diff --git a/.azure-pipelines/azure-pipelines-build.yml b/.azure-pipelines/azure-pipelines-build.yml index 67cfeaca95f4..df51700c4f20 100644 --- a/.azure-pipelines/azure-pipelines-build.yml +++ b/.azure-pipelines/azure-pipelines-build.yml @@ -130,6 +130,10 @@ jobs: make $BUILD_OPTIONS ENABLE_ASAN=y target/docker-sonic-vs.gz mv target/docker-sonic-vs.gz target/docker-sonic-vs-asan.gz fi + if [ $(K8S_OPTIONS) == 'INCLUDE_KUBERNETES_MASTER=y' ]; then + make $BUILD_OPTIONS $(K8S_OPTIONS) target/sonic-vs.img.gz + mv target/sonic-vs.img.gz target/sonic-vs-k8s.img.gz + fi make $BUILD_OPTIONS target/docker-sonic-vs.gz target/sonic-vs.img.gz target/docker-ptf.gz make $BUILD_OPTIONS target/docker-ptf-sai.gz if [ $(Build.Reason) != 'PullRequest' ];then diff --git a/.azure-pipelines/template-skipvstest.yml b/.azure-pipelines/template-skipvstest.yml index b47f17ce6e81..ca968d009c94 100644 --- a/.azure-pipelines/template-skipvstest.yml +++ b/.azure-pipelines/template-skipvstest.yml @@ -2,7 +2,13 @@ steps: - ${{ if eq(variables['Build.Reason'], 'PullRequest') }}: - script: | set -ex - tar_branch=origin/$(System.PullRequest.TargetBranch) + tar_branch=origin/$(System.PullRequest.TargetBranchName) + # Check if k8s master entrance script is changed + if ! git diff $tar_branch..HEAD --name-only | grep -F files/image_config/kubernetes/kubernetes_master_entrance.sh; then + echo "##vso[task.setvariable variable=K8S_OPTIONS;]INCLUDE_KUBERNETES_MASTER=n" + else + echo "##vso[task.setvariable variable=K8S_OPTIONS;]INCLUDE_KUBERNETES_MASTER=y" + fi git diff $tar_branch..HEAD --name-only | grep -v -f .azure-pipelines/vstest-exclude && exit 0 git diff $tar_branch..HEAD --name-only | grep -f .azure-pipelines/vstest-include && exit 0 set +x diff --git a/.gitmodules b/.gitmodules index a3074763797a..f4f0d43c0f43 100644 --- a/.gitmodules +++ b/.gitmodules @@ -46,7 +46,7 @@ [submodule "src/sonic-frr/frr"] path = src/sonic-frr/frr url = https://github.com/sonic-net/sonic-frr.git - branch = frr/8.2 + branch = frr/8.5 [submodule "platform/p4/p4-hlir/p4-hlir-v1.1"] path = platform/p4/p4-hlir/p4-hlir-v1.1 url = https://github.com/p4lang/p4-hlir.git @@ -65,9 +65,6 @@ [submodule "src/scapy"] path = src/scapy url = https://github.com/secdev/scapy.git -[submodule "platform/mellanox/mlnx-sai/SAI-Implementation"] - path = platform/mellanox/mlnx-sai/SAI-Implementation - url = https://github.com/Mellanox/SAI-Implementation [submodule "src/sonic-mgmt-framework"] path = src/sonic-mgmt-framework url = https://github.com/sonic-net/sonic-mgmt-framework diff --git a/LICENSE b/LICENSE index d15bca6acb81..d45c7ebd6840 100644 --- a/LICENSE +++ b/LICENSE @@ -1,15 +1,13 @@ -Copyright (C) 2016 Microsoft +Copyright (C) 2023 Microsoft -This program is free software; you can redistribute it and/or -modify it under the terms of the GNU General Public License -as published by the Free Software Foundation; either version 2 -of the License, or (at your option) any later version. +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + http://www.apache.org/licenses/LICENSE-2.0 -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. diff --git a/azure-pipelines.yml b/azure-pipelines.yml index e7d8c3f3b011..88b0cd01cb3e 100644 --- a/azure-pipelines.yml +++ b/azure-pipelines.yml @@ -28,6 +28,7 @@ resources: - repository: sonic-mgmt type: github name: sonic-net/sonic-mgmt + ref: master endpoint: sonic-net - repository: buildimage type: github @@ -55,8 +56,6 @@ stages: - stage: Build pool: sonicbld - variables: - INSTALL_DEBUG_TOOLS: y dependsOn: [] jobs: - template: .azure-pipelines/azure-pipelines-build.yml @@ -67,6 +66,10 @@ stages: variables: swi_image: yes - name: mellanox + variables: + dbg_image: yes + docker_syncd_rpc_image: yes + platform_rpc: mlnx - name: marvell-arm64 pool: sonicbld-arm64 variables: @@ -152,12 +155,12 @@ stages: timeoutInMinutes: 240 continueOnError: false steps: - - template: .azure-pipelines/run-test-scheduler-template.yml + - template: .azure-pipelines/run-test-elastictest-template.yml@sonic-mgmt parameters: TOPOLOGY: t0 MIN_WORKER: $(T0_INSTANCE_NUM) MAX_WORKER: $(T0_INSTANCE_NUM) - MGMT_BRANCH: master + MGMT_BRANCH: "master" - job: t0_2vlans_elastictest pool: ubuntu-20.04 @@ -165,13 +168,13 @@ stages: timeoutInMinutes: 240 continueOnError: false steps: - - template: .azure-pipelines/run-test-scheduler-template.yml + - template: .azure-pipelines/run-test-elastictest-template.yml@sonic-mgmt parameters: TOPOLOGY: t0 TEST_SET: t0-2vlans MIN_WORKER: $(T0_2VLANS_INSTANCE_NUM) MAX_WORKER: $(T0_2VLANS_INSTANCE_NUM) - MGMT_BRANCH: master + MGMT_BRANCH: "master" DEPLOY_MG_EXTRA_PARAMS: "-e vlan_config=two_vlan_a" - job: t1_lag_elastictest @@ -180,12 +183,12 @@ stages: timeoutInMinutes: 240 continueOnError: false steps: - - template: .azure-pipelines/run-test-scheduler-template.yml + - template: .azure-pipelines/run-test-elastictest-template.yml@sonic-mgmt parameters: TOPOLOGY: t1-lag MIN_WORKER: $(T1_LAG_INSTANCE_NUM) MAX_WORKER: $(T1_LAG_INSTANCE_NUM) - MGMT_BRANCH: master + MGMT_BRANCH: "master" - job: multi_asic_elastictest displayName: "kvmtest-multi-asic-t1-lag by Elastictest" @@ -193,14 +196,14 @@ stages: timeoutInMinutes: 240 continueOnError: false steps: - - template: .azure-pipelines/run-test-scheduler-template.yml + - template: .azure-pipelines/run-test-elastictest-template.yml@sonic-mgmt parameters: TOPOLOGY: t1-8-lag TEST_SET: multi-asic-t1-lag MIN_WORKER: $(MULTI_ASIC_INSTANCE_NUM) MAX_WORKER: $(MULTI_ASIC_INSTANCE_NUM) NUM_ASIC: 4 - MGMT_BRANCH: master + MGMT_BRANCH: "master" - job: dualtor_elastictest pool: ubuntu-20.04 @@ -208,12 +211,12 @@ stages: timeoutInMinutes: 240 continueOnError: false steps: - - template: .azure-pipelines/run-test-scheduler-template.yml + - template: .azure-pipelines/run-test-elastictest-template.yml@sonic-mgmt parameters: TOPOLOGY: dualtor MIN_WORKER: $(T0_DUALTOR_INSTANCE_NUM) MAX_WORKER: $(T0_DUALTOR_INSTANCE_NUM) - MGMT_BRANCH: master + MGMT_BRANCH: "master" COMMON_EXTRA_PARAMS: "--disable_loganalyzer " - job: sonic_t0_elastictest @@ -222,13 +225,13 @@ stages: timeoutInMinutes: 240 continueOnError: false steps: - - template: .azure-pipelines/run-test-scheduler-template.yml + - template: .azure-pipelines/run-test-elastictest-template.yml@sonic-mgmt parameters: TOPOLOGY: t0-64-32 MIN_WORKER: $(T0_SONIC_INSTANCE_NUM) MAX_WORKER: $(T0_SONIC_INSTANCE_NUM) TEST_SET: t0-sonic - MGMT_BRANCH: master + MGMT_BRANCH: "master" COMMON_EXTRA_PARAMS: "--neighbor_type=sonic " VM_TYPE: vsonic diff --git a/build_debian.sh b/build_debian.sh index b6555da92480..195ec7017d5c 100755 --- a/build_debian.sh +++ b/build_debian.sh @@ -303,17 +303,8 @@ then echo '[INFO] Install kubernetes master' install_kubernetes ${MASTER_KUBERNETES_VERSION} - sudo https_proxy=$https_proxy LANG=C chroot $FILESYSTEM_ROOT curl -fsSL \ - https://packages.microsoft.com/keys/microsoft.asc | \ - sudo LANG=C chroot $FILESYSTEM_ROOT apt-key add - - sudo https_proxy=$https_proxy LANG=C chroot $FILESYSTEM_ROOT curl -fsSL \ - https://packages.microsoft.com/keys/msopentech.asc | \ - sudo LANG=C chroot $FILESYSTEM_ROOT apt-key add - - echo "deb [arch=amd64] https://packages.microsoft.com/repos/azurecore-debian $IMAGE_DISTRO main" | \ - sudo tee $FILESYSTEM_ROOT/etc/apt/sources.list.d/azure.list sudo LANG=C chroot $FILESYSTEM_ROOT apt-get update sudo LANG=C chroot $FILESYSTEM_ROOT apt-get -y install hyperv-daemons gnupg xmlstarlet - sudo LANG=C chroot $FILESYSTEM_ROOT apt-get -y install metricsext2 sudo LANG=C chroot $FILESYSTEM_ROOT apt-get -y remove gnupg sudo https_proxy=$https_proxy LANG=C chroot $FILESYSTEM_ROOT curl -o /tmp/cri-dockerd.deb -fsSL \ https://github.com/Mirantis/cri-dockerd/releases/download/v${MASTER_CRI_DOCKERD}/cri-dockerd_${MASTER_CRI_DOCKERD}.3-0.debian-${IMAGE_DISTRO}_amd64.deb @@ -554,6 +545,9 @@ sudo https_proxy=$https_proxy LANG=C chroot $FILESYSTEM_ROOT pip3 install 'docke # Install scapy sudo https_proxy=$https_proxy LANG=C chroot $FILESYSTEM_ROOT pip3 install 'scapy==2.4.4' +# The option --no-build-isolation can be removed when upgrading PyYAML to 6.0.1 +sudo https_proxy=$https_proxy LANG=C chroot $FILESYSTEM_ROOT pip3 install 'PyYAML==5.4.1' --no-build-isolation + ## Note: keep pip installed for maintainance purpose # Install GCC, needed for building/installing some Python packages @@ -658,6 +652,10 @@ then fi +## Set FIPS runtime default option +sudo LANG=C chroot $FILESYSTEM_ROOT /bin/bash -c "mkdir -p /etc/fips" +sudo LANG=C chroot $FILESYSTEM_ROOT /bin/bash -c "echo 0 > /etc/fips/fips_enable" + # ################# # secure boot # ################# @@ -794,6 +792,9 @@ sudo cp files/image_config/resolv-config/resolv.conf.head $FILESYSTEM_ROOT/etc/r sudo mksquashfs $FILESYSTEM_ROOT $FILESYSTEM_SQUASHFS -comp zstd -b 1M -e boot -e var/lib/docker -e $PLATFORM_DIR +## Reduce /boot permission +sudo chmod -R go-wx $FILESYSTEM_ROOT/boot + # Ensure admin gid is 1000 gid_user=$(sudo LANG=C chroot $FILESYSTEM_ROOT id -g $USERNAME) || gid_user="none" if [ "${gid_user}" != "1000" ]; then diff --git a/device/arista/x86_64-arista_7060dx4_32/Arista-7060DX4-C32/th3-a7060dx4-c32-32x400G.config.bcm b/device/arista/x86_64-arista_7060dx4_32/Arista-7060DX4-C32/th3-a7060dx4-c32-32x400G.config.bcm index 7bd96fed83b8..48f8a3643731 100644 --- a/device/arista/x86_64-arista_7060dx4_32/Arista-7060DX4-C32/th3-a7060dx4-c32-32x400G.config.bcm +++ b/device/arista/x86_64-arista_7060dx4_32/Arista-7060DX4-C32/th3-a7060dx4-c32-32x400G.config.bcm @@ -16,6 +16,8 @@ miim_intr_enable.0=0 module_64ports.0=1 multicast_l2_range.0=511 oversubscribe_mode=1 +sai_tunnel_global_sip_mask_enable=1 +bcm_tunnel_term_compatible_mode=1 parity_correction=1 parity_enable=1 pbmp_xport_xe.0=0x3ffffffffffffffffffffffffffffffffffffffe diff --git a/device/arista/x86_64-arista_7060dx4_32/th3-a7060dx4-32-flex.config.bcm b/device/arista/x86_64-arista_7060dx4_32/th3-a7060dx4-32-flex.config.bcm index 2eae80ff1180..dc75f1acafad 100644 --- a/device/arista/x86_64-arista_7060dx4_32/th3-a7060dx4-32-flex.config.bcm +++ b/device/arista/x86_64-arista_7060dx4_32/th3-a7060dx4-32-flex.config.bcm @@ -16,6 +16,8 @@ miim_intr_enable.0=0 module_64ports.0=1 multicast_l2_range.0=511 oversubscribe_mode=1 +sai_tunnel_global_sip_mask_enable=1 +bcm_tunnel_term_compatible_mode=1 parity_correction=1 parity_enable=1 pbmp_xport_xe.0=0x3ffffffffffffffffffffffffffffffffffffffe diff --git a/device/arista/x86_64-arista_7060dx5_32/Arista-7060DX5-32/BALANCED b/device/arista/x86_64-arista_7060dx5_32/Arista-7060DX5-32/BALANCED new file mode 120000 index 000000000000..2c9506a909fb --- /dev/null +++ b/device/arista/x86_64-arista_7060dx5_32/Arista-7060DX5-32/BALANCED @@ -0,0 +1 @@ +../../../common/profiles/th4/gen/BALANCED \ No newline at end of file diff --git a/device/arista/x86_64-arista_7060dx5_32/Arista-7060DX5-32/buffers.json.j2 b/device/arista/x86_64-arista_7060dx5_32/Arista-7060DX5-32/buffers.json.j2 new file mode 100644 index 000000000000..0b1cb2c541b6 --- /dev/null +++ b/device/arista/x86_64-arista_7060dx5_32/Arista-7060DX5-32/buffers.json.j2 @@ -0,0 +1,2 @@ +{%- set default_topo = 't1' %} +{%- include 'buffers_config.j2' %} diff --git a/device/arista/x86_64-arista_7060dx5_32/Arista-7060DX5-32/buffers_defaults_t0.j2 b/device/arista/x86_64-arista_7060dx5_32/Arista-7060DX5-32/buffers_defaults_t0.j2 new file mode 120000 index 000000000000..9524e6a476ac --- /dev/null +++ b/device/arista/x86_64-arista_7060dx5_32/Arista-7060DX5-32/buffers_defaults_t0.j2 @@ -0,0 +1 @@ +BALANCED/buffers_defaults_t0.j2 \ No newline at end of file diff --git a/device/arista/x86_64-arista_7060dx5_32/Arista-7060DX5-32/buffers_defaults_t1.j2 b/device/arista/x86_64-arista_7060dx5_32/Arista-7060DX5-32/buffers_defaults_t1.j2 new file mode 120000 index 000000000000..c25cc95d6d57 --- /dev/null +++ b/device/arista/x86_64-arista_7060dx5_32/Arista-7060DX5-32/buffers_defaults_t1.j2 @@ -0,0 +1 @@ +BALANCED/buffers_defaults_t1.j2 \ No newline at end of file diff --git a/device/arista/x86_64-arista_7060dx5_32/Arista-7060DX5-32/hwsku.json b/device/arista/x86_64-arista_7060dx5_32/Arista-7060DX5-32/hwsku.json new file mode 100644 index 000000000000..46936732aa5e --- /dev/null +++ b/device/arista/x86_64-arista_7060dx5_32/Arista-7060DX5-32/hwsku.json @@ -0,0 +1,104 @@ +{ + "interfaces": { + "Ethernet0": { + "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G]" + }, + "Ethernet8": { + "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G]" + }, + "Ethernet16": { + "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G]" + }, + "Ethernet24": { + "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G]" + }, + "Ethernet32": { + "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G]" + }, + "Ethernet40": { + "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G]" + }, + "Ethernet48": { + "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G]" + }, + "Ethernet56": { + "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G]" + }, + "Ethernet64": { + "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G]" + }, + "Ethernet72": { + "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G]" + }, + "Ethernet80": { + "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G]" + }, + "Ethernet88": { + "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G]" + }, + "Ethernet96": { + "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G]" + }, + "Ethernet104": { + "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G]" + }, + "Ethernet112": { + "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G]" + }, + "Ethernet120": { + "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G]" + }, + "Ethernet128": { + "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G]" + }, + "Ethernet136": { + "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G]" + }, + "Ethernet144": { + "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G]" + }, + "Ethernet152": { + "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G]" + }, + "Ethernet160": { + "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G]" + }, + "Ethernet168": { + "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G]" + }, + "Ethernet176": { + "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G]" + }, + "Ethernet184": { + "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G]" + }, + "Ethernet192": { + "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G]" + }, + "Ethernet200": { + "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G]" + }, + "Ethernet208": { + "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G]" + }, + "Ethernet216": { + "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G]" + }, + "Ethernet224": { + "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G]" + }, + "Ethernet232": { + "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G]" + }, + "Ethernet240": { + "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G]" + }, + "Ethernet248": { + "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G]" + }, + "Ethernet256": { + "default_brkout_mode": "1x10G", + "fec": "none" + } + } +} diff --git a/device/arista/x86_64-arista_7060dx5_32/Arista-7060DX5-32/pg_profile_lookup.ini b/device/arista/x86_64-arista_7060dx5_32/Arista-7060DX5-32/pg_profile_lookup.ini new file mode 120000 index 000000000000..297cddb2d223 --- /dev/null +++ b/device/arista/x86_64-arista_7060dx5_32/Arista-7060DX5-32/pg_profile_lookup.ini @@ -0,0 +1 @@ +BALANCED/pg_profile_lookup.ini \ No newline at end of file diff --git a/device/arista/x86_64-arista_7060dx5_32/Arista-7060DX5-32/port_config.ini b/device/arista/x86_64-arista_7060dx5_32/Arista-7060DX5-32/port_config.ini new file mode 100644 index 000000000000..9e4a4a6e91c5 --- /dev/null +++ b/device/arista/x86_64-arista_7060dx5_32/Arista-7060DX5-32/port_config.ini @@ -0,0 +1,34 @@ +# name lanes alias index speed fec +Ethernet0 1,2,3,4,5,6,7,8 Ethernet1/1 1 400000 rs +Ethernet8 9,10,11,12,13,14,15,16 Ethernet2/1 2 400000 rs +Ethernet16 17,18,19,20,21,22,23,24 Ethernet3/1 3 400000 rs +Ethernet24 25,26,27,28,29,30,31,32 Ethernet4/1 4 400000 rs +Ethernet32 33,34,35,36,37,38,39,40 Ethernet5/1 5 400000 rs +Ethernet40 41,42,43,44,45,46,47,48 Ethernet6/1 6 400000 rs +Ethernet48 49,50,51,52,53,54,55,56 Ethernet7/1 7 400000 rs +Ethernet56 57,58,59,60,61,62,63,64 Ethernet8/1 8 400000 rs +Ethernet64 65,66,67,68,69,70,71,72 Ethernet9/1 9 400000 rs +Ethernet72 73,74,75,76,77,78,79,80 Ethernet10/1 10 400000 rs +Ethernet80 81,82,83,84,85,86,87,88 Ethernet11/1 11 400000 rs +Ethernet88 89,90,91,92,93,94,95,96 Ethernet12/1 12 400000 rs +Ethernet96 97,98,99,100,101,102,103,104 Ethernet13/1 13 400000 rs +Ethernet104 105,106,107,108,109,110,111,112 Ethernet14/1 14 400000 rs +Ethernet112 113,114,115,116,117,118,119,120 Ethernet15/1 15 400000 rs +Ethernet120 121,122,123,124,125,126,127,128 Ethernet16/1 16 400000 rs +Ethernet128 385,386,387,388,389,390,391,392 Ethernet17/1 17 400000 rs +Ethernet136 393,394,395,396,397,398,399,400 Ethernet18/1 18 400000 rs +Ethernet144 401,402,403,404,405,406,407,408 Ethernet19/1 19 400000 rs +Ethernet152 409,410,411,412,413,414,415,416 Ethernet20/1 20 400000 rs +Ethernet160 417,418,419,420,421,422,423,424 Ethernet21/1 21 400000 rs +Ethernet168 425,426,427,428,429,430,431,432 Ethernet22/1 22 400000 rs +Ethernet176 433,434,435,436,437,438,439,440 Ethernet23/1 23 400000 rs +Ethernet184 441,442,443,444,445,446,447,448 Ethernet24/1 24 400000 rs +Ethernet192 449,450,451,452,453,454,455,456 Ethernet25/1 25 400000 rs +Ethernet200 457,458,459,460,461,462,463,464 Ethernet26/1 26 400000 rs +Ethernet208 465,466,467,468,469,470,471,472 Ethernet27/1 27 400000 rs +Ethernet216 473,474,475,476,477,478,479,480 Ethernet28/1 28 400000 rs +Ethernet224 481,482,483,484,485,486,487,488 Ethernet29/1 29 400000 rs +Ethernet232 489,490,491,492,493,494,495,496 Ethernet30/1 30 400000 rs +Ethernet240 497,498,499,500,501,502,503,504 Ethernet31/1 31 400000 rs +Ethernet248 505,506,507,508,509,510,511,512 Ethernet32/1 32 400000 rs +Ethernet256 513 Ethernet33 33 10000 none diff --git a/device/arista/x86_64-arista_7060dx5_32/Arista-7060DX5-32/qos.json.j2 b/device/arista/x86_64-arista_7060dx5_32/Arista-7060DX5-32/qos.json.j2 new file mode 100644 index 000000000000..3e548325ea30 --- /dev/null +++ b/device/arista/x86_64-arista_7060dx5_32/Arista-7060DX5-32/qos.json.j2 @@ -0,0 +1 @@ +{%- include 'qos_config.j2' %} diff --git a/device/arista/x86_64-arista_7060dx5_32/Arista-7060DX5-32/sai.profile b/device/arista/x86_64-arista_7060dx5_32/Arista-7060DX5-32/sai.profile new file mode 100644 index 000000000000..ee4438ef3910 --- /dev/null +++ b/device/arista/x86_64-arista_7060dx5_32/Arista-7060DX5-32/sai.profile @@ -0,0 +1 @@ +SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/th4-a7060dx5-32.config.bcm diff --git a/device/arista/x86_64-arista_7060dx5_32/Arista-7060DX5-32/th4-a7060dx5-32.config.bcm b/device/arista/x86_64-arista_7060dx5_32/Arista-7060DX5-32/th4-a7060dx5-32.config.bcm new file mode 100644 index 000000000000..f61168ea5d94 --- /dev/null +++ b/device/arista/x86_64-arista_7060dx5_32/Arista-7060DX5-32/th4-a7060dx5-32.config.bcm @@ -0,0 +1,1643 @@ +# $Copyright: Broadcom Ltd.$ +# +# BCM56990 64x400g port configuration. +# +# configuration yaml file +# device: +# : +# : +# ? +# : +# : +# ... +# : +# : +# : +# : +# ... +# : +# + +--- +bcm_device: + 0: + global: + pktio_mode: 1 + vlan_flooding_l2mc_num_reserved: 0 + ipv6_lpm_128b_enable: 1 + shared_block_mask_section: uc_bc + skip_protocol_default_entries: 1 + # LTSW uses value 1 for ALPM combined mode + l3_alpm_template: 1 + l3_alpm_hit_skip: 1 + sai_feat_tail_timestamp : 1 + sai_field_group_auto_prioritize: 1 + #l3_intf_vlan_split_egress for MTU at L3IF + l3_intf_vlan_split_egress : 1 + + # vxlan + l3_alpm_template: 1 + riot_overlay_l3_egress_mem_size: 16384 + riot_overlay_l3_intf_mem_size: 4096 + l3_ecmp_member_first_lkup_mem_size: 12288 + bcm_tunnel_term_compatible_mode: 1 + shared_l2_tunnel: 1 + sai_tunnel_support: 10 + sai_tunnel_underlay_route_mode: 2 + sai_tunnel_ecmp_sharing_mode: 0 # change to 2 if SAI_NEXT_HOP_GROUP_ATTR_LEVEL_1 used + + # bfd + bfd_enable: 1 + bfd_sha1_keys: 5 + bfd_num_sessions: 2048 + bfd_simple_password_keys: 5 + num_queues_pci: 47 + num_queues_uc0: 1 + bfd_feature_enable: 1 + bfd_use_endpoint_id_as_discriminator: 1 + bfd_tx_raw_ingress_enable: 1 + sai_eapp_config_file: "/usr/share/sonic/device/x86_64-broadcom_common/eapps/eapp_config.json" +--- +device: + 0: + PC_SERDES_CONFIG: + PKG_SWAP_BYPASS: 1 + + PC_PM_CORE: + ? + PC_PM_ID: 1 + CORE_INDEX: 0 + : + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP_AUTO: 0 + RX_LANE_MAP: 0x67235401 + TX_LANE_MAP: 0x2731465 + RX_POLARITY_FLIP: 0x00 + TX_POLARITY_FLIP: 0x00 + ? + PC_PM_ID: 2 + CORE_INDEX: 0 + : + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP_AUTO: 0 + RX_LANE_MAP: 0x31752064 + TX_LANE_MAP: 0x76025314 + RX_POLARITY_FLIP: 0xff + TX_POLARITY_FLIP: 0xff + ? + PC_PM_ID: 3 + CORE_INDEX: 0 + : + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP_AUTO: 0 + RX_LANE_MAP: 0x67241503 + TX_LANE_MAP: 0x13650274 + RX_POLARITY_FLIP: 0x00 + TX_POLARITY_FLIP: 0x01 + ? + PC_PM_ID: 4 + CORE_INDEX: 0 + : + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP_AUTO: 0 + RX_LANE_MAP: 0x46025713 + TX_LANE_MAP: 0x31650274 + RX_POLARITY_FLIP: 0x00 + TX_POLARITY_FLIP: 0x00 + ? + PC_PM_ID: 5 + CORE_INDEX: 0 + : + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP_AUTO: 0 + RX_LANE_MAP: 0x62713054 + TX_LANE_MAP: 0x21703465 + RX_POLARITY_FLIP: 0x00 + TX_POLARITY_FLIP: 0xd8 + ? + PC_PM_ID: 6 + CORE_INDEX: 0 + : + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP_AUTO: 0 + RX_LANE_MAP: 0x13460257 + TX_LANE_MAP: 0x64137502 + RX_POLARITY_FLIP: 0xff + TX_POLARITY_FLIP: 0xff + ? + PC_PM_ID: 7 + CORE_INDEX: 0 + : + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP_AUTO: 0 + RX_LANE_MAP: 0x43512670 + TX_LANE_MAP: 0x2571364 + RX_POLARITY_FLIP: 0x00 + TX_POLARITY_FLIP: 0x00 + ? + PC_PM_ID: 8 + CORE_INDEX: 0 + : + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP_AUTO: 0 + RX_LANE_MAP: 0x14270356 + TX_LANE_MAP: 0x64237501 + RX_POLARITY_FLIP: 0xfb + TX_POLARITY_FLIP: 0xff + ? + PC_PM_ID: 9 + CORE_INDEX: 0 + : + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP_AUTO: 0 + RX_LANE_MAP: 0x76140235 + TX_LANE_MAP: 0x74036521 + RX_POLARITY_FLIP: 0xc1 + TX_POLARITY_FLIP: 0x00 + ? + PC_PM_ID: 10 + CORE_INDEX: 0 + : + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP_AUTO: 0 + RX_LANE_MAP: 0x47125603 + TX_LANE_MAP: 0x30451276 + RX_POLARITY_FLIP: 0xff + TX_POLARITY_FLIP: 0xff + ? + PC_PM_ID: 11 + CORE_INDEX: 0 + : + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP_AUTO: 0 + RX_LANE_MAP: 0x76041235 + TX_LANE_MAP: 0x74036512 + RX_POLARITY_FLIP: 0x40 + TX_POLARITY_FLIP: 0x00 + ? + PC_PM_ID: 12 + CORE_INDEX: 0 + : + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP_AUTO: 0 + RX_LANE_MAP: 0x27145603 + TX_LANE_MAP: 0x21450376 + RX_POLARITY_FLIP: 0xff + TX_POLARITY_FLIP: 0xff + ? + PC_PM_ID: 13 + CORE_INDEX: 0 + : + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP_AUTO: 0 + RX_LANE_MAP: 0x2735146 + TX_LANE_MAP: 0x3657421 + RX_POLARITY_FLIP: 0x00 + TX_POLARITY_FLIP: 0xc8 + ? + PC_PM_ID: 14 + CORE_INDEX: 0 + : + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP_AUTO: 0 + RX_LANE_MAP: 0x47306521 + TX_LANE_MAP: 0x12643075 + RX_POLARITY_FLIP: 0xff + TX_POLARITY_FLIP: 0x33 + ? + PC_PM_ID: 15 + CORE_INDEX: 0 + : + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP_AUTO: 0 + RX_LANE_MAP: 0x20157436 + TX_LANE_MAP: 0x56237104 + RX_POLARITY_FLIP: 0x08 + TX_POLARITY_FLIP: 0x00 + ? + PC_PM_ID: 16 + CORE_INDEX: 0 + : + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP_AUTO: 0 + RX_LANE_MAP: 0x14270356 + TX_LANE_MAP: 0x76325014 + RX_POLARITY_FLIP: 0xff + TX_POLARITY_FLIP: 0xff + ? + PC_PM_ID: 49 + CORE_INDEX: 0 + : + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP_AUTO: 0 + RX_LANE_MAP: 0x56704312 + TX_LANE_MAP: 0x32641570 + RX_POLARITY_FLIP: 0xff + TX_POLARITY_FLIP: 0xff + ? + PC_PM_ID: 50 + CORE_INDEX: 0 + : + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP_AUTO: 0 + RX_LANE_MAP: 0x21564073 + TX_LANE_MAP: 0x50314762 + RX_POLARITY_FLIP: 0x00 + TX_POLARITY_FLIP: 0x00 + ? + PC_PM_ID: 51 + CORE_INDEX: 0 + : + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP_AUTO: 0 + RX_LANE_MAP: 0x36715402 + TX_LANE_MAP: 0x32641075 + RX_POLARITY_FLIP: 0xff + TX_POLARITY_FLIP: 0xff + ? + PC_PM_ID: 52 + CORE_INDEX: 0 + : + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP_AUTO: 0 + RX_LANE_MAP: 0x51462073 + TX_LANE_MAP: 0x5127634 + RX_POLARITY_FLIP: 0x69 + TX_POLARITY_FLIP: 0x08 + ? + PC_PM_ID: 53 + CORE_INDEX: 0 + : + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP_AUTO: 0 + RX_LANE_MAP: 0x73204651 + TX_LANE_MAP: 0x32640175 + RX_POLARITY_FLIP: 0x69 + TX_POLARITY_FLIP: 0xff + ? + PC_PM_ID: 54 + CORE_INDEX: 0 + : + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP_AUTO: 0 + RX_LANE_MAP: 0x5134627 + TX_LANE_MAP: 0x60137254 + RX_POLARITY_FLIP: 0x00 + TX_POLARITY_FLIP: 0x00 + ? + PC_PM_ID: 55 + CORE_INDEX: 0 + : + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP_AUTO: 0 + RX_LANE_MAP: 0x57420163 + TX_LANE_MAP: 0x32651074 + RX_POLARITY_FLIP: 0xff + TX_POLARITY_FLIP: 0xff + ? + PC_PM_ID: 56 + CORE_INDEX: 0 + : + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP_AUTO: 0 + RX_LANE_MAP: 0x5134627 + TX_LANE_MAP: 0x10524376 + RX_POLARITY_FLIP: 0x05 + TX_POLARITY_FLIP: 0x00 + ? + PC_PM_ID: 57 + CORE_INDEX: 0 + : + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP_AUTO: 0 + RX_LANE_MAP: 0x73520146 + TX_LANE_MAP: 0x31650274 + RX_POLARITY_FLIP: 0x3d + TX_POLARITY_FLIP: 0xff + ? + PC_PM_ID: 58 + CORE_INDEX: 0 + : + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP_AUTO: 0 + RX_LANE_MAP: 0x16072354 + TX_LANE_MAP: 0x51634270 + RX_POLARITY_FLIP: 0x01 + TX_POLARITY_FLIP: 0x00 + ? + PC_PM_ID: 59 + CORE_INDEX: 0 + : + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP_AUTO: 0 + RX_LANE_MAP: 0x72530164 + TX_LANE_MAP: 0x32506147 + RX_POLARITY_FLIP: 0xff + TX_POLARITY_FLIP: 0xff + ? + PC_PM_ID: 60 + CORE_INDEX: 0 + : + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP_AUTO: 0 + RX_LANE_MAP: 0x4371256 + TX_LANE_MAP: 0x21673054 + RX_POLARITY_FLIP: 0x00 + TX_POLARITY_FLIP: 0xcc + ? + PC_PM_ID: 61 + CORE_INDEX: 0 + : + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP_AUTO: 0 + RX_LANE_MAP: 0x67241503 + TX_LANE_MAP: 0x12730465 + RX_POLARITY_FLIP: 0x20 + TX_POLARITY_FLIP: 0x00 + ? + PC_PM_ID: 62 + CORE_INDEX: 0 + : + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP_AUTO: 0 + RX_LANE_MAP: 0x73625140 + TX_LANE_MAP: 0x12640573 + RX_POLARITY_FLIP: 0x00 + TX_POLARITY_FLIP: 0x00 + ? + PC_PM_ID: 63 + CORE_INDEX: 0 + : + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP_AUTO: 0 + RX_LANE_MAP: 0x23674015 + TX_LANE_MAP: 0x57206143 + RX_POLARITY_FLIP: 0xff + TX_POLARITY_FLIP: 0xff + ? + PC_PM_ID: 64 + CORE_INDEX: 0 + : + RX_LANE_MAP_AUTO: 0 + TX_LANE_MAP_AUTO: 0 + RX_POLARITY_FLIP_AUTO: 0 + TX_POLARITY_FLIP_AUTO: 0 + RX_LANE_MAP: 0x57314260 + TX_LANE_MAP: 0x1735264 + RX_POLARITY_FLIP: 0x10 + TX_POLARITY_FLIP: 0x00 +... +--- +device: + 0: + PC_PORT_PHYS_MAP: + ? + # CPU port + PORT_ID: 0 + : + PC_PHYS_PORT_ID: 0 + ? + PORT_ID: 1 + : + PC_PHYS_PORT_ID: 1 + ? + PORT_ID: 2 + : + PC_PHYS_PORT_ID: 5 + ? + PORT_ID: 3 + : + PC_PHYS_PORT_ID: 9 + ? + PORT_ID: 4 + : + PC_PHYS_PORT_ID: 13 + ? + PORT_ID: 17 + : + PC_PHYS_PORT_ID: 17 + ? + PORT_ID: 18 + : + PC_PHYS_PORT_ID: 21 + ? + PORT_ID: 19 + : + PC_PHYS_PORT_ID: 25 + ? + PORT_ID: 20 + : + PC_PHYS_PORT_ID: 29 + ? + PORT_ID: 34 + : + PC_PHYS_PORT_ID: 33 + ? + PORT_ID: 35 + : + PC_PHYS_PORT_ID: 37 + ? + PORT_ID: 36 + : + PC_PHYS_PORT_ID: 41 + ? + PORT_ID: 37 + : + PC_PHYS_PORT_ID: 45 + ? + PORT_ID: 51 + : + PC_PHYS_PORT_ID: 49 + ? + PORT_ID: 52 + : + PC_PHYS_PORT_ID: 53 + ? + PORT_ID: 53 + : + PC_PHYS_PORT_ID: 57 + ? + PORT_ID: 54 + : + PC_PHYS_PORT_ID: 61 + ? + PORT_ID: 204 + : + PC_PHYS_PORT_ID: 193 + ? + PORT_ID: 205 + : + PC_PHYS_PORT_ID: 197 + ? + PORT_ID: 206 + : + PC_PHYS_PORT_ID: 201 + ? + PORT_ID: 207 + : + PC_PHYS_PORT_ID: 205 + ? + PORT_ID: 221 + : + PC_PHYS_PORT_ID: 209 + ? + PORT_ID: 222 + : + PC_PHYS_PORT_ID: 213 + ? + PORT_ID: 223 + : + PC_PHYS_PORT_ID: 217 + ? + PORT_ID: 224 + : + PC_PHYS_PORT_ID: 221 + ? + PORT_ID: 238 + : + PC_PHYS_PORT_ID: 225 + ? + PORT_ID: 239 + : + PC_PHYS_PORT_ID: 229 + ? + PORT_ID: 240 + : + PC_PHYS_PORT_ID: 233 + ? + PORT_ID: 241 + : + PC_PHYS_PORT_ID: 237 + ? + PORT_ID: 255 + : + PC_PHYS_PORT_ID: 241 + ? + PORT_ID: 256 + : + PC_PHYS_PORT_ID: 245 + ? + PORT_ID: 257 + : + PC_PHYS_PORT_ID: 249 + ? + PORT_ID: 258 + : + PC_PHYS_PORT_ID: 253 + ? + PORT_ID: 50 + : + PC_PHYS_PORT_ID: 258 +... +--- +device: + 0: + PC_PORT: + ? + PORT_ID: 0 + : + &port_mode_10g + ENABLE: 1 + SPEED: 10000 + NUM_LANES: 1 + ? + PORT_ID: [[50, 50]] + : + ENABLE: 0 + MAX_FRAME_SIZE: 9416 + SPEED: 10000 + NUM_LANES: 1 + ? + PORT_ID: [[1, 4], + [17, 20], + [34, 37], + [51, 54], + [204, 207], + [221, 224], + [238, 241], + [255, 258]] + : + ENABLE: 0 + SPEED: 400000 + NUM_LANES: 8 + FEC_MODE: PC_FEC_RS544_2XN + MAX_FRAME_SIZE: 9416 +... +--- +device: + 0: + # Per pipe flex counter configuration + CTR_EFLEX_CONFIG: + CTR_ING_EFLEX_OPERMODE_PIPEUNIQUE: 0 + CTR_EGR_EFLEX_OPERMODE_PIPEUNIQUE: 0 + + # Per pipe flex state configuration + #FLEX_STATE_CONFIG: + # FLEX_STATE_ING_OPERMODE_PIPEUNIQUE: 0 + # FLEX_STATE_EGR_OPERMODE_PIPEUNIQUE: 1 + + # Lossy vs Lossless mode + TM_THD_CONFIG: + THRESHOLD_MODE: LOSSLESS + + # IFP mode + FP_CONFIG: + FP_ING_OPERMODE: GLOBAL_PIPE_AWARE +... +--- +device: + 0: + TM_THD_CONFIG: + SKIP_BUFFER_RESERVATION: 1 + THRESHOLD_MODE: LOSSY_AND_LOSSLESS + + TM_SCHEDULER_CONFIG: + NUM_MC_Q: NUM_MC_Q_2 +... +--- +device: + 0: + TM_ING_THD_PORT_PRI_GRP: + ? + PORT_ID: [[0,67], [204,219], [221,253],[255,271]] + TM_PRI_GRP_ID: [[0,7]] + : + MIN_GUARANTEE_CELLS: 0 + DYNAMIC_SHARED_LIMITS: 0 + SHARED_LIMIT_CELLS_STATIC: 0 + HEADROOM_LIMIT_CELLS: 0 + + TM_ING_THD_PORT_SERVICE_POOL: + ? + PORT_ID: [[0,67], [204,219], [221,253],[255,271]] + TM_ING_SERVICE_POOL_ID: [[0,3]] + : + MIN_GUARANTEE_CELLS: 0 + SHARED_LIMIT_CELLS: 0 + + TM_ING_THD_HEADROOM_POOL: + ? + BUFFER_POOL: 0 + TM_HEADROOM_POOL_ID: [[0,3]] + : + LIMIT_CELLS: 0 + + TM_THD_UC_Q: + ? + PORT_ID: [[1,67], [204,219], [221,253],[255,271]] + TM_UC_Q_ID: [[0,11]] + : + MIN_GUARANTEE_CELLS: 0 + SHARED_LIMITS: 1 + DYNAMIC_SHARED_LIMITS: 0 + SHARED_LIMIT_CELLS_STATIC: 0 + + TM_THD_MC_Q: + ? + PORT_ID: 0 + TM_MC_Q_ID: [[0,47]] + : + MIN_GUARANTEE_CELLS: 0 + ? + PORT_ID: [[1,67], [204,219], [221,253],[255,271]] + TM_MC_Q_ID: [[0,5]] + : + MIN_GUARANTEE_CELLS: 0 + SHARED_LIMITS: 1 + DYNAMIC_SHARED_LIMITS: 0 + SHARED_LIMIT_CELLS_STATIC: 0 + + TM_THD_Q_GRP: + ? + PORT_ID: [[0,67], [204,219], [221,253],[255,271]] + : + UC_Q_GRP_MIN_GUARANTEE_CELLS: 0 + MC_Q_GRP_MIN_GUARANTEE_CELLS: 0 +... +--- +device: + 0: + TM_ING_PORT: + ? + PORT_ID: [[0,67], [204,219], [221,253],[255,271]] + : + PAUSE: 0 + + TM_ING_PORT_PRI_GRP: + ? + PORT_ID: [[0,67], [204,219], [221,253],[255,271]] + TM_PRI_GRP_ID: [[0,7]] + : + PFC: 0 + LOSSLESS: 0 + ING_MIN_MODE: USE_PRI_GRP_MIN + + TM_PORT_UC_Q_TO_SERVICE_POOL: + ? + PORT_ID: [[1,67], [204,219], [221,253],[255,271]] + TM_UC_Q_ID: [[0,11]] + : + USE_QGROUP_MIN: 0 + + TM_PORT_MC_Q_TO_SERVICE_POOL: + ? + PORT_ID: 0 + TM_MC_Q_ID: [[0,47]] + : + USE_QGROUP_MIN: 0 + ? + PORT_ID: [[1,67], [204,219], [221,253],[255,271]] + TM_MC_Q_ID: [[0,5]] + : + USE_QGROUP_MIN: 0 +... +--- +device: + 0: + TM_ING_THD_HEADROOM_POOL: + ? + BUFFER_POOL: 0 + TM_HEADROOM_POOL_ID: [[0,3]] + : + LIMIT_CELLS: 0 + + TM_ING_THD_SERVICE_POOL: + ? + BUFFER_POOL: 0 + TM_ING_SERVICE_POOL_ID: [[0,3]] + : + SHARED_LIMIT_CELLS: 0 + SHARED_RESUME_OFFSET_CELLS: 0 + COLOR_SPECIFIC_LIMITS: 0 + + TM_EGR_THD_SERVICE_POOL: + ? + BUFFER_POOL: 0 + TM_EGR_SERVICE_POOL_ID: [[0,3]] + : + SHARED_LIMIT_CELLS: 0 + SHARED_RESUME_LIMIT_CELLS: 0 + COLOR_SPECIFIC_LIMITS: 0 + YELLOW_SHARED_LIMIT_CELLS: 0 + YELLOW_SHARED_RESUME_LIMIT_CELLS: 0 + RED_SHARED_LIMIT_CELLS: 0 + RED_SHARED_RESUME_LIMIT_CELLS: 0 + + TM_THD_MC_EGR_SERVICE_POOL: + ? + BUFFER_POOL: 0 + TM_EGR_SERVICE_POOL_ID: [[0,3]] + : + SHARED_LIMIT_CELLS: 0 + SHARED_RESUME_LIMIT_CELLS: 0 + COLOR_SPECIFIC_LIMITS: 0 + YELLOW_SHARED_LIMIT_CELLS: 0 + YELLOW_SHARED_RESUME_LIMIT_CELLS: 0 + RED_SHARED_LIMIT_CELLS: 0 + RED_SHARED_RESUME_LIMIT_CELLS: 0 +... + +### Mapping +--- +device: + 0: + TM_ING_UC_ING_PRI_MAP: + ? + # Profile 1 + TM_ING_UC_ING_PRI_MAP_ID: 1 + ING_PRI: [0, 1, 2, 5, 6, [8,15]] + : + TM_PRI_GRP_ID: 0 + ? + TM_ING_UC_ING_PRI_MAP_ID: 1 + ING_PRI: 3 + : + TM_PRI_GRP_ID: 3 + ? + TM_ING_UC_ING_PRI_MAP_ID: 1 + ING_PRI: 4 + : + TM_PRI_GRP_ID: 4 + ? + TM_ING_UC_ING_PRI_MAP_ID: 1 + ING_PRI: 7 + : + TM_PRI_GRP_ID: 7 + ? + # Profile 2 + TM_ING_UC_ING_PRI_MAP_ID: 1 + ING_PRI: [0, 1, 5, [8,15]] + : + TM_PRI_GRP_ID: 0 + ? + TM_ING_UC_ING_PRI_MAP_ID: 2 + ING_PRI: 2 + : + TM_PRI_GRP_ID: 2 + ? + TM_ING_UC_ING_PRI_MAP_ID: 2 + ING_PRI: 3 + : + TM_PRI_GRP_ID: 3 + ? + TM_ING_UC_ING_PRI_MAP_ID: 2 + ING_PRI: 4 + : + TM_PRI_GRP_ID: 4 + ? + TM_ING_UC_ING_PRI_MAP_ID: 2 + ING_PRI: 6 + : + TM_PRI_GRP_ID: 6 + ? + TM_ING_UC_ING_PRI_MAP_ID: 2 + ING_PRI: 7 + : + TM_PRI_GRP_ID: 7 + ? + # Profile 3 + TM_ING_UC_ING_PRI_MAP_ID: 3 + ING_PRI: [[0,15]] + : + TM_PRI_GRP_ID: 7 + + TM_ING_NONUC_ING_PRI_MAP: + ? + # Profile 1 + TM_ING_NONUC_ING_PRI_MAP_ID: 1 + ING_PRI: [0, 1, 2, 5, 6, [8,15]] + : + TM_PRI_GRP_ID: 0 + ? + TM_ING_NONUC_ING_PRI_MAP_ID: 1 + ING_PRI: 3 + : + TM_PRI_GRP_ID: 3 + ? + TM_ING_NONUC_ING_PRI_MAP_ID: 1 + ING_PRI: 4 + : + TM_PRI_GRP_ID: 4 + ? + TM_ING_NONUC_ING_PRI_MAP_ID: 1 + ING_PRI: 7 + : + TM_PRI_GRP_ID: 7 + ? + # Profile 2 + TM_ING_NONUC_ING_PRI_MAP_ID: 1 + ING_PRI: [0, 1, 5, [8,15]] + : + TM_PRI_GRP_ID: 0 + ? + TM_ING_NONUC_ING_PRI_MAP_ID: 2 + ING_PRI: 2 + : + TM_PRI_GRP_ID: 2 + ? + TM_ING_NONUC_ING_PRI_MAP_ID: 2 + ING_PRI: 3 + : + TM_PRI_GRP_ID: 3 + ? + TM_ING_NONUC_ING_PRI_MAP_ID: 2 + ING_PRI: 4 + : + TM_PRI_GRP_ID: 4 + ? + TM_ING_NONUC_ING_PRI_MAP_ID: 2 + ING_PRI: 6 + : + TM_PRI_GRP_ID: 6 + ? + TM_ING_NONUC_ING_PRI_MAP_ID: 2 + ING_PRI: 7 + : + TM_PRI_GRP_ID: 7 + ? + # Profile 3 + TM_ING_NONUC_ING_PRI_MAP_ID: 3 + ING_PRI: [[0,15]] + : + TM_PRI_GRP_ID: 7 + + TM_PRI_GRP_POOL_MAP: + ? + TM_PRI_GRP_POOL_MAP_ID: 1 + TM_PRI_GRP_ID: [[0,6]] + : + TM_ING_SERVICE_POOL_ID: 0 + TM_HEADROOM_POOL_ID: 0 + ? + TM_PRI_GRP_POOL_MAP_ID: 1 + TM_PRI_GRP_ID: 7 + : + TM_ING_SERVICE_POOL_ID: 1 + TM_HEADROOM_POOL_ID: 1 + + TM_ING_PORT: + ? + PORT_ID: [0] + : + ING_PRI_MAP_ID: 3 + PRI_GRP_MAP_ID: 1 + ? + PORT_ID: [[1,4], [204,207]] + : + ING_PRI_MAP_ID: 1 + PRI_GRP_MAP_ID: 1 + ? + PORT_ID: [[17,20], [34,37], [51,54], [221,224], [238,241], [255,258]] + : + ING_PRI_MAP_ID: 2 + PRI_GRP_MAP_ID: 1 + ? + PORT_ID: [50] + : + ING_PRI_MAP_ID: 1 + PRI_GRP_MAP_ID: 1 + ? + PORT_ID: [33, 67, 237, 271] + : + ING_PRI_MAP_ID: 1 + PRI_GRP_MAP_ID: 1 + + TM_PORT_UC_Q_TO_SERVICE_POOL: + ? + PORT_ID: [[1,4], [17,20], [33,37], [50,54], 67, [204,207], [221,224], [237,241], [255,258], 271] + TM_UC_Q_ID: [[0,6], [8,9]] + : + TM_EGR_SERVICE_POOL_ID: 0 + ? + PORT_ID: [[1,4], [17,20], [33,37], [50,54], 67, [204,207], [221,224], [237,241], [255,258], 271] + TM_UC_Q_ID: 7 + : + TM_EGR_SERVICE_POOL_ID: 1 + + TM_PORT_MC_Q_TO_SERVICE_POOL: + ? + PORT_ID: [0] + TM_MC_Q_ID: [[0,47]] + : + TM_EGR_SERVICE_POOL_ID: 1 + ? + PORT_ID: [[1,4], [17,20], [33,37], [50,54], 67, [204,207], [221,224], [237,241], [255,258], 271] + TM_MC_Q_ID: [[0,1]] + : + TM_EGR_SERVICE_POOL_ID: 0 +... + +### Scheduler +--- +device: + 0: + TM_SCHEDULER_PROFILE: + ? + TM_SCHEDULER_PROFILE_ID: 1 + TM_SCHEDULER_NODE_ID: [0, 1] + : + NUM_UC_Q: 1 + NUM_MC_Q: 1 + FLOW_CTRL_UC: 0 + ? + TM_SCHEDULER_PROFILE_ID: 1 + TM_SCHEDULER_NODE_ID: [2, 5, 6, 7, 8, 9] + : + NUM_UC_Q: 1 + NUM_MC_Q: 0 + FLOW_CTRL_UC: 0 + ? + TM_SCHEDULER_PROFILE_ID: 1 + TM_SCHEDULER_NODE_ID: [3, 4] + : + NUM_UC_Q: 1 + NUM_MC_Q: 0 + FLOW_CTRL_UC: 1 + ? + TM_SCHEDULER_PROFILE_ID: 1 + TM_SCHEDULER_NODE_ID: [10, 11] + : + NUM_UC_Q: 0 + NUM_MC_Q: 0 + FLOW_CTRL_UC: 0 + + TM_SCHEDULER_PROFILE: + ? + TM_SCHEDULER_PROFILE_ID: 2 + TM_SCHEDULER_NODE_ID: [0, 1] + : + NUM_UC_Q: 1 + NUM_MC_Q: 1 + FLOW_CTRL_UC: 0 + ? + TM_SCHEDULER_PROFILE_ID: 2 + TM_SCHEDULER_NODE_ID: [5, 7, 8, 9] + : + NUM_UC_Q: 1 + NUM_MC_Q: 0 + FLOW_CTRL_UC: 0 + ? + TM_SCHEDULER_PROFILE_ID: 2 + TM_SCHEDULER_NODE_ID: [2, 3, 4, 6] + : + NUM_UC_Q: 1 + NUM_MC_Q: 0 + FLOW_CTRL_UC: 1 + ? + TM_SCHEDULER_PROFILE_ID: 2 + TM_SCHEDULER_NODE_ID: [10, 11] + : + NUM_UC_Q: 0 + NUM_MC_Q: 0 + FLOW_CTRL_UC: 0 +... +--- +device: + 0: + TM_SCHEDULER_PORT_PROFILE: + ? + PORT_ID: [[1,4], [204,207]] + : + TM_SCHEDULER_PROFILE_ID: 1 + WRR: 0 + TM_SCHEDULER_PORT_PROFILE: + ? + PORT_ID: [[17,20], [34,37], [51,54], [221,224], [238,241], [255,258]] + : + TM_SCHEDULER_PROFILE_ID: 2 + WRR: 0 +... + +### Pools +### hard code service pool size for TH4 per architecture requirement. +--- +device: + 0: + TM_ING_THD_HEADROOM_POOL: + ? + BUFFER_POOL: 0 + TM_HEADROOM_POOL_ID: 0 + : + LIMIT_CELLS: 45696 + + TM_ING_THD_SERVICE_POOL: + ? + BUFFER_POOL: 0 + TM_ING_SERVICE_POOL_ID: 0 + : + SHARED_LIMIT_CELLS: 173222 + SHARED_RESUME_OFFSET_CELLS: 74 + COLOR_SPECIFIC_LIMITS: 0 + ? + BUFFER_POOL: 0 + TM_ING_SERVICE_POOL_ID: 1 + : + SHARED_LIMIT_CELLS: 605 + SHARED_RESUME_OFFSET_CELLS: 74 + COLOR_SPECIFIC_LIMITS: 0 + + TM_EGR_THD_SERVICE_POOL: + ? + BUFFER_POOL: 0 + TM_EGR_SERVICE_POOL_ID: 0 + : + SHARED_LIMIT_CELLS: 173222 + SHARED_RESUME_LIMIT_CELLS: 21643 + COLOR_SPECIFIC_LIMITS: 1 + YELLOW_SHARED_LIMIT_CELLS: 16240 + YELLOW_SHARED_RESUME_LIMIT_CELLS: 16230 + RED_SHARED_LIMIT_CELLS: 13533 + RED_SHARED_RESUME_LIMIT_CELLS: 13523 + ? + BUFFER_POOL: 0 + TM_EGR_SERVICE_POOL_ID: 1 + : + SHARED_LIMIT_CELLS: 605 + SHARED_RESUME_LIMIT_CELLS: 73 + COLOR_SPECIFIC_LIMITS: 1 + YELLOW_SHARED_LIMIT_CELLS: 57 + YELLOW_SHARED_RESUME_LIMIT_CELLS: 55 + RED_SHARED_LIMIT_CELLS: 48 + RED_SHARED_RESUME_LIMIT_CELLS: 46 + + TM_THD_MC_EGR_SERVICE_POOL: + ? + BUFFER_POOL: 0 + TM_EGR_SERVICE_POOL_ID: 0 + : + SHARED_LIMIT_CELLS: 15779 + SHARED_RESUME_LIMIT_CELLS: 1962 + COLOR_SPECIFIC_LIMITS: 1 + YELLOW_SHARED_LIMIT_CELLS: 1480 + YELLOW_SHARED_RESUME_LIMIT_CELLS: 1470 + RED_SHARED_LIMIT_CELLS: 1233 + RED_SHARED_RESUME_LIMIT_CELLS: 1223 + ? + BUFFER_POOL: 0 + TM_EGR_SERVICE_POOL_ID: 1 + : + SHARED_LIMIT_CELLS: 605 + SHARED_RESUME_LIMIT_CELLS: 73 + COLOR_SPECIFIC_LIMITS: 1 + YELLOW_SHARED_LIMIT_CELLS: 57 + YELLOW_SHARED_RESUME_LIMIT_CELLS: 55 + RED_SHARED_LIMIT_CELLS: 46 + RED_SHARED_RESUME_LIMIT_CELLS: 46 +... + +### Thresholds +###################################### +--- +device: + 0: + TM_ING_THD_PORT_PRI_GRP: + ? + PORT_ID: [[0,4], [17,20], [33,37], [50,54], 67, [204,207], [221,224], [237,241], [255,258], 271] + TM_PRI_GRP_ID: [0, 1, 5, 7] + : + SHARED_LIMIT_CELLS_STATIC: 227317 + MIN_GUARANTEE_CELLS: 0 + DYNAMIC_SHARED_LIMITS: 0 + RESUME_OFFSET_CELLS: 0 + RESUME_FLOOR_CELLS: 0 + HEADROOM_LIMIT_AUTO: 0 + HEADROOM_LIMIT_CELLS: 0 + ? + PORT_ID: [[1,4], [204,207]] + TM_PRI_GRP_ID: [2, 3, 4, 6] + : + MIN_GUARANTEE_CELLS: 18 + DYNAMIC_SHARED_LIMITS: 1 + SHARED_LIMIT_DYNAMIC: ALPHA_1_4 + RESUME_OFFSET_CELLS: 18 + RESUME_FLOOR_CELLS: 0 + HEADROOM_LIMIT_AUTO: 0 + HEADROOM_LIMIT_CELLS: 2874 + ? + PORT_ID: [[17,20], [34,37], [51,54], [221,224], [238,241], [255,258]] + TM_PRI_GRP_ID: [2, 3, 4, 6] + : + MIN_GUARANTEE_CELLS: 18 + DYNAMIC_SHARED_LIMITS: 1 + SHARED_LIMIT_DYNAMIC: ALPHA_1_4 + RESUME_OFFSET_CELLS: 18 + RESUME_FLOOR_CELLS: 0 + HEADROOM_LIMIT_AUTO: 0 + HEADROOM_LIMIT_CELLS: 675 + ? + PORT_ID: [50] + TM_PRI_GRP_ID: [2, 3, 4, 6] + : + MIN_GUARANTEE_CELLS: 0 + DYNAMIC_SHARED_LIMITS: 1 + SHARED_LIMIT_DYNAMIC: ALPHA_1_4 + RESUME_OFFSET_CELLS: 0 + RESUME_FLOOR_CELLS: 0 + HEADROOM_LIMIT_AUTO: 0 + ? + PORT_ID: [33, 67, 237, 271] + TM_PRI_GRP_ID: [2, 3, 4, 6] + : + MIN_GUARANTEE_CELLS: 0 + DYNAMIC_SHARED_LIMITS: 1 + SHARED_LIMIT_DYNAMIC: ALPHA_1_4 + RESUME_OFFSET_CELLS: 0 + RESUME_FLOOR_CELLS: 0 + HEADROOM_LIMIT_AUTO: 0 + ? + PORT_ID: [0] + TM_PRI_GRP_ID: [2, 3, 4, 6] + : + MIN_GUARANTEE_CELLS: 0 + DYNAMIC_SHARED_LIMITS: 1 + SHARED_LIMIT_DYNAMIC: ALPHA_1_4 + RESUME_OFFSET_CELLS: 0 + RESUME_FLOOR_CELLS: 0 + HEADROOM_LIMIT_AUTO: 0 + + TM_ING_THD_PORT_SERVICE_POOL: + ? + PORT_ID: [[0,4], [17,20], [33,37], [50,54], 67, [204,207], [221,224], [237,241], [255,258], 271] + TM_ING_SERVICE_POOL_ID: [0, 1] + : + MIN_GUARANTEE_CELLS: 0 + SHARED_LIMIT_CELLS: 227317 + RESUME_LIMIT_CELLS: 227317 + + TM_THD_UC_Q: + ? + PORT_ID: [[1,4], [17,20], [33,37], [50,54], 67, [204,207], [221,224], [237,241], [255,258], 271] + TM_UC_Q_ID: [0, 1, 5, 7, 8, 9] + : + SHARED_LIMITS: 1 + COLOR_SPECIFIC_LIMITS: 1 + RED_LIMIT_DYNAMIC: PERCENTAGE_675 + YELLOW_LIMIT_DYNAMIC: PERCENTAGE_750 + COLOR_SPECIFIC_DYNAMIC_LIMITS: 1 + MIN_GUARANTEE_CELLS: 7 + DYNAMIC_SHARED_LIMITS: 1 + SHARED_LIMIT_DYNAMIC: ALPHA_1 + RESUME_OFFSET_CELLS: 2 + ? + PORT_ID: [[1,4], [17,20], [33,37], [50,54], 67, [204,207], [221,224], [237,241], [255,258], 271] + TM_UC_Q_ID: [2, 3, 4, 6] + : + SHARED_LIMITS: 0 + COLOR_SPECIFIC_LIMITS: 0 + COLOR_SPECIFIC_DYNAMIC_LIMITS: 0 + MIN_GUARANTEE_CELLS: 0 + DYNAMIC_SHARED_LIMITS: 0 + SHARED_LIMIT_CELLS_STATIC: 227317 + RESUME_OFFSET_CELLS: 2 + + TM_THD_MC_Q: + ? + PORT_ID: [0] + TM_MC_Q_ID: [0, 1, 2, 3] + : + MIN_GUARANTEE_CELLS: 37 + DYNAMIC_SHARED_LIMITS: 1 + SHARED_LIMIT_DYNAMIC: ALPHA_2 + COLOR_SPECIFIC_LIMITS: 1 + COLOR_SPECIFIC_DYNAMIC_LIMITS: 1 + YELLOW_LIMIT_DYNAMIC: PERCENTAGE_750 + RED_LIMIT_DYNAMIC: PERCENTAGE_675 + RESUME_OFFSET_CELLS: 2 + ? + PORT_ID: [0] + TM_MC_Q_ID: [4, 5, 6, 7, 8, 9] + : + MIN_GUARANTEE_CELLS: 7 + SHARED_LIMITS: 1 + DYNAMIC_SHARED_LIMITS: 1 + SHARED_LIMIT_DYNAMIC: ALPHA_1_4 + COLOR_SPECIFIC_LIMITS: 1 + COLOR_SPECIFIC_DYNAMIC_LIMITS: 1 + YELLOW_LIMIT_DYNAMIC: PERCENTAGE_750 + RED_LIMIT_DYNAMIC: PERCENTAGE_675 + RESUME_OFFSET_CELLS: 2 + ? + PORT_ID: [[1,4], [17,20], [33,37], [50,54], 67, [204,207], [221,224], [237,241], [255,258], 271] + TM_MC_Q_ID: [0, 1] + : + SHARED_LIMITS: 1 + DYNAMIC_SHARED_LIMITS: 1 + SHARED_LIMIT_DYNAMIC: ALPHA_1 + COLOR_SPECIFIC_LIMITS: 1 + COLOR_SPECIFIC_DYNAMIC_LIMITS: 1 + YELLOW_LIMIT_DYNAMIC: PERCENTAGE_750 + RED_LIMIT_DYNAMIC: PERCENTAGE_675 + RESUME_OFFSET_CELLS: 2 + + TM_EGR_THD_UC_PORT_SERVICE_POOL: + ? + PORT_ID: [[1,4], [17,20], [33,37], [50,54], 67, [204,207], [221,224], [237,241], [255,258], 271] + TM_EGR_SERVICE_POOL_ID: 0 + : + SHARED_LIMIT_CELLS: 173222 + SHARED_RESUME_LIMIT_CELLS: 21651 + COLOR_SPECIFIC_LIMITS: 1 + YELLOW_SHARED_LIMIT_CELLS: 16239 + YELLOW_SHARED_RESUME_LIMIT_CELLS: 16237 + RED_SHARED_LIMIT_CELLS: 13532 + RED_SHARED_RESUME_LIMIT_CELLS: 13530 + ? + PORT_ID: [[1,4], [17,20], [33,37], [50,54], 67, [204,207], [221,224], [237,241], [255,258], 271] + TM_EGR_SERVICE_POOL_ID: 1 + : + SHARED_LIMIT_CELLS: 605 + SHARED_RESUME_LIMIT_CELLS: 73 + COLOR_SPECIFIC_LIMITS: 1 + YELLOW_SHARED_LIMIT_CELLS: 56 + YELLOW_SHARED_RESUME_LIMIT_CELLS: 54 + RED_SHARED_LIMIT_CELLS: 47 + RED_SHARED_RESUME_LIMIT_CELLS: 45 + + TM_EGR_THD_MC_PORT_SERVICE_POOL: + ? + PORT_ID: [[0,4], [17,20], [33,37], [50,54], 67, [204,207], [221,224], [237,241], [255,258], 271] + TM_EGR_SERVICE_POOL_ID: 0 + : + COLOR_SPECIFIC_LIMITS: 1 + RED_SHARED_LIMIT_CELLS: 1232 + YELLOW_SHARED_LIMIT_CELLS: 1479 + SHARED_LIMIT_CELLS: 15779 + RED_SHARED_RESUME_LIMIT_CELLS: 1230 + YELLOW_SHARED_RESUME_LIMIT_CELLS: 1477 + SHARED_RESUME_LIMIT_CELLS: 1970 + ? + PORT_ID: [[0,4], [17,20], [33,37], [50,54], 67, [204,207], [221,224], [237,241], [255,258], 271] + TM_EGR_SERVICE_POOL_ID: 1 + : + COLOR_SPECIFIC_LIMITS: 1 + RED_SHARED_LIMIT_CELLS: 47 + YELLOW_SHARED_LIMIT_CELLS: 56 + SHARED_LIMIT_CELLS: 605 + RED_SHARED_RESUME_LIMIT_CELLS: 45 + YELLOW_SHARED_RESUME_LIMIT_CELLS: 54 + SHARED_RESUME_LIMIT_CELLS: 73 + + +... +### THDR Limits +--- +device: + 0: + TM_THD_REPL_SERVICE_POOL: + COLOR_SPECIFIC_LIMITS: 1 + SHARED_LIMIT_CELLS: 2961 + SHARED_RESUME_LIMIT_CELLS: 2947 + YELLOW_SHARED_LIMIT_CELLS: 2220 + YELLOW_SHARED_RESUME_LIMIT_CELLS: 2206 + RED_SHARED_LIMIT_CELLS: 1850 + RED_SHARED_RESUME_LIMIT_CELLS: 1836 + + TM_THD_REPL_Q: + ? + REPL_Q_NUM: [0,8] + : + COLOR_SPECIFIC_LIMITS: 1 + COLOR_SPECIFIC_DYNAMIC_LIMITS: 1 + SHARED_LIMITS: 1 + DYNAMIC_SHARED_LIMITS: 1 + RESUME_OFFSET_CELLS: 14 + SHARED_LIMIT_DYNAMIC: ALPHA_1 + YELLOW_LIMIT_DYNAMIC: PERCENTAGE_750 + RED_LIMIT_DYNAMIC: PERCENTAGE_675 + RESUME_OFFSET_YELLOW_CELLS: 14 + RESUME_OFFSET_RED_CELLS: 14 + + TM_THD_REPL_Q: + ? + REPL_Q_NUM: [0,5] + : + MIN_GUARANTEE_CELLS: 0 + ? + REPL_Q_NUM: [6,8] + : + MIN_GUARANTEE_CELLS: 37 + +... +### Mirror-on-drop +--- +device: + 0: + TM_MIRROR_ON_DROP_CONTROL: + RESERVED_LIMIT_CELLS: 2580 + + TM_MIRROR_ON_DROP_PROFILE: + ? + TM_MIRROR_ON_DROP_PROFILE_ID: 0 + : + PERCENTAGE_0_25: 65535 + PERCENTAGE_25_50: 65535 + PERCENTAGE_50_75: 65535 + PERCENTAGE_75_100: 65535 + + TM_MIRROR_ON_DROP_DESTINATION: + ? + TM_MIRROR_ON_DROP_DESTINATION_ID: 0 + : + TM_MC_Q_ID: 1 + PORT_ID: 1 +... + +### OBM +--- +device: + 0: + TM_OBM_PORT_PKT_PARSE: + ? + PORT_ID: [[1,4], [204,207]] + : + DSCP_MAP: 1 + HEADER_TYPE: OBM_HEADER_TYPE_ETHERNET + DEFAULT_PKT_PRI: 0 + + TM_OBM_PORT_PKT_PARSE: + ? + PORT_ID: [[17,20], [34,37], [51,54], [221,224], [238,241], [255,258]] + : + DSCP_MAP: 1 + HEADER_TYPE: OBM_HEADER_TYPE_ETHERNET + DEFAULT_PKT_PRI: 0 + + TM_OBM_PORT_PKT_PRI_TC_MAP: + ? + PORT_ID: [[1,4], [204,207]] + PKT_PRI_TYPE: PKT_PRI_TYPE_DSCP + PKT_PRI: [3, 4] + : + TRAFFIC_CLASS: OBM_TC_LOSSLESS0 + + TM_OBM_PORT_PKT_PRI_TC_MAP: + ? + PORT_ID: [[17,20], [34,37], [51,54], [221,224], [238,241], [255,258]] + PKT_PRI_TYPE: PKT_PRI_TYPE_DSCP + PKT_PRI: [2, 3, 4, 6] + : + TRAFFIC_CLASS: OBM_TC_LOSSLESS0 + + TM_OBM_THD_PORT: + ? + PORT_ID: [[1,4], [204,207]] + : + THD_AUTO: 0 + LOSSY_LOW_MAX_BYTES: 37376 + LOSSLESS0_MAX_BYTES: 235264 + MAX_BYTES: 235264 + + TM_OBM_THD_PORT: + ? + PORT_ID: [[17,20], [34,37], [51,54], [221,224], [238,241], [255,258]] + : + THD_AUTO: 0 + LOSSY_LOW_MAX_BYTES: 37376 + LOSSLESS0_MAX_BYTES: 235264 + MAX_BYTES: 235264 + + TM_OBM_THD_PORT_FLOW_CTRL: + ? + PORT_ID: [[1,4], [204,207]] + : + THD_AUTO: 0 + LOSSLESS0_XOFF_BYTES: 5184 + LOSSLESS0_XON_BYTES: 4672 + XOFF_BYTES: 5184 + XON_BYTES: 4672 + + TM_OBM_THD_PORT_FLOW_CTRL: + ? + PORT_ID: [[17,20], [34,37], [51,54], [221,224], [238,241], [255,258]] + : + THD_AUTO: 0 + LOSSLESS0_XOFF_BYTES: 5184 + LOSSLESS0_XON_BYTES: 4672 + XOFF_BYTES: 5184 + XON_BYTES: 4672 + + TM_OBM_PORT_FLOW_CTRL: + ? + PORT_ID: [[1,4], [204,207]] + : + FLOW_CTRL: 1 + FLOW_CTRL_TYPE: PFC + LOSSLESS0_FLOW_CTRL: 1 + + TM_OBM_PORT_FLOW_CTRL: + ? + PORT_ID: [[17,20], [34,37], [51,54], [221,224], [238,241], [255,258]] + : + FLOW_CTRL: 1 + FLOW_CTRL_TYPE: PFC + LOSSLESS0_FLOW_CTRL: 1 +... + +### PFC +--- +device: + 0: + PC_MAC_CONTROL: + ? + PORT_ID: [[1,4], [17,20], [33,37], [50,54], 67, [204,207], [221,224], [237,241], [255,258], 271] + : + PAUSE_TX: 0 + PAUSE_RX: 0 + + TM_PFC_EGR: + ? + PORT_ID: [[1,4], [204,207]] + : + TM_PFC_PRI_PROFILE_ID: 1 + + TM_PFC_EGR: + ? + PORT_ID: [[17,20], [34,37], [51,54], [221,224], [238,241], [255,258]] + : + TM_PFC_PRI_PROFILE_ID: 2 +... +--- +device: + 0: + TM_PFC_PRI_TO_PRI_GRP_MAP: + ? + TM_PFC_PRI_TO_PRI_GRP_MAP_ID: 1 + PFC_PRI: 3 + : + TM_PRI_GRP_ID: 3 + + TM_PFC_PRI_TO_PRI_GRP_MAP: + ? + TM_PFC_PRI_TO_PRI_GRP_MAP_ID: 1 + PFC_PRI: 4 + : + TM_PRI_GRP_ID: 4 + + TM_PFC_PRI_TO_PRI_GRP_MAP: + ? + TM_PFC_PRI_TO_PRI_GRP_MAP_ID: 2 + PFC_PRI: 2 + : + TM_PRI_GRP_ID: 2 + + TM_PFC_PRI_TO_PRI_GRP_MAP: + ? + TM_PFC_PRI_TO_PRI_GRP_MAP_ID: 2 + PFC_PRI: 3 + : + TM_PRI_GRP_ID: 3 + + TM_PFC_PRI_TO_PRI_GRP_MAP: + ? + TM_PFC_PRI_TO_PRI_GRP_MAP_ID: 2 + PFC_PRI: 4 + : + TM_PRI_GRP_ID: 4 + + TM_PFC_PRI_TO_PRI_GRP_MAP: + ? + TM_PFC_PRI_TO_PRI_GRP_MAP_ID: 2 + PFC_PRI: 6 + : + TM_PRI_GRP_ID: 6 + + TM_PFC_PRI_PROFILE: + ? + TM_PFC_PRI_PROFILE_ID: 1 + PFC_PRI: 3 + : + PFC: 1 + COS_LIST: [0, 0, 0, 1, 0, 0, 0, 0, 0, 0] + + TM_PFC_PRI_PROFILE: + ? + TM_PFC_PRI_PROFILE_ID: 1 + PFC_PRI: 4 + : + PFC: 1 + COS_LIST: [0, 0, 0, 0, 1, 0, 0, 0, 0, 0] + + TM_PFC_PRI_PROFILE: + ? + TM_PFC_PRI_PROFILE_ID: 2 + PFC_PRI: 2 + : + PFC: 1 + COS_LIST: [0, 0, 1, 0, 0, 0, 0, 0, 0, 0] + + TM_PFC_PRI_PROFILE: + ? + TM_PFC_PRI_PROFILE_ID: 2 + PFC_PRI: 3 + : + PFC: 1 + COS_LIST: [0, 0, 0, 1, 0, 0, 0, 0, 0, 0] + + TM_PFC_PRI_PROFILE: + ? + TM_PFC_PRI_PROFILE_ID: 2 + PFC_PRI: 4 + : + PFC: 1 + COS_LIST: [0, 0, 0, 0, 1, 0, 0, 0, 0, 0] + + TM_PFC_PRI_PROFILE: + ? + TM_PFC_PRI_PROFILE_ID: 2 + PFC_PRI: 6 + : + PFC: 1 + COS_LIST: [0, 0, 0, 0, 0, 0, 1, 0, 0, 0] + + TM_ING_PORT_PRI_GRP: + ? + PORT_ID: [[1,4], [204,207]] + TM_PRI_GRP_ID: [3, 4] + : + PFC: 1 + LOSSLESS: 1 + + TM_ING_PORT_PRI_GRP: + ? + PORT_ID: [[17,20], [34,37], [51,54], [221,224], [238,241], [255,258]] + TM_PRI_GRP_ID: [2, 3, 4, 6] + : + PFC: 1 + LOSSLESS: 1 + + PC_PFC: + ? + PORT_ID: [[1,4], [204,207]] + : + ENABLE_RX: 1 + ENABLE_TX: 1 + + PC_PFC: + ? + PORT_ID: [[17,20], [34,37], [51,54], [221,224], [238,241], [255,258]] + : + ENABLE_RX: 1 + ENABLE_TX: 1 +... diff --git a/device/arista/x86_64-arista_7060dx5_32/default_sku b/device/arista/x86_64-arista_7060dx5_32/default_sku new file mode 100644 index 000000000000..6636cf97eedb --- /dev/null +++ b/device/arista/x86_64-arista_7060dx5_32/default_sku @@ -0,0 +1 @@ +Arista-7060DX5-32 t1 diff --git a/device/arista/x86_64-arista_7060dx5_32/platform.json b/device/arista/x86_64-arista_7060dx5_32/platform.json new file mode 100644 index 000000000000..e98355e15ada --- /dev/null +++ b/device/arista/x86_64-arista_7060dx5_32/platform.json @@ -0,0 +1,933 @@ +{ + "chassis": { + "name": "DCS-7060DX5-32", + "components": [ + { + "name": "Aboot()" + }, + { + "name": "Scd(addr=0000:00:18.7)" + }, + { + "name": "Scd(addr=0000:01:00.0)" + }, + { + "name": "LorikeetSysCpld(addr=13-0023)" + } + ], + "fans": [], + "fan_drawers": [ + { + "name": "slot1", + "fans": [ + { + "name": "fan1" + }, + { + "name": "fan2" + } + ] + }, + { + "name": "slot2", + "fans": [ + { + "name": "fan3" + }, + { + "name": "fan4" + } + ] + }, + { + "name": "slot3", + "fans": [ + { + "name": "fan5" + }, + { + "name": "fan6" + } + ] + } + ], + "psus": [ + { + "name": "psu1", + "fans": [ + { + "name": "psu1/1", + "speed": { + "controllable": false + } + } + ] + }, + { + "name": "psu2", + "fans": [ + { + "name": "psu2/1", + "speed": { + "controllable": false + } + } + ] + } + ], + "thermals": [ + { + "name": "Cpu temp sensor", + "controllable": false + }, + { + "name": "CPU board temp sensor", + "controllable": false + }, + { + "name": "Back-panel temp sensor", + "controllable": false + }, + { + "name": "Center Rear", + "controllable": false + }, + { + "name": "Switch board right sensor", + "controllable": false + }, + { + "name": "Switch board left sensor", + "controllable": false + }, + { + "name": "Front-panel temp sensor", + "controllable": false + }, + { + "name": "Switch chip diode 1 sensor", + "controllable": false + }, + { + "name": "Switch chip diode 2 sensor", + "controllable": false + } + ], + "sfps": [ + { + "name": "osfp1" + }, + { + "name": "osfp2" + }, + { + "name": "osfp3" + }, + { + "name": "osfp4" + }, + { + "name": "osfp5" + }, + { + "name": "osfp6" + }, + { + "name": "osfp7" + }, + { + "name": "osfp8" + }, + { + "name": "osfp9" + }, + { + "name": "osfp10" + }, + { + "name": "osfp11" + }, + { + "name": "osfp12" + }, + { + "name": "osfp13" + }, + { + "name": "osfp14" + }, + { + "name": "osfp15" + }, + { + "name": "osfp16" + }, + { + "name": "osfp17" + }, + { + "name": "osfp18" + }, + { + "name": "osfp19" + }, + { + "name": "osfp20" + }, + { + "name": "osfp21" + }, + { + "name": "osfp22" + }, + { + "name": "osfp23" + }, + { + "name": "osfp24" + }, + { + "name": "osfp25" + }, + { + "name": "osfp26" + }, + { + "name": "osfp27" + }, + { + "name": "osfp28" + }, + { + "name": "osfp29" + }, + { + "name": "osfp30" + }, + { + "name": "osfp31" + }, + { + "name": "osfp32" + }, + { + "name": "sfp33" + } + ] + }, + "interfaces": { + "Ethernet0": { + "index": "1,1,1,1,1,1,1,1", + "lanes": "1,2,3,4,5,6,7,8", + "breakout_modes": { + "1x400G[200G,100G,50G,40G,25G,10G]": [ + "Ethernet1/1" + ], + "2x200G[100G,50G,40G,25G,10G]": [ + "Ethernet1/1", + "Ethernet1/5" + ], + "4x100G[50G,40G,25G,10G]": [ + "Ethernet1/1", + "Ethernet1/3", + "Ethernet1/5", + "Ethernet1/7" + ], + "1x100G(4)": [ + "Ethernet1/1" + ] + } + }, + "Ethernet8": { + "index": "2,2,2,2,2,2,2,2", + "lanes": "9,10,11,12,13,14,15,16", + "breakout_modes": { + "1x400G[200G,100G,50G,40G,25G,10G]": [ + "Ethernet2/1" + ], + "2x200G[100G,50G,40G,25G,10G]": [ + "Ethernet2/1", + "Ethernet2/5" + ], + "4x100G[50G,40G,25G,10G]": [ + "Ethernet2/1", + "Ethernet2/3", + "Ethernet2/5", + "Ethernet2/7" + ], + "1x100G(4)": [ + "Ethernet2/1" + ] + } + }, + "Ethernet16": { + "index": "3,3,3,3,3,3,3,3", + "lanes": "17,18,19,20,21,22,23,24", + "breakout_modes": { + "1x400G[200G,100G,50G,40G,25G,10G]": [ + "Ethernet3/1" + ], + "2x200G[100G,50G,40G,25G,10G]": [ + "Ethernet3/1", + "Ethernet3/5" + ], + "4x100G[50G,40G,25G,10G]": [ + "Ethernet3/1", + "Ethernet3/3", + "Ethernet3/5", + "Ethernet3/7" + ], + "1x100G(4)": [ + "Ethernet3/1" + ] + } + }, + "Ethernet24": { + "index": "4,4,4,4,4,4,4,4", + "lanes": "25,26,27,28,29,30,31,32", + "breakout_modes": { + "1x400G[200G,100G,50G,40G,25G,10G]": [ + "Ethernet4/1" + ], + "2x200G[100G,50G,40G,25G,10G]": [ + "Ethernet4/1", + "Ethernet4/5" + ], + "4x100G[50G,40G,25G,10G]": [ + "Ethernet4/1", + "Ethernet4/3", + "Ethernet4/5", + "Ethernet4/7" + ], + "1x100G(4)": [ + "Ethernet4/1" + ] + } + }, + "Ethernet32": { + "index": "5,5,5,5,5,5,5,5", + "lanes": "33,34,35,36,37,38,39,40", + "breakout_modes": { + "1x400G[200G,100G,50G,40G,25G,10G]": [ + "Ethernet5/1" + ], + "2x200G[100G,50G,40G,25G,10G]": [ + "Ethernet5/1", + "Ethernet5/5" + ], + "4x100G[50G,40G,25G,10G]": [ + "Ethernet5/1", + "Ethernet5/3", + "Ethernet5/5", + "Ethernet5/7" + ], + "1x100G(4)": [ + "Ethernet5/1" + ] + } + }, + "Ethernet40": { + "index": "6,6,6,6,6,6,6,6", + "lanes": "41,42,43,44,45,46,47,48", + "breakout_modes": { + "1x400G[200G,100G,50G,40G,25G,10G]": [ + "Ethernet6/1" + ], + "2x200G[100G,50G,40G,25G,10G]": [ + "Ethernet6/1", + "Ethernet6/5" + ], + "4x100G[50G,40G,25G,10G]": [ + "Ethernet6/1", + "Ethernet6/3", + "Ethernet6/5", + "Ethernet6/7" + ], + "1x100G(4)": [ + "Ethernet6/1" + ] + } + }, + "Ethernet48": { + "index": "7,7,7,7,7,7,7,7", + "lanes": "49,50,51,52,53,54,55,56", + "breakout_modes": { + "1x400G[200G,100G,50G,40G,25G,10G]": [ + "Ethernet7/1" + ], + "2x200G[100G,50G,40G,25G,10G]": [ + "Ethernet7/1", + "Ethernet7/5" + ], + "4x100G[50G,40G,25G,10G]": [ + "Ethernet7/1", + "Ethernet7/3", + "Ethernet7/5", + "Ethernet7/7" + ], + "1x100G(4)": [ + "Ethernet7/1" + ] + } + }, + "Ethernet56": { + "index": "8,8,8,8,8,8,8,8", + "lanes": "57,58,59,60,61,62,63,64", + "breakout_modes": { + "1x400G[200G,100G,50G,40G,25G,10G]": [ + "Ethernet8/1" + ], + "2x200G[100G,50G,40G,25G,10G]": [ + "Ethernet8/1", + "Ethernet8/5" + ], + "4x100G[50G,40G,25G,10G]": [ + "Ethernet8/1", + "Ethernet8/3", + "Ethernet8/5", + "Ethernet8/7" + ], + "1x100G(4)": [ + "Ethernet8/1" + ] + } + }, + "Ethernet64": { + "index": "9,9,9,9,9,9,9,9", + "lanes": "65,66,67,68,69,70,71,72", + "breakout_modes": { + "1x400G[200G,100G,50G,40G,25G,10G]": [ + "Ethernet9/1" + ], + "2x200G[100G,50G,40G,25G,10G]": [ + "Ethernet9/1", + "Ethernet9/5" + ], + "4x100G[50G,40G,25G,10G]": [ + "Ethernet9/1", + "Ethernet9/3", + "Ethernet9/5", + "Ethernet9/7" + ], + "1x100G(4)": [ + "Ethernet9/1" + ] + } + }, + "Ethernet72": { + "index": "10,10,10,10,10,10,10,10", + "lanes": "73,74,75,76,77,78,79,80", + "breakout_modes": { + "1x400G[200G,100G,50G,40G,25G,10G]": [ + "Ethernet10/1" + ], + "2x200G[100G,50G,40G,25G,10G]": [ + "Ethernet10/1", + "Ethernet10/5" + ], + "4x100G[50G,40G,25G,10G]": [ + "Ethernet10/1", + "Ethernet10/3", + "Ethernet10/5", + "Ethernet10/7" + ], + "1x100G(4)": [ + "Ethernet10/1" + ] + } + }, + "Ethernet80": { + "index": "11,11,11,11,11,11,11,11", + "lanes": "81,82,83,84,85,86,87,88", + "breakout_modes": { + "1x400G[200G,100G,50G,40G,25G,10G]": [ + "Ethernet11/1" + ], + "2x200G[100G,50G,40G,25G,10G]": [ + "Ethernet11/1", + "Ethernet11/5" + ], + "4x100G[50G,40G,25G,10G]": [ + "Ethernet11/1", + "Ethernet11/3", + "Ethernet11/5", + "Ethernet11/7" + ], + "1x100G(4)": [ + "Ethernet11/1" + ] + } + }, + "Ethernet88": { + "index": "12,12,12,12,12,12,12,12", + "lanes": "89,90,91,92,93,94,95,96", + "breakout_modes": { + "1x400G[200G,100G,50G,40G,25G,10G]": [ + "Ethernet12/1" + ], + "2x200G[100G,50G,40G,25G,10G]": [ + "Ethernet12/1", + "Ethernet12/5" + ], + "4x100G[50G,40G,25G,10G]": [ + "Ethernet12/1", + "Ethernet12/3", + "Ethernet12/5", + "Ethernet12/7" + ], + "1x100G(4)": [ + "Ethernet12/1" + ] + } + }, + "Ethernet96": { + "index": "13,13,13,13,13,13,13,13", + "lanes": "97,98,99,100,101,102,103,104", + "breakout_modes": { + "1x400G[200G,100G,50G,40G,25G,10G]": [ + "Ethernet13/1" + ], + "2x200G[100G,50G,40G,25G,10G]": [ + "Ethernet13/1", + "Ethernet13/5" + ], + "4x100G[50G,40G,25G,10G]": [ + "Ethernet13/1", + "Ethernet13/3", + "Ethernet13/5", + "Ethernet13/7" + ], + "1x100G(4)": [ + "Ethernet13/1" + ] + } + }, + "Ethernet104": { + "index": "14,14,14,14,14,14,14,14", + "lanes": "105,106,107,108,109,110,111,112", + "breakout_modes": { + "1x400G[200G,100G,50G,40G,25G,10G]": [ + "Ethernet14/1" + ], + "2x200G[100G,50G,40G,25G,10G]": [ + "Ethernet14/1", + "Ethernet14/5" + ], + "4x100G[50G,40G,25G,10G]": [ + "Ethernet14/1", + "Ethernet14/3", + "Ethernet14/5", + "Ethernet14/7" + ], + "1x100G(4)": [ + "Ethernet14/1" + ] + } + }, + "Ethernet112": { + "index": "15,15,15,15,15,15,15,15", + "lanes": "113,114,115,116,117,118,119,120", + "breakout_modes": { + "1x400G[200G,100G,50G,40G,25G,10G]": [ + "Ethernet15/1" + ], + "2x200G[100G,50G,40G,25G,10G]": [ + "Ethernet15/1", + "Ethernet15/5" + ], + "4x100G[50G,40G,25G,10G]": [ + "Ethernet15/1", + "Ethernet15/3", + "Ethernet15/5", + "Ethernet15/7" + ], + "1x100G(4)": [ + "Ethernet15/1" + ] + } + }, + "Ethernet120": { + "index": "16,16,16,16,16,16,16,16", + "lanes": "121,122,123,124,125,126,127,128", + "breakout_modes": { + "1x400G[200G,100G,50G,40G,25G,10G]": [ + "Ethernet16/1" + ], + "2x200G[100G,50G,40G,25G,10G]": [ + "Ethernet16/1", + "Ethernet16/5" + ], + "4x100G[50G,40G,25G,10G]": [ + "Ethernet16/1", + "Ethernet16/3", + "Ethernet16/5", + "Ethernet16/7" + ], + "1x100G(4)": [ + "Ethernet16/1" + ] + } + }, + "Ethernet128": { + "index": "17,17,17,17,17,17,17,17", + "lanes": "385,386,387,388,389,390,391,392", + "breakout_modes": { + "1x400G[200G,100G,50G,40G,25G,10G]": [ + "Ethernet17/1" + ], + "2x200G[100G,50G,40G,25G,10G]": [ + "Ethernet17/1", + "Ethernet17/5" + ], + "4x100G[50G,40G,25G,10G]": [ + "Ethernet17/1", + "Ethernet17/3", + "Ethernet17/5", + "Ethernet17/7" + ], + "1x100G(4)": [ + "Ethernet17/1" + ] + } + }, + "Ethernet136": { + "index": "18,18,18,18,18,18,18,18", + "lanes": "393,394,395,396,397,398,399,400", + "breakout_modes": { + "1x400G[200G,100G,50G,40G,25G,10G]": [ + "Ethernet18/1" + ], + "2x200G[100G,50G,40G,25G,10G]": [ + "Ethernet18/1", + "Ethernet18/5" + ], + "4x100G[50G,40G,25G,10G]": [ + "Ethernet18/1", + "Ethernet18/3", + "Ethernet18/5", + "Ethernet18/7" + ], + "1x100G(4)": [ + "Ethernet18/1" + ] + } + }, + "Ethernet144": { + "index": "19,19,19,19,19,19,19,19", + "lanes": "401,402,403,404,405,406,407,408", + "breakout_modes": { + "1x400G[200G,100G,50G,40G,25G,10G]": [ + "Ethernet19/1" + ], + "2x200G[100G,50G,40G,25G,10G]": [ + "Ethernet19/1", + "Ethernet19/5" + ], + "4x100G[50G,40G,25G,10G]": [ + "Ethernet19/1", + "Ethernet19/3", + "Ethernet19/5", + "Ethernet19/7" + ], + "1x100G(4)": [ + "Ethernet19/1" + ] + } + }, + "Ethernet152": { + "index": "20,20,20,20,20,20,20,20", + "lanes": "409,410,411,412,413,414,415,416", + "breakout_modes": { + "1x400G[200G,100G,50G,40G,25G,10G]": [ + "Ethernet20/1" + ], + "2x200G[100G,50G,40G,25G,10G]": [ + "Ethernet20/1", + "Ethernet20/5" + ], + "4x100G[50G,40G,25G,10G]": [ + "Ethernet20/1", + "Ethernet20/3", + "Ethernet20/5", + "Ethernet20/7" + ], + "1x100G(4)": [ + "Ethernet20/1" + ] + } + }, + "Ethernet160": { + "index": "21,21,21,21,21,21,21,21", + "lanes": "417,418,419,420,421,422,423,424", + "breakout_modes": { + "1x400G[200G,100G,50G,40G,25G,10G]": [ + "Ethernet21/1" + ], + "2x200G[100G,50G,40G,25G,10G]": [ + "Ethernet21/1", + "Ethernet21/5" + ], + "4x100G[50G,40G,25G,10G]": [ + "Ethernet21/1", + "Ethernet21/3", + "Ethernet21/5", + "Ethernet21/7" + ], + "1x100G(4)": [ + "Ethernet21/1" + ] + } + }, + "Ethernet168": { + "index": "22,22,22,22,22,22,22,22", + "lanes": "425,426,427,428,429,430,431,432", + "breakout_modes": { + "1x400G[200G,100G,50G,40G,25G,10G]": [ + "Ethernet22/1" + ], + "2x200G[100G,50G,40G,25G,10G]": [ + "Ethernet22/1", + "Ethernet22/5" + ], + "4x100G[50G,40G,25G,10G]": [ + "Ethernet22/1", + "Ethernet22/3", + "Ethernet22/5", + "Ethernet22/7" + ], + "1x100G(4)": [ + "Ethernet22/1" + ] + } + }, + "Ethernet176": { + "index": "23,23,23,23,23,23,23,23", + "lanes": "433,434,435,436,437,438,439,440", + "breakout_modes": { + "1x400G[200G,100G,50G,40G,25G,10G]": [ + "Ethernet23/1" + ], + "2x200G[100G,50G,40G,25G,10G]": [ + "Ethernet23/1", + "Ethernet23/5" + ], + "4x100G[50G,40G,25G,10G]": [ + "Ethernet23/1", + "Ethernet23/3", + "Ethernet23/5", + "Ethernet23/7" + ], + "1x100G(4)": [ + "Ethernet23/1" + ] + } + }, + "Ethernet184": { + "index": "24,24,24,24,24,24,24,24", + "lanes": "441,442,443,444,445,446,447,448", + "breakout_modes": { + "1x400G[200G,100G,50G,40G,25G,10G]": [ + "Ethernet24/1" + ], + "2x200G[100G,50G,40G,25G,10G]": [ + "Ethernet24/1", + "Ethernet24/5" + ], + "4x100G[50G,40G,25G,10G]": [ + "Ethernet24/1", + "Ethernet24/3", + "Ethernet24/5", + "Ethernet24/7" + ], + "1x100G(4)": [ + "Ethernet24/1" + ] + } + }, + "Ethernet192": { + "index": "25,25,25,25,25,25,25,25", + "lanes": "449,450,451,452,453,454,455,456", + "breakout_modes": { + "1x400G[200G,100G,50G,40G,25G,10G]": [ + "Ethernet25/1" + ], + "2x200G[100G,50G,40G,25G,10G]": [ + "Ethernet25/1", + "Ethernet25/5" + ], + "4x100G[50G,40G,25G,10G]": [ + "Ethernet25/1", + "Ethernet25/3", + "Ethernet25/5", + "Ethernet25/7" + ], + "1x100G(4)": [ + "Ethernet25/1" + ] + } + }, + "Ethernet200": { + "index": "26,26,26,26,26,26,26,26", + "lanes": "457,458,459,460,461,462,463,464", + "breakout_modes": { + "1x400G[200G,100G,50G,40G,25G,10G]": [ + "Ethernet26/1" + ], + "2x200G[100G,50G,40G,25G,10G]": [ + "Ethernet26/1", + "Ethernet26/5" + ], + "4x100G[50G,40G,25G,10G]": [ + "Ethernet26/1", + "Ethernet26/3", + "Ethernet26/5", + "Ethernet26/7" + ], + "1x100G(4)": [ + "Ethernet26/1" + ] + } + }, + "Ethernet208": { + "index": "27,27,27,27,27,27,27,27", + "lanes": "465,466,467,468,469,470,471,472", + "breakout_modes": { + "1x400G[200G,100G,50G,40G,25G,10G]": [ + "Ethernet27/1" + ], + "2x200G[100G,50G,40G,25G,10G]": [ + "Ethernet27/1", + "Ethernet27/5" + ], + "4x100G[50G,40G,25G,10G]": [ + "Ethernet27/1", + "Ethernet27/3", + "Ethernet27/5", + "Ethernet27/7" + ], + "1x100G(4)": [ + "Ethernet27/1" + ] + } + }, + "Ethernet216": { + "index": "28,28,28,28,28,28,28,28", + "lanes": "473,474,475,476,477,478,479,480", + "breakout_modes": { + "1x400G[200G,100G,50G,40G,25G,10G]": [ + "Ethernet28/1" + ], + "2x200G[100G,50G,40G,25G,10G]": [ + "Ethernet28/1", + "Ethernet28/5" + ], + "4x100G[50G,40G,25G,10G]": [ + "Ethernet28/1", + "Ethernet28/3", + "Ethernet28/5", + "Ethernet28/7" + ], + "1x100G(4)": [ + "Ethernet28/1" + ] + } + }, + "Ethernet224": { + "index": "29,29,29,29,29,29,29,29", + "lanes": "481,482,483,484,485,486,487,488", + "breakout_modes": { + "1x400G[200G,100G,50G,40G,25G,10G]": [ + "Ethernet29/1" + ], + "2x200G[100G,50G,40G,25G,10G]": [ + "Ethernet29/1", + "Ethernet29/5" + ], + "4x100G[50G,40G,25G,10G]": [ + "Ethernet29/1", + "Ethernet29/3", + "Ethernet29/5", + "Ethernet29/7" + ], + "1x100G(4)": [ + "Ethernet29/1" + ] + } + }, + "Ethernet232": { + "index": "30,30,30,30,30,30,30,30", + "lanes": "489,490,491,492,493,494,495,496", + "breakout_modes": { + "1x400G[200G,100G,50G,40G,25G,10G]": [ + "Ethernet30/1" + ], + "2x200G[100G,50G,40G,25G,10G]": [ + "Ethernet30/1", + "Ethernet30/5" + ], + "4x100G[50G,40G,25G,10G]": [ + "Ethernet30/1", + "Ethernet30/3", + "Ethernet30/5", + "Ethernet30/7" + ], + "1x100G(4)": [ + "Ethernet30/1" + ] + } + }, + "Ethernet240": { + "index": "31,31,31,31,31,31,31,31", + "lanes": "497,498,499,500,501,502,503,504", + "breakout_modes": { + "1x400G[200G,100G,50G,40G,25G,10G]": [ + "Ethernet31/1" + ], + "2x200G[100G,50G,40G,25G,10G]": [ + "Ethernet31/1", + "Ethernet31/5" + ], + "4x100G[50G,40G,25G,10G]": [ + "Ethernet31/1", + "Ethernet31/3", + "Ethernet31/5", + "Ethernet31/7" + ], + "1x100G(4)": [ + "Ethernet31/1" + ] + } + }, + "Ethernet248": { + "index": "32,32,32,32,32,32,32,32", + "lanes": "505,506,507,508,509,510,511,512", + "breakout_modes": { + "1x400G[200G,100G,50G,40G,25G,10G]": [ + "Ethernet32/1" + ], + "2x200G[100G,50G,40G,25G,10G]": [ + "Ethernet32/1", + "Ethernet32/5" + ], + "4x100G[50G,40G,25G,10G]": [ + "Ethernet32/1", + "Ethernet32/3", + "Ethernet32/5", + "Ethernet32/7" + ], + "1x100G(4)": [ + "Ethernet32/1" + ] + } + }, + "Ethernet256": { + "index": "33", + "lanes": "513", + "breakout_modes": { + "1x10G": [ + "Ethernet33" + ] + } + } + } +} diff --git a/device/arista/x86_64-arista_7060dx5_32/platform_asic b/device/arista/x86_64-arista_7060dx5_32/platform_asic new file mode 100644 index 000000000000..960467652765 --- /dev/null +++ b/device/arista/x86_64-arista_7060dx5_32/platform_asic @@ -0,0 +1 @@ +broadcom diff --git a/device/arista/x86_64-arista_7060dx5_32/platform_components.json b/device/arista/x86_64-arista_7060dx5_32/platform_components.json new file mode 100644 index 000000000000..26c3bafc31a8 --- /dev/null +++ b/device/arista/x86_64-arista_7060dx5_32/platform_components.json @@ -0,0 +1,12 @@ +{ + "chassis": { + "DCS-7060DX5-32": { + "component": { + "Aboot()": {}, + "Scd(addr=0000:00:18.7)": {}, + "Scd(addr=0000:01:00.0)": {}, + "LorikeetSysCpld(addr=13-0023)": {} + } + } + } +} diff --git a/device/arista/x86_64-arista_7060dx5_32/platform_env.conf b/device/arista/x86_64-arista_7060dx5_32/platform_env.conf new file mode 100644 index 000000000000..dd7cf4fe01c5 --- /dev/null +++ b/device/arista/x86_64-arista_7060dx5_32/platform_env.conf @@ -0,0 +1,2 @@ +SYNCD_SHM_SIZE=512m +is_ltsw_chip=1 diff --git a/device/arista/x86_64-arista_7060dx5_32/platform_reboot b/device/arista/x86_64-arista_7060dx5_32/platform_reboot new file mode 120000 index 000000000000..7f94a49e38b0 --- /dev/null +++ b/device/arista/x86_64-arista_7060dx5_32/platform_reboot @@ -0,0 +1 @@ +../x86_64-arista_common/platform_reboot \ No newline at end of file diff --git a/device/arista/x86_64-arista_7060dx5_32/plugins b/device/arista/x86_64-arista_7060dx5_32/plugins new file mode 120000 index 000000000000..5fbbf98a6284 --- /dev/null +++ b/device/arista/x86_64-arista_7060dx5_32/plugins @@ -0,0 +1 @@ +../x86_64-arista_common/plugins/ \ No newline at end of file diff --git a/device/arista/x86_64-arista_7060dx5_32/pmon_daemon_control.json b/device/arista/x86_64-arista_7060dx5_32/pmon_daemon_control.json new file mode 120000 index 000000000000..51d5ab7b0059 --- /dev/null +++ b/device/arista/x86_64-arista_7060dx5_32/pmon_daemon_control.json @@ -0,0 +1 @@ +../x86_64-arista_common/pmon_daemon_control.json \ No newline at end of file diff --git a/device/arista/x86_64-arista_7060dx5_32/sensors.conf b/device/arista/x86_64-arista_7060dx5_32/sensors.conf new file mode 100644 index 000000000000..ba4e8045c5f7 --- /dev/null +++ b/device/arista/x86_64-arista_7060dx5_32/sensors.conf @@ -0,0 +1,36 @@ +# libsensors configuration file for DCS-7060DX4-32 +# ------------------------------------------------# + +bus "i2c-9" "SCD 0000:00:18.7 SMBus master 0 bus 0" +bus "i2c-29" "SCD 0000:01:00.0 SMBus master 1 bus 0" +bus "i2c-32" "SCD 0000:01:00.0 SMBus master 1 bus 3" +bus "i2c-33" "SCD 0000:01:00.0 SMBus master 1 bus 4" + +chip "max6658-i2c-9-4c" + label temp1 "CPU board temp sensor" + label temp2 "Back-panel temp sensor" + +chip "max6581-i2c-29-4d" + label temp1 "Center Rear" + label temp2 "Switch board right sensor" + label temp3 "Switch board left sensor" + label temp4 "Front-panel temp sensor" + label temp5 "Switch chip diode 1 sensor" + label temp6 "Switch chip diode 2 sensor" + ignore temp7 + ignore temp8 + +chip "pmbus-i2c-32-58" + label temp1 "Power supply 1 hotspot sensor" + label temp2 "Power supply 1 inlet temp sensor" + label temp3 "Power supply 1 exhaust temp sensor" + ignore fan2 + ignore fan3 + +chip "pmbus-i2c-33-58" + label temp1 "Power supply 2 hotspot sensor" + label temp2 "Power supply 2 inlet temp sensor" + label temp3 "Power supply 2 exhaust temp sensor" + ignore fan2 + ignore fan3 + diff --git a/device/arista/x86_64-arista_7060dx5_32/system_health_monitoring_config.json b/device/arista/x86_64-arista_7060dx5_32/system_health_monitoring_config.json new file mode 120000 index 000000000000..1185f771fa8e --- /dev/null +++ b/device/arista/x86_64-arista_7060dx5_32/system_health_monitoring_config.json @@ -0,0 +1 @@ +../x86_64-arista_common/system_health_monitoring_config.json \ No newline at end of file diff --git a/device/arista/x86_64-arista_7060dx5_32/thermal_policy.json b/device/arista/x86_64-arista_7060dx5_32/thermal_policy.json new file mode 120000 index 000000000000..0991dc7f3638 --- /dev/null +++ b/device/arista/x86_64-arista_7060dx5_32/thermal_policy.json @@ -0,0 +1 @@ +../x86_64-arista_common/thermal_policy.json \ No newline at end of file diff --git a/device/arista/x86_64-arista_7060dx5_64s/Arista-7060DX5-64S/hwsku.json b/device/arista/x86_64-arista_7060dx5_64s/Arista-7060DX5-64S/hwsku.json index 7862b2cd4667..56c0816289b2 100644 --- a/device/arista/x86_64-arista_7060dx5_64s/Arista-7060DX5-64S/hwsku.json +++ b/device/arista/x86_64-arista_7060dx5_64s/Arista-7060DX5-64S/hwsku.json @@ -255,6 +255,14 @@ "Ethernet504": { "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G]", "fec": "rs" + }, + "Ethernet512": { + "default_brkout_mode": "1x10G", + "fec": "none" + }, + "Ethernet513": { + "default_brkout_mode": "1x10G", + "fec": "none" } } } diff --git a/device/arista/x86_64-arista_7060dx5_64s/Arista-7060DX5-64S/port_config.ini b/device/arista/x86_64-arista_7060dx5_64s/Arista-7060DX5-64S/port_config.ini index 1aaf907498e2..c7bdcf79be6a 100644 --- a/device/arista/x86_64-arista_7060dx5_64s/Arista-7060DX5-64S/port_config.ini +++ b/device/arista/x86_64-arista_7060dx5_64s/Arista-7060DX5-64S/port_config.ini @@ -63,3 +63,5 @@ Ethernet480 237,238,239,240,241,242,243,244 Ethernet61/1 61 400000 rs Ethernet488 229,230,231,232,233,234,235,236 Ethernet62/1 62 400000 rs Ethernet496 249,250,251,252,253,254,255,256 Ethernet63/1 63 400000 rs Ethernet504 245,246,247,248,249,250,251,252 Ethernet64/1 64 400000 rs +Ethernet512 258 Ethernet65 65 10000 none +Ethernet513 257 Ethernet66 66 10000 none diff --git a/device/arista/x86_64-arista_7060dx5_64s/Arista-7060DX5-64S/th4-a7060dx5-64s.config.bcm b/device/arista/x86_64-arista_7060dx5_64s/Arista-7060DX5-64S/th4-a7060dx5-64s.config.bcm index 12225a79ce74..1d5894498362 100644 --- a/device/arista/x86_64-arista_7060dx5_64s/Arista-7060DX5-64S/th4-a7060dx5-64s.config.bcm +++ b/device/arista/x86_64-arista_7060dx5_64s/Arista-7060DX5-64S/th4-a7060dx5-64s.config.bcm @@ -34,7 +34,7 @@ bcm_device: sai_field_group_auto_prioritize: 1 #l3_intf_vlan_split_egress for MTU at L3IF l3_intf_vlan_split_egress : 1 - + bcm_tunnel_term_compatible_mode: 1 --- device: 0: @@ -1073,6 +1073,14 @@ device: PORT_ID: 258 : PC_PHYS_PORT_ID: 253 + ? + PORT_ID: 152 + : + PC_PHYS_PORT_ID: 257 + ? + PORT_ID: 50 + : + PC_PHYS_PORT_ID: 258 ... --- device: @@ -1085,6 +1093,13 @@ device: ENABLE: 1 SPEED: 10000 NUM_LANES: 1 + ? + PORT_ID: [[50, 50], [152, 152]] + : + ENABLE: 1 + MAX_FRAME_SIZE: 9416 + SPEED: 10000 + NUM_LANES: 1 ? PORT_ID: [[1, 4], [17, 20], @@ -1103,7 +1118,7 @@ device: [238, 241], [255, 258]] : - ENABLE: 1 + ENABLE: 0 SPEED: 400000 NUM_LANES: 8 FEC_MODE: PC_FEC_RS544_2XN diff --git a/device/arista/x86_64-arista_7060dx5_64s/platform.json b/device/arista/x86_64-arista_7060dx5_64s/platform.json index 6442500a35d2..fa89a17687b5 100644 --- a/device/arista/x86_64-arista_7060dx5_64s/platform.json +++ b/device/arista/x86_64-arista_7060dx5_64s/platform.json @@ -49,52 +49,52 @@ ], "thermals": [ { - "name": "Cpu temp sensor" + "name": "Board sensor", + "controllable": false }, { - "name": "CPU board temp sensor" + "name": "TH4 exhaust temp sensor", + "controllable": false }, { - "name": "Back-panel temp sensor" + "name": "Inlet temp sensor", + "controllable": false }, { - "name": "Board sensor" + "name": "CPU board temp sensor", + "controllable": false }, { - "name": "Switch board middle sensor" + "name": "Back panel temp sensor", + "controllable": false }, { - "name": "Switch board left sensor" + "name": "Front panel temp sensor", + "controllable": false }, { - "name": "Front-panel temp sensor" + "name": "Power supply 1 hotspot sensor", + "controllable": false }, { - "name": "Switch chip diode 1 sensor" + "name": "Power supply 1 inlet temp sensor", + "controllable": false }, { - "name": "Switch chip diode 2 sensor" + "name": "Power supply 1 exhaust temp sensor", + "controllable": false }, { - "name": "Front-panel temp sensor" + "name": "Power supply 2 hotspot sensor", + "controllable": false }, { - "name": "Power supply 1 inlet temp sensor" + "name": "Power supply 2 inlet temp sensor", + "controllable": false }, { - "name": "Power supply 1 secondary hotspot sensor" - }, - { - "name": "Power supply 1 primary hotspot sensor" - }, - { - "name": "Power supply 2 inlet temp sensor" - }, - { - "name": "Power supply 2 secondary hotspot sensor" - }, - { - "name": "Power supply 2 primary hotspot sensor" + "name": "Power supply 2 exhaust temp sensor", + "controllable": false } ], "sfps": [ @@ -2154,6 +2154,24 @@ "Ethernet64/8" ] } + }, + "Ethernet512": { + "index": "65", + "lanes": "258", + "breakout_modes": { + "1x10G": [ + "Ethernet65" + ] + } + }, + "Ethernet513": { + "index": "66", + "lanes": "257", + "breakout_modes": { + "1x10G": [ + "Ethernet66" + ] + } } } } diff --git a/device/arista/x86_64-arista_7060px4_32/Arista-7060PX4-C64/th3-a7060px4-32-64x100G.config.bcm b/device/arista/x86_64-arista_7060px4_32/Arista-7060PX4-C64/th3-a7060px4-32-64x100G.config.bcm index c429c28bad68..efa670b477a1 100644 --- a/device/arista/x86_64-arista_7060px4_32/Arista-7060PX4-C64/th3-a7060px4-32-64x100G.config.bcm +++ b/device/arista/x86_64-arista_7060px4_32/Arista-7060PX4-C64/th3-a7060px4-32-64x100G.config.bcm @@ -20,6 +20,8 @@ miim_intr_enable.0=0 module_64ports.0=1 multicast_l2_range.0=511 oversubscribe_mode=1 +sai_tunnel_global_sip_mask_enable=1 +bcm_tunnel_term_compatible_mode=1 parity_correction=1 parity_enable=1 pbmp_xport_xe.0=0x3ffffffffffffffffffffffffffffffffffffffe diff --git a/device/arista/x86_64-arista_7060px4_32/Arista-7060PX4-O32/th3-a7060px4-o32-32x400G.config.bcm b/device/arista/x86_64-arista_7060px4_32/Arista-7060PX4-O32/th3-a7060px4-o32-32x400G.config.bcm index b23b8abf1377..3cd40c229727 100644 --- a/device/arista/x86_64-arista_7060px4_32/Arista-7060PX4-O32/th3-a7060px4-o32-32x400G.config.bcm +++ b/device/arista/x86_64-arista_7060px4_32/Arista-7060PX4-O32/th3-a7060px4-o32-32x400G.config.bcm @@ -20,6 +20,8 @@ miim_intr_enable.0=0 module_64ports.0=1 multicast_l2_range.0=511 oversubscribe_mode=1 +sai_tunnel_global_sip_mask_enable=1 +bcm_tunnel_term_compatible_mode=1 parity_correction=1 parity_enable=1 pbmp_xport_xe.0=0x3ffffffffffffffffffffffffffffffffffffffe diff --git a/device/arista/x86_64-arista_7060px4_32/th3-a7060px4-32-flex.config.bcm b/device/arista/x86_64-arista_7060px4_32/th3-a7060px4-32-flex.config.bcm index b7018cf7c46f..e25d7db00ec6 100644 --- a/device/arista/x86_64-arista_7060px4_32/th3-a7060px4-32-flex.config.bcm +++ b/device/arista/x86_64-arista_7060px4_32/th3-a7060px4-32-flex.config.bcm @@ -16,6 +16,8 @@ miim_intr_enable.0=0 module_64ports.0=1 multicast_l2_range.0=511 oversubscribe_mode=1 +sai_tunnel_global_sip_mask_enable=1 +bcm_tunnel_term_compatible_mode=1 parity_correction=1 parity_enable=1 pbmp_xport_xe.0=0x3ffffffffffffffffffffffffffffffffffffffe diff --git a/device/arista/x86_64-arista_7060px5_64s/Arista-7060PX5-64S/blackhawk.xml b/device/arista/x86_64-arista_7060px5_64s/Arista-7060PX5-64S/blackhawk.xml index 5db2840cef95..b9fe12f1e471 100644 --- a/device/arista/x86_64-arista_7060px5_64s/Arista-7060PX5-64S/blackhawk.xml +++ b/device/arista/x86_64-arista_7060px5_64s/Arista-7060PX5-64S/blackhawk.xml @@ -4,12 +4,6 @@ 0 retimer 1 - - 2,-8,17,0,0 - 0,-8,17,0,0 - - 0,0,1,0,0 - @@ -26,4 +20,23 @@ + + + + + + + + + + + + + + + + + + + diff --git a/device/arista/x86_64-arista_7060px5_64s/sensors.conf b/device/arista/x86_64-arista_7060px5_64s/sensors.conf index e9f43494d6a9..835a10c3cc51 100644 --- a/device/arista/x86_64-arista_7060px5_64s/sensors.conf +++ b/device/arista/x86_64-arista_7060px5_64s/sensors.conf @@ -7,20 +7,15 @@ bus "i2c-23" "SCD 0000:01:00.0 SMBus master 1 bus 4" bus "i2c-24" "SCD 0000:01:00.0 SMBus master 1 bus 5" bus "i2c-107" "SCD 0000:00:18.7 SMBus master 0 bus 0" -chip "max6581-i2c-19-4d" +chip "tmp464-i2c-19-48" label temp1 "Board sensor" label temp2 "TH4 exhaust temp sensor" - label temp3 "Left edge PCB rear temp sensor" - label temp4 "Inlet temp sensor" - ignore temp5 - ignore temp6 - label temp7 "Diode temp sensor 1" - label temp8 "Diode temp sensor 2" + label temp3 "Inlet temp sensor" chip "dps800-i2c-22-58" label temp1 "Power supply 1 hotspot sensor" label temp2 "Power supply 1 inlet temp sensor" - label temp3 "Power supply 1 exhaust temp sensor" + ignore temp3 "Power supply 1 exhaust temp sensor" chip "dps800-i2c-23-58" label temp1 "Power supply 2 hotspot sensor" diff --git a/device/arista/x86_64-arista_7260cx3_64/Arista-7260CX3-C64/config.bcm.j2 b/device/arista/x86_64-arista_7260cx3_64/Arista-7260CX3-C64/config.bcm.j2 index 97040d332ced..ee67a684bf77 100644 --- a/device/arista/x86_64-arista_7260cx3_64/Arista-7260CX3-C64/config.bcm.j2 +++ b/device/arista/x86_64-arista_7260cx3_64/Arista-7260CX3-C64/config.bcm.j2 @@ -14,8 +14,7 @@ {%- set switch_subtype = DEVICE_METADATA['localhost']['subtype'] -%} {%- if 'dualtor' in switch_subtype.lower() %} {%- set IPinIP_sock = -'sai_tunnel_support=1 -sai_tunnel_underlay_route_mode=1 +'sai_tunnel_underlay_route_mode=1 host_as_route_disable=1 l3_ecmp_levels=2' -%} {%- set map_prio = 'sai_remap_prio_on_tnl_egress=1' -%} @@ -1049,5 +1048,6 @@ serdes_preemphasis_116=0x103706 serdes_preemphasis_117=0x133c06 {{ mmu_sock }} +sai_tunnel_support=1 {{ IPinIP_sock }} phy_an_lt_msft=1 diff --git a/device/arista/x86_64-arista_7260cx3_64/Arista-7260CX3-D108C10/config.bcm.j2 b/device/arista/x86_64-arista_7260cx3_64/Arista-7260CX3-D108C10/config.bcm.j2 index 019f556edb8f..9ba820196e68 100644 --- a/device/arista/x86_64-arista_7260cx3_64/Arista-7260CX3-D108C10/config.bcm.j2 +++ b/device/arista/x86_64-arista_7260cx3_64/Arista-7260CX3-D108C10/config.bcm.j2 @@ -6,8 +6,7 @@ {%- set switch_subtype = DEVICE_METADATA['localhost']['subtype'] -%} {%- if 'dualtor' in switch_subtype.lower() %} {%- set IPinIP_sock = -'sai_tunnel_support=1 -sai_tunnel_underlay_route_mode=1 +'sai_tunnel_underlay_route_mode=1 host_as_route_disable=1 l3_ecmp_levels=2' -%} {%- set map_prio = 'sai_remap_prio_on_tnl_egress=1' -%} @@ -956,5 +955,6 @@ serdes_preemphasis_130=0x580c serdes_preemphasis_131=0x580c mmu_init_config="MSFT-TH2-Tier0" +sai_tunnel_support=1 {{ IPinIP_sock }} phy_an_lt_msft=1 diff --git a/device/arista/x86_64-arista_7260cx3_64/Arista-7260CX3-D108C8/config.bcm.j2 b/device/arista/x86_64-arista_7260cx3_64/Arista-7260CX3-D108C8/config.bcm.j2 index 1efa8ef69567..70403df33967 100644 --- a/device/arista/x86_64-arista_7260cx3_64/Arista-7260CX3-D108C8/config.bcm.j2 +++ b/device/arista/x86_64-arista_7260cx3_64/Arista-7260CX3-D108C8/config.bcm.j2 @@ -6,8 +6,7 @@ {%- set switch_subtype = DEVICE_METADATA['localhost']['subtype'] -%} {%- if 'dualtor' in switch_subtype.lower() %} {%- set IPinIP_sock = -'sai_tunnel_support=1 -sai_tunnel_underlay_route_mode=1 +'sai_tunnel_underlay_route_mode=1 host_as_route_disable=1 l3_ecmp_levels=2' -%} {%- set map_prio = 'sai_remap_prio_on_tnl_egress=1' -%} @@ -960,5 +959,6 @@ serdes_preemphasis_130=0x580c serdes_preemphasis_131=0x580c mmu_init_config="MSFT-TH2-Tier0" +sai_tunnel_support=1 {{ IPinIP_sock }} phy_an_lt_msft=1 diff --git a/device/arista/x86_64-arista_7260cx3_64/Arista-7260CX3-Q64/config.bcm.j2 b/device/arista/x86_64-arista_7260cx3_64/Arista-7260CX3-Q64/config.bcm.j2 index de7cac15435a..464796bf4d72 100644 --- a/device/arista/x86_64-arista_7260cx3_64/Arista-7260CX3-Q64/config.bcm.j2 +++ b/device/arista/x86_64-arista_7260cx3_64/Arista-7260CX3-Q64/config.bcm.j2 @@ -14,8 +14,7 @@ {%- set switch_subtype = DEVICE_METADATA['localhost']['subtype'] -%} {%- if 'dualtor' in switch_subtype.lower() %} {%- set IPinIP_sock = -'sai_tunnel_support=1 -sai_tunnel_underlay_route_mode=1 +'sai_tunnel_underlay_route_mode=1 host_as_route_disable=1 l3_ecmp_levels=2' -%} {%- set map_prio = 'sai_remap_prio_on_tnl_egress=1' -%} @@ -1048,5 +1047,6 @@ serdes_preemphasis_116=0x105004 serdes_preemphasis_117=0x105004 {{ mmu_sock }} +sai_tunnel_support=1 {{ IPinIP_sock }} phy_an_lt_msft=1 diff --git a/device/celestica/x86_64-cel_e1031-r0/platform_reboot b/device/celestica/x86_64-cel_e1031-r0/platform_reboot new file mode 100755 index 000000000000..3bcaf6a8af09 --- /dev/null +++ b/device/celestica/x86_64-cel_e1031-r0/platform_reboot @@ -0,0 +1,9 @@ +#!/bin/bash + +declare -r CPLD_SETREG_PATH="/sys/bus/platform/devices/e1031.smc/setreg" + +sync ; sync +umount -fa > /dev/null 2&>1 + +# Board level power cycle +echo "0x0113 0xAA" > ${CPLD_SETREG_PATH} diff --git a/device/celestica/x86_64-cel_e1031-r0/platform_update_reboot_cause b/device/celestica/x86_64-cel_e1031-r0/platform_update_reboot_cause new file mode 100755 index 000000000000..9ffb2129c87f --- /dev/null +++ b/device/celestica/x86_64-cel_e1031-r0/platform_update_reboot_cause @@ -0,0 +1,8 @@ +#!/bin/bash + +REBOOT_USER=$(logname) +REBOOT_TIME=$(date) +declare -r REBOOT_CAUSE_FILE="/host/reboot-cause/reboot-cause.txt" + +echo "User issued 'reboot' with platform-specific command [User: ${REBOOT_USER}, Time: ${REBOOT_TIME}]" > ${REBOOT_CAUSE_FILE} +sync diff --git a/device/common/profiles/th4/gen/BALANCED/buffers_defaults_t0.j2 b/device/common/profiles/th4/gen/BALANCED/buffers_defaults_t0.j2 new file mode 100644 index 000000000000..2bd54b00be50 --- /dev/null +++ b/device/common/profiles/th4/gen/BALANCED/buffers_defaults_t0.j2 @@ -0,0 +1,46 @@ +{%- set default_cable = '5m' %} + +{%- macro generate_port_lists(PORT_ALL) %} + {# Generate list of ports #} + {%- for port_idx in range(0,256,8) %} + {%- if PORT_ALL.append("Ethernet%d" % (port_idx)) %}{%- endif %} + {%- endfor %} +{%- endmacro %} + +{%- macro generate_buffer_pool_and_profiles() %} + "BUFFER_POOL": { + "ingress_lossless_pool": { + "size": "37333333", + "type": "ingress", + "mode": "dynamic", + "xoff": "24000000" + }, + "egress_lossy_pool": { + "size": "34000000", + "type": "egress", + "mode": "dynamic" + }, + "egress_lossless_pool": { + "size": "56000000", + "type": "egress", + "mode": "static" + } + }, + "BUFFER_PROFILE": { + "ingress_lossy_profile": { + "pool":"ingress_lossless_pool", + "size":"0", + "dynamic_th":"3" + }, + "egress_lossless_profile": { + "pool":"egress_lossless_pool", + "size":"1518", + "static_th":"56000000" + }, + "egress_lossy_profile": { + "pool":"egress_lossy_pool", + "size":"1518", + "dynamic_th":"3" + } + }, +{%- endmacro %} diff --git a/device/common/profiles/th4/gen/BALANCED/buffers_defaults_t1.j2 b/device/common/profiles/th4/gen/BALANCED/buffers_defaults_t1.j2 new file mode 100644 index 000000000000..2bd54b00be50 --- /dev/null +++ b/device/common/profiles/th4/gen/BALANCED/buffers_defaults_t1.j2 @@ -0,0 +1,46 @@ +{%- set default_cable = '5m' %} + +{%- macro generate_port_lists(PORT_ALL) %} + {# Generate list of ports #} + {%- for port_idx in range(0,256,8) %} + {%- if PORT_ALL.append("Ethernet%d" % (port_idx)) %}{%- endif %} + {%- endfor %} +{%- endmacro %} + +{%- macro generate_buffer_pool_and_profiles() %} + "BUFFER_POOL": { + "ingress_lossless_pool": { + "size": "37333333", + "type": "ingress", + "mode": "dynamic", + "xoff": "24000000" + }, + "egress_lossy_pool": { + "size": "34000000", + "type": "egress", + "mode": "dynamic" + }, + "egress_lossless_pool": { + "size": "56000000", + "type": "egress", + "mode": "static" + } + }, + "BUFFER_PROFILE": { + "ingress_lossy_profile": { + "pool":"ingress_lossless_pool", + "size":"0", + "dynamic_th":"3" + }, + "egress_lossless_profile": { + "pool":"egress_lossless_pool", + "size":"1518", + "static_th":"56000000" + }, + "egress_lossy_profile": { + "pool":"egress_lossy_pool", + "size":"1518", + "dynamic_th":"3" + } + }, +{%- endmacro %} diff --git a/device/common/profiles/th4/gen/BALANCED/pg_profile_lookup.ini b/device/common/profiles/th4/gen/BALANCED/pg_profile_lookup.ini new file mode 100644 index 000000000000..673df369a9bb --- /dev/null +++ b/device/common/profiles/th4/gen/BALANCED/pg_profile_lookup.ini @@ -0,0 +1,17 @@ +# PG lossless profiles. +# speed cable size xon xoff threshold xon_offset + 10000 5m 1248 2288 35776 0 2288 + 25000 5m 1248 2288 53248 0 2288 + 40000 5m 1248 2288 66560 0 2288 + 50000 5m 1248 2288 90272 0 2288 + 100000 5m 1248 2288 165568 0 2288 + 10000 40m 1248 2288 37024 0 2288 + 25000 40m 1248 2288 53248 0 2288 + 40000 40m 1248 2288 71552 0 2288 + 50000 40m 1248 2288 96096 0 2288 + 100000 40m 1248 2288 177632 0 2288 + 10000 300m 1248 2288 46176 0 2288 + 25000 300m 1248 2288 79040 0 2288 + 40000 300m 1248 2288 108160 0 2288 + 50000 300m 1248 2288 141856 0 2288 + 100000 300m 1248 2288 268736 0 2288 diff --git a/device/dell/x86_64-dell_e3224f-r0/Dell-E3224F/buffers.json.j2 b/device/dell/x86_64-dell_e3224f-r0/Dell-E3224F/buffers.json.j2 new file mode 100644 index 000000000000..1083a6210fc9 --- /dev/null +++ b/device/dell/x86_64-dell_e3224f-r0/Dell-E3224F/buffers.json.j2 @@ -0,0 +1,2 @@ +{%- set default_topo = 't0' %} +{%- include 'buffers_config.j2' %} diff --git a/device/dell/x86_64-dell_e3224f-r0/Dell-E3224F/buffers_defaults_t0.j2 b/device/dell/x86_64-dell_e3224f-r0/Dell-E3224F/buffers_defaults_t0.j2 new file mode 100644 index 000000000000..e26d7cdf1c34 --- /dev/null +++ b/device/dell/x86_64-dell_e3224f-r0/Dell-E3224F/buffers_defaults_t0.j2 @@ -0,0 +1,41 @@ +{%- set default_cable = '5m' %} + +{%- macro generate_port_lists(PORT_ALL) %} + {# Generate list of ports #} + {% for port_idx in range(0,24) %} + {% if PORT_ALL.append("Ethernet%d" % (port_idx * 4)) %}{% endif %} + {% endfor %} +{%- endmacro %} + +{%- macro generate_buffer_pool_and_profiles() %} + "BUFFER_POOL": { + "ingress_lossless_pool": { + "size": "8192000", + "type": "ingress", + "mode": "dynamic", + "xoff": "196608" + }, + "egress_lossless_pool": { + "size": "8388608", + "type": "egress", + "mode": "static" + } + }, + "BUFFER_PROFILE": { + "ingress_lossy_profile": { + "pool":"[BUFFER_POOL|ingress_lossless_pool]", + "size":"0", + "dynamic_th":"3" + }, + "egress_lossless_profile": { + "pool":"[BUFFER_POOL|egress_lossless_pool]", + "size":"0", + "static_th":"8388608" + }, + "egress_lossy_profile": { + "pool":"[BUFFER_POOL|egress_lossless_pool]", + "size":"1518", + "dynamic_th":"3" + } + }, +{%- endmacro %} diff --git a/device/dell/x86_64-dell_e3224f-r0/Dell-E3224F/buffers_defaults_t1.j2 b/device/dell/x86_64-dell_e3224f-r0/Dell-E3224F/buffers_defaults_t1.j2 new file mode 100644 index 000000000000..c41501e4fb29 --- /dev/null +++ b/device/dell/x86_64-dell_e3224f-r0/Dell-E3224F/buffers_defaults_t1.j2 @@ -0,0 +1,41 @@ +{%- set default_cable = '300m' %} + +{%- macro generate_port_lists(PORT_ALL) %} + {# Generate list of ports #} + {% for port_idx in range(0,24) %} + {% if PORT_ALL.append("Ethernet%d" % (port_idx * 4)) %}{% endif %} + {% endfor %} +{%- endmacro %} + +{%- macro generate_buffer_pool_and_profiles() %} + "BUFFER_POOL": { + "ingress_lossless_pool": { + "size": "8192000", + "type": "ingress", + "mode": "dynamic", + "xoff": "196608" + }, + "egress_lossless_pool": { + "size": "8388608", + "type": "egress", + "mode": "static" + } + }, + "BUFFER_PROFILE": { + "ingress_lossy_profile": { + "pool":"[BUFFER_POOL|ingress_lossless_pool]", + "size":"0", + "dynamic_th":"3" + }, + "egress_lossless_profile": { + "pool":"[BUFFER_POOL|egress_lossless_pool]", + "size":"0", + "static_th":"8388608" + }, + "egress_lossy_profile": { + "pool":"[BUFFER_POOL|egress_lossless_pool]", + "size":"1518", + "dynamic_th":"3" + } + }, +{%- endmacro %} diff --git a/device/dell/x86_64-dell_e3224f-r0/Dell-E3224F/copp_capabilities_config.j2 b/device/dell/x86_64-dell_e3224f-r0/Dell-E3224F/copp_capabilities_config.j2 new file mode 100644 index 000000000000..ba28f2410393 --- /dev/null +++ b/device/dell/x86_64-dell_e3224f-r0/Dell-E3224F/copp_capabilities_config.j2 @@ -0,0 +1,3 @@ +{ + "copp_rx_rate":15000 +} diff --git a/device/dell/x86_64-dell_e3224f-r0/Dell-E3224F/copp_platform_config.j2 b/device/dell/x86_64-dell_e3224f-r0/Dell-E3224F/copp_platform_config.j2 new file mode 100644 index 000000000000..35c0066dc59e --- /dev/null +++ b/device/dell/x86_64-dell_e3224f-r0/Dell-E3224F/copp_platform_config.j2 @@ -0,0 +1,145 @@ +{ + "COPP_GROUP": { + "copp-system-lacp": { + "cir":"250", + "cbs":"250" + }, + "copp-system-udld": { + "cir":"250", + "cbs":"250" + }, + "copp-system-stp": { + "cir":"8000", + "cbs":"8000" + }, + "copp-system-bfd": { + "cir":"750", + "cbs":"750" + }, + "copp-system-lldp": { + "cir":"250", + "cbs":"250" + }, + "copp-system-vrrp": { + "cir":"250", + "cbs":"250" + }, + "copp-system-iccp": { + "cir":"2500", + "cbs":"2500" + }, + "copp-system-ospf": { + "cir":"2500", + "cbs":"2500" + }, + "copp-system-bgp": { + "cir":"5000", + "cbs":"5000" + }, + "copp-system-pim": { + "cir":"2500", + "cbs":"2500" + }, + "copp-system-igmp": { + "cir":"1000", + "cbs":"1000" + }, + "copp-system-suppress": { + "cir":"1500", + "cbs":"1500" + }, + "copp-system-arp": { + "cir":"1500", + "cbs":"1500" + }, + "copp-system-dhcp": { + "cir":"150", + "cbs":"150" + }, + "copp-system-icmp": { + "cir":"500", + "cbs":"500" + }, + "copp-system-ip2me": { + "cir":"3000", + "cbs":"3000" + }, + "copp-system-subnet": { + "cir":"1000", + "cbs":"1000" + }, + "copp-system-mtu": { + "cir":"250", + "cbs":"250" + }, + "copp-system-sflow": { + "cir":"4000", + "cbs":"4000" + } + }, + "SCHEDULER": { + "copp-scheduler-policy@23": { + "pir": "250" + }, + "copp-scheduler-policy@22": { + "pir": "250" + }, + "copp-scheduler-policy@21": { + "pir": "8000" + }, + "copp-scheduler-policy@20": { + "pir": "750" + }, + "copp-scheduler-policy@19": { + "pir": "2500" + }, + "copp-scheduler-policy@18": { + "pir": "250" + }, + "copp-scheduler-policy@17": { + "pir": "250" + }, + "copp-scheduler-policy@16": { + "pir": "2500" + }, + "copp-scheduler-policy@15": { + "pir": "2500" + }, + "copp-scheduler-policy@14": { + "pir": "5000" + }, + "copp-scheduler-policy@13": { + "pir": "2500" + }, + "copp-scheduler-policy@12": { + "pir": "1000" + }, + "copp-scheduler-policy@11": { + "pir": "1500" + }, + "copp-scheduler-policy@10": { + "pir": "1500" + }, + "copp-scheduler-policy@9": { + "pir": "150" + }, + "copp-scheduler-policy@8": { + "pir": "500" + }, + "copp-scheduler-policy@7": { + "pir": "3000" + }, + "copp-scheduler-policy@6": { + "pir": "1000" + }, + "copp-scheduler-policy@4": { + "pir": "250" + }, + "copp-scheduler-policy@3": { + "pir": "4000" + }, + "copp-scheduler-policy@1": { + "pir": "100" + } + } +} diff --git a/device/dell/x86_64-dell_e3224f-r0/Dell-E3224F/custom_led.bin b/device/dell/x86_64-dell_e3224f-r0/Dell-E3224F/custom_led.bin new file mode 100644 index 000000000000..631b4712fa28 Binary files /dev/null and b/device/dell/x86_64-dell_e3224f-r0/Dell-E3224F/custom_led.bin differ diff --git a/device/dell/x86_64-dell_e3224f-r0/Dell-E3224F/hx5-e3224f-24x1G+4x10G.config.bcm b/device/dell/x86_64-dell_e3224f-r0/Dell-E3224F/hx5-e3224f-24x1G+4x10G.config.bcm new file mode 100644 index 000000000000..f3dfd20652dc --- /dev/null +++ b/device/dell/x86_64-dell_e3224f-r0/Dell-E3224F/hx5-e3224f-24x1G+4x10G.config.bcm @@ -0,0 +1,157 @@ +bcm_num_cos=8 +bcm_stat_interval=2000000 +bcm_tunnel_term_compatible_mode=1 +cdma_timeout_usec=3000000 +flow_init_mode=0 +ifa_enable=0 +ifp_inports_support_enable=1 +ipv6_lpm_128b_enable=0x1 +l2xmsg_mode=1 + +#Default L3 profile + +l2_mem_entries=32768 +l3_alpm_enable=2 +l3_alpm_ipv6_128b_bkt_rsvd=1 +l3_max_ecmp_mode=1 +l3_mem_entries=16348 +lpm_scaling_enable=0 +memlist_enable=1 +reglist_enable=1 +scache_filename=/tmp/brcm_bcm_scache +schan_intr_enable=0 +stable_size=0x5500000 +tdma_timeout_usec=3000000 + +pfc_deadlock_seq_control=1 + +#Port and PHY configs + +core_clock_frequency=668 +pbmp_xport_xe=0x1ffffffe +port_gmii_mode_33=1 +port_gmii_mode_17=1 +port_gmii_mode_1=1 +portmap_1=1:1 +portmap_2=2:1 +portmap_3=3:1 +portmap_4=4:1 +portmap_5=5:1 +portmap_6=6:1 +portmap_7=7:1 +portmap_8=8:1 +portmap_9=9:1 +portmap_10=10:1 +portmap_11=11:1 +portmap_12=12:1 +portmap_13=13:1 +portmap_14=14:1 +portmap_15=15:1 +portmap_16=16:1 +portmap_17=17:1 +portmap_18=18:1 +portmap_19=19:1 +portmap_20=20:1 +portmap_21=21:1 +portmap_22=22:1 +portmap_23=23:1 +portmap_24=24:1 +portmap_25=64:10 +portmap_26=63:10 +portmap_27=62:10 +portmap_28=61:10 +portmap_29=69:100 +portmap_33=73:100 +phy_chain_tx_lane_map_physical{33.0}=0x2301 +phy_chain_rx_lane_map_physical{33.0}=0x2301 +phy_port_primary_and_offset_1=0x0100 +phy_port_primary_and_offset_2=0x0101 +phy_port_primary_and_offset_3=0x0102 +phy_port_primary_and_offset_4=0x0103 +phy_port_primary_and_offset_5=0x0104 +phy_port_primary_and_offset_6=0x0105 +phy_port_primary_and_offset_7=0x0106 +phy_port_primary_and_offset_8=0x0107 +phy_port_primary_and_offset_9=0x0900 +phy_port_primary_and_offset_10=0x0901 +phy_port_primary_and_offset_11=0x0902 +phy_port_primary_and_offset_12=0x0903 +phy_port_primary_and_offset_13=0x0904 +phy_port_primary_and_offset_14=0x0905 +phy_port_primary_and_offset_15=0x0906 +phy_port_primary_and_offset_16=0x0907 +phy_port_primary_and_offset_17=0x1200 +phy_port_primary_and_offset_18=0x1201 +phy_port_primary_and_offset_19=0x1202 +phy_port_primary_and_offset_20=0x1203 +phy_port_primary_and_offset_21=0x1204 +phy_port_primary_and_offset_22=0x1205 +phy_port_primary_and_offset_23=0x1206 +phy_port_primary_and_offset_24=0x1207 +port_phy_addr_1=0x0 +port_phy_addr_2=0x1 +port_phy_addr_3=0x2 +port_phy_addr_4=0x3 +port_phy_addr_5=0x4 +port_phy_addr_6=0x5 +port_phy_addr_7=0x6 +port_phy_addr_8=0x7 +port_phy_addr_9=0x9 +port_phy_addr_10=0xa +port_phy_addr_11=0xb +port_phy_addr_12=0xc +port_phy_addr_13=0xd +port_phy_addr_14=0xe +port_phy_addr_15=0xf +port_phy_addr_16=0x10 +port_phy_addr_17=0x12 +port_phy_addr_18=0x13 +port_phy_addr_19=0x14 +port_phy_addr_20=0x15 +port_phy_addr_21=0x16 +port_phy_addr_22=0x17 +port_phy_addr_23=0x18 +port_phy_addr_24=0x19 +port_phy_addr_25=0x20 +port_phy_addr_26=0x21 +port_phy_addr_27=0x22 +port_phy_addr_28=0x23 +phy_force_firmware_load_26=0x01 +phy_force_firmware_load_27=0x01 +phy_force_firmware_load_28=0x01 +phy_pcs_repeater_25=0x01 +phy_pcs_repeater_26=0x01 +phy_pcs_repeater_27=0x01 +phy_pcs_repeater_28=0x01 +phy_fiber_pref_ge=1 +phy_automedium_ge=0 +dport_map_port_1=8 +dport_map_port_2=7 +dport_map_port_3=6 +dport_map_port_4=5 +dport_map_port_5=4 +dport_map_port_6=3 +dport_map_port_7=2 +dport_map_port_8=1 +dport_map_port_9=16 +dport_map_port_10=15 +dport_map_port_11=14 +dport_map_port_12=13 +dport_map_port_13=12 +dport_map_port_14=11 +dport_map_port_15=10 +dport_map_port_16=9 +dport_map_port_17=24 +dport_map_port_18=23 +dport_map_port_19=22 +dport_map_port_20=21 +dport_map_port_21=20 +dport_map_port_22=19 +dport_map_port_23=18 +dport_map_port_24=17 +dport_map_port_25=25 +dport_map_port_26=26 +dport_map_port_27=27 +dport_map_port_28=28 + +sai_preinit_cmd_file=/usr/share/sonic/hwsku/sai_preinit_cmd.soc diff --git a/device/dell/x86_64-dell_e3224f-r0/Dell-E3224F/linkscan_led_fw.bin b/device/dell/x86_64-dell_e3224f-r0/Dell-E3224F/linkscan_led_fw.bin new file mode 100644 index 000000000000..e86cdc1ef647 Binary files /dev/null and b/device/dell/x86_64-dell_e3224f-r0/Dell-E3224F/linkscan_led_fw.bin differ diff --git a/device/dell/x86_64-dell_e3224f-r0/Dell-E3224F/pg_profile_lookup.ini b/device/dell/x86_64-dell_e3224f-r0/Dell-E3224F/pg_profile_lookup.ini new file mode 100644 index 000000000000..6d91d03ae684 --- /dev/null +++ b/device/dell/x86_64-dell_e3224f-r0/Dell-E3224F/pg_profile_lookup.ini @@ -0,0 +1,17 @@ +# PG lossless profiles. +# speed cable size xon xoff threshold xon_offset + 10000 5m 9427 0 50176 1 3584 + 25000 5m 9427 0 50176 1 3584 + 40000 5m 9427 0 50176 1 3584 + 50000 5m 9427 0 50176 1 3584 + 100000 5m 9427 0 50176 1 3584 + 10000 40m 9427 0 50176 1 3584 + 25000 40m 9427 0 50176 1 3584 + 40000 40m 9427 0 50176 1 3584 + 50000 40m 9427 0 50176 1 3584 + 100000 40m 9427 0 50176 1 3584 + 10000 300m 9427 0 50176 1 3584 + 25000 300m 9427 0 50176 1 3584 + 40000 300m 9427 0 50176 1 3584 + 50000 300m 9427 0 50176 1 3584 + 100000 300m 9427 0 50176 1 3584 diff --git a/device/dell/x86_64-dell_e3224f-r0/Dell-E3224F/port_config.ini b/device/dell/x86_64-dell_e3224f-r0/Dell-E3224F/port_config.ini new file mode 100644 index 000000000000..48fe0d9e2720 --- /dev/null +++ b/device/dell/x86_64-dell_e3224f-r0/Dell-E3224F/port_config.ini @@ -0,0 +1,31 @@ +# name lanes alias index speed autoneg +Ethernet0 8 oneGigE1/1 1 1000 1 +Ethernet1 7 oneGigE1/2 2 1000 1 +Ethernet2 6 oneGigE1/3 3 1000 1 +Ethernet3 5 oneGigE1/4 4 1000 1 +Ethernet4 4 oneGigE1/5 5 1000 1 +Ethernet5 3 oneGigE1/6 6 1000 1 +Ethernet6 2 oneGigE1/7 7 1000 1 +Ethernet7 1 oneGigE1/8 8 1000 1 +Ethernet8 16 oneGigE1/9 9 1000 1 +Ethernet9 15 oneGigE1/10 10 1000 1 +Ethernet10 14 oneGigE1/11 11 1000 1 +Ethernet11 13 oneGigE1/12 12 1000 1 +Ethernet12 12 oneGigE1/13 13 1000 1 +Ethernet13 11 oneGigE1/14 14 1000 1 +Ethernet14 10 oneGigE1/15 15 1000 1 +Ethernet15 9 oneGigE1/16 16 1000 1 +Ethernet16 24 oneGigE1/17 17 1000 1 +Ethernet17 23 oneGigE1/18 18 1000 1 +Ethernet18 22 oneGigE1/19 19 1000 1 +Ethernet19 21 oneGigE1/20 20 1000 1 +Ethernet20 20 oneGigE1/21 21 1000 1 +Ethernet21 19 oneGigE1/22 22 1000 1 +Ethernet22 18 oneGigE1/23 23 1000 1 +Ethernet23 17 oneGigE1/24 24 1000 1 +Ethernet24 64 tenGigE1/25 25 10000 0 +Ethernet25 63 tenGigE1/26 26 10000 0 +Ethernet26 62 tenGigE1/27 27 10000 0 +Ethernet27 61 tenGigE1/28 28 10000 0 +Ethernet28 69,70,71,72 hundredGigE1/29 29 100000 0 +Ethernet32 73,74,75,76 hundredGigE1/30 30 100000 0 diff --git a/device/dell/x86_64-dell_e3224f-r0/Dell-E3224F/qos.json.j2 b/device/dell/x86_64-dell_e3224f-r0/Dell-E3224F/qos.json.j2 new file mode 100644 index 000000000000..ee67c6e26221 --- /dev/null +++ b/device/dell/x86_64-dell_e3224f-r0/Dell-E3224F/qos.json.j2 @@ -0,0 +1 @@ +{%- include 'qos_config_t1.j2' %} diff --git a/device/dell/x86_64-dell_e3224f-r0/Dell-E3224F/qos_config_t1.j2 b/device/dell/x86_64-dell_e3224f-r0/Dell-E3224F/qos_config_t1.j2 new file mode 100644 index 000000000000..5fe5324a85c1 --- /dev/null +++ b/device/dell/x86_64-dell_e3224f-r0/Dell-E3224F/qos_config_t1.j2 @@ -0,0 +1,175 @@ +{%- set PORT_ALL = [] %} +{%- for port in PORT %} + {%- if PORT_ALL.append(port) %}{% endif %} +{%- endfor %} +{%- if PORT_ALL | sort_by_port_index %}{% endif %} + +{%- set port_names_list_all = [] %} +{%- for port in PORT_ALL %} + {%- if port_names_list_all.append(port) %}{% endif %} +{%- endfor %} +{%- set port_names_all = port_names_list_all | join(',') -%} + + +{%- set PORT_ACTIVE = [] %} +{%- if DEVICE_NEIGHBOR is not defined %} + {%- set PORT_ACTIVE = PORT_ALL %} +{%- else %} + {%- for port in DEVICE_NEIGHBOR.keys() %} + {%- if PORT_ACTIVE.append(port) %}{%- endif %} + {%- endfor %} +{%- endif %} +{%- if PORT_ACTIVE | sort_by_port_index %}{% endif %} + +{%- set port_names_list_active = [] %} +{%- for port in PORT_ACTIVE %} + {%- if port_names_list_active.append(port) %}{%- endif %} +{%- endfor %} +{%- set port_names_active = port_names_list_active | join(',') -%} + + +{%- set pfc_to_pg_map_supported_asics = ['mellanox', 'barefoot', 'marvell'] -%} + + +{ +{% if generate_tc_to_pg_map is defined %} + {{- generate_tc_to_pg_map() }} +{% else %} + "TC_TO_PRIORITY_GROUP_MAP": { + "AZURE": { + "0": "0", + "1": "0", + "2": "0", + "3": "3", + "4": "4", + "5": "0", + "6": "0", + "7": "7" + } + }, +{% endif %} + "MAP_PFC_PRIORITY_TO_QUEUE": { + "AZURE": { + "0": "0", + "1": "1", + "2": "2", + "3": "3", + "4": "4", + "5": "5", + "6": "6", + "7": "7" + } + }, + "TC_TO_QUEUE_MAP": { + "AZURE": { + "0": "0", + "1": "1", + "2": "2", + "3": "3", + "4": "4", + "5": "5", + "6": "6", + "7": "7" + } + }, + "DSCP_TO_TC_MAP": { + "AZURE": { + "0" : "1", + "1" : "1", + "2" : "1", + "3" : "3", + "4" : "4", + "5" : "2", + "6" : "1", + "7" : "1", + "8" : "0", + "9" : "1", + "10": "1", + "11": "1", + "12": "1", + "13": "1", + "14": "1", + "15": "1", + "16": "1", + "17": "1", + "18": "1", + "19": "1", + "20": "1", + "21": "1", + "22": "1", + "23": "1", + "24": "1", + "25": "1", + "26": "1", + "27": "1", + "28": "1", + "29": "1", + "30": "1", + "31": "1", + "32": "1", + "33": "1", + "34": "1", + "35": "1", + "36": "1", + "37": "1", + "38": "1", + "39": "1", + "40": "1", + "41": "1", + "42": "1", + "43": "1", + "44": "1", + "45": "1", + "46": "5", + "47": "1", + "48": "6", + "49": "1", + "50": "1", + "51": "1", + "52": "1", + "53": "1", + "54": "1", + "55": "1", + "56": "1", + "57": "1", + "58": "1", + "59": "1", + "60": "1", + "61": "1", + "62": "1", + "63": "1" + } + }, + "SCHEDULER": { + "scheduler.0": { + "type" : "DWRR", + "weight": "14" + }, + "scheduler.1": { + "type" : "DWRR", + "weight": "15" + } + }, +{% if asic_type in pfc_to_pg_map_supported_asics %} + "PFC_PRIORITY_TO_PRIORITY_GROUP_MAP": { + "AZURE": { + "3": "3", + "4": "4" + } + }, +{% endif %} + "PORT_QOS_MAP": { +{% for port in PORT_ACTIVE %} + "{{ port }}": { + "dscp_to_tc_map" : "[DSCP_TO_TC_MAP|AZURE]", + "tc_to_queue_map" : "[TC_TO_QUEUE_MAP|AZURE]", + "tc_to_pg_map" : "[TC_TO_PRIORITY_GROUP_MAP|AZURE]", + "pfc_to_queue_map": "[MAP_PFC_PRIORITY_TO_QUEUE|AZURE]", +{% if asic_type in pfc_to_pg_map_supported_asics %} + "pfc_to_pg_map" : "[PFC_PRIORITY_TO_PRIORITY_GROUP_MAP|AZURE]", +{% endif %} + "pfc_enable" : "3,4" + }{% if not loop.last %},{% endif %} +{% endfor %} + } +} diff --git a/device/dell/x86_64-dell_e3224f-r0/Dell-E3224F/sai.profile b/device/dell/x86_64-dell_e3224f-r0/Dell-E3224F/sai.profile new file mode 100644 index 000000000000..7725e59fcc0f --- /dev/null +++ b/device/dell/x86_64-dell_e3224f-r0/Dell-E3224F/sai.profile @@ -0,0 +1 @@ +SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/hx5-e3224f-24x1G+4x10G.config.bcm diff --git a/device/dell/x86_64-dell_e3224f-r0/Dell-E3224F/sai_preinit_cmd.soc b/device/dell/x86_64-dell_e3224f-r0/Dell-E3224F/sai_preinit_cmd.soc new file mode 100644 index 000000000000..4d62900f898f --- /dev/null +++ b/device/dell/x86_64-dell_e3224f-r0/Dell-E3224F/sai_preinit_cmd.soc @@ -0,0 +1,2 @@ +m0 load 0 0x0 /usr/share/sonic/hwsku/linkscan_led_fw.bin +m0 load 0 0x3800 /usr/share/sonic/hwsku/custom_led.bin diff --git a/device/dell/x86_64-dell_e3224f-r0/default_sku b/device/dell/x86_64-dell_e3224f-r0/default_sku new file mode 100644 index 000000000000..1157285f3a34 --- /dev/null +++ b/device/dell/x86_64-dell_e3224f-r0/default_sku @@ -0,0 +1 @@ +Dell-E3224F t1 diff --git a/device/dell/x86_64-dell_e3224f-r0/init_cfg.json b/device/dell/x86_64-dell_e3224f-r0/init_cfg.json new file mode 100644 index 000000000000..dc933239006c --- /dev/null +++ b/device/dell/x86_64-dell_e3224f-r0/init_cfg.json @@ -0,0 +1,13 @@ +{ + "FEATURE": { + "tam": { + "state": "disabled" + }, + "telemetry": { + "state": "disabled" + }, + "nat": { + "state": "disabled" + } + } +} diff --git a/device/dell/x86_64-dell_e3224f-r0/installer.conf b/device/dell/x86_64-dell_e3224f-r0/installer.conf new file mode 100644 index 000000000000..d67012ee4f7c --- /dev/null +++ b/device/dell/x86_64-dell_e3224f-r0/installer.conf @@ -0,0 +1,4 @@ +CONSOLE_PORT=0x3f8 +CONSOLE_DEV=0 +VAR_LOG_SIZE=512 +ONIE_PLATFORM_EXTRA_CMDLINE_LINUX="intel_iommu=off irqfixup" diff --git a/device/dell/x86_64-dell_e3224f-r0/led_proc_init.soc b/device/dell/x86_64-dell_e3224f-r0/led_proc_init.soc new file mode 100644 index 000000000000..841e4493c2f2 --- /dev/null +++ b/device/dell/x86_64-dell_e3224f-r0/led_proc_init.soc @@ -0,0 +1,7 @@ +# LED microprocessor initialization for Dell E3224F +# +# +#Led0 +#led auto on +m0 load 0 0x3800 /usr/share/sonic/hwsku/custom_led.bin +led start diff --git a/device/dell/x86_64-dell_e3224f-r0/platform.json b/device/dell/x86_64-dell_e3224f-r0/platform.json new file mode 100644 index 000000000000..9a3a631469f6 --- /dev/null +++ b/device/dell/x86_64-dell_e3224f-r0/platform.json @@ -0,0 +1,281 @@ +{ + "chassis": { + "name": "E3224F-ON", + "status_led": { + "controllable": true, + "colors": ["green", "blink_green", "yellow", "blink_yellow"] + }, + "thermal_manager" : false, + "components": [ + { + "name": "BIOS" + }, + { + "name": "CPU CPLD" + }, + { + "name": "SYS CPLD" + }, + { + "name": "PORT CPLD" + } + ], + "fans": [ + { + "name": "FanTray1-Fan1", + "speed": { + "controllable":false + }, + "status_led": { + "available": false + } + }, + { + "name": "FanTray2-Fan1", + "speed": { + "controllable":false + }, + "status_led": { + "available": false + } + }, + { + "name": "FanTray3-Fan1", + "speed": { + "controllable":false + }, + "status_led": { + "available": false + } + } + ], + "fan_drawers":[ + { + "name": "FanTray1", + "status_led": { + "controllable": true, + "colors": ["off", "green", "yellow"] + }, + "fans": [ + { + "name": "FanTray1-Fan1", + "speed": { + "controllable":false + }, + "status_led": { + "available": false + } + } + ] + }, + { + "name": "FanTray2", + "status_led": { + "controllable": true, + "colors": ["off", "green", "yellow"] + }, + "fans": [ + { + "name": "FanTray2-Fan1", + "speed": { + "controllable":false + }, + "status_led": { + "available": false + } + } + ] + }, + { + "name": "FanTray3", + "status_led": { + "controllable": true, + "colors": ["off", "green", "yellow"] + }, + "fans": [ + { + "name": "FanTray3-Fan1", + "speed": { + "controllable":false + }, + "status_led": { + "available": false + } + } + ] + } + ], + "psus": [ + { + "name": "PSU1", + "status_led": { + "controllable": false + }, + "fans": [ + { + "name": "PSU1 Fan", + "speed": { + "controllable": false + }, + "status_led": { + "available": false + } + } + ] + }, + { + "name": "PSU2", + "status_led": { + "controllable": false + }, + "fans": [ + { + "name": "PSU2 Fan", + "speed": { + "controllable": false + }, + "status_led": { + "available": false + } + } + ] + } + ], + "thermals": [ + { + "name": "Front Panel PHY Temperature", + "controllable": false, + "low-crit-threshold": false, + "high-crit-threshold": false, + "minimum-recorded": false, + "maximum-recorded": false + }, + { + "name": "Middle Fan Tray Temperature", + "controllable": false, + "low-crit-threshold": false, + "high-crit-threshold": false, + "minimum-recorded": false, + "maximum-recorded": false + }, + { + "name": "Near Front Panel Temperature", + "controllable": false, + "low-crit-threshold": false, + "high-crit-threshold": false, + "minimum-recorded": false, + "maximum-recorded": false + }, + { + "name": "Switch Near Temperature", + "controllable": false, + "low-crit-threshold": false, + "high-crit-threshold": false, + "minimum-recorded": false, + "maximum-recorded": false + }, + { + "name": "Switch Rear Temperature", + "controllable": false, + "low-crit-threshold": false, + "high-crit-threshold": false, + "minimum-recorded": false, + "maximum-recorded": false + } + ], + "modules": [], + "sfps": [ + { + "name": "SFP" + }, + { + "name": "SFP" + }, + { + "name": "SFP" + }, + { + "name": "SFP" + }, + { + "name": "SFP" + }, + { + "name": "SFP" + }, + { + "name": "SFP" + }, + { + "name": "SFP" + }, + { + "name": "SFP" + }, + { + "name": "SFP" + }, + { + "name": "SFP" + }, + { + "name": "SFP" + }, + { + "name": "SFP" + }, + { + "name": "SFP" + }, + { + "name": "SFP" + }, + { + "name": "SFP" + }, + { + "name": "SFP" + }, + { + "name": "SFP" + }, + { + "name": "SFP" + }, + { + "name": "SFP" + }, + { + "name": "SFP" + }, + { + "name": "SFP" + }, + { + "name": "SFP" + }, + { + "name": "SFP" + }, + { + "name": "SFP/SFP+/SFP28" + }, + { + "name": "SFP/SFP+/SFP28" + }, + { + "name": "SFP/SFP+/SFP28" + }, + { + "name": "SFP/SFP+/SFP28" + }, + { + "name": "QSFP or later" + }, + { + "name": "QSFP or later" + } + ] + }, + "interfaces": {} +} diff --git a/device/dell/x86_64-dell_e3224f-r0/platform_asic b/device/dell/x86_64-dell_e3224f-r0/platform_asic new file mode 100644 index 000000000000..960467652765 --- /dev/null +++ b/device/dell/x86_64-dell_e3224f-r0/platform_asic @@ -0,0 +1 @@ +broadcom diff --git a/device/dell/x86_64-dell_e3224f-r0/plugins/eeprom.py b/device/dell/x86_64-dell_e3224f-r0/plugins/eeprom.py new file mode 100644 index 000000000000..be6f1952f03a --- /dev/null +++ b/device/dell/x86_64-dell_e3224f-r0/plugins/eeprom.py @@ -0,0 +1,22 @@ +#!/usr/bin/python3 + +############################################################################# +# Dell E3224F +# +# Platform and model specific eeprom subclass, inherits from the base class, +# and provides the followings: +# - the eeprom format definition +# - specific encoder/decoder if there is special need +############################################################################# + +try: + from sonic_eeprom import eeprom_tlvinfo +except ImportError as e: + raise ImportError (str(e) + "- required module not found") + + +class board(eeprom_tlvinfo.TlvInfoDecoder): + + def __init__(self, name, path, cpld_root, ro): + self.eeprom_path = "/sys/class/i2c-adapter/i2c-2/2-0050/eeprom" + super(board, self).__init__(self.eeprom_path, 0, '', True) diff --git a/device/dell/x86_64-dell_e3224f-r0/plugins/fanutil.py b/device/dell/x86_64-dell_e3224f-r0/plugins/fanutil.py new file mode 100644 index 000000000000..73d171e857cc --- /dev/null +++ b/device/dell/x86_64-dell_e3224f-r0/plugins/fanutil.py @@ -0,0 +1,71 @@ +# +# fanutil.py +# Platform-specific FAN status interface for SONiC +# + +import sys +from sonic_py_common.general import getstatusoutput_noshell + +SENSORS_CMD = ["docker", "exec", "-i", "pmon", "/usr/bin/sensors"] +DOCKER_SENSORS_CMD = "/usr/bin/sensors" + + +try: + from sonic_fan.fan_base import FanBase +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + + +class FanUtil(FanBase): + """Platform-specific FanUtil class""" + _fan_mapping = { + 1 : '0', + 2 : '1', + 3 : '2' + } + + def __init__(self): + FanBase.__init__(self) + + def isDockerEnv(self): + num_docker = open('/proc/self/cgroup', 'r').read().count(":/docker") + if num_docker > 0: + return True + + def get_num_fans(self): + E3224F_MAX_FANTRAYS = 3 + return E3224F_MAX_FANTRAYS + + def get_presence(self, idx): + sysfs_path = "/sys/devices/platform/dell-e3224f-cpld.0/fan" + self._fan_mapping[idx] + "_prs" + return int(open(sysfs_path).read(), 16) + + def get_direction(self, idx): + sysfs_path = "/sys/devices/platform/dell-e3224f-cpld.0/fan" + self._fan_mapping[idx] + "_dir" + return open(sysfs_path).read() + + def get_speed(self, idx): + dockerenv = self.isDockerEnv() + if not dockerenv: + status, cmd_output = getstatusoutput_noshell(SENSORS_CMD) + else: + status, cmd_output = getstatusoutput_noshell(DOCKER_SENSORS_CMD) + if status: + print('Failed to execute sensors command') + sys.exit(0) + fan_id = 'Fan ' + str(idx) + found = False + for line in cmd_output.splitlines(): + if line.startswith('emc2305-i2c-7-2c'): + found = True + if found and line.startswith(fan_id): + return line.split()[3] + return 0.0 + + def get_status(self, idx): + sysfs_path = "/sys/devices/platform/dell-e3224f-cpld.0/fan" + self._fan_mapping[idx] + "_prs" + return int(open(sysfs_path).read(), 16) + + + def set_speed(self, idx): + return False diff --git a/device/dell/x86_64-dell_e3224f-r0/plugins/pcie.yaml b/device/dell/x86_64-dell_e3224f-r0/plugins/pcie.yaml new file mode 100644 index 000000000000..dd8049268567 --- /dev/null +++ b/device/dell/x86_64-dell_e3224f-r0/plugins/pcie.yaml @@ -0,0 +1,16 @@ +- bus: '02' + dev: '00' + fn: '0' + id: '1533' + name: 'Ethernet controller: Intel Corporation I210 Gigabit Network Connection (rev + 03)' +- bus: '01' + dev: '00' + fn: '0' + id: b371 + name: 'Ethernet controller: Broadcom Limited BCM56371 Switch ASIC (rev 02)' +- bus: '00' + dev: '14' + fn: '0' + id: 19c2 + name: 'SATA controller: Intel Corporation DNV SATA Controller 1 (rev 11)' diff --git a/device/dell/x86_64-dell_e3224f-r0/plugins/psuutil.py b/device/dell/x86_64-dell_e3224f-r0/plugins/psuutil.py new file mode 100644 index 000000000000..14ed58d70115 --- /dev/null +++ b/device/dell/x86_64-dell_e3224f-r0/plugins/psuutil.py @@ -0,0 +1,190 @@ +# +# psuutil.py +# Platform-specific PSU status interface for SONiC +# + +import os +import sys +from sonic_py_common.general import getstatusoutput_noshell + +SENSORS_CMD = ["docker", "exec", "-i", "pmon", "/usr/bin/sensors"] +DOCKER_SENSORS_CMD = "/usr/bin/sensors" + +try: + from sonic_psu.psu_base import PsuBase +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + + +class PsuUtil(PsuBase): + """Platform-specific PSUutil class""" + _psu_mapping = { + 1 : '0', + 2 : '1' + } + + def __init__(self): + PsuBase.__init__(self) + + def isDockerEnv(self): + num_docker = open('/proc/self/cgroup', 'r').read().count(":/docker") + if num_docker > 0: + return True + else: + return False + + def remove_nonnumeric(self, text): + digits='0123456789.' + return ''.join(c for c in text if c in digits) + + def get_cpld_register(self, reg_name): + cpld_dir = "/sys/devices/platform/dell-e3224f-cpld.0/" + retval = 'ERR' + reg_file = cpld_dir +'/' + reg_name + if (not os.path.isfile(reg_file)): + return retval + + try: + with open(reg_file, 'r') as fd: + retval = fd.read() + except Exception as error: + print("Unable to open ", reg_file, "file !") + + retval = retval.rstrip('\r\n') + return retval + + def get_num_psus(self): + """ + Retrieves the number of PSUs available on the device + :return: An integer, the number of PSUs available on the device + """ + E3224F_MAX_PSUS = 2 + return E3224F_MAX_PSUS + + def get_psu_status(self, index): + """ + Retrieves the oprational status of power supply unit (PSU) defined + by index + :param index: An integer, index of the PSU of which to query status + :return: Boolean, True if PSU is operating properly, False if PSU is\ + faulty + """ + status = 0 + psu_status = self.get_cpld_register('psu'+self._psu_mapping[index]+'_status') + if (psu_status != 'ERR'): + status = int(psu_status, 10) + + presence = self.get_psu_presence(index) + + return (status & presence) + + def get_psu_presence(self, index): + """ + Retrieves the presence status of power supply unit (PSU) defined + by index + :param index: An integer, index of the PSU of which to query status + :return: Boolean, True if PSU is plugged, False if not + """ + status = 0 + psu_presence = self.get_cpld_register('psu'+self._psu_mapping[index]+'_prs') + if (psu_presence != 'ERR'): + status = int(psu_presence, 10) + + return status + + def get_sensor(self): + dockerenv = self.isDockerEnv() + if not dockerenv: + status, cmd_output = getstatusoutput_noshell(SENSORS_CMD) + else: + status, cmd_output = getstatusoutput_noshell(DOCKER_SENSORS_CMD) + if status: + print('Failed to execute sensors command') + sys.exit(0) + return cmd_output + + def get_output_current(self, index): + cmd_output= self.get_sensor() + sensor_name = 'dps460-i2c-10' if index == 1 else 'dps460-i2c-11' + found = False + for line in cmd_output.splitlines(): + if line.startswith(sensor_name): + found = True + if found: + if 'Output Current' in line : + return float(self.remove_nonnumeric(line.split()[2])) + return 0.0 + + def get_output_voltage(self, index): + cmd_output= self.get_sensor() + sensor_name = 'dps460-i2c-10' if index == 1 else 'dps460-i2c-11' + found = False + for line in cmd_output.splitlines(): + if line.startswith(sensor_name): + found = True + if found: + if 'Output Voltage' in line : + return float(self.remove_nonnumeric(line.split()[2])) + return 0.0 + + def get_fan_rpm(self, index, fan_index): + if fan_index > 1 : return 0.0 + cmd_output= self.get_sensor() + sensor_name = 'dps460-i2c-10' if index == 1 else 'dps460-i2c-11' + found = False + for line in cmd_output.splitlines(): + if line.startswith(sensor_name): + found = True + if found: + if 'Fan RPM' in line : + return self.remove_nonnumeric(line.split()[2]) + return 0.0 + + def get_output_power(self, index): + cmd_output= self.get_sensor() + sensor_name = 'dps460-i2c-10' if index == 1 else 'dps460-i2c-11' + found = False + for line in cmd_output.splitlines(): + if line.startswith(sensor_name): + found = True + if found: + if 'Output Power' in line : + return float(self.remove_nonnumeric(line.split()[2])) + return 0.0 + + def get_direction(self, index): + psuid = '0' if index == 1 else '1' + sysfs_path = '/sys/devices/platform/dell-e3224f-cpld.0/psu' + psuid + '_prs' + found_psu = int(open(sysfs_path).read()) + if not found_psu : return '' + bus_no = '10' if index == 1 else '11' + sysfs_path = "/sys/bus/i2c/devices/" + bus_no + "-0056/eeprom" + val = (open(sysfs_path, "rb").read())[0xe1:0xe8] + dir = 'F2B' if 'FORWARD' == val else 'B2F' + return dir + + def get_serial(self, index): + psuid = '0' if index == 1 else '1' + sysfs_path = '/sys/devices/platform/dell-e3224f-cpld.0/psu' + psuid + '_prs' + found_psu = int(open(sysfs_path).read()) + if not found_psu : return '' + bus_no = '10' if index == 1 else '11' + sysfs_path = "/sys/bus/i2c/devices/" + bus_no + "-0056/eeprom" + val = (open(sysfs_path, "rb").read())[0xc4:0xd9] + return val + + def get_model(self, index): + psuid = '0' if index == 1 else '1' + sysfs_path = '/sys/devices/platform/dell-e3224f-cpld.0/psu' + psuid + '_prs' + found_psu = int(open(sysfs_path).read()) + if not found_psu : return '' + bus_no = '10' if index == 1 else '11' + sysfs_path = "/sys/bus/i2c/devices/" + bus_no + "-0056/eeprom" + val = (open(sysfs_path, "rb").read())[0x50:0x62] + return val + + def get_mfr_id(self, index): + psuid = '0' if index == 1 else '1' + sysfs_path = '/sys/devices/platform/dell-e3224f-cpld.0/psu' + psuid + '_prs' + found_psu = int(open(sysfs_path).read()) + return 'DELTA' if found_psu else '' diff --git a/device/dell/x86_64-dell_e3224f-r0/plugins/sfputil.py b/device/dell/x86_64-dell_e3224f-r0/plugins/sfputil.py new file mode 100644 index 000000000000..bccc745a4d68 --- /dev/null +++ b/device/dell/x86_64-dell_e3224f-r0/plugins/sfputil.py @@ -0,0 +1,198 @@ +# sfputil.py +# +# Platform-specific SFP transceiver interface for SONiC +# + +try: + import time + from socket import * + from select import * + from sonic_sfp.sfputilbase import SfpUtilBase +except ImportError as e: + raise ImportError("%s - required module not found" % str(e)) + +class SfpUtil(SfpUtilBase): + """Platform-specific SfpUtil class""" + + PORT_START = 1 + PORT_END = 30 + PORTS_IN_BLOCK = 30 + SFP_PORT_START = 1 + SFP_PORT_END = 28 + + EEPROM_OFFSET = 14 + + _port_to_eeprom_mapping = {} + _port_i2c_mapping = { + 1: 27, + 2: 28, + 3: 29, + 4: 30, + 5: 31, + 6: 32, + 7: 33, + 8: 34, + 9: 35, + 10: 36, + 11: 37, + 12: 38, + 13: 39, + 14: 40, + 15: 41, + 16: 42, + 17: 43, + 18: 44, + 19: 45, + 20: 46, + 21: 47, + 22: 48, + 23: 49, + 24: 50, + 25: 20, + 26: 21, + 27: 22, + 28: 23, + 29: 24, + 30: 25 + } + port_dict = {} + + @property + def port_start(self): + return self.PORT_START + + @property + def port_end(self): + return self.PORT_END + + @property + def qsfp_ports(self) : + return range(self.SFP_PORT_END+1, self.PORT_END+1) + + @property + def port_to_eeprom_mapping(self): + return self._port_to_eeprom_mapping + + @property + def get_transceiver_status(self): + + try: + sfp_modprs_path = "/sys/devices/platform/dell-e3224f-cpld.0/sfp_modprs" + reg_file = open(sfp_modprs_path) + + except IOError as e: + print ("Error: unable to open file: %s" % str(e)) + return False + + content = reg_file.readline().rstrip() + + reg_file.close() + + return int(content, 16) + + + def __init__(self): + + sfpplus_eeprom_path = "/sys/class/i2c-adapter/i2c-{0}/{0}-0050/eeprom" + + for x in range(self.SFP_PORT_START, self.PORT_END + 1): + self.port_to_eeprom_mapping[x] = sfpplus_eeprom_path.format(self._port_i2c_mapping[x]) + # Get Transceiver status + self.modprs_register = self.get_transceiver_status + + SfpUtilBase.__init__(self) + + def get_presence(self, port_num): + # Check for invalid port_num + if port_num < self.port_start or port_num > self.port_end: + return False + + if port_num < self.SFP_PORT_START : + return False + port_num -= self.SFP_PORT_START + try: + sfp_modprs_path = "/sys/devices/platform/dell-e3224f-cpld.0/sfp_modprs" + reg_file = open(sfp_modprs_path) + except IOError as e: + print ("Error: unable to open file: %s" % str(e)) + return False + + content = reg_file.readline().rstrip() + + # content is a string containing the hex representation of the register + reg_value = int(content, 16) + + # Mask off the bit corresponding to our port + mask = (1 << port_num) + + # ModPrsL is active low + if (reg_value & mask) == 0: + return True + + return False + + def get_low_power_mode(self, port_num): + return False + + def set_low_power_mode(self, port_num, lpmode): + return False + + def reset(self, port_num): + return False + + def get_transceiver_change_event(self, timeout=0): + + start_time = time.time() + port = self.SFP_PORT_START + forever = False + + if timeout == 0: + forever = True + elif timeout > 0: + timeout = timeout / float(1000) # Convert to secs + else: + print ('get_transceiver_change_event:Invalid timeout value', timeout) + return False, {} + + end_time = start_time + timeout + if start_time > end_time: + print ('get_transceiver_change_event:' \ + 'time wrap / invalid timeout value', timeout) + + return False, {} # Time wrap or possibly incorrect timeout + + while timeout >= 0: + # Check for OIR events and return updated port_dict + reg_value = self.get_transceiver_status + if reg_value != self.modprs_register: + changed_ports = self.modprs_register ^ reg_value + while port >= self.SFP_PORT_START and port <= self.SFP_PORT_END: + + # Mask off the bit corresponding to our port + mask = (1 << (port - self.SFP_PORT_START)) + + if changed_ports & mask: + # ModPrsL is active low + if reg_value & mask == 0: + self.port_dict[port] = '1' + else: + self.port_dict[port] = '0' + + port += 1 + + # Update reg value + self.modprs_register = reg_value + return True, self.port_dict + + if forever: + time.sleep(1) + else: + timeout = end_time - time.time() + if timeout >= 1: + time.sleep(1) # We poll at 1 second granularity + else: + if timeout > 0: + time.sleep(timeout) + return True, {} + print ("get_transceiver_change_event: Should not reach here.") + return False, {} diff --git a/device/dell/x86_64-dell_e3224f-r0/pmon_daemon_control.json b/device/dell/x86_64-dell_e3224f-r0/pmon_daemon_control.json new file mode 100644 index 000000000000..4f701c3b3400 --- /dev/null +++ b/device/dell/x86_64-dell_e3224f-r0/pmon_daemon_control.json @@ -0,0 +1,3 @@ +{ + "skip_ledd": true +} diff --git a/device/dell/x86_64-dell_e3224f-r0/sensors.conf b/device/dell/x86_64-dell_e3224f-r0/sensors.conf new file mode 100644 index 000000000000..987b4ad73984 --- /dev/null +++ b/device/dell/x86_64-dell_e3224f-r0/sensors.conf @@ -0,0 +1,58 @@ +# libsensors configuration file for Dell N3248TE +# The i2c bus portion is omit because adapter name +# changes every time when system boot up. + +bus "i2c-7" "i2c-0-mux (chan_id 5)" +bus "i2c-5" "i2c-0-mux (chan_id 3)" +bus "i2c-10" "i2c-5-mux (chan_id 0)" +bus "i2c-11" "i2c-5-mux (chan_id 1)" + +chip "tmp75-i2c-7-49" + label temp1 "Switch Near Temperature" +chip "tmp75-i2c-7-4a" + label temp1 "Switch Rear Temperature" +chip "tmp75-i2c-7-4b" + label temp1 "Front Panel PHY Temperature" +chip "tmp75-i2c-7-4c" + label temp1 "Near Front Panel Temperature" +chip "tmp75-i2c-7-4f" + label temp1 "Middle Fan Tray Temperature" + + +chip "emc2305-i2c-7-2c" + ignore fan4 + ignore fan5 + label fan1 "Fan 1 " + label fan2 "Fan 2 " + label fan3 "Fan 3 " + +chip "dps460-i2c-10-5e" + label power1 "Input Power" + label power2 "Output Power" + label curr1 "Input Current" + label curr2 "Output Current" + label in1 "Input Voltage" + ignore in2 + label in3 "Output Voltage" + label fan1 "Fan RPM" + ignore fan2 + ignore fan3 + ignore temp1 + label temp2 "FAN Airflow Temperature" + label temp3 "FAN Normal Temperature" + + +chip "dps460-i2c-11-5e" + label power1 "Input Power" + label power2 "Output Power" + label curr1 "Input Current" + label curr2 "Output Current" + label in1 "Input Voltage" + ignore in2 + label in3 "Output Voltage" + label fan1 "Fan RPM" + ignore fan2 + ignore fan3 + ignore temp1 + label temp2 "FAN Airflow Temperature" + label temp3 "FAN Normal Temperature" diff --git a/device/dell/x86_64-dell_e3224f-r0/system_health_monitoring_config.json b/device/dell/x86_64-dell_e3224f-r0/system_health_monitoring_config.json new file mode 100644 index 000000000000..dc20d412147f --- /dev/null +++ b/device/dell/x86_64-dell_e3224f-r0/system_health_monitoring_config.json @@ -0,0 +1,11 @@ +{ + "services_to_ignore": [], + "devices_to_ignore": ["fan.speed","psu.temperature","psu.voltage","asic"], + "user_defined_checkers": [], + "polling_interval": 60, + "led_color": { + "fault" : "blink_yellow", + "normal" : "green", + "booting": "blink_green" + } +} diff --git a/device/dell/x86_64-dellemc_s5248f_c3538-r0/DellEMC-S5248f-P-10G/custom_led.bin b/device/dell/x86_64-dellemc_s5248f_c3538-r0/DellEMC-S5248f-P-10G/custom_led.bin index b3966e520c51..626e41c3bbbd 100755 Binary files a/device/dell/x86_64-dellemc_s5248f_c3538-r0/DellEMC-S5248f-P-10G/custom_led.bin and b/device/dell/x86_64-dellemc_s5248f_c3538-r0/DellEMC-S5248f-P-10G/custom_led.bin differ diff --git a/device/dell/x86_64-dellemc_s5248f_c3538-r0/DellEMC-S5248f-P-10G/td3-s5248f-10g.config.bcm b/device/dell/x86_64-dellemc_s5248f_c3538-r0/DellEMC-S5248f-P-10G/td3-s5248f-10g.config.bcm index 69c3d1af90d9..3a7aeafc586a 100644 --- a/device/dell/x86_64-dellemc_s5248f_c3538-r0/DellEMC-S5248f-P-10G/td3-s5248f-10g.config.bcm +++ b/device/dell/x86_64-dellemc_s5248f_c3538-r0/DellEMC-S5248f-P-10G/td3-s5248f-10g.config.bcm @@ -350,5 +350,4 @@ dport_map_port_5=55 dport_map_port_41=56 mmu_init_config="TD3-DELL-lossless" -#sai_preinit_cmd_file=/usr/share/sonic/hwsku/sai_preinit_cmd.soc - +sai_preinit_cmd_file=/usr/share/sonic/hwsku/sai_preinit_cmd.soc diff --git a/device/dell/x86_64-dellemc_s5248f_c3538-r0/DellEMC-S5248f-P-25G/custom_led.bin b/device/dell/x86_64-dellemc_s5248f_c3538-r0/DellEMC-S5248f-P-25G/custom_led.bin index b3966e520c51..626e41c3bbbd 100755 Binary files a/device/dell/x86_64-dellemc_s5248f_c3538-r0/DellEMC-S5248f-P-25G/custom_led.bin and b/device/dell/x86_64-dellemc_s5248f_c3538-r0/DellEMC-S5248f-P-25G/custom_led.bin differ diff --git a/device/dell/x86_64-dellemc_s5248f_c3538-r0/DellEMC-S5248f-P-25G/td3-s5248f-25g.config.bcm b/device/dell/x86_64-dellemc_s5248f_c3538-r0/DellEMC-S5248f-P-25G/td3-s5248f-25g.config.bcm index 468b7d527989..028a04484a88 100644 --- a/device/dell/x86_64-dellemc_s5248f_c3538-r0/DellEMC-S5248f-P-25G/td3-s5248f-25g.config.bcm +++ b/device/dell/x86_64-dellemc_s5248f_c3538-r0/DellEMC-S5248f-P-25G/td3-s5248f-25g.config.bcm @@ -352,5 +352,5 @@ dport_map_port_5=55 dport_map_port_41=56 mmu_init_config="TD3-DELL-lossless" -#sai_preinit_cmd_file=/usr/share/sonic/hwsku/sai_preinit_cmd.soc +sai_preinit_cmd_file=/usr/share/sonic/hwsku/sai_preinit_cmd.soc diff --git a/device/dell/x86_64-dellemc_s5248f_c3538-r0/port-locator.soc b/device/dell/x86_64-dellemc_s5248f_c3538-r0/port-locator.soc new file mode 100644 index 000000000000..23fd23b47b0f --- /dev/null +++ b/device/dell/x86_64-dellemc_s5248f_c3538-r0/port-locator.soc @@ -0,0 +1,152 @@ +# LED interface controls +config add sai_led_intf_enable_0=1 +config add sai_led_intf_head_0=1 +config add sai_led_intf_tail_0=24 +config add sai_led_intf_bits_0=2 + +config add sai_led_intf_enable_1=1 +config add sai_led_intf_head_1=25 +config add sai_led_intf_tail_1=80 +config add sai_led_intf_bits_1=2 + +# LED data patterns for ON/OFF +config add sai_led_patt_off_0=0x3 +config add sai_led_patt_on_0=0x2 + +# Physical Port --> LED Port (1-based indexing) +# 1-lane port [49-49] Ethernet0 Eth1/1 +config add sai_led_portmap_49=2 +# 1-lane port [50-50] Ethernet1 Eth1/2 +config add sai_led_portmap_50=3 +# 1-lane port [51-51] Ethernet2 Eth1/3 +config add sai_led_portmap_51=4 +# 1-lane port [52-52] Ethernet3 Eth1/4 +config add sai_led_portmap_52=5 +# 1-lane port [57-57] Ethernet4 Eth1/5 +config add sai_led_portmap_57=6 +# 1-lane port [58-58] Ethernet5 Eth1/6 +config add sai_led_portmap_58=7 +# 1-lane port [59-59] Ethernet6 Eth1/7 +config add sai_led_portmap_59=8 +# 1-lane port [60-60] Ethernet7 Eth1/8 +config add sai_led_portmap_60=9 +# 1-lane port [61-61] Ethernet8 Eth1/9 +config add sai_led_portmap_61=10 +# 1-lane port [62-62] Ethernet9 Eth1/10 +config add sai_led_portmap_62=11 +# 1-lane port [63-63] Ethernet10 Eth1/11 +config add sai_led_portmap_63=12 +# 1-lane port [64-64] Ethernet11 Eth1/12 +config add sai_led_portmap_64=13 +# 1-lane port [77-77] Ethernet12 Eth1/13 +config add sai_led_portmap_77=14 +# 1-lane port [78-78] Ethernet13 Eth1/14 +config add sai_led_portmap_78=15 +# 1-lane port [79-79] Ethernet14 Eth1/15 +config add sai_led_portmap_79=16 +# 1-lane port [80-80] Ethernet15 Eth1/16 +config add sai_led_portmap_80=17 +# 1-lane port [85-85] Ethernet16 Eth1/17 +config add sai_led_portmap_85=18 +# 1-lane port [86-86] Ethernet17 Eth1/18 +config add sai_led_portmap_86=19 +# 1-lane port [87-87] Ethernet18 Eth1/19 +config add sai_led_portmap_87=20 +# 1-lane port [88-88] Ethernet19 Eth1/20 +config add sai_led_portmap_88=21 +# 1-lane port [93-93] Ethernet20 Eth1/21 +config add sai_led_portmap_93=22 +# 1-lane port [94-94] Ethernet21 Eth1/22 +config add sai_led_portmap_94=23 +# 1-lane port [95-95] Ethernet22 Eth1/23 +config add sai_led_portmap_95=24 +# 1-lane port [96-96] Ethernet23 Eth1/24 +config add sai_led_portmap_96=25 +# 1-lane port [13-13] Ethernet24 Eth1/25 +config add sai_led_portmap_13=26 +# 1-lane port [14-14] Ethernet25 Eth1/26 +config add sai_led_portmap_14=27 +# 1-lane port [15-15] Ethernet26 Eth1/27 +config add sai_led_portmap_15=28 +# 1-lane port [16-16] Ethernet27 Eth1/28 +config add sai_led_portmap_16=29 +# 1-lane port [21-21] Ethernet28 Eth1/29 +config add sai_led_portmap_21=30 +# 1-lane port [22-22] Ethernet29 Eth1/30 +config add sai_led_portmap_22=31 +# 1-lane port [23-23] Ethernet30 Eth1/31 +config add sai_led_portmap_23=32 +# 1-lane port [24-24] Ethernet31 Eth1/32 +config add sai_led_portmap_24=33 +# 1-lane port [29-29] Ethernet32 Eth1/33 +config add sai_led_portmap_29=34 +# 1-lane port [30-30] Ethernet33 Eth1/34 +config add sai_led_portmap_30=35 +# 1-lane port [31-31] Ethernet34 Eth1/35 +config add sai_led_portmap_31=36 +# 1-lane port [32-32] Ethernet35 Eth1/36 +config add sai_led_portmap_32=37 +# 1-lane port [97-97] Ethernet36 Eth1/37 +config add sai_led_portmap_97=38 +# 1-lane port [98-98] Ethernet37 Eth1/38 +config add sai_led_portmap_98=39 +# 1-lane port [99-99] Ethernet38 Eth1/39 +config add sai_led_portmap_99=40 +# 1-lane port [100-100] Ethernet39 Eth1/40 +config add sai_led_portmap_100=41 +# 1-lane port [105-105] Ethernet40 Eth1/41 +config add sai_led_portmap_105=42 +# 1-lane port [106-106] Ethernet41 Eth1/42 +config add sai_led_portmap_106=43 +# 1-lane port [107-107] Ethernet42 Eth1/43 +config add sai_led_portmap_107=44 +# 1-lane port [108-108] Ethernet43 Eth1/44 +config add sai_led_portmap_108=45 +# 1-lane port [113-113] Ethernet44 Eth1/45 +config add sai_led_portmap_113=46 +# 1-lane port [114-114] Ethernet45 Eth1/46 +config add sai_led_portmap_114=47 +# 1-lane port [115-115] Ethernet46 Eth1/47 +config add sai_led_portmap_115=48 +# 1-lane port [116-116] Ethernet47 Eth1/48 +config add sai_led_portmap_116=49 +# QSFP [121-124] Ethernet48-51 Eth1/49/1-4 +config add sai_led_portmap_121=66 +config add sai_led_portmap_122=67 +config add sai_led_portmap_123=68 +config add sai_led_portmap_124=69 +# QSFP [125-128] Ethernet52-55 Eth1/50/1-4 +config add sai_led_portmap_125=70 +config add sai_led_portmap_126=71 +config add sai_led_portmap_127=72 +config add sai_led_portmap_128=73 +# QSFP [69-72] Ethernet56-59 Eth1/51/1-4 +config add sai_led_portmap_69=74 +config add sai_led_portmap_70=75 +config add sai_led_portmap_71=76 +config add sai_led_portmap_72=77 +# QSFP [65-68] Ethernet60-63 Eth1/52/1-4 +config add sai_led_portmap_65=78 +config add sai_led_portmap_66=79 +config add sai_led_portmap_67=80 +config add sai_led_portmap_68=81 +# QSFP [1-4] Ethernet64-67 Eth1/53/1-4 +config add sai_led_portmap_1=50 +config add sai_led_portmap_2=51 +config add sai_led_portmap_3=52 +config add sai_led_portmap_4=53 +# QSFP [33-36] Ethernet68-71 Eth1/54/1-4 +config add sai_led_portmap_33=54 +config add sai_led_portmap_34=55 +config add sai_led_portmap_35=56 +config add sai_led_portmap_36=57 +# QSFP [5-8] Ethernet72-75 Eth1/55/1-4 +config add sai_led_portmap_5=58 +config add sai_led_portmap_6=59 +config add sai_led_portmap_7=60 +config add sai_led_portmap_8=61 +# QSFP [41-44] Ethernet76-79 Eth1/56/1-4 +config add sai_led_portmap_41=62 +config add sai_led_portmap_42=63 +config add sai_led_portmap_43=64 +config add sai_led_portmap_44=65 diff --git a/device/mellanox/x86_64-mlnx_msn2700-r0/pcie.yaml b/device/mellanox/x86_64-mlnx_msn2700-r0/pcie.yaml index 440afffc3256..74c796f94383 100644 --- a/device/mellanox/x86_64-mlnx_msn2700-r0/pcie.yaml +++ b/device/mellanox/x86_64-mlnx_msn2700-r0/pcie.yaml @@ -35,7 +35,7 @@ - bus: '00' dev: '01' fn: '2' - id: 0159 + id: '0159' name: 'PCI bridge: Intel Corporation Xeon E3-1200 v2/3rd Gen Core processor PCI Express Root Port (rev 09)' - bus: '00' diff --git a/device/mellanox/x86_64-mlnx_msn2700-r0/platform_reboot b/device/mellanox/x86_64-mlnx_msn2700-r0/platform_reboot index b2188fde6f5d..9b68790498a1 100755 --- a/device/mellanox/x86_64-mlnx_msn2700-r0/platform_reboot +++ b/device/mellanox/x86_64-mlnx_msn2700-r0/platform_reboot @@ -21,13 +21,24 @@ function ParseArguments() { } function SafePwrCycle() { - sync ; sync - umount -fa > /dev/null 2&>1 + sync; sync + umount -fa > /dev/null 2>&1 echo 1 > $SYSFS_PWR_CYCLE } ParseArguments "$@" +# Reboot immediately if the kdump capture kernel is running +VMCORE_FILE=/proc/vmcore +if [ -s $VMCORE_FILE ]; then + sync; sync + umount -fa > /dev/null 2>&1 + + # Run Debian reboot because the platform reboot isn't available + /sbin/reboot +fi + + ${FW_UPGRADE_SCRIPT} --upgrade --verbose EXIT_CODE="$?" if [[ "${EXIT_CODE}" != "${EXIT_SUCCESS}" ]]; then diff --git a/device/mellanox/x86_64-mlnx_msn3420-r0/ACS-MSN3420/sai.profile b/device/mellanox/x86_64-mlnx_msn3420-r0/ACS-MSN3420/sai.profile index 74228eb6446c..9b50bab67670 100644 --- a/device/mellanox/x86_64-mlnx_msn3420-r0/ACS-MSN3420/sai.profile +++ b/device/mellanox/x86_64-mlnx_msn3420-r0/ACS-MSN3420/sai.profile @@ -1,3 +1,4 @@ SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/sai_3420.xml SAI_DUMP_STORE_PATH=/var/log/mellanox/sdk-dumps SAI_DUMP_STORE_AMOUNT=10 +SAI_DUMP_MFT_CFG_PATH=/etc/mft/fwtrace_cfg diff --git a/device/mellanox/x86_64-mlnx_msn3700-r0/ACS-MSN3700/sai.profile b/device/mellanox/x86_64-mlnx_msn3700-r0/ACS-MSN3700/sai.profile index a2f615568e59..a040416bf51b 100644 --- a/device/mellanox/x86_64-mlnx_msn3700-r0/ACS-MSN3700/sai.profile +++ b/device/mellanox/x86_64-mlnx_msn3700-r0/ACS-MSN3700/sai.profile @@ -1,3 +1,4 @@ SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/sai_3700.xml SAI_DUMP_STORE_PATH=/var/log/mellanox/sdk-dumps SAI_DUMP_STORE_AMOUNT=10 +SAI_DUMP_MFT_CFG_PATH=/etc/mft/fwtrace_cfg diff --git a/device/mellanox/x86_64-mlnx_msn3700c-r0/ACS-MSN3700C/sai.profile b/device/mellanox/x86_64-mlnx_msn3700c-r0/ACS-MSN3700C/sai.profile index 21afbfe5c6d3..1b1b4bbe2477 100644 --- a/device/mellanox/x86_64-mlnx_msn3700c-r0/ACS-MSN3700C/sai.profile +++ b/device/mellanox/x86_64-mlnx_msn3700c-r0/ACS-MSN3700C/sai.profile @@ -1,3 +1,4 @@ SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/sai_3700c.xml SAI_DUMP_STORE_PATH=/var/log/mellanox/sdk-dumps SAI_DUMP_STORE_AMOUNT=10 +SAI_DUMP_MFT_CFG_PATH=/etc/mft/fwtrace_cfg diff --git a/device/mellanox/x86_64-mlnx_msn3800-r0/ACS-MSN3800/sai.profile b/device/mellanox/x86_64-mlnx_msn3800-r0/ACS-MSN3800/sai.profile index 9c74ce166084..5fe089467374 100644 --- a/device/mellanox/x86_64-mlnx_msn3800-r0/ACS-MSN3800/sai.profile +++ b/device/mellanox/x86_64-mlnx_msn3800-r0/ACS-MSN3800/sai.profile @@ -1,3 +1,4 @@ SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/sai_3800.xml SAI_DUMP_STORE_PATH=/var/log/mellanox/sdk-dumps SAI_DUMP_STORE_AMOUNT=10 +SAI_DUMP_MFT_CFG_PATH=/etc/mft/fwtrace_cfg diff --git a/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-C64/sai.profile b/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-C64/sai.profile index 9c74ce166084..5fe089467374 100644 --- a/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-C64/sai.profile +++ b/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-C64/sai.profile @@ -1,3 +1,4 @@ SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/sai_3800.xml SAI_DUMP_STORE_PATH=/var/log/mellanox/sdk-dumps SAI_DUMP_STORE_AMOUNT=10 +SAI_DUMP_MFT_CFG_PATH=/etc/mft/fwtrace_cfg diff --git a/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D100C12S2/sai.profile b/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D100C12S2/sai.profile index 2d6c6ad4acc8..5a8b32f589b8 100644 --- a/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D100C12S2/sai.profile +++ b/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D100C12S2/sai.profile @@ -1 +1,4 @@ SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/sai_3800_2x10g_100x50g_12x100g.xml +SAI_DUMP_STORE_PATH=/var/log/mellanox/sdk-dumps +SAI_DUMP_STORE_AMOUNT=10 +SAI_DUMP_MFT_CFG_PATH=/etc/mft/fwtrace_cfg diff --git a/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D112C8/sai.profile b/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D112C8/sai.profile index 181ced0f1269..a2c98b0402c8 100644 --- a/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D112C8/sai.profile +++ b/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D112C8/sai.profile @@ -1,3 +1,4 @@ SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/sai_3800_112x50g_8x100g.xml SAI_DUMP_STORE_PATH=/var/log/mellanox/sdk-dumps SAI_DUMP_STORE_AMOUNT=10 +SAI_DUMP_MFT_CFG_PATH=/etc/mft/fwtrace_cfg diff --git a/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D24C52/sai.profile b/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D24C52/sai.profile index 6580208c68de..56d838caad12 100644 --- a/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D24C52/sai.profile +++ b/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D24C52/sai.profile @@ -1,3 +1,4 @@ SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/sai_3800_24x50g_52x100g.xml SAI_DUMP_STORE_PATH=/var/log/mellanox/sdk-dumps SAI_DUMP_STORE_AMOUNT=10 +SAI_DUMP_MFT_CFG_PATH=/etc/mft/fwtrace_cfg diff --git a/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D28C49S1/sai.profile b/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D28C49S1/sai.profile index bd07d661025d..1e4875e52a2d 100644 --- a/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D28C49S1/sai.profile +++ b/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D28C49S1/sai.profile @@ -1,3 +1,4 @@ SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/sai_3800_1x10g_28x50g_49x100g.xml SAI_DUMP_STORE_PATH=/var/log/mellanox/sdk-dumps SAI_DUMP_STORE_AMOUNT=10 +SAI_DUMP_MFT_CFG_PATH=/etc/mft/fwtrace_cfg diff --git a/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D28C50/sai.profile b/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D28C50/sai.profile index ef03ceff837e..be194b72c731 100644 --- a/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D28C50/sai.profile +++ b/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D28C50/sai.profile @@ -1,3 +1,4 @@ SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/sai_3800_28x50g_52x100g.xml SAI_DUMP_STORE_PATH=/var/log/mellanox/sdk-dumps SAI_DUMP_STORE_AMOUNT=10 +SAI_DUMP_MFT_CFG_PATH=/etc/mft/fwtrace_cfg diff --git a/device/mellanox/x86_64-mlnx_msn4410-r0/ACS-MSN4410/hwsku.json b/device/mellanox/x86_64-mlnx_msn4410-r0/ACS-MSN4410/hwsku.json index 13eceb4baba5..6e1c31705bd4 100644 --- a/device/mellanox/x86_64-mlnx_msn4410-r0/ACS-MSN4410/hwsku.json +++ b/device/mellanox/x86_64-mlnx_msn4410-r0/ACS-MSN4410/hwsku.json @@ -1,76 +1,76 @@ { "interfaces": { "Ethernet0": { - "default_brkout_mode": "2x100G[50G,40G,25G,10G,1G]" + "default_brkout_mode": "2x100G[200G,50G,40G,25G,10G,1G]" }, "Ethernet8": { - "default_brkout_mode": "2x100G[50G,40G,25G,10G,1G]" + "default_brkout_mode": "2x100G[200G,50G,40G,25G,10G,1G]" }, "Ethernet16": { - "default_brkout_mode": "2x100G[50G,40G,25G,10G,1G]" + "default_brkout_mode": "2x100G[200G,50G,40G,25G,10G,1G]" }, "Ethernet24": { - "default_brkout_mode": "2x100G[50G,40G,25G,10G,1G]" + "default_brkout_mode": "2x100G[200G,50G,40G,25G,10G,1G]" }, "Ethernet32": { - "default_brkout_mode": "2x100G[50G,40G,25G,10G,1G]" + "default_brkout_mode": "2x100G[200G,50G,40G,25G,10G,1G]" }, "Ethernet40": { - "default_brkout_mode": "2x100G[50G,40G,25G,10G,1G]" + "default_brkout_mode": "2x100G[200G,50G,40G,25G,10G,1G]" }, "Ethernet48": { - "default_brkout_mode": "2x100G[50G,40G,25G,10G,1G]" + "default_brkout_mode": "2x100G[200G,50G,40G,25G,10G,1G]" }, "Ethernet56": { - "default_brkout_mode": "2x100G[50G,40G,25G,10G,1G]" + "default_brkout_mode": "2x100G[200G,50G,40G,25G,10G,1G]" }, "Ethernet64": { - "default_brkout_mode": "2x100G[50G,40G,25G,10G,1G]" + "default_brkout_mode": "2x100G[200G,50G,40G,25G,10G,1G]" }, "Ethernet72": { - "default_brkout_mode": "2x100G[50G,40G,25G,10G,1G]" + "default_brkout_mode": "2x100G[200G,50G,40G,25G,10G,1G]" }, "Ethernet80": { - "default_brkout_mode": "2x100G[50G,40G,25G,10G,1G]" + "default_brkout_mode": "2x100G[200G,50G,40G,25G,10G,1G]" }, "Ethernet88": { - "default_brkout_mode": "2x100G[50G,40G,25G,10G,1G]" + "default_brkout_mode": "2x100G[200G,50G,40G,25G,10G,1G]" }, "Ethernet96": { - "default_brkout_mode": "2x100G[50G,40G,25G,10G,1G]" + "default_brkout_mode": "2x100G[200G,50G,40G,25G,10G,1G]" }, "Ethernet104": { - "default_brkout_mode": "2x100G[50G,40G,25G,10G,1G]" + "default_brkout_mode": "2x100G[200G,50G,40G,25G,10G,1G]" }, "Ethernet112": { - "default_brkout_mode": "2x100G[50G,40G,25G,10G,1G]" + "default_brkout_mode": "2x100G[200G,50G,40G,25G,10G,1G]" }, "Ethernet120": { - "default_brkout_mode": "2x100G[50G,40G,25G,10G,1G]" + "default_brkout_mode": "2x100G[200G,50G,40G,25G,10G,1G]" }, "Ethernet128": { - "default_brkout_mode": "2x100G[50G,40G,25G,10G,1G]" + "default_brkout_mode": "2x100G[200G,50G,40G,25G,10G,1G]" }, "Ethernet136": { - "default_brkout_mode": "2x100G[50G,40G,25G,10G,1G]" + "default_brkout_mode": "2x100G[200G,50G,40G,25G,10G,1G]" }, "Ethernet144": { - "default_brkout_mode": "2x100G[50G,40G,25G,10G,1G]" + "default_brkout_mode": "2x100G[200G,50G,40G,25G,10G,1G]" }, "Ethernet152": { - "default_brkout_mode": "2x100G[50G,40G,25G,10G,1G]" + "default_brkout_mode": "2x100G[200G,50G,40G,25G,10G,1G]" }, "Ethernet160": { - "default_brkout_mode": "2x100G[50G,40G,25G,10G,1G]" + "default_brkout_mode": "2x100G[200G,50G,40G,25G,10G,1G]" }, "Ethernet168": { - "default_brkout_mode": "2x100G[50G,40G,25G,10G,1G]" + "default_brkout_mode": "2x100G[200G,50G,40G,25G,10G,1G]" }, "Ethernet176": { - "default_brkout_mode": "2x100G[50G,40G,25G,10G,1G]" + "default_brkout_mode": "2x100G[200G,50G,40G,25G,10G,1G]" }, "Ethernet184": { - "default_brkout_mode": "2x100G[50G,40G,25G,10G,1G]" + "default_brkout_mode": "2x100G[200G,50G,40G,25G,10G,1G]" }, "Ethernet192": { "default_brkout_mode": "1x400G[200G,100G,50G,40G,25G,10G,1G]" diff --git a/device/mellanox/x86_64-mlnx_msn4410-r0/ACS-MSN4410/sai.profile b/device/mellanox/x86_64-mlnx_msn4410-r0/ACS-MSN4410/sai.profile index 1fd5ba39f3af..09cacbed000d 100644 --- a/device/mellanox/x86_64-mlnx_msn4410-r0/ACS-MSN4410/sai.profile +++ b/device/mellanox/x86_64-mlnx_msn4410-r0/ACS-MSN4410/sai.profile @@ -1,3 +1,4 @@ SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/sai_4410.xml SAI_DUMP_STORE_PATH=/var/log/mellanox/sdk-dumps SAI_DUMP_STORE_AMOUNT=10 +SAI_DUMP_MFT_CFG_PATH=/etc/mft/fwtrace_cfg diff --git a/device/mellanox/x86_64-mlnx_msn4410-r0/platform.json b/device/mellanox/x86_64-mlnx_msn4410-r0/platform.json index bf9b9ea30247..f357ea2a48b3 100644 --- a/device/mellanox/x86_64-mlnx_msn4410-r0/platform.json +++ b/device/mellanox/x86_64-mlnx_msn4410-r0/platform.json @@ -411,216 +411,288 @@ "index": "1,1,1,1,1,1,1,1", "lanes": "0,1,2,3,4,5,6,7", "breakout_modes": { + "1x50G(1)": ["etp1"], + "1x100G(2)": ["etp1"], + "1x200G(4)": ["etp1"], "1x100G[50G,40G,25G,10G,1G]": ["etp1"], - "2x100G[50G,40G,25G,10G,1G]": ["etp1a", "etp1b"], - "4x50G[25G,10G,1G]": ["etp1a", "etp1b", "etp1c", "etp1d"] + "2x200G[100G,50G,40G,25G,10G,1G]": ["etp1a", "etp1b"], + "4x100G[50G,25G,10G,1G]": ["etp1a", "etp1b", "etp1c", "etp1d"] } }, "Ethernet8": { "index": "2,2,2,2,2,2,2,2", "lanes": "8,9,10,11,12,13,14,15", "breakout_modes": { + "1x50G(1)": ["etp2"], + "1x100G(2)": ["etp2"], + "1x200G(4)": ["etp2"], "1x100G[50G,40G,25G,10G,1G]": ["etp2"], - "2x100G[50G,40G,25G,10G,1G]": ["etp2a", "etp2b"], - "4x50G[25G,10G,1G]": ["etp2a", "etp2b", "etp2c", "etp2d"] + "2x200G[100G,50G,40G,25G,10G,1G]": ["etp2a", "etp2b"], + "4x100G[50G,25G,10G,1G]": ["etp2a", "etp2b", "etp2c", "etp2d"] } }, "Ethernet16": { "index": "3,3,3,3,3,3,3,3", "lanes": "16,17,18,19,20,21,22,23", "breakout_modes": { + "1x50G(1)": ["etp3"], + "1x100G(2)": ["etp3"], + "1x200G(4)": ["etp3"], "1x100G[50G,40G,25G,10G,1G]": ["etp3"], - "2x100G[50G,40G,25G,10G,1G]": ["etp3a", "etp3b"], - "4x50G[25G,10G,1G]": ["etp3a", "etp3b", "etp3c", "etp3d"] + "2x200G[100G,50G,40G,25G,10G,1G]": ["etp3a", "etp3b"], + "4x100G[50G,25G,10G,1G]": ["etp3a", "etp3b", "etp3c", "etp3d"] } }, "Ethernet24": { "index": "4,4,4,4,4,4,4,4", "lanes": "24,25,26,27,28,29,30,31", "breakout_modes": { + "1x50G(1)": ["etp4"], + "1x100G(2)": ["etp4"], + "1x200G(4)": ["etp4"], "1x100G[50G,40G,25G,10G,1G]": ["etp4"], - "2x100G[50G,40G,25G,10G,1G]": ["etp4a", "etp4b"], - "4x50G[25G,10G,1G]": ["etp4a", "etp4b", "etp4c", "etp4d"] + "2x200G[100G,50G,40G,25G,10G,1G]": ["etp4a", "etp4b"], + "4x100G[50G,25G,10G,1G]": ["etp4a", "etp4b", "etp4c", "etp4d"] } }, "Ethernet32": { "index": "5,5,5,5,5,5,5,5,5", "lanes": "32,33,34,35,36,37,38,39", "breakout_modes": { + "1x50G(1)": ["etp5"], + "1x100G(2)": ["etp5"], + "1x200G(4)": ["etp5"], "1x100G[50G,40G,25G,10G,1G]": ["etp5"], - "2x100G[50G,40G,25G,10G,1G]": ["etp5a", "etp5b"], - "4x50G[25G,10G,1G]": ["etp5a", "etp5b", "etp5c", "etp5d"] + "2x200G[100G,50G,40G,25G,10G,1G]": ["etp5a", "etp5b"], + "4x100G[50G,25G,10G,1G]": ["etp5a", "etp5b", "etp5c", "etp5d"] } }, "Ethernet40": { "index": "6,6,6,6,6,6,6,6", "lanes": "40,41,42,43,44,45,46,47", "breakout_modes": { + "1x50G(1)": ["etp6"], + "1x100G(2)": ["etp6"], + "1x200G(4)": ["etp6"], "1x100G[50G,40G,25G,10G,1G]": ["etp6"], - "2x100G[50G,40G,25G,10G,1G]": ["etp6a", "etp6b"], - "4x50G[25G,10G,1G]": ["etp6a", "etp6b", "etp6c", "etp6d"] + "2x200G[100G,50G,40G,25G,10G,1G]": ["etp6a", "etp6b"], + "4x100G[50G,25G,10G,1G]": ["etp6a", "etp6b", "etp6c", "etp6d"] } }, "Ethernet48": { "index": "7,7,7,7,7,7,7,7", "lanes": "48,49,50,51,52,53,54,55", "breakout_modes": { + "1x50G(1)": ["etp7"], + "1x100G(2)": ["etp7"], + "1x200G(4)": ["etp7"], "1x100G[50G,40G,25G,10G,1G]": ["etp7"], - "2x100G[50G,40G,25G,10G,1G]": ["etp7a", "etp7b"], - "4x50G[25G,10G,1G]": ["etp7a", "etp7b", "etp7c", "etp7d"] + "2x200G[100G,50G,40G,25G,10G,1G]": ["etp7a", "etp7b"], + "4x100G[50G,25G,10G,1G]": ["etp7a", "etp7b", "etp7c", "etp7d"] } }, "Ethernet56": { "index": "8,8,8,8,8,8,8,8", "lanes": "56,57,58,59,60,61,62,63", "breakout_modes": { + "1x50G(1)": ["etp8"], + "1x100G(2)": ["etp8"], + "1x200G(4)": ["etp8"], "1x100G[50G,40G,25G,10G,1G]": ["etp8"], - "2x100G[50G,40G,25G,10G,1G]": ["etp8a", "etp8b"], - "4x50G[25G,10G,1G]": ["etp8a", "etp8b", "etp8c", "etp8d"] + "2x200G[100G,50G,40G,25G,10G,1G]": ["etp8a", "etp8b"], + "4x100G[50G,25G,10G,1G]": ["etp8a", "etp8b", "etp8c", "etp8d"] } }, "Ethernet64": { "index": "9,9,9,9,9,9,9,9", "lanes": "64,65,66,67,68,69,70,71", "breakout_modes": { + "1x50G(1)": ["etp9"], + "1x100G(2)": ["etp9"], + "1x200G(4)": ["etp9"], "1x100G[50G,40G,25G,10G,1G]": ["etp9"], - "2x100G[50G,40G,25G,10G,1G]": ["etp9a", "etp9b"], - "4x50G[25G,10G,1G]": ["etp9a", "etp9b", "etp9c", "etp9d"] + "2x200G[100G,50G,40G,25G,10G,1G]": ["etp9a", "etp9b"], + "4x100G[50G,25G,10G,1G]": ["etp9a", "etp9b", "etp9c", "etp9d"] } }, "Ethernet72": { "index": "10,10,10,10,10,10,10,10", "lanes": "72,73,74,75,76,77,78,79", "breakout_modes": { + "1x50G(1)": ["etp10"], + "1x100G(2)": ["etp10"], + "1x200G(4)": ["etp10"], "1x100G[50G,40G,25G,10G,1G]": ["etp10"], - "2x100G[50G,40G,25G,10G,1G]": ["etp10a", "etp10b"], - "4x50G[25G,10G,1G]": ["etp10a", "etp10b", "etp10c", "etp10d"] + "2x200G[100G,50G,40G,25G,10G,1G]": ["etp10a", "etp10b"], + "4x100G[50G,25G,10G,1G]": ["etp10a", "etp10b", "etp10c", "etp10d"] } }, "Ethernet80": { "index": "11,11,11,11,11,11,11,11", "lanes": "80,81,82,83,84,85,86,87", "breakout_modes": { + "1x50G(1)": ["etp11"], + "1x100G(2)": ["etp11"], + "1x200G(4)": ["etp11"], "1x100G[50G,40G,25G,10G,1G]": ["etp11"], - "2x100G[50G,40G,25G,10G,1G]": ["etp11a", "etp11b"], - "4x50G[25G,10G,1G]": ["etp11a", "etp11b", "etp11c", "etp11d"] + "2x200G[100G,50G,40G,25G,10G,1G]": ["etp11a", "etp11b"], + "4x100G[50G,25G,10G,1G]": ["etp11a", "etp11b", "etp11c", "etp11d"] } }, "Ethernet88": { "index": "12,12,12,12,12,12,12,12", "lanes": "88,89,90,91,92,93,94,95", "breakout_modes": { + "1x50G(1)": ["etp12"], + "1x100G(2)": ["etp12"], + "1x200G(4)": ["etp12"], "1x100G[50G,40G,25G,10G,1G]": ["etp12"], - "2x100G[50G,40G,25G,10G,1G]": ["etp12a", "etp12b"], - "4x50G[25G,10G,1G]": ["etp12a", "etp12b", "etp12c", "etp12d"] + "2x200G[100G,50G,40G,25G,10G,1G]": ["etp12a", "etp12b"], + "4x100G[50G,25G,10G,1G]": ["etp12a", "etp12b", "etp12c", "etp12d"] } }, "Ethernet96": { "index": "13,13,13,13,13,13,13,13", "lanes": "96,97,98,99,100,101,102,103", "breakout_modes": { + "1x50G(1)": ["etp13"], + "1x100G(2)": ["etp13"], + "1x200G(4)": ["etp13"], "1x100G[50G,40G,25G,10G,1G]": ["etp13"], - "2x100G[50G,40G,25G,10G,1G]": ["etp13a", "etp13b"], - "4x50G[25G,10G,1G]": ["etp13a", "etp13b", "etp13c", "etp13d"] + "2x200G[100G,50G,40G,25G,10G,1G]": ["etp13a", "etp13b"], + "4x100G[50G,25G,10G,1G]": ["etp13a", "etp13b", "etp13c", "etp13d"] } }, "Ethernet104": { "index": "14,14,14,14,14,14,14,14", "lanes": "104,105,106,107,108,109,110,111", "breakout_modes": { + "1x50G(1)": ["etp14"], + "1x100G(2)": ["etp14"], + "1x200G(4)": ["etp14"], "1x100G[50G,40G,25G,10G,1G]": ["etp14"], - "2x100G[50G,40G,25G,10G,1G]": ["etp14a", "etp14b"], - "4x50G[25G,10G,1G]": ["etp14a", "etp14b", "etp14c", "etp14d"] + "2x200G[100G,50G,40G,25G,10G,1G]": ["etp14a", "etp14b"], + "4x100G[50G,25G,10G,1G]": ["etp14a", "etp14b", "etp14c", "etp14d"] } }, "Ethernet112": { "index": "15,15,15,15,15,15,15,15", "lanes": "112,113,114,115,116,117,118,119", "breakout_modes": { + "1x50G(1)": ["etp15"], + "1x100G(2)": ["etp15"], + "1x200G(4)": ["etp15"], "1x100G[50G,40G,25G,10G,1G]": ["etp15"], - "2x100G[50G,40G,25G,10G,1G]": ["etp15a", "etp15b"], - "4x50G[25G,10G,1G]": ["etp15a", "etp15b", "etp15c", "etp15d"] + "2x200G[100G,50G,40G,25G,10G,1G]": ["etp15a", "etp15b"], + "4x100G[50G,25G,10G,1G]": ["etp15a", "etp15b", "etp15c", "etp15d"] } }, "Ethernet120": { "index": "16,16,16,16,16,16,16,16", "lanes": "120,121,122,123,124,125,126,127", "breakout_modes": { + "1x50G(1)": ["etp16"], + "1x100G(2)": ["etp16"], + "1x200G(4)": ["etp16"], "1x100G[50G,40G,25G,10G,1G]": ["etp16"], - "2x100G[50G,40G,25G,10G,1G]": ["etp16a", "etp16b"], - "4x50G[25G,10G,1G]": ["etp16a", "etp16b", "etp16c", "etp16d"] + "2x200G[100G,50G,40G,25G,10G,1G]": ["etp16a", "etp16b"], + "4x100G[50G,25G,10G,1G]": ["etp16a", "etp16b", "etp16c", "etp16d"] } }, "Ethernet128": { "index": "17,17,17,17,17,17,17,17", "lanes": "128,129,130,131,132,133,134,135", "breakout_modes": { + "1x50G(1)": ["etp17"], + "1x100G(2)": ["etp17"], + "1x200G(4)": ["etp17"], "1x100G[50G,40G,25G,10G,1G]": ["etp17"], - "2x100G[50G,40G,25G,10G,1G]": ["etp17a", "etp17b"], - "4x50G[25G,10G,1G]": ["etp17a", "etp17b", "etp17c", "etp17d"] + "2x200G[100G,50G,40G,25G,10G,1G]": ["etp17a", "etp17b"], + "4x100G[50G,25G,10G,1G]": ["etp17a", "etp17b", "etp17c", "etp17d"] } }, "Ethernet136": { "index": "18,18,18,18,18,18,18,18", "lanes": "136,137,138,139,140,141,142,143", "breakout_modes": { + "1x50G(1)": ["etp18"], + "1x100G(2)": ["etp18"], + "1x200G(4)": ["etp18"], "1x100G[50G,40G,25G,10G,1G]": ["etp18"], - "2x100G[50G,40G,25G,10G,1G]": ["etp18a", "etp18b"], - "4x50G[25G,10G,1G]": ["etp18a", "etp18b", "etp18c", "etp18d"] + "2x200G[100G,50G,40G,25G,10G,1G]": ["etp18a", "etp18b"], + "4x100G[50G,25G,10G,1G]": ["etp18a", "etp18b", "etp18c", "etp18d"] } }, "Ethernet144": { "index": "19,19,19,19,19,19,19,19", "lanes": "144,145,146,147,148,149,150,151", "breakout_modes": { + "1x50G(1)": ["etp19"], + "1x100G(2)": ["etp19"], + "1x200G(4)": ["etp19"], "1x100G[50G,40G,25G,10G,1G]": ["etp19"], - "2x100G[50G,40G,25G,10G,1G]": ["etp19a", "etp19b"], - "4x50G[25G,10G,1G]": ["etp19a", "etp19b", "etp19c", "etp19d"] + "2x200G[100G,50G,40G,25G,10G,1G]": ["etp19a", "etp19b"], + "4x100G[50G,25G,10G,1G]": ["etp19a", "etp19b", "etp19c", "etp19d"] } }, "Ethernet152": { "index": "20,20,20,20,20,20,20,20", "lanes": "152,153,154,155,156,157,158,159", "breakout_modes": { + "1x50G(1)": ["etp20"], + "1x100G(2)": ["etp20"], + "1x200G(4)": ["etp20"], "1x100G[50G,40G,25G,10G,1G]": ["etp20"], - "2x100G[50G,40G,25G,10G,1G]": ["etp20a", "etp20b"], - "4x50G[25G,10G,1G]": ["etp20a", "etp20b", "etp20c", "etp20d"] + "2x200G[100G,50G,40G,25G,10G,1G]": ["etp20a", "etp20b"], + "4x100G[50G,25G,10G,1G]": ["etp20a", "etp20b", "etp20c", "etp20d"] } }, "Ethernet160": { "index": "21,21,21,21,21,21,21,21", "lanes": "160,161,162,163,164,165,166,167", "breakout_modes": { + "1x50G(1)": ["etp21"], + "1x100G(2)": ["etp21"], + "1x200G(4)": ["etp21"], "1x100G[50G,40G,25G,10G,1G]": ["etp21"], - "2x100G[50G,40G,25G,10G,1G]": ["etp21a", "etp21b"], - "4x50G[25G,10G,1G]": ["etp21a", "etp21b", "etp21c", "etp21d"] + "2x200G[100G,50G,40G,25G,10G,1G]": ["etp21a", "etp21b"], + "4x100G[50G,25G,10G,1G]": ["etp21a", "etp21b", "etp21c", "etp21d"] } }, "Ethernet168": { "index": "22,22,22,22,22,22,22,22", "lanes": "168,169,170,171,172,173,174,175", "breakout_modes": { + "1x50G(1)": ["etp22"], + "1x100G(2)": ["etp22"], + "1x200G(4)": ["etp22"], "1x100G[50G,40G,25G,10G,1G]": ["etp22"], - "2x100G[50G,40G,25G,10G,1G]": ["etp22a", "etp22b"], - "4x50G[25G,10G,1G]": ["etp22a", "etp22b", "etp22c", "etp22d"] + "2x200G[100G,50G,40G,25G,10G,1G]": ["etp22a", "etp22b"], + "4x100G[50G,25G,10G,1G]": ["etp22a", "etp22b", "etp22c", "etp22d"] } }, "Ethernet176": { "index": "23,23,23,23,23,23,23,23", "lanes": "176,177,178,179,180,181,182,183", "breakout_modes": { + "1x50G(1)": ["etp23"], + "1x100G(2)": ["etp23"], + "1x200G(4)": ["etp23"], "1x100G[50G,40G,25G,10G,1G]": ["etp23"], - "2x100G[50G,40G,25G,10G,1G]": ["etp23a", "etp23b"], - "4x50G[25G,10G,1G]": ["etp23a", "etp23b", "etp23c", "etp23d"] + "2x200G[100G,50G,40G,25G,10G,1G]": ["etp23a", "etp23b"], + "4x100G[50G,25G,10G,1G]": ["etp23a", "etp23b", "etp23c", "etp23d"] } }, "Ethernet184": { "index": "24,24,24,24,24,24,24,24", "lanes": "184,185,186,187,188,189,190,191", "breakout_modes": { + "1x50G(1)": ["etp24"], + "1x100G(2)": ["etp24"], + "1x200G(4)": ["etp24"], "1x100G[50G,40G,25G,10G,1G]": ["etp24"], - "2x100G[50G,40G,25G,10G,1G]": ["etp24a", "etp24b"], - "4x50G[25G,10G,1G]": ["etp24a", "etp24b", "etp24c", "etp24d"] + "2x200G[100G,50G,40G,25G,10G,1G]": ["etp24a", "etp24b"], + "4x100G[50G,25G,10G,1G]": ["etp24a", "etp24b", "etp24c", "etp24d"] } }, "Ethernet192": { diff --git a/device/mellanox/x86_64-mlnx_msn4600-r0/ACS-MSN4600/sai.profile b/device/mellanox/x86_64-mlnx_msn4600-r0/ACS-MSN4600/sai.profile index 8dc29d810f8e..f9d5172456a1 100644 --- a/device/mellanox/x86_64-mlnx_msn4600-r0/ACS-MSN4600/sai.profile +++ b/device/mellanox/x86_64-mlnx_msn4600-r0/ACS-MSN4600/sai.profile @@ -1,3 +1,4 @@ SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/sai_4600.xml SAI_DUMP_STORE_PATH=/var/log/mellanox/sdk-dumps SAI_DUMP_STORE_AMOUNT=10 +SAI_DUMP_MFT_CFG_PATH=/etc/mft/fwtrace_cfg diff --git a/device/mellanox/x86_64-mlnx_msn4600c-r0/ACS-MSN4600C/sai.profile b/device/mellanox/x86_64-mlnx_msn4600c-r0/ACS-MSN4600C/sai.profile index 33f195e4a17f..6dfcaf49bf66 100644 --- a/device/mellanox/x86_64-mlnx_msn4600c-r0/ACS-MSN4600C/sai.profile +++ b/device/mellanox/x86_64-mlnx_msn4600c-r0/ACS-MSN4600C/sai.profile @@ -1,3 +1,4 @@ SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/sai_4600C.xml SAI_DUMP_STORE_PATH=/var/log/mellanox/sdk-dumps SAI_DUMP_STORE_AMOUNT=10 +SAI_DUMP_MFT_CFG_PATH=/etc/mft/fwtrace_cfg diff --git a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-C64/sai.profile b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-C64/sai.profile index 33f195e4a17f..6dfcaf49bf66 100644 --- a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-C64/sai.profile +++ b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-C64/sai.profile @@ -1,3 +1,4 @@ SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/sai_4600C.xml SAI_DUMP_STORE_PATH=/var/log/mellanox/sdk-dumps SAI_DUMP_STORE_AMOUNT=10 +SAI_DUMP_MFT_CFG_PATH=/etc/mft/fwtrace_cfg diff --git a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D100C12S2/sai.profile b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D100C12S2/sai.profile index 2b9929123105..4987094a5454 100644 --- a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D100C12S2/sai.profile +++ b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D100C12S2/sai.profile @@ -1,3 +1,4 @@ SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/sai_4600c_100x50g_12x100g_2x10g.xml SAI_DUMP_STORE_PATH=/var/log/mellanox/sdk-dumps SAI_DUMP_STORE_AMOUNT=10 +SAI_DUMP_MFT_CFG_PATH=/etc/mft/fwtrace_cfg diff --git a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D112C8/sai.profile b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D112C8/sai.profile index eef447eba2f4..21d8fe5a9239 100644 --- a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D112C8/sai.profile +++ b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D112C8/sai.profile @@ -1,3 +1,4 @@ SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/sai_4600c_112x50g_8x100g.xml SAI_DUMP_STORE_PATH=/var/log/mellanox/sdk-dumps SAI_DUMP_STORE_AMOUNT=10 +SAI_DUMP_MFT_CFG_PATH=/etc/mft/fwtrace_cfg diff --git a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D48C40/sai.profile b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D48C40/sai.profile index c255886841ba..1970e7030832 100644 --- a/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D48C40/sai.profile +++ b/device/mellanox/x86_64-mlnx_msn4600c-r0/Mellanox-SN4600C-D48C40/sai.profile @@ -1,3 +1,4 @@ SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/sai_4600c_48x50g_40x100g.xml SAI_DUMP_STORE_PATH=/var/log/mellanox/sdk-dumps SAI_DUMP_STORE_AMOUNT=10 +SAI_DUMP_MFT_CFG_PATH=/etc/mft/fwtrace_cfg diff --git a/device/mellanox/x86_64-mlnx_msn4600c-r0/pcie.yaml b/device/mellanox/x86_64-mlnx_msn4600c-r0/pcie.yaml index 4356f48a250b..0ec69ca08c82 100644 --- a/device/mellanox/x86_64-mlnx_msn4600c-r0/pcie.yaml +++ b/device/mellanox/x86_64-mlnx_msn4600c-r0/pcie.yaml @@ -154,7 +154,7 @@ - bus: '09' dev: '00' fn: '0' - id: 1533 + id: '1533' name: 'Ethernet controller: Intel Corporation I210 Gigabit Network Connection (rev 03)' - bus: 'ff' diff --git a/device/mellanox/x86_64-mlnx_msn4700-r0/ACS-MSN4700/sai.profile b/device/mellanox/x86_64-mlnx_msn4700-r0/ACS-MSN4700/sai.profile index c6fb815168fe..8c76d4ca1bbc 100644 --- a/device/mellanox/x86_64-mlnx_msn4700-r0/ACS-MSN4700/sai.profile +++ b/device/mellanox/x86_64-mlnx_msn4700-r0/ACS-MSN4700/sai.profile @@ -1,3 +1,4 @@ SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/sai_4700.xml SAI_DUMP_STORE_PATH=/var/log/mellanox/sdk-dumps SAI_DUMP_STORE_AMOUNT=10 +SAI_DUMP_MFT_CFG_PATH=/etc/mft/fwtrace_cfg diff --git a/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-A96C8V8/sai.profile b/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-A96C8V8/sai.profile index 377656b4ca8f..b90eb55a9ba3 100644 --- a/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-A96C8V8/sai.profile +++ b/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-A96C8V8/sai.profile @@ -1,3 +1,4 @@ SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/sai_4700_8x200g_8x100g_96x25g.xml SAI_DUMP_STORE_PATH=/var/log/mellanox/sdk-dumps SAI_DUMP_STORE_AMOUNT=10 +SAI_DUMP_MFT_CFG_PATH=/etc/sonic/mft/fwtrace_cfg diff --git a/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-C128/sai.profile b/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-C128/sai.profile index d20b5e46b843..cd04cc332c5d 100644 --- a/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-C128/sai.profile +++ b/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-C128/sai.profile @@ -1,3 +1,4 @@ SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/sai_4700_128x100g.xml SAI_DUMP_STORE_PATH=/var/log/mellanox/sdk-dumps SAI_DUMP_STORE_AMOUNT=10 +SAI_DUMP_MFT_CFG_PATH=/etc/sonic/mft/fwtrace_cfg diff --git a/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8C48/sai.profile b/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8C48/sai.profile index 6834ab76afc0..4fab1773b390 100644 --- a/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8C48/sai.profile +++ b/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-O8C48/sai.profile @@ -1,3 +1,4 @@ SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/sai_4700_8x400g_48x100g.xml SAI_DUMP_STORE_PATH=/var/log/mellanox/sdk-dumps SAI_DUMP_STORE_AMOUNT=10 +SAI_DUMP_MFT_CFG_PATH=/etc/sonic/mft/fwtrace_cfg diff --git a/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-V48C32/sai.profile b/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-V48C32/sai.profile index 42518df9d9e2..27e1cdad33b5 100644 --- a/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-V48C32/sai.profile +++ b/device/mellanox/x86_64-mlnx_msn4700-r0/Mellanox-SN4700-V48C32/sai.profile @@ -1,3 +1,4 @@ SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/sai_4700_32x100g_48x200g.xml SAI_DUMP_STORE_PATH=/var/log/mellanox/sdk-dumps SAI_DUMP_STORE_AMOUNT=10 +SAI_DUMP_MFT_CFG_PATH=/etc/sonic/mft/fwtrace_cfg diff --git a/device/mellanox/x86_64-nvidia_sn4800-r0/ACS-SN4800/sai.profile b/device/mellanox/x86_64-nvidia_sn4800-r0/ACS-SN4800/sai.profile index c00fc21f89c5..2ce406ef0185 100644 --- a/device/mellanox/x86_64-nvidia_sn4800-r0/ACS-SN4800/sai.profile +++ b/device/mellanox/x86_64-nvidia_sn4800-r0/ACS-SN4800/sai.profile @@ -1,3 +1,4 @@ SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/sai_4800.xml SAI_DUMP_STORE_PATH=/var/log/mellanox/sdk-dumps SAI_DUMP_STORE_AMOUNT=10 +SAI_DUMP_MFT_CFG_PATH=/etc/mft/fwtrace_cfg diff --git a/device/mellanox/x86_64-nvidia_sn5600-r0/ACS-SN5600/sai.profile b/device/mellanox/x86_64-nvidia_sn5600-r0/ACS-SN5600/sai.profile index b37ca8c3ed0c..00ef9280e0fe 100644 --- a/device/mellanox/x86_64-nvidia_sn5600-r0/ACS-SN5600/sai.profile +++ b/device/mellanox/x86_64-nvidia_sn5600-r0/ACS-SN5600/sai.profile @@ -1,3 +1,4 @@ SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/sai_5600.xml SAI_DUMP_STORE_PATH=/var/log/mellanox/sdk-dumps SAI_DUMP_STORE_AMOUNT=10 +SAI_DUMP_MFT_CFG_PATH=/etc/mft/fwtrace_cfg diff --git a/device/mellanox/x86_64-nvidia_sn5600_simx-r0/ACS-SN5600/sai.profile b/device/mellanox/x86_64-nvidia_sn5600_simx-r0/ACS-SN5600/sai.profile index b37ca8c3ed0c..00ef9280e0fe 100644 --- a/device/mellanox/x86_64-nvidia_sn5600_simx-r0/ACS-SN5600/sai.profile +++ b/device/mellanox/x86_64-nvidia_sn5600_simx-r0/ACS-SN5600/sai.profile @@ -1,3 +1,4 @@ SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/sai_5600.xml SAI_DUMP_STORE_PATH=/var/log/mellanox/sdk-dumps SAI_DUMP_STORE_AMOUNT=10 +SAI_DUMP_MFT_CFG_PATH=/etc/mft/fwtrace_cfg diff --git a/device/nokia/arm64-nokia_ixs7215_52xb-r0/Nokia-7215-A1/ASK-Board-AC5X-xb.md5 b/device/nokia/arm64-nokia_ixs7215_52xb-r0/Nokia-7215-A1/ASK-Board-AC5X-xb.md5 index 16326740c24b..64cb21addf3a 100644 --- a/device/nokia/arm64-nokia_ixs7215_52xb-r0/Nokia-7215-A1/ASK-Board-AC5X-xb.md5 +++ b/device/nokia/arm64-nokia_ixs7215_52xb-r0/Nokia-7215-A1/ASK-Board-AC5X-xb.md5 @@ -1 +1 @@ -8668dc21ae107bff2d5e4242fe532e38 \ No newline at end of file +ee44e299ca857b9f0abf2e804ec4850f \ No newline at end of file diff --git a/device/nokia/arm64-nokia_ixs7215_52xb-r0/Nokia-7215-A1/ASK-Board-AC5X-xb.xml b/device/nokia/arm64-nokia_ixs7215_52xb-r0/Nokia-7215-A1/ASK-Board-AC5X-xb.xml index 839af3d55daf..08936c1339e4 100644 --- a/device/nokia/arm64-nokia_ixs7215_52xb-r0/Nokia-7215-A1/ASK-Board-AC5X-xb.xml +++ b/device/nokia/arm64-nokia_ixs7215_52xb-r0/Nokia-7215-A1/ASK-Board-AC5X-xb.xml @@ -1,5 +1,5 @@ - + @@ -677,7 +677,7 @@ lowercase characters. 0 ASK-PP-AC5X-xb.xml ASK-L1-AC5X-xb.xml - na + sip6 0 @@ -694,6 +694,10 @@ lowercase characters. 0 + + 63 + false + 1 @@ -711,6 +715,10 @@ lowercase characters. 0 + + 63 + false + 2 @@ -728,6 +736,10 @@ lowercase characters. 0 + + 63 + false + 3 @@ -745,6 +757,10 @@ lowercase characters. 0 + + 63 + false + 4 @@ -762,6 +778,10 @@ lowercase characters. 0 + + 63 + false + 5 @@ -779,6 +799,10 @@ lowercase characters. 0 + + 63 + false + 6 @@ -796,6 +820,10 @@ lowercase characters. 0 + + 63 + false + 7 @@ -813,6 +841,10 @@ lowercase characters. 0 + + 63 + false + 8 @@ -830,6 +862,10 @@ lowercase characters. 0 + + 63 + false + 9 @@ -847,6 +883,10 @@ lowercase characters. 0 + + 63 + false + 10 @@ -864,6 +904,10 @@ lowercase characters. 0 + + 63 + false + 11 @@ -881,6 +925,10 @@ lowercase characters. 0 + + 63 + false + 12 @@ -898,6 +946,10 @@ lowercase characters. 0 + + 63 + false + 13 @@ -915,6 +967,10 @@ lowercase characters. 0 + + 63 + false + 14 @@ -932,6 +988,10 @@ lowercase characters. 0 + + 63 + false + 15 @@ -949,6 +1009,10 @@ lowercase characters. 0 + + 63 + false + 16 @@ -966,6 +1030,10 @@ lowercase characters. 0 + + 63 + false + 17 @@ -983,6 +1051,10 @@ lowercase characters. 0 + + 63 + false + 18 @@ -1000,6 +1072,10 @@ lowercase characters. 0 + + 63 + false + 19 @@ -1017,6 +1093,10 @@ lowercase characters. 0 + + 63 + false + 20 @@ -1034,6 +1114,10 @@ lowercase characters. 0 + + 63 + false + 21 @@ -1051,6 +1135,10 @@ lowercase characters. 0 + + 63 + false + 22 @@ -1068,6 +1156,10 @@ lowercase characters. 0 + + 63 + false + 23 @@ -1085,6 +1177,10 @@ lowercase characters. 0 + + 63 + false + 24 @@ -1102,6 +1198,10 @@ lowercase characters. 1 + + 63 + false + 25 @@ -1119,6 +1219,10 @@ lowercase characters. 1 + + 63 + false + 26 @@ -1136,6 +1240,10 @@ lowercase characters. 1 + + 63 + false + 27 @@ -1153,6 +1261,10 @@ lowercase characters. 1 + + 63 + false + 28 @@ -1170,6 +1282,10 @@ lowercase characters. 1 + + 63 + false + 29 @@ -1187,6 +1303,10 @@ lowercase characters. 1 + + 63 + false + 30 @@ -1204,6 +1324,10 @@ lowercase characters. 1 + + 63 + false + 31 @@ -1221,6 +1345,10 @@ lowercase characters. 1 + + 63 + false + 32 @@ -1238,6 +1366,10 @@ lowercase characters. 1 + + 63 + false + 33 @@ -1255,6 +1387,10 @@ lowercase characters. 1 + + 63 + false + 34 @@ -1272,6 +1408,10 @@ lowercase characters. 1 + + 63 + false + 35 @@ -1289,6 +1429,10 @@ lowercase characters. 1 + + 63 + false + 36 @@ -1306,6 +1450,10 @@ lowercase characters. 1 + + 63 + false + 37 @@ -1323,6 +1471,10 @@ lowercase characters. 1 + + 63 + false + 38 @@ -1340,6 +1492,10 @@ lowercase characters. 1 + + 63 + false + 39 @@ -1357,6 +1513,10 @@ lowercase characters. 1 + + 63 + false + 40 @@ -1374,6 +1534,10 @@ lowercase characters. 1 + + 63 + false + 41 @@ -1391,6 +1555,10 @@ lowercase characters. 1 + + 63 + false + 42 @@ -1408,6 +1576,10 @@ lowercase characters. 1 + + 63 + false + 43 @@ -1425,6 +1597,10 @@ lowercase characters. 1 + + 63 + false + 44 @@ -1442,6 +1618,10 @@ lowercase characters. 1 + + 63 + false + 45 @@ -1459,6 +1639,10 @@ lowercase characters. 1 + + 63 + false + 46 @@ -1476,6 +1660,10 @@ lowercase characters. 1 + + 63 + false + 47 @@ -1493,6 +1681,10 @@ lowercase characters. 1 + + 63 + false + 48 @@ -1507,6 +1699,14 @@ lowercase characters. NA + + 0 + + 2 + false + + false + 49 @@ -1521,6 +1721,14 @@ lowercase characters. NA + + 1 + + 2 + false + + false + 50 @@ -1535,6 +1743,14 @@ lowercase characters. NA + + 0 + + 2 + false + + false + 51 @@ -1549,6 +1765,14 @@ lowercase characters. NA + + 1 + + 2 + false + + false + 60 @@ -1570,6 +1794,157 @@ lowercase characters. NETWORK + + 0 + false + false + + + 1 + false + false + + + 2 + false + false + + + 3 + false + false + + + 4 + false + false + + + 5 + false + false + + + 6 + true + false + + + 7 + false + false + + + 8 + true + false + + + 9 + false + false + + + 10 + false + false + + + 11 + false + false + + + 0 + + ORDER_MODE_BY_PORT + BLINK_DUTY_CYCLE_1 + BLINK_DURATION_2 + BLINK_DUTY_CYCLE_1 + BLINK_DURATION_2 + PULSE_STRETCH_1 + false + 1627 + true + + 1 + true + + + 2 + true + + + 3 + true + + + 4 + 0 + 15 + false + + + 5 + 0 + 15 + false + + + 6 + true + + + 7 + true + + + 8 + true + + + 9 + true + + + 10 + true + + + 11 + true + + + 12 + true + + + 13 + true + + + 14 + true + + + 15 + true + + + 16 + true + + + + 2 + PORT_TYPE_XG + true + BLINK_SELECT_1 + false + false + true + + . diff --git a/device/nokia/arm64-nokia_ixs7215_52xb-r0/Nokia-7215-A1/ASK-L1-AC5X-xb.md5 b/device/nokia/arm64-nokia_ixs7215_52xb-r0/Nokia-7215-A1/ASK-L1-AC5X-xb.md5 index 5205acca39e0..e8daa7b6f38b 100644 --- a/device/nokia/arm64-nokia_ixs7215_52xb-r0/Nokia-7215-A1/ASK-L1-AC5X-xb.md5 +++ b/device/nokia/arm64-nokia_ixs7215_52xb-r0/Nokia-7215-A1/ASK-L1-AC5X-xb.md5 @@ -1 +1 @@ -6d7161d3d4fdf922d5f26243642d8110 \ No newline at end of file +8d006b7a29c75f81b641df68102a6aa3 \ No newline at end of file diff --git a/device/nokia/arm64-nokia_ixs7215_52xb-r0/Nokia-7215-A1/ASK-L1-AC5X-xb.xml b/device/nokia/arm64-nokia_ixs7215_52xb-r0/Nokia-7215-A1/ASK-L1-AC5X-xb.xml index 2e612d014eba..534b218554f1 100644 --- a/device/nokia/arm64-nokia_ixs7215_52xb-r0/Nokia-7215-A1/ASK-L1-AC5X-xb.xml +++ b/device/nokia/arm64-nokia_ixs7215_52xb-r0/Nokia-7215-A1/ASK-L1-AC5X-xb.xml @@ -1,5 +1,5 @@ - + diff --git a/device/nokia/arm64-nokia_ixs7215_52xb-r0/Nokia-7215-A1/ASK-PP-AC5X-xb.md5 b/device/nokia/arm64-nokia_ixs7215_52xb-r0/Nokia-7215-A1/ASK-PP-AC5X-xb.md5 index e0b9509d1dab..de23afe95536 100644 --- a/device/nokia/arm64-nokia_ixs7215_52xb-r0/Nokia-7215-A1/ASK-PP-AC5X-xb.md5 +++ b/device/nokia/arm64-nokia_ixs7215_52xb-r0/Nokia-7215-A1/ASK-PP-AC5X-xb.md5 @@ -1 +1 @@ -75737f56687883d181ea3da8d1c24da6 \ No newline at end of file +b42f2a2be9da6c7752c0807f9dee48bf \ No newline at end of file diff --git a/device/nokia/arm64-nokia_ixs7215_52xb-r0/Nokia-7215-A1/ASK-PP-AC5X-xb.xml b/device/nokia/arm64-nokia_ixs7215_52xb-r0/Nokia-7215-A1/ASK-PP-AC5X-xb.xml index 50daefc694d6..ad457fe7db03 100644 --- a/device/nokia/arm64-nokia_ixs7215_52xb-r0/Nokia-7215-A1/ASK-PP-AC5X-xb.xml +++ b/device/nokia/arm64-nokia_ixs7215_52xb-r0/Nokia-7215-A1/ASK-PP-AC5X-xb.xml @@ -1,5 +1,5 @@ - + diff --git a/device/nokia/arm64-nokia_ixs7215_52xb-r0/Nokia-7215-A1/SAI-AC5X-xb.md5 b/device/nokia/arm64-nokia_ixs7215_52xb-r0/Nokia-7215-A1/SAI-AC5X-xb.md5 index ee93b73e2534..951dd3007b76 100644 --- a/device/nokia/arm64-nokia_ixs7215_52xb-r0/Nokia-7215-A1/SAI-AC5X-xb.md5 +++ b/device/nokia/arm64-nokia_ixs7215_52xb-r0/Nokia-7215-A1/SAI-AC5X-xb.md5 @@ -1 +1 @@ -ac4217e114fbd773ddbc6e0053948000 \ No newline at end of file +b43a871130f9e59ac21a74940574558f \ No newline at end of file diff --git a/device/nokia/arm64-nokia_ixs7215_52xb-r0/Nokia-7215-A1/SAI-AC5X-xb.xml b/device/nokia/arm64-nokia_ixs7215_52xb-r0/Nokia-7215-A1/SAI-AC5X-xb.xml index 6f45980f2c74..5e374fdb06b1 100644 --- a/device/nokia/arm64-nokia_ixs7215_52xb-r0/Nokia-7215-A1/SAI-AC5X-xb.xml +++ b/device/nokia/arm64-nokia_ixs7215_52xb-r0/Nokia-7215-A1/SAI-AC5X-xb.xml @@ -1,5 +1,5 @@ - + diff --git a/device/nokia/arm64-nokia_ixs7215_52xb-r0/platform.json b/device/nokia/arm64-nokia_ixs7215_52xb-r0/platform.json index 633d92d7b522..0ddd1f39583a 100644 --- a/device/nokia/arm64-nokia_ixs7215_52xb-r0/platform.json +++ b/device/nokia/arm64-nokia_ixs7215_52xb-r0/platform.json @@ -11,28 +11,46 @@ ], "fans": [ { - "name": "Fan1" + "name": "Fan1", + "status_led": { + "controllable": false + } }, { - "name": "Fan2" + "name": "Fan2", + "status_led": { + "controllable": false + } } ], "fan_drawers": [ { "name": "drawer1", + "status_led": { + "controllable": false + }, "max_consumed_power": false, "fans": [ { - "name": "Fan1" + "name": "Fan1", + "status_led": { + "controllable": false + } } ] }, { "name": "drawer2", + "status_led": { + "controllable": false + }, "max_consumed_power": false, "fans": [ { - "name": "Fan2" + "name": "Fan2", + "status_led": { + "controllable": false + } } ] } @@ -40,6 +58,9 @@ "psus": [ { "name": "PSU1", + "status_led": { + "controllable": false + }, "current": false, "power": false, "max_power": false, @@ -49,6 +70,9 @@ }, { "name": "PSU2", + "status_led": { + "controllable": false + }, "current": false, "power": false, "max_power": false, @@ -73,12 +97,18 @@ "high-crit-threshold": false }, { - "name": "CPU Core", + "name": "AC5X CORE", "controllable": false, "low-threshold": false, - "high-threshold": false, "low-crit-threshold": false, "high-crit-threshold": false + }, + { + "name": "OOB PHY", + "controllable": false, + "low-threshold": false, + "high-threshold": false, + "low-crit-threshold": false } ], "sfps": [ @@ -227,16 +257,16 @@ "name": "Ethernet47" }, { - "name": "Ethernet48" + "name": "SFP48" }, { - "name": "Ethernet49" + "name": "SFP49" }, { - "name": "Ethernet50" + "name": "SFP50" }, { - "name": "Ethernet51" + "name": "SFP51" } ] }, diff --git a/device/nokia/arm64-nokia_ixs7215_52xb-r0/platform_reboot b/device/nokia/arm64-nokia_ixs7215_52xb-r0/platform_reboot old mode 100755 new mode 100644 diff --git a/device/nokia/arm64-nokia_ixs7215_52xb-r0/plugins/led_control.py b/device/nokia/arm64-nokia_ixs7215_52xb-r0/plugins/led_control.py new file mode 100644 index 000000000000..0a2dfdd7fc93 --- /dev/null +++ b/device/nokia/arm64-nokia_ixs7215_52xb-r0/plugins/led_control.py @@ -0,0 +1,119 @@ +# +# led_control.py +# +# Platform-specific LED control functionality for SONiC +# + +try: + from sonic_led.led_control_base import LedControlBase + import os + import time + import syslog + import sonic_platform.platform + import sonic_platform.chassis +except ImportError as e: + raise ImportError(str(e) + " - required module not found") + +CPLD_DIR = "/sys/bus/i2c/devices/0-0041/" + +def DBG_PRINT(str): + syslog.openlog("nokia-led") + syslog.syslog(syslog.LOG_INFO, str) + syslog.closelog() + + +class LedControl(LedControlBase): + """Platform specific LED control class""" + + # Constructor + def __init__(self): + self.chassis = sonic_platform.platform.Platform().get_chassis() + self._initDefaultConfig() + + def _initDefaultConfig(self): + # The fan tray leds and system led managed by new chassis class API + # leaving only a couple other front panel leds to be done old style + DBG_PRINT("starting system leds") + self._initSystemLed() + DBG_PRINT(" led done") + + def _read_sysfs_file(self, sysfs_file): + # On successful read, returns the value read from given + # reg_name and on failure returns 'ERR' + rv = 'ERR' + + if (not os.path.isfile(sysfs_file)): + return rv + try: + with open(sysfs_file, 'r') as fd: + rv = fd.read() + except Exception as e: + rv = 'ERR' + + rv = rv.rstrip('\r\n') + rv = rv.lstrip(" ") + return rv + + def _write_sysfs_file(self, sysfs_file, value): + # On successful write, the value read will be written on + # reg_name and on failure returns 'ERR' + rv = 'ERR' + + if (not os.path.isfile(sysfs_file)): + return rv + try: + with open(sysfs_file, 'w') as fd: + rv = fd.write(str(value)) + except Exception as e: + rv = 'ERR' + + return rv + + def _initSystemLed(self): + # Front Panel System LEDs setting + oldfan = 0xf # 0=amber, 1=green + oldpsu = 0xf # 0=amber, 1=green + + # Write sys led + status = self._write_sysfs_file(CPLD_DIR+"system_led", "green") + if status == "ERR": + DBG_PRINT(" System LED NOT set correctly") + else: + DBG_PRINT(" System LED set O.K. ") + + # Timer loop to monitor and set front panel Status, Fan, and PSU LEDs + while True: + # Front Panel FAN Panel LED setting + if (self.chassis.get_fan(0).get_status() == self.chassis.get_fan(1).get_status() == True): + if (os.path.isfile(CPLD_DIR+"fan_led")): + if oldfan != 0x1: + self._write_sysfs_file(CPLD_DIR+"fan_led", "green") + oldfan = 0x1 + else: + oldfan = 0xf + else: + if (os.path.isfile(CPLD_DIR+"fan_led")): + if oldfan != 0x0: + self._write_sysfs_file(CPLD_DIR+"fan_led", "amber") + oldfan = 0x0 + else: + oldfan = 0xf + + # Front Panel PSU Panel LED setting + if (self.chassis.get_psu(0).get_status() == self.chassis.get_psu(1).get_status() == True): + if (os.path.isfile(CPLD_DIR+"psu_led")): + if oldpsu != 0x1: + self._write_sysfs_file(CPLD_DIR+"psu_led", "green") + oldpsu = 0x1 + else: + oldpsu = 0xf + else: + if (os.path.isfile(CPLD_DIR+"psu_led")): + if oldpsu != 0x0: + status = self._write_sysfs_file(CPLD_DIR+"psu_led", "amber") + oldpsu = 0x0 + else: + oldpsu = 0xf + + time.sleep(6) + diff --git a/device/nokia/arm64-nokia_ixs7215_52xb-r0/pmon_daemon_control.json b/device/nokia/arm64-nokia_ixs7215_52xb-r0/pmon_daemon_control.json new file mode 100644 index 000000000000..f6445f875922 --- /dev/null +++ b/device/nokia/arm64-nokia_ixs7215_52xb-r0/pmon_daemon_control.json @@ -0,0 +1,3 @@ +{ + "skip_pcied": true +} diff --git a/device/nokia/arm64-nokia_ixs7215_52xb-r0/thermal_policy.json b/device/nokia/arm64-nokia_ixs7215_52xb-r0/thermal_policy.json index fb6e044e266c..d20c3b817add 100644 --- a/device/nokia/arm64-nokia_ixs7215_52xb-r0/thermal_policy.json +++ b/device/nokia/arm64-nokia_ixs7215_52xb-r0/thermal_policy.json @@ -43,7 +43,9 @@ "actions": [ { "type": "thermal.temp_check_and_set_all_fan_speed", - "default_speed": "50", + "default_speed": "25", + "threshold1_speed": "40", + "threshold2_speed": "75", "hightemp_speed": "100" } ] diff --git a/device/nokia/x86_64-nokia_ixr7250e_36x400g-r0/Nokia-IXR7250E-36x100G/0/pg_profile_lookup.ini b/device/nokia/x86_64-nokia_ixr7250e_36x400g-r0/Nokia-IXR7250E-36x100G/0/pg_profile_lookup.ini index 7eb58931c209..e8289ab03112 100644 --- a/device/nokia/x86_64-nokia_ixr7250e_36x400g-r0/Nokia-IXR7250E-36x100G/0/pg_profile_lookup.ini +++ b/device/nokia/x86_64-nokia_ixr7250e_36x400g-r0/Nokia-IXR7250E-36x100G/0/pg_profile_lookup.ini @@ -1,12 +1,17 @@ # PG lossless profiles. -# speed cable size xon xoff threshold xon_offset +# speed cable size xon xoff threshold xon_offset + 40000 300m 1280 2560 69632 0 1280 100000 300m 1280 2560 110592 0 1280 400000 300m 1280 2560 315392 0 1280 + 40000 1000m 1280 2560 114688 0 1280 100000 1000m 1280 2560 225280 0 1280 400000 1000m 1280 2560 778240 0 1280 + 40000 2000m 1280 2560 184320 0 1280 100000 2000m 1280 2560 393216 0 1280 400000 2000m 1280 2560 1445888 0 1280 - 100000 80000m 1280 2560 1388544 0 1280 - 400000 80000m 1280 2560 5435392 0 1280 - 100000 120000m 1280 2560 2056192 0 1280 - 400000 120000m 1280 2560 8093696 0 1280 + 40000 80000m 1280 2560 5369856 0 1280 + 100000 80000m 1280 2560 13357056 0 1280 + 400000 80000m 1280 2560 53305344 0 1280 + 40000 120000m 1280 2560 8028160 0 1280 + 100000 120000m 1280 2560 20004864 0 1280 + 400000 120000m 1280 2560 79900672 0 1280 diff --git a/device/nokia/x86_64-nokia_ixr7250e_36x400g-r0/Nokia-IXR7250E-36x100G/1/pg_profile_lookup.ini b/device/nokia/x86_64-nokia_ixr7250e_36x400g-r0/Nokia-IXR7250E-36x100G/1/pg_profile_lookup.ini index 7eb58931c209..e8289ab03112 100644 --- a/device/nokia/x86_64-nokia_ixr7250e_36x400g-r0/Nokia-IXR7250E-36x100G/1/pg_profile_lookup.ini +++ b/device/nokia/x86_64-nokia_ixr7250e_36x400g-r0/Nokia-IXR7250E-36x100G/1/pg_profile_lookup.ini @@ -1,12 +1,17 @@ # PG lossless profiles. -# speed cable size xon xoff threshold xon_offset +# speed cable size xon xoff threshold xon_offset + 40000 300m 1280 2560 69632 0 1280 100000 300m 1280 2560 110592 0 1280 400000 300m 1280 2560 315392 0 1280 + 40000 1000m 1280 2560 114688 0 1280 100000 1000m 1280 2560 225280 0 1280 400000 1000m 1280 2560 778240 0 1280 + 40000 2000m 1280 2560 184320 0 1280 100000 2000m 1280 2560 393216 0 1280 400000 2000m 1280 2560 1445888 0 1280 - 100000 80000m 1280 2560 1388544 0 1280 - 400000 80000m 1280 2560 5435392 0 1280 - 100000 120000m 1280 2560 2056192 0 1280 - 400000 120000m 1280 2560 8093696 0 1280 + 40000 80000m 1280 2560 5369856 0 1280 + 100000 80000m 1280 2560 13357056 0 1280 + 400000 80000m 1280 2560 53305344 0 1280 + 40000 120000m 1280 2560 8028160 0 1280 + 100000 120000m 1280 2560 20004864 0 1280 + 400000 120000m 1280 2560 79900672 0 1280 diff --git a/device/nokia/x86_64-nokia_ixr7250e_36x400g-r0/platform_reboot b/device/nokia/x86_64-nokia_ixr7250e_36x400g-r0/platform_reboot index 180db164df69..43aace70f7ee 100755 --- a/device/nokia/x86_64-nokia_ixr7250e_36x400g-r0/platform_reboot +++ b/device/nokia/x86_64-nokia_ixr7250e_36x400g-r0/platform_reboot @@ -1,23 +1,24 @@ #!/bin/bash -update_reboot_cause_for_supervisor_reboot() +update_reboot_cause() { DEVICE_MGR_REBOOT_FILE=/tmp/device_mgr_reboot REBOOT_CAUSE_FILE=/host/reboot-cause/reboot-cause.txt - TMP_REBOOT_CAUSE_FILE=/tmp/tmp-reboot-cause.txt - if [ -f $DEVICE_MGR_REBOOT_FILE ]; then - if [ -f $REBOOT_CAUSE_FILE ]; then - t1=`sudo grep "User: ," $REBOOT_CAUSE_FILE` - if [ ! -z "$t1" ]; then - echo $t1 | sed 's/reboot/reboot from Supervisor/g' | sed 's/User: /User: admin/g' > $TMP_REBOOT_CAUSE_FILE - cp $TMP_REBOOT_CAUSE_FILE $REBOOT_CAUSE_FILE - fi + DEVICE_REBOOT_CAUSE_FILE=/etc/opt/srlinux/reboot-cause.txt + if [ -e $DEVICE_MGR_REBOOT_FILE ]; then + if [ -e $DEVICE_REBOOT_CAUSE_FILE ]; then + cp -f $DEVICE_REBOOT_CAUSE_FILE $REBOOT_CAUSE_FILE fi + rm -f $DEVICE_MGR_REBOOT_FILE + else + touch /etc/opt/srlinux/devmgr_reboot_cause.done + rm -f $DEVICE_REBOOT_CAUSE_FILE &> /dev/null fi + sync } # update the reboot_cuase file when reboot is trigger by device-mgr -update_reboot_cause_for_supervisor_reboot +update_reboot_cause systemctl stop nokia-watchdog.service sleep 2 @@ -25,7 +26,5 @@ echo "w" > /dev/watchdog kick_date=`date -u` echo "last watchdog kick $kick_date" > /var/log/nokia-watchdog-last.log rm -f /sys/firmware/efi/efivars/dump-* -touch /etc/opt/srlinux/devmgr_reboot_cause.done -rm -f /etc/opt/srlinux/reboot-cause.txt sync exec /sbin/reboot $@ diff --git a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/RA-B6510-48V8C/port_config.ini b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/RA-B6510-48V8C/port_config.ini index 823f53160c33..b71ad39648c9 100755 --- a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/RA-B6510-48V8C/port_config.ini +++ b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/RA-B6510-48V8C/port_config.ini @@ -1,57 +1,57 @@ -# name lanes alias index speed admin_status -Ethernet1 1 twentyfiveGigE0/1 0 25000 up -Ethernet2 2 twentyfiveGigE0/2 1 25000 up -Ethernet3 3 twentyfiveGigE0/3 2 25000 up -Ethernet4 4 twentyfiveGigE0/4 3 25000 up -Ethernet5 5 twentyfiveGigE0/5 4 25000 up -Ethernet6 6 twentyfiveGigE0/6 5 25000 up -Ethernet7 7 twentyfiveGigE0/7 6 25000 up -Ethernet8 8 twentyfiveGigE0/8 7 25000 up -Ethernet9 13 twentyfiveGigE0/9 8 25000 up -Ethernet10 14 twentyfiveGigE0/10 9 25000 up -Ethernet11 15 twentyfiveGigE0/11 10 25000 up -Ethernet12 16 twentyfiveGigE0/12 11 25000 up -Ethernet13 21 twentyfiveGigE0/13 12 25000 up -Ethernet14 22 twentyfiveGigE0/14 13 25000 up -Ethernet15 23 twentyfiveGigE0/15 14 25000 up -Ethernet16 24 twentyfiveGigE0/16 15 25000 up -Ethernet17 29 twentyfiveGigE0/17 16 25000 up -Ethernet18 30 twentyfiveGigE0/18 17 25000 up -Ethernet19 31 twentyfiveGigE0/19 18 25000 up -Ethernet20 32 twentyfiveGigE0/20 19 25000 up -Ethernet21 33 twentyfiveGigE0/21 20 25000 up -Ethernet22 34 twentyfiveGigE0/22 21 25000 up -Ethernet23 35 twentyfiveGigE0/23 22 25000 up -Ethernet24 36 twentyfiveGigE0/24 23 25000 up -Ethernet25 41 twentyfiveGigE0/25 24 25000 up -Ethernet26 42 twentyfiveGigE0/26 25 25000 up -Ethernet27 43 twentyfiveGigE0/27 26 25000 up -Ethernet28 44 twentyfiveGigE0/28 27 25000 up -Ethernet29 49 twentyfiveGigE0/29 28 25000 up -Ethernet30 50 twentyfiveGigE0/30 29 25000 up -Ethernet31 51 twentyfiveGigE0/31 30 25000 up -Ethernet32 52 twentyfiveGigE0/32 31 25000 up -Ethernet33 57 twentyfiveGigE0/33 32 25000 up -Ethernet34 58 twentyfiveGigE0/34 33 25000 up -Ethernet35 59 twentyfiveGigE0/35 34 25000 up -Ethernet36 60 twentyfiveGigE0/36 35 25000 up -Ethernet37 61 twentyfiveGigE0/37 36 25000 up -Ethernet38 62 twentyfiveGigE0/38 37 25000 up -Ethernet39 63 twentyfiveGigE0/39 38 25000 up -Ethernet40 64 twentyfiveGigE0/40 39 25000 up -Ethernet41 65 twentyfiveGigE0/41 40 25000 up -Ethernet42 66 twentyfiveGigE0/42 41 25000 up -Ethernet43 67 twentyfiveGigE0/43 42 25000 up -Ethernet44 68 twentyfiveGigE0/44 43 25000 up -Ethernet45 69 twentyfiveGigE0/45 44 25000 up -Ethernet46 70 twentyfiveGigE0/46 45 25000 up -Ethernet47 71 twentyfiveGigE0/47 46 25000 up -Ethernet48 72 twentyfiveGigE0/48 47 25000 up -Ethernet49 85,86,87,88 hundredGigE0/1 48 100000 up -Ethernet50 77,78,79,80 hundredGigE0/2 49 100000 up -Ethernet51 97,98,99,100 hundredGigE0/3 50 100000 up -Ethernet52 93,94,95,96 hundredGigE0/4 51 100000 up -Ethernet53 113,114,115,116 hundredGigE0/5 52 100000 up -Ethernet54 105,106,107,108 hundredGigE0/6 53 100000 up -Ethernet55 121,122,123,124 hundredGigE0/7 54 100000 up -Ethernet56 125,126,127,128 hundredGigE0/8 55 100000 up +# name lanes alias index speed admin_status +Ethernet1 57 twentyfiveGigE0/1 1 25000 up +Ethernet2 58 twentyfiveGigE0/2 2 25000 up +Ethernet3 59 twentyfiveGigE0/3 3 25000 up +Ethernet4 60 twentyfiveGigE0/4 4 25000 up +Ethernet5 61 twentyfiveGigE0/5 5 25000 up +Ethernet6 62 twentyfiveGigE0/6 6 25000 up +Ethernet7 63 twentyfiveGigE0/7 7 25000 up +Ethernet8 64 twentyfiveGigE0/8 8 25000 up +Ethernet9 1 twentyfiveGigE0/9 9 25000 up +Ethernet10 2 twentyfiveGigE0/10 10 25000 up +Ethernet11 3 twentyfiveGigE0/11 11 25000 up +Ethernet12 4 twentyfiveGigE0/12 12 25000 up +Ethernet13 5 twentyfiveGigE0/13 13 25000 up +Ethernet14 6 twentyfiveGigE0/14 14 25000 up +Ethernet15 7 twentyfiveGigE0/15 15 25000 up +Ethernet16 8 twentyfiveGigE0/16 16 25000 up +Ethernet17 13 twentyfiveGigE0/17 17 25000 up +Ethernet18 14 twentyfiveGigE0/18 18 25000 up +Ethernet19 15 twentyfiveGigE0/19 19 25000 up +Ethernet20 16 twentyfiveGigE0/20 20 25000 up +Ethernet21 21 twentyfiveGigE0/21 21 25000 up +Ethernet22 22 twentyfiveGigE0/22 22 25000 up +Ethernet23 23 twentyfiveGigE0/23 23 25000 up +Ethernet24 24 twentyfiveGigE0/24 24 25000 up +Ethernet25 29 twentyfiveGigE0/25 25 25000 up +Ethernet26 30 twentyfiveGigE0/26 26 25000 up +Ethernet27 31 twentyfiveGigE0/27 27 25000 up +Ethernet28 32 twentyfiveGigE0/28 28 25000 up +Ethernet29 33 twentyfiveGigE0/29 29 25000 up +Ethernet30 34 twentyfiveGigE0/30 30 25000 up +Ethernet31 35 twentyfiveGigE0/31 31 25000 up +Ethernet32 36 twentyfiveGigE0/32 32 25000 up +Ethernet33 41 twentyfiveGigE0/33 33 25000 up +Ethernet34 42 twentyfiveGigE0/34 34 25000 up +Ethernet35 43 twentyfiveGigE0/35 35 25000 up +Ethernet36 44 twentyfiveGigE0/36 36 25000 up +Ethernet37 49 twentyfiveGigE0/37 37 25000 up +Ethernet38 50 twentyfiveGigE0/38 38 25000 up +Ethernet39 51 twentyfiveGigE0/39 39 25000 up +Ethernet40 52 twentyfiveGigE0/40 40 25000 up +Ethernet41 65 twentyfiveGigE0/41 41 25000 up +Ethernet42 66 twentyfiveGigE0/42 42 25000 up +Ethernet43 67 twentyfiveGigE0/43 43 25000 up +Ethernet44 68 twentyfiveGigE0/44 44 25000 up +Ethernet45 69 twentyfiveGigE0/45 45 25000 up +Ethernet46 70 twentyfiveGigE0/46 46 25000 up +Ethernet47 71 twentyfiveGigE0/47 47 25000 up +Ethernet48 72 twentyfiveGigE0/48 48 25000 up +Ethernet49 85,86,87,88 hundredGigE0/1 49 100000 up +Ethernet50 77,78,79,80 hundredGigE0/2 50 100000 up +Ethernet51 97,98,99,100 hundredGigE0/3 51 100000 up +Ethernet52 93,94,95,96 hundredGigE0/4 52 100000 up +Ethernet53 113,114,115,116 hundredGigE0/5 53 100000 up +Ethernet54 105,106,107,108 hundredGigE0/6 54 100000 up +Ethernet55 121,122,123,124 hundredGigE0/7 55 100000 up +Ethernet56 125,126,127,128 hundredGigE0/8 56 100000 up diff --git a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/RA-B6510-48V8C/td3-ra-b6510-48v8c-48x25G+8x100G.config.bcm b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/RA-B6510-48V8C/td3-ra-b6510-48v8c-48x25G+8x100G.config.bcm index 27656bd3d466..e86eb1b9fa36 100644 --- a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/RA-B6510-48V8C/td3-ra-b6510-48v8c-48x25G+8x100G.config.bcm +++ b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/RA-B6510-48V8C/td3-ra-b6510-48v8c-48x25G+8x100G.config.bcm @@ -5,6 +5,8 @@ l3_alpm_enable=2 ipv6_lpm_128b_enable=0x1 l2xmsg_mode=0 l3_max_ecmp_mode=1 +svi_my_station_optimization=1 +sai_nbr_bcast_ifp_optimized=2 bcm_num_cos=8 bcm_stat_interval=2000000 cdma_timeout_usec=3000000 @@ -22,381 +24,579 @@ oversubscribe_mode=1 parity_enable=1 pbmp_gport_stack.0=0x0000000000000000000000000000000000000000000000000000000000000000 #pbmp_xport_xe.0=0x00000000000000000000000000000000888ffffffffffff9fffffffffffffffe -pbmp_xport_xe=0x488080808808087f9fe1e1e1fe1e1e1fe -phy_chain_rx_lane_map_physical{1.0}=0x1032 +pbmp_xport_xe=0xffffffffffffffffffffffffffffffffffffffffe +port_flex_enable=1 +phy_chain_tx_lane_map_physical{57.0}=0x0123 +phy_chain_tx_lane_map_physical{61.0}=0x0123 phy_chain_tx_lane_map_physical{1.0}=0x0123 -phy_chain_rx_lane_map_physical{5.0}=0x1032 phy_chain_tx_lane_map_physical{5.0}=0x0123 -phy_chain_rx_lane_map_physical{13.0}=0x1032 phy_chain_tx_lane_map_physical{13.0}=0x0123 -phy_chain_rx_lane_map_physical{21.0}=0x1032 phy_chain_tx_lane_map_physical{21.0}=0x0123 -phy_chain_rx_lane_map_physical{29.0}=0x1032 phy_chain_tx_lane_map_physical{29.0}=0x0123 -phy_chain_rx_lane_map_physical{33.0}=0x1032 phy_chain_tx_lane_map_physical{33.0}=0x0123 -phy_chain_rx_lane_map_physical{41.0}=0x1032 phy_chain_tx_lane_map_physical{41.0}=0x0123 -phy_chain_rx_lane_map_physical{49.0}=0x1032 phy_chain_tx_lane_map_physical{49.0}=0x0123 +phy_chain_tx_lane_map_physical{65.0}=0x3210 +phy_chain_tx_lane_map_physical{69.0}=0x3210 +phy_chain_tx_lane_map_physical{85.0}=0x3210 +phy_chain_tx_lane_map_physical{77.0}=0x0213 +phy_chain_tx_lane_map_physical{97.0}=0x3210 +phy_chain_tx_lane_map_physical{93.0}=0x0213 +phy_chain_tx_lane_map_physical{113.0}=0x3210 +phy_chain_tx_lane_map_physical{105.0}=0x0213 +phy_chain_tx_lane_map_physical{121.0}=0x3120 +phy_chain_tx_lane_map_physical{125.0}=0x1203 + phy_chain_rx_lane_map_physical{57.0}=0x1032 -phy_chain_tx_lane_map_physical{57.0}=0x0123 phy_chain_rx_lane_map_physical{61.0}=0x1032 -phy_chain_tx_lane_map_physical{61.0}=0x0123 +phy_chain_rx_lane_map_physical{1.0}=0x1032 +phy_chain_rx_lane_map_physical{5.0}=0x1032 +phy_chain_rx_lane_map_physical{13.0}=0x1032 +phy_chain_rx_lane_map_physical{21.0}=0x1032 +phy_chain_rx_lane_map_physical{29.0}=0x1032 +phy_chain_rx_lane_map_physical{33.0}=0x1032 +phy_chain_rx_lane_map_physical{41.0}=0x1032 +phy_chain_rx_lane_map_physical{49.0}=0x1032 phy_chain_rx_lane_map_physical{65.0}=0x2301 -phy_chain_tx_lane_map_physical{65.0}=0x3210 phy_chain_rx_lane_map_physical{69.0}=0x2301 -phy_chain_tx_lane_map_physical{69.0}=0x3210 -phy_chain_rx_lane_map_physical{77.0}=0x1032 -phy_chain_tx_lane_map_physical{77.0}=0x3210 phy_chain_rx_lane_map_physical{85.0}=0x1032 -phy_chain_tx_lane_map_physical{85.0}=0x3210 -phy_chain_rx_lane_map_physical{93.0}=0x1032 -phy_chain_tx_lane_map_physical{93.0}=0x3210 +phy_chain_rx_lane_map_physical{77.0}=0x1032 phy_chain_rx_lane_map_physical{97.0}=0x1032 -phy_chain_tx_lane_map_physical{97.0}=0x3210 -phy_chain_rx_lane_map_physical{105.0}=0x1032 -phy_chain_tx_lane_map_physical{105.0}=0x3210 +phy_chain_rx_lane_map_physical{93.0}=0x1032 phy_chain_rx_lane_map_physical{113.0}=0x1032 -phy_chain_tx_lane_map_physical{113.0}=0x3210 +phy_chain_rx_lane_map_physical{105.0}=0x1032 phy_chain_rx_lane_map_physical{121.0}=0x2031 -phy_chain_tx_lane_map_physical{121.0}=0x3210 -phy_chain_rx_lane_map_physical{125.0}=0x1032 -phy_chain_tx_lane_map_physical{125.0}=0x1203 -phy_chain_tx_polarity_flip_physical{1.0}=0x1 -phy_chain_rx_polarity_flip_physical{1.0}=0x0 +phy_chain_rx_lane_map_physical{125.0}=0x1023 + +portmap_57=57:25 +portmap_58=58:25 +portmap_59=59:25 +portmap_60=60:25 +portmap_61=61:25 +portmap_62=62:25 +portmap_63=63:25 +portmap_64=64:25 +portmap_1=1:25 +portmap_2=2:25 +portmap_3=3:25 +portmap_4=4:25 +portmap_5=5:25 +portmap_6=6:25 +portmap_7=7:25 +portmap_8=8:25 +portmap_13=13:25 +portmap_14=14:25 +portmap_15=15:25 +portmap_16=16:25 +portmap_21=21:25 +portmap_22=22:25 +portmap_23=23:25 +portmap_24=24:25 +portmap_29=29:25 +portmap_30=30:25 +portmap_31=31:25 +portmap_32=32:25 +portmap_33=33:25 +portmap_34=34:25 +portmap_35=35:25 +portmap_36=36:25 +portmap_41=41:25 +portmap_42=42:25 +portmap_43=43:25 +portmap_44=44:25 +portmap_49=49:25 +portmap_50=50:25 +portmap_51=51:25 +portmap_52=52:25 +portmap_67=65:25 +portmap_68=66:25 +portmap_69=67:25 +portmap_70=68:25 +portmap_71=69:25 +portmap_72=70:25 +portmap_73=71:25 +portmap_74=72:25 +portmap_87=85:100 +portmap_79=77:100 +portmap_99=97:100 +portmap_95=93:100 +portmap_115=113:100 +portmap_107=105:100 +portmap_123=121:100 +portmap_127=125:100 + +dport_map_port_57=1 +dport_map_port_58=2 +dport_map_port_59=3 +dport_map_port_60=4 +dport_map_port_61=5 +dport_map_port_62=6 +dport_map_port_63=7 +dport_map_port_64=8 +dport_map_port_1=9 +dport_map_port_2=10 +dport_map_port_3=11 +dport_map_port_4=12 +dport_map_port_5=13 +dport_map_port_6=14 +dport_map_port_7=15 +dport_map_port_8=16 +dport_map_port_13=17 +dport_map_port_14=18 +dport_map_port_15=19 +dport_map_port_16=20 +dport_map_port_21=21 +dport_map_port_22=22 +dport_map_port_23=23 +dport_map_port_24=24 +dport_map_port_29=25 +dport_map_port_30=26 +dport_map_port_31=27 +dport_map_port_32=28 +dport_map_port_33=29 +dport_map_port_34=30 +dport_map_port_35=31 +dport_map_port_36=32 +dport_map_port_41=33 +dport_map_port_42=34 +dport_map_port_43=35 +dport_map_port_44=36 +dport_map_port_49=37 +dport_map_port_50=38 +dport_map_port_51=39 +dport_map_port_52=40 +dport_map_port_67=41 +dport_map_port_68=42 +dport_map_port_69=43 +dport_map_port_70=44 +dport_map_port_71=45 +dport_map_port_72=46 +dport_map_port_73=47 +dport_map_port_74=48 +dport_map_port_87=49 +dport_map_port_79=50 +dport_map_port_99=51 +dport_map_port_95=52 +dport_map_port_115=53 +dport_map_port_107=54 +dport_map_port_123=55 +dport_map_port_127=56 + +phy_chain_tx_polarity_flip_physical{57.0}=0x1 +phy_chain_tx_polarity_flip_physical{58.0}=0x0 +phy_chain_tx_polarity_flip_physical{59.0}=0x1 +phy_chain_tx_polarity_flip_physical{60.0}=0x0 +phy_chain_tx_polarity_flip_physical{61.0}=0x1 +phy_chain_tx_polarity_flip_physical{62.0}=0x0 +phy_chain_tx_polarity_flip_physical{63.0}=0x1 +phy_chain_tx_polarity_flip_physical{64.0}=0x0 +phy_chain_tx_polarity_flip_physical{1.0}=0x0 phy_chain_tx_polarity_flip_physical{2.0}=0x0 -phy_chain_rx_polarity_flip_physical{2.0}=0x0 -phy_chain_tx_polarity_flip_physical{3.0}=0x1 -phy_chain_rx_polarity_flip_physical{3.0}=0x0 +phy_chain_tx_polarity_flip_physical{3.0}=0x0 phy_chain_tx_polarity_flip_physical{4.0}=0x0 -phy_chain_rx_polarity_flip_physical{4.0}=0x0 -phy_chain_tx_polarity_flip_physical{5.0}=0x1 -phy_chain_rx_polarity_flip_physical{5.0}=0x0 +phy_chain_tx_polarity_flip_physical{5.0}=0x0 phy_chain_tx_polarity_flip_physical{6.0}=0x0 -phy_chain_rx_polarity_flip_physical{6.0}=0x0 -phy_chain_tx_polarity_flip_physical{7.0}=0x1 -phy_chain_rx_polarity_flip_physical{7.0}=0x0 +phy_chain_tx_polarity_flip_physical{7.0}=0x0 phy_chain_tx_polarity_flip_physical{8.0}=0x0 -phy_chain_rx_polarity_flip_physical{8.0}=0x0 phy_chain_tx_polarity_flip_physical{13.0}=0x0 -phy_chain_rx_polarity_flip_physical{13.0}=0x0 phy_chain_tx_polarity_flip_physical{14.0}=0x0 -phy_chain_rx_polarity_flip_physical{14.0}=0x0 phy_chain_tx_polarity_flip_physical{15.0}=0x0 -phy_chain_rx_polarity_flip_physical{15.0}=0x0 phy_chain_tx_polarity_flip_physical{16.0}=0x0 -phy_chain_rx_polarity_flip_physical{16.0}=0x0 -phy_chain_tx_polarity_flip_physical{21.0}=0x1 -phy_chain_rx_polarity_flip_physical{21.0}=0x0 +phy_chain_tx_polarity_flip_physical{21.0}=0x0 phy_chain_tx_polarity_flip_physical{22.0}=0x0 -phy_chain_rx_polarity_flip_physical{22.0}=0x0 -phy_chain_tx_polarity_flip_physical{23.0}=0x1 -phy_chain_rx_polarity_flip_physical{23.0}=0x0 +phy_chain_tx_polarity_flip_physical{23.0}=0x0 phy_chain_tx_polarity_flip_physical{24.0}=0x0 -phy_chain_rx_polarity_flip_physical{24.0}=0x0 phy_chain_tx_polarity_flip_physical{29.0}=0x0 -phy_chain_rx_polarity_flip_physical{29.0}=0x1 phy_chain_tx_polarity_flip_physical{30.0}=0x0 -phy_chain_rx_polarity_flip_physical{30.0}=0x1 phy_chain_tx_polarity_flip_physical{31.0}=0x0 -phy_chain_rx_polarity_flip_physical{31.0}=0x1 phy_chain_tx_polarity_flip_physical{32.0}=0x0 -phy_chain_rx_polarity_flip_physical{32.0}=0x1 phy_chain_tx_polarity_flip_physical{33.0}=0x0 -phy_chain_rx_polarity_flip_physical{33.0}=0x0 phy_chain_tx_polarity_flip_physical{34.0}=0x0 -phy_chain_rx_polarity_flip_physical{34.0}=0x0 phy_chain_tx_polarity_flip_physical{35.0}=0x0 -phy_chain_rx_polarity_flip_physical{35.0}=0x0 phy_chain_tx_polarity_flip_physical{36.0}=0x0 -phy_chain_rx_polarity_flip_physical{36.0}=0x0 phy_chain_tx_polarity_flip_physical{41.0}=0x0 -phy_chain_rx_polarity_flip_physical{41.0}=0x0 phy_chain_tx_polarity_flip_physical{42.0}=0x0 -phy_chain_rx_polarity_flip_physical{42.0}=0x0 phy_chain_tx_polarity_flip_physical{43.0}=0x0 -phy_chain_rx_polarity_flip_physical{43.0}=0x0 phy_chain_tx_polarity_flip_physical{44.0}=0x0 -phy_chain_rx_polarity_flip_physical{44.0}=0x0 phy_chain_tx_polarity_flip_physical{49.0}=0x0 -phy_chain_rx_polarity_flip_physical{49.0}=0x0 phy_chain_tx_polarity_flip_physical{50.0}=0x0 -phy_chain_rx_polarity_flip_physical{50.0}=0x0 phy_chain_tx_polarity_flip_physical{51.0}=0x0 -phy_chain_rx_polarity_flip_physical{51.0}=0x0 phy_chain_tx_polarity_flip_physical{52.0}=0x0 -phy_chain_rx_polarity_flip_physical{52.0}=0x0 -phy_chain_tx_polarity_flip_physical{57.0}=0x0 +phy_chain_tx_polarity_flip_physical{65.0}=0x0 +phy_chain_tx_polarity_flip_physical{66.0}=0x0 +phy_chain_tx_polarity_flip_physical{67.0}=0x0 +phy_chain_tx_polarity_flip_physical{68.0}=0x0 +phy_chain_tx_polarity_flip_physical{69.0}=0x0 +phy_chain_tx_polarity_flip_physical{70.0}=0x0 +phy_chain_tx_polarity_flip_physical{71.0}=0x0 +phy_chain_tx_polarity_flip_physical{72.0}=0x0 +phy_chain_tx_polarity_flip_physical{85.0}=0x0 +phy_chain_tx_polarity_flip_physical{86.0}=0x0 +phy_chain_tx_polarity_flip_physical{87.0}=0x1 +phy_chain_tx_polarity_flip_physical{88.0}=0x0 +phy_chain_tx_polarity_flip_physical{77.0}=0x1 +phy_chain_tx_polarity_flip_physical{78.0}=0x0 +phy_chain_tx_polarity_flip_physical{79.0}=0x1 +phy_chain_tx_polarity_flip_physical{80.0}=0x0 +phy_chain_tx_polarity_flip_physical{97.0}=0x0 +phy_chain_tx_polarity_flip_physical{98.0}=0x0 +phy_chain_tx_polarity_flip_physical{99.0}=0x1 +phy_chain_tx_polarity_flip_physical{100.0}=0x0 +phy_chain_tx_polarity_flip_physical{93.0}=0x0 +phy_chain_tx_polarity_flip_physical{94.0}=0x1 +phy_chain_tx_polarity_flip_physical{95.0}=0x1 +phy_chain_tx_polarity_flip_physical{96.0}=0x0 +phy_chain_tx_polarity_flip_physical{113.0}=0x0 +phy_chain_tx_polarity_flip_physical{114.0}=0x0 +phy_chain_tx_polarity_flip_physical{115.0}=0x1 +phy_chain_tx_polarity_flip_physical{116.0}=0x0 +phy_chain_tx_polarity_flip_physical{105.0}=0x0 +phy_chain_tx_polarity_flip_physical{106.0}=0x1 +phy_chain_tx_polarity_flip_physical{107.0}=0x1 +phy_chain_tx_polarity_flip_physical{108.0}=0x0 +phy_chain_tx_polarity_flip_physical{121.0}=0x1 +phy_chain_tx_polarity_flip_physical{122.0}=0x0 +phy_chain_tx_polarity_flip_physical{123.0}=0x1 +phy_chain_tx_polarity_flip_physical{124.0}=0x0 +phy_chain_tx_polarity_flip_physical{125.0}=0x1 +phy_chain_tx_polarity_flip_physical{126.0}=0x0 +phy_chain_tx_polarity_flip_physical{127.0}=0x1 +phy_chain_tx_polarity_flip_physical{128.0}=0x1 + phy_chain_rx_polarity_flip_physical{57.0}=0x0 -phy_chain_tx_polarity_flip_physical{58.0}=0x0 phy_chain_rx_polarity_flip_physical{58.0}=0x0 -phy_chain_tx_polarity_flip_physical{59.0}=0x0 phy_chain_rx_polarity_flip_physical{59.0}=0x0 -phy_chain_tx_polarity_flip_physical{60.0}=0x0 phy_chain_rx_polarity_flip_physical{60.0}=0x0 -phy_chain_tx_polarity_flip_physical{61.0}=0x0 phy_chain_rx_polarity_flip_physical{61.0}=0x1 -phy_chain_tx_polarity_flip_physical{62.0}=0x0 phy_chain_rx_polarity_flip_physical{62.0}=0x1 -phy_chain_tx_polarity_flip_physical{63.0}=0x0 phy_chain_rx_polarity_flip_physical{63.0}=0x1 -phy_chain_tx_polarity_flip_physical{64.0}=0x0 phy_chain_rx_polarity_flip_physical{64.0}=0x1 -phy_chain_tx_polarity_flip_physical{65.0}=0x0 +phy_chain_rx_polarity_flip_physical{1.0}=0x1 +phy_chain_rx_polarity_flip_physical{2.0}=0x1 +phy_chain_rx_polarity_flip_physical{3.0}=0x1 +phy_chain_rx_polarity_flip_physical{4.0}=0x1 +phy_chain_rx_polarity_flip_physical{5.0}=0x0 +phy_chain_rx_polarity_flip_physical{6.0}=0x0 +phy_chain_rx_polarity_flip_physical{7.0}=0x0 +phy_chain_rx_polarity_flip_physical{8.0}=0x0 +phy_chain_rx_polarity_flip_physical{13.0}=0x0 +phy_chain_rx_polarity_flip_physical{14.0}=0x0 +phy_chain_rx_polarity_flip_physical{15.0}=0x0 +phy_chain_rx_polarity_flip_physical{16.0}=0x0 +phy_chain_rx_polarity_flip_physical{21.0}=0x0 +phy_chain_rx_polarity_flip_physical{22.0}=0x0 +phy_chain_rx_polarity_flip_physical{23.0}=0x0 +phy_chain_rx_polarity_flip_physical{24.0}=0x0 +phy_chain_rx_polarity_flip_physical{29.0}=0x0 +phy_chain_rx_polarity_flip_physical{30.0}=0x1 +phy_chain_rx_polarity_flip_physical{31.0}=0x0 +phy_chain_rx_polarity_flip_physical{32.0}=0x0 +phy_chain_rx_polarity_flip_physical{33.0}=0x1 +phy_chain_rx_polarity_flip_physical{34.0}=0x1 +phy_chain_rx_polarity_flip_physical{35.0}=0x1 +phy_chain_rx_polarity_flip_physical{36.0}=0x1 +phy_chain_rx_polarity_flip_physical{41.0}=0x1 +phy_chain_rx_polarity_flip_physical{42.0}=0x1 +phy_chain_rx_polarity_flip_physical{43.0}=0x1 +phy_chain_rx_polarity_flip_physical{44.0}=0x1 +phy_chain_rx_polarity_flip_physical{49.0}=0x1 +phy_chain_rx_polarity_flip_physical{50.0}=0x1 +phy_chain_rx_polarity_flip_physical{51.0}=0x1 +phy_chain_rx_polarity_flip_physical{52.0}=0x1 phy_chain_rx_polarity_flip_physical{65.0}=0x1 -phy_chain_tx_polarity_flip_physical{66.0}=0x0 phy_chain_rx_polarity_flip_physical{66.0}=0x1 -phy_chain_tx_polarity_flip_physical{67.0}=0x0 phy_chain_rx_polarity_flip_physical{67.0}=0x1 -phy_chain_tx_polarity_flip_physical{68.0}=0x0 phy_chain_rx_polarity_flip_physical{68.0}=0x1 -phy_chain_tx_polarity_flip_physical{69.0}=0x0 phy_chain_rx_polarity_flip_physical{69.0}=0x0 -phy_chain_tx_polarity_flip_physical{70.0}=0x0 phy_chain_rx_polarity_flip_physical{70.0}=0x0 -phy_chain_tx_polarity_flip_physical{71.0}=0x0 phy_chain_rx_polarity_flip_physical{71.0}=0x0 -phy_chain_tx_polarity_flip_physical{72.0}=0x0 phy_chain_rx_polarity_flip_physical{72.0}=0x0 -phy_chain_tx_polarity_flip_physical{85.0}=0x1 phy_chain_rx_polarity_flip_physical{85.0}=0x1 -phy_chain_tx_polarity_flip_physical{86.0}=0x0 phy_chain_rx_polarity_flip_physical{86.0}=0x1 -phy_chain_tx_polarity_flip_physical{87.0}=0x1 phy_chain_rx_polarity_flip_physical{87.0}=0x1 -phy_chain_tx_polarity_flip_physical{88.0}=0x0 phy_chain_rx_polarity_flip_physical{88.0}=0x1 -phy_chain_tx_polarity_flip_physical{77.0}=0x1 -phy_chain_rx_polarity_flip_physical{77.0}=0x1 -phy_chain_tx_polarity_flip_physical{78.0}=0x1 +phy_chain_rx_polarity_flip_physical{77.0}=0x0 phy_chain_rx_polarity_flip_physical{78.0}=0x0 -phy_chain_tx_polarity_flip_physical{79.0}=0x1 -phy_chain_rx_polarity_flip_physical{79.0}=0x1 -phy_chain_tx_polarity_flip_physical{80.0}=0x1 -phy_chain_rx_polarity_flip_physical{80.0}=0x1 -phy_chain_tx_polarity_flip_physical{97.0}=0x1 +phy_chain_rx_polarity_flip_physical{79.0}=0x0 +phy_chain_rx_polarity_flip_physical{80.0}=0x0 phy_chain_rx_polarity_flip_physical{97.0}=0x0 -phy_chain_tx_polarity_flip_physical{98.0}=0x0 phy_chain_rx_polarity_flip_physical{98.0}=0x0 -phy_chain_tx_polarity_flip_physical{99.0}=0x1 phy_chain_rx_polarity_flip_physical{99.0}=0x0 -phy_chain_tx_polarity_flip_physical{100.0}=0x0 phy_chain_rx_polarity_flip_physical{100.0}=0x0 -phy_chain_tx_polarity_flip_physical{93.0}=0x1 -phy_chain_rx_polarity_flip_physical{93.0}=0x1 -phy_chain_tx_polarity_flip_physical{94.0}=0x1 +phy_chain_rx_polarity_flip_physical{93.0}=0x0 phy_chain_rx_polarity_flip_physical{94.0}=0x0 -phy_chain_tx_polarity_flip_physical{95.0}=0x1 -phy_chain_rx_polarity_flip_physical{95.0}=0x1 -phy_chain_tx_polarity_flip_physical{96.0}=0x1 -phy_chain_rx_polarity_flip_physical{96.0}=0x1 -phy_chain_tx_polarity_flip_physical{113.0}=0x1 +phy_chain_rx_polarity_flip_physical{95.0}=0x0 +phy_chain_rx_polarity_flip_physical{96.0}=0x0 phy_chain_rx_polarity_flip_physical{113.0}=0x1 -phy_chain_tx_polarity_flip_physical{114.0}=0x0 phy_chain_rx_polarity_flip_physical{114.0}=0x1 -phy_chain_tx_polarity_flip_physical{115.0}=0x1 phy_chain_rx_polarity_flip_physical{115.0}=0x1 -phy_chain_tx_polarity_flip_physical{116.0}=0x0 phy_chain_rx_polarity_flip_physical{116.0}=0x1 -phy_chain_tx_polarity_flip_physical{105.0}=0x1 -phy_chain_rx_polarity_flip_physical{105.0}=0x1 -phy_chain_tx_polarity_flip_physical{106.0}=0x1 +phy_chain_rx_polarity_flip_physical{105.0}=0x0 phy_chain_rx_polarity_flip_physical{106.0}=0x0 -phy_chain_tx_polarity_flip_physical{107.0}=0x1 -phy_chain_rx_polarity_flip_physical{107.0}=0x1 -phy_chain_tx_polarity_flip_physical{108.0}=0x1 -phy_chain_rx_polarity_flip_physical{108.0}=0x1 -phy_chain_tx_polarity_flip_physical{121.0}=0x1 +phy_chain_rx_polarity_flip_physical{107.0}=0x0 +phy_chain_rx_polarity_flip_physical{108.0}=0x0 phy_chain_rx_polarity_flip_physical{121.0}=0x1 -phy_chain_tx_polarity_flip_physical{122.0}=0x0 -phy_chain_rx_polarity_flip_physical{122.0}=0x0 -phy_chain_tx_polarity_flip_physical{123.0}=0x1 +phy_chain_rx_polarity_flip_physical{122.0}=0x1 phy_chain_rx_polarity_flip_physical{123.0}=0x0 -phy_chain_tx_polarity_flip_physical{124.0}=0x0 phy_chain_rx_polarity_flip_physical{124.0}=0x1 -phy_chain_tx_polarity_flip_physical{125.0}=0x0 -phy_chain_rx_polarity_flip_physical{125.0}=0x0 -phy_chain_tx_polarity_flip_physical{126.0}=0x1 -phy_chain_rx_polarity_flip_physical{126.0}=0x1 -phy_chain_tx_polarity_flip_physical{127.0}=0x0 +phy_chain_rx_polarity_flip_physical{125.0}=0x1 +phy_chain_rx_polarity_flip_physical{126.0}=0x0 phy_chain_rx_polarity_flip_physical{127.0}=0x0 -phy_chain_tx_polarity_flip_physical{128.0}=0x0 phy_chain_rx_polarity_flip_physical{128.0}=0x0 -port_flex_enable=1 -portmap_1=1:25 -portmap_2=2:25 -portmap_3=3:25 -portmap_4=4:25 -portmap_5=5:25 -portmap_6=6:25 -portmap_7=7:25 -portmap_8=8:25 -portmap_13=13:25 -portmap_14=14:25 -portmap_15=15:25 -portmap_16=16:25 -portmap_21=21:25 -portmap_22=22:25 -portmap_23=23:25 -portmap_24=24:25 -portmap_29=29:25 -portmap_30=30:25 -portmap_31=31:25 -portmap_32=32:25 -portmap_33=33:25 -portmap_34=34:25 -portmap_35=35:25 -portmap_36=36:25 -portmap_41=41:25 -portmap_42=42:25 -portmap_43=43:25 -portmap_44=44:25 -portmap_49=49:25 -portmap_50=50:25 -portmap_51=51:25 -portmap_52=52:25 -portmap_57=57:25 -portmap_58=58:25 -portmap_59=59:25 -portmap_60=60:25 -portmap_61=61:25 -portmap_62=62:25 -portmap_63=63:25 -portmap_64=64:25 -portmap_67=65:25 -portmap_68=66:25 -portmap_69=67:25 -portmap_70=68:25 -portmap_71=69:25 -portmap_72=70:25 -portmap_73=71:25 -portmap_74=72:25 -portmap_79=77:100 -portmap_87=85:100 -portmap_95=93:100 -portmap_99=97:100 -portmap_107=105:100 -portmap_115=113:100 -portmap_123=121:100 -portmap_127=125:100 -dport_map_port_1=1 -dport_map_port_2=2 -dport_map_port_3=3 -dport_map_port_4=4 -dport_map_port_5=5 -dport_map_port_6=6 -dport_map_port_7=7 -dport_map_port_8=8 -dport_map_port_13=9 -dport_map_port_14=10 -dport_map_port_15=11 -dport_map_port_16=12 -dport_map_port_21=13 -dport_map_port_22=14 -dport_map_port_23=15 -dport_map_port_24=16 -dport_map_port_29=17 -dport_map_port_30=18 -dport_map_port_31=19 -dport_map_port_32=20 -dport_map_port_33=21 -dport_map_port_34=22 -dport_map_port_35=23 -dport_map_port_36=24 -dport_map_port_41=25 -dport_map_port_42=26 -dport_map_port_43=27 -dport_map_port_44=28 -dport_map_port_49=29 -dport_map_port_50=30 -dport_map_port_51=31 -dport_map_port_52=32 -dport_map_port_57=33 -dport_map_port_58=34 -dport_map_port_59=35 -dport_map_port_60=36 -dport_map_port_61=37 -dport_map_port_62=38 -dport_map_port_63=39 -dport_map_port_64=40 -dport_map_port_67=41 -dport_map_port_68=42 -dport_map_port_69=43 -dport_map_port_70=44 -dport_map_port_71=45 -dport_map_port_72=46 -dport_map_port_73=47 -dport_map_port_74=48 -dport_map_port_87=49 -dport_map_port_79=50 -dport_map_port_99=51 -dport_map_port_95=52 -dport_map_port_115=53 -dport_map_port_107=54 -dport_map_port_123=55 -dport_map_port_127=56 +serdes_preemphasis_lane0_57=0x0f480d +serdes_preemphasis_lane1_57=0x0f480d +serdes_preemphasis_lane2_57=0x0f480d +serdes_preemphasis_lane3_57=0x0f480d +serdes_preemphasis_lane0_58=0x0f480d +serdes_preemphasis_lane1_58=0x0f480d +serdes_preemphasis_lane2_58=0x0f480d +serdes_preemphasis_lane3_58=0x0f480d +serdes_preemphasis_lane0_59=0x0f480d +serdes_preemphasis_lane1_59=0x0f480d +serdes_preemphasis_lane2_59=0x0f480d +serdes_preemphasis_lane3_59=0x0f480d +serdes_preemphasis_lane0_60=0x0f480d +serdes_preemphasis_lane1_60=0x0f480d +serdes_preemphasis_lane2_60=0x0f480d +serdes_preemphasis_lane3_60=0x0f480d +serdes_preemphasis_lane0_61=0x0f480d +serdes_preemphasis_lane1_61=0x0f480d +serdes_preemphasis_lane2_61=0x0f480d +serdes_preemphasis_lane3_61=0x0f480d +serdes_preemphasis_lane0_62=0x0f480d +serdes_preemphasis_lane1_62=0x0f480d +serdes_preemphasis_lane2_62=0x0f480d +serdes_preemphasis_lane3_62=0x0f480d +serdes_preemphasis_lane0_63=0x0f480d +serdes_preemphasis_lane1_63=0x0f480d +serdes_preemphasis_lane2_63=0x0f480d +serdes_preemphasis_lane3_63=0x0f480d +serdes_preemphasis_lane0_64=0x0f480d +serdes_preemphasis_lane1_64=0x0f480d +serdes_preemphasis_lane2_64=0x0f480d +serdes_preemphasis_lane3_64=0x0f480d +serdes_preemphasis_lane0_1=0x0f480d +serdes_preemphasis_lane1_1=0x0f480d +serdes_preemphasis_lane2_1=0x0f480d +serdes_preemphasis_lane3_1=0x0f480d +serdes_preemphasis_lane0_2=0x0d4b0c +serdes_preemphasis_lane1_2=0x0d4b0c +serdes_preemphasis_lane2_2=0x0d4b0c +serdes_preemphasis_lane3_2=0x0d4b0c +serdes_preemphasis_lane0_3=0x0f480d +serdes_preemphasis_lane1_3=0x0f480d +serdes_preemphasis_lane2_3=0x0f480d +serdes_preemphasis_lane3_3=0x0f480d +serdes_preemphasis_lane0_4=0x0d4b0c +serdes_preemphasis_lane1_4=0x0d4b0c +serdes_preemphasis_lane2_4=0x0d4b0c +serdes_preemphasis_lane3_4=0x0d4b0c +serdes_preemphasis_lane0_5=0x0f480d +serdes_preemphasis_lane1_5=0x0f480d +serdes_preemphasis_lane2_5=0x0f480d +serdes_preemphasis_lane3_5=0x0f480d +serdes_preemphasis_lane0_6=0x0d4b0c +serdes_preemphasis_lane1_6=0x0d4b0c +serdes_preemphasis_lane2_6=0x0d4b0c +serdes_preemphasis_lane3_6=0x0d4b0c +serdes_preemphasis_lane0_7=0x0f480d +serdes_preemphasis_lane1_7=0x0f480d +serdes_preemphasis_lane2_7=0x0f480d +serdes_preemphasis_lane3_7=0x0f480d +serdes_preemphasis_lane0_8=0x0d4b0c +serdes_preemphasis_lane1_8=0x0d4b0c +serdes_preemphasis_lane2_8=0x0d4b0c +serdes_preemphasis_lane3_8=0x0d4b0c +serdes_preemphasis_lane0_13=0x0f480d +serdes_preemphasis_lane1_13=0x0f480d +serdes_preemphasis_lane2_13=0x0f480d +serdes_preemphasis_lane3_13=0x0f480d +serdes_preemphasis_lane0_14=0x0d4b0c +serdes_preemphasis_lane1_14=0x0d4b0c +serdes_preemphasis_lane2_14=0x0d4b0c +serdes_preemphasis_lane3_14=0x0d4b0c +serdes_preemphasis_lane0_15=0x0f480d +serdes_preemphasis_lane1_15=0x0f480d +serdes_preemphasis_lane2_15=0x0f480d +serdes_preemphasis_lane3_15=0x0f480d +serdes_preemphasis_lane0_16=0x0d4b0c +serdes_preemphasis_lane1_16=0x0d4b0c +serdes_preemphasis_lane2_16=0x0d4b0c +serdes_preemphasis_lane3_16=0x0d4b0c +serdes_preemphasis_lane0_21=0x0d4b0c +serdes_preemphasis_lane1_21=0x0d4b0c +serdes_preemphasis_lane2_21=0x0d4b0c +serdes_preemphasis_lane3_21=0x0d4b0c +serdes_preemphasis_lane0_22=0x0d4b0c +serdes_preemphasis_lane1_22=0x0d4b0c +serdes_preemphasis_lane2_22=0x0d4b0c +serdes_preemphasis_lane3_22=0x0d4b0c +serdes_preemphasis_lane0_23=0x0d4b0c +serdes_preemphasis_lane1_23=0x0d4b0c +serdes_preemphasis_lane2_23=0x0d4b0c +serdes_preemphasis_lane3_23=0x0d4b0c +serdes_preemphasis_lane0_24=0x0d4b0c +serdes_preemphasis_lane1_24=0x0d4b0c +serdes_preemphasis_lane2_24=0x0d4b0c +serdes_preemphasis_lane3_24=0x0d4b0c +serdes_preemphasis_lane0_29=0x0d4b0c +serdes_preemphasis_lane1_29=0x0d4b0c +serdes_preemphasis_lane2_29=0x0d4b0c +serdes_preemphasis_lane3_29=0x0d4b0c +serdes_preemphasis_lane0_30=0x0d4b0c +serdes_preemphasis_lane1_30=0x0d4b0c +serdes_preemphasis_lane2_30=0x0d4b0c +serdes_preemphasis_lane3_30=0x0d4b0c +serdes_preemphasis_lane0_31=0x0d4b0c +serdes_preemphasis_lane1_31=0x0d4b0c +serdes_preemphasis_lane2_31=0x0d4b0c +serdes_preemphasis_lane3_31=0x0d4b0c +serdes_preemphasis_lane0_32=0x0d4b0c +serdes_preemphasis_lane1_32=0x0d4b0c +serdes_preemphasis_lane2_32=0x0d4b0c +serdes_preemphasis_lane3_32=0x0d4b0c +serdes_preemphasis_lane0_33=0x0d4b0c +serdes_preemphasis_lane1_33=0x0d4b0c +serdes_preemphasis_lane2_33=0x0d4b0c +serdes_preemphasis_lane3_33=0x0d4b0c +serdes_preemphasis_lane0_34=0x0d4b0c +serdes_preemphasis_lane1_34=0x0d4b0c +serdes_preemphasis_lane2_34=0x0d4b0c +serdes_preemphasis_lane3_34=0x0d4b0c +serdes_preemphasis_lane0_35=0x0d4b0c +serdes_preemphasis_lane1_35=0x0d4b0c +serdes_preemphasis_lane2_35=0x0d4b0c +serdes_preemphasis_lane3_35=0x0d4b0c +serdes_preemphasis_lane0_36=0x0d4b0c +serdes_preemphasis_lane1_36=0x0d4b0c +serdes_preemphasis_lane2_36=0x0d4b0c +serdes_preemphasis_lane3_36=0x0d4b0c +serdes_preemphasis_lane0_41=0x0d4b0c +serdes_preemphasis_lane1_41=0x0d4b0c +serdes_preemphasis_lane2_41=0x0d4b0c +serdes_preemphasis_lane3_41=0x0d4b0c +serdes_preemphasis_lane0_42=0x0d4b0c +serdes_preemphasis_lane1_42=0x0d4b0c +serdes_preemphasis_lane2_42=0x0d4b0c +serdes_preemphasis_lane3_42=0x0d4b0c +serdes_preemphasis_lane0_43=0x0d4b0c +serdes_preemphasis_lane1_43=0x0d4b0c +serdes_preemphasis_lane2_43=0x0d4b0c +serdes_preemphasis_lane3_43=0x0d4b0c +serdes_preemphasis_lane0_44=0x0d4b0c +serdes_preemphasis_lane1_44=0x0d4b0c +serdes_preemphasis_lane2_44=0x0d4b0c +serdes_preemphasis_lane3_44=0x0d4b0c +serdes_preemphasis_lane0_49=0x0f480d +serdes_preemphasis_lane1_49=0x0f480d +serdes_preemphasis_lane2_49=0x0f480d +serdes_preemphasis_lane3_49=0x0f480d +serdes_preemphasis_lane0_50=0x0d4b0c +serdes_preemphasis_lane1_50=0x0d4b0c +serdes_preemphasis_lane2_50=0x0d4b0c +serdes_preemphasis_lane3_50=0x0d4b0c +serdes_preemphasis_lane0_51=0x0f480d +serdes_preemphasis_lane1_51=0x0f480d +serdes_preemphasis_lane2_51=0x0f480d +serdes_preemphasis_lane3_51=0x0f480d +serdes_preemphasis_lane0_52=0x0d4b0c +serdes_preemphasis_lane1_52=0x0d4b0c +serdes_preemphasis_lane2_52=0x0d4b0c +serdes_preemphasis_lane3_52=0x0d4b0c +serdes_preemphasis_lane0_67=0x0d4b0c +serdes_preemphasis_lane1_67=0x0d4b0c +serdes_preemphasis_lane2_67=0x0d4b0c +serdes_preemphasis_lane3_67=0x0d4b0c +serdes_preemphasis_lane0_68=0x0d4b0c +serdes_preemphasis_lane1_68=0x0d4b0c +serdes_preemphasis_lane2_68=0x0d4b0c +serdes_preemphasis_lane3_68=0x0d4b0c +serdes_preemphasis_lane0_69=0x0d4b0c +serdes_preemphasis_lane1_69=0x0d4b0c +serdes_preemphasis_lane2_69=0x0d4b0c +serdes_preemphasis_lane3_69=0x0d4b0c +serdes_preemphasis_lane0_70=0x0d4b0c +serdes_preemphasis_lane1_70=0x0d4b0c +serdes_preemphasis_lane2_70=0x0d4b0c +serdes_preemphasis_lane3_70=0x0d4b0c +serdes_preemphasis_lane0_71=0x0d4b0c +serdes_preemphasis_lane1_71=0x0d4b0c +serdes_preemphasis_lane2_71=0x0d4b0c +serdes_preemphasis_lane3_71=0x0d4b0c +serdes_preemphasis_lane0_72=0x0d4b0c +serdes_preemphasis_lane1_72=0x0d4b0c +serdes_preemphasis_lane2_72=0x0d4b0c +serdes_preemphasis_lane3_72=0x0d4b0c +serdes_preemphasis_lane0_73=0x0d4b0c +serdes_preemphasis_lane1_73=0x0d4b0c +serdes_preemphasis_lane2_73=0x0d4b0c +serdes_preemphasis_lane3_73=0x0d4b0c +serdes_preemphasis_lane0_74=0x0d4b0c +serdes_preemphasis_lane1_74=0x0d4b0c +serdes_preemphasis_lane2_74=0x0d4b0c +serdes_preemphasis_lane3_74=0x0d4b0c +serdes_preemphasis_lane0_87=0x0d4b0c +serdes_preemphasis_lane1_87=0x0d4b0c +serdes_preemphasis_lane2_87=0x0d4b0c +serdes_preemphasis_lane3_87=0x0d4b0c +serdes_preemphasis_lane0_79=0x0d4b0c +serdes_preemphasis_lane1_79=0x0d4b0c +serdes_preemphasis_lane2_79=0x0d4b0c +serdes_preemphasis_lane3_79=0x0d4b0c +serdes_preemphasis_lane0_99=0x0d4b0c +serdes_preemphasis_lane1_99=0x0d4b0c +serdes_preemphasis_lane2_99=0x0d4b0c +serdes_preemphasis_lane3_99=0x0d4b0c +serdes_preemphasis_lane0_95=0x0d4b0c +serdes_preemphasis_lane1_95=0x0d4b0c +serdes_preemphasis_lane2_95=0x0d4b0c +serdes_preemphasis_lane3_95=0x0d4b0c +serdes_preemphasis_lane0_115=0x0d4b0c +serdes_preemphasis_lane1_115=0x0d4b0c +serdes_preemphasis_lane2_115=0x0d4b0c +serdes_preemphasis_lane3_115=0x0d4b0c +serdes_preemphasis_lane0_107=0x0d4b0c +serdes_preemphasis_lane1_107=0x0d4b0c +serdes_preemphasis_lane2_107=0x0d4b0c +serdes_preemphasis_lane3_107=0x0d4b0c +serdes_preemphasis_lane0_123=0x14460a +serdes_preemphasis_lane1_123=0x14460a +serdes_preemphasis_lane2_123=0x14460a +serdes_preemphasis_lane3_123=0x14460a +serdes_preemphasis_lane0_127=0x14460a +serdes_preemphasis_lane1_127=0x14460a +serdes_preemphasis_lane2_127=0x14460a +serdes_preemphasis_lane3_127=0x14460a -serdes_if_type_1=13 -serdes_if_type_2=13 -serdes_if_type_3=13 -serdes_if_type_4=13 -serdes_if_type_5=13 -serdes_if_type_6=13 -serdes_if_type_7=13 -serdes_if_type_8=13 -serdes_if_type_13=13 -serdes_if_type_14=13 -serdes_if_type_15=13 -serdes_if_type_16=13 -serdes_if_type_21=13 -serdes_if_type_22=13 -serdes_if_type_23=13 -serdes_if_type_24=13 -serdes_if_type_29=13 -serdes_if_type_30=13 -serdes_if_type_31=13 -serdes_if_type_32=13 -serdes_if_type_33=13 -serdes_if_type_34=13 -serdes_if_type_35=13 -serdes_if_type_36=13 -serdes_if_type_41=13 -serdes_if_type_42=13 -serdes_if_type_43=13 -serdes_if_type_44=13 -serdes_if_type_49=13 -serdes_if_type_50=13 -serdes_if_type_51=13 -serdes_if_type_52=13 -serdes_if_type_57=13 -serdes_if_type_58=13 -serdes_if_type_59=13 -serdes_if_type_60=13 -serdes_if_type_61=13 -serdes_if_type_62=13 -serdes_if_type_63=13 -serdes_if_type_64=13 -serdes_if_type_67=13 -serdes_if_type_68=13 -serdes_if_type_69=13 -serdes_if_type_70=13 -serdes_if_type_71=13 -serdes_if_type_72=13 -serdes_if_type_73=13 -serdes_if_type_74=13 -serdes_if_type_87=14 -serdes_if_type_79=14 -serdes_if_type_99=14 -serdes_if_type_95=14 -serdes_if_type_115=14 -serdes_if_type_107=14 -serdes_if_type_123=14 -serdes_if_type_127=14 reglist_enable=1 -scache_filename=/tmp/scache +scache_filename=/var/warmboot/wbscache schan_intr_enable=0 -stable_size=0x5500000 +stable_size=0x55000000 +stable_location=3 +warmboot_knet_shutdown_mode=1 tdma_timeout_usec=3000000 + +#vxlan flex flow mode +flow_init_mode=1 + +riot_enable=1 +riot_overlay_l3_intf_mem_size=4096 +riot_overlay_l3_egress_mem_size=32768 +riot_overlay_ecmp_resilient_hash_size=16384 + +l3_ecmp_levels=2 + +use_all_splithorizon_groups=1 +sai_tunnel_support=1 + +#This property allows to enable L2 FDB entry to discard based on Source Mac +sai_fdb_entry_l2_discard_src_enable=1 + +#RDMA +sai_pfc_defaults_disable=1 +sai_optimized_mmu=1 + +#ACL wb count +ctr_evict_enable=0 diff --git a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/custom_led.bin b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/custom_led.bin index 1fe5585e0779..e02f94e7ed87 100644 Binary files a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/custom_led.bin and b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/custom_led.bin differ diff --git a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/dev.xml b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/dev.xml old mode 100755 new mode 100644 index f5e871564350..3bdd16e80365 --- a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/dev.xml +++ b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/dev.xml @@ -7,116 +7,413 @@ --> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/dev_exhaust.xml b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/dev_exhaust.xml new file mode 100644 index 000000000000..c6c4852077c5 --- /dev/null +++ b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/dev_exhaust.xml @@ -0,0 +1,419 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/fru.py b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/fru.py new file mode 100644 index 000000000000..f95164e03601 --- /dev/null +++ b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/fru.py @@ -0,0 +1,961 @@ +#!/usr/bin/python3 +import collections +from datetime import datetime, timedelta +from bitarray import bitarray + + +__DEBUG__ = "N" + + +class FruException(Exception): + def __init__(self, message='fruerror', code=-100): + err = 'errcode: {0} message:{1}'.format(code, message) + Exception.__init__(self, err) + self.code = code + self.message = message + + +def e_print(err): + print("ERROR: " + err) + + +def d_print(debug_info): + if __DEBUG__ == "Y": + print(debug_info) + + +class FruUtil(): + @staticmethod + def decodeLength(value): + a = bitarray(8) + a.setall(True) + a[0:1] = 0 + a[1:2] = 0 + x = ord(a.tobytes()) + return x & ord(value) + + @staticmethod + def minToData(): + starttime = datetime(1996, 1, 1, 0, 0, 0) + endtime = datetime.now() + seconds = (endtime - starttime).total_seconds() + mins = seconds // 60 + m = int(round(mins)) + return m + + @staticmethod + def getTimeFormat(): + return datetime.now().strftime('%Y-%m-%d') + + @staticmethod + def getTypeLength(value): + if value is None or len(value) == 0: + return 0 + a = bitarray(8) + a.setall(False) + a[0:1] = 1 + a[1:2] = 1 + x = ord(a.tobytes()) + return x | len(value) + + @staticmethod + def checksum(b): + result = 0 + for item in b: + result += ord(item) + return (0x100 - (result & 0xff)) & 0xff + + +class BaseArea(object): + SUGGESTED_SIZE_COMMON_HEADER = 8 + SUGGESTED_SIZE_INTERNAL_USE_AREA = 72 + SUGGESTED_SIZE_CHASSIS_INFO_AREA = 32 + SUGGESTED_SIZE_BOARD_INFO_AREA = 80 + SUGGESTED_SIZE_PRODUCT_INFO_AREA = 80 + + INITVALUE = b'\x00' + resultvalue = INITVALUE * 256 + COMMON_HEAD_VERSION = b'\x01' + __childList = None + + def __init__(self, name="", size=0, offset=0): + self.__childList = [] + self._offset = offset + self.name = name + self._size = size + self._isPresent = False + self._data = b'\x00' * size + + @property + def childList(self): + return self.__childList + + @childList.setter + def childList(self, value): + self.__childList = value + + @property + def offset(self): + return self._offset + + @offset.setter + def offset(self, value): + self._offset = value + + @property + def size(self): + return self._size + + @size.setter + def size(self, value): + self._size = value + + @property + def data(self): + return self._data + + @data.setter + def data(self, value): + self._data = value + + @property + def isPresent(self): + return self._isPresent + + @isPresent.setter + def isPresent(self, value): + self._isPresent = value + + +class InternalUseArea(BaseArea): + pass + + +class ChassisInfoArea(BaseArea): + pass + + +class BoardInfoArea(BaseArea): + _boardTime = None + _fields = None + _mfg_date = None + areaversion = None + _boardversion = None + _language = None + + def __str__(self): + formatstr = "version : %x\n" \ + "length : %d \n" \ + "language : %x \n" \ + "mfg_date : %s \n" \ + "boardManufacturer : %s \n" \ + "boardProductName : %s \n" \ + "boardSerialNumber : %s \n" \ + "boardPartNumber : %s \n" \ + "fruFileId : %s \n" + + tmpstr = formatstr % (ord(self.boardversion), self.size, + self.language, self.getMfgRealData(), + self.boardManufacturer, self.boardProductName, + self.boardSerialNumber, self.boardPartNumber, + self.fruFileId) + for i in range(1, 11): + valtmp = "boardextra%d" % i + if hasattr(self, valtmp): + valtmpval = getattr(self, valtmp) + tmpstr += "boardextra%d : %s \n" % (i, valtmpval) + else: + break + + return tmpstr + + def todict(self): + dic = collections.OrderedDict() + dic["boardversion"] = ord(self.boardversion) + dic["boardlength"] = self.size + dic["boardlanguage"] = self.language + dic["boardmfg_date"] = self.getMfgRealData() + dic["boardManufacturer"] = self.boardManufacturer + dic["boardProductName"] = self.boardProductName + dic["boardSerialNumber"] = self.boardSerialNumber + dic["boardPartNumber"] = self.boardPartNumber + dic["boardfruFileId"] = self.fruFileId + for i in range(1, 11): + valtmp = "boardextra%d" % i + if hasattr(self, valtmp): + valtmpval = getattr(self, valtmp) + dic[valtmp] = valtmpval + else: + break + return dic + + def decodedata(self): + index = 0 + self.areaversion = self.data[index] + index += 1 + d_print("decode length :%d class size:%d" % + ((ord(self.data[index]) * 8), self.size)) + index += 2 + + timetmp = self.data[index: index + 3] + self.mfg_date = ord(timetmp[0]) | ( + ord(timetmp[1]) << 8) | (ord(timetmp[2]) << 16) + d_print("decode getMfgRealData :%s" % self.getMfgRealData()) + index += 3 + + templen = FruUtil.decodeLength(self.data[index]) + self.boardManufacturer = self.data[index + 1: index + templen + 1] + index += templen + 1 + d_print("decode boardManufacturer:%s" % self.boardManufacturer) + + templen = FruUtil.decodeLength(self.data[index]) + self.boardProductName = self.data[index + 1: index + templen + 1] + index += templen + 1 + d_print("decode boardProductName:%s" % self.boardProductName) + + templen = FruUtil.decodeLength(self.data[index]) + self.boardSerialNumber = self.data[index + 1: index + templen + 1] + index += templen + 1 + d_print("decode boardSerialNumber:%s" % self.boardSerialNumber) + + templen = FruUtil.decodeLength(self.data[index]) + self.boardPartNumber = self.data[index + 1: index + templen + 1] + index += templen + 1 + d_print("decode boardPartNumber:%s" % self.boardPartNumber) + + templen = FruUtil.decodeLength(self.data[index]) + self.fruFileId = self.data[index + 1: index + templen + 1] + index += templen + 1 + d_print("decode fruFileId:%s" % self.fruFileId) + + for i in range(1, 11): + valtmp = "boardextra%d" % i + if self.data[index] != chr(0xc1): + templen = FruUtil.decodeLength(self.data[index]) + tmpval = self.data[index + 1: index + templen + 1] + setattr(self, valtmp, tmpval) + index += templen + 1 + d_print("decode boardextra%d:%s" % (i, tmpval)) + else: + break + + def fruSetValue(self, field, value): + tmp_field = getattr(self, field, None) + if tmp_field is not None: + setattr(self, field, value) + + def recalcute(self): + d_print("boardInfoArea version:%x" % ord(self.boardversion)) + d_print("boardInfoArea length:%d" % self.size) + d_print("boardInfoArea language:%x" % self.language) + self.mfg_date = FruUtil.minToData() + d_print("boardInfoArea mfg_date:%x" % self.mfg_date) + + self.data = chr(ord(self.boardversion)) + \ + chr(self.size // 8) + chr(self.language) + + self.data += chr(self.mfg_date & 0xFF) + self.data += chr((self.mfg_date >> 8) & 0xFF) + self.data += chr((self.mfg_date >> 16) & 0xFF) + + d_print("boardInfoArea boardManufacturer:%s" % self.boardManufacturer) + typelength = FruUtil.getTypeLength(self.boardManufacturer) + self.data += chr(typelength) + self.data += self.boardManufacturer + + d_print("boardInfoArea boardProductName:%s" % self.boardProductName) + self.data += chr(FruUtil.getTypeLength(self.boardProductName)) + self.data += self.boardProductName + + d_print("boardInfoArea boardSerialNumber:%s" % self.boardSerialNumber) + self.data += chr(FruUtil.getTypeLength(self.boardSerialNumber)) + self.data += self.boardSerialNumber + + d_print("boardInfoArea boardPartNumber:%s" % self.boardPartNumber) + self.data += chr(FruUtil.getTypeLength(self.boardPartNumber)) + self.data += self.boardPartNumber + + d_print("boardInfoArea fruFileId:%s" % self.fruFileId) + self.data += chr(FruUtil.getTypeLength(self.fruFileId)) + self.data += self.fruFileId + + for i in range(1, 11): + valtmp = "boardextra%d" % i + if hasattr(self, valtmp): + valtmpval = getattr(self, valtmp) + d_print("boardInfoArea boardextra%d:%s" % (i, valtmpval)) + self.data += chr(FruUtil.getTypeLength(valtmpval)) + if valtmpval is not None: + self.data += valtmpval + else: + break + + self.data += chr(0xc1) + + if len(self.data) > (self.size - 1): + incr = (len(self.data) - self.size) // 8 + 1 + self.size += incr * 8 + + self.data = self.data[0:1] + chr(self.size // 8) + self.data[2:] + d_print("self data:%d" % len(self.data)) + d_print("self size:%d" % self.size) + d_print("adjust size:%d" % (self.size - len(self.data) - 1)) + self.data = self.data.ljust((self.size - 1), chr(self.INITVALUE[0])) + + # checksum + checksum = FruUtil.checksum(self.data) + d_print("board info checksum:%x" % checksum) + self.data += chr(checksum) + + def getMfgRealData(self): + starttime = datetime(1996, 1, 1, 0, 0, 0) + mactime = starttime + timedelta(minutes=self.mfg_date) + return mactime + + @property + def language(self): + self._language = 25 + return self._language + + @property + def mfg_date(self): + return self._mfg_date + + @mfg_date.setter + def mfg_date(self, val): + self._mfg_date = val + + @property + def boardversion(self): + self._boardversion = self.COMMON_HEAD_VERSION + return self._boardversion + + @property + def fruFileId(self): + return self._FRUFileID + + @fruFileId.setter + def fruFileId(self, val): + self._FRUFileID = val + + @property + def boardPartNumber(self): + return self._boardPartNumber + + @boardPartNumber.setter + def boardPartNumber(self, val): + self._boardPartNumber = val + + @property + def boardSerialNumber(self): + return self._boardSerialNumber + + @boardSerialNumber.setter + def boardSerialNumber(self, val): + self._boardSerialNumber = val + + @property + def boardProductName(self): + return self._boradProductName + + @boardProductName.setter + def boardProductName(self, val): + self._boradProductName = val + + @property + def boardManufacturer(self): + return self._boardManufacturer + + @boardManufacturer.setter + def boardManufacturer(self, val): + self._boardManufacturer = val + + @property + def boardTime(self): + return self._boardTime + + @boardTime.setter + def boardTime(self, val): + self._boardTime = val + + @property + def fields(self): + return self._fields + + @fields.setter + def fields(self, val): + self._fields = val + + +class ProductInfoArea(BaseArea): + _productManufacturer = None + _productAssetTag = None + _FRUFileID = None + _language = None + + def __str__(self): + formatstr = "version : %x\n" \ + "length : %d \n" \ + "language : %x \n" \ + "productManufacturer : %s \n" \ + "productName : %s \n" \ + "productPartModelName: %s \n" \ + "productVersion : %s \n" \ + "productSerialNumber : %s \n" \ + "productAssetTag : %s \n" \ + "fruFileId : %s \n" + + tmpstr = formatstr % (ord(self.areaversion), self.size, + self.language, self.productManufacturer, + self.productName, self.productPartModelName, + self.productVersion, self.productSerialNumber, + self.productAssetTag, self.fruFileId) + + for i in range(1, 11): + valtmp = "productextra%d" % i + if hasattr(self, valtmp): + valtmpval = getattr(self, valtmp) + tmpstr += "productextra%d : %s \n" % (i, valtmpval) + else: + break + + return tmpstr + + def todict(self): + dic = collections.OrderedDict() + dic["productversion"] = ord(self.areaversion) + dic["productlength"] = self.size + dic["productlanguage"] = self.language + dic["productManufacturer"] = self.productManufacturer + dic["productName"] = self.productName + dic["productPartModelName"] = self.productPartModelName + dic["productVersion"] = int(self.productVersion, 16) + dic["productSerialNumber"] = self.productSerialNumber + dic["productAssetTag"] = self.productAssetTag + dic["productfruFileId"] = self.fruFileId + for i in range(1, 11): + valtmp = "productextra%d" % i + if hasattr(self, valtmp): + valtmpval = getattr(self, valtmp) + dic[valtmp] = valtmpval + else: + break + return dic + + def decodedata(self): + index = 0 + self.areaversion = self.data[index] # 0 + index += 1 + d_print("decode length %d" % (ord(self.data[index]) * 8)) + d_print("class size %d" % self.size) + index += 2 + + templen = FruUtil.decodeLength(self.data[index]) + self.productManufacturer = self.data[index + 1: index + templen + 1] + index += templen + 1 + d_print("decode productManufacturer:%s" % self.productManufacturer) + + templen = FruUtil.decodeLength(self.data[index]) + self.productName = self.data[index + 1: index + templen + 1] + index += templen + 1 + d_print("decode productName:%s" % self.productName) + + templen = FruUtil.decodeLength(self.data[index]) + self.productPartModelName = self.data[index + 1: index + templen + 1] + index += templen + 1 + d_print("decode productPartModelName:%s" % self.productPartModelName) + + templen = FruUtil.decodeLength(self.data[index]) + self.productVersion = self.data[index + 1: index + templen + 1] + index += templen + 1 + d_print("decode productVersion:%s" % self.productVersion) + + templen = FruUtil.decodeLength(self.data[index]) + self.productSerialNumber = self.data[index + 1: index + templen + 1] + index += templen + 1 + d_print("decode productSerialNumber:%s" % self.productSerialNumber) + + templen = FruUtil.decodeLength(self.data[index]) + self.productAssetTag = self.data[index + 1: index + templen + 1] + index += templen + 1 + d_print("decode productAssetTag:%s" % self.productAssetTag) + + templen = FruUtil.decodeLength(self.data[index]) + self.fruFileId = self.data[index + 1: index + templen + 1] + index += templen + 1 + d_print("decode fruFileId:%s" % self.fruFileId) + + for i in range(1, 11): + valtmp = "productextra%d" % i + if self.data[index] != chr(0xc1) and index < self.size - 1: + templen = FruUtil.decodeLength(self.data[index]) + if templen == 0: + break + tmpval = self.data[index + 1: index + templen + 1] + d_print("decode boardextra%d:%s" % (i, tmpval)) + setattr(self, valtmp, tmpval) + index += templen + 1 + else: + break + + @property + def productVersion(self): + return self._productVersion + + @productVersion.setter + def productVersion(self, name): + self._productVersion = name + + @property + def areaversion(self): + self._areaversion = self.COMMON_HEAD_VERSION + return self._areaversion + + @areaversion.setter + def areaversion(self, name): + self._areaversion = name + + @property + def language(self): + self._language = 25 + return self._language + + @property + def productManufacturer(self): + return self._productManufacturer + + @productManufacturer.setter + def productManufacturer(self, name): + self._productManufacturer = name + + @property + def productName(self): + return self._productName + + @productName.setter + def productName(self, name): + self._productName = name + + @property + def productPartModelName(self): + return self._productPartModelName + + @productPartModelName.setter + def productPartModelName(self, name): + self._productPartModelName = name + + @property + def productSerialNumber(self): + return self._productSerialNumber + + @productSerialNumber.setter + def productSerialNumber(self, name): + self._productSerialNumber = name + + @property + def productAssetTag(self): + return self._productAssetTag + + @productAssetTag.setter + def productAssetTag(self, name): + self._productAssetTag = name + + @property + def fruFileId(self): + return self._FRUFileID + + @fruFileId.setter + def fruFileId(self, name): + self._FRUFileID = name + + def fruSetValue(self, field, value): + tmp_field = getattr(self, field, None) + if tmp_field is not None: + setattr(self, field, value) + + def recalcute(self): + d_print("product version:%x" % ord(self.areaversion)) + d_print("product length:%d" % self.size) + d_print("product language:%x" % self.language) + self.data = chr(ord(self.areaversion)) + \ + chr(self.size // 8) + chr(self.language) + + typelength = FruUtil.getTypeLength(self.productManufacturer) + self.data += chr(typelength) + self.data += self.productManufacturer + + self.data += chr(FruUtil.getTypeLength(self.productName)) + self.data += self.productName + + self.data += chr(FruUtil.getTypeLength(self.productPartModelName)) + self.data += self.productPartModelName + + self.data += chr(FruUtil.getTypeLength(self.productVersion)) + self.data += self.productVersion + + self.data += chr(FruUtil.getTypeLength(self.productSerialNumber)) + self.data += self.productSerialNumber + + self.data += chr(FruUtil.getTypeLength(self.productAssetTag)) + if self.productAssetTag is not None: + self.data += self.productAssetTag + + self.data += chr(FruUtil.getTypeLength(self.fruFileId)) + self.data += self.fruFileId + + for i in range(1, 11): + valtmp = "productextra%d" % i + if hasattr(self, valtmp): + valtmpval = getattr(self, valtmp) + d_print("boardInfoArea productextra%d:%s" % (i, valtmpval)) + self.data += chr(FruUtil.getTypeLength(valtmpval)) + if valtmpval is not None: + self.data += valtmpval + else: + break + + self.data += chr(0xc1) + if len(self.data) > (self.size - 1): + incr = (len(self.data) - self.size) // 8 + 1 + self.size += incr * 8 + d_print("self.data:%d" % len(self.data)) + d_print("self.size:%d" % self.size) + + self.data = self.data[0:1] + chr(self.size // 8) + self.data[2:] + self.data = self.data.ljust((self.size - 1), chr(self.INITVALUE[0])) + checksum = FruUtil.checksum(self.data) + d_print("board info checksum:%x" % checksum) + self.data += chr(checksum) + + +class MultiRecordArea(BaseArea): + pass + + +class Field(object): + + def __init__(self, fieldType="ASCII", fieldData=""): + self.fieldData = fieldData + self.fieldType = fieldType + + @property + def fieldType(self): + return self.fieldType + + @property + def fieldData(self): + return self.fieldData + + +class ipmifru(BaseArea): + _BoardInfoArea = None + _ProductInfoArea = None + _InternalUseArea = None + _ChassisInfoArea = None + _multiRecordArea = None + _productinfoAreaOffset = BaseArea.INITVALUE + _boardInfoAreaOffset = BaseArea.INITVALUE + _internalUserAreaOffset = BaseArea.INITVALUE + _chassicInfoAreaOffset = BaseArea.INITVALUE + _multiRecordAreaOffset = BaseArea.INITVALUE + _bindata = None + _bodybin = None + _version = BaseArea.COMMON_HEAD_VERSION + _zeroCheckSum = None + _frusize = 256 + + def __str__(self): + tmpstr = "" + if self.boardInfoArea.isPresent: + tmpstr += "\nboardinfoarea: \n" + tmpstr += self.boardInfoArea.__str__() + if self.productInfoArea.isPresent: + tmpstr += "\nproductinfoarea: \n" + tmpstr += self.productInfoArea.__str__() + return tmpstr + + def decodeBin(self, eeprom): + commonHead = eeprom[0:8] + d_print("decode version %x" % ord(commonHead[0])) + if ord(self.COMMON_HEAD_VERSION) != ord(commonHead[0]): + raise FruException("HEAD VERSION error,not Fru format!", -10) + if FruUtil.checksum(commonHead[0:7]) != ord(commonHead[7]): + strtemp = "check header checksum error [cal:%02x data:%02x]" % ( + FruUtil.checksum(commonHead[0:7]), ord(commonHead[7])) + raise FruException(strtemp, -3) + if ord(commonHead[1]) != ord(self.INITVALUE): + d_print("Internal Use Area is present") + self.internalUseArea = InternalUseArea( + name="Internal Use Area", size=self.SUGGESTED_SIZE_INTERNAL_USE_AREA) + self.internalUseArea.isPresent = True + self.internalUserAreaOffset = ord(commonHead[1]) + self.internalUseArea.data = eeprom[self.internalUserAreaOffset * 8: ( + self.internalUserAreaOffset * 8 + self.internalUseArea.size)] + if ord(commonHead[2]) != ord(self.INITVALUE): + d_print("Chassis Info Area is present") + self.chassisInfoArea = ChassisInfoArea( + name="Chassis Info Area", size=self.SUGGESTED_SIZE_CHASSIS_INFO_AREA) + self.chassisInfoArea.isPresent = True + self.chassicInfoAreaOffset = ord(commonHead[2]) + self.chassisInfoArea.data = eeprom[self.chassicInfoAreaOffset * 8: ( + self.chassicInfoAreaOffset * 8 + self.chassisInfoArea.size)] + if ord(commonHead[3]) != ord(self.INITVALUE): + self.boardInfoArea = BoardInfoArea( + name="Board Info Area", size=self.SUGGESTED_SIZE_BOARD_INFO_AREA) + self.boardInfoArea.isPresent = True + self.boardInfoAreaOffset = ord(commonHead[3]) + self.boardInfoArea.size = ord( + eeprom[self.boardInfoAreaOffset * 8 + 1]) * 8 + d_print("Board Info Area is present size:%d" % + (self.boardInfoArea.size)) + self.boardInfoArea.data = eeprom[self.boardInfoAreaOffset * 8: ( + self.boardInfoAreaOffset * 8 + self.boardInfoArea.size)] + if FruUtil.checksum(self.boardInfoArea.data[:-1]) != ord(self.boardInfoArea.data[-1:]): + strtmp = "check boardInfoArea checksum error[cal:%02x data:%02x]" % \ + (FruUtil.checksum( + self.boardInfoArea.data[:-1]), ord(self.boardInfoArea.data[-1:])) + raise FruException(strtmp, -3) + self.boardInfoArea.decodedata() + if ord(commonHead[4]) != ord(self.INITVALUE): + d_print("Product Info Area is present") + self.productInfoArea = ProductInfoArea( + name="Product Info Area ", size=self.SUGGESTED_SIZE_PRODUCT_INFO_AREA) + self.productInfoArea.isPresent = True + self.productinfoAreaOffset = ord(commonHead[4]) + d_print("length offset value: %02x" % + ord(eeprom[self.productinfoAreaOffset * 8 + 1])) + self.productInfoArea.size = ord( + eeprom[self.productinfoAreaOffset * 8 + 1]) * 8 + d_print("Product Info Area is present size:%d" % + (self.productInfoArea.size)) + + self.productInfoArea.data = eeprom[self.productinfoAreaOffset * 8: ( + self.productinfoAreaOffset * 8 + self.productInfoArea.size)] + if FruUtil.checksum(self.productInfoArea.data[:-1]) != ord(self.productInfoArea.data[-1:]): + strtmp = "check productInfoArea checksum error [cal:%02x data:%02x]" % ( + FruUtil.checksum(self.productInfoArea.data[:-1]), ord(self.productInfoArea.data[-1:])) + raise FruException(strtmp, -3) + self.productInfoArea.decodedata() + if ord(commonHead[5]) != ord(self.INITVALUE): + self.multiRecordArea = MultiRecordArea( + name="MultiRecord record Area ") + d_print("MultiRecord record present") + self.multiRecordArea.isPresent = True + self.multiRecordAreaOffset = ord(commonHead[5]) + self.multiRecordArea.data = eeprom[self.multiRecordAreaOffset * 8: ( + self.multiRecordAreaOffset * 8 + self.multiRecordArea.size)] + + def initDefault(self): + self.version = self.COMMON_HEAD_VERSION + self.internalUserAreaOffset = self.INITVALUE + self.chassicInfoAreaOffset = self.INITVALUE + self.boardInfoAreaOffset = self.INITVALUE + self.productinfoAreaOffset = self.INITVALUE + self.multiRecordAreaOffset = self.INITVALUE + self.zeroCheckSum = self.INITVALUE + self.offset = self.SUGGESTED_SIZE_COMMON_HEADER + self.productInfoArea = None + self.internalUseArea = None + self.boardInfoArea = None + self.chassisInfoArea = None + self.multiRecordArea = None + # self.recalcute() + + @property + def version(self): + return self._version + + @version.setter + def version(self, name): + self._version = name + + @property + def internalUserAreaOffset(self): + return self._internalUserAreaOffset + + @internalUserAreaOffset.setter + def internalUserAreaOffset(self, obj): + self._internalUserAreaOffset = obj + + @property + def chassicInfoAreaOffset(self): + return self._chassicInfoAreaOffset + + @chassicInfoAreaOffset.setter + def chassicInfoAreaOffset(self, obj): + self._chassicInfoAreaOffset = obj + + @property + def productinfoAreaOffset(self): + return self._productinfoAreaOffset + + @productinfoAreaOffset.setter + def productinfoAreaOffset(self, obj): + self._productinfoAreaOffset = obj + + @property + def boardInfoAreaOffset(self): + return self._boardInfoAreaOffset + + @boardInfoAreaOffset.setter + def boardInfoAreaOffset(self, obj): + self._boardInfoAreaOffset = obj + + @property + def multiRecordAreaOffset(self): + return self._multiRecordAreaOffset + + @multiRecordAreaOffset.setter + def multiRecordAreaOffset(self, obj): + self._multiRecordAreaOffset = obj + + @property + def zeroCheckSum(self): + return self._zeroCheckSum + + @zeroCheckSum.setter + def zeroCheckSum(self, obj): + self._zeroCheckSum = obj + + @property + def productInfoArea(self): + return self._ProductInfoArea + + @productInfoArea.setter + def productInfoArea(self, obj): + self._ProductInfoArea = obj + + @property + def internalUseArea(self): + return self._InternalUseArea + + @internalUseArea.setter + def internalUseArea(self, obj): + self.internalUseArea = obj + + @property + def boardInfoArea(self): + return self._BoardInfoArea + + @boardInfoArea.setter + def boardInfoArea(self, obj): + self._BoardInfoArea = obj + + @property + def chassisInfoArea(self): + return self._ChassisInfoArea + + @chassisInfoArea.setter + def chassisInfoArea(self, obj): + self._ChassisInfoArea = obj + + @property + def multiRecordArea(self): + return self._multiRecordArea + + @multiRecordArea.setter + def multiRecordArea(self, obj): + self._multiRecordArea = obj + + @property + def bindata(self): + return self._bindata + + @bindata.setter + def bindata(self, obj): + self._bindata = obj + + @property + def bodybin(self): + return self._bodybin + + @bodybin.setter + def bodybin(self, obj): + self._bodybin = obj + + def recalcuteCommonHead(self): + self.bindata = "" + self.offset = self.SUGGESTED_SIZE_COMMON_HEADER + d_print("common Header %d" % self.offset) + d_print("fru eeprom size %d" % self._frusize) + if self.internalUseArea is not None and self.internalUseArea.isPresent: + self.internalUserAreaOffset = self.offset // 8 + self.offset += self.internalUseArea.size + d_print("internalUseArea is present offset:%d" % self.offset) + + if self.chassisInfoArea is not None and self.chassisInfoArea.isPresent: + self.chassicInfoAreaOffset = self.offset // 8 + self.offset += self.chassisInfoArea.size + d_print("chassisInfoArea is present offset:%d" % self.offset) + + if self.boardInfoArea is not None and self.boardInfoArea.isPresent: + self.boardInfoAreaOffset = self.offset // 8 + self.offset += self.boardInfoArea.size + d_print("boardInfoArea is present offset:%d" % self.offset) + d_print("boardInfoArea is present size:%d" % + self.boardInfoArea.size) + + if self.productInfoArea is not None and self.productInfoArea.isPresent: + self.productinfoAreaOffset = self.offset // 8 + self.offset += self.productInfoArea.size + d_print("productInfoArea is present offset:%d" % self.offset) + + if self.multiRecordArea is not None and self.multiRecordArea.isPresent: + self.multiRecordAreaOffset = self.offset // 8 + d_print("multiRecordArea is present offset:%d" % self.offset) + + if self.internalUserAreaOffset == self.INITVALUE: + self.internalUserAreaOffset = 0 + if self.productinfoAreaOffset == self.INITVALUE: + self.productinfoAreaOffset = 0 + if self.chassicInfoAreaOffset == self.INITVALUE: + self.chassicInfoAreaOffset = 0 + if self.boardInfoAreaOffset == self.INITVALUE: + self.boardInfoAreaOffset = 0 + if self.multiRecordAreaOffset == self.INITVALUE: + self.multiRecordAreaOffset = 0 + + self.zeroCheckSum = (0x100 - ord(self.version) - self.internalUserAreaOffset - self.chassicInfoAreaOffset - self.productinfoAreaOffset + - self.boardInfoAreaOffset - self.multiRecordAreaOffset) & 0xff + d_print("zerochecksum:%x" % self.zeroCheckSum) + self.data = "" + self.data += chr(self.version[0]) + chr(self.internalUserAreaOffset) + chr(self.chassicInfoAreaOffset) + chr( + self.boardInfoAreaOffset) + chr(self.productinfoAreaOffset) + chr(self.multiRecordAreaOffset) + chr(self.INITVALUE[0]) + chr(self.zeroCheckSum) + + self.bindata = self.data + self.bodybin + totallen = len(self.bindata) + d_print("totallen %d" % totallen) + if totallen < self._frusize: + self.bindata = self.bindata.ljust(self._frusize, chr(self.INITVALUE[0])) + else: + raise FruException('bin data more than %d' % self._frusize, -2) + + def recalcutebin(self): + self.bodybin = "" + if self.internalUseArea is not None and self.internalUseArea.isPresent: + d_print("internalUseArea present") + self.bodybin += self.internalUseArea.data + if self.chassisInfoArea is not None and self.chassisInfoArea.isPresent: + d_print("chassisInfoArea present") + self.bodybin += self.chassisInfoArea.data + if self.boardInfoArea is not None and self.boardInfoArea.isPresent: + d_print("boardInfoArea present") + self.boardInfoArea.recalcute() + self.bodybin += self.boardInfoArea.data + if self.productInfoArea is not None and self.productInfoArea.isPresent: + d_print("productInfoAreapresent") + self.productInfoArea.recalcute() + self.bodybin += self.productInfoArea.data + if self.multiRecordArea is not None and self.multiRecordArea.isPresent: + d_print("multiRecordArea present") + self.bodybin += self.productInfoArea.data + + def recalcute(self, fru_eeprom_size=256): + self._frusize = fru_eeprom_size + self.recalcutebin() + self.recalcuteCommonHead() + + def setValue(self, area, field, value): + tmp_area = getattr(self, area, None) + if tmp_area is not None: + tmp_area.fruSetValue(field, value) diff --git a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/latest_firmware/bios_upgrade_header.bin b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/latest_firmware/bios_upgrade_header.bin new file mode 100644 index 000000000000..08eba59b3a77 Binary files /dev/null and b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/latest_firmware/bios_upgrade_header.bin differ diff --git a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/latest_firmware/cpu_cpld_upgrade_header.vme b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/latest_firmware/cpu_cpld_upgrade_header.vme new file mode 100644 index 000000000000..83f6b99d2a8b Binary files /dev/null and b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/latest_firmware/cpu_cpld_upgrade_header.vme differ diff --git a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/latest_firmware/fpga_upgrade_header.bin b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/latest_firmware/fpga_upgrade_header.bin new file mode 100644 index 000000000000..675ffa24dc94 Binary files /dev/null and b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/latest_firmware/fpga_upgrade_header.bin differ diff --git a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/latest_firmware/other_cpld_upgrade_header.vme b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/latest_firmware/other_cpld_upgrade_header.vme new file mode 100644 index 000000000000..7be3d61ea215 Binary files /dev/null and b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/latest_firmware/other_cpld_upgrade_header.vme differ diff --git a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/monitor.py b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/monitor.py old mode 100755 new mode 100644 index 103a2f30ac29..e300df137ef9 --- a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/monitor.py +++ b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/monitor.py @@ -1,113 +1,235 @@ #!/usr/bin/python3 -# -*- coding: UTF-8 -*- -""" -* onboard temperature sensors -* FAN trays -* PSU -""" +# * onboard temperature sensors +# * FAN trays +# * PSU +# import os +import xml.etree.ElementTree as ET import glob -from lxml import etree as ET +import json +from decimal import Decimal +from fru import ipmifru + MAILBOX_DIR = "/sys/bus/i2c/devices/" -PORTS_DIR = "/sys/class/net/" +BOARD_ID_PATH = "/sys/module/platform_common/parameters/dfd_my_type" +BOARD_AIRFLOW_PATH = "/etc/sonic/.airflow" + + CONFIG_NAME = "dev.xml" -def getPMCreg(location): +def byteTostr(val): + strtmp = '' + for value in val: + strtmp += chr(value) + return strtmp + + +def typeTostr(val): + if isinstance(val, bytes): + strtmp = byteTostr(val) + return strtmp + return val + + +def get_board_id(): + if not os.path.exists(BOARD_ID_PATH): + return "NA" + with open(BOARD_ID_PATH) as fd: + id_str = fd.read().strip() + return "0x%x" % (int(id_str, 10)) + + +def getboardairflow(): + if not os.path.exists(BOARD_AIRFLOW_PATH): + return "NA" + with open(BOARD_AIRFLOW_PATH) as fd: + airflow_str = fd.read().strip() + data = json.loads(airflow_str) + airflow = data.get("board", "NA") + return airflow + + +boardid = get_board_id() +boardairflow = getboardairflow() + + +DEV_XML_FILE_LIST = [ + "dev_" + boardid + "_" + boardairflow + ".xml", + "dev_" + boardid + ".xml", + "dev_" + boardairflow + ".xml", +] + + +def dev_file_read(path, offset, read_len): retval = "ERR" + val_list = [] + msg = "" + ret = "" + fd = -1 + + if not os.path.exists(path): + return False, "%s %s not found" % (retval, path) + + try: + fd = os.open(path, os.O_RDONLY) + os.lseek(fd, offset, os.SEEK_SET) + ret = os.read(fd, read_len) + for item in ret: + val_list.append(item) + except Exception as e: + msg = str(e) + return False, "%s %s" % (retval, msg) + finally: + if fd > 0: + os.close(fd) + return True, val_list + + +def getPMCreg(location): + retval = 'ERR' if not os.path.isfile(location): return "%s %s notfound" % (retval, location) try: - with open(location, "r") as fd: + with open(location, 'r') as fd: retval = fd.read() - except Exception: - pass - # logging.error("Unable to open ", location, "file !") + except Exception as error: + return "ERR %s" % str(error) - retval = retval.rstrip("\r\n") + retval = retval.rstrip('\r\n') retval = retval.lstrip(" ") return retval # Get a mailbox register def get_pmc_register(reg_name): - retval = "ERR" - if reg_name[0:4] == "/rif" or reg_name[0:4] == "/ma1" or reg_name[0:4] == "/eth": - mb_reg_file = PORTS_DIR + reg_name - else: - mb_reg_file = MAILBOX_DIR + reg_name + retval = 'ERR' + mb_reg_file = reg_name filepath = glob.glob(mb_reg_file) if len(filepath) == 0: return "%s %s notfound" % (retval, mb_reg_file) - mb_reg_file = filepath[0] # use first found patch + mb_reg_file = filepath[0] if not os.path.isfile(mb_reg_file): + # print mb_reg_file, 'not found !' return "%s %s notfound" % (retval, mb_reg_file) try: - with open(mb_reg_file, "r") as fd: + with open(mb_reg_file, 'rb') as fd: retval = fd.read() - except Exception: - pass - # logging.error("Unable to open ", mb_reg_file, "file !") + retval = typeTostr(retval) + except Exception as error: + retval = "%s %s read failed, msg: %s" % (retval, mb_reg_file, str(error)) - retval = retval.rstrip("\r\n") + retval = retval.rstrip('\r\n') retval = retval.lstrip(" ") return retval -class checktype: +class checktype(): def __init__(self, test1): self.test1 = test1 @staticmethod - def check(name, location, bit, value, tips, err1): - psu_status = int(get_pmc_register(location), 16) - val = (psu_status & (1 << bit)) >> bit - if val != value: - err1["errmsg"] = tips - err1["code"] = -1 - return -1 - else: - err1["errmsg"] = "none" - err1["code"] = 0 - return 0 - - @staticmethod - def getValue(location, bit, type): - value_t = get_pmc_register(location) - if value_t.startswith("ERR"): + def getValue(location, bit, data_type, coefficient=1, addend=0): + try: + value_t = get_pmc_register(location) + if value_t.startswith("ERR") or value_t.startswith("NA"): + return value_t + if data_type == 1: + return float('%.1f' % ((float(value_t) / 1000) + addend)) + if data_type == 2: + return float('%.1f' % (float(value_t) / 100)) + if data_type == 3: + psu_status = int(value_t, 16) + return (psu_status & (1 << bit)) >> bit + if data_type == 4: + return int(value_t, 10) + if data_type == 5: + return float('%.1f' % (float(value_t) / 1000 / 1000)) + if data_type == 6: + return Decimal(float(value_t) * coefficient / 1000).quantize(Decimal('0.000')) return value_t - if type == 1: - return float(value_t) / 1000 - elif type == 2: - return float(value_t) / 100 - elif type == 3: - psu_status = int(value_t, 16) - return (psu_status & (1 << bit)) >> bit - elif type == 4: - return int(value_t, 10) - else: + except Exception as e: + value_t = "ERR %s" % str(e) return value_t - # temperature + # fanFRU @staticmethod - def getTemp(self, name, location, ret_t): - ret2 = self.getValue(location + "temp1_input", " ", 1) - ret3 = self.getValue(location + "temp1_max", " ", 1) - ret4 = self.getValue(location + "temp1_max_hyst", " ", 1) - ret_t["temp1_input"] = ret2 - ret_t["temp1_max"] = ret3 - ret_t["temp1_max_hyst"] = ret4 + def decodeBinByValue(retval): + fru = ipmifru() + fru.decodeBin(retval) + return fru @staticmethod - def getLM75(name, location, result): - c1 = checktype - r1 = {} - c1.getTemp(c1, name, location, r1) - result[name] = r1 + def getfruValue(prob_t, root, val): + try: + ret, binval_bytes = dev_file_read(val, 0, 256) + if ret is False: + return binval_bytes + binval = byteTostr(binval_bytes) + fanpro = {} + ret = checktype.decodeBinByValue(binval) + fanpro['fan_type'] = ret.productInfoArea.productName + fanpro['hw_version'] = str(int(ret.productInfoArea.productVersion, 16)) + fanpro['sn'] = ret.productInfoArea.productSerialNumber + fan_display_name_dict = status.getDecodValue(root, "fan_display_name") + fan_name = fanpro['fan_type'].strip() + if len(fan_display_name_dict) == 0: + return fanpro + if fan_name not in fan_display_name_dict: + prob_t['errcode'] = -1 + prob_t['errmsg'] = '%s' % ("ERR fan name: %s not support" % fan_name) + else: + fanpro['fan_type'] = fan_display_name_dict[fan_name] + return fanpro + except Exception as error: + return "ERR " + str(error) + @staticmethod + def getslotfruValue(val): + try: + binval = checktype.getValue(val, 0, 0) + if binval.startswith("ERR"): + return binval + slotpro = {} + ret = checktype.decodeBinByValue(binval) + slotpro['slot_type'] = ret.boardInfoArea.boardProductName + slotpro['hw_version'] = ret.boardInfoArea.boardextra1 + slotpro['sn'] = ret.boardInfoArea.boardSerialNumber + return slotpro + except Exception as error: + return "ERR " + str(error) + + @staticmethod + def getpsufruValue(prob_t, root, val): + try: + psu_match = False + binval = checktype.getValue(val, 0, 0) + if binval.startswith("ERR"): + return binval + psupro = {} + ret = checktype.decodeBinByValue(binval) + psupro['type1'] = ret.productInfoArea.productPartModelName + psupro['sn'] = ret.productInfoArea.productSerialNumber + psupro['hw_version'] = ret.productInfoArea.productVersion + psu_dict = status.getDecodValue(root, "psutype") + psupro['type1'] = psupro['type1'].strip() + if len(psu_dict) == 0: + return psupro + for psu_name, display_name in psu_dict.items(): + if psu_name in psupro['type1']: + psupro['type1'] = display_name + psu_match = True + break + if psu_match is not True: + prob_t['errcode'] = -1 + prob_t['errmsg'] = '%s' % ("ERR psu name: %s not support" % psupro['type1']) + return psupro + except Exception as error: + return "ERR " + str(error) -class status: + +class status(): def __init__(self, productname): self.productname = productname @@ -119,10 +241,12 @@ def getETroot(filename): @staticmethod def getDecodValue(collection, decode): - decodes = collection.find("decode") + decodes = collection.find('decode') testdecode = decodes.find(decode) test = {} - for neighbor in testdecode.iter("code"): + if testdecode is None: + return test + for neighbor in testdecode.iter('code'): test[neighbor.attrib["key"]] = neighbor.attrib["value"] return test @@ -136,37 +260,67 @@ def getETValue(a, filename, tagname): for neighbor in root.iter(tagname): prob_t = {} prob_t = neighbor.attrib - prob_t["errcode"] = 0 - prob_t["errmsg"] = "" + prob_t['errcode'] = 0 + prob_t['errmsg'] = '' for pros in neighbor.iter("property"): - ret = dict(neighbor.attrib.items() + pros.attrib.items()) - if "type" not in ret.keys(): + ret = dict(list(neighbor.attrib.items()) + list(pros.attrib.items())) + if ret.get('e2type') == 'fru' and ret.get("name") == "fru": + fruval = checktype.getfruValue(prob_t, root, ret["location"]) + if isinstance(fruval, str) and fruval.startswith("ERR"): + prob_t['errcode'] = -1 + prob_t['errmsg'] = fruval + break + prob_t.update(fruval) + continue + + if ret.get("name") == "psu" and ret.get('e2type') == 'fru': + psuval = checktype.getpsufruValue(prob_t, root, ret["location"]) + if isinstance(psuval, str) and psuval.startswith("ERR"): + prob_t['errcode'] = -1 + prob_t['errmsg'] = psuval + break + prob_t.update(psuval) + continue + + if ret.get("gettype") == "config": + prob_t[ret["name"]] = ret["value"] + continue + + if 'type' not in ret.keys(): val = "0" else: val = ret["type"] - if "bit" not in ret.keys(): + if 'bit' not in ret.keys(): bit = "0" else: bit = ret["bit"] - s = checktype.getValue(ret["location"], int(bit), int(val)) + if 'coefficient' not in ret.keys(): + coefficient = 1 + else: + coefficient = float(ret["coefficient"]) + if 'addend' not in ret.keys(): + addend = 0 + else: + addend = float(ret["addend"]) + + s = checktype.getValue(ret["location"], int(bit), int(val), coefficient, addend) if isinstance(s, str) and s.startswith("ERR"): - prob_t["errcode"] = -1 - prob_t["errmsg"] = s - if "default" in ret.keys(): - rt = status.getDecodValue(root, ret["decode"]) - prob_t["errmsg"] = rt[str(s)] + prob_t['errcode'] = -1 + prob_t['errmsg'] = s + break + if 'default' in ret.keys(): + rt = status.getDecodValue(root, ret['decode']) + prob_t['errmsg'] = rt[str(s)] if str(s) != ret["default"]: - prob_t["errcode"] = -1 + prob_t['errcode'] = -1 break else: - if "decode" in ret.keys(): - rt = status.getDecodValue(root, ret["decode"]) - if ( - ret["decode"] == "psutype" - and s.replace("\x00", "").rstrip() not in rt.keys() - ): # PSU type detect - prob_t["errcode"] = -1 - prob_t["errmsg"] = "%s" % ("The power type does not match, please check whether the power is correct!") + if 'decode' in ret.keys(): + rt = status.getDecodValue(root, ret['decode']) + if (ret['decode'] == "psutype" and s.replace("\x00", "").rstrip() not in rt): + prob_t['errcode'] = -1 + prob_t['errmsg'] = '%s' % ("ERR psu name: %s not support" % + (s.replace("\x00", "").rstrip())) else: s = rt[str(s).replace("\x00", "").rstrip()] name = ret["name"] @@ -187,46 +341,39 @@ def getCPUValue(a, filename, tagname): for i in range(len(L)): prob_t = {} prob_t["name"] = getPMCreg("%s/temp%d_label" % (location, i + 1)) - prob_t["temp"] = ( - float(getPMCreg("%s/temp%d_input" % (location, i + 1))) / 1000 - ) - prob_t["alarm"] = ( - float(getPMCreg("%s/temp%d_crit_alarm" % (location, i + 1))) / 1000 - ) - prob_t["crit"] = ( - float(getPMCreg("%s/temp%d_crit" % (location, i + 1))) / 1000 - ) + prob_t["temp"] = float(getPMCreg("%s/temp%d_input" % (location, i + 1))) / 1000 + prob_t["alarm"] = float(getPMCreg("%s/temp%d_crit_alarm" % (location, i + 1))) / 1000 + prob_t["crit"] = float(getPMCreg("%s/temp%d_crit" % (location, i + 1))) / 1000 prob_t["max"] = float(getPMCreg("%s/temp%d_max" % (location, i + 1))) / 1000 a.append(prob_t) @staticmethod def getFileName(): - return os.path.dirname(os.path.realpath(__file__)) + "/" + CONFIG_NAME - - @staticmethod - def getFan(ret): - _filename = status.getFileName() - _tagname = "fan" - status.getvalue(ret, _filename, _tagname) + fpath = os.path.dirname(os.path.realpath(__file__)) + for file in DEV_XML_FILE_LIST: + xml = fpath + "/" + file + if os.path.exists(xml): + return xml + return fpath + "/" + CONFIG_NAME @staticmethod def checkFan(ret): _filename = status.getFileName() - # _filename = "/usr/local/bin/" + status.getFileName() + # _filename = "/usr/local/bin/" + status.getFileName() _tagname = "fan" status.getETValue(ret, _filename, _tagname) @staticmethod def getTemp(ret): _filename = status.getFileName() - # _filename = "/usr/local/bin/" + status.getFileName() + # _filename = "/usr/local/bin/" + status.getFileName() _tagname = "temp" status.getETValue(ret, _filename, _tagname) @staticmethod def getPsu(ret): _filename = status.getFileName() - # _filename = "/usr/local/bin/" + status.getFileName() + # _filename = "/usr/local/bin/" + status.getFileName() _tagname = "psu" status.getETValue(ret, _filename, _tagname) @@ -237,8 +384,19 @@ def getcputemp(ret): status.getCPUValue(ret, _filename, _tagname) @staticmethod - def getMgmtRx(ret): + def getDcdc(ret): + _filename = status.getFileName() + _tagname = "dcdc" + status.getETValue(ret, _filename, _tagname) + + @staticmethod + def getmactemp(ret): + _filename = status.getFileName() + _tagname = "mactemp" + status.getETValue(ret, _filename, _tagname) + + @staticmethod + def getmacpower(ret): _filename = status.getFileName() - # _filename = "/usr/local/bin/" + status.getFileName() - _tagname = "mgmt_rx" + _tagname = "macpower" status.getETValue(ret, _filename, _tagname) diff --git a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/pcie.yaml b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/pcie.yaml index 90ebf1740641..7b026cec395e 100644 --- a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/pcie.yaml +++ b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/pcie.yaml @@ -82,6 +82,12 @@ id: 8c10 name: 'PCI bridge: Intel Corporation 8 Series/C220 Series Chipset Family PCI Express Root Port #1 (rev d5)' +- bus: '00' + dev: 1c + fn: '1' + id: 8c12 + name: 'PCI bridge: Intel Corporation 8 Series/C220 Series Chipset Family PCI Express + Root Port #2 (rev d5)' - bus: '00' dev: 1d fn: '0' @@ -109,9 +115,8 @@ - bus: '01' dev: '00' fn: '0' - id: '1533' - name: 'Ethernet controller: Intel Corporation I210 Gigabit Network Connection (rev - 03)' + id: b873 + name: 'Ethernet controller: Broadcom Inc. and subsidiaries Device b873 (rev 01)' - bus: '03' dev: '00' fn: '0' @@ -149,8 +154,14 @@ - bus: '07' dev: '00' fn: '0' - id: b873 - name: 'Ethernet controller: Broadcom Limited Device b873 (rev 01)' + id: '1537' + name: 'Ethernet controller: Intel Corporation I210 Gigabit Backplane Connection + (rev 03)' +- bus: 08 + dev: '00' + fn: '0' + id: '7022' + name: 'Memory controller: Xilinx Corporation Device 7022' - bus: ff dev: 0b fn: '0' diff --git a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/pddf/pd-plugin.json b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/pddf/pd-plugin.json deleted file mode 100644 index ffa06ff74303..000000000000 --- a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/pddf/pd-plugin.json +++ /dev/null @@ -1,67 +0,0 @@ -{ - "XCVR": { - "xcvr_present": { - "i2c": { - "valmap-SFP28": { - "1": true, - "0": false - }, - "valmap-QSFP28": { - "1": true, - "0": false - } - } - } - }, - - "PSU": { - "psu_present": { - "i2c": { - "valmap": { - "1": true, - "0": false - } - } - }, - - "psu_power_good": { - "i2c": { - "valmap": { - "1": true, - "0": false - } - } - }, - - "psu_fan_dir": { - "i2c": { - "valmap": { - "F2B": "EXHAUST", - "B2F": "INTAKE" - } - } - }, - "PSU_FAN_MAX_SPEED": "18000" - }, - - "FAN": { - "direction": { - "i2c": { - "valmap": { - "1": "INTAKE", - "0": "EXHAUST" - } - } - }, - "present": { - "i2c": { - "valmap": { - "1": true, - "0": false - } - } - }, - "duty_cycle_to_pwm": "lambda dc: dc*255/100", - "pwm_to_duty_cycle": "lambda pwm: pwm*100/255" - } -} diff --git a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/pddf/pddf-device.json b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/pddf/pddf-device.json deleted file mode 100644 index e9fc701bb8df..000000000000 --- a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/pddf/pddf-device.json +++ /dev/null @@ -1,6502 +0,0 @@ -{ - "PLATFORM": { - "num_psus": 2, - "num_fantrays": 4, - "num_fans_pertray": 1, - "num_ports": 56, - "num_temps": 3, - "pddf_dev_types": { - "description": "RA-B6510-48v8c", - "CPLD": [ - "i2c_cpld" - ], - "PSU": [ - "psu_eeprom", - "psu_pmbus" - ], - "FAN": [ - "fan_ctrl", - "fan_cpld", - "fan_eeprom" - ], - "PORT_MODULE": [ - "pddf_xcvr", - "optoe1", - "optoe2" - ] - }, - "std_kos": [ - "i2c-ismt", - "i2c-i801", - "i2c_dev", - "i2c_gpio", - "i2c_algo_bit", - "i2c_mux_pca9641", - "i2c_mux_pca954x force_create_bus=1 close_chan_force_reset=1", - "lm75", - "optoe", - "at24", - "pmbus_core" - ], - "pddf_kos": [ - "pddf_client_module", - "pddf_cpld_module", - "pddf_cpld_driver", - "pddf_mux_module", - "pddf_xcvr_module", - "pddf_xcvr_driver_module", - "pddf_psu_driver_module", - "pddf_psu_module", - "pddf_fan_driver_module", - "pddf_fan_module", - "pddf_led_module", - "pddf_sysstatus_module" - ], - "custom_kos": [ - "ragile_platform", - "ragile_common dfd_my_type=0x404a", - "rg_cpld", - "rg_fan", - "rg_psu", - "rg_gpio_xeon", - "csu550" - ] - - }, - - "SYSTEM": { - "dev_info": { - "device_type": "CPU", - "device_name": "ROOT_COMPLEX", - "device_parent": null - }, - "i2c": { - "CONTROLLERS": [{ - "dev_name": "i2c-0", - "dev": "SMBUS0" - }, { - "dev_name": "i2c-2", - "dev": "SMBUS1" - }, { - "dev_name": "i2c-1", - "dev": "I2C-GPIO0" - }] - } - }, - - "SMBUS0": { - "dev_info": { - "device_type": "SMBUS", - "device_name": "SMBUS0", - "device_parent": "SYSTEM" - }, - "i2c": { - "topo_info": { - "dev_addr": "0x0" - }, - "DEVICES": [{ - "dev": "CPU_CPLD" - }, - { - "dev": "CONNECT_BOARD_CPLD1" - } - ] - } - }, - - "CPU_CPLD": { - "dev_info": { - "device_type": "CPLD", - "device_name": "CPU_CPLD", - "device_parent": "SMBUS0" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x0", - "dev_addr": "0x0d", - "dev_type": "i2c_cpld" - }, - "dev_attr": {} - } - }, - - "CONNECT_BOARD_CPLD1": { - "dev_info": { - "device_type": "CPLD", - "device_name": "CONNECT_BOARD_CPLD1", - "device_parent": "SMBUS0" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x0", - "dev_addr": "0x32", - "dev_type": "i2c_cpld" - }, - "dev_attr": {} - } - }, - - "SMBUS1": { - "dev_info": { - "device_type": "SMBUS", - "device_name": "SMBUS1", - "device_parent": "SYSTEM" - }, - "i2c": { - "topo_info": { - "dev_addr": "0x2" - }, - "DEVICES": [{ - "dev": "MAC_BOARD_CPLD1_A" - }, - { - "dev": "MAC_BOARD_CPLD2_A" - }, - { - "dev": "CONNECT_BOARD_CPLD2" - }, - { - "dev": "FAN-CTRL" - }, - { - "dev": "TEMP1" - }, - { - "dev": "TEMP2" - }, - { - "dev": "TEMP3" - }, - { - "dev": "EEPROM1" - }, - { - "dev": "MUX1" - } - ] - } - }, - - "MAC_BOARD_CPLD1_A": { - "dev_info": { - "device_type": "CPLD", - "device_name": "MAC_BOARD_CPLD1_A", - "device_parent": "SMBUS1" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x2", - "dev_addr": "0x33", - "dev_type": "i2c_cpld" - }, - "dev_attr": {} - } - }, - - "MAC_BOARD_CPLD2_A": { - "dev_info": { - "device_type": "CPLD", - "device_name": "MAC_BOARD_CPLD2_A", - "device_parent": "SMBUS1" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x2", - "dev_addr": "0x35", - "dev_type": "i2c_cpld" - }, - "dev_attr": {} - } - }, - - "FAN-CTRL": { - "dev_info": { - "device_type": "FAN", - "device_name": "FAN-CTRL", - "device_parent": "SMBUS1" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x2", - "dev_addr": "0x66", - "dev_type": "fan_cpld" - }, - "dev_attr": { - "num_fantrays": "4" - }, - "attr_list": [{ - "attr_name": "fan1_present", - "attr_devtype": "cpld", - "attr_devaddr": "0x37", - "attr_offset": "0x30", - "attr_mask": "0x1", - "attr_cmpval": "0x0", - "attr_len": "1" - }, - { - "attr_name": "fan2_present", - "attr_devtype": "cpld", - "attr_devaddr": "0x37", - "attr_offset": "0x30", - "attr_mask": "0x2", - "attr_cmpval": "0x0", - "attr_len": "1" - }, - { - "attr_name": "fan3_present", - "attr_devtype": "cpld", - "attr_devaddr": "0x37", - "attr_offset": "0x30", - "attr_mask": "0x4", - "attr_cmpval": "0x0", - "attr_len": "1" - }, - { - "attr_name": "fan4_present", - "attr_devtype": "cpld", - "attr_devaddr": "0x37", - "attr_offset": "0x30", - "attr_mask": "0x8", - "attr_cmpval": "0x0", - "attr_len": "1" - }, - { - "attr_name": "fan1_input", - "attr_devname": "CONNECT_BOARD_CPLD2", - "attr_devtype": "cpld", - "attr_devaddr": "0x37", - "attr_offset": "0x1b", - "attr_mult": "1", - "attr_len": "2" - }, - { - "attr_name": "fan2_input", - "attr_devname": "CONNECT_BOARD_CPLD2", - "attr_devtype": "cpld", - "attr_devaddr": "0x37", - "attr_offset": "0x1d", - "attr_mult": "1", - "attr_len": "2" - }, - { - "attr_name": "fan3_input", - "attr_devname": "CONNECT_BOARD_CPLD2", - "attr_devtype": "cpld", - "attr_devaddr": "0x37", - "attr_offset": "0x1f", - "attr_mult": "1", - "attr_len": "2" - }, - { - "attr_name": "fan4_input", - "attr_devname": "CONNECT_BOARD_CPLD2", - "attr_devtype": "cpld", - "attr_devaddr": "0x37", - "attr_offset": "0x21", - "attr_mult": "1", - "attr_len": "2" - }, - { - "attr_name": "fan1_pwm", - "attr_devtype": "cpld", - "attr_devaddr": "0x32", - "attr_offset": "0x15", - "attr_mask": "0xff", - "attr_len": "1" - }, - { - "attr_name": "fan2_pwm", - "attr_devtype": "cpld", - "attr_devaddr": "0x32", - "attr_offset": "0x15", - "attr_mask": "0xff", - "attr_len": "1" - }, - { - "attr_name": "fan3_pwm", - "attr_devtype": "cpld", - "attr_devaddr": "0x32", - "attr_offset": "0x15", - "attr_mask": "0xff", - "attr_len": "1" - }, - { - "attr_name": "fan4_pwm", - "attr_devtype": "cpld", - "attr_devaddr": "0x32", - "attr_offset": "0x15", - "attr_mask": "0xff", - "attr_len": "1" - } - ] - } - }, - - "CONNECT_BOARD_CPLD2": { - "dev_info": { - "device_type": "CPLD", - "device_name": "CONNECT_BOARD_CPLD2", - "device_parent": "SMBUS1" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x2", - "dev_addr": "0x37", - "dev_type": "i2c_cpld" - }, - "dev_attr": {} - } - }, - - "TEMP1": { - "dev_info": { - "device_type": "TEMP_SENSOR", - "device_name": "MAC_TEMP_INLET", - "device_parent": "SMBUS1" - }, - "dev_attr": { - "display_name": "Temp_1" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x2", - "dev_addr": "0x48", - "dev_type": "lm75" - }, - "attr_list": [{ - "attr_name": "temp1_high_threshold", - "drv_attr_name": "temp1_max" - }, - { - "attr_name": "temp1_max_hyst" - }, - { - "attr_name": "temp1_input" - } - ] - } - }, - - "TEMP2": { - "dev_info": { - "device_type": "TEMP_SENSOR", - "device_name": "MAC_TEMP_OUTLET", - "device_parent": "SMBUS1" - }, - "dev_attr": { - "display_name": "Temp_2" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x2", - "dev_addr": "0x49", - "dev_type": "lm75" - }, - "attr_list": [{ - "attr_name": "temp1_high_threshold", - "drv_attr_name": "temp1_max" - }, - { - "attr_name": "temp1_max_hyst" - }, - { - "attr_name": "temp1_input" - } - ] - } - }, - - "TEMP3": { - "dev_info": { - "device_type": "TEMP_SENSOR", - "device_name": "MAC_TEMP_HOTEST", - "device_parent": "SMBUS1" - }, - "dev_attr": { - "display_name": "Temp_3" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x2", - "dev_addr": "0x4a", - "dev_type": "lm75" - }, - "attr_list": [{ - "attr_name": "temp1_high_threshold", - "drv_attr_name": "temp1_max" - }, - { - "attr_name": "temp1_max_hyst" - }, - { - "attr_name": "temp1_input" - } - ] - } - }, - - "EEPROM1": { - "dev_info": { - "device_type": "EEPROM", - "device_name": "EEPROM1", - "device_parent": "SMBUS1" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x2", - "dev_addr": "0x57", - "dev_type": "24c02" - }, - "dev_attr": { - "access_mode": "BLOCK" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "MUX1": { - "dev_info": { - "device_type": "MUX", - "device_name": "MUX1", - "device_parent": "SMBUS1" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x2", - "dev_addr": "0x70", - "dev_type": "pca9548" - }, - "dev_attr": { - "virt_bus": "0x3" - }, - "channel": [{ - "chn": "0", - "dev": "FAN1-EEPROM" - }, - { - "chn": "1", - "dev": "FAN2-EEPROM" - }, - { - "chn": "2", - "dev": "FAN3-EEPROM" - }, - { - "chn": "3", - "dev": "FAN4-EEPROM" - }, - { - "chn": "4", - "dev": "PSU1" - }, - { - "chn": "5", - "dev": "PSU2" - } - ] - } - }, - - "FAN1-EEPROM": { - "dev_info": { - "device_type": "EEPROM", - "device_name": "FAN1-EEPROM", - "device_parent": "MUX1" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x3", - "dev_addr": "0x53", - "dev_type": "rg_fan" - }, - "dev_attr": { - "access_mode": "BLOCK" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "FAN2-EEPROM": { - "dev_info": { - "device_type": "EEPROM", - "device_name": "FAN2-EEPROM", - "device_parent": "MUX1" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x4", - "dev_addr": "0x53", - "dev_type": "rg_fan" - }, - "dev_attr": { - "access_mode": "BLOCK" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "FAN3-EEPROM": { - "dev_info": { - "device_type": "EEPROM", - "device_name": "FAN3-EEPROM", - "device_parent": "MUX1" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x5", - "dev_addr": "0x53", - "dev_type": "rg_fan" - }, - "dev_attr": { - "access_mode": "BLOCK" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "FAN4-EEPROM": { - "dev_info": { - "device_type": "EEPROM", - "device_name": "FAN4-EEPROM", - "device_parent": "MUX1" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x6", - "dev_addr": "0x53", - "dev_type": "rg_fan" - }, - "dev_attr": { - "access_mode": "BLOCK" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PSU1": { - "dev_info": { - "device_type": "PSU", - "device_name": "PSU1", - "device_parent": "MUX1" - }, - "dev_attr": { - "dev_idx": "1", - "num_psu_fans": "1" - }, - "i2c": { - "interface": [{ - "itf": "pmbus", - "dev": "PSU1-PMBUS" - }, - { - "itf": "eeprom", - "dev": "PSU1-EEPROM" - } - ] - } - }, - - "PSU1-PMBUS": { - "dev_info": { - "device_type": "PSU-PMBUS", - "device_name": "PSU1-PMBUS", - "device_parent": "MUX1", - "virt_parent": "PSU1" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x7", - "dev_addr": "0x58", - "dev_type": "psu_pmbus" - }, - "attr_list": [{ - "attr_name": "psu_present", - "attr_devaddr": "0x37", - "attr_devtype": "cpld", - "attr_offset": "0x51", - "attr_mask": "0x1", - "attr_cmpval": "0x0", - "attr_len": "1" - }, - { - "attr_name": "psu_model_name", - "attr_devaddr": "0x58", - "attr_devtype": "pmbus", - "attr_offset": "0x9a", - "attr_mask": "0x0", - "attr_cmpval": "0xff", - "attr_len": "12" - }, - { - "attr_name": "psu_power_good", - "attr_devaddr": "0x37", - "attr_devtype": "cpld", - "attr_offset": "0x51", - "attr_mask": "0x2", - "attr_cmpval": "0x2", - "attr_len": "1" - }, - { - "attr_name": "psu_mfr_id", - "attr_devaddr": "0x58", - "attr_devtype": "pmbus", - "attr_offset": "0x99", - "attr_mask": "0x0", - "attr_cmpval": "0xff", - "attr_len": "10" - }, - { - "attr_name": "psu_fan_dir", - "attr_devaddr": "0x58", - "attr_devtype": "pmbus", - "attr_offset": "0xc3", - "attr_mask": "0x0", - "attr_cmpval": "0xff", - "attr_len": "5" - }, - { - "attr_name": "psu_v_out", - "attr_devaddr": "0x58", - "attr_devtype": "pmbus", - "attr_offset": "0x8b", - "attr_mask": "0x0", - "attr_cmpval": "0xff", - "attr_len": "2" - }, - { - "attr_name": "psu_i_out", - "attr_devaddr": "0x58", - "attr_devtype": "pmbus", - "attr_offset": "0x8c", - "attr_mask": "0x0", - "attr_cmpval": "0xff", - "attr_len": "2" - }, - { - "attr_name": "psu_p_out", - "attr_devaddr": "0x58", - "attr_devtype": "pmbus", - "attr_offset": "0x96", - "attr_mask": "0x0", - "attr_cmpval": "0xff", - "attr_len": "2" - }, - { - "attr_name": "psu_fan1_speed_rpm", - "attr_devaddr": "0x58", - "attr_devtype": "pmbus", - "attr_offset": "0x90", - "attr_mask": "0x0", - "attr_cmpval": "0xff", - "attr_len": "2" - }, - { - "attr_name": "psu_temp1_input", - "attr_devaddr": "0x58", - "attr_devtype": "pmbus", - "attr_offset": "0x8d", - "attr_mask": "0x0", - "attr_cmpval": "0xff", - "attr_len": "2" - } - ] - } - }, - - "PSU1-EEPROM": { - "dev_info": { - "device_type": "PSU-EEPROM", - "device_name": "PSU1-EEPROM", - "device_parent": "MUX1", - "virt_parent": "PSU1" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x7", - "dev_addr": "0x50", - "dev_type": "psu_eeprom" - }, - "attr_list": [{ - "attr_name": "psu_serial_num", - "attr_devaddr": "0x50", - "attr_devtype": "eeprom", - "attr_offset": "0x38", - "attr_mask": "0x0", - "attr_cmpval": "0xff", - "attr_len": "20" - }] - } - }, - - "PSU2": { - "dev_info": { - "device_type": "PSU", - "device_name": "PSU2", - "device_parent": "MUX1" - }, - "dev_attr": { - "dev_idx": "2", - "num_psu_fans": "1" - }, - "i2c": { - "interface": [{ - "itf": "pmbus", - "dev": "PSU2-PMBUS" - }, - { - "itf": "eeprom", - "dev": "PSU2-EEPROM" - } - ] - } - }, - - "PSU2-PMBUS": { - "dev_info": { - "device_type": "PSU-PMBUS", - "device_name": "PSU2-PMBUS", - "device_parent": "MUX1", - "virt_parent": "PSU2" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x8", - "dev_addr": "0x5b", - "dev_type": "psu_pmbus" - }, - "attr_list": [{ - "attr_name": "psu_present", - "attr_devaddr": "0x37", - "attr_devtype": "cpld", - "attr_offset": "0x51", - "attr_mask": "0x10", - "attr_cmpval": "0x0", - "attr_len": "1" - }, - { - "attr_name": "psu_model_name", - "attr_devaddr": "0x5b", - "attr_devtype": "pmbus", - "attr_offset": "0x9a", - "attr_mask": "0x0", - "attr_cmpval": "0xff", - "attr_len": "12" - }, - { - "attr_name": "psu_power_good", - "attr_devaddr": "0x37", - "attr_devtype": "cpld", - "attr_offset": "0x51", - "attr_mask": "0x20", - "attr_cmpval": "0x20", - "attr_len": "1" - }, - { - "attr_name": "psu_mfr_id", - "attr_devaddr": "0x5b", - "attr_devtype": "pmbus", - "attr_offset": "0x99", - "attr_mask": "0x0", - "attr_cmpval": "0xff", - "attr_len": "10" - }, - { - "attr_name": "psu_fan_dir", - "attr_devaddr": "0x5b", - "attr_devtype": "pmbus", - "attr_offset": "0xc3", - "attr_mask": "0x0", - "attr_cmpval": "0xff", - "attr_len": "5" - }, - { - "attr_name": "psu_v_out", - "attr_devaddr": "0x5b", - "attr_devtype": "pmbus", - "attr_offset": "0x8b", - "attr_mask": "0x0", - "attr_cmpval": "0xff", - "attr_len": "2" - }, - { - "attr_name": "psu_i_out", - "attr_devaddr": "0x5b", - "attr_devtype": "pmbus", - "attr_offset": "0x8c", - "attr_mask": "0x0", - "attr_cmpval": "0xff", - "attr_len": "2" - }, - { - "attr_name": "psu_p_out", - "attr_devaddr": "0x5b", - "attr_devtype": "pmbus", - "attr_offset": "0x96", - "attr_mask": "0x0", - "attr_cmpval": "0xff", - "attr_len": "2" - }, - { - "attr_name": "psu_fan1_speed_rpm", - "attr_devaddr": "0x5b", - "attr_devtype": "pmbus", - "attr_offset": "0x90", - "attr_mask": "0x0", - "attr_cmpval": "0xff", - "attr_len": "2" - }, - { - "attr_name": "psu_temp1_input", - "attr_devaddr": "0x5b", - "attr_devtype": "pmbus", - "attr_offset": "0x8d", - "attr_mask": "0x0", - "attr_cmpval": "0xff", - "attr_len": "2" - } - ] - } - }, - - "PSU2-EEPROM": { - "dev_info": { - "device_type": "PSU-EEPROM", - "device_name": "PSU2-EEPROM", - "device_parent": "MUX1", - "virt_parent": "PSU2" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x8", - "dev_addr": "0x53", - "dev_type": "psu_eeprom" - }, - "attr_list": [{ - "attr_name": "psu_serial_num", - "attr_devaddr": "0x53", - "attr_devtype": "eeprom", - "attr_offset": "0x38", - "attr_mask": "0x0", - "attr_cmpval": "0xff", - "attr_len": "20" - }] - } - }, - - "I2C-GPIO0": { - "dev_info": { - "device_type": "I2C-GPIO", - "device_name": "I2C-GPIO0", - "device_parent": "SYSTEM" - }, - "i2c": { - "topo_info": { - "dev_addr": "0x1" - }, - "DEVICES": [{ - "dev": "MAC_BOARD_CPLD1_B" - }, - { - "dev": "MAC_BOARD_CPLD2_B" - }, - { - "dev": "PORT-MUX1" - }, - { - "dev": "PORT-MUX2" - }, - { - "dev": "PORT-MUX3" - }, - { - "dev": "PORT-MUX4" - }, - { - "dev": "PORT-MUX5" - }, - { - "dev": "PORT-MUX6" - }, - { - "dev": "PORT-MUX7" - }, - { - "dev": "PORT-MUX8" - } - ] - } - }, - - "MAC_BOARD_CPLD1_B": { - "dev_info": { - "device_type": "CPLD", - "device_name": "MAC_BOARD_CPLD1_B", - "device_parent": "I2C-GPIO0" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x1", - "dev_addr": "0x34", - "dev_type": "i2c_cpld" - }, - "dev_attr": {} - } - }, - - "MAC_BOARD_CPLD2_B": { - "dev_info": { - "device_type": "CPLD", - "device_name": "MAC_BOARD_CPLD2_B", - "device_parent": "I2C-GPIO0" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x1", - "dev_addr": "0x36", - "dev_type": "i2c_cpld" - }, - "dev_attr": {} - } - }, - - "PORT-MUX1": { - "dev_info": { - "device_type": "MUX", - "device_name": "PORT-MUX1", - "device_parent": "I2C-GPIO0" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x1", - "dev_addr": "0x70", - "dev_type": "pca9548" - }, - "dev_attr": { - "virt_bus": "0xb" - }, - "channel": [{ - "chn": "0", - "dev": "PORT1" - }, - { - "chn": "1", - "dev": "PORT2" - }, - { - "chn": "2", - "dev": "PORT3" - }, - { - "chn": "3", - "dev": "PORT4" - }, - { - "chn": "4", - "dev": "PORT5" - }, - { - "chn": "5", - "dev": "PORT6" - }, - { - "chn": "6", - "dev": "PORT7" - }, - { - "chn": "7", - "dev": "PORT8" - } - ] - } - }, - - "PORT-MUX2": { - "dev_info": { - "device_type": "MUX", - "device_name": "PORT-MUX2", - "device_parent": "I2C-GPIO0" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x1", - "dev_addr": "0x71", - "dev_type": "pca9548" - }, - "dev_attr": { - "virt_bus": "0x13" - }, - "channel": [{ - "chn": "0", - "dev": "PORT9" - }, - { - "chn": "1", - "dev": "PORT10" - }, - { - "chn": "2", - "dev": "PORT11" - }, - { - "chn": "3", - "dev": "PORT12" - }, - { - "chn": "4", - "dev": "PORT13" - }, - { - "chn": "5", - "dev": "PORT14" - }, - { - "chn": "6", - "dev": "PORT15" - }, - { - "chn": "7", - "dev": "PORT16" - } - ] - } - }, - - "PORT-MUX3": { - "dev_info": { - "device_type": "MUX", - "device_name": "PORT-MUX3", - "device_parent": "I2C-GPIO0" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x1", - "dev_addr": "0x72", - "dev_type": "pca9548" - }, - "dev_attr": { - "virt_bus": "0x1b" - }, - "channel": [{ - "chn": "0", - "dev": "PORT17" - }, - { - "chn": "1", - "dev": "PORT18" - }, - { - "chn": "2", - "dev": "PORT19" - }, - { - "chn": "3", - "dev": "PORT20" - }, - { - "chn": "4", - "dev": "PORT21" - }, - { - "chn": "5", - "dev": "PORT22" - }, - { - "chn": "6", - "dev": "PORT23" - }, - { - "chn": "7", - "dev": "PORT24" - } - ] - } - }, - - "PORT-MUX4": { - "dev_info": { - "device_type": "MUX", - "device_name": "PORT-MUX4", - "device_parent": "I2C-GPIO0" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x1", - "dev_addr": "0x73", - "dev_type": "pca9548" - }, - "dev_attr": { - "virt_bus": "0x23" - }, - "channel": [{ - "chn": "0", - "dev": "PORT25" - }, - { - "chn": "1", - "dev": "PORT26" - }, - { - "chn": "2", - "dev": "PORT27" - }, - { - "chn": "3", - "dev": "PORT28" - }, - { - "chn": "4", - "dev": "PORT29" - }, - { - "chn": "5", - "dev": "PORT30" - }, - { - "chn": "6", - "dev": "PORT31" - }, - { - "chn": "7", - "dev": "PORT32" - } - ] - } - }, - - "PORT-MUX5": { - "dev_info": { - "device_type": "MUX", - "device_name": "PORT-MUX5", - "device_parent": "I2C-GPIO0" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x1", - "dev_addr": "0x74", - "dev_type": "pca9548" - }, - "dev_attr": { - "virt_bus": "0x2b" - }, - "channel": [{ - "chn": "0", - "dev": "PORT33" - }, - { - "chn": "1", - "dev": "PORT34" - }, - { - "chn": "2", - "dev": "PORT35" - }, - { - "chn": "3", - "dev": "PORT36" - }, - { - "chn": "4", - "dev": "PORT37" - }, - { - "chn": "5", - "dev": "PORT38" - }, - { - "chn": "6", - "dev": "PORT39" - }, - { - "chn": "7", - "dev": "PORT40" - } - ] - } - }, - - "PORT-MUX6": { - "dev_info": { - "device_type": "MUX", - "device_name": "PORT-MUX6", - "device_parent": "I2C-GPIO0" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x1", - "dev_addr": "0x75", - "dev_type": "pca9548" - }, - "dev_attr": { - "virt_bus": "0x33" - }, - "channel": [{ - "chn": "0", - "dev": "PORT41" - }, - { - "chn": "1", - "dev": "PORT42" - }, - { - "chn": "2", - "dev": "PORT43" - }, - { - "chn": "3", - "dev": "PORT44" - }, - { - "chn": "4", - "dev": "PORT45" - }, - { - "chn": "5", - "dev": "PORT46" - }, - { - "chn": "6", - "dev": "PORT47" - }, - { - "chn": "7", - "dev": "PORT48" - } - ] - } - }, - - "PORT-MUX7": { - "dev_info": { - "device_type": "MUX", - "device_name": "PORT-MUX7", - "device_parent": "I2C-GPIO0" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x1", - "dev_addr": "0x76", - "dev_type": "pca9548" - }, - "dev_attr": { - "virt_bus": "0x3b" - }, - "channel": [{ - "chn": "0", - "dev": "PORT49" - }, - { - "chn": "1", - "dev": "PORT50" - }, - { - "chn": "2", - "dev": "PORT51" - }, - { - "chn": "3", - "dev": "PORT52" - }, - { - "chn": "4", - "dev": "PORT53" - }, - { - "chn": "5", - "dev": "PORT54" - }, - { - "chn": "6", - "dev": "PORT55" - }, - { - "chn": "7", - "dev": "PORT56" - } - ] - } - }, - - "PORT-MUX8": { - "dev_info": { - "device_type": "MUX", - "device_name": "PORT-MUX8", - "device_parent": "I2C-GPIO0" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x1", - "dev_addr": "0x77", - "dev_type": "pca9548" - }, - "dev_attr": { - "virt_bus": "0x43" - }, - "channel": [] - } - }, - - "PORT1": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT1", - "device_parent": "PORT-MUX1" - }, - "dev_attr": { - "dev_idx": "1" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT1-EEPROM" - }, { - "itf": "control", - "dev": "PORT1-CTRL" - }] - } - }, - - "PORT1-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT1-EEPROM", - "device_parent": "PORT-MUX1", - "virt_parent": "PORT1" - }, - "i2c": { - "topo_info": { - "parent_bus": "0xb", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT1-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT1-CTRL", - "device_parent": "PORT-MUX1", - "virt_parent": "PORT1" - }, - "i2c": { - "topo_info": { - "parent_bus": "0xb", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x30", - "attr_mask": "0x00", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x60", - "attr_mask": "0x00", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x40", - "attr_mask": "0x00", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - "PORT2": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT2", - "device_parent": "PORT-MUX1" - }, - "dev_attr": { - "dev_idx": "2" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT2-EEPROM" - }, { - "itf": "control", - "dev": "PORT2-CTRL" - }] - } - }, - - "PORT2-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT2-EEPROM", - "device_parent": "PORT-MUX1", - "virt_parent": "PORT2" - }, - "i2c": { - "topo_info": { - "parent_bus": "0xc", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT2-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT2-CTRL", - "device_parent": "PORT-MUX1", - "virt_parent": "PORT2" - }, - "i2c": { - "topo_info": { - "parent_bus": "0xc", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x30", - "attr_mask": "0x01", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x60", - "attr_mask": "0x01", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x40", - "attr_mask": "0x01", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - "PORT3": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT3", - "device_parent": "PORT-MUX1" - }, - "dev_attr": { - "dev_idx": "3" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT3-EEPROM" - }, { - "itf": "control", - "dev": "PORT3-CTRL" - }] - } - }, - - "PORT3-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT3-EEPROM", - "device_parent": "PORT-MUX1", - "virt_parent": "PORT3" - }, - "i2c": { - "topo_info": { - "parent_bus": "0xd", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT3-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT3-CTRL", - "device_parent": "PORT-MUX1", - "virt_parent": "PORT3" - }, - "i2c": { - "topo_info": { - "parent_bus": "0xd", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x30", - "attr_mask": "0x02", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x60", - "attr_mask": "0x02", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x40", - "attr_mask": "0x02", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - - "PORT4": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT4", - "device_parent": "PORT-MUX1" - }, - "dev_attr": { - "dev_idx": "4" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT4-EEPROM" - }, { - "itf": "control", - "dev": "PORT4-CTRL" - }] - } - }, - - "PORT4-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT4-EEPROM", - "device_parent": "PORT-MUX1", - "virt_parent": "PORT4" - }, - "i2c": { - "topo_info": { - "parent_bus": "0xe", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT4-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT4-CTRL", - "device_parent": "PORT-MUX1", - "virt_parent": "PORT4" - }, - "i2c": { - "topo_info": { - "parent_bus": "0xe", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x30", - "attr_mask": "0x03", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x60", - "attr_mask": "0x03", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x40", - "attr_mask": "0x03", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - - "PORT5": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT5", - "device_parent": "PORT-MUX1" - }, - "dev_attr": { - "dev_idx": "5" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT5-EEPROM" - }, { - "itf": "control", - "dev": "PORT5-CTRL" - }] - } - }, - - "PORT5-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT5-EEPROM", - "device_parent": "PORT-MUX1", - "virt_parent": "PORT5" - }, - "i2c": { - "topo_info": { - "parent_bus": "0xf", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT5-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT5-CTRL", - "device_parent": "PORT-MUX1", - "virt_parent": "PORT5" - }, - "i2c": { - "topo_info": { - "parent_bus": "0xf", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x30", - "attr_mask": "0x04", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x60", - "attr_mask": "0x04", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x40", - "attr_mask": "0x04", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - - "PORT6": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT6", - "device_parent": "PORT-MUX1" - }, - "dev_attr": { - "dev_idx": "6" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT6-EEPROM" - }, { - "itf": "control", - "dev": "PORT6-CTRL" - }] - } - }, - - "PORT6-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT6-EEPROM", - "device_parent": "PORT-MUX1", - "virt_parent": "PORT6" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x10", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT6-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT6-CTRL", - "device_parent": "PORT-MUX1", - "virt_parent": "PORT6" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x10", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x30", - "attr_mask": "0x05", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x60", - "attr_mask": "0x05", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x40", - "attr_mask": "0x05", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - "PORT7": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT7", - "device_parent": "PORT-MUX1" - }, - "dev_attr": { - "dev_idx": "7" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT7-EEPROM" - }, { - "itf": "control", - "dev": "PORT7-CTRL" - }] - } - }, - - "PORT7-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT7-EEPROM", - "device_parent": "PORT-MUX1", - "virt_parent": "PORT7" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x11", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT7-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT7-CTRL", - "device_parent": "PORT-MUX1", - "virt_parent": "PORT7" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x11", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x30", - "attr_mask": "0x06", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x60", - "attr_mask": "0x06", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x40", - "attr_mask": "0x06", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - "PORT8": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT8", - "device_parent": "PORT-MUX1" - }, - "dev_attr": { - "dev_idx": "8" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT8-EEPROM" - }, { - "itf": "control", - "dev": "PORT8-CTRL" - }] - } - }, - - "PORT8-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT8-EEPROM", - "device_parent": "PORT-MUX1", - "virt_parent": "PORT8" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x12", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT8-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT8-CTRL", - "device_parent": "PORT-MUX1", - "virt_parent": "PORT8" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x12", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x30", - "attr_mask": "0x07", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x60", - "attr_mask": "0x07", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x40", - "attr_mask": "0x07", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - "PORT9": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT9", - "device_parent": "PORT-MUX2" - }, - "dev_attr": { - "dev_idx": "9" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT9-EEPROM" - }, { - "itf": "control", - "dev": "PORT9-CTRL" - }] - } - }, - - "PORT9-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT9-EEPROM", - "device_parent": "PORT-MUX2", - "virt_parent": "PORT9" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x13", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT9-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT9-CTRL", - "device_parent": "PORT-MUX2", - "virt_parent": "PORT9" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x13", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x31", - "attr_mask": "0x00", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x61", - "attr_mask": "0x00", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x41", - "attr_mask": "0x00", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - "PORT10": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT10", - "device_parent": "PORT-MUX2" - }, - "dev_attr": { - "dev_idx": "10" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT10-EEPROM" - }, { - "itf": "control", - "dev": "PORT10-CTRL" - }] - } - }, - - "PORT10-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT10-EEPROM", - "device_parent": "PORT-MUX2", - "virt_parent": "PORT10" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x14", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT10-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT10-CTRL", - "device_parent": "PORT-MUX2", - "virt_parent": "PORT10" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x14", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x31", - "attr_mask": "0x01", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x61", - "attr_mask": "0x01", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x41", - "attr_mask": "0x01", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - - "PORT11": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT11", - "device_parent": "PORT-MUX2" - }, - "dev_attr": { - "dev_idx": "11" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT11-EEPROM" - }, { - "itf": "control", - "dev": "PORT11-CTRL" - }] - } - }, - - "PORT11-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT11-EEPROM", - "device_parent": "PORT-MUX2", - "virt_parent": "PORT11" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x15", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT11-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT11-CTRL", - "device_parent": "PORT-MUX2", - "virt_parent": "PORT11" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x15", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x31", - "attr_mask": "0x02", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x61", - "attr_mask": "0x02", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x41", - "attr_mask": "0x02", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - - "PORT12": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT12", - "device_parent": "PORT-MUX2" - }, - "dev_attr": { - "dev_idx": "12" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT12-EEPROM" - }, { - "itf": "control", - "dev": "PORT12-CTRL" - }] - } - }, - - "PORT12-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT12-EEPROM", - "device_parent": "PORT-MUX2", - "virt_parent": "PORT12" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x16", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT12-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT12-CTRL", - "device_parent": "PORT-MUX2", - "virt_parent": "PORT12" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x16", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x31", - "attr_mask": "0x03", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x61", - "attr_mask": "0x03", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x41", - "attr_mask": "0x03", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - - "PORT13": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT13", - "device_parent": "PORT-MUX2" - }, - "dev_attr": { - "dev_idx": "13" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT13-EEPROM" - }, { - "itf": "control", - "dev": "PORT13-CTRL" - }] - } - }, - - "PORT13-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT13-EEPROM", - "device_parent": "PORT-MUX2", - "virt_parent": "PORT13" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x17", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT13-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT13-CTRL", - "device_parent": "PORT-MUX2", - "virt_parent": "PORT13" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x17", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x31", - "attr_mask": "0x04", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x61", - "attr_mask": "0x04", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x41", - "attr_mask": "0x04", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - - "PORT14": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT14", - "device_parent": "PORT-MUX2" - }, - "dev_attr": { - "dev_idx": "14" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT14-EEPROM" - }, { - "itf": "control", - "dev": "PORT14-CTRL" - }] - } - }, - - "PORT14-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT14-EEPROM", - "device_parent": "PORT-MUX2", - "virt_parent": "PORT14" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x18", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT14-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT14-CTRL", - "device_parent": "PORT-MUX2", - "virt_parent": "PORT14" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x18", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x31", - "attr_mask": "0x05", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x61", - "attr_mask": "0x05", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x41", - "attr_mask": "0x05", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - "PORT15": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT15", - "device_parent": "PORT-MUX2" - }, - "dev_attr": { - "dev_idx": "15" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT15-EEPROM" - }, { - "itf": "control", - "dev": "PORT15-CTRL" - }] - } - }, - - "PORT15-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT15-EEPROM", - "device_parent": "PORT-MUX2", - "virt_parent": "PORT15" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x19", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT15-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT15-CTRL", - "device_parent": "PORT-MUX2", - "virt_parent": "PORT15" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x19", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x31", - "attr_mask": "0x06", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x61", - "attr_mask": "0x06", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x41", - "attr_mask": "0x06", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - "PORT16": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT16", - "device_parent": "PORT-MUX2" - }, - "dev_attr": { - "dev_idx": "16" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT16-EEPROM" - }, { - "itf": "control", - "dev": "PORT16-CTRL" - }] - } - }, - - "PORT16-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT16-EEPROM", - "device_parent": "PORT-MUX2", - "virt_parent": "PORT16" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x1a", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT16-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT16-CTRL", - "device_parent": "PORT-MUX2", - "virt_parent": "PORT16" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x1a", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x31", - "attr_mask": "0x07", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x61", - "attr_mask": "0x07", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x41", - "attr_mask": "0x07", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - "PORT17": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT17", - "device_parent": "PORT-MUX3" - }, - "dev_attr": { - "dev_idx": "17" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT17-EEPROM" - }, { - "itf": "control", - "dev": "PORT17-CTRL" - }] - } - }, - - "PORT17-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT17-EEPROM", - "device_parent": "PORT-MUX3", - "virt_parent": "PORT17" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x1b", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT17-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT17-CTRL", - "device_parent": "PORT-MUX3", - "virt_parent": "PORT17" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x1b", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x32", - "attr_mask": "0x00", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x62", - "attr_mask": "0x00", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x42", - "attr_mask": "0x00", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - "PORT18": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT18", - "device_parent": "PORT-MUX3" - }, - "dev_attr": { - "dev_idx": "18" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT18-EEPROM" - }, { - "itf": "control", - "dev": "PORT18-CTRL" - }] - } - }, - - "PORT18-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT18-EEPROM", - "device_parent": "PORT-MUX3", - "virt_parent": "PORT18" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x1c", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT18-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT18-CTRL", - "device_parent": "PORT-MUX3", - "virt_parent": "PORT18" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x1c", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x32", - "attr_mask": "0x01", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x62", - "attr_mask": "0x01", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x42", - "attr_mask": "0x01", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - - "PORT19": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT19", - "device_parent": "PORT-MUX3" - }, - "dev_attr": { - "dev_idx": "19" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT19-EEPROM" - }, { - "itf": "control", - "dev": "PORT19-CTRL" - }] - } - }, - - "PORT19-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT19-EEPROM", - "device_parent": "PORT-MUX3", - "virt_parent": "PORT19" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x1d", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT19-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT19-CTRL", - "device_parent": "PORT-MUX3", - "virt_parent": "PORT19" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x1d", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x32", - "attr_mask": "0x02", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x62", - "attr_mask": "0x02", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x42", - "attr_mask": "0x02", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - - "PORT20": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT20", - "device_parent": "PORT-MUX3" - }, - "dev_attr": { - "dev_idx": "20" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT20-EEPROM" - }, { - "itf": "control", - "dev": "PORT20-CTRL" - }] - } - }, - - "PORT20-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT20-EEPROM", - "device_parent": "PORT-MUX3", - "virt_parent": "PORT20" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x1e", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT20-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT20-CTRL", - "device_parent": "PORT-MUX3", - "virt_parent": "PORT20" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x1e", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x32", - "attr_mask": "0x03", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x62", - "attr_mask": "0x03", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x42", - "attr_mask": "0x03", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - - "PORT21": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT21", - "device_parent": "PORT-MUX3" - }, - "dev_attr": { - "dev_idx": "21" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT21-EEPROM" - }, { - "itf": "control", - "dev": "PORT21-CTRL" - }] - } - }, - - "PORT21-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT21-EEPROM", - "device_parent": "PORT-MUX3", - "virt_parent": "PORT21" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x1f", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT21-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT21-CTRL", - "device_parent": "PORT-MUX3", - "virt_parent": "PORT21" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x1f", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x32", - "attr_mask": "0x04", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x62", - "attr_mask": "0x04", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x42", - "attr_mask": "0x04", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - - "PORT22": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT22", - "device_parent": "PORT-MUX3" - }, - "dev_attr": { - "dev_idx": "22" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT22-EEPROM" - }, { - "itf": "control", - "dev": "PORT22-CTRL" - }] - } - }, - - "PORT22-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT22-EEPROM", - "device_parent": "PORT-MUX3", - "virt_parent": "PORT22" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x20", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT22-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT22-CTRL", - "device_parent": "PORT-MUX3", - "virt_parent": "PORT22" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x20", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x32", - "attr_mask": "0x05", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x62", - "attr_mask": "0x05", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x42", - "attr_mask": "0x05", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - "PORT23": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT23", - "device_parent": "PORT-MUX3" - }, - "dev_attr": { - "dev_idx": "23" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT23-EEPROM" - }, { - "itf": "control", - "dev": "PORT23-CTRL" - }] - } - }, - - "PORT23-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT23-EEPROM", - "device_parent": "PORT-MUX3", - "virt_parent": "PORT23" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x21", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT23-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT23-CTRL", - "device_parent": "PORT-MUX3", - "virt_parent": "PORT23" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x21", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x32", - "attr_mask": "0x06", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x62", - "attr_mask": "0x06", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x42", - "attr_mask": "0x06", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - "PORT24": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT24", - "device_parent": "PORT-MUX3" - }, - "dev_attr": { - "dev_idx": "24" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT24-EEPROM" - }, { - "itf": "control", - "dev": "PORT24-CTRL" - }] - } - }, - - "PORT24-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT24-EEPROM", - "device_parent": "PORT-MUX3", - "virt_parent": "PORT24" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x22", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT24-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT24-CTRL", - "device_parent": "PORT-MUX3", - "virt_parent": "PORT24" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x22", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x32", - "attr_mask": "0x07", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x62", - "attr_mask": "0x07", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD1_B", - "attr_devaddr": "0x34", - "attr_devtype": "cpld", - "attr_offset": "0x42", - "attr_mask": "0x07", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - "PORT25": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT25", - "device_parent": "PORT-MUX4" - }, - "dev_attr": { - "dev_idx": "25" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT25-EEPROM" - }, { - "itf": "control", - "dev": "PORT25-CTRL" - }] - } - }, - - "PORT25-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT25-EEPROM", - "device_parent": "PORT-MUX4", - "virt_parent": "PORT25" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x23", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT25-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT25-CTRL", - "device_parent": "PORT-MUX4", - "virt_parent": "PORT25" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x23", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x30", - "attr_mask": "0x00", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x60", - "attr_mask": "0x00", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x40", - "attr_mask": "0x00", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - "PORT26": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT26", - "device_parent": "PORT-MUX4" - }, - "dev_attr": { - "dev_idx": "26" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT26-EEPROM" - }, { - "itf": "control", - "dev": "PORT26-CTRL" - }] - } - }, - - "PORT26-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT26-EEPROM", - "device_parent": "PORT-MUX4", - "virt_parent": "PORT26" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x24", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT26-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT26-CTRL", - "device_parent": "PORT-MUX4", - "virt_parent": "PORT26" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x24", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x30", - "attr_mask": "0x01", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x60", - "attr_mask": "0x01", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x40", - "attr_mask": "0x01", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - - "PORT27": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT27", - "device_parent": "PORT-MUX4" - }, - "dev_attr": { - "dev_idx": "27" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT27-EEPROM" - }, { - "itf": "control", - "dev": "PORT27-CTRL" - }] - } - }, - - "PORT27-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT27-EEPROM", - "device_parent": "PORT-MUX4", - "virt_parent": "PORT27" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x25", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT27-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT27-CTRL", - "device_parent": "PORT-MUX4", - "virt_parent": "PORT27" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x25", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x30", - "attr_mask": "0x02", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x60", - "attr_mask": "0x02", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x40", - "attr_mask": "0x02", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - - "PORT28": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT28", - "device_parent": "PORT-MUX4" - }, - "dev_attr": { - "dev_idx": "28" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT28-EEPROM" - }, { - "itf": "control", - "dev": "PORT28-CTRL" - }] - } - }, - - "PORT28-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT28-EEPROM", - "device_parent": "PORT-MUX4", - "virt_parent": "PORT28" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x26", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT28-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT28-CTRL", - "device_parent": "PORT-MUX4", - "virt_parent": "PORT28" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x26", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x30", - "attr_mask": "0x03", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x60", - "attr_mask": "0x03", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x40", - "attr_mask": "0x03", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - - "PORT29": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT29", - "device_parent": "PORT-MUX4" - }, - "dev_attr": { - "dev_idx": "29" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT29-EEPROM" - }, { - "itf": "control", - "dev": "PORT29-CTRL" - }] - } - }, - - "PORT29-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT29-EEPROM", - "device_parent": "PORT-MUX4", - "virt_parent": "PORT29" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x27", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT29-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT29-CTRL", - "device_parent": "PORT-MUX4", - "virt_parent": "PORT29" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x27", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x30", - "attr_mask": "0x04", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x60", - "attr_mask": "0x04", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x40", - "attr_mask": "0x04", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - - "PORT30": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT30", - "device_parent": "PORT-MUX4" - }, - "dev_attr": { - "dev_idx": "30" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT30-EEPROM" - }, { - "itf": "control", - "dev": "PORT30-CTRL" - }] - } - }, - - "PORT30-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT30-EEPROM", - "device_parent": "PORT-MUX4", - "virt_parent": "PORT30" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x28", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT30-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT30-CTRL", - "device_parent": "PORT-MUX4", - "virt_parent": "PORT30" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x28", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x30", - "attr_mask": "0x05", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x60", - "attr_mask": "0x05", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x40", - "attr_mask": "0x05", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - "PORT31": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT31", - "device_parent": "PORT-MUX4" - }, - "dev_attr": { - "dev_idx": "31" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT31-EEPROM" - }, { - "itf": "control", - "dev": "PORT31-CTRL" - }] - } - }, - - "PORT31-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT31-EEPROM", - "device_parent": "PORT-MUX4", - "virt_parent": "PORT31" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x29", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT31-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT31-CTRL", - "device_parent": "PORT-MUX4", - "virt_parent": "PORT31" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x29", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x30", - "attr_mask": "0x06", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x60", - "attr_mask": "0x06", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x40", - "attr_mask": "0x06", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - "PORT32": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT32", - "device_parent": "PORT-MUX4" - }, - "dev_attr": { - "dev_idx": "32" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT32-EEPROM" - }, { - "itf": "control", - "dev": "PORT32-CTRL" - }] - } - }, - - "PORT32-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT32-EEPROM", - "device_parent": "PORT-MUX4", - "virt_parent": "PORT32" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x2a", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT32-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT32-CTRL", - "device_parent": "PORT-MUX4", - "virt_parent": "PORT32" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x2a", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x30", - "attr_mask": "0x07", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x60", - "attr_mask": "0x07", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x40", - "attr_mask": "0x07", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - "PORT33": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT33", - "device_parent": "PORT-MUX5" - }, - "dev_attr": { - "dev_idx": "33" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT33-EEPROM" - }, { - "itf": "control", - "dev": "PORT33-CTRL" - }] - } - }, - - "PORT33-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT33-EEPROM", - "device_parent": "PORT-MUX5", - "virt_parent": "PORT33" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x2b", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT33-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT33-CTRL", - "device_parent": "PORT-MUX5", - "virt_parent": "PORT33" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x2b", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x31", - "attr_mask": "0x00", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x61", - "attr_mask": "0x00", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x41", - "attr_mask": "0x00", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - "PORT34": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT34", - "device_parent": "PORT-MUX5" - }, - "dev_attr": { - "dev_idx": "34" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT34-EEPROM" - }, { - "itf": "control", - "dev": "PORT34-CTRL" - }] - } - }, - - "PORT34-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT34-EEPROM", - "device_parent": "PORT-MUX5", - "virt_parent": "PORT34" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x2c", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT34-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT34-CTRL", - "device_parent": "PORT-MUX5", - "virt_parent": "PORT34" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x2c", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x31", - "attr_mask": "0x01", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x61", - "attr_mask": "0x01", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x41", - "attr_mask": "0x01", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - - "PORT35": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT35", - "device_parent": "PORT-MUX5" - }, - "dev_attr": { - "dev_idx": "35" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT35-EEPROM" - }, { - "itf": "control", - "dev": "PORT35-CTRL" - }] - } - }, - - "PORT35-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT35-EEPROM", - "device_parent": "PORT-MUX5", - "virt_parent": "PORT35" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x2d", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT35-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT35-CTRL", - "device_parent": "PORT-MUX5", - "virt_parent": "PORT35" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x2d", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x31", - "attr_mask": "0x02", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x61", - "attr_mask": "0x02", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x41", - "attr_mask": "0x02", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - - "PORT36": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT36", - "device_parent": "PORT-MUX5" - }, - "dev_attr": { - "dev_idx": "36" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT36-EEPROM" - }, { - "itf": "control", - "dev": "PORT36-CTRL" - }] - } - }, - - "PORT36-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT36-EEPROM", - "device_parent": "PORT-MUX5", - "virt_parent": "PORT36" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x2e", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT36-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT36-CTRL", - "device_parent": "PORT-MUX5", - "virt_parent": "PORT36" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x2e", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x31", - "attr_mask": "0x03", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x61", - "attr_mask": "0x03", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x41", - "attr_mask": "0x03", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - - "PORT37": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT37", - "device_parent": "PORT-MUX5" - }, - "dev_attr": { - "dev_idx": "37" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT37-EEPROM" - }, { - "itf": "control", - "dev": "PORT37-CTRL" - }] - } - }, - - "PORT37-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT37-EEPROM", - "device_parent": "PORT-MUX5", - "virt_parent": "PORT37" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x2f", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT37-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT37-CTRL", - "device_parent": "PORT-MUX5", - "virt_parent": "PORT37" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x2f", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x31", - "attr_mask": "0x04", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x61", - "attr_mask": "0x04", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x41", - "attr_mask": "0x04", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - - "PORT38": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT38", - "device_parent": "PORT-MUX5" - }, - "dev_attr": { - "dev_idx": "38" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT38-EEPROM" - }, { - "itf": "control", - "dev": "PORT38-CTRL" - }] - } - }, - - "PORT38-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT38-EEPROM", - "device_parent": "PORT-MUX5", - "virt_parent": "PORT38" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x30", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT38-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT38-CTRL", - "device_parent": "PORT-MUX5", - "virt_parent": "PORT38" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x30", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x31", - "attr_mask": "0x05", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x61", - "attr_mask": "0x05", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x41", - "attr_mask": "0x05", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - "PORT39": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT39", - "device_parent": "PORT-MUX5" - }, - "dev_attr": { - "dev_idx": "39" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT39-EEPROM" - }, { - "itf": "control", - "dev": "PORT39-CTRL" - }] - } - }, - - "PORT39-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT39-EEPROM", - "device_parent": "PORT-MUX5", - "virt_parent": "PORT39" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x31", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT39-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT39-CTRL", - "device_parent": "PORT-MUX5", - "virt_parent": "PORT39" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x31", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x31", - "attr_mask": "0x06", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x61", - "attr_mask": "0x06", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x41", - "attr_mask": "0x06", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - "PORT40": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT40", - "device_parent": "PORT-MUX5" - }, - "dev_attr": { - "dev_idx": "40" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT40-EEPROM" - }, { - "itf": "control", - "dev": "PORT40-CTRL" - }] - } - }, - - "PORT40-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT40-EEPROM", - "device_parent": "PORT-MUX5", - "virt_parent": "PORT40" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x32", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT40-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT40-CTRL", - "device_parent": "PORT-MUX5", - "virt_parent": "PORT40" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x32", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x31", - "attr_mask": "0x07", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x61", - "attr_mask": "0x07", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x41", - "attr_mask": "0x07", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - "PORT41": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT41", - "device_parent": "PORT-MUX6" - }, - "dev_attr": { - "dev_idx": "41" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT41-EEPROM" - }, { - "itf": "control", - "dev": "PORT41-CTRL" - }] - } - }, - - "PORT41-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT41-EEPROM", - "device_parent": "PORT-MUX6", - "virt_parent": "PORT41" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x33", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT41-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT41-CTRL", - "device_parent": "PORT-MUX6", - "virt_parent": "PORT41" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x33", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x32", - "attr_mask": "0x00", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x62", - "attr_mask": "0x00", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x42", - "attr_mask": "0x00", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - "PORT42": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT42", - "device_parent": "PORT-MUX6" - }, - "dev_attr": { - "dev_idx": "42" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT42-EEPROM" - }, { - "itf": "control", - "dev": "PORT42-CTRL" - }] - } - }, - - "PORT42-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT42-EEPROM", - "device_parent": "PORT-MUX6", - "virt_parent": "PORT42" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x34", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT42-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT42-CTRL", - "device_parent": "PORT-MUX6", - "virt_parent": "PORT42" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x34", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x32", - "attr_mask": "0x01", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x62", - "attr_mask": "0x01", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x42", - "attr_mask": "0x01", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - - "PORT43": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT43", - "device_parent": "PORT-MUX6" - }, - "dev_attr": { - "dev_idx": "43" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT43-EEPROM" - }, { - "itf": "control", - "dev": "PORT43-CTRL" - }] - } - }, - - "PORT43-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT43-EEPROM", - "device_parent": "PORT-MUX6", - "virt_parent": "PORT43" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x35", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT43-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT43-CTRL", - "device_parent": "PORT-MUX6", - "virt_parent": "PORT43" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x35", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x32", - "attr_mask": "0x02", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x62", - "attr_mask": "0x02", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x42", - "attr_mask": "0x02", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - - "PORT44": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT44", - "device_parent": "PORT-MUX6" - }, - "dev_attr": { - "dev_idx": "44" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT44-EEPROM" - }, { - "itf": "control", - "dev": "PORT44-CTRL" - }] - } - }, - - "PORT44-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT44-EEPROM", - "device_parent": "PORT-MUX6", - "virt_parent": "PORT44" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x36", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT44-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT44-CTRL", - "device_parent": "PORT-MUX6", - "virt_parent": "PORT44" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x36", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x32", - "attr_mask": "0x03", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x62", - "attr_mask": "0x03", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x42", - "attr_mask": "0x03", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - - "PORT45": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT45", - "device_parent": "PORT-MUX6" - }, - "dev_attr": { - "dev_idx": "45" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT45-EEPROM" - }, { - "itf": "control", - "dev": "PORT45-CTRL" - }] - } - }, - - "PORT45-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT45-EEPROM", - "device_parent": "PORT-MUX6", - "virt_parent": "PORT45" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x37", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT45-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT45-CTRL", - "device_parent": "PORT-MUX6", - "virt_parent": "PORT45" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x37", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x32", - "attr_mask": "0x04", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x62", - "attr_mask": "0x04", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x42", - "attr_mask": "0x04", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - - "PORT46": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT46", - "device_parent": "PORT-MUX6" - }, - "dev_attr": { - "dev_idx": "46" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT46-EEPROM" - }, { - "itf": "control", - "dev": "PORT46-CTRL" - }] - } - }, - - "PORT46-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT46-EEPROM", - "device_parent": "PORT-MUX6", - "virt_parent": "PORT46" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x38", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT46-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT46-CTRL", - "device_parent": "PORT-MUX6", - "virt_parent": "PORT46" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x38", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x32", - "attr_mask": "0x05", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x62", - "attr_mask": "0x05", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x42", - "attr_mask": "0x05", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - "PORT47": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT47", - "device_parent": "PORT-MUX6" - }, - "dev_attr": { - "dev_idx": "47" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT47-EEPROM" - }, { - "itf": "control", - "dev": "PORT47-CTRL" - }] - } - }, - - "PORT47-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT47-EEPROM", - "device_parent": "PORT-MUX6", - "virt_parent": "PORT47" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x39", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT47-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT47-CTRL", - "device_parent": "PORT-MUX6", - "virt_parent": "PORT47" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x39", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x32", - "attr_mask": "0x06", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x62", - "attr_mask": "0x06", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x42", - "attr_mask": "0x06", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - "PORT48": { - "dev_info": { - "device_type": "SFP28", - "device_name": "PORT48", - "device_parent": "PORT-MUX6" - }, - "dev_attr": { - "dev_idx": "48" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT48-EEPROM" - }, { - "itf": "control", - "dev": "PORT48-CTRL" - }] - } - }, - - "PORT48-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT48-EEPROM", - "device_parent": "PORT-MUX6", - "virt_parent": "PORT48" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x3a", - "dev_addr": "0x50", - "dev_type": "optoe2" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT48-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT48-CTRL", - "device_parent": "PORT-MUX6", - "virt_parent": "PORT48" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x3a", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x32", - "attr_mask": "0x07", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_txdisable", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x62", - "attr_mask": "0x07", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_intr_status", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x42", - "attr_mask": "0x07", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - "PORT49": { - "dev_info": { - "device_type": "QSFP28", - "device_name": "PORT49", - "device_parent": "PORT-MUX7" - }, - "dev_attr": { - "dev_idx": "49" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT49-EEPROM" - }, { - "itf": "control", - "dev": "PORT49-CTRL" - }] - } - }, - - "PORT49-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT49-EEPROM", - "device_parent": "PORT-MUX7", - "virt_parent": "PORT49" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x3b", - "dev_addr": "0x50", - "dev_type": "optoe1" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT49-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT49-CTRL", - "device_parent": "PORT-MUX7", - "virt_parent": "PORT49" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x3b", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x33", - "attr_mask": "0x00", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_reset", - "attr_devaddr": "0x36", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devtype": "cpld", - "attr_offset": "0xb9", - "attr_mask": "0x00", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - "PORT50": { - "dev_info": { - "device_type": "QSFP28", - "device_name": "PORT50", - "device_parent": "PORT-MUX7" - }, - "dev_attr": { - "dev_idx": "50" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT50-EEPROM" - }, { - "itf": "control", - "dev": "PORT50-CTRL" - }] - } - }, - - "PORT50-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT50-EEPROM", - "device_parent": "PORT-MUX7", - "virt_parent": "PORT50" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x3c", - "dev_addr": "0x50", - "dev_type": "optoe1" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT50-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT50-CTRL", - "device_parent": "PORT-MUX7", - "virt_parent": "PORT50" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x3c", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x33", - "attr_mask": "0x01", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_reset", - "attr_devaddr": "0x36", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devtype": "cpld", - "attr_offset": "0xb9", - "attr_mask": "0x01", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - - "PORT51": { - "dev_info": { - "device_type": "QSFP28", - "device_name": "PORT51", - "device_parent": "PORT-MUX7" - }, - "dev_attr": { - "dev_idx": "51" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT51-EEPROM" - }, { - "itf": "control", - "dev": "PORT51-CTRL" - }] - } - }, - - "PORT51-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT51-EEPROM", - "device_parent": "PORT-MUX7", - "virt_parent": "PORT51" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x3d", - "dev_addr": "0x50", - "dev_type": "optoe1" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT51-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT51-CTRL", - "device_parent": "PORT-MUX7", - "virt_parent": "PORT51" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x3d", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x33", - "attr_mask": "0x02", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_reset", - "attr_devaddr": "0x36", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devtype": "cpld", - "attr_offset": "0xb9", - "attr_mask": "0x02", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - - "PORT52": { - "dev_info": { - "device_type": "QSFP28", - "device_name": "PORT52", - "device_parent": "PORT-MUX7" - }, - "dev_attr": { - "dev_idx": "52" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT52-EEPROM" - }, { - "itf": "control", - "dev": "PORT52-CTRL" - }] - } - }, - - "PORT52-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT52-EEPROM", - "device_parent": "PORT-MUX7", - "virt_parent": "PORT52" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x3e", - "dev_addr": "0x50", - "dev_type": "optoe1" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT52-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT52-CTRL", - "device_parent": "PORT-MUX7", - "virt_parent": "PORT52" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x3e", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x33", - "attr_mask": "0x03", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_reset", - "attr_devaddr": "0x36", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devtype": "cpld", - "attr_offset": "0xb9", - "attr_mask": "0x03", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - - "PORT53": { - "dev_info": { - "device_type": "QSFP28", - "device_name": "PORT53", - "device_parent": "PORT-MUX7" - }, - "dev_attr": { - "dev_idx": "53" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT53-EEPROM" - }, { - "itf": "control", - "dev": "PORT53-CTRL" - }] - } - }, - - "PORT53-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT53-EEPROM", - "device_parent": "PORT-MUX7", - "virt_parent": "PORT53" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x3f", - "dev_addr": "0x50", - "dev_type": "optoe1" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT53-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT53-CTRL", - "device_parent": "PORT-MUX7", - "virt_parent": "PORT53" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x3f", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x33", - "attr_mask": "0x04", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_reset", - "attr_devaddr": "0x36", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devtype": "cpld", - "attr_offset": "0xb9", - "attr_mask": "0x04", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - - "PORT54": { - "dev_info": { - "device_type": "QSFP28", - "device_name": "PORT54", - "device_parent": "PORT-MUX7" - }, - "dev_attr": { - "dev_idx": "54" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT54-EEPROM" - }, { - "itf": "control", - "dev": "PORT54-CTRL" - }] - } - }, - - "PORT54-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT54-EEPROM", - "device_parent": "PORT-MUX7", - "virt_parent": "PORT54" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x40", - "dev_addr": "0x50", - "dev_type": "optoe1" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT54-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT54-CTRL", - "device_parent": "PORT-MUX7", - "virt_parent": "PORT54" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x40", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x33", - "attr_mask": "0x05", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_reset", - "attr_devaddr": "0x36", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devtype": "cpld", - "attr_offset": "0xb9", - "attr_mask": "0x05", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - "PORT55": { - "dev_info": { - "device_type": "QSFP28", - "device_name": "PORT55", - "device_parent": "PORT-MUX7" - }, - "dev_attr": { - "dev_idx": "55" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT55-EEPROM" - }, { - "itf": "control", - "dev": "PORT55-CTRL" - }] - } - }, - - "PORT55-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT55-EEPROM", - "device_parent": "PORT-MUX7", - "virt_parent": "PORT55" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x41", - "dev_addr": "0x50", - "dev_type": "optoe1" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT55-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT55-CTRL", - "device_parent": "PORT-MUX7", - "virt_parent": "PORT55" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x41", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x33", - "attr_mask": "0x06", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_reset", - "attr_devaddr": "0x36", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devtype": "cpld", - "attr_offset": "0xb9", - "attr_mask": "0x06", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - "PORT56": { - "dev_info": { - "device_type": "QSFP28", - "device_name": "PORT56", - "device_parent": "PORT-MUX7" - }, - "dev_attr": { - "dev_idx": "56" - }, - "i2c": { - "interface": [{ - "itf": "eeprom", - "dev": "PORT56-EEPROM" - }, { - "itf": "control", - "dev": "PORT56-CTRL" - }] - } - }, - - "PORT56-EEPROM": { - "dev_info": { - "device_type": "", - "device_name": "PORT56-EEPROM", - "device_parent": "PORT-MUX7", - "virt_parent": "PORT56" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x42", - "dev_addr": "0x50", - "dev_type": "optoe1" - }, - "attr_list": [{ - "attr_name": "eeprom" - }] - } - }, - - "PORT56-CTRL": { - "dev_info": { - "device_type": "", - "device_name": "PORT56-CTRL", - "device_parent": "PORT-MUX7", - "virt_parent": "PORT56" - }, - "i2c": { - "topo_info": { - "parent_bus": "0x42", - "dev_addr": "0x53", - "dev_type": "pddf_xcvr" - }, - "attr_list": [{ - "attr_name": "xcvr_present", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devaddr": "0x36", - "attr_devtype": "cpld", - "attr_offset": "0x33", - "attr_mask": "0x07", - "attr_cmpval": "0x0", - "attr_len": "1" - }, { - "attr_name": "xcvr_reset", - "attr_devaddr": "0x36", - "attr_devname": "MAC_BOARD_CPLD2_B", - "attr_devtype": "cpld", - "attr_offset": "0xb9", - "attr_mask": "0x07", - "attr_cmpval": "0x0", - "attr_len": "1" - }] - } - }, - - "FRONT_BOARD_BMC_LED": { - "dev_info": { - "device_type": "LED", - "device_name": "DIAG_LED" - }, - "dev_attr": { - "index": "0" - }, - "i2c": { - "attr_list": [{ - "attr_name": "STATUS_LED_COLOR_RED", - "descr": "Red", - "bits": "2:0", - "value": "0x2", - "swpld_addr": "0x33", - "swpld_addr_offset": "0xb1" - }, - { - "attr_name": "STATUS_LED_COLOR_RED_BLINK", - "descr": "Red Blinking", - "bits": "2:0", - "value": "0x1", - "swpld_addr": "0x33", - "swpld_addr_offset": "0xb1" - }, - { - "attr_name": "STATUS_LED_COLOR_GREEN", - "descr": "Green", - "bits": "2:0", - "value": "0x4", - "swpld_addr": "0x33", - "swpld_addr_offset": "0xb1" - }, - { - "attr_name": "STATUS_LED_COLOR_GREEN_BLINK", - "descr": "Green Blinking", - "bits": "2:0", - "value": "0x3", - "swpld_addr": "0x33", - "swpld_addr_offset": "0xb1" - }, - { - "attr_name": "STATUS_LED_COLOR_AMBER", - "descr": "Amber", - "bits": "2:0", - "value": "0x6", - "swpld_addr": "0x33", - "swpld_addr_offset": "0xb1" - }, - { - "attr_name": "STATUS_LED_COLOR_AMBER_BLINK", - "descr": "Amber Blinking", - "bits": "2:0", - "value": "0x5", - "swpld_addr": "0x33", - "swpld_addr_offset": "0xb1" - }, - { - "attr_name": "STATUS_LED_COLOR_OFF", - "descr": "Off", - "bits": "2:0", - "value": "0x0", - "swpld_addr": "0x33", - "swpld_addr_offset": "0xb1" - } - ] - } - }, - - "FRONT_BOARD_CPU_LED": { - "dev_info": { - "device_type": "LED", - "device_name": "SYS_LED" - }, - "dev_attr": { - "index": "0" - }, - "i2c": { - "attr_list": [{ - "attr_name": "STATUS_LED_COLOR_RED", - "descr": "Red", - "bits": "2:0", - "value": "0x2", - "swpld_addr": "0x33", - "swpld_addr_offset": "0xb2" - }, - { - "attr_name": "STATUS_LED_COLOR_RED_BLINK", - "descr": "Red Blinking", - "bits": "2:0", - "value": "0x1", - "swpld_addr": "0x33", - "swpld_addr_offset": "0xb2" - }, - { - "attr_name": "STATUS_LED_COLOR_GREEN", - "descr": "Green", - "bits": "2:0", - "value": "0x4", - "swpld_addr": "0x33", - "swpld_addr_offset": "0xb2" - }, - { - "attr_name": "STATUS_LED_COLOR_GREEN_BLINK", - "descr": "Green Blinking", - "bits": "2:0", - "value": "0x3", - "swpld_addr": "0x33", - "swpld_addr_offset": "0xb2" - }, - { - "attr_name": "STATUS_LED_COLOR_AMBER", - "descr": "Amber", - "bits": "2:0", - "value": "0x6", - "swpld_addr": "0x33", - "swpld_addr_offset": "0xb2" - }, - { - "attr_name": "STATUS_LED_COLOR_AMBER_BLINK", - "descr": "Amber Blinking", - "bits": "2:0", - "value": "0x5", - "swpld_addr": "0x33", - "swpld_addr_offset": "0xb2" - }, - { - "attr_name": "STATUS_LED_COLOR_OFF", - "descr": "Off", - "bits": "2:0", - "value": "0x0", - "swpld_addr": "0x33", - "swpld_addr_offset": "0xb2" - } - ] - } - }, - - "FRONT_BOARD_PSU_LED": { - "dev_info": { - "device_type": "LED", - "device_name": "LOC_LED" - }, - "dev_attr": { - "index": "0" - }, - "i2c": { - "attr_list": [{ - "attr_name": "STATUS_LED_COLOR_RED", - "descr": "Red", - "bits": "2:0", - "value": "0x2", - "swpld_addr": "0x33", - "swpld_addr_offset": "0xb3" - }, - { - "attr_name": "STATUS_LED_COLOR_RED_BLINK", - "descr": "Red Blinking", - "bits": "2:0", - "value": "0x1", - "swpld_addr": "0x33", - "swpld_addr_offset": "0xb3" - }, - { - "attr_name": "STATUS_LED_COLOR_GREEN", - "descr": "Green", - "bits": "2:0", - "value": "0x4", - "swpld_addr": "0x33", - "swpld_addr_offset": "0xb3" - }, - { - "attr_name": "STATUS_LED_COLOR_GREEN_BLINK", - "descr": "Green Blinking", - "bits": "2:0", - "value": "0x3", - "swpld_addr": "0x33", - "swpld_addr_offset": "0xb3" - }, - { - "attr_name": "STATUS_LED_COLOR_AMBER", - "descr": "Amber", - "bits": "2:0", - "value": "0x6", - "swpld_addr": "0x33", - "swpld_addr_offset": "0xb3" - }, - { - "attr_name": "STATUS_LED_COLOR_AMBER_BLINK", - "descr": "Amber Blinking", - "bits": "2:0", - "value": "0x5", - "swpld_addr": "0x33", - "swpld_addr_offset": "0xb3" - }, - { - "attr_name": "STATUS_LED_COLOR_OFF", - "descr": "Off", - "bits": "2:0", - "value": "0x0", - "swpld_addr": "0x33", - "swpld_addr_offset": "0xb3" - } - ] - } - }, - - "FRONT_BOARD_FAN_LED": { - "dev_info": { - "device_type": "LED", - "device_name": "FAN_LED" - }, - "dev_attr": { - "index": "0" - }, - "i2c": { - "attr_list": [{ - "attr_name": "STATUS_LED_COLOR_RED", - "descr": "Red", - "bits": "2:0", - "value": "0x2", - "swpld_addr": "0x33", - "swpld_addr_offset": "0xb4" - }, - { - "attr_name": "STATUS_LED_COLOR_RED_BLINK", - "descr": "Red Blinking", - "bits": "2:0", - "value": "0x1", - "swpld_addr": "0x33", - "swpld_addr_offset": "0xb4" - }, - { - "attr_name": "STATUS_LED_COLOR_GREEN", - "descr": "Green", - "bits": "2:0", - "value": "0x4", - "swpld_addr": "0x33", - "swpld_addr_offset": "0xb4" - }, - { - "attr_name": "STATUS_LED_COLOR_GREEN_BLINK", - "descr": "Green Blinking", - "bits": "2:0", - "value": "0x3", - "swpld_addr": "0x33", - "swpld_addr_offset": "0xb4" - }, - { - "attr_name": "STATUS_LED_COLOR_AMBER", - "descr": "Amber", - "bits": "2:0", - "value": "0x6", - "swpld_addr": "0x33", - "swpld_addr_offset": "0xb4" - }, - { - "attr_name": "STATUS_LED_COLOR_AMBER_BLINK", - "descr": "Amber Blinking", - "bits": "2:0", - "value": "0x5", - "swpld_addr": "0x33", - "swpld_addr_offset": "0xb4" - }, - { - "attr_name": "STATUS_LED_COLOR_OFF", - "descr": "Off", - "bits": "2:0", - "value": "0x0", - "swpld_addr": "0x33", - "swpld_addr_offset": "0xb4" - } - ] - } - }, - - "FAN1_LED": { - "dev_info": { - "device_type": "LED", - "device_name": "FANTRAY_LED" - }, - "dev_attr": { - "index": "0" - }, - "i2c": { - "attr_list": [{ - "attr_name": "STATUS_LED_COLOR_RED", - "descr": "Red", - "bits": "3:0", - "value": "0xa", - "swpld_addr": "0x32", - "swpld_addr_offset": "0x23" - }, - { - "attr_name": "STATUS_LED_COLOR_RED_BLINK", - "descr": "Red Blinking", - "bits": "3:0", - "value": "0xe", - "swpld_addr": "0x32", - "swpld_addr_offset": "0x23" - }, - { - "attr_name": "STATUS_LED_COLOR_GREEN", - "descr": "Green", - "bits": "3:0", - "value": "0x9", - "swpld_addr": "0x32", - "swpld_addr_offset": "0x23" - }, - { - "attr_name": "STATUS_LED_COLOR_GREEN_BLINK", - "descr": "Green Blinking", - "bits": "3:0", - "value": "0xd", - "swpld_addr": "0x32", - "swpld_addr_offset": "0x23" - }, - { - "attr_name": "STATUS_LED_COLOR_AMBER", - "descr": "Amber", - "bits": "3:0", - "value": "0x3", - "swpld_addr": "0x32", - "swpld_addr_offset": "0x23" - }, - { - "attr_name": "STATUS_LED_COLOR_AMBER_BLINK", - "descr": "Amber Blinking", - "bits": "3:0", - "value": "0x7", - "swpld_addr": "0x32", - "swpld_addr_offset": "0x23" - }, - { - "attr_name": "STATUS_LED_COLOR_OFF", - "descr": "Off", - "bits": "3:0", - "value": "0xb", - "swpld_addr": "0x32", - "swpld_addr_offset": "0x23" - } - ] - } - }, - - "FAN2_LED": { - "dev_info": { - "device_type": "LED", - "device_name": "FANTRAY_LED" - }, - "dev_attr": { - "index": "1" - }, - "i2c": { - "attr_list": [{ - "attr_name": "STATUS_LED_COLOR_RED", - "descr": "Red", - "bits": "3:0", - "value": "0xa", - "swpld_addr": "0x32", - "swpld_addr_offset": "0x24" - }, - { - "attr_name": "STATUS_LED_COLOR_RED_BLINK", - "descr": "Red Blinking", - "bits": "3:0", - "value": "0xe", - "swpld_addr": "0x32", - "swpld_addr_offset": "0x24" - }, - { - "attr_name": "STATUS_LED_COLOR_GREEN", - "descr": "Green", - "bits": "3:0", - "value": "0x9", - "swpld_addr": "0x32", - "swpld_addr_offset": "0x24" - }, - { - "attr_name": "STATUS_LED_COLOR_GREEN_BLINK", - "descr": "Green Blinking", - "bits": "3:0", - "value": "0xd", - "swpld_addr": "0x32", - "swpld_addr_offset": "0x24" - }, - { - "attr_name": "STATUS_LED_COLOR_AMBER", - "descr": "Amber", - "bits": "3:0", - "value": "0x3", - "swpld_addr": "0x32", - "swpld_addr_offset": "0x24" - }, - { - "attr_name": "STATUS_LED_COLOR_AMBER_BLINK", - "descr": "Amber Blinking", - "bits": "3:0", - "value": "0x7", - "swpld_addr": "0x32", - "swpld_addr_offset": "0x24" - }, - { - "attr_name": "STATUS_LED_COLOR_OFF", - "descr": "Off", - "bits": "3:0", - "value": "0xb", - "swpld_addr": "0x32", - "swpld_addr_offset": "0x24" - } - ] - } - }, - - "FAN3_LED": { - "dev_info": { - "device_type": "LED", - "device_name": "FANTRAY_LED" - }, - "dev_attr": { - "index": "2" - }, - "i2c": { - "attr_list": [{ - "attr_name": "STATUS_LED_COLOR_RED", - "descr": "Red", - "bits": "3:0", - "value": "0xa", - "swpld_addr": "0x32", - "swpld_addr_offset": "0x25" - }, - { - "attr_name": "STATUS_LED_COLOR_RED_BLINK", - "descr": "Red Blinking", - "bits": "3:0", - "value": "0xe", - "swpld_addr": "0x32", - "swpld_addr_offset": "0x25" - }, - { - "attr_name": "STATUS_LED_COLOR_GREEN", - "descr": "Green", - "bits": "3:0", - "value": "0x9", - "swpld_addr": "0x32", - "swpld_addr_offset": "0x25" - }, - { - "attr_name": "STATUS_LED_COLOR_GREEN_BLINK", - "descr": "Green Blinking", - "bits": "3:0", - "value": "0xd", - "swpld_addr": "0x32", - "swpld_addr_offset": "0x25" - }, - { - "attr_name": "STATUS_LED_COLOR_AMBER", - "descr": "Amber", - "bits": "3:0", - "value": "0x3", - "swpld_addr": "0x32", - "swpld_addr_offset": "0x25" - }, - { - "attr_name": "STATUS_LED_COLOR_AMBER_BLINK", - "descr": "Amber Blinking", - "bits": "3:0", - "value": "0x7", - "swpld_addr": "0x32", - "swpld_addr_offset": "0x25" - }, - { - "attr_name": "STATUS_LED_COLOR_OFF", - "descr": "Off", - "bits": "3:0", - "value": "0xb", - "swpld_addr": "0x32", - "swpld_addr_offset": "0x25" - } - ] - } - }, - - "FAN4_LED": { - "dev_info": { - "device_type": "LED", - "device_name": "FANTRAY_LED" - }, - "dev_attr": { - "index": "3" - }, - "i2c": { - "attr_list": [{ - "attr_name": "STATUS_LED_COLOR_RED", - "descr": "Red", - "bits": "3:0", - "value": "0xa", - "swpld_addr": "0x32", - "swpld_addr_offset": "0x26" - }, - { - "attr_name": "STATUS_LED_COLOR_RED_BLINK", - "descr": "Red Blinking", - "bits": "3:0", - "value": "0xe", - "swpld_addr": "0x32", - "swpld_addr_offset": "0x26" - }, - { - "attr_name": "STATUS_LED_COLOR_GREEN", - "descr": "Green", - "bits": "3:0", - "value": "0x9", - "swpld_addr": "0x32", - "swpld_addr_offset": "0x26" - }, - { - "attr_name": "STATUS_LED_COLOR_GREEN_BLINK", - "descr": "Green Blinking", - "bits": "3:0", - "value": "0xd", - "swpld_addr": "0x32", - "swpld_addr_offset": "0x26" - }, - { - "attr_name": "STATUS_LED_COLOR_AMBER", - "descr": "Amber", - "bits": "3:0", - "value": "0x3", - "swpld_addr": "0x32", - "swpld_addr_offset": "0x26" - }, - { - "attr_name": "STATUS_LED_COLOR_AMBER_BLINK", - "descr": "Amber Blinking", - "bits": "3:0", - "value": "0x7", - "swpld_addr": "0x32", - "swpld_addr_offset": "0x26" - }, - { - "attr_name": "STATUS_LED_COLOR_OFF", - "descr": "Off", - "bits": "3:0", - "value": "0xb", - "swpld_addr": "0x32", - "swpld_addr_offset": "0x26" - } - ] - } - } -} diff --git a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/platform.json b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/platform.json new file mode 100644 index 000000000000..6e9b40b80516 --- /dev/null +++ b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/platform.json @@ -0,0 +1,402 @@ +{ + "chassis": { + "name": "RA-B6510-48V8C", + "thermal_manager": false, + "status_led": { + "controllable": false, + "colors": ["green", "blinking_green", "amber", "blinking_amber"] + }, + "components": [ + { + "name": "CPU_CPLD" + }, + { + "name": "CONNECT_CPLD" + }, + { + "name": "CONNECT_CPLD-FAN" + }, + { + "name": "MAC_CPLD1" + }, + { + "name": "MAC_CPLD2" + }, + { + "name": "FPGA" + }, + { + "name": "BIOS" + } + ], + "fans": [ + { + "name": "Fantray1_1", + "speed": { + "controllable": true, + "minimum": 50, + "maximum": 100 + }, + "status_led": { + "available": false, + "colors": ["off", "red", "amber", "green"] + } + }, + { + "name": "Fantray1_2", + "speed": { + "controllable": true, + "minimum": 50, + "maximum": 100 + }, + "status_led": { + "available": false, + "colors": ["off", "red", "amber", "green"] + } + }, + { + "name": "Fantray2_1", + "speed": { + "controllable": true, + "minimum": 50, + "maximum": 100 + }, + "status_led": { + "available": false, + "colors": ["off", "red", "amber", "green"] + } + }, + { + "name": "Fantray2_2", + "speed": { + "controllable": true, + "minimum": 50, + "maximum": 100 + }, + "status_led": { + "available": false, + "colors": ["off", "red", "amber", "green"] + } + }, + { + "name": "Fantray3_1", + "speed": { + "controllable": true, + "minimum": 50, + "maximum": 100 + }, + "status_led": { + "available": false, + "colors": ["off", "red", "amber", "green"] + } + }, + { + "name": "Fantray3_2", + "speed": { + "controllable": true, + "minimum": 50, + "maximum": 100 + }, + "status_led": { + "available": false, + "colors": ["off", "red", "amber", "green"] + } + }, + { + "name": "Fantray4_1", + "speed": { + "controllable": true, + "minimum": 50, + "maximum": 100 + }, + "status_led": { + "available": false, + "colors": ["off", "red", "amber", "green"] + } + }, + { + "name": "Fantray4_2", + "speed": { + "controllable": true, + "minimum": 50, + "maximum": 100 + }, + "status_led": { + "available": false, + "colors": ["off", "red", "amber", "green"] + } + } + ], + "fan_drawers":[ + { + "name": "Fantray1", + "num_fans" : 2, + "status_led": { + "controllable": false, + "colors": ["amber", "green", "off"] + }, + "fans": [ + { + "name": "FanTray1_1", + "speed": { + "controllable": true, + "minimum": 50, + "maximum": 100 + }, + "status_led": { + "available": false + } + }, + { + "name": "FanTray1_2", + "speed": { + "controllable": true, + "minimum": 50, + "maximum": 100 + }, + "status_led": { + "available": false + } + } + ] + }, + { + "name": "Fantray2", + "num_fans" : 2, + "status_led": { + "controllable": false, + "colors": ["amber", "green", "off"] + }, + "fans": [ + { + "name": "FanTray2_1", + "speed": { + "controllable": true, + "minimum": 50, + "maximum": 100 + }, + "status_led": { + "available": false + } + }, + { + "name": "FanTray2_2", + "speed": { + "controllable": true, + "minimum": 50, + "maximum": 100 + }, + "status_led": { + "available": false + } + } + ] + }, + { + "name": "Fantray3", + "num_fans" : 2, + "status_led": { + "controllable": false, + "colors": ["amber", "green", "off"] + }, + "fans": [ + { + "name": "FanTray3_1", + "speed": { + "controllable": true, + "minimum": 50, + "maximum": 100 + }, + "status_led": { + "available": false + } + }, + { + "name": "FanTray3_2", + "speed": { + "controllable": true, + "minimum": 50, + "maximum": 100 + }, + "status_led": { + "available": false + } + } + ] + }, + { + "name": "Fantray4", + "num_fans" : 2, + "status_led": { + "controllable": false, + "colors": ["amber", "green", "off"] + }, + "fans": [ + { + "name": "FanTray4_1", + "speed": { + "controllable": true, + "minimum": 50, + "maximum": 100 + }, + "status_led": { + "available": false + } + }, + { + "name": "FanTray4_2", + "speed": { + "controllable": true, + "minimum": 50, + "maximum": 100 + }, + "status_led": { + "available": false + } + } + ] + } + ], + "psus": [ + { + "name": "Psu1", + "voltage": true, + "current": true, + "power": true, + "max_power": false, + "voltage_high_threshold": true, + "voltage_low_threshold": true, + "temperature": true, + "fans_target_speed": true, + "status_led": { + "controllable": false + }, + "fans": [ + { + "name": "PSU1_FAN1", + "speed": { + "controllable": true, + "minimum": 50, + "maximum": 100 + }, + "status_led": { + "available": false + } + } + ] + }, + { + "name": "Psu2", + "voltage": true, + "current": true, + "power": true, + "max_power": false, + "voltage_high_threshold": true, + "voltage_low_threshold": true, + "temperature": true, + "fans_target_speed": true, + "status_led": { + "controllable": false + }, + "fans": [ + { + "name": "PSU2_FAN1", + "speed": { + "controllable": true, + "minimum": 50, + "maximum": 100 + }, + "status_led": { + "available": false + } + } + ] + } + ], + "thermals": [ + { + "name": "ASIC_TEMP", + "controllable": false, + "low-crit-threshold": true, + "high-crit-threshold": true, + "low-threshold": true, + "high-threshold": true, + "minimum-recorded": true, + "maximum-recorded": true + }, + { + "name": "CPU_TEMP", + "controllable": false, + "low-crit-threshold": true, + "high-crit-threshold": true, + "low-threshold": true, + "high-threshold": true, + "minimum-recorded": true, + "maximum-recorded": true + }, + { + "name": "INLET_TEMP", + "controllable": false, + "low-crit-threshold": true, + "high-crit-threshold": true, + "low-threshold": true, + "high-threshold": true, + "minimum-recorded": true, + "maximum-recorded": true + }, + { + "name": "OUTLET_TEMP", + "controllable": false, + "low-crit-threshold": true, + "high-crit-threshold": true, + "low-threshold": true, + "high-threshold": true, + "minimum-recorded": true, + "maximum-recorded": true + }, + { + "name": "MAC_OUT_TEMP", + "controllable": false, + "low-crit-threshold": true, + "high-crit-threshold": true, + "low-threshold": true, + "high-threshold": true, + "minimum-recorded": true, + "maximum-recorded": true + }, + { + "name": "MAC_IN_TEMP", + "controllable": false, + "low-crit-threshold": true, + "high-crit-threshold": true, + "low-threshold": true, + "high-threshold": true, + "minimum-recorded": true, + "maximum-recorded": true + }, + { + "name": "PSU1_TEMP", + "controllable": false, + "low-crit-threshold": true, + "high-crit-threshold": true, + "low-threshold": true, + "high-threshold": true, + "minimum-recorded": true, + "maximum-recorded": true + }, + { + "name": "PSU2_TEMP", + "controllable": false, + "low-crit-threshold": true, + "high-crit-threshold": true, + "low-threshold": true, + "high-threshold": true, + "minimum-recorded": true, + "maximum-recorded": true + } + ], + "modules": [], + "sfps": [] + }, + "interfaces": {} +} diff --git a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/platform_components.json b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/platform_components.json new file mode 100644 index 000000000000..2e6f4b8d1217 --- /dev/null +++ b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/platform_components.json @@ -0,0 +1,37 @@ +{ + "chassis": { + "RA-B6510-48V8C": { + "component": { + "CPU_CPLD": { + "firmware": "/usr/share/sonic/device/x86_64-ragile_ra-b6510-48v8c-r0/latest_firmware/cpu_cpld_upgrade_header.vme", + "version": "27190516" + }, + "CONNECT_CPLD": { + "firmware": "/usr/share/sonic/device/x86_64-ragile_ra-b6510-48v8c-r0/latest_firmware/other_cpld_upgrade_header.vme", + "version": "49191230" + }, + "CONNECT_CPLD-FAN": { + "firmware": "/usr/share/sonic/device/x86_64-ragile_ra-b6510-48v8c-r0/latest_firmware/other_cpld_upgrade_header.vme", + "version": "49191230" + }, + "MAC_CPLD1": { + "firmware" : "/usr/share/sonic/device/x86_64-ragile_ra-b6510-48v8c-r0/latest_firmware/other_cpld_upgrade_header.vme", + "version" : "16190108" + }, + "MAC_CPLD2": { + "firmware" : "/usr/share/sonic/device/x86_64-ragile_ra-b6510-48v8c-r0/latest_firmware/other_cpld_upgrade_header.vme", + "version" : "17200110" + }, + "FPGA": { + "firmware": "/usr/share/sonic/device/x86_64-ragile_ra-b6510-48v8c-r0/latest_firmware/fpga_upgrade_header.bin", + "version": "7a150016" + }, + "BIOS": { + "firmware" : "/usr/share/sonic/device/x86_64-ragile_ra-b6510-48v8c-r0/latest_firmware/bios_upgrade_header.bin", + "version" : "5.11(3BARB029)" + } + } + } + } +} + diff --git a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/plugins/eeprom.py b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/plugins/eeprom.py deleted file mode 100755 index cf7215e0c9ac..000000000000 --- a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/plugins/eeprom.py +++ /dev/null @@ -1,25 +0,0 @@ -try: - import os - import sys - import json - sys.path.append('/usr/share/sonic/platform/plugins') - import pddfparse - #from sonic_eeprom import eeprom_base - from sonic_eeprom import eeprom_tlvinfo -except ImportError as e: - raise ImportError(str(e) + "- required module not found") - - -class board(eeprom_tlvinfo.TlvInfoDecoder): - _TLV_INFO_MAX_LEN = 256 - - def __init__(self, name, path, cpld_root, ro): - global pddf_obj - global plugin_data - with open(os.path.join(os.path.dirname(os.path.realpath(__file__)) + '/../pddf/pd-plugin.json')) as pd: - plugin_data = json.load(pd) - - pddf_obj = pddfparse.PddfParse() - # system EEPROM always has device name EEPROM1 - self.eeprom_path = pddf_obj.get_path("EEPROM1", "eeprom") - super(board, self).__init__(self.eeprom_path, 0, '', True) diff --git a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/plugins/fanutil.py b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/plugins/fanutil.py deleted file mode 100755 index 58c38d1d7367..000000000000 --- a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/plugins/fanutil.py +++ /dev/null @@ -1,187 +0,0 @@ -# Sample pddf_fanutil file -# All the supported FAN SysFS aattributes are -#- fan_present -#- fan_direction -#- fan_input -#- fan_pwm -#- fan_fault -# where idx is in the range [1-12] -# - - -import os.path -import sys -sys.path.append('/usr/share/sonic/platform/plugins') -import pddfparse -import json - -try: - from sonic_fan.fan_base import FanBase -except ImportError as e: - raise ImportError(str(e) + "- required module not found") - - -class FanUtil(FanBase): - """PDDF generic FAN util class""" - - def __init__(self): - FanBase.__init__(self) - global pddf_obj - global plugin_data - with open(os.path.join(os.path.dirname(os.path.realpath(__file__)) + '/../pddf/pd-plugin.json')) as pd: - plugin_data = json.load(pd) - - pddf_obj = pddfparse.PddfParse() - self.platform = pddf_obj.get_platform() - - self.num_fans = (self.platform['num_fantrays'] * self.platform['num_fans_pertray']) - - def get_num_fans(self): - return self.num_fans - - def get_presence(self, idx): - # 1 based fan index - if idx < 1 or idx > self.num_fans: - print("Invalid fan index %d\n" % idx) - return False - - attr_name = "fan" + str(idx) + "_present" - output = pddf_obj.get_attr_name_output("FAN-CTRL", attr_name) - if not output: - return False - - mode = output['mode'] - presence = output['status'].rstrip() - - vmap = plugin_data['FAN']['present'][mode]['valmap'] - - if presence in vmap: - status = vmap[presence] - else: - status = False - - return status - - def get_status(self, idx): - # 1 based fan index - if idx < 1 or idx > self.num_fans: - print("Invalid fan index %d\n" % idx) - return False - - speed = self.get_speed(idx) - status = True if (speed != 0) else False - return status - - def get_direction(self, idx): - # 1 based fan index - if idx < 1 or idx > self.num_fans: - print("Invalid fan index %d\n" % idx) - return None - - attr = "fan" + str(idx) + "_direction" - output = pddf_obj.get_attr_name_output("FAN-CTRL", attr) - if not output: - return None - - mode = output['mode'] - val = output['status'] - - val = val.rstrip() - vmap = plugin_data['FAN']['direction'][mode]['valmap'] - - if val in vmap: - direction = vmap[val] - else: - direction = val - - return direction - - def get_directions(self): - num_fan = self.get_num_fan() - - for i in range(1, num_fan+1): - attr = "fan" + str(i) + "_direction" - output = pddf_obj.get_attr_name_output("FAN-CTRL", attr) - if not output: - return None - - mode = output['mode'] - val = output['status'] - - val = val.rstrip() - vmap = plugin_data['FAN']['direction'][mode]['valmap'] - - direction = vmap[str(val)] - - print("FAN-%d direction is %s" % (i, direction)) - - return 0 - - def get_speed(self, idx): - # 1 based fan index - if idx < 1 or idx > self.num_fans: - print("Invalid fan index %d\n" % idx) - return 0 - - attr = "fan" + str(idx) + "_input" - output = pddf_obj.get_attr_name_output("FAN-CTRL", attr) - if not output: - return 0 - - #mode = output['mode'] - val = output['status'].rstrip() - - if val.isalpha(): - return 0 - else: - rpm_speed = int(float(val)) - - return rpm_speed - - def get_speeds(self): - num_fan = self.get_num_fan() - ret = "FAN_INDEX\t\tRPM\n" - - for i in range(1, num_fan+1): - attr1 = "fan" + str(i) + "_input" - output = pddf_obj.get_attr_name_output("FAN-CTRL", attr1) - if not output: - return "" - - #mode = output['mode'] - val = output['status'].rstrip() - - if val.isalpha(): - frpm = 0 - else: - frpm = int(val) - - ret += "FAN-%d\t\t\t%d\n" % (i, frpm) - - return ret - - def set_speed(self, val): - if val < 0 or val > 100: - print("Error: Invalid speed %d. Please provide a valid speed percentage" % val) - return False - - #num_fan = self.num_fans - if 'duty_cycle_to_pwm' not in plugin_data['FAN']: - print("Setting fan speed is not allowed !") - return False - else: - print("setspeed nothing to do") - return False - - #return True - - def dump_sysfs(self): - return pddf_obj.cli_dump_dsysfs('fan') - - def get_change_event(self): - """ - TODO: This function need to be implemented - when decide to support monitoring FAN(fand) - on this platform. - """ - raise NotImplementedError diff --git a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/plugins/ledutil.py b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/plugins/ledutil.py deleted file mode 100755 index 5f9e2e99dbfa..000000000000 --- a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/plugins/ledutil.py +++ /dev/null @@ -1,59 +0,0 @@ -import sys -sys.path.append('/usr/share/sonic/platform/plugins') -import pddfparse - - -class LedUtil: - color_map = { - "STATUS_LED_COLOR_GREEN": "on", - "STATUS_LED_COLOR_RED": "faulty", - "STATUS_LED_COLOR_OFF": "off" - } - - def __init__(self): - global pddf_obj - pddf_obj = pddfparse.PddfParse() - self.path = "pddf/devices/led" - self.cur_state_path = "pddf/devices/led/cur_state" - - def set_status_led(self, led_device_name, color, color_state="SOLID"): - if (not led_device_name in list(pddf_obj.data.keys())): - status = "ERROR: " + led_device_name + " is not configured" - return (status) - - if (not color in list(self.color_map.keys())): - status = "ERROR: Invalid color" - return (status) - - index = pddf_obj.data[led_device_name]['dev_attr']['index'] - pddf_obj.create_attr('device_name', led_device_name, self.path) - pddf_obj.create_attr('index', index, self.path) - pddf_obj.create_attr( - 'color', self.color_map[color], self.cur_state_path) - pddf_obj.create_attr('color_state', color_state, self.cur_state_path) - pddf_obj.create_attr('dev_ops', 'set_status', self.path) - return ("Executed") - - def get_status_led(self, led_device_name): - if (not led_device_name in list(pddf_obj.data.keys())): - status = "ERROR: " + led_device_name + " is not configured" - return (status) - - index = pddf_obj.data[led_device_name]['dev_attr']['index'] - pddf_obj.create_attr('device_name', led_device_name, self.path) - pddf_obj.create_attr('index', index, self.path) - pddf_obj.create_attr('dev_ops', 'get_status', self.path) - color_f = "/sys/kernel/" + self.cur_state_path + "/color" - color_state_f = "/sys/kernel/" + self.cur_state_path + "/color_state" - - try: - with open(color_f, 'r') as f: - color = f.read().strip("\r\n") - with open(color_state_f, 'r') as f: - color_state = f.read().strip("\r\n") - except IOError: - status = "ERROR :" + color_f + " open failed" - return (status) - status = "%s-%s:\t%s %s\n" % (led_device_name, - index, color, color_state) - return (status) diff --git a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/plugins/psuutil.py b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/plugins/psuutil.py deleted file mode 100755 index dccb1ac1a155..000000000000 --- a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/plugins/psuutil.py +++ /dev/null @@ -1,270 +0,0 @@ -# -# Sample pddf_psuutil file -# -# All the supported PSU SysFS aattributes are -#- psu_present -#- psu_model_name -#- psu_power_good -#- psu_mfr_id -#- psu_serial_num -#- psu_fan_dir -#- psu_v_out -#- psu_i_out -#- psu_p_out -#- psu_fan1_speed_rpm -# - -import os.path -import sys -sys.path.append('/usr/share/sonic/platform/plugins') -import pddfparse -import json - -try: - from sonic_psu.psu_base import PsuBase -except ImportError as e: - raise ImportError(str(e) + "- required module not found") - - -class PsuUtil(PsuBase): - """PDDF generic PSU util class""" - - def __init__(self): - PsuBase.__init__(self) - global pddf_obj - global plugin_data - with open(os.path.join(os.path.dirname(os.path.realpath(__file__)) + '/../pddf/pd-plugin.json')) as pd: - plugin_data = json.load(pd) - - pddf_obj = pddfparse.PddfParse() - self.platform = pddf_obj.get_platform() - - def get_num_psus(self): - return int(self.platform['num_psus']) - - def get_psu_status(self, index): - if index is None: - return False - - device = "PSU" + "%d" % index - output = pddf_obj.get_attr_name_output(device, "psu_power_good") - if not output: - return False - - mode = output['mode'] - val = output['status'] - - val = val.rstrip() - vmap = plugin_data['PSU']['psu_power_good'][mode]['valmap'] - - if val in vmap: - return vmap[val] - else: - return False - - def get_psu_presence(self, index): - if index is None: - return False - - status = 0 - device = "PSU" + "%d" % index - output = pddf_obj.get_attr_name_output(device, "psu_present") - if not output: - return False - - mode = output['mode'] - status = output['status'] - - vmap = plugin_data['PSU']['psu_present'][mode]['valmap'] - - if status.rstrip('\n') in vmap: - return vmap[status.rstrip('\n')] - else: - return False - - def get_powergood_status(self, idx): - if idx is None: - return False - - if idx < 1 or idx > self.platform['num_psus']: - print("Invalid index %d\n" % idx) - return False - - device = "PSU"+"%d" % (idx) - output = pddf_obj.get_attr_name_output(device, "psu_power_good") - if not output: - return False - - mode = output['mode'] - status = output['status'] - - vmap = plugin_data['PSU']['psu_power_good'][mode]['valmap'] - - if status.rstrip('\n') in vmap: - return vmap[status.rstrip('\n')] - else: - return False - - def get_model(self, idx): - if idx is None: - return None - - if idx < 1 or idx > self.platform['num_psus']: - print("Invalid index %d\n" % idx) - return None - - device = "PSU"+"%d" % (idx) - output = pddf_obj.get_attr_name_output(device, "psu_model_name") - if not output: - return None - - model = output['status'] - - # strip_non_ascii - stripped = (c for c in model if 0 < ord(c) < 127) - model = ''.join(stripped) - - return model.rstrip('\n') - - def get_mfr_id(self, idx): - if idx is None: - return None - - if idx < 1 or idx > self.platform['num_psus']: - print("Invalid index %d\n" % idx) - return None - - device = "PSU"+"%d" % (idx) - output = pddf_obj.get_attr_name_output(device, "psu_mfr_id") - if not output: - return None - - mfr = output['status'] - - return mfr.rstrip('\n') - - def get_serial(self, idx): - if idx is None: - return None - - if idx < 1 or idx > self.platform['num_psus']: - print("Invalid index %d\n" % idx) - return None - - device = "PSU"+"%d" % (idx) - output = pddf_obj.get_attr_name_output(device, "psu_serial_num") - if not output: - return None - - serial = output['status'] - - return serial.rstrip('\n') - - def get_direction(self, idx): - if idx is None: - return None - - if idx < 1 or idx > self.platform['num_psus']: - print("Invalid index %d\n" % idx) - return None - - device = "PSU"+"%d" % (idx) - output = pddf_obj.get_attr_name_output(device, "psu_fan_dir") - if not output: - return None - - mode = output['mode'] - direction = output['status'].rstrip('\n') - - vmap = plugin_data['PSU']['psu_fan_dir'][mode]['valmap'] - if direction in vmap: - airflow_dir_real = vmap[direction] - else: - airflow_dir_real = direction - - return airflow_dir_real - - def get_output_voltage(self, idx): - if idx is None: - return 0.0 - - if idx < 1 or idx > self.platform['num_psus']: - print("Invalid index %d\n" % idx) - return 0.0 - - device = "PSU"+"%d" % (idx) - output = pddf_obj.get_attr_name_output(device, "psu_v_out") - if not output: - return 0.0 - - v_out = output['status'] - - # value returned by the psu driver is in mV - return float(v_out)/1000 - - def get_output_current(self, idx): - if idx is None: - return 0.0 - - if idx < 1 or idx > self.platform['num_psus']: - print("Invalid index %d\n" % idx) - return 0.0 - - device = "PSU"+"%d" % (idx) - output = pddf_obj.get_attr_name_output(device, "psu_i_out") - if not output: - return 0.0 - - i_out = output['status'] - - # current in mA - return float(i_out)/1000 - - def get_output_power(self, idx): - if idx is None: - return 0.0 - - if idx < 1 or idx > self.platform['num_psus']: - print("Invalid index %d\n" % idx) - return 0.0 - - device = "PSU"+"%d" % (idx) - output = pddf_obj.get_attr_name_output(device, "psu_p_out") - if not output: - return 0.0 - - p_out = output['status'] - - # power is returned in micro watts - return float(p_out)/1000000 - - def get_fan_rpm(self, idx, fan_idx): - if idx is None or fan_idx is None: - return 0 - - if idx < 1 or idx > self.platform['num_psus']: - print("Invalid index %d\n" % idx) - return 0 - - device = "PSU"+"%d" % (idx) - num_fans = pddf_obj.get_num_psu_fans(device) - - if fan_idx < 1 or fan_idx > num_fans: - print("Invalid PSU-fan index %d\n" % fan_idx) - return 0 - - output = pddf_obj.get_attr_name_output(device, "psu_fan"+str(fan_idx)+"_speed_rpm") - if not output: - return 0 - - #mode = output['mode'] - output['status'] = output['status'].rstrip() - if output['status'].isalpha(): - return 0 - else: - speed = int(output['status']) - - return speed - - def dump_sysfs(self): - return pddf_obj.cli_dump_dsysfs('psu') diff --git a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/plugins/sfputil.py b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/plugins/sfputil.py old mode 100755 new mode 100644 index 1ca925610822..3e195a36f6cb --- a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/plugins/sfputil.py +++ b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/plugins/sfputil.py @@ -1,236 +1,243 @@ -import os.path -import sys -sys.path.append('/usr/share/sonic/platform/plugins') -import pddfparse -import json +# sfputil.py +# +# Platform-specific SFP transceiver interface for SONiC +# try: import time - from ctypes import create_string_buffer + import os + import traceback from sonic_sfp.sfputilbase import SfpUtilBase except ImportError as e: - raise ImportError(str(e) + "- required module not found") - + raise ImportError("%s - required module not found" % str(e)) class SfpUtil(SfpUtilBase): - """Platform generic PDDF SfpUtil class""" + """Platform-specific SfpUtil class""" + + PORT_START = 1 + PORT_END = 56 + PORTS_IN_BLOCK = 57 + + EEPROM_OFFSET = 32 + SFP_DEVICE_TYPE = "optoe2" + QSFP_DEVICE_TYPE = "optoe1" + I2C_MAX_ATTEMPT = 3 _port_to_eeprom_mapping = {} - _port_start = 0 - _port_end = 0 - _port_to_type_mapping = {} - _qsfp_ports = [] - _sfp_ports = [] + port_to_i2cbus_mapping ={} + + @property + def port_start(self): + return self.PORT_START + + @property + def port_end(self): + return self.PORT_END + + @property + def qsfp_ports(self): + return range(49, self.PORTS_IN_BLOCK) + + @property + def port_to_eeprom_mapping(self): + return self._port_to_eeprom_mapping def __init__(self): + for x in range(self.PORT_START, self.PORTS_IN_BLOCK): + self.port_to_i2cbus_mapping[x] = x + self.EEPROM_OFFSET - 1 SfpUtilBase.__init__(self) - global pddf_obj - global plugin_data - with open(os.path.join(os.path.dirname(os.path.realpath(__file__)) + '/../pddf/pd-plugin.json')) as pd: - plugin_data = json.load(pd) - - pddf_obj = pddfparse.PddfParse() - self.platform = pddf_obj.get_platform() - self._port_start = 0 - self._port_end = self.get_num_ports() - - for port_num in range(self._port_start, self._port_end): - device = "PORT" + "%d" % (port_num+1) - port_eeprom_path = pddf_obj.get_path(device, "eeprom") - self._port_to_eeprom_mapping[port_num] = port_eeprom_path - port_type = pddf_obj.get_device_type(device) - self._port_to_type_mapping[port_num] = port_type - self.populate_port_type(port_num) - - def get_num_ports(self): - return int(self.platform['num_ports']) - - def is_valid_port(self, port_num): - if port_num < self._port_start or port_num > self._port_end: + + def _sfp_read_file_path(self, file_path, offset, num_bytes): + attempts = 0 + while attempts < self.I2C_MAX_ATTEMPT: + try: + file_path.seek(offset) + read_buf = file_path.read(num_bytes) + except Exception: + attempts += 1 + time.sleep(0.05) + return True, read_buf + return False, None + + def _sfp_eeprom_present(self, sysfs_sfp_i2c_client_eeprompath, offset): + """Tries to read the eeprom file to determine if the + device/sfp is present or not. If sfp present, the read returns + valid bytes. If not, read returns error 'Connection timed out""" + + if not os.path.exists(sysfs_sfp_i2c_client_eeprompath): return False + with open(sysfs_sfp_i2c_client_eeprompath, "rb", buffering=0) as sysfsfile: + rv, buf = self._sfp_read_file_path(sysfsfile, offset, 1) + return rv + + def _add_new_sfp_device(self, sysfs_sfp_i2c_adapter_path, devaddr, devtype): + try: + sysfs_nd_path = "%s/new_device" % sysfs_sfp_i2c_adapter_path + + # Write device address to new_device file + nd_str = "%s %s" % (devtype, hex(devaddr)) + with open(sysfs_nd_path, "w") as nd_file: + nd_file.write(nd_str) + + except Exception as err: + print("Error writing to new device file: %s" % str(err)) + return 1 else: - return True + return 0 - def get_presence(self, port_num): - if port_num < self._port_start or port_num > self._port_end: - return False + def _get_port_eeprom_path(self, port_num, devid): + sysfs_i2c_adapter_base_path = "" - device = "PORT" + "%d" % (port_num+1) - output = pddf_obj.get_attr_name_output(device, 'xcvr_present') - if not output: - return False + if port_num in self.port_to_eeprom_mapping: + sysfs_sfp_i2c_client_eeprom_path = self.port_to_eeprom_mapping[port_num] + else: + sysfs_i2c_adapter_base_path = "/sys/class/i2c-adapter" + + i2c_adapter_id = self._get_port_i2c_adapter_id(port_num) + if i2c_adapter_id is None: + print("Error getting i2c bus num") + return None + + # Get i2c virtual bus path for the sfp + sysfs_sfp_i2c_adapter_path = "%s/i2c-%s" % (sysfs_i2c_adapter_base_path, + str(i2c_adapter_id)) + + # If i2c bus for port does not exist + if not os.path.exists(sysfs_sfp_i2c_adapter_path): + print("Could not find i2c bus %s. Driver not loaded?" % sysfs_sfp_i2c_adapter_path) + return None + + sysfs_sfp_i2c_client_path = "%s/%s-00%s" % (sysfs_sfp_i2c_adapter_path, + str(i2c_adapter_id), + hex(devid)[-2:]) + + # If sfp device is not present on bus, Add it + if not os.path.exists(sysfs_sfp_i2c_client_path): + if port_num in self.qsfp_ports: + ret = self._add_new_sfp_device( + sysfs_sfp_i2c_adapter_path, devid, self.QSFP_DEVICE_TYPE) + else: + ret = self._add_new_sfp_device( + sysfs_sfp_i2c_adapter_path, devid, self.SFP_DEVICE_TYPE) + if ret != 0: + print("Error adding sfp device") + return None - #mode = output['mode'] - modpres = output['status'].rstrip() - if 'XCVR' in plugin_data: - if 'xcvr_present' in plugin_data['XCVR']: - ptype = self._port_to_type_mapping[port_num] - vtype = 'valmap-'+ptype - if vtype in plugin_data['XCVR']['xcvr_present']: - vmap = plugin_data['XCVR']['xcvr_present'][vtype] - if modpres in vmap: - return vmap[modpres] - else: - return False - # if plugin_data doesn't specify anything regarding Transceivers - if modpres == '1': - return True + sysfs_sfp_i2c_client_eeprom_path = "%s/eeprom" % sysfs_sfp_i2c_client_path - return False + return sysfs_sfp_i2c_client_eeprom_path - def populate_port_type(self, port): - if self._port_to_type_mapping[port] == 'QSFP' or self._port_to_type_mapping[port] == 'QSFP28': - self._qsfp_ports.append(port) - elif self._port_to_type_mapping[port] == 'SFP' or self._port_to_type_mapping[port] == 'SFP28': - self._sfp_ports.append(port) + def _read_eeprom_specific_bytes(self, sysfsfile_eeprom, offset, num_bytes): + eeprom_raw = [] + for i in range(0, num_bytes): + eeprom_raw.append("0x00") - @property - def port_start(self): - return self._port_start + rv, raw = self._sfp_read_file_path(sysfsfile_eeprom, offset, num_bytes) + if rv is False: + return None - @property - def port_end(self): - return (self._port_end - 1) + try: + for n in range(0, num_bytes): + eeprom_raw[n] = hex(raw[n])[2:].zfill(2) + except Exception: + return None - @property - def port_to_eeprom_mapping(self): - return self._port_to_eeprom_mapping + return eeprom_raw - @property - def qsfp_ports(self): - return self._qsfp_ports + def get_eeprom_dom_raw(self, port_num): + if port_num in self.qsfp_ports: + # QSFP DOM EEPROM is also at addr 0x50 and thus also stored in eeprom_ifraw + return None + # Read dom eeprom at addr 0x51 + return self._read_eeprom_devid(port_num, self.IDENTITY_EEPROM_ADDR, 256) - def reset(self, port_num): - if port_num < self._port_start or port_num > self._port_end: + def get_presence(self, port_num): + # Check for invalid port_num + if port_num < self.port_start or port_num > self.port_end: return False - device = "PORT" + "%d" % (port_num+1) - port_ps = pddf_obj.get_path(device, "xcvr_reset") - if port_ps is None: - return False + presence_path = "/sys/wb_plat/sff/sff%d/present" % port_num try: - reg_file = open(port_ps, 'w') - except IOError as e: - print("Error: unable to open file: %s" % str(e)) + with open(presence_path, "rb") as data: + presence_data = data.read(2) + if presence_data == "": + return False + result = int(presence_data, 16) + except IOError: return False - try: - reg_file.seek(0) - reg_file.write('1') - time.sleep(1) - reg_file.seek(0) - reg_file.write('0') - reg_file.close() + if result == 1: return True - except IOError as e: - return False + return False def get_low_power_mode(self, port_num): # Check for invalid port_num - if port_num < self._port_start or port_num > self._port_end: - return False - if not self.get_presence(port_num): + return True + + def set_low_power_mode(self, port_num, lpmode): + # Check for invalid port_num + + return True + + def reset(self, port_num): + # Check for invalid port_num + if port_num < self.port_start or port_num > self.port_end: return False - device = "PORT" + "%d" % (port_num+1) - output = pddf_obj.get_attr_name_output(device, 'xcvr_lpmode') - if not output: - if port_num not in self.qsfp_ports: - return False # Read from eeprom only for QSFP ports - try: - eeprom = None - eeprom = open(self.port_to_eeprom_mapping[port_num], "rb") - # check for valid connector type - eeprom.seek(2) - ctype = eeprom.read(1) - if ctype in ['21', '23']: - return False + return True - eeprom.seek(93) - lpmode = ord(eeprom.read(1)) + def get_transceiver_change_event(self, timeout=0): + return False, {} - if ((lpmode & 0x3) == 0x3): - return True # Low Power Mode if "Power override" bit is 1 and "Power set" bit is 1 - else: - # High Power Mode if one of the following conditions is matched: - # 1. "Power override" bit is 0 - # 2. "Power override" bit is 1 and "Power set" bit is 0 - return False - except IOError as e: - print("Error: unable to open file: %s" % str(e)) - return False - finally: - if eeprom is not None: - eeprom.close() - time.sleep(0.01) - else: - #mode = output['mode'] - status = int(output['status'].rstrip()) + def get_highest_temperature(self): + offset = 0 + hightest_temperature = -9999 - if status == 1: - return True - else: - return False + presence_flag = False + read_eeprom_flag = False + temperature_valid_flag = False - def set_low_power_mode(self, port_num, lpmode): - # Check for invalid port_num - if port_num < self._port_start or port_num > self._port_end: - return False + for port in range(49, self.PORTS_IN_BLOCK): + if self.get_presence(port) is False: + continue - if not self.get_presence(port_num): - return False # Port is not present, unable to set the eeprom + presence_flag = True - device = "PORT" + "%d" % (port_num+1) - port_ps = pddf_obj.get_path(device, "xcvr_lpmode") - if port_ps is None: - if port_num not in self.qsfp_ports: - return False # Write to eeprom only for QSFP ports - try: - eeprom = None - eeprom = open(self.port_to_eeprom_mapping[port_num], "r+b") - # check for valid connector type - eeprom.seek(2) - ctype = eeprom.read(1) - if ctype in ['21', '23']: - return False + if port in self.qsfp_ports: + offset = 22 + else: + offset = 96 - # Fill in write buffer - regval = 0x3 if lpmode else 0x1 # 0x3:Low Power Mode, 0x1:High Power Mode - buffer = create_string_buffer(1) - buffer[0] = chr(regval) - - # Write to eeprom - eeprom.seek(93) - eeprom.write(buffer[0]) - return True - except IOError as e: - print("Error: unable to open file: %s" % str(e)) - return False - finally: - if eeprom is not None: - eeprom.close() - time.sleep(0.01) - else: + eeprom_path = self._get_port_eeprom_path(port, 0x50) try: - f = open(port_ps, 'w') - if lpmode: - f.write('1') - else: - f.write('0') - f.close() - return True - except IOError as e: - return False - - def get_transceiver_change_event(self): - """ - TODO: This function need to be implemented - when decide to support monitoring SFP(Xcvrd) - on this platform. - """ - raise NotImplementedError - - def dump_sysfs(self): - return pddf_obj.cli_dump_dsysfs('xcvr') + with open(eeprom_path, mode="rb", buffering=0) as eeprom: + read_eeprom_flag = True + eeprom_raw = self._read_eeprom_specific_bytes(eeprom, offset, 2) + msb = int(eeprom_raw[0], 16) + lsb = int(eeprom_raw[1], 16) + + result = (msb << 8) | (lsb & 0xff) + result = float(result / 256.0) + if -50 <= result <= 200: + temperature_valid_flag = True + hightest_temperature = max(hightest_temperature, result) + except Exception: + print(traceback.format_exc()) + + # all port not presence + if presence_flag is False: + hightest_temperature = -10000 + + # all port read eeprom fail + elif read_eeprom_flag is False: + hightest_temperature = -9999 + + # all port temperature invalid + elif read_eeprom_flag is True and temperature_valid_flag is False: + hightest_temperature = -10000 + + hightest_temperature = round(hightest_temperature, 2) + + return hightest_temperature diff --git a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/plugins/ssd_util.py b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/plugins/ssd_util.py new file mode 100755 index 000000000000..89d3ccd770bd --- /dev/null +++ b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/plugins/ssd_util.py @@ -0,0 +1,311 @@ +# +# ssd_util.py +# +# Generic implementation of the SSD health API +# SSD models supported: +# - InnoDisk +# - StorFly +# - Virtium + +try: + import re + import os + import subprocess + from sonic_platform_base.sonic_ssd.ssd_base import SsdBase +except ImportError as e: + raise ImportError (str(e) + "- required module not found") + +SMARTCTL = "smartctl {} -a" +INNODISK = "iSmart -d {}" +VIRTIUM = "SmartCmd -m {}" +DISK_LIST_CMD = "fdisk -l -o Device" +DISK_FREE_CMD = "df -h" +MOUNT_CMD = "mount" + +NOT_AVAILABLE = "N/A" +PE_CYCLE = 3000 +FAIL_PERCENT = 95 + +# Set Vendor Specific IDs +INNODISK_HEALTH_ID = 169 +INNODISK_TEMPERATURE_ID = 194 + +class SsdUtil(SsdBase): + """ + Generic implementation of the SSD health API + """ + model = NOT_AVAILABLE + serial = NOT_AVAILABLE + firmware = NOT_AVAILABLE + temperature = NOT_AVAILABLE + health = NOT_AVAILABLE + remaining_life = NOT_AVAILABLE + sata_rate = NOT_AVAILABLE + ssd_info = NOT_AVAILABLE + vendor_ssd_info = NOT_AVAILABLE + + def __init__(self, diskdev): + self.vendor_ssd_utility = { + "Generic" : { "utility" : SMARTCTL, "parser" : self.parse_generic_ssd_info }, + "InnoDisk" : { "utility" : INNODISK, "parser" : self.parse_innodisk_info }, + "M.2" : { "utility" : INNODISK, "parser" : self.parse_innodisk_info }, + "StorFly" : { "utility" : VIRTIUM, "parser" : self.parse_virtium_info }, + "Virtium" : { "utility" : VIRTIUM, "parser" : self.parse_virtium_info } + } + + """ + The dict model_attr keys relate the vendors + LITEON : "ER2-GD","AF2MA31DTDLT" + Intel : "SSDSCKKB" + SMI : "SM619GXC" + samsung: "MZNLH" + ADATA : "IM2S3134N" + """ + self.model_attr = { + "ER2-GD" : { "temperature" : "\n190\s+(.+?)\n", "remainingLife" : "\n202\s+(.+?)\n" }, + "AF2MA31DTDLT" : { "temperature" : "\n194\s+(.+?)\n", "remainingLife" : "\n202\s+(.+?)\n" }, + "SSDSCK" : { "temperature" : "\n194\s+(.+?)\n", "remainingLife" : "\n233\s+(.+?)\n" }, + "SM619GXC" : { "temperature" : "\n194\s+(.+?)\n", "remainingLife" : "\n169\s+(.+?)\n" }, + "MZNLH" : { "temperature" : "\n190\s+(.+?)\n", "remainingLife" : "\n245\s+(.+?)\n" }, + "IM2S3134N" : { "temperature" : "\n194\s+(.+?)\n", "remainingLife" : "\n231\s+(.+?)\n" } + } + + self.key_list = list(self.model_attr.keys()) + self.attr_info_rule = "[\s\S]*SMART Attributes Data Structure revision number: 1|SMART Error Log Version[\s\S]*" + self.dev = diskdev + # Generic part + self.fetch_generic_ssd_info(diskdev) + self.parse_generic_ssd_info() + self.fetch_vendor_ssd_info(diskdev, "Generic") + + # Known vendor part + if self.model: + model_short = self.model.split()[0] + if model_short in self.vendor_ssd_utility: + self.fetch_vendor_ssd_info(diskdev, model_short) + self.parse_vendor_ssd_info(model_short) + else: + # No handler registered for this disk model + pass + else: + # Failed to get disk model + self.model = "Unknown" + + def _execute_shell(self, cmd): + process = subprocess.Popen(cmd.split(), universal_newlines=True, stdout=subprocess.PIPE) + output, error = process.communicate() + exit_code = process.returncode + if exit_code: + return None + return output + + def _parse_re(self, pattern, buffer): + res_list = re.findall(pattern, str(buffer)) + return res_list[0] if res_list else NOT_AVAILABLE + + def fetch_generic_ssd_info(self, diskdev): + self.ssd_info = self._execute_shell(self.vendor_ssd_utility["Generic"]["utility"].format(diskdev)) + + # Health and temperature values may be overwritten with vendor specific data + def parse_generic_ssd_info(self): + if "nvme" in self.dev: + self.model = self._parse_re('Model Number:\s*(.+?)\n', self.ssd_info) + + health_raw = self._parse_re('Percentage Used\s*(.+?)\n', self.ssd_info) + if health_raw == NOT_AVAILABLE: + self.health = NOT_AVAILABLE + else: + health_raw = health_raw.split()[-1] + self.health = 100 - float(health_raw.strip('%')) + + temp_raw = self._parse_re('Temperature\s*(.+?)\n', self.ssd_info) + if temp_raw == NOT_AVAILABLE: + self.temperature = NOT_AVAILABLE + else: + temp_raw = temp_raw.split()[-2] + self.temperature = float(temp_raw) + else: + self.model = self._parse_re('Device Model:\s*(.+?)\n', self.ssd_info) + model_key = "" + for key in self.key_list: + if re.search(key, self.model): + model_key = key + break + if model_key != "": + self.remaining_life = self._parse_re(self.model_attr[model_key]["remainingLife"], re.sub(self.attr_info_rule,"",self.ssd_info)).split()[2] + self.temperature = self._parse_re(self.model_attr[model_key]["temperature"], re.sub(self.attr_info_rule,"",self.ssd_info)).split()[8] + self.health = self.remaining_life + # Get the LITEON ssd health value by (PE CYCLE - AVG ERASE CYCLE )/(PE CYCLE) + if model_key in ["ER2-GD", "AF2MA31DTDLT"]: + avg_erase = int(self._parse_re('\n173\s+(.+?)\n' ,re.sub(self.attr_info_rule,"",self.ssd_info)).split()[-1]) + self.health = int(round((PE_CYCLE - avg_erase)/PE_CYCLE*100,0)) + if self.remaining_life != NOT_AVAILABLE and int(self.remaining_life) < FAIL_PERCENT: + self.remaining_life = "Fail" + self.sata_rate = self._parse_re('SATA Version is:.*current: (.+?)\)\n', self.ssd_info) + self.serial = self._parse_re('Serial Number:\s*(.+?)\n', self.ssd_info) + self.firmware = self._parse_re('Firmware Version:\s*(.+?)\n', self.ssd_info) + + def parse_innodisk_info(self): + if self.vendor_ssd_info: + self.health = self._parse_re('Health:\s*(.+?)%', self.vendor_ssd_info) + self.temperature = self._parse_re('Temperature\s*\[\s*(.+?)\]', self.vendor_ssd_info) + else: + if self.health == NOT_AVAILABLE: + health_raw = self.parse_id_number(INNODISK_HEALTH_ID) + self.health = health_raw.split()[-1] + if self.temperature == NOT_AVAILABLE: + temp_raw = self.parse_id_number(INNODISK_TEMPERATURE_ID) + self.temperature = temp_raw.split()[-6] + + def parse_virtium_info(self): + if self.vendor_ssd_info: + self.temperature = self._parse_re('Temperature_Celsius\s*\d*\s*(\d+?)\s+', self.vendor_ssd_info) + nand_endurance = self._parse_re('NAND_Endurance\s*\d*\s*(\d+?)\s+', self.vendor_ssd_info) + avg_erase_count = self._parse_re('Average_Erase_Count\s*\d*\s*(\d+?)\s+', self.vendor_ssd_info) + try: + self.health = 100 - (float(avg_erase_count) * 100 / float(nand_endurance)) + except (ValueError, ZeroDivisionError): + # Invalid avg_erase_count or nand_endurance. + pass + + def fetch_vendor_ssd_info(self, diskdev, model): + self.vendor_ssd_info = self._execute_shell(self.vendor_ssd_utility[model]["utility"].format(diskdev)) + + def parse_vendor_ssd_info(self, model): + self.vendor_ssd_utility[model]["parser"]() + + def check_readonly2(self, partition, filesystem): + # parse mount cmd output info + mount_info = self._execute_shell(MOUNT_CMD) + for line in mount_info.split('\n'): + column_list = line.split() + if line == '': + continue + if column_list[0] == partition and column_list[2] == filesystem: + if column_list[5].split(',')[0][1:] == "ro": + return partition + else: + return NOT_AVAILABLE + return NOT_AVAILABLE + + def check_readonly(self, partition, filesystem): + ret = os.access(filesystem, os.W_OK) + if ret == False: + return partition + else: + return NOT_AVAILABLE + + def get_health(self): + """ + Retrieves current disk health in percentages + + Returns: + A float number of current ssd health + e.g. 83.5 + """ + return float(self.health) + + def get_temperature(self): + """ + Retrieves current disk temperature in Celsius + + Returns: + A float number of current temperature in Celsius + e.g. 40.1 + """ + return float(self.temperature) + + def get_model(self): + """ + Retrieves model for the given disk device + + Returns: + A string holding disk model as provided by the manufacturer + """ + return self.model + + def get_firmware(self): + """ + Retrieves firmware version for the given disk device + + Returns: + A string holding disk firmware version as provided by the manufacturer + """ + return self.firmware + + def get_serial(self): + """ + Retrieves serial number for the given disk device + + Returns: + A string holding disk serial number as provided by the manufacturer + """ + return self.serial + def get_sata_rate(self): + """ + Retrieves SATA rate for the given disk device + Returns: + A string holding current SATA rate as provided by the manufacturer + """ + return self.sata_rate + def get_remaining_life(self): + """ + Retrieves remaining life for the given disk device + Returns: + A string holding disk remaining life as provided by the manufacturer + """ + return self.remaining_life + def get_vendor_output(self): + """ + Retrieves vendor specific data for the given disk device + + Returns: + A string holding some vendor specific disk information + """ + return self.vendor_ssd_info + + def parse_id_number(self, id): + return self._parse_re('{}\s*(.+?)\n'.format(id), self.ssd_info) + + def get_readonly_partition(self): + """ + Check the partition mount filesystem is readonly status,then output the result. + Returns: + The readonly partition list + """ + + ro_partition_list = [] + partition_list = [] + + # parse fdisk cmd output info + disk_info = self._execute_shell(DISK_LIST_CMD) + begin_flag = False + for line in disk_info.split('\n'): + if line == "Device": + begin_flag = True + continue + if begin_flag: + if line != "": + partition_list.append(line) + else: + break + + # parse df cmd output info + disk_free = self._execute_shell(DISK_FREE_CMD) + disk_dict = {} + line_num = 0 + for line in disk_free.split('\n'): + line_num = line_num + 1 + if line_num == 1 or line == "": + continue + column_list = line.split() + disk_dict[column_list[0]] = column_list[5] + + # get partition which is readonly + for partition in partition_list: + if partition in disk_dict: + ret = self.check_readonly(partition, disk_dict[partition]) + if (ret != NOT_AVAILABLE): + ro_partition_list.append(ret) + + return ro_partition_list diff --git a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/plugins/sysstatutil.py b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/plugins/sysstatutil.py deleted file mode 100755 index af4dd5915361..000000000000 --- a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/plugins/sysstatutil.py +++ /dev/null @@ -1,82 +0,0 @@ -import os.path -import sys -sys.path.append('/usr/share/sonic/platform/plugins') -import pddfparse -import json - - -class SYSStatusUtil(): - """Platform-specific SYSStatus class""" - - def __init__(self): - global pddf_obj - global plugin_data - with open(os.path.join(os.path.dirname(os.path.realpath(__file__)) + '/../pddf/pd-plugin.json')) as pd: - plugin_data = json.load(pd) - - pddf_obj = pddfparse.PddfParse() - - def get_board_info(self): - device = "SYSSTATUS" - node = pddf_obj.get_path(device, "board_info") - if node is None: - return False - try: - with open(node, 'r') as f: - status = f.read() - print("board_info : %s" % status) - except IOError: - return False - - def get_cpld_versio(self): - device = "SYSSTATUS" - node = pddf_obj.get_path(device, "cpld1_version") - if node is None: - return False - try: - with open(node, 'r') as f: - status = f.read() - print("cpld1_version : %s" % status) - except IOError: - return False - - def get_power_module_status(self): - device = "SYSSTATUS" - node = pddf_obj.get_path(device, "power_module_status") - if node is None: - return False - try: - with open(node, 'r') as f: - status = f.read() - print("power_module_status : %s" % status) - except IOError: - return False - - def get_system_reset_status(self): - device = "SYSSTATUS" - for i in range(1, 8): - node = pddf_obj.get_path(device, "system_reset"+str(i)) - if node is None: - return False - try: - with open(node, 'r') as f: - status = f.read() - print("system_reset%s : %s" % (i, status)) - except IOError: - print("system_reset%s not supported" % i) - - def get_misc_status(self): - device = "SYSSTATUS" - for i in range(1, 3): - node = pddf_obj.get_path(device, "misc"+str(i)) - if node is None: - return False - try: - with open(node, 'r') as f: - status = f.read() - print("misc%s : %s" % (i, status)) - except IOError: - print("system_reset%s not supported" % i) - - def dump_sysfs(self): - return pddf_obj.cli_dump_dsysfs('sys-status') diff --git a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/plugins/thermalutil.py b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/plugins/thermalutil.py deleted file mode 100755 index 6aef47b7e924..000000000000 --- a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/plugins/thermalutil.py +++ /dev/null @@ -1,75 +0,0 @@ -import os.path -import sys -import json -sys.path.append('/usr/share/sonic/platform/plugins') -import pddfparse - - -class ThermalUtil: - def __init__(self): - global pddf_obj - global plugin_data - with open(os.path.join(os.path.dirname(os.path.realpath(__file__)) + '/../pddf/pd-plugin.json')) as pd: - plugin_data = json.load(pd) - - pddf_obj = pddfparse.PddfParse() - self.platform = pddf_obj.get_platform() - self.num_thermals = self.platform['num_temps'] - self.info = [] - - def get_num_thermals(self): - return (self.num_thermals) - - def get_thermal_info(self): - list = [] - pddf_obj.get_device_list(list, "TEMP_SENSOR") - list.sort() - for dev in list: - data = {} - device_name = dev['dev_info']['device_name'] - topo_info = dev['i2c']['topo_info'] - label = "%s-i2c-%d-%x" % (topo_info['dev_type'], - int(topo_info['parent_bus'], 0), int(topo_info['dev_addr'], 0)) - attr_list = dev['i2c']['attr_list'] - data['device_name'] = device_name - data['label'] = label - for attr in attr_list: - attr_name = attr['attr_name'] - node = pddf_obj.get_path(device_name, attr_name) - if node is None: - return False - try: - with open(node, 'r') as f: - attr_value = int(f.read()) - except IOError: - return False - data[attr_name] = attr_value/float(1000) - self.info.append(data) - - def show_thermal_temp_values(self, idx): - if idx < 1 or idx > self.num_thermals: - print("Invalid temperature sensor idx %d" % idx) - return None - self.get_thermal_info() - thermal_name = "TEMP"+"%d" % idx - label = "" - value = "" - for temp in self.info: - if thermal_name == temp['device_name']: - label = temp['label'] - value = "temp1\t %+.1f C (high = %+.1f C, hyst = %+.1f C)" % ( - temp['temp1_input'], temp['temp1_max'], temp['temp1_max_hyst']) - else: - continue - - return (label, value) - - def show_temp_values(self): - self.get_thermal_info() - for temp in self.info: - print(temp['label']) - print("temp1\t %+.1f C (high = %+.1f C, hyst = %+.1f C)" % - (temp['temp1_input'], temp['temp1_max'], temp['temp1_max_hyst'])) - - def dump_sysfs(self): - return pddf_obj.cli_dump_dsysfs('temp-sensors') diff --git a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/pmon_daemon_control.json b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/pmon_daemon_control.json index 50c21289d260..94592fa8cebc 100644 --- a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/pmon_daemon_control.json +++ b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/pmon_daemon_control.json @@ -1,3 +1,3 @@ -{ - "skip_ledd": true -} +{ + "skip_ledd": true +} diff --git a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/sensors.conf b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/sensors.conf deleted file mode 100755 index 9b0569d1541d..000000000000 --- a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/sensors.conf +++ /dev/null @@ -1,21 +0,0 @@ -# libsensors configuration file -# ---------------------------------------------- -# - -bus "i2c-2" "i2c-0-mux (chan_id 0)" - -chip "lm75-i2c-2-48" - label temp1 "LM75_0 air_inlet" - set temp1_max 80 - set temp1_max_hyst 75 - -chip "lm75-i2c-2-49" - label temp1 "LM75_1 air_outlet" - set temp1_max 80 - set temp1_max_hyst 75 - -chip "lm75-i2c-2-4a" - label temp1 "LM75_2 hottest" - set temp1_max 80 - set temp1_max_hyst 75 - diff --git a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/sonic_platform_config/chassis.json b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/sonic_platform_config/chassis.json deleted file mode 100644 index c5ea46918ff2..000000000000 --- a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/sonic_platform_config/chassis.json +++ /dev/null @@ -1,3 +0,0 @@ -{ - "eeprom": {"bus": 2, "loc": "0057"} -} \ No newline at end of file diff --git a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/sonic_platform_config/component.json b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/sonic_platform_config/component.json deleted file mode 100644 index 35f4b4586447..000000000000 --- a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/sonic_platform_config/component.json +++ /dev/null @@ -1,60 +0,0 @@ -{ - "components": [ - { - "name": "CPLD1 (MAC Board A)", - "firmware_version": { - "bus": 2, - "addr": 51, - "offset": 0, - "size": 4, - "way": 1, - "format": 7, - "sep": "/" - }, - "desc": "Used for managing IO modules, SFP+ modules and system LEDs", - "slot": 0 - }, - { - "name": "CPLD2 (MAC Board B)", - "firmware_version": { - "bus": 2, - "addr": 53, - "offset": 0, - "size": 4, - "way": 1, - "format": 7, - "sep": "/" - }, - "desc": "Used for managing IO modules, SFP+ modules and system LEDs", - "slot": 0 - }, - { - "name": "CPLD3 (CONNECT Board A)", - "firmware_version": { - "bus": 2, - "addr": 55, - "offset": 0, - "size": 4, - "way": 1, - "format": 7, - "sep": "/" - }, - "desc": "Used for managing IO modules, SFP+ modules and system LEDs", - "slot": 0 - }, - { - "name": "CPLD4 (CPU Board)", - "firmware_version": { - "bus": 0, - "addr": 13, - "offset": 0, - "size": 4, - "way": 1, - "format": 7, - "sep": "/" - }, - "desc": "Used for managing IO modules, SFP+ modules and system LEDs", - "slot": 1 - } - ] -} \ No newline at end of file diff --git a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/sonic_platform_config/fan.json b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/sonic_platform_config/fan.json deleted file mode 100644 index de7030ec1f90..000000000000 --- a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/sonic_platform_config/fan.json +++ /dev/null @@ -1,152 +0,0 @@ -{ - "fans": [ - { - "name": "fan1", - "e2loc": {"bus": 3, "addr": 83, "way": "i2c", "size": "256"}, - "present": { - "loc": "/sys/bus/i2c/devices/2-0037/fan_present", - "format": 2, - "bit": 0 - }, - "status": { - "loc": "/sys/bus/i2c/devices/2-0037/fan_status", - "format": 2, - "bit": 0 - }, - "hw_version": {"loc": "/sys/bus/i2c/devices/3-0053/fan_hw_version"}, - "sn": {"loc": "/sys/bus/i2c/devices/3-0053/fan_sn"}, - "led": { - "loc": "/sys/bus/i2c/devices/0-0032/fan0_led", - "format": 6, - "mask": 11 - }, - "led_colors": { - "green": 9, - "red": 10, - "amber": 3 - }, - "rotors": [ - { - "speed_getter": { - "loc": "/sys/bus/i2c/devices/2-0037/hwmon/*/fan1_input" - }, - "speed_setter": { - "loc": "/sys/bus/i2c/devices/0-0032/fan_speed_set" - }, - "speed_max": 23000 - } - ] - }, - { - "name": "fan2", - "e2loc": {"bus": 4, "addr": 83, "way": "i2c", "size": "256"}, - "present": { - "loc": "/sys/bus/i2c/devices/2-0037/fan_present", - "format": 2, - "bit": 1 - }, - "status": { - "loc": "/sys/bus/i2c/devices/2-0037/fan_status", - "format": 2, - "bit": 1 - }, - "hw_version": {"loc": "/sys/bus/i2c/devices/4-0053/fan_hw_version"}, - "sn": {"loc": "/sys/bus/i2c/devices/4-0053/fan_sn"}, - "led": { - "loc": "/sys/bus/i2c/devices/0-0032/fan1_led", - "format": 6, - "mask": 11 - }, - "led_colors": { - "green": 9, - "red": 10, - "amber": 3 - }, - "rotors": [ - { - "speed_getter": { - "loc": "/sys/bus/i2c/devices/2-0037/hwmon/*/fan2_input" - }, - "speed_setter": { - "loc": "/sys/bus/i2c/devices/0-0032/fan_speed_set" - }, - "speed_max": 23000 - } - ] - }, - { - "name": "fan3", - "e2loc": {"bus": 3, "addr": 83, "way": "i2c", "size": "256"}, - "present": { - "loc": "/sys/bus/i2c/devices/2-0037/fan_present", - "format": 2, - "bit": 2 - }, - "status": { - "loc": "/sys/bus/i2c/devices/2-0037/fan_status", - "format": 2, - "bit": 2 - }, - "hw_version": {"loc": "/sys/bus/i2c/devices/5-0053/fan_hw_version"}, - "sn": {"loc": "/sys/bus/i2c/devices/5-0053/fan_sn"}, - "led": { - "loc": "/sys/bus/i2c/devices/0-0032/fan2_led", - "format": 6, - "mask": 11 - }, - "led_colors": { - "green": 9, - "red": 10, - "amber": 3 - }, - "rotors": [ - { - "speed_getter": { - "loc": "/sys/bus/i2c/devices/2-0037/hwmon/*/fan3_input" - }, - "speed_setter": { - "loc": "/sys/bus/i2c/devices/0-0032/fan_speed_set" - }, - "speed_max": 23000 - } - ] - }, - { - "name": "fan4", - "e2loc": {"bus": 3, "addr": 83, "way": "i2c", "size": "256"}, - "present": { - "loc": "/sys/bus/i2c/devices/2-0037/fan_present", - "format": 2, - "bit": 3 - }, - "status": { - "loc": "/sys/bus/i2c/devices/2-0037/fan_status", - "format": 2, - "bit": 3 - }, - "hw_version": {"loc": "/sys/bus/i2c/devices/6-0053/fan_hw_version"}, - "sn": {"loc": "/sys/bus/i2c/devices/6-0053/fan_sn"}, - "led": { - "loc": "/sys/bus/i2c/devices/0-0032/fan3_led", - "format": 6, - "mask": 11 - }, - "led_colors":{ - "green": 9, - "red": 10, - "amber": 3 - }, - "rotors": [ - { - "speed_getter": { - "loc": "/sys/bus/i2c/devices/2-0037/hwmon/*/fan4_input" - }, - "speed_setter": { - "loc": "/sys/bus/i2c/devices/0-0032/fan_speed_set" - }, - "speed_max": 23000 - } - ] - } - ] -} \ No newline at end of file diff --git a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/sonic_platform_config/psu.json b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/sonic_platform_config/psu.json deleted file mode 100644 index c807b51fc4b6..000000000000 --- a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/sonic_platform_config/psu.json +++ /dev/null @@ -1,134 +0,0 @@ -{ - "psus": [ - { - "name": "psu1", - "present": { - "loc": "/sys/bus/i2c/devices/2-0037/psu_status", - "format": 2, - "bit": 0 - }, - "status": { - "loc": "/sys/bus/i2c/devices/2-0037/psu_status", - "format": 2, - "bit": 1 - }, - "sn": {"loc": "/sys/bus/i2c/devices/7-0050/psu_sn"}, - "in_current": { - "loc": "/sys/bus/i2c/devices/7-0058/hwmon/*/curr1_input", - "format": 4 - }, - "in_voltage": { - "loc": "/sys/bus/i2c/devices/7-0058/hwmon/*/in1_input", - "format": 4 - }, - "out_voltage": { - "loc": "/sys/bus/i2c/devices/7-0058/hwmon/*/in2_input", - "format": 4 - }, - "out_current": { - "loc": "/sys/bus/i2c/devices/7-0058/hwmon/*/curr2_input", - "format": 4 - }, - "temperature": { - "loc": "/sys/bus/i2c/devices/7-0058/hwmon/*/temp1_input", - "format": 4 - }, - "hw_version": {"loc": "/sys/bus/i2c/devices/7-0050/psu_hw"}, - "psu_type": {"loc": "/sys/bus/i2c/devices/7-0050/psu_type"}, - "fans": [ - { - "name": "psu_fan1", - "present": { - "loc": "/sys/bus/i2c/devices/7-0058/hwmon/*/fan1_fault" - }, - "status": { - "loc": "/sys/bus/i2c/devices/2-0037/psu_status", - "format": 2, - "bit": 1 - }, - "rotors": [ - { - "speed_getter": { - "loc": "/sys/bus/i2c/devices/7-0058/hwmon/*/fan1_input" - }, - "speed_max": 28000 - } - ] - } - ], - "in_power": { - "loc": "/sys/bus/i2c/devices/7-0058/hwmon/*/power1_input", - "format": 5 - }, - "out_power": { - "loc": "/sys/bus/i2c/devices/7-0058/hwmon/*/power2_input", - "format": 5 - } - }, - { - "name": "psu2", - "present": { - "loc": "/sys/bus/i2c/devices/2-0037/psu_status", - "format": 2, - "bit": 4 - }, - "status": { - "loc": "/sys/bus/i2c/devices/2-0037/psu_status", - "format": 2, - "bit": 5 - }, - "sn": {"loc": "/sys/bus/i2c/devices/8-0053/psu_sn"}, - "in_current": { - "loc": "/sys/bus/i2c/devices/8-005b/hwmon/*/curr1_input", - "format": 4 - }, - "in_voltage": { - "loc": "/sys/bus/i2c/devices/8-005b/hwmon/*/in1_input", - "format": 4 - }, - "out_voltage": { - "loc": "/sys/bus/i2c/devices/8-005b/hwmon/*/in2_input", - "format": 4 - }, - "out_current": { - "loc": "/sys/bus/i2c/devices/8-005b/hwmon/*/curr2_input", - "format": 4 - }, - "temperature": { - "loc": "/sys/bus/i2c/devices/8-005b/hwmon/*/temp1_input", - "format": 4 - }, - "hw_version": {"loc": "/sys/bus/i2c/devices/8-0053/psu_hw"}, - "psu_type": {"loc": "/sys/bus/i2c/devices/8-0053/psu_type"}, - "fans": [ - { - "name": "psu_fan1", - "present": { - "loc": "/sys/bus/i2c/devices/8-005b/hwmon/*/fan1_fault" - }, - "status": { - "loc": "/sys/bus/i2c/devices/2-0037/psu_status", - "format": 2, - "bit": 5 - }, - "rotors": [ - { - "speed_getter": { - "loc": "/sys/bus/i2c/devices/8-005b/hwmon/*/fan1_input" - }, - "speed_max": 28000 - } - ] - } - ], - "in_power": { - "loc": "/sys/bus/i2c/devices/8-005b/hwmon/*/power1_input", - "format": 5 - }, - "out_power": { - "loc": "/sys/bus/i2c/devices/8-005b/hwmon/*/power2_input", - "format": 5 - } - } - ] -} \ No newline at end of file diff --git a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/sonic_platform_config/thermal.json b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/sonic_platform_config/thermal.json deleted file mode 100644 index 319336673534..000000000000 --- a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/sonic_platform_config/thermal.json +++ /dev/null @@ -1,130 +0,0 @@ -{"thermals": [ - { - "name": "INLET TEMP", - "high": { - "loc": "/sys/bus/i2c/devices/2-0048/hwmon/*/temp1_max", - "format": 4 - }, - "low": null, - "crit_low": null, - "crit_high": null, - "temperature": { - "loc": "/sys/bus/i2c/devices/2-0048/hwmon/*/temp1_input", - "format": 4 - } - }, - { - "name": "OUTLET TEMP", - "high": { - "loc": "/sys/bus/i2c/devices/2-0049/hwmon/*/temp1_max", - "format": 4 - }, - "low": null, - "crit_low": null, - "crit_high": null, - "temperature": { - "loc": "/sys/bus/i2c/devices/2-0049/hwmon/*/temp1_input", - "format": 4 - } - }, - { - "name": "BOARD TEMP", - "high": { - "loc": "/sys/bus/i2c/devices/2-004a/hwmon/*/temp1_max", - "format": 4 - }, - "low": null, - "crit_low": null, - "crit_high": null, - "temperature": { - "loc": "/sys/bus/i2c/devices/2-004a/hwmon/*/temp1_input", - "format": 4 - } - }, - { - "name": "PHYSICAL ID 0", - "high": { - "loc": "/sys/class/hwmon/hwmon0/temp1_max", - "format": 4 - }, - "low": null, - "crit_low": null, - "crit_high": { - "loc": "/sys/class/hwmon/hwmon0/temp1_crit", - "format": 4 - }, - "temperature": { - "loc": "/sys/class/hwmon/hwmon0/temp1_input", - "format": 4 - } - }, - { - "name": "CPU CORE 0", - "high": { - "loc": "/sys/class/hwmon/hwmon0/temp2_max", - "format": 4 - }, - "low": null, - "crit_low": null, - "crit_high": { - "loc": "/sys/class/hwmon/hwmon0/temp2_crit", - "format": 4 - }, - "temperature": { - "loc": "/sys/class/hwmon/hwmon0/temp2_input", - "format": 4 - } - }, - { - "name": "CPU CORE 1", - "high": { - "loc": "/sys/class/hwmon/hwmon0/temp3_max", - "format": 4 - }, - "low": null, - "crit_low": null, - "crit_high": { - "loc": "/sys/class/hwmon/hwmon0/temp3_crit", - "format": 4 - }, - "temperature": { - "loc": "/sys/class/hwmon/hwmon0/temp3_input", - "format": 4 - } - }, - { - "name": "CPU CORE 2", - "high": { - "loc": "/sys/class/hwmon/hwmon0/temp4_max", - "format": 4 - }, - "low": null, - "crit_low": null, - "crit_high": { - "loc": "/sys/class/hwmon/hwmon0/temp4_crit", - "format": 4 - }, - "temperature": { - "loc": "/sys/class/hwmon/hwmon0/temp4_input", - "format": 4 - } - }, - { - "name": "CPU CORE 3", - "high": { - "loc": "/sys/class/hwmon/hwmon0/temp5_max", - "format": 4 - }, - "low": null, - "crit_low": null, - "crit_high": { - "loc": "/sys/class/hwmon/hwmon0/temp5_crit", - "format": 4 - }, - "temperature": { - "loc": "/sys/class/hwmon/hwmon0/temp5_input", - "format": 4 - } - } - ] -} \ No newline at end of file diff --git a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/pddf_support b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/system_health_monitoring_config.json old mode 100644 new mode 100755 similarity index 100% rename from device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/pddf_support rename to device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/system_health_monitoring_config.json diff --git a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/systest.py b/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/systest.py deleted file mode 100644 index 38e9ff6aa0c9..000000000000 --- a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/systest.py +++ /dev/null @@ -1,43 +0,0 @@ -#!/usr/bin/python3 -# -*- coding: UTF-8 -*- -""" -* onboard temperature sensors -* FAN trays -* PSU -""" -import time -import datetime -from monitor import status - -def doWork(): - a=[]; - ''' - return: [{'status': '1', 'hw_version': '1.00', 'errcode': 0, 'fan_type': 'M6510-FAN-F', 'errmsg': 'OK', 'Speed': '9778', 'id': 'fan1', 'present': '0', 'sn': '1000000000014'}, - {'id': 'fan2', 'errmsg': 'not present', 'errcode': -1}, - {'id': 'fan3', 'errmsg': 'not present', 'errcode': -1}, - {'id': 'fan4', 'errmsg': 'not present', 'errcode': -1} - ] - description: 1.get id - 2.errcode equal 0 : dev normal - not equal 0 : get errmsg - 3.other message add when all check success - ''' - status.checkFan(a) - #status.getTemp(a) - #status.getPsu(a) - - nowTime=datetime.datetime.now().strftime('%Y-%m-%d %H:%M:%S') - print(nowTime) - print(a) -def run(interval): - while True: - try: - time_remaining = interval - time.time()%interval - time.sleep(time_remaining) - doWork() - except Exception as e: - print(e) - -if __name__ == '__main__': - interval = 1 - run(interval) diff --git a/device/supermicro/x86_64-supermicro_sse_t7132s-r0/CSV/TL7_DAC_1M.csv b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/CSV/TL7_DAC_1M.csv new file mode 100755 index 000000000000..00afc9d8efc9 --- /dev/null +++ b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/CSV/TL7_DAC_1M.csv @@ -0,0 +1,263 @@ +VERSION,CABLE TYPE,VENDOR,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +1.2,DAC_1M,GENERIC,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,SPEED,ENCODING,,,,,,,,,SPEED,ENCODING,,,,,,,,,,,,,SPEED,ENCODING,,,,,,,SPEED,ENCODING,,,,,,,SPEED,ENCODING,,,,,,,,,, +,,,50G/400G,PAM4,,,,,,,,,25G/100G,NRZ,,,,,,,,,,,,,10G/40G,NRZ,,,,,,,LT 50G/400G ,PAM4,,,,,,,ANLT 25G/100G ,NRZ,,,,,,,,,, +index,Front Port,lane,TX_EQ_ATTN,TX_EQ_PRE1,TX_EQ_PRE2,TX_EQ_PRE3,TX_EQ_POST,RX_EQ_COARSE_TUNE_EFFORT_50G,RX_EQ_FINE_TUNE_EFFORT_50G,RX_GAINSHAPE1,RX_GAINSHAPE2,LINK_TRAINING,TX_EQ_ATTN,TX_EQ_PRE1,TX_EQ_PRE2,TX_EQ_PRE3,TX_EQ_POST,RX_GAINSHAPE1,RX_GAINSHAPE2,RX_AGC_TARGET,RX_EYE_DISQUALIFY_THRESHOLD_25G,RX_EQ_COARSE_TUNE_EFFORT_25G,RX_EQ_FINE_TUNE_EFFORT_25G,SD_RESET_THRESHOLD,SD_RESET_25G,LINK_TRAINING,TX_EQ_ATTN,TX_EQ_PRE1,TX_EQ_PRE2,TX_EQ_PRE3,TX_EQ_POST,RX_GAINSHAPE1,RX_GAINSHAPE2,LINK_TRAINING,RX_GAINSHAPE1,RX_GAINSHAPE2,RX_EQ_COARSE_TUNE_EFFORT_50G,RX_EQ_FINE_TUNE_EFFORT_50G,RX_CTLE_LF,RX_CTLE_HF,RX_CTLE_BW,LINK_TRAINING,RX_GAINSHAPE1,RX_GAINSHAPE2,RX_AGC_TARGET,RX_EYE_DISQUALIFY_THRESHOLD_25G,RX_EQ_COARSE_TUNE_EFFORT_25G,RX_EQ_FINE_TUNE_EFFORT_25G,SD_RESET_25G,SD_RESET_THRESHOLD_25G,LINK_TRAINING,AN,AN_ABILITY,FEC +0,0,0,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +1,0,1,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +2,0,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +3,0,3,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +4,0,4,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +5,0,5,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +6,0,6,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +7,0,7,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +8,1,0,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +9,1,1,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +10,1,2,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +11,1,3,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +12,1,4,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +13,1,5,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +14,1,6,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +15,1,7,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +16,2,0,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +17,2,1,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +18,2,2,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +19,2,3,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +20,2,4,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +21,2,5,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +22,2,6,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +23,2,7,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +24,3,0,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +25,3,1,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +26,3,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +27,3,3,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +28,3,4,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +29,3,5,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +30,3,6,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +31,3,7,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +32,4,0,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +33,4,1,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +34,4,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +35,4,3,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +36,4,4,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +37,4,5,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +38,4,6,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +39,4,7,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +40,5,0,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +41,5,1,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +42,5,2,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +43,5,3,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +44,5,4,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +45,5,5,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +46,5,6,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +47,5,7,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +48,6,0,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +49,6,1,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +50,6,2,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +51,6,3,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +52,6,4,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +53,6,5,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +54,6,6,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +55,6,7,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +56,7,0,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +57,7,1,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +58,7,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +59,7,3,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +60,7,4,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +61,7,5,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +62,7,6,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +63,7,7,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +64,8,0,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +65,8,1,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +66,8,2,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +67,8,3,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +68,8,4,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +69,8,5,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +70,8,6,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +71,8,7,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +72,9,0,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +73,9,1,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +74,9,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +75,9,3,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +76,9,4,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +77,9,5,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +78,9,6,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +79,9,7,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +80,10,0,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +81,10,1,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +82,10,2,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +83,10,3,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +84,10,4,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +85,10,5,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +86,10,6,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +87,10,7,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +88,11,0,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +89,11,1,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +90,11,2,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +91,11,3,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +92,11,4,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +93,11,5,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +94,11,6,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +95,11,7,0,2,0,0,2,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +96,12,0,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +97,12,1,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +98,12,2,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +99,12,3,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +100,12,4,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +101,12,5,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +102,12,6,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +103,12,7,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +104,13,0,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +105,13,1,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +106,13,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +107,13,3,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +108,13,4,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +109,13,5,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +110,13,6,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +111,13,7,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +112,14,0,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +113,14,1,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +114,14,2,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +115,14,3,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +116,14,4,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +117,14,5,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +118,14,6,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +119,14,7,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +120,15,0,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +121,15,1,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +122,15,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +123,15,3,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +124,15,4,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +125,15,5,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +126,15,6,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +127,15,7,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +128,16,0,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +129,16,1,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +130,16,2,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +131,16,3,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +132,16,4,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +133,16,5,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +134,16,6,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +135,16,7,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +136,17,0,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +137,17,1,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +138,17,2,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +139,17,3,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +140,17,4,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +141,17,5,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +142,17,6,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +143,17,7,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +144,18,0,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +145,18,1,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +146,18,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +147,18,3,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +148,18,4,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +149,18,5,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +150,18,6,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +151,18,7,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +152,19,0,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +153,19,1,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +154,19,2,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +155,19,3,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +156,19,4,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +157,19,5,0,4,0,0,4,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +158,19,6,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +159,19,7,0,2,0,0,2,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +160,20,0,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +161,20,1,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +162,20,2,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +163,20,3,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +164,20,4,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +165,20,5,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +166,20,6,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +167,20,7,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +168,21,0,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +169,21,1,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +170,21,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +171,21,3,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +172,21,4,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +173,21,5,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +174,21,6,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +175,21,7,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +176,22,0,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +177,22,1,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +178,22,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +179,22,3,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +180,22,4,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +181,22,5,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +182,22,6,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +183,22,7,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +184,23,0,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +185,23,1,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +186,23,2,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +187,23,3,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +188,23,4,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +189,23,5,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +190,23,6,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +191,23,7,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +192,24,0,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +193,24,1,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +194,24,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +195,24,3,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +196,24,4,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +197,24,5,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +198,24,6,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +199,24,7,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +200,25,0,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +201,25,1,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +202,25,2,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +203,25,3,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +204,25,4,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +205,25,5,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +206,25,6,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +207,25,7,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +208,26,0,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +209,26,1,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +210,26,2,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +211,26,3,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +212,26,4,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +213,26,5,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +214,26,6,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +215,26,7,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +216,27,0,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +217,27,1,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +218,27,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +219,27,3,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +220,27,4,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +221,27,5,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +222,27,6,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +223,27,7,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +224,28,0,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +225,28,1,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +226,28,2,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +227,28,3,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +228,28,4,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +229,28,5,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +230,28,6,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +231,28,7,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +232,29,0,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +233,29,1,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +234,29,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +235,29,3,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +236,29,4,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +237,29,5,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +238,29,6,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +239,29,7,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +240,30,0,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +241,30,1,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +242,30,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +243,30,3,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +244,30,4,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +245,30,5,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +246,30,6,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +247,30,7,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +248,31,0,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +249,31,1,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +250,31,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +251,31,3,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +252,31,4,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +253,31,5,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +254,31,6,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +255,31,7,0,8,0,0,8,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +256,32,0,0,0,0,0,0,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,10GBASE-CR4,NONE +257,32,1,0,0,0,0,0,Medium,HIGH,0,2,0,0,0,0,0,0,0,1,130,100,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,10GBASE-CR4,NONE diff --git a/device/supermicro/x86_64-supermicro_sse_t7132s-r0/CSV/TL7_DAC_3M.csv b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/CSV/TL7_DAC_3M.csv new file mode 100755 index 000000000000..6b9579b3d055 --- /dev/null +++ b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/CSV/TL7_DAC_3M.csv @@ -0,0 +1,263 @@ +VERSION,CABLE TYPE,VENDOR,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +1.2,DAC_3M,GENERIC,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,SPEED,ENCODING,,,,,,,,,SPEED,ENCODING,,,,,,,,,,,,,SPEED,ENCODING,,,,,,,SPEED,ENCODING,,,,,,,SPEED,ENCODING,,,,,,,,,, +,,,50G/400G,PAM4,,,,,,,,,25G/100G,NRZ,,,,,,,,,,,,,10G/40G,NRZ,,,,,,,LT 50G/400G,PAM4,,,,,,,ANLT 25G/100G,NRZ,,,,,,,,,, +index,Front Port,lane,TX_EQ_ATTN,TX_EQ_PRE1,TX_EQ_PRE2,TX_EQ_PRE3,TX_EQ_POST,RX_EQ_COARSE_TUNE_EFFORT_50G,RX_EQ_FINE_TUNE_EFFORT_50G,RX_GAINSHAPE1,RX_GAINSHAPE2,LINK_TRAINING,TX_EQ_ATTN,TX_EQ_PRE1,TX_EQ_PRE2,TX_EQ_PRE3,TX_EQ_POST,RX_GAINSHAPE1,RX_GAINSHAPE2,RX_AGC_TARGET,RX_EYE_DISQUALIFY_THRESHOLD_25G,RX_EQ_COARSE_TUNE_EFFORT_25G,RX_EQ_FINE_TUNE_EFFORT_25G,SD_RESET_THRESHOLD,SD_RESET_25G,LINK_TRAINING,TX_EQ_ATTN,TX_EQ_PRE1,TX_EQ_PRE2,TX_EQ_PRE3,TX_EQ_POST,RX_GAINSHAPE1,RX_GAINSHAPE2,LINK_TRAINING,RX_GAINSHAPE1,RX_GAINSHAPE2,RX_EQ_COARSE_TUNE_EFFORT_50G,RX_EQ_FINE_TUNE_EFFORT_50G,RX_CTLE_LF,RX_CTLE_HF,RX_CTLE_BW,LINK_TRAINING,RX_GAINSHAPE1,RX_GAINSHAPE2,RX_AGC_TARGET,RX_EYE_DISQUALIFY_THRESHOLD_25G,RX_EQ_COARSE_TUNE_EFFORT_25G,RX_EQ_FINE_TUNE_EFFORT_25G,SD_RESET_25G,SD_RESET_THRESHOLD_25G,LINK_TRAINING,AN,AN_ABILITY,FEC +0,0,0,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +1,0,1,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +2,0,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +3,0,3,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +4,0,4,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +5,0,5,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +6,0,6,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +7,0,7,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +8,1,0,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +9,1,1,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +10,1,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +11,1,3,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +12,1,4,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +13,1,5,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +14,1,6,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +15,1,7,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +16,2,0,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +17,2,1,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +18,2,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +19,2,3,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +20,2,4,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +21,2,5,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +22,2,6,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +23,2,7,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +24,3,0,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +25,3,1,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +26,3,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +27,3,3,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +28,3,4,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +29,3,5,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +30,3,6,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +31,3,7,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +32,4,0,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +33,4,1,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +34,4,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +35,4,3,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +36,4,4,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +37,4,5,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +38,4,6,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +39,4,7,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +40,5,0,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +41,5,1,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +42,5,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +43,5,3,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +44,5,4,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +45,5,5,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +46,5,6,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +47,5,7,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +48,6,0,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +49,6,1,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +50,6,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +51,6,3,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +52,6,4,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +53,6,5,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +54,6,6,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +55,6,7,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +56,7,0,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +57,7,1,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +58,7,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +59,7,3,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +60,7,4,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +61,7,5,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +62,7,6,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +63,7,7,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +64,8,0,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +65,8,1,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +66,8,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +67,8,3,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +68,8,4,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +69,8,5,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +70,8,6,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +71,8,7,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +72,9,0,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +73,9,1,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +74,9,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +75,9,3,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +76,9,4,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +77,9,5,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +78,9,6,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +79,9,7,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +80,10,0,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +81,10,1,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +82,10,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +83,10,3,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +84,10,4,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +85,10,5,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +86,10,6,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +87,10,7,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +88,11,0,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +89,11,1,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +90,11,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +91,11,3,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +92,11,4,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +93,11,5,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +94,11,6,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +95,11,7,0,2,0,0,2,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +96,12,0,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +97,12,1,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +98,12,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +99,12,3,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +100,12,4,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +101,12,5,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +102,12,6,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +103,12,7,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +104,13,0,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +105,13,1,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +106,13,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +107,13,3,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +108,13,4,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +109,13,5,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +110,13,6,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +111,13,7,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +112,14,0,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +113,14,1,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +114,14,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +115,14,3,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +116,14,4,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +117,14,5,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +118,14,6,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +119,14,7,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +120,15,0,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +121,15,1,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +122,15,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +123,15,3,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +124,15,4,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +125,15,5,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +126,15,6,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +127,15,7,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +128,16,0,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +129,16,1,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +130,16,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +131,16,3,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +132,16,4,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +133,16,5,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +134,16,6,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +135,16,7,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +136,17,0,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +137,17,1,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +138,17,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +139,17,3,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +140,17,4,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +141,17,5,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +142,17,6,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +143,17,7,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +144,18,0,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +145,18,1,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +146,18,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +147,18,3,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +148,18,4,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +149,18,5,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +150,18,6,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +151,18,7,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +152,19,0,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +153,19,1,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +154,19,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +155,19,3,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +156,19,4,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +157,19,5,0,4,0,0,4,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +158,19,6,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +159,19,7,0,2,0,0,2,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +160,20,0,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +161,20,1,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +162,20,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +163,20,3,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +164,20,4,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +165,20,5,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +166,20,6,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +167,20,7,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +168,21,0,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +169,21,1,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +170,21,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +171,21,3,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +172,21,4,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +173,21,5,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +174,21,6,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +175,21,7,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +176,22,0,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +177,22,1,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +178,22,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +179,22,3,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +180,22,4,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +181,22,5,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +182,22,6,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +183,22,7,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +184,23,0,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +185,23,1,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +186,23,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +187,23,3,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +188,23,4,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +189,23,5,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +190,23,6,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +191,23,7,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +192,24,0,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +193,24,1,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +194,24,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +195,24,3,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +196,24,4,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +197,24,5,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +198,24,6,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +199,24,7,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +200,25,0,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +201,25,1,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +202,25,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +203,25,3,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +204,25,4,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +205,25,5,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +206,25,6,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +207,25,7,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +208,26,0,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +209,26,1,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +210,26,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +211,26,3,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +212,26,4,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +213,26,5,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +214,26,6,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +215,26,7,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +216,27,0,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +217,27,1,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +218,27,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +219,27,3,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +220,27,4,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +221,27,5,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +222,27,6,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +223,27,7,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +224,28,0,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +225,28,1,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +226,28,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +227,28,3,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +228,28,4,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +229,28,5,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +230,28,6,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +231,28,7,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +232,29,0,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +233,29,1,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +234,29,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +235,29,3,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +236,29,4,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +237,29,5,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +238,29,6,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +239,29,7,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +240,30,0,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +241,30,1,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +242,30,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +243,30,3,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +244,30,4,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +245,30,5,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +246,30,6,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +247,30,7,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +248,31,0,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +249,31,1,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +250,31,2,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +251,31,3,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +252,31,4,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +253,31,5,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +254,31,6,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +255,31,7,0,6,0,0,6,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,1,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,100GBASE-KR4,NONE +256,32,0,0,0,0,0,0,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,2,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,10GBASE-CR4,NONE +257,32,1,0,0,0,0,0,Medium,HIGH,0,2,0,0,0,0,0,0,2,2,130,150,Low,Low,5,TRUE,0,3,2,-2,0,4,0,2,0,0,2,Medium,High,0,10,10,1,0,1,130,100,Low,Low,0,NA,1,1,10GBASE-CR4,NONE diff --git a/device/supermicro/x86_64-supermicro_sse_t7132s-r0/CSV/TL7_Optics.csv b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/CSV/TL7_Optics.csv new file mode 100755 index 000000000000..07ac2b449d12 --- /dev/null +++ b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/CSV/TL7_Optics.csv @@ -0,0 +1,263 @@ +VERSION,CABLE TYPE,VENDOR,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +1.2,OPTICS,GENERIC,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,SPEED,ENCODING,,,,,,,,,,SPEED,ENCODING,,,,,,,,,,,,,,SPEED,ENCODING,,,,,, +,,,50G/400G,PAM4,,,,,,,,,,25G/100G,NRZ,,,,,,,,,,,,,,10G/40G,NRZ,,,,,, +index,Front Port,lane,TX_EQ_ATTN,TX_EQ_PRE1,TX_EQ_PRE2,TX_EQ_PRE3,TX_EQ_POST,Optical Module CTLE,RX_EQ_COARSE_TUNE_EFFORT_50G,RX_EQ_FINE_TUNE_EFFORT_50G,RX_GAINSHAPE1,RX_GAINSHAPE2,LINK_TRAINING,TX_EQ_ATTN,TX_EQ_PRE1,TX_EQ_PRE2,TX_EQ_PRE3,TX_EQ_POST,Optical Module CTLE,RX_GAINSHAPE1,RX_GAINSHAPE2,RX_AGC_TARGET,RX_EYE_DISQUALIFY_THRESHOLD_25G,RX_EQ_COARSE_TUNE_EFFORT_25G,RX_EQ_FINE_TUNE_EFFORT_25G,SD_RESET_THRESHOLD,SD_RESET_25G,LINK_TRAINING,TX_EQ_ATTN,TX_EQ_PRE1,TX_EQ_PRE2,TX_EQ_PRE3,TX_EQ_POST,RX_GAINSHAPE1,RX_GAINSHAPE2,LINK_TRAINING +0,0,0,0,4,0,0,4,4.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,High,High,NA,FALSE,0,0,0,0,0,0,0,0,0 +1,0,1,0,4,-1,0,2,6,Medium,High,0,0,0,0,4,0,0,4,4,0,0,100,100,High,High,NA,FALSE,0,0,0,0,0,0,0,0,0 +2,0,2,0,4,0,0,0,6,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,High,High,NA,FALSE,0,0,0,0,0,0,0,0,0 +3,0,3,0,4,0,0,4,4.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,High,High,NA,FALSE,0,0,0,0,0,0,0,0,0 +4,0,4,0,4,0,0,4,5.5,Medium,High,0,0,0,0,4,0,0,4,4,0,0,100,100,High,High,NA,FALSE,0,0,0,0,0,0,0,0,0 +5,0,5,0,4,0,0,4,5.5,Medium,High,0,0,0,0,2,0,0,4,4,0,0,100,100,High,High,NA,FALSE,0,0,0,0,0,0,0,0,0 +6,0,6,0,4,0,0,4,5.5,Medium,High,0,0,0,0,4,0,0,4,4,0,0,100,100,High,High,NA,FALSE,0,0,0,0,0,0,0,0,0 +7,0,7,0,4,0,0,4,5,Medium,High,0,0,0,0,4,0,0,4,4,0,0,100,100,High,High,NA,FALSE,0,0,0,0,0,0,0,0,0 +8,1,0,0,4,0,0,2,4.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +9,1,1,0,4,0,0,2,5.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +10,1,2,0,4,0,0,0,6,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +11,1,3,0,4,0,0,2,5.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +12,1,4,0,4,0,0,2,5.5,Medium,High,0,0,0,0,4,-1,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +13,1,5,0,4,0,0,2,5.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +14,1,6,0,4,0,0,4,5,Medium,High,0,0,0,0,4,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +15,1,7,0,4,0,0,2,5.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +16,2,0,0,4,0,0,0,6,Medium,High,0,0,0,0,2,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +17,2,1,0,4,0,0,2,5.5,Medium,High,0,0,0,0,2,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +18,2,2,0,4,0,0,0,6,Medium,High,0,0,0,0,2,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +19,2,3,0,4,0,0,0,6,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +20,2,4,0,4,0,0,4,5,Medium,High,0,0,0,0,2,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +21,2,5,0,4,0,0,2,5.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +22,2,6,0,4,0,0,4,5,Medium,High,0,0,0,0,2,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +23,2,7,0,4,0,0,2,5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +24,3,0,0,4,0,0,2,5.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +25,3,1,0,4,0,0,2,5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +26,3,2,0,4,0,0,0,5.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +27,3,3,0,4,0,0,2,5.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +28,3,4,0,4,-1,0,0,5.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +29,3,5,0,4,0,0,2,5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +30,3,6,0,2,0,0,4,4.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +31,3,7,0,4,0,0,2,5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +32,4,0,0,4,0,0,2,4,Medium,High,0,0,0,0,6,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +33,4,1,0,2,0,0,2,5.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +34,4,2,0,4,0,0,2,4,Medium,High,0,0,0,1,0,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +35,4,3,0,4,0,0,2,4.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +36,4,4,0,4,0,0,2,5.5,Medium,High,0,0,0,0,2,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +37,4,5,0,4,0,0,2,5,Medium,High,0,0,0,0,2,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +38,4,6,0,4,0,0,2,5.5,Medium,High,0,0,0,0,2,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +39,4,7,0,4,0,0,2,4.5,Medium,High,0,0,0,0,4,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +40,5,0,0,4,0,0,0,5,Medium,High,0,0,0,0,4,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +41,5,1,0,4,0,0,0,5,Medium,High,0,0,0,0,4,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +42,5,2,0,4,0,0,2,5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +43,5,3,0,4,0,0,0,5,Medium,High,0,0,0,0,4,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +44,5,4,0,4,0,0,2,4.5,Medium,High,0,0,0,0,4,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +45,5,5,0,2,0,0,4,4,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +46,5,6,0,4,0,0,2,5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +47,5,7,0,4,0,0,0,5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +48,6,0,0,4,0,0,0,5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +49,6,1,0,4,0,0,2,5.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +50,6,2,0,4,0,0,2,4,Medium,High,0,0,0,0,4,-1,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +51,6,3,0,4,0,0,0,5.5,Medium,High,0,0,0,0,2,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +52,6,4,0,4,0,0,2,5.5,Medium,High,0,0,0,0,2,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +53,6,5,0,4,0,0,2,5.5,Medium,High,0,0,0,0,2,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +54,6,6,0,2,0,0,2,5.5,Medium,High,0,0,0,0,2,0,1,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +55,6,7,0,4,0,0,2,4.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +56,7,0,0,4,0,0,0,5.5,Medium,High,0,0,0,0,4,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +57,7,1,0,4,0,0,0,5.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +58,7,2,0,4,-1,0,0,5.5,Medium,High,0,0,0,0,4,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +59,7,3,0,4,0,0,2,4,Medium,High,0,0,0,0,4,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +60,7,4,0,4,0,0,0,5,Medium,High,0,0,0,0,4,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +61,7,5,0,4,0,0,0,4.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +62,7,6,0,4,0,0,0,5.5,Medium,High,0,0,0,0,4,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +63,7,7,0,4,0,0,4,4,Medium,High,0,0,0,1,4,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +64,8,0,0,4,0,0,4,4.5,Medium,High,0,0,0,0,4,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +65,8,1,0,4,0,0,4,5,Medium,High,0,0,0,0,4,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +66,8,2,0,4,0,0,2,6,Medium,High,0,0,0,0,4,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +67,8,3,0,4,0,0,2,5,Medium,High,0,0,0,0,4,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +68,8,4,0,4,0,0,4,6,Medium,High,0,0,0,0,2,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +69,8,5,0,4,0,0,4,5.5,Medium,High,0,0,0,0,4,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +70,8,6,0,2,0,0,4,6,Medium,High,0,0,0,0,4,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +71,8,7,0,4,0,0,4,4.5,Medium,High,0,0,0,0,2,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +72,9,0,0,4,0,0,4,5.5,Medium,High,0,0,0,0,2,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +73,9,1,0,4,0,0,0,6.5,Medium,High,0,0,0,0,4,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +74,9,2,0,4,0,0,4,5.5,Medium,High,0,0,0,0,2,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +75,9,3,0,4,0,0,0,6.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +76,9,4,0,4,0,0,4,6,Medium,High,0,0,0,0,4,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +77,9,5,0,4,0,0,4,5.5,Medium,High,0,0,0,0,4,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +78,9,6,0,4,0,0,2,6,Medium,High,0,0,0,0,2,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +79,9,7,0,4,0,0,4,5.5,Medium,High,0,0,0,0,4,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +80,10,0,0,4,0,0,4,4,Medium,High,0,0,0,0,2,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +81,10,1,0,4,0,0,4,5.5,Medium,High,0,0,0,0,4,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +82,10,2,0,4,0,0,4,4,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +83,10,3,0,4,0,0,2,6,Medium,High,0,0,0,0,4,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +84,10,4,0,4,-1,0,4,6,Medium,High,0,0,0,0,6,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +85,10,5,0,4,0,0,4,5.5,Medium,High,0,0,0,0,4,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +86,10,6,0,4,0,0,4,5,Medium,High,0,0,0,0,4,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +87,10,7,0,4,0,0,4,4.5,Medium,High,0,0,0,0,4,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +88,11,0,0,4,0,0,0,6.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +89,11,1,0,4,0,0,2,5.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +90,11,2,0,4,0,0,0,6,Medium,High,0,0,0,0,4,0,1,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +91,11,3,0,4,0,0,0,5.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +92,11,4,0,4,0,0,4,5,Medium,High,0,0,0,0,4,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +93,11,5,0,4,0,0,2,7,Medium,High,0,0,0,0,4,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +94,11,6,0,4,0,0,2,5.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +95,11,7,0,4,0,0,2,5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +96,12,0,0,4,0,0,0,5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +97,12,1,0,4,0,0,2,5.5,Medium,High,0,0,0,0,4,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +98,12,2,0,4,0,0,0,5.5,Medium,High,0,0,0,0,4,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +99,12,3,0,4,0,0,2,5,Medium,High,0,0,0,2,2,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +100,12,4,0,4,0,0,2,6,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +101,12,5,0,4,0,0,2,5.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +102,12,6,0,4,0,0,4,4.5,Medium,High,0,0,0,0,2,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +103,12,7,0,4,0,0,0,5.5,Medium,High,0,0,0,0,2,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +104,13,0,0,2,0,0,4,4.5,Medium,High,0,0,0,0,4,-1,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +105,13,1,0,4,0,0,0,5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +106,13,2,0,4,0,0,0,5,Medium,High,0,0,0,0,4,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +107,13,3,0,2,0,0,2,4.5,Medium,High,0,0,0,1,4,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +108,13,4,0,4,0,0,2,6,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +109,13,5,0,4,0,0,4,4,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +110,13,6,0,4,0,0,0,5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +111,13,7,0,4,-1,0,0,5,Medium,High,0,0,0,0,4,-1,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +112,14,0,0,4,0,0,0,5,Medium,High,0,0,0,4,0,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +113,14,1,0,4,0,0,2,4.5,Medium,High,0,0,0,0,2,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +114,14,2,0,4,0,0,0,5,Medium,High,0,0,0,0,4,0,1,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +115,14,3,0,4,0,0,0,5,Medium,High,0,0,0,1,4,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +116,14,4,0,4,0,0,4,4.5,Medium,High,0,0,0,0,2,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +117,14,5,0,4,0,0,2,5.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +118,14,6,0,4,0,0,0,5.5,Medium,High,0,0,0,0,4,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +119,14,7,0,4,0,0,0,5,Medium,High,0,0,0,1,4,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +120,15,0,0,4,0,0,2,5.5,Medium,High,0,0,0,0,4,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +121,15,1,0,4,0,0,0,5.5,Medium,High,0,0,0,0,4,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +122,15,2,0,4,0,0,0,5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +123,15,3,0,4,0,0,0,5.5,Medium,High,0,0,0,0,4,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +124,15,4,0,4,-1,0,0,5,Medium,High,0,0,0,0,4,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +125,15,5,0,4,0,0,0,5,Medium,High,0,0,0,0,4,-1,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +126,15,6,0,4,0,0,0,4.5,Medium,High,0,0,0,0,4,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +127,15,7,0,4,0,0,0,5.5,Medium,High,0,0,0,0,2,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +128,16,0,0,2,0,0,2,4.5,Medium,High,0,0,0,0,2,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +129,16,1,0,4,0,0,0,5,Medium,High,0,0,0,0,4,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +130,16,2,0,4,0,0,0,5.5,Medium,High,0,0,0,0,4,0,1,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +131,16,3,0,4,0,0,2,4.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +132,16,4,0,4,0,0,0,5.5,Medium,High,0,0,0,0,2,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +133,16,5,0,2,0,0,2,5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +134,16,6,0,4,0,0,0,6.5,Medium,High,0,0,0,0,2,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +135,16,7,0,4,0,0,2,5,Medium,High,0,0,0,0,4,0,1,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +136,17,0,0,4,0,0,0,5.5,Medium,High,0,0,0,0,4,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +137,17,1,0,4,0,0,0,5.5,Medium,High,0,0,0,0,4,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +138,17,2,0,4,0,0,0,5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +139,17,3,0,4,0,0,0,5.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +140,17,4,1,4,0,0,0,5.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +141,17,5,0,4,0,0,0,5.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +142,17,6,0,4,0,0,2,4.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +143,17,7,0,4,0,0,2,5,Medium,High,0,0,0,1,4,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +144,18,0,0,4,0,0,2,4.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +145,18,1,0,4,0,0,2,5,Medium,High,0,0,0,0,2,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +146,18,2,0,4,0,0,0,5.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +147,18,3,0,4,0,0,2,5,Medium,High,0,0,0,0,2,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +148,18,4,0,2,0,0,0,7,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +149,18,5,0,2,0,0,2,5.5,Medium,High,0,0,0,0,2,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +150,18,6,0,4,0,0,2,5.5,Medium,High,0,0,0,0,2,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +151,18,7,0,4,0,0,4,4,Medium,High,0,0,0,0,2,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +152,19,0,0,2,0,0,0,5.5,Medium,High,0,0,0,0,4,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +153,19,1,0,4,0,0,2,5.5,Medium,High,0,0,0,0,2,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +154,19,2,0,4,0,0,0,5,Medium,High,0,0,0,0,4,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +155,19,3,0,4,0,0,-2,6,Medium,High,0,0,0,0,4,-1,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +156,19,4,0,4,0,0,0,5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +157,19,5,0,4,0,0,0,4.5,Medium,High,0,0,0,0,2,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +158,19,6,0,4,0,0,2,4.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +159,19,7,0,4,0,0,0,5,Medium,High,0,0,0,0,4,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +160,20,0,0,4,0,0,2,5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +161,20,1,0,2,0,0,2,5,Medium,High,0,0,0,0,2,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +162,20,2,0,4,0,0,4,4.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +163,20,3,0,4,0,0,0,5.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +164,20,4,0,2,0,0,2,5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +165,20,5,0,4,0,0,2,5.5,Medium,High,0,0,0,0,2,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +166,20,6,0,4,0,0,4,4.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +167,20,7,0,4,0,0,2,5.5,Medium,High,0,0,0,0,2,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +168,21,0,0,4,0,0,0,5.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +169,21,1,0,4,-1,0,0,6,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +170,21,2,0,4,0,0,0,5.5,Medium,High,0,0,0,0,4,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +171,21,3,0,4,0,0,0,5.5,Medium,High,0,0,0,0,2,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +172,21,4,0,4,0,0,2,4.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +173,21,5,0,4,0,0,2,4.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +174,21,6,0,2,0,0,2,5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +175,21,7,0,4,0,0,2,4.5,Medium,High,0,0,0,0,2,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +176,22,0,0,4,0,0,4,5,Medium,High,0,0,0,0,2,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +177,22,1,0,4,0,0,2,5.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +178,22,2,0,4,0,0,2,5.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +179,22,3,0,4,-1,0,4,5.5,Medium,High,0,0,0,0,2,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +180,22,4,0,4,0,0,4,4.5,Medium,High,0,0,0,0,2,-1,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +181,22,5,0,4,0,0,4,4.5,Medium,High,0,0,0,0,2,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +182,22,6,0,4,0,0,4,5,Medium,High,0,0,0,0,4,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +183,22,7,0,4,0,0,4,5,Medium,High,0,0,0,0,2,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +184,23,0,0,2,0,0,2,6,Medium,High,0,0,0,0,2,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +185,23,1,0,4,0,0,4,4.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +186,23,2,0,4,0,0,2,6,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +187,23,3,0,4,0,0,0,6,Medium,High,0,0,0,0,4,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +188,23,4,0,4,0,0,2,5,Medium,High,0,0,0,0,2,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +189,23,5,0,4,0,0,2,5,Medium,High,0,0,0,0,2,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +190,23,6,0,4,0,0,2,5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +191,23,7,0,4,0,0,4,5.5,Medium,High,0,0,0,0,6,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +192,24,0,0,4,0,0,2,5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +193,24,1,0,2,0,0,2,5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +194,24,2,0,4,0,0,2,4.5,Medium,High,0,0,0,1,2,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +195,24,3,0,4,0,0,0,5.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +196,24,4,0,4,0,0,4,4.5,Medium,High,0,0,0,0,2,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +197,24,5,0,4,0,0,2,5,Medium,High,0,0,0,0,2,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +198,24,6,0,4,0,0,2,4.5,Medium,High,0,0,0,0,4,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +199,24,7,0,4,0,0,2,4,Medium,High,0,0,0,0,4,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +200,25,0,0,4,0,0,0,5.5,Medium,High,0,0,0,0,4,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +201,25,1,0,4,0,0,0,5,Medium,High,0,0,0,0,4,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +202,25,2,0,4,0,0,2,4.5,Medium,High,0,0,0,0,4,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +203,25,3,0,4,0,0,2,5,Medium,High,0,0,0,0,4,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +204,25,4,0,4,0,0,0,5.5,Medium,High,0,0,0,0,2,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +205,25,5,0,4,0,0,0,5,Medium,High,0,0,0,1,4,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +206,25,6,0,4,0,0,2,5,Medium,High,0,0,0,0,4,-1,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +207,25,7,0,4,0,0,2,5,Medium,High,0,0,0,0,2,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +208,26,0,0,4,0,0,2,5.5,Medium,High,0,0,0,0,4,0,-1,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +209,26,1,0,4,0,0,2,5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +210,26,2,0,4,0,0,0,5,Medium,High,0,0,0,0,4,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +211,26,3,0,4,0,0,2,4.5,Medium,High,0,0,0,0,2,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +212,26,4,0,2,0,0,2,5,Medium,High,0,0,0,0,2,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +213,26,5,0,4,0,0,0,5.5,Medium,High,0,0,0,0,2,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +214,26,6,0,4,0,0,4,3.5,Medium,High,0,0,0,0,2,-1,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +215,26,7,0,4,0,0,0,5,Medium,High,0,0,0,0,4,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +216,27,0,0,4,0,0,2,5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +217,27,1,0,4,0,0,2,6,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +218,27,2,0,4,0,0,2,5,Medium,High,0,0,0,0,4,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +219,27,3,0,4,0,0,4,5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +220,27,4,0,4,0,0,2,5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +221,27,5,0,4,0,0,4,4.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +222,27,6,0,2,0,0,0,6,Medium,High,0,0,0,0,4,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +223,27,7,0,4,0,0,2,5.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +224,28,0,0,4,0,0,0,5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +225,28,1,0,4,0,0,2,4.5,Medium,High,0,0,0,2,2,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +226,28,2,0,4,0,0,0,4.5,Medium,High,0,0,0,0,4,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +227,28,3,0,4,0,0,2,5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +228,28,4,0,4,0,0,2,4.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +229,28,5,0,2,0,0,2,5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +230,28,6,0,2,0,0,2,4.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +231,28,7,0,4,0,0,2,5,Medium,High,0,0,0,0,4,0,0,0,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +232,29,0,0,4,0,0,4,4,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +233,29,1,0,4,0,0,4,5.5,Medium,High,0,0,0,0,4,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +234,29,2,0,4,0,0,2,5,Medium,High,0,0,0,0,2,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +235,29,3,0,4,0,0,2,5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +236,29,4,0,4,0,0,2,5,Medium,High,0,0,0,0,2,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +237,29,5,0,4,0,0,4,5.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +238,29,6,0,4,0,0,2,5,Medium,High,0,0,0,0,2,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +239,29,7,0,4,0,0,2,5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +240,30,0,0,4,0,0,2,4.5,Medium,High,0,0,0,0,2,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +241,30,1,0,4,0,0,2,5.5,Medium,High,0,0,0,0,2,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +242,30,2,0,4,0,0,2,5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +243,30,3,0,2,0,0,2,6,Medium,High,0,0,0,0,2,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +244,30,4,0,4,0,0,2,5,Medium,High,0,0,0,0,4,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +245,30,5,0,4,0,0,4,5,Medium,High,0,0,0,0,4,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +246,30,6,0,4,0,0,4,4.5,Medium,High,0,0,0,0,4,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +247,30,7,0,4,0,0,4,5,Medium,High,0,0,0,0,2,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +248,31,0,0,4,0,0,4,4.5,Medium,High,0,0,0,0,4,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +249,31,1,0,4,0,-1,2,5.5,Medium,High,0,0,0,0,4,0,1,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +250,31,2,0,4,0,0,2,4.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +251,31,3,0,4,0,0,4,4.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +252,31,4,0,4,-1,0,4,5.5,Medium,High,0,0,0,0,4,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +253,31,5,0,4,0,0,4,6,Medium,High,0,0,0,0,4,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +254,31,6,0,4,0,0,2,5,Medium,High,0,0,0,0,4,-1,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +255,31,7,0,4,0,0,2,5.5,Medium,High,0,0,0,0,4,0,0,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +256,32,0,0,4,0,0,4,4.5,Medium,High,0,0,0,0,4,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +257,32,1,0,4,0,0,2,5.5,Medium,High,0,0,0,0,4,0,1,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 diff --git a/device/supermicro/x86_64-supermicro_sse_t7132s-r0/CSV/TL7_RJ45.csv b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/CSV/TL7_RJ45.csv new file mode 100755 index 000000000000..342eef997698 --- /dev/null +++ b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/CSV/TL7_RJ45.csv @@ -0,0 +1,7 @@ +VERSION,CABLE TYPE,VENDOR,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +1.2,RJ45,GENERIC,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,SPEED,ENCODING,,,,,,,,,,SPEED,ENCODING,,,,,,,,,,,,,,SPEED,ENCODING,,,,,, +,,,50G/400G,PAM4,,,,,,,,,,25G/100G,NRZ,,,,,,,,,,,,,,10G/40G,NRZ,,,,,, +index,Front Port,lane,TX_EQ_ATTN,TX_EQ_PRE1,TX_EQ_PRE2,TX_EQ_PRE3,TX_EQ_POST,Optical Module CTLE,RX_EQ_COARSE_TUNE_EFFORT_50G,RX_EQ_FINE_TUNE_EFFORT_50G,RX_GAINSHAPE1,RX_GAINSHAPE2,LINK_TRAINING,TX_EQ_ATTN,TX_EQ_PRE1,TX_EQ_PRE2,TX_EQ_PRE3,TX_EQ_POST,Optical Module CTLE,RX_GAINSHAPE1,RX_GAINSHAPE2,RX_AGC_TARGET,RX_EYE_DISQUALIFY_THRESHOLD_25G,RX_EQ_COARSE_TUNE_EFFORT_25G,RX_EQ_FINE_TUNE_EFFORT_25G,SD_RESET_THRESHOLD,SD_RESET_25G,LINK_TRAINING,TX_EQ_ATTN,TX_EQ_PRE1,TX_EQ_PRE2,TX_EQ_PRE3,TX_EQ_POST,RX_GAINSHAPE1,RX_GAINSHAPE2,LINK_TRAINING +256,32,0,0,4,0,0,4,4.5,Medium,High,0,2,0,0,4,0,0,4,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 +257,32,1,0,4,0,0,2,5.5,Medium,High,0,2,0,0,4,0,1,2,4,0,0,100,100,LOW,LOW,NA,FALSE,0,0,0,0,0,0,0,0,0 diff --git a/device/supermicro/x86_64-supermicro_sse_t7132s-r0/Supermicro_sse_t7132s/buffers.json.j2 b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/Supermicro_sse_t7132s/buffers.json.j2 new file mode 100755 index 000000000000..9b95afc21f81 --- /dev/null +++ b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/Supermicro_sse_t7132s/buffers.json.j2 @@ -0,0 +1,167 @@ +{# Default values which will be used if no actual configura available #} +{% set default_cable = '40m' %} +{% set mgmt_port_name = ['Ethernet256','Ethernet257'] %} + +{# Port configuration to cable length look-up table #} +{# Each record describes mapping of DUT (DUT port) role and neighbor role to cable length #} +{# Roles described in the minigraph #} +{% set ports2cable = { + 'torrouter_server' : '5m', + 'leafrouter_torrouter' : '40m', + 'spinerouter_leafrouter' : '300m' + } +%} + +{%- macro cable_length(port_name) %} + {%- set cable_len = [] %} + {%- for local_port in DEVICE_NEIGHBOR %} + {%- if local_port == port_name %} + {%- if DEVICE_NEIGHBOR_METADATA is defined and DEVICE_NEIGHBOR_METADATA[DEVICE_NEIGHBOR[local_port].name] %} + {%- set neighbor = DEVICE_NEIGHBOR_METADATA[DEVICE_NEIGHBOR[local_port].name] %} + {%- set neighbor_role = neighbor.type %} + {%- set roles1 = switch_role + '_' + neighbor_role %} + {%- set roles2 = neighbor_role + '_' + switch_role %} + {%- set roles1 = roles1 | lower %} + {%- set roles2 = roles2 | lower %} + {%- if roles1 in ports2cable %} + {%- if cable_len.append(ports2cable[roles1]) %}{% endif %} + {%- elif roles2 in ports2cable %} + {%- if cable_len.append(ports2cable[roles2]) %}{% endif %} + {%- endif %} + {%- endif %} + {%- endif %} + {%- endfor %} + {%- if cable_len -%} + {{ cable_len.0 }} + {%- else %} + {%- if switch_role.lower() == 'torrouter' %} + {%- for local_port in VLAN_MEMBER %} + {%- if local_port[1] == port_name %} + {%- set roles3 = switch_role + '_' + 'server' %} + {%- set roles3 = roles3 | lower %} + {%- if roles3 in ports2cable %} + {%- if cable_len.append(ports2cable[roles3]) %}{% endif %} + {%- endif %} + {%- endif %} + {%- endfor %} + {%- if cable_len -%} + {{ cable_len.0 }} + {%- else -%} + {{ default_cable }} + {%- endif %} + {%- else -%} + {{ default_cable }} + {%- endif %} + {%- endif %} +{%- endmacro %} + +{%- if DEVICE_METADATA is defined %} +{%- set switch_role = DEVICE_METADATA['localhost']['type'] %} +{%- endif -%} + +{% set port_names_list = [] %} +{% for port in PORT %} + {% if port not in mgmt_port_name %} + {%- if port_names_list.append(port) %}{% endif %} + {% endif %} +{% endfor %} +{% set port_names = port_names_list | join(',') -%} + +{ + "CABLE_LENGTH": { + "AZURE": { + {% for port in PORT %} + {% if port not in mgmt_port_name %} + {% set cable = cable_length(port) -%} + "{{ port }}": "{{ cable }}"{%- if not loop.last -%},{% endif %} + {% endif %} + {% endfor %} + } + }, + "BUFFER_POOL": { + "ingress_lossless_pool": { + "size": "51691264", + "type": "ingress", + "mode": "dynamic", + "xoff": "17708800" + }, + "lossy_pool": { + "size": "18874368", + "type": "egress", + "mode": "dynamic", + "xoff": "0" + }, + "egress_lossless_pool": { + "size": "70565632", + "type": "egress", + "mode": "static" + } + }, + "BUFFER_PROFILE": { + "ingress_lossless_profile": { + "pool":"ingress_lossless_pool", + "xoff":"38816", + "size":"1518", + "dynamic_th":"1", + "xon_offset":"9408" + }, + "egress_lossless_profile": { + "pool":"ingress_lossless_pool", + "size":"0", + "static_th":"10243072" + }, + "ingress_lossy_profile": { + "pool":"lossy_pool", + "size":"0", + "static_th":"10243072" + }, + "egress_lossy_profile": { + "pool":"lossy_pool", + "size":"1518", + "dynamic_th":"2" + } + }, + "BUFFER_PG": { +{% for port in port_names_list %} + "{{ port }}|3-4": { + {% set cable = cable_length(port) -%} + "profile" : "pg_lossless_400000_{{ cable }}_profile" + }, +{% endfor %} +{% for port in port_names_list %} + "{{ port }}|0": { + "profile" : "ingress_lossy_profile" + }, +{% endfor %} +{% for port in port_names_list %} + "{{ port }}|1-2": { + "profile" : "ingress_lossy_profile" + }, +{% endfor %} +{% for port in port_names_list %} + "{{ port }}|5-7": { + "profile" : "ingress_lossy_profile" + }{% if not loop.last %},{% endif %} + +{% endfor %} + }, + + "BUFFER_QUEUE": { +{% for port in port_names_list %} + "{{ port }}|3-4": { + "profile" : "egress_lossless_profile" + }, +{% endfor %} +{% for port in port_names_list %} + "{{ port }}|0-2": { + "profile" : "egress_lossy_profile" + }, +{% endfor %} +{% for port in port_names_list %} + "{{ port }}|5-7": { + "profile" : "egress_lossy_profile" + }{% if not loop.last %},{% endif %} + +{% endfor %} + } +} diff --git a/device/supermicro/x86_64-supermicro_sse_t7132s-r0/Supermicro_sse_t7132s/buffers_defaults_def_lossy.j2 b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/Supermicro_sse_t7132s/buffers_defaults_def_lossy.j2 new file mode 100644 index 000000000000..8b1291ac2674 --- /dev/null +++ b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/Supermicro_sse_t7132s/buffers_defaults_def_lossy.j2 @@ -0,0 +1,45 @@ +{% set mgmt_port_name = ['Ethernet256','Ethernet257'] %} +{% set port_names_list = [] %} +{% for port in PORT %} + {% if port not in mgmt_port_name %} + {%- if port_names_list.append(port) %}{% endif %} + {% endif %} +{% endfor %} +{% set port_names = port_names_list | join(',') -%} + +{ + "BUFFER_POOL": { + "lossy_pool": { + "size": "61458432", + "type": "egress", + "mode": "dynamic", + "xoff": "0" + } + }, + "BUFFER_PROFILE": { + "ingress_lossy_profile": { + "pool":"lossy_pool", + "size":"0", + "static_th":"10243072" + }, + "egress_lossy_profile": { + "pool":"lossy_pool", + "size":"1518", + "dynamic_th":"2" + } + }, + "BUFFER_PG": { +{% for port in port_names_list %} + "{{ port }}|0-7": { + "profile" : "ingress_lossy_profile" + }{% if not loop.last %},{% endif %} +{% endfor %} + }, + "BUFFER_QUEUE": { +{% for port in port_names_list %} + "{{ port }}|0-7": { + "profile" : "egress_lossy_profile" + }{% if not loop.last %},{% endif %} +{% endfor %} + } +} diff --git a/device/supermicro/x86_64-supermicro_sse_t7132s-r0/Supermicro_sse_t7132s/buffers_defaults_t1.j2 b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/Supermicro_sse_t7132s/buffers_defaults_t1.j2 new file mode 100755 index 000000000000..9b95afc21f81 --- /dev/null +++ b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/Supermicro_sse_t7132s/buffers_defaults_t1.j2 @@ -0,0 +1,167 @@ +{# Default values which will be used if no actual configura available #} +{% set default_cable = '40m' %} +{% set mgmt_port_name = ['Ethernet256','Ethernet257'] %} + +{# Port configuration to cable length look-up table #} +{# Each record describes mapping of DUT (DUT port) role and neighbor role to cable length #} +{# Roles described in the minigraph #} +{% set ports2cable = { + 'torrouter_server' : '5m', + 'leafrouter_torrouter' : '40m', + 'spinerouter_leafrouter' : '300m' + } +%} + +{%- macro cable_length(port_name) %} + {%- set cable_len = [] %} + {%- for local_port in DEVICE_NEIGHBOR %} + {%- if local_port == port_name %} + {%- if DEVICE_NEIGHBOR_METADATA is defined and DEVICE_NEIGHBOR_METADATA[DEVICE_NEIGHBOR[local_port].name] %} + {%- set neighbor = DEVICE_NEIGHBOR_METADATA[DEVICE_NEIGHBOR[local_port].name] %} + {%- set neighbor_role = neighbor.type %} + {%- set roles1 = switch_role + '_' + neighbor_role %} + {%- set roles2 = neighbor_role + '_' + switch_role %} + {%- set roles1 = roles1 | lower %} + {%- set roles2 = roles2 | lower %} + {%- if roles1 in ports2cable %} + {%- if cable_len.append(ports2cable[roles1]) %}{% endif %} + {%- elif roles2 in ports2cable %} + {%- if cable_len.append(ports2cable[roles2]) %}{% endif %} + {%- endif %} + {%- endif %} + {%- endif %} + {%- endfor %} + {%- if cable_len -%} + {{ cable_len.0 }} + {%- else %} + {%- if switch_role.lower() == 'torrouter' %} + {%- for local_port in VLAN_MEMBER %} + {%- if local_port[1] == port_name %} + {%- set roles3 = switch_role + '_' + 'server' %} + {%- set roles3 = roles3 | lower %} + {%- if roles3 in ports2cable %} + {%- if cable_len.append(ports2cable[roles3]) %}{% endif %} + {%- endif %} + {%- endif %} + {%- endfor %} + {%- if cable_len -%} + {{ cable_len.0 }} + {%- else -%} + {{ default_cable }} + {%- endif %} + {%- else -%} + {{ default_cable }} + {%- endif %} + {%- endif %} +{%- endmacro %} + +{%- if DEVICE_METADATA is defined %} +{%- set switch_role = DEVICE_METADATA['localhost']['type'] %} +{%- endif -%} + +{% set port_names_list = [] %} +{% for port in PORT %} + {% if port not in mgmt_port_name %} + {%- if port_names_list.append(port) %}{% endif %} + {% endif %} +{% endfor %} +{% set port_names = port_names_list | join(',') -%} + +{ + "CABLE_LENGTH": { + "AZURE": { + {% for port in PORT %} + {% if port not in mgmt_port_name %} + {% set cable = cable_length(port) -%} + "{{ port }}": "{{ cable }}"{%- if not loop.last -%},{% endif %} + {% endif %} + {% endfor %} + } + }, + "BUFFER_POOL": { + "ingress_lossless_pool": { + "size": "51691264", + "type": "ingress", + "mode": "dynamic", + "xoff": "17708800" + }, + "lossy_pool": { + "size": "18874368", + "type": "egress", + "mode": "dynamic", + "xoff": "0" + }, + "egress_lossless_pool": { + "size": "70565632", + "type": "egress", + "mode": "static" + } + }, + "BUFFER_PROFILE": { + "ingress_lossless_profile": { + "pool":"ingress_lossless_pool", + "xoff":"38816", + "size":"1518", + "dynamic_th":"1", + "xon_offset":"9408" + }, + "egress_lossless_profile": { + "pool":"ingress_lossless_pool", + "size":"0", + "static_th":"10243072" + }, + "ingress_lossy_profile": { + "pool":"lossy_pool", + "size":"0", + "static_th":"10243072" + }, + "egress_lossy_profile": { + "pool":"lossy_pool", + "size":"1518", + "dynamic_th":"2" + } + }, + "BUFFER_PG": { +{% for port in port_names_list %} + "{{ port }}|3-4": { + {% set cable = cable_length(port) -%} + "profile" : "pg_lossless_400000_{{ cable }}_profile" + }, +{% endfor %} +{% for port in port_names_list %} + "{{ port }}|0": { + "profile" : "ingress_lossy_profile" + }, +{% endfor %} +{% for port in port_names_list %} + "{{ port }}|1-2": { + "profile" : "ingress_lossy_profile" + }, +{% endfor %} +{% for port in port_names_list %} + "{{ port }}|5-7": { + "profile" : "ingress_lossy_profile" + }{% if not loop.last %},{% endif %} + +{% endfor %} + }, + + "BUFFER_QUEUE": { +{% for port in port_names_list %} + "{{ port }}|3-4": { + "profile" : "egress_lossless_profile" + }, +{% endfor %} +{% for port in port_names_list %} + "{{ port }}|0-2": { + "profile" : "egress_lossy_profile" + }, +{% endfor %} +{% for port in port_names_list %} + "{{ port }}|5-7": { + "profile" : "egress_lossy_profile" + }{% if not loop.last %},{% endif %} + +{% endfor %} + } +} diff --git a/device/supermicro/x86_64-supermicro_sse_t7132s-r0/Supermicro_sse_t7132s/config_32x400G_sse_t7132s.yaml b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/Supermicro_sse_t7132s/config_32x400G_sse_t7132s.yaml new file mode 100644 index 000000000000..9c84910a1f4d --- /dev/null +++ b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/Supermicro_sse_t7132s/config_32x400G_sse_t7132s.yaml @@ -0,0 +1,440 @@ +ifcs: + options: + log_level: "info" +nodes: +- node_id: "0" + options: + sd_low_power_mode_global_default: "true" + sku: "configs/sku/innovium.77700_A" + netdev: + - auto_create: "no" + multi_interface: "yes" + pcie_attn: "10, 0, 0, 0" + pcie_post: "10, 0, 0, 0" + pcie_pre1: "0, 0, 0, 0" + buffer_management_mode: "api_driven" + wred_cr_ip_proto_list: "17" + cr_assignment_mode: "1" + max_lossless_tc: "2" + ilpm_enable: "1" + ecn_stats_enable: "1" + forward_profile: "IFCS_FORWARD_PROFILE_ID_PROFILE_E" + led_cfg_sck_rate: "0x5" + led_refresh_precliff_timer: "0x18eec2" + led_refresh_cliff_timer: "0x15e" + led_cfg_pic_stream_mode: "1" + led_refresh_tmr_ctl_enable: "1" + txring: + - txring_id: "0" + desc_count: "1024" + prio: "1" + netdev: "true" + - txring_id: "1" + desc_count: "1024" + prio: "1" + netdev: "true" + - txring_id: "2" + desc_count: "1024" + prio: "1" + netdev: "true" + - txring_id: "3" + desc_count: "1024" + prio: "1" + netdev: "true" + rxring: + - rxring_id: "0" + desc_count: "1024" + prio: "1" + netdev: "true" + queues: "0, 3, 6, 9, 12, 15, 18, 21, 24, 27, 30, 33, 36, 39" + - rxring_id: "1" + desc_count: "1024" + prio: "1" + netdev: "true" + queues: "1, 4, 7, 10, 13, 16, 19, 22, 25, 28, 31, 34, 37, 40" + - rxring_id: "2" + desc_count: "1024" + prio: "1" + netdev: "true" + queues: "2, 5, 8, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 47" + - rxring_id: "3" + desc_count: "1024" + prio: "1" + queues: "42, 43, 44, 45, 46" + sys_clk: "1720" + ifc_clk: "1200" + mac_clk: "1340" + + devports: + - id: "0" + sysport: "1000" + type: "cpu" + - fec: "KPFEC" + id: "241" + lanes: "0:8" + serdes_group: "30" + speed: "400G" + sysport: "241" + type: "eth" + - fec: "KPFEC" + id: "249" + lanes: "0:8" + serdes_group: "31" + speed: "400G" + sysport: "249" + type: "eth" + - fec: "KPFEC" + id: "225" + lanes: "0:8" + serdes_group: "28" + speed: "400G" + sysport: "225" + type: "eth" + - fec: "KPFEC" + id: "233" + lanes: "0:8" + serdes_group: "29" + speed: "400G" + sysport: "233" + type: "eth" + - fec: "KPFEC" + id: "217" + lanes: "0:8" + serdes_group: "27" + speed: "400G" + sysport: "217" + type: "eth" + - fec: "KPFEC" + id: "209" + lanes: "0:8" + serdes_group: "26" + speed: "400G" + sysport: "209" + type: "eth" + - fec: "KPFEC" + id: "201" + lanes: "0:8" + serdes_group: "25" + speed: "400G" + sysport: "201" + type: "eth" + - fec: "KPFEC" + id: "193" + lanes: "0:8" + serdes_group: "24" + speed: "400G" + sysport: "193" + type: "eth" + - fec: "KPFEC" + id: "185" + lanes: "0:8" + serdes_group: "23" + speed: "400G" + sysport: "185" + type: "eth" + - fec: "KPFEC" + id: "177" + lanes: "0:8" + serdes_group: "22" + speed: "400G" + sysport: "177" + type: "eth" + - fec: "KPFEC" + id: "169" + lanes: "0:8" + serdes_group: "21" + speed: "400G" + sysport: "169" + type: "eth" + - fec: "KPFEC" + id: "161" + lanes: "0:8" + serdes_group: "20" + speed: "400G" + sysport: "161" + type: "eth" + - fec: "KPFEC" + id: "153" + lanes: "0:8" + serdes_group: "19" + speed: "400G" + sysport: "153" + type: "eth" + - fec: "KPFEC" + id: "145" + lanes: "0:8" + serdes_group: "18" + speed: "400G" + sysport: "145" + type: "eth" + - fec: "KPFEC" + id: "137" + lanes: "0:8" + serdes_group: "17" + speed: "400G" + sysport: "137" + type: "eth" + - fec: "KPFEC" + id: "129" + lanes: "0:8" + serdes_group: "16" + speed: "400G" + sysport: "129" + type: "eth" + - fec: "KPFEC" + id: "121" + lanes: "0:8" + serdes_group: "15" + speed: "400G" + sysport: "121" + type: "eth" + - fec: "KPFEC" + id: "113" + lanes: "0:8" + serdes_group: "14" + speed: "400G" + sysport: "113" + type: "eth" + - fec: "KPFEC" + id: "105" + lanes: "0:8" + serdes_group: "13" + speed: "400G" + sysport: "105" + type: "eth" + - fec: "KPFEC" + id: "97" + lanes: "0:8" + serdes_group: "12" + speed: "400G" + sysport: "97" + type: "eth" + - fec: "KPFEC" + id: "89" + lanes: "0:8" + serdes_group: "11" + speed: "400G" + sysport: "89" + type: "eth" + - fec: "KPFEC" + id: "81" + lanes: "0:8" + serdes_group: "10" + speed: "400G" + sysport: "81" + type: "eth" + - fec: "KPFEC" + id: "73" + lanes: "0:8" + serdes_group: "9" + speed: "400G" + sysport: "73" + type: "eth" + - fec: "KPFEC" + id: "65" + lanes: "0:8" + serdes_group: "8" + speed: "400G" + sysport: "65" + type: "eth" + - fec: "KPFEC" + id: "57" + lanes: "0:8" + serdes_group: "7" + speed: "400G" + sysport: "57" + type: "eth" + - fec: "KPFEC" + id: "49" + lanes: "0:8" + serdes_group: "6" + speed: "400G" + sysport: "49" + type: "eth" + - fec: "KPFEC" + id: "41" + lanes: "0:8" + serdes_group: "5" + speed: "400G" + sysport: "41" + type: "eth" + - fec: "KPFEC" + id: "33" + lanes: "0:8" + serdes_group: "4" + speed: "400G" + sysport: "33" + type: "eth" + - fec: "KPFEC" + id: "25" + lanes: "0:8" + serdes_group: "3" + speed: "400G" + sysport: "25" + type: "eth" + - fec: "KPFEC" + id: "17" + lanes: "0:8" + serdes_group: "2" + speed: "400G" + sysport: "17" + type: "eth" + - fec: "KPFEC" + id: "9" + lanes: "0:8" + serdes_group: "1" + speed: "400G" + sysport: "9" + type: "eth" + - fec: "KPFEC" + id: "1" + lanes: "0:8" + serdes_group: "0" + speed: "400G" + sysport: "1" + type: "eth" + - fec: "NONE" + id: "257" + lanes: "0:1" + serdes_group: "32" + sysport: "257" + type: "mgmt 0" + - fec: "NONE" + id: "258" + lanes: "1:1" + serdes_group: "32" + sysport: "258" + type: "mgmt 1" + isg: + - id: "0" + tx_polarity: "10100000" + rx_polarity: "11111011" + lane_swap: "37250416" + - id: "1" + tx_polarity: "01010011" + rx_polarity: "00000100" + lane_swap: "52407613" + - id: "2" + tx_polarity: "11010001" + rx_polarity: "01111100" + lane_swap: "06153427" + - id: "3" + tx_polarity: "00100000" + rx_polarity: "10001001" + lane_swap: "74501263" + - id: "4" + tx_polarity: "10100000" + rx_polarity: "11101000" + lane_swap: "05471632" + - id: "5" + tx_polarity: "00010100" + rx_polarity: "00111100" + lane_swap: "72604351" + - id: "6" + tx_polarity: "11011001" + rx_polarity: "00011001" + lane_swap: "16340725" + - id: "7" + tx_polarity: "11010000" + rx_polarity: "11000010" + lane_swap: "70615324" + - id: "8" + tx_polarity: "00111101" + rx_polarity: "11011000" + lane_swap: "25074613" + - id: "9" + tx_polarity: "00001010" + rx_polarity: "01000011" + lane_swap: "32706451" + - id: "10" + tx_polarity: "00100010" + rx_polarity: "01001011" + lane_swap: "07162543" + - id: "11" + tx_polarity: "01101001" + rx_polarity: "11110001" + lane_swap: "41706253" + - id: "12" + tx_polarity: "11001000" + rx_polarity: "11000011" + lane_swap: "07136524" + - id: "13" + tx_polarity: "01100001" + rx_polarity: "10010000" + lane_swap: "73506412" + - id: "14" + tx_polarity: "01010001" + rx_polarity: "10110110" + lane_swap: "26143705" + - id: "15" + tx_polarity: "00001000" + rx_polarity: "11101100" + lane_swap: "51602437" + - id: "16" + tx_polarity: "00010000" + rx_polarity: "11101011" + lane_swap: "45076312" + - id: "17" + tx_polarity: "01011000" + rx_polarity: "00000000" + lane_swap: "50642371" + - id: "18" + tx_polarity: "01010100" + rx_polarity: "00011001" + lane_swap: "07436125" + - id: "19" + tx_polarity: "00011010" + rx_polarity: "01001011" + lane_swap: "61734250" + - id: "20" + tx_polarity: "00111110" + rx_polarity: "10011100" + lane_swap: "04275631" + - id: "21" + tx_polarity: "10110100" + rx_polarity: "01110110" + lane_swap: "41620573" + - id: "22" + tx_polarity: "01100110" + rx_polarity: "10010000" + lane_swap: "17240635" + - id: "23" + tx_polarity: "01010000" + rx_polarity: "11110101" + lane_swap: "52704631" + - id: "24" + tx_polarity: "00010001" + rx_polarity: "10100100" + lane_swap: "16253704" + - id: "25" + tx_polarity: "01000101" + rx_polarity: "00010000" + lane_swap: "53607241" + - id: "26" + tx_polarity: "00110101" + rx_polarity: "11101110" + lane_swap: "16074325" + - id: "27" + tx_polarity: "10000111" + rx_polarity: "01011110" + lane_swap: "75604231" + - id: "28" + tx_polarity: "01010100" + rx_polarity: "01010101" + lane_swap: "70614235" + - id: "29" + tx_polarity: "01010001" + rx_polarity: "01000001" + lane_swap: "24610537" + - id: "30" + tx_polarity: "01101011" + rx_polarity: "01010011" + lane_swap: "70614352" + - id: "31" + tx_polarity: "01101001" + rx_polarity: "10100000" + lane_swap: "34250716" + - id: "32" + tx_polarity: "00000000" + rx_polarity: "00000000" + lane_swap: "01234567" diff --git a/device/supermicro/x86_64-supermicro_sse_t7132s-r0/Supermicro_sse_t7132s/innovium.77700_A b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/Supermicro_sse_t7132s/innovium.77700_A new file mode 100644 index 000000000000..ec13307805e1 --- /dev/null +++ b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/Supermicro_sse_t7132s/innovium.77700_A @@ -0,0 +1,60 @@ +sku: innovium.77700_A + +device_id: 0x1b58 + +# Hardware constraint information +hardware: + num_ibs: 6 + ib_active: 0,1,2,3,4,5 + + ports_per_ib: 32, 32, 32, 32, 20, 20 + recirc_port_num: 32, 32, 32, 32, 32, 32 + cpu_port_num: 33 + cpu_port_ib: 0 + mgmt_port_num: 33 + mgmt_port_ibs: 1,2 + + pics_per_ib: 6, 7, 6, 5, 5, 5 + pic_ports_per_pic: 8 + max_serdes_speed: 50 + + num_shared_pics: 2 + + isg [0-4]: + ib: 0 + pic_id: [0-4] + + isg [5-9]: + ib: 5 + pic_id: [0-4] + + isg [10-14]: + ib: 1 + pic_id: [0-4] + + isg [16-20]: + ib: 3 + pic_id: [0-4] + + isg [21-25]: + ib: 4 + pic_id: [0-4] + + isg [26-30]: + ib: 2 + pic_id: [0-4] + + isg 15: + mode: 8:0 + ib: 1 + pic_id: 5 + + isg 31: + mode: 8:0 + ib: 0 + pic_id: 5 + + isg 32: + mode: 1:1 + ib: 1, 2 + pic_id: 6 diff --git a/device/supermicro/x86_64-supermicro_sse_t7132s-r0/Supermicro_sse_t7132s/innovium.77700_B b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/Supermicro_sse_t7132s/innovium.77700_B new file mode 100644 index 000000000000..57ba52cbc3bc --- /dev/null +++ b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/Supermicro_sse_t7132s/innovium.77700_B @@ -0,0 +1,60 @@ +sku: innovium.77700_B + +device_id: 0x1b58 + +# Hardware constraint information +hardware: + num_ibs: 6 + ib_active: 0,1,2,3,4,5 + + ports_per_ib: 32, 32, 32, 32, 20, 20 + recirc_port_num: 32, 32, 32, 32, 32, 32 + cpu_port_num: 33 + cpu_port_ib: 0 + mgmt_port_num: 33 + mgmt_port_ibs: 1,2 + + pics_per_ib: 6, 7, 7, 6, 5, 5 + pic_ports_per_pic: 8 + max_serdes_speed: 50 + + num_shared_pics: 2 + + isg [0-4]: + ib: 0 + pic_id: [0-4] + + isg [5-9]: + ib: 5 + pic_id: [0-4] + + isg [10-14]: + ib: 1 + pic_id: [0-4] + + isg [16-20]: + ib: 3 + pic_id: [0-4] + + isg [21-25]: + ib: 4 + pic_id: [0-4] + + isg [26-30]: + ib: 2 + pic_id: [0-4] + + isg 15: + mode: 4:4 + ib: 1, 3 + pic_id: 5 + + isg 31: + mode: 4:4 + ib: 0, 2 + pic_id: 5 + + isg 32: + mode: 1:1 + ib: 1, 2 + pic_id: 6 diff --git a/device/supermicro/x86_64-supermicro_sse_t7132s-r0/Supermicro_sse_t7132s/ivm.sai.config.yaml b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/Supermicro_sse_t7132s/ivm.sai.config.yaml new file mode 100755 index 000000000000..e896723a03c3 --- /dev/null +++ b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/Supermicro_sse_t7132s/ivm.sai.config.yaml @@ -0,0 +1,10 @@ +IFCS_INIT_FILE : "/usr/share/sonic/hwsku/config_32x400G_sse_t7132s.yaml" +IFCS_SKU_FILE : "/usr/share/sonic/hwsku/innovium.77700_A" +IFCS_INNO_CLI_PORT : "9999" +IFCS_TARGET : "device" +ULIMIT : "65536" +INNOVIUM_DIR : "/innovium" +PYTHONPATH : "$INNOVIUM_DIR:$INNOVIUM_DIR/cmds:$INNOVIUM_DIR/scripts:$INNOVIUM_DIR/test/:$INNOVIUM_DIR/test/utils:$INNOVIUM_DIR/utils:$INNOVIUM_DIR/pyctypes:$INNOVIUM_DIR/ifcs_cmds:$INNOVIUM_DIR/testutil:$INNOVIUM_DIR/isai_cmds" +PLATFORM_LIBRARY: "/usr/share/sonic/platform/lib_ivm_serdes_pltfm.so" +IVM_SAI_DATAPATH_CONFIG_FILE: "/usr/share/sonic/hwsku/ivm.sai.datapath.config.yaml" +IVM_SAI_PARAM_A0008: "32" diff --git a/device/supermicro/x86_64-supermicro_sse_t7132s-r0/Supermicro_sse_t7132s/ivm.sai.datapath.config.yaml b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/Supermicro_sse_t7132s/ivm.sai.datapath.config.yaml new file mode 100644 index 000000000000..891b0b3e2834 --- /dev/null +++ b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/Supermicro_sse_t7132s/ivm.sai.datapath.config.yaml @@ -0,0 +1,9 @@ +ISAI_PARAM_P0_0_LS : "4608 4608 4608 4608 2880 2880" +ISAI_PARAM_P0_1_LS : "2226 1946 1946 1890 1218 1218" +ISAI_PARAM_P0_1_ALS : "434 154 154 98 98 98" +ISAI_PARAM_P1_0_LS : "1536 1536 1536 1536 960 960" +ISAI_PARAM_P1_0_LL : "3072 3072 3072 3072 1920 1920" +ISAI_PARAM_P1_1_LS : "1778 1498 1498 1442 938 938" +ISAI_PARAM_P1_1_LL : "2478 2478 2478 2478 2478 2478" +ISAI_PARAM_P1_1_ALS : "434 154 154 98 98 98" +ISAI_PARAM_P1_1_ALL : "126 126 126 126 126 126" diff --git a/device/supermicro/x86_64-supermicro_sse_t7132s-r0/Supermicro_sse_t7132s/pg_profile_lookup.ini b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/Supermicro_sse_t7132s/pg_profile_lookup.ini new file mode 100644 index 000000000000..0d881737cfa1 --- /dev/null +++ b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/Supermicro_sse_t7132s/pg_profile_lookup.ini @@ -0,0 +1,22 @@ +# PG lossless profiles. +# speed cable size xon xoff threshold xon_offset + 25000 5m 1518 0 15680 1 9408 + 50000 5m 1518 0 21248 1 9408 + 100000 5m 1518 0 34624 1 9408 + 200000 5m 1518 0 62368 1 9408 + 400000 5m 1518 0 117536 1 9408 + 25000 40m 1518 0 16928 1 9408 + 50000 40m 1518 0 23392 1 9408 + 100000 40m 1518 0 38816 1 9408 + 200000 40m 1518 0 71904 1 9408 + 400000 40m 1518 0 135520 1 9408 + 25000 100m 1518 0 18848 1 9408 + 50000 100m 1518 0 27264 1 9408 + 100000 100m 1518 0 46496 1 9408 + 200000 100m 1518 0 87168 1 9408 + 400000 100m 1518 0 166688 1 9408 + 25000 300m 1518 0 25184 1 9408 + 50000 300m 1518 0 40128 1 9408 + 100000 300m 1518 0 72384 1 9408 + 200000 300m 1518 0 138112 1 9408 + 400000 300m 1518 0 268640 1 9408 diff --git a/device/supermicro/x86_64-supermicro_sse_t7132s-r0/Supermicro_sse_t7132s/port_config.ini b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/Supermicro_sse_t7132s/port_config.ini new file mode 100755 index 000000000000..950038f8a8bb --- /dev/null +++ b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/Supermicro_sse_t7132s/port_config.ini @@ -0,0 +1,35 @@ +# name lanes alias speed index mtu fec +Ethernet0 241,242,243,244,245,246,247,248 Eth1 400000 1 9126 rs +Ethernet8 249,250,251,252,253,254,255,256 Eth2 400000 2 9126 rs +Ethernet16 225,226,227,228,229,230,231,232 Eth3 400000 3 9126 rs +Ethernet24 233,234,235,236,237,238,239,240 Eth4 400000 4 9126 rs +Ethernet32 217,218,219,220,221,222,223,224 Eth5 400000 5 9126 rs +Ethernet40 209,210,211,212,213,214,215,216 Eth6 400000 6 9126 rs +Ethernet48 201,202,203,204,205,206,207,208 Eth7 400000 7 9126 rs +Ethernet56 193,194,195,196,197,198,199,200 Eth8 400000 8 9126 rs +Ethernet64 185,186,187,188,189,190,191,192 Eth9 400000 9 9126 rs +Ethernet72 177,178,179,180,181,182,183,184 Eth10 400000 10 9126 rs +Ethernet80 169,170,171,172,173,174,175,176 Eth11 400000 11 9126 rs +Ethernet88 161,162,163,164,165,166,167,168 Eth12 400000 12 9126 rs +Ethernet96 153,154,155,156,157,158,159,160 Eth13 400000 13 9126 rs +Ethernet104 145,146,147,148,149,150,151,152 Eth14 400000 14 9126 rs +Ethernet112 137,138,139,140,141,142,143,144 Eth15 400000 15 9126 rs +Ethernet120 129,130,131,132,133,134,135,136 Eth16 400000 16 9126 rs +Ethernet128 121,122,123,124,125,126,127,128 Eth17 400000 17 9126 rs +Ethernet136 113,114,115,116,117,118,119,120 Eth18 400000 18 9126 rs +Ethernet144 105,106,107,108,109,110,111,112 Eth19 400000 19 9126 rs +Ethernet152 97,98,99,100,101,102,103,104 Eth20 400000 20 9126 rs +Ethernet160 89,90,91,92,93,94,95,96 Eth21 400000 21 9126 rs +Ethernet168 81,82,83,84,85,86,87,88 Eth22 400000 22 9126 rs +Ethernet176 73,74,75,76,77,78,79,80 Eth23 400000 23 9126 rs +Ethernet184 65,66,67,68,69,70,71,72 Eth24 400000 24 9126 rs +Ethernet192 57,58,59,60,61,62,63,64 Eth25 400000 25 9126 rs +Ethernet200 49,50,51,52,53,54,55,56 Eth26 400000 26 9126 rs +Ethernet208 41,42,43,44,45,46,47,48 Eth27 400000 27 9126 rs +Ethernet216 33,34,35,36,37,38,39,40 Eth28 400000 28 9126 rs +Ethernet224 25,26,27,28,29,30,31,32 Eth29 400000 29 9126 rs +Ethernet232 17,18,19,20,21,22,23,24 Eth30 400000 30 9126 rs +Ethernet240 9,10,11,12,13,14,15,16 Eth31 400000 31 9126 rs +Ethernet248 1,2,3,4,5,6,7,8 Eth32 400000 32 9126 rs +Ethernet256 257 Eth33 10000 33 9126 none +Ethernet257 258 Eth34 10000 34 9126 none diff --git a/device/supermicro/x86_64-supermicro_sse_t7132s-r0/Supermicro_sse_t7132s/qos.json.j2 b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/Supermicro_sse_t7132s/qos.json.j2 new file mode 100755 index 000000000000..34f7413d9522 --- /dev/null +++ b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/Supermicro_sse_t7132s/qos.json.j2 @@ -0,0 +1,195 @@ +{% set mgmt_port_name = ['Ethernet256','Ethernet257'] %} +{% set port_names_list = [] %} +{% for port in PORT %} + {% if port not in mgmt_port_name %} + {%- if port_names_list.append(port) %}{% endif %} + {% endif %} +{% endfor %} +{% set port_names = port_names_list | join(',') -%} + + +{ + "TC_TO_QUEUE_MAP":{ + "AZURE":{ + "0":"0", + "1":"1", + "2":"2", + "3":"3", + "4":"4", + "5":"5", + "6":"6", + "7":"7" + } + }, + "MAP_PFC_PRIORITY_TO_QUEUE": { + "AZURE": { + "0": "0", + "1": "1", + "2": "2", + "3": "3", + "4": "4", + "5": "5", + "6": "6", + "7": "7" + } + }, + "TC_TO_PRIORITY_GROUP_MAP": { + "AZURE": { + "0": "0", + "1": "0", + "2": "0", + "3": "3", + "4": "4", + "5": "0", + "6": "0", + "7": "0" + } + }, + "DSCP_TO_TC_MAP": { + "AZURE": { + "0" : "1", + "1" : "1", + "2" : "1", + "3" : "3", + "4" : "4", + "5" : "2", + "6" : "1", + "7" : "1", + "8" : "0", + "9" : "1", + "10": "1", + "11": "1", + "12": "1", + "13": "1", + "14": "1", + "15": "1", + "16": "1", + "17": "1", + "18": "1", + "19": "1", + "20": "1", + "21": "1", + "22": "1", + "23": "1", + "24": "1", + "25": "1", + "26": "1", + "27": "1", + "28": "1", + "29": "1", + "30": "1", + "31": "1", + "32": "1", + "33": "1", + "34": "1", + "35": "1", + "36": "1", + "37": "1", + "38": "1", + "39": "1", + "40": "1", + "41": "1", + "42": "1", + "43": "1", + "44": "1", + "45": "1", + "46": "5", + "47": "1", + "48": "6", + "49": "1", + "50": "1", + "51": "1", + "52": "1", + "53": "1", + "54": "1", + "55": "1", + "56": "1", + "57": "1", + "58": "1", + "59": "1", + "60": "1", + "61": "1", + "62": "1", + "63": "1" + } + }, + "SCHEDULER": { + "scheduler.0": { + "type" : "DWRR", + "weight": "1" + }, + "scheduler.1": { + "type" : "DWRR", + "weight": "1" + } + }, + "QUEUE": { +{% for port in port_names_list %} + "{{ port }}|3": { + "scheduler" : "scheduler.1", + "wred_profile" : "AZURE_LOSSLESS" + }, +{% endfor %} +{% for port in port_names_list %} + "{{ port }}|4": { + "scheduler" : "scheduler.1", + "wred_profile" : "AZURE_LOSSLESS" + }, +{% endfor %} +{% for port in port_names_list %} + "{{ port }}|0": { + "scheduler": "scheduler.0" + }, +{% endfor %} +{% for port in port_names_list %} + "{{ port }}|1": { + "scheduler": "scheduler.0" + }, +{% endfor %} +{% for port in port_names_list %} + "{{ port }}|2": { + "scheduler": "scheduler.0" + }, +{% endfor %} +{% for port in port_names_list %} + "{{ port }}|5": { + "scheduler": "scheduler.0" + }, +{% endfor %} +{% for port in port_names_list %} + "{{ port }}|6": { + "scheduler": "scheduler.0" + }{% if not loop.last %},{% endif %} + +{% endfor %} + }, + "PORT_QOS_MAP": { +{% for port in port_names_list %} + "{{ port }}": { + "tc_to_pg_map": "AZURE", + "tc_to_queue_map": "AZURE", + "dscp_to_tc_map": "AZURE", + "pfc_to_queue_map": "AZURE", + "pfc_enable": "3,4" + }{% if not loop.last %},{% endif %} + +{% endfor %} + }, + "WRED_PROFILE": { + "AZURE_LOSSLESS" : { + "wred_green_enable" : "true", + "wred_yellow_enable" : "true", + "wred_red_enable" : "true", + "ecn" : "ecn_all", + "green_max_threshold" : "2097152", + "green_min_threshold" : "1048576", + "yellow_max_threshold" : "2097152", + "yellow_min_threshold" : "1048576", + "red_max_threshold" : "2097152", + "red_min_threshold" : "1048576", + "green_drop_probability" : "5", + "yellow_drop_probability": "5", + "red_drop_probability" : "5" + } + } +} diff --git a/device/supermicro/x86_64-supermicro_sse_t7132s-r0/Supermicro_sse_t7132s/qos_defaults_def_lossy.j2 b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/Supermicro_sse_t7132s/qos_defaults_def_lossy.j2 new file mode 100644 index 000000000000..a390d37b4ffb --- /dev/null +++ b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/Supermicro_sse_t7132s/qos_defaults_def_lossy.j2 @@ -0,0 +1,124 @@ +{% set mgmt_port_name = ['Ethernet256','Ethernet257'] %} +{% set port_names_list = [] %} +{% for port in PORT %} + {% if port not in mgmt_port_name %} + {%- if port_names_list.append(port) %}{% endif %} + {% endif %} +{% endfor %} +{% set port_names = port_names_list | join(',') -%} + + +{ + "TC_TO_QUEUE_MAP":{ + "AZURE":{ + "0":"0", + "1":"1", + "2":"2", + "3":"3", + "4":"4", + "5":"5", + "6":"6", + "7":"7" + } + }, + "TC_TO_PRIORITY_GROUP_MAP": { + "AZURE": { + "0": "0", + "1": "0", + "2": "0", + "3": "1", + "4": "2", + "5": "0", + "6": "0", + "7": "0" + } + }, + "DSCP_TO_TC_MAP": { + "AZURE": { + "0":"0", + "1":"0", + "2":"0", + "3":"0", + "4":"0", + "5":"0", + "6":"0", + "7":"0", + "8":"0", + "9":"0", + "10":"0", + "11":"0", + "12":"0", + "13":"0", + "14":"0", + "15":"0", + "16":"0", + "17":"0", + "18":"0", + "19":"0", + "20":"0", + "21":"0", + "22":"0", + "23":"0", + "24":"0", + "25":"0", + "26":"0", + "27":"0", + "28":"0", + "29":"0", + "30":"0", + "31":"0", + "32":"0", + "33":"0", + "34":"0", + "35":"0", + "36":"0", + "37":"0", + "38":"0", + "39":"0", + "40":"0", + "41":"0", + "42":"0", + "43":"0", + "44":"0", + "45":"0", + "46":"0", + "47":"0", + "48":"0", + "49":"0", + "50":"0", + "51":"0", + "52":"0", + "53":"0", + "54":"0", + "55":"0", + "56":"0", + "57":"0", + "58":"0", + "59":"0", + "60":"0", + "61":"0", + "62":"0", + "63":"0" + } + }, + "PORT_QOS_MAP": { +{% for port in port_names_list %} + "{{ port }}": { + "tc_to_pg_map": "AZURE", + "tc_to_queue_map": "AZURE", + "dscp_to_tc_map": "AZURE" + }{% if not loop.last %},{% endif %} + +{% endfor %} + }, + "SCHEDULER": { + "scheduler.7": { + "type": "STRICT" + } + }, + "QUEUE": { + "{{ port_names }}|7": { + "scheduler": "[SCHEDULER|scheduler.7]" + } + } +} diff --git a/device/supermicro/x86_64-supermicro_sse_t7132s-r0/Supermicro_sse_t7132s/qos_defaults_t1.j2 b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/Supermicro_sse_t7132s/qos_defaults_t1.j2 new file mode 100644 index 000000000000..34f7413d9522 --- /dev/null +++ b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/Supermicro_sse_t7132s/qos_defaults_t1.j2 @@ -0,0 +1,195 @@ +{% set mgmt_port_name = ['Ethernet256','Ethernet257'] %} +{% set port_names_list = [] %} +{% for port in PORT %} + {% if port not in mgmt_port_name %} + {%- if port_names_list.append(port) %}{% endif %} + {% endif %} +{% endfor %} +{% set port_names = port_names_list | join(',') -%} + + +{ + "TC_TO_QUEUE_MAP":{ + "AZURE":{ + "0":"0", + "1":"1", + "2":"2", + "3":"3", + "4":"4", + "5":"5", + "6":"6", + "7":"7" + } + }, + "MAP_PFC_PRIORITY_TO_QUEUE": { + "AZURE": { + "0": "0", + "1": "1", + "2": "2", + "3": "3", + "4": "4", + "5": "5", + "6": "6", + "7": "7" + } + }, + "TC_TO_PRIORITY_GROUP_MAP": { + "AZURE": { + "0": "0", + "1": "0", + "2": "0", + "3": "3", + "4": "4", + "5": "0", + "6": "0", + "7": "0" + } + }, + "DSCP_TO_TC_MAP": { + "AZURE": { + "0" : "1", + "1" : "1", + "2" : "1", + "3" : "3", + "4" : "4", + "5" : "2", + "6" : "1", + "7" : "1", + "8" : "0", + "9" : "1", + "10": "1", + "11": "1", + "12": "1", + "13": "1", + "14": "1", + "15": "1", + "16": "1", + "17": "1", + "18": "1", + "19": "1", + "20": "1", + "21": "1", + "22": "1", + "23": "1", + "24": "1", + "25": "1", + "26": "1", + "27": "1", + "28": "1", + "29": "1", + "30": "1", + "31": "1", + "32": "1", + "33": "1", + "34": "1", + "35": "1", + "36": "1", + "37": "1", + "38": "1", + "39": "1", + "40": "1", + "41": "1", + "42": "1", + "43": "1", + "44": "1", + "45": "1", + "46": "5", + "47": "1", + "48": "6", + "49": "1", + "50": "1", + "51": "1", + "52": "1", + "53": "1", + "54": "1", + "55": "1", + "56": "1", + "57": "1", + "58": "1", + "59": "1", + "60": "1", + "61": "1", + "62": "1", + "63": "1" + } + }, + "SCHEDULER": { + "scheduler.0": { + "type" : "DWRR", + "weight": "1" + }, + "scheduler.1": { + "type" : "DWRR", + "weight": "1" + } + }, + "QUEUE": { +{% for port in port_names_list %} + "{{ port }}|3": { + "scheduler" : "scheduler.1", + "wred_profile" : "AZURE_LOSSLESS" + }, +{% endfor %} +{% for port in port_names_list %} + "{{ port }}|4": { + "scheduler" : "scheduler.1", + "wred_profile" : "AZURE_LOSSLESS" + }, +{% endfor %} +{% for port in port_names_list %} + "{{ port }}|0": { + "scheduler": "scheduler.0" + }, +{% endfor %} +{% for port in port_names_list %} + "{{ port }}|1": { + "scheduler": "scheduler.0" + }, +{% endfor %} +{% for port in port_names_list %} + "{{ port }}|2": { + "scheduler": "scheduler.0" + }, +{% endfor %} +{% for port in port_names_list %} + "{{ port }}|5": { + "scheduler": "scheduler.0" + }, +{% endfor %} +{% for port in port_names_list %} + "{{ port }}|6": { + "scheduler": "scheduler.0" + }{% if not loop.last %},{% endif %} + +{% endfor %} + }, + "PORT_QOS_MAP": { +{% for port in port_names_list %} + "{{ port }}": { + "tc_to_pg_map": "AZURE", + "tc_to_queue_map": "AZURE", + "dscp_to_tc_map": "AZURE", + "pfc_to_queue_map": "AZURE", + "pfc_enable": "3,4" + }{% if not loop.last %},{% endif %} + +{% endfor %} + }, + "WRED_PROFILE": { + "AZURE_LOSSLESS" : { + "wred_green_enable" : "true", + "wred_yellow_enable" : "true", + "wred_red_enable" : "true", + "ecn" : "ecn_all", + "green_max_threshold" : "2097152", + "green_min_threshold" : "1048576", + "yellow_max_threshold" : "2097152", + "yellow_min_threshold" : "1048576", + "red_max_threshold" : "2097152", + "red_min_threshold" : "1048576", + "green_drop_probability" : "5", + "yellow_drop_probability": "5", + "red_drop_probability" : "5" + } + } +} diff --git a/device/supermicro/x86_64-supermicro_sse_t7132s-r0/Supermicro_sse_t7132s/sai.profile b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/Supermicro_sse_t7132s/sai.profile new file mode 100644 index 000000000000..aba4fc81fb17 --- /dev/null +++ b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/Supermicro_sse_t7132s/sai.profile @@ -0,0 +1 @@ +SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/ivm.sai.config.yaml diff --git a/device/supermicro/x86_64-supermicro_sse_t7132s-r0/default_sku b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/default_sku new file mode 100755 index 000000000000..8feb806f2f82 --- /dev/null +++ b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/default_sku @@ -0,0 +1 @@ +Supermicro_sse_t7132s t1 diff --git a/device/supermicro/x86_64-supermicro_sse_t7132s-r0/fast-reboot_plugin b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/fast-reboot_plugin new file mode 100755 index 000000000000..6bc65e0edfa2 --- /dev/null +++ b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/fast-reboot_plugin @@ -0,0 +1,2 @@ +#!/bin/bash +/usr/local/bin/sysledctl.py reboot diff --git a/device/supermicro/x86_64-supermicro_sse_t7132s-r0/installer.conf b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/installer.conf new file mode 100755 index 000000000000..1eb3e9e4949b --- /dev/null +++ b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/installer.conf @@ -0,0 +1,4 @@ +CONSOLE_PORT=0x3f8 +CONSOLE_DEV=0 +CONSOLE_SPEED=115200 +ONIE_PLATFORM_EXTRA_CMDLINE_LINUX="intel_iommu=off pcie_aspm=off usbcore.old_scheme_first=1" diff --git a/device/supermicro/x86_64-supermicro_sse_t7132s-r0/lib_ivm_serdes_pltfm.so b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/lib_ivm_serdes_pltfm.so new file mode 100755 index 000000000000..651e66a19ff5 Binary files /dev/null and b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/lib_ivm_serdes_pltfm.so differ diff --git a/device/supermicro/x86_64-supermicro_sse_t7132s-r0/pcie.yaml b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/pcie.yaml new file mode 100755 index 000000000000..2b8dce2e0635 --- /dev/null +++ b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/pcie.yaml @@ -0,0 +1,453 @@ +- bus: '00' + dev: '00' + fn: '0' + id: 6f00 + name: 'Host bridge: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D DMI2 + (rev 03)' +- bus: '00' + dev: '01' + fn: '0' + id: 6f02 + name: 'PCI bridge: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D PCI + Express Root Port 1 (rev 03)' +- bus: '00' + dev: '01' + fn: '1' + id: 6f03 + name: 'PCI bridge: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D PCI + Express Root Port 1 (rev 03)' +- bus: '00' + dev: '02' + fn: '0' + id: 6f04 + name: 'PCI bridge: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D PCI + Express Root Port 2 (rev 03)' +- bus: '00' + dev: '02' + fn: '2' + id: 6f06 + name: 'PCI bridge: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D PCI + Express Root Port 2 (rev 03)' +- bus: '00' + dev: '03' + fn: '0' + id: 6f08 + name: 'PCI bridge: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D PCI + Express Root Port 3 (rev 03)' +- bus: '00' + dev: '03' + fn: '3' + id: 6f0b + name: 'PCI bridge: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon D PCI + Express Root Port 3 (rev 03)' +- bus: '00' + dev: '05' + fn: '0' + id: 6f28 + name: 'System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D Map/VTd_Misc/System Management (rev 03)' +- bus: '00' + dev: '05' + fn: '1' + id: 6f29 + name: 'System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D IIO Hot Plug (rev 03)' +- bus: '00' + dev: '05' + fn: '2' + id: 6f2a + name: 'System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D IIO RAS/Control Status/Global Errors (rev 03)' +- bus: '00' + dev: '14' + fn: '0' + id: 8c31 + name: 'USB controller: Intel Corporation 8 Series/C220 Series Chipset Family USB + xHCI (rev 05)' +- bus: '00' + dev: '16' + fn: '0' + id: 8c3a + name: 'Communication controller: Intel Corporation 8 Series/C220 Series Chipset + Family MEI Controller #1 (rev 04)' +- bus: '00' + dev: '16' + fn: '1' + id: 8c3b + name: 'Communication controller: Intel Corporation 8 Series/C220 Series Chipset + Family MEI Controller #2 (rev 04)' +- bus: '00' + dev: 1a + fn: '0' + id: 8c2d + name: 'USB controller: Intel Corporation 8 Series/C220 Series Chipset Family USB + EHCI #2 (rev 05)' +- bus: '00' + dev: 1c + fn: '0' + id: 8c10 + name: 'PCI bridge: Intel Corporation 8 Series/C220 Series Chipset Family PCI Express + Root Port #1 (rev d5)' +- bus: '00' + dev: 1c + fn: '3' + id: 8c16 + name: 'PCI bridge: Intel Corporation 8 Series/C220 Series Chipset Family PCI Express + Root Port #4 (rev d5)' +- bus: '00' + dev: 1d + fn: '0' + id: 8c26 + name: 'USB controller: Intel Corporation 8 Series/C220 Series Chipset Family USB + EHCI #1 (rev 05)' +- bus: '00' + dev: 1f + fn: '0' + id: 8c54 + name: 'ISA bridge: Intel Corporation C224 Series Chipset Family Server Standard + SKU LPC Controller (rev 05)' +- bus: '00' + dev: 1f + fn: '2' + id: 8c02 + name: 'SATA controller: Intel Corporation 8 Series/C220 Series Chipset Family 6-port + SATA Controller 1 [AHCI mode] (rev 05)' +- bus: '00' + dev: 1f + fn: '3' + id: 8c22 + name: 'SMBus: Intel Corporation 8 Series/C220 Series Chipset Family SMBus Controller + (rev 05)' +- bus: '00' + dev: 1f + fn: '6' + id: 8c24 + name: 'Signal processing controller: Intel Corporation 8 Series Chipset Family Thermal + Management Controller (rev 05)' +- bus: '03' + dev: '00' + fn: '0' + id: 6f50 + name: 'System peripheral: Intel Corporation Xeon Processor D Family QuickData Technology + Register DMA Channel 0' +- bus: '03' + dev: '00' + fn: '1' + id: 6f51 + name: 'System peripheral: Intel Corporation Xeon Processor D Family QuickData Technology + Register DMA Channel 1' +- bus: '03' + dev: '00' + fn: '2' + id: 6f52 + name: 'System peripheral: Intel Corporation Xeon Processor D Family QuickData Technology + Register DMA Channel 2' +- bus: '03' + dev: '00' + fn: '3' + id: 6f53 + name: 'System peripheral: Intel Corporation Xeon Processor D Family QuickData Technology + Register DMA Channel 3' +- bus: '05' + dev: '00' + fn: '0' + id: 1b58 + name: 'Ethernet controller: Device 1d98:1b58 (rev 10)' +- bus: '06' + dev: '00' + fn: '0' + id: '9110' + name: 'Bridge: Asix Electronics Corporation Device 9110' +- bus: '07' + dev: '00' + fn: '0' + id: '1533' + name: 'Ethernet controller: Intel Corporation I210 Gigabit Network Connection (rev + 03)' +- bus: 08 + dev: '00' + fn: '0' + id: '1150' + name: 'PCI bridge: ASPEED Technology, Inc. AST1150 PCI-to-PCI Bridge (rev 06)' +- bus: 09 + dev: '00' + fn: '0' + id: '2000' + name: 'VGA compatible controller: ASPEED Technology, Inc. ASPEED Graphics Family + (rev 52)' +- bus: ff + dev: 0b + fn: '0' + id: 6f81 + name: 'System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D R3 QPI Link 0/1 (rev 03)' +- bus: ff + dev: 0b + fn: '1' + id: 6f36 + name: 'Performance counters: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D R3 QPI Link 0/1 (rev 03)' +- bus: ff + dev: 0b + fn: '2' + id: 6f37 + name: 'Performance counters: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D R3 QPI Link 0/1 (rev 03)' +- bus: ff + dev: 0b + fn: '3' + id: 6f76 + name: 'System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D R3 QPI Link Debug (rev 03)' +- bus: ff + dev: 0c + fn: '0' + id: 6fe0 + name: 'System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D Caching Agent (rev 03)' +- bus: ff + dev: 0c + fn: '1' + id: 6fe1 + name: 'System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D Caching Agent (rev 03)' +- bus: ff + dev: 0c + fn: '2' + id: 6fe2 + name: 'System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D Caching Agent (rev 03)' +- bus: ff + dev: 0c + fn: '3' + id: 6fe3 + name: 'System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D Caching Agent (rev 03)' +- bus: ff + dev: 0f + fn: '0' + id: 6ff8 + name: 'System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D Caching Agent (rev 03)' +- bus: ff + dev: 0f + fn: '4' + id: 6ffc + name: 'System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D Caching Agent (rev 03)' +- bus: ff + dev: 0f + fn: '5' + id: 6ffd + name: 'System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D Caching Agent (rev 03)' +- bus: ff + dev: 0f + fn: '6' + id: 6ffe + name: 'System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D Caching Agent (rev 03)' +- bus: ff + dev: '10' + fn: '0' + id: 6f1d + name: 'System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D R2PCIe Agent (rev 03)' +- bus: ff + dev: '10' + fn: '1' + id: 6f34 + name: 'Performance counters: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D R2PCIe Agent (rev 03)' +- bus: ff + dev: '10' + fn: '5' + id: 6f1e + name: 'System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D Ubox (rev 03)' +- bus: ff + dev: '10' + fn: '6' + id: 6f7d + name: 'Performance counters: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D Ubox (rev 03)' +- bus: ff + dev: '10' + fn: '7' + id: 6f1f + name: 'System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D Ubox (rev 03)' +- bus: ff + dev: '12' + fn: '0' + id: 6fa0 + name: 'System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D Home Agent 0 (rev 03)' +- bus: ff + dev: '12' + fn: '1' + id: 6f30 + name: 'Performance counters: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D Home Agent 0 (rev 03)' +- bus: ff + dev: '13' + fn: '0' + id: 6fa8 + name: 'System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D Memory Controller 0 - Target Address/Thermal/RAS (rev 03)' +- bus: ff + dev: '13' + fn: '1' + id: 6f71 + name: 'System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D Memory Controller 0 - Target Address/Thermal/RAS (rev 03)' +- bus: ff + dev: '13' + fn: '2' + id: 6faa + name: 'System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D Memory Controller 0 - Channel Target Address Decoder (rev 03)' +- bus: ff + dev: '13' + fn: '3' + id: 6fab + name: 'System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D Memory Controller 0 - Channel Target Address Decoder (rev 03)' +- bus: ff + dev: '13' + fn: '4' + id: 6fac + name: 'System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D Memory Controller 0 - Channel Target Address Decoder (rev 03)' +- bus: ff + dev: '13' + fn: '5' + id: 6fad + name: 'System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D Memory Controller 0 - Channel Target Address Decoder (rev 03)' +- bus: ff + dev: '13' + fn: '6' + id: 6fae + name: 'System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D DDRIO Channel 0/1 Broadcast (rev 03)' +- bus: ff + dev: '13' + fn: '7' + id: 6faf + name: 'System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D DDRIO Global Broadcast (rev 03)' +- bus: ff + dev: '14' + fn: '0' + id: 6fb0 + name: 'System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D Memory Controller 0 - Channel 0 Thermal Control (rev 03)' +- bus: ff + dev: '14' + fn: '1' + id: 6fb1 + name: 'System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D Memory Controller 0 - Channel 1 Thermal Control (rev 03)' +- bus: ff + dev: '14' + fn: '2' + id: 6fb2 + name: 'System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D Memory Controller 0 - Channel 0 Error (rev 03)' +- bus: ff + dev: '14' + fn: '3' + id: 6fb3 + name: 'System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D Memory Controller 0 - Channel 1 Error (rev 03)' +- bus: ff + dev: '14' + fn: '4' + id: 6fbc + name: 'System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D DDRIO Channel 0/1 Interface (rev 03)' +- bus: ff + dev: '14' + fn: '5' + id: 6fbd + name: 'System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D DDRIO Channel 0/1 Interface (rev 03)' +- bus: ff + dev: '14' + fn: '6' + id: 6fbe + name: 'System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D DDRIO Channel 0/1 Interface (rev 03)' +- bus: ff + dev: '14' + fn: '7' + id: 6fbf + name: 'System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D DDRIO Channel 0/1 Interface (rev 03)' +- bus: ff + dev: '15' + fn: '0' + id: 6fb4 + name: 'System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D Memory Controller 0 - Channel 2 Thermal Control (rev 03)' +- bus: ff + dev: '15' + fn: '1' + id: 6fb5 + name: 'System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D Memory Controller 0 - Channel 3 Thermal Control (rev 03)' +- bus: ff + dev: '15' + fn: '2' + id: 6fb6 + name: 'System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D Memory Controller 0 - Channel 2 Error (rev 03)' +- bus: ff + dev: '15' + fn: '3' + id: 6fb7 + name: 'System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D Memory Controller 0 - Channel 3 Error (rev 03)' +- bus: ff + dev: 1e + fn: '0' + id: 6f98 + name: 'System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D Power Control Unit (rev 03)' +- bus: ff + dev: 1e + fn: '1' + id: 6f99 + name: 'System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D Power Control Unit (rev 03)' +- bus: ff + dev: 1e + fn: '2' + id: 6f9a + name: 'System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D Power Control Unit (rev 03)' +- bus: ff + dev: 1e + fn: '3' + id: 6fc0 + name: 'System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D Power Control Unit (rev 03)' +- bus: ff + dev: 1e + fn: '4' + id: 6f9c + name: 'System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D Power Control Unit (rev 03)' +- bus: ff + dev: 1f + fn: '0' + id: 6f88 + name: 'System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D Power Control Unit (rev 03)' +- bus: ff + dev: 1f + fn: '2' + id: 6f8a + name: 'System peripheral: Intel Corporation Xeon E7 v4/Xeon E5 v4/Xeon E3 v4/Xeon + D Power Control Unit (rev 03)' diff --git a/device/supermicro/x86_64-supermicro_sse_t7132s-r0/platform.json b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/platform.json new file mode 100644 index 000000000000..e28ca23c7aee --- /dev/null +++ b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/platform.json @@ -0,0 +1,238 @@ +{ + "chassis": { + "name": "Supermicro-SSE-T7132S-R0", + "components": [ + { + "name": "CPLD1" + }, + { + "name": "CPLD2" + } + ], + "fans": [ + { + "name": "FAN-1" + }, + { + "name": "FAN-2" + }, + { + "name": "FAN-3" + }, + { + "name": "FAN-4" + }, + { + "name": "FAN-5" + }, + { + "name": "FAN-6" + } + ], + "fan_drawers": [ + { + "name": "Drawer1", + "fans": [ + { + "name": "FAN-1" + } + ] + }, + { + "name": "Drawer2", + "fans": [ + { + "name": "FAN-2" + } + ] + }, + { + "name": "Drawer3", + "fans": [ + { + "name": "FAN-3" + } + ] + }, + { + "name": "Drawer4", + "fans": [ + { + "name": "FAN-4" + } + ] + }, + { + "name": "Drawer5", + "fans": [ + { + "name": "FAN-5" + } + ] + }, + { + "name": "Drawer6", + "fans": [ + { + "name": "FAN-6" + } + ] + } + ], + "psus": [ + { + "name": "PSU 1", + "fans": [ + { + "name": "PSU 1 FAN-1", + "speed": { + "controllable": false + }, + "status_led": { + "controllable": false + } + } + ] + }, + { + "name": "PSU 2", + "fans": [ + { + "name": "PSU 2 FAN-1", + "speed": { + "controllable": false + }, + "status_led": { + "controllable": false + } + } + ] + } + ], + "thermals": [ + { + "name": "CPU Temp" + }, + { + "name": "PCH Temp" + }, + { + "name": "Peripheral Temp" + }, + { + "name": "Switch Buttom-1" + }, + { + "name": "Switch Buttom-2" + }, + { + "name": "Switch Top-1" + }, + { + "name": "Switch Top-2" + }, + { + "name": "System Temp" + } + ], + "sfps": [ + { + "name": "Ethernet0" + }, + { + "name": "Ethernet8" + }, + { + "name": "Ethernet16" + }, + { + "name": "Ethernet24" + }, + { + "name": "Ethernet32" + }, + { + "name": "Ethernet40" + }, + { + "name": "Ethernet48" + }, + { + "name": "Ethernet56" + }, + { + "name": "Ethernet64" + }, + { + "name": "Ethernet72" + }, + { + "name": "Ethernet80" + }, + { + "name": "Ethernet88" + }, + { + "name": "Ethernet96" + }, + { + "name": "Ethernet104" + }, + { + "name": "Ethernet112" + }, + { + "name": "Ethernet120" + }, + { + "name": "Ethernet128" + }, + { + "name": "Ethernet136" + }, + { + "name": "Ethernet144" + }, + { + "name": "Ethernet152" + }, + { + "name": "Ethernet160" + }, + { + "name": "Ethernet168" + }, + { + "name": "Ethernet176" + }, + { + "name": "Ethernet184" + }, + { + "name": "Ethernet192" + }, + { + "name": "Ethernet200" + }, + { + "name": "Ethernet208" + }, + { + "name": "Ethernet216" + }, + { + "name": "Ethernet224" + }, + { + "name": "Ethernet232" + }, + { + "name": "Ethernet240" + }, + { + "name": "Ethernet248" + } + ] + }, + "interfaces": {} +} diff --git a/device/supermicro/x86_64-supermicro_sse_t7132s-r0/platform_asic b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/platform_asic new file mode 100644 index 000000000000..84083a7415d9 --- /dev/null +++ b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/platform_asic @@ -0,0 +1 @@ +innovium diff --git a/device/supermicro/x86_64-supermicro_sse_t7132s-r0/plugins/eeprom.py b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/plugins/eeprom.py new file mode 100644 index 000000000000..ba6a569c7104 --- /dev/null +++ b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/plugins/eeprom.py @@ -0,0 +1,20 @@ +############################################################################# +# Celestica Silverstone +# +# Platform and model specific eeprom subclass, inherits from the base class, +# and provides the followings: +# - the eeprom format definition +# - specific encoder/decoder if there is special need +############################################################################# + +try: + from sonic_eeprom import eeprom_tlvinfo +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + + +class board(eeprom_tlvinfo.TlvInfoDecoder): + + def __init__(self, name, path, cpld_root, ro): + self.eeprom_path = "/sys/class/i2c-adapter/i2c-0/0-0053/eeprom" + super(board, self).__init__(self.eeprom_path, 0, '', True) diff --git a/device/supermicro/x86_64-supermicro_sse_t7132s-r0/plugins/psuutil.py b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/plugins/psuutil.py new file mode 100644 index 000000000000..3bba2adc2063 --- /dev/null +++ b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/plugins/psuutil.py @@ -0,0 +1,84 @@ +import os.path +import subprocess +import sys +import re + +IPMI_PSU1_DATA = "docker exec -it pmon ipmitool sdr list | grep PS1 | awk -F \"|\" '{print $2}'" +IPMI_PSU2_DATA = "docker exec -it pmon ipmitool sdr list | grep PS2 | awk -F \"|\" '{print $2}'" + +try: + from sonic_psu.psu_base import PsuBase +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + + +class PsuUtil(PsuBase): + """Platform-specific PSUutil class""" + + def __init__(self): + PsuBase.__init__(self) + + def run_command(self, command): + proc = subprocess.Popen(command, shell=True, universal_newlines=True, stdout=subprocess.PIPE) + (out, err) = proc.communicate() + + if proc.returncode != 0: + sys.exit(proc.returncode) + + return out + + def get_num_psus(self): + """ + Retrieves the number of PSUs available on the device + :return: An integer, the number of PSUs available on the device + """ + return 2 + + def get_psu_status(self, index): + """ + Retrieves the oprational status of power supply unit (PSU) defined + by 1-based index + :param index: An integer, 1-based index of the PSU of which to query status + :return: Boolean, True if PSU is operating properly, False if PSU is faulty + """ + if index is None: + return False + if index == 1: + res_string = self.run_command(IPMI_PSU1_DATA) + else: + res_string = self.run_command(IPMI_PSU2_DATA) + + try: + ret_value = int(res_string, 0) + except ValueError as e: + return False + + if ret_value == 0x1: + return True + else: + return False + + def get_psu_presence(self, index): + """ + Retrieves the presence status of power supply unit (PSU) defined + by 1-based index + :param index: An integer, 1-based index of the PSU of which to query status + :return: Boolean, True if PSU is plugged, False if not + """ + if index is None: + return False + + if index == 1: + res_string = self.run_command(IPMI_PSU1_DATA) + else: + res_string = self.run_command(IPMI_PSU2_DATA) + + try: + ret_value = int(res_string, 0) + except ValueError as e: + return False + + if ret_value == 0x1 or ret_value == 0xb: + return True + else: + return False diff --git a/device/supermicro/x86_64-supermicro_sse_t7132s-r0/plugins/sfputil.py b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/plugins/sfputil.py new file mode 100644 index 000000000000..f8fb3d2744c3 --- /dev/null +++ b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/plugins/sfputil.py @@ -0,0 +1,211 @@ +# Platform-specific SFP transceiver interface for SONiC +# This plugin supports QSFP and SFP. + +try: + import time + from sonic_sfp.sfputilbase import SfpUtilBase +except ImportError as e: + raise ImportError("%s - required module not found" % str(e)) + + +class SfpUtil(SfpUtilBase): + """Platform-specific SfpUtil class""" + + PORT_START = 0 + PORT_END = 34 + QSFP_PORT_START = 0 + QSFP_PORT_END = 32 + SFP_PORT_START = 33 + SFP_PORT_END = 34 + + EEPROM_OFFSET = 11 + PORT_INFO_PATH = '/sys/class/t7132s_cpld' + + _port_name = "" + _port_to_eeprom_mapping = {} + _port_to_i2cbus_mapping = {} + _port_to_offset = [11, 30, 12, 29, 13, 28, 14, 27, 15, 34, + 16, 33, 17, 32, 18, 31, 19, 38, 20, 37, + 21, 36, 22, 35, 23, 42, 24, 41, 25, 40, + 26, 39, + 43, 44] + _global_port_pres_dict = {} + + @property + def port_start(self): + return self.PORT_START + + @property + def port_end(self): + return self.PORT_END + + @property + def qsfp_ports(self): + return [] + + @property + def qsfp_ports(self): + return list(range(self.QSFP_PORT_START, self.QSFP_PORT_END)) + + @property + def port_to_eeprom_mapping(self): + return self._port_to_eeprom_mapping + + @property + def port_to_i2cbus_mapping(self): + return self._port_to_i2cbus_mapping + + def get_port_name(self, port_num): + if port_num in self.qsfp_ports: + self._port_name = "QSFP" + str(port_num + 1) + else: + self._port_name = "SFP" + str(port_num - self.QSFP_PORT_END + 1) + return self._port_name + + def get_eeprom_dom_raw(self, port_num): + if port_num in self.qsfp_ports: + # QSFP DOM EEPROM is also at addr 0x50 and thus also stored in eeprom_ifraw + return None + else: + # Read dom eeprom at addr 0x51 + return self._read_eeprom_devid(port_num, self.DOM_EEPROM_ADDR, 256) + + def __init__(self): + # Override port_to_eeprom_mapping for class initialization + eeprom_path = '/sys/bus/i2c/devices/i2c-{0}/{0}-0050/eeprom' + + for x in range(self.PORT_START, self.PORT_END): + self.port_to_i2cbus_mapping[x] = (x + self.EEPROM_OFFSET) + self.port_to_eeprom_mapping[x] = eeprom_path.format( + self._port_to_offset[x]) + self.init_global_port_presence() + SfpUtilBase.__init__(self) + + def init_global_port_presence(self): + for port_num in range(self.port_start, (self.port_end)): + presence = self.get_presence(port_num) + if(presence): + self._global_port_pres_dict[port_num] = '1' + else: + self._global_port_pres_dict[port_num] = '0' + + def get_presence(self, port_num): + # Check for invalid port_num + if port_num not in list(range(self.port_start, self.port_end + 1)): + return False + + # Get path for access port presence status + port_name = self.get_port_name(port_num) + sysfs_filename = "qsfp_modprs" if port_num in self.qsfp_ports else "sfp_modabs" + reg_path = "/".join([self.PORT_INFO_PATH, port_name, sysfs_filename]) + + # Read status + try: + reg_file = open(reg_path) + content = reg_file.readline().rstrip() + reg_value = int(content) + except IOError as e: + print("Error: unable to open file: %s" % str(e)) + return False + + # Module present is active low + if reg_value == 0: + return True + + return False + + def get_low_power_mode(self, port_num): + # Check for invalid QSFP port_num + if port_num not in self.qsfp_ports: + return False + + try: + port_name = self.get_port_name(port_num) + reg_file = open("/".join([self.PORT_INFO_PATH, + port_name, "qsfp_lpmode"])) + except IOError as e: + print("Error: unable to open file: %s" % str(e)) + return False + + # Read status + content = reg_file.readline().rstrip() + reg_value = int(content) + # low power mode is active high + if reg_value == 0: + return False + + return True + + def set_low_power_mode(self, port_num, lpmode): + # Check for invalid QSFP port_num + if port_num not in self.qsfp_ports: + return False + + try: + port_name = self.get_port_name(port_num) + reg_file = open("/".join([self.PORT_INFO_PATH, + port_name, "qsfp_lpmode"]), "r+") + except IOError as e: + print("Error: unable to open file: %s" % str(e)) + return False + + content = hex(lpmode) + + reg_file.seek(0) + reg_file.write(content) + reg_file.close() + + return True + + def reset(self, port_num): + # Check for invalid QSFP port_num + if port_num not in self.qsfp_ports: + return False + + try: + port_name = self.get_port_name(port_num) + reg_file = open("/".join([self.PORT_INFO_PATH, + port_name, "qsfp_reset"]), "w") + except IOError as e: + print("Error: unable to open file: %s" % str(e)) + return False + + # Convert our register value back to a hex string and write back + reg_file.seek(0) + reg_file.write(hex(0)) + reg_file.close() + + # Sleep 1 second to allow it to settle + time.sleep(1) + + # Flip the bit back high and write back to the register to take port out of reset + try: + reg_file = open( + "/".join([self.PORT_INFO_PATH, port_name, "qsfp_reset"]), "w") + except IOError as e: + print("Error: unable to open file: %s" % str(e)) + return False + + reg_file.seek(0) + reg_file.write(hex(1)) + reg_file.close() + + return True + + def get_transceiver_change_event(self): + port_dict = {} + while True: + for port_num in range(self.port_start, (self.port_end + 1)): + presence = self.get_presence(port_num) + if(presence and self._global_port_pres_dict[port_num] == '0'): + self._global_port_pres_dict[port_num] = '1' + port_dict[port_num] = '1' + elif(not presence and + self._global_port_pres_dict[port_num] == '1'): + self._global_port_pres_dict[port_num] = '0' + port_dict[port_num] = '0' + + if(len(port_dict) > 0): + return True, port_dict + + time.sleep(0.5) diff --git a/device/supermicro/x86_64-supermicro_sse_t7132s-r0/plugins/ssd_util.py b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/plugins/ssd_util.py new file mode 100644 index 000000000000..3a26dbfe4388 --- /dev/null +++ b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/plugins/ssd_util.py @@ -0,0 +1,8 @@ +from sonic_platform_base.sonic_ssd.ssd_generic import SsdUtil as SsdUtilGeneric + +class SsdUtil(SsdUtilGeneric): + def parse_innodisk_info(self): + super().parse_innodisk_info() + if self.vendor_ssd_info: + # fix too lazy pattern 'Health:\s*(.+?)%?' + self.health = self._parse_re('Health:\s*(.+?)%', self.vendor_ssd_info) diff --git a/device/supermicro/x86_64-supermicro_sse_t7132s-r0/pmon_daemon_control.json b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/pmon_daemon_control.json new file mode 100644 index 000000000000..16f0755583ac --- /dev/null +++ b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/pmon_daemon_control.json @@ -0,0 +1,6 @@ +{ + "skip_ledd": true, + "skip_xcvrd": false, + "skip_psud": false, + "skip_thermalctld": false +} diff --git a/device/supermicro/x86_64-supermicro_sse_t7132s-r0/sensors.conf b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/sensors.conf new file mode 100755 index 000000000000..7c9a6321dfc0 --- /dev/null +++ b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/sensors.conf @@ -0,0 +1,2 @@ +# libsensors configuration file for Celestica Midstone-200i. +# The i2c bus portion is omit because adapter name diff --git a/device/supermicro/x86_64-supermicro_sse_t7132s-r0/system_health_monitoring_config.json b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/system_health_monitoring_config.json new file mode 100644 index 000000000000..728dcb491e75 --- /dev/null +++ b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/system_health_monitoring_config.json @@ -0,0 +1,11 @@ +{ + "services_to_ignore": [], + "devices_to_ignore": ["asic", "psu.temperature"], + "user_defined_checkers": ["python3 /usr/local/bin/health_checker_thermal.py"], + "polling_interval": 60, + "led_color": { + "fault": "red", + "normal": "green", + "booting": "green_blink" + } +} diff --git a/device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/platform_env.conf b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/thermal_policy.json similarity index 100% rename from device/ragile/x86_64-ragile_ra-b6510-48v8c-r0/platform_env.conf rename to device/supermicro/x86_64-supermicro_sse_t7132s-r0/thermal_policy.json diff --git a/device/supermicro/x86_64-supermicro_sse_t7132s-r0/topo.conf b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/topo.conf new file mode 100644 index 000000000000..795ea43143eb --- /dev/null +++ b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/topo.conf @@ -0,0 +1 @@ +t1 diff --git a/device/supermicro/x86_64-supermicro_sse_t7132s-r0/warm-reboot_plugin b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/warm-reboot_plugin new file mode 100755 index 000000000000..6bc65e0edfa2 --- /dev/null +++ b/device/supermicro/x86_64-supermicro_sse_t7132s-r0/warm-reboot_plugin @@ -0,0 +1,2 @@ +#!/bin/bash +/usr/local/bin/sysledctl.py reboot diff --git a/device/ufispace/x86_64-ufispace_s6301_56st-r0/UFISPACE-S6301-56ST/hwsku.json b/device/ufispace/x86_64-ufispace_s6301_56st-r0/UFISPACE-S6301-56ST/hwsku.json new file mode 100644 index 000000000000..4f341c2eddce --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s6301_56st-r0/UFISPACE-S6301-56ST/hwsku.json @@ -0,0 +1,221 @@ +{ + "interfaces": { + "Ethernet0": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet1": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet2": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet3": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet4": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet5": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet6": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet7": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet8": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet9": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet10": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet11": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet12": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet13": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet14": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet15": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet16": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet17": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet18": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet19": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet20": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet21": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet22": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet23": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet24": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet25": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet26": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet27": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet28": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet29": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet30": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet31": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet32": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet33": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet34": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet35": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet36": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet37": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet38": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet39": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet40": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet41": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet42": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet43": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet44": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet45": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet46": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet47": { + "default_brkout_mode": "1x1G", + "autoneg": "on" + }, + "Ethernet48": { + "default_brkout_mode": "1x10G" + }, + "Ethernet49": { + "default_brkout_mode": "1x10G" + }, + "Ethernet50": { + "default_brkout_mode": "1x10G" + }, + "Ethernet51": { + "default_brkout_mode": "1x10G" + }, + "Ethernet52": { + "default_brkout_mode": "1x10G" + }, + "Ethernet53": { + "default_brkout_mode": "1x10G" + }, + "Ethernet54": { + "default_brkout_mode": "1x10G" + }, + "Ethernet55": { + "default_brkout_mode": "1x10G" + } + } +} + diff --git a/device/ufispace/x86_64-ufispace_s6301_56st-r0/UFISPACE-S6301-56ST/sai.profile b/device/ufispace/x86_64-ufispace_s6301_56st-r0/UFISPACE-S6301-56ST/sai.profile new file mode 100644 index 000000000000..33b427a78fce --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s6301_56st-r0/UFISPACE-S6301-56ST/sai.profile @@ -0,0 +1 @@ +SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/td3-x2-s6301-56st.config.bcm diff --git a/device/ufispace/x86_64-ufispace_s6301_56st-r0/UFISPACE-S6301-56ST/td3-x2-s6301-56st.config.bcm b/device/ufispace/x86_64-ufispace_s6301_56st-r0/UFISPACE-S6301-56ST/td3-x2-s6301-56st.config.bcm new file mode 100644 index 000000000000..7bf91509ca39 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s6301_56st-r0/UFISPACE-S6301-56ST/td3-x2-s6301-56st.config.bcm @@ -0,0 +1,295 @@ +# r2, 20230713 + +sram_scan_enable=0 +stable_size=0x5500000 +tdma_timeout_usec=15000000 +tslam_timeout_usec=15000000 +sai_mdio_access_clause22=1 +sai_verify_incoming_chksum=0 +robust_hash_disable_egress_vlan=1 +robust_hash_disable_mpls=1 +robust_hash_disable_vlan=1 +port_flex_enable=1 +arl_clean_timeout_usec=15000000 +asf_mem_profile=0 +bcm_num_cos=9 +bcm_stat_flags=1 +bcm_stat_jumbo=9236 +cdma_timeout_usec=15000000 +disable_pcie_firmware_check=1 +dma_desc_timeout_usec=15000000 +fpem_mem_entries=0 +higig2_hdr_mode=1 +ifp_inports_support_enable=1 +ipv6_lpm_128b_enable=1 +l2xmsg_mode=1 +l2_mem_entries=65536 +l3_mem_entries=32768 +max_vp_lags=0 +mem_scan_enable=1 +miim_intr_enable=0 +module_64ports=1 +multicast_l2_range=4095 +multicast_l3_range=0 +os=unix + +# global setting + +pbmp_xport_xe=0x1fe00000000000000 +pbmp_xport_ge=0x00001fffffffffffe + +phy_chain_tx_lane_map_physical{25}=0x2310 +phy_chain_rx_lane_map_physical{25}=0x2310 + +phy_chain_tx_lane_map_physical{41}=0x3102 +phy_chain_rx_lane_map_physical{41}=0x3102 + +port_gmii_mode_25=1 +port_gmii_mode_26=1 +port_gmii_mode_27=1 +port_gmii_mode_28=1 +port_gmii_mode_29=1 +port_gmii_mode_30=1 +port_gmii_mode_31=1 +port_gmii_mode_32=1 + +port_gmii_mode_33=1 +port_gmii_mode_34=1 +port_gmii_mode_35=1 +port_gmii_mode_36=1 +port_gmii_mode_37=1 +port_gmii_mode_38=1 +port_gmii_mode_39=1 +port_gmii_mode_40=1 + +port_gmii_mode_41=1 +port_gmii_mode_42=1 +port_gmii_mode_43=1 +port_gmii_mode_44=1 +port_gmii_mode_45=1 +port_gmii_mode_46=1 +port_gmii_mode_47=1 +port_gmii_mode_48=1 + +# GPHY0 +portmap_1=1:1 +portmap_2=2:1 +portmap_3=3:1 +portmap_4=4:1 + +# GPHY1 +portmap_5=5:1 +portmap_6=6:1 +portmap_7=7:1 +portmap_8=8:1 + +# GPHY2 +portmap_9=9:1 +portmap_10=10:1 +portmap_11=11:1 +portmap_12=12:1 + +# GPHY3 +portmap_13=13:1 +portmap_14=14:1 +portmap_15=15:1 +portmap_16=16:1 + +# GPHY4 +portmap_17=17:1 +portmap_18=18:1 +portmap_19=19:1 +portmap_20=20:1 + +# GPHY5 +portmap_21=21:1 +portmap_22=22:1 +portmap_23=23:1 +portmap_24=24:1 + +phy_port_primary_and_offset_1.0=0x0100 +phy_port_primary_and_offset_2.0=0x0101 +phy_port_primary_and_offset_3.0=0x0102 +phy_port_primary_and_offset_4.0=0x0103 +phy_port_primary_and_offset_5.0=0x0104 +phy_port_primary_and_offset_6.0=0x0105 +phy_port_primary_and_offset_7.0=0x0106 +phy_port_primary_and_offset_8.0=0x0107 + +phy_port_primary_and_offset_9.0=0x0900 +phy_port_primary_and_offset_10.0=0x0901 +phy_port_primary_and_offset_11.0=0x0902 +phy_port_primary_and_offset_12.0=0x0903 +phy_port_primary_and_offset_13.0=0x0904 +phy_port_primary_and_offset_14.0=0x0905 +phy_port_primary_and_offset_15.0=0x0906 +phy_port_primary_and_offset_16.0=0x0907 + +phy_port_primary_and_offset_17.0=0x1100 +phy_port_primary_and_offset_18.0=0x1101 +phy_port_primary_and_offset_19.0=0x1102 +phy_port_primary_and_offset_20.0=0x1103 +phy_port_primary_and_offset_21.0=0x1104 +phy_port_primary_and_offset_22.0=0x1105 +phy_port_primary_and_offset_23.0=0x1106 +phy_port_primary_and_offset_24.0=0x1107 + +# Comment out configuration on PHY ports + +# MCQ 0 - QSGMII +portmap_25=25:1 +portmap_26=26:1 +portmap_27=27:1 +portmap_28=28:1 +portmap_29=29:1 +portmap_30=30:1 +portmap_31=31:1 +portmap_32=32:1 + +# 54182_1 PHY ADDR 0x1-0x8 +port_phy_addr_25=0x01 +port_phy_addr_26=0x02 +port_phy_addr_27=0x03 +port_phy_addr_28=0x04 +port_phy_addr_29=0x05 +port_phy_addr_30=0x06 +port_phy_addr_31=0x07 +port_phy_addr_32=0x08 +phy_port_primary_and_offset_25.0=0x1900 +phy_port_primary_and_offset_26.0=0x1901 +phy_port_primary_and_offset_27.0=0x1902 +phy_port_primary_and_offset_28.0=0x1903 +phy_port_primary_and_offset_29.0=0x1904 +phy_port_primary_and_offset_30.0=0x1905 +phy_port_primary_and_offset_31.0=0x1906 +phy_port_primary_and_offset_32.0=0x1907 + +# MCQ 1 - QSGMII +portmap_33=33:1 +portmap_34=34:1 +portmap_35=35:1 +portmap_36=36:1 +portmap_37=37:1 +portmap_38=38:1 +portmap_39=39:1 +portmap_40=40:1 + +# 54182_2 PHY ADDR 0x21-0x28 +port_phy_addr_33=0x21 +port_phy_addr_34=0x22 +port_phy_addr_35=0x23 +port_phy_addr_36=0x24 +port_phy_addr_37=0x25 +port_phy_addr_38=0x26 +port_phy_addr_39=0x27 +port_phy_addr_40=0x28 + +phy_port_primary_and_offset_33.0=0x2100 +phy_port_primary_and_offset_34.0=0x2101 +phy_port_primary_and_offset_35.0=0x2102 +phy_port_primary_and_offset_36.0=0x2103 +phy_port_primary_and_offset_37.0=0x2104 +phy_port_primary_and_offset_38.0=0x2105 +phy_port_primary_and_offset_39.0=0x2106 +phy_port_primary_and_offset_40.0=0x2107 + +# MCQ2-2L 50182 +portmap_41=41:1 +portmap_42=42:1 +portmap_43=43:1 +portmap_44=44:1 +portmap_45=45:1 +portmap_46=46:1 +portmap_47=47:1 +portmap_48=48:1 + +# 54182_3 PHY ADDR 0x41-0x48 +port_phy_addr_41=0x41 +port_phy_addr_42=0x42 +port_phy_addr_43=0x43 +port_phy_addr_44=0x44 +port_phy_addr_45=0x45 +port_phy_addr_46=0x46 +port_phy_addr_47=0x47 +port_phy_addr_48=0x48 + +phy_port_primary_and_offset_41.0=0x2900 +phy_port_primary_and_offset_42.0=0x2901 +phy_port_primary_and_offset_43.0=0x2902 +phy_port_primary_and_offset_44.0=0x2903 +phy_port_primary_and_offset_45.0=0x2904 +phy_port_primary_and_offset_46.0=0x2905 +phy_port_primary_and_offset_47.0=0x2906 +phy_port_primary_and_offset_48.0=0x2907 + +# TSCF SFP +portmap_57=57:10 +portmap_58=58:10 +portmap_59=59:10 +portmap_60=60:10 + +portmap_61=61:10 +portmap_62=62:10 +portmap_63=63:10 +portmap_64=64:10 + + +dport_map_enable=1 + +dport_map_port_25=1 +dport_map_port_26=2 +dport_map_port_27=3 +dport_map_port_28=4 +dport_map_port_29=5 +dport_map_port_30=6 +dport_map_port_31=7 +dport_map_port_32=8 +dport_map_port_33=9 +dport_map_port_34=10 +dport_map_port_35=11 +dport_map_port_36=12 +dport_map_port_37=13 +dport_map_port_38=14 +dport_map_port_39=15 +dport_map_port_40=16 +dport_map_port_41=17 +dport_map_port_42=18 +dport_map_port_43=19 +dport_map_port_44=20 +dport_map_port_45=21 +dport_map_port_46=22 +dport_map_port_47=23 +dport_map_port_48=24 +dport_map_port_1=25 +dport_map_port_2=26 +dport_map_port_3=27 +dport_map_port_4=28 +dport_map_port_5=29 +dport_map_port_6=30 +dport_map_port_7=31 +dport_map_port_8=32 +dport_map_port_9=33 +dport_map_port_10=34 +dport_map_port_11=35 +dport_map_port_12=36 +dport_map_port_13=37 +dport_map_port_14=38 +dport_map_port_15=39 +dport_map_port_16=40 +dport_map_port_17=41 +dport_map_port_18=42 +dport_map_port_19=43 +dport_map_port_20=44 +dport_map_port_21=45 +dport_map_port_22=46 +dport_map_port_23=47 +dport_map_port_24=48 +dport_map_port_57=49 +dport_map_port_58=50 +dport_map_port_59=51 +dport_map_port_60=52 +dport_map_port_64=53 +dport_map_port_63=54 +dport_map_port_62=55 +dport_map_port_61=56 + diff --git a/device/ufispace/x86_64-ufispace_s6301_56st-r0/custom_led.bin b/device/ufispace/x86_64-ufispace_s6301_56st-r0/custom_led.bin new file mode 100644 index 000000000000..cb3a607afed6 Binary files /dev/null and b/device/ufispace/x86_64-ufispace_s6301_56st-r0/custom_led.bin differ diff --git a/device/ufispace/x86_64-ufispace_s6301_56st-r0/default_sku b/device/ufispace/x86_64-ufispace_s6301_56st-r0/default_sku new file mode 100644 index 000000000000..81aaf36922c0 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s6301_56st-r0/default_sku @@ -0,0 +1 @@ +UFISPACE-S6301-56ST t1 diff --git a/device/ufispace/x86_64-ufispace_s6301_56st-r0/fancontrol b/device/ufispace/x86_64-ufispace_s6301_56st-r0/fancontrol new file mode 100644 index 000000000000..1234cd994f3f --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s6301_56st-r0/fancontrol @@ -0,0 +1,10 @@ +# Configuration file generated by pwmconfig, changes will be lost +INTERVAL=10 +DEVPATH= +DEVNAME= +FCTEMPS= +FCFANS= +MINTEMP= +MAXTEMP= +MINSTART= +MINSTOP= diff --git a/device/ufispace/x86_64-ufispace_s6301_56st-r0/installer.conf b/device/ufispace/x86_64-ufispace_s6301_56st-r0/installer.conf new file mode 100644 index 000000000000..8f9944da69a6 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s6301_56st-r0/installer.conf @@ -0,0 +1,4 @@ +CONSOLE_PORT=0x3f8 +CONSOLE_DEV=0 +CONSOLE_SPEED=115200 +ONIE_PLATFORM_EXTRA_CMDLINE_LINUX="module_blacklist=gpio_ich nomodeset pcie_aspm=off" diff --git a/device/ufispace/x86_64-ufispace_s6301_56st-r0/led_proc_init.soc b/device/ufispace/x86_64-ufispace_s6301_56st-r0/led_proc_init.soc new file mode 100644 index 000000000000..a65a2eac30ed --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s6301_56st-r0/led_proc_init.soc @@ -0,0 +1,4 @@ +led stop +m0 load 0 0x3800 /usr/share/sonic/platform/custom_led.bin +led auto on +led start diff --git a/device/ufispace/x86_64-ufispace_s6301_56st-r0/pcie.yaml b/device/ufispace/x86_64-ufispace_s6301_56st-r0/pcie.yaml new file mode 100644 index 000000000000..9397b3a26d23 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s6301_56st-r0/pcie.yaml @@ -0,0 +1,178 @@ +- bus: '00' + dev: '00' + fn: '0' + id: '1980' + name: 'Host bridge: Intel Corporation Atom Processor C3000 Series System Agent (rev + 11)' +- bus: '00' + dev: '04' + fn: '0' + id: 19a1 + name: 'Host bridge: Intel Corporation Atom Processor C3000 Series Error Registers + (rev 11)' +- bus: '00' + dev: '05' + fn: '0' + id: 19a2 + name: 'Generic system peripheral [0807]: Intel Corporation Atom Processor C3000 + Series Root Complex Event Collector (rev 11)' +- bus: '00' + dev: '06' + fn: '0' + id: 19a3 + name: 'PCI bridge: Intel Corporation Atom Processor C3000 Series Integrated QAT + Root Port (rev 11)' +- bus: '00' + dev: 09 + fn: '0' + id: 19a4 + name: 'PCI bridge: Intel Corporation Atom Processor C3000 Series PCI Express Root + Port #0 (rev 11)' +- bus: '00' + dev: 0a + fn: '0' + id: 19a5 + name: 'PCI bridge: Intel Corporation Atom Processor C3000 Series PCI Express Root + Port #1 (rev 11)' +- bus: '00' + dev: 0b + fn: '0' + id: 19a6 + name: 'PCI bridge: Intel Corporation Atom Processor C3000 Series PCI Express Root + Port #2 (rev 11)' +- bus: '00' + dev: 0c + fn: '0' + id: 19a7 + name: 'PCI bridge: Intel Corporation Atom Processor C3000 Series PCI Express Root + Port #3 (rev 11)' +- bus: '00' + dev: 0e + fn: '0' + id: 19a8 + name: 'PCI bridge: Intel Corporation Atom Processor C3000 Series PCI Express Root + Port #4 (rev 11)' +- bus: '00' + dev: 0f + fn: '0' + id: 19a9 + name: 'PCI bridge: Intel Corporation Atom Processor C3000 Series PCI Express Root + Port #5 (rev 11)' +- bus: '00' + dev: '10' + fn: '0' + id: 19aa + name: 'PCI bridge: Intel Corporation Atom Processor C3000 Series PCI Express Root + Port #6 (rev 11)' +- bus: '00' + dev: '11' + fn: '0' + id: 19ab + name: 'PCI bridge: Intel Corporation Atom Processor C3000 Series PCI Express Root + Port #7 (rev 11)' +- bus: '00' + dev: '12' + fn: '0' + id: 19ac + name: 'System peripheral: Intel Corporation Atom Processor C3000 Series SMBus Contoller + - Host (rev 11)' +- bus: '00' + dev: '14' + fn: '0' + id: 19c2 + name: 'SATA controller: Intel Corporation Atom Processor C3000 Series SATA Controller + 1 (rev 11)' +- bus: '00' + dev: '15' + fn: '0' + id: 19d0 + name: 'USB controller: Intel Corporation Atom Processor C3000 Series USB 3.0 xHCI + Controller (rev 11)' +- bus: '00' + dev: '16' + fn: '0' + id: 19d1 + name: 'PCI bridge: Intel Corporation Atom Processor C3000 Series Integrated LAN + Root Port #0 (rev 11)' +- bus: '00' + dev: '17' + fn: '0' + id: 19d2 + name: 'PCI bridge: Intel Corporation Atom Processor C3000 Series Integrated LAN + Root Port #1 (rev 11)' +- bus: '00' + dev: '18' + fn: '0' + id: 19d3 + name: 'Communication controller: Intel Corporation Atom Processor C3000 Series ME + HECI 1 (rev 11)' +- bus: '00' + dev: 1c + fn: '0' + id: 19db + name: 'SD Host controller: Intel Corporation Device 19db (rev 11)' +- bus: '00' + dev: 1f + fn: '0' + id: 19dc + name: 'ISA bridge: Intel Corporation Atom Processor C3000 Series LPC or eSPI (rev + 11)' +- bus: '00' + dev: 1f + fn: '2' + id: 19de + name: 'Memory controller: Intel Corporation Atom Processor C3000 Series Power Management + Controller (rev 11)' +- bus: '00' + dev: 1f + fn: '4' + id: 19df + name: 'SMBus: Intel Corporation Atom Processor C3000 Series SMBus controller (rev + 11)' +- bus: '00' + dev: 1f + fn: '5' + id: 19e0 + name: 'Serial bus controller [0c80]: Intel Corporation Atom Processor C3000 Series + SPI Controller (rev 11)' +- bus: '01' + dev: '00' + fn: '0' + id: 19e2 + name: 'Co-processor: Intel Corporation Atom Processor C3000 Series QuickAssist Technology + (rev 11)' +- bus: '02' + dev: '00' + fn: '0' + id: b277 + name: 'Ethernet controller: Broadcom Inc. and subsidiaries Device b277 (rev 02)' +- bus: '07' + dev: '00' + fn: '0' + id: '1533' + name: 'Ethernet controller: Intel Corporation I210 Gigabit Network Connection (rev + 03)' +- bus: 0a + dev: '00' + fn: '0' + id: 15c3 + name: 'Ethernet controller: Intel Corporation Ethernet Connection X553 Backplane + (rev 11)' +- bus: 0a + dev: '00' + fn: '1' + id: 15c3 + name: 'Ethernet controller: Intel Corporation Ethernet Connection X553 Backplane + (rev 11)' +- bus: 0b + dev: '00' + fn: '0' + id: 15c3 + name: 'Ethernet controller: Intel Corporation Ethernet Connection X553 Backplane + (rev 11)' +- bus: 0b + dev: '00' + fn: '1' + id: 15c3 + name: 'Ethernet controller: Intel Corporation Ethernet Connection X553 Backplane + (rev 11)' diff --git a/device/ufispace/x86_64-ufispace_s6301_56st-r0/pddf/pd-plugin.json b/device/ufispace/x86_64-ufispace_s6301_56st-r0/pddf/pd-plugin.json new file mode 100644 index 000000000000..49c09b0a7888 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s6301_56st-r0/pddf/pd-plugin.json @@ -0,0 +1,79 @@ +{ + + "XCVR": + { + "xcvr_present": + { + "i2c": + { + "valmap-SFP+": {"0":true, "1":false } + } + + }, + "plug_status": + { + "inserted": "1", + "removed": "0" + } + }, + "PSU": + { + "psu_present": + { + "i2c": + { + "valmap": { "1":true, "0":false } + } + }, + + "psu_power_good": + { + "i2c": + { + "valmap": { "1": true, "0":false } + } + }, + "psu_support_list": + [ + {"Mfr_id": "ASPOWER","Model": "U1A-K10150-DRB-13", "Dir": "EXHAUST"}, + {"Mfr_id": "ASPOWER","Model": "U1A-K0150-B-13", "Dir": "INTAKE"}, + {"Mfr_id": "ASPOWER","Model": "U1D-K0150-A-13", "Dir": "EXHAUST"}, + {"Mfr_id": "ASPOWER","Model": "U1D-K0150-B-13", "Dir": "INTAKE"} + ], + "PSU_FAN_MAX_SPEED":"13000" + }, + + "FAN": + { + "direction": + { + "i2c": + { + "valmap": {"0":"INTAKE", "1":"EXHAUST"} + } + }, + + "present": + { + "i2c": + { + "valmap": {"1":true, "0":false} + } + }, + + "FAN_MAX_SPEED":"25000" + }, + + "LED": + { + "capability": + { + "ro": ["SYS_LED", "FAN_LED", "PSU1_LED", "PSU2_LED"], + "rw": ["ID_LED"] + } + }, + "REBOOT_CAUSE": + { + "reboot_cause_file": "/host/reboot-cause/reboot-cause.txt" + } +} diff --git a/device/ufispace/x86_64-ufispace_s6301_56st-r0/pddf/pddf-device.json b/device/ufispace/x86_64-ufispace_s6301_56st-r0/pddf/pddf-device.json new file mode 100644 index 000000000000..abf83dd93e48 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s6301_56st-r0/pddf/pddf-device.json @@ -0,0 +1,2277 @@ +{ + "PLATFORM": { + "num_psus": 2, + "num_fantrays": 2, + "num_fans_pertray": 1, + "num_ports": 56, + "num_temps": 5, + "pddf_dev_types": { + "description": "PDDF supported devices", + "CPLD": [ + "i2c_cpld" + ], + "PSU": [ + "psu_eeprom", + "psu_pmbus" + ], + "FAN": + [ + "fan_ctrl", + "fan_eeprom", + "fan_cpld" + ], + "PORT_MODULE": [ + "pddf_xcvr" + ] + }, + "std_kos": [ + "i2c_i801", + "i2c-ismt", + "i2c_dev", + "i2c_mux_pca954x", + "optoe", + "lm75", + "gpio-pca953x", + "ucd9000", + "eeprom" + ], + "pddf_kos": [ + "pddf_client_module", + "pddf_cpld_module", + "pddf_cpld_driver", + "pddf_mux_module", + "pddf_xcvr_module", + "pddf_xcvr_driver_module", + "pddf_psu_driver_module", + "pddf_psu_module", + "pddf_fan_driver_module", + "pddf_fan_module", + "pddf_led_module", + "pddf_gpio_module" + ], + "custom_kos": [ + "x86-64-ufispace-s6301-56st-lpc", + "x86-64-ufispace-s6301-56st-sys-eeprom" + ] + }, + "SYSTEM": { + "dev_info": { + "device_type": "CPU", + "device_name": "ROOT_COMPLEX", + "device_parent": null + }, + "i2c": { + "CONTROLLERS": [ + { + "dev_name": "i2c-1", + "dev": "SMBUS1" + }, + { + "dev_name": "i2c-0", + "dev": "SMBUS0" + } + ] + } + }, + "SMBUS1": { + "dev_info": { + "device_type": "SMBUS", "device_name": "SMBUS1", "device_parent": "SYSTEM" + }, + "i2c": { + "topo_info": { + "dev_addr": "0x1" + }, + "DEVICES": [ + { + "dev": "EEPROM1" + }, + { + "dev": "MUX1" + }, + { + "dev": "MUX2" + }, + { + "dev": "CPLD1" + }, + { + "dev": "FAN-CTRL" + } + ] + } + }, + "EEPROM1": { + "dev_info": { + "device_type": "EEPROM", + "device_name": "EEPROM1", + "device_parent": "SMBUS1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1", + "dev_addr": "0x56", + "dev_type": "sys_eeprom" + }, + "dev_attr": { + "access_mode": "BLOCK" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "MUX1": { + "dev_info": { "device_type": "MUX", "device_name": "MUX1", "device_parent": "SMBUS1"}, + "i2c": { + "topo_info": { + "parent_bus": "0x1", + "dev_addr": "0x72", + "dev_type": "pca9546" + }, + "dev_attr": { + "virt_bus": "0x2", + "idle_state": "-2" + }, + "channel": [ + { + "chn": "0", + "dev": "PSU1" + }, + { + "chn": "0", + "dev": "PSU2" + }, + { + "chn": "1", + "dev": "TEMP1" + }, + { + "chn": "1", + "dev": "TEMP2" + }, + { + "chn": "1", + "dev": "GPIO4" + }, + { + "chn": "3", + "dev": "TEMP3" + } + ] + } + }, + "MUX2": { + "dev_info": { "device_type": "MUX", "device_name": "MUX2", "device_parent": "SMBUS1"}, + "i2c": { + "topo_info": { + "parent_bus": "0x1", + "dev_addr": "0x70", + "dev_type": "pca9546" + }, + "dev_attr": { + "virt_bus": "0x6", + "idle_state": "-2" + }, + "channel": [ + { + "chn": "0", + "dev": "GPIO1" + }, + { + "chn": "1", + "dev": "GPIO2" + }, + { + "chn": "2", + "dev": "GPIO3" + } + ] + } + }, + "GPIO1": { + "dev_info": { + "device_type": "GPIO", + "device_name": "GPIO1", + "device_parent": "MUX2" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x6", + "dev_addr": "0x20", + "dev_type": "pca9535" + }, + "dev_attr": { + "gpio_base": "0x1f0" + }, + "ports": [ + { + "port_num": "0", + "direction": "in", + "value": "", + "edge": "", + "active_low": "" + }, + { + "port_num": "1", + "direction": "in", + "value": "", + "edge": "", + "active_low": "" + }, + { + "port_num": "2", + "direction": "in", + "value": "", + "edge": "", + "active_low": "" + }, + { + "port_num": "3", + "direction": "in", + "value": "", + "edge": "", + "active_low": "" + }, + { + "port_num": "4", + "direction": "in", + "value": "", + "edge": "", + "active_low": "" + }, + { + "port_num": "5", + "direction": "in", + "value": "", + "edge": "", + "active_low": "" + }, + { + "port_num": "6", + "direction": "in", + "value": "", + "edge": "", + "active_low": "" + }, + { + "port_num": "7", + "direction": "in", + "value": "", + "edge": "", + "active_low": "" + }, + { + "port_num": "8", + "direction": "in", + "value": "", + "edge": "", + "active_low": "" + }, + { + "port_num": "9", + "direction": "in", + "value": "", + "edge": "", + "active_low": "" + }, + { + "port_num": "10", + "direction": "in", + "value": "", + "edge": "", + "active_low": "" + }, + { + "port_num": "11", + "direction": "in", + "value": "", + "edge": "", + "active_low": "" + }, + { + "port_num": "12", + "direction": "in", + "value": "", + "edge": "", + "active_low": "" + }, + { + "port_num": "13", + "direction": "in", + "value": "", + "edge": "", + "active_low": "" + }, + { + "port_num": "14", + "direction": "in", + "value": "", + "edge": "", + "active_low": "" + }, + { + "port_num": "15", + "direction": "in", + "value": "", + "edge": "", + "active_low": "" + } + ] + } + }, + "GPIO2": { + "dev_info": { + "device_type": "GPIO", + "device_name": "GPIO2", + "device_parent": "MUX2" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x7", + "dev_addr": "0x21", + "dev_type": "pca9535" + }, + "dev_attr": { + "gpio_base": "0x1e0" + }, + "ports": [ + { + "port_num": "0", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "1", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "2", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "3", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "4", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "5", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "6", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "7", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "8", + "direction": "out", + "value": "0", + "edge": "", + "active_low": "" + }, + { + "port_num": "9", + "direction": "out", + "value": "0", + "edge": "", + "active_low": "" + }, + { + "port_num": "10", + "direction": "out", + "value": "0", + "edge": "", + "active_low": "" + }, + { + "port_num": "11", + "direction": "out", + "value": "0", + "edge": "", + "active_low": "" + }, + { + "port_num": "12", + "direction": "out", + "value": "0", + "edge": "", + "active_low": "" + }, + { + "port_num": "13", + "direction": "out", + "value": "0", + "edge": "", + "active_low": "" + }, + { + "port_num": "14", + "direction": "out", + "value": "0", + "edge": "", + "active_low": "" + }, + { + "port_num": "15", + "direction": "out", + "value": "0", + "edge": "", + "active_low": "" + } + ] + } + }, + "GPIO3": { + "dev_info": { + "device_type": "GPIO", + "device_name": "GPIO3", + "device_parent": "MUX2" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x8", + "dev_addr": "0x22", + "dev_type": "pca9535" + }, + "dev_attr": { + "gpio_base": "0x1d0" + }, + "ports": [ + { + "port_num": "0", + "direction": "in", + "value": "", + "edge": "", + "active_low": "" + }, + { + "port_num": "1", + "direction": "in", + "value": "", + "edge": "", + "active_low": "" + }, + { + "port_num": "2", + "direction": "in", + "value": "", + "edge": "", + "active_low": "" + }, + { + "port_num": "3", + "direction": "in", + "value": "", + "edge": "", + "active_low": "" + }, + { + "port_num": "4", + "direction": "in", + "value": "", + "edge": "", + "active_low": "" + }, + { + "port_num": "5", + "direction": "in", + "value": "", + "edge": "", + "active_low": "" + }, + { + "port_num": "6", + "direction": "in", + "value": "", + "edge": "", + "active_low": "" + }, + { + "port_num": "7", + "direction": "in", + "value": "", + "edge": "", + "active_low": "" + }, + { + "port_num": "8", + "direction": "in", + "value": "", + "edge": "", + "active_low": "" + }, + { + "port_num": "9", + "direction": "in", + "value": "", + "edge": "", + "active_low": "" + }, + { + "port_num": "10", + "direction": "in", + "value": "", + "edge": "", + "active_low": "" + }, + { + "port_num": "11", + "direction": "in", + "value": "", + "edge": "", + "active_low": "" + }, + { + "port_num": "12", + "direction": "in", + "value": "", + "edge": "", + "active_low": "" + }, + { + "port_num": "13", + "direction": "in", + "value": "", + "edge": "", + "active_low": "" + }, + { + "port_num": "14", + "direction": "in", + "value": "", + "edge": "", + "active_low": "" + }, + { + "port_num": "15", + "direction": "in", + "value": "", + "edge": "", + "active_low": "" + } + ] + } + }, + "GPIO4": { + "dev_info": { + "device_type": "GPIO", + "device_name": "GPIO4", + "device_parent": "MUX1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x3", + "dev_addr": "0x21", + "dev_type": "pca9554" + }, + "dev_attr": { + "gpio_base": "0x1C8" + }, + "ports": [ + { + "port_num": "0", + "direction": "in", + "value": "", + "edge": "", + "active_low": "" + }, + { + "port_num": "1", + "direction": "in", + "value": "", + "edge": "", + "active_low": "" + }, + { + "port_num": "2", + "direction": "in", + "value": "", + "edge": "", + "active_low": "" + }, + { + "port_num": "3", + "direction": "in", + "value": "", + "edge": "", + "active_low": "" + }, + { + "port_num": "4", + "direction": "in", + "value": "", + "edge": "", + "active_low": "" + }, + { + "port_num": "5", + "direction": "in", + "value": "", + "edge": "", + "active_low": "" + }, + { + "port_num": "6", + "direction": "in", + "value": "", + "edge": "", + "active_low": "" + }, + { + "port_num": "7", + "direction": "in", + "value": "", + "edge": "", + "active_low": "" + } + ] + } + }, + "CPLD1": { + "dev_info": { + "device_type": "CPLD", + "device_name": "CPLD1", + "device_parent": "SMBUS1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1", + "dev_addr": "0x33", + "dev_type": "i2c_cpld" + }, + "dev_attr": {} + } + }, + "SMBUS0": { + "dev_info": { + "device_type": "SMBUS", "device_name": "SMBUS0", "device_parent": "SYSTEM" + }, + "i2c": { + "topo_info": { + "dev_addr": "0x0" + }, + "DEVICES": [ + { + "dev": "MUX3" + } + ] + } + }, + "MUX3": { + "dev_info": { "device_type":"MUX", "device_name":"MUX3", "device_parent":"SMBUS0"}, + "i2c": + { + "topo_info": { "parent_bus":"0x0", "dev_addr":"0x71", "dev_type":"pca9548"}, + "dev_attr": { "virt_bus":"0xa", "idle_state":"-2"}, + "channel": + [ + { "chn":"0", "dev":"PORT49" }, + { "chn":"1", "dev":"PORT50" }, + { "chn":"2", "dev":"PORT51" }, + { "chn":"3", "dev":"PORT52" }, + { "chn":"4", "dev":"PORT53" }, + { "chn":"5", "dev":"PORT54" }, + { "chn":"6", "dev":"PORT55" }, + { "chn":"7", "dev":"PORT56" } + ] + } + }, + "TEMP1": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TEMP1", + "device_parent": "MUX1" + }, + "dev_attr": { + "display_name": "Temp_FAN1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x3", + "dev_addr": "0x49", + "dev_type": "tmp75" + }, + "attr_list": [ + { + "attr_name": "temp1_high_threshold", + "drv_attr_name": "temp1_max" + }, + { + "attr_name": "temp1_max_hyst" + }, + { + "attr_name": "temp1_input" + } + ] + } + }, + "TEMP2": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TEMP2", + "device_parent": "MUX1" + }, + "dev_attr": { + "display_name": "Temp_FAN2" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x3", + "dev_addr": "0x4A", + "dev_type": "tmp75" + }, + "attr_list": [ + { + "attr_name": "temp1_high_threshold", + "drv_attr_name": "temp1_max" + }, + { + "attr_name": "temp1_max_hyst" + }, + { + "attr_name": "temp1_input" + } + ] + } + }, + "TEMP3": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TEMP3", + "device_parent": "MUX1" + }, + "dev_attr": { + "display_name": "Temp_PSUDB" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x5", + "dev_addr": "0x34", + "dev_type": "ucd90124" + }, + "attr_list": [ + { + "attr_name": "temp1_high_threshold", + "drv_attr_name": "temp2_max" + }, + { + "attr_name": "temp1_input", + "drv_attr_name": "temp2_input" + } + ] + } + }, + "TEMP4": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TEMP4", + "device_parent": "MUX1" + }, + "dev_attr": { + "display_name": "Temp_MAC" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x5", + "dev_addr": "0x34", + "dev_type": "ucd90124" + }, + "attr_list": [ + { + "attr_name": "temp1_high_threshold", + "drv_attr_name": "temp3_max" + }, + { + "attr_name": "temp1_input", + "drv_attr_name": "temp3_input" + } + ] + } + }, + "TEMP5": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TEMP5", + "device_parent": "MUX1" + }, + "dev_attr": { + "display_name": "Temp_INLET" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x5", + "dev_addr": "0x34", + "dev_type": "ucd90124" + }, + "attr_list": [ + { + "attr_name": "temp1_high_threshold", + "drv_attr_name": "temp4_max" + }, + { + "attr_name": "temp1_input", + "drv_attr_name": "temp4_input" + } + ] + } + }, + "PSU1": { + "dev_info": { + "device_type": "PSU", + "device_name": "PSU1", + "device_parent": "MUX1" + }, + "dev_attr": { + "dev_idx": "1", + "num_psu_fans": "1" + }, + "i2c": { + "interface": [ + { "itf":"pmbus", "dev":"PSU1-PMBUS" }, + { "itf":"eeprom", "dev":"PSU1-EEPROM" } + ] + } + }, + "PSU1-PMBUS": { + "dev_info": { + "device_type": "PSU-PMBUS", + "device_name": "PSU1-PMBUS", + "device_parent": "MUX1", + "virt_parent": "PSU1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2", + "dev_addr": "0x58", + "dev_type": "psu_pmbus" + }, + "attr_list": [ + { + "attr_name": "psu_present", + "attr_devaddr":"0x33", + "attr_devtype": "cpld", + "attr_devname":"CPLD1", + "attr_offset": "0x59", + "attr_mask": "0x1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "psu_power_good", + "attr_devaddr": "0x33", + "attr_devtype": "cpld", + "attr_devname": "CPLD1", + "attr_offset": "0x59", + "attr_mask": "0x10", + "attr_cmpval": "0x10", + "attr_len": "1" + }, + { + "attr_name": "psu_model_name", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0x9a", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "12" + }, + { + "attr_name": "psu_mfr_id", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0x99", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "10" + }, + { + "attr_name": "psu_v_in", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0x88", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "2" + }, + { + "attr_name": "psu_i_in", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0x89", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "2" + }, + { + "attr_name": "psu_p_in", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0x97", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "2" + }, + { + "attr_name": "psu_v_out", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0x8b", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "2" + }, + { + "attr_name": "psu_i_out", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0x8c", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "2" + }, + { + "attr_name": "psu_p_out", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0x96", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "2" + }, + { + "attr_name": "psu_fan1_speed_rpm", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0x90", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "2" + }, + { + "attr_name": "psu_temp1_input", + "attr_devaddr": "0x58", + "attr_devtype": "pmbus", + "attr_offset": "0x8d", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "2" + } + ] + } + }, + "PSU1-EEPROM": + { + "dev_info": { + "device_type":"", + "device_name":"PSU1-EEPROM", + "device_parent":"MUX1", + "virt_parent":"PSU1" + }, + "i2c": + { + "topo_info":{ + "parent_bus":"0x2", + "dev_addr":"0x50", + "dev_type":"eeprom" + }, + "attr_list": + [ + { "attr_name":"eeprom" } + ] + } + }, + "PSU2": { + "dev_info": { + "device_type": "PSU", + "device_name": "PSU2", + "device_parent": "MUX1" + }, + "dev_attr": { + "dev_idx": "2", + "num_psu_fans": "1" + }, + "i2c": { + "interface": [ + { "itf":"pmbus", "dev":"PSU2-PMBUS" }, + { "itf":"eeprom", "dev":"PSU2-EEPROM" } + ] + } + }, + "PSU2-PMBUS": { + "dev_info": { + "device_type": "PSU-PMBUS", + "device_name": "PSU2-PMBUS", + "device_parent": "MUX1", + "virt_parent": "PSU2" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2", + "dev_addr": "0x59", + "dev_type": "psu_pmbus" + }, + "attr_list": [ + { + "attr_name": "psu_present", + "attr_devaddr":"0x33", + "attr_devtype": "cpld", + "attr_devname":"CPLD1", + "attr_offset": "0x59", + "attr_mask": "0x2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "psu_power_good", + "attr_devaddr": "0x33", + "attr_devtype": "cpld", + "attr_devname": "CPLD1", + "attr_offset": "0x59", + "attr_mask": "0x20", + "attr_cmpval": "0x20", + "attr_len": "1" + }, + { + "attr_name": "psu_model_name", + "attr_devaddr": "0x59", + "attr_devtype": "pmbus", + "attr_offset": "0x9a", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "12" + }, + { + "attr_name": "psu_mfr_id", + "attr_devaddr": "0x59", + "attr_devtype": "pmbus", + "attr_offset": "0x99", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "10" + }, + { + "attr_name": "psu_v_in", + "attr_devaddr": "0x59", + "attr_devtype": "pmbus", + "attr_offset": "0x88", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "2" + }, + { + "attr_name": "psu_i_in", + "attr_devaddr": "0x59", + "attr_devtype": "pmbus", + "attr_offset": "0x89", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "2" + }, + { + "attr_name": "psu_p_in", + "attr_devaddr": "0x59", + "attr_devtype": "pmbus", + "attr_offset": "0x97", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "2" + }, + { + "attr_name": "psu_v_out", + "attr_devaddr": "0x59", + "attr_devtype": "pmbus", + "attr_offset": "0x8b", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "2" + }, + { + "attr_name": "psu_i_out", + "attr_devaddr": "0x59", + "attr_devtype": "pmbus", + "attr_offset": "0x8c", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "2" + }, + { + "attr_name": "psu_p_out", + "attr_devaddr": "0x59", + "attr_devtype": "pmbus", + "attr_offset": "0x96", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "2" + }, + { + "attr_name": "psu_fan1_speed_rpm", + "attr_devaddr": "0x59", + "attr_devtype": "pmbus", + "attr_offset": "0x90", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "2" + }, + { + "attr_name": "psu_temp1_input", + "attr_devaddr": "0x59", + "attr_devtype": "pmbus", + "attr_offset": "0x8d", + "attr_mask": "0x0", + "attr_cmpval": "0xff", + "attr_len": "2" + } + ] + } + }, + "PSU2-EEPROM": + { + "dev_info": { + "device_type":"", + "device_name":"PSU2-EEPROM", + "device_parent":"MUX1", + "virt_parent":"PSU2" + }, + "i2c": + { + "topo_info":{ + "parent_bus":"0x2", + "dev_addr":"0x51", + "dev_type":"eeprom" + }, + "attr_list": + [ + { "attr_name":"eeprom" } + ] + } + }, + "FAN-CTRL": { + "dev_info": { + "device_type": "FAN", + "device_name": "FAN-CTRL", + "device_parent": "SMBUS1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1", + "dev_addr": "0x60", + "dev_type": "fan_cpld" + }, + "dev_attr": { "num_fantrays":"2"}, + "attr_list": [ + { + "attr_name": "fan1_present", + "attr_devaddr":"0x33", + "attr_devtype": "cpld", + "attr_devname":"CPLD1", + "attr_offset": "0x55", + "attr_mask": "0x1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "fan2_present", + "attr_devaddr":"0x33", + "attr_devtype": "cpld", + "attr_devname":"CPLD1", + "attr_offset": "0x55", + "attr_mask": "0x2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "fan1_direction", + "attr_devaddr":"0x21", + "attr_devtype": "gpio", + "attr_devname":"GPIO4", + "attr_offset": "0x4", + "attr_mask": "", + "attr_cmpval": "", + "attr_len": "" + }, + { + "attr_name": "fan2_direction", + "attr_devaddr":"0x21", + "attr_devtype": "gpio", + "attr_devname":"GPIO4", + "attr_offset": "0x3", + "attr_mask": "", + "attr_cmpval": "", + "attr_len": "" + } + ] + } + }, + "SYS_LED": { + "dev_info": { + "device_type": "LED", + "device_name": "SYS_LED" + }, + "dev_attr": { + "index": "0" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "green", + "bits": "7:4", + "descr": "Green", + "value": "0x09;0x0b", + "swpld_addr": "0x33", + "swpld_addr_offset": "0x81" + }, + { + "attr_name": "green_blink", + "bits": "7:4", + "descr": "Green Blinking", + "value": "0x0d;0x0f", + "swpld_addr": "0x33", + "swpld_addr_offset": "0x81" + }, + { + "attr_name": "yellow", + "bits": "7:4", + "descr": "Yellow", + "value": "0x08;0x0a", + "swpld_addr": "0x33", + "swpld_addr_offset": "0x81" + }, + { + "attr_name": "yellow_blink", + "bits": "7:4", + "descr": "Yellow Blinking", + "value": "0x0c;0x0e", + "swpld_addr": "0x33", + "swpld_addr_offset": "0x81" + }, + { + "attr_name": "off", + "bits": "7", + "descr": "Off", + "value": "0x0", + "swpld_addr": "0x33", + "swpld_addr_offset": "0x81" + } + ] + } + }, + "ID_LED": { + "dev_info": { + "device_type": "LED", + "device_name": "LOC_LED" + }, + "dev_attr": { + "index": "0" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "blue", + "bits": "3:0", + "descr": "Bule", + "value": "0x09;0x0b", + "swpld_addr": "0x33", + "swpld_addr_offset": "0x81" + }, + { + "attr_name": "blue_blink", + "bits": "3:0", + "descr": "Blue Blinking", + "value": "0x0d;0x0f", + "swpld_addr": "0x33", + "swpld_addr_offset": "0x81" + }, + { + "attr_name": "off", + "bits": "3", + "descr": "Off", + "value": "0x0", + "swpld_addr": "0x33", + "swpld_addr_offset": "0x81" + } + ] + } + }, + "FAN_LED": { + "dev_info": { + "device_type": "LED", + "device_name": "FAN_LED" + }, + "dev_attr": { + "index": "0" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "green", + "bits": "7:4", + "descr": "Green", + "value": "0x09;0x0b", + "swpld_addr": "0x33", + "swpld_addr_offset": "0x83" + }, + { + "attr_name": "green_blink", + "bits": "7:4", + "descr": "Green Blinking", + "value": "0x0d;0x0f", + "swpld_addr": "0x33", + "swpld_addr_offset": "0x83" + }, + { + "attr_name": "yellow", + "bits": "7:4", + "descr": "Yellow", + "value": "0x08;0x0a", + "swpld_addr": "0x33", + "swpld_addr_offset": "0x83" + }, + { + "attr_name": "yellow_blink", + "bits": "7:4", + "descr": "Yellow Blinking", + "value": "0x0c;0x0e", + "swpld_addr": "0x33", + "swpld_addr_offset": "0x83" + }, + { + "attr_name": "off", + "bits": "7", + "descr": "Off", + "value": "0x0", + "swpld_addr": "0x33", + "swpld_addr_offset": "0x83" + } + ] + } + }, + "PSU2_LED": { + "dev_info": { + "device_type": "LED", + "device_name": "PSU_LED" + }, + "dev_attr": { + "index": "1" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "green", + "bits": "7:4", + "descr": "Green", + "value": "0x09;0x0b", + "swpld_addr": "0x33", + "swpld_addr_offset": "0x84" + }, + { + "attr_name": "green_blink", + "bits": "7:4", + "descr": "Green Blinking", + "value": "0x0d;0x0f", + "swpld_addr": "0x33", + "swpld_addr_offset": "0x84" + }, + { + "attr_name": "yellow", + "bits": "7:4", + "descr": "Yellow", + "value": "0x08;0x0a", + "swpld_addr": "0x33", + "swpld_addr_offset": "0x84" + }, + { + "attr_name": "yellow_blink", + "bits": "7:4", + "descr": "Yellow Blinking", + "value": "0x0c;0x0e", + "swpld_addr": "0x33", + "swpld_addr_offset": "0x84" + }, + { + "attr_name": "off", + "bits": "7", + "descr": "Off", + "value": "0x0", + "swpld_addr": "0x33", + "swpld_addr_offset": "0x84" + } + ] + } + }, + "PSU1_LED": { + "dev_info": { + "device_type": "LED", + "device_name": "PSU_LED" + }, + "dev_attr": { + "index": "0" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "green", + "bits": "3:0", + "descr": "Green", + "value": "0x09;0x0b", + "swpld_addr": "0x33", + "swpld_addr_offset": "0x84" + }, + { + "attr_name": "green_blink", + "bits": "3:0", + "descr": "Green Blinking", + "value": "0x0d;0x0f", + "swpld_addr": "0x33", + "swpld_addr_offset": "0x84" + }, + { + "attr_name": "yellow", + "bits": "3:0", + "descr": "Yellow", + "value": "0x08;0x0a", + "swpld_addr": "0x33", + "swpld_addr_offset": "0x84" + }, + { + "attr_name": "yellow_blink", + "bits": "3:0", + "descr": "Yellow Blinking", + "value": "0x0c;0x0e", + "swpld_addr": "0x33", + "swpld_addr_offset": "0x84" + }, + { + "attr_name": "off", + "bits": "3", + "descr": "Off", + "value": "0x0", + "swpld_addr": "0x33", + "swpld_addr_offset": "0x84" + } + ] + } + }, + "PORT49": { + "dev_info": { + "device_type": "SFP+", + "device_name": "PORT49", + "device_parent": "MUX3" + }, + "dev_attr": { + "dev_idx": "49" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT49-EEPROM" + }, + { + "itf": "control", + "dev": "PORT49-CTRL" + } + ] + } + }, + "PORT49-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT49-EEPROM", + "device_parent": "MUX3", + "virt_parent": "PORT49" + }, + "i2c": { + "topo_info": { + "parent_bus": "0xA", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT49-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT49-CTRL", + "device_parent": "MUX3", + "virt_parent": "PORT49" + }, + "i2c": { + "topo_info": { + "parent_bus": "0xA", + "dev_addr": "0x54", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x20", + "attr_devname": "GPIO1", + "attr_devtype": "gpio", + "attr_offset": "0x7", + "attr_mask": "", + "attr_cmpval": "", + "attr_len": "" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x22", + "attr_devname": "GPIO3", + "attr_devtype": "gpio", + "attr_offset": "0xF", + "attr_mask": "", + "attr_cmpval": "", + "attr_len": "" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x22", + "attr_devname": "GPIO3", + "attr_devtype": "gpio", + "attr_offset": "0x7", + "attr_mask": "", + "attr_cmpval": "", + "attr_len": "" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x21", + "attr_devname": "GPIO2", + "attr_devtype": "gpio", + "attr_offset": "0xF", + "attr_mask": "", + "attr_cmpval": "", + "attr_len": "" + } + ] + } + }, + "PORT50": { + "dev_info": { + "device_type": "SFP+", + "device_name": "PORT50", + "device_parent": "MUX3" + }, + "dev_attr": { + "dev_idx": "50" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT50-EEPROM" + }, + { + "itf": "control", + "dev": "PORT50-CTRL" + } + ] + } + }, + "PORT50-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT50-EEPROM", + "device_parent": "MUX3", + "virt_parent": "PORT50" + }, + "i2c": { + "topo_info": { + "parent_bus": "0xB", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT50-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT50-CTRL", + "device_parent": "MUX3", + "virt_parent": "PORT50" + }, + "i2c": { + "topo_info": { + "parent_bus": "0xB", + "dev_addr": "0x54", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x20", + "attr_devname": "GPIO1", + "attr_devtype": "gpio", + "attr_offset": "0x6", + "attr_mask": "", + "attr_cmpval": "", + "attr_len": "" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x22", + "attr_devname": "GPIO3", + "attr_devtype": "gpio", + "attr_offset": "0xE", + "attr_mask": "", + "attr_cmpval": "", + "attr_len": "" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x22", + "attr_devname": "GPIO3", + "attr_devtype": "gpio", + "attr_offset": "0x6", + "attr_mask": "", + "attr_cmpval": "", + "attr_len": "" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x21", + "attr_devname": "GPIO2", + "attr_devtype": "gpio", + "attr_offset": "0xE", + "attr_mask": "", + "attr_cmpval": "", + "attr_len": "" + } + ] + } + }, + "PORT51": { + "dev_info": { + "device_type": "SFP+", + "device_name": "PORT51", + "device_parent": "MUX3" + }, + "dev_attr": { + "dev_idx": "51" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT51-EEPROM" + }, + { + "itf": "control", + "dev": "PORT51-CTRL" + } + ] + } + }, + "PORT51-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT51-EEPROM", + "device_parent": "MUX3", + "virt_parent": "PORT51" + }, + "i2c": { + "topo_info": { + "parent_bus": "0xC", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT51-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT51-CTRL", + "device_parent": "MUX3", + "virt_parent": "PORT51" + }, + "i2c": { + "topo_info": { + "parent_bus": "0xC", + "dev_addr": "0x54", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x20", + "attr_devname": "GPIO1", + "attr_devtype": "gpio", + "attr_offset": "0x5", + "attr_mask": "", + "attr_cmpval": "", + "attr_len": "" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x22", + "attr_devname": "GPIO3", + "attr_devtype": "gpio", + "attr_offset": "0xD", + "attr_mask": "", + "attr_cmpval": "", + "attr_len": "" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x22", + "attr_devname": "GPIO3", + "attr_devtype": "gpio", + "attr_offset": "0x5", + "attr_mask": "", + "attr_cmpval": "", + "attr_len": "" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x21", + "attr_devname": "GPIO2", + "attr_devtype": "gpio", + "attr_offset": "0xD", + "attr_mask": "", + "attr_cmpval": "", + "attr_len": "" + } + ] + } + }, + "PORT52": { + "dev_info": { + "device_type": "SFP+", + "device_name": "PORT52", + "device_parent": "MUX3" + }, + "dev_attr": { + "dev_idx": "52" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT52-EEPROM" + }, + { + "itf": "control", + "dev": "PORT52-CTRL" + } + ] + } + }, + "PORT52-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT52-EEPROM", + "device_parent": "MUX3", + "virt_parent": "PORT52" + }, + "i2c": { + "topo_info": { + "parent_bus": "0xD", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT52-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT52-CTRL", + "device_parent": "MUX3", + "virt_parent": "PORT52" + }, + "i2c": { + "topo_info": { + "parent_bus": "0xD", + "dev_addr": "0x54", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x20", + "attr_devname": "GPIO1", + "attr_devtype": "gpio", + "attr_offset": "0x4", + "attr_mask": "", + "attr_cmpval": "", + "attr_len": "" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x22", + "attr_devname": "GPIO3", + "attr_devtype": "gpio", + "attr_offset": "0xC", + "attr_mask": "", + "attr_cmpval": "", + "attr_len": "" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x22", + "attr_devname": "GPIO3", + "attr_devtype": "gpio", + "attr_offset": "0x4", + "attr_mask": "", + "attr_cmpval": "", + "attr_len": "" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x21", + "attr_devname": "GPIO2", + "attr_devtype": "gpio", + "attr_offset": "0xC", + "attr_mask": "", + "attr_cmpval": "", + "attr_len": "" + } + ] + } + }, + "PORT53": { + "dev_info": { + "device_type": "SFP+", + "device_name": "PORT53", + "device_parent": "MUX3" + }, + "dev_attr": { + "dev_idx": "53" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT53-EEPROM" + }, + { + "itf": "control", + "dev": "PORT53-CTRL" + } + ] + } + }, + "PORT53-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT53-EEPROM", + "device_parent": "MUX3", + "virt_parent": "PORT53" + }, + "i2c": { + "topo_info": { + "parent_bus": "0xE", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT53-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT53-CTRL", + "device_parent": "MUX3", + "virt_parent": "PORT53" + }, + "i2c": { + "topo_info": { + "parent_bus": "0xE", + "dev_addr": "0x54", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x20", + "attr_devname": "GPIO1", + "attr_devtype": "gpio", + "attr_offset": "0x3", + "attr_mask": "", + "attr_cmpval": "", + "attr_len": "" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x22", + "attr_devname": "GPIO3", + "attr_devtype": "gpio", + "attr_offset": "0xB", + "attr_mask": "", + "attr_cmpval": "", + "attr_len": "" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x22", + "attr_devname": "GPIO3", + "attr_devtype": "gpio", + "attr_offset": "0x3", + "attr_mask": "", + "attr_cmpval": "", + "attr_len": "" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x21", + "attr_devname": "GPIO2", + "attr_devtype": "gpio", + "attr_offset": "0xB", + "attr_mask": "", + "attr_cmpval": "", + "attr_len": "" + } + ] + } + }, + "PORT54": { + "dev_info": { + "device_type": "SFP+", + "device_name": "PORT54", + "device_parent": "MUX3" + }, + "dev_attr": { + "dev_idx": "54" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT54-EEPROM" + }, + { + "itf": "control", + "dev": "PORT54-CTRL" + } + ] + } + }, + "PORT54-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT54-EEPROM", + "device_parent": "MUX3", + "virt_parent": "PORT54" + }, + "i2c": { + "topo_info": { + "parent_bus": "0xF", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT54-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT54-CTRL", + "device_parent": "MUX3", + "virt_parent": "PORT54" + }, + "i2c": { + "topo_info": { + "parent_bus": "0xF", + "dev_addr": "0x54", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x20", + "attr_devname": "GPIO1", + "attr_devtype": "gpio", + "attr_offset": "0x2", + "attr_mask": "", + "attr_cmpval": "", + "attr_len": "" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x22", + "attr_devname": "GPIO3", + "attr_devtype": "gpio", + "attr_offset": "0xA", + "attr_mask": "", + "attr_cmpval": "", + "attr_len": "" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x22", + "attr_devname": "GPIO3", + "attr_devtype": "gpio", + "attr_offset": "0x2", + "attr_mask": "", + "attr_cmpval": "", + "attr_len": "" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x21", + "attr_devname": "GPIO2", + "attr_devtype": "gpio", + "attr_offset": "0xA", + "attr_mask": "", + "attr_cmpval": "", + "attr_len": "" + } + ] + } + }, + "PORT55": { + "dev_info": { + "device_type": "SFP+", + "device_name": "PORT55", + "device_parent": "MUX3" + }, + "dev_attr": { + "dev_idx": "55" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT55-EEPROM" + }, + { + "itf": "control", + "dev": "PORT55-CTRL" + } + ] + } + }, + "PORT55-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT55-EEPROM", + "device_parent": "MUX3", + "virt_parent": "PORT55" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x10", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT55-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT55-CTRL", + "device_parent": "MUX3", + "virt_parent": "PORT55" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x10", + "dev_addr": "0x54", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x20", + "attr_devname": "GPIO1", + "attr_devtype": "gpio", + "attr_offset": "0x1", + "attr_mask": "", + "attr_cmpval": "", + "attr_len": "" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x22", + "attr_devname": "GPIO3", + "attr_devtype": "gpio", + "attr_offset": "0x9", + "attr_mask": "", + "attr_cmpval": "", + "attr_len": "" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x22", + "attr_devname": "GPIO3", + "attr_devtype": "gpio", + "attr_offset": "0x1", + "attr_mask": "", + "attr_cmpval": "", + "attr_len": "" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x21", + "attr_devname": "GPIO2", + "attr_devtype": "gpio", + "attr_offset": "0x9", + "attr_mask": "", + "attr_cmpval": "", + "attr_len": "" + } + ] + } + }, + "PORT56": { + "dev_info": { + "device_type": "SFP+", + "device_name": "PORT56", + "device_parent": "MUX3" + }, + "dev_attr": { + "dev_idx": "56" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT56-EEPROM" + }, + { + "itf": "control", + "dev": "PORT56-CTRL" + } + ] + } + }, + "PORT56-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT56-EEPROM", + "device_parent": "MUX3", + "virt_parent": "PORT56" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x11", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT56-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT56-CTRL", + "device_parent": "MUX3", + "virt_parent": "PORT56" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x11", + "dev_addr": "0x54", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x20", + "attr_devname": "GPIO1", + "attr_devtype": "gpio", + "attr_offset": "0x0", + "attr_mask": "", + "attr_cmpval": "", + "attr_len": "" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x22", + "attr_devname": "GPIO3", + "attr_devtype": "gpio", + "attr_offset": "0x8", + "attr_mask": "", + "attr_cmpval": "", + "attr_len": "" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x22", + "attr_devname": "GPIO3", + "attr_devtype": "gpio", + "attr_offset": "0x0", + "attr_mask": "", + "attr_cmpval": "", + "attr_len": "" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x21", + "attr_devname": "GPIO2", + "attr_devtype": "gpio", + "attr_offset": "0x8", + "attr_mask": "", + "attr_cmpval": "", + "attr_len": "" + } + ] + } + } +} \ No newline at end of file diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/lib/rgutil/__init__.py b/device/ufispace/x86_64-ufispace_s6301_56st-r0/pddf_support old mode 100755 new mode 100644 similarity index 100% rename from platform/broadcom/sonic-platform-modules-ragile/common/lib/rgutil/__init__.py rename to device/ufispace/x86_64-ufispace_s6301_56st-r0/pddf_support diff --git a/device/ufispace/x86_64-ufispace_s6301_56st-r0/platform.json b/device/ufispace/x86_64-ufispace_s6301_56st-r0/platform.json new file mode 100644 index 000000000000..814d8577f2b5 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s6301_56st-r0/platform.json @@ -0,0 +1,651 @@ +{ + "chassis": { + "name": "S6301-56ST", + "components": [ + { + "name": "CPLD1" + }, + { + "name": "BIOS" + } + ], + "fans": [ + { + "name": "Fantray1" + }, + { + "name": "Fantray2" + } + ], + "fan_drawers":[ + { + "name": "Fantray1", + "num_fans" : 1, + "fans": [ + { + "name": "Fantray1" + } + ] + }, + { + "name": "Fantray2", + "num_fans" : 1, + "fans": [ + { + "name": "Fantray2" + } + ] + } + ], + "psus": [ + { + "name": "PSU1", + "fans": [ + { + "name": "PSU1_FAN1" + } + ], + "thermals": [ + { + "name": "PSU1_TEMP1" + } + ] + }, + { + "name": "PSU2", + "fans": [ + { + "name": "PSU2_FAN1" + } + ], + "thermals": [ + { + "name": "PSU2_TEMP1" + } + ] + } + ], + "thermals": [ + { + "name": "Temp_FAN1" + }, + { + "name": "Temp_FAN2" + }, + { + "name": "Temp_PSUDB" + }, + { + "name": "Temp_MAC" + }, + { + "name": "Temp_INLET" + } + ], + "sfps": [ + { + "name": "Ethernet0" + }, + { + "name": "Ethernet1" + }, + { + "name": "Ethernet2" + }, + { + "name": "Ethernet3" + }, + { + "name": "Ethernet4" + }, + { + "name": "Ethernet5" + }, + { + "name": "Ethernet6" + }, + { + "name": "Ethernet7" + }, + { + "name": "Ethernet8" + }, + { + "name": "Ethernet9" + }, + { + "name": "Ethernet10" + }, + { + "name": "Ethernet11" + }, + { + "name": "Ethernet12" + }, + { + "name": "Ethernet13" + }, + { + "name": "Ethernet14" + }, + { + "name": "Ethernet15" + }, + { + "name": "Ethernet16" + }, + { + "name": "Ethernet17" + }, + { + "name": "Ethernet18" + }, + { + "name": "Ethernet19" + }, + { + "name": "Ethernet20" + }, + { + "name": "Ethernet21" + }, + { + "name": "Ethernet22" + }, + { + "name": "Ethernet23" + }, + { + "name": "Ethernet24" + }, + { + "name": "Ethernet25" + }, + { + "name": "Ethernet26" + }, + { + "name": "Ethernet27" + }, + { + "name": "Ethernet28" + }, + { + "name": "Ethernet29" + }, + { + "name": "Ethernet30" + }, + { + "name": "Ethernet31" + }, + { + "name": "Ethernet32" + }, + { + "name": "Ethernet33" + }, + { + "name": "Ethernet34" + }, + { + "name": "Ethernet35" + }, + { + "name": "Ethernet36" + }, + { + "name": "Ethernet37" + }, + { + "name": "Ethernet38" + }, + { + "name": "Ethernet39" + }, + { + "name": "Ethernet40" + }, + { + "name": "Ethernet41" + }, + { + "name": "Ethernet42" + }, + { + "name": "Ethernet43" + }, + { + "name": "Ethernet44" + }, + { + "name": "Ethernet45" + }, + { + "name": "Ethernet46" + }, + { + "name": "Ethernet47" + }, + { + "name": "Ethernet48" + }, + { + "name": "Ethernet49" + }, + { + "name": "Ethernet50" + }, + { + "name": "Ethernet51" + }, + { + "name": "Ethernet52" + }, + { + "name": "Ethernet53" + }, + { + "name": "Ethernet54" + }, + { + "name": "Ethernet55" + } + ] + }, + "interfaces": { + "Ethernet0": { + "index": "0", + "lanes": "25", + "breakout_modes": { + "1x1G": ["Eth0(Port0)"] + } + }, + "Ethernet1": { + "index": "1", + "lanes": "26", + "breakout_modes": { + "1x1G": ["Eth1(Port1)"] + } + }, + "Ethernet2": { + "index": "2", + "lanes": "27", + "breakout_modes": { + "1x1G": ["Eth2(Port2)"] + } + }, + "Ethernet3": { + "index": "3", + "lanes": "28", + "breakout_modes": { + "1x1G": ["Eth3(Port3)"] + } + }, + "Ethernet4": { + "index": "4", + "lanes": "29", + "breakout_modes": { + "1x1G": ["Eth4(Port4)"] + } + }, + "Ethernet5": { + "index": "5", + "lanes": "30", + "breakout_modes": { + "1x1G": ["Eth5(Port5)"] + } + }, + "Ethernet6": { + "index": "6", + "lanes": "31", + "breakout_modes": { + "1x1G": ["Eth6(Port6)"] + } + }, + "Ethernet7": { + "index": "7", + "lanes": "32", + "breakout_modes": { + "1x1G": ["Eth7(Port7)"] + } + }, + "Ethernet8": { + "index": "8", + "lanes": "33", + "breakout_modes": { + "1x1G": ["Eth8(Port8)"] + } + }, + "Ethernet9": { + "index": "9", + "lanes": "34", + "breakout_modes": { + "1x1G": ["Eth9(Port9)"] + } + }, + "Ethernet10": { + "index": "10", + "lanes": "35", + "breakout_modes": { + "1x1G": ["Eth10(Port10)"] + } + }, + "Ethernet11": { + "index": "11", + "lanes": "36", + "breakout_modes": { + "1x1G": ["Eth11(Port11)"] + } + }, + "Ethernet12": { + "index": "12", + "lanes": "37", + "breakout_modes": { + "1x1G": ["Eth12(Port12)"] + } + }, + "Ethernet13": { + "index": "13", + "lanes": "38", + "breakout_modes": { + "1x1G": ["Eth13(Port13)"] + } + }, + "Ethernet14": { + "index": "14", + "lanes": "39", + "breakout_modes": { + "1x1G": ["Eth14(Port14)"] + } + }, + "Ethernet15": { + "index": "15", + "lanes": "40", + "breakout_modes": { + "1x1G": ["Eth15(Port15)"] + } + }, + "Ethernet16": { + "index": "16", + "lanes": "41", + "breakout_modes": { + "1x1G": ["Eth16(Port16)"] + } + }, + "Ethernet17": { + "index": "17", + "lanes": "42", + "breakout_modes": { + "1x1G": ["Eth17(Port17)"] + } + }, + "Ethernet18": { + "index": "18", + "lanes": "43", + "breakout_modes": { + "1x1G": ["Eth18(Port18)"] + } + }, + "Ethernet19": { + "index": "19", + "lanes": "44", + "breakout_modes": { + "1x1G": ["Eth19(Port19)"] + } + }, + "Ethernet20": { + "index": "20", + "lanes": "45", + "breakout_modes": { + "1x1G": ["Eth20(Port20)"] + } + }, + "Ethernet21": { + "index": "21", + "lanes": "46", + "breakout_modes": { + "1x1G": ["Eth21(Port21)"] + } + }, + "Ethernet22": { + "index": "22", + "lanes": "47", + "breakout_modes": { + "1x1G": ["Eth22(Port22)"] + } + }, + "Ethernet23": { + "index": "23", + "lanes": "48", + "breakout_modes": { + "1x1G": ["Eth23(Port23)"] + } + }, + "Ethernet24": { + "index": "24", + "lanes": "1", + "breakout_modes": { + "1x1G": ["Eth24(Port24)"] + } + }, + "Ethernet25": { + "index": "25", + "lanes": "2", + "breakout_modes": { + "1x1G": ["Eth25(Port25)"] + } + }, + "Ethernet26": { + "index": "26", + "lanes": "3", + "breakout_modes": { + "1x1G": ["Eth26(Port26)"] + } + }, + "Ethernet27": { + "index": "27", + "lanes": "4", + "breakout_modes": { + "1x1G": ["Eth27(Port27)"] + } + }, + "Ethernet28": { + "index": "28", + "lanes": "5", + "breakout_modes": { + "1x1G": ["Eth28(Port28)"] + } + }, + "Ethernet29": { + "index": "29", + "lanes": "6", + "breakout_modes": { + "1x1G": ["Eth29(Port29)"] + } + }, + "Ethernet30": { + "index": "30", + "lanes": "7", + "breakout_modes": { + "1x1G": ["Eth30(Port30)"] + } + }, + "Ethernet31": { + "index": "31", + "lanes": "8", + "breakout_modes": { + "1x1G": ["Eth31(Port31)"] + } + }, + "Ethernet32": { + "index": "32", + "lanes": "9", + "breakout_modes": { + "1x1G": ["Eth32(Port32)"] + } + }, + "Ethernet33": { + "index": "33", + "lanes": "10", + "breakout_modes": { + "1x1G": ["Eth33(Port33)"] + } + }, + "Ethernet34": { + "index": "34", + "lanes": "11", + "breakout_modes": { + "1x1G": ["Eth34(Port34)"] + } + }, + "Ethernet35": { + "index": "35", + "lanes": "12", + "breakout_modes": { + "1x1G": ["Eth35(Port35)"] + } + }, + "Ethernet36": { + "index": "36", + "lanes": "13", + "breakout_modes": { + "1x1G": ["Eth36(Port36)"] + } + }, + "Ethernet37": { + "index": "37", + "lanes": "14", + "breakout_modes": { + "1x1G": ["Eth37(Port37)"] + } + }, + "Ethernet38": { + "index": "38", + "lanes": "15", + "breakout_modes": { + "1x1G": ["Eth38(Port38)"] + } + }, + "Ethernet39": { + "index": "39", + "lanes": "16", + "breakout_modes": { + "1x1G": ["Eth39(Port39)"] + } + }, + "Ethernet40": { + "index": "40", + "lanes": "17", + "breakout_modes": { + "1x1G": ["Eth40(Port40)"] + } + }, + "Ethernet41": { + "index": "41", + "lanes": "18", + "breakout_modes": { + "1x1G": ["Eth41(Port41)"] + } + }, + "Ethernet42": { + "index": "42", + "lanes": "19", + "breakout_modes": { + "1x1G": ["Eth42(Port42)"] + } + }, + "Ethernet43": { + "index": "43", + "lanes": "20", + "breakout_modes": { + "1x1G": ["Eth43(Port43)"] + } + }, + "Ethernet44": { + "index": "44", + "lanes": "21", + "breakout_modes": { + "1x1G": ["Eth44(Port44)"] + } + }, + "Ethernet45": { + "index": "45", + "lanes": "22", + "breakout_modes": { + "1x1G": ["Eth45(Port45)"] + } + }, + "Ethernet46": { + "index": "46", + "lanes": "23", + "breakout_modes": { + "1x1G": ["Eth46(Port46)"] + } + }, + "Ethernet47": { + "index": "47", + "lanes": "24", + "breakout_modes": { + "1x1G": ["Eth47(Port47)"] + } + }, + "Ethernet48": { + "index": "48", + "lanes": "57", + "breakout_modes": { + "1x10G": ["Eth48(Port48)"] + } + }, + "Ethernet49": { + "index": "49", + "lanes": "58", + "breakout_modes": { + "1x10G": ["Eth49(Port49)"] + } + }, + "Ethernet50": { + "index": "50", + "lanes": "59", + "breakout_modes": { + "1x10G": ["Eth50(Port50)"] + } + }, + "Ethernet51": { + "index": "51", + "lanes": "60", + "breakout_modes": { + "1x10G": ["Eth51(Port51)"] + } + }, + "Ethernet52": { + "index": "52", + "lanes": "64", + "breakout_modes": { + "1x10G": ["Eth52(Port52)"] + } + }, + "Ethernet53": { + "index": "53", + "lanes": "63", + "breakout_modes": { + "1x10G": ["Eth53(Port53)"] + } + }, + "Ethernet54": { + "index": "54", + "lanes": "62", + "breakout_modes": { + "1x10G": ["Eth54(Port54)"] + } + }, + "Ethernet55": { + "index": "55", + "lanes": "61", + "breakout_modes": { + "1x10G": ["Eth55(Port55)"] + } + } + } +} + diff --git a/device/ufispace/x86_64-ufispace_s6301_56st-r0/platform_asic b/device/ufispace/x86_64-ufispace_s6301_56st-r0/platform_asic new file mode 100644 index 000000000000..960467652765 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s6301_56st-r0/platform_asic @@ -0,0 +1 @@ +broadcom diff --git a/device/ufispace/x86_64-ufispace_s6301_56st-r0/platform_components.json b/device/ufispace/x86_64-ufispace_s6301_56st-r0/platform_components.json new file mode 100644 index 000000000000..a581c95c99c2 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s6301_56st-r0/platform_components.json @@ -0,0 +1,10 @@ +{ + "chassis": { + "x86_64-ufispace_s6301_56st-r0": { + "component": { + "CPLD1": { }, + "BIOS": { } + } + } + } +} diff --git a/device/ufispace/x86_64-ufispace_s6301_56st-r0/platform_env.conf b/device/ufispace/x86_64-ufispace_s6301_56st-r0/platform_env.conf new file mode 100644 index 000000000000..6313683d8830 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s6301_56st-r0/platform_env.conf @@ -0,0 +1,2 @@ +SYNCD_SHM_SIZE=256m + diff --git a/device/ufispace/x86_64-ufispace_s6301_56st-r0/pmon_daemon_control.json b/device/ufispace/x86_64-ufispace_s6301_56st-r0/pmon_daemon_control.json new file mode 100644 index 000000000000..e348e0168fa5 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s6301_56st-r0/pmon_daemon_control.json @@ -0,0 +1,9 @@ +{ + "skip_pcied": false, + "skip_fancontrol": false, + "skip_thermalctld": false, + "skip_ledd": true, + "skip_xcvrd": false, + "skip_psud": false, + "skip_syseepromd": false +} diff --git a/device/ufispace/x86_64-ufispace_s6301_56st-r0/sensors.conf b/device/ufispace/x86_64-ufispace_s6301_56st-r0/sensors.conf new file mode 100644 index 000000000000..b1a69433405b --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s6301_56st-r0/sensors.conf @@ -0,0 +1 @@ +# libsensors configuration file diff --git a/device/ufispace/x86_64-ufispace_s6301_56st-r0/system_health_monitoring_config.json b/device/ufispace/x86_64-ufispace_s6301_56st-r0/system_health_monitoring_config.json new file mode 100644 index 000000000000..43816ab55169 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s6301_56st-r0/system_health_monitoring_config.json @@ -0,0 +1,15 @@ +{ + "services_to_ignore": [], + "devices_to_ignore": [ + "asic", + "psu", + "fan" + ], + "user_defined_checkers": [], + "polling_interval": 60, + "led_color": { + "fault": "yellow_blink", + "normal": "green", + "booting": "green_blink" + } +} \ No newline at end of file diff --git a/device/ufispace/x86_64-ufispace_s7801_54xs-r0/UFISPACE-S7801-54XS/hwsku.json b/device/ufispace/x86_64-ufispace_s7801_54xs-r0/UFISPACE-S7801-54XS/hwsku.json new file mode 100644 index 000000000000..db472c5ce225 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s7801_54xs-r0/UFISPACE-S7801-54XS/hwsku.json @@ -0,0 +1,166 @@ +{ + "interfaces": { + "Ethernet0": { + "default_brkout_mode": "1x10G" + }, + "Ethernet1": { + "default_brkout_mode": "1x10G" + }, + "Ethernet2": { + "default_brkout_mode": "1x10G" + }, + "Ethernet3": { + "default_brkout_mode": "1x10G" + }, + "Ethernet4": { + "default_brkout_mode": "1x10G" + }, + "Ethernet5": { + "default_brkout_mode": "1x10G" + }, + "Ethernet6": { + "default_brkout_mode": "1x10G" + }, + "Ethernet7": { + "default_brkout_mode": "1x10G" + }, + "Ethernet8": { + "default_brkout_mode": "1x10G" + }, + "Ethernet9": { + "default_brkout_mode": "1x10G" + }, + "Ethernet10": { + "default_brkout_mode": "1x10G" + }, + "Ethernet11": { + "default_brkout_mode": "1x10G" + }, + "Ethernet12": { + "default_brkout_mode": "1x10G" + }, + "Ethernet13": { + "default_brkout_mode": "1x10G" + }, + "Ethernet14": { + "default_brkout_mode": "1x10G" + }, + "Ethernet15": { + "default_brkout_mode": "1x10G" + }, + "Ethernet16": { + "default_brkout_mode": "1x10G" + }, + "Ethernet17": { + "default_brkout_mode": "1x10G" + }, + "Ethernet18": { + "default_brkout_mode": "1x10G" + }, + "Ethernet19": { + "default_brkout_mode": "1x10G" + }, + "Ethernet20": { + "default_brkout_mode": "1x10G" + }, + "Ethernet21": { + "default_brkout_mode": "1x10G" + }, + "Ethernet22": { + "default_brkout_mode": "1x10G" + }, + "Ethernet23": { + "default_brkout_mode": "1x10G" + }, + "Ethernet24": { + "default_brkout_mode": "1x10G" + }, + "Ethernet25": { + "default_brkout_mode": "1x10G" + }, + "Ethernet26": { + "default_brkout_mode": "1x10G" + }, + "Ethernet27": { + "default_brkout_mode": "1x10G" + }, + "Ethernet28": { + "default_brkout_mode": "1x10G" + }, + "Ethernet29": { + "default_brkout_mode": "1x10G" + }, + "Ethernet30": { + "default_brkout_mode": "1x10G" + }, + "Ethernet31": { + "default_brkout_mode": "1x10G" + }, + "Ethernet32": { + "default_brkout_mode": "1x10G" + }, + "Ethernet33": { + "default_brkout_mode": "1x10G" + }, + "Ethernet34": { + "default_brkout_mode": "1x10G" + }, + "Ethernet35": { + "default_brkout_mode": "1x10G" + }, + "Ethernet36": { + "default_brkout_mode": "1x10G" + }, + "Ethernet37": { + "default_brkout_mode": "1x10G" + }, + "Ethernet38": { + "default_brkout_mode": "1x10G" + }, + "Ethernet39": { + "default_brkout_mode": "1x10G" + }, + "Ethernet40": { + "default_brkout_mode": "1x10G" + }, + "Ethernet41": { + "default_brkout_mode": "1x10G" + }, + "Ethernet42": { + "default_brkout_mode": "1x10G" + }, + "Ethernet43": { + "default_brkout_mode": "1x10G" + }, + "Ethernet44": { + "default_brkout_mode": "1x10G" + }, + "Ethernet45": { + "default_brkout_mode": "1x10G" + }, + "Ethernet46": { + "default_brkout_mode": "1x10G" + }, + "Ethernet47": { + "default_brkout_mode": "1x10G" + }, + "Ethernet48": { + "default_brkout_mode": "1x100G[40G]" + }, + "Ethernet52": { + "default_brkout_mode": "1x100G[40G]" + }, + "Ethernet56": { + "default_brkout_mode": "1x100G[40G]" + }, + "Ethernet60": { + "default_brkout_mode": "1x100G[40G]" + }, + "Ethernet64": { + "default_brkout_mode": "1x100G[40G]" + }, + "Ethernet68": { + "default_brkout_mode": "1x100G[40G]" + } + } +} diff --git a/device/ufispace/x86_64-ufispace_s7801_54xs-r0/UFISPACE-S7801-54XS/sai.profile b/device/ufispace/x86_64-ufispace_s7801_54xs-r0/UFISPACE-S7801-54XS/sai.profile new file mode 100644 index 000000000000..c712c4511d4c --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s7801_54xs-r0/UFISPACE-S7801-54XS/sai.profile @@ -0,0 +1 @@ +SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/td3-x5-s7801-54xs.config.bcm diff --git a/device/ufispace/x86_64-ufispace_s7801_54xs-r0/UFISPACE-S7801-54XS/td3-x5-s7801-54xs.config.bcm b/device/ufispace/x86_64-ufispace_s7801_54xs-r0/UFISPACE-S7801-54XS/td3-x5-s7801-54xs.config.bcm new file mode 100644 index 000000000000..bfbc045d02eb --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s7801_54xs-r0/UFISPACE-S7801-54XS/td3-x5-s7801-54xs.config.bcm @@ -0,0 +1,502 @@ +# cfg version: r1, 20230628 + +pbmp_xport_xe=0x7fffffffffffffffdfffffffffffffffe + + +#FC 0 +phy_chain_tx_polarity_flip_physical{1}=0x0 +phy_chain_tx_polarity_flip_physical{2}=0x0 +phy_chain_tx_polarity_flip_physical{3}=0x0 +phy_chain_tx_polarity_flip_physical{4}=0x0 + +phy_chain_rx_polarity_flip_physical{1}=0x0 +phy_chain_rx_polarity_flip_physical{2}=0x0 +phy_chain_rx_polarity_flip_physical{3}=0x0 +phy_chain_rx_polarity_flip_physical{4}=0x0 + +phy_chain_tx_lane_map_physical{1.0}=0x0123 +phy_chain_rx_lane_map_physical{1.0}=0x0123 + +#FC 1 +phy_chain_tx_polarity_flip_physical{5}=0x0 +phy_chain_tx_polarity_flip_physical{6}=0x0 +phy_chain_tx_polarity_flip_physical{7}=0x0 +phy_chain_tx_polarity_flip_physical{8}=0x0 + +phy_chain_rx_polarity_flip_physical{5}=0x1 +phy_chain_rx_polarity_flip_physical{6}=0x1 +phy_chain_rx_polarity_flip_physical{7}=0x1 +phy_chain_rx_polarity_flip_physical{8}=0x1 + +phy_chain_tx_lane_map_physical{5.0}=0x0123 +phy_chain_rx_lane_map_physical{5.0}=0x0123 + +#FC 2 +phy_chain_tx_polarity_flip_physical{9}=0x0 +phy_chain_tx_polarity_flip_physical{10}=0x0 +phy_chain_tx_polarity_flip_physical{11}=0x0 +phy_chain_tx_polarity_flip_physical{12}=0x0 + +phy_chain_rx_polarity_flip_physical{9}=0x1 +phy_chain_rx_polarity_flip_physical{10}=0x1 +phy_chain_rx_polarity_flip_physical{11}=0x1 +phy_chain_rx_polarity_flip_physical{12}=0x1 + +phy_chain_tx_lane_map_physical{9.0}=0x0123 +phy_chain_rx_lane_map_physical{9.0}=0x0123 + +#FC 3 +phy_chain_tx_polarity_flip_physical{13}=0x0 +phy_chain_tx_polarity_flip_physical{14}=0x0 +phy_chain_tx_polarity_flip_physical{15}=0x0 +phy_chain_tx_polarity_flip_physical{16}=0x0 + +phy_chain_rx_polarity_flip_physical{13}=0x1 +phy_chain_rx_polarity_flip_physical{14}=0x1 +phy_chain_rx_polarity_flip_physical{15}=0x1 +phy_chain_rx_polarity_flip_physical{16}=0x1 + +phy_chain_tx_lane_map_physical{13.0}=0x0123 +phy_chain_rx_lane_map_physical{13.0}=0x0123 + +#FC 4 +phy_chain_tx_polarity_flip_physical{17}=0x0 +phy_chain_tx_polarity_flip_physical{18}=0x0 +phy_chain_tx_polarity_flip_physical{19}=0x0 +phy_chain_tx_polarity_flip_physical{20}=0x0 + +phy_chain_rx_polarity_flip_physical{17}=0x0 +phy_chain_rx_polarity_flip_physical{18}=0x0 +phy_chain_rx_polarity_flip_physical{19}=0x0 +phy_chain_rx_polarity_flip_physical{20}=0x0 + +phy_chain_tx_lane_map_physical{17.0}=0x0123 +phy_chain_rx_lane_map_physical{17.0}=0x0123 + +#FC 5 +phy_chain_tx_polarity_flip_physical{21}=0x0 +phy_chain_tx_polarity_flip_physical{22}=0x0 +phy_chain_tx_polarity_flip_physical{23}=0x0 +phy_chain_tx_polarity_flip_physical{24}=0x0 + +phy_chain_rx_polarity_flip_physical{21}=0x1 +phy_chain_rx_polarity_flip_physical{22}=0x1 +phy_chain_rx_polarity_flip_physical{23}=0x1 +phy_chain_rx_polarity_flip_physical{24}=0x1 + +phy_chain_tx_lane_map_physical{21.0}=0x0123 +phy_chain_rx_lane_map_physical{21.0}=0x0123 + +#FC 6 +phy_chain_tx_polarity_flip_physical{25}=0x0 +phy_chain_tx_polarity_flip_physical{26}=0x0 +phy_chain_tx_polarity_flip_physical{27}=0x0 +phy_chain_tx_polarity_flip_physical{28}=0x0 + +phy_chain_rx_polarity_flip_physical{25}=0x1 +phy_chain_rx_polarity_flip_physical{26}=0x1 +phy_chain_rx_polarity_flip_physical{27}=0x1 +phy_chain_rx_polarity_flip_physical{28}=0x1 + +phy_chain_tx_lane_map_physical{25.0}=0x0123 +phy_chain_rx_lane_map_physical{25.0}=0x0123 + +#FC 7 not use +phy_chain_tx_polarity_flip_physical{29}=0x0 +phy_chain_tx_polarity_flip_physical{30}=0x0 +phy_chain_tx_polarity_flip_physical{31}=0x0 +phy_chain_tx_polarity_flip_physical{32}=0x0 + +phy_chain_rx_polarity_flip_physical{29}=0x0 +phy_chain_rx_polarity_flip_physical{30}=0x0 +phy_chain_rx_polarity_flip_physical{31}=0x0 +phy_chain_rx_polarity_flip_physical{32}=0x0 + +phy_chain_tx_lane_map_physical{29.0}=0x0123 +phy_chain_rx_lane_map_physical{29.0}=0x0123 + +#FC 8 +phy_chain_tx_polarity_flip_physical{33}=0x1 +phy_chain_tx_polarity_flip_physical{34}=0x0 +phy_chain_tx_polarity_flip_physical{35}=0x1 +phy_chain_tx_polarity_flip_physical{36}=0x1 + +phy_chain_rx_polarity_flip_physical{33}=0x0 +phy_chain_rx_polarity_flip_physical{34}=0x0 +phy_chain_rx_polarity_flip_physical{35}=0x1 +phy_chain_rx_polarity_flip_physical{36}=0x0 + +phy_chain_tx_lane_map_physical{33.0}=0x3120 +phy_chain_rx_lane_map_physical{33.0}=0x0213 + +#FC 9 +phy_chain_tx_polarity_flip_physical{37}=0x0 +phy_chain_tx_polarity_flip_physical{38}=0x0 +phy_chain_tx_polarity_flip_physical{39}=0x1 +phy_chain_tx_polarity_flip_physical{40}=0x1 + +phy_chain_rx_polarity_flip_physical{37}=0x1 +phy_chain_rx_polarity_flip_physical{38}=0x1 +phy_chain_rx_polarity_flip_physical{39}=0x0 +phy_chain_rx_polarity_flip_physical{40}=0x0 + +phy_chain_tx_lane_map_physical{37.0}=0x2031 +phy_chain_rx_lane_map_physical{37.0}=0x1302 + +#FC 10 +phy_chain_tx_polarity_flip_physical{41}=0x0 +phy_chain_tx_polarity_flip_physical{42}=0x0 +phy_chain_tx_polarity_flip_physical{43}=0x0 +phy_chain_tx_polarity_flip_physical{44}=0x0 + +phy_chain_rx_polarity_flip_physical{41}=0x1 +phy_chain_rx_polarity_flip_physical{42}=0x1 +phy_chain_rx_polarity_flip_physical{43}=0x1 +phy_chain_rx_polarity_flip_physical{44}=0x1 + +phy_chain_tx_lane_map_physical{41.0}=0x3210 +phy_chain_rx_lane_map_physical{41.0}=0x0123 + +#FC 11 +phy_chain_tx_polarity_flip_physical{45}=0x0 +phy_chain_tx_polarity_flip_physical{46}=0x0 +phy_chain_tx_polarity_flip_physical{47}=0x1 +phy_chain_tx_polarity_flip_physical{48}=0x1 + +phy_chain_rx_polarity_flip_physical{45}=0x0 +phy_chain_rx_polarity_flip_physical{46}=0x0 +phy_chain_rx_polarity_flip_physical{47}=0x0 +phy_chain_rx_polarity_flip_physical{48}=0x1 + +phy_chain_tx_lane_map_physical{45.0}=0x3120 +phy_chain_rx_lane_map_physical{45.0}=0x2130 + +#FC 12 +phy_chain_tx_polarity_flip_physical{49}=0x1 +phy_chain_tx_polarity_flip_physical{50}=0x0 +phy_chain_tx_polarity_flip_physical{51}=0x0 +phy_chain_tx_polarity_flip_physical{52}=0x1 + +phy_chain_rx_polarity_flip_physical{49}=0x0 +phy_chain_rx_polarity_flip_physical{50}=0x1 +phy_chain_rx_polarity_flip_physical{51}=0x1 +phy_chain_rx_polarity_flip_physical{52}=0x0 + +phy_chain_tx_lane_map_physical{49.0}=0x3201 +phy_chain_rx_lane_map_physical{49.0}=0x1023 + +#FC 13 +phy_chain_tx_polarity_flip_physical{53}=0x0 +phy_chain_tx_polarity_flip_physical{54}=0x0 +phy_chain_tx_polarity_flip_physical{55}=0x1 +phy_chain_tx_polarity_flip_physical{56}=0x1 + +phy_chain_rx_polarity_flip_physical{53}=0x0 +phy_chain_rx_polarity_flip_physical{54}=0x0 +phy_chain_rx_polarity_flip_physical{55}=0x0 +phy_chain_rx_polarity_flip_physical{56}=0x1 + +phy_chain_tx_lane_map_physical{53.0}=0x3120 +phy_chain_rx_lane_map_physical{53.0}=0x2130 + +#FC 14 +phy_chain_tx_polarity_flip_physical{57}=0x1 +phy_chain_tx_polarity_flip_physical{58}=0x0 +phy_chain_tx_polarity_flip_physical{59}=0x0 +phy_chain_tx_polarity_flip_physical{60}=0x1 + +phy_chain_rx_polarity_flip_physical{57}=0x0 +phy_chain_rx_polarity_flip_physical{58}=0x1 +phy_chain_rx_polarity_flip_physical{59}=0x1 +phy_chain_rx_polarity_flip_physical{60}=0x0 + +phy_chain_tx_lane_map_physical{57.0}=0x3201 +phy_chain_rx_lane_map_physical{57.0}=0x1023 + +#FC 15 +phy_chain_tx_polarity_flip_physical{61}=0x0 +phy_chain_tx_polarity_flip_physical{62}=0x0 +phy_chain_tx_polarity_flip_physical{63}=0x0 +phy_chain_tx_polarity_flip_physical{64}=0x0 + +phy_chain_rx_polarity_flip_physical{61}=0x0 +phy_chain_rx_polarity_flip_physical{62}=0x0 +phy_chain_rx_polarity_flip_physical{63}=0x0 +phy_chain_rx_polarity_flip_physical{64}=0x0 + +phy_chain_tx_lane_map_physical{61.0}=0x3210 +phy_chain_rx_lane_map_physical{61.0}=0x3210 + +#FC 16 +phy_chain_tx_polarity_flip_physical{65}=0x0 +phy_chain_tx_polarity_flip_physical{66}=0x0 +phy_chain_tx_polarity_flip_physical{67}=0x0 +phy_chain_tx_polarity_flip_physical{68}=0x0 + +phy_chain_rx_polarity_flip_physical{65}=0x1 +phy_chain_rx_polarity_flip_physical{66}=0x1 +phy_chain_rx_polarity_flip_physical{67}=0x1 +phy_chain_rx_polarity_flip_physical{68}=0x1 + +phy_chain_tx_lane_map_physical{65.0}=0x3210 +phy_chain_rx_lane_map_physical{65.0}=0x3210 + +#FC 17 +phy_chain_tx_polarity_flip_physical{69}=0x0 +phy_chain_tx_polarity_flip_physical{70}=0x0 +phy_chain_tx_polarity_flip_physical{71}=0x0 +phy_chain_tx_polarity_flip_physical{72}=0x0 + +phy_chain_rx_polarity_flip_physical{69}=0x1 +phy_chain_rx_polarity_flip_physical{70}=0x1 +phy_chain_rx_polarity_flip_physical{71}=0x1 +phy_chain_rx_polarity_flip_physical{72}=0x1 + +phy_chain_tx_lane_map_physical{69.0}=0x3210 +phy_chain_rx_lane_map_physical{69.0}=0x3210 + +#FC 18 +phy_chain_tx_polarity_flip_physical{73}=0x0 +phy_chain_tx_polarity_flip_physical{74}=0x0 +phy_chain_tx_polarity_flip_physical{75}=0x0 +phy_chain_tx_polarity_flip_physical{76}=0x0 + +phy_chain_rx_polarity_flip_physical{73}=0x1 +phy_chain_rx_polarity_flip_physical{74}=0x1 +phy_chain_rx_polarity_flip_physical{75}=0x1 +phy_chain_rx_polarity_flip_physical{76}=0x1 + +phy_chain_tx_lane_map_physical{73.0}=0x3210 +phy_chain_rx_lane_map_physical{73.0}=0x3210 + +#FC 19 not use +phy_chain_tx_polarity_flip_physical{77}=0x0 +phy_chain_tx_polarity_flip_physical{78}=0x0 +phy_chain_tx_polarity_flip_physical{79}=0x0 +phy_chain_tx_polarity_flip_physical{80}=0x0 + +phy_chain_rx_polarity_flip_physical{77}=0x0 +phy_chain_rx_polarity_flip_physical{78}=0x0 +phy_chain_rx_polarity_flip_physical{79}=0x0 +phy_chain_rx_polarity_flip_physical{80}=0x0 + +phy_chain_tx_lane_map_physical{77.0}=0x3210 +phy_chain_rx_lane_map_physical{77.0}=0x3210 + + +#FC0 sfp28 port 0-3 +portmap_1=1:10 +portmap_2=2:10 +portmap_3=3:10 +portmap_4=4:10 + +#FC1 sfp28 port 4-7 +portmap_5=5:10 +portmap_6=6:10 +portmap_7=7:10 +portmap_8=8:10 + +#FC2 sfp28 port 8-11 +portmap_9=9:10 +portmap_10=10:10 +portmap_11=11:10 +portmap_12=12:10 + +#FC3 sfp28 port 12-15 +portmap_13=13:10 +portmap_14=14:10 +portmap_15=15:10 +portmap_16=16:10 + +#FC4 sfp28 port 16-19 +portmap_17=17:10 +portmap_18=18:10 +portmap_19=19:10 +portmap_20=20:10 + +#FC5 sfp28 port 20-23 +portmap_21=21:10 +portmap_22=22:10 +portmap_23=23:10 +portmap_24=24:10 + +#FC6 sfp28 port 24-27 +portmap_25=25:10 +portmap_26=26:10 +portmap_27=27:10 +portmap_28=28:10 + +#FC7 not use + +#FC10 sfp28 port 28-31 +portmap_33=41:10 +portmap_34=42:10 +portmap_35=43:10 +portmap_36=44:10 + +#FC15 sfp28 port 32-35 +portmap_37=61:10 +portmap_38=62:10 +portmap_39=63:10 +portmap_40=64:10 + +#FC16 sfp28 port 36-39 +portmap_41=65:10 +portmap_42=66:10 +portmap_43=67:10 +portmap_44=68:10 + +#FC17 sfp28 port 40-43 +portmap_45=69:10 +portmap_46=70:10 +portmap_47=71:10 +portmap_48=72:10 + +#FC18 sfp28 port 44-47 +portmap_49=73:10 +portmap_50=74:10 +portmap_51=75:10 +portmap_52=76:10 + +#FC9 qsfp port 48 +portmap_29=37:100 + +#FC8 qsfp port 49 +portmap_30=33:100 + +#FC11 qsfp port 50 +portmap_53=45:100 + +#FC12 qsfp port 51 +portmap_54=49:100 + +#FC13 qsfp port 52 +portmap_55=53:100 + +#FC14 qsfp port 53 +portmap_59=57:100 + +#FC19 not use + +# dport +dport_map_enable=1 + +dport_map_port_1=1 +dport_map_port_2=2 +dport_map_port_3=3 +dport_map_port_4=4 +dport_map_port_5=5 +dport_map_port_6=6 +dport_map_port_7=7 +dport_map_port_8=8 +dport_map_port_9=9 +dport_map_port_10=10 +dport_map_port_11=11 +dport_map_port_12=12 +dport_map_port_13=13 +dport_map_port_14=14 +dport_map_port_15=15 +dport_map_port_16=16 +dport_map_port_17=17 +dport_map_port_18=18 +dport_map_port_19=19 +dport_map_port_20=20 +dport_map_port_21=21 +dport_map_port_22=22 +dport_map_port_23=23 +dport_map_port_24=24 +dport_map_port_25=25 +dport_map_port_26=26 +dport_map_port_27=27 +dport_map_port_28=28 +dport_map_port_33=29 +dport_map_port_34=30 +dport_map_port_35=31 +dport_map_port_36=32 +dport_map_port_37=33 +dport_map_port_38=34 +dport_map_port_39=35 +dport_map_port_40=36 +dport_map_port_41=37 +dport_map_port_42=38 +dport_map_port_43=39 +dport_map_port_44=40 +dport_map_port_45=41 +dport_map_port_46=42 +dport_map_port_47=43 +dport_map_port_48=44 +dport_map_port_49=45 +dport_map_port_50=46 +dport_map_port_51=47 +dport_map_port_52=48 +dport_map_port_29=49 +dport_map_port_30=50 +dport_map_port_53=51 +dport_map_port_54=52 +dport_map_port_55=53 +dport_map_port_59=54 + +# cfg for timing +ptp_bs_fref_0=50000000 +ptp_bs_fref_1=50000000 + +port_flex_enable=1 +oversubscribe_mode=1 +core_clock_frequency=1525 + +#25G,10G and 1G support +serdes_10g_at_25g_vco=1 +serdes_1000x_at_25g_vco=1 + +l2xmsg_mode=1 +l2xmsg_hostbuf_size=16384 +module_64ports=0 + +#Interrupts and Parity +max_vp_lags=0 +schan_intr_enable=0 +tdma_timeout_usec=5000000 +stable_size=0x5500000 + +#Default L3 profile +l2_mem_entries=40960 +l3_alpm_enable=2 +l3_alpm_ipv6_128b_bkt_rsvd=1 +l3_mem_entries=40960 + +#Tunnels +use_all_splithorizon_groups=1 +sai_tunnel_support=1 +bcm_tunnel_term_compatible_mode=1 + +#RIOT Enable +riot_enable=1 +riot_overlay_l3_intf_mem_size=8192 +riot_overlay_l3_egress_mem_size=32768 +l3_ecmp_levels=2 +riot_overlay_ecmp_resilient_hash_size=16384 +pfc_deadlock_seq_control=1 + +mem_cache_enable=0 +ifp_inports_support_enable=1 +ipv6_lpm_128b_enable=0x1 +l3_max_ecmp_mode=1 +lpm_scaling_enable=0 +bcm_num_cos=10 +default_cpu_tx_queue=9 +mmu_lossless=0 +host_as_route_disable=1 +sai_fast_convergence_support=1 +flow_init_mode=1 +sai_interface_type_auto_detect=0 +mpls_mem_entries=16384 +vlan_xlate_1_mem_entries=65536 +vlan_xlate_2_mem_entries=16384 +sai_nbr_bcast_ifp_optimized=1 +sai_brcm_sonic_acl_enhancements=1 + +# Reduced Trap Group QSET for BRCM Sonic +sai_brcm_sonic_trap_group=1 +l2_entry_used_as_my_station=1 +multi_hash_recurse_depth_l3=2 + diff --git a/device/ufispace/x86_64-ufispace_s7801_54xs-r0/custom_led.bin b/device/ufispace/x86_64-ufispace_s7801_54xs-r0/custom_led.bin new file mode 100644 index 000000000000..af49a6baba15 Binary files /dev/null and b/device/ufispace/x86_64-ufispace_s7801_54xs-r0/custom_led.bin differ diff --git a/device/ufispace/x86_64-ufispace_s7801_54xs-r0/default_sku b/device/ufispace/x86_64-ufispace_s7801_54xs-r0/default_sku new file mode 100644 index 000000000000..9cb01149fbce --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s7801_54xs-r0/default_sku @@ -0,0 +1 @@ +UFISPACE-S7801-54XS t1 diff --git a/device/ufispace/x86_64-ufispace_s7801_54xs-r0/fancontrol b/device/ufispace/x86_64-ufispace_s7801_54xs-r0/fancontrol new file mode 100644 index 000000000000..1234cd994f3f --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s7801_54xs-r0/fancontrol @@ -0,0 +1,10 @@ +# Configuration file generated by pwmconfig, changes will be lost +INTERVAL=10 +DEVPATH= +DEVNAME= +FCTEMPS= +FCFANS= +MINTEMP= +MAXTEMP= +MINSTART= +MINSTOP= diff --git a/device/ufispace/x86_64-ufispace_s7801_54xs-r0/installer.conf b/device/ufispace/x86_64-ufispace_s7801_54xs-r0/installer.conf new file mode 100644 index 000000000000..8f9944da69a6 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s7801_54xs-r0/installer.conf @@ -0,0 +1,4 @@ +CONSOLE_PORT=0x3f8 +CONSOLE_DEV=0 +CONSOLE_SPEED=115200 +ONIE_PLATFORM_EXTRA_CMDLINE_LINUX="module_blacklist=gpio_ich nomodeset pcie_aspm=off" diff --git a/device/ufispace/x86_64-ufispace_s7801_54xs-r0/led_proc_init.soc b/device/ufispace/x86_64-ufispace_s7801_54xs-r0/led_proc_init.soc new file mode 100644 index 000000000000..57ee7fedaf2b --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s7801_54xs-r0/led_proc_init.soc @@ -0,0 +1,3 @@ +m0 load 0 0x3800 /usr/share/sonic/platform/custom_led.bin +led auto on +led start diff --git a/device/ufispace/x86_64-ufispace_s7801_54xs-r0/pcie.yaml b/device/ufispace/x86_64-ufispace_s7801_54xs-r0/pcie.yaml new file mode 100644 index 000000000000..c2465f5e0b65 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s7801_54xs-r0/pcie.yaml @@ -0,0 +1,172 @@ +- bus: '00' + dev: '00' + fn: '0' + id: '1980' + name: 'Host bridge: Intel Corporation Atom Processor C3000 Series System Agent (rev + 11)' +- bus: '00' + dev: '04' + fn: '0' + id: 19a1 + name: 'Host bridge: Intel Corporation Atom Processor C3000 Series Error Registers + (rev 11)' +- bus: '00' + dev: '05' + fn: '0' + id: 19a2 + name: 'Generic system peripheral [0807]: Intel Corporation Atom Processor C3000 + Series Root Complex Event Collector (rev 11)' +- bus: '00' + dev: '06' + fn: '0' + id: 19a3 + name: 'PCI bridge: Intel Corporation Atom Processor C3000 Series Integrated QAT + Root Port (rev 11)' +- bus: '00' + dev: 09 + fn: '0' + id: 19a4 + name: 'PCI bridge: Intel Corporation Atom Processor C3000 Series PCI Express Root + Port #0 (rev 11)' +- bus: '00' + dev: 0a + fn: '0' + id: 19a5 + name: 'PCI bridge: Intel Corporation Atom Processor C3000 Series PCI Express Root + Port #1 (rev 11)' +- bus: '00' + dev: 0b + fn: '0' + id: 19a6 + name: 'PCI bridge: Intel Corporation Atom Processor C3000 Series PCI Express Root + Port #2 (rev 11)' +- bus: '00' + dev: 0e + fn: '0' + id: 19a8 + name: 'PCI bridge: Intel Corporation Atom Processor C3000 Series PCI Express Root + Port #4 (rev 11)' +- bus: '00' + dev: 0f + fn: '0' + id: 19a9 + name: 'PCI bridge: Intel Corporation Atom Processor C3000 Series PCI Express Root + Port #5 (rev 11)' +- bus: '00' + dev: '10' + fn: '0' + id: 19aa + name: 'PCI bridge: Intel Corporation Atom Processor C3000 Series PCI Express Root + Port #6 (rev 11)' +- bus: '00' + dev: '11' + fn: '0' + id: 19ab + name: 'PCI bridge: Intel Corporation Atom Processor C3000 Series PCI Express Root + Port #7 (rev 11)' +- bus: '00' + dev: '12' + fn: '0' + id: 19ac + name: 'System peripheral: Intel Corporation Atom Processor C3000 Series SMBus Contoller + - Host (rev 11)' +- bus: '00' + dev: '14' + fn: '0' + id: 19c2 + name: 'SATA controller: Intel Corporation Atom Processor C3000 Series SATA Controller + 1 (rev 11)' +- bus: '00' + dev: '15' + fn: '0' + id: 19d0 + name: 'USB controller: Intel Corporation Atom Processor C3000 Series USB 3.0 xHCI + Controller (rev 11)' +- bus: '00' + dev: '16' + fn: '0' + id: 19d1 + name: 'PCI bridge: Intel Corporation Atom Processor C3000 Series Integrated LAN + Root Port #0 (rev 11)' +- bus: '00' + dev: '17' + fn: '0' + id: 19d2 + name: 'PCI bridge: Intel Corporation Atom Processor C3000 Series Integrated LAN + Root Port #1 (rev 11)' +- bus: '00' + dev: '18' + fn: '0' + id: 19d3 + name: 'Communication controller: Intel Corporation Atom Processor C3000 Series ME + HECI 1 (rev 11)' +- bus: '00' + dev: 1c + fn: '0' + id: 19db + name: 'SD Host controller: Intel Corporation Device 19db (rev 11)' +- bus: '00' + dev: 1f + fn: '0' + id: 19dc + name: 'ISA bridge: Intel Corporation Atom Processor C3000 Series LPC or eSPI (rev + 11)' +- bus: '00' + dev: 1f + fn: '2' + id: 19de + name: 'Memory controller: Intel Corporation Atom Processor C3000 Series Power Management + Controller (rev 11)' +- bus: '00' + dev: 1f + fn: '4' + id: 19df + name: 'SMBus: Intel Corporation Atom Processor C3000 Series SMBus controller (rev + 11)' +- bus: '00' + dev: 1f + fn: '5' + id: 19e0 + name: 'Serial bus controller [0c80]: Intel Corporation Atom Processor C3000 Series + SPI Controller (rev 11)' +- bus: '01' + dev: '00' + fn: '0' + id: 19e2 + name: 'Co-processor: Intel Corporation Atom Processor C3000 Series QuickAssist Technology + (rev 11)' +- bus: '04' + dev: '00' + fn: '0' + id: b771 + name: 'Ethernet controller: Broadcom Inc. and subsidiaries Device b771 (rev 01)' +- bus: '06' + dev: '00' + fn: '0' + id: '1533' + name: 'Ethernet controller: Intel Corporation I210 Gigabit Network Connection (rev + 03)' +- bus: 09 + dev: '00' + fn: '0' + id: 15c3 + name: 'Ethernet controller: Intel Corporation Ethernet Connection X553 Backplane + (rev 11)' +- bus: 09 + dev: '00' + fn: '1' + id: 15c3 + name: 'Ethernet controller: Intel Corporation Ethernet Connection X553 Backplane + (rev 11)' +- bus: 0a + dev: '00' + fn: '0' + id: 15c3 + name: 'Ethernet controller: Intel Corporation Ethernet Connection X553 Backplane + (rev 11)' +- bus: 0a + dev: '00' + fn: '1' + id: 15c3 + name: 'Ethernet controller: Intel Corporation Ethernet Connection X553 Backplane + (rev 11)' diff --git a/device/ufispace/x86_64-ufispace_s7801_54xs-r0/pddf/pd-plugin.json b/device/ufispace/x86_64-ufispace_s7801_54xs-r0/pddf/pd-plugin.json new file mode 100644 index 000000000000..81ff5e283bc9 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s7801_54xs-r0/pddf/pd-plugin.json @@ -0,0 +1,97 @@ +{ + + "XCVR": + { + "xcvr_present": + { + "i2c": + { + "valmap-SFP": {"1":true, "0":false }, + "valmap-SFP28": {"1":true, "0":false }, + "valmap-QSFP28": {"1":true, "0":false }, + "valmap-QSFP-DD": {"1":true, "0":false} + } + }, + + "plug_status": + { + "inserted": "1", + "removed": "0" + } + }, + "PSU": + { + "psu_present": + { + "i2c": + { + "valmap": { "1":true, "0":false } + }, + "bmc": + { + "valmap": { "0x0280|":true, "0x0180|":false } + } + }, + + "psu_power_good": + { + "i2c": + { + "valmap": { "1": true, "0":false } + }, + "bmc": + { + "valmap": { "0x0280|":true, "0x0180|":false } + } + }, + + "psu_fan_dir": + { + "bmc": + { + "valmap": {"0": "UNKNOWN", "1":"INTAKE", "2":"EXHAUST"} + } + }, + + "psu_support_list": + [ + {"Manufacturer": "FSPGROUP", "Name": "YNEB0450BM", "MaxSpd": "PSU_FAN_MAX_SPEED_AC"}, + {"Manufacturer": "FSPGROUP", "Name": "YNEB0450AM", "MaxSpd": "PSU_FAN_MAX_SPEED_DC"}, + {"Manufacturer": "DELTA", "Name": "DPS-450AB-27", "MaxSpd": "PSU_FAN_MAX_SPEED_AC"}, + {"Manufacturer": "DELTA", "Name": "DPS-450AB-28", "MaxSpd": "PSU_FAN_MAX_SPEED_DC"} + ], + + "valmap": { + "PSU_FAN_MAX_SPEED":"20000", + "PSU_FAN_MAX_SPEED_AC":"20000", + "PSU_FAN_MAX_SPEED_DC":"18000" + } + }, + "FAN": + { + "direction": + { + "bmc": + { + "valmap": {"0": "UNKNOWN", "1":"INTAKE", "2":"EXHAUST"} + } + }, + + "present": + { + "i2c": + { + "valmap": {"1":true, "0":false} + }, + "bmc": + { + "valmap": { "0x0280|":true, "0x0180|":false, "Device Present":true, "Device Absent":false} + } + }, + "FAN_MAX_SPEED":"25000" + }, + "REBOOT_CAUSE": + { + "reboot_cause_file": "/host/reboot-cause/reboot-cause.txt" + } +} diff --git a/device/ufispace/x86_64-ufispace_s7801_54xs-r0/pddf/pddf-device.json b/device/ufispace/x86_64-ufispace_s7801_54xs-r0/pddf/pddf-device.json new file mode 100644 index 000000000000..7110b2ed6cc3 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s7801_54xs-r0/pddf/pddf-device.json @@ -0,0 +1,7850 @@ +{ + "PLATFORM": { + "num_psus": 2, + "num_fantrays": 5, + "num_fans_pertray": 1, + "num_ports": 54, + "num_temps": 8, + "pddf_dev_types": { + "description": "PDDF supported devices", + "CPLD": [ + "i2c_cpld" + ], + "PSU": [ + "psu_eeprom", + "psu_pmbus" + ], + "PORT_MODULE": [ + "pddf_xcvr" + ] + }, + "std_kos": [ + "i2c_i801", + "i2c_ismt", + "i2c_dev", + "i2c_mux_pca954x", + "coretemp", + "optoe", + "gpio-pca953x" + ], + "pddf_kos": [ + "pddf_client_module", + "pddf_cpld_module", + "pddf_cpld_driver", + "pddf_mux_module", + "pddf_xcvr_module", + "pddf_xcvr_driver_module", + "pddf_psu_driver_module", + "pddf_psu_module", + "pddf_fan_driver_module", + "pddf_fan_module", + "pddf_led_module", + "pddf_gpio_module" + ], + "custom_kos": [ + "x86-64-ufispace-s7801-54xs-lpc", + "x86-64-ufispace-s7801-54xs-sys-eeprom", + "pddf_custom_sysstatus_module" + ] + }, + "SYSTEM": { + "dev_info": { + "device_type": "CPU", + "device_name": "ROOT_COMPLEX", + "device_parent": null + }, + "i2c": { + "CONTROLLERS": [ + { + "dev_name": "i2c-1", + "dev": "SMBUS1" + }, + { + "dev_name": "i2c-0", + "dev": "SMBUS0" + } + ] + } + }, + "SMBUS0": { + "dev_info": { + "device_type": "SMBUS", + "device_name": "SMBUS0", + "device_parent": "SYSTEM" + }, + "i2c": { + "topo_info": { + "dev_addr": "0x0" + }, + "DEVICES": [ + { + "dev": "MUX3" + } + ] + } + }, + "SMBUS1": { + "dev_info": { + "device_type": "SMBUS", + "device_name": "SMBUS1", + "device_parent": "SYSTEM" + }, + "i2c": { + "topo_info": { + "dev_addr": "0x1" + }, + "DEVICES": [ + { + "dev": "MUX1" + }, + { + "dev": "MUX2" + } + ] + } + }, + "MUX1": { + "dev_info": { + "device_type": "MUX", + "device_name": "MUX1", + "device_parent": "SMBUS1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1", + "dev_addr": "0x70", + "dev_type": "pca9548" + }, + "dev_attr": { + "virt_bus": "0x2", + "idle_state": "-2" + }, + "channel": [ + { + "chn": "0", + "dev": "CPLD1" + }, + { + "chn": "0", + "dev": "CPLD2" + }, + { + "chn": "0", + "dev": "PSU1" + }, + { + "chn": "0", + "dev": "PSU2" + }, + { + "chn": "3", + "dev": "EEPROM1" + }, + { + "chn": "4", + "dev": "GPIO1" + }, + { + "chn": "4", + "dev": "GPIO2" + }, + { + "chn": "5", + "dev": "GPIO3" + }, + { + "chn": "5", + "dev": "GPIO4" + } + ] + } + }, + "MUX2": { + "dev_info": { + "device_type": "MUX", + "device_name": "MUX2", + "device_parent": "SMBUS1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1", + "dev_addr": "0x71", + "dev_type": "pca9548" + }, + "dev_attr": { + "virt_bus": "0xa", + "idle_state": "-2" + }, + "channel": [ + ] + } + }, + "MUX3": { + "dev_info": { + "device_type": "MUX", + "device_name": "MUX3", + "device_parent": "SMBUS0" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x0", + "dev_addr": "0x72", + "dev_type": "pca9548" + }, + "dev_attr": { + "virt_bus": "0x12", + "idle_state": "-2" + }, + "channel": [ + { + "chn": "0", + "dev": "MUX4" + }, + { + "chn": "1", + "dev": "MUX5" + }, + { + "chn": "2", + "dev": "MUX6" + }, + { + "chn": "3", + "dev": "MUX7" + }, + { + "chn": "4", + "dev": "MUX8" + }, + { + "chn": "5", + "dev": "MUX9" + }, + { + "chn": "6", + "dev": "MUX10" + } + ] + } + }, + "MUX4": { + "dev_info": { + "device_type": "MUX", + "device_name": "MUX4", + "device_parent": "MUX3" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x12", + "dev_addr": "0x73", + "dev_type": "pca9548" + }, + "dev_attr": { + "virt_bus": "0x1a", + "idle_state": "-2" + }, + "channel": [ + { + "chn": "0", + "dev": "PORT1" + }, + { + "chn": "1", + "dev": "PORT2" + }, + { + "chn": "2", + "dev": "PORT3" + }, + { + "chn": "3", + "dev": "PORT4" + }, + { + "chn": "4", + "dev": "PORT5" + }, + { + "chn": "5", + "dev": "PORT6" + }, + { + "chn": "6", + "dev": "PORT7" + }, + { + "chn": "7", + "dev": "PORT8" + } + ] + } + }, + "MUX5": { + "dev_info": { + "device_type": "MUX", + "device_name": "MUX5", + "device_parent": "MUX3" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x13", + "dev_addr": "0x73", + "dev_type": "pca9548" + }, + "dev_attr": { + "virt_bus": "0x22", + "idle_state": "-2" + }, + "channel": [ + { + "chn": "0", + "dev": "PORT9" + }, + { + "chn": "1", + "dev": "PORT10" + }, + { + "chn": "2", + "dev": "PORT11" + }, + { + "chn": "3", + "dev": "PORT12" + }, + { + "chn": "4", + "dev": "PORT13" + }, + { + "chn": "5", + "dev": "PORT14" + }, + { + "chn": "6", + "dev": "PORT15" + }, + { + "chn": "7", + "dev": "PORT16" + } + ] + } + }, + "MUX6": { + "dev_info": { + "device_type": "MUX", + "device_name": "MUX6", + "device_parent": "MUX3" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x14", + "dev_addr": "0x73", + "dev_type": "pca9548" + }, + "dev_attr": { + "virt_bus": "0x2a", + "idle_state": "-2" + }, + "channel": [ + { + "chn": "0", + "dev": "PORT17" + }, + { + "chn": "1", + "dev": "PORT18" + }, + { + "chn": "2", + "dev": "PORT19" + }, + { + "chn": "3", + "dev": "PORT20" + }, + { + "chn": "4", + "dev": "PORT21" + }, + { + "chn": "5", + "dev": "PORT22" + }, + { + "chn": "6", + "dev": "PORT23" + }, + { + "chn": "7", + "dev": "PORT24" + } + ] + } + }, + "MUX7": { + "dev_info": { + "device_type": "MUX", + "device_name": "MUX7", + "device_parent": "MUX3" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x15", + "dev_addr": "0x73", + "dev_type": "pca9548" + }, + "dev_attr": { + "virt_bus": "032", + "idle_state": "-2" + }, + "channel": [ + { + "chn": "0", + "dev": "PORT25" + }, + { + "chn": "1", + "dev": "PORT26" + }, + { + "chn": "2", + "dev": "PORT27" + }, + { + "chn": "3", + "dev": "PORT28" + }, + { + "chn": "4", + "dev": "PORT29" + }, + { + "chn": "5", + "dev": "PORT30" + }, + { + "chn": "6", + "dev": "PORT31" + }, + { + "chn": "7", + "dev": "PORT32" + } + ] + } + }, + "MUX8": { + "dev_info": { + "device_type": "MUX", + "device_name": "MUX8", + "device_parent": "MUX3" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x16", + "dev_addr": "0x73", + "dev_type": "pca9548" + }, + "dev_attr": { + "virt_bus": "03a", + "idle_state": "-2" + }, + "channel": [ + { + "chn": "0", + "dev": "PORT33" + }, + { + "chn": "1", + "dev": "PORT34" + }, + { + "chn": "2", + "dev": "PORT35" + }, + { + "chn": "3", + "dev": "PORT36" + }, + { + "chn": "4", + "dev": "PORT37" + }, + { + "chn": "5", + "dev": "PORT38" + }, + { + "chn": "6", + "dev": "PORT39" + }, + { + "chn": "7", + "dev": "PORT40" + } + ] + } + }, + "MUX9": { + "dev_info": { + "device_type": "MUX", + "device_name": "MUX9", + "device_parent": "MUX3" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x17", + "dev_addr": "0x73", + "dev_type": "pca9548" + }, + "dev_attr": { + "virt_bus": "042", + "idle_state": "-2" + }, + "channel": [ + { + "chn": "0", + "dev": "PORT41" + }, + { + "chn": "1", + "dev": "PORT42" + }, + { + "chn": "2", + "dev": "PORT43" + }, + { + "chn": "3", + "dev": "PORT44" + }, + { + "chn": "4", + "dev": "PORT45" + }, + { + "chn": "5", + "dev": "PORT46" + }, + { + "chn": "6", + "dev": "PORT47" + }, + { + "chn": "7", + "dev": "PORT48" + } + ] + } + }, + "MUX10": { + "dev_info": { + "device_type": "MUX", + "device_name": "MUX10", + "device_parent": "MUX3" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x18", + "dev_addr": "0x73", + "dev_type": "pca9548" + }, + "dev_attr": { + "virt_bus": "04a", + "idle_state": "-2" + }, + "channel": [ + { + "chn": "0", + "dev": "PORT49" + }, + { + "chn": "1", + "dev": "PORT50" + }, + { + "chn": "2", + "dev": "PORT51" + }, + { + "chn": "3", + "dev": "PORT52" + }, + { + "chn": "4", + "dev": "PORT53" + }, + { + "chn": "5", + "dev": "PORT54" + } + ] + } + }, + "CPLD1": { + "dev_info": { + "device_type": "CPLD", + "device_name": "CPLD1", + "device_parent": "MUX1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2", + "dev_addr": "0x30", + "dev_type": "i2c_cpld" + }, + "dev_attr": {} + } + }, + "CPLD2": { + "dev_info": { + "device_type": "CPLD", + "device_name": "CPLD2", + "device_parent": "MUX1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2", + "dev_addr": "0x31", + "dev_type": "i2c_cpld" + }, + "dev_attr": {} + } + }, + "SYSSTATUS": { + "dev_info": { + "device_type": "SYSSTAT", + "device_name": "SYSSTATUS" + }, + "dev_attr": {}, + "attr_list": + [ + { + "attr_name": "board_sku_id", + "attr_devaddr": "0x30", + "attr_offset": "0x0", + "attr_mask": "0xff", + "attr_len": "0x1" + }, + { + "attr_name": "board_hw_id", + "attr_devaddr": "0x30", + "attr_offset": "0x1", + "attr_mask": "0x03", + "attr_len": "0x1" + }, + { + "attr_name": "board_deph_id", + "attr_devaddr": "0x30", + "attr_offset": "0x1", + "attr_mask": "0x4", + "attr_len": "0x1" + }, + { + "attr_name": "board_build_id", + "attr_devaddr": "0x30", + "attr_offset": "0x1", + "attr_mask": "0x18", + "attr_len": "0x1" + }, + { + "attr_name": "cpld1_major_ver", + "attr_devaddr": "0x30", + "attr_offset": "0x2", + "attr_mask": "0xc0", + "attr_len": "0x1" + }, + { + "attr_name": "cpld1_minor_ver", + "attr_devaddr": "0x30", + "attr_offset": "0x2", + "attr_mask": "0x3f", + "attr_len": "0x1" + }, + { + "attr_name": "cpld1_build", + "attr_devaddr": "0x30", + "attr_offset": "0x4", + "attr_mask": "0xff", + "attr_len": "0x1" + }, + { + "attr_name": "cpld2_major_ver", + "attr_devaddr": "0x31", + "attr_offset": "0x2", + "attr_mask": "0xc0", + "attr_len": "0x1" + }, + { + "attr_name": "cpld2_minor_ver", + "attr_devaddr": "0x31", + "attr_offset": "0x2", + "attr_mask": "0x3f", + "attr_len": "0x1" + }, + { + "attr_name": "cpld2_build", + "attr_devaddr": "0x31", + "attr_offset": "0x4", + "attr_mask": "0xff", + "attr_len": "0x1" + }, + { + "attr_name": "psu_status", + "attr_devaddr": "0x30", + "attr_offset": "0x51", + "attr_mask": "0xff", + "attr_len": "0x1" + }, + { + "attr_name": "system_led_psu", + "attr_devaddr": "0x30", + "attr_offset": "0x80", + "attr_mask": "0xff", + "attr_len": "0x1" + }, + { + "attr_name": "system_led_sys", + "attr_devaddr": "0x30", + "attr_offset": "0x81", + "attr_mask": "0xff", + "attr_len": "0x1" + }, + { + "attr_name": "system_led_sync", + "attr_devaddr": "0x30", + "attr_offset": "0x82", + "attr_mask": "0xff", + "attr_len": "0x1" + }, + { + "attr_name": "system_led_fan", + "attr_devaddr": "0x30", + "attr_offset": "0x83", + "attr_mask": "0xff", + "attr_len": "0x1" + }, + { + "attr_name": "system_led_id", + "attr_devaddr": "0x30", + "attr_offset": "0x84", + "attr_mask": "0xff", + "attr_len": "0x1" + } + ] + }, + "EEPROM1": { + "dev_info": { + "device_type": "EEPROM", + "device_name": "EEPROM1", + "device_parent": "MUX1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x5", + "dev_addr": "0x53", + "dev_type": "sys_eeprom" + }, + "dev_attr": { + "access_mode": "BLOCK" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "GPIO1": { + "dev_info": { + "device_type": "GPIO", + "device_name": "GPIO1", + "device_parent": "MUX1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x6", + "dev_addr": "0x22", + "dev_type": "tca6424" + }, + "dev_attr": { + "gpio_base": "0x1d0" + }, + "ports": [ + { + "port_num": "0", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "1", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "2", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "3", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "4", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "5", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "6", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "7", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "8", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "9", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "10", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "11", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "12", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "13", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "14", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "15", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "16", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "17", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "18", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "19", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "20", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "21", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "22", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "23", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + } + ] + } + }, + "GPIO2": { + "dev_info": { + "device_type": "GPIO", + "device_name": "GPIO2", + "device_parent": "MUX1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x6", + "dev_addr": "0x23", + "dev_type": "tca6424" + }, + "dev_attr": { + "gpio_base": "0x1a0" + }, + "ports": [ + { + "port_num": "0", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "1", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "2", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "3", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "4", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "5", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "6", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "7", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "8", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "9", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "10", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "11", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "12", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "13", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "14", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "15", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "16", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "17", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "18", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "19", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "20", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "21", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "22", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "23", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + } + ] + } + }, + "GPIO3": { + "dev_info": { + "device_type": "GPIO", + "device_name": "GPIO3", + "device_parent": "MUX1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x7", + "dev_addr": "0x22", + "dev_type": "tca6424" + }, + "dev_attr": { + "gpio_base": "0x1e8" + }, + "ports": [ + { + "port_num": "0", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "1", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "2", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "3", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "4", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "5", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "6", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "7", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "8", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "9", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "10", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "11", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "12", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "13", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "14", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "15", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "16", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "17", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "18", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "19", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "20", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "21", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "22", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "23", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + } + ] + } + }, + "GPIO4": { + "dev_info": { + "device_type": "GPIO", + "device_name": "GPIO4", + "device_parent": "MUX1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x7", + "dev_addr": "0x23", + "dev_type": "tca6424" + }, + "dev_attr": { + "gpio_base": "0x1b8" + }, + "ports": [ + { + "port_num": "0", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "1", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "2", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "3", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "4", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "5", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "6", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "7", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "8", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "9", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "10", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "11", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "12", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "13", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "14", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "15", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "16", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "17", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "18", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "19", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "20", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "21", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "22", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "23", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + } + ] + } + }, + "TEMP1": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TEMP1", + "device_parent": "SMBUS0" + }, + "dev_attr": { + "display_name": "TEMP_MAC" + }, + "bmc": { + "ipmitool": { + "attr_list": [ + { + "attr_name": "temp1_input", + "bmc_cmd": "ipmitool sdr -c get TEMP_MAC", + "raw": "0", + "field_name": "TEMP_MAC", + "field_pos": "2", + "separator": "," + }, + { + "attr_name": "temp1_high_crit_threshold", + "bmc_cmd": "ipmitool sdr -c get TEMP_MAC", + "raw": "0", + "field_name": "TEMP_MAC", + "field_pos": "12", + "separator": "," + }, + { + "attr_name": "temp1_high_threshold", + "bmc_cmd": "ipmitool sdr -c get TEMP_MAC", + "raw": "0", + "field_name": "TEMP_MAC", + "field_pos": "13", + "separator": "," + } + ] + } + } + }, + "TEMP2": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TEMP2", + "device_parent": "SMBUS0" + }, + "dev_attr": { + "display_name": "TEMP_ENV_MACCASE" + }, + "bmc": { + "ipmitool": { + "attr_list": [ + { + "attr_name": "temp1_input", + "bmc_cmd": "ipmitool sdr -c get TEMP_ENV_MACCASE", + "raw": "0", + "field_name": "TEMP_ENV_MACCASE", + "field_pos": "2", + "separator": "," + }, + { + "attr_name": "temp1_high_crit_threshold", + "bmc_cmd": "ipmitool sdr -c get TEMP_ENV_MACCASE", + "raw": "0", + "field_name": "TEMP_ENV_MACCASE", + "field_pos": "12", + "separator": "," + }, + { + "attr_name": "temp1_high_threshold", + "bmc_cmd": "ipmitool sdr -c get TEMP_ENV_MACCASE", + "raw": "0", + "field_name": "TEMP_ENV_MACCASE", + "field_pos": "13", + "separator": "," + } + ] + } + } + }, + "TEMP3": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TEMP3", + "device_parent": "SMBUS0" + }, + "dev_attr": { + "display_name": "TEMP_ENV_PSUCASE" + }, + "bmc": { + "ipmitool": { + "attr_list": [ + { + "attr_name": "temp1_input", + "bmc_cmd": "ipmitool sdr -c get TEMP_ENV_PSUCASE", + "raw": "0", + "field_name": "TEMP_ENV_PSUCASE", + "field_pos": "2", + "separator": "," + }, + { + "attr_name": "temp1_high_crit_threshold", + "bmc_cmd": "ipmitool sdr -c get TEMP_ENV_PSUCASE", + "raw": "0", + "field_name": "TEMP_ENV_PSUCASE", + "field_pos": "12", + "separator": "," + }, + { + "attr_name": "temp1_high_threshold", + "bmc_cmd": "ipmitool sdr -c get TEMP_ENV_PSUCASE", + "raw": "0", + "field_name": "TEMP_ENV_PSUCASE", + "field_pos": "13", + "separator": "," + } + ] + } + } + }, + "TEMP4": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TEMP4", + "device_parent": "SMBUS0" + }, + "dev_attr": { + "display_name": "TEMP_ENV_FANCONN" + }, + "bmc": { + "ipmitool": { + "attr_list": [ + { + "attr_name": "temp1_input", + "bmc_cmd": "ipmitool sdr -c get TEMP_ENV_FANCONN", + "raw": "0", + "field_name": "TEMP_ENV_FANCONN", + "field_pos": "2", + "separator": "," + }, + { + "attr_name": "temp1_high_crit_threshold", + "bmc_cmd": "ipmitool sdr -c get TEMP_ENV_FANCONN", + "raw": "0", + "field_name": "TEMP_ENV_FANCONN", + "field_pos": "12", + "separator": "," + }, + { + "attr_name": "temp1_high_threshold", + "bmc_cmd": "ipmitool sdr -c get TEMP_ENV_FANCONN", + "raw": "0", + "field_name": "TEMP_ENV_FANCONN", + "field_pos": "13", + "separator": "," + } + ] + } + } + }, + "TEMP5": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TEMP5", + "device_parent": "SMBUS0" + }, + "dev_attr": { + "display_name": "TEMP_ENV_FANCARD" + }, + "bmc": { + "ipmitool": { + "attr_list": [ + { + "attr_name": "temp1_input", + "bmc_cmd": "ipmitool sdr -c get TEMP_ENV_FANCARD", + "raw": "0", + "field_name": "TEMP_ENV_FANCARD", + "field_pos": "2", + "separator": "," + }, + { + "attr_name": "temp1_high_crit_threshold", + "bmc_cmd": "ipmitool sdr -c get TEMP_ENV_FANCARD", + "raw": "0", + "field_name": "TEMP_ENV_FANCARD", + "field_pos": "12", + "separator": "," + }, + { + "attr_name": "temp1_high_threshold", + "bmc_cmd": "ipmitool sdr -c get TEMP_ENV_FANCARD", + "raw": "0", + "field_name": "TEMP_ENV_FANCARD", + "field_pos": "13", + "separator": "," + } + ] + } + } + }, + "TEMP6": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TEMP6", + "device_parent": "SMBUS0" + }, + "dev_attr": { + "display_name": "TEMP_ENV_BMC" + }, + "bmc": { + "ipmitool": { + "attr_list": [ + { + "attr_name": "temp1_input", + "bmc_cmd": "ipmitool sdr -c get TEMP_ENV_BMC", + "raw": "0", + "field_name": "TEMP_ENV_BMC", + "field_pos": "2", + "separator": "," + }, + { + "attr_name": "temp1_high_crit_threshold", + "bmc_cmd": "ipmitool sdr -c get TEMP_ENV_BMC", + "raw": "0", + "field_name": "TEMP_ENV_BMC", + "field_pos": "12", + "separator": "," + }, + { + "attr_name": "temp1_high_threshold", + "bmc_cmd": "ipmitool sdr -c get TEMP_ENV_BMC", + "raw": "0", + "field_name": "TEMP_ENV_BMC", + "field_pos": "13", + "separator": "," + } + ] + } + } + }, + "TEMP7": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TEMP7", + "device_parent": "SMBUS0" + }, + "dev_attr": { + "display_name": "TEMP_PSU0_TEMP1" + }, + "bmc": { + "ipmitool": { + "attr_list": [ + { + "attr_name": "temp1_input", + "bmc_cmd": "ipmitool sdr -c get PSU0_TEMP1 | sed -e 's/,,/,0,/g' -e 's/,,/,0,/g'", + "raw": "0", + "field_name": "PSU0_TEMP1", + "field_pos": "2", + "separator": "," + }, + { + "attr_name": "temp1_high_crit_threshold", + "bmc_cmd": "ipmitool sdr -c get PSU0_TEMP1", + "raw": "0", + "field_name": "PSU0_TEMP1", + "field_pos": "12", + "separator": "," + }, + { + "attr_name": "temp1_high_threshold", + "bmc_cmd": "ipmitool sdr -c get PSU0_TEMP1", + "raw": "0", + "field_name": "PSU0_TEMP1", + "field_pos": "13", + "separator": "," + } + ] + } + } + }, + "TEMP8": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TEMP8", + "device_parent": "SMBUS0" + }, + "dev_attr": { + "display_name": "TEMP_PSU1_TEMP1" + }, + "bmc": { + "ipmitool": { + "attr_list": [ + { + "attr_name": "temp1_input", + "bmc_cmd": "ipmitool sdr -c get PSU1_TEMP1 | sed -e 's/,,/,0,/g' -e 's/,,/,0,/g'", + "raw": "0", + "field_name": "PSU1_TEMP1", + "field_pos": "2", + "separator": "," + }, + { + "attr_name": "temp1_high_crit_threshold", + "bmc_cmd": "ipmitool sdr -c get PSU1_TEMP1", + "raw": "0", + "field_name": "PSU1_TEMP1", + "field_pos": "12", + "separator": "," + }, + { + "attr_name": "temp1_high_threshold", + "bmc_cmd": "ipmitool sdr -c get PSU1_TEMP1", + "raw": "0", + "field_name": "PSU1_TEMP1", + "field_pos": "13", + "separator": "," + } + ] + } + } + }, + "PSU1": { + "dev_info": { + "device_type": "PSU", + "device_name": "PSU1", + "device_parent": "MUX1" + }, + "dev_attr": { + "dev_idx": "1", + "num_psu_fans": "1" + }, + "i2c": { + "interface": [ + { "itf":"eeprom", "dev":"PSU1-EEPROM" } + ] + }, + "bmc": { + "ipmitool": { + "attr_list": [ + { + "attr_name": "psu_temp1_input", + "bmc_cmd": "ipmitool sdr -c get PSU0_TEMP1 | sed -e 's/,,/,0,/g' -e 's/,,/,0,/g'", + "raw": "0", + "field_name": "PSU0_TEMP1", + "field_pos": "2", + "mult": "1000", + "separator": "," + }, + { + "attr_name": "psu_fan1_speed_rpm", + "bmc_cmd": "ipmitool sdr -c get PSU0_FAN1 | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "field_name": "PSU0_FAN1", + "field_pos": "2", + "separator": "," + }, + { + "attr_name": "psu_v_out", + "bmc_cmd": "ipmitool sdr -c get PSU0_VOUT | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "field_name": "PSU0_VOUT", + "field_pos": "2", + "mult": "1000", + "separator": "," + }, + { + "attr_name": "psu_i_out", + "bmc_cmd": "ipmitool sdr -c get PSU0_IOUT | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "field_name": "PSU0_IOUT", + "field_pos": "2", + "mult": "1000", + "separator": "," + }, + { + "attr_name": "psu_mfr_id", + "bmc_cmd": "_rv=$(ipmitool fru print 1 2>/dev/null | tr -s ' ' | cut -d' ' -f3-5 | grep 'Manufacturer') && echo $_rv || echo 'Manufacturer : N/A'", + "raw": "0", + "separator": ":", + "field_name": "Manufacturer", + "field_pos": "2" + }, + { + "attr_name": "psu_model_name", + "bmc_cmd": "_rv=$(ipmitool fru print 1 2>/dev/null | tr -s ' ' | cut -d' ' -f3-5 | grep 'Name') && echo $_rv || echo 'Name : N/A'", + "raw": "0", + "separator": ":", + "field_name": "Name", + "field_pos": "2" + }, + { + "attr_name": "psu_serial_num", + "bmc_cmd": "_rv=$(ipmitool fru print 1 2>/dev/null | tr -s ' ' | cut -d' ' -f3-5 | grep 'Serial') && echo $_rv || echo 'Serial : N/A'", + "raw": "0", + "separator": ":", + "field_name": "Serial", + "field_pos": "2" + }, + { + "attr_name": "psu_fan_dir", + "bmc_cmd": "ipmitool raw 0x3c 0x30 0x0 | xargs | cut -d' ' -f1", + "raw": "1", + "type": "raw" + } + ] + } + } + }, + "PSU1-EEPROM": { + "dev_info": { + "device_type": "PSU-EEPROM", + "device_name": "PSU1-EEPROM", + "device_parent": "MUX1", + "virt_parent": "PSU1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2", + "dev_addr": "0x50", + "dev_type": "psu_eeprom" + }, + "attr_list": [ + { + "attr_name":"psu_present", + "attr_devaddr":"0x30", + "attr_devtype":"cpld", + "attr_offset":"0x51", + "attr_mask":"0x1", + "attr_cmpval":"0x0", + "attr_len":"1" + }, + { + "attr_name":"psu_power_good", + "attr_devaddr":"0x30", + "attr_devtype":"cpld", + "attr_offset":"0x51", + "attr_mask":"0x10", + "attr_cmpval":"0x10", + "attr_len":"1" + } + ] + } + }, + "PSU2": { + "dev_info": { + "device_type": "PSU", + "device_name": "PSU2", + "device_parent": "MUX1" + }, + "dev_attr": { + "dev_idx": "2", + "num_psu_fans": "1" + }, + "i2c": { + "interface": [ + { "itf":"eeprom", "dev":"PSU2-EEPROM" } + ] + }, + "bmc": { + "ipmitool": { + "attr_list": [ + { + "attr_name": "psu_temp1_input", + "bmc_cmd": "ipmitool sdr -c get PSU1_TEMP1 | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "field_name": "PSU1_TEMP1", + "field_pos": "2", + "mult": "1000", + "separator": "," + }, + { + "attr_name": "psu_fan1_speed_rpm", + "bmc_cmd": "ipmitool sdr -c get PSU1_FAN1 | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "field_name": "PSU1_FAN1", + "field_pos": "2", + "separator": "," + }, + { + "attr_name": "psu_v_out", + "bmc_cmd": "ipmitool sdr -c get PSU1_VOUT | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "field_name": "PSU1_VOUT", + "field_pos": "2", + "mult": "1000", + "separator": "," + }, + { + "attr_name": "psu_i_out", + "bmc_cmd": "ipmitool sdr -c get PSU1_IOUT | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "field_name": "PSU1_IOUT", + "field_pos": "2", + "mult": "1000", + "separator": "," + }, + { + "attr_name": "psu_mfr_id", + "bmc_cmd": "_rv=$(ipmitool fru print 2 2>/dev/null | tr -s ' ' | cut -d' ' -f3-5 | grep 'Manufacturer') && echo $_rv || echo 'Manufacturer : N/A'", + "raw": "0", + "separator": ":", + "field_name": "Manufacturer", + "field_pos": "2" + }, + { + "attr_name": "psu_model_name", + "bmc_cmd": "_rv=$(ipmitool fru print 2 2>/dev/null | tr -s ' ' | cut -d' ' -f3-5 | grep 'Name') && echo $_rv || echo 'Name : N/A'", + "raw": "0", + "separator": ":", + "field_name": "Name", + "field_pos": "2" + }, + { + "attr_name": "psu_serial_num", + "bmc_cmd": "_rv=$(ipmitool fru print 2 2>/dev/null | tr -s ' ' | cut -d' ' -f3-5 | grep 'Serial') && echo $_rv || echo 'Serial : N/A'", + "raw": "0", + "separator": ":", + "field_name": "Serial", + "field_pos": "2" + }, + + { + "attr_name": "psu_fan_dir", + "bmc_cmd": "ipmitool raw 0x3c 0x30 0x0 | xargs | cut -d' ' -f2", + "raw": "1", + "type": "raw" + } + ] + } + } + }, + "PSU2-EEPROM": { + "dev_info": { + "device_type": "PSU-EEPROM", + "device_name": "PSU2-EEPROM", + "device_parent": "MUX1", + "virt_parent": "PSU2" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2", + "dev_addr": "0x51", + "dev_type": "psu_eeprom" + }, + "attr_list": [ + { + "attr_name":"psu_present", + "attr_devaddr":"0x30", + "attr_devtype":"cpld", + "attr_offset":"0x51", + "attr_mask":"0x2", + "attr_cmpval":"0x0", + "attr_len":"1" + }, + { + "attr_name":"psu_power_good", + "attr_devaddr":"0x30", + "attr_devtype":"cpld", + "attr_offset":"0x51", + "attr_mask":"0x20", + "attr_cmpval":"0x20", + "attr_len":"1" + } + ] + } + }, + "FAN-CTRL": { + "dev_info": { + "device_type": "FAN", + "device_name": "FAN-CTRL", + "device_parent": "" + }, + "bmc": { + "ipmitool": { + "attr_list": [ + { + "attr_name": "fan1_present", + "bmc_cmd": "ipmitool sdr -c get FAN0_PRSNT_L", + "raw": "0", + "field_name": "FAN0_PRSNT_L", + "field_pos": "5", + "separator": "," + }, + { + "attr_name": "fan2_present", + "bmc_cmd": "ipmitool sdr -c get FAN1_PRSNT_L", + "raw": "0", + "field_name": "FAN1_PRSNT_L", + "field_pos": "5", + "separator": "," + }, + { + "attr_name": "fan3_present", + "bmc_cmd": "ipmitool sdr -c get FAN2_PRSNT_L", + "raw": "0", + "field_name": "FAN2_PRSNT_L", + "field_pos": "5", + "separator": "," + }, + { + "attr_name": "fan4_present", + "bmc_cmd": "ipmitool sdr -c get FAN3_PRSNT_L", + "raw": "0", + "field_name": "FAN3_PRSNT_L", + "field_pos": "5", + "separator": "," + }, + { + "attr_name": "fan5_present", + "bmc_cmd": "ipmitool sdr -c get FAN4_PRSNT_L", + "raw": "0", + "field_name": "FAN4_PRSNT_L", + "field_pos": "5", + "separator": "," + }, + { + "attr_name": "fan1_input", + "bmc_cmd": "ipmitool sdr -c get FAN0_RPM | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "field_name": "FAN0_RPM", + "field_pos": "2", + "separator": "," + }, + { + "attr_name": "fan2_input", + "bmc_cmd": "ipmitool sdr -c get FAN1_RPM | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "field_name": "FAN1_RPM", + "field_pos": "2", + "separator": "," + }, + { + "attr_name": "fan3_input", + "bmc_cmd": "ipmitool sdr -c get FAN2_RPM | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "field_name": "FAN2_RPM", + "field_pos": "2", + "separator": "," + }, + { + "attr_name": "fan4_input", + "bmc_cmd": "ipmitool sdr -c get FAN3_RPM | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "field_name": "FAN3_RPM", + "field_pos": "2", + "separator": "," + }, + { + "attr_name": "fan5_input", + "bmc_cmd": "ipmitool sdr -c get FAN4_RPM | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "field_name": "FAN4_RPM", + "field_pos": "2", + "separator": "," + }, + { + "attr_name": "fan1_direction", + "bmc_cmd": "ipmitool raw 0x3c 0x31 0x0 | xargs | cut -d' ' -f1", + "raw": "1", + "type": "raw" + }, + { + "attr_name": "fan2_direction", + "bmc_cmd": "ipmitool raw 0x3c 0x31 0x0 | xargs | cut -d' ' -f2", + "raw": "1", + "type": "raw" + }, + { + "attr_name": "fan3_direction", + "bmc_cmd": "ipmitool raw 0x3c 0x31 0x0 | xargs | cut -d' ' -f3", + "raw": "1", + "type": "raw" + }, + { + "attr_name": "fan4_direction", + "bmc_cmd": "ipmitool raw 0x3c 0x31 0x0 | xargs | cut -d' ' -f4", + "raw": "1", + "type": "raw" + }, + { + "attr_name": "fan5_direction", + "bmc_cmd": "ipmitool raw 0x3c 0x31 0x0 | xargs | cut -d' ' -f5", + "raw": "1", + "type": "raw" + } + ] + } + } + }, + "SYNC_LED": { + "dev_info": { + "device_type": "LED", + "device_name": "DIAG_LED" + }, + "dev_attr": { + "index": "0", + "flag": "rw" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "green", + "bits": "3:0", + "descr": "Green", + "value": "0x09;0x0b", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x82" + }, + { + "attr_name": "green_blink", + "bits": "3:0", + "descr": "Green Blinking", + "value": "0x0d;0x0f", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x82" + }, + { + "attr_name": "yellow", + "bits": "3:0", + "descr": "Yellow", + "value": "0x08;0x0a", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x82" + }, + { + "attr_name": "yellow_blink", + "bits": "3:0", + "descr": "Yellow Blinking", + "value": "0x0c;0x0e", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x82" + }, + { + "attr_name": "off", + "bits": "3:2", + "descr": "Off", + "value": "0x1;0x0", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x82" + } + ] + } + }, + "SYS_LED": { + "dev_info": { + "device_type": "LED", + "device_name": "SYS_LED" + }, + "dev_attr": { + "index": "0", + "flag": "rw" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "green", + "bits": "7:4", + "descr": "Green", + "value": "0x09;0x0b", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x81" + }, + { + "attr_name": "green_blink", + "bits": "7:4", + "descr": "Green Blinking", + "value": "0x0d;0x0f", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x81" + }, + { + "attr_name": "yellow", + "bits": "7:4", + "descr": "Yellow", + "value": "0x08;0x0a", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x81" + }, + { + "attr_name": "yellow_blink", + "bits": "7:4", + "descr": "Yellow Blinking", + "value": "0x0c;0x0e", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x81" + }, + { + "attr_name": "off", + "bits": "7:6", + "descr": "Off", + "value": "0x01;0x0", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x81" + } + ] + } + }, + "FAN_LED": { + "dev_info": { + "device_type": "LED", + "device_name": "FAN_LED" + }, + "dev_attr": { + "index": "0", + "flag": "ro" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "green", + "bits": "3:0", + "descr": "Green", + "value": "0x09;0x0b", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x83" + }, + { + "attr_name": "green_blink", + "bits": "3:0", + "descr": "Green Blinking", + "value": "0x0d;0x0f", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x83" + }, + { + "attr_name": "yellow", + "bits": "3:0", + "descr": "Yellow", + "value": "0x08;0x0a", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x83" + }, + { + "attr_name": "yellow_blink", + "bits": "3:0", + "descr": "Yellow Blinking", + "value": "0x0c;0x0e", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x83" + }, + { + "attr_name": "off", + "bits": "3", + "descr": "Off", + "value": "0x0", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x83" + } + ] + } + }, + "PSU1_LED": { + "dev_info": { + "device_type": "LED", + "device_name": "PSU_LED" + }, + "dev_attr": { + "index": "0", + "flag": "ro" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "green", + "bits": "3:0", + "descr": "Green", + "value": "0x09;0x0b", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x80" + }, + { + "attr_name": "green_blink", + "bits": "3:0", + "descr": "Green Blinking", + "value": "0x0d;0x0f", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x80" + }, + { + "attr_name": "yellow", + "bits": "3:0", + "descr": "Yellow", + "value": "0x08;0x0a", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x80" + }, + { + "attr_name": "yellow_blink", + "bits": "3:0", + "descr": "Yellow Blinking", + "value": "0x0c;0x0e", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x80" + }, + { + "attr_name": "off", + "bits": "3", + "descr": "Off", + "value": "0x0", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x80" + } + ] + } + }, + "PSU2_LED": { + "dev_info": { + "device_type": "LED", + "device_name": "PSU_LED" + }, + "dev_attr": { + "index": "1", + "flag": "ro" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "green", + "bits": "7:4", + "descr": "Green", + "value": "0x09;0x0b", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x80" + }, + { + "attr_name": "green_blink", + "bits": "7:4", + "descr": "Green Blinking", + "value": "0x0d;0x0f", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x80" + }, + { + "attr_name": "yellow", + "bits": "7:4", + "descr": "Yellow", + "value": "0x08;0x0a", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x80" + }, + { + "attr_name": "yellow_blink", + "bits": "7:4", + "descr": "Yellow Blinking", + "value": "0x0c;0x0e", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x80" + }, + { + "attr_name": "off", + "bits": "7", + "descr": "Off", + "value": "0x0", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x80" + } + ] + } + }, + "ID_LED": { + "dev_info": { + "device_type": "LED", + "device_name": "LOC_LED" + }, + "dev_attr": { + "index": "0", + "flag": "rw" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "blue", + "bits": "3:1", + "descr": "Blue", + "value": "0x04;0x05", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x84" + }, + { + "attr_name": "blue_blink", + "bits": "3:1", + "descr": "Blue Blinking", + "value": "0x06;0x07", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x84" + }, + { + "attr_name": "off", + "bits": "3:2", + "descr": "Off", + "value": "0x01;0x0", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x84" + } + ] + } + }, + "PORT1": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT1", + "device_parent": "MUX4" + }, + "dev_attr": { + "dev_idx": "1" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT1-EEPROM" + }, + { + "itf": "control", + "dev": "PORT1-CTRL" + } + ] + } + }, + "PORT1-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT1-EEPROM", + "device_parent": "MUX4", + "virt_parent": "PORT1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1a", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT1-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT1-CTRL", + "device_parent": "MUX4", + "virt_parent": "PORT1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1a", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x10", + "attr_mask": "0x0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x40", + "attr_mask": "0x0", + "attr_cmpval": "0x1", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x46", + "attr_mask": "0x0", + "attr_cmpval": "0x1", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x70", + "attr_mask": "0x0", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT2": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT2", + "device_parent": "MUX4" + }, + "dev_attr": { + "dev_idx": "2" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT2-EEPROM" + }, + { + "itf": "control", + "dev": "PORT2-CTRL" + } + ] + } + }, + "PORT2-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT2-EEPROM", + "device_parent": "MUX4", + "virt_parent": "PORT2" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1b", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT2-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT2-CTRL", + "device_parent": "MUX4", + "virt_parent": "PORT2" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1b", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x10", + "attr_mask": "0x1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x40", + "attr_mask": "0x1", + "attr_cmpval": "0x2", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x46", + "attr_mask": "0x1", + "attr_cmpval": "0x2", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x70", + "attr_mask": "0x1", + "attr_cmpval": "0x2", + "attr_len": "1" + } + ] + } + }, + "PORT3": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT3", + "device_parent": "MUX4" + }, + "dev_attr": { + "dev_idx": "3" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT3-EEPROM" + }, + { + "itf": "control", + "dev": "PORT3-CTRL" + } + ] + } + }, + "PORT3-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT3-EEPROM", + "device_parent": "MUX4", + "virt_parent": "PORT3" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1c", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT3-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT3-CTRL", + "device_parent": "MUX4", + "virt_parent": "PORT3" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1c", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x10", + "attr_mask": "0x2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x40", + "attr_mask": "0x2", + "attr_cmpval": "0x4", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x46", + "attr_mask": "0x2", + "attr_cmpval": "0x4", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x70", + "attr_mask": "0x2", + "attr_cmpval": "0x4", + "attr_len": "1" + } + ] + } + }, + "PORT4": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT4", + "device_parent": "MUX4" + }, + "dev_attr": { + "dev_idx": "4" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT4-EEPROM" + }, + { + "itf": "control", + "dev": "PORT4-CTRL" + } + ] + } + }, + "PORT4-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT4-EEPROM", + "device_parent": "MUX4", + "virt_parent": "PORT4" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1d", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT4-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT4-CTRL", + "device_parent": "MUX4", + "virt_parent": "PORT4" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1d", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x10", + "attr_mask": "0x3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x40", + "attr_mask": "0x3", + "attr_cmpval": "0x8", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x46", + "attr_mask": "0x3", + "attr_cmpval": "0x8", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x70", + "attr_mask": "0x3", + "attr_cmpval": "0x8", + "attr_len": "1" + } + ] + } + }, + "PORT5": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT5", + "device_parent": "MUX4" + }, + "dev_attr": { + "dev_idx": "5" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT5-EEPROM" + }, + { + "itf": "control", + "dev": "PORT5-CTRL" + } + ] + } + }, + "PORT5-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT5-EEPROM", + "device_parent": "MUX4", + "virt_parent": "PORT5" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1e", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT5-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT5-CTRL", + "device_parent": "MUX4", + "virt_parent": "PORT5" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1e", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x10", + "attr_mask": "0x4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x40", + "attr_mask": "0x4", + "attr_cmpval": "0x10", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x46", + "attr_mask": "0x4", + "attr_cmpval": "0x10", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x70", + "attr_mask": "0x4", + "attr_cmpval": "0x10", + "attr_len": "1" + } + ] + } + }, + "PORT6": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT6", + "device_parent": "MUX4" + }, + "dev_attr": { + "dev_idx": "6" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT6-EEPROM" + }, + { + "itf": "control", + "dev": "PORT6-CTRL" + } + ] + } + }, + "PORT6-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT6-EEPROM", + "device_parent": "MUX4", + "virt_parent": "PORT6" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1f", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT6-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT6-CTRL", + "device_parent": "MUX4", + "virt_parent": "PORT6" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1f", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x10", + "attr_mask": "0x5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x40", + "attr_mask": "0x5", + "attr_cmpval": "0x20", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x46", + "attr_mask": "0x5", + "attr_cmpval": "0x20", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x70", + "attr_mask": "0x5", + "attr_cmpval": "0x20", + "attr_len": "1" + } + ] + } + }, + "PORT7": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT7", + "device_parent": "MUX4" + }, + "dev_attr": { + "dev_idx": "7" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT7-EEPROM" + }, + { + "itf": "control", + "dev": "PORT7-CTRL" + } + ] + } + }, + "PORT7-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT7-EEPROM", + "device_parent": "MUX4", + "virt_parent": "PORT7" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x20", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT7-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT7-CTRL", + "device_parent": "MUX4", + "virt_parent": "PORT7" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x20", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x10", + "attr_mask": "0x6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x40", + "attr_mask": "0x6", + "attr_cmpval": "0x40", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x46", + "attr_mask": "0x6", + "attr_cmpval": "0x40", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x70", + "attr_mask": "0x6", + "attr_cmpval": "0x40", + "attr_len": "1" + } + ] + } + }, + "PORT8": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT8", + "device_parent": "MUX4" + }, + "dev_attr": { + "dev_idx": "8" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT8-EEPROM" + }, + { + "itf": "control", + "dev": "PORT8-CTRL" + } + ] + } + }, + "PORT8-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT8-EEPROM", + "device_parent": "MUX4", + "virt_parent": "PORT8" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x21", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT8-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT8-CTRL", + "device_parent": "MUX4", + "virt_parent": "PORT8" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x21", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x10", + "attr_mask": "0x7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x40", + "attr_mask": "0x7", + "attr_cmpval": "0x80", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x46", + "attr_mask": "0x7", + "attr_cmpval": "0x80", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x70", + "attr_mask": "0x7", + "attr_cmpval": "0x80", + "attr_len": "1" + } + ] + } + }, + "PORT9": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT9", + "device_parent": "MUX5" + }, + "dev_attr": { + "dev_idx": "9" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT9-EEPROM" + }, + { + "itf": "control", + "dev": "PORT9-CTRL" + } + ] + } + }, + "PORT9-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT9-EEPROM", + "device_parent": "MUX5", + "virt_parent": "PORT9" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x22", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT9-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT9-CTRL", + "device_parent": "MUX5", + "virt_parent": "PORT9" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x22", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x11", + "attr_mask": "0x0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x41", + "attr_mask": "0x0", + "attr_cmpval": "0x1", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x47", + "attr_mask": "0x0", + "attr_cmpval": "0x1", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x71", + "attr_mask": "0x0", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT10": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT10", + "device_parent": "MUX5" + }, + "dev_attr": { + "dev_idx": "10" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT10-EEPROM" + }, + { + "itf": "control", + "dev": "PORT10-CTRL" + } + ] + } + }, + "PORT10-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT10-EEPROM", + "device_parent": "MUX5", + "virt_parent": "PORT10" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x23", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT10-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT10-CTRL", + "device_parent": "MUX5", + "virt_parent": "PORT10" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x23", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x11", + "attr_mask": "0x1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x41", + "attr_mask": "0x1", + "attr_cmpval": "0x2", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x47", + "attr_mask": "0x1", + "attr_cmpval": "0x2", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x71", + "attr_mask": "0x1", + "attr_cmpval": "0x2", + "attr_len": "1" + } + ] + } + }, + "PORT11": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT11", + "device_parent": "MUX5" + }, + "dev_attr": { + "dev_idx": "11" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT11-EEPROM" + }, + { + "itf": "control", + "dev": "PORT11-CTRL" + } + ] + } + }, + "PORT11-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT11-EEPROM", + "device_parent": "MUX5", + "virt_parent": "PORT11" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x24", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT11-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT11-CTRL", + "device_parent": "MUX5", + "virt_parent": "PORT11" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x24", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x11", + "attr_mask": "0x2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x41", + "attr_mask": "0x2", + "attr_cmpval": "0x4", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x47", + "attr_mask": "0x2", + "attr_cmpval": "0x4", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x71", + "attr_mask": "0x2", + "attr_cmpval": "0x4", + "attr_len": "1" + } + ] + } + }, + "PORT12": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT12", + "device_parent": "MUX5" + }, + "dev_attr": { + "dev_idx": "12" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT12-EEPROM" + }, + { + "itf": "control", + "dev": "PORT12-CTRL" + } + ] + } + }, + "PORT12-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT12-EEPROM", + "device_parent": "MUX5", + "virt_parent": "PORT12" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x25", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT12-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT12-CTRL", + "device_parent": "MUX5", + "virt_parent": "PORT12" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x25", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x11", + "attr_mask": "0x3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x41", + "attr_mask": "0x3", + "attr_cmpval": "0x8", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x47", + "attr_mask": "0x3", + "attr_cmpval": "0x8", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x71", + "attr_mask": "0x3", + "attr_cmpval": "0x8", + "attr_len": "1" + } + ] + } + }, + "PORT13": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT13", + "device_parent": "MUX5" + }, + "dev_attr": { + "dev_idx": "13" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT13-EEPROM" + }, + { + "itf": "control", + "dev": "PORT13-CTRL" + } + ] + } + }, + "PORT13-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT13-EEPROM", + "device_parent": "MUX5", + "virt_parent": "PORT13" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x26", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT13-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT13-CTRL", + "device_parent": "MUX5", + "virt_parent": "PORT13" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x26", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x11", + "attr_mask": "0x4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x41", + "attr_mask": "0x4", + "attr_cmpval": "0x10", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x47", + "attr_mask": "0x4", + "attr_cmpval": "0x10", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x71", + "attr_mask": "0x4", + "attr_cmpval": "0x10", + "attr_len": "1" + } + ] + } + }, + "PORT14": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT14", + "device_parent": "MUX5" + }, + "dev_attr": { + "dev_idx": "14" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT14-EEPROM" + }, + { + "itf": "control", + "dev": "PORT14-CTRL" + } + ] + } + }, + "PORT14-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT14-EEPROM", + "device_parent": "MUX5", + "virt_parent": "PORT14" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x27", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT14-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT14-CTRL", + "device_parent": "MUX5", + "virt_parent": "PORT14" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x27", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x11", + "attr_mask": "0x5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x41", + "attr_mask": "0x5", + "attr_cmpval": "0x20", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x47", + "attr_mask": "0x5", + "attr_cmpval": "0x20", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x71", + "attr_mask": "0x5", + "attr_cmpval": "0x20", + "attr_len": "1" + } + ] + } + }, + "PORT15": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT15", + "device_parent": "MUX5" + }, + "dev_attr": { + "dev_idx": "15" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT15-EEPROM" + }, + { + "itf": "control", + "dev": "PORT15-CTRL" + } + ] + } + }, + "PORT15-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT15-EEPROM", + "device_parent": "MUX5", + "virt_parent": "PORT15" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x28", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT15-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT15-CTRL", + "device_parent": "MUX5", + "virt_parent": "PORT15" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x28", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x11", + "attr_mask": "0x6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x41", + "attr_mask": "0x6", + "attr_cmpval": "0x40", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x47", + "attr_mask": "0x6", + "attr_cmpval": "0x40", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x71", + "attr_mask": "0x6", + "attr_cmpval": "0x40", + "attr_len": "1" + } + ] + } + }, + "PORT16": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT16", + "device_parent": "MUX5" + }, + "dev_attr": { + "dev_idx": "16" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT16-EEPROM" + }, + { + "itf": "control", + "dev": "PORT16-CTRL" + } + ] + } + }, + "PORT16-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT16-EEPROM", + "device_parent": "MUX5", + "virt_parent": "PORT16" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x29", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT16-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT16-CTRL", + "device_parent": "MUX5", + "virt_parent": "PORT16" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x29", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x11", + "attr_mask": "0x7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x41", + "attr_mask": "0x7", + "attr_cmpval": "0x80", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x47", + "attr_mask": "0x7", + "attr_cmpval": "0x80", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x71", + "attr_mask": "0x7", + "attr_cmpval": "0x80", + "attr_len": "1" + } + ] + } + }, + "PORT17": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT17", + "device_parent": "MUX6" + }, + "dev_attr": { + "dev_idx": "17" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT17-EEPROM" + }, + { + "itf": "control", + "dev": "PORT17-CTRL" + } + ] + } + }, + "PORT17-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT17-EEPROM", + "device_parent": "MUX6", + "virt_parent": "PORT17" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2a", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT17-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT17-CTRL", + "device_parent": "MUX6", + "virt_parent": "PORT17" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2a", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x12", + "attr_mask": "0x0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x42", + "attr_mask": "0x0", + "attr_cmpval": "0x1", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x48", + "attr_mask": "0x0", + "attr_cmpval": "0x1", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x72", + "attr_mask": "0x0", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT18": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT18", + "device_parent": "MUX6" + }, + "dev_attr": { + "dev_idx": "18" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT18-EEPROM" + }, + { + "itf": "control", + "dev": "PORT18-CTRL" + } + ] + } + }, + "PORT18-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT18-EEPROM", + "device_parent": "MUX6", + "virt_parent": "PORT18" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2b", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT18-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT18-CTRL", + "device_parent": "MUX6", + "virt_parent": "PORT18" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2b", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x12", + "attr_mask": "0x1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x42", + "attr_mask": "0x1", + "attr_cmpval": "0x2", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x48", + "attr_mask": "0x1", + "attr_cmpval": "0x2", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x72", + "attr_mask": "0x1", + "attr_cmpval": "0x2", + "attr_len": "1" + } + ] + } + }, + "PORT19": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT19", + "device_parent": "MUX6" + }, + "dev_attr": { + "dev_idx": "19" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT19-EEPROM" + }, + { + "itf": "control", + "dev": "PORT19-CTRL" + } + ] + } + }, + "PORT19-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT19-EEPROM", + "device_parent": "MUX6", + "virt_parent": "PORT19" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2c", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT19-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT19-CTRL", + "device_parent": "MUX6", + "virt_parent": "PORT19" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2c", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x12", + "attr_mask": "0x2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x42", + "attr_mask": "0x2", + "attr_cmpval": "0x4", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x48", + "attr_mask": "0x2", + "attr_cmpval": "0x4", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x72", + "attr_mask": "0x2", + "attr_cmpval": "0x4", + "attr_len": "1" + } + ] + } + }, + "PORT20": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT20", + "device_parent": "MUX6" + }, + "dev_attr": { + "dev_idx": "20" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT20-EEPROM" + }, + { + "itf": "control", + "dev": "PORT20-CTRL" + } + ] + } + }, + "PORT20-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT20-EEPROM", + "device_parent": "MUX6", + "virt_parent": "PORT20" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2d", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT20-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT20-CTRL", + "device_parent": "MUX6", + "virt_parent": "PORT20" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2d", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x12", + "attr_mask": "0x3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x42", + "attr_mask": "0x3", + "attr_cmpval": "0x8", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x48", + "attr_mask": "0x3", + "attr_cmpval": "0x8", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x72", + "attr_mask": "0x3", + "attr_cmpval": "0x8", + "attr_len": "1" + } + ] + } + }, + "PORT21": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT21", + "device_parent": "MUX6" + }, + "dev_attr": { + "dev_idx": "21" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT21-EEPROM" + }, + { + "itf": "control", + "dev": "PORT21-CTRL" + } + ] + } + }, + "PORT21-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT21-EEPROM", + "device_parent": "MUX6", + "virt_parent": "PORT21" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2e", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT21-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT21-CTRL", + "device_parent": "MUX6", + "virt_parent": "PORT21" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2e", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x12", + "attr_mask": "0x4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x42", + "attr_mask": "0x4", + "attr_cmpval": "0x10", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x48", + "attr_mask": "0x4", + "attr_cmpval": "0x10", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x72", + "attr_mask": "0x4", + "attr_cmpval": "0x10", + "attr_len": "1" + } + ] + } + }, + "PORT22": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT22", + "device_parent": "MUX6" + }, + "dev_attr": { + "dev_idx": "22" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT22-EEPROM" + }, + { + "itf": "control", + "dev": "PORT22-CTRL" + } + ] + } + }, + "PORT22-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT22-EEPROM", + "device_parent": "MUX6", + "virt_parent": "PORT22" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2f", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT22-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT22-CTRL", + "device_parent": "MUX6", + "virt_parent": "PORT22" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2f", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x12", + "attr_mask": "0x5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x42", + "attr_mask": "0x5", + "attr_cmpval": "0x20", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x48", + "attr_mask": "0x5", + "attr_cmpval": "0x20", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x72", + "attr_mask": "0x5", + "attr_cmpval": "0x20", + "attr_len": "1" + } + ] + } + }, + "PORT23": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT23", + "device_parent": "MUX6" + }, + "dev_attr": { + "dev_idx": "23" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT23-EEPROM" + }, + { + "itf": "control", + "dev": "PORT23-CTRL" + } + ] + } + }, + "PORT23-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT23-EEPROM", + "device_parent": "MUX6", + "virt_parent": "PORT23" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x30", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT23-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT23-CTRL", + "device_parent": "MUX6", + "virt_parent": "PORT23" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x30", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x12", + "attr_mask": "0x6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x42", + "attr_mask": "0x6", + "attr_cmpval": "0x40", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x48", + "attr_mask": "0x6", + "attr_cmpval": "0x40", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x72", + "attr_mask": "0x6", + "attr_cmpval": "0x40", + "attr_len": "1" + } + ] + } + }, + "PORT24": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT24", + "device_parent": "MUX6" + }, + "dev_attr": { + "dev_idx": "24" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT24-EEPROM" + }, + { + "itf": "control", + "dev": "PORT24-CTRL" + } + ] + } + }, + "PORT24-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT24-EEPROM", + "device_parent": "MUX6", + "virt_parent": "PORT24" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x31", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT24-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT24-CTRL", + "device_parent": "MUX6", + "virt_parent": "PORT24" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x31", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x12", + "attr_mask": "0x7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x42", + "attr_mask": "0x7", + "attr_cmpval": "0x80", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x48", + "attr_mask": "0x7", + "attr_cmpval": "0x80", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x72", + "attr_mask": "0x7", + "attr_cmpval": "0x80", + "attr_len": "1" + } + ] + } + }, + "PORT25": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT25", + "device_parent": "MUX7" + }, + "dev_attr": { + "dev_idx": "25" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT25-EEPROM" + }, + { + "itf": "control", + "dev": "PORT25-CTRL" + } + ] + } + }, + "PORT25-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT25-EEPROM", + "device_parent": "MUX7", + "virt_parent": "PORT25" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x32", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT25-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT25-CTRL", + "device_parent": "MUX7", + "virt_parent": "PORT25" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x32", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x13", + "attr_mask": "0x0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x43", + "attr_mask": "0x0", + "attr_cmpval": "0x1", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x49", + "attr_mask": "0x0", + "attr_cmpval": "0x1", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x73", + "attr_mask": "0x0", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT26": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT26", + "device_parent": "MUX7" + }, + "dev_attr": { + "dev_idx": "26" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT26-EEPROM" + }, + { + "itf": "control", + "dev": "PORT26-CTRL" + } + ] + } + }, + "PORT26-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT26-EEPROM", + "device_parent": "MUX7", + "virt_parent": "PORT26" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x33", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT26-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT26-CTRL", + "device_parent": "MUX7", + "virt_parent": "PORT26" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x33", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x13", + "attr_mask": "0x1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x43", + "attr_mask": "0x1", + "attr_cmpval": "0x2", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x49", + "attr_mask": "0x1", + "attr_cmpval": "0x2", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x73", + "attr_mask": "0x1", + "attr_cmpval": "0x2", + "attr_len": "1" + } + ] + } + }, + "PORT27": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT27", + "device_parent": "MUX7" + }, + "dev_attr": { + "dev_idx": "27" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT27-EEPROM" + }, + { + "itf": "control", + "dev": "PORT27-CTRL" + } + ] + } + }, + "PORT27-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT27-EEPROM", + "device_parent": "MUX7", + "virt_parent": "PORT27" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x34", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT27-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT27-CTRL", + "device_parent": "MUX7", + "virt_parent": "PORT27" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x34", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x13", + "attr_mask": "0x2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x43", + "attr_mask": "0x2", + "attr_cmpval": "0x4", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x49", + "attr_mask": "0x2", + "attr_cmpval": "0x4", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x73", + "attr_mask": "0x2", + "attr_cmpval": "0x4", + "attr_len": "1" + } + ] + } + }, + "PORT28": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT28", + "device_parent": "MUX7" + }, + "dev_attr": { + "dev_idx": "28" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT28-EEPROM" + }, + { + "itf": "control", + "dev": "PORT28-CTRL" + } + ] + } + }, + "PORT28-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT28-EEPROM", + "device_parent": "MUX7", + "virt_parent": "PORT28" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x35", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT28-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT28-CTRL", + "device_parent": "MUX7", + "virt_parent": "PORT28" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x35", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x13", + "attr_mask": "0x3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x43", + "attr_mask": "0x3", + "attr_cmpval": "0x8", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x49", + "attr_mask": "0x3", + "attr_cmpval": "0x8", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x73", + "attr_mask": "0x3", + "attr_cmpval": "0x8", + "attr_len": "1" + } + ] + } + }, + "PORT29": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT29", + "device_parent": "MUX7" + }, + "dev_attr": { + "dev_idx": "29" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT29-EEPROM" + }, + { + "itf": "control", + "dev": "PORT29-CTRL" + } + ] + } + }, + "PORT29-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT29-EEPROM", + "device_parent": "MUX7", + "virt_parent": "PORT29" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x36", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT29-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT29-CTRL", + "device_parent": "MUX7", + "virt_parent": "PORT29" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x36", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x13", + "attr_mask": "0x4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x43", + "attr_mask": "0x4", + "attr_cmpval": "0x10", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x49", + "attr_mask": "0x4", + "attr_cmpval": "0x10", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x73", + "attr_mask": "0x4", + "attr_cmpval": "0x10", + "attr_len": "1" + } + ] + } + }, + "PORT30": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT30", + "device_parent": "MUX7" + }, + "dev_attr": { + "dev_idx": "30" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT30-EEPROM" + }, + { + "itf": "control", + "dev": "PORT30-CTRL" + } + ] + } + }, + "PORT30-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT30-EEPROM", + "device_parent": "MUX7", + "virt_parent": "PORT30" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x37", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT30-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT30-CTRL", + "device_parent": "MUX7", + "virt_parent": "PORT30" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x37", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x13", + "attr_mask": "0x5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x43", + "attr_mask": "0x5", + "attr_cmpval": "0x20", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x49", + "attr_mask": "0x5", + "attr_cmpval": "0x20", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x73", + "attr_mask": "0x5", + "attr_cmpval": "0x20", + "attr_len": "1" + } + ] + } + }, + "PORT31": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT31", + "device_parent": "MUX7" + }, + "dev_attr": { + "dev_idx": "31" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT31-EEPROM" + }, + { + "itf": "control", + "dev": "PORT31-CTRL" + } + ] + } + }, + "PORT31-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT31-EEPROM", + "device_parent": "MUX7", + "virt_parent": "PORT31" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x38", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT31-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT31-CTRL", + "device_parent": "MUX7", + "virt_parent": "PORT31" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x38", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x13", + "attr_mask": "0x6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x43", + "attr_mask": "0x6", + "attr_cmpval": "0x40", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x49", + "attr_mask": "0x6", + "attr_cmpval": "0x40", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x73", + "attr_mask": "0x6", + "attr_cmpval": "0x40", + "attr_len": "1" + } + ] + } + }, + "PORT32": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT32", + "device_parent": "MUX7" + }, + "dev_attr": { + "dev_idx": "32" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT32-EEPROM" + }, + { + "itf": "control", + "dev": "PORT32-CTRL" + } + ] + } + }, + "PORT32-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT32-EEPROM", + "device_parent": "MUX7", + "virt_parent": "PORT32" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x39", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT32-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT32-CTRL", + "device_parent": "MUX7", + "virt_parent": "PORT32" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x39", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x13", + "attr_mask": "0x7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x43", + "attr_mask": "0x7", + "attr_cmpval": "0x80", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x49", + "attr_mask": "0x7", + "attr_cmpval": "0x80", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x73", + "attr_mask": "0x7", + "attr_cmpval": "0x80", + "attr_len": "1" + } + ] + } + }, + "PORT33": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT33", + "device_parent": "MUX8" + }, + "dev_attr": { + "dev_idx": "33" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT33-EEPROM" + }, + { + "itf": "control", + "dev": "PORT33-CTRL" + } + ] + } + }, + "PORT33-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT33-EEPROM", + "device_parent": "MUX8", + "virt_parent": "PORT33" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x3a", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT33-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT33-CTRL", + "device_parent": "MUX8", + "virt_parent": "PORT33" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x3a", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x14", + "attr_mask": "0x0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x44", + "attr_mask": "0x0", + "attr_cmpval": "0x1", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x4a", + "attr_mask": "0x0", + "attr_cmpval": "0x1", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x74", + "attr_mask": "0x0", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT34": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT34", + "device_parent": "MUX8" + }, + "dev_attr": { + "dev_idx": "34" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT34-EEPROM" + }, + { + "itf": "control", + "dev": "PORT34-CTRL" + } + ] + } + }, + "PORT34-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT34-EEPROM", + "device_parent": "MUX8", + "virt_parent": "PORT34" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x3b", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT34-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT34-CTRL", + "device_parent": "MUX8", + "virt_parent": "PORT34" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x3b", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x14", + "attr_mask": "0x1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x44", + "attr_mask": "0x1", + "attr_cmpval": "0x2", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x4a", + "attr_mask": "0x1", + "attr_cmpval": "0x2", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x74", + "attr_mask": "0x1", + "attr_cmpval": "0x2", + "attr_len": "1" + } + ] + } + }, + "PORT35": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT35", + "device_parent": "MUX8" + }, + "dev_attr": { + "dev_idx": "35" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT35-EEPROM" + }, + { + "itf": "control", + "dev": "PORT35-CTRL" + } + ] + } + }, + "PORT35-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT35-EEPROM", + "device_parent": "MUX8", + "virt_parent": "PORT35" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x3c", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT35-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT35-CTRL", + "device_parent": "MUX8", + "virt_parent": "PORT35" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x3c", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x14", + "attr_mask": "0x2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x44", + "attr_mask": "0x2", + "attr_cmpval": "0x4", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x4a", + "attr_mask": "0x2", + "attr_cmpval": "0x4", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x74", + "attr_mask": "0x2", + "attr_cmpval": "0x4", + "attr_len": "1" + } + ] + } + }, + "PORT36": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT36", + "device_parent": "MUX8" + }, + "dev_attr": { + "dev_idx": "36" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT36-EEPROM" + }, + { + "itf": "control", + "dev": "PORT36-CTRL" + } + ] + } + }, + "PORT36-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT36-EEPROM", + "device_parent": "MUX8", + "virt_parent": "PORT36" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x3d", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT36-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT36-CTRL", + "device_parent": "MUX8", + "virt_parent": "PORT36" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x3d", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x14", + "attr_mask": "0x3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x44", + "attr_mask": "0x3", + "attr_cmpval": "0x8", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x4a", + "attr_mask": "0x3", + "attr_cmpval": "0x8", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x74", + "attr_mask": "0x3", + "attr_cmpval": "0x8", + "attr_len": "1" + } + ] + } + }, + "PORT37": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT37", + "device_parent": "MUX8" + }, + "dev_attr": { + "dev_idx": "37" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT37-EEPROM" + }, + { + "itf": "control", + "dev": "PORT37-CTRL" + } + ] + } + }, + "PORT37-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT37-EEPROM", + "device_parent": "MUX8", + "virt_parent": "PORT37" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x3e", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT37-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT37-CTRL", + "device_parent": "MUX8", + "virt_parent": "PORT37" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x3e", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x14", + "attr_mask": "0x4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x44", + "attr_mask": "0x4", + "attr_cmpval": "0x10", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x4a", + "attr_mask": "0x4", + "attr_cmpval": "0x10", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x74", + "attr_mask": "0x4", + "attr_cmpval": "0x10", + "attr_len": "1" + } + ] + } + }, + "PORT38": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT38", + "device_parent": "MUX8" + }, + "dev_attr": { + "dev_idx": "38" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT38-EEPROM" + }, + { + "itf": "control", + "dev": "PORT38-CTRL" + } + ] + } + }, + "PORT38-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT38-EEPROM", + "device_parent": "MUX8", + "virt_parent": "PORT38" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x3f", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT38-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT38-CTRL", + "device_parent": "MUX8", + "virt_parent": "PORT38" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x3f", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x14", + "attr_mask": "0x5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x44", + "attr_mask": "0x5", + "attr_cmpval": "0x20", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x4a", + "attr_mask": "0x5", + "attr_cmpval": "0x20", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x74", + "attr_mask": "0x5", + "attr_cmpval": "0x20", + "attr_len": "1" + } + ] + } + }, + "PORT39": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT39", + "device_parent": "MUX8" + }, + "dev_attr": { + "dev_idx": "39" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT39-EEPROM" + }, + { + "itf": "control", + "dev": "PORT39-CTRL" + } + ] + } + }, + "PORT39-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT39-EEPROM", + "device_parent": "MUX8", + "virt_parent": "PORT39" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x40", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT39-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT39-CTRL", + "device_parent": "MUX8", + "virt_parent": "PORT39" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x40", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x14", + "attr_mask": "0x6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x44", + "attr_mask": "0x6", + "attr_cmpval": "0x40", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x4a", + "attr_mask": "0x6", + "attr_cmpval": "0x40", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x74", + "attr_mask": "0x6", + "attr_cmpval": "0x40", + "attr_len": "1" + } + ] + } + }, + "PORT40": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT40", + "device_parent": "MUX8" + }, + "dev_attr": { + "dev_idx": "40" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT40-EEPROM" + }, + { + "itf": "control", + "dev": "PORT40-CTRL" + } + ] + } + }, + "PORT40-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT40-EEPROM", + "device_parent": "MUX8", + "virt_parent": "PORT40" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x41", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT40-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT40-CTRL", + "device_parent": "MUX8", + "virt_parent": "PORT40" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x41", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x14", + "attr_mask": "0x7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x44", + "attr_mask": "0x7", + "attr_cmpval": "0x80", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x4a", + "attr_mask": "0x7", + "attr_cmpval": "0x80", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x74", + "attr_mask": "0x7", + "attr_cmpval": "0x80", + "attr_len": "1" + } + ] + } + }, + "PORT41": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT41", + "device_parent": "MUX9" + }, + "dev_attr": { + "dev_idx": "41" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT41-EEPROM" + }, + { + "itf": "control", + "dev": "PORT41-CTRL" + } + ] + } + }, + "PORT41-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT41-EEPROM", + "device_parent": "MUX9", + "virt_parent": "PORT41" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x42", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT41-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT41-CTRL", + "device_parent": "MUX9", + "virt_parent": "PORT41" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x42", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x15", + "attr_mask": "0x0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x45", + "attr_mask": "0x0", + "attr_cmpval": "0x1", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x4b", + "attr_mask": "0x0", + "attr_cmpval": "0x1", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x75", + "attr_mask": "0x0", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT42": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT42", + "device_parent": "MUX9" + }, + "dev_attr": { + "dev_idx": "42" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT42-EEPROM" + }, + { + "itf": "control", + "dev": "PORT42-CTRL" + } + ] + } + }, + "PORT42-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT42-EEPROM", + "device_parent": "MUX9", + "virt_parent": "PORT42" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x43", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT42-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT42-CTRL", + "device_parent": "MUX9", + "virt_parent": "PORT42" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x43", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x15", + "attr_mask": "0x1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x45", + "attr_mask": "0x1", + "attr_cmpval": "0x2", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x4b", + "attr_mask": "0x1", + "attr_cmpval": "0x2", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x75", + "attr_mask": "0x1", + "attr_cmpval": "0x2", + "attr_len": "1" + } + ] + } + }, + "PORT43": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT43", + "device_parent": "MUX9" + }, + "dev_attr": { + "dev_idx": "43" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT43-EEPROM" + }, + { + "itf": "control", + "dev": "PORT43-CTRL" + } + ] + } + }, + "PORT43-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT43-EEPROM", + "device_parent": "MUX9", + "virt_parent": "PORT43" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x44", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT43-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT43-CTRL", + "device_parent": "MUX9", + "virt_parent": "PORT43" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x44", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x15", + "attr_mask": "0x2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x45", + "attr_mask": "0x2", + "attr_cmpval": "0x4", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x4b", + "attr_mask": "0x2", + "attr_cmpval": "0x4", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x75", + "attr_mask": "0x2", + "attr_cmpval": "0x4", + "attr_len": "1" + } + ] + } + }, + "PORT44": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT44", + "device_parent": "MUX9" + }, + "dev_attr": { + "dev_idx": "44" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT44-EEPROM" + }, + { + "itf": "control", + "dev": "PORT44-CTRL" + } + ] + } + }, + "PORT44-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT44-EEPROM", + "device_parent": "MUX9", + "virt_parent": "PORT44" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x45", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT44-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT44-CTRL", + "device_parent": "MUX9", + "virt_parent": "PORT44" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x45", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x15", + "attr_mask": "0x3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x45", + "attr_mask": "0x3", + "attr_cmpval": "0x8", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x4b", + "attr_mask": "0x3", + "attr_cmpval": "0x8", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x75", + "attr_mask": "0x3", + "attr_cmpval": "0x8", + "attr_len": "1" + } + ] + } + }, + "PORT45": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT45", + "device_parent": "MUX9" + }, + "dev_attr": { + "dev_idx": "45" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT45-EEPROM" + }, + { + "itf": "control", + "dev": "PORT45-CTRL" + } + ] + } + }, + "PORT45-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT45-EEPROM", + "device_parent": "MUX9", + "virt_parent": "PORT45" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x46", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT45-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT45-CTRL", + "device_parent": "MUX9", + "virt_parent": "PORT45" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x46", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x15", + "attr_mask": "0x4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x45", + "attr_mask": "0x4", + "attr_cmpval": "0x10", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x4b", + "attr_mask": "0x4", + "attr_cmpval": "0x10", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x75", + "attr_mask": "0x4", + "attr_cmpval": "0x10", + "attr_len": "1" + } + ] + } + }, + "PORT46": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT46", + "device_parent": "MUX9" + }, + "dev_attr": { + "dev_idx": "46" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT46-EEPROM" + }, + { + "itf": "control", + "dev": "PORT46-CTRL" + } + ] + } + }, + "PORT46-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT46-EEPROM", + "device_parent": "MUX9", + "virt_parent": "PORT46" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x47", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT46-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT46-CTRL", + "device_parent": "MUX9", + "virt_parent": "PORT46" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x47", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x15", + "attr_mask": "0x5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x45", + "attr_mask": "0x5", + "attr_cmpval": "0x20", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x4b", + "attr_mask": "0x5", + "attr_cmpval": "0x20", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x75", + "attr_mask": "0x5", + "attr_cmpval": "0x20", + "attr_len": "1" + } + ] + } + }, + "PORT47": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT47", + "device_parent": "MUX9" + }, + "dev_attr": { + "dev_idx": "47" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT47-EEPROM" + }, + { + "itf": "control", + "dev": "PORT47-CTRL" + } + ] + } + }, + "PORT47-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT47-EEPROM", + "device_parent": "MUX9", + "virt_parent": "PORT47" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x48", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT47-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT47-CTRL", + "device_parent": "MUX9", + "virt_parent": "PORT47" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x48", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x15", + "attr_mask": "0x6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x45", + "attr_mask": "0x6", + "attr_cmpval": "0x40", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x4b", + "attr_mask": "0x6", + "attr_cmpval": "0x40", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x75", + "attr_mask": "0x6", + "attr_cmpval": "0x40", + "attr_len": "1" + } + ] + } + }, + "PORT48": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT48", + "device_parent": "MUX9" + }, + "dev_attr": { + "dev_idx": "48" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT48-EEPROM" + }, + { + "itf": "control", + "dev": "PORT48-CTRL" + } + ] + } + }, + "PORT48-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT48-EEPROM", + "device_parent": "MUX9", + "virt_parent": "PORT48" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x49", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT48-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT48-CTRL", + "device_parent": "MUX9", + "virt_parent": "PORT48" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x49", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x15", + "attr_mask": "0x7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x45", + "attr_mask": "0x7", + "attr_cmpval": "0x80", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x4b", + "attr_mask": "0x7", + "attr_cmpval": "0x80", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x75", + "attr_mask": "0x7", + "attr_cmpval": "0x80", + "attr_len": "1" + } + ] + } + }, + "PORT49": { + "dev_info": { + "device_type": "QSFP28", + "device_name": "PORT49", + "device_parent": "MUX10" + }, + "dev_attr": { + "dev_idx": "49" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT49-EEPROM" + }, + { + "itf": "control", + "dev": "PORT49-CTRL" + } + ] + } + }, + "PORT49-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT49-EEPROM", + "device_parent": "MUX10", + "virt_parent": "PORT49" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x4a", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT49-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT49-CTRL", + "device_parent": "MUX10", + "virt_parent": "PORT49" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x4a", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x16", + "attr_mask": "0x0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x17", + "attr_mask": "0x0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x76", + "attr_mask": "0x0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x77", + "attr_mask": "0x0", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT50": { + "dev_info": { + "device_type": "QSFP28", + "device_name": "PORT50", + "device_parent": "MUX10" + }, + "dev_attr": { + "dev_idx": "50" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT50-EEPROM" + }, + { + "itf": "control", + "dev": "PORT50-CTRL" + } + ] + } + }, + "PORT50-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT50-EEPROM", + "device_parent": "MUX10", + "virt_parent": "PORT50" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x4b", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT50-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT50-CTRL", + "device_parent": "MUX10", + "virt_parent": "PORT50" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x4b", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x16", + "attr_mask": "0x1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x17", + "attr_mask": "0x1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x76", + "attr_mask": "0x1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x77", + "attr_mask": "0x1", + "attr_cmpval": "0x2", + "attr_len": "1" + } + ] + } + }, + "PORT51": { + "dev_info": { + "device_type": "QSFP28", + "device_name": "PORT51", + "device_parent": "MUX10" + }, + "dev_attr": { + "dev_idx": "51" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT51-EEPROM" + }, + { + "itf": "control", + "dev": "PORT51-CTRL" + } + ] + } + }, + "PORT51-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT51-EEPROM", + "device_parent": "MUX10", + "virt_parent": "PORT51" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x4c", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT51-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT51-CTRL", + "device_parent": "MUX10", + "virt_parent": "PORT51" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x4c", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x16", + "attr_mask": "0x2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x17", + "attr_mask": "0x2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x76", + "attr_mask": "0x2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x77", + "attr_mask": "0x2", + "attr_cmpval": "0x4", + "attr_len": "1" + } + ] + } + }, + "PORT52": { + "dev_info": { + "device_type": "QSFP28", + "device_name": "PORT52", + "device_parent": "MUX10" + }, + "dev_attr": { + "dev_idx": "52" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT52-EEPROM" + }, + { + "itf": "control", + "dev": "PORT52-CTRL" + } + ] + } + }, + "PORT52-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT52-EEPROM", + "device_parent": "MUX10", + "virt_parent": "PORT52" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x4d", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT52-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT52-CTRL", + "device_parent": "MUX10", + "virt_parent": "PORT52" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x4d", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x16", + "attr_mask": "0x3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x17", + "attr_mask": "0x3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x76", + "attr_mask": "0x3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x77", + "attr_mask": "0x3", + "attr_cmpval": "0x8", + "attr_len": "1" + } + ] + } + }, + "PORT53": { + "dev_info": { + "device_type": "QSFP28", + "device_name": "PORT53", + "device_parent": "MUX10" + }, + "dev_attr": { + "dev_idx": "53" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT53-EEPROM" + }, + { + "itf": "control", + "dev": "PORT53-CTRL" + } + ] + } + }, + "PORT53-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT53-EEPROM", + "device_parent": "MUX10", + "virt_parent": "PORT53" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x4e", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT53-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT53-CTRL", + "device_parent": "MUX10", + "virt_parent": "PORT53" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x4e", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x16", + "attr_mask": "0x4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x17", + "attr_mask": "0x4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x76", + "attr_mask": "0x4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x77", + "attr_mask": "0x4", + "attr_cmpval": "0x10", + "attr_len": "1" + } + ] + } + }, + "PORT54": { + "dev_info": { + "device_type": "QSFP28", + "device_name": "PORT54", + "device_parent": "MUX10" + }, + "dev_attr": { + "dev_idx": "54" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT54-EEPROM" + }, + { + "itf": "control", + "dev": "PORT54-CTRL" + } + ] + } + }, + "PORT54-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT54-EEPROM", + "device_parent": "MUX10", + "virt_parent": "PORT54" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x4f", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT54-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT54-CTRL", + "device_parent": "MUX10", + "virt_parent": "PORT54" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x4f", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x16", + "attr_mask": "0x5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x17", + "attr_mask": "0x5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x76", + "attr_mask": "0x5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x77", + "attr_mask": "0x5", + "attr_cmpval": "0x20", + "attr_len": "1" + } + ] + } + } +} diff --git a/device/ufispace/x86_64-ufispace_s7801_54xs-r0/pddf_support b/device/ufispace/x86_64-ufispace_s7801_54xs-r0/pddf_support new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/device/ufispace/x86_64-ufispace_s7801_54xs-r0/platform.json b/device/ufispace/x86_64-ufispace_s7801_54xs-r0/platform.json new file mode 100644 index 000000000000..7800ce50ddc2 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s7801_54xs-r0/platform.json @@ -0,0 +1,691 @@ +{ + "chassis": { + "name": "S7801-54XS", + "components": [ + { + "name": "CPLD1" + }, + { + "name": "CPLD2" + }, + { + "name": "BIOS" + }, + { + "name": "BMC" + } + ], + "fans": [ + { + "name": "Fan_1" + }, + { + "name": "Fan_2" + }, + { + "name": "Fan_3" + }, + { + "name": "Fan_4" + }, + { + "name": "Fan_5" + } + ], + "fan_drawers":[ + { + "name": "Fantray1", + "num_fans" : 1, + "fans": [ + { + "name": "Fan_1" + } + ] + }, + { + "name": "Fantray2", + "num_fans" : 1, + "fans": [ + { + "name": "Fan_2" + } + ] + }, + { + "name": "Fantray3", + "num_fans" : 1, + "fans": [ + { + "name": "Fan_3" + } + ] + }, + { + "name": "Fantray4", + "num_fans" : 1, + "fans": [ + { + "name": "Fan_4" + } + ] + }, + { + "name": "Fantray5", + "num_fans" : 1, + "fans": [ + { + "name": "Fan_5" + } + ] + } + ], + "psus": [ + { + "name": "PSU1", + "fans": [ + { + "name": "PSU1_FAN1" + } + ], + "thermals": [ + { + "name": "PSU1_TEMP1" + } + ] + }, + { + "name": "PSU2", + "fans": [ + { + "name": "PSU2_FAN1" + } + ], + "thermals": [ + { + "name": "PSU2_TEMP1" + } + ] + } + ], + "thermals": [ + { + "name": "TEMP_MAC" + }, + { + "name": "TEMP_ENV_MACCASE" + }, + { + "name": "TEMP_ENV_PSUCASE" + }, + { + "name": "TEMP_ENV_FANCONN" + }, + { + "name": "TEMP_ENV_FANCARD" + }, + { + "name": "TEMP_ENV_BMC" + }, + { + "name": "PSU-0-Thermal" + }, + { + "name": "PSU-1-Thermal" + } + ], + "sfps": [ + { + "name": "Ethernet0" + }, + { + "name": "Ethernet1" + }, + { + "name": "Ethernet2" + }, + { + "name": "Ethernet3" + }, + { + "name": "Ethernet4" + }, + { + "name": "Ethernet5" + }, + { + "name": "Ethernet6" + }, + { + "name": "Ethernet7" + }, + { + "name": "Ethernet8" + }, + { + "name": "Ethernet9" + }, + { + "name": "Ethernet10" + }, + { + "name": "Ethernet11" + }, + { + "name": "Ethernet12" + }, + { + "name": "Ethernet13" + }, + { + "name": "Ethernet14" + }, + { + "name": "Ethernet15" + }, + { + "name": "Ethernet16" + }, + { + "name": "Ethernet17" + }, + { + "name": "Ethernet18" + }, + { + "name": "Ethernet19" + }, + { + "name": "Ethernet20" + }, + { + "name": "Ethernet21" + }, + { + "name": "Ethernet22" + }, + { + "name": "Ethernet23" + }, + { + "name": "Ethernet24" + }, + { + "name": "Ethernet25" + }, + { + "name": "Ethernet26" + }, + { + "name": "Ethernet27" + }, + { + "name": "Ethernet28" + }, + { + "name": "Ethernet29" + }, + { + "name": "Ethernet30" + }, + { + "name": "Ethernet31" + }, + { + "name": "Ethernet32" + }, + { + "name": "Ethernet33" + }, + { + "name": "Ethernet34" + }, + { + "name": "Ethernet35" + }, + { + "name": "Ethernet36" + }, + { + "name": "Ethernet37" + }, + { + "name": "Ethernet38" + }, + { + "name": "Ethernet39" + }, + { + "name": "Ethernet40" + }, + { + "name": "Ethernet41" + }, + { + "name": "Ethernet42" + }, + { + "name": "Ethernet43" + }, + { + "name": "Ethernet44" + }, + { + "name": "Ethernet45" + }, + { + "name": "Ethernet46" + }, + { + "name": "Ethernet47" + }, + { + "name": "Ethernet48" + }, + { + "name": "Ethernet52" + }, + { + "name": "Ethernet56" + }, + { + "name": "Ethernet60" + }, + { + "name": "Ethernet64" + }, + { + "name": "Ethernet68" + }, + { + "name": "Ethernet72" + } + ] + }, + "interfaces": { + "Ethernet0": { + "index": "0", + "lanes": "1", + "breakout_modes": { + "1x10G" : [ "Eth0(Port0)" ] + } + }, + "Ethernet1": { + "index": "1", + "lanes": "2", + "breakout_modes": { + "1x10G" : [ "Eth1(Port1)" ] + } + }, + "Ethernet2": { + "index": "2", + "lanes": "3", + "breakout_modes": { + "1x10G" : [ "Eth2(Port2)" ] + } + }, + "Ethernet3": { + "index": "3", + "lanes": "4", + "breakout_modes": { + "1x10G" : [ "Eth3(Port3)" ] + } + }, + "Ethernet4": { + "index": "4", + "lanes": "5", + "breakout_modes": { + "1x10G" : [ "Eth4(Port4)" ] + } + }, + "Ethernet5": { + "index": "5", + "lanes": "6", + "breakout_modes": { + "1x10G" : [ "Eth5(Port5)" ] + } + }, + "Ethernet6": { + "index": "6", + "lanes": "7", + "breakout_modes": { + "1x10G" : [ "Eth6(Port6)" ] + } + }, + "Ethernet7": { + "index": "7", + "lanes": "8", + "breakout_modes": { + "1x10G" : [ "Eth7(Port7)" ] + } + }, + "Ethernet8": { + "index": "8", + "lanes": "9", + "breakout_modes": { + "1x10G" : [ "Eth8(Port8)" ] + } + }, + "Ethernet9": { + "index": "9", + "lanes": "10", + "breakout_modes": { + "1x10G" : [ "Eth9(Port9)" ] + } + }, + "Ethernet10": { + "index": "10", + "lanes": "11", + "breakout_modes": { + "1x10G" : [ "Eth10(Port10)" ] + } + }, + "Ethernet11": { + "index": "11", + "lanes": "12", + "breakout_modes": { + "1x10G" : [ "Eth11(Port11)" ] + } + }, + "Ethernet12": { + "index": "12", + "lanes": "13", + "breakout_modes": { + "1x10G" : [ "Eth12(Port12)" ] + } + }, + "Ethernet13": { + "index": "13", + "lanes": "14", + "breakout_modes": { + "1x10G" : [ "Eth13(Port13)" ] + } + }, + "Ethernet14": { + "index": "14", + "lanes": "15", + "breakout_modes": { + "1x10G" : [ "Eth14(Port14)" ] + } + }, + "Ethernet15": { + "index": "15", + "lanes": "16", + "breakout_modes": { + "1x10G" : [ "Eth15(Port15)" ] + } + }, + "Ethernet16": { + "index": "16", + "lanes": "17", + "breakout_modes": { + "1x10G" : [ "Eth16(Port16)" ] + } + }, + "Ethernet17": { + "index": "17", + "lanes": "18", + "breakout_modes": { + "1x10G" : [ "Eth17(Port17)" ] + } + }, + "Ethernet18": { + "index": "18", + "lanes": "19", + "breakout_modes": { + "1x10G" : [ "Eth18(Port18)" ] + } + }, + "Ethernet19": { + "index": "19", + "lanes": "20", + "breakout_modes": { + "1x10G" : [ "Eth19(Port19)" ] + } + }, + "Ethernet20": { + "index": "20", + "lanes": "21", + "breakout_modes": { + "1x10G" : [ "Eth20(Port20)" ] + } + }, + "Ethernet21": { + "index": "21", + "lanes": "22", + "breakout_modes": { + "1x10G" : [ "Eth21(Port21)" ] + } + }, + "Ethernet22": { + "index": "22", + "lanes": "23", + "breakout_modes": { + "1x10G" : [ "Eth22(Port22)" ] + } + }, + "Ethernet23": { + "index": "23", + "lanes": "24", + "breakout_modes": { + "1x10G" : [ "Eth23(Port23)" ] + } + }, + "Ethernet24": { + "index": "24", + "lanes": "25", + "breakout_modes": { + "1x10G" : [ "Eth24(Port24)" ] + } + }, + "Ethernet25": { + "index": "25", + "lanes": "26", + "breakout_modes": { + "1x10G" : [ "Eth25(Port25)" ] + } + }, + "Ethernet26": { + "index": "26", + "lanes": "27", + "breakout_modes": { + "1x10G" : [ "Eth26(Port26)" ] + } + }, + "Ethernet27": { + "index": "27", + "lanes": "28", + "breakout_modes": { + "1x10G" : [ "Eth27(Port27)" ] + } + }, + "Ethernet28": { + "index": "28", + "lanes": "41", + "breakout_modes": { + "1x10G" : [ "Eth28(Port28)" ] + } + }, + "Ethernet29": { + "index": "29", + "lanes": "42", + "breakout_modes": { + "1x10G" : [ "Eth29(Port29)" ] + } + }, + "Ethernet30": { + "index": "30", + "lanes": "43", + "breakout_modes": { + "1x10G" : [ "Eth30(Port30)" ] + } + }, + "Ethernet31": { + "index": "31", + "lanes": "44", + "breakout_modes": { + "1x10G" : [ "Eth31(Port31)" ] + } + }, + "Ethernet32": { + "index": "32", + "lanes": "61", + "breakout_modes": { + "1x10G" : [ "Eth32(Port32)" ] + } + }, + "Ethernet33": { + "index": "33", + "lanes": "62", + "breakout_modes": { + "1x10G" : [ "Eth33(Port33)" ] + } + }, + "Ethernet34": { + "index": "34", + "lanes": "63", + "breakout_modes": { + "1x10G" : [ "Eth34(Port34)" ] + } + }, + "Ethernet35": { + "index": "35", + "lanes": "64", + "breakout_modes": { + "1x10G" : [ "Eth35(Port35)" ] + } + }, + "Ethernet36": { + "index": "36", + "lanes": "65", + "breakout_modes": { + "1x10G" : [ "Eth36(Port36)" ] + } + }, + "Ethernet37": { + "index": "37", + "lanes": "66", + "breakout_modes": { + "1x10G" : [ "Eth37(Port37)" ] + } + }, + "Ethernet38": { + "index": "38", + "lanes": "67", + "breakout_modes": { + "1x10G" : [ "Eth38(Port38)" ] + } + }, + "Ethernet39": { + "index": "39", + "lanes": "68", + "breakout_modes": { + "1x10G" : [ "Eth39(Port39)" ] + } + }, + "Ethernet40": { + "index": "40", + "lanes": "69", + "breakout_modes": { + "1x10G" : [ "Eth40(Port40)" ] + } + }, + "Ethernet41": { + "index": "41", + "lanes": "70", + "breakout_modes": { + "1x10G" : [ "Eth41(Port41)" ] + } + }, + "Ethernet42": { + "index": "42", + "lanes": "71", + "breakout_modes": { + "1x10G" : [ "Eth42(Port42)" ] + } + }, + "Ethernet43": { + "index": "43", + "lanes": "72", + "breakout_modes": { + "1x10G" : [ "Eth43(Port43)" ] + } + }, + "Ethernet44": { + "index": "44", + "lanes": "73", + "breakout_modes": { + "1x10G" : [ "Eth44(Port44)" ] + } + }, + "Ethernet45": { + "index": "45", + "lanes": "74", + "breakout_modes": { + "1x10G" : [ "Eth45(Port45)" ] + } + }, + "Ethernet46": { + "index": "46", + "lanes": "75", + "breakout_modes": { + "1x10G" : [ "Eth46(Port46)" ] + } + }, + "Ethernet47": { + "index": "47", + "lanes": "76", + "breakout_modes": { + "1x10G" : [ "Eth47(Port47)" ] + } + }, + "Ethernet48": { + "index": "48,48,48,48", + "lanes": "37,38,39,40", + "breakout_modes": { + "1x100G[40G]" : [ "Eth48(Port48)" ] + } + }, + "Ethernet52": { + "index": "49,49,49,49", + "lanes": "33,34,35,36", + "breakout_modes": { + "1x100G[40G]" : [ "Eth49(Port49)" ] + } + }, + "Ethernet56": { + "index": "50,50,50,50", + "lanes": "45,46,47,48", + "breakout_modes": { + "1x100G[40G]" : [ "Eth50(Port50)" ] + } + }, + "Ethernet60": { + "index": "51,51,51,51", + "lanes": "49,50,51,52", + "breakout_modes": { + "1x100G[40G]" : [ "Eth51(Port51)" ] + } + }, + "Ethernet64": { + "index": "52,52,52,52", + "lanes": "53,54,55,56", + "breakout_modes": { + "1x100G[40G]": ["Eth52(Port52)"], + "2x50G": ["Eth52/1(Port52)", "Eth52/2(Port52)"], + "4x25G": ["Eth52/1(Port52)", "Eth52/2(Port52)", "Eth52/3(Port52)", "Eth52/4(Port52)"], + "4x10G": ["Eth52/1(Port52)", "Eth52/2(Port52)", "Eth52/3(Port52)", "Eth52/4(Port52)"] + } + }, + "Ethernet68": { + "index": "53,53,53,53", + "lanes": "57,58,59,60", + "breakout_modes": { + "1x100G[40G]": ["Eth53(Port53)"], + "2x50G": ["Eth53/1(Port53)", "Eth53/2(Port53)"], + "4x25G": ["Eth53/1(Port53)", "Eth53/2(Port53)", "Eth53/3(Port53)", "Eth53/4(Port53)"], + "4x10G": ["Eth53/1(Port53)", "Eth53/2(Port53)", "Eth53/3(Port53)", "Eth53/4(Port53)"] + } + } + } +} + diff --git a/device/ufispace/x86_64-ufispace_s7801_54xs-r0/platform_asic b/device/ufispace/x86_64-ufispace_s7801_54xs-r0/platform_asic new file mode 100644 index 000000000000..960467652765 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s7801_54xs-r0/platform_asic @@ -0,0 +1 @@ +broadcom diff --git a/device/ufispace/x86_64-ufispace_s7801_54xs-r0/platform_components.json b/device/ufispace/x86_64-ufispace_s7801_54xs-r0/platform_components.json new file mode 100644 index 000000000000..5ab2d23557f3 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s7801_54xs-r0/platform_components.json @@ -0,0 +1,12 @@ +{ + "chassis": { + "x86_64-ufispace_s7801_54xs-r0": { + "component": { + "CPLD1": { }, + "CPLD2": { }, + "BIOS": { }, + "BMC": {} + } + } + } +} diff --git a/device/ufispace/x86_64-ufispace_s7801_54xs-r0/platform_env.conf b/device/ufispace/x86_64-ufispace_s7801_54xs-r0/platform_env.conf new file mode 100644 index 000000000000..77fd88ac3678 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s7801_54xs-r0/platform_env.conf @@ -0,0 +1 @@ +SYNCD_SHM_SIZE=256m diff --git a/device/ufispace/x86_64-ufispace_s7801_54xs-r0/pmon_daemon_control.json b/device/ufispace/x86_64-ufispace_s7801_54xs-r0/pmon_daemon_control.json new file mode 100644 index 000000000000..e348e0168fa5 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s7801_54xs-r0/pmon_daemon_control.json @@ -0,0 +1,9 @@ +{ + "skip_pcied": false, + "skip_fancontrol": false, + "skip_thermalctld": false, + "skip_ledd": true, + "skip_xcvrd": false, + "skip_psud": false, + "skip_syseepromd": false +} diff --git a/device/ufispace/x86_64-ufispace_s7801_54xs-r0/sensors.conf b/device/ufispace/x86_64-ufispace_s7801_54xs-r0/sensors.conf new file mode 100644 index 000000000000..b1a69433405b --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s7801_54xs-r0/sensors.conf @@ -0,0 +1 @@ +# libsensors configuration file diff --git a/device/ufispace/x86_64-ufispace_s7801_54xs-r0/system_health_monitoring_config.json b/device/ufispace/x86_64-ufispace_s7801_54xs-r0/system_health_monitoring_config.json new file mode 100644 index 000000000000..467d81304de0 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s7801_54xs-r0/system_health_monitoring_config.json @@ -0,0 +1,15 @@ +{ + "services_to_ignore": [], + "devices_to_ignore": [ + "asic", + "psu", + "fan" + ], + "user_defined_checkers": [], + "polling_interval": 60, + "led_color": { + "fault": "yellow", + "normal": "green", + "booting": "green_blink" + } +} diff --git a/device/ufispace/x86_64-ufispace_s8901_54xc-r0/UFISPACE-S8901-54XC/hwsku.json b/device/ufispace/x86_64-ufispace_s8901_54xc-r0/UFISPACE-S8901-54XC/hwsku.json new file mode 100644 index 000000000000..041ad2b5df26 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s8901_54xc-r0/UFISPACE-S8901-54XC/hwsku.json @@ -0,0 +1,166 @@ +{ + "interfaces": { + "Ethernet0": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet1": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet2": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet3": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet4": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet5": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet6": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet7": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet8": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet9": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet10": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet11": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet12": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet13": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet14": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet15": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet16": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet17": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet18": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet19": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet20": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet21": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet22": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet23": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet24": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet25": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet26": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet27": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet28": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet29": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet30": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet31": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet32": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet33": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet34": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet35": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet36": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet37": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet38": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet39": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet40": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet41": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet42": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet43": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet44": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet45": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet46": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet47": { + "default_brkout_mode": "1x25G[10G]" + }, + "Ethernet48": { + "default_brkout_mode": "1x100G[40G]" + }, + "Ethernet52": { + "default_brkout_mode": "1x100G[40G]" + }, + "Ethernet56": { + "default_brkout_mode": "1x100G[40G]" + }, + "Ethernet60": { + "default_brkout_mode": "1x100G[40G]" + }, + "Ethernet64": { + "default_brkout_mode": "1x100G[40G]" + }, + "Ethernet68": { + "default_brkout_mode": "1x100G[40G]" + } + } +} diff --git a/device/ufispace/x86_64-ufispace_s8901_54xc-r0/UFISPACE-S8901-54XC/sai.profile b/device/ufispace/x86_64-ufispace_s8901_54xc-r0/UFISPACE-S8901-54XC/sai.profile new file mode 100644 index 000000000000..39a5f795f1a3 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s8901_54xc-r0/UFISPACE-S8901-54XC/sai.profile @@ -0,0 +1 @@ +SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/td3-x5-s8901-54xc.config.bcm \ No newline at end of file diff --git a/device/ufispace/x86_64-ufispace_s8901_54xc-r0/UFISPACE-S8901-54XC/td3-x5-s8901-54xc.config.bcm b/device/ufispace/x86_64-ufispace_s8901_54xc-r0/UFISPACE-S8901-54XC/td3-x5-s8901-54xc.config.bcm new file mode 100644 index 000000000000..37d9d8ec80d9 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s8901_54xc-r0/UFISPACE-S8901-54XC/td3-x5-s8901-54xc.config.bcm @@ -0,0 +1,502 @@ +# cfg version: r2, 20230515 + +pbmp_xport_xe=0x7fffffffffffffffdfffffffffffffffe + + +#FC 0 +phy_chain_tx_polarity_flip_physical{1}=0x0 +phy_chain_tx_polarity_flip_physical{2}=0x0 +phy_chain_tx_polarity_flip_physical{3}=0x0 +phy_chain_tx_polarity_flip_physical{4}=0x0 + +phy_chain_rx_polarity_flip_physical{1}=0x0 +phy_chain_rx_polarity_flip_physical{2}=0x0 +phy_chain_rx_polarity_flip_physical{3}=0x0 +phy_chain_rx_polarity_flip_physical{4}=0x0 + +phy_chain_tx_lane_map_physical{1.0}=0x0123 +phy_chain_rx_lane_map_physical{1.0}=0x0123 + +#FC 1 +phy_chain_tx_polarity_flip_physical{5}=0x0 +phy_chain_tx_polarity_flip_physical{6}=0x0 +phy_chain_tx_polarity_flip_physical{7}=0x0 +phy_chain_tx_polarity_flip_physical{8}=0x0 + +phy_chain_rx_polarity_flip_physical{5}=0x1 +phy_chain_rx_polarity_flip_physical{6}=0x1 +phy_chain_rx_polarity_flip_physical{7}=0x1 +phy_chain_rx_polarity_flip_physical{8}=0x1 + +phy_chain_tx_lane_map_physical{5.0}=0x0123 +phy_chain_rx_lane_map_physical{5.0}=0x0123 + +#FC 2 +phy_chain_tx_polarity_flip_physical{9}=0x0 +phy_chain_tx_polarity_flip_physical{10}=0x0 +phy_chain_tx_polarity_flip_physical{11}=0x0 +phy_chain_tx_polarity_flip_physical{12}=0x0 + +phy_chain_rx_polarity_flip_physical{9}=0x1 +phy_chain_rx_polarity_flip_physical{10}=0x1 +phy_chain_rx_polarity_flip_physical{11}=0x1 +phy_chain_rx_polarity_flip_physical{12}=0x1 + +phy_chain_tx_lane_map_physical{9.0}=0x0123 +phy_chain_rx_lane_map_physical{9.0}=0x0123 + +#FC 3 +phy_chain_tx_polarity_flip_physical{13}=0x0 +phy_chain_tx_polarity_flip_physical{14}=0x0 +phy_chain_tx_polarity_flip_physical{15}=0x0 +phy_chain_tx_polarity_flip_physical{16}=0x0 + +phy_chain_rx_polarity_flip_physical{13}=0x1 +phy_chain_rx_polarity_flip_physical{14}=0x1 +phy_chain_rx_polarity_flip_physical{15}=0x1 +phy_chain_rx_polarity_flip_physical{16}=0x1 + +phy_chain_tx_lane_map_physical{13.0}=0x0123 +phy_chain_rx_lane_map_physical{13.0}=0x0123 + +#FC 4 +phy_chain_tx_polarity_flip_physical{17}=0x0 +phy_chain_tx_polarity_flip_physical{18}=0x0 +phy_chain_tx_polarity_flip_physical{19}=0x0 +phy_chain_tx_polarity_flip_physical{20}=0x0 + +phy_chain_rx_polarity_flip_physical{17}=0x0 +phy_chain_rx_polarity_flip_physical{18}=0x0 +phy_chain_rx_polarity_flip_physical{19}=0x0 +phy_chain_rx_polarity_flip_physical{20}=0x0 + +phy_chain_tx_lane_map_physical{17.0}=0x0123 +phy_chain_rx_lane_map_physical{17.0}=0x0123 + +#FC 5 +phy_chain_tx_polarity_flip_physical{21}=0x0 +phy_chain_tx_polarity_flip_physical{22}=0x0 +phy_chain_tx_polarity_flip_physical{23}=0x0 +phy_chain_tx_polarity_flip_physical{24}=0x0 + +phy_chain_rx_polarity_flip_physical{21}=0x1 +phy_chain_rx_polarity_flip_physical{22}=0x1 +phy_chain_rx_polarity_flip_physical{23}=0x1 +phy_chain_rx_polarity_flip_physical{24}=0x1 + +phy_chain_tx_lane_map_physical{21.0}=0x0123 +phy_chain_rx_lane_map_physical{21.0}=0x0123 + +#FC 6 +phy_chain_tx_polarity_flip_physical{25}=0x0 +phy_chain_tx_polarity_flip_physical{26}=0x0 +phy_chain_tx_polarity_flip_physical{27}=0x0 +phy_chain_tx_polarity_flip_physical{28}=0x0 + +phy_chain_rx_polarity_flip_physical{25}=0x1 +phy_chain_rx_polarity_flip_physical{26}=0x1 +phy_chain_rx_polarity_flip_physical{27}=0x1 +phy_chain_rx_polarity_flip_physical{28}=0x1 + +phy_chain_tx_lane_map_physical{25.0}=0x0123 +phy_chain_rx_lane_map_physical{25.0}=0x0123 + +#FC 7 not use +phy_chain_tx_polarity_flip_physical{29}=0x0 +phy_chain_tx_polarity_flip_physical{30}=0x0 +phy_chain_tx_polarity_flip_physical{31}=0x0 +phy_chain_tx_polarity_flip_physical{32}=0x0 + +phy_chain_rx_polarity_flip_physical{29}=0x0 +phy_chain_rx_polarity_flip_physical{30}=0x0 +phy_chain_rx_polarity_flip_physical{31}=0x0 +phy_chain_rx_polarity_flip_physical{32}=0x0 + +phy_chain_tx_lane_map_physical{29.0}=0x0123 +phy_chain_rx_lane_map_physical{29.0}=0x0123 + +#FC 8 +phy_chain_tx_polarity_flip_physical{33}=0x1 +phy_chain_tx_polarity_flip_physical{34}=0x0 +phy_chain_tx_polarity_flip_physical{35}=0x1 +phy_chain_tx_polarity_flip_physical{36}=0x1 + +phy_chain_rx_polarity_flip_physical{33}=0x0 +phy_chain_rx_polarity_flip_physical{34}=0x0 +phy_chain_rx_polarity_flip_physical{35}=0x1 +phy_chain_rx_polarity_flip_physical{36}=0x0 + +phy_chain_tx_lane_map_physical{33.0}=0x3120 +phy_chain_rx_lane_map_physical{33.0}=0x0213 + +#FC 9 +phy_chain_tx_polarity_flip_physical{37}=0x0 +phy_chain_tx_polarity_flip_physical{38}=0x0 +phy_chain_tx_polarity_flip_physical{39}=0x1 +phy_chain_tx_polarity_flip_physical{40}=0x1 + +phy_chain_rx_polarity_flip_physical{37}=0x1 +phy_chain_rx_polarity_flip_physical{38}=0x1 +phy_chain_rx_polarity_flip_physical{39}=0x0 +phy_chain_rx_polarity_flip_physical{40}=0x0 + +phy_chain_tx_lane_map_physical{37.0}=0x2031 +phy_chain_rx_lane_map_physical{37.0}=0x1302 + +#FC 10 +phy_chain_tx_polarity_flip_physical{41}=0x0 +phy_chain_tx_polarity_flip_physical{42}=0x0 +phy_chain_tx_polarity_flip_physical{43}=0x0 +phy_chain_tx_polarity_flip_physical{44}=0x0 + +phy_chain_rx_polarity_flip_physical{41}=0x1 +phy_chain_rx_polarity_flip_physical{42}=0x1 +phy_chain_rx_polarity_flip_physical{43}=0x1 +phy_chain_rx_polarity_flip_physical{44}=0x1 + +phy_chain_tx_lane_map_physical{41.0}=0x3210 +phy_chain_rx_lane_map_physical{41.0}=0x0123 + +#FC 11 +phy_chain_tx_polarity_flip_physical{45}=0x0 +phy_chain_tx_polarity_flip_physical{46}=0x0 +phy_chain_tx_polarity_flip_physical{47}=0x1 +phy_chain_tx_polarity_flip_physical{48}=0x1 + +phy_chain_rx_polarity_flip_physical{45}=0x0 +phy_chain_rx_polarity_flip_physical{46}=0x0 +phy_chain_rx_polarity_flip_physical{47}=0x0 +phy_chain_rx_polarity_flip_physical{48}=0x1 + +phy_chain_tx_lane_map_physical{45.0}=0x3120 +phy_chain_rx_lane_map_physical{45.0}=0x2130 + +#FC 12 +phy_chain_tx_polarity_flip_physical{49}=0x1 +phy_chain_tx_polarity_flip_physical{50}=0x0 +phy_chain_tx_polarity_flip_physical{51}=0x0 +phy_chain_tx_polarity_flip_physical{52}=0x1 + +phy_chain_rx_polarity_flip_physical{49}=0x0 +phy_chain_rx_polarity_flip_physical{50}=0x1 +phy_chain_rx_polarity_flip_physical{51}=0x1 +phy_chain_rx_polarity_flip_physical{52}=0x0 + +phy_chain_tx_lane_map_physical{49.0}=0x3201 +phy_chain_rx_lane_map_physical{49.0}=0x1023 + +#FC 13 +phy_chain_tx_polarity_flip_physical{53}=0x0 +phy_chain_tx_polarity_flip_physical{54}=0x0 +phy_chain_tx_polarity_flip_physical{55}=0x1 +phy_chain_tx_polarity_flip_physical{56}=0x1 + +phy_chain_rx_polarity_flip_physical{53}=0x0 +phy_chain_rx_polarity_flip_physical{54}=0x0 +phy_chain_rx_polarity_flip_physical{55}=0x0 +phy_chain_rx_polarity_flip_physical{56}=0x1 + +phy_chain_tx_lane_map_physical{53.0}=0x3120 +phy_chain_rx_lane_map_physical{53.0}=0x2130 + +#FC 14 +phy_chain_tx_polarity_flip_physical{57}=0x1 +phy_chain_tx_polarity_flip_physical{58}=0x0 +phy_chain_tx_polarity_flip_physical{59}=0x0 +phy_chain_tx_polarity_flip_physical{60}=0x1 + +phy_chain_rx_polarity_flip_physical{57}=0x0 +phy_chain_rx_polarity_flip_physical{58}=0x1 +phy_chain_rx_polarity_flip_physical{59}=0x1 +phy_chain_rx_polarity_flip_physical{60}=0x0 + +phy_chain_tx_lane_map_physical{57.0}=0x3201 +phy_chain_rx_lane_map_physical{57.0}=0x1023 + +#FC 15 +phy_chain_tx_polarity_flip_physical{61}=0x0 +phy_chain_tx_polarity_flip_physical{62}=0x0 +phy_chain_tx_polarity_flip_physical{63}=0x0 +phy_chain_tx_polarity_flip_physical{64}=0x0 + +phy_chain_rx_polarity_flip_physical{61}=0x0 +phy_chain_rx_polarity_flip_physical{62}=0x0 +phy_chain_rx_polarity_flip_physical{63}=0x0 +phy_chain_rx_polarity_flip_physical{64}=0x0 + +phy_chain_tx_lane_map_physical{61.0}=0x3210 +phy_chain_rx_lane_map_physical{61.0}=0x3210 + +#FC 16 +phy_chain_tx_polarity_flip_physical{65}=0x0 +phy_chain_tx_polarity_flip_physical{66}=0x0 +phy_chain_tx_polarity_flip_physical{67}=0x0 +phy_chain_tx_polarity_flip_physical{68}=0x0 + +phy_chain_rx_polarity_flip_physical{65}=0x1 +phy_chain_rx_polarity_flip_physical{66}=0x1 +phy_chain_rx_polarity_flip_physical{67}=0x1 +phy_chain_rx_polarity_flip_physical{68}=0x1 + +phy_chain_tx_lane_map_physical{65.0}=0x3210 +phy_chain_rx_lane_map_physical{65.0}=0x3210 + +#FC 17 +phy_chain_tx_polarity_flip_physical{69}=0x0 +phy_chain_tx_polarity_flip_physical{70}=0x0 +phy_chain_tx_polarity_flip_physical{71}=0x0 +phy_chain_tx_polarity_flip_physical{72}=0x0 + +phy_chain_rx_polarity_flip_physical{69}=0x1 +phy_chain_rx_polarity_flip_physical{70}=0x1 +phy_chain_rx_polarity_flip_physical{71}=0x1 +phy_chain_rx_polarity_flip_physical{72}=0x1 + +phy_chain_tx_lane_map_physical{69.0}=0x3210 +phy_chain_rx_lane_map_physical{69.0}=0x3210 + +#FC 18 +phy_chain_tx_polarity_flip_physical{73}=0x0 +phy_chain_tx_polarity_flip_physical{74}=0x0 +phy_chain_tx_polarity_flip_physical{75}=0x0 +phy_chain_tx_polarity_flip_physical{76}=0x0 + +phy_chain_rx_polarity_flip_physical{73}=0x1 +phy_chain_rx_polarity_flip_physical{74}=0x1 +phy_chain_rx_polarity_flip_physical{75}=0x1 +phy_chain_rx_polarity_flip_physical{76}=0x1 + +phy_chain_tx_lane_map_physical{73.0}=0x3210 +phy_chain_rx_lane_map_physical{73.0}=0x3210 + +#FC 19 not use +phy_chain_tx_polarity_flip_physical{77}=0x0 +phy_chain_tx_polarity_flip_physical{78}=0x0 +phy_chain_tx_polarity_flip_physical{79}=0x0 +phy_chain_tx_polarity_flip_physical{80}=0x0 + +phy_chain_rx_polarity_flip_physical{77}=0x0 +phy_chain_rx_polarity_flip_physical{78}=0x0 +phy_chain_rx_polarity_flip_physical{79}=0x0 +phy_chain_rx_polarity_flip_physical{80}=0x0 + +phy_chain_tx_lane_map_physical{77.0}=0x3210 +phy_chain_rx_lane_map_physical{77.0}=0x3210 + + +#FC0 sfp28 port 0-3 +portmap_1=1:25 +portmap_2=2:25 +portmap_3=3:25 +portmap_4=4:25 + +#FC1 sfp28 port 4-7 +portmap_5=5:25 +portmap_6=6:25 +portmap_7=7:25 +portmap_8=8:25 + +#FC2 sfp28 port 8-11 +portmap_9=9:25 +portmap_10=10:25 +portmap_11=11:25 +portmap_12=12:25 + +#FC3 sfp28 port 12-15 +portmap_13=13:25 +portmap_14=14:25 +portmap_15=15:25 +portmap_16=16:25 + +#FC4 sfp28 port 16-19 +portmap_17=17:25 +portmap_18=18:25 +portmap_19=19:25 +portmap_20=20:25 + +#FC5 sfp28 port 20-23 +portmap_21=21:25 +portmap_22=22:25 +portmap_23=23:25 +portmap_24=24:25 + +#FC6 sfp28 port 24-27 +portmap_25=25:25 +portmap_26=26:25 +portmap_27=27:25 +portmap_28=28:25 + +#FC7 not use + +#FC10 sfp28 port 28-31 +portmap_33=41:25 +portmap_34=42:25 +portmap_35=43:25 +portmap_36=44:25 + +#FC15 sfp28 port 32-35 +portmap_37=61:25 +portmap_38=62:25 +portmap_39=63:25 +portmap_40=64:25 + +#FC16 sfp28 port 36-39 +portmap_41=65:25 +portmap_42=66:25 +portmap_43=67:25 +portmap_44=68:25 + +#FC17 sfp28 port 40-43 +portmap_45=69:25 +portmap_46=70:25 +portmap_47=71:25 +portmap_48=72:25 + +#FC18 sfp28 port 44-47 +portmap_49=73:25 +portmap_50=74:25 +portmap_51=75:25 +portmap_52=76:25 + +#FC9 qsfp port 48 +portmap_29=37:100 + +#FC8 qsfp port 49 +portmap_30=33:100 + +#FC11 qsfp port 50 +portmap_53=45:100 + +#FC12 qsfp port 51 +portmap_54=49:100 + +#FC13 qsfp port 52 +portmap_55=53:100 + +#FC14 qsfp port 53 +portmap_59=57:100 + +#FC19 not use + +# dport +dport_map_enable=1 + +dport_map_port_1=1 +dport_map_port_2=2 +dport_map_port_3=3 +dport_map_port_4=4 +dport_map_port_5=5 +dport_map_port_6=6 +dport_map_port_7=7 +dport_map_port_8=8 +dport_map_port_9=9 +dport_map_port_10=10 +dport_map_port_11=11 +dport_map_port_12=12 +dport_map_port_13=13 +dport_map_port_14=14 +dport_map_port_15=15 +dport_map_port_16=16 +dport_map_port_17=17 +dport_map_port_18=18 +dport_map_port_19=19 +dport_map_port_20=20 +dport_map_port_21=21 +dport_map_port_22=22 +dport_map_port_23=23 +dport_map_port_24=24 +dport_map_port_25=25 +dport_map_port_26=26 +dport_map_port_27=27 +dport_map_port_28=28 +dport_map_port_33=29 +dport_map_port_34=30 +dport_map_port_35=31 +dport_map_port_36=32 +dport_map_port_37=33 +dport_map_port_38=34 +dport_map_port_39=35 +dport_map_port_40=36 +dport_map_port_41=37 +dport_map_port_42=38 +dport_map_port_43=39 +dport_map_port_44=40 +dport_map_port_45=41 +dport_map_port_46=42 +dport_map_port_47=43 +dport_map_port_48=44 +dport_map_port_49=45 +dport_map_port_50=46 +dport_map_port_51=47 +dport_map_port_52=48 +dport_map_port_29=49 +dport_map_port_30=50 +dport_map_port_53=51 +dport_map_port_54=52 +dport_map_port_55=53 +dport_map_port_59=54 + +# cfg for timing +ptp_bs_fref_0=50000000 +ptp_bs_fref_1=50000000 + +port_flex_enable=1 +oversubscribe_mode=1 +core_clock_frequency=1525 + +#25G,10G and 1G support +serdes_10g_at_25g_vco=1 +serdes_1000x_at_25g_vco=1 + +l2xmsg_mode=1 +l2xmsg_hostbuf_size=16384 +module_64ports=0 + +#Interrupts and Parity +max_vp_lags=0 +schan_intr_enable=0 +tdma_timeout_usec=5000000 +stable_size=0x5500000 + +#Default L3 profile +l2_mem_entries=40960 +l3_alpm_enable=2 +l3_alpm_ipv6_128b_bkt_rsvd=1 +l3_mem_entries=40960 + +#Tunnels +use_all_splithorizon_groups=1 +sai_tunnel_support=1 +bcm_tunnel_term_compatible_mode=1 + +#RIOT Enable +riot_enable=1 +riot_overlay_l3_intf_mem_size=8192 +riot_overlay_l3_egress_mem_size=32768 +l3_ecmp_levels=2 +riot_overlay_ecmp_resilient_hash_size=16384 +pfc_deadlock_seq_control=1 + +mem_cache_enable=0 +ifp_inports_support_enable=1 +ipv6_lpm_128b_enable=0x1 +l3_max_ecmp_mode=1 +lpm_scaling_enable=0 +bcm_num_cos=10 +default_cpu_tx_queue=9 +mmu_lossless=0 +host_as_route_disable=1 +sai_fast_convergence_support=1 +flow_init_mode=1 +sai_interface_type_auto_detect=0 +mpls_mem_entries=16384 +vlan_xlate_1_mem_entries=65536 +vlan_xlate_2_mem_entries=16384 +sai_nbr_bcast_ifp_optimized=1 +sai_brcm_sonic_acl_enhancements=1 + +# Reduced Trap Group QSET for BRCM Sonic +sai_brcm_sonic_trap_group=1 +l2_entry_used_as_my_station=1 +multi_hash_recurse_depth_l3=2 + diff --git a/device/ufispace/x86_64-ufispace_s8901_54xc-r0/custom_led.bin b/device/ufispace/x86_64-ufispace_s8901_54xc-r0/custom_led.bin new file mode 100644 index 000000000000..af49a6baba15 Binary files /dev/null and b/device/ufispace/x86_64-ufispace_s8901_54xc-r0/custom_led.bin differ diff --git a/device/ufispace/x86_64-ufispace_s8901_54xc-r0/default_sku b/device/ufispace/x86_64-ufispace_s8901_54xc-r0/default_sku new file mode 100644 index 000000000000..c4420766f9ca --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s8901_54xc-r0/default_sku @@ -0,0 +1 @@ +UFISPACE-S8901-54XC t1 diff --git a/device/ufispace/x86_64-ufispace_s8901_54xc-r0/fancontrol b/device/ufispace/x86_64-ufispace_s8901_54xc-r0/fancontrol new file mode 100644 index 000000000000..1234cd994f3f --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s8901_54xc-r0/fancontrol @@ -0,0 +1,10 @@ +# Configuration file generated by pwmconfig, changes will be lost +INTERVAL=10 +DEVPATH= +DEVNAME= +FCTEMPS= +FCFANS= +MINTEMP= +MAXTEMP= +MINSTART= +MINSTOP= diff --git a/device/ufispace/x86_64-ufispace_s8901_54xc-r0/installer.conf b/device/ufispace/x86_64-ufispace_s8901_54xc-r0/installer.conf new file mode 100644 index 000000000000..8f9944da69a6 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s8901_54xc-r0/installer.conf @@ -0,0 +1,4 @@ +CONSOLE_PORT=0x3f8 +CONSOLE_DEV=0 +CONSOLE_SPEED=115200 +ONIE_PLATFORM_EXTRA_CMDLINE_LINUX="module_blacklist=gpio_ich nomodeset pcie_aspm=off" diff --git a/device/ufispace/x86_64-ufispace_s8901_54xc-r0/led_proc_init.soc b/device/ufispace/x86_64-ufispace_s8901_54xc-r0/led_proc_init.soc new file mode 100644 index 000000000000..57ee7fedaf2b --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s8901_54xc-r0/led_proc_init.soc @@ -0,0 +1,3 @@ +m0 load 0 0x3800 /usr/share/sonic/platform/custom_led.bin +led auto on +led start diff --git a/device/ufispace/x86_64-ufispace_s8901_54xc-r0/pcie.yaml b/device/ufispace/x86_64-ufispace_s8901_54xc-r0/pcie.yaml new file mode 100644 index 000000000000..341b6836826b --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s8901_54xc-r0/pcie.yaml @@ -0,0 +1,172 @@ +- bus: '00' + dev: '00' + fn: '0' + id: '1980' + name: 'Host bridge: Intel Corporation Atom Processor C3000 Series System Agent (rev + 11)' +- bus: '00' + dev: '04' + fn: '0' + id: 19a1 + name: 'Host bridge: Intel Corporation Atom Processor C3000 Series Error Registers + (rev 11)' +- bus: '00' + dev: '05' + fn: '0' + id: 19a2 + name: 'Generic system peripheral [0807]: Intel Corporation Atom Processor C3000 + Series Root Complex Event Collector (rev 11)' +- bus: '00' + dev: '06' + fn: '0' + id: 19a3 + name: 'PCI bridge: Intel Corporation Atom Processor C3000 Series Integrated QAT + Root Port (rev 11)' +- bus: '00' + dev: 09 + fn: '0' + id: 19a4 + name: 'PCI bridge: Intel Corporation Atom Processor C3000 Series PCI Express Root + Port #0 (rev 11)' +- bus: '00' + dev: 0a + fn: '0' + id: 19a5 + name: 'PCI bridge: Intel Corporation Atom Processor C3000 Series PCI Express Root + Port #1 (rev 11)' +- bus: '00' + dev: 0b + fn: '0' + id: 19a6 + name: 'PCI bridge: Intel Corporation Atom Processor C3000 Series PCI Express Root + Port #2 (rev 11)' +- bus: '00' + dev: 0e + fn: '0' + id: 19a8 + name: 'PCI bridge: Intel Corporation Atom Processor C3000 Series PCI Express Root + Port #4 (rev 11)' +- bus: '00' + dev: 0f + fn: '0' + id: 19a9 + name: 'PCI bridge: Intel Corporation Atom Processor C3000 Series PCI Express Root + Port #5 (rev 11)' +- bus: '00' + dev: '10' + fn: '0' + id: 19aa + name: 'PCI bridge: Intel Corporation Atom Processor C3000 Series PCI Express Root + Port #6 (rev 11)' +- bus: '00' + dev: '11' + fn: '0' + id: 19ab + name: 'PCI bridge: Intel Corporation Atom Processor C3000 Series PCI Express Root + Port #7 (rev 11)' +- bus: '00' + dev: '12' + fn: '0' + id: 19ac + name: 'System peripheral: Intel Corporation Atom Processor C3000 Series SMBus Contoller + - Host (rev 11)' +- bus: '00' + dev: '14' + fn: '0' + id: 19c2 + name: 'SATA controller: Intel Corporation Atom Processor C3000 Series SATA Controller + 1 (rev 11)' +- bus: '00' + dev: '15' + fn: '0' + id: 19d0 + name: 'USB controller: Intel Corporation Atom Processor C3000 Series USB 3.0 xHCI + Controller (rev 11)' +- bus: '00' + dev: '16' + fn: '0' + id: 19d1 + name: 'PCI bridge: Intel Corporation Atom Processor C3000 Series Integrated LAN + Root Port #0 (rev 11)' +- bus: '00' + dev: '17' + fn: '0' + id: 19d2 + name: 'PCI bridge: Intel Corporation Atom Processor C3000 Series Integrated LAN + Root Port #1 (rev 11)' +- bus: '00' + dev: '18' + fn: '0' + id: 19d3 + name: 'Communication controller: Intel Corporation Atom Processor C3000 Series ME + HECI 1 (rev 11)' +- bus: '00' + dev: 1c + fn: '0' + id: 19db + name: 'SD Host controller: Intel Corporation Device 19db (rev 11)' +- bus: '00' + dev: 1f + fn: '0' + id: 19dc + name: 'ISA bridge: Intel Corporation Atom Processor C3000 Series LPC or eSPI (rev + 11)' +- bus: '00' + dev: 1f + fn: '2' + id: 19de + name: 'Memory controller: Intel Corporation Atom Processor C3000 Series Power Management + Controller (rev 11)' +- bus: '00' + dev: 1f + fn: '4' + id: 19df + name: 'SMBus: Intel Corporation Atom Processor C3000 Series SMBus controller (rev + 11)' +- bus: '00' + dev: 1f + fn: '5' + id: 19e0 + name: 'Serial bus controller [0c80]: Intel Corporation Atom Processor C3000 Series + SPI Controller (rev 11)' +- bus: '01' + dev: '00' + fn: '0' + id: 19e2 + name: 'Co-processor: Intel Corporation Atom Processor C3000 Series QuickAssist Technology + (rev 11)' +- bus: '04' + dev: '00' + fn: '0' + id: b770 + name: 'Ethernet controller: Broadcom Inc. and subsidiaries Device b770 (rev 01)' +- bus: '06' + dev: '00' + fn: '0' + id: '1533' + name: 'Ethernet controller: Intel Corporation I210 Gigabit Network Connection (rev + 03)' +- bus: 09 + dev: '00' + fn: '0' + id: 15c3 + name: 'Ethernet controller: Intel Corporation Ethernet Connection X553 Backplane + (rev 11)' +- bus: 09 + dev: '00' + fn: '1' + id: 15c3 + name: 'Ethernet controller: Intel Corporation Ethernet Connection X553 Backplane + (rev 11)' +- bus: 0a + dev: '00' + fn: '0' + id: 15c3 + name: 'Ethernet controller: Intel Corporation Ethernet Connection X553 Backplane + (rev 11)' +- bus: 0a + dev: '00' + fn: '1' + id: 15c3 + name: 'Ethernet controller: Intel Corporation Ethernet Connection X553 Backplane + (rev 11)' diff --git a/device/ufispace/x86_64-ufispace_s8901_54xc-r0/pddf/pd-plugin.json b/device/ufispace/x86_64-ufispace_s8901_54xc-r0/pddf/pd-plugin.json new file mode 100644 index 000000000000..81ff5e283bc9 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s8901_54xc-r0/pddf/pd-plugin.json @@ -0,0 +1,97 @@ +{ + + "XCVR": + { + "xcvr_present": + { + "i2c": + { + "valmap-SFP": {"1":true, "0":false }, + "valmap-SFP28": {"1":true, "0":false }, + "valmap-QSFP28": {"1":true, "0":false }, + "valmap-QSFP-DD": {"1":true, "0":false} + } + }, + + "plug_status": + { + "inserted": "1", + "removed": "0" + } + }, + "PSU": + { + "psu_present": + { + "i2c": + { + "valmap": { "1":true, "0":false } + }, + "bmc": + { + "valmap": { "0x0280|":true, "0x0180|":false } + } + }, + + "psu_power_good": + { + "i2c": + { + "valmap": { "1": true, "0":false } + }, + "bmc": + { + "valmap": { "0x0280|":true, "0x0180|":false } + } + }, + + "psu_fan_dir": + { + "bmc": + { + "valmap": {"0": "UNKNOWN", "1":"INTAKE", "2":"EXHAUST"} + } + }, + + "psu_support_list": + [ + {"Manufacturer": "FSPGROUP", "Name": "YNEB0450BM", "MaxSpd": "PSU_FAN_MAX_SPEED_AC"}, + {"Manufacturer": "FSPGROUP", "Name": "YNEB0450AM", "MaxSpd": "PSU_FAN_MAX_SPEED_DC"}, + {"Manufacturer": "DELTA", "Name": "DPS-450AB-27", "MaxSpd": "PSU_FAN_MAX_SPEED_AC"}, + {"Manufacturer": "DELTA", "Name": "DPS-450AB-28", "MaxSpd": "PSU_FAN_MAX_SPEED_DC"} + ], + + "valmap": { + "PSU_FAN_MAX_SPEED":"20000", + "PSU_FAN_MAX_SPEED_AC":"20000", + "PSU_FAN_MAX_SPEED_DC":"18000" + } + }, + "FAN": + { + "direction": + { + "bmc": + { + "valmap": {"0": "UNKNOWN", "1":"INTAKE", "2":"EXHAUST"} + } + }, + + "present": + { + "i2c": + { + "valmap": {"1":true, "0":false} + }, + "bmc": + { + "valmap": { "0x0280|":true, "0x0180|":false, "Device Present":true, "Device Absent":false} + } + }, + "FAN_MAX_SPEED":"25000" + }, + "REBOOT_CAUSE": + { + "reboot_cause_file": "/host/reboot-cause/reboot-cause.txt" + } +} diff --git a/device/ufispace/x86_64-ufispace_s8901_54xc-r0/pddf/pddf-device.json b/device/ufispace/x86_64-ufispace_s8901_54xc-r0/pddf/pddf-device.json new file mode 100644 index 000000000000..18d0dd9abe2b --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s8901_54xc-r0/pddf/pddf-device.json @@ -0,0 +1,7850 @@ +{ + "PLATFORM": { + "num_psus": 2, + "num_fantrays": 5, + "num_fans_pertray": 1, + "num_ports": 54, + "num_temps": 8, + "pddf_dev_types": { + "description": "PDDF supported devices", + "CPLD": [ + "i2c_cpld" + ], + "PSU": [ + "psu_eeprom", + "psu_pmbus" + ], + "PORT_MODULE": [ + "pddf_xcvr" + ] + }, + "std_kos": [ + "i2c_i801", + "i2c_ismt", + "i2c_dev", + "i2c_mux_pca954x", + "coretemp", + "optoe", + "gpio-pca953x" + ], + "pddf_kos": [ + "pddf_client_module", + "pddf_cpld_module", + "pddf_cpld_driver", + "pddf_mux_module", + "pddf_xcvr_module", + "pddf_xcvr_driver_module", + "pddf_psu_driver_module", + "pddf_psu_module", + "pddf_fan_driver_module", + "pddf_fan_module", + "pddf_led_module", + "pddf_gpio_module" + ], + "custom_kos": [ + "x86-64-ufispace-s8901-54xc-lpc", + "x86-64-ufispace-s8901-54xc-sys-eeprom", + "pddf_custom_sysstatus_module" + ] + }, + "SYSTEM": { + "dev_info": { + "device_type": "CPU", + "device_name": "ROOT_COMPLEX", + "device_parent": null + }, + "i2c": { + "CONTROLLERS": [ + { + "dev_name": "i2c-1", + "dev": "SMBUS1" + }, + { + "dev_name": "i2c-0", + "dev": "SMBUS0" + } + ] + } + }, + "SMBUS0": { + "dev_info": { + "device_type": "SMBUS", + "device_name": "SMBUS0", + "device_parent": "SYSTEM" + }, + "i2c": { + "topo_info": { + "dev_addr": "0x0" + }, + "DEVICES": [ + { + "dev": "MUX3" + } + ] + } + }, + "SMBUS1": { + "dev_info": { + "device_type": "SMBUS", + "device_name": "SMBUS1", + "device_parent": "SYSTEM" + }, + "i2c": { + "topo_info": { + "dev_addr": "0x1" + }, + "DEVICES": [ + { + "dev": "MUX1" + }, + { + "dev": "MUX2" + } + ] + } + }, + "MUX1": { + "dev_info": { + "device_type": "MUX", + "device_name": "MUX1", + "device_parent": "SMBUS1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1", + "dev_addr": "0x70", + "dev_type": "pca9548" + }, + "dev_attr": { + "virt_bus": "0x2", + "idle_state": "-2" + }, + "channel": [ + { + "chn": "0", + "dev": "CPLD1" + }, + { + "chn": "0", + "dev": "CPLD2" + }, + { + "chn": "0", + "dev": "PSU1" + }, + { + "chn": "0", + "dev": "PSU2" + }, + { + "chn": "3", + "dev": "EEPROM1" + }, + { + "chn": "4", + "dev": "GPIO1" + }, + { + "chn": "4", + "dev": "GPIO2" + }, + { + "chn": "5", + "dev": "GPIO3" + }, + { + "chn": "5", + "dev": "GPIO4" + } + ] + } + }, + "MUX2": { + "dev_info": { + "device_type": "MUX", + "device_name": "MUX2", + "device_parent": "SMBUS1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1", + "dev_addr": "0x71", + "dev_type": "pca9548" + }, + "dev_attr": { + "virt_bus": "0xa", + "idle_state": "-2" + }, + "channel": [ + ] + } + }, + "MUX3": { + "dev_info": { + "device_type": "MUX", + "device_name": "MUX3", + "device_parent": "SMBUS0" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x0", + "dev_addr": "0x72", + "dev_type": "pca9548" + }, + "dev_attr": { + "virt_bus": "0x12", + "idle_state": "-2" + }, + "channel": [ + { + "chn": "0", + "dev": "MUX4" + }, + { + "chn": "1", + "dev": "MUX5" + }, + { + "chn": "2", + "dev": "MUX6" + }, + { + "chn": "3", + "dev": "MUX7" + }, + { + "chn": "4", + "dev": "MUX8" + }, + { + "chn": "5", + "dev": "MUX9" + }, + { + "chn": "6", + "dev": "MUX10" + } + ] + } + }, + "MUX4": { + "dev_info": { + "device_type": "MUX", + "device_name": "MUX4", + "device_parent": "MUX3" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x12", + "dev_addr": "0x73", + "dev_type": "pca9548" + }, + "dev_attr": { + "virt_bus": "0x1a", + "idle_state": "-2" + }, + "channel": [ + { + "chn": "0", + "dev": "PORT1" + }, + { + "chn": "1", + "dev": "PORT2" + }, + { + "chn": "2", + "dev": "PORT3" + }, + { + "chn": "3", + "dev": "PORT4" + }, + { + "chn": "4", + "dev": "PORT5" + }, + { + "chn": "5", + "dev": "PORT6" + }, + { + "chn": "6", + "dev": "PORT7" + }, + { + "chn": "7", + "dev": "PORT8" + } + ] + } + }, + "MUX5": { + "dev_info": { + "device_type": "MUX", + "device_name": "MUX5", + "device_parent": "MUX3" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x13", + "dev_addr": "0x73", + "dev_type": "pca9548" + }, + "dev_attr": { + "virt_bus": "0x22", + "idle_state": "-2" + }, + "channel": [ + { + "chn": "0", + "dev": "PORT9" + }, + { + "chn": "1", + "dev": "PORT10" + }, + { + "chn": "2", + "dev": "PORT11" + }, + { + "chn": "3", + "dev": "PORT12" + }, + { + "chn": "4", + "dev": "PORT13" + }, + { + "chn": "5", + "dev": "PORT14" + }, + { + "chn": "6", + "dev": "PORT15" + }, + { + "chn": "7", + "dev": "PORT16" + } + ] + } + }, + "MUX6": { + "dev_info": { + "device_type": "MUX", + "device_name": "MUX6", + "device_parent": "MUX3" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x14", + "dev_addr": "0x73", + "dev_type": "pca9548" + }, + "dev_attr": { + "virt_bus": "0x2a", + "idle_state": "-2" + }, + "channel": [ + { + "chn": "0", + "dev": "PORT17" + }, + { + "chn": "1", + "dev": "PORT18" + }, + { + "chn": "2", + "dev": "PORT19" + }, + { + "chn": "3", + "dev": "PORT20" + }, + { + "chn": "4", + "dev": "PORT21" + }, + { + "chn": "5", + "dev": "PORT22" + }, + { + "chn": "6", + "dev": "PORT23" + }, + { + "chn": "7", + "dev": "PORT24" + } + ] + } + }, + "MUX7": { + "dev_info": { + "device_type": "MUX", + "device_name": "MUX7", + "device_parent": "MUX3" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x15", + "dev_addr": "0x73", + "dev_type": "pca9548" + }, + "dev_attr": { + "virt_bus": "032", + "idle_state": "-2" + }, + "channel": [ + { + "chn": "0", + "dev": "PORT25" + }, + { + "chn": "1", + "dev": "PORT26" + }, + { + "chn": "2", + "dev": "PORT27" + }, + { + "chn": "3", + "dev": "PORT28" + }, + { + "chn": "4", + "dev": "PORT29" + }, + { + "chn": "5", + "dev": "PORT30" + }, + { + "chn": "6", + "dev": "PORT31" + }, + { + "chn": "7", + "dev": "PORT32" + } + ] + } + }, + "MUX8": { + "dev_info": { + "device_type": "MUX", + "device_name": "MUX8", + "device_parent": "MUX3" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x16", + "dev_addr": "0x73", + "dev_type": "pca9548" + }, + "dev_attr": { + "virt_bus": "03a", + "idle_state": "-2" + }, + "channel": [ + { + "chn": "0", + "dev": "PORT33" + }, + { + "chn": "1", + "dev": "PORT34" + }, + { + "chn": "2", + "dev": "PORT35" + }, + { + "chn": "3", + "dev": "PORT36" + }, + { + "chn": "4", + "dev": "PORT37" + }, + { + "chn": "5", + "dev": "PORT38" + }, + { + "chn": "6", + "dev": "PORT39" + }, + { + "chn": "7", + "dev": "PORT40" + } + ] + } + }, + "MUX9": { + "dev_info": { + "device_type": "MUX", + "device_name": "MUX9", + "device_parent": "MUX3" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x17", + "dev_addr": "0x73", + "dev_type": "pca9548" + }, + "dev_attr": { + "virt_bus": "042", + "idle_state": "-2" + }, + "channel": [ + { + "chn": "0", + "dev": "PORT41" + }, + { + "chn": "1", + "dev": "PORT42" + }, + { + "chn": "2", + "dev": "PORT43" + }, + { + "chn": "3", + "dev": "PORT44" + }, + { + "chn": "4", + "dev": "PORT45" + }, + { + "chn": "5", + "dev": "PORT46" + }, + { + "chn": "6", + "dev": "PORT47" + }, + { + "chn": "7", + "dev": "PORT48" + } + ] + } + }, + "MUX10": { + "dev_info": { + "device_type": "MUX", + "device_name": "MUX10", + "device_parent": "MUX3" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x18", + "dev_addr": "0x73", + "dev_type": "pca9548" + }, + "dev_attr": { + "virt_bus": "04a", + "idle_state": "-2" + }, + "channel": [ + { + "chn": "0", + "dev": "PORT49" + }, + { + "chn": "1", + "dev": "PORT50" + }, + { + "chn": "2", + "dev": "PORT51" + }, + { + "chn": "3", + "dev": "PORT52" + }, + { + "chn": "4", + "dev": "PORT53" + }, + { + "chn": "5", + "dev": "PORT54" + } + ] + } + }, + "CPLD1": { + "dev_info": { + "device_type": "CPLD", + "device_name": "CPLD1", + "device_parent": "MUX1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2", + "dev_addr": "0x30", + "dev_type": "i2c_cpld" + }, + "dev_attr": {} + } + }, + "CPLD2": { + "dev_info": { + "device_type": "CPLD", + "device_name": "CPLD2", + "device_parent": "MUX1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2", + "dev_addr": "0x31", + "dev_type": "i2c_cpld" + }, + "dev_attr": {} + } + }, + "SYSSTATUS": { + "dev_info": { + "device_type": "SYSSTAT", + "device_name": "SYSSTATUS" + }, + "dev_attr": {}, + "attr_list": + [ + { + "attr_name": "board_sku_id", + "attr_devaddr": "0x30", + "attr_offset": "0x0", + "attr_mask": "0xff", + "attr_len": "0x1" + }, + { + "attr_name": "board_hw_id", + "attr_devaddr": "0x30", + "attr_offset": "0x1", + "attr_mask": "0x03", + "attr_len": "0x1" + }, + { + "attr_name": "board_deph_id", + "attr_devaddr": "0x30", + "attr_offset": "0x1", + "attr_mask": "0x4", + "attr_len": "0x1" + }, + { + "attr_name": "board_build_id", + "attr_devaddr": "0x30", + "attr_offset": "0x1", + "attr_mask": "0x18", + "attr_len": "0x1" + }, + { + "attr_name": "cpld1_major_ver", + "attr_devaddr": "0x30", + "attr_offset": "0x2", + "attr_mask": "0xc0", + "attr_len": "0x1" + }, + { + "attr_name": "cpld1_minor_ver", + "attr_devaddr": "0x30", + "attr_offset": "0x2", + "attr_mask": "0x3f", + "attr_len": "0x1" + }, + { + "attr_name": "cpld1_build", + "attr_devaddr": "0x30", + "attr_offset": "0x4", + "attr_mask": "0xff", + "attr_len": "0x1" + }, + { + "attr_name": "cpld2_major_ver", + "attr_devaddr": "0x31", + "attr_offset": "0x2", + "attr_mask": "0xc0", + "attr_len": "0x1" + }, + { + "attr_name": "cpld2_minor_ver", + "attr_devaddr": "0x31", + "attr_offset": "0x2", + "attr_mask": "0x3f", + "attr_len": "0x1" + }, + { + "attr_name": "cpld2_build", + "attr_devaddr": "0x31", + "attr_offset": "0x4", + "attr_mask": "0xff", + "attr_len": "0x1" + }, + { + "attr_name": "psu_status", + "attr_devaddr": "0x30", + "attr_offset": "0x51", + "attr_mask": "0xff", + "attr_len": "0x1" + }, + { + "attr_name": "system_led_psu", + "attr_devaddr": "0x30", + "attr_offset": "0x80", + "attr_mask": "0xff", + "attr_len": "0x1" + }, + { + "attr_name": "system_led_sys", + "attr_devaddr": "0x30", + "attr_offset": "0x81", + "attr_mask": "0xff", + "attr_len": "0x1" + }, + { + "attr_name": "system_led_sync", + "attr_devaddr": "0x30", + "attr_offset": "0x82", + "attr_mask": "0xff", + "attr_len": "0x1" + }, + { + "attr_name": "system_led_fan", + "attr_devaddr": "0x30", + "attr_offset": "0x83", + "attr_mask": "0xff", + "attr_len": "0x1" + }, + { + "attr_name": "system_led_id", + "attr_devaddr": "0x30", + "attr_offset": "0x84", + "attr_mask": "0xff", + "attr_len": "0x1" + } + ] + }, + "EEPROM1": { + "dev_info": { + "device_type": "EEPROM", + "device_name": "EEPROM1", + "device_parent": "MUX1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x5", + "dev_addr": "0x53", + "dev_type": "sys_eeprom" + }, + "dev_attr": { + "access_mode": "BLOCK" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "GPIO1": { + "dev_info": { + "device_type": "GPIO", + "device_name": "GPIO1", + "device_parent": "MUX1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x6", + "dev_addr": "0x22", + "dev_type": "tca6424" + }, + "dev_attr": { + "gpio_base": "0x1d0" + }, + "ports": [ + { + "port_num": "0", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "1", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "2", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "3", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "4", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "5", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "6", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "7", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "8", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "9", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "10", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "11", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "12", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "13", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "14", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "15", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "16", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "17", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "18", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "19", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "20", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "21", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "22", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "23", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + } + ] + } + }, + "GPIO2": { + "dev_info": { + "device_type": "GPIO", + "device_name": "GPIO2", + "device_parent": "MUX1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x6", + "dev_addr": "0x23", + "dev_type": "tca6424" + }, + "dev_attr": { + "gpio_base": "0x1a0" + }, + "ports": [ + { + "port_num": "0", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "1", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "2", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "3", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "4", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "5", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "6", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "7", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "8", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "9", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "10", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "11", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "12", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "13", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "14", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "15", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "16", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "17", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "18", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "19", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "20", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "21", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "22", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "23", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + } + ] + } + }, + "GPIO3": { + "dev_info": { + "device_type": "GPIO", + "device_name": "GPIO3", + "device_parent": "MUX1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x7", + "dev_addr": "0x22", + "dev_type": "tca6424" + }, + "dev_attr": { + "gpio_base": "0x1e8" + }, + "ports": [ + { + "port_num": "0", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "1", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "2", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "3", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "4", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "5", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "6", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "7", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "8", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "9", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "10", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "11", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "12", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "13", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "14", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "15", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "16", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "17", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "18", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "19", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "20", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "21", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "22", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "23", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + } + ] + } + }, + "GPIO4": { + "dev_info": { + "device_type": "GPIO", + "device_name": "GPIO4", + "device_parent": "MUX1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x7", + "dev_addr": "0x23", + "dev_type": "tca6424" + }, + "dev_attr": { + "gpio_base": "0x1b8" + }, + "ports": [ + { + "port_num": "0", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "1", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "2", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "3", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "4", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "5", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "6", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "7", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "8", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "9", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "10", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "11", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "12", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "13", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "14", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "15", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "16", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "17", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "18", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "19", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "20", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "21", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "22", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + }, + { + "port_num": "23", + "direction": "out", + "value": "1", + "edge": "", + "active_low": "" + } + ] + } + }, + "TEMP1": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TEMP1", + "device_parent": "SMBUS0" + }, + "dev_attr": { + "display_name": "TEMP_MAC" + }, + "bmc": { + "ipmitool": { + "attr_list": [ + { + "attr_name": "temp1_input", + "bmc_cmd": "ipmitool sdr -c get TEMP_MAC", + "raw": "0", + "field_name": "TEMP_MAC", + "field_pos": "2", + "separator": "," + }, + { + "attr_name": "temp1_high_crit_threshold", + "bmc_cmd": "ipmitool sdr -c get TEMP_MAC", + "raw": "0", + "field_name": "TEMP_MAC", + "field_pos": "12", + "separator": "," + }, + { + "attr_name": "temp1_high_threshold", + "bmc_cmd": "ipmitool sdr -c get TEMP_MAC", + "raw": "0", + "field_name": "TEMP_MAC", + "field_pos": "13", + "separator": "," + } + ] + } + } + }, + "TEMP2": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TEMP2", + "device_parent": "SMBUS0" + }, + "dev_attr": { + "display_name": "TEMP_ENV_MACCASE" + }, + "bmc": { + "ipmitool": { + "attr_list": [ + { + "attr_name": "temp1_input", + "bmc_cmd": "ipmitool sdr -c get TEMP_ENV_MACCASE", + "raw": "0", + "field_name": "TEMP_ENV_MACCASE", + "field_pos": "2", + "separator": "," + }, + { + "attr_name": "temp1_high_crit_threshold", + "bmc_cmd": "ipmitool sdr -c get TEMP_ENV_MACCASE", + "raw": "0", + "field_name": "TEMP_ENV_MACCASE", + "field_pos": "12", + "separator": "," + }, + { + "attr_name": "temp1_high_threshold", + "bmc_cmd": "ipmitool sdr -c get TEMP_ENV_MACCASE", + "raw": "0", + "field_name": "TEMP_ENV_MACCASE", + "field_pos": "13", + "separator": "," + } + ] + } + } + }, + "TEMP3": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TEMP3", + "device_parent": "SMBUS0" + }, + "dev_attr": { + "display_name": "TEMP_ENV_PSUCASE" + }, + "bmc": { + "ipmitool": { + "attr_list": [ + { + "attr_name": "temp1_input", + "bmc_cmd": "ipmitool sdr -c get TEMP_ENV_PSUCASE", + "raw": "0", + "field_name": "TEMP_ENV_PSUCASE", + "field_pos": "2", + "separator": "," + }, + { + "attr_name": "temp1_high_crit_threshold", + "bmc_cmd": "ipmitool sdr -c get TEMP_ENV_PSUCASE", + "raw": "0", + "field_name": "TEMP_ENV_PSUCASE", + "field_pos": "12", + "separator": "," + }, + { + "attr_name": "temp1_high_threshold", + "bmc_cmd": "ipmitool sdr -c get TEMP_ENV_PSUCASE", + "raw": "0", + "field_name": "TEMP_ENV_PSUCASE", + "field_pos": "13", + "separator": "," + } + ] + } + } + }, + "TEMP4": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TEMP4", + "device_parent": "SMBUS0" + }, + "dev_attr": { + "display_name": "TEMP_ENV_FANCONN" + }, + "bmc": { + "ipmitool": { + "attr_list": [ + { + "attr_name": "temp1_input", + "bmc_cmd": "ipmitool sdr -c get TEMP_ENV_FANCONN", + "raw": "0", + "field_name": "TEMP_ENV_FANCONN", + "field_pos": "2", + "separator": "," + }, + { + "attr_name": "temp1_high_crit_threshold", + "bmc_cmd": "ipmitool sdr -c get TEMP_ENV_FANCONN", + "raw": "0", + "field_name": "TEMP_ENV_FANCONN", + "field_pos": "12", + "separator": "," + }, + { + "attr_name": "temp1_high_threshold", + "bmc_cmd": "ipmitool sdr -c get TEMP_ENV_FANCONN", + "raw": "0", + "field_name": "TEMP_ENV_FANCONN", + "field_pos": "13", + "separator": "," + } + ] + } + } + }, + "TEMP5": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TEMP5", + "device_parent": "SMBUS0" + }, + "dev_attr": { + "display_name": "TEMP_ENV_FANCARD" + }, + "bmc": { + "ipmitool": { + "attr_list": [ + { + "attr_name": "temp1_input", + "bmc_cmd": "ipmitool sdr -c get TEMP_ENV_FANCARD", + "raw": "0", + "field_name": "TEMP_ENV_FANCARD", + "field_pos": "2", + "separator": "," + }, + { + "attr_name": "temp1_high_crit_threshold", + "bmc_cmd": "ipmitool sdr -c get TEMP_ENV_FANCARD", + "raw": "0", + "field_name": "TEMP_ENV_FANCARD", + "field_pos": "12", + "separator": "," + }, + { + "attr_name": "temp1_high_threshold", + "bmc_cmd": "ipmitool sdr -c get TEMP_ENV_FANCARD", + "raw": "0", + "field_name": "TEMP_ENV_FANCARD", + "field_pos": "13", + "separator": "," + } + ] + } + } + }, + "TEMP6": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TEMP6", + "device_parent": "SMBUS0" + }, + "dev_attr": { + "display_name": "TEMP_ENV_BMC" + }, + "bmc": { + "ipmitool": { + "attr_list": [ + { + "attr_name": "temp1_input", + "bmc_cmd": "ipmitool sdr -c get TEMP_ENV_BMC", + "raw": "0", + "field_name": "TEMP_ENV_BMC", + "field_pos": "2", + "separator": "," + }, + { + "attr_name": "temp1_high_crit_threshold", + "bmc_cmd": "ipmitool sdr -c get TEMP_ENV_BMC", + "raw": "0", + "field_name": "TEMP_ENV_BMC", + "field_pos": "12", + "separator": "," + }, + { + "attr_name": "temp1_high_threshold", + "bmc_cmd": "ipmitool sdr -c get TEMP_ENV_BMC", + "raw": "0", + "field_name": "TEMP_ENV_BMC", + "field_pos": "13", + "separator": "," + } + ] + } + } + }, + "TEMP7": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TEMP7", + "device_parent": "SMBUS0" + }, + "dev_attr": { + "display_name": "TEMP_PSU0_TEMP1" + }, + "bmc": { + "ipmitool": { + "attr_list": [ + { + "attr_name": "temp1_input", + "bmc_cmd": "ipmitool sdr -c get PSU0_TEMP1 | sed -e 's/,,/,0,/g' -e 's/,,/,0,/g'", + "raw": "0", + "field_name": "PSU0_TEMP1", + "field_pos": "2", + "separator": "," + }, + { + "attr_name": "temp1_high_crit_threshold", + "bmc_cmd": "ipmitool sdr -c get PSU0_TEMP1", + "raw": "0", + "field_name": "PSU0_TEMP1", + "field_pos": "12", + "separator": "," + }, + { + "attr_name": "temp1_high_threshold", + "bmc_cmd": "ipmitool sdr -c get PSU0_TEMP1", + "raw": "0", + "field_name": "PSU0_TEMP1", + "field_pos": "13", + "separator": "," + } + ] + } + } + }, + "TEMP8": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TEMP8", + "device_parent": "SMBUS0" + }, + "dev_attr": { + "display_name": "TEMP_PSU1_TEMP1" + }, + "bmc": { + "ipmitool": { + "attr_list": [ + { + "attr_name": "temp1_input", + "bmc_cmd": "ipmitool sdr -c get PSU1_TEMP1 | sed -e 's/,,/,0,/g' -e 's/,,/,0,/g'", + "raw": "0", + "field_name": "PSU1_TEMP1", + "field_pos": "2", + "separator": "," + }, + { + "attr_name": "temp1_high_crit_threshold", + "bmc_cmd": "ipmitool sdr -c get PSU1_TEMP1", + "raw": "0", + "field_name": "PSU1_TEMP1", + "field_pos": "12", + "separator": "," + }, + { + "attr_name": "temp1_high_threshold", + "bmc_cmd": "ipmitool sdr -c get PSU1_TEMP1", + "raw": "0", + "field_name": "PSU1_TEMP1", + "field_pos": "13", + "separator": "," + } + ] + } + } + }, + "PSU1": { + "dev_info": { + "device_type": "PSU", + "device_name": "PSU1", + "device_parent": "MUX1" + }, + "dev_attr": { + "dev_idx": "1", + "num_psu_fans": "1" + }, + "i2c": { + "interface": [ + { "itf":"eeprom", "dev":"PSU1-EEPROM" } + ] + }, + "bmc": { + "ipmitool": { + "attr_list": [ + { + "attr_name": "psu_temp1_input", + "bmc_cmd": "ipmitool sdr -c get PSU0_TEMP1 | sed -e 's/,,/,0,/g' -e 's/,,/,0,/g'", + "raw": "0", + "field_name": "PSU0_TEMP1", + "field_pos": "2", + "mult": "1000", + "separator": "," + }, + { + "attr_name": "psu_fan1_speed_rpm", + "bmc_cmd": "ipmitool sdr -c get PSU0_FAN1 | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "field_name": "PSU0_FAN1", + "field_pos": "2", + "separator": "," + }, + { + "attr_name": "psu_v_out", + "bmc_cmd": "ipmitool sdr -c get PSU0_VOUT | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "field_name": "PSU0_VOUT", + "field_pos": "2", + "mult": "1000", + "separator": "," + }, + { + "attr_name": "psu_i_out", + "bmc_cmd": "ipmitool sdr -c get PSU0_IOUT | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "field_name": "PSU0_IOUT", + "field_pos": "2", + "mult": "1000", + "separator": "," + }, + { + "attr_name": "psu_mfr_id", + "bmc_cmd": "_rv=$(ipmitool fru print 1 2>/dev/null | tr -s ' ' | cut -d' ' -f3-5 | grep 'Manufacturer') && echo $_rv || echo 'Manufacturer : N/A'", + "raw": "0", + "separator": ":", + "field_name": "Manufacturer", + "field_pos": "2" + }, + { + "attr_name": "psu_model_name", + "bmc_cmd": "_rv=$(ipmitool fru print 1 2>/dev/null | tr -s ' ' | cut -d' ' -f3-5 | grep 'Name') && echo $_rv || echo 'Name : N/A'", + "raw": "0", + "separator": ":", + "field_name": "Name", + "field_pos": "2" + }, + { + "attr_name": "psu_serial_num", + "bmc_cmd": "_rv=$(ipmitool fru print 1 2>/dev/null | tr -s ' ' | cut -d' ' -f3-5 | grep 'Serial') && echo $_rv || echo 'Serial : N/A'", + "raw": "0", + "separator": ":", + "field_name": "Serial", + "field_pos": "2" + }, + { + "attr_name": "psu_fan_dir", + "bmc_cmd": "ipmitool raw 0x3c 0x30 0x0 | xargs | cut -d' ' -f1", + "raw": "1", + "type": "raw" + } + ] + } + } + }, + "PSU1-EEPROM": { + "dev_info": { + "device_type": "PSU-EEPROM", + "device_name": "PSU1-EEPROM", + "device_parent": "MUX1", + "virt_parent": "PSU1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2", + "dev_addr": "0x50", + "dev_type": "psu_eeprom" + }, + "attr_list": [ + { + "attr_name":"psu_present", + "attr_devaddr":"0x30", + "attr_devtype":"cpld", + "attr_offset":"0x51", + "attr_mask":"0x1", + "attr_cmpval":"0x0", + "attr_len":"1" + }, + { + "attr_name":"psu_power_good", + "attr_devaddr":"0x30", + "attr_devtype":"cpld", + "attr_offset":"0x51", + "attr_mask":"0x10", + "attr_cmpval":"0x10", + "attr_len":"1" + } + ] + } + }, + "PSU2": { + "dev_info": { + "device_type": "PSU", + "device_name": "PSU2", + "device_parent": "MUX1" + }, + "dev_attr": { + "dev_idx": "2", + "num_psu_fans": "1" + }, + "i2c": { + "interface": [ + { "itf":"eeprom", "dev":"PSU2-EEPROM" } + ] + }, + "bmc": { + "ipmitool": { + "attr_list": [ + { + "attr_name": "psu_temp1_input", + "bmc_cmd": "ipmitool sdr -c get PSU1_TEMP1 | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "field_name": "PSU1_TEMP1", + "field_pos": "2", + "mult": "1000", + "separator": "," + }, + { + "attr_name": "psu_fan1_speed_rpm", + "bmc_cmd": "ipmitool sdr -c get PSU1_FAN1 | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "field_name": "PSU1_FAN1", + "field_pos": "2", + "separator": "," + }, + { + "attr_name": "psu_v_out", + "bmc_cmd": "ipmitool sdr -c get PSU1_VOUT | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "field_name": "PSU1_VOUT", + "field_pos": "2", + "mult": "1000", + "separator": "," + }, + { + "attr_name": "psu_i_out", + "bmc_cmd": "ipmitool sdr -c get PSU1_IOUT | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "field_name": "PSU1_IOUT", + "field_pos": "2", + "mult": "1000", + "separator": "," + }, + { + "attr_name": "psu_mfr_id", + "bmc_cmd": "_rv=$(ipmitool fru print 2 2>/dev/null | tr -s ' ' | cut -d' ' -f3-5 | grep 'Manufacturer') && echo $_rv || echo 'Manufacturer : N/A'", + "raw": "0", + "separator": ":", + "field_name": "Manufacturer", + "field_pos": "2" + }, + { + "attr_name": "psu_model_name", + "bmc_cmd": "_rv=$(ipmitool fru print 2 2>/dev/null | tr -s ' ' | cut -d' ' -f3-5 | grep 'Name') && echo $_rv || echo 'Name : N/A'", + "raw": "0", + "separator": ":", + "field_name": "Name", + "field_pos": "2" + }, + { + "attr_name": "psu_serial_num", + "bmc_cmd": "_rv=$(ipmitool fru print 2 2>/dev/null | tr -s ' ' | cut -d' ' -f3-5 | grep 'Serial') && echo $_rv || echo 'Serial : N/A'", + "raw": "0", + "separator": ":", + "field_name": "Serial", + "field_pos": "2" + }, + + { + "attr_name": "psu_fan_dir", + "bmc_cmd": "ipmitool raw 0x3c 0x30 0x0 | xargs | cut -d' ' -f2", + "raw": "1", + "type": "raw" + } + ] + } + } + }, + "PSU2-EEPROM": { + "dev_info": { + "device_type": "PSU-EEPROM", + "device_name": "PSU2-EEPROM", + "device_parent": "MUX1", + "virt_parent": "PSU2" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2", + "dev_addr": "0x51", + "dev_type": "psu_eeprom" + }, + "attr_list": [ + { + "attr_name":"psu_present", + "attr_devaddr":"0x30", + "attr_devtype":"cpld", + "attr_offset":"0x51", + "attr_mask":"0x2", + "attr_cmpval":"0x0", + "attr_len":"1" + }, + { + "attr_name":"psu_power_good", + "attr_devaddr":"0x30", + "attr_devtype":"cpld", + "attr_offset":"0x51", + "attr_mask":"0x20", + "attr_cmpval":"0x20", + "attr_len":"1" + } + ] + } + }, + "FAN-CTRL": { + "dev_info": { + "device_type": "FAN", + "device_name": "FAN-CTRL", + "device_parent": "" + }, + "bmc": { + "ipmitool": { + "attr_list": [ + { + "attr_name": "fan1_present", + "bmc_cmd": "ipmitool sdr -c get FAN0_PRSNT_L", + "raw": "0", + "field_name": "FAN0_PRSNT_L", + "field_pos": "5", + "separator": "," + }, + { + "attr_name": "fan2_present", + "bmc_cmd": "ipmitool sdr -c get FAN1_PRSNT_L", + "raw": "0", + "field_name": "FAN1_PRSNT_L", + "field_pos": "5", + "separator": "," + }, + { + "attr_name": "fan3_present", + "bmc_cmd": "ipmitool sdr -c get FAN2_PRSNT_L", + "raw": "0", + "field_name": "FAN2_PRSNT_L", + "field_pos": "5", + "separator": "," + }, + { + "attr_name": "fan4_present", + "bmc_cmd": "ipmitool sdr -c get FAN3_PRSNT_L", + "raw": "0", + "field_name": "FAN3_PRSNT_L", + "field_pos": "5", + "separator": "," + }, + { + "attr_name": "fan5_present", + "bmc_cmd": "ipmitool sdr -c get FAN4_PRSNT_L", + "raw": "0", + "field_name": "FAN4_PRSNT_L", + "field_pos": "5", + "separator": "," + }, + { + "attr_name": "fan1_input", + "bmc_cmd": "ipmitool sdr -c get FAN0_RPM | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "field_name": "FAN0_RPM", + "field_pos": "2", + "separator": "," + }, + { + "attr_name": "fan2_input", + "bmc_cmd": "ipmitool sdr -c get FAN1_RPM | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "field_name": "FAN1_RPM", + "field_pos": "2", + "separator": "," + }, + { + "attr_name": "fan3_input", + "bmc_cmd": "ipmitool sdr -c get FAN2_RPM | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "field_name": "FAN2_RPM", + "field_pos": "2", + "separator": "," + }, + { + "attr_name": "fan4_input", + "bmc_cmd": "ipmitool sdr -c get FAN3_RPM | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "field_name": "FAN3_RPM", + "field_pos": "2", + "separator": "," + }, + { + "attr_name": "fan5_input", + "bmc_cmd": "ipmitool sdr -c get FAN4_RPM | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "field_name": "FAN4_RPM", + "field_pos": "2", + "separator": "," + }, + { + "attr_name": "fan1_direction", + "bmc_cmd": "ipmitool raw 0x3c 0x31 0x0 | xargs | cut -d' ' -f1", + "raw": "1", + "type": "raw" + }, + { + "attr_name": "fan2_direction", + "bmc_cmd": "ipmitool raw 0x3c 0x31 0x0 | xargs | cut -d' ' -f2", + "raw": "1", + "type": "raw" + }, + { + "attr_name": "fan3_direction", + "bmc_cmd": "ipmitool raw 0x3c 0x31 0x0 | xargs | cut -d' ' -f3", + "raw": "1", + "type": "raw" + }, + { + "attr_name": "fan4_direction", + "bmc_cmd": "ipmitool raw 0x3c 0x31 0x0 | xargs | cut -d' ' -f4", + "raw": "1", + "type": "raw" + }, + { + "attr_name": "fan5_direction", + "bmc_cmd": "ipmitool raw 0x3c 0x31 0x0 | xargs | cut -d' ' -f5", + "raw": "1", + "type": "raw" + } + ] + } + } + }, + "SYNC_LED": { + "dev_info": { + "device_type": "LED", + "device_name": "DIAG_LED" + }, + "dev_attr": { + "index": "0", + "flag": "rw" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "green", + "bits": "3:0", + "descr": "Green", + "value": "0x09;0x0b", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x82" + }, + { + "attr_name": "green_blink", + "bits": "3:0", + "descr": "Green Blinking", + "value": "0x0d;0x0f", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x82" + }, + { + "attr_name": "yellow", + "bits": "3:0", + "descr": "Yellow", + "value": "0x08;0x0a", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x82" + }, + { + "attr_name": "yellow_blink", + "bits": "3:0", + "descr": "Yellow Blinking", + "value": "0x0c;0x0e", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x82" + }, + { + "attr_name": "off", + "bits": "3:2", + "descr": "Off", + "value": "0x1;0x0", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x82" + } + ] + } + }, + "SYS_LED": { + "dev_info": { + "device_type": "LED", + "device_name": "SYS_LED" + }, + "dev_attr": { + "index": "0", + "flag": "rw" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "green", + "bits": "7:4", + "descr": "Green", + "value": "0x09;0x0b", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x81" + }, + { + "attr_name": "green_blink", + "bits": "7:4", + "descr": "Green Blinking", + "value": "0x0d;0x0f", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x81" + }, + { + "attr_name": "yellow", + "bits": "7:4", + "descr": "Yellow", + "value": "0x08;0x0a", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x81" + }, + { + "attr_name": "yellow_blink", + "bits": "7:4", + "descr": "Yellow Blinking", + "value": "0x0c;0x0e", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x81" + }, + { + "attr_name": "off", + "bits": "7:6", + "descr": "Off", + "value": "0x01;0x0", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x81" + } + ] + } + }, + "FAN_LED": { + "dev_info": { + "device_type": "LED", + "device_name": "FAN_LED" + }, + "dev_attr": { + "index": "0", + "flag": "ro" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "green", + "bits": "3:0", + "descr": "Green", + "value": "0x09;0x0b", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x83" + }, + { + "attr_name": "green_blink", + "bits": "3:0", + "descr": "Green Blinking", + "value": "0x0d;0x0f", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x83" + }, + { + "attr_name": "yellow", + "bits": "3:0", + "descr": "Yellow", + "value": "0x08;0x0a", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x83" + }, + { + "attr_name": "yellow_blink", + "bits": "3:0", + "descr": "Yellow Blinking", + "value": "0x0c;0x0e", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x83" + }, + { + "attr_name": "off", + "bits": "3", + "descr": "Off", + "value": "0x0", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x83" + } + ] + } + }, + "PSU1_LED": { + "dev_info": { + "device_type": "LED", + "device_name": "PSU_LED" + }, + "dev_attr": { + "index": "0", + "flag": "ro" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "green", + "bits": "3:0", + "descr": "Green", + "value": "0x09;0x0b", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x80" + }, + { + "attr_name": "green_blink", + "bits": "3:0", + "descr": "Green Blinking", + "value": "0x0d;0x0f", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x80" + }, + { + "attr_name": "yellow", + "bits": "3:0", + "descr": "Yellow", + "value": "0x08;0x0a", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x80" + }, + { + "attr_name": "yellow_blink", + "bits": "3:0", + "descr": "Yellow Blinking", + "value": "0x0c;0x0e", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x80" + }, + { + "attr_name": "off", + "bits": "3", + "descr": "Off", + "value": "0x0", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x80" + } + ] + } + }, + "PSU2_LED": { + "dev_info": { + "device_type": "LED", + "device_name": "PSU_LED" + }, + "dev_attr": { + "index": "1", + "flag": "ro" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "green", + "bits": "7:4", + "descr": "Green", + "value": "0x09;0x0b", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x80" + }, + { + "attr_name": "green_blink", + "bits": "7:4", + "descr": "Green Blinking", + "value": "0x0d;0x0f", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x80" + }, + { + "attr_name": "yellow", + "bits": "7:4", + "descr": "Yellow", + "value": "0x08;0x0a", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x80" + }, + { + "attr_name": "yellow_blink", + "bits": "7:4", + "descr": "Yellow Blinking", + "value": "0x0c;0x0e", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x80" + }, + { + "attr_name": "off", + "bits": "7", + "descr": "Off", + "value": "0x0", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x80" + } + ] + } + }, + "ID_LED": { + "dev_info": { + "device_type": "LED", + "device_name": "LOC_LED" + }, + "dev_attr": { + "index": "0", + "flag": "rw" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "blue", + "bits": "3:1", + "descr": "Blue", + "value": "0x04;0x05", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x84" + }, + { + "attr_name": "blue_blink", + "bits": "3:1", + "descr": "Blue Blinking", + "value": "0x06;0x07", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x84" + }, + { + "attr_name": "off", + "bits": "3:2", + "descr": "Off", + "value": "0x01;0x0", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x84" + } + ] + } + }, + "PORT1": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT1", + "device_parent": "MUX4" + }, + "dev_attr": { + "dev_idx": "1" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT1-EEPROM" + }, + { + "itf": "control", + "dev": "PORT1-CTRL" + } + ] + } + }, + "PORT1-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT1-EEPROM", + "device_parent": "MUX4", + "virt_parent": "PORT1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1a", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT1-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT1-CTRL", + "device_parent": "MUX4", + "virt_parent": "PORT1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1a", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x10", + "attr_mask": "0x0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x40", + "attr_mask": "0x0", + "attr_cmpval": "0x1", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x46", + "attr_mask": "0x0", + "attr_cmpval": "0x1", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x70", + "attr_mask": "0x0", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT2": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT2", + "device_parent": "MUX4" + }, + "dev_attr": { + "dev_idx": "2" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT2-EEPROM" + }, + { + "itf": "control", + "dev": "PORT2-CTRL" + } + ] + } + }, + "PORT2-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT2-EEPROM", + "device_parent": "MUX4", + "virt_parent": "PORT2" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1b", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT2-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT2-CTRL", + "device_parent": "MUX4", + "virt_parent": "PORT2" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1b", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x10", + "attr_mask": "0x1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x40", + "attr_mask": "0x1", + "attr_cmpval": "0x2", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x46", + "attr_mask": "0x1", + "attr_cmpval": "0x2", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x70", + "attr_mask": "0x1", + "attr_cmpval": "0x2", + "attr_len": "1" + } + ] + } + }, + "PORT3": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT3", + "device_parent": "MUX4" + }, + "dev_attr": { + "dev_idx": "3" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT3-EEPROM" + }, + { + "itf": "control", + "dev": "PORT3-CTRL" + } + ] + } + }, + "PORT3-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT3-EEPROM", + "device_parent": "MUX4", + "virt_parent": "PORT3" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1c", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT3-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT3-CTRL", + "device_parent": "MUX4", + "virt_parent": "PORT3" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1c", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x10", + "attr_mask": "0x2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x40", + "attr_mask": "0x2", + "attr_cmpval": "0x4", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x46", + "attr_mask": "0x2", + "attr_cmpval": "0x4", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x70", + "attr_mask": "0x2", + "attr_cmpval": "0x4", + "attr_len": "1" + } + ] + } + }, + "PORT4": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT4", + "device_parent": "MUX4" + }, + "dev_attr": { + "dev_idx": "4" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT4-EEPROM" + }, + { + "itf": "control", + "dev": "PORT4-CTRL" + } + ] + } + }, + "PORT4-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT4-EEPROM", + "device_parent": "MUX4", + "virt_parent": "PORT4" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1d", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT4-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT4-CTRL", + "device_parent": "MUX4", + "virt_parent": "PORT4" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1d", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x10", + "attr_mask": "0x3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x40", + "attr_mask": "0x3", + "attr_cmpval": "0x8", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x46", + "attr_mask": "0x3", + "attr_cmpval": "0x8", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x70", + "attr_mask": "0x3", + "attr_cmpval": "0x8", + "attr_len": "1" + } + ] + } + }, + "PORT5": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT5", + "device_parent": "MUX4" + }, + "dev_attr": { + "dev_idx": "5" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT5-EEPROM" + }, + { + "itf": "control", + "dev": "PORT5-CTRL" + } + ] + } + }, + "PORT5-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT5-EEPROM", + "device_parent": "MUX4", + "virt_parent": "PORT5" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1e", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT5-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT5-CTRL", + "device_parent": "MUX4", + "virt_parent": "PORT5" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1e", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x10", + "attr_mask": "0x4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x40", + "attr_mask": "0x4", + "attr_cmpval": "0x10", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x46", + "attr_mask": "0x4", + "attr_cmpval": "0x10", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x70", + "attr_mask": "0x4", + "attr_cmpval": "0x10", + "attr_len": "1" + } + ] + } + }, + "PORT6": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT6", + "device_parent": "MUX4" + }, + "dev_attr": { + "dev_idx": "6" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT6-EEPROM" + }, + { + "itf": "control", + "dev": "PORT6-CTRL" + } + ] + } + }, + "PORT6-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT6-EEPROM", + "device_parent": "MUX4", + "virt_parent": "PORT6" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1f", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT6-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT6-CTRL", + "device_parent": "MUX4", + "virt_parent": "PORT6" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1f", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x10", + "attr_mask": "0x5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x40", + "attr_mask": "0x5", + "attr_cmpval": "0x20", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x46", + "attr_mask": "0x5", + "attr_cmpval": "0x20", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x70", + "attr_mask": "0x5", + "attr_cmpval": "0x20", + "attr_len": "1" + } + ] + } + }, + "PORT7": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT7", + "device_parent": "MUX4" + }, + "dev_attr": { + "dev_idx": "7" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT7-EEPROM" + }, + { + "itf": "control", + "dev": "PORT7-CTRL" + } + ] + } + }, + "PORT7-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT7-EEPROM", + "device_parent": "MUX4", + "virt_parent": "PORT7" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x20", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT7-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT7-CTRL", + "device_parent": "MUX4", + "virt_parent": "PORT7" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x20", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x10", + "attr_mask": "0x6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x40", + "attr_mask": "0x6", + "attr_cmpval": "0x40", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x46", + "attr_mask": "0x6", + "attr_cmpval": "0x40", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x70", + "attr_mask": "0x6", + "attr_cmpval": "0x40", + "attr_len": "1" + } + ] + } + }, + "PORT8": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT8", + "device_parent": "MUX4" + }, + "dev_attr": { + "dev_idx": "8" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT8-EEPROM" + }, + { + "itf": "control", + "dev": "PORT8-CTRL" + } + ] + } + }, + "PORT8-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT8-EEPROM", + "device_parent": "MUX4", + "virt_parent": "PORT8" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x21", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT8-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT8-CTRL", + "device_parent": "MUX4", + "virt_parent": "PORT8" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x21", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x10", + "attr_mask": "0x7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x40", + "attr_mask": "0x7", + "attr_cmpval": "0x80", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x46", + "attr_mask": "0x7", + "attr_cmpval": "0x80", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x70", + "attr_mask": "0x7", + "attr_cmpval": "0x80", + "attr_len": "1" + } + ] + } + }, + "PORT9": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT9", + "device_parent": "MUX5" + }, + "dev_attr": { + "dev_idx": "9" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT9-EEPROM" + }, + { + "itf": "control", + "dev": "PORT9-CTRL" + } + ] + } + }, + "PORT9-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT9-EEPROM", + "device_parent": "MUX5", + "virt_parent": "PORT9" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x22", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT9-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT9-CTRL", + "device_parent": "MUX5", + "virt_parent": "PORT9" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x22", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x11", + "attr_mask": "0x0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x41", + "attr_mask": "0x0", + "attr_cmpval": "0x1", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x47", + "attr_mask": "0x0", + "attr_cmpval": "0x1", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x71", + "attr_mask": "0x0", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT10": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT10", + "device_parent": "MUX5" + }, + "dev_attr": { + "dev_idx": "10" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT10-EEPROM" + }, + { + "itf": "control", + "dev": "PORT10-CTRL" + } + ] + } + }, + "PORT10-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT10-EEPROM", + "device_parent": "MUX5", + "virt_parent": "PORT10" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x23", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT10-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT10-CTRL", + "device_parent": "MUX5", + "virt_parent": "PORT10" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x23", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x11", + "attr_mask": "0x1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x41", + "attr_mask": "0x1", + "attr_cmpval": "0x2", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x47", + "attr_mask": "0x1", + "attr_cmpval": "0x2", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x71", + "attr_mask": "0x1", + "attr_cmpval": "0x2", + "attr_len": "1" + } + ] + } + }, + "PORT11": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT11", + "device_parent": "MUX5" + }, + "dev_attr": { + "dev_idx": "11" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT11-EEPROM" + }, + { + "itf": "control", + "dev": "PORT11-CTRL" + } + ] + } + }, + "PORT11-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT11-EEPROM", + "device_parent": "MUX5", + "virt_parent": "PORT11" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x24", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT11-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT11-CTRL", + "device_parent": "MUX5", + "virt_parent": "PORT11" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x24", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x11", + "attr_mask": "0x2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x41", + "attr_mask": "0x2", + "attr_cmpval": "0x4", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x47", + "attr_mask": "0x2", + "attr_cmpval": "0x4", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x71", + "attr_mask": "0x2", + "attr_cmpval": "0x4", + "attr_len": "1" + } + ] + } + }, + "PORT12": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT12", + "device_parent": "MUX5" + }, + "dev_attr": { + "dev_idx": "12" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT12-EEPROM" + }, + { + "itf": "control", + "dev": "PORT12-CTRL" + } + ] + } + }, + "PORT12-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT12-EEPROM", + "device_parent": "MUX5", + "virt_parent": "PORT12" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x25", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT12-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT12-CTRL", + "device_parent": "MUX5", + "virt_parent": "PORT12" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x25", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x11", + "attr_mask": "0x3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x41", + "attr_mask": "0x3", + "attr_cmpval": "0x8", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x47", + "attr_mask": "0x3", + "attr_cmpval": "0x8", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x71", + "attr_mask": "0x3", + "attr_cmpval": "0x8", + "attr_len": "1" + } + ] + } + }, + "PORT13": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT13", + "device_parent": "MUX5" + }, + "dev_attr": { + "dev_idx": "13" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT13-EEPROM" + }, + { + "itf": "control", + "dev": "PORT13-CTRL" + } + ] + } + }, + "PORT13-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT13-EEPROM", + "device_parent": "MUX5", + "virt_parent": "PORT13" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x26", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT13-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT13-CTRL", + "device_parent": "MUX5", + "virt_parent": "PORT13" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x26", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x11", + "attr_mask": "0x4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x41", + "attr_mask": "0x4", + "attr_cmpval": "0x10", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x47", + "attr_mask": "0x4", + "attr_cmpval": "0x10", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x71", + "attr_mask": "0x4", + "attr_cmpval": "0x10", + "attr_len": "1" + } + ] + } + }, + "PORT14": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT14", + "device_parent": "MUX5" + }, + "dev_attr": { + "dev_idx": "14" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT14-EEPROM" + }, + { + "itf": "control", + "dev": "PORT14-CTRL" + } + ] + } + }, + "PORT14-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT14-EEPROM", + "device_parent": "MUX5", + "virt_parent": "PORT14" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x27", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT14-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT14-CTRL", + "device_parent": "MUX5", + "virt_parent": "PORT14" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x27", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x11", + "attr_mask": "0x5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x41", + "attr_mask": "0x5", + "attr_cmpval": "0x20", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x47", + "attr_mask": "0x5", + "attr_cmpval": "0x20", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x71", + "attr_mask": "0x5", + "attr_cmpval": "0x20", + "attr_len": "1" + } + ] + } + }, + "PORT15": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT15", + "device_parent": "MUX5" + }, + "dev_attr": { + "dev_idx": "15" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT15-EEPROM" + }, + { + "itf": "control", + "dev": "PORT15-CTRL" + } + ] + } + }, + "PORT15-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT15-EEPROM", + "device_parent": "MUX5", + "virt_parent": "PORT15" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x28", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT15-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT15-CTRL", + "device_parent": "MUX5", + "virt_parent": "PORT15" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x28", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x11", + "attr_mask": "0x6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x41", + "attr_mask": "0x6", + "attr_cmpval": "0x40", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x47", + "attr_mask": "0x6", + "attr_cmpval": "0x40", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x71", + "attr_mask": "0x6", + "attr_cmpval": "0x40", + "attr_len": "1" + } + ] + } + }, + "PORT16": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT16", + "device_parent": "MUX5" + }, + "dev_attr": { + "dev_idx": "16" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT16-EEPROM" + }, + { + "itf": "control", + "dev": "PORT16-CTRL" + } + ] + } + }, + "PORT16-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT16-EEPROM", + "device_parent": "MUX5", + "virt_parent": "PORT16" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x29", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT16-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT16-CTRL", + "device_parent": "MUX5", + "virt_parent": "PORT16" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x29", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x11", + "attr_mask": "0x7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x41", + "attr_mask": "0x7", + "attr_cmpval": "0x80", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x47", + "attr_mask": "0x7", + "attr_cmpval": "0x80", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x71", + "attr_mask": "0x7", + "attr_cmpval": "0x80", + "attr_len": "1" + } + ] + } + }, + "PORT17": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT17", + "device_parent": "MUX6" + }, + "dev_attr": { + "dev_idx": "17" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT17-EEPROM" + }, + { + "itf": "control", + "dev": "PORT17-CTRL" + } + ] + } + }, + "PORT17-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT17-EEPROM", + "device_parent": "MUX6", + "virt_parent": "PORT17" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2a", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT17-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT17-CTRL", + "device_parent": "MUX6", + "virt_parent": "PORT17" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2a", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x12", + "attr_mask": "0x0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x42", + "attr_mask": "0x0", + "attr_cmpval": "0x1", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x48", + "attr_mask": "0x0", + "attr_cmpval": "0x1", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x72", + "attr_mask": "0x0", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT18": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT18", + "device_parent": "MUX6" + }, + "dev_attr": { + "dev_idx": "18" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT18-EEPROM" + }, + { + "itf": "control", + "dev": "PORT18-CTRL" + } + ] + } + }, + "PORT18-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT18-EEPROM", + "device_parent": "MUX6", + "virt_parent": "PORT18" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2b", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT18-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT18-CTRL", + "device_parent": "MUX6", + "virt_parent": "PORT18" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2b", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x12", + "attr_mask": "0x1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x42", + "attr_mask": "0x1", + "attr_cmpval": "0x2", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x48", + "attr_mask": "0x1", + "attr_cmpval": "0x2", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x72", + "attr_mask": "0x1", + "attr_cmpval": "0x2", + "attr_len": "1" + } + ] + } + }, + "PORT19": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT19", + "device_parent": "MUX6" + }, + "dev_attr": { + "dev_idx": "19" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT19-EEPROM" + }, + { + "itf": "control", + "dev": "PORT19-CTRL" + } + ] + } + }, + "PORT19-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT19-EEPROM", + "device_parent": "MUX6", + "virt_parent": "PORT19" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2c", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT19-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT19-CTRL", + "device_parent": "MUX6", + "virt_parent": "PORT19" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2c", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x12", + "attr_mask": "0x2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x42", + "attr_mask": "0x2", + "attr_cmpval": "0x4", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x48", + "attr_mask": "0x2", + "attr_cmpval": "0x4", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x72", + "attr_mask": "0x2", + "attr_cmpval": "0x4", + "attr_len": "1" + } + ] + } + }, + "PORT20": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT20", + "device_parent": "MUX6" + }, + "dev_attr": { + "dev_idx": "20" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT20-EEPROM" + }, + { + "itf": "control", + "dev": "PORT20-CTRL" + } + ] + } + }, + "PORT20-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT20-EEPROM", + "device_parent": "MUX6", + "virt_parent": "PORT20" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2d", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT20-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT20-CTRL", + "device_parent": "MUX6", + "virt_parent": "PORT20" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2d", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x12", + "attr_mask": "0x3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x42", + "attr_mask": "0x3", + "attr_cmpval": "0x8", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x48", + "attr_mask": "0x3", + "attr_cmpval": "0x8", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x72", + "attr_mask": "0x3", + "attr_cmpval": "0x8", + "attr_len": "1" + } + ] + } + }, + "PORT21": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT21", + "device_parent": "MUX6" + }, + "dev_attr": { + "dev_idx": "21" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT21-EEPROM" + }, + { + "itf": "control", + "dev": "PORT21-CTRL" + } + ] + } + }, + "PORT21-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT21-EEPROM", + "device_parent": "MUX6", + "virt_parent": "PORT21" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2e", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT21-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT21-CTRL", + "device_parent": "MUX6", + "virt_parent": "PORT21" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2e", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x12", + "attr_mask": "0x4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x42", + "attr_mask": "0x4", + "attr_cmpval": "0x10", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x48", + "attr_mask": "0x4", + "attr_cmpval": "0x10", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x72", + "attr_mask": "0x4", + "attr_cmpval": "0x10", + "attr_len": "1" + } + ] + } + }, + "PORT22": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT22", + "device_parent": "MUX6" + }, + "dev_attr": { + "dev_idx": "22" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT22-EEPROM" + }, + { + "itf": "control", + "dev": "PORT22-CTRL" + } + ] + } + }, + "PORT22-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT22-EEPROM", + "device_parent": "MUX6", + "virt_parent": "PORT22" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2f", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT22-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT22-CTRL", + "device_parent": "MUX6", + "virt_parent": "PORT22" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2f", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x12", + "attr_mask": "0x5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x42", + "attr_mask": "0x5", + "attr_cmpval": "0x20", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x48", + "attr_mask": "0x5", + "attr_cmpval": "0x20", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x72", + "attr_mask": "0x5", + "attr_cmpval": "0x20", + "attr_len": "1" + } + ] + } + }, + "PORT23": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT23", + "device_parent": "MUX6" + }, + "dev_attr": { + "dev_idx": "23" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT23-EEPROM" + }, + { + "itf": "control", + "dev": "PORT23-CTRL" + } + ] + } + }, + "PORT23-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT23-EEPROM", + "device_parent": "MUX6", + "virt_parent": "PORT23" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x30", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT23-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT23-CTRL", + "device_parent": "MUX6", + "virt_parent": "PORT23" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x30", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x12", + "attr_mask": "0x6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x42", + "attr_mask": "0x6", + "attr_cmpval": "0x40", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x48", + "attr_mask": "0x6", + "attr_cmpval": "0x40", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x72", + "attr_mask": "0x6", + "attr_cmpval": "0x40", + "attr_len": "1" + } + ] + } + }, + "PORT24": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT24", + "device_parent": "MUX6" + }, + "dev_attr": { + "dev_idx": "24" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT24-EEPROM" + }, + { + "itf": "control", + "dev": "PORT24-CTRL" + } + ] + } + }, + "PORT24-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT24-EEPROM", + "device_parent": "MUX6", + "virt_parent": "PORT24" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x31", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT24-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT24-CTRL", + "device_parent": "MUX6", + "virt_parent": "PORT24" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x31", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x12", + "attr_mask": "0x7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x42", + "attr_mask": "0x7", + "attr_cmpval": "0x80", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x48", + "attr_mask": "0x7", + "attr_cmpval": "0x80", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x72", + "attr_mask": "0x7", + "attr_cmpval": "0x80", + "attr_len": "1" + } + ] + } + }, + "PORT25": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT25", + "device_parent": "MUX7" + }, + "dev_attr": { + "dev_idx": "25" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT25-EEPROM" + }, + { + "itf": "control", + "dev": "PORT25-CTRL" + } + ] + } + }, + "PORT25-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT25-EEPROM", + "device_parent": "MUX7", + "virt_parent": "PORT25" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x32", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT25-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT25-CTRL", + "device_parent": "MUX7", + "virt_parent": "PORT25" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x32", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x13", + "attr_mask": "0x0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x43", + "attr_mask": "0x0", + "attr_cmpval": "0x1", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x49", + "attr_mask": "0x0", + "attr_cmpval": "0x1", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x73", + "attr_mask": "0x0", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT26": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT26", + "device_parent": "MUX7" + }, + "dev_attr": { + "dev_idx": "26" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT26-EEPROM" + }, + { + "itf": "control", + "dev": "PORT26-CTRL" + } + ] + } + }, + "PORT26-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT26-EEPROM", + "device_parent": "MUX7", + "virt_parent": "PORT26" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x33", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT26-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT26-CTRL", + "device_parent": "MUX7", + "virt_parent": "PORT26" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x33", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x13", + "attr_mask": "0x1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x43", + "attr_mask": "0x1", + "attr_cmpval": "0x2", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x49", + "attr_mask": "0x1", + "attr_cmpval": "0x2", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x73", + "attr_mask": "0x1", + "attr_cmpval": "0x2", + "attr_len": "1" + } + ] + } + }, + "PORT27": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT27", + "device_parent": "MUX7" + }, + "dev_attr": { + "dev_idx": "27" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT27-EEPROM" + }, + { + "itf": "control", + "dev": "PORT27-CTRL" + } + ] + } + }, + "PORT27-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT27-EEPROM", + "device_parent": "MUX7", + "virt_parent": "PORT27" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x34", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT27-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT27-CTRL", + "device_parent": "MUX7", + "virt_parent": "PORT27" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x34", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x13", + "attr_mask": "0x2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x43", + "attr_mask": "0x2", + "attr_cmpval": "0x4", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x49", + "attr_mask": "0x2", + "attr_cmpval": "0x4", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x73", + "attr_mask": "0x2", + "attr_cmpval": "0x4", + "attr_len": "1" + } + ] + } + }, + "PORT28": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT28", + "device_parent": "MUX7" + }, + "dev_attr": { + "dev_idx": "28" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT28-EEPROM" + }, + { + "itf": "control", + "dev": "PORT28-CTRL" + } + ] + } + }, + "PORT28-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT28-EEPROM", + "device_parent": "MUX7", + "virt_parent": "PORT28" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x35", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT28-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT28-CTRL", + "device_parent": "MUX7", + "virt_parent": "PORT28" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x35", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x13", + "attr_mask": "0x3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x43", + "attr_mask": "0x3", + "attr_cmpval": "0x8", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x49", + "attr_mask": "0x3", + "attr_cmpval": "0x8", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x73", + "attr_mask": "0x3", + "attr_cmpval": "0x8", + "attr_len": "1" + } + ] + } + }, + "PORT29": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT29", + "device_parent": "MUX7" + }, + "dev_attr": { + "dev_idx": "29" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT29-EEPROM" + }, + { + "itf": "control", + "dev": "PORT29-CTRL" + } + ] + } + }, + "PORT29-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT29-EEPROM", + "device_parent": "MUX7", + "virt_parent": "PORT29" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x36", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT29-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT29-CTRL", + "device_parent": "MUX7", + "virt_parent": "PORT29" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x36", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x13", + "attr_mask": "0x4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x43", + "attr_mask": "0x4", + "attr_cmpval": "0x10", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x49", + "attr_mask": "0x4", + "attr_cmpval": "0x10", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x73", + "attr_mask": "0x4", + "attr_cmpval": "0x10", + "attr_len": "1" + } + ] + } + }, + "PORT30": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT30", + "device_parent": "MUX7" + }, + "dev_attr": { + "dev_idx": "30" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT30-EEPROM" + }, + { + "itf": "control", + "dev": "PORT30-CTRL" + } + ] + } + }, + "PORT30-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT30-EEPROM", + "device_parent": "MUX7", + "virt_parent": "PORT30" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x37", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT30-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT30-CTRL", + "device_parent": "MUX7", + "virt_parent": "PORT30" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x37", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x13", + "attr_mask": "0x5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x43", + "attr_mask": "0x5", + "attr_cmpval": "0x20", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x49", + "attr_mask": "0x5", + "attr_cmpval": "0x20", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x73", + "attr_mask": "0x5", + "attr_cmpval": "0x20", + "attr_len": "1" + } + ] + } + }, + "PORT31": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT31", + "device_parent": "MUX7" + }, + "dev_attr": { + "dev_idx": "31" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT31-EEPROM" + }, + { + "itf": "control", + "dev": "PORT31-CTRL" + } + ] + } + }, + "PORT31-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT31-EEPROM", + "device_parent": "MUX7", + "virt_parent": "PORT31" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x38", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT31-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT31-CTRL", + "device_parent": "MUX7", + "virt_parent": "PORT31" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x38", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x13", + "attr_mask": "0x6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x43", + "attr_mask": "0x6", + "attr_cmpval": "0x40", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x49", + "attr_mask": "0x6", + "attr_cmpval": "0x40", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x73", + "attr_mask": "0x6", + "attr_cmpval": "0x40", + "attr_len": "1" + } + ] + } + }, + "PORT32": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT32", + "device_parent": "MUX7" + }, + "dev_attr": { + "dev_idx": "32" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT32-EEPROM" + }, + { + "itf": "control", + "dev": "PORT32-CTRL" + } + ] + } + }, + "PORT32-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT32-EEPROM", + "device_parent": "MUX7", + "virt_parent": "PORT32" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x39", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT32-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT32-CTRL", + "device_parent": "MUX7", + "virt_parent": "PORT32" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x39", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x13", + "attr_mask": "0x7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x43", + "attr_mask": "0x7", + "attr_cmpval": "0x80", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x49", + "attr_mask": "0x7", + "attr_cmpval": "0x80", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x73", + "attr_mask": "0x7", + "attr_cmpval": "0x80", + "attr_len": "1" + } + ] + } + }, + "PORT33": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT33", + "device_parent": "MUX8" + }, + "dev_attr": { + "dev_idx": "33" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT33-EEPROM" + }, + { + "itf": "control", + "dev": "PORT33-CTRL" + } + ] + } + }, + "PORT33-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT33-EEPROM", + "device_parent": "MUX8", + "virt_parent": "PORT33" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x3a", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT33-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT33-CTRL", + "device_parent": "MUX8", + "virt_parent": "PORT33" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x3a", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x14", + "attr_mask": "0x0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x44", + "attr_mask": "0x0", + "attr_cmpval": "0x1", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x4a", + "attr_mask": "0x0", + "attr_cmpval": "0x1", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x74", + "attr_mask": "0x0", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT34": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT34", + "device_parent": "MUX8" + }, + "dev_attr": { + "dev_idx": "34" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT34-EEPROM" + }, + { + "itf": "control", + "dev": "PORT34-CTRL" + } + ] + } + }, + "PORT34-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT34-EEPROM", + "device_parent": "MUX8", + "virt_parent": "PORT34" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x3b", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT34-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT34-CTRL", + "device_parent": "MUX8", + "virt_parent": "PORT34" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x3b", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x14", + "attr_mask": "0x1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x44", + "attr_mask": "0x1", + "attr_cmpval": "0x2", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x4a", + "attr_mask": "0x1", + "attr_cmpval": "0x2", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x74", + "attr_mask": "0x1", + "attr_cmpval": "0x2", + "attr_len": "1" + } + ] + } + }, + "PORT35": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT35", + "device_parent": "MUX8" + }, + "dev_attr": { + "dev_idx": "35" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT35-EEPROM" + }, + { + "itf": "control", + "dev": "PORT35-CTRL" + } + ] + } + }, + "PORT35-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT35-EEPROM", + "device_parent": "MUX8", + "virt_parent": "PORT35" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x3c", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT35-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT35-CTRL", + "device_parent": "MUX8", + "virt_parent": "PORT35" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x3c", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x14", + "attr_mask": "0x2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x44", + "attr_mask": "0x2", + "attr_cmpval": "0x4", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x4a", + "attr_mask": "0x2", + "attr_cmpval": "0x4", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x74", + "attr_mask": "0x2", + "attr_cmpval": "0x4", + "attr_len": "1" + } + ] + } + }, + "PORT36": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT36", + "device_parent": "MUX8" + }, + "dev_attr": { + "dev_idx": "36" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT36-EEPROM" + }, + { + "itf": "control", + "dev": "PORT36-CTRL" + } + ] + } + }, + "PORT36-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT36-EEPROM", + "device_parent": "MUX8", + "virt_parent": "PORT36" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x3d", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT36-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT36-CTRL", + "device_parent": "MUX8", + "virt_parent": "PORT36" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x3d", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x14", + "attr_mask": "0x3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x44", + "attr_mask": "0x3", + "attr_cmpval": "0x8", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x4a", + "attr_mask": "0x3", + "attr_cmpval": "0x8", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x74", + "attr_mask": "0x3", + "attr_cmpval": "0x8", + "attr_len": "1" + } + ] + } + }, + "PORT37": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT37", + "device_parent": "MUX8" + }, + "dev_attr": { + "dev_idx": "37" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT37-EEPROM" + }, + { + "itf": "control", + "dev": "PORT37-CTRL" + } + ] + } + }, + "PORT37-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT37-EEPROM", + "device_parent": "MUX8", + "virt_parent": "PORT37" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x3e", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT37-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT37-CTRL", + "device_parent": "MUX8", + "virt_parent": "PORT37" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x3e", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x14", + "attr_mask": "0x4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x44", + "attr_mask": "0x4", + "attr_cmpval": "0x10", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x4a", + "attr_mask": "0x4", + "attr_cmpval": "0x10", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x74", + "attr_mask": "0x4", + "attr_cmpval": "0x10", + "attr_len": "1" + } + ] + } + }, + "PORT38": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT38", + "device_parent": "MUX8" + }, + "dev_attr": { + "dev_idx": "38" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT38-EEPROM" + }, + { + "itf": "control", + "dev": "PORT38-CTRL" + } + ] + } + }, + "PORT38-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT38-EEPROM", + "device_parent": "MUX8", + "virt_parent": "PORT38" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x3f", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT38-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT38-CTRL", + "device_parent": "MUX8", + "virt_parent": "PORT38" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x3f", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x14", + "attr_mask": "0x5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x44", + "attr_mask": "0x5", + "attr_cmpval": "0x20", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x4a", + "attr_mask": "0x5", + "attr_cmpval": "0x20", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x74", + "attr_mask": "0x5", + "attr_cmpval": "0x20", + "attr_len": "1" + } + ] + } + }, + "PORT39": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT39", + "device_parent": "MUX8" + }, + "dev_attr": { + "dev_idx": "39" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT39-EEPROM" + }, + { + "itf": "control", + "dev": "PORT39-CTRL" + } + ] + } + }, + "PORT39-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT39-EEPROM", + "device_parent": "MUX8", + "virt_parent": "PORT39" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x40", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT39-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT39-CTRL", + "device_parent": "MUX8", + "virt_parent": "PORT39" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x40", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x14", + "attr_mask": "0x6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x44", + "attr_mask": "0x6", + "attr_cmpval": "0x40", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x4a", + "attr_mask": "0x6", + "attr_cmpval": "0x40", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x74", + "attr_mask": "0x6", + "attr_cmpval": "0x40", + "attr_len": "1" + } + ] + } + }, + "PORT40": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT40", + "device_parent": "MUX8" + }, + "dev_attr": { + "dev_idx": "40" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT40-EEPROM" + }, + { + "itf": "control", + "dev": "PORT40-CTRL" + } + ] + } + }, + "PORT40-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT40-EEPROM", + "device_parent": "MUX8", + "virt_parent": "PORT40" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x41", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT40-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT40-CTRL", + "device_parent": "MUX8", + "virt_parent": "PORT40" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x41", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x14", + "attr_mask": "0x7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x44", + "attr_mask": "0x7", + "attr_cmpval": "0x80", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x4a", + "attr_mask": "0x7", + "attr_cmpval": "0x80", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x74", + "attr_mask": "0x7", + "attr_cmpval": "0x80", + "attr_len": "1" + } + ] + } + }, + "PORT41": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT41", + "device_parent": "MUX9" + }, + "dev_attr": { + "dev_idx": "41" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT41-EEPROM" + }, + { + "itf": "control", + "dev": "PORT41-CTRL" + } + ] + } + }, + "PORT41-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT41-EEPROM", + "device_parent": "MUX9", + "virt_parent": "PORT41" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x42", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT41-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT41-CTRL", + "device_parent": "MUX9", + "virt_parent": "PORT41" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x42", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x15", + "attr_mask": "0x0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x45", + "attr_mask": "0x0", + "attr_cmpval": "0x1", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x4b", + "attr_mask": "0x0", + "attr_cmpval": "0x1", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x75", + "attr_mask": "0x0", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT42": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT42", + "device_parent": "MUX9" + }, + "dev_attr": { + "dev_idx": "42" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT42-EEPROM" + }, + { + "itf": "control", + "dev": "PORT42-CTRL" + } + ] + } + }, + "PORT42-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT42-EEPROM", + "device_parent": "MUX9", + "virt_parent": "PORT42" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x43", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT42-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT42-CTRL", + "device_parent": "MUX9", + "virt_parent": "PORT42" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x43", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x15", + "attr_mask": "0x1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x45", + "attr_mask": "0x1", + "attr_cmpval": "0x2", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x4b", + "attr_mask": "0x1", + "attr_cmpval": "0x2", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x75", + "attr_mask": "0x1", + "attr_cmpval": "0x2", + "attr_len": "1" + } + ] + } + }, + "PORT43": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT43", + "device_parent": "MUX9" + }, + "dev_attr": { + "dev_idx": "43" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT43-EEPROM" + }, + { + "itf": "control", + "dev": "PORT43-CTRL" + } + ] + } + }, + "PORT43-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT43-EEPROM", + "device_parent": "MUX9", + "virt_parent": "PORT43" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x44", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT43-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT43-CTRL", + "device_parent": "MUX9", + "virt_parent": "PORT43" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x44", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x15", + "attr_mask": "0x2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x45", + "attr_mask": "0x2", + "attr_cmpval": "0x4", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x4b", + "attr_mask": "0x2", + "attr_cmpval": "0x4", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x75", + "attr_mask": "0x2", + "attr_cmpval": "0x4", + "attr_len": "1" + } + ] + } + }, + "PORT44": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT44", + "device_parent": "MUX9" + }, + "dev_attr": { + "dev_idx": "44" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT44-EEPROM" + }, + { + "itf": "control", + "dev": "PORT44-CTRL" + } + ] + } + }, + "PORT44-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT44-EEPROM", + "device_parent": "MUX9", + "virt_parent": "PORT44" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x45", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT44-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT44-CTRL", + "device_parent": "MUX9", + "virt_parent": "PORT44" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x45", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x15", + "attr_mask": "0x3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x45", + "attr_mask": "0x3", + "attr_cmpval": "0x8", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x4b", + "attr_mask": "0x3", + "attr_cmpval": "0x8", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x75", + "attr_mask": "0x3", + "attr_cmpval": "0x8", + "attr_len": "1" + } + ] + } + }, + "PORT45": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT45", + "device_parent": "MUX9" + }, + "dev_attr": { + "dev_idx": "45" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT45-EEPROM" + }, + { + "itf": "control", + "dev": "PORT45-CTRL" + } + ] + } + }, + "PORT45-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT45-EEPROM", + "device_parent": "MUX9", + "virt_parent": "PORT45" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x46", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT45-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT45-CTRL", + "device_parent": "MUX9", + "virt_parent": "PORT45" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x46", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x15", + "attr_mask": "0x4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x45", + "attr_mask": "0x4", + "attr_cmpval": "0x10", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x4b", + "attr_mask": "0x4", + "attr_cmpval": "0x10", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x75", + "attr_mask": "0x4", + "attr_cmpval": "0x10", + "attr_len": "1" + } + ] + } + }, + "PORT46": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT46", + "device_parent": "MUX9" + }, + "dev_attr": { + "dev_idx": "46" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT46-EEPROM" + }, + { + "itf": "control", + "dev": "PORT46-CTRL" + } + ] + } + }, + "PORT46-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT46-EEPROM", + "device_parent": "MUX9", + "virt_parent": "PORT46" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x47", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT46-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT46-CTRL", + "device_parent": "MUX9", + "virt_parent": "PORT46" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x47", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x15", + "attr_mask": "0x5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x45", + "attr_mask": "0x5", + "attr_cmpval": "0x20", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x4b", + "attr_mask": "0x5", + "attr_cmpval": "0x20", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x75", + "attr_mask": "0x5", + "attr_cmpval": "0x20", + "attr_len": "1" + } + ] + } + }, + "PORT47": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT47", + "device_parent": "MUX9" + }, + "dev_attr": { + "dev_idx": "47" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT47-EEPROM" + }, + { + "itf": "control", + "dev": "PORT47-CTRL" + } + ] + } + }, + "PORT47-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT47-EEPROM", + "device_parent": "MUX9", + "virt_parent": "PORT47" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x48", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT47-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT47-CTRL", + "device_parent": "MUX9", + "virt_parent": "PORT47" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x48", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x15", + "attr_mask": "0x6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x45", + "attr_mask": "0x6", + "attr_cmpval": "0x40", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x4b", + "attr_mask": "0x6", + "attr_cmpval": "0x40", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x75", + "attr_mask": "0x6", + "attr_cmpval": "0x40", + "attr_len": "1" + } + ] + } + }, + "PORT48": { + "dev_info": { + "device_type": "SFP28", + "device_name": "PORT48", + "device_parent": "MUX9" + }, + "dev_attr": { + "dev_idx": "48" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT48-EEPROM" + }, + { + "itf": "control", + "dev": "PORT48-CTRL" + } + ] + } + }, + "PORT48-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT48-EEPROM", + "device_parent": "MUX9", + "virt_parent": "PORT48" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x49", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT48-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT48-CTRL", + "device_parent": "MUX9", + "virt_parent": "PORT48" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x49", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x15", + "attr_mask": "0x7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x45", + "attr_mask": "0x7", + "attr_cmpval": "0x80", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x4b", + "attr_mask": "0x7", + "attr_cmpval": "0x80", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x75", + "attr_mask": "0x7", + "attr_cmpval": "0x80", + "attr_len": "1" + } + ] + } + }, + "PORT49": { + "dev_info": { + "device_type": "QSFP28", + "device_name": "PORT49", + "device_parent": "MUX10" + }, + "dev_attr": { + "dev_idx": "49" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT49-EEPROM" + }, + { + "itf": "control", + "dev": "PORT49-CTRL" + } + ] + } + }, + "PORT49-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT49-EEPROM", + "device_parent": "MUX10", + "virt_parent": "PORT49" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x4a", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT49-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT49-CTRL", + "device_parent": "MUX10", + "virt_parent": "PORT49" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x4a", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x16", + "attr_mask": "0x0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x17", + "attr_mask": "0x0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x76", + "attr_mask": "0x0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x77", + "attr_mask": "0x0", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT50": { + "dev_info": { + "device_type": "QSFP28", + "device_name": "PORT50", + "device_parent": "MUX10" + }, + "dev_attr": { + "dev_idx": "50" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT50-EEPROM" + }, + { + "itf": "control", + "dev": "PORT50-CTRL" + } + ] + } + }, + "PORT50-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT50-EEPROM", + "device_parent": "MUX10", + "virt_parent": "PORT50" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x4b", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT50-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT50-CTRL", + "device_parent": "MUX10", + "virt_parent": "PORT50" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x4b", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x16", + "attr_mask": "0x1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x17", + "attr_mask": "0x1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x76", + "attr_mask": "0x1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x77", + "attr_mask": "0x1", + "attr_cmpval": "0x2", + "attr_len": "1" + } + ] + } + }, + "PORT51": { + "dev_info": { + "device_type": "QSFP28", + "device_name": "PORT51", + "device_parent": "MUX10" + }, + "dev_attr": { + "dev_idx": "51" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT51-EEPROM" + }, + { + "itf": "control", + "dev": "PORT51-CTRL" + } + ] + } + }, + "PORT51-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT51-EEPROM", + "device_parent": "MUX10", + "virt_parent": "PORT51" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x4c", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT51-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT51-CTRL", + "device_parent": "MUX10", + "virt_parent": "PORT51" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x4c", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x16", + "attr_mask": "0x2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x17", + "attr_mask": "0x2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x76", + "attr_mask": "0x2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x77", + "attr_mask": "0x2", + "attr_cmpval": "0x4", + "attr_len": "1" + } + ] + } + }, + "PORT52": { + "dev_info": { + "device_type": "QSFP28", + "device_name": "PORT52", + "device_parent": "MUX10" + }, + "dev_attr": { + "dev_idx": "52" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT52-EEPROM" + }, + { + "itf": "control", + "dev": "PORT52-CTRL" + } + ] + } + }, + "PORT52-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT52-EEPROM", + "device_parent": "MUX10", + "virt_parent": "PORT52" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x4d", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT52-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT52-CTRL", + "device_parent": "MUX10", + "virt_parent": "PORT52" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x4d", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x16", + "attr_mask": "0x3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x17", + "attr_mask": "0x3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x76", + "attr_mask": "0x3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x77", + "attr_mask": "0x3", + "attr_cmpval": "0x8", + "attr_len": "1" + } + ] + } + }, + "PORT53": { + "dev_info": { + "device_type": "QSFP28", + "device_name": "PORT53", + "device_parent": "MUX10" + }, + "dev_attr": { + "dev_idx": "53" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT53-EEPROM" + }, + { + "itf": "control", + "dev": "PORT53-CTRL" + } + ] + } + }, + "PORT53-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT53-EEPROM", + "device_parent": "MUX10", + "virt_parent": "PORT53" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x4e", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT53-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT53-CTRL", + "device_parent": "MUX10", + "virt_parent": "PORT53" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x4e", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x16", + "attr_mask": "0x4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x17", + "attr_mask": "0x4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x76", + "attr_mask": "0x4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x77", + "attr_mask": "0x4", + "attr_cmpval": "0x10", + "attr_len": "1" + } + ] + } + }, + "PORT54": { + "dev_info": { + "device_type": "QSFP28", + "device_name": "PORT54", + "device_parent": "MUX10" + }, + "dev_attr": { + "dev_idx": "54" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT54-EEPROM" + }, + { + "itf": "control", + "dev": "PORT54-CTRL" + } + ] + } + }, + "PORT54-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT54-EEPROM", + "device_parent": "MUX10", + "virt_parent": "PORT54" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x4f", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT54-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT54-CTRL", + "device_parent": "MUX10", + "virt_parent": "PORT54" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x4f", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x16", + "attr_mask": "0x5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x17", + "attr_mask": "0x5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x76", + "attr_mask": "0x5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x77", + "attr_mask": "0x5", + "attr_cmpval": "0x20", + "attr_len": "1" + } + ] + } + } +} diff --git a/device/ufispace/x86_64-ufispace_s8901_54xc-r0/pddf_support b/device/ufispace/x86_64-ufispace_s8901_54xc-r0/pddf_support new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/device/ufispace/x86_64-ufispace_s8901_54xc-r0/platform.json b/device/ufispace/x86_64-ufispace_s8901_54xc-r0/platform.json new file mode 100644 index 000000000000..3db26c98428e --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s8901_54xc-r0/platform.json @@ -0,0 +1,691 @@ +{ + "chassis": { + "name": "S8901-54XC", + "components": [ + { + "name": "CPLD1" + }, + { + "name": "CPLD2" + }, + { + "name": "BIOS" + }, + { + "name": "BMC" + } + ], + "fans": [ + { + "name": "Fan_1" + }, + { + "name": "Fan_2" + }, + { + "name": "Fan_3" + }, + { + "name": "Fan_4" + }, + { + "name": "Fan_5" + } + ], + "fan_drawers":[ + { + "name": "Fantray1", + "num_fans" : 1, + "fans": [ + { + "name": "Fan_1" + } + ] + }, + { + "name": "Fantray2", + "num_fans" : 1, + "fans": [ + { + "name": "Fan_2" + } + ] + }, + { + "name": "Fantray3", + "num_fans" : 1, + "fans": [ + { + "name": "Fan_3" + } + ] + }, + { + "name": "Fantray4", + "num_fans" : 1, + "fans": [ + { + "name": "Fan_4" + } + ] + }, + { + "name": "Fantray5", + "num_fans" : 1, + "fans": [ + { + "name": "Fan_5" + } + ] + } + ], + "psus": [ + { + "name": "PSU1", + "fans": [ + { + "name": "PSU1_FAN1" + } + ], + "thermals": [ + { + "name": "PSU1_TEMP1" + } + ] + }, + { + "name": "PSU2", + "fans": [ + { + "name": "PSU2_FAN1" + } + ], + "thermals": [ + { + "name": "PSU2_TEMP1" + } + ] + } + ], + "thermals": [ + { + "name": "TEMP_MAC" + }, + { + "name": "TEMP_ENV_MACCASE" + }, + { + "name": "TEMP_ENV_PSUCASE" + }, + { + "name": "TEMP_ENV_FANCONN" + }, + { + "name": "TEMP_ENV_FANCARD" + }, + { + "name": "TEMP_ENV_BMC" + }, + { + "name": "PSU-0-Thermal" + }, + { + "name": "PSU-1-Thermal" + } + ], + "sfps": [ + { + "name": "Ethernet0" + }, + { + "name": "Ethernet1" + }, + { + "name": "Ethernet2" + }, + { + "name": "Ethernet3" + }, + { + "name": "Ethernet4" + }, + { + "name": "Ethernet5" + }, + { + "name": "Ethernet6" + }, + { + "name": "Ethernet7" + }, + { + "name": "Ethernet8" + }, + { + "name": "Ethernet9" + }, + { + "name": "Ethernet10" + }, + { + "name": "Ethernet11" + }, + { + "name": "Ethernet12" + }, + { + "name": "Ethernet13" + }, + { + "name": "Ethernet14" + }, + { + "name": "Ethernet15" + }, + { + "name": "Ethernet16" + }, + { + "name": "Ethernet17" + }, + { + "name": "Ethernet18" + }, + { + "name": "Ethernet19" + }, + { + "name": "Ethernet20" + }, + { + "name": "Ethernet21" + }, + { + "name": "Ethernet22" + }, + { + "name": "Ethernet23" + }, + { + "name": "Ethernet24" + }, + { + "name": "Ethernet25" + }, + { + "name": "Ethernet26" + }, + { + "name": "Ethernet27" + }, + { + "name": "Ethernet28" + }, + { + "name": "Ethernet29" + }, + { + "name": "Ethernet30" + }, + { + "name": "Ethernet31" + }, + { + "name": "Ethernet32" + }, + { + "name": "Ethernet33" + }, + { + "name": "Ethernet34" + }, + { + "name": "Ethernet35" + }, + { + "name": "Ethernet36" + }, + { + "name": "Ethernet37" + }, + { + "name": "Ethernet38" + }, + { + "name": "Ethernet39" + }, + { + "name": "Ethernet40" + }, + { + "name": "Ethernet41" + }, + { + "name": "Ethernet42" + }, + { + "name": "Ethernet43" + }, + { + "name": "Ethernet44" + }, + { + "name": "Ethernet45" + }, + { + "name": "Ethernet46" + }, + { + "name": "Ethernet47" + }, + { + "name": "Ethernet48" + }, + { + "name": "Ethernet52" + }, + { + "name": "Ethernet56" + }, + { + "name": "Ethernet60" + }, + { + "name": "Ethernet64" + }, + { + "name": "Ethernet68" + }, + { + "name": "Ethernet72" + } + ] + }, + "interfaces": { + "Ethernet0": { + "index": "0", + "lanes": "1", + "breakout_modes": { + "1x25G[10G]" : [ "Eth0(Port0)" ] + } + }, + "Ethernet1": { + "index": "1", + "lanes": "2", + "breakout_modes": { + "1x25G[10G]" : [ "Eth1(Port1)" ] + } + }, + "Ethernet2": { + "index": "2", + "lanes": "3", + "breakout_modes": { + "1x25G[10G]" : [ "Eth2(Port2)" ] + } + }, + "Ethernet3": { + "index": "3", + "lanes": "4", + "breakout_modes": { + "1x25G[10G]" : [ "Eth3(Port3)" ] + } + }, + "Ethernet4": { + "index": "4", + "lanes": "5", + "breakout_modes": { + "1x25G[10G]" : [ "Eth4(Port4)" ] + } + }, + "Ethernet5": { + "index": "5", + "lanes": "6", + "breakout_modes": { + "1x25G[10G]" : [ "Eth5(Port5)" ] + } + }, + "Ethernet6": { + "index": "6", + "lanes": "7", + "breakout_modes": { + "1x25G[10G]" : [ "Eth6(Port6)" ] + } + }, + "Ethernet7": { + "index": "7", + "lanes": "8", + "breakout_modes": { + "1x25G[10G]" : [ "Eth7(Port7)" ] + } + }, + "Ethernet8": { + "index": "8", + "lanes": "9", + "breakout_modes": { + "1x25G[10G]" : [ "Eth8(Port8)" ] + } + }, + "Ethernet9": { + "index": "9", + "lanes": "10", + "breakout_modes": { + "1x25G[10G]" : [ "Eth9(Port9)" ] + } + }, + "Ethernet10": { + "index": "10", + "lanes": "11", + "breakout_modes": { + "1x25G[10G]" : [ "Eth10(Port10)" ] + } + }, + "Ethernet11": { + "index": "11", + "lanes": "12", + "breakout_modes": { + "1x25G[10G]" : [ "Eth11(Port11)" ] + } + }, + "Ethernet12": { + "index": "12", + "lanes": "13", + "breakout_modes": { + "1x25G[10G]" : [ "Eth12(Port12)" ] + } + }, + "Ethernet13": { + "index": "13", + "lanes": "14", + "breakout_modes": { + "1x25G[10G]" : [ "Eth13(Port13)" ] + } + }, + "Ethernet14": { + "index": "14", + "lanes": "15", + "breakout_modes": { + "1x25G[10G]" : [ "Eth14(Port14)" ] + } + }, + "Ethernet15": { + "index": "15", + "lanes": "16", + "breakout_modes": { + "1x25G[10G]" : [ "Eth15(Port15)" ] + } + }, + "Ethernet16": { + "index": "16", + "lanes": "17", + "breakout_modes": { + "1x25G[10G]" : [ "Eth16(Port16)" ] + } + }, + "Ethernet17": { + "index": "17", + "lanes": "18", + "breakout_modes": { + "1x25G[10G]" : [ "Eth17(Port17)" ] + } + }, + "Ethernet18": { + "index": "18", + "lanes": "19", + "breakout_modes": { + "1x25G[10G]" : [ "Eth18(Port18)" ] + } + }, + "Ethernet19": { + "index": "19", + "lanes": "20", + "breakout_modes": { + "1x25G[10G]" : [ "Eth19(Port19)" ] + } + }, + "Ethernet20": { + "index": "20", + "lanes": "21", + "breakout_modes": { + "1x25G[10G]" : [ "Eth20(Port20)" ] + } + }, + "Ethernet21": { + "index": "21", + "lanes": "22", + "breakout_modes": { + "1x25G[10G]" : [ "Eth21(Port21)" ] + } + }, + "Ethernet22": { + "index": "22", + "lanes": "23", + "breakout_modes": { + "1x25G[10G]" : [ "Eth22(Port22)" ] + } + }, + "Ethernet23": { + "index": "23", + "lanes": "24", + "breakout_modes": { + "1x25G[10G]" : [ "Eth23(Port23)" ] + } + }, + "Ethernet24": { + "index": "24", + "lanes": "25", + "breakout_modes": { + "1x25G[10G]" : [ "Eth24(Port24)" ] + } + }, + "Ethernet25": { + "index": "25", + "lanes": "26", + "breakout_modes": { + "1x25G[10G]" : [ "Eth25(Port25)" ] + } + }, + "Ethernet26": { + "index": "26", + "lanes": "27", + "breakout_modes": { + "1x25G[10G]" : [ "Eth26(Port26)" ] + } + }, + "Ethernet27": { + "index": "27", + "lanes": "28", + "breakout_modes": { + "1x25G[10G]" : [ "Eth27(Port27)" ] + } + }, + "Ethernet28": { + "index": "28", + "lanes": "41", + "breakout_modes": { + "1x25G[10G]" : [ "Eth28(Port28)" ] + } + }, + "Ethernet29": { + "index": "29", + "lanes": "42", + "breakout_modes": { + "1x25G[10G]" : [ "Eth29(Port29)" ] + } + }, + "Ethernet30": { + "index": "30", + "lanes": "43", + "breakout_modes": { + "1x25G[10G]" : [ "Eth30(Port30)" ] + } + }, + "Ethernet31": { + "index": "31", + "lanes": "44", + "breakout_modes": { + "1x25G[10G]" : [ "Eth31(Port31)" ] + } + }, + "Ethernet32": { + "index": "32", + "lanes": "61", + "breakout_modes": { + "1x25G[10G]" : [ "Eth32(Port32)" ] + } + }, + "Ethernet33": { + "index": "33", + "lanes": "62", + "breakout_modes": { + "1x25G[10G]" : [ "Eth33(Port33)" ] + } + }, + "Ethernet34": { + "index": "34", + "lanes": "63", + "breakout_modes": { + "1x25G[10G]" : [ "Eth34(Port34)" ] + } + }, + "Ethernet35": { + "index": "35", + "lanes": "64", + "breakout_modes": { + "1x25G[10G]" : [ "Eth35(Port35)" ] + } + }, + "Ethernet36": { + "index": "36", + "lanes": "65", + "breakout_modes": { + "1x25G[10G]" : [ "Eth36(Port36)" ] + } + }, + "Ethernet37": { + "index": "37", + "lanes": "66", + "breakout_modes": { + "1x25G[10G]" : [ "Eth37(Port37)" ] + } + }, + "Ethernet38": { + "index": "38", + "lanes": "67", + "breakout_modes": { + "1x25G[10G]" : [ "Eth38(Port38)" ] + } + }, + "Ethernet39": { + "index": "39", + "lanes": "68", + "breakout_modes": { + "1x25G[10G]" : [ "Eth39(Port39)" ] + } + }, + "Ethernet40": { + "index": "40", + "lanes": "69", + "breakout_modes": { + "1x25G[10G]" : [ "Eth40(Port40)" ] + } + }, + "Ethernet41": { + "index": "41", + "lanes": "70", + "breakout_modes": { + "1x25G[10G]" : [ "Eth41(Port41)" ] + } + }, + "Ethernet42": { + "index": "42", + "lanes": "71", + "breakout_modes": { + "1x25G[10G]" : [ "Eth42(Port42)" ] + } + }, + "Ethernet43": { + "index": "43", + "lanes": "72", + "breakout_modes": { + "1x25G[10G]" : [ "Eth43(Port43)" ] + } + }, + "Ethernet44": { + "index": "44", + "lanes": "73", + "breakout_modes": { + "1x25G[10G]" : [ "Eth44(Port44)" ] + } + }, + "Ethernet45": { + "index": "45", + "lanes": "74", + "breakout_modes": { + "1x25G[10G]" : [ "Eth45(Port45)" ] + } + }, + "Ethernet46": { + "index": "46", + "lanes": "75", + "breakout_modes": { + "1x25G[10G]" : [ "Eth46(Port46)" ] + } + }, + "Ethernet47": { + "index": "47", + "lanes": "76", + "breakout_modes": { + "1x25G[10G]" : [ "Eth47(Port47)" ] + } + }, + "Ethernet48": { + "index": "48,48,48,48", + "lanes": "37,38,39,40", + "breakout_modes": { + "1x100G[40G]" : [ "Eth48(Port48)" ] + } + }, + "Ethernet52": { + "index": "49,49,49,49", + "lanes": "33,34,35,36", + "breakout_modes": { + "1x100G[40G]" : [ "Eth49(Port49)" ] + } + }, + "Ethernet56": { + "index": "50,50,50,50", + "lanes": "45,46,47,48", + "breakout_modes": { + "1x100G[40G]" : [ "Eth50(Port50)" ] + } + }, + "Ethernet60": { + "index": "51,51,51,51", + "lanes": "49,50,51,52", + "breakout_modes": { + "1x100G[40G]" : [ "Eth51(Port51)" ] + } + }, + "Ethernet64": { + "index": "52,52,52,52", + "lanes": "53,54,55,56", + "breakout_modes": { + "1x100G[40G]" : [ "Eth52(Port52)" ], + "2x50G": ["Eth52/1(Port52)", "Eth52/2(Port52)"], + "4x25G": ["Eth52/1(Port52)", "Eth52/2(Port52)", "Eth52/3(Port52)", "Eth52/4(Port52)"], + "4x10G": ["Eth52/1(Port52)", "Eth52/2(Port52)", "Eth52/3(Port52)", "Eth52/4(Port52)"] + } + }, + "Ethernet68": { + "index": "53,53,53,53", + "lanes": "57,58,59,60", + "breakout_modes": { + "1x100G[40G]" : [ "Eth53(Port53)" ], + "2x50G": ["Eth53/1(Port53)", "Eth53/2(Port53)"], + "4x25G": ["Eth53/1(Port53)", "Eth53/2(Port53)", "Eth53/3(Port53)", "Eth53/4(Port53)"], + "4x10G": ["Eth53/1(Port53)", "Eth53/2(Port53)", "Eth53/3(Port53)", "Eth53/4(Port53)"] + } + } + } +} + diff --git a/device/ufispace/x86_64-ufispace_s8901_54xc-r0/platform_asic b/device/ufispace/x86_64-ufispace_s8901_54xc-r0/platform_asic new file mode 100644 index 000000000000..960467652765 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s8901_54xc-r0/platform_asic @@ -0,0 +1 @@ +broadcom diff --git a/device/ufispace/x86_64-ufispace_s8901_54xc-r0/platform_components.json b/device/ufispace/x86_64-ufispace_s8901_54xc-r0/platform_components.json new file mode 100644 index 000000000000..d122f45806c0 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s8901_54xc-r0/platform_components.json @@ -0,0 +1,12 @@ +{ + "chassis": { + "x86_64-ufispace_s8901_54xc-r0": { + "component": { + "CPLD1": { }, + "CPLD2": { }, + "BIOS": { }, + "BMC": {} + } + } + } +} diff --git a/device/ufispace/x86_64-ufispace_s8901_54xc-r0/platform_env.conf b/device/ufispace/x86_64-ufispace_s8901_54xc-r0/platform_env.conf new file mode 100644 index 000000000000..77fd88ac3678 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s8901_54xc-r0/platform_env.conf @@ -0,0 +1 @@ +SYNCD_SHM_SIZE=256m diff --git a/device/ufispace/x86_64-ufispace_s8901_54xc-r0/pmon_daemon_control.json b/device/ufispace/x86_64-ufispace_s8901_54xc-r0/pmon_daemon_control.json new file mode 100644 index 000000000000..e348e0168fa5 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s8901_54xc-r0/pmon_daemon_control.json @@ -0,0 +1,9 @@ +{ + "skip_pcied": false, + "skip_fancontrol": false, + "skip_thermalctld": false, + "skip_ledd": true, + "skip_xcvrd": false, + "skip_psud": false, + "skip_syseepromd": false +} diff --git a/device/ufispace/x86_64-ufispace_s8901_54xc-r0/sensors.conf b/device/ufispace/x86_64-ufispace_s8901_54xc-r0/sensors.conf new file mode 100644 index 000000000000..b1a69433405b --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s8901_54xc-r0/sensors.conf @@ -0,0 +1 @@ +# libsensors configuration file diff --git a/device/ufispace/x86_64-ufispace_s8901_54xc-r0/system_health_monitoring_config.json b/device/ufispace/x86_64-ufispace_s8901_54xc-r0/system_health_monitoring_config.json new file mode 100644 index 000000000000..467d81304de0 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s8901_54xc-r0/system_health_monitoring_config.json @@ -0,0 +1,15 @@ +{ + "services_to_ignore": [], + "devices_to_ignore": [ + "asic", + "psu", + "fan" + ], + "user_defined_checkers": [], + "polling_interval": 60, + "led_color": { + "fault": "yellow", + "normal": "green", + "booting": "green_blink" + } +} diff --git a/device/ufispace/x86_64-ufispace_s9110_32x-r0/UFISPACE-S9110-32X/hwsku.json b/device/ufispace/x86_64-ufispace_s9110_32x-r0/UFISPACE-S9110-32X/hwsku.json new file mode 100644 index 000000000000..52ee4d8e9daa --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s9110_32x-r0/UFISPACE-S9110-32X/hwsku.json @@ -0,0 +1,136 @@ +{ + "interfaces": { + "Ethernet0": { + "default_brkout_mode": "1x100G[40G]" + }, + + "Ethernet4": { + "default_brkout_mode": "1x100G[40G]" + }, + + "Ethernet8": { + "default_brkout_mode": "1x100G[40G]" + }, + + "Ethernet12": { + "default_brkout_mode": "1x100G[40G]" + }, + + "Ethernet16": { + "default_brkout_mode": "1x100G[40G]" + }, + + "Ethernet20": { + "default_brkout_mode": "1x100G[40G]" + }, + + "Ethernet24": { + "default_brkout_mode": "1x100G[40G]" + }, + + "Ethernet28": { + "default_brkout_mode": "1x100G[40G]" + }, + + "Ethernet32": { + "default_brkout_mode": "1x100G[40G]" + }, + + "Ethernet36": { + "default_brkout_mode": "1x100G[40G]" + }, + + "Ethernet40": { + "default_brkout_mode": "1x100G[40G]" + }, + + "Ethernet44": { + "default_brkout_mode": "1x100G[40G]" + }, + + "Ethernet48": { + "default_brkout_mode": "1x100G[40G]" + }, + + "Ethernet52": { + "default_brkout_mode": "1x100G[40G]" + }, + + "Ethernet56": { + "default_brkout_mode": "1x100G[40G]" + }, + + "Ethernet60": { + "default_brkout_mode": "1x100G[40G]" + }, + + "Ethernet64": { + "default_brkout_mode": "1x100G[40G]" + }, + + "Ethernet68": { + "default_brkout_mode": "1x100G[40G]" + }, + + "Ethernet72": { + "default_brkout_mode": "1x100G[40G]" + }, + + "Ethernet76": { + "default_brkout_mode": "1x100G[40G]" + }, + + "Ethernet80": { + "default_brkout_mode": "1x100G[40G]" + }, + + "Ethernet84": { + "default_brkout_mode": "1x100G[40G]" + }, + + "Ethernet88": { + "default_brkout_mode": "1x100G[40G]" + }, + + "Ethernet92": { + "default_brkout_mode": "1x100G[40G]" + }, + + "Ethernet96": { + "default_brkout_mode": "1x100G[40G]" + }, + + "Ethernet100": { + "default_brkout_mode": "1x100G[40G]" + }, + + "Ethernet104": { + "default_brkout_mode": "1x100G[40G]" + }, + + "Ethernet108": { + "default_brkout_mode": "1x100G[40G]" + }, + + "Ethernet112": { + "default_brkout_mode": "1x100G[40G]" + }, + + "Ethernet116": { + "default_brkout_mode": "1x100G[40G]" + }, + + "Ethernet120": { + "default_brkout_mode": "1x100G[40G]" + }, + + "Ethernet124": { + "default_brkout_mode": "1x100G[40G]" + }, + + "Ethernet128": { + "default_brkout_mode": "1x10G" + } + } +} + diff --git a/device/ufispace/x86_64-ufispace_s9110_32x-r0/UFISPACE-S9110-32X/sai.profile b/device/ufispace/x86_64-ufispace_s9110_32x-r0/UFISPACE-S9110-32X/sai.profile new file mode 100755 index 000000000000..f602ed298f70 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s9110_32x-r0/UFISPACE-S9110-32X/sai.profile @@ -0,0 +1 @@ +SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/td3-x7-s9110-32x.config.bcm diff --git a/device/ufispace/x86_64-ufispace_s9110_32x-r0/UFISPACE-S9110-32X/td3-x7-s9110-32x.config.bcm b/device/ufispace/x86_64-ufispace_s9110_32x-r0/UFISPACE-S9110-32X/td3-x7-s9110-32x.config.bcm new file mode 100755 index 000000000000..94e9aa183a45 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s9110_32x-r0/UFISPACE-S9110-32X/td3-x7-s9110-32x.config.bcm @@ -0,0 +1,671 @@ +# cfg version: r2, 20230713 + +pbmp_xport_xe=0xFFFFFFFFFFFFFFFFFfffffffffffffffe + +# Software config lane swaps + +#FC0 QSFP port 0 +phy_chain_rx_lane_map_physical{1}=0x2310 +phy_chain_tx_lane_map_physical{1}=0x0132 + +#FC1 QSFP port 1 +phy_chain_rx_lane_map_physical{5}=0x3120 +phy_chain_tx_lane_map_physical{5}=0x1203 + +#FC2 QSFP port 2 +phy_chain_rx_lane_map_physical{9}=0x2310 +phy_chain_tx_lane_map_physical{9}=0x0213 + +#FC3 QSFP port 3 +phy_chain_rx_lane_map_physical{13}=0x3120 +phy_chain_tx_lane_map_physical{13}=0x1203 + +#FC4 QSFP port 4 +phy_chain_rx_lane_map_physical{17}=0x2310 +phy_chain_tx_lane_map_physical{17}=0x0132 + +#FC5 QSFP port 5 +phy_chain_rx_lane_map_physical{21}=0x3120 +phy_chain_tx_lane_map_physical{21}=0x1203 + +#FC6 QSFP port 6 +phy_chain_rx_lane_map_physical{25}=0x2310 +phy_chain_tx_lane_map_physical{25}=0x0132 + +#FC7 QSFP port 7 +phy_chain_rx_lane_map_physical{29}=0x3120 +phy_chain_tx_lane_map_physical{29}=0x1203 + +#FC8 QSFP port 8 +phy_chain_rx_lane_map_physical{33}=0x2310 +phy_chain_tx_lane_map_physical{33}=0x0132 + +#FC9 QSFP port 9 +phy_chain_rx_lane_map_physical{37}=0x3120 +phy_chain_tx_lane_map_physical{37}=0x1203 + +#FC10 QSFP port 10 +phy_chain_rx_lane_map_physical{41}=0x2310 +phy_chain_tx_lane_map_physical{41}=0x0132 + +#FC11 QSFP port 11 +phy_chain_rx_lane_map_physical{45}=0x3120 +phy_chain_tx_lane_map_physical{45}=0x1203 + +#FC12 QSFP port 12 +phy_chain_rx_lane_map_physical{49}=0x1320 +phy_chain_tx_lane_map_physical{49}=0x0231 + +#FC13 QSFP port 13 +phy_chain_rx_lane_map_physical{53}=0x3120 +phy_chain_tx_lane_map_physical{53}=0x1203 + +#FC14 QSFP port 14 +phy_chain_rx_lane_map_physical{57}=0x2310 +phy_chain_tx_lane_map_physical{57}=0x0132 + +#FC15 QSFP port 15 +phy_chain_rx_lane_map_physical{61}=0x3120 +phy_chain_tx_lane_map_physical{61}=0x1203 + +#FC16 QSFP port 17 +phy_chain_rx_lane_map_physical{65}=0x3021 +phy_chain_tx_lane_map_physical{65}=0x0312 + +#FC17 QSFP port 16 +phy_chain_rx_lane_map_physical{69}=0x1032 +phy_chain_tx_lane_map_physical{69}=0x3201 + +#FC18 QSFP port 19 +phy_chain_rx_lane_map_physical{73}=0x3021 +phy_chain_tx_lane_map_physical{73}=0x1302 + +#FC19 QSFP port 18 +phy_chain_rx_lane_map_physical{77}=0x2013 +phy_chain_tx_lane_map_physical{77}=0x3210 + +#FC20 QSFP port 21 +phy_chain_rx_lane_map_physical{81}=0x3021 +phy_chain_tx_lane_map_physical{81}=0x1302 + +#FC21 QSFP port 20 +phy_chain_rx_lane_map_physical{85}=0x2031 +phy_chain_tx_lane_map_physical{85}=0x3201 + +#FC22 QSFP port 23 +phy_chain_rx_lane_map_physical{89}=0x3021 +phy_chain_tx_lane_map_physical{89}=0x1302 + +#FC23 QSFP port 22 +phy_chain_rx_lane_map_physical{93}=0x2031 +phy_chain_tx_lane_map_physical{93}=0x3201 + +#FC24 QSFP port 25 +phy_chain_rx_lane_map_physical{97}=0x3021 +phy_chain_tx_lane_map_physical{97}=0x1302 + +#FC25 QSFP port 24 +phy_chain_rx_lane_map_physical{101}=0x2031 +phy_chain_tx_lane_map_physical{101}=0x1302 + +#FC26 QSFP port 27 +phy_chain_rx_lane_map_physical{105}=0x3021 +phy_chain_tx_lane_map_physical{105}=0x1302 + +#FC27 QSFP port 26 +phy_chain_rx_lane_map_physical{109}=0x2031 +phy_chain_tx_lane_map_physical{109}=0x1302 + +#FC28 QSFP port 29 +phy_chain_rx_lane_map_physical{113}=0x2031 +phy_chain_tx_lane_map_physical{113}=0x1302 + +#FC29 QSFP port 28 +phy_chain_rx_lane_map_physical{117}=0x2031 +phy_chain_tx_lane_map_physical{117}=0x1302 + +#FC30 QSFP port 31 +phy_chain_rx_lane_map_physical{121}=0x2031 +phy_chain_tx_lane_map_physical{121}=0x1302 + +#FC31 QSFP port 30 +phy_chain_rx_lane_map_physical{125}=0x2031 +phy_chain_tx_lane_map_physical{125}=0x3201 + +#MC management port (front port) +phy_chain_rx_lane_map_physical{129}=0x3210 +phy_chain_tx_lane_map_physical{129}=0x3210 + + +####### Polarity flips after lane swaps ###### + +#FC0 QSFP port 0 +phy_chain_rx_polarity_flip_physical{1}=0x1 +phy_chain_rx_polarity_flip_physical{2}=0x0 +phy_chain_rx_polarity_flip_physical{3}=0x0 +phy_chain_rx_polarity_flip_physical{4}=0x1 + +phy_chain_tx_polarity_flip_physical{1}=0x1 +phy_chain_tx_polarity_flip_physical{2}=0x0 +phy_chain_tx_polarity_flip_physical{3}=0x0 +phy_chain_tx_polarity_flip_physical{4}=0x1 + +#FC1 QSFP port 1 +phy_chain_rx_polarity_flip_physical{5}=0x0 +phy_chain_rx_polarity_flip_physical{6}=0x0 +phy_chain_rx_polarity_flip_physical{7}=0x1 +phy_chain_rx_polarity_flip_physical{8}=0x1 + +phy_chain_tx_polarity_flip_physical{5}=0x0 +phy_chain_tx_polarity_flip_physical{6}=0x1 +phy_chain_tx_polarity_flip_physical{7}=0x1 +phy_chain_tx_polarity_flip_physical{8}=0x1 + +#FC2 QSFP port 2 +phy_chain_rx_polarity_flip_physical{9}=0x1 +phy_chain_rx_polarity_flip_physical{10}=0x0 +phy_chain_rx_polarity_flip_physical{11}=0x0 +phy_chain_rx_polarity_flip_physical{12}=0x1 + +phy_chain_tx_polarity_flip_physical{9}=0x0 +phy_chain_tx_polarity_flip_physical{10}=0x1 +phy_chain_tx_polarity_flip_physical{11}=0x1 +phy_chain_tx_polarity_flip_physical{12}=0x0 + +#FC3 QSFP port 3 +phy_chain_rx_polarity_flip_physical{13}=0x0 +phy_chain_rx_polarity_flip_physical{14}=0x0 +phy_chain_rx_polarity_flip_physical{15}=0x1 +phy_chain_rx_polarity_flip_physical{16}=0x1 + +phy_chain_tx_polarity_flip_physical{13}=0x0 +phy_chain_tx_polarity_flip_physical{14}=0x1 +phy_chain_tx_polarity_flip_physical{15}=0x1 +phy_chain_tx_polarity_flip_physical{16}=0x1 + +#FC4 QSFP port 4 +phy_chain_rx_polarity_flip_physical{17}=0x1 +phy_chain_rx_polarity_flip_physical{18}=0x0 +phy_chain_rx_polarity_flip_physical{19}=0x0 +phy_chain_rx_polarity_flip_physical{20}=0x1 + +phy_chain_tx_polarity_flip_physical{17}=0x0 +phy_chain_tx_polarity_flip_physical{18}=0x0 +phy_chain_tx_polarity_flip_physical{19}=0x1 +phy_chain_tx_polarity_flip_physical{20}=0x1 + +#FC5 QSFP port 5 +phy_chain_rx_polarity_flip_physical{21}=0x0 +phy_chain_rx_polarity_flip_physical{22}=0x0 +phy_chain_rx_polarity_flip_physical{23}=0x1 +phy_chain_rx_polarity_flip_physical{24}=0x1 + +phy_chain_tx_polarity_flip_physical{21}=0x0 +phy_chain_tx_polarity_flip_physical{22}=0x1 +phy_chain_tx_polarity_flip_physical{23}=0x1 +phy_chain_tx_polarity_flip_physical{24}=0x1 + +#FC6 QSFP port 6 +phy_chain_rx_polarity_flip_physical{25}=0x0 +phy_chain_rx_polarity_flip_physical{26}=0x1 +phy_chain_rx_polarity_flip_physical{27}=0x1 +phy_chain_rx_polarity_flip_physical{28}=0x0 + +phy_chain_tx_polarity_flip_physical{25}=0x1 +phy_chain_tx_polarity_flip_physical{26}=0x0 +phy_chain_tx_polarity_flip_physical{27}=0x0 +phy_chain_tx_polarity_flip_physical{28}=0x0 + +#FC7 QSFP port 7 +phy_chain_rx_polarity_flip_physical{29}=0x1 +phy_chain_rx_polarity_flip_physical{30}=0x1 +phy_chain_rx_polarity_flip_physical{31}=0x0 +phy_chain_rx_polarity_flip_physical{32}=0x0 + +phy_chain_tx_polarity_flip_physical{29}=0x0 +phy_chain_tx_polarity_flip_physical{30}=0x1 +phy_chain_tx_polarity_flip_physical{31}=0x1 +phy_chain_tx_polarity_flip_physical{32}=0x1 + +#FC8 QSFP port 8 +phy_chain_rx_polarity_flip_physical{33}=0x0 +phy_chain_rx_polarity_flip_physical{34}=0x1 +phy_chain_rx_polarity_flip_physical{35}=0x1 +phy_chain_rx_polarity_flip_physical{36}=0x0 + +phy_chain_tx_polarity_flip_physical{33}=0x0 +phy_chain_tx_polarity_flip_physical{34}=0x0 +phy_chain_tx_polarity_flip_physical{35}=0x1 +phy_chain_tx_polarity_flip_physical{36}=0x1 + +#FC9 QSFP port 9 +phy_chain_rx_polarity_flip_physical{37}=0x1 +phy_chain_rx_polarity_flip_physical{38}=0x1 +phy_chain_rx_polarity_flip_physical{39}=0x0 +phy_chain_rx_polarity_flip_physical{40}=0x0 + +phy_chain_tx_polarity_flip_physical{37}=0x0 +phy_chain_tx_polarity_flip_physical{38}=0x1 +phy_chain_tx_polarity_flip_physical{39}=0x1 +phy_chain_tx_polarity_flip_physical{40}=0x1 + +#FC10 QSFP port 10 +phy_chain_rx_polarity_flip_physical{41}=0x0 +phy_chain_rx_polarity_flip_physical{42}=0x1 +phy_chain_rx_polarity_flip_physical{43}=0x1 +phy_chain_rx_polarity_flip_physical{44}=0x0 + +phy_chain_tx_polarity_flip_physical{41}=0x1 +phy_chain_tx_polarity_flip_physical{42}=0x0 +phy_chain_tx_polarity_flip_physical{43}=0x0 +phy_chain_tx_polarity_flip_physical{44}=0x1 + +#FC11 QSFP port 11 +phy_chain_rx_polarity_flip_physical{45}=0x1 +phy_chain_rx_polarity_flip_physical{46}=0x1 +phy_chain_rx_polarity_flip_physical{47}=0x0 +phy_chain_rx_polarity_flip_physical{48}=0x0 + +phy_chain_tx_polarity_flip_physical{45}=0x0 +phy_chain_tx_polarity_flip_physical{46}=0x1 +phy_chain_tx_polarity_flip_physical{47}=0x1 +phy_chain_tx_polarity_flip_physical{48}=0x1 + +#FC12 QSFP port 12 +phy_chain_rx_polarity_flip_physical{49}=0x0 +phy_chain_rx_polarity_flip_physical{50}=0x0 +phy_chain_rx_polarity_flip_physical{51}=0x1 +phy_chain_rx_polarity_flip_physical{52}=0x1 + +phy_chain_tx_polarity_flip_physical{49}=0x1 +phy_chain_tx_polarity_flip_physical{50}=0x0 +phy_chain_tx_polarity_flip_physical{51}=0x0 +phy_chain_tx_polarity_flip_physical{52}=0x1 + +#FC13 QSFP port 13 +phy_chain_rx_polarity_flip_physical{53}=0x0 +phy_chain_rx_polarity_flip_physical{54}=0x0 +phy_chain_rx_polarity_flip_physical{55}=0x1 +phy_chain_rx_polarity_flip_physical{56}=0x1 + +phy_chain_tx_polarity_flip_physical{53}=0x1 +phy_chain_tx_polarity_flip_physical{54}=0x0 +phy_chain_tx_polarity_flip_physical{55}=0x0 +phy_chain_tx_polarity_flip_physical{56}=0x0 + +#FC14 QSFP port 14 +phy_chain_rx_polarity_flip_physical{57}=0x1 +phy_chain_rx_polarity_flip_physical{58}=0x0 +phy_chain_rx_polarity_flip_physical{59}=0x0 +phy_chain_rx_polarity_flip_physical{60}=0x1 + +phy_chain_tx_polarity_flip_physical{57}=0x1 +phy_chain_tx_polarity_flip_physical{58}=0x1 +phy_chain_tx_polarity_flip_physical{59}=0x1 +phy_chain_tx_polarity_flip_physical{60}=0x0 + +#FC15 QSFP port 15 +phy_chain_rx_polarity_flip_physical{61}=0x0 +phy_chain_rx_polarity_flip_physical{62}=0x0 +phy_chain_rx_polarity_flip_physical{63}=0x1 +phy_chain_rx_polarity_flip_physical{64}=0x1 + +phy_chain_tx_polarity_flip_physical{61}=0x1 +phy_chain_tx_polarity_flip_physical{62}=0x0 +phy_chain_tx_polarity_flip_physical{63}=0x0 +phy_chain_tx_polarity_flip_physical{64}=0x0 + +#FC16 QSFP port 17 +phy_chain_rx_polarity_flip_physical{65}=0x1 +phy_chain_rx_polarity_flip_physical{66}=0x1 +phy_chain_rx_polarity_flip_physical{67}=0x0 +phy_chain_rx_polarity_flip_physical{68}=0x0 + +phy_chain_tx_polarity_flip_physical{65}=0x1 +phy_chain_tx_polarity_flip_physical{66}=0x0 +phy_chain_tx_polarity_flip_physical{67}=0x0 +phy_chain_tx_polarity_flip_physical{68}=0x0 + +#FC17 QSFP port 16 +phy_chain_rx_polarity_flip_physical{69}=0x1 +phy_chain_rx_polarity_flip_physical{70}=0x0 +phy_chain_rx_polarity_flip_physical{71}=0x1 +phy_chain_rx_polarity_flip_physical{72}=0x1 + +phy_chain_tx_polarity_flip_physical{69}=0x1 +phy_chain_tx_polarity_flip_physical{70}=0x0 +phy_chain_tx_polarity_flip_physical{71}=0x0 +phy_chain_tx_polarity_flip_physical{72}=0x0 + +#FC18 QSFP port 19 +phy_chain_rx_polarity_flip_physical{73}=0x1 +phy_chain_rx_polarity_flip_physical{74}=0x1 +phy_chain_rx_polarity_flip_physical{75}=0x0 +phy_chain_rx_polarity_flip_physical{76}=0x0 + +phy_chain_tx_polarity_flip_physical{73}=0x1 +phy_chain_tx_polarity_flip_physical{74}=0x1 +phy_chain_tx_polarity_flip_physical{75}=0x0 +phy_chain_tx_polarity_flip_physical{76}=0x1 + +#FC19 QSFP port 18 +phy_chain_rx_polarity_flip_physical{77}=0x0 +phy_chain_rx_polarity_flip_physical{78}=0x0 +phy_chain_rx_polarity_flip_physical{79}=0x1 +phy_chain_rx_polarity_flip_physical{80}=0x1 + +phy_chain_tx_polarity_flip_physical{77}=0x0 +phy_chain_tx_polarity_flip_physical{78}=0x0 +phy_chain_tx_polarity_flip_physical{79}=0x0 +phy_chain_tx_polarity_flip_physical{80}=0x0 + +#FC20 QSFP port 21 +phy_chain_rx_polarity_flip_physical{81}=0x1 +phy_chain_rx_polarity_flip_physical{82}=0x1 +phy_chain_rx_polarity_flip_physical{83}=0x0 +phy_chain_rx_polarity_flip_physical{84}=0x0 + +phy_chain_tx_polarity_flip_physical{81}=0x1 +phy_chain_tx_polarity_flip_physical{82}=0x1 +phy_chain_tx_polarity_flip_physical{83}=0x0 +phy_chain_tx_polarity_flip_physical{84}=0x1 + +#FC21 QSFP port 20 +phy_chain_rx_polarity_flip_physical{85}=0x0 +phy_chain_rx_polarity_flip_physical{86}=0x1 +phy_chain_rx_polarity_flip_physical{87}=0x1 +phy_chain_rx_polarity_flip_physical{88}=0x0 + +phy_chain_tx_polarity_flip_physical{85}=0x0 +phy_chain_tx_polarity_flip_physical{86}=0x0 +phy_chain_tx_polarity_flip_physical{87}=0x1 +phy_chain_tx_polarity_flip_physical{88}=0x0 + +#FC22 QSFP port 23 +phy_chain_rx_polarity_flip_physical{89}=0x1 +phy_chain_rx_polarity_flip_physical{90}=0x1 +phy_chain_rx_polarity_flip_physical{91}=0x0 +phy_chain_rx_polarity_flip_physical{92}=0x0 + +phy_chain_tx_polarity_flip_physical{89}=0x1 +phy_chain_tx_polarity_flip_physical{90}=0x1 +phy_chain_tx_polarity_flip_physical{91}=0x0 +phy_chain_tx_polarity_flip_physical{92}=0x1 + +#FC23 QSFP port 22 +phy_chain_rx_polarity_flip_physical{93}=0x0 +phy_chain_rx_polarity_flip_physical{94}=0x1 +phy_chain_rx_polarity_flip_physical{95}=0x1 +phy_chain_rx_polarity_flip_physical{96}=0x0 + +phy_chain_tx_polarity_flip_physical{93}=0x0 +phy_chain_tx_polarity_flip_physical{94}=0x1 +phy_chain_tx_polarity_flip_physical{95}=0x1 +phy_chain_tx_polarity_flip_physical{96}=0x0 + +#FC24 QSFP port 25 +phy_chain_rx_polarity_flip_physical{97}=0x1 +phy_chain_rx_polarity_flip_physical{98}=0x1 +phy_chain_rx_polarity_flip_physical{99}=0x0 +phy_chain_rx_polarity_flip_physical{100}=0x0 + +phy_chain_tx_polarity_flip_physical{97}=0x1 +phy_chain_tx_polarity_flip_physical{98}=0x1 +phy_chain_tx_polarity_flip_physical{99}=0x0 +phy_chain_tx_polarity_flip_physical{100}=0x1 + +#FC25 QSFP port 24 +phy_chain_rx_polarity_flip_physical{101}=0x0 +phy_chain_rx_polarity_flip_physical{102}=0x1 +phy_chain_rx_polarity_flip_physical{103}=0x1 +phy_chain_rx_polarity_flip_physical{104}=0x0 + +phy_chain_tx_polarity_flip_physical{101}=0x1 +phy_chain_tx_polarity_flip_physical{102}=0x0 +phy_chain_tx_polarity_flip_physical{103}=0x0 +phy_chain_tx_polarity_flip_physical{104}=0x1 + +#FC26 QSFP port 27 +phy_chain_rx_polarity_flip_physical{105}=0x0 +phy_chain_rx_polarity_flip_physical{106}=0x0 +phy_chain_rx_polarity_flip_physical{107}=0x1 +phy_chain_rx_polarity_flip_physical{108}=0x1 + +phy_chain_tx_polarity_flip_physical{105}=0x1 +phy_chain_tx_polarity_flip_physical{106}=0x1 +phy_chain_tx_polarity_flip_physical{107}=0x0 +phy_chain_tx_polarity_flip_physical{108}=0x1 + +#FC27 QSFP port 26 +phy_chain_rx_polarity_flip_physical{109}=0x1 +phy_chain_rx_polarity_flip_physical{110}=0x0 +phy_chain_rx_polarity_flip_physical{111}=0x0 +phy_chain_rx_polarity_flip_physical{112}=0x1 + +phy_chain_tx_polarity_flip_physical{109}=0x1 +phy_chain_tx_polarity_flip_physical{110}=0x0 +phy_chain_tx_polarity_flip_physical{111}=0x0 +phy_chain_tx_polarity_flip_physical{112}=0x0 + +#FC28 QSFP port 29 +phy_chain_rx_polarity_flip_physical{113}=0x0 +phy_chain_rx_polarity_flip_physical{114}=0x1 +phy_chain_rx_polarity_flip_physical{115}=0x1 +phy_chain_rx_polarity_flip_physical{116}=0x0 + +phy_chain_tx_polarity_flip_physical{113}=0x1 +phy_chain_tx_polarity_flip_physical{114}=0x1 +phy_chain_tx_polarity_flip_physical{115}=0x0 +phy_chain_tx_polarity_flip_physical{116}=0x1 + +#FC29 QSFP port 28 +phy_chain_rx_polarity_flip_physical{117}=0x1 +phy_chain_rx_polarity_flip_physical{118}=0x0 +phy_chain_rx_polarity_flip_physical{119}=0x0 +phy_chain_rx_polarity_flip_physical{120}=0x1 + +phy_chain_tx_polarity_flip_physical{117}=0x1 +phy_chain_tx_polarity_flip_physical{118}=0x0 +phy_chain_tx_polarity_flip_physical{119}=0x0 +phy_chain_tx_polarity_flip_physical{120}=0x1 + +#FC30 QSFP port 31 +phy_chain_rx_polarity_flip_physical{121}=0x1 +phy_chain_rx_polarity_flip_physical{122}=0x1 +phy_chain_rx_polarity_flip_physical{123}=0x0 +phy_chain_rx_polarity_flip_physical{124}=0x0 + +phy_chain_tx_polarity_flip_physical{121}=0x1 +phy_chain_tx_polarity_flip_physical{122}=0x1 +phy_chain_tx_polarity_flip_physical{123}=0x0 +phy_chain_tx_polarity_flip_physical{124}=0x1 + +#FC31 QSFP port 30 +phy_chain_rx_polarity_flip_physical{125}=0x1 +phy_chain_rx_polarity_flip_physical{126}=0x0 +phy_chain_rx_polarity_flip_physical{127}=0x0 +phy_chain_rx_polarity_flip_physical{128}=0x1 + +phy_chain_tx_polarity_flip_physical{125}=0x0 +phy_chain_tx_polarity_flip_physical{126}=0x0 +phy_chain_tx_polarity_flip_physical{127}=0x1 +phy_chain_tx_polarity_flip_physical{128}=0x0 + +#MC +phy_chain_rx_polarity_flip_physical{129}=0x0 +phy_chain_rx_polarity_flip_physical{130}=0x0 +phy_chain_rx_polarity_flip_physical{131}=0x0 +phy_chain_rx_polarity_flip_physical{132}=0x0 + +phy_chain_tx_polarity_flip_physical{129}=0x0 +phy_chain_tx_polarity_flip_physical{130}=0x0 +phy_chain_tx_polarity_flip_physical{131}=0x0 +phy_chain_tx_polarity_flip_physical{132}=0x0 + + +#Portmap setting +#FC0 QSFP port 0 +portmap_1=1:100 + +#FC1 QSFP port 1 +portmap_5=5:100 + +#FC2 QSFP port 2 +portmap_9=9:100 + +#FC3 QSFP port 3 +portmap_13=13:100 + +#FC4 QSFP port 4 +portmap_17=17:100 + +#FC5 QSFP port 5 +portmap_21=21:100 + +#FC6 QSFP port 6 +portmap_25=25:100 + +#FC7 QSFP port 7 +portmap_29=29:100 + +#FC8 QSFP port 8 +portmap_33=33:100 + +#FC9 QSFP port 9 +portmap_37=37:100 + +#FC10 QSFP port 10 +portmap_41=41:100 + +#FC11 QSFP port 11 +portmap_45=45:100 + +#FC12 QSFP port 12 +portmap_49=49:100 + +#FC13 QSFP port 13 +portmap_53=53:100 + +#FC14 QSFP port 14 +portmap_57=57:100 + +#FC15 QSFP port 15 +portmap_61=61:100 + +#MC port 66 - management port (front port) +portmap_66=129:10:m + + +#FC16 QSFP port 17 +portmap_67=65:100 + +#FC17 QSFP port 16 +portmap_71=69:100 + +#FC18 QSFP port 19 +portmap_75=73:100 + +#FC19 QSFP port 18 +portmap_79=77:100 + +#FC20 QSFP port 21 +portmap_83=81:100 + +#FC21 QSFP port 20 +portmap_87=85:100 + +#FC22 QSFP port 23 +portmap_91=89:100 + +#FC23 QSFP port 22 +portmap_95=93:100 + +#FC24 QSFP port 25 +portmap_99=97:100 + +#FC25 QSFP port 24 +portmap_103=101:100 + +#FC26 QSFP port 27 +portmap_107=105:100 + +#FC27 QSFP port 26 +portmap_111=109:100 + +#FC28 QSFP port 29 +portmap_115=113:100 + +#FC29 QSFP port 28 +portmap_119=117:100 + +#FC30 QSFP port 31 +portmap_123=121:100 + +#FC31 QSFP port 30 +portmap_127=125:100 + + +dport_map_enable=1 + +dport_map_port_1=1 +dport_map_port_5=2 +dport_map_port_9=3 +dport_map_port_13=4 +dport_map_port_17=5 +dport_map_port_21=6 +dport_map_port_25=7 +dport_map_port_29=8 +dport_map_port_33=9 +dport_map_port_37=10 +dport_map_port_41=11 +dport_map_port_45=12 +dport_map_port_49=13 +dport_map_port_53=14 +dport_map_port_57=15 +dport_map_port_61=16 +dport_map_port_71=17 +dport_map_port_67=18 +dport_map_port_79=19 +dport_map_port_75=20 +dport_map_port_87=21 +dport_map_port_83=22 +dport_map_port_95=23 +dport_map_port_91=24 +dport_map_port_103=25 +dport_map_port_99=26 +dport_map_port_111=27 +dport_map_port_107=28 +dport_map_port_119=29 +dport_map_port_115=30 +dport_map_port_127=31 +dport_map_port_123=32 +dport_map_port_66=33 + + +core_clock_frequency=1525 +dpp_clock_ratio=2:3 +oversubscribe_mode=1 +parity_enable=0 +mem_cache_enable=0 +l2_mem_entries=32768 +l3_mem_entries=16384 +fpem_mem_entries=131072 +l2xmsg_mode=1 +bcm_num_cos=10 +bcm_stat_interval=2000000 +cdma_timeout_usec=3000000 +ipv6_lpm_128b_enable=0x1 +l3_max_ecmp_mode=1 +lpm_scaling_enable=0 +max_vp_lags=0 +miim_intr_enable=0 +module_64ports=1 +schan_intr_enable=0 +stable_size=0x5500000 +tdma_timeout_usec=3000000 +skip_L2_USER_ENTRY=0 +bcm_tunnel_term_compatible_mode=1 +ifp_inports_support_enable=1 +port_flex_enable=1 + + diff --git a/device/ufispace/x86_64-ufispace_s9110_32x-r0/custom_led.bin b/device/ufispace/x86_64-ufispace_s9110_32x-r0/custom_led.bin new file mode 100755 index 000000000000..82315db109ed Binary files /dev/null and b/device/ufispace/x86_64-ufispace_s9110_32x-r0/custom_led.bin differ diff --git a/device/ufispace/x86_64-ufispace_s9110_32x-r0/default_sku b/device/ufispace/x86_64-ufispace_s9110_32x-r0/default_sku new file mode 100644 index 000000000000..de055565f62a --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s9110_32x-r0/default_sku @@ -0,0 +1 @@ +UFISPACE-S9110-32X t1 diff --git a/device/ufispace/x86_64-ufispace_s9110_32x-r0/fancontrol b/device/ufispace/x86_64-ufispace_s9110_32x-r0/fancontrol new file mode 100644 index 000000000000..1234cd994f3f --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s9110_32x-r0/fancontrol @@ -0,0 +1,10 @@ +# Configuration file generated by pwmconfig, changes will be lost +INTERVAL=10 +DEVPATH= +DEVNAME= +FCTEMPS= +FCFANS= +MINTEMP= +MAXTEMP= +MINSTART= +MINSTOP= diff --git a/device/ufispace/x86_64-ufispace_s9110_32x-r0/installer.conf b/device/ufispace/x86_64-ufispace_s9110_32x-r0/installer.conf new file mode 100644 index 000000000000..8f9944da69a6 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s9110_32x-r0/installer.conf @@ -0,0 +1,4 @@ +CONSOLE_PORT=0x3f8 +CONSOLE_DEV=0 +CONSOLE_SPEED=115200 +ONIE_PLATFORM_EXTRA_CMDLINE_LINUX="module_blacklist=gpio_ich nomodeset pcie_aspm=off" diff --git a/device/ufispace/x86_64-ufispace_s9110_32x-r0/led_proc_init.soc b/device/ufispace/x86_64-ufispace_s9110_32x-r0/led_proc_init.soc new file mode 100755 index 000000000000..a65a2eac30ed --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s9110_32x-r0/led_proc_init.soc @@ -0,0 +1,4 @@ +led stop +m0 load 0 0x3800 /usr/share/sonic/platform/custom_led.bin +led auto on +led start diff --git a/device/ufispace/x86_64-ufispace_s9110_32x-r0/pcie.yaml b/device/ufispace/x86_64-ufispace_s9110_32x-r0/pcie.yaml new file mode 100644 index 000000000000..821972019ef5 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s9110_32x-r0/pcie.yaml @@ -0,0 +1,172 @@ +- bus: '00' + dev: '00' + fn: '0' + id: '1980' + name: 'Host bridge: Intel Corporation Atom Processor C3000 Series System Agent (rev + 11)' +- bus: '00' + dev: '04' + fn: '0' + id: 19a1 + name: 'Host bridge: Intel Corporation Atom Processor C3000 Series Error Registers + (rev 11)' +- bus: '00' + dev: '05' + fn: '0' + id: 19a2 + name: 'Generic system peripheral [0807]: Intel Corporation Atom Processor C3000 + Series Root Complex Event Collector (rev 11)' +- bus: '00' + dev: '06' + fn: '0' + id: 19a3 + name: 'PCI bridge: Intel Corporation Atom Processor C3000 Series Integrated QAT + Root Port (rev 11)' +- bus: '00' + dev: 09 + fn: '0' + id: 19a4 + name: 'PCI bridge: Intel Corporation Atom Processor C3000 Series PCI Express Root + Port #0 (rev 11)' +- bus: '00' + dev: 0a + fn: '0' + id: 19a5 + name: 'PCI bridge: Intel Corporation Atom Processor C3000 Series PCI Express Root + Port #1 (rev 11)' +- bus: '00' + dev: 0b + fn: '0' + id: 19a6 + name: 'PCI bridge: Intel Corporation Atom Processor C3000 Series PCI Express Root + Port #2 (rev 11)' +- bus: '00' + dev: 0e + fn: '0' + id: 19a8 + name: 'PCI bridge: Intel Corporation Atom Processor C3000 Series PCI Express Root + Port #4 (rev 11)' +- bus: '00' + dev: 0f + fn: '0' + id: 19a9 + name: 'PCI bridge: Intel Corporation Atom Processor C3000 Series PCI Express Root + Port #5 (rev 11)' +- bus: '00' + dev: '10' + fn: '0' + id: 19aa + name: 'PCI bridge: Intel Corporation Atom Processor C3000 Series PCI Express Root + Port #6 (rev 11)' +- bus: '00' + dev: '11' + fn: '0' + id: 19ab + name: 'PCI bridge: Intel Corporation Atom Processor C3000 Series PCI Express Root + Port #7 (rev 11)' +- bus: '00' + dev: '12' + fn: '0' + id: 19ac + name: 'System peripheral: Intel Corporation Atom Processor C3000 Series SMBus Contoller + - Host (rev 11)' +- bus: '00' + dev: '14' + fn: '0' + id: 19c2 + name: 'SATA controller: Intel Corporation Atom Processor C3000 Series SATA Controller + 1 (rev 11)' +- bus: '00' + dev: '15' + fn: '0' + id: 19d0 + name: 'USB controller: Intel Corporation Atom Processor C3000 Series USB 3.0 xHCI + Controller (rev 11)' +- bus: '00' + dev: '16' + fn: '0' + id: 19d1 + name: 'PCI bridge: Intel Corporation Atom Processor C3000 Series Integrated LAN + Root Port #0 (rev 11)' +- bus: '00' + dev: '17' + fn: '0' + id: 19d2 + name: 'PCI bridge: Intel Corporation Atom Processor C3000 Series Integrated LAN + Root Port #1 (rev 11)' +- bus: '00' + dev: '18' + fn: '0' + id: 19d3 + name: 'Communication controller: Intel Corporation Atom Processor C3000 Series ME + HECI 1 (rev 11)' +- bus: '00' + dev: 1c + fn: '0' + id: 19db + name: 'SD Host controller: Intel Corporation Device 19db (rev 11)' +- bus: '00' + dev: 1f + fn: '0' + id: 19dc + name: 'ISA bridge: Intel Corporation Atom Processor C3000 Series LPC or eSPI (rev + 11)' +- bus: '00' + dev: 1f + fn: '2' + id: 19de + name: 'Memory controller: Intel Corporation Atom Processor C3000 Series Power Management + Controller (rev 11)' +- bus: '00' + dev: 1f + fn: '4' + id: 19df + name: 'SMBus: Intel Corporation Atom Processor C3000 Series SMBus controller (rev + 11)' +- bus: '00' + dev: 1f + fn: '5' + id: 19e0 + name: 'Serial bus controller [0c80]: Intel Corporation Atom Processor C3000 Series + SPI Controller (rev 11)' +- bus: '01' + dev: '00' + fn: '0' + id: 19e2 + name: 'Co-processor: Intel Corporation Atom Processor C3000 Series QuickAssist Technology + (rev 11)' +- bus: '04' + dev: '00' + fn: '0' + id: b870 + name: 'Ethernet controller: Broadcom Inc. and subsidiaries Device b870 (rev 01)' +- bus: '06' + dev: '00' + fn: '0' + id: '1533' + name: 'Ethernet controller: Intel Corporation I210 Gigabit Network Connection (rev + 03)' +- bus: 09 + dev: '00' + fn: '0' + id: 15c3 + name: 'Ethernet controller: Intel Corporation Ethernet Connection X553 Backplane + (rev 11)' +- bus: 09 + dev: '00' + fn: '1' + id: 15c3 + name: 'Ethernet controller: Intel Corporation Ethernet Connection X553 Backplane + (rev 11)' +- bus: 0a + dev: '00' + fn: '0' + id: 15c3 + name: 'Ethernet controller: Intel Corporation Ethernet Connection X553 Backplane + (rev 11)' +- bus: 0a + dev: '00' + fn: '1' + id: 15c3 + name: 'Ethernet controller: Intel Corporation Ethernet Connection X553 Backplane + (rev 11)' diff --git a/device/ufispace/x86_64-ufispace_s9110_32x-r0/pddf/pd-plugin.json b/device/ufispace/x86_64-ufispace_s9110_32x-r0/pddf/pd-plugin.json new file mode 100644 index 000000000000..775f0c934f05 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s9110_32x-r0/pddf/pd-plugin.json @@ -0,0 +1,85 @@ +{ + + "XCVR": + { + "xcvr_present": + { + "i2c": + { + "valmap-SFP": {"1":true, "0":false }, + "valmap-QSFP-DD": {"1":true, "0":false}, + "valmap-QSFP": {"1":true, "0":false} + } + }, + "status": + { + "inserted": "1", + "removed": "0" + } + }, + + "PSU": + { + "psu_present": + { + "i2c": + { + "valmap": { "1":true, "0":false } + } + }, + + "psu_power_good": + { + "i2c": + { + "valmap": { "1": true, "0":false } + } + }, + + "psu_fan_dir": + { + "bmc": + { + "valmap": {"0": "UNKNOWN", "1":"INTAKE", "2":"EXHAUST"} + } + }, + "psu_support_list": + [ + {"Manufacturer": "FSPGROUP","Name": "YNEE0750EM", "MaxSpd": "PSU_AC_FAN_MAX_SPEED"}, + {"Manufacturer": "FSPGROUP","Name": "YNEE0750BM", "MaxSpd": "PSU_AC_FAN_MAX_SPEED"}, + {"Manufacturer": "FSPGROUP","Name": "YNEE0750AM", "MaxSpd": "PSU_DC_FAN_MAX_SPEED"} + ], + + "valmap": {"PSU_AC_FAN_MAX_SPEED": "26500", "PSU_DC_FAN_MAX_SPEED":"29000"} + }, + + "FAN": + { + "direction": + { + "bmc": + { + "valmap": {"0": "UNKNOWN", "1":"INTAKE", "2":"EXHAUST"} + } + }, + + "present": + { + "i2c": + { + "valmap": {"1":true, "0":false} + }, + "bmc": + { + "valmap": {"Device Present":true, "Device Absent":false} + } + }, + "FAN_R_MAX_SPEED":"32000", + "FAN_F_MAX_SPEED":"36200" + }, + + "REBOOT_CAUSE": + { + "reboot_cause_file": "/host/reboot-cause/reboot-cause.txt" + } +} diff --git a/device/ufispace/x86_64-ufispace_s9110_32x-r0/pddf/pddf-device-beta.json b/device/ufispace/x86_64-ufispace_s9110_32x-r0/pddf/pddf-device-beta.json new file mode 100644 index 000000000000..d55cf071f5c3 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s9110_32x-r0/pddf/pddf-device-beta.json @@ -0,0 +1,4629 @@ +{ + "PLATFORM": { + "num_psus": 2, + "num_fantrays": 4, + "num_fans_pertray": 2, + "num_ports": 33, + "num_temps": 7, + "pddf_dev_types": { + "description": "PDDF supported devices", + "CPLD": [ + "i2c_cpld" + ], + "PSU": [ + "psu_eeprom", + "psu_pmbus" + ], + "PORT_MODULE": [ + "pddf_xcvr" + ] + }, + "std_kos": [ + "i2c_i801", + "i2c-ismt", + "i2c_dev", + "i2c_mux_pca954x", + "optoe" + ], + "pddf_kos": [ + "pddf_client_module", + "pddf_cpld_module", + "pddf_cpld_driver", + "pddf_mux_module", + "pddf_xcvr_module", + "pddf_xcvr_driver_module", + "pddf_psu_driver_module", + "pddf_psu_module", + "pddf_fan_driver_module", + "pddf_fan_module", + "pddf_led_module" + ], + "custom_kos": [ + "x86-64-ufispace-s9110-32x-lpc", + "x86-64-ufispace-s9110-32x-sys-eeprom", + "pddf_custom_sysstatus_module" + ] + }, + "SYSTEM": { + "dev_info": { + "device_type": "CPU", + "device_name": "ROOT_COMPLEX", + "device_parent": null + }, + "i2c": { + "CONTROLLERS": [ + { + "dev_name": "i2c-1", + "dev": "SMBUS1" + }, + { + "dev_name": "i2c-0", + "dev": "SMBUS0" + } + ] + } + }, + "SMBUS1": { + "dev_info": { + "device_type": "SMBUS", "device_name": "SMBUS1", "device_parent": "SYSTEM" + }, + "i2c": { + "topo_info": { + "dev_addr": "0x1" + }, + "DEVICES": [ + { + "dev": "EEPROM1" + }, + { + "dev": "MUX1" + } + ] + } + }, + "EEPROM1": { + "dev_info": { + "device_type": "EEPROM", + "device_name": "EEPROM1", + "device_parent": "SMBUS1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1", + "dev_addr": "0x57", + "dev_type": "sys_eeprom" + }, + "dev_attr": { + "access_mode": "BLOCK" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "MUX1": { + "dev_info": { "device_type": "MUX", "device_name": "MUX1", "device_parent": "SMBUS1"}, + "i2c": { + "topo_info": { + "parent_bus": "0x1", + "dev_addr": "0x70", + "dev_type": "pca9548" + }, + "dev_attr": { + "virt_bus": "0x2", + "idle_state": "-2" + }, + "channel": [ + { + "chn": "0", + "dev": "CPLD1" + }, + { + "chn": "0", + "dev": "CPLD2" + }, + { + "chn": "0", + "dev": "PSU1" + }, + { + "chn": "0", + "dev": "PSU2" + } + ] + } + }, + "CPLD1": { + "dev_info": { + "device_type": "CPLD", + "device_name": "CPLD1", + "device_parent": "MUX1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2", + "dev_addr": "0x30", + "dev_type": "i2c_cpld" + }, + "dev_attr": {} + } + }, + "CPLD2": { + "dev_info": { + "device_type": "CPLD", + "device_name": "CPLD2", + "device_parent": "MUX1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2", + "dev_addr": "0x31", + "dev_type": "i2c_cpld" + }, + "dev_attr": {} + } + }, + "SMBUS0": { + "dev_info": { + "device_type": "SMBUS", "device_name": "SMBUS0", "device_parent": "SYSTEM" + }, + "i2c": { + "topo_info": { + "dev_addr": "0x0" + }, + "DEVICES": [ + { + "dev": "MUX2" + } + ] + } + }, + "MUX2": { + "dev_info": { "device_type":"MUX", "device_name":"MUX2", "device_parent":"SMBUS0"}, + "i2c": + { + "topo_info": { "parent_bus":"0x0", "dev_addr":"0x72", "dev_type":"pca9548"}, + "dev_attr": { "virt_bus":"0xa", "idle_state":"-2"}, + "channel": + [ + { "chn":"0", "dev":"MUX3" }, + { "chn":"1", "dev":"MUX4" }, + { "chn":"2", "dev":"MUX5" }, + { "chn":"3", "dev":"MUX6" }, + { "chn":"4", "dev":"MUX7" } + ] + } + }, + "MUX3": { + "dev_info": { "device_type":"MUX", "device_name":"MUX3", "device_parent":"MUX2"}, + "i2c": { + "topo_info": { "parent_bus":"0xa", "dev_addr":"0x73", "dev_type":"pca9548"}, + "dev_attr": { "virt_bus":"0x12", "idle_state":"-2"}, + "channel": [ + { "chn":"0", "dev":"PORT1" }, + { "chn":"1", "dev":"PORT2" }, + { "chn":"2", "dev":"PORT3" }, + { "chn":"3", "dev":"PORT4" }, + { "chn":"4", "dev":"PORT5" }, + { "chn":"5", "dev":"PORT6" }, + { "chn":"6", "dev":"PORT7" }, + { "chn":"7", "dev":"PORT8" } + ] + } + }, + "MUX4": { + "dev_info": { "device_type":"MUX", "device_name":"MUX4", "device_parent":"MUX2"}, + "i2c": { + "topo_info": { "parent_bus":"0xb", "dev_addr":"0x73", "dev_type":"pca9548"}, + "dev_attr": { "virt_bus":"0x1a", "idle_state":"-2"}, + "channel": [ + { "chn":"0", "dev":"PORT9" }, + { "chn":"1", "dev":"PORT10" }, + { "chn":"2", "dev":"PORT11" }, + { "chn":"3", "dev":"PORT12" }, + { "chn":"4", "dev":"PORT13" }, + { "chn":"5", "dev":"PORT14" }, + { "chn":"6", "dev":"PORT15" }, + { "chn":"7", "dev":"PORT16" } + ] + } + }, + "MUX5": { + "dev_info": { "device_type":"MUX", "device_name":"MUX5", "device_parent":"MUX2"}, + "i2c": { + "topo_info": { "parent_bus":"0xc", "dev_addr":"0x73", "dev_type":"pca9548"}, + "dev_attr": { "virt_bus":"0x22", "idle_state":"-2"}, + "channel": [ + { "chn":"0", "dev":"PORT17" }, + { "chn":"1", "dev":"PORT18" }, + { "chn":"2", "dev":"PORT19" }, + { "chn":"3", "dev":"PORT20" }, + { "chn":"4", "dev":"PORT21" }, + { "chn":"5", "dev":"PORT22" }, + { "chn":"6", "dev":"PORT23" }, + { "chn":"7", "dev":"PORT24" } + ] + } + }, + "MUX6": { + "dev_info": { "device_type":"MUX", "device_name":"MUX6", "device_parent":"MUX2"}, + "i2c": { + "topo_info": { "parent_bus":"0xd", "dev_addr":"0x73", "dev_type":"pca9548"}, + "dev_attr": { "virt_bus":"0x2a", "idle_state":"-2"}, + "channel": [ + { "chn":"0", "dev":"PORT25" }, + { "chn":"1", "dev":"PORT26" }, + { "chn":"2", "dev":"PORT27" }, + { "chn":"3", "dev":"PORT28" }, + { "chn":"4", "dev":"PORT29" }, + { "chn":"5", "dev":"PORT30" }, + { "chn":"6", "dev":"PORT31" }, + { "chn":"7", "dev":"PORT32" } + ] + } + }, + "MUX7": { + "dev_info": { "device_type":"MUX", "device_name":"MUX7", "device_parent":"MUX2"}, + "i2c": { + "topo_info": { "parent_bus":"0xe", "dev_addr":"0x73", "dev_type":"pca9548"}, + "dev_attr": { "virt_bus":"0x32", "idle_state":"-2"}, + "channel": [ + { "chn":"1", "dev":"PORT33" } + ] + } + }, + "TEMP1": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TEMP1", + "device_parent": "SMBUS0" + }, + "dev_attr": { + "display_name": "TEMP_MAC" + }, + "bmc": { + "ipmitool": { + "attr_list": [ + { + "attr_name": "temp1_input", + "bmc_cmd": "ipmitool sdr get -c TEMP_MAC", + "raw": "0", + "separator": ",", + "field_name": "TEMP_MAC", + "field_pos": "2" + }, + { + "attr_name": "temp1_high_threshold", + "bmc_cmd": "ipmitool sdr get -c TEMP_MAC", + "raw": "0", + "separator": ",", + "field_name": "TEMP_MAC", + "field_pos": "13" + }, + { + "attr_name": "temp1_high_crit_threshold", + "bmc_cmd": "ipmitool sdr get -c TEMP_MAC", + "raw": "0", + "separator": ",", + "field_name": "TEMP_MAC", + "field_pos": "12" + } + ] + } + } + }, + "TEMP2": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TEMP2", + "device_parent": "SMBUS0" + }, + "dev_attr": { + "display_name": "TEMP_ENV_MACCASE" + }, + "bmc": { + "ipmitool": { + "attr_list": [ + { + "attr_name": "temp1_input", + "bmc_cmd": "ipmitool sdr get -c TEMP_ENV_MACCASE", + "raw": "0", + "separator": ",", + "field_name": "TEMP_ENV_MACCASE", + "field_pos": "2" + }, + { + "attr_name": "temp1_high_threshold", + "bmc_cmd": "ipmitool sdr get -c TEMP_ENV_MACCASE", + "raw": "0", + "separator": ",", + "field_name": "TEMP_ENV_MACCASE", + "field_pos": "13" + }, + { + "attr_name": "temp1_high_crit_threshold", + "bmc_cmd": "ipmitool sdr get -c TEMP_ENV_MACCASE", + "raw": "0", + "separator": ",", + "field_name": "TEMP_ENV_MACCASE", + "field_pos": "12" + } + ] + } + } + }, + "TEMP3": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TEMP3", + "device_parent": "SMBUS0" + }, + "dev_attr": { + "display_name": "TEMP_ENV_SSDCASE" + }, + "bmc": { + "ipmitool": { + "attr_list": [ + { + "attr_name": "temp1_input", + "bmc_cmd": "ipmitool sdr get -c TEMP_ENV_SSDCASE", + "raw": "0", + "separator": ",", + "field_name": "TEMP_ENV_SSDCASE", + "field_pos": "2" + }, + { + "attr_name": "temp1_high_threshold", + "bmc_cmd": "ipmitool sdr get -c TEMP_ENV_SSDCASE", + "raw": "0", + "separator": ",", + "field_name": "TEMP_ENV_SSDCASE", + "field_pos": "13" + }, + { + "attr_name": "temp1_high_crit_threshold", + "bmc_cmd": "ipmitool sdr get -c TEMP_ENV_SSDCASE", + "raw": "0", + "separator": ",", + "field_name": "TEMP_ENV_SSDCASE", + "field_pos": "12" + } + ] + } + } + }, + "TEMP4": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TEMP4", + "device_parent": "SMBUS0" + }, + "dev_attr": { + "display_name": "TEMP_ENV_PSUCASE" + }, + "bmc": { + "ipmitool": { + "attr_list": [ + { + "attr_name": "temp1_input", + "bmc_cmd": "ipmitool sdr get -c TEMP_ENV_PSUCASE", + "raw": "0", + "separator": ",", + "field_name": "TEMP_ENV_PSUCASE", + "field_pos": "2" + }, + { + "attr_name": "temp1_high_threshold", + "bmc_cmd": "ipmitool sdr get -c TEMP_ENV_PSUCASE", + "raw": "0", + "separator": ",", + "field_name": "TEMP_ENV_PSUCASE", + "field_pos": "13" + }, + { + "attr_name": "temp1_high_crit_threshold", + "bmc_cmd": "ipmitool sdr get -c TEMP_ENV_PSUCASE", + "raw": "0", + "separator": ",", + "field_name": "TEMP_ENV_PSUCASE", + "field_pos": "12" + } + ] + } + } + }, + "TEMP5": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TEMP5", + "device_parent": "SMBUS0" + }, + "dev_attr": { + "display_name": "TEMP_ENV_BMC" + }, + "bmc": { + "ipmitool": { + "attr_list": [ + { + "attr_name": "temp1_input", + "bmc_cmd": "ipmitool sdr get -c TEMP_ENV_BMC", + "raw": "0", + "separator": ",", + "field_name": "TEMP_ENV_BMC", + "field_pos": "2" + }, + { + "attr_name": "temp1_high_threshold", + "bmc_cmd": "ipmitool sdr get -c TEMP_ENV_BMC", + "raw": "0", + "separator": ",", + "field_name": "TEMP_ENV_BMC", + "field_pos": "13" + }, + { + "attr_name": "temp1_high_crit_threshold", + "bmc_cmd": "ipmitool sdr get -c TEMP_ENV_BMC", + "raw": "0", + "separator": ",", + "field_name": "TEMP_ENV_BMC", + "field_pos": "12" + } + ] + } + } + }, + "TEMP6": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TEMP6", + "device_parent": "SMBUS0" + }, + "dev_attr": { + "display_name": "TEMP_PSU0_TEMP1" + }, + "bmc": { + "ipmitool": { + "attr_list": [ + { + "attr_name": "temp1_input", + "bmc_cmd": "ipmitool sdr get -c PSU0_TEMP1 | sed -e 's/,,/,0,/g' -e 's/,,/,0,/g'", + "raw": "0", + "separator": ",", + "field_name": "PSU0_TEMP1", + "field_pos": "2" + }, + { + "attr_name": "temp1_high_threshold", + "bmc_cmd": "ipmitool sdr get -c PSU0_TEMP1", + "raw": "0", + "separator": ",", + "field_name": "PSU0_TEMP1", + "field_pos": "13" + }, + { + "attr_name": "temp1_high_crit_threshold", + "bmc_cmd": "ipmitool sdr get -c PSU0_TEMP1", + "raw": "0", + "separator": ",", + "field_name": "PSU0_TEMP1", + "field_pos": "12" + } + ] + } + } + }, + "TEMP7": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TEMP7", + "device_parent": "SMBUS0" + }, + "dev_attr": { + "display_name": "TEMP_PSU1_TEMP1" + }, + "bmc": { + "ipmitool": { + "attr_list": [ + { + "attr_name": "temp1_input", + "bmc_cmd": "ipmitool sdr get -c PSU1_TEMP1 | sed -e 's/,,/,0,/g' -e 's/,,/,0,/g'", + "raw": "0", + "separator": ",", + "field_name": "PSU1_TEMP1", + "field_pos": "2" + }, + { + "attr_name": "temp1_high_threshold", + "bmc_cmd": "ipmitool sdr get -c PSU1_TEMP1", + "raw": "0", + "separator": ",", + "field_name": "PSU1_TEMP1", + "field_pos": "13" + }, + { + "attr_name": "temp1_high_crit_threshold", + "bmc_cmd": "ipmitool sdr get -c PSU1_TEMP1", + "raw": "0", + "separator": ",", + "field_name": "PSU1_TEMP1", + "field_pos": "12" + } + ] + } + } + }, + "SYSSTATUS": { + "dev_info": { + "device_type": "SYSSTAT", + "device_name": "SYSSTATUS" + }, + "dev_attr": {}, + "attr_list": + [ + { + "attr_name": "board_sku_id", + "attr_devaddr": "0x30", + "attr_offset": "0x0", + "attr_mask": "0xff", + "attr_len": "0x1" + }, + { + "attr_name": "board_hw_id", + "attr_devaddr": "0x30", + "attr_offset": "0x1", + "attr_mask": "0x03", + "attr_len": "0x1" + }, + { + "attr_name": "board_deph_id", + "attr_devaddr": "0x30", + "attr_offset": "0x1", + "attr_mask": "0x4", + "attr_len": "0x1" + }, + { + "attr_name": "board_build_id", + "attr_devaddr": "0x30", + "attr_offset": "0x1", + "attr_mask": "0x18", + "attr_len": "0x1" + }, + { + "attr_name": "cpld1_major_ver", + "attr_devaddr": "0x30", + "attr_offset": "0x2", + "attr_mask": "0xc0", + "attr_len": "0x1" + }, + { + "attr_name": "cpld1_minor_ver", + "attr_devaddr": "0x30", + "attr_offset": "0x2", + "attr_mask": "0x3f", + "attr_len": "0x1" + }, + { + "attr_name": "cpld1_build", + "attr_devaddr": "0x30", + "attr_offset": "0x4", + "attr_mask": "0xff", + "attr_len": "0x1" + }, + { + "attr_name": "cpld2_major_ver", + "attr_devaddr": "0x31", + "attr_offset": "0x2", + "attr_mask": "0xc0", + "attr_len": "0x1" + }, + { + "attr_name": "cpld2_minor_ver", + "attr_devaddr": "0x31", + "attr_offset": "0x2", + "attr_mask": "0x3f", + "attr_len": "0x1" + }, + { + "attr_name": "cpld2_build", + "attr_devaddr": "0x31", + "attr_offset": "0x4", + "attr_mask": "0xff", + "attr_len": "0x1" + }, + { + "attr_name": "psu_status", + "attr_devaddr": "0x30", + "attr_offset": "0x51", + "attr_mask": "0xff", + "attr_len": "0x1" + }, + { + "attr_name": "system_led_psu", + "attr_devaddr": "0x30", + "attr_offset": "0x80", + "attr_mask": "0xff", + "attr_len": "0x1" + }, + { + "attr_name": "system_led_sys", + "attr_devaddr": "0x30", + "attr_offset": "0x81", + "attr_mask": "0xff", + "attr_len": "0x1" + }, + { + "attr_name": "system_led_fan", + "attr_devaddr": "0x30", + "attr_offset": "0x83", + "attr_mask": "0xff", + "attr_len": "0x1" + }, + { + "attr_name": "system_led_id", + "attr_devaddr": "0x30", + "attr_offset": "0x84", + "attr_mask": "0xff", + "attr_len": "0x1" + } + ] + }, + "PSU1": { + "dev_info": { + "device_type": "PSU", + "device_name": "PSU1", + "device_parent": "MUX1" + }, + "dev_attr": { + "dev_idx": "1", + "num_psu_fans": "1" + }, + "i2c": { + "interface": [ + { "itf":"eeprom", "dev":"PSU1-EEPROM" } + ] + }, + "bmc": { + "ipmitool": { + "attr_list": + [ + { + "attr_name": "psu_v_out", + "bmc_cmd": "ipmitool sdr get -c PSU0_VOUT | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "separator": ",", + "field_name": "PSU0_VOUT", + "field_pos": "2", + "mult": "1000" + }, + { + "attr_name": "psu_i_out", + "bmc_cmd": "ipmitool sdr get -c PSU0_IOUT | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "separator": ",", + "field_name": "PSU0_IOUT", + "field_pos": "2", + "mult": "1000" + }, + { + "attr_name": "psu_temp1_input", + "bmc_cmd": "ipmitool sdr get -c PSU0_TEMP1 | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "separator": ",", + "field_name": "PSU0_TEMP1", + "field_pos": "2", + "mult": "1000" + }, + { + "attr_name": "psu_fan1_speed_rpm", + "bmc_cmd": "ipmitool sdr get -c PSU0_FAN1 | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "separator": ",", + "field_name": "PSU0_FAN1", + "field_pos": "2" + }, + { + "attr_name": "psu_mfr_id", + "bmc_cmd": "_rv=$(ipmitool fru print 1 2>/dev/null | tr -s ' ' | cut -d' ' -f3-5 | grep 'Manufacturer') && echo $_rv || echo 'Manufacturer : N/A'", + "raw": "0", + "separator": ":", + "field_name": "Manufacturer", + "field_pos": "2" + }, + { + "attr_name": "psu_model_name", + "bmc_cmd": "_rv=$(ipmitool fru print 1 2>/dev/null | tr -s ' ' | cut -d' ' -f3-5 | grep 'Name') && echo $_rv || echo 'Name : N/A'", + "raw": "0", + "separator": ":", + "field_name": "Name", + "field_pos": "2" + }, + { + "attr_name": "psu_serial_num", + "bmc_cmd": "_rv=$(ipmitool fru print 1 2>/dev/null | tr -s ' ' | cut -d' ' -f3-5 | grep 'Serial') && echo $_rv || echo 'Serial : N/A'", + "raw": "0", + "separator": ":", + "field_name": "Serial", + "field_pos": "2" + }, + { + "attr_name": "psu_fan_dir", + "bmc_cmd": "ipmitool raw 0x3c 0x30 0x0 | xargs | cut -d' ' -f1", + "raw": "1", + "type": "raw" + } + ] + } + } + }, + "PSU1-EEPROM": { + "dev_info": { + "device_type": "PSU-EEPROM", + "device_name": "PSU1-EEPROM", + "device_parent": "MUX1", + "virt_parent": "PSU1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2", + "dev_addr": "0x5a", + "dev_type": "psu_eeprom" + }, + "attr_list": [ + { + "attr_name":"psu_present", + "attr_devaddr":"0x30", + "attr_devtype":"cpld", + "attr_offset":"0x51", + "attr_mask":"0x1", + "attr_cmpval":"0x0", + "attr_len":"1" + }, + { + "attr_name":"psu_power_good", + "attr_devaddr":"0x30", + "attr_devtype":"cpld", + "attr_offset":"0x51", + "attr_mask":"0x10", + "attr_cmpval":"0x10", + "attr_len":"1" + } + ] + } + }, + "PSU2": { + "dev_info": { + "device_type": "PSU", + "device_name": "PSU2", + "device_parent": "MUX1" + }, + "dev_attr": { + "dev_idx": "2", + "num_psu_fans": "1" + }, + "i2c": { + "interface": [ + { "itf":"eeprom", "dev":"PSU2-EEPROM" } + ] + }, + "bmc": { + "ipmitool": { + "attr_list": + [ + { + "attr_name": "psu_v_out", + "bmc_cmd": "ipmitool sdr get -c PSU1_VOUT | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "separator": ",", + "field_name": "PSU1_VOUT", + "field_pos": "2", + "mult": "1000" + }, + { + "attr_name": "psu_i_out", + "bmc_cmd": "ipmitool sdr get -c PSU1_IOUT | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "separator": ",", + "field_name": "PSU1_IOUT", + "field_pos": "2", + "mult": "1000" + }, + { + "attr_name": "psu_temp1_input", + "bmc_cmd": "ipmitool sdr get -c PSU1_TEMP1 | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "separator": ",", + "field_name": "PSU1_TEMP1", + "field_pos": "2", + "mult": "1000" + }, + { + "attr_name": "psu_fan1_speed_rpm", + "bmc_cmd": "ipmitool sdr get -c PSU1_FAN1 | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "separator": ",", + "field_name": "PSU1_FAN1", + "field_pos": "2" + }, + { + "attr_name": "psu_mfr_id", + "bmc_cmd": "_rv=$(ipmitool fru print 2 2>/dev/null | tr -s ' ' | cut -d' ' -f3-5 | grep 'Manufacturer') && echo $_rv || echo 'Manufacturer : N/A'", + "raw": "0", + "separator": ":", + "field_name": "Manufacturer", + "field_pos": "2" + }, + { + "attr_name": "psu_model_name", + "bmc_cmd": "_rv=$(ipmitool fru print 2 2>/dev/null | tr -s ' ' | cut -d' ' -f3-5 | grep 'Name') && echo $_rv || echo 'Name : N/A'", + "raw": "0", + "separator": ":", + "field_name": "Name", + "field_pos": "2" + }, + { + "attr_name": "psu_serial_num", + "bmc_cmd": "_rv=$(ipmitool fru print 2 2>/dev/null | tr -s ' ' | cut -d' ' -f3-5 | grep 'Serial') && echo $_rv || echo 'Serial : N/A'", + "raw": "0", + "separator": ":", + "field_name": "Serial", + "field_pos": "2" + }, + { + "attr_name": "psu_fan_dir", + "bmc_cmd": "ipmitool raw 0x3c 0x30 0x0 | xargs | cut -d' ' -f2", + "raw": "1", + "type": "raw" + } + ] + } + } + }, + "PSU2-EEPROM": { + "dev_info": { + "device_type": "PSU-EEPROM", + "device_name": "PSU2-EEPROM", + "device_parent": "MUX1", + "virt_parent": "PSU2" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2", + "dev_addr": "0x5b", + "dev_type": "psu_eeprom" + }, + "attr_list": [ + { + "attr_name":"psu_present", + "attr_devaddr":"0x30", + "attr_devtype":"cpld", + "attr_offset":"0x51", + "attr_mask":"0x2", + "attr_cmpval":"0x0", + "attr_len":"1" + }, + { + "attr_name":"psu_power_good", + "attr_devaddr":"0x30", + "attr_devtype":"cpld", + "attr_offset":"0x51", + "attr_mask":"0x20", + "attr_cmpval":"0x20", + "attr_len":"1" + } + ] + } + }, + "FAN-CTRL": { + "dev_info": { + "device_type": "FAN", + "device_name": "FAN-CTRL", + "device_parent": "" + }, + "bmc": { + "ipmitool": { + "attr_list": [ + { + "attr_name": "fan1_present", + "bmc_cmd": "ipmitool sdr get -c FAN0_PRSNT_L", + "raw": "0", + "separator": ",", + "field_name": "FAN0_PRSNT_L", + "field_pos": "5" + }, + { + "attr_name": "fan2_present", + "bmc_cmd": "ipmitool sdr get -c FAN0_PRSNT_L", + "raw": "0", + "separator": ",", + "field_name": "FAN0_PRSNT_L", + "field_pos": "5" + }, + { + "attr_name": "fan3_present", + "bmc_cmd": "ipmitool sdr get -c FAN1_PRSNT_L", + "raw": "0", + "separator": ",", + "field_name": "FAN1_PRSNT_L", + "field_pos": "5" + }, + { + "attr_name": "fan4_present", + "bmc_cmd": "ipmitool sdr get -c FAN1_PRSNT_L", + "raw": "0", + "separator": ",", + "field_name": "FAN1_PRSNT_L", + "field_pos": "5" + }, + { + "attr_name": "fan5_present", + "bmc_cmd": "ipmitool sdr get -c FAN2_PRSNT_L", + "raw": "0", + "separator": ",", + "field_name": "FAN2_PRSNT_L", + "field_pos": "5" + }, + { + "attr_name": "fan6_present", + "bmc_cmd": "ipmitool sdr get -c FAN2_PRSNT_L", + "raw": "0", + "separator": ",", + "field_name": "FAN2_PRSNT_L", + "field_pos": "5" + }, + { + "attr_name": "fan7_present", + "bmc_cmd": "ipmitool sdr get -c FAN3_PRSNT_L", + "raw": "0", + "separator": ",", + "field_name": "FAN3_PRSNT_L", + "field_pos": "5" + }, + { + "attr_name": "fan8_present", + "bmc_cmd": "ipmitool sdr get -c FAN3_PRSNT_L", + "raw": "0", + "separator": ",", + "field_name": "FAN3_PRSNT_L", + "field_pos": "5" + }, + { + "attr_name": "fan1_input", + "bmc_cmd": "ipmitool sdr get -c FAN0_RPM_F | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "separator": ",", + "field_name": "FAN0_RPM_F", + "field_pos": "2" + }, + { + "attr_name": "fan2_input", + "bmc_cmd": "ipmitool sdr get -c FAN0_RPM_R | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "separator": ",", + "field_name": "FAN0_RPM_R", + "field_pos": "2" + }, + { + "attr_name": "fan3_input", + "bmc_cmd": "ipmitool sdr get -c FAN1_RPM_F | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "separator": ",", + "field_name": "FAN1_RPM_F", + "field_pos": "2" + }, + { + "attr_name": "fan4_input", + "bmc_cmd": "ipmitool sdr get -c FAN1_RPM_R | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "separator": ",", + "field_name": "FAN1_RPM_R", + "field_pos": "2" + }, + { + "attr_name": "fan5_input", + "bmc_cmd": "ipmitool sdr get -c FAN2_RPM_F | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "separator": ",", + "field_name": "FAN2_RPM_F", + "field_pos": "2" + }, + { + "attr_name": "fan6_input", + "bmc_cmd": "ipmitool sdr get -c FAN2_RPM_R | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "separator": ",", + "field_name": "FAN2_RPM_R", + "field_pos": "2" + }, + { + "attr_name": "fan7_input", + "bmc_cmd": "ipmitool sdr get -c FAN3_RPM_F | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "separator": ",", + "field_name": "FAN3_RPM_F", + "field_pos": "2" + }, + { + "attr_name": "fan8_input", + "bmc_cmd": "ipmitool sdr get -c FAN3_RPM_R | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "separator": ",", + "field_name": "FAN3_RPM_R", + "field_pos": "2" + }, + { + "attr_name": "fan1_direction", + "bmc_cmd": "ipmitool raw 0x3c 0x31 0x0 | xargs | cut -d' ' -f1", + "raw": "1", + "type": "raw" + }, + { + "attr_name": "fan2_direction", + "bmc_cmd": "ipmitool raw 0x3c 0x31 0x0 | xargs | cut -d' ' -f1", + "raw": "1", + "type": "raw" + }, + { + "attr_name": "fan3_direction", + "bmc_cmd": "ipmitool raw 0x3c 0x31 0x0 | xargs | cut -d' ' -f2", + "raw": "1", + "type": "raw" + }, + { + "attr_name": "fan4_direction", + "bmc_cmd": "ipmitool raw 0x3c 0x31 0x0 | xargs | cut -d' ' -f2", + "raw": "1", + "type": "raw" + }, + { + "attr_name": "fan5_direction", + "bmc_cmd": "ipmitool raw 0x3c 0x31 0x0 | xargs | cut -d' ' -f3", + "raw": "1", + "type": "raw" + }, + { + "attr_name": "fan6_direction", + "bmc_cmd": "ipmitool raw 0x3c 0x31 0x0 | xargs | cut -d' ' -f3", + "raw": "1", + "type": "raw" + }, + { + "attr_name": "fan7_direction", + "bmc_cmd": "ipmitool raw 0x3c 0x31 0x0 | xargs | cut -d' ' -f4", + "raw": "1", + "type": "raw" + }, + { + "attr_name": "fan8_direction", + "bmc_cmd": "ipmitool raw 0x3c 0x31 0x0 | xargs | cut -d' ' -f4", + "raw": "1", + "type": "raw" + } + ] + } + } + }, + "SYS_LED": { + "dev_info": { + "device_type": "LED", + "device_name": "SYS_LED" + }, + "dev_attr": { + "index": "0", + "flag": "rw" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "green", + "bits": "7:4", + "descr": "Green", + "value": "0x09;0x0b", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x81" + }, + { + "attr_name": "green_blink", + "bits": "7:4", + "descr": "Green Blinking", + "value": "0x0d;0x0f", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x81" + }, + { + "attr_name": "yellow", + "bits": "7:4", + "descr": "Yellow", + "value": "0x08;0x0a", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x81" + }, + { + "attr_name": "yellow_blink", + "bits": "7:4", + "descr": "Yellow Blinking", + "value": "0x0c;0x0e", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x81" + }, + { + "attr_name": "off", + "bits": "7:6", + "descr": "Off", + "value": "0x01;0x0", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x81" + } + ] + } + }, + "FAN_LED": { + "dev_info": { + "device_type": "LED", + "device_name": "FAN_LED" + }, + "dev_attr": { + "index": "0", + "flag": "ro" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "green", + "bits": "3:0", + "descr": "Green", + "value": "0x09;0x0b", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x83" + }, + { + "attr_name": "green_blink", + "bits": "3:0", + "descr": "Green Blinking", + "value": "0x0d;0x0f", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x83" + }, + { + "attr_name": "yellow", + "bits": "3:0", + "descr": "Yellow", + "value": "0x08;0x0a", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x83" + }, + { + "attr_name": "yellow_blink", + "bits": "3:0", + "descr": "Yellow Blinking", + "value": "0x0c;0x0e", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x83" + }, + { + "attr_name": "off", + "bits": "3", + "descr": "Off", + "value": "0x0", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x83" + } + ] + } + }, + "PSU1_LED": { + "dev_info": { + "device_type": "LED", + "device_name": "PSU_LED" + }, + "dev_attr": { + "index": "0", + "flag": "ro" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "green", + "bits": "3:0", + "descr": "Green", + "value": "0x09;0x0b", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x80" + }, + { + "attr_name": "green_blink", + "bits": "3:0", + "descr": "Green Blinking", + "value": "0x0d;0x0f", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x80" + }, + { + "attr_name": "yellow", + "bits": "3:0", + "descr": "Yellow", + "value": "0x08;0x0a", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x80" + }, + { + "attr_name": "yellow_blink", + "bits": "3:0", + "descr": "Yellow Blinking", + "value": "0x0c;0x0e", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x80" + }, + { + "attr_name": "off", + "bits": "3", + "descr": "Off", + "value": "0x0", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x80" + } + ] + } + }, + "PSU2_LED": { + "dev_info": { + "device_type": "LED", + "device_name": "PSU_LED" + }, + "dev_attr": { + "index": "1", + "flag": "ro" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "green", + "bits": "7:4", + "descr": "Green", + "value": "0x09;0x0b", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x80" + }, + { + "attr_name": "green_blink", + "bits": "7:4", + "descr": "Green Blinking", + "value": "0x0d;0x0f", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x80" + }, + { + "attr_name": "yellow", + "bits": "7:4", + "descr": "Yellow", + "value": "0x08;0x0a", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x80" + }, + { + "attr_name": "yellow_blink", + "bits": "7:4", + "descr": "Yellow Blinking", + "value": "0x0c;0x0e", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x80" + }, + { + "attr_name": "off", + "bits": "7", + "descr": "Off", + "value": "0x0", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x80" + } + ] + } + }, + "ID_LED": { + "dev_info": { + "device_type": "LED", + "device_name": "LOC_LED" + }, + "dev_attr": { + "index": "0", + "flag": "rw" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "blue", + "bits": "3:1", + "descr": "Blue", + "value": "0x04;0x05", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x84" + }, + { + "attr_name": "blue_blink", + "bits": "3:1", + "descr": "Blue Blinking", + "value": "0x06;0x07", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x84" + }, + { + "attr_name": "off", + "bits": "3:2", + "descr": "Off", + "value": "0x01;0x0", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x84" + } + ] + } + }, + "PORT1": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT1", + "device_parent": "MUX3" + }, + "dev_attr": { + "dev_idx": "1" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT1-EEPROM" + }, + { + "itf": "control", + "dev": "PORT1-CTRL" + } + ] + } + }, + "PORT1-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT1-EEPROM", + "device_parent": "MUX3", + "virt_parent": "PORT1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x12", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT1-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT1-CTRL", + "device_parent": "MUX3", + "virt_parent": "PORT1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x12", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x14", + "attr_mask": "0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x10", + "attr_mask": "0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x40", + "attr_mask": "0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x44", + "attr_mask": "0", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT2": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT2", + "device_parent": "MUX3" + }, + "dev_attr": { + "dev_idx": "2" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT2-EEPROM" + }, + { + "itf": "control", + "dev": "PORT2-CTRL" + } + ] + } + }, + "PORT2-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT2-EEPROM", + "device_parent": "MUX3", + "virt_parent": "PORT2" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x13", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT2-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT2-CTRL", + "device_parent": "MUX3", + "virt_parent": "PORT2" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x13", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x14", + "attr_mask": "1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x10", + "attr_mask": "1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x40", + "attr_mask": "1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x44", + "attr_mask": "1", + "attr_cmpval": "0x2", + "attr_len": "1" + } + ] + } + }, + "PORT3": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT3", + "device_parent": "MUX3" + }, + "dev_attr": { + "dev_idx": "3" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT3-EEPROM" + }, + { + "itf": "control", + "dev": "PORT3-CTRL" + } + ] + } + }, + "PORT3-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT3-EEPROM", + "device_parent": "MUX3", + "virt_parent": "PORT3" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x14", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT3-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT3-CTRL", + "device_parent": "MUX3", + "virt_parent": "PORT3" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x14", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x14", + "attr_mask": "2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x10", + "attr_mask": "2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x40", + "attr_mask": "2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x44", + "attr_mask": "2", + "attr_cmpval": "0x4", + "attr_len": "1" + } + ] + } + }, + "PORT4": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT4", + "device_parent": "MUX3" + }, + "dev_attr": { + "dev_idx": "4" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT4-EEPROM" + }, + { + "itf": "control", + "dev": "PORT4-CTRL" + } + ] + } + }, + "PORT4-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT4-EEPROM", + "device_parent": "MUX3", + "virt_parent": "PORT4" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x15", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT4-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT4-CTRL", + "device_parent": "MUX3", + "virt_parent": "PORT4" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x15", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x14", + "attr_mask": "3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x10", + "attr_mask": "3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x40", + "attr_mask": "3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x44", + "attr_mask": "3", + "attr_cmpval": "0x8", + "attr_len": "1" + } + ] + } + }, + "PORT5": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT5", + "device_parent": "MUX3" + }, + "dev_attr": { + "dev_idx": "5" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT5-EEPROM" + }, + { + "itf": "control", + "dev": "PORT5-CTRL" + } + ] + } + }, + "PORT5-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT5-EEPROM", + "device_parent": "MUX3", + "virt_parent": "PORT5" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x16", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT5-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT5-CTRL", + "device_parent": "MUX3", + "virt_parent": "PORT5" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x16", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x14", + "attr_mask": "4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x10", + "attr_mask": "4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x40", + "attr_mask": "4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x44", + "attr_mask": "4", + "attr_cmpval": "0x10", + "attr_len": "1" + } + ] + } + }, + "PORT6": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT6", + "device_parent": "MUX3" + }, + "dev_attr": { + "dev_idx": "6" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT6-EEPROM" + }, + { + "itf": "control", + "dev": "PORT6-CTRL" + } + ] + } + }, + "PORT6-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT6-EEPROM", + "device_parent": "MUX3", + "virt_parent": "PORT6" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x17", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT6-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT6-CTRL", + "device_parent": "MUX3", + "virt_parent": "PORT6" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x17", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x14", + "attr_mask": "5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x10", + "attr_mask": "5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x40", + "attr_mask": "5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x44", + "attr_mask": "5", + "attr_cmpval": "0x20", + "attr_len": "1" + } + ] + } + }, + "PORT7": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT7", + "device_parent": "MUX3" + }, + "dev_attr": { + "dev_idx": "7" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT7-EEPROM" + }, + { + "itf": "control", + "dev": "PORT7-CTRL" + } + ] + } + }, + "PORT7-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT7-EEPROM", + "device_parent": "MUX3", + "virt_parent": "PORT7" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x18", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT7-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT7-CTRL", + "device_parent": "MUX3", + "virt_parent": "PORT7" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x18", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x14", + "attr_mask": "6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x10", + "attr_mask": "6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x40", + "attr_mask": "6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x44", + "attr_mask": "6", + "attr_cmpval": "0x40", + "attr_len": "1" + } + ] + } + }, + "PORT8": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT8", + "device_parent": "MUX3" + }, + "dev_attr": { + "dev_idx": "8" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT8-EEPROM" + }, + { + "itf": "control", + "dev": "PORT8-CTRL" + } + ] + } + }, + "PORT8-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT8-EEPROM", + "device_parent": "MUX3", + "virt_parent": "PORT8" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x19", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT8-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT8-CTRL", + "device_parent": "MUX3", + "virt_parent": "PORT8" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x19", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x14", + "attr_mask": "7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x10", + "attr_mask": "7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x40", + "attr_mask": "7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x44", + "attr_mask": "7", + "attr_cmpval": "0x80", + "attr_len": "1" + } + ] + } + }, + "PORT9": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT9", + "device_parent": "MUX4" + }, + "dev_attr": { + "dev_idx": "9" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT9-EEPROM" + }, + { + "itf": "control", + "dev": "PORT9-CTRL" + } + ] + } + }, + "PORT9-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT9-EEPROM", + "device_parent": "MUX4", + "virt_parent": "PORT9" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1A", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT9-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT9-CTRL", + "device_parent": "MUX4", + "virt_parent": "PORT9" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1A", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x15", + "attr_mask": "0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x11", + "attr_mask": "0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x41", + "attr_mask": "0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x45", + "attr_mask": "0", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT10": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT10", + "device_parent": "MUX4" + }, + "dev_attr": { + "dev_idx": "10" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT10-EEPROM" + }, + { + "itf": "control", + "dev": "PORT10-CTRL" + } + ] + } + }, + "PORT10-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT10-EEPROM", + "device_parent": "MUX4", + "virt_parent": "PORT10" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1B", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT10-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT10-CTRL", + "device_parent": "MUX4", + "virt_parent": "PORT10" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1B", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x15", + "attr_mask": "1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x11", + "attr_mask": "1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x41", + "attr_mask": "1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x45", + "attr_mask": "1", + "attr_cmpval": "0x2", + "attr_len": "1" + } + ] + } + }, + "PORT11": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT11", + "device_parent": "MUX4" + }, + "dev_attr": { + "dev_idx": "11" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT11-EEPROM" + }, + { + "itf": "control", + "dev": "PORT11-CTRL" + } + ] + } + }, + "PORT11-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT11-EEPROM", + "device_parent": "MUX4", + "virt_parent": "PORT11" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1C", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT11-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT11-CTRL", + "device_parent": "MUX4", + "virt_parent": "PORT11" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1C", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x15", + "attr_mask": "2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x11", + "attr_mask": "2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x41", + "attr_mask": "2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x45", + "attr_mask": "2", + "attr_cmpval": "0x4", + "attr_len": "1" + } + ] + } + }, + "PORT12": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT12", + "device_parent": "MUX4" + }, + "dev_attr": { + "dev_idx": "12" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT12-EEPROM" + }, + { + "itf": "control", + "dev": "PORT12-CTRL" + } + ] + } + }, + "PORT12-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT12-EEPROM", + "device_parent": "MUX4", + "virt_parent": "PORT12" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1D", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT12-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT12-CTRL", + "device_parent": "MUX4", + "virt_parent": "PORT12" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1D", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x15", + "attr_mask": "3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x11", + "attr_mask": "3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x41", + "attr_mask": "3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x45", + "attr_mask": "3", + "attr_cmpval": "0x8", + "attr_len": "1" + } + ] + } + }, + "PORT13": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT13", + "device_parent": "MUX4" + }, + "dev_attr": { + "dev_idx": "13" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT13-EEPROM" + }, + { + "itf": "control", + "dev": "PORT13-CTRL" + } + ] + } + }, + "PORT13-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT13-EEPROM", + "device_parent": "MUX4", + "virt_parent": "PORT13" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1E", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT13-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT13-CTRL", + "device_parent": "MUX4", + "virt_parent": "PORT13" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1E", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x15", + "attr_mask": "4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x11", + "attr_mask": "4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x41", + "attr_mask": "4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x45", + "attr_mask": "4", + "attr_cmpval": "0x10", + "attr_len": "1" + } + ] + } + }, + "PORT14": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT14", + "device_parent": "MUX4" + }, + "dev_attr": { + "dev_idx": "14" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT14-EEPROM" + }, + { + "itf": "control", + "dev": "PORT14-CTRL" + } + ] + } + }, + "PORT14-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT14-EEPROM", + "device_parent": "MUX4", + "virt_parent": "PORT14" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1F", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT14-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT14-CTRL", + "device_parent": "MUX4", + "virt_parent": "PORT14" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1F", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x15", + "attr_mask": "5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x11", + "attr_mask": "5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x41", + "attr_mask": "5", + "attr_cmpval": "0x20", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x45", + "attr_mask": "5", + "attr_cmpval": "0x20", + "attr_len": "1" + } + ] + } + }, + "PORT15": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT15", + "device_parent": "MUX4" + }, + "dev_attr": { + "dev_idx": "15" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT15-EEPROM" + }, + { + "itf": "control", + "dev": "PORT15-CTRL" + } + ] + } + }, + "PORT15-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT15-EEPROM", + "device_parent": "MUX4", + "virt_parent": "PORT15" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x20", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT15-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT15-CTRL", + "device_parent": "MUX4", + "virt_parent": "PORT15" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x20", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x15", + "attr_mask": "6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x11", + "attr_mask": "6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x41", + "attr_mask": "6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x45", + "attr_mask": "6", + "attr_cmpval": "0x40", + "attr_len": "1" + } + ] + } + }, + "PORT16": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT16", + "device_parent": "MUX4" + }, + "dev_attr": { + "dev_idx": "16" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT16-EEPROM" + }, + { + "itf": "control", + "dev": "PORT16-CTRL" + } + ] + } + }, + "PORT16-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT16-EEPROM", + "device_parent": "MUX4", + "virt_parent": "PORT16" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x21", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT16-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT16-CTRL", + "device_parent": "MUX4", + "virt_parent": "PORT16" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x21", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x15", + "attr_mask": "7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x11", + "attr_mask": "7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x41", + "attr_mask": "7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x45", + "attr_mask": "7", + "attr_cmpval": "0x80", + "attr_len": "1" + } + ] + } + }, + "PORT17": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT17", + "device_parent": "MUX5" + }, + "dev_attr": { + "dev_idx": "17" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT17-EEPROM" + }, + { + "itf": "control", + "dev": "PORT17-CTRL" + } + ] + } + }, + "PORT17-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT17-EEPROM", + "device_parent": "MUX5", + "virt_parent": "PORT17" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x22", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT17-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT17-CTRL", + "device_parent": "MUX5", + "virt_parent": "PORT17" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x22", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x16", + "attr_mask": "0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x12", + "attr_mask": "0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x42", + "attr_mask": "0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x46", + "attr_mask": "0", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT18": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT18", + "device_parent": "MUX5" + }, + "dev_attr": { + "dev_idx": "18" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT18-EEPROM" + }, + { + "itf": "control", + "dev": "PORT18-CTRL" + } + ] + } + }, + "PORT18-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT18-EEPROM", + "device_parent": "MUX5", + "virt_parent": "PORT18" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x23", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT18-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT18-CTRL", + "device_parent": "MUX5", + "virt_parent": "PORT18" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x23", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x16", + "attr_mask": "1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x12", + "attr_mask": "1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x42", + "attr_mask": "1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x46", + "attr_mask": "1", + "attr_cmpval": "0x2", + "attr_len": "1" + } + ] + } + }, + "PORT19": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT19", + "device_parent": "MUX5" + }, + "dev_attr": { + "dev_idx": "19" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT19-EEPROM" + }, + { + "itf": "control", + "dev": "PORT19-CTRL" + } + ] + } + }, + "PORT19-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT19-EEPROM", + "device_parent": "MUX5", + "virt_parent": "PORT19" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x24", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT19-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT19-CTRL", + "device_parent": "MUX5", + "virt_parent": "PORT19" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x24", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x16", + "attr_mask": "2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x12", + "attr_mask": "2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x42", + "attr_mask": "2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x46", + "attr_mask": "2", + "attr_cmpval": "0x4", + "attr_len": "1" + } + ] + } + }, + "PORT20": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT20", + "device_parent": "MUX5" + }, + "dev_attr": { + "dev_idx": "20" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT20-EEPROM" + }, + { + "itf": "control", + "dev": "PORT20-CTRL" + } + ] + } + }, + "PORT20-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT20-EEPROM", + "device_parent": "MUX5", + "virt_parent": "PORT20" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x25", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT20-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT20-CTRL", + "device_parent": "MUX5", + "virt_parent": "PORT20" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x25", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x16", + "attr_mask": "3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x12", + "attr_mask": "3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x42", + "attr_mask": "3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x46", + "attr_mask": "3", + "attr_cmpval": "0x8", + "attr_len": "1" + } + ] + } + }, + "PORT21": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT21", + "device_parent": "MUX5" + }, + "dev_attr": { + "dev_idx": "21" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT21-EEPROM" + }, + { + "itf": "control", + "dev": "PORT21-CTRL" + } + ] + } + }, + "PORT21-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT21-EEPROM", + "device_parent": "MUX5", + "virt_parent": "PORT21" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x26", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT21-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT21-CTRL", + "device_parent": "MUX5", + "virt_parent": "PORT21" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x26", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x16", + "attr_mask": "4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x12", + "attr_mask": "4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x42", + "attr_mask": "4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x46", + "attr_mask": "4", + "attr_cmpval": "0x10", + "attr_len": "1" + } + ] + } + }, + "PORT22": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT22", + "device_parent": "MUX5" + }, + "dev_attr": { + "dev_idx": "22" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT22-EEPROM" + }, + { + "itf": "control", + "dev": "PORT22-CTRL" + } + ] + } + }, + "PORT22-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT22-EEPROM", + "device_parent": "MUX5", + "virt_parent": "PORT22" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x27", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT22-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT22-CTRL", + "device_parent": "MUX5", + "virt_parent": "PORT22" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x27", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x16", + "attr_mask": "5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x12", + "attr_mask": "5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x42", + "attr_mask": "5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x46", + "attr_mask": "5", + "attr_cmpval": "0x20", + "attr_len": "1" + } + ] + } + }, + "PORT23": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT23", + "device_parent": "MUX5" + }, + "dev_attr": { + "dev_idx": "23" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT23-EEPROM" + }, + { + "itf": "control", + "dev": "PORT23-CTRL" + } + ] + } + }, + "PORT23-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT23-EEPROM", + "device_parent": "MUX5", + "virt_parent": "PORT23" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x28", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT23-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT23-CTRL", + "device_parent": "MUX5", + "virt_parent": "PORT23" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x28", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x16", + "attr_mask": "6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x12", + "attr_mask": "6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x42", + "attr_mask": "6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x46", + "attr_mask": "6", + "attr_cmpval": "0x40", + "attr_len": "1" + } + ] + } + }, + "PORT24": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT24", + "device_parent": "MUX5" + }, + "dev_attr": { + "dev_idx": "24" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT24-EEPROM" + }, + { + "itf": "control", + "dev": "PORT24-CTRL" + } + ] + } + }, + "PORT24-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT24-EEPROM", + "device_parent": "MUX5", + "virt_parent": "PORT24" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x29", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT24-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT24-CTRL", + "device_parent": "MUX5", + "virt_parent": "PORT24" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x29", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x16", + "attr_mask": "7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x12", + "attr_mask": "7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x42", + "attr_mask": "7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x46", + "attr_mask": "7", + "attr_cmpval": "0x80", + "attr_len": "1" + } + ] + } + }, + "PORT25": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT25", + "device_parent": "MUX6" + }, + "dev_attr": { + "dev_idx": "25" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT25-EEPROM" + }, + { + "itf": "control", + "dev": "PORT25-CTRL" + } + ] + } + }, + "PORT25-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT25-EEPROM", + "device_parent": "MUX6", + "virt_parent": "PORT25" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2A", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT25-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT25-CTRL", + "device_parent": "MUX6", + "virt_parent": "PORT25" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2A", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x17", + "attr_mask": "0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x13", + "attr_mask": "0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x43", + "attr_mask": "0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x47", + "attr_mask": "0", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT26": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT26", + "device_parent": "MUX6" + }, + "dev_attr": { + "dev_idx": "26" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT26-EEPROM" + }, + { + "itf": "control", + "dev": "PORT26-CTRL" + } + ] + } + }, + "PORT26-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT26-EEPROM", + "device_parent": "MUX6", + "virt_parent": "PORT26" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2B", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT26-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT26-CTRL", + "device_parent": "MUX6", + "virt_parent": "PORT26" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2B", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x17", + "attr_mask": "1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x13", + "attr_mask": "1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x43", + "attr_mask": "1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x47", + "attr_mask": "1", + "attr_cmpval": "0x2", + "attr_len": "1" + } + ] + } + }, + "PORT27": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT27", + "device_parent": "MUX6" + }, + "dev_attr": { + "dev_idx": "27" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT27-EEPROM" + }, + { + "itf": "control", + "dev": "PORT27-CTRL" + } + ] + } + }, + "PORT27-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT27-EEPROM", + "device_parent": "MUX6", + "virt_parent": "PORT27" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2C", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT27-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT27-CTRL", + "device_parent": "MUX6", + "virt_parent": "PORT27" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2C", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x17", + "attr_mask": "2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x13", + "attr_mask": "2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x43", + "attr_mask": "2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x47", + "attr_mask": "2", + "attr_cmpval": "0x4", + "attr_len": "1" + } + ] + } + }, + "PORT28": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT28", + "device_parent": "MUX6" + }, + "dev_attr": { + "dev_idx": "28" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT28-EEPROM" + }, + { + "itf": "control", + "dev": "PORT28-CTRL" + } + ] + } + }, + "PORT28-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT28-EEPROM", + "device_parent": "MUX6", + "virt_parent": "PORT28" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2D", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT28-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT28-CTRL", + "device_parent": "MUX6", + "virt_parent": "PORT28" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2D", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x17", + "attr_mask": "3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x13", + "attr_mask": "3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x43", + "attr_mask": "3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x47", + "attr_mask": "3", + "attr_cmpval": "0x8", + "attr_len": "1" + } + ] + } + }, + "PORT29": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT29", + "device_parent": "MUX6" + }, + "dev_attr": { + "dev_idx": "29" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT29-EEPROM" + }, + { + "itf": "control", + "dev": "PORT29-CTRL" + } + ] + } + }, + "PORT29-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT29-EEPROM", + "device_parent": "MUX6", + "virt_parent": "PORT29" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2E", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT29-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT29-CTRL", + "device_parent": "MUX6", + "virt_parent": "PORT29" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2E", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x17", + "attr_mask": "4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x13", + "attr_mask": "4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x43", + "attr_mask": "4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x47", + "attr_mask": "4", + "attr_cmpval": "0x10", + "attr_len": "1" + } + ] + } + }, + "PORT30": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT30", + "device_parent": "MUX6" + }, + "dev_attr": { + "dev_idx": "30" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT30-EEPROM" + }, + { + "itf": "control", + "dev": "PORT30-CTRL" + } + ] + } + }, + "PORT30-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT30-EEPROM", + "device_parent": "MUX6", + "virt_parent": "PORT30" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2F", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT30-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT30-CTRL", + "device_parent": "MUX6", + "virt_parent": "PORT30" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2F", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x17", + "attr_mask": "5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x13", + "attr_mask": "5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x43", + "attr_mask": "5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x47", + "attr_mask": "5", + "attr_cmpval": "0x20", + "attr_len": "1" + } + ] + } + }, + "PORT31": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT31", + "device_parent": "MUX6" + }, + "dev_attr": { + "dev_idx": "31" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT31-EEPROM" + }, + { + "itf": "control", + "dev": "PORT31-CTRL" + } + ] + } + }, + "PORT31-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT31-EEPROM", + "device_parent": "MUX6", + "virt_parent": "PORT31" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x30", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT31-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT31-CTRL", + "device_parent": "MUX6", + "virt_parent": "PORT31" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x30", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x17", + "attr_mask": "6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x13", + "attr_mask": "6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x43", + "attr_mask": "6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x47", + "attr_mask": "6", + "attr_cmpval": "0x40", + "attr_len": "1" + } + ] + } + }, + "PORT32": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT32", + "device_parent": "MUX6" + }, + "dev_attr": { + "dev_idx": "32" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT32-EEPROM" + }, + { + "itf": "control", + "dev": "PORT32-CTRL" + } + ] + } + }, + "PORT32-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT32-EEPROM", + "device_parent": "MUX6", + "virt_parent": "PORT32" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x31", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT32-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT32-CTRL", + "device_parent": "MUX6", + "virt_parent": "PORT32" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x31", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x17", + "attr_mask": "7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x13", + "attr_mask": "7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x43", + "attr_mask": "7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x47", + "attr_mask": "7", + "attr_cmpval": "0x80", + "attr_len": "1" + } + ] + } + }, + "PORT33": { + "dev_info": { + "device_type": "SFP", + "device_name": "PORT33", + "device_parent": "MUX7" + }, + "dev_attr": { + "dev_idx": "33" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT33-EEPROM" + }, + { + "itf": "control", + "dev": "PORT33-CTRL" + } + ] + } + }, + "PORT33-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT33", + "device_parent": "MUX7", + "virt_parent": "PORT33" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x33", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT33-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT33-CTRL", + "device_parent": "MUX7", + "virt_parent": "PORT33" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x33", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x18", + "attr_mask": "1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x19", + "attr_mask": "1", + "attr_cmpval": "0x2", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x1A", + "attr_mask": "1", + "attr_cmpval": "0x2", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x48", + "attr_mask": "1", + "attr_cmpval": "0x2", + "attr_len": "1" + } + ] + } + } + +} diff --git a/device/ufispace/x86_64-ufispace_s9110_32x-r0/pddf/pddf-device-pvt.json b/device/ufispace/x86_64-ufispace_s9110_32x-r0/pddf/pddf-device-pvt.json new file mode 100644 index 000000000000..4f86b045c858 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s9110_32x-r0/pddf/pddf-device-pvt.json @@ -0,0 +1,4585 @@ +{ + "PLATFORM": { + "num_psus": 2, + "num_fantrays": 3, + "num_fans_pertray": 2, + "num_ports": 33, + "num_temps": 7, + "pddf_dev_types": { + "description": "PDDF supported devices", + "CPLD": [ + "i2c_cpld" + ], + "PSU": [ + "psu_eeprom", + "psu_pmbus" + ], + "PORT_MODULE": [ + "pddf_xcvr" + ] + }, + "std_kos": [ + "i2c_i801", + "i2c-ismt", + "i2c_dev", + "i2c_mux_pca954x", + "optoe" + ], + "pddf_kos": [ + "pddf_client_module", + "pddf_cpld_module", + "pddf_cpld_driver", + "pddf_mux_module", + "pddf_xcvr_module", + "pddf_xcvr_driver_module", + "pddf_psu_driver_module", + "pddf_psu_module", + "pddf_fan_driver_module", + "pddf_fan_module", + "pddf_led_module" + ], + "custom_kos": [ + "x86-64-ufispace-s9110-32x-lpc", + "x86-64-ufispace-s9110-32x-sys-eeprom", + "pddf_custom_sysstatus_module" + ] + }, + "SYSTEM": { + "dev_info": { + "device_type": "CPU", + "device_name": "ROOT_COMPLEX", + "device_parent": null + }, + "i2c": { + "CONTROLLERS": [ + { + "dev_name": "i2c-1", + "dev": "SMBUS1" + }, + { + "dev_name": "i2c-0", + "dev": "SMBUS0" + } + ] + } + }, + "SMBUS1": { + "dev_info": { + "device_type": "SMBUS", "device_name": "SMBUS1", "device_parent": "SYSTEM" + }, + "i2c": { + "topo_info": { + "dev_addr": "0x1" + }, + "DEVICES": [ + { + "dev": "EEPROM1" + }, + { + "dev": "MUX1" + } + ] + } + }, + "EEPROM1": { + "dev_info": { + "device_type": "EEPROM", + "device_name": "EEPROM1", + "device_parent": "SMBUS1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1", + "dev_addr": "0x57", + "dev_type": "sys_eeprom" + }, + "dev_attr": { + "access_mode": "BLOCK" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "MUX1": { + "dev_info": { "device_type": "MUX", "device_name": "MUX1", "device_parent": "SMBUS1"}, + "i2c": { + "topo_info": { + "parent_bus": "0x1", + "dev_addr": "0x70", + "dev_type": "pca9548" + }, + "dev_attr": { + "virt_bus": "0x2", + "idle_state": "-2" + }, + "channel": [ + { + "chn": "0", + "dev": "CPLD1" + }, + { + "chn": "0", + "dev": "CPLD2" + }, + { + "chn": "0", + "dev": "PSU1" + }, + { + "chn": "0", + "dev": "PSU2" + } + ] + } + }, + "CPLD1": { + "dev_info": { + "device_type": "CPLD", + "device_name": "CPLD1", + "device_parent": "MUX1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2", + "dev_addr": "0x30", + "dev_type": "i2c_cpld" + }, + "dev_attr": {} + } + }, + "CPLD2": { + "dev_info": { + "device_type": "CPLD", + "device_name": "CPLD2", + "device_parent": "MUX1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2", + "dev_addr": "0x31", + "dev_type": "i2c_cpld" + }, + "dev_attr": {} + } + }, + "SMBUS0": { + "dev_info": { + "device_type": "SMBUS", "device_name": "SMBUS0", "device_parent": "SYSTEM" + }, + "i2c": { + "topo_info": { + "dev_addr": "0x0" + }, + "DEVICES": [ + { + "dev": "MUX2" + } + ] + } + }, + "MUX2": { + "dev_info": { "device_type":"MUX", "device_name":"MUX2", "device_parent":"SMBUS0"}, + "i2c": + { + "topo_info": { "parent_bus":"0x0", "dev_addr":"0x72", "dev_type":"pca9548"}, + "dev_attr": { "virt_bus":"0xa", "idle_state":"-2"}, + "channel": + [ + { "chn":"0", "dev":"MUX3" }, + { "chn":"1", "dev":"MUX4" }, + { "chn":"2", "dev":"MUX5" }, + { "chn":"3", "dev":"MUX6" }, + { "chn":"4", "dev":"MUX7" } + ] + } + }, + "MUX3": { + "dev_info": { "device_type":"MUX", "device_name":"MUX3", "device_parent":"MUX2"}, + "i2c": { + "topo_info": { "parent_bus":"0xa", "dev_addr":"0x73", "dev_type":"pca9548"}, + "dev_attr": { "virt_bus":"0x12", "idle_state":"-2"}, + "channel": [ + { "chn":"0", "dev":"PORT1" }, + { "chn":"1", "dev":"PORT2" }, + { "chn":"2", "dev":"PORT3" }, + { "chn":"3", "dev":"PORT4" }, + { "chn":"4", "dev":"PORT5" }, + { "chn":"5", "dev":"PORT6" }, + { "chn":"6", "dev":"PORT7" }, + { "chn":"7", "dev":"PORT8" } + ] + } + }, + "MUX4": { + "dev_info": { "device_type":"MUX", "device_name":"MUX4", "device_parent":"MUX2"}, + "i2c": { + "topo_info": { "parent_bus":"0xb", "dev_addr":"0x73", "dev_type":"pca9548"}, + "dev_attr": { "virt_bus":"0x1a", "idle_state":"-2"}, + "channel": [ + { "chn":"0", "dev":"PORT9" }, + { "chn":"1", "dev":"PORT10" }, + { "chn":"2", "dev":"PORT11" }, + { "chn":"3", "dev":"PORT12" }, + { "chn":"4", "dev":"PORT13" }, + { "chn":"5", "dev":"PORT14" }, + { "chn":"6", "dev":"PORT15" }, + { "chn":"7", "dev":"PORT16" } + ] + } + }, + "MUX5": { + "dev_info": { "device_type":"MUX", "device_name":"MUX5", "device_parent":"MUX2"}, + "i2c": { + "topo_info": { "parent_bus":"0xc", "dev_addr":"0x73", "dev_type":"pca9548"}, + "dev_attr": { "virt_bus":"0x22", "idle_state":"-2"}, + "channel": [ + { "chn":"0", "dev":"PORT17" }, + { "chn":"1", "dev":"PORT18" }, + { "chn":"2", "dev":"PORT19" }, + { "chn":"3", "dev":"PORT20" }, + { "chn":"4", "dev":"PORT21" }, + { "chn":"5", "dev":"PORT22" }, + { "chn":"6", "dev":"PORT23" }, + { "chn":"7", "dev":"PORT24" } + ] + } + }, + "MUX6": { + "dev_info": { "device_type":"MUX", "device_name":"MUX6", "device_parent":"MUX2"}, + "i2c": { + "topo_info": { "parent_bus":"0xd", "dev_addr":"0x73", "dev_type":"pca9548"}, + "dev_attr": { "virt_bus":"0x2a", "idle_state":"-2"}, + "channel": [ + { "chn":"0", "dev":"PORT25" }, + { "chn":"1", "dev":"PORT26" }, + { "chn":"2", "dev":"PORT27" }, + { "chn":"3", "dev":"PORT28" }, + { "chn":"4", "dev":"PORT29" }, + { "chn":"5", "dev":"PORT30" }, + { "chn":"6", "dev":"PORT31" }, + { "chn":"7", "dev":"PORT32" } + ] + } + }, + "MUX7": { + "dev_info": { "device_type":"MUX", "device_name":"MUX7", "device_parent":"MUX2"}, + "i2c": { + "topo_info": { "parent_bus":"0xe", "dev_addr":"0x73", "dev_type":"pca9548"}, + "dev_attr": { "virt_bus":"0x32", "idle_state":"-2"}, + "channel": [ + { "chn":"1", "dev":"PORT33" } + ] + } + }, + "TEMP1": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TEMP1", + "device_parent": "SMBUS0" + }, + "dev_attr": { + "display_name": "TEMP_MAC" + }, + "bmc": { + "ipmitool": { + "attr_list": [ + { + "attr_name": "temp1_input", + "bmc_cmd": "ipmitool sdr get -c TEMP_MAC", + "raw": "0", + "separator": ",", + "field_name": "TEMP_MAC", + "field_pos": "2" + }, + { + "attr_name": "temp1_high_threshold", + "bmc_cmd": "ipmitool sdr get -c TEMP_MAC", + "raw": "0", + "separator": ",", + "field_name": "TEMP_MAC", + "field_pos": "13" + }, + { + "attr_name": "temp1_high_crit_threshold", + "bmc_cmd": "ipmitool sdr get -c TEMP_MAC", + "raw": "0", + "separator": ",", + "field_name": "TEMP_MAC", + "field_pos": "12" + } + ] + } + } + }, + "TEMP2": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TEMP2", + "device_parent": "SMBUS0" + }, + "dev_attr": { + "display_name": "TEMP_ENV_MACCASE" + }, + "bmc": { + "ipmitool": { + "attr_list": [ + { + "attr_name": "temp1_input", + "bmc_cmd": "ipmitool sdr get -c TEMP_ENV_MACCASE", + "raw": "0", + "separator": ",", + "field_name": "TEMP_ENV_MACCASE", + "field_pos": "2" + }, + { + "attr_name": "temp1_high_threshold", + "bmc_cmd": "ipmitool sdr get -c TEMP_ENV_MACCASE", + "raw": "0", + "separator": ",", + "field_name": "TEMP_ENV_MACCASE", + "field_pos": "13" + }, + { + "attr_name": "temp1_high_crit_threshold", + "bmc_cmd": "ipmitool sdr get -c TEMP_ENV_MACCASE", + "raw": "0", + "separator": ",", + "field_name": "TEMP_ENV_MACCASE", + "field_pos": "12" + } + ] + } + } + }, + "TEMP3": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TEMP3", + "device_parent": "SMBUS0" + }, + "dev_attr": { + "display_name": "TEMP_ENV_SSDCASE" + }, + "bmc": { + "ipmitool": { + "attr_list": [ + { + "attr_name": "temp1_input", + "bmc_cmd": "ipmitool sdr get -c TEMP_ENV_SSDCASE", + "raw": "0", + "separator": ",", + "field_name": "TEMP_ENV_SSDCASE", + "field_pos": "2" + }, + { + "attr_name": "temp1_high_threshold", + "bmc_cmd": "ipmitool sdr get -c TEMP_ENV_SSDCASE", + "raw": "0", + "separator": ",", + "field_name": "TEMP_ENV_SSDCASE", + "field_pos": "13" + }, + { + "attr_name": "temp1_high_crit_threshold", + "bmc_cmd": "ipmitool sdr get -c TEMP_ENV_SSDCASE", + "raw": "0", + "separator": ",", + "field_name": "TEMP_ENV_SSDCASE", + "field_pos": "12" + } + ] + } + } + }, + "TEMP4": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TEMP4", + "device_parent": "SMBUS0" + }, + "dev_attr": { + "display_name": "TEMP_ENV_PSUCASE" + }, + "bmc": { + "ipmitool": { + "attr_list": [ + { + "attr_name": "temp1_input", + "bmc_cmd": "ipmitool sdr get -c TEMP_ENV_PSUCASE", + "raw": "0", + "separator": ",", + "field_name": "TEMP_ENV_PSUCASE", + "field_pos": "2" + }, + { + "attr_name": "temp1_high_threshold", + "bmc_cmd": "ipmitool sdr get -c TEMP_ENV_PSUCASE", + "raw": "0", + "separator": ",", + "field_name": "TEMP_ENV_PSUCASE", + "field_pos": "13" + }, + { + "attr_name": "temp1_high_crit_threshold", + "bmc_cmd": "ipmitool sdr get -c TEMP_ENV_PSUCASE", + "raw": "0", + "separator": ",", + "field_name": "TEMP_ENV_PSUCASE", + "field_pos": "12" + } + ] + } + } + }, + "TEMP5": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TEMP5", + "device_parent": "SMBUS0" + }, + "dev_attr": { + "display_name": "TEMP_ENV_BMC" + }, + "bmc": { + "ipmitool": { + "attr_list": [ + { + "attr_name": "temp1_input", + "bmc_cmd": "ipmitool sdr get -c TEMP_ENV_BMC", + "raw": "0", + "separator": ",", + "field_name": "TEMP_ENV_BMC", + "field_pos": "2" + }, + { + "attr_name": "temp1_high_threshold", + "bmc_cmd": "ipmitool sdr get -c TEMP_ENV_BMC", + "raw": "0", + "separator": ",", + "field_name": "TEMP_ENV_BMC", + "field_pos": "13" + }, + { + "attr_name": "temp1_high_crit_threshold", + "bmc_cmd": "ipmitool sdr get -c TEMP_ENV_BMC", + "raw": "0", + "separator": ",", + "field_name": "TEMP_ENV_BMC", + "field_pos": "12" + } + ] + } + } + }, + "TEMP6": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TEMP6", + "device_parent": "SMBUS0" + }, + "dev_attr": { + "display_name": "TEMP_PSU0_TEMP1" + }, + "bmc": { + "ipmitool": { + "attr_list": [ + { + "attr_name": "temp1_input", + "bmc_cmd": "ipmitool sdr get -c PSU0_TEMP1 | sed -e 's/,,/,0,/g' -e 's/,,/,0,/g'", + "raw": "0", + "separator": ",", + "field_name": "PSU0_TEMP1", + "field_pos": "2" + }, + { + "attr_name": "temp1_high_threshold", + "bmc_cmd": "ipmitool sdr get -c PSU0_TEMP1", + "raw": "0", + "separator": ",", + "field_name": "PSU0_TEMP1", + "field_pos": "13" + }, + { + "attr_name": "temp1_high_crit_threshold", + "bmc_cmd": "ipmitool sdr get -c PSU0_TEMP1", + "raw": "0", + "separator": ",", + "field_name": "PSU0_TEMP1", + "field_pos": "12" + } + ] + } + } + }, + "TEMP7": { + "dev_info": { + "device_type": "TEMP_SENSOR", + "device_name": "TEMP7", + "device_parent": "SMBUS0" + }, + "dev_attr": { + "display_name": "TEMP_PSU1_TEMP1" + }, + "bmc": { + "ipmitool": { + "attr_list": [ + { + "attr_name": "temp1_input", + "bmc_cmd": "ipmitool sdr get -c PSU1_TEMP1 | sed -e 's/,,/,0,/g' -e 's/,,/,0,/g'", + "raw": "0", + "separator": ",", + "field_name": "PSU1_TEMP1", + "field_pos": "2" + }, + { + "attr_name": "temp1_high_threshold", + "bmc_cmd": "ipmitool sdr get -c PSU1_TEMP1", + "raw": "0", + "separator": ",", + "field_name": "PSU1_TEMP1", + "field_pos": "13" + }, + { + "attr_name": "temp1_high_crit_threshold", + "bmc_cmd": "ipmitool sdr get -c PSU1_TEMP1", + "raw": "0", + "separator": ",", + "field_name": "PSU1_TEMP1", + "field_pos": "12" + } + ] + } + } + }, + "SYSSTATUS": { + "dev_info": { + "device_type": "SYSSTAT", + "device_name": "SYSSTATUS" + }, + "dev_attr": {}, + "attr_list": + [ + { + "attr_name": "board_sku_id", + "attr_devaddr": "0x30", + "attr_offset": "0x0", + "attr_mask": "0xff", + "attr_len": "0x1" + }, + { + "attr_name": "board_hw_id", + "attr_devaddr": "0x30", + "attr_offset": "0x1", + "attr_mask": "0x03", + "attr_len": "0x1" + }, + { + "attr_name": "board_deph_id", + "attr_devaddr": "0x30", + "attr_offset": "0x1", + "attr_mask": "0x4", + "attr_len": "0x1" + }, + { + "attr_name": "board_build_id", + "attr_devaddr": "0x30", + "attr_offset": "0x1", + "attr_mask": "0x18", + "attr_len": "0x1" + }, + { + "attr_name": "cpld1_major_ver", + "attr_devaddr": "0x30", + "attr_offset": "0x2", + "attr_mask": "0xc0", + "attr_len": "0x1" + }, + { + "attr_name": "cpld1_minor_ver", + "attr_devaddr": "0x30", + "attr_offset": "0x2", + "attr_mask": "0x3f", + "attr_len": "0x1" + }, + { + "attr_name": "cpld1_build", + "attr_devaddr": "0x30", + "attr_offset": "0x4", + "attr_mask": "0xff", + "attr_len": "0x1" + }, + { + "attr_name": "cpld2_major_ver", + "attr_devaddr": "0x31", + "attr_offset": "0x2", + "attr_mask": "0xc0", + "attr_len": "0x1" + }, + { + "attr_name": "cpld2_minor_ver", + "attr_devaddr": "0x31", + "attr_offset": "0x2", + "attr_mask": "0x3f", + "attr_len": "0x1" + }, + { + "attr_name": "cpld2_build", + "attr_devaddr": "0x31", + "attr_offset": "0x4", + "attr_mask": "0xff", + "attr_len": "0x1" + }, + { + "attr_name": "psu_status", + "attr_devaddr": "0x30", + "attr_offset": "0x51", + "attr_mask": "0xff", + "attr_len": "0x1" + }, + { + "attr_name": "system_led_psu", + "attr_devaddr": "0x30", + "attr_offset": "0x80", + "attr_mask": "0xff", + "attr_len": "0x1" + }, + { + "attr_name": "system_led_sys", + "attr_devaddr": "0x30", + "attr_offset": "0x81", + "attr_mask": "0xff", + "attr_len": "0x1" + }, + { + "attr_name": "system_led_fan", + "attr_devaddr": "0x30", + "attr_offset": "0x83", + "attr_mask": "0xff", + "attr_len": "0x1" + }, + { + "attr_name": "system_led_id", + "attr_devaddr": "0x30", + "attr_offset": "0x84", + "attr_mask": "0xff", + "attr_len": "0x1" + } + ] + }, + "PSU1": { + "dev_info": { + "device_type": "PSU", + "device_name": "PSU1", + "device_parent": "MUX1" + }, + "dev_attr": { + "dev_idx": "1", + "num_psu_fans": "1" + }, + "i2c": { + "interface": [ + { "itf":"eeprom", "dev":"PSU1-EEPROM" } + ] + }, + "bmc": { + "ipmitool": { + "attr_list": + [ + { + "attr_name": "psu_v_out", + "bmc_cmd": "ipmitool sdr get -c PSU0_VOUT | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "separator": ",", + "field_name": "PSU0_VOUT", + "field_pos": "2", + "mult": "1000" + }, + { + "attr_name": "psu_i_out", + "bmc_cmd": "ipmitool sdr get -c PSU0_IOUT | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "separator": ",", + "field_name": "PSU0_IOUT", + "field_pos": "2", + "mult": "1000" + }, + { + "attr_name": "psu_temp1_input", + "bmc_cmd": "ipmitool sdr get -c PSU0_TEMP1 | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "separator": ",", + "field_name": "PSU0_TEMP1", + "field_pos": "2", + "mult": "1000" + }, + { + "attr_name": "psu_fan1_speed_rpm", + "bmc_cmd": "ipmitool sdr get -c PSU0_FAN1 | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "separator": ",", + "field_name": "PSU0_FAN1", + "field_pos": "2" + }, + { + "attr_name": "psu_mfr_id", + "bmc_cmd": "_rv=$(ipmitool fru print 1 2>/dev/null | tr -s ' ' | cut -d' ' -f3-5 | grep 'Manufacturer') && echo $_rv || echo 'Manufacturer : N/A'", + "raw": "0", + "separator": ":", + "field_name": "Manufacturer", + "field_pos": "2" + }, + { + "attr_name": "psu_model_name", + "bmc_cmd": "_rv=$(ipmitool fru print 1 2>/dev/null | tr -s ' ' | cut -d' ' -f3-5 | grep 'Name') && echo $_rv || echo 'Name : N/A'", + "raw": "0", + "separator": ":", + "field_name": "Name", + "field_pos": "2" + }, + { + "attr_name": "psu_serial_num", + "bmc_cmd": "_rv=$(ipmitool fru print 1 2>/dev/null | tr -s ' ' | cut -d' ' -f3-5 | grep 'Serial') && echo $_rv || echo 'Serial : N/A'", + "raw": "0", + "separator": ":", + "field_name": "Serial", + "field_pos": "2" + }, + { + "attr_name": "psu_fan_dir", + "bmc_cmd": "ipmitool raw 0x3c 0x30 0x0 | xargs | cut -d' ' -f1", + "raw": "1", + "type": "raw" + } + ] + } + } + }, + "PSU1-EEPROM": { + "dev_info": { + "device_type": "PSU-EEPROM", + "device_name": "PSU1-EEPROM", + "device_parent": "MUX1", + "virt_parent": "PSU1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2", + "dev_addr": "0x5a", + "dev_type": "psu_eeprom" + }, + "attr_list": [ + { + "attr_name":"psu_present", + "attr_devaddr":"0x30", + "attr_devtype":"cpld", + "attr_offset":"0x51", + "attr_mask":"0x1", + "attr_cmpval":"0x0", + "attr_len":"1" + }, + { + "attr_name":"psu_power_good", + "attr_devaddr":"0x30", + "attr_devtype":"cpld", + "attr_offset":"0x51", + "attr_mask":"0x10", + "attr_cmpval":"0x10", + "attr_len":"1" + } + ] + } + }, + "PSU2": { + "dev_info": { + "device_type": "PSU", + "device_name": "PSU2", + "device_parent": "MUX1" + }, + "dev_attr": { + "dev_idx": "2", + "num_psu_fans": "1" + }, + "i2c": { + "interface": [ + { "itf":"eeprom", "dev":"PSU2-EEPROM" } + ] + }, + "bmc": { + "ipmitool": { + "attr_list": + [ + { + "attr_name": "psu_v_out", + "bmc_cmd": "ipmitool sdr get -c PSU1_VOUT | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "separator": ",", + "field_name": "PSU1_VOUT", + "field_pos": "2", + "mult": "1000" + }, + { + "attr_name": "psu_i_out", + "bmc_cmd": "ipmitool sdr get -c PSU1_IOUT | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "separator": ",", + "field_name": "PSU1_IOUT", + "field_pos": "2", + "mult": "1000" + }, + { + "attr_name": "psu_temp1_input", + "bmc_cmd": "ipmitool sdr get -c PSU1_TEMP1 | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "separator": ",", + "field_name": "PSU1_TEMP1", + "field_pos": "2", + "mult": "1000" + }, + { + "attr_name": "psu_fan1_speed_rpm", + "bmc_cmd": "ipmitool sdr get -c PSU1_FAN1 | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "separator": ",", + "field_name": "PSU1_FAN1", + "field_pos": "2" + }, + { + "attr_name": "psu_mfr_id", + "bmc_cmd": "_rv=$(ipmitool fru print 2 2>/dev/null | tr -s ' ' | cut -d' ' -f3-5 | grep 'Manufacturer') && echo $_rv || echo 'Manufacturer : N/A'", + "raw": "0", + "separator": ":", + "field_name": "Manufacturer", + "field_pos": "2" + }, + { + "attr_name": "psu_model_name", + "bmc_cmd": "_rv=$(ipmitool fru print 2 2>/dev/null | tr -s ' ' | cut -d' ' -f3-5 | grep 'Name') && echo $_rv || echo 'Name : N/A'", + "raw": "0", + "separator": ":", + "field_name": "Name", + "field_pos": "2" + }, + { + "attr_name": "psu_serial_num", + "bmc_cmd": "_rv=$(ipmitool fru print 2 2>/dev/null | tr -s ' ' | cut -d' ' -f3-5 | grep 'Serial') && echo $_rv || echo 'Serial : N/A'", + "raw": "0", + "separator": ":", + "field_name": "Serial", + "field_pos": "2" + }, + { + "attr_name": "psu_fan_dir", + "bmc_cmd": "ipmitool raw 0x3c 0x30 0x0 | xargs | cut -d' ' -f2", + "raw": "1", + "type": "raw" + } + ] + } + } + }, + "PSU2-EEPROM": { + "dev_info": { + "device_type": "PSU-EEPROM", + "device_name": "PSU2-EEPROM", + "device_parent": "MUX1", + "virt_parent": "PSU2" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2", + "dev_addr": "0x5b", + "dev_type": "psu_eeprom" + }, + "attr_list": [ + { + "attr_name":"psu_present", + "attr_devaddr":"0x30", + "attr_devtype":"cpld", + "attr_offset":"0x51", + "attr_mask":"0x2", + "attr_cmpval":"0x0", + "attr_len":"1" + }, + { + "attr_name":"psu_power_good", + "attr_devaddr":"0x30", + "attr_devtype":"cpld", + "attr_offset":"0x51", + "attr_mask":"0x20", + "attr_cmpval":"0x20", + "attr_len":"1" + } + ] + } + }, + "FAN-CTRL": { + "dev_info": { + "device_type": "FAN", + "device_name": "FAN-CTRL", + "device_parent": "" + }, + "bmc": { + "ipmitool": { + "attr_list": [ + { + "attr_name": "fan1_present", + "bmc_cmd": "ipmitool sdr get -c FAN0_PRSNT_L", + "raw": "0", + "separator": ",", + "field_name": "FAN0_PRSNT_L", + "field_pos": "5" + }, + { + "attr_name": "fan2_present", + "bmc_cmd": "ipmitool sdr get -c FAN0_PRSNT_L", + "raw": "0", + "separator": ",", + "field_name": "FAN0_PRSNT_L", + "field_pos": "5" + }, + { + "attr_name": "fan3_present", + "bmc_cmd": "ipmitool sdr get -c FAN1_PRSNT_L", + "raw": "0", + "separator": ",", + "field_name": "FAN1_PRSNT_L", + "field_pos": "5" + }, + { + "attr_name": "fan4_present", + "bmc_cmd": "ipmitool sdr get -c FAN1_PRSNT_L", + "raw": "0", + "separator": ",", + "field_name": "FAN1_PRSNT_L", + "field_pos": "5" + }, + { + "attr_name": "fan5_present", + "bmc_cmd": "ipmitool sdr get -c FAN2_PRSNT_L", + "raw": "0", + "separator": ",", + "field_name": "FAN2_PRSNT_L", + "field_pos": "5" + }, + { + "attr_name": "fan6_present", + "bmc_cmd": "ipmitool sdr get -c FAN2_PRSNT_L", + "raw": "0", + "separator": ",", + "field_name": "FAN2_PRSNT_L", + "field_pos": "5" + }, + { + "attr_name": "fan1_input", + "bmc_cmd": "ipmitool sdr get -c FAN0_RPM_F | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "separator": ",", + "field_name": "FAN0_RPM_F", + "field_pos": "2" + }, + { + "attr_name": "fan2_input", + "bmc_cmd": "ipmitool sdr get -c FAN0_RPM_R | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "separator": ",", + "field_name": "FAN0_RPM_R", + "field_pos": "2" + }, + { + "attr_name": "fan3_input", + "bmc_cmd": "ipmitool sdr get -c FAN1_RPM_F | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "separator": ",", + "field_name": "FAN1_RPM_F", + "field_pos": "2" + }, + { + "attr_name": "fan4_input", + "bmc_cmd": "ipmitool sdr get -c FAN1_RPM_R | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "separator": ",", + "field_name": "FAN1_RPM_R", + "field_pos": "2" + }, + { + "attr_name": "fan5_input", + "bmc_cmd": "ipmitool sdr get -c FAN2_RPM_F | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "separator": ",", + "field_name": "FAN2_RPM_F", + "field_pos": "2" + }, + { + "attr_name": "fan6_input", + "bmc_cmd": "ipmitool sdr get -c FAN2_RPM_R | sed -e 's/,,/,N\\/A,/g' -e 's/,,/,N\\/A,/g'", + "raw": "0", + "separator": ",", + "field_name": "FAN2_RPM_R", + "field_pos": "2" + }, + { + "attr_name": "fan1_direction", + "bmc_cmd": "ipmitool raw 0x3c 0x31 0x0 | xargs | cut -d' ' -f1", + "raw": "1", + "type": "raw" + }, + { + "attr_name": "fan2_direction", + "bmc_cmd": "ipmitool raw 0x3c 0x31 0x0 | xargs | cut -d' ' -f1", + "raw": "1", + "type": "raw" + }, + { + "attr_name": "fan3_direction", + "bmc_cmd": "ipmitool raw 0x3c 0x31 0x0 | xargs | cut -d' ' -f2", + "raw": "1", + "type": "raw" + }, + { + "attr_name": "fan4_direction", + "bmc_cmd": "ipmitool raw 0x3c 0x31 0x0 | xargs | cut -d' ' -f2", + "raw": "1", + "type": "raw" + }, + { + "attr_name": "fan5_direction", + "bmc_cmd": "ipmitool raw 0x3c 0x31 0x0 | xargs | cut -d' ' -f3", + "raw": "1", + "type": "raw" + }, + { + "attr_name": "fan6_direction", + "bmc_cmd": "ipmitool raw 0x3c 0x31 0x0 | xargs | cut -d' ' -f3", + "raw": "1", + "type": "raw" + } + ] + } + } + }, + "SYS_LED": { + "dev_info": { + "device_type": "LED", + "device_name": "SYS_LED" + }, + "dev_attr": { + "index": "0", + "flag": "rw" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "green", + "bits": "7:4", + "descr": "Green", + "value": "0x09;0x0b", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x81" + }, + { + "attr_name": "green_blink", + "bits": "7:4", + "descr": "Green Blinking", + "value": "0x0d;0x0f", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x81" + }, + { + "attr_name": "yellow", + "bits": "7:4", + "descr": "Yellow", + "value": "0x08;0x0a", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x81" + }, + { + "attr_name": "yellow_blink", + "bits": "7:4", + "descr": "Yellow Blinking", + "value": "0x0c;0x0e", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x81" + }, + { + "attr_name": "off", + "bits": "7:6", + "descr": "Off", + "value": "0x01;0x0", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x81" + } + ] + } + }, + "FAN_LED": { + "dev_info": { + "device_type": "LED", + "device_name": "FAN_LED" + }, + "dev_attr": { + "index": "0", + "flag": "ro" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "green", + "bits": "3:0", + "descr": "Green", + "value": "0x09;0x0b", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x83" + }, + { + "attr_name": "green_blink", + "bits": "3:0", + "descr": "Green Blinking", + "value": "0x0d;0x0f", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x83" + }, + { + "attr_name": "yellow", + "bits": "3:0", + "descr": "Yellow", + "value": "0x08;0x0a", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x83" + }, + { + "attr_name": "yellow_blink", + "bits": "3:0", + "descr": "Yellow Blinking", + "value": "0x0c;0x0e", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x83" + }, + { + "attr_name": "off", + "bits": "3", + "descr": "Off", + "value": "0x0", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x83" + } + ] + } + }, + "PSU1_LED": { + "dev_info": { + "device_type": "LED", + "device_name": "PSU_LED" + }, + "dev_attr": { + "index": "0", + "flag": "ro" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "green", + "bits": "3:0", + "descr": "Green", + "value": "0x09;0x0b", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x80" + }, + { + "attr_name": "green_blink", + "bits": "3:0", + "descr": "Green Blinking", + "value": "0x0d;0x0f", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x80" + }, + { + "attr_name": "yellow", + "bits": "3:0", + "descr": "Yellow", + "value": "0x08;0x0a", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x80" + }, + { + "attr_name": "yellow_blink", + "bits": "3:0", + "descr": "Yellow Blinking", + "value": "0x0c;0x0e", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x80" + }, + { + "attr_name": "off", + "bits": "3", + "descr": "Off", + "value": "0x0", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x80" + } + ] + } + }, + "PSU2_LED": { + "dev_info": { + "device_type": "LED", + "device_name": "PSU_LED" + }, + "dev_attr": { + "index": "1", + "flag": "ro" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "green", + "bits": "7:4", + "descr": "Green", + "value": "0x09;0x0b", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x80" + }, + { + "attr_name": "green_blink", + "bits": "7:4", + "descr": "Green Blinking", + "value": "0x0d;0x0f", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x80" + }, + { + "attr_name": "yellow", + "bits": "7:4", + "descr": "Yellow", + "value": "0x08;0x0a", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x80" + }, + { + "attr_name": "yellow_blink", + "bits": "7:4", + "descr": "Yellow Blinking", + "value": "0x0c;0x0e", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x80" + }, + { + "attr_name": "off", + "bits": "7", + "descr": "Off", + "value": "0x0", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x80" + } + ] + } + }, + "ID_LED": { + "dev_info": { + "device_type": "LED", + "device_name": "LOC_LED" + }, + "dev_attr": { + "index": "0", + "flag": "rw" + }, + "i2c": { + "attr_list": [ + { + "attr_name": "blue", + "bits": "3:1", + "descr": "Blue", + "value": "0x04;0x05", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x84" + }, + { + "attr_name": "blue_blink", + "bits": "3:1", + "descr": "Blue Blinking", + "value": "0x06;0x07", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x84" + }, + { + "attr_name": "off", + "bits": "3:2", + "descr": "Off", + "value": "0x01;0x0", + "swpld_addr": "0x30", + "swpld_addr_offset": "0x84" + } + ] + } + }, + "PORT1": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT1", + "device_parent": "MUX3" + }, + "dev_attr": { + "dev_idx": "1" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT1-EEPROM" + }, + { + "itf": "control", + "dev": "PORT1-CTRL" + } + ] + } + }, + "PORT1-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT1-EEPROM", + "device_parent": "MUX3", + "virt_parent": "PORT1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x12", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT1-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT1-CTRL", + "device_parent": "MUX3", + "virt_parent": "PORT1" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x12", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x14", + "attr_mask": "0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x10", + "attr_mask": "0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x40", + "attr_mask": "0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x44", + "attr_mask": "0", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT2": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT2", + "device_parent": "MUX3" + }, + "dev_attr": { + "dev_idx": "2" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT2-EEPROM" + }, + { + "itf": "control", + "dev": "PORT2-CTRL" + } + ] + } + }, + "PORT2-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT2-EEPROM", + "device_parent": "MUX3", + "virt_parent": "PORT2" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x13", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT2-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT2-CTRL", + "device_parent": "MUX3", + "virt_parent": "PORT2" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x13", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x14", + "attr_mask": "1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x10", + "attr_mask": "1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x40", + "attr_mask": "1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x44", + "attr_mask": "1", + "attr_cmpval": "0x2", + "attr_len": "1" + } + ] + } + }, + "PORT3": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT3", + "device_parent": "MUX3" + }, + "dev_attr": { + "dev_idx": "3" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT3-EEPROM" + }, + { + "itf": "control", + "dev": "PORT3-CTRL" + } + ] + } + }, + "PORT3-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT3-EEPROM", + "device_parent": "MUX3", + "virt_parent": "PORT3" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x14", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT3-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT3-CTRL", + "device_parent": "MUX3", + "virt_parent": "PORT3" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x14", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x14", + "attr_mask": "2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x10", + "attr_mask": "2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x40", + "attr_mask": "2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x44", + "attr_mask": "2", + "attr_cmpval": "0x4", + "attr_len": "1" + } + ] + } + }, + "PORT4": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT4", + "device_parent": "MUX3" + }, + "dev_attr": { + "dev_idx": "4" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT4-EEPROM" + }, + { + "itf": "control", + "dev": "PORT4-CTRL" + } + ] + } + }, + "PORT4-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT4-EEPROM", + "device_parent": "MUX3", + "virt_parent": "PORT4" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x15", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT4-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT4-CTRL", + "device_parent": "MUX3", + "virt_parent": "PORT4" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x15", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x14", + "attr_mask": "3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x10", + "attr_mask": "3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x40", + "attr_mask": "3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x44", + "attr_mask": "3", + "attr_cmpval": "0x8", + "attr_len": "1" + } + ] + } + }, + "PORT5": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT5", + "device_parent": "MUX3" + }, + "dev_attr": { + "dev_idx": "5" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT5-EEPROM" + }, + { + "itf": "control", + "dev": "PORT5-CTRL" + } + ] + } + }, + "PORT5-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT5-EEPROM", + "device_parent": "MUX3", + "virt_parent": "PORT5" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x16", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT5-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT5-CTRL", + "device_parent": "MUX3", + "virt_parent": "PORT5" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x16", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x14", + "attr_mask": "4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x10", + "attr_mask": "4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x40", + "attr_mask": "4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x44", + "attr_mask": "4", + "attr_cmpval": "0x10", + "attr_len": "1" + } + ] + } + }, + "PORT6": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT6", + "device_parent": "MUX3" + }, + "dev_attr": { + "dev_idx": "6" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT6-EEPROM" + }, + { + "itf": "control", + "dev": "PORT6-CTRL" + } + ] + } + }, + "PORT6-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT6-EEPROM", + "device_parent": "MUX3", + "virt_parent": "PORT6" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x17", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT6-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT6-CTRL", + "device_parent": "MUX3", + "virt_parent": "PORT6" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x17", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x14", + "attr_mask": "5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x10", + "attr_mask": "5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x40", + "attr_mask": "5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x44", + "attr_mask": "5", + "attr_cmpval": "0x20", + "attr_len": "1" + } + ] + } + }, + "PORT7": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT7", + "device_parent": "MUX3" + }, + "dev_attr": { + "dev_idx": "7" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT7-EEPROM" + }, + { + "itf": "control", + "dev": "PORT7-CTRL" + } + ] + } + }, + "PORT7-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT7-EEPROM", + "device_parent": "MUX3", + "virt_parent": "PORT7" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x18", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT7-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT7-CTRL", + "device_parent": "MUX3", + "virt_parent": "PORT7" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x18", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x14", + "attr_mask": "6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x10", + "attr_mask": "6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x40", + "attr_mask": "6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x44", + "attr_mask": "6", + "attr_cmpval": "0x40", + "attr_len": "1" + } + ] + } + }, + "PORT8": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT8", + "device_parent": "MUX3" + }, + "dev_attr": { + "dev_idx": "8" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT8-EEPROM" + }, + { + "itf": "control", + "dev": "PORT8-CTRL" + } + ] + } + }, + "PORT8-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT8-EEPROM", + "device_parent": "MUX3", + "virt_parent": "PORT8" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x19", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT8-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT8-CTRL", + "device_parent": "MUX3", + "virt_parent": "PORT8" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x19", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x14", + "attr_mask": "7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x10", + "attr_mask": "7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x40", + "attr_mask": "7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x44", + "attr_mask": "7", + "attr_cmpval": "0x80", + "attr_len": "1" + } + ] + } + }, + "PORT9": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT9", + "device_parent": "MUX4" + }, + "dev_attr": { + "dev_idx": "9" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT9-EEPROM" + }, + { + "itf": "control", + "dev": "PORT9-CTRL" + } + ] + } + }, + "PORT9-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT9-EEPROM", + "device_parent": "MUX4", + "virt_parent": "PORT9" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1A", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT9-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT9-CTRL", + "device_parent": "MUX4", + "virt_parent": "PORT9" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1A", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x15", + "attr_mask": "0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x11", + "attr_mask": "0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x41", + "attr_mask": "0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x45", + "attr_mask": "0", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT10": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT10", + "device_parent": "MUX4" + }, + "dev_attr": { + "dev_idx": "10" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT10-EEPROM" + }, + { + "itf": "control", + "dev": "PORT10-CTRL" + } + ] + } + }, + "PORT10-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT10-EEPROM", + "device_parent": "MUX4", + "virt_parent": "PORT10" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1B", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT10-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT10-CTRL", + "device_parent": "MUX4", + "virt_parent": "PORT10" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1B", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x15", + "attr_mask": "1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x11", + "attr_mask": "1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x41", + "attr_mask": "1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x45", + "attr_mask": "1", + "attr_cmpval": "0x2", + "attr_len": "1" + } + ] + } + }, + "PORT11": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT11", + "device_parent": "MUX4" + }, + "dev_attr": { + "dev_idx": "11" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT11-EEPROM" + }, + { + "itf": "control", + "dev": "PORT11-CTRL" + } + ] + } + }, + "PORT11-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT11-EEPROM", + "device_parent": "MUX4", + "virt_parent": "PORT11" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1C", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT11-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT11-CTRL", + "device_parent": "MUX4", + "virt_parent": "PORT11" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1C", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x15", + "attr_mask": "2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x11", + "attr_mask": "2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x41", + "attr_mask": "2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x45", + "attr_mask": "2", + "attr_cmpval": "0x4", + "attr_len": "1" + } + ] + } + }, + "PORT12": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT12", + "device_parent": "MUX4" + }, + "dev_attr": { + "dev_idx": "12" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT12-EEPROM" + }, + { + "itf": "control", + "dev": "PORT12-CTRL" + } + ] + } + }, + "PORT12-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT12-EEPROM", + "device_parent": "MUX4", + "virt_parent": "PORT12" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1D", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT12-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT12-CTRL", + "device_parent": "MUX4", + "virt_parent": "PORT12" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1D", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x15", + "attr_mask": "3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x11", + "attr_mask": "3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x41", + "attr_mask": "3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x45", + "attr_mask": "3", + "attr_cmpval": "0x8", + "attr_len": "1" + } + ] + } + }, + "PORT13": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT13", + "device_parent": "MUX4" + }, + "dev_attr": { + "dev_idx": "13" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT13-EEPROM" + }, + { + "itf": "control", + "dev": "PORT13-CTRL" + } + ] + } + }, + "PORT13-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT13-EEPROM", + "device_parent": "MUX4", + "virt_parent": "PORT13" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1E", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT13-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT13-CTRL", + "device_parent": "MUX4", + "virt_parent": "PORT13" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1E", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x15", + "attr_mask": "4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x11", + "attr_mask": "4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x41", + "attr_mask": "4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x45", + "attr_mask": "4", + "attr_cmpval": "0x10", + "attr_len": "1" + } + ] + } + }, + "PORT14": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT14", + "device_parent": "MUX4" + }, + "dev_attr": { + "dev_idx": "14" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT14-EEPROM" + }, + { + "itf": "control", + "dev": "PORT14-CTRL" + } + ] + } + }, + "PORT14-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT14-EEPROM", + "device_parent": "MUX4", + "virt_parent": "PORT14" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1F", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT14-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT14-CTRL", + "device_parent": "MUX4", + "virt_parent": "PORT14" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x1F", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x15", + "attr_mask": "5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x11", + "attr_mask": "5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x41", + "attr_mask": "5", + "attr_cmpval": "0x20", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x45", + "attr_mask": "5", + "attr_cmpval": "0x20", + "attr_len": "1" + } + ] + } + }, + "PORT15": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT15", + "device_parent": "MUX4" + }, + "dev_attr": { + "dev_idx": "15" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT15-EEPROM" + }, + { + "itf": "control", + "dev": "PORT15-CTRL" + } + ] + } + }, + "PORT15-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT15-EEPROM", + "device_parent": "MUX4", + "virt_parent": "PORT15" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x20", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT15-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT15-CTRL", + "device_parent": "MUX4", + "virt_parent": "PORT15" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x20", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x15", + "attr_mask": "6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x11", + "attr_mask": "6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x41", + "attr_mask": "6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x45", + "attr_mask": "6", + "attr_cmpval": "0x40", + "attr_len": "1" + } + ] + } + }, + "PORT16": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT16", + "device_parent": "MUX4" + }, + "dev_attr": { + "dev_idx": "16" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT16-EEPROM" + }, + { + "itf": "control", + "dev": "PORT16-CTRL" + } + ] + } + }, + "PORT16-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT16-EEPROM", + "device_parent": "MUX4", + "virt_parent": "PORT16" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x21", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT16-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT16-CTRL", + "device_parent": "MUX4", + "virt_parent": "PORT16" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x21", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x15", + "attr_mask": "7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x11", + "attr_mask": "7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x41", + "attr_mask": "7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x45", + "attr_mask": "7", + "attr_cmpval": "0x80", + "attr_len": "1" + } + ] + } + }, + "PORT17": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT17", + "device_parent": "MUX5" + }, + "dev_attr": { + "dev_idx": "17" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT17-EEPROM" + }, + { + "itf": "control", + "dev": "PORT17-CTRL" + } + ] + } + }, + "PORT17-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT17-EEPROM", + "device_parent": "MUX5", + "virt_parent": "PORT17" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x22", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT17-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT17-CTRL", + "device_parent": "MUX5", + "virt_parent": "PORT17" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x22", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x16", + "attr_mask": "0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x12", + "attr_mask": "0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x42", + "attr_mask": "0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x46", + "attr_mask": "0", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT18": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT18", + "device_parent": "MUX5" + }, + "dev_attr": { + "dev_idx": "18" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT18-EEPROM" + }, + { + "itf": "control", + "dev": "PORT18-CTRL" + } + ] + } + }, + "PORT18-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT18-EEPROM", + "device_parent": "MUX5", + "virt_parent": "PORT18" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x23", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT18-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT18-CTRL", + "device_parent": "MUX5", + "virt_parent": "PORT18" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x23", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x16", + "attr_mask": "1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x12", + "attr_mask": "1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x42", + "attr_mask": "1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x46", + "attr_mask": "1", + "attr_cmpval": "0x2", + "attr_len": "1" + } + ] + } + }, + "PORT19": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT19", + "device_parent": "MUX5" + }, + "dev_attr": { + "dev_idx": "19" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT19-EEPROM" + }, + { + "itf": "control", + "dev": "PORT19-CTRL" + } + ] + } + }, + "PORT19-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT19-EEPROM", + "device_parent": "MUX5", + "virt_parent": "PORT19" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x24", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT19-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT19-CTRL", + "device_parent": "MUX5", + "virt_parent": "PORT19" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x24", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x16", + "attr_mask": "2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x12", + "attr_mask": "2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x42", + "attr_mask": "2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x46", + "attr_mask": "2", + "attr_cmpval": "0x4", + "attr_len": "1" + } + ] + } + }, + "PORT20": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT20", + "device_parent": "MUX5" + }, + "dev_attr": { + "dev_idx": "20" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT20-EEPROM" + }, + { + "itf": "control", + "dev": "PORT20-CTRL" + } + ] + } + }, + "PORT20-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT20-EEPROM", + "device_parent": "MUX5", + "virt_parent": "PORT20" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x25", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT20-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT20-CTRL", + "device_parent": "MUX5", + "virt_parent": "PORT20" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x25", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x16", + "attr_mask": "3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x12", + "attr_mask": "3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x42", + "attr_mask": "3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x46", + "attr_mask": "3", + "attr_cmpval": "0x8", + "attr_len": "1" + } + ] + } + }, + "PORT21": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT21", + "device_parent": "MUX5" + }, + "dev_attr": { + "dev_idx": "21" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT21-EEPROM" + }, + { + "itf": "control", + "dev": "PORT21-CTRL" + } + ] + } + }, + "PORT21-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT21-EEPROM", + "device_parent": "MUX5", + "virt_parent": "PORT21" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x26", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT21-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT21-CTRL", + "device_parent": "MUX5", + "virt_parent": "PORT21" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x26", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x16", + "attr_mask": "4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x12", + "attr_mask": "4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x42", + "attr_mask": "4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x46", + "attr_mask": "4", + "attr_cmpval": "0x10", + "attr_len": "1" + } + ] + } + }, + "PORT22": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT22", + "device_parent": "MUX5" + }, + "dev_attr": { + "dev_idx": "22" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT22-EEPROM" + }, + { + "itf": "control", + "dev": "PORT22-CTRL" + } + ] + } + }, + "PORT22-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT22-EEPROM", + "device_parent": "MUX5", + "virt_parent": "PORT22" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x27", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT22-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT22-CTRL", + "device_parent": "MUX5", + "virt_parent": "PORT22" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x27", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x16", + "attr_mask": "5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x12", + "attr_mask": "5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x42", + "attr_mask": "5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x46", + "attr_mask": "5", + "attr_cmpval": "0x20", + "attr_len": "1" + } + ] + } + }, + "PORT23": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT23", + "device_parent": "MUX5" + }, + "dev_attr": { + "dev_idx": "23" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT23-EEPROM" + }, + { + "itf": "control", + "dev": "PORT23-CTRL" + } + ] + } + }, + "PORT23-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT23-EEPROM", + "device_parent": "MUX5", + "virt_parent": "PORT23" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x28", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT23-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT23-CTRL", + "device_parent": "MUX5", + "virt_parent": "PORT23" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x28", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x16", + "attr_mask": "6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x12", + "attr_mask": "6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x42", + "attr_mask": "6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x46", + "attr_mask": "6", + "attr_cmpval": "0x40", + "attr_len": "1" + } + ] + } + }, + "PORT24": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT24", + "device_parent": "MUX5" + }, + "dev_attr": { + "dev_idx": "24" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT24-EEPROM" + }, + { + "itf": "control", + "dev": "PORT24-CTRL" + } + ] + } + }, + "PORT24-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT24-EEPROM", + "device_parent": "MUX5", + "virt_parent": "PORT24" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x29", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT24-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT24-CTRL", + "device_parent": "MUX5", + "virt_parent": "PORT24" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x29", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x16", + "attr_mask": "7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x12", + "attr_mask": "7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x42", + "attr_mask": "7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x46", + "attr_mask": "7", + "attr_cmpval": "0x80", + "attr_len": "1" + } + ] + } + }, + "PORT25": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT25", + "device_parent": "MUX6" + }, + "dev_attr": { + "dev_idx": "25" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT25-EEPROM" + }, + { + "itf": "control", + "dev": "PORT25-CTRL" + } + ] + } + }, + "PORT25-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT25-EEPROM", + "device_parent": "MUX6", + "virt_parent": "PORT25" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2A", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT25-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT25-CTRL", + "device_parent": "MUX6", + "virt_parent": "PORT25" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2A", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x17", + "attr_mask": "0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x13", + "attr_mask": "0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x43", + "attr_mask": "0", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x47", + "attr_mask": "0", + "attr_cmpval": "0x1", + "attr_len": "1" + } + ] + } + }, + "PORT26": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT26", + "device_parent": "MUX6" + }, + "dev_attr": { + "dev_idx": "26" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT26-EEPROM" + }, + { + "itf": "control", + "dev": "PORT26-CTRL" + } + ] + } + }, + "PORT26-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT26-EEPROM", + "device_parent": "MUX6", + "virt_parent": "PORT26" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2B", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT26-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT26-CTRL", + "device_parent": "MUX6", + "virt_parent": "PORT26" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2B", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x17", + "attr_mask": "1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x13", + "attr_mask": "1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x43", + "attr_mask": "1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x47", + "attr_mask": "1", + "attr_cmpval": "0x2", + "attr_len": "1" + } + ] + } + }, + "PORT27": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT27", + "device_parent": "MUX6" + }, + "dev_attr": { + "dev_idx": "27" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT27-EEPROM" + }, + { + "itf": "control", + "dev": "PORT27-CTRL" + } + ] + } + }, + "PORT27-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT27-EEPROM", + "device_parent": "MUX6", + "virt_parent": "PORT27" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2C", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT27-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT27-CTRL", + "device_parent": "MUX6", + "virt_parent": "PORT27" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2C", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x17", + "attr_mask": "2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x13", + "attr_mask": "2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x43", + "attr_mask": "2", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x47", + "attr_mask": "2", + "attr_cmpval": "0x4", + "attr_len": "1" + } + ] + } + }, + "PORT28": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT28", + "device_parent": "MUX6" + }, + "dev_attr": { + "dev_idx": "28" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT28-EEPROM" + }, + { + "itf": "control", + "dev": "PORT28-CTRL" + } + ] + } + }, + "PORT28-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT28-EEPROM", + "device_parent": "MUX6", + "virt_parent": "PORT28" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2D", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT28-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT28-CTRL", + "device_parent": "MUX6", + "virt_parent": "PORT28" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2D", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x17", + "attr_mask": "3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x13", + "attr_mask": "3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x43", + "attr_mask": "3", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x47", + "attr_mask": "3", + "attr_cmpval": "0x8", + "attr_len": "1" + } + ] + } + }, + "PORT29": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT29", + "device_parent": "MUX6" + }, + "dev_attr": { + "dev_idx": "29" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT29-EEPROM" + }, + { + "itf": "control", + "dev": "PORT29-CTRL" + } + ] + } + }, + "PORT29-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT29-EEPROM", + "device_parent": "MUX6", + "virt_parent": "PORT29" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2E", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT29-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT29-CTRL", + "device_parent": "MUX6", + "virt_parent": "PORT29" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2E", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x17", + "attr_mask": "4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x13", + "attr_mask": "4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x43", + "attr_mask": "4", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x47", + "attr_mask": "4", + "attr_cmpval": "0x10", + "attr_len": "1" + } + ] + } + }, + "PORT30": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT30", + "device_parent": "MUX6" + }, + "dev_attr": { + "dev_idx": "30" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT30-EEPROM" + }, + { + "itf": "control", + "dev": "PORT30-CTRL" + } + ] + } + }, + "PORT30-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT30-EEPROM", + "device_parent": "MUX6", + "virt_parent": "PORT30" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2F", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT30-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT30-CTRL", + "device_parent": "MUX6", + "virt_parent": "PORT30" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x2F", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x17", + "attr_mask": "5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x13", + "attr_mask": "5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x43", + "attr_mask": "5", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x47", + "attr_mask": "5", + "attr_cmpval": "0x20", + "attr_len": "1" + } + ] + } + }, + "PORT31": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT31", + "device_parent": "MUX6" + }, + "dev_attr": { + "dev_idx": "31" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT31-EEPROM" + }, + { + "itf": "control", + "dev": "PORT31-CTRL" + } + ] + } + }, + "PORT31-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT31-EEPROM", + "device_parent": "MUX6", + "virt_parent": "PORT31" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x30", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT31-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT31-CTRL", + "device_parent": "MUX6", + "virt_parent": "PORT31" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x30", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x17", + "attr_mask": "6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x13", + "attr_mask": "6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x43", + "attr_mask": "6", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x47", + "attr_mask": "6", + "attr_cmpval": "0x40", + "attr_len": "1" + } + ] + } + }, + "PORT32": { + "dev_info": { + "device_type": "QSFP", + "device_name": "PORT32", + "device_parent": "MUX6" + }, + "dev_attr": { + "dev_idx": "32" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT32-EEPROM" + }, + { + "itf": "control", + "dev": "PORT32-CTRL" + } + ] + } + }, + "PORT32-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT32-EEPROM", + "device_parent": "MUX6", + "virt_parent": "PORT32" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x31", + "dev_addr": "0x50", + "dev_type": "optoe1" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT32-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT32-CTRL", + "device_parent": "MUX6", + "virt_parent": "PORT32" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x31", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_intr_status", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x17", + "attr_mask": "7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x13", + "attr_mask": "7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_reset", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x43", + "attr_mask": "7", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_lpmode", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x47", + "attr_mask": "7", + "attr_cmpval": "0x80", + "attr_len": "1" + } + ] + } + }, + "PORT33": { + "dev_info": { + "device_type": "SFP", + "device_name": "PORT33", + "device_parent": "MUX7" + }, + "dev_attr": { + "dev_idx": "33" + }, + "i2c": { + "interface": [ + { + "itf": "eeprom", + "dev": "PORT33-EEPROM" + }, + { + "itf": "control", + "dev": "PORT33-CTRL" + } + ] + } + }, + "PORT33-EEPROM": { + "dev_info": { + "device_type": "", + "device_name": "PORT33", + "device_parent": "MUX7", + "virt_parent": "PORT33" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x33", + "dev_addr": "0x50", + "dev_type": "optoe2" + }, + "attr_list": [ + { + "attr_name": "eeprom" + } + ] + } + }, + "PORT33-CTRL": { + "dev_info": { + "device_type": "", + "device_name": "PORT33-CTRL", + "device_parent": "MUX7", + "virt_parent": "PORT33" + }, + "i2c": { + "topo_info": { + "parent_bus": "0x33", + "dev_addr": "0x53", + "dev_type": "pddf_xcvr" + }, + "attr_list": [ + { + "attr_name": "xcvr_present", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x18", + "attr_mask": "1", + "attr_cmpval": "0x0", + "attr_len": "1" + }, + { + "attr_name": "xcvr_rxlos", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x19", + "attr_mask": "1", + "attr_cmpval": "0x2", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txfault", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x1A", + "attr_mask": "1", + "attr_cmpval": "0x2", + "attr_len": "1" + }, + { + "attr_name": "xcvr_txdisable", + "attr_devaddr": "0x31", + "attr_devname": "CPLD2", + "attr_devtype": "cpld", + "attr_offset": "0x48", + "attr_mask": "1", + "attr_cmpval": "0x2", + "attr_len": "1" + } + ] + } + } + +} diff --git a/device/ufispace/x86_64-ufispace_s9110_32x-r0/pddf/pddf-device.json b/device/ufispace/x86_64-ufispace_s9110_32x-r0/pddf/pddf-device.json new file mode 120000 index 000000000000..28f5a100186a --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s9110_32x-r0/pddf/pddf-device.json @@ -0,0 +1 @@ +pddf-device-pvt.json \ No newline at end of file diff --git a/device/ufispace/x86_64-ufispace_s9110_32x-r0/pddf_support b/device/ufispace/x86_64-ufispace_s9110_32x-r0/pddf_support new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/device/ufispace/x86_64-ufispace_s9110_32x-r0/platform-beta.json b/device/ufispace/x86_64-ufispace_s9110_32x-r0/platform-beta.json new file mode 100644 index 000000000000..717adf878d7e --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s9110_32x-r0/platform-beta.json @@ -0,0 +1,596 @@ +{ + "chassis": { + "name": "S9110-32X", + "components": [ + { + "name": "CPLD1" + }, + { + "name": "CPLD2" + }, + { + "name": "BIOS" + }, + { + "name": "BMC" + } + ], + "fans": [ + { + "name": "Fantray1_1" + }, + { + "name": "Fantray1_2" + }, + { + "name": "Fantray2_1" + }, + { + "name": "Fantray2_2" + }, + { + "name": "Fantray3_1" + }, + { + "name": "Fantray3_2" + }, + { + "name": "Fantray4_1" + }, + { + "name": "Fantray4_2" + } + ], + "fan_drawers":[ + { + "name": "Fantray1", + "num_fans" : 2, + "fans": [ + { + "name": "Fantray1_1" + }, + { + "name": "Fantray1_2" + } + ] + }, + { + "name": "Fantray2", + "num_fans" : 2, + "fans": [ + { + "name": "Fantray2_1" + }, + { + "name": "Fantray2_2" + } + ] + }, + { + "name": "Fantray3", + "num_fans" : 2, + "fans": [ + { + "name": "Fantray3_1" + }, + { + "name": "Fantray3_2" + } + ] + } + ], + "psus": [ + { + "name": "PSU1", + "fans": [ + { + "name": "PSU1_FAN1" + } + ], + "thermals": [ + { + "name": "PSU1_TEMP1" + } + ] + }, + { + "name": "PSU2", + "fans": [ + { + "name": "PSU2_FAN1" + } + ], + "thermals": [ + { + "name": "PSU2_TEMP1" + } + ] + } + ], + "thermals": [ + { + "name": "TEMP_MAC" + }, + { + "name": "TEMP_ENV_MACCASE" + }, + { + "name": "TEMP_ENV_SSDCASE" + }, + { + "name": "TEMP_ENV_PSUCASE" + }, + { + "name": "TEMP_ENV_BMC" + }, + { + "name": "TEMP_PSU0_TEMP1" + }, + { + "name": "TEMP_PSU1_TEMP1" + } + ], + "sfps": [ + { + "name": "Ethernet0" + }, + { + "name": "Ethernet4" + }, + { + "name": "Ethernet8" + }, + { + "name": "Ethernet12" + }, + { + "name": "Ethernet16" + }, + { + "name": "Ethernet20" + }, + { + "name": "Ethernet24" + }, + { + "name": "Ethernet28" + }, + { + "name": "Ethernet32" + }, + { + "name": "Ethernet36" + }, + { + "name": "Ethernet40" + }, + { + "name": "Ethernet44" + }, + { + "name": "Ethernet48" + }, + { + "name": "Ethernet52" + }, + { + "name": "Ethernet56" + }, + { + "name": "Ethernet60" + }, + { + "name": "Ethernet64" + }, + { + "name": "Ethernet68" + }, + { + "name": "Ethernet72" + }, + { + "name": "Ethernet76" + }, + { + "name": "Ethernet80" + }, + { + "name": "Ethernet84" + }, + { + "name": "Ethernet88" + }, + { + "name": "Ethernet92" + }, + { + "name": "Ethernet96" + }, + { + "name": "Ethernet100" + }, + { + "name": "Ethernet104" + }, + { + "name": "Ethernet108" + }, + { + "name": "Ethernet112" + }, + { + "name": "Ethernet116" + }, + { + "name": "Ethernet120" + }, + { + "name": "Ethernet124" + }, + { + "name": "Ethernet128" + } + ] + }, + "interfaces": { + "Ethernet0": { + "index": "0,0,0,0", + "lanes": "1,2,3,4", + "breakout_modes": { + "1x100G[40G]": ["Eth0(Port0)"], + "2x50G": ["Eth0/1(Port0)", "Eth0/2(Port0)"], + "4x25G": ["Eth0/1(Port0)", "Eth0/2(Port0)", "Eth0/3(Port0)", "Eth0/4(Port0)"], + "4x10G": ["Eth0/1(Port0)", "Eth0/2(Port0)", "Eth0/3(Port0)", "Eth0/4(Port0)"] + } + }, + + "Ethernet4": { + "index": "1,1,1,1", + "lanes": "5,6,7,8", + "breakout_modes": { + "1x100G[40G]": ["Eth1(Port1)"], + "2x50G": ["Eth1/1(Port1)", "Eth1/2(Port1)"], + "4x25G": ["Eth1/1(Port1)", "Eth1/2(Port1)", "Eth1/3(Port1)", "Eth1/4(Port1)"], + "4x10G": ["Eth1/1(Port1)", "Eth1/2(Port1)", "Eth1/3(Port1)", "Eth1/4(Port1)"] + } + }, + + "Ethernet8": { + "index": "2,2,2,2", + "lanes": "9,10,11,12", + "breakout_modes": { + "1x100G[40G]": ["Eth2(Port2)"], + "2x50G": ["Eth2/1(Port2)", "Eth2/2(Port2)"], + "4x25G": ["Eth2/1(Port2)", "Eth2/2(Port2)", "Eth2/3(Port2)", "Eth2/4(Port2)"], + "4x10G": ["Eth2/1(Port2)", "Eth2/2(Port2)", "Eth2/3(Port2)", "Eth2/4(Port2)"] + } + }, + + "Ethernet12": { + "index": "3,3,3,3", + "lanes": "13,14,15,16", + "breakout_modes": { + "1x100G[40G]": ["Eth3(Port3)"], + "2x50G": ["Eth3/1(Port3)", "Eth3/2(Port3)"], + "4x25G": ["Eth3/1(Port3)", "Eth3/2(Port3)", "Eth3/3(Port3)", "Eth3/4(Port3)"], + "4x10G": ["Eth3/1(Port3)", "Eth3/2(Port3)", "Eth3/3(Port3)", "Eth3/4(Port3)"] + } + }, + + "Ethernet16": { + "index": "4,4,4,4", + "lanes": "17,18,19,20", + "breakout_modes": { + "1x100G[40G]": ["Eth4(Port4)"], + "2x50G": ["Eth4/1(Port4)", "Eth4/2(Port4)"], + "4x25G": ["Eth4/1(Port4)", "Eth4/2(Port4)", "Eth4/3(Port4)", "Eth4/4(Port4)"], + "4x10G": ["Eth4/1(Port4)", "Eth4/2(Port4)", "Eth4/3(Port4)", "Eth4/4(Port4)"] + } + }, + + "Ethernet20": { + "index": "5,5,5,5", + "lanes": "21,22,23,24", + "breakout_modes": { + "1x100G[40G]": ["Eth5(Port5)"], + "2x50G": ["Eth5/1(Port5)", "Eth5/2(Port5)"], + "4x25G": ["Eth5/1(Port5)", "Eth5/2(Port5)", "Eth5/3(Port5)", "Eth5/4(Port5)"], + "4x10G": ["Eth5/1(Port5)", "Eth5/2(Port5)", "Eth5/3(Port5)", "Eth5/4(Port5)"] + } + }, + + "Ethernet24": { + "index": "6,6,6,6", + "lanes": "25,26,27,28", + "breakout_modes": { + "1x100G[40G]": ["Eth6(Port6)"], + "2x50G": ["Eth6/1(Port6)", "Eth6/2(Port6)"], + "4x25G": ["Eth6/1(Port6)", "Eth6/2(Port6)", "Eth6/3(Port6)", "Eth6/4(Port6)"], + "4x10G": ["Eth6/1(Port6)", "Eth6/2(Port6)", "Eth6/3(Port6)", "Eth6/4(Port6)"] + } + }, + + "Ethernet28": { + "index": "7,7,7,7", + "lanes": "29,30,31,32", + "breakout_modes": { + "1x100G[40G]": ["Eth7(Port7)"], + "2x50G": ["Eth7/1(Port7)", "Eth7/2(Port7)"], + "4x25G": ["Eth7/1(Port7)", "Eth7/2(Port7)", "Eth7/3(Port7)", "Eth7/4(Port7)"], + "4x10G": ["Eth7/1(Port7)", "Eth7/2(Port7)", "Eth7/3(Port7)", "Eth7/4(Port7)"] + } + }, + + "Ethernet32": { + "index": "8,8,8,8", + "lanes": "33,34,35,36", + "breakout_modes": { + "1x100G[40G]": ["Eth8(Port8)"], + "2x50G": ["Eth8/1(Port8)", "Eth8/2(Port8)"], + "4x25G": ["Eth8/1(Port8)", "Eth8/2(Port8)", "Eth8/3(Port8)", "Eth8/4(Port8)"], + "4x10G": ["Eth8/1(Port8)", "Eth8/2(Port8)", "Eth8/3(Port8)", "Eth8/4(Port8)"] + } + }, + + "Ethernet36": { + "index": "9,9,9,9", + "lanes": "37,38,39,40", + "breakout_modes": { + "1x100G[40G]": ["Eth9(Port9)"], + "2x50G": ["Eth9/1(Port9)", "Eth9/2(Port9)"], + "4x25G": ["Eth9/1(Port9)", "Eth9/2(Port9)", "Eth9/3(Port9)", "Eth9/4(Port9)"], + "4x10G": ["Eth9/1(Port9)", "Eth9/2(Port9)", "Eth9/3(Port9)", "Eth9/4(Port9)"] + } + }, + + "Ethernet40": { + "index": "10,10,10,10", + "lanes": "41,42,43,44", + "breakout_modes": { + "1x100G[40G]": ["Eth10(Port10)"], + "2x50G": ["Eth10/1(Port10)", "Eth10/2(Port10)"], + "4x25G": ["Eth10/1(Port10)", "Eth10/2(Port10)", "Eth10/3(Port10)", "Eth10/4(Port10)"], + "4x10G": ["Eth10/1(Port10)", "Eth10/2(Port10)", "Eth10/3(Port10)", "Eth10/4(Port10)"] + } + }, + + "Ethernet44": { + "index": "11,11,11,11", + "lanes": "45,46,47,48", + "breakout_modes": { + "1x100G[40G]": ["Eth11(Port11)"], + "2x50G": ["Eth11/1(Port11)", "Eth11/2(Port11)"], + "4x25G": ["Eth11/1(Port11)", "Eth11/2(Port11)", "Eth11/3(Port11)", "Eth11/4(Port11)"], + "4x10G": ["Eth11/1(Port11)", "Eth11/2(Port11)", "Eth11/3(Port11)", "Eth11/4(Port11)"] + } + }, + + "Ethernet48": { + "index": "12,12,12,12", + "lanes": "49,50,51,52", + "breakout_modes": { + "1x100G[40G]": ["Eth12(Port12)"], + "2x50G": ["Eth12/1(Port12)", "Eth12/2(Port12)"], + "4x25G": ["Eth12/1(Port12)", "Eth12/2(Port12)", "Eth12/3(Port12)", "Eth12/4(Port12)"], + "4x10G": ["Eth12/1(Port12)", "Eth12/2(Port12)", "Eth12/3(Port12)", "Eth12/4(Port12)"] + } + }, + + "Ethernet52": { + "index": "13,13,13,13", + "lanes": "53,54,55,56", + "breakout_modes": { + "1x100G[40G]": ["Eth13(Port13)"], + "2x50G": ["Eth13/1(Port13)", "Eth13/2(Port13)"], + "4x25G": ["Eth13/1(Port13)", "Eth13/2(Port13)", "Eth13/3(Port13)", "Eth13/4(Port13)"], + "4x10G": ["Eth13/1(Port13)", "Eth13/2(Port13)", "Eth13/3(Port13)", "Eth13/4(Port13)"] + } + }, + + "Ethernet56": { + "index": "14,14,14,14", + "lanes": "57,58,59,60", + "breakout_modes": { + "1x100G[40G]": ["Eth14(Port14)"], + "2x50G": ["Eth14/1(Port14)", "Eth14/2(Port14)"], + "4x25G": ["Eth14/1(Port14)", "Eth14/2(Port14)", "Eth14/3(Port14)", "Eth14/4(Port14)"], + "4x10G": ["Eth14/1(Port14)", "Eth14/2(Port14)", "Eth14/3(Port14)", "Eth14/4(Port14)"] + } + }, + + "Ethernet60": { + "index": "15,15,15,15", + "lanes": "61,62,63,64", + "breakout_modes": { + "1x100G[40G]": ["Eth15(Port15)"], + "2x50G": ["Eth15/1(Port15)", "Eth15/2(Port15)"], + "4x25G": ["Eth15/1(Port15)", "Eth15/2(Port15)", "Eth15/3(Port15)", "Eth15/4(Port15)"], + "4x10G": ["Eth15/1(Port15)", "Eth15/2(Port15)", "Eth15/3(Port15)", "Eth15/4(Port15)"] + } + }, + + "Ethernet64": { + "index": "16,16,16,16", + "lanes": "69,70,71,72", + "breakout_modes": { + "1x100G[40G]": ["Eth16(Port16)"], + "2x50G": ["Eth16/1(Port16)", "Eth16/2(Port16)"], + "4x25G": ["Eth16/1(Port16)", "Eth16/2(Port16)", "Eth16/3(Port16)", "Eth16/4(Port16)"], + "4x10G": ["Eth16/1(Port16)", "Eth16/2(Port16)", "Eth16/3(Port16)", "Eth16/4(Port16)"] + } + }, + + "Ethernet68": { + "index": "17,17,17,17", + "lanes": "65,66,67,68", + "breakout_modes": { + "1x100G[40G]": ["Eth17(Port17)"], + "2x50G": ["Eth17/1(Port17)", "Eth17/2(Port17)"], + "4x25G": ["Eth17/1(Port17)", "Eth17/2(Port17)", "Eth17/3(Port17)", "Eth17/4(Port17)"], + "4x10G": ["Eth17/1(Port17)", "Eth17/2(Port17)", "Eth17/3(Port17)", "Eth17/4(Port17)"] + } + }, + + "Ethernet72": { + "index": "18,18,18,18", + "lanes": "77,78,79,80", + "breakout_modes": { + "1x100G[40G]": ["Eth18(Port18)"], + "2x50G": ["Eth18/1(Port18)", "Eth18/2(Port18)"], + "4x25G": ["Eth18/1(Port18)", "Eth18/2(Port18)", "Eth18/3(Port18)", "Eth18/4(Port18)"], + "4x10G": ["Eth18/1(Port18)", "Eth18/2(Port18)", "Eth18/3(Port18)", "Eth18/4(Port18)"] + } + }, + + "Ethernet76": { + "index": "19,19,19,19", + "lanes": "73,74,75,76", + "breakout_modes": { + "1x100G[40G]": ["Eth19(Port19)"], + "2x50G": ["Eth19/1(Port19)", "Eth19/2(Port19)"], + "4x25G": ["Eth19/1(Port19)", "Eth19/2(Port19)", "Eth19/3(Port19)", "Eth19/4(Port19)"], + "4x10G": ["Eth19/1(Port19)", "Eth19/2(Port19)", "Eth19/3(Port19)", "Eth19/4(Port19)"] + } + }, + + "Ethernet80": { + "index": "20,20,20,20", + "lanes": "85,86,87,88", + "breakout_modes": { + "1x100G[40G]": ["Eth20(Port20)"], + "2x50G": ["Eth20/1(Port20)", "Eth20/2(Port20)"], + "4x25G": ["Eth20/1(Port20)", "Eth20/2(Port20)", "Eth20/3(Port20)", "Eth20/4(Port20)"], + "4x10G": ["Eth20/1(Port20)", "Eth20/2(Port20)", "Eth20/3(Port20)", "Eth20/4(Port20)"] + } + }, + + "Ethernet84": { + "index": "21,21,21,21", + "lanes": "81,82,83,84", + "breakout_modes": { + "1x100G[40G]": ["Eth21(Port21)"], + "2x50G": ["Eth21/1(Port21)", "Eth21/2(Port21)"], + "4x25G": ["Eth21/1(Port21)", "Eth21/2(Port21)", "Eth21/3(Port21)", "Eth21/4(Port21)"], + "4x10G": ["Eth21/1(Port21)", "Eth21/2(Port21)", "Eth21/3(Port21)", "Eth21/4(Port21)"] + } + }, + + "Ethernet88": { + "index": "22,22,22,22", + "lanes": "93,94,95,96", + "breakout_modes": { + "1x100G[40G]": ["Eth22(Port22)"], + "2x50G": ["Eth22/1(Port22)", "Eth22/2(Port22)"], + "4x25G": ["Eth22/1(Port22)", "Eth22/2(Port22)", "Eth22/3(Port22)", "Eth22/4(Port22)"], + "4x10G": ["Eth22/1(Port22)", "Eth22/2(Port22)", "Eth22/3(Port22)", "Eth22/4(Port22)"] + } + }, + + "Ethernet92": { + "index": "23,23,23,23", + "lanes": "89,90,91,92", + "breakout_modes": { + "1x100G[40G]": ["Eth23(Port23)"], + "2x50G": ["Eth23/1(Port23)", "Eth23/2(Port23)"], + "4x25G": ["Eth23/1(Port23)", "Eth23/2(Port23)", "Eth23/3(Port23)", "Eth23/4(Port23)"], + "4x10G": ["Eth23/1(Port23)", "Eth23/2(Port23)", "Eth23/3(Port23)", "Eth23/4(Port23)"] + } + }, + + "Ethernet96": { + "index": "24,24,24,24", + "lanes": "101,102,103,104", + "breakout_modes": { + "1x100G[40G]": ["Eth24(Port24)"], + "2x50G": ["Eth24/1(Port24)", "Eth24/2(Port24)"], + "4x25G": ["Eth24/1(Port24)", "Eth24/2(Port24)", "Eth24/3(Port24)", "Eth24/4(Port24)"], + "4x10G": ["Eth24/1(Port24)", "Eth24/2(Port24)", "Eth24/3(Port24)", "Eth24/4(Port24)"] + } + }, + + "Ethernet100": { + "index": "25,25,25,25", + "lanes": "97,98,99,100", + "breakout_modes": { + "1x100G[40G]": ["Eth25(Port25)"], + "2x50G": ["Eth25/1(Port25)", "Eth25/2(Port25)"], + "4x25G": ["Eth25/1(Port25)", "Eth25/2(Port25)", "Eth25/3(Port25)", "Eth25/4(Port25)"], + "4x10G": ["Eth25/1(Port25)", "Eth25/2(Port25)", "Eth25/3(Port25)", "Eth25/4(Port25)"] + } + }, + + "Ethernet104": { + "index": "26,26,26,26", + "lanes": "109,110,111,112", + "breakout_modes": { + "1x100G[40G]": ["Eth26(Port26)"], + "2x50G": ["Eth26/1(Port26)", "Eth26/2(Port26)"], + "4x25G": ["Eth26/1(Port26)", "Eth26/2(Port26)", "Eth26/3(Port26)", "Eth26/4(Port26)"], + "4x10G": ["Eth26/1(Port26)", "Eth26/2(Port26)", "Eth26/3(Port26)", "Eth26/4(Port26)"] + } + }, + + "Ethernet108": { + "index": "27,27,27,27", + "lanes": "105,106,107,108", + "breakout_modes": { + "1x100G[40G]": ["Eth27(Port27)"], + "2x50G": ["Eth27/1(Port27)", "Eth27/2(Port27)"], + "4x25G": ["Eth27/1(Port27)", "Eth27/2(Port27)", "Eth27/3(Port27)", "Eth27/4(Port27)"], + "4x10G": ["Eth27/1(Port27)", "Eth27/2(Port27)", "Eth27/3(Port27)", "Eth27/4(Port27)"] + } + }, + + "Ethernet112": { + "index": "28,28,28,28", + "lanes": "117,118,119,120", + "breakout_modes": { + "1x100G[40G]": ["Eth28(Port28)"], + "2x50G": ["Eth28/1(Port28)", "Eth28/2(Port28)"], + "4x25G": ["Eth28/1(Port28)", "Eth28/2(Port28)", "Eth28/3(Port28)", "Eth28/4(Port28)"], + "4x10G": ["Eth28/1(Port28)", "Eth28/2(Port28)", "Eth28/3(Port28)", "Eth28/4(Port28)"] + } + }, + + "Ethernet116": { + "index": "29,29,29,29", + "lanes": "113,114,115,116", + "breakout_modes": { + "1x100G[40G]": ["Eth29(Port29)"], + "2x50G": ["Eth29/1(Port29)", "Eth29/2(Port29)"], + "4x25G": ["Eth29/1(Port29)", "Eth29/2(Port29)", "Eth29/3(Port29)", "Eth29/4(Port29)"], + "4x10G": ["Eth29/1(Port29)", "Eth29/2(Port29)", "Eth29/3(Port29)", "Eth29/4(Port29)"] + } + }, + + "Ethernet120": { + "index": "30,30,30,30", + "lanes": "125,126,127,128", + "breakout_modes": { + "1x100G[40G]": ["Eth30(Port30)"], + "2x50G": ["Eth30/1(Port30)", "Eth30/2(Port30)"], + "4x25G": ["Eth30/1(Port30)", "Eth30/2(Port30)", "Eth30/3(Port30)", "Eth30/4(Port30)"], + "4x10G": ["Eth30/1(Port30)", "Eth30/2(Port30)", "Eth30/3(Port30)", "Eth30/4(Port30)"] + } + }, + + "Ethernet124": { + "index": "31,31,31,31", + "lanes": "121,122,123,124", + "breakout_modes": { + "1x100G[40G]": ["Eth31(Port31)"], + "2x50G": ["Eth31/1(Port31)", "Eth31/2(Port31)"], + "4x25G": ["Eth31/1(Port31)", "Eth31/2(Port31)", "Eth31/3(Port31)", "Eth31/4(Port31)"], + "4x10G": ["Eth31/1(Port31)", "Eth31/2(Port31)", "Eth31/3(Port31)", "Eth31/4(Port31)"] + } + }, + "Ethernet128": { + "index": "32", + "lanes": "129", + "breakout_modes": { + "1x10G": ["Eth32(Port32)"] + } + } + } +} + diff --git a/device/ufispace/x86_64-ufispace_s9110_32x-r0/platform-pvt.json b/device/ufispace/x86_64-ufispace_s9110_32x-r0/platform-pvt.json new file mode 100644 index 000000000000..6114bf5ef460 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s9110_32x-r0/platform-pvt.json @@ -0,0 +1,590 @@ +{ + "chassis": { + "name": "S9110-32X", + "components": [ + { + "name": "CPLD1" + }, + { + "name": "CPLD2" + }, + { + "name": "BIOS" + }, + { + "name": "BMC" + } + ], + "fans": [ + { + "name": "Fantray1_1" + }, + { + "name": "Fantray1_2" + }, + { + "name": "Fantray2_1" + }, + { + "name": "Fantray2_2" + }, + { + "name": "Fantray3_1" + }, + { + "name": "Fantray3_2" + } + ], + "fan_drawers":[ + { + "name": "Fantray1", + "num_fans" : 2, + "fans": [ + { + "name": "Fantray1_1" + }, + { + "name": "Fantray1_2" + } + ] + }, + { + "name": "Fantray2", + "num_fans" : 2, + "fans": [ + { + "name": "Fantray2_1" + }, + { + "name": "Fantray2_2" + } + ] + }, + { + "name": "Fantray3", + "num_fans" : 2, + "fans": [ + { + "name": "Fantray3_1" + }, + { + "name": "Fantray3_2" + } + ] + } + ], + "psus": [ + { + "name": "PSU1", + "fans": [ + { + "name": "PSU1_FAN1" + } + ], + "thermals": [ + { + "name": "PSU1_TEMP1" + } + ] + }, + { + "name": "PSU2", + "fans": [ + { + "name": "PSU2_FAN1" + } + ], + "thermals": [ + { + "name": "PSU2_TEMP1" + } + ] + } + ], + "thermals": [ + { + "name": "TEMP_MAC" + }, + { + "name": "TEMP_ENV_MACCASE" + }, + { + "name": "TEMP_ENV_SSDCASE" + }, + { + "name": "TEMP_ENV_PSUCASE" + }, + { + "name": "TEMP_ENV_BMC" + }, + { + "name": "TEMP_PSU0_TEMP1" + }, + { + "name": "TEMP_PSU1_TEMP1" + } + ], + "sfps": [ + { + "name": "Ethernet0" + }, + { + "name": "Ethernet4" + }, + { + "name": "Ethernet8" + }, + { + "name": "Ethernet12" + }, + { + "name": "Ethernet16" + }, + { + "name": "Ethernet20" + }, + { + "name": "Ethernet24" + }, + { + "name": "Ethernet28" + }, + { + "name": "Ethernet32" + }, + { + "name": "Ethernet36" + }, + { + "name": "Ethernet40" + }, + { + "name": "Ethernet44" + }, + { + "name": "Ethernet48" + }, + { + "name": "Ethernet52" + }, + { + "name": "Ethernet56" + }, + { + "name": "Ethernet60" + }, + { + "name": "Ethernet64" + }, + { + "name": "Ethernet68" + }, + { + "name": "Ethernet72" + }, + { + "name": "Ethernet76" + }, + { + "name": "Ethernet80" + }, + { + "name": "Ethernet84" + }, + { + "name": "Ethernet88" + }, + { + "name": "Ethernet92" + }, + { + "name": "Ethernet96" + }, + { + "name": "Ethernet100" + }, + { + "name": "Ethernet104" + }, + { + "name": "Ethernet108" + }, + { + "name": "Ethernet112" + }, + { + "name": "Ethernet116" + }, + { + "name": "Ethernet120" + }, + { + "name": "Ethernet124" + }, + { + "name": "Ethernet128" + } + ] + }, + "interfaces": { + "Ethernet0": { + "index": "0,0,0,0", + "lanes": "1,2,3,4", + "breakout_modes": { + "1x100G[40G]": ["Eth0(Port0)"], + "2x50G": ["Eth0/1(Port0)", "Eth0/2(Port0)"], + "4x25G": ["Eth0/1(Port0)", "Eth0/2(Port0)", "Eth0/3(Port0)", "Eth0/4(Port0)"], + "4x10G": ["Eth0/1(Port0)", "Eth0/2(Port0)", "Eth0/3(Port0)", "Eth0/4(Port0)"] + } + }, + + "Ethernet4": { + "index": "1,1,1,1", + "lanes": "5,6,7,8", + "breakout_modes": { + "1x100G[40G]": ["Eth1(Port1)"], + "2x50G": ["Eth1/1(Port1)", "Eth1/2(Port1)"], + "4x25G": ["Eth1/1(Port1)", "Eth1/2(Port1)", "Eth1/3(Port1)", "Eth1/4(Port1)"], + "4x10G": ["Eth1/1(Port1)", "Eth1/2(Port1)", "Eth1/3(Port1)", "Eth1/4(Port1)"] + } + }, + + "Ethernet8": { + "index": "2,2,2,2", + "lanes": "9,10,11,12", + "breakout_modes": { + "1x100G[40G]": ["Eth2(Port2)"], + "2x50G": ["Eth2/1(Port2)", "Eth2/2(Port2)"], + "4x25G": ["Eth2/1(Port2)", "Eth2/2(Port2)", "Eth2/3(Port2)", "Eth2/4(Port2)"], + "4x10G": ["Eth2/1(Port2)", "Eth2/2(Port2)", "Eth2/3(Port2)", "Eth2/4(Port2)"] + } + }, + + "Ethernet12": { + "index": "3,3,3,3", + "lanes": "13,14,15,16", + "breakout_modes": { + "1x100G[40G]": ["Eth3(Port3)"], + "2x50G": ["Eth3/1(Port3)", "Eth3/2(Port3)"], + "4x25G": ["Eth3/1(Port3)", "Eth3/2(Port3)", "Eth3/3(Port3)", "Eth3/4(Port3)"], + "4x10G": ["Eth3/1(Port3)", "Eth3/2(Port3)", "Eth3/3(Port3)", "Eth3/4(Port3)"] + } + }, + + "Ethernet16": { + "index": "4,4,4,4", + "lanes": "17,18,19,20", + "breakout_modes": { + "1x100G[40G]": ["Eth4(Port4)"], + "2x50G": ["Eth4/1(Port4)", "Eth4/2(Port4)"], + "4x25G": ["Eth4/1(Port4)", "Eth4/2(Port4)", "Eth4/3(Port4)", "Eth4/4(Port4)"], + "4x10G": ["Eth4/1(Port4)", "Eth4/2(Port4)", "Eth4/3(Port4)", "Eth4/4(Port4)"] + } + }, + + "Ethernet20": { + "index": "5,5,5,5", + "lanes": "21,22,23,24", + "breakout_modes": { + "1x100G[40G]": ["Eth5(Port5)"], + "2x50G": ["Eth5/1(Port5)", "Eth5/2(Port5)"], + "4x25G": ["Eth5/1(Port5)", "Eth5/2(Port5)", "Eth5/3(Port5)", "Eth5/4(Port5)"], + "4x10G": ["Eth5/1(Port5)", "Eth5/2(Port5)", "Eth5/3(Port5)", "Eth5/4(Port5)"] + } + }, + + "Ethernet24": { + "index": "6,6,6,6", + "lanes": "25,26,27,28", + "breakout_modes": { + "1x100G[40G]": ["Eth6(Port6)"], + "2x50G": ["Eth6/1(Port6)", "Eth6/2(Port6)"], + "4x25G": ["Eth6/1(Port6)", "Eth6/2(Port6)", "Eth6/3(Port6)", "Eth6/4(Port6)"], + "4x10G": ["Eth6/1(Port6)", "Eth6/2(Port6)", "Eth6/3(Port6)", "Eth6/4(Port6)"] + } + }, + + "Ethernet28": { + "index": "7,7,7,7", + "lanes": "29,30,31,32", + "breakout_modes": { + "1x100G[40G]": ["Eth7(Port7)"], + "2x50G": ["Eth7/1(Port7)", "Eth7/2(Port7)"], + "4x25G": ["Eth7/1(Port7)", "Eth7/2(Port7)", "Eth7/3(Port7)", "Eth7/4(Port7)"], + "4x10G": ["Eth7/1(Port7)", "Eth7/2(Port7)", "Eth7/3(Port7)", "Eth7/4(Port7)"] + } + }, + + "Ethernet32": { + "index": "8,8,8,8", + "lanes": "33,34,35,36", + "breakout_modes": { + "1x100G[40G]": ["Eth8(Port8)"], + "2x50G": ["Eth8/1(Port8)", "Eth8/2(Port8)"], + "4x25G": ["Eth8/1(Port8)", "Eth8/2(Port8)", "Eth8/3(Port8)", "Eth8/4(Port8)"], + "4x10G": ["Eth8/1(Port8)", "Eth8/2(Port8)", "Eth8/3(Port8)", "Eth8/4(Port8)"] + } + }, + + "Ethernet36": { + "index": "9,9,9,9", + "lanes": "37,38,39,40", + "breakout_modes": { + "1x100G[40G]": ["Eth9(Port9)"], + "2x50G": ["Eth9/1(Port9)", "Eth9/2(Port9)"], + "4x25G": ["Eth9/1(Port9)", "Eth9/2(Port9)", "Eth9/3(Port9)", "Eth9/4(Port9)"], + "4x10G": ["Eth9/1(Port9)", "Eth9/2(Port9)", "Eth9/3(Port9)", "Eth9/4(Port9)"] + } + }, + + "Ethernet40": { + "index": "10,10,10,10", + "lanes": "41,42,43,44", + "breakout_modes": { + "1x100G[40G]": ["Eth10(Port10)"], + "2x50G": ["Eth10/1(Port10)", "Eth10/2(Port10)"], + "4x25G": ["Eth10/1(Port10)", "Eth10/2(Port10)", "Eth10/3(Port10)", "Eth10/4(Port10)"], + "4x10G": ["Eth10/1(Port10)", "Eth10/2(Port10)", "Eth10/3(Port10)", "Eth10/4(Port10)"] + } + }, + + "Ethernet44": { + "index": "11,11,11,11", + "lanes": "45,46,47,48", + "breakout_modes": { + "1x100G[40G]": ["Eth11(Port11)"], + "2x50G": ["Eth11/1(Port11)", "Eth11/2(Port11)"], + "4x25G": ["Eth11/1(Port11)", "Eth11/2(Port11)", "Eth11/3(Port11)", "Eth11/4(Port11)"], + "4x10G": ["Eth11/1(Port11)", "Eth11/2(Port11)", "Eth11/3(Port11)", "Eth11/4(Port11)"] + } + }, + + "Ethernet48": { + "index": "12,12,12,12", + "lanes": "49,50,51,52", + "breakout_modes": { + "1x100G[40G]": ["Eth12(Port12)"], + "2x50G": ["Eth12/1(Port12)", "Eth12/2(Port12)"], + "4x25G": ["Eth12/1(Port12)", "Eth12/2(Port12)", "Eth12/3(Port12)", "Eth12/4(Port12)"], + "4x10G": ["Eth12/1(Port12)", "Eth12/2(Port12)", "Eth12/3(Port12)", "Eth12/4(Port12)"] + } + }, + + "Ethernet52": { + "index": "13,13,13,13", + "lanes": "53,54,55,56", + "breakout_modes": { + "1x100G[40G]": ["Eth13(Port13)"], + "2x50G": ["Eth13/1(Port13)", "Eth13/2(Port13)"], + "4x25G": ["Eth13/1(Port13)", "Eth13/2(Port13)", "Eth13/3(Port13)", "Eth13/4(Port13)"], + "4x10G": ["Eth13/1(Port13)", "Eth13/2(Port13)", "Eth13/3(Port13)", "Eth13/4(Port13)"] + } + }, + + "Ethernet56": { + "index": "14,14,14,14", + "lanes": "57,58,59,60", + "breakout_modes": { + "1x100G[40G]": ["Eth14(Port14)"], + "2x50G": ["Eth14/1(Port14)", "Eth14/2(Port14)"], + "4x25G": ["Eth14/1(Port14)", "Eth14/2(Port14)", "Eth14/3(Port14)", "Eth14/4(Port14)"], + "4x10G": ["Eth14/1(Port14)", "Eth14/2(Port14)", "Eth14/3(Port14)", "Eth14/4(Port14)"] + } + }, + + "Ethernet60": { + "index": "15,15,15,15", + "lanes": "61,62,63,64", + "breakout_modes": { + "1x100G[40G]": ["Eth15(Port15)"], + "2x50G": ["Eth15/1(Port15)", "Eth15/2(Port15)"], + "4x25G": ["Eth15/1(Port15)", "Eth15/2(Port15)", "Eth15/3(Port15)", "Eth15/4(Port15)"], + "4x10G": ["Eth15/1(Port15)", "Eth15/2(Port15)", "Eth15/3(Port15)", "Eth15/4(Port15)"] + } + }, + + "Ethernet64": { + "index": "16,16,16,16", + "lanes": "69,70,71,72", + "breakout_modes": { + "1x100G[40G]": ["Eth16(Port16)"], + "2x50G": ["Eth16/1(Port16)", "Eth16/2(Port16)"], + "4x25G": ["Eth16/1(Port16)", "Eth16/2(Port16)", "Eth16/3(Port16)", "Eth16/4(Port16)"], + "4x10G": ["Eth16/1(Port16)", "Eth16/2(Port16)", "Eth16/3(Port16)", "Eth16/4(Port16)"] + } + }, + + "Ethernet68": { + "index": "17,17,17,17", + "lanes": "65,66,67,68", + "breakout_modes": { + "1x100G[40G]": ["Eth17(Port17)"], + "2x50G": ["Eth17/1(Port17)", "Eth17/2(Port17)"], + "4x25G": ["Eth17/1(Port17)", "Eth17/2(Port17)", "Eth17/3(Port17)", "Eth17/4(Port17)"], + "4x10G": ["Eth17/1(Port17)", "Eth17/2(Port17)", "Eth17/3(Port17)", "Eth17/4(Port17)"] + } + }, + + "Ethernet72": { + "index": "18,18,18,18", + "lanes": "77,78,79,80", + "breakout_modes": { + "1x100G[40G]": ["Eth18(Port18)"], + "2x50G": ["Eth18/1(Port18)", "Eth18/2(Port18)"], + "4x25G": ["Eth18/1(Port18)", "Eth18/2(Port18)", "Eth18/3(Port18)", "Eth18/4(Port18)"], + "4x10G": ["Eth18/1(Port18)", "Eth18/2(Port18)", "Eth18/3(Port18)", "Eth18/4(Port18)"] + } + }, + + "Ethernet76": { + "index": "19,19,19,19", + "lanes": "73,74,75,76", + "breakout_modes": { + "1x100G[40G]": ["Eth19(Port19)"], + "2x50G": ["Eth19/1(Port19)", "Eth19/2(Port19)"], + "4x25G": ["Eth19/1(Port19)", "Eth19/2(Port19)", "Eth19/3(Port19)", "Eth19/4(Port19)"], + "4x10G": ["Eth19/1(Port19)", "Eth19/2(Port19)", "Eth19/3(Port19)", "Eth19/4(Port19)"] + } + }, + + "Ethernet80": { + "index": "20,20,20,20", + "lanes": "85,86,87,88", + "breakout_modes": { + "1x100G[40G]": ["Eth20(Port20)"], + "2x50G": ["Eth20/1(Port20)", "Eth20/2(Port20)"], + "4x25G": ["Eth20/1(Port20)", "Eth20/2(Port20)", "Eth20/3(Port20)", "Eth20/4(Port20)"], + "4x10G": ["Eth20/1(Port20)", "Eth20/2(Port20)", "Eth20/3(Port20)", "Eth20/4(Port20)"] + } + }, + + "Ethernet84": { + "index": "21,21,21,21", + "lanes": "81,82,83,84", + "breakout_modes": { + "1x100G[40G]": ["Eth21(Port21)"], + "2x50G": ["Eth21/1(Port21)", "Eth21/2(Port21)"], + "4x25G": ["Eth21/1(Port21)", "Eth21/2(Port21)", "Eth21/3(Port21)", "Eth21/4(Port21)"], + "4x10G": ["Eth21/1(Port21)", "Eth21/2(Port21)", "Eth21/3(Port21)", "Eth21/4(Port21)"] + } + }, + + "Ethernet88": { + "index": "22,22,22,22", + "lanes": "93,94,95,96", + "breakout_modes": { + "1x100G[40G]": ["Eth22(Port22)"], + "2x50G": ["Eth22/1(Port22)", "Eth22/2(Port22)"], + "4x25G": ["Eth22/1(Port22)", "Eth22/2(Port22)", "Eth22/3(Port22)", "Eth22/4(Port22)"], + "4x10G": ["Eth22/1(Port22)", "Eth22/2(Port22)", "Eth22/3(Port22)", "Eth22/4(Port22)"] + } + }, + + "Ethernet92": { + "index": "23,23,23,23", + "lanes": "89,90,91,92", + "breakout_modes": { + "1x100G[40G]": ["Eth23(Port23)"], + "2x50G": ["Eth23/1(Port23)", "Eth23/2(Port23)"], + "4x25G": ["Eth23/1(Port23)", "Eth23/2(Port23)", "Eth23/3(Port23)", "Eth23/4(Port23)"], + "4x10G": ["Eth23/1(Port23)", "Eth23/2(Port23)", "Eth23/3(Port23)", "Eth23/4(Port23)"] + } + }, + + "Ethernet96": { + "index": "24,24,24,24", + "lanes": "101,102,103,104", + "breakout_modes": { + "1x100G[40G]": ["Eth24(Port24)"], + "2x50G": ["Eth24/1(Port24)", "Eth24/2(Port24)"], + "4x25G": ["Eth24/1(Port24)", "Eth24/2(Port24)", "Eth24/3(Port24)", "Eth24/4(Port24)"], + "4x10G": ["Eth24/1(Port24)", "Eth24/2(Port24)", "Eth24/3(Port24)", "Eth24/4(Port24)"] + } + }, + + "Ethernet100": { + "index": "25,25,25,25", + "lanes": "97,98,99,100", + "breakout_modes": { + "1x100G[40G]": ["Eth25(Port25)"], + "2x50G": ["Eth25/1(Port25)", "Eth25/2(Port25)"], + "4x25G": ["Eth25/1(Port25)", "Eth25/2(Port25)", "Eth25/3(Port25)", "Eth25/4(Port25)"], + "4x10G": ["Eth25/1(Port25)", "Eth25/2(Port25)", "Eth25/3(Port25)", "Eth25/4(Port25)"] + } + }, + + "Ethernet104": { + "index": "26,26,26,26", + "lanes": "109,110,111,112", + "breakout_modes": { + "1x100G[40G]": ["Eth26(Port26)"], + "2x50G": ["Eth26/1(Port26)", "Eth26/2(Port26)"], + "4x25G": ["Eth26/1(Port26)", "Eth26/2(Port26)", "Eth26/3(Port26)", "Eth26/4(Port26)"], + "4x10G": ["Eth26/1(Port26)", "Eth26/2(Port26)", "Eth26/3(Port26)", "Eth26/4(Port26)"] + } + }, + + "Ethernet108": { + "index": "27,27,27,27", + "lanes": "105,106,107,108", + "breakout_modes": { + "1x100G[40G]": ["Eth27(Port27)"], + "2x50G": ["Eth27/1(Port27)", "Eth27/2(Port27)"], + "4x25G": ["Eth27/1(Port27)", "Eth27/2(Port27)", "Eth27/3(Port27)", "Eth27/4(Port27)"], + "4x10G": ["Eth27/1(Port27)", "Eth27/2(Port27)", "Eth27/3(Port27)", "Eth27/4(Port27)"] + } + }, + + "Ethernet112": { + "index": "28,28,28,28", + "lanes": "117,118,119,120", + "breakout_modes": { + "1x100G[40G]": ["Eth28(Port28)"], + "2x50G": ["Eth28/1(Port28)", "Eth28/2(Port28)"], + "4x25G": ["Eth28/1(Port28)", "Eth28/2(Port28)", "Eth28/3(Port28)", "Eth28/4(Port28)"], + "4x10G": ["Eth28/1(Port28)", "Eth28/2(Port28)", "Eth28/3(Port28)", "Eth28/4(Port28)"] + } + }, + + "Ethernet116": { + "index": "29,29,29,29", + "lanes": "113,114,115,116", + "breakout_modes": { + "1x100G[40G]": ["Eth29(Port29)"], + "2x50G": ["Eth29/1(Port29)", "Eth29/2(Port29)"], + "4x25G": ["Eth29/1(Port29)", "Eth29/2(Port29)", "Eth29/3(Port29)", "Eth29/4(Port29)"], + "4x10G": ["Eth29/1(Port29)", "Eth29/2(Port29)", "Eth29/3(Port29)", "Eth29/4(Port29)"] + } + }, + + "Ethernet120": { + "index": "30,30,30,30", + "lanes": "125,126,127,128", + "breakout_modes": { + "1x100G[40G]": ["Eth30(Port30)"], + "2x50G": ["Eth30/1(Port30)", "Eth30/2(Port30)"], + "4x25G": ["Eth30/1(Port30)", "Eth30/2(Port30)", "Eth30/3(Port30)", "Eth30/4(Port30)"], + "4x10G": ["Eth30/1(Port30)", "Eth30/2(Port30)", "Eth30/3(Port30)", "Eth30/4(Port30)"] + } + }, + + "Ethernet124": { + "index": "31,31,31,31", + "lanes": "121,122,123,124", + "breakout_modes": { + "1x100G[40G]": ["Eth31(Port31)"], + "2x50G": ["Eth31/1(Port31)", "Eth31/2(Port31)"], + "4x25G": ["Eth31/1(Port31)", "Eth31/2(Port31)", "Eth31/3(Port31)", "Eth31/4(Port31)"], + "4x10G": ["Eth31/1(Port31)", "Eth31/2(Port31)", "Eth31/3(Port31)", "Eth31/4(Port31)"] + } + }, + "Ethernet128": { + "index": "32", + "lanes": "129", + "breakout_modes": { + "1x10G": ["Eth32(Port32)"] + } + } + } +} + diff --git a/device/ufispace/x86_64-ufispace_s9110_32x-r0/platform.json b/device/ufispace/x86_64-ufispace_s9110_32x-r0/platform.json new file mode 120000 index 000000000000..bb59660c3c3a --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s9110_32x-r0/platform.json @@ -0,0 +1 @@ +platform-pvt.json \ No newline at end of file diff --git a/device/ufispace/x86_64-ufispace_s9110_32x-r0/platform_asic b/device/ufispace/x86_64-ufispace_s9110_32x-r0/platform_asic new file mode 100644 index 000000000000..960467652765 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s9110_32x-r0/platform_asic @@ -0,0 +1 @@ +broadcom diff --git a/device/ufispace/x86_64-ufispace_s9110_32x-r0/platform_components.json b/device/ufispace/x86_64-ufispace_s9110_32x-r0/platform_components.json new file mode 100644 index 000000000000..a5bb2093cbaa --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s9110_32x-r0/platform_components.json @@ -0,0 +1,12 @@ +{ + "chassis": { + "x86_64-ufispace_s9110_32x-r0": { + "component": { + "CPLD1": { }, + "CPLD2": { }, + "BIOS": { }, + "BMC": {} + } + } + } +} diff --git a/device/ufispace/x86_64-ufispace_s9110_32x-r0/platform_env.conf b/device/ufispace/x86_64-ufispace_s9110_32x-r0/platform_env.conf new file mode 100644 index 000000000000..77fd88ac3678 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s9110_32x-r0/platform_env.conf @@ -0,0 +1 @@ +SYNCD_SHM_SIZE=256m diff --git a/device/ufispace/x86_64-ufispace_s9110_32x-r0/pmon_daemon_control.json b/device/ufispace/x86_64-ufispace_s9110_32x-r0/pmon_daemon_control.json new file mode 100644 index 000000000000..e348e0168fa5 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s9110_32x-r0/pmon_daemon_control.json @@ -0,0 +1,9 @@ +{ + "skip_pcied": false, + "skip_fancontrol": false, + "skip_thermalctld": false, + "skip_ledd": true, + "skip_xcvrd": false, + "skip_psud": false, + "skip_syseepromd": false +} diff --git a/device/ufispace/x86_64-ufispace_s9110_32x-r0/sensors.conf b/device/ufispace/x86_64-ufispace_s9110_32x-r0/sensors.conf new file mode 100644 index 000000000000..29e3604b4127 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s9110_32x-r0/sensors.conf @@ -0,0 +1 @@ +# libsensors configuration file \ No newline at end of file diff --git a/device/ufispace/x86_64-ufispace_s9110_32x-r0/system_health_monitoring_config.json b/device/ufispace/x86_64-ufispace_s9110_32x-r0/system_health_monitoring_config.json new file mode 100644 index 000000000000..43816ab55169 --- /dev/null +++ b/device/ufispace/x86_64-ufispace_s9110_32x-r0/system_health_monitoring_config.json @@ -0,0 +1,15 @@ +{ + "services_to_ignore": [], + "devices_to_ignore": [ + "asic", + "psu", + "fan" + ], + "user_defined_checkers": [], + "polling_interval": 60, + "led_color": { + "fault": "yellow_blink", + "normal": "green", + "booting": "green_blink" + } +} \ No newline at end of file diff --git a/dockers/docker-config-engine-bullseye/Dockerfile.j2 b/dockers/docker-config-engine-bullseye/Dockerfile.j2 index f6804de903be..700af660a91d 100644 --- a/dockers/docker-config-engine-bullseye/Dockerfile.j2 +++ b/dockers/docker-config-engine-bullseye/Dockerfile.j2 @@ -23,6 +23,10 @@ RUN apt-get install -y \ RUN pip3 install pyangbind==0.8.1 RUN pip3 uninstall -y enum34 +# Fix armhf build failure +# The option --no-build-isolation can be removed when upgrading PyYAML to 6.0.1 +RUN pip3 install PyYAML==5.4.1 --no-build-isolation + # Install python-redis RUN pip3 install redis==4.5.4 diff --git a/dockers/docker-config-engine-buster/Dockerfile.j2 b/dockers/docker-config-engine-buster/Dockerfile.j2 index 084956eed5f5..cfa61bc0ba8c 100644 --- a/dockers/docker-config-engine-buster/Dockerfile.j2 +++ b/dockers/docker-config-engine-buster/Dockerfile.j2 @@ -23,6 +23,10 @@ RUN apt-get install -y \ RUN pip3 install pyangbind==0.8.1 RUN pip3 uninstall -y enum34 +# Fix armhf build failure +# The option --no-build-isolation can be removed when upgrading PyYAML to 6.0.1 +RUN pip3 install PyYAML==5.4.1 --no-build-isolation + # Install python-redis RUN pip3 install redis==4.5.4 diff --git a/dockers/docker-dhcp-relay/dhcpv6-relay.agents.j2 b/dockers/docker-dhcp-relay/dhcpv6-relay.agents.j2 index 8f83e05efc7c..e392711f5326 100644 --- a/dockers/docker-dhcp-relay/dhcpv6-relay.agents.j2 +++ b/dockers/docker-dhcp-relay/dhcpv6-relay.agents.j2 @@ -13,7 +13,7 @@ [program:dhcp6relay] command=/usr/sbin/dhcp6relay {#- Dual ToR Option #} -{% if 'subtype' in DEVICE_METADATA['localhost'] and DEVICE_METADATA['localhost']['subtype'] == 'DualToR' %} -d{% endif %} +{% if 'subtype' in DEVICE_METADATA['localhost'] and DEVICE_METADATA['localhost']['subtype'] == 'DualToR' %} -u Loopback0 {% endif %} priority=3 autostart=false diff --git a/dockers/docker-fpm-frr/frr/bgpd/bgpd.main.conf.j2 b/dockers/docker-fpm-frr/frr/bgpd/bgpd.main.conf.j2 index 1e564579e30f..793ab055c215 100644 --- a/dockers/docker-fpm-frr/frr/bgpd/bgpd.main.conf.j2 +++ b/dockers/docker-fpm-frr/frr/bgpd/bgpd.main.conf.j2 @@ -104,6 +104,9 @@ router bgp {{ DEVICE_METADATA['localhost']['bgp_asn'] }} network {{ get_ipv6_loopback_address(LOOPBACK_INTERFACE, "Loopback0") | ip }}/128 {% else %} network {{ get_ipv6_loopback_address(LOOPBACK_INTERFACE, "Loopback0") | ip }}/64 +{% if DEVICE_METADATA['localhost']['switch_type'] == 'voq' or DEVICE_METADATA['localhost']['switch_type'] == 'chassis-packet' %} + network {{ get_ipv6_loopback_address(LOOPBACK_INTERFACE, "Loopback0") | ip }}/128 route-map HIDE_INTERNAL +{% endif %} {% endif %} exit-address-family {% endif %} diff --git a/dockers/docker-fpm-frr/frr/bgpd/templates/sentinels/instance.conf.j2 b/dockers/docker-fpm-frr/frr/bgpd/templates/sentinels/instance.conf.j2 new file mode 100644 index 000000000000..951138507689 --- /dev/null +++ b/dockers/docker-fpm-frr/frr/bgpd/templates/sentinels/instance.conf.j2 @@ -0,0 +1,31 @@ +! +! template: bgpd/templates/sentinels/instance.conf.j2 +! + neighbor {{ bgp_session['name'] }} peer-group + neighbor {{ bgp_session['name'] }} remote-as {{ bgp_asn }} +{% if bgp_session['src_address'] is defined %} + neighbor {{ bgp_session['name'] }} update-source {{ bgp_session['src_address'] | ip }} +{% endif %} +{% for ip_range in bgp_session['ip_range'].split(',') %} + bgp listen range {{ ip_range }} peer-group {{ bgp_session['name'] }} +{% endfor %} +! + address-family ipv4 + neighbor {{ bgp_session['name'] }} activate + neighbor {{ bgp_session['name'] }} addpath-tx-all-paths + neighbor {{ bgp_session['name'] }} soft-reconfiguration inbound + neighbor {{ bgp_session['name'] }} route-map FROM_BGP_SENTINEL in + neighbor {{ bgp_session['name'] }} route-map TO_BGP_SENTINEL out + neighbor {{ bgp_session['name'] }} maximum-prefix 200 + exit-address-family + address-family ipv6 + neighbor {{ bgp_session['name'] }} activate + neighbor {{ bgp_session['name'] }} addpath-tx-all-paths + neighbor {{ bgp_session['name'] }} soft-reconfiguration inbound + neighbor {{ bgp_session['name'] }} route-map FROM_BGP_SENTINEL in + neighbor {{ bgp_session['name'] }} route-map TO_BGP_SENTINEL out + neighbor {{ bgp_session['name'] }} maximum-prefix 200 + exit-address-family +! +! end of template: bgpd/templates/sentinels/instance.conf.j2 +! diff --git a/dockers/docker-fpm-frr/frr/bgpd/templates/sentinels/peer-group.conf.j2 b/dockers/docker-fpm-frr/frr/bgpd/templates/sentinels/peer-group.conf.j2 new file mode 100644 index 000000000000..dcbc3fb578b8 --- /dev/null +++ b/dockers/docker-fpm-frr/frr/bgpd/templates/sentinels/peer-group.conf.j2 @@ -0,0 +1,7 @@ +! +! template: bgpd/templates/sentinels/peer-group.conf.j2 +! +! nothing is here +! +! end of template: bgpd/templates/sentinels/peer-group.conf.j2 +! diff --git a/dockers/docker-fpm-frr/frr/bgpd/templates/sentinels/policies.conf.j2 b/dockers/docker-fpm-frr/frr/bgpd/templates/sentinels/policies.conf.j2 new file mode 100644 index 000000000000..46a72344f341 --- /dev/null +++ b/dockers/docker-fpm-frr/frr/bgpd/templates/sentinels/policies.conf.j2 @@ -0,0 +1,16 @@ +! +! template: bgpd/templates/sentinels/policies.conf.j2 +! +{% if constants.bgp.sentinel_community is defined %} +bgp community-list standard sentinel_community permit {{ constants.bgp.sentinel_community }} +! +route-map FROM_BGP_SENTINEL permit 100 + match community sentinel_community +{% endif %} +! +route-map FROM_BGP_SENTINEL deny 200 +! +route-map TO_BGP_SENTINEL permit 100 +! +! end of template: bgpd/templates/sentinels/policies.conf.j2 +! diff --git a/dockers/docker-orchagent/orchagent.sh b/dockers/docker-orchagent/orchagent.sh index 7585e4896cf4..45571944db30 100755 --- a/dockers/docker-orchagent/orchagent.sh +++ b/dockers/docker-orchagent/orchagent.sh @@ -17,8 +17,8 @@ fi mkdir -p /var/log/swss ORCHAGENT_ARGS="-d /var/log/swss " -# Set orchagent pop batch size to 8192 -ORCHAGENT_ARGS+="-b 8192 " +# Set orchagent pop batch size to 1024 +ORCHAGENT_ARGS+="-b 1024 " # Set synchronous mode if it is enabled in CONFIG_DB SYNC_MODE=$(echo $SWSS_VARS | jq -r '.synchronous_mode') diff --git a/dockers/docker-snmp/snmpd.conf.j2 b/dockers/docker-snmp/snmpd.conf.j2 index cf7f8f385138..182056b636e1 100644 --- a/dockers/docker-snmp/snmpd.conf.j2 +++ b/dockers/docker-snmp/snmpd.conf.j2 @@ -30,16 +30,27 @@ agentAddress {{ protocol(agentip) }}:[{{ agentip }}]{% if port %}:{{ port }}{% e {% endfor %} {% elif NAMESPACE_COUNT is not defined or NAMESPACE_COUNT|int <= 1 %} {% if MGMT_INTERFACE is defined %} -{% for if, ip in MGMT_INTERFACE %} -{% set agentip = ip.split('/')[0] %} -agentAddress {{ protocol(agentip) }}:[{{ agentip }}]:161 +{% for intf, ip in MGMT_INTERFACE %} +{% set agentip = ip.split('/')[0]|lower %} +{% set zoneid = '' %} +# Use interface as zoneid for link local ipv6 +{% if agentip.startswith('fe80') %} +{% set zoneid = '%' + intf %} +{% endif %} +agentAddress {{ protocol(agentip) }}:[{{ agentip }}{{ zoneid }}]:161 {% endfor %} {% endif %} {% if LOOPBACK_INTERFACE is defined %} {% for lo in LOOPBACK_INTERFACE %} {% if lo | length == 2 %} -{% set agentip = lo[1].split('/')[0] %} -agentAddress {{ protocol(agentip) }}:[{{ agentip }}]:161 +{% set intf = lo[0] %} +{% set agentip = lo[1].split('/')[0]|lower %} +{% set zoneid = '' %} +# Use interface as zoneid for link local ipv6 +{% if agentip.startswith('fe80') %} +{% set zoneid = '%' + intf %} +{% endif %} +agentAddress {{ protocol(agentip) }}:[{{ agentip }}{{ zoneid }}]:161 {% endif %} {% endfor %} {% endif %} diff --git a/dockers/docker-sonic-mgmt/Dockerfile.j2 b/dockers/docker-sonic-mgmt/Dockerfile.j2 index 0a5e31eac415..a91d4bac4af8 100755 --- a/dockers/docker-sonic-mgmt/Dockerfile.j2 +++ b/dockers/docker-sonic-mgmt/Dockerfile.j2 @@ -46,7 +46,7 @@ RUN pip3 install aiohttp \ azure-kusto-data \ azure-kusto-ingest \ defusedxml \ - celery[redis]==4.4.7 \ + celery[redis]==5.2.7 \ cffi \ contextlib2==0.6.0.post1 \ cryptography==3.3.2 \ @@ -54,7 +54,7 @@ RUN pip3 install aiohttp \ "future>=0.16.0" \ gitpython \ ipaddr \ - ipython==5.4.1 \ + ipython==8.12.2 \ ixnetwork-restpy==1.0.64 \ ixnetwork-open-traffic-generator==0.0.79 \ jinja2==2.10.1 \ @@ -210,6 +210,27 @@ RUN dpkg -i \ debs/{{ deb }}{{' '}} {%- endfor %} +# Install protobuf 3.21.12 +RUN mkdir -p /tmp/protobuf \ + && cd /tmp/protobuf \ + && wget https://sonicstorage.blob.core.windows.net/public/ubuntu/20.04/libprotobuf-dev_3.21.12-3_amd64.deb \ + && wget https://sonicstorage.blob.core.windows.net/public/ubuntu/20.04/libprotobuf-lite32_3.21.12-3_amd64.deb \ + && wget https://sonicstorage.blob.core.windows.net/public/ubuntu/20.04/libprotobuf32_3.21.12-3_amd64.deb \ + && wget https://sonicstorage.blob.core.windows.net/public/ubuntu/20.04/libprotoc-dev_3.21.12-3_amd64.deb \ + && wget https://sonicstorage.blob.core.windows.net/public/ubuntu/20.04/libprotoc32_3.21.12-3_amd64.deb \ + && wget https://sonicstorage.blob.core.windows.net/public/ubuntu/20.04/protobuf-compiler_3.21.12-3_amd64.deb \ + && wget https://sonicstorage.blob.core.windows.net/public/ubuntu/20.04/python3-protobuf_3.21.12-3_amd64.deb \ + && dpkg -i *.deb \ + && rm -rf /tmp/protobuf + +# Install dash-api +RUN cd /tmp \ + && mkdir -p /usr/lib/python3/dist-packages/dash_api \ + && wget https://raw.githubusercontent.com/sonic-net/sonic-buildimage/master/src/sonic-dash-api/pypkg/__init__.py -O /usr/lib/python3/dist-packages/dash_api/__init__.py \ + && git clone https://github.com/sonic-net/sonic-dash-api.git \ + && protoc -I=sonic-dash-api/proto --python_out=/usr/lib/python3/dist-packages/dash_api sonic-dash-api/proto/*.proto \ + && rm -rf /tmp/sonic-dash-api + RUN mkdir /var/run/sshd EXPOSE 22 @@ -242,7 +263,7 @@ WORKDIR /var/$user # Add az symlink for backwards compatibility RUN mkdir bin && ln -s /usr/bin/az bin/az -RUN python3 -m venv env-python3 +RUN python3 -m venv --system-site-packages env-python3 # Activating a virtualenv. The virtualenv automatically works for RUN, ENV and CMD. ENV VIRTUAL_ENV=env-python3 @@ -259,7 +280,7 @@ RUN python3 -m pip install aiohttp \ azure-kusto-data \ azure-kusto-ingest \ defusedxml \ - celery[redis]==4.4.7 \ + celery[redis]==5.2.7 \ cffi \ contextlib2==0.6.0.post1 \ cryptography==3.3.2 \ @@ -267,7 +288,7 @@ RUN python3 -m pip install aiohttp \ "future>=0.16.0" \ gitpython \ ipaddr \ - ipython==5.4.1 \ + ipython==8.12.2 \ ixnetwork-restpy==1.0.64 \ ixnetwork-open-traffic-generator==0.0.79 \ jinja2==2.10.1 \ diff --git a/files/Aboot/boot0.j2 b/files/Aboot/boot0.j2 index c35302e126e3..898eb0bcdde3 100644 --- a/files/Aboot/boot0.j2 +++ b/files/Aboot/boot0.j2 @@ -554,6 +554,9 @@ write_platform_specific_cmdline() { if [ "$sid" = "BlackhawkT4DD" ]; then aboot_machine=arista_7050dx4_32s fi + if [ "$sid" = "BlackhawkTH4DD" ] || [ "$sid" = "BlackhawkTh4Dd" ]; then + aboot_machine=arista_7060dx5_32 + fi if [ "$sid" = "Smartsville" ]; then aboot_machine=arista_7280cr3_32p4 fi diff --git a/files/build/versions/build/build-sonic-slave-bullseye/versions-deb-bullseye b/files/build/versions/build/build-sonic-slave-bullseye/versions-deb-bullseye index 55ab22200759..da953843ce6f 100644 --- a/files/build/versions/build/build-sonic-slave-bullseye/versions-deb-bullseye +++ b/files/build/versions/build/build-sonic-slave-bullseye/versions-deb-bullseye @@ -24,6 +24,7 @@ libsairedis==1.0.0 libsairedis-dev==1.0.0 libsaithrift-dev==0.9.4 libsaivs==1.0.0 +libsaivs-dev==1.0.0 libswsscommon==1.0.0 libswsscommon-dev==1.0.0 libtac-dev==1.4.1-1 @@ -33,7 +34,7 @@ libteam-utils==1.30-1 libteam5==1.30-1 libteamdctl0==1.30-1 libthrift-0.11.0==0.11.0-4 -libthrift-dev==0.14.1 +libthrift-dev==0.11.0-4 libthrift0==0.14.1 libyang==1.0.73 libyang-cpp==1.0.73 @@ -43,7 +44,6 @@ linux-headers-5.10.0-18-2-common==5.10.140-1 lldpd==1.0.4-1 lm-sensors==1:3.6.0-7 mft==4.22.1-15 -mlnx-sai==1.mlnx.SAIBuild2305.24.0.1 net-tools==1.60+git20181103.0eebece-1 protobuf-compiler==3.21.12-3 python-thrift==0.11.0-4 @@ -74,7 +74,7 @@ sxd-libs==1.mlnx.4.5.5142 sxd-libs-dev==1.mlnx.4.5.5142 syncd==1.0.0 syncd-vs==1.0.0 -thrift-compiler==0.14.1 +thrift-compiler==0.11.0-4 wjh-libs==1.mlnx.4.5.5142 wjh-libs-dev==1.mlnx.4.5.5142 wpasupplicant==2:2.9.0-14 diff --git a/files/build/versions/default/versions-git b/files/build/versions/default/versions-git index ae358adf44e1..5257da550715 100644 --- a/files/build/versions/default/versions-git +++ b/files/build/versions/default/versions-git @@ -1,11 +1,11 @@ -https://chromium.googlesource.com/chromium/tools/depot_tools.git==247429efd9e04d492ff5fe756818661d7feb7889 +https://chromium.googlesource.com/chromium/tools/depot_tools.git==d411904b84c0d9f539bbdc84e3d63f9f282c658b https://github.com/aristanetworks/swi-tools.git==b5f087e4774168bf536360d43c9c509c8f14ad9f https://github.com/CESNET/libyang.git==ea94c8b9f513f8a6ddc6ce1540fa41eaf4c8922a https://github.com/daveolson53/audisp-tacplus.git==559c9f22edd4f2dea0ecedffb3ad9502b12a75b6 https://github.com/daveolson53/libnss-tacplus.git==19008ab68d9d504aa58eb34d5f564755a1613b8b https://github.com/dyninc/OpenBFDD.git==e35f43ad8d2b3f084e96a84c392528a90d05a287 -https://github.com/flashrom/flashrom.git==b66f4766b5d7dc614ad609f27dd2794e06b5e2a4 -https://github.com/FreeRADIUS/freeradius-server.git==02df5b27df68396150c6424d2a16618f361329af +https://github.com/flashrom/flashrom.git==2b692d78c2ab8cb1ba68516cb4bd2ceae80d8936 +https://github.com/FreeRADIUS/freeradius-server.git==1be5b1d181b5c51c34dc4b7f8e639082f80d6c87 https://github.com/FreeRADIUS/pam_radius.git==8d373539bb9f13b0abfe8bcae0095a930a00fad0 https://github.com/jeroennijhof/pam_tacplus.git==4284d9016e64def2bb81d5f50f96dc3b59bfdc39 https://github.com/jpirko/libteam.git==7cb5de8b01be132bd4150eff460bfd83296414b6 @@ -21,4 +21,4 @@ https://salsa.debian.org/debian/libteam.git==48142125234a665ad5367b724af36a58fb4 https://salsa.debian.org/kernel-team/ethtool/==d0578651310379629399dde060577d4b9b0bcab1 https://salsa.debian.org/kernel-team/initramfs-tools.git==193dfbb7929e518976f89f6c8dd9201982e56f80 https://salsa.debian.org/sk-guest/monit.git==c9da7ebb1f35dfba17b50b5969a6e75e29cbec0d -https://salsa.debian.org/ssh-team/openssh.git==74d15e80b8730335a9b13469ca6cafe4c1c8e485 +https://salsa.debian.org/ssh-team/openssh.git==d9a514f93f17d22766cfe760e25254ef13cb5eb1 diff --git a/files/build/versions/default/versions-mirror b/files/build/versions/default/versions-mirror index 70254c9d8fdc..3615751938ee 100644 --- a/files/build/versions/default/versions-mirror +++ b/files/build/versions/default/versions-mirror @@ -1,15 +1,15 @@ deb.nodesource.com_node%5f14.x_dists_bullseye==2023-02-17T00:35:28Z deb.nodesource.com_node%5f14.x_dists_buster==2023-02-17T00:35:28Z -debian==20230707T000210Z -debian-security==20230707T000202Z +debian==20230723T000130Z +debian-security==20230723T000131Z download.docker.com_linux_debian_dists_bullseye==2023-07-07T20:10:57Z download.docker.com_linux_debian_dists_buster==2023-07-07T20:10:57Z packages.microsoft.com_repos_sonic-dev_dists_jessie==2022-10-31T19:34:29Z -packages.trafficmanager.net_snapshot_debian-security_20230707T000202Z_dists_bullseye-security==2023-07-06T20:09:13Z -packages.trafficmanager.net_snapshot_debian-security_20230707T000202Z_dists_buster_updates==2023-07-06T20:09:13Z -packages.trafficmanager.net_snapshot_debian_20230707T000210Z_dists_bullseye==2023-06-10T08:52:21Z -packages.trafficmanager.net_snapshot_debian_20230707T000210Z_dists_bullseye-backports==2023-07-06T20:09:27Z -packages.trafficmanager.net_snapshot_debian_20230707T000210Z_dists_bullseye-updates==2023-07-06T20:09:28Z -packages.trafficmanager.net_snapshot_debian_20230707T000210Z_dists_buster==2023-06-10T08:53:33Z -packages.trafficmanager.net_snapshot_debian_20230707T000210Z_dists_buster-backports==2023-07-06T20:09:27Z -packages.trafficmanager.net_snapshot_debian_20230707T000210Z_dists_buster-updates==2023-06-10T08:55:10Z +packages.trafficmanager.net_snapshot_debian-security_20230723T000131Z_dists_bullseye-security==2023-07-22T08:48:51Z +packages.trafficmanager.net_snapshot_debian-security_20230723T000131Z_dists_buster_updates==2023-07-22T08:48:51Z +packages.trafficmanager.net_snapshot_debian_20230723T000130Z_dists_bullseye==2023-06-10T08:52:21Z +packages.trafficmanager.net_snapshot_debian_20230723T000130Z_dists_bullseye-backports==2023-07-22T20:31:09Z +packages.trafficmanager.net_snapshot_debian_20230723T000130Z_dists_bullseye-updates==2023-07-22T20:31:09Z +packages.trafficmanager.net_snapshot_debian_20230723T000130Z_dists_buster==2023-06-10T08:53:33Z +packages.trafficmanager.net_snapshot_debian_20230723T000130Z_dists_buster-backports==2023-07-22T20:31:09Z +packages.trafficmanager.net_snapshot_debian_20230723T000130Z_dists_buster-updates==2023-06-10T08:55:10Z diff --git a/files/build/versions/default/versions-web b/files/build/versions/default/versions-web index a569f211b972..f4ff7b5914fb 100644 --- a/files/build/versions/default/versions-web +++ b/files/build/versions/default/versions-web @@ -31,7 +31,7 @@ https://deb.debian.org/debian/pool/main/k/kdump-tools/kdump-tools_1.6.8.4.tar.xz https://deb.nodesource.com/gpgkey/nodesource.gpg.key==003b51a89a133b5db4cca98b2dea3117 https://deb.nodesource.com/node_14.x/dists/bullseye/Release==6b7d50c433d129d4c6fd95bdf56070fa https://deb.nodesource.com/node_14.x/dists/buster/Release==42875141604382f0abb4d047f645dfe1 -https://deb.nodesource.com/setup_14.x==1c9de9348c0acd5f2ee422a6d0c333b3 +https://deb.nodesource.com/setup_14.x==472c9614e7c6dd029f205890ed356a22 https://download.docker.com/linux/debian/gpg==1afae06b34a13c1b3d9cb61a26285a15 https://github.com/aristanetworks/sonic-firmware/raw/446f30ccd8626f904d89d5798da7294948e090a6/phy/phy-credo_1.0_amd64.deb==6c3d6c32477615cbe049b9161ce15bd5 https://github.com/barefootnetworks/sonic-release-pkgs/raw/dev/bfnplatform_20221130_sai_1.11.0_deb11.deb==4a77e5f35b75ad7ce062f631581b40e2 @@ -49,6 +49,8 @@ https://github.com/Marvell-switching/sonic-marvell-binaries/raw/master/armhf/sai https://github.com/Mellanox/Spectrum-SDK-Drivers-SONiC-Bins/releases/download/fw-2010.5144/fw-SPC-rel-13_2010_5144-EVB.mfa==49de2652fc105ce1d8624d15cb02033d https://github.com/Mellanox/Spectrum-SDK-Drivers-SONiC-Bins/releases/download/fw-2010.5144/fw-SPC2-rel-29_2010_5144-EVB.mfa==0415936df3dfbbed9015d30b8244d110 https://github.com/Mellanox/Spectrum-SDK-Drivers-SONiC-Bins/releases/download/fw-2010.5144/fw-SPC3-rel-30_2010_5144-EVB.mfa==c0b6b9d92320341da004c22ce14c2e52 +https://github.com/Mellanox/Spectrum-SDK-Drivers-SONiC-Bins/releases/download/sai-SAIBuild2305.24.0.1-bullseye-amd64/mlnx-sai-dbgsym_1.mlnx.SAIBuild2305.24.0.1_amd64.deb==796605c9b759059c2b3ee099d924d76c +https://github.com/Mellanox/Spectrum-SDK-Drivers-SONiC-Bins/releases/download/sai-SAIBuild2305.24.0.1-bullseye-amd64/mlnx-sai_1.mlnx.SAIBuild2305.24.0.1_amd64.deb==865bbb442e7db0f67eb48e957d10738c https://github.com/Mellanox/Spectrum-SDK-Drivers-SONiC-Bins/releases/download/sdk-4.5.5142-bullseye-amd64/applibs-dev_1.mlnx.4.5.5142_amd64.deb==ddbee8ca24473dac9109b11ecafbc2ff https://github.com/Mellanox/Spectrum-SDK-Drivers-SONiC-Bins/releases/download/sdk-4.5.5142-bullseye-amd64/applibs_1.mlnx.4.5.5142_amd64.deb==3c0925b00e1844291f0c1bff00f7192d https://github.com/Mellanox/Spectrum-SDK-Drivers-SONiC-Bins/releases/download/sdk-4.5.5142-bullseye-amd64/python-sdk-api_1.mlnx.4.5.5142_amd64.deb==0deb403e4cd293f5b4f94fda120e9441 diff --git a/files/build/versions/dockers/docker-base-bullseye/versions-py3 b/files/build/versions/dockers/docker-base-bullseye/versions-py3 index 19d10a4bd0ba..61ebeea0c4ca 100644 --- a/files/build/versions/dockers/docker-base-bullseye/versions-py3 +++ b/files/build/versions/dockers/docker-base-bullseye/versions-py3 @@ -1,7 +1,7 @@ j2cli==0.3.10 jinja2==3.1.2 markupsafe==2.1.3 -pip==23.1.2 +pip==23.2.1 setuptools==49.6.0 supervisor==4.2.1 supervisord-dependent-startup==1.4.0 diff --git a/files/build/versions/dockers/docker-base-buster/versions-py3 b/files/build/versions/dockers/docker-base-buster/versions-py3 index 19d10a4bd0ba..61ebeea0c4ca 100644 --- a/files/build/versions/dockers/docker-base-buster/versions-py3 +++ b/files/build/versions/dockers/docker-base-buster/versions-py3 @@ -1,7 +1,7 @@ j2cli==0.3.10 jinja2==3.1.2 markupsafe==2.1.3 -pip==23.1.2 +pip==23.2.1 setuptools==49.6.0 supervisor==4.2.1 supervisord-dependent-startup==1.4.0 diff --git a/files/build/versions/dockers/docker-config-engine-bullseye/versions-deb-bullseye-arm64 b/files/build/versions/dockers/docker-config-engine-bullseye/versions-deb-bullseye-arm64 index 956750587805..93aa4686b2cd 100644 --- a/files/build/versions/dockers/docker-config-engine-bullseye/versions-deb-bullseye-arm64 +++ b/files/build/versions/dockers/docker-config-engine-bullseye/versions-deb-bullseye-arm64 @@ -10,5 +10,5 @@ libxml2==2.9.10+dfsg-6.7+deb11u4 libxml2-dev==2.9.10+dfsg-6.7+deb11u4 libxslt1-dev==1.1.34-4+deb11u1 libxslt1.1==1.1.34-4+deb11u1 -linux-libc-dev==5.10.179-1 +linux-libc-dev==5.10.179-2 zlib1g-dev==1:1.2.11.dfsg-2+deb11u2 diff --git a/files/build/versions/dockers/docker-config-engine-bullseye/versions-deb-bullseye-armhf b/files/build/versions/dockers/docker-config-engine-bullseye/versions-deb-bullseye-armhf index 956750587805..93aa4686b2cd 100644 --- a/files/build/versions/dockers/docker-config-engine-bullseye/versions-deb-bullseye-armhf +++ b/files/build/versions/dockers/docker-config-engine-bullseye/versions-deb-bullseye-armhf @@ -10,5 +10,5 @@ libxml2==2.9.10+dfsg-6.7+deb11u4 libxml2-dev==2.9.10+dfsg-6.7+deb11u4 libxslt1-dev==1.1.34-4+deb11u1 libxslt1.1==1.1.34-4+deb11u1 -linux-libc-dev==5.10.179-1 +linux-libc-dev==5.10.179-2 zlib1g-dev==1:1.2.11.dfsg-2+deb11u2 diff --git a/files/build/versions/dockers/docker-gbsyncd-broncos/versions-deb-bullseye b/files/build/versions/dockers/docker-gbsyncd-broncos/versions-deb-bullseye index d3cbca6be966..3eeffa6b2690 100644 --- a/files/build/versions/dockers/docker-gbsyncd-broncos/versions-deb-bullseye +++ b/files/build/versions/dockers/docker-gbsyncd-broncos/versions-deb-bullseye @@ -29,7 +29,7 @@ libsource-highlight4v5==3.1.9-3+b1 libswsscommon-dbgsym==1.0.0 libtirpc-dev==1.3.1-1+deb11u1 libunwind8==1.3.2-2 -linux-libc-dev==5.10.179-1 +linux-libc-dev==5.10.179-2 openssh-client==1:8.4p1-5+deb11u1 sshpass==1.09-1+b1 strace==5.10-1 diff --git a/files/build/versions/dockers/docker-platform-monitor/versions-py3 b/files/build/versions/dockers/docker-platform-monitor/versions-py3 index bf73e4489323..515fdf285eff 100644 --- a/files/build/versions/dockers/docker-platform-monitor/versions-py3 +++ b/files/build/versions/dockers/docker-platform-monitor/versions-py3 @@ -1,5 +1,5 @@ attrs==20.3.0 -certifi==2023.5.7 +certifi==2023.7.22 charset-normalizer==3.2.0 grpcio==1.39.0 grpcio-tools==1.39.0 @@ -15,5 +15,5 @@ pyrsistent==0.15.5 python_sdk_api==4.5.5142 requests==2.31.0 thrift==0.13.0 -urllib3==2.0.3 +urllib3==2.0.4 zipp==1.0.0 diff --git a/files/build/versions/dockers/docker-ptf-sai/versions-py3 b/files/build/versions/dockers/docker-ptf-sai/versions-py3 index 4454071cb0f1..6eb06bd6a9e4 100644 --- a/files/build/versions/dockers/docker-ptf-sai/versions-py3 +++ b/files/build/versions/dockers/docker-ptf-sai/versions-py3 @@ -1,5 +1,6 @@ crc16==0.1.1 getmac==0.9.4 +importlib-metadata==6.7.0 netifaces==0.11.0 packet-helper==0.0.1 psutil==5.9.5 @@ -9,4 +10,6 @@ pysubnettree==0.35 scapy-helper==0.14.8 tabulate==0.8.10 thrift==0.14.1 +typing-extensions==4.7.1 xmlrunner==1.7.7 +zipp==3.15.0 diff --git a/files/build/versions/dockers/docker-ptf/versions-py2 b/files/build/versions/dockers/docker-ptf/versions-py2 index ab45c6a42cce..a135ecbc2739 100644 --- a/files/build/versions/dockers/docker-ptf/versions-py2 +++ b/files/build/versions/dockers/docker-ptf/versions-py2 @@ -1,4 +1,4 @@ -backports.functools-lru-cache==1.6.5 +backports.functools-lru-cache==1.6.6 backports.shutil-get-terminal-size==1.0.0 bcrypt==3.1.7 cffi==1.15.1 diff --git a/files/build/versions/dockers/docker-sonic-mgmt-framework/versions-py3 b/files/build/versions/dockers/docker-sonic-mgmt-framework/versions-py3 index e36571edbf43..161ed038506e 100644 --- a/files/build/versions/dockers/docker-sonic-mgmt-framework/versions-py3 +++ b/files/build/versions/dockers/docker-sonic-mgmt-framework/versions-py3 @@ -1,11 +1,11 @@ attrs==23.1.0 certifi==2017.4.17 charset-normalizer==3.2.0 -click==8.1.4 +click==8.1.6 clickclick==20.10.2 connexion==2.7.0 flask==2.2.5 -grpcio==1.56.0 +grpcio==1.56.2 grpcio-tools==1.20.0 idna==3.4 importlib-resources==5.12.0 diff --git a/files/build/versions/dockers/docker-sonic-telemetry/versions-deb-bullseye b/files/build/versions/dockers/docker-sonic-telemetry/versions-deb-bullseye index 8390c1ad927b..8712cc4d6618 100644 --- a/files/build/versions/dockers/docker-sonic-telemetry/versions-deb-bullseye +++ b/files/build/versions/dockers/docker-sonic-telemetry/versions-deb-bullseye @@ -35,7 +35,7 @@ libtirpc-dev==1.3.1-1+deb11u1 libtsan0==10.2.1-6 libubsan1==10.2.1-6 libunwind8==1.3.2-2 -linux-libc-dev==5.10.179-1 +linux-libc-dev==5.10.179-2 openssh-client==1:8.4p1-5+deb11u1 sonic-gnmi==0.1 sonic-mgmt-common==1.0.0 diff --git a/files/build/versions/dockers/docker-sonic-vs/versions-deb-bullseye b/files/build/versions/dockers/docker-sonic-vs/versions-deb-bullseye index 3bba9a262312..bd6cb0114a26 100644 --- a/files/build/versions/dockers/docker-sonic-vs/versions-deb-bullseye +++ b/files/build/versions/dockers/docker-sonic-vs/versions-deb-bullseye @@ -98,7 +98,7 @@ libxml2==2.9.10+dfsg-6.7+deb11u4 libxml2-dev==2.9.10+dfsg-6.7+deb11u4 libyang2==2.0.112-6 libzmq3-dev==4.3.4-1 -linux-libc-dev==5.10.179-1 +linux-libc-dev==5.10.179-2 logrotate==3.18.0-2+deb11u1 lsof==4.93.2+dfsg-1.1 mailcap==3.69 diff --git a/files/build/versions/dockers/docker-sonic-vs/versions-py3 b/files/build/versions/dockers/docker-sonic-vs/versions-py3 index e52e03bd01dc..cbc33ce14d50 100644 --- a/files/build/versions/dockers/docker-sonic-vs/versions-py3 +++ b/files/build/versions/dockers/docker-sonic-vs/versions-py3 @@ -1,7 +1,7 @@ async-timeout==4.0.2 bcrypt==3.2.2 blessed==1.20.0 -certifi==2023.5.7 +certifi==2023.7.22 cffi==1.15.1 charset-normalizer==3.2.0 click==7.0 diff --git a/files/build/versions/dockers/docker-syncd-bfn/versions-deb-bullseye b/files/build/versions/dockers/docker-syncd-bfn/versions-deb-bullseye index 4b273e62a28a..cba5596e21ba 100644 --- a/files/build/versions/dockers/docker-syncd-bfn/versions-deb-bullseye +++ b/files/build/versions/dockers/docker-syncd-bfn/versions-deb-bullseye @@ -24,6 +24,6 @@ libunwind-dev==1.3.2-2 libunwind8==1.3.2-2 libusb-1.0-0==2:1.0.24-3 libxml2==2.9.10+dfsg-6.7+deb11u4 -linux-libc-dev==5.10.179-1 +linux-libc-dev==5.10.179-2 pkg-config==0.29.2-1 syncd==1.0.0 diff --git a/files/build/versions/dockers/docker-syncd-brcm-dnx-rpc/versions-deb-bullseye b/files/build/versions/dockers/docker-syncd-brcm-dnx-rpc/versions-deb-bullseye index dcb8098d1bee..529c5c0b326a 100644 --- a/files/build/versions/dockers/docker-syncd-brcm-dnx-rpc/versions-deb-bullseye +++ b/files/build/versions/dockers/docker-syncd-brcm-dnx-rpc/versions-deb-bullseye @@ -57,7 +57,7 @@ libtsan0==10.2.1-6 libubsan1==10.2.1-6 libuv1==1.40.0-2 libxml2==2.9.10+dfsg-6.7+deb11u4 -linux-libc-dev==5.10.179-1 +linux-libc-dev==5.10.179-2 mailcap==3.69 make==4.3-4.1 mime-support==3.66 diff --git a/files/build/versions/dockers/docker-syncd-brcm-rpc/versions-deb-bullseye b/files/build/versions/dockers/docker-syncd-brcm-rpc/versions-deb-bullseye index dcb8098d1bee..529c5c0b326a 100644 --- a/files/build/versions/dockers/docker-syncd-brcm-rpc/versions-deb-bullseye +++ b/files/build/versions/dockers/docker-syncd-brcm-rpc/versions-deb-bullseye @@ -57,7 +57,7 @@ libtsan0==10.2.1-6 libubsan1==10.2.1-6 libuv1==1.40.0-2 libxml2==2.9.10+dfsg-6.7+deb11u4 -linux-libc-dev==5.10.179-1 +linux-libc-dev==5.10.179-2 mailcap==3.69 make==4.3-4.1 mime-support==3.66 diff --git a/files/build/versions/dockers/docker-syncd-centec-rpc/versions-deb-bullseye b/files/build/versions/dockers/docker-syncd-centec-rpc/versions-deb-bullseye index dcb8098d1bee..529c5c0b326a 100644 --- a/files/build/versions/dockers/docker-syncd-centec-rpc/versions-deb-bullseye +++ b/files/build/versions/dockers/docker-syncd-centec-rpc/versions-deb-bullseye @@ -57,7 +57,7 @@ libtsan0==10.2.1-6 libubsan1==10.2.1-6 libuv1==1.40.0-2 libxml2==2.9.10+dfsg-6.7+deb11u4 -linux-libc-dev==5.10.179-1 +linux-libc-dev==5.10.179-2 mailcap==3.69 make==4.3-4.1 mime-support==3.66 diff --git a/files/build/versions/dockers/docker-syncd-mlnx/versions-deb-bullseye b/files/build/versions/dockers/docker-syncd-mlnx/versions-deb-bullseye index 92530838ec0e..bbcaf6ff5a01 100644 --- a/files/build/versions/dockers/docker-syncd-mlnx/versions-deb-bullseye +++ b/files/build/versions/dockers/docker-syncd-mlnx/versions-deb-bullseye @@ -40,7 +40,7 @@ libswsscommon-dbgsym==1.0.0 libtirpc-dev==1.3.1-1+deb11u1 libunwind8==1.3.2-2 libxml2==2.9.10+dfsg-6.7+deb11u4 -linux-libc-dev==5.10.179-1 +linux-libc-dev==5.10.179-2 mft==4.22.1-15 mlnx-sai==1.mlnx.SAIBuild2305.24.0.1 openssh-client==1:8.4p1-5+deb11u1 diff --git a/files/build/versions/dockers/sonic-slave-bullseye/versions-deb-bullseye b/files/build/versions/dockers/sonic-slave-bullseye/versions-deb-bullseye index 2a4aeca2a106..5a87a20b6da1 100644 --- a/files/build/versions/dockers/sonic-slave-bullseye/versions-deb-bullseye +++ b/files/build/versions/dockers/sonic-slave-bullseye/versions-deb-bullseye @@ -1397,12 +1397,12 @@ libzvbi0==0.2.35-18 libzzip-0-13==0.13.62-3.3+deb11u1 licensecheck==3.1.1-2 lintian==2.104.0 -linux-compiler-gcc-10-x86==5.10.179-1 -linux-headers-5.10.0-23-amd64==5.10.179-1 -linux-headers-5.10.0-23-common==5.10.179-1 -linux-headers-amd64==5.10.179-1 -linux-kbuild-5.10==5.10.179-1 -linux-libc-dev==5.10.179-1 +linux-compiler-gcc-10-x86==5.10.179-2 +linux-headers-5.10.0-23-amd64==5.10.179-2 +linux-headers-5.10.0-23-common==5.10.179-2 +linux-headers-amd64==5.10.179-2 +linux-kbuild-5.10==5.10.179-2 +linux-libc-dev==5.10.179-2 linuxdoc-tools==0.9.82-1 llvm-11==1:11.0.1-2 llvm-11-runtime==1:11.0.1-2 diff --git a/files/build/versions/dockers/sonic-slave-bullseye/versions-deb-bullseye-arm64 b/files/build/versions/dockers/sonic-slave-bullseye/versions-deb-bullseye-arm64 index 05ebfa8e9f35..78977dcfbdd5 100644 --- a/files/build/versions/dockers/sonic-slave-bullseye/versions-deb-bullseye-arm64 +++ b/files/build/versions/dockers/sonic-slave-bullseye/versions-deb-bullseye-arm64 @@ -18,6 +18,6 @@ libstdc++6-armhf-cross==10.2.1-6cross1 libubsan1-armhf-cross==10.2.1-6cross1 libunicode-linebreak-perl==0.0.20190101-1+b2 libxslt1-dev==1.1.34-4+deb11u1 -linux-headers-5.10.0-23-arm64==5.10.179-1 -linux-headers-arm64==5.10.179-1 +linux-headers-5.10.0-23-arm64==5.10.179-2 +linux-headers-arm64==5.10.179-2 nodejs==14.21.3-deb-1nodesource1 diff --git a/files/build/versions/dockers/sonic-slave-bullseye/versions-deb-bullseye-armhf b/files/build/versions/dockers/sonic-slave-bullseye/versions-deb-bullseye-armhf index 69454f7ebe94..b834957ecc26 100644 --- a/files/build/versions/dockers/sonic-slave-bullseye/versions-deb-bullseye-armhf +++ b/files/build/versions/dockers/sonic-slave-bullseye/versions-deb-bullseye-armhf @@ -7,8 +7,8 @@ libjpeg-dev==1:2.0.6-4 libjpeg62-turbo-dev==1:2.0.6-4 libunicode-linebreak-perl==0.0.20190101-1+b2 libxslt1-dev==1.1.34-4+deb11u1 -linux-compiler-gcc-10-arm==5.10.179-1 -linux-headers-5.10.0-23-armmp==5.10.179-1 -linux-headers-armmp==5.10.179-1 +linux-compiler-gcc-10-arm==5.10.179-2 +linux-headers-5.10.0-23-armmp==5.10.179-2 +linux-headers-armmp==5.10.179-2 nasm==2.15.05-1 nodejs==14.21.3-deb-1nodesource1 diff --git a/files/build/versions/dockers/sonic-slave-bullseye/versions-py3 b/files/build/versions/dockers/sonic-slave-bullseye/versions-py3 index fefafa377ca5..b50abe043315 100644 --- a/files/build/versions/dockers/sonic-slave-bullseye/versions-py3 +++ b/files/build/versions/dockers/sonic-slave-bullseye/versions-py3 @@ -6,7 +6,7 @@ automat==20.2.0 babel==2.8.0 bcrypt==3.1.7 beautifulsoup4==4.9.3 -bitarray==2.7.6 +bitarray==2.8.0 certifi==2020.6.20 chardet==4.0.0 click==7.1.2 @@ -46,7 +46,7 @@ markdown==3.3.4 markupsafe==1.1.1 mccabe==0.6.1 mmh3==2.5.1 -mock==5.0.2 +mock==5.1.0 mockredispy==2.9.3 more-itertools==4.2.0 mypy-extensions==0.4.3 @@ -58,7 +58,7 @@ parameterized==0.8.1 parse==1.6.6 pexpect==4.8.0 pillow==9.4.0 -pip==23.1.2 +pip==23.2.1 pluggy==0.13.0 ptyprocess==0.7.0 py==1.10.0 @@ -67,7 +67,7 @@ pyangbind==0.8.1 pyasn1==0.4.8 pyasn1-modules==0.2.1 pycurl==7.43.0.6 -pyfakefs==5.2.2 +pyfakefs==5.2.3 pygments==2.7.1 pygobject==3.38.0 pyhamcrest==1.9.0 diff --git a/files/build/versions/dockers/sonic-slave-buster/versions-deb-buster b/files/build/versions/dockers/sonic-slave-buster/versions-deb-buster index ae07b4e673b3..f73bbd7143db 100644 --- a/files/build/versions/dockers/sonic-slave-buster/versions-deb-buster +++ b/files/build/versions/dockers/sonic-slave-buster/versions-deb-buster @@ -23,7 +23,7 @@ autopoint==0.19.8.1-9 autotools-dev==20180224.1 bash-completion==1:2.8-6 bc==1.07.1-2+b1 -bind9-host==1:9.11.5.P4+dfsg-5.1+deb10u8 +bind9-host==1:9.11.5.P4+dfsg-5.1+deb10u9 binfmt-support==2.2.0-2 binutils==2.31.1-16 binutils-common==2.31.1-16 @@ -85,7 +85,7 @@ distro-info-data==0.41+deb10u7 dkms==2.6.1-4 dmeventd==2:1.02.155-3 dmsetup==2:1.02.155-3 -dnsutils==1:9.11.5.P4+dfsg-5.1+deb10u8 +dnsutils==1:9.11.5.P4+dfsg-5.1+deb10u9 docbook==4.5-6 docbook-dsssl==1.79-9.1 docbook-to-man==1:2.0.0-42 @@ -286,8 +286,8 @@ libbabeltrace-dev==1.5.6-2+deb10u1 libbabeltrace1==1.5.6-2+deb10u1 libbatik-java==1.10-2+deb10u2 libbdplus0==0.1.2-3 -libbind-export-dev==1:9.11.5.P4+dfsg-5.1+deb10u8 -libbind9-161==1:9.11.5.P4+dfsg-5.1+deb10u8 +libbind-export-dev==1:9.11.5.P4+dfsg-5.1+deb10u9 +libbind9-161==1:9.11.5.P4+dfsg-5.1+deb10u9 libbinutils==2.31.1-16 libbison-dev==2:3.3.2.dfsg-1 libbit-vector-perl==7.4-1+b5 @@ -451,8 +451,8 @@ libdist-checkconflicts-perl==0.11-1 libdistro-info-perl==0.21 libdjvulibre-text==3.5.27.1-10+deb10u1 libdjvulibre21==3.5.27.1-10+deb10u1 -libdns-export1104==1:9.11.5.P4+dfsg-5.1+deb10u8 -libdns1104==1:9.11.5.P4+dfsg-5.1+deb10u8 +libdns-export1104==1:9.11.5.P4+dfsg-5.1+deb10u9 +libdns1104==1:9.11.5.P4+dfsg-5.1+deb10u9 libdom4j-java==2.1.1-2 libdouble-conversion1==3.1.0-3 libdoxia-core-java==1.7-2 @@ -669,14 +669,14 @@ libipc-system-simple-perl==1.25-4 libipt2==2.0-2 libiptc-dev==1.8.2-4 libiptc0==1.8.2-4 -libirs-export161==1:9.11.5.P4+dfsg-5.1+deb10u8 -libirs161==1:9.11.5.P4+dfsg-5.1+deb10u8 -libisc-export1100==1:9.11.5.P4+dfsg-5.1+deb10u8 -libisc1100==1:9.11.5.P4+dfsg-5.1+deb10u8 -libisccc-export161==1:9.11.5.P4+dfsg-5.1+deb10u8 -libisccc161==1:9.11.5.P4+dfsg-5.1+deb10u8 -libisccfg-export163==1:9.11.5.P4+dfsg-5.1+deb10u8 -libisccfg163==1:9.11.5.P4+dfsg-5.1+deb10u8 +libirs-export161==1:9.11.5.P4+dfsg-5.1+deb10u9 +libirs161==1:9.11.5.P4+dfsg-5.1+deb10u9 +libisc-export1100==1:9.11.5.P4+dfsg-5.1+deb10u9 +libisc1100==1:9.11.5.P4+dfsg-5.1+deb10u9 +libisccc-export161==1:9.11.5.P4+dfsg-5.1+deb10u9 +libisccc161==1:9.11.5.P4+dfsg-5.1+deb10u9 +libisccfg-export163==1:9.11.5.P4+dfsg-5.1+deb10u9 +libisccfg163==1:9.11.5.P4+dfsg-5.1+deb10u9 libisl19==0.20-2 libitext1-java==1.4-7 libitm1==8.3.0-6 @@ -756,7 +756,7 @@ liblua5.1-0-dev==5.1.5-8.1+b2 liblvm2cmd2.03==2.03.02-3 liblwp-mediatypes-perl==6.02-1 liblwp-protocol-https-perl==6.07-2 -liblwres161==1:9.11.5.P4+dfsg-5.1+deb10u8 +liblwres161==1:9.11.5.P4+dfsg-5.1+deb10u9 liblzma-dev==5.2.4-1+deb10u1 liblzo2-2==2.10-0.1 liblzo2-dev==2.10-0.1 @@ -1341,7 +1341,7 @@ libxxf86vm-dev==1:1.1.4-1+b2 libxxf86vm1==1:1.1.4-1+b2 libxxhash0==0.6.5-2 libxz-java==1.8-2 -libyajl2==2.1.0-3+deb10u1 +libyajl2==2.1.0-3+deb10u2 libyaml-0-2==0.2.1-1 libyaml-dev==0.2.1-1 libyaml-libyaml-perl==0.76+repack-1 diff --git a/files/build/versions/dockers/sonic-slave-buster/versions-py3 b/files/build/versions/dockers/sonic-slave-buster/versions-py3 index 88949d47b256..d5db69b79086 100644 --- a/files/build/versions/dockers/sonic-slave-buster/versions-py3 +++ b/files/build/versions/dockers/sonic-slave-buster/versions-py3 @@ -4,7 +4,7 @@ async-timeout==4.0.2 atomicwrites==1.1.5 attrs==18.2.0 babel==2.6.0 -bitarray==2.7.6 +bitarray==2.8.0 certifi==2018.8.24 chardet==3.0.4 cov-core==1.15.0 @@ -41,7 +41,7 @@ parameterized==0.8.1 pbr==4.2.0 pexpect==4.8.0 pillow==9.4.0 -pip==23.1.2 +pip==23.2.1 pluggy==0.8.0 ptyprocess==0.7.0 py==1.7.0 @@ -49,7 +49,7 @@ pyang==2.4.0 pyangbind==0.8.1 pycrypto==2.6.1 pycurl==7.43.0.2 -pyfakefs==5.2.2 +pyfakefs==5.2.3 pygments==2.3.1 pygobject==3.30.4 pympler==0.8 diff --git a/files/build/versions/host-image/versions-deb-bullseye b/files/build/versions/host-image/versions-deb-bullseye index 04dac275779c..d83dccb5d7ce 100644 --- a/files/build/versions/host-image/versions-deb-bullseye +++ b/files/build/versions/host-image/versions-deb-bullseye @@ -242,8 +242,8 @@ libyang-cpp==1.0.73 libzmq5==4.3.4-1 linux-base==4.6 linux-image-5.10.0-18-2-amd64-unsigned==5.10.140-1 -linux-perf==5.10.179-1 -linux-perf-5.10==5.10.179-1 +linux-perf==5.10.179-2 +linux-perf-5.10==5.10.179-2 locales==2.31-13+deb11u6 logrotate==3.18.0-2+deb11u1 lsb-release==11.1.0 diff --git a/files/build/versions/host-image/versions-deb-bullseye-arm64 b/files/build/versions/host-image/versions-deb-bullseye-arm64 index 2f85f0b7a89d..021ffd2b236f 100644 --- a/files/build/versions/host-image/versions-deb-bullseye-arm64 +++ b/files/build/versions/host-image/versions-deb-bullseye-arm64 @@ -13,7 +13,7 @@ libxml2-dev==2.9.10+dfsg-6.7+deb11u4 libxslt1-dev==1.1.34-4+deb11u1 libxslt1.1==1.1.34-4+deb11u1 linux-image-5.10.0-18-2-arm64-unsigned==5.10.140-1 -linux-libc-dev==5.10.179-1 +linux-libc-dev==5.10.179-2 ntpstat==0.0.0.1-2 picocom==3.1-2 tsingma-bsp==1.0 diff --git a/files/build/versions/host-image/versions-deb-bullseye-armhf b/files/build/versions/host-image/versions-deb-bullseye-armhf index b6819a1d40db..707f042f3170 100644 --- a/files/build/versions/host-image/versions-deb-bullseye-armhf +++ b/files/build/versions/host-image/versions-deb-bullseye-armhf @@ -14,7 +14,7 @@ libxml2-dev==2.9.10+dfsg-6.7+deb11u4 libxslt1-dev==1.1.34-4+deb11u1 libxslt1.1==1.1.34-4+deb11u1 linux-image-5.10.0-18-2-armmp==5.10.140-1 -linux-libc-dev==5.10.179-1 +linux-libc-dev==5.10.179-2 mrvlprestera==1.0 ntpstat==0.0.0.1-2 openssh-client==1:8.4p1-5+deb11u1 diff --git a/files/build/versions/host-image/versions-py3 b/files/build/versions/host-image/versions-py3 index e90730ed21a6..556f4825ce42 100644 --- a/files/build/versions/host-image/versions-py3 +++ b/files/build/versions/host-image/versions-py3 @@ -4,7 +4,7 @@ azure-storage==0.36.0 bcrypt==3.2.2 bitarray==1.5.3 blessed==1.20.0 -certifi==2023.5.7 +certifi==2023.7.22 cffi==1.15.1 charset-normalizer==3.2.0 click==7.0 @@ -40,7 +40,7 @@ paramiko==2.11.0 pathtools==0.1.2 pddf-platform==1.0 pexpect==4.8.0 -pip==23.1.2 +pip==23.2.1 prefixed==0.7.0 prettyprinter==0.18.0 protobuf==3.20.3 diff --git a/files/build_templates/dns.j2 b/files/build_templates/dns.j2 new file mode 100644 index 000000000000..96fb81f9a1f3 --- /dev/null +++ b/files/build_templates/dns.j2 @@ -0,0 +1,11 @@ +{# Please follow below example to add your DNS server +{ + "DNS_NAMESERVER": { + "6.6.6.6": {}, + "2001:4860:4860::64": {} + } +} +#} +{ + "DNS_NAMESERVER": {} +} diff --git a/files/build_templates/docker_image_ctl.j2 b/files/build_templates/docker_image_ctl.j2 index 01a52fb7a0d3..924f0283bad6 100644 --- a/files/build_templates/docker_image_ctl.j2 +++ b/files/build_templates/docker_image_ctl.j2 @@ -235,6 +235,7 @@ function postStartAction() ($(docker exec -i database$DEV sonic-db-cli PING | grep -c PONG) -gt 0) ]]; do sleep 1; done + if [[ ("$BOOT_TYPE" == "warm" || "$BOOT_TYPE" == "fastfast" || "$BOOT_TYPE" == "fast") && -f $WARM_DIR/dump.rdb ]]; then # retain the dump file from last boot for debugging purposes mv $WARM_DIR/dump.rdb $WARM_DIR/dump.rdb.old @@ -248,28 +249,18 @@ function postStartAction() $SONIC_CFGGEN -j /etc/sonic/config_db$DEV.json --write-to-db fi fi - - if [[ "$BOOT_TYPE" == "fast" ]]; then - # set the key to expire in 3 minutes - $SONIC_DB_CLI STATE_DB SET "FAST_REBOOT|system" "1" "EX" "180" - fi - - $SONIC_DB_CLI CONFIG_DB SET "CONFIG_DB_INITIALIZED" "1" fi - if [ -e /tmp/pending_config_migration ]; then + if [ -e /tmp/pending_config_migration ] || [ -e /tmp/pending_config_initialization ]; then # this is first boot to a new image, config-setup execution is pending. - # For fast/cold reboot case, DB contains nothing at this point - # Call db_migrator after config-setup loads the config (from old config or minigraph) - echo "Delaying db_migrator until config migration is over" + # for warmboot case, DB is loaded but migration is still pending + # For firstbboot/fast/cold reboot case, DB contains nothing at this point + # unset CONFIG_DB_INITIALIZED to indicate pending config load and migration + # This flag will be set to "1" after DB migration/initialization is completed as part of config-setup + $SONIC_DB_CLI CONFIG_DB SET "CONFIG_DB_INITIALIZED" "0" else - # this is not a first time boot to a new image. Datbase container starts w/ old pre-existing config - if [[ -x /usr/local/bin/db_migrator.py ]]; then - # Migrate the DB to the latest schema version if needed - if [ -z "$DEV" ]; then - /usr/local/bin/db_migrator.py -o migrate - fi - fi + # set CONFIG_DB_INITIALIZED to indicate end of config load and migration + $SONIC_DB_CLI CONFIG_DB SET "CONFIG_DB_INITIALIZED" "1" fi # Add redis UDS to the redis group and give read/write access to the group REDIS_SOCK="/var/run/redis${DEV}/redis.sock" @@ -596,6 +587,7 @@ start() { -v /usr/share/sonic/device/$PLATFORM/$HWSKU/$DEV:/usr/share/sonic/hwsku:ro \ {%- endif %} $REDIS_MNT \ + -v /etc/fips/fips_enable:/etc/fips/fips_enable:ro \ -v /usr/share/sonic/device/$PLATFORM:/usr/share/sonic/platform:ro \ -v /usr/share/sonic/templates/rsyslog-container.conf.j2:/usr/share/sonic/templates/rsyslog-container.conf.j2:ro \ {%- if sonic_asic_platform != "mellanox" %} diff --git a/files/build_templates/init_cfg.json.j2 b/files/build_templates/init_cfg.json.j2 index f7331037130e..0f933c30e9aa 100644 --- a/files/build_templates/init_cfg.json.j2 +++ b/files/build_templates/init_cfg.json.j2 @@ -37,7 +37,6 @@ ("database", "always_enabled", false, "always_enabled"), ("lldp", "enabled", true, "enabled"), ("pmon", "enabled", true, "enabled"), - ("pmon", "enabled", false, "enabled"), ("snmp", "enabled", true, "enabled"), ("eventd", "enabled", false, "enabled"), ("swss", "enabled", false, "enabled"), diff --git a/files/build_templates/qos_config.j2 b/files/build_templates/qos_config.j2 index f9900714d829..44b13763632d 100644 --- a/files/build_templates/qos_config.j2 +++ b/files/build_templates/qos_config.j2 @@ -1,5 +1,24 @@ {%- set PORT_ALL = [] %} {%- set PORT_BP = [] %} +{%- set SYSTEM_PORT_ALL = [] %} + +{%- set voq_chassis = false %} +{%- if DEVICE_METADATA is defined and DEVICE_METADATA['localhost']['switch_type'] is defined and DEVICE_METADATA['localhost']['switch_type'] == 'voq' %} +{%- set voq_chassis = true %} +{%- endif -%} + +{%- if voq_chassis %} + {%- for system_port in SYSTEM_PORT %} + {% if '|' not in system_port %} + {%- set system_port_name = system_port|join("|") %} + {% else %} + {%- set system_port_name = system_port %} + {% endif %} + {%- if 'cpu' not in system_port_name.lower() and 'IB' not in system_port_name and 'Rec' not in system_port_name %} + {%- if SYSTEM_PORT_ALL.append(system_port_name) %}{%- endif %} + {%- endif %} + {%- endfor %} +{%- endif %} {%- for port in PORT %} {%- if not port.startswith('Ethernet-Rec') and not port.startswith('Ethernet-IB') %} {%- if PORT_ALL.append(port) %}{% endif %} @@ -307,7 +326,48 @@ } }, {% endif %} +{% if voq_chassis %} "QUEUE": { +{% for system_port in SYSTEM_PORT_ALL %} + "{{ system_port }}|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, +{% endfor %} +{% for system_port in SYSTEM_PORT_ALL %} + "{{ system_port }}|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, +{% endfor %} +{% for system_port in SYSTEM_PORT_ALL %} + "{{ system_port }}|0": { + "scheduler": "scheduler.0" + }, +{% endfor %} +{% for system_port in SYSTEM_PORT_ALL %} + "{{ system_port }}|1": { + "scheduler": "scheduler.0" + }, +{% endfor %} +{% for system_port in SYSTEM_PORT_ALL %} + "{{ system_port }}|2": { + "scheduler": "scheduler.0" + }, +{% endfor %} +{% for system_port in SYSTEM_PORT_ALL %} + "{{ system_port }}|5": { + "scheduler": "scheduler.0" + }, +{% endfor %} +{% for system_port in SYSTEM_PORT_ALL %} + "{{ system_port }}|6": { + "scheduler": "scheduler.0" + }{% if not loop.last %},{% endif %} +{% endfor %} + } +{% else %} + "QUEUE": { {% for port in PORT_ACTIVE %} "{{ port }}|3": { "scheduler" : "scheduler.1", @@ -372,4 +432,5 @@ {% endfor %} } +{% endif %} } diff --git a/files/build_templates/sonic_debian_extension.j2 b/files/build_templates/sonic_debian_extension.j2 index a35fcbd03c7a..c2c190540c2a 100644 --- a/files/build_templates/sonic_debian_extension.j2 +++ b/files/build_templates/sonic_debian_extension.j2 @@ -373,6 +373,9 @@ sudo cp $IMAGE_CONFIGS/ntp/ntp-systemd-wrapper $FILESYSTEM_ROOT/usr/lib/ntp/ sudo cp $IMAGE_CONFIGS/ntp/ntp.service $FILESYSTEM_ROOT_USR_LIB_SYSTEMD_SYSTEM echo "ntp.service" | sudo tee -a $GENERATED_SERVICE_FILE +# Copy DNS templates +sudo cp $BUILD_TEMPLATES/dns.j2 $FILESYSTEM_ROOT_USR_SHARE_SONIC_TEMPLATES/ + # Copy warmboot-finalizer files sudo LANG=C cp $IMAGE_CONFIGS/warmboot-finalizer/finalize-warmboot.sh $FILESYSTEM_ROOT/usr/local/bin/finalize-warmboot.sh sudo LANG=C cp $IMAGE_CONFIGS/warmboot-finalizer/warmboot-finalizer.service $FILESYSTEM_ROOT_USR_LIB_SYSTEMD_SYSTEM @@ -790,15 +793,27 @@ sudo https_proxy=$https_proxy LANG=C chroot $FILESYSTEM_ROOT docker $SONIC_NATIV sudo https_proxy=$https_proxy LANG=C chroot $FILESYSTEM_ROOT docker $SONIC_NATIVE_DOCKERD_FOR_DOCKERFS pull k8s.gcr.io/kube-proxy:${MASTER_KUBERNETES_CONTAINER_IMAGE_VERSION} sudo https_proxy=$https_proxy LANG=C chroot $FILESYSTEM_ROOT docker $SONIC_NATIVE_DOCKERD_FOR_DOCKERFS pull k8s.gcr.io/coredns/coredns:${MASTER_COREDNS_VERSION} sudo https_proxy=$https_proxy LANG=C chroot $FILESYSTEM_ROOT docker $SONIC_NATIVE_DOCKERD_FOR_DOCKERFS pull k8s.gcr.io/etcd:${MASTER_ETCD_VERSION} +sudo https_proxy=$https_proxy LANG=C chroot $FILESYSTEM_ROOT docker $SONIC_NATIVE_DOCKERD_FOR_DOCKERFS pull kubernetesui/metrics-scraper:${MASTER_UI_METRIC_VERSION} +sudo https_proxy=$https_proxy LANG=C chroot $FILESYSTEM_ROOT docker $SONIC_NATIVE_DOCKERD_FOR_DOCKERFS pull kubernetesui/dashboard:${MASTER_UI_DASH_VERSION} +sudo https_proxy=$https_proxy LANG=C chroot $FILESYSTEM_ROOT docker $SONIC_NATIVE_DOCKERD_FOR_DOCKERFS pull linuxgeneva-microsoft.azurecr.io/distroless/genevamdm:${MASTER_MDM_VERSION} +sudo https_proxy=$https_proxy LANG=C chroot $FILESYSTEM_ROOT docker $SONIC_NATIVE_DOCKERD_FOR_DOCKERFS tag linuxgeneva-microsoft.azurecr.io/distroless/genevamdm:${MASTER_MDM_VERSION} linuxgeneva-microsoft.azurecr.io/distroless/genevamdm:latest +sudo https_proxy=$https_proxy LANG=C chroot $FILESYSTEM_ROOT docker $SONIC_NATIVE_DOCKERD_FOR_DOCKERFS pull linuxgeneva-microsoft.azurecr.io/distroless/genevamdsd:${MASTER_MDS_VERSION} +sudo https_proxy=$https_proxy LANG=C chroot $FILESYSTEM_ROOT docker $SONIC_NATIVE_DOCKERD_FOR_DOCKERFS tag linuxgeneva-microsoft.azurecr.io/distroless/genevamdsd:${MASTER_MDS_VERSION} linuxgeneva-microsoft.azurecr.io/distroless/genevamdsd:latest +sudo https_proxy=$https_proxy LANG=C chroot $FILESYSTEM_ROOT docker $SONIC_NATIVE_DOCKERD_FOR_DOCKERFS pull linuxgeneva-microsoft.azurecr.io/distroless/genevafluentd_td-agent:${MASTER_FLUENTD_VERSION} +sudo https_proxy=$https_proxy LANG=C chroot $FILESYSTEM_ROOT docker $SONIC_NATIVE_DOCKERD_FOR_DOCKERFS tag linuxgeneva-microsoft.azurecr.io/distroless/genevafluentd_td-agent:${MASTER_FLUENTD_VERSION} linuxgeneva-microsoft.azurecr.io/distroless/genevafluentd_td-agent:latest echo "kubernetes master docker images pull complete" -# Install python package for mdm service usage +# Install python packages for mdm metrics collection service usage sudo https_proxy=$https_proxy LANG=C chroot $FILESYSTEM_ROOT pip3 install psutil sudo https_proxy=$https_proxy LANG=C chroot $FILESYSTEM_ROOT pip3 install statsd -sudo LANG=C chroot $FILESYSTEM_ROOT systemctl enable mdm.service +sudo https_proxy=$https_proxy LANG=C chroot $FILESYSTEM_ROOT pip3 install kubernetes +# Install python packages to upload and download etcd backup files for backup and restore service usage +sudo https_proxy=$https_proxy LANG=C chroot $FILESYSTEM_ROOT pip3 install azure-storage-blob azure-identity sudo LANG=C chroot $FILESYSTEM_ROOT systemctl enable kubelet.service # Add kubernetes master entrance -sudo cp files/image_config/kubernetes/kubernetes_master_entrance.sh $FILESYSTEM_ROOT/usr/sbin/ -sudo sed -i '/^exit 0/i\bash /usr/sbin/kubernetes_master_entrance.sh' $FILESYSTEM_ROOT/etc/rc.local +sudo cp files/image_config/kubernetes/kubernetes_master_entrance.service ${FILESYSTEM_ROOT_USR_LIB_SYSTEMD_SYSTEM}/ +sudo cp files/image_config/kubernetes/kubernetes_master_entrance.sh $FILESYSTEM_ROOT/usr/bin/ +sudo chmod +x $FILESYSTEM_ROOT/usr/bin/kubernetes_master_entrance.sh +sudo LANG=C chroot $FILESYSTEM_ROOT systemctl enable kubernetes_master_entrance.service {% endif %} {% macro get_install_options(set_owner, enabled) -%} @@ -923,6 +938,7 @@ declare -rA FW_FILE_MAP=( \ [$MLNX_SPC_FW_FILE]="fw-SPC.mfa" \ [$MLNX_SPC2_FW_FILE]="fw-SPC2.mfa" \ [$MLNX_SPC3_FW_FILE]="fw-SPC3.mfa" \ + [$MLNX_SPC4_FW_FILE]="fw-SPC4.mfa" \ ) sudo mkdir -p $FILESYSTEM_ROOT/$PLATFORM_DIR/fw/asic/ sudo mkdir -p $FILESYSTEM_ROOT_ETC/mlnx/ diff --git a/files/image_config/config-setup/config-setup b/files/image_config/config-setup/config-setup index b23d84cf2607..3369b0ec86e7 100755 --- a/files/image_config/config-setup/config-setup +++ b/files/image_config/config-setup/config-setup @@ -295,6 +295,7 @@ do_config_initialization() fi rm -f /tmp/pending_config_initialization + sonic-db-cli CONFIG_DB SET "CONFIG_DB_INITIALIZED" "1" } # Restore config-setup post migration hooks from a backup copy @@ -344,13 +345,14 @@ check_all_config_db_present() } # DB schema is subject to change between two images -# Perform DB schema migration after loading backup config from previous image +# Perform DB schema migration after loading backup config/minigraph from previous image do_db_migration() { if [[ -x /usr/local/bin/db_migrator.py ]]; then # Migrate the DB to the latest schema version if needed /usr/local/bin/db_migrator.py -o migrate fi + sonic-db-cli CONFIG_DB SET "CONFIG_DB_INITIALIZED" "1" } # Perform configuration migration from backup copy. diff --git a/files/image_config/constants/constants.yml b/files/image_config/constants/constants.yml index 94f3d0e9706c..4c5339700396 100644 --- a/files/image_config/constants/constants.yml +++ b/files/image_config/constants/constants.yml @@ -4,6 +4,7 @@ constants: "2" : 65433 bgp: traffic_shift_community: 12345:12345 + sentinel_community: 12345:12346 families: - ipv4 - ipv6 @@ -58,3 +59,7 @@ constants: enabled: true db_table: "BGP_VOQ_CHASSIS_NEIGHBOR" template_dir: "voq_chassis" + sentinels: # peer_type + enabled: true + db_table: "BGP_SENTINELS" + template_dir: "sentinels" diff --git a/files/image_config/kubernetes/kubernetes_master_entrance.service b/files/image_config/kubernetes/kubernetes_master_entrance.service new file mode 100644 index 000000000000..3f407cf618ae --- /dev/null +++ b/files/image_config/kubernetes/kubernetes_master_entrance.service @@ -0,0 +1,13 @@ +[Unit] +Description=Setup k8s master services +Requires=rc-local.service +After=rc-local.service +Before=sonic.target + +[Service] +Type=oneshot +RemainAfterExit=yes +ExecStart=/usr/bin/kubernetes_master_entrance.sh + +[Install] +WantedBy=multi-user.target diff --git a/files/image_config/kubernetes/kubernetes_master_entrance.sh b/files/image_config/kubernetes/kubernetes_master_entrance.sh index b7695a61cae5..d73f4c4cb13c 100644 --- a/files/image_config/kubernetes/kubernetes_master_entrance.sh +++ b/files/image_config/kubernetes/kubernetes_master_entrance.sh @@ -1,2 +1,47 @@ +#!/bin/bash + # This script is for kubernetes master image usage # Will mount kubernetes master disk and execute kubernetes entrance script + +set -x + +# mount disk from host +mount_point="/from_host" +disk_by_path_dir="/dev/disk/by-path" +# We can't ensure the mounted disk name is sda or sdb +# Currently we specify the disk logic unit number to 2 when create master VM +# We find the correct disk by the disk logic unit number from by-path directory +target_str="lun-2-part1" +disk_path_file=$(ls $disk_by_path_dir | grep $target_str) + +# Check whether the disk path file exists +if [ -z "$disk_path_file" ]; then + echo "Error: Disk path file not found." + exit 1 +fi + +# Check the number of lines returned +line_count=$(echo "$disk_path_file" | wc -l) + +# If there are multiple lines, exit with status 1 +if [ "$line_count" -ne 1 ]; then + echo "Error: multiple disk path files found." + exit 1 +fi + +disk="${disk_by_path_dir}/${disk_path_file}" +mkdir -p $mount_point +mount $disk $mount_point + +# check whether it is the first time to boot +first_boot_flag_file="/from_host/first_boot_flag" +if [ -f $first_boot_flag_file ]; then + exit 0 +fi +touch $first_boot_flag_file + +# execute entrance script +init_file_name="entrance.sh" +init_file=${mount_point}/${init_file_name} +chmod +x $init_file +source $init_file diff --git a/files/image_config/monit/conf.d/sonic-host b/files/image_config/monit/conf.d/sonic-host index d65325207543..482a992b6df7 100644 --- a/files/image_config/monit/conf.d/sonic-host +++ b/files/image_config/monit/conf.d/sonic-host @@ -31,6 +31,13 @@ check program routeCheck with path "/usr/local/bin/route_check.py" every 5 cycles if status != 0 for 3 cycle then alert repeat every 1 cycles +# dualtor_neighbor_check.py: script to check if the neighbor entries in APPL_DB +# has correct neighbor or tunnel route entries in ASIC_DB based on the mux +# states. +check program dualtorNeighborCheck with path "/usr/local/bin/dualtor_neighbor_check.py -o SYSLOG -s ERROR" + every 5 cycles + if status != 0 for 3 cycle then alert repeat every 1 cycles + # Check if /etc & /home are writable. If not, make them writable. # Raise syslog error message, in case of underlying issues # diff --git a/files/image_config/warmboot-finalizer/finalize-warmboot.sh b/files/image_config/warmboot-finalizer/finalize-warmboot.sh index 783f3881816b..b01832a6c7b8 100755 --- a/files/image_config/warmboot-finalizer/finalize-warmboot.sh +++ b/files/image_config/warmboot-finalizer/finalize-warmboot.sh @@ -74,7 +74,7 @@ function wait_for_database_service() done # Wait for configDB initialization - until [[ $(sonic-db-cli CONFIG_DB GET "CONFIG_DB_INITIALIZED") ]]; + until [[ $(sonic-db-cli CONFIG_DB GET "CONFIG_DB_INITIALIZED") -eq 1 ]]; do sleep 1; done diff --git a/files/scripts/swss.sh b/files/scripts/swss.sh index 0e37fe1376cd..f79e7ed13731 100755 --- a/files/scripts/swss.sh +++ b/files/scripts/swss.sh @@ -87,7 +87,7 @@ function wait_for_database_service() done # Wait for configDB initialization - until [[ $($SONIC_DB_CLI CONFIG_DB GET "CONFIG_DB_INITIALIZED") ]]; + until [[ $($SONIC_DB_CLI CONFIG_DB GET "CONFIG_DB_INITIALIZED") -eq 1 ]]; do sleep 1; done } @@ -318,6 +318,16 @@ function check_macsec() fi } +function check_add_bgp_dependency() +{ + if ! is_chassis_supervisor; then + if [ "$DEV" ]; then + DEPENDENT="${DEPENDENT} bgp@${DEV}" + else + DEPENDENT="${DEPENDENT} bgp" + fi + fi +} function check_ports_present() { PORT_CONFIG_INI=/usr/share/sonic/device/$PLATFORM/$HWSKU/$DEV/port_config.ini @@ -353,11 +363,9 @@ fi if [ "$DEV" ]; then NET_NS="$NAMESPACE_PREFIX$DEV" #name of the network namespace SONIC_DB_CLI="sonic-db-cli -n $NET_NS" - DEPENDENT+=" bgp@${DEV}" else NET_NS="" SONIC_DB_CLI="sonic-db-cli" - DEPENDENT+=" bgp" fi PLATFORM=`$SONIC_DB_CLI CONFIG_DB hget 'DEVICE_METADATA|localhost' platform` @@ -365,7 +373,7 @@ HWSKU=`$SONIC_DB_CLI CONFIG_DB hget 'DEVICE_METADATA|localhost' hwsku` check_peer_gbsyncd check_macsec - +check_add_bgp_dependency check_ports_present PORTS_PRESENT=$? diff --git a/files/scripts/syncd.sh b/files/scripts/syncd.sh index 8aacfe8f6c1a..827be1463f6a 100755 --- a/files/scripts/syncd.sh +++ b/files/scripts/syncd.sh @@ -2,6 +2,18 @@ . /usr/local/bin/syncd_common.sh +declare -r UNKN_MST="unknown" + +function GetMstDevice() { + local _MST_DEVICE="$(ls /dev/mst/*_pci_cr0 2>&1)" + + if [[ ! -c "${_MST_DEVICE}" ]]; then + echo "${UNKN_MST}" + else + echo "${_MST_DEVICE}" + fi +} + function startplatform() { # platform specific tasks @@ -23,6 +35,12 @@ function startplatform() { debug "Starting Firmware update procedure" /usr/bin/mst start --with_i2cdev + + local -r _MST_DEVICE="$(GetMstDevice)" + if [[ "${_MST_DEVICE}" != "${UNKN_MST}" ]]; then + /usr/bin/flint -d $_MST_DEVICE --clear_semaphore + fi + /usr/bin/mlnx-fw-upgrade.sh /etc/init.d/sxdkernel restart debug "Firmware update procedure ended" diff --git a/files/scripts/syncd_common.sh b/files/scripts/syncd_common.sh index a850e31b207d..826cdd731ba6 100755 --- a/files/scripts/syncd_common.sh +++ b/files/scripts/syncd_common.sh @@ -66,7 +66,7 @@ function wait_for_database_service() done # Wait for configDB initialization - until [[ $($SONIC_DB_CLI CONFIG_DB GET "CONFIG_DB_INITIALIZED") ]]; + until [[ $($SONIC_DB_CLI CONFIG_DB GET "CONFIG_DB_INITIALIZED") -eq 1 ]]; do sleep 1; done } diff --git a/installer/install.sh b/installer/install.sh index 51b5a75eb574..7f3feae42b7c 100755 --- a/installer/install.sh +++ b/installer/install.sh @@ -243,6 +243,11 @@ fi echo "ONIE_IMAGE_PART_SIZE=$demo_part_size" extra_cmdline_linux=%%EXTRA_CMDLINE_LINUX%% +# Inherit the FIPS option, so not necessary to do another reboot after upgraded +if grep -q '\bsonic_fips=1\b' /proc/cmdline && echo " $extra_cmdline_linux" | grep -qv '\bsonic_fips=.\b'; then + extra_cmdline_linux="$extra_cmdline_linux sonic_fips=1" +fi + echo "EXTRA_CMDLINE_LINUX=$extra_cmdline_linux" # Update Bootloader Menu with installed image diff --git a/platform/broadcom/one-image.mk b/platform/broadcom/one-image.mk index 82c96104a015..c9660299ed7e 100755 --- a/platform/broadcom/one-image.mk +++ b/platform/broadcom/one-image.mk @@ -20,6 +20,7 @@ $(SONIC_ONE_IMAGE)_LAZY_INSTALLS += $(DELL_S6000_PLATFORM_MODULE) \ $(DELL_S6100_PLATFORM_MODULE) \ $(DELL_N3248PXE_PLATFORM_MODULE) \ $(DELL_N3248TE_PLATFORM_MODULE) \ + $(DELL_E3224F_PLATFORM_MODULE) \ $(INGRASYS_S8900_54XC_PLATFORM_MODULE) \ $(INGRASYS_S8900_64XC_PLATFORM_MODULE) \ $(INGRASYS_S9100_PLATFORM_MODULE) \ @@ -78,13 +79,14 @@ $(SONIC_ONE_IMAGE)_LAZY_INSTALLS += $(DELL_S6000_PLATFORM_MODULE) \ $(DELTA_AGC032_PLATFORM_MODULE) \ $(RUIJIE_B6510_48VS8CQ_PLATFORM_MODULE) \ $(RAGILE_RA_B6510_48V8C_PLATFORM_MODULE) \ - $(RAGILE_RA_B6910_64C_PLATFORM_MODULE) \ - $(RAGILE_RA_B6510_32C_PLATFORM_MODULE) \ - $(RAGILE_RA_B6920_4S_PLATFORM_MODULE) \ $(NOKIA_IXR7250_PLATFORM_MODULE) \ $(TENCENT_TCS8400_PLATFORM_MODULE) \ $(TENCENT_TCS9400_PLATFORM_MODULE) \ - $(UFISPACE_S9300_32D_PLATFORM_MODULE) + $(UFISPACE_S9300_32D_PLATFORM_MODULE) \ + $(UFISPACE_S9110_32X_PLATFORM_MODULE) \ + $(UFISPACE_S8901_54XC_PLATFORM_MODULE) \ + $(UFISPACE_S7801_54XS_PLATFORM_MODULE) \ + $(UFISPACE_S6301_56ST_PLATFORM_MODULE) $(SONIC_ONE_IMAGE)_LAZY_BUILD_INSTALLS = $(BRCM_OPENNSL_KERNEL) $(BRCM_DNX_OPENNSL_KERNEL) ifeq ($(INSTALL_DEBUG_TOOLS),y) diff --git a/platform/broadcom/platform-modules-dell.mk b/platform/broadcom/platform-modules-dell.mk index a9d2a1880b28..900ec881a5f9 100644 --- a/platform/broadcom/platform-modules-dell.mk +++ b/platform/broadcom/platform-modules-dell.mk @@ -13,6 +13,7 @@ DELL_S5248F_PLATFORM_MODULE_VERSION = 1.1 DELL_S5296F_PLATFORM_MODULE_VERSION = 1.1 DELL_N3248PXE_PLATFORM_MODULE_VERSION = 1.1 DELL_N3248TE_PLATFORM_MODULE_VERSION = 1.1 +DELL_E3224F_PLATFORM_MODULE_VERSION = 1.1 export DELL_S6000_PLATFORM_MODULE_VERSION export DELL_Z9100_PLATFORM_MODULE_VERSION @@ -27,6 +28,7 @@ export DELL_S5248F_PLATFORM_MODULE_VERSION export DELL_S5296F_PLATFORM_MODULE_VERSION export DELL_N3248PXE_PLATFORM_MODULE_VERSION export DELL_N3248TE_PLATFORM_MODULE_VERSION +export DELL_E3224F_PLATFORM_MODULE_VERSION DELL_Z9100_PLATFORM_MODULE = platform-modules-z9100_$(DELL_Z9100_PLATFORM_MODULE_VERSION)_amd64.deb $(DELL_Z9100_PLATFORM_MODULE)_SRC_PATH = $(PLATFORM_PATH)/sonic-platform-modules-dell @@ -75,6 +77,10 @@ DELL_N3248TE_PLATFORM_MODULE = platform-modules-n3248te_$(DELL_N3248TE_PLATFORM_ $(DELL_N3248TE_PLATFORM_MODULE)_PLATFORM = x86_64-dellemc_n3248te_c3338-r0 $(eval $(call add_extra_package,$(DELL_Z9100_PLATFORM_MODULE),$(DELL_N3248TE_PLATFORM_MODULE))) +DELL_E3224F_PLATFORM_MODULE = platform-modules-e3224f_$(DELL_E3224F_PLATFORM_MODULE_VERSION)_amd64.deb +$(DELL_E3224F_PLATFORM_MODULE)_PLATFORM = x86_64-dell_e3224f-r0 +$(eval $(call add_extra_package,$(DELL_Z9100_PLATFORM_MODULE),$(DELL_E3224F_PLATFORM_MODULE))) + DELL_S5296F_PLATFORM_MODULE = platform-modules-s5296f_$(DELL_S5296F_PLATFORM_MODULE_VERSION)_amd64.deb $(DELL_S5296F_PLATFORM_MODULE)_PLATFORM = x86_64-dellemc_s5296f_c3538-r0 $(eval $(call add_extra_package,$(DELL_Z9100_PLATFORM_MODULE),$(DELL_S5296F_PLATFORM_MODULE))) diff --git a/platform/broadcom/platform-modules-ragile.mk b/platform/broadcom/platform-modules-ragile.mk index 12236b1e72ce..b0cc3b91b2a0 100644 --- a/platform/broadcom/platform-modules-ragile.mk +++ b/platform/broadcom/platform-modules-ragile.mk @@ -10,25 +10,25 @@ SONIC_DPKG_DEBS += $(RAGILE_RA_B6510_48V8C_PLATFORM_MODULE) SONIC_STRETCH_DEBS += $(RAGILE_RA_B6510_48V8C_PLATFORM_MODULE) ## RA-B6910-64C -RAGILE_RA_B6910_64C_PLATFORM_MODULE_VERSION = 1.0 -export RAGILE_RA_B6910_64C_PLATFORM_MODULE_VERSION +## RAGILE_RA_B6910_64C_PLATFORM_MODULE_VERSION = 1.0 +## export RAGILE_RA_B6910_64C_PLATFORM_MODULE_VERSION -RAGILE_RA_B6910_64C_PLATFORM_MODULE = platform-modules-ragile-ra-b6910-64c_$(RAGILE_RA_B6910_64C_PLATFORM_MODULE_VERSION)_amd64.deb -$(RAGILE_RA_B6910_64C_PLATFORM_MODULE)_PLATFORM = x86_64-ragile_ra-b6910-64c-r0 -$(eval $(call add_extra_package,$(RAGILE_RA_B6510_48V8C_PLATFORM_MODULE),$(RAGILE_RA_B6910_64C_PLATFORM_MODULE))) +## RAGILE_RA_B6910_64C_PLATFORM_MODULE = platform-modules-ragile-ra-b6910-64c_$(RAGILE_RA_B6910_64C_PLATFORM_MODULE_VERSION)_amd64.deb +## $(RAGILE_RA_B6910_64C_PLATFORM_MODULE)_PLATFORM = x86_64-ragile_ra-b6910-64c-r0 +## $(eval $(call add_extra_package,$(RAGILE_RA_B6510_48V8C_PLATFORM_MODULE),$(RAGILE_RA_B6910_64C_PLATFORM_MODULE))) ## RA-B6510-32C -RAGILE_RA_B6510_32C_PLATFORM_MODULE_VERSION = 1.0 -export RAGILE_RA_B6510_32C_PLATFORM_MODULE_VERSION +## RAGILE_RA_B6510_32C_PLATFORM_MODULE_VERSION = 1.0 +## export RAGILE_RA_B6510_32C_PLATFORM_MODULE_VERSION -RAGILE_RA_B6510_32C_PLATFORM_MODULE = platform-modules-ragile-ra-b6510-32c_$(RAGILE_RA_B6510_32C_PLATFORM_MODULE_VERSION)_amd64.deb -$(RAGILE_RA_B6510_32C_PLATFORM_MODULE)_PLATFORM = x86_64-ragile_ra-b6510-32c-r0 -$(eval $(call add_extra_package,$(RAGILE_RA_B6510_48V8C_PLATFORM_MODULE),$(RAGILE_RA_B6510_32C_PLATFORM_MODULE))) +## RAGILE_RA_B6510_32C_PLATFORM_MODULE = platform-modules-ragile-ra-b6510-32c_$(RAGILE_RA_B6510_32C_PLATFORM_MODULE_VERSION)_amd64.deb +## $(RAGILE_RA_B6510_32C_PLATFORM_MODULE)_PLATFORM = x86_64-ragile_ra-b6510-32c-r0 +## $(eval $(call add_extra_package,$(RAGILE_RA_B6510_48V8C_PLATFORM_MODULE),$(RAGILE_RA_B6510_32C_PLATFORM_MODULE))) ## RA-B6920-4s -RAGILE_RA_B6920_4S_PLATFORM_MODULE_VERSION = 1.0 -export RAGILE_RA_B6920_4S_PLATFORM_MODULE_VERSION +## RAGILE_RA_B6920_4S_PLATFORM_MODULE_VERSION = 1.0 +## export RAGILE_RA_B6920_4S_PLATFORM_MODULE_VERSION -RAGILE_RA_B6920_4S_PLATFORM_MODULE = platform-modules-ragile-ra-b6920-4s_$(RAGILE_RA_B6920_4S_PLATFORM_MODULE_VERSION)_amd64.deb -$(RAGILE_RA_B6920_4S_PLATFORM_MODULE)_PLATFORM = x86_64-ragile_ra-b6920-4s-r0 -$(eval $(call add_extra_package,$(RAGILE_RA_B6510_48V8C_PLATFORM_MODULE),$(RAGILE_RA_B6920_4S_PLATFORM_MODULE))) +## RAGILE_RA_B6920_4S_PLATFORM_MODULE = platform-modules-ragile-ra-b6920-4s_$(RAGILE_RA_B6920_4S_PLATFORM_MODULE_VERSION)_amd64.deb +## $(RAGILE_RA_B6920_4S_PLATFORM_MODULE)_PLATFORM = x86_64-ragile_ra-b6920-4s-r0 +## $(eval $(call add_extra_package,$(RAGILE_RA_B6510_48V8C_PLATFORM_MODULE),$(RAGILE_RA_B6920_4S_PLATFORM_MODULE))) diff --git a/platform/broadcom/platform-modules-ufispace.mk b/platform/broadcom/platform-modules-ufispace.mk index 1e0c4638c9de..3fc5f6e72fec 100644 --- a/platform/broadcom/platform-modules-ufispace.mk +++ b/platform/broadcom/platform-modules-ufispace.mk @@ -1,8 +1,16 @@ # UfiSpace Platform modules UFISPACE_S9300_32D_PLATFORM_MODULE_VERSION = 1.0.0 +UFISPACE_S9110_32X_PLATFORM_MODULE_VERSION = 1.0.0 +UFISPACE_S8901_54XC_PLATFORM_MODULE_VERSION = 1.0.0 +UFISPACE_S7801_54XS_PLATFORM_MODULE_VERSION = 1.0.0 +UFISPACE_S6301_56ST_PLATFORM_MODULE_VERSION = 1.0.0 export UFISPACE_S9300_32D_PLATFORM_MODULE_VERSION +export UFISPACE_S9110_32X_PLATFORM_MODULE_VERSION +export UFISPACE_S8901_54XC_PLATFORM_MODULE_VERSION +export UFISPACE_S7801_54XS_PLATFORM_MODULE_VERSION +export UFISPACE_S6301_56ST_PLATFORM_MODULE_VERSION UFISPACE_S9300_32D_PLATFORM_MODULE = sonic-platform-ufispace-s9300-32d_$(UFISPACE_S9300_32D_PLATFORM_MODULE_VERSION)_amd64.deb $(UFISPACE_S9300_32D_PLATFORM_MODULE)_SRC_PATH = $(PLATFORM_PATH)/sonic-platform-modules-ufispace @@ -10,3 +18,18 @@ $(UFISPACE_S9300_32D_PLATFORM_MODULE)_DEPENDS += $(LINUX_HEADERS) $(LINUX_HEADER $(UFISPACE_S9300_32D_PLATFORM_MODULE)_PLATFORM = x86_64-ufispace_s9300_32d-r0 SONIC_DPKG_DEBS += $(UFISPACE_S9300_32D_PLATFORM_MODULE) +UFISPACE_S9110_32X_PLATFORM_MODULE = sonic-platform-ufispace-s9110-32x_$(UFISPACE_S9110_32X_PLATFORM_MODULE_VERSION)_amd64.deb +$(UFISPACE_S9110_32X_PLATFORM_MODULE)_PLATFORM = x86_64-ufispace_s9110_32x-r0 +$(eval $(call add_extra_package,$(UFISPACE_S9300_32D_PLATFORM_MODULE),$(UFISPACE_S9110_32X_PLATFORM_MODULE))) + +UFISPACE_S8901_54XC_PLATFORM_MODULE = sonic-platform-ufispace-s8901-54xc_$(UFISPACE_S8901_54XC_PLATFORM_MODULE_VERSION)_amd64.deb +$(UFISPACE_S8901_54XC_PLATFORM_MODULE)_PLATFORM = x86_64-ufispace_s8901_54xc-r0 +$(eval $(call add_extra_package,$(UFISPACE_S9300_32D_PLATFORM_MODULE),$(UFISPACE_S8901_54XC_PLATFORM_MODULE))) + +UFISPACE_S7801_54XS_PLATFORM_MODULE = sonic-platform-ufispace-s7801-54xs_$(UFISPACE_S7801_54XS_PLATFORM_MODULE_VERSION)_amd64.deb +$(UFISPACE_S7801_54XS_PLATFORM_MODULE)_PLATFORM = x86_64-ufispace_s7801_54xs-r0 +$(eval $(call add_extra_package,$(UFISPACE_S9300_32D_PLATFORM_MODULE),$(UFISPACE_S7801_54XS_PLATFORM_MODULE))) + +UFISPACE_S6301_56ST_PLATFORM_MODULE = sonic-platform-ufispace-s6301-56st_$(UFISPACE_S6301_56ST_PLATFORM_MODULE_VERSION)_amd64.deb +$(UFISPACE_S6301_56ST_PLATFORM_MODULE)_PLATFORM = x86_64-ufispace_s6301_56st-r0 +$(eval $(call add_extra_package,$(UFISPACE_S9300_32D_PLATFORM_MODULE),$(UFISPACE_S6301_56ST_PLATFORM_MODULE))) \ No newline at end of file diff --git a/platform/broadcom/sonic-platform-modules-cel/debian/platform-modules-haliburton.init b/platform/broadcom/sonic-platform-modules-cel/debian/platform-modules-haliburton.init index 3f6358bf4ab4..aff8503d7543 100644 --- a/platform/broadcom/sonic-platform-modules-cel/debian/platform-modules-haliburton.init +++ b/platform/broadcom/sonic-platform-modules-cel/debian/platform-modules-haliburton.init @@ -53,6 +53,7 @@ start) [ $found -eq 0 ] && echo "cannot find iSMT" && exit 1 i2cset -y ${devnum} 0x73 0x10 0x00 0x01 i + sleep 0.5 # Attach PCA9548 0x73 Channel Extender for CPU Board echo pca9548 0x73 > /sys/bus/i2c/devices/i2c-${devnum}/new_device diff --git a/platform/broadcom/sonic-platform-modules-cel/debian/platform-modules-haliburton.install b/platform/broadcom/sonic-platform-modules-cel/debian/platform-modules-haliburton.install index 6c58afe6d55e..c3d598623ed5 100644 --- a/platform/broadcom/sonic-platform-modules-cel/debian/platform-modules-haliburton.install +++ b/platform/broadcom/sonic-platform-modules-cel/debian/platform-modules-haliburton.install @@ -1,5 +1,6 @@ haliburton/cfg/haliburton-modules.conf etc/modules-load.d haliburton/systemd/platform-modules-haliburton.service lib/systemd/system +haliburton/systemd/cpu_wdt.service lib/systemd/system haliburton/script/fancontrol.sh etc/init.d haliburton/script/fancontrol.service lib/systemd/system services/fancontrol/fancontrol usr/local/bin @@ -8,4 +9,5 @@ services/platform_api/platform_api_mgnt.sh usr/local/bin haliburton/script/popmsg.sh usr/local/bin haliburton/script/udev_prefix.sh usr/local/bin haliburton/script/reload_udev.sh usr/local/bin +haliburton/script/cpu_wdt usr/local/bin haliburton/script/50-ttyUSB-C0.rules etc/udev/rules.d diff --git a/platform/broadcom/sonic-platform-modules-cel/debian/platform-modules-haliburton.postinst b/platform/broadcom/sonic-platform-modules-cel/debian/platform-modules-haliburton.postinst index 57ac1be34152..d427f17579f3 100644 --- a/platform/broadcom/sonic-platform-modules-cel/debian/platform-modules-haliburton.postinst +++ b/platform/broadcom/sonic-platform-modules-cel/debian/platform-modules-haliburton.postinst @@ -3,6 +3,7 @@ depmod -a sudo chmod +x /usr/local/bin/udev_prefix.sh sudo chmod +x /usr/local/bin/popmsg.sh sudo chmod +x /usr/local/bin/reload_udev.sh +sudo chmod +x /usr/local/bin/cpu_wdt /usr/local/bin/platform_api_mgnt.sh install /etc/init.d/fancontrol.sh install @@ -10,6 +11,8 @@ sudo chmod +x /usr/local/bin/reload_udev.sh systemctl enable platform-modules-haliburton.service systemctl enable fancontrol.service +systemctl enable cpu_wdt.service systemctl start platform-modules-haliburton.service -systemctl start fancontrol.service \ No newline at end of file +systemctl start fancontrol.service +systemctl start cpu_wdt.service diff --git a/platform/broadcom/sonic-platform-modules-cel/haliburton/script/cpu_wdt b/platform/broadcom/sonic-platform-modules-cel/haliburton/script/cpu_wdt new file mode 100644 index 000000000000..8eed59013b7d --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-cel/haliburton/script/cpu_wdt @@ -0,0 +1,89 @@ +#!/bin/bash + +SYSLOG_IDENTIFIER="cpu_wdt" +CPUWDT_MAIN_TASK_RUNNING_FLAG=true +TIMEOUT=180 +KEEPALIVE=60 + +function log_info() +{ + logger -p info -t ${SYSLOG_IDENTIFIER} "$@" +} + +function usage() +{ + echo "Usage: $0 ACTION [OPTIONS]..." + echo "" + echo "Actions:" + echo " start Start CPU WDT" + echo " stop Stop CPU WDT" + echo "" + echo "Options:" + echo " -h Show this help" + echo " -t WDT timeout period: {30|60|180}, default 180" + echo " -k WDT keep alive period, {1..(timeout-5)}, default 60" + exit 1 +} + +function validate_action() +{ + if [[ "${ACTION}" != "start" && "${ACTION}" != "stop" ]]; then + echo -e "Invalid action: ${ACTION}\n" + usage + fi +} + +function validate_options() +{ + if [[ ${TIMEOUT} != "30" && ${TIMEOUT} != "60" && ${TIMEOUT} != "180" ]]; then + echo -e "Invalid timeout value: ${TIMEOUT}\n" + usage + fi + if [[ ${KEEPALIVE} -le 0 || ${KEEPALIVE} -gt $((TIMEOUT - 5)) ]]; then + echo "Invalid keepalive value: ${KEEPALIVE}" + echo "" + usage + fi +} + +trap 'log_info "Caught SIGHUP - ignoring..."' SIGHUP +trap 'log_info "Caught SIGINT - exiting..."; CPUWDT_MAIN_TASK_RUNNING_FLAG=false' SIGINT +trap 'log_info "Caught SIGTERM - exiting..."; CPUWDT_MAIN_TASK_RUNNING_FLAG=false' SIGTERM + +ACTION=$1 +shift +validate_action + +while getopts "t:k:" OPTION; do + case $OPTION in + t) + TIMEOUT=${OPTARG} + ;; + k) + KEEPALIVE=${OPTARG} + ;; + *) + usage + esac +done + +validate_options + +if [[ "${ACTION}" == "start" ]]; then + # enable + log_info "Enable CPU WDT.." + watchdogutil arm -s "${TIMEOUT}" > /dev/null + log_info "CPU WDT has been enabled with $TIMEOUT seconds timeout" + + # keep alive + log_info "Enable keep alive messaging every $KEEPALIVE seconds" + while [[ ${CPUWDT_MAIN_TASK_RUNNING_FLAG} == "true" ]]; do + watchdogutil arm -s "${TIMEOUT}" > /dev/null + sleep "${KEEPALIVE}" + done + log_info "Keep alive messaging has been disabled" +fi + +log_info "Disable CPU WDT.." +watchdogutil disarm +log_info "CPU WDT has been disabled!" diff --git a/platform/broadcom/sonic-platform-modules-cel/haliburton/systemd/cpu_wdt.service b/platform/broadcom/sonic-platform-modules-cel/haliburton/systemd/cpu_wdt.service new file mode 100644 index 000000000000..51cc537c20b9 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-cel/haliburton/systemd/cpu_wdt.service @@ -0,0 +1,10 @@ +[Unit] +Description=CPU WDT +After=platform-modules-haliburton.service +Requires=platform-modules-haliburton.service + +[Service] +ExecStart=-/usr/local/bin/cpu_wdt start + +[Install] +WantedBy=multi-user.target diff --git a/platform/broadcom/sonic-platform-modules-dell/debian/control b/platform/broadcom/sonic-platform-modules-dell/debian/control index 7ba69682ed39..d3bc5767be12 100644 --- a/platform/broadcom/sonic-platform-modules-dell/debian/control +++ b/platform/broadcom/sonic-platform-modules-dell/debian/control @@ -65,6 +65,11 @@ Architecture: amd64 Depends: linux-image-5.10.0-18-2-amd64-unsigned Description: kernel modules for platform devices such as fan, led, sfp +Package: platform-modules-e3224f +Architecture: amd64 +Depends: linux-image-5.10.0-18-2-amd64-unsigned +Description: kernel modules for platform devices such as fan, led, sfp + Package: platform-modules-s5296f Architecture: amd64 Depends: linux-image-5.10.0-18-2-amd64-unsigned diff --git a/platform/broadcom/sonic-platform-modules-dell/debian/platform-modules-e3224f.init b/platform/broadcom/sonic-platform-modules-dell/debian/platform-modules-e3224f.init new file mode 100755 index 000000000000..5b0b9597524a --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-dell/debian/platform-modules-e3224f.init @@ -0,0 +1,39 @@ +#!/bin/bash + +### BEGIN INIT INFO +# Provides: setup-board +# Required-Start: +# Required-Stop: +# Should-Start: +# Should-Stop: +# Default-Start: S +# Default-Stop: 0 6 +# Short-Description: Setup S3000 board. +### END INIT INFO + +case "$1" in +start) + echo -n "Setting up board... " + + /usr/local/bin/e3224f_platform.sh init + + echo "done." + ;; + +stop) + /usr/local/bin/e3224f_platform.sh deinit + echo "done." + + ;; + +force-reload|restart) + echo "Not supported" + ;; + +*) + echo "Usage: /etc/init.d/platform-modules-e3224f.init {start|stop}" + exit 1 + ;; +esac + +exit 0 diff --git a/platform/broadcom/sonic-platform-modules-dell/debian/platform-modules-e3224f.install b/platform/broadcom/sonic-platform-modules-dell/debian/platform-modules-e3224f.install new file mode 100644 index 000000000000..95effa8fef8f --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-dell/debian/platform-modules-e3224f.install @@ -0,0 +1,12 @@ +e3224f/scripts/e3224f_platform.sh usr/local/bin +e3224f/scripts/platform_sensors.py usr/local/bin +e3224f/scripts/sensors usr/bin +e3224f/scripts//portiocfg.py usr/local/bin +e3224f/scripts//ports_xcvrd_notify.py usr/local/bin +e3224f/systemd/platform-modules-e3224f.service etc/systemd/system +e3224f/cfg/e3224f-modules.conf etc/modules-load.d +common/dell_i2c_utils.sh usr/local/bin +e3224f/modules/sonic_platform-1.0-py3-none-any.whl usr/share/sonic/device/x86_64-dell_e3224f-r0 +common/platform_reboot usr/share/sonic/device/x86_64-dell_e3224f-r0 +common/fw-updater /usr/local/bin +common/onie_mode_set usr/local/bin diff --git a/platform/broadcom/sonic-platform-modules-dell/debian/platform-modules-e3224f.postinst b/platform/broadcom/sonic-platform-modules-dell/debian/platform-modules-e3224f.postinst new file mode 100644 index 000000000000..0af6928db1b0 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-dell/debian/platform-modules-e3224f.postinst @@ -0,0 +1,7 @@ +# postinst script for E3224F + +# Enable Dell-E3224F-platform-service +depmod -a +systemctl enable platform-modules-e3224f.service +systemctl start platform-modules-e3224f.service +#DEBHELPER# diff --git a/platform/broadcom/sonic-platform-modules-dell/debian/rules b/platform/broadcom/sonic-platform-modules-dell/debian/rules index 0c9b62fa559c..183e9439e0da 100755 --- a/platform/broadcom/sonic-platform-modules-dell/debian/rules +++ b/platform/broadcom/sonic-platform-modules-dell/debian/rules @@ -5,7 +5,7 @@ export INSTALL_MOD_DIR:=extra KVERSION ?= $(shell uname -r) KERNEL_SRC := /lib/modules/$(KVERSION) MOD_SRC_DIR:= $(shell pwd) -MODULE_DIRS:= s6000 z9100 s6100 z9264f s5212f s5224f s5232f s5248f z9332f z9432f s5296f n3248pxe n3248te +MODULE_DIRS:= s6000 z9100 s6100 z9264f s5212f s5224f s5232f s5248f z9332f z9432f s5296f n3248pxe n3248te e3224f COMMON_DIR := common %: @@ -85,6 +85,10 @@ override_dh_auto_build: cd $(MOD_SRC_DIR)/$${mod}; \ python3 setup.py bdist_wheel -d $(MOD_SRC_DIR)/$${mod}/modules; \ cd $(MOD_SRC_DIR); \ + elif [ $$mod = "e3224f" ]; then \ + cd $(MOD_SRC_DIR)/$${mod}; \ + python3 setup.py bdist_wheel -d $(MOD_SRC_DIR)/$${mod}/modules; \ + cd $(MOD_SRC_DIR); \ fi; \ echo "making man page alias $$mod -> $$mod APIs";\ make -C $(KERNEL_SRC)/build M=$(MOD_SRC_DIR)/$${mod}/modules; \ @@ -187,6 +191,11 @@ override_dh_clean: rm -f $(MOD_SRC_DIR)/$${mod}/modules/*.whl; \ rm -rf $(MOD_SRC_DIR)/$${mod}/build; \ rm -rf $(MOD_SRC_DIR)/$${mod}/build/*.egg-info; \ + elif [ $$mod = "e3224f" ]; then \ + rm -f $(MOD_SRC_DIR)/$${mod}/sonic_platform/ipmihelper.py; \ + rm -f $(MOD_SRC_DIR)/$${mod}/modules/*.whl; \ + rm -rf $(MOD_SRC_DIR)/$${mod}/build; \ + rm -rf $(MOD_SRC_DIR)/$${mod}/build/*.egg-info; \ fi; \ make -C $(KERNEL_SRC)/build M=$(MOD_SRC_DIR)/$${mod}/modules clean; \ done); \ diff --git a/platform/broadcom/sonic-platform-modules-dell/e3224f/cfg/e3224f-modules.conf b/platform/broadcom/sonic-platform-modules-dell/e3224f/cfg/e3224f-modules.conf new file mode 100644 index 000000000000..fac96cee335e --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-dell/e3224f/cfg/e3224f-modules.conf @@ -0,0 +1,14 @@ +# /etc/modules: kernel modules to load at boot time. +# +# This file contains the names of kernel modules that should be loaded +# at boot time, one per line. Lines beginning with "#" are ignored. + +i2c-isch +i2c-ismt +i2c-dev +i2c-mux +i2c-smbus + +i2c-mux-pca954x +dell_e3224f_platform + diff --git a/platform/broadcom/sonic-platform-modules-dell/e3224f/modules/Makefile b/platform/broadcom/sonic-platform-modules-dell/e3224f/modules/Makefile new file mode 100644 index 000000000000..521bb070717c --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-dell/e3224f/modules/Makefile @@ -0,0 +1,2 @@ +obj-m := dell_e3224f_platform.o emc2305.o + diff --git a/platform/broadcom/sonic-platform-modules-dell/e3224f/modules/dell_e3224f_platform.c b/platform/broadcom/sonic-platform-modules-dell/e3224f/modules/dell_e3224f_platform.c new file mode 100644 index 000000000000..4c19f7d38760 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-dell/e3224f/modules/dell_e3224f_platform.c @@ -0,0 +1,1563 @@ +/* Copyright (c) 2020 Dell Inc. + * dell_e3224f_platform.c - Driver for E3224F switches + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + + #define PSU_MODULE_BASE_NR 10 + #define FANTRAY_MODULE_BASE_NR 15 + #define SFP_MODULE_BASE_NR 20 + #define SFP_MUX_BASE_NR 8 + #define FANTRAY_MUX_BASE_NR 4 + #define PSU_MUX_BASE_NR 5 + + #define PHY_RESET_REG 0x40 + #define RESET_ALL_PHY 0x7F + #define SYS_CTRL_REG 0x15 + #define POWER_CYCLE_SYS 0x1 + #define CPLD_DEVICE_NUM 3 + #define PF_MUX_DEVICES 3 + #define SYS_MISC_CTRL_REG 0x0B + + #define FAN_0 0 + #define FAN_1 1 + #define FAN_2 2 + + static int get_i2c_adapter_name(void); + + static void device_release(struct device *dev) + { + return; + } + + /* + * E3224F CPLD + */ + + enum cpld_type { + cpu_cpld, + sys_cpld, + port_cpld, + }; + + struct cpld_platform_data { + int reg_addr; + struct i2c_client *client; + }; + + static struct cpld_platform_data e3224f_cpld_platform_data[] = { + [cpu_cpld] = { + .reg_addr = 0x31, + }, + + [sys_cpld] = { + .reg_addr = 0x32, + }, + + [port_cpld] = { + .reg_addr = 0x34, + }, + }; + + static struct platform_device e3224f_cpld = { + .name = "dell-e3224f-cpld", + .id = 0, + .dev = { + .platform_data = e3224f_cpld_platform_data, + .release = device_release + }, + }; + + /* + * E3224F MUX + */ + + struct mux_platform_data { + int parent; + int base_nr; + int reg_addr; + struct i2c_client *cpld; + int no_of_buses; + int mux_offset; + }; + + struct pf_mux { + struct mux_platform_data data; + }; + + static struct mux_platform_data e3224f_mux_platform_data[] = { + { + .parent = SFP_MUX_BASE_NR, + .base_nr = SFP_MODULE_BASE_NR, + .cpld = NULL, + .reg_addr = 0x11, + .no_of_buses = 31, + .mux_offset = 1, + }, + { + .parent = FANTRAY_MUX_BASE_NR, + .base_nr = FANTRAY_MODULE_BASE_NR, + .cpld = NULL, + .reg_addr = 0x13, + .no_of_buses = 3, + .mux_offset = 1, + }, + { + .parent = PSU_MUX_BASE_NR, + .base_nr = PSU_MODULE_BASE_NR, + .cpld = NULL, + .reg_addr = 0x12, + .no_of_buses = 2, + .mux_offset = 1, + }, + }; + + static struct platform_device e3224f_mux[] = { + { + .name = "dell-e3224f-mux", + .id = 0, + .dev = { + .platform_data = &e3224f_mux_platform_data[0], + .release = device_release, + }, + }, + { + .name = "dell-e3224f-mux", + .id = 1, + .dev = { + .platform_data = &e3224f_mux_platform_data[1], + .release = device_release, + }, + }, + { + .name = "dell-e3224f-mux", + .id = 2, + .dev = { + .platform_data = &e3224f_mux_platform_data[2], + .release = device_release, + }, + }, + }; + + static int cpld_reg_write_byte(struct i2c_client *client, u8 regaddr, u8 val) + { + union i2c_smbus_data data; + + data.byte = val; + return client->adapter->algo->smbus_xfer(client->adapter, client->addr, + client->flags, + I2C_SMBUS_WRITE, + regaddr, I2C_SMBUS_BYTE_DATA, &data); + } + + static int mux_select(struct i2c_mux_core *muxc, u32 chan) + { + struct pf_mux *mux = i2c_mux_priv(muxc); + u8 chan_data = chan + mux->data.mux_offset; + + return cpld_reg_write_byte(mux->data.cpld, mux->data.reg_addr, chan_data); + } + + static int __init mux_probe(struct platform_device *pdev) + { + struct i2c_mux_core *muxc; + struct pf_mux *mux; + struct mux_platform_data *pdata; + struct i2c_adapter *parent; + int i, ret; + + pdata = pdev->dev.platform_data; + if (!pdata) { + dev_err(&pdev->dev, "Missing platform data\n"); + return -ENODEV; + } + + mux = devm_kzalloc(&pdev->dev, sizeof(*mux), GFP_KERNEL); + if (!mux) { + return -ENOMEM; + } + + mux->data = *pdata; + + parent = i2c_get_adapter(pdata->parent); + if (!parent) { + dev_err(&pdev->dev, "Parent adapter (%d) not found\n", + pdata->parent); + return -EPROBE_DEFER; + } + + muxc = i2c_mux_alloc(parent, &pdev->dev, pdata->no_of_buses, 0, 0, + mux_select, NULL); + if (!muxc) { + ret = -ENOMEM; + goto alloc_failed; + } + muxc->priv = mux; + + platform_set_drvdata(pdev, muxc); + + for (i = 0; i < pdata->no_of_buses; i++) { + int nr = pdata->base_nr + i; + unsigned int class = 0; + + ret = i2c_mux_add_adapter(muxc, nr, i, class); + if (ret) { + dev_err(&pdev->dev, "Failed to add adapter %d\n", i); + goto add_adapter_failed; + } + } + + return 0; + + add_adapter_failed: + i2c_mux_del_adapters(muxc); + alloc_failed: + i2c_put_adapter(parent); + + return ret; + } + + static int mux_remove(struct platform_device *pdev) + { + struct i2c_mux_core *muxc = platform_get_drvdata(pdev); + + i2c_mux_del_adapters(muxc); + + i2c_put_adapter(muxc->parent); + + return 0; + } + + static struct platform_driver mux_driver = { + .probe = mux_probe, + .remove = mux_remove, + .driver = { + .owner = THIS_MODULE, + .name = "dell-e3224f-mux", + }, + }; + + static ssize_t sfp_modprs_show (struct device *dev, struct device_attribute *devattr, char *buf) + { + int i; + s32 ret = 0; + uint32_t data=0; + struct cpld_platform_data *pdata = dev->platform_data; + + for (i=0;i<=2;i++) { + ret = i2c_smbus_read_byte_data(pdata[port_cpld].client, 0x10+i); + if (ret < 0) + return sprintf(buf, "read error"); + + data = data + ret << (8*i); + //printk(KERN_WARNING "sfp_modprs_show %d %x %x\n",i,ret,data); + } + + return sprintf(buf, "0x%x\n", data); + } + + static ssize_t sfp_txdis_show (struct device *dev, struct device_attribute *devattr, char *buf) + { + int i; + s32 ret = 0; + uint32_t data=0; + struct cpld_platform_data *pdata = dev->platform_data; + + for (i=0;i<=2;i++) { + ret = i2c_smbus_read_byte_data(pdata[port_cpld].client, 0x14+i); + if (ret < 0) + return sprintf(buf, "read error"); + + data = data + (ret << (8*i)); + //printk(KERN_WARNING "sfp_txdis_show %d %x %x\n",i,ret,data); + } + return sprintf(buf, "0x%x\n", (uint32_t)data); + } + + static ssize_t sfp_txdis_store (struct device *dev, struct device_attribute *devattr, const char *buf, size_t size) + { + int i; + s32 ret = 0; + long value=0; + u8 data; + struct cpld_platform_data *pdata = dev->platform_data; + ssize_t status; + + status = kstrtol(buf, 0, &value); + printk(KERN_WARNING "sfp_txdis_store %x\n",value); + if (status == 0) { + + for (i=0;i<=2;i++) { + ret = i2c_smbus_read_byte_data(pdata[port_cpld].client, 0x14+i); + if (ret < 0) + return sprintf(buf, "read error"); + + data = ((value >> (8*i)) & 0xFF); + printk(KERN_WARNING " txdis [%d] read[%x] data[%x]\n",i,ret,data); + + if (ret != data) { + printk(KERN_WARNING " txdis write [%d] \n",i); + status = i2c_smbus_write_byte_data(pdata[port_cpld].client, 0x14+i, data); + if (status < 0) + printk(KERN_WARNING " txdis failed to set [%d] data[%x]\n",i,data); + } + } + status = size; + } + return status; + } + + static ssize_t sfp_rxlos_show (struct device *dev, struct device_attribute *devattr, char *buf) + { + int i; + s32 ret = 0; + uint32_t data=0; + struct cpld_platform_data *pdata = dev->platform_data; + + for (i=0;i<=2;i++) { + ret = i2c_smbus_read_byte_data(pdata[port_cpld].client, 0x18+i); + if (ret < 0) + return sprintf(buf, "read error"); + + data = data + (ret << (8*i)); + printk(KERN_WARNING "sfp_rxlos_show %d %x %x\n",i,ret,data); + } + return sprintf(buf, "0x%x\n", (uint32_t)data); + } + + static ssize_t sfp_txfault_show (struct device *dev, struct device_attribute *devattr, char *buf) + { + int i; + s32 ret = 0; + uint32_t data=0; + struct cpld_platform_data *pdata = dev->platform_data; + + for (i=0;i<=2;i++) { + ret = i2c_smbus_read_byte_data(pdata[port_cpld].client, 0x1C+i); + if (ret < 0) + return sprintf(buf, "read error"); + + data = data + (ret << (8*i)); + printk(KERN_WARNING "sfp_txfault_show %d %x %x\n",i,ret,data); + } + return sprintf(buf, "0x%x\n", (uint32_t)data); + } + + static ssize_t sfpplus_modprs_show (struct device *dev, struct device_attribute *devattr, char *buf) + { + s32 ret = 0; + struct cpld_platform_data *pdata = dev->platform_data; + + ret = i2c_smbus_read_byte_data(pdata[sys_cpld].client, 0x30); + if (ret < 0) + return sprintf(buf, "read error"); + + return sprintf(buf, "0x%x\n", (u8)ret); + } + + static ssize_t sfpplus_txdis_show (struct device *dev, struct device_attribute *devattr, char *buf) + { + s32 ret = 0; + struct cpld_platform_data *pdata = dev->platform_data; + + ret = i2c_smbus_read_byte_data(pdata[sys_cpld].client, 0x31); + if (ret < 0) + return sprintf(buf, "read error"); + + return sprintf(buf, "0x%x\n", (u8)ret); + } + + static ssize_t sfpplus_txdis_store (struct device *dev, struct device_attribute *devattr, const char *buf, size_t size) + { + long value; + struct cpld_platform_data *pdata = dev->platform_data; + s32 ret; + u8 data; + ssize_t status; + + status = kstrtol(buf, 0, &value); + if (status == 0) { + ret = i2c_smbus_read_byte_data(pdata[sys_cpld].client, 0x31); + if (ret < 0) + return ret; + data = (u8)ret & ~(0x0F); + data = data | (value & 0x0F); + + ret = i2c_smbus_write_byte_data(pdata[sys_cpld].client, 0x31, data); + if (ret < 0) + return ret; + + status = size; + } + + return status; + } + + static ssize_t sfpplus_rxlos_show (struct device *dev, struct device_attribute *devattr, char *buf) + { + s32 ret = 0; + struct cpld_platform_data *pdata = dev->platform_data; + + ret = i2c_smbus_read_byte_data(pdata[sys_cpld].client, 0x32); + if (ret < 0) + return sprintf(buf, "read error"); + + return sprintf(buf, "0x%x\n", (u8)ret); + } + + static ssize_t sfpplus_txfault_show (struct device *dev, struct device_attribute *devattr, char *buf) + { + s32 ret = 0; + struct cpld_platform_data *pdata = dev->platform_data; + + ret = i2c_smbus_read_byte_data(pdata[sys_cpld].client, 0x33); + if (ret < 0) + return sprintf(buf, "read error"); + + return sprintf(buf, "0x%x\n", (u8)ret); + } + + static ssize_t qsfp_modprs_show (struct device *dev, struct device_attribute *devattr, char *buf) + { + s32 ret = 0; + struct cpld_platform_data *pdata = dev->platform_data; + + ret = i2c_smbus_read_byte_data(pdata[sys_cpld].client, 0x20); + if (ret < 0) + return sprintf(buf, "read error"); + + return sprintf(buf, "0x%x\n", (u8)ret); + } + + static ssize_t qsfp_rst_show (struct device *dev, struct device_attribute *devattr, char *buf) + { + s32 ret = 0; + struct cpld_platform_data *pdata = dev->platform_data; + + ret = i2c_smbus_read_byte_data(pdata[sys_cpld].client, 0x21); + if (ret < 0) + return sprintf(buf, "read error"); + + return sprintf(buf, "0x%x\n", (u8)ret); + } + + static ssize_t qsfp_rst_store (struct device *dev, struct device_attribute *devattr, const char *buf, size_t size) + { + long value; + struct cpld_platform_data *pdata = dev->platform_data; + s32 ret; + u8 data; + ssize_t status; + + status = kstrtol(buf, 0, &value); + if (status == 0) { + ret = i2c_smbus_read_byte_data(pdata[sys_cpld].client, 0x21); + if (ret < 0) + return ret; + data = (u8)ret & ~(0x0F); + data = data | (value & 0x0F); + + ret = i2c_smbus_write_byte_data(pdata[sys_cpld].client, 0x21, data); + if (ret < 0) + return ret; + + status = size; + } + + return status; + } + + static ssize_t qsfp_lpmode_show (struct device *dev, struct device_attribute *devattr, char *buf) + { + s32 ret = 0; + struct cpld_platform_data *pdata = dev->platform_data; + + ret = i2c_smbus_read_byte_data(pdata[sys_cpld].client, 0x22); + if (ret < 0) + return sprintf(buf, "read error"); + + return sprintf(buf, "0x%x\n", (u8)ret); + } + + static ssize_t qsfp_lpmode_store (struct device *dev, struct device_attribute *devattr, const char *buf, size_t size) + { + long value; + struct cpld_platform_data *pdata = dev->platform_data; + s32 ret; + u8 data; + ssize_t status; + + status = kstrtol(buf, 0, &value); + if (status == 0) { + ret = i2c_smbus_read_byte_data(pdata[sys_cpld].client, 0x22); + if (ret < 0) + return ret; + data = (u8)ret & ~(0x0F); + data = data | (value & 0x0F); + + ret = i2c_smbus_write_byte_data(pdata[sys_cpld].client, 0x22, data); + if (ret < 0) + return ret; + + status = size; + } + + return status; + } + + static ssize_t reboot_cause_show (struct device *dev, struct device_attribute *devattr, char *buf) + { + s32 ret = 0; + u8 data; + struct cpld_platform_data *pdata = dev->platform_data; + + ret = i2c_smbus_read_byte_data(pdata[sys_cpld].client, 0x10); + if (ret < 0) + return sprintf(buf, "read error"); + + data = (u8)ret; + return sprintf(buf, "0x%x\n", data); + } + + static ssize_t reboot_cause_store(struct device *dev, struct device_attribute *devattr, const char *buf, size_t count) + { + unsigned long data; + s32 status, ret; + struct cpld_platform_data *pdata = dev->platform_data; + + status = kstrtoul(buf, 0, &data); + ret = i2c_smbus_write_byte_data(pdata[sys_cpld].client, 0x10, (u8)(data)); + if (ret < 0) + return ret; + return count; + } + + static ssize_t power_reset_store(struct device *dev, struct device_attribute *devattr, const char *buf, size_t count) + { + unsigned long data; + s32 err; + struct cpld_platform_data *pdata = dev->platform_data; + + err = kstrtoul(buf, 10, &data); + if (err) + return err; + + if (data) + { + i2c_smbus_write_byte_data(pdata[sys_cpld].client, SYS_CTRL_REG, (u8)(POWER_CYCLE_SYS)); + } + + return count; + } + + static ssize_t power_reset_show(struct device *dev, struct device_attribute *devattr, char *buf) + { + s32 ret = 0; + struct cpld_platform_data *pdata = dev->platform_data; + + ret = i2c_smbus_read_byte_data(pdata[sys_cpld].client, SYS_CTRL_REG); + if (ret < 0) + return sprintf(buf, "read error"); + + return sprintf(buf, "0x%x\n", ret); + } + + static ssize_t fan_dir_show(struct device *dev, struct device_attribute *devattr, char *buf) + { + s32 ret; + u8 data = 0; + struct cpld_platform_data *pdata = dev->platform_data; + struct sensor_device_attribute *sa = to_sensor_dev_attr(devattr); + int index = sa->index; + u8 mask = 1 << (index+4); + + ret = i2c_smbus_read_byte_data(pdata[sys_cpld].client, 0xA); + if (ret < 0) + return sprintf(buf, "read error"); + data = (u8)((ret & mask) >> (index+4)); + + return sprintf(buf, "%s\n", data? "B2F" : "F2B"); +} + +static ssize_t fan_prs_show(struct device *dev, struct device_attribute *devattr, char *buf) +{ + s32 ret; + u8 data = 0; + struct cpld_platform_data *pdata = dev->platform_data; + struct sensor_device_attribute *sa = to_sensor_dev_attr(devattr); + int index = sa->index; + uint8_t mask = 1 << index; + + ret = i2c_smbus_read_byte_data(pdata[sys_cpld].client, 0xA); + if (ret < 0) + return sprintf(buf, "read error"); + data = (u32)((ret & mask) >> index); + + data = ~data & 0x1; + + return sprintf(buf, "0x%x\n", data); +} + +static ssize_t psu0_prs_show(struct device *dev, struct device_attribute *devattr, char *buf) +{ + s32 ret; + u8 data = 0; + struct cpld_platform_data *pdata = dev->platform_data; + + ret = i2c_smbus_read_byte_data(pdata[sys_cpld].client, 0xC); + if (ret < 0) + return sprintf(buf, "read error"); + + if (!(ret & 0x80)) + data = 1; + + return sprintf(buf, "%d\n", data); +} + +static ssize_t psu1_prs_show(struct device *dev, struct device_attribute *devattr, char *buf) +{ + s32 ret; + u8 data = 0; + struct cpld_platform_data *pdata = dev->platform_data; + + ret = i2c_smbus_read_byte_data(pdata[sys_cpld].client, 0xC); + if (ret < 0) + return sprintf(buf, "read error"); + + if (!(ret & 0x08)) + data = 1; + + return sprintf(buf, "%d\n", data); +} + +static ssize_t psu0_status_show(struct device *dev, struct device_attribute *devattr, char *buf) +{ + s32 ret; + u8 data = 0; + struct cpld_platform_data *pdata = dev->platform_data; + + ret = i2c_smbus_read_byte_data(pdata[sys_cpld].client, 0xC); + if (ret < 0) + return sprintf(buf, "read error"); + + if ((ret & 0x40)) + data = 1; + + return sprintf(buf, "%d\n", data); +} + +static ssize_t psu1_status_show(struct device *dev, struct device_attribute *devattr, char *buf) +{ + s32 ret; + u8 data = 0; + struct cpld_platform_data *pdata = dev->platform_data; + + ret = i2c_smbus_read_byte_data(pdata[sys_cpld].client, 0xC); + if (ret < 0) + return sprintf(buf, "read error"); + + if ((ret & 0x04)) + data = 1; + + return sprintf(buf, "%d\n", data); +} + +static ssize_t fani_led_show(struct device *dev, struct device_attribute *devattr, char *buf) +{ + s32 ret; + u8 data = 0; + struct cpld_platform_data *pdata = dev->platform_data; + struct sensor_device_attribute *sa = to_sensor_dev_attr(devattr); + int index = sa->index; + uint8_t mask = 3 << (index*2); + + ret = i2c_smbus_read_byte_data(pdata[sys_cpld].client, 0x9); + if (ret < 0) + return sprintf(buf, "read error"); + + data = (u32)(ret & mask) >> (index*2); + + switch (data) + { + case 0: + ret = sprintf(buf, "off\n"); + break; + case 1: + ret = sprintf(buf, "green\n"); + break; + case 2: + ret = sprintf(buf, "amber\n"); + break; + default: + ret = sprintf(buf, "unknown\n"); + } + + return ret; +} + +static ssize_t fani_led_store(struct device *dev, struct device_attribute *devattr, const char *buf, size_t count) +{ + s32 ret; + u8 mask, data = 0; + struct cpld_platform_data *pdata = dev->platform_data; + struct sensor_device_attribute *sa = to_sensor_dev_attr(devattr); + int index = sa->index; + + if (!strncmp(buf, "off", 3)) + { + data = 0; + } + else if (!strncmp(buf, "amber", 5)) + { + data = 2; + } + else if (!strncmp(buf, "green", 5)) + { + data = 1; + } + else + { + return -1; + } + + + mask = ~((uint8_t)(3 << (index*2))); + ret = i2c_smbus_read_byte_data(pdata[sys_cpld].client, 0x9); + if (ret < 0) + return ret; + + ret = i2c_smbus_write_byte_data(pdata[sys_cpld].client, 0x9, (u8)((ret & mask) | (data << (index * 2)))); + if (ret < 0) + return ret; + + return count; +} + +static ssize_t system_led_show(struct device *dev, struct device_attribute *devattr, char *buf) +{ + s32 ret; + u8 data = 0; + struct cpld_platform_data *pdata = dev->platform_data; + + ret = i2c_smbus_read_byte_data(pdata[sys_cpld].client, 0x7); + if (ret < 0) + return sprintf(buf, "read error"); + + data = (u8)(ret & 0x30) >> 4; + + switch (data) + { + case 0: + ret = sprintf(buf, "blink_green\n"); + break; + case 1: + ret = sprintf(buf, "green\n"); + break; + case 2: + ret = sprintf(buf, "yellow\n"); + break; + default: + ret = sprintf(buf, "blink_yellow\n"); + } + + return ret; +} + +static ssize_t system_led_store(struct device *dev, struct device_attribute *devattr, const char *buf, size_t count) +{ + s32 ret; + u8 data = 0; + struct cpld_platform_data *pdata = dev->platform_data; + + if (!strncmp(buf, "blink_green", 11)) + { + data = 0; + } + else if (!strncmp(buf, "green", 5)) + { + data = 1; + } + else if (!strncmp(buf, "yellow", 6)) + { + data = 2; + } + else if (!strncmp(buf, "blink_yellow", 12)) + { + data = 3; + } + else + { + return -1; + } + + ret = i2c_smbus_read_byte_data(pdata[sys_cpld].client, 0x7); + if (ret < 0) + return ret; + + ret = i2c_smbus_write_byte_data(pdata[sys_cpld].client, 0x7, (u8)((ret & 0xCF) | (data << 4))); + if (ret < 0) + return ret; + + return count; +} + +static ssize_t watchdog_show(struct device *dev, + struct device_attribute *devattr, char *buf) +{ + s32 ret; + u8 data = 0; + struct cpld_platform_data *pdata = dev->platform_data; + + ret = i2c_smbus_read_byte_data(pdata[cpu_cpld].client, 0x7); + if (ret < 0) + return sprintf(buf, "read error"); + data = ret; + + return sprintf(buf, "%x\n", data); +} + +static ssize_t watchdog_store(struct device *dev, struct device_attribute *devattr, const char *buf, size_t count) +{ + s32 ret, err; + unsigned long val; + u8 data = 0; + struct cpld_platform_data *pdata = dev->platform_data; + + err = kstrtoul(buf, 10, &val); + if (err) + return err; + + data = (u8) val; + if (data) + { + ret = i2c_smbus_write_byte_data(pdata[cpu_cpld].client, 0x7, data); + if (ret < 0) + return ret; + } + + return count; +} + +static ssize_t locator_led_show(struct device *dev, struct device_attribute *devattr, char *buf) +{ + s32 ret; + u8 data = 0; + struct cpld_platform_data *pdata = dev->platform_data; + + ret = i2c_smbus_read_byte_data(pdata[sys_cpld].client, 0x7); + if (ret < 0) + return sprintf(buf, "read error"); + + data = (u32)(ret & 0x08) >> 3; + + switch (data) + { + case 0: + ret = sprintf(buf, "off\n"); + break; + case 1: + ret = sprintf(buf, "blink_blue\n"); + break; + default: + ret = sprintf(buf, "invalid\n"); + } + + return ret; +} + +static ssize_t locator_led_store(struct device *dev, struct device_attribute *devattr, const char *buf, size_t count) +{ + s32 ret; + u8 data = 0; + struct cpld_platform_data *pdata = dev->platform_data; + + if (!strncmp(buf, "off", 3)) + { + data = 0; + } + else if (!strncmp(buf, "blink_blue", 10)) + { + data = 1; + } + else + { + return -1; + } + + ret = i2c_smbus_read_byte_data(pdata[sys_cpld].client, 0x7); + if (ret < 0) + return ret; + + ret = i2c_smbus_write_byte_data(pdata[sys_cpld].client, 0x7, (u8)((ret & 0xF7) | (data << 3))); + if (ret < 0) + return ret; + + return count; +} + +static ssize_t power_led_show(struct device *dev, struct device_attribute *devattr, char *buf) +{ + s32 ret; + u8 data = 0; + struct cpld_platform_data *pdata = dev->platform_data; + + ret = i2c_smbus_read_byte_data(pdata[sys_cpld].client, 0x7); + if (ret < 0) + return sprintf(buf, "read error"); + + data = (u32)(ret & 0x06) >> 1; + + switch (data) + { + case 0: + ret = sprintf(buf, "off\n"); + break; + case 1: + ret = sprintf(buf, "yellow\n"); + break; + case 2: + ret = sprintf(buf, "green\n"); + break; + default: + ret = sprintf(buf, "blink_yellow\n"); + } + + return ret; +} + +static ssize_t power_led_store(struct device *dev, struct device_attribute *devattr, const char *buf, size_t count) +{ + s32 ret; + u8 data = 0; + struct cpld_platform_data *pdata = dev->platform_data; + + if (!strncmp(buf, "off", 3)) + { + data = 0; + } + else if (!strncmp(buf, "yellow", 6)) + { + data = 1; + } + else if (!strncmp(buf, "green", 5)) + { + data = 2; + } + else if (!strncmp(buf, "blink_yellow", 12)) + { + data = 3; + } + else + { + return -1; + } + + ret = i2c_smbus_read_byte_data(pdata[sys_cpld].client, 0x7); + if (ret < 0) + return ret; + + ret = i2c_smbus_write_byte_data(pdata[sys_cpld].client, 0x7, (u8)((ret & 0xF9) | (data << 1))); + if (ret < 0) + return ret; + + return count; +} + +static ssize_t primary_led_show(struct device *dev, struct device_attribute *devattr, char *buf) +{ + s32 ret; + u8 data = 0; + struct cpld_platform_data *pdata = dev->platform_data; + + ret = i2c_smbus_read_byte_data(pdata[sys_cpld].client, 0x7); + if (ret < 0) + return sprintf(buf, "read error"); + + data = (u32)(ret & 0x1); + + switch (data) + { + case 0: + ret = sprintf(buf, "green\n"); + break; + default: + ret = sprintf(buf, "off\n"); + break; + } + + return ret; +} + +static ssize_t primary_led_store(struct device *dev, struct device_attribute *devattr, const char *buf, size_t count) +{ + s32 ret; + u8 data = 0; + struct cpld_platform_data *pdata = dev->platform_data; + + if (!strncmp(buf, "green", 5)) + { + data = 0; + } + else if (!strncmp(buf, "off", 3)) + { + data = 1; + } + else + { + return -1; + } + + ret = i2c_smbus_read_byte_data(pdata[sys_cpld].client, 0x7); + if (ret < 0) + return ret; + + ret = i2c_smbus_write_byte_data(pdata[sys_cpld].client, 0x7, (u8)((ret & 0xFE) | data)); + if (ret < 0) + return ret; + + return count; +} + +static ssize_t fan_led_show(struct device *dev, struct device_attribute *devattr, char *buf) +{ + s32 ret; + u8 data = 0; + struct cpld_platform_data *pdata = dev->platform_data; + + ret = i2c_smbus_read_byte_data(pdata[sys_cpld].client, 0x7); + if (ret < 0) + return sprintf(buf, "read error"); + + data = (u8)(ret & 0xC0) >> 6; + + switch (data) + { + case 0: + ret = sprintf(buf, "off\n"); + break; + case 1: + ret = sprintf(buf, "yellow\n"); + break; + case 2: + ret = sprintf(buf, "green\n"); + break; + default: + ret = sprintf(buf, "blink_yellow\n"); + } + + return ret; +} + +static ssize_t fan_led_store(struct device *dev, struct device_attribute *devattr, const char *buf, size_t count) +{ + s32 ret; + u8 data = 0; + struct cpld_platform_data *pdata = dev->platform_data; + + if (!strncmp(buf, "off", 3)) + { + data = 0; + } + else if (!strncmp(buf, "yellow", 6)) + { + data = 1; + } + else if (!strncmp(buf, "green", 5)) + { + data = 2; + } + else if (!strncmp(buf, "blink_yellow", 12)) + { + data = 3; + } + else + { + return -1; + } + + ret = i2c_smbus_read_byte_data(pdata[sys_cpld].client, 0x7); + if (ret < 0) + return ret; + + ret = i2c_smbus_write_byte_data(pdata[sys_cpld].client, 0x7, (u8)((ret & 0x3F) | (data << 6))); + if (ret < 0) + return ret; + + return count; +} + + +static ssize_t power_good_show(struct device *dev, + struct device_attribute *devattr, char *buf) +{ + s32 ret; + u8 pwr_good1 = 0; + u8 pwr_good2 = 0; + struct cpld_platform_data *pdata = dev->platform_data; + + ret = i2c_smbus_read_byte_data(pdata[cpu_cpld].client, 0xc); + if (ret < 0) + return sprintf(buf, "read error"); + pwr_good1 = ret; + + ret = i2c_smbus_read_byte_data(pdata[cpu_cpld].client, 0xd); + if (ret < 0) + return sprintf(buf, "read error"); + pwr_good2 = ret; + + return sprintf(buf, "0x%x\n", (pwr_good1 == 0xFF && (pwr_good2 & 0x1F) == 0x1F)); +} + +static ssize_t cpu_cpld_mjr_ver_show(struct device *dev, + struct device_attribute *devattr, char *buf) +{ + s32 ret; + u8 data = 0; + struct cpld_platform_data *pdata = dev->platform_data; + + ret = i2c_smbus_read_byte_data(pdata[cpu_cpld].client, 0x1); + if (ret < 0) + return sprintf(buf, "read error"); + data = ret; + + return sprintf(buf, "0x%x\n", data); +} + +static ssize_t cpu_cpld_mnr_ver_show(struct device *dev, + struct device_attribute *devattr, char *buf) +{ + s32 ret; + u8 data = 0; + struct cpld_platform_data *pdata = dev->platform_data; + + ret = i2c_smbus_read_byte_data(pdata[cpu_cpld].client, 0x0); + if (ret < 0) + return sprintf(buf, "read error"); + data = ret; + + return sprintf(buf, "0x%x\n", data); +} + +static ssize_t sys_cpld_mjr_ver_show(struct device *dev, + struct device_attribute *devattr, char *buf) +{ + s32 ret; + u8 data = 0; + struct cpld_platform_data *pdata = dev->platform_data; + + ret = i2c_smbus_read_byte_data(pdata[sys_cpld].client, 0x1); + if (ret < 0) + return sprintf(buf, "read error"); + data = ret; + + return sprintf(buf, "0x%x\n", data); +} + +static ssize_t sys_cpld_mnr_ver_show(struct device *dev, + struct device_attribute *devattr, char *buf) +{ + s32 ret; + u8 data = 0; + struct cpld_platform_data *pdata = dev->platform_data; + + ret = i2c_smbus_read_byte_data(pdata[sys_cpld].client, 0x0); + if (ret < 0) + return sprintf(buf, "read error"); + data = ret; + + return sprintf(buf, "0x%x\n", data); +} + +static ssize_t port_cpld_mjr_ver_show(struct device *dev, + struct device_attribute *devattr, char *buf) +{ + s32 ret; + u8 data = 0; + struct cpld_platform_data *pdata = dev->platform_data; + + ret = i2c_smbus_read_byte_data(pdata[port_cpld].client, 0x1); + if (ret < 0) + return sprintf(buf, "read error"); + data = ret; + printk(KERN_WARNING "port_cpld_mjr_ver_show %d\n",ret); + + return sprintf(buf, "0x%x\n", data); +} + +static ssize_t port_cpld_mnr_ver_show(struct device *dev, + struct device_attribute *devattr, char *buf) +{ + s32 ret; + u8 data = 0; + struct cpld_platform_data *pdata = dev->platform_data; + + ret = i2c_smbus_read_byte_data(pdata[port_cpld].client, 0x0); + if (ret < 0) + return sprintf(buf, "read error"); + data = ret; + + return sprintf(buf, "0x%x\n", data); +} + +static DEVICE_ATTR_RW(sfp_txdis); +static DEVICE_ATTR_RO(sfp_modprs); +static DEVICE_ATTR_RO(sfp_rxlos); +static DEVICE_ATTR_RO(sfp_txfault); +static DEVICE_ATTR_RW(sfpplus_txdis); +static DEVICE_ATTR_RO(sfpplus_modprs); +static DEVICE_ATTR_RO(sfpplus_rxlos); +static DEVICE_ATTR_RO(sfpplus_txfault); +static DEVICE_ATTR_RO(qsfp_modprs); +static DEVICE_ATTR_RW(qsfp_rst); +static DEVICE_ATTR_RW(qsfp_lpmode); +static DEVICE_ATTR_RW(reboot_cause); +static DEVICE_ATTR_RW(power_reset); +static DEVICE_ATTR_RO(psu0_prs); +static DEVICE_ATTR_RO(psu1_prs); +static DEVICE_ATTR_RO(psu0_status); +static DEVICE_ATTR_RO(psu1_status); +static DEVICE_ATTR_RW(system_led); +static DEVICE_ATTR_RW(watchdog); +static DEVICE_ATTR_RW(locator_led); +static DEVICE_ATTR_RW(power_led); +static DEVICE_ATTR_RW(primary_led); +static DEVICE_ATTR_RW(fan_led); +static DEVICE_ATTR_RO(power_good); +static DEVICE_ATTR_RO(cpu_cpld_mjr_ver); +static DEVICE_ATTR_RO(cpu_cpld_mnr_ver); +static DEVICE_ATTR_RO(sys_cpld_mjr_ver); +static DEVICE_ATTR_RO(sys_cpld_mnr_ver); +static DEVICE_ATTR_RO(port_cpld_mjr_ver); +static DEVICE_ATTR_RO(port_cpld_mnr_ver); + +static SENSOR_DEVICE_ATTR(fan0_dir, S_IRUGO, fan_dir_show, NULL, FAN_0); +static SENSOR_DEVICE_ATTR(fan1_dir, S_IRUGO, fan_dir_show, NULL, FAN_1); +static SENSOR_DEVICE_ATTR(fan2_dir, S_IRUGO, fan_dir_show, NULL, FAN_2); +static SENSOR_DEVICE_ATTR(fan0_prs, S_IRUGO, fan_prs_show, NULL, FAN_0); +static SENSOR_DEVICE_ATTR(fan1_prs, S_IRUGO, fan_prs_show, NULL, FAN_1); +static SENSOR_DEVICE_ATTR(fan2_prs, S_IRUGO, fan_prs_show, NULL, FAN_2); +static SENSOR_DEVICE_ATTR(fan0_led, S_IRUGO | S_IWUSR, fani_led_show, fani_led_store, FAN_0); +static SENSOR_DEVICE_ATTR(fan1_led, S_IRUGO | S_IWUSR, fani_led_show, fani_led_store, FAN_1); +static SENSOR_DEVICE_ATTR(fan2_led, S_IRUGO | S_IWUSR, fani_led_show, fani_led_store, FAN_2); + +static struct attribute *e3224f_cpld_attrs[] = { + &dev_attr_sfp_txdis.attr, + &dev_attr_sfp_modprs.attr, + &dev_attr_sfp_rxlos.attr, + &dev_attr_sfp_txfault.attr, + &dev_attr_sfpplus_txdis.attr, + &dev_attr_sfpplus_modprs.attr, + &dev_attr_sfpplus_rxlos.attr, + &dev_attr_sfpplus_txfault.attr, + &dev_attr_qsfp_modprs.attr, + &dev_attr_qsfp_rst.attr, + &dev_attr_qsfp_lpmode.attr, + &dev_attr_reboot_cause.attr, + &dev_attr_power_reset.attr, + &sensor_dev_attr_fan0_dir.dev_attr.attr, + &sensor_dev_attr_fan1_dir.dev_attr.attr, + &sensor_dev_attr_fan2_dir.dev_attr.attr, + &sensor_dev_attr_fan0_prs.dev_attr.attr, + &sensor_dev_attr_fan1_prs.dev_attr.attr, + &sensor_dev_attr_fan2_prs.dev_attr.attr, + &sensor_dev_attr_fan0_led.dev_attr.attr, + &sensor_dev_attr_fan1_led.dev_attr.attr, + &sensor_dev_attr_fan2_led.dev_attr.attr, + &dev_attr_psu0_prs.attr, + &dev_attr_psu1_prs.attr, + &dev_attr_psu0_status.attr, + &dev_attr_psu1_status.attr, + &dev_attr_system_led.attr, + &dev_attr_watchdog.attr, + &dev_attr_locator_led.attr, + &dev_attr_power_led.attr, + &dev_attr_primary_led.attr, + &dev_attr_fan_led.attr, + &dev_attr_power_good.attr, + &dev_attr_cpu_cpld_mjr_ver.attr, + &dev_attr_cpu_cpld_mnr_ver.attr, + &dev_attr_sys_cpld_mjr_ver.attr, + &dev_attr_sys_cpld_mnr_ver.attr, + &dev_attr_port_cpld_mjr_ver.attr, + &dev_attr_port_cpld_mnr_ver.attr, + NULL, +}; + +static struct attribute_group e3224f_cpld_attr_grp = { + .attrs = e3224f_cpld_attrs, +}; + +static int get_ismt_base_nr(void) +{ + struct i2c_adapter *ismt_adap; + static int ismt_base_nr = -1; + + if (ismt_base_nr != -1) { + return ismt_base_nr; + } + for (ismt_base_nr = 0; ismt_base_nr < 2; ismt_base_nr++) { + ismt_adap = i2c_get_adapter(ismt_base_nr); + if (!ismt_adap) { + printk(KERN_WARNING "iSMT adapter (%d) not found\n", ismt_base_nr); + return -ENODEV; + } + if (!strstr(ismt_adap->name, "iSMT adapter")) { + i2c_put_adapter(ismt_adap); + printk("I2C %d adapter is %s\n", ismt_base_nr, ismt_adap->name); + } else { + i2c_put_adapter(ismt_adap); + return ismt_base_nr; + } + } + return -ENODEV; +} + +static int get_port_mux_base_nr(void) +{ + struct i2c_adapter *mux_adap; + static int mux_base_nr = -1; + + if (mux_base_nr != -1) { + return mux_base_nr; + } + for (mux_base_nr = 0; mux_base_nr < 10; mux_base_nr++) { + mux_adap = i2c_get_adapter(mux_base_nr); + if (!mux_adap) { + printk(KERN_WARNING "I2C adapter (%d) not found\n", mux_base_nr); + continue; + } + if (!strstr(mux_adap->name, "mux (chan_id 0)")) { + i2c_put_adapter(mux_adap); + printk("I2C %d adapter is %s\n", mux_base_nr, mux_adap->name); + } else { + i2c_put_adapter(mux_adap); + return mux_base_nr; + } + } + return -ENODEV; +} + +static int __init cpld_probe(struct platform_device *pdev) +{ + struct cpld_platform_data *pdata; + struct i2c_adapter *parent; + int i, cpld_bus, port_cpld_bus; + int ret; + + pdata = pdev->dev.platform_data; + if (!pdata) { + dev_err(&pdev->dev, "Missing platform data\n"); + return -ENODEV; + } + + cpld_bus = get_ismt_base_nr(); + if (cpld_bus < 0) { + return -ENODEV; + } + parent = i2c_get_adapter(cpld_bus); + if (!parent) { + printk(KERN_WARNING "Parent adapter (%d) not found\n", cpld_bus); + return -ENODEV; + } + + for (i = 0; i < (CPLD_DEVICE_NUM - 1); i++) { // cpu and sys cpld + pdata[i].client = i2c_new_dummy_device(parent, pdata[i].reg_addr); + if (!pdata[i].client) { + printk(KERN_WARNING "Fail to create dummy i2c client for addr %d\n", pdata[i].reg_addr); + goto error; + } + } + + // PORT CPLD + port_cpld_bus = get_port_mux_base_nr(); + if (port_cpld_bus < 0) { + return -ENODEV; + } + parent = i2c_get_adapter(port_cpld_bus); + if (!parent) { + printk(KERN_WARNING "Parent adapter (port_cpld) not found\n"); + return -ENODEV; + } + else + { + printk (KERN_WARNING "Parent adapter (port_cpld) FOUND \n"); + } + pdata[port_cpld].client = i2c_new_dummy_device(parent, pdata[port_cpld].reg_addr); + if (!pdata[port_cpld].client) { + printk(KERN_WARNING "Fail to create dummy i2c client for addr %d\n", pdata[port_cpld].reg_addr); + goto error; + } + + ret = sysfs_create_group(&pdev->dev.kobj, &e3224f_cpld_attr_grp); + if (ret) + goto error; + + return 0; + +error: + i--; + for (; i >= 0; i--) { + if (pdata[i].client) { + i2c_unregister_device(pdata[i].client); + } + } + + i2c_put_adapter(parent); + + return -ENODEV; +} + +static int __exit cpld_remove(struct platform_device *pdev) +{ + int i; + struct i2c_adapter *parent = NULL; + struct cpld_platform_data *pdata = pdev->dev.platform_data; + + sysfs_remove_group(&pdev->dev.kobj, &e3224f_cpld_attr_grp); + + if (!pdata) { + dev_err(&pdev->dev, "Missing platform data\n"); + } else { + for (i = 0; i < CPLD_DEVICE_NUM; i++) { + if (pdata[i].client) { + if (!parent) { + parent = (pdata[i].client)->adapter; + } + i2c_unregister_device(pdata[i].client); + } + } + } + + i2c_put_adapter(parent); + + return 0; +} + +static struct platform_driver cpld_driver = { + .probe = cpld_probe, + .remove = __exit_p(cpld_remove), + .driver = { + .owner = THIS_MODULE, + .name = "dell-e3224f-cpld", + }, +}; + +static struct i2c_board_info sys_board_mux[] = { + { + I2C_BOARD_INFO("pca9548", 0x71) + } +}; + +static int __init dell_e3224f_platform_init(void) +{ + int ret = 0; + struct i2c_adapter *sys_i2c_adap; + struct i2c_client *mux_i2c_cli; + struct cpld_platform_data *cpld_pdata; + struct mux_platform_data *pdata; + int i, sys_i2c_bus; + + printk("dell_e3224f_platform module initialization\n"); + sys_i2c_bus = get_ismt_base_nr(); + if (sys_i2c_bus < 0) { + return -ENODEV; + } + + sys_i2c_adap = i2c_get_adapter(sys_i2c_bus); + mux_i2c_cli = i2c_new_client_device(sys_i2c_adap, sys_board_mux); + if (!mux_i2c_cli) + return PTR_ERR_OR_ZERO(mux_i2c_cli); + + ret = platform_driver_register(&cpld_driver); + if (ret) { + printk(KERN_WARNING "Fail to register cpld driver\n"); + goto error_cpld_driver; + } + + ret = platform_driver_register(&mux_driver); + if (ret) { + printk(KERN_WARNING "Fail to register mux driver\n"); + goto error_mux_driver; + } + + ret = platform_device_register(&e3224f_cpld); + if (ret) { + printk(KERN_WARNING "Fail to create cpld device\n"); + goto error_cpld; + } + + cpld_pdata = e3224f_cpld.dev.platform_data; + + for (i = 0; i < PF_MUX_DEVICES; i++) { + pdata = e3224f_mux[i].dev.platform_data; + pdata->cpld = cpld_pdata[sys_cpld].client; + ret = platform_device_register(&e3224f_mux[i]); + if (ret) { + printk(KERN_WARNING "fail to create mux %d\n", i); + goto error_mux; + } + } + ret = i2c_smbus_write_byte_data(cpld_pdata[sys_cpld].client, PHY_RESET_REG, RESET_ALL_PHY); + if (ret) + goto error_mux; + + /* To enable FAN set FAN_EN bit (Set bit 0 to 1) in SYS_MISC_CTRL: 0x0B by read modify write. */ + ret = i2c_smbus_read_byte_data(cpld_pdata[sys_cpld].client, SYS_MISC_CTRL_REG); + if (ret < 0) + goto error_mux; + ret = i2c_smbus_write_byte_data(cpld_pdata[sys_cpld].client, SYS_MISC_CTRL_REG, (u8)(ret | 0x01)); + if (ret) + goto error_mux; + + return 0; + +error_mux: + i--; + for (; i >= 0; i--) { + platform_device_unregister(&e3224f_mux[i]); + } + platform_device_unregister(&e3224f_cpld); +error_cpld: + platform_driver_unregister(&mux_driver); +error_mux_driver: + platform_driver_unregister(&cpld_driver); +error_cpld_driver: + return ret; +} + +static void __exit dell_e3224f_platform_exit(void) +{ + int i; + + for (i = 0; i < PF_MUX_DEVICES; i++) + platform_device_unregister(&e3224f_mux[i]); + platform_device_unregister(&e3224f_cpld); + platform_driver_unregister(&cpld_driver); + platform_driver_unregister(&mux_driver); +} + +module_init(dell_e3224f_platform_init); +module_exit(dell_e3224f_platform_exit); + +MODULE_DESCRIPTION("DELL E3224F Platform Support"); +MODULE_AUTHOR("Dhanakumar Subramanian "); +MODULE_LICENSE("GPL"); diff --git a/platform/broadcom/sonic-platform-modules-dell/e3224f/modules/emc2305.c b/platform/broadcom/sonic-platform-modules-dell/e3224f/modules/emc2305.c new file mode 100644 index 000000000000..7a3f3351059e --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-dell/e3224f/modules/emc2305.c @@ -0,0 +1,1203 @@ +/* + * emc2305.c - hwmon driver for SMSC EMC2305 fan controller + * (C) Copyright 2013 + * Reinhard Pfau, Guntermann & Drunck GmbH + * + * Based on emc2103 driver by SMSC. + * + * Datasheet available at: + * http://www.smsc.com/Downloads/SMSC/Downloads_Public/Data_Sheets/2305.pdf + * + * Also supports the EMC2303 fan controller which has the same functionality + * and register layout as EMC2305, but supports only up to 3 fans instead of 5. + * + * Also supports EMC2302 (up to 2 fans) and EMC2301 (1 fan) fan controller. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Addresses scanned. + * Listed in the same order as they appear in the EMC2305, EMC2303 data sheets. + * + * Note: these are the I2C adresses which are possible for EMC2305 and EMC2303 + * chips. + * The EMC2302 supports only 0x2e (EMC2302-1) and 0x2f (EMC2302-2). + * The EMC2301 supports only 0x2f. + */ +static const unsigned short i2c_adresses[] = { + 0x2E, + 0x2F, + 0x2C, + 0x2D, + 0x4C, + 0x4D, + I2C_CLIENT_END +}; + +/* + * global registers + */ +enum { + REG_CONFIGURATION = 0x20, + REG_FAN_STATUS = 0x24, + REG_FAN_STALL_STATUS = 0x25, + REG_FAN_SPIN_STATUS = 0x26, + REG_DRIVE_FAIL_STATUS = 0x27, + REG_FAN_INTERRUPT_ENABLE = 0x29, + REG_PWM_POLARITY_CONFIG = 0x2a, + REG_PWM_OUTPUT_CONFIG = 0x2b, + REG_PWM_BASE_FREQ_1 = 0x2c, + REG_PWM_BASE_FREQ_2 = 0x2d, + REG_SOFTWARE_LOCK = 0xef, + REG_PRODUCT_FEATURES = 0xfc, + REG_PRODUCT_ID = 0xfd, + REG_MANUFACTURER_ID = 0xfe, + REG_REVISION = 0xff +}; + +/* + * fan specific registers + */ +enum { + REG_FAN_SETTING = 0x30, + REG_PWM_DIVIDE = 0x31, + REG_FAN_CONFIGURATION_1 = 0x32, + REG_FAN_CONFIGURATION_2 = 0x33, + REG_GAIN = 0x35, + REG_FAN_SPIN_UP_CONFIG = 0x36, + REG_FAN_MAX_STEP = 0x37, + REG_FAN_MINIMUM_DRIVE = 0x38, + REG_FAN_VALID_TACH_COUNT = 0x39, + REG_FAN_DRIVE_FAIL_BAND_LOW = 0x3a, + REG_FAN_DRIVE_FAIL_BAND_HIGH = 0x3b, + REG_TACH_TARGET_LOW = 0x3c, + REG_TACH_TARGET_HIGH = 0x3d, + REG_TACH_READ_HIGH = 0x3e, + REG_TACH_READ_LOW = 0x3f, +}; + +#define SEL_FAN(fan, reg) (reg + fan * 0x10) + +/* + * Factor by equations [2] and [3] from data sheet; valid for fans where the + * number of edges equals (poles * 2 + 1). + */ + +#define EMC2305_TACH_FREQ 32768 /* 32.768KHz */ +#define EMC2305_RPM_CONST_VAL 60 + +#define EMC2305_FAN_CONFIG_RANGE_MASK 0x60 +#define TACH_READING_DEFAULT_VAL 0xFFF8 +#define EMC2305_PERCENT_VAL 100 +#define EMC2305_FAN_SETTING_MAX_VAL 0xff +#define EMC2305_FAN_WATCHDOG_STATUS_MASK 0x80 + +#define FAN_MAX_RPM_SPEED 28600 +#define TACH_VALUE_SHIFT_BITS 3 +#define SPEED_PWM_LEN_STRING 7 + +struct emc2305_fan_data { + bool enabled; + bool valid; + unsigned long last_updated; + bool rpm_control; + uint8_t multiplier; + uint8_t poles; + uint16_t target; + uint16_t tach; + uint16_t rpm_factor; + uint8_t pwm; + uint8_t ranges; + uint8_t edges; +}; + +struct emc2305_data { + struct device *hwmon_dev; + struct mutex update_lock; + int fans; + struct emc2305_fan_data fan[5]; +}; + +/* Fault status registers */ +static const uint8_t emc2305_fault_status_reg[] = { REG_FAN_STATUS, + REG_FAN_STALL_STATUS, + REG_FAN_SPIN_STATUS, + REG_DRIVE_FAIL_STATUS }; + +/* + * @brief Convert speed percentage value to volt. + * @param percent[in] - RPM speed in percent + * Return - corresponding voltage value. + */ +static uint8_t emc2305_speed_percent_to_drv_volt_get(uint8_t percent) +{ + return ((percent * EMC2305_FAN_SETTING_MAX_VAL) / EMC2305_PERCENT_VAL); +} + +/* + * @brief Convert RPM to speed percentage. + * @param max_speed[in] - Max Fan speed. + * @param rpm[in] - RPM value. + * Return - corresponding speed_percent value. + */ +static uint8_t emc2305_rpm_to_speed_percent_get(uint32_t max_speed, long rpm) +{ + return ((rpm * EMC2305_PERCENT_VAL) / max_speed); +} + +/** + * @brief This function calculates the tach count based on the passed parameters. + * @param[in] fan_data - The fan details of the fan + * @param[in] rpm - The speed of the fan in RPM + * @returns tach value in tach counts + */ +uint16_t calculate_tach_count_emc23xx(struct emc2305_fan_data *fan_data, uint32_t rpm) +{ + uint16_t tachval = 0; + + if ((rpm == 0) || (fan_data->poles == 0)) { + return 0; + } + tachval = (((fan_data->edges - 1) * EMC2305_TACH_FREQ * EMC2305_RPM_CONST_VAL * fan_data->multiplier) / + (fan_data->poles * rpm)); + tachval = tachval << TACH_VALUE_SHIFT_BITS; + + return tachval; +} + + +/** + * @brief This function calculates the fan rpm based on the passed parameters. + * @param[in] fan - fan details + * @param[in] tachval - The tach counts of the fan + * @returns speed of the fan in RPM + */ +uint32_t calculate_rpm_emc23xx(struct emc2305_fan_data *fan, uint16_t tachval) +{ + uint32_t speed = 0; + + if ((tachval == 0) || (fan->poles == 0)) { + return 0; + } + + speed = (((fan->edges - 1) * EMC2305_TACH_FREQ * fan->multiplier * EMC2305_RPM_CONST_VAL) + / (tachval * fan->poles)); + + return speed; +} + +static int read_u8_from_i2c(struct i2c_client *client, uint8_t i2c_reg, uint8_t *output) +{ + int status = i2c_smbus_read_byte_data(client, i2c_reg); + if (status < 0) { + dev_warn(&client->dev, "reg 0x%02x, err %d\n", + i2c_reg, status); + } else { + *output = status; + } + return status; +} + +/* Clear the fan fault status in the EMC2305 Controller. + */ +static void emc2305_clear_fan_fault(struct i2c_client *client) +{ + uint8_t buf = 0, index = 0; + int rc = 0; + + for (index = 0; index < sizeof(emc2305_fault_status_reg); index++) { + /* All the status register are Read-On-Clear */ + rc = read_u8_from_i2c(client, emc2305_fault_status_reg[index], &buf); + if (rc < 0) { + return; + } + } +} + +static void read_fan_from_i2c(struct i2c_client *client, uint16_t *output, + uint8_t hi_addr, uint8_t lo_addr) +{ + uint8_t high_byte = 0, lo_byte = 0; + + if (read_u8_from_i2c (client, hi_addr, &high_byte) < 0) + return; + + if (read_u8_from_i2c (client, lo_addr, &lo_byte) < 0) + return; + + *output = (((uint16_t) high_byte << 8) | (lo_byte)); +} + +static void write_fan_target_to_i2c(struct i2c_client *client, int fan, + uint32_t rpm) +{ + struct emc2305_data *data = i2c_get_clientdata (client); + struct emc2305_fan_data *fan_data = &data->fan[fan]; + const uint8_t lo_reg = SEL_FAN (fan, REG_TACH_TARGET_LOW); + const uint8_t hi_reg = SEL_FAN (fan, REG_TACH_TARGET_HIGH); + uint16_t tachval = 0; + uint8_t tach[2] = { 0, 0 }; + + // The Tach Target are in registers 3c/3d, 4c/4d, 5c/5d, 6c/6d & 7c/7d + tachval = calculate_tach_count_emc23xx (fan_data, rpm); + tach[1] = (tachval & 0xff00) >> 8; // High Byte + tach[0] = (tachval & 0xff); // Low Byte + + i2c_smbus_write_byte_data (client, lo_reg, tach[0]); + i2c_smbus_write_byte_data (client, hi_reg, tach[1]); +} + +static void read_fan_config_from_i2c(struct i2c_client *client, int fan) + +{ + struct emc2305_data *data = i2c_get_clientdata(client); + uint8_t conf = 0; + + if (read_u8_from_i2c(client, SEL_FAN(fan, REG_FAN_CONFIGURATION_1), + &conf) < 0) { + return; + } + data->fan[fan].rpm_control = (conf & 0x80) != 0; + data->fan[fan].ranges = ((conf & EMC2305_FAN_CONFIG_RANGE_MASK) >> 5); + data->fan[fan].multiplier = 1 << (data->fan[fan].ranges); + data->fan[fan].poles = ((conf & 0x18) >> 3) + 1; + data->fan[fan].edges = (data->fan[fan].poles * 2) + 1; +} + +static void read_fan_setting(struct i2c_client *client, int fan) +{ + struct emc2305_data *data = i2c_get_clientdata(client); + uint8_t setting = 0; + + if (read_u8_from_i2c(client, SEL_FAN(fan, REG_FAN_SETTING), + &setting) < 0) + return; + + data->fan[fan].pwm = setting; +} + +static void read_fan_data(struct i2c_client *client, int fan_idx) +{ + struct emc2305_data *data = i2c_get_clientdata(client); + + read_fan_from_i2c(client, &data->fan[fan_idx].target, + SEL_FAN(fan_idx, REG_TACH_TARGET_HIGH), + SEL_FAN(fan_idx, REG_TACH_TARGET_LOW)); + + read_fan_from_i2c(client, &data->fan[fan_idx].tach, + SEL_FAN(fan_idx, REG_TACH_READ_HIGH), + SEL_FAN(fan_idx, REG_TACH_READ_LOW)); +} + + static struct emc2305_fan_data * +emc2305_update_fan(struct i2c_client *client, int fan_idx) +{ + struct emc2305_data *data = i2c_get_clientdata(client); + struct emc2305_fan_data *fan_data = &data->fan[fan_idx]; + + mutex_lock(&data->update_lock); + + if (time_after(jiffies, fan_data->last_updated + HZ + HZ / 2) + || !fan_data->valid) { + read_fan_config_from_i2c(client, fan_idx); + read_fan_data(client, fan_idx); + read_fan_setting(client, fan_idx); + fan_data->valid = true; + fan_data->last_updated = jiffies; + } + + mutex_unlock(&data->update_lock); + return fan_data; +} + + static struct emc2305_fan_data * +emc2305_update_device_fan(struct device *dev, struct device_attribute *da) +{ + struct i2c_client *client = to_i2c_client(dev); + int fan_idx = to_sensor_dev_attr(da)->index; + + return emc2305_update_fan(client, fan_idx); +} + +static void read_fan_status(struct device *dev, struct device_attribute *da, bool *fault) +{ + struct i2c_client *client = to_i2c_client(dev); + int fan_idx = to_sensor_dev_attr(da)->index; + uint8_t reg = 0, index = 0; + int rc = 0; + *fault = false; + for (index = 1; index < sizeof(emc2305_fault_status_reg); index++) { + rc = read_u8_from_i2c(client, emc2305_fault_status_reg[index], ®); + if (rc < 0) { + return; + } + *fault = (reg & (1 << fan_idx)) ? true : false; + if (*fault == true) + return; + } + rc = read_u8_from_i2c(client, emc2305_fault_status_reg[0], ®); + if (rc < 0) { + return; + } + *fault = (reg & EMC2305_FAN_WATCHDOG_STATUS_MASK) ? true : false; + return; +} + +/* + * set/ config functions + */ + +/* + * Note: we also update the fan target here, because its value is + * determined in part by the fan clock divider. This follows the principle + * of least surprise; the user doesn't expect the fan target to change just + * because the divider changed. + */ + static int +emc2305_set_fan_div(struct i2c_client *client, int fan_idx, long new_div) +{ + struct emc2305_data *data = i2c_get_clientdata(client); + struct emc2305_fan_data *fan = emc2305_update_fan(client, fan_idx); + const uint8_t reg_conf1 = SEL_FAN(fan_idx, REG_FAN_CONFIGURATION_1); + int new_range_bits, old_div = 8 / fan->multiplier; + int status = 0; + + if (new_div == old_div) /* No change */ + return 0; + + switch (new_div) { + case 1: + new_range_bits = 3; + break; + case 2: + new_range_bits = 2; + break; + case 4: + new_range_bits = 1; + break; + case 8: + new_range_bits = 0; + break; + default: + return -EINVAL; + } + + mutex_lock(&data->update_lock); + + status = i2c_smbus_read_byte_data(client, reg_conf1); + if (status < 0) { + dev_dbg(&client->dev, "reg 0x%02x, err %d\n", + reg_conf1, status); + status = -EIO; + goto exit_unlock; + } + status &= 0x9F; + status |= (new_range_bits << 5); + status = i2c_smbus_write_byte_data(client, reg_conf1, status); + if (status < 0) { + status = -EIO; + goto exit_invalidate; + } + + fan->multiplier = 8 / new_div; + + /* update fan target if high byte is not disabled */ + if ((fan->target & 0x7fff) != 0x7fff) { + uint16_t new_target = (fan->target * old_div) / new_div; + fan->target = min_t(uint16_t, new_target, FAN_MAX_RPM_SPEED); + write_fan_target_to_i2c(client, fan_idx, fan->target); + } + +exit_invalidate: + /* invalidate fan data to force re-read from hardware */ + fan->valid = false; +exit_unlock: + mutex_unlock(&data->update_lock); + return status; +} + + static int +emc2305_set_fan_target(struct i2c_client *client, int fan_idx, long rpm_target) +{ + struct emc2305_data *data = i2c_get_clientdata (client); + struct emc2305_fan_data *fan = emc2305_update_fan (client, fan_idx); + const uint8_t reg_fan_conf1 = SEL_FAN (fan_idx, REG_FAN_CONFIGURATION_1); + int status = 0; + uint8_t conf_reg = 0, speed_percent = 0, reg = 0, setting = 0; + + /* + * Datasheet states 16000 as maximum RPM target + * (table 2.2 and section 4.3) + */ + if (rpm_target < 0) { + return -EINVAL; + } + + mutex_lock (&data->update_lock); + + if ((rpm_target == 0) || (rpm_target > FAN_MAX_RPM_SPEED)) { + rpm_target = FAN_MAX_RPM_SPEED; + } + + if (fan->rpm_control) { + /* RPM mode */ + write_fan_target_to_i2c (client, fan_idx, (uint16_t) rpm_target); + /* Set RPM mode */ + status = read_u8_from_i2c (client, reg_fan_conf1, &conf_reg); + if (status < 0) { + status = -EIO; + } + + fan->rpm_control = true; + conf_reg |= 0x80; + + status = i2c_smbus_write_byte_data (client, reg_fan_conf1, conf_reg); + if (status < 0) { + status = -EIO; + } + + } else { + /* Direct Method */ + /* Set the fan speed */ + speed_percent = emc2305_rpm_to_speed_percent_get (FAN_MAX_RPM_SPEED, rpm_target); + setting = emc2305_speed_percent_to_drv_volt_get (speed_percent); + reg = SEL_FAN (fan_idx, REG_FAN_SETTING); + i2c_smbus_write_byte_data (client, reg, setting); + } + + mutex_unlock (&data->update_lock); + return status; +} + + static int +emc2305_set_pwm_enable(struct i2c_client *client, int fan_idx, long enable) +{ + struct emc2305_data *data = i2c_get_clientdata(client); + struct emc2305_fan_data *fan = emc2305_update_fan(client, fan_idx); + const uint8_t reg_fan_conf1 = SEL_FAN(fan_idx, REG_FAN_CONFIGURATION_1); + int status = 0; + uint8_t conf_reg; + + mutex_lock(&data->update_lock); + switch (enable) { + case 0: + fan->rpm_control = false; + break; + case 3: + fan->rpm_control = true; + break; + default: + status = -EINVAL; + goto exit_unlock; + } + + status = read_u8_from_i2c(client, reg_fan_conf1, &conf_reg); + if (status < 0) { + status = -EIO; + goto exit_unlock; + } + + if (fan->rpm_control) + conf_reg |= 0x80; + else + conf_reg &= ~0x80; + + status = i2c_smbus_write_byte_data(client, reg_fan_conf1, conf_reg); + if (status < 0) + status = -EIO; + +exit_unlock: + mutex_unlock(&data->update_lock); + return status; +} + + static int +emc2305_set_pwm(struct i2c_client *client, int fan_idx, long pwm) +{ + struct emc2305_data *data = i2c_get_clientdata(client); + struct emc2305_fan_data *fan = emc2305_update_fan(client, fan_idx); + const uint8_t reg_fan_setting = SEL_FAN(fan_idx, REG_FAN_SETTING); + int status = 0; + + /* + * Datasheet states 255 as maximum PWM + * (section 5.7) + */ + if ((pwm < 0) || (pwm > 255)) { + return -EINVAL; + } + + fan->pwm = pwm; + + mutex_lock(&data->update_lock); + + status = i2c_smbus_write_byte_data(client, reg_fan_setting, fan->pwm); + + mutex_unlock(&data->update_lock); + return status; +} + + static ssize_t +read_fan_input_target(struct device *dev, struct device_attribute *da, char *buf) +{ + struct i2c_client *client = to_i2c_client(dev); + struct emc2305_data *data = i2c_get_clientdata(client); + struct emc2305_fan_data *fan = emc2305_update_device_fan(dev, da); + int fan_idx = to_sensor_dev_attr(da)->index; + uint32_t speed = 0; + uint16_t tach_fanstop_mask = 0, fanstop = 0, tachval =0; + uint8_t index = 0, conf = 0, value = 0, range = 0; + + mutex_lock(&data->update_lock); + read_fan_from_i2c(client, &tachval, + SEL_FAN(fan_idx, REG_TACH_READ_HIGH), + SEL_FAN(fan_idx, REG_TACH_READ_LOW)); + + // Get Fan Configuration value + conf = SEL_FAN (fan_idx, REG_FAN_CONFIGURATION_1); + value = i2c_smbus_read_byte_data (client, conf); + + // Get Range from Configuration value + range = ((value & EMC2305_FAN_CONFIG_RANGE_MASK) >> 5); + + switch (range) { + case 0: + fanstop = (uint16_t)0xFFF8; + break; + case 1: + fanstop = (uint16_t)0xFFF0; + break; + case 2: + fanstop = (uint16_t)0xFFE0; + break; + case 3: + fanstop = (uint16_t)0xFFC0; + break; + default: + //shouldn't reach here, as the mask 0x60 + return 0; + } + + // TACH_READING_DEFAULT_VAL: 0xFFF8, tach_fanstop_mask: 0x7 + tach_fanstop_mask = (uint16_t)~TACH_READING_DEFAULT_VAL; + + for (index = 1; index <= range; index++) { + tach_fanstop_mask = (tach_fanstop_mask << 1); + tach_fanstop_mask |= 0x1; + } + + // Mask off the lower bits which are indeterminate + tachval &= ~tach_fanstop_mask; + tachval = tachval >> TACH_VALUE_SHIFT_BITS; + + /* Disable the fan speed in case of fanstop value */ + if (tachval == fanstop) { + speed = 0; + } else { + speed = calculate_rpm_emc23xx(fan, tachval); + } + + mutex_unlock(&data->update_lock); + return snprintf(buf, SPEED_PWM_LEN_STRING, "%d\n", speed); +} + +/* + * sysfs callback functions + * + * Note: + * Naming of the funcs is modelled after the naming scheme described in + * Documentation/hwmon/sysfs-interface: + * + * For a sysfs file _ the functions are named like this: + * the show function: show__ + * the store function: set__ + * For read only (RO) attributes of course only the show func is required. + * + * This convention allows us to define the sysfs attributes by using macros. + */ + static ssize_t +show_fan_input(struct device *dev, struct device_attribute *da, char *buf) +{ + struct i2c_client *client = to_i2c_client (dev); + int fan_idx = to_sensor_dev_attr (da)->index; + struct emc2305_data *data = i2c_get_clientdata (client); + struct emc2305_fan_data *fan = emc2305_update_fan (client, fan_idx); + uint8_t setting = 0, speed_percent = 0; + uint32_t speed = 0; + + if (fan->rpm_control) { + return read_fan_input_target (dev, da, buf); + } else { + if (read_u8_from_i2c(client, SEL_FAN (fan_idx, REG_FAN_SETTING), &setting) < 0) { + return 0; + } + speed_percent = (setting * EMC2305_PERCENT_VAL) / (EMC2305_FAN_SETTING_MAX_VAL); + speed = (FAN_MAX_RPM_SPEED * speed_percent) / EMC2305_PERCENT_VAL; + return snprintf (buf, SPEED_PWM_LEN_STRING, "%d\n", speed); + } + +} + + static ssize_t +show_fan_fault(struct device *dev, struct device_attribute *da, char *buf) +{ + struct emc2305_fan_data *fan = emc2305_update_device_fan(dev, da); + bool fault; + read_fan_status(dev, da, &fault); + return snprintf(buf, SPEED_PWM_LEN_STRING, "%d\n", fault ? 1 : 0); +} + + static ssize_t +show_fan_div(struct device *dev, struct device_attribute *da, char *buf) +{ + struct emc2305_fan_data *fan = emc2305_update_device_fan(dev, da); + int fan_div = 8 / fan->multiplier; + return snprintf(buf, SPEED_PWM_LEN_STRING, "%d\n", fan_div); +} + + static ssize_t +set_fan_div(struct device *dev, struct device_attribute *da, + const char *buf, size_t count) +{ + struct i2c_client *client = to_i2c_client(dev); + int fan_idx = to_sensor_dev_attr(da)->index; + long new_div; + int status; + + status = kstrtol(buf, 10, &new_div); + if (status < 0) { + return -EINVAL; + } + + status = emc2305_set_fan_div(client, fan_idx, new_div); + if (status < 0) + return status; + + return count; +} + + static ssize_t +show_fan_target(struct device *dev, struct device_attribute *da, char *buf) +{ + struct i2c_client *client = to_i2c_client (dev); + int fan_idx = to_sensor_dev_attr (da)->index; + struct emc2305_data *data = i2c_get_clientdata (client); + struct emc2305_fan_data *fan = emc2305_update_fan (client, fan_idx); + uint8_t setting = 0, speed_percent = 0; + uint32_t speed = 0; + + if (fan->rpm_control) { + /* RPM mode */ + return read_fan_input_target (dev, da, buf); + } else { + /* Direct Method */ + if (read_u8_from_i2c(client, SEL_FAN (fan_idx, REG_FAN_SETTING), &setting) < 0) { + return 0; + } + speed_percent = (setting * EMC2305_PERCENT_VAL) / (EMC2305_FAN_SETTING_MAX_VAL); + speed = (FAN_MAX_RPM_SPEED * speed_percent) / EMC2305_PERCENT_VAL; + return snprintf (buf, SPEED_PWM_LEN_STRING, "%d\n", speed); + } +} + +static ssize_t set_fan_target(struct device *dev, struct device_attribute *da, + const char *buf, size_t count) +{ + struct i2c_client *client = to_i2c_client(dev); + int fan_idx = to_sensor_dev_attr(da)->index; + long rpm_target = 0; + int status = 0; + + status = kstrtol(buf, 10, &rpm_target); + if (status < 0) { + return -EINVAL; + } + + status = emc2305_set_fan_target(client, fan_idx, rpm_target); + if (status < 0) + return status; + + return count; +} + + static ssize_t +show_pwm_enable(struct device *dev, struct device_attribute *da, char *buf) +{ + struct emc2305_fan_data *fan = emc2305_update_device_fan(dev, da); + return snprintf(buf, SPEED_PWM_LEN_STRING, "%d\n", fan->rpm_control ? 3 : 0); +} + +static ssize_t set_pwm_enable(struct device *dev, struct device_attribute *da, + const char *buf, size_t count) +{ + struct i2c_client *client = to_i2c_client(dev); + int fan_idx = to_sensor_dev_attr(da)->index; + long new_value; + int status; + + status = kstrtol(buf, 10, &new_value); + if (status < 0) { + return -EINVAL; + } + status = emc2305_set_pwm_enable(client, fan_idx, new_value); + return count; +} + +static ssize_t show_pwm(struct device *dev, struct device_attribute *da, + char *buf) +{ + struct emc2305_fan_data *fan = emc2305_update_device_fan(dev, da); + return snprintf(buf, SPEED_PWM_LEN_STRING, "%d\n", fan->pwm); +} + +static ssize_t set_pwm(struct device *dev, struct device_attribute *da, + const char *buf, size_t count) +{ + struct i2c_client *client = to_i2c_client(dev); + int fan_idx = to_sensor_dev_attr(da)->index; + unsigned long val = 0; + int ret = 0; + int status = 0; + + ret = kstrtoul(buf, 10, &val); + if (ret) + return ret; + if (val > 255) { + return -EINVAL; + } + + status = emc2305_set_pwm(client, fan_idx, val); + return count; +} + +/* define a read only attribute */ +#define EMC2305_ATTR_RO(_type, _item, _num) \ + SENSOR_ATTR(_type ## _num ## _ ## _item, S_IRUGO, \ + show_## _type ## _ ## _item, NULL, _num - 1) + +/* define a read/write attribute */ +#define EMC2305_ATTR_RW(_type, _item, _num) \ + SENSOR_ATTR(_type ## _num ## _ ## _item, S_IRUGO | S_IWUSR, \ + show_## _type ##_ ## _item, \ + set_## _type ## _ ## _item, _num - 1) + +/* + * TODO: Ugly hack, but temporary as this whole logic needs + * to be rewritten as per standard HWMON sysfs registration + */ + +/* define a read/write attribute */ +#define EMC2305_ATTR_RW2(_type, _num) \ + SENSOR_ATTR(_type ## _num, S_IRUGO | S_IWUSR, \ + show_## _type, set_## _type, _num - 1) + +/* defines the attributes for a single fan */ +#define EMC2305_DEFINE_FAN_ATTRS(_num) \ + static const \ +struct sensor_device_attribute emc2305_attr_fan ## _num[] = { \ + EMC2305_ATTR_RO(fan, input, _num), \ + EMC2305_ATTR_RO(fan, fault, _num), \ + EMC2305_ATTR_RW(fan, div, _num), \ + EMC2305_ATTR_RW(fan, target, _num), \ + EMC2305_ATTR_RW(pwm, enable, _num), \ + EMC2305_ATTR_RW2(pwm, _num) \ +} + +#define EMC2305_NUM_FAN_ATTRS ARRAY_SIZE(emc2305_attr_fan1) + +/* common attributes for EMC2303 and EMC2305 */ +static const struct sensor_device_attribute emc2305_attr_common[] = { +}; + +/* fan attributes for the single fans */ +EMC2305_DEFINE_FAN_ATTRS(1); +EMC2305_DEFINE_FAN_ATTRS(2); +EMC2305_DEFINE_FAN_ATTRS(3); +EMC2305_DEFINE_FAN_ATTRS(4); +EMC2305_DEFINE_FAN_ATTRS(5); +EMC2305_DEFINE_FAN_ATTRS(6); + +/* fan attributes */ +static const struct sensor_device_attribute *emc2305_fan_attrs[] = { + emc2305_attr_fan1, + emc2305_attr_fan2, + emc2305_attr_fan3, + emc2305_attr_fan4, + emc2305_attr_fan5, +}; + +/* + * driver interface + */ + +static int emc2305_remove(struct i2c_client *client) +{ + struct emc2305_data *data = i2c_get_clientdata(client); + int fan_idx, i; + + hwmon_device_unregister(data->hwmon_dev); + + for (fan_idx = 0; fan_idx < data->fans; ++fan_idx) + for (i = 0; i < EMC2305_NUM_FAN_ATTRS; ++i) + device_remove_file( + &client->dev, + &emc2305_fan_attrs[fan_idx][i].dev_attr); + + for (i = 0; i < ARRAY_SIZE(emc2305_attr_common); ++i) + device_remove_file(&client->dev, + &emc2305_attr_common[i].dev_attr); + + kfree(data); + return 0; +} + + +#ifdef CONFIG_OF +/* + * device tree support + */ + +struct of_fan_attribute { + const char *name; + int (*set)(struct i2c_client*, int, long); +}; + +struct of_fan_attribute of_fan_attributes[] = { + {"fan-div", emc2305_set_fan_div}, + {"fan-target", emc2305_set_fan_target}, + {"pwm-enable", emc2305_set_pwm_enable}, + {NULL, NULL} +}; + +static int emc2305_config_of(struct i2c_client *client) +{ + struct emc2305_data *data = i2c_get_clientdata(client); + struct device_node *node; + unsigned int fan_idx; + + if (!client->dev.of_node) + { + return -EINVAL; + } + if (!of_get_next_child(client->dev.of_node, NULL)) + return 0; + + for (fan_idx = 0; fan_idx < data->fans; ++fan_idx) + data->fan[fan_idx].enabled = false; + + for_each_child_of_node(client->dev.of_node, node) { + const __be32 *property; + int len; + struct of_fan_attribute *attr; + + property = of_get_property(node, "reg", &len); + if (!property || len != sizeof(int)) { + dev_err(&client->dev, "invalid reg on %s\n", + node->full_name); + continue; + } + + fan_idx = be32_to_cpup(property); + if (fan_idx >= data->fans) { + dev_err(&client->dev, + "invalid fan index %d on %s\n", + fan_idx, node->full_name); + continue; + } + + data->fan[fan_idx].enabled = true; + + for (attr = of_fan_attributes; attr->name; ++attr) { + int status = 0; + long value; + property = of_get_property(node, attr->name, &len); + if (!property) + continue; + if (len != sizeof(int)) { + dev_err(&client->dev, "invalid %s on %s\n", + attr->name, node->full_name); + continue; + } + value = be32_to_cpup(property); + status = attr->set(client, fan_idx, value); + if (status == -EINVAL) { + dev_err(&client->dev, + "invalid value for %s on %s\n", + attr->name, node->full_name); + } + } + } + + return 0; +} + +#endif + +static void emc2305_device_init(struct i2c_client *client) +{ + int fan_index; + uint16_t rpm = 0; + uint8_t conf = 0; + uint8_t value = 0; + struct emc2305_data *data = i2c_get_clientdata (client); + + /* Clear status registers */ + emc2305_clear_fan_fault (client); + + conf = REG_PWM_OUTPUT_CONFIG; + value = 0x1f; + i2c_smbus_write_byte_data (client, conf, value); + + conf = REG_PWM_BASE_FREQ_1; + value = 0x0f; + i2c_smbus_write_byte_data (client, conf, value); + + conf = REG_PWM_BASE_FREQ_2; + value = 0x3f; + i2c_smbus_write_byte_data (client, conf, value); + + + for (fan_index = 0; fan_index < data->fans; ++fan_index) { + conf = SEL_FAN (fan_index, REG_FAN_CONFIGURATION_1); + value = 0x4b; + i2c_smbus_write_byte_data (client, conf, value); + + conf = SEL_FAN (fan_index, REG_FAN_MAX_STEP); + value = 0x01; + i2c_smbus_write_byte_data (client, conf, value); + + conf = SEL_FAN (fan_index, REG_FAN_VALID_TACH_COUNT); + value = 0xfe; + i2c_smbus_write_byte_data (client, conf, value); + + /* Set default speed (12000 RPM) */ + rpm = 12000; + write_fan_target_to_i2c (client, fan_index, rpm); + + conf = SEL_FAN(fan_index, REG_FAN_SETTING); + value = 0x0; + i2c_smbus_write_byte_data (client, conf, value); + + conf = SEL_FAN (fan_index, REG_FAN_MINIMUM_DRIVE); + value = 0x01; + i2c_smbus_write_byte_data (client, conf, value); + + conf = SEL_FAN(fan_index, REG_FAN_SETTING); + value = 0x0; + i2c_smbus_write_byte_data (client, conf, value); + + /* Change to RPM Mode */ + conf = SEL_FAN (fan_index, REG_FAN_CONFIGURATION_1); + value = i2c_smbus_read_byte_data (client, conf); + value |= 0x80; + i2c_smbus_write_byte_data (client, conf, value); + + conf = SEL_FAN (fan_index, REG_PWM_DIVIDE); + value = 0x0; + i2c_smbus_write_byte_data (client, conf, value); + + conf = SEL_FAN(fan_index, REG_FAN_SETTING); + value = 0x0; + i2c_smbus_write_byte_data (client, conf, value); + + conf = SEL_FAN (fan_index, REG_FAN_CONFIGURATION_1); + value = 0x4b; + i2c_smbus_write_byte_data (client, conf, value); + } + +} + +static void emc2305_get_config(struct i2c_client *client) +{ + int i; + struct emc2305_data *data = i2c_get_clientdata(client); + + for (i = 0; i < data->fans; ++i) { + data->fan[i].enabled = true; + emc2305_update_fan(client, i); + } + +#ifdef CONFIG_OF + emc2305_config_of(client); +#endif + +} + + static int +emc2305_probe(struct i2c_client *client, const struct i2c_device_id *id) +{ + struct emc2305_data *data; + int status; + int i; + int fan_idx; + + if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) + return -EIO; + + data = kzalloc(sizeof(struct emc2305_data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + i2c_set_clientdata(client, data); + mutex_init(&data->update_lock); + + status = i2c_smbus_read_byte_data(client, REG_PRODUCT_ID); + switch (status) { + case 0x34: /* EMC2305 */ + data->fans = 5; + break; + case 0x35: /* EMC2303 */ + data->fans = 3; + break; + case 0x36: /* EMC2302 */ + data->fans = 2; + break; + case 0x37: /* EMC2301 */ + data->fans = 1; + break; + default: + if (status >= 0) { + + status = -EINVAL; + } + goto exit_free; + } + + /* initialise EMC2305 driver */ + emc2305_device_init(client); + + emc2305_get_config(client); + + for (i = 0; i < ARRAY_SIZE(emc2305_attr_common); ++i) { + status = device_create_file(&client->dev, + &emc2305_attr_common[i].dev_attr); + if (status) + goto exit_remove; + } + for (fan_idx = 0; fan_idx < data->fans; ++fan_idx) + for (i = 0; i < EMC2305_NUM_FAN_ATTRS; ++i) { + if (!data->fan[fan_idx].enabled) + continue; + status = device_create_file( + &client->dev, + &emc2305_fan_attrs[fan_idx][i].dev_attr); + if (status) + goto exit_remove_fans; + } + + data->hwmon_dev = hwmon_device_register(&client->dev); + if (IS_ERR(data->hwmon_dev)) { + status = PTR_ERR(data->hwmon_dev); + goto exit_remove_fans; + } + + dev_info(&client->dev, "%s: sensor '%s'\n", + dev_name(data->hwmon_dev), client->name); + + return 0; + +exit_remove_fans: + for (fan_idx = 0; fan_idx < data->fans; ++fan_idx) + for (i = 0; i < EMC2305_NUM_FAN_ATTRS; ++i) + device_remove_file( + &client->dev, + &emc2305_fan_attrs[fan_idx][i].dev_attr); + +exit_remove: + for (i = 0; i < ARRAY_SIZE(emc2305_attr_common); ++i) + device_remove_file(&client->dev, + &emc2305_attr_common[i].dev_attr); +exit_free: + kfree(data); + return status; +} + +static const struct i2c_device_id emc2305_id[] = { + { "emc2305", 0 }, + { "emc2303", 0 }, + { "emc2302", 0 }, + { "emc2301", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, emc2305_id); + +/* Return 0 if detection is successful, -ENODEV otherwise */ + static int +emc2305_detect(struct i2c_client *new_client, struct i2c_board_info *info) +{ + struct i2c_adapter *adapter = new_client->adapter; + int manufacturer, product; + + if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) + return -ENODEV; + + manufacturer = + i2c_smbus_read_byte_data(new_client, REG_MANUFACTURER_ID); + if (manufacturer != 0x5D) + return -ENODEV; + + product = i2c_smbus_read_byte_data(new_client, REG_PRODUCT_ID); + + switch (product) { + case 0x34: + strlcpy(info->type, "emc2305", I2C_NAME_SIZE); + break; + case 0x35: + strlcpy(info->type, "emc2303", I2C_NAME_SIZE); + break; + case 0x36: + strlcpy(info->type, "emc2302", I2C_NAME_SIZE); + break; + case 0x37: + strlcpy(info->type, "emc2301", I2C_NAME_SIZE); + break; + default: + return -ENODEV; + } + + return 0; +} + +static struct i2c_driver emc2305_driver = { + .class = I2C_CLASS_HWMON, + .driver = { + .name = "emc2305", + }, + .probe = emc2305_probe, + .remove = emc2305_remove, + .id_table = emc2305_id, + /* + .detect = emc2305_detect, + .address_list = i2c_adresses, + */ +}; + +module_i2c_driver(emc2305_driver); + +MODULE_AUTHOR("Reinhard Pfau "); +MODULE_DESCRIPTION("SMSC EMC2305 hwmon driver"); +MODULE_LICENSE("GPL"); diff --git a/platform/broadcom/sonic-platform-modules-dell/e3224f/modules/pmbus.h b/platform/broadcom/sonic-platform-modules-dell/e3224f/modules/pmbus.h new file mode 100644 index 000000000000..521baf6da49a --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-dell/e3224f/modules/pmbus.h @@ -0,0 +1,425 @@ +/* + * pmbus.h - Common defines and structures for PMBus devices + * + * Copyright (c) 2010, 2011 Ericsson AB. + * Copyright (c) 2012 Guenter Roeck + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef PMBUS_H +#define PMBUS_H + +#include +#include + +/* + * Registers + */ +enum pmbus_regs { + PMBUS_PAGE = 0x00, + PMBUS_OPERATION = 0x01, + PMBUS_ON_OFF_CONFIG = 0x02, + PMBUS_CLEAR_FAULTS = 0x03, + PMBUS_PHASE = 0x04, + + PMBUS_CAPABILITY = 0x19, + PMBUS_QUERY = 0x1A, + + PMBUS_VOUT_MODE = 0x20, + PMBUS_VOUT_COMMAND = 0x21, + PMBUS_VOUT_TRIM = 0x22, + PMBUS_VOUT_CAL_OFFSET = 0x23, + PMBUS_VOUT_MAX = 0x24, + PMBUS_VOUT_MARGIN_HIGH = 0x25, + PMBUS_VOUT_MARGIN_LOW = 0x26, + PMBUS_VOUT_TRANSITION_RATE = 0x27, + PMBUS_VOUT_DROOP = 0x28, + PMBUS_VOUT_SCALE_LOOP = 0x29, + PMBUS_VOUT_SCALE_MONITOR = 0x2A, + + PMBUS_COEFFICIENTS = 0x30, + PMBUS_POUT_MAX = 0x31, + + PMBUS_FAN_CONFIG_12 = 0x3A, + PMBUS_FAN_COMMAND_1 = 0x3B, + PMBUS_FAN_COMMAND_2 = 0x3C, + PMBUS_FAN_CONFIG_34 = 0x3D, + PMBUS_FAN_COMMAND_3 = 0x3E, + PMBUS_FAN_COMMAND_4 = 0x3F, + + PMBUS_VOUT_OV_FAULT_LIMIT = 0x40, + PMBUS_VOUT_OV_FAULT_RESPONSE = 0x41, + PMBUS_VOUT_OV_WARN_LIMIT = 0x42, + PMBUS_VOUT_UV_WARN_LIMIT = 0x43, + PMBUS_VOUT_UV_FAULT_LIMIT = 0x44, + PMBUS_VOUT_UV_FAULT_RESPONSE = 0x45, + PMBUS_IOUT_OC_FAULT_LIMIT = 0x46, + PMBUS_IOUT_OC_FAULT_RESPONSE = 0x47, + PMBUS_IOUT_OC_LV_FAULT_LIMIT = 0x48, + PMBUS_IOUT_OC_LV_FAULT_RESPONSE = 0x49, + PMBUS_IOUT_OC_WARN_LIMIT = 0x4A, + PMBUS_IOUT_UC_FAULT_LIMIT = 0x4B, + PMBUS_IOUT_UC_FAULT_RESPONSE = 0x4C, + + PMBUS_OT_FAULT_LIMIT = 0x4F, + PMBUS_OT_FAULT_RESPONSE = 0x50, + PMBUS_OT_WARN_LIMIT = 0x51, + PMBUS_UT_WARN_LIMIT = 0x52, + PMBUS_UT_FAULT_LIMIT = 0x53, + PMBUS_UT_FAULT_RESPONSE = 0x54, + PMBUS_VIN_OV_FAULT_LIMIT = 0x55, + PMBUS_VIN_OV_FAULT_RESPONSE = 0x56, + PMBUS_VIN_OV_WARN_LIMIT = 0x57, + PMBUS_VIN_UV_WARN_LIMIT = 0x58, + PMBUS_VIN_UV_FAULT_LIMIT = 0x59, + + PMBUS_IIN_OC_FAULT_LIMIT = 0x5B, + PMBUS_IIN_OC_WARN_LIMIT = 0x5D, + + PMBUS_POUT_OP_FAULT_LIMIT = 0x68, + PMBUS_POUT_OP_WARN_LIMIT = 0x6A, + PMBUS_PIN_OP_WARN_LIMIT = 0x6B, + + PMBUS_STATUS_BYTE = 0x78, + PMBUS_STATUS_WORD = 0x79, + PMBUS_STATUS_VOUT = 0x7A, + PMBUS_STATUS_IOUT = 0x7B, + PMBUS_STATUS_INPUT = 0x7C, + PMBUS_STATUS_TEMPERATURE = 0x7D, + PMBUS_STATUS_CML = 0x7E, + PMBUS_STATUS_OTHER = 0x7F, + PMBUS_STATUS_MFR_SPECIFIC = 0x80, + PMBUS_STATUS_FAN_12 = 0x81, + PMBUS_STATUS_FAN_34 = 0x82, + + PMBUS_READ_VIN = 0x88, + PMBUS_READ_IIN = 0x89, + PMBUS_READ_VCAP = 0x8A, + PMBUS_READ_VOUT = 0x8B, + PMBUS_READ_IOUT = 0x8C, + PMBUS_READ_TEMPERATURE_1 = 0x8D, + PMBUS_READ_TEMPERATURE_2 = 0x8E, + PMBUS_READ_TEMPERATURE_3 = 0x8F, + PMBUS_READ_FAN_SPEED_1 = 0x90, + PMBUS_READ_FAN_SPEED_2 = 0x91, + PMBUS_READ_FAN_SPEED_3 = 0x92, + PMBUS_READ_FAN_SPEED_4 = 0x93, + PMBUS_READ_DUTY_CYCLE = 0x94, + PMBUS_READ_FREQUENCY = 0x95, + PMBUS_READ_POUT = 0x96, + PMBUS_READ_PIN = 0x97, + + PMBUS_REVISION = 0x98, + PMBUS_MFR_ID = 0x99, + PMBUS_MFR_MODEL = 0x9A, + PMBUS_MFR_REVISION = 0x9B, + PMBUS_MFR_LOCATION = 0x9C, + PMBUS_MFR_DATE = 0x9D, + PMBUS_MFR_SERIAL = 0x9E, + +/* + * Virtual registers. + * Useful to support attributes which are not supported by standard PMBus + * registers but exist as manufacturer specific registers on individual chips. + * Must be mapped to real registers in device specific code. + * + * Semantics: + * Virtual registers are all word size. + * READ registers are read-only; writes are either ignored or return an error. + * RESET registers are read/write. Reading reset registers returns zero + * (used for detection), writing any value causes the associated history to be + * reset. + * Virtual registers have to be handled in device specific driver code. Chip + * driver code returns non-negative register values if a virtual register is + * supported, or a negative error code if not. The chip driver may return + * -ENODATA or any other error code in this case, though an error code other + * than -ENODATA is handled more efficiently and thus preferred. Either case, + * the calling PMBus core code will abort if the chip driver returns an error + * code when reading or writing virtual registers. + */ + PMBUS_VIRT_BASE = 0x100, + PMBUS_VIRT_READ_TEMP_AVG, + PMBUS_VIRT_READ_TEMP_MIN, + PMBUS_VIRT_READ_TEMP_MAX, + PMBUS_VIRT_RESET_TEMP_HISTORY, + PMBUS_VIRT_READ_VIN_AVG, + PMBUS_VIRT_READ_VIN_MIN, + PMBUS_VIRT_READ_VIN_MAX, + PMBUS_VIRT_RESET_VIN_HISTORY, + PMBUS_VIRT_READ_IIN_AVG, + PMBUS_VIRT_READ_IIN_MIN, + PMBUS_VIRT_READ_IIN_MAX, + PMBUS_VIRT_RESET_IIN_HISTORY, + PMBUS_VIRT_READ_PIN_AVG, + PMBUS_VIRT_READ_PIN_MIN, + PMBUS_VIRT_READ_PIN_MAX, + PMBUS_VIRT_RESET_PIN_HISTORY, + PMBUS_VIRT_READ_POUT_AVG, + PMBUS_VIRT_READ_POUT_MIN, + PMBUS_VIRT_READ_POUT_MAX, + PMBUS_VIRT_RESET_POUT_HISTORY, + PMBUS_VIRT_READ_VOUT_AVG, + PMBUS_VIRT_READ_VOUT_MIN, + PMBUS_VIRT_READ_VOUT_MAX, + PMBUS_VIRT_RESET_VOUT_HISTORY, + PMBUS_VIRT_READ_IOUT_AVG, + PMBUS_VIRT_READ_IOUT_MIN, + PMBUS_VIRT_READ_IOUT_MAX, + PMBUS_VIRT_RESET_IOUT_HISTORY, + PMBUS_VIRT_READ_TEMP2_AVG, + PMBUS_VIRT_READ_TEMP2_MIN, + PMBUS_VIRT_READ_TEMP2_MAX, + PMBUS_VIRT_RESET_TEMP2_HISTORY, + + PMBUS_VIRT_READ_VMON, + PMBUS_VIRT_VMON_UV_WARN_LIMIT, + PMBUS_VIRT_VMON_OV_WARN_LIMIT, + PMBUS_VIRT_VMON_UV_FAULT_LIMIT, + PMBUS_VIRT_VMON_OV_FAULT_LIMIT, + PMBUS_VIRT_STATUS_VMON, +}; + +/* + * OPERATION + */ +#define PB_OPERATION_CONTROL_ON BIT(7) + +/* + * CAPABILITY + */ +#define PB_CAPABILITY_SMBALERT BIT(4) +#define PB_CAPABILITY_ERROR_CHECK BIT(7) + +/* + * VOUT_MODE + */ +#define PB_VOUT_MODE_MODE_MASK 0xe0 +#define PB_VOUT_MODE_PARAM_MASK 0x1f + +#define PB_VOUT_MODE_LINEAR 0x00 +#define PB_VOUT_MODE_VID 0x20 +#define PB_VOUT_MODE_DIRECT 0x40 + +/* + * Fan configuration + */ +#define PB_FAN_2_PULSE_MASK (BIT(0) | BIT(1)) +#define PB_FAN_2_RPM BIT(2) +#define PB_FAN_2_INSTALLED BIT(3) +#define PB_FAN_1_PULSE_MASK (BIT(4) | BIT(5)) +#define PB_FAN_1_RPM BIT(6) +#define PB_FAN_1_INSTALLED BIT(7) + +/* + * STATUS_BYTE, STATUS_WORD (lower) + */ +#define PB_STATUS_NONE_ABOVE BIT(0) +#define PB_STATUS_CML BIT(1) +#define PB_STATUS_TEMPERATURE BIT(2) +#define PB_STATUS_VIN_UV BIT(3) +#define PB_STATUS_IOUT_OC BIT(4) +#define PB_STATUS_VOUT_OV BIT(5) +#define PB_STATUS_OFF BIT(6) +#define PB_STATUS_BUSY BIT(7) + +/* + * STATUS_WORD (upper) + */ +#define PB_STATUS_UNKNOWN BIT(8) +#define PB_STATUS_OTHER BIT(9) +#define PB_STATUS_FANS BIT(10) +#define PB_STATUS_POWER_GOOD_N BIT(11) +#define PB_STATUS_WORD_MFR BIT(12) +#define PB_STATUS_INPUT BIT(13) +#define PB_STATUS_IOUT_POUT BIT(14) +#define PB_STATUS_VOUT BIT(15) + +/* + * STATUS_IOUT + */ +#define PB_POUT_OP_WARNING BIT(0) +#define PB_POUT_OP_FAULT BIT(1) +#define PB_POWER_LIMITING BIT(2) +#define PB_CURRENT_SHARE_FAULT BIT(3) +#define PB_IOUT_UC_FAULT BIT(4) +#define PB_IOUT_OC_WARNING BIT(5) +#define PB_IOUT_OC_LV_FAULT BIT(6) +#define PB_IOUT_OC_FAULT BIT(7) + +/* + * STATUS_VOUT, STATUS_INPUT + */ +#define PB_VOLTAGE_UV_FAULT BIT(4) +#define PB_VOLTAGE_UV_WARNING BIT(5) +#define PB_VOLTAGE_OV_WARNING BIT(6) +#define PB_VOLTAGE_OV_FAULT BIT(7) + +/* + * STATUS_INPUT + */ +#define PB_PIN_OP_WARNING BIT(0) +#define PB_IIN_OC_WARNING BIT(1) +#define PB_IIN_OC_FAULT BIT(2) + +/* + * STATUS_TEMPERATURE + */ +#define PB_TEMP_UT_FAULT BIT(4) +#define PB_TEMP_UT_WARNING BIT(5) +#define PB_TEMP_OT_WARNING BIT(6) +#define PB_TEMP_OT_FAULT BIT(7) + +/* + * STATUS_FAN + */ +#define PB_FAN_AIRFLOW_WARNING BIT(0) +#define PB_FAN_AIRFLOW_FAULT BIT(1) +#define PB_FAN_FAN2_SPEED_OVERRIDE BIT(2) +#define PB_FAN_FAN1_SPEED_OVERRIDE BIT(3) +#define PB_FAN_FAN2_WARNING BIT(4) +#define PB_FAN_FAN1_WARNING BIT(5) +#define PB_FAN_FAN2_FAULT BIT(6) +#define PB_FAN_FAN1_FAULT BIT(7) + +/* + * CML_FAULT_STATUS + */ +#define PB_CML_FAULT_OTHER_MEM_LOGIC BIT(0) +#define PB_CML_FAULT_OTHER_COMM BIT(1) +#define PB_CML_FAULT_PROCESSOR BIT(3) +#define PB_CML_FAULT_MEMORY BIT(4) +#define PB_CML_FAULT_PACKET_ERROR BIT(5) +#define PB_CML_FAULT_INVALID_DATA BIT(6) +#define PB_CML_FAULT_INVALID_COMMAND BIT(7) + +enum pmbus_sensor_classes { + PSC_VOLTAGE_IN = 0, + PSC_VOLTAGE_OUT, + PSC_CURRENT_IN, + PSC_CURRENT_OUT, + PSC_POWER, + PSC_TEMPERATURE, + PSC_FAN, + PSC_NUM_CLASSES /* Number of power sensor classes */ +}; + +#define PMBUS_PAGES 32 /* Per PMBus specification */ + +/* Functionality bit mask */ +#define PMBUS_HAVE_VIN BIT(0) +#define PMBUS_HAVE_VCAP BIT(1) +#define PMBUS_HAVE_VOUT BIT(2) +#define PMBUS_HAVE_IIN BIT(3) +#define PMBUS_HAVE_IOUT BIT(4) +#define PMBUS_HAVE_PIN BIT(5) +#define PMBUS_HAVE_POUT BIT(6) +#define PMBUS_HAVE_FAN12 BIT(7) +#define PMBUS_HAVE_FAN34 BIT(8) +#define PMBUS_HAVE_TEMP BIT(9) +#define PMBUS_HAVE_TEMP2 BIT(10) +#define PMBUS_HAVE_TEMP3 BIT(11) +#define PMBUS_HAVE_STATUS_VOUT BIT(12) +#define PMBUS_HAVE_STATUS_IOUT BIT(13) +#define PMBUS_HAVE_STATUS_INPUT BIT(14) +#define PMBUS_HAVE_STATUS_TEMP BIT(15) +#define PMBUS_HAVE_STATUS_FAN12 BIT(16) +#define PMBUS_HAVE_STATUS_FAN34 BIT(17) +#define PMBUS_HAVE_VMON BIT(18) +#define PMBUS_HAVE_STATUS_VMON BIT(19) + +enum pmbus_data_format { linear = 0, direct, vid }; +enum vrm_version { vr11 = 0, vr12 }; + +struct pmbus_driver_info { + int pages; /* Total number of pages */ + enum pmbus_data_format format[PSC_NUM_CLASSES]; + enum vrm_version vrm_version; + /* + * Support one set of coefficients for each sensor type + * Used for chips providing data in direct mode. + */ + int m[PSC_NUM_CLASSES]; /* mantissa for direct data format */ + int b[PSC_NUM_CLASSES]; /* offset */ + int R[PSC_NUM_CLASSES]; /* exponent */ + + u32 func[PMBUS_PAGES]; /* Functionality, per page */ + /* + * The following functions map manufacturing specific register values + * to PMBus standard register values. Specify only if mapping is + * necessary. + * Functions return the register value (read) or zero (write) if + * successful. A return value of -ENODATA indicates that there is no + * manufacturer specific register, but that a standard PMBus register + * may exist. Any other negative return value indicates that the + * register does not exist, and that no attempt should be made to read + * the standard register. + */ + int (*read_byte_data)(struct i2c_client *client, int page, int reg); + int (*read_word_data)(struct i2c_client *client, int page, int reg); + int (*write_word_data)(struct i2c_client *client, int page, int reg, + u16 word); + int (*write_byte)(struct i2c_client *client, int page, u8 value); + /* + * The identify function determines supported PMBus functionality. + * This function is only necessary if a chip driver supports multiple + * chips, and the chip functionality is not pre-determined. + */ + int (*identify)(struct i2c_client *client, + struct pmbus_driver_info *info); + + /* Regulator functionality, if supported by this chip driver. */ + int num_regulators; + const struct regulator_desc *reg_desc; +}; + +/* Regulator ops */ + +extern const struct regulator_ops pmbus_regulator_ops; + +/* Macro for filling in array of struct regulator_desc */ +#define PMBUS_REGULATOR(_name, _id) \ + [_id] = { \ + .name = (_name # _id), \ + .id = (_id), \ + .of_match = of_match_ptr(_name # _id), \ + .regulators_node = of_match_ptr("regulators"), \ + .ops = &pmbus_regulator_ops, \ + .type = REGULATOR_VOLTAGE, \ + .owner = THIS_MODULE, \ + } + +/* Function declarations */ + +void pmbus_clear_cache(struct i2c_client *client); +int pmbus_set_page(struct i2c_client *client, u8 page); +int pmbus_read_word_data(struct i2c_client *client, u8 page, u8 reg); +int pmbus_write_word_data(struct i2c_client *client, u8 page, u8 reg, u16 word); +int pmbus_read_byte_data(struct i2c_client *client, int page, u8 reg); +int pmbus_write_byte(struct i2c_client *client, int page, u8 value); +int pmbus_write_byte_data(struct i2c_client *client, int page, u8 reg, + u8 value); +int pmbus_update_byte_data(struct i2c_client *client, int page, u8 reg, + u8 mask, u8 value); +void pmbus_clear_faults(struct i2c_client *client); +bool pmbus_check_byte_register(struct i2c_client *client, int page, int reg); +bool pmbus_check_word_register(struct i2c_client *client, int page, int reg); +int pmbus_do_probe(struct i2c_client *client, const struct i2c_device_id *id, + struct pmbus_driver_info *info); +int pmbus_do_remove(struct i2c_client *client); +const struct pmbus_driver_info *pmbus_get_driver_info(struct i2c_client + *client); + +#endif /* PMBUS_H */ \ No newline at end of file diff --git a/platform/broadcom/sonic-platform-modules-dell/e3224f/scripts/e3224f_platform.sh b/platform/broadcom/sonic-platform-modules-dell/e3224f/scripts/e3224f_platform.sh new file mode 100755 index 000000000000..05af9667fe14 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-dell/e3224f/scripts/e3224f_platform.sh @@ -0,0 +1,174 @@ +#!/bin/bash + +#platform init script for Dell E3224F + +source dell_i2c_utils.sh + +SONIC_VERSION=$(cat /etc/sonic/sonic_version.yml | grep "build_version" | sed -e "s/build_version: //g;s/'//g") +FIRST_BOOT_FILE="/host/image-${SONIC_VERSION}/platform/firsttime" + +#Attach/Detach the system devices +sys_devices() { + case $1 in + "new_device") #syseeprom + i2c_config "echo 24c02 0x50 > /sys/bus/i2c/devices/i2c-2/$1" + #Attach Fan Controller + i2c_config "echo emc2305 0x2c > /sys/bus/i2c/devices/i2c-7/$1" + #Attach temperature monitor + i2c_config "echo tmp75 0x48 > /sys/bus/i2c/devices/i2c-7/$1" + i2c_config "echo tmp75 0x49 > /sys/bus/i2c/devices/i2c-7/$1" + i2c_config "echo tmp75 0x4a > /sys/bus/i2c/devices/i2c-7/$1" + i2c_config "echo tmp75 0x4b > /sys/bus/i2c/devices/i2c-7/$1" + i2c_config "echo tmp75 0x4c > /sys/bus/i2c/devices/i2c-7/$1" + i2c_config "echo tmp75 0x4f > /sys/bus/i2c/devices/i2c-7/$1" + #Attach Fan EEPROM + i2c_config "echo 24c02 0x50 > /sys/bus/i2c/devices/i2c-15/$1" + i2c_config "echo 24c02 0x50 > /sys/bus/i2c/devices/i2c-16/$1" + i2c_config "echo 24c02 0x50 > /sys/bus/i2c/devices/i2c-17/$1" + ;; + "delete_device") i2c_config "echo 0x50 > /sys/bus/i2c/devices/i2c-2/$1" + i2c_config "echo 0x2c > /sys/bus/i2c/devices/i2c-7/$1" + i2c_config "echo 0x48 > /sys/bus/i2c/devices/i2c-7/$1" + i2c_config "echo 0x49 > /sys/bus/i2c/devices/i2c-7/$1" + i2c_config "echo 0x4a > /sys/bus/i2c/devices/i2c-7/$1" + i2c_config "echo 0x4b > /sys/bus/i2c/devices/i2c-7/$1" + i2c_config "echo 0x4c > /sys/bus/i2c/devices/i2c-7/$1" + i2c_config "echo 0x4f > /sys/bus/i2c/devices/i2c-7/$1" + i2c_config "echo 0x50 > /sys/bus/i2c/devices/i2c-15/$1" + i2c_config "echo 0x50 > /sys/bus/i2c/devices/i2c-16/$1" + i2c_config "echo 0x50 > /sys/bus/i2c/devices/i2c-17/$1" + ;; + *) echo "e3224f_platform: main_board_mux : invalid command !" + ;; + esac +} + +#Attach/Detach the SFP modules on PCA9548_2 +switch_board_sfp() { + case $1 in + "new_device") + # SFP ports + for ((i=27;i<=50;i++)); + do + i2c_config "echo optoe2 0x50 > /sys/bus/i2c/devices/i2c-$i/$1" + done + # SFP+ ports + for ((i=20;i<=23;i++)); + do + i2c_config "echo optoe2 0x50 > /sys/bus/i2c/devices/i2c-$i/$1" + done + # QSFP ports + i2c_config "echo optoe1 0x50 > /sys/bus/i2c/devices/i2c-24/$1" + i2c_config "echo optoe1 0x50 > /sys/bus/i2c/devices/i2c-25/$1" + + ;; + "delete_device") + for ((i=20;i<=50;i++)); + do + i2c_config "echo 0x50 > /sys/bus/i2c/devices/i2c-$i/$1" + done + ;; + "media_down") + for ((i=20;i<=23;i++)); + do + # Tx disable for 10G BaseT copper optics + eeprom=/sys/bus/i2c/devices/i2c-$i/$i-0050/eeprom + + # Gen2 or Gen3 copper optics + # Check for F10 encoding (starts with '0f10' or 'df10') at offset 96 and 7 byte size + # and then compare the 'product id' but skip other part of F10 string + f10_encoding=`hexdump -n7 -s96 $eeprom -e'7/1 "%02x"' 2>&1` + if [[ $f10_encoding =~ ^[0d]f10....28....|^[0d]f10....29.... ]]; then + cmd="\x01\x00\x09\x00\x01\x02" + echo -n -e $cmd | dd bs=1 count=6 of=$eeprom seek=506 obs=1 status=none + fi + done + ;; + *) echo "e3224f_platform: switch_board_sfp: invalid command !" + ;; + esac +} + +#Forcibly bring quad-port phy out of reset for 48-1G port functionality + +platform_firmware_versions() { + +FIRMWARE_VERSION_FILE=/var/log/firmware_versions +rm -rf ${FIRMWARE_VERSION_FILE} +# Get BIOS version +echo "BIOS: `dmidecode -s system-version `" > $FIRMWARE_VERSION_FILE +# Get CPU CPLD version +echo "CPU CPLD: $((`cat /sys/devices/platform/dell-e3224f-cpld.0/cpu_cpld_mjr_ver`)).$((`cat /sys/devices/platform/dell-e3224f-cpld.0/cpu_cpld_mnr_ver`))" >> $FIRMWARE_VERSION_FILE +# Get SYS CPLD version +echo "SYS CPLD: $((`cat /sys/devices/platform/dell-e3224f-cpld.0/sys_cpld_mjr_ver`)).$((`cat /sys/devices/platform/dell-e3224f-cpld.0/sys_cpld_mnr_ver`))" >> $FIRMWARE_VERSION_FILE +# Get PORT CPLD version +echo "PORT CPLD: $((`cat /sys/devices/platform/dell-e3224f-cpld.0/port_cpld_mjr_ver`)).$((`cat /sys/devices/platform/dell-e3224f-cpld.0/port_cpld_mnr_ver`))" >> $FIRMWARE_VERSION_FILE + +} + +install_python_api_package() { + device="/usr/share/sonic/device" + platform=$(/usr/local/bin/sonic-cfggen -H -v DEVICE_METADATA.localhost.platform) + + pip3 install $device/$platform/sonic_platform-1.0-py3-none-any.whl +} + +remove_python_api_package() { + rv=$(pip3 show sonic-platform > /dev/null 2>/dev/null) + if [ $? -eq 0 ]; then + rv=$(pip3 uninstall -y sonic-platform > /dev/null 2>/dev/null) + fi +} + +get_reboot_cause() { + REBOOT_REASON_FILE="/host/reboot-cause/platform/reboot_reason" + mkdir -p $(dirname $REBOOT_REASON_FILE) + + # Handle First Boot into software version with reboot cause determination support + if [[ ! -e $REBOOT_REASON_FILE ]]; then + echo "0x0" > $REBOOT_REASON_FILE + else + cat /sys/devices/platform/dell-e3224f-cpld.0/reboot_cause > $REBOOT_REASON_FILE + fi + echo "0x0" > /sys/devices/platform/dell-e3224f-cpld.0/reboot_cause +} + + +if [[ "$1" == "init" ]]; then + if [ -f $FIRST_BOOT_FILE ]; then + systemctl enable system-health.service + systemctl start --no-block system-health.service + fi + modprobe i2c-dev + modprobe i2c-mux-pca954x + modprobe pmbus + modprobe emc2305 + modprobe dell_e3224f_platform + + sys_devices "new_device" + get_reboot_cause + switch_board_sfp "new_device" + switch_board_sfp "media_down" + echo 0x00 > /sys/devices/platform/dell-e3224f-cpld.0/sfp_txdis + echo 0xf0 > /sys/devices/platform/dell-e3224f-cpld.0/sfpplus_txdis + echo 0xf3 > /sys/devices/platform/dell-e3224f-cpld.0/qsfp_rst + echo 0x00 > /sys/devices/platform/dell-e3224f-cpld.0/qsfp_lpmode + install_python_api_package + platform_firmware_versions +elif [[ "$1" == "deinit" ]]; then + switch_board_sfp "media_down" + switch_board_sfp "delete_device" + sys_devices "delete_device" + + modprobe -r dell_e3224f_platform + + modprobe -r emc2305 + modprobe -r pmbus + modprobe -r i2c-mux-pca954x + modprobe -r i2c-dev + remove_python_api_package +elif [ "$1" == "media_down" ]; then + switch_board_sfp $1 +else + echo "e3224f_platform : Invalid option !" +fi diff --git a/platform/broadcom/sonic-platform-modules-dell/e3224f/scripts/mux_controller.sh b/platform/broadcom/sonic-platform-modules-dell/e3224f/scripts/mux_controller.sh new file mode 100755 index 000000000000..f357b1179986 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-dell/e3224f/scripts/mux_controller.sh @@ -0,0 +1,27 @@ +#!/bin/bash + +init_devnum() { + found=0 + for devnum in 0 1; do + devname=`cat /sys/bus/i2c/devices/i2c-${devnum}/name` + # iSMT adapter can be at dff5c000 + echo $devname + if [[ "$devname" == 'SMBus iSMT adapter at '* ]] ; then + found=1 + break + fi + done + + [ $found -eq 0 ] && echo "cannot find iSMT" && exit 0 +} + +init_devnum +while [ 1 ] +do + if [ ! -f /sys/class/i2c-adapter/i2c-${devnum}/${devnum}-0071/idle_state ]; then + sleep 1 + continue + fi + echo -2 > /sys/class/i2c-adapter/i2c-${devnum}/${devnum}-0071/idle_state + break +done diff --git a/platform/broadcom/sonic-platform-modules-dell/e3224f/scripts/platform-modules-e3224f.sh b/platform/broadcom/sonic-platform-modules-dell/e3224f/scripts/platform-modules-e3224f.sh new file mode 100755 index 000000000000..cb6a8b6359e8 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-dell/e3224f/scripts/platform-modules-e3224f.sh @@ -0,0 +1,6 @@ +#!/bin/bash + +function platform-modules-e3224fServicePreStop() +{ + /usr/local/bin/e3224f_platform.sh media_down +} diff --git a/platform/broadcom/sonic-platform-modules-dell/e3224f/scripts/platform_sensors.py b/platform/broadcom/sonic-platform-modules-dell/e3224f/scripts/platform_sensors.py new file mode 100755 index 000000000000..454687e68469 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-dell/e3224f/scripts/platform_sensors.py @@ -0,0 +1,162 @@ +#!/usr/bin/python3 +""" + This provides support for the following objects: + * Onboard temperature sensors + * FAN trays + * PSU +""" + +import subprocess + +output = "" +try: + rc = 0 + output = subprocess.check_output('/usr/bin/sensors', stderr=subprocess.STDOUT, \ + encoding="utf-8").splitlines() + + valid = False + for line in output: + if line.startswith('acpitz') or line.startswith('coretemp'): + valid = True + if valid: + print(line) + if line == '': + valid = False + + print("Onboard Temperature Sensors:") + idx = 0 + for line in output: + if line.startswith('tmp75'): + print('\t' + output[idx+2].split('(')[0]) + idx += 1 + + print("\nFan Trays:") + idx = 0 + found_emc = False + fan_status = [' Normal', ' Abnormal'] + for line in output: + if line.startswith('emc'): + found_emc = True + with open('/sys/devices/platform/dell-e3224f-cpld.0/fan0_prs') as f: + line = f.readline() + present = int(line, 0) + if present: + print('\t' + 'Fan Tray 1:') + with open('/sys/bus/i2c/devices/7-002c/fan1_fault') as f: + line = f.readline() + status = int(line, 0) + print('\t\t' + 'Fan State:' + fan_status[status]) + print('\t\t' + 'Fan Speed:' + (output[idx+2].split('(')[0]).split(':')[1]) + with open('/sys/devices/platform/dell-e3224f-cpld.0/fan0_dir') as f: + line = f.readline() + direction = 'Intake' if line[:-1] == 'B2F' else 'Exhaust' + print('\t\t' + 'Airflow:\t' + direction) + else: + print('\t' + 'Fan Tray 1:\tNot Present') + + with open('/sys/devices/platform/dell-e3224f-cpld.0/fan1_prs') as f: + line = f.readline() + present = int(line, 0) + if present: + print('\t' + 'Fan Tray 2:') + with open('/sys/bus/i2c/devices/7-002c/fan2_fault') as f: + line = f.readline() + status = int(line, 0) + print('\t\t' + 'Fan State:' + fan_status[status]) + print('\t\t' + 'Fan Speed:' + (output[idx+3].split('(')[0]).split(':')[1]) + with open('/sys/devices/platform/dell-e3224f-cpld.0/fan1_dir') as f: + line = f.readline() + direction = 'Intake' if line[:-1] == 'B2F' else 'Exhaust' + print('\t\t' + 'Airflow:\t' + direction) + else: + print('\t' + 'Fan Tray 2:\tNot Present') + + with open('/sys/devices/platform/dell-e3224f-cpld.0/fan2_prs') as f: + line = f.readline() + present = int(line, 0) + if present: + print('\t' + 'Fan Tray 3:') + with open('/sys/bus/i2c/devices/7-002c/fan3_fault') as f: + line = f.readline() + status = int(line, 0) + print('\t\t' + 'Fan State:' + fan_status[status]) + print('\t\t' + 'Fan Speed:' + (output[idx+4].split('(')[0]).split(':')[1]) + with open('/sys/devices/platform/dell-e3224f-cpld.0/fan2_dir') as f: + line = f.readline() + direction = 'Intake' if line[:-1] == 'B2F' else 'Exhaust' + print('\t\t' + 'Airflow:\t' + direction) + else: + print('\t' + 'Fan Tray 3:\tNot Present') + idx += 1 + if not found_emc: + print('\t' + 'Fan Tray 1:\tNot Present') + print('\t' + 'Fan Tray 2:\tNot Present') + print('\t' + 'Fan Tray 3:\tNot Present') + + print('\nPSUs:') + idx = 0 + with open('/sys/devices/platform/dell-e3224f-cpld.0/psu0_prs') as f: + line = f.readline() + found_psu1 = int(line, 0) + if not found_psu1: + print('\tPSU1:\tNot Present') + else: + for line in output: + if line.startswith('dps460-i2c-10'): + with open('/sys/devices/platform/dell-e3224f-cpld.0/psu0_status') as f: + line = f.readline() + status = int(line, 0) + if not status: + print('\tPSU1:\tNot OK') + break + with open('/sys/bus/i2c/devices/10-0056/eeprom', encoding="ISO-8859-1") as f: + line = f.readline() + direction = 'Exhaust' if 'FORWARD' in line else 'Intake' + print('\tPSU1:') + print('\t\t' + output[idx+2].split('(')[0]) + print('\t\t' + output[idx+4].split('(')[0]) + print('\t\t' + output[idx+6].split('(')[0]) + print('\t\t' + output[idx+7].split('(')[0]) + print('\t\t' + output[idx+9].split('(')[0]) + print('\t\t' + output[idx+11].split('(')[0]) + print('\t\t' + output[idx+13].split('(')[0]) + print('\t\t' + output[idx+14].split('(')[0]) + print('\t\t' + output[idx+16].split('(')[0]) + print('\t\t' + output[idx+17].split('(')[0]) + print('\t\t' + 'Airflow:\t\t ' + direction) + idx += 1 + idx = 0 + with open('/sys/devices/platform/dell-e3224f-cpld.0/psu1_prs') as f: + line = f.readline() + found_psu2 = int(line, 0) + if not found_psu2: + print('\tPSU2:\tNot Present') + else: + for line in output: + if line.startswith('dps460-i2c-11'): + with open('/sys/devices/platform/dell-e3224f-cpld.0/psu1_status') as f: + line = f.readline() + status = int(line, 0) + if not status: + print('\tPSU2:\tNot OK') + break + print('\tPSU2:') + with open('/sys/bus/i2c/devices/11-0056/eeprom', encoding="ISO-8859-1") as f: + line = f.readline() + direction = 'Exhaust' if 'FORWARD' in line else 'Intake' + print('\t\t' + output[idx+2].split('(')[0]) + print('\t\t' + output[idx+4].split('(')[0]) + print('\t\t' + output[idx+6].split('(')[0]) + print('\t\t' + output[idx+7].split('(')[0]) + print('\t\t' + output[idx+9].split('(')[0]) + print('\t\t' + output[idx+11].split('(')[0]) + print('\t\t' + output[idx+13].split('(')[0]) + print('\t\t' + output[idx+14].split('(')[0]) + print('\t\t' + output[idx+16].split('(')[0]) + print('\t\t' + output[idx+17].split('(')[0]) + print('\t\t' + 'Airflow:\t\t ' + direction) + idx += 1 + +except subprocess.CalledProcessError as err: + print("Exception when calling get_sonic_error -> %s\n" %(err)) + rc = err.returncode diff --git a/platform/broadcom/sonic-platform-modules-dell/e3224f/scripts/portiocfg.py b/platform/broadcom/sonic-platform-modules-dell/e3224f/scripts/portiocfg.py new file mode 100755 index 000000000000..035a75bcc4dc --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-dell/e3224f/scripts/portiocfg.py @@ -0,0 +1,105 @@ +#!/usr/bin/python3 +# Copyright (c) 2015 Dell Inc. +# +# Licensed under the Apache License, Version 2.0 (the "License"); you may +# not use this file except in compliance with the License. You may obtain +# a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +# +# THIS CODE IS PROVIDED ON AN *AS IS* BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT +# LIMITATION ANY IMPLIED WARRANTIES OR CONDITIONS OF TITLE, FITNESS +# FOR A PARTICULAR PURPOSE, MERCHANTABLITY OR NON-INFRINGEMENT. +# +# See the Apache Version 2.0 License for specific language governing +# permissions and limitations under the License. +#Script to read/write the portio based registers + +import sys +import os +import getopt +import struct + +resource = '/dev/port' + +def usage(): + ''' This is the Usage Method ''' + + print('\t\t portiocfg.py --default') + print('\t\t portiocfg.py --get --offset ') + print('\t\t portiocfg.py --set --val --offset ') + sys.exit(1) + +def portio_reg_read(resource, offset): + fd = os.open(resource, os.O_RDONLY) + if fd < 0: + print('file open failed %s"%resource') + return + if os.lseek(fd, offset, os.SEEK_SET) != offset: + print('lseek failed on %s'%resource) + return + buf = os.read(fd, 1) + reg_val1 = ord(buf) + print('reg value %x'%reg_val1) + os.close(fd) + +def portio_reg_write(resource, offset, val): + fd = os.open(resource, os.O_RDWR) + if fd < 0: + print('file open failed %s"%resource') + return + if os.lseek(fd, offset, os.SEEK_SET) != offset: + print('lseek failed on %s'%resource) + return + ret = os.write(fd, struct.pack('B', val)) + if ret != 1: + print('write failed %d'%ret) + return + os.close(fd) + +def main(argv): + + ''' The main function will read the user input from the + command line argument and process the request ''' + + opts = '' + val = '' + choice = '' + resource = '' + offset = '' + + try: + opts, args = getopt.getopt(argv, "hgs:", \ + ["val=", "offset=", "help", "get", "set"]) + + except getopt.GetoptError: + usage() + + for opt, arg in opts: + + if opt in ('-h', '--help'): + choice = 'help' + + elif opt in ('-g', '--get'): + choice = 'get' + + elif opt in ('-s', '--set'): + choice = 'set' + + elif opt == '--offset': + offset = int(arg, 16) + + elif opt == '--val': + val = int(arg, 16) + + if choice == 'get' and offset != '': + portio_reg_read(resource, offset) + + elif choice == 'set' and offset != '' and val != '': + portio_reg_write(resource, offset, val) + + else: + usage() + +#Calling the main method +if __name__ == "__main__": + main(sys.argv[1:]) diff --git a/platform/broadcom/sonic-platform-modules-dell/e3224f/scripts/ports_xcvrd_notify.py b/platform/broadcom/sonic-platform-modules-dell/e3224f/scripts/ports_xcvrd_notify.py new file mode 100755 index 000000000000..c791590fb576 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-dell/e3224f/scripts/ports_xcvrd_notify.py @@ -0,0 +1,107 @@ +#!/usr/bin/env python3 + +""" + port_notify + port notify status change for SONiC +""" + +try: + from datetime import datetime + from swsscommon import swsscommon + from sonic_py_common import daemon_base, logger +except ImportError as e: + raise ImportError (str(e) + " - required module not found") + +# +# Constants ==================================================================== +# + +SYSLOG_IDENTIFIER = "port_notify" + + +STATE_PORT_TABLE = 'PORT_TABLE' + + +RJ45_PORT_START = 0; +RJ45_PORT_END = 47; + +# Global logger class instance +helper_logger = logger.Logger(SYSLOG_IDENTIFIER) + +XCVR_STATE_EMPTY = 0 +XCVR_STATE_ERROR = 1 +XCVR_STATE_INCOMP = 2 +XCVR_STATE_CONFIG = 3 +XCVR_STATE_READY = 4 +XCVR_STATE_TIMEOUT = 5 + +xcvr_state_tbl = { + XCVR_STATE_EMPTY: { "xcvr_state": "N/A", "xcvr_app_status": "down" }, + XCVR_STATE_ERROR: { "xcvr_state": "Error", "xcvr_app_status": "down" }, + XCVR_STATE_INCOMP: { "xcvr_state": "Incompatible", "xcvr_app_status": "up" }, + XCVR_STATE_CONFIG: { "xcvr_state": "Config", "xcvr_app_status": "down" }, + XCVR_STATE_TIMEOUT: { "xcvr_state": "Timeout", "xcvr_app_status": "up" }, + XCVR_STATE_READY: { "xcvr_state": "Ready", "xcvr_app_status": "up" } +} + +# Wait for port init is done +def wait_for_port_init_done(): + # Connect to APPL_DB and subscribe to PORT table notifications + appl_db = daemon_base.db_connect("APPL_DB") + + sel = swsscommon.Select() + sst = swsscommon.SubscriberStateTable(appl_db, swsscommon.APP_PORT_TABLE_NAME) + sel.addSelectable(sst) + + # Make sure this daemon started after all port configured + while True: + (state, c) = sel.select(1000) + if state == swsscommon.Select.TIMEOUT: + continue + if state != swsscommon.Select.OBJECT: + helper_logger.log_warning("sel.select() did not return swsscommon.Select.OBJECT") + continue + + (key, op, fvp) = sst.pop() + + # Wait until PortInitDone + if key in ["PortInitDone"]: + break + +def notify_port_xcvr_status(port_name, app_status_port_tbl, state_port_tbl, flag): + + fvs = swsscommon.FieldValuePairs([("xcvr_status", xcvr_state_tbl[flag]["xcvr_app_status"])]) + tm = datetime.now().strftime("%Y-%m-%d %H:%M:%S") + state_fvs = swsscommon.FieldValuePairs([("xcvr_status", xcvr_state_tbl[flag]["xcvr_state"]), ("xcvr_time", tm)]) + + state_port_tbl.set(port_name, state_fvs) + + app_status_port_tbl.set(port_name, fvs) + + helper_logger.log_notice("Port {} xcvr_app_status change to {}".format(port_name, xcvr_state_tbl[flag]["xcvr_app_status"])) + return True + + +def main(): + helper_logger.log_notice("Start port_notify") + # Connect to APP_DB and create transceiver dom info table + appl_db = daemon_base.db_connect("APPL_DB") + + app_status_port_tbl = swsscommon.ProducerStateTable(appl_db, + swsscommon.APP_PORT_APP_STATUS_TABLE_NAME) + + state_db = daemon_base.db_connect("STATE_DB") + state_port_tbl = swsscommon.Table(state_db, STATE_PORT_TABLE) + + # Wait for PortInitDone + wait_for_port_init_done() + + for port in range(RJ45_PORT_START, RJ45_PORT_END+1): + #print("Ethernet{}".format(port)) + notify_port_xcvr_status("Ethernet{}".format(port), app_status_port_tbl, state_port_tbl, XCVR_STATE_READY) + + helper_logger.log_notice("End port_notify") + + +if __name__ == '__main__': + main() diff --git a/platform/broadcom/sonic-platform-modules-dell/e3224f/scripts/sensors b/platform/broadcom/sonic-platform-modules-dell/e3224f/scripts/sensors new file mode 100755 index 000000000000..572b9d45e9e3 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-dell/e3224f/scripts/sensors @@ -0,0 +1,8 @@ +#!/bin/bash +#docker exec -i pmon sensors "$@" +docker exec -i pmon /usr/bin/platform_sensors.py "$@" + +#To probe sensors not part of lm-sensors +#if [ -r /usr/local/bin/platform_sensors.py ]; then +# python /usr/local/bin/platform_sensors.py +#fi diff --git a/platform/broadcom/sonic-platform-modules-dell/e3224f/setup.py b/platform/broadcom/sonic-platform-modules-dell/e3224f/setup.py new file mode 120000 index 000000000000..4f6de9941d96 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-dell/e3224f/setup.py @@ -0,0 +1 @@ +../s6100/setup.py \ No newline at end of file diff --git a/platform/broadcom/sonic-platform-modules-dell/e3224f/sonic_platform/__init__.py b/platform/broadcom/sonic-platform-modules-dell/e3224f/sonic_platform/__init__.py new file mode 100644 index 000000000000..3e1260e6b854 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-dell/e3224f/sonic_platform/__init__.py @@ -0,0 +1,8 @@ +""" +Module sonic_platform provides the platform dependent population of +platform.py, chassis.py, component.py, sfp.py, thermal.py, psu.py, +fan.py and watchdog.py +""" +__all__ = ["platform", "chassis", "sfp", "eeprom", "component", "thermal", "psu", "fan", "fan_drawer", "watchdog"] +from sonic_platform import * + diff --git a/platform/broadcom/sonic-platform-modules-dell/e3224f/sonic_platform/chassis.py b/platform/broadcom/sonic-platform-modules-dell/e3224f/sonic_platform/chassis.py new file mode 100644 index 000000000000..15dddd1b4126 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-dell/e3224f/sonic_platform/chassis.py @@ -0,0 +1,442 @@ +#!/usr/bin/env python + +############################################################################# +# DELLEMC E3224F +# +# Module contains an implementation of SONiC Platform Base API and +# provides the platform information +# +############################################################################# + +try: + import os + import sys + import time + from sonic_platform_base.chassis_base import ChassisBase + from sonic_platform.sfp import Sfp + from sonic_platform.eeprom import Eeprom + from sonic_platform.component import Component + from sonic_platform.psu import Psu + from sonic_platform.thermal import Thermal + from sonic_platform.watchdog import Watchdog + from sonic_platform.fan_drawer import FanDrawer +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + + +MAX_E3224F_FANTRAY = 3 +MAX_E3224F_FAN = 1 +MAX_E3224F_PSU = 2 +MAX_E3224F_THERMAL = 5 +MAX_E3224F_COMPONENT = 3 # BIOS, CPU CPLD and SYS CPLD + +media_part_num_list = set([ \ +"8T47V","XTY28","MHVPK","GF76J","J6FGD","F1KMV","9DN5J","H4DHD","6MCNV","0WRX0","X7F70","5R2PT","WTRD1","WTRD1","WTRD1","WTRD1","5250G","WTRD1","C5RNH","C5RNH","FTLX8571D3BCL-FC", +"C5RNH","5250G","N8TDR","7D64H","7D64H","RN84N","RN84N","HMTNW","6K3Y6","6K3Y6","TY5FM","50M0R","PGYJT","WP2PP","85Y13","1HCGH","FP9R1","FYD0M","C6Y7M","C6Y7M","V250M","V250M", +"5CWK6","5CWK6","53HVN","53HVN","358VV","358VV","MV799","MV799","YJF03","P9GND","T1KCN","1DXKP","MT7R2","K0T7R","W5G04","7TCDN","7TCDN","7TCDN","7TCDN","7TCDN","V3XJK","0MV31", +"5FVP7","N6KM9","C41MF","77KC3","XW7J0","V4NJV","2XJHY","H93DH","H93DH","F8CG0","F8CG0","F8CG0","119N6","WFMF5","794RX","288F6","1M31V","1M31V","5NP8R","5NP8R","4TC09","4TC09", +"FC6KV","FC6KV","J90VN","J90VN","05RH0","05RH0","YDN52","0C2YV","YDN52","0C2YV","9JT65","D7M6H","6GW14","FYVFW","0VF5H","P4YPY","P4YPY","TCPM2","TCPM2","JNPF8","JNPF8","27GG5", +"27GG5","P8T4W","P8T4W","JR54Y","M6N0J","XJYD0","K44H9","035KG","P7C7N","76V43","3CC35","FN4FC","26FN3","YFNDD","YFNDD","7R9N9","035KG","P7C7N","76V43","3CC35","PLRXPLSCS43811", +"FN4FC","26FN3","YFNDD","YFNDD","7R9N9","G86YJ","V407F","V407F","9KH6T","G86YJ","V407F","9KH6T","2JVDD","D0R73","VXFJY","9X8JP","2JVDD","D0R73","VXFJY","9X8JP","2JVDD","D0R73","VXFJY", +"9X8JP","GMFC5","GMFC5","GMFC5","D7P80","3MFXG","3MFXG","0GWXJ","THPF3","THPF3","THPF3","THPF3","THPF3","PJ62G","3XCX1","JJYKG","RRRTK","16K56","86JM2","K5R6C","7MG2C","WTPPN","9HTT2", +"NKM4F","VXGGG","JC9W6","6MR8M","RP3GV","M5PPJ","XKY55","TKCXT","05J8P","5WGKD","XFDRT","NW8DM","YPKH3","5WGKD","XFDRT","NW8DM","YPKH3","71XXK","MVCX6","0XYP6","HPPVW","3GHRT","71XXK", +"MVCX6","0XYP6","HPPVW","3GHRT","2X5T6","135V2","KD5MV","2X5T6","KD5MV","HHFK0","3YWG7","5CMT2","RCVP5","X5DH4","HHFK0","3YWG7","5CMT2","RCVP5","X5DH4","3YWG7","5CMT2","RCVP5","X5DH4", +"4WJ41","4WJ41","14NV5","14NV5","14NV5","4WGYD","YKMH7","X7CCC","X7CCC","0X9CT","0CY8V","P7D7R","W4GPP","W4GPP","W4GPP","HHHCHC","07RN7","07RN7","0YR96","0YR96","JCYM9","FTLX8571D3BCL", +"DDW0X","VPFDJ","229KM","9FC7D","DDW0X","VPFDJ","6FMR5","J7K20","N3K9W","6FMR5","8R4VM","7VN5T","D9YM8","8R4VM","VYXPW","87TPX","WY6FK","VYXPW","87TPX","WY6FK","WG8C4","N8K82","2DV6Y", +"77C3C","RC0HM","77C3C","RC0HM","JHXTN","3P3PG","92YVM","4VX5M","4VX5M","6RRGD","W4JWV","22V6R","XR11M","9GMDY","JMCWK","TP2F0","6MGDY","78RHK", "C0TP5","0WDNV","FCLF8522P2BTL"\ +]) +class Chassis(ChassisBase): + """ + DELLEMC Platform-specific Chassis class + """ + REBOOT_CAUSE_PATH = "/host/reboot-cause/platform/reboot_reason" + CPLD_DIR = '/sys/devices/platform/dell-e3224f-cpld.0/' + + _global_port_pres_dict = {} + + _sfpp_port_to_i2c_mapping = { + 25: 20, + 26: 21, + 27: 22, + 28: 23, + 29: 24, + 30: 25, + 1: 27, + 2: 28, + 3: 29, + 4: 30, + 5: 31, + 6: 32, + 7: 33, + 8: 34, + 9: 35, + 10: 36, + 11: 37, + 12: 38, + 13: 39, + 14: 40, + 15: 41, + 16: 42, + 17: 43, + 18: 44, + 19: 45, + 20: 46, + 21: 47, + 22: 48, + 23: 49, + 24: 50, + } + SYSTEM_LED_COLORS = { + "green", + "blink_green", + "yellow", + "blink_yellow" + } + + def __init__(self): + ChassisBase.__init__(self) + # sfp.py will read eeprom contents and retrive the eeprom data. + # We pass the eeprom path from chassis.py + self.PORT_START = 1 + self.PORT_END = 30 + self.PORTS_IN_BLOCK = (self.PORT_END + 1) + self.SFP_PORT_START = 1 + self._sfp_port = range(self.SFP_PORT_START, self.PORTS_IN_BLOCK) + eeprom_base = "/sys/class/i2c-adapter/i2c-{0}/{0}-0050/eeprom" + for index in range(self.PORT_START, self.PORTS_IN_BLOCK): + eeprom_path = '' + if index in self._sfp_port: + eeprom_path = eeprom_base.format(self._sfpp_port_to_i2c_mapping[index]) + if(index < 29): + port_type = 'SFP' + else: + port_type = 'QSFP' + + sfp_node = Sfp(index, port_type, eeprom_path) + self._sfp_list.append(sfp_node) + + self._eeprom = Eeprom() + self._watchdog = Watchdog() + self._num_sfps = 30 + self._num_fans = MAX_E3224F_FANTRAY * MAX_E3224F_FAN + for k in range(MAX_E3224F_FANTRAY): + fandrawer = FanDrawer(k) + self._fan_drawer_list.append(fandrawer) + self._fan_list.extend(fandrawer._fan_list) + + self._psu_list = [Psu(i) for i in range(MAX_E3224F_PSU)] + self._thermal_list = [Thermal(i) for i in range(MAX_E3224F_THERMAL)] + self._component_list = [Component(i) for i in range(MAX_E3224F_COMPONENT)] + for port_num in self._sfp_port: + # sfp get uses zero-indexing, but port numbers start from 1 + presence = self.get_sfp(port_num-1).get_presence() + self._global_port_pres_dict[port_num] = '1' if presence else '0' + + self._watchdog = Watchdog() + self.status_led_reg = "system_led" + self.locator_led_reg = "locator_led" + self.LOCATOR_LED_ON = "blink_blue" + self.LOCATOR_LED_OFF = self.STATUS_LED_COLOR_OFF + + def _get_cpld_register(self, reg_name): + # On successful read, returns the value read from given + # reg name and on failure rethrns 'ERR' + cpld_reg_file = self.CPLD_DIR + '/' + reg_name + try: + with open(cpld_reg_file, 'r') as fd: + rv = fd.read() + except IOError : return 'ERR' + return rv.strip('\r\n').lstrip(' ') + + def _set_cpld_register(self, reg_name, value): + # On successful write, returns the value will be written on + # reg_name and on failure returns 'ERR' + rv = 'ERR' + cpld_reg_file = self.CPLD_DIR + '/' + reg_name + + if (not os.path.isfile(cpld_reg_file)): + return rv + + try: + with open(cpld_reg_file, 'w') as fd: + rv = fd.write(str(value)) + except Exception: + rv = 'ERR' + + return rv + + def get_status_led(self): + """ + Gets the current system LED color + + Returns: + A string that represents the supported color + """ + + color = self._get_cpld_register(self.status_led_reg) + + if color not in list(self.SYSTEM_LED_COLORS): + return self.sys_ledcolor + + return color + + def initizalize_system_led(self): + self.sys_ledcolor = "green" + + def set_status_led(self,color): + """ + Set system LED status based on the color type passed in the argument. + Argument: Color to be set + Returns: + bool: True is specified color is set, Otherwise return False + """ + + if color not in list(self.SYSTEM_LED_COLORS): + return False + if(not self._set_cpld_register(self.status_led_reg, color)): + return False + + self.sys_ledcolor = color + return True + +# check for this event change for sfp / do we need to handle timeout/sleep + + def get_change_event(self, timeout=0): + """ + Returns a nested dictionary containing all devices which have + experienced a change at chassis level + """ + port_dict = {} + change_dict = {} + change_dict['sfp'] = port_dict + while True: + for port_num in self._sfp_port: + # sfp get uses zero-indexing, but port numbers start from 1 + presence = self.get_sfp(port_num-1).get_presence() + if(presence and self._global_port_pres_dict[port_num] == '0'): + self._global_port_pres_dict[port_num] = '1' + port_dict[port_num] = '1' + elif(not presence and self._global_port_pres_dict[port_num] == '1'): + self._global_port_pres_dict[port_num] = '0' + port_dict[port_num] = '0' + + if(len(port_dict) > 0): + return True, change_dict + + time.sleep(0.5) + + + + def get_sfp(self, index): + """ + Retrieves sfp represented by (0-based) index + + Args: + index: An integer, the index (0-based) of the sfp to retrieve. + The index should be the sequence of a physical port in a chassis, + starting from 0. + For example, 0 for Ethernet0, 1 for Ethernet4 and so on. + + Returns: + An object dervied from SfpBase representing the specified sfp + """ + sfp = None + + try: + # The index will start from 0 + sfp = self._sfp_list[index-1] + except IndexError: + sys.stderr.write("SFP index {} out of range (1-{})\n".format( + index, len(self._sfp_list))) + return sfp + + def get_name(self): + """ + Retrieves the name of the chassis + Returns: + string: The name of the chassis + """ + return self._eeprom.modelstr() + + def get_presence(self): + """ + Retrieves the presence of the chassis + Returns: + bool: True if chassis is present, False if not + """ + return True + + def get_model(self): + """ + Retrieves the model number (or part number) of the chassis + Returns: + string: Model/part number of chassis + """ + return self._eeprom.part_number_str() + + def get_serial(self): + """ + Retrieves the serial number of the chassis (Service tag) + Returns: + string: Serial number of chassis + """ + return self._eeprom.serial_str() + + def get_status(self): + """ + Retrieves the operational status of the chassis + Returns: + bool: A boolean value, True if chassis is operating properly + False if not + """ + return True + + def get_base_mac(self): + """ + Retrieves the base MAC address for the chassis + Returns: + A string containing the MAC address in the format + 'XX:XX:XX:XX:XX:XX' + """ + return self._eeprom.base_mac_addr('') + + def get_serial_number(self): + """ + Retrieves the hardware serial number for the chassis + Returns: + A string containing the hardware serial number for this chassis. + """ + return self._eeprom.serial_number_str() + + def get_system_eeprom_info(self): + """ + Retrieves the full content of system EEPROM information for the chassis + Returns: + A dictionary where keys are the type code defined in + OCP ONIE TlvInfo EEPROM format and values are their corresponding + values. + """ + return self._eeprom.system_eeprom_info() + + def get_reboot_cause(self): + """ + Retrieves the cause of the previous reboot + Returns: + A tuple (string, string) where the first element is a string + containing the cause of the previous reboot. This string must be + one of the predefined strings in this class. If the first string + is "REBOOT_CAUSE_HARDWARE_OTHER", the second string can be used + to pass a description of the reboot cause. + """ + + try: + with open(self.REBOOT_CAUSE_PATH) as fd: + reset_reason = int(fd.read(), 16) + except: + return(ChassisBase.REBOOT_CAUSE_NON_HARDWARE, None) + + if (reset_reason & 0x02) : + return (ChassisBase.REBOOT_CAUSE_NON_HARDWARE, 'Shutdown by CPU') + elif (reset_reason & 0x04) : + return (ChassisBase.REBOOT_CAUSE_NON_HARDWARE, "Failed to boot from configured boot device") + elif (reset_reason & 0x8) : + return (ChassisBase.REBOOT_CAUSE_NON_HARDWARE, "Booted from Backup BIOS") + elif (reset_reason & 0x10) : + return(ChassisBase.REBOOT_CAUSE_WATCHDOG, None) + elif (reset_reason & 0x20): + return(ChassisBase.REBOOT_CAUSE_THERMAL_OVERLOAD_CPU) + elif (reset_reason & 0x40) : + return (ChassisBase.REBOOT_CAUSE_NON_HARDWARE, 'Warm Reset') + elif (reset_reason & 0x80) : + return (ChassisBase.REBOOT_CAUSE_NON_HARDWARE, 'Cold Reset') + elif (reset_reason & 0x01) : + return (ChassisBase.REBOOT_CAUSE_POWER_LOSS, None) + + def get_eeprom(self): + """ + Retrieves the Sys Eeprom instance for the chassis. + Returns : + The instance of the Sys Eeprom + """ + return self._eeprom + + def get_num_fans(self): + """ + Retrives the number of Fans on the chassis. + Returns : + An integer represents the number of Fans on the chassis. + """ + return self._num_fans + + def get_num_sfps(self): + """ + Retrives the numnber of Media on the chassis. + Returns: + An integer represences the number of SFPs on the chassis. + """ + return self._num_sfps + + def get_qualified_media_list(self): + return media_part_num_list + + def set_locator_led(self, color): + """ + Sets the state of the Chassis Locator LED + + Args: + color: A string representing the color with which to set the Chassis Locator LED + + Returns: + bool: True if the Chassis Locator LED state is set successfully, False if not + + """ + if color == self.LOCATOR_LED_ON or color == self.LOCATOR_LED_OFF: + rv = self._set_cpld_register(self.locator_led_reg, color) + if (rv != 'ERR'): + return True + else: + return False + + def get_locator_led(self): + """ + Gets the state of the Chassis Locator LED + + Returns: + LOCATOR_LED_ON or LOCATOR_LED_OFF + """ + loc_led = self._get_cpld_register(self.locator_led_reg) + if (loc_led != 'ERR'): + # Actually driver returns the color code 'blink_blue' + # Returning "blue_blink" to make it common to all platforms output + if (loc_led == self.LOCATOR_LED_ON): + self.LOCATOR_LED_ON = self.STATUS_LED_COLOR_BLUE_BLINK + return self.LOCATOR_LED_ON + else: + return self.LOCATOR_LED_OFF + else: + return self.LOCATOR_LED_OFF + + def get_position_in_parent(self): + """ + Retrieves 1-based relative physical position in parent device. + Returns: + integer: The 1-based relative physical position in parent + device or -1 if cannot determine the position + """ + return -1 + + def is_replaceable(self): + """ + Indicate whether Chassis is replaceable. + Returns: + bool: True if it is replaceable. + """ + return False + def get_revision(self): + """ + Retrives the hardware revision of the device + + Returns: + string: Revision value of device + """ + return self._eeprom.revision_str() diff --git a/platform/broadcom/sonic-platform-modules-dell/e3224f/sonic_platform/component.py b/platform/broadcom/sonic-platform-modules-dell/e3224f/sonic_platform/component.py new file mode 100644 index 000000000000..778727d6bc4b --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-dell/e3224f/sonic_platform/component.py @@ -0,0 +1,137 @@ +#!/usr/bin/env python + +######################################################################## +# DELLEMC E3224F +# +# Module contains an implementation of SONiC Platform Base API and +# provides the Components' (e.g., BIOS, CPLD, FPGA, BMC etc.) available in +# the platform +# +######################################################################## + +try: + import subprocess + from sonic_platform_base.component_base import ComponentBase + +except ImportError as e: + raise ImportError(str(e) + "- required module not found") +def get_bios_version(): + return subprocess.check_output(['dmidecode', '-s', 'system-version']).strip().decode() + +def get_cpld_version(cpld): + mjr_ver_path = '/sys/devices/platform/dell-e3224f-cpld.0/' + cpld + '_mjr_ver' + mnr_ver_path = '/sys/devices/platform/dell-e3224f-cpld.0/' + cpld + '_mnr_ver' + mjr_ver = subprocess.check_output(['cat', mjr_ver_path]).strip()[2:].decode() + mnr_ver = subprocess.check_output(['cat', mnr_ver_path]).strip()[2:].decode() + return (str(mjr_ver) + '.' + str(mnr_ver)) + +class Component(ComponentBase): + """DellEMC Platform-specific Component class""" + + CHASSIS_COMPONENTS = [ + ['BIOS', + 'Performs initialization of hardware components during booting', + get_bios_version() + ], + ['CPU CPLD', + 'Used for managing the CPU power sequence and CPU states', + get_cpld_version('cpu_cpld') + ], + ['SYS CPLD', + 'Used for managing FAN, PSU, SFP+ modules (25-28) and QSFP modules (29-30)', + get_cpld_version('sys_cpld') + ], + ['PORT CPLD', + 'Used for managing SFP modules (1-24)', + get_cpld_version('port_cpld') + ] + ] + + def __init__(self, component_index=0): + self.index = component_index + self.name = self.CHASSIS_COMPONENTS[self.index][0] + self.description = self.CHASSIS_COMPONENTS[self.index][1] + self.version = self.CHASSIS_COMPONENTS[self.index][2] + + def get_name(self): + """ + Retrieves the name of the component + Returns: + A string containing the name of the component + """ + return self.name + + def get_description(self): + """ + Retrieves the description of the component + Returns: + A string containing the description of the component + """ + return self.description + + def get_firmware_version(self): + """ + Retrieves the firmware version of the component + Returns: + A string containing the firmware version of the component + """ + return self.version + + def install_firmware(self, image_path): + """ + Installs firmware to the component + Args: + image_path: A string, path to firmware image + Returns: + A boolean, True if install was successful, False if not + """ + return False + + def get_presence(self): + """ + Retrieves the presence of the component + Returns: + bool: True if present, False if not + """ + return True + + def get_model(self): + """ + Retrieves the part number of the component + Returns: + string: Part number of component + """ + return 'NA' + + def get_serial(self): + """ + Retrieves the serial number of the component + Returns: + string: Serial number of component + """ + return 'NA' + + def get_status(self): + """ + Retrieves the operational status of the component + Returns: + bool: True if component is operating properly, False if not + """ + return True + + def get_position_in_parent(self): + """ + Retrieves 1-based relative physical position in parent device. + Returns: + integer: The 1-based relative physical position in parent + device or -1 if cannot determine the position + """ + return -1 + + def is_replaceable(self): + """ + Indicate whether component is replaceable. + Returns: + bool: True if it is replaceable. + """ + return False diff --git a/platform/broadcom/sonic-platform-modules-dell/e3224f/sonic_platform/eeprom.py b/platform/broadcom/sonic-platform-modules-dell/e3224f/sonic_platform/eeprom.py new file mode 100644 index 000000000000..4ee3d12b899e --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-dell/e3224f/sonic_platform/eeprom.py @@ -0,0 +1,131 @@ +#!/usr/bin/env python + +############################################################################# +# DellEmc E3224F +# +# Platform and model specific eeprom subclass, inherits from the base class, +# and provides the followings: +# - the eeprom format definition +# - specific encoder/decoder if there is special need +############################################################################# +try: + import os.path + from sonic_eeprom import eeprom_tlvinfo +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + + +class Eeprom(eeprom_tlvinfo.TlvInfoDecoder): + + def __init__(self): + self.eeprom_path = None + f = '/sys/class/i2c-adapter/i2c-2/2-0050/eeprom' + if not os.path.exists(f): + return + self.eeprom_path = f + super(Eeprom, self).__init__(self.eeprom_path, 0, '', True) + self.eeprom_tlv_dict = dict() + try: + self.eeprom_data = self.read_eeprom() + except Exception: + self.eeprom_data = "N/A" + raise RuntimeError("Eeprom is not Programmed") + + eeprom = self.eeprom_data + + if not self.is_valid_tlvinfo_header(eeprom): + return + + total_length = ((eeprom[9]) << 8) | (eeprom[10]) + tlv_index = self._TLV_INFO_HDR_LEN + tlv_end = self._TLV_INFO_HDR_LEN + total_length + + while (tlv_index + 2) < len(eeprom) and tlv_index < tlv_end: + if not self.is_valid_tlv(eeprom[tlv_index:]): + break + + tlv = eeprom[tlv_index:tlv_index + 2 + + (eeprom[tlv_index + 1])] + code = "0x%02X" % ((tlv[0])) + + + name, value = self.decoder(None, tlv) + + self.eeprom_tlv_dict[code] = value + if (eeprom[tlv_index]) == self._TLV_CODE_CRC_32: + break + + tlv_index += (eeprom[tlv_index+1]) + 2 + + def serial_number_str(self): + """ + Returns the serial number + """ + (is_valid, results) = self.get_tlv_field( + self.eeprom_data, self._TLV_CODE_SERIAL_NUMBER) + if not is_valid: + return "N/A" + return results[2].decode('ascii') + + def base_mac_addr(self, e): + """ + Returns the base mac address found in the system EEPROM + """ + (is_valid, t) = self.get_tlv_field( + self.eeprom_data, self._TLV_CODE_MAC_BASE) + if not is_valid or t[1] != 6: + return super(TlvInfoDecoder, self).switchaddrstr(e) + + return ":".join(["{:02x}".format(T) for T in t[2]]).upper() + + def modelstr(self): + """ + Returns the Model name + """ + (is_valid, results) = self.get_tlv_field( + self.eeprom_data, self._TLV_CODE_PRODUCT_NAME) + if not is_valid: + return "N/A" + + return results[2].decode('ascii') + + def part_number_str(self): + """ + Returns the part number + """ + (is_valid, results) = self.get_tlv_field( + self.eeprom_data, self._TLV_CODE_PART_NUMBER) + if not is_valid: + return "N/A" + + return results[2].decode('ascii') + + def serial_str(self): + """ + Returns the servicetag number + """ + (is_valid, results) = self.get_tlv_field( + self.eeprom_data, self._TLV_CODE_SERVICE_TAG) + if not is_valid: + return "N/A" + + return results[2].decode('ascii') + + def revision_str(self): + """ + Returns the device revision + """ + (is_valid, results) = self.get_tlv_field( + self.eeprom_data, self._TLV_CODE_DEVICE_VERSION) + if not is_valid: + return "N/A" + + return results[2].decode('ascii') + + def system_eeprom_info(self): + """ + Returns a dictionary, where keys are the type code defined in + ONIE EEPROM format and values are their corresponding values + found in the system EEPROM. + """ + return self.eeprom_tlv_dict diff --git a/platform/broadcom/sonic-platform-modules-dell/e3224f/sonic_platform/fan.py b/platform/broadcom/sonic-platform-modules-dell/e3224f/sonic_platform/fan.py new file mode 100644 index 000000000000..620a398c24c7 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-dell/e3224f/sonic_platform/fan.py @@ -0,0 +1,254 @@ +#!/usr/bin/env python + +######################################################################## +# DellEMC E3224F +# +# Module contains an implementation of SONiC Platform Base API and +# provides the Fans' information which are available in the platform. +# +######################################################################## +try: + import os + from sonic_platform_base.fan_base import FanBase +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + + +class Fan(FanBase): + """DellEMC Platform-specific Fan class""" + + def __init__(self, fantray_index=0, fan_index=0, psu_fan=False, dependency=None): + self.is_psu_fan = psu_fan + + if not self.is_psu_fan: + # API index is starting from 0, DellEMC platform index is + # starting from 1 + self.presence_reg = "fan{}_prs".format(fantray_index) + self.dir_reg = "fan{}_dir".format(fantray_index) + self.rpm_file = "/sys/bus/i2c/devices/7-002c/fan{}_input".format(fantray_index+1) + self.status_file = "/sys/bus/i2c/devices/7-002c/fan{}_fault".format(fantray_index+1) + self.eeprom = "/sys/bus/i2c/devices/{}-0050/eeprom".format(15 + fantray_index) + self.fantray_index = fantray_index + self.fan_index = fan_index + else: + self.psu_index = fan_index - 1 + self.dependancy = dependency + self.presence_reg = "psu{}_prs".format(self.psu_index) + self.status_reg = "psu{}_status".format(self.psu_index) + self.dir_reg = "" + self.dps_hwmon = "/sys/bus/i2c/devices/{}-005e/hwmon/".format(self.psu_index + 10) + self.eeprom = "/sys/bus/i2c/devices/{}-0056/eeprom".format(self.psu_index + 10) + self.fan_index = fan_index + self.max_speed = 0 + + def _get_cpld_register(self, reg_name): + # On successful read, returns the value read from given + # reg name and on failure rethrns 'ERR' + cpld_dir = "/sys/devices/platform/dell-e3224f-cpld.0/" + cpld_reg_file = cpld_dir + '/' + reg_name + try: + with open(cpld_reg_file, 'r')as fd: + buf = fd.read() + except (IOError, AttributeError): + return 'ERR' + return buf.strip('\r\n').lstrip(' ') + + def get_name(self): + """ + Retrieves the name of the device + Returns: + String: The name of the device + """ + if self.is_psu_fan: + return "PSU{} Fan".format(self.psu_index+1) + else: + return "FanTray{}-Fan{}".format(self.fantray_index+1, self.fan_index+1) + + def get_model(self): + """ + Retrieves the part number of the FAN + Returns: + String: Part number of FAN + """ + try: + val = open(self.eeprom, "rb").read()[13:19] + except Exception: + val = None + return val.decode() + + def get_serial(self): + """ + Retrieves the serial number of the FAN + Returns: + String: Serial number of FAN + """ + try: + val = open(self.eeprom, "rb").read()[21:41] + except Exception: + val = None + return val.decode() + + def get_presence(self): + """ + Retrieves the presence of the FAN + Returns: + bool: True if fan is present, False if not + """ + + presence = self._get_cpld_register(self.presence_reg) + if presence == 'ERR': + return False + if int(presence,0) == 1: + return True + else: + return False + + def get_status(self): + """ + Retrieves the operational status of the FAN + Returns: + bool: True if FAN is operating properly, False if not + """ + if not self.is_psu_fan: + status = open(self.status_file, "rb").read() + if int(status, 0) == 1: + return False + else: + return True + else: + status = self._get_cpld_register(self.status_reg) + if status == 'ERR': + return False + if int(status, 0) == 1: + return True + else: + return False + + def get_direction(self): + """ + Retrieves the fan airfow direction + Returns: + A string, either FAN_DIRECTION_INTAKE or FAN_DIRECTION_EXHAUST + depending on fan direction + + Notes: + In DellEMC platforms, + - Forward/Exhaust : Air flows from Port side to Fan side. + - Reverse/Intake : Air flows from Fan side to Port side. + """ + if not self.is_psu_fan: + val = self._get_cpld_register(self.dir_reg) + direction = 'exhaust' if val == 'F2B' else 'intake' + if direction == 'ERR': + return None + else: + try: + val = open(self.eeprom, "rb").read()[0xe1:0xe8] + except Exception: + return None + direction = 'exhaust' if val == 'FORWARD' else 'intake' + return direction + + def get_speed(self): + """ + Retrieves the speed of the fan + Returns: + int: percentage of the max fan speed + """ + if self.max_speed == 0: + self.max_speed = 23500 + fan_speed = 0 + try: + if not self.is_psu_fan: + rpm_file = self.rpm_file + else: + dps_dir = self.dps_hwmon + '/' + os.listdir(self.dps_hwmon)[0] + rpm_file = dps_dir + '/' + 'fan1_input' + fan_speed = int(open(rpm_file, "rb").read()) + except Exception: + return None + speed = (100 * fan_speed)//self.max_speed + return speed + + def get_speed_rpm(self): + """ + Retrieves the speed of the fan + Returns: + int: percentage of the max fan speed + """ + fan_speed = 0 + try: + if not self.is_psu_fan: + rpm_file = self.rpm_file + else: + dps_dir = self.dps_hwmon + '/' + os.listdir(self.dps_hwmon)[0] + rpm_file = dps_dir + '/' + 'fan1_input' + fan_speed = int(open(rpm_file, "rb").read()) + except Exception: + return None + return fan_speed + + def get_position_in_parent(self): + """ + Retrieves 1-based relative physical position in parent device. + Returns: + integer: The 1-based relative physical position in parent + device or -1 if cannot determine the position + """ + return self.fan_index + + def is_replaceable(self): + """ + Indicate whether Fan is replaceable. + Returns: + bool: True if it is replaceable. + """ + return False + + def get_speed_tolerance(self): + """ + Retrieves the speed tolerance of the fan + Returns: + An integer, the percentage of variance from target speed which is + considered tolerable + """ + if self.get_presence(): + # The tolerance value is fixed as 20% for all the DellEMC platforms + tolerance = 20 + else: + tolerance = 0 + + return tolerance + + def set_status_led(self, color): + """ + Set led to expected color + Args: + color: A string representing the color with which to set the + fan status LED + Returns: + bool: True if set success, False if fail. + """ + # E3224F has led only on FanTray and not available for seperate fans + return True + + def get_status_led(self): + """ + Gets the current system LED color + + Returns: + A string that represents the supported color + """ + + return None + + def get_target_speed(self): + """ + Retrieves the target (expected) speed of the fan + Returns: + An integer, the percentage of full fan speed, in the range 0 (off) + to 100 (full speed) + """ + # Return current speed to avoid false thermalctld alarm. + return self.get_speed() + diff --git a/platform/broadcom/sonic-platform-modules-dell/e3224f/sonic_platform/fan_drawer.py b/platform/broadcom/sonic-platform-modules-dell/e3224f/sonic_platform/fan_drawer.py new file mode 100644 index 000000000000..a7619fa70b1f --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-dell/e3224f/sonic_platform/fan_drawer.py @@ -0,0 +1,158 @@ +#!/usr/bin/env python + +######################################################################## +# DellEMC E3224F +# +# Module contains an implementation of SONiC Platform Base API and +# provides the Fan-Drawers' information available in the platform. +# +######################################################################## + +try: + from sonic_platform_base.fan_drawer_base import FanDrawerBase + from sonic_platform.fan import Fan +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + +E3224F_FANS_PER_FANTRAY = 1 + + +class FanDrawer(FanDrawerBase): + """DellEMC Platform-specific Fan class""" + + FANTRAY_LED_COLORS = { + "off", + "green", + "yellow" + } + + def __init__(self, fantray_index): + + FanDrawerBase.__init__(self) + # FanTray is 1-based in DellEMC platforms + self.fantray_led_reg = "fan{}_led".format(fantray_index) + self.fantrayindex = fantray_index + 1 + for i in range(E3224F_FANS_PER_FANTRAY): + self._fan_list.append(Fan(fantray_index, i)) + + def _get_cpld_register(self, reg_name): + # On successful read, returns the value read from given + # reg name and on failure rethrns 'ERR' + cpld_dir = "/sys/devices/platform/dell-e3224f-cpld.0/" + cpld_reg_file = cpld_dir + '/' + reg_name + try: + rv = open(cpld_reg_file, 'r').read() + except IOError : return 'ERR' + return rv.strip('\r\n').lstrip(' ') + + def _set_cpld_register(self, reg_name, value): + # On successful write, returns the value will be written on + # reg_name and on failure returns 'ERR' + cpld_dir = "/sys/devices/platform/dell-e3224f-cpld.0/" + cpld_reg_file = cpld_dir + '/' + reg_name + + try: + with open(cpld_reg_file, 'w') as fd: + rv = fd.write(str(value)) + except Exception: + rv = 'ERR' + + return rv + + def get_name(self): + """ + Retrieves the fan drawer name + Returns: + string: The name of the device + """ + return "FanTray{}".format(self.fantrayindex) + + def get_status_led(self): + """ + Gets the current system LED color + + Returns: + A string that represents the supported color + """ + + color = self._get_cpld_register(self.fantray_led_reg) + + #if color not in list(self.FANTRAY_LED_COLORS): + # return self.sys_ledcolor + + return color + + def set_status_led(self,color): + """ + Set system LED status based on the color type passed in the argument. + Argument: Color to be set + Returns: + bool: True is specified color is set, Otherwise return False + """ + + if color not in list(self.FANTRAY_LED_COLORS): + return False + + if(not self._set_cpld_register(self.fantray_led_reg, color)): + return False + + return True + + def get_presence(self): + """ + Retrives the presence of the fan drawer + Returns: + bool: True if fan_tray is present, False if not + """ + return self.get_fan(0).get_presence() + + def get_model(self): + """ + Retrieves the part number of the fan drawer + Returns: + string: Part number of fan drawer + """ + return "NA" + + def get_serial(self): + """ + Retrieves the serial number of the fan drawer + Returns: + string: Serial number of the fan drawer + """ + return "NA" + + def get_status(self): + """ + Retrieves the operational status of the fan drawer + Returns: + bool: True if fan drawer is operating properly, False if not + """ + return True + + def get_position_in_parent(self): + """ + Retrieves 1-based relative physical position in parent device. + Returns: + integer: The 1-based relative physical position in parent + device or -1 if cannot determine the position + """ + return self.fantrayindex + + def is_replaceable(self): + """ + Indicate whether this fan drawer is replaceable. + Returns: + bool: True if it is replaceable, False if not + """ + return True + + def get_maximum_consumed_power(self): + """ + Retrives the maximum power drawn by Fan Drawer + + Returns: + A float, with value of the maximum consumable power of the + component. + """ + return 0.0 diff --git a/platform/broadcom/sonic-platform-modules-dell/e3224f/sonic_platform/platform.py b/platform/broadcom/sonic-platform-modules-dell/e3224f/sonic_platform/platform.py new file mode 100644 index 000000000000..996d94cf5a6e --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-dell/e3224f/sonic_platform/platform.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python + +############################################################################# +# +# Module contains an implementation of SONiC Platform Base API and +# provides the platform information +# +############################################################################# + +try: + from sonic_platform_base.platform_base import PlatformBase + from sonic_platform.chassis import Chassis +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + + +class Platform(PlatformBase): + """ + DELLEMC Platform-specific class + """ + + def __init__(self): + PlatformBase.__init__(self) + self._chassis = Chassis() diff --git a/platform/broadcom/sonic-platform-modules-dell/e3224f/sonic_platform/psu.py b/platform/broadcom/sonic-platform-modules-dell/e3224f/sonic_platform/psu.py new file mode 100644 index 000000000000..38118f6390cc --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-dell/e3224f/sonic_platform/psu.py @@ -0,0 +1,255 @@ +#!/usr/bin/env python + +######################################################################## +# DellEMC E3224F +# +# Module contains an implementation of SONiC Platform Base API and +# provides the PSUs' information which are available in the platform +# +######################################################################## + +try: + import os + from sonic_platform_base.psu_base import PsuBase + from sonic_platform.fan import Fan +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + + +class Psu(PsuBase): + """DellEMC Platform-specific PSU class""" + + def __init__(self, psu_index): + PsuBase.__init__(self) + self.index = psu_index + 1 # PSU is 1-based in DellEMC platforms + self.psu_presence_reg = "psu{}_prs".format(psu_index) + self.psu_status = "psu{}_status".format(psu_index) + self.eeprom = "/sys/bus/i2c/devices/{}-0056/eeprom".format(10+psu_index) + self.psu_voltage_reg = 'in3_input' + self.psu_current_reg = 'curr2_input' + self.psu_power_reg = 'power2_input' + self.dps_hwmon = "/sys/bus/i2c/devices/{}-005e/hwmon/".format(10 + psu_index) + self.dps_hwmon_exist = os.path.exists(self.dps_hwmon) + self._fan_list.append(Fan(fan_index=self.index, psu_fan=True, dependency=self)) + + def _get_cpld_register(self, reg_name): + # On successful read, returns the value read from given + # reg name and on failure rethrns 'ERR' + cpld_dir = "/sys/devices/platform/dell-e3224f-cpld.0/" + cpld_reg_file = cpld_dir + '/' + reg_name + try: + with open(cpld_reg_file, 'r') as fd: + rv = fd.read() + except IOError : return 'ERR' + return rv.strip('\r\n').lstrip(' ') + + def _get_dps_register(self, reg_name): + try : + dps_dir = self.dps_hwmon + '/' + os.listdir(self.dps_hwmon)[0] + dps_reg_file = dps_dir + '/' + reg_name + with open(dps_reg_file, 'r') as fd: + rv = fd.read() + except (IOError, OSError) : return 'ERR' + return rv + + def get_name(self): + """ + Retrieves the name of the device + + Returns: + string: The name of the device + """ + return "PSU{}".format(self.index) + + def _reload_dps_module(self): + try: + file = "/sys/bus/i2c/devices/i2c-{}/delete_device".format(10 + self.index - 1) + with open(file, 'w') as f: + f.write('0x56\n') + except (IOError, OSError): + pass + try: + file = "/sys/bus/i2c/devices/i2c-{}/delete_device".format(10 + self.index - 1) + with open(file, 'w') as f: + f.write('0x5e\n') + except (IOError, OSError): + pass + try: + file = "/sys/bus/i2c/devices/i2c-{}/new_device".format(10 + self.index - 1) + with open(file, 'w') as f: + f.write('24c02 0x56\n') + file = "/sys/bus/i2c/devices/i2c-{}/new_device".format(10 + self.index - 1) + with open(file, 'w') as f: + f.write('dps460 0x5e\n') + except (IOError, OSError): + pass + + def get_presence(self): + """ + Retrieves the presence of the Power Supply Unit (PSU) + + Returns: + bool: True if PSU is present, False if not + """ + presence = self._get_cpld_register(self.psu_presence_reg).strip() + if presence == 'ERR': + return False + + status = self.get_status() + if int(presence, 0) and status == False: + return int(presence, 0) + + if not self.dps_hwmon_exist and int(presence, 0): + self.dps_hwmon_exist = os.path.exists(self.dps_hwmon) + if not self.dps_hwmon_exist: + self._reload_dps_module() + if int(presence, 0) == 1: + return True + return False + + def get_model(self): + """ + Retrieves the part number of the PSU + + Returns: + string: Part number of PSU + """ + try: val = open(self.eeprom, "rb").read()[0x50:0x62] + except Exception: + val = None + return val.decode('ascii') + + def get_serial(self): + """ + Retrieves the serial number of the PSU + + Returns: + string: Serial number of PSU + """ + try: val = open(self.eeprom, "rb").read()[0xc4:0xd9] + except Exception: + val = None + return val.decode('ascii') + + def get_revision(self): + """ + Retrieves the serial number of the PSU + + Returns: + string: Serial number of PSU + """ + try: val = open(self.eeprom, "rb").read()[0xc4:0xd9] + except Exception: + val = None + if val != "NA" and len(val) == 23: + return val[-3:] + else: + return "NA" + + def get_status(self): + """ + Retrieves the operational status of the PSU + + Returns: + bool: True if PSU is operating properly, False if not + """ + status = self._get_cpld_register(self.psu_status).strip() + if status == 'ERR' : return False + if int(status, 0) == 1: + return True + return False + + def get_voltage(self): + """ + Retrieves current PSU voltage output + + Returns: + A float number, the output voltage in volts, + e.g. 12.1 + """ + volt_reading = self._get_dps_register(self.psu_voltage_reg) + try: + voltage = int(volt_reading)/1000 + except Exception: + return None + return float(voltage) + + def get_current(self): + """ + Retrieves present electric current supplied by PSU + + Returns: + A float number, electric current in amperes, + e.g. 15.4 + """ + curr_reading = self._get_dps_register(self.psu_current_reg) + try: + current = int(curr_reading)/1000 + except Exception: + return None + return float(current) + + def get_power(self): + """ + Retrieves current energy supplied by PSU + + Returns: + A float number, the power in watts, + e.g. 302.6 + """ + power_reading = self._get_dps_register(self.psu_power_reg) + try: + power = int(power_reading)/(1000*1000) + except Exception: + return None + return float(power) + + def get_powergood_status(self): + """ + Retrieves the powergood status of PSU + + Returns: + A boolean, True if PSU has stablized its output voltages and + passed all its internal self-tests, False if not. + """ + power_good = self._get_cpld_register(self.psu_status).strip() + if power_good == 'ERR' : return False + return int(power_good, 0) + + def get_mfr_id(self): + """ + Retrives the Manufacturer Id of PSU + + Returns: + A string, the manunfacturer id. + """ + return 'DELTA' + + def get_type(self): + """ + Retrives the Power Type of PSU + + Returns : + A string, PSU power type + """ + try: val = open(self.eeprom, "rb").read()[0xe8:0xea] + except Exception: + return None + return val.decode() + def get_position_in_parent(self): + """ + Retrieves 1-based relative physical position in parent device. + Returns: + integer: The 1-based relative physical position in parent + device or -1 if cannot determine the position + """ + return self.index + + def is_replaceable(self): + """ + Indicate whether this PSU is replaceable. + Returns: + bool: True if it is replaceable. + """ + return True + diff --git a/platform/broadcom/sonic-platform-modules-dell/e3224f/sonic_platform/sfp.py b/platform/broadcom/sonic-platform-modules-dell/e3224f/sonic_platform/sfp.py new file mode 100644 index 000000000000..9b76465f30fe --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-dell/e3224f/sonic_platform/sfp.py @@ -0,0 +1,343 @@ +#!/usr/bin/env python + +############################################################################# +# DELLEMC E3224F +# +# Module contains an implementation of SONiC Platform Base API and +# provides the platform information +# +############################################################################# + +try: + import os + import struct + import mmap + from sonic_platform_base.sonic_xcvr.sfp_optoe_base import SfpOptoeBase + +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + +SFP_PORT_START = 1 +SFP_PORT_END = 24 +SFPPLUS_PORT_START = 25 +SFPPLUS_PORT_END = 28 +PORT_END = 30 + +QSFP_INFO_OFFSET = 128 +SFP_INFO_OFFSET = 0 +QSFP_DD_PAGE0 = 0 + +SFP_TYPE_LIST = [ + '0x3' # SFP/SFP+/SFP28 and later +] +QSFP_TYPE_LIST = [ + '0xc', # QSFP + '0xd', # QSFP+ or later + '0x11' # QSFP28 or later +] +QSFP_DD_TYPE_LIST = [ + '0x18' #QSFP_DD Type +] + +class Sfp(SfpOptoeBase): + """ + DELLEMC Platform-specific Sfp class + """ + + _port_to_i2c_mapping = { + 1: 27, + 2: 28, + 3: 29, + 4: 30, + 5: 31, + 6: 32, + 7: 33, + 8: 34, + 9: 35, + 10: 36, + 11: 37, + 12: 38, + 13: 39, + 14: 40, + 15: 41, + 16: 42, + 17: 43, + 18: 44, + 19: 45, + 20: 46, + 21: 47, + 22: 48, + 23: 49, + 24: 50, + 25: 20, + 26: 21, + 27: 22, + 28: 23, + 29: 24, + 30: 25, + } + + def __init__(self, index, sfp_type, eeprom_path): + SfpOptoeBase.__init__(self) + self.sfp_type = sfp_type + self.port_type = sfp_type + self.index = index + self.eeprom_path = eeprom_path + self._initialize_media(delay=False) + + def get_eeprom_path(self): + return self.eeprom_path + + def get_name(self): + if not (self.index >= SFP_PORT_START and self.index <= PORT_END): + return "N/A" + if self.index <= SFP_PORT_END: + return "SFP8" + elif self.index <= SFPPLUS_PORT_END: + return "SFP/SFP+/SFP28" + else: + return "QSFP or later" + + def _initialize_media(self,delay=False): + """ + Initialize the media type and eeprom driver for SFP + """ + if delay: + time.sleep(1) + self._xcvr_api = None + self.get_xcvr_api() + + self.set_media_type() + self.reinit_sfp_driver() + + def set_media_type(self): + """ + Reads optic eeprom byte to determine media type inserted + """ + eeprom_raw = [] + eeprom_raw = self._xcvr_api_factory._get_id() + if eeprom_raw is not None: + eeprom_raw = hex(eeprom_raw) + if eeprom_raw in SFP_TYPE_LIST: + self.sfp_type = 'SFP' + elif eeprom_raw in QSFP_TYPE_LIST: + self.sfp_type = 'QSFP' + elif eeprom_raw in QSFP_DD_TYPE_LIST: + self.sfp_type = 'QSFP_DD' + else: + #Set native port type if EEPROM type is not recognized/readable + self.sfp_type = self.port_type + else: + self.sfp_type = self.port_type + + return self.sfp_type + + def reinit_sfp_driver(self): + """ + Changes the driver based on media type detected + """ + del_sfp_path = "/sys/class/i2c-adapter/i2c-{0}/delete_device".format(self._port_to_i2c_mapping[self.index]) + new_sfp_path = "/sys/class/i2c-adapter/i2c-{0}/new_device".format(self._port_to_i2c_mapping[self.index]) + driver_path = "/sys/class/i2c-adapter/i2c-{0}/{0}-0050/name".format(self._port_to_i2c_mapping[self.index]) + + if not os.path.isfile(driver_path): + print(driver_path, "does not exist") + return False + + try: + with os.fdopen(os.open(driver_path, os.O_RDONLY)) as fd: + driver_name = fd.read() + driver_name = driver_name.rstrip('\r\n') + driver_name = driver_name.lstrip(" ") + + #Avoid re-initialization of the QSFP/SFP optic on QSFP/SFP port. + if self.sfp_type == 'SFP' and driver_name in ['optoe1', 'optoe3']: + with open(del_sfp_path, 'w') as f: + f.write('0x50\n') + time.sleep(0.2) + with open(new_sfp_path, 'w') as f: + f.write('optoe2 0x50\n') + time.sleep(2) + elif self.sfp_type == 'QSFP' and driver_name in ['optoe2', 'optoe3']: + with open(del_sfp_path, 'w') as f: + f.write('0x50\n') + time.sleep(0.2) + with open(new_sfp_path, 'w') as f: + f.write('optoe1 0x50\n') + time.sleep(2) + elif self.sfp_type == 'QSFP_DD' and driver_name in ['optoe1', 'optoe2']: + with open(del_sfp_path, 'w') as f: + f.write('0x50\n') + time.sleep(0.2) + with open(new_sfp_path, 'w') as f: + f.write('optoe3 0x50\n') + time.sleep(2) + + except IOError as e: + print("Error: Unable to open file: %s" % str(e)) + return False + + def get_position_in_parent(self): + """ + Retrieves 1-based relative physical position in parent device. + Returns: + integer: The 1-based relative physical position in parent + device or -1 if cannot determine the position + """ + return self.index + + def _get_cpld_register(self, reg): + reg_file = '/sys/devices/platform/dell-e3224f-cpld.0/' + reg + try: + with open(reg_file, 'r') as fd: + rv = fd.read() + except IOError : return 'ERR' + return rv.strip('\r\n').lstrip(' ') + + def _set_cpld_register(self, reg_name, value): + # On successful write, returns the value will be written on + # reg_name and on failure returns 'ERR' + + cpld_dir = "/sys/devices/platform/dell-e3224f-cpld.0/" + cpld_reg_file = cpld_dir + '/' + reg_name + + try: + with open(cpld_reg_file, 'w') as fd: + rv = fd.write(str(value)) + except Exception: + rv = 'ERR' + + return rv + + def get_presence(self): + """ + Retrieves the presence of the sfp + Returns : True if sfp is present and false if it is absent + """ + # Check for invalid port_num + presence = False + if not (self.index >= SFP_PORT_START and self.index <= PORT_END): + return presence + try: + if self.index <= SFP_PORT_END: + bit_mask = 1 << (self.index - SFP_PORT_START) + sfp_mod_prs = self._get_cpld_register('sfp_modprs') + if sfp_mod_prs == 'ERR': + return presence + presence = ((int(sfp_mod_prs, 16) & bit_mask) == 0) + elif self.index <= SFPPLUS_PORT_END: + bit_mask = 1 << (self.index - SFPPLUS_PORT_START) + sfpplus_mod_prs = self._get_cpld_register('sfpplus_modprs') + if sfpplus_mod_prs == 'ERR': + return presence + presence = ((int(sfpplus_mod_prs, 16) & bit_mask) == 0) + else: + bit_mask = (1 << (self.index - (SFPPLUS_PORT_START+4))) + qsfp_mod_prs = self._get_cpld_register('qsfp_modprs') + if qsfp_mod_prs == 'ERR': + return presence + presence = ((int(qsfp_mod_prs, 16) & bit_mask) == 0) + except TypeError: + pass + return presence + + def tx_disable(self, tx_disable): + """ + Enable/Disable the TX disable bit of the optics. + """ + rval = False + if not (self.index >= SFP_PORT_START and self.index <= SFPPLUS_PORT_END): + return rval + if self.sfp_type == 'SFP': + if self.index <= SFP_PORT_END: + sfp_txdis = int(self._get_cpld_register('sfp_txdis'), 16) + if sfp_txdis != 'ERR': + bit_mask = 1 << (self.index - SFP_PORT_START) + sfp_txdis = sfp_txdis | bit_mask if tx_disable \ + else sfp_txdis & ~bit_mask + rval = (self._set_cpld_register('sfp_txdis', sfp_txdis) != 'ERR') + elif self.index <= SFPPLUS_PORT_END: + sfpplus_txdis = int(self._get_cpld_register('sfpplus_txdis'), 16) + if sfpplus_txdis != 'ERR': + bit_mask = 1 << (self.index - SFPPLUS_PORT_START) + sfpplus_txdis = sfpplus_txdis | bit_mask if tx_disable \ + else sfpplus_txdis & ~bit_mask + rval = (self._set_cpld_register('sfpplus_txdis', sfpplus_txdis) != 'ERR') + return rval + + def get_reset_status(self): + """ + Retrives the reset status of SFP + """ + reset_status = False + return reset_status + + def get_lpmode(self): + """ + Retrieves the lpmode(low power mode) of this SFP + """ + lpmode_state = False + return lpmode_state + + def reset(self): + """ + Reset the SFP and returns all user settings to their default state + """ + return False + + def set_lpmode(self, lpmode): + """ + Sets the lpmode(low power mode) of this SFP + """ + return True + + def get_status(self): + """ + Retrieves the operational status of the device + """ + reset = self.get_reset_status() + return (not reset) + + def get_max_port_power(self): + """ + Retrieves the maximumum power allowed on the port in watts + """ + return 5.0 if self.sfp_type == 'QSFP' else 2.5 + + def is_replaceable(self): + """ + Indicate whether this device is replaceable. + Returns: + bool: True if it is replaceable. + """ + return True + + def get_error_description(self): + """ + Retrives the error descriptions of the SFP module + Returns: + String that represents the current error descriptions of vendor specific errors + In case there are multiple errors, they should be joined by '|', + like: "Bad EEPROM|Unsupported cable" + """ + if not self.get_presence(): + return self.SFP_STATUS_UNPLUGGED + else: + if not os.path.isfile(self.eeprom_path): + return "EEPROM driver is not attached" + + if self.sfp_type == 'SFP': + offset = SFP_INFO_OFFSET + elif self.sfp_type == 'QSFP': + offset = QSFP_INFO_OFFSET + elif self.sfp_type == 'QSFP_DD': + offset = QSFP_DD_PAGE0 + + try: + with open(self.eeprom_path, mode="rb", buffering=0) as eeprom: + eeprom.seek(offset) + eeprom.read(1) + except OSError as e: + return "EEPROM read failed ({})".format(e.strerror) + + return self.SFP_STATUS_OK diff --git a/platform/broadcom/sonic-platform-modules-dell/e3224f/sonic_platform/thermal.py b/platform/broadcom/sonic-platform-modules-dell/e3224f/sonic_platform/thermal.py new file mode 100644 index 000000000000..f9e547e05525 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-dell/e3224f/sonic_platform/thermal.py @@ -0,0 +1,163 @@ +#!/usr/bin/env python + +######################################################################## +# DellEMC E3224F +# +# Module contains an implementation of SONiC Platform Base API and +# provides the Thermals' information which are available in the platform +# +######################################################################## + + +try: + import os + from sonic_platform_base.thermal_base import ThermalBase +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + + +class Thermal(ThermalBase): + """DellEMC Platform-specific Thermal class""" + + # [ Sensor-Name, Sensor-ID ] + SENSOR_MAPPING = [ + ['Switch Near Temperature', '7-0049'], + ['Switch Rear Temperature', '7-004a'], + ['Front Panel PHY Temperature', '7-004b'], + ['Near Front Panel Temperature', '7-004c'], + ['Middle Fan Tray Temperature', '7-004f'], + ] + + def __init__(self, thermal_index): + ThermalBase.__init__(self) + self.index = thermal_index + 1 + temp_hwmon = '/sys/bus/i2c/devices/' + self.SENSOR_MAPPING[thermal_index][1] + '/hwmon' + self.temp_file = temp_hwmon + '/' + os.listdir(temp_hwmon)[0] + '/' + 'temp1_input' + + def get_name(self): + """ + Retrieves the name of the thermal + + Returns: + string: The name of the thermal + """ + return self.SENSOR_MAPPING[self.index - 1][0] + + def get_presence(self): + """ + Retrieves the presence of the thermal + + Returns: + bool: True if thermal is present, False if not + """ + return True + + def get_model(self): + """ + Retrieves the model number (or part number) of the Thermal + + Returns: + string: Model/part number of Thermal + """ + return 'NA' + + def get_serial(self): + """ + Retrieves the serial number of the Thermal + + Returns: + string: Serial number of Thermal + """ + return 'NA' + + def get_status(self): + """ + Retrieves the operational status of the thermal + + Returns: + A boolean value, True if thermal is operating properly, + False if not + """ + return True + + def get_temperature(self): + """ + Retrieves current temperature reading from thermal + + Returns: + A float number of current temperature in Celsius up to + nearest thousandth of one degree Celsius, e.g. 30.125 + """ + temperature = 0.0 + try : + temperature = float(open(self.temp_file).read()) / 1000.0 + except Exception: + pass + return float(temperature) + + def get_high_threshold(self): + """ + Retrieves the high threshold temperature of thermal + + Returns: + A float number, the high threshold temperature of thermal in + Celsius up to nearest thousandth of one degree Celsius, + e.g. 30.125 + """ + return 75.0 + + def get_low_threshold(self): + """ + Retrieves the low threshold temperature of thermal + + Returns: + A float number, the low threshold temperature of thermal in + Celsius up to nearest thousandth of one degree Celsius, + e.g. 30.125 + """ + return 0.0 + + def set_high_threshold(self, temperature): + """ + Sets the high threshold temperature of thermal + + Args : + temperature: A float number up to nearest thousandth of one + degree Celsius, e.g. 30.125 + Returns: + A boolean, True if threshold is set successfully, False if + not + """ + # Thermal threshold values are pre-defined based on HW. + return False + + def set_low_threshold(self, temperature): + """ + Sets the low threshold temperature of thermal + + Args : + temperature: A float number up to nearest thousandth of one + degree Celsius, e.g. 30.125 + Returns: + A boolean, True if threshold is set successfully, False if + not + """ + # Thermal threshold values are pre-defined based on HW. + return False + + def get_position_in_parent(self): + """ + Retrieves 1-based relative physical position in parent device. + Returns: + integer: The 1-based relative physical position in parent + device or -1 if cannot determine the position + """ + return self.index + + def is_replaceable(self): + """ + Indicate whether this Thermal is replaceable. + Returns: + bool: True if it is replaceable. + """ + return False diff --git a/platform/broadcom/sonic-platform-modules-dell/e3224f/sonic_platform/watchdog.py b/platform/broadcom/sonic-platform-modules-dell/e3224f/sonic_platform/watchdog.py new file mode 100644 index 000000000000..15aa40c4eb54 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-dell/e3224f/sonic_platform/watchdog.py @@ -0,0 +1,207 @@ +#!/usr/bin/env python + +######################################################################## +# +# DELLEMC E3224F +# +# Abstract base class for implementing a platform-specific class with +# which to interact with a hardware watchdog module in SONiC +# +######################################################################## + +try: + import ctypes + from sonic_platform_base.watchdog_base import WatchdogBase +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + + +class _timespec(ctypes.Structure): + _fields_ = [ + ('tv_sec', ctypes.c_long), + ('tv_nsec', ctypes.c_long) + ] + + +class Watchdog(WatchdogBase): + """ + Abstract base class for interfacing with a hardware watchdog module + """ + + TIMERS = [15,20,30,40,50,60,65,70,80,100,120,140,160,180,210,240] + + armed_time = 0 + timeout = 0 + CLOCK_MONOTONIC = 1 + + def __init__(self): + WatchdogBase.__init__(self) + self._librt = ctypes.CDLL('librt.so.1', use_errno=True) + self._clock_gettime = self._librt.clock_gettime + self._clock_gettime.argtypes=[ctypes.c_int, ctypes.POINTER(_timespec)] + self.watchdog_reg = "watchdog" + + def _get_cpld_register(self, reg_name): + # On successful read, returns the value read from given + # reg name and on failure rethrns 'ERR' + cpld_dir = "/sys/devices/platform/dell-e3224f-cpld.0/" + cpld_reg_file = cpld_dir + '/' + reg_name + try: + with open(cpld_reg_file, 'r') as fd: + rv = fd.read() + except IOError : return 'ERR' + return rv.strip('\r\n').lstrip(' ') + + def _set_cpld_register(self, reg_name, value): + # On successful write, returns the value will be written on + # reg_name and on failure returns 'ERR' + + cpld_dir = "/sys/devices/platform/dell-e3224f-cpld.0/" + cpld_reg_file = cpld_dir + '/' + reg_name + + try: + with open(cpld_reg_file, 'w') as fd: + rv = fd.write(str(value)) + except Exception: + rv = 'ERR' + + return rv + + def _get_reg_val(self): + value = self._get_cpld_register(self.watchdog_reg).strip() + if value == 'ERR': return False + + return int(value,16) + + def _set_reg_val(self,val): + value = self._set_cpld_register(self.watchdog_reg, val) + return value + + def _get_time(self): + """ + To get clock monotonic time + """ + ts = _timespec() + if self._clock_gettime(self.CLOCK_MONOTONIC, ctypes.pointer(ts)) != 0: + self._errno = ctypes.get_errno() + return 0 + return ts.tv_sec + ts.tv_nsec * 1e-9 + + def arm(self, seconds): + """ + Arm the hardware watchdog with a timeout of seconds. + If the watchdog is currently armed, calling this function will + simply reset the timer to the provided value. If the underlying + hardware does not support the value provided in , this + method should arm the watchdog with the *next greater* + available value. + + Returns: + An integer specifying the *actual* number of seconds the + watchdog was armed with. On failure returns -1. + """ + timer_offset = -1 + for key,timer_seconds in enumerate(self.TIMERS): + if seconds > 0 and seconds <= timer_seconds: + timer_offset = key + seconds = timer_seconds + break + + if timer_offset == -1: + return -1 + + # Extracting 5th to 8th bits for WD timer values + reg_val = self._get_reg_val() + wd_timer_offset = (reg_val >> 4) & 0xF + + if wd_timer_offset != timer_offset: + # Setting 5th to 8th bits + # value from timer_offset + self.disarm() + self._set_reg_val((reg_val & 0x0F) | (timer_offset << 4)) + + if self.is_armed(): + # Setting last bit to WD Timer punch + # Last bit = WD Timer punch + self._set_reg_val(reg_val & 0xFE) + + else: + # Setting 4th bit to enable WD + # 4th bit = Enable WD + reg_val = self._get_reg_val() + self._set_reg_val(reg_val | 0x8) + + self.armed_time = self._get_time() + self.timeout = seconds + return seconds + + def disarm(self): + """ + Disarm the hardware watchdog + + Returns: + A boolean, True if watchdog is disarmed successfully, False + if not + """ + if self.is_armed(): + # Setting 4th bit to disable WD + # 4th bit = Disable WD + reg_val = self._get_reg_val() + self._set_reg_val(reg_val & 0xF7) + + self.armed_time = 0 + self.timeout = 0 + return True + + return False + + def is_armed(self): + """ + Retrieves the armed state of the hardware watchdog. + + Returns: + A boolean, True if watchdog is armed, False if not + """ + + # Extracting 4th bit to get WD Enable/Disable status + # 0 - Disabled WD + # 1 - Enabled WD + reg_val = self._get_reg_val() + wd_offset = (reg_val >> 3) & 1 + + return bool(wd_offset) + + def get_remaining_time(self): + """ + If the watchdog is armed, retrieve the number of seconds + remaining on the watchdog timer + + Returns: + An integer specifying the number of seconds remaining on + their watchdog timer. If the watchdog is not armed, returns + -1. + + E3224F doesnot have hardware support to show remaining time. + Due to this limitation, this API is implemented in software. + This API would return correct software time difference if it + is called from the process which armed the watchdog timer. + If this API called from any other process, it would return + 0. If the watchdog is not armed, this API would return -1. + """ + if not self.is_armed(): + return -1 + + if self.armed_time > 0 and self.timeout != 0: + cur_time = self._get_time() + + if cur_time <= 0: + return 0 + + diff_time = int(cur_time - self.armed_time) + + if diff_time > self.timeout: + return self.timeout + else: + return self.timeout - diff_time + + return 0 diff --git a/platform/broadcom/sonic-platform-modules-dell/e3224f/systemd/mux-ctrl.service b/platform/broadcom/sonic-platform-modules-dell/e3224f/systemd/mux-ctrl.service new file mode 100644 index 000000000000..20530424d35e --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-dell/e3224f/systemd/mux-ctrl.service @@ -0,0 +1,13 @@ +[Unit] +Description=Dell E3224F Platform mux ctrl +Before=pmon.service +After=platform-modules-e3224f.service +DefaultDependencies=no + +[Service] +Type=oneshot +ExecStart=/usr/local/bin/mux_controller.sh +RemainAfterExit=yes + +[Install] +WantedBy=multi-user.target diff --git a/platform/broadcom/sonic-platform-modules-dell/e3224f/systemd/platform-modules-e3224f.service b/platform/broadcom/sonic-platform-modules-dell/e3224f/systemd/platform-modules-e3224f.service new file mode 100644 index 000000000000..66b90132ecee --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-dell/e3224f/systemd/platform-modules-e3224f.service @@ -0,0 +1,14 @@ +[Unit] +Description=Dell E3224F Platform modules +Before=pmon.service +After=platform-init.service +DefaultDependencies=no + +[Service] +Type=oneshot +ExecStart=/usr/local/bin/e3224f_platform.sh init +ExecStop=/usr/local/bin/e3224f_platform.sh deinit +RemainAfterExit=yes + +[Install] +WantedBy=multi-user.target diff --git a/platform/broadcom/sonic-platform-modules-dell/s5224f/sonic_platform/fan.py b/platform/broadcom/sonic-platform-modules-dell/s5224f/sonic_platform/fan.py index 57e163469a95..b67f6acea657 100644 --- a/platform/broadcom/sonic-platform-modules-dell/s5224f/sonic_platform/fan.py +++ b/platform/broadcom/sonic-platform-modules-dell/s5224f/sonic_platform/fan.py @@ -71,8 +71,7 @@ def __init__(self, fantray_index=1, fan_index=1, psu_fan=False, self.fru = IpmiFru(self.PSU_FRU_MAPPING[self.fanindex]) self.max_speed_offset = PSU_FAN_MAX_SPEED_OFFSET self.fan_direction_offset = PSU_FAN_DIRECTION_OFFSET - self.max_speed = self.fru.get_fru_data(self.max_speed_offset,2)[1] - self.max_speed = self.max_speed[1] << 8 | self.max_speed[0] + self.max_speed = 0 def get_name(self): """ @@ -163,11 +162,14 @@ def get_speed(self): int: percentage of the max fan speed """ if self.max_speed == 0: - self.max_speed = self.fru.get_fru_data(self.max_speed_offset,2)[1] - self.max_speed = self.max_speed[1] << 8 | self.max_speed[0] + is_valid, max_speed = self.fru.get_fru_data(self.max_speed_offset,2) + if not is_valid: + return 0 + self.max_speed = max_speed[1] + self.max_speed = max_speed[1] << 8 | max_speed[0] is_valid, fan_speed = self.speed_sensor.get_reading() if not is_valid or self.max_speed == 0: - return None + speed = 0 else: speed = (100 * fan_speed)//self.max_speed return speed diff --git a/platform/broadcom/sonic-platform-modules-dell/s5232f/sonic_platform/fan.py b/platform/broadcom/sonic-platform-modules-dell/s5232f/sonic_platform/fan.py index c634dc7d0d17..2b37bd3783d2 100644 --- a/platform/broadcom/sonic-platform-modules-dell/s5232f/sonic_platform/fan.py +++ b/platform/broadcom/sonic-platform-modules-dell/s5232f/sonic_platform/fan.py @@ -69,8 +69,7 @@ def __init__(self, fantray_index=1, fan_index=1, psu_fan=False, self.fru = IpmiFru(self.PSU_FRU_MAPPING[self.fanindex]) self.max_speed_offset = PSU_FAN_MAX_SPEED_OFFSET self.fan_direction_offset = PSU_FAN_DIRECTION_OFFSET - self.max_speed = self.fru.get_fru_data(self.max_speed_offset,2)[1] - self.max_speed = self.max_speed[1] << 8 | self.max_speed[0] + self.max_speed = 0 def get_name(self): """ @@ -163,8 +162,11 @@ def get_speed(self): int: percentage of the max fan speed """ if self.max_speed == 0: - self.max_speed = self.fru.get_fru_data(self.max_speed_offset,2)[1] - self.max_speed = self.max_speed[1] << 8 | self.max_speed[0] + is_valid, max_speed = self.fru.get_fru_data(self.max_speed_offset,2) + if not is_valid: + return 0 + self.max_speed = max_speed[1] + self.max_speed = max_speed[1] << 8 | max_speed[0] is_valid, fan_speed = self.speed_sensor.get_reading() if not is_valid or self.max_speed == 0: speed = 0 diff --git a/platform/broadcom/sonic-platform-modules-dell/s5248f/sonic_platform/fan.py b/platform/broadcom/sonic-platform-modules-dell/s5248f/sonic_platform/fan.py index 55327d5ddf58..a9b0fcc4b2f7 100644 --- a/platform/broadcom/sonic-platform-modules-dell/s5248f/sonic_platform/fan.py +++ b/platform/broadcom/sonic-platform-modules-dell/s5248f/sonic_platform/fan.py @@ -71,8 +71,7 @@ def __init__(self, fantray_index=1, fan_index=1, psu_fan=False, self.fru = IpmiFru(self.PSU_FRU_MAPPING[self.fanindex]) self.max_speed_offset = PSU_FAN_MAX_SPEED_OFFSET self.fan_direction_offset = PSU_FAN_DIRECTION_OFFSET - self.max_speed = self.fru.get_fru_data(self.max_speed_offset,2)[1] - self.max_speed = self.max_speed[1] << 8 | self.max_speed[0] + self.max_speed = 0 def get_name(self): """ @@ -165,11 +164,14 @@ def get_speed(self): int: percentage of the max fan speed """ if self.max_speed == 0: - self.max_speed = self.fru.get_fru_data(self.max_speed_offset,2)[1] - self.max_speed = self.max_speed[1] << 8 | self.max_speed[0] + is_valid, max_speed = self.fru.get_fru_data(self.max_speed_offset,2) + if not is_valid: + return 0 + self.max_speed = max_speed[1] + self.max_speed = max_speed[1] << 8 | max_speed[0] is_valid, fan_speed = self.speed_sensor.get_reading() if not is_valid or self.max_speed == 0: - return None + speed = 0 else: speed = (100 * fan_speed)//self.max_speed return speed diff --git a/platform/broadcom/sonic-platform-modules-dell/s6100/scripts/iSMART_64 b/platform/broadcom/sonic-platform-modules-dell/s6100/scripts/iSMART_64 index e485a6ee104e..0b5cb66bd1ab 100755 Binary files a/platform/broadcom/sonic-platform-modules-dell/s6100/scripts/iSMART_64 and b/platform/broadcom/sonic-platform-modules-dell/s6100/scripts/iSMART_64 differ diff --git a/platform/broadcom/sonic-platform-modules-dell/z9264f/sonic_platform/fan.py b/platform/broadcom/sonic-platform-modules-dell/z9264f/sonic_platform/fan.py index b7d990877daa..f9dacc94d9de 100644 --- a/platform/broadcom/sonic-platform-modules-dell/z9264f/sonic_platform/fan.py +++ b/platform/broadcom/sonic-platform-modules-dell/z9264f/sonic_platform/fan.py @@ -71,8 +71,7 @@ def __init__(self, fantray_index=1, fan_index=1, psu_fan=False, self.fru = IpmiFru(self.PSU_FRU_MAPPING[self.fanindex]) self.max_speed_offset = PSU_FAN_MAX_SPEED_OFFSET self.fan_direction_offset = PSU_FAN_DIRECTION_OFFSET - self.max_speed = self.fru.get_fru_data(self.max_speed_offset,2)[1] - self.max_speed = self.max_speed[1] << 8 | self.max_speed[0] + self.max_speed = 0 def get_name(self): """ @@ -165,8 +164,11 @@ def get_speed(self): int: percentage of the max fan speed """ if self.max_speed == 0: - self.max_speed = self.fru.get_fru_data(self.max_speed_offset,2)[1] - self.max_speed = self.max_speed[1] << 8 | self.max_speed[0] + is_valid, max_speed = self.fru.get_fru_data(self.max_speed_offset,2) + if not is_valid: + return 0 + self.max_speed = max_speed[1] + self.max_speed = max_speed[1] << 8 | max_speed[0] is_valid, fan_speed = self.speed_sensor.get_reading() if not is_valid or self.max_speed == 0: speed = 0 diff --git a/platform/broadcom/sonic-platform-modules-dell/z9432f/sonic_platform/fan.py b/platform/broadcom/sonic-platform-modules-dell/z9432f/sonic_platform/fan.py index b95b4d070ae0..a928d559cbfa 100644 --- a/platform/broadcom/sonic-platform-modules-dell/z9432f/sonic_platform/fan.py +++ b/platform/broadcom/sonic-platform-modules-dell/z9432f/sonic_platform/fan.py @@ -165,8 +165,11 @@ def get_speed(self): int: percentage of the max fan speed """ if self.max_speed == 0: - self.max_speed = self.fru.get_fru_data(self.max_speed_offset, 2)[1] - self.max_speed = self.max_speed[1] << 8 | self.max_speed[0] + is_valid, max_speed = self.fru.get_fru_data(self.max_speed_offset, 2) + if not is_valid: + return 0 + self.max_speed = max_speed[1] + self.max_speed = max_speed[1] << 8 | max_speed[0] is_valid, fan_speed = self.speed_sensor.get_reading() if not is_valid or self.max_speed == 0: return None diff --git a/platform/broadcom/sonic-platform-modules-ragile/LICENSE b/platform/broadcom/sonic-platform-modules-ragile/LICENSE old mode 100755 new mode 100644 index d37122689f3e..5681cac34476 --- a/platform/broadcom/sonic-platform-modules-ragile/LICENSE +++ b/platform/broadcom/sonic-platform-modules-ragile/LICENSE @@ -1,5 +1,4 @@ Copyright (C) 2016 Microsoft, Inc -Copyright (C) 2018 Ragile Network Corporation This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/Makefile b/platform/broadcom/sonic-platform-modules-ragile/common/Makefile index 6daf3d2b2fd1..578d65b3bf3e 100755 --- a/platform/broadcom/sonic-platform-modules-ragile/common/Makefile +++ b/platform/broadcom/sonic-platform-modules-ragile/common/Makefile @@ -9,33 +9,34 @@ SUB_BUILD_DIR = $(PWD)/build DIR_KERNEL_SRC = $(PWD)/modules SCRIPT_DIR = $(PWD)/script SERVICE_DIR = $(PWD)/service -DEPMOD_CONF_DIR = $(PWD)/depmod_conf +BLACK_DRIVER_CONF_DIR = $(PWD)/modprobe_conf -KBUILD_EXTRA_SYMBOLS += $(DIR_KERNEL_SRC)/Module.symvers -export KBUILD_EXTRA_SYMBOLS +app_dir = $(PWD)/app +app_build_dir = $(app_dir)/build +modules_build_dir = $(DIR_KERNEL_SRC)/build INSTALL_MODULE_DIR = $(SUB_BUILD_DIR)/$(KERNEL_SRC)/$(INSTALL_MOD_DIR) INSTALL_SCRIPT_DIR = $(SUB_BUILD_DIR)/usr/local/bin INSTALL_SERVICE_DIR = $(SUB_BUILD_DIR)/lib/systemd/system -INSTALL_LIB_DIR = $(SUB_BUILD_DIR)/usr/lib/python3.7/dist-packages -INSTALL_DEPMOD_CONF = $(SUB_BUILD_DIR)/etc/depmod.d +INSTALL_LIB_DIR = $(SUB_BUILD_DIR)/usr/lib/python3/dist-packages +INSTALL_BLACK_DRIVER = $(SUB_BUILD_DIR)/etc/modprobe.d all: - $(MAKE) -C $(KERNEL_SRC)/build M=$(DIR_KERNEL_SRC) modules + $(MAKE) -C $(app_dir) + $(MAKE) -C $(DIR_KERNEL_SRC) @if [ ! -d ${INSTALL_MODULE_DIR} ]; then mkdir -p ${INSTALL_MODULE_DIR} ;fi @if [ ! -d ${INSTALL_SCRIPT_DIR} ]; then mkdir -p ${INSTALL_SCRIPT_DIR} ;fi @if [ ! -d ${INSTALL_SERVICE_DIR} ]; then mkdir -p ${INSTALL_SERVICE_DIR} ;fi @if [ ! -d ${INSTALL_LIB_DIR} ]; then mkdir -p ${INSTALL_LIB_DIR} ;fi @if [ -d $(PWD)/lib/ ]; then cp -r $(PWD)/lib/* ${INSTALL_LIB_DIR} ;fi - @if [ -d $(PWD)/lib/ ]; then cp -r $(PWD)/lib/* ${INSTALL_LIB_DIR2} ;fi - @if [ ! -d ${INSTALL_DEPMOD_CONF} ]; then mkdir -p ${INSTALL_DEPMOD_CONF} ;fi - cp -r $(DEPMOD_CONF_DIR)/* $(INSTALL_DEPMOD_CONF) - cp -r $(DIR_KERNEL_SRC)/*.ko $(INSTALL_MODULE_DIR) + @if [ -d $(PWD)/sonic_platform/ ]; then cp -rf $(PWD)/sonic_platform ${INSTALL_LIB_DIR} ;fi + cp -r $(app_build_dir)/module/*.ko $(INSTALL_MODULE_DIR) + cp -r $(modules_build_dir)/*.ko $(INSTALL_MODULE_DIR) + cp -r $(app_dir)/build/app/* $(INSTALL_SCRIPT_DIR) cp -r $(SCRIPT_DIR)/* $(INSTALL_SCRIPT_DIR) cp -r $(SERVICE_DIR)/* $(INSTALL_SERVICE_DIR) @if [ -d $(INSTALL_SCRIPT_DIR) ]; then chmod +x $(INSTALL_SCRIPT_DIR)/* ;fi + @if [ ! -d ${INSTALL_BLACK_DRIVER} ]; then mkdir -p ${INSTALL_BLACK_DRIVER} ;fi + cp -r $(BLACK_DRIVER_CONF_DIR)/* $(INSTALL_BLACK_DRIVER) clean: - rm -f ${DIR_KERNEL_SRC}/*.o ${DIR_KERNEL_SRC}/*.ko ${DIR_KERNEL_SRC}/*.mod.c ${DIR_KERNEL_SRC}/.*.cmd - rm -f ${DIR_KERNEL_SRC}/Module.markers ${DIR_KERNEL_SRC}/Module.symvers ${DIR_KERNEL_SRC}/modules.order - rm -rf ${DIR_KERNEL_SRC}/.tmp_versions rm -rf $(SUB_BUILD_DIR) diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/Makefile b/platform/broadcom/sonic-platform-modules-ragile/common/app/Makefile new file mode 100644 index 000000000000..25ba3c5a9156 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/Makefile @@ -0,0 +1,25 @@ +pes_parent_dir:=$(shell pwd)/$(lastword $(MAKEFILE_LIST)) +pes_parent_dir:=$(shell dirname $(pes_parent_dir)) + +SUBDIRS=$(shell ls -l | grep ^d | awk '{if($$9 != "build") print $$9}') +INC = -I./inc + +COMMON_OUT_PUT := $(shell pwd)/build +common_out_put_dir := $(COMMON_OUT_PUT)/app +common_module_dir := $(COMMON_OUT_PUT)/module/ +export common_out_put_dir common_module_dir + +all : CHECK $(SUBDIRS) +CHECK : + @echo $(pes_parent_dir) + +$(SUBDIRS):ECHO + #@echo $@ + make -C $@ + +ECHO: + @echo $(SUBDIRS) + +.PHONY : clean +clean : + -rm -rf $(COMMON_OUT_PUT) diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/dev_util/Makefile b/platform/broadcom/sonic-platform-modules-ragile/common/app/dev_util/Makefile new file mode 100644 index 000000000000..e4078716eb33 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/dev_util/Makefile @@ -0,0 +1,30 @@ +top_srcdir:=$(shell pwd) +#include $(top_srcdir)/Rules.mk +DIR=$(shell pwd) +BUILD_OUTPUT=$(DIR)/tmp +SRCS=$(wildcard *.c) +OBJS=$(patsubst %.c, $(BUILD_OUTPUT)/%.o, $(SRCS)) +DEPS=$(patsubst %.o, %.d, $(OBJS)) +CFLAGS+=-Wall -W -g -I$(DIR)/include +LDFLAGS= +PROGRAM=dfd_debug + +.PHONY: all + +all:$(OBJS) + $(CC) $(OBJS) $(LDFLAGS) -o $(BUILD_OUTPUT)/$(PROGRAM) + @if [ ! -d ${common_out_put_dir} ]; then mkdir -p ${common_out_put_dir} ;fi + cp -p $(BUILD_OUTPUT)/$(PROGRAM) $(common_out_put_dir) + +$(OBJS):$(SRCS) + @if [ ! -d ${BUILD_OUTPUT} ]; then mkdir -p ${BUILD_OUTPUT} ;fi + $(CC) -c $(CFLAGS) $(INCLUDE) $(*F).c -o $@ + +.PHONY: install +install: + @mkdir -p $(common_out_put_dir) + cp -p $(BUILD_OUTPUT)/$(PROGRAM) $(common_out_put_dir) + +rebuild: clean all +clean: + @rm -rf $(BUILD_OUTPUT)/* diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/dev_util/dfd_debug.c b/platform/broadcom/sonic-platform-modules-ragile/common/app/dev_util/dfd_debug.c new file mode 100644 index 000000000000..93ed6066efed --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/dev_util/dfd_debug.c @@ -0,0 +1,43 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include "dfd_utest.h" + +int g_dfd_debug_sw = 0; +int g_dfd_debugpp_sw = 0; + +void dfd_debug_set_init(void) +{ + FILE *fp; + char buf[10]; + + mem_clear(buf, sizeof(buf)); + fp = fopen(DFD_DEBUGP_DEBUG_FILE, "r"); + if (fp != NULL) { + + g_dfd_debug_sw = 1; + fclose(fp); + } + + fp = fopen(DFD_DEBUGPP_DEBUG_FILE, "r"); + if (fp != NULL) { + + g_dfd_debugpp_sw = 1; + fclose(fp); + } + + return; +} + +int main(int argc, char* argv[]) +{ + dfd_debug_set_init(); + dfd_utest_cmd_main(argc, argv); + + return 0; +} diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/dev_util/dfd_utest.c b/platform/broadcom/sonic-platform-modules-ragile/common/app/dev_util/dfd_utest.c new file mode 100644 index 000000000000..9c711830958e --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/dev_util/dfd_utest.c @@ -0,0 +1,1802 @@ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "dfd_utest.h" + +#define DFD_UTEST_MAX_RDWR_NUM (256) +#define DFD_UTEST_DEFAULT_WR_NUM (1) + +#define DEV_MEM_NAME "/dev/mem" +#define DEV_KMEM_NAME "/dev/kmem" + +#define WIDTH_1Byte (1) +#define WIDTH_2Byte (2) +#define WIDTH_4Byte (4) +#define DFD_UTEST_MAX_BIT_WIDTH (4) + +#ifdef DFD_UTEST_ITEM +#undef DFD_UTEST_ITEM +#endif +#define DFD_UTEST_ITEM(_id, _type_str, _help_info, _help_info_detail) {_id, #_type_str, dfd_utest_##_type_str, _help_info, _help_info_detail}, +static dfd_utest_t g_dfd_unit_test[] = { + DFD_UTEST_ITEM_ALL +}; + +static int g_sys_page_size; +#define SYS_PAGE_SIZE g_sys_page_size +#define SYS_PAGE_MASK (~(SYS_PAGE_SIZE - 1)) + +void dfd_utest_print_cmd(int argc, char* argv[]) +{ + int i; + + for (i = 1; i < argc; i++) { + if (i != 1) { + printf(" "); + } + printf("%s", argv[i]); + } + return; +} + +void dfd_utest_print_all_help(void) +{ + int i, tbl_size; + + tbl_size = sizeof(g_dfd_unit_test) / sizeof(g_dfd_unit_test[0]); + + for (i = 0; i < tbl_size; i++) { + printf("%-20s\t\t\t%s\r\n", g_dfd_unit_test[i].type_str, g_dfd_unit_test[i].help_info); + } + + return; +} + +void dfd_utest_printf_single_help(int utest_type) +{ + int i, tbl_size; + + tbl_size = sizeof(g_dfd_unit_test) / sizeof(g_dfd_unit_test[0]); + for (i = 0; i < tbl_size; i++) { + if (g_dfd_unit_test[i].utest_type == utest_type) { + printf("%-20s\t\t\t%s\r\n", g_dfd_unit_test[i].type_str, g_dfd_unit_test[i].help_info_detail); + return; + } + } + + DFD_DEBUG_DBG("type: %d not match.\n", utest_type); + return; + +} + +void dfd_utest_printf_reg(uint8_t *buf, int buf_len, uint32_t offset_addr) +{ + int i, j, tmp; + + j = offset_addr % 16; + tmp = j; + offset_addr -= j; + printf("\n "); + + for (i = 0; i < 16; i++) { + printf("%2x ", i); + } + + for (i = 0; i < buf_len + j; i++) { + if ((i % 16) == 0) { + printf("\n0x%08x ", offset_addr); + offset_addr = offset_addr + 16; + } + if (tmp) { + printf(" "); + tmp--; + } else { + printf("%02x ", buf[i-j]); + } + } + + printf("\n"); + return; +} + +#define I2C_RETRIES 0x0701 +#define I2C_TIMEOUT 0x0702 +#define I2C_RDWR 0x0707 + +#define I2C_SLAVE 0x0703 /* Use this slave address */ + +#define I2C_SLAVE_FORCE 0x0706 /* Use this slave address, even if it + is already in use by a driver! */ +#define I2C_PEC 0x0708 /* != 0 to use PEC with SMBus */ +#define I2C_SMBUS 0x0720 /* SMBus transfer */ + +struct i2c_msg +{ + unsigned short addr; + unsigned short flags; +#define I2C_M_TEN 0x0010 +#define I2C_M_RD 0x0001 + unsigned short len; + unsigned char *buf; +}; + +struct i2c_rdwr_ioctl_data +{ + struct i2c_msg *msgs; + int nmsgs; + +}; + +#define DFD_I2C_SHORT_ADDR_TYPE 0 +#define DFD_I2C_RETRY_SLEEP_TIME (10000) /* 10ms */ +#define DFD_I2C_RETRY_TIME (50000 / DFD_I2C_RETRY_SLEEP_TIME) +/* i2c_smbus_xfer read or write markers */ +#define I2C_SMBUS_READ 1 +#define I2C_SMBUS_WRITE 0 + +/* SMBus transaction types (size parameter in the above functions) + Note: these no longer correspond to the (arbitrary) PIIX4 internal codes! */ +#define I2C_SMBUS_QUICK 0 +#define I2C_SMBUS_BYTE 1 +#define I2C_SMBUS_BYTE_DATA 2 +#define I2C_SMBUS_WORD_DATA 3 +#define I2C_SMBUS_PROC_CALL 4 +#define I2C_SMBUS_BLOCK_DATA 5 +#define I2C_SMBUS_I2C_BLOCK_BROKEN 6 +#define I2C_SMBUS_BLOCK_PROC_CALL 7 /* SMBus 2.0 */ +#define I2C_SMBUS_I2C_BLOCK_DATA 8 + +#if LINUX_VERSION_CODE < KERNEL_VERSION(4,0,36) +/* fix tjm */ + +#ifndef __ASSEMBLY__ +/* + * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the + * header files exported to user space + */ +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +typedef __signed__ long __s64; +typedef unsigned long __u64; + +#endif /* __ASSEMBLY__ */ + +#else +/* do noting add tjm */ +#endif + +/* + * Data for SMBus Messages + */ +#define I2C_SMBUS_BLOCK_MAX 32 /* As specified in SMBus standard */ +union i2c_smbus_data { + __u8 byte; + __u16 word; + __u8 block[I2C_SMBUS_BLOCK_MAX + 2]; /* block[0] is used for length */ + /* and one more for user-space compatibility */ +}; + +/* This is the structure as used in the I2C_SMBUS ioctl call */ +struct i2c_smbus_ioctl_data { + __u8 read_write; + __u8 command; + __u32 size; + union i2c_smbus_data *data; +}; +int32_t dfd_read_port_i2c_one_time_smbus(char *i2c_name, uint16_t dev_addr, uint16_t offset_addr, + uint8_t *recv_buf, int32_t size, int addr_type) +{ + union i2c_smbus_data data; + struct i2c_smbus_ioctl_data ioctl_data; + unsigned long addr = dev_addr; + int fd; + int rc; + int rv; + int i; + + mem_clear(&ioctl_data, sizeof(struct i2c_smbus_ioctl_data)); + if (i2c_name == NULL || recv_buf == NULL) { + DFD_DEBUG_ERROR("i2c_num = NULL, recv_buf = NULL\r\n"); + return -1; + } + + DFD_DEBUG_DBG("i2c name: %s, dev_addr: 0x%x, offset_addr: 0x%x, size: %d, addr_type: %d.\n", i2c_name, dev_addr, + offset_addr, size, addr_type); + + rv = 0; + fd = open(i2c_name, O_RDWR | O_SYNC); + if (fd < 0) { + DFD_DEBUG_ERROR("i2c open fail fd %d\n", fd); + rv = fd; + goto err; + } + if (ioctl(fd, I2C_SLAVE_FORCE , addr) < 0) { + DFD_DEBUG_ERROR("ioctl 2C_SLAVE_FORCE %d.\n", errno); + rv =-1; + goto fail; + } + for (i = 0 ;i < size; i++) { + data.byte = 0; + ioctl_data.read_write = I2C_SMBUS_READ; + ioctl_data.command = (offset_addr + i); + ioctl_data.size = I2C_SMBUS_BYTE_DATA; + ioctl_data.data= &data; + + rc = ioctl(fd, I2C_SMBUS, &ioctl_data); + if (rc < 0) { + DFD_DEBUG_ERROR("read, I2C_SMBUS failed: %d.\n", errno); + rv = -1; + goto fail; + } + *(recv_buf + i) = data.byte; + } + fail: + close(fd); + err: + return rv; + +} + +int32_t dfd_read_port_i2c_one_time(char *i2c_name, uint16_t dev_addr, uint16_t offset_addr, + uint8_t *recv_buf, int32_t size, int addr_type) +{ + + int32_t fd, rv; + struct i2c_rdwr_ioctl_data ioctl_data; + struct i2c_msg msgs[2]; + uint8_t buf[2]; + + if (i2c_name == NULL || recv_buf == NULL) { + DFD_DEBUG_ERROR("i2c_num = NULL, recv_buf = NULL\r\n"); + return -1; + } + + DFD_DEBUG_DBG("i2c name %s, dev_addr 0x%x, offset_addr 0x%x, size %d, addr_type %d.\n", i2c_name, dev_addr, + offset_addr, size, addr_type); + + rv = 0; + fd = open(i2c_name, O_RDWR | O_SYNC); + if (fd < 0) { + DFD_DEBUG_ERROR("i2c open fail fd %d\n", fd); + return -1; + } + mem_clear(&ioctl_data, sizeof(ioctl_data)); + mem_clear(msgs, sizeof(msgs)); + mem_clear(buf, sizeof(buf)); + if (ioctl(fd, I2C_SLAVE, dev_addr) < 0) { + + DFD_DEBUG_ERROR("%s %dioctl fail(ret:%d, errno:%s)!\r\n", __func__ , __LINE__, rv, strerror(errno)); + rv = -1; + goto fail; + } + + buf[0] = (uint8_t)(offset_addr); + msgs[0].addr= dev_addr; + msgs[0].len= 2; + msgs[0].buf= buf; + msgs[1].addr= dev_addr; + msgs[1].flags|= I2C_M_RD; + msgs[1].len= 1; + msgs[1].buf= recv_buf; + ioctl_data.nmsgs= 1; + ioctl_data.msgs= msgs; + + rv = ioctl(fd, I2C_RDWR, &ioctl_data); + if(rv < 0) { + DFD_DEBUG_ERROR("%s %dioctl fail(ret:%d, errno:%s)!\r\n", __func__ , __LINE__, rv, strerror(errno)); + goto fail; + } + ioctl_data.msgs= &msgs[1]; + DFD_DEBUG_DBG("ioctlread, return :%d/n", ioctl(fd, I2C_RDWR, &ioctl_data)); + DFD_DEBUG_DBG("dfd_read_port_i2c addr: 0x%X, offset: 0x%X, value: 0x%X\n", dev_addr, offset_addr, *recv_buf); + fail: + close(fd); + return rv; + +} + +int32_t dfd_read_port_i2c(char *i2c_name, uint16_t dev_addr, uint16_t offset_addr, + uint8_t *recv_buf, int32_t size) +{ + int i; + int rv; + + for (i = 0; i < DFD_I2C_RETRY_TIME; i++) { + rv = dfd_read_port_i2c_one_time_smbus(i2c_name, dev_addr, offset_addr, recv_buf, size, DFD_I2C_SHORT_ADDR_TYPE); + if (rv < 0) { + DFD_DEBUG_ERROR("(read times %d)i2c name %s, dev_addr 0x%X, offset_addr 0x%X, addr_type %d\n", i, i2c_name, dev_addr, offset_addr, DFD_I2C_SHORT_ADDR_TYPE); + usleep(DFD_I2C_RETRY_SLEEP_TIME); + continue; + } + break; + } + + return rv; +} + +int32_t dfd_write_port_i2c_one_time(char *i2c_name, uint16_t dev_addr, uint16_t offset_addr, + uint8_t *write_buf, int32_t size,int addr_type) +{ + int32_t fd, rv; + int index; + struct i2c_smbus_ioctl_data ioctl_data; + union i2c_smbus_data data; + uint8_t addr_buf[2]; + uint8_t write_buf_tmp[256]; + + if (i2c_name == NULL || write_buf == NULL ) { + DFD_DEBUG_ERROR("i2c_num = NULL \r\n"); + return -1; + } + + if (size <= 0) { + DFD_DEBUG_ERROR("error:size\n"); + return -1; + } + DFD_DEBUG_DBG("i2c name %s, dev_addr 0x%x, offset_addr 0x%x, size %d, addr_type %d\n",i2c_name, dev_addr, + offset_addr, size, addr_type); + mem_clear(&ioctl_data, sizeof(ioctl_data)); + mem_clear(addr_buf, sizeof(addr_buf)); + mem_clear(write_buf_tmp, sizeof(write_buf_tmp)); + + rv = 0; + + fd = open(i2c_name, O_RDWR | O_SYNC); + if (fd < 0) { + DFD_DEBUG_ERROR("i2c open fail fd %d\n", fd); + return -1; + } + + if (ioctl(fd, I2C_SLAVE_FORCE, dev_addr) < 0) { + DFD_DEBUG_ERROR("ioctl, I2C_SLAVE failed: %d.\n", errno); + rv = -1; + goto fail; + } + + for (index = 0; index < size; index++) { + data.byte = *(write_buf + index); + ioctl_data.read_write = I2C_SMBUS_WRITE; + ioctl_data.command = (offset_addr + index); + ioctl_data.size = I2C_SMBUS_BYTE_DATA; + ioctl_data.data= &data; + rv = ioctl(fd, I2C_SMBUS, (unsigned long)&ioctl_data); + if(rv < 0) { + DFD_DEBUG_ERROR("ioctl fail(ret:%d, errno:%s %d) !\r\n", rv, strerror(errno),errno); + break; + } + DFD_DEBUG_DBG("ret:%d value:0x%02x\n", rv, data.byte); + usleep(5000); + } + +fail: + close(fd); + return rv; +} + +int32_t dfd_write_port_i2c(char *i2c_name, uint16_t dev_addr, uint16_t offset_addr, + uint8_t *write_buf, int32_t size) +{ + int i; + int rv; + + for (i = 0; i < DFD_I2C_RETRY_TIME; i++) { + rv = dfd_write_port_i2c_one_time(i2c_name, dev_addr, offset_addr, write_buf,size, DFD_I2C_SHORT_ADDR_TYPE); + if (rv < 0) { + DFD_DEBUG_ERROR("(write times %d)i2c name %s, dev_addr 0x%X, offset_addr 0x%X, addr_type %d\n", + i, i2c_name, dev_addr, offset_addr, DFD_I2C_SHORT_ADDR_TYPE); + usleep(DFD_I2C_RETRY_SLEEP_TIME); + continue; + } + break; + } + + return rv; +} + +static int dfd_read_io_port(uint16_t offset_addr, uint8_t *recv_buf, int32_t size) +{ + int fd; + int ret; + + fd = open("/dev/port", O_RDWR); + if (fd < 0) { + printf("open failed ret %d.\n", fd); + return -1; + } + + ret = lseek(fd, offset_addr, SEEK_SET); + if (ret < 0) { + printf("lseek failed ret %d.\n", ret); + goto exit; + } + + ret = read(fd, recv_buf, size); + if (ret != size) { + printf("read failed ret %d size %d.\n", ret, size); + ret = -1; + goto exit; + } + +exit: + close(fd); + return ret; +} + +static int dfd_write_io_port(uint16_t offset_addr, uint8_t *write_buf, int32_t size) +{ + int fd; + int ret; + + fd = open("/dev/port", O_RDWR); + if (fd < 0) { + printf("open failed ret %d.\n", fd); + return -1; + } + + ret = lseek(fd, offset_addr, SEEK_SET); + if (ret < 0) { + printf("lseek failed ret %d.\n", ret); + goto exit; + } + + ret = write(fd, write_buf, size); + if (ret != size) { + printf("write failed ret %d size %d.\n", ret, size); + ret = -1; + goto exit; + } + +exit: + close(fd); + return ret; +} + +static int dfd_process_mem(char *dev_name, char is_wr, char width, off_t offset, uint8_t *buf, int32_t size) +{ + int mfd, ret = 0; + void *base; + int i, j; + unsigned int val; + off_t map_offset; + size_t map_size; + + if (size & (width - 1)) { + printf("size %d invalid.\n", size); + return -1; + } + + mfd = open(dev_name, O_RDWR); + if (mfd < 0) { + printf("Cannot open %s.\n", dev_name); + return -1; + } + + g_sys_page_size = getpagesize(); + map_offset = offset & SYS_PAGE_MASK; + map_size = size + offset - map_offset; + base = mmap(NULL, map_size, PROT_READ | PROT_WRITE, MAP_SHARED, mfd, map_offset); + if (base == MAP_FAILED) { + printf("mmap offset 0x%lx failed error(%s).\n", map_offset, strerror(errno)); + close(mfd); + return -1; + } + printf("width %d map_offset 0x%lx, offset 0x%lx, mmap base %p, g_sys_page_size %d\n", + width, map_offset, offset, base, g_sys_page_size); + + if (is_wr) { + for (i = 0; i < size; i = i + width) { + val = 0; + for (j = 0; j < width; j++) { + val |= buf[i + j] << (8 * j); + } + switch (width) { + case 1: + *((volatile unsigned char*)(base + i + offset - map_offset)) = val; + break; + case 2: + *((volatile unsigned short*)(base + i + offset - map_offset)) = val; + break; + case 4: + *((volatile unsigned int*)(base + i + offset - map_offset)) = val; + break; + default: + ret = -1; + printf("Not support width %d.\n", width); + goto exit; + } + } + } else { + for (i = 0; i < size; i = i + width) { + switch (width) { + case 1: + val = *((volatile unsigned char*)(base + i + offset - map_offset)); + break; + case 2: + val = *((volatile unsigned short*)(base + i + offset - map_offset)); + break; + case 4: + val = *((volatile unsigned int*)(base + i + offset - map_offset)); + break; + default: + ret = -1; + printf("Not support width %d.\n", width); + goto exit; + } + for (j = 0; j < width; j++) { + buf[i + j] = (val >> (8 * j)) & 0xff; + } + } + } +exit: + munmap(base, map_size); + close(mfd); + return ret; +} + +int32_t dfd_i2c_gen_read_one_time(char *i2c_path, uint32_t dev_addr, uint32_t addr_bitwidth, + uint32_t offset_addr, uint8_t *recv_buf, int32_t rd_len) +{ + int32_t fd, rv, i; + struct i2c_rdwr_ioctl_data ioctl_data; + struct i2c_msg msgs[2]; + uint8_t buf[DFD_UTEST_MAX_BIT_WIDTH]; + + fd = open(i2c_path, O_RDWR | O_SYNC); + if (fd < 0) { + DFD_DEBUG_ERROR("i2c open fail fd:%d\n", fd); + return -1; + } + mem_clear(&ioctl_data, sizeof(ioctl_data)); + mem_clear(msgs, sizeof(msgs)); + mem_clear(buf, sizeof(buf)); + + i = 0; + + switch (addr_bitwidth) { + case WIDTH_4Byte: + buf[i++] = (offset_addr >> 24) & 0xFF; + buf[i++] = (offset_addr >> 16) & 0xFF; + buf[i++] = (offset_addr >> 8) & 0xFF; + buf[i++] = offset_addr & 0xFF; + break; + case WIDTH_2Byte: + buf[i++] = (offset_addr >> 8) & 0xFF; + buf[i++] = offset_addr & 0xFF; + break; + case WIDTH_1Byte: + buf[i++] = offset_addr & 0xFF; + break; + default: + DFD_DEBUG_ERROR("Only support 1,2,4 Byte Address Width,but set %u addr_bitwidth \n", addr_bitwidth); + rv = -1; + goto fail; + } + + msgs[0].addr = dev_addr; + msgs[0].flags = 0; + msgs[0].len = addr_bitwidth; + msgs[0].buf = buf; + msgs[1].addr = dev_addr; + msgs[1].flags |= I2C_M_RD; + msgs[1].len = rd_len; + msgs[1].buf = recv_buf; + ioctl_data.nmsgs = 2; + ioctl_data.msgs = msgs; + + rv = ioctl(fd, I2C_RDWR, &ioctl_data); + if(rv < 0) { + DFD_DEBUG_ERROR("%s %d Error: Sending messages failed:(ret:%d, errno:%s)!\n", __func__ , __LINE__, rv, strerror(errno)); + goto fail; + } + +fail: + close(fd); + return rv; +} + +int32_t dfd_i2c_gen_read(char *i2c_path, uint32_t dev_addr, uint32_t addr_bitwidth, + uint32_t offset_addr, uint8_t *recv_buf, int32_t rd_len) +{ + int i; + int rv; + + for (i = 0; i < DFD_I2C_RETRY_TIME; i++) { + rv = dfd_i2c_gen_read_one_time(i2c_path, dev_addr, addr_bitwidth, offset_addr, recv_buf, rd_len); + if (rv < 0) { + DFD_DEBUG_ERROR("(read times:%d) i2c_path:%s, dev_addr:0x%x, addr_bitwidth:%u, offset_addr:0x%x, rd_len:%u\n", + i, i2c_path, dev_addr, addr_bitwidth, offset_addr, rd_len); + usleep(DFD_I2C_RETRY_SLEEP_TIME); + continue; + } + break; + } + + return rv; +} + +int dfd_utest_i2c_gen_rd(int argc, char* argv[]) +{ + int ret; + uint32_t i2c_bus, dev_addr, addr_bitwidth, offset_addr, data_bitwidth, rd_len, i, j; + char *stopstring; + char i2c_path[32]; + uint8_t tmp_value[DFD_UTEST_MAX_RDWR_NUM]; + uint8_t rd_value[DFD_UTEST_MAX_RDWR_NUM]; + + if (argc != 8) { + DFD_DEBUG_ERROR("params error\n"); + dfd_utest_printf_single_help(DFD_UTEST_ITEM_I2C_GEN_RD); + goto exit; + } + + i2c_bus = strtol(argv[2], &stopstring, 10); + dev_addr = strtol(argv[3], &stopstring, 16); + addr_bitwidth = strtol(argv[4], &stopstring, 10); + offset_addr = strtol(argv[5], &stopstring, 16); + data_bitwidth = strtol(argv[6], &stopstring, 10); + rd_len = strtol(argv[7], &stopstring, 10); + + if (rd_len > DFD_UTEST_MAX_RDWR_NUM) { + DFD_DEBUG_ERROR("Input num %d exceed max.\n", rd_len); + dfd_utest_printf_single_help(DFD_UTEST_ITEM_I2C_GEN_RD); + goto exit; + } + + dfd_utest_print_cmd(argc, argv); + printf(":\n"); + snprintf(i2c_path, sizeof(i2c_path), "/dev/i2c-%d", i2c_bus); + mem_clear(tmp_value, sizeof(tmp_value)); + ret = dfd_i2c_gen_read(i2c_path, dev_addr, addr_bitwidth, offset_addr, tmp_value, rd_len); + if (ret < 0) { + printf("read failed. ret:%d\n", ret); + goto exit; + } + + mem_clear(rd_value, sizeof(rd_value)); + if (data_bitwidth == WIDTH_1Byte) { + memcpy(rd_value, tmp_value, rd_len); + } else { + for (i = 0; i < rd_len; i += data_bitwidth) { + for (j = 0; (j < data_bitwidth) && (i + j < rd_len); j++) { + rd_value[i + data_bitwidth - j - 1] = tmp_value[i + j]; + } + } + } + + dfd_utest_printf_reg(rd_value, rd_len, offset_addr); + +exit: + return DFD_RV_MODE_NOTSUPPORT; +} + +int32_t dfd_i2c_gen_write_one_time(char *i2c_path, uint32_t dev_addr, uint32_t addr_bitwidth, + uint32_t offset_addr, uint8_t *wr_value, uint32_t wr_len) +{ + int32_t fd, rv, i; + struct i2c_rdwr_ioctl_data ioctl_data; + struct i2c_msg msgs[1]; + uint8_t buf[DFD_UTEST_MAX_BIT_WIDTH + DFD_UTEST_MAX_RDWR_NUM]; + + fd = open(i2c_path, O_RDWR | O_SYNC); + if (fd < 0) { + DFD_DEBUG_ERROR("i2c open fail fd %d\n", fd); + return -1; + } + mem_clear(&ioctl_data, sizeof(ioctl_data)); + mem_clear(msgs, sizeof(msgs)); + mem_clear(buf, sizeof(buf)); + + i = 0; + + switch (addr_bitwidth) { + case WIDTH_4Byte: + buf[i++] = (offset_addr >> 24) & 0xFF; + buf[i++] = (offset_addr >> 16) & 0xFF; + buf[i++] = (offset_addr >> 8) & 0xFF; + buf[i++] = offset_addr & 0xFF; + break; + case WIDTH_2Byte: + buf[i++] = (offset_addr >> 8) & 0xFF; + buf[i++] = offset_addr & 0xFF; + break; + case WIDTH_1Byte: + buf[i++] = offset_addr & 0xFF; + break; + default: + DFD_DEBUG_ERROR("Only support 1,2,4 Byte Address Width,but set %u addr_bitwidth \r\n", addr_bitwidth); + rv = -1; + goto fail; + } + + memcpy(buf + addr_bitwidth, wr_value, wr_len); + + msgs[0].addr= dev_addr; + msgs[0].flags = 0; + msgs[0].len= addr_bitwidth + wr_len; + msgs[0].buf= buf; + + ioctl_data.nmsgs= 1; + ioctl_data.msgs= msgs; + + rv = ioctl(fd, I2C_RDWR, &ioctl_data); + if(rv < 0) { + DFD_DEBUG_ERROR("%s %dError: Sending messages failed:(ret:%d, errno:%s)!\n", __func__ , __LINE__, rv, strerror(errno)); + goto fail; + } else if (rv < ioctl_data.nmsgs) { + DFD_DEBUG_ERROR("%s %dWarning: only %d/%d messages were sent\n", __func__ , __LINE__, rv, ioctl_data.nmsgs); + } + +fail: + close(fd); + return rv; +} + +int32_t dfd_i2c_gen_write(char *i2c_path, uint32_t dev_addr, uint32_t addr_bitwidth, + uint32_t offset_addr, uint8_t *wr_value, uint32_t wr_len) +{ + int i; + int rv; + + for (i = 0; i < DFD_I2C_RETRY_TIME; i++) { + rv = dfd_i2c_gen_write_one_time(i2c_path, dev_addr, addr_bitwidth, offset_addr, wr_value, wr_len); + if (rv < 0) { + DFD_DEBUG_ERROR("(write times:%d)i2c_path:%s, dev_addr:0x%x, addr_bitwidth:%u, offset_addr:0x%x, wr_len:%u\n", + i, i2c_path, dev_addr, addr_bitwidth, offset_addr, wr_len); + usleep(DFD_I2C_RETRY_SLEEP_TIME); + continue; + } + break; + } + + return rv; +} + +int dfd_utest_i2c_gen_wr(int argc, char* argv[]) +{ + int ret; + uint32_t i2c_bus, dev_addr, addr_bitwidth, offset_addr, data_bitwidth, wr_len, tmp_data, para_len, i, j; + char *stopstring; + char i2c_path[32]; + uint8_t wr_value[DFD_UTEST_MAX_RDWR_NUM]; + + if (argc < 8) { + DFD_DEBUG_ERROR("Input invalid.\n"); + dfd_utest_printf_single_help(DFD_UTEST_ITEM_I2C_GEN_WR); + goto exit; + } + + i2c_bus = strtol(argv[2], &stopstring, 10); + dev_addr = strtol(argv[3], &stopstring, 16); + addr_bitwidth = strtol(argv[4], &stopstring, 10); + offset_addr = strtol(argv[5], &stopstring, 16); + data_bitwidth = strtol(argv[6], &stopstring, 10); + + para_len = argc - 7; + wr_len = para_len * data_bitwidth; + + if (wr_len > DFD_UTEST_MAX_RDWR_NUM) { + DFD_DEBUG_ERROR("Input num %d exceed max.\n", wr_len); + dfd_utest_printf_single_help(DFD_UTEST_ITEM_I2C_GEN_WR); + goto exit; + } + + if (data_bitwidth == WIDTH_1Byte) { + for (i = 0; i < para_len; i++) { + wr_value[i] = strtol(argv[7 + i], &stopstring, 16); + DFD_DEBUG_DBG(" index :%d value 0x%x\n", i , wr_value[i]); + } + } else { + for (i = 0; i < para_len; i++) { + tmp_data = strtol(argv[7 + i], &stopstring, 16); + DFD_DEBUG_DBG(" index :%d value 0x%x\n", i , tmp_data); + for (j = 0; j < data_bitwidth; j++) { + tmp_data = strtol(argv[7 + i], &stopstring, 16); + wr_value[j + i * data_bitwidth] = (tmp_data >> (24 - 8 * j)) & 0xFF; + } + } + } + + dfd_utest_print_cmd(argc, argv); + + printf(":\n"); + snprintf(i2c_path, sizeof(i2c_path), "/dev/i2c-%d", i2c_bus); + + ret = dfd_i2c_gen_write(i2c_path, dev_addr, addr_bitwidth, offset_addr, wr_value, wr_len); + if (ret < 0) { + printf("write failed. ret:%d\n", ret); + } else { + printf("write success\n"); + } +exit: + return DFD_RV_MODE_NOTSUPPORT; +} + +int dfd_utest_i2c_rd(int argc, char* argv[]) +{ + int ret; + uint8_t value[DFD_UTEST_MAX_RDWR_NUM]; + uint16_t dev_addr, offset_addr; + char *stopstring; + int num, i2c_bus; + char i2c_path[32]; + + if (argc != 6) { + DFD_DEBUG_ERROR("params error\n"); + dfd_utest_printf_single_help(DFD_UTEST_ITEM_I2C_RD); + goto exit; + } + + i2c_bus = strtol(argv[2], &stopstring, 10); + dev_addr = strtol(argv[3], &stopstring, 16); + offset_addr = strtol(argv[4], &stopstring, 16); + num = strtol(argv[5], &stopstring, 10); + + if (num > DFD_UTEST_MAX_RDWR_NUM) { + DFD_DEBUG_ERROR("Input num %d exceed max.\n", num); + dfd_utest_printf_single_help(DFD_UTEST_ITEM_I2C_RD); + goto exit; + } + + dfd_utest_print_cmd(argc, argv); + printf(":\n"); + snprintf(i2c_path, sizeof(i2c_path), "/dev/i2c-%d", i2c_bus); + mem_clear(value, sizeof(value)); + ret = dfd_read_port_i2c(i2c_path, dev_addr, offset_addr, value, num); + if (ret < 0) { + printf("failed ret %d\n", ret); + goto exit; + } + + dfd_utest_printf_reg(value, num, offset_addr); + +exit: + return DFD_RV_MODE_NOTSUPPORT; + +} + +int dfd_utest_i2c_wr(int argc, char* argv[]) +{ + int ret; + uint16_t dev_addr, offset_addr; + char *stopstring; + int i2c_bus; + char i2c_path[32]; + uint8_t wr_len,i; + uint8_t wr_value[DFD_UTEST_MAX_RDWR_NUM]; + + if (argc < 6) { + DFD_DEBUG_ERROR("Input invalid.\n"); + dfd_utest_printf_single_help(DFD_UTEST_ITEM_I2C_WR); + goto exit; + } + + wr_len = argc - 5; + i2c_bus = strtol(argv[2], &stopstring, 10); + dev_addr = strtol(argv[3], &stopstring, 16); + offset_addr = strtol(argv[4], &stopstring, 16); + + for (i = 0; i < wr_len; i++) { + wr_value[i] = strtol(argv[5+i], &stopstring, 16); + DFD_DEBUG_DBG(" index :%d value %x\n", i , wr_value[i]); + } + + dfd_utest_print_cmd(argc, argv); + + printf(":\n"); + snprintf(i2c_path, sizeof(i2c_path), "/dev/i2c-%d", i2c_bus); + + ret = dfd_write_port_i2c(i2c_path, dev_addr, offset_addr, wr_value, wr_len); + if (ret < 0) { + printf("failed ret %d\n", ret); + } else { + printf("success\n"); + } +exit: + return DFD_RV_MODE_NOTSUPPORT; +} + +int dfd_utest_io_rd(int argc, char* argv[]) +{ + int ret; + uint8_t value[DFD_UTEST_MAX_RDWR_NUM]; + uint16_t offset_addr; + char *stopstring; + int num; + + if (argc != 4) { + DFD_DEBUG_ERROR("params error\n"); + dfd_utest_printf_single_help(DFD_UTEST_ITEM_IO_RD); + goto exit; + } + + offset_addr = strtol(argv[2], &stopstring, 16); + num = strtol(argv[3], &stopstring, 10); + + if (num > DFD_UTEST_MAX_RDWR_NUM) { + DFD_DEBUG_ERROR("Input num %d exceed max.\n", num); + dfd_utest_printf_single_help(DFD_UTEST_ITEM_IO_RD); + goto exit; + } + + dfd_utest_print_cmd(argc, argv); + printf(":\n"); + mem_clear(value, sizeof(value)); + ret = dfd_read_io_port(offset_addr, value, num); + if (ret < 0) { + printf("failed ret %d\n", ret); + goto exit; + } + + dfd_utest_printf_reg(value, num, offset_addr); + +exit: + return DFD_RV_MODE_NOTSUPPORT; +} + +int dfd_utest_io_wr(int argc, char* argv[]) +{ + int ret; + uint16_t offset_addr; + char *stopstring; + int32_t wr_len,i; + uint8_t wr_value[DFD_UTEST_MAX_RDWR_NUM]; + + if (argc < 4) { + DFD_DEBUG_ERROR("Input invalid.\n"); + dfd_utest_printf_single_help(DFD_UTEST_ITEM_IO_WR); + goto exit; + } + + wr_len = argc - 3; + if (wr_len > DFD_UTEST_MAX_RDWR_NUM) { + DFD_DEBUG_ERROR("Input num %d exceed max.\n", wr_len); + dfd_utest_printf_single_help(DFD_UTEST_ITEM_IO_WR); + goto exit; + } + + offset_addr = strtol(argv[2], &stopstring, 16); + + for (i = 0; i < wr_len; i++) { + wr_value[i] = strtol(argv[3 + i], &stopstring, 16); + DFD_DEBUG_DBG(" index :%d value %x\n", i , wr_value[i]); + } + + dfd_utest_print_cmd(argc, argv); + + printf(":\n"); + ret = dfd_write_io_port(offset_addr, wr_value, wr_len); + if (ret < 0) { + printf("failed ret %d\n", ret); + } else { + printf("success\n"); + } +exit: + return DFD_RV_MODE_NOTSUPPORT; +} + +int dfd_utest_phymem_rd(int argc, char* argv[]) +{ + int ret, width; + uint8_t value[DFD_UTEST_MAX_RDWR_NUM]; + off_t offset_addr; + char *stopstring; + int num; + + if (argc != 5) { + DFD_DEBUG_ERROR("params error\n"); + dfd_utest_printf_single_help(DFD_UTEST_ITEM_PHYMEM_RD); + goto exit; + } + + width = strtol(argv[2], &stopstring, 10); + offset_addr = strtol(argv[3], &stopstring, 16); + num = strtol(argv[4], &stopstring, 10); + + if (num > DFD_UTEST_MAX_RDWR_NUM) { + DFD_DEBUG_ERROR("Input num %d exceed max.\n", num); + dfd_utest_printf_single_help(DFD_UTEST_ITEM_PHYMEM_RD); + goto exit; + } + + dfd_utest_print_cmd(argc, argv); + printf(":\n"); + mem_clear(value, sizeof(value)); + ret = dfd_process_mem(DEV_MEM_NAME, 0, width, offset_addr, value, num); + if (ret < 0) { + printf("failed ret %d\n", ret); + goto exit; + } + + dfd_utest_printf_reg(value, num, offset_addr); + +exit: + return DFD_RV_MODE_NOTSUPPORT; +} + +int dfd_utest_phymem_wr(int argc, char* argv[]) +{ + int ret, width; + off_t offset_addr; + char *stopstring; + int32_t wr_len,i; + uint8_t wr_value[DFD_UTEST_MAX_RDWR_NUM]; + + if (argc < 5) { + DFD_DEBUG_ERROR("Input invalid.\n"); + dfd_utest_printf_single_help(DFD_UTEST_ITEM_PHYMEM_WR); + goto exit; + } + + wr_len = argc - 4; + if (wr_len > DFD_UTEST_MAX_RDWR_NUM) { + DFD_DEBUG_ERROR("Input num %d exceed max.\n", wr_len); + dfd_utest_printf_single_help(DFD_UTEST_ITEM_PHYMEM_WR); + goto exit; + } + + width = strtol(argv[2], &stopstring, 10); + offset_addr = strtol(argv[3], &stopstring, 16); + + for (i = 0; i < wr_len; i++) { + wr_value[i] = strtol(argv[4 + i], &stopstring, 16); + DFD_DEBUG_DBG(" index :%d value %x\n", i , wr_value[i]); + } + + dfd_utest_print_cmd(argc, argv); + + printf(":\n"); + ret = dfd_process_mem(DEV_MEM_NAME, 1, width, offset_addr, wr_value, wr_len); + if (ret < 0) { + printf("failed ret %d\n", ret); + } else { + printf("success\n"); + } +exit: + return DFD_RV_MODE_NOTSUPPORT; +} + +int dfd_utest_kmem_rd(int argc, char* argv[]) +{ + int ret, width; + uint8_t value[DFD_UTEST_MAX_RDWR_NUM]; + uint16_t offset_addr; + char *stopstring; + int num; + + if (argc != 5) { + DFD_DEBUG_ERROR("params error\n"); + dfd_utest_printf_single_help(DFD_UTEST_ITEM_KMEM_RD); + goto exit; + } + + width = strtol(argv[2], &stopstring, 10); + offset_addr = strtol(argv[3], &stopstring, 16); + num = strtol(argv[4], &stopstring, 10); + + if (num > DFD_UTEST_MAX_RDWR_NUM) { + DFD_DEBUG_ERROR("Input num %d exceed max.\n", num); + dfd_utest_printf_single_help(DFD_UTEST_ITEM_KMEM_RD); + goto exit; + } + + dfd_utest_print_cmd(argc, argv); + printf(":\n"); + mem_clear(value, sizeof(value)); + ret = dfd_process_mem(DEV_KMEM_NAME, 0, width, offset_addr, value, num); + if (ret < 0) { + printf("failed ret %d\n", ret); + goto exit; + } + + dfd_utest_printf_reg(value, num, offset_addr); + +exit: + return DFD_RV_MODE_NOTSUPPORT; +} + +int dfd_utest_kmem_wr(int argc, char* argv[]) +{ + int ret; + uint16_t offset_addr, width; + char *stopstring; + int32_t wr_len,i; + uint8_t wr_value[DFD_UTEST_MAX_RDWR_NUM]; + + if (argc < 5) { + DFD_DEBUG_ERROR("Input invalid.\n"); + dfd_utest_printf_single_help(DFD_UTEST_ITEM_KMEM_WR); + goto exit; + } + + wr_len = argc - 4; + if (wr_len > DFD_UTEST_MAX_RDWR_NUM) { + DFD_DEBUG_ERROR("Input num %d exceed max.\n", wr_len); + dfd_utest_printf_single_help(DFD_UTEST_ITEM_KMEM_WR); + goto exit; + } + + width = strtol(argv[2], &stopstring, 10); + offset_addr = strtol(argv[3], &stopstring, 16); + + for (i = 0; i < wr_len; i++) { + wr_value[i] = strtol(argv[4 + i], &stopstring, 16); + DFD_DEBUG_DBG(" index :%d value %x\n", i , wr_value[i]); + } + + dfd_utest_print_cmd(argc, argv); + + printf(":\n"); + ret = dfd_process_mem(DEV_KMEM_NAME, 1, width, offset_addr, wr_value, wr_len); + if (ret < 0) { + printf("failed ret %d\n", ret); + } else { + printf("success\n"); + } +exit: + return DFD_RV_MODE_NOTSUPPORT; +} + +static unsigned long dfd_utest_get_file_size(const char *path) +{ + unsigned long filesize; + struct stat statbuff; + + if (stat(path, &statbuff) < 0) { + filesize = -1; + } else { + filesize = statbuff.st_size; + } + + return filesize; +} + +int dfd_utest_i2c_file_wr(int argc, char* argv[]) +{ + int ret; + uint16_t dev_addr, offset_addr; + char *stopstring; + int i2c_bus; + char i2c_path[32]; + char *file_name; + unsigned long filesize; + int fd; + uint8_t wr_buf[DFD_UTEST_MAX_RDWR_NUM]; + int len; + int bpt; /* byte per times*/ + int page_left; + + if (argc != 7) { + printf("Input invalid.\n"); + dfd_utest_printf_single_help(DFD_UTEST_ITEM_I2C_FILE_WR); + goto exit; + } + + i2c_bus = strtol(argv[2], &stopstring, 10); + dev_addr = strtol(argv[3], &stopstring, 16); + offset_addr = strtol(argv[4], &stopstring, 16); + bpt = strtol(argv[5], &stopstring, 10); + file_name = argv[6]; + + if ((bpt <= 0) || (bpt > DFD_UTEST_MAX_RDWR_NUM)) { + bpt = DFD_UTEST_MAX_RDWR_NUM; + } + + if ((bpt & (bpt - 1)) != 0) { + printf("Bytes per times %d isn't power of two.\n",bpt); + goto exit; + } + + filesize = dfd_utest_get_file_size(file_name); + if (filesize <= 0) { + printf("Input invalid file %s, filesize %lu.\n", file_name, filesize); + goto exit; + } + + fd = open(file_name, O_RDONLY); + if (fd < 0) { + printf("open file[%s] fail.\n", file_name); + goto exit; + } + + dfd_utest_print_cmd(argc, argv); + + printf(":\n"); + snprintf(i2c_path, sizeof(i2c_path), "/dev/i2c-%d", i2c_bus); + + while (filesize > 0) { + mem_clear(wr_buf, DFD_UTEST_MAX_RDWR_NUM); + len = bpt; + if (offset_addr & (bpt - 1)) { + page_left = bpt - (offset_addr & (bpt - 1)); + len = len > page_left ? page_left : len; + } + + len = read(fd, wr_buf, len); + + ret = dfd_write_port_i2c(i2c_path, dev_addr, offset_addr, wr_buf, len); + if (ret < 0) { + break; + } + offset_addr += len; + filesize -= len; + } + + close(fd); + + if (ret < 0) { + printf("failed ret %d\n", ret); + } else { + printf("success\n"); + } + +exit: + return DFD_RV_MODE_NOTSUPPORT; + +} + +/* compare with sys_flie_wr, One more step is read back verification */ +int dfd_utest_sysfs_file_upg(int argc, char* argv[]) +{ + int ret = 0; + uint32_t offset_addr; + char *file_name; + char *sysfs_loc; + char *stopstring; + unsigned long filesize; + int fd, file_fd; + uint8_t wr_buf[DFD_UTEST_MAX_RDWR_NUM]; + int len, write_len, per_wr_len; + int i; + uint8_t reread_buf[DFD_UTEST_MAX_RDWR_NUM]; + int reback_len, reread_len; + int j = 0; + + if (argc != 5 && argc != 6) { + printf("Input invalid.\n"); + dfd_utest_printf_single_help(DFD_UTEST_ITEM_SYSFS_FILE_UPG); + goto exit; + } + + sysfs_loc = argv[2]; + offset_addr = strtol(argv[3], &stopstring, 16); + file_name = argv[4]; + + if (argc == 6) { + per_wr_len = strtol(argv[5], &stopstring, 10); + if (per_wr_len > DFD_UTEST_MAX_RDWR_NUM || per_wr_len <= 0) { + printf("per_wr_byte %d invalid, not in range (0, 256]\n", per_wr_len); + goto exit; + } + } else { + per_wr_len = DFD_UTEST_DEFAULT_WR_NUM; + } + DFD_DEBUG_DBG("per_wr_byte: %d\n", per_wr_len); + filesize = dfd_utest_get_file_size(file_name); + if (filesize <= 0) { + printf("Input invalid file %s, filesize %lu.\n", file_name, filesize); + goto exit; + } + + fd = open(sysfs_loc, O_RDWR | O_SYNC); + if (fd < 0) { + printf("open file[%s] fail.\n", sysfs_loc); + goto exit; + } + + file_fd = open(file_name, O_RDONLY); + if (file_fd < 0) { + printf("open file[%s] fail.\n", file_name); + goto open_dev_err; + } + + dfd_utest_print_cmd(argc, argv); + + ret = lseek(fd, offset_addr, SEEK_SET); + if (ret < 0) { + printf("lseek file[%s offset=%d] fail,\n", sysfs_loc, offset_addr); + goto fail; + } + + printf(":\n"); + while (filesize > 0) { + if (filesize > (unsigned long)per_wr_len) { + len = per_wr_len; + } else { + len = filesize; + } + + mem_clear(wr_buf, DFD_UTEST_MAX_RDWR_NUM); + for (i = 0; i < DFD_I2C_RETRY_TIME; i++) { + len = read(file_fd, wr_buf, len); + if (len < 0) { + DFD_DEBUG_ERROR("read file[%s] fail, offset = 0x%x retrytimes = %d ret = %d\n", + sysfs_loc, offset_addr, i ,len); + usleep(DFD_I2C_RETRY_SLEEP_TIME); + continue; + } + break; + } + if (i == DFD_I2C_RETRY_TIME) { + printf("read file[%s] fail, offset = 0x%x, ret = %d\n", sysfs_loc, offset_addr, len); + goto fail; + } + + for (i = 0; i < DFD_I2C_RETRY_TIME; i++) { + write_len = write(fd, wr_buf, len); + if (write_len != len) { + DFD_DEBUG_ERROR("write file[%s] fail,offset = 0x%x retrytimes = %d len = %d,write_len =%d\n", + sysfs_loc, offset_addr, i ,len, write_len); + usleep(DFD_I2C_RETRY_SLEEP_TIME); + continue; + } + break; + } + if (i == DFD_I2C_RETRY_TIME) { + printf("write file[%s] fail, offset = 0x%x, len = %d,write_len =%d\n", + sysfs_loc, offset_addr, len, write_len); + goto fail; + } + + reback_len = write_len; + ret = lseek(fd, -reback_len, SEEK_CUR); + if (ret < 0) { + printf("reread lseek file[%s offset=%d] fail,lseek len=%d\n", + sysfs_loc, offset_addr, reback_len); + goto fail; + } + + mem_clear(reread_buf, DFD_UTEST_MAX_RDWR_NUM); + for (i = 0; i < DFD_I2C_RETRY_TIME; i++) { + reread_len = read(fd, reread_buf, reback_len); + if (reread_len != reback_len) { + DFD_DEBUG_ERROR("reread file[%s] fail,offset = 0x%x retrytimes = %d reread_len = %d,reback_len =%d\n", + sysfs_loc, offset_addr, i ,reread_len, reback_len); + usleep(DFD_I2C_RETRY_SLEEP_TIME); + continue; + } + break; + } + if (i == DFD_I2C_RETRY_TIME) { + printf("reread file[%s] fail, offset = 0x%x, reread_len = %d,reback_len = %d\n", + sysfs_loc, offset_addr, reread_len, reback_len); + goto fail; + } + + if (memcmp(reread_buf, wr_buf, reread_len) != 0) { + if (j < DFD_I2C_RETRY_TIME) { + DFD_DEBUG_ERROR("memcmp file[%s] fail,offset = 0x%x retrytimes = %d\n", + sysfs_loc, offset_addr, j); + j++; + ret = lseek(file_fd, -len, SEEK_CUR); + if (ret < 0) { + printf("retry file_fd lseek fail,lseek len=%d\n", len); + goto fail; + } + ret = lseek(fd, -write_len, SEEK_CUR); + if (ret < 0) { + printf("retry fd lseek fail,lseek len=%d\n", write_len); + goto fail; + } + continue; + } + + printf("upgrade file[%s] fail, offset = 0x%x.\n", sysfs_loc, offset_addr); + printf("want to write buf :\n"); + for (i = 0; i < reread_len; i++) { + printf("0x%x ", wr_buf[i]); + } + printf("\n"); + + printf("actually reread buf :\n"); + for (i = 0; i < reread_len; i++) { + printf("0x%x ", reread_buf[i]); + } + printf("\n"); + + goto fail; + } + + offset_addr += len; + filesize -= len; + usleep(5000); + } + + printf("success\n"); + close(file_fd); + close(fd); + return DFD_RV_OK; + +fail: + close(file_fd); +open_dev_err: + close(fd); +exit: + return DFD_RV_MODE_NOTSUPPORT; +} + +int dfd_utest_sysfs_file_wr(int argc, char* argv[]) +{ + int ret = 0; + uint32_t offset_addr; + char *file_name; + char *sysfs_loc; + char *stopstring; + unsigned long filesize; + int fd, file_fd; + uint8_t wr_buf[DFD_UTEST_MAX_RDWR_NUM]; + int len, write_len, per_wr_len; + int i; + + if (argc != 5 && argc != 6) { + printf("Input invalid.\n"); + dfd_utest_printf_single_help(DFD_UTEST_ITEM_SYSFS_FILE_WR); + goto exit; + } + + sysfs_loc = argv[2]; + offset_addr = strtol(argv[3], &stopstring, 16); + file_name = argv[4]; + + if (argc == 6) { + per_wr_len = strtol(argv[5], &stopstring, 10); + if (per_wr_len > DFD_UTEST_MAX_RDWR_NUM || per_wr_len <= 0) { + printf("per_wr_byte %d invalid, not in range (0, 256]\n", per_wr_len); + goto exit; + } + } else { + per_wr_len = DFD_UTEST_DEFAULT_WR_NUM; + } + DFD_DEBUG_DBG("per_wr_byte: %d\n", per_wr_len); + filesize = dfd_utest_get_file_size(file_name); + if (filesize <= 0) { + printf("Input invalid file %s, filesize %lu.\n", file_name, filesize); + goto exit; + } + + fd = open(sysfs_loc, O_RDWR | O_SYNC); + if (fd < 0) { + printf("open file[%s] fail.\n", sysfs_loc); + goto exit; + } + + file_fd = open(file_name, O_RDONLY); + if (file_fd < 0) { + printf("open file[%s] fail.\n", file_name); + goto open_dev_err; + } + + dfd_utest_print_cmd(argc, argv); + + ret = lseek(fd, offset_addr, SEEK_SET); + if (ret < 0) { + printf("lseek file[%s offset=%d] fail,\n", sysfs_loc, offset_addr); + goto fail; + } + + printf(":\n"); + while (filesize > 0) { + if (filesize > (unsigned long)per_wr_len) { + len = per_wr_len; + } else { + len = filesize; + } + + mem_clear(wr_buf, DFD_UTEST_MAX_RDWR_NUM); + for (i = 0; i < DFD_I2C_RETRY_TIME; i++) { + len = read(file_fd, wr_buf, len); + if (len < 0) { + DFD_DEBUG_ERROR("read file[%s] fail, offset = 0x%x retrytimes = %d ret = %d\n", + sysfs_loc, offset_addr, i ,len); + usleep(DFD_I2C_RETRY_SLEEP_TIME); + continue; + } + break; + } + if (i == DFD_I2C_RETRY_TIME) { + printf("read file[%s] fail, offset = 0x%x, ret = %d\n", sysfs_loc, offset_addr, len); + goto fail; + } + for (i = 0; i < DFD_I2C_RETRY_TIME; i++) { + write_len = write(fd, wr_buf, len); + if (write_len != len) { + DFD_DEBUG_ERROR("write file[%s] fail,offset = 0x%x retrytimes = %d len = %d,write_len =%d\n", sysfs_loc, offset_addr, i ,len, write_len); + usleep(DFD_I2C_RETRY_SLEEP_TIME); + continue; + } + break; + } + + if(i == DFD_I2C_RETRY_TIME) { + printf("write file[%s] fail, offset = 0x%x, len = %d,write_len =%d\n", sysfs_loc, offset_addr, len, write_len); + ret = -1; + goto fail; + } + offset_addr += len; + filesize -= len; + usleep(5000); + } + + printf("success\n"); + close(file_fd); + close(fd); + return DFD_RV_OK; + +fail: + close(file_fd); +open_dev_err: + close(fd); +exit: + return DFD_RV_MODE_NOTSUPPORT; +} + +int dfd_utest_sysfs_file_rd(int argc, char* argv[]) +{ + int ret = 0; + uint32_t offset_addr; + char *sysfs_loc; + char *stopstring; + int fd; + uint8_t rd_buf[DFD_UTEST_MAX_RDWR_NUM]; + int len, read_len;; + + if (argc != 5) { + printf("Input invalid.\n"); + dfd_utest_printf_single_help(DFD_UTEST_ITEM_SYSFS_FILE_RD); + goto exit; + } + + sysfs_loc = argv[2]; + offset_addr = strtol(argv[3], &stopstring, 16); + len = strtol(argv[4], &stopstring, 10); + + if (len > DFD_UTEST_MAX_RDWR_NUM) { + printf("Input num %d exceed max 256.\n", len); + goto exit; + } + + fd = open(sysfs_loc, O_RDONLY); + if (fd < 0) { + printf("open file[%s] fail.\n", sysfs_loc); + goto exit; + } + dfd_utest_print_cmd(argc, argv); + + printf(":\n"); + + ret = lseek(fd, offset_addr, SEEK_SET); + if (ret < 0) { + printf("lseek failed ret %d.\n", ret); + goto fail; + } + + mem_clear(rd_buf, DFD_UTEST_MAX_RDWR_NUM); + read_len = read(fd, rd_buf, len); + if (read_len != len) { + printf("read failed read_len %d len %d.\n", read_len, len); + goto fail; + } + dfd_utest_printf_reg(rd_buf, read_len, offset_addr); + close(fd); + return DFD_RV_OK; + +fail: + close(fd); +exit: + return DFD_RV_MODE_NOTSUPPORT; +} + +int dfd_utest_msr_rd(int argc, char* argv[]) +{ + int fd; + char msr_file_name[64]; + uint64_t data; + uint64_t read_result; + char *stopstring; + uint8_t cpu_index, width; + uint64_t offset; + + if (argc != 5) { + printf("rdmsr failed: Input invalid.\n"); + dfd_utest_printf_single_help(DFD_UTEST_ITEM_MSR_RD); + goto exit; + } + + cpu_index = strtol(argv[2], &stopstring, 10); + offset = strtol(argv[3], &stopstring, 16); + width = strtol(argv[4], &stopstring, 10); + + if (width != 8 && width != 16 && width != 32 && width != 64) { + printf("rdmsr failed: width:%u Input invalid.only support 8 16 32 64\n", width); + goto exit; + } + + mem_clear(msr_file_name, sizeof(msr_file_name)); + sprintf(msr_file_name, "/dev/cpu/%u/msr", cpu_index); + + fd = open(msr_file_name, O_RDONLY); + if (fd < 0) { + if (errno == ENXIO) { + fprintf(stderr, "rdmsr failed: No CPU %u\n", cpu_index); + } else if (errno == EIO) { + fprintf(stderr, "rdmsr failed: CPU %u doesn't support MSRs\n", cpu_index); + } else if (errno == ENOENT) { + fprintf(stderr, "rdmsr failed: can't find %s file, Please check if modprobe msr driver already\n", msr_file_name); + } else { + printf("rdmsr failed: %s open failed. errno:%d\n", msr_file_name, errno); + } + goto exit; + } + + if (pread(fd, &data, sizeof(data), offset) != sizeof(data)) { + fprintf(stderr, "rdmsr failed: CPU:%u offset:0x%lx read failed\n", cpu_index, offset); + goto fail; + } + + switch (width) { + case 8: + read_result = (volatile uint8_t)data; + break; + case 16: + read_result = (volatile uint16_t)data; + break; + case 32: + read_result = (volatile uint32_t)data; + break; + case 64: + read_result = (volatile uint64_t)data; + break; + default: + printf("rdmsr failed: width:%u illegal width.\n", width); + goto fail; + } + + printf("0x%lx\n", read_result); + close(fd); + return DFD_RV_OK; + +fail: + close(fd); +exit: + return DFD_RV_MODE_NOTSUPPORT; +} + +int dfd_utest_sysfs_data_wr(int argc, char* argv[]) +{ + uint32_t offset; + char *sysfs_loc; + char *stopstring; + uint8_t wr_buf[DFD_UTEST_MAX_RDWR_NUM]; + int ret, i; + int fd, len, write_len, index; + + if (argc < 5) { + DFD_DEBUG_ERROR("Input invalid.\n"); + dfd_utest_printf_single_help(DFD_UTEST_ITEM_SYSFS_DATA_WR); + goto exit; + } + + dfd_utest_print_cmd(argc, argv); + printf(":\n"); + + sysfs_loc = argv[2]; + offset = strtol(argv[3], &stopstring, 16); + len = argc - 4; + mem_clear(wr_buf, sizeof(wr_buf)); + for (i = 0; i < len; i++) { + wr_buf[i] = strtol(argv[4 + i], &stopstring, 16); + DFD_DEBUG_DBG("index :%d value %x\n", i , wr_buf[i]); + } + + fd = open(sysfs_loc, O_RDWR | O_SYNC); + if (fd < 0) { + printf("open file[%s] fail.\n", sysfs_loc); + goto exit; + } + + ret = lseek(fd, offset, SEEK_SET); + if (ret < 0) { + printf("lseek file[%s offset=%d] fail,\n", sysfs_loc, offset); + goto fail; + } + index = 0; + while (len > 0) { + for (i = 0; i < DFD_I2C_RETRY_TIME; i++) { + write_len = write(fd, &wr_buf[index], len); + if (write_len < 0) { + DFD_DEBUG_ERROR("write file[%s] fail, retrytimes: %d, offset: 0x%x, len: %d, write_len: %d\n", + sysfs_loc, offset, i, len, write_len); + usleep(DFD_I2C_RETRY_SLEEP_TIME); + continue; + } + if (write_len == 0) { + DFD_DEBUG_ERROR("write file[%s] EOF, offset: 0x%x, len: %d, write_len: %d\n", + sysfs_loc, offset, len, write_len); + goto fail; + } + break; + } + if(i == DFD_I2C_RETRY_TIME) { + printf("write file[%s] fail, offset: 0x%x, len: %d, write_len: %d\n", + sysfs_loc, offset, len, write_len); + goto fail; + } + offset += write_len; + index += write_len; + len -= write_len; + usleep(5000); + } + printf("success\n"); + close(fd); + return DFD_RV_OK; +fail: + close(fd); +exit: + return DFD_RV_MODE_NOTSUPPORT; +} + +dfd_utest_proc_fun dfd_utest_get_proc_func(char *type_str) +{ + int i, tbl_size; + + tbl_size = sizeof(g_dfd_unit_test) / sizeof(g_dfd_unit_test[0]); + + for (i = 0; i < tbl_size; i++) { + if (!strncmp(g_dfd_unit_test[i].type_str, type_str, strlen(g_dfd_unit_test[i].type_str))) { + return g_dfd_unit_test[i].utest_func; + } + } + DFD_DEBUG_DBG("type: %s not match.\n", type_str); + return NULL; +} + +void dfd_utest_cmd_main(int argc, char* argv[]) +{ + dfd_utest_proc_fun pfunc; + int ret; + + if (argc < 2) { + dfd_utest_print_all_help(); + return; + } + + pfunc = dfd_utest_get_proc_func(argv[1]); + if (pfunc == NULL) { + DFD_DEBUG_DBG("utest type %s in not support.\n", argv[1]); + dfd_utest_print_all_help(); + return; + } + ret = pfunc(argc, argv); + if ((ret != DFD_RV_MODE_NOTSUPPORT) && (ret != DFD_RV_INDEX_INVALID)) { + if (ret == DFD_RV_OK) { + DFD_DEBUG_DBG(" [SUCCESS]\n"); + } else { + DFD_DEBUG_DBG(" [FAIL(%d)]\n", ret); + } + } + + return; +} diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/dev_util/dfd_utest.h b/platform/broadcom/sonic-platform-modules-ragile/common/app/dev_util/dfd_utest.h new file mode 100644 index 000000000000..aa194a4dcdd7 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/dev_util/dfd_utest.h @@ -0,0 +1,103 @@ +/* monitor_utest.h */ +#ifndef __DFD_UTEST_H__ +#define __DFD_UTEST_H__ + +#include + +extern int g_dfd_debug_sw; +extern int g_dfd_debugpp_sw; + +#define DFD_UTEST_TRUE_FALSE_STRING(flag) ((flag == true) ? "true" : "false") + +#define DFD_DEBUG_DBG(fmt, args...) do { \ + if (g_dfd_debug_sw) { \ + printf("" fmt,\ + ##args); \ + } \ +} while (0) + +#define DFD_DEBUG_ERROR(fmt, args...) do { \ + if (g_dfd_debugpp_sw) { \ + printf("" fmt,\ + ##args); \ + } \ +} while (0) + +#define mem_clear(data, size) memset((data), 0, (size)) + +typedef enum dfd_rv_s { + DFD_RV_OK = 0, + DFD_RV_INIT_ERR = 1, + DFD_RV_SLOT_INVALID = 2, + DFD_RV_MODE_INVALID = 3, + DFD_RV_MODE_NOTSUPPORT = 4, + DFD_RV_TYPE_ERR = 5, + DFD_RV_DEV_NOTSUPPORT = 6, + DFD_RV_DEV_FAIL = 7, + DFD_RV_INDEX_INVALID = 8, + DFD_RV_NO_INTF = 9, + DFD_RV_NO_NODE = 10, + DFD_RV_NODE_FAIL = 11, +} dfd_rv_t; + +#define DFD_DEBUG_BUF_LEN (32) +#define DFD_DEBUGP_DEBUG_FILE "/sbin/.dfd_debugp_flag" +#define DFD_DEBUGPP_DEBUG_FILE "/sbin/.dfd_debugpp_flag" + +#define DFD_UTEST_MAX_PARA_NUM (4) +#define DFD_UTEST_TYPE_STRING_LEN (64) +#define DFD_UTEST_MATCH_STRING_LEN (64) +#define DFD_UTEST_HELP_STRING_LEN (256) +#define DFD_UTEST_INVALID_PARA (-1) +#define DFD_UTEST_BUFF_LEN (64) + +typedef enum dfd_fpga_cpld_flag_e { + DFD_CPLD_RW_FLAG = 0x00, + DFD_FPGA_RW_FLAG = 0x01, +} dfd_fpga_cpld_flag_t; + +typedef int (* dfd_utest_proc_fun)(int argc, char* argv[]); + +#define DFD_UTEST_ITEM_ALL \ + DFD_UTEST_ITEM(DFD_UTEST_ITEM_I2C_RD, i2c_rd, "i2c_rd [i2c_bus] [slave_addr] [offset] [len]", "i2c_rd [i2c_bus] [slave_addr] [offset] [len]") \ + DFD_UTEST_ITEM(DFD_UTEST_ITEM_I2C_WR, i2c_wr, "i2c_wr [i2c_bus] [slave_addr] [offset] [data0] ... [dataN]", "i2c_wr [i2c_bus] [slave_addr] [offset] [data0] ... [dataN]") \ + DFD_UTEST_ITEM(DFD_UTEST_ITEM_IO_RD, io_rd, "io_rd [offset] [len]", "io_rd [offset] [len]") \ + DFD_UTEST_ITEM(DFD_UTEST_ITEM_IO_WR, io_wr, "io_wr [offset] [data0]... [dataN]", "io_wr [offset] [data0]... [dataN]") \ + DFD_UTEST_ITEM(DFD_UTEST_ITEM_PHYMEM_RD, phymem_rd, "phymem_rd [bit_width] [offset] [len]", "phymem_rd [bit_width] [offset] [len]") \ + DFD_UTEST_ITEM(DFD_UTEST_ITEM_PHYMEM_WR, phymem_wr, "phymem_wr [bit_width] [offset] [data0]... [dataN]", "phymem_wr [bit_width] [offset] [data0]... [dataN]") \ + DFD_UTEST_ITEM(DFD_UTEST_ITEM_KMEM_RD, kmem_rd, "kmem_rd [bit_width] [offset] [len]", "kmem_rd [bit_width] [offset] [len]") \ + DFD_UTEST_ITEM(DFD_UTEST_ITEM_KMEM_WR, kmem_wr, "kmem_wr [bit_width][offset] [data0]... [dataN]", "kmem_wr [bit_width] [offset] [data0]... [dataN]") \ + DFD_UTEST_ITEM(DFD_UTEST_ITEM_I2C_FILE_WR, i2c_file_wr, "i2c_file_wr [i2c_bus] [slave_addr] [offset] [bpt] [filename]", "i2c_file_wr [i2c_bus] [slave_addr] [offset] [bpt] [filename]\nbpt:bytes per times") \ + DFD_UTEST_ITEM(DFD_UTEST_ITEM_SYSFS_FILE_WR, sysfs_file_wr, "sysfs_file_wr [sysfs_loc] [offset] [filename] [per_wr_byte]", "sysfs_file_wr [sysfs_loc] [offset] [filename] [per_wr_byte]") \ + DFD_UTEST_ITEM(DFD_UTEST_ITEM_SYSFS_FILE_RD, sysfs_file_rd, "sysfs_file_rd [sysfs_loc] [offset] [len]", "sysfs_file_rd [sysfs_loc] [offset] [len]") \ + DFD_UTEST_ITEM(DFD_UTEST_ITEM_SYSFS_FILE_UPG, sysfs_file_upg, "sysfs_file_upg [sysfs_loc] [offset] [filename] [per_wr_byte]", "sysfs_file_upg [sysfs_loc] [offset] [filename] [per_wr_byte]") \ + DFD_UTEST_ITEM(DFD_UTEST_ITEM_I2C_GEN_RD, i2c_gen_rd, "i2c_gen_rd [i2c_bus] [slave_addr] [addr_bitwidth] [offset] [data_bitwidth] [len]", "i2c_gen_rd [i2c_bus] [slave_addr] [addr_bitwidth] [offset] [data_bitwidth] [len]") \ + DFD_UTEST_ITEM(DFD_UTEST_ITEM_I2C_GEN_WR, i2c_gen_wr, "i2c_gen_wr [i2c_bus] [slave_addr] [addr_bitwidth] [offset] [data_bitwidth] [data0]... [dataN]", "i2c_gen_wr [i2c_bus] [slave_addr] [addr_bitwidth] [offset] [data_bitwidth] [data0]... [dataN]") \ + DFD_UTEST_ITEM(DFD_UTEST_ITEM_MSR_RD, msr_rd, "msr_rd [cpu_index] [offset] [width]", "msr_rd [cpu_index] [offset] [width]") \ + DFD_UTEST_ITEM(DFD_UTEST_ITEM_SYSFS_DATA_WR, sysfs_data_wr, "sysfs_data_wr [sysfs_loc] [offset] [data0] ... [dataN]", "sysfs_data_wr [sysfs_loc] [offset] [data0] ... [dataN]]") \ + +#ifdef DFD_UTEST_ITEM +#undef DFD_UTEST_ITEM +#endif +#define DFD_UTEST_ITEM(_id, _type_str, _help_info, _help_info_detail) _id, +typedef enum dfd_utest_item_id_s { + DFD_UTEST_ITEM_ALL +} dfd_utest_item_id_t; + +typedef struct { + int utest_type; + char type_str[DFD_UTEST_TYPE_STRING_LEN]; + dfd_utest_proc_fun utest_func; + char help_info[DFD_UTEST_HELP_STRING_LEN]; + char help_info_detail[DFD_UTEST_HELP_STRING_LEN]; +} dfd_utest_t; + +void dfd_utest_cmd_main(int argc, char* argv[]); + +#ifdef DFD_UTEST_ITEM +#undef DFD_UTEST_ITEM +#endif +#define DFD_UTEST_ITEM(_id, _type_str, _help_info, _help_info_detail) int dfd_utest_##_type_str(int argc, char* argv[]); +DFD_UTEST_ITEM_ALL + +#endif diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/Makefile b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/Makefile new file mode 100644 index 000000000000..62663efdbbd5 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/Makefile @@ -0,0 +1,19 @@ +top_srcdir:=$(shell pwd) +include $(top_srcdir)/Rules.mk + +firmware-y:= +firmware-y += firmware_driver +firmware-y += firmware_upgrade + +.PHONY: all +all: build + +.PHONY: build +build: $(firmware-y) +$(foreach dir,$(firmware-y),$(eval $(call compile_dirs,$(dir)))) + +.PHONY: rpmpkg +rpmpkg: +ifeq ("$(CONFIG_CPLD_UPGRADE_ISPVME)", "y") + #$(RPMPKG) $(install_cpld_dir) firmware-cpld-ispvme.spec git +endif diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/Rules.mk b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/Rules.mk new file mode 100644 index 000000000000..5fb5a09d34fd --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/Rules.mk @@ -0,0 +1,42 @@ +CC ?= $(CROSS)gcc +AR ?= $(CROSS)ar +AS ?= $(CROSS)as +LD ?= $(CROSS)ld +STRIP ?= $(CROSS)strip + +install_root:=${top_srcdir}/images + +install_header_dir:=${install_root}/header +install_adir:=$(install_root)/lib +install_symbol_dir:=$(install_root)/symbol +symbol_files:=$(shell find $(EXPORT_SYMBOL) -name 'Module.symvers') +# +# symbol_files += $(shell find $(install_symbol_dir) -name 'Module.symvers') +# KBUILD_EXTRA_SYMBOLS += $(symbol_files) +# export KBUILD_EXTRA_SYMBOLS + +# top root: install_rootfs_dir +install_rootfs_dir:=$(install_root)/rootfs + +install_sodir:=$(install_rootfs_dir)/$(INSTALL_SODIR) + +install_usr_bin_dir:=$(install_rootfs_dir)/usr/bin +install_sbin_dir:=$(install_rootfs_dir)/sbin +install_etc_dir:=$(install_rootfs_dir)/etc + +export INSTALL_MOD_PATH:=$(ROOT) + +BUILD_CFLAGS:=$(CFLAGS) -I$(install_header_dir) +BUILD_LDFLAGS:=$(LDFLAGS) -L/$(install_sodir) -L/$(install_adir) + +define compile_dirs +.PHONY: $(1) +$(1): + @echo;echo "building $(1)..." + @$(MAKE) -C ${1} +endef + +compile.c = $(CC) $(BUILD_CFLAGS) -d -c -o $@ $< +%.o: %.c + $(compile.c) + diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/Makefile b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/Makefile new file mode 100644 index 000000000000..e8879aeff5e7 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/Makefile @@ -0,0 +1,19 @@ +include $(top_srcdir)/Rules.mk + +firmware-y:= +firmware-y += firmware_driver_ispvme +firmware-y += firmware_driver_cpld +firmware-y += firmware_driver_sysfs + +.PHONY: all +all: build + +.PHONY: build +build: $(firmware-y) +$(foreach dir,$(firmware-y),$(eval $(call compile_dirs,$(dir)))) + +.PHONY: rpmpkg +rpmpkg: +ifeq ("$(CONFIG_CPLD_UPGRADE_ISPVME)", "y") + #$(RPMPKG) $(install_cpld_dir) firmware-cpld-ispvme.spec git +endif diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/Makefile b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/Makefile new file mode 100644 index 000000000000..0add28cb9056 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/Makefile @@ -0,0 +1,23 @@ +#include $(top_srcdir)/debian/rules +#KERNELDIR := ${KBUILD_OUTPUT} + +PWD = $(shell pwd) + +EXTRA_CFLAGS:= -I$(M)/include +MAKEFILE_FILE_PATH = $(abspath $(lastword $(MAKEFILE_LIST))) +FIRMWARE_UPGRADE_PATH = $(abspath $(MAKEFILE_FILE_PATH)/../../include) +EXTRA_CFLAGS+= -I$(FIRMWARE_UPGRADE_PATH) +EXTRA_CFLAGS+= -Wall + +firmware_driver_cpld-objs := firmware.o +firmware_driver_cpld-objs += firmware_cpld.o firmware_cpld_upgrade.o +firmware_driver_cpld-objs += jbicomp.o jbijtag.o jbimain.o jbistub.o + +#ifndef CONFIG_FRM_PRODUCT_FILE + +$(warning $(firmware_driver_cpld-objs)) +obj-m := firmware_driver_cpld.o +all: + $(MAKE) -C $(KERNEL_SRC)/build M=$(PWD) modules + @if [ ! -d $(common_module_dir) ]; then mkdir -p $(common_module_dir) ;fi + cp -p $(PWD)/*.ko $(common_module_dir) diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/firmware.c b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/firmware.c new file mode 100644 index 000000000000..db72b369465a --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/firmware.c @@ -0,0 +1,144 @@ +#include +#include +#include + +int g_firmware_driver_debug = 0; +module_param(g_firmware_driver_debug, int, S_IRUGO | S_IWUSR); + +static LIST_HEAD(drv_list); +static LIST_HEAD(dev_list); + +/** + * firmware_driver_register + * function:Registered Device Driver + * @fw_drv:param[in] Driver information + * return value : success--FIRMWARE_SUCCESS; fail--FIRMWARE_FAILED + */ +int firmware_driver_register(firmware_driver_t *fw_drv) +{ + int ret; + + if (fw_drv == NULL) { + FIRMWARE_DRIVER_DEBUG_ERROR("Parameter error.\n"); + return FIRMWARE_FAILED; + } + + ret = platform_driver_register(fw_drv->drv); + if (ret < 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("Error: failed to register firmware upgrade driver \n"); + return FIRMWARE_FAILED; + } + + /* Adds driver information to the driver list */ + list_add(&fw_drv->list, &drv_list); + FIRMWARE_DRIVER_DEBUG_VERBOSE("firmware upgrade driver register sucess \n"); + + return FIRMWARE_SUCCESS; +} + +/** + * firmware_driver_unregister + * function:unregister Device Driver + * @fw_drv:param[in] Driver information + */ +void firmware_driver_unregister(firmware_driver_t *fw_drv) +{ + list_del_init(&fw_drv->list); + platform_driver_unregister(fw_drv->drv); +} + +/* + * firmware_get_device_by_minor + * function: Get device information based on minor + */ +firmware_device_t *firmware_get_device_by_minor(int minor) +{ + firmware_device_t *tmp; + + list_for_each_entry(tmp, &dev_list, list) { + if (tmp->dev.minor == minor) { + return tmp; + } + } + + return NULL; +} + +/** + * firmware_device_register + * function:Registered Driver Device + * @fw_dev: param[in] Driver information + * return value:success--FIRMWARE_SUCCESS; fail--FIRMWARE_FAILED + */ +int firmware_device_register(firmware_device_t *fw_dev) +{ + int ret; + firmware_device_t *tmp; + + if (fw_dev == NULL) { + FIRMWARE_DRIVER_DEBUG_ERROR("Parameter error.\n"); + return FIRMWARE_FAILED; + } + /* Check whether the device file name already exists in the device linked list */ + list_for_each_entry(tmp, &dev_list, list) { + if (strcmp(tmp->name, fw_dev->name) == 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("devie %s already exists.\n", fw_dev->name); + return FIRMWARE_FAILED; + } + } + + /* Registere device */ + ret = misc_register(&fw_dev->dev); + if (ret < 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("register misc error, ret=%d.\n", ret); + return FIRMWARE_FAILED; + } + + /* Adds a device to the device list */ + list_add(&fw_dev->list, &dev_list); + + return FIRMWARE_SUCCESS; +} + +/** + * firmware_device_unregister + * function: unregister Driver Device + */ +void firmware_device_unregister(firmware_device_t *fw_dev) +{ + list_del(&fw_dev->list); + misc_deregister(&fw_dev->dev); +} + +static int __init firmware_driver_init(void) +{ + int ret; + + INIT_LIST_HEAD(&drv_list); + INIT_LIST_HEAD(&dev_list); + FIRMWARE_DRIVER_DEBUG_VERBOSE("firmware driver init.\n"); + ret = firmware_cpld_init(); + if (ret < 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("firmware driver init failed.\n"); + return FIRMWARE_FAILED; + } + + return FIRMWARE_SUCCESS; +} + +static void __exit firmware_driver_exit(void) +{ + FIRMWARE_DRIVER_DEBUG_VERBOSE("firmware driver exit.\n"); + firmware_cpld_exit(); + INIT_LIST_HEAD(&drv_list); + INIT_LIST_HEAD(&dev_list); + return; +} + +module_init(firmware_driver_init); +module_exit(firmware_driver_exit); + +MODULE_AUTHOR("support"); +MODULE_DESCRIPTION("Firmware upgrade driver"); +MODULE_LICENSE("GPL"); +MODULE_VERSION("1.0"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/firmware_cpld.c b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/firmware_cpld.c new file mode 100644 index 000000000000..18ec509d0f2e --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/firmware_cpld.c @@ -0,0 +1,384 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static int firmware_cpld_open(struct inode *inode, struct file *file) +{ + firmware_device_t *frm_dev; + + FIRMWARE_DRIVER_DEBUG_VERBOSE("Open cpld device.\n"); + frm_dev = firmware_get_device_by_minor(MINOR(inode->i_rdev)); + if (frm_dev == NULL) { + return -ENXIO; + } + file->private_data = frm_dev; + + return FIRMWARE_SUCCESS; +} + +static ssize_t firmware_cpld_read (struct file *file, char __user *buf, size_t count, + loff_t *offset) +{ + return 0; +} + +static ssize_t firmware_cpld_write (struct file *file, const char __user *buf, size_t count, + loff_t *offset) +{ + return 0; +} + +static loff_t firmware_cpld_llseek(struct file *file, loff_t offset, int origin) +{ + return 0; +} + +/* + * firmware_cpld_ioctl + * function: ioctl command parsing function + * @file: param[in] device file name + * @cmd: param[in] command + * @arg: param[in] the parameters in the command + * return value: success-FIRMWARE_SUCCESS; fail:other value + */ +static long firmware_cpld_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + int ret; + char *buf; + void __user *argp; + char version[FIRMWARE_NAME_LEN]; + char chip_name[FIRMWARE_NAME_LEN]; + cmd_info_t cmd_info; + firmware_device_t *frm_dev; + firmware_cpld_t *cpld_info; + + /* Get device private data */ + mem_clear(&cmd_info, sizeof(cmd_info_t)); + frm_dev = (firmware_device_t *)file->private_data; + cpld_info = NULL; + if (frm_dev != NULL) { + if (frm_dev->priv != NULL) { + cpld_info = (firmware_cpld_t *)frm_dev->priv; + } + } + if (cpld_info == NULL) { + FIRMWARE_DRIVER_DEBUG_ERROR("Error: Failed to frm_dev->priv sysfs info.\n"); + return FIRMWARE_FAILED; + } + argp = (void __user *)arg; + + switch (cmd) { + case FIRMWARE_GET_CHIPNAME: + /* get chip name */ + if (copy_from_user(&cmd_info, argp, sizeof(cmd_info_t))) { + return -EFAULT; + } + mem_clear(chip_name, FIRMWARE_NAME_LEN); + ret = fmw_cpld_upg_get_chip_name(frm_dev->chain, cpld_info, chip_name, FIRMWARE_NAME_LEN); + if (ret != FIRMWARE_SUCCESS) { + FIRMWARE_DRIVER_DEBUG_ERROR("Failed to get chip name.\n"); + return -ENXIO; + } + if (copy_to_user(cmd_info.data, chip_name, cmd_info.size)) { + return -EFAULT; + } + break; + case FIRMWARE_PROGRAM: + case FIRMWARE_PROGRAM_JBI: + /* firmware upgrade */ + if (copy_from_user(&cmd_info, argp, sizeof(cmd_info_t))) { + return -EFAULT; + } + buf = (char *) kzalloc(cmd_info.size + 1, GFP_KERNEL); + if (buf == NULL) { + return -ENOMEM; + } + if (copy_from_user(buf, cmd_info.data, cmd_info.size)) { + kfree(buf); + return -EFAULT; + } + buf[cmd_info.size] = 0; + if (cmd == FIRMWARE_PROGRAM_JBI) { + /* JBI firmware upgrade */ + ret = fmw_cpld_upg_program_jbi(frm_dev->chain, cpld_info, buf, cmd_info.size); + } else { + /* ISC firmware upgrade */ + ret = fmw_cpld_upg_program(frm_dev->chain, cpld_info, buf, cmd_info.size); + } + if (ret != FIRMWARE_SUCCESS) { + FIRMWARE_DRIVER_DEBUG_ERROR("Failed to program cpld.\n"); + kfree(buf); + return -ESRCH; + } + kfree(buf); + break; + case FIRMWARE_GET_VERSION: + /* get version */ + if (copy_from_user(&cmd_info, argp, sizeof(cmd_info_t))) { + return -EFAULT; + } + mem_clear(version, FIRMWARE_NAME_LEN); + ret = fmw_cpld_upg_get_version(frm_dev->chain, cpld_info, version, FIRMWARE_NAME_LEN); + if (ret != FIRMWARE_SUCCESS) { + FIRMWARE_DRIVER_DEBUG_ERROR("Failed to get version.\n"); + return -ENXIO; + } + if (copy_to_user(cmd_info.data, version, cmd_info.size)) { + return -EFAULT; + } + break; + default: + FIRMWARE_DRIVER_DEBUG_ERROR("not find cmd: %d\r\n", cmd); + return -ENOTTY; + } /* End of switch */ + + return FIRMWARE_SUCCESS; +} + +static int firmware_cpld_release(struct inode *inode, struct file *file) +{ + return 0; +} + +static const struct file_operations cpld_dev_fops = { + .owner = THIS_MODULE, + .llseek = firmware_cpld_llseek, + .read = firmware_cpld_read, + .write = firmware_cpld_write, + .unlocked_ioctl = firmware_cpld_ioctl, + .open = firmware_cpld_open, + .release = firmware_cpld_release, +}; + +static int of_firmware_upgrade_config_init(struct device *dev, firmware_cpld_t *cpld_info) +{ + int ret; + char *name; + int i; + char buf[64]; + + FIRMWARE_DRIVER_DEBUG_VERBOSE("Enter firmware_upgrade_config_init\r\n"); + if (cpld_info == NULL) { + FIRMWARE_DRIVER_DEBUG_ERROR("info is null\r\n"); + return -1; + } + + mem_clear(cpld_info, sizeof(firmware_cpld_t)); + ret = 0; + ret += of_property_read_string(dev->of_node, "type", (const char **)&name); + ret += of_property_read_u32(dev->of_node, "tdi", &cpld_info->tdi); + ret += of_property_read_u32(dev->of_node, "tck", &cpld_info->tck); + ret += of_property_read_u32(dev->of_node, "tms", &cpld_info->tms); + ret += of_property_read_u32(dev->of_node, "tdo", &cpld_info->tdo); + + ret += of_property_read_u32(dev->of_node, "chain", &cpld_info->chain); + ret += of_property_read_u32(dev->of_node, "chip_index", &cpld_info->chip_index); + + if (ret != 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("dts config error, ret:%d.\n", ret); + return -ENXIO; + } + + strncpy(cpld_info->type, name, sizeof(cpld_info->type) - 1); + + ret = of_property_read_u32(dev->of_node, "tck_delay", &cpld_info->tck_delay); + if(ret != 0) { + cpld_info->tck_delay = 60; + } + + cpld_info->gpio_en_info_num = 0; + /* Enable through GPIO */ + for (i = 0; i < FIRMWARE_EN_INFO_MAX; i++) { + mem_clear(buf, sizeof(buf)); + snprintf(buf, sizeof(buf) - 1, "en_gpio_%d", i); + ret = of_property_read_u32(dev->of_node, buf, &cpld_info->gpio_en_info[i].en_gpio); + if(ret != 0) { + break; + } + + mem_clear(buf, sizeof(buf)); + snprintf(buf, sizeof(buf) - 1, "en_level_%d", i); + ret = of_property_read_u32(dev->of_node, buf, &cpld_info->gpio_en_info[i].en_level); + if(ret != 0) { + break; + } + cpld_info->gpio_en_info_num++; + } + + FIRMWARE_DRIVER_DEBUG_VERBOSE("type:%s, chain:%u, chip_index:%u, en_info_num:%u\n", + cpld_info->type, cpld_info->chain, cpld_info->chip_index, cpld_info->gpio_en_info_num); + FIRMWARE_DRIVER_DEBUG_VERBOSE("tdi:%u, tck:%u, tms:%u, tdo:%u tck_delay:%u.\n", + cpld_info->tdi, cpld_info->tck, cpld_info->tms, cpld_info->tdo, cpld_info->tck_delay); + + return 0; +} + +static int firmware_upgrade_config_init(struct device *dev, firmware_cpld_t *cpld_info) +{ + int i; + + firmware_upgrade_device_t *firmware_upgrade_device; + firmware_jtag_device_t jtag_upg_device; + + FIRMWARE_DRIVER_DEBUG_VERBOSE("Enter firmware_upgrade_config_init\r\n"); + if (cpld_info == NULL) { + FIRMWARE_DRIVER_DEBUG_ERROR("info is null\r\n"); + return -1; + } + + if (dev->platform_data == NULL) { + FIRMWARE_DRIVER_DEBUG_ERROR("platform data config error.\n"); + return -1; + } + firmware_upgrade_device = dev->platform_data; + jtag_upg_device = firmware_upgrade_device->upg_type.jtag; + + mem_clear(cpld_info, sizeof(firmware_cpld_t)); + + strncpy(cpld_info->type, firmware_upgrade_device->type, sizeof(cpld_info->type) - 1); + cpld_info->tdi = jtag_upg_device.tdi; + cpld_info->tck = jtag_upg_device.tck; + cpld_info->tms = jtag_upg_device.tms; + cpld_info->tdo = jtag_upg_device.tdo; + cpld_info->chain = firmware_upgrade_device->chain; + cpld_info->chip_index = firmware_upgrade_device->chip_index; + + if (jtag_upg_device.tck_delay == 0) { + cpld_info->tck_delay = 60; + FIRMWARE_DRIVER_DEBUG_VERBOSE("no config tck_delay, use default value:%u\n", cpld_info->tck_delay); + } else { + cpld_info->tck_delay = jtag_upg_device.tck_delay; + } + + if (firmware_upgrade_device->en_gpio_num > FIRMWARE_EN_INFO_MAX) { + FIRMWARE_DRIVER_DEBUG_ERROR("The number of en_gpio_num:%u configurations exceeds the maximum limit:%u.\n", + firmware_upgrade_device->en_gpio_num, FIRMWARE_EN_INFO_MAX); + return -ENXIO; + } + cpld_info->gpio_en_info_num = firmware_upgrade_device->en_gpio_num; + /* Enable through GPIO */ + for (i = 0; i < cpld_info->gpio_en_info_num; i++) { + cpld_info->gpio_en_info[i].en_gpio = firmware_upgrade_device->en_gpio[i]; + cpld_info->gpio_en_info[i].en_level = firmware_upgrade_device->en_level[i]; + } + + FIRMWARE_DRIVER_DEBUG_VERBOSE("type:%s, chain:%u, chip_index:%u, en_info_num:%u\n", + cpld_info->type, cpld_info->chain, cpld_info->chip_index, cpld_info->gpio_en_info_num); + FIRMWARE_DRIVER_DEBUG_VERBOSE("tdi:%u, tck:%u, tms:%u, tdo:%u tck_delay:%u.\n", + cpld_info->tdi, cpld_info->tck, cpld_info->tms, cpld_info->tdo, cpld_info->tck_delay); + + return 0; +} + +static int firmware_cpld_probe(struct platform_device *pdev) +{ + int ret; + firmware_cpld_t *cpld_info; + firmware_device_t *frm_dev; + + FIRMWARE_DRIVER_DEBUG_VERBOSE("Enter firmware_cpld_probe\r\n"); + /* Gets the information in the device tree */ + cpld_info = devm_kzalloc(&pdev->dev, sizeof(firmware_cpld_t), GFP_KERNEL); + if (cpld_info == NULL) { + FIRMWARE_DRIVER_DEBUG_ERROR("Failed to kzalloc cpld device tree.\n"); + return -EPERM; + } + + if (pdev->dev.of_node) { + ret = of_firmware_upgrade_config_init(&pdev->dev, cpld_info); + } else { + ret = firmware_upgrade_config_init(&pdev->dev, cpld_info); + } + if (ret < 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("get config init from dts error.\n"); + return -EPERM; + } + + frm_dev = devm_kzalloc(&pdev->dev, sizeof(firmware_device_t), GFP_KERNEL); + if (frm_dev == NULL) { + FIRMWARE_DRIVER_DEBUG_ERROR("Failed to kzalloc firmware device.\n"); + return -EPERM; + } + + /* Based on the link number, determine the name of the device file */ + frm_dev->chain = cpld_info->chain; + snprintf(frm_dev->name, FIRMWARE_NAME_LEN - 1, "firmware_cpld%d", frm_dev->chain); + strncpy(cpld_info->devname, frm_dev->name, strlen(frm_dev->name) + 1); + + INIT_LIST_HEAD(&frm_dev->list); + frm_dev->dev.minor = MISC_DYNAMIC_MINOR; + frm_dev->dev.name = frm_dev->name; + frm_dev->dev.fops = &cpld_dev_fops; + frm_dev->priv = cpld_info; + + FIRMWARE_DRIVER_DEBUG_VERBOSE("Register cpld firmware chain:%d, name:%s.\n", frm_dev->chain, frm_dev->name); + + ret = firmware_device_register(frm_dev); + if (ret < 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("Failed to register firmware device.\n"); + return -EPERM; + } + + platform_set_drvdata(pdev, frm_dev); + return 0; +} + +static int __exit firmware_cpld_remove(struct platform_device *pdev) +{ + firmware_device_t *frm_dev; + + frm_dev = (firmware_device_t *)platform_get_drvdata(pdev); + firmware_device_unregister(frm_dev); + platform_set_drvdata(pdev, NULL); + + return 0; +} + +static struct of_device_id cpld_match[] = { + { + .compatible = "firmware_cpld", + }, + {}, +}; + +static struct platform_driver cpld_driver = { + .driver = { + .name = "firmware_cpld", + .owner = THIS_MODULE, + .of_match_table = cpld_match, + }, + .probe = firmware_cpld_probe, + .remove = firmware_cpld_remove, +}; + +static firmware_driver_t fmw_drv_cpld = { + .name = "firmware_cpld", + .drv = &cpld_driver, +}; + +int firmware_cpld_init(void) +{ + int ret; + + INIT_LIST_HEAD(&fmw_drv_cpld.list); + FIRMWARE_DRIVER_DEBUG_VERBOSE("cpld upgrade driver register \n"); + ret = firmware_driver_register(&fmw_drv_cpld); + if (ret < 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("cpld upgrade driver register failed.\n"); + return ret; + } + return 0; +} + +void firmware_cpld_exit(void) +{ + firmware_driver_unregister(&fmw_drv_cpld); + INIT_LIST_HEAD(&fmw_drv_cpld.list); +} diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/firmware_cpld_upgrade.c b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/firmware_cpld_upgrade.c new file mode 100644 index 000000000000..8252c2a39bb2 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/firmware_cpld_upgrade.c @@ -0,0 +1,1879 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* CPLD file parses the relevant parameters */ +#define CPLD_HEX 16 +#define DEC_VAL 10 +#define CPLD_INIT_CNT 4 +#define CPLD_UNIT_SZ 4 +#define CPLD_HEAD_KEYWORD "Header" +#define CPLD_NAME_KEYWORD "Entity" +#define CPLD_INIT_KEYWORD "INITIALIZE" +#define CPLD_REPEAT_KEYWORD "REPEAT" +#define CPLD_END_CHAR ',' + +/* TCK clock MAX 16MHz */ +#define TCK_DELAY (current_fmw_cpld->tck_delay) + +/* + * The instruction format of the MAX II CPLD is 10 bits + * For shift_ir state machine use + */ +#define BYPASS 0x3FF +#define EXTEST 0xF +#define SAMPLE 0x5 +#define IDCODE 0x6 +#define USERCODE 0x7 +#define CLAMP 0xA +#define HIGHZ 0xB + +/* Following 7 instructions are IEEE 1532 instructions */ +#define ISC_ENABLE 0x2CC +#define ISC_DISABLE 0x201 +#define ISC_PROGRAM 0x2F4 +#define ISC_ERASE 0x2F2 +#define ISC_ADDRESS_SHIFT 0x203 +#define ISC_READ 0x205 +#define ISC_NOOP 0x210 + +/* + * MAX II devices support the real-time in-system programmability (ISP) + * feature that allows you to program the device while it is still in operation. + * when there is either a power cycle to the device (powering down and powering + * up again) or with the execution of certain ISP instructions to start the SRAM + * download process when realtime ISP has completed. + */ +#define RT_ISC_ENABLE 0x199 +#define RT_ISC_DISABLE 0x166 + +/* Chip ID */ +#define EPM240_G 0x020A10DD +#define EPM570_G 0x020A20DD +#define EPM1270_G 0x020A30DD +#define EPM2210_G 0x020A40DD +#define EPM240_Z 0x020A50DD +#define EPM570_Z 0x020A60DD + +/* The size of the output data for ID validation */ +#define VERIFY_IDCODE_SIZE 0x5 + +/* Erasure and programmatic delay handling */ +#define ERASE_DELAY 0x1024 +#define PROGRAM_DELAY 0x5 + +/* Chip instruction register */ +#define CPLD_INSTRUCTION_SIZE 10 + +/* + * Currently, only two connectors are supported + * The size of the instruction register needs to be changed + * when more than two connectors are used + */ +#ifndef CPLD_MAX_CHIP +#define CPLD_MAX_CHIP 2 +#endif + +typedef struct cpld_chip_id { + char *name; + uint id; + int addr_register_length; + int data_register_length; + int eeprom_array_length; + int first_blank_check_length; + int second_blank_check_length; + int first_erase_addr; + int second_erase_addr; + int third_erase_addr; + int verify_idcode_addr; +} cpld_chip_id_t; + +static cpld_chip_id_t cpld_id_table[] = { + {"EPM240T100", EPM240_G, 13, 16, 4604, 3327, 511, 0x0, 0x1, 0x11, 0x89}, + {"EPM570T144", EPM570_G, 14, 16, 8700, 3327, 511, 0x0, 0x1, 0x21, 0x111}, + {"EPM1270F256", EPM1270_G, 15, 16, 16892, 16383, 511, 0x0, 0x1, 0x41, 0x221}, + {"5M240Z", EPM240_Z, 13, 16, 4604, 3327, 511, 0x0, 0x1, 0x11, 0x89}, + {"5M570Z", EPM570_Z, 14, 16, 8700, 3327, 511, 0x0, 0x1, 0x21, 0x111}, + {NULL, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, +}; + +static cpld_chip_id_t *chip_cpld_info = NULL; + +/* The following variables are used when cascading multiple chips */ +static int chip_num, current_chip_index; +static firmware_cpld_t *current_fmw_cpld; + +static int TDI_PULL_UP(void); +static int TDI_PULL_DOWN(void); +static int TMS_PULL_UP(void); +static int TMS_PULL_DOWN(void); +static int TCK_PULL_UP(void); +static int TCK_PULL_DOWN(void); + +/* + * set_currrent_cpld_info + * function: Save the current device information + * @info: param[in] Information about the device to be updated + */ +static void set_currrent_cpld_info(firmware_cpld_t *info) +{ + current_fmw_cpld = info; +} + +/* + * firmware_upgrade_en + * function: Upgrade access enabling switch + * @flag: !0:enable 0:disable + */ +static int firmware_upgrade_en(int flag) +{ + int i; + int ret; + + for (i = 0; i < current_fmw_cpld->gpio_en_info_num; i++) { + if (flag) { + ret = gpio_request(current_fmw_cpld->gpio_en_info[i].en_gpio, "cpld_upgrade"); + if (ret) { + FIRMWARE_DRIVER_DEBUG_ERROR("Requesting cpld_ispvme_upgrade EN[%d] GPIO[%d] failed!\n", + i, current_fmw_cpld->gpio_en_info[i].en_gpio); + goto free_gpio; + } + gpio_direction_output(current_fmw_cpld->gpio_en_info[i].en_gpio, current_fmw_cpld->gpio_en_info[i].en_level); + current_fmw_cpld->gpio_en_info[i].flag = 1; + } else { + gpio_set_value(current_fmw_cpld->gpio_en_info[i].en_gpio, !current_fmw_cpld->gpio_en_info[i].en_level); + gpio_free(current_fmw_cpld->gpio_en_info[i].en_gpio); + current_fmw_cpld->gpio_en_info[i].flag = 0; + } + } + return 0; +free_gpio: + for (i = 0; i < current_fmw_cpld->gpio_en_info_num; i++) { + if (current_fmw_cpld->gpio_en_info[i].flag == 1) { + gpio_set_value(current_fmw_cpld->gpio_en_info[i].en_gpio, !current_fmw_cpld->gpio_en_info[i].en_level); + gpio_free(current_fmw_cpld->gpio_en_info[i].en_gpio); + current_fmw_cpld->gpio_en_info[i].flag = 0; + } else { + break; + } + } + + return -1; +} + +/* + * init_cpld + * function:Initialize CPLD + * return value: 0 success ; -1 fail + */ +static int init_cpld(void) +{ + int ret; + + if (current_fmw_cpld == NULL) { + return -1; + } + mdelay(10); + ret = gpio_request(current_fmw_cpld->tdi, "cpld_upgrade"); + if (ret) { + FIRMWARE_DRIVER_DEBUG_ERROR("Requesting cpld_upgrade TDI GPIO failed!\n"); + return ret; + } + ret = gpio_request(current_fmw_cpld->tck, "cpld_upgrade"); + if (ret) { + FIRMWARE_DRIVER_DEBUG_ERROR("Requesting cpld_upgrade TCK GPIO failed!\n"); + goto free_tdi; + } + ret = gpio_request(current_fmw_cpld->tms, "cpld_upgrade"); + if (ret) { + FIRMWARE_DRIVER_DEBUG_ERROR("Requesting cpld_upgrade TMS GPIO failed!\n"); + goto free_tck; + } + ret = gpio_request(current_fmw_cpld->tdo, "cpld_upgrade"); + if (ret) { + FIRMWARE_DRIVER_DEBUG_ERROR("Requesting cpld_upgrade TDO GPIO failed!\n"); + goto free_tms; + } + + gpio_direction_output(current_fmw_cpld->tdi, 1); + gpio_direction_output(current_fmw_cpld->tck, 1); + gpio_direction_output(current_fmw_cpld->tms, 1); + + gpio_direction_input(current_fmw_cpld->tdo); + ret = firmware_upgrade_en(1); + if (ret) { + FIRMWARE_DRIVER_DEBUG_ERROR("Error: open firmware upgrade en failed, ret %d.\n", ret); + goto free_tdo; + } + + /* test GPIO */ + if (TDI_PULL_UP() < 0 ) { + FIRMWARE_DRIVER_DEBUG_ERROR("Error: TDI_PULL_UP failed.\n"); + goto free_tdo; + } + if (TDI_PULL_DOWN() < 0 ) { + FIRMWARE_DRIVER_DEBUG_ERROR("Error: TDI_PULL_DOWN failed.\n"); + goto free_tdo; + } + if (TMS_PULL_UP() < 0 ) { + FIRMWARE_DRIVER_DEBUG_ERROR("Error: TMS_PULL_UP failed.\n"); + goto free_tdo; + } + if (TMS_PULL_DOWN() < 0 ) { + FIRMWARE_DRIVER_DEBUG_ERROR("Error: TMS_PULL_DOWN failed.\n"); + goto free_tdo; + } + if (TCK_PULL_UP() < 0 ) { + FIRMWARE_DRIVER_DEBUG_ERROR("Error: TCK_PULL_UP failed.\n"); + goto free_tdo; + } + if (TCK_PULL_DOWN() < 0 ) { + FIRMWARE_DRIVER_DEBUG_ERROR("Error: TCK_PULL_DOWN failed.\n"); + goto free_tdo; + } + + mdelay(10); + return 0; + +free_tdo: + gpio_free(current_fmw_cpld->tdo); +free_tms: + gpio_free(current_fmw_cpld->tms); +free_tck: + gpio_free(current_fmw_cpld->tck); +free_tdi: + gpio_free(current_fmw_cpld->tdi); + return ret; +} + +/* + * finish_cpld + * function: finish CPLD upgrade operation + * return value: 0 success ; -1 fail + */ +static int finish_cpld(void) +{ + int ret; + + if (current_fmw_cpld == NULL) { + return -1; + } + mdelay(10); + ret = firmware_upgrade_en(0); + if (ret < 0){ + FIRMWARE_DRIVER_DEBUG_ERROR("Error: close firmware upgrade en failed, ret %d.\r\n", ret); + } + + gpio_free(current_fmw_cpld->tdi); + gpio_free(current_fmw_cpld->tck); + gpio_free(current_fmw_cpld->tms); + gpio_free(current_fmw_cpld->tdo); + mdelay(10); + return 0; +} + +/* Loop waiting for */ +static int pull_wait(int gpio, int value) { + int i, j; + /* Timeout time is two seconds */ + for (i = 0; i < 20; i++) { + for (j = 0; j < 100; j++) { + if (!!gpio_get_value(gpio) == !!value ) { + return 0; + } + /* The first loop does not delay, normally the first loop can immediately return the result */ + if (i) { + mdelay(1); + } + } + /* The CPU is released every 100ms */ + schedule(); + } + /* timeout */ + FIRMWARE_DRIVER_DEBUG_ERROR("Error: Wait gpio %d pull to %d failed.\n", gpio, value); + return -1; +} + +/* TDI pull-up */ +static int pull_tdi_up(void) +{ + if (current_fmw_cpld == NULL) { + return -1; + } + gpio_set_value(current_fmw_cpld->tdi, 1); + + /* Wait for the GPIO value to be set successfully */ + return pull_wait(current_fmw_cpld->tdi, 1); +} + +/* TDI pull-down */ +static int pull_tdi_down(void) +{ + if (current_fmw_cpld == NULL) { + return -1; + } + gpio_set_value(current_fmw_cpld->tdi, 0); + + /* Wait for the GPIO value to be set successfully */ + return pull_wait(current_fmw_cpld->tdi, 0); +} + +/* TCK pull-up */ +static int pull_tck_up(void) +{ + if (current_fmw_cpld == NULL) { + return -1; + } + gpio_set_value(current_fmw_cpld->tck, 1); + + /* Wait for the GPIO value to be set successfully */ + return pull_wait(current_fmw_cpld->tck, 1); +} + +/* TCK pull-down */ +static int pull_tck_down(void) +{ + if (current_fmw_cpld == NULL) { + return -1; + } + gpio_set_value(current_fmw_cpld->tck, 0); + + /* Wait for the GPIO value to be set successfully */ + return pull_wait(current_fmw_cpld->tck, 0); +} + +/* TMS pull-up */ +static int pull_tms_up(void) +{ + if (current_fmw_cpld == NULL) { + return -1; + } + gpio_set_value(current_fmw_cpld->tms, 1); + + /* Wait for the GPIO value to be set successfully */ + return pull_wait(current_fmw_cpld->tms, 1); +} + +/* TMS pull-down */ +static int pull_tms_down(void) +{ + if (current_fmw_cpld == NULL) { + return -1; + } + gpio_set_value(current_fmw_cpld->tms, 0); + + /* Wait for the GPIO value to be set successfully */ + return pull_wait(current_fmw_cpld->tms, 0); +} + +/* Read TDO */ +static int read_tdo(void) +{ + if (current_fmw_cpld == NULL) { + return -1; + } + return gpio_get_value(current_fmw_cpld->tdo); +} + +static firmware_cpld_function_t function_fmw_cpld = { + .pull_tdi_up = pull_tdi_up, + .pull_tdi_down = pull_tdi_down, + .pull_tck_up = pull_tck_up, + .pull_tck_down = pull_tck_down, + .pull_tms_up = pull_tms_up, + .pull_tms_down = pull_tms_down, + .read_tdo = read_tdo, + .init_cpld = init_cpld, + .finish_cpld = finish_cpld, +}; + +/* + * TDI_PULL_DOWN + * function: Lower TDI + */ +static int TDI_PULL_DOWN(void) +{ + if ( function_fmw_cpld.pull_tdi_down != NULL) { + return function_fmw_cpld.pull_tdi_down(); + } else { + FIRMWARE_DRIVER_DEBUG_ERROR("NO support TDI_PULL_DOWN.\n"); + return -1; + } +} + +/* + * TDI_PULL_UP + * function: High TDI + */ +static int TDI_PULL_UP(void) +{ + if (function_fmw_cpld.pull_tdi_up != NULL) { + return function_fmw_cpld.pull_tdi_up(); + } else { + FIRMWARE_DRIVER_DEBUG_ERROR("NO support TDI_PULL_UP.\n"); + return -1; + } +} + +/* + * TCK_PULL_DOWN + * function: Lower TCK + */ +static int TCK_PULL_DOWN(void) +{ + if (function_fmw_cpld.pull_tck_down != NULL) { + return function_fmw_cpld.pull_tck_down(); + } else { + FIRMWARE_DRIVER_DEBUG_ERROR("NO support TCK_PULL_DOWN.\n"); + return -1; + } +} + +/* + * TCK_PULL_UP + * function: High TCK + */ +static int TCK_PULL_UP(void) +{ + if (function_fmw_cpld.pull_tck_up != NULL) { + return function_fmw_cpld.pull_tck_up(); + } else { + FIRMWARE_DRIVER_DEBUG_ERROR("NO support TCK_PULL_UP.\n"); + return -1; + } +} + +/* + * TMS_PULL_DOWN + * function: Lower TMS + */ +static int TMS_PULL_DOWN(void) +{ + if (function_fmw_cpld.pull_tms_down != NULL) { + return function_fmw_cpld.pull_tms_down(); + } else { + FIRMWARE_DRIVER_DEBUG_ERROR("NO support TMS_PULL_DOWN.\n"); + return -1; + } +} + +/* + * TMS_PULL_UP + * function: High TMS + */ +static int TMS_PULL_UP(void) +{ + if (function_fmw_cpld.pull_tms_up != NULL) { + return function_fmw_cpld.pull_tms_up(); + } else { + FIRMWARE_DRIVER_DEBUG_ERROR("NO support TMS_PULL_UP.\n"); + return -1; + } +} + +/* + * TDO_READ + * function:Read the TDO level + */ +static int TDO_READ(void) +{ + if (function_fmw_cpld.read_tdo != NULL) { + return function_fmw_cpld.read_tdo(); + } else { + FIRMWARE_DRIVER_DEBUG_ERROR("NO support TDO_READ.\n"); + return -1; + } +} + +/* + * tap_test_logic_reset + * function: reset JTAG + * No matter what the original state of the controoler, it will enter + * Test_Logic_Reset when TMS is held high for at least five rising + * edges of TCK (16MHz) + * The controller remains in this state while TMS is high + */ +static void tap_test_logic_reset(void) +{ + int i; + TMS_PULL_UP(); + TCK_PULL_DOWN(); + ndelay(TCK_DELAY); + + for (i = 0; i < 5; i++) { + TCK_PULL_UP(); + ndelay(TCK_DELAY); + TCK_PULL_DOWN(); + ndelay(TCK_DELAY); + } + TCK_PULL_UP(); + ndelay(TCK_DELAY); +} + +/* + * tap_run_test_idle + * function: A controller state between scan operations.Once entered, the controller + * will remain in the Run_Test/Idle state as long as TMS is held low. + */ +static void tap_run_test_idle(void) +{ + TMS_PULL_DOWN(); + TCK_PULL_DOWN(); + ndelay(TCK_DELAY); + TCK_PULL_UP(); + ndelay(TCK_DELAY); +} + +/* + * tap_select_dr_scan + * function :This is a temporary controller state in which all test data registers + * selected by the current instruction retain their previous state. + */ +static void tap_select_dr_scan(void) +{ + TMS_PULL_UP(); + TCK_PULL_DOWN(); + ndelay(TCK_DELAY); + TCK_PULL_UP(); + ndelay(TCK_DELAY); +} + +/* + * tap_capture_dr + * function : In this controller state data may be parallel-loaded into test data + * register selected by the current instruction on the rising edge of TCK + */ +static void tap_capture_dr(void) +{ + TMS_PULL_DOWN(); + TCK_PULL_DOWN(); + ndelay(TCK_DELAY); + TCK_PULL_UP(); + ndelay(TCK_DELAY); +} + +/* + * tap_shift_dr + * function: In this controller state.the test data register connected between TDI + * and TDO as a result of the current instruction shifts one stage + * toward its serial output on each rising edge of TCK. + */ +static void tap_shift_dr(void) +{ + TMS_PULL_DOWN(); + TCK_PULL_DOWN(); + ndelay(TCK_DELAY); + TCK_PULL_UP(); + ndelay(TCK_DELAY); +} + +/* + * tap_exit1_dr + * function: This is a temporary controller state. + */ +static void tap_exit1_dr(int data) +{ + int j; + if (data) { + TDI_PULL_UP(); + } else { + TDI_PULL_DOWN(); + } + + /* need to idle here */ + for (j = 1; j < current_chip_index; j++) { + TCK_PULL_DOWN(); + ndelay(TCK_DELAY); + TCK_PULL_UP(); + ndelay(TCK_DELAY); + } + TMS_PULL_UP(); + TCK_PULL_DOWN(); + ndelay(TCK_DELAY); + TCK_PULL_UP(); + ndelay(TCK_DELAY); +} + +/* + * tap_update_dr + * function : Some test data registers may be provided with a latched parallel output to + * prevent changes at the parallel out-put while data is shifted in the + * associated whift-register path in response to certain instructions.Data is + * latched onto the parallel output of these test data registers from the + * shift-register path on the falling edge of TCK in the Update-DR controler state. + */ +static void tap_update_dr(void) +{ + TMS_PULL_UP(); + TCK_PULL_DOWN(); + ndelay(TCK_DELAY); + TCK_PULL_UP(); + ndelay(TCK_DELAY); +} + +/* + * tap_select_ir_scan + * function:This is a temporarily controler state in which all test data register selected + * by the current instruction retain their previous state. + */ +static void tap_select_ir_scan(void) +{ + TMS_PULL_UP(); + TCK_PULL_DOWN(); + ndelay(TCK_DELAY); + TCK_PULL_UP(); + ndelay(TCK_DELAY); +} + +/* + * tap_capture_ir + * function :In this controller state the shift-register contained in the instruction + * register loads a pattern of fixed logic values on the rising edge of + * TCK.design-specific data may be loaded into shift-register stages that + * are not required to be set to fixed values. + */ +static void tap_capture_ir(void) +{ + TMS_PULL_DOWN(); + TCK_PULL_DOWN(); + ndelay(TCK_DELAY); + TCK_PULL_UP(); + ndelay(TCK_DELAY); +} + +/* + * tap_exit1_ir + * function : enter exit1 ir state. This is a temporary controller state. + */ +static void tap_exit1_ir(int data) +{ + if (data) { + TDI_PULL_UP(); + } else { + TDI_PULL_DOWN(); + } + TMS_PULL_UP(); + TCK_PULL_DOWN(); + ndelay(TCK_DELAY); + TCK_PULL_UP(); + ndelay(TCK_DELAY); +} + +/* + * tap_shift_ir + * function: In this controller state the shift-register contained in the instruction + * register is connected between TDI and TDO and shifts data one stage + * toward its serial output on each rising edge of TCK. + */ +static void tap_shift_ir(void) +{ + TMS_PULL_DOWN(); + TCK_PULL_DOWN(); + ndelay(TCK_DELAY); + TCK_PULL_UP(); + ndelay(TCK_DELAY); +} + +/* + * The instruction shifted into the instruction register is latched onto the parallel output + * from the shift-register path on the falling edge of TCK in this controller state.Once the + * new instruction has been latched,it becomes the current instruction. + * + */ +static void tap_update_ir(void) +{ + TMS_PULL_UP(); + TCK_PULL_DOWN(); + ndelay(TCK_DELAY); + TCK_PULL_UP(); + ndelay(TCK_DELAY); +} + +static void tap_send_instruction(int instruction, int ins_len) +{ + int i; + for (i = 0; i < (ins_len - 1); i++) { + if (instruction & 0x1) { + TDI_PULL_UP(); + } else { + TDI_PULL_DOWN(); + } + TCK_PULL_DOWN(); + ndelay(TCK_DELAY); + TCK_PULL_UP(); + ndelay(TCK_DELAY); + instruction = instruction >> 1; + } +} + +static void tap_send_data(int data, int data_len) +{ + int i; + for (i = 0; i < (data_len - 1); i++) { + if (data & 0x1) { + TDI_PULL_UP(); + } else { + TDI_PULL_DOWN(); + } + TCK_PULL_DOWN(); + ndelay(TCK_DELAY); + TCK_PULL_UP(); + ndelay(TCK_DELAY); + data = data >> 1; + } +} + +/* + * tap_rcv_byte + * function : Receive data from the device side + * @data : param[out] Received data */ +static void tap_rcv_byte(u8 *data) +{ + int i; + u8 rec_data = 0; + unsigned char tmp; + ndelay(TCK_DELAY); + for (i = 0; i < 8; i++) { + TCK_PULL_DOWN(); + ndelay(TCK_DELAY); + tmp = TDO_READ(); + rec_data |= (tmp << i); + TCK_PULL_UP(); + ndelay(TCK_DELAY); + } + *data = rec_data; +} + +/* + * tap_idle + * function :Used for state machine idling + */ +static void tap_idle(void) +{ + int i; + for (i = 0; i < 0x100; i++) { + TCK_PULL_DOWN(); + ndelay(TCK_DELAY); + TCK_PULL_UP(); + ndelay(TCK_DELAY); + + /* Timely release of CPU */ + schedule(); + } +} + +/* + * jtag_read_data + * function :Read the JTAG output data + * @size: param[in] buffer size + * @data: param[out] read data buffer + */ +static void jtag_read_data(u8 *buf, int size) +{ + int i, j; + /* JTAG state switching */ + tap_run_test_idle(); + tap_select_dr_scan(); + tap_capture_dr(); + tap_shift_dr(); + for (j = current_chip_index; j < chip_num; j++) { + TCK_PULL_DOWN(); + ndelay(TCK_DELAY); + TCK_PULL_UP(); + ndelay(TCK_DELAY); + } + /* Receive data from the device side */ + for (i = 0; i < size; i++) { + tap_rcv_byte(&buf[i]); + } + /* JTAG state switching */ + tap_exit1_dr(0); + tap_update_dr(); + tap_run_test_idle(); +} + +/* + * jtag_send_instruction + * function :JTAG instruction sending interface + * @instruction: param[in] Instruction to be sent + * @ins_length: param[in] Instruction length + */ +static void jtag_send_instruction(int instruction, int ins_length) +{ + int i, j; + i = 1 << (ins_length - 1); + /* JTAG state switching */ + tap_run_test_idle(); + tap_select_dr_scan(); + tap_select_ir_scan(); + tap_capture_ir(); + tap_shift_ir(); + + for (j = chip_num; j > 1; j--) { + if (j == current_chip_index) { + tap_send_instruction(instruction, ins_length + 1); + } else { + tap_send_instruction(BYPASS, ins_length + 1); + } + } + + if (current_chip_index == 1) { + tap_send_instruction(instruction, ins_length); + /* Gets the highest bit of the instruction */ + tap_exit1_ir((instruction & i) >> (ins_length - 1)); + } else { + tap_send_instruction(BYPASS, ins_length); + /* Gets the highest bit of the instruction */ + tap_exit1_ir((BYPASS & i) >> (ins_length - 1)); + } + + /* JTAG state switching */ + tap_update_ir(); + tap_run_test_idle(); +} + +/* + * jtag_send_data + * function :JTAG data sending interface + * @buf : param[in] Data that needs to be sent + * @data_length: param[in] Data length + */ +static void jtag_send_data(unsigned int buf, int data_length) +{ + int i; + i = 1 << (data_length - 1); + + /* JTAG state switching */ + tap_run_test_idle(); + tap_select_dr_scan(); + tap_capture_dr(); + tap_shift_dr(); + tap_send_data(buf, data_length); + /* Gets the highest bit of the instruction */ + tap_exit1_dr((buf & i) >> (data_length - 1)); + tap_update_dr(); + tap_run_test_idle(); +} + +/* + * jtag_program_donebit + * JTAG programming end point */ +static void jtag_program_donebit(void) +{ + jtag_send_instruction(ISC_ADDRESS_SHIFT, CPLD_INSTRUCTION_SIZE); + tap_idle(); + jtag_send_data(0x0, chip_cpld_info->addr_register_length); + tap_idle(); + + switch (chip_cpld_info->id) { + case EPM240_G: + case EPM570_G: + jtag_send_instruction(ISC_PROGRAM, CPLD_INSTRUCTION_SIZE); + tap_idle(); + jtag_send_data(0x7BFF, chip_cpld_info->data_register_length); + tap_idle(); + break; + case EPM1270_G: + jtag_send_instruction(ISC_PROGRAM, CPLD_INSTRUCTION_SIZE); + tap_idle(); + jtag_send_data(0x7FFF, chip_cpld_info->data_register_length); + tap_idle(); + + jtag_send_instruction(ISC_PROGRAM, CPLD_INSTRUCTION_SIZE); + tap_idle(); + jtag_send_data(0xFFFF, chip_cpld_info->data_register_length); + tap_idle(); + + jtag_send_instruction(ISC_PROGRAM, CPLD_INSTRUCTION_SIZE); + tap_idle(); + jtag_send_data(0xFFBF, chip_cpld_info->data_register_length); + tap_idle(); + + jtag_send_instruction(ISC_PROGRAM, CPLD_INSTRUCTION_SIZE); + tap_idle(); + jtag_send_data(0xFFFF, chip_cpld_info->data_register_length); + tap_idle(); + break; + default: + break; + } /* End of switch */ +} + +/* + * jtag_rt_disable + * JTAG Disable state machine under Real-Time ISP + */ +static void jtag_rt_disable(void) +{ + jtag_send_instruction(RT_ISC_DISABLE, CPLD_INSTRUCTION_SIZE); + tap_idle(); + jtag_send_instruction(BYPASS, CPLD_INSTRUCTION_SIZE); + tap_idle(); +} + +/* + * jtag_verify_idcode + * function :JTAG internal ID reading + */ +static void jtag_verify_idcode(void) +{ + int data, i; + u8 buf[2]; + + jtag_send_instruction(ISC_ADDRESS_SHIFT, CPLD_INSTRUCTION_SIZE); + tap_idle(); + jtag_send_data(chip_cpld_info->verify_idcode_addr, + chip_cpld_info->addr_register_length); + tap_idle(); + for (i = 0; i < VERIFY_IDCODE_SIZE; i++) { + jtag_send_instruction(ISC_READ, CPLD_INSTRUCTION_SIZE); + tap_idle(); + + jtag_read_data(buf, 2); + + /* When validating the ID, the data is compared to the corresponding chip value, + which is retrieved from the BSDL file*/ + data = (buf[1] << 8) | buf[0]; + } +} + +/* + * jtag_rt_enable + * Enter Real-Time ISP mode; JTAG Enable State Machine under Real-Time ISP + */ +static void jtag_rt_enable(void) +{ + jtag_send_instruction(RT_ISC_ENABLE, CPLD_INSTRUCTION_SIZE); + tap_idle(); +} + +/* + * jtag_erase + * JTAG erases the timing + */ +static void jtag_erase(void) +{ + int i; + + jtag_send_instruction(ISC_ADDRESS_SHIFT, CPLD_INSTRUCTION_SIZE); + tap_idle(); + jtag_send_data(chip_cpld_info->first_erase_addr, + chip_cpld_info->addr_register_length); + tap_idle(); + jtag_send_instruction(ISC_ERASE, CPLD_INSTRUCTION_SIZE); + tap_idle(); + for (i = 0; i < ERASE_DELAY; i++) { + tap_idle(); + tap_idle(); + } + + jtag_send_instruction(ISC_ADDRESS_SHIFT, CPLD_INSTRUCTION_SIZE); + tap_idle(); + jtag_send_data(chip_cpld_info->second_erase_addr, + chip_cpld_info->addr_register_length); + tap_idle(); + jtag_send_instruction(ISC_ERASE, CPLD_INSTRUCTION_SIZE); + tap_idle(); + for (i = 0; i < ERASE_DELAY; i++) { + tap_idle(); + tap_idle(); + } + + jtag_send_instruction(ISC_ADDRESS_SHIFT, CPLD_INSTRUCTION_SIZE); + tap_idle(); + jtag_send_data(chip_cpld_info->third_erase_addr, + chip_cpld_info->addr_register_length); + tap_idle(); + jtag_send_instruction(ISC_ERASE, CPLD_INSTRUCTION_SIZE); + tap_idle(); + for (i = 0; i < ERASE_DELAY; i++) { + tap_idle(); + tap_idle(); + } +} + +/* + * jtag_blank_check + * JTAG blank detection */ +static void jtag_blank_check(void) +{ + int j; + int data; + u8 buf[2]; + + jtag_send_instruction(ISC_ADDRESS_SHIFT, CPLD_INSTRUCTION_SIZE); + tap_idle(); + jtag_send_data(0x0, chip_cpld_info->addr_register_length); + tap_idle(); + for (j = 0; j < chip_cpld_info->first_blank_check_length; j++) { + jtag_send_instruction(ISC_READ, CPLD_INSTRUCTION_SIZE); + tap_idle(); + + jtag_read_data(buf, 2); + data = (buf[1] << 8) | buf[0]; + } + + jtag_send_instruction(ISC_ADDRESS_SHIFT, CPLD_INSTRUCTION_SIZE); + tap_idle(); + jtag_send_data(0x1, chip_cpld_info->addr_register_length); + tap_idle(); + for (j = 0; j < chip_cpld_info->second_blank_check_length; j++) { + jtag_send_instruction(ISC_READ, CPLD_INSTRUCTION_SIZE); + tap_idle(); + + jtag_read_data(buf, 2); + data = (buf[1] << 8) | buf[0]; + } +} + +/* + * jtag_verify1 + * function :JTAG content validation + * @buffer : param[in] original data + * return value 0 validation success; -1 validation failed + */ +static int jtag_verify1(unsigned int *buffer) +{ + int j, ret = 0; + unsigned int data; + u8 buf[2]; + + jtag_send_instruction(ISC_ADDRESS_SHIFT, CPLD_INSTRUCTION_SIZE); + tap_idle(); + jtag_send_data(0x0, chip_cpld_info->addr_register_length); + tap_idle(); + for (j = 0; j < chip_cpld_info->eeprom_array_length; j++) { + jtag_send_instruction(ISC_READ, CPLD_INSTRUCTION_SIZE); + tap_idle(); + + jtag_read_data(buf, 2); + data = (buf[1] << 8) | buf[0]; + + if (data != buffer[j]) { + FIRMWARE_DRIVER_DEBUG_ERROR("%d: %02x, %02x.\n", j, data, buffer[j]); + ret = -1; + break; + } + } + return ret; +} + +/* + * jtag_read_buffer + * function:JTAG internal data reading + * @size: param[in] Read size + * @buffer: param[out] Pointer to read data + */ +static void jtag_read_buffer(unsigned int *buffer, int size) +{ + int j; + int data; + u8 buf[2]; + + jtag_send_instruction(ISC_ADDRESS_SHIFT, CPLD_INSTRUCTION_SIZE); + tap_idle(); + jtag_send_data(0x0, chip_cpld_info->addr_register_length); + tap_idle(); + for (j = 0; j < size; j++) { + jtag_send_instruction(ISC_READ, CPLD_INSTRUCTION_SIZE); + tap_idle(); + + jtag_read_data(buf, 2); + data = (buf[1] << 8) | buf[0]; + buffer[j] = data; + } +} + +/* + * jtag_program + * function:JTAG programming timing + * @buffer: param[in] data pointer to program + */ +static void jtag_program(unsigned int *buffer) +{ + int i, j; + + jtag_send_instruction(ISC_ADDRESS_SHIFT, CPLD_INSTRUCTION_SIZE); + tap_idle(); + jtag_send_data(0x0, chip_cpld_info->addr_register_length); + tap_idle(); + for (j = 0; j < chip_cpld_info->eeprom_array_length; j++) { + jtag_send_instruction(ISC_PROGRAM, CPLD_INSTRUCTION_SIZE); + tap_idle(); + + jtag_send_data(buffer[j], chip_cpld_info->data_register_length); + for (i = 0; i < PROGRAM_DELAY; i++) { + tap_idle(); + tap_idle(); + } + } +} + +/* + * cpld_read_id + * function: CPLD chip ID read + * @chip: param[in] chip index + * id : param[out] ID point */ +static void cpld_read_id(int chip, unsigned int *id) +{ + u8 data[sizeof(int)]; + if (!chip_num || chip > chip_num) { + return; + } + current_chip_index = chip; + /* Send instructions */ + jtag_send_instruction(IDCODE, CPLD_INSTRUCTION_SIZE); + /* Read Data */ + jtag_read_data(data, sizeof(int)); + *id = (data[3] << 24) | (data[2] << 16) | (data[1] << 8) | data[0]; +} + +/* + * chip_num_init + * function:CPLD number of chips initialized */ +static void chip_num_init(void) +{ + unsigned int i, id; + unsigned char buf[sizeof(int) * CPLD_MAX_CHIP]; + chip_num = 0; + + /* JTAG state switching */ + tap_run_test_idle(); + tap_select_dr_scan(); + tap_capture_dr(); + tap_shift_dr(); + + for (i = 0; i < sizeof(int) * CPLD_MAX_CHIP; i++) { + tap_rcv_byte(&buf[i]); + } + + /* JTAG state switching */ + tap_exit1_dr(0); + tap_update_dr(); + tap_run_test_idle(); + + for (i = 0; i < sizeof(int) * CPLD_MAX_CHIP; i += 4) { + id = (buf[i + 3] << 24) | (buf[i + 2] << 16) | (buf[i + 1] << 8) | buf[i]; + FIRMWARE_DRIVER_DEBUG_VERBOSE("ID: %04x\n", id); + if (id != 0xFFFFFFFF && id != 0) { + chip_num++; + } + } +} + +/* + * cpld_reset + * function: reset JTAG + * @chip: param[in] chip index + */ +static void cpld_reset(int chip) +{ + unsigned int chip_type_id = 0; + int i; + /* JTAG enters the reset state */ + tap_test_logic_reset(); + /* Gets the number of chips in the CPLD */ + chip_num_init(); + if (!chip_num) { + pr_notice("There is no CPLD chip or the chip is not supported!!\r\n"); + FIRMWARE_DRIVER_DEBUG_ERROR("chip_num == NULL.\n"); + } else { + FIRMWARE_DRIVER_DEBUG_VERBOSE("enter cpld read id.\n"); + current_chip_index = chip; + /* Read chip ID */ + cpld_read_id(current_chip_index, &chip_type_id); + FIRMWARE_DRIVER_DEBUG_VERBOSE("get cpld id: 0x%x.\n", chip_type_id); + for (i = 0; cpld_id_table[i].name != NULL; i++) { + if (cpld_id_table[i].id == chip_type_id) { + chip_cpld_info = &cpld_id_table[i]; + break; + } + } + } + current_chip_index = -1; + tap_test_logic_reset(); +} + +/* + * cpld_program + * function: CPLD programming interface + * @chip: param[in] Chip serial number/chip index + * @buffer: param[in] data pointer to program + * return value: 0 success; -1 fail + */ +static int cpld_program(int chip, unsigned int *buffer) +{ + int ret; + int counte; + + if (!chip_num || chip > chip_num + || chip_cpld_info == NULL) { + return -1; + } + current_chip_index = chip; + + /* Enter Real-Time ISP mode */ + jtag_rt_enable(); + /* JTAG internal ID reading */ + jtag_verify_idcode(); + /* JTAG erases */ + jtag_erase(); + /* JTAG blank detection */ + jtag_blank_check(); + /* JTAG programming timing */ + jtag_program(buffer); + + /* In the process of upgrade, there is a problem with reading data, + * which may occur in the process of reading. Some bit reading fails, + * but the reason is not found. + * Avoidance resolution: perform multiple checks */ + for (counte = 0; counte < 4; counte++) { + ret = jtag_verify1(buffer); + if (counte > 0) { + pr_notice("Verify again(%d).\n", counte + 1); + } + + if (ret == 0) { + break; + } + } + pr_notice("Write chip %d cpld success(%d).\n", chip, ret); + jtag_program_donebit(); + + /* JTAG Disable state machine under Real-Time ISP */ + jtag_rt_disable(); + + return ret; +} + +static void cpld_read_buffer(int chip, unsigned int *buffer, unsigned int size) +{ + if (!chip_num || chip > chip_num + || chip_cpld_info == NULL) { + return; + } + current_chip_index = chip; + + /* Enter Real-Time ISP mode */ + jtag_rt_enable(); + + /* JTAG internal ID reading */ + jtag_verify_idcode(); + + /* JTAG internal data reading */ + jtag_read_buffer(buffer, size); + + jtag_rt_disable(); + +} + +/* + * cpld_eeprom_size + * function:CPLD chip capacity size + * return value :Returns chip capacity on success, or 0 on failure + */ +static int cpld_eeprom_size(void) +{ + int ret; + + if (!chip_num || chip_cpld_info == NULL) { + FIRMWARE_DRIVER_DEBUG_ERROR("chip_num:%d or chip_cpld_info == NULL.\n", chip_num); + ret = 0; + } else { + ret = chip_cpld_info->eeprom_array_length; + FIRMWARE_DRIVER_DEBUG_ERROR("chip_cpld_info->eeprom_array_length = %d.\n", + chip_cpld_info->eeprom_array_length); + } + + return ret; +} + +/* + * cpld_read_name + * function: Gets the CPLD chip name + * @chip: param[in] Chip serial number/chip index + * return value :chip name */ +static char *cpld_read_name(int chip) +{ + uint chip_type_id; + int i; + + chip_type_id = 0; + cpld_read_id(chip, &chip_type_id); + for (i = 0; cpld_id_table[i].name != NULL; i++) { + if (cpld_id_table[i].id == chip_type_id) { + return cpld_id_table[i].name; + } + } + + return NULL; +} + +/* + * cpld_upgrade_init + * function:Initialize GPIO and CPLD + * return value: success--FIRMWARE_SUCCESS; fail--FIRMWARE_FAILED + */ +static int cpld_upgrade_init(void) +{ + int ret; + + if (function_fmw_cpld.init_cpld != NULL) { + ret = function_fmw_cpld.init_cpld(); + if (ret != FIRMWARE_SUCCESS) { + return ret; + } + } + + return FIRMWARE_SUCCESS; +} + +/* + * cpld_upgrade_finish + * function:Release GPIO and CPLD + * return value: success--FIRMWARE_SUCCESS; fail--FIRMWARE_FAILED + */ +static int cpld_upgrade_finish(void) +{ + int ret; + + if (function_fmw_cpld.finish_cpld != NULL) { + ret = function_fmw_cpld.finish_cpld(); + if (ret != FIRMWARE_SUCCESS) { + return ret; + } + } + + return FIRMWARE_SUCCESS; +} + +static int cpld_str_hex_to_dec(char *str, char end_char) +{ + int i; + int result; + + if (str == NULL) { + return FIRMWARE_FAILED; + } + + i = 0; + result = 0; + while (str[i] != end_char) { + /* Check for hexadecimal characters:0123456789abcdef */ + if (!isxdigit(str[i]) || i >= CPLD_UNIT_SZ) { + return FIRMWARE_FAILED; + } + /* Check for a number between 0 and 9 */ + if (isdigit(str[i])) { + result = result * CPLD_HEX + str[i] - '0'; + } + /* Check if the character is uppercase */ + else if (isupper(str[i])) { + result = result * CPLD_HEX + str[i] - 'A' + DEC_VAL; + } else { + result = result * CPLD_HEX + str[i] - 'a' + DEC_VAL; + } + + i++; + } + + return result; +} + +static int cpld_check_upgrade_data(char *src, int src_len, int *dst, int dst_len) +{ + int i, init_lcnt, tmp; + char *ptr; + int ret; + + if (src == NULL || dst == NULL) { + return FIRMWARE_FAILED; + } + /* Pointers the ptr pointer to the data following the CPLD_INIT_KEYWORD */ + ret = FIRMWARE_SUCCESS; + ptr = strstr(src, CPLD_INIT_KEYWORD); + if (ptr == NULL) { + return FIRMWARE_FAILED; + } else { + ptr += strlen(CPLD_INIT_KEYWORD); + while (*ptr == '(' || *ptr == '\r' || *ptr == '\n') { + ptr++; + } + } + + /* Converts a hexadecimal string to decimal, with 4 groups of 4 bytes each */ + i = 0; + init_lcnt = 0; + for (init_lcnt = 0; init_lcnt < CPLD_INIT_CNT; init_lcnt++) { + tmp = cpld_str_hex_to_dec(ptr, CPLD_END_CHAR); + if (tmp < 0) { + ret = tmp; + return ret; + } + /* int type is 4 bytes */ + dst[i++] = tmp; + if (i >= dst_len) { + return FIRMWARE_SUCCESS; + } + + ptr += CPLD_UNIT_SZ + 1; + + while (*ptr == '\r' || *ptr == '\n') { + ptr++; + } + } + + /* Point the ptr pointer to the data after CPLD_REPEAT_KEYWORD */ + ptr = strstr(src, CPLD_REPEAT_KEYWORD); + if (ptr == NULL) { + return FIRMWARE_FAILED; + } else { + ptr += strlen(CPLD_REPEAT_KEYWORD); + while (*ptr == '(' || *ptr == '\r' || *ptr == '\n') { + ptr++; + } + } + + while (1) { + /* Converts the 4 bytes before ',' to base 10 */ + tmp = cpld_str_hex_to_dec(ptr, CPLD_END_CHAR); + if (tmp < 0) { + ret = tmp; + break; + } + dst[i++] = tmp; + if (i >= dst_len) { + return FIRMWARE_SUCCESS; + } + + ptr += CPLD_UNIT_SZ + 1; + + while (*ptr == '\r' || *ptr == '\n') { + ptr++; + } + } + + return FIRMWARE_SUCCESS; +} + +/** + * fmw_cpld_upg_get_chip_name + * function:get chip name + * @chain: param[in] chain + * @cpld: param[in] Device private data + * @len: param[in] chip name length + * @info: param[out] chip name + * return value: success--FIRMWARE_SUCCESS; fail--FIRMWARE_FAILED + */ +int fmw_cpld_upg_get_chip_name(int chain, firmware_cpld_t *cpld, char *info, int len) +{ + int ret; + char *name; + + /* Check the input and output parameters */ + if (chain < 0 || info == NULL || len <= 0) { + return FIRMWARE_FAILED; + } + + FIRMWARE_DRIVER_DEBUG_VERBOSE("Cpld driver to get chip name.\n"); + + if (cpld == NULL) { + FIRMWARE_DRIVER_DEBUG_ERROR("Failed to get gpio info.(chain = %d)\n", chain); + } else { + set_currrent_cpld_info(cpld); + } + + if (chain != current_fmw_cpld->chain) { + FIRMWARE_DRIVER_DEBUG_ERROR("The chain num is not fit." + "(chain = %d, current chain = %d, current name: %s)\n", + chain, current_fmw_cpld->chain, current_fmw_cpld->devname); + } + + /* Initialize GPIO and CPLD */ + ret = cpld_upgrade_init( ); + if (ret != FIRMWARE_SUCCESS) { + FIRMWARE_DRIVER_DEBUG_ERROR("Error:Failed to get chip name when init upgrade.(chain = %d)\n", + chain); + return FIRMWARE_FAILED; + } + + /* reset JTAG */ + cpld_reset(current_fmw_cpld->chip_index); + /* Read chip name */ + name = cpld_read_name(current_fmw_cpld->chip_index); + if (name == NULL) { + FIRMWARE_DRIVER_DEBUG_ERROR("Error: Failed to get chip name when read name.(chain %d, index %d)\n", + chain, current_fmw_cpld->chip_index); + cpld_upgrade_finish( ); + return FIRMWARE_FAILED; + } + + /* Release GPIO */ + ret = cpld_upgrade_finish( ); + if (ret != FIRMWARE_SUCCESS) { + FIRMWARE_DRIVER_DEBUG_ERROR("Error: Failed to get chip name when finish upgrade.(chain = %d)\n", + chain); + return FIRMWARE_FAILED; + } + + strncpy(info, name, len); + + return FIRMWARE_SUCCESS; +} + +/** + * fmw_cpld_upg_program + * function:Upgrade CPLD(ISC file format) + * @chain: param[in] chain + * @cpld: param[in] Device private data + * @info: param[in] Data to be written + * @len: param[in] Length of data to be written + * return value: success--FIRMWARE_SUCCESS; fail--FIRMWARE_FAILED + */ +int fmw_cpld_upg_program(int chain, firmware_cpld_t *cpld, char *info, int len) +{ + int i; + int time; + int ret; + int target_len; + int *target_buf; + + /* Check the input parameters */ + if (chain < 0 || info == NULL || len <= 0) { + return FIRMWARE_FAILED; + } + + FIRMWARE_DRIVER_DEBUG_VERBOSE("Cpld driver to program chip.\n"); + + if (cpld == NULL) { + FIRMWARE_DRIVER_DEBUG_ERROR("Failed to get gpio info.(chain = %d)\n", chain); + } else { + set_currrent_cpld_info(cpld); + } + + if (chain != current_fmw_cpld->chain) { + FIRMWARE_DRIVER_DEBUG_ERROR("The chain num is not fit.(chain = %d, current chain = %d)\n", + chain, current_fmw_cpld->chain); + } + /* Initialize GPIO and CPLD */ + ret = cpld_upgrade_init( ); + if (ret != FIRMWARE_SUCCESS) { + FIRMWARE_DRIVER_DEBUG_ERROR("Error: Failed to program when init upgrade.(chain = %d)\n", + chain); + return FIRMWARE_FAILED; + } + + /* reset JTAG */ + cpld_reset(current_fmw_cpld->chip_index); + /* CPLD chip capacity size */ + target_len = cpld_eeprom_size(); + if (target_len <= 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("Error: Failed to get cpld size.(chain = %d)\n", + chain); + cpld_upgrade_finish( ); + return FIRMWARE_FAILED; + } + + target_buf = (int *) kzalloc(target_len * sizeof(int), GFP_KERNEL); + if (target_buf == NULL) { + FIRMWARE_DRIVER_DEBUG_ERROR("Error: Failed to malloc target buffer.(chain = %d)\n", + chain); + cpld_upgrade_finish( ); + return FIRMWARE_FAILED; + } + + FIRMWARE_DRIVER_DEBUG_VERBOSE("cpld_check_upgrade_data start.(chain = %d, %d)\n", + chain, target_len); + /* Remove extraneous information */ + ret = cpld_check_upgrade_data(info, len, target_buf, target_len); + if (ret < 0){ + FIRMWARE_DRIVER_DEBUG_ERROR("Error: Failed to check data.(chain = %d)\n", + chain); + kfree(target_buf); + cpld_upgrade_finish( ); + return FIRMWARE_FAILED; + } + + for (i = 0; i < 16 * 8; i += 8) { + FIRMWARE_DRIVER_DEBUG_VERBOSE(" %x %x %x %x %x %x %x %x\n", + target_buf[i], target_buf[i + 1], + target_buf[i + 2], target_buf[i + 3], + target_buf[i + 4], target_buf[i + 5], + target_buf[i + 6], target_buf[i + 7]); + } + + FIRMWARE_DRIVER_DEBUG_VERBOSE("cpld_check_upgrade_data finish.(chain = %d)\n", chain); + + /* CPLD device writing */ + for (time = 0; time < 10; time++) { + FIRMWARE_DRIVER_DEBUG_VERBOSE("Start upgrade cpld: %d.(chain = %d)\n", time, chain); + ret = cpld_program(current_fmw_cpld->chip_index, target_buf); + if (ret >= 0) { + break; + } + } + if (ret < 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("Error: Failed to program.(chain = %d)\n", chain); + kfree(target_buf); + cpld_upgrade_finish( ); + return FIRMWARE_FAILED; + } + + FIRMWARE_DRIVER_DEBUG_VERBOSE("SUCCESS PROGRAM.\n"); + + /* Release GPIO */ + ret = cpld_upgrade_finish(); + if (ret != FIRMWARE_SUCCESS) { + FIRMWARE_DRIVER_DEBUG_ERROR("Failed to program when finish upgrade.(chain = %d)\n", + chain); + } + + kfree(target_buf); + return FIRMWARE_SUCCESS; +} + +/** + * fmw_cpld_upg_program_jbi + * function: Upgrade CPLD(JBI file format) + * @chain: param[in] chain + * @cpld: param[in] Device private data + * @info: param[in] Data to be written + * @len: param[in] Length of data to be written + * return value : success--FIRMWARE_SUCCESS; fail--FIRMWARE_FAILED + */ +int fmw_cpld_upg_program_jbi(int chain, firmware_cpld_t *cpld, char *info, int len) +{ + int time, ret; + int argc = 3; + char *argv[] = { + "-r", + "-aprogram", + "-ddo_real_time_isp=1" + }; + + /* Check the input parameters */ + if (chain < 0 || info == NULL || len <= 0) { + return FIRMWARE_FAILED; + } + + FIRMWARE_DRIVER_DEBUG_VERBOSE("Cpld driver to program chip %d(%p,%p,%d).\n", + chain, cpld, info, len); + + if (cpld == NULL) { + FIRMWARE_DRIVER_DEBUG_ERROR("Failed to get gpio info.(chain = %d)\n", chain); + } else { + set_currrent_cpld_info(cpld); + } + + if (chain != current_fmw_cpld->chain) { + FIRMWARE_DRIVER_DEBUG_ERROR("The chain num is not fit.(chain = %d, current chain = %d)\n", + chain, current_fmw_cpld->chain); + } + /* Initialize GPIO and CPLD */ + ret = cpld_upgrade_init( ); + if (ret != FIRMWARE_SUCCESS) { + FIRMWARE_DRIVER_DEBUG_ERROR("Error: Failed to program when init upgrade.(chain = %d)\n", + chain); + return FIRMWARE_FAILED; + } + + /* reset JTAG */ + cpld_reset(current_fmw_cpld->chip_index); + + for (time = 0; time < 30; time++) { + FIRMWARE_DRIVER_DEBUG_VERBOSE("Start upgrade cpld: %d.(chain = %d)\n", time, chain); + ret = jbi_main((unsigned char *) info, (unsigned long) len, argc, argv); + if (ret == 0) { + break; + } + } + if (ret < 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("Error: Failed to program.(chain = %d)\n", chain); + cpld_upgrade_finish( ); + return FIRMWARE_FAILED; + } + FIRMWARE_DRIVER_DEBUG_VERBOSE("SUCCESS PROGRAM.\n"); + + /* Release GPIO and CPLD */ + ret = cpld_upgrade_finish( ); + if (ret != FIRMWARE_SUCCESS) { + FIRMWARE_DRIVER_DEBUG_ERROR("Failed to program when finish upgrade.(chain = %d)\n", + chain); + } + + return FIRMWARE_SUCCESS; +} + +/** + * fmw_cpld_upg_get_version + * function: get version + * @chain: param[in] chain + * @cpld: param[in] Device private data + * @len: param[in] Data length + * @info: param[out] Version information buffer + * return value : success--FIRMWARE_SUCCESS; fail--FIRMWARE_FAILED + */ +int fmw_cpld_upg_get_version(int chain, firmware_cpld_t *cpld, char *info, int len) +{ + int ret; + + FIRMWARE_DRIVER_DEBUG_VERBOSE("Cpld driver to get version.\n"); + if (cpld == NULL) { + FIRMWARE_DRIVER_DEBUG_ERROR("Failed to get gpio info.(chain = %d)\n", chain); + } else { + set_currrent_cpld_info(cpld); + } + + if (chain != current_fmw_cpld->chain) { + FIRMWARE_DRIVER_DEBUG_ERROR("The chain num is not fit.(chain = %d, current chain = %d)\n", + chain, current_fmw_cpld->chain); + } + + /* CPLD device can't get version */ + if (function_fmw_cpld.get_version != NULL) { + ret = function_fmw_cpld.get_version(chain, info, len); + if (ret < 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("Error: Failed get version in chain: %d.\n", chain); + return FIRMWARE_FAILED; + } + + return FIRMWARE_SUCCESS; + } else { + FIRMWARE_DRIVER_DEBUG_ERROR("The get_version is NULL in chain: %d.\n", chain); + } + + return FIRMWARE_FAILED; +} + +/** + * fmw_cpld_upg_get_chip_info + * function: Get chip content + * @chain: param[in] chain + * @cpld: param[in] Device private data + * @len: param[in] Data length + * @info: param[out] Read Data Buffer + * return value : success--FIRMWARE_SUCCESS; fail--FIRMWARE_FAILED + */ +int fmw_cpld_upg_get_chip_info(int chain, firmware_cpld_t *cpld, void *info, int len) +{ + int i; + int ret; + int target_len; + int *target_buf; + + /* Check input and output parameters */ + if (chain < 0 || info == NULL || len <= 0) { + return FIRMWARE_FAILED; + } + + FIRMWARE_DRIVER_DEBUG_VERBOSE("Cpld driver to read chip.\n"); + + if (cpld == NULL) { + FIRMWARE_DRIVER_DEBUG_ERROR("Failed to get gpio info.(chain = %d)\n", chain); + } else { + set_currrent_cpld_info(cpld); + } + + FIRMWARE_DRIVER_DEBUG_VERBOSE("Cpld driver to read chip: %s.\n",current_fmw_cpld->devname); + if (chain != current_fmw_cpld->chain) { + FIRMWARE_DRIVER_DEBUG_ERROR("The chain num is not fit.(chain = %d, current chain = %d)\n", + chain, current_fmw_cpld->chain); + } + + /* Initialize GPIO and CPLD */ + ret = cpld_upgrade_init( ); + if (ret != FIRMWARE_SUCCESS) { + FIRMWARE_DRIVER_DEBUG_ERROR("Error: Failed to program when init upgrade.(chain = %d)\n", + chain); + return FIRMWARE_FAILED; + } + + /* reset JTAG*/ + cpld_reset(current_fmw_cpld->chip_index); + /* CPLD chip capacity size */ + target_len = cpld_eeprom_size(); + if (target_len <= 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("Error: Failed to get cpld size.(chain = %d)\n", + chain); + cpld_upgrade_finish( ); + return FIRMWARE_FAILED; + } + + target_buf = (int *) kzalloc(target_len * sizeof(int), GFP_KERNEL); + if (target_buf == NULL) { + FIRMWARE_DRIVER_DEBUG_ERROR("Error: Failed to malloc target buffer.(chain = %d)\n", + chain); + cpld_upgrade_finish( ); + return FIRMWARE_FAILED; + } + /* Read chip */ + cpld_read_buffer(current_fmw_cpld->chip_index, target_buf, target_len); + + for (i = 0; i < 16 * 8; i += 8) { + FIRMWARE_DRIVER_DEBUG_VERBOSE(" %x %x %x %x %x %x %x %x\n", + target_buf[i], target_buf[i + 1], + target_buf[i + 2], target_buf[i + 3], + target_buf[i + 4], target_buf[i + 5], + target_buf[i + 6], target_buf[i + 7]); + } + + FIRMWARE_DRIVER_DEBUG_VERBOSE("Success Read.\n"); + + /* Release GPIO and CPLD */ + ret = cpld_upgrade_finish( ); + if (ret != FIRMWARE_SUCCESS) { + FIRMWARE_DRIVER_DEBUG_ERROR("Failed to program when finish upgrade.(chain = %d)\n", + chain); + } + + if (copy_to_user(info, target_buf, (len > target_len) ? target_len : len)) { + kfree(target_buf); + return FIRMWARE_FAILED; + } + + kfree(target_buf); + return FIRMWARE_SUCCESS; +} + +/** + * jbi_jtag_io_ + * function: JBI GPIO operation + * @tms: param[in] TMS signal level + * @tdi: param[in] TDI signal level + * @read_tdo: param[in] Whether to read the level of the TDO + * return value : tdo + */ +int __attribute__ ((weak)) jbi_jtag_io_(int tms, int tdi, int read_tdo) +{ + int tdo = 0; + + if (tms) { + TMS_PULL_UP(); + } else { + TMS_PULL_DOWN(); + } + + if (tdi) { + TDI_PULL_UP(); + } else { + TDI_PULL_DOWN(); + } + + TCK_PULL_UP(); + ndelay(TCK_DELAY); + + if (read_tdo) { + tdo = TDO_READ(); + } + + TCK_PULL_DOWN(); + ndelay(TCK_DELAY); + + return tdo; +} diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/include/firmware.h b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/include/firmware.h new file mode 100644 index 000000000000..3a6ab117df5d --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/include/firmware.h @@ -0,0 +1,82 @@ +#ifndef __FIRMWARE_H__ +#define __FIRMWARE_H__ + +#include +#include + +#include + +/* Debug switch level */ +typedef enum { + FIRWMARE_VERBOSE, + FIRWMARE_WARN, + FIRWMARE_ERROR, + FIRWMARE_END, +} firmware_debug_level_t; + +#define FIRMWARE_DRIVER_DEBUG_VERBOSE(fmt, args...) do { \ + if ((g_firmware_driver_debug) & (1U << FIRWMARE_VERBOSE)) { \ + printk(KERN_INFO "[FIRMWARW_DRIVER_CPLD][VER][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +#define FIRMWARE_DRIVER_DEBUG_ERROR(fmt, args...) do { \ + if ((g_firmware_driver_debug) & (1U << FIRWMARE_ERROR)) { \ + printk(KERN_ERR "[FIRMWARW_DRIVER_CPLD][ERR][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +#define FIRMWARE_NAME_LEN 48 + +#define FIRMWARE_FAILED (-1) +#define FIRMWARE_SUCCESS 0 + +/* ioctl publi command, the same as "firmware_upgrade\include\firmware_app.h" */ +#define FIRMWARE_COMMON_TYPE 'C' +#define FIRMWARE_GET_CHIPNAME _IOR(FIRMWARE_COMMON_TYPE, 0, char) /* get the chip name */ +#define FIRMWARE_GET_VERSION _IOR(FIRMWARE_COMMON_TYPE, 2, int) /* get version */ + +/* firmware cpld driver ioctl command, the same as "firmware_upgrade\include\firmware_app.h" */ +#define FIRMWARE_TYPE 'J' +#define FIRMWARE_PROGRAM _IOW(FIRMWARE_TYPE, 1, char) /* firmware upgrade ISC */ +#define FIRMWARE_READ_CHIP _IOR(FIRMWARE_TYPE, 5, int) /* read the contents of the chip */ +#define FIRMWARE_PROGRAM_JBI _IOW(FIRMWARE_TYPE, 6, char) /* firmware upgrade JBI */ + +typedef struct cmd_info_s { + uint32_t size; + void __user *data; +} cmd_info_t; + +typedef struct firmware_device_s { + struct list_head list; /* device list */ + uint32_t chain; /* chain number */ + char name[FIRMWARE_NAME_LEN]; /* name */ + struct miscdevice dev; /* device */ + void *priv; /* private data */ +} firmware_device_t; + +typedef struct firmware_driver_s { + struct list_head list; /* list */ + char name[FIRMWARE_NAME_LEN]; /* name */ + struct platform_driver *drv; /* driver */ + void *priv; /* private data */ +} firmware_driver_t; + +extern int g_firmware_driver_debug; + +/* Get device information based on minor */ +extern firmware_device_t *firmware_get_device_by_minor(int minor); +/* Registere device */ +extern int firmware_device_register(firmware_device_t *fw_dev); +/* Unregister device */ +extern void firmware_device_unregister(firmware_device_t *fw_dev); +/* Registere driver */ +extern int firmware_driver_register(firmware_driver_t *fw_drv); +/* Unregister driver */ +extern void firmware_driver_unregister(firmware_driver_t *fw_drv); +/* CPLD upgrade initialized */ +extern int firmware_cpld_init(void); +/* CPLD unload function */ +extern void firmware_cpld_exit(void); + +#endif /* end of __FIRMWARE_H__ */ diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/include/firmware_cpld.h b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/include/firmware_cpld.h new file mode 100644 index 000000000000..ef69655a4b2e --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/include/firmware_cpld.h @@ -0,0 +1,64 @@ +#ifndef __FIRMWARE_CPLD_H__ +#define __FIRMWARE_CPLD_H__ + +#define FIRMWARE_DEV_NAME_LEN 32 +#define FIRMWARE_MAX_CPLD_NUM 16 +#define FIRMWARE_TYPE_LEN 10 +#define FIRMWARE_EN_INFO_MAX 16 +#define FIRMWARE_EN_INFO_BUF 128 + +typedef struct firmware_gpio_jtag_en_s { + uint32_t en_gpio; /* GPIO enable pin */ + uint32_t en_level; /* GPIO enable level */ + int flag; /* init flag; 1-init 0-not init */ +} firmware_gpio_jtag_en_t; + +typedef struct firmware_cpld_s { + char devname[FIRMWARE_DEV_NAME_LEN]; /* Device name */ + char type[FIRMWARE_TYPE_LEN]; /* interface type */ + uint32_t tdi; /* TDI signal corresponding to GPIO pin information */ + uint32_t tck; /* TCK signal corresponding to GPIO pin information */ + uint32_t tms; /* TMS signal corresponding to GPIO pin information */ + uint32_t tdo; /* TDO signal corresponding to GPIO pin information */ + uint32_t chain; /* chain num */ + uint32_t chip_index; /* chip index */ + uint32_t tck_delay; /* Delay time */ + uint32_t gpio_en_info_num; /* GPIO Enable Number */ + firmware_gpio_jtag_en_t gpio_en_info[FIRMWARE_EN_INFO_MAX]; /* GPIO Enable Information */ +} firmware_cpld_t; + +typedef struct firmware_cpld_function_s{ + int (*pull_tdi_up)(void); /* TDI pull-up */ + int (*pull_tdi_down)(void); /* TDI pull-down */ + int (*pull_tck_up)(void); /* TCK pull-up */ + int (*pull_tck_down)(void); /* TCK pull-down */ + int (*pull_tms_up)(void); /* TMS pull-up */ + int (*pull_tms_down)(void); /* TCK pull-down */ + int (*read_tdo)(void); /* Read TDO */ + int (*init_cpld)(void); /* CPLD upgrade initializes the operation */ + int (*init_chip)(int chain); /* chip initializes the operation */ + int (*finish_chip)(int chain); /* chip completes the operation*/ + int (*finish_cpld)(void); /* CPLD upgrade completes the operation */ + int (*get_version)(int chain, char *ver, int len); /* get version */ +}firmware_cpld_function_t; + +/* get chip name */ +extern int fmw_cpld_upg_get_chip_name(int chain, firmware_cpld_t *cpld, char *info, int len); +/* ISC firmware upgrad */ +extern int fmw_cpld_upg_program(int chain, firmware_cpld_t *cpld, char *info, int len); +/* get version */ +extern int fmw_cpld_upg_get_version(int chain, firmware_cpld_t *cpld, char *info, int len); +/* Read the contents of Chip */ +extern int fmw_cpld_upg_get_chip_info(int chain, firmware_cpld_t *cpld, void *info, int len); +/* operate TDI */ +extern int fwm_cpld_tdi_op(int value); +/* operate TCK */ +extern int fwm_cpld_tck_op(int value); +/* operate TMS */ +extern int fwm_cpld_tms_op(int value); +/* operate TDO */ +extern int fwm_cpld_tdo_op(void); +/* JBI firmware upgrad */ +extern int fmw_cpld_upg_program_jbi(int chain, firmware_cpld_t *cpld, char *info, int len); + +#endif /* __FIRMWARE_CPLD_H__ */ diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/include/jbi.h b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/include/jbi.h new file mode 100644 index 000000000000..865c8d352174 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/include/jbi.h @@ -0,0 +1,15 @@ +#ifndef __JBI_H__ +#define __JBI_H__ + +#include + +/* JTAG operation interface*/ +extern int jbi_jtag_io_(int tms, int tdi, int read_tdo); +/* delay function */ +extern void jbi_jtag_udelay(unsigned long us); +/* Debug switch */ +extern int jbi_debug(int level); +/* JBI upgrade function */ +extern int jbi_main(unsigned char *addr, unsigned long size, int argc, char * const argv[]); + +#endif /* __JBI_JTAG_H__ */ diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/jbicomp.c b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/jbicomp.c new file mode 100644 index 000000000000..064d0ae50ec4 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/jbicomp.c @@ -0,0 +1,438 @@ +/****************************************************************************/ +/* */ +/* Module: jbicomp.c */ +/* */ +/* Copyright (C) Altera Corporation 1997-2001 */ +/* */ +/* Description: Contains the code for compressing and uncompressing */ +/* Boolean array data. */ +/* */ +/* This algorithm works by searching previous bytes in the */ +/* data that match the current data. If a match is found, */ +/* then the offset and length of the matching data can */ +/* replace the actual data in the output. */ +/* */ +/* Revisions: 2.2 fixed /W4 warnings */ +/* */ +/****************************************************************************/ + +#include "jbiport.h" +#include "jbiexprt.h" +#include "jbicomp.h" +#include "jbistub.h" + +#define SHORT_BITS 16 +#define CHAR_BITS 8 +#define DATA_BLOB_LENGTH 3 +#define MATCH_DATA_LENGTH 8192 +#define JBI_ACA_REQUEST_SIZE 1024 +#define JBI_ACA_BUFFER_SIZE (MATCH_DATA_LENGTH + JBI_ACA_REQUEST_SIZE) + +unsigned long jbi_in_length = 0L; +unsigned long jbi_in_index = 0L; /* byte index into compressed array */ +unsigned int jbi_bits_avail = CHAR_BITS; + +#if PORT == DOS +int jbi_current_variable_id = -1; +int jbi_current_page = -1; +int jbi_version = 0; +unsigned long jbi_out_length = 0L; +unsigned int jbi_out_index = 0; /* byte index into jbi_aca_out_buffer[] */ +unsigned long jbi_aca_in_offset = 0L; +unsigned char jbi_aca_out_buffer[JBI_ACA_BUFFER_SIZE]; +#endif + +/****************************************************************************/ +/* */ +/* The following functions implement incremental decompression of Boolean */ +/* array data, using a small memory window. */ +/* */ +/* This algorithm works by searching previous bytes in the data that match */ +/* the current data. If a match is found, then the offset and length of */ +/* the matching data can replace the actual data in the output. */ +/* */ +/* Memory usage is reduced by maintaining a "window" buffer which contains */ +/* the uncompressed data for one 8K page, plus some extra amount specified */ +/* by JBI_ACA_REQUEST_SIZE. The function jbi_uncompress_page() is used to */ +/* request a subrange of the uncompressed data, starting at a particular */ +/* bit position and extending a maximum of JBI_ACA_REQUEST_SIZE bytes. */ +/* */ +/****************************************************************************/ + +/****************************************************************************/ +/* */ + +unsigned int jbi_bits_required(unsigned int n) + +/* */ +/* Description: Calculate the minimum number of bits required to */ +/* represent n. */ +/* */ +/* Returns: Number of bits. */ +/* */ +/****************************************************************************/ +{ + unsigned int result = SHORT_BITS; + + if (n == 0) + { + result = 1; + } + else + { + /* Look for the highest non-zero bit position */ + while ((n & (1 << (SHORT_BITS - 1))) == 0) + { + n <<= 1; + --result; + } + } + + return (result); +} + +/****************************************************************************/ +/* */ + +unsigned int jbi_read_packed +( +#if PORT!=DOS + unsigned char *buffer, +#endif + unsigned int bits +) + +/* */ +/* Description: Read the next value from the input array "buffer". */ +/* Read only "bits" bits from the array. The amount of */ +/* bits that have already been read from "buffer" is */ +/* stored internally to this function. */ +/* */ +/* Returns: Up to 16 bit value. -1 if buffer overrun. */ +/* */ +/****************************************************************************/ +{ + unsigned int result = 0; + unsigned int shift = 0; + unsigned int databyte = 0; + + while (bits > 0) + { +#if PORT==DOS + databyte = GET_BYTE(jbi_aca_in_offset + jbi_in_index); +#else + databyte = buffer[jbi_in_index]; +#endif + result |= (((databyte >> (CHAR_BITS - jbi_bits_avail)) + & (0xFF >> (CHAR_BITS - jbi_bits_avail))) << shift); + + if (bits <= jbi_bits_avail) + { + result &= (0xFFFF >> (SHORT_BITS - (bits + shift))); + jbi_bits_avail -= bits; + bits = 0; + } + else + { + ++jbi_in_index; + shift += jbi_bits_avail; + bits -= jbi_bits_avail; + jbi_bits_avail = CHAR_BITS; + } + } + + return (result); +} + +#if PORT==DOS + +/****************************************************************************/ +/* */ + +void jbi_uncompress_next_page(int version) + +/* */ +/* Description: Uncompresses one page of compressed data, using */ +/* data page as reference for repeated sections. */ +/* Overwrites previous page of data in buffer. */ +/* */ +/* Returns: TRUE for success, FALSE if error encountered */ +/* */ +/****************************************************************************/ +{ + unsigned int i, j, offset, length; + unsigned int end_index; + unsigned long tmp_in_index = jbi_in_index; + unsigned int tmp_out_index = jbi_out_index; + unsigned int tmp_bits_avail = jbi_bits_avail; + unsigned int prev[3]; + unsigned long long_end; + unsigned int match_data_length = MATCH_DATA_LENGTH; + + if (version > 0) --match_data_length; + + if (jbi_current_page < 0) + { + /* this is the first page of the array */ + jbi_current_page = 0; + jbi_in_index = 4; /* skip over length field */ + jbi_out_index = 0; + end_index = (jbi_out_length < JBI_ACA_BUFFER_SIZE) ? + (unsigned int) jbi_out_length : JBI_ACA_BUFFER_SIZE; + } + else + { + /* this is not the first page */ + ++jbi_current_page; + jbi_out_index -= MATCH_DATA_LENGTH; + long_end = jbi_out_length - + ((long) jbi_current_page * (long) MATCH_DATA_LENGTH); + end_index = (long_end < JBI_ACA_BUFFER_SIZE) ? + (unsigned int) long_end : JBI_ACA_BUFFER_SIZE; + + /* copy extra data from end of circular buffer to beginning */ + for (i = 0; i < jbi_out_index; ++i) + { + jbi_aca_out_buffer[i] = jbi_aca_out_buffer[i + MATCH_DATA_LENGTH]; + } + } + + while (jbi_out_index < end_index) + { + /* save state so we can undo the last packet when we reach the end */ + tmp_in_index = jbi_in_index; + tmp_out_index = jbi_out_index; + tmp_bits_avail = jbi_bits_avail; + + /* A 0 bit indicates literal data. */ + if (jbi_read_packed(1) == 0) + { + for (i = 0; i < DATA_BLOB_LENGTH; ++i) + { + if (jbi_out_index < end_index) + { + if (version == 0) + { + prev[i] = jbi_aca_out_buffer[jbi_out_index] & 0xff; + } + jbi_aca_out_buffer[jbi_out_index++] = + (unsigned char) jbi_read_packed(CHAR_BITS); + } + } + } + else + { + /* A 1 bit indicates offset/length to follow. */ + offset = jbi_read_packed(jbi_bits_required( + (jbi_current_page > 0) ? match_data_length : + (jbi_out_index > match_data_length ? match_data_length : + jbi_out_index))); + length = jbi_read_packed(CHAR_BITS); + + if ((version == 0) && (offset == match_data_length + 3)) + { + jbi_aca_out_buffer[jbi_out_index++] = (unsigned char) prev[0]; + jbi_aca_out_buffer[jbi_out_index++] = (unsigned char) prev[1]; + jbi_aca_out_buffer[jbi_out_index++] = (unsigned char) prev[2]; + length -= 3; + } + + for (i = 0; i < length; ++i) + { + if (jbi_out_index < end_index) + { + if (offset > jbi_out_index) + { + j = jbi_out_index + MATCH_DATA_LENGTH - offset; + } + else j = jbi_out_index - offset; + jbi_aca_out_buffer[jbi_out_index] = jbi_aca_out_buffer[j]; + ++jbi_out_index; + } + } + + if (version == 0) + { + prev[0] = jbi_aca_out_buffer[jbi_out_index - 3] & 0xff; + prev[1] = jbi_aca_out_buffer[jbi_out_index - 2] & 0xff; + prev[2] = jbi_aca_out_buffer[jbi_out_index - 1] & 0xff; + } + } + } + + /* restore the state before the previous packet */ + jbi_in_index = tmp_in_index; + jbi_out_index = tmp_out_index; + jbi_bits_avail = tmp_bits_avail; +} + +/****************************************************************************/ +/* */ + +void jbi_uncompress_page +( + int variable_id, + int page, + int version +) + +/* */ +/* Description: Uncompress requested page of variable data. Stores */ +/* uncompressed data in jbi_aca_out_buffer[]. */ +/* */ +/* Returns: TRUE if successful, otherwise FALSE if: */ +/* 1) variable is not a compressed array */ +/* 2) compressed data is illegal or corrupted */ +/* 3) requested page is beyond the end of the array */ +/* 4) internal error in the code */ +/* */ +/****************************************************************************/ +{ + unsigned long symbol_table; + unsigned long data_section; + unsigned long offset; + unsigned long value; + int delta = version * 2; + + if (variable_id != jbi_current_variable_id) + { + /* initialize to uncompress the desired variable */ + symbol_table = GET_DWORD(16 + (version * 8)); + data_section = GET_DWORD(20 + (version * 8)); + offset = symbol_table + ((11 + delta) * variable_id); + value = GET_DWORD(offset + 3 + delta); + jbi_current_variable_id = variable_id; + jbi_current_page = -1; + jbi_bits_avail = CHAR_BITS; + jbi_in_length = GET_DWORD(offset + 7 + delta); + jbi_out_length = + (((unsigned long) GET_BYTE(data_section + value)) | + (((unsigned long) GET_BYTE(data_section + value + 1)) << 8) | + (((unsigned long) GET_BYTE(data_section + value + 2)) << 16) | + (((unsigned long) GET_BYTE(data_section + value + 3)) << 24)); + jbi_in_index = 4; /* skip over length field */ + jbi_out_index = 0; + jbi_aca_in_offset = data_section + value; + } + + /* to look back at an earlier page, start over at the beginning */ + if (page < jbi_current_page) + { + jbi_current_page = -1; + jbi_in_index = 4; /* skip over length field */ + jbi_bits_avail = CHAR_BITS; + } + + /* uncompress sequentially up to the desired page */ + while (page > jbi_current_page) + { + jbi_uncompress_next_page(version); + } +} + +#else + +/****************************************************************************/ +/* */ + +unsigned long jbi_uncompress +( + unsigned char *in, + unsigned long in_length, + unsigned char *out, + unsigned long out_length, + int version +) + +/* */ +/* Description: Uncompress data in "in" and write result to "out". */ +/* */ +/* Returns: Length of uncompressed data. -1 if: */ +/* 1) out_length is too small */ +/* 2) Internal error in the code */ +/* 3) in doesn't contain ACA compressed data. */ +/* */ +/****************************************************************************/ +{ +#ifdef CONFIG_64BIT + unsigned int data_length = 0; +#else + unsigned long data_length = 0L; +#endif + unsigned long i, j; + unsigned int offset, length; + unsigned int match_data_length = MATCH_DATA_LENGTH; + + if (version > 0) --match_data_length; + + jbi_in_length = in_length; + jbi_bits_avail = CHAR_BITS; + jbi_in_index = 0L; + for (i = 0; i < out_length; ++i) out[i] = 0; + + /* Read number of bytes in data. */ +#ifdef CONFIG_64BIT + for (i = 0; i < sizeof(unsigned int); ++i) + { + data_length = data_length | ((unsigned int) + jbi_read_packed(in, CHAR_BITS) << (i * CHAR_BITS)); + } +#else + for (i = 0; i < sizeof (in_length); ++i) + { + data_length = data_length | ((unsigned long) + jbi_read_packed(in, CHAR_BITS) << (i * CHAR_BITS)); + } +#endif + + if (data_length > out_length) + { +#ifdef CONFIG_64BIT + jbi_dbg(DEBUG_ERR, "data_length(0x%x,0x%lx)\n", + data_length, out_length); + data_length = 0; +#else + jbi_dbg(DEBUG_ERR, "data_length(0x%lx,0x%lx)\n", + data_length, out_length); + data_length = 0L; +#endif + } + else + { + i = 0; + while (i < data_length) + { + /* A 0 bit indicates literal data. */ + if (jbi_read_packed(in, 1) == 0) + { + for (j = 0; j < DATA_BLOB_LENGTH; ++j) + { + if (i < data_length) + { + out[i] = (unsigned char) jbi_read_packed(in, CHAR_BITS); + i++; + } + } + } + else + { + /* A 1 bit indicates offset/length to follow. */ + offset = jbi_read_packed(in, jbi_bits_required((short) (i > match_data_length ? match_data_length : i))); + length = jbi_read_packed(in, CHAR_BITS); + + for (j = 0; j < length; ++j) + { + if (i < data_length) + { + out[i] = out[i - offset]; + i++; + } + } + } + } + } + + return (data_length); +} + +#endif diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/jbicomp.h b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/jbicomp.h new file mode 100644 index 000000000000..4dacdcd5d773 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/jbicomp.h @@ -0,0 +1,37 @@ +/****************************************************************************/ +/* */ +/* Module: jbicomp.h */ +/* */ +/* Copyright (C) Altera Corporation 1997-2001 */ +/* */ +/* Description: Contains the function prototypes for compressing */ +/* and uncompressing Boolean array data. */ +/* */ +/****************************************************************************/ + +#ifndef INC_JBICOMP_H +#define INC_JBICOMP_H + +#if PORT==DOS + +void jbi_uncompress_page +( + int variable_id, + int page, + int version +); + +#else + +unsigned long jbi_uncompress +( + unsigned char *in, + unsigned long in_length, + unsigned char *out, + unsigned long out_length, + int version +); + +#endif /* PORT==DOS */ + +#endif /* INC_JBICOMP_H */ diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/jbiexprt.h b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/jbiexprt.h new file mode 100644 index 000000000000..ef4699dd6db3 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/jbiexprt.h @@ -0,0 +1,224 @@ +/****************************************************************************/ +/* */ +/* Module: jbiexprt.h */ +/* */ +/* Copyright (C) Altera Corporation 1998-2001 */ +/* */ +/* Description: Jam STAPL ByteCode Player Export Header File */ +/* */ +/* Revisions: */ +/* */ +/****************************************************************************/ + +#ifndef INC_JBIEXPRT_H +#define INC_JBIEXPRT_H + +/****************************************************************************/ +/* */ +/* Return codes from most JBI functions */ +/* */ +/****************************************************************************/ + +#define JBI_RETURN_TYPE int + +#define JBIC_SUCCESS 0 +#define JBIC_OUT_OF_MEMORY 1 +#define JBIC_IO_ERROR 2 +/* #define JAMC_SYNTAX_ERROR 3 */ +#define JBIC_UNEXPECTED_END 4 +#define JBIC_UNDEFINED_SYMBOL 5 +/* #define JAMC_REDEFINED_SYMBOL 6 */ +#define JBIC_INTEGER_OVERFLOW 7 +#define JBIC_DIVIDE_BY_ZERO 8 +#define JBIC_CRC_ERROR 9 +#define JBIC_INTERNAL_ERROR 10 +#define JBIC_BOUNDS_ERROR 11 +/* #define JAMC_TYPE_MISMATCH 12 */ +/* #define JAMC_ASSIGN_TO_CONST 13 */ +/* #define JAMC_NEXT_UNEXPECTED 14 */ +/* #define JAMC_POP_UNEXPECTED 15 */ +/* #define JAMC_RETURN_UNEXPECTED 16 */ +/* #define JAMC_ILLEGAL_SYMBOL 17 */ +#define JBIC_VECTOR_MAP_FAILED 18 +#define JBIC_USER_ABORT 19 +#define JBIC_STACK_OVERFLOW 20 +#define JBIC_ILLEGAL_OPCODE 21 +/* #define JAMC_PHASE_ERROR 22 */ +/* #define JAMC_SCOPE_ERROR 23 */ +#define JBIC_ACTION_NOT_FOUND 24 + +/****************************************************************************/ +/* */ +/* Macro Definitions */ +/* */ +/****************************************************************************/ + +/* +* For DOS port, program data is stored in a set of 16K pages, accessed +* through a pointer table. For 32-bit version, the buffer is continuous. +* The macro GET_BYTE gets a single byte for either case. +*/ +#if PORT==DOS +#define PROGRAM_PTR unsigned char ** +#else +#define PROGRAM_PTR unsigned char * +#endif + +#if PORT==DOS +#define GET_BYTE(x) (jbi_program[(x) >> 14L][(x) & 0x3fffL]) +#else +#define GET_BYTE(x) (program[x]) +#endif + +#define GET_WORD(x) \ + (((((unsigned short) GET_BYTE(x)) << 8) & 0xFF00) | \ + (((unsigned short) GET_BYTE((x)+1)) & 0x00FF)) + +#define GET_DWORD(x) \ + (((((unsigned long) GET_BYTE(x)) << 24L) & 0xFF000000L) | \ + ((((unsigned long) GET_BYTE((x)+1)) << 16L) & 0x00FF0000L) | \ + ((((unsigned long) GET_BYTE((x)+2)) << 8L) & 0x0000FF00L) | \ + (((unsigned long) GET_BYTE((x)+3)) & 0x000000FFL)) + +/****************************************************************************/ +/* */ +/* Structured Types */ +/* */ +/****************************************************************************/ + +typedef struct JBI_PROCINFO_STRUCT +{ + char *name; + unsigned char attributes; + struct JBI_PROCINFO_STRUCT *next; +} +JBI_PROCINFO; + +/****************************************************************************/ +/* */ +/* Global Data Prototypes */ +/* */ +/****************************************************************************/ + +#if PORT==DOS +extern unsigned char jbi_aca_out_buffer[8192 + 1024]; +#endif + +extern PROGRAM_PTR jbi_program; + +extern char *jbi_workspace; + +extern long jbi_workspace_size; + +/****************************************************************************/ +/* */ +/* Function Prototypes */ +/* */ +/****************************************************************************/ + +JBI_RETURN_TYPE jbi_execute +( + PROGRAM_PTR program, + long program_size, + char *workspace, + long workspace_size, + char *action, + char **init_list, + int reset_jtag, + long *error_address, + int *exit_code, + int *format_version +); + +JBI_RETURN_TYPE jbi_get_note +( + PROGRAM_PTR program, + long program_size, + long *offset, + char *key, + char *value, + int length +); + +JBI_RETURN_TYPE jbi_check_crc +( + PROGRAM_PTR program, + long program_size, + unsigned short *expected_crc, + unsigned short *actual_crc +); + +JBI_RETURN_TYPE jbi_get_file_info +( + PROGRAM_PTR program, + long program_size, + int *format_version, + int *action_count, + int *procedure_count +); + +JBI_RETURN_TYPE jbi_get_action_info +( + PROGRAM_PTR program, + long program_size, + int index, + char **name, + char **description, + JBI_PROCINFO **procedure_list +); + +int jbi_jtag_io +( + int tms, + int tdi, + int read_tdo +); + +void jbi_message +( + char *message_text +); + +void jbi_export_integer +( + char *key, + long value +); + +void jbi_export_boolean_array +( + char *key, + unsigned char *data, + long count +); + +void jbi_delay +( + long microseconds +); + +int jbi_vector_map +( + int signal_count, + char **signals +); + +int jbi_vector_io +( + int signal_count, + long *dir_vect, + long *data_vect, + long *capture_vect +); + +void *jbi_malloc +( + unsigned int size +); + +void jbi_free +( + void *ptr +); + +#endif /* INC_JBIEXPRT_H */ diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/jbijtag.c b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/jbijtag.c new file mode 100644 index 000000000000..f013100eecb8 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/jbijtag.c @@ -0,0 +1,1679 @@ +/****************************************************************************/ +/* */ +/* Module: jbijtag.c */ +/* */ +/* Copyright (C) Altera Corporation 1998-2001 */ +/* */ +/* Description: Contains JTAG interface functions */ +/* */ +/* Revisions: 2.2 updated state transition paths */ +/* 2.0 added multi-page scan code for 16-bit PORT */ +/* */ +/****************************************************************************/ + +#include "jbiport.h" +#include "jbiexprt.h" +#include "jbicomp.h" +#include "jbijtag.h" + +#define NULL 0 + +char *jbi_workspace = NULL; +long jbi_workspace_size = 0L; + +/****************************************************************************/ +/* */ +/* Enumerated Types */ +/* */ +/****************************************************************************/ + +/* maximum JTAG IR and DR lengths (in bits) */ +#define JBIC_MAX_JTAG_IR_PREAMBLE 256 +#define JBIC_MAX_JTAG_IR_POSTAMBLE 256 +#define JBIC_MAX_JTAG_IR_LENGTH 512 +#define JBIC_MAX_JTAG_DR_PREAMBLE 1024 +#define JBIC_MAX_JTAG_DR_POSTAMBLE 1024 +#define JBIC_MAX_JTAG_DR_LENGTH 2048 + +/* +* Global variable to store the current JTAG state +*/ +JBIE_JTAG_STATE jbi_jtag_state = JBI_ILLEGAL_JTAG_STATE; + +/* +* Store current stop-state for DR and IR scan commands +*/ +JBIE_JTAG_STATE jbi_drstop_state = IDLE; +JBIE_JTAG_STATE jbi_irstop_state = IDLE; + +/* +* Store current padding values +*/ +unsigned int jbi_dr_preamble = 0; +unsigned int jbi_dr_postamble = 0; +unsigned int jbi_ir_preamble = 0; +unsigned int jbi_ir_postamble = 0; +unsigned int jbi_dr_length = 0; +unsigned int jbi_ir_length = 0; +unsigned char *jbi_dr_preamble_data = NULL; +unsigned char *jbi_dr_postamble_data = NULL; +unsigned char *jbi_ir_preamble_data = NULL; +unsigned char *jbi_ir_postamble_data = NULL; +unsigned char *jbi_dr_buffer = NULL; +unsigned char *jbi_ir_buffer = NULL; + +/* +* This structure shows, for each JTAG state, which state is reached after +* a single TCK clock cycle with TMS high or TMS low, respectively. This +* describes all possible state transitions in the JTAG state machine. +*/ +struct JBIS_JTAG_MACHINE +{ + JBIE_JTAG_STATE tms_high; + JBIE_JTAG_STATE tms_low; +} jbi_jtag_state_transitions[] = +{ +/* RESET */ { RESET, IDLE }, +/* IDLE */ { DRSELECT, IDLE }, +/* DRSELECT */ { IRSELECT, DRCAPTURE }, +/* DRCAPTURE */ { DREXIT1, DRSHIFT }, +/* DRSHIFT */ { DREXIT1, DRSHIFT }, +/* DREXIT1 */ { DRUPDATE, DRPAUSE }, +/* DRPAUSE */ { DREXIT2, DRPAUSE }, +/* DREXIT2 */ { DRUPDATE, DRSHIFT }, +/* DRUPDATE */ { DRSELECT, IDLE }, +/* IRSELECT */ { RESET, IRCAPTURE }, +/* IRCAPTURE */ { IREXIT1, IRSHIFT }, +/* IRSHIFT */ { IREXIT1, IRSHIFT }, +/* IREXIT1 */ { IRUPDATE, IRPAUSE }, +/* IRPAUSE */ { IREXIT2, IRPAUSE }, +/* IREXIT2 */ { IRUPDATE, IRSHIFT }, +/* IRUPDATE */ { DRSELECT, IDLE } +}; + +/* +* This table contains the TMS value to be used to take the NEXT STEP on +* the path to the desired state. The array index is the current state, +* and the bit position is the desired endstate. To find out which state +* is used as the intermediate state, look up the TMS value in the +* jbi_jtag_state_transitions[] table. +*/ +unsigned short jbi_jtag_path_map[16] = +{ +/* RST RTI SDRS CDR SDR E1DR PDR E2DR */ + 0x0001, 0xFFFD, 0xFE01, 0xFFE7, 0xFFEF, 0xFF0F, 0xFFBF, 0xFFFF, +/* UDR SIRS CIR SIR E1IR PIR E2IR UIR */ + 0xFEFD, 0x0001, 0xF3FF, 0xF7FF, 0x87FF, 0xDFFF, 0xFFFF, 0x7FFD +}; + +/* +* Flag bits for jbi_jtag_io() function +*/ +#define TMS_HIGH 1 +#define TMS_LOW 0 +#define TDI_HIGH 1 +#define TDI_LOW 0 +#define READ_TDO 1 +#define IGNORE_TDO 0 + +/****************************************************************************/ +/* */ + +JBI_RETURN_TYPE jbi_init_jtag() + +/* */ +/****************************************************************************/ +{ + /* initial JTAG state is unknown */ + jbi_jtag_state = JBI_ILLEGAL_JTAG_STATE; + + /* initialize global variables to default state */ + jbi_drstop_state = IDLE; + jbi_irstop_state = IDLE; + jbi_dr_preamble = 0; + jbi_dr_postamble = 0; + jbi_ir_preamble = 0; + jbi_ir_postamble = 0; + jbi_dr_length = 0; + jbi_ir_length = 0; + + if (jbi_workspace != NULL) + { + jbi_dr_preamble_data = (unsigned char *) jbi_workspace; + jbi_dr_postamble_data = &jbi_dr_preamble_data[JBIC_MAX_JTAG_DR_PREAMBLE / 8]; + jbi_ir_preamble_data = &jbi_dr_postamble_data[JBIC_MAX_JTAG_DR_POSTAMBLE / 8]; + jbi_ir_postamble_data = &jbi_ir_preamble_data[JBIC_MAX_JTAG_IR_PREAMBLE / 8]; + jbi_dr_buffer = &jbi_ir_postamble_data[JBIC_MAX_JTAG_IR_POSTAMBLE / 8]; + jbi_ir_buffer = &jbi_dr_buffer[JBIC_MAX_JTAG_DR_LENGTH / 8]; + } + else + { + jbi_dr_preamble_data = NULL; + jbi_dr_postamble_data = NULL; + jbi_ir_preamble_data = NULL; + jbi_ir_postamble_data = NULL; + jbi_dr_buffer = NULL; + jbi_ir_buffer = NULL; + } + + return (JBIC_SUCCESS); +} + +/****************************************************************************/ +/* */ + +JBI_RETURN_TYPE jbi_set_drstop_state +( + JBIE_JTAG_STATE state +) + +/* */ +/****************************************************************************/ +{ + jbi_drstop_state = state; + + return (JBIC_SUCCESS); +} + +/****************************************************************************/ +/* */ + +JBI_RETURN_TYPE jbi_set_irstop_state +( + JBIE_JTAG_STATE state +) + +/* */ +/****************************************************************************/ +{ + jbi_irstop_state = state; + + return (JBIC_SUCCESS); +} + +/****************************************************************************/ +/* */ + +JBI_RETURN_TYPE jbi_set_dr_preamble +( + unsigned int count, + unsigned int start_index, + unsigned char *preamble_data +) + +/* */ +/****************************************************************************/ +{ + JBI_RETURN_TYPE status = JBIC_SUCCESS; + unsigned int i; + unsigned int j; + + if (jbi_workspace != NULL) + { + if (count > JBIC_MAX_JTAG_DR_PREAMBLE) + { + status = JBIC_OUT_OF_MEMORY; + } + else + { + jbi_dr_preamble = count; + } + } + else + { + if (count > jbi_dr_preamble) + { + jbi_free(jbi_dr_preamble_data); + jbi_dr_preamble_data = (unsigned char *) jbi_malloc((count + 7) >> 3); + + if (jbi_dr_preamble_data == NULL) + { + status = JBIC_OUT_OF_MEMORY; + } + else + { + jbi_dr_preamble = count; + } + } + else + { + jbi_dr_preamble = count; + } + } + + if (status == JBIC_SUCCESS) + { + for (i = 0; i < count; ++i) + { + j = i + start_index; + + if (preamble_data == NULL) + { + jbi_dr_preamble_data[i >> 3] |= (1 << (i & 7)); + } + else + { + if (preamble_data[j >> 3] & (1 << (j & 7))) + { + jbi_dr_preamble_data[i >> 3] |= (1 << (i & 7)); + } + else + { + jbi_dr_preamble_data[i >> 3] &= + ~(unsigned int) (1 << (i & 7)); + } + } + } + } + + return (status); +} + +/****************************************************************************/ +/* */ + +JBI_RETURN_TYPE jbi_set_ir_preamble +( + unsigned int count, + unsigned int start_index, + unsigned char *preamble_data +) + +/* */ +/****************************************************************************/ +{ + JBI_RETURN_TYPE status = JBIC_SUCCESS; + unsigned int i; + unsigned int j; + + if (jbi_workspace != NULL) + { + if (count > JBIC_MAX_JTAG_IR_PREAMBLE) + { + status = JBIC_OUT_OF_MEMORY; + } + else + { + jbi_ir_preamble = count; + } + } + else + { + if (count > jbi_ir_preamble) + { + jbi_free(jbi_ir_preamble_data); + jbi_ir_preamble_data = (unsigned char *) jbi_malloc((count + 7) >> 3); + + if (jbi_ir_preamble_data == NULL) + { + status = JBIC_OUT_OF_MEMORY; + } + else + { + jbi_ir_preamble = count; + } + } + else + { + jbi_ir_preamble = count; + } + } + + if (status == JBIC_SUCCESS) + { + for (i = 0; i < count; ++i) + { + j = i + start_index; + + if (preamble_data == NULL) + { + jbi_ir_preamble_data[i >> 3] |= (1 << (i & 7)); + } + else + { + if (preamble_data[j >> 3] & (1 << (j & 7))) + { + jbi_ir_preamble_data[i >> 3] |= (1 << (i & 7)); + } + else + { + jbi_ir_preamble_data[i >> 3] &= + ~(unsigned int) (1 << (i & 7)); + } + } + } + } + + return (status); +} + +/****************************************************************************/ +/* */ + +JBI_RETURN_TYPE jbi_set_dr_postamble +( + unsigned int count, + unsigned int start_index, + unsigned char *postamble_data +) + +/* */ +/****************************************************************************/ +{ + JBI_RETURN_TYPE status = JBIC_SUCCESS; + unsigned int i; + unsigned int j; + + if (jbi_workspace != NULL) + { + if (count > JBIC_MAX_JTAG_DR_POSTAMBLE) + { + status = JBIC_OUT_OF_MEMORY; + } + else + { + jbi_dr_postamble = count; + } + } + else + { + if (count > jbi_dr_postamble) + { + jbi_free(jbi_dr_postamble_data); + jbi_dr_postamble_data = (unsigned char *) jbi_malloc((count + 7) >> 3); + + if (jbi_dr_postamble_data == NULL) + { + status = JBIC_OUT_OF_MEMORY; + } + else + { + jbi_dr_postamble = count; + } + } + else + { + jbi_dr_postamble = count; + } + } + + if (status == JBIC_SUCCESS) + { + for (i = 0; i < count; ++i) + { + j = i + start_index; + + if (postamble_data == NULL) + { + jbi_dr_postamble_data[i >> 3] |= (1 << (i & 7)); + } + else + { + if (postamble_data[j >> 3] & (1 << (j & 7))) + { + jbi_dr_postamble_data[i >> 3] |= (1 << (i & 7)); + } + else + { + jbi_dr_postamble_data[i >> 3] &= + ~(unsigned int) (1 << (i & 7)); + } + } + } + } + + return (status); +} + +/****************************************************************************/ +/* */ + +JBI_RETURN_TYPE jbi_set_ir_postamble +( + unsigned int count, + unsigned int start_index, + unsigned char *postamble_data +) + +/* */ +/****************************************************************************/ +{ + JBI_RETURN_TYPE status = JBIC_SUCCESS; + unsigned int i; + unsigned int j; + + if (jbi_workspace != NULL) + { + if (count > JBIC_MAX_JTAG_IR_POSTAMBLE) + { + status = JBIC_OUT_OF_MEMORY; + } + else + { + jbi_ir_postamble = count; + } + } + else + { + if (count > jbi_ir_postamble) + { + jbi_free(jbi_ir_postamble_data); + jbi_ir_postamble_data = (unsigned char *) jbi_malloc((count + 7) >> 3); + + if (jbi_ir_postamble_data == NULL) + { + status = JBIC_OUT_OF_MEMORY; + } + else + { + jbi_ir_postamble = count; + } + } + else + { + jbi_ir_postamble = count; + } + } + + if (status == JBIC_SUCCESS) + { + for (i = 0; i < count; ++i) + { + j = i + start_index; + + if (postamble_data == NULL) + { + jbi_ir_postamble_data[i >> 3] |= (1 << (i & 7)); + } + else + { + if (postamble_data[j >> 3] & (1 << (j & 7))) + { + jbi_ir_postamble_data[i >> 3] |= (1 << (i & 7)); + } + else + { + jbi_ir_postamble_data[i >> 3] &= + ~(unsigned int) (1 << (i & 7)); + } + } + } + } + + return (status); +} + +/****************************************************************************/ +/* */ + +void jbi_jtag_reset_idle(void) + +/* */ +/****************************************************************************/ +{ + int i; + + /* + * Go to Test Logic Reset (no matter what the starting state may be) + */ + for (i = 0; i < 5; ++i) + { + jbi_jtag_io(TMS_HIGH, TDI_LOW, IGNORE_TDO); + } + + /* + * Now step to Run Test / Idle + */ + jbi_jtag_io(TMS_LOW, TDI_LOW, IGNORE_TDO); + + jbi_jtag_state = IDLE; +} + +/****************************************************************************/ +/* */ + +JBI_RETURN_TYPE jbi_goto_jtag_state +( + JBIE_JTAG_STATE state +) + +/* */ +/****************************************************************************/ +{ + int tms; + int count = 0; + JBI_RETURN_TYPE status = JBIC_SUCCESS; + unsigned int tmp_state; + + if (jbi_jtag_state == JBI_ILLEGAL_JTAG_STATE) + { + /* initialize JTAG chain to known state */ + jbi_jtag_reset_idle(); + } + + if (jbi_jtag_state == state) + { + /* + * We are already in the desired state. If it is a stable state, + * loop here. Otherwise do nothing (no clock cycles). + */ + if ((state == IDLE) || + (state == DRSHIFT) || + (state == DRPAUSE) || + (state == IRSHIFT) || + (state == IRPAUSE)) + { + jbi_jtag_io(TMS_LOW, TDI_LOW, IGNORE_TDO); + } + else if (state == RESET) + { + jbi_jtag_io(TMS_HIGH, TDI_LOW, IGNORE_TDO); + } + } + else + { + while ((jbi_jtag_state != state) && (count < 9)) + { + /* + * Get TMS value to take a step toward desired state + */ + if (state < 0) { + tmp_state = 0; + } else { + tmp_state = state; + } + tms = (jbi_jtag_path_map[jbi_jtag_state] & (1 << tmp_state)) ? + TMS_HIGH : TMS_LOW; + + /* + * Take a step + */ + jbi_jtag_io(tms, TDI_LOW, IGNORE_TDO); + + if (tms) + { + jbi_jtag_state = + jbi_jtag_state_transitions[jbi_jtag_state].tms_high; + } + else + { + jbi_jtag_state = + jbi_jtag_state_transitions[jbi_jtag_state].tms_low; + } + + ++count; + } + } + + if (jbi_jtag_state != state) + { + status = JBIC_INTERNAL_ERROR; + } + + return (status); +} + +/****************************************************************************/ +/* */ + +JBI_RETURN_TYPE jbi_do_wait_cycles +( + long cycles, + JBIE_JTAG_STATE wait_state +) + +/* */ +/* Description: Causes JTAG hardware to loop in the specified stable */ +/* state for the specified number of TCK clock cycles. */ +/* */ +/* Returns: JBIC_SUCCESS for success, else appropriate error code */ +/* */ +/****************************************************************************/ +{ + int tms; + long count; + JBI_RETURN_TYPE status = JBIC_SUCCESS; + + if (jbi_jtag_state != wait_state) + { + status = jbi_goto_jtag_state(wait_state); + } + + if (status == JBIC_SUCCESS) + { + /* + * Set TMS high to loop in RESET state + * Set TMS low to loop in any other stable state + */ + tms = (wait_state == RESET) ? TMS_HIGH : TMS_LOW; + + for (count = 0L; count < cycles; count++) + { + jbi_jtag_io(tms, TDI_LOW, IGNORE_TDO); + } + } + + return (status); +} + +/****************************************************************************/ +/* */ + +JBI_RETURN_TYPE jbi_do_wait_microseconds +( + long microseconds, + JBIE_JTAG_STATE wait_state +) + +/* */ +/* Description: Causes JTAG hardware to sit in the specified stable */ +/* state for the specified duration of real time. If */ +/* no JTAG operations have been performed yet, then only */ +/* a delay is performed. This permits the WAIT USECS */ +/* statement to be used in VECTOR programs without causing */ +/* any JTAG operations. */ +/* */ +/* Returns: JBIC_SUCCESS for success, else appropriate error code */ +/* */ +/****************************************************************************/ +{ + JBI_RETURN_TYPE status = JBIC_SUCCESS; + + if ((jbi_jtag_state != JBI_ILLEGAL_JTAG_STATE) && + (jbi_jtag_state != wait_state)) + { + status = jbi_goto_jtag_state(wait_state); + } + + if (status == JBIC_SUCCESS) + { + /* + * Wait for specified time interval + */ + jbi_delay(microseconds); + } + + return (status); +} + +/****************************************************************************/ +/* */ + +void jbi_jtag_concatenate_data +( + unsigned char *buffer, + unsigned char *preamble_data, + unsigned int preamble_count, + unsigned char *target_data, + unsigned long start_index, + unsigned int target_count, + unsigned char *postamble_data, + unsigned int postamble_count +) + +/* */ +/* Description: Copies preamble data, target data, and postamble data */ +/* into one buffer for IR or DR scans. */ +/* */ +/* Returns: nothing */ +/* */ +/****************************************************************************/ +{ + unsigned long i; + unsigned long j; + unsigned long k; + + for (i = 0L; i < preamble_count; ++i) + { + if (preamble_data[i >> 3L] & (1L << (i & 7L))) + { + buffer[i >> 3L] |= (1L << (i & 7L)); + } + else + { + buffer[i >> 3L] &= ~(unsigned int) (1L << (i & 7L)); + } + } + + j = start_index; + k = preamble_count + target_count; + for (; i < k; ++i, ++j) + { + if (target_data[j >> 3L] & (1L << (j & 7L))) + { + buffer[i >> 3L] |= (1L << (i & 7L)); + } + else + { + buffer[i >> 3L] &= ~(unsigned int) (1L << (i & 7L)); + } + } + + j = 0L; + k = preamble_count + target_count + postamble_count; + for (; i < k; ++i, ++j) + { + if (postamble_data[j >> 3L] & (1L << (j & 7L))) + { + buffer[i >> 3L] |= (1L << (i & 7L)); + } + else + { + buffer[i >> 3L] &= ~(unsigned int) (1L << (i & 7L)); + } + } +} + +int jbi_jtag_drscan +( + int start_state, + int count, + unsigned char *tdi, + unsigned char *tdo +) +{ + int i = 0; + int tdo_bit = 0; + int status = 1; + + /* + * First go to DRSHIFT state + */ + switch (start_state) + { + case 0: /* IDLE */ + jbi_jtag_io(1, 0, 0); /* DRSELECT */ + jbi_jtag_io(0, 0, 0); /* DRCAPTURE */ + jbi_jtag_io(0, 0, 0); /* DRSHIFT */ + break; + + case 1: /* DRPAUSE */ + jbi_jtag_io(1, 0, 0); /* DREXIT2 */ + jbi_jtag_io(1, 0, 0); /* DRUPDATE */ + jbi_jtag_io(1, 0, 0); /* DRSELECT */ + jbi_jtag_io(0, 0, 0); /* DRCAPTURE */ + jbi_jtag_io(0, 0, 0); /* DRSHIFT */ + break; + + case 2: /* IRPAUSE */ + jbi_jtag_io(1, 0, 0); /* IREXIT2 */ + jbi_jtag_io(1, 0, 0); /* IRUPDATE */ + jbi_jtag_io(1, 0, 0); /* DRSELECT */ + jbi_jtag_io(0, 0, 0); /* DRCAPTURE */ + jbi_jtag_io(0, 0, 0); /* DRSHIFT */ + break; + + default: + status = 0; + } + + if (status) + { + /* loop in the SHIFT-DR state */ + for (i = 0; i < count; i++) + { + tdo_bit = jbi_jtag_io( + (i == count - 1), + tdi[i >> 3] & (1 << (i & 7)), + (tdo != NULL)); + + if (tdo != NULL) + { + if (tdo_bit) + { + tdo[i >> 3] |= (1 << (i & 7)); + } + else + { + tdo[i >> 3] &= ~(unsigned int) (1 << (i & 7)); + } + } + } + + jbi_jtag_io(0, 0, 0); /* DRPAUSE */ + } + + return (status); +} + +int jbi_jtag_irscan +( + int start_state, + int count, + unsigned char *tdi, + unsigned char *tdo +) +{ + int i = 0; + int tdo_bit = 0; + int status = 1; + + /* + * First go to IRSHIFT state + */ + switch (start_state) + { + case 0: /* IDLE */ + jbi_jtag_io(1, 0, 0); /* DRSELECT */ + jbi_jtag_io(1, 0, 0); /* IRSELECT */ + jbi_jtag_io(0, 0, 0); /* IRCAPTURE */ + jbi_jtag_io(0, 0, 0); /* IRSHIFT */ + break; + + case 1: /* DRPAUSE */ + jbi_jtag_io(1, 0, 0); /* DREXIT2 */ + jbi_jtag_io(1, 0, 0); /* DRUPDATE */ + jbi_jtag_io(1, 0, 0); /* DRSELECT */ + jbi_jtag_io(1, 0, 0); /* IRSELECT */ + jbi_jtag_io(0, 0, 0); /* IRCAPTURE */ + jbi_jtag_io(0, 0, 0); /* IRSHIFT */ + break; + + case 2: /* IRPAUSE */ + jbi_jtag_io(1, 0, 0); /* IREXIT2 */ + jbi_jtag_io(1, 0, 0); /* IRUPDATE */ + jbi_jtag_io(1, 0, 0); /* DRSELECT */ + jbi_jtag_io(1, 0, 0); /* IRSELECT */ + jbi_jtag_io(0, 0, 0); /* IRCAPTURE */ + jbi_jtag_io(0, 0, 0); /* IRSHIFT */ + break; + + default: + status = 0; + } + + if (status) + { + /* loop in the SHIFT-IR state */ + for (i = 0; i < count; i++) + { + tdo_bit = jbi_jtag_io( + (i == count - 1), + tdi[i >> 3] & (1 << (i & 7)), + (tdo != NULL)); + + if (tdo != NULL) + { + if (tdo_bit) + { + tdo[i >> 3] |= (1 << (i & 7)); + } + else + { + tdo[i >> 3] &= ~(unsigned int) (1 << (i & 7)); + } + } + } + + jbi_jtag_io(0, 0, 0); /* IRPAUSE */ + } + + return (status); +} + +/****************************************************************************/ +/* */ + +void jbi_jtag_extract_target_data +( + unsigned char *buffer, + unsigned char *target_data, + unsigned int start_index, + unsigned int preamble_count, + unsigned int target_count +) + +/* */ +/* Description: Copies target data from scan buffer, filtering out */ +/* preamble and postamble data. */ +/* */ +/* Returns: nothing */ +/* */ +/****************************************************************************/ +{ + unsigned int i; + unsigned int j; + unsigned int k; + + j = preamble_count; + k = start_index + target_count; + for (i = start_index; i < k; ++i, ++j) + { + if (buffer[j >> 3] & (1 << (j & 7))) + { + target_data[i >> 3] |= (1 << (i & 7)); + } + else + { + target_data[i >> 3] &= ~(unsigned int) (1 << (i & 7)); + } + } +} + +/****************************************************************************/ +/* */ + +JBI_RETURN_TYPE jbi_do_irscan +( + unsigned int count, + unsigned char *tdi_data, + unsigned int start_index +) + +/* */ +/* Description: Shifts data into instruction register */ +/* */ +/* Returns: JBIC_SUCCESS for success, else appropriate error code */ +/* */ +/****************************************************************************/ +{ + int start_code = 0; + unsigned int alloc_chars = 0; + unsigned int shift_count = jbi_ir_preamble + count + jbi_ir_postamble; + JBI_RETURN_TYPE status = JBIC_SUCCESS; + JBIE_JTAG_STATE start_state = JBI_ILLEGAL_JTAG_STATE; + + switch (jbi_jtag_state) + { + case JBI_ILLEGAL_JTAG_STATE: + case RESET: + case IDLE: + start_code = 0; + start_state = IDLE; + break; + + case DRSELECT: + case DRCAPTURE: + case DRSHIFT: + case DREXIT1: + case DRPAUSE: + case DREXIT2: + case DRUPDATE: + start_code = 1; + start_state = DRPAUSE; + break; + + case IRSELECT: + case IRCAPTURE: + case IRSHIFT: + case IREXIT1: + case IRPAUSE: + case IREXIT2: + case IRUPDATE: + start_code = 2; + start_state = IRPAUSE; + break; + + default: + status = JBIC_INTERNAL_ERROR; + break; + } + + if (status == JBIC_SUCCESS) + { + if (jbi_jtag_state != start_state) + { + status = jbi_goto_jtag_state(start_state); + } + } + + if (status == JBIC_SUCCESS) + { + if (jbi_workspace != NULL) + { + if (shift_count > JBIC_MAX_JTAG_IR_LENGTH) + { + status = JBIC_OUT_OF_MEMORY; + } + } + else if (shift_count > jbi_ir_length) + { + alloc_chars = (shift_count + 7) >> 3; + jbi_free(jbi_ir_buffer); + jbi_ir_buffer = (unsigned char *) jbi_malloc(alloc_chars); + + if (jbi_ir_buffer == NULL) + { + status = JBIC_OUT_OF_MEMORY; + } + else + { + jbi_ir_length = alloc_chars * 8; + } + } + } + + if (status == JBIC_SUCCESS) + { + /* + * Copy preamble data, IR data, and postamble data into a buffer + */ + jbi_jtag_concatenate_data + ( + jbi_ir_buffer, + jbi_ir_preamble_data, + jbi_ir_preamble, + tdi_data, + start_index, + count, + jbi_ir_postamble_data, + jbi_ir_postamble + ); + + /* + * Do the IRSCAN + */ + jbi_jtag_irscan + ( + start_code, + shift_count, + jbi_ir_buffer, + NULL + ); + + /* jbi_jtag_irscan() always ends in IRPAUSE state */ + jbi_jtag_state = IRPAUSE; + } + + if (status == JBIC_SUCCESS) + { + if (jbi_irstop_state != IRPAUSE) + { + status = jbi_goto_jtag_state(jbi_irstop_state); + } + } + + return (status); +} + +/****************************************************************************/ +/* */ + +JBI_RETURN_TYPE jbi_swap_ir +( + unsigned int count, + unsigned char *in_data, + unsigned int in_index, + unsigned char *out_data, + unsigned int out_index +) + +/* */ +/* Description: Shifts data into instruction register, capturing output */ +/* data */ +/* */ +/* Returns: JBIC_SUCCESS for success, else appropriate error code */ +/* */ +/****************************************************************************/ +{ + int start_code = 0; + unsigned int alloc_chars = 0; + unsigned int shift_count = jbi_ir_preamble + count + jbi_ir_postamble; + JBI_RETURN_TYPE status = JBIC_SUCCESS; + JBIE_JTAG_STATE start_state = JBI_ILLEGAL_JTAG_STATE; + + switch (jbi_jtag_state) + { + case JBI_ILLEGAL_JTAG_STATE: + case RESET: + case IDLE: + start_code = 0; + start_state = IDLE; + break; + + case DRSELECT: + case DRCAPTURE: + case DRSHIFT: + case DREXIT1: + case DRPAUSE: + case DREXIT2: + case DRUPDATE: + start_code = 1; + start_state = DRPAUSE; + break; + + case IRSELECT: + case IRCAPTURE: + case IRSHIFT: + case IREXIT1: + case IRPAUSE: + case IREXIT2: + case IRUPDATE: + start_code = 2; + start_state = IRPAUSE; + break; + + default: + status = JBIC_INTERNAL_ERROR; + break; + } + + if (status == JBIC_SUCCESS) + { + if (jbi_jtag_state != start_state) + { + status = jbi_goto_jtag_state(start_state); + } + } + + if (status == JBIC_SUCCESS) + { + if (jbi_workspace != NULL) + { + if (shift_count > JBIC_MAX_JTAG_IR_LENGTH) + { + status = JBIC_OUT_OF_MEMORY; + } + } + else if (shift_count > jbi_ir_length) + { + alloc_chars = (shift_count + 7) >> 3; + jbi_free(jbi_ir_buffer); + jbi_ir_buffer = (unsigned char *) jbi_malloc(alloc_chars); + + if (jbi_ir_buffer == NULL) + { + status = JBIC_OUT_OF_MEMORY; + } + else + { + jbi_ir_length = alloc_chars * 8; + } + } + } + + if (status == JBIC_SUCCESS) + { + /* + * Copy preamble data, IR data, and postamble data into a buffer + */ + jbi_jtag_concatenate_data + ( + jbi_ir_buffer, + jbi_ir_preamble_data, + jbi_ir_preamble, + in_data, + in_index, + count, + jbi_ir_postamble_data, + jbi_ir_postamble + ); + + /* + * Do the IRSCAN + */ + jbi_jtag_irscan + ( + start_code, + shift_count, + jbi_ir_buffer, + jbi_ir_buffer + ); + + /* jbi_jtag_irscan() always ends in IRPAUSE state */ + jbi_jtag_state = IRPAUSE; + } + + if (status == JBIC_SUCCESS) + { + if (jbi_irstop_state != IRPAUSE) + { + status = jbi_goto_jtag_state(jbi_irstop_state); + } + } + + if (status == JBIC_SUCCESS) + { + /* + * Now extract the returned data from the buffer + */ + jbi_jtag_extract_target_data + ( + jbi_ir_buffer, + out_data, + out_index, + jbi_ir_preamble, + count + ); + } + + return (status); +} + +/****************************************************************************/ +/* */ + +JBI_RETURN_TYPE jbi_do_drscan +( + unsigned int count, + unsigned char *tdi_data, + unsigned long start_index +) + +/* */ +/* Description: Shifts data into data register (ignoring output data) */ +/* */ +/* Returns: JBIC_SUCCESS for success, else appropriate error code */ +/* */ +/****************************************************************************/ +{ + int start_code = 0; + unsigned int alloc_chars = 0; + unsigned int shift_count = jbi_dr_preamble + count + jbi_dr_postamble; + JBI_RETURN_TYPE status = JBIC_SUCCESS; + JBIE_JTAG_STATE start_state = JBI_ILLEGAL_JTAG_STATE; + + switch (jbi_jtag_state) + { + case JBI_ILLEGAL_JTAG_STATE: + case RESET: + case IDLE: + start_code = 0; + start_state = IDLE; + break; + + case DRSELECT: + case DRCAPTURE: + case DRSHIFT: + case DREXIT1: + case DRPAUSE: + case DREXIT2: + case DRUPDATE: + start_code = 1; + start_state = DRPAUSE; + break; + + case IRSELECT: + case IRCAPTURE: + case IRSHIFT: + case IREXIT1: + case IRPAUSE: + case IREXIT2: + case IRUPDATE: + start_code = 2; + start_state = IRPAUSE; + break; + + default: + status = JBIC_INTERNAL_ERROR; + break; + } + + if (status == JBIC_SUCCESS) + { + if (jbi_jtag_state != start_state) + { + status = jbi_goto_jtag_state(start_state); + } + } + + if (status == JBIC_SUCCESS) + { + if (jbi_workspace != NULL) + { + if (shift_count > JBIC_MAX_JTAG_DR_LENGTH) + { + status = JBIC_OUT_OF_MEMORY; + } + } + else if (shift_count > jbi_dr_length) + { + alloc_chars = (shift_count + 7) >> 3; + jbi_free(jbi_dr_buffer); + jbi_dr_buffer = (unsigned char *) jbi_malloc(alloc_chars); + + if (jbi_dr_buffer == NULL) + { + status = JBIC_OUT_OF_MEMORY; + } + else + { + jbi_dr_length = alloc_chars * 8; + } + } + } + + if (status == JBIC_SUCCESS) + { + /* + * Copy preamble data, DR data, and postamble data into a buffer + */ + jbi_jtag_concatenate_data + ( + jbi_dr_buffer, + jbi_dr_preamble_data, + jbi_dr_preamble, + tdi_data, + start_index, + count, + jbi_dr_postamble_data, + jbi_dr_postamble + ); + + /* + * Do the DRSCAN + */ + jbi_jtag_drscan + ( + start_code, + shift_count, + jbi_dr_buffer, + NULL + ); + + /* jbi_jtag_drscan() always ends in DRPAUSE state */ + jbi_jtag_state = DRPAUSE; + } + + if (status == JBIC_SUCCESS) + { + if (jbi_drstop_state != DRPAUSE) + { + status = jbi_goto_jtag_state(jbi_drstop_state); + } + } + + return (status); +} + +/****************************************************************************/ +/* */ + +JBI_RETURN_TYPE jbi_swap_dr +( + unsigned int count, + unsigned char *in_data, + unsigned long in_index, + unsigned char *out_data, + unsigned int out_index +) + +/* */ +/* Description: Shifts data into data register, capturing output data */ +/* */ +/* Returns: JBIC_SUCCESS for success, else appropriate error code */ +/* */ +/****************************************************************************/ +{ + int start_code = 0; + unsigned int alloc_chars = 0; + unsigned int shift_count = jbi_dr_preamble + count + jbi_dr_postamble; + JBI_RETURN_TYPE status = JBIC_SUCCESS; + JBIE_JTAG_STATE start_state = JBI_ILLEGAL_JTAG_STATE; + + switch (jbi_jtag_state) + { + case JBI_ILLEGAL_JTAG_STATE: + case RESET: + case IDLE: + start_code = 0; + start_state = IDLE; + break; + + case DRSELECT: + case DRCAPTURE: + case DRSHIFT: + case DREXIT1: + case DRPAUSE: + case DREXIT2: + case DRUPDATE: + start_code = 1; + start_state = DRPAUSE; + break; + + case IRSELECT: + case IRCAPTURE: + case IRSHIFT: + case IREXIT1: + case IRPAUSE: + case IREXIT2: + case IRUPDATE: + start_code = 2; + start_state = IRPAUSE; + break; + + default: + status = JBIC_INTERNAL_ERROR; + break; + } + + if (status == JBIC_SUCCESS) + { + if (jbi_jtag_state != start_state) + { + status = jbi_goto_jtag_state(start_state); + } + } + + if (status == JBIC_SUCCESS) + { + if (jbi_workspace != NULL) + { + if (shift_count > JBIC_MAX_JTAG_DR_LENGTH) + { + status = JBIC_OUT_OF_MEMORY; + } + } + else if (shift_count > jbi_dr_length) + { + alloc_chars = (shift_count + 7) >> 3; + jbi_free(jbi_dr_buffer); + jbi_dr_buffer = (unsigned char *) jbi_malloc(alloc_chars); + + if (jbi_dr_buffer == NULL) + { + status = JBIC_OUT_OF_MEMORY; + } + else + { + jbi_dr_length = alloc_chars * 8; + } + } + } + + if (status == JBIC_SUCCESS) + { + /* + * Copy preamble data, DR data, and postamble data into a buffer + */ + jbi_jtag_concatenate_data + ( + jbi_dr_buffer, + jbi_dr_preamble_data, + jbi_dr_preamble, + in_data, + in_index, + count, + jbi_dr_postamble_data, + jbi_dr_postamble + ); + + /* + * Do the DRSCAN + */ + jbi_jtag_drscan + ( + start_code, + shift_count, + jbi_dr_buffer, + jbi_dr_buffer + ); + + /* jbi_jtag_drscan() always ends in DRPAUSE state */ + jbi_jtag_state = DRPAUSE; + } + + if (status == JBIC_SUCCESS) + { + if (jbi_drstop_state != DRPAUSE) + { + status = jbi_goto_jtag_state(jbi_drstop_state); + } + } + + if (status == JBIC_SUCCESS) + { + /* + * Now extract the returned data from the buffer + */ + jbi_jtag_extract_target_data + ( + jbi_dr_buffer, + out_data, + out_index, + jbi_dr_preamble, + count + ); + } + + return (status); +} + +/****************************************************************************/ +/* */ + +void jbi_free_jtag_padding_buffers(int reset_jtag) + +/* */ +/* Description: Frees memory allocated for JTAG IR and DR buffers */ +/* */ +/* Returns: nothing */ +/* */ +/****************************************************************************/ +{ + /* + * If the JTAG interface was used, reset it to TLR + */ + if (reset_jtag && (jbi_jtag_state != JBI_ILLEGAL_JTAG_STATE)) + { + jbi_jtag_reset_idle(); + } + + if (jbi_workspace == NULL) + { + if (jbi_dr_preamble_data != NULL) + { + jbi_free(jbi_dr_preamble_data); + jbi_dr_preamble_data = NULL; + } + + if (jbi_dr_postamble_data != NULL) + { + jbi_free(jbi_dr_postamble_data); + jbi_dr_postamble_data = NULL; + } + + if (jbi_dr_buffer != NULL) + { + jbi_free(jbi_dr_buffer); + jbi_dr_buffer = NULL; + } + + if (jbi_ir_preamble_data != NULL) + { + jbi_free(jbi_ir_preamble_data); + jbi_ir_preamble_data = NULL; + } + + if (jbi_ir_postamble_data != NULL) + { + jbi_free(jbi_ir_postamble_data); + jbi_ir_postamble_data = NULL; + } + + if (jbi_ir_buffer != NULL) + { + jbi_free(jbi_ir_buffer); + jbi_ir_buffer = NULL; + } + } +} + +#if PORT==DOS + +/****************************************************************************/ +/* */ + +JBI_RETURN_TYPE jbi_do_drscan_multi_page +( + unsigned int variable_id, + unsigned long count, + unsigned long start_index, + int version +) + +/* */ +/* Description: Shifts data into data register (ignoring output data) */ +/* Scan data comes from compressed Boolean array. */ +/* */ +/* Returns: JBIC_SUCCESS for success, else appropriate error code */ +/* */ +/****************************************************************************/ +{ + JBI_RETURN_TYPE status = JBIC_SUCCESS; + unsigned long shift_count = jbi_dr_preamble + count + jbi_dr_postamble; + unsigned long i; + unsigned long j; + unsigned long k; + unsigned int bi; + + if (status == JBIC_SUCCESS) + { + status = jbi_goto_jtag_state(DRSHIFT); + } + + if (status == JBIC_SUCCESS) + { + /* + * Get preamble data, DR data, and postamble data one bit at a time + * and immediately scan it into the JTAG chain + */ + + for (i = 0L; i < jbi_dr_preamble; ++i) + { + jbi_jtag_io((i == shift_count - 1), + (int) (jbi_dr_preamble_data[i >> 3L] & (1L << (i & 7L))), 0); + } + + j = start_index; + k = jbi_dr_preamble + count; + + jbi_uncompress_page(variable_id, (unsigned int) (j >> 16L), version); + + for (; i < k; ++i, ++j) + { + bi = (unsigned int) (j & 0x0000ffffL); + + /* check for page boundary - load next page if necessary */ + if (bi == 0) + { + jbi_uncompress_page(variable_id, (unsigned int) (j >> 16L), version); + } + + jbi_jtag_io((i == shift_count - 1), + (int) (jbi_aca_out_buffer[bi >> 3] & (1 << (bi & 7))), 0); + } + + j = 0L; + k = jbi_dr_preamble + count + jbi_dr_postamble; + for (; i < k; ++i, ++j) + { + jbi_jtag_io((i == shift_count - 1), + (int) (jbi_dr_postamble_data[j >> 3L] & (1L << (j & 7L))), 0); + } + + jbi_jtag_io(0, 0, 0); /* DRPAUSE */ + + /* jbi_jtag_drscan() always ends in DRPAUSE state */ + jbi_jtag_state = DRPAUSE; + + if (jbi_drstop_state != DRPAUSE) + { + status = jbi_goto_jtag_state(jbi_drstop_state); + } + } + + return (status); +} + +#endif diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/jbijtag.h b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/jbijtag.h new file mode 100644 index 000000000000..fab2dac0266a --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/jbijtag.h @@ -0,0 +1,146 @@ +/****************************************************************************/ +/* */ +/* Module: jbijtag.h */ +/* */ +/* Copyright (C) Altera Corporation 1998-2001 */ +/* */ +/* Description: Definitions of JTAG constants, types, and functions */ +/* */ +/****************************************************************************/ + +#ifndef INC_JBIJTAG_H +#define INC_JBIJTAG_H + +/****************************************************************************/ +/* */ +/* Function Prototypes */ +/* */ +/****************************************************************************/ +typedef enum +{ + JBI_ILLEGAL_JTAG_STATE = -1, + RESET = 0, + IDLE = 1, + DRSELECT = 2, + DRCAPTURE = 3, + DRSHIFT = 4, + DREXIT1 = 5, + DRPAUSE = 6, + DREXIT2 = 7, + DRUPDATE = 8, + IRSELECT = 9, + IRCAPTURE = 10, + IRSHIFT = 11, + IREXIT1 = 12, + IRPAUSE = 13, + IREXIT2 = 14, + IRUPDATE = 15 + +} JBIE_JTAG_STATE; + +JBI_RETURN_TYPE jbi_init_jtag +( + void +); + +JBI_RETURN_TYPE jbi_set_drstop_state +( + JBIE_JTAG_STATE state +); + +JBI_RETURN_TYPE jbi_set_irstop_state +( + JBIE_JTAG_STATE state +); + +JBI_RETURN_TYPE jbi_set_dr_preamble +( + unsigned int count, + unsigned int start_index, + unsigned char *preamble_data +); + +JBI_RETURN_TYPE jbi_set_ir_preamble +( + unsigned int count, + unsigned int start_index, + unsigned char *preamble_data +); + +JBI_RETURN_TYPE jbi_set_dr_postamble +( + unsigned int count, + unsigned int start_index, + unsigned char *postamble_data +); + +JBI_RETURN_TYPE jbi_set_ir_postamble +( + unsigned int count, + unsigned int start_index, + unsigned char *postamble_data +); + +JBI_RETURN_TYPE jbi_goto_jtag_state +( + JBIE_JTAG_STATE state +); + +JBI_RETURN_TYPE jbi_do_wait_cycles +( + long cycles, + JBIE_JTAG_STATE wait_state +); + +JBI_RETURN_TYPE jbi_do_wait_microseconds +( + long microseconds, + JBIE_JTAG_STATE wait_state +); + +JBI_RETURN_TYPE jbi_do_irscan +( + unsigned int count, + unsigned char *tdi_data, + unsigned int start_index +); + +JBI_RETURN_TYPE jbi_swap_ir +( + unsigned int count, + unsigned char *in_data, + unsigned int in_index, + unsigned char *out_data, + unsigned int out_index +); + +JBI_RETURN_TYPE jbi_do_drscan +( + unsigned int count, + unsigned char *tdi_data, + unsigned long start_index +); + +JBI_RETURN_TYPE jbi_swap_dr +( + unsigned int count, + unsigned char *in_data, + unsigned long in_index, + unsigned char *out_data, + unsigned int out_index +); + +void jbi_free_jtag_padding_buffers +( + int reset_jtag +); + +JBI_RETURN_TYPE jbi_do_drscan_multi_page +( + unsigned int variable_id, + unsigned long long_count, + unsigned long long_index, + int version +); + +#endif /* INC_JBIJTAG_H */ diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/jbimain.c b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/jbimain.c new file mode 100644 index 000000000000..b8cab4857074 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/jbimain.c @@ -0,0 +1,3362 @@ +/****************************************************************************/ +/* */ +/* Module: jbimain.c */ +/* */ +/* Copyright (C) Altera Corporation 1998-2001 */ +/* */ +/* Description: Jam STAPL ByteCode Player (Interpreter) */ +/* */ +/* Revisions: 2.2 fixed /W4 warnings */ +/* 2.0 added support for STAPL ByteCode format */ +/* */ +/****************************************************************************/ + +#include "jbiport.h" +#include "jbiexprt.h" +#include "jbijtag.h" +#include "jbicomp.h" +#include "jbistub.h" + +/****************************************************************************/ +/* */ +/* MACROS */ +/* */ +/****************************************************************************/ + +#ifndef NULL +#define NULL 0 +#endif + +#define JBI_STACK_SIZE 128 + +#define JBIC_MESSAGE_LENGTH 1024 + +/* +* This macro checks if enough parameters are available on the stack. The +* argument is the number of parameters needed. +*/ +#define IF_CHECK_STACK(x) \ + if (stack_ptr < (int) (x)) \ + { \ + status = JBIC_STACK_OVERFLOW; \ + } \ + else + +/* +* This macro checks if a code address is inside the code section +*/ +#define CHECK_PC \ + if ((pc < code_section) || (pc >= debug_section)) \ + { \ + status = JBIC_BOUNDS_ERROR; \ + } + +/****************************************************************************/ +/* */ +/* GLOBAL VARIABLES */ +/* */ +/****************************************************************************/ + +#if PORT==DOS +/* +* jbi_program is a global pointer used by macros GET_BYTE, GET_WORD, and +* GET_DWORD to read data from the JBC file +*/ +PROGRAM_PTR jbi_program; +#endif + +/****************************************************************************/ +/* */ +/* UTILITY FUNCTIONS */ +/* */ +/****************************************************************************/ + +int jbi_strlen(char *string) +{ + int len = 0; + + while (string[len] != '\0') ++len; + + return (len); +} + +long jbi_atol(char *buffer) +{ + long result = 0L; + int index = 0; + + while ((buffer[index] >= '0') && (buffer[index] <= '9')) + { + result = (result * 10) + (buffer[index] - '0'); + ++index; + } + + return (result); +} + +void jbi_ltoa(char *buffer, long number) +{ + int index = 0; + int rev_index = 0; + char reverse[32]; + + if (number < 0L) + { + buffer[index++] = '-'; + number = 0 - number; + } + else if (number == 0) + { + buffer[index++] = '0'; + } + + while (number != 0) + { + reverse[rev_index++] = (char) ((number % 10) + '0'); + number /= 10; + } + + while (rev_index > 0) + { + buffer[index++] = reverse[--rev_index]; + } + + buffer[index] = '\0'; +} + +char jbi_toupper(char ch) +{ + return ((char) (((ch >= 'a') && (ch <= 'z')) ? (ch + 'A' - 'a') : ch)); +} + +int jbi_stricmp(char *left, char *right) +{ + int result = 0; + char l, r; + + do + { + l = jbi_toupper(*left); + r = jbi_toupper(*right); + result = l - r; + ++left; + ++right; + } + while ((result == 0) && (l != '\0') && (r != '\0')); + + return (result); +} + +void jbi_strncpy(char *left, char *right, int count) +{ + char ch; + + do + { + *left = *right; + ch = *right; + ++left; + ++right; + --count; + } + while ((ch != '\0') && (count != 0)); +} + +void jbi_make_dword(unsigned char *buf, unsigned long num) +{ + buf[0] = (unsigned char) num; + buf[1] = (unsigned char) (num >> 8L); + buf[2] = (unsigned char) (num >> 16L); + buf[3] = (unsigned char) (num >> 24L); +} + +unsigned long jbi_get_dword(unsigned char *buf) +{ + return + (((unsigned long) buf[0]) | + (((unsigned long) buf[1]) << 8L) | + (((unsigned long) buf[2]) << 16L) | + (((unsigned long) buf[3]) << 24L)); +} + +/****************************************************************************/ +/* */ + +JBI_RETURN_TYPE jbi_execute +( + PROGRAM_PTR program, + long program_size, + char *workspace, + long workspace_size, + char *action, + char **init_list, + int reset_jtag, + long *error_address, + int *exit_code, + int *format_version +) + +/* */ +/* Description: */ +/* */ +/* Returns: */ +/* */ +/****************************************************************************/ +{ + JBI_RETURN_TYPE status = JBIC_SUCCESS; + unsigned long first_word = 0L; + unsigned long action_table = 0L; + unsigned long proc_table = 0L; + unsigned long string_table = 0L; + unsigned long symbol_table = 0L; + unsigned long data_section = 0L; + unsigned long code_section = 0L; + unsigned long debug_section = 0L; + unsigned long action_count = 0L; + unsigned long proc_count = 0L; + unsigned long symbol_count = 0L; + /*char message_buffer[JBIC_MESSAGE_LENGTH + 1];*/ + char *message_buffer; + addr_t *variables = NULL; + long *variable_size = NULL; + char *attributes = NULL; + unsigned char *proc_attributes = NULL; + unsigned long pc; + unsigned long opcode_address; + unsigned long args[3]; + unsigned int opcode; + unsigned long name_id; + addr_t stack[JBI_STACK_SIZE] = {0}; + unsigned char charbuf[4]; + long long_temp; + unsigned int variable_id; + unsigned char *charptr_temp; + unsigned char *charptr_temp2; + long *longptr_temp; + int version = 0; + int delta = 0; + int stack_ptr = 0; + unsigned int arg_count; + int done = 0; + int bad_opcode = 0; + unsigned int count; + unsigned int index; + unsigned int index2; + long long_count; + long long_index; + long long_index2; + unsigned int i; + unsigned int j; + unsigned long uncompressed_size, uncompressed_result; + unsigned int offset; + unsigned long value; + int current_proc = 0; + char *equal_ptr; + int length; + int reverse; + + unsigned long debug_cnt = 0; + +#if PORT==DOS + char name[33]; +#else + char *name; +#endif + + jbi_workspace = workspace; + jbi_workspace_size = workspace_size; + +#if PORT==DOS + jbi_program = program; +#endif + + /* Resolve compilation warnings: the frame size of 1664 bytes is larger than 1024 bytes */ + message_buffer = (char *) kzalloc(JBIC_MESSAGE_LENGTH + 1, GFP_KERNEL); + if (message_buffer == NULL) { + jbi_dbg(DEBUG_DETAIL, "Memory not enough jbi_execute \n"); + return JBIC_OUT_OF_MEMORY; + } + + /* + * Read header information + */ + if (program_size > 52L) + { + first_word = GET_DWORD(0); + version = (int) (first_word & 1L); + *format_version = version + 1; + delta = version * 8; + + action_table = GET_DWORD(4); + proc_table = GET_DWORD(8); + string_table = GET_DWORD(4 + delta); + symbol_table = GET_DWORD(16 + delta); + data_section = GET_DWORD(20 + delta); + code_section = GET_DWORD(24 + delta); + debug_section = GET_DWORD(28 + delta); + action_count = GET_DWORD(40 + delta); + proc_count = GET_DWORD(44 + delta); + symbol_count = GET_DWORD(48 + (2 * delta)); + + jbi_dbg(DEBUG_DETAIL, "version: %d\n", version); + jbi_dbg(DEBUG_DETAIL, "delta: %d\n", delta); + jbi_dbg(DEBUG_DETAIL, "action_table: 0x%08lx\n", action_table); + jbi_dbg(DEBUG_DETAIL, "proc_table: 0x%08lx\n", proc_table); + jbi_dbg(DEBUG_DETAIL, "string_table: 0x%08lx\n", string_table); + jbi_dbg(DEBUG_DETAIL, "symbol_table: 0x%08lx\n", symbol_table); + jbi_dbg(DEBUG_DETAIL, "data_section: 0x%08lx\n", data_section); + jbi_dbg(DEBUG_DETAIL, "code_section: 0x%08lx\n", code_section); + jbi_dbg(DEBUG_DETAIL, "debug_section: 0x%08lx\n", debug_section); + jbi_dbg(DEBUG_DETAIL, "action_count: 0x%08lx\n", action_count); + jbi_dbg(DEBUG_DETAIL, "proc_count: 0x%08lx\n", proc_count); + jbi_dbg(DEBUG_DETAIL, "symbol_count: 0x%08lx\n", symbol_count); + jbi_dbg(DEBUG_DETAIL, "\n"); + } + + if ((first_word != 0x4A414D00L) && (first_word != 0x4A414D01L)) + { + jbi_dbg(DEBUG_ERR, "first_word 0x%lx\n", first_word); + done = 1; + status = JBIC_IO_ERROR; + } + + if ((status == JBIC_SUCCESS) && (symbol_count > 0)) + { + variables = (addr_t *) jbi_malloc( + (unsigned int) symbol_count * sizeof(long)); + + if (variables == NULL) status = JBIC_OUT_OF_MEMORY; + + if (status == JBIC_SUCCESS) + { + variable_size = (long *) jbi_malloc( + (unsigned int) symbol_count * sizeof(long)); + + if (variable_size == NULL) status = JBIC_OUT_OF_MEMORY; + } + + if (status == JBIC_SUCCESS) + { + attributes = (char *) jbi_malloc((unsigned int) symbol_count); + + if (attributes == NULL) status = JBIC_OUT_OF_MEMORY; + } + + if ((status == JBIC_SUCCESS) && (version > 0)) + { + proc_attributes = (unsigned char *) jbi_malloc((unsigned int) proc_count); + + if (proc_attributes == NULL) status = JBIC_OUT_OF_MEMORY; + } + + if (status == JBIC_SUCCESS) + { + delta = version * 2; + + for (i = 0; i < (unsigned int) symbol_count; ++i) + { + offset = (unsigned int) (symbol_table + ((11 + delta) * i)); + + value = GET_DWORD(offset + 3 + delta); + + attributes[i] = GET_BYTE(offset); + + /* use bit 7 of attribute byte to indicate that this buffer */ + /* was dynamically allocated and should be freed later */ + attributes[i] &= 0x7f; + + variable_size[i] = GET_DWORD(offset + 7 + delta); + + jbi_dbg(DEBUG_NOISY, "symbol %03d: 0x%02x,0x%08lx,0x%08lx\n", + i, attributes[i], value, variable_size[i]); + + /* + * Attribute bits: + * bit 0: 0 = read-only, 1 = read-write + * bit 1: 0 = not compressed, 1 = compressed + * bit 2: 0 = not initialized, 1 = initialized + * bit 3: 0 = scalar, 1 = array + * bit 4: 0 = Boolean, 1 = integer + * bit 5: 0 = declared variable, + * 1 = compiler created temporary variable + */ + + if ((attributes[i] & 0x0c) == 0x04) + { + /* initialized scalar variable */ + variables[i] = value; + } + else if ((attributes[i] & 0x1e) == 0x0e) + { + /* initialized compressed Boolean array */ +#if PORT==DOS + /* for DOS port, get the size but do not uncompress */ + long_index = data_section + value; + uncompressed_size = + (((unsigned long) GET_BYTE(long_index)) | + (((unsigned long) GET_BYTE(long_index + 1L)) << 8L) | + (((unsigned long) GET_BYTE(long_index + 2L)) << 16L) | + (((unsigned long) GET_BYTE(long_index + 3L)) << 24L)); + variable_size[i] = uncompressed_size; +#else + uncompressed_size = jbi_get_dword( + &program[data_section + value]); + + /* allocate a buffer for the uncompressed data */ + variables[i] = (addr_t) jbi_malloc(uncompressed_size); + + if (variables[i] == (addr_t) 0L) + { + status = JBIC_OUT_OF_MEMORY; + } + else + { + /* set flag so buffer will be freed later */ + attributes[i] |= 0x80; + + /* uncompress the data */ + uncompressed_result = + jbi_uncompress( + &program[data_section + value], + variable_size[i], + (unsigned char *) variables[i], + uncompressed_size, + version); + if (uncompressed_result != uncompressed_size) + { + /* decompression failed */ + jbi_dbg(DEBUG_ERR, "uncompress fail(0x%lx,0x%lx,0x%lx)(0x%lx)\n", + variable_size[i], uncompressed_result, uncompressed_size, value); + status = JBIC_IO_ERROR; + } + else + { + variable_size[i] = uncompressed_size * 8L; + } + } +#endif + } + else if ((attributes[i] & 0x1e) == 0x0c) + { + /* initialized Boolean array */ +#if PORT==DOS + /* flag attributes so that memory is freed */ + attributes[i] |= 0x80; + + if (variable_size[i] > 0) + { + unsigned int size = (unsigned int) + ((variable_size[i] + 7L) / 8L); + + variables[i] = (long) jbi_malloc(size); + + if (variables[i] == NULL) + { + status = JBIC_OUT_OF_MEMORY; + } + else + { + unsigned char *p = (unsigned char *) variables[i]; + /* copy array values into buffer */ + for (j = 0; j < size; ++j) + { + p[j] = GET_BYTE(data_section + value + j); + } + } + } + else + { + variables[i] = 0; + } +#else + variables[i] = value + data_section + (addr_t) program; +#endif + } + else if ((attributes[i] & 0x1c) == 0x1c) + { + /* initialized integer array */ + variables[i] = value + data_section; + } + else if ((attributes[i] & 0x0c) == 0x08) + { + /* uninitialized array */ + + /* flag attributes so that memory is freed */ + attributes[i] |= 0x80; + + if (variable_size[i] > 0) + { + unsigned int size; + + if (attributes[i] & 0x10) + { + /* integer array */ + size = (unsigned int) + (variable_size[i] * sizeof(long)); + } + else + { + /* Boolean array */ + size = (unsigned int) + ((variable_size[i] + 7L) / 8L); + } + + variables[i] = (addr_t) jbi_malloc(size); + + if (variables[i] == (addr_t) NULL) + { + status = JBIC_OUT_OF_MEMORY; + } + else + { + /* zero out memory */ + for (j = 0; j < size; ++j) + { + ((unsigned char *)(variables[i]))[j] = 0; + } + } + } + else + { + variables[i] = 0; + } + } + else + { + variables[i] = 0; + } + + jbi_dbg(DEBUG_NOISY, " variables: 0x%08lx,0x%016llx\n", + variable_size[i], (long long) variables[i]); + } + } + + jbi_dbg(DEBUG_NOISY, "\n"); + } + + /* + * Initialize variables listed in init_list + */ + if ((status == JBIC_SUCCESS) && (init_list != NULL) && (version == 0)) + { + delta = version * 2; + count = 0; + while (init_list[count] != NULL) + { + equal_ptr = init_list[count]; + length = 0; + while ((*equal_ptr != '=') && (*equal_ptr != '\0')) + { + ++equal_ptr; + ++length; + } + if (*equal_ptr == '=') + { + ++equal_ptr; + value = jbi_atol(equal_ptr); + jbi_strncpy(message_buffer, init_list[count], length); + message_buffer[length] = '\0'; + for (i = 0; i < (unsigned int) symbol_count; ++i) + { + offset = (unsigned int) (symbol_table + ((11 + delta) * i)); + name_id = (version == 0) ? GET_WORD(offset + 1) : + GET_DWORD(offset + 1); +#if PORT==DOS + for (j = 0; j < 32; ++j) + { + name[j] = GET_BYTE(string_table + name_id + j); + } + name[32] = '\0'; +#else + name = (char *) &program[string_table + name_id]; +#endif + + if (jbi_stricmp(message_buffer, name) == 0) + { + variables[i] = value; + } + + jbi_dbg(DEBUG_NOISY, "init_list %03d: 0x%08lx,%s,0x%016llx\n", + i, name_id, name, (long long) variables[i]); + } + } + + ++count; + } + + jbi_dbg(DEBUG_NOISY, "\n"); + } + + if (status != JBIC_SUCCESS) done = 1; + + jbi_init_jtag(); + + pc = code_section; + message_buffer[0] = '\0'; + + /* + * For JBC version 2, we will execute the procedures corresponding to + * the selected ACTION + */ + if (version > 0) + { + if (action == NULL) + { + status = JBIC_ACTION_NOT_FOUND; + done = 1; + } + else + { + int action_found = 0; + + for (i = 0; (i < action_count) && !action_found; ++i) + { + name_id = GET_DWORD(action_table + (12 * i)); + +#if PORT==DOS + for (j = 0; j < 32; ++j) + { + name[j] = GET_BYTE(string_table + name_id + j); + } + name[32] = '\0'; +#else + name = (char *) &program[string_table + name_id]; +#endif + + if (jbi_stricmp(action, name) == 0) + { + action_found = 1; + current_proc = (int) GET_DWORD(action_table + (12 * i) + 8); + } + + jbi_dbg(DEBUG_NOISY, "action %03d: 0x%08lx,%s, %d,%d\n", + i, name_id, name, action_found, current_proc); + } + + if (!action_found) + { + status = JBIC_ACTION_NOT_FOUND; + done = 1; + } + } + + if (status == JBIC_SUCCESS) + { + int first_time = 1; + i = current_proc; + while ((i != 0) || first_time) + { + first_time = 0; + /* check procedure attribute byte */ + proc_attributes[i] = (unsigned char) + (GET_BYTE(proc_table + (13 * i) + 8) & 0x03); + + jbi_dbg(DEBUG_NOISY, " proc_attributes %03d: 0x%02x\n", + i, proc_attributes[i]); + + if (proc_attributes[i] != 0) + { + /* + * BIT0 - OPTIONAL + * BIT1 - RECOMMENDED + * BIT6 - FORCED OFF + * BIT7 - FORCED ON + */ + if (init_list != NULL) + { + name_id = GET_DWORD(proc_table + (13 * i)); +#if PORT==DOS + for (j = 0; j < 32; ++j) + { + name[j] = GET_BYTE(string_table + name_id + j); + } + name[32] = '\0'; +#else + name = (char *) &program[string_table + name_id]; +#endif + + jbi_dbg(DEBUG_NOISY, " init_list %03d: 0x%08lx,%s\n", + i, name_id, name); + + count = 0; + while (init_list[count] != NULL) + { + equal_ptr = init_list[count]; + length = 0; + while ((*equal_ptr != '=') && (*equal_ptr != '\0')) + { + ++equal_ptr; + ++length; + } + if (*equal_ptr == '=') + { + ++equal_ptr; + jbi_strncpy(message_buffer, init_list[count], length); + message_buffer[length] = '\0'; + + if (jbi_stricmp(message_buffer, name) == 0) + { + if (jbi_atol(equal_ptr) == 0) + { + proc_attributes[i] |= 0x40; + } + else + { + proc_attributes[i] |= 0x80; + } + } + } + + jbi_dbg(DEBUG_NOISY, " proc_attributes %03d: 0x%02x\n", + i, proc_attributes[i]); + + ++count; + } + } + } + + i = (unsigned int) GET_DWORD(proc_table + (13 * i) + 4); + } + + /* + * Set current_proc to the first procedure to be executed + */ + i = current_proc; + while ((i != 0) && + ((proc_attributes[i] == 1) || + ((proc_attributes[i] & 0xc0) == 0x40))) + { + i = (unsigned int) GET_DWORD(proc_table + (13 * i) + 4); + } + + if ((i != 0) || ((i == 0) && (current_proc == 0) && + ((proc_attributes[0] != 1) && + ((proc_attributes[0] & 0xc0) != 0x40)))) + { + current_proc = i; + pc = code_section + GET_DWORD(proc_table + (13 * i) + 9); + CHECK_PC; + } + else + { + /* there are no procedures to execute! */ + done = 1; + } + } + + jbi_dbg(DEBUG_NOISY, "\n"); + } + + message_buffer[0] = '\0'; + + jbi_dbg(DEBUG_NOISY, "excute pc: 0x%lx,%d\n", pc, current_proc); + while (!done) + { + opcode = (unsigned int) (GET_BYTE(pc) & 0xff); + debug_cnt++; + jbi_dbg(DEBUG_NOISY, "op: 0x%02x(%03d:0x%08lx,%08lx)", + opcode, stack_ptr, pc, debug_cnt); + opcode_address = pc; + ++pc; + + arg_count = (opcode >> 6) & 3; + jbi_dbg(DEBUG_NOISY, " - %u:", arg_count); + for (i = 0; i < arg_count; ++i) + { + args[i] = GET_DWORD(pc); + jbi_dbg(DEBUG_NOISY, " 0x%08lx", args[i]); + pc += 4; + } + jbi_dbg(DEBUG_NOISY, "\n"); + + switch (opcode) + { + case 0x00: /* NOP */ + /* do nothing */ + break; + + case 0x01: /* DUP */ + IF_CHECK_STACK(1) + { + stack[stack_ptr] = stack[stack_ptr - 1]; + ++stack_ptr; + } + break; + + case 0x02: /* SWP */ + IF_CHECK_STACK(2) + { + long_temp = stack[stack_ptr - 2]; + stack[stack_ptr - 2] = stack[stack_ptr - 1]; + stack[stack_ptr - 1] = long_temp; + } + break; + + case 0x03: /* ADD */ + IF_CHECK_STACK(2) + { + --stack_ptr; + stack[stack_ptr - 1] += stack[stack_ptr]; + } + break; + + case 0x04: /* SUB */ + IF_CHECK_STACK(2) + { + --stack_ptr; + stack[stack_ptr - 1] -= stack[stack_ptr]; + } + break; + + case 0x05: /* MULT */ + IF_CHECK_STACK(2) + { + --stack_ptr; + stack[stack_ptr - 1] *= stack[stack_ptr]; + } + break; + + case 0x06: /* DIV */ + IF_CHECK_STACK(2) + { + --stack_ptr; + stack[stack_ptr - 1] /= stack[stack_ptr]; + } + break; + + case 0x07: /* MOD */ + IF_CHECK_STACK(2) + { + --stack_ptr; + stack[stack_ptr - 1] %= stack[stack_ptr]; + } + break; + + case 0x08: /* SHL */ + IF_CHECK_STACK(2) + { + --stack_ptr; + stack[stack_ptr - 1] <<= stack[stack_ptr]; + } + break; + + case 0x09: /* SHR */ + IF_CHECK_STACK(2) + { + --stack_ptr; + stack[stack_ptr - 1] >>= stack[stack_ptr]; + } + break; + + case 0x0A: /* NOT */ + IF_CHECK_STACK(1) + { + stack[stack_ptr - 1] ^= (-1L); + } + break; + + case 0x0B: /* AND */ + IF_CHECK_STACK(2) + { + --stack_ptr; + stack[stack_ptr - 1] &= stack[stack_ptr]; + } + break; + + case 0x0C: /* OR */ + IF_CHECK_STACK(2) + { + --stack_ptr; + stack[stack_ptr - 1] |= stack[stack_ptr]; + } + break; + + case 0x0D: /* XOR */ + IF_CHECK_STACK(2) + { + --stack_ptr; + stack[stack_ptr - 1] ^= stack[stack_ptr]; + } + break; + + case 0x0E: /* INV */ + IF_CHECK_STACK(1) + { + stack[stack_ptr - 1] = stack[stack_ptr - 1] ? 0L : 1L; + } + break; + + case 0x0F: /* GT */ + IF_CHECK_STACK(2) + { + --stack_ptr; + stack[stack_ptr - 1] = + (stack[stack_ptr - 1] > stack[stack_ptr]) ? 1L : 0L; + } + break; + + case 0x10: /* LT */ + IF_CHECK_STACK(2) + { + --stack_ptr; + stack[stack_ptr - 1] = + (stack[stack_ptr - 1] < stack[stack_ptr]) ? 1L : 0L; + } + break; + + case 0x11: /* RET */ + if ((version > 0) && (stack_ptr == 0)) + { + /* + * We completed one of the main procedures of an ACTION. + * Find the next procedure to be executed and jump to it. + * If there are no more procedures, then EXIT. + */ + i = (unsigned int) GET_DWORD(proc_table + (13 * current_proc) + 4); + while ((i != 0) && + ((proc_attributes[i] == 1) || + ((proc_attributes[i] & 0xc0) == 0x40))) + { + i = (unsigned int) GET_DWORD(proc_table + (13 * i) + 4); + } + + if (i == 0) + { + /* there are no procedures to execute! */ + done = 1; + *exit_code = 0; /* success */ + } + else + { + current_proc = i; + pc = code_section + GET_DWORD(proc_table + (13 * i) + 9); + CHECK_PC; + } + } + else IF_CHECK_STACK(1) + { + pc = stack[--stack_ptr] + code_section; + CHECK_PC; + if (pc == code_section) + { + status = JBIC_BOUNDS_ERROR; + } + } + break; + + case 0x12: /* CMPS */ + /* + * Array short compare + * ...stack 0 is source 1 value + * ...stack 1 is source 2 value + * ...stack 2 is mask value + * ...stack 3 is count + */ + IF_CHECK_STACK(4) + { + long a = stack[--stack_ptr]; + long b = stack[--stack_ptr]; + long_temp = stack[--stack_ptr]; + count = (unsigned int) stack[stack_ptr - 1]; + + if ((count < 1) || (count > 32)) + { + status = JBIC_BOUNDS_ERROR; + } + else + { + long_temp &= ((-1L) >> (32 - count)); + + stack[stack_ptr - 1] = + ((a & long_temp) == (b & long_temp)) ? 1L : 0L; + } + } + break; + + case 0x13: /* PINT */ + /* + * PRINT add integer + * ...stack 0 is integer value + */ + IF_CHECK_STACK(1) + { + jbi_ltoa(&message_buffer[jbi_strlen(message_buffer)], + stack[--stack_ptr]); + } + break; + + case 0x14: /* PRNT */ + /* + * PRINT finish + */ + jbi_message(message_buffer); + message_buffer[0] = '\0'; + break; + + case 0x15: /* DSS */ + /* + * DRSCAN short + * ...stack 0 is scan data + * ...stack 1 is count + */ + IF_CHECK_STACK(2) + { + long_temp = stack[--stack_ptr]; + count = (unsigned int) stack[--stack_ptr]; + jbi_make_dword(charbuf, long_temp); + status = jbi_do_drscan(count, charbuf, 0); + } + break; + + case 0x16: /* DSSC */ + /* + * DRSCAN short with capture + * ...stack 0 is scan data + * ...stack 1 is count + */ + IF_CHECK_STACK(2) + { + long_temp = stack[--stack_ptr]; + count = (unsigned int) stack[stack_ptr - 1]; + jbi_make_dword(charbuf, long_temp); + status = jbi_swap_dr(count, charbuf, 0, charbuf, 0); + stack[stack_ptr - 1] = jbi_get_dword(charbuf); + } + break; + + case 0x17: /* ISS */ + /* + * IRSCAN short + * ...stack 0 is scan data + * ...stack 1 is count + */ + IF_CHECK_STACK(2) + { + long_temp = stack[--stack_ptr]; + count = (unsigned int) stack[--stack_ptr]; + jbi_make_dword(charbuf, long_temp); + status = jbi_do_irscan(count, charbuf, 0); + } + break; + + case 0x18: /* ISSC */ + /* + * IRSCAN short with capture + * ...stack 0 is scan data + * ...stack 1 is count + */ + IF_CHECK_STACK(2) + { + long_temp = stack[--stack_ptr]; + count = (unsigned int) stack[stack_ptr - 1]; + jbi_make_dword(charbuf, long_temp); + status = jbi_swap_ir(count, charbuf, 0, charbuf, 0); + stack[stack_ptr - 1] = jbi_get_dword(charbuf); + } + break; + + case 0x19: /* VSS */ + /* + * VECTOR short + * ...stack 0 is scan data + * ...stack 1 is count + */ + bad_opcode = 1; + break; + + case 0x1A: /* VSSC */ + /* + * VECTOR short with capture + * ...stack 0 is scan data + * ...stack 1 is count + */ + bad_opcode = 1; + break; + + case 0x1B: /* VMPF */ + /* + * VMAP finish + */ + bad_opcode = 1; + break; + + case 0x1C: /* DPR */ + IF_CHECK_STACK(1) + { + count = (unsigned int) stack[--stack_ptr]; + status = jbi_set_dr_preamble(count, 0, NULL); + } + break; + + case 0x1D: /* DPRL */ + /* + * DRPRE with literal data + * ...stack 0 is count + * ...stack 1 is literal data + */ + IF_CHECK_STACK(2) + { + count = (unsigned int) stack[--stack_ptr]; + long_temp = stack[--stack_ptr]; + jbi_make_dword(charbuf, long_temp); + status = jbi_set_dr_preamble(count, 0, charbuf); + } + break; + + case 0x1E: /* DPO */ + /* + * DRPOST + * ...stack 0 is count + */ + IF_CHECK_STACK(1) + { + count = (unsigned int) stack[--stack_ptr]; + status = jbi_set_dr_postamble(count, 0, NULL); + } + break; + + case 0x1F: /* DPOL */ + /* + * DRPOST with literal data + * ...stack 0 is count + * ...stack 1 is literal data + */ + IF_CHECK_STACK(2) + { + count = (unsigned int) stack[--stack_ptr]; + long_temp = stack[--stack_ptr]; + jbi_make_dword(charbuf, long_temp); + status = jbi_set_dr_postamble(count, 0, charbuf); + } + break; + + case 0x20: /* IPR */ + IF_CHECK_STACK(1) + { + count = (unsigned int) stack[--stack_ptr]; + status = jbi_set_ir_preamble(count, 0, NULL); + } + break; + + case 0x21: /* IPRL */ + /* + * IRPRE with literal data + * ...stack 0 is count + * ...stack 1 is literal data + */ + IF_CHECK_STACK(2) + { + count = (unsigned int) stack[--stack_ptr]; + long_temp = stack[--stack_ptr]; + jbi_make_dword(charbuf, long_temp); + status = jbi_set_ir_preamble(count, 0, charbuf); + } + break; + + case 0x22: /* IPO */ + /* + * IRPOST + * ...stack 0 is count + */ + IF_CHECK_STACK(1) + { + count = (unsigned int) stack[--stack_ptr]; + status = jbi_set_ir_postamble(count, 0, NULL); + } + break; + + case 0x23: /* IPOL */ + /* + * IRPOST with literal data + * ...stack 0 is count + * ...stack 1 is literal data + */ + IF_CHECK_STACK(2) + { + count = (unsigned int) stack[--stack_ptr]; + long_temp = stack[--stack_ptr]; + jbi_make_dword(charbuf, long_temp); + status = jbi_set_ir_postamble(count, 0, charbuf); + } + break; + + case 0x24: /* PCHR */ + IF_CHECK_STACK(1) + { + unsigned char ch; + count = jbi_strlen(message_buffer); + ch = (char) stack[--stack_ptr]; + if ((ch < 1) || (ch > 127)) + { + /* character code out of range */ + /* instead of flagging an error, force the value to 127 */ + ch = 127; + } + message_buffer[count] = ch; + message_buffer[count + 1] = '\0'; + } + break; + + case 0x25: /* EXIT */ + IF_CHECK_STACK(1) + { + *exit_code = (int) stack[--stack_ptr]; + } + done = 1; + break; + + case 0x26: /* EQU */ + IF_CHECK_STACK(2) + { + --stack_ptr; + stack[stack_ptr - 1] = + (stack[stack_ptr - 1] == stack[stack_ptr]) ? 1L : 0L; + } + break; + + case 0x27: /* POPT */ + IF_CHECK_STACK(1) + { + --stack_ptr; + } + break; + + case 0x28: /* TRST */ + bad_opcode = 1; + break; + + case 0x29: /* FRQ */ + bad_opcode = 1; + break; + + case 0x2A: /* FRQU */ + bad_opcode = 1; + break; + + case 0x2B: /* PD32 */ + bad_opcode = 1; + break; + + case 0x2C: /* ABS */ + IF_CHECK_STACK(1) + { + if (stack[stack_ptr - 1] < 0) + { + stack[stack_ptr - 1] = 0 - stack[stack_ptr - 1]; + } + } + break; + + case 0x2D: /* BCH0 */ + /* + * Batch operation 0 + * SWP + * SWPN 7 + * SWP + * SWPN 6 + * DUPN 8 + * SWPN 2 + * SWP + * DUPN 6 + * DUPN 6 + */ + + /* SWP */ + IF_CHECK_STACK(2) + { + long_temp = stack[stack_ptr - 2]; + stack[stack_ptr - 2] = stack[stack_ptr - 1]; + stack[stack_ptr - 1] = long_temp; + } + + /* SWPN 7 */ + index = 7 + 1; + IF_CHECK_STACK(index) + { + long_temp = stack[stack_ptr - index]; + stack[stack_ptr - index] = stack[stack_ptr - 1]; + stack[stack_ptr - 1] = long_temp; + } + + /* SWP */ + IF_CHECK_STACK(2) + { + long_temp = stack[stack_ptr - 2]; + stack[stack_ptr - 2] = stack[stack_ptr - 1]; + stack[stack_ptr - 1] = long_temp; + } + + /* SWPN 6 */ + index = 6 + 1; + IF_CHECK_STACK(index) + { + long_temp = stack[stack_ptr - index]; + stack[stack_ptr - index] = stack[stack_ptr - 1]; + stack[stack_ptr - 1] = long_temp; + } + + /* DUPN 8 */ + index = 8 + 1; + IF_CHECK_STACK(index) + { + stack[stack_ptr] = stack[stack_ptr - index]; + ++stack_ptr; + } + + /* SWPN 2 */ + index = 2 + 1; + IF_CHECK_STACK(index) + { + long_temp = stack[stack_ptr - index]; + stack[stack_ptr - index] = stack[stack_ptr - 1]; + stack[stack_ptr - 1] = long_temp; + } + + /* SWP */ + IF_CHECK_STACK(2) + { + long_temp = stack[stack_ptr - 2]; + stack[stack_ptr - 2] = stack[stack_ptr - 1]; + stack[stack_ptr - 1] = long_temp; + } + + /* DUPN 6 */ + index = 6 + 1; + IF_CHECK_STACK(index) + { + stack[stack_ptr] = stack[stack_ptr - index]; + ++stack_ptr; + } + + /* DUPN 6 */ + index = 6 + 1; + IF_CHECK_STACK(index) + { + stack[stack_ptr] = stack[stack_ptr - index]; + ++stack_ptr; + } + break; + + case 0x2E: /* BCH1 */ + /* + * Batch operation 1 + * SWPN 8 + * SWP + * SWPN 9 + * SWPN 3 + * SWP + * SWPN 2 + * SWP + * SWPN 7 + * SWP + * SWPN 6 + * DUPN 5 + * DUPN 5 + */ + bad_opcode = 1; + break; + + case 0x2F: /* PSH0 */ + stack[stack_ptr++] = 0; + break; + + case 0x40: /* PSHL */ + stack[stack_ptr++] = (long) args[0]; + break; + + case 0x41: /* PSHV */ + stack[stack_ptr++] = variables[args[0]]; + break; + + case 0x42: /* JMP */ + pc = args[0] + code_section; + CHECK_PC; + break; + + case 0x43: /* CALL */ + stack[stack_ptr++] = pc; + pc = args[0] + code_section; + CHECK_PC; + break; + + case 0x44: /* NEXT */ + /* + * Process FOR / NEXT loop + * ...argument 0 is variable ID + * ...stack 0 is step value + * ...stack 1 is end value + * ...stack 2 is top address + */ + IF_CHECK_STACK(3) + { + long step = stack[stack_ptr - 1]; + long end = stack[stack_ptr - 2]; + long top = stack[stack_ptr - 3]; + long iterator = variables[args[0]]; + int break_out = 0; + + if (step < 0) + { + if (iterator <= end) break_out = 1; + } + else + { + if (iterator >= end) break_out = 1; + } + + if (break_out) + { + stack_ptr -= 3; + } + else + { + variables[args[0]] = iterator + step; + pc = top + code_section; + CHECK_PC; + } + } + break; + + case 0x45: /* PSTR */ + /* + * PRINT add string + * ...argument 0 is string ID + */ +#if PORT==DOS + long_index = string_table + args[0]; + index2 = jbi_strlen(message_buffer); + + do + { + i = GET_BYTE(long_index); + message_buffer[index2] = (char) i; + ++long_index; + ++index2; + } + while ((i != '\0') && (index2 < JBIC_MESSAGE_LENGTH)); +#else + count = jbi_strlen(message_buffer); + jbi_strncpy(&message_buffer[count], + (char *) &program[string_table + args[0]], + JBIC_MESSAGE_LENGTH - count); +#endif + message_buffer[JBIC_MESSAGE_LENGTH] = '\0'; + break; + + case 0x46: /* VMAP */ + /* + * VMAP add signal name + * ...argument 0 is string ID + */ + bad_opcode = 1; + break; + + case 0x47: /* SINT */ + /* + * STATE intermediate state + * ...argument 0 is state code + */ + status = jbi_goto_jtag_state((int) args[0]); + break; + + case 0x48: /* ST */ + /* + * STATE final state + * ...argument 0 is state code + */ + status = jbi_goto_jtag_state((int) args[0]); + break; + + case 0x49: /* ISTP */ + /* + * IRSTOP state + * ...argument 0 is state code + */ + status = jbi_set_irstop_state((int) args[0]); + break; + + case 0x4A: /* DSTP */ + /* + * DRSTOP state + * ...argument 0 is state code + */ + status = jbi_set_drstop_state((int) args[0]); + break; + + case 0x4B: /* SWPN */ + /* + * Exchange top with Nth stack value + * ...argument 0 is 0-based stack entry to swap with top element + */ + index = ((int) args[0]) + 1; + IF_CHECK_STACK(index) + { + long_temp = stack[stack_ptr - index]; + stack[stack_ptr - index] = stack[stack_ptr - 1]; + stack[stack_ptr - 1] = long_temp; + } + break; + + case 0x4C: /* DUPN */ + /* + * Duplicate Nth stack value + * ...argument 0 is 0-based stack entry to duplicate + */ + index = ((int) args[0]) + 1; + IF_CHECK_STACK(index) + { + stack[stack_ptr] = stack[stack_ptr - index]; + ++stack_ptr; + } + break; + + case 0x4D: /* POPV */ + /* + * Pop stack into scalar variable + * ...argument 0 is variable ID + * ...stack 0 is value + */ + IF_CHECK_STACK(1) + { + variables[args[0]] = stack[--stack_ptr]; + } + break; + + case 0x4E: /* POPE */ + /* + * Pop stack into integer array element + * ...argument 0 is variable ID + * ...stack 0 is array index + * ...stack 1 is value + */ + IF_CHECK_STACK(2) + { + variable_id = (unsigned int) args[0]; + + /* + * If variable is read-only, convert to writable array + */ + if ((version > 0) && + ((attributes[variable_id] & 0x9c) == 0x1c)) + { + /* + * Allocate a writable buffer for this array + */ + count = (unsigned int) variable_size[variable_id]; + long_temp = variables[variable_id]; + longptr_temp = (long *) jbi_malloc(count * sizeof(long)); + variables[variable_id] = (addr_t) longptr_temp; + + if (variables[variable_id] == (addr_t) NULL) + { + status = JBIC_OUT_OF_MEMORY; + break; + } + else + { + /* copy previous contents into buffer */ + for (i = 0; i < count; ++i) + { + longptr_temp[i] = GET_DWORD(long_temp); + long_temp += 4L; + } + + /* set bit 7 - buffer was dynamically allocated */ + attributes[variable_id] |= 0x80; + + /* clear bit 2 - variable is writable */ + attributes[variable_id] &= ~0x04; + attributes[variable_id] |= 0x01; + } + } + +#if PORT==DOS + /* for 16-bit version, allow writing in allocated buffers */ + if ((version > 0) && + ((attributes[variable_id] & 0x9c) == 0x9c)) + { + attributes[variable_id] &= ~0x04; + attributes[variable_id] |= 0x01; + } +#endif + + /* check that variable is a writable integer array */ + if ((attributes[variable_id] & 0x1c) != 0x18) + { + status = JBIC_BOUNDS_ERROR; + } + else + { + longptr_temp = (long *) variables[variable_id]; + + /* pop the array index */ + index = (unsigned int) stack[--stack_ptr]; + + /* pop the value and store it into the array */ + longptr_temp[index] = stack[--stack_ptr]; + } + } + break; + + case 0x4F: /* POPA */ + /* + * Pop stack into Boolean array + * ...argument 0 is variable ID + * ...stack 0 is count + * ...stack 1 is array index + * ...stack 2 is value + */ + IF_CHECK_STACK(3) + { + variable_id = (unsigned int) args[0]; + + /* + * If variable is read-only, convert to writable array + */ + if ((version > 0) && + ((attributes[variable_id] & 0x9c) == 0x0c)) + { + /* + * Allocate a writable buffer for this array + */ + long_temp = (variable_size[variable_id] + 7L) >> 3L; + charptr_temp2 = (unsigned char *) variables[variable_id]; + charptr_temp = jbi_malloc((unsigned int) long_temp); + variables[variable_id] = (addr_t) charptr_temp; + + if (variables[variable_id] == (addr_t) NULL) + { + status = JBIC_OUT_OF_MEMORY; + } + else + { + /* zero the buffer */ + for (long_index = 0L; + long_index < long_temp; + ++long_index) + { + charptr_temp[long_index] = 0; + } + + /* copy previous contents into buffer */ + for (long_index = 0L; + long_index < variable_size[variable_id]; + ++long_index) + { +#if PORT==DOS + if ((attributes[variable_id] & 0x02) && + ((long_index & 0x0000FFFF) == 0L)) + { + /* initialized compressed Boolean array */ + jbi_uncompress_page(variable_id, + (int) (long_index >> 16), version); + charptr_temp = jbi_aca_out_buffer; + long_index2 = long_index & 0xFFFF; + } +#else + long_index2 = long_index; +#endif + + if (charptr_temp2[long_index2 >> 3] & + (1 << (long_index2 & 7))) + { + charptr_temp[long_index >> 3] |= + (1 << (long_index & 7)); + } + } + + /* set bit 7 - buffer was dynamically allocated */ + attributes[variable_id] |= 0x80; + + /* clear bit 2 - variable is writable */ + attributes[variable_id] &= ~0x04; + attributes[variable_id] |= 0x01; + } + } + +#if PORT==DOS + /* for 16-bit version, allow writing in allocated buffers */ + if ((version > 0) && + ((attributes[variable_id] & 0x9c) == 0x8c)) + { + attributes[variable_id] &= ~0x04; + attributes[variable_id] |= 0x01; + } +#endif + + /* check that variable is a writable Boolean array */ + if ((attributes[variable_id] & 0x1c) != 0x08) + { + status = JBIC_BOUNDS_ERROR; + } + else + { + charptr_temp = (unsigned char *) variables[variable_id]; + + /* pop the count (number of bits to copy) */ + long_count = stack[--stack_ptr]; + + /* pop the array index */ + long_index = stack[--stack_ptr]; + + reverse = 0; + + if (version > 0) + { + /* stack 0 = array right index */ + /* stack 1 = array left index */ + + if (long_index > long_count) + { + reverse = 1; + long_temp = long_count; + long_count = 1 + long_index - long_count; + long_index = long_temp; + + /* reverse POPA is not supported */ + status = JBIC_BOUNDS_ERROR; + break; + } + else + { + long_count = 1 + long_count - long_index; + } + } + + /* pop the data */ + long_temp = stack[--stack_ptr]; + + if (long_count < 1) + { + status = JBIC_BOUNDS_ERROR; + } + else + { + for (i = 0; i < (unsigned int) long_count; ++i) + { + if (long_temp & (1L << (long) i)) + { + charptr_temp[long_index >> 3L] |= + (1L << (long_index & 7L)); + } + else + { + charptr_temp[long_index >> 3L] &= + ~ (unsigned int) (1L << (long_index & 7L)); + } + ++long_index; + } + } + } + } + break; + + case 0x50: /* JMPZ */ + /* + * Pop stack and branch if zero + * ...argument 0 is address + * ...stack 0 is condition value + */ + IF_CHECK_STACK(1) + { + if (stack[--stack_ptr] == 0) + { + pc = args[0] + code_section; + CHECK_PC; + } + } + break; + + case 0x51: /* DS */ + case 0x52: /* IS */ + /* + * DRSCAN + * IRSCAN + * ...argument 0 is scan data variable ID + * ...stack 0 is array index + * ...stack 1 is count + */ + IF_CHECK_STACK(2) + { + long_index = stack[--stack_ptr]; + long_count = stack[--stack_ptr]; + + reverse = 0; + + if (version > 0) + { + /* stack 0 = array right index */ + /* stack 1 = array left index */ + /* stack 2 = count */ + long_temp = long_count; + long_count = stack[--stack_ptr]; + + if (long_index > long_temp) + { + reverse = 1; + long_index = long_temp; + } + } + +#if PORT==DOS + if (((long_index & 0xFFFF0000) == 0) && + ((long_count & 0xFFFF0000) == 0)) + { + variable_id = (unsigned int) args[0]; + if ((attributes[variable_id] & 0x1e) == 0x0e) + { + /* initialized compressed Boolean array */ + jbi_uncompress_page(variable_id, + (int) (long_index >> 16), version); + long_index &= 0x0000ffff; + charptr_temp = jbi_aca_out_buffer; + } + else + { + charptr_temp = (unsigned char *) variables[variable_id]; + } + + if (reverse) + { + /* allocate a buffer and reverse the data order */ + charptr_temp2 = charptr_temp; + charptr_temp = jbi_malloc((unsigned int) + ((long_count >> 3L) + 1L)); + + if (charptr_temp == NULL) + { + status = JBIC_OUT_OF_MEMORY; + break; + } + else + { + long_temp = long_index + long_count - 1; + long_index2 = 0; + while (long_index2 < long_count) + { + if (charptr_temp2[long_temp >> 3] & + (1 << (long_temp & 7))) + { + charptr_temp[long_index2 >> 3] |= + (1 << (long_index2 & 7)); + } + else + { + charptr_temp[long_index2 >> 3] &= + ~(1 << (long_index2 & 7)); + } + + --long_temp; + ++long_index2; + } + } + } + + if (opcode == 0x51) /* DS */ + { + status = jbi_do_drscan((unsigned int) long_count, + charptr_temp, (unsigned long) long_index); + } + else /* IS */ + { + status = jbi_do_irscan((unsigned int) long_count, + charptr_temp, (unsigned int) long_index); + } + + if (reverse) jbi_free(charptr_temp); + } + else if ((opcode == 0x51) && !reverse) + { + status = jbi_do_drscan_multi_page( + (unsigned int) args[0], + (unsigned long) long_count, + (unsigned long) long_index, version); + } + else + { + /* reverse multi-page scans are not supported */ + /* multi-page IR scans are not supported */ + status = JBIC_BOUNDS_ERROR; + } +#else + charptr_temp = (unsigned char *) variables[args[0]]; + + if (reverse) + { + /* allocate a buffer and reverse the data order */ + charptr_temp2 = charptr_temp; + charptr_temp = jbi_malloc((long_count >> 3) + 1); + if (charptr_temp == NULL) + { + status = JBIC_OUT_OF_MEMORY; + break; + } + else + { + long_temp = long_index + long_count - 1; + long_index2 = 0; + while (long_index2 < long_count) + { + if (charptr_temp2[long_temp >> 3] & + (1 << (long_temp & 7))) + { + charptr_temp[long_index2 >> 3] |= + (1 << (long_index2 & 7)); + } + else + { + charptr_temp[long_index2 >> 3] &= + ~(1 << (long_index2 & 7)); + } + + --long_temp; + ++long_index2; + } + } + } + + if (opcode == 0x51) /* DS */ + { + status = jbi_do_drscan((unsigned int) long_count, + charptr_temp, (unsigned long) long_index); + } + else /* IS */ + { + status = jbi_do_irscan((unsigned int) long_count, + charptr_temp, (unsigned int) long_index); + } +#endif + + if (reverse && (charptr_temp != NULL)) + { + jbi_free(charptr_temp); + } + } + break; + + case 0x53: /* DPRA */ + /* + * DRPRE with array data + * ...argument 0 is variable ID + * ...stack 0 is array index + * ...stack 1 is count + */ + IF_CHECK_STACK(2) + { + index = (unsigned int) stack[--stack_ptr]; + count = (unsigned int) stack[--stack_ptr]; + + if (version > 0) + { + /* stack 0 = array right index */ + /* stack 1 = array left index */ + count = 1 + count - index; + } + + charptr_temp = (unsigned char *) variables[args[0]]; + status = jbi_set_dr_preamble(count, index, charptr_temp); + } + break; + + case 0x54: /* DPOA */ + /* + * DRPOST with array data + * ...argument 0 is variable ID + * ...stack 0 is array index + * ...stack 1 is count + */ + IF_CHECK_STACK(2) + { + index = (unsigned int) stack[--stack_ptr]; + count = (unsigned int) stack[--stack_ptr]; + + if (version > 0) + { + /* stack 0 = array right index */ + /* stack 1 = array left index */ + count = 1 + count - index; + } + + charptr_temp = (unsigned char *) variables[args[0]]; + status = jbi_set_dr_postamble(count, index, charptr_temp); + } + break; + + case 0x55: /* IPRA */ + /* + * IRPRE with array data + * ...argument 0 is variable ID + * ...stack 0 is array index + * ...stack 1 is count + */ + IF_CHECK_STACK(2) + { + index = (unsigned int) stack[--stack_ptr]; + count = (unsigned int) stack[--stack_ptr]; + + if (version > 0) + { + /* stack 0 = array right index */ + /* stack 1 = array left index */ + count = 1 + count - index; + } + + charptr_temp = (unsigned char *) variables[args[0]]; + status = jbi_set_ir_preamble(count, index, charptr_temp); + } + break; + + case 0x56: /* IPOA */ + /* + * IRPOST with array data + * ...argument 0 is variable ID + * ...stack 0 is array index + * ...stack 1 is count + */ + IF_CHECK_STACK(2) + { + index = (unsigned int) stack[--stack_ptr]; + count = (unsigned int) stack[--stack_ptr]; + + if (version > 0) + { + /* stack 0 = array right index */ + /* stack 1 = array left index */ + count = 1 + count - index; + } + + charptr_temp = (unsigned char *) variables[args[0]]; + status = jbi_set_ir_postamble(count, index, charptr_temp); + } + break; + + case 0x57: /* EXPT */ + /* + * EXPORT + * ...argument 0 is string ID + * ...stack 0 is integer expression + */ + IF_CHECK_STACK(1) + { +#if PORT==DOS + name_id = args[0]; + for (j = 0; j < 32; ++j) + { + name[j] = GET_BYTE(string_table + name_id + j); + } + name[32] = '\0'; +#else + name = (char *) &program[string_table + args[0]]; +#endif + long_temp = stack[--stack_ptr]; + jbi_export_integer(name, long_temp); + } + break; + + case 0x58: /* PSHE */ + /* + * Push integer array element + * ...argument 0 is variable ID + * ...stack 0 is array index + */ + IF_CHECK_STACK(1) + { + variable_id = (unsigned int) args[0]; + index = (unsigned int) stack[stack_ptr - 1]; + + /* check variable type */ + if ((attributes[variable_id] & 0x1f) == 0x19) + { + /* writable integer array */ + longptr_temp = (long *) variables[variable_id]; + stack[stack_ptr - 1] = longptr_temp[index]; + } + else if ((attributes[variable_id] & 0x1f) == 0x1c) + { + /* read-only integer array */ + long_temp = variables[variable_id] + (4L * index); + stack[stack_ptr - 1] = GET_DWORD(long_temp); + } + else + { + status = JBIC_BOUNDS_ERROR; + } + } + break; + + case 0x59: /* PSHA */ + /* + * Push Boolean array + * ...argument 0 is variable ID + * ...stack 0 is count + * ...stack 1 is array index + */ + IF_CHECK_STACK(2) + { + variable_id = (unsigned int) args[0]; + + /* check that variable is a Boolean array */ + if ((attributes[variable_id] & 0x18) != 0x08) + { + status = JBIC_BOUNDS_ERROR; + } + else + { + charptr_temp = (unsigned char *) variables[variable_id]; + + /* pop the count (number of bits to copy) */ + count = (unsigned int) stack[--stack_ptr]; + + /* pop the array index */ + index = (unsigned int) stack[stack_ptr - 1]; + + if (version > 0) + { + /* stack 0 = array right index */ + /* stack 1 = array left index */ + count = 1 + count - index; + } + + if ((count < 1) || (count > 32)) + { + status = JBIC_BOUNDS_ERROR; + } + else + { +#if PORT==DOS + if ((attributes[variable_id] & 0x1e) == 0x0e) + { + /* initialized compressed Boolean array */ + jbi_uncompress_page(variable_id, + (int) (stack[stack_ptr - 1] >> 16), version); + charptr_temp = jbi_aca_out_buffer; + } +#endif + long_temp = 0L; + + for (i = 0; i < count; ++i) + { + if (charptr_temp[(i + index) >> 3] & + (1 << ((i + index) & 7))) + { + long_temp |= (1L << i); + } + } + + stack[stack_ptr - 1] = long_temp; + } + } + } + break; + + case 0x5A: /* DYNA */ + /* + * Dynamically change size of array + * ...argument 0 is variable ID + * ...stack 0 is new size + */ + IF_CHECK_STACK(1) + { + variable_id = (unsigned int) args[0]; + long_temp = stack[--stack_ptr]; + + if (long_temp > variable_size[variable_id]) + { + variable_size[variable_id] = long_temp; + + if (attributes[variable_id] & 0x10) + { + /* allocate integer array */ + long_temp *= 4; + } + else + { + /* allocate Boolean array */ + long_temp = (long_temp + 7) >> 3; + } + + /* + * If the buffer was previously allocated, free it + */ + if ((attributes[variable_id] & 0x80) && + (variables[variable_id] != (addr_t) NULL)) + { + jbi_free((void *) variables[variable_id]); + variables[variable_id] = (addr_t) NULL; + } + + /* + * Allocate a new buffer of the requested size + */ + variables[variable_id] = (addr_t) + jbi_malloc((unsigned int) long_temp); + + if (variables[variable_id] == (addr_t) NULL) + { + status = JBIC_OUT_OF_MEMORY; + } + else + { + /* + * Set the attribute bit to indicate that this buffer + * was dynamically allocated and should be freed later + */ + attributes[variable_id] |= 0x80; + + /* zero out memory */ + count = (unsigned int) + ((variable_size[variable_id] + 7L) / 8L); + charptr_temp = (unsigned char *) + (variables[variable_id]); + for (index = 0; index < count; ++index) + { + charptr_temp[index] = 0; + } + } + } + } + break; + + case 0x5B: /* EXPR */ + bad_opcode = 1; + break; + + case 0x5C: /* EXPV */ + /* + * Export Boolean array + * ...argument 0 is string ID + * ...stack 0 is variable ID + * ...stack 1 is array right index + * ...stack 2 is array left index + */ + IF_CHECK_STACK(3) + { + if (version == 0) + { + /* EXPV is not supported in JBC 1.0 */ + bad_opcode = 1; + break; + } +#if PORT==DOS + name_id = args[0]; + for (j = 0; j < 32; ++j) + { + name[j] = GET_BYTE(string_table + name_id + j); + } + name[32] = '\0'; +#else + name = (char *) &program[string_table + args[0]]; +#endif + variable_id = (unsigned int) stack[--stack_ptr]; + long_index = stack[--stack_ptr]; /* right index */ + long_index2 = stack[--stack_ptr]; /* left index */ + + if (long_index > long_index2) + { + /* reverse indices not supported */ + status = JBIC_BOUNDS_ERROR; + break; + } + + long_count = 1 + long_index2 - long_index; + + charptr_temp = (unsigned char *) variables[variable_id]; + charptr_temp2 = NULL; + +#if PORT==DOS + if ((attributes[variable_id] & 0x1e) == 0x0e) + { + /* initialized compressed Boolean array */ + jbi_uncompress_page(variable_id, + (int) (long_index >> 16), version); + charptr_temp = jbi_aca_out_buffer; + long_index &= 0x0000FFFF; + } +#endif + + if ((long_index & 7L) != 0) + { + charptr_temp2 = jbi_malloc((unsigned int) + ((long_count + 7L) / 8L)); + if (charptr_temp2 == NULL) + { + status = JBIC_OUT_OF_MEMORY; + break; + } + else + { + long k = long_index; + for (i = 0; i < (unsigned int) long_count; ++i) + { + if (charptr_temp[k >> 3] & (1 << (k & 7))) + { + charptr_temp2[i >> 3] |= (1 << (i & 7)); + } + else + { + charptr_temp2[i >> 3] &= ~(1 << (i & 7)); + } + + ++k; + } + charptr_temp = charptr_temp2; + } + } + else if (long_index != 0) + { + charptr_temp = &charptr_temp[long_index >> 3]; + } + + jbi_export_boolean_array(name, charptr_temp, long_count); + + /* free allocated buffer */ + if (((long_index & 7L) != 0) && (charptr_temp2 != NULL)) + { + jbi_free(charptr_temp2); + } + } + break; + + case 0x80: /* COPY */ + /* + * Array copy + * ...argument 0 is dest ID + * ...argument 1 is source ID + * ...stack 0 is count + * ...stack 1 is dest index + * ...stack 2 is source index + */ + IF_CHECK_STACK(3) + { + long copy_count = stack[--stack_ptr]; + long copy_index = stack[--stack_ptr]; + long copy_index2 = stack[--stack_ptr]; + long destleft; + long src_count; + long dest_count; + int src_reverse = 0; + int dest_reverse = 0; + + reverse = 0; + + if (version > 0) + { + /* stack 0 = source right index */ + /* stack 1 = source left index */ + /* stack 2 = destination right index */ + /* stack 3 = destination left index */ + destleft = stack[--stack_ptr]; + + if (copy_count > copy_index) + { + src_reverse = 1; + reverse = 1; + src_count = 1 + copy_count - copy_index; + /* copy_index = source start index */ + } + else + { + src_count = 1 + copy_index - copy_count; + copy_index = copy_count; /* source start index */ + } + + if (copy_index2 > destleft) + { + dest_reverse = 1; + reverse = !reverse; + dest_count = 1 + copy_index2 - destleft; + copy_index2 = destleft; /* destination start index */ + } + else + { + dest_count = 1 + destleft - copy_index2; + /* copy_index2 = destination start index */ + } + + copy_count = (src_count < dest_count) ? src_count : dest_count; + + if ((src_reverse || dest_reverse) && + (src_count != dest_count)) + { + /* If either the source or destination is reversed, */ + /* we can't tolerate a length mismatch, because we */ + /* "left justify" the arrays when copying. This */ + /* won't work correctly with reversed arrays. */ + status = JBIC_BOUNDS_ERROR; + } + } + + count = (unsigned int) copy_count; + index = (unsigned int) copy_index; + index2 = (unsigned int) copy_index2; + + /* + * If destination is a read-only array, allocate a buffer + * and convert it to a writable array + */ + variable_id = (unsigned int) args[1]; + if ((version > 0) && ((attributes[variable_id] & 0x9c) == 0x0c)) + { + /* + * Allocate a writable buffer for this array + */ + long_temp = (variable_size[variable_id] + 7L) >> 3L; + charptr_temp2 = (unsigned char *) variables[variable_id]; + charptr_temp = jbi_malloc((unsigned int) long_temp); + variables[variable_id] = (addr_t) charptr_temp; + + if (variables[variable_id] == (addr_t) NULL) + { + status = JBIC_OUT_OF_MEMORY; + break; + } + else + { + /* zero the buffer */ + for (long_index = 0L; + long_index < long_temp; + ++long_index) + { + charptr_temp[long_index] = 0; + } + + /* copy previous contents into buffer */ + for (long_index = 0L; + long_index < variable_size[variable_id]; + ++long_index) + { +#if PORT==DOS + if ((attributes[variable_id] & 0x02) && + ((long_index & 0x0000FFFF) == 0L)) + { + /* initialized compressed Boolean array */ + jbi_uncompress_page(variable_id, + (int) (long_index >> 16), version); + charptr_temp = jbi_aca_out_buffer; + long_index2 = long_index & 0xFFFF; + } +#else + long_index2 = long_index; +#endif + + if (charptr_temp2[long_index2 >> 3] & + (1 << (long_index2 & 7))) + { + charptr_temp[long_index >> 3] |= + (1 << (long_index & 7)); + } + } + + /* set bit 7 - buffer was dynamically allocated */ + attributes[variable_id] |= 0x80; + + /* clear bit 2 - variable is writable */ + attributes[variable_id] &= ~0x04; + attributes[variable_id] |= 0x01; + } + } + +#if PORT==DOS + /* for 16-bit version, allow writing in allocated buffers */ + if ((version > 0) && + ((attributes[variable_id] & 0x9c) == 0x8c)) + { + attributes[variable_id] &= ~0x04; + attributes[variable_id] |= 0x01; + } +#endif + + charptr_temp = (unsigned char *) variables[args[1]]; + charptr_temp2 = (unsigned char *) variables[args[0]]; + +#if PORT==DOS + variable_id = (unsigned int) args[0]; + if ((attributes[variable_id] & 0x1e) == 0x0e) + { + /* initialized compressed Boolean array */ + jbi_uncompress_page(variable_id, + (int) (copy_index >> 16), version); + charptr_temp2 = jbi_aca_out_buffer; + } +#endif + + /* check that destination is a writable Boolean array */ + if ((attributes[args[1]] & 0x1c) != 0x08) + { + status = JBIC_BOUNDS_ERROR; + break; + } + + if (count < 1) + { + status = JBIC_BOUNDS_ERROR; + } + else + { + if (reverse) + { + index2 += (count - 1); + } + + for (i = 0; i < count; ++i) + { + if (charptr_temp2[index >> 3] & (1 << (index & 7))) + { + charptr_temp[index2 >> 3] |= (1 << (index2 & 7)); + } + else + { + charptr_temp[index2 >> 3] &= + ~(unsigned int) (1 << (index2 & 7)); + } + ++index; + if (reverse) --index2; else ++index2; + } + } + } + break; + + case 0x81: /* REVA */ + /* + * ARRAY COPY reversing bit order + * ...argument 0 is dest ID + * ...argument 1 is source ID + * ...stack 0 is dest index + * ...stack 1 is source index + * ...stack 2 is count + */ + bad_opcode = 1; + break; + + case 0x82: /* DSC */ + case 0x83: /* ISC */ + /* + * DRSCAN with capture + * IRSCAN with capture + * ...argument 0 is scan data variable ID + * ...argument 1 is capture variable ID + * ...stack 0 is capture index + * ...stack 1 is scan data index + * ...stack 2 is count + */ + IF_CHECK_STACK(3) + { + long scan_right, scan_left; + long capture_count = 0; + long scan_count = 0; + long capture_index = stack[--stack_ptr]; + long scan_index = stack[--stack_ptr]; + if (version > 0) + { + /* stack 0 = capture right index */ + /* stack 1 = capture left index */ + /* stack 2 = scan right index */ + /* stack 3 = scan left index */ + /* stack 4 = count */ + scan_right = stack[--stack_ptr]; + scan_left = stack[--stack_ptr]; + capture_count = 1 + scan_index - capture_index; + scan_count = 1 + scan_left - scan_right; + scan_index = scan_right; + } + long_count = stack[--stack_ptr]; + + /* + * If capture array is read-only, allocate a buffer + * and convert it to a writable array + */ + variable_id = (unsigned int) args[1]; + if ((version > 0) && ((attributes[variable_id] & 0x9c) == 0x0c)) + { + /* + * Allocate a writable buffer for this array + */ + long_temp = (variable_size[variable_id] + 7L) >> 3L; + charptr_temp2 = (unsigned char *) variables[variable_id]; + charptr_temp = jbi_malloc((unsigned int) long_temp); + variables[variable_id] = (addr_t) charptr_temp; + + if (variables[variable_id] == (addr_t) NULL) + { + status = JBIC_OUT_OF_MEMORY; + break; + } + else + { + /* zero the buffer */ + for (long_index = 0L; + long_index < long_temp; + ++long_index) + { + charptr_temp[long_index] = 0; + } + + /* copy previous contents into buffer */ + for (long_index = 0L; + long_index < variable_size[variable_id]; + ++long_index) + { +#if PORT==DOS + if ((attributes[variable_id] & 0x02) && + ((long_index & 0x0000FFFF) == 0L)) + { + /* initialized compressed Boolean array */ + jbi_uncompress_page(variable_id, + (int) (long_index >> 16), version); + charptr_temp = jbi_aca_out_buffer; + long_index2 = long_index & 0xFFFF; + } +#else + long_index2 = long_index; +#endif + + if (charptr_temp2[long_index2 >> 3] & + (1 << (long_index2 & 7))) + { + charptr_temp[long_index >> 3] |= + (1 << (long_index & 7)); + } + } + + /* set bit 7 - buffer was dynamically allocated */ + attributes[variable_id] |= 0x80; + + /* clear bit 2 - variable is writable */ + attributes[variable_id] &= ~0x04; + attributes[variable_id] |= 0x01; + } + } + +#if PORT==DOS + /* for 16-bit version, allow writing in allocated buffers */ + if ((version > 0) && + ((attributes[variable_id] & 0x9c) == 0x8c)) + { + attributes[variable_id] &= ~0x04; + attributes[variable_id] |= 0x01; + } +#endif + + charptr_temp = (unsigned char *) variables[args[0]]; + charptr_temp2 = (unsigned char *) variables[args[1]]; + +#if PORT==DOS + variable_id = (unsigned int) args[0]; + if ((attributes[variable_id] & 0x1e) == 0x0e) + { + /* initialized compressed Boolean array */ + jbi_uncompress_page(variable_id, + (int) (scan_index >> 16), version); + scan_index &= 0x0000ffff; + charptr_temp = jbi_aca_out_buffer; + } +#endif + + if ((version > 0) && + ((long_count > capture_count) || (long_count > scan_count))) + { + status = JBIC_BOUNDS_ERROR; + } + + /* check that capture array is a writable Boolean array */ + if ((attributes[args[1]] & 0x1c) != 0x08) + { + status = JBIC_BOUNDS_ERROR; + } + + if (status == JBIC_SUCCESS) + { + if (opcode == 0x82) /* DSC */ + { + status = jbi_swap_dr((unsigned int) long_count, + charptr_temp, (unsigned long) scan_index, + charptr_temp2, (unsigned int) capture_index); + } + else /* ISC */ + { + status = jbi_swap_ir((unsigned int) long_count, + charptr_temp, (unsigned int) scan_index, + charptr_temp2, (unsigned int) capture_index); + } + } + } + break; + + case 0x84: /* WAIT */ + /* + * WAIT + * ...argument 0 is wait state + * ...argument 1 is end state + * ...stack 0 is cycles + * ...stack 1 is microseconds + */ + IF_CHECK_STACK(2) + { + long_temp = stack[--stack_ptr]; + + if (long_temp != 0L) + { + status = jbi_do_wait_cycles(long_temp, (unsigned int) args[0]); + } + + long_temp = stack[--stack_ptr]; + + if ((status == JBIC_SUCCESS) && (long_temp != 0L)) + { + status = jbi_do_wait_microseconds(long_temp, (unsigned int) args[0]); + } + + if ((status == JBIC_SUCCESS) && (args[1] != args[0])) + { + status = jbi_goto_jtag_state((unsigned int) args[1]); + } + + if (version > 0) + { + --stack_ptr; /* throw away MAX cycles */ + --stack_ptr; /* throw away MAX microseconds */ + } + } + break; + + case 0x85: /* VS */ + /* + * VECTOR + * ...argument 0 is dir data variable ID + * ...argument 1 is scan data variable ID + * ...stack 0 is dir array index + * ...stack 1 is scan array index + * ...stack 2 is count + */ + bad_opcode = 1; + break; + + case 0xC0: /* CMPA */ + /* + * Array compare + * ...argument 0 is source 1 ID + * ...argument 1 is source 2 ID + * ...argument 2 is mask ID + * ...stack 0 is source 1 index + * ...stack 1 is source 2 index + * ...stack 2 is mask index + * ...stack 3 is count + */ + IF_CHECK_STACK(4) + { + long a, b; + unsigned char *source1 = (unsigned char *) variables[args[0]]; + unsigned char *source2 = (unsigned char *) variables[args[1]]; + unsigned char *mask = (unsigned char *) variables[args[2]]; + unsigned long index1 = stack[--stack_ptr]; + unsigned long index2 = stack[--stack_ptr]; + unsigned long mask_index = stack[--stack_ptr]; + long_count = stack[--stack_ptr]; + + if (version > 0) + { + /* stack 0 = source 1 right index */ + /* stack 1 = source 1 left index */ + /* stack 2 = source 2 right index */ + /* stack 3 = source 2 left index */ + /* stack 4 = mask right index */ + /* stack 5 = mask left index */ + long mask_right = stack[--stack_ptr]; + long mask_left = stack[--stack_ptr]; + a = 1 + index2 - index1; /* source 1 count */ + b = 1 + long_count - mask_index; /* source 2 count */ + a = (a < b) ? a : b; + b = 1 + mask_left - mask_right; /* mask count */ + a = (a < b) ? a : b; + index2 = mask_index; /* source 2 start index */ + mask_index = mask_right; /* mask start index */ + long_count = a; + } + + long_temp = 1L; + + if (long_count < 1) + { + status = JBIC_BOUNDS_ERROR; + } + else + { +#if PORT==DOS + variable_id = (unsigned int) args[0]; + if ((attributes[variable_id] & 0x1e) == 0x0e) + { + jbi_uncompress_page(variable_id, + (int) (index1 >> 16), version); + index1 &= 0x0000ffff; + source1 = jbi_aca_out_buffer; + } + + variable_id = (unsigned int) args[1]; + if ((attributes[variable_id] & 0x1e) == 0x0e) + { + jbi_uncompress_page(variable_id, + (int) (index2 >> 16), version); + index2 &= 0x0000ffff; + source2 = jbi_aca_out_buffer; + } +#endif + count = (unsigned int) long_count; + + for (i = 0; i < count; ++i) + { + if (mask[mask_index >> 3] & (1 << (mask_index & 7))) + { + a = source1[index1 >> 3] & (1 << (index1 & 7)) + ? 1 : 0; + b = source2[index2 >> 3] & (1 << (index2 & 7)) + ? 1 : 0; + + if (a != b) long_temp = 0L; /* failure */ + } + ++index1; + ++index2; + ++mask_index; + } + } + + stack[stack_ptr++] = long_temp; + } + break; + + case 0xC1: /* VSC */ + /* + * VECTOR with capture + * ...argument 0 is dir data variable ID + * ...argument 1 is scan data variable ID + * ...argument 2 is capture variable ID + * ...stack 0 is capture index + * ...stack 1 is scan data index + * ...stack 2 is dir data index + * ...stack 3 is count + */ + bad_opcode = 1; + break; + + default: + /* + * Unrecognized opcode -- ERROR! + */ + bad_opcode = 1; + break; + } + + if (bad_opcode) + { + status = JBIC_ILLEGAL_OPCODE; + } + + if ((stack_ptr < 0) || (stack_ptr >= JBI_STACK_SIZE)) + { + status = JBIC_STACK_OVERFLOW; + } + + if (status != JBIC_SUCCESS) + { + done = 1; + *error_address = (long) (opcode_address - code_section); + } + } + jbi_dbg(DEBUG_DETAIL, "debug_cnt(total): 0x%lx\n", debug_cnt); + + jbi_dbg(DEBUG_NOISY, "jbi_free_jtag_padding_buffers\n"); + jbi_free_jtag_padding_buffers(reset_jtag); + + /* + * Free all dynamically allocated arrays + */ + jbi_dbg(DEBUG_NOISY, "jbi_free_attributes\n"); + if ((attributes != NULL) && (variables != NULL)) + { + for (i = 0; i < (unsigned int) symbol_count; ++i) + { + if ((attributes[i] & 0x80) && (variables[i] != (addr_t) NULL) + && (variables[i] != (addr_t) 1)) + { + jbi_free((void *) variables[i]); + } + } + } + + if (variables != NULL) jbi_free(variables); + + if (variable_size != NULL) jbi_free(variable_size); + + if (attributes != NULL) jbi_free(attributes); + + if (proc_attributes != NULL) jbi_free(proc_attributes); + + jbi_dbg(DEBUG_NOISY, "return status %d\n", status); + kfree(message_buffer); + return (status); +} + +/****************************************************************************/ +/* */ + +JBI_RETURN_TYPE jbi_get_note +( + PROGRAM_PTR program, + long program_size, + long *offset, + char *key, + char *value, + int length +) + +/* */ +/* Description: Gets key and value of NOTE fields in the JBC file. */ +/* Can be called in two modes: if offset pointer is NULL, */ +/* then the function searches for note fields which match */ +/* the key string provided. If offset is not NULL, then */ +/* the function finds the next note field of any key, */ +/* starting at the offset specified by the offset pointer. */ +/* */ +/* Returns: JBIC_SUCCESS for success, else appropriate error code */ +/* */ +/****************************************************************************/ +{ + JBI_RETURN_TYPE status = JBIC_UNEXPECTED_END; + unsigned long note_strings = 0L; + unsigned long note_table = 0L; + unsigned long note_count = 0L; + unsigned long first_word = 0L; + int version = 0; + int delta = 0; + char *key_ptr; + char *value_ptr; + int i; + +#if PORT==DOS + int count = 0; + int done = 0; + long long_index = 0; + char key_buffer[256]; + char value_buffer[256]; + + jbi_program = program; +#endif + + /* + * Read header information + */ + if (program_size > 52L) + { + first_word = GET_DWORD(0); + version = (int) (first_word & 1L); + delta = version * 8; + + note_strings = GET_DWORD(8 + delta); + note_table = GET_DWORD(12 + delta); + note_count = GET_DWORD(44 + (2 * delta)); + } + + if ((first_word != 0x4A414D00L) && (first_word != 0x4A414D01L)) + { + status = JBIC_IO_ERROR; + } + else if (note_count > 0L) + { + if (offset == NULL) + { + /* + * We will search for the first note with a specific key, and + * return only the value + */ + for (i = 0; (i < (int) note_count) && (status != JBIC_SUCCESS); ++i) + { +#if PORT==DOS + done = 0; + count = 0; + long_index = note_strings + GET_DWORD(note_table + (8 * i)); + while ((count < 255) && !done) + { + key_buffer[count] = GET_BYTE(long_index); + if (key_buffer[count] == '\0') done = 1; + ++long_index; + ++count; + } + key_buffer[255] = '\0'; + key_ptr = key_buffer; +#else + key_ptr = (char *) &program[note_strings + + GET_DWORD(note_table + (8 * i))]; +#endif + if ((key != NULL) && (jbi_stricmp(key, key_ptr) == 0)) + { + status = JBIC_SUCCESS; + +#if PORT==DOS + done = 0; + count = 0; + long_index = note_strings + GET_DWORD(note_table + (8 * i) + 4); + while ((count < 255) && !done) + { + value_buffer[count] = GET_BYTE(long_index); + if (value_buffer[count] == '\0') done = 1; + ++long_index; + ++count; + } + value_buffer[255] = '\0'; + value_ptr = value_buffer; +#else + value_ptr = (char *) &program[note_strings + + GET_DWORD(note_table + (8 * i) + 4)]; +#endif + + if (value != NULL) + { + jbi_strncpy(value, value_ptr, length); + } + } + } + } + else + { + /* + * We will search for the next note, regardless of the key, and + * return both the value and the key + */ + + i = (int) *offset; + + if ((i >= 0) && (i < (int) note_count)) + { + status = JBIC_SUCCESS; + + if (key != NULL) + { +#if PORT==DOS + done = 0; + count = 0; + long_index = note_strings + + GET_DWORD(note_table + (8 * i)); + + while ((count < length) && !done) + { + key[count] = GET_BYTE(long_index); + if (key[count] == '\0') done = 1; + ++long_index; + ++count; + } +#else + jbi_strncpy(key, (char *) &program[note_strings + + GET_DWORD(note_table + (8 * i))], length); +#endif + } + + if (value != NULL) + { +#if PORT==DOS + done = 0; + count = 0; + long_index = note_strings + + GET_DWORD(note_table + (8 * i) + 4); + + while ((count < length) && !done) + { + value[count] = GET_BYTE(long_index); + if (value[count] == '\0') done = 1; + ++long_index; + ++count; + } +#else + jbi_strncpy(value, (char *) &program[note_strings + + GET_DWORD(note_table + (8 * i) + 4)], length); +#endif + } + + *offset = i + 1; + } + } + } + + return (status); +} + +/****************************************************************************/ +/* */ + +JBI_RETURN_TYPE jbi_check_crc +( + PROGRAM_PTR program, + long program_size, + unsigned short *expected_crc, + unsigned short *actual_crc +) + +/* */ +/* Description: This function reads the entire input file and computes */ +/* the CRC of everything up to the CRC field. */ +/* */ +/* Returns: JBIC_SUCCESS for success, JBIC_CRC_ERROR for failure */ +/* */ +/****************************************************************************/ +{ + JBI_RETURN_TYPE status = JBIC_SUCCESS; + unsigned short local_expected, local_actual, shift_reg = 0xffff; + int bit, feedback; + unsigned char databyte; + unsigned long i; + unsigned long crc_section = 0L; + unsigned long first_word = 0L; + int version = 0; + int delta = 0; + +#if PORT==DOS + jbi_program = program; +#endif + + if (program_size > 52L) + { + first_word = GET_DWORD(0); + version = (int) (first_word & 1L); + delta = version * 8; + + crc_section = GET_DWORD(32 + delta); + } + + if ((first_word != 0x4A414D00L) && (first_word != 0x4A414D01L)) + { + status = JBIC_IO_ERROR; + } + + if (crc_section >= (unsigned long) program_size) + { + status = JBIC_IO_ERROR; + } + + if (status == JBIC_SUCCESS) + { + local_expected = (unsigned short) GET_WORD(crc_section); + if (expected_crc != NULL) *expected_crc = local_expected; + + for (i = 0; i < crc_section; ++i) + { + databyte = GET_BYTE(i); + for (bit = 0; bit < 8; bit++) /* compute for each bit */ + { + feedback = (databyte ^ shift_reg) & 0x01; + shift_reg >>= 1; /* shift the shift register */ + if (feedback) shift_reg ^= 0x8408; /* invert selected bits */ + databyte >>= 1; /* get the next bit of input_byte */ + } + } + + local_actual = (unsigned short) ~shift_reg; + if (actual_crc != NULL) *actual_crc = local_actual; + + if (local_expected != local_actual) + { + status = JBIC_CRC_ERROR; + } + } + + return (status); +} + +JBI_RETURN_TYPE jbi_get_file_info +( + PROGRAM_PTR program, + long program_size, + int *format_version, + int *action_count, + int *procedure_count +) +{ + JBI_RETURN_TYPE status = JBIC_IO_ERROR; + unsigned long first_word = 0; + int version = 0; + +#if PORT==DOS + jbi_program = program; +#endif + + /* + * Read header information + */ + if (program_size > 52L) + { + first_word = GET_DWORD(0); + + if ((first_word == 0x4A414D00L) || (first_word == 0x4A414D01L)) + { + status = JBIC_SUCCESS; + + version = (int) (first_word & 1L); + *format_version = version + 1; + + if (version > 0) + { + *action_count = (int) GET_DWORD(48); + *procedure_count = (int) GET_DWORD(52); + } + } + + } + + return (status); +} + +JBI_RETURN_TYPE jbi_get_action_info +( + PROGRAM_PTR program, + long program_size, + int index, + char **name, + char **description, + JBI_PROCINFO **procedure_list +) +{ + JBI_RETURN_TYPE status = JBIC_IO_ERROR; + JBI_PROCINFO *procptr = NULL; + JBI_PROCINFO *tmpptr = NULL; + unsigned long first_word = 0L; + unsigned long action_table = 0L; + unsigned long proc_table = 0L; + unsigned long string_table = 0L; + unsigned long note_strings = 0L; + unsigned long action_count = 0L; + unsigned long proc_count = 0L; + unsigned long act_name_id = 0L; + unsigned long act_desc_id = 0L; + unsigned long act_proc_id = 0L; + unsigned long act_proc_name = 0L; + unsigned char act_proc_attribute = 0; + +#if PORT==DOS + int i, length; + jbi_program = program; +#endif + + /* + * Read header information + */ + if (program_size > 52L) + { + first_word = GET_DWORD(0); + + if (first_word == 0x4A414D01L) + { + action_table = GET_DWORD(4); + proc_table = GET_DWORD(8); + string_table = GET_DWORD(12); + note_strings = GET_DWORD(16); + action_count = GET_DWORD(48); + proc_count = GET_DWORD(52); + + if (index < (int) action_count) + { + act_name_id = GET_DWORD(action_table + (12 * index)); + act_desc_id = GET_DWORD(action_table + (12 * index) + 4); + act_proc_id = GET_DWORD(action_table + (12 * index) + 8); + +#if PORT==DOS + length = 0; + while (GET_BYTE(string_table + act_name_id + length) != 0) ++length; + *name = jbi_malloc(length + 1); + if (*name == NULL) + { + status = JBIC_OUT_OF_MEMORY; + } + else + { + for (i = 0; i < length; ++i) + { + (*name)[i] = GET_BYTE(string_table + act_name_id + i); + } + (*name)[length] = '\0'; + } +#else + *name = (char *) &program[string_table + act_name_id]; +#endif + + if (act_desc_id < (note_strings - string_table)) + { +#if PORT==DOS + length = 0; + while (GET_BYTE(string_table + act_desc_id + length) != 0) ++length; + *description = jbi_malloc(length + 1); + if (*description == NULL) + { + status = JBIC_OUT_OF_MEMORY; + } + else + { + for (i = 0; i < length; ++i) + { + (*description)[i] = GET_BYTE(string_table + act_desc_id + i); + } + (*description)[length] = '\0'; + } +#else + *description = (char *) &program[string_table + act_desc_id]; +#endif + } + + do + { + act_proc_name = GET_DWORD(proc_table + (13 * act_proc_id)); + act_proc_attribute = (unsigned char) + (GET_BYTE(proc_table + (13 * act_proc_id) + 8) & 0x03); + + procptr = (JBI_PROCINFO *) jbi_malloc(sizeof(JBI_PROCINFO)); + + if (procptr == NULL) + { + status = JBIC_OUT_OF_MEMORY; + } + else + { +#if PORT==DOS + length = 0; + while (GET_BYTE(string_table + act_proc_name + length) != 0) ++length; + procptr->name = jbi_malloc(length + 1); + if (procptr->name == NULL) + { + status = JBIC_OUT_OF_MEMORY; + } + else + { + for (i = 0; i < length; ++i) + { + procptr->name[i] = + GET_BYTE(string_table + act_proc_name + i); + } + procptr->name[length] = '\0'; + } +#else + procptr->name = (char *) + &program[string_table + act_proc_name]; +#endif + procptr->attributes = act_proc_attribute; + procptr->next = NULL; + + /* add record to end of linked list */ + if (*procedure_list == NULL) + { + *procedure_list = procptr; + } + else + { + tmpptr = *procedure_list; + while (tmpptr->next != NULL) tmpptr = tmpptr->next; + tmpptr->next = procptr; + } + } + + act_proc_id = + GET_DWORD(proc_table + (13 * act_proc_id) + 4); + } + while ((act_proc_id != 0) && (act_proc_id < proc_count)); + } + } + + } + + return (status); +} diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/jbiport.h b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/jbiport.h new file mode 100644 index 000000000000..28669dc81ff6 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/jbiport.h @@ -0,0 +1,45 @@ +/****************************************************************************/ +/* */ +/* Module: jbiport.h */ +/* */ +/* Copyright (C) Altera Corporation 2000-2001 */ +/* */ +/* Description: Defines porting macros */ +/* */ +/****************************************************************************/ + +#ifndef INC_JBIPORT_H +#define INC_JBIPORT_H + +/* +* PORT defines the target platform: DOS, WINDOWS, UNIX, or EMBEDDED +* +* PORT = DOS means a 16-bit DOS console-mode application +* +* PORT = WINDOWS means a 32-bit WIN32 console-mode application for +* Windows 95, 98, 2000, ME or NT. On NT this will use the +* DeviceIoControl() API to access the Parallel Port. +* +* PORT = UNIX means any UNIX system. BitBlaster access is support via +* the standard ANSI system calls open(), read(), write(). +* The ByteBlaster is not supported. +* +* PORT = EMBEDDED means all DOS, WINDOWS, and UNIX code is excluded. +* Remaining code supports 16 and 32-bit compilers. +* Additional porting steps may be necessary. See readme +* file for more details. +*/ + +#define DOS 2 +#define WINDOWS 3 +#define UNIX 4 +#define EMBEDDED 5 + +#define PORT EMBEDDED + +#ifndef PORT +/* change this line to build a different port */ +#define PORT WINDOWS +#endif + +#endif /* INC_JBIPORT_H */ diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/jbistub.c b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/jbistub.c new file mode 100644 index 000000000000..396c92caca2b --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/jbistub.c @@ -0,0 +1,2518 @@ +/****************************************************************************/ +/* */ +/* Module: jbistub.c */ +/* */ +/* Copyright (C) Altera Corporation 1997-2001 */ +/* */ +/* Description: Jam STAPL ByteCode Player main source file */ +/* */ +/* Supports Altera ByteBlaster hardware download cable */ +/* on Windows 95 and Windows NT operating systems. */ +/* (A device driver is required for Windows NT.) */ +/* */ +/* Also supports BitBlaster hardware download cable on */ +/* Windows 95, Windows NT, and UNIX platforms. */ +/* */ +/* Revisions: 1.1 fixed control port initialization for ByteBlaster */ +/* 2.0 added support for STAPL bytecode format, added code */ +/* to get printer port address from Windows registry */ +/* 2.1 improved messages, fixed delay-calibration bug in */ +/* 16-bit DOS port, added support for "alternative */ +/* cable X", added option to control whether to reset */ +/* the TAP after execution, moved porting macros into */ +/* jbiport.h */ +/* 2.2 added support for static memory */ +/* fixed /W4 warnings */ +/* */ +/****************************************************************************/ + +#ifndef NO_ALTERA_STDIO +#define NO_ALTERA_STDIO +#endif + +#if 0 +#if ( _MSC_VER >= 800 ) +#pragma warning(disable:4115) +#pragma warning(disable:4201) +#pragma warning(disable:4214) +#pragma warning(disable:4514) +#endif +#endif + +#include "jbiport.h" + +#if PORT == WINDOWS +#include +#else +typedef int BOOL; +typedef unsigned char BYTE; +typedef unsigned short WORD; +#if PORT == EMBEDDED +typedef unsigned int DWORD; +#else +typedef unsigned long DWORD; +#endif +#define TRUE 1 +#define FALSE 0 +#endif + +#if PORT != EMBEDDED +#include +#include +#include +#include +#include +#include +#endif + +#include + +#include "jbiexprt.h" +#include "jbistub.h" + +#if defined(USE_STATIC_MEMORY) + #define N_STATIC_MEMORY_KBYTES ((unsigned int) USE_STATIC_MEMORY) + #define N_STATIC_MEMORY_BYTES (N_STATIC_MEMORY_KBYTES * 1024) + #define POINTER_ALIGNMENT sizeof(DWORD) +#else /* USE_STATIC_MEMORY */ + /* #include */ + #define POINTER_ALIGNMENT sizeof(BYTE) +#endif /* USE_STATIC_MEMORY */ + +#if PORT != EMBEDDED +#include +#include +#include +#include +#include +#endif + +#if PORT == DOS +#include +#endif + +int jbi_debug_level = DEBUG_NONE; +static long jbi_delay_us = 0, jbi_delay_count = 0, jbi_peak_us = 0; + +void __jbi_jtag_udelay(unsigned long us) +{ + udelay(us); +} +void jbi_jtag_udelay(unsigned long us) __attribute__((weak, alias("__jbi_jtag_udelay"))); + +#if PORT == WINDOWS +#define PGDC_IOCTL_GET_DEVICE_INFO_PP 0x00166A00L +#define PGDC_IOCTL_READ_PORT_PP 0x00166A04L +#define PGDC_IOCTL_WRITE_PORT_PP 0x0016AA08L +#define PGDC_IOCTL_PROCESS_LIST_PP 0x0016AA1CL +#define PGDC_READ_INFO 0x0a80 +#define PGDC_READ_PORT 0x0a81 +#define PGDC_WRITE_PORT 0x0a82 +#define PGDC_PROCESS_LIST 0x0a87 +#define PGDC_HDLC_NTDRIVER_VERSION 2 +#define PORT_IO_BUFFER_SIZE 256 +#endif + +#if PORT == WINDOWS +#ifdef __BORLANDC__ +/* create dummy inp() and outp() functions for Borland 32-bit compile */ +WORD inp(WORD address) { address = address; return(0); } +void outp(WORD address, WORD data) { address = address; data = data; } +#else +#pragma intrinsic (inp, outp) +#endif +#endif + +/* +* For Borland C compiler (16-bit), set the stack size +*/ +#if PORT == DOS +#ifdef __BORLANDC__ +extern unsigned int _stklen = 50000; +#endif +#endif + +/************************************************************************ +* +* Global variables +*/ + +/* file buffer for Jam STAPL ByteCode input file */ +#if PORT == DOS +unsigned char **file_buffer = NULL; +#else +unsigned char *file_buffer = NULL; +#endif +long file_pointer = 0L; +long file_length = 0L; + +/* delay count for one millisecond delay */ +long one_ms_delay = 0L; + +/* serial port interface available on all platforms */ +BOOL jtag_hardware_initialized = FALSE; +char *serial_port_name = NULL; +BOOL specified_com_port = FALSE; +int com_port = -1; +void initialize_jtag_hardware(void); +void close_jtag_hardware(void); + +#if defined(USE_STATIC_MEMORY) + unsigned char static_memory_heap[N_STATIC_MEMORY_BYTES] = { 0 }; +#endif /* USE_STATIC_MEMORY */ + +#if defined(USE_STATIC_MEMORY) || defined(MEM_TRACKER) + unsigned int n_bytes_allocated = 0; +#endif /* USE_STATIC_MEMORY || MEM_TRACKER */ + +#if defined(MEM_TRACKER) + unsigned int peak_memory_usage = 0; + unsigned int peak_allocations = 0; + unsigned int n_allocations = 0; +#if defined(USE_STATIC_MEMORY) + unsigned int n_bytes_not_recovered = 0; +#endif /* USE_STATIC_MEMORY */ + const DWORD BEGIN_GUARD = 0x01234567; + const DWORD END_GUARD = 0x76543210; +#endif /* MEM_TRACKER */ + +#if PORT == WINDOWS || PORT == DOS +/* parallel port interface available on PC only */ +BOOL specified_lpt_port = FALSE; +BOOL specified_lpt_addr = FALSE; +int lpt_port = 1; +int initial_lpt_ctrl = 0; +WORD lpt_addr = 0x3bc; +WORD lpt_addr_table[3] = { 0x3bc, 0x378, 0x278 }; +BOOL alternative_cable_l = FALSE; +BOOL alternative_cable_x = FALSE; +void write_byteblaster(int port, int data); +int read_byteblaster(int port); +#endif + +#if PORT==WINDOWS +#ifndef __BORLANDC__ +WORD lpt_addresses_from_registry[4] = { 0 }; +#endif +#endif + +#if PORT == WINDOWS +/* variables to manage cached I/O under Windows NT */ +BOOL windows_nt = FALSE; +int port_io_count = 0; +HANDLE nt_device_handle = INVALID_HANDLE_VALUE; +struct PORT_IO_LIST_STRUCT +{ + USHORT command; + USHORT data; +} port_io_buffer[PORT_IO_BUFFER_SIZE]; +extern void flush_ports(void); +BOOL initialize_nt_driver(void); +#endif + +/* function prototypes to allow forward reference */ +extern void delay_loop(long count); + +/* +* This structure stores information about each available vector signal +*/ +struct VECTOR_LIST_STRUCT +{ + char *signal_name; + int hardware_bit; + int vector_index; +}; + +struct VECTOR_LIST_STRUCT vector_list[] = +{ + /* add a record here for each vector signal */ + { "", 0, -1 } +}; + +#define VECTOR_SIGNAL_COUNT ((int)(sizeof(vector_list)/sizeof(vector_list[0]))) + +BOOL verbose = FALSE; + +/************************************************************************ +* +* Customized interface functions for Jam STAPL ByteCode Player I/O: +* +* jbi_jtag_io() +* jbi_message() +* jbi_delay() +*/ + +int jbi_jtag_io(int tms, int tdi, int read_tdo) +{ +#if PORT == WINDOWS || PORT == DOS + int data = 0; +#endif + int tdo = 0; + int i = 0; + int result = 0; + char ch_data = 0; + + if (!jtag_hardware_initialized) + { + initialize_jtag_hardware(); + jtag_hardware_initialized = TRUE; + } + + if (specified_com_port) + { + ch_data = (char) + ((tdi ? 0x01 : 0) | (tms ? 0x02 : 0) | 0x60); + + write(com_port, &ch_data, 1); + + if (read_tdo) + { + ch_data = 0x7e; + write(com_port, &ch_data, 1); + for (i = 0; (i < 100) && (result != 1); ++i) + { + result = read(com_port, &ch_data, 1); + } + if (result == 1) + { + tdo = ch_data & 0x01; + } + else + { + fprintf(stderr, "Error: BitBlaster not responding\n"); + } + } + + ch_data = (char) + ((tdi ? 0x01 : 0) | (tms ? 0x02 : 0) | 0x64); + + write(com_port, &ch_data, 1); + } + else + { +#if PORT == WINDOWS || PORT == DOS + data = (alternative_cable_l ? ((tdi ? 0x01 : 0) | (tms ? 0x04 : 0)) : + (alternative_cable_x ? ((tdi ? 0x01 : 0) | (tms ? 0x04 : 0) | 0x10) : + ((tdi ? 0x40 : 0) | (tms ? 0x02 : 0)))); + + write_byteblaster(0, data); + + if (read_tdo) + { + tdo = read_byteblaster(1); + tdo = (alternative_cable_l ? ((tdo & 0x40) ? 1 : 0) : + (alternative_cable_x ? ((tdo & 0x10) ? 1 : 0) : + ((tdo & 0x80) ? 0 : 1))); + } + + write_byteblaster(0, data | (alternative_cable_l ? 0x02 : (alternative_cable_x ? 0x02: 0x01))); + + write_byteblaster(0, data); +#elif PORT == EMBEDDED + /* Output variables TDI, TMS to the corresponding pin; As read_tdo, return the corresponding pin to the variable tdo */ + tdo = jbi_jtag_io_(tms, tdi, read_tdo); +#else + /* parallel port interface not available */ + tdo = 0; +#endif + } + + return (tdo); +} + +void jbi_message(char *message_text) +{ + puts(message_text); + puts("\n"); + fflush(stdout); +} + +void jbi_export_integer(char *key, long value) +{ + if (verbose) + { + printf("Export: key = \"%s\", value = %ld\n", key, value); + fflush(stdout); + } +} + +#define HEX_LINE_CHARS 72 +#define HEX_LINE_BITS (HEX_LINE_CHARS * 4) + +char conv_to_hex(unsigned long value) +{ + char c; + + if (value > 9) + { + c = (char) (value + ('A' - 10)); + } + else + { + c = (char) (value + '0'); + } + + return (c); +} + +void jbi_export_boolean_array(char *key, unsigned char *data, long count) +{ + char string[HEX_LINE_CHARS + 1]; + long i, offset; + unsigned long size, line, lines, linebits, value, j, k; + + if (verbose) + { + if (count > HEX_LINE_BITS) + { + printf("Export: key = \"%s\", %ld bits, value = HEX\n", key, count); + lines = (count + (HEX_LINE_BITS - 1)) / HEX_LINE_BITS; + + for (line = 0; line < lines; ++line) + { + if (line < (lines - 1)) + { + linebits = HEX_LINE_BITS; + size = HEX_LINE_CHARS; + offset = count - ((line + 1) * HEX_LINE_BITS); + } + else + { + linebits = count - ((lines - 1) * HEX_LINE_BITS); + size = (linebits + 3) / 4; + offset = 0L; + } + + string[size] = '\0'; + j = size - 1; + value = 0; + + for (k = 0; k < linebits; ++k) + { + i = k + offset; + if (data[i >> 3] & (1 << (i & 7))) value |= (1 << (i & 3)); + if ((i & 3) == 3) + { + string[j] = conv_to_hex(value); + value = 0; + --j; + } + } + if ((k & 3) > 0) string[j] = conv_to_hex(value); + + printf("%s\n", string); + } + + fflush(stdout); + } + else + { + size = (count + 3) / 4; + string[size] = '\0'; + j = size - 1; + value = 0; + + for (i = 0; i < count; ++i) + { + if (data[i >> 3] & (1 << (i & 7))) value |= (1 << (i & 3)); + if ((i & 3) == 3) + { + string[j] = conv_to_hex(value); + value = 0; + --j; + } + } + if ((i & 3) > 0) string[j] = conv_to_hex(value); + + printf("Export: key = \"%s\", %ld bits, value = HEX %s\n", + key, count, string); + fflush(stdout); + } + } +} + +void jbi_delay(long microseconds) +{ + if (jbi_peak_us < microseconds) { + jbi_peak_us = microseconds; + } + jbi_delay_us += microseconds; + jbi_delay_count++; + +#if PORT == WINDOWS + /* if Windows NT, flush I/O cache buffer before delay loop */ + if (windows_nt && (port_io_count > 0)) flush_ports(); +#endif + +#if PORT == EMBEDDED + udelay(microseconds); +#else + delay_loop(microseconds * + ((one_ms_delay / 1000L) + ((one_ms_delay % 1000L) ? 1 : 0))); +#endif +} + +int jbi_vector_map +( + int signal_count, + char **signals +) +{ + int signal, vector, ch_index, diff; + int matched_count = 0; + char l, r; + + for (vector = 0; (vector < VECTOR_SIGNAL_COUNT); ++vector) + { + vector_list[vector].vector_index = -1; + } + + for (signal = 0; signal < signal_count; ++signal) + { + diff = 1; + for (vector = 0; (diff != 0) && (vector < VECTOR_SIGNAL_COUNT); + ++vector) + { + if (vector_list[vector].vector_index == -1) + { + ch_index = 0; + do + { + l = signals[signal][ch_index]; + r = vector_list[vector].signal_name[ch_index]; + diff = (((l >= 'a') && (l <= 'z')) ? (l - ('a' - 'A')) : l) + - (((r >= 'a') && (r <= 'z')) ? (r - ('a' - 'A')) : r); + ++ch_index; + } + while ((diff == 0) && (l != '\0') && (r != '\0')); + + if (diff == 0) + { + vector_list[vector].vector_index = signal; + ++matched_count; + } + } + } + } + + return (matched_count); +} + +int jbi_vector_io +( + int signal_count, + long *dir_vect, + long *data_vect, + long *capture_vect +) +{ + int signal, vector, bit; + int matched_count = 0; + int data = 0; + int mask = 0; + int dir = 0; + int i = 0; + int result = 0; + char ch_data = 0; + + if (!jtag_hardware_initialized) + { + initialize_jtag_hardware(); + jtag_hardware_initialized = TRUE; + } + + /* + * Collect information about output signals + */ + for (vector = 0; vector < VECTOR_SIGNAL_COUNT; ++vector) + { + signal = vector_list[vector].vector_index; + + if ((signal >= 0) && (signal < signal_count)) + { + bit = (1 << vector_list[vector].hardware_bit); + + mask |= bit; + if (data_vect[signal >> 5] & (1L << (signal & 0x1f))) data |= bit; + if (dir_vect[signal >> 5] & (1L << (signal & 0x1f))) dir |= bit; + + ++matched_count; + } + } + + /* + * Write outputs to hardware interface, if any + */ + if (dir != 0) + { + if (specified_com_port) + { + ch_data = (char) (((data >> 6) & 0x01) | (data & 0x02) | + ((data << 2) & 0x04) | ((data << 3) & 0x08) | 0x60); + write(com_port, &ch_data, 1); + } + else + { +#if PORT == WINDOWS || PORT == DOS + + write_byteblaster(0, data); + +#endif + } + } + + /* + * Read the input signals and save information in capture_vect[] + */ + if ((dir != mask) && (capture_vect != NULL)) + { + if (specified_com_port) + { + ch_data = 0x7e; + write(com_port, &ch_data, 1); + for (i = 0; (i < 100) && (result != 1); ++i) + { + result = read(com_port, &ch_data, 1); + } + if (result == 1) + { + data = ((ch_data << 7) & 0x80) | ((ch_data << 3) & 0x10); + } + else + { + fprintf(stderr, "Error: BitBlaster not responding\n"); + } + } + else + { +#if PORT == WINDOWS || PORT == DOS + + data = read_byteblaster(1) ^ 0x80; /* parallel port inverts bit 7 */ + +#endif + } + + for (vector = 0; vector < VECTOR_SIGNAL_COUNT; ++vector) + { + signal = vector_list[vector].vector_index; + + if ((signal >= 0) && (signal < signal_count)) + { + bit = (1 << vector_list[vector].hardware_bit); + + if ((dir & bit) == 0) /* if it is an input signal... */ + { + if (data & bit) + { + capture_vect[signal >> 5] |= (1L << (signal & 0x1f)); + } + else + { + capture_vect[signal >> 5] &= ~(unsigned long) + (1L << (signal & 0x1f)); + } + } + } + } + } + + return (matched_count); +} + +void *jbi_malloc(unsigned int size) +{ + unsigned int n_bytes_to_allocate = +#if defined(USE_STATIC_MEMORY) || defined(MEM_TRACKER) + sizeof(unsigned int) + +#endif /* USE_STATIC_MEMORY || MEM_TRACKER */ +#if defined(MEM_TRACKER) + (2 * sizeof(DWORD)) + +#endif /* MEM_TRACKER */ + (POINTER_ALIGNMENT * ((size + POINTER_ALIGNMENT - 1) / POINTER_ALIGNMENT)); + + unsigned char *ptr = 0; + +#if defined(MEM_TRACKER) + if ((n_bytes_allocated + n_bytes_to_allocate) > peak_memory_usage) + { + peak_memory_usage = n_bytes_allocated + n_bytes_to_allocate; + } + if ((n_allocations + 1) > peak_allocations) + { + peak_allocations = n_allocations + 1; + } +#endif /* MEM_TRACKER */ + +#if defined(USE_STATIC_MEMORY) + if ((n_bytes_allocated + n_bytes_to_allocate) <= N_STATIC_MEMORY_BYTES) + { + ptr = (&(static_memory_heap[n_bytes_allocated])); + } +#else /* USE_STATIC_MEMORY */ + ptr = (unsigned char *) malloc(n_bytes_to_allocate); +#endif /* USE_STATIC_MEMORY */ + +#if defined(USE_STATIC_MEMORY) || defined(MEM_TRACKER) + if (ptr != 0) + { + unsigned int i = 0; + +#if defined(MEM_TRACKER) + for (i = 0; i < sizeof(DWORD); ++i) + { + *ptr = (unsigned char) (BEGIN_GUARD >> (8 * i)); + ++ptr; + } +#endif /* MEM_TRACKER */ + + for (i = 0; i < sizeof(unsigned int); ++i) + { + *ptr = (unsigned char) (size >> (8 * i)); + ++ptr; + } + +#if defined(MEM_TRACKER) + for (i = 0; i < sizeof(DWORD); ++i) + { + *(ptr + size + i) = (unsigned char) (END_GUARD >> (8 * i)); + /* don't increment ptr */ + } + + ++n_allocations; +#endif /* MEM_TRACKER */ + + n_bytes_allocated += n_bytes_to_allocate; + } +#endif /* USE_STATIC_MEMORY || MEM_TRACKER */ + + jbi_dbg(DEBUG_MM, "malloc 0x%p(%d,%d)\n", ptr, size, n_bytes_to_allocate); + + return ptr; +} + +void jbi_free(void *ptr) +{ + jbi_dbg(DEBUG_MM, "free 0x%p\n", ptr); + + if + ( +#if defined(MEM_TRACKER) + (n_allocations > 0) && +#endif /* MEM_TRACKER */ + (ptr != 0) + ) + { + unsigned char *tmp_ptr = (unsigned char *) ptr; + +#if defined(USE_STATIC_MEMORY) || defined(MEM_TRACKER) + unsigned int n_bytes_to_free = 0; + unsigned int i = 0; + unsigned int size = 0; +#endif /* USE_STATIC_MEMORY || MEM_TRACKER */ +#if defined(MEM_TRACKER) + DWORD begin_guard = 0; + DWORD end_guard = 0; + + tmp_ptr -= sizeof(DWORD); +#endif /* MEM_TRACKER */ +#if defined(USE_STATIC_MEMORY) || defined(MEM_TRACKER) + tmp_ptr -= sizeof(unsigned int); +#endif /* USE_STATIC_MEMORY || MEM_TRACKER */ + ptr = tmp_ptr; + +#if defined(MEM_TRACKER) + for (i = 0; i < sizeof(DWORD); ++i) + { + begin_guard |= (((DWORD)(*tmp_ptr)) << (8 * i)); + ++tmp_ptr; + } +#endif /* MEM_TRACKER */ + +#if defined(USE_STATIC_MEMORY) || defined(MEM_TRACKER) + for (i = 0; i < sizeof(unsigned int); ++i) + { + size |= (((unsigned int)(*tmp_ptr)) << (8 * i)); + ++tmp_ptr; + } +#endif /* USE_STATIC_MEMORY || MEM_TRACKER */ + +#if defined(MEM_TRACKER) + tmp_ptr += size; + + for (i = 0; i < sizeof(DWORD); ++i) + { + end_guard |= (((DWORD)(*tmp_ptr)) << (8 * i)); + ++tmp_ptr; + } + + if ((begin_guard != BEGIN_GUARD) || (end_guard != END_GUARD)) + { + fprintf(stderr, "Error: memory corruption detected for allocation #%d... bad %s guard\n", + n_allocations, (begin_guard != BEGIN_GUARD) ? "begin" : "end"); + } + + --n_allocations; +#endif /* MEM_TRACKER */ + +#if defined(USE_STATIC_MEMORY) || defined(MEM_TRACKER) + n_bytes_to_free = +#if defined(MEM_TRACKER) + (2 * sizeof(DWORD)) + +#endif /* MEM_TRACKER */ + sizeof(unsigned int) + + (POINTER_ALIGNMENT * ((size + POINTER_ALIGNMENT - 1) / POINTER_ALIGNMENT)); +#endif /* USE_STATIC_MEMORY || MEM_TRACKER */ + +#if defined(USE_STATIC_MEMORY) + if ((((unsigned long) ptr - (unsigned long) static_memory_heap) + n_bytes_to_free) == (unsigned long) n_bytes_allocated) + { + n_bytes_allocated -= n_bytes_to_free; + } +#if defined(MEM_TRACKER) + else + { + n_bytes_not_recovered += n_bytes_to_free; + } +#endif /* MEM_TRACKER */ +#else /* USE_STATIC_MEMORY */ +#if defined(MEM_TRACKER) + n_bytes_allocated -= n_bytes_to_free; +#endif /* MEM_TRACKER */ + free(ptr); +#endif /* USE_STATIC_MEMORY */ + } +#if defined(MEM_TRACKER) + else + { + if (ptr != 0) + { + fprintf(stderr, "Error: attempt to free unallocated memory\n"); + } + } +#endif /* MEM_TRACKER */ +} + +#if PORT == WINDOWS || PORT == DOS +/************************************************************************ +* +* get_tick_count() -- Get system tick count in milliseconds +* +* for DOS, use BIOS function _bios_timeofday() +* for WINDOWS use GetTickCount() function +* for UNIX use clock() system function +*/ +DWORD get_tick_count(void) +{ + DWORD tick_count = 0L; + +#if PORT == WINDOWS + tick_count = GetTickCount(); +#elif PORT == DOS + _bios_timeofday(_TIME_GETCLOCK, (long *)&tick_count); + tick_count *= 55L; /* convert to milliseconds */ +#else + /* assume clock() function returns microseconds */ + tick_count = (DWORD) (clock() / 1000L); +#endif + + return (tick_count); +} +#endif + +#define DELAY_SAMPLES 10 +#define DELAY_CHECK_LOOPS 10000 + +void calibrate_delay(void) +{ +#if PORT == WINDOWS || PORT == DOS + int sample = 0; + int count = 0; + DWORD tick_count1 = 0L; + DWORD tick_count2 = 0L; +#endif + + one_ms_delay = 0L; + +#if PORT == WINDOWS || PORT == DOS + for (sample = 0; sample < DELAY_SAMPLES; ++sample) + { + count = 0; + tick_count1 = get_tick_count(); + while ((tick_count2 = get_tick_count()) == tick_count1) {}; + do { delay_loop(DELAY_CHECK_LOOPS); count++; } while + ((tick_count1 = get_tick_count()) == tick_count2); + one_ms_delay += ((DELAY_CHECK_LOOPS * (DWORD)count) / + (tick_count1 - tick_count2)); + } + + one_ms_delay /= DELAY_SAMPLES; +#else + /* This is system-dependent! Update this number for target system */ + one_ms_delay = 1000L; +#endif +} + +char *error_text[] = +{ +/* JBIC_SUCCESS 0 */ "success", +/* JBIC_OUT_OF_MEMORY 1 */ "out of memory", +/* JBIC_IO_ERROR 2 */ "file access error", +/* JAMC_SYNTAX_ERROR 3 */ "syntax error", +/* JBIC_UNEXPECTED_END 4 */ "unexpected end of file", +/* JBIC_UNDEFINED_SYMBOL 5 */ "undefined symbol", +/* JAMC_REDEFINED_SYMBOL 6 */ "redefined symbol", +/* JBIC_INTEGER_OVERFLOW 7 */ "integer overflow", +/* JBIC_DIVIDE_BY_ZERO 8 */ "divide by zero", +/* JBIC_CRC_ERROR 9 */ "CRC mismatch", +/* JBIC_INTERNAL_ERROR 10 */ "internal error", +/* JBIC_BOUNDS_ERROR 11 */ "bounds error", +/* JAMC_TYPE_MISMATCH 12 */ "type mismatch", +/* JAMC_ASSIGN_TO_CONST 13 */ "assignment to constant", +/* JAMC_NEXT_UNEXPECTED 14 */ "NEXT unexpected", +/* JAMC_POP_UNEXPECTED 15 */ "POP unexpected", +/* JAMC_RETURN_UNEXPECTED 16 */ "RETURN unexpected", +/* JAMC_ILLEGAL_SYMBOL 17 */ "illegal symbol name", +/* JBIC_VECTOR_MAP_FAILED 18 */ "vector signal name not found", +/* JBIC_USER_ABORT 19 */ "execution cancelled", +/* JBIC_STACK_OVERFLOW 20 */ "stack overflow", +/* JBIC_ILLEGAL_OPCODE 21 */ "illegal instruction code", +/* JAMC_PHASE_ERROR 22 */ "phase error", +/* JAMC_SCOPE_ERROR 23 */ "scope error", +/* JBIC_ACTION_NOT_FOUND 24 */ "action not found", +}; + +#define MAX_ERROR_CODE (int)(sizeof(error_text)/sizeof(error_text[0])) + +/************************************************************************/ + +#if 0 +int main(int argc, char **argv) +{ + BOOL help = FALSE; + BOOL error = FALSE; + char *filename = NULL; + long offset = 0L; + long error_address = 0L; + JBI_RETURN_TYPE crc_result = JBIC_SUCCESS; + JBI_RETURN_TYPE exec_result = JBIC_SUCCESS; + unsigned short expected_crc = 0; + unsigned short actual_crc = 0; + char key[33] = {0}; + char value[257] = {0}; + int exit_status = 0; + int arg = 0; + int exit_code = 0; + int format_version = 0; + time_t start_time = 0; + time_t end_time = 0; + int time_delta = 0; + char *workspace = NULL; + char *action = NULL; + char *init_list[10]; + int init_count = 0; + FILE *fp = NULL; + struct stat sbuf; + long workspace_size = 0; + char *exit_string = NULL; + int reset_jtag = 1; + int execute_program = 1; + int action_count = 0; + int procedure_count = 0; + int index = 0; + char *action_name = NULL; + char *description = NULL; + JBI_PROCINFO *procedure_list = NULL; + JBI_PROCINFO *procptr = NULL; + + verbose = FALSE; + + init_list[0] = NULL; + + /* print out the version string and copyright message */ + fprintf(stderr, "Jam STAPL ByteCode Player Version 2.2\nCopyright (C) 1998-2001 Altera Corporation\n\n"); + + for (arg = 1; arg < argc; arg++) + { +#if PORT == UNIX + if (argv[arg][0] == '-') +#else + if ((argv[arg][0] == '-') || (argv[arg][0] == '/')) +#endif + { + switch(toupper(argv[arg][1])) + { + case 'A': /* set action name */ + if (action == NULL) + { + action = &argv[arg][2]; + } + else + { + error = TRUE; + } + break; + +#if PORT == WINDOWS || PORT == DOS + case 'C': /* Use alternative ISP download cable */ + if(toupper(argv[arg][2]) == 'L') + alternative_cable_l = TRUE; + else if(toupper(argv[arg][2]) == 'X') + alternative_cable_x = TRUE; + break; +#endif + + case 'D': /* initialization list */ + if (argv[arg][2] == '"') + { + init_list[init_count] = &argv[arg][3]; + } + else + { + init_list[init_count] = &argv[arg][2]; + } + init_list[++init_count] = NULL; + break; + +#if PORT == WINDOWS || PORT == DOS + case 'P': /* set LPT port address */ + specified_lpt_port = TRUE; + if (sscanf(&argv[arg][2], "%d", &lpt_port) != 1) error = TRUE; + if ((lpt_port < 1) || (lpt_port > 3)) error = TRUE; + if (error) + { + if (sscanf(&argv[arg][2], "%x", &lpt_port) == 1) + { + if ((lpt_port == 0x3bc) || + (lpt_port == 0x378) || + (lpt_port == 0x278)) + { + error = FALSE; + specified_lpt_addr = TRUE; + lpt_addr = (WORD) lpt_port; + lpt_port = 1; + } + } + } + break; +#endif + + case 'R': /* don't reset the JTAG chain after use */ + reset_jtag = 0; + break; + + case 'S': /* set serial port address */ + serial_port_name = &argv[arg][2]; + specified_com_port = TRUE; + break; + + case 'M': /* set memory size */ + if (sscanf(&argv[arg][2], "%ld", &workspace_size) != 1) + error = TRUE; + if (workspace_size == 0) error = TRUE; + break; + + case 'H': /* help */ + help = TRUE; + break; + + case 'V': /* verbose */ + verbose = TRUE; + break; + + case 'I': /* show info only, do not execute */ + verbose = TRUE; + execute_program = 0; + break; + + default: + error = TRUE; + break; + } + } + else + { + /* it's a filename */ + if (filename == NULL) + { + filename = argv[arg]; + } + else + { + /* error -- we already found a filename */ + error = TRUE; + } + } + + if (error) + { + fprintf(stderr, "Illegal argument: \"%s\"\n", argv[arg]); + help = TRUE; + error = FALSE; + } + } + +#if PORT == WINDOWS || PORT == DOS + if (specified_lpt_port && specified_com_port) + { + fprintf(stderr, "Error: -s and -p options may not be used together\n\n"); + help = TRUE; + } +#endif + + if (help || (filename == NULL)) + { + fprintf(stderr, "Usage: jbi [options] \n"); + fprintf(stderr, "\nAvailable options:\n"); + fprintf(stderr, " -h : show help message\n"); + fprintf(stderr, " -v : show verbose messages\n"); + fprintf(stderr, " -i : show file info only - does not execute any action\n"); + fprintf(stderr, " -a : specify an action name (Jam STAPL)\n"); + fprintf(stderr, " -d : initialize variable to specified value (Jam 1.1)\n"); + fprintf(stderr, " -d : enable optional procedure (Jam STAPL)\n"); + fprintf(stderr, " -d : disable recommended procedure (Jam STAPL)\n"); +#if PORT == WINDOWS || PORT == DOS + fprintf(stderr, " -p : parallel port number or address (for ByteBlaster)\n"); + fprintf(stderr, " -c : alternative download cable compatibility: -cl or -cx\n"); +#endif + fprintf(stderr, " -s : serial port name (for BitBlaster)\n"); + fprintf(stderr, " -r : don't reset JTAG TAP after use\n"); + exit_status = 1; + } + else if ((workspace_size > 0) && + ((workspace = (char *) jbi_malloc((size_t) workspace_size)) == NULL)) + { + fprintf(stderr, "Error: can't allocate memory (%d Kbytes)\n", + (int) (workspace_size / 1024L)); + exit_status = 1; + } + else if (access(filename, 0) != 0) + { + fprintf(stderr, "Error: can't access file \"%s\"\n", filename); + exit_status = 1; + } + else + { + /* get length of file */ + if (stat(filename, &sbuf) == 0) file_length = sbuf.st_size; + + if ((fp = fopen(filename, "rb")) == NULL) + { + fprintf(stderr, "Error: can't open file \"%s\"\n", filename); + exit_status = 1; + } + else + { + /* + * Read entire file into a buffer + */ +#if PORT == DOS + int pages = 1 + (int) (file_length >> 14L); + int page; + file_buffer = (unsigned char **) jbi_malloc( + (size_t) (pages * sizeof(char *))); + + for (page = 0; page < pages; ++page) + { + /* allocate enough 16K blocks to store the file */ + file_buffer[page] = (unsigned char *) jbi_malloc (0x4000); + if (file_buffer[page] == NULL) + { + /* flag error and break out of loop */ + file_buffer = NULL; + page = pages; + } + } +#else + file_buffer = (unsigned char *) jbi_malloc((size_t) file_length); +#endif + + if (file_buffer == NULL) + { + fprintf(stderr, "Error: can't allocate memory (%d Kbytes)\n", + (int) (file_length / 1024L)); + exit_status = 1; + } + else + { +#if PORT == DOS + int pages = 1 + (int) (file_length >> 14L); + int page; + size_t page_size = 0x4000; + for (page = 0; (page < pages) && (exit_status == 0); ++page) + { + if (page == (pages - 1)) + { + /* last page may not be full 16K bytes */ + page_size = (size_t) (file_length & 0x3fffL); + } + if (fread(file_buffer[page], 1, page_size, fp) != page_size) + { + fprintf(stderr, "Error reading file \"%s\"\n", filename); + exit_status = 1; + } + } +#else + if (fread(file_buffer, 1, (size_t) file_length, fp) != + (size_t) file_length) + { + fprintf(stderr, "Error reading file \"%s\"\n", filename); + exit_status = 1; + } +#endif + } + + fclose(fp); + } + + if (exit_status == 0) + { + /* + * Get Operating System type + */ +#if PORT == WINDOWS + windows_nt = !(GetVersion() & 0x80000000); +#endif + + /* + * Calibrate the delay loop function + */ + calibrate_delay(); + + /* + * Check CRC + */ + crc_result = jbi_check_crc(file_buffer, file_length, + &expected_crc, &actual_crc); + + if (verbose || (crc_result == JBIC_CRC_ERROR)) + { + switch (crc_result) + { + case JBIC_SUCCESS: + printf("CRC matched: CRC value = %04X\n", actual_crc); + break; + + case JBIC_CRC_ERROR: + printf("CRC mismatch: expected %04X, actual %04X\n", + expected_crc, actual_crc); + break; + + case JBIC_UNEXPECTED_END: + printf("Expected CRC not found, actual CRC value = %04X\n", + actual_crc); + break; + + case JBIC_IO_ERROR: + printf("Error: File format is not recognized.\n"); + exit(1); + break; + + default: + printf("CRC function returned error code %d\n", crc_result); + break; + } + } + + if (verbose) + { + /* + * Display file format version + */ + jbi_get_file_info(file_buffer, file_length, + &format_version, &action_count, &procedure_count); + + printf("File format is %s ByteCode format\n", + (format_version == 2) ? "Jam STAPL" : "pre-standardized Jam 1.1"); + + /* + * Dump out NOTE fields + */ + while (jbi_get_note(file_buffer, file_length, + &offset, key, value, 256) == 0) + { + printf("NOTE \"%s\" = \"%s\"\n", key, value); + } + + /* + * Dump the action table + */ + if ((format_version == 2) && (action_count > 0)) + { + printf("\nActions available in this file:\n"); + + for (index = 0; index < action_count; ++index) + { + jbi_get_action_info(file_buffer, file_length, + index, &action_name, &description, &procedure_list); + + if (description == NULL) + { + printf("%s\n", action_name); + } + else + { + printf("%s \"%s\"\n", action_name, description); + } + +#if PORT == DOS + if (action_name != NULL) jbi_free(action_name); + if (description != NULL) jbi_free(description); +#endif + + procptr = procedure_list; + while (procptr != NULL) + { + if (procptr->attributes != 0) + { + printf(" %s (%s)\n", procptr->name, + (procptr->attributes == 1) ? + "optional" : "recommended"); + } + +#if PORT == DOS + if (procptr->name != NULL) jbi_free(procptr->name); +#endif + + procedure_list = procptr->next; + jbi_free(procptr); + procptr = procedure_list; + } + } + + /* add a blank line before execution messages */ + if (execute_program) printf("\n"); + } + } + + if (execute_program) + { + /* + * Execute the Jam STAPL ByteCode program + */ + time(&start_time); + exec_result = jbi_execute(file_buffer, file_length, workspace, + workspace_size, action, init_list, reset_jtag, + &error_address, &exit_code, &format_version); + time(&end_time); + + if (exec_result == JBIC_SUCCESS) + { + if (format_version == 2) + { + switch (exit_code) + { + case 0: exit_string = "Success"; break; + case 1: exit_string = "Checking chain failure"; break; + case 2: exit_string = "Reading IDCODE failure"; break; + case 3: exit_string = "Reading USERCODE failure"; break; + case 4: exit_string = "Reading UESCODE failure"; break; + case 5: exit_string = "Entering ISP failure"; break; + case 6: exit_string = "Unrecognized device"; break; + case 7: exit_string = "Device revision is not supported"; break; + case 8: exit_string = "Erase failure"; break; + case 9: exit_string = "Device is not blank"; break; + case 10: exit_string = "Device programming failure"; break; + case 11: exit_string = "Device verify failure"; break; + case 12: exit_string = "Read failure"; break; + case 13: exit_string = "Calculating checksum failure"; break; + case 14: exit_string = "Setting security bit failure"; break; + case 15: exit_string = "Querying security bit failure"; break; + case 16: exit_string = "Exiting ISP failure"; break; + case 17: exit_string = "Performing system test failure"; break; + default: exit_string = "Unknown exit code"; break; + } + } + else + { + switch (exit_code) + { + case 0: exit_string = "Success"; break; + case 1: exit_string = "Illegal initialization values"; break; + case 2: exit_string = "Unrecognized device"; break; + case 3: exit_string = "Device revision is not supported"; break; + case 4: exit_string = "Device programming failure"; break; + case 5: exit_string = "Device is not blank"; break; + case 6: exit_string = "Device verify failure"; break; + case 7: exit_string = "SRAM configuration failure"; break; + default: exit_string = "Unknown exit code"; break; + } + } + + printf("Exit code = %d... %s\n", exit_code, exit_string); + } + else if ((format_version == 2) && + (exec_result == JBIC_ACTION_NOT_FOUND)) + { + if ((action == NULL) || (*action == '\0')) + { + printf("Error: no action specified for Jam STAPL file.\nProgram terminated.\n"); + } + else + { + printf("Error: action \"%s\" is not supported for this Jam STAPL file.\nProgram terminated.\n", action); + } + } + else if (exec_result < MAX_ERROR_CODE) + { + printf("Error at address %ld: %s.\nProgram terminated.\n", + error_address, error_text[exec_result]); + } + else + { + printf("Unknown error code %ld\n", exec_result); + } + + /* + * Print out elapsed time + */ + if (verbose) + { + time_delta = (int) (end_time - start_time); + printf("Elapsed time = %02u:%02u:%02u\n", + time_delta / 3600, /* hours */ + (time_delta % 3600) / 60, /* minutes */ + time_delta % 60); /* seconds */ + } + } + } + } + + if (jtag_hardware_initialized) close_jtag_hardware(); + + if (workspace != NULL) jbi_free(workspace); + if (file_buffer != NULL) jbi_free(file_buffer); + +#if defined(MEM_TRACKER) + if (verbose) + { +#if defined(USE_STATIC_MEMORY) + fprintf(stdout, "Memory Usage Info: static memory size = %ud (%dKB)\n", N_STATIC_MEMORY_BYTES, N_STATIC_MEMORY_KBYTES); +#endif /* USE_STATIC_MEMORY */ + fprintf(stdout, "Memory Usage Info: peak memory usage = %ud (%dKB)\n", peak_memory_usage, (peak_memory_usage + 1023) / 1024); + fprintf(stdout, "Memory Usage Info: peak allocations = %d\n", peak_allocations); +#if defined(USE_STATIC_MEMORY) + if ((n_bytes_allocated - n_bytes_not_recovered) != 0) + { + fprintf(stdout, "Memory Usage Info: bytes still allocated = %d (%dKB)\n", (n_bytes_allocated - n_bytes_not_recovered), ((n_bytes_allocated - n_bytes_not_recovered) + 1023) / 1024); + } +#else /* USE_STATIC_MEMORY */ + if (n_bytes_allocated != 0) + { + fprintf(stdout, "Memory Usage Info: bytes still allocated = %d (%dKB)\n", n_bytes_allocated, (n_bytes_allocated + 1023) / 1024); + } +#endif /* USE_STATIC_MEMORY */ + if (n_allocations != 0) + { + fprintf(stdout, "Memory Usage Info: allocations not freed = %d\n", n_allocations); + } + } +#endif /* MEM_TRACKER */ + + return (exit_status); +} +#endif + +#if PORT==WINDOWS +#ifndef __BORLANDC__ +/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * +* +* SEARCH_DYN_DATA +* +* Searches recursively in Windows 95/98 Registry for parallel port info +* under HKEY_DYN_DATA registry key. Called by search_local_machine(). +*/ +void search_dyn_data +( + char *dd_path, + char *hardware_key, + int lpt +) +{ + DWORD index; + DWORD size; + DWORD type; + LONG result; + HKEY key; + int length; + WORD address; + char buffer[1024]; + FILETIME last_write = {0}; + WORD *word_ptr; + int i; + + length = strlen(dd_path); + + if (RegOpenKeyEx( + HKEY_DYN_DATA, + dd_path, + 0L, + KEY_READ, + &key) + == ERROR_SUCCESS) + { + size = 1023; + + if (RegQueryValueEx( + key, + "HardWareKey", + NULL, + &type, + (unsigned char *) buffer, + &size) + == ERROR_SUCCESS) + { + if ((type == REG_SZ) && (stricmp(buffer, hardware_key) == 0)) + { + size = 1023; + + if (RegQueryValueEx( + key, + "Allocation", + NULL, + &type, + (unsigned char *) buffer, + &size) + == ERROR_SUCCESS) + { + /* + * By "inspection", I have found five cases: size 32, 48, + * 56, 60, and 80 bytes. The port address seems to be + * located at different offsets in the buffer for these + * five cases, as shown below. If a valid port address + * is not found, or the size is not one of these known + * sizes, then I search through the entire buffer and + * look for a value which is a valid port address. + */ + + word_ptr = (WORD *) buffer; + + if ((type == REG_BINARY) && (size == 32)) + { + address = word_ptr[10]; + } + else if ((type == REG_BINARY) && (size == 48)) + { + address = word_ptr[18]; + } + else if ((type == REG_BINARY) && (size == 56)) + { + address = word_ptr[22]; + } + else if ((type == REG_BINARY) && (size == 60)) + { + address = word_ptr[24]; + } + else if ((type == REG_BINARY) && (size == 80)) + { + address = word_ptr[24]; + } + else address = 0; + + /* if not found, search through entire buffer */ + i = 0; + while ((i < (int) (size / 2)) && + (address != 0x278) && + (address != 0x27C) && + (address != 0x378) && + (address != 0x37C) && + (address != 0x3B8) && + (address != 0x3BC)) + { + if ((word_ptr[i] == 0x278) || + (word_ptr[i] == 0x27C) || + (word_ptr[i] == 0x378) || + (word_ptr[i] == 0x37C) || + (word_ptr[i] == 0x3B8) || + (word_ptr[i] == 0x3BC)) + { + address = word_ptr[i]; + } + ++i; + } + + if ((address == 0x278) || + (address == 0x27C) || + (address == 0x378) || + (address == 0x37C) || + (address == 0x3B8) || + (address == 0x3BC)) + { + lpt_addresses_from_registry[lpt] = address; + } + } + } + } + + index = 0; + + do + { + size = 1023; + + result = RegEnumKeyEx( + key, + index++, + buffer, + &size, + NULL, + NULL, + NULL, + &last_write); + + if (result == ERROR_SUCCESS) + { + dd_path[length] = '\\'; + dd_path[length + 1] = '\0'; + strcpy(&dd_path[length + 1], buffer); + + search_dyn_data(dd_path, hardware_key, lpt); + + dd_path[length] = '\0'; + } + } + while (result == ERROR_SUCCESS); + + RegCloseKey(key); + } +} + +/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * +* +* SEARCH_LOCAL_MACHINE +* +* Searches recursively in Windows 95/98 Registry for parallel port info +* under HKEY_LOCAL_MACHINE\Enum. When parallel port is found, calls +* search_dyn_data() to get the port address. +*/ +void search_local_machine +( + char *lm_path, + char *dd_path +) +{ + DWORD index; + DWORD size; + DWORD type; + LONG result; + HKEY key; + int length; + char buffer[1024]; + FILETIME last_write = {0}; + + length = strlen(lm_path); + + if (RegOpenKeyEx( + HKEY_LOCAL_MACHINE, + lm_path, + 0L, + KEY_READ, + &key) + == ERROR_SUCCESS) + { + size = 1023; + + if (RegQueryValueEx( + key, + "PortName", + NULL, + &type, + (unsigned char *) buffer, + &size) + == ERROR_SUCCESS) + { + if ((type == REG_SZ) && + (size == 5) && + (buffer[0] == 'L') && + (buffer[1] == 'P') && + (buffer[2] == 'T') && + (buffer[3] >= '1') && + (buffer[3] <= '4') && + (buffer[4] == '\0')) + { + /* we found the entry in HKEY_LOCAL_MACHINE, now we need to */ + /* find the corresponding entry under HKEY_DYN_DATA. */ + /* add 5 to lm_path to skip over "Enum" and backslash */ + search_dyn_data(dd_path, &lm_path[5], (buffer[3] - '1')); + } + } + + index = 0; + + do + { + size = 1023; + + result = RegEnumKeyEx( + key, + index++, + buffer, + &size, + NULL, + NULL, + NULL, + &last_write); + + if (result == ERROR_SUCCESS) + { + lm_path[length] = '\\'; + lm_path[length + 1] = '\0'; + strcpy(&lm_path[length + 1], buffer); + + search_local_machine(lm_path, dd_path); + + lm_path[length] = '\0'; + } + } + while (result == ERROR_SUCCESS); + + RegCloseKey(key); + } +} + +/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * +* +* GET_LPT_ADDRESSES_FROM_REGISTRY +* +* Searches Win95/98 registry recursively to get I/O port addresses for +* parallel ports. +*/ +void get_lpt_addresses_from_registry() +{ + char lm_path[1024]; + char dd_path[1024]; + + strcpy(lm_path, "Enum"); + strcpy(dd_path, "Config Manager"); + search_local_machine(lm_path, dd_path); +} +#endif +#endif + +void initialize_jtag_hardware() +{ + if (specified_com_port) + { + com_port = open(serial_port_name, O_RDWR); + if (com_port == -1) + { + fprintf(stderr, "Error: can't open serial port \"%s\"\n", + serial_port_name); + } + else + { + int i = 0, result = 0; + char data = 0; + + data = 0x7e; + write(com_port, &data, 1); + + for (i = 0; (i < 100) && (result != 1); ++i) + { + result = read(com_port, &data, 1); + } + + if (result == 1) + { + data = 0x70; write(com_port, &data, 1); /* TDO echo off */ + data = 0x72; write(com_port, &data, 1); /* auto LEDs off */ + data = 0x74; write(com_port, &data, 1); /* ERROR LED off */ + data = 0x76; write(com_port, &data, 1); /* DONE LED off */ + data = 0x60; write(com_port, &data, 1); /* signals low */ + } + else + { + fprintf(stderr, "Error: BitBlaster is not responding on %s\n", + serial_port_name); + close(com_port); + com_port = -1; + } + } + } + else + { +#if PORT == WINDOWS || PORT == DOS + +#if PORT == WINDOWS + if (windows_nt) + { + initialize_nt_driver(); + } + else + { +#ifdef __BORLANDC__ + fprintf(stderr, "Error: parallel port access is not available\n"); +#else + if (!specified_lpt_addr) + { + get_lpt_addresses_from_registry(); + + lpt_addr = 0; + + if (specified_lpt_port) + { + lpt_addr = lpt_addresses_from_registry[lpt_port - 1]; + } + + if (lpt_addr == 0) + { + if (lpt_addresses_from_registry[3] != 0) + lpt_addr = lpt_addresses_from_registry[3]; + if (lpt_addresses_from_registry[2] != 0) + lpt_addr = lpt_addresses_from_registry[2]; + if (lpt_addresses_from_registry[1] != 0) + lpt_addr = lpt_addresses_from_registry[1]; + if (lpt_addresses_from_registry[0] != 0) + lpt_addr = lpt_addresses_from_registry[0]; + } + + if (lpt_addr == 0) + { + if (specified_lpt_port) + { + lpt_addr = lpt_addr_table[lpt_port - 1]; + } + else + { + lpt_addr = lpt_addr_table[0]; + } + } + } + initial_lpt_ctrl = windows_nt ? 0x0c : read_byteblaster(2); +#endif + } +#endif + +#if PORT == DOS + /* + * Read word at specific memory address to get the LPT port address + */ + WORD *bios_address = (WORD *) 0x00400008; + + if (!specified_lpt_addr) + { + lpt_addr = bios_address[lpt_port - 1]; + + if ((lpt_addr != 0x278) && + (lpt_addr != 0x27c) && + (lpt_addr != 0x378) && + (lpt_addr != 0x37c) && + (lpt_addr != 0x3b8) && + (lpt_addr != 0x3bc)) + { + lpt_addr = lpt_addr_table[lpt_port - 1]; + } + } + initial_lpt_ctrl = read_byteblaster(2); +#endif + + /* set AUTO-FEED low to enable ByteBlaster (value to port inverted) */ + /* set DIRECTION low for data output from parallel port */ + write_byteblaster(2, (initial_lpt_ctrl | 0x02) & 0xDF); +#endif + } +} + +void close_jtag_hardware() +{ + if (specified_com_port) + { + if (com_port != -1) close(com_port); + } + else + { +#if PORT == WINDOWS || PORT == DOS + /* set AUTO-FEED high to disable ByteBlaster */ + write_byteblaster(2, initial_lpt_ctrl & 0xfd); + +#if PORT == WINDOWS + if (windows_nt && (nt_device_handle != INVALID_HANDLE_VALUE)) + { + if (port_io_count > 0) flush_ports(); + + CloseHandle(nt_device_handle); + } +#endif +#endif + } +} + +#if PORT == WINDOWS +/**************************************************************************/ +/* */ + +BOOL initialize_nt_driver() + +/* */ +/* Uses CreateFile() to open a connection to the Windows NT device */ +/* driver. */ +/* */ +/**************************************************************************/ +{ + BOOL status = FALSE; + + ULONG buffer[1]; + ULONG returned_length = 0; + char nt_lpt_str[] = { '\\', '\\', '.', '\\', + 'A', 'L', 'T', 'L', 'P', 'T', '1', '\0' }; + + nt_lpt_str[10] = (char) ('1' + (lpt_port - 1)); + + nt_device_handle = CreateFile( + nt_lpt_str, + GENERIC_READ | GENERIC_WRITE, + 0, + NULL, + OPEN_EXISTING, + FILE_ATTRIBUTE_NORMAL, + NULL); + + if (nt_device_handle == INVALID_HANDLE_VALUE) + { + fprintf(stderr, + "I/O error: cannot open device %s\nCheck port number and device driver installation", + nt_lpt_str); + } + else + { + if (DeviceIoControl( + nt_device_handle, /* Handle to device */ + PGDC_IOCTL_GET_DEVICE_INFO_PP, /* IO Control code */ + (ULONG *)NULL, /* Buffer to driver. */ + 0, /* Length of buffer in bytes. */ + &buffer, /* Buffer from driver. */ + sizeof(ULONG), /* Length of buffer in bytes. */ + &returned_length, /* Bytes placed in data_buffer. */ + NULL)) /* Wait for operation to complete */ + { + if (returned_length == sizeof(ULONG)) + { + if (buffer[0] == PGDC_HDLC_NTDRIVER_VERSION) + { + status = TRUE; + } + else + { + fprintf(stderr, + "I/O error: device driver %s is not compatible\n(Driver version is %lu, expected version %lu.\n", + nt_lpt_str, + (unsigned long) buffer[0], + (unsigned long) PGDC_HDLC_NTDRIVER_VERSION); + } + } + else + { + fprintf(stderr, "I/O error: device driver %s is not compatible.\n", + nt_lpt_str); + } + } + + if (!status) + { + CloseHandle(nt_device_handle); + nt_device_handle = INVALID_HANDLE_VALUE; + } + } + + if (!status) + { + /* error message already given */ + exit(1); + } + + return (status); +} +#endif + +#if PORT == WINDOWS || PORT == DOS +/**************************************************************************/ +/* */ + +void write_byteblaster +( + int port, + int data +) + +/* */ +/**************************************************************************/ +{ +#if PORT == WINDOWS + BOOL status = FALSE; + + int returned_length = 0; + int buffer[2]; + + if (windows_nt) + { + /* + * On Windows NT, access hardware through device driver + */ + if (port == 0) + { + port_io_buffer[port_io_count].data = (USHORT) data; + port_io_buffer[port_io_count].command = PGDC_WRITE_PORT; + ++port_io_count; + + if (port_io_count >= PORT_IO_BUFFER_SIZE) flush_ports(); + } + else + { + if (port_io_count > 0) flush_ports(); + + buffer[0] = port; + buffer[1] = data; + + status = DeviceIoControl( + nt_device_handle, /* Handle to device */ + PGDC_IOCTL_WRITE_PORT_PP, /* IO Control code for write */ + (ULONG *)&buffer, /* Buffer to driver. */ + 2 * sizeof(int), /* Length of buffer in bytes. */ + (ULONG *)NULL, /* Buffer from driver. Not used. */ + 0, /* Length of buffer in bytes. */ + (ULONG *)&returned_length, /* Bytes returned. Should be zero. */ + NULL); /* Wait for operation to complete */ + + if ((!status) || (returned_length != 0)) + { + fprintf(stderr, "I/O error: Cannot access ByteBlaster hardware\n"); + CloseHandle(nt_device_handle); + exit(1); + } + } + } + else +#endif + { + /* + * On Windows 95, access hardware directly + */ + outp((WORD)(port + lpt_addr), (WORD)data); + } +} + +/**************************************************************************/ +/* */ + +int read_byteblaster +( + int port +) + +/* */ +/**************************************************************************/ +{ + int data = 0; + +#if PORT == WINDOWS + + BOOL status = FALSE; + + int returned_length = 0; + + if (windows_nt) + { + /* flush output cache buffer before reading from device */ + if (port_io_count > 0) flush_ports(); + + /* + * On Windows NT, access hardware through device driver + */ + status = DeviceIoControl( + nt_device_handle, /* Handle to device */ + PGDC_IOCTL_READ_PORT_PP, /* IO Control code for Read */ + (ULONG *)&port, /* Buffer to driver. */ + sizeof(int), /* Length of buffer in bytes. */ + (ULONG *)&data, /* Buffer from driver. */ + sizeof(int), /* Length of buffer in bytes. */ + (ULONG *)&returned_length, /* Bytes placed in data_buffer. */ + NULL); /* Wait for operation to complete */ + + if ((!status) || (returned_length != sizeof(int))) + { + fprintf(stderr, "I/O error: Cannot access ByteBlaster hardware\n"); + CloseHandle(nt_device_handle); + exit(1); + } + } + else +#endif + { + /* + * On Windows 95, access hardware directly + */ + data = inp((WORD)(port + lpt_addr)); + } + + return (data & 0xff); +} + +#if PORT == WINDOWS +void flush_ports(void) +{ + ULONG n_writes = 0L; + BOOL status; + + status = DeviceIoControl( + nt_device_handle, /* handle to device */ + PGDC_IOCTL_PROCESS_LIST_PP, /* IO control code */ + (LPVOID)port_io_buffer, /* IN buffer (list buffer) */ + port_io_count * sizeof(struct PORT_IO_LIST_STRUCT),/* length of IN buffer in bytes */ + (LPVOID)port_io_buffer, /* OUT buffer (list buffer) */ + port_io_count * sizeof(struct PORT_IO_LIST_STRUCT),/* length of OUT buffer in bytes */ + &n_writes, /* number of writes performed */ + 0); /* wait for operation to complete */ + + if ((!status) || ((port_io_count * sizeof(struct PORT_IO_LIST_STRUCT)) != n_writes)) + { + fprintf(stderr, "I/O error: Cannot access ByteBlaster hardware\n"); + CloseHandle(nt_device_handle); + exit(1); + } + + port_io_count = 0; +} +#endif /* PORT == WINDOWS */ +#endif /* PORT == WINDOWS || PORT == DOS */ + +#if 0 +#if !defined (DEBUG) +#pragma optimize ("ceglt", off) +#endif +#endif + +void delay_loop(long count) +{ + while (count != 0L) count--; +} + +#if PORT == EMBEDDED + +static void jbi_init_mm(void) +{ +#if defined(USE_STATIC_MEMORY) + int i; +#endif /* USE_STATIC_MEMORY */ + +#if defined(USE_STATIC_MEMORY) || defined(MEM_TRACKER) + n_bytes_allocated = 0; +#endif /* USE_STATIC_MEMORY || MEM_TRACKER */ + +#if defined(MEM_TRACKER) + peak_memory_usage = 0; + peak_allocations = 0; + n_allocations = 0; +#if defined(USE_STATIC_MEMORY) + n_bytes_not_recovered = 0; +#endif /* USE_STATIC_MEMORY */ +#endif /* MEM_TRACKER */ + +#if defined(USE_STATIC_MEMORY) + jbi_dbg(DEBUG_DETAIL, "static_memory_heap: 0x%p(0x%x)\n", + static_memory_heap, N_STATIC_MEMORY_BYTES); + for (i = 0; i < N_STATIC_MEMORY_BYTES; i++) { + static_memory_heap[i] = 0; + } +#endif /* USE_STATIC_MEMORY */ + + jbi_delay_us = 0; + jbi_delay_count = 0; + jbi_peak_us = 0; +} + +static void jbi_exit_mm(void) +{ +#if defined(USE_STATIC_MEMORY) || defined(MEM_TRACKER) + jbi_dbg(DEBUG_DETAIL, "n_bytes_allocated: %u\n", n_bytes_allocated); + n_bytes_allocated = 0; +#endif /* USE_STATIC_MEMORY || MEM_TRACKER */ + +#if defined(MEM_TRACKER) + jbi_dbg(DEBUG_DETAIL, "peak_memory_usage: %u\n", peak_memory_usage); + jbi_dbg(DEBUG_DETAIL, "peak_allocations: %u\n", peak_allocations); + jbi_dbg(DEBUG_DETAIL, "n_allocations: %u\n", n_allocations); + peak_memory_usage = 0; + peak_allocations = 0; + n_allocations = 0; +#if defined(USE_STATIC_MEMORY) + jbi_dbg(DEBUG_DETAIL, "n_bytes_not_recovered: %u\n", n_bytes_not_recovered); + n_bytes_not_recovered = 0; +#endif /* USE_STATIC_MEMORY */ +#endif /* MEM_TRACKER */ + + jbi_dbg(DEBUG_DETAIL, "jbi_delay: %ld us, %ld count, peak %ld us\n", + jbi_delay_us, jbi_delay_count, jbi_peak_us); +} + +static char *get_exit_string(int format_version, int exit_code) +{ + char *exit_string = NULL; + + if (format_version == 2){ + switch (exit_code) { + case 0: + exit_string = "Success"; + break; + case 1: + exit_string = "Checking chain failure"; + break; + case 2: + exit_string = "Reading IDCODE failure"; + break; + case 3: + exit_string = "Reading USERCODE failure"; + break; + case 4: + exit_string = "Reading UESCODE failure"; + break; + case 5: + exit_string = "Entering ISP failure"; + break; + case 6: + exit_string = "Unrecognized device"; + break; + case 7: + exit_string = "Device revision is not supported"; + break; + case 8: + exit_string = "Erase failure"; + break; + case 9: + exit_string = "Device is not blank"; + break; + case 10: + exit_string = "Device programming failure"; + break; + case 11: + exit_string = "Device verify failure"; + break; + case 12: + exit_string = "Read failure"; break; + case 13: + exit_string = "Calculating checksum failure"; + break; + case 14: + exit_string = "Setting security bit failure"; + break; + case 15: + exit_string = "Querying security bit failure"; + break; + case 16: + exit_string = "Exiting ISP failure"; + break; + case 17: + exit_string = "Performing system test failure"; + break; + default: + exit_string = "Unknown exit code"; + break; + } + } else { + switch (exit_code) { + case 0: + exit_string = "Success"; + break; + case 1: + exit_string = "Illegal initialization values"; + break; + case 2: + exit_string = "Unrecognized device"; + break; + case 3: + exit_string = "Device revision is not supported"; + break; + case 4: + exit_string = "Device programming failure"; + break; + case 5: + exit_string = "Device is not blank"; + break; + case 6: + exit_string = "Device verify failure"; + break; + case 7: + exit_string = "SRAM configuration failure"; + break; + default: + exit_string = "Unknown exit code"; + break; + } + } + + return exit_string; +} + +static void jbi_help(void) +{ + fprintf(stderr, "Usage: jbi [options]\n"); + fprintf(stderr, "\nAvailable options:\n"); + fprintf(stderr, " -h : show help message\n"); + fprintf(stderr, " -v : show verbose messages\n"); + fprintf(stderr, " -i : show file info only - does not execute any action\n"); + fprintf(stderr, " -a : specify an action name (Jam STAPL)\n"); + fprintf(stderr, " -d : initialize variable to specified value (Jam 1.1)\n"); + fprintf(stderr, " -d : enable optional procedure (Jam STAPL)\n"); + fprintf(stderr, " -d : disable recommended procedure (Jam STAPL)\n"); + fprintf(stderr, " -r : don't reset JTAG TAP after use\n"); +} + +int jbi_debug(int level) +{ + jbi_debug_level = level; + + return 0; +} + +int jbi_main(unsigned char *addr, unsigned long size, int argc, char * const argv[]) +{ + BOOL help = FALSE; + BOOL error = FALSE; + long offset = 0L; + long error_address = 0L; + JBI_RETURN_TYPE crc_result = JBIC_SUCCESS; + JBI_RETURN_TYPE exec_result = JBIC_SUCCESS; + unsigned short expected_crc = 0; + unsigned short actual_crc = 0; + char key[33] = {0}; + char value[257] = {0}; + int exit_status = 0; + int arg = 0; + int exit_code = 0; + int format_version = 0; + char *workspace = NULL; + char *action = NULL; + char *init_list[10]; + int init_count = 0; + long workspace_size = 0; + char *exit_string = NULL; + int reset_jtag = 1; + int execute_program = 1; + int action_count = 0; + int procedure_count = 0; + int index = 0; + char *action_name = NULL; + char *description = NULL; + JBI_PROCINFO *procedure_list = NULL; + JBI_PROCINFO *procptr = NULL; + char *endp = NULL; + + verbose = FALSE; + + init_list[0] = NULL; + + /* print out the version string and copyright message */ + printf("Jam STAPL ByteCode Player Version 2.2\n"); + printf("Copyright (C) 1998-2001 Altera Corporation\n\n"); + + for (arg = 0; arg < argc; arg++) { + if (argv[arg][0] == '-') { + switch (toupper(argv[arg][1])) { + case 'A': /* set action name */ + if (action == NULL) { + action = &argv[arg][2]; + } else { + error = TRUE; + } + break; + case 'D': /* initialization list */ + if (argv[arg][2] == '"') { + init_list[init_count] = &argv[arg][3]; + } else { + init_list[init_count] = &argv[arg][2]; + } + init_list[++init_count] = NULL; + break; + case 'R': /* don't reset the JTAG chain after use */ + reset_jtag = 0; + break; + case 'M': /* set memory size */ + workspace = (char *) simple_strtoul(&argv[arg][2], &endp, 16); + if (workspace == NULL) { + printf("Error workspace\n"); + error = TRUE; + } else { + if (*endp == '.') { + workspace_size = simple_strtoul(endp + 1, &endp, 16); + if (*endp != '\0') { + printf("Error workspace size end\n"); + error = TRUE; + } + } else { + printf("No workspace size\n"); + error = TRUE; + } + } + break; + case 'H': /* help */ + help = TRUE; + break; + case 'V': /* verbose */ + verbose = TRUE; + break; + case 'I': /* show info only, do not execute */ + verbose = TRUE; + execute_program = 0; + break; + default: + error = TRUE; + break; + } + } else { + error = TRUE; + } + + if (error) { + fprintf(stderr, "Illegal argument: \"%s\"\n", argv[arg]); + help = TRUE; + error = FALSE; + } + } + + if (help) { + jbi_help(); + return 0; + } + + /* Calibrate the delay loop function */ + calibrate_delay(); + + jbi_init_mm(); + + /* Check CRC */ + crc_result = jbi_check_crc(addr, size, &expected_crc, &actual_crc); + if (verbose || (crc_result == JBIC_CRC_ERROR)) { + switch (crc_result) { + case JBIC_SUCCESS: + printf("CRC matched: CRC value = %04X\n", actual_crc); + break; + case JBIC_CRC_ERROR: + printf("CRC mismatch: expected %04X, actual %04X\n", expected_crc, actual_crc); + return -1; + case JBIC_UNEXPECTED_END: + printf("Expected CRC not found, actual CRC value = %04X\n", actual_crc); + return -1; + case JBIC_IO_ERROR: + printf("Error: File format is not recognized.\n"); + return -1; + default: + printf("CRC function returned error code %d\n", crc_result); + return -1; + } + } + + if (verbose) { + /* Display file format version */ + jbi_get_file_info(addr, size, &format_version, + &action_count, &procedure_count); + + printf("File format is %s ByteCode format\n", + (format_version == 2) ? "Jam STAPL" : "pre-standardized Jam 1.1"); + + /* Dump out NOTE fields */ + while (jbi_get_note(addr, size, &offset, key, value, 256) == 0) { + printf("NOTE \"%s\" = \"%s\"\n", key, value); + } + + /* Dump the action table */ + if ((format_version == 2) && (action_count > 0)) { + printf("\nActions available in this file:\n"); + + for (index = 0; index < action_count; ++index) { + jbi_get_action_info(addr, size, + index, &action_name, &description, &procedure_list); + + if (description == NULL) { + printf("%s\n", action_name); + } else { + printf("%s \"%s\"\n", action_name, description); + } + + procptr = procedure_list; + while (procptr != NULL) { + if (procptr->attributes != 0) { + printf(" %s (%s)\n", procptr->name, + (procptr->attributes == 1) ? "optional" : "recommended"); + } + + procedure_list = procptr->next; + jbi_free(procptr); + procptr = procedure_list; + } + } + + /* add a blank line before execution messages */ + if (execute_program) + printf("\n"); + } + } + + if (execute_program) { + /* Execute the Jam STAPL ByteCode program */ + exec_result = jbi_execute(addr, size, workspace, + workspace_size, action, init_list, reset_jtag, + &error_address, &exit_code, &format_version); + if (exec_result == JBIC_SUCCESS) { + exit_string = get_exit_string(format_version, exit_code); + printf("Exit code = %d... %s\n", exit_code, exit_string); + } else if ((format_version == 2) && (exec_result == JBIC_ACTION_NOT_FOUND)) { + if ((action == NULL) || (*action == '\0')) { + printf("Error: no action specified for Jam STAPL file.\n" + "Program terminated.\n"); + } else { + printf("Error: action \"%s\" is not supported for this Jam STAPL file.\n" + "Program terminated.\n", action); + } + } else if (exec_result < MAX_ERROR_CODE) { + printf("Error at address %ld: %s.\nProgram terminated.\n", + error_address, error_text[exec_result]); + } else { + printf("Unknown error code %d\n", exec_result); + } + } + + if (jtag_hardware_initialized) { + close_jtag_hardware(); + jtag_hardware_initialized = FALSE; + } + +#if defined(MEM_TRACKER) + if (verbose) { +#if defined(USE_STATIC_MEMORY) + fprintf(stdout, "Memory Usage Info: static memory size = %uBytes (%dKB)\n", + N_STATIC_MEMORY_BYTES, N_STATIC_MEMORY_KBYTES); +#endif /* USE_STATIC_MEMORY */ + fprintf(stdout, "Memory Usage Info: peak memory usage = %uBytes (%dKB)\n", + peak_memory_usage, (peak_memory_usage + 1023) / 1024); + fprintf(stdout, "Memory Usage Info: peak allocations = %u\n", + peak_allocations); +#if defined(USE_STATIC_MEMORY) + if ((n_bytes_allocated - n_bytes_not_recovered) != 0) { + fprintf(stdout, "Memory Usage Info: bytes still allocated = %d (%dKB)\n", + (n_bytes_allocated - n_bytes_not_recovered), + ((n_bytes_allocated - n_bytes_not_recovered) + 1023) / 1024); + } +#else /* USE_STATIC_MEMORY */ + if (n_bytes_allocated != 0) { + fprintf(stdout, "Memory Usage Info: bytes still allocated = %d (%dKB)\n", + n_bytes_allocated, (n_bytes_allocated + 1023) / 1024); + } +#endif /* USE_STATIC_MEMORY */ + if (n_allocations != 0) { + fprintf(stdout, "Memory Usage Info: allocations not freed = %d\n", n_allocations); + } + } +#endif /* MEM_TRACKER */ + + jbi_exit_mm(); + + if (exec_result != JBIC_SUCCESS) { + return (-exec_result); + } + + if (exit_code != 0) { + return (exit_code); + } + + return (exit_status); +} + +#endif /* PORT == EMBEDDED */ diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/jbistub.h b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/jbistub.h new file mode 100644 index 000000000000..5e5c5332f385 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_cpld/jbistub.h @@ -0,0 +1,95 @@ +#ifndef __JBISTUB_H__ +#define __JBISTUB_H__ + +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_64BIT +typedef s64 addr_t; +#else +typedef s32 addr_t; +#endif +/* typedef long addr_t; */ + +/* #define USE_STATIC_MEMORY 100 */ +/* #define MEM_TRACKER */ + +/* #define O_RDWR 1 */ + +#define stdout (1) +#define stderr (2) + +#define puts printk +#define printf printk + +#define fprintf(std, fmt, arg...) \ + do { \ + printf(fmt, ##arg); \ + } while (0) + +#define DEBUG_NONE 0 +#define DEBUG_ERR 1 +#define DEBUG_DETAIL 2 +#define DEBUG_NOISY 3 +#define DEBUG_MM 4 + +#define jbi_dbg(level, fmt, arg...) \ + do { \ + if (level <= jbi_debug_level) { \ + printf(fmt, ##arg); \ + } \ + } while (0) + +extern int jbi_debug_level; + +static inline int open(char *path, int flag) +{ + return 0; +} + +static inline int close(int fd) +{ + return 0; +} + +static inline int read(int fd, char *buf, int count) +{ + return 0; +} + +static inline int write(int fd, char *buf, int count) +{ + return 0; +} + +static inline int fflush(int fd) +{ + return 0; +} + +static inline int clock(void) +{ + return 0; +} + +static inline int atoi(const char *nptr) +{ + return (int) simple_strtol(nptr, (char **) NULL, 10); +} + +static inline void *malloc(size_t size) +{ + return kmalloc(size, GFP_KERNEL); +} + +static inline void free(void *ptr) +{ + kfree(ptr); +} + +#endif /* __JBISTUB_H__ */ diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_ispvme/Makefile b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_ispvme/Makefile new file mode 100644 index 000000000000..caad44948030 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_ispvme/Makefile @@ -0,0 +1,22 @@ +#include $(top_srcdir)/debian/rules +#KERNELDIR := ${KBUILD_OUTPUT} + +PWD = $(shell pwd) + +EXTRA_CFLAGS:= -I$(M)/include +MAKEFILE_FILE_PATH = $(abspath $(lastword $(MAKEFILE_LIST))) +FIRMWARE_UPGRADE_PATH = $(abspath $(MAKEFILE_FILE_PATH)/../../include) +EXTRA_CFLAGS+= -I$(FIRMWARE_UPGRADE_PATH) +EXTRA_CFLAGS+= -Wall + +firmware_driver_ispvme-objs := firmware_ispvme.o +firmware_driver_ispvme-objs += firmware_cpld_ispvme.o firmware_cpld_upgrade_ispvme.o + +#ifndef CONFIG_FRM_PRODUCT_FILE + +$(warning $(firmware_driver_ispvme-objs)) +obj-m := firmware_driver_ispvme.o +all: + $(MAKE) -C $(KERNEL_SRC)/build M=$(PWD) modules + @if [ ! -d $(common_module_dir) ]; then mkdir -p $(common_module_dir) ;fi + cp -p $(PWD)/*.ko $(common_module_dir) diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_ispvme/firmware_cpld_ispvme.c b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_ispvme/firmware_cpld_ispvme.c new file mode 100644 index 000000000000..9841782290c1 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_ispvme/firmware_cpld_ispvme.c @@ -0,0 +1,450 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static int firmware_cpld_open(struct inode *inode, struct file *file) +{ + firmware_device_t *frm_dev; + + FIRMWARE_DRIVER_DEBUG_VERBOSE("Open cpld device.\n"); + frm_dev = firmware_get_device_by_minor(MINOR(inode->i_rdev)); + if (frm_dev == NULL) { + return -ENXIO; + } + file->private_data = frm_dev; + + return FIRMWARE_SUCCESS; +} + +static ssize_t firmware_cpld_read (struct file *file, char __user *buf, size_t count, + loff_t *offset) +{ + return 0; +} + +static ssize_t firmware_cpld_write (struct file *file, const char __user *buf, size_t count, + loff_t *offset) +{ + return 0; +} + +static loff_t firmware_cpld_llseek(struct file *file, loff_t offset, int origin) +{ + return 0; +} + +/* + * firmware_cpld_ioctl + * function: ispvme driver ioctl command parsing function + * @file: param[in] device file name + * @cmd: param[in] command + * @arg: param[in] the parameters in the command + * return value: success-FIRMWARE_SUCCESS; fail:other value + */ +static long firmware_cpld_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + int ret; + void __user *argp; + firmware_device_t *frm_dev; + firmware_cpld_t *cpld_info; + char value; + + /* Get device private data */ + frm_dev = (firmware_device_t *)file->private_data; + cpld_info = NULL; + if (frm_dev != NULL) { + if (frm_dev->priv != NULL) { + cpld_info = (firmware_cpld_t *)frm_dev->priv; + } + } + if (cpld_info == NULL) { + FIRMWARE_DRIVER_DEBUG_ERROR("Error: Failed to frm_dev->priv sysfs info.\n"); + return FIRMWARE_FAILED; + } + argp = (void __user *)arg; + + switch (cmd) { + case FIRMWARE_JTAG_TDI: + /* Set the TDI signal */ + if (copy_from_user(&value, argp, sizeof(value))) { + return -EFAULT; + } + if (fwm_cpld_tdi_op(value) < 0 ) { + return -EFAULT; + } + break; + case FIRMWARE_JTAG_TCK: + /* Set the TCK signal */ + if (copy_from_user(&value, argp, sizeof(value))) { + return -EFAULT; + } + if (fwm_cpld_tck_op(value) < 0) { + return -EFAULT; + } + break; + case FIRMWARE_JTAG_TMS: + /* Set the TMS signal */ + if (copy_from_user(&value, argp, sizeof(value))) { + return -EFAULT; + } + if (fwm_cpld_tms_op(value) < 0) { + return -EFAULT; + } + break; + case FIRMWARE_JTAG_TDO: + /* Read the TDO signal */ + value = fwm_cpld_tdo_op(); + if (copy_to_user(argp, &value, sizeof(value))) { + return -EFAULT; + } + break; + case FIRMWARE_JTAG_INIT: + /* The VME upgrade mode initializes the operation */ + ret=firmware_init_vme(cpld_info); + if (ret != FIRMWARE_SUCCESS) { + FIRMWARE_DRIVER_DEBUG_ERROR("Error: Failed to init upgrade.(chain = %d)\n", + frm_dev != NULL ? frm_dev->chain : -1); + return FIRMWARE_FAILED; + } + break; + case FIRMWARE_JTAG_FINISH: + /* The VME upgrade mode completes the operation */ + ret=firmware_finish_vme(cpld_info); + if (ret != FIRMWARE_SUCCESS) { + FIRMWARE_DRIVER_DEBUG_ERROR("Error: Failed to release upgrade.(chain = %d)\n", + frm_dev != NULL ? frm_dev->chain : -1); + return FIRMWARE_FAILED; + } + break; + default: + FIRMWARE_DRIVER_DEBUG_ERROR("not find cmd: %d\r\n", cmd); + return -ENOTTY; + } /* End of switch */ + + return FIRMWARE_SUCCESS; +} + +static int firmware_cpld_release(struct inode *inode, struct file *file) +{ + return 0; +} + +static const struct file_operations cpld_dev_fops = { + .owner = THIS_MODULE, + .llseek = firmware_cpld_llseek, + .read = firmware_cpld_read, + .write = firmware_cpld_write, + .unlocked_ioctl = firmware_cpld_ioctl, + .open = firmware_cpld_open, + .release = firmware_cpld_release, +}; + +static int of_firmware_upgrade_config_init(struct device *dev, firmware_cpld_t *cpld_info) +{ + int ret; + char *name; + int i; + char buf[64]; + firmware_logic_dev_en_t *firmware_logic_dev_en_point; + + FIRMWARE_DRIVER_DEBUG_VERBOSE("Enter firmware_upgrade_config_init\r\n"); + if (cpld_info == NULL) { + FIRMWARE_DRIVER_DEBUG_ERROR("info is null\r\n"); + return -1; + } + + mem_clear(cpld_info, sizeof(firmware_cpld_t)); + ret = 0; + ret += of_property_read_string(dev->of_node, "type", (const char **)&name); + ret += of_property_read_u32(dev->of_node, "tdi", &cpld_info->tdi); + ret += of_property_read_u32(dev->of_node, "tck", &cpld_info->tck); + ret += of_property_read_u32(dev->of_node, "tms", &cpld_info->tms); + ret += of_property_read_u32(dev->of_node, "tdo", &cpld_info->tdo); + + ret += of_property_read_u32(dev->of_node, "chain", &cpld_info->chain); + ret += of_property_read_u32(dev->of_node, "chip_index", &cpld_info->chip_index); + + if (ret != 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("dts config error, ret:%d.\n", ret); + return -ENXIO; + } + + strncpy(cpld_info->type, name, sizeof(cpld_info->type) - 1); + + ret = of_property_read_u32(dev->of_node, "tck_delay", &cpld_info->tck_delay); + if(ret != 0) { + cpld_info->tck_delay = 60; + } + + cpld_info->gpio_en_info_num = 0; + /* Enable through GPIO */ + for (i = 0; i < FIRMWARE_EN_INFO_MAX; i++) { + mem_clear(buf, sizeof(buf)); + snprintf(buf, sizeof(buf) - 1, "en_gpio_%d", i); + ret = of_property_read_u32(dev->of_node, buf, &cpld_info->gpio_en_info[i].en_gpio); + if(ret != 0) { + break; + } + + mem_clear(buf, sizeof(buf)); + snprintf(buf, sizeof(buf) - 1, "en_level_%d", i); + ret = of_property_read_u32(dev->of_node, buf, &cpld_info->gpio_en_info[i].en_level); + if(ret != 0) { + break; + } + cpld_info->gpio_en_info_num++; + } + + cpld_info->logic_dev_en_num = 0; + /* Enable through register */ + for (i = 0; i < FIRMWARE_EN_INFO_MAX; i++) { + firmware_logic_dev_en_point = &cpld_info->logic_dev_en_info[i]; + mem_clear(buf, sizeof(buf)); + snprintf(buf, sizeof(buf) - 1, "en_logic_dev_%d", i); + ret = 0; + ret += of_property_read_string(dev->of_node, buf, (const char **)&name); + if(ret != 0) { + /* Failure to resolve to EN_LOGIC_DEV means no logical device is enabled. No failure is returned */ + ret = 0; + break; + } + strncpy(firmware_logic_dev_en_point->dev_name, name, FIRMWARE_DEV_NAME_LEN - 1); + + mem_clear(buf, sizeof(buf)); + snprintf(buf, sizeof(buf) - 1, "en_logic_addr_%d", i); + ret = of_property_read_u32(dev->of_node, buf, &firmware_logic_dev_en_point->addr); + if (ret != 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("Failed to config en en_logic_addr_%d ret =%d.\n", i, ret); + break; + } + + mem_clear(buf, sizeof(buf)); + snprintf(buf, sizeof(buf) - 1, "en_logic_mask_%d", i); + ret = of_property_read_u32(dev->of_node, buf, &firmware_logic_dev_en_point->mask); + if (ret != 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("Failed to config en en_logic_mask_%d ret =%d.\n", i, ret); + break; + } + + mem_clear(buf, sizeof(buf)); + snprintf(buf, sizeof(buf) - 1, "en_logic_en_val_%d", i); + ret = of_property_read_u32(dev->of_node, buf, &firmware_logic_dev_en_point->en_val); + if (ret != 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("Failed to config en en_logic_en_val_%d ret =%d.\n", i, ret); + break; + } + + mem_clear(buf, sizeof(buf)); + snprintf(buf, sizeof(buf) - 1, "en_logic_dis_val_%d", i); + ret = of_property_read_u32(dev->of_node, buf, &firmware_logic_dev_en_point->dis_val); + if (ret != 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("Failed to config en en_logic_dis_val_%d ret =%d.\n", i, ret); + break; + } + + mem_clear(buf, sizeof(buf)); + snprintf(buf, sizeof(buf) - 1, "en_logic_width_%d", i); + ret = of_property_read_u32(dev->of_node, buf, &firmware_logic_dev_en_point->width); + if (ret != 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("Failed to config en en_logic_width_%d ret =%d.\n", i, ret); + break; + } + + cpld_info->logic_dev_en_num++; + } + + FIRMWARE_DRIVER_DEBUG_VERBOSE("type:%s, chain:%u, chip_index:%u, gpio_en_info_num:%u logic_dev_en_num:%u\n", + cpld_info->type, cpld_info->chain, cpld_info->chip_index, cpld_info->gpio_en_info_num, cpld_info->logic_dev_en_num); + FIRMWARE_DRIVER_DEBUG_VERBOSE("tdi:%u, tck:%u, tms:%u, tdo:%u tck_delay:%u.\n", + cpld_info->tdi, cpld_info->tck, cpld_info->tms, cpld_info->tdo, cpld_info->tck_delay); + + return 0; +} + +static int firmware_upgrade_config_init(struct device *dev, firmware_cpld_t *cpld_info) +{ + int i; + + firmware_logic_dev_en_t *firmware_logic_dev_en_point; + firmware_upgrade_device_t *firmware_upgrade_device; + firmware_jtag_device_t jtag_upg_device; + + FIRMWARE_DRIVER_DEBUG_VERBOSE("Enter firmware_upgrade_config_init\r\n"); + if (cpld_info == NULL) { + FIRMWARE_DRIVER_DEBUG_ERROR("info is null\r\n"); + return -1; + } + + if (dev->platform_data == NULL) { + FIRMWARE_DRIVER_DEBUG_ERROR("platform data config error.\n"); + return -1; + } + firmware_upgrade_device = dev->platform_data; + jtag_upg_device = firmware_upgrade_device->upg_type.jtag; + + mem_clear(cpld_info, sizeof(firmware_cpld_t)); + strncpy(cpld_info->type, firmware_upgrade_device->type, sizeof(cpld_info->type) - 1); + cpld_info->tdi = jtag_upg_device.tdi; + cpld_info->tck = jtag_upg_device.tck; + cpld_info->tms = jtag_upg_device.tms; + cpld_info->tdo = jtag_upg_device.tdo; + cpld_info->chain = firmware_upgrade_device->chain; + cpld_info->chip_index = firmware_upgrade_device->chip_index; + + if (jtag_upg_device.tck_delay == 0) { + cpld_info->tck_delay = 60; + FIRMWARE_DRIVER_DEBUG_VERBOSE("no config tck_delay, use default value:%u\n", cpld_info->tck_delay); + } else { + cpld_info->tck_delay = jtag_upg_device.tck_delay; + } + + if (firmware_upgrade_device->en_gpio_num > FIRMWARE_EN_INFO_MAX) { + FIRMWARE_DRIVER_DEBUG_ERROR("The number of en_gpio_num:%u configurations exceeds the maximum limit:%u.\n", + firmware_upgrade_device->en_gpio_num, FIRMWARE_EN_INFO_MAX); + return -ENXIO; + } + cpld_info->gpio_en_info_num = firmware_upgrade_device->en_gpio_num; + /* Enable through GPIO */ + for (i = 0; i < cpld_info->gpio_en_info_num; i++) { + cpld_info->gpio_en_info[i].en_gpio = firmware_upgrade_device->en_gpio[i]; + cpld_info->gpio_en_info[i].en_level = firmware_upgrade_device->en_level[i]; + } + + if (firmware_upgrade_device->en_logic_num > FIRMWARE_EN_INFO_MAX) { + FIRMWARE_DRIVER_DEBUG_ERROR("The number of en_logic_num:%u configurations exceeds the maximum limit:%u.\n", + firmware_upgrade_device->en_logic_num, FIRMWARE_EN_INFO_MAX); + return -ENXIO; + } + cpld_info->logic_dev_en_num = firmware_upgrade_device->en_logic_num; + /* Enable through register */ + for (i = 0; i < cpld_info->logic_dev_en_num; i++) { + firmware_logic_dev_en_point = &cpld_info->logic_dev_en_info[i]; + strncpy(firmware_logic_dev_en_point->dev_name, firmware_upgrade_device->en_logic_dev[i], + FIRMWARE_DEV_NAME_LEN - 1); + firmware_logic_dev_en_point->addr = firmware_upgrade_device->en_logic_addr[i]; + firmware_logic_dev_en_point->mask = firmware_upgrade_device->en_logic_mask[i]; + firmware_logic_dev_en_point->en_val = firmware_upgrade_device->en_logic_en_val[i]; + firmware_logic_dev_en_point->dis_val = firmware_upgrade_device->en_logic_dis_val[i]; + firmware_logic_dev_en_point->width = firmware_upgrade_device->en_logic_width[i]; + } + + FIRMWARE_DRIVER_DEBUG_VERBOSE("type:%s, chain:%u, chip_index:%u, gpio_en_info_num:%u logic_dev_en_num:%u\n", + cpld_info->type, cpld_info->chain, cpld_info->chip_index, cpld_info->gpio_en_info_num, cpld_info->logic_dev_en_num); + FIRMWARE_DRIVER_DEBUG_VERBOSE("tdi:%u, tck:%u, tms:%u, tdo:%u tck_delay:%u.\n", + cpld_info->tdi, cpld_info->tck, cpld_info->tms, cpld_info->tdo, cpld_info->tck_delay); + + return 0; +} + +static int firmware_cpld_probe(struct platform_device *pdev) +{ + int ret; + firmware_cpld_t *cpld_info; + firmware_device_t *frm_dev; + + FIRMWARE_DRIVER_DEBUG_VERBOSE("Enter firmware_cpld_probe\r\n"); + /* Gets the information in the device tree */ + cpld_info = devm_kzalloc(&pdev->dev, sizeof(firmware_cpld_t), GFP_KERNEL); + if (cpld_info == NULL) { + FIRMWARE_DRIVER_DEBUG_ERROR("Failed to kzalloc cpld device tree.\n"); + return -EPERM; + } + + if (pdev->dev.of_node) { + ret = of_firmware_upgrade_config_init(&pdev->dev, cpld_info); + } else { + ret = firmware_upgrade_config_init(&pdev->dev, cpld_info); + } + if (ret < 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("get config init from dts error.\n"); + return -EPERM; + } + + frm_dev = devm_kzalloc(&pdev->dev, sizeof(firmware_device_t), GFP_KERNEL); + if (frm_dev == NULL) { + FIRMWARE_DRIVER_DEBUG_ERROR("Failed to kzalloc firmware device.\n"); + return -EPERM; + } + + /* Based on the link number, determine the name of the device file */ + frm_dev->chain = cpld_info->chain; + snprintf(frm_dev->name, FIRMWARE_NAME_LEN - 1, "firmware_cpld_ispvme%d", frm_dev->chain); + strncpy(cpld_info->devname, frm_dev->name, strlen(frm_dev->name) + 1); + + INIT_LIST_HEAD(&frm_dev->list); + frm_dev->dev.minor = MISC_DYNAMIC_MINOR; + frm_dev->dev.name = frm_dev->name; + frm_dev->dev.fops = &cpld_dev_fops; + frm_dev->priv = cpld_info; + + FIRMWARE_DRIVER_DEBUG_VERBOSE("Register cpld firmware chain:%d, name:%s.\n", frm_dev->chain, frm_dev->name); + + ret = firmware_device_register(frm_dev); + if (ret < 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("Failed to register firmware device.\n"); + return -EPERM; + } + + platform_set_drvdata(pdev, frm_dev); + return 0; +} + +static int __exit firmware_cpld_remove(struct platform_device *pdev) +{ + firmware_device_t *frm_dev; + + frm_dev = (firmware_device_t *)platform_get_drvdata(pdev); + firmware_device_unregister(frm_dev); + platform_set_drvdata(pdev, NULL); + + return 0; +} + +static struct of_device_id cpld_match[] = { + { + .compatible = "firmware_cpld_ispvme", + }, + {}, +}; + +static struct platform_driver cpld_driver = { + .driver = { + .name = "firmware_cpld_ispvme", + .owner = THIS_MODULE, + .of_match_table = cpld_match, + }, + .probe = firmware_cpld_probe, + .remove = firmware_cpld_remove, +}; + +static firmware_driver_t fmw_drv_cpld = { + .name = "firmware_cpld_ispvme", + .drv = &cpld_driver, +}; + +int firmware_cpld_init(void) +{ + int ret; + + INIT_LIST_HEAD(&fmw_drv_cpld.list); + FIRMWARE_DRIVER_DEBUG_VERBOSE("ispvme upgrade driver register \n"); + ret = firmware_driver_register(&fmw_drv_cpld); + if (ret < 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("ispvme upgrade driver register failed\n"); + return ret; + } + return 0; +} + +void firmware_cpld_exit(void) +{ + firmware_driver_unregister(&fmw_drv_cpld); + INIT_LIST_HEAD(&fmw_drv_cpld.list); +} diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_ispvme/firmware_cpld_upgrade_ispvme.c b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_ispvme/firmware_cpld_upgrade_ispvme.c new file mode 100644 index 000000000000..b8896ed75f38 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_ispvme/firmware_cpld_upgrade_ispvme.c @@ -0,0 +1,691 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* TCK clock MAX 16MHz */ +#define TCK_DELAY (current_fmw_cpld->tck_delay) + +#if 0 +static firmware_cpld_t default_fmw_cpld; +#endif + +static firmware_cpld_t *current_fmw_cpld; + +static int TDI_PULL_UP(void); +static int TDI_PULL_DOWN(void); +static int TMS_PULL_UP(void); +static int TMS_PULL_DOWN(void); +static int TCK_PULL_UP(void); +static int TCK_PULL_DOWN(void); + +/* + * set_currrent_cpld_info + * function: Save the current device information + * @info: param[in] Information about the device to be updated + */ +static void set_currrent_cpld_info(firmware_cpld_t *info) +{ + current_fmw_cpld = info; +} + +static int firmware_file_read(const char *path, uint32_t addr, uint8_t *val, size_t size) +{ + int ret; + struct file *filp; + loff_t pos; + + filp = filp_open(path, O_RDONLY, 0); + if (IS_ERR(filp)) { + FIRMWARE_DRIVER_DEBUG_ERROR("read open failed errno = %ld\r\n", -PTR_ERR(filp)); + filp = NULL; + goto exit; + } + + pos = (loff_t)addr; + ret = kernel_read(filp, val, size, &pos); + if (ret != size) { + FIRMWARE_DRIVER_DEBUG_ERROR("read kernel_read failed, path=%s, addr=%d, size=%ld, ret=%d\r\n", path, addr, size, ret); + goto exit; + } + filp_close(filp, NULL); + + return ret; + +exit: + if (filp != NULL) { + filp_close(filp, NULL); + } + + return -1; +} + +static int firmware_file_write(const char *path, uint32_t addr, uint8_t *val, size_t size) +{ + int ret; + struct file *filp; + loff_t pos; + + filp = filp_open(path, O_RDWR, 777); + if (IS_ERR(filp)) { + FIRMWARE_DRIVER_DEBUG_ERROR("write open failed errno = %ld\r\n", -PTR_ERR(filp)); + filp = NULL; + goto exit; + } + + pos = (loff_t)addr; + ret = kernel_write(filp, (void*)val, size, &pos); + if (ret < 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("write kernel_write failed, path=%s, addr=%d, size=%ld, ret=%d\r\n", path, addr, size, ret); + goto exit; + } + vfs_fsync(filp, 1); + filp_close(filp, NULL); + + return ret; + +exit: + if (filp != NULL) { + filp_close(filp, NULL); + } + + return -1; +} + +/* + * firmware_file_do_work + * function: Sets logical register values + * @path:param[in] Logic device descriptor + * @addr:param[in] Logic device address + * @value:param[in] the register value needs to be set + * @mask:param[in] register mask + * @width:param[in] register bit width + * return: 0:success, <0:failed + */ +static int firmware_file_do_work(char *path, uint32_t addr, uint32_t value, uint32_t mask, + int32_t width) +{ + int ret; + uint8_t read_value[4], write_value[4]; + uint8_t tmp_read8, tmp_write8, tmp_mask8; + uint32_t tmp_read32, tmp_write32; + + FIRMWARE_DRIVER_DEBUG_VERBOSE("path=%s, addr=0x%x, value=0x%x mask=0x%x\r\n", path, addr, value, mask); + if ((width > 4) || (width < 0)) { + FIRMWARE_DRIVER_DEBUG_ERROR("width %d is not support.\r\n", width); + return -1; + } + ret = 0; + mem_clear(read_value, sizeof(read_value)); + mem_clear(write_value, sizeof(write_value)); + ret = firmware_file_read(path, addr, read_value, width); + if (ret < 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("firmware sysfs read.\r\n"); + return -1; + } + + switch (width) { + case 1: + tmp_read8 = read_value[0]; + tmp_mask8 = (uint8_t)(mask) & 0xFF; + tmp_write8 = (uint8_t)value & 0xFF; + write_value[0] = (tmp_read8 & tmp_mask8) | tmp_write8; + FIRMWARE_DRIVER_DEBUG_VERBOSE("1 byte write val[0]:0x%x", write_value[0]); + break; + case 2: + FIRMWARE_DRIVER_DEBUG_ERROR("width %d is not support.\r\n", width); + return -1; + case 4: + memcpy((uint8_t *)&tmp_read32, read_value, 4); + tmp_write32 = (tmp_read32 & mask) | value; + memcpy(write_value, (uint8_t *)&tmp_write32, 4); + FIRMWARE_DRIVER_DEBUG_VERBOSE("4 byte write val[0]:0x%x, val[1]:0x%x, val[2]:0x%x, val[3]:0x%x", + write_value[0], write_value[1], write_value[2], write_value[3]); + break; + default: + FIRMWARE_DRIVER_DEBUG_ERROR("width %d is not support.\r\n", width); + return -1; + } + + FIRMWARE_DRIVER_DEBUG_VERBOSE("write logic dev[%s] addr[0x%x].\r\n", path, addr); + ret = firmware_file_write(path, addr, write_value, width); + if (ret < 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("firmware_file_write %s addr 0x%x failed, ret=%d.\r\n", path, addr, ret); + return -1; + } + + return 0; +} + +/* + * firmware_upgrade_en + * function: Upgrade access enabling switch + * @flag: !0:enable 0:disable + */ +static int firmware_upgrade_en(int flag) +{ + int i; + firmware_logic_dev_en_t *firmware_logic_dev_en_info; + int ret, rv; + char *dev_name; + + ret = 0; + FIRMWARE_DRIVER_DEBUG_VERBOSE("%s en switch: gpio en num %d, logic reg en num %d.\n", + flag ? "Open" : "Close", current_fmw_cpld->gpio_en_info_num, current_fmw_cpld->logic_dev_en_num); + for (i = 0; i < current_fmw_cpld->gpio_en_info_num; i++) { + if (flag) { + ret = gpio_request(current_fmw_cpld->gpio_en_info[i].en_gpio, "cpld_ispvme_upgrade"); + if (ret) { + FIRMWARE_DRIVER_DEBUG_ERROR("Requesting cpld_ispvme_upgrade EN[%d] GPIO[%d] failed!\n", + i, current_fmw_cpld->gpio_en_info[i].en_gpio); + goto free_gpio; + } + gpio_direction_output(current_fmw_cpld->gpio_en_info[i].en_gpio, current_fmw_cpld->gpio_en_info[i].en_level); + current_fmw_cpld->gpio_en_info[i].flag = 1; + } else { + gpio_set_value(current_fmw_cpld->gpio_en_info[i].en_gpio, !current_fmw_cpld->gpio_en_info[i].en_level); + gpio_free(current_fmw_cpld->gpio_en_info[i].en_gpio); + current_fmw_cpld->gpio_en_info[i].flag = 0; + } + } + + for (i = 0; i < current_fmw_cpld->logic_dev_en_num; i++) { + firmware_logic_dev_en_info = ¤t_fmw_cpld->logic_dev_en_info[i]; + dev_name = firmware_logic_dev_en_info->dev_name; + FIRMWARE_DRIVER_DEBUG_VERBOSE("firmware sysfs [%d] dev_name[%s] addr[0x%x] mask[0x%x]" + " en_val[0x%x] dis_val[0x%x] width[%d]\n", + i , firmware_logic_dev_en_info->dev_name, firmware_logic_dev_en_info->addr, + firmware_logic_dev_en_info->mask, firmware_logic_dev_en_info->en_val, + firmware_logic_dev_en_info->dis_val, firmware_logic_dev_en_info->width); + if (flag) { + ret = firmware_file_do_work(dev_name, firmware_logic_dev_en_info->addr, + firmware_logic_dev_en_info->en_val, firmware_logic_dev_en_info->mask, + firmware_logic_dev_en_info->width); + if (ret < 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("Open logic register [%d] EN failed, ret %d.\n", i, ret); + goto free_logic_dev; + } else { + firmware_logic_dev_en_info->flag = 1; + } + } else { + rv = firmware_file_do_work(dev_name, firmware_logic_dev_en_info->addr, + firmware_logic_dev_en_info->dis_val, firmware_logic_dev_en_info->mask, + firmware_logic_dev_en_info->width); + if (rv < 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("Close logic register [%d] EN failed, ret %d.\n", i, rv); + ret = -1; + } + firmware_logic_dev_en_info->flag = 0; + } + } + + return ret; +free_logic_dev: + for (i = 0; i < current_fmw_cpld->logic_dev_en_num; i++) { + firmware_logic_dev_en_info = ¤t_fmw_cpld->logic_dev_en_info[i]; + dev_name = firmware_logic_dev_en_info->dev_name; + if (firmware_logic_dev_en_info->flag == 1) { + ret = firmware_file_do_work(dev_name, firmware_logic_dev_en_info->addr, + firmware_logic_dev_en_info->dis_val, firmware_logic_dev_en_info->mask, + firmware_logic_dev_en_info->width); + if (ret < 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("Close logic register [%d] EN failed, ret %d.\n", i, ret); + } + firmware_logic_dev_en_info->flag = 0; + } else { + break; + } + } +free_gpio: + for (i = 0; i < current_fmw_cpld->gpio_en_info_num; i++) { + if (current_fmw_cpld->gpio_en_info[i].flag == 1) { + gpio_set_value(current_fmw_cpld->gpio_en_info[i].en_gpio, !current_fmw_cpld->gpio_en_info[i].en_level); + gpio_free(current_fmw_cpld->gpio_en_info[i].en_gpio); + current_fmw_cpld->gpio_en_info[i].flag = 0; + } else { + break; + } + } + + return -1; +} + +/* + * init_cpld + * function:Initialize CPLD + * return value: 0 success ; -1 fail + */ +static int init_cpld(void) +{ + int ret; + if (current_fmw_cpld == NULL) { + return -1; + } + mdelay(10); + ret = 0; + ret = gpio_request(current_fmw_cpld->tdi, "cpld_ispvme_upgrade"); + if (ret) { + FIRMWARE_DRIVER_DEBUG_ERROR("Requesting cpld_ispvme_upgrade TDI GPIO failed!\n"); + return ret; + } + ret = gpio_request(current_fmw_cpld->tck, "cpld_ispvme_upgrade"); + if (ret) { + FIRMWARE_DRIVER_DEBUG_ERROR("Requesting cpld_ispvme_upgrade TCK GPIO failed!\n"); + goto free_tdi; + } + ret = gpio_request(current_fmw_cpld->tms, "cpld_ispvme_upgrade"); + if (ret) { + FIRMWARE_DRIVER_DEBUG_ERROR("Requesting cpld_ispvme_upgrade TMS GPIO failed!\n"); + goto free_tck; + } + ret = gpio_request(current_fmw_cpld->tdo, "cpld_ispvme_upgrade"); + if (ret) { + FIRMWARE_DRIVER_DEBUG_ERROR("Requesting cpld_ispvme_upgrade TDO GPIO failed!\n"); + goto free_tms; + } + + gpio_direction_output(current_fmw_cpld->tdi, 1); + gpio_direction_output(current_fmw_cpld->tck, 1); + gpio_direction_output(current_fmw_cpld->tms, 1); + + gpio_direction_input(current_fmw_cpld->tdo); + ret = firmware_upgrade_en(1); + if (ret) { + FIRMWARE_DRIVER_DEBUG_ERROR("Error: open firmware upgrade en failed, ret %d.\n", ret); + goto free_tdo; + } +#if 0 + /* test GPIO */ + if (TDI_PULL_UP() < 0 ) { + FIRMWARE_DRIVER_DEBUG_ERROR("Error: TDI_PULL_UP failed.\n"); + goto free_tdo; + } + if (TDI_PULL_DOWN() < 0 ) { + FIRMWARE_DRIVER_DEBUG_ERROR("Error: TDI_PULL_DOWN failed.\n"); + goto free_tdo; + } + if (TMS_PULL_UP() < 0 ) { + FIRMWARE_DRIVER_DEBUG_ERROR("Error: TMS_PULL_UP failed.\n"); + goto free_tdo; + } + if (TMS_PULL_DOWN() < 0 ) { + FIRMWARE_DRIVER_DEBUG_ERROR("Error: TMS_PULL_DOWN failed.\n"); + goto free_tdo; + } + if (TCK_PULL_UP() < 0 ) { + FIRMWARE_DRIVER_DEBUG_ERROR("Error: TCK_PULL_UP failed.\n"); + goto free_tdo; + } + if (TCK_PULL_DOWN() < 0 ) { + FIRMWARE_DRIVER_DEBUG_ERROR("Error: TCK_PULL_DOWN failed.\n"); + goto free_tdo; + } +#endif + mdelay(10); + return 0; + +free_tdo: + gpio_free(current_fmw_cpld->tdo); +free_tms: + gpio_free(current_fmw_cpld->tms); +free_tck: + gpio_free(current_fmw_cpld->tck); +free_tdi: + gpio_free(current_fmw_cpld->tdi); + return ret; +} + +/* + * finish_cpld + * function: finish CPLD upgrade operation + * return value: 0 success ; -1 fail + */ +static int finish_cpld(void) +{ + int ret; + + if (current_fmw_cpld == NULL) { + return -1; + } + mdelay(10); + ret = firmware_upgrade_en(0); + if (ret < 0){ + FIRMWARE_DRIVER_DEBUG_ERROR("Error: close firmware upgrade en failed, ret %d.\r\n", ret); + } + + gpio_free(current_fmw_cpld->tdi); + gpio_free(current_fmw_cpld->tck); + gpio_free(current_fmw_cpld->tms); + gpio_free(current_fmw_cpld->tdo); + mdelay(10); + return 0; +} + +/* Loop waiting for */ +static int pull_wait(int gpio, int value) { + int i, j; + /* Timeout time is two seconds */ + for (i = 0; i < 20; i++) { + for (j = 0; j < 100; j++) { + if (!!gpio_get_value(gpio) == !!value ) { + return 0; + } + /* The first loop does not delay, normally the first loop can immediately return the result */ + if (i) { + mdelay(1); + } + } + /* The CPU is released every 100ms */ + schedule(); + } + /* timeout */ + FIRMWARE_DRIVER_DEBUG_ERROR("Error: Wait gpio %d pull to %d failed.\n", gpio, value); + return -1; +} + +/* TDI pull-up */ +static int pull_tdi_up(void) +{ + if (current_fmw_cpld == NULL) { + return -1; + } + gpio_set_value(current_fmw_cpld->tdi, 1); + + /* Wait for the GPIO value to be set successfully */ + return pull_wait(current_fmw_cpld->tdi, 1); +} + +/* TDI pull-down */ +static int pull_tdi_down(void) +{ + if (current_fmw_cpld == NULL) { + return -1; + } + gpio_set_value(current_fmw_cpld->tdi, 0); + + /* Wait for the GPIO value to be set successfully */ + return pull_wait(current_fmw_cpld->tdi, 0); +} + +/* TCK pull-up */ +static int pull_tck_up(void) +{ + if (current_fmw_cpld == NULL) { + return -1; + } + gpio_set_value(current_fmw_cpld->tck, 1); + + /* Wait for the GPIO value to be set successfully */ + return pull_wait(current_fmw_cpld->tck, 1); +} + +/* TCK pull-down */ +static int pull_tck_down(void) +{ + if (current_fmw_cpld == NULL) { + return -1; + } + gpio_set_value(current_fmw_cpld->tck, 0); + + /* Wait for the GPIO value to be set successfully */ + return pull_wait(current_fmw_cpld->tck, 0); +} + +/* TMS pull-up */ +static int pull_tms_up(void) +{ + if (current_fmw_cpld == NULL) { + return -1; + } + gpio_set_value(current_fmw_cpld->tms, 1); + + /* Wait for the GPIO value to be set successfully */ + return pull_wait(current_fmw_cpld->tms, 1); +} + +/* TMS pull-down */ +static int pull_tms_down(void) +{ + if (current_fmw_cpld == NULL) { + return -1; + } + gpio_set_value(current_fmw_cpld->tms, 0); + + /* Wait for the GPIO value to be set successfully */ + return pull_wait(current_fmw_cpld->tms, 0); +} + +/* Read TDO */ +static int read_tdo(void) +{ + if (current_fmw_cpld == NULL) { + return -1; + } + return gpio_get_value(current_fmw_cpld->tdo); +} + +static firmware_cpld_function_t function_fmw_cpld = { + .pull_tdi_up = pull_tdi_up, + .pull_tdi_down = pull_tdi_down, + .pull_tck_up = pull_tck_up, + .pull_tck_down = pull_tck_down, + .pull_tms_up = pull_tms_up, + .pull_tms_down = pull_tms_down, + .read_tdo = read_tdo, + .init_cpld = init_cpld, + .finish_cpld = finish_cpld, +}; + +/* + * TDI_PULL_DOWN + * function: Lower TDI + */ +static int TDI_PULL_DOWN(void) +{ + if ( function_fmw_cpld.pull_tdi_down != NULL) { + return function_fmw_cpld.pull_tdi_down(); + } else { + FIRMWARE_DRIVER_DEBUG_ERROR("NO support TDI_PULL_DOWN.\n"); + return -1; + } +} + +/* + * TDI_PULL_UP + * function: High TDI + */ +static int TDI_PULL_UP(void) +{ + if (function_fmw_cpld.pull_tdi_up != NULL) { + return function_fmw_cpld.pull_tdi_up(); + } else { + FIRMWARE_DRIVER_DEBUG_ERROR("NO support TDI_PULL_UP.\n"); + return -1; + } +} + +/* + * TCK_PULL_DOWN + * function: Lower TCK + */ +static int TCK_PULL_DOWN(void) +{ + if (function_fmw_cpld.pull_tck_down != NULL) { + return function_fmw_cpld.pull_tck_down(); + } else { + FIRMWARE_DRIVER_DEBUG_ERROR("NO support TCK_PULL_DOWN.\n"); + return -1; + } +} + +/* + * TCK_PULL_UP + * function: High TCK + */ +static int TCK_PULL_UP(void) +{ + if (function_fmw_cpld.pull_tck_up != NULL) { + return function_fmw_cpld.pull_tck_up(); + } else { + FIRMWARE_DRIVER_DEBUG_ERROR("NO support TCK_PULL_UP.\n"); + return -1; + } +} + +/* + * TMS_PULL_DOWN + * function: Lower TMS + */ +static int TMS_PULL_DOWN(void) +{ + if (function_fmw_cpld.pull_tms_down != NULL) { + return function_fmw_cpld.pull_tms_down(); + } else { + FIRMWARE_DRIVER_DEBUG_ERROR("NO support TMS_PULL_DOWN.\n"); + return -1; + } +} + +/* + * TMS_PULL_UP + * function: High TMS + */ +static int TMS_PULL_UP(void) +{ + if (function_fmw_cpld.pull_tms_up != NULL) { + return function_fmw_cpld.pull_tms_up(); + } else { + FIRMWARE_DRIVER_DEBUG_ERROR("NO support TMS_PULL_UP.\n"); + return -1; + } +} + +/* + * TDO_READ + * function:Read the TDO level + */ +static int TDO_READ(void) +{ + if (function_fmw_cpld.read_tdo != NULL) { + return function_fmw_cpld.read_tdo(); + } else { + FIRMWARE_DRIVER_DEBUG_ERROR("NO support TDO_READ.\n"); + return -1; + } +} + +/* + * cpld_upgrade_init + * function:Initialize GPIO and CPLD + * return value: success--FIRMWARE_SUCCESS; fail--FIRMWARE_FAILED + */ +static int cpld_upgrade_init(void) +{ + int ret; + + if (function_fmw_cpld.init_cpld != NULL) { + ret = function_fmw_cpld.init_cpld(); + if (ret != FIRMWARE_SUCCESS) { + return ret; + } + } + + return FIRMWARE_SUCCESS; +} + +/* + * cpld_upgrade_finish + * function:Release GPIO and CPLD + * return value: success--FIRMWARE_SUCCESS; fail--FIRMWARE_FAILED + */ +static int cpld_upgrade_finish(void) +{ + int ret; + + if (function_fmw_cpld.finish_cpld != NULL) { + ret = function_fmw_cpld.finish_cpld(); + if (ret != FIRMWARE_SUCCESS) { + return ret; + } + } + + return FIRMWARE_SUCCESS; +} + +/** + * firmware_init_vme + * function: Initialize GPIO, + * @cpld_info: param[in] Information about the device to be written to + */ +int firmware_init_vme(firmware_cpld_t *cpld_info){ + int ret; + set_currrent_cpld_info(cpld_info); + /* Initialize GPIO and CPLD */ + ret = cpld_upgrade_init(); + return ret; +} + +/** + * firmware_finish_vme + * function: Release GPIO + * @cpld_info: param[in] Information about the device to be written to + */ +int firmware_finish_vme(firmware_cpld_t *cpld_info){ + int ret; + set_currrent_cpld_info(cpld_info); + ret = cpld_upgrade_finish(); + return ret; +} + +/** + * fwm_cpld_tdi_op + * function: Operate TDI + * @value: param[in] TDI level */ +int fwm_cpld_tdi_op(int value) +{ + if (value) { + return TDI_PULL_UP(); + } else { + return TDI_PULL_DOWN(); + } +} + +/** + * fwm_cpld_tck_op + * function: Operate TCK + * @value: param[in] TCK level */ +int fwm_cpld_tck_op(int value) +{ + if (value) { + return TCK_PULL_UP(); + } else { + return TCK_PULL_DOWN(); + } +} + +/** + * fwm_cpld_tms_op + * function: Operate TMS + * value: param[in] TMS level */ +int fwm_cpld_tms_op(int value) +{ + if (value) { + return TMS_PULL_UP(); + } else { + return TMS_PULL_DOWN(); + } +} + +/** + * fwm_cpld_tdo_op + * function: Read TDO + */ +int fwm_cpld_tdo_op() +{ + return TDO_READ(); +} diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_ispvme/firmware_ispvme.c b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_ispvme/firmware_ispvme.c new file mode 100644 index 000000000000..e8f75844ae34 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_ispvme/firmware_ispvme.c @@ -0,0 +1,140 @@ +#include +#include +#include + +int g_firmware_driver_debug = 0; +module_param(g_firmware_driver_debug, int, S_IRUGO | S_IWUSR); + +static LIST_HEAD(drv_list); +static LIST_HEAD(dev_list); + +/** + * firmware_driver_register + * function:Registered Device Driver + * @fw_drv:param[in] Driver information + * return value : success--FIRMWARE_SUCCESS; fail--FIRMWARE_FAILED + */ +int firmware_driver_register(firmware_driver_t *fw_drv) +{ + int ret; + + if (fw_drv == NULL) { + return FIRMWARE_FAILED; + } + + ret = platform_driver_register(fw_drv->drv); + if (ret < 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("Error: failed to register firmware upgrade driver \n"); + return FIRMWARE_FAILED; + } + + /* Adds driver information to the driver list */ + list_add(&fw_drv->list, &drv_list); + FIRMWARE_DRIVER_DEBUG_VERBOSE("firmware upgrade driver register sucess \n"); + + return FIRMWARE_SUCCESS; +} + +/** + * firmware_driver_unregister + * function:unregister Device Driver + * @fw_drv:param[in] Driver information + */ +void firmware_driver_unregister(firmware_driver_t *fw_drv) +{ + list_del_init(&fw_drv->list); + platform_driver_unregister(fw_drv->drv); +} + +/* + * firmware_get_device_by_minor + * function: Get device information based on minor + */ +firmware_device_t *firmware_get_device_by_minor(int minor) +{ + firmware_device_t *tmp; + + list_for_each_entry(tmp, &dev_list, list) { + if (tmp->dev.minor == minor) { + return tmp; + } + } + + return NULL; +} + +/** + * firmware_device_register + * function:Registered Driver Device + * @fw_dev: param[in] Driver information + * return value:success--FIRMWARE_SUCCESS; fail--FIRMWARE_FAILED + */ +int firmware_device_register(firmware_device_t *fw_dev) +{ + int ret; + firmware_device_t *tmp; + + if (fw_dev == NULL) { + return FIRMWARE_FAILED; + } + /* Check whether the device file name already exists in the device linked list */ + list_for_each_entry(tmp, &dev_list, list) { + if (strcmp(tmp->name, fw_dev->name) == 0) { + return FIRMWARE_FAILED; + } + } + + /* Registere device */ + ret = misc_register(&fw_dev->dev); + if (ret < 0) { + return FIRMWARE_FAILED; + } + + /* Adds a device to the device list */ + list_add(&fw_dev->list, &dev_list); + + return FIRMWARE_SUCCESS; +} + +/** + * firmware_device_unregister + * function: unregister Driver Device + */ +void firmware_device_unregister(firmware_device_t *fw_dev) +{ + list_del(&fw_dev->list); + misc_deregister(&fw_dev->dev); +} + +static int __init firmware_driver_init(void) +{ + int ret; + + INIT_LIST_HEAD(&drv_list); + INIT_LIST_HEAD(&dev_list); + FIRMWARE_DRIVER_DEBUG_VERBOSE("firmware driver ispvme init.\n"); + ret = firmware_cpld_init(); + if (ret < 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("firmware driver ispvme init failed.\n"); + return FIRMWARE_FAILED; + } + + return FIRMWARE_SUCCESS; +} + +static void __exit firmware_driver_exit(void) +{ + FIRMWARE_DRIVER_DEBUG_VERBOSE("firmware driver ispvme exit.\n"); + firmware_cpld_exit(); + INIT_LIST_HEAD(&drv_list); + INIT_LIST_HEAD(&dev_list); + return; +} + +module_init(firmware_driver_init); +module_exit(firmware_driver_exit); + +MODULE_AUTHOR("support"); +MODULE_DESCRIPTION("Firmware upgrade ispvme driver"); +MODULE_LICENSE("GPL"); +MODULE_VERSION("1.0"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_ispvme/include/firmware_cpld_ispvme.h b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_ispvme/include/firmware_cpld_ispvme.h new file mode 100644 index 000000000000..eb737d3a56ed --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_ispvme/include/firmware_cpld_ispvme.h @@ -0,0 +1,70 @@ +#ifndef __FIRMWARE_CPLD_H__ +#define __FIRMWARE_CPLD_H__ + +#define FIRMWARE_DEV_NAME_LEN 32 +#define FIRMWARE_MAX_CPLD_NUM 16 +#define FIRMWARE_TYPE_LEN 10 +#define FIRMWARE_EN_INFO_MAX 16 +#define FIRMWARE_EN_INFO_BUF 128 + +typedef struct firmware_gpio_jtag_en_s { + uint32_t en_gpio; /* GPIO enable pin */ + uint32_t en_level; /* GPIO enable level */ + int flag; /* init flag; 1-init 0-not init */ +} firmware_gpio_jtag_en_t; + +typedef struct firmware_logic_dev_en_s { + char dev_name[FIRMWARE_DEV_NAME_LEN]; /* Logical device name */ + uint32_t addr; /* Enable register address */ + uint32_t mask; /* mask */ + uint32_t en_val; /* Enable value */ + uint32_t dis_val; /* Disable value*/ + uint32_t width; /* width */ + int flag; /* init flag; 1-init 0-not init */ +} firmware_logic_dev_en_t; + +typedef struct firmware_cpld_s { + char devname[FIRMWARE_DEV_NAME_LEN]; /* Device name */ + char type[FIRMWARE_TYPE_LEN]; /* interface type */ + uint32_t tdi; /* TDI signal corresponding to GPIO pin information */ + uint32_t tck; /* TCK signal corresponding to GPIO pin information */ + uint32_t tms; /* TMS signal corresponding to GPIO pin information */ + uint32_t tdo; /* TDO signal corresponding to GPIO pin information */ + uint32_t chain; /* chain num */ + uint32_t chip_index; /* chip index */ + uint32_t tck_delay; /* Delay time */ + uint32_t gpio_en_info_num; /* GPIO Enable Number */ + firmware_gpio_jtag_en_t gpio_en_info[FIRMWARE_EN_INFO_MAX]; /* GPIO Enable Information */ + uint32_t logic_dev_en_num; /* Register Enable Number */ + firmware_logic_dev_en_t logic_dev_en_info[FIRMWARE_EN_INFO_MAX]; /* Register Enable Information */ +} firmware_cpld_t; + +typedef struct firmware_cpld_function_s{ + int (*pull_tdi_up)(void); /* TDI pull-up */ + int (*pull_tdi_down)(void); /* TDI pull-down */ + int (*pull_tck_up)(void); /* TCK pull-up */ + int (*pull_tck_down)(void); /* TCK pull-down */ + int (*pull_tms_up)(void); /* TMS pull-up */ + int (*pull_tms_down)(void); /* TCK pull-down */ + int (*read_tdo)(void); /* Read TDO */ + int (*init_cpld)(void); /* CPLD upgrade initializes the operation */ + int (*init_chip)(int chain); /* chip initializes the operation */ + int (*finish_chip)(int chain); /* chip completes the operation*/ + int (*finish_cpld)(void); /* CPLD upgrade completes the operation */ + int (*get_version)(int chain, char *ver, int len); /* get version */ +}firmware_cpld_function_t; + +/* operate TDI */ +extern int fwm_cpld_tdi_op(int value); +/* operate TCK */ +extern int fwm_cpld_tck_op(int value); +/* operate TMS */ +extern int fwm_cpld_tms_op(int value); +/* operate TDO */ +extern int fwm_cpld_tdo_op(void); +/* VME upgrade mode completes the operation*/ +extern int firmware_finish_vme(firmware_cpld_t *cpld_info); +/* VME upgrade mode initializes the operation*/ +extern int firmware_init_vme(firmware_cpld_t *cpld_info); + +#endif /* __FIRMWARE_CPLD_H__ */ diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_ispvme/include/firmware_ispvme.h b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_ispvme/include/firmware_ispvme.h new file mode 100644 index 000000000000..39baf3f30717 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_ispvme/include/firmware_ispvme.h @@ -0,0 +1,86 @@ +#ifndef __FIRMWARE_H__ +#define __FIRMWARE_H__ + +#include +#include + +#include + +/* Debug switch level */ +typedef enum { + FIRWMARE_VERBOSE, + FIRWMARE_WARN, + FIRWMARE_ERROR, + FIRWMARE_END, +} firmware_debug_level_t; + +#define FIRMWARE_DRIVER_DEBUG_VERBOSE(fmt, args...) do { \ + if ((g_firmware_driver_debug) & (1U << FIRWMARE_VERBOSE)) { \ + printk(KERN_INFO "[FIRMWARW_DRIVER_ISPVME][VER][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +#define FIRMWARE_DRIVER_DEBUG_ERROR(fmt, args...) do { \ + if ((g_firmware_driver_debug) & (1U << FIRWMARE_ERROR)) { \ + printk(KERN_ERR "[FIRMWARW_DRIVER_ISPVME][ERR][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +#define FIRMWARE_NAME_LEN 48 + +#define FIRMWARE_FAILED (-1) +#define FIRMWARE_SUCCESS 0 + +/* ioctl publi command, the same as "firmware_upgrade\include\firmware_app.h" */ +#define FIRMWARE_COMMON_TYPE 'C' +#define FIRMWARE_GET_CHIPNAME _IOR(FIRMWARE_COMMON_TYPE, 0, char) /* get the chip name */ +#define FIRMWARE_GET_VERSION _IOR(FIRMWARE_COMMON_TYPE, 2, int) /* get version */ + +/* firmware cpld ispvme driver ioctl command, the same as "firmware_upgrade\include\firmware_app.h" */ +#define FIRMWARE_VME_TYPE 'V' +#define FIRMWARE_JTAG_TDI _IOR(FIRMWARE_VME_TYPE, 0, char) +#define FIRMWARE_JTAG_TDO _IOR(FIRMWARE_VME_TYPE, 1, char) +#define FIRMWARE_JTAG_TCK _IOR(FIRMWARE_VME_TYPE, 2, char) +#define FIRMWARE_JTAG_TMS _IOR(FIRMWARE_VME_TYPE, 3, char) +#define FIRMWARE_JTAG_EN _IOR(FIRMWARE_VME_TYPE, 4, char) +#define FIRMWARE_JTAG_INIT _IOR(FIRMWARE_VME_TYPE, 7, char) /* enable upgrade access */ +#define FIRMWARE_JTAG_FINISH _IOR(FIRMWARE_VME_TYPE, 8, char) /* disable upgrade access */ + +typedef struct cmd_info_s { + uint32_t size; + void __user *data; +} cmd_info_t; + +typedef struct firmware_device_s { + struct list_head list; /* device list */ + uint32_t chain; /* chain number */ + char name[FIRMWARE_NAME_LEN]; /* name */ + struct miscdevice dev; /* device */ + void *priv; /* private data */ +} firmware_device_t; + +typedef struct firmware_driver_s { + struct list_head list; /* list */ + char name[FIRMWARE_NAME_LEN]; /* name */ + struct platform_driver *drv; /* driver */ + void *priv; /* private data */ +} firmware_driver_t; + +extern int g_firmware_driver_debug; + +/* Get device information based on minor */ +extern firmware_device_t *firmware_get_device_by_minor(int minor); +/* Registere device */ +extern int firmware_device_register(firmware_device_t *fw_dev); +/* Unregister device */ +extern void firmware_device_unregister(firmware_device_t *fw_dev); +/* Registere driver */ +extern int firmware_driver_register(firmware_driver_t *fw_drv); +/* Unregister driver */ +extern void firmware_driver_unregister(firmware_driver_t *fw_drv); +/* CPLD upgrade initialized */ +extern int firmware_cpld_init(void); +/* CPLD unload function */ +extern void firmware_cpld_exit(void); + +#endif /* end of __FIRMWARE_H__ */ diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_sysfs/Makefile b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_sysfs/Makefile new file mode 100644 index 000000000000..a1d6d2e2ef68 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_sysfs/Makefile @@ -0,0 +1,22 @@ +#include $(top_srcdir)/debian/rules +#KERNELDIR := ${KBUILD_OUTPUT} + +PWD = $(shell pwd) + +EXTRA_CFLAGS:= -I$(M)/include +MAKEFILE_FILE_PATH = $(abspath $(lastword $(MAKEFILE_LIST))) +FIRMWARE_UPGRADE_PATH = $(abspath $(MAKEFILE_FILE_PATH)/../../include) +EXTRA_CFLAGS+= -I$(FIRMWARE_UPGRADE_PATH) +EXTRA_CFLAGS+= -Wall + +firmware_driver_sysfs-objs := firmware.o +firmware_driver_sysfs-objs += firmware_sysfs.o firmware_sysfs_upgrade.o + +#ifndef CONFIG_FRM_PRODUCT_FILE + +$(warning $(firmware_driver_sysfs-objs)) +obj-m := firmware_driver_sysfs.o +all: + $(MAKE) -C $(KERNEL_SRC)/build M=$(PWD) modules + @if [ ! -d $(common_module_dir) ]; then mkdir -p $(common_module_dir) ;fi + cp -p $(PWD)/*.ko $(common_module_dir) diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_sysfs/firmware.c b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_sysfs/firmware.c new file mode 100644 index 000000000000..fec51d6238a6 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_sysfs/firmware.c @@ -0,0 +1,143 @@ +#include +#include +#include + +int g_firmware_driver_debug = 0; +module_param(g_firmware_driver_debug, int, S_IRUGO | S_IWUSR); + +static LIST_HEAD(drv_list); +static LIST_HEAD(dev_list); + +/** + * firmware_driver_register + * function:Registered Device Driver + * @fw_drv:param[in] Driver information + * return value : success--FIRMWARE_SUCCESS; fail--FIRMWARE_FAILED + */ +int firmware_driver_register(firmware_driver_t *fw_drv) +{ + int ret; + + if (fw_drv == NULL) { + FIRMWARE_DRIVER_DEBUG_ERROR("Parameter error.\n"); + return FIRMWARE_FAILED; + } + + ret = platform_driver_register(fw_drv->drv); + if (ret < 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("Error: failed to register firmware upgrade driver \n"); + return FIRMWARE_FAILED; + } + + /* Adds driver information to the driver list */ + list_add(&fw_drv->list, &drv_list); + FIRMWARE_DRIVER_DEBUG_VERBOSE("firmware upgrade driver register sucess \n"); + + return FIRMWARE_SUCCESS; +} + +/** + * firmware_driver_unregister + * function:unregister Device Driver + * @fw_drv:param[in] Driver information + */ +void firmware_driver_unregister(firmware_driver_t *fw_drv) +{ + list_del_init(&fw_drv->list); + platform_driver_unregister(fw_drv->drv); +} + +/* + * firmware_get_device_by_minor + * function: Get device information based on minor + */ +firmware_device_t *firmware_get_device_by_minor(int minor) +{ + firmware_device_t *tmp; + + list_for_each_entry(tmp, &dev_list, list) { + if (tmp->dev.minor == minor) { + return tmp; + } + } + + return NULL; +} + +/** + * firmware_device_register + * function:Registered Driver Device + * @fw_dev: param[in] Driver information + * return value:success--FIRMWARE_SUCCESS; fail--FIRMWARE_FAILED + */ +int firmware_device_register(firmware_device_t *fw_dev) +{ + int ret; + firmware_device_t *tmp; + + if (fw_dev == NULL) { + FIRMWARE_DRIVER_DEBUG_ERROR("Parameter error.\n"); + return FIRMWARE_FAILED; + } + /* Check whether the device file name already exists in the device linked list */ + list_for_each_entry(tmp, &dev_list, list) { + if (strcmp(tmp->name, fw_dev->name) == 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("devie %s already exists.\n", fw_dev->name); + return FIRMWARE_FAILED; + } + } + + ret = misc_register(&fw_dev->dev); + if (ret < 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("register misc error, ret=%d.\n", ret); + return FIRMWARE_FAILED; + } + + /* Adds driver information to the driver list */ + list_add(&fw_dev->list, &dev_list); + + return FIRMWARE_SUCCESS; +} + +/** + * firmware_device_unregister + * function: unregister Driver Device + */ +void firmware_device_unregister(firmware_device_t *fw_dev) +{ + list_del(&fw_dev->list); + misc_deregister(&fw_dev->dev); +} + +static int __init firmware_driver_init(void) +{ + int ret; + + INIT_LIST_HEAD(&drv_list); + INIT_LIST_HEAD(&dev_list); + FIRMWARE_DRIVER_DEBUG_VERBOSE("firmware driver sysfs init.\n"); + ret = firmware_sysfs_init(); + if (ret < 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("firmware driver sysfs init failed.\n"); + return FIRMWARE_FAILED; + } + + return FIRMWARE_SUCCESS; +} + +static void __exit firmware_driver_exit(void) +{ + FIRMWARE_DRIVER_DEBUG_VERBOSE("firmware driver sysfs exit.\n"); + firmware_sysfs_exit(); + INIT_LIST_HEAD(&drv_list); + INIT_LIST_HEAD(&dev_list); + return; +} + +module_init(firmware_driver_init); +module_exit(firmware_driver_exit); + +MODULE_AUTHOR("support"); +MODULE_DESCRIPTION("Firmware upgrade driver"); +MODULE_LICENSE("GPL"); +MODULE_VERSION("1.0"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_sysfs/firmware_sysfs.c b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_sysfs/firmware_sysfs.c new file mode 100644 index 000000000000..a823cdc4f294 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_sysfs/firmware_sysfs.c @@ -0,0 +1,495 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static int firmware_sysfs_open(struct inode *inode, struct file *file) +{ + firmware_device_t *frm_dev; + + FIRMWARE_DRIVER_DEBUG_VERBOSE("Open device.\n"); + frm_dev = firmware_get_device_by_minor(MINOR(inode->i_rdev)); + if (frm_dev == NULL) { + return -ENXIO; + } + file->private_data = frm_dev; + + return FIRMWARE_SUCCESS; +} + +static ssize_t firmware_sysfs_read (struct file *file, char __user *buf, size_t count, + loff_t *offset) +{ + return 0; +} + +static ssize_t firmware_sysfs_write (struct file *file, const char __user *buf, size_t count, + loff_t *offset) +{ + return 0; +} + +static loff_t firmware_sysfs_llseek(struct file *file, loff_t offset, int origin) +{ + return 0; +} + +/* firmware_sysfs_ioctl +* function:ioctl command parsing function +* @file: param[in] device file name +* @cmd: param[in] command +* @arg: param[in] the parameters in the command +* return value: success-FIRMWARE_SUCCESS; fail:other value +*/ +static long firmware_sysfs_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + void __user *argp; + firmware_device_t *frm_dev; + firmware_sysfs_t *sysfs_info; + int ret; + + /* Get device private data */ + frm_dev = (firmware_device_t *)file->private_data; + sysfs_info = NULL; + if (frm_dev != NULL) { + if (frm_dev->priv != NULL) { + sysfs_info = (firmware_sysfs_t *)frm_dev->priv; + } + } + if (sysfs_info == NULL) { + FIRMWARE_DRIVER_DEBUG_ERROR("Error: Failed to frm_dev->priv sysfs info.\n"); + return FIRMWARE_FAILED; + } + argp = (void __user *)arg; + + switch (cmd) { + case FIRMWARE_SYSFS_INIT: + /* enable upgrade access */ + ret = firmware_init_dev_loc(sysfs_info); + if (ret != FIRMWARE_SUCCESS) { + FIRMWARE_DRIVER_DEBUG_ERROR("Error: Failed to init upgrade.(chain = %d)\n", + frm_dev != NULL ? frm_dev->chain : -1); + return FIRMWARE_FAILED; + } + break; + case FIRMWARE_SYSFS_FINISH: + /* disable upgrade access */ + ret = firmware_finish_dev_loc(sysfs_info); + if (ret != FIRMWARE_SUCCESS) { + FIRMWARE_DRIVER_DEBUG_ERROR("Error: Failed to release upgrade.(chain = %d)\n", + frm_dev != NULL ? frm_dev->chain : -1); + return FIRMWARE_FAILED; + } + break; + case FIRMWARE_SYSFS_SPI_INFO: + /* Get SPI logic device information */ + if (copy_to_user(argp, &sysfs_info->info.spi_logic_info, sizeof(firmware_spi_logic_info_t))) { + return -EFAULT; + } + break; + case FIRMWARE_SYSFS_DEV_FILE_INFO: + /*Get logic device information */ + if (copy_to_user(argp, &sysfs_info->info.dev_file_info, sizeof(firmware_dev_file_info_t))) { + return -EFAULT; + } + break; + case FIRMWARE_SYSFS_MTD_INFO: + /*Get logic device information */ + if (copy_to_user(argp, &sysfs_info->info.mtd_info, sizeof(firmware_mtd_info_t))) { + return -EFAULT; + } + break; + default: + FIRMWARE_DRIVER_DEBUG_ERROR("not find cmd: %d\r\n", cmd); + return -ENOTTY; + } /* End of switch */ + + return FIRMWARE_SUCCESS; +} + +static int firmware_sysfs_release(struct inode *inode, struct file *file) +{ + return 0; +} + +static const struct file_operations sysfs_dev_fops = { + .owner = THIS_MODULE, + .llseek = firmware_sysfs_llseek, + .read = firmware_sysfs_read, + .write = firmware_sysfs_write, + .unlocked_ioctl = firmware_sysfs_ioctl, + .open = firmware_sysfs_open, + .release = firmware_sysfs_release, +}; + +/* Gets the information in the device tree */ +static int of_firmware_upgrade_config_init(struct device *dev, firmware_sysfs_t *sysfs_info) +{ + int ret; + char *name; + int8_t buf[64]; + int i; + firmware_logic_dev_en_t *firmware_logic_dev_en_point; + uint32_t test_base, test_size; + + FIRMWARE_DRIVER_DEBUG_VERBOSE("Enter firmware_dev_loc_config_init\r\n"); + if (sysfs_info == NULL) { + FIRMWARE_DRIVER_DEBUG_ERROR("info is null\r\n"); + return -1; + } + + mem_clear(sysfs_info, sizeof(firmware_sysfs_t)); + ret = 0; + ret += of_property_read_string(dev->of_node, "type", (const char **)&name); + + ret += of_property_read_u32(dev->of_node, "chain", &sysfs_info->chain); + ret += of_property_read_u32(dev->of_node, "chip_index", &sysfs_info->chip_index); + if (ret != 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("dts config error, ret:%d.\n", ret); + return -ENXIO; + } + strncpy(sysfs_info->type, name, sizeof(sysfs_info->type) - 1); + + ret = of_property_read_u32(dev->of_node, "test_base", &test_base); + if (ret != 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("dts config test_base, ret:%d.\n", ret); + test_base = 0; + } + + ret = of_property_read_u32(dev->of_node, "test_size", &test_size); + if (ret != 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("dts config test_size, ret:%d.\n", ret); + test_size = 0; + } + + if (strcmp(sysfs_info->type, FIRMWARE_SYSFS_TYPE_SPI_LOGIC) == 0) { + ret = of_property_read_string(dev->of_node, "dev_name", (const char **)&name); + if (ret != 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("dts config dev_name error, ret:%d.\n", ret); + return -ENXIO; + } + strncpy(sysfs_info->info.spi_logic_info.dev_name, name, FIRMWARE_DEV_NAME_LEN - 1); + + ret = of_property_read_u32(dev->of_node, "flash_base", &sysfs_info->info.spi_logic_info.flash_base); + if (ret != 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("dts config flash_base error, ret:%d.\n", ret); + return -ENXIO; + } + + ret = of_property_read_u32(dev->of_node, "ctrl_base", &sysfs_info->info.spi_logic_info.ctrl_base); + if (ret != 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("dts config ctrl_base error, ret:%d.\n", ret); + return -ENXIO; + } + sysfs_info->info.spi_logic_info.test_base = test_base; + sysfs_info->info.spi_logic_info.test_size = test_size; + } else if (strcmp(sysfs_info->type, FIRMWARE_SYSFS_TYPE_SYSFS) == 0) { + ret = of_property_read_string(dev->of_node, "sysfs_name", (const char **)&name); + if (ret != 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("dts config sysfs_name error, ret:%d.\n", ret); + return -ENXIO; + } + strncpy(sysfs_info->info.dev_file_info.sysfs_name, name, FIRMWARE_DEV_NAME_LEN - 1); + + ret = of_property_read_u32(dev->of_node, "dev_base", &sysfs_info->info.dev_file_info.dev_base); + if (ret != 0) { + FIRMWARE_DRIVER_DEBUG_VERBOSE("dts don't config dev_base, dev_base is 0.\n"); + sysfs_info->info.dev_file_info.dev_base = 0; + } + + ret = of_property_read_u32(dev->of_node, "per_len", &sysfs_info->info.dev_file_info.per_len); + if (ret != 0) { + FIRMWARE_DRIVER_DEBUG_VERBOSE("dts don't config per_len, per_len is 0.\n"); + sysfs_info->info.dev_file_info.per_len = 0; + } + sysfs_info->info.dev_file_info.test_base = test_base; + sysfs_info->info.dev_file_info.test_size = test_size; + } else if (strcmp(sysfs_info->type, FIRMWARE_SYSFS_TYPE_MTD) == 0) { + ret = of_property_read_string(dev->of_node, "mtd_name", (const char **)&name); + if (ret != 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("dts config mtd_name error, ret:%d.\n", ret); + return -ENXIO; + } + strncpy(sysfs_info->info.mtd_info.mtd_name, name, FIRMWARE_DEV_NAME_LEN - 1); + + ret = of_property_read_u32(dev->of_node, "flash_base", &sysfs_info->info.mtd_info.flash_base); + if (ret != 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("dts config flash_base error, ret:%d.\n", ret); + return -ENXIO; + } + sysfs_info->info.mtd_info.test_base = test_base; + sysfs_info->info.mtd_info.test_size = test_size; + } else { + FIRMWARE_DRIVER_DEBUG_ERROR("dts config sysfs type[%s] is not support, ret:%d.\n", sysfs_info->type, ret); + return -ENXIO; + } + + sysfs_info->gpio_en_info_num = 0; + /* Enable through GPIO */ + for (i = 0; i < FIRMWARE_EN_INFO_MAX; i++) { + mem_clear(buf, sizeof(buf)); + snprintf(buf, sizeof(buf) - 1, "en_gpio_%d", i); + ret = of_property_read_u32(dev->of_node, buf, &sysfs_info->gpio_en_info[i].en_gpio); + if(ret != 0) { + break; + } + + mem_clear(buf, sizeof(buf)); + snprintf(buf, sizeof(buf) - 1, "en_level_%d", i); + ret = of_property_read_u32(dev->of_node, buf, &sysfs_info->gpio_en_info[i].en_level); + if(ret != 0) { + break; + } + sysfs_info->gpio_en_info_num++; + } + + sysfs_info->logic_dev_en_num = 0; + /* Enable through register */ + for (i = 0; i < FIRMWARE_EN_INFO_MAX; i++) { + firmware_logic_dev_en_point = &sysfs_info->logic_dev_en_info[i]; + mem_clear(buf, sizeof(buf)); + snprintf(buf, sizeof(buf) - 1, "en_logic_dev_%d", i); + ret = 0; + ret += of_property_read_string(dev->of_node, buf, (const char **)&name); + if(ret != 0) { + /* Failure to resolve to EN_LOGIC_DEV means no logical device is enabled. No failure is returned */ + ret = 0; + break; + } + strncpy(firmware_logic_dev_en_point->dev_name, name, FIRMWARE_DEV_NAME_LEN - 1); + + mem_clear(buf, sizeof(buf)); + snprintf(buf, sizeof(buf) - 1, "en_logic_addr_%d", i); + ret = of_property_read_u32(dev->of_node, buf, &firmware_logic_dev_en_point->addr); + if (ret != 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("Failed to config en en_logic_addr_%d ret =%d.\n", i, ret); + break; + } + + mem_clear(buf, sizeof(buf)); + snprintf(buf, sizeof(buf) - 1, "en_logic_mask_%d", i); + ret = of_property_read_u32(dev->of_node, buf, &firmware_logic_dev_en_point->mask); + if (ret != 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("Failed to config en en_logic_mask_%d ret =%d.\n", i, ret); + break; + } + + mem_clear(buf, sizeof(buf)); + snprintf(buf, sizeof(buf) - 1, "en_logic_en_val_%d", i); + ret = of_property_read_u32(dev->of_node, buf, &firmware_logic_dev_en_point->en_val); + if (ret != 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("Failed to config en en_logic_en_val_%d ret =%d.\n", i, ret); + break; + } + + mem_clear(buf, sizeof(buf)); + snprintf(buf, sizeof(buf) - 1, "en_logic_dis_val_%d", i); + ret = of_property_read_u32(dev->of_node, buf, &firmware_logic_dev_en_point->dis_val); + if (ret != 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("Failed to config en en_logic_dis_val_%d ret =%d.\n", i, ret); + break; + } + + mem_clear(buf, sizeof(buf)); + snprintf(buf, sizeof(buf) - 1, "en_logic_width_%d", i); + ret = of_property_read_u32(dev->of_node, buf, &firmware_logic_dev_en_point->width); + if (ret != 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("Failed to config en en_logic_width_%d ret =%d.\n", i, ret); + break; + } + + sysfs_info->logic_dev_en_num++; + } + + return ret; +} + +static int firmware_upgrade_config_init(struct device *dev, firmware_sysfs_t *sysfs_info) +{ + int i; + firmware_logic_dev_en_t *firmware_logic_dev_en_point; + firmware_upgrade_device_t *firmware_upgrade_device; + firmware_sysfs_device_t sysfs_upg_device; + + FIRMWARE_DRIVER_DEBUG_VERBOSE("Enter firmware_dev_loc_config_init\r\n"); + if (sysfs_info == NULL) { + FIRMWARE_DRIVER_DEBUG_ERROR("info is null\r\n"); + return -1; + } + + if (dev->platform_data == NULL) { + FIRMWARE_DRIVER_DEBUG_ERROR("platform data config error.\n"); + return -1; + } + firmware_upgrade_device = dev->platform_data; + sysfs_upg_device = firmware_upgrade_device->upg_type.sysfs; + + mem_clear(sysfs_info, sizeof(firmware_sysfs_t)); + strncpy(sysfs_info->type, firmware_upgrade_device->type, sizeof(sysfs_info->type) - 1); + sysfs_info->chain = firmware_upgrade_device->chain; + sysfs_info->chip_index = firmware_upgrade_device->chip_index; + + if (strcmp(sysfs_info->type, FIRMWARE_SYSFS_TYPE_SPI_LOGIC) == 0) { + strncpy(sysfs_info->info.spi_logic_info.dev_name, sysfs_upg_device.dev_name, FIRMWARE_DEV_NAME_LEN - 1); + sysfs_info->info.spi_logic_info.flash_base = sysfs_upg_device.flash_base; + sysfs_info->info.spi_logic_info.ctrl_base = sysfs_upg_device.ctrl_base; + sysfs_info->info.spi_logic_info.test_base = sysfs_upg_device.test_base; + sysfs_info->info.spi_logic_info.test_size = sysfs_upg_device.test_size; + } else if (strcmp(sysfs_info->type, FIRMWARE_SYSFS_TYPE_SYSFS) == 0) { + strncpy(sysfs_info->info.dev_file_info.sysfs_name, sysfs_upg_device.sysfs_name, FIRMWARE_DEV_NAME_LEN - 1); + sysfs_info->info.dev_file_info.dev_base = sysfs_upg_device.dev_base; + sysfs_info->info.dev_file_info.per_len = sysfs_upg_device.per_len; + sysfs_info->info.dev_file_info.test_base = sysfs_upg_device.test_base; + sysfs_info->info.dev_file_info.test_size = sysfs_upg_device.test_size; + } else if (strcmp(sysfs_info->type, FIRMWARE_SYSFS_TYPE_MTD) == 0) { + strncpy(sysfs_info->info.mtd_info.mtd_name, sysfs_upg_device.mtd_name, FIRMWARE_DEV_NAME_LEN - 1); + sysfs_info->info.mtd_info.flash_base = sysfs_upg_device.flash_base; + sysfs_info->info.mtd_info.test_base = sysfs_upg_device.test_base; + sysfs_info->info.mtd_info.test_size = sysfs_upg_device.test_size; + } else { + FIRMWARE_DRIVER_DEBUG_ERROR("config sysfs type[%s] is not support.\n", sysfs_info->type); + return -ENXIO; + } + + if (firmware_upgrade_device->en_gpio_num > FIRMWARE_EN_INFO_MAX) { + FIRMWARE_DRIVER_DEBUG_ERROR("The number of en_gpio_num:%u configurations exceeds the maximum limit:%u.\n", + firmware_upgrade_device->en_gpio_num, FIRMWARE_EN_INFO_MAX); + return -ENXIO; + } + sysfs_info->gpio_en_info_num = firmware_upgrade_device->en_gpio_num; + /* Enable through GPIO */ + for (i = 0; i < sysfs_info->gpio_en_info_num; i++) { + sysfs_info->gpio_en_info[i].en_gpio = firmware_upgrade_device->en_gpio[i]; + sysfs_info->gpio_en_info[i].en_level = firmware_upgrade_device->en_level[i]; + } + + if (firmware_upgrade_device->en_logic_num > FIRMWARE_EN_INFO_MAX) { + FIRMWARE_DRIVER_DEBUG_ERROR("The number of en_logic_num:%u configurations exceeds the maximum limit:%u.\n", + firmware_upgrade_device->en_logic_num, FIRMWARE_EN_INFO_MAX); + return -ENXIO; + } + sysfs_info->logic_dev_en_num = firmware_upgrade_device->en_logic_num; + /* Enable through register */ + for (i = 0; i < sysfs_info->logic_dev_en_num; i++) { + firmware_logic_dev_en_point = &sysfs_info->logic_dev_en_info[i]; + strncpy(firmware_logic_dev_en_point->dev_name, firmware_upgrade_device->en_logic_dev[i], FIRMWARE_DEV_NAME_LEN - 1); + firmware_logic_dev_en_point->addr = firmware_upgrade_device->en_logic_addr[i]; + firmware_logic_dev_en_point->mask = firmware_upgrade_device->en_logic_mask[i]; + firmware_logic_dev_en_point->en_val = firmware_upgrade_device->en_logic_en_val[i]; + firmware_logic_dev_en_point->dis_val = firmware_upgrade_device->en_logic_dis_val[i]; + firmware_logic_dev_en_point->width = firmware_upgrade_device->en_logic_width[i]; + } + + return 0; +} + +static int firmware_sysfs_probe(struct platform_device *pdev) +{ + int ret; + firmware_sysfs_t *sysfs_info; + firmware_device_t *frm_dev; + + FIRMWARE_DRIVER_DEBUG_VERBOSE("Enter firmware_sysfs_probe\r\n"); + sysfs_info = devm_kzalloc(&pdev->dev, sizeof(firmware_sysfs_t), GFP_KERNEL); + if (sysfs_info == NULL) { + FIRMWARE_DRIVER_DEBUG_ERROR("Failed to kzalloc device tree.\n"); + return -EPERM; + } + + if (pdev->dev.of_node) { + ret = of_firmware_upgrade_config_init(&pdev->dev, sysfs_info); + } else { + ret = firmware_upgrade_config_init(&pdev->dev, sysfs_info); + } + if (ret < 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("get config init from dts error.\n"); + return -EPERM; + } + + frm_dev = devm_kzalloc(&pdev->dev, sizeof(firmware_device_t), GFP_KERNEL); + if (frm_dev == NULL) { + FIRMWARE_DRIVER_DEBUG_ERROR("Failed to kzalloc firmware device.\n"); + return -EPERM; + } + + /* Based on the link number, determine the name of the device file */ + frm_dev->chain = sysfs_info->chain; + snprintf(frm_dev->name, FIRMWARE_NAME_LEN - 1, "firmware_sysfs%d", frm_dev->chain); + strncpy(sysfs_info->devname, frm_dev->name, strlen(frm_dev->name) + 1); + + INIT_LIST_HEAD(&frm_dev->list); + frm_dev->dev.minor = MISC_DYNAMIC_MINOR; + frm_dev->dev.name = frm_dev->name; + frm_dev->dev.fops = &sysfs_dev_fops; + frm_dev->priv = sysfs_info; + + FIRMWARE_DRIVER_DEBUG_VERBOSE("Register sysfs firmware chain:%d, name:%s.\n", frm_dev->chain, frm_dev->name); + + ret = firmware_device_register(frm_dev); + if (ret < 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("Failed to register firmware device.\n"); + return -EPERM; + } + + platform_set_drvdata(pdev, frm_dev); + return 0; +} + +static int __exit firmware_sysfs_remove(struct platform_device *pdev) +{ + firmware_device_t *frm_dev; + + frm_dev = (firmware_device_t *)platform_get_drvdata(pdev); + firmware_device_unregister(frm_dev); + platform_set_drvdata(pdev, NULL); + + return 0; +} + +static struct of_device_id sysfs_match[] = { + { + .compatible = "firmware_sysfs", + }, + {}, +}; + +static struct platform_driver sysfs_driver = { + .driver = { + .name = "firmware_sysfs", + .owner = THIS_MODULE, + .of_match_table = sysfs_match, + }, + .probe = firmware_sysfs_probe, + .remove = firmware_sysfs_remove, +}; + +static firmware_driver_t fmw_drv_sysfs = { + .name = "firmware_sysfs", + .drv = &sysfs_driver, +}; + +int firmware_sysfs_init(void) +{ + int ret; + + INIT_LIST_HEAD(&fmw_drv_sysfs.list); + FIRMWARE_DRIVER_DEBUG_VERBOSE("sysfs upgrade driver register \n"); + ret = firmware_driver_register(&fmw_drv_sysfs); + if (ret < 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("sysfs upgrade driver register failed\n"); + return ret; + } + return 0; +} + +void firmware_sysfs_exit(void) +{ + firmware_driver_unregister(&fmw_drv_sysfs); + INIT_LIST_HEAD(&fmw_drv_sysfs.list); +} diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_sysfs/firmware_sysfs_upgrade.c b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_sysfs/firmware_sysfs_upgrade.c new file mode 100644 index 000000000000..8b883006de53 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_sysfs/firmware_sysfs_upgrade.c @@ -0,0 +1,258 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static int firmware_file_read(const char *path, uint32_t addr, uint8_t *val, size_t size) +{ + int ret; + struct file *filp; + loff_t pos; + + filp = filp_open(path, O_RDONLY, 0); + if (IS_ERR(filp)) { + FIRMWARE_DRIVER_DEBUG_ERROR("read open failed errno = %ld\r\n", -PTR_ERR(filp)); + filp = NULL; + goto exit; + } + + pos = (loff_t)addr; + ret = kernel_read(filp, val, size, &pos); + if (ret != size) { + FIRMWARE_DRIVER_DEBUG_ERROR("read kernel_read failed, path=%s, addr=%d, size=%ld, ret=%d\r\n", path, addr, size, ret); + goto exit; + } + filp_close(filp, NULL); + + return ret; + +exit: + if (filp != NULL) { + filp_close(filp, NULL); + } + + return -1; +} + +static int firmware_file_write(const char *path, uint32_t addr, uint8_t *val, size_t size) +{ + int ret; + struct file *filp; + loff_t pos; + + filp = filp_open(path, O_RDWR, 777); + if (IS_ERR(filp)) { + FIRMWARE_DRIVER_DEBUG_ERROR("write open failed errno = %ld\r\n", -PTR_ERR(filp)); + filp = NULL; + goto exit; + } + + pos = (loff_t)addr; + ret = kernel_write(filp, (void*)val, size, &pos); + if (ret < 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("write kernel_write failed, path=%s, addr=%d, size=%ld, ret=%d\r\n", path, addr, size, ret); + goto exit; + } + vfs_fsync(filp, 1); + filp_close(filp, NULL); + + return ret; + +exit: + if (filp != NULL) { + filp_close(filp, NULL); + } + + return -1; +} + +/* + * firmware_file_do_work + * function: Sets logical register values + * @path:param[in] Logic device descriptor + * @addr:param[in] Logic device address + * @value:param[in] the register value needs to be set + * @mask:param[in] register mask + * @width:param[in] register bit width + * return: 0:success, <0:failed + */ +static int firmware_file_do_work(char *path, uint32_t addr, uint32_t value, uint32_t mask, + int32_t width) +{ + int ret; + uint8_t read_value[4], write_value[4]; + uint8_t tmp_read8, tmp_write8, tmp_mask8; + uint32_t tmp_read32, tmp_write32; + + FIRMWARE_DRIVER_DEBUG_VERBOSE("path=%s, addr=0x%x, value=0x%x mask=0x%x\r\n", path, addr, value, mask); + if ((width > 4) || (width < 0)) { + FIRMWARE_DRIVER_DEBUG_ERROR("width %d is not support.\r\n", width); + return -1; + } + ret = 0; + mem_clear(read_value, sizeof(read_value)); + mem_clear(write_value, sizeof(write_value)); + ret = firmware_file_read(path, addr, read_value, width); + if (ret < 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("firmware sysfs read.\r\n"); + return -1; + } + + switch (width) { + case 1: + tmp_read8 = read_value[0]; + tmp_mask8 = (uint8_t)(mask) & 0xFF; + tmp_write8 = (uint8_t)value & 0xFF; + write_value[0] = (tmp_read8 & tmp_mask8) | tmp_write8; + FIRMWARE_DRIVER_DEBUG_VERBOSE("1 byte write val[0]:0x%x", write_value[0]); + break; + case 2: + FIRMWARE_DRIVER_DEBUG_ERROR("width %d is not support.\r\n", width); + return -1; + case 4: + memcpy((uint8_t *)&tmp_read32, read_value, 4); + tmp_write32 = (tmp_read32 & mask) | value; + memcpy(write_value, (uint8_t *)&tmp_write32, 4); + FIRMWARE_DRIVER_DEBUG_VERBOSE("4 byte write val[0]:0x%x, val[1]:0x%x, val[2]:0x%x, val[3]:0x%x", + write_value[0], write_value[1], write_value[2], write_value[3]); + break; + default: + FIRMWARE_DRIVER_DEBUG_ERROR("width %d is not support.\r\n", width); + return -1; + } + + FIRMWARE_DRIVER_DEBUG_VERBOSE("write logic dev[%s] addr[0x%x].\r\n", path, addr); + ret = firmware_file_write(path, addr, write_value, width); + if (ret < 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("firmware_file_write %s addr 0x%x failed, ret=%d.\r\n", path, addr, ret); + return -1; + } + + return 0; +} + +/* + * firmware_upgrade_en + * function:param[in] Upgrade access enabling switch + * @flag:param[in] !0:enable 0:disable + * return: 0:success, <0:failed + */ +static int firmware_upgrade_en(firmware_sysfs_t *sysfs_info, int flag) +{ + int i; + firmware_logic_dev_en_t *firmware_logic_dev_en_info; + int ret, rv; + char *dev_name; + + ret = 0; + FIRMWARE_DRIVER_DEBUG_VERBOSE("%s en switch: gpio en num %d, logic reg en num %d.\n", + flag ? "Open" : "Close", sysfs_info->gpio_en_info_num, sysfs_info->logic_dev_en_num); + for (i = 0; i < sysfs_info->gpio_en_info_num; i++) { + FIRMWARE_DRIVER_DEBUG_VERBOSE("firmware sysfs [%d] gpio[%d] en_level[%d]\n", + i, sysfs_info->gpio_en_info[i].en_gpio, sysfs_info->gpio_en_info[i].en_level); + if (flag) { + ret = gpio_request(sysfs_info->gpio_en_info[i].en_gpio, "sysfs_upgrade_gpio_en"); + if (ret) { + FIRMWARE_DRIVER_DEBUG_ERROR("Requesting cpld_ispvme_upgrade EN[%d] GPIO[%d] failed!\n", + i, sysfs_info->gpio_en_info[i].en_gpio); + goto free_gpio; + } + gpio_direction_output(sysfs_info->gpio_en_info[i].en_gpio, sysfs_info->gpio_en_info[i].en_level); + sysfs_info->gpio_en_info[i].flag = 1; + } else { + gpio_set_value(sysfs_info->gpio_en_info[i].en_gpio, !sysfs_info->gpio_en_info[i].en_level); + gpio_free(sysfs_info->gpio_en_info[i].en_gpio); + sysfs_info->gpio_en_info[i].flag = 0; + } + } + + for (i = 0; i < sysfs_info->logic_dev_en_num; i++) { + firmware_logic_dev_en_info = &sysfs_info->logic_dev_en_info[i]; + dev_name = firmware_logic_dev_en_info->dev_name; + FIRMWARE_DRIVER_DEBUG_VERBOSE("firmware sysfs [%d] dev_name[%s] addr[0x%x] mask[0x%x]" + " en_val[0x%x] dis_val[0x%x] width[%d]\n", + i , firmware_logic_dev_en_info->dev_name, firmware_logic_dev_en_info->addr, + firmware_logic_dev_en_info->mask, firmware_logic_dev_en_info->en_val, + firmware_logic_dev_en_info->dis_val, firmware_logic_dev_en_info->width); + if (flag) { + ret = firmware_file_do_work(dev_name, firmware_logic_dev_en_info->addr, + firmware_logic_dev_en_info->en_val, firmware_logic_dev_en_info->mask, + firmware_logic_dev_en_info->width); + if (ret < 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("Open logic register [%d] EN failed, ret %d.\n", i, ret); + goto free_logic_dev; + } else { + firmware_logic_dev_en_info->flag = 1; + } + } else { + rv = firmware_file_do_work(dev_name, firmware_logic_dev_en_info->addr, + firmware_logic_dev_en_info->dis_val, firmware_logic_dev_en_info->mask, + firmware_logic_dev_en_info->width); + if (rv < 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("Close logic register [%d] EN failed, ret %d.\n", i, rv); + ret = -1; + } + firmware_logic_dev_en_info->flag = 0; + } + } + + return ret; +free_logic_dev: + for (i = 0; i < sysfs_info->logic_dev_en_num; i++) { + firmware_logic_dev_en_info = &sysfs_info->logic_dev_en_info[i]; + dev_name = firmware_logic_dev_en_info->dev_name; + if (firmware_logic_dev_en_info->flag == 1) { + ret = firmware_file_do_work(dev_name, firmware_logic_dev_en_info->addr, + firmware_logic_dev_en_info->dis_val, firmware_logic_dev_en_info->mask, + firmware_logic_dev_en_info->width); + if (ret < 0) { + FIRMWARE_DRIVER_DEBUG_ERROR("Close logic register [%d] EN failed, ret %d.\n", i, ret); + } + firmware_logic_dev_en_info->flag = 0; + } else { + break; + } + } +free_gpio: + for (i = 0; i < sysfs_info->gpio_en_info_num; i++) { + if (sysfs_info->gpio_en_info[i].flag == 1) { + gpio_set_value(sysfs_info->gpio_en_info[i].en_gpio, !sysfs_info->gpio_en_info[i].en_level); + gpio_free(sysfs_info->gpio_en_info[i].en_gpio); + sysfs_info->gpio_en_info[i].flag = 0; + } else { + break; + } + } + + return -1; +} + +/* + * firmware_init_dev_loc + * function: init logic device, enable upgrade access + * return: 0:success, <0:failed + */ +int firmware_init_dev_loc(firmware_sysfs_t *sysfs_info) +{ + int ret; + + ret = firmware_upgrade_en(sysfs_info, 1); + return ret; +} + +/* + * firmware_finish_dev_loc + * function: finish logic device, disable upgrade access + * return: 0:success, <0:failed + */ +int firmware_finish_dev_loc(firmware_sysfs_t *sysfs_info){ + int ret; + ret = firmware_upgrade_en(sysfs_info, 0); + return ret; +} diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_sysfs/include/firmware_sysfs.h b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_sysfs/include/firmware_sysfs.h new file mode 100644 index 000000000000..9da2303c7c00 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_sysfs/include/firmware_sysfs.h @@ -0,0 +1,88 @@ +#ifndef __FIRMWARE_SYSFS_H__ +#define __FIRMWARE_SYSFS_H__ + +#include +#include + +#include + +/* Debug switch level */ +typedef enum { + FIRWMARE_VERBOSE, + FIRWMARE_WARN, + FIRWMARE_ERROR, + FIRWMARE_END, +} firmware_debug_level_t; + +#define FIRMWARE_DRIVER_DEBUG_VERBOSE(fmt, args...) do { \ + if ((g_firmware_driver_debug) & (1U << FIRWMARE_VERBOSE)) { \ + printk(KERN_INFO "[FIRMWARW_DRIVER_SYSFS][VER][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +#define FIRMWARE_DRIVER_DEBUG_ERROR(fmt, args...) do { \ + if ((g_firmware_driver_debug) & (1U << FIRWMARE_ERROR)) { \ + printk(KERN_ERR "[FIRMWARW_DRIVER_SYSFS][ERR][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +#define FIRMWARE_NAME_LEN 48 + +#define FIRMWARE_FAILED (-1) +#define FIRMWARE_SUCCESS 0 + +/* ioctl publi command, the same as "firmware_upgrade\include\firmware_app.h" */ +#define FIRMWARE_COMMON_TYPE 'C' +#define FIRMWARE_GET_CHIPNAME _IOR(FIRMWARE_COMMON_TYPE, 0, char) /* get the chip name */ +#define FIRMWARE_GET_VERSION _IOR(FIRMWARE_COMMON_TYPE, 2, int) /* get version */ + +/* firmware sysfs driver ioctl command, the same as "firmware_upgrade\include\firmware_app.h" */ +#define FIRMWARE_SYSFS_TYPE 'S' +#define FIRMWARE_SYSFS_INIT _IOR(FIRMWARE_SYSFS_TYPE, 0, char) /* enable upgrade access */ +#define FIRMWARE_SYSFS_FINISH _IOR(FIRMWARE_SYSFS_TYPE, 1, char) /* disable upgrade access */ +#define FIRMWARE_SYSFS_SPI_INFO _IOR(FIRMWARE_SYSFS_TYPE, 2, char) /* spi flash upgrade */ +#define FIRMWARE_SYSFS_DEV_FILE_INFO _IOR(FIRMWARE_SYSFS_TYPE, 3, char) /* sysfs upgrade */ +#define FIRMWARE_SYSFS_MTD_INFO _IOR(FIRMWARE_SYSFS_TYPE, 4, char) /* sysfs mtd upgrade */ + +#define FIRMWARE_SYSFS_TYPE_SPI_LOGIC "SPI_LOGIC" +#define FIRMWARE_SYSFS_TYPE_SYSFS "SYSFS" +#define FIRMWARE_SYSFS_TYPE_MTD "MTD_DEV" + +typedef struct cmd_info_s { + uint32_t size; + void __user *data; +} cmd_info_t; + +typedef struct firmware_device_s { + struct list_head list; /* device list */ + uint32_t chain; /* chain number */ + char name[FIRMWARE_NAME_LEN]; /* name */ + struct miscdevice dev; /* device */ + void *priv; /* private data */ +} firmware_device_t; + +typedef struct firmware_driver_s { + struct list_head list; /* list */ + char name[FIRMWARE_NAME_LEN]; /* name */ + struct platform_driver *drv; /* driver */ + void *priv; /* private data */ +} firmware_driver_t; + +extern int g_firmware_driver_debug; + +/* Get device information based on minor */ +extern firmware_device_t *firmware_get_device_by_minor(int minor); +/* Registere device */ +extern int firmware_device_register(firmware_device_t *fw_dev); +/* Unregister device */ +extern void firmware_device_unregister(firmware_device_t *fw_dev); +/* Registere driver */ +extern int firmware_driver_register(firmware_driver_t *fw_drv); +/* Unregister driver */ +extern void firmware_driver_unregister(firmware_driver_t *fw_drv); +/* SYSFS upgrade initialized */ +extern int firmware_sysfs_init(void); +/* SYSFS unload function */ +extern void firmware_sysfs_exit(void); + +#endif /* end of __FIRMWARE_SYSFS_H__ */ diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_sysfs/include/firmware_sysfs_upgrade.h b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_sysfs/include/firmware_sysfs_upgrade.h new file mode 100644 index 000000000000..9c6b970274b1 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/firmware_driver_sysfs/include/firmware_sysfs_upgrade.h @@ -0,0 +1,72 @@ +#ifndef __FIRMWARE_SYSFS_UPGRADE_H__ +#define __FIRMWARE_SYSFS_UPGRADE_H__ + +#define FIRMWARE_DEV_NAME_LEN 64 /* the macro definition needs to same as app space define */ +#define FIRMWARE_TYPE_LEN 10 +#define FIRMWARE_EN_INFO_MAX 16 + +typedef struct firmware_spi_logic_info_s { + char dev_name[FIRMWARE_DEV_NAME_LEN]; /* Logical device name */ + uint32_t flash_base; /* Flash Upgrade Address */ + uint32_t ctrl_base; /* SPI upgrade control register base address */ + uint32_t test_base; /* Test flash address */ + uint32_t test_size; /* Test flash size */ +} firmware_spi_logic_info_t; + +typedef struct firmware_dev_file_info_s { + char sysfs_name[FIRMWARE_DEV_NAME_LEN]; /* sysfs name */ + uint32_t dev_base; /* device upgrade base address */ + uint32_t per_len; /* The length of bytes per operation */ + uint32_t test_base; /* Test flash address */ + uint32_t test_size; /* Test flash size */ +} firmware_dev_file_info_t; + +typedef struct firmware_mtd_info_s { + char mtd_name[FIRMWARE_DEV_NAME_LEN]; /* sysfs name */ + uint32_t flash_base; /* Flash Upgrade Address */ + uint32_t test_base; /* Test flash address */ + uint32_t test_size; /* Test flash size */ +} firmware_mtd_info_t; + +typedef struct firmware_gpio_jtag_en_s { + uint32_t en_gpio; /* GPIO enable pin */ + uint32_t en_level; /* GPIO enable level */ + int flag; /* init flag; 1-init 0-not init */ +} firmware_gpio_jtag_en_t; + +typedef struct firmware_logic_dev_en_s { + char dev_name[FIRMWARE_DEV_NAME_LEN]; /* Logical device name */ + uint32_t addr; /* Enable register address */ + uint32_t mask; /* mask */ + uint32_t en_val; /* Enable value */ + uint32_t dis_val; /* Disable value*/ + uint32_t width; /* width */ + int flag; /* init flag; 1-init 0-not init */ +} firmware_logic_dev_en_t; + +typedef struct firmware_sysfs_s { + char devname[FIRMWARE_DEV_NAME_LEN]; /* Device name */ + char type[FIRMWARE_TYPE_LEN]; /* interface type */ + uint32_t chain; /* chain num */ + uint32_t chip_index; /* chip index */ + union { + firmware_spi_logic_info_t spi_logic_info; /* SPI logic Information */ + firmware_dev_file_info_t dev_file_info; /* device file Information */ + firmware_mtd_info_t mtd_info; /* mtd device Information */ + } info; + uint32_t gpio_en_info_num; /* GPIO Enable Number */ + firmware_gpio_jtag_en_t gpio_en_info[FIRMWARE_EN_INFO_MAX]; /* GPIO Enable Information */ + uint32_t logic_dev_en_num; /* Register Enable Number */ + firmware_logic_dev_en_t logic_dev_en_info[FIRMWARE_EN_INFO_MAX]; /* Register Enable Information */ +} firmware_sysfs_t; + +typedef struct firmware_sysfs_function_s{ + int (*init_dev)(void); /* upgrade initializes the operation */ + int (*finish_dev)(void); /* upgrade completes the operation */ +}firmware_sysfs_function_t; + +extern void firmware_set_sysfs_info(firmware_sysfs_t *sysfs_info); +extern int firmware_init_dev_loc(firmware_sysfs_t *sysfs_info); +extern int firmware_finish_dev_loc(firmware_sysfs_t *sysfs_info); + +#endif /* __FIRMWARE_SYSFS_UPGRADE_H__ */ diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/include/firmware_upgrade.h b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/include/firmware_upgrade.h new file mode 100644 index 000000000000..600c69646b1b --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_driver/include/firmware_upgrade.h @@ -0,0 +1,57 @@ +#ifndef __FIRMWARE_UPGRADE_H__ +#define __FIRMWARE_UPGRADE_H__ + +#include + +#define TYPE_LEN (10) +#define DEV_NAME_LEN (64) +#define ENABLE_NUM (16) + +#define mem_clear(data, size) memset((data), 0, (size)) + +typedef struct firmware_jtag_device_s { + uint32_t tdi; + uint32_t tck; + uint32_t tms; + uint32_t tdo; + uint32_t tck_delay; +} firmware_jtag_device_t; + +typedef struct firmware_sysfs_device_s { + uint32_t test_base; + uint32_t test_size; + char dev_name[DEV_NAME_LEN]; + uint32_t flash_base; + uint32_t ctrl_base; + char sysfs_name[DEV_NAME_LEN]; + uint32_t dev_base; + uint32_t per_len; + char mtd_name[DEV_NAME_LEN]; +} firmware_sysfs_device_t; + +typedef struct firmware_upgrade_device_s { + char type[TYPE_LEN]; + uint32_t chain; + uint32_t chip_index; + + uint32_t en_gpio_num; /* the number of en_gpio */ + uint32_t en_gpio[ENABLE_NUM]; + uint32_t en_level[ENABLE_NUM]; + + uint32_t en_logic_num; /* the number of en_logic */ + char en_logic_dev[ENABLE_NUM][DEV_NAME_LEN]; + uint32_t en_logic_addr[ENABLE_NUM]; + uint32_t en_logic_mask[ENABLE_NUM]; + uint32_t en_logic_en_val[ENABLE_NUM]; + uint32_t en_logic_dis_val[ENABLE_NUM]; + uint32_t en_logic_width[ENABLE_NUM]; + + int device_flag; + union { + firmware_jtag_device_t jtag; + firmware_sysfs_device_t sysfs; + } upg_type; + +} firmware_upgrade_device_t; + +#endif diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/Makefile b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/Makefile new file mode 100644 index 000000000000..176d44d2abd9 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/Makefile @@ -0,0 +1,33 @@ +include $(top_srcdir)/Rules.mk + +#OBJ = firmware_app.o debug.o hardware.o ispvm_ui.o ivm_core.o crc32.o +PWD = $(shell pwd) +SRC := +SRC += $(shell find $(PWD) -name '*.c') + +OBJ := $(SRC:%.c=%.o) +LIB += $(BUILD_CFALGS) $(BUILD_LDFLAGS) -lpthread -lreadline -lncurses +INCLUDE = -Iinclude +INCLUDE+= -Wall +APP = firmware_upgrade +ELF_FILE = $(APP) +MAP_FILE = $(APP).map.sym + +.PHONY: build +build:$(OBJ) + $(CC) $^ -o $(ELF_FILE) $(LINKFLAGS) $(LIB) + $(NM) $(ELF_FILE) | grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' \ + | sort > $(MAP_FILE) + cp -p $(ELF_FILE) $(common_out_put_dir) + +%.o:%.c + $(CC) -c $(CFLAGS) $(INCLUDE) $< -o $@ + +.PHONY: install +install: + echo "firmware_upgrade install success." + cp -p $(ELF_FILE) $(common_out_put_dir) + +.PHONY: clean +clean: + rm -rf $(BUILD_DIR) diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/crc32.c b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/crc32.c new file mode 100644 index 000000000000..5b60b40ad1ba --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/crc32.c @@ -0,0 +1,216 @@ +/* + * This file is derived from crc32.c from the zlib-1.1.3 distribution + * by Jean-loup Gailly and Mark Adler. + */ + +/* crc32.c -- compute the CRC-32 of a data stream + * Copyright (C) 1995-1998 Mark Adler + * For conditions of distribution and use, see copyright notice in zlib.h + */ +/* xxxx: by chihl for compile error */ +#if 1 + +#ifndef FAR +#define FAR +#endif + +typedef unsigned char Byte; /* 8 bits */ +typedef unsigned int uInt; /* 16 bits or more */ +typedef unsigned long uLong; /* 32 bits or more */ + +typedef Byte FAR Bytef; +typedef char FAR charf; +typedef int FAR intf; +typedef uInt FAR uIntf; +typedef uLong FAR uLongf; + +#ifndef OF /* function prototypes */ +#ifdef STDC +#define OF(args) args +#else +#define OF(args) () +#endif +#endif + +#endif + +#define local static +#define ZEXPORT /* empty */ +unsigned long crc32 (unsigned long, const unsigned char *, unsigned int); + +#define DYNAMIC_CRC_TABLE + +#ifdef DYNAMIC_CRC_TABLE + +local int crc_table_empty = 1; +local uLongf crc_table[256]; +local void make_crc_table OF((void)); + +/* + Generate a table for a byte-wise 32-bit CRC calculation on the polynomial: + x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1. + + Polynomials over GF(2) are represented in binary, one bit per coefficient, + with the lowest powers in the most significant bit. Then adding polynomials + is just exclusive-or, and multiplying a polynomial by x is a right shift by + one. If we call the above polynomial p, and represent a byte as the + polynomial q, also with the lowest power in the most significant bit (so the + byte 0xb1 is the polynomial x^7+x^3+x+1), then the CRC is (q*x^32) mod p, + where a mod b means the remainder after dividing a by b. + + This calculation is done using the shift-register method of multiplying and + taking the remainder. The register is initialized to zero, and for each + incoming bit, x^32 is added mod p to the register if the bit is a one (where + x^32 mod p is p+x^32 = x^26+...+1), and the register is multiplied mod p by + x (which is shifting right by one and adding x^32 mod p if the bit shifted + out is a one). We start with the highest power (least significant bit) of + q and repeat for all eight bits of q. + + The table is simply the CRC of all possible eight bit values. This is all + the information needed to generate CRC's on data a byte at a time for all + combinations of CRC register values and incoming bytes. +*/ +local void make_crc_table() +{ + uLong c; + int n, k; + uLong poly; /* polynomial exclusive-or pattern */ + /* terms of polynomial defining this crc (except x^32): */ + static const Byte p[] = {0,1,2,4,5,7,8,10,11,12,16,22,23,26}; + + /* make exclusive-or pattern from polynomial (0xedb88320L) */ + poly = 0L; + for (n = 0; n < sizeof(p)/sizeof(Byte); n++) + poly |= 1L << (31 - p[n]); + + for (n = 0; n < 256; n++) + { + c = (uLong)n; + for (k = 0; k < 8; k++) + c = c & 1 ? poly ^ (c >> 1) : c >> 1; + crc_table[n] = c; + } + crc_table_empty = 0; +} +#else +/* ======================================================================== + * Table of CRC-32's of all single-byte values (made by make_crc_table) + */ +local const uLongf crc_table[256] = { + 0x00000000L, 0x77073096L, 0xee0e612cL, 0x990951baL, 0x076dc419L, + 0x706af48fL, 0xe963a535L, 0x9e6495a3L, 0x0edb8832L, 0x79dcb8a4L, + 0xe0d5e91eL, 0x97d2d988L, 0x09b64c2bL, 0x7eb17cbdL, 0xe7b82d07L, + 0x90bf1d91L, 0x1db71064L, 0x6ab020f2L, 0xf3b97148L, 0x84be41deL, + 0x1adad47dL, 0x6ddde4ebL, 0xf4d4b551L, 0x83d385c7L, 0x136c9856L, + 0x646ba8c0L, 0xfd62f97aL, 0x8a65c9ecL, 0x14015c4fL, 0x63066cd9L, + 0xfa0f3d63L, 0x8d080df5L, 0x3b6e20c8L, 0x4c69105eL, 0xd56041e4L, + 0xa2677172L, 0x3c03e4d1L, 0x4b04d447L, 0xd20d85fdL, 0xa50ab56bL, + 0x35b5a8faL, 0x42b2986cL, 0xdbbbc9d6L, 0xacbcf940L, 0x32d86ce3L, + 0x45df5c75L, 0xdcd60dcfL, 0xabd13d59L, 0x26d930acL, 0x51de003aL, + 0xc8d75180L, 0xbfd06116L, 0x21b4f4b5L, 0x56b3c423L, 0xcfba9599L, + 0xb8bda50fL, 0x2802b89eL, 0x5f058808L, 0xc60cd9b2L, 0xb10be924L, + 0x2f6f7c87L, 0x58684c11L, 0xc1611dabL, 0xb6662d3dL, 0x76dc4190L, + 0x01db7106L, 0x98d220bcL, 0xefd5102aL, 0x71b18589L, 0x06b6b51fL, + 0x9fbfe4a5L, 0xe8b8d433L, 0x7807c9a2L, 0x0f00f934L, 0x9609a88eL, + 0xe10e9818L, 0x7f6a0dbbL, 0x086d3d2dL, 0x91646c97L, 0xe6635c01L, + 0x6b6b51f4L, 0x1c6c6162L, 0x856530d8L, 0xf262004eL, 0x6c0695edL, + 0x1b01a57bL, 0x8208f4c1L, 0xf50fc457L, 0x65b0d9c6L, 0x12b7e950L, + 0x8bbeb8eaL, 0xfcb9887cL, 0x62dd1ddfL, 0x15da2d49L, 0x8cd37cf3L, + 0xfbd44c65L, 0x4db26158L, 0x3ab551ceL, 0xa3bc0074L, 0xd4bb30e2L, + 0x4adfa541L, 0x3dd895d7L, 0xa4d1c46dL, 0xd3d6f4fbL, 0x4369e96aL, + 0x346ed9fcL, 0xad678846L, 0xda60b8d0L, 0x44042d73L, 0x33031de5L, + 0xaa0a4c5fL, 0xdd0d7cc9L, 0x5005713cL, 0x270241aaL, 0xbe0b1010L, + 0xc90c2086L, 0x5768b525L, 0x206f85b3L, 0xb966d409L, 0xce61e49fL, + 0x5edef90eL, 0x29d9c998L, 0xb0d09822L, 0xc7d7a8b4L, 0x59b33d17L, + 0x2eb40d81L, 0xb7bd5c3bL, 0xc0ba6cadL, 0xedb88320L, 0x9abfb3b6L, + 0x03b6e20cL, 0x74b1d29aL, 0xead54739L, 0x9dd277afL, 0x04db2615L, + 0x73dc1683L, 0xe3630b12L, 0x94643b84L, 0x0d6d6a3eL, 0x7a6a5aa8L, + 0xe40ecf0bL, 0x9309ff9dL, 0x0a00ae27L, 0x7d079eb1L, 0xf00f9344L, + 0x8708a3d2L, 0x1e01f268L, 0x6906c2feL, 0xf762575dL, 0x806567cbL, + 0x196c3671L, 0x6e6b06e7L, 0xfed41b76L, 0x89d32be0L, 0x10da7a5aL, + 0x67dd4accL, 0xf9b9df6fL, 0x8ebeeff9L, 0x17b7be43L, 0x60b08ed5L, + 0xd6d6a3e8L, 0xa1d1937eL, 0x38d8c2c4L, 0x4fdff252L, 0xd1bb67f1L, + 0xa6bc5767L, 0x3fb506ddL, 0x48b2364bL, 0xd80d2bdaL, 0xaf0a1b4cL, + 0x36034af6L, 0x41047a60L, 0xdf60efc3L, 0xa867df55L, 0x316e8eefL, + 0x4669be79L, 0xcb61b38cL, 0xbc66831aL, 0x256fd2a0L, 0x5268e236L, + 0xcc0c7795L, 0xbb0b4703L, 0x220216b9L, 0x5505262fL, 0xc5ba3bbeL, + 0xb2bd0b28L, 0x2bb45a92L, 0x5cb36a04L, 0xc2d7ffa7L, 0xb5d0cf31L, + 0x2cd99e8bL, 0x5bdeae1dL, 0x9b64c2b0L, 0xec63f226L, 0x756aa39cL, + 0x026d930aL, 0x9c0906a9L, 0xeb0e363fL, 0x72076785L, 0x05005713L, + 0x95bf4a82L, 0xe2b87a14L, 0x7bb12baeL, 0x0cb61b38L, 0x92d28e9bL, + 0xe5d5be0dL, 0x7cdcefb7L, 0x0bdbdf21L, 0x86d3d2d4L, 0xf1d4e242L, + 0x68ddb3f8L, 0x1fda836eL, 0x81be16cdL, 0xf6b9265bL, 0x6fb077e1L, + 0x18b74777L, 0x88085ae6L, 0xff0f6a70L, 0x66063bcaL, 0x11010b5cL, + 0x8f659effL, 0xf862ae69L, 0x616bffd3L, 0x166ccf45L, 0xa00ae278L, + 0xd70dd2eeL, 0x4e048354L, 0x3903b3c2L, 0xa7672661L, 0xd06016f7L, + 0x4969474dL, 0x3e6e77dbL, 0xaed16a4aL, 0xd9d65adcL, 0x40df0b66L, + 0x37d83bf0L, 0xa9bcae53L, 0xdebb9ec5L, 0x47b2cf7fL, 0x30b5ffe9L, + 0xbdbdf21cL, 0xcabac28aL, 0x53b39330L, 0x24b4a3a6L, 0xbad03605L, + 0xcdd70693L, 0x54de5729L, 0x23d967bfL, 0xb3667a2eL, 0xc4614ab8L, + 0x5d681b02L, 0x2a6f2b94L, 0xb40bbe37L, 0xc30c8ea1L, 0x5a05df1bL, + 0x2d02ef8dL +}; +#endif + +#if 0 +/* ========================================================================= + * This function can be used by asm versions of crc32() + */ +const uLongf * ZEXPORT get_crc_table() +{ +#ifdef DYNAMIC_CRC_TABLE + if (crc_table_empty) make_crc_table(); +#endif + return (const uLongf *)crc_table; +} +#endif + +/* ========================================================================= */ +#define DO1(buf) crc = crc_table[((int)crc ^ (*buf++)) & 0xff] ^ (crc >> 8); +#define DO2(buf) DO1(buf); DO1(buf); +#define DO4(buf) DO2(buf); DO2(buf); +#define DO8(buf) DO4(buf); DO4(buf); + +/* ========================================================================= */ +uLong ZEXPORT crc32(uLong crc, const Bytef *buf, uInt len) +{ +#ifdef DYNAMIC_CRC_TABLE + if (crc_table_empty) + make_crc_table(); +#endif + crc = crc ^ 0xffffffffL; + while (len >= 8) + { + DO8(buf); + len -= 8; + } + if (len) do { + DO1(buf); + } while (--len); + return crc ^ 0xffffffffL; +} + +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) + +/* No ones complement version. JFFS2 (and other things ?) + * don't use ones compliment in their CRC calculations. + */ +uLong ZEXPORT crc32_no_comp(uLong crc, const Bytef *buf, uInt len) +{ +#ifdef DYNAMIC_CRC_TABLE + if (crc_table_empty) + make_crc_table(); +#endif + while (len >= 8) + { + DO8(buf); + len -= 8; + } + if (len) do { + DO1(buf); + } while (--len); + + return crc; +} + +#endif /* CFG_CMD_JFFS2 */ diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/debug.c b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/debug.c new file mode 100644 index 000000000000..dc1b1ccfc70a --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/debug.c @@ -0,0 +1,60 @@ +/* + * debug.c + * firmware upgrade debug switch control + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int is_debug_on = DEBUG_IGNORE; + +/* + * firmware_upgrade_debug + * function: Debug switch + * Parses the file "/var/tmp/.firmware_upgrade_debug" and returns the corresponding debug level + * return:off--DEBUG_OFF, app debug on---DEBUG_APP_ON, kernel debug on--DEBUG_KERN_ON, + * all debug on--DEBUG_ALL_ON, other--DEBUG_IGNORE + */ +int firmware_upgrade_debug(void) +{ + int size; + FILE *fp; + char debug_info[DEBUG_INFO_LEN]; + + fp = fopen(DEBUG_FILE, "r"); + if (fp == NULL) { + return DEBUG_IGNORE; + } + + mem_clear(debug_info, DEBUG_INFO_LEN); + size = fread(debug_info, DEBUG_INFO_LEN - 1, 1, fp); + if (size < 0) { + fclose(fp); + return DEBUG_IGNORE; + } + + if (strncmp(debug_info, DEBUG_ON_INFO, 1) == 0) { + fclose(fp); + return DEBUG_APP_ON; + } + + if (strncmp(debug_info, DEBUG_ON_ALL, 1) == 0) { + fclose(fp); + return DEBUG_ALL_ON; + } + + if (strncmp(debug_info, DEBUG_OFF_INFO, 1) == 0) { + fclose(fp); + return DEBUG_OFF; + } + + fclose(fp); + return DEBUG_IGNORE; +} diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/firmware_app.c b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/firmware_app.c new file mode 100644 index 000000000000..ecdc37ef350f --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/firmware_app.c @@ -0,0 +1,985 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int header_offset; + +static firmware_file_name_t firmware_file_str[] = { + {"VME", FIRMWARE_VME}, + {"ISC", FIRMWARE_ISC}, + {"JBI", FIRMWARE_JBI}, + {"SPI-LOGIC-DEV", FIRMWARE_SPI_LOGIC_DEV}, + {"SYSFS", FIRMWARE_SYSFS_DEV}, + {"MTD", FIRMWARE_MTD}, +}; + +/** + * firmware_error_type + * function:set error code + * @action: param[in] The stage where the error occurs + * @info: param[in] Upgrade file information + * return value: error code + */ +int firmware_error_type(int action, name_info_t *info) +{ + if (info == NULL) { + return ERR_FW_UPGRADE; + } + + if((info->type <= FIRMWARE_UNDEF_TYPE) || (info->type > FIRMWARE_OTHER)) { + return ERR_FW_UPGRADE; + } + + if (info->type == FIRMWARE_CPLD) { + switch (action) { + case FIRMWARE_ACTION_CHECK: + return ERR_FW_CHECK_CPLD_UPGRADE; + case FIRMWARE_ACTION_MATCH: + return ERR_FW_MATCH_CPLD_UPGRADE; + case FIRMWARE_ACTION_VERCHECK: + return ERR_FW_SAMEVER_CPLD_UPGRADE; + case FIRMWARE_ACTION_UPGRADE: + return ERR_FW_DO_CPLD_UPGRADE; + case FIRMWARE_ACTION_SUPPORT: + return ERR_FW_DO_UPGRADE_NOT_SUPPORT; + default: + return ERR_FW_UPGRADE; + } + } else if (info->type == FIRMWARE_FPGA) { + switch (action) { + case FIRMWARE_ACTION_CHECK: + return ERR_FW_CHECK_FPGA_UPGRADE; + case FIRMWARE_ACTION_MATCH: + return ERR_FW_MATCH_FPGA_UPGRADE; + case FIRMWARE_ACTION_VERCHECK: + return ERR_FW_SAMEVER_FPGA_UPGRADE; + case FIRMWARE_ACTION_UPGRADE: + return ERR_FW_DO_FPGA_UPGRADE; + case FIRMWARE_ACTION_SUPPORT: + return ERR_FW_DO_UPGRADE_NOT_SUPPORT; + default: + return ERR_FW_UPGRADE; + } + } else { + switch (action) { + case FIRMWARE_ACTION_CHECK: + return ERR_FW_CHECK_UPGRADE; + case FIRMWARE_ACTION_MATCH: + return ERR_FW_MATCH_UPGRADE; + case FIRMWARE_ACTION_VERCHECK: + return ERR_FW_SAMEVER_UPGRADE; + case FIRMWARE_ACTION_UPGRADE: + return ERR_FW_DO_UPGRADE; + case FIRMWARE_ACTION_SUPPORT: + return ERR_FW_DO_UPGRADE_NOT_SUPPORT; + default: + return ERR_FW_UPGRADE; + } + } + +} + +/* + * firmware_check_file_info + * function:Check the file information to determine that the file is available for use on the device + * @info: param[in] Upgrade file information + * @main_type : param[in] main type + * @sub_type : param[in] sub type + * @slot : param[in] 0--main, sub slot starts at 1 + * return value : success--FIRMWARE_SUCCESS, other fail return error code + */ +static int firmware_check_file_info(name_info_t *info, int main_type, int sub_type, int slot) +{ + int i; + + dbg_print(is_debug_on, "Check file info.\n"); + /* Check the mainboard type */ + for (i = 0; i < MAX_DEV_NUM; i++) { + if (main_type == info->card_type[i]) { + dbg_print(is_debug_on, "main type is 0x%x \n", main_type); + break; + } + } + if (i == MAX_DEV_NUM) { + dbg_print(is_debug_on, "Error: The main type[0x%x] is not matched \n", main_type); + return firmware_error_type(FIRMWARE_ACTION_MATCH, info); + } + + /* Check the sub board type, if firwmare upgrade sub board, then sub_type must be 0 */ + for (i = 0; i < MAX_DEV_NUM; i++) { + if (sub_type == info->sub_type[i]) { + dbg_print(is_debug_on, "sub type is 0x%x \n", sub_type); + break; + } + } + if (i == MAX_DEV_NUM) { + dbg_print(is_debug_on, "Error: The sub type[0x%x] is not matched \n", sub_type); + return firmware_error_type(FIRMWARE_ACTION_MATCH, info); + } + + /* if firwmare upgrade main board, then sub_type must be 0 and slot must be 0 + * if firwmare upgrade sub board, then sub_type must not be 0 and slot must not be 0 */ + if (((sub_type != 0) && (slot < 1)) || ((sub_type == 0) && (slot != 0))) { + dbg_print(is_debug_on, "Error: The sub type[0x%x] is not match slot %d error.\n", sub_type, slot); + return firmware_error_type(FIRMWARE_ACTION_MATCH, info); + } + + dbg_print(is_debug_on, "Success check file info.\n"); + + return FIRMWARE_SUCCESS; +} + +/* + * firmware_get_dev_file_name + * function:Gets the name of the device file + * @info: param[in] Upgrade file information + * @len: param[in] Device file name length + * @file_name: param[out] Device file name + */ +static int firmware_get_dev_file_name(name_info_t *info, char *file_name, int len) +{ + int ret; + + ret = FIRMWARE_SUCCESS; + switch(info->file_type) { + case FIRMWARE_VME: + snprintf(file_name, len, "/dev/firmware_cpld_ispvme%d", info->chain); + break; + case FIRMWARE_ISC: + case FIRMWARE_JBI: + snprintf(file_name, len, "/dev/firmware_cpld%d", info->chain); + break; + case FIRMWARE_SPI_LOGIC_DEV: + case FIRMWARE_SYSFS_DEV: + case FIRMWARE_MTD: + snprintf(file_name, len, "/dev/firmware_sysfs%d", info->chain); + break; + default: + ret = FIRMWARE_FAILED; + break; + } + + return ret; + } + +/** + * firmware_check_chip_verison + * function: Check chip version + * @fd: param[in] Device file descriptor + * @info: param[in] Upgrade file information + * return value : success--FIRMWARE_SUCCESS, other fail return error code + */ +int firmware_check_chip_verison(int fd, name_info_t *info) +{ + int ret; + cmd_info_t cmd_info; + char version[FIRMWARE_NAME_LEN + 1]; + + dbg_print(is_debug_on, "Check chip version.\n"); + mem_clear(version, FIRMWARE_NAME_LEN); + cmd_info.size = FIRMWARE_NAME_LEN; + cmd_info.data = (void *) version; + + /* Ignore version checking */ + if (strncmp("v", info->version, 1) == 0) { + dbg_print(is_debug_on, "Skip check chip version.\n"); + return FIRMWARE_SUCCESS; + } + + /* Get the program version from the device file */ + ret = ioctl(fd, FIRMWARE_GET_VERSION, &cmd_info); + if (ret < 0) { + dbg_print(is_debug_on, "Error: Failed to get version(chain %d, version %s).\n", + info->chain, info->version); + return firmware_error_type(FIRMWARE_ACTION_CHECK, NULL); + } + dbg_print(is_debug_on, "Chip verion: %s, file chip verion: %s.\n", version, info->version); + + /* The device version is the same and does not upgrade */ + if (strcmp(version, info->version) == 0) { + dbg_print(is_debug_on, "the file program version is same as the firmware version %s \n", + info->version); + return firmware_error_type(FIRMWARE_ACTION_CHECK, info); + } + dbg_print(is_debug_on, "Check version pass.\n"); + + return FIRMWARE_SUCCESS; +} + +/* + * firmware_get_file_size + * function: Gets the upgrade file size + * @file_name: param[in] Upgrade file name + * @size: param[out] Upgrade file size + * return value : success--FIRMWARE_SUCCESS; fail--FIRMWARE_FAILED + */ +static int firmware_get_file_size(char *file_name, uint32_t *size) +{ + int ret; + struct stat buf; + + ret = stat(file_name, &buf); + if (ret < 0) { + return FIRMWARE_FAILED; + } + + if (buf.st_size < 0 || buf.st_size - header_offset < 0) { + return FIRMWARE_FAILED; + } + /* Remove the upgrade file header information to actually upgrade the content size */ + *size = buf.st_size - header_offset; + + return FIRMWARE_SUCCESS; +} + +/* + * firmware_get_file_info + * function: Gets the contents of the upgrade file + * @file_name: param[in] Upgrade file name + * @size: param[in] Upgrade file size + * @buf: param[out] Upgrade the file content + * return value : success--FIRMWARE_SUCCESS; fail--FIRMWARE_FAILED + */ +static int firmware_get_file_info(char *file_name, uint8_t *buf, uint32_t size) +{ + FILE *fp; + int len; + int ret; + + fp = fopen(file_name, "r"); + if (fp == NULL) { + return FIRMWARE_FAILED; + } + /* Removes the contents of the upgrade file header information */ + ret = fseek(fp, header_offset, SEEK_SET); + if (ret < 0) { + fclose(fp); + return FIRMWARE_FAILED; + } + + len = fread(buf, size, 1, fp); + if (len < 0) { + fclose(fp); + return FIRMWARE_FAILED; + } + fclose(fp); + + return FIRMWARE_SUCCESS; +} + +/* +* firmware_upgrade +* function: firmware upgrade +* @file_name: param[in] Upgrade file name +* @info: param[in] Upgrade file information +* return value : success--FIRMWARE_SUCCESS, other fail return error code +*/ +static int firmware_upgrade(char *file_name, name_info_t *info) +{ + int ret; + int fd; + uint32_t upg_size; + uint8_t *upg_buf; + char dev_file_name[FIRMWARE_NAME_LEN]; + unsigned long crc; + + dbg_print(is_debug_on, "Upgrade firmware: %s.\n", file_name); + mem_clear(dev_file_name, FIRMWARE_NAME_LEN); + ret = firmware_get_dev_file_name(info, dev_file_name, FIRMWARE_NAME_LEN - 1); + if (ret != FIRMWARE_SUCCESS) { + dbg_print(is_debug_on, "Error: Failed to get dev file name.\n"); + return firmware_error_type(FIRMWARE_ACTION_CHECK, info); + } + + fd = open(dev_file_name, O_RDWR); + if (fd < 0) { + dbg_print(is_debug_on, "Error: Failed to open %s.\n", dev_file_name); + return firmware_error_type(FIRMWARE_ACTION_CHECK, info); + } + +#if 0 + /* check chip name */ + ret = firmware_check_chip_name(fd, info); + if (ret != FIRMWARE_SUCCESS) { + dbg_print(is_debug_on, "Error: Failed to check chip name: %s.\n", dev_file_name); + close(fd); + return firmware_error_type(FIRMWARE_ACTION_CHECK, info); + } +#endif + + /* Check chip version */ + ret = firmware_check_chip_verison(fd, info); + if (ret != FIRMWARE_SUCCESS) { + dbg_print(is_debug_on, "Error: Failed to check chip version: %s.\n", dev_file_name); + close(fd); + return firmware_error_type(FIRMWARE_ACTION_CHECK, info); + } + + /* Gets the upgrade file size */ + ret = firmware_get_file_size(file_name, &upg_size); + if (ret != FIRMWARE_SUCCESS) { + dbg_print(is_debug_on, "Error: Failed to get file size: %s.\n", file_name); + close(fd); + return firmware_error_type(FIRMWARE_ACTION_CHECK, info); + } + + if (upg_size == 0) { + dbg_print(is_debug_on, "Error: The upgrade file is empty \n"); + close(fd); + return firmware_error_type(FIRMWARE_ACTION_CHECK, info); + } + + upg_buf = (uint8_t *) malloc(upg_size + 1); + if (upg_buf == NULL) { + dbg_print(is_debug_on, "Error: Failed to malloc memory for upgrade file info: %s.\n", + dev_file_name); + close(fd); + return firmware_error_type(FIRMWARE_ACTION_CHECK, info); + } + + /* Gets the contents of the upgrade file */ + mem_clear(upg_buf, upg_size + 1); + ret = firmware_get_file_info(file_name, upg_buf, upg_size); + if (ret != FIRMWARE_SUCCESS) { + dbg_print(is_debug_on, "Error: Failed to read file info: %s.\n", file_name); + free(upg_buf); + close(fd); + return firmware_error_type(FIRMWARE_ACTION_CHECK, info); + } + + /* file crc32 check */ + crc = crc32(0, (const unsigned char *)upg_buf, (unsigned int)upg_size); + if (crc != info->crc32) { + dbg_print(is_debug_on, "Error: Failed to check file crc: %s.\n", file_name); + dbg_print(is_debug_on, "the crc value is : %#08x.\n", (unsigned int)crc); + free(upg_buf); + close(fd); + return firmware_error_type(FIRMWARE_ACTION_CHECK, info); + } + + dbg_print(is_debug_on, "Start upgrading firmware, wait...\n"); + + /* Start firmware upgrade */ + switch (info->file_type) { + case FIRMWARE_VME: + dbg_print(is_debug_on, "start to ispvme upgrade: %s.\n", file_name); + ret = firmware_upgrade_ispvme(fd, file_name, info); + break; + case FIRMWARE_ISC: + case FIRMWARE_JBI: + dbg_print(is_debug_on, "start to upgrade: %s.\n", file_name); + ret = firmware_upgrade_jtag(fd, upg_buf, upg_size, info); + break; + case FIRMWARE_SPI_LOGIC_DEV: + dbg_print(is_debug_on, "start to spi logic dev upgrade: %s.\n", file_name); + ret = firmware_upgrade_spi_logic_dev(fd, upg_buf, upg_size, info); + break; + case FIRMWARE_SYSFS_DEV: + dbg_print(is_debug_on, "start to sysfs upgrade: %s.\n", file_name); + ret = firmware_upgrade_sysfs(fd, upg_buf, upg_size, info); + break; + case FIRMWARE_MTD: + dbg_print(is_debug_on, "start to mtd device upgrade: %s.\n", file_name); + ret = firmware_upgrade_mtd(fd, upg_buf, upg_size, info); + break; + default: + dbg_print(is_debug_on, "Error: file type is not support: %s.\n", file_name); + free(upg_buf); + close(fd); + return firmware_error_type(FIRMWARE_ACTION_UPGRADE, info); + } + + dbg_print(is_debug_on, "Completed.\n"); + if (ret != FIRMWARE_SUCCESS) { + dbg_print(is_debug_on, "Error: Failed to upgrade: %s.\n", dev_file_name); + free(upg_buf); + close(fd); + return firmware_error_type(FIRMWARE_ACTION_UPGRADE, info); + } + + free(upg_buf); + close(fd); + + return FIRMWARE_SUCCESS; +} + +/* +* firmware_upgrade_test +* function: firmware upgrade test +* @file_name: param[in] Upgrade file name +* @info: param[in] Upgrade file information +* return value : success--FIRMWARE_SUCCESS, other fail return error code +*/ +static int firmware_upgrade_test(char *file_name, name_info_t *info) +{ + int ret; + int fd; + uint32_t upg_size; + uint8_t *upg_buf; + char dev_file_name[FIRMWARE_NAME_LEN]; + unsigned long crc; + + dbg_print(is_debug_on, "Upgrade firmware test: %s.\n", file_name); + mem_clear(dev_file_name, FIRMWARE_NAME_LEN); + ret = firmware_get_dev_file_name(info, dev_file_name, FIRMWARE_NAME_LEN - 1); + if (ret != FIRMWARE_SUCCESS) { + dbg_print(is_debug_on, "Error: Failed to get dev file name.\n"); + return firmware_error_type(FIRMWARE_ACTION_CHECK, info); + } + + fd = open(dev_file_name, O_RDWR); + if (fd < 0) { + dbg_print(is_debug_on, "Error: Failed to open %s.\n", dev_file_name); + return firmware_error_type(FIRMWARE_ACTION_CHECK, info); + } + +#if 0 + /* check chip name */ + ret = firmware_check_chip_name(fd, info); + if (ret != FIRMWARE_SUCCESS) { + dbg_print(is_debug_on, "Error: Failed to check chip name: %s.\n", dev_file_name); + close(fd); + return firmware_error_type(FIRMWARE_ACTION_CHECK, info); + } +#endif + + /* Check chip version */ + ret = firmware_check_chip_verison(fd, info); + if (ret != FIRMWARE_SUCCESS) { + dbg_print(is_debug_on, "Error: Failed to check chip version: %s.\n", dev_file_name); + close(fd); + return firmware_error_type(FIRMWARE_ACTION_CHECK, info); + } + + /* Gets the upgrade file size */ + ret = firmware_get_file_size(file_name, &upg_size); + if (ret != FIRMWARE_SUCCESS) { + dbg_print(is_debug_on, "Error: Failed to get file size: %s.\n", file_name); + close(fd); + return firmware_error_type(FIRMWARE_ACTION_CHECK, info); + } + + upg_buf = (uint8_t *) malloc(upg_size + 1); + if (upg_buf == NULL) { + dbg_print(is_debug_on, "Error: Failed to malloc memory for upgrade file info: %s.\n", + dev_file_name); + close(fd); + return firmware_error_type(FIRMWARE_ACTION_CHECK, info); + } + + /* Gets the contents of the upgrade file */ + mem_clear(upg_buf, upg_size + 1); + ret = firmware_get_file_info(file_name, upg_buf, upg_size); + if (ret != FIRMWARE_SUCCESS) { + dbg_print(is_debug_on, "Error: Failed to read file info: %s.\n", file_name); + free(upg_buf); + close(fd); + return firmware_error_type(FIRMWARE_ACTION_CHECK, info); + } + + /* file crc32 check */ + crc = crc32(0, (const unsigned char *)upg_buf, (unsigned int)upg_size); + if (crc != info->crc32) { + dbg_print(is_debug_on, "Error: Failed to check file crc: %s.\n", file_name); + dbg_print(is_debug_on, "the crc value is : %#08x.\n", (unsigned int)crc); + free(upg_buf); + close(fd); + return firmware_error_type(FIRMWARE_ACTION_CHECK, info); + } + + dbg_print(is_debug_on, "Start upgrading firmware test, wait...\n"); + + /* Start firmware upgrade */ + switch (info->file_type) { + case FIRMWARE_VME: + dbg_print(is_debug_on, "start to ispvme upgrade test: %s.\n", file_name); + /* WME upgrade link testing is the same as upgrading, using vme test file. */ + ret = firmware_upgrade_ispvme(fd, file_name, info); + break; + case FIRMWARE_ISC: + case FIRMWARE_JBI: + dbg_print(is_debug_on, "start to upgrade test: %s.\n", file_name); + ret = firmware_upgrade_jtag_test(fd, upg_buf, upg_size, info); + break; + case FIRMWARE_SPI_LOGIC_DEV: + dbg_print(is_debug_on, "start to spi logic dev upgrade test: %s.\n", file_name); + ret = firmware_upgrade_spi_logic_dev_test(fd,info); + break; + case FIRMWARE_SYSFS_DEV: + dbg_print(is_debug_on, "start to sysfs upgrade test: %s.\n", file_name); + ret = firmware_upgrade_sysfs_test(fd, info); + break; + case FIRMWARE_MTD: + dbg_print(is_debug_on, "start to mtd device upgrade test: %s.\n", file_name); + ret = firmware_upgrade_mtd_test(fd, info); + break; + default: + dbg_print(is_debug_on, "Error: test file type is not support: %s.\n", file_name); + free(upg_buf); + close(fd); + return firmware_error_type(FIRMWARE_ACTION_UPGRADE, info); + } + + if (ret != FIRMWARE_SUCCESS) { + dbg_print(is_debug_on, "Error: Failed to upgrade test: %s ret=%d.\n", dev_file_name, ret); + free(upg_buf); + close(fd); + if (ret == FIRMWARE_NOT_SUPPORT) { + return firmware_error_type(FIRMWARE_ACTION_SUPPORT, info); + } else { + return firmware_error_type(FIRMWARE_ACTION_UPGRADE, info); + } + } + + free(upg_buf); + close(fd); + + return FIRMWARE_SUCCESS; +} + +/* + * firmware_upgrade_file_type_map + * function:Gets the corresponding upgrade file type from the upgrade file type list + * @value : param[in] file type name + * return value : file type, firmware_file_type_t + */ +static firmware_file_type_t firmware_upgrade_file_type_map(char *type_str) +{ + int type_num; + int i; + + type_num = (sizeof(firmware_file_str) /sizeof(firmware_file_str[0])); + for (i = 0; i < type_num; i++) { + if (!strncmp(firmware_file_str[i].firmware_file_name_str, type_str, + strlen(firmware_file_str[i].firmware_file_name_str))) { + return firmware_file_str[i].firmware_file_type; + } + } + + dbg_print(is_debug_on, "firmware file type unknown\n"); + return FIRMWARE_NONE; +} + +/* + * firmware_upgrade_parse_kv + * function:Parses the header information of the upgrade file based on the key and value + * @key: param[in] key + * @value : param[in] value + * @info : param[out] Upgrade file information + * return value : success--FIRMWARE_SUCCESS, other fail return error code + */ +static int firmware_upgrade_parse_kv(const char *key, const char *value, name_info_t *info) +{ + int i; + if (key == NULL || value == NULL) { + dbg_print(is_debug_on, "Error: failed to get ther key or value.\n"); + return firmware_error_type(FIRMWARE_ACTION_CHECK, info); + } else if (strcmp(key, FILEHEADER_DEVTYPE) == 0) { + /* main board type */ + for (i = 0; i < MAX_DEV_NUM && info->card_type[i]; i++); + if (i == MAX_DEV_NUM) { + dbg_print(is_debug_on, "Error: card type is full for %s. \n", value); + return firmware_error_type(FIRMWARE_ACTION_CHECK, info); + } + info->card_type[i] = strtoul(value, NULL, 0); + } else if (strcmp(key, FILEHEADER_SUBTYPE) == 0) { + /* sub board type */ + for (i = 0; i < MAX_DEV_NUM && info->sub_type[i]; i++); + if (i == MAX_DEV_NUM) { + dbg_print(is_debug_on, "Error: sub type is full for %s. \n", value); + return firmware_error_type(FIRMWARE_ACTION_CHECK, info); + } + info->sub_type[i] = strtoul(value, NULL, 0); + } else if (strcmp(key, FILEHEADER_TYPE) == 0) { + /* Device type */ + if (strcmp(value, FIRMWARE_CPLD_NAME) == 0) { + info->type = FIRMWARE_CPLD; + } else if (strcmp(value, FIRMWARE_FPGA_NAME) == 0) { + info->type = FIRMWARE_FPGA; + } else { + info->type = FIRMWARE_OTHER; + } + } else if (strcmp(key, FILEHEADER_CHAIN) == 0) { + /* link num */ + info->chain = strtoul(value, NULL, 10); + } else if (strcmp(key, FILEHEADER_CHIPNAME) == 0) { + /* chip name */ + if (strlen(value) >= FIRMWARE_NAME_LEN) { + dbg_print(is_debug_on, "Error: '%s' is too long for a chipname.\n", value); + return firmware_error_type(FIRMWARE_ACTION_CHECK, info); + } + mem_clear(info->chip_name, sizeof(info->chip_name)); + snprintf(info->chip_name, sizeof(info->chip_name) - 1, "%s", value); + } else if (strcmp(key, FILEHEADER_VERSION) == 0) { + /* version */ + if (strlen(value) >= FIRMWARE_NAME_LEN) { + dbg_print(is_debug_on, "Error: '%s' is too long for a version.\n", value); + return firmware_error_type(FIRMWARE_ACTION_CHECK, info); + } + mem_clear(info->version, sizeof(info->version)); + snprintf(info->version, sizeof(info->version) - 1, "%s", value); + } else if (strcmp(key, FILEHEADER_FILETYPE) == 0) { + /* file type */ + info->file_type = firmware_upgrade_file_type_map((char *)value); + } else if (strcmp(key, FILEHEADER_CRC) == 0) { + /* file crc32 */ + info->crc32 = strtoul(value, NULL, 0); + } else { + dbg_print(is_debug_on, "Warning: key '%s' is unknown. Continue anyway.\n", key); + return FIRMWARE_SUCCESS; + } + dbg_print(is_debug_on, "key %s is matched.\n", key); + return FIRMWARE_SUCCESS; + } + +/* + * firmware_upgrade_parse_check + * function:Check the results of header parsing + * @file_name: Upgrade file name + * @info : Upgrade file information + * return value : success--FIRMWARE_SUCCESS, other fail return error code + */ +static int firmware_upgrade_parse_check(char *file_name, name_info_t *info) +{ + int i; + if (info->card_type[0] == 0) { + dbg_print(is_debug_on, "Error: %s card type is missing.\n", file_name); + return firmware_error_type(FIRMWARE_ACTION_CHECK, info); + } + if ((info->type <= FIRMWARE_UNDEF_TYPE) || (info->type > FIRMWARE_OTHER)) { + dbg_print(is_debug_on, "Error: %s type is unknown.\n", file_name); + return firmware_error_type(FIRMWARE_ACTION_CHECK, info); + } + if (strlen(info->chip_name) == 0) { + dbg_print(is_debug_on, "Error: %s chip_name is empty.\n", file_name); + return firmware_error_type(FIRMWARE_ACTION_CHECK, info); + } + if (strlen(info->version) == 0) { + dbg_print(is_debug_on, "Error: %s version is empty.\n", file_name); + return firmware_error_type(FIRMWARE_ACTION_CHECK, info); + } + if ((info->file_type <= FIRMWARE_UNDEF_FILE_TYPE) || (info->file_type > FIRMWARE_NONE)) { + dbg_print(is_debug_on, "Error: %s file type is unknown.\n", file_name); + return firmware_error_type(FIRMWARE_ACTION_CHECK, info); + } + dbg_print(is_debug_on, "The file header parse:(%s) \n" , file_name); + dbg_print(is_debug_on, " card type: "); + for (i = 0; i < MAX_DEV_NUM && info->card_type[i]; i++){ + dbg_print(is_debug_on, "0x%x, ", info->card_type[i]); + } + dbg_print(is_debug_on, "\n" + " sub type : "); + for (i = 0; i < MAX_DEV_NUM && info->sub_type[i]; i++){ + dbg_print(is_debug_on, "0x%x, ", info->sub_type[i]); + } + dbg_print(is_debug_on, "\n" + " type : %d, \n" + " chain : %d, \n" + " chip name: %s \n" + " version : %s \n" + " file type: %d \n" + " the crc32 value: %#x \n", + info->type, info->chain, info->chip_name, info->version, info->file_type, info->crc32); + return FIRMWARE_SUCCESS; +} + +/* + * firmware_upgrade_read_header + * function:Read the header information of the upgrade file + * @file_name: param[in] Upgrade file name + * @info : param[out] Upgrade file information + * return value : success--FIRMWARE_SUCCESS, other fail return error code + */ +static int firmware_upgrade_read_header( char *file_name, name_info_t *info) +{ + FILE *fp; + char *charp; + char *charn; + char header_buffer[MAX_HEADER_SIZE]; + char header_key[MAX_HEADER_KV_SIZE]; + char header_var[MAX_HEADER_KV_SIZE]; + int ret; + int len; + + fp = fopen(file_name, "r"); + if (fp == NULL) { + dbg_print(is_debug_on, "Error: Failed to open file: %s. \n", file_name); + perror("fopen"); + return firmware_error_type(FIRMWARE_ACTION_CHECK, info); + } + + mem_clear(header_buffer, sizeof(header_buffer)); + len = fread(header_buffer, MAX_HEADER_SIZE - 1, 1, fp); + fclose(fp); + if (len < 0) { + dbg_print(is_debug_on, "Error: Failed to read header : %s. \n", file_name); + return firmware_error_type(FIRMWARE_ACTION_CHECK, info); + } + header_buffer[MAX_HEADER_SIZE - 1] = 0; + + charp = strstr(header_buffer, "FILEHEADER(\n"); + if (charp == NULL) { + dbg_print(is_debug_on, "Error: The file format %s is wrong. \n", file_name); + return firmware_error_type(FIRMWARE_ACTION_CHECK, info); + } + charp += strlen("FILEHEADER(\n"); + + dbg_print(is_debug_on, "File parse start.\n"); + mem_clear(info, sizeof(name_info_t)); + ret = 0; + charn = charp; + mem_clear(header_key, sizeof(header_key)); + while (*charn != ')') { + charn = strpbrk(charp, "=,)\n"); + if (charn == NULL) { + dbg_print(is_debug_on, "Error: The parser can't find mark.\n"); + return firmware_error_type(FIRMWARE_ACTION_CHECK, info); + } + if (charn - charp >= MAX_HEADER_KV_SIZE) { + dbg_print(is_debug_on, "Error: The parser find a overflow mark.\n"); + return firmware_error_type(FIRMWARE_ACTION_CHECK, info); + } + switch (*charn) { + case '=': + mem_clear(header_key, sizeof(header_key)); + memcpy(header_key, charp, charn - charp); + break; + case '\n': + case ',': + mem_clear(header_var, sizeof(header_var)); + memcpy(header_var, charp, charn - charp); + dbg_print(is_debug_on, "Parser: %s = %s .\n", header_key, header_var); + firmware_upgrade_parse_kv(header_key, header_var, info); + break; + case ')': + break; + default: + dbg_print(is_debug_on, "Error: The parser get unexpected mark '%c(0x%02X)'.\n", *charn, *charn); + return firmware_error_type(FIRMWARE_ACTION_CHECK, info); + } + charp = (charn + 1); + } + + ret = firmware_upgrade_parse_check(file_name, info); + if (ret != FIRMWARE_SUCCESS) { + return FIRMWARE_FAILED; + } + + header_offset = charp + 1 - header_buffer; /* charp at '\n' */ + dbg_print(is_debug_on,"the header offset is %d \n", header_offset); + return FIRMWARE_SUCCESS; +} + +/* + * firmware_upgrade_one_file + * function: upgrade file + * @file_name: Upgrade file name + * @main_type: main board type + * @sub_type: sub board type + * @slot: 0--main, sub slot starts at 1 + * return value : success--FIRMWARE_SUCCESS, other fail return error code + */ +static int firmware_upgrade_one_file(char *file_name, int main_type, int sub_type, int slot) +{ + int ret; + name_info_t info; + + if ((slot < 0) || (file_name == NULL)) { + dbg_print(is_debug_on, "Failed firmware_upgrade_one_file parameter err.\n"); + return FIRMWARE_FAILED; + } + + dbg_print(is_debug_on, "firmware upgrade %s 0x%x 0x%x %d\n", file_name, main_type, sub_type, slot); + /* Read the header information of the upgrade file */ + ret = firmware_upgrade_read_header(file_name, &info); + if (ret != FIRMWARE_SUCCESS) { + dbg_print(is_debug_on, "Failed to get file header: %s\n", file_name); + return ret; + } + + /* Check the file information to determine that the file is available for use on the device */ + ret = firmware_check_file_info(&info, main_type, sub_type, slot); + if (ret != FIRMWARE_SUCCESS) { + dbg_print(is_debug_on, "File is not match with the device: %s.\n", file_name); + return ret; + } + + /* The link number corresponding to the upgrade file is calculated based on the slot number. + 16 links are reserved for each slot. main boade slot is 0. */ + info.chain += slot * FIRMWARE_SLOT_MAX_NUM; + ret = firmware_upgrade(file_name, &info); + if (ret != FIRMWARE_SUCCESS) { + dbg_print(is_debug_on, "Failed to upgrade: %s.\n", file_name); + return ret; + } + + return FIRMWARE_SUCCESS; +} + +/* + * firmware_upgrade_file_test + * function: upgrade file + * @file_name: Upgrade file name + * @main_type: main board type + * @sub_type: sub board type + * @slot: 0--main, sub slot starts at 1 + * return value : success--FIRMWARE_SUCCESS, other fail return error code + */ +static int firmware_upgrade_file_test(char *file_name, int main_type, int sub_type, int slot) +{ + int ret; + name_info_t info; + + if ((slot < 0) || (file_name == NULL)) { + dbg_print(is_debug_on, "Failed firmware_upgrade_one_file parameter err.\n"); + return FIRMWARE_FAILED; + } + + dbg_print(is_debug_on, "firmware upgrade %s 0x%x 0x%x %d\n", file_name, main_type, sub_type, slot); + /* Read the header information of the upgrade file */ + ret = firmware_upgrade_read_header(file_name, &info); + if (ret != FIRMWARE_SUCCESS) { + dbg_print(is_debug_on, "Failed to get file header: %s, ret=%d\n", file_name, ret); + return ret; + } + + /* Check the file information to determine that the file is available for use on the device */ + ret = firmware_check_file_info(&info, main_type, sub_type, slot); + if (ret != FIRMWARE_SUCCESS) { + dbg_print(is_debug_on, "File is not match with the device: %s, ret=%d.\n", file_name, ret); + return ret; + } + + /* The link number corresponding to the upgrade file is calculated based on the slot number. + 16 links are reserved for each slot. main boade slot is 0. */ + info.chain += slot * FIRMWARE_SLOT_MAX_NUM; + ret = firmware_upgrade_test(file_name, &info); + if (ret != FIRMWARE_SUCCESS) { + dbg_print(is_debug_on, "Failed to upgrade: %s, ret=%d\n", file_name, ret); + return ret; + } + + return FIRMWARE_SUCCESS; +} + +static int firmware_upgrade_data_dump(char *argv[]) +{ + int ret; + uint32_t offset, len; + + /* dump by type */ + if (strcmp(argv[2], "spi_logic_dev") == 0) { + /* usag: firmware_upgrade dump spi_logic_dev dev_path offset size print/record_file_path */ + offset = strtoul(argv[4], NULL, 0); + len = strtoul(argv[5], NULL, 0); + /* offset needs align by 256 bytes */ + if ((offset & 0xff) || (len == 0)) { + dbg_print(is_debug_on,"only support offset align by 256 bytes.\n"); + return FIRMWARE_FAILED; + } + dbg_print(is_debug_on, "start to dump %s data. offset:0x%x, len:0x%x\n", argv[2], offset, len); + ret = firmware_upgrade_spi_logic_dev_dump(argv[3], offset, len, argv[6]); + } else { + dbg_print(is_debug_on, "Error: %s not support dump data.\n", argv[2]); + return FIRMWARE_FAILED; + } + + if (ret != FIRMWARE_SUCCESS) { + dbg_print(is_debug_on, "Failed to dump %s data. ret:%d\n", argv[3], ret); + return FIRMWARE_FAILED; + } + + return FIRMWARE_SUCCESS; +} + +int main(int argc, char *argv[]) +{ + int ret; + int main_type, sub_type, slot; + + is_debug_on = firmware_upgrade_debug(); + + signal(SIGTERM, SIG_IGN); /* ignore kill signal */ + signal(SIGINT, SIG_IGN); /* ignore ctrl+c signal */ + signal(SIGTSTP, SIG_IGN); /* ignore ctrl+z signal */ + + if ((argc != 5) && (argc != 6) && (argc != 7)) { + printf("Use:\n"); + printf(" upgrade file : firmware_upgrade file main_type sub_type slot\n"); + printf(" upgrade test : firmware_upgrade test file main_type sub_type slot\n"); + printf(" spi_logic_dev dump : firmware_upgrade dump spi_logic_dev dev_path offset size print/record_file_path\n"); + dbg_print(is_debug_on, "Failed to upgrade the number of argv: %d.\n", argc); + return ERR_FW_UPGRADE; + } + + if (argc == 5) { + main_type = strtoul(argv[2], NULL, 16); + sub_type = strtoul(argv[3], NULL, 16); + slot = strtoul(argv[4], NULL, 10); + printf("+================================+\n"); + printf("|Begin to upgrade, please wait...|\n"); + ret = firmware_upgrade_one_file(argv[1], main_type, sub_type, slot); + if (ret != FIRMWARE_SUCCESS) { + dbg_print(is_debug_on, "Failed to upgrade a firmware file: %s. (%d)\n", argv[1], ret); + printf("| Upgrade failed! |\n"); + printf("+================================+\n"); + return ret; + } + + printf("| Upgrade succeeded! |\n"); + printf("+================================+\n"); + dbg_print(is_debug_on, "Sucess to upgrade a firmware file: %s.\n", argv[1]); + return FIRMWARE_SUCCESS; + } else if ((argc == 6) && (strcmp(argv[1], "test") == 0)) { + main_type = strtoul(argv[3], NULL, 16); + sub_type = strtoul(argv[4], NULL, 16); + slot = strtoul(argv[5], NULL, 10); + printf("+=====================================+\n"); + printf("|Begin to upgrade test, please wait...|\n"); + ret = firmware_upgrade_file_test(argv[2], main_type, sub_type, slot); + if (ret == FIRMWARE_SUCCESS) { + printf("| Upgrade test succeeded! |\n"); + printf("+=====================================+\n"); + dbg_print(is_debug_on, "Sucess to upgrade test a firmware file: %s.\n", argv[2]); + return FIRMWARE_SUCCESS; + } else if (ret == ERR_FW_DO_UPGRADE_NOT_SUPPORT) { + dbg_print(is_debug_on, "do not support to upgrade test a firmware file: %s. (%d)\n", argv[2], ret); + printf("| Not support to upgrade test! |\n"); + printf("+=====================================+\n"); + return ret; + } else { + dbg_print(is_debug_on, "Failed to upgrade test a firmware file: %s. (%d)\n", argv[2], ret); + printf("| Upgrade test failed! |\n"); + printf("+=====================================+\n"); + return ret; + } + } else if (strcmp(argv[1], "dump") == 0) { + /* print device data */ + ret = firmware_upgrade_data_dump(argv); + if (ret == FIRMWARE_SUCCESS) { + printf("dump data succeeded.\n"); + return FIRMWARE_SUCCESS; + } else { + printf("dump data failed. ret:%d\n", ret); + return ret; + } + } + + printf("+=================+\n"); + printf("| UPGRADE FAIL! |\n"); + printf("+=================+\n"); + + return ERR_FW_UPGRADE; + } diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/fw_upg_gpio_vme/hardware.c b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/fw_upg_gpio_vme/hardware.c new file mode 100644 index 000000000000..c43c9095fda6 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/fw_upg_gpio_vme/hardware.c @@ -0,0 +1,263 @@ +/********************************************************************************* +* Lattice Semiconductor Corp. Copyright 2000-2008 +* +* This is the hardware.c of ispVME V12.1 for JTAG programmable devices. +* All the functions requiring customization are organized into this file for +* the convinience of porting. +*********************************************************************************/ +/********************************************************************************* +* Revision History: +* +* 09/11/07 NN Type cast mismatch variables +* 09/24/07 NN Added calibration function. +* Calibration will help to determine the system clock frequency +* and the count value for one micro-second delay of the target +* specific hardware. +* Modified the ispVMDelay function +* Removed Delay Percent support +* Moved the sclock() function from ivm_core.c to hardware.c +*********************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/******************************************************************************** +* Declaration of global variables +* +*********************************************************************************/ + +unsigned char g_siIspPins = 0x00; /*Keeper of JTAG pin state*/ +unsigned short g_usInPort = 0x379; /*Address of the TDO pin*/ +unsigned short g_usOutPort = 0x378; /*Address of TDI, TMS, TCK pin*/ +unsigned short g_usCpu_Frequency = 1000; /*Enter your CPU frequency here, unit in MHz.*/ + +/********************************************************************************* +* This is the definition of the bit locations of each respective +* signal in the global variable g_siIspPins. +* +* NOTE: Users must add their own implementation here to define +* the bit location of the signal to target their hardware. +* The example below is for the Lattice download cable on +* on the parallel port. +* +*********************************************************************************/ + +#if 0 +const unsigned char g_ucPinTDI = JTAG_TDI; /* Bit address of TDI */ +const unsigned char g_ucPinTCK = JTAG_TCK; /* Bit address of TCK */ +const unsigned char g_ucPinTMS = JTAG_TMS; /* Bit address of TMS */ +const unsigned char g_ucPinENABLE = JTAG_ENABLE; /* Bit address of ENABLE */ +const unsigned char g_ucPinTRST = JTAG_TRST; /* Bit address of TRST */ +const unsigned char g_ucPinTDO = JTAG_TDO; /* Bit address of TDO*/ +#endif +int g_file_fd = -1; +/*************************************************************** +* +* Functions declared in hardware.c module. +* +***************************************************************/ +void writePort(unsigned char a_ucPins, unsigned char a_ucValue); +unsigned char readPort(); +void sclock(); +void ispVMDelay(unsigned short a_usTimeDelay); +void calibration(void); + +/******************************************************************************** +* writePort +* To apply the specified value to the pins indicated. This routine will +* be modified for specific systems. +* As an example, this code uses the IBM-PC standard Parallel port, along with the +* schematic shown in Lattice documentation, to apply the signals to the +* JTAG pins. +* +* PC Parallel port pin Signal name Port bit address +* 2 g_ucPinTDI 1 +* 3 g_ucPinTCK 2 +* 4 g_ucPinTMS 4 +* 5 g_ucPinENABLE 8 +* 6 g_ucPinTRST 16 +* 10 g_ucPinTDO 64 +* +* Parameters: +* - a_ucPins, which is actually a set of bit flags (defined above) +* that correspond to the bits of the data port. Each of the I/O port +* bits that drives an isp programming pin is assigned a flag +* (through a #define) corresponding to the signal it drives. To +* change the value of more than one pin at once, the flags are added +* together, much like file access flags are. +* +* The bit flags are only set if the pin is to be changed. Bits that +* do not have their flags set do not have their levels changed. The +* state of the port is always manintained in the static global +* variable g_siIspPins, so that each pin can be addressed individually +* without disturbing the others. +* +* - a_ucValue, which is either HIGH (0x01 ) or LOW (0x00 ). Only these two +* values are valid. Any non-zero number sets the pin(s) high. +* +*********************************************************************************/ + +void writePort(unsigned char a_ucPins, unsigned char a_ucValue) +{ + switch (a_ucPins) { + case JTAG_TCK: + ioctl(g_file_fd, FIRMWARE_JTAG_TCK, &a_ucValue); + break; + case JTAG_TDI: + ioctl(g_file_fd, FIRMWARE_JTAG_TDI, &a_ucValue); + break; + case JTAG_TMS: + ioctl(g_file_fd, FIRMWARE_JTAG_TMS, &a_ucValue); + break; + case JTAG_ENABLE: + ioctl(g_file_fd, FIRMWARE_JTAG_EN, &a_ucValue); + break; + case JTAG_TRST: + //ioctl(g_file_fd, FIRMWARE_JTAG_TRST, &a_ucValue); + break; + default: + break; + } +} + +/********************************************************************************* +* +* readPort +* +* Returns the value of the TDO from the device. +* +**********************************************************************************/ +unsigned char readPort() +{ + unsigned char ucRet = 0; + + ioctl(g_file_fd, FIRMWARE_JTAG_TDO, &ucRet); + return (ucRet); +} + +/********************************************************************************* +* sclock +* +* Apply a pulse to TCK. +* +* This function is located here so that users can modify to slow down TCK if +* it is too fast (> 25MHZ). Users can change the IdleTime assignment from 0 to +* 1, 2... to effectively slowing down TCK by half, quarter... +* +*********************************************************************************/ +void sclock() +{ + unsigned short IdleTime = 0; //change to > 0 if need to slow down TCK + unsigned short usIdleIndex = 0; + IdleTime++; + for (usIdleIndex = 0; usIdleIndex < IdleTime; usIdleIndex++) { + writePort(JTAG_TCK, 0x01); + } + for (usIdleIndex = 0; usIdleIndex < IdleTime; usIdleIndex++) { + writePort(JTAG_TCK, 0x00); + } +} +/******************************************************************************** +* +* ispVMDelay +* +* +* Users must implement a delay to observe a_usTimeDelay, where +* bit 15 of the a_usTimeDelay defines the unit. +* 1 = milliseconds +* 0 = microseconds +* Example: +* a_usTimeDelay = 0x0001 = 1 microsecond delay. +* a_usTimeDelay = 0x8001 = 1 millisecond delay. +* +* This subroutine is called upon to provide a delay from 1 millisecond to a few +* hundreds milliseconds each time. +* It is understood that due to a_usTimeDelay is defined as unsigned short, a 16 bits +* integer, this function is restricted to produce a delay to 64000 micro-seconds +* or 32000 milli-second maximum. The VME file will never pass on to this function +* a delay time > those maximum number. If it needs more than those maximum, the VME +* file will launch the delay function several times to realize a larger delay time +* cummulatively. +* It is perfectly alright to provide a longer delay than required. It is not +* acceptable if the delay is shorter. +* +* Delay function example--using the machine clock signal of the native CPU------ +* When porting ispVME to a native CPU environment, the speed of CPU or +* the system clock that drives the CPU is usually known. +* The speed or the time it takes for the native CPU to execute one for loop +* then can be calculated as follows: +* The for loop usually is compiled into the ASSEMBLY code as shown below: +* LOOP: DEC RA; +* JNZ LOOP; +* If each line of assembly code needs 4 machine cycles to execute, +* the total number of machine cycles to execute the loop is 2 x 4 = 8. +* Usually system clock = machine clock (the internal CPU clock). +* Note: Some CPU has a clock multiplier to double the system clock for + the machine clock. +* +* Let the machine clock frequency of the CPU be F, or 1 machine cycle = 1/F. +* The time it takes to execute one for loop = (1/F ) x 8. +* Or one micro-second = F(MHz)/8; +* +* Example: The CPU internal clock is set to 100Mhz, then one micro-second = 100/8 = 12 +* +* The C code shown below can be used to create the milli-second accuracy. +* Users only need to enter the speed of the cpu. +* +**********************************************************************************/ +void ispVMDelay(unsigned short a_usTimeDelay) +{ + struct timespec ts; + + if (a_usTimeDelay & 0x8000) { + /* milliseconds */ + a_usTimeDelay &= 0x7FFF; + ts.tv_sec = (long int) (a_usTimeDelay / 1000); + ts.tv_nsec = (long int) (a_usTimeDelay % 1000) * 1000000ul; + } else { + /* microseconds */ + ts.tv_sec = 0; + ts.tv_nsec = (long int) a_usTimeDelay * 1000ul; + } + + nanosleep(&ts, NULL); +} + +/********************************************************************************* +* +* calibration +* +* It is important to confirm if the delay function is indeed providing +* the accuracy required. Also one other important parameter needed +* checking is the clock frequency. +* Calibration will help to determine the system clock frequency +* and the loop_per_micro value for one micro-second delay of the target +* specific hardware. +* +**********************************************************************************/ +void calibration(void) +{ + /*Apply 2 pulses to TCK.*/ + writePort(JTAG_TCK, 0x00); + writePort(JTAG_TCK, 0x01); + writePort(JTAG_TCK, 0x00); + writePort(JTAG_TCK, 0x01); + writePort(JTAG_TCK, 0x00); + + /*Delay for 1 millisecond. Pass on 1000 or 0x8001 both = 1ms delay.*/ + ispVMDelay(0x8001); + + /*Apply 2 pulses to TCK*/ + writePort(JTAG_TCK, 0x01); + writePort(JTAG_TCK, 0x00); + writePort(JTAG_TCK, 0x01); + writePort(JTAG_TCK, 0x00); +} diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/fw_upg_gpio_vme/ispvm_ui.c b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/fw_upg_gpio_vme/ispvm_ui.c new file mode 100644 index 000000000000..69a8e53852b5 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/fw_upg_gpio_vme/ispvm_ui.c @@ -0,0 +1,837 @@ +/************************************************************** +* +* Lattice Semiconductor Corp. Copyright 2008 +* +* ispVME Embedded allows programming of Lattice's suite of FPGA +* devices on embedded systems through the JTAG port. The software +* is distributed in source code form and is open to re - distribution +* and modification where applicable. +* +* ispVME Embedded C Source comprised with 3 modules: +* ispvm_ui.c is the module provides input and output support. +* ivm_core.c is the module interpret the VME file(s). +* hardware.c is the module access the JTAG port of the device(s). +* +* The optional module cable.c is for supporting Lattice's parallel +* port ispDOWNLOAD cable on DOS and Windows 95/98 O/S. It can be +* requested from Lattice's ispVMSupport. +* +***************************************************************/ + +/************************************************************** +* +* Revision History of ispvm_ui.c +* +* 3/6/07 ht Added functions vme_out_char(),vme_out_hex(), +* vme_out_string() to provide output resources. +* Consolidate all printf() calls into the added output +* functions. +* +* 09/11/07 NN Added Global variables initialization +* 09/24/07 NN Added a switch allowing users to do calibration. +* Calibration will help to determine the system clock frequency +* and the count value for one micro-second delay of the target +* specific hardware. +* Removed Delay Percent support +* 11/15/07 NN moved the checking of the File CRC to the end of processing +* 08/28/08 NN Added Calculate checksum support. +***************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include + +/*************************************************************** +* +* File pointer to the VME file. +* +***************************************************************/ + +FILE *g_pVMEFile = NULL; + +/*************************************************************** +* +* Functions declared in this ispvm_ui.c module +* +***************************************************************/ +unsigned char GetByte(void); +void vme_out_char(unsigned char charOut); +void vme_out_hex(unsigned char hexOut); +void vme_out_string(char *stringOut); +void ispVMMemManager(signed char cTarget, unsigned short usSize); +void ispVMFreeMem(void); +void error_handler(short a_siRetCode, char *pszMessage); +signed char ispVM(const char *a_pszFilename); + +/*************************************************************** +* +* Global variables. +* +***************************************************************/ +unsigned short g_usPreviousSize = 0; +unsigned short g_usExpectedCRC = 0; + +/*************************************************************** +* +* External variables and functions declared in ivm_core.c module. +* +***************************************************************/ +extern signed char ispVMCode(); +extern void ispVMCalculateCRC32(unsigned char a_ucData); +extern void ispVMStart(); +extern void ispVMEnd(); +extern unsigned short g_usCalculatedCRC; +extern unsigned short g_usDataType; +extern unsigned char *g_pucOutMaskData, +*g_pucInData, +*g_pucOutData, +*g_pucHIRData, +*g_pucTIRData, +*g_pucHDRData, +*g_pucTDRData, +*g_pucOutDMaskData, +*g_pucIntelBuffer; +extern unsigned char *g_pucHeapMemory; +extern unsigned short g_iHeapCounter; +extern unsigned short g_iHEAPSize; +extern unsigned short g_usIntelDataIndex; +extern unsigned short g_usIntelBufferSize; +extern LVDSPair *g_pLVDSList; +//08/28/08 NN Added Calculate checksum support. +extern unsigned long g_usChecksum; +extern unsigned int g_uiChecksumIndex; + +/* Added reinit for call ispvme more than once */ +extern void ivm_core_reinit(); +/*************************************************************** +* +* External variables and functions declared in hardware.c module. +* +***************************************************************/ +extern void calibration(void); +extern unsigned short g_usCpu_Frequency; +extern int g_file_fd; + +/*************************************************************** +* +* Supported VME versions. +* +***************************************************************/ + +const char *const g_szSupportedVersions[] = { "__VME2.0", "__VME3.0", "____12.0", "____12.1", 0 }; + +/*************************************************************** +* +* GetByte +* +* Returns a byte to the caller. The returned byte depends on the +* g_usDataType register. If the HEAP_IN bit is set, then the byte +* is returned from the HEAP. If the LHEAP_IN bit is set, then +* the byte is returned from the intelligent buffer. Otherwise, +* the byte is returned directly from the VME file. +* +***************************************************************/ + +char* strlwr(char *str) +{ + char *orig = str; +// process the string + for (; *str != '\0'; str++) + *str = tolower(*str); + return orig; +} + +unsigned char GetByte() +{ + unsigned char ucData = 0; + + if (g_usDataType & HEAP_IN) { + + /*************************************************************** + * + * Get data from repeat buffer. + * + ***************************************************************/ + + if (g_iHeapCounter > g_iHEAPSize) { + + /*************************************************************** + * + * Data over-run. + * + ***************************************************************/ + + return 0xFF; + } + + ucData = g_pucHeapMemory[g_iHeapCounter++]; + } + else if ( g_usDataType & LHEAP_IN ) { + + /*************************************************************** + * + * Get data from intel buffer. + * + ***************************************************************/ + + if (g_usIntelDataIndex >= g_usIntelBufferSize) { + + /*************************************************************** + * + * Data over-run. + * + ***************************************************************/ + + return 0xFF; + } + + ucData = g_pucIntelBuffer[g_usIntelDataIndex++]; + } + else { + + /*************************************************************** + * + * Get data from file. + * + ***************************************************************/ + + ucData = (unsigned char)fgetc(g_pVMEFile); + + if (feof(g_pVMEFile)) { + + /*************************************************************** + * + * Reached EOF. + * + ***************************************************************/ + + return 0xFF; + } + /*************************************************************** + * + * Calculate the 32-bit CRC if the expected CRC exist. + * + ***************************************************************/ + if( g_usExpectedCRC != 0) + { + ispVMCalculateCRC32(ucData); + } + } + + return (ucData); +} + +/*************************************************************** +* +* vme_out_char +* +* Send a character out to the output resource if available. +* The monitor is the default output resource. +* +* +***************************************************************/ +void vme_out_char(unsigned char charOut) +{ + dbg_print(is_debug_on, "%c", charOut); +} +/*************************************************************** +* +* vme_out_hex +* +* Send a character out as in hex format to the output resource +* if available. The monitor is the default output resource. +* +* +***************************************************************/ +void vme_out_hex(unsigned char hexOut) +{ + dbg_print(is_debug_on, "%.2X", hexOut); +} +/*************************************************************** +* +* vme_out_string +* +* Send a text string out to the output resource if available. +* The monitor is the default output resource. +* +* +***************************************************************/ +void vme_out_string(char *stringOut) +{ + dbg_print(is_debug_on,"%s",stringOut); +} +/*************************************************************** +* +* ispVMMemManager +* +* Allocate memory based on cTarget. The memory size is specified +* by usSize. +* +***************************************************************/ + +void ispVMMemManager(signed char cTarget, unsigned short usSize) +{ + switch (cTarget) { + case XTDI: + case TDI: + if (g_pucInData != NULL) { + if (g_usPreviousSize == usSize) { /*memory exist*/ + break; + } + else { + free(g_pucInData); + g_pucInData = NULL; + } + } + g_pucInData = (unsigned char *)malloc(usSize / 8 + 2); + g_usPreviousSize = usSize; + case XTDO: + case TDO: + if (g_pucOutData != NULL) { + if (g_usPreviousSize == usSize) { /*already exist*/ + break; + } + else { + free(g_pucOutData); + g_pucOutData = NULL; + } + } + g_pucOutData = (unsigned char *)malloc(usSize / 8 + 2); + g_usPreviousSize = usSize; + break; + case MASK: + if (g_pucOutMaskData != NULL) { + if (g_usPreviousSize == usSize) { /*already allocated*/ + break; + } + else { + free(g_pucOutMaskData); + g_pucOutMaskData = NULL; + } + } + g_pucOutMaskData = (unsigned char *)malloc(usSize / 8 + 2); + g_usPreviousSize = usSize; + break; + case HIR: + if (g_pucHIRData != NULL) { + free(g_pucHIRData); + g_pucHIRData = NULL; + } + g_pucHIRData = (unsigned char *)malloc(usSize / 8 + 2); + break; + case TIR: + if (g_pucTIRData != NULL) { + free(g_pucTIRData); + g_pucTIRData = NULL; + } + g_pucTIRData = (unsigned char *)malloc(usSize / 8 + 2); + break; + case HDR: + if (g_pucHDRData != NULL) { + free(g_pucHDRData); + g_pucHDRData = NULL; + } + g_pucHDRData = (unsigned char *)malloc(usSize / 8 + 2); + break; + case TDR: + if (g_pucTDRData != NULL) { + free(g_pucTDRData); + g_pucTDRData = NULL; + } + g_pucTDRData = (unsigned char *)malloc(usSize / 8 + 2); + break; + case HEAP: + if (g_pucHeapMemory != NULL) { + free(g_pucHeapMemory); + g_pucHeapMemory = NULL; + } + g_pucHeapMemory = (unsigned char *)malloc(usSize + 2); + break; + case DMASK: + if (g_pucOutDMaskData != NULL) { + if (g_usPreviousSize == usSize) { /*already allocated*/ + break; + } + else { + free(g_pucOutDMaskData); + g_pucOutDMaskData = NULL; + } + } + g_pucOutDMaskData = (unsigned char *)malloc(usSize / 8 + 2); + g_usPreviousSize = usSize; + break; + case LHEAP: + if (g_pucIntelBuffer != NULL) { + free(g_pucIntelBuffer); + g_pucIntelBuffer = NULL; + } + g_pucIntelBuffer = (unsigned char *)malloc(usSize + 2); + break; + case LVDS: + if (g_pLVDSList != NULL) { + free(g_pLVDSList); + g_pLVDSList = NULL; + } + g_pLVDSList = (LVDSPair * )calloc(usSize, sizeof(LVDSPair)); + break; + default: + return; + } +} + +/*************************************************************** +* +* ispVMFreeMem +* +* Free memory that were dynamically allocated. +* +***************************************************************/ + +void ispVMFreeMem() +{ + if (g_pucHeapMemory != NULL) { + free(g_pucHeapMemory); + g_pucHeapMemory = NULL; + } + + if (g_pucOutMaskData != NULL) { + free(g_pucOutMaskData); + g_pucOutMaskData = NULL; + } + + if (g_pucInData != NULL) { + free(g_pucInData); + g_pucInData = NULL; + } + + if (g_pucOutData != NULL) { + free(g_pucOutData); + g_pucOutData = NULL; + } + + if (g_pucHIRData != NULL) { + free(g_pucHIRData); + g_pucHIRData = NULL; + } + + if (g_pucTIRData != NULL) { + free(g_pucTIRData); + g_pucTIRData = NULL; + } + + if (g_pucHDRData != NULL) { + free(g_pucHDRData); + g_pucHDRData = NULL; + } + + if (g_pucTDRData != NULL) { + free(g_pucTDRData); + g_pucTDRData = NULL; + } + + if (g_pucOutDMaskData != NULL) { + free(g_pucOutDMaskData); + g_pucOutDMaskData = NULL; + } + + if (g_pucIntelBuffer != NULL) { + free(g_pucIntelBuffer); + g_pucIntelBuffer = NULL; + } + + if (g_pLVDSList != NULL) { + free(g_pLVDSList); + g_pLVDSList = NULL; + } +} + +/*************************************************************** +* +* error_handler +* +* Reports the error message. +* +***************************************************************/ + +void error_handler(short a_siRetCode, char *pszMessage) +{ + const char *pszErrorMessage[] = { "pass", + "verification fail", + "can't find the file", + "wrong file type", + "file error", + "option error", + "crc verification error" }; + + strcpy(pszMessage, pszErrorMessage[-a_siRetCode]); +} +/*************************************************************** +* +* ispVM +* +* The entry point of the ispVM embedded. If the version and CRC +* are verified, then the VME will be processed. +* +***************************************************************/ +signed char ispVM(const char *a_pszFilename) +{ + char szFileVersion[9] = { 0 }; + signed char cRetCode = 0; + signed char cIndex = 0; + signed char cVersionIndex = 0; + unsigned char ucReadByte = 0; + int ret; + /*************************************************************** + * + * Global variables initialization. + * + * 09/11/07 NN Added + ***************************************************************/ + g_pucHeapMemory = NULL; + g_iHeapCounter = 0; + g_iHEAPSize = 0; + g_usIntelDataIndex = 0; + g_usIntelBufferSize = 0; + g_usPreviousSize = 0; + + /*************************************************************** + * + * Open a file pointer to the VME file. + * + ***************************************************************/ + + if ((g_pVMEFile = fopen(a_pszFilename, "rb")) == NULL) { + return VME_FILE_READ_FAILURE; + } + /* Skip the contents of the file header */ + ret=fseek(g_pVMEFile, header_offset, SEEK_SET); + if (ret < 0) { + vme_out_string("Failed to skip header.\n"); + fclose(g_pVMEFile); + g_pVMEFile = NULL; + return VME_ARGUMENT_FAILURE; + } + + g_usCalculatedCRC = 0; + g_usExpectedCRC = 0; + ucReadByte = GetByte(); + switch (ucReadByte) { + case FILE_CRC: + + /*************************************************************** + * + * Read and store the expected CRC to do the comparison at the end. + * Only versions 3.0 and higher support CRC protection. + * + ***************************************************************/ + + g_usExpectedCRC = (unsigned char)fgetc(g_pVMEFile); + g_usExpectedCRC <<= 8; + g_usExpectedCRC |= fgetc(g_pVMEFile); + + /*************************************************************** + * + * Read and store the version of the VME file. + * + ***************************************************************/ + + for (cIndex = 0; cIndex < 8; cIndex++) { + szFileVersion[cIndex] = GetByte(); + } + break; + default: + + /*************************************************************** + * + * Read and store the version of the VME file. Must be version 2.0. + * + ***************************************************************/ + + szFileVersion[0] = (signed char)ucReadByte; + for (cIndex = 1; cIndex < 8; cIndex++) { + szFileVersion[cIndex] = GetByte(); + } + + break; + } + + /*************************************************************** + * + * Compare the VME file version against the supported version. + * + ***************************************************************/ + for (cVersionIndex = 0; g_szSupportedVersions[cVersionIndex] != 0; cVersionIndex++) { + for (cIndex = 0; cIndex < 8; cIndex++) { + if (szFileVersion[cIndex] != g_szSupportedVersions[cVersionIndex][cIndex]) { + cRetCode = VME_VERSION_FAILURE; + break; + } + cRetCode = 0; + } + + if (cRetCode == 0) { + + /*************************************************************** + * + * Found matching version, break. + * + ***************************************************************/ + + break; + } + } + + if (cRetCode < 0) { + + /*************************************************************** + * + * VME file version failed to match the supported versions. + * + ***************************************************************/ + + fclose(g_pVMEFile); + g_pVMEFile = NULL; + return VME_VERSION_FAILURE; + } + + /*************************************************************** + * + * Enable the JTAG port to communicate with the device. + * Set the JTAG state machine to the Test-Logic/Reset State. + * + ***************************************************************/ + ispVMStart(); + + /*************************************************************** + * + * Process the VME file. + * + ***************************************************************/ + + cRetCode = ispVMCode(); + + /*************************************************************** + * + * Set the JTAG State Machine to Test-Logic/Reset state then disable + * the communication with the JTAG port. + * + ***************************************************************/ + + ispVMEnd(); + + fclose(g_pVMEFile); + g_pVMEFile = NULL; + + ispVMFreeMem(); + + /*************************************************************** + * + * Compare the expected CRC versus the calculated CRC. + * + ***************************************************************/ + + if (cRetCode == 0 && g_usExpectedCRC != 0 && (g_usExpectedCRC != g_usCalculatedCRC)) { + printf("Expected CRC: 0x%.4X\n", g_usExpectedCRC); + printf("Calculated CRC: 0x%.4X\n", g_usCalculatedCRC); + return VME_CRC_FAILURE; + } + + return (cRetCode); +} + +/*************************************************************** +* +* ispvme_reinit +* +* Reinit ispvm_ui variables. +* +***************************************************************/ +static void ispvm_ui_reinit() +{ + g_pVMEFile = NULL; + g_usPreviousSize = 0; + g_usExpectedCRC = 0; +} + +/*************************************************************** +* +* main +* +***************************************************************/ + +int ispvme_main(int argc, char *argv[], int file_fd, name_info_t *info) +{ + unsigned short iCommandLineIndex = 0; + short siRetCode = 0; + char szExtension[5] = { 0 }; + char szCommandLineArg[300] = { 0 }; + short sicalibrate = 0; + + ispvm_ui_reinit(); + ivm_core_reinit(); + + //08/28/08 NN Added Calculate checksum support. + g_usChecksum = 0; + g_uiChecksumIndex = 0; + + if (file_fd < 0) { + dbg_print(is_debug_on, "Error:firmware upgrade ispvme dev parameters failed.\r\n"); + return -1; + } else { + g_file_fd = file_fd; + } + +#if 0 + ret = firmware_check_chip_name(g_file_fd, info); + if (ret != FIRMWARE_SUCCESS) { + dbg_print(is_debug_on, "Error: Failed to check chip name: %s.\n", file_name); + close(g_file_fd); + return firmware_error_type(FIRMWARE_ACTION_CHECK, info); + } + + ret = firmware_check_chip_verison(g_file_fd, info); + if (ret != FIRMWARE_SUCCESS) { + dbg_print(is_debug_on, "Error: Failed to check chip version: %s.\n", file_name); + close(g_file_fd); + return firmware_error_type(FIRMWARE_ACTION_CHECK, info); + } +#endif + + vme_out_string(" Lattice Semiconductor Corp.\n"); + vme_out_string("\n ispVME(tm) V"); + vme_out_string(VME_VERSION_NUMBER); + vme_out_string(" Copyright 1998-2011.\n"); + vme_out_string("\nFor daisy chain programming of all in-system programmable devices\n\n"); + + if (argc < 2) { + vme_out_string("\nUsage: vme [option] vme_file [vme_file]\n"); + vme_out_string("Example: vme vme_file1.vme vme_file2.vme\n"); + vme_out_string("option -c: do the calibration.\n"); + vme_out_string("Example: vme -c\n"); + vme_out_string("Example: vme -c vme_file1.vme vme_file2.vme\n"); + vme_out_string("\n\n"); + g_file_fd = -1; + /* Change return to determine whether the upgrade was successful */ + return -1; + } + for (iCommandLineIndex = 1; iCommandLineIndex < argc; iCommandLineIndex++) { + strncpy(szCommandLineArg, argv[iCommandLineIndex], sizeof(szCommandLineArg) - 1); + if (!strcmp(strlwr(szCommandLineArg), "-c") && (iCommandLineIndex == 1)) { + sicalibrate = 1; + } else if (!strcmp(strlwr(szCommandLineArg), "-c") && (iCommandLineIndex != 1)) { + vme_out_string("Error: calibrate option -c must be the first argument\n\n"); + g_file_fd = -1; + /* Change return to determine whether the upgrade was successful */ + return -1; + //exit(1); + } else { + strcpy(szExtension, &szCommandLineArg[strlen(szCommandLineArg) - 4]); + strlwr(szExtension); + if (strcmp(szExtension, ".vme")) { + vme_out_string("Error: VME files must end with the extension *.vme\n\n"); + g_file_fd = -1; + /* Change return to determine whether the upgrade was successful */ + return -1; + //exit(1); + } + } + } + siRetCode = 0; + + if (sicalibrate) { + calibration(); + } + for (iCommandLineIndex = 1; iCommandLineIndex < argc; iCommandLineIndex++) { /* Process all VME files sequentially */ + strcpy(szCommandLineArg, argv[iCommandLineIndex]); + if (!strcmp(strlwr(szCommandLineArg), "-c") && (iCommandLineIndex == 1)) { + + } else if (!strcmp(strlwr(szCommandLineArg), "-checksum")) { + + } else { + vme_out_string("Processing virtual machine file ("); + vme_out_string(szCommandLineArg); + vme_out_string(")......\n\n"); + siRetCode = ispVM(argv[iCommandLineIndex]); + if (siRetCode < 0) { + break; + } + } + } + + if (siRetCode < 0) { + error_handler(siRetCode, szCommandLineArg); + vme_out_string("Failed due to "); + vme_out_string(szCommandLineArg); + vme_out_string("\n\n"); + vme_out_string("+=======+\n"); + vme_out_string("| FAIL! |\n"); + vme_out_string("+=======+\n\n"); + } else { + vme_out_string("+=======+\n"); + vme_out_string("| PASS! |\n"); + vme_out_string("+=======+\n\n"); + //08/28/08 NN Added Calculate checksum support. + if (g_usChecksum != 0) { + g_usChecksum &= 0xFFFF; + printf("Data Checksum: %.4X\n\n", (unsigned int)g_usChecksum); + g_usChecksum = 0; + } + } + g_file_fd = -1; + /* Change return to determine whether the upgrade was successful */ + return siRetCode; + //exit(siRetCode); +} + +/* + * firmware_upgrade_ispvme + * function: ispvme firmware upgrade + * @file_fd: param[in] Upgrade devices fd + * @upgrade_file_name: param[in] Upgrade file name + * @info: param[in] Upgrade file information + * return value : success--FIRMWARE_SUCCESS, other fail return error code + */ +int firmware_upgrade_ispvme(int file_fd, char *upgrade_file_name, name_info_t *info) +{ + char *argv[2]; + int ret, rv, i, retry; + + argv[1] = upgrade_file_name; + + /* Initialize and enable */ + rv = ioctl(file_fd, FIRMWARE_JTAG_INIT,NULL); + if (rv < 0) { + vme_out_string("Failed to init GPIO.\n"); + return VME_ARGUMENT_FAILURE; + } + + i = 0; + retry = FIRMWARE_UPGRADE_RETRY_CNT; + + ret = 0; + while(i < retry) { + ret = ispvme_main(2, argv, file_fd, info); + if (ret < 0) { + i++; + dbg_print(is_debug_on, "%d times ispvme upgrade failed. ret %d.\n", i, ret); + continue; + } else { + dbg_print(is_debug_on, "ispvme upgrade success.\n"); + break; + } + } + + /* Upgrade completed, release */ + rv = ioctl(file_fd, FIRMWARE_JTAG_FINISH, NULL); + if (rv < 0) { + vme_out_string("Failed to release GPIO.\n"); + return VME_ARGUMENT_FAILURE; + } + + return ret; +} diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/fw_upg_gpio_vme/ivm_core.c b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/fw_upg_gpio_vme/ivm_core.c new file mode 100644 index 000000000000..540be481d35e --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/fw_upg_gpio_vme/ivm_core.c @@ -0,0 +1,3097 @@ +/*************************************************************** +* +* Lattice Semiconductor Corp. Copyright 2009 +* +* ispVME Embedded allows programming of Lattice's suite of FPGA +* devices on embedded systems through the JTAG port. The software +* is distributed in source code form and is open to re - distribution +* and modification where applicable. +* +* Revision History of ivm_core.c module: +* 4/25/06 ht Change some variables from unsigned short or int +* to long int to make the code compiler independent. +* 5/24/06 ht Support using RESET (TRST) pin as a special purpose +* control pin such as triggering the loading of known +* state exit. +* 3/6/07 ht added functions to support output to terminals +* +* 09/24/07 NN Type cast mismatch variables +* Moved the sclock() function to hardware.c +* 08/28/08 NN Added Calculate checksum support. +* 4/1/09 Nguyen replaced the recursive function call codes on +* the ispVMLCOUNT function +* +***************************************************************/ + +#include +#include +#include +#include + +/*************************************************************** +* +* Global variables used to specify the flow control and data type. +* +* g_usFlowControl: flow control register. Each bit in the +* register can potentially change the +* personality of the embedded engine. +* g_usDataType: holds the data type of the current row. +* +***************************************************************/ + +unsigned short g_usFlowControl = 0x0000; +unsigned short g_usDataType = 0x0000; + +/*************************************************************** +* +* Global variables used to specify the ENDDR and ENDIR. +* +* g_ucEndDR: the state that the device goes to after SDR. +* g_ucEndIR: the state that the device goes to after SIR. +* +***************************************************************/ + +unsigned char g_ucEndDR = DRPAUSE; +unsigned char g_ucEndIR = IRPAUSE; + +/*************************************************************** +* +* Global variables used to support header/trailer. +* +* g_usHeadDR: the number of lead devices in bypass. +* g_usHeadIR: the sum of IR length of lead devices. +* g_usTailDR: the number of tail devices in bypass. +* g_usTailIR: the sum of IR length of tail devices. +* +***************************************************************/ + +unsigned short g_usHeadDR = 0; +unsigned short g_usHeadIR = 0; +unsigned short g_usTailDR = 0; +unsigned short g_usTailIR = 0; + +/*************************************************************** +* +* Global variable to store the number of bits of data or instruction +* to be shifted into or out from the device. +* +***************************************************************/ + +unsigned short g_usiDataSize = 0; + +/*************************************************************** +* +* Stores the frequency. Default to 1 MHz. +* +***************************************************************/ + +int g_iFrequency = 1000; + +/*************************************************************** +* +* Stores the maximum amount of ram needed to hold a row of data. +* +***************************************************************/ + +unsigned short g_usMaxSize = 0; + +/*************************************************************** +* +* Stores the LSH or RSH value. +* +***************************************************************/ + +unsigned short g_usShiftValue = 0; + +/*************************************************************** +* +* Stores the current repeat loop value. +* +***************************************************************/ + +unsigned short g_usRepeatLoops = 0; + +/*************************************************************** +* +* Stores the current vendor. +* +***************************************************************/ + +signed char g_cVendor = LATTICE; + +/*************************************************************** +* +* Stores the VME file CRC. +* +***************************************************************/ + +unsigned short g_usCalculatedCRC = 0; + +/*************************************************************** +* +* Stores the Device Checksum. +* +***************************************************************/ +//08/28/08 NN Added Calculate checksum support. +unsigned long g_usChecksum = 0; +unsigned int g_uiChecksumIndex = 0; + +/*************************************************************** +* +* Stores the current state of the JTAG state machine. +* +***************************************************************/ + +signed char g_cCurrentJTAGState = 0; + +/*************************************************************** +* +* Global variables used to support looping. +* +* g_pucHeapMemory: holds the entire repeat loop. +* g_iHeapCounter: points to the current byte in the repeat loop. +* g_iHEAPSize: the current size of the repeat in bytes. +* +***************************************************************/ + +unsigned char *g_pucHeapMemory = NULL; +unsigned short g_iHeapCounter = 0; +unsigned short g_iHEAPSize = 0; + +/*************************************************************** +* +* Global variables used to support intelligent programming. +* +* g_usIntelDataIndex: points to the current byte of the +* intelligent buffer. +* g_usIntelBufferSize: holds the size of the intelligent +* buffer. +* +***************************************************************/ + +unsigned short g_usIntelDataIndex = 0; +unsigned short g_usIntelBufferSize = 0; + +/**************************************************************************** +* +* Holds the maximum size of each respective buffer. These variables are used +* to write the HEX files when converting VME to HEX. +* +*****************************************************************************/ + +unsigned short g_usTDOSize = 0; +unsigned short g_usMASKSize = 0; +unsigned short g_usTDISize = 0; +unsigned short g_usDMASKSize = 0; +unsigned short g_usLCOUNTSize = 0; +unsigned short g_usHDRSize = 0; +unsigned short g_usTDRSize = 0; +unsigned short g_usHIRSize = 0; +unsigned short g_usTIRSize = 0; +unsigned short g_usHeapSize = 0; + +/*************************************************************** +* +* Global variables used to store data. +* +* g_pucOutMaskData: local RAM to hold one row of MASK data. +* g_pucInData: local RAM to hold one row of TDI data. +* g_pucOutData: local RAM to hold one row of TDO data. +* g_pucHIRData: local RAM to hold the current SIR header. +* g_pucTIRData: local RAM to hold the current SIR trailer. +* g_pucHDRData: local RAM to hold the current SDR header. +* g_pucTDRData: local RAM to hold the current SDR trailer. +* g_pucIntelBuffer: local RAM to hold the current intelligent buffer. +* g_pucOutDMaskData: local RAM to hold one row of DMASK data. +* +***************************************************************/ + +unsigned char *g_pucOutMaskData = NULL, +*g_pucInData = NULL, +*g_pucOutData = NULL, +*g_pucHIRData = NULL, +*g_pucTIRData = NULL, +*g_pucHDRData = NULL, +*g_pucTDRData = NULL, +*g_pucIntelBuffer = NULL, +*g_pucOutDMaskData = NULL; + +/*************************************************************** +* +* JTAG state machine transition table. +* +***************************************************************/ + +struct { + unsigned char CurState; /* From this state */ + unsigned char NextState; /* Step to this state */ + unsigned char Pattern; /* The tragetory of TMS */ + unsigned char Pulses; /* The number of steps */ +} g_JTAGTransistions[25] = { + { RESET, RESET, 0xFC, 6 }, /* Transitions from RESET */ + { RESET, IDLE, 0x00, 1 }, + { RESET, DRPAUSE, 0x50, 5 }, + { RESET, IRPAUSE, 0x68, 6 }, + { IDLE, RESET, 0xE0, 3 }, /* Transitions from IDLE */ + { IDLE, DRPAUSE, 0xA0, 4 }, + { IDLE, IRPAUSE, 0xD0, 5 }, + { DRPAUSE, RESET, 0xF8, 5 }, /* Transitions from DRPAUSE */ + { DRPAUSE, IDLE, 0xC0, 3 }, + { DRPAUSE, IRPAUSE, 0xF4, 7 }, + { DRPAUSE, DRPAUSE, 0xE8, 6 }, /* 06/14/06 Support POLING STATUS LOOP*/ + { IRPAUSE, RESET, 0xF8, 5 }, /* Transitions from IRPAUSE */ + { IRPAUSE, IDLE, 0xC0, 3 }, + { IRPAUSE, DRPAUSE, 0xE8, 6 }, + { DRPAUSE, SHIFTDR, 0x80, 2 }, /* Extra transitions using SHIFTDR */ + { IRPAUSE, SHIFTDR, 0xE0, 5 }, + { SHIFTDR, DRPAUSE, 0x80, 2 }, + { SHIFTDR, IDLE, 0xC0, 3 }, + { IRPAUSE, SHIFTIR, 0x80, 2 }, /* Extra transitions using SHIFTIR */ + { SHIFTIR, IRPAUSE, 0x80, 2 }, + { SHIFTIR, IDLE, 0xC0, 3 }, + { DRPAUSE, DRCAPTURE, 0xE0, 4 }, /* 11/15/05 Support DRCAPTURE*/ + { DRCAPTURE, DRPAUSE, 0x80, 2 }, + { IDLE, DRCAPTURE, 0x80, 2 }, + { IRPAUSE, DRCAPTURE, 0xE0, 4 } +}; + +/*************************************************************** +* +* List to hold all LVDS pairs. +* +***************************************************************/ + +LVDSPair *g_pLVDSList = NULL; +unsigned short g_usLVDSPairCount = 0; + +/*************************************************************** +* +* Function prototypes. +* +***************************************************************/ + +signed char ispVMCode(); +signed char ispVMDataCode(); +long int ispVMDataSize(); +void ispVMData(unsigned char *Data); +signed char ispVMShift(signed char Code); +signed char ispVMAmble(signed char Code); +signed char ispVMLoop(unsigned short a_usLoopCount); +signed char ispVMBitShift(signed char mode, unsigned short bits); +void ispVMComment(unsigned short a_usCommentSize); +void ispVMHeader(unsigned short a_usHeaderSize); +signed char ispVMLCOUNT(unsigned short a_usCountSize); +void ispVMClocks(unsigned short Clocks); +void ispVMBypass(signed char ScanType, unsigned short Bits); +void ispVMStateMachine(signed char NextState); +void ispVMStart(); +void ispVMEnd(); +signed char ispVMSend(unsigned short int); +signed char ispVMRead(unsigned short int); +signed char ispVMReadandSave(unsigned short int); +signed char ispVMProcessLVDS(unsigned short a_usLVDSCount); + +/*************************************************************** +* +* External variables and functions in ispvm_ui.c module +* +***************************************************************/ +extern void vme_out_char(unsigned char charOut); +extern void vme_out_hex(unsigned char hexOut); +extern void vme_out_string(char *stringOut); +extern unsigned char GetByte(); +extern void ispVMMemManager(signed char types, unsigned short size); + +/*************************************************************** +* +* External variables and functions in hardware.c module +* +***************************************************************/ +extern void ispVMDelay(unsigned short int a_usMicroSecondDelay); +extern unsigned char readPort(); +extern void writePort(unsigned char pins, unsigned char value); +extern void sclock(); +extern signed char g_cCurrentJTAGState; +#ifdef VME_DEBUG + +/*************************************************************** +* +* GetState +* +* Returns the state as a string based on the opcode. Only used +* for debugging purposes. +* +***************************************************************/ + +const char* GetState(unsigned char a_ucState) +{ + switch (a_ucState) { + case RESET: + return ("RESET"); + case IDLE: + return ("IDLE"); + case IRPAUSE: + return ("IRPAUSE"); + case DRPAUSE: + return ("DRPAUSE"); + case SHIFTIR: + return ("SHIFTIR"); + case SHIFTDR: + return ("SHIFTDR"); + case DRCAPTURE: /* 11/15/05 support DRCAPTURE*/ + return ("DRCAPTURE"); + default: + break; + } + + return 0; +} + +/*************************************************************** +* +* PrintData +* +* Prints the data. Only used for debugging purposes. +* +***************************************************************/ + +void PrintData(unsigned short a_iDataSize, unsigned char *a_pucData) +{ + //09/11/07 NN added local variables initialization + unsigned short usByteSize = 0; + unsigned short usBitIndex = 0; + signed short usByteIndex = 0; + unsigned char ucByte = 0; + unsigned char ucFlipByte = 0; + + if (a_iDataSize % 8) { + //09/11/07 NN Type cast mismatch variables + usByteSize = (unsigned short)(a_iDataSize / 8 + 1); + } else { + //09/11/07 NN Type cast mismatch variables + usByteSize = (unsigned short)(a_iDataSize / 8);// 4 + } + printf("("); + //09/11/07 NN Type cast mismatch variables + for (usByteIndex = (signed short)(usByteSize - 1); usByteIndex >= 0; usByteIndex--) { + ucByte = a_pucData[usByteIndex]; + ucFlipByte = 0x00; + + /*************************************************************** + * + * Flip each byte. + * + ***************************************************************/ + + for (usBitIndex = 0; usBitIndex < 8; usBitIndex++) { + ucFlipByte <<= 1; + if (ucByte & 0x1) { + ucFlipByte |= 0x1; + } + + ucByte >>= 1; + } + + /*************************************************************** + * + * Print the flipped byte. + * + ***************************************************************/ + + printf("%.02X", ucFlipByte); + if ((usByteSize - usByteIndex) % 40 == 39) { + printf("\n\t\t"); + } + if (usByteIndex < 0) + break; + } + printf(")"); +} +#endif //VME_DEBUG + +/*************************************************************** +* +* ispVMDataSize +* +* Returns a VME-encoded number, usually used to indicate the +* bit length of an SIR/SDR command. +* +***************************************************************/ + +long int ispVMDataSize() +{ + //09/11/07 NN added local variables initialization + long int iSize = 0; + signed char cCurrentByte = 0; + signed char cIndex = 0; + cIndex = 0; + + while ((cCurrentByte = GetByte()) & 0x80) { + iSize |= ((long int)(cCurrentByte & 0x7F)) << cIndex; + cIndex += 7; + } + iSize |= ((long int)(cCurrentByte & 0x7F)) << cIndex; + + return iSize; +} + +/*************************************************************** +* +* ispVMCode +* +* This is the heart of the embedded engine. All the high-level opcodes +* are extracted here. Once they have been identified, then it +* will call other functions to handle the processing. +* +***************************************************************/ + +signed char ispVMCode() +{ + //09/11/07 NN added local variables initialization + unsigned short iRepeatSize = 0; + signed char cOpcode = 0; + signed char cRetCode = 0; + unsigned char ucState = 0; + unsigned short usDelay = 0; + unsigned short usToggle = 0; + unsigned char usByte = 0; + + /*************************************************************** + * + * Check the compression flag only if this is the first time + * this function is entered. Do not check the compression flag if + * it is being called recursively from other functions within + * the embedded engine. + * + ***************************************************************/ + + if (!(g_usDataType & LHEAP_IN) && !(g_usDataType & HEAP_IN)) { + usByte = GetByte(); + if (usByte == 0xf1) { + g_usDataType |= COMPRESS; + } else if (usByte == 0xf2) { + g_usDataType &= ~COMPRESS; + } else { + return VME_INVALID_FILE; + } + } + + /*************************************************************** + * + * Begin looping through all the VME opcodes. + * + ***************************************************************/ + while ((cOpcode = GetByte()) >= 0) { + switch (cOpcode) { + case STATE: + + /*************************************************************** + * + * Step the JTAG state machine. + * + ***************************************************************/ + + ucState = GetByte(); + /*************************************************************** + * + * Step the JTAG state machine to DRCAPTURE to support Looping. + * + ***************************************************************/ + + if ((g_usDataType & LHEAP_IN) && + (ucState == DRPAUSE) && + (g_cCurrentJTAGState == ucState)) { + ispVMStateMachine(DRCAPTURE); + } + + ispVMStateMachine(ucState); + +#ifdef VME_DEBUG + if (g_usDataType & LHEAP_IN) { + printf("LDELAY %s ", GetState(ucState)); + } else { + printf("STATE %s;\n", GetState(ucState)); + } +#endif //VME_DEBUG + break; + case SIR: + case SDR: + case XSDR: + +#ifdef VME_DEBUG + switch (cOpcode) { + case SIR: + printf("SIR "); + break; + case SDR: + case XSDR: + if (g_usDataType & LHEAP_IN) { + printf("LSDR "); + } else { + printf("SDR "); + } + break; + } +#endif //VME_DEBUG + /*************************************************************** + * + * Shift in data into the device. + * + ***************************************************************/ + cRetCode = ispVMShift(cOpcode); + if (cRetCode != 0) { + return (cRetCode); + } + break; + case WAIT: + + /*************************************************************** + * + * Observe delay. + * + ***************************************************************/ + + //09/11/07 NN Type cast mismatch variables + usDelay = (unsigned short)ispVMDataSize(); + ispVMDelay(usDelay); + +#ifdef VME_DEBUG + if (usDelay & 0x8000) { + + /*************************************************************** + * + * Since MSB is set, the delay time must be decoded to + * millisecond. The SVF2VME encodes the MSB to represent + * millisecond. + * + ***************************************************************/ + + usDelay &= ~0x8000; + if (g_usDataType & LHEAP_IN) { + printf("%.2E SEC;\n", (float)usDelay / 1000); + } else { + printf("RUNTEST %.2E SEC;\n", (float)usDelay / 1000); + } + } else { + + /*************************************************************** + * + * Since MSB is not set, the delay time is given as microseconds. + * + ***************************************************************/ + + if (g_usDataType & LHEAP_IN) { + printf("%.2E SEC;\n", (float)usDelay / 1000000); + } else { + printf("RUNTEST %.2E SEC;\n", (float)usDelay / 1000000); + } + } +#endif //VME_DEBUG + break; + case TCK: + + /*************************************************************** + * + * Issue clock toggles. + * + ***************************************************************/ + + //09/11/07 NN Type cast mismatch variables + usToggle = (unsigned short)ispVMDataSize(); + ispVMClocks(usToggle); + +#ifdef VME_DEBUG + printf("RUNTEST %d TCK;\n", usToggle); +#endif //VME_DEBUG + break; + case ENDDR: + + /*************************************************************** + * + * Set the ENDDR. + * + ***************************************************************/ + + g_ucEndDR = GetByte(); + +#ifdef VME_DEBUG + printf("ENDDR %s;\n", GetState(g_ucEndDR)); +#endif //VME_DEBUG + break; + case ENDIR: + + /*************************************************************** + * + * Set the ENDIR. + * + ***************************************************************/ + + g_ucEndIR = GetByte(); + +#ifdef VME_DEBUG + printf("ENDIR %s;\n", GetState(g_ucEndIR)); +#endif //VME_DEBUG + break; + case HIR: + case TIR: + case HDR: + case TDR: + +#ifdef VME_DEBUG + switch (cOpcode) { + case HIR: + printf("HIR "); + break; + case TIR: + printf("TIR "); + break; + case HDR: + printf("HDR "); + break; + case TDR: + printf("TDR "); + break; + } +#endif //VME_DEBUG + + /*************************************************************** + * + * Set the header/trailer of the device in order to bypass + * successfully. + * + ***************************************************************/ + + cRetCode = ispVMAmble(cOpcode); + if (cRetCode != 0) { + return (cRetCode); + } + +#ifdef VME_DEBUG + printf(";\n"); +#endif //VME_DEBUG + break; + case MEM: + + /*************************************************************** + * + * The maximum RAM required to support processing one row of the + * VME file. + * + ***************************************************************/ + + //09/11/07 NN Type cast mismatch variables + g_usMaxSize = (unsigned short)ispVMDataSize(); + +#ifdef VME_DEBUG + printf("// MEMSIZE %d\n", g_usMaxSize); +#endif //VME_DEBUG + break; + case VENDOR: + + /*************************************************************** + * + * Set the VENDOR type. + * + ***************************************************************/ + + cOpcode = GetByte(); + switch (cOpcode) { + case LATTICE: +#ifdef VME_DEBUG + printf("// VENDOR LATTICE\n"); +#endif //VME_DEBUG + g_cVendor = LATTICE; + break; + case ALTERA: +#ifdef VME_DEBUG + printf("// VENDOR ALTERA\n"); +#endif //VME_DEBUG + g_cVendor = ALTERA; + break; + case XILINX: +#ifdef VME_DEBUG + printf("// VENDOR XILINX\n"); +#endif //VME_DEBUG + g_cVendor = XILINX; + break; + default: + break; + } + break; + case SETFLOW: + + /*************************************************************** + * + * Set the flow control. Flow control determines the personality + * of the embedded engine. + * + ***************************************************************/ + + //09/11/07 NN Type cast mismatch variables + g_usFlowControl |= (unsigned short)ispVMDataSize(); + break; + case RESETFLOW: + + /*************************************************************** + * + * Unset the flow control. + * + ***************************************************************/ + + //09/11/07 NN Type cast mismatch variables + g_usFlowControl &= (unsigned short)~(ispVMDataSize()); + break; + case HEAP: + + /*************************************************************** + * + * Allocate heap size to store loops. + * + ***************************************************************/ + + cRetCode = GetByte(); + if (cRetCode != SECUREHEAP) { + return VME_INVALID_FILE; + } + //09/11/07 NN Type cast mismatch variables + g_iHEAPSize = (unsigned short)ispVMDataSize(); + + /**************************************************************************** + * + * Store the maximum size of the HEAP buffer. Used to convert VME to HEX. + * + *****************************************************************************/ + + if (g_iHEAPSize > g_usHeapSize) { + g_usHeapSize = g_iHEAPSize; + } + + ispVMMemManager(HEAP, (unsigned short)g_iHEAPSize); + break; + case REPEAT: + + /*************************************************************** + * + * Execute loops. + * + ***************************************************************/ + + g_usRepeatLoops = 0; + + //09/11/07 NN Type cast mismatch variables + iRepeatSize = (unsigned short)ispVMDataSize(); + + cRetCode = ispVMLoop((unsigned short)iRepeatSize); + if (cRetCode != 0) { + return (cRetCode); + } + break; + case ENDLOOP: + + /*************************************************************** + * + * Exit point from processing loops. + * + ***************************************************************/ + + return (cRetCode); + case ENDVME: + + /*************************************************************** + * + * The only valid exit point that indicates end of programming. + * + ***************************************************************/ + + return (cRetCode); + case SHR: + + /*************************************************************** + * + * Right-shift address. + * + ***************************************************************/ + + g_usFlowControl |= SHIFTRIGHT; + + //09/11/07 NN Type cast mismatch variables + g_usShiftValue = (unsigned short)(g_usRepeatLoops * (unsigned short)GetByte()); + break; + case SHL: + + /*************************************************************** + * + * Left-shift address. + * + ***************************************************************/ + + g_usFlowControl |= SHIFTLEFT; + + //09/11/07 NN Type cast mismatch variables + g_usShiftValue = (unsigned short)(g_usRepeatLoops * (unsigned short)GetByte()); + break; + case FREQUENCY: + + /*************************************************************** + * + * Set the frequency. + * + ***************************************************************/ + + //09/11/07 NN Type cast mismatch variables + g_iFrequency = (int)(ispVMDataSize()); + //10/23/08 NN changed to check if the frequency smaller than 1000 + if (g_iFrequency >= 1000) { + g_iFrequency = g_iFrequency / 1000; + if (g_iFrequency == 1) + g_iFrequency = 1000; +#ifdef VME_DEBUG + printf("FREQUENCY %.2E HZ;\n", (float)g_iFrequency * 1000); +#endif //VME_DEBUG + } else { + if (g_iFrequency == 0) + g_iFrequency = 1000; +#ifdef VME_DEBUG + printf("FREQUENCY %.2E HZ;\n", (float)g_iFrequency); +#endif //VME_DEBUG + } + break; + case LCOUNT: + + /*************************************************************** + * + * Process LCOUNT command. + * + ***************************************************************/ + + cRetCode = ispVMLCOUNT((unsigned short)ispVMDataSize()); + if (cRetCode != 0) { + return (cRetCode); + } + break; + case VUES: + + /*************************************************************** + * + * Set the flow control to verify USERCODE. + * + ***************************************************************/ + + g_usFlowControl |= VERIFYUES; + break; + case COMMENT: + + /*************************************************************** + * + * Display comment. + * + ***************************************************************/ + + ispVMComment((unsigned short)ispVMDataSize()); + break; + case LVDS: + + /*************************************************************** + * + * Process LVDS command. + * + ***************************************************************/ + + ispVMProcessLVDS((unsigned short)ispVMDataSize()); + break; + case HEADER: + + /*************************************************************** + * + * Discard header. + * + ***************************************************************/ + + ispVMHeader((unsigned short)ispVMDataSize()); + break; + /* 03/14/06 Support Toggle ispENABLE signal*/ + case ispEN: + ucState = GetByte(); + if ((ucState == ON) || (ucState == 0x01)) + writePort(JTAG_ENABLE, 0x01); + else + writePort(JTAG_ENABLE, 0x00); + ispVMDelay(1); + break; + /* 05/24/06 support Toggle TRST pin*/ + case TRST: + ucState = GetByte(); + if (ucState == 0x01) + writePort(JTAG_TRST, 0x01); + else + writePort(JTAG_TRST, 0x00); + ispVMDelay(1); + break; + default: + + /*************************************************************** + * + * Invalid opcode encountered. + * + ***************************************************************/ + +#ifdef VME_DEBUG + printf("\nINVALID OPCODE: 0x%.2X\n", cOpcode); +#endif //VME_DEBUG + + return VME_INVALID_FILE; + } + } + + /*************************************************************** + * + * Invalid exit point. Processing the token 'ENDVME' is the only + * valid way to exit the embedded engine. + * + ***************************************************************/ + + return (VME_INVALID_FILE); +} + +/*************************************************************** +* +* ispVMDataCode +* +* Processes the TDI/TDO/MASK/DMASK etc of an SIR/SDR command. +* +***************************************************************/ + +signed char ispVMDataCode() +{ + //09/11/07 NN added local variables initialization + signed char cDataByte = 0; + signed char siDataSource = 0; /*source of data from file by default*/ + + if (g_usDataType & HEAP_IN) { + siDataSource = 1; /*the source of data from memory*/ + } + + /**************************************************************************** + * + * Clear the data type register. + * + *****************************************************************************/ + + g_usDataType &= ~(MASK_DATA + TDI_DATA + TDO_DATA + DMASK_DATA + CMASK_DATA); + + /**************************************************************************** + * + * Iterate through SIR/SDR command and look for TDI, TDO, MASK, etc. + * + *****************************************************************************/ + + while ((cDataByte = GetByte()) >= 0) { + + ispVMMemManager(cDataByte, g_usMaxSize); + switch (cDataByte) { + case TDI: + + /**************************************************************************** + * + * Store the maximum size of the TDI buffer. Used to convert VME to HEX. + * + *****************************************************************************/ + + if (g_usiDataSize > g_usTDISize) { + g_usTDISize = g_usiDataSize; + } + /**************************************************************************** + * + * Updated data type register to indicate that TDI data is currently being + * used. Process the data in the VME file into the TDI buffer. + * + *****************************************************************************/ + + g_usDataType |= TDI_DATA; + ispVMData(g_pucInData); + break; + case XTDO: + + /**************************************************************************** + * + * Store the maximum size of the TDO buffer. Used to convert VME to HEX. + * + *****************************************************************************/ + + if (g_usiDataSize > g_usTDOSize) { + g_usTDOSize = g_usiDataSize; + } + + /**************************************************************************** + * + * Updated data type register to indicate that TDO data is currently being + * used. + * + *****************************************************************************/ + + g_usDataType |= TDO_DATA; + break; + case TDO: + + /**************************************************************************** + * + * Store the maximum size of the TDO buffer. Used to convert VME to HEX. + * + *****************************************************************************/ + + if (g_usiDataSize > g_usTDOSize) { + g_usTDOSize = g_usiDataSize; + } + + /**************************************************************************** + * + * Updated data type register to indicate that TDO data is currently being + * used. Process the data in the VME file into the TDO buffer. + * + *****************************************************************************/ + + g_usDataType |= TDO_DATA; + ispVMData(g_pucOutData); + break; + case MASK: + + /**************************************************************************** + * + * Store the maximum size of the MASK buffer. Used to convert VME to HEX. + * + *****************************************************************************/ + + if (g_usiDataSize > g_usMASKSize) { + g_usMASKSize = g_usiDataSize; + } + + /**************************************************************************** + * + * Updated data type register to indicate that MASK data is currently being + * used. Process the data in the VME file into the MASK buffer. + * + *****************************************************************************/ + + g_usDataType |= MASK_DATA; + ispVMData(g_pucOutMaskData); + break; + case DMASK: + + /**************************************************************************** + * + * Store the maximum size of the DMASK buffer. Used to convert VME to HEX. + * + *****************************************************************************/ + + if (g_usiDataSize > g_usDMASKSize) { + g_usDMASKSize = g_usiDataSize; + } + + /**************************************************************************** + * + * Updated data type register to indicate that DMASK data is currently being + * used. Process the data in the VME file into the DMASK buffer. + * + *****************************************************************************/ + + g_usDataType |= DMASK_DATA; + ispVMData(g_pucOutDMaskData); + break; + case CMASK: + + /**************************************************************************** + * + * Updated data type register to indicate that CMASK data is currently being + * used. Process the data in the VME file into the CMASK buffer. + * + *****************************************************************************/ + + g_usDataType |= CMASK_DATA; + ispVMData(g_pucOutMaskData); + break; + case CONTINUE: + return (0); + default: + + /**************************************************************************** + * + * Encountered invalid opcode. + * + *****************************************************************************/ + + return (VME_INVALID_FILE); + } + + switch (cDataByte) { + case TDI: + + /**************************************************************************** + * + * Left bit shift. Used when performing algorithm looping. + * + *****************************************************************************/ + + if (g_usFlowControl & SHIFTLEFT) { + ispVMBitShift(SHL, g_usShiftValue); + g_usFlowControl &= ~SHIFTLEFT; + } + + /**************************************************************************** + * + * Right bit shift. Used when performing algorithm looping. + * + *****************************************************************************/ + + if (g_usFlowControl & SHIFTRIGHT) { + ispVMBitShift(SHR, g_usShiftValue); + g_usFlowControl &= ~SHIFTRIGHT; + } + default: + break; + } + + if (siDataSource) { + g_usDataType |= HEAP_IN; /*restore data from memory*/ + } + } + + if (siDataSource) { /*fetch data from heap memory upon return*/ + g_usDataType |= HEAP_IN; + } + + if (cDataByte < 0) { + + /**************************************************************************** + * + * Encountered invalid opcode. + * + *****************************************************************************/ + + return (VME_INVALID_FILE); + } else { + return (0); + } +} + +/*************************************************************** +* +* ispVMData +* Extract one row of data operand from the current data type opcode. Perform +* the decompression if necessary. Extra RAM is not required for the +* decompression process. The decompression scheme employed in this module +* is on row by row basis. The format of the data stream: +* [compression code][compressed data stream] +* 0x00 --No compression +* 0x01 --Compress by 0x00. +* Example: +* Original stream: 0x000000000000000000000001 +* Compressed stream: 0x01000901 +* Detail: 0x01 is the code, 0x00 is the key, +* 0x09 is the count of 0x00 bytes, +* 0x01 is the uncompressed byte. +* 0x02 --Compress by 0xFF. +* Example: +* Original stream: 0xFFFFFFFFFFFFFFFFFFFFFF01 +* Compressed stream: 0x02FF0901 +* Detail: 0x02 is the code, 0xFF is the key, +* 0x09 is the count of 0xFF bytes, +* 0x01 is the uncompressed byte. +* 0x03 +* : : +* 0xFE -- Compress by nibble blocks. +* Example: +* Original stream: 0x84210842108421084210 +* Compressed stream: 0x0584210 +* Detail: 0x05 is the code, means 5 nibbles block. +* 0x84210 is the 5 nibble blocks. +* The whole row is 80 bits given by g_usiDataSize. +* The number of times the block repeat itself +* is found by g_usiDataSize/(4*0x05) which is 4. +* 0xFF -- Compress by the most frequently happen byte. +* Example: +* Original stream: 0x04020401030904040404 +* Compressed stream: 0xFF04(0,1,0x02,0,1,0x01,1,0x03,1,0x09,0,0,0) +* or: 0xFF044090181C240 +* Detail: 0xFF is the code, 0x04 is the key. +* a bit of 0 represent the key shall be put into +* the current bit position and a bit of 1 +* represent copying the next of 8 bits of data +* in. +* +***************************************************************/ + +void ispVMData(unsigned char *ByteData) +{ + //09/11/07 NN added local variables initialization + unsigned short size = 0; + unsigned short i, j, m, getData = 0; + unsigned char cDataByte = 0; + unsigned char compress = 0; + unsigned short FFcount = 0; + unsigned char compr_char = 0xFF; + unsigned short index = 0; + signed char compression = 0; + + /*convert number in bits to bytes*/ + if (g_usiDataSize % 8 > 0) { + //09/11/07 NN Type cast mismatch variables + size = (unsigned short)(g_usiDataSize / 8 + 1); + } else { + //09/11/07 NN Type cast mismatch variables + size = (unsigned short)(g_usiDataSize / 8); + } + + /* If there is compression, then check if compress by key of 0x00 or 0xFF + or by other keys or by nibble blocks*/ + + if (g_usDataType & COMPRESS) { + compression = 1; + if (((compress = GetByte()) == VAR) && (g_usDataType & HEAP_IN)) { + getData = 1; + g_usDataType &= ~(HEAP_IN); + compress = GetByte(); + } + + switch (compress) { + case 0x00: + /* No compression */ + compression = 0; + break; + case 0x01: + /* Compress by byte 0x00 */ + compr_char = 0x00; + break; + case 0x02: + /* Compress by byte 0xFF */ + compr_char = 0xFF; + break; + case 0xFF: + /* Huffman encoding */ + compr_char = GetByte(); + i = 8; + for (index = 0; index < size; index++) { + ByteData[index] = 0x00; + if (i > 7) { + cDataByte = GetByte(); + i = 0; + } + if ((cDataByte << i++) & 0x80) + m = 8; + else { + ByteData[index] = compr_char; + m = 0; + } + + for (j = 0; j < m; j++) { + if (i > 7) { + cDataByte = GetByte(); + i = 0; + } + ByteData[index] |= ((cDataByte << i++) & 0x80) >> j; + } + } + size = 0; + break; + default: + for (index = 0; index < size; index++) + ByteData[index] = 0x00; + for (index = 0; index < compress; index++) { + if (index % 2 == 0) + cDataByte = GetByte(); + for (i = 0; i < size * 2 / compress; i++) { + //09/11/07 NN Type cast mismatch variables + j = (unsigned short)(index + (i * (unsigned short)compress)); + /*clear the nibble to zero first*/ + if (j % 2) { + if (index % 2) + ByteData[j / 2] |= cDataByte & 0x0F; + else + ByteData[j / 2] |= cDataByte >> 4; + } else { + if (index % 2) + ByteData[j / 2] |= cDataByte << 4; + else + ByteData[j / 2] |= cDataByte & 0xF0; + } + } + } + size = 0; + break; + } + } + + FFcount = 0; + + /* Decompress by byte 0x00 or 0xFF */ + for (index = 0; index < size; index++) { + if (FFcount <= 0) { + cDataByte = GetByte(); + if ((cDataByte == VAR) && (g_usDataType & HEAP_IN) && !getData && !(g_usDataType & COMPRESS)) { + getData = 1; + g_usDataType &= ~(HEAP_IN); + cDataByte = GetByte(); + } + ByteData[index] = cDataByte; + if ((compression) && (cDataByte == compr_char)) /*decompression is on*/ + //09/11/07 NN Type cast mismatch variables + FFcount = (unsigned short)ispVMDataSize(); /*The number of 0xFF or 0x00 bytes*/ + } else { + FFcount--; /*Use up the 0xFF chain first*/ + ByteData[index] = compr_char; + } + } + + if (getData) { + g_usDataType |= HEAP_IN; + getData = 0; + } +} + +/*************************************************************** +* +* ispVMShift +* +* Processes the SDR/XSDR/SIR commands. +* +***************************************************************/ + +signed char ispVMShift(signed char a_cCode) +{ + //09/11/07 NN added local variables initialization + unsigned short iDataIndex = 0; + unsigned short iReadLoop = 0; + signed char cRetCode = 0; + + cRetCode = 0; + //09/11/07 NN Type cast mismatch variables + g_usiDataSize = (unsigned short)ispVMDataSize(); + + g_usDataType &= ~(SIR_DATA + EXPRESS + SDR_DATA); /*clear the flags first*/ + + switch (a_cCode) { + case SIR: + g_usDataType |= SIR_DATA; + /* 1/15/04 If performing cascading, then go directly to SHIFTIR. Else, + go to IRPAUSE before going to SHIFTIR */ + if (g_usFlowControl & CASCADE) { + ispVMStateMachine(SHIFTIR); + } else { + ispVMStateMachine(IRPAUSE); + ispVMStateMachine(SHIFTIR); + if (g_usHeadIR > 0) { + ispVMBypass(HIR, g_usHeadIR); + sclock(); + } + } + break; + case XSDR: + g_usDataType |= EXPRESS; /*mark simultaneous in and out*/ + case SDR: + g_usDataType |= SDR_DATA; + /* 1/15/04 If already in SHIFTDR, then do not move state or shift in header. + This would imply that the previously shifted frame was a cascaded frame. */ + if (g_cCurrentJTAGState != SHIFTDR) { + /* 1/15/04 If performing cascading, then go directly to SHIFTDR. Else, + go to DRPAUSE before going to SHIFTDR */ + if (g_usFlowControl & CASCADE) { + if (g_cCurrentJTAGState == DRPAUSE) { + ispVMStateMachine(SHIFTDR); + /* 1/15/04 If cascade flag has been set and the current state is + DRPAUSE, this implies that the first cascaded frame is about to + be shifted in. The header must be shifted prior to shifting + the first cascaded frame. */ + if (g_usHeadDR > 0) { + ispVMBypass(HDR, g_usHeadDR); + sclock(); + } + } else { + ispVMStateMachine(SHIFTDR); + } + } else { + ispVMStateMachine(DRPAUSE); + ispVMStateMachine(SHIFTDR); + if (g_usHeadDR > 0) { + ispVMBypass(HDR, g_usHeadDR); + sclock(); + } + } + } + break; + default: + return (VME_INVALID_FILE); + } + + cRetCode = ispVMDataCode(); + if (cRetCode != 0) { + return (VME_INVALID_FILE); + } + +#ifdef VME_DEBUG + if (g_usDataType & TDI_DATA) { + printf("\n\t\tTDI "); + PrintData(g_usiDataSize, g_pucInData); + } + + if (g_usDataType & TDO_DATA) { + printf("\n\t\tTDO "); + PrintData(g_usiDataSize, g_pucOutData); + } + + if (g_usDataType & MASK_DATA) { + printf("\n\t\tMASK "); + PrintData(g_usiDataSize, g_pucOutMaskData); + } + + if (g_usDataType & DMASK_DATA) { + printf("\n\t\tDMASK "); + PrintData(g_usiDataSize, g_pucOutDMaskData); + } + + printf(";\n"); +#endif //VME_DEBUG + if (g_usDataType & TDO_DATA || g_usDataType & DMASK_DATA) { + if (g_usDataType & DMASK_DATA) { + + cRetCode = ispVMReadandSave(g_usiDataSize); + + if (!cRetCode) { + if (g_usTailDR > 0) { + sclock(); + ispVMBypass(TDR, g_usTailDR); + } + ispVMStateMachine(DRPAUSE); + ispVMStateMachine(SHIFTDR); + if (g_usHeadDR > 0) { + ispVMBypass(HDR, g_usHeadDR); + sclock(); + } + for (iDataIndex = 0; iDataIndex < g_usiDataSize / 8 + 1; iDataIndex++) + g_pucInData[iDataIndex] = g_pucOutData[iDataIndex]; + g_usDataType &= ~(TDO_DATA + DMASK_DATA); + cRetCode = ispVMSend(g_usiDataSize); + } + } else { + + cRetCode = ispVMRead(g_usiDataSize); + if (cRetCode == -1 && g_cVendor == XILINX) { + for (iReadLoop = 0; iReadLoop < 30; iReadLoop++) { + cRetCode = ispVMRead(g_usiDataSize); + if (!cRetCode) { + break; + } else { + ispVMStateMachine(DRPAUSE); /*Always DRPAUSE*/ + /*Bypass other devices when appropriate*/ + ispVMBypass(TDR, g_usTailDR); + ispVMStateMachine(g_ucEndDR); + ispVMStateMachine(IDLE); + ispVMDelay(1000); + } + } + } + } + } else { /*TDI only*/ + cRetCode = ispVMSend(g_usiDataSize); + + } + + /*transfer the input data to the output buffer for the next verify*/ + if ((g_usDataType & EXPRESS) || (a_cCode == SDR)) { + if (g_pucOutData) { + for (iDataIndex = 0; iDataIndex < g_usiDataSize / 8 + 1; iDataIndex++) + g_pucOutData[iDataIndex] = g_pucInData[iDataIndex]; + } + } + + switch (a_cCode) { + case SIR: + /* 1/15/04 If not performing cascading, then shift ENDIR */ + if (!(g_usFlowControl & CASCADE)) { + if (g_usTailIR > 0) { + sclock(); + ispVMBypass(TIR, g_usTailIR); + } + ispVMStateMachine(g_ucEndIR); + } + break; + case XSDR: + case SDR: + /* 1/15/04 If not performing cascading, then shift ENDDR */ + if (!(g_usFlowControl & CASCADE)) { + if (g_usTailDR > 0) { + sclock(); + ispVMBypass(TDR, g_usTailDR); + } + ispVMStateMachine(g_ucEndDR); + } + break; + default: + break; + } + + return (cRetCode); +} + +/*************************************************************** +* +* ispVMAmble +* +* This routine is to extract Header and Trailer parameter for SIR and +* SDR operations. +* +* The Header and Trailer parameter are the pre-amble and post-amble bit +* stream need to be shifted into TDI or out of TDO of the devices. Mostly +* is for the purpose of bypassing the leading or trailing devices. ispVM +* supports only shifting data into TDI to bypass the devices. +* +* For a single device, the header and trailer parameters are all set to 0 +* as default by ispVM. If it is for multiple devices, the header and trailer +* value will change as specified by the VME file. +* +***************************************************************/ + +signed char ispVMAmble(signed char Code) +{ + signed char compress = 0; + //09/11/07 NN Type cast mismatch variables + g_usiDataSize = (unsigned short)ispVMDataSize(); + +#ifdef VME_DEBUG + printf("%d", g_usiDataSize); +#endif //VME_DEBUG + + if (g_usiDataSize) { + + /**************************************************************************** + * + * Discard the TDI byte and set the compression bit in the data type register + * to false if compression is set because TDI data after HIR/HDR/TIR/TDR is not + * compressed. + * + *****************************************************************************/ + + GetByte(); + if (g_usDataType & COMPRESS) { + g_usDataType &= ~(COMPRESS); + compress = 1; + } + } + + switch (Code) { + case HIR: + + /**************************************************************************** + * + * Store the maximum size of the HIR buffer. Used to convert VME to HEX. + * + *****************************************************************************/ + + if (g_usiDataSize > g_usHIRSize) { + g_usHIRSize = g_usiDataSize; + } + + /**************************************************************************** + * + * Assign the HIR value and allocate memory. + * + *****************************************************************************/ + + g_usHeadIR = g_usiDataSize; + if (g_usHeadIR) { + ispVMMemManager(HIR, g_usHeadIR); + ispVMData(g_pucHIRData); + +#ifdef VME_DEBUG + printf(" TDI "); + PrintData(g_usHeadIR, g_pucHIRData); +#endif //VME_DEBUG + } + break; + case TIR: + + /**************************************************************************** + * + * Store the maximum size of the TIR buffer. Used to convert VME to HEX. + * + *****************************************************************************/ + + if (g_usiDataSize > g_usTIRSize) { + g_usTIRSize = g_usiDataSize; + } + + /**************************************************************************** + * + * Assign the TIR value and allocate memory. + * + *****************************************************************************/ + + g_usTailIR = g_usiDataSize; + if (g_usTailIR) { + ispVMMemManager(TIR, g_usTailIR); + ispVMData(g_pucTIRData); + +#ifdef VME_DEBUG + printf(" TDI "); + PrintData(g_usTailIR, g_pucTIRData); +#endif //VME_DEBUG + } + break; + case HDR: + + /**************************************************************************** + * + * Store the maximum size of the HDR buffer. Used to convert VME to HEX. + * + *****************************************************************************/ + + if (g_usiDataSize > g_usHDRSize) { + g_usHDRSize = g_usiDataSize; + } + + /**************************************************************************** + * + * Assign the HDR value and allocate memory. + * + *****************************************************************************/ + + g_usHeadDR = g_usiDataSize; + if (g_usHeadDR) { + ispVMMemManager(HDR, g_usHeadDR); + ispVMData(g_pucHDRData); + +#ifdef VME_DEBUG + printf(" TDI "); + PrintData(g_usHeadDR, g_pucHDRData); +#endif //VME_DEBUG + } + break; + case TDR: + + /**************************************************************************** + * + * Store the maximum size of the TDR buffer. Used to convert VME to HEX. + * + *****************************************************************************/ + + if (g_usiDataSize > g_usTDRSize) { + g_usTDRSize = g_usiDataSize; + } + + /**************************************************************************** + * + * Assign the TDR value and allocate memory. + * + *****************************************************************************/ + + g_usTailDR = g_usiDataSize; + if (g_usTailDR) { + ispVMMemManager(TDR, g_usTailDR); + ispVMData(g_pucTDRData); + +#ifdef VME_DEBUG + printf(" TDI "); + PrintData(g_usTailDR, g_pucTDRData); +#endif //VME_DEBUG + } + break; + default: + break; + } + + /**************************************************************************** + * + * Re-enable compression if it was previously set. + * + *****************************************************************************/ + + if (compress) { + g_usDataType |= COMPRESS; + } + + if (g_usiDataSize) { + Code = GetByte(); + if (Code == CONTINUE) { + return 0; + } else { + + /**************************************************************************** + * + * Encountered invalid opcode. + * + *****************************************************************************/ + + return VME_INVALID_FILE; + } + } + + return 0; +} + +/*************************************************************** +* +* ispVMLoop +* +* Perform the function call upon by the REPEAT opcode. +* Memory is to be allocated to store the entire loop from REPEAT to ENDLOOP. +* After the loop is stored then execution begin. The REPEATLOOP flag is set +* on the g_usFlowControl register to indicate the repeat loop is in session +* and therefore fetch opcode from the memory instead of from the file. +* +***************************************************************/ + +signed char ispVMLoop(unsigned short a_usLoopCount) +{ + //09/11/07 NN added local variables initialization + signed char cRetCode = 0; + unsigned short iHeapIndex = 0; + unsigned short iLoopIndex = 0; + + g_usShiftValue = 0; + for (iHeapIndex = 0; iHeapIndex < g_iHEAPSize; iHeapIndex++) { + g_pucHeapMemory[iHeapIndex] = GetByte(); + } + + if (g_pucHeapMemory[iHeapIndex - 1] != ENDLOOP) { + return (VME_INVALID_FILE); + } + + g_usFlowControl |= REPEATLOOP; + g_usDataType |= HEAP_IN; + + for (iLoopIndex = 0; iLoopIndex < a_usLoopCount; iLoopIndex++) { + g_iHeapCounter = 0; + cRetCode = ispVMCode(); + g_usRepeatLoops++; + if (cRetCode < 0) { + break; + } + } + + g_usDataType &= ~(HEAP_IN); + g_usFlowControl &= ~(REPEATLOOP); + return (cRetCode); +} + +/*************************************************************** +* +* ispVMBitShift +* +* Shift the TDI stream left or right by the number of bits. The data in +* *g_pucInData is of the VME format, so the actual shifting is the reverse of +* IEEE 1532 or SVF format. +* +***************************************************************/ + +signed char ispVMBitShift(signed char mode, unsigned short bits) +{ + //09/11/07 NN added local variables initialization + unsigned short i = 0; + unsigned short size = 0; + unsigned short tmpbits = 0; + + if (g_usiDataSize % 8 > 0) { + //09/11/07 NN Type cast mismatch variables + size = (unsigned short)(g_usiDataSize / 8 + 1); + } else { + //09/11/07 NN Type cast mismatch variables + size = (unsigned short)(g_usiDataSize / 8); + } + + switch (mode) { + case SHR: + for (i = 0; i < size; i++) { + if (g_pucInData[i] != 0) { + tmpbits = bits; + while (tmpbits > 0) { + g_pucInData[i] <<= 1; + if (g_pucInData[i] == 0) { + i--; + g_pucInData[i] = 1; + } + tmpbits--; + } + } + } + break; + case SHL: + for (i = 0; i < size; i++) { + if (g_pucInData[i] != 0) { + tmpbits = bits; + while (tmpbits > 0) { + g_pucInData[i] >>= 1; + if (g_pucInData[i] == 0) { + i--; + g_pucInData[i] = 8; + } + tmpbits--; + } + } + } + break; + default: + return (VME_INVALID_FILE); + } + + return (0); +} + +/*************************************************************** +* +* ispVMComment +* +* Displays the SVF comments. +* +***************************************************************/ + +void ispVMComment(unsigned short a_usCommentSize) +{ + char cCurByte = 0; + for (; a_usCommentSize > 0; a_usCommentSize--) { + /**************************************************************************** + * + * Print character to the terminal. + * + *****************************************************************************/ + cCurByte = GetByte(); + vme_out_char(cCurByte); + } + cCurByte = '\n'; + vme_out_char(cCurByte); +} + +/*************************************************************** +* +* ispVMHeader +* +* Iterate the length of the header and discard it. +* +***************************************************************/ + +void ispVMHeader(unsigned short a_usHeaderSize) +{ + for (; a_usHeaderSize > 0; a_usHeaderSize--) { + GetByte(); + } +} + +/*************************************************************** +* +* ispVMCalculateCRC32 +* +* Calculate the 32-bit CRC. +* +***************************************************************/ + +void ispVMCalculateCRC32(unsigned char a_ucData) +{ + //09/11/07 NN added local variables initialization + unsigned char ucIndex = 0; + unsigned char ucFlipData = 0; + unsigned short usCRCTableEntry = 0; + unsigned int crc_table[16] = { + 0x0000, 0xCC01, 0xD801, + 0x1400, 0xF001, 0x3C00, + 0x2800, 0xE401, 0xA001, + 0x6C00, 0x7800, 0xB401, + 0x5000, 0x9C01, 0x8801, + 0x4400 + }; + + for (ucIndex = 0; ucIndex < 8; ucIndex++) { + ucFlipData <<= 1; + if (a_ucData & 0x01) { + ucFlipData |= 0x01; + } + a_ucData >>= 1; + } + + //09/11/07 NN Type cast mismatch variables + usCRCTableEntry = (unsigned short)(crc_table[g_usCalculatedCRC & 0xF]); + g_usCalculatedCRC = (unsigned short)((g_usCalculatedCRC >> 4) & 0x0FFF); + g_usCalculatedCRC = (unsigned short)(g_usCalculatedCRC ^ usCRCTableEntry ^ crc_table[ucFlipData & 0xF]); + usCRCTableEntry = (unsigned short)(crc_table[g_usCalculatedCRC & 0xF]); + g_usCalculatedCRC = (unsigned short)((g_usCalculatedCRC >> 4) & 0x0FFF); + g_usCalculatedCRC = (unsigned short)(g_usCalculatedCRC ^ usCRCTableEntry ^ crc_table[(ucFlipData >> 4) & 0xF]); +} + +/*************************************************************** +* +* ispVMLCOUNT +* +* Process the intelligent programming loops. +* +***************************************************************/ + +signed char ispVMLCOUNT(unsigned short a_usCountSize) +{ + unsigned short usContinue = 1; + unsigned short usIntelBufferIndex = 0; + unsigned short usCountIndex = 0; + signed char cRetCode = 0; + signed char cRepeatHeap = 0; + signed char cOpcode = 0; + unsigned char ucState = 0; + unsigned short usDelay = 0; + unsigned short usToggle = 0; + + g_usIntelBufferSize = (unsigned short)ispVMDataSize(); + + /**************************************************************************** + * + * Allocate memory for intel buffer. + * + *****************************************************************************/ + + ispVMMemManager(LHEAP, g_usIntelBufferSize); + + /**************************************************************************** + * + * Store the maximum size of the intelligent buffer. Used to convert VME to HEX. + * + *****************************************************************************/ + + if (g_usIntelBufferSize > g_usLCOUNTSize) { + g_usLCOUNTSize = g_usIntelBufferSize; + } + + /**************************************************************************** + * + * Copy intel data to the buffer. + * + *****************************************************************************/ + + for (usIntelBufferIndex = 0; usIntelBufferIndex < g_usIntelBufferSize; usIntelBufferIndex++) { + g_pucIntelBuffer[usIntelBufferIndex] = GetByte(); + } + + /**************************************************************************** + * + * Set the data type register to get data from the intelligent data buffer. + * + *****************************************************************************/ + + g_usDataType |= LHEAP_IN; + + /**************************************************************************** + * + * If the HEAP_IN flag is set, temporarily unset the flag so data will be + * retrieved from the status buffer. + * + *****************************************************************************/ + + if (g_usDataType & HEAP_IN) { + g_usDataType &= ~HEAP_IN; + cRepeatHeap = 1; + } + +#ifdef VME_DEBUG + printf("LCOUNT %d;\n", a_usCountSize); +#endif //VME_DEBUG + + /**************************************************************************** + * + * Iterate through the intelligent programming command. + * + *****************************************************************************/ + + for (usCountIndex = 0; usCountIndex < a_usCountSize; usCountIndex++) { + + /**************************************************************************** + * + * Initialize the intel data index to 0 before each iteration. + * + *****************************************************************************/ + + g_usIntelDataIndex = 0; + cOpcode = 0; + ucState = 0; + usDelay = 0; + usToggle = 0; + usContinue = 1; + + /*************************************************************** + * + * Begin looping through all the VME opcodes. + * + ***************************************************************/ + /*************************************************************** + * 4/1/09 Nguyen replaced the recursive function call codes on + * the ispVMLCOUNT function + * + ***************************************************************/ + while (usContinue) { + cOpcode = GetByte(); + switch (cOpcode) { + case HIR: + case TIR: + case HDR: + case TDR: + /*************************************************************** + * + * Set the header/trailer of the device in order to bypass + * successfully. + * + ***************************************************************/ + + ispVMAmble(cOpcode); + break; + case STATE: + + /*************************************************************** + * + * Step the JTAG state machine. + * + ***************************************************************/ + + ucState = GetByte(); + /*************************************************************** + * + * Step the JTAG state machine to DRCAPTURE to support Looping. + * + ***************************************************************/ + + if ((g_usDataType & LHEAP_IN) && + (ucState == DRPAUSE) && + (g_cCurrentJTAGState == ucState)) { + ispVMStateMachine(DRCAPTURE); + } + ispVMStateMachine(ucState); +#ifdef VME_DEBUG + printf("LDELAY %s ", GetState(ucState)); +#endif //VME_DEBUG + break; + case SIR: +#ifdef VME_DEBUG + printf("SIR "); +#endif //VME_DEBUG + /*************************************************************** + * + * Shift in data into the device. + * + ***************************************************************/ + + cRetCode = ispVMShift(cOpcode); + break; + case SDR: + +#ifdef VME_DEBUG + printf("LSDR "); +#endif //VME_DEBUG + /*************************************************************** + * + * Shift in data into the device. + * + ***************************************************************/ + + cRetCode = ispVMShift(cOpcode); + break; + case WAIT: + + /*************************************************************** + * + * Observe delay. + * + ***************************************************************/ + + usDelay = (unsigned short)ispVMDataSize(); + ispVMDelay(usDelay); + +#ifdef VME_DEBUG + if (usDelay & 0x8000) { + + /*************************************************************** + * + * Since MSB is set, the delay time must be decoded to + * millisecond. The SVF2VME encodes the MSB to represent + * millisecond. + * + ***************************************************************/ + + usDelay &= ~0x8000; + printf("%.2E SEC;\n", (float)usDelay / 1000); + } else { + + /*************************************************************** + * + * Since MSB is not set, the delay time is given as microseconds. + * + ***************************************************************/ + + printf("%.2E SEC;\n", (float)usDelay / 1000000); + } +#endif //VME_DEBUG + break; + case TCK: + + /*************************************************************** + * + * Issue clock toggles. + * + ***************************************************************/ + + usToggle = (unsigned short)ispVMDataSize(); + ispVMClocks(usToggle); + +#ifdef VME_DEBUG + printf("RUNTEST %d TCK;\n", usToggle); +#endif //VME_DEBUG + break; + case ENDLOOP: + + /*************************************************************** + * + * Exit point from processing loops. + * + ***************************************************************/ + usContinue = 0; + break; + + case COMMENT: + + /*************************************************************** + * + * Display comment. + * + ***************************************************************/ + + ispVMComment((unsigned short)ispVMDataSize()); + break; + case ispEN: + ucState = GetByte(); + if ((ucState == ON) || (ucState == 0x01)) + writePort(JTAG_ENABLE, 0x01); + else + writePort(JTAG_ENABLE, 0x00); + ispVMDelay(1); + break; + case TRST: + if (GetByte() == 0x01) + writePort(JTAG_TRST, 0x01); + else + writePort(JTAG_TRST, 0x00); + ispVMDelay(1); + break; + default: + + /*************************************************************** + * + * Invalid opcode encountered. + * + ***************************************************************/ + +#ifdef VME_DEBUG + printf("\nINVALID OPCODE: 0x%.2X\n", cOpcode); +#endif //VME_DEBUG + + return VME_INVALID_FILE; + } + } + if (cRetCode >= 0) { + /**************************************************************************** + * + * Break if intelligent programming is successful. + * + *****************************************************************************/ + + break; + } + + } + /**************************************************************************** + * + * If HEAP_IN flag was temporarily disabled, re-enable it before exiting. + * + *****************************************************************************/ + + if (cRepeatHeap) { + g_usDataType |= HEAP_IN; + } + + /**************************************************************************** + * + * Set the data type register to not get data from the intelligent data buffer. + * + *****************************************************************************/ + + g_usDataType &= ~LHEAP_IN; + return cRetCode; +} + +/*************************************************************** +* +* ispVMClocks +* +* Applies the specified number of pulses to TCK. +* +***************************************************************/ + +void ispVMClocks(unsigned short Clocks) +{ + unsigned short iClockIndex = 0; + for (iClockIndex = 0; iClockIndex < Clocks; iClockIndex++) { + sclock(); + } +} + +/*************************************************************** +* +* ispVMBypass +* +* This procedure takes care of the HIR, HDR, TIR, TDR for the +* purpose of putting the other devices into Bypass mode. The +* current state is checked to find out if it is at DRPAUSE or +* IRPAUSE. If it is at DRPAUSE, perform bypass register scan. +* If it is at IRPAUSE, scan into instruction registers the bypass +* instruction. +* +***************************************************************/ + +void ispVMBypass(signed char ScanType, unsigned short Bits) +{ + //09/11/07 NN added local variables initialization + unsigned short iIndex = 0; + unsigned short iSourceIndex = 0; + unsigned char cBitState = 0; + unsigned char cCurByte = 0; + unsigned char *pcSource = NULL; + + if (Bits <= 0) { + return; + } + + switch (ScanType) { + case HIR: + pcSource = g_pucHIRData; + break; + case TIR: + pcSource = g_pucTIRData; + break; + case HDR: + pcSource = g_pucHDRData; + break; + case TDR: + pcSource = g_pucTDRData; + break; + default: + break; + } + if (pcSource) { + iSourceIndex = 0; + cBitState = 0; + for (iIndex = 0; iIndex < Bits - 1; iIndex++) { + /* Scan instruction or bypass register */ + if (iIndex % 8 == 0) { + cCurByte = pcSource[iSourceIndex++]; + } + cBitState = (unsigned char)(((cCurByte << iIndex % 8) & 0x80) ? 0x01 : 0x00); + writePort(JTAG_TDI, cBitState); + sclock(); + } + + if (iIndex % 8 == 0) { + cCurByte = pcSource[iSourceIndex++]; + } + + cBitState = (unsigned char)(((cCurByte << iIndex % 8) & 0x80) ? 0x01 : 0x00); + writePort(JTAG_TDI, cBitState); + } +} + +/*************************************************************** +* +* ispVMStateMachine +* +* This procedure steps all devices in the daisy chain from a given +* JTAG state to the next desirable state. If the next state is TLR, +* the JTAG state machine is brute forced into TLR by driving TMS +* high and pulse TCK 6 times. +* +***************************************************************/ + +void ispVMStateMachine(signed char cNextJTAGState) +{ + //09/11/07 NN added local variables initialization + signed char cPathIndex = 0; + signed char cStateIndex = 0; + short int found = 0; + + if ((g_cCurrentJTAGState == cNextJTAGState) && (cNextJTAGState != RESET)) { + return; + } + + for (cStateIndex = 0; cStateIndex < 25; cStateIndex++) { + if ((g_cCurrentJTAGState == g_JTAGTransistions[cStateIndex].CurState) && (cNextJTAGState == g_JTAGTransistions[cStateIndex].NextState)) { + found = 1; + break; + } + } + if (found) { + g_cCurrentJTAGState = cNextJTAGState; + for (cPathIndex = 0; cPathIndex < g_JTAGTransistions[cStateIndex].Pulses; cPathIndex++) { + if ((g_JTAGTransistions[cStateIndex].Pattern << cPathIndex) & 0x80) { + writePort(JTAG_TMS, (unsigned char)0x01); + } else { + writePort(JTAG_TMS, (unsigned char)0x00); + } + sclock(); + } + + writePort(JTAG_TDI, 0x00); + writePort(JTAG_TMS, 0x00); + } +} + +/*************************************************************** +* +* ispVMStart +* +* Enable the port to the device and set the state to RESET (TLR). +* +***************************************************************/ + +void ispVMStart() +{ +#ifdef VME_DEBUG + printf("// ISPVM EMBEDDED ADDED\n"); + printf("STATE RESET;\n"); +#endif + + ispVMStateMachine(RESET); /*step devices to RESET state*/ + +} + +/*************************************************************** +* +* ispVMEnd +* +* Set the state of devices to RESET to enable the devices and disable +* the port. +* +***************************************************************/ + +void ispVMEnd() +{ +#ifdef VME_DEBUG + printf("// ISPVM EMBEDDED ADDED\n"); + printf("STATE RESET;\n"); + printf("RUNTEST 1.00E-001 SEC;\n"); +#endif + + ispVMStateMachine(RESET); /*step devices to RESET state */ + ispVMDelay(1000); /*wake up devices*/ +} + +/*************************************************************** +* +* ispVMSend +* +* Send the TDI data stream to devices. The data stream can be +* instructions or data. +* +***************************************************************/ + +signed char ispVMSend(unsigned short a_usiDataSize) +{ + //09/11/07 NN added local variables initialization + unsigned short iIndex = 0; + unsigned short iInDataIndex = 0; + unsigned char cCurByte = 0; + unsigned char cBitState = 0; + + for (iIndex = 0; iIndex < a_usiDataSize - 1; iIndex++) { + if (iIndex % 8 == 0) { + cCurByte = g_pucInData[iInDataIndex++]; + } + cBitState = (unsigned char)(((cCurByte << iIndex % 8) & 0x80) ? 0x01 : 0x00); + writePort(JTAG_TDI, cBitState); + sclock(); + } + + if (iIndex % 8 == 0) { + /* Take care of the last bit */ + cCurByte = g_pucInData[iInDataIndex]; + } + + cBitState = (unsigned char)(((cCurByte << iIndex % 8) & 0x80) ? 0x01 : 0x00); + + writePort(JTAG_TDI, cBitState); + if (g_usFlowControl & CASCADE) { + /* 1/15/04 Clock in last bit for the first n-1 cascaded frames */ + sclock(); + } + + return 0; +} + +/*************************************************************** +* +* ispVMRead +* +* Read the data stream from devices and verify. +* +***************************************************************/ + +signed char ispVMRead(unsigned short a_usiDataSize) //32 +{ + //09/11/07 NN added local variables initialization + unsigned short usDataSizeIndex = 0; + unsigned short usErrorCount = 0; + unsigned short usLastBitIndex = 0; + unsigned char cDataByte = 0; + unsigned char cMaskByte = 0; + unsigned char cInDataByte = 0; + unsigned char cCurBit = 0; + unsigned char cByteIndex = 0; + unsigned short usBufferIndex = 0; + unsigned char ucDisplayByte = 0x00; + unsigned char ucDisplayFlag = 0x01; + char StrChecksum[256] = { 0 }; + unsigned char g_usCalculateChecksum = 0x00; + + //09/11/07 NN Type cast mismatch variables + usLastBitIndex = (unsigned short)(a_usiDataSize - 1); + + /**************************************************************************** + * + * If mask is not all zeros, then set the display flag to 0x00, otherwise + * it shall be set to 0x01 to indicate that data read from the device shall + * be displayed. If VME_DEBUG is defined, always display data. + * + *****************************************************************************/ + + for (usDataSizeIndex = 0; usDataSizeIndex < (a_usiDataSize + 7) / 8; usDataSizeIndex++) { + + if (g_usDataType & MASK_DATA) { + if (g_pucOutMaskData[usDataSizeIndex] != 0x00) { + ucDisplayFlag = 0x00; + break; + } + } else if (g_usDataType & CMASK_DATA) { + g_usCalculateChecksum = 0x01; + ucDisplayFlag = 0x00; + break; + } else { + ucDisplayFlag = 0x00; + break; + } + } + + /**************************************************************************** + * + * Begin shifting data in and out of the device. + * + *****************************************************************************/ + for (usDataSizeIndex = 0; usDataSizeIndex < a_usiDataSize; usDataSizeIndex++) { + if (cByteIndex == 0) { + + /*************************************************************** + * + * Grab byte from TDO buffer. + * + ***************************************************************/ + + if (g_usDataType & TDO_DATA) { + cDataByte = g_pucOutData[usBufferIndex]; + } + + /*************************************************************** + * + * Grab byte from MASK buffer. + * + ***************************************************************/ + + if (g_usDataType & MASK_DATA) { + cMaskByte = g_pucOutMaskData[usBufferIndex]; + } else { + cMaskByte = 0xFF; + } + + /*************************************************************** + * + * Grab byte from CMASK buffer. + * + ***************************************************************/ + + if (g_usDataType & CMASK_DATA) { + cMaskByte = 0x00; + g_usCalculateChecksum = 0x01; + } + + /*************************************************************** + * + * Grab byte from TDI buffer. + * + ***************************************************************/ + + if (g_usDataType & TDI_DATA) { + cInDataByte = g_pucInData[usBufferIndex]; + } + + usBufferIndex++; + } + + cCurBit = readPort(); + + if (ucDisplayFlag) { + ucDisplayByte <<= 1; + ucDisplayByte |= cCurBit; + } + + /**************************************************************************** + * + * Check if data read from port matches with expected TDO. + * + *****************************************************************************/ + + if (g_usDataType & TDO_DATA) { + //08/28/08 NN Added Calculate checksum support. + if (g_usCalculateChecksum) { + if (cCurBit == 0x01) + g_usChecksum += (1 << (g_uiChecksumIndex % 8)); + g_uiChecksumIndex++; + } else { + if ((((cMaskByte << cByteIndex) & 0x80) ? 0x01 : 0x00)) { + if (cCurBit != (unsigned char)(((cDataByte << cByteIndex) & 0x80) ? 0x01 : 0x00)) { + usErrorCount++; + } + } + } + } + + /**************************************************************************** + * + * Write TDI data to the port. + * + *****************************************************************************/ + + writePort(JTAG_TDI, (unsigned char)(((cInDataByte << cByteIndex) & 0x80) ? 0x01 : 0x00)); + + if (usDataSizeIndex < usLastBitIndex) { + + /**************************************************************************** + * + * Clock data out from the data shift register. + * + *****************************************************************************/ + + sclock(); + } else if (g_usFlowControl & CASCADE) { + + /**************************************************************************** + * + * Clock in last bit for the first N - 1 cascaded frames. + * + *****************************************************************************/ + + sclock(); + } + + /*************************************************************** + * + * Increment the byte index. If it exceeds 7, then reset it back + * to zero. + * + ***************************************************************/ + + cByteIndex++; + if (cByteIndex >= 8) { + if (ucDisplayFlag) { + + /*************************************************************** + * + * Store displayed data in the TDO buffer. By reusing the TDO + * buffer to store displayed data, there is no need to allocate + * a buffer simply to hold display data. This will not cause any + * false verification errors because the true TDO byte has already + * been consumed. + * + ***************************************************************/ + + g_pucOutData[usBufferIndex - 1] = ucDisplayByte; + ucDisplayByte = 0; + } + + cByteIndex = 0; + } + //09/12/07 Nguyen changed to display the 1 bit expected data + else if (a_usiDataSize == 1) { + if (ucDisplayFlag) { + + /*************************************************************** + * + * Store displayed data in the TDO buffer. By reusing the TDO + * buffer to store displayed data, there is no need to allocate + * a buffer simply to hold display data. This will not cause any + * false verification errors because the true TDO byte has already + * been consumed. + * + ***************************************************************/ + + /**************************************************************************** + * + * Flip ucDisplayByte and store it in cDataByte. + * + *****************************************************************************/ + cDataByte = 0x00; + for (usBufferIndex = 0; usBufferIndex < 8; usBufferIndex++) { + cDataByte <<= 1; + if (ucDisplayByte & 0x01) { + cDataByte |= 0x01; + } + ucDisplayByte >>= 1; + } + g_pucOutData[0] = cDataByte; + ucDisplayByte = 0; + } + + cByteIndex = 0; + } + } + if (ucDisplayFlag) { + + /**************************************************************************** + * + * Display data read from the device. + * + *****************************************************************************/ + +#ifdef VME_DEBUG + printf("RECIEVED TDO ("); +#else + vme_out_string("Display Data: 0x"); +#endif //VME_DEBUG + + //09/11/07 NN Type cast mismatch variables + for (usDataSizeIndex = (unsigned short)((a_usiDataSize + 7) / 8); usDataSizeIndex > 0; usDataSizeIndex--) { + cMaskByte = g_pucOutData[usDataSizeIndex - 1]; + cDataByte = 0x00; + + /**************************************************************************** + * + * Flip cMaskByte and store it in cDataByte. + * + *****************************************************************************/ + + for (usBufferIndex = 0; usBufferIndex < 8; usBufferIndex++) { + cDataByte <<= 1; + if (cMaskByte & 0x01) { + cDataByte |= 0x01; + } + cMaskByte >>= 1; + } +#ifdef VME_DEBUG + printf("%.2X", cDataByte); + if ((((a_usiDataSize + 7) / 8) - usDataSizeIndex) % 40 == 39) { + printf("\n\t\t"); + } +#else + vme_out_hex(cDataByte); +#endif //VME_DEBUG + } + +#ifdef VME_DEBUG + printf(")\n\n"); +#else + vme_out_string("\n\n"); +#endif //VME_DEBUG + //09/02/08 Nguyen changed to display the data Checksum + vme_out_string("g_usChecksum:"); + sprintf(StrChecksum, "%.4X\n\n", (unsigned int)g_usChecksum); + vme_out_string(StrChecksum); + vme_out_string("\n\n"); + if (g_usChecksum != 0) { + g_usChecksum &= 0xFFFF; + sprintf(StrChecksum, "Data Checksum: %.4X\n\n", (unsigned int)g_usChecksum); + vme_out_string(StrChecksum); + g_usChecksum = 0; + } + } + + if (usErrorCount > 0) { + + if (g_usFlowControl & VERIFYUES) { + vme_out_string("USERCODE verification failed. Continue programming......\n\n"); + g_usFlowControl &= ~(VERIFYUES); + return 0; + } else { + +#ifdef VME_DEBUG + printf("TOTAL ERRORS: %d\n", usErrorCount); +#endif //VME_DEBUG + + return VME_VERIFICATION_FAILURE; + } + } else { + if (g_usFlowControl & VERIFYUES) { + vme_out_string("USERCODE verification passed. Programming aborted. \n\n"); + g_usFlowControl &= ~(VERIFYUES); + return 1; + } else { + return 0; + } + } +} + +/*************************************************************** +* +* ispVMReadandSave +* +* Support dynamic I/O. +* +***************************************************************/ + +signed char ispVMReadandSave(unsigned short int a_usiDataSize) +{ + //09/11/07 NN added local variables initialization + unsigned short int usDataSizeIndex = 0; + unsigned short int usLastBitIndex = 0; + unsigned short int usBufferIndex = 0; + unsigned short int usOutBitIndex = 0; + unsigned short int usLVDSIndex = 0; + unsigned char cDataByte = 0; + unsigned char cDMASKByte = 0; + unsigned char cInDataByte = 0; + unsigned char cCurBit = 0; + unsigned char cByteIndex = 0; + signed char cLVDSByteIndex = 0; + + //09/11/07 NN Type cast mismatch variables + usLastBitIndex = (unsigned short)(a_usiDataSize - 1); + + /*************************************************************** + * + * Iterate through the data bits. + * + ***************************************************************/ + + for (usDataSizeIndex = 0; usDataSizeIndex < a_usiDataSize; usDataSizeIndex++) { + if (cByteIndex == 0) { + + /*************************************************************** + * + * Grab byte from DMASK buffer. + * + ***************************************************************/ + + if (g_usDataType & DMASK_DATA) { + cDMASKByte = g_pucOutDMaskData[usBufferIndex]; + } else { + cDMASKByte = 0x00; + } + + /*************************************************************** + * + * Grab byte from TDI buffer. + * + ***************************************************************/ + + if (g_usDataType & TDI_DATA) { + cInDataByte = g_pucInData[usBufferIndex]; + } + + usBufferIndex++; + } + + cCurBit = readPort(); + cDataByte = (unsigned char)(((cInDataByte << cByteIndex) & 0x80) ? 0x01 : 0x00); + + /*************************************************************** + * + * Initialize the byte to be zero. + * + ***************************************************************/ + + if (usOutBitIndex % 8 == 0) { + g_pucOutData[usOutBitIndex / 8] = 0x00; + } + + /*************************************************************** + * + * Use TDI, DMASK, and device TDO to create new TDI (actually + * stored in g_pucOutData). + * + ***************************************************************/ + + if ((((cDMASKByte << cByteIndex) & 0x80) ? 0x01 : 0x00)) { + + if (g_pLVDSList) { + for (usLVDSIndex = 0; usLVDSIndex < g_usLVDSPairCount; usLVDSIndex++) { + if (g_pLVDSList[usLVDSIndex].usNegativeIndex == usDataSizeIndex) { + g_pLVDSList[usLVDSIndex].ucUpdate = 0x01; + break; + } + } + } + + /*************************************************************** + * + * DMASK bit is 1, use TDI. + * + ***************************************************************/ + + g_pucOutData[usOutBitIndex / 8] |= (unsigned char)(((cDataByte & 0x1) ? 0x01 : 0x00) << (7 - usOutBitIndex % 8)); + } else { + + /*************************************************************** + * + * DMASK bit is 0, use device TDO. + * + ***************************************************************/ + + g_pucOutData[usOutBitIndex / 8] |= (unsigned char)(((cCurBit & 0x1) ? 0x01 : 0x00) << (7 - usOutBitIndex % 8)); + } + + /*************************************************************** + * + * Shift in TDI in order to get TDO out. + * + ***************************************************************/ + + usOutBitIndex++; + writePort(JTAG_TDI, cDataByte); + if (usDataSizeIndex < usLastBitIndex) { + sclock(); + } + + /*************************************************************** + * + * Increment the byte index. If it exceeds 7, then reset it back + * to zero. + * + ***************************************************************/ + + cByteIndex++; + if (cByteIndex >= 8) { + cByteIndex = 0; + } + } + + /*************************************************************** + * + * If g_pLVDSList exists and pairs need updating, then update + * the negative-pair to receive the flipped positive-pair value. + * + ***************************************************************/ + + if (g_pLVDSList) { + for (usLVDSIndex = 0; usLVDSIndex < g_usLVDSPairCount; usLVDSIndex++) { + if (g_pLVDSList[usLVDSIndex].ucUpdate) { + + /*************************************************************** + * + * Read the positive value and flip it. + * + ***************************************************************/ + + cDataByte = (unsigned char)(((g_pucOutData[g_pLVDSList[usLVDSIndex].usPositiveIndex / 8] << (g_pLVDSList[usLVDSIndex].usPositiveIndex % 8)) & 0x80) ? 0x01 : 0x00); + //09/11/07 NN Type cast mismatch variables + cDataByte = (unsigned char)(!cDataByte); + + /*************************************************************** + * + * Get the byte that needs modification. + * + ***************************************************************/ + + cInDataByte = g_pucOutData[g_pLVDSList[usLVDSIndex].usNegativeIndex / 8]; + + if (cDataByte) { + + /*************************************************************** + * + * Copy over the current byte and set the negative bit to 1. + * + ***************************************************************/ + + cDataByte = 0x00; + for (cLVDSByteIndex = 7; cLVDSByteIndex >= 0; cLVDSByteIndex--) { + cDataByte <<= 1; + if (7 - (g_pLVDSList[usLVDSIndex].usNegativeIndex % 8) == cLVDSByteIndex) { + + /*************************************************************** + * + * Set negative bit to 1. + * + ***************************************************************/ + + cDataByte |= 0x01; + } else if (cInDataByte & 0x80) { + cDataByte |= 0x01; + } + + cInDataByte <<= 1; + } + + /*************************************************************** + * + * Store the modified byte. + * + ***************************************************************/ + + g_pucOutData[g_pLVDSList[usLVDSIndex].usNegativeIndex / 8] = cDataByte; + } else { + + /*************************************************************** + * + * Copy over the current byte and set the negative bit to 0. + * + ***************************************************************/ + + cDataByte = 0x00; + for (cLVDSByteIndex = 7; cLVDSByteIndex >= 0; cLVDSByteIndex--) { + cDataByte <<= 1; + if (7 - (g_pLVDSList[usLVDSIndex].usNegativeIndex % 8) == cLVDSByteIndex) { + + /*************************************************************** + * + * Set negative bit to 0. + * + ***************************************************************/ + + cDataByte |= 0x00; + } else if (cInDataByte & 0x80) { + cDataByte |= 0x01; + } + + cInDataByte <<= 1; + } + + /*************************************************************** + * + * Store the modified byte. + * + ***************************************************************/ + + g_pucOutData[g_pLVDSList[usLVDSIndex].usNegativeIndex / 8] = cDataByte; + } + + break; + } + } + } + + return (0); +} + +signed char ispVMProcessLVDS(unsigned short a_usLVDSCount) +{ + unsigned short usLVDSIndex = 0; + + /*************************************************************** + * + * Allocate memory to hold LVDS pairs. + * + ***************************************************************/ + + ispVMMemManager(LVDS, a_usLVDSCount); + g_usLVDSPairCount = a_usLVDSCount; + +#ifdef VME_DEBUG + printf("LVDS %d (", a_usLVDSCount); +#endif //VME_DEBUG + + /*************************************************************** + * + * Iterate through each given LVDS pair. + * + ***************************************************************/ + + for (usLVDSIndex = 0; usLVDSIndex < g_usLVDSPairCount; usLVDSIndex++) { + + /*************************************************************** + * + * Assign the positive and negative indices of the LVDS pair. + * + ***************************************************************/ + + //09/11/07 NN Type cast mismatch variables + g_pLVDSList[usLVDSIndex].usPositiveIndex = (unsigned short)ispVMDataSize(); + //09/11/07 NN Type cast mismatch variables + g_pLVDSList[usLVDSIndex].usNegativeIndex = (unsigned short)ispVMDataSize(); + +#ifdef VME_DEBUG + if (usLVDSIndex < g_usLVDSPairCount - 1) { + printf("%d:%d, ", g_pLVDSList[usLVDSIndex].usPositiveIndex, g_pLVDSList[usLVDSIndex].usNegativeIndex); + } else { + printf("%d:%d", g_pLVDSList[usLVDSIndex].usPositiveIndex, g_pLVDSList[usLVDSIndex].usNegativeIndex); + } +#endif //VME_DEBUG + + } + +#ifdef VME_DEBUG + printf(") -- %d;\n", a_usLVDSCount); +#endif //VME_DEBUG + + return (0); +} + +/*************************************************************** +* +* ivm_core_reinit +* +* Reinit ivm_core variables. +* +***************************************************************/ +void ivm_core_reinit() +{ + g_usFlowControl = 0x0000; + g_usDataType = 0x0000; + + g_ucEndDR = DRPAUSE; + g_ucEndIR = IRPAUSE; + + g_usHeadDR = 0; + g_usHeadIR = 0; + g_usTailDR = 0; + g_usTailIR = 0; + + g_usiDataSize = 0; + + g_iFrequency = 1000; + + g_usMaxSize = 0; + + g_usShiftValue = 0; + + g_usRepeatLoops = 0; + + g_cVendor = LATTICE; + + g_usCalculatedCRC = 0; + + g_usChecksum = 0; + g_uiChecksumIndex = 0; + + g_cCurrentJTAGState = 0; + + g_pucHeapMemory = NULL; + g_iHeapCounter = 0; + g_iHEAPSize = 0; + + g_usIntelDataIndex = 0; + g_usIntelBufferSize = 0; + + g_usTDOSize = 0; + g_usMASKSize = 0; + g_usTDISize = 0; + g_usDMASKSize = 0; + g_usLCOUNTSize = 0; + g_usHDRSize = 0; + g_usTDRSize = 0; + g_usHIRSize = 0; + g_usTIRSize = 0; + g_usHeapSize = 0; + + g_pucOutMaskData = NULL; + g_pucInData = NULL; + g_pucOutData = NULL; + g_pucHIRData = NULL; + g_pucTIRData = NULL; + g_pucHDRData = NULL; + g_pucTDRData = NULL; + g_pucIntelBuffer = NULL; + g_pucOutDMaskData = NULL; + + g_pLVDSList = NULL; + g_usLVDSPairCount = 0; +} diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/fw_upg_isc/firmware_upgrade_isc.c b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/fw_upg_isc/firmware_upgrade_isc.c new file mode 100644 index 000000000000..c252dfde7c57 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/fw_upg_isc/firmware_upgrade_isc.c @@ -0,0 +1,68 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * firmware_upgrade_jtag + * function: Determine whether to upgrade ISC or JBI + * @fd: param[in] Device file descriptor + * @buf: param[in] Upgrade the file content + * @size: param[in] Upgrade file size + * @info: param[in] Upgrade file information + * return value : success--FIRMWARE_SUCCESS; fail--FIRMWARE_FAILED + */ +int firmware_upgrade_jtag(int fd, uint8_t *buf, uint32_t size, name_info_t *info) +{ + int ret; + cmd_info_t cmd_info; + + cmd_info.size = size; + cmd_info.data = buf; + ret = 0; + + if (info->type == FIRMWARE_CPLD) { + /* 0x4A,0x41,0x4D,0x01 is JBI file */ + if (buf[0] == 0x4A && buf[1] == 0x41 && buf[2] == 0x4D && buf[3] == 0x01) { + dbg_print(is_debug_on, "Use jbi file.\n"); + ret = ioctl(fd, FIRMWARE_PROGRAM_JBI, &cmd_info); + } else { + dbg_print(is_debug_on, "Use isc file.\n"); + ret = ioctl(fd, FIRMWARE_PROGRAM, &cmd_info); + } + } + + if (info->type == FIRMWARE_FPGA) { + ret = ioctl(fd, FIRMWARE_PROGRAM, &cmd_info); + } + + if (ret < 0) { + return FIRMWARE_FAILED; + } + + return FIRMWARE_SUCCESS; +} + +/* + * firmware_upgrade_jtag_test + * function: Determine whether to upgrade ISC or JBI + * @fd: param[in] Device file descriptor + * @buf: param[in] Upgrade the file content + * @size: param[in] Upgrade file size + * @info: param[in] Upgrade file information + * return value : success--FIRMWARE_SUCCESS; fail--FIRMWARE_FAILED + */ +int firmware_upgrade_jtag_test(int fd, uint8_t *buf, uint32_t size, name_info_t *info) +{ + return FIRMWARE_SUCCESS; +} diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/fw_upg_mtd/firmware_upgrade_mtd.c b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/fw_upg_mtd/firmware_upgrade_mtd.c new file mode 100644 index 000000000000..0a7659f0e428 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/fw_upg_mtd/firmware_upgrade_mtd.c @@ -0,0 +1,446 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "firmware_upgrade_mtd.h" +#include "mtd-abi.h" + +static int get_mtdnum_from_name(char *name, int *mtdnum) +{ + FILE *fp; + int ret; + char buf[PATH_LEN]; + char *start; + char *end; + char *key_w = "mtd"; + + if (name == NULL || mtdnum == NULL) { + dbg_print(is_debug_on, "Input invalid error.\n"); + return -EINVAL; + } + ret = 0; + *mtdnum = -1; + fp = fopen("/proc/mtd", "r"); + if (fp == NULL) { + dbg_print(is_debug_on, "Not find mtd device.\n"); + return -FIRWMARE_MTD_PART_INFO_ERR; + } + + mem_clear(buf, sizeof(buf)); + while(fgets(buf, sizeof(buf), fp)) { + if (strstr(buf, name) != NULL) { + start = strstr(buf, key_w); + if (start == NULL) { + dbg_print(is_debug_on, "/proc/mtd don't find %s.\n", key_w); + ret = -FIRWMARE_MTD_PART_INFO_ERR; + goto exit; + } + start += strlen(key_w); + end = strchr(start, ':'); + if (end == NULL) { + dbg_print(is_debug_on, "/proc/mtd don't find %c.\n", ':'); + ret = -FIRWMARE_MTD_PART_INFO_ERR; + goto exit; + } + + *end = '\0'; + *mtdnum = atoi(start); + if (*mtdnum < 0) { + dbg_print(is_debug_on, "Not get mtd num.\n"); + ret = -FIRWMARE_MTD_PART_INFO_ERR; + goto exit; + } + } + } + + if (*mtdnum == -1) { + ret = -FIRWMARE_MTD_PART_INFO_ERR; + goto exit; + } +exit: + if (fp != NULL) { + fclose(fp); + } + + return ret; +} + +static int firmware_sysfs_get_dev_info(int fd, firmware_mtd_info_t *dev_info) +{ + int ret; + + ret = ioctl(fd, FIRMWARE_SYSFS_MTD_INFO, dev_info); + if (ret < 0) { + dbg_print(is_debug_on, "Failed to get upg device file info.\n"); + return ret; + } + + dbg_print(is_debug_on, "mtd_name=%s flash_base=0x%x test_base=0x%x test_size=%d.\n", + dev_info->mtd_name, dev_info->flash_base, dev_info->test_base, dev_info->test_size); + return 0; +} + +/* + * MEMGETINFO + */ +static int getmeminfo(int fd, struct mtd_info_user *mtd) +{ + return ioctl(fd, MEMGETINFO, mtd); +} + +/* + * MEMERASE + */ +static int memerase(int fd, struct erase_info_user *erase) +{ + return ioctl(fd, MEMERASE, erase); +} + +static int erase_flash(int fd, uint32_t offset, uint32_t bytes) +{ + int err; + struct erase_info_user erase; + erase.start = offset; + erase.length = bytes; + err = memerase(fd, &erase); + if (err < 0) { + dbg_print(is_debug_on, "Error: memerase failed, err=%d\n", err); + return -FIRWMARE_MTD_MEMERASE; + } + dbg_print(is_debug_on, "Erased %d bytes from address 0x%.8x in flash\n", bytes, offset); + return 0; +} + +/* + * firmware_upgrade_mtd_block + * function: upgrade mtd device block + * @dev_info: param[in] Device file descriptor + * @buf: param[in] Upgrade the file content + * @size: param[in] Upgrade file size + * return value : success--FIRMWARE_SUCCESS; fail--FIRMWARE_FAILED + */ +static int firmware_upgrade_mtd_block(int mtd_fd, uint32_t offset, + uint8_t *buf, uint32_t size, uint32_t erasesize) +{ + int ret; + int i; + uint8_t *reread_buf; + uint32_t cmp_retry, reread_len, write_len; + + /* Read back data */ + reread_buf = (uint8_t *) malloc(size); + if (reread_buf == NULL) { + dbg_print(is_debug_on, "Error: Failed to malloc memory for read back data buf, size=%d.\n", size); + return FIRMWARE_FAILED; + } + + for (cmp_retry = 0; cmp_retry < FW_SYSFS_RETRY_TIME; cmp_retry++) { + for (i = 0; i < FW_SYSFS_RETRY_TIME; i++) { + if (offset != lseek(mtd_fd, offset, SEEK_SET)) { + dbg_print(is_debug_on, "Error:lseek mtd offset=%x retrytimes=%d failed.\n", offset, i); + usleep(FW_SYSFS_RETRY_SLEEP_TIME); + continue; + } + + dbg_print(is_debug_on, "erase mtd offset=0x%x erasesize=%d retrytimes=%d.\n", + offset, erasesize, i); + ret = erase_flash(mtd_fd, offset, erasesize); + if (ret < 0) { + dbg_print(is_debug_on, "Error:erase mtd offset=%x size=%d retrytimes=%d failed, ret=%d\n", + offset, size, i, ret); + usleep(FW_SYSFS_RETRY_SLEEP_TIME); + continue; + } + + dbg_print(is_debug_on, "write mtd offset=0x%x size=%d retrytimes=%d.\n", + offset, size, i); + write_len = write(mtd_fd, buf, size); + if (write_len != size) { + dbg_print(is_debug_on, "Error:write mtd offset=0x%x size=%d write_len=%d retrytimes=%d.\n", + offset, size, write_len, i); + usleep(FW_SYSFS_RETRY_SLEEP_TIME); + continue; + } + break; + } + if (i == FW_SYSFS_RETRY_TIME) { + dbg_print(is_debug_on, "Error: upgrade mtd fail, offset = 0x%x, size = %d\n", offset, size); + free(reread_buf); + return FIRMWARE_FAILED; + } + + usleep(FW_SYSFS_RETRY_SLEEP_TIME); + dbg_print(is_debug_on, "Reread mtd offset=0x%x size=%d\n", offset, size); + for (i = 0; i < FW_SYSFS_RETRY_TIME; i++) { + if (offset != lseek(mtd_fd, offset, SEEK_SET)) { + dbg_print(is_debug_on, "Error:lseek mtd offset=%x retrytimes=%d failed.\n", offset, i); + usleep(FW_SYSFS_RETRY_SLEEP_TIME); + continue; + } + + reread_len = read(mtd_fd, reread_buf, size); + if (reread_len != size) { + dbg_print(is_debug_on, "Error:reread mtd offset=0x%x size=%d reread_len=%d retrytimes=%d.\n", + offset, size, reread_len, i); + usleep(FW_SYSFS_RETRY_SLEEP_TIME); + continue; + } + break; + } + if (i == FW_SYSFS_RETRY_TIME) { + dbg_print(is_debug_on, "Error: reread mtd fail, offset = 0x%x size = %d\n", offset, size); + free(reread_buf); + return FIRMWARE_FAILED; + } + + /* Check data */ + if (memcmp(reread_buf, buf, size) != 0) { + dbg_print(is_debug_on, "memcmp mtd fail,offset = 0x%x retrytimes = %d\n", offset, cmp_retry); + } else { + break; + } + } + if (cmp_retry >= FW_SYSFS_RETRY_TIME) { + dbg_print(is_debug_on, "upgrade mtd fail, offset = 0x%x.\n", offset); + dbg_print(is_debug_on, "want to write buf :\n"); + for (i = 0; i < size; i++) { + dbg_print(is_debug_on, "0x%x ", buf[i]); + if (((i + 1) % 16) == 0) { + dbg_print(is_debug_on, "\n"); + } + } + dbg_print(is_debug_on, "\n"); + + dbg_print(is_debug_on, "actually reread buf :\n"); + for (i = 0; i < size; i++) { + dbg_print(is_debug_on, "0x%x ", reread_buf[i]); + if (((i + 1) % 16) == 0) { + dbg_print(is_debug_on, "\n"); + } + } + dbg_print(is_debug_on, "\n"); + + free(reread_buf); + return FIRMWARE_FAILED; + } + + free(reread_buf); + dbg_print(is_debug_on, "firmware upgrade mtd block offset[0x%.8x] success.\n", offset); + return FIRMWARE_SUCCESS; +} + +/* + * firmware_upgrade_mtd_program + * function: upgrade mtd device + * @dev_info: param[in] Device file descriptor + * @flash_base: param[in] Upgrade the flash start address + * @buf: param[in] Upgrade the file content + * @size: param[in] Upgrade file size + * return value : success--FIRMWARE_SUCCESS; fail--FIRMWARE_FAILED + */ +static int firmware_upgrade_mtd_program(firmware_mtd_info_t *dev_info, + int flash_base, uint8_t *buf, uint32_t size) +{ + int ret; + int mtdnum; + char dev_mtd[PATH_LEN]; + int mtd_fd; + uint32_t offset, len, block_size; + struct mtd_info_user mtd_info; + uint8_t *data_point; + + ret = get_mtdnum_from_name(dev_info->mtd_name, &mtdnum); + if (ret < 0) { + dbg_print(is_debug_on, "Error:not find %s mtd num.\n", dev_info->mtd_name); + return FIRMWARE_FAILED; + } + + mem_clear(dev_mtd, sizeof(dev_mtd)); + snprintf(dev_mtd, sizeof(dev_mtd) - 1, "/dev/mtd%d", mtdnum); + + mtd_fd = open(dev_mtd, O_SYNC | O_RDWR); + if (mtd_fd < 0) { + dbg_print(is_debug_on, "Error:open %s failed.\n", dev_mtd); + goto err; + } + + ret = getmeminfo(mtd_fd, &mtd_info); + if (ret < 0) { + dbg_print(is_debug_on, "Error:get mtd info failed, ret=%d.\n", ret); + goto failed; + } + + offset = flash_base; + if (offset >= mtd_info.size) { + dbg_print(is_debug_on, "Error: offset[0x%.8x] over size[0x%.8x]\n", offset, size); + goto failed; + } + + len = size; + data_point = buf; + while ((offset < mtd_info.size) && (len > 0)) { + if (len > mtd_info.erasesize) { + block_size = mtd_info.erasesize; + } else { + block_size = len; + } + dbg_print(is_debug_on, "upgrade mtd[%s] block offset[0x%.8x] size[%d] relen[%d].\n", dev_mtd, offset, size, len); + ret = firmware_upgrade_mtd_block(mtd_fd, offset, data_point, block_size, mtd_info.erasesize); + if (ret < 0) { + dbg_print(is_debug_on, "Error: mt block offset[0x%.8x] size[0x%.8x] failed.\n", offset, block_size); + goto failed; + } + len -= block_size; + data_point += block_size; + offset += block_size; + usleep(FW_MTD_BLOCK_SLEEP_TIME); + } + + if (close(mtd_fd) < 0) { + dbg_print(is_debug_on, "Error:close %s failed.\n", dev_mtd); + } + dbg_print(is_debug_on, "firmware upgrade mtd device success.\n"); + return FIRMWARE_SUCCESS; + +failed: + if (close(mtd_fd) < 0) { + dbg_print(is_debug_on, "Error:close %s failed.\n", dev_mtd); + } + +err: + dbg_print(is_debug_on, "firmware upgrade mtd device fail.\n"); + return FIRMWARE_FAILED; +} + +/* + * firmware_upgrade_mtd + * function: Determine whether to upgrade ISC or JBI + * @fd: param[in] Device file descriptor + * @buf: param[in] Upgrade the file content + * @size: param[in] Upgrade file size + * @info: param[in] Upgrade file information + * return value : success--FIRMWARE_SUCCESS; fail--FIRMWARE_FAILED + */ +int firmware_upgrade_mtd(int fd, uint8_t *buf, uint32_t size, name_info_t *info) +{ + int ret; + firmware_mtd_info_t dev_info; + + if ((buf == NULL) || (info == NULL)) { + dbg_print(is_debug_on, "Input invalid error.\n"); + return FIRMWARE_FAILED; + } + + /* get sysfs information*/ + ret = firmware_sysfs_get_dev_info(fd, &dev_info); + if (ret < 0) { + dbg_print(is_debug_on, "firmware_sysfs_get_dev_info failed, ret %d.\n", ret); + return FIRMWARE_FAILED; + } + + /* enable upgrade access */ + ret = ioctl(fd, FIRMWARE_SYSFS_INIT, NULL); + if (ret < 0) { + dbg_print(is_debug_on, "init dev logic faile\n"); + return FIRMWARE_FAILED; + } + + ret = firmware_upgrade_mtd_program(&dev_info, dev_info.flash_base, buf, size); + if (ret < 0) { + dbg_print(is_debug_on, "Error:mtd device program failed, ret=%d.\n", ret); + goto failed; + } + + /* disable upgrade access */ + ret = ioctl(fd, FIRMWARE_SYSFS_FINISH, NULL); + if (ret < 0) { + dbg_print(is_debug_on, "close dev logic en failed.\n"); + } + + return FIRMWARE_SUCCESS; + +failed: + /* disable upgrade access */ + ret = ioctl(fd, FIRMWARE_SYSFS_FINISH,NULL); + if (ret < 0) { + dbg_print(is_debug_on, "close dev logic en failed.\n"); + } + + return FIRMWARE_FAILED; +} + +/* + * firmware_upgrade_mtd_test + * function: Determine whether to upgrade ISC or JBI + * @fd: param[in] Device file descriptor + * @info: param[in] Upgrade file information + * return value : success--FIRMWARE_SUCCESS; fail--FIRMWARE_FAILED + */ +int firmware_upgrade_mtd_test(int fd, name_info_t *info) +{ + int ret, rv; + firmware_mtd_info_t dev_info; + uint8_t *data_buf; + uint8_t num; + int j; + + if (info == NULL) { + dbg_print(is_debug_on, "Input invalid error.\n"); + return FIRMWARE_FAILED; + } + + /* get sysfs information*/ + ret = firmware_sysfs_get_dev_info(fd, &dev_info); + if (ret < 0) { + dbg_print(is_debug_on, "firmware_sysfs_get_dev_info failed, ret %d.\n", ret); + return FIRMWARE_FAILED; + } + + if (dev_info.test_size == 0) { + dbg_print(is_debug_on, "Error: get flash size:%d, not support.\n", dev_info.test_size); + return FIRMWARE_NOT_SUPPORT; + } + + data_buf = (uint8_t *) malloc(dev_info.test_size); + if (data_buf == NULL) { + dbg_print(is_debug_on, "Error: Failed to malloc memory for test data buf, size=%d.\n", dev_info.test_size); + return FIRMWARE_FAILED; + } + + /* Get random data */ + for (j = 0; j < dev_info.test_size; j++) { + num = (uint8_t) rand() % 256; + data_buf[j] = num & 0xff; + } + + /* enable upgrade access */ + ret = ioctl(fd, FIRMWARE_SYSFS_INIT, NULL); + if (ret < 0) { + dbg_print(is_debug_on, "init dev logic faile\n"); + free(data_buf); + return FIRMWARE_FAILED; + } + + ret = firmware_upgrade_mtd_program(&dev_info, dev_info.test_base, data_buf, dev_info.test_size); + /* disable upgrade access */ + rv = ioctl(fd, FIRMWARE_SYSFS_FINISH, NULL); + if (rv < 0) { + dbg_print(is_debug_on, "close dev logic en failed.\n"); + } + free(data_buf); + if (ret < 0) { + dbg_print(is_debug_on, "Error:mtd device program failed, ret=%d.\n", ret); + return FIRMWARE_FAILED; + } + return FIRMWARE_SUCCESS; +} diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/fw_upg_mtd/firmware_upgrade_mtd.h b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/fw_upg_mtd/firmware_upgrade_mtd.h new file mode 100644 index 000000000000..06e36b3149d5 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/fw_upg_mtd/firmware_upgrade_mtd.h @@ -0,0 +1,32 @@ +#ifndef __FIRMWARE_UPGRADE_MTD_H__ +#define __FIRMWARE_UPGRADE_MTD_H__ + +#include + +#define FIRMWARE_DEV_NAME_LEN 64 /* the macro definition needs to same as FIRMWARE_DEV_NAME_LEN in firmware_sysfs_upgrade.h */ +#define PATH_LEN (256) +#define FW_MTD_BLOCK_SLEEP_TIME (10000) /* 10ms */ +#define FW_SYSFS_RETRY_SLEEP_TIME (10000) /* 10ms */ +#define FW_SYSFS_RETRY_TIME (5) /* retry 5 times, 50ms = FW_SYSFS_RETRY_TIME *FW_SYSFS_RETRY_SLEEP_TIME; */ + +/* Debug switch level */ +typedef enum { + FIRWMARE_MTD_SUCCESS = 0, + FIRWMARE_MTD_PART_INFO_ERR, + FIRWMARE_MTD_MEMERASE, + FIRWMARE_MTD_MEMGETINFO, + FIRWMARE_END, +} firmware_debug_level_t; + +#define debug(fmt, argv...) do { \ + dbg_print(is_debug_on, ""fmt , ##argv);\ + } while(0) + +typedef struct firmware_mtd_info_s { + char mtd_name[FIRMWARE_DEV_NAME_LEN]; /* sysfs name */ + uint32_t flash_base; /* Flash Upgrade Address */ + uint32_t test_base; /* Test flash address */ + uint32_t test_size; /* Test flash size */ +} firmware_mtd_info_t; + +#endif /* End of __FIRMWARE_UPGRADE_MTD_H__ */ diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/fw_upg_mtd/mtd-abi.h b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/fw_upg_mtd/mtd-abi.h new file mode 100644 index 000000000000..f326d23e732e --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/fw_upg_mtd/mtd-abi.h @@ -0,0 +1,259 @@ + +#ifndef __MTD_ABI_H__ +#define __MTD_ABI_H__ + +#include + +struct erase_info_user { + __u32 start; + __u32 length; +}; + +struct erase_info_user64 { + __u64 start; + __u64 length; +}; + +struct mtd_oob_buf { + __u32 start; + __u32 length; + unsigned char *ptr; +}; + +struct mtd_oob_buf64 { + __u64 start; + __u32 pad; + __u32 length; + __u64 usr_ptr; +}; + +/** + * MTD operation modes + * + * @MTD_OPS_PLACE_OOB: OOB data are placed at the given offset (default) + * @MTD_OPS_AUTO_OOB: OOB data are automatically placed at the free areas + * which are defined by the internal ecclayout + * @MTD_OPS_RAW: data are transferred as-is, with no error correction; + * this mode implies %MTD_OPS_PLACE_OOB + * + * These modes can be passed to ioctl(MEMWRITE) and are also used internally. + * See notes on "MTD file modes" for discussion on %MTD_OPS_RAW vs. + * %MTD_FILE_MODE_RAW. + */ +enum { + MTD_OPS_PLACE_OOB = 0, + MTD_OPS_AUTO_OOB = 1, + MTD_OPS_RAW = 2, +}; + +/** + * struct mtd_write_req - data structure for requesting a write operation + * + * @start: start address + * @len: length of data buffer + * @ooblen: length of OOB buffer + * @usr_data: user-provided data buffer + * @usr_oob: user-provided OOB buffer + * @mode: MTD mode (see "MTD operation modes") + * @padding: reserved, must be set to 0 + * + * This structure supports ioctl(MEMWRITE) operations, allowing data and/or OOB + * writes in various modes. To write to OOB-only, set @usr_data == NULL, and to + * write data-only, set @usr_oob == NULL. However, setting both @usr_data and + * @usr_oob to NULL is not allowed. + */ +struct mtd_write_req { + __u64 start; + __u64 len; + __u64 ooblen; + __u64 usr_data; + __u64 usr_oob; + __u8 mode; + __u8 padding[7]; +}; + +#define MTD_ABSENT 0 +#define MTD_RAM 1 +#define MTD_ROM 2 +#define MTD_NORFLASH 3 +#define MTD_NANDFLASH 4 +#define MTD_DATAFLASH 6 +#define MTD_UBIVOLUME 7 +#define MTD_MLCNANDFLASH 8 + +#define MTD_WRITEABLE 0x400 /* Device is writeable */ +#define MTD_BIT_WRITEABLE 0x800 /* Single bits can be flipped */ +#define MTD_NO_ERASE 0x1000 /* No erase necessary */ +#define MTD_POWERUP_LOCK 0x2000 /* Always locked after reset */ + +/* Some common devices / combinations of capabilities */ +#define MTD_CAP_ROM 0 +#define MTD_CAP_RAM (MTD_WRITEABLE | MTD_BIT_WRITEABLE | MTD_NO_ERASE) +#define MTD_CAP_NORFLASH (MTD_WRITEABLE | MTD_BIT_WRITEABLE) +#define MTD_CAP_NANDFLASH (MTD_WRITEABLE) + +/* Obsolete ECC byte placement modes (used with obsolete MEMGETOOBSEL) */ +#define MTD_NANDECC_OFF 0 // Switch off ECC (Not recommended) +#define MTD_NANDECC_PLACE 1 // Use the given placement in the structure (YAFFS1 legacy mode) +#define MTD_NANDECC_AUTOPLACE 2 // Use the default placement scheme +#define MTD_NANDECC_PLACEONLY 3 // Use the given placement in the structure (Do not store ecc result on read) +#define MTD_NANDECC_AUTOPL_USR 4 // Use the given autoplacement scheme rather than using the default + +/* OTP mode selection */ +#define MTD_OTP_OFF 0 +#define MTD_OTP_FACTORY 1 +#define MTD_OTP_USER 2 + +typedef struct mtd_info_user { + __u8 type; + __u32 flags; + __u32 size; /* Total size of the MTD */ + __u32 erasesize; + __u32 writesize; + __u32 oobsize; /* Amount of OOB data per block (e.g. 16) */ + __u64 padding; /* Old obsolete field; do not use */ +} mtd_info_user_t; + +struct region_info_user { + __u32 offset; /* At which this region starts, + * from the beginning of the MTD */ + __u32 erasesize; /* For this region */ + __u32 numblocks; /* Number of blocks in this region */ + __u32 regionindex; +}; + +struct otp_info { + __u32 start; + __u32 length; + __u32 locked; +}; + +/* + * Note, the following ioctl existed in the past and was removed: + * #define MEMSETOOBSEL _IOW('M', 9, struct nand_oobinfo) + * Try to avoid adding a new ioctl with the same ioctl number. + */ + +/* Get basic MTD characteristics info (better to use sysfs) */ +#define MEMGETINFO _IOR('M', 1, struct mtd_info_user) +/* Erase segment of MTD */ +#define MEMERASE _IOW('M', 2, struct erase_info_user) +/* Write out-of-band data from MTD */ +#define MEMWRITEOOB _IOWR('M', 3, struct mtd_oob_buf) +/* Read out-of-band data from MTD */ +#define MEMREADOOB _IOWR('M', 4, struct mtd_oob_buf) +/* Lock a chip (for MTD that supports it) */ +#define MEMLOCK _IOW('M', 5, struct erase_info_user) +/* Unlock a chip (for MTD that supports it) */ +#define MEMUNLOCK _IOW('M', 6, struct erase_info_user) +/* Get the number of different erase regions */ +#define MEMGETREGIONCOUNT _IOR('M', 7, int) +/* Get information about the erase region for a specific index */ +#define MEMGETREGIONINFO _IOWR('M', 8, struct region_info_user) +/* Get info about OOB modes (e.g., RAW, PLACE, AUTO) - legacy interface */ +#define MEMGETOOBSEL _IOR('M', 10, struct nand_oobinfo) +/* Check if an eraseblock is bad */ +#define MEMGETBADBLOCK _IOW('M', 11, __kernel_loff_t) +/* Mark an eraseblock as bad */ +#define MEMSETBADBLOCK _IOW('M', 12, __kernel_loff_t) +/* Set OTP (One-Time Programmable) mode (factory vs. user) */ +#define OTPSELECT _IOR('M', 13, int) +/* Get number of OTP (One-Time Programmable) regions */ +#define OTPGETREGIONCOUNT _IOW('M', 14, int) +/* Get all OTP (One-Time Programmable) info about MTD */ +#define OTPGETREGIONINFO _IOW('M', 15, struct otp_info) +/* Lock a given range of user data (must be in mode %MTD_FILE_MODE_OTP_USER) */ +#define OTPLOCK _IOR('M', 16, struct otp_info) +/* Get ECC layout (deprecated) */ +#define ECCGETLAYOUT _IOR('M', 17, struct nand_ecclayout_user) +/* Get statistics about corrected/uncorrected errors */ +#define ECCGETSTATS _IOR('M', 18, struct mtd_ecc_stats) +/* Set MTD mode on a per-file-descriptor basis (see "MTD file modes") */ +#define MTDFILEMODE _IO('M', 19) +/* Erase segment of MTD (supports 64-bit address) */ +#define MEMERASE64 _IOW('M', 20, struct erase_info_user64) +/* Write data to OOB (64-bit version) */ +#define MEMWRITEOOB64 _IOWR('M', 21, struct mtd_oob_buf64) +/* Read data from OOB (64-bit version) */ +#define MEMREADOOB64 _IOWR('M', 22, struct mtd_oob_buf64) +/* Check if chip is locked (for MTD that supports it) */ +#define MEMISLOCKED _IOR('M', 23, struct erase_info_user) +/* + * Most generic write interface; can write in-band and/or out-of-band in various + * modes (see "struct mtd_write_req") + */ +#define MEMWRITE _IOWR('M', 24, struct mtd_write_req) + +/* + * Obsolete legacy interface. Keep it in order not to break userspace + * interfaces + */ +struct nand_oobinfo { + __u32 useecc; + __u32 eccbytes; + __u32 oobfree[8][2]; + __u32 eccpos[32]; +}; + +struct nand_oobfree { + __u32 offset; + __u32 length; +}; + +#define MTD_MAX_OOBFREE_ENTRIES 8 +#define MTD_MAX_ECCPOS_ENTRIES 64 +/* + * OBSOLETE: ECC layout control structure. Exported to user-space via ioctl + * ECCGETLAYOUT for backwards compatbility and should not be mistaken as a + * complete set of ECC information. The ioctl truncates the larger internal + * structure to retain binary compatibility with the static declaration of the + * ioctl. Note that the "MTD_MAX_..._ENTRIES" macros represent the max size of + * the user struct, not the MAX size of the internal struct nand_ecclayout. + */ +struct nand_ecclayout_user { + __u32 eccbytes; + __u32 eccpos[MTD_MAX_ECCPOS_ENTRIES]; + __u32 oobavail; + struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES]; +}; + +/** + * struct mtd_ecc_stats - error correction stats + * + * @corrected: number of corrected bits + * @failed: number of uncorrectable errors + * @badblocks: number of bad blocks in this partition + * @bbtblocks: number of blocks reserved for bad block tables + */ +struct mtd_ecc_stats { + __u32 corrected; + __u32 failed; + __u32 badblocks; + __u32 bbtblocks; +}; + +/* + * MTD file modes - for read/write access to MTD + * + * @MTD_FILE_MODE_NORMAL: OTP disabled, ECC enabled + * @MTD_FILE_MODE_OTP_FACTORY: OTP enabled in factory mode + * @MTD_FILE_MODE_OTP_USER: OTP enabled in user mode + * @MTD_FILE_MODE_RAW: OTP disabled, ECC disabled + * + * These modes can be set via ioctl(MTDFILEMODE). The mode mode will be retained + * separately for each open file descriptor. + * + * Note: %MTD_FILE_MODE_RAW provides the same functionality as %MTD_OPS_RAW - + * raw access to the flash, without error correction or autoplacement schemes. + * Wherever possible, the MTD_OPS_* mode will override the MTD_FILE_MODE_* mode + * (e.g., when using ioctl(MEMWRITE)), but in some cases, the MTD_FILE_MODE is + * used out of necessity (e.g., `write()', ioctl(MEMWRITEOOB64)). + */ +enum mtd_file_modes { + MTD_FILE_MODE_NORMAL = MTD_OTP_OFF, + MTD_FILE_MODE_OTP_FACTORY = MTD_OTP_FACTORY, + MTD_FILE_MODE_OTP_USER = MTD_OTP_USER, + MTD_FILE_MODE_RAW, +}; + +#endif /* __MTD_ABI_H__ */ diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/fw_upg_sysfs/firmware_upgrade_sysfs.c b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/fw_upg_sysfs/firmware_upgrade_sysfs.c new file mode 100644 index 000000000000..10a429d93bde --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/fw_upg_sysfs/firmware_upgrade_sysfs.c @@ -0,0 +1,285 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "firmware_upgrade_sysfs.h" + +static int firmware_sysfs_get_dev_info(int fd, firmware_dev_file_info_t *dev_info) +{ + int ret; + + ret = ioctl(fd, FIRMWARE_SYSFS_DEV_FILE_INFO, dev_info); + if (ret < 0) { + dbg_print(is_debug_on, "Failed to get upg flash dev info.\n"); + return ret; + } + + dbg_print(is_debug_on, "sysfs_name=%s per_len=%u.\n", dev_info->sysfs_name, dev_info->per_len); + return 0; +} + +/* sysfs upgrade program function */ +int firmware_upgrade_sysfs_program(firmware_dev_file_info_t *dev_info, uint32_t dev_base, + uint8_t *buf, uint32_t size) +{ + int ret = 0; + uint32_t offset_addr, buf_offset, len; + uint32_t write_len, cmp_retry, reread_len; + int sysfs_fd; + uint8_t *reread_buf; + int i; + + if (dev_info->per_len > 0) { + if (size % dev_info->per_len) { + dbg_print(is_debug_on, "firmware sysfs upgrade size[%u] is width[%u] mismatch, ret %d.\n", + size, dev_info->per_len, ret); + return FIRMWARE_FAILED; + } + len = dev_info->per_len; + } else { + /* Write to the maximum buffer if the length of each write is not configured */ + len = size; + } + + /* Read back data */ + reread_buf = (uint8_t *) malloc(len); + if (reread_buf == NULL) { + dbg_print(is_debug_on, "Error: Failed to malloc memory for read back data buf, len=%u.\n", len); + return FIRMWARE_FAILED; + } + + sysfs_fd = open(dev_info->sysfs_name, O_RDWR | O_SYNC); + if (sysfs_fd < 0) { + dbg_print(is_debug_on, "open file[%s] fail.\n", dev_info->sysfs_name); + free(reread_buf); + return FIRMWARE_FAILED; + } + + offset_addr = dev_base; + buf_offset = 0; + cmp_retry = 0; + while (buf_offset < size) { + /* Calibrate upgrade data length */ + if (buf_offset + len > size) { + len = size - buf_offset; + } + + for (i = 0; i < FW_SYSFS_RETRY_TIME; i++) { + ret = lseek(sysfs_fd, offset_addr, SEEK_SET); + if (ret < 0) { + dbg_print(is_debug_on, "lseek file[%s offset=%u] fail.\n", dev_info->sysfs_name, offset_addr); + close(sysfs_fd); + free(reread_buf); + return FIRMWARE_FAILED; + } + write_len = write(sysfs_fd, buf + buf_offset, len); + if (write_len != len) { + dbg_print(is_debug_on, "write file[%s] fail,offset = 0x%x retrytimes = %u len = %u, write_len =%u\n", + dev_info->sysfs_name, offset_addr, i ,len, write_len); + usleep(FW_SYSFS_RETRY_SLEEP_TIME); + continue; + } + break; + } + + if (i == FW_SYSFS_RETRY_TIME) { + dbg_print(is_debug_on, "write file[%s] fail, offset = 0x%x, len = %u, write_len =%u\n", + dev_info->sysfs_name, offset_addr, len, write_len); + close(sysfs_fd); + free(reread_buf); + return FIRMWARE_FAILED; + } + + mem_clear(reread_buf, len); + ret = lseek(sysfs_fd, offset_addr, SEEK_SET); + if (ret < 0) { + dbg_print(is_debug_on, "reread lseek file[%s offset=%u] fail.\n", dev_info->sysfs_name, offset_addr); + close(sysfs_fd); + free(reread_buf); + return FIRMWARE_FAILED; + } + + for (i = 0; i < FW_SYSFS_RETRY_TIME; i++) { + reread_len = read(sysfs_fd, reread_buf, len); + if (reread_len != len) { + dbg_print(is_debug_on, "reread file[%s] fail,offset = 0x%x retrytimes = %u reread_len = %u, len =%u\n", + dev_info->sysfs_name, offset_addr, i ,reread_len, len); + usleep(FW_SYSFS_RETRY_SLEEP_TIME); + continue; + } + break; + } + if (i == FW_SYSFS_RETRY_TIME) { + dbg_print(is_debug_on, "reread file[%s] fail, offset = 0x%x, reread_len = %u, len = %u\n", + dev_info->sysfs_name, offset_addr, reread_len, len); + close(sysfs_fd); + free(reread_buf); + return FIRMWARE_FAILED; + } + + /* Check data */ + if (memcmp(reread_buf, buf + buf_offset, len) != 0) { + if (cmp_retry < FW_SYSFS_RETRY_TIME) { + dbg_print(is_debug_on, "memcmp file[%s] fail,offset = 0x%x retrytimes = %u\n", + dev_info->sysfs_name, offset_addr, cmp_retry); + cmp_retry++; + continue; + } + + dbg_print(is_debug_on, "upgrade file[%s] fail, offset = 0x%x.\n", dev_info->sysfs_name, offset_addr); + dbg_print(is_debug_on, "want to write buf :\n"); + for (i = 0; i < len; i++) { + dbg_print(is_debug_on, "0x%x ", buf[buf_offset + i]); + if (((i + 1) % 16) == 0) { + dbg_print(is_debug_on, "\n"); + } + } + dbg_print(is_debug_on, "\n"); + + dbg_print(is_debug_on, "actually reread buf :\n"); + for (i = 0; i < len; i++) { + dbg_print(is_debug_on, "0x%x ", reread_buf[i]); + if (((i + 1) % 16) == 0) { + dbg_print(is_debug_on, "\n"); + } + } + dbg_print(is_debug_on, "\n"); + + close(sysfs_fd); + free(reread_buf); + return FIRMWARE_FAILED; + } + offset_addr += len; + buf_offset += len; + usleep(5000); + } + free(reread_buf); + + dbg_print(is_debug_on, "firmware upgrade sysfs success.\n"); + close(sysfs_fd); + return FIRMWARE_SUCCESS; +} + +/* sysfs upgrade function */ +int firmware_upgrade_sysfs(int fd, uint8_t *buf, uint32_t size, name_info_t *info) +{ + int ret = 0; + firmware_dev_file_info_t dev_info; + + if ((buf == NULL) || (info == NULL)) { + dbg_print(is_debug_on, "Input invalid error.\n"); + goto exit; + } + + /* get sysfs information*/ + ret = firmware_sysfs_get_dev_info(fd, &dev_info); + if (ret < 0) { + dbg_print(is_debug_on, "firmware_sysfs_get_dev_info failed, ret %d.\n", ret); + goto exit; + } + + /* enable upgrade access */ + ret = ioctl(fd, FIRMWARE_SYSFS_INIT, NULL); + if (ret < 0) { + dbg_print(is_debug_on, "init dev logic faile\n"); + goto exit; + } + + ret = firmware_upgrade_sysfs_program(&dev_info, dev_info.dev_base, buf, size); + if (ret < 0) { + dbg_print(is_debug_on, "init dev logic faile\n"); + goto fail; + } + + dbg_print(is_debug_on, "firmware upgrade sysfs success.\n"); + /* disable upgrade access */ + ret = ioctl(fd, FIRMWARE_SYSFS_FINISH,NULL); + if (ret < 0) { + dbg_print(is_debug_on, "close dev logic en failed.\n"); + } + return FIRMWARE_SUCCESS; + +fail: + /* disable upgrade access */ + ret = ioctl(fd, FIRMWARE_SYSFS_FINISH, NULL); + if (ret < 0) { + dbg_print(is_debug_on, "close dev logic en failed.\n"); + } +exit: + dbg_print(is_debug_on, "firmware upgrade sysfs fail.\n"); + return FIRMWARE_FAILED; +} + +/* sysfs upgrade test function */ +int firmware_upgrade_sysfs_test(int fd, name_info_t *info) +{ + int ret, rv; + firmware_dev_file_info_t dev_info; + uint8_t *data_buf; + uint8_t num; + int j; + + if (info == NULL) { + dbg_print(is_debug_on, "Input invalid error.\n"); + return FIRMWARE_FAILED; + } + + /* get sysfs information*/ + ret = firmware_sysfs_get_dev_info(fd, &dev_info); + if (ret < 0) { + dbg_print(is_debug_on, "firmware_sysfs_get_dev_info failed, ret %d.\n", ret); + return FIRMWARE_FAILED; + } + + if (dev_info.test_size == 0) { + dbg_print(is_debug_on, "Error: get sysfs test size:%d, not support.\n", dev_info.test_size); + return FIRMWARE_NOT_SUPPORT; + } + + data_buf = (uint8_t *) malloc(dev_info.test_size); + if (data_buf == NULL) { + dbg_print(is_debug_on, "Error: Failed to malloc memory for test data buf, size=%d.\n", dev_info.test_size); + return FIRMWARE_FAILED; + } + + /* Get random data */ + for (j = 0; j < dev_info.test_size; j++) { + num = (uint8_t) rand() % 256; + data_buf[j] = num & 0xff; + } + + /* enable upgrade access */ + ret = ioctl(fd, FIRMWARE_SYSFS_INIT, NULL); + if (ret < 0) { + dbg_print(is_debug_on, "init dev logic faile\n"); + free(data_buf); + return FIRMWARE_FAILED; + } + + ret = firmware_upgrade_sysfs_program(&dev_info, dev_info.test_base, data_buf, dev_info.test_size); + /* disable upgrade access */ + rv = ioctl(fd, FIRMWARE_SYSFS_FINISH,NULL); + if (rv < 0) { + dbg_print(is_debug_on, "close dev logic en failed.\n"); + } + free(data_buf); + + if (ret < 0) { + dbg_print(is_debug_on, "init dev logic faile\n"); + return FIRMWARE_FAILED; + } + + dbg_print(is_debug_on, "firmware upgrade sysfs success.\n"); + return FIRMWARE_SUCCESS; +} diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/fw_upg_sysfs/firmware_upgrade_sysfs.h b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/fw_upg_sysfs/firmware_upgrade_sysfs.h new file mode 100644 index 000000000000..b69080ea642e --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/fw_upg_sysfs/firmware_upgrade_sysfs.h @@ -0,0 +1,16 @@ +#ifndef __FIRMWARE_UPGRADE_SYSFS_H__ +#define __FIRMWARE_UPGRADE_SYSFS_H__ + +#define FIRMWARE_DEV_NAME_LEN (64) /* the macro definition needs to same as FIRMWARE_DEV_NAME_LEN in firmware_sysfs_upgrade.h */ +#define FW_SYSFS_RETRY_SLEEP_TIME (10000) /* 10ms */ +#define FW_SYSFS_RETRY_TIME (5) /* retry 5 times, 50ms = FW_SYSFS_RETRY_TIME *FW_SYSFS_RETRY_SLEEP_TIME; */ + +typedef struct firmware_dev_file_info_s { + char sysfs_name[FIRMWARE_DEV_NAME_LEN]; /* sysfs name */ + uint32_t dev_base; /* device upgrade base address */ + uint32_t per_len; /* The length of bytes per operation */ + uint32_t test_base; /* Test device address */ + uint32_t test_size; /* Test flash size */ +} firmware_dev_file_info_t; + +#endif /* End of __FIRMWARE_UPGRADE_SYSFS_H__ */ diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/fw_upg_sysfs/fw_upg_spi_logic_dev.c b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/fw_upg_sysfs/fw_upg_spi_logic_dev.c new file mode 100644 index 000000000000..7db3c1b7b6ec --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/fw_upg_sysfs/fw_upg_spi_logic_dev.c @@ -0,0 +1,1181 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "fw_upg_spi_logic_dev.h" + +#define be32_to_cpus(p) __be32_to_cpus(p) +#define le32_to_cpus(p) __le32_to_cpus(p) +#define cpu_to_be32s(p) __cpu_to_be32s(p) +#define cpu_to_le32s(p) __cpu_to_le32s(p) + +static void firmware_upgrade_printf_reg(uint8_t *buf, int buf_len, uint32_t offset_addr) +{ + int i, j, tmp; + + j = offset_addr % 16; + tmp = j; + offset_addr -= j; + printf("\n "); + + for (i = 0; i < 16; i++) { + printf("%2x ", i); + } + + for (i = 0; i < buf_len + j; i++) { + if ((i % 16) == 0) { + printf("\n0x%08x ", offset_addr); + offset_addr = offset_addr + 16; + } + if (tmp) { + printf(" "); + tmp--; + } else { + printf("%02x ", buf[i-j]); + } + } + + printf("\n"); + return; +} + +static int firmware_upgrade_get_spi_logic_info(int fd, firmware_spi_logic_upg_t *current_upg_priv) +{ + int ret; + firmware_spi_logic_info_t syfs_info; + + if (fd < 0) { + dbg_print(is_debug_on, "Error: get spi logic info fd %d.\n", fd); + return fd; + } + + ret = 0; + ret = ioctl(fd, FIRMWARE_SYSFS_SPI_INFO, &syfs_info); + if (ret < 0) { + dbg_print(is_debug_on, "Failed to get upg flash dev info, ret=%d\n", ret); + return -FW_SPI_FLASH_GET_INFO_ERR; + } + + current_upg_priv->flash_base = syfs_info.flash_base; + current_upg_priv->ctrl_base = syfs_info.ctrl_base; + memcpy(current_upg_priv->dev_path, syfs_info.logic_dev_name, FIRMWARE_LOGIC_DEV_NAME_LEN - 1); + current_upg_priv->status_reg = syfs_info.ctrl_base + FPGA_UPG_STATUS_REG; + current_upg_priv->spi_ctrl_reg = syfs_info.ctrl_base + FPGA_UPG_SPI_CTRL_REG; + current_upg_priv->wr_flash_status_reg = syfs_info.ctrl_base + FPGA_UPG_WR_FLASH_STATUS_REG; + current_upg_priv->rd_flash_status_reg = syfs_info.ctrl_base + FPGA_UPG_RD_FLASH_STATUS_REG; + current_upg_priv->instruction_reg = syfs_info.ctrl_base + FPGA_UPG_INSTRUCTION_REG; + current_upg_priv->addr_reg = syfs_info.ctrl_base + FPGA_UPG_ADDR_REG; + current_upg_priv->length_reg = syfs_info.ctrl_base + FPGA_UPG_LENGTH_REG; + current_upg_priv->device_id_reg = syfs_info.ctrl_base + FPGA_UPG_DEVICE_ID_REG; + current_upg_priv->drop_reg_num_reg = syfs_info.ctrl_base + FPGA_UPG_DROP_REQ_NUM_REG; + current_upg_priv->test_base = syfs_info.test_base; + current_upg_priv->test_size = syfs_info.test_size; + + return 0; +} + +static int firmware_upgrade_spi_logic_init(int fd) +{ + int ret; + + ret = 0; + ret = ioctl(fd, FIRMWARE_SYSFS_INIT, NULL); + if (ret < 0) { + dbg_print(is_debug_on, "Failed to init spi logic, ret=%d\n", ret); + return -1; + } + + return 0; +} + +static int firmware_upgrade_spi_logic_finish(int fd) +{ + int ret; + + if (fd < 0) { + dbg_print(is_debug_on, "Error: get spi logic info fd %d.\n", fd); + return -1; + } + + ret = 0; + ret = ioctl(fd, FIRMWARE_SYSFS_FINISH, NULL); + if (ret < 0) { + dbg_print(is_debug_on, "Failed to release spi logic, ret=%d\n", ret); + return -1; + } + + return 0; +} + +/** + * firmware_fpga_file_read - + * function:Provide FPGA read-register interface (address must be 4-byte aligned) + * @dev_name: Device file descriptor + * @offset: device offset + * @buf: Read Data Buffer + * @rd_len: Read Data Length + * return: 0--success; other--fail + */ +int firmware_fpga_file_read(char *dev_name, uint32_t offset, uint8_t *buf, uint32_t rd_len) +{ + int ret, fd; + + if ((dev_name == NULL) || (buf == NULL)) { + dbg_print(is_debug_on, "upg_priv or read buf is null.\n"); + return -1; + } + + if ((fd = open(dev_name, O_RDWR, S_IRWXU | S_IRWXG | S_IRWXO)) < 0) { + dbg_print(is_debug_on, "Error: Could not open file %s. Errno=%d\n", dev_name, errno); + return -1; + } + + ret = lseek(fd, offset, SEEK_SET); + if (ret < 0) { + dbg_print(is_debug_on, "read llseek failed, errno: %s\n", strerror(errno)); + close(fd); + return -1; + } + + ret = read(fd, buf, rd_len); + if (ret < 0) { + dbg_print(is_debug_on, "read failed, err: %s\n", strerror(errno)); + close(fd); + return -1; + } + + close(fd); + return 0; +} + +static int firmware_fpga_read_word(char *dev_name, uint32_t addr, uint32_t *val) +{ + int ret; + uint32_t retry; + + if (sizeof(int) < FIRMWARE_FPGA_WORD_LEN) { + dbg_print(is_debug_on, "Error:dfd_fpga_read_word buf len %ld support len %d.\n", + sizeof(int), FIRMWARE_FPGA_WORD_LEN); + return -1; + } + + retry = 0; + *val = 0; + while(retry < FIRMWARE_FPGA_UPG_RETRY_CNT) { + ret = firmware_fpga_file_read(dev_name, addr, (uint8_t *)val, FIRMWARE_FPGA_WORD_LEN); + if (ret) { + retry++; + dbg_print(is_debug_on, "firmware_fpga_file_read addr 0x%x retry %u failed ret %d.\n", + addr, retry, ret); + continue; + } else { + le32_to_cpus(val); + return 0; + } + } + + dbg_print(is_debug_on, "dfd_fpga_read_word addr 0x%x retry %u failed ret %d.\n", addr, retry, ret); + return -1; +} + +static int firmware_fpga_read_buf(char *dev_name, uint32_t addr, uint8_t *buf, uint32_t rd_len) +{ + int ret; + uint32_t retry; + + retry = 0; + while(retry < FIRMWARE_FPGA_UPG_RETRY_CNT) { + ret = firmware_fpga_file_read(dev_name, addr, buf, rd_len); + if (ret) { + retry++; + dbg_print(is_debug_on, "firmware_fpga_file_read addr 0x%x rd_len %u i %d failed ret %d.\n", + addr, rd_len, retry, ret); + continue; + } else { + return 0; + } + } + + dbg_print(is_debug_on, "firmware_fpga_file_read addr 0x%x rd_len %u retry %u failed ret %d.\n", + addr, rd_len, retry, ret); + return -1; +} + +/** + * firmware_fpga_file_write - + * function:Provide FPGA write-register interface (address must be 4-byte aligned) + * @dev_name: Device file descriptor + * @offset: device offset + * @buf: Write Data Buffer + * @wr_len: Write Data Length + * return: 0--success; other--fail + */ +int firmware_fpga_file_write(char *dev_name, uint32_t offset, uint8_t *buf, uint32_t wr_len) +{ + int ret, fd; + + if ((dev_name == NULL) || (buf == NULL)) { + dbg_print(is_debug_on, "dev_name or write buf is null.\n"); + return -1; + } + + if ((fd = open(dev_name, O_RDWR, S_IRWXU | S_IRWXG | S_IRWXO)) < 0) { + dbg_print(is_debug_on, "Error: Could not open file %s. Errno=%d\n", dev_name, errno); + return -1; + } + + ret = lseek(fd, offset, SEEK_SET); + if (ret < 0) { + dbg_print(is_debug_on, "write llseek failed, err: %s\n", strerror(errno)); + close(fd); + return -1; + } + + ret = write(fd, buf, wr_len); + if (ret < 0 ) { + dbg_print(is_debug_on, "write failed, err: %s\n", strerror(errno)); + close(fd); + return -1; + } + + close(fd); + return 0; +} + +static int firmware_fpga_write_word(char *dev_name, uint32_t addr, uint32_t val) +{ + int ret; + uint32_t retry, tmp; + + retry = 0; + tmp = val; + cpu_to_le32s(&tmp); + while(retry < FIRMWARE_FPGA_UPG_RETRY_CNT) { + ret = firmware_fpga_file_write(dev_name, addr, (uint8_t *)&tmp, FIRMWARE_FPGA_WORD_LEN); + if (ret) { + retry++; + dbg_print(is_debug_on, "firmware_fpga_file_write addr 0x%x val 0x%x retry %u failed ret %d.\n", + addr, val, retry, ret); + continue; + } else { + return 0; + } + } + + dbg_print(is_debug_on, "firmware_fpga_file_write addr 0x%x val 0x%x retry %u failed ret %d.\n", + addr, val, retry, ret); + return -1; +} + +static int firmware_fpga_write_buf(char *dev_name, uint32_t addr, uint8_t *buf, uint32_t wr_len) +{ + int ret; + uint32_t retry; + + retry = 0; + while(retry < FIRMWARE_FPGA_UPG_RETRY_CNT) { + ret = firmware_fpga_file_write(dev_name, addr, buf, wr_len); + if (ret) { + retry++; + dbg_print(is_debug_on, "firmware_fpga_file_write addr 0x%x wr_len 0x%x retry %u failed ret %d.\n", + addr, wr_len, retry, ret); + continue; + } else { + return 0; + } + } + + dbg_print(is_debug_on, "dfd_fpga_buf_write addr 0x%x wr_len 0x%x retry %u failed ret %d.\n", + addr, wr_len, retry, ret); + + return -1; +} + +/* Whether the SPI port is idle, 0--idle, 1--busy */ +static int firmware_fpga_get_status(firmware_spi_logic_upg_t *upg_priv, char *status) +{ + int ret; + uint32_t addr, val; + + addr = upg_priv->status_reg; + ret = firmware_fpga_read_word(upg_priv->dev_path, addr, &val); + if (ret) { + dbg_print(is_debug_on, "firmware_fpga_get_status addr 0x%x failed ret %d.\n", addr, ret); + return -1; + } + + *status = val & FPGA_UPG_STATUS_MASK; + + return 0; +} + +/* Wait for the SPI port to become free again */ +static int firmware_fpga_wait_ready(firmware_spi_logic_upg_t *upg_priv) +{ + int timeout; + char status; + int ret; + + timeout = FIRMWARE_UPG_RETRY_TIME_CNT; + while (timeout--) { + usleep(FIRMWARE_UPG_RETRY_SLEEP_TIME); + ret = firmware_fpga_get_status(upg_priv, &status); + if (ret) { + dbg_print(is_debug_on, "firmware_fpga_get_status failed ret %d.\n", ret); + continue; + } + + /* Determine if it's idle */ + if (!status) { + return 0; + } + } + + return -1; +} + +/* Configure access */ +static int firmware_fpga_set_access(firmware_spi_logic_upg_t *upg_priv, uint32_t cmd) +{ + int ret; + uint32_t addr, val; + + addr = upg_priv->instruction_reg; + val = cmd; + ret = firmware_fpga_write_word(upg_priv->dev_path, addr, val); + if (ret) { + dbg_print(is_debug_on, "firmware_fpga_write_word addr 0x%x val 0x%x failed ret %d.\n", addr, val, ret); + return -1; + } + + addr = upg_priv->spi_ctrl_reg; + val = FPGA_UPG_ACCESS_ENABLE; + ret = firmware_fpga_write_word(upg_priv->dev_path, addr, val); + if (ret) { + dbg_print(is_debug_on, "firmware_fpga_write_word addr 0x%x val 0x%x failed ret %d.\n", addr, val, ret); + return -1; + } + + /* Wait for the SPI port on the FPGA to become free again*/ + ret = firmware_fpga_wait_ready(upg_priv); + if (ret) { + dbg_print(is_debug_on,"firmware_fpga_wait_ready failed ret %d.\n", ret); + return -FW_SPI_FLASH_BUSY; + } + + return 0; +} + +/* Get SPI STATUS register */ +static int firmware_fpga_get_spi_status(firmware_spi_logic_upg_t *upg_priv, char *status) +{ + int ret; + uint32_t val, addr, cmd; + + cmd = FPGA_UPG_INSTRUTION_RDSR; + ret = firmware_fpga_set_access(upg_priv, cmd); + if (ret) { + dbg_print(is_debug_on, "firmware_fpga_set_access cmd 0x%x failed ret %d.\n", cmd, ret); + return -1; + } + + addr = upg_priv->rd_flash_status_reg; + ret = firmware_fpga_read_word(upg_priv->dev_path, addr, &val); + if (ret) { + dbg_print(is_debug_on, "firmware_fpga_read_word addr 0x%x failed ret %d.\n", addr, ret); + return -1; + } + + *status = val & FPGA_UPG_SPI_STATUS_MASK; + + return 0; +} + +/* Wait for the SPI chip operation to complete */ +static int firmware_fpga_wait_spi_ready(firmware_spi_logic_upg_t *upg_priv, + uint32_t timeout, uint32_t usleep_time) +{ + char status; + int ret; + + while (timeout--) { + usleep(usleep_time); + ret = firmware_fpga_get_spi_status(upg_priv, &status); + if (ret) { + dbg_print(is_debug_on, "firmware_fpga_get_spi_status failed ret %d.\n", ret); + continue; + } + /* Determine if it's idle */ + if (!status) { + return 0; + } + } + + return -FW_SPI_FLASH_SPI_BUSY; +} + +/* Configure FPGA upgrade write enable */ +static int firmware_fpga_set_wr_enable(firmware_spi_logic_upg_t *upg_priv) +{ + int ret; + uint32_t cmd; + + cmd = FPGA_UPG_INSTRUTION_WREN; + ret = firmware_fpga_set_access(upg_priv, cmd); + if (ret) { + dbg_print(is_debug_on, "firmware_fpga_set_access cmd %d failed ret %d.\n", cmd, ret); + return -1; + } + + return 0; +} + +#if 0 +/* erase all flash */ +static int firmware_fpga_upg_set_erase_all(firmware_spi_logic_upg_t *upg_priv) +{ + int ret; + int cmd; + + /* Wait for the SPI port on the FPGA to become free */ + ret = firmware_fpga_wait_ready(upg_priv); + if (ret) { + dbg_print(is_debug_on, "firmware_fpga_wait_ready failed ret %d.\n", ret); + return -1; + } + + /* Configure FPGA upgrade write enable */ + ret = firmware_fpga_set_wr_enable(upg_priv); + if (ret) { + dbg_print(is_debug_on, "firmware_fpga_set_wr_enable failed ret %d.\n", ret); + return -1; + } + + cmd = FPGA_UPG_INSTRUTION_BE; + ret = firmware_fpga_set_access(upg_priv, cmd); + if (ret) { + dbg_print(is_debug_on, "firmware_fpga_set_access cmd %d failed ret %d.\n", cmd, ret); + return -1; + } + + /* Hardware requirements, delay of 1s */ + sleep(1); + + /* Wait for the SPI chip operation to complete, 1s check status once, max delay 300s */ + ret = firmware_fpga_wait_spi_ready(upg_priv, 300, (1 * 1000 * 1000)); + if (ret) { + dbg_print(is_debug_on, "dfd_fpga_wait_spi_ready failed ret %d.\n", ret); + return -1; + } + + dbg_print(is_debug_on, "Success.\n"); + return 0; +} +#endif + +/* Erase sectors (256 pages, 64K total) */ +static int firmware_fpga_erase_sector(firmware_spi_logic_upg_t *upg_priv, uint32_t spi_addr) +{ + int ret; + uint32_t val, addr, cmd; + + /* Wait for the SPI port on the FPGA to become free again */ + ret = firmware_fpga_wait_ready(upg_priv); + if (ret < 0) { + dbg_print(is_debug_on, "firmware_fpga_wait_ready failed ret %d.\n", ret); + return -FW_SPI_FLASH_BUSY; + } + + /* Enable write */ + ret = firmware_fpga_set_wr_enable(upg_priv); + if (ret < 0) { + dbg_print(is_debug_on, "firmware_fpga_set_wr_enable failed ret %d.\n", ret); + return -FW_SPI_FLASH_WR_ENABLE_ERR; + } + + /* Write erase address */ + val = spi_addr; + addr = upg_priv->addr_reg; + ret = firmware_fpga_write_word(upg_priv->dev_path, addr, val); + if (ret) { + dbg_print(is_debug_on, "firmware_fpga_write_word addr 0x%x val 0x%x failed ret %d.\n", addr, val, ret); + return -FW_SPI_FLASH_ERASE_ADDR_ERR; + } + + /* Enable sector erasure */ + cmd = FPGA_UPG_INSTRUTION_SE; + ret = firmware_fpga_set_access(upg_priv, cmd); + if (ret) { + dbg_print(is_debug_on, "firmware_fpga_set_access cmd %d failed ret %d.\n", cmd, ret); + return -FW_SPI_FLASH_ERASE_SECTOR_ERR; + } + + /* Hardware requirements, delay of 0.25s */ + usleep(250 * 1000); + + /* Wait for the SPI chip operation to complete, 1s check status once, max delay 10s */ + ret = firmware_fpga_wait_spi_ready(upg_priv, FPGA_UPG_WAIT_SPI_RETRY_CNT, (100 * 1000)); + if (ret) { + dbg_print(is_debug_on, "firmware_fpga_wait_spi_ready failed ret %d.\n", ret); + return -FW_SPI_FLASH_SPI_BUSY; + } + + return 0; +} + +#if 0 +int firmware_fpga_erase64_sector(firmware_spi_logic_upg_t *upg_priv, int offset) +{ + int ret; + ret = -1; + + if ((offset % FIRMWARE_SPI_LOGIC_SECTOR_SIZE) == 0) { + dbg_print(is_debug_on, "erase 64k area, offset 0x%x.\n", offset); + ret = firmware_fpga_erase_sector(upg_priv, offset); + if (ret) { + dbg_print(is_debug_on, "firmware_fpga_erase_sector offset 0x%x failed ret %d.\n", offset, ret); + return ret; + } + } else { + dbg_print(is_debug_on, "Input para invalid, offset 0x%x.\n", offset); + } + + return ret; +} +#endif + +static int firmware_fpga_upg_program(firmware_spi_logic_upg_t *upg_priv, + uint32_t spi_addr, uint8_t *buf, uint32_t len) +{ + int ret; + uint32_t addr, val, cmd, wr_len; + + /* Write data to the Upgrade Content Register */ + addr = upg_priv->ctrl_base; + wr_len = len; + ret = firmware_fpga_write_buf(upg_priv->dev_path, addr, (uint8_t*)buf, wr_len); + if (ret) { + dbg_print(is_debug_on,"firmware_fpga_write_buf addr 0x%x wr_len %d failed ret %d.\n", + addr, len, ret); + return -FW_SPI_FLASH_WR_ERR; + } + + /* Write length register, FPGA is fixed 256 lengths */ + val = FFPGA_UPG_DATA_SIZE; + addr = upg_priv->length_reg; + ret = firmware_fpga_write_word(upg_priv->dev_path, addr, val); + if (ret) { + dbg_print(is_debug_on,"firmware_fpga_write_word addr 0x%x val 0x%x failed ret %d.\n", + addr, val, ret); + return -FW_SPI_FLASH_WR_LENGTH_ERR; + } + + /* Write address register */ + val = spi_addr; + addr = upg_priv->addr_reg; + ret = firmware_fpga_write_word(upg_priv->dev_path, addr, val); + if (ret) { + dbg_print(is_debug_on,"firmware_fpga_write_word addr 0x%x val 0x%x failed ret %d.\n", + addr, val, ret); + return -FW_SPI_FLASH_WR_ADDR_ERR; + } + + /* Start writing upgrade data to SPI */ + cmd = FPGA_UPG_INSTRUTION_PP; + ret = firmware_fpga_set_access(upg_priv, cmd); + if (ret) { + dbg_print(is_debug_on,"firmware_fpga_set_access cmd %d failed ret %d.\n", cmd, ret); + return -FW_SPI_FLASH_SET_ACCESS_ERR; + } + + /* min write wait 0.33ms */ + usleep(330); + + /* Wait for the SPI chip operation to complete, 100us check status once, max delay 10ms */ + ret = firmware_fpga_wait_spi_ready(upg_priv, FPGA_UPG_WAIT_SPI_RETRY_CNT, (100)); + if (ret) { + dbg_print(is_debug_on,"firmware_fpga_wait_spi_ready failed ret %d.\n", ret); + return -FW_SPI_FLASH_BUSY; + } + + return 0; +} + +/** + * firmware_fpga_upg_write + * function: write interface provided to the upgrade module + * @upg_priv: Device information + * @addr: upgrade addr + * @buf: Write Data Buffer + * @len: Write Data Length + * return: 0--success; other--fail + */ +static int firmware_fpga_upg_write(firmware_spi_logic_upg_t *upg_priv, + uint32_t addr, uint8_t *buf, uint32_t len) +{ + int ret; + + /* address must be 256 bytes aligned */ + if ((upg_priv == NULL) || (buf == NULL) || (addr & 0xff) || (len > 256)) { + dbg_print(is_debug_on,"Input para invalid upg_priv %p buf %p addr 0x%x len %u.\n", + upg_priv, buf, addr, len); + return -FW_SPI_FLASH_PARAM_ERR; + } + + /* Wait for the SPI port on the FPGA to become free again*/ + ret = firmware_fpga_wait_ready(upg_priv); + if (ret) { + dbg_print(is_debug_on,"firmware_fpga_wait_ready failed ret %d.\n", ret); + return -FW_SPI_FLASH_BUSY; + } + + /* Configure write enable */ + ret = firmware_fpga_set_wr_enable(upg_priv); + if (ret) { + dbg_print(is_debug_on,"firmware_fpga_set_wr_enable failed ret %d.\n", ret); + return -FW_SPI_FLASH_WR_ENABLE_ERR; + } + + /* Write upgrade data */ + ret = firmware_fpga_upg_program(upg_priv, addr, buf, len); + if (ret) { + dbg_print(is_debug_on,"dfd_fpga_upg_program addr 0x%x len %u failed ret %d.\n", addr, len, ret); + return -FW_SPI_FLASH_UPG_ERR; + } + + return 0; +} + +static int firmware_fpga_fast_read(firmware_spi_logic_upg_t *upg_priv, + uint32_t spi_addr, uint8_t *buf, uint32_t len) +{ + int ret; + uint32_t val, addr, cmd; + + /* Clear register value */ + addr = upg_priv->ctrl_base; + ret = firmware_fpga_write_buf(upg_priv->dev_path, addr, buf, len); + if (ret) { + dbg_print(is_debug_on, "firmware_fpga_write_buf addr 0x%x len %d failed ret %d.\n", addr, len, ret); + return -FW_SPI_FLASH_WR_ERR; + } + /* Write length register */ + val = FFPGA_UPG_DATA_SIZE; + addr = upg_priv->length_reg; + ret = firmware_fpga_write_word(upg_priv->dev_path, addr, val); + if (ret) { + dbg_print(is_debug_on, "firmware_fpga_write_word addr 0x%x val 0x%x failed ret %d.\n", + addr, val, ret); + return -FW_SPI_FLASH_WR_LENGTH_ERR; + } + + /* Write address register */ + val = spi_addr; + addr = upg_priv->addr_reg; + ret = firmware_fpga_write_word(upg_priv->dev_path, addr, val); + if (ret) { + dbg_print(is_debug_on, "firmware_fpga_write_word addr 0x%x val 0x%x failed ret %d.\n", + addr, val, ret); + return -FW_SPI_FLASH_WR_ADDR_ERR; + } + + /* Start reading SPI data */ + cmd = FPGA_UPG_INSTRUTION_FR; + ret = firmware_fpga_set_access(upg_priv, cmd); + if (ret) { + dbg_print(is_debug_on, "firmware_fpga_set_access cmd %d failed ret %d.\n", cmd, ret); + return -FW_SPI_FLASH_SET_ACCESS_ERR; + } + + /* Read the upgraded content register to the buffer, + * FPGA only supports 4 bytes of read and write */ + addr = upg_priv->ctrl_base; + ret = firmware_fpga_read_buf(upg_priv->dev_path, addr, (uint8_t*)buf, len); + if (ret) { + dbg_print(is_debug_on, "firmware_fpga_read_buf addr 0x%x len %d failed ret %d.\n", addr, len, ret); + return -FW_SPI_FLASH_RD_ERR; + } + + return 0; +} + +/** + * firmware_fpga_upg_read + * function: read interface provided to the upgrade module + * @upg_priv: Device information + * @addr: upgrade addr + * @buf: Read Data Buffer + * @len: Read Data Length + * return: 0--success; other--fail + */ +static int firmware_fpga_upg_read(firmware_spi_logic_upg_t *upg_priv, + uint32_t addr, uint8_t *buf, uint32_t len) +{ + int ret; + + /* address must be 256 bytes aligned */ + if ((upg_priv == NULL) || (buf == NULL) || (addr & 0xff) || (len > 256)) { + dbg_print(is_debug_on, "Input para invalid upg_priv %p buf %p addr 0x%x len %u.\n", + upg_priv, buf, addr, len); + return -FW_SPI_FLASH_PARAM_ERR; + } + + /* Wait for the SPI port on the FPGA to become free again */ + ret = firmware_fpga_wait_ready(upg_priv); + if (ret) { + dbg_print(is_debug_on, "firmware_fpga_wait_ready failed ret %d.\n", ret); + return -FW_SPI_FLASH_BUSY; + } + + /* Configure write enable */ + ret = firmware_fpga_set_wr_enable(upg_priv); + if (ret) { + dbg_print(is_debug_on, "firmware_fpga_set_wr_enable failed ret %d.\n", ret); + return -FW_SPI_FLASH_WR_ENABLE_ERR; + } + + /* Read upgrade data */ + ret = firmware_fpga_fast_read(upg_priv, addr, buf, len); + if (ret) { + dbg_print(is_debug_on, "firmware_fpga_fast_read addr 0x%x len %u failed ret %d.\n", addr, len, ret); + return -FW_SPI_FLASH_RD_ERR; + } + + return 0; + +} + +static int firmware_upgreade_fpga_onetime(firmware_spi_logic_upg_t *upg_priv, + uint32_t flash_base, uint8_t *buf, uint32_t size) +{ + uint32_t offset, len, flash_addr, retry; + int ret, res; + uint8_t rbuf[FFPGA_UPG_DATA_SIZE]; + + offset = 0; + while(offset < size) { + flash_addr = flash_base + offset; + /* Erases a sector */ + if ((flash_addr % FIRMWARE_SPI_LOGIC_SECTOR_SIZE) == 0) { + ret = firmware_fpga_erase_sector(upg_priv, flash_addr); + if (ret < 0) { + dbg_print(is_debug_on, "firmware_fpga_erase_sector flash_addr 0x%x failed ret %d.\n", + flash_addr, ret); + goto exit; + } + } + + if (size > FFPGA_UPG_DATA_SIZE) { + len = FFPGA_UPG_DATA_SIZE; + } else { + len = size; + } + + /* first, Write data */ + ret = firmware_fpga_upg_write(upg_priv, flash_addr, buf + offset, len); + if (ret) { + dbg_print(is_debug_on, "firmware_fpga_upg_write addr 0x%x len 0x%x failed ret %d.\n", + flash_addr, len, ret); + ret = -FW_SPI_FLASH_UPG_ERR; + goto exit; + } + + /* Read back the data and compare the correctness of the data */ + for (retry = 0; retry < FPGA_UPG_RETRY_TIMES; retry++) { /*retry 3 times*/ + mem_clear(rbuf, len); + ret = firmware_fpga_upg_read(upg_priv, flash_addr, rbuf, len); + res = memcmp(rbuf, buf + offset, len); + if (ret || res) { + usleep(1000); + continue; + } + break; + } + + if (ret) { + dbg_print(is_debug_on, "firmware fpga read offset 0x%x len 0x%x failed ret %d.\n", flash_addr, len, ret); + ret = -FW_SPI_FLASH_RD_ERR; + goto exit; + } + + if (res) { + dbg_print(is_debug_on, "firmware fpga rbuf wbuf not equal, len 0x%x, check failed.\n", len); + ret = -FW_SPI_FLASH_DATA_CMP_ERR; + goto exit; + } + offset += len; + } + + dbg_print(is_debug_on, "Update success.\n"); + return FIRMWARE_SUCCESS; +exit: + dbg_print(is_debug_on, "Update failed.\n"); + return FIRMWARE_FAILED; +} + +static int firmware_upgrade_do_spi_logic(firmware_spi_logic_upg_t *current_upg_priv, + unsigned char *buf, uint32_t size) +{ + int i, ret; + uint32_t retry; + + i = 0; + retry = FIRMWARE_SPI_LOGIC_UPG_RETRY_CNT; + + ret = 0; + while(i < retry) { + ret = firmware_upgreade_fpga_onetime(current_upg_priv, current_upg_priv->flash_base, buf, size); + if (ret) { + i++; + dbg_print(is_debug_on, "firmware_upgreade_fpga_onetime size 0x%x failed ret %d.\n", size, ret); + continue; + } else { + dbg_print(is_debug_on, "firmware_upgreade_fpga_onetime success.\n"); + return 0; + } + } + + return ret; +} + +/* + * firmware_upgrade_spi_logic_dev + * function: FPGA SPI FLASH Firmware upgrade handler function + * @fd: param[in] sysfs device descriptor + * @buf: param[in] Update data + * @size: param[in] Update data size + * @info: param[in] Upgrade file information + * return value : success--FIRMWARE_SUCCESS; fail--FIRMWARE_FAILED + */ +int firmware_upgrade_spi_logic_dev(int fd, uint8_t *buf, uint32_t size, name_info_t *info) +{ + int ret; + firmware_spi_logic_upg_t current_upg_priv; + + if ((fd < 0) || (buf == NULL) || (info == NULL)) { + dbg_print(is_debug_on, "Error:firmware upgrade spi logic dev parameters failed.\n"); + return FIRMWARE_FAILED; + } + + /* Gets the current logical device information */ + mem_clear(¤t_upg_priv, sizeof(firmware_spi_logic_upg_t)); + ret = firmware_upgrade_get_spi_logic_info(fd, ¤t_upg_priv); + if (ret < 0) { + dbg_print(is_debug_on, "Error:firmware_upgrade_get_spi_logic_info failed ret %d.\n", ret); + return FIRMWARE_FAILED; + } + + dbg_print(is_debug_on, "current_upg_priv dev_path[%s] flash_base[0x%0x] ctrl_base[0x%0x]\n", + current_upg_priv.dev_path, current_upg_priv.flash_base, + current_upg_priv.ctrl_base); + + /* Enable upgrade access */ + ret = firmware_upgrade_spi_logic_init(fd); + if (ret < 0) { + dbg_print(is_debug_on, "Error:firmware_upgrade_spi_logic_init failed ret %d.\n", ret); + return FIRMWARE_FAILED; + } + + /* Upgrade logic device */ + ret = firmware_upgrade_do_spi_logic(¤t_upg_priv, buf, size); + if (ret < 0) { + dbg_print(is_debug_on, "Error:firmware_upgrade_do_spi_logic failed ret %d.\n", ret); + goto fail; + } + + /* disable upgrade access */ + ret = firmware_upgrade_spi_logic_finish(fd); + if (ret < 0) { + dbg_print(is_debug_on, "Error:firmware_upgrade_spi_logic_finish failed ret %d.\n", ret); + } + + return FIRMWARE_SUCCESS; +fail: + /* disable upgrade access */ + ret = firmware_upgrade_spi_logic_finish(fd); + if (ret < 0) { + dbg_print(is_debug_on, "Error:firmware_upgrade_spi_logic_finish failed ret %d.\n", ret); + } + + return FIRMWARE_FAILED; +} + +int firmware_fpga_upgrade_test(firmware_spi_logic_upg_t *current_upg_priv) +{ + int ret, i, j, num; + uint8_t *wbuf; + uint32_t retry; + + ret = FW_SPI_FLASH_RV_OK; + wbuf = (uint8_t *) malloc(current_upg_priv->test_size); + if (wbuf == NULL) { + dbg_print(is_debug_on, "Error: Failed to malloc memory for test data buf, size=0x%x.\n", current_upg_priv->test_size); + ret = -FW_SPI_FLASH_NOT_SUPPORT_TEST; + goto exit; + } + mem_clear(wbuf, current_upg_priv->test_size); + /* Get random data */ + for (j = 0; j < current_upg_priv->test_size; j++) { + num = rand() % 256; + wbuf[j] = num & 0xff; + } + + i = 0; + retry = FIRMWARE_SPI_LOGIC_UPG_RETRY_CNT; + + ret = 0; + while(i < retry) { + ret = firmware_upgreade_fpga_onetime(current_upg_priv, current_upg_priv->test_base, wbuf, current_upg_priv->test_size); + if (ret) { + i++; + dbg_print(is_debug_on, "firmware_upgreade_fpga_onetime test size 0x%x failed ret %d.\n", + current_upg_priv->test_size, ret); + continue; + } else { + dbg_print(is_debug_on, "firmware_upgreade_fpga_onetime test success.\n"); + break; + } + } + free(wbuf); +exit: + return ret; +} + +/* + * firmware_upgrade_spi_logic_dev_test + * function: FPGA SPI FLASH Firmware upgrade test handler function + * @fd: param[in] sysfs device descriptor + * @buf: param[in] Update data + * @size: param[in] Update data size + * @info: param[in] Upgrade file information + * return value : success--FIRMWARE_SUCCESS; fail--FIRMWARE_FAILED + */ +int firmware_upgrade_spi_logic_dev_test(int fd, name_info_t *info) +{ + int ret; + firmware_spi_logic_upg_t current_upg_priv; + + if ((fd < 0) || (info == NULL)) { + dbg_print(is_debug_on, "Error:firmware upgrade spi logic dev parameters failed.\n"); + return FIRMWARE_FAILED; + } + + /* Gets the current logical device information */ + mem_clear(¤t_upg_priv, sizeof(firmware_spi_logic_upg_t)); + ret = firmware_upgrade_get_spi_logic_info(fd, ¤t_upg_priv); + if (ret < 0) { + dbg_print(is_debug_on, "Error:firmware_upgrade_get_spi_logic_info failed ret %d.\n", ret); + return FIRMWARE_FAILED; + } + + dbg_print(is_debug_on, "current_upg_priv dev_path[%s] test_base[0x%0x] test_size[0x%x]\n", + current_upg_priv.dev_path, current_upg_priv.test_base, current_upg_priv.test_size); + if (current_upg_priv.test_size <= 0) { + dbg_print(is_debug_on, "Error: don't support flast test.\n"); + return FIRMWARE_NOT_SUPPORT; + } + + /* Enable upgrade access */ + ret = firmware_upgrade_spi_logic_init(fd); + if (ret < 0) { + dbg_print(is_debug_on, "Error:firmware_upgrade_spi_logic_init failed ret %d.\n", ret); + return FIRMWARE_FAILED; + } + + /* Upgrade logic device */ + ret = firmware_fpga_upgrade_test(¤t_upg_priv); + if (ret < 0) { + dbg_print(is_debug_on, "Error:firmware_upgrade_do_spi_logic failed ret %d.\n", ret); + goto fail; + } + + /* disable upgrade access */ + ret = firmware_upgrade_spi_logic_finish(fd); + if (ret < 0) { + dbg_print(is_debug_on, "Error:firmware_upgrade_spi_logic_finish failed ret %d.\n", ret); + } + + return FIRMWARE_SUCCESS; +fail: + /* disable upgrade access */ + ret = firmware_upgrade_spi_logic_finish(fd); + if (ret < 0) { + dbg_print(is_debug_on, "Error:firmware_upgrade_spi_logic_finish failed ret %d.\n", ret); + } + + return FIRMWARE_FAILED; +} + +static int firmware_upgreade_spi_logic_dump(firmware_spi_logic_upg_t *upg_priv, + uint32_t offset, uint8_t *buf, uint32_t size) +{ + int ret, i; + uint32_t addr, buf_page, retry, cnt, rd_len; + + buf_page = FFPGA_UPG_DATA_SIZE; /* read data by BUF SIZE each time */ + + cnt = size / FFPGA_UPG_DATA_SIZE; + if (size % FFPGA_UPG_DATA_SIZE) { + cnt++; + } + dbg_print(is_debug_on, "need read number of times:%d.\n", cnt); + + for (i = 0; i < cnt; i++) { + addr = offset + i * FFPGA_UPG_DATA_SIZE; + if (i == (cnt - 1)) { + /* last time read remain size */ + rd_len = size - buf_page * i; + } else { + /* each time read buf page size */ + rd_len = buf_page; + } + + for (retry = 0; retry < FPGA_UPG_RETRY_TIMES; retry++) { + ret = firmware_fpga_upg_read(upg_priv, addr, buf, rd_len); + if (ret < 0) { + dbg_print(is_debug_on, "addr:0x%x read %d time failed. ret %d\n", addr, retry, ret); + continue; + } + break; + } + + if (ret < 0) { + dbg_print(is_debug_on, "finally addr:0x%x read failed ret %d\n", addr, ret); + return FIRMWARE_FAILED; + } + + buf += rd_len; /* buf pointer offset rd_len */ + } + + return FIRMWARE_SUCCESS; +} + +static int firmware_fpga_dump_read(int fd, uint32_t offset, uint8_t *buf, uint32_t len) +{ + int ret; + firmware_spi_logic_upg_t current_upg_priv; + + if ((fd < 0) || (buf == NULL)) { + dbg_print(is_debug_on, "Error:firmware upgrade spi logic dev parameters failed.\n"); + return FIRMWARE_FAILED; + } + + /* Gets the current logical device information */ + mem_clear(¤t_upg_priv, sizeof(firmware_spi_logic_upg_t)); + ret = firmware_upgrade_get_spi_logic_info(fd, ¤t_upg_priv); + if (ret < 0) { + dbg_print(is_debug_on, "Error:firmware_upgrade_get_spi_logic_info failed ret %d.\n", ret); + return FIRMWARE_FAILED; + } + + dbg_print(is_debug_on, "current_upg_priv dev_path[%s] flash_base[0x%0x] ctrl_base[0x%0x]\n", + current_upg_priv.dev_path, current_upg_priv.flash_base, + current_upg_priv.ctrl_base); + + /* Enable upgrade access */ + ret = firmware_upgrade_spi_logic_init(fd); + if (ret < 0) { + dbg_print(is_debug_on, "Error:firmware_upgrade_spi_logic_init failed ret %d.\n", ret); + return FIRMWARE_FAILED; + } + + /* read logic device */ + ret = firmware_upgreade_spi_logic_dump(¤t_upg_priv, offset, buf, len); + if (ret < 0) { + dbg_print(is_debug_on, "Error:firmware_upgrade_do_spi_logic failed ret %d.\n", ret); + goto fail; + } + + /* disable upgrade access */ + ret = firmware_upgrade_spi_logic_finish(fd); + if (ret < 0) { + dbg_print(is_debug_on, "Error:firmware_upgrade_spi_logic_finish failed ret %d.\n", ret); + } + + return FIRMWARE_SUCCESS; + +fail: + /* disable upgrade access */ + ret = firmware_upgrade_spi_logic_finish(fd); + if (ret < 0) { + dbg_print(is_debug_on, "Error:firmware_upgrade_spi_logic_finish failed ret %d.\n", ret); + } + + return FIRMWARE_FAILED; +} + +int firmware_upgrade_spi_logic_dev_dump(char *dev_name, uint32_t offset, + uint32_t len, char *record_file) +{ + int ret, dev_fd, file_fd; + char save_file[FIRMWARE_LOGIC_DEV_NAME_LEN]; + uint8_t *buf; + + dev_fd = open(dev_name, O_RDWR); + if (dev_fd < 0) { + dbg_print(is_debug_on, "Error: Failed to open %s, errno:%d.\n", dev_name, errno); + return FIRMWARE_FAILED; + } + + dbg_print(is_debug_on, "open dev file %s succeeded.\n", dev_name); + + buf = (uint8_t *) malloc(len); + if (buf == NULL) { + dbg_print(is_debug_on, "Error: Failed to malloc memory read %s data.\n", dev_name); + ret = FIRMWARE_FAILED; + goto free_dev_fd; + } + + mem_clear(buf, len); + ret = firmware_fpga_dump_read(dev_fd, offset, buf, len); + if (ret < 0) { + dbg_print(is_debug_on, "addr 0x%x read 0x%x failed ret:%d\n", offset, len, ret); + goto free_data; + } + + dbg_print(is_debug_on, "dump data succeeded. offset:0x%x, len:0x%x\n", offset, len); + + if (strcmp(record_file, "print") != 0) { /* record dump data on 'record_file' */ + mem_clear(save_file, FIRMWARE_LOGIC_DEV_NAME_LEN); + strncpy(save_file, record_file, FIRMWARE_LOGIC_DEV_NAME_LEN - 1); + file_fd = open(save_file, O_RDWR|O_CREAT|O_TRUNC, S_IRWXG|S_IRWXU|S_IRWXO); + if (file_fd < 0) { + dbg_print(is_debug_on, "open file %s fail, errno:%d.\n", save_file, errno); + ret = -ENOENT; + goto free_data; + } + + dbg_print(is_debug_on, "open save file %s succeeded.\n", save_file); + + ret = write(file_fd, buf, len); + if (ret < 0) { + dbg_print(is_debug_on, "write failed (errno: %d).\n", errno); + goto free_file_fd; + } + dbg_print(is_debug_on, "write save file %s succeeded.\n", save_file); + ret = FIRMWARE_SUCCESS; + } else { /* print reg on terminal by format */ + firmware_upgrade_printf_reg((uint8_t*)buf, len, offset); + ret = FIRMWARE_SUCCESS; + goto free_data; + } + +free_file_fd: + close(file_fd); +free_data: + free(buf); +free_dev_fd: + close(dev_fd); + + return ret; +} diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/fw_upg_sysfs/fw_upg_spi_logic_dev.h b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/fw_upg_sysfs/fw_upg_spi_logic_dev.h new file mode 100644 index 000000000000..32f820161e86 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/fw_upg_sysfs/fw_upg_spi_logic_dev.h @@ -0,0 +1,90 @@ +#ifndef __FW_UPG_SPI_LOGIC_DEV_H__ +#define __FW_UPG_SPI_LOGIC_DEV_H__ + +#define FIRMWARE_FPGA_WORD_LEN (4) + +#define FIRMWARE_LOGIC_DEV_NAME_LEN (64) /* the macro definition needs to same as FIRMWARE_DEV_NAME_LEN in firmware_sysfs_upgrade.h */ +#define FIRMWARE_SPI_LOGIC_UPG_RETRY_CNT (10) +#define FIRMWARE_SPI_LOGIC_UPG_BUFF_SIZE (256) +#define FIRMWARE_SPI_LOGIC_SECTOR_SIZE (0x10000) /* One sector is 64Kk */ + +#define FIRMWARE_UPG_RETRY_SLEEP_TIME (10) /* 10us */ +#define FIRMWARE_UPG_RETRY_TIME_CNT (1000) +#define FPGA_UPG_WAIT_SPI_RETRY_CNT (100) +#define FPGA_UPG_WAIT_SPI_RETRY_SLEEP_TIME (1000 * 10) /* 10ms */ + +#define FIRMWARE_FPGA_UPG_RETRY_CNT (100) + +/* FPGA upgrades related instruction definitions */ +#define FPGA_UPG_INSTRUTION_SE (0xD8) +#define FPGA_UPG_INSTRUTION_RDSR (0x05) +#define FPGA_UPG_INSTRUTION_WREN (0x06) +#define FPGA_UPG_INSTRUTION_PP (0x02) +#define FPGA_UPG_INSTRUTION_FR (0x0B) +#define FPGA_UPG_INSTRUTION_BE (0xC7) +#define FPGA_UPG_STATUS_MASK (0x1) +#define FPGA_UPG_ACCESS_ENABLE (0x3) +#define FPGA_UPG_SPI_STATUS_MASK (0x1) +#define FFPGA_UPG_DATA_SIZE (256) + +#define FPGA_UPG_RETRY_TIMES (3) + +/* FPGA upgrades the offset of the associated register */ +#define FPGA_UPG_STATUS_REG (0x180) +#define FPGA_UPG_SPI_CTRL_REG (0x184) +#define FPGA_UPG_WR_FLASH_STATUS_REG (0x188) +#define FPGA_UPG_RD_FLASH_STATUS_REG (0x18C) +#define FPGA_UPG_INSTRUCTION_REG (0x190) +#define FPGA_UPG_ADDR_REG (0x194) +#define FPGA_UPG_LENGTH_REG (0x198) +#define FPGA_UPG_DEVICE_ID_REG (0x19C) +#define FPGA_UPG_DROP_REQ_NUM_REG (0x1A8) + +typedef struct firmware_spi_logic_info_s { + char logic_dev_name[FIRMWARE_LOGIC_DEV_NAME_LEN]; /* Logical device name */ + uint32_t flash_base; /* Flash Upgrade Address */ + uint32_t ctrl_base; /* SPI upgrade control register base address */ + uint32_t test_base; /* Test flash address */ + uint32_t test_size; /* Test flash size */ +} firmware_spi_logic_info_t; + +typedef struct firmware_spi_logic_upg_s { + char dev_path[FIRMWARE_LOGIC_DEV_NAME_LEN]; + uint32_t flash_base; /* Flash Upgrade Address */ + uint32_t ctrl_base; /* SPI upgrade control register base address */ + uint32_t status_reg; + uint32_t spi_ctrl_reg; + uint32_t wr_flash_status_reg; + uint32_t rd_flash_status_reg; + uint32_t instruction_reg; + uint32_t addr_reg; + uint32_t length_reg; + uint32_t device_id_reg; + uint32_t drop_reg_num_reg; + uint32_t test_base; /* Test flash address */ + uint32_t test_size; /* Test flash size */ +}firmware_spi_logic_upg_t; + +typedef enum firmware_spi_flash_rv_s { + FW_SPI_FLASH_RV_OK = 0, + FW_SPI_FLASH_STATUS_ERR, + FW_SPI_FLASH_BUSY, + FW_SPI_FLASH_SPI_BUSY, + FW_SPI_FLASH_WR_ENABLE_ERR, + FW_SPI_FLASH_ERASE_ADDR_ERR, + FW_SPI_FLASH_ERASE_SECTOR_ERR, + FW_SPI_FLASH_WR_ERR, + FW_SPI_FLASH_RD_ERR, + FW_SPI_FLASH_PARAM_ERR, + FW_SPI_FLASH_UPG_ERR, + FW_SPI_FLASH_WR_LENGTH_ERR, + FW_SPI_FLASH_WR_ADDR_ERR, + FW_SPI_FLASH_SET_ACCESS_ERR, + FW_SPI_FLASH_DATA_CMP_ERR, + FW_SPI_FLASH_GET_INFO_ERR, + FW_SPI_FLASH_NOT_SUPPORT_TEST, +} firmware_spi_flash_rv_t; + +int fpga_test_spi_logic_flash(int argc, char *argv[]); + +#endif /* End of __FW_UPG_SPI_LOGIC_DEV_H__ */ diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/include/debug.h b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/include/debug.h new file mode 100644 index 000000000000..17dd42c3ef77 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/include/debug.h @@ -0,0 +1,34 @@ +/* + * + * debug.h + * firmware upgrade debug switch control + */ + +#ifndef __FIRMWARE_UPGRADE_DEBUG_H__ +#define __FIRMWARE_UPGRADE_DEBUG_H__ +#include + +#define mem_clear(data, size) memset((data), 0, (size)) + +#define DEBUG_INFO_LEN 20 +#define DEBUG_FILE "/tmp/.firmware_upgrade_debug" +#define DEBUG_ON_ALL "3" +#define DEBUG_ON_INFO "1" +#define DEBUG_OFF_INFO "0" + +enum debug_s { + DEBUG_OFF = 0, /* off debug */ + DEBUG_APP_ON, /* open app debug */ + DEBUG_ALL_ON, /* open all debug */ + DEBUG_IGNORE, /* ignore debug */ +}; + +#define dbg_print(debug, fmt, arg...) \ + if (debug == DEBUG_APP_ON || debug == DEBUG_ALL_ON) \ + { do{printf(fmt,##arg);} while(0); } + +/* firmware upgrade debug switch */ +extern int firmware_upgrade_debug(void); +extern int is_debug_on; + +#endif /* End of __FIRMWARE_UPGRADE_DEBUG_H__ */ diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/include/firmware_app.h b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/include/firmware_app.h new file mode 100644 index 000000000000..581b2e969ec9 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/include/firmware_app.h @@ -0,0 +1,172 @@ +#ifndef __FIRMWARE_APP_H__ +#define __FIRMWARE_APP_H__ + +#include +#include +#include +#include +#include +#include + +#define ERR_FW_CHECK_CPLD_UPGRADE (-601) /* File validation error */ +#define ERR_FW_CHECK_FPGA_UPGRADE (-602) +#define ERR_FW_MATCH_CPLD_UPGRADE (-603) /* No matching upgrade file found */ +#define ERR_FW_MATCH_FPGA_UPGRADE (-604) +#define ERR_FW_SAMEVER_CPLD_UPGRADE (-605) /* the same version */ +#define ERR_FW_SAMEVER_FPGA_UPGRADE (-606) +#define ERR_FW_DO_CPLD_UPGRADE (-607) /* upgrade fail */ +#define ERR_FW_DO_FPGA_UPGRADE (-608) +#define ERR_FW_UPGRADE (-609) /* other fail */ +#define ERR_FW_CHECK_UPGRADE (-610) /* File validation error */ +#define ERR_FW_MATCH_UPGRADE (-611) /* No matching upgrade file found */ +#define ERR_FW_SAMEVER_UPGRADE (-612) /* the same version */ +#define ERR_FW_DO_UPGRADE (-613) /* upgrade fail */ +#define ERR_FW_DO_UPGRADE_NOT_SUPPORT (-614) /* upgrade fail */ + +#define FIRMWARE_NOT_SUPPORT (-2) +#define FIRMWARE_FAILED (-1) +#define FIRMWARE_SUCCESS (0) + +#define FIRMWARE_ACTION_CHECK 0 +#define FIRMWARE_ACTION_MATCH 1 +#define FIRMWARE_ACTION_VERCHECK 2 +#define FIRMWARE_ACTION_UPGRADE 3 +#define FIRMWARE_ACTION_SUPPORT 4 + +#define FIRMWARE_UPGRADE_RETRY_CNT (10) +#define FIRMWARE_NAME_LEN (48) +#define FIRMWARE_SLOT_MAX_NUM (16) /* Maximum number of links supported by board cards */ + +/* Upgrade file headers */ +#define MAX_DEV_NUM 10 /* Maximum number of devices to which the upgrade file is applicable */ +#define INSMOD_DRIVER 1 /* insmod driver */ +#define RMMOD_DRIVER 0 /* rmmod driver */ +#define MAX_HEADER_SIZE 1000 /* Upgrade the maximum length of file header information */ +#define MAX_HEADER_KV_SIZE 64 /* Upgrade the maximum length of the file header key value */ + +/* Upgrade file header key values */ +#define FILEHEADER_DEVTYPE "DEVTYPE" +#define FILEHEADER_SUBTYPE "SUBTYPE" +#define FILEHEADER_TYPE "TYPE" +#define FILEHEADER_CHAIN "CHAIN" +#define FILEHEADER_CHIPNAME "CHIPNAME" +#define FILEHEADER_VERSION "VERSION" +#define FILEHEADER_FILETYPE "FILETYPE" +#define FILEHEADER_CRC "CRC" + +#define FIRMWARE_CPLD_NAME "cpld" +#define FIRMWARE_FPGA_NAME "fpga" + +/* ioctl publi command, the same as driver */ +#define FIRMWARE_COMMON_TYPE 'C' +#define FIRMWARE_GET_CHIPNAME _IOR(FIRMWARE_COMMON_TYPE, 0, char) /* get the chip name */ +#define FIRMWARE_GET_VERSION _IOR(FIRMWARE_COMMON_TYPE, 2, int) /* get version */ +#define FIRMWARE_SET_DEBUG_ON _IOW(FIRMWARE_COMMON_TYPE, 3, int) /* debug on */ +#define FIRMWARE_SET_DEBUG_OFF _IOW(FIRMWARE_COMMON_TYPE, 4, int) /* debug off */ + +/* firmware cpld driver ioctl command, the same as "firmware_driver\firmware_driver\include\firmware.h" */ +#define FIRMWARE_TYPE 'J' +#define FIRMWARE_PROGRAM _IOW(FIRMWARE_TYPE, 1, char) /* firmware upgrade ISC */ +#define FIRMWARE_READ_CHIP _IOR(FIRMWARE_TYPE, 5, int) /* read the contents of the chip */ +#define FIRMWARE_PROGRAM_JBI _IOW(FIRMWARE_TYPE, 6, char) /* firmware upgrade JBI */ + +/* firmware cpld ispvme driver ioctl command, the same as "firmware_driver\firmware_driver_ispvme\include\firmware_ispvme.h" */ +#define FIRMWARE_VME_TYPE 'V' +#define FIRMWARE_JTAG_TDI _IOR(FIRMWARE_VME_TYPE, 0, char) +#define FIRMWARE_JTAG_TDO _IOR(FIRMWARE_VME_TYPE, 1, char) +#define FIRMWARE_JTAG_TCK _IOR(FIRMWARE_VME_TYPE, 2, char) +#define FIRMWARE_JTAG_TMS _IOR(FIRMWARE_VME_TYPE, 3, char) +#define FIRMWARE_JTAG_EN _IOR(FIRMWARE_VME_TYPE, 4, char) +#define FIRMWARE_JTAG_INIT _IOR(FIRMWARE_VME_TYPE, 7, char) /* enable upgrade access */ +#define FIRMWARE_JTAG_FINISH _IOR(FIRMWARE_VME_TYPE, 8, char) /* disable upgrade access */ + +/* firmware sysfs driver ioctl command, the same as "firmware_driver\firmware_driver_sysfs\include\firmware_sysfs.h" */ +#define FIRMWARE_SYSFS_TYPE 'S' +#define FIRMWARE_SYSFS_INIT _IOR(FIRMWARE_SYSFS_TYPE, 0, char) /* enable upgrade access */ +#define FIRMWARE_SYSFS_FINISH _IOR(FIRMWARE_SYSFS_TYPE, 1, char) /* disable upgrade access */ +#define FIRMWARE_SYSFS_SPI_INFO _IOR(FIRMWARE_SYSFS_TYPE, 2, char) /* spi flash upgrade */ +#define FIRMWARE_SYSFS_DEV_FILE_INFO _IOR(FIRMWARE_SYSFS_TYPE, 3, char) /* sysfs upgrade */ +#define FIRMWARE_SYSFS_MTD_INFO _IOR(FIRMWARE_SYSFS_TYPE, 4, char) /* sysfs mtd upgrade */ + +/* VME file, used to distinguish the JTAG signal that needs to operate */ +#define JTAG_TDO 1 +#define JTAG_TCK 2 +#define JTAG_TDI 3 +#define JTAG_TMS 4 +#define JTAG_ENABLE 5 +#define JTAG_TRST 6 + +typedef struct name_info_s { + int card_type[MAX_DEV_NUM]; /* main board type */ + int sub_type[MAX_DEV_NUM]; /* sub board type */ + int type; /* device type */ + int chain; /* chain num */ + char chip_name[FIRMWARE_NAME_LEN]; /* chip name */ + char version[FIRMWARE_NAME_LEN]; /* version */ + int file_type; /* file type */ + unsigned int crc32; /* 4 byte CRC values */ +} name_info_t; + +typedef struct cmd_info_s { + uint32_t size; + void *data; +} cmd_info_t; + +enum firmware_type_s { + FIRMWARE_UNDEF_TYPE = 0, + FIRMWARE_CPLD, + FIRMWARE_FPGA, + FIRMWARE_SYSFS, + FIRMWARE_OTHER, +}; + +typedef enum firmware_file_type_s { + FIRMWARE_UNDEF_FILE_TYPE = 0, + FIRMWARE_VME, /* ispvme cpld, GPIO simulates JTAG */ + FIRMWARE_ISC, /* cpld, GPIO simulates JTAG */ + FIRMWARE_JBI, + FIRMWARE_SPI_LOGIC_DEV, /* FPGA SPI upgrde register upgrade flash */ + FIRMWARE_SYSFS_DEV, /* write file upgrade eeprom */ + FIRMWARE_MTD, /* upgrade mtd device */ + FIRMWARE_NONE, +} firmware_file_type_t; + +typedef struct firmware_file_name_s { + char firmware_file_name_str[MAX_HEADER_KV_SIZE]; + int firmware_file_type; +} firmware_file_name_t; + +extern int header_offset; + +/* CRC32 calculation */ +extern unsigned long crc32(unsigned long crc, const unsigned char *buf, unsigned int len); +/* VME file upgrade */ +extern int firmware_upgrade_ispvme(int file_fd, char *upgrade_file_name, name_info_t *info); +extern void writePort(unsigned char a_ucPins, unsigned char a_ucValue); +extern unsigned char readPort(); +extern void sclock(); +extern void ispVMStateMachine(signed char NextState); + +/* spi flash upgrade */ +extern int firmware_upgrade_spi_logic_dev(int fd, uint8_t *buf, uint32_t size, name_info_t *info); +/* spi flash upgrade test*/ +extern int firmware_upgrade_spi_logic_dev_test(int fd, name_info_t *info); +/* spi flash data print*/ +extern int firmware_upgrade_spi_logic_dev_dump(char *dev_name, uint32_t offset, uint32_t size, char *record_file); + +/* sysfs upgrade */ +extern int firmware_upgrade_sysfs(int fd, uint8_t *buf, uint32_t size, name_info_t *info); +/* sysfs upgrade test*/ +extern int firmware_upgrade_sysfs_test(int fd, name_info_t *info); + +/* isc upgrade */ +extern int firmware_upgrade_jtag(int fd, uint8_t *buf, uint32_t size, name_info_t *info); +/* isc upgrade test */ +extern int firmware_upgrade_jtag_test(int fd, uint8_t *buf, uint32_t size, name_info_t *info); + +/* mtd upgrade */ +extern int firmware_upgrade_mtd(int fd, uint8_t *buf, uint32_t size, name_info_t *info); +/* mtd upgrade test */ +extern int firmware_upgrade_mtd_test(int fd, name_info_t *info); + +#endif /* End of __FIRMWARE_APP_H__ */ diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/include/vmopcode.h b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/include/vmopcode.h new file mode 100644 index 000000000000..ae9d713ff86c --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/firmware_upgrade/firmware_upgrade/include/vmopcode.h @@ -0,0 +1,192 @@ +/*************************************************************** +* +* This is the include file for Lattice Semiconductor's ispVM +* Embedded software application. +* +***************************************************************/ + +/*************************************************************** +* +* VME version. +* +* History: +* +***************************************************************/ + +#define VME_VERSION_NUMBER "12.2" + +/*************************************************************** +* +* Maximum declarations. +* +***************************************************************/ + +#define VMEHEXMAX 60000L /* The hex file is split 60K per file. */ +#define SCANMAX 64000L /* The maximum SDR/SIR burst. */ + +/*************************************************************** +* +* Supported JTAG state transitions. +* +***************************************************************/ + +#define RESET 0x00 +#define IDLE 0x01 +#define IRPAUSE 0x02 +#define DRPAUSE 0x03 +#define SHIFTIR 0x04 +#define SHIFTDR 0x05 +#define DRCAPTURE 0x06 + +/*************************************************************** +* +* Flow control register bit definitions. A set bit indicates +* that the register currently exhibits the corresponding mode. +* +***************************************************************/ + +#define INTEL_PRGM 0x0001 /* Intelligent programming is in effect. */ +#define CASCADE 0x0002 /* Currently splitting large SDR. */ +#define REPEATLOOP 0x0008 /* Currently executing a repeat loop. */ +#define SHIFTRIGHT 0x0080 /* The next data stream needs a right shift. */ +#define SHIFTLEFT 0x0100 /* The next data stream needs a left shift. */ +#define VERIFYUES 0x0200 /* Continue if fail is in effect. */ + +/*************************************************************** +* +* DataType register bit definitions. A set bit indicates +* that the register currently holds the corresponding type of data. +* +***************************************************************/ + +#define EXPRESS 0x0001 /* Simultaneous program and verify. */ +#define SIR_DATA 0x0002 /* SIR is the active SVF command. */ +#define SDR_DATA 0x0004 /* SDR is the active SVF command. */ +#define COMPRESS 0x0008 /* Data is compressed. */ +#define TDI_DATA 0x0010 /* TDI data is present. */ +#define TDO_DATA 0x0020 /* TDO data is present. */ +#define MASK_DATA 0x0040 /* MASK data is present. */ +#define HEAP_IN 0x0080 /* Data is from the heap. */ +#define LHEAP_IN 0x0200 /* Data is from intel data buffer. */ +#define VARIABLE 0x0400 /* Data is from a declared variable. */ +#define CRC_DATA 0x0800 /* CRC data is pressent. */ +#define CMASK_DATA 0x1000 /* CMASK data is pressent. */ +#define RMASK_DATA 0x2000 /* RMASK data is pressent. */ +#define READ_DATA 0x4000 /* READ data is pressent. */ +#define DMASK_DATA 0x8000 /* DMASK data is pressent. */ + +/*************************************************************** +* +* Pin opcodes. +* +***************************************************************/ + +#define signalENABLE 0x1C /* ispENABLE pin. */ +#define signalTMS 0x1D /* TMS pin. */ +#define signalTCK 0x1E /* TCK pin. */ +#define signalTDI 0x1F /* TDI pin. */ +#define signalTRST 0x20 /* TRST pin. */ + +/*************************************************************** +* +* Supported vendors. +* +***************************************************************/ + +#define VENDOR 0x56 +#define LATTICE 0x01 +#define ALTERA 0x02 +#define XILINX 0x03 + +/*************************************************************** +* +* Opcode definitions. +* +* Note: opcodes must be unique. +* +***************************************************************/ + +#define ENDDATA 0x00 /* The end of the current SDR data stream. */ +#define RUNTEST 0x01 /* The duration to stay at the stable state. */ +#define ENDDR 0x02 /* The stable state after SDR. */ +#define ENDIR 0x03 /* The stable state after SIR. */ +#define ENDSTATE 0x04 /* The stable state after RUNTEST. */ +#define TRST 0x05 /* Assert the TRST pin. */ +#define HIR 0x06 /* The sum of the IR bits of the leading devices. */ +#define TIR 0x07 /* The sum of the IR bits of the trailing devices. */ +#define HDR 0x08 /* The number of leading devices. */ +#define TDR 0x09 /* The number of trailing devices. */ +#define ispEN 0x0A /* Assert the ispEN pin. */ +#define FREQUENCY 0x0B /* The maximum clock rate to run the JTAG state machine. */ +#define STATE 0x10 /* Move to the next stable state. */ +#define SIR 0x11 /* The instruction stream follows. */ +#define SDR 0x12 /* The data stream follows. */ +#define TDI 0x13 /* The following data stream feeds into the device. */ +#define TDO 0x14 /* The following data stream is compared against the device. */ +#define MASK 0x15 /* The following data stream is used as mask. */ +#define XSDR 0x16 /* The following data stream is for simultaneous program and verify. */ +#define XTDI 0x17 /* The following data stream is for shift in only. It must be stored for the next XSDR. */ +#define XTDO 0x18 /* There is not data stream. The data stream was stored from the previous XTDI. */ +#define MEM 0x19 /* The maximum memory needed to allocate in order hold one row of data. */ +#define WAIT 0x1A /* The duration of delay to observe. */ +#define TCK 0x1B /* The number of TCK pulses. */ +#define SHR 0x23 /* Set the flow control register for right shift. */ +#define SHL 0x24 /* Set the flow control register for left shift. */ +#define HEAP 0x32 /* The memory size needed to hold one loop. */ +#define REPEAT 0x33 /* The beginning of the loop. */ +#define LEFTPAREN 0x35 /* The beginning of data following the loop. */ +#define VAR 0x55 /* Plac holder for loop data. */ +#define SEC 0x1C /* The delay time in seconds that must be observed. */ +#define SMASK 0x1D /* The mask for TDI data. */ +#define MAX 0x1E /* The absolute maximum wait time. */ +#define ON 0x1F /* Assert the targeted pin. */ +#define OFF 0x20 /* Dis-assert the targeted pin. */ +#define SETFLOW 0x30 /* Change the flow control register. */ +#define RESETFLOW 0x31 /* Clear the flow control register. */ +#define CRC 0x47 /* The following data stream is used for CRC calculation. */ +#define CMASK 0x48 /* The following data stream is used as mask for CRC calculation. */ +#define RMASK 0x49 /* The following data stream is used as mask for read and save. */ +#define READ 0x50 /* The following data stream is used for read and save. */ +#define ENDLOOP 0x59 /* The end of the repeat loop. */ +#define SECUREHEAP 0x60 /* Used to secure the HEAP opcode. */ +#define VUES 0x61 /* Support continue if fail. */ +#define DMASK 0x62 /* The following data stream is used for dynamic I/O. */ +#define COMMENT 0x63 /* Support SVF comments in the VME file. */ +#define HEADER 0x64 /* Support header in VME file. */ +#define FILE_CRC 0x65 /* Support crc-protected VME file. */ +#define LCOUNT 0x66 /* Support intelligent programming. */ +#define LDELAY 0x67 /* Support intelligent programming. */ +#define LSDR 0x68 /* Support intelligent programming. */ +#define LHEAP 0x69 /* Memory needed to hold intelligent data buffer */ +#define CONTINUE 0x70 /* Allow continuation. */ +#define LVDS 0x71 /* Support LVDS. */ +#define ENDVME 0x7F /* End of the VME file. */ +#define HIGH 0x80 /* Assert the targeted pin. */ +#define LOW 0x81 /* Dis-assert the targeted pin. */ +#define ENDFILE 0xFF /* End of file. */ + +/*************************************************************** +* +* ispVM Embedded Return Codes. +* +***************************************************************/ + +#define VME_VERIFICATION_FAILURE -1 +#define VME_FILE_READ_FAILURE -2 +#define VME_VERSION_FAILURE -3 +#define VME_INVALID_FILE -4 +#define VME_ARGUMENT_FAILURE -5 +#define VME_CRC_FAILURE -6 + +/*************************************************************** +* +* Type definitions. +* +***************************************************************/ + +/* Support LVDS */ +typedef struct { + unsigned short usPositiveIndex; + unsigned short usNegativeIndex; + unsigned char ucUpdate; +} LVDSPair; diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/fw_upgrade/Makefile b/platform/broadcom/sonic-platform-modules-ragile/common/app/fw_upgrade/Makefile new file mode 100644 index 000000000000..1701b5f62114 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/fw_upgrade/Makefile @@ -0,0 +1,18 @@ +top_srcdir:=$(shell pwd) +include $(top_srcdir)/Rules.mk + +firmware-y:= +firmware-y += fw_upgrade + +.PHONY: all +all: build + +.PHONY: build +build: $(firmware-y) +$(foreach dir,$(firmware-y),$(eval $(call compile_dirs,$(dir)))) + +.PHONY: rpmpkg +rpmpkg: +ifeq ("$(CONFIG_CPLD_UPGRADE_ISPVME)", "y") + #$(RPMPKG) $(install_cpld_dir) firmware-cpld-ispvme.spec git +endif diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/fw_upgrade/Rules.mk b/platform/broadcom/sonic-platform-modules-ragile/common/app/fw_upgrade/Rules.mk new file mode 100644 index 000000000000..5fb5a09d34fd --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/fw_upgrade/Rules.mk @@ -0,0 +1,42 @@ +CC ?= $(CROSS)gcc +AR ?= $(CROSS)ar +AS ?= $(CROSS)as +LD ?= $(CROSS)ld +STRIP ?= $(CROSS)strip + +install_root:=${top_srcdir}/images + +install_header_dir:=${install_root}/header +install_adir:=$(install_root)/lib +install_symbol_dir:=$(install_root)/symbol +symbol_files:=$(shell find $(EXPORT_SYMBOL) -name 'Module.symvers') +# +# symbol_files += $(shell find $(install_symbol_dir) -name 'Module.symvers') +# KBUILD_EXTRA_SYMBOLS += $(symbol_files) +# export KBUILD_EXTRA_SYMBOLS + +# top root: install_rootfs_dir +install_rootfs_dir:=$(install_root)/rootfs + +install_sodir:=$(install_rootfs_dir)/$(INSTALL_SODIR) + +install_usr_bin_dir:=$(install_rootfs_dir)/usr/bin +install_sbin_dir:=$(install_rootfs_dir)/sbin +install_etc_dir:=$(install_rootfs_dir)/etc + +export INSTALL_MOD_PATH:=$(ROOT) + +BUILD_CFLAGS:=$(CFLAGS) -I$(install_header_dir) +BUILD_LDFLAGS:=$(LDFLAGS) -L/$(install_sodir) -L/$(install_adir) + +define compile_dirs +.PHONY: $(1) +$(1): + @echo;echo "building $(1)..." + @$(MAKE) -C ${1} +endef + +compile.c = $(CC) $(BUILD_CFLAGS) -d -c -o $@ $< +%.o: %.c + $(compile.c) + diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/fw_upgrade/fw_upgrade/Makefile b/platform/broadcom/sonic-platform-modules-ragile/common/app/fw_upgrade/fw_upgrade/Makefile new file mode 100644 index 000000000000..8b4bca739087 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/fw_upgrade/fw_upgrade/Makefile @@ -0,0 +1,39 @@ +include ../Rules.mk + +OBJ = fw_upgrade.o fw_upgrade_debug.o + +LIB += $(BUILD_CFALGS) $(BUILD_LDFLAGS) -lpthread +ifdef ENABLE_GCOV +ifeq ($(ENABLE_GCOV), y) +LIB += -fprofile-arcs +endif +endif # ENABLE_GCOV + +APP = fw_upgrade +BUILD_DIR = tmp +ELF_FILE = $(BUILD_DIR)/$(APP) +MAP_FILE = $(BUILD_DIR)/$(APP).map.sym +INCLUDE = -Iinclude +CFLAGS+=-Wall -W -g + +.PHONY: build +build:make-dir $(addprefix $(BUILD_DIR)/,$(OBJ)) + $(CC) -o $(ELF_FILE) $(addprefix $(BUILD_DIR)/,$(OBJ)) $(LINKFLAGS) $(LIB) + + cp -p $(ELF_FILE) $(common_out_put_dir) + +.PHONY: make-dir +make-dir: + @mkdir -p $(BUILD_DIR) + +$(BUILD_DIR)/%.o:%.c + $(CC) -c $(CFLAGS) $(INCLUDE) $< -o $@ + +.PHONY: install +install: + echo "fw_upgrade install success." + cp -p $(ELF_FILE) $(common_out_put_dir) + +.PHONY: clean +clean: + rm -rf $(BUILD_DIR) diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/fw_upgrade/fw_upgrade/fw_upgrade.c b/platform/broadcom/sonic-platform-modules-ragile/common/app/fw_upgrade/fw_upgrade/fw_upgrade.c new file mode 100644 index 000000000000..2045608d5c3b --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/fw_upgrade/fw_upgrade/fw_upgrade.c @@ -0,0 +1,1632 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "fw_upgrade.h" + +static flash_info_t flash_info[] = { + { + .flash_name = "M25L6433F", + .flash_size = M32, + .flash_type = SPI, + .page_size = BYTE_256, + .flash_id = MX25L6433F, + .block_size = STEP_64, + .full_erase = 1, + .erase_block_command = BLOCK_ERASE_64, + .page_program = COMMON_PAGE_PROGRAM, + }, + { + .flash_name = "S25FL512S", + .flash_size = M64, + .flash_type = SPI, + .page_size = BYTE_256, + .flash_id = S25FL512S, + .block_size = STEP_256, + .full_erase = 0, + .erase_block_command = BLOCK_ERASE_64, + .page_program = COMMON_PAGE_PROGRAM, + }, + { + .flash_name = "MX25l512", + .flash_size = M64, + .flash_type = SPI, + .page_size = BYTE_256, + .flash_id = MX25l512, + .block_size = STEP_64, + .full_erase = 1, + .erase_block_command = BLOCK_ERASE_64, + .page_program = COMMON_PAGE_PROGRAM, + }, + { + .flash_name = "STM25P64", + .flash_size = M12, + .flash_type = SPI, + .page_size = BYTE_256, + .flash_id = STM25P64, + .block_size = STEP_256, + .full_erase = 1, + .erase_block_command = BLOCK_ERASE_64, + .page_program = COMMON_PAGE_PROGRAM, + }, + { + .flash_name = "STM25P128", + .flash_size = M16, + .flash_type = SPI, + .page_size = BYTE_256, + .flash_id = STM25P128, + .block_size = STEP_256, + .full_erase = 1, + .erase_block_command = BLOCK_ERASE_64, + .page_program = COMMON_PAGE_PROGRAM, + }, + { + .flash_name = "N25Q256", + .flash_size = M16, + .flash_type = SPI, + .page_size = BYTE_256, + .flash_id = N25Q256, + .block_size = STEP_256, + .full_erase = 1, + .erase_block_command = BLOCK_ERASE_64, + .page_program = COMMON_PAGE_PROGRAM, + }, + { + .flash_name = "N25Q512", + .flash_size = M16, + .flash_type = SPI, + .page_size = BYTE_256, + .flash_id = N25Q512, + .block_size = STEP_256, + .full_erase = 1, + .erase_block_command = BLOCK_ERASE_64, + .page_program = COMMON_PAGE_PROGRAM, + }, + { + .flash_name = "W25X16", + .flash_size = M3, + .flash_type = SPI, + .page_size = BYTE_256, + .flash_id = W25X16, + .block_size = STEP_256, + .full_erase = 1, + .erase_block_command = BLOCK_ERASE_64, + .page_program = COMMON_PAGE_PROGRAM, + }, + { + .flash_name = "W25X64", + .flash_size = M12, + .flash_type = SPI, + .page_size = BYTE_256, + .flash_id = W25X64, + .block_size = STEP_256, + .full_erase = 1, + .erase_block_command = BLOCK_ERASE_64, + .page_program = COMMON_PAGE_PROGRAM, + }, + { + .flash_name = "W25Q64BV", + .flash_size = M12, + .flash_type = SPI, + .page_size = BYTE_256, + .flash_id = W25Q64BV, + .block_size = STEP_256, + .full_erase = 1, + .erase_block_command = BLOCK_ERASE_64, + .page_program = COMMON_PAGE_PROGRAM, + }, + { + .flash_name = "W25Q128BV", + .flash_size = M16, + .flash_type = SPI, + .page_size = BYTE_256, + .flash_id = W25Q128BV, + .block_size = STEP_256, + .full_erase = 1, + .erase_block_command = BLOCK_ERASE_64, + .page_program = COMMON_PAGE_PROGRAM, + }, + { + .flash_name = "W25Q256FV", + .flash_size = M16, + .flash_type = SPI, + .page_size = BYTE_256, + .flash_id = W25Q256FV, + .block_size = STEP_256, + .full_erase = 1, + .erase_block_command = BLOCK_ERASE_64, + .page_program = COMMON_PAGE_PROGRAM, + }, + { + .flash_name = "MX25L1605D", + .flash_size = M32, + .flash_type = SPI, + .page_size = BYTE_256, + .flash_id = MX25L1605D, + .block_size = STEP_256, + .full_erase = 1, + .erase_block_command = BLOCK_ERASE_64, + .page_program = COMMON_PAGE_PROGRAM, + }, + { + .flash_name = "MX25L12805D", + .flash_size = M32, + .flash_type = SPI, + .page_size = BYTE_256, + .flash_id = MX25L12805D, + .block_size = STEP_256, + .full_erase = 1, + .erase_block_command = BLOCK_ERASE_64, + .page_program = COMMON_PAGE_PROGRAM, + }, + { + .flash_name = "MX66L1G45G", + .flash_size = M128, + .flash_type = SPI, + .page_size = BYTE_256, + .flash_id = MX66L1G45G, + .block_size = STEP_256, + .full_erase = 1, + .erase_block_command = BLOCK_ERASE_64, + .page_program = COMMON_PAGE_PROGRAM, + }, + { + .flash_name = "GD25Q256", + .flash_size = M16, + .flash_type = SPI, + .page_size = BYTE_256, + .flash_id = GD25Q256, + .block_size = STEP_256, + .full_erase = 1, + .erase_block_command = BLOCK_ERASE_64, + .page_program = COMMON_PAGE_PROGRAM, + }, +}; + +static int debug_on; + +static void help(void) +{ + printf("------------------------------BMC Upgrade Tool--------------------------------\n"); + printf("Program Flash:\n"); + printf("\tfw_upgrade upgrade [file name] [chip select: 0 | 1 | 2] "); + printf("[erase type: full | block]\n"); + printf("\t[file name] if file is not located at /home/admin, path should be added\n"); + printf("\t[chip select] 0:master, 1:slave, 2:both\n"); + printf("\t[erase type] choose a way to erase chip, full erase would be faster\n"); + printf("Read BMC Reg:\n"); + printf("\tfw_upgrade rd [address] [length]\n"); + printf("\t[address(Hexadecimal)] register address of BMC\n"); + printf("\t[length(decimal)] length of read data, should be times of 4\n"); + + return; +} + +static int set_ioport_rw_access(void) +{ + + if ( iopl(3) < 0) { + printf("Can't get access to /dev/port \n"); + return -1; + } + + return 0; +} + +static int get_file_size(char *file_name) +{ + FILE * pFile; + int size; + + pFile = fopen(file_name,"rb"); + if (pFile == NULL) { + printf("Error opening file\n"); + return -1; + } + fseek (pFile, 0, SEEK_END); + size = ftell(pFile); + fclose (pFile); + return size; +} + +static uint8_t _read(uint16_t addr) +{ + return inb(addr); +} + +static void _write(uint16_t addr, uint8_t val) +{ + outb(val, addr); + + return; +} + +static void write_addr_port(uint8_t addr_val, uint16_t addr_port) +{ + _write(addr_port, addr_val); + + return; +} + +static void write_data_port(uint8_t val, uint16_t data_port) +{ + _write(data_port, val); + + return; +} + +static uint8_t read_data_port(uint16_t data_port) +{ + return _read(data_port); +} + +static void write_ilpc2ahb_addr(uint32_t addr) +{ + int i; + + for (i = 0; i < 4; i++) { + write_addr_port(SUPERIO_REG0 + i, LPC_ADDR_PORT); + write_data_port((addr >> (8 * (3 - i))) & MASK, LPC_DATA_PORT); + } + + return; +} + +static void write_ilpc2ahb_data(uint32_t data) +{ + int i; + + for (i = 0; i < 4; i++) { + write_addr_port(SUPERIO_REG4 + i, LPC_ADDR_PORT); + write_data_port((data >> (8 * (3 - i))) & MASK, LPC_DATA_PORT); + } + + return; +} + +static uint32_t read_ilpc2ahb_data(void) +{ + int i, tmp; + uint32_t res; + + res = 0; + for (i = 0; i < 4; i++) { + write_addr_port(SUPERIO_REG4 + i, LPC_ADDR_PORT); + tmp = read_data_port(LPC_DATA_PORT); + res |= (tmp << (8 * (3 - i))); + } + + return res; +} + +static void trigger_ilpc2ahb_read(void) +{ + write_addr_port(SUPERIO_FE, LPC_ADDR_PORT); + read_data_port(LPC_DATA_PORT); + + return; +} + +static void trigger_ilpc2ahb_write(void) +{ + write_addr_port(SUPERIO_FE, LPC_ADDR_PORT); + write_data_port(TOGGLE_WRITE, LPC_DATA_PORT); + + return; +} + +static uint32_t read_bmc_reg(uint32_t addr) +{ + uint32_t res; + + write_ilpc2ahb_addr(addr); + trigger_ilpc2ahb_read(); + res = read_ilpc2ahb_data(); + + return res; +} + +static void write_bmc_reg(uint32_t addr, uint32_t val) +{ + write_ilpc2ahb_addr(addr); + write_ilpc2ahb_data(val); + trigger_ilpc2ahb_write(); + + return; +} + +static uint32_t read_bmc_flash_data(void) +{ + uint32_t res; + + trigger_ilpc2ahb_read(); + res = read_ilpc2ahb_data(); + + return res; +} + +static void write_bmc_flash_data(uint32_t data) +{ + write_ilpc2ahb_data(data); + trigger_ilpc2ahb_write(); + + return; +} + +static void write_bmc_flash_addr(uint32_t addr) +{ + int i; + + for (i = 0; i < 4; i++) { + write_addr_port(SUPERIO_REG4 + i, LPC_ADDR_PORT); + write_data_port((addr >> (8 * i)) & MASK, LPC_DATA_PORT); + } + + trigger_ilpc2ahb_write(); + + return; +} + +static void enable_bytes(int byte) +{ + write_addr_port(SUPERIO_REG8, LPC_ADDR_PORT); + switch (byte) { + case BYTE1: + write_data_port(SUPERIO_A0 + BYTE1_VAL, LPC_DATA_PORT); + break; + case BYTE2: + write_data_port(SUPERIO_A0 + BYTE2_VAL, LPC_DATA_PORT); + break; + case BYTE4: + write_data_port(SUPERIO_A0 + BYTE4_VAL, LPC_DATA_PORT); + break; + default: + write_data_port(SUPERIO_A0 + BYTE_RESERVED, LPC_DATA_PORT); + break; + } + + return; +} + +static void pull_ce_down(flash_info_t* info) +{ + write_bmc_reg(info->ce_control_reg, USER_MODE_PULL_CE_DOWN); + + return; +} + +static void pull_ce_up(flash_info_t* info) +{ + write_bmc_reg(info->ce_control_reg, USER_MODE_PULL_CE_UP); + + return; +} + +static void send_cmd(uint32_t flash_base_addr, int cmd) +{ + write_ilpc2ahb_addr(flash_base_addr); + enable_bytes(1); + write_addr_port(SUPERIO_REG7, LPC_ADDR_PORT); + write_data_port(cmd & MASK, LPC_DATA_PORT); + trigger_ilpc2ahb_write(); + enable_bytes(4); + + return; +} + +static void send_cmd_to_flash(flash_info_t* info, int cmd) +{ + pull_ce_down(info); + send_cmd(info->flash_base_addr, cmd); + pull_ce_up(info); + + return; +} + +static void check_data_length(void) +{ + uint8_t tmp; + /* Data length check, 4 bytes */ + write_addr_port(SUPERIO_REG8, LPC_ADDR_PORT); + tmp = read_data_port(LPC_DATA_PORT); + if (tmp != SUPERIO_A2) { + write_data_port(SUPERIO_A2, LPC_DATA_PORT); + } + + return; +} + +static void enable_ilpc2ahb(void) +{ + /* Write 0xAA then write 0xA5 twice to enable super IO*/ + write_addr_port(DISABLE_LPC, LPC_ADDR_PORT); + write_addr_port(ENABLE_LPC, LPC_ADDR_PORT); + write_addr_port(ENABLE_LPC, LPC_ADDR_PORT); + + /* Enable iLPC2AHB */ + write_addr_port(SUPERIO_07, LPC_ADDR_PORT); + write_data_port(LPC_TO_AHB, LPC_DATA_PORT); + write_addr_port(SUPERIO_30, LPC_ADDR_PORT); + write_data_port(ENABLE_LPC_TO_AHB, LPC_DATA_PORT); + + /* Data length */ + check_data_length(); + + return; +} + +static void disable_ilpc2ahb(void) +{ + /* disable ilpc2ahb */ + write_addr_port(SUPERIO_30, LPC_ADDR_PORT); + write_data_port(DISABLE_LPC_TO_AHB, LPC_DATA_PORT); + /* disable super IO */ + write_addr_port(DISABLE_LPC, LPC_ADDR_PORT); + + return; +} + +/* Enable CPU */ +static void enable_cpu(void) +{ + /* unlock SCU register */ + write_bmc_reg(SCU_ADDR, UNLOCK_SCU_KEY); + /* enable ARM */ + write_bmc_reg(REBOOT_CPU_REGISTER, SET_BMC_CPU_BOOT); + /* lock SCU register */ + write_bmc_reg(SCU_ADDR, LOCK_SCU_KEY); + + return; +} + +/* diasble CPU */ +static void disable_cpu(void) +{ + uint32_t scu_hw_strap_val; + + /* unlock SCU register */ + write_bmc_reg(SCU_ADDR, UNLOCK_SCU_KEY); + /* disable ARM */ + scu_hw_strap_val = read_bmc_reg(HARDWARE_STRAP_REGISTER); + write_bmc_reg(HARDWARE_STRAP_REGISTER, scu_hw_strap_val |0x01); + /* lock SCU register */ + write_bmc_reg(SCU_ADDR, LOCK_SCU_KEY); + + return; +} + +static void enable_upgrade(void) +{ + + enable_ilpc2ahb(); + /* diasble CPU */ + disable_cpu(); + /* init CE control register */ + write_bmc_reg(CE0_CONTROL_REGISTER, 0); + write_bmc_reg(CE1_CONTROL_REGISTER, 0); + /* disable WDT2 */ + write_bmc_reg(WATCHDOG2_CONTROL, DISABLE_WATCHDOG); + + return; +} + +static void disable_upgrade(void) +{ + enable_cpu(); + dbg_print(debug_on, "DEBUG 0x%x\n", read_bmc_reg(HARDWARE_STRAP_REGISTER)); + disable_ilpc2ahb(); + + return; +} + +static void watchdog_status_debug(void) +{ + uint32_t watchdog_reg; + + /* Watchdog Control Register */ + watchdog_reg = read_bmc_reg(WATCHDOG2_CONTROL); + dbg_print(debug_on,"Watchdog Control Register: 0x%x\n", watchdog_reg); + dbg_print(debug_on,"Watchdog Enable Signal: 0x%x\n", watchdog_reg & BIT1); + dbg_print(debug_on,"Watchdog Reset SyS En: 0x%x\n", (watchdog_reg & BIT2) >> 1); + dbg_print(debug_on,"Watchdog Reset Mode: 0x%x\n", (watchdog_reg & (BIT6 | BIT7)) >> 5); + switch (watchdog_reg & (BIT6 | BIT7)) { + case SOC_SYS: + dbg_print(debug_on,"\tReset Mode En: SoC System\n"); + break; + case FULL_CHIP: + dbg_print(debug_on,"\tReset Mode En: Full Chip\n"); + break; + case ARM_CPU: + dbg_print(debug_on,"\tReset Mode En: ARM Cpu\n"); + break; + default: + break; + } + + /* Watchdog Timeout Status Register */ + watchdog_reg = read_bmc_reg(WATCHDOG2_TSR); + dbg_print(debug_on,"Watchdog Timeout Occur: 0x%x\n", watchdog_reg & BIT1); + dbg_print(debug_on,"Watchdog Boot from: CD%d\n", watchdog_reg & BIT2); + dbg_print(debug_on,"Watchdog Interrupt Occur: 0x%x\n", watchdog_reg & BIT3); + + return; +} + +/* CE Type Setting Register */ +static void ce_type_setting_debug(void) +{ + uint32_t fmc_reg; + + fmc_reg = read_bmc_reg(FMC_CE_TYPE_SETTING_REG); + if ((fmc_reg & CE0_SPI_TYPE) == SPI) { + dbg_print(debug_on,"CE0 Type Seeting: 0x%x, Type: SPI\n", fmc_reg & CE0_SPI_TYPE); + } else { + dbg_print(debug_on,"CE0 Type Seeting: 0x%x, Type: Unknown\n", fmc_reg & CE0_SPI_TYPE); + } + if (((fmc_reg & CE1_SPI_TYPE) >> BIT2) == SPI) { + dbg_print(debug_on,"CE1 Type Seeting: 0x%x, Type: SPI\n", (fmc_reg & CE1_SPI_TYPE) >> BIT2); + } else { + dbg_print(debug_on,"CE1 Type Seeting: 0x%x, Type: Unknown\n", (fmc_reg & CE1_SPI_TYPE) >> BIT2); + } + + return; +} +/* CE Control Register */ +static void ce_control_debug(void) +{ + uint32_t fmc_reg; + + fmc_reg = read_bmc_reg(CE_CONTROL_REGISTER); + dbg_print(debug_on,"CE0 Address Mode: 0x%x, Mode: %d Bytes\n", + fmc_reg & BIT1, (fmc_reg & BIT1) + 3); + dbg_print(debug_on,"CE1 Address Mode: 0x%x, Mode: %d Bytes\n", + (fmc_reg & BIT2) >> 1, ((fmc_reg & BIT2) >> 1) + 3); + + return; +} + +/* Interrupt Control & Status Register */ +static void irq_control_status_debug(void) +{ + uint32_t fmc_reg; + + fmc_reg = read_bmc_reg(INR_STATUS_CONTROL_REGISTER); + dbg_print(debug_on,"SPI Write Address Protected Interrupt EN: 0x%x\n", fmc_reg & BIT2); + dbg_print(debug_on,"SPI Command Abort Interrupt EN: 0x%x\n", fmc_reg & BIT3); + dbg_print(debug_on,"SPI Write Address Protected Status: 0x%x, Status: %s\n", + RIGHT_SHIFT_8(fmc_reg) & BIT2, (RIGHT_SHIFT_8(fmc_reg) & BIT2) == BIT2 ? "Occur" : "Normal"); + dbg_print(debug_on,"SPI Command Abort Status: 0x%x, Status: %s\n", + RIGHT_SHIFT_8(fmc_reg) & BIT3, (RIGHT_SHIFT_8(fmc_reg) & BIT3) == BIT3 ? "Occur" : "Normal"); + /*Clear Abnormal Status*/ + if ((RIGHT_SHIFT_8(fmc_reg) & BIT3) || (RIGHT_SHIFT_8(fmc_reg) & BIT2)) { + write_bmc_reg(INR_STATUS_CONTROL_REGISTER, CLEAR_INR_STATUS_CONTROL); + } + + return; +} + +/* Command Control Register */ +static void command_control_debug(void) +{ + uint32_t fmc_reg; + + fmc_reg = read_bmc_reg(COMMAND_CONTROL_REGISTER); + dbg_print(debug_on,"Data Byte Line 0: %s\n", ((fmc_reg & BIT4) != 0) ? "Disable" : "Enable"); + dbg_print(debug_on,"Data Byte Line 1: %s\n", ((fmc_reg & BIT3) != 0) ? "Disable" : "Enable"); + dbg_print(debug_on,"Data Byte Line 2: %s\n", ((fmc_reg & BIT2) != 0) ? "Disable" : "Enable"); + dbg_print(debug_on,"Data Byte Line 3: %s\n", ((fmc_reg & BIT1) != 0) ? "Disable" : "Enable"); + + dbg_print(debug_on,"Address Byte Line 0: %s\n", ((fmc_reg & BIT8) != 0) ? "Disable" : "Enable"); + dbg_print(debug_on,"Address Byte Line 1: %s\n", ((fmc_reg & BIT7) != 0) ? "Disable" : "Enable"); + dbg_print(debug_on,"Address Byte Line 2: %s\n", ((fmc_reg & BIT6) != 0) ? "Disable" : "Enable"); + dbg_print(debug_on,"Address Byte Line 3: %s\n", ((fmc_reg & BIT5) != 0) ? "Disable" : "Enable"); + + return; +} + +static void ce_control_reg_debug(void) +{ + uint32_t fmc_reg; + + /* CE0 Control Register */ + fmc_reg = read_bmc_reg(CE0_CONTROL_REGISTER); + switch (fmc_reg & (BIT1 | BIT2)){ + case NORMAL_READ: + dbg_print(debug_on,"CE0 Command Mode: Normal Read\n"); + break; + case READ_MODE: + dbg_print(debug_on,"CE0 Command Mode: Read Command\n"); + break; + case WRITE_MODE: + dbg_print(debug_on,"CE0 Command Mode: Write Command\n"); + break; + case USER_MODE: + dbg_print(debug_on,"CE0 Command Mode: User Mode\n"); + break; + default: + break; + } + switch((RIGHT_SHIFT_24(fmc_reg) & (BIT5 | BIT6 | BIT7))){ + case 0: + dbg_print(debug_on,"CE0 IO Mode: Single Mode\n"); + break; + case 2: + case 3: + dbg_print(debug_on,"CE0 IO Mode: Dual Mode\n"); + break; + default: + break; + } + + dbg_print(debug_on,"CE0 Inactive Pulse Width: %d HCLK\n", + DEFAULT_WIDTH - (RIGHT_SHIFT_24(fmc_reg) & (BIT1 | BIT2 | BIT3 | BIT4))); + dbg_print(debug_on,"CE0 Data Input Mode: %s Mode\n", (fmc_reg & BIT4) == 0 ? "Single" : "Dual"); + dbg_print(debug_on,"CE0 MSB | LSB: %s First\n", (fmc_reg & BIT6) == 0 ? "MSB" : "LSB"); + + /* CE1 Control Register */ + fmc_reg = read_bmc_reg(CE1_CONTROL_REGISTER); + switch (fmc_reg & (BIT1 | BIT2)){ + case NORMAL_READ: + dbg_print(debug_on,"CE1 Command Mode: Normal Read\n"); + break; + case READ_MODE: + dbg_print(debug_on,"CE1 Command Mode: Read Command\n"); + break; + case WRITE_MODE: + dbg_print(debug_on,"CE1 Command Mode: Write Command\n"); + break; + case USER_MODE: + dbg_print(debug_on,"CE1 Command Mode: User Mode\n"); + break; + default: + break; + } + switch((RIGHT_SHIFT_24(fmc_reg) & (BIT5 | BIT6 | BIT7))){ + case 0: + dbg_print(debug_on,"CE1 IO Mode: Single Mode\n"); + break; + case 2: + case 3: + dbg_print(debug_on,"CE1 IO Mode: Dual Mode\n"); + break; + default: + break; + } + + dbg_print(debug_on,"CE1 Inactive Pulse Width: %d HCLK\n", + DEFAULT_WIDTH - (RIGHT_SHIFT_24(fmc_reg) & (BIT1 | BIT2 | BIT3 | BIT4))); + dbg_print(debug_on,"CE1 Data Input Mode: %s Mode\n", (fmc_reg & BIT4) == 0 ? "Single" : "Dual"); + dbg_print(debug_on,"CE1 MSB | LSB: %s First\n", (fmc_reg & BIT6) == 0 ? "MSB" : "LSB"); + + return; +} + +static void fmc_debug(void) +{ + ce_type_setting_debug(); + ce_control_debug(); + irq_control_status_debug(); + command_control_debug(); + ce_control_reg_debug(); + + return; +} + +/* Enable WatchDog to reset BMC*/ +static void enable_watchdog(int cs) +{ + uint32_t enable_watch_cmd; + + enable_watch_cmd = (cs == CE0) ? ENABLE_WATCHDOG : ENABLE_WATCHDOG | BOOT_DEFAULT_MASK; + write_bmc_reg(WATCHDOG2_CLEAR_STATUS, CLEAR_WATCHDOG_STATUS); + write_bmc_reg(WATCHDOG2_RESET_FUN_MASK, WATCHDOG_GATEMASK); + write_bmc_reg(WATCHDOG2_RELOAD_VALUE, WATCHDOG_NEW_COUNT); + write_bmc_reg(WATCHDOG2_COUNTER_RST, WATCHDOG_RELOAD_COUNTER); + write_bmc_reg(WATCHDOG2_CONTROL, enable_watch_cmd); + + return; +} + +static void bmc_reboot(int cs) +{ + enable_watchdog(cs); + watchdog_status_debug(); + disable_upgrade(); + printf("Upgrade-Complete, BMC rebooting...\n"); + + return; +} + +static int get_current_bmc(void) +{ + return (read_bmc_reg(WATCHDOG2_TSR) & 0x02) >> 1; +} + +static void get_flash_base_and_ce_ctrl(int current_bmc, int cs, uint32_t *flash_base_addr, uint32_t *ce_ctrl_addr) +{ + uint32_t ce0_addr_range_reg_val, ce0_decode_addr; + uint32_t ce1_addr_range_reg_val, ce1_decode_addr; + + ce0_addr_range_reg_val = read_bmc_reg(CE0_ADDRESS_RANGE_REGISTER); + ce0_decode_addr = SEGMENT_ADDR_START(ce0_addr_range_reg_val); + ce1_addr_range_reg_val = read_bmc_reg(CE1_ADDRESS_RANGE_REGISTER); + ce1_decode_addr = SEGMENT_ADDR_START(ce1_addr_range_reg_val); + dbg_print(debug_on,"CE0 addr decode range reg value:0x%08x, decode addr:0x%08x.\n", + ce0_addr_range_reg_val, ce0_decode_addr); + dbg_print(debug_on,"CE1 addr decode range reg value:0x%08x, decode addr:0x%08x.\n", + ce1_addr_range_reg_val, ce1_decode_addr); + + if (((current_bmc == CURRENT_MASTER) && (cs ==CE0)) || ((current_bmc == CURRENT_SLAVE) && (cs ==CE1))) { + *ce_ctrl_addr = CE0_CONTROL_REGISTER; + *flash_base_addr = ce0_decode_addr; + } else { + *ce_ctrl_addr = CE1_CONTROL_REGISTER; + *flash_base_addr = ce1_decode_addr; + } + + return; +} + +static int get_flash_id(uint32_t flash_base_addr, uint32_t ce_ctrl_addr) +{ + uint32_t origin_flash_id, flash_id; + + write_bmc_reg(ce_ctrl_addr, USER_MODE_PULL_CE_DOWN); + send_cmd(flash_base_addr, READID); + origin_flash_id = read_bmc_flash_data(); + write_bmc_reg(ce_ctrl_addr, USER_MODE_PULL_CE_UP); + flash_id = origin_flash_id & 0xFFFFFF; + dbg_print(debug_on,"origin flash id:0x%x, flash id:0x%x\n", origin_flash_id, flash_id); + + return flash_id; +} + +static uint8_t get_flash_status(flash_info_t* info) +{ + uint8_t flash_status; + + pull_ce_down(info); + + send_cmd(info->flash_base_addr, READ_FLASH_STATUS); + + flash_status = read_bmc_flash_data() & MASK; + pull_ce_up(info); + + dbg_print(debug_on,"get_flash_status:0x%x\n", flash_status); + return flash_status; +} + +static int check_flash_write_enable(flash_info_t* info) +{ + uint8_t flash_status; + int i, count; + + count = FLASH_WEL_TIMEOUT / FLASH_WEL_SLEEP_TIME; + for (i = 0; i <= count; i++) { + flash_status = get_flash_status(info); + if ((flash_status & FLASH_WRITE_ENABLE_MASK) != FLASH_WRITE_ENABLE_MASK) { + usleep(FLASH_WEL_SLEEP_TIME); + } else { + dbg_print(debug_on,"Check flash WEL success, RDSR:0x%x\n", flash_status); + return 0; + } + } + printf("Check flash WEL timeout, RDSR:0x%x\n", flash_status); + return -1; +} + +static int check_flash_write_process(flash_info_t* info, int timeout, int sleep_time) +{ + int i, count; + uint8_t flash_status; + + count = timeout / sleep_time; + for (i = 0; i <= count; i++) { + flash_status = get_flash_status(info); + if ((flash_status & FLASH_WIP_MASK) != 0) { + usleep(sleep_time); + } else { + dbg_print(debug_on,"Check flash WIP success, RDSR:0x%x\n", flash_status); + return 0; + } + } + printf("Check flash WIP timeout, RDSR:0x%x.\n", flash_status); + return -1; +} + +static int flash_write_enable(flash_info_t* info) +{ + int ret; + + send_cmd_to_flash(info, WRITE_ENABLE_FLASH); + ret = check_flash_write_enable(info); + if (ret < 0) { + return -1; + } + return 0; +} + +static void send_block_erase_cmd(flash_info_t* info, uint32_t block_addr) +{ + pull_ce_down(info); + send_cmd(info->flash_base_addr, info->erase_block_command); + write_bmc_flash_addr(block_addr); /* Erase Block addr */ + pull_ce_up(info); + + return; +} + +static void send_chip_erase_cmd(flash_info_t* info) +{ + send_cmd_to_flash(info, CHIP_ERASE_FLASH); + + return; +} + +static int write_bmc_flash_page(flash_info_t* info, uint32_t page_addr, uint8_t *p, int len) +{ + int pos; + + if (len % 4) { + printf("Page size %d invalid.\n", len); + return -1; + } + + pos = 0; + pull_ce_down(info); + send_cmd(info->flash_base_addr, info->page_program); + write_bmc_flash_addr(page_addr); /* page address */ + while (len) { + write_bmc_flash_data((*(uint32_t *)(p + pos))); + pos += 4; + len -= 4; + } + pull_ce_up(info); + + return 0; +} + +static int erase_chip_full(flash_info_t* info) +{ + time_t timep; + int ret; + + if (info->full_erase == 0) { + printf("Flash not support full erase function.\n"); + return -1; + } + + ret = flash_write_enable(info); + if(ret < 0) { + printf("Chip erase, enable flash write error.\n"); + return -1; + } + + time(&timep); + printf("Full chip erasing, please wait...\n"); + dbg_print(debug_on,"Erase Start-%s\n",asctime(gmtime(&timep))); + send_chip_erase_cmd(info); + ret = check_flash_write_process(info, CHIP_ERASE_TIMEOUT, CHIP_ERASE_SLEEP_TIME); + if (ret < 0) { + printf("Chip erase timeout.\n"); + return -1; + } + time(&timep); + dbg_print(debug_on,"Erase Finish-%s\n",asctime(gmtime(&timep))); + printf("Erase Finish\n"); + printf("=========================================\n"); + return 0; +} + +static int erase_chip_block(flash_info_t* info) +{ + uint32_t block_addr, end_addr; + time_t timep; + int ret; + + printf("Block erasing...\n"); + time (&timep); + dbg_print(debug_on,"Erase-Start-%s\n", asctime(gmtime(&timep))); + end_addr = info->flash_base_addr + info->flash_size; + block_addr = info->flash_base_addr; + while (1) { + /* Enable write */ + ret = flash_write_enable(info); + if(ret < 0) { + printf("Block erase, enable flash write error, block addr:0x%x\n", block_addr); + return -1; + } + + send_block_erase_cmd(info, block_addr); + /* Erase Block(64KB) MAX time 650ms*/ + ret = check_flash_write_process(info, BLOCK_ERASE_TIMEOUT, BLOCK_ERASE_SLEEP_TIME); + if (ret < 0) { + printf("Block erase, check write status error, block addr:0x%x\n", block_addr); + return -1; + } + printf("\r0x%x", block_addr); + fflush(stdout); + if (block_addr >= end_addr) { + time(&timep); + printf("\r\nErase Finish\n"); + printf("=========================================\n"); + dbg_print(debug_on,"\nEnd-Earse-%s\n",asctime(gmtime(&timep))); + break; + } + block_addr += info->block_size; + } + return 0; +} + +static int program_chip(uint32_t file_size, uint8_t *p, flash_info_t* info) +{ + time_t timep; + uint32_t page_addr, end_addr; + int ret, page_size; + + page_addr = info->flash_base_addr; + page_size = info->page_size; + end_addr = file_size + info->flash_base_addr; + time (&timep); + printf("Programming...\n"); + dbg_print(debug_on,"Program Start-%s\n",asctime(gmtime(&timep))); + /* Debug info */ + fmc_debug(); + while (1) { + /* Write enable */ + ret = flash_write_enable(info); + if(ret < 0) { + printf("Page program, enable flash write error, page addr:0x%x\n", page_addr); + return -1; + } + ret = write_bmc_flash_page(info, page_addr, p, page_size); + if (ret < 0) { + printf("Page program, write bmc flash page error, page addr:0x%x\n", page_addr); + return -1; + } + /* page program MAX time 1.5ms */ + ret = check_flash_write_process(info, PAGE_PROGRAM_TIMEOUT, PAGE_PROGRAM_SLEEP_TIME); + if (ret < 0) { + printf("Page program, check write status error, page addr:0x%x\n", page_addr); + return -1; + } + page_addr += page_size; + p += page_size; + if ((page_addr % 0x10000) == 0) { + printf("\r0x%x", page_addr); + fflush(stdout); + } + + if (page_addr >= end_addr) { + printf("\nProgram Finish\n"); + printf("=========================================\n"); + time(&timep); + dbg_print(debug_on,"\nProgram-End-%s\n",asctime(gmtime(&timep))); + break; + } + } /* End of while (1) */ + return 0; +} + +static int check_chip(uint32_t file_size, uint8_t *p, flash_info_t* info) +{ + time_t timep; + uint32_t offset_addr, rd_val, end_addr; + int pos; + + offset_addr = info->flash_base_addr; + end_addr = file_size + info->flash_base_addr; + pos=0; + /* Checking */ + time(&timep); + printf("Checking...\n"); + dbg_print(debug_on,"Checking-Start-%s\n",asctime(gmtime(&timep))); + + pull_ce_down(info); + send_cmd(info->flash_base_addr, COMMON_FLASH_READ); + write_bmc_flash_addr(info->flash_base_addr); + while (1) { + if (offset_addr >= end_addr) { + break; + } + rd_val = read_bmc_flash_data(); + if (rd_val != (*(uint32_t *)(p + pos))) { + printf("Check Error at 0x%08x\n", offset_addr); + printf("READ:0x%08x VALUE:0x%08x\n", rd_val, (*(uint32_t *)(p + pos))); + pull_ce_up(info); + return -1; + } + if ((offset_addr % 0x10000) == 0) { + printf("\r0x%x ", offset_addr); + fflush(stdout); + } + offset_addr += 4; + pos += 4; + } + pull_ce_up(info); + printf("\r\nFlash Checked\n"); + printf("=========================================\n"); + time(&timep); + dbg_print(debug_on,"Checking-End-%s\n",asctime(gmtime(&timep))); + return 0; +} + +flash_info_t* get_flash_info(int current_bmc, int cs) +{ + int i, size; + uint32_t flash_base_addr, ce_ctrl_addr, flash_id; + + get_flash_base_and_ce_ctrl(current_bmc, cs, &flash_base_addr, &ce_ctrl_addr); + + size = (sizeof(flash_info) / sizeof((flash_info)[0])); + + flash_id = get_flash_id(flash_base_addr, ce_ctrl_addr); + for (i = 0; i < size; i++) { + if (flash_info[i].flash_id == flash_id) { + flash_info[i].flash_base_addr = flash_base_addr; + flash_info[i].ce_control_reg = ce_ctrl_addr; + flash_info[i].cs = cs; + return &flash_info[i]; + } + } + printf("Cannot get flash info, cs:%d, flash base addr:0x%x, ce control addr:0x%x, flash_id:0x%x.\n", + cs, flash_base_addr, ce_ctrl_addr, flash_id); + return NULL; +} + +static void init_flash(flash_info_t* info) +{ + send_cmd_to_flash(info, RSTEN); + send_cmd_to_flash(info, RST); + send_cmd_to_flash(info, EXIT_OTP); + send_cmd_to_flash(info, ENABLE_BYTE4); + + return; +} + +static int upgrade_bmc_core(char *file_name, int erase_type, flash_info_t* info) +{ + int file_size, fp, ret; + uint8_t *p; + + file_size = get_file_size(file_name); + if (file_size < 0) { + printf("file size %d Error\n", file_size); + return -1; + } + + fp = open(file_name, O_RDWR); + if (fp < 0) { + printf("Cannot open %s.\n", file_name); + return -1; + } + + p = mmap(NULL, file_size, PROT_READ, MAP_SHARED, fp, 0); + if (p == MAP_FAILED) { + printf("Could not mmap %s, error(%s).\n", file_name, strerror(errno)); + close(fp); + return -1; + } + + printf("* CE%d FLASH TYPE: SPI FLASH\n", info->cs); + printf("* FLASH NAME: %s\n", info->flash_name); + printf("* File Size:%d, 0x%x\n", file_size, file_size); + printf("=========================================\n"); + + /* Select erase type */ + switch (erase_type) { + case FULL_ERASE: + ret = erase_chip_full(info); + break; + case BLOCK_ERASE: + ret = erase_chip_block(info); + break; + default: + printf("Unsupport earse type:%d\n", erase_type); + goto exit; + break; + } + + if (ret < 0) { + printf("Erase Chip Error\n"); + goto exit; + } + + /* Program the flash */ + ret = program_chip(file_size, p, info); + if(ret < 0) { + printf("Program Chip Error\n"); + goto exit; + } + /* Check */ + ret = check_chip(file_size, p, info); + if(ret < 0) { + printf("Check Chip Error\n"); + goto exit; + } + + munmap(p, file_size); + close(fp); + return 0; +exit: + munmap(p, file_size); + close(fp); + return -1; +} + +static int upgrade_bmc_flash(char *filename, int current_bmc, int cs, int erase_type) +{ + int ret; + flash_info_t* info; + + info = get_flash_info(current_bmc, cs); + if(info == NULL) { + return -1; + } + + init_flash(info); + + ret = upgrade_bmc_core(filename, erase_type, info); + + return ret; +} + +static int upgrade_both_flash(char *filename, int erase_type) +{ + int ret, current_bmc; + + enable_upgrade(); + + current_bmc = get_current_bmc(); + if (current_bmc == CURRENT_MASTER) { + printf("* Current Bmc Default Boot: CE0\n"); + } else { + printf("* Current Bmc Default Boot: CE1\n"); + } + + ret = upgrade_bmc_flash(filename, current_bmc, CE0, erase_type); + if (ret < 0) { + printf("Upgrade master bmc flash failed, stop upgrade.\n"); + goto err; + } + printf("Upgrade master bmc flash success.\n"); + + ret = upgrade_bmc_flash(filename, current_bmc, CE1, erase_type); + if (ret < 0) { + printf("Upgrade slave bmc flash failed.\n"); + goto err; + } + printf("Upgrade slave bmc flash success.\n"); + + bmc_reboot(CE0); + return 0; +err: + disable_upgrade(); + return -1; +} + +static int upgrade_single_flash(char *filename, int cs, int erase_type) +{ + int ret, current_bmc; + + enable_upgrade(); + + current_bmc = get_current_bmc(); + if (current_bmc == CURRENT_MASTER) { + printf("* Current Bmc Default Boot: CE0\n"); + } else { + printf("* Current Bmc Default Boot: CE1\n"); + } + + ret = upgrade_bmc_flash(filename, current_bmc, cs, erase_type); + if (ret < 0) { + printf("Upgrade %s bmc flash failed.\n", cs == 0 ? "master":"slave"); + goto err; + } + printf("Upgrade %s bmc flash success.\n", cs == 0 ? "master":"slave"); + + bmc_reboot(cs); + return 0; +err: + disable_upgrade(); + return -1; +} + +static int upgrade_bmc(char *filename, int cs, int erase_type) +{ + int ret; + + if (access(filename, F_OK) < 0) { + printf("Can't find file\n"); + help(); + return -1; + } + + ret = set_ioport_rw_access(); + if (ret < 0) { + printf("IO ERROR\n"); + return -1; + } + + switch(cs) { + /* Single */ + case CE0: + case CE1: + ret = upgrade_single_flash(filename, cs, erase_type); + break; + /* Both */ + case BOTHFLASH: + ret = upgrade_both_flash(filename, erase_type); + break; + default: + ret = -1; + printf("Unsupport cs:%d\n", cs); + break; + } + + return ret; +} + +static int read_single_bmc_flash(flash_info_t* info, uint32_t start_addr, int read_size, int is_print) +{ + uint32_t res, flash_start_addr, flash_end_addr; + char filename[MAX_FILENAME_LENGTH]; + int fd, ret; + + flash_start_addr = info->flash_base_addr + start_addr; + flash_end_addr = flash_start_addr + read_size; + ret = 0; + fd = 0; + if (!is_print) { + mem_clear(filename, MAX_FILENAME_LENGTH); + snprintf(filename, MAX_FILENAME_LENGTH, "/tmp/image-bmc%d", info->cs); + fd = open(filename, O_RDWR | O_CREAT | O_TRUNC, S_IRWXG|S_IRWXU|S_IRWXO); + if (fd < 0) { + printf("open file %s fail(err:%d)!\r\n", filename, errno); + return -1; + } + } + + printf("* CE%d FLASH TYPE: SPI FLASH\n", info->cs); + printf("* FLASH NAME: %s\n", info->flash_name); + printf("* Read flash addr:0x%x, size:0x%x\n", flash_start_addr, read_size); + printf("=========================================\n"); + printf("Reading...\n"); + + pull_ce_down(info); + send_cmd(info->flash_base_addr, COMMON_FLASH_READ); + write_bmc_flash_addr(flash_start_addr); + while (1) { + if (flash_start_addr >= flash_end_addr) { + break; + } + res = read_bmc_flash_data(); + if (is_print) { + printf("addr:0x%08x, val:0x%08x\n", flash_start_addr, res); + } else { + ret = write(fd, &res, sizeof(res)); + if (ret < 0) { + printf("write failed (errno: %d).\n", errno); + ret = -1; + goto exit; + } + } + if (((flash_start_addr % 0x10000) == 0) && (!is_print)) { + printf("\r0x%x ", flash_start_addr); + fflush(stdout); + } + flash_start_addr += 4; + } + printf("\r\nRead Finish\n"); + printf("=========================================\n"); +exit: + pull_ce_up(info); + if (fd > 0) { + close(fd); + } + return ret; +} + +static int read_bmc_flash(int cs, uint32_t start_addr, int read_size, int is_print) +{ + int ret, current_bmc; + flash_info_t* info; + + ret = set_ioport_rw_access(); + if (ret < 0) { + printf("IO ERROR\n"); + return -1; + } + + enable_upgrade(); + + current_bmc = get_current_bmc(); + if (current_bmc == CURRENT_MASTER) { + printf("* Current Bmc Default Boot: CE0\n"); + } else { + printf("* Current Bmc Default Boot: CE1\n"); + } + + info = get_flash_info(current_bmc, cs); + if(info == NULL) { + goto err; + } + + if (start_addr >= info->flash_size) { + printf("start_addr 0x%x out of range.\n", start_addr); + goto err; + } + + if ((start_addr + read_size) > info->flash_size) { + printf("read size %d exceed flash size.\n", read_size); + read_size = info->flash_size - start_addr; + } + + init_flash(info); + + ret = read_single_bmc_flash(info, start_addr, read_size, is_print); + if (ret < 0) { + printf("Read %s bmc flash failed.\n", cs == 0 ? "master" : "slave"); + goto err; + } + disable_upgrade(); + return 0; +err: + disable_upgrade(); + return -1; +} + +static int read_bmc_reg_main(int argc, char* argv[]) +{ + uint32_t start_addr, read_val; + int read_size, ret; + char *stopstring; + + if (argc != 4) { + printf("Input invalid.\n"); + help(); + return -1; + } + + start_addr = strtoul(argv[2], &stopstring, 16); + read_size = strtol(argv[3], &stopstring, 10); + + if (read_size <= 0) { + printf("read length %d invalid\n", read_size); + return -1; + } + + if (((start_addr % 4) != 0) || ((read_size % 4) != 0)) { + printf("Params invalid, start_addr:0x%08x, read_size:%d\n", start_addr, read_size); + printf("Please input address/length times of 4\n"); + return -1; + } + + ret = set_ioport_rw_access(); + if (ret < 0) { + printf("IO ERROR\n"); + return -1; + } + + enable_ilpc2ahb(); + + printf("read bcm reg, start_addr:0x%08x, read length:%d\n", start_addr, read_size); + printf("===Addr=== | ===Cont===\n"); + while (read_size) { + read_val = read_bmc_reg(start_addr); + printf("0x%08x | 0x%08x\n", start_addr, read_val); + start_addr += 4; + read_size -= 4; + } + + disable_ilpc2ahb(); + return 0; +} + +static int write_bmc_reg_main(int argc, char* argv[]) +{ + uint32_t addr, wr_val; + int ret; + char *stopstring; + + if (argc != 4) { + printf("Input invalid.\n"); + help(); + return -1; + } + + addr = strtoul(argv[2], &stopstring, 16); + wr_val = strtoul(argv[3], &stopstring, 16); + + if (((addr & MASK_BYTE) != REGISTER_HEAD) || ((addr % 4) != 0)) { + printf("Address[0x%08x] invalid, address should be register address and times of 4.\n", addr); + return -1; + } + + ret = set_ioport_rw_access(); + if (ret < 0) { + printf("IO ERROR\n"); + return -1; + } + + printf("write bcm reg, addr:0x%08x, val:0x%08x\n", addr, wr_val); + + enable_ilpc2ahb(); + write_bmc_reg(addr, wr_val); + disable_ilpc2ahb(); + + return 0; +} + +static int get_fmc_info_main(void) +{ + int ret; + + ret = set_ioport_rw_access(); + if (ret < 0) { + printf("IO ERROR\n"); + return -1; + } + + enable_ilpc2ahb(); + + debug_on = 3; + fmc_debug(); + debug_on = 0; + + disable_ilpc2ahb(); + return 0; +} + +static int program_flash_main(int argc, char* argv[]) +{ + int cs, erase_way, ret; + char *stopstring; + char tmp[128]; + + if (argc != 5) { + printf("Input invalid.\n"); + help(); + return -1; + } + + cs = strtol(argv[3], &stopstring, 10); + if ((strlen(stopstring) != 0) || cs < 0 || cs > 2) { + snprintf(tmp, sizeof(tmp), "%s", argv[3]); + printf("Incorrect chip select %s\n", tmp); + help(); + return -1; + } + + if (strcmp(argv[4], "full") == 0) { + erase_way = FULL_ERASE; + } else if (strcmp(argv[4], "block") == 0) { + erase_way = BLOCK_ERASE; + } else { + snprintf(tmp, sizeof(tmp), "%s", argv[4]); + printf("Incorrect erase type %s\n", tmp); + help(); + return -1; + } + + printf("============BMC Upgrade Tool=============\n"); + ret = upgrade_bmc(argv[2], cs, erase_way); + return ret; +} + +static int read_bmc_flash_main(int argc, char* argv[]) +{ + int cs, ret, read_size, is_print; + uint32_t start_addr; + char *stopstring; + char tmp[128]; + + if (argc != 6) { + printf("Input invalid.\n"); + help(); + return -1; + } + + cs = strtol(argv[2], &stopstring, 10); + if ((strlen(stopstring) != 0) || cs < 0 || cs > 1) { + snprintf(tmp, sizeof(tmp), "%s", argv[2]); + printf("Incorrect chip select %s\n", tmp); + help(); + return -1; + } + + start_addr = strtoul(argv[3], &stopstring, 16); + read_size = strtol(argv[4], &stopstring, 10); + + if (read_size <= 0) { + printf("read length %d invalid\n", read_size); + return -1; + } + + if (((start_addr % 4) != 0) || ((read_size % 4) != 0)) { + printf("Params invalid, start_addr:0x%08x, read_size:%d\n", start_addr, read_size); + printf("Please input address/length times of 4\n"); + return -1; + } + + if (strcmp(argv[5], "print") == 0) { + is_print = 1; + } else { + is_print = 0; + } + + printf("============READ BMC FLASH=============\n"); + ret = read_bmc_flash(cs, start_addr, read_size, is_print); + return ret; +} + +int main(int argc, char *argv[]) +{ + int ret; + + debug_on = fw_upgrade_debug(); + + if (argc < 2) { + help(); + return -1; + } + + if (argc == 2) { + if (strcmp(argv[1], "-h") == 0 || strcmp(argv[1], "--help") == 0) { + help(); + return 0; + } + } + + if (strcmp(argv[1], "rd") == 0) { + ret = read_bmc_reg_main(argc, argv); + if (ret < 0) { + printf("Read Failed\n"); + } + return ret; + } + + if (strcmp(argv[1], "wr") == 0 && debug_on == 3) { + ret = write_bmc_reg_main(argc, argv); + if (ret < 0) { + printf("Write Failed\n"); + } + return ret; + } + + if (strcmp(argv[1], "info") == 0) { + ret = get_fmc_info_main(); + if (ret < 0) { + printf("Get fmc info Failed\n"); + } + return ret; + } + + if (strcmp(argv[1], "upgrade") == 0) { + ret = program_flash_main(argc, argv); + if (ret < 0) { + printf("Upgrade BMC failed.\n"); + } + return ret; + } + + if (strcmp(argv[1], "read_bmc_flash") == 0) { + ret = read_bmc_flash_main(argc, argv); + if (ret < 0) { + printf("Read BMC flash failed.\n"); + } + return ret; + } + + printf("Input invalid.\n"); + help(); + + return -1; +} diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/fw_upgrade/fw_upgrade/fw_upgrade_debug.c b/platform/broadcom/sonic-platform-modules-ragile/common/app/fw_upgrade/fw_upgrade/fw_upgrade_debug.c new file mode 100644 index 000000000000..a7a78d011011 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/fw_upgrade/fw_upgrade/fw_upgrade_debug.c @@ -0,0 +1,51 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include "fw_upgrade_debug.h" + +int fw_upgrade_debug(void) +{ + int size; + FILE *fp; + char debug_info[DEBUG_INFO_LEN]; + + fp = fopen(DEBUG_FILE, "r"); + if (fp == NULL) { + return DEBUG_IGNORE; + } + + mem_clear(debug_info, DEBUG_INFO_LEN); + size = fread(debug_info, DEBUG_INFO_LEN - 1, 1, fp); + if (size < 0) { + fclose(fp); + return DEBUG_IGNORE; + } + + if (strncmp(debug_info, DEBUG_ON_INFO, 1) == 0) { + fclose(fp); + return DEBUG_APP_ON; + } + + if (strncmp(debug_info, DEBUG_ON_KERN, 1) == 0) { + fclose(fp); + return DEBUG_KERN_ON; + } + + if (strncmp(debug_info, DEBUG_ON_ALL, 1) == 0) { + fclose(fp); + return DEBUG_ALL_ON; + } + + if (strncmp(debug_info, DEBUG_OFF_INFO, 1) == 0) { + fclose(fp); + return DEBUG_OFF; + } + + fclose(fp); + return DEBUG_IGNORE; +} diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/fw_upgrade/fw_upgrade/include/fw_upgrade.h b/platform/broadcom/sonic-platform-modules-ragile/common/app/fw_upgrade/fw_upgrade/include/fw_upgrade.h new file mode 100644 index 000000000000..bd806a94b154 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/fw_upgrade/fw_upgrade/include/fw_upgrade.h @@ -0,0 +1,230 @@ +#ifndef _FW_UPGRADE_H_ +#define _FW_UPGRADE_H_ + +#include "fw_upgrade_debug.h" + +#define dbg_print(debug, fmt, arg...) \ + if (debug == DEBUG_APP_ON || debug == DEBUG_ALL_ON) \ + { do{printf(fmt,##arg);} while(0); } + +/* LPC Interface */ +#define LPC_ADDR_PORT (0x4E) +#define LPC_DATA_PORT (0x4F) + +/* FMC REGISTER ADDR */ +#define FMC_BASE_ADDR (0x1E620000) +#define FMC_CE_TYPE_SETTING_REG (FMC_BASE_ADDR + 0x00) +#define CE_CONTROL_REGISTER (FMC_BASE_ADDR + 0x04) +#define INR_STATUS_CONTROL_REGISTER (FMC_BASE_ADDR + 0x08) +#define COMMAND_CONTROL_REGISTER (FMC_BASE_ADDR + 0x0C) +#define CE0_CONTROL_REGISTER (FMC_BASE_ADDR + 0x10) +#define CE1_CONTROL_REGISTER (FMC_BASE_ADDR + 0x14) +#define CE0_ADDRESS_RANGE_REGISTER (FMC_BASE_ADDR + 0x30) +#define CE1_ADDRESS_RANGE_REGISTER (FMC_BASE_ADDR + 0x34) + +/* SCU REGISTER ADDR */ +#define SCU_ADDR (0x1E6E2000) +#define HARDWARE_STRAP_REGISTER (SCU_ADDR + 0x70) +#define REBOOT_CPU_REGISTER (SCU_ADDR + 0x7C) + +/* SCU KEY */ +#define UNLOCK_SCU_KEY (0x1688A8A8) +#define LOCK_SCU_KEY (0x11111111) + +/* WATCHDOG REGISTER ADDR */ +#define WATCHDOG_ADDR (0x1E785000) +#define WATCHDOG1_RELOAD_VALUE (WATCHDOG_ADDR + 0x04) +#define WATCHDOG1_COUNTER_RST (WATCHDOG_ADDR + 0x08) +#define WATCHDOG1_CONTROL (WATCHDOG_ADDR + 0x0C) +#define WATCHDOG1_TSR (WATCHDOG_ADDR + 0x10) +#define WATCHDOG1_CLEAR_STATUS (WATCHDOG_ADDR + 0x14) +#define WATCHDOG1_RESET_FUN_MASK (WATCHDOG_ADDR + 0x1C) + +#define WATCHDOG2_RELOAD_VALUE (WATCHDOG_ADDR + 0x24) +#define WATCHDOG2_COUNTER_RST (WATCHDOG_ADDR + 0x28) +#define WATCHDOG2_CONTROL (WATCHDOG_ADDR + 0x2C) +#define WATCHDOG2_TSR (WATCHDOG_ADDR + 0x30) +#define WATCHDOG2_CLEAR_STATUS (WATCHDOG_ADDR + 0x34) +#define WATCHDOG2_RESET_FUN_MASK (WATCHDOG_ADDR + 0x3C) + +/* User Mode Command */ +#define WRITE_STATUS (0x01) +#define COMMON_PAGE_PROGRAM (0x02) +#define COMMON_FLASH_READ (0x03) +#define WRITE_DISABLE_FLASH (0x04) +#define READ_FLASH_STATUS (0x05) +#define WRITE_ENABLE_FLASH (0x06) +#define PAGE_PROGRAM_FLASH (0x12) +#define SECTOR_ERASE (0x20) +#define CLEAR_FLAG (0x50) +#define SUBBLOCK_ERASE (0x52) +#define CHIP_ERASE_FLASH (0x60) +#define BLOCK_ERASE_64 (0xD8) +#define READID (0x9F) +#define ENABLE_BYTE4 (0xB7) +#define EXIT_OTP (0xC1) +#define RSTEN (0x66) +#define RST (0x99) + +#define BIT1 (0x01) +#define BIT2 (0x02) +#define BIT3 (0x04) +#define BIT4 (0x08) +#define BIT5 (0x10) +#define BIT6 (0x20) +#define BIT7 (0x40) +#define BIT8 (0x80) +#define RIGHT_SHIFT_8(reg) (reg >> 8) +#define RIGHT_SHIFT_16(reg) (reg >> 16) +#define RIGHT_SHIFT_24(reg) (reg >> 24) +#define MASK (0xFF) +#define FLASH_TYPE_MASK (BIT1 | BIT2) +#define BOOT_DEFAULT_MASK (BIT8) +#define HEAD_MASK (0x00FFFF00) +#define MASK_BYTE (0xFF000000) +#define BYTE1 (1) +#define BYTE2 (2) +#define BYTE4 (4) +#define BYTE1_VAL (0) +#define BYTE2_VAL (1) +#define BYTE4_VAL (2) +#define BYTE_RESERVED (3) + +/* SuperIO */ +#define SUPERIO_07 (0x07) +#define SUPERIO_30 (0x30) +#define SUPERIO_A0 (0xA0) +#define SUPERIO_A2 (0xA2) +#define SUPERIO_REG0 (0xF0) +#define SUPERIO_REG1 (0xF1) +#define SUPERIO_REG2 (0xF2) +#define SUPERIO_REG3 (0xF3) +#define SUPERIO_REG4 (0xF4) +#define SUPERIO_REG5 (0xF5) +#define SUPERIO_REG6 (0xF6) +#define SUPERIO_REG7 (0xF7) +#define SUPERIO_REG8 (0xF8) +#define SUPERIO_FE (0xFE) + +/* SPI Command */ +#define HIGH_CLOCK (0x00000000) +#define NORMAL_READ (0x00000000) +#define READ_MODE (0x00000001) +#define WRITE_MODE (0x00000002) +#define USER_MODE (0x00000003) +#define PULL_DOWN (0x00000000) +#define PULL_UP (0x00000004) + +#define CHIP_ERASE_TIME (60) +#define CHIP_ERASE_TIMEOUT (300 * 1000 * 1000) +#define CHIP_ERASE_SLEEP_TIME (5 * 1000 * 1000) +#define BLOCK_ERASE_TIMEOUT (10 * 1000 * 1000) +#define BLOCK_ERASE_SLEEP_TIME (100 * 1000) +#define PAGE_PROGRAM_TIMEOUT (100 * 1000) +#define PAGE_PROGRAM_SLEEP_TIME (1000) +#define FLASH_WEL_TIMEOUT (100 * 1000) +#define FLASH_WEL_SLEEP_TIME (1000) +#define FLASH_WIP_MASK (0x00000001) +#define FLASH_WRITE_ENABLE_MASK (0x00000002) + +#define DATA_LENGTH_MASK (0xA2) +#define TOGGLE_WRITE (0xCF) +#define DISABLE_LPC (0xAA) +#define ENABLE_LPC (0xA5) +#define LPC_TO_AHB (0x0D) +#define ENABLE_LPC_TO_AHB (0x01) +#define DISABLE_LPC_TO_AHB (0x00) +#define ENABLE_BMC_CPU_BOOT (0xF10BD286) +#define DISABLE_BMC_CPU_BOOT (0xF10BD287) +#define SET_BMC_CPU_BOOT (0x01) +#define CLEAR_WATCHDOG_STATUS (0x01) +#define DISABLE_WATCHDOG (0x00000030) +#define ENABLE_WATCHDOG (0x00000033) +#define WATCHDOG_GATEMASK (0x033FFFF3) +#define WATCHDOG_NEW_COUNT (0x00050000) +#define WATCHDOG_RELOAD_COUNTER (0x4755) + +#define CE0_SPI_TYPE (0x00000002) +#define CE1_SPI_TYPE (0x00000008) +#define ERROR_COMMAND (0x00000400) +#define ADDRESS_PROTECT (0x00000200) +#define CLEAR_INR_STATUS_CONTROL (ERROR_COMMAND | ADDRESS_PROTECT) +#define USER_MODE_PULL_CE_DOWN (HIGH_CLOCK | USER_MODE | PULL_DOWN) +#define USER_MODE_PULL_CE_UP (HIGH_CLOCK | USER_MODE | PULL_UP) + +#define STEP_64 (64 * 1024) +#define STEP_256 (256 * 1024) +#define BYTE_256 (256) + +#define CE0 (0) +#define CE1 (1) +#define BOTHFLASH (2) +#define SOC_SYS (0) +#define FULL_CHIP (1) +#define ARM_CPU (2) +#define FULL_ERASE (0) +#define BLOCK_ERASE (1) +#define READ_ALL (2) +#define CURRENT_SLAVE (1) +#define CURRENT_MASTER (0) +#define REGISTER_HEAD (0x1e000000) +#define DEFAULT_WIDTH (16) +#define MAX_FILENAME_LENGTH (64) +#define SEGMENT_ADDR_START(_r) ((((_r) >> 16) & 0xFF) << 23) + +typedef struct flash_info { + uint32_t flash_size; + int cs; + int flash_type; + uint32_t flash_id; + int page_size; + char flash_name[64]; + int erase_block_command; + int page_program; + int block_size; + int full_erase; + uint32_t ce_control_reg; + uint32_t flash_base_addr; +} flash_info_t; + +typedef enum flash_id { + MX25L6433F = 0x1920c2, + S25FL512S = 0x200201, + MX25l512 = 0x1a20c2, + STM25P64 = 0x172020, + STM25P128 = 0x182020, + N25Q256 = 0x19ba20, + N25Q512 = 0x20ba20, + W25X16 = 0x1530ef, + W25X64 = 0x1730ef, + W25Q64BV = 0x1740ef, + W25Q128BV = 0x1840ef, + W25Q256FV = 0x1940ef, + MX25L1605D = 0x1520C2, + MX25L12805D = 0x1820C2, + MX66L1G45G = 0x1B20C2, + SST25VF016B = 0x4125bf, + SST25VF064C = 0x4b25bf, + SST25VF040B = 0x8d25bf, + AT25DF161 = 0x02461F, + AT25DF321 = 0x01471F, + GD25Q256 = 0X1940c8, +} flash_id_t; + +typedef enum flash_type { + NOR = 0, + SPI = 2, +} flash_type_t; + +typedef enum flash_size { + M1 = 0x00080000, + M3 = 0x00200000, /* 3M */ + M6 = 0x00400000, /* 6M */ + M12 = 0x00800000, /* 12M */ + M16 = 0x01000000, /* 16M */ + M32 = 0x02000000, /* 32M */ + M64 = 0x04000000, /* 64M */ + M128 = 0x08000000, /* 128M */ +} flash_size_t; + +#endif /*_FW_UPGRADE_H_*/ diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/app/fw_upgrade/fw_upgrade/include/fw_upgrade_debug.h b/platform/broadcom/sonic-platform-modules-ragile/common/app/fw_upgrade/fw_upgrade/include/fw_upgrade_debug.h new file mode 100644 index 000000000000..05911da62a7e --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/app/fw_upgrade/fw_upgrade/include/fw_upgrade_debug.h @@ -0,0 +1,25 @@ +#ifndef __FW_UPGRADE_DEBUG_H__ +#define __FW_UPGRADE_DEBUG_H__ + +#include + +#define DEBUG_INFO_LEN 20 +#define DEBUG_FILE "/tmp/.fw_upgrade_debug" +#define DEBUG_ON_ALL "3" +#define DEBUG_ON_KERN "2" +#define DEBUG_ON_INFO "1" +#define DEBUG_OFF_INFO "0" + +#define mem_clear(data, size) memset((data), 0, (size)) + +enum debug_s { + DEBUG_OFF = 0, + DEBUG_APP_ON, + DEBUG_KERN_ON, + DEBUG_ALL_ON, + DEBUG_IGNORE, +}; + +extern int fw_upgrade_debug(void); + +#endif /* End of __FW_UPGRADE_DEBUG_H__ */ diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/depmod_conf/distsearch.conf b/platform/broadcom/sonic-platform-modules-ragile/common/depmod_conf/distsearch.conf deleted file mode 100644 index ad60b2eb6f95..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/common/depmod_conf/distsearch.conf +++ /dev/null @@ -1,4 +0,0 @@ -# depmod.conf -# -# override default search ordering for kmod packaging -search updates extra external built-in weak-updates diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/lib/algorithm/__init__.py b/platform/broadcom/sonic-platform-modules-ragile/common/lib/algorithm/__init__.py new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/lib/algorithm/hysteresis.py b/platform/broadcom/sonic-platform-modules-ragile/common/lib/algorithm/hysteresis.py new file mode 100644 index 000000000000..81fd596e7fee --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/lib/algorithm/hysteresis.py @@ -0,0 +1,169 @@ +#!/usr/bin/env python3 +import os +import syslog +import copy + +from plat_hal.baseutil import baseutil + +HYST_DEBUG_FILE = "/etc/.hysteresis_debug_flag" + +HYSTERROR = 1 +HYSTDEBUG = 2 + +debuglevel = 0 + + +def hyst_debug(s): + if HYSTDEBUG & debuglevel: + syslog.openlog("FANCONTROL-HYST", syslog.LOG_PID) + syslog.syslog(syslog.LOG_DEBUG, s) + + +def hyst_error(s): + if HYSTERROR & debuglevel: + syslog.openlog("FANCONTROL-HYST", syslog.LOG_PID) + syslog.syslog(syslog.LOG_ERR, s) + + +class hysteresis(object): + __config = None + __hyst_config = None + + def __init__(self): + self.__config = baseutil.get_monitor_config() + self.__hyst_config = copy.deepcopy(self.__config.get("hyst", {})) + # init check + errcnt = 0 + errmsg = "" + self.debug_init() + for temp_hyst_conf in self.__hyst_config.values(): + if temp_hyst_conf["flag"] == 0: + continue + for i in range(temp_hyst_conf["temp_min"], temp_hyst_conf["temp_max"] + 1): + if i not in temp_hyst_conf["rising"]: + errcnt -= 1 + msg = "%s hyst config error, temp value %d not in rising curve;" % (temp_hyst_conf["name"], i) + hyst_error(msg) + errmsg += msg + if i not in temp_hyst_conf["descending"]: + errcnt -= 1 + msg = "%s hyst config error, temp value %d not in descending curve;" % (temp_hyst_conf["name"], i) + hyst_error(msg) + errmsg += msg + if errcnt < 0: + raise KeyError(errmsg) + + def debug_init(self): + global debuglevel + if os.path.exists(HYST_DEBUG_FILE): + debuglevel = debuglevel | HYSTDEBUG | HYSTERROR + else: + debuglevel = debuglevel & ~(HYSTDEBUG | HYSTERROR) + + def get_temp_hyst_conf(self, temp_name): + temp_hyst_conf = self.__hyst_config.get(temp_name) + return temp_hyst_conf + + def get_temp_update(self, hyst_para, current_temp): + temp = hyst_para["value"] + if temp is None: + return None + temp.append(current_temp) + del temp[0] + return temp + + def duty_to_pwm(self, duty): + pwm = int(round(float(duty) * 255 / 100)) + return pwm + + def pwm_to_duty(self, pwm): + duty = int(round(float(pwm) * 100 / 255)) + return duty + + def calc_hyst_val(self, temp_name, temp_list): + + temp_hyst_conf = self.get_temp_hyst_conf(temp_name) + hyst_min = temp_hyst_conf["hyst_min"] + hyst_max = temp_hyst_conf["hyst_max"] + temp_min = temp_hyst_conf["temp_min"] + temp_max = temp_hyst_conf["temp_max"] + rising = temp_hyst_conf["rising"] + descending = temp_hyst_conf["descending"] + last_hyst_value = temp_hyst_conf["last_hyst_value"] + current_temp = temp_list[1] + last_temp = temp_list[0] + + hyst_debug("calc_hyst_val, temp_name: %s, current_temp: %s, last_temp: %s, last_hyst_value: %s" % + (temp_name, current_temp, last_temp, last_hyst_value)) + + if current_temp < temp_min: + hyst_debug("%s current_temp %s less than temp_min %s, set min hyst value: %s" % + (temp_name, current_temp, temp_min, hyst_min)) + return hyst_min + + if current_temp > temp_max: + hyst_debug("%s current_temp %s more than temp_max %s, set max hyst value: %s" % + (temp_name, current_temp, temp_max, hyst_max)) + return hyst_max + + if last_temp is None: # first time + hyst_value = rising[current_temp] + hyst_debug("last_temp is None, it's first hysteresis, using rising hyst value: %s" % hyst_value) + return hyst_value + + if current_temp == last_temp: # temp unchanging + hyst_debug("current_temp equal last_temp, keep last hyst value: %s" % last_hyst_value) + return last_hyst_value + + if current_temp > last_temp: + calc_hyst_value = rising[current_temp] + if calc_hyst_value < last_hyst_value: + hyst_value = last_hyst_value + else: + hyst_value = calc_hyst_value + hyst_debug("temp rising, last_hyst_value: %s, calc_hyst_value: %s, set hyst value: %s" % + (last_hyst_value, calc_hyst_value, hyst_value)) + return hyst_value + + calc_hyst_value = descending[current_temp] + if calc_hyst_value > last_hyst_value: + hyst_value = last_hyst_value + else: + hyst_value = calc_hyst_value + hyst_debug("temp descending, last_hyst_value: %s, calc_hyst_value: %s, set hyst value: %s" % + (last_hyst_value, calc_hyst_value, hyst_value)) + return hyst_value + + def cacl(self, temp_name, current_temp): + self.debug_init() + try: + temp_hyst_conf = self.get_temp_hyst_conf(temp_name) + if temp_hyst_conf is None: + hyst_debug("get %s hysteresis config failed" % temp_name) + return None + + flag = temp_hyst_conf["flag"] + if flag != 1: + hyst_debug("%s hysteresis flag == 0, skip" % temp_name) + return None + + temp = self.get_temp_update(temp_hyst_conf, current_temp) + if temp is None: + hyst_debug("get %s update failed" % temp_name) + return None + + value = self.calc_hyst_val(temp_name, temp) + + temp_hyst_conf["last_hyst_value"] = value + + speed_type = temp_hyst_conf["type"] + if speed_type == "duty": + pwm = self.duty_to_pwm(value) + else: + pwm = value + + hyst_debug("temp_name: %s, current_temp: %s, set pwm 0x%x" % (temp_name, current_temp, pwm)) + return pwm + except Exception as e: + hyst_error("temp_name: %s calc hysteresis pwm error, msg: %s" % (temp_name, str(e))) + return None diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/lib/algorithm/openloop.py b/platform/broadcom/sonic-platform-modules-ragile/common/lib/algorithm/openloop.py new file mode 100644 index 000000000000..6ff731fa7eb2 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/lib/algorithm/openloop.py @@ -0,0 +1,104 @@ +#!/usr/bin/env python3 +import os +import syslog + +from plat_hal.baseutil import baseutil + +OPENLOOP_DEBUG_FILE = "/etc/.openloop_debug_flag" + +OPENLOOPERROR = 1 +OPENLOOPDEBUG = 2 + +debuglevel = 0 + + +def openloop_debug(s): + if OPENLOOPDEBUG & debuglevel: + syslog.openlog("FANCONTROL-OPENLOOP", syslog.LOG_PID) + syslog.syslog(syslog.LOG_DEBUG, s) + + +def openloop_error(s): + if OPENLOOPERROR & debuglevel: + syslog.openlog("FANCONTROL-OPENLOOP", syslog.LOG_PID) + syslog.syslog(syslog.LOG_ERR, s) + + +class openloop(object): + __config = None + __openloop_config = None + + def __init__(self): + self.__config = baseutil.get_monitor_config() + self.__openloop_config = self.__config["openloop"] + + def debug_init(self): + global debuglevel + if os.path.exists(OPENLOOP_DEBUG_FILE): + debuglevel = debuglevel | OPENLOOPDEBUG | OPENLOOPERROR + else: + debuglevel = debuglevel & ~(OPENLOOPDEBUG | OPENLOOPERROR) + + def get_para(self, t): + para = self.__openloop_config.get(t) + return para + + def linear_cacl(self, temp): + self.debug_init() + openloop_para = self.get_para("linear") + if openloop_para is None: + openloop_debug("linear openloop: get para failed") + return None + + K = openloop_para["K"] + tin_min = openloop_para["tin_min"] + pwm_min = openloop_para["pwm_min"] + pwm_max = openloop_para["pwm_max"] + flag = openloop_para["flag"] + + if flag != 1: + openloop_debug("linear openloop: flag == 0") + return None + + if temp <= tin_min: + openloop_debug("linear openloop: temp = %d less than tin_min[%d]" % (temp, tin_min)) + return pwm_min + + pwm = int(pwm_min + (temp - tin_min) * K) + openloop_debug("linear openloop: cacl_pwm = 0x%x" % pwm) + + pwm = min(pwm, pwm_max) + pwm = max(pwm, pwm_min) + openloop_debug("linear openloop: temp = %d, pwm = 0x%x" % (temp, pwm)) + return pwm + + def curve_cacl(self, temp): + self.debug_init() + openloop_para = self.get_para("curve") + if openloop_para is None: + openloop_debug("curve openloop: get para failed") + return None + + a = openloop_para["a"] + b = openloop_para["b"] + c = openloop_para["c"] + tin_min = openloop_para["tin_min"] + pwm_min = openloop_para["pwm_min"] + pwm_max = openloop_para["pwm_max"] + flag = openloop_para["flag"] + + if flag != 1: + openloop_debug("curve openloop: flag == 0") + return None + + if temp <= tin_min: + openloop_debug("curve openloop: temp = %d less than tin_min[%d]" % (temp, tin_min)) + return pwm_min + + pwm = int(a * temp * temp + b * temp + c) + openloop_debug("curve openloop: cacl_pwm = 0x%x" % pwm) + + pwm = min(pwm, pwm_max) + pwm = max(pwm, pwm_min) + openloop_debug("curve openloop: temp = %d, pwm = 0x%x" % (temp, pwm)) + return pwm diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/lib/algorithm/pid.py b/platform/broadcom/sonic-platform-modules-ragile/common/lib/algorithm/pid.py new file mode 100644 index 000000000000..c33c1df33b4e --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/lib/algorithm/pid.py @@ -0,0 +1,106 @@ +#!/usr/bin/env python3 +import os +import syslog +import copy + +from plat_hal.baseutil import baseutil + +PID_DEBUG_FILE = "/etc/.pid_debug_flag" + +PIDERROR = 1 +PIDDEBUG = 2 + +debuglevel = 0 + + +def pid_debug(s): + if PIDDEBUG & debuglevel: + syslog.openlog("FANCONTROL-PID", syslog.LOG_PID) + syslog.syslog(syslog.LOG_DEBUG, s) + + +def pid_error(s): + if PIDERROR & debuglevel: + syslog.openlog("FANCONTROL-PID", syslog.LOG_PID) + syslog.syslog(syslog.LOG_ERR, s) + + +class pid(object): + __config = None + __pid_config = None + + def __init__(self): + self.__config = baseutil.get_monitor_config() + self.__pid_config = copy.deepcopy(self.__config["pid"]) + + def debug_init(self): + global debuglevel + if os.path.exists(PID_DEBUG_FILE): + debuglevel = debuglevel | PIDDEBUG | PIDERROR + else: + debuglevel = debuglevel & ~(PIDDEBUG | PIDERROR) + + def get_para(self, name): + para = self.__pid_config.get(name) + return para + + def get_temp_update(self, pid_para, current_temp): + temp = pid_para["value"] + if temp is None: + return None + temp.append(current_temp) + del temp[0] + return temp + + def cacl(self, last_pwm, name, current_temp): + delta_pwm = 0 + self.debug_init() + pid_debug("last_pwm = %d" % last_pwm) + + pid_para = self.get_para(name) + if pid_para is None: + pid_debug("get %s pid para failed" % name) + return None + + temp = self.get_temp_update(pid_para, current_temp) + if temp is None: + pid_debug("get %s update failed" % name) + return None + + speed_type = pid_para["type"] + Kp = pid_para["Kp"] + Ki = pid_para["Ki"] + Kd = pid_para["Kd"] + target = pid_para["target"] + pwm_min = pid_para["pwm_min"] + pwm_max = pid_para["pwm_max"] + flag = pid_para["flag"] + + if flag != 1: + pid_debug("%s pid flag == 0" % name) + return None + + if speed_type == "duty": + current_pwm = round(last_pwm * 100 / 255) + else: + current_pwm = last_pwm + + if temp[2] is None: + tmp_pwm = current_pwm + elif ((temp[0] is None) or (temp[1] is None)): + delta_pwm = Ki * (temp[2] - target) + tmp_pwm = current_pwm + delta_pwm + else: + delta_pwm = Kp * (temp[2] - temp[1]) + Ki * (temp[2] - target) + Kd * (temp[2] - 2 * temp[1] + temp[0]) + tmp_pwm = current_pwm + delta_pwm + + pid_debug("delta_pwm = %d" % delta_pwm) + if speed_type == "duty": + pwm = round(tmp_pwm * 255 / 100) + else: + pwm = int(tmp_pwm) + + pwm = min(pwm, pwm_max) + pwm = max(pwm, pwm_min) + pid_debug("last_pwm = 0x%x, pwm = 0x%x" % (last_pwm, pwm)) + return pwm diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/lib/eepromutil/fantlv.py b/platform/broadcom/sonic-platform-modules-ragile/common/lib/eepromutil/fantlv.py index 38beb068f44c..4be78e7fdc03 100644 --- a/platform/broadcom/sonic-platform-modules-ragile/common/lib/eepromutil/fantlv.py +++ b/platform/broadcom/sonic-platform-modules-ragile/common/lib/eepromutil/fantlv.py @@ -1,19 +1,21 @@ #!/usr/bin/python3 # -*- coding: utf-8 -*- + class FantlvException(Exception): - def __init__(self, message='fantlverror', code=-100): + def __init__(self, message='fantlverror', code=-100): err = 'errcode: {0} message:{1}'.format(code, message) Exception.__init__(self, err) self.code = code self.message = message -class fan_tlv(object): + +class fan_tlv(): HEAD_INFO = "\x01\x7e\x01\xf1" - VERSION = 0x01 # E2PROM file init version is 0x01 - FLAG = 0x7E #new version E2PROM mark as 0x7E - HW_VER = 0X01 # consists of master version and revised version - TYPE = 0xf1 # hardware type define - TLV_LEN = 00 # vaild data length(16bit) + VERSION = 0x01 + FLAG = 0x7E + HW_VER = 0X01 + TYPE = 0xf1 + TLV_LEN = 00 _FAN_TLV_HDR_LEN = 6 _FAN_TLV_CRC_LEN = 2 @@ -22,8 +24,6 @@ class fan_tlv(object): _FAN_TLV_TYPE_HW_INFO = 0x05 _FAN_TLV_TYPE_DEV_TYPE = 0x06 - _fandecodetime = 0 - @property def dstatus(self): return self._dstatus @@ -44,18 +44,6 @@ def typehwinfo(self): def typedevtype(self): return self._typedevtype - @property - def fanbus(self): - return self._fanbus - - @property - def fanloc(self): - return self._fanloc - - @property - def fandecodetime(self): - return self._fandecodetime - def __init__(self): self._typename = "" self._typesn = "" @@ -63,25 +51,20 @@ def __init__(self): self._typedevtype = "" self._dstatus = 0 - def strtoarr(self, str): + def strtoarr(self, val): s = [] - if str is not None: - for index in range(len(str)): - s.append(str[index]) + if not isinstance(val, str): + return s + for index in val: + s.append(index) return s - def str_to_hex(self,rest_v): - value = 0 - for index in range(len(rest_v)): - value |= ord(rest_v[index]) << ((len(rest_v) - index - 1) * 8) - return value - - def hex_to_str(self,s): + def hex_to_str(self, s): len_t = len(s) if len_t % 2 != 0: return 0 ret = "" - for t in range(0, int(len_t / 2)): + for t in range(0, len_t / 2): ret += chr(int(s[2 * t:2 * t + 2], 16)) return ret @@ -92,7 +75,7 @@ def generate_fan_value(self): bin_buffer[2] = chr(self.HW_VER) bin_buffer[3] = chr(self.TYPE) - temp_t = "%08x" % self.typedevtype # handle devtype first + temp_t = "%08x" % self.typedevtype typedevtype_t = self.hex_to_str(temp_t) total_len = len(self.typename) + len(self.typesn) + \ len(self.typehwinfo) + len(typedevtype_t) + 8 @@ -125,10 +108,9 @@ def generate_fan_value(self): len(typedevtype_t)] = self.strtoarr(typedevtype_t) index_start = index_start + 2 + len(typedevtype_t) - crcs = fan_tlv.fancrc(''.join(bin_buffer[0:index_start])) # 2bytes checking + crcs = fan_tlv.fancrc(''.join(bin_buffer[0:index_start])) bin_buffer[index_start] = chr(crcs >> 8) bin_buffer[index_start + 1] = chr(crcs & 0x00ff) - # printvalue(bin_buffer) return bin_buffer def decode(self, e2): @@ -144,7 +126,6 @@ def decode(self, e2): tlv_index = self._FAN_TLV_HDR_LEN tlv_end = self._FAN_TLV_HDR_LEN + self.TLV_LEN - # check sum if len(e2) < self._FAN_TLV_HDR_LEN + self.TLV_LEN + 2: raise FantlvException("Fan tlv eeprom len error!", -2) sumcrc = fan_tlv.fancrc(e2[0:self._FAN_TLV_HDR_LEN + self.TLV_LEN]) @@ -152,8 +133,7 @@ def decode(self, e2): ) << 8 | ord(e2[self._FAN_TLV_HDR_LEN + self.TLV_LEN + 1]) if sumcrc != readcrc: raise FantlvException("Fan tlv eeprom checksum error!", -1) - else: - self._dstatus = 0 + self._dstatus = 0 while (tlv_index + 2) < len(e2) and tlv_index < tlv_end: s = self.decoder( e2[tlv_index:tlv_index + 2 + ord(e2[tlv_index + 1])]) @@ -164,15 +144,16 @@ def decode(self, e2): @staticmethod def fancrc(t): - sum = 0 - for index in range(len(t)): - sum += ord(t[index]) - return sum + crc = 0 + for item in t: + crc += ord(item) + return crc def decoder(self, t): try: name = "" value = "" + _len = 0 if ord(t[0]) == self._FAN_TLV_TYPE_NAME: name = "Product Name" _len = ord(t[1]) @@ -194,10 +175,10 @@ def decoder(self, t): value = "0x" for c in t[2:2 + ord(t[1])]: value += "%02X" % (ord(c),) - self._typedevtype = int(value,16) + self._typedevtype = int(value, 16) except Exception as e: print(e) - return {"name": name, "code": ord(t[0]), "value": value,"lens": _len} + return {"name": name, "code": ord(t[0]), "value": value, "lens": _len} def __str__(self): formatstr = "VERSION : 0x%02x \n" \ @@ -207,6 +188,5 @@ def __str__(self): "typename : %s \n" \ "typesn : %s \n" \ "typehwinfo : %s \n" - return formatstr % (self.VERSION, self.FLAG, self.HW_VER, self.TYPE, self.typename, self.typesn, self.typehwinfo) - - + return formatstr % (self.VERSION, self.FLAG, self.HW_VER, self.TYPE, + self.typename, self.typesn, self.typehwinfo) diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/lib/eepromutil/fru.py b/platform/broadcom/sonic-platform-modules-ragile/common/lib/eepromutil/fru.py index 90a690a19edd..f95164e03601 100644 --- a/platform/broadcom/sonic-platform-modules-ragile/common/lib/eepromutil/fru.py +++ b/platform/broadcom/sonic-platform-modules-ragile/common/lib/eepromutil/fru.py @@ -1,18 +1,14 @@ #!/usr/bin/python3 -# -*- coding: utf-8 -*- import collections -from bitarray import bitarray from datetime import datetime, timedelta -import sys +from bitarray import bitarray -__all__ = ["FruException", "FruUtil", "BaseArea", "BoardInfoArea", "ProductInfoArea", - "MultiRecordArea", "Field", "ipmifru"] __DEBUG__ = "N" class FruException(Exception): - def __init__(self, message='fruerror', code=-100): + def __init__(self, message='fruerror', code=-100): err = 'errcode: {0} message:{1}'.format(code, message) Exception.__init__(self, err) self.code = code @@ -24,7 +20,7 @@ def e_print(err): def d_print(debug_info): - if(__DEBUG__ == "Y"): + if __DEBUG__ == "Y": print(debug_info) @@ -43,7 +39,7 @@ def minToData(): starttime = datetime(1996, 1, 1, 0, 0, 0) endtime = datetime.now() seconds = (endtime - starttime).total_seconds() - mins = seconds / 60 + mins = seconds // 60 m = int(round(mins)) return m @@ -53,7 +49,7 @@ def getTimeFormat(): @staticmethod def getTypeLength(value): - if value is None: + if value is None or len(value) == 0: return 0 a = bitarray(8) a.setall(False) @@ -65,8 +61,8 @@ def getTypeLength(value): @staticmethod def checksum(b): result = 0 - for i in range(len(b)): - result += ord(b[i]) + for item in b: + result += ord(item) return (0x100 - (result & 0xff)) & 0xff @@ -89,7 +85,6 @@ def __init__(self, name="", size=0, offset=0): self._size = size self._isPresent = False self._data = b'\x00' * size - self.__dataoffset = 0 @property def childList(self): @@ -144,6 +139,9 @@ class BoardInfoArea(BaseArea): _boardTime = None _fields = None _mfg_date = None + areaversion = None + _boardversion = None + _language = None def __str__(self): formatstr = "version : %x\n" \ @@ -229,8 +227,7 @@ def decodedata(self): self.fruFileId = self.data[index + 1: index + templen + 1] index += templen + 1 d_print("decode fruFileId:%s" % self.fruFileId) - - + for i in range(1, 11): valtmp = "boardextra%d" % i if self.data[index] != chr(0xc1): @@ -242,6 +239,11 @@ def decodedata(self): else: break + def fruSetValue(self, field, value): + tmp_field = getattr(self, field, None) + if tmp_field is not None: + setattr(self, field, value) + def recalcute(self): d_print("boardInfoArea version:%x" % ord(self.boardversion)) d_print("boardInfoArea length:%d" % self.size) @@ -250,7 +252,7 @@ def recalcute(self): d_print("boardInfoArea mfg_date:%x" % self.mfg_date) self.data = chr(ord(self.boardversion)) + \ - chr(self.size / 8) + chr(self.language) + chr(self.size // 8) + chr(self.language) self.data += chr(self.mfg_date & 0xFF) self.data += chr((self.mfg_date >> 8) & 0xFF) @@ -283,9 +285,7 @@ def recalcute(self): valtmpval = getattr(self, valtmp) d_print("boardInfoArea boardextra%d:%s" % (i, valtmpval)) self.data += chr(FruUtil.getTypeLength(valtmpval)) - if valtmpval is None: - pass - else: + if valtmpval is not None: self.data += valtmpval else: break @@ -293,14 +293,14 @@ def recalcute(self): self.data += chr(0xc1) if len(self.data) > (self.size - 1): - incr = (len(self.data) - self.size) / 8 + 1 + incr = (len(self.data) - self.size) // 8 + 1 self.size += incr * 8 - self.data = self.data[0:1] + chr(self.size / 8) + self.data[2:] + self.data = self.data[0:1] + chr(self.size // 8) + self.data[2:] d_print("self data:%d" % len(self.data)) d_print("self size:%d" % self.size) d_print("adjust size:%d" % (self.size - len(self.data) - 1)) - self.data = self.data.ljust((self.size - 1), self.INITVALUE) + self.data = self.data.ljust((self.size - 1), chr(self.INITVALUE[0])) # checksum checksum = FruUtil.checksum(self.data) @@ -391,6 +391,7 @@ class ProductInfoArea(BaseArea): _productManufacturer = None _productAssetTag = None _FRUFileID = None + _language = None def __str__(self): formatstr = "version : %x\n" \ @@ -483,7 +484,7 @@ def decodedata(self): self.fruFileId = self.data[index + 1: index + templen + 1] index += templen + 1 d_print("decode fruFileId:%s" % self.fruFileId) - + for i in range(1, 11): valtmp = "productextra%d" % i if self.data[index] != chr(0xc1) and index < self.size - 1: @@ -567,12 +568,17 @@ def fruFileId(self): def fruFileId(self, name): self._FRUFileID = name + def fruSetValue(self, field, value): + tmp_field = getattr(self, field, None) + if tmp_field is not None: + setattr(self, field, value) + def recalcute(self): d_print("product version:%x" % ord(self.areaversion)) d_print("product length:%d" % self.size) d_print("product language:%x" % self.language) self.data = chr(ord(self.areaversion)) + \ - chr(self.size / 8) + chr(self.language) + chr(self.size // 8) + chr(self.language) typelength = FruUtil.getTypeLength(self.productManufacturer) self.data += chr(typelength) @@ -597,29 +603,26 @@ def recalcute(self): self.data += chr(FruUtil.getTypeLength(self.fruFileId)) self.data += self.fruFileId - # whether the extended field exists or not for i in range(1, 11): valtmp = "productextra%d" % i if hasattr(self, valtmp): valtmpval = getattr(self, valtmp) d_print("boardInfoArea productextra%d:%s" % (i, valtmpval)) self.data += chr(FruUtil.getTypeLength(valtmpval)) - if valtmpval is None: - pass - else: + if valtmpval is not None: self.data += valtmpval else: break self.data += chr(0xc1) if len(self.data) > (self.size - 1): - incr = (len(self.data) - self.size) / 8 + 1 + incr = (len(self.data) - self.size) // 8 + 1 self.size += incr * 8 d_print("self.data:%d" % len(self.data)) d_print("self.size:%d" % self.size) - self.data = self.data[0:1] + chr(self.size / 8) + self.data[2:] - self.data = self.data.ljust((self.size - 1), self.INITVALUE) + self.data = self.data[0:1] + chr(self.size // 8) + self.data[2:] + self.data = self.data.ljust((self.size - 1), chr(self.INITVALUE[0])) checksum = FruUtil.checksum(self.data) d_print("board info checksum:%x" % checksum) self.data += chr(checksum) @@ -635,17 +638,13 @@ def __init__(self, fieldType="ASCII", fieldData=""): self.fieldData = fieldData self.fieldType = fieldType - @property - def data(self): - return self._data - @property def fieldType(self): - return self._fieldType + return self.fieldType @property def fieldData(self): - return self._fieldData + return self.fieldData class ipmifru(BaseArea): @@ -663,6 +662,7 @@ class ipmifru(BaseArea): _bodybin = None _version = BaseArea.COMMON_HEAD_VERSION _zeroCheckSum = None + _frusize = 256 def __str__(self): tmpstr = "" @@ -677,13 +677,13 @@ def __str__(self): def decodeBin(self, eeprom): commonHead = eeprom[0:8] d_print("decode version %x" % ord(commonHead[0])) - if self.COMMON_HEAD_VERSION != commonHead[0]: + if ord(self.COMMON_HEAD_VERSION) != ord(commonHead[0]): raise FruException("HEAD VERSION error,not Fru format!", -10) if FruUtil.checksum(commonHead[0:7]) != ord(commonHead[7]): strtemp = "check header checksum error [cal:%02x data:%02x]" % ( FruUtil.checksum(commonHead[0:7]), ord(commonHead[7])) raise FruException(strtemp, -3) - if commonHead[1] != self.INITVALUE: + if ord(commonHead[1]) != ord(self.INITVALUE): d_print("Internal Use Area is present") self.internalUseArea = InternalUseArea( name="Internal Use Area", size=self.SUGGESTED_SIZE_INTERNAL_USE_AREA) @@ -691,7 +691,7 @@ def decodeBin(self, eeprom): self.internalUserAreaOffset = ord(commonHead[1]) self.internalUseArea.data = eeprom[self.internalUserAreaOffset * 8: ( self.internalUserAreaOffset * 8 + self.internalUseArea.size)] - if commonHead[2] != self.INITVALUE: + if ord(commonHead[2]) != ord(self.INITVALUE): d_print("Chassis Info Area is present") self.chassisInfoArea = ChassisInfoArea( name="Chassis Info Area", size=self.SUGGESTED_SIZE_CHASSIS_INFO_AREA) @@ -699,7 +699,7 @@ def decodeBin(self, eeprom): self.chassicInfoAreaOffset = ord(commonHead[2]) self.chassisInfoArea.data = eeprom[self.chassicInfoAreaOffset * 8: ( self.chassicInfoAreaOffset * 8 + self.chassisInfoArea.size)] - if commonHead[3] != self.INITVALUE: + if ord(commonHead[3]) != ord(self.INITVALUE): self.boardInfoArea = BoardInfoArea( name="Board Info Area", size=self.SUGGESTED_SIZE_BOARD_INFO_AREA) self.boardInfoArea.isPresent = True @@ -711,12 +711,12 @@ def decodeBin(self, eeprom): self.boardInfoArea.data = eeprom[self.boardInfoAreaOffset * 8: ( self.boardInfoAreaOffset * 8 + self.boardInfoArea.size)] if FruUtil.checksum(self.boardInfoArea.data[:-1]) != ord(self.boardInfoArea.data[-1:]): - print("check boardInfoArea checksum error[cal:%02x data:%02x]" % \ + strtmp = "check boardInfoArea checksum error[cal:%02x data:%02x]" % \ (FruUtil.checksum( - self.boardInfoArea.data[:-1]), ord(self.boardInfoArea.data[-1:]))) - sys.exit(-1) + self.boardInfoArea.data[:-1]), ord(self.boardInfoArea.data[-1:])) + raise FruException(strtmp, -3) self.boardInfoArea.decodedata() - if commonHead[4] != self.INITVALUE: + if ord(commonHead[4]) != ord(self.INITVALUE): d_print("Product Info Area is present") self.productInfoArea = ProductInfoArea( name="Product Info Area ", size=self.SUGGESTED_SIZE_PRODUCT_INFO_AREA) @@ -736,7 +736,7 @@ def decodeBin(self, eeprom): FruUtil.checksum(self.productInfoArea.data[:-1]), ord(self.productInfoArea.data[-1:])) raise FruException(strtmp, -3) self.productInfoArea.decodedata() - if commonHead[5] != self.INITVALUE: + if ord(commonHead[5]) != ord(self.INITVALUE): self.multiRecordArea = MultiRecordArea( name="MultiRecord record Area ") d_print("MultiRecord record present") @@ -752,7 +752,6 @@ def initDefault(self): self.boardInfoAreaOffset = self.INITVALUE self.productinfoAreaOffset = self.INITVALUE self.multiRecordAreaOffset = self.INITVALUE - self.PAD = self.INITVALUE self.zeroCheckSum = self.INITVALUE self.offset = self.SUGGESTED_SIZE_COMMON_HEADER self.productInfoArea = None @@ -878,30 +877,31 @@ def recalcuteCommonHead(self): self.bindata = "" self.offset = self.SUGGESTED_SIZE_COMMON_HEADER d_print("common Header %d" % self.offset) + d_print("fru eeprom size %d" % self._frusize) if self.internalUseArea is not None and self.internalUseArea.isPresent: - self.internalUserAreaOffset = self.offset / 8 + self.internalUserAreaOffset = self.offset // 8 self.offset += self.internalUseArea.size d_print("internalUseArea is present offset:%d" % self.offset) if self.chassisInfoArea is not None and self.chassisInfoArea.isPresent: - self.chassicInfoAreaOffset = self.offset / 8 + self.chassicInfoAreaOffset = self.offset // 8 self.offset += self.chassisInfoArea.size d_print("chassisInfoArea is present offset:%d" % self.offset) if self.boardInfoArea is not None and self.boardInfoArea.isPresent: - self.boardInfoAreaOffset = self.offset / 8 + self.boardInfoAreaOffset = self.offset // 8 self.offset += self.boardInfoArea.size d_print("boardInfoArea is present offset:%d" % self.offset) d_print("boardInfoArea is present size:%d" % self.boardInfoArea.size) if self.productInfoArea is not None and self.productInfoArea.isPresent: - self.productinfoAreaOffset = self.offset / 8 + self.productinfoAreaOffset = self.offset // 8 self.offset += self.productInfoArea.size d_print("productInfoArea is present offset:%d" % self.offset) if self.multiRecordArea is not None and self.multiRecordArea.isPresent: - self.multiRecordAreaOffset = self.offset / 8 + self.multiRecordAreaOffset = self.offset // 8 d_print("multiRecordArea is present offset:%d" % self.offset) if self.internalUserAreaOffset == self.INITVALUE: @@ -918,16 +918,17 @@ def recalcuteCommonHead(self): self.zeroCheckSum = (0x100 - ord(self.version) - self.internalUserAreaOffset - self.chassicInfoAreaOffset - self.productinfoAreaOffset - self.boardInfoAreaOffset - self.multiRecordAreaOffset) & 0xff d_print("zerochecksum:%x" % self.zeroCheckSum) - self.data = self.version + chr(self.internalUserAreaOffset) + chr(self.chassicInfoAreaOffset) + chr( - self.boardInfoAreaOffset) + chr(self.productinfoAreaOffset) + chr(self.multiRecordAreaOffset) + self.INITVALUE + chr(self.zeroCheckSum) + self.data = "" + self.data += chr(self.version[0]) + chr(self.internalUserAreaOffset) + chr(self.chassicInfoAreaOffset) + chr( + self.boardInfoAreaOffset) + chr(self.productinfoAreaOffset) + chr(self.multiRecordAreaOffset) + chr(self.INITVALUE[0]) + chr(self.zeroCheckSum) self.bindata = self.data + self.bodybin totallen = len(self.bindata) d_print("totallen %d" % totallen) - if (totallen < 256): - self.bindata = self.bindata.ljust(256, self.INITVALUE) + if totallen < self._frusize: + self.bindata = self.bindata.ljust(self._frusize, chr(self.INITVALUE[0])) else: - raise FruException('bin data more than 256', -2) + raise FruException('bin data more than %d' % self._frusize, -2) def recalcutebin(self): self.bodybin = "" @@ -949,6 +950,12 @@ def recalcutebin(self): d_print("multiRecordArea present") self.bodybin += self.productInfoArea.data - def recalcute(self): + def recalcute(self, fru_eeprom_size=256): + self._frusize = fru_eeprom_size self.recalcutebin() self.recalcuteCommonHead() + + def setValue(self, area, field, value): + tmp_area = getattr(self, area, None) + if tmp_area is not None: + tmp_area.fruSetValue(field, value) diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/lib/eepromutil/onietlv.py b/platform/broadcom/sonic-platform-modules-ragile/common/lib/eepromutil/onietlv.py new file mode 100644 index 000000000000..a90f8f8453c8 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/lib/eepromutil/onietlv.py @@ -0,0 +1,441 @@ +#!/usr/bin/python3 +import binascii + + +class OnietlvException(Exception): + def __init__(self, message='onietlverror', code=-100): + err = 'errcode: {0} message:{1}'.format(code, message) + Exception.__init__(self, err) + self.code = code + self.message = message + + +class onie_tlv(object): + TLV_INFO_ID_STRING = "TlvInfo\x00" + TLV_INFO_INIA_ID = "\x00\x00\x13\x11" + TLV_INFO_VERSION = 0x01 + TLV_INFO_LENGTH = 0x00 + TLV_INFO_LENGTH_VALUE = 0xba + + TLV_CODE_PRODUCT_NAME = 0x21 + TLV_CODE_PART_NUMBER = 0x22 + TLV_CODE_SERIAL_NUMBER = 0x23 + TLV_CODE_MAC_BASE = 0x24 + TLV_CODE_MANUF_DATE = 0x25 + TLV_CODE_DEVICE_VERSION = 0x26 + TLV_CODE_LABEL_REVISION = 0x27 + TLV_CODE_PLATFORM_NAME = 0x28 + TLV_CODE_ONIE_VERSION = 0x29 + TLV_CODE_MAC_SIZE = 0x2A + TLV_CODE_MANUF_NAME = 0x2B + TLV_CODE_MANUF_COUNTRY = 0x2C + TLV_CODE_VENDOR_NAME = 0x2D + TLV_CODE_DIAG_VERSION = 0x2E + TLV_CODE_SERVICE_TAG = 0x2F + TLV_CODE_VENDOR_EXT = 0xFD + TLV_CODE_CRC_32 = 0xFE + _TLV_DISPLAY_VENDOR_EXT = 1 + TLV_CODE_WB_CARID = 0x01 + _TLV_INFO_HDR_LEN = 11 + TLV_CODE_PRODUCT_ID = 0x40 + TLV_CODE_HW_VERSION = 0x41 + TLV_CODE_MAIN_FILENAME = 0x42 + TLV_CODE_DTS_FINENAME = 0x43 + TLV_CODE_SY_SERIAL0 = 0x44 + TLV_CODE_SY_SERIAL1 = 0x45 + TLV_CODE_SY_SERIAL2 = 0x46 + TLV_CODE_SY_SERIAL3 = 0x47 + TLV_CODE_PROJECT_ID = 0x48 + TLV_CODE_SETMAC_VERSION = 0x49 + TLV_CODE_EEPROM_TYPE = 0x4A + + @property + def dstatus(self): + return self._dstatus + + @property + def cardid(self): + return self._cardid + + @property + def productname(self): + return self._productname + + @property + def partnum(self): + return self._partnum + + @property + def serialnum(self): + return self._serialnum + + @property + def macbase(self): + return self._macbase + + @property + def manufdate(self): + return self._manufdate + + @property + def deviceversion(self): + return self._deviceversion + + @property + def labelrevision(self): + return self._labelrevision + + @property + def platformname(self): + return self._platformname + + @property + def onieversion(self): + return self._onieversion + + @property + def macsize(self): + return self._macsize + + @property + def manufname(self): + return self._manufname + + @property + def manufcountry(self): + return self._manufcountry + + @property + def vendorname(self): + return self._vendorname + + @property + def diagname(self): + return self._diagname + + @property + def servicetag(self): + return self._servicetag + + @property + def vendorext(self): + return self._vendorext + + def __init__(self): + self._cardid = "" + self._productname = "" + self._partnum = "" + self._serialnum = "" + self._macbase = "" + self._manufdate = "" + self._deviceversion = "" + self._labelrevision = "" + self._platformname = "" + self._onieversion = "" + self._macsize = "" + self._manufname = "" + self._manufcountry = "" + self._vendorname = "" + self._diagname = "" + self._servicetag = "" + self._vendorext = "" + self._productid = "" + self._hwversion = "" + self._mainfilename = "" + self._dtsfilename = "" + self._syserial0 = "" + self._syserial1 = "" + self._syserial2 = "" + self._syserial3 = "" + self._projectid = "" + self._setmacversion = "" + self._eepromtype = "" + self._crc32 = "" + self._dstatus = 0 + + def oniecrc32(self, v): + data_array = bytearray() + for x in v: + data_array.append(ord(x)) + return '0x%08x' % (binascii.crc32(bytes(data_array)) & 0xffffffff) + + def getTLV_BODY(self, tlv_type, value): + x = [] + temp_t = "" + if tlv_type == self.TLV_CODE_MAC_BASE: + arr = value.split(':') + for tt in arr: + temp_t += chr(int(tt, 16)) + elif tlv_type == self.TLV_CODE_DEVICE_VERSION: + temp_t = chr(value) + elif tlv_type == self.TLV_CODE_MAC_SIZE: + temp_t = chr(value >> 8) + chr(value & 0x00ff) + else: + temp_t = value + x.append(chr(tlv_type)) + x.append(chr(len(temp_t))) + for i in temp_t: + x.append(i) + return x + + def generate_ext(self, cardid): + s = "%08x" % cardid + ret = "" + for t in range(0, 4): + ret += chr(int(s[2 * t:2 * t + 2], 16)) + ret = chr(0x01) + chr(len(ret)) + ret + return ret + + def generate_value(self, _t): + ret = [] + for i in self.TLV_INFO_ID_STRING: + ret.append(i) + ret.append(chr(self.TLV_INFO_VERSION)) + ret.append(chr(self.TLV_INFO_LENGTH)) + ret.append(chr(self.TLV_INFO_LENGTH_VALUE)) + + total_len = 0 + for key in _t: + x = self.getTLV_BODY(key, _t[key]) + ret += x + total_len += len(x) + ret[10] = chr(total_len + 6) + + ret.append(chr(0xFE)) + ret.append(chr(0x04)) + s = self.oniecrc32(''.join(ret)) + for t in range(0, 4): + ret.append(chr(int(s[2 * t + 2:2 * t + 4], 16))) + totallen = len(ret) + if totallen < 256: + for left_t in range(0, 256 - totallen): + ret.append(chr(0x00)) + return (ret, True) + + def decode_tlv(self, e): + tlv_index = 0 + tlv_end = len(e) + ret = [] + while tlv_index < tlv_end and (tlv_index + 2 + ord(e[tlv_index + 1])) <= len(e): + rt = self.decoder(e[tlv_index:tlv_index + 2 + ord(e[tlv_index + 1])]) + ret.append(rt) + if ord(e[tlv_index]) == self.TLV_CODE_CRC_32: + break + tlv_index += ord(e[tlv_index + 1]) + 2 + return ret + + def decode(self, e): + if e[0:8] != self.TLV_INFO_ID_STRING: + raise OnietlvException("ONIE tlv head info error,not onie tlv type", -1) + total_len = (ord(e[9]) << 8) | ord(e[10]) + tlv_index = self._TLV_INFO_HDR_LEN + tlv_end = self._TLV_INFO_HDR_LEN + total_len + if tlv_end > len(e): + raise OnietlvException("ONIE tlv length error", -2) + ret = [] + ret = self.decode_tlv(e[tlv_index:tlv_end]) + for item in ret: + if item['code'] == self.TLV_CODE_VENDOR_EXT: + if item["value"][0:4] == self.TLV_INFO_INIA_ID: + rt = self.decode_tlv(item["value"][4:]) + else: + rt = self.decode_tlv(item["value"][0:]) + ret.extend(rt) + return ret + + def decoder(self, t): + if ord(t[0]) == self.TLV_CODE_PRODUCT_NAME: + name = "Product Name" + _len = ord(t[1]) + value = t[2:2 + ord(t[1])] + self._productname = value + elif ord(t[0]) == self.TLV_CODE_PART_NUMBER: + name = "Part Number" + _len = ord(t[1]) + value = t[2:2 + ord(t[1])] + self._partnum = value + elif ord(t[0]) == self.TLV_CODE_SERIAL_NUMBER: + name = "Serial Number" + _len = ord(t[1]) + value = t[2:2 + ord(t[1])] + self._serialnum = value + elif ord(t[0]) == self.TLV_CODE_MAC_BASE: + name = "Base MAC Address" + _len = ord(t[1]) + value = ":".join(['%02X' % ord(T) for T in t[2:8]]).upper() + self._macbase = value + elif ord(t[0]) == self.TLV_CODE_MANUF_DATE: + name = "Manufacture Date" + _len = ord(t[1]) + value = t[2:2 + ord(t[1])] + self._manufdate = value + elif ord(t[0]) == self.TLV_CODE_DEVICE_VERSION: + name = "Device Version" + _len = ord(t[1]) + value = ord(t[2]) + self._deviceversion = value + elif ord(t[0]) == self.TLV_CODE_LABEL_REVISION: + name = "Label Revision" + _len = ord(t[1]) + value = t[2:2 + ord(t[1])] + self._labelrevision = value + elif ord(t[0]) == self.TLV_CODE_PLATFORM_NAME: + name = "Platform Name" + _len = ord(t[1]) + value = t[2:2 + ord(t[1])] + self._platformname = value + elif ord(t[0]) == self.TLV_CODE_ONIE_VERSION: + name = "ONIE Version" + _len = ord(t[1]) + value = t[2:2 + ord(t[1])] + self._onieversion = value + elif ord(t[0]) == self.TLV_CODE_MAC_SIZE: + name = "MAC Addresses" + _len = ord(t[1]) + value = str((ord(t[2]) << 8) | ord(t[3])) + self._macsize = value + elif ord(t[0]) == self.TLV_CODE_MANUF_NAME: + name = "Manufacturer" + _len = ord(t[1]) + value = t[2:2 + ord(t[1])] + self._manufname = value + elif ord(t[0]) == self.TLV_CODE_MANUF_COUNTRY: + name = "Manufacture Country" + _len = ord(t[1]) + value = t[2:2 + ord(t[1])] + self._manufcountry = value + elif ord(t[0]) == self.TLV_CODE_VENDOR_NAME: + name = "Vendor Name" + _len = ord(t[1]) + value = t[2:2 + ord(t[1])] + self._vendorname = value + elif ord(t[0]) == self.TLV_CODE_DIAG_VERSION: + name = "Diag Version" + _len = ord(t[1]) + value = t[2:2 + ord(t[1])] + self._diagname = value + elif ord(t[0]) == self.TLV_CODE_SERVICE_TAG: + name = "Service Tag" + _len = ord(t[1]) + value = t[2:2 + ord(t[1])] + self._servicetag = value + elif ord(t[0]) == self.TLV_CODE_VENDOR_EXT: + name = "Vendor Extension" + _len = ord(t[1]) + value = "" + if self._TLV_DISPLAY_VENDOR_EXT: + value = t[2:2 + ord(t[1])] + self._vendorext = value + elif ord(t[0]) == self.TLV_CODE_CRC_32 and len(t) == 6: + name = "CRC-32" + _len = ord(t[1]) + value = "0x%08X" % (((ord(t[2]) << 24) | ( + ord(t[3]) << 16) | (ord(t[4]) << 8) | ord(t[5])),) + self._crc32 = value + elif ord(t[0]) == self.TLV_CODE_WB_CARID: + name = "Card id" + _len = ord(t[1]) + value = "" + for c in t[2:2 + ord(t[1])]: + value += "%02X" % (ord(c),) + self._cardid = value + elif ord(t[0]) == self.TLV_CODE_PRODUCT_ID: + name = "Product id" + _len = ord(t[1]) + value = t[2:2 + ord(t[1])] + self._productid = value + elif ord(t[0]) == self.TLV_CODE_HW_VERSION: + name = "Hardware Version" + _len = ord(t[1]) + value = t[2:2 + ord(t[1])] + self._hwversion = value + elif ord(t[0]) == self.TLV_CODE_MAIN_FILENAME: + name = "Main File Name" + _len = ord(t[1]) + value = t[2:2 + ord(t[1])] + self._mainfilename = value + elif ord(t[0]) == self.TLV_CODE_DTS_FINENAME: + name = "DTS File Name" + _len = ord(t[1]) + value = t[2:2 + ord(t[1])] + self._dtsfilename = value + elif ord(t[0]) == self.TLV_CODE_SY_SERIAL0: + name = "SY Serial 0" + _len = ord(t[1]) + value = t[2:2 + ord(t[1])] + self._syserial0 = value + elif ord(t[0]) == self.TLV_CODE_SY_SERIAL1: + name = "SY Serial 1" + _len = ord(t[1]) + value = t[2:2 + ord(t[1])] + self._syserial1 = value + elif ord(t[0]) == self.TLV_CODE_SY_SERIAL2: + name = "SY Serial 2" + _len = ord(t[1]) + value = t[2:2 + ord(t[1])] + self._syserial2 = value + elif ord(t[0]) == self.TLV_CODE_SY_SERIAL3: + name = "SY Serial 3" + _len = ord(t[1]) + value = t[2:2 + ord(t[1])] + self._syserial3 = value + elif ord(t[0]) == self.TLV_CODE_PROJECT_ID: + name = "Project id" + _len = ord(t[1]) + value = t[2:2 + ord(t[1])] + self._projectid = value + elif ord(t[0]) == self.TLV_CODE_SETMAC_VERSION: + name = "Setmac Version" + _len = ord(t[1]) + value = t[2:2 + ord(t[1])] + self._setmacversion = value + elif ord(t[0]) == self.TLV_CODE_EEPROM_TYPE: + name = "EEPROM Type" + _len = ord(t[1]) + value = "" + for c in t[2:2 + ord(t[1])]: + value += "%02X" % (ord(c),) + self._eepromtype = value + else: + name = "Unknown" + _len = ord(t[1]) + value = "" + for c in t[2:2 + ord(t[1])]: + value += "0x%02X " % (ord(c),) + return {"name": name, "code": ord(t[0]), "value": value, "lens": _len} + + def __str__(self): + formatstr = "Card id : %s \n" \ + "Product Name : %s \n" \ + "Part Number : %s \n" \ + "Serial Number : %s \n" \ + "Base MAC Address : %s \n" \ + "Manufacture Date : %s \n" \ + "Device Version : %s \n" \ + "Label Revision : %s \n" \ + "Platform Name : %s \n" \ + "ONIE Version : %s \n" \ + "MAC Addresses : %s \n" \ + "Manufacturer : %s \n" \ + "Manufacture Country : %s \n" \ + "Vendor Name : %s \n" \ + "Diag Version : %s \n" \ + "Service Tag : %s \n" \ + "CRC-32 : %s \n" + return formatstr % (self._cardid, + self._productname, + self._partnum, + self._serialnum, + self._macbase, + self._manufdate, + self._deviceversion, + self._labelrevision, + self._platformname, + self._onieversion, + self._macsize, + self._manufname, + self._manufcountry, + self._vendorname, + self._diagname, + self._servicetag, + self._crc32) diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/__init__.py b/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/__init__.py new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/baseutil.py b/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/baseutil.py new file mode 100644 index 000000000000..ffe271a424c9 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/baseutil.py @@ -0,0 +1,164 @@ +#!/usr/bin/env python3 +####################################################### +# +# baseutil.py +# Python implementation of the Class baseutil +# +####################################################### +import importlib.machinery +import os +import syslog +import json +from plat_hal.osutil import osutil + +SYSLOG_IDENTIFIER = "HAL" + +CONFIG_DB_PATH = "/etc/sonic/config_db.json" +BOARD_ID_PATH = "/sys/module/platform_common/parameters/dfd_my_type" +BOARD_AIRFLOW_PATH = "/etc/sonic/.airflow" + + +def getonieplatform(path): + if not os.path.isfile(path): + return "" + machine_vars = {} + with open(path) as machine_file: + for line in machine_file: + tokens = line.split('=') + if len(tokens) < 2: + continue + machine_vars[tokens[0]] = tokens[1].strip() + return machine_vars.get("onie_platform") + + +def getboardid(): + if not os.path.exists(BOARD_ID_PATH): + return "NA" + with open(BOARD_ID_PATH) as fd: + id_str = fd.read().strip() + return "0x%x" % (int(id_str, 10)) + + +def getboardairflow(): + if not os.path.exists(BOARD_AIRFLOW_PATH): + return "NA" + with open(BOARD_AIRFLOW_PATH) as fd: + airflow_str = fd.read().strip() + data = json.loads(airflow_str) + airflow = data.get("board", "NA") + return airflow + + +def getplatform_config_db(): + if not os.path.isfile(CONFIG_DB_PATH): + return "" + val = os.popen("sonic-cfggen -j %s -v DEVICE_METADATA.localhost.platform" % CONFIG_DB_PATH).read().strip() + if len(val) <= 0: + return "" + return val + + +def getplatform_name(): + if os.path.isfile('/host/machine.conf'): + return getonieplatform('/host/machine.conf') + if os.path.isfile('/usr/share/sonic/hwsku/machine.conf'): + return getonieplatform('/usr/share/sonic/hwsku/machine.conf') + return getplatform_config_db() + + +platform = (getplatform_name()).replace("-", "_") +boardid = getboardid() +boardairflow = getboardairflow() + + +CONFIG_FILE_PATH_LIST = [ + "/usr/local/bin/", + "/usr/lib/python3/dist-packages/", + "/usr/local/lib/python3.7/dist-packages/hal-config/", + "/usr/local/lib/python3.9/dist-packages/hal-config/" +] + + +DEVICE_CONFIG_FILE_LIST = [ + platform + "_" + boardid + "_" + boardairflow + "_device.py", + platform + "_" + boardid + "_device.py", + platform + "_" + boardairflow + "_device.py", + platform + "_device.py" +] + + +MONITOR_CONFIG_FILE_LIST = [ + platform + "_" + boardid + "_" + boardairflow + "_monitor.py", + platform + "_" + boardid + "_monitor.py", + platform + "_" + boardairflow + "_monitor.py", + platform + "_monitor.py" +] + + +class baseutil: + + CONFIG_NAME = 'devices' + MONITOR_CONFIG_NAME = 'monitor' + UBOOT_ENV_URL = '/etc/device/uboot_env' + + @staticmethod + def get_config(): + real_path = None + for configfile_path in CONFIG_FILE_PATH_LIST: + for config_file in DEVICE_CONFIG_FILE_LIST: + file = configfile_path + config_file + if os.path.exists(file): + real_path = file + break + if real_path is not None: + break + + if real_path is None: + raise Exception("get hal device config error") + devices = importlib.machinery.SourceFileLoader(baseutil.CONFIG_NAME, real_path).load_module() + return devices.devices + + @staticmethod + def get_monitor_config(): + real_path = None + for configfile_path in CONFIG_FILE_PATH_LIST: + for config_file in MONITOR_CONFIG_FILE_LIST: + file = configfile_path + config_file + if os.path.exists(file): + real_path = file + break + if real_path is not None: + break + + if real_path is None: + raise Exception("get hal monitor config error") + monitor = importlib.machinery.SourceFileLoader(baseutil.MONITOR_CONFIG_NAME, real_path).load_module() + return monitor.monitor + + @staticmethod + def get_productname(): + ret, val = osutil.command("cat %s |grep productname | awk -F\"=\" '{print $2;}'" % baseutil.UBOOT_ENV_URL) + tmp = val.lower().replace('-', '_') + if ret != 0 or len(val) <= 0: + raise Exception("get productname error") + return tmp + + @staticmethod + def get_platform(): + ret, val = osutil.command("cat %s |grep conffitname | awk -F\"=\" '{print $2;}'" % baseutil.UBOOT_ENV_URL) + if ret != 0 or len(val) <= 0: + raise Exception("get platform error") + return val + + @staticmethod + def get_product_fullname(): + ret, val = osutil.command("cat %s |grep productname | awk -F\"=\" '{print $2;}'" % baseutil.UBOOT_ENV_URL) + if ret != 0 or len(val) <= 0: + raise Exception("get productname error") + return val + + @staticmethod + def logger_debug(msg): + syslog.openlog(SYSLOG_IDENTIFIER) + syslog.syslog(syslog.LOG_DEBUG, msg) + syslog.closelog() diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/chassisbase.py b/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/chassisbase.py new file mode 100644 index 000000000000..767d6da34ba9 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/chassisbase.py @@ -0,0 +1,318 @@ +#!/usr/bin/env python3 +####################################################### +# +# chassisbase.py +# Python implementation of the Class chassisbase +# +####################################################### +from plat_hal.dcdc import dcdc +from plat_hal.onie_e2 import onie_e2 +from plat_hal.psu import psu +from plat_hal.led import led +from plat_hal.temp import temp +from plat_hal.fan import fan +from plat_hal.cpld import cpld +from plat_hal.component import component +from plat_hal.cpu import cpu +from plat_hal.baseutil import baseutil + + +class chassisbase(object): + __onie_e2_list = [] + __psu_list = [] + __led_list = [] + __temp_list = [] + __fan_list = [] + __card_list = [] + __sensor_list = [] + __dcdc_list = [] + __cpld_list = [] + __comp_list = [] + __bios_list = [] + __bmc_list = [] + __cpu = None + + def __init__(self, conftype=0, conf=None): + # type: (object, object, object) -> object + """ + init chassisbase as order + + type = 0 use default conf, maybe auto find by platform + type = 1 use given conf, conf is not None + + BITMAP + bit 16 + bit 0 PSU + bit 1 LED + bit 2 TEMP + bit 3 fan + bit 4 card + bit 5 sensor + """ + __confTemp = None + + if conftype == 0: + # user + __confTemp = baseutil.get_config() + elif conftype == 1: + __confTemp = conf + + # onie_e2 + onie_e2temp = [] + onie_e2config = __confTemp.get('onie_e2', []) + for item in onie_e2config: + onie_e2_1 = onie_e2(item) + onie_e2temp.append(onie_e2_1) + self.onie_e2_list = onie_e2temp + + # psu + psutemp = [] + psuconfig = __confTemp.get('psus', []) + for item in psuconfig: + psu1 = psu(item) + psutemp.append(psu1) + self.psu_list = psutemp + + # led + ledtemp = [] + ledconfig = __confTemp.get('leds', []) + for item in ledconfig: + led1 = led(item) + ledtemp.append(led1) + self.led_list = ledtemp + + # temp + temptemp = [] + tempconfig = __confTemp.get('temps', []) + for item in tempconfig: + temp1 = temp(item) + temptemp.append(temp1) + self.temp_list = temptemp + + # fan + fantemp = [] + fanconfig = __confTemp.get('fans', []) + for item in fanconfig: + fan1 = fan(item) + fantemp.append(fan1) + self.fan_list = fantemp + + # dcdc + dcdctemp = [] + dcdcconfig = __confTemp.get('dcdc', []) + for item in dcdcconfig: + dcdc1 = dcdc(item) + dcdctemp.append(dcdc1) + self.dcdc_list = dcdctemp + + # cpld + cpldtemp = [] + cpldconfig = __confTemp.get('cplds', []) + for item in cpldconfig: + cpld1 = cpld(item) + cpldtemp.append(cpld1) + self.cpld_list = cpldtemp + + # compoment: cpld/fpga/bios + comptemp = [] + compconfig = __confTemp.get('comp_cpld', []) + for item in compconfig: + comp1 = component(item) + comptemp.append(comp1) + self.comp_list = comptemp + + compconfig = __confTemp.get('comp_fpga', []) + for item in compconfig: + comp1 = component(item) + self.comp_list.append(comp1) + + compconfig = __confTemp.get('comp_bios', []) + for item in compconfig: + comp1 = component(item) + self.comp_list.append(comp1) + + # cpu + cpuconfig = __confTemp.get('cpu', []) + if len(cpuconfig): + self.cpu = cpu(cpuconfig[0]) + + # dcdc + @property + def dcdc_list(self): + return self.__dcdc_list + + @dcdc_list.setter + def dcdc_list(self, val): + self.__dcdc_list = val + + # sensor + @property + def sensor_list(self): + return self.__sensor_list + + @sensor_list.setter + def sensor_list(self, val): + self.__sensor_list = val + + def get_sensor_byname(self, name): + tmp = self.sensor_list + for item in tmp: + if name == item.name: + return item + return None + + # onie_e2 + @property + def onie_e2_list(self): + return self.__onie_e2_list + + @onie_e2_list.setter + def onie_e2_list(self, val): + self.__onie_e2_list = val + + def get_onie_e2_byname(self, name): + tmp = self.onie_e2_list + for item in tmp: + if name == item.name: + return item + return None + + # psu + @property + def psu_list(self): + return self.__psu_list + + @psu_list.setter + def psu_list(self, val): + self.__psu_list = val + + def get_psu_byname(self, name): + tmp = self.psu_list + for item in tmp: + if name == item.name: + return item + return None + + # fan + @property + def fan_list(self): + return self.__fan_list + + @fan_list.setter + def fan_list(self, val): + self.__fan_list = val + + def get_fan_byname(self, name): + tmp = self.fan_list + for item in tmp: + if name == item.name: + return item + return None + + # led + + @property + def led_list(self): + return self.__led_list + + @led_list.setter + def led_list(self, val): + self.__led_list = val + + def get_led_byname(self, name): + tmp = self.led_list + for item in tmp: + if name == item.name: + return item + return None + + # temp + @property + def temp_list(self): + return self.__temp_list + + @temp_list.setter + def temp_list(self, val): + self.__temp_list = val + + def get_temp_byname(self, name): + tmp = self.temp_list + for item in tmp: + if name == item.name: + return item + return None + + # cpld + @property + def cpld_list(self): + return self.__cpld_list + + @cpld_list.setter + def cpld_list(self, val): + self.__cpld_list = val + + def get_cpld_byname(self, name): + tmp = self.cpld_list + for item in tmp: + if name == item.name: + return item + return None + + @property + def comp_list(self): + return self.__comp_list + + @comp_list.setter + def comp_list(self, val): + self.__comp_list = val + + def get_comp_byname(self, name): + tmp = self.comp_list + for item in tmp: + if name == item.name: + return item + return None + + # bios + @property + def bios_list(self): + return self.__bios_list + + @bios_list.setter + def bios_list(self, val): + self.__bios_list = val + + def get_bios_byname(self, name): + tmp = self.bios_list + for item in tmp: + if name == item.name: + return item + return None + + # bmc + @property + def bmc_list(self): + return self.__bmc_list + + @bmc_list.setter + def bmc_list(self, val): + self.__bmc_list = val + + def get_bmc_byname(self, name): + tmp = self.bmc_list + for item in tmp: + if name == item.name: + return item + return None + + # cpu + @property + def cpu(self): + return self.__cpu + + @cpu.setter + def cpu(self, val): + self.__cpu = val + + def get_cpu_byname(self, name): + return self.cpu diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/component.py b/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/component.py new file mode 100644 index 000000000000..0f2ad2167485 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/component.py @@ -0,0 +1,33 @@ +#!/usr/bin/env python3 +####################################################### +# +# component.py +# Python implementation of the Class fan +# +####################################################### +from plat_hal.devicebase import devicebase +from plat_hal.osutil import osutil + + +class component(devicebase): + __user_reg = None + + def __init__(self, conf=None): + if conf is not None: + self.name = conf.get('name', None) + self.version_file = conf.get('VersionFile', None) + self.comp_id = conf.get("comp_id", None) + self.desc = conf.get("desc", None) + self.slot = conf.get("slot", None) + + def get_version(self): + version = "NA" + try: + ret, version = self.get_value(self.version_file) + if ret is False: + return version + pattern = self.version_file.get('pattern', None) + version = osutil.std_match(version, pattern) + except Exception: + return version + return version diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/cpld.py b/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/cpld.py new file mode 100644 index 000000000000..09eed5f975ee --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/cpld.py @@ -0,0 +1,66 @@ +#!/usr/bin/env python3 +####################################################### +# +# fan.py +# Python implementation of the Class fan +# +####################################################### +from plat_hal.devicebase import devicebase + + +class cpld(devicebase): + __user_reg = None + + def __init__(self, conf=None): + if conf is not None: + self.name = conf.get('name', None) + self.user_reg = conf.get('UserReg', None) + self.console_reg = conf.get('ConsoleReg', None) + self.console_reg_attrs = conf.get('ConsoleRegAttrs', None) + self.version_file = conf.get('VersionFile', None) + self.cpld_id = conf.get("cpld_id", None) + self.desc = conf.get("desc", None) + self.slot = conf.get("slot", None) + self.format = conf.get("format", "big_endian") + self.warm = conf.get("warm", None) + self.type = conf.get("type", None) + + def get_user_reg(self): + if self.user_reg is None: + return False + ret, val = self.get_value(self.user_reg) + return val + + def set_user_reg(self, value): + if self.user_reg is None: + return False + byte = value & 0xFF + ret, val = self.set_value(self.user_reg, byte) + return ret + + def set_console_owner(self, owner): + ret = False + + if self.console_reg is None: + return False + tmpattr = self.console_reg_attrs.get(owner, None) + if tmpattr is not None: + ret, val = self.set_value(self.console_reg, tmpattr) + return ret + + def get_version(self): + ret, val = self.get_value(self.version_file) + if ret is False: + val = "N/A" + return val + if self.type == "str": + return val.strip('\n') + val = val.strip('\n').split(" ") + if len(val) < 4: + val = "N/A" + return val + if self.format == "little_endian": + cpld_version = "%s%s%s%s" % (val[3], val[2], val[1], val[0]) + else: + cpld_version = "%s%s%s%s" % (val[0], val[1], val[2], val[3]) + return cpld_version diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/cpu.py b/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/cpu.py new file mode 100644 index 000000000000..c6bec1abd1c2 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/cpu.py @@ -0,0 +1,48 @@ +#!/usr/bin/env python3 +############################################################################### +# +# Hardware Abstraction Layer APIs -- CPU APIs. +# +############################################################################### +from plat_hal.devicebase import devicebase + + +class cpu(devicebase): + + def __init__(self, conf=None): + if conf is not None: + self.name = conf.get('name', None) + self.cpu_reset_cnt_reg = conf.get('CpuResetCntReg', None) + self.reboot_cause_path = conf.get('reboot_cause_path', "/etc/sonic/.reboot/.previous-reboot-cause.txt") + + def get_cpu_reset_num(self): + """ + get cpu reset num. + @return cpu reset number, -1 for failure + """ + ret = -1 + if self.cpu_reset_cnt_reg is None: + self.logger_debug("ERR: no support get cpu reset num") + return ret + ret, reset_num = self.get_value(self.cpu_reset_cnt_reg) + if ret is False or reset_num is None: + self.logger_debug("ERR: i2c read cpu_reset_cnt_reg,result:%s" % reset_num) + else: + if isinstance(reset_num, str): + ret = int(reset_num, 16) + else: + ret = reset_num + return ret + + def get_cpu_reboot_cause(self): + """ + get_cpu_reboot_cause + @return cpu reset number, -1 for failure + """ + try: + with open(self.reboot_cause_path) as fd: + reboot_cause = fd.read().strip() + return reboot_cause + except Exception: + return "Unknown reboot cause" + diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/dcdc.py b/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/dcdc.py new file mode 100644 index 000000000000..ba604995043d --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/dcdc.py @@ -0,0 +1,11 @@ +#!/usr/bin/env python3 +from plat_hal.devicebase import devicebase +from plat_hal.sensor import sensor + + +class dcdc(devicebase): + def __init__(self, conf=None): + if conf is not None: + self.name = conf.get('name', None) + self.dcdc_id = conf.get("dcdc_id", None) + self.sensor = sensor(conf) diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/devicebase.py b/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/devicebase.py new file mode 100644 index 000000000000..e66ae0143f02 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/devicebase.py @@ -0,0 +1,355 @@ +#!/usr/bin/env python3 +####################################################### +# +# devicebase.py +# Python implementation of the Class devicebase +# +####################################################### +import subprocess +import shlex +import ast +from plat_hal.osutil import osutil +from plat_hal.baseutil import baseutil + +class CodeVisitor(ast.NodeVisitor): + + def __init__(self): + self.value = None + + def get_value(self): + return self.value + + def get_op_value(self, node): + if isinstance(node, ast.Call): # node is func call + value = self.visit_Call(node) + elif isinstance(node, ast.BinOp): # node is BinOp + value = self.visit_BinOp(node) + elif isinstance(node, ast.UnaryOp): # node is UnaryOp + value = self.visit_UnaryOp(node) + elif isinstance(node, ast.Num): # node is Num Constant + value = node.n + elif isinstance(node, ast.Str): # node is Str Constant + value = node.s + else: + raise NotImplementedError("Unsupport operand type: %s" % type(node)) + return value + + def visit_UnaryOp(self, node): + ''' + node.op: operand type, only support ast.UAdd/ast.USub + node.operand: only support ast.Call/ast.Constant(ast.Num/ast.Str)/ast.BinOp/ast.UnaryOp + ''' + + operand_value = self.get_op_value(node.operand) + if isinstance(node.op, ast.UAdd): + self.value = operand_value + elif isinstance(node.op, ast.USub): + self.value = 0 - operand_value + else: + raise NotImplementedError("Unsupport arithmetic methods %s" % type(node.op)) + return self.value + + def visit_BinOp(self, node): + ''' + node.left: left operand, only support ast.Call/ast.Constant(ast.Num)/ast.BinOp + node.op: operand type, only support ast.Add/ast.Sub/ast.Mult/ast.Div + node.right: right operan, only support ast.Call/ast.Constant(ast.Num/ast.Str)/ast.BinOp + ''' + left_value = self.get_op_value(node.left) + right_value = self.get_op_value(node.right) + + if isinstance(node.op, ast.Add): + self.value = left_value + right_value + elif isinstance(node.op, ast.Sub): + self.value = left_value - right_value + elif isinstance(node.op, ast.Mult): + self.value = left_value * right_value + elif isinstance(node.op, ast.Div): + self.value = left_value / right_value + else: + raise NotImplementedError("Unsupport arithmetic methods %s" % type(node.op)) + return self.value + + def visit_Call(self, node): + ''' + node.func.id: func name, only support 'float', 'int', 'str' + node.args: func args list,only support ast.Constant(ast.Num/ast.Str)/ast.BinOp/ast.Call + str/float only support one parameter, eg: float(XXX), str(xxx) + int support one or two parameters, eg: int(xxx) or int(xxx, 16) + xxx can be ast.Call/ast.Constant(ast.Num/ast.Str)/ast.BinOp + ''' + calc_tuple = ("float", "int", "str") + + if node.func.id not in calc_tuple: + raise NotImplementedError("Unsupport function call type: %s" % node.func.id) + + args_val_list = [] + for item in node.args: + ret = self.get_op_value(item) + args_val_list.append(ret) + + if node.func.id == "str": + if len(args_val_list) != 1: + raise TypeError("str() takes 1 positional argument but %s were given" % len(args_val_list)) + value = str(args_val_list[0]) + self.value = value + return value + + if node.func.id == "float": + if len(args_val_list) != 1: + raise TypeError("float() takes 1 positional argument but %s were given" % len(args_val_list)) + value = float(args_val_list[0]) + self.value = value + return value + # int + if len(args_val_list) == 1: + value = int(args_val_list[0]) + self.value = value + return value + if len(args_val_list) == 2: + value = int(args_val_list[0], args_val_list[1]) + self.value = value + return value + raise TypeError("int() takes 1 or 2 arguments (%s given)" % len(args_val_list)) + + +class devicebase(object): + _name = None + __error_ret = -99999 + + @property + def name(self): + return self._name + + @name.setter + def name(self, val): + self._name = val + + def dumpValueByI2c(self, bus, loc): + value = "" + for i in range(256): + ret, val = self.get_i2c(bus, loc, i) + value += chr(val) + return value + + def byteTostr(self, val): + strtmp = '' + for value in val: + strtmp += chr(value) + return strtmp + + def get_eeprom_info(self, conf): + eeprom = "" + if conf.get('way') == 'sysfs': + ret, eeprom = self.get_value(conf) + if ret is False: + return None + elif conf.get('way') == 'devfile': + ret, eeprom_list = self.get_value(conf) + if ret is False: + return None + for item in eeprom_list: + eeprom += chr(item) + else: + eeprom = self.dumpValueByI2c(conf.get('bus'), conf.get('addr')) + return eeprom + + def exec_os_cmd(self, cmd): + cmds = cmd.split('|') + procs = [] + for i, c in enumerate(cmds): + stdin = None if i == 0 else procs[i-1].stdout + p = subprocess.Popen(shlex.split(c), stdin=stdin, stdout=subprocess.PIPE, shell=False, stderr=subprocess.STDOUT) + procs.append(p) + for proc in procs: + proc.wait() + return procs[-1].returncode, self.byteTostr(procs[-1].communicate()[0]) + + def get_value(self, config): + ''' + get value by config way + way i2c/sysfs/lpc + ''' + way = config.get("way") + if way == 'sysfs': + return self.get_sysfs(config.get("loc"), config.get("flock_path")) + if way == "i2c": + bus = config.get("bus") + addr = config.get("addr") + offset = config.get("offset") + return self.get_i2c(bus, addr, offset) + if way == "io": + io_addr = config.get('io_addr') + read_len = config.get('read_len', 1) + return self.get_io(io_addr, read_len) + if way == "i2cword": + bus = config.get("bus") + addr = config.get("addr") + offset = config.get("offset") + return self.get_i2cword(bus, addr, offset) + if way == "devmem": + addr = config.get("addr") + digit = config.get("digit") + mask = config.get("mask", None) + return self.get_devmem(addr, digit, mask) + if way == "sdk": + get_type = config.get("type") + if get_type == "bcm_temp": + return self.getbcmtemp() + if get_type == "bcm_reg": + reg = config.get("reg") + return self.getbcmreg(reg) + raise Exception("cannot found sdk type deal") + if way == "devfile": + loc = config.get("loc") + offset = config.get("offset") + length = config.get("len") + ret, val_list = self.devfile_read(loc, offset, length) + if ret is True: + if length == 1: + val = val_list[0] + return True, val + return True, val_list + return False, ("devfile read failed. path:%s, offset:0x%x, read_len:%d" % (loc, offset, length)) + if way == "devfile_ascii": + loc = config.get("loc") + offset = config.get("offset") + length = config.get("len") + return self.devfile_read_ascii(loc, offset, length) + if way == 'cmd': + cmd = config.get("cmd") + ret, log = self.exec_os_cmd(cmd) + if ret: + return False, ("cmd write exec %s failed, log: %s" % (cmd, log)) + return True, log + raise Exception("cannot found way deal") + + def devfile_read(self, loc, offset, length): + return osutil.readdevfile(loc, offset, length) + + def devfile_read_ascii(self, loc, offset, length): + return osutil.readdevfile_ascii(loc, offset, length) + + def get_sysfs(self, loc, flock_path=None): + return self.getsysfs(loc, flock_path) + + def getsysfs(self, loc, flock_path=None): + ret, val = osutil.readsysfs(loc, flock_path) + return ret, val + + def get_devmem(self, addr, digit, mask): + return osutil.getdevmem(addr, digit, mask) + + def get_i2cword(self, bus, addr, offset): + return self.geti2cword(bus, addr, offset) + + def geti2cword(self, bus, addr, offset): + ret, val = osutil.geti2cword(bus, addr, offset) + return ret, val + + def get_io(self, reg_addr, read_len): + return self.getio(reg_addr, read_len) + + def getio(self, reg_addr, read_len): + ret, val = osutil.io_rd(reg_addr, read_len) + return ret, val + + def get_i2c(self, bus, addr, offset): + return self.geti2c(bus, addr, offset) + + def geti2c(self, bus, addr, offset): + ret, val = osutil.wbi2cget(bus, addr, offset) + return ret, val + + def set_value(self, config, val): + ''' + get value by config way + way i2c/sysfs/lpc + ''' + way = config.get("way") + if way == 'sysfs': + return self.set_sysfs(config.get("loc"), "0x%02x" % val) + if way == "i2c": + bus = config.get("bus") + addr = config.get("addr") + offset = config.get("offset") + return self.set_i2c(bus, addr, offset, val) + if way == "i2cpec": + bus = config.get("bus") + addr = config.get("addr") + offset = config.get("offset") + return self.seti2c_byte_pec(bus, addr, offset, val) + if way == 'i2cword': + bus = config.get("bus") + addr = config.get("addr") + offset = config.get("offset") + return self.set_i2cword(bus, addr, offset, val) + if way == "i2cwordpec": + bus = config.get("bus") + addr = config.get("addr") + offset = config.get("offset") + return self.set_i2cwordpec(bus, addr, offset, val) + if way == "devfile": + loc = config.get("loc") + offset = config.get("offset") + return self.devfile_write(loc, offset, val) + return False, "unsupport way: %s" % way + + def set_sysfs(self, loc, value): + return self.setsysfs(loc, value) + + def setsysfs(self, loc, value): + return osutil.writesysfs(loc, value) + + def set_i2cword(self, bus, addr, offset, byte): + return self.seti2cword(bus, addr, offset, byte) + + def seti2cword(self, bus, addr, offset, byte): + return osutil.seti2cword(bus, addr, offset, byte) + + def set_i2cwordpec(self, bus, addr, offset, val): + return osutil.seti2cwordpec(bus, addr, offset, val) + + def seti2c_byte_pec(self, bus, addr, offset, val): + return osutil.seti2c_byte_pec(bus, addr, offset, val) + + def set_i2c(self, bus, addr, offset, byte): + return self.seti2c(bus, addr, offset, byte) + + def seti2c(self, bus, addr, offset, byte): + ret, val = osutil.wbi2cset(bus, addr, offset, byte) + return ret, val + + def devfile_write(self, loc, offset, val): + ret, val = osutil.writedevfile(loc, offset, val) + return ret, val + + def getbcmtemp(self): + try: + sta, ret = osutil.getmactemp() + if sta is True: + mac_aver = float(ret.get("average", self.__error_ret)) + mac_aver = mac_aver * 1000 + else: + return False, ret + except AttributeError as e: + return False, str(e) + return True, mac_aver + + def getbcmreg(self, reg): + ret, val = osutil.getsdkreg(reg) + return ret, val + + def logger_debug(self, msg): + baseutil.logger_debug(msg) + + def command(self, cmd): + ret, output = osutil.command(cmd) + return ret, output + + def get_format_value(self, format_str): + ast_obj = ast.parse(format_str, mode='eval') + visitor = CodeVisitor() + visitor.visit(ast_obj) + ret = visitor.get_value() + return ret diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/fan.py b/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/fan.py new file mode 100644 index 000000000000..8b503bf6418f --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/fan.py @@ -0,0 +1,413 @@ +#!/usr/bin/env python3 +####################################################### +# +# fan.py +# Python implementation of the Class fan +# +####################################################### +from eepromutil.fru import ipmifru +from eepromutil.fantlv import fan_tlv +from plat_hal.devicebase import devicebase +from plat_hal.rotor import rotor + + +class fan(devicebase): + __rotor_list = [] + __pn = None + __raweeprom = None + __sn = None + __hw_version = None + __e2loc = None + __rotors = None + __AirFlow = None + __SpeedMin = None + __SpeedMax = None + __PowerMax = None + __productName = None + __productSerialNumber = None + __WatchdogStatus = None + __led_attrs_config = None + __led_config = None + __WatchdogStatus_config = None + __AirFlowconifg = None + __EnableWatchdogConf = None + __Rotor_config = None + __fan_display_name = None # 'N/A' + __fan_display_name_conifg = None + + def __init__(self, conf=None): + if conf is not None: + self.name = conf.get('name', None) + self.sn = conf.get('sn', None) + self.present = conf.get('present', None) + self.e2loc = conf.get('e2loc', None) + self.SpeedMin = conf.get('SpeedMin', None) + self.SpeedMax = conf.get('SpeedMax', None) + self.PowerMax = conf.get('PowerMax', None) + self.AirFlowconifg = conf.get("airflow", None) + self.WatchdogStatus_config = conf.get('WatchdogStatus', None) + self.EnableWatchdogConf = conf.get('EnableWatchdogConf', None) + self.led_attrs_config = conf.get('led_attrs', None) + self.led_config = conf.get('led', None) + self.Rotor_config = conf.get('Rotor', None) + self.fan_display_name_conifg = conf.get("fan_display_name", None) + rotor_tmp = [] + for value in self.Rotor_config.values(): + rotor_tmp.append(rotor(value)) + rotor_tmp.sort(key=lambda x: x.name, reverse=False) + self.rotor_list = rotor_tmp + self.rotors = len(self.rotor_list) + + @property + def EnableWatchdogConf(self): + return self.__EnableWatchdogConf + + @EnableWatchdogConf.setter + def EnableWatchdogConf(self, val): + self.__EnableWatchdogConf = val + + @property + def rotor_list(self): + return self.__rotor_list + + @rotor_list.setter + def rotor_list(self, val): + self.__rotor_list = val + + @property + def Rotor_config(self): + return self.__Rotor_config + + @Rotor_config.setter + def Rotor_config(self, val): + self.__Rotor_config = val + + @property + def productName(self): + return self.__productName + + @productName.setter + def productName(self, val): + self.__productName = val + + @property + def productSerialNumber(self): + return self.__productSerialNumber + + @productSerialNumber.setter + def productSerialNumber(self, val): + self.__productSerialNumber = val + + @property + def hw_version(self): + return self.__hw_version + + @hw_version.setter + def hw_version(self, val): + self.__hw_version = val + + @property + def sn(self): + return self.__sn + + @sn.setter + def sn(self, val): + self.__sn = val + + @property + def pn(self): + return self.__pn + + @pn.setter + def pn(self, val): + self.__pn = val + + @property + def raweeprom(self): + return self.__raweeprom + + @raweeprom.setter + def raweeprom(self, val): + self.__raweeprom = val + + @property + def SpeedMax(self): + return self.__SpeedMax + + @SpeedMax.setter + def SpeedMax(self, val): + self.__SpeedMax = val + + @property + def SpeedMin(self): + return self.__SpeedMin + + @SpeedMin.setter + def SpeedMin(self, val): + self.__SpeedMin = val + + @property + def PowerMax(self): + return self.__PowerMax + + @PowerMax.setter + def PowerMax(self, val): + self.__PowerMax = val + + @property + def rotors(self): + return self.__rotors + + @property + def AirFlow(self): + return self.__AirFlow + + @AirFlow.setter + def AirFlow(self, val): + self.__AirFlow = val + + @rotors.setter + def rotors(self, val): + self.__rotors = val + + @property + def fan_display_name_conifg(self): + return self.__fan_display_name_conifg + + @fan_display_name_conifg.setter + def fan_display_name_conifg(self, val): + self.__fan_display_name_conifg = val + + @property + def fan_display_name(self): + return self.__fan_display_name + + @fan_display_name.setter + def fan_display_name(self, val): + self.__fan_display_name = val + + def getspeed(self, conf): + tmp = None + if conf is None: + return -1 + ret, val = self.get_value(conf) + if ret is True: + tmp = int(str(val), 10) + else: + val = None + if val is not None: + return int(15000000 / tmp) + return -1 + + def get_speed(self, rotor_index): + rotor_item = self.get_rotor_index(rotor_index) + if rotor_item is None: + return None + speed = rotor_item.rotor_Speed.Value + if speed is None: + return None + return int(speed) + + def set_led(self, color): + status = self.led_attrs_config.get(color, None) + if status is None: + return False + + mask = self.led_attrs_config.get('mask', 0xff) + ret, value = self.get_value(self.led_config) + if ret is False or value is None: + return False + setval = (int(value) & ~mask) | (status) + ret, val = self.set_value(self.led_config, setval) + return ret + + def get_led(self): + mask = self.led_attrs_config.get('mask', 0xff) + ret, value = self.get_value(self.led_config) + if ret is False or value is None: + return False, 'N/A' + ledval = int(value) & mask + for key, val in self.led_attrs_config.items(): + if (ledval == val) and (key != "mask"): + return True, key + return False, 'N/A' + + def set_speed(self, rotor_index, level): + if level > 255 or level < 0: + return False + rotor_item = self.get_rotor_index(rotor_index) + if rotor_item is None: + return False + ret, val = self.set_value(rotor_item.Speedconfig, int(level)) + return ret + + def get_rotor_index(self, rotor_index): + if rotor_index > len(self.rotor_list): + return None + rotor_item = self.rotor_list[rotor_index - 1] + return rotor_item + + def get_rotor_byname(self, rotor_index): + for rotor_item in self.rotor_list: + if rotor_item.name == rotor_index: + return rotor_item + return None + + def get_presence(self): + ret, val = self.get_value(self.present) + if ret is False or val is None: + return -1 + if isinstance(val, str): + value = int(val, 16) + else: + value = val + mask = self.present.get("mask") + flag = value & mask + okval = self.present.get("okval", 0) + if flag == okval: + return True + return False + + def get_speed_pwm(self, rotor_index): + rotor_item = self.get_rotor_index(rotor_index) + if rotor_item is None: + return False + if rotor_item.i2c_speed is None: + return False + val = round(rotor_item.i2c_speed * 100 / 255) + return val + + def feed_watchdog(self): + ret = False + for rotor_item in self.rotor_list: + ret, val = rotor_item.feed_watchdog() + if ret is False: + return ret + return ret + + def get_fru_info(self): + try: + if self.get_presence() is False: + raise Exception("%s: not present" % self.name) + eeprom = self.get_eeprom_info(self.e2loc) + if eeprom is None: + raise Exception("%s: value is none" % self.name) + fru = ipmifru() + if isinstance(eeprom, bytes): + eeprom = self.byteTostr(eeprom) + fru.decodeBin(eeprom) + self.productName = fru.productInfoArea.productName.strip() # PN + self.productSerialNumber = fru.productInfoArea.productSerialNumber.strip() # SN + self.hw_version = fru.productInfoArea.productVersion.strip() # HW + except Exception: + self.productName = None + self.productSerialNumber = None + self.hw_version = None + return False + return True + + def get_tlv_info(self): + try: + if self.get_presence() is False: + raise Exception("%s: not present" % self.name) + eeprom = self.get_eeprom_info(self.e2loc) + if eeprom is None: + raise Exception("%s: value is none" % self.name) + tlv = fan_tlv() + rets = tlv.decode(eeprom) + for item in rets: + if item["name"] == "Product Name": + self.productName = item["value"].replace("\x00", "").strip() + elif item["name"] == "serial Number": + self.productSerialNumber = item["value"].replace("\x00", "").strip() + elif item["name"] == "hardware info": + self.hw_version = item["value"].replace("\x00", "").strip() + except Exception: + self.productName = None + self.productSerialNumber = None + self.hw_version = None + return False + return True + + def decode_eeprom_info(self): + '''get fan name, hw version, sn''' + ret = self.get_tlv_info() + if ret is True: + return ret + return self.get_fru_info() + + def get_AirFlow(self): + if self.productName is None: + ret = self.decode_eeprom_info() + if ret is False: + self.AirFlow = None + return False + if self.AirFlowconifg is None: + self.AirFlow = None + return False + for i in self.AirFlowconifg: + if self.productName in self.AirFlowconifg[i]: + self.AirFlow = i + return True + self.AirFlow = None + return False + + def enable_watchdog(self, enable): + ret = False + if enable is True: + byte = self.EnableWatchdogConf.get("enable_byte", None) + ret, val = self.set_value(self.EnableWatchdogConf, byte) + elif enable is False: + byte = self.EnableWatchdogConf.get("disable_byte", None) + ret, val = self.set_value(self.EnableWatchdogConf, byte) + return ret + + def get_watchdog_status(self): + dic = {"support": None, "open": None, "work_full": None, "work_allow_set": None} + if self.WatchdogStatus_config is None: + return None + ret, val = self.get_value(self.WatchdogStatus_config) + if ret is False or val is None: + return None + support_watchdog_off = self.WatchdogStatus_config.get("support_watchdog_off", None) + is_open_off = self.WatchdogStatus_config.get("is_open_off", None) + full_running_off = self.WatchdogStatus_config.get("full_running_off", None) + running_setting_off = self.WatchdogStatus_config.get("running_setting_off", None) + if support_watchdog_off is not None: + if support_watchdog_off & val == self.WatchdogStatus_config.get("support_watchdog_mask", None): + dic["support"] = True + else: + dic["support"] = False + return dic + if is_open_off is not None: + if is_open_off & val == self.WatchdogStatus_config.get("is_open_mask", None): + dic["open"] = True + else: + dic["open"] = False + if full_running_off is not None: + if full_running_off & val == self.WatchdogStatus_config.get("full_running_mask", None): + dic["work_full"] = True + else: + dic["work_full"] = False + if running_setting_off is not None: + if running_setting_off & val == self.WatchdogStatus_config.get("running_setting_mask", None): + dic["work_allow_set"] = True + else: + dic["work_allow_set"] = False + return dic + + def get_fan_display_name(self): + if self.productName is None: + ret = self.get_fru_info() + if ret is False: + self.fan_display_name = None + return False + if self.fan_display_name_conifg is None: + self.fan_display_name = self.productName + return False + for i in self.fan_display_name_conifg: + if self.productName in self.fan_display_name_conifg[i]: + self.fan_display_name = i + return True + self.fan_display_name = self.productName + return False diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/interface.py b/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/interface.py new file mode 100644 index 000000000000..19c78d640073 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/interface.py @@ -0,0 +1,1324 @@ +#!/usr/bin/env python3 +####################################################### +# +# interface.py +# Python implementation of the Class interface +# +####################################################### +import collections +from plat_hal.chassisbase import chassisbase +from plat_hal.baseutil import baseutil +from plat_hal.osutil import osutil + + +def Singleton(cls): + _instance = {} + + def _singleton(*args, **kargs): + if cls not in _instance: + _instance[cls] = cls(*args, **kargs) + return _instance[cls] + + return _singleton + + +@Singleton +class interface(object): + __chas = None + __error_ret = None + + def __init__(self): + self.chas = chassisbase() + self.__error_ret = -99999 + self.__na_ret = 'N/A' + + @property + def na_ret(self): + return self.__na_ret + + @na_ret.setter + def na_ret(self, val): + self.__na_ret = val + + @property + def error_ret(self): + return self.__error_ret + + @error_ret.setter + def error_ret(self, val): + self.__error_ret = val + + @property + def chas(self): + return self.__chas + + @chas.setter + def chas(self, val): + self.__chas = val + + # onie_e2 + def get_onie_e2(self): + onie_e2_list = self.chas.onie_e2_list + return onie_e2_list + + def get_onie_e2_path(self, name): + onie_e2 = self.chas.get_onie_e2_byname(name) + if onie_e2 is None: + return None + return onie_e2.e2_path + + def get_device_airflow(self, name): + onie_e2 = self.chas.get_onie_e2_byname(name) + if onie_e2 is None: + return None + return onie_e2.airflow + + def get_onie_e2_obj(self, name): + onie_e2 = self.chas.get_onie_e2_byname(name) + if onie_e2 is None: + return None + onie_e2.get_onie_e2_info() + return onie_e2 + + # temp + def get_temps(self): + templist = self.chas.temp_list + return templist + + def get_temp_total_number(self): + templist = self.chas.temp_list + return len(templist) + + def check_temp_id_exist(self, temp_id): + templist = self.chas.temp_list + for temp in templist: + if temp.temp_id == temp_id: + return True + return False + + def get_temp_id_number(self): + templist = self.chas.temp_list + temp_num = 0 + for i in range(len(templist)): + temp_id = "TEMP" + str(i + 1) + ret = self.check_temp_id_exist(temp_id) + if ret is True: + temp_num = temp_num + 1 + else: + return temp_num + return temp_num + + def get_temp_location(self, temp_name): + temp = self.chas.get_temp_byname(temp_name) + return temp.get_location() + + def set_temp_location(self, temp_name, location): + temp = self.chas.get_temp_byname(temp_name) + return temp.set_location(location) + + def set_temp_name(self, temp_name, name): + temp = self.chas.get_temp_byname(temp_name) + return temp.set_name(name) + + def get_appoint_temp(self, temp_name): + temp = self.chas.get_led_byname(temp_name) + return temp.get_temp() + + def set_appoint_temp(self, temp_name, val): + temp = self.chas.get_temp_byname(temp_name) + return temp.set_temp(val) + + def get_temp_mintemp(self, temp_name): + temp = self.chas.get_temp_byname(temp_name) + return temp.get_mintemp() + + def set_temp_mintemp(self, temp_name, val): + temp = self.chas.get_temp_byname(temp_name) + return temp.set_mintemp(val) + + # led + def get_leds(self): + ledlist = self.chas.led_list + return ledlist + + def get_led_total_number(self): + ledlist = self.chas.led_list + return len(ledlist) + + def get_led_color(self, led_name): + led = self.chas.get_led_byname(led_name) + if led is None: + return -1 + return led.get_color() + + def get_led_color_by_type(self, led_type): + ledlist = self.chas.led_list + ledtmp = None + for temp in ledlist: + if temp.led_type == led_type: + ledtmp = temp + break + if ledtmp is None: + return -1 + return ledtmp.get_color() + + def set_led_color(self, led_name, color): + led = self.chas.get_led_byname(led_name) + if led is None: + return -1 + return led.set_color(color) + + # psu + def get_psu_total_number(self): + psulist = self.chas.psu_list + if psulist is None: + return -1 + return len(psulist) + + def get_psus(self): + psulist = self.chas.psu_list + return psulist + + def get_psu_presence(self, psu_name): + psu = self.chas.get_psu_byname(psu_name) + if psu is None: + return -1 + return psu.present + + def get_psu_fru_info(self, psu_name): + ''' + { + "Name": "PSU1", + "SN": "serial_number_example", # 'N/A' + "PN": "part_number_example", # 'N/A' + "AirFlow": "B2F" # 'N/A' + } + ''' + psu = self.chas.get_psu_byname(psu_name) + if psu is None: + return -1 + psu.get_fru_info() + psu.get_AirFlow() + psu.get_psu_display_name() + + dic = collections.OrderedDict() + dic["Name"] = psu.name + dic["SN"] = psu.productSerialNumber if (psu.productSerialNumber is not None) else self.na_ret + dic["PN"] = psu.productPartModelName if (psu.productPartModelName is not None) else self.na_ret + dic["DisplayName"] = psu.psu_display_name if (psu.psu_display_name is not None) else self.na_ret + dic["VENDOR"] = psu.productManufacturer if (psu.productManufacturer is not None) else self.na_ret + dic["HW"] = psu.productVersion if (psu.productVersion is not None) else self.na_ret + dic["AirFlow"] = psu.AirFlow if (psu.AirFlow is not None) else self.na_ret + return dic + + def get_psu_input_output_status(self, psu_name): + psu = self.chas.get_psu_byname(psu_name) + if psu is None: + return -1 + psu.InputsCurrent.Value # just for clear faults + if (psu.InputStatus is True) and (psu.OutputStatus is True): + return True + return False + + def get_psu_status(self, psu_name): + """ + Get status of a specific PSU + @return dict of the specific PSU's status, None for failure + Example return value(all keys are mandatory) + { + "Name": "PSU1", + "InputType": "DC", # "AC" or 'N/A' + "InputStatus": True, # H/W status bit + "OutputStatus": True # H/W status bit + "FanSpeed": { + "Value": 4000, # -99999 + "Min": 2000, # -99999 + "Max": 10000 # -99999 + }, + "Temperature": { + "Value": 40.0, # -99999.0 + "Min": -30.0, # -99999.0 + "Max": 50.0 # -99999.0 + } + } + """ + psu = self.chas.get_psu_byname(psu_name) + if psu is None: + return -1 + + dic = collections.OrderedDict() + # psu.get_Temperature() + temp_dict = collections.OrderedDict() + temp_dict['Min'] = psu.Temperature.Min + temp_dict['Max'] = psu.Temperature.Max + temp_dict['Value'] = psu.Temperature.Value + temp_dict['Unit'] = psu.Temperature.Unit + dic["Temperature"] = temp_dict + + # psu.get_FanSpeed() + fan_speed_dict = collections.OrderedDict() + fan_speed_dict['Min'] = psu.FanSpeed.Min + fan_speed_dict['Max'] = psu.FanSpeed.Max + fan_speed_dict['Tolerance'] = psu.FanSpeedTolerance + fan_speed_dict['Value'] = psu.FanSpeed.Value + fan_speed_dict['Unit'] = psu.FanSpeed.Unit + dic["FanSpeed"] = fan_speed_dict + + dic["Name"] = psu.name + dic["InputType"] = psu.InputsType + dic["InputStatus"] = psu.InputStatus + dic["OutputStatus"] = psu.OutputStatus + dic["TempStatus"] = psu.TempStatus + dic["FanStatus"] = psu.FanStatus + return dic + + def get_psu_power_status(self, psu_name): + """ + Get power status of a specific PSU + @return dict of the specific PSU's power status, None for failure + Example return value + { + "Name": "PSU1", + "Inputs": { + "Status": True, # H/W status bit + "Type": "DC", # or "AC" or "N/A" + "Voltage": { + "Value": 220, # -1 + "LowAlarm": 200, # -1 + "HighAlarm": 240, # -1 + "Unit": "V" + }, + "Current": { + "Value": 6.0, # -99999.0 + "LowAlarm": 0.2, # -99999.0 + "HighAlarm": 7.0, # -99999.0 + "Unit": "A" + }, + "Power": { + "Value": 1000, # -99999 + "LowAlarm": -1, # -99999 + "HighAlarm": 1400, # -99999 + "Unit": "W" + } + }, + "Outputs": { + "Status": True, + "Voltage": { + "Value": 220, + "LowAlarm": 200, + "HighAlarm": 240, + "Unit": "V" + }, + "Current": { + "Value": 6.0, + "LowAlarm": 0.2, + "HighAlarm": 7.0, + "Unit": "A" + }, + "Power": { + "Value": 1000, + "LowAlarm": -1, # Don't care + "HighAlarm": 1400, + "Unit": "W" + } + } + } + """ + psu = self.chas.get_psu_byname(psu_name) + if psu is None: + return -1 + + dic = collections.OrderedDict() + inputdic = collections.OrderedDict() + Outputsdic = collections.OrderedDict() + dic["Name"] = psu.name + inputdic["Status"] = psu.InputStatus + inputdic["Type"] = psu.InputsType + + # psu.get_InputsVoltage() + inputdic_voltage = collections.OrderedDict() + + inputdic_voltage["Value"] = psu.InputsVoltage.Value + inputdic_voltage["LowAlarm"] = psu.InputsVoltage.Min + inputdic_voltage["HighAlarm"] = psu.InputsVoltage.Max + inputdic_voltage["Unit"] = psu.InputsVoltage.Unit + + inputdic["Voltage"] = inputdic_voltage + inputdic_current = collections.OrderedDict() + inputdic_current["Value"] = psu.InputsCurrent.Value + inputdic_current["LowAlarm"] = psu.InputsCurrent.Min + inputdic_current["HighAlarm"] = psu.InputsCurrent.Max + inputdic_current["Unit"] = psu.InputsCurrent.Unit + inputdic["Current"] = inputdic_current + + inputdic_power = collections.OrderedDict() + inputdic_power["Value"] = psu.InputsPower.Value + inputdic_power["LowAlarm"] = psu.InputsPower.Min + inputdic_power["HighAlarm"] = psu.InputsPower.Max + inputdic_power["Unit"] = psu.InputsPower.Unit + inputdic["Power"] = inputdic_power + Outputsdic["Status"] = psu.InputStatus + + outputdic_voltage = collections.OrderedDict() + outputdic_current = collections.OrderedDict() + outputdic_power = collections.OrderedDict() + + outputdic_voltage["Value"] = psu.OutputsVoltage.Value + outputdic_voltage["LowAlarm"] = psu.OutputsVoltage.Min + outputdic_voltage["HighAlarm"] = psu.OutputsVoltage.Max + outputdic_voltage["Unit"] = psu.OutputsVoltage.Unit + + outputdic_current["Value"] = psu.OutputsCurrent.Value + outputdic_current["LowAlarm"] = psu.OutputsCurrent.Min + outputdic_current["HighAlarm"] = psu.OutputsCurrent.Max + outputdic_current["Unit"] = psu.OutputsCurrent.Unit + + outputdic_power["Value"] = psu.OutputsPower.Value + outputdic_power["LowAlarm"] = psu.OutputsPower.Min + outputdic_power["HighAlarm"] = psu.OutputsPower.Max + outputdic_power["Unit"] = psu.OutputsPower.Unit + + Outputsdic["Voltage"] = outputdic_voltage + Outputsdic["Current"] = outputdic_current + Outputsdic["Power"] = outputdic_power + + dic["Inputs"] = inputdic + dic["Outputs"] = Outputsdic + + return dic + + def set_psu_fan_speed_pwm(self, psu_name, pwm): + psu = self.chas.get_psu_byname(psu_name) + if psu is None: + return -1 + return psu.set_fan_speed_pwm(pwm) + + def get_psu_fan_speed_pwm(self, psu_name): + psu = self.chas.get_psu_byname(psu_name) + if psu is None: + return -1 + return psu.get_fan_speed_pwm() + + def get_psu_info_all(self): + """ + { + "Number": 2, + "PSU1": { + "SN": "serial_number_example", # 'N/A' + "PN": "part_number_example", # 'N/A' + "AirFlow": "intake", # 'N/A' + + "FanSpeed": { + "Value": 4000, + "Min": 2000, + "Max": 30000 + }, + "Temperature": { + "Value": 35.0, + "Min": -20.0, + "Max": 45.0 + }, + "Inputs": { + "Status": True, # H/W status bit + "Type": "DC", # or "AC" + "Voltage": { + "Value": 220, + "LowAlarm": 200, + "HighAlarm": 240, + "Unit": "V" + }, + "Current": { + "Value": 6.0, + "LowAlarm": 0.2, + "HighAlarm": 7.0, + "Unit": "A" + }, + "Power": { + "Value": 1000, + "LowAlarm": -1, + "HighAlarm": 1400, + "Unit": "W" + } + }, + "Outputs": { + "Status": True, + "Voltage": { + "Value": 220, + "LowAlarm": 200, + "HighAlarm": 240, + "Unit": "V" + }, + "Current": { + "Value": 6.0, + "LowAlarm": 0.2, + "HighAlarm": 7.0, + "Unit": "A" + }, + "Power": { + "Value": 1000, + "LowAlarm": -1, # Don't care + "HighAlarm": 1400, + "Unit": "W" + } + } + } + } + """ + + psus = self.get_psus() + psu_dict = collections.OrderedDict() + psu_dict['Number'] = len(psus) + for psu in psus: + dicttmp = self.get_psu_fru_info(psu.name) + dicttmp.update(self.get_psu_status(psu.name)) + dicttmp.update(self.get_psu_power_status(psu.name)) + if self.get_psu_presence(psu.name) is True: + dicttmp['Present'] = 'yes' + else: + dicttmp['Present'] = 'no' + psu_dict[psu.name] = dicttmp + return psu_dict + + def get_fans(self): + fanlist = self.chas.fan_list + return fanlist + + # fan + def get_fan_total_number(self): + fanlist = self.chas.fan_list + if fanlist is None: + return -1 + return len(fanlist) + + def get_fan_rotor_number(self, fan_name): + fan = self.chas.get_fan_byname(fan_name) + if fan is None: + return -1 + ret = fan.rotors + if ret is None: + return -1 + return ret + + def get_fan_speed(self, fan_name, rotor_index): + fan = self.chas.get_fan_byname(fan_name) + if fan is None: + return -1 + ret = fan.get_speed(rotor_index) + if ret is None: + return -1 + return ret + + def fan_speed_set_level(self, fan_name, rotor_index, level): + fan = self.chas.get_fan_byname(fan_name) + if fan is None: + return -1 + ret = fan.set_speed(rotor_index, level) + if ret is True: + return 0 + return -1 + + def get_fan_speed_pwm(self, fan_name, rotor_index): + fan = self.chas.get_fan_byname(fan_name) + if fan is None: + return -1 + val = fan.get_speed_pwm(rotor_index) + if val is False: + return -1 + return val + + def set_fan_speed_pwm(self, fan_name, rotor_index, pwm): + fan = self.chas.get_fan_byname(fan_name) + if fan is None: + return -1 + if isinstance(pwm, str): + rate = float(pwm.strip('%s')) + speed = round(rate * 255 / 100) + elif isinstance(pwm, int): + speed = round(pwm * 255 / 100) + elif isinstance(pwm, float): + speed = round(pwm * 255 / 100) + else: + return -1 + ret = self.fan_speed_set_level(fan.name, rotor_index, speed) + if ret == 0: + return 0 + return -1 + + def get_fan_watchdog_status(self): + fan = self.chas.fan_list[0] + dic = fan.get_watchdog_status() + if dic is None or dic["support"] is False: + return self.na_ret + if dic["open"] is False or dic["work_allow_set"] is True: + return "Normal" + if dic["work_full"] is True: + return "Abnormal" + return "Abnormal" + + def enable_fan_watchdog(self, enable=True): + fan = self.chas.fan_list[0] + ret = fan.enable_watchdog(enable) + if ret is True: + return 0 + return -1 + + def feed_fan_watchdog(self): + fan_list = self.chas.fan_list + if fan_list is None: + return -1 + for fan in fan_list: + ret = fan.feed_watchdog() + if ret is False: + return -1 + return 0 + + def set_fan_led(self, fan_name, color): + fan = self.chas.get_fan_byname(fan_name) + if fan is None: + return -1 + ret = fan.set_led(color) + if ret is True: + return 0 + return -1 + + def get_fan_led(self, fan_name): + fan = self.chas.get_fan_byname(fan_name) + if fan is None: + return False, 'N/A' + return fan.get_led() + + def get_fan_presence(self, fan_name): + fan = self.chas.get_fan_byname(fan_name) + if fan is None: + return -1 + return fan.get_presence() + + def get_fan_fru_info(self, fan_name): + """ + Get specific fan's information + # Properties + "Name": "FAN1", + "SN": "serial_number_example", # 'N/A' + "PN": "part_number_exampple", # 'N/A' + "Rotors": 2, # -1 + "AirFlow": "intake", # 'N/A' + "SpeedMin": 2000, # -1 + "SpeedMax": 30000 # -1 + """ + fan = self.chas.get_fan_byname(fan_name) + fan.get_fru_info() + fan.get_AirFlow() + fan.get_fan_display_name() + + dic = collections.OrderedDict() + dic["Name"] = fan.name + dic["SN"] = fan.productSerialNumber + if dic["SN"] is None: + dic["SN"] = self.na_ret + dic["PN"] = fan.productName + if dic["PN"] is None: + dic["PN"] = self.na_ret + dic["DisplayName"] = fan.fan_display_name + if dic["DisplayName"] is None: + dic["DisplayName"] = self.na_ret + + dic["Rotors"] = fan.rotors + dic["AirFlow"] = fan.AirFlow + if dic["AirFlow"] is None: + dic["AirFlow"] = self.na_ret + dic["SpeedMin"] = fan.SpeedMin + dic["SpeedMax"] = fan.SpeedMax + return dic + + def get_fan_eeprom_info(self, fan_name): + """ + Get specific fan's information + # Properties + "Name": "M6510-FAN-F", # 'N/A' + "SN": "serial_number_example", # 'N/A' + "HW": "hw_version_exampple", # 'N/A' + """ + fan = self.chas.get_fan_byname(fan_name) + fan.decode_eeprom_info() + dic = collections.OrderedDict() + dic["NAME"] = fan.productName + if dic["NAME"] is None: + dic["NAME"] = self.na_ret + dic["SN"] = fan.productSerialNumber + if dic["SN"] is None: + dic["SN"] = self.na_ret + dic["HW"] = fan.hw_version + if dic["HW"] is None: + dic["HW"] = self.na_ret + + return dic + + def get_product_fullname(self): + return baseutil.get_product_fullname() + + def get_fan_status(self, fan_name): + fan = self.chas.get_fan_byname(fan_name) + if fan is None: + return -1 + rotorlist = fan.rotor_list + dic = collections.OrderedDict() + for rotor in rotorlist: + dic_val = collections.OrderedDict() + if rotor.rotor_Running is True: + dic_val['Running'] = 'yes' + else: + dic_val['Running'] = 'no' + if rotor.rotor_HwAlarm is True: + dic_val['HwAlarm'] = 'yes' + else: + dic_val['HwAlarm'] = 'no' + dic_val['Speed'] = int(rotor.rotor_Speed.Value) + dic[rotor.name] = dic_val + return dic + + def get_fan_rotor_status(self, fan_name, rotor_name): + fan = self.chas.get_fan_byname(fan_name) + if fan is None: + return -1 + rotorlist = fan.rotor_list + for rotor in rotorlist: + if rotor_name == rotor.name: + if rotor.rotor_Running is True: + return True + return False + return -1 + + def get_fan_roll_status(self, fan_name, rotor_index): + fan = self.chas.get_fan_byname(fan_name) + if fan is None: + return -1 + rotor = fan.get_rotor_index(rotor_index) + if rotor is None: + return -1 + if rotor.rotor_Running is True: + return True + return False + + def get_fan_info_fru(self, fan_name): + fan = self.chas.get_fan_byname(fan_name) + fan.get_fru_info() + fan.get_AirFlow() + dic = collections.OrderedDict() + dic["Name"] = fan.name + dic["SN"] = fan.productSerialNumber + if dic["SN"] is None: + dic["SN"] = self.na_ret + dic["PN"] = fan.productPartModelName + if dic["PN"] is None: + dic["PN"] = self.na_ret + flag = self.get_fan_presence(fan_name) + if flag is True: + dic["Present"] = "yes" + elif flag is False: + dic["Present"] = "no" + else: + dic["Present"] = self.na_ret + dic["Rotors"] = fan.rotors + dic["AirFlow"] = fan.AirFlow + if dic["AirFlow"] is None: + dic["AirFlow"] = self.na_ret + return dic + + # support TLV and FRU FAN E2 + def get_fan_info(self, fan_name): + fan = self.chas.get_fan_byname(fan_name) + if fan is None: + return None + fan.get_AirFlow() + dic = self.get_fan_eeprom_info(fan_name) + flag = self.get_fan_presence(fan_name) + if flag is True: + dic["Present"] = "yes" + elif flag is False: + dic["Present"] = "no" + else: + dic["Present"] = self.na_ret + dic["Rotors"] = fan.rotors + dic["AirFlow"] = fan.AirFlow + if dic["AirFlow"] is None: + dic["AirFlow"] = self.na_ret + dic["PowerMax"] = fan.PowerMax + if dic["PowerMax"] is None: + dic["PowerMax"] = self.na_ret + return dic + + def get_fan_info_rotor(self, fan_name): + fan = self.chas.get_fan_byname(fan_name) + if fan is None: + return -1 + rotorlist = fan.rotor_list + dic = collections.OrderedDict() + for rotor in rotorlist: + dic_val = collections.OrderedDict() + if rotor.rotor_Running is True: + dic_val['Running'] = 'yes' + else: + dic_val['Running'] = 'no' + if rotor.rotor_HwAlarm is True: + dic_val['HwAlarm'] = 'yes' + else: + dic_val['HwAlarm'] = 'no' + speed_value = rotor.rotor_Speed.Value + if speed_value is None: + dic_val['Speed'] = self.error_ret + else: + dic_val['Speed'] = int(speed_value) + if rotor.SpeedMin is None: + dic_val['SpeedMin'] = self.error_ret + else: + dic_val['SpeedMin'] = rotor.SpeedMin + if rotor.SpeedMax is None: + dic_val['SpeedMax'] = self.error_ret + else: + dic_val['SpeedMax'] = rotor.SpeedMax + if rotor.Tolerance is None: + dic_val['Tolerance'] = self.error_ret + else: + dic_val['Tolerance'] = rotor.Tolerance + + dic[rotor.name] = dic_val + return dic + + def get_fan_info_all(self): + fanlist = self.chas.fan_list + dic = collections.OrderedDict() + dic['Number'] = len(fanlist) + dic['WatchdogStatus'] = self.get_fan_watchdog_status() + for fan in fanlist: + dic[fan.name] = self.get_fan_info(fan.name) + dic[fan.name].update(self.get_fan_info_rotor(fan.name)) + return dic + + def temp_test(self): + templist = self.chas.temp_list + dicret = collections.OrderedDict() + + for temp in templist: + dic = collections.OrderedDict() + temp_value = temp.Value + dic["Value"] = temp_value if (temp_value is not None) else self.error_ret + dic["LowAlarm"] = temp.Min + dic["HighAlarm"] = temp.Max + dicret[temp.name] = dic + return dicret + + # dcdc + def get_dcdc_total_number(self): + dcdclist = self.chas.dcdc_list + if dcdclist is None: + return -1 + return len(dcdclist) + + def get_dcdc_by_id(self, dcdc_id): + dcdclist = self.chas.dcdc_list + dcdctmp = None + for dcdc in dcdclist: + if dcdc.dcdc_id == dcdc_id: + dcdctmp = dcdc + dic = collections.OrderedDict() + if dcdctmp is None: + dic["Name"] = self.error_ret + dic["Min"] = self.error_ret + dic["Max"] = self.error_ret + dic["Low"] = self.error_ret + dic["High"] = self.error_ret + dic["Value"] = self.error_ret + dic["Unit"] = self.error_ret + else: + dic["Name"] = dcdctmp.name + dic["Min"] = dcdctmp.sensor.Min + dic["Max"] = dcdctmp.sensor.Max + dic["Low"] = dcdctmp.sensor.Low + dic["High"] = dcdctmp.sensor.High + tmp = dcdctmp.sensor.Value + if tmp is not None: + dic['Value'] = tmp + else: + dic['Value'] = self.error_ret + dic["Unit"] = dcdctmp.sensor.Unit + return dic + + def get_dcdc_all_info(self): + val_list = collections.OrderedDict() + dcdclist = self.chas.dcdc_list + for dcdc in dcdclist: + dicttmp = {} + sensorname = "%s" % (dcdc.name) + dicttmp['Min'] = dcdc.sensor.Min + dicttmp['Max'] = dcdc.sensor.Max + tmp = dcdc.sensor.Value + if tmp is not None: + dicttmp['Value'] = tmp + else: + dicttmp['Value'] = self.error_ret + dicttmp['Unit'] = dcdc.sensor.Unit + val_list[sensorname] = dicttmp + return val_list + + # sensors + def get_monitor_temp(self, name): + templist = self.chas.temp_list + temptmp = None + for temp in templist: + if temp.name == name: + temptmp = temp + + dic = collections.OrderedDict() + if temptmp is None: + dic["Min"] = self.error_ret + dic["Max"] = self.error_ret + dic["Value"] = self.error_ret + dic["Unit"] = self.error_ret + else: + dic["Min"] = temptmp.Min + dic["Max"] = temptmp.Max + temp_value = temptmp.Value + dic["Value"] = temp_value if (temp_value is not None) else self.error_ret + dic["Unit"] = temptmp.Unit + return dic + + def get_monitor_temp_by_id(self, temp_id): + templist = self.chas.temp_list + temptmp = None + for temp in templist: + if temp.temp_id == temp_id: + temptmp = temp + + dic = collections.OrderedDict() + if temptmp is None: + dic["Name"] = self.error_ret + dic["Api_name"] = self.error_ret + dic["Min"] = self.error_ret + dic["Max"] = self.error_ret + dic["Low"] = self.error_ret + dic["High"] = self.error_ret + dic["Value"] = self.error_ret + dic["Unit"] = self.error_ret + else: + dic["Name"] = temptmp.name + dic["Api_name"] = temptmp.api_name + dic["Min"] = temptmp.Min + dic["Max"] = temptmp.Max + dic["Low"] = temptmp.Low + dic["High"] = temptmp.High + temp_value = temptmp.Value + dic["Value"] = temp_value if (temp_value is not None) else self.error_ret + dic["Unit"] = temptmp.Unit + return dic + + def get_temp_info(self): + val_list = collections.OrderedDict() + # temp + templist = self.chas.temp_list + for temp in templist: + dic = collections.OrderedDict() + dic["Min"] = temp.Min + dic["Max"] = temp.Max + dic["Low"] = temp.Low + dic["High"] = temp.High + temp_value = temp.Value + dic["Value"] = temp_value if (temp_value is not None) else self.error_ret + dic["Unit"] = temp.Unit + val_list[temp.name] = dic + return val_list + + def get_sensor_info(self): + val_list = collections.OrderedDict() + # temp + templist = self.chas.temp_list + for temp in templist: + dic = collections.OrderedDict() + dic["Min"] = temp.Min + dic["Max"] = temp.Max + dic["Low"] = temp.Low + dic["High"] = temp.High + temp_value = temp.Value + dic["Value"] = temp_value if (temp_value is not None) else self.error_ret + dic["Unit"] = temp.Unit + val_list[temp.name] = dic + # fan + fanlist = self.chas.fan_list + for fan in fanlist: + for rotor in fan.rotor_list: + sensorname = "%s%s" % (fan.name, rotor.name) + speed = collections.OrderedDict() + speed['Min'] = rotor.rotor_Speed.Min + speed['Max'] = rotor.rotor_Speed.Max + rotor_speed_Value = rotor.rotor_Speed.Value + speed['Value'] = rotor_speed_Value if (rotor_speed_Value is not None) else self.error_ret + speed['Unit'] = rotor.rotor_Speed.Unit + val_list[sensorname] = speed + + val_list.update(self.get_dcdc_all_info()) + + # psu + psulist = self.chas.psu_list + for psu in psulist: + inputdic_voltage = collections.OrderedDict() + inputdic_current = collections.OrderedDict() + inputdic_power = collections.OrderedDict() + outputdic_voltage = collections.OrderedDict() + outputdic_current = collections.OrderedDict() + outputdic_power = collections.OrderedDict() + temperature = collections.OrderedDict() + fanspeed = collections.OrderedDict() + + psu_temp_value = psu.Temperature.Value + temperature["Value"] = psu_temp_value if (psu_temp_value is not None) else self.error_ret + temperature["Min"] = psu.Temperature.Min + temperature["Max"] = psu.Temperature.Max + temperature["Unit"] = psu.Temperature.Unit + + fanspeed["Value"] = psu.FanSpeed.Value + fanspeed["Min"] = psu.FanSpeed.Min + fanspeed["Max"] = psu.FanSpeed.Max + fanspeed["Unit"] = psu.FanSpeed.Unit + + psu_inputvoltage_value = psu.InputsVoltage.Value + inputdic_voltage["Value"] = psu_inputvoltage_value if ( + psu_inputvoltage_value is not None) else self.error_ret + inputdic_voltage["Min"] = psu.InputsVoltage.Min + inputdic_voltage["Max"] = psu.InputsVoltage.Max + inputdic_voltage["Unit"] = psu.InputsVoltage.Unit + + psu_inputcurrent_value = psu.InputsCurrent.Value + inputdic_current["Value"] = psu_inputcurrent_value if ( + psu_inputcurrent_value is not None) else self.error_ret + inputdic_current["Min"] = psu.InputsCurrent.Min + inputdic_current["Max"] = psu.InputsCurrent.Max + inputdic_current["Unit"] = psu.InputsCurrent.Unit + + psu_inputpower_value = psu.InputsPower.Value + inputdic_power["Value"] = psu_inputpower_value if (psu_inputpower_value is not None) else self.error_ret + inputdic_power["Min"] = psu.InputsPower.Min + inputdic_power["Max"] = psu.InputsPower.Max + inputdic_power["Unit"] = psu.InputsPower.Unit + + psu_outputvoltage_value = psu.OutputsVoltage.Value + outputdic_voltage["Value"] = psu_outputvoltage_value if ( + psu_outputvoltage_value is not None) else self.error_ret + outputdic_voltage["Min"] = psu.OutputsVoltage.Min + outputdic_voltage["Max"] = psu.OutputsVoltage.Max + outputdic_voltage["Unit"] = psu.OutputsVoltage.Unit + + psu_outputcurrent_value = psu.OutputsCurrent.Value + outputdic_current["Value"] = psu_outputcurrent_value if ( + psu_outputcurrent_value is not None) else self.error_ret + outputdic_current["Min"] = psu.OutputsCurrent.Min + outputdic_current["Max"] = psu.OutputsCurrent.Max + outputdic_current["Unit"] = psu.OutputsCurrent.Unit + + psu_outputpower_value = psu.OutputsPower.Value + outputdic_power["Value"] = psu_outputpower_value if ( + psu_outputpower_value is not None) else self.error_ret + outputdic_power["Min"] = psu.OutputsPower.Min + outputdic_power["Max"] = psu.OutputsPower.Max + outputdic_power["Unit"] = psu.OutputsPower.Unit + + val_list["%s%s" % (psu.name, "Vol_I")] = inputdic_voltage + val_list["%s%s" % (psu.name, "Curr_I")] = inputdic_current + val_list["%s%s" % (psu.name, "Power_I")] = inputdic_power + val_list["%s%s" % (psu.name, "Vol_O")] = outputdic_voltage + val_list["%s%s" % (psu.name, "Curr_O")] = outputdic_current + val_list["%s%s" % (psu.name, "Power_O")] = outputdic_power + val_list["%s%s" % (psu.name, "Fan")] = fanspeed + val_list["%s%s" % (psu.name, "Temp")] = temperature + + return val_list + + # cpld + def get_cpld_total_number(self): + cpldlist = self.chas.cpld_list + return len(cpldlist) + + def get_cpld_user_reg(self): + cpld = self.chas.get_cpld_byname("BASE_CPLD") + if cpld is None: + return None + return cpld.get_user_reg() + + def set_cpld_user_reg(self, value): + if isinstance(value, int) is False: + baseutil.logger_debug("value must int %s" % type(value)) + return -1 + if (int(value) < 0 or int(value) > 255): + baseutil.logger_debug("value must [0 - 255]") + return -1 + cpld = self.chas.get_cpld_byname("BASE_CPLD") + if cpld is None: + baseutil.logger_debug("name BASE_CPLD not find") + return -1 + if cpld.set_user_reg(value) is True: + return 0 + return -1 + + def set_cpld_console_owner(self, owner): + """ + Set console I/O owner + + @param owner I/O owner of the console, either "cpu" or "bmc" + + @return 0 for success, -1 for failure + """ + if owner is None: + baseutil.logger_debug("owner is None") + return -1 + owner_tuple = ("cpu", "bmc") + if owner not in owner_tuple: + baseutil.logger_debug("owner is %s, must cpu or bmc" % owner) + return -1 + cpld = self.chas.get_cpld_byname("BASE_CPLD") + if cpld is None: + baseutil.logger_debug("name BASE_CPLD not find") + return -1 + if cpld.set_console_owner(owner) is True: + return 0 + return -1 + + def get_cpld_version_by_id(self, cpld_id): + cpldlist = self.chas.cpld_list + cpldtmp = None + for cpld in cpldlist: + if cpld.cpld_id == cpld_id: + cpldtmp = cpld + + dic = collections.OrderedDict() + if cpldtmp is None: + dic["Name"] = self.na_ret + dic["Version"] = self.na_ret + dic["Desc"] = self.na_ret + dic["Slot"] = None + dic["Warm"] = None + else: + dic["Name"] = cpldtmp.name + dic["Version"] = cpldtmp.get_version() + dic["Desc"] = cpldtmp.desc + dic["Slot"] = cpldtmp.slot + dic["Warm"] = cpldtmp.warm + return dic + + def get_cpld_all_version(self): + """ + Get version of all CPLDs' that can be read from BMC + + @return dict of CPLDs' version or None for failure. + example outputs: + { + "BASE_CPLD": "0.1", # or "N/A" for read failure + "FAN_CPLD": "0.2" + } + """ + cpld_version = { + "BASE_CPLD": "N/A", + "FAN_CPLD": "N/A" + } + for cpld_name in cpld_version: + cpld = self.chas.get_cpld_byname(cpld_name) + if cpld is None: + baseutil.logger_debug("name %s not find" % cpld_name) + continue + cpld_version[cpld_name] = cpld.get_version() + return cpld_version + + # comp + def get_comp_total_number(self): + complist = self.chas.comp_list + return len(complist) + + def get_comp_list(self): + return self.chas.comp_list + + def get_comp_id(self, comp): + return comp.comp_id + + def get_comp_version_by_id(self, comp_id): + comp_list = self.chas.comp_list + comptmp = None + for comp in comp_list: + if comp.comp_id == comp_id: + comptmp = comp + break + + dic = collections.OrderedDict() + if comptmp is None: + dic["Name"] = self.na_ret + dic["Version"] = self.na_ret + dic["Desc"] = self.na_ret + dic["Slot"] = None + else: + dic["Name"] = comptmp.name + dic["Version"] = comptmp.get_version() + dic["Desc"] = comptmp.desc + dic["Slot"] = comptmp.slot + return dic + + def get_bmc_productname(self): + """ + Get product name + + @return product name string, e.g. $(device name)-F-$(VENDOR_NAME), if error return "N/A" + """ + bmc = self.chas.get_bmc_byname("master") + if bmc is None: + baseutil.logger_debug("name bmc(master) not find") + return self.na_ret + return bmc.get_productname() + + def call_bmc_diagcmd(self, cmdstr): + """ + Call BMC diag comman func + + @return ret: 0 sucess , -1 fail + outmsg: if success is out msg, or fail is err msg + """ + if (cmdstr is None or cmdstr == ""): + outmsg = "cmdstr is empty" + baseutil.logger_debug(outmsg) + return -1, outmsg + bmc = self.chas.get_bmc_byname("master") + if bmc is None: + outmsg = "name bmc(master) not find" + baseutil.logger_debug(outmsg) + return -1, outmsg + baseutil.logger_debug("call cmdstr %s" % cmdstr) + return bmc.call_diagcmd(cmdstr) + + def write_bios_version(self, flash, version): + bios = self.chas.get_bios_byname("master") + if bios is None: + baseutil.logger_debug("name bios(master) not find") + return -1 + return bios.set_bios_version(flash, version) + + def get_bios_version(self): + bios = self.chas.get_bios_byname("master") + if bios is None: + baseutil.logger_debug("name bios(master) not find") + return -1 + return bios.get_bios_version() + + def get_bios_status(self): + bios = self.chas.get_bios_byname("master") + if bios is None: + baseutil.logger_debug("name bios(master) not find") + return -1 + return bios.get_bios_boot_status() + + def get_bmc_mac_rov(self): + """ + Get BMC mac rov + + @return ret: 0 sucess , -1 fail + outmsg: if success is out msg, or fail is err msg + """ + bmc = self.chas.get_bmc_byname("master") + if bmc is None: + msg = "name master not find" + baseutil.logger_debug(msg) + return -1, msg + return bmc.get_mac_rov() + + def get_bmc_next_boot(self): + """ + Get next booting flash of BMC + + @return 'master'/'slave' on success, "N/A" for failure + """ + bmc = self.chas.get_bmc_byname("master") + if bmc is None: + baseutil.logger_debug("name master not find") + return self.na_ret + return bmc.get_next_boot() + + def set_bmc_next_boot(self, flash): + """ + Set flash from which next BMC boot + + @param flash Booting flash of BMC, "master" or "slave" + + @return 0 on success, -1 for failure + """ + flash_status = ("master", "slave") + if flash is None or flash not in flash_status: + baseutil.logger_debug("parameter flash illegal, should be [master|slave]") + return -1 + bmc = self.chas.get_bmc_byname("master") + if bmc is None: + baseutil.logger_debug("name master not find") + return -1 + return bmc.set_next_boot(flash) + + def reboot_bmc(self): + """ + Reboot running BMC + """ + bmc = self.chas.get_bmc_byname("master") + if bmc is None: + baseutil.logger_debug("name master not find") + return -1 + return bmc.reboot() + + def get_bmc_info(self): + """ + Get BMC info + + @return dict of BMC info or None for failure + "Version": "1.1.1", # "N/A" + "Flash": "master", # "N/A" + "Next": "master" # "N/A" + """ + bmc = self.chas.get_bmc_byname("master") + if bmc is None: + baseutil.logger_debug("name master not find") + return self.na_ret + return bmc.get_info() + + def get_bmc_version_all(self): + """ + @return dict of BMCs + { + "MasterVersion": "1.1.1", # "N/A" + "SlaveVersion": "1.1.1" # "N/A" + } + """ + bmc = self.chas.get_bmc_byname("master") + if bmc is None: + baseutil.logger_debug("name master not find") + return self.na_ret + return bmc.get_version_all() + + def bmc_execute_command(self, cmd_str): + ret, output = osutil.command(cmd_str) + if ret: + baseutil.logger_debug("execute %s command failed" % (cmd_str)) + return ret, output + + def get_cpu_reset_num(self): + """ + Get CPU reset num + @return CPU reset num on success, -1 for failure + """ + cpu = self.chas.get_cpu_byname("cpu") + if cpu is None: + msg = "name cpu not find" + baseutil.logger_debug(msg) + return -1 + return cpu.get_cpu_reset_num() + + def get_cpu_reboot_cause(self): + """ + Get CPU reboot cause + @return string of cpu reboot reason + """ + cpu = self.chas.get_cpu_byname("cpu") + if cpu is None: + msg = "name cpu not find" + baseutil.logger_debug(msg) + return "Unknown reboot cause" + return cpu.get_cpu_reboot_cause() + diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/led.py b/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/led.py new file mode 100644 index 000000000000..7fb869c74d7f --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/led.py @@ -0,0 +1,52 @@ +#!/usr/bin/env python3 +####################################################### +# +# led.py +# Python implementation of the Class led +# +####################################################### +from plat_hal.devicebase import devicebase + + +class led(devicebase): + def __init__(self, conf=None): + if conf is not None: + self.name = conf.get('name', None) + self.led_type = conf.get('led_type', None) + self.led_attrs_config = conf.get('led_attrs', None) + self.led_config = conf.get('led', None) + + def set_color(self, color): + status = self.led_attrs_config.get(color, None) + if status is None: + return False + + mask = self.led_attrs_config.get('mask', 0xff) + + if isinstance(self.led_config, list): + for led_config_index in self.led_config: + ret, value = self.get_value(led_config_index) + if (ret is False) or (value is None): + return False + setval = (int(value) & ~mask) | (status) + ret, val = self.set_value(led_config_index, setval) + if ret is False: + return ret + else: + ret, value = self.get_value(self.led_config) + if (ret is False) or (value is None): + return False + setval = (int(value) & ~mask) | (status) + ret, val = self.set_value(self.led_config, setval) + return ret + + def get_color(self): + mask = self.led_attrs_config.get('mask', 0xff) + ret, value = self.get_value(self.led_config) + if ret is False or value is None: + return False, 'N/A' + ledval = int(value) & mask + for key, val in self.led_attrs_config.items(): + if (ledval == val) and (key != "mask"): + return True, key + return False, 'N/A' diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/onie_e2.py b/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/onie_e2.py new file mode 100644 index 000000000000..9ac32cace263 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/onie_e2.py @@ -0,0 +1,127 @@ +#!/usr/bin/env python3 +####################################################### +# +# onie_e2.py +# Python implementation of the Class onie_e2 +# +####################################################### +from plat_hal.devicebase import devicebase +from eepromutil.onietlv import onie_tlv + + +class onie_e2(devicebase): + + def __init__(self, conf=None): + self._cardid = "" + self._productname = "" + self._partnum = "" + self._serialnum = "" + self._macbase = "" + self._manufdate = "" + self._deviceversion = "" + self._labelrevision = "" + self._platformname = "" + self._onieversion = "" + self._macsize = "" + self._manufname = "" + self._manufcountry = "" + self._vendorname = "" + self._diagname = "" + self._servicetag = "" + + if conf is not None: + self.name = conf.get('name', None) + self.e2loc = conf.get('e2loc', None) + self.e2_path = self.e2loc.get('loc', None) + self.airflow = conf.get('airflow', "intake") + + @property + def cardid(self): + return self._cardid + + @property + def productname(self): + return self._productname + + @property + def partnum(self): + return self._partnum + + @property + def serialnum(self): + return self._serialnum + + @property + def macbase(self): + return self._macbase + + @property + def manufdate(self): + return self._manufdate + + @property + def deviceversion(self): + return self._deviceversion + + @property + def labelrevision(self): + return self._labelrevision + + @property + def platformname(self): + return self._platformname + + @property + def onieversion(self): + return self._onieversion + + @property + def macsize(self): + return self._macsize + + @property + def manufname(self): + return self._manufname + + @property + def manufcountry(self): + return self._manufcountry + + @property + def vendorname(self): + return self._vendorname + + @property + def diagname(self): + return self._diagname + + @property + def servicetag(self): + return self._servicetag + + def get_onie_e2_info(self): + try: + eeprom = self.get_eeprom_info(self.e2loc) + if eeprom is None: + raise Exception("%s: value is none" % self.name) + onietlv = onie_tlv() + onietlv.decode(eeprom) + self._cardid = onietlv.cardid + self._productname = onietlv.productname + self._partnum = onietlv.partnum + self._serialnum = onietlv.serialnum + self._macbase = onietlv.macbase + self._manufdate = onietlv.manufdate + self._deviceversion = onietlv.deviceversion + self._labelrevision = onietlv.labelrevision + self._platformname = onietlv.platformname + self._onieversion = onietlv.onieversion + self._macsize = onietlv.macsize + self._manufname = onietlv.manufname + self._manufcountry = onietlv.manufcountry + self._vendorname = onietlv.vendorname + self._diagname = onietlv.diagname + self._servicetag = onietlv.servicetag + except Exception: + return False + return True diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/osutil.py b/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/osutil.py new file mode 100644 index 000000000000..684e26bb9ecd --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/osutil.py @@ -0,0 +1,440 @@ +#!/usr/bin/env python3 +####################################################### +# +# osutil.py +# Python implementation of the Class osutil +# +####################################################### + +import os +import glob +import re +import time +import subprocess +import fcntl +import syslog +from functools import wraps +from wbutil.smbus import SMBus + + +PLATFORM_HAL_DEBUG_FILE = "/etc/.platform_hal_debug_flag" + + +def platform_hal_debug(s): + if os.path.exists(PLATFORM_HAL_DEBUG_FILE): + syslog.openlog("PLATFORM_HAL", syslog.LOG_PID) + syslog.syslog(syslog.LOG_DEBUG, s) + + +def retry(maxretry=6, delay=0.01): + ''' + maxretry: max retry times + delay : interval after last retry + ''' + def decorator(f): + @wraps(f) + def wrapper(*args, **kwargs): + time_retry = maxretry + time_delay = delay + result_msg = "" + while time_retry: + try: + val, result_msg = f(*args, **kwargs) + if val is True: + return val, result_msg + time_retry -= 1 + time.sleep(time_delay) + except Exception as e: + time_retry -= 1 + result_msg = str(e) + time.sleep(time_delay) + return False, "max time retry last errmsg is {}".format(result_msg) + return wrapper + return decorator + + +pidfile = None + + +def file_rw_lock(file_path): + global pidfile + pidfile = open(file_path, "r") + try: + fcntl.flock(pidfile, fcntl.LOCK_EX | fcntl.LOCK_NB) + platform_hal_debug("file_rw_lock success") + return True + except Exception: + if pidfile is not None: + pidfile.close() + pidfile = None + return False + + +def file_rw_unlock(): + try: + global pidfile + + if pidfile is not None: + fcntl.flock(pidfile, fcntl.LOCK_UN) + pidfile.close() + pidfile = None + platform_hal_debug("file_rw_unlock success") + else: + platform_hal_debug("pidfile is invalid, do nothing") + return True + except Exception as e: + platform_hal_debug("file_rw_unlock err, msg: %s" % (str(e))) + return False + + +def take_file_rw_lock(file_path): + loop = 1000 + ret = False + for i in range(0, loop): + ret = file_rw_lock(file_path) + if ret is True: + break + time.sleep(0.001) + return ret + + +class osutil(object): + """ + osutil + """ + + @staticmethod + @retry(maxretry=6) + def wbi2cget_python(bus, addr, reg): + with SMBus(bus) as y: + val, ind = y.read_byte_data(addr, reg, True) + return val, ind + + @staticmethod + @retry(maxretry=6) + def wbi2cset_python(bus, addr, reg, value): + with SMBus(bus) as y: + val, ind = y.write_byte_data(addr, reg, value, True) + return val, ind + + @staticmethod + @retry(maxretry=6) + def wbi2cgetword_python(bus, addr, reg): + with SMBus(bus) as y: + val, ind = y.read_word_data(addr, reg, True) + return val, ind + + @staticmethod + @retry(maxretry=6) + def wbi2csetword_python(bus, addr, reg, value): + with SMBus(bus) as y: + val, ind = y.write_word_data(addr, reg, value, True) + return val, ind + + @staticmethod + @retry(maxretry=6) + def wbi2csetwordpec_python(bus, addr, reg, value): + with SMBus(bus) as y: + val, ind = y.write_word_data_pec(addr, reg, value, True) + return val, ind + + @staticmethod + @retry(maxretry=6) + def wbi2cset_byte_pec_python(bus, addr, reg, value): + with SMBus(bus) as y: + val, ind = y.write_byte_data_pec(addr, reg, value, True) + return val, ind + + @staticmethod + def command(cmdstr): + retcode, output = subprocess.getstatusoutput(cmdstr) + return retcode, output + + @staticmethod + def geti2cword_i2ctool(bus, addr, offset): + command_line = "i2cget -f -y %d 0x%02x 0x%02x wp" % (bus, addr, offset) + retrytime = 6 + ret_t = "" + for i in range(retrytime): + ret, ret_t = osutil.command(command_line) + if ret == 0: + return True, int(ret_t, 16) + time.sleep(0.1) + return False, ret_t + + @staticmethod + def seti2cword_i2ctool(bus, addr, offset, val): + command_line = "i2cset -f -y %d 0x%02x 0x%0x 0x%04x wp" % (bus, addr, offset, val) + retrytime = 6 + ret_t = "" + for i in range(retrytime): + ret, ret_t = osutil.command(command_line) + if ret == 0: + return True, ret_t + time.sleep(0.1) + return False, ret_t + + @staticmethod + def wbi2cget_i2ctool(bus, devno, address): + command_line = "i2cget -f -y %d 0x%02x 0x%02x " % (bus, devno, address) + retrytime = 6 + ret_t = "" + for i in range(retrytime): + ret, ret_t = osutil.command(command_line) + if ret == 0: + return True, int(ret_t, 16) + time.sleep(0.1) + return False, ret_t + + @staticmethod + def wbi2cset_i2ctool(bus, devno, address, byte): + command_line = "i2cset -f -y %d 0x%02x 0x%02x 0x%02x" % ( + bus, devno, address, byte) + retrytime = 6 + ret_t = "" + for i in range(retrytime): + ret, ret_t = osutil.command(command_line) + if ret == 0: + return True, ret_t + return False, ret_t + + @staticmethod + def geti2cword(bus, addr, offset): + return osutil.wbi2cgetword_python(bus, addr, offset) + + @staticmethod + def seti2cword(bus, addr, offset, val): + return osutil.wbi2csetword_python(bus, addr, offset, val) + + @staticmethod + def seti2cwordpec(bus, addr, offset, val): + return osutil.wbi2csetwordpec_python(bus, addr, offset, val) + + @staticmethod + def seti2c_byte_pec(bus, addr, offset, val): + return osutil.wbi2cset_byte_pec_python(bus, addr, offset, val) + + @staticmethod + def wbi2cget(bus, devno, address): + return osutil.wbi2cget_python(bus, devno, address) + + @staticmethod + def wbi2cset(bus, devno, address, byte): + return osutil.wbi2cset_python(bus, devno, address, byte) + + @staticmethod + def byteTostr(val): + strtmp = '' + for value in val: + strtmp += chr(value) + return strtmp + + @staticmethod + def io_rd(reg_addr, read_len=1): + try: + regaddr = 0 + if isinstance(reg_addr, int): + regaddr = reg_addr + else: + regaddr = int(reg_addr, 16) + devfile = "/dev/port" + fd = os.open(devfile, os.O_RDWR | os.O_CREAT) + os.lseek(fd, regaddr, os.SEEK_SET) + val = os.read(fd, read_len) + return True, "".join(["%02x" % item for item in val]) + except ValueError as e: + return False, str(e) + except Exception as e: + return False, str(e) + finally: + os.close(fd) + + @staticmethod + def readsysfs(location, flock_path=None): + flock_path_tmp = None + platform_hal_debug("readsysfs, location:%s, flock_path:%s" % (location, flock_path)) + try: + if flock_path is not None: + flock_paths = glob.glob(flock_path) + if len(flock_paths) != 0: + flock_path_tmp = flock_paths[0] + platform_hal_debug("try to get file lock, path:%s" % flock_path_tmp) + ret = take_file_rw_lock(flock_path_tmp) + if ret is False: + platform_hal_debug("take file lock timeout, path:%s" % flock_path_tmp) + return False, ("take file rw lock timeout, path:%s" % flock_path_tmp) + else: + platform_hal_debug("config error, can't find flock_path:%s" % flock_path) + + locations = glob.glob(location) + with open(locations[0], 'rb') as fd1: + retval = fd1.read() + retval = osutil.byteTostr(retval) + if flock_path_tmp is not None: + file_rw_unlock() + + retval = retval.rstrip('\r\n') + retval = retval.lstrip(" ") + except Exception as e: + if flock_path_tmp is not None: + file_rw_unlock() + platform_hal_debug("readsysfs error, msg:%s" % str(e)) + return False, (str(e) + " location[%s]" % location) + return True, retval + + @staticmethod + def writesysfs(location, value): + try: + if not os.path.isfile(location): + print(location, 'not found !') + return False, ("location[%s] not found !" % location) + with open(location, 'w') as fd1: + fd1.write(value) + except Exception as e: + return False, (str(e) + " location[%s]" % location) + return True, ("set location[%s] %s success !" % (location, value)) + + @staticmethod + def getdevmem(addr, digit, mask): + command_line = "devmem 0x%02x %d" % (addr, digit) + retrytime = 6 + ret_t = "" + for i in range(retrytime): + ret, ret_t = osutil.command(command_line) + if ret == 0: + if mask is not None: + ret_t = str(int(ret_t, 16) & mask) + return True, ret_t + return False, ret_t + + @staticmethod + def readdevfile_ascii(path, offset, length): + msg = "" + ret = "" + joinstr = '' + fd = -1 + + if not os.path.exists(path): + msg = path + " not found !" + return False, msg + + try: + fd = os.open(path, os.O_RDONLY) + os.lseek(fd, offset, os.SEEK_SET) + ret = os.read(fd, length) + for item in ret: + joinstr += '%02x ' % item # like sysfs, display in hex + except Exception as e: + msg = str(e) + return False, msg + finally: + if fd > 0: + os.close(fd) + return True, joinstr + + @staticmethod + def readdevfile(path, offset, length): + msg = "" + ret = "" + fd = -1 + val_list = [] + + if not os.path.exists(path): + msg = path + " not found !" + return False, msg + + try: + fd = os.open(path, os.O_RDONLY) + os.lseek(fd, offset, os.SEEK_SET) + ret = os.read(fd, length) + for item in ret: + val_list.append(item) + except Exception as e: + msg = str(e) + return False, msg + finally: + if fd > 0: + os.close(fd) + return True, val_list + + @staticmethod + def writedevfile(path, offset, buf): + msg = "" + fd = -1 + + if not os.path.exists(path): + msg = path + " not found !" + return False, msg + + if isinstance(buf, list): + if len(buf) == 0: + msg = "buf:%s is NONE !" % buf + return False, msg + elif isinstance(buf, int): + buf = [buf] + else: + msg = "buf:%s is not list type or not int type !" % buf + return False, msg + + try: + fd = os.open(path, os.O_WRONLY) + os.lseek(fd, offset, os.SEEK_SET) + ret = os.write(fd, bytes(buf)) + except Exception as e: + msg = str(e) + return False, msg + finally: + if fd > 0: + os.close(fd) + + return True, ret + + @staticmethod + def wb_os_system(cmd): + status, output = subprocess.getstatusoutput(cmd) + return status, output + + @staticmethod + def getsdkreg(reg): + try: + cmd = "bcmcmd -t 1 'getr %s ' < /dev/null" % reg + ret, result = osutil.wb_os_system(cmd) + result_t = result.strip().replace("\r", "").replace("\n", "") + if ret != 0 or "Error:" in result_t: + return False, result + patt = r"%s.(.*):(.*)>drivshell" % reg + rt = re.findall(patt, result_t, re.S) + test = re.findall("=(.*)", rt[0][0])[0] + except Exception as e: + return False, 'get sdk register error, msg: %s' % str(e) + return True, test + + @staticmethod + def getmactemp(): + try: + result = {} + # need to exec twice + osutil.wb_os_system("bcmcmd -t 1 \"show temp\" < /dev/null") + ret, log = osutil.wb_os_system("bcmcmd -t 1 \"show temp\" < /dev/null") + if ret: + return False, result + logs = log.splitlines() + for line in logs: + if "average" in line: + b = re.findall(r'\d+.\d+', line) + result["average"] = b[0] + elif "maximum" in line: + b = re.findall(r'\d+.\d+', line) + result["maximum"] = b[0] + except Exception as e: + return False, str(e) + return True, result + + @staticmethod + def std_match(stdout, pattern): + if pattern is None: + return stdout.strip() + for line in stdout.splitlines(): + if re.match(pattern, line): + return line.strip() + return None diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/psu.py b/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/psu.py new file mode 100644 index 000000000000..e7db0cdcca8b --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/psu.py @@ -0,0 +1,607 @@ +#!/usr/bin/env python3 +####################################################### +# +# psu.py +# Python implementation of the Class psu +# +####################################################### +from eepromutil.fru import ipmifru +from plat_hal.devicebase import devicebase +from plat_hal.sensor import sensor + + +class psu(devicebase): + __pmbus = None + __e2loc = None + __productManufacturer = None # : ARTESYN + __productName = None # : CRPS550W + __productPartModelName = None # : CSU550AP-3-300 + __productVersion = None # : AB + __productSerialNumber = None # : M623UZ00JYABL + __AirFlow = None # 'N/A' + __AirFlowconifg = None + __psu_display_name = None # 'N/A' + __psu_display_name_conifg = None + __psu_not_present_pwm = None + __InputStatus_config = None + __OutputStatus_config = None + __FanSpeed_config = None + __Temperature_config = None + __InputStatus = None + __OutputStatus = None + __FanSpeed = None + __Temperature = None + __FanSpeedMin = None + __FanSpeedMax = None + __FanSpeedTolerance = None + __InputsVoltage_config = None + __InputsCurrent_config = None + __InputsPower_config = None + __OutputsVoltage_config = None + __OutputsCurrent_config = None + __OutputsPower_config = None + __InputsVoltage = {} + __InputsCurrent = None + __InputsPower = None + __OutputsVoltage = None + __OutputsCurrent = None + __OutputsPower = None + __InputsType_config = None + __InputsType = None + __psu_sn_config = None + __psu_hw_config = None + __psu_pn_config = None + __psu_vendor_config = None + __TempStatus_config = None + __FanStatus_config = None + __TempStatus = None + __FanStatus = None + + def __init__(self, conf=None): + self.pmbus = conf.get("pmbusloc", None) + self.e2loc = conf.get("e2loc", None) + self.__presentconfig = conf.get("present", None) + self.name = conf.get("name", None) + self.AirFlowconifg = conf.get("airflow", None) + self.psu_display_name_conifg = conf.get("psu_display_name", None) + self.psu_not_present_pwm = conf.get("psu_not_present_pwm", 100) + self.Temperature_config = conf.get("Temperature", None) + self.Temperature = sensor(self.Temperature_config) + + self.FanSpeedTolerance = conf.get('psu_fan_tolerance', 30) + self.FanSpeed_config = conf.get("FanSpeed", None) + self.FanSpeed = sensor(self.FanSpeed_config) + + self.__InputsVoltage_config = conf.get("InputsVoltage", None) + self.generate_psu_input_vol(self.__InputsVoltage_config) + self.__InputsCurrent_config = conf.get("InputsCurrent", None) + self.InputsCurrent = sensor(self.__InputsCurrent_config) + self.__InputsPower_config = conf.get("InputsPower", None) + self.InputsPower = sensor(self.__InputsPower_config) + self.__OutputsVoltage_config = conf.get("OutputsVoltage", None) + self.OutputsVoltage = sensor(self.__OutputsVoltage_config) + self.__OutputsCurrent_config = conf.get("OutputsCurrent", None) + self.OutputsCurrent = sensor(self.__OutputsCurrent_config) + self.__OutputsPower_config = conf.get("OutputsPower", None) + self.OutputsPower = sensor(self.__OutputsPower_config) + + self.__InputStatus_config = conf.get("InputsStatus", None) + self.__OutputStatus_config = conf.get("OutputsStatus", None) + self.__InputsType_config = conf.get('InputsType', None) + self.__psu_sn_config = conf.get('psu_sn', None) + self.__psu_hw_config = conf.get('psu_hw', None) + self.__psu_pn_config = conf.get('psu_pn', None) + self.__psu_vendor_config = conf.get('psu_vendor', None) + self.__TempStatus_config = conf.get("TempStatus", None) + self.__FanStatus_config = conf.get("FanStatus", None) + + def generate_psu_input_vol(self, config): + tmp = {} + for (key, item) in config.items(): + tmp.setdefault(key, sensor(item)) + self.__InputsVoltage = tmp + + def get_psu_sensor_by_name(self, psutype): + return self.__InputsVoltage.get(psutype) or self.__InputsVoltage.get('other') + + @property + def InputsVoltage(self): + psutype = self.InputsType + input_sensor = self.get_psu_sensor_by_name(psutype) + if input_sensor is None: + return None + return input_sensor + + @InputsVoltage.setter + def InputsVoltage(self, val): + self.__InputsVoltage = val + + @property + def InputsCurrent(self): + return self.__InputsCurrent + + @InputsCurrent.setter + def InputsCurrent(self, val): + self.__InputsCurrent = val + + @property + def InputsPower(self): + return self.__InputsPower + + @InputsPower.setter + def InputsPower(self, val): + self.__InputsPower = val + + @property + def OutputsVoltage(self): + return self.__OutputsVoltage + + @OutputsVoltage.setter + def OutputsVoltage(self, val): + self.__OutputsVoltage = val + + @property + def OutputsCurrent(self): + return self.__OutputsCurrent + + @OutputsCurrent.setter + def OutputsCurrent(self, val): + self.__OutputsCurrent = val + + @property + def OutputsPower(self): + return self.__OutputsPower + + @OutputsPower.setter + def OutputsPower(self, val): + self.__OutputsPower = val + + @property + def InputStatus(self): + if self.present is False: + self.__InputStatus = False + else: + ret, val = self.get_value(self.__InputStatus_config) + mask = self.__InputStatus_config.get("mask") + if ret is True: + ttt = val & mask + if ttt == 0: + self.__InputStatus = True + else: + self.__InputStatus = False + else: + self.__InputStatus = False + return self.__InputStatus + + @InputStatus.setter + def InputStatus(self, val): + self.__InputStatus = val + + @property + def TempStatus(self): + if self.__TempStatus_config is None: + return None + if self.present is False: + self.__TempStatus = False + else: + ret, val = self.get_value(self.__TempStatus_config) + mask = self.__TempStatus_config.get("mask") + if ret is True: + ttt = val & mask + if ttt == 0: + self.__TempStatus = True + else: + self.__TempStatus = False + else: + self.__TempStatus = False + return self.__TempStatus + + @TempStatus.setter + def TempStatus(self, val): + self.__TempStatus = val + + @property + def FanStatus(self): + if self.__FanStatus_config is None: + return None + if self.present is False: + self.__FanStatus = False + else: + ret, val = self.get_value(self.__FanStatus_config) + mask = self.__FanStatus_config.get("mask") + if ret is True: + ttt = val & mask + if ttt == 0: + self.__FanStatus = True + else: + self.__FanStatus = False + else: + self.__FanStatus = False + return self.__FanStatus + + @FanStatus.setter + def FanStatus(self, val): + self.__FanStatus = val + + @property + def InputsType(self): + psutypedecode = self.__InputsType_config.get('psutypedecode', None) + if self.present is False: + self.__InputsType = psutypedecode.get(0x00) + else: + ret, val = self.get_value(self.__InputsType_config) + self.__InputsType = self.__InputsType_config.get(val, None) + if self.__InputsType is not None: + return self.__InputsType + if ret is True and val in psutypedecode: + self.__InputsType = psutypedecode.get(val) + else: + self.__InputsType = psutypedecode.get(0x00) + return self.__InputsType + + @InputsType.setter + def InputsType(self, val): + self.__InputsType = val + + @property + def FanSpeedMin(self): + return self.__FanSpeedMin + + @FanSpeedMin.setter + def FanSpeedMin(self, val): + self.__FanSpeedMin = val + + @property + def FanSpeedMax(self): + return self.__FanSpeedMax + + @FanSpeedMax.setter + def FanSpeedMax(self, val): + self.__FanSpeedMax = val + + @property + def FanSpeedTolerance(self): + return self.__FanSpeedTolerance + + @FanSpeedTolerance.setter + def FanSpeedTolerance(self, val): + self.__FanSpeedTolerance = val + + @property + def OutputStatus(self): + if self.present is False: + self.__OutputStatus = False + else: + ret, val = self.get_value(self.__OutputStatus_config) + mask = self.__OutputStatus_config.get("mask") + if ret is True: + ttt = val & mask + if ttt == 0: + self.__OutputStatus = True + else: + self.__OutputStatus = False + else: + self.__OutputStatus = False + return self.__OutputStatus + + @OutputStatus.setter + def OutputStatus(self, val): + self.__OutputStatus = val + + @property + def FanSpeed(self): + return self.__FanSpeed + + @FanSpeed.setter + def FanSpeed(self, val): + self.__FanSpeed = val + + @property + def Temperature(self): + return self.__Temperature + + @Temperature.setter + def Temperature(self, val): + self.__Temperature = val + + @property + def Temperature_config(self): + return self.__Temperature_config + + @Temperature_config.setter + def Temperature_config(self, val): + self.__Temperature_config = val + + @property + def AirFlowconifg(self): + return self.__AirFlowconifg + + @AirFlowconifg.setter + def AirFlowconifg(self, val): + self.__AirFlowconifg = val + + @property + def psu_display_name_conifg(self): + return self.__psu_display_name_conifg + + @psu_display_name_conifg.setter + def psu_display_name_conifg(self, val): + self.__psu_display_name_conifg = val + + @property + def pmbus(self): + return self.__pmbus + + @pmbus.setter + def pmbus(self, val): + self.__pmbus = val + + @property + def e2loc(self): + return self.__e2loc + + @e2loc.setter + def e2loc(self, val): + self.__e2loc = val + + @property + def AirFlow(self): + return self.__AirFlow + + @AirFlow.setter + def AirFlow(self, val): + self.__AirFlow = val + + @property + def psu_display_name(self): + return self.__psu_display_name + + @psu_display_name.setter + def psu_display_name(self, val): + self.__psu_display_name = val + + @property + def psu_not_present_pwm(self): + return self.__psu_not_present_pwm + + @psu_not_present_pwm.setter + def psu_not_present_pwm(self, val): + self.__psu_not_present_pwm = val + + @property + def present(self): + ret, val = self.get_value(self.__presentconfig) + if ret is False or val is None: + return False + mask = self.__presentconfig.get("mask") + if isinstance(val, str): + value = int(val, 16) + else: + value = val + ttt = value & mask + okval = self.__presentconfig.get("okval", 0) + if ttt == okval: + return True + return False + + @property + def productManufacturer(self): + return self.__productManufacturer + + @productManufacturer.setter + def productManufacturer(self, val): + self.__productManufacturer = val + + @property + def productName(self): + return self.__productName + + @productName.setter + def productName(self, val): + self.__productName = val + + @property + def productPartModelName(self): + return self.__productPartModelName + + @productPartModelName.setter + def productPartModelName(self, val): + self.__productPartModelName = val + + @property + def productVersion(self): + return self.__productVersion + + @productVersion.setter + def productVersion(self, val): + self.__productVersion = val + + @property + def productSerialNumber(self): + return self.__productSerialNumber + + @productSerialNumber.setter + def productSerialNumber(self, val): + self.__productSerialNumber = val + + @property + def psu_sn_sysfs(self): + if self.__psu_sn_config is None: + return None + ret, val = self.get_value(self.__psu_sn_config) + if ret is False or val is None: + return None + return val + + @property + def psu_hw_sysfs(self): + if self.__psu_hw_config is None: + return None + ret, val = self.get_value(self.__psu_hw_config) + if ret is False or val is None: + return None + return val + + @property + def psu_pn_sysfs(self): + if self.__psu_pn_config is None: + return None + ret, val = self.get_value(self.__psu_pn_config) + if ret is False or val is None: + return None + return val + + @property + def psu_vendor_sysfs(self): + if self.__psu_vendor_config is None: + return None + ret, val = self.get_value(self.__psu_vendor_config) + if ret is False or val is None: + return None + return val + + def __str__(self): + formatstr = \ + "name : %s \n" \ + "productManufacturer : %s \n" \ + "productName : %s \n" \ + "productPartModelName: %s \n" \ + "productVersion : %s \n" \ + "productSerialNumber : %s \n" \ + "AirFlow : %s \n" \ + + tmpstr = formatstr % (self.name, self.productManufacturer, + self.productName, self.productPartModelName, + self.productVersion, self.productSerialNumber, self.AirFlow) + return tmpstr + + def get_fan_speed_pwm(self): + if self.present is False: + return self.psu_not_present_pwm + selfconfig = {} + selfconfig['bus'] = self.pmbus['bus'] + selfconfig['addr'] = self.pmbus['addr'] + selfconfig['way'] = 'i2cword' + selfconfig['offset'] = 0x3b + ret, val = self.get_value(selfconfig) + if ret is True: + return val + return None + + def set_fan_speed_pwm(self, pwm): + ''' + pmbus + if duty: + i2cset -f -y 0x3b 0x0064 wp + ''' + if self.present is False: + return None + if 0 <= pwm <= 100: + # enable duty first + selfconfig = {} + + selfconfig['bus'] = self.pmbus['bus'] + selfconfig['addr'] = self.pmbus['addr'] + selfconfig['way'] = 'i2cpec' + selfconfig['offset'] = 0x3a + self.set_value(selfconfig, 0x80) + + selfconfig['way'] = 'i2cwordpec' + selfconfig['offset'] = 0x3b + bytetmp = pwm + ret, val = self.set_value(selfconfig, int(bytetmp)) + if ret is True: + return True + return None + raise Exception("pwm not in range [0,100]") + + def get_fru_info_by_sysfs(self): + try: + psu_sn = self.psu_sn_sysfs + psu_hw = self.psu_hw_sysfs + psu_pn = self.psu_pn_sysfs + psu_vendor = self.psu_vendor_sysfs + if psu_sn is None or psu_hw is None or psu_pn is None or psu_vendor is None: + return False + self.productSerialNumber = psu_sn.strip().replace(chr(0), "") + self.productVersion = psu_hw.strip() + self.productPartModelName = psu_pn.strip() + self.productManufacturer = psu_vendor.strip().replace(chr(0), "") + except Exception: + self.productSerialNumber = None + self.productVersion = None + self.productPartModelName = None + self.productManufacturer = None + return False + return True + + def get_fru_info_by_decode(self): + try: + eeprom = self.get_eeprom_info(self.e2loc) + if eeprom is None: + raise Exception("%s:value is none" % self.name) + fru = ipmifru() + if isinstance(eeprom, bytes): + eeprom = self.byteTostr(eeprom) + fru.decodeBin(eeprom) + if fru.productInfoArea is not None: + self.productManufacturer = fru.productInfoArea.productManufacturer.strip() + self.productName = fru.productInfoArea.productName.strip() + self.productPartModelName = fru.productInfoArea.productPartModelName.strip() + self.productVersion = fru.productInfoArea.productVersion.strip() + self.productSerialNumber = fru.productInfoArea.productSerialNumber.strip().replace(chr(0), "") + except Exception: + self.productManufacturer = None + self.productName = None + self.productPartModelName = None + self.productVersion = None + self.productSerialNumber = None + return False + return True + + def get_fru_info(self): + try: + if self.present is not True: + raise Exception("%s: not present" % self.name) + if self.get_fru_info_by_sysfs() is True: + return True + return self.get_fru_info_by_decode() + except Exception: + self.productManufacturer = None + self.productName = None + self.productPartModelName = None + self.productVersion = None + self.productSerialNumber = None + return False + + def get_AirFlow(self): + if self.productPartModelName is None: + ret = self.get_fru_info() + if ret is False: + self.AirFlow = None + return False + if self.AirFlowconifg is None: + self.AirFlow = None + return False + for i in self.AirFlowconifg: + if self.productPartModelName in self.AirFlowconifg[i]: + self.AirFlow = i + return True + self.AirFlow = None + return False + + def get_psu_display_name(self): + if self.productPartModelName is None: + ret = self.get_fru_info() + if ret is False: + self.psu_display_name = None + return False + if self.psu_display_name_conifg is None: + self.psu_display_name = self.productPartModelName + return False + for i in self.psu_display_name_conifg: + if self.productPartModelName in self.psu_display_name_conifg[i]: + self.psu_display_name = i + return True + self.psu_display_name = self.productPartModelName + return False diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/rotor.py b/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/rotor.py new file mode 100644 index 000000000000..2b4e4ffd5f0e --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/rotor.py @@ -0,0 +1,149 @@ +#!/usr/bin/env python3 +####################################################### +# +# rotor.py +# Python implementation of the Class rotor +# +####################################################### +from plat_hal.devicebase import devicebase +from plat_hal.sensor import sensor + + +class rotor(devicebase): + __rotor_Running = None + __rotor_HwAlarm_conf = None + __rotor_Speed = None + __rotor_run_conf = None + __Speedconfig = None + __i2c_speed = None + __SpeedMin = None + __SpeedMax = None + __SpeedTolerance = None + + def __init__(self, conf=None): + self.name = conf.get('name', None) + self.rotor_HwAlarm_conf = conf.get('HwAlarm', None) + self.rotor_run_conf = conf.get('Running', None) + self.SpeedMin = conf.get('SpeedMin', None) + self.SpeedMax = conf.get('SpeedMax', None) + self.Tolerance = conf.get('tolerance', 30) + self.rotor_Speed = sensor(conf.get('Speed', None)) + self.Speedconfig = conf.get('Set_speed', None) + + def getRunning(self): + ret, val = self.get_value(self.rotor_run_conf) + if ret is False or val is None: + return False + if isinstance(val, str): + value = int(val, 16) + else: + value = val + mask = self.rotor_run_conf.get("mask") + is_runing_value = self.rotor_run_conf.get("is_runing") + flag = value & mask + if flag == is_runing_value: + return True + return False + + @property + def SpeedMin(self): + return self.__SpeedMin + + @SpeedMin.setter + def SpeedMin(self, val): + self.__SpeedMin = val + + @property + def SpeedMax(self): + return self.__SpeedMax + + @SpeedMax.setter + def SpeedMax(self, val): + self.__SpeedMax = val + + @property + def Tolerance(self): + return self.__SpeedTolerance + + @Tolerance.setter + def Tolerance(self, val): + self.__SpeedTolerance = val + + @property + def i2c_speed(self): + ret, val = self.get_value(self.Speedconfig) + if ret is False: + return None + if val is not None: + self.__i2c_speed = val + return self.__i2c_speed + + def feed_watchdog(self): + ret, val = self.get_value(self.Speedconfig) + if ret is False: + return False, None + if val is not None: + ret, val = self.set_value(self.Speedconfig, val) + return ret, val + return False, None + + @i2c_speed.setter + def i2c_speed(self, val): + self.__i2c_speed = val + + @property + def Speedconfig(self): + return self.__Speedconfig + + @Speedconfig.setter + def Speedconfig(self, val): + self.__Speedconfig = val + + @property + def rotor_run_conf(self): + return self.__rotor_run_conf + + @rotor_run_conf.setter + def rotor_run_conf(self, val): + self.__rotor_run_conf = val + + @property + def rotor_Speed(self): + return self.__rotor_Speed + + @rotor_Speed.setter + def rotor_Speed(self, val): + self.__rotor_Speed = val + + @property + def rotor_HwAlarm(self): + ret, val = self.get_value(self.rotor_HwAlarm_conf) + mask = self.rotor_HwAlarm_conf.get("mask") + no_alarm_value = self.rotor_HwAlarm_conf.get("no_alarm") + if ret is False or val is None: + return False + if isinstance(val, str): + value = int(val, 16) + else: + value = val + flag = value & mask + if flag == no_alarm_value: + return False + return True + + @property + def rotor_HwAlarm_conf(self): + return self.__rotor_HwAlarm_conf + + @rotor_HwAlarm_conf.setter + def rotor_HwAlarm_conf(self, val): + self.__rotor_HwAlarm_conf = val + + @property + def rotor_Running(self): + self.__rotor_Running = self.getRunning() + return self.__rotor_Running + + @rotor_Running.setter + def rotor_Running(self, val): + self.__rotor_Running = val diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/sensor.py b/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/sensor.py new file mode 100644 index 000000000000..2b4e05e00e43 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/sensor.py @@ -0,0 +1,219 @@ +#!/usr/bin/env python3 +####################################################### +# +# sensor.py +# Python implementation of the Class sensor +# +####################################################### +import time +from plat_hal.devicebase import devicebase + + +class sensor(devicebase): + + __Value = None + __Min = None + __Max = None + __Low = None + __High = None + __ValueConfig = None + __Flag = None + __Unit = None + __format = None + __read_times = None + + __Min_config = None + __Max_config = None + __Low_config = None + __High_config = None + + @property + def Min_config(self): + return self.__Min_config + + @Min_config.setter + def Min_config(self, val): + self.__Min_config = val + + @property + def Max_config(self): + return self.__Max_config + + @Max_config.setter + def Max_config(self, val): + self.__Max_config = val + + @property + def Low_config(self): + return self.__Low_config + + @Low_config.setter + def Low_config(self, val): + self.__Low_config = val + + @property + def High_config(self): + return self.__High_config + + @High_config.setter + def High_config(self, val): + self.__High_config = val + + @property + def Unit(self): + return self.__Unit + + @Unit.setter + def Unit(self, val): + self.__Unit = val + + @property + def format(self): + return self.__format + + @format.setter + def format(self, val): + self.__format = val + + @property + def read_times(self): + return self.__read_times + + @read_times.setter + def read_times(self, val): + self.__read_times = val + + @property + def ValueConfig(self): + return self.__ValueConfig + + @ValueConfig.setter + def ValueConfig(self, val): + self.__ValueConfig = val + + @property + def Flag(self): + return self.__Flag + + @Flag.setter + def Flag(self, val): + self.__Flag = val + + def get_median(self, value_config, read_times): + val_list = [] + for i in range(0, read_times): + ret, real_value = self.get_value(value_config) + if i != (read_times - 1): + time.sleep(0.01) + if ret is False or real_value is None: + continue + val_list.append(real_value) + val_list.sort() + if val_list: + return True, val_list[int((len(val_list) - 1) / 2)] + return False, None + + @property + def Value(self): + try: + ret, val = self.get_median(self.ValueConfig, self.read_times) + if ret is False or val is None: + return None + if self.format is None: + self.__Value = int(val) + else: + self.__Value = self.get_format_value(self.format % val) + self.__Value = round(float(self.__Value), 3) + except Exception: + return None + return self.__Value + + @Value.setter + def Value(self, val): + self.__Value = val + + @property + def Min(self): + try: + if self.format is None: + self.__Min = self.Min_config + else: + self.__Min = self.get_format_value(self.format % self.Min_config) + self.__Min = round(float(self.__Min), 3) + except Exception: + return None + return self.__Min + + @Min.setter + def Min(self, val): + self.__Min = val + + @property + def Max(self): + try: + if self.format is None: + self.__Max = self.Max_config + else: + self.__Max = self.get_format_value(self.format % self.Max_config) + self.__Max = round(float(self.__Max), 3) + except Exception: + return None + return self.__Max + + @Max.setter + def Max(self, val): + self.__Max = val + + @property + def Low(self): + try: + if self.format is None: + self.__Low = self.Low_config + else: + self.__Low = self.get_format_value(self.format % self.Low_config) + except Exception: + return None + return self.__Low + + @Low.setter + def Low(self, val): + self.__Low = val + + @property + def High(self): + try: + if self.format is None: + self.__High = self.High_config + else: + self.__High = self.get_format_value(self.format % self.High_config) + except Exception: + return None + return self.__High + + @High.setter + def High(self, val): + self.__High = val + + def __init__(self, conf=None): + self.ValueConfig = conf.get("value", None) + self.Flag = conf.get("flag", None) + self.Min_config = conf.get("Min", None) + self.Max_config = conf.get("Max", None) + self.Low_config = conf.get("Low", None) + self.High_config = conf.get("High", None) + self.Unit = conf.get('Unit', None) + self.format = conf.get('format', None) + self.read_times = conf.get('read_times', 1) + + def __str__(self): + formatstr = \ + "ValueConfig: : %s \n" \ + "Min : %s \n" \ + "Max : %s \n" \ + "Unit : %s \n" \ + "format: : %s \n" + + tmpstr = formatstr % (self.ValueConfig, self.Min, + self.Max, self.Unit, + self.format) + return tmpstr diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/temp.py b/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/temp.py new file mode 100644 index 000000000000..a202c20339c9 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/lib/plat_hal/temp.py @@ -0,0 +1,139 @@ +#!/usr/bin/env python3 +####################################################### +# +# temp.py +# Python implementation of the Class temp +# +####################################################### +import os +import syslog +from plat_hal.sensor import sensor + + +PLATFORM_HAL_TEMP_DEBUG_FILE = "/etc/.platform_hal_temp_debug_flag" + + +def platform_hal_temp_debug(s): + if os.path.exists(PLATFORM_HAL_TEMP_DEBUG_FILE): + syslog.openlog("PLATFORM_HAL_TEPM", syslog.LOG_PID) + syslog.syslog(syslog.LOG_DEBUG, s) + + +class temp(sensor): + def __init__(self, conf=None): + super(temp, self).__init__(conf.get('Temperature', None)) + self.name = conf.get("name", None) + self.temp_id = conf.get("temp_id", None) + self.api_name = conf.get("api_name", self.name) + self.fix_value = conf.get("fix_value", None) + self.temp_invalid = conf.get("invalid", None) + self.temp_error = conf.get("error", None) + + def temp_cali_by_fan_pwm(self, param, origin_value): + fan_pwm_conf = param.get("fan_pwm") + temp_fix_list = param.get("temp_fix_list") + + ret, val = self.get_value(fan_pwm_conf) + if ret is False or val is None: + platform_hal_temp_debug("temp calibration get fan pwm failed, msg: %s, return None" % (val)) + return None + + fan_pwm = int(val) + for item in temp_fix_list: + if item["min"] <= fan_pwm <= item["max"]: + fix_value = origin_value + item["fix"] + platform_hal_temp_debug("temp calibration by fan pwm, origin_value: %s, pwm: %s, fix_value: %s" % + (origin_value, fan_pwm, fix_value)) + return fix_value + platform_hal_temp_debug("temp calibration by fan pwm, origin_value: %s, pwm: %s, not match return None" % + (origin_value, fan_pwm)) + return None + + def fix_temp_value(self, origin_value): + try: + fix_type = self.fix_value.get("fix_type") + + if fix_type == "func": + func_name = self.fix_value.get("func_name") + func_param = self.fix_value.get("func_param") + func = getattr(self, func_name) + if func is None: + platform_hal_temp_debug("function %s, not defined" % func_name) + return None + value = func(func_param, origin_value) + return value + + if fix_type == "config": + coefficient = self.fix_value.get("coefficient", 1) + addend = self.fix_value.get("addend", 0) + value = (origin_value + addend) * coefficient + platform_hal_temp_debug("temp calibration by config, coefficient: %s, addend: %s, origin_value: %s, fix_value: %s" % + (coefficient, addend, origin_value, value)) + return value + + platform_hal_temp_debug("unsupport fix type: %s, return origin value: %s" % (fix_type, origin_value)) + return origin_value + except Exception as e: + platform_hal_temp_debug("fix_temp_value raise exception, msg: %s" % (str(e))) + return None + + def get_max_value(self, conf): + try: + ret, val = self.get_value(conf) + if ret is False or val is None: + return None + return val + except Exception: + return None + + def check_flag(self): + try: + okbit = self.Flag.get('okbit') + okval = self.Flag.get('okval') + ret, val = self.get_value(self.Flag) + if (ret is False) or (val is None): + return False + val_t = (int(val) & (1 << okbit)) >> okbit + if val_t != okval: + return False + except Exception: + return False + return True + + @property + def Value(self): + try: + if self.Flag is not None: + if self.check_flag() is False: + return None + if isinstance(self.ValueConfig, list): + max_val = None + for i in self.ValueConfig: + tmp = self.get_max_value(i) + if tmp is None: + continue + if max_val is None or max_val < tmp: + max_val = tmp + if max_val is None: + return None + if self.format is None: + self.__Value = int(max_val) + else: + self.__Value = self.get_format_value(self.format % max_val) + else: + ret, val = self.get_value(self.ValueConfig) + if ret is False or val is None: + return None + if self.format is None: + self.__Value = int(val) + else: + self.__Value = self.get_format_value(self.format % val) + except Exception: + return None + if self.fix_value is not None and self.__Value != self.temp_invalid and self.__Value != self.temp_error: + self.__Value = self.fix_temp_value(self.__Value) + return self.__Value + + @Value.setter + def Value(self, val): + self.__Value = val diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/lib/rgutil/logutil.py b/platform/broadcom/sonic-platform-modules-ragile/common/lib/rgutil/logutil.py deleted file mode 100644 index 2b001f21d72c..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/common/lib/rgutil/logutil.py +++ /dev/null @@ -1,67 +0,0 @@ -# -*- coding: UTF-8 -*- - -import logging -from syslog import ( - syslog, - openlog, - LOG_WARNING, - LOG_CRIT, - LOG_DEBUG, - LOG_ERR, - LOG_PID, - LOG_INFO, -) - -class Logger(): - def __init__(self, prefix, filepath=None, syslog=False, dbg_mask=0x0): - self.logger = None - if syslog is False: - if filepath is None: - raise AttributeError("filepath needed") - - # init logging - formatter = logging.Formatter( "%(asctime)s %(levelname)s %(filename)s[%(funcName)s][%(lineno)s]: %(message)s") - handler = logging.FileHandler(self.filepath) - handler.setFormatter(formatter) - self.logger = logging.getLogger(__name__) - self.logger.setLevel(logging.DEBUG) - self.logger.addHandler(handler) - - self.prefix = prefix - self.use_syslog = syslog - self.dbg_mask = dbg_mask - - def info(self, s): - if self.use_syslog: - self._syslog(s, LOG_INFO) - else: - self.logger.info(s) - - def debug(self, dbg_lvl, s): - if dbg_lvl & self.dbg_mask: - if self.use_syslog: - self._syslog(s, LOG_DEBUG) - else: - self.logger.debug(s) - - def warn(self, s): - if self.use_syslog: - self._syslog(s, LOG_WARNING) - else: - self.logger.warning(s) - - def error(self, s): - if self.use_syslog: - self._syslog(s, LOG_ERR) - else: - self.logger.error(s) - - def crit(self, s): - if self.use_syslog: - self._syslog(s, LOG_CRIT) - else: - self.logger.critical(s) - - def _syslog(self, s, t): - openlog(self.prefix, LOG_PID) - syslog(t, s) diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/lib/wbutil/__init__.py b/platform/broadcom/sonic-platform-modules-ragile/common/lib/wbutil/__init__.py new file mode 100644 index 000000000000..e69de29bb2d1 diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/lib/rgutil/baseutil.py b/platform/broadcom/sonic-platform-modules-ragile/common/lib/wbutil/baseutil.py similarity index 51% rename from platform/broadcom/sonic-platform-modules-ragile/common/lib/rgutil/baseutil.py rename to platform/broadcom/sonic-platform-modules-ragile/common/lib/wbutil/baseutil.py index 1cf74d32d22f..340a1f7a733f 100644 --- a/platform/broadcom/sonic-platform-modules-ragile/common/lib/rgutil/baseutil.py +++ b/platform/broadcom/sonic-platform-modules-ragile/common/lib/wbutil/baseutil.py @@ -1,6 +1,7 @@ -# -*- coding: UTF-8 -*- +#!/usr/bin/env python3 import os + def get_machine_info(): if not os.path.isfile('/host/machine.conf'): return None @@ -13,11 +14,25 @@ def get_machine_info(): machine_vars[tokens[0]] = tokens[1].strip() return machine_vars + def get_platform_info(machine_info): - if machine_info != None: + if machine_info is not None: if 'onie_platform' in machine_info: - return machine_info['onie_platform'] - elif 'aboot_platform' in machine_info: + return machine_info['onie_platform'] + if 'aboot_platform' in machine_info: return machine_info['aboot_platform'] return None + +def get_board_id(machine_info): + if machine_info is not None: + if 'onie_board_id' in machine_info: + return machine_info['onie_board_id'].lower() + return "NA" + + +def get_onie_machine(machine_info): + if machine_info is not None: + if 'onie_machine' in machine_info: + return machine_info['onie_machine'] + return None diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/lib/rgutil/smbus.py b/platform/broadcom/sonic-platform-modules-ragile/common/lib/wbutil/smbus.py similarity index 89% rename from platform/broadcom/sonic-platform-modules-ragile/common/lib/rgutil/smbus.py rename to platform/broadcom/sonic-platform-modules-ragile/common/lib/wbutil/smbus.py index f3651fe59a4a..5f1659b3bbf0 100644 --- a/platform/broadcom/sonic-platform-modules-ragile/common/lib/rgutil/smbus.py +++ b/platform/broadcom/sonic-platform-modules-ragile/common/lib/wbutil/smbus.py @@ -1,4 +1,5 @@ -"""smbus2 - A drop-in replacement for smbus-cffi/smbus-python""" +#!/usr/bin/env python3 +# smbus2 - A drop-in replacement for smbus-cffi/smbus-python # The MIT License (MIT) # Copyright (c) 2017 Karl-Petter Lindegaard # @@ -32,6 +33,7 @@ I2C_FUNCS = 0x0705 # Get the adapter functionality mask I2C_RDWR = 0x0707 # Combined R/W transfer (one STOP only) I2C_SMBUS = 0x0720 # SMBus transfer. Takes pointer to i2c_smbus_ioctl_data +I2C_PEC = 0x0708 # SMBus transfer read or write markers from uapi/linux/i2c.h I2C_SMBUS_WRITE = 0 @@ -43,7 +45,8 @@ I2C_SMBUS_BYTE_DATA = 2 I2C_SMBUS_WORD_DATA = 3 I2C_SMBUS_PROC_CALL = 4 -I2C_SMBUS_BLOCK_DATA = 5 # This isn't supported by Pure-I2C drivers with SMBUS emulation, like those in RaspberryPi, OrangePi, etc :( +# This isn't supported by Pure-I2C drivers with SMBUS emulation, like those in RaspberryPi, OrangePi, etc :( +I2C_SMBUS_BLOCK_DATA = 5 I2C_SMBUS_BLOCK_PROC_CALL = 7 # Like I2C_SMBUS_BLOCK_DATA, it isn't supported by Pure-I2C drivers either. I2C_SMBUS_I2C_BLOCK_DATA = 8 I2C_SMBUS_BLOCK_MAX = 32 @@ -216,12 +219,12 @@ def write(address, buf): :rtype: :py:class:`i2c_msg` """ if sys.version_info.major >= 3: - if type(buf) is str: + if isinstance(buf, str): buf = bytes(map(ord, buf)) else: buf = bytes(buf) else: - if type(buf) is not str: + if not isinstance(buf, str): buf = ''.join([chr(x) for x in buf]) arr = create_string_buffer(buf, len(buf)) return i2c_msg( @@ -406,7 +409,7 @@ def read_byte_data(self, i2c_addr, register, force=None): :rtype: int """ val_t = -1 - returnmsg="" + returnmsg = "" try: self._set_address(i2c_addr, force=force) msg = i2c_smbus_ioctl_data.create( @@ -418,8 +421,7 @@ def read_byte_data(self, i2c_addr, register, force=None): returnmsg = str(e) if val_t < 0: return False, returnmsg - else: - return True, msg.data.contents.byte + return True, msg.data.contents.byte def write_byte_data(self, i2c_addr, register, value, force=None): """ @@ -449,8 +451,40 @@ def write_byte_data(self, i2c_addr, register, value, force=None): self.close() if val_t < 0: return False, returnmsg or "" - else: - return True, "" + return True, "" + + def write_byte_data_pec(self, i2c_addr, register, value, force=None): + """ + Write a byte to a given register. + + :param i2c_addr: i2c address + :type i2c_addr: int + :param register: Register to write to + :type register: int + :param value: Byte value to transmit + :type value: int + :param force: + :type force: Boolean + :rtype: None + """ + val_t = -1 + returnmsg = "" + try: + val_t = ioctl(self.fd, I2C_PEC, 1) + if val_t < 0: + raise Exception("set pec mod error") + self._set_address(i2c_addr, force=force) + msg = i2c_smbus_ioctl_data.create( + read_write=I2C_SMBUS_WRITE, command=register, size=I2C_SMBUS_BYTE_DATA + ) + msg.data.contents.byte = value + val_t = ioctl(self.fd, I2C_SMBUS, msg) + except Exception as e: + returnmsg = str(e) + self.close() + if val_t < 0: + return False, returnmsg or "" + return True, "" def read_word_data(self, i2c_addr, register, force=None): """ @@ -478,8 +512,40 @@ def read_word_data(self, i2c_addr, register, force=None): self.close() if val_t < 0: return False, returnmsg or "" - else: - return True, msg.data.contents.word + return True, msg.data.contents.word + + def write_word_data_pec(self, i2c_addr, register, value, force=None): + """ + Write a byte to a given register. + + :param i2c_addr: i2c address + :type i2c_addr: int + :param register: Register to write to + :type register: int + :param value: Word value to transmit + :type value: int + :param force: + :type force: Boolean + :rtype: None + """ + val_t = -1 + returnmsg = "" + try: + val_t = ioctl(self.fd, I2C_PEC, 1) + if val_t < 0: + raise Exception("set pec mod error") + self._set_address(i2c_addr, force=force) + msg = i2c_smbus_ioctl_data.create( + read_write=I2C_SMBUS_WRITE, command=register, size=I2C_SMBUS_WORD_DATA + ) + msg.data.contents.word = value + val_t = ioctl(self.fd, I2C_SMBUS, msg) + except Exception as e: + returnmsg = str(e) + self.close() + if val_t < 0: + return False, returnmsg or "" + return True, "" def write_word_data(self, i2c_addr, register, value, force=None): """ @@ -509,8 +575,7 @@ def write_word_data(self, i2c_addr, register, value, force=None): self.close() if val_t < 0: return False, returnmsg or "" - else: - return True, "" + return True, "" def process_call(self, i2c_addr, register, value, force=None): """ @@ -685,6 +750,7 @@ class SMBusWrapper: :py:class:`SMBus` handle will be automatically closed upon exit of the ``with`` block. """ + def __init__(self, bus_number=0, auto_cleanup=True, force=False): """ :param auto_cleanup: Close bus when leaving scope. @@ -695,6 +761,7 @@ def __init__(self, bus_number=0, auto_cleanup=True, force=False): self.bus_number = bus_number self.auto_cleanup = auto_cleanup self.force = force + self.bus = None def __enter__(self): self.bus = SMBus(bus=self.bus_number, force=self.force) diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modprobe_conf/kernel_drivers_blacklist.conf b/platform/broadcom/sonic-platform-modules-ragile/common/modprobe_conf/kernel_drivers_blacklist.conf new file mode 100644 index 000000000000..5e861802d915 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modprobe_conf/kernel_drivers_blacklist.conf @@ -0,0 +1,5 @@ +blacklist wb_fpga_pcie +blacklist wb_i2c_i801 +blacklist wb_spi_gpio +blacklist intel_spi +blacklist intel_spi_platform diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/Makefile b/platform/broadcom/sonic-platform-modules-ragile/common/modules/Makefile old mode 100755 new mode 100644 index f7204c8684d9..8727f1f508f1 --- a/platform/broadcom/sonic-platform-modules-ragile/common/modules/Makefile +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/Makefile @@ -1,15 +1,55 @@ -obj-m := rg-gpio-xeon.o -obj-m += rg_fan.o -obj-m += rg_psu.o -obj-m += ragile_platform.o -obj-m += i2c-mux-pca9641.o -obj-m += i2c-mux-pca954x.o -obj-m += csu550.o -ragile_common-objs := ragile_common_module.o -obj-m += ragile_common.o -obj-m += fpga_pcie_i2c.o -obj-m += fpga_i2c_ocores.o -obj-m += lpc_dbg.o -obj-m += lpc_cpld_i2c_ocores.o -obj-m += rg-i2c-algo-bit.o -obj-m += rg-i2c-gpio.o +PWD = $(shell pwd) +EXTRA_CFLAGS:= -I$(M)/include +EXTRA_CFLAGS+= -Wall +KVERSION ?= $(shell uname -r) +KERNEL_SRC ?= /lib/modules/$(KVERSION) + +module_out_put_dir := $(PWD)/build +export module_out_put_dir + +KERNEL_MODULES_SRC = $(PWD)/linux-5.10 + +PLAT_SYSFS_DIR = $(PWD)/plat_sysfs +INTEL_SPI = $(PWD)/intel_spi + +export PLAT_SYSFS_DIR + +platform_common-objs := platform_common_module.o dfd_tlveeprom.o +obj-m += platform_common.o +obj-m += wb_mac_bsc.o +obj-m += wb_fpga_pcie.o +obj-m += wb_pcie_dev.o +obj-m += wb_fpga_i2c_bus_drv.o +obj-m += wb_fpga_pca954x_drv.o +obj-m += wb_lpc_drv.o +obj-m += wb_i2c_dev.o +obj-m += wb_platform_i2c_dev.o +obj-m += wb_io_dev.o +obj-m += wb_eeprom_93xx46.o +obj-m += wb_spi_93xx46.o +obj-m += wb_gpio_d1500.o +obj-m += wb_gpio_device.o +obj-m += wb_i2c_ocores.o +obj-m += wb_spi_ocores.o +obj-m += wb_spi_dev.o +obj-m += wb_wdt.o +obj-m += wb_optoe.o +obj-m += wb_spi_gpio.o +obj-m += wb_spi_gpio_device.o +obj-m += wb_spi_nor_device.o +obj-m += wb_xdpe132g5c.o +obj-m += wb_uio_irq.o + +all : + $(MAKE) -C $(KERNEL_MODULES_SRC) + $(MAKE) -C $(PLAT_SYSFS_DIR) + $(MAKE) -C $(INTEL_SPI) + $(MAKE) -C $(KERNEL_SRC)/build M=$(PWD) modules + @if [ ! -d $(module_out_put_dir) ]; then mkdir -p $(module_out_put_dir) ;fi + cp -p $(PWD)/*.ko $(module_out_put_dir) + +clean : + rm -rf $(module_out_put_dir) + rm -f ${PWD}/*.o ${PWD}/*.ko ${PWD}/*.mod.c ${PWD}/.*.cmd ${PWD}/.*.o.d ${PWD}/*.mod + rm -f ${PWD}/Module.markers ${PWD}/Module.symvers ${PWD}/modules.order + rm -rf ${PWD}/.tmp_versions diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/csu550.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/csu550.c deleted file mode 100755 index b1d1a9847218..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/common/modules/csu550.c +++ /dev/null @@ -1,252 +0,0 @@ -/* - * csu550.c - A driver for pmbus - * - * Copyright (c) 2010, 2011 Ericsson AB. - * Copyright (c) 2019 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "pmbus.h" - -struct pmbus_device_info { - int pages; - u32 flags; -}; - -static const struct i2c_device_id pmbus_id[]; - -/* - * Find sensor groups and status registers on each page. - */ -static void pmbus_find_sensor_groups(struct i2c_client *client, - struct pmbus_driver_info *info) -{ - int page; - - /* Sensors detected on page 0 only */ - if (pmbus_check_word_register(client, 0, PMBUS_READ_VIN)) - info->func[0] |= PMBUS_HAVE_VIN; - if (pmbus_check_word_register(client, 0, PMBUS_READ_IIN)) - info->func[0] |= PMBUS_HAVE_IIN; - if (pmbus_check_word_register(client, 0, PMBUS_READ_PIN)) - info->func[0] |= PMBUS_HAVE_PIN; - if (info->func[0] && pmbus_check_byte_register(client, 0, PMBUS_STATUS_INPUT)) - info->func[0] |= PMBUS_HAVE_STATUS_INPUT; - if (pmbus_check_byte_register(client, 0, PMBUS_FAN_CONFIG_12) && - pmbus_check_word_register(client, 0, PMBUS_READ_FAN_SPEED_1)) { - info->func[0] |= PMBUS_HAVE_FAN12; - if (pmbus_check_byte_register(client, 0, PMBUS_STATUS_FAN_12)) - info->func[0] |= PMBUS_HAVE_STATUS_FAN12; - } - if (pmbus_check_word_register(client, 0, PMBUS_READ_TEMPERATURE_1)) - info->func[0] |= PMBUS_HAVE_TEMP; - if (pmbus_check_word_register(client, 0, PMBUS_READ_TEMPERATURE_2)) - info->func[0] |= PMBUS_HAVE_TEMP2; - if (pmbus_check_word_register(client, 0, PMBUS_READ_TEMPERATURE_3)) - info->func[0] |= PMBUS_HAVE_TEMP3; - if (info->func[0] & (PMBUS_HAVE_TEMP | PMBUS_HAVE_TEMP2 | PMBUS_HAVE_TEMP3) - && pmbus_check_byte_register(client, 0, PMBUS_STATUS_TEMPERATURE)) - info->func[0] |= PMBUS_HAVE_STATUS_TEMP; - - /* Sensors detected on all pages */ - for (page = 0; page < info->pages; page++) { - if (pmbus_check_word_register(client, page, PMBUS_READ_VOUT)) { - info->func[page] |= PMBUS_HAVE_VOUT; - if (pmbus_check_byte_register(client, page, - PMBUS_STATUS_VOUT)) - info->func[page] |= PMBUS_HAVE_STATUS_VOUT; - } - if (pmbus_check_word_register(client, page, PMBUS_READ_IOUT)) { - info->func[page] |= PMBUS_HAVE_IOUT; - if (pmbus_check_byte_register(client, 0, - PMBUS_STATUS_IOUT)) - info->func[page] |= PMBUS_HAVE_STATUS_IOUT; - } - if (pmbus_check_word_register(client, page, PMBUS_READ_POUT)) - info->func[page] |= PMBUS_HAVE_POUT; - } -} - -/* - * Identify chip parameters. - */ -static int pmbus_identify(struct i2c_client *client, - struct pmbus_driver_info *info) -{ - int ret = 0; - - if (!info->pages) { - /* - * Check if the PAGE command is supported. If it is, - * keep setting the page number until it fails or until the - * maximum number of pages has been reached. Assume that - * this is the number of pages supported by the chip. - */ - if (pmbus_check_byte_register(client, 0, PMBUS_PAGE)) { - int page; - - for (page = 1; page < PMBUS_PAGES; page++) { - if (pmbus_set_page(client, page) < 0) - break; - } - pmbus_set_page(client, 0); - info->pages = page; - } else { - info->pages = 1; - } - } - - if (pmbus_check_byte_register(client, 0, PMBUS_VOUT_MODE)) { - int vout_mode, i; - - vout_mode = pmbus_read_byte_data(client, 0, PMBUS_VOUT_MODE); - if (vout_mode >= 0 && vout_mode != 0xff) { - switch (vout_mode >> 5) { - case 0: - break; - case 1: - info->format[PSC_VOLTAGE_OUT] = vid; -#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0) - for (i = 0; i < info->pages; i++) { - info->vrm_version[i] = vr11; - } -#endif - break; - case 2: - info->format[PSC_VOLTAGE_OUT] = direct; - break; - default: - ret = -ENODEV; - goto abort; - } - } - } - - /* - * We should check if the COEFFICIENTS register is supported. - * If it is, and the chip is configured for direct mode, we can read - * the coefficients from the chip, one set per group of sensor - * registers. - * - * To do this, we will need access to a chip which actually supports the - * COEFFICIENTS command, since the command is too complex to implement - * without testing it. Until then, abort if a chip configured for direct - * mode was detected. - */ - if (info->format[PSC_VOLTAGE_OUT] == direct) { - ret = -ENODEV; - goto abort; - } - - /* Try to find sensor groups */ - pmbus_find_sensor_groups(client, info); -abort: - return ret; -} - -#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0) -static int pmbus_probe(struct i2c_client *client, const struct i2c_device_id *id) -{ - struct pmbus_driver_info *info; - struct pmbus_platform_data *pdata = NULL; - struct device *dev = &client->dev; - - info = devm_kzalloc(&client->dev, sizeof(struct pmbus_driver_info), GFP_KERNEL); - if (!info) - return -ENOMEM; - - if (!strncmp(id->name, "dps460", sizeof("dps460")) || - !strncmp(id->name, "fsp1200", sizeof("fsp1200")) || !strncmp(id->name, "dps550", sizeof("dps550"))) { - pdata = kzalloc(sizeof(struct pmbus_platform_data), GFP_KERNEL); - if (!pdata) { - kfree(info); - return -ENOMEM; - } - pdata->flags = PMBUS_SKIP_STATUS_CHECK; - } - - info->pages = id->driver_data; - info->identify = pmbus_identify; - dev->platform_data = pdata; - - return pmbus_do_probe(client, id, info); -} -#else -static int pmbus_probe(struct i2c_client *client) -{ - struct pmbus_driver_info *info; - struct pmbus_platform_data *pdata = NULL; - struct device *dev = &client->dev; - struct pmbus_device_info *device_info; - - info = devm_kzalloc(dev, sizeof(struct pmbus_driver_info), GFP_KERNEL); - if (!info) - return -ENOMEM; - - device_info = (struct pmbus_device_info *)i2c_match_id(pmbus_id, client)->driver_data; - if (device_info->flags & PMBUS_SKIP_STATUS_CHECK) { - pdata = devm_kzalloc(dev, sizeof(struct pmbus_platform_data), GFP_KERNEL); - if (!pdata) { - return -ENOMEM; - } - pdata->flags = PMBUS_SKIP_STATUS_CHECK; - } - - info->pages = device_info->pages; - info->identify = pmbus_identify; - dev->platform_data = pdata; - - return pmbus_do_probe(client, info); -} -#endif -static const struct i2c_device_id pmbus_id[] = { - {"csu550", 0}, - {"csu800", 1}, - {"fsp1200", 1}, - {"dps550", 1}, - {} -}; -MODULE_DEVICE_TABLE(i2c, pmbus_id); - -/* This is the driver that will be inserted */ -static struct i2c_driver pmbus_driver = { -#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0) - .probe = pmbus_probe, -#else - .probe_new = pmbus_probe, -#endif - .id_table = pmbus_id, - .driver = { - .name = "pmbus", - }, -}; - -module_i2c_driver(pmbus_driver); - -MODULE_AUTHOR("support "); -MODULE_DESCRIPTION("ragile psupmbus driver"); -MODULE_LICENSE("GPL"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/dfd_tlveeprom.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/dfd_tlveeprom.c new file mode 100644 index 000000000000..0d6f38ecc551 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/dfd_tlveeprom.c @@ -0,0 +1,516 @@ +/* + * Copyright (C) 2003-2014 FreeIPMI Core Team + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + */ +/*****************************************************************************\ + * Copyright (C) 2007-2014 Lawrence Livermore National Security, LLC. + * Copyright (C) 2007 The Regents of the University of California. + * Produced at Lawrence Livermore National Laboratory (cf, DISCLAIMER). + * Written by Albert Chu + * UCRL-CODE-232183 + * + * This file is part of Ipmi-fru, a tool used for retrieving + * motherboard field replaceable unit (FRU) information. For details, + * see http://www.llnl.gov/linux/. + * + * Ipmi-fru is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 3 of the License, or (at your + * option) any later version. + * + * Ipmi-fru is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with Ipmi-fru. If not, see . +\*****************************************************************************/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "platform_common.h" +#include "dfd_tlveeprom.h" + +/* using in is_valid_tlvinfo_header */ +static u_int32_t eeprom_size; + +/* + * List of TLV codes and names. + */ +static const struct tlv_code_desc tlv_code_list[] = { + { TLV_CODE_PRODUCT_NAME , "Product Name"}, + { TLV_CODE_PART_NUMBER , "Part Number"}, + { TLV_CODE_SERIAL_NUMBER , "Serial Number"}, + { TLV_CODE_MAC_BASE , "Base MAC Address"}, + { TLV_CODE_MANUF_DATE , "Manufacture Date"}, + { TLV_CODE_DEVICE_VERSION , "Device Version"}, + { TLV_CODE_LABEL_REVISION , "Label Revision"}, + { TLV_CODE_PLATFORM_NAME , "Platform Name"}, + { TLV_CODE_ONIE_VERSION , "ONIE Version"}, + { TLV_CODE_MAC_SIZE , "MAC Addresses"}, + { TLV_CODE_MANUF_NAME , "Manufacturer"}, + { TLV_CODE_MANUF_COUNTRY , "Country Code"}, + { TLV_CODE_VENDOR_NAME , "Vendor Name"}, + { TLV_CODE_DIAG_VERSION , "Diag Version"}, + { TLV_CODE_SERVICE_TAG , "Service Tag"}, + { TLV_CODE_VENDOR_EXT , "Vendor Extension"}, + { TLV_CODE_CRC_32 , "CRC-32"}, +}; + +#if 0 +#define OPENBMC_VPD_KEY_INVAIL_VAL 0 + +static const tlv_code_map_t tlv_code_map[] = { + { TLV_CODE_PRODUCT_NAME , OPENBMC_VPD_KEY_PRODUCT_NAME}, + { TLV_CODE_PART_NUMBER , OPENBMC_VPD_KEY_PRODUCT_PART_MODEL_NUM}, + { TLV_CODE_SERIAL_NUMBER , OPENBMC_VPD_KEY_PRODUCT_SERIAL_NUM}, + { TLV_CODE_MAC_BASE , OPENBMC_VPD_KEY_INVAIL_VAL}, + { TLV_CODE_MANUF_DATE , OPENBMC_VPD_KEY_BOARD_MFG_DATE}, + { TLV_CODE_DEVICE_VERSION , OPENBMC_VPD_KEY_PRODUCT_VER}, + { TLV_CODE_LABEL_REVISION , OPENBMC_VPD_KEY_PRODUCT_CUSTOM7}, + { TLV_CODE_PLATFORM_NAME , OPENBMC_VPD_KEY_PRODUCT_CUSTOM1}, + { TLV_CODE_ONIE_VERSION , OPENBMC_VPD_KEY_PRODUCT_CUSTOM2}, + { TLV_CODE_MAC_SIZE , OPENBMC_VPD_KEY_INVAIL_VAL}, + { TLV_CODE_MANUF_NAME , OPENBMC_VPD_KEY_PRODUCT_MFR}, + { TLV_CODE_MANUF_COUNTRY , OPENBMC_VPD_KEY_PRODUCT_CUSTOM3}, + { TLV_CODE_VENDOR_NAME , OPENBMC_VPD_KEY_PRODUCT_CUSTOM4}, + { TLV_CODE_DIAG_VERSION , OPENBMC_VPD_KEY_PRODUCT_CUSTOM8}, + { TLV_CODE_SERVICE_TAG , OPENBMC_VPD_KEY_PRODUCT_CUSTOM5}, + { TLV_CODE_VENDOR_EXT , OPENBMC_VPD_KEY_PRODUCT_CUSTOM6}, + { TLV_CODE_CRC_32 , OPENBMC_VPD_KEY_INVAIL_VAL}, +}; +#endif + +#define TLV_CODE_NUM (sizeof(tlv_code_list) / sizeof(tlv_code_list[0])) + +#if 0 +#define TLV_CODE_MAP_NUM (sizeof(tlv_code_map) / sizeof(tlv_code_map[0])) +#endif + +const unsigned long crc_table[] = { + 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3, + 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988, 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, + 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, + 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5, + 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172, 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, + 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59, + 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f, + 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924, 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, + 0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433, + 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01, + 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, + 0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65, + 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, + 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0, 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, + 0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f, + 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad, + 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a, 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, + 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, + 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7, + 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc, 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, + 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b, + 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79, + 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236, 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, + 0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d, + 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713, + 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, + 0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777, + 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, + 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2, 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, + 0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9, + 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf, + 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94, 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d, +}; + +static unsigned long crc32(unsigned long crc, const unsigned char *buf, unsigned len) +{ + unsigned i; + if (len < 1) + return 0xffffffff; + + for (i = 0; i != len; ++i) + { + crc = crc_table[(crc ^ buf[i]) & 0xff] ^ (crc >> 8); + } + + crc = crc ^ 0xffffffff; + + return crc; +} + +/* + * is_valid_tlv + * + * Perform basic sanity checks on a TLV field. The TLV is pointed to + * by the parameter provided. + * 1. The type code is not reserved (0x00 or 0xFF) + */ +static inline bool is_valid_tlv(tlvinfo_tlv_t *tlv) +{ + return ((tlv->type != 0x00) && (tlv->type != 0xFF)); +} + +/* + * is_valid_tlvinfo_header + * + * Perform sanity checks on the first 11 bytes of the TlvInfo EEPROM + * data pointed to by the parameter: + * 1. First 8 bytes contain null-terminated ASCII string "TlvInfo" + * 2. Version byte is 1 + * 3. Total length bytes contain value which is less than or equal + * to the allowed maximum (2048-11) + * + */ +static inline bool is_valid_tlvinfo_header(tlvinfo_header_t *hdr) +{ + int max_size = eeprom_size; + return((strcmp(hdr->signature, TLV_INFO_ID_STRING) == 0) && + (hdr->version == TLV_INFO_VERSION) && + (be16_to_cpu(hdr->totallen) <= max_size) ); +} + +/* + * decode_tlv_value + * + * Decode a single TLV value into a string. + + * The validity of EEPROM contents and the TLV field have been verified + * prior to calling this function. + */ +static void decode_tlv_value(tlvinfo_tlv_t *tlv, tlv_decode_value_t *decode_value) +{ + int i; + char *value; + u_int32_t length; + + value = (char *)decode_value->value; + + switch (tlv->type) { + case TLV_CODE_PRODUCT_NAME: + case TLV_CODE_PART_NUMBER: + case TLV_CODE_SERIAL_NUMBER: + case TLV_CODE_MANUF_DATE: + case TLV_CODE_LABEL_REVISION: + case TLV_CODE_PLATFORM_NAME: + case TLV_CODE_ONIE_VERSION: + case TLV_CODE_MANUF_NAME: + case TLV_CODE_MANUF_COUNTRY: + case TLV_CODE_VENDOR_NAME: + case TLV_CODE_DIAG_VERSION: + case TLV_CODE_SERVICE_TAG: + case TLV_CODE_VENDOR_EXT: + memcpy(value, tlv->value, tlv->length); + value[tlv->length] = 0; + length = tlv->length; + break; + case TLV_CODE_MAC_BASE: + length = sprintf(value, "%02X:%02X:%02X:%02X:%02X:%02X", + tlv->value[0], tlv->value[1], tlv->value[2], + tlv->value[3], tlv->value[4], tlv->value[5]); + break; + case TLV_CODE_DEVICE_VERSION: + length = sprintf(value, "%u", tlv->value[0]); + break; + case TLV_CODE_MAC_SIZE: + length = sprintf(value, "%u", (tlv->value[0] << 8) | tlv->value[1]); + break; + #if 0 + case TLV_CODE_VENDOR_EXT: + value[0] = 0; + length = 0; + for (i = 0; (i < (TLV_DECODE_VALUE_MAX_LEN/5)) && (i < tlv->length); i++) { + length += sprintf(value, "%s 0x%02X", value, tlv->value[i]); + } + break; + #endif + case TLV_CODE_CRC_32: + length = sprintf(value, "0x%02X%02X%02X%02X", tlv->value[0], + tlv->value[1], tlv->value[2], tlv->value[3]); + break; + default: + value[0] = 0; + length = 0; + for (i = 0; (i < (TLV_DECODE_VALUE_MAX_LEN/5)) && (i < tlv->length); i++) { + length += sprintf(value, "%s 0x%02X", value, tlv->value[i]); + } + break; + } + + decode_value->length = length; +} + +/* + * is_checksum_valid + * + * Validate the checksum in the provided TlvInfo EEPROM data. First, + * verify that the TlvInfo header is valid, then make sure the last + * TLV is a CRC-32 TLV. Then calculate the CRC over the EEPROM data + * and compare it to the value stored in the EEPROM CRC-32 TLV. + */ +static bool is_checksum_valid(u_int8_t *eeprom) +{ + tlvinfo_header_t *eeprom_hdr; + tlvinfo_tlv_t *eeprom_crc; + unsigned int calc_crc; + unsigned int stored_crc; + + eeprom_hdr = (tlvinfo_header_t *) eeprom; + + // Is the eeprom header valid? + if (!is_valid_tlvinfo_header(eeprom_hdr)) { + return false; + } + + // Is the last TLV a CRC? + eeprom_crc = (tlvinfo_tlv_t *) &eeprom[sizeof(tlvinfo_header_t) + + be16_to_cpu(eeprom_hdr->totallen) - (sizeof(tlvinfo_tlv_t) + 4)]; + if ((eeprom_crc->type != TLV_CODE_CRC_32) || (eeprom_crc->length != 4)) { + return false; + } + + // Calculate the checksum + calc_crc = crc32(0xffffffffL, (const unsigned char *)eeprom, sizeof(tlvinfo_header_t) + + be16_to_cpu(eeprom_hdr->totallen) - 4); + stored_crc = ((eeprom_crc->value[0] << 24) | (eeprom_crc->value[1] << 16) | + (eeprom_crc->value[2] << 8) | eeprom_crc->value[3]); + + return (calc_crc == stored_crc); +} + +/* + * tlvinfo_find_tlv + * + * This function finds the TLV with the supplied code in the EERPOM. + * An offset from the beginning of the EEPROM is returned in the + * eeprom_index parameter if the TLV is found. + */ +static bool tlvinfo_find_tlv(u_int8_t *eeprom, u_int8_t tcode, int *eeprom_index) +{ + tlvinfo_header_t *eeprom_hdr; + tlvinfo_tlv_t *eeprom_tlv; + int eeprom_end; + + eeprom_hdr = (tlvinfo_header_t *) eeprom; + + // Search through the TLVs, looking for the first one which matches the + // supplied type code. + *eeprom_index = sizeof(tlvinfo_header_t); + eeprom_end = sizeof(tlvinfo_header_t) + be16_to_cpu(eeprom_hdr->totallen); + while (*eeprom_index < eeprom_end) { + eeprom_tlv = (tlvinfo_tlv_t *) &eeprom[*eeprom_index]; + if (!is_valid_tlv(eeprom_tlv)) { + return false; + } + + if (eeprom_tlv->type == tcode) { + return true; + } + + *eeprom_index += sizeof(tlvinfo_tlv_t) + eeprom_tlv->length; + } + + return false; +} + +/* + * tlvinfo_decode_tlv + * + * This function finds the TLV with the supplied code in the EERPOM + * and decodes the value into the buffer provided. + */ +static bool tlvinfo_decode_tlv(u_int8_t *eeprom, u_int8_t tcode, tlv_decode_value_t *decode_value) +{ + int eeprom_index; + tlvinfo_tlv_t *eeprom_tlv; + + // Find the TLV and then decode it + if (tlvinfo_find_tlv(eeprom, tcode, &eeprom_index)) { + eeprom_tlv = (tlvinfo_tlv_t *) &eeprom[eeprom_index]; + decode_tlv_value(eeprom_tlv, decode_value); + return true; + } + + return false; +} + +/* + * parse_tlv_eeprom + * + * parse the EEPROM into memory, if it hasn't already been read. + */ +int parse_tlv_eeprom(u_int8_t *eeprom, u_int32_t size) +{ + unsigned int i; + bool ret; + tlvinfo_header_t *eeprom_hdr; + //tlv_info_vec_t tlv_info; + tlv_decode_value_t decode_value; + int j; + + eeprom_hdr = (tlvinfo_header_t *) eeprom; + eeprom_size = size; /* eeprom real size */ + + if (!is_valid_tlvinfo_header(eeprom_hdr)) { + DBG_ERROR("Failed to check tlv header.\n"); + return -1; + } + + if (!is_checksum_valid(eeprom)) { + DBG_ERROR("Failed to check tlv crc.\n"); + return -1; + } + + for (i = 0; i < TLV_CODE_NUM; i++) { + mem_clear((void *)&decode_value, sizeof(tlv_decode_value_t)); + ret = tlvinfo_decode_tlv(eeprom, tlv_code_list[i].m_code, &decode_value); + if (!ret) { + DBG_ERROR("No found type: %s\n", tlv_code_list[i].m_name); + continue; + } + + DBG_DEBUG("i: %d,Found type: %s tlv[%d]:%s\n", i, tlv_code_list[i].m_name, tlv_code_list[i].m_code, + decode_value.value); + for (j = 0; j < decode_value.length; j++) { + if ((j % 16) == 0) { + DBG_DEBUG("\n"); + } + DBG_DEBUG("%02x ", decode_value.value[j]); + } + DBG_DEBUG("\n\n"); + } + return 0; +} +static int dfd_parse_tlv_eeprom(u_int8_t *eeprom, u_int32_t size, u_int8_t main_type, tlv_decode_value_t *decode_value) +{ + bool ret; + tlvinfo_header_t *eeprom_hdr; + //tlv_info_vec_t tlv_info; + int j; + + eeprom_hdr = (tlvinfo_header_t *) eeprom; + eeprom_size = size; /* eeprom real size */ + + if (!is_valid_tlvinfo_header(eeprom_hdr)) { + DBG_ERROR("Failed to check tlv header.\n"); + return -1; + } + + if (!is_checksum_valid(eeprom)) { + DBG_ERROR("Failed to check tlv crc.\n"); + return -1; + } + + ret = tlvinfo_decode_tlv(eeprom, main_type, decode_value); + if (!ret) { + DBG_ERROR("No found type: %d\n", main_type); + return -1; + } + + DBG_DEBUG("Found type: %d, value: %s\n", main_type,decode_value->value); + for (j = 0; j < decode_value->length; j++) { + if ((j % 16) == 0) { + DBG_DEBUG("\n"); + } + DBG_DEBUG("%02x ", decode_value->value[j]); + } + DBG_DEBUG("\n\n"); + + return 0; +} + +static int tlvinfo_find_wb_ext_tlv(tlv_decode_value_t *ext_tlv_value, u_int8_t ext_type, + u_int8_t *buf, u_int8_t *buf_len) +{ + tlvinfo_tlv_t *eeprom_tlv; + int eeprom_end, eeprom_index; + + // Search through the TLVs, looking for the first one which matches the + // supplied type code. + DBG_DEBUG("ext_tlv_value->length: %d.\n", ext_tlv_value->length); + for (eeprom_index = 0; eeprom_index < ext_tlv_value->length; eeprom_index++) { + if ((eeprom_index % 16) == 0) { + DBG_DEBUG("\n"); + } + DBG_DEBUG("%02x ", ext_tlv_value->value[eeprom_index]); + } + + DBG_DEBUG("\n"); + + eeprom_index = 0; + eeprom_end = ext_tlv_value->length; + while (eeprom_index < eeprom_end) { + eeprom_tlv = (tlvinfo_tlv_t *) &(ext_tlv_value->value[eeprom_index]); + if (!is_valid_tlv(eeprom_tlv)) { + DBG_ERROR("tlv is not valid, eeprom_tlv->type 0x%x.\n", eeprom_tlv->type); + return -1; + } + + DBG_DEBUG("eeprom_tlv->length %d.\n", eeprom_tlv->length); + if (eeprom_tlv->type == ext_type) { + if (*buf_len >= eeprom_tlv->length) { + memcpy(buf, eeprom_tlv->value, eeprom_tlv->length); + DBG_DEBUG("eeprom_tlv->length %d.\n", eeprom_tlv->length); + *buf_len = eeprom_tlv->length; + return 0; + } + DBG_ERROR("buf_len %d small than info_len %d.\n", *buf_len, eeprom_tlv->length); + return -1; + } + + eeprom_index += sizeof(tlvinfo_tlv_t) + eeprom_tlv->length; + } + + DBG_ERROR("ext_type %d: tlv is not found.\n", ext_type); + return -1; +} + +int dfd_tlvinfo_get_e2prom_info(u_int8_t *eeprom, u_int32_t size, dfd_tlv_type_t *tlv_type, u_int8_t* buf, u_int8_t *buf_len) +{ + tlv_decode_value_t decode_value; + int ret; + + if (eeprom == NULL || tlv_type == NULL || buf == NULL) { + DBG_ERROR("Input para invalid.\n"); + return -1; + } + + mem_clear((void *)&decode_value, sizeof(tlv_decode_value_t)); + ret = dfd_parse_tlv_eeprom(eeprom, size, tlv_type->main_type, &decode_value); + if (ret) { + DBG_ERROR("dfd_parse_tlv_eeprom failed ret %d.\n", ret); + return ret; + } + + if (tlv_type->main_type != TLV_CODE_VENDOR_EXT) { + if (*buf_len >= decode_value.length) { + memcpy(buf, decode_value.value, decode_value.length); + *buf_len = decode_value.length; + return 0; + } + DBG_ERROR("buf_len %d small than info_len %d.\n", *buf_len, decode_value.length); + return -1; + } + DBG_DEBUG("info_len %d.\n", decode_value.length); + + return tlvinfo_find_wb_ext_tlv(&decode_value, tlv_type->ext_type, buf, buf_len); +} diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/dfd_tlveeprom.h b/platform/broadcom/sonic-platform-modules-ragile/common/modules/dfd_tlveeprom.h new file mode 100644 index 000000000000..6eaac5848223 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/dfd_tlveeprom.h @@ -0,0 +1,121 @@ +#ifndef DFD_OPENBMC_TLVEEPROM_H +#define DFD_OPENBMC_TLVEEPROM_H + +#ifndef u_int8_t +#define u_int8_t unsigned char +#endif + +#ifndef u_int16_t +#define u_int16_t unsigned short +#endif + +#ifndef u_int32_t +#define u_int32_t unsigned int +#endif + +#ifndef be16_to_cpu +#define be16_to_cpu(x) ntohs(x) +#endif + +#ifndef cpu_to_be16 +#define cpu_to_be16(x) htons(x) +#endif + +/** + * The TLV Types. + * + * Keep these in sync with tlv_code_list in cmd_sys_eeprom.c + */ +#define TLV_CODE_PRODUCT_NAME 0x21 +#define TLV_CODE_PART_NUMBER 0x22 +#define TLV_CODE_SERIAL_NUMBER 0x23 +#define TLV_CODE_MAC_BASE 0x24 +#define TLV_CODE_MANUF_DATE 0x25 +#define TLV_CODE_DEVICE_VERSION 0x26 +#define TLV_CODE_LABEL_REVISION 0x27 +#define TLV_CODE_PLATFORM_NAME 0x28 +#define TLV_CODE_ONIE_VERSION 0x29 +#define TLV_CODE_MAC_SIZE 0x2A +#define TLV_CODE_MANUF_NAME 0x2B +#define TLV_CODE_MANUF_COUNTRY 0x2C +#define TLV_CODE_VENDOR_NAME 0x2D +#define TLV_CODE_DIAG_VERSION 0x2E +#define TLV_CODE_SERVICE_TAG 0x2F +#define TLV_CODE_VENDOR_EXT 0xFD +#define TLV_CODE_CRC_32 0xFE + +#define TLV_CODE_NAME_LEN 64 +/* + * Struct for displaying the TLV codes and names. + */ +struct tlv_code_desc { + u_int8_t m_code; + char m_name[TLV_CODE_NAME_LEN]; +}; + +typedef struct dfd_tlv_type_s { + u_int8_t main_type; + u_int8_t ext_type; +} dfd_tlv_type_t; + +// Header Field Constants +#define TLV_INFO_ID_STRING "TlvInfo" +#define TLV_INFO_VERSION 0x01 +/*#define TLV_TOTAL_LEN_MAX (XXXXXXXX - sizeof(tlvinfo_header_t))*/ + +struct __attribute__ ((__packed__)) tlvinfo_header_s { + char signature[8]; /* 0x00 - 0x07 EEPROM Tag "TlvInfo" */ + u_int8_t version; /* 0x08 Structure version */ + u_int16_t totallen; /* 0x09 - 0x0A Length of all data which follows */ +}; +typedef struct tlvinfo_header_s tlvinfo_header_t; + +/* + * TlvInfo TLV: Layout of a TLV field + */ +struct __attribute__ ((__packed__)) tlvinfo_tlv_s { + u_int8_t type; + u_int8_t length; + u_int8_t value[0]; +}; +typedef struct tlvinfo_tlv_s tlvinfo_tlv_t; + +#define TLV_VALUE_MAX_LEN 255 +/* + * The max decode value is currently for the 'raw' type or the 'vendor + * extension' type, both of which have the same decode format. The + * max decode string size is computed as follows: + * + * strlen(" 0xFF") * TLV_VALUE_MAX_LEN + 1 + * + */ +#define TLV_DECODE_VALUE_MAX_LEN ((5 * TLV_VALUE_MAX_LEN) + 1) + +typedef struct tlv_decode_value_s { + u_int8_t value[TLV_DECODE_VALUE_MAX_LEN]; + u_int32_t length; +} tlv_decode_value_t; + +typedef enum dfd_tlvinfo_ext_tlv_type_e { + DFD_TLVINFO_EXT_TLV_TYPE_DEV_TYPE = 1, +} dfd_tlvinfo_ext_tlv_type_t; + +#if 0 +#define TLV_TIME_LEN 64 + +int ipmi_tlv_validate_fru_area(const uint8_t fruid, const char *fru_file_name, + sd_bus *bus_type, const bool bmc_fru); + +extern const char *get_vpd_key_names(int key_id); +extern std::string getService(sdbusplus::bus::bus& bus, + const std::string& intf, + const std::string& path); +extern std::string getFRUValue(const std::string& section, + const std::string& key, + const std::string& delimiter, + IPMIFruInfo& fruData); +#endif + +int dfd_tlvinfo_get_e2prom_info(u_int8_t *eeprom, u_int32_t size, dfd_tlv_type_t *tlv_type, u_int8_t* buf, u_int8_t *buf_len); + +#endif /* endif DFD_OPENBMC_TLVEEPROM_H */ diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/fpga_i2c.h b/platform/broadcom/sonic-platform-modules-ragile/common/modules/fpga_i2c.h new file mode 100644 index 000000000000..649a8452debe --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/fpga_i2c.h @@ -0,0 +1,133 @@ +#ifndef _FPGA_I2C_H +#define _FPGA_I2C_H + +#include +#include +#include +#include + +#define mem_clear(data, size) memset((data), 0, (size)) + +#if 0 + +#define FPGA_I2C_EXT_9548_ADDR (0x00) +#define FPGA_I2C_EXT_9548_CHAN (0x04) +#define FPGA_I2C_DEV_SLAVE_ADDR (0x08) +#define FPGA_I2C_DEV_REG_ADDR (0x0C) +#define FPGA_I2C_DEV_RDWR_LEN (0x10) +#define FPGA_I2C_CTRL_REG (0x14) +#define FPGA_I2C_STATUS_REG (0x18) +#define FPGA_I2C_SCALE_REG (0x1C) +#define FPGA_I2C_FILTER_REG (0x20) +#define FPGA_I2C_STRETCH_REG (0x24) +#define FPGA_I2C_EXT_9548_EXITS_FLAG (0x28) +#define FPGA_I2C_INTERNAL_9548_CHAN (0x2C) +#define FPGA_I2C_RDWR_DATA_BUF (0x80) +#endif +#define FPGA_I2C_RDWR_MAX_LEN_DEFAULT (128) +#define I2C_REG_MAX_WIDTH (16) + +#define DEV_NAME_MAX_LEN (64) + +#define FPGA_I2C_MAX_TIMES (10) +#define FPGA_I2C_XFER_TIME_OUT (100000) +#define FPGA_I2C_SLEEP_TIME (40) + +typedef struct fpga_i2c_reg_s { + uint32_t i2c_scale; + uint32_t i2c_filter; + uint32_t i2c_stretch; + uint32_t i2c_ext_9548_exits_flag; + uint32_t i2c_ext_9548_addr; + uint32_t i2c_ext_9548_chan; + uint32_t i2c_in_9548_chan; + uint32_t i2c_slave; + uint32_t i2c_reg; + uint32_t i2c_reg_len; + uint32_t i2c_data_len; + uint32_t i2c_ctrl; + uint32_t i2c_status; + uint32_t i2c_err_vec; + uint32_t i2c_data_buf; + uint32_t i2c_data_buf_len; +} fpga_i2c_reg_t; + +typedef struct fpga_i2c_reset_cfg_s { + uint32_t i2c_adap_reset_flag; + uint32_t reset_addr; + uint32_t reset_on; + uint32_t reset_off; + uint32_t reset_delay_b; + uint32_t reset_delay; + uint32_t reset_delay_a; +} fpga_i2c_reset_cfg_t; + +typedef struct fpga_i2c_reg_addr_s { + uint8_t reg_addr_len; + uint8_t read_reg_addr[I2C_REG_MAX_WIDTH]; +} fpga_i2c_reg_addr_t; + +typedef struct fpga_i2c_dev_s { + fpga_i2c_reg_t reg; + fpga_i2c_reset_cfg_t reset_cfg; + fpga_i2c_reg_addr_t i2c_addr_desc; + const char *dev_name; + uint32_t i2c_scale_value; + uint32_t i2c_filter_value; + uint32_t i2c_stretch_value; + uint32_t i2c_timeout; + uint32_t i2c_func_mode; + wait_queue_head_t queue; + struct i2c_adapter adap; + int adap_nr; + struct device *dev; + bool i2c_params_check; +} fpga_i2c_dev_t; + +typedef struct fpga_i2c_bus_device_s { + int i2c_timeout; + int i2c_scale; + int i2c_filter; + int i2c_stretch; + int i2c_ext_9548_exits_flag; + int i2c_ext_9548_addr; + int i2c_ext_9548_chan; + int i2c_in_9548_chan; + int i2c_slave; + int i2c_reg; + int i2c_reg_len; + int i2c_data_len; + int i2c_ctrl; + int i2c_status; + int i2c_err_vec; + int i2c_data_buf; + int i2c_data_buf_len; + char dev_name[DEV_NAME_MAX_LEN]; + int adap_nr; + int i2c_scale_value; + int i2c_filter_value; + int i2c_stretch_value; + int i2c_func_mode; + int i2c_adap_reset_flag; + int i2c_reset_addr; + int i2c_reset_on; + int i2c_reset_off; + int i2c_rst_delay_b; /* delay time before reset(us) */ + int i2c_rst_delay; /* reset time(us) */ + int i2c_rst_delay_a; /* delay time after reset(us) */ + int device_flag; + bool i2c_params_check; + int i2c_data_buf_len_reg; + int i2c_offset_reg; +} fpga_i2c_bus_device_t; + +typedef struct fpga_pca954x_device_s { + struct i2c_client *client; + uint32_t i2c_bus; + uint32_t i2c_addr; + uint32_t fpga_9548_flag; + uint32_t fpga_9548_reset_flag; + uint32_t pca9548_base_nr; +} fpga_pca954x_device_t; + +#endif /* _FPGA_I2C_H */ diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/fpga_i2c_ocores.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/fpga_i2c_ocores.c deleted file mode 100755 index 7857f854d60e..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/common/modules/fpga_i2c_ocores.c +++ /dev/null @@ -1,911 +0,0 @@ -/* - * i2c-ocores.c: I2C bus driver for OpenCores I2C controller - * (http://www.opencores.org/projects.cgi/web/i2c/overview). - * - * Peter Korsgaard - * - * Support for the GRLIB port of the controller by - * Andreas Larsson - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "fpga_i2c_ocores.h" -#include -#include -#include - -struct ocores_i2c { - void __iomem *base; - u32 reg_shift; - u32 reg_io_width; - wait_queue_head_t wait; - struct i2c_adapter adap; - struct i2c_msg *msg; - int pos; - int nmsgs; - int state; /* see STATE_ */ - spinlock_t process_lock; - struct mutex xfer_lock; - int clock_khz; - void (*setreg)(struct ocores_i2c *i2c, int reg, u8 value); - u8 (*getreg)(struct ocores_i2c *i2c, int reg); -}; - -/* registers */ -#define OCI2C_PRELOW 0x0 -#define OCI2C_PREHIGH 0x4 -#define OCI2C_CONTROL 0x8 -#define OCI2C_DATA 0xc -#define OCI2C_CMD 0x10 /* write only */ -#define OCI2C_STATUS 0x10 /* read only, same address as OCI2C_CMD */ - -#define OCI2C_TRAN_REV 0x14 -#define OCI2C_CMD_REV 0x18 - - -#define OCI2C_CTRL_IEN 0x40 -#define OCI2C_CTRL_EN 0x80 - -#define OCI2C_CMD_START 0x91 -#define OCI2C_CMD_STOP 0x41 -#define OCI2C_CMD_READ 0x21 -#define OCI2C_CMD_WRITE 0x11 -#define OCI2C_CMD_READ_ACK 0x21 -#define OCI2C_CMD_READ_NACK 0x29 -#define OCI2C_CMD_IACK 0x01 - -#define OCI2C_STAT_IF 0x01 -#define OCI2C_STAT_TIP 0x02 -#define OCI2C_STAT_ARBLOST 0x20 -#define OCI2C_STAT_BUSY 0x40 -#define OCI2C_STAT_NACK 0x80 - -#define STATE_DONE 0 -#define STATE_START 1 -#define STATE_WRITE 2 -#define STATE_READ 3 -#define STATE_ERROR 4 - -#define TYPE_OCORES 0 -#define TYPE_GRLIB 1 - -#define BUF_SIZE 256 -#define DEFAULT_I2C_SCL 100 -#define DEFAULT_I2C_PRE 0xF9 - -int g_fpga_i2c_debug = 0; -int g_fpga_i2c_irq = 0; -int g_fpga_i2c_error = 0; -int g_irq_dump_debug = 0; -int g_irq_invalid_cnt = 0; -int g_fpga_debug = 0; - -module_param(g_fpga_i2c_debug, int, S_IRUGO | S_IWUSR); -module_param(g_fpga_i2c_error, int, S_IRUGO | S_IWUSR); -module_param(g_fpga_i2c_irq, int, S_IRUGO | S_IWUSR); -module_param(g_irq_dump_debug, int, S_IRUGO | S_IWUSR); -module_param(g_irq_invalid_cnt, int, S_IRUGO | S_IWUSR); -module_param(g_fpga_debug, int, S_IRUGO | S_IWUSR); - -#define FPGA_I2C_DEBUG(fmt, args...) do { \ - if (g_fpga_debug) { \ - printk(KERN_DEBUG ""fmt, ## args); \ - } \ -} while (0) - -#define FPGA_I2C_DEBUG_DUMP(fmt, args...) do { \ - if (g_irq_dump_debug) { \ - printk(KERN_ERR ""fmt, ## args); \ - } \ -} while (0) - -#define FPGA_I2C_DEBUG_XFER(fmt, args...) do { \ - if (g_fpga_i2c_irq) { \ - printk(KERN_ERR "[FPGA_I2C][XFER][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ - } \ -} while (0) - -#define FPGA_I2C_DEBUG_VERBOSE(fmt, args...) do { \ - if (g_fpga_i2c_debug) { \ - printk(KERN_ERR "[FPGA_I2C][VER][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ - } \ -} while (0) - -#define FPGA_I2C_DEBUG_ERROR(fmt, args...) do { \ - if (g_fpga_i2c_error) { \ - printk(KERN_ERR "[FPGA_I2C][ERR][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ - } \ -} while (0) - -static int check_ocores_i2c(struct i2c_msg *msgs, int num); -static void oc_debug_dump_reg(struct ocores_i2c *i2c); -static void oc_debug_dump_reg_dump(struct ocores_i2c *i2c); -static int oc_set_scl_clk(struct ocores_i2c *i2c, int val); - -static void oc_setreg_8(struct ocores_i2c *i2c, int reg, u8 value) -{ - iowrite8(value, i2c->base + (reg << i2c->reg_shift)); -} - -static void oc_setreg_16(struct ocores_i2c *i2c, int reg, u8 value) -{ - iowrite16(value, i2c->base + (reg << i2c->reg_shift)); -} - -static void oc_setreg_32(struct ocores_i2c *i2c, int reg, u8 value) -{ - iowrite32(value, i2c->base + (reg << i2c->reg_shift)); -} - -static inline u8 oc_getreg_8(struct ocores_i2c *i2c, int reg) -{ - return ioread8(i2c->base + (reg << i2c->reg_shift)); -} - -static inline u8 oc_getreg_16(struct ocores_i2c *i2c, int reg) -{ - return ioread16(i2c->base + (reg << i2c->reg_shift)); -} - -static inline u8 oc_getreg_32(struct ocores_i2c *i2c, int reg) -{ - return ioread32(i2c->base + (reg << i2c->reg_shift)); -} - -static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value) -{ - i2c->setreg(i2c, reg, value); -} - -static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg) -{ - return i2c->getreg(i2c, reg); -} - -#define FPGA_I2C_SPIN_LOCK(lock, flags) spin_lock_irqsave(&(lock), (flags)) -#define FPGA_I2C_SPIN_UNLOCK(lock, flags) spin_unlock_irqrestore(&(lock), (flags)) -#define FPGA_I2C_MUTEX_LOCK(lock) mutex_lock(&(lock)) -#define FPGA_I2C_MUTEX_UNLOCK(lock) mutex_unlock(&(lock)) - -static void ocores_process(struct ocores_i2c *i2c, u8 stat) -{ - struct i2c_msg *msg = i2c->msg; - - FPGA_I2C_DEBUG_XFER("Enter nr %d.\n", i2c->adap.nr); - if ((i2c->state == STATE_DONE) || (i2c->state == STATE_ERROR)) { - /* stop has been sent */ - oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK); - wake_up(&i2c->wait); - FPGA_I2C_DEBUG_XFER("stop has been sent, exit.\n"); - goto out; - } - - FPGA_I2C_DEBUG_XFER("Enter 111.\n"); - - /* error */ - if (stat & OCI2C_STAT_ARBLOST) { - i2c->state = STATE_ERROR; - oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); - FPGA_I2C_DEBUG_XFER("error, exit.\n"); - goto out; - } - - FPGA_I2C_DEBUG_XFER("Enter 222.\n"); - - if (check_ocores_i2c(i2c->msg, i2c->nmsgs) != 0) { - FPGA_I2C_DEBUG("i2c->msg->buf is null, i2c->state:%d exit.\n", i2c->state); - oc_debug_dump_reg_dump(i2c); - i2c->state = STATE_ERROR; - oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); - goto out; - } - - if ((i2c->state == STATE_START) || (i2c->state == STATE_WRITE)) { - i2c->state = - (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE; - - if (stat & OCI2C_STAT_NACK) { - i2c->state = STATE_ERROR; - oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); - FPGA_I2C_DEBUG_XFER("OCI2C_STAT_NACK, exit.\n"); - goto out; - } - } else { - msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA); - } - FPGA_I2C_DEBUG_XFER("Enter 333.\n"); - - /* end of msg? */ - if (i2c->pos == msg->len) { - FPGA_I2C_DEBUG_XFER("Enter end of msg.\n"); - i2c->nmsgs--; - i2c->msg++; - i2c->pos = 0; - msg = i2c->msg; - - if (i2c->nmsgs) { /* end? */ - /* send start? */ - if (!(msg->flags & I2C_M_NOSTART)) { - u8 addr = (msg->addr << 1); - - if (msg->flags & I2C_M_RD) - addr |= 1; - - i2c->state = STATE_START; - - oc_setreg(i2c, OCI2C_DATA, addr); - oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START); - FPGA_I2C_DEBUG_XFER("send start, exit.\n"); - goto out; - } - - i2c->state = (msg->flags & I2C_M_RD) - ? STATE_READ : STATE_WRITE; - } else { - i2c->state = STATE_DONE; - oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); - FPGA_I2C_DEBUG_XFER("send OCI2C_CMD_STOP, exit.\n"); - goto out; - } - } - - if (i2c->state == STATE_READ) { - oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len-1) ? - OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK); - } else { - oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]); - oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE); - } - -out: - FPGA_I2C_DEBUG_XFER("normal, exit nr %d.\n", i2c->adap.nr); -} - -static irqreturn_t ocores_isr(int irq, void *dev_id) -{ - struct ocores_i2c *i2c = dev_id; - unsigned long flags; - u8 stat; - - if (!i2c) { - return IRQ_NONE; - } - /* - * If we spin here is because we are in timeout, so we are going - * to be in STATE_ERROR. See ocores_process_timeout() - */ - FPGA_I2C_SPIN_LOCK(i2c->process_lock, flags); - stat = oc_getreg(i2c, OCI2C_STATUS); - if (!(stat & OCI2C_STAT_IF)) { - g_irq_invalid_cnt++; - FPGA_I2C_SPIN_UNLOCK(i2c->process_lock, flags); - return IRQ_NONE; - } - - FPGA_I2C_DEBUG_XFER("Enter, irq %d nr %d addr 0x%x.\n", irq, i2c->adap.nr, (!i2c->msg)?0:i2c->msg->addr); - ocores_process(i2c, stat); - FPGA_I2C_DEBUG_XFER("Leave, irq %d nr %d addr 0x%x.\n", irq, i2c->adap.nr, (!i2c->msg)?0:i2c->msg->addr); - - FPGA_I2C_SPIN_UNLOCK(i2c->process_lock, flags); - return IRQ_HANDLED; -} - -/** - * Process timeout event - * @i2c: ocores I2C device instance - */ -static void ocores_process_timeout(struct ocores_i2c *i2c) -{ - unsigned long flags; - - FPGA_I2C_SPIN_LOCK(i2c->process_lock, flags); - FPGA_I2C_DEBUG_ERROR("wait_event_timeout i2c->state %d.\n", i2c->state); - oc_debug_dump_reg(i2c); - i2c->state = STATE_ERROR; - oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); - mdelay(1); - FPGA_I2C_SPIN_UNLOCK(i2c->process_lock, flags); -} - -static int check_ocores_i2c(struct i2c_msg *msgs, int num) -{ - int i; - if (!msgs) { - return -1; - } - for (i = 0; i < num; ++i) { - if (!msgs[i].buf) { - return -1; - } - } - return 0; -} - -static int ocores_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) -{ - struct ocores_i2c *i2c; - int ret; - unsigned long flags; - int xfer_ret; - - if (!adap || check_ocores_i2c(msgs, num) != 0) { - FPGA_I2C_DEBUG("msgs: %p , num:%d exit.\n", msgs, num); - return -EINVAL; - } - i2c = i2c_get_adapdata(adap); - - FPGA_I2C_MUTEX_LOCK(i2c->xfer_lock); - FPGA_I2C_SPIN_LOCK(i2c->process_lock, flags); - i2c->msg = msgs; - i2c->pos = 0; - i2c->nmsgs = num; - i2c->state = STATE_START; - FPGA_I2C_DEBUG_XFER("Enter, nr %d addr 0x%x num %d.\n", adap->nr, i2c->msg->addr, num); - - oc_setreg(i2c, OCI2C_DATA, - (i2c->msg->addr << 1) | - ((i2c->msg->flags & I2C_M_RD) ? 1:0)); - - oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START); - FPGA_I2C_DEBUG_XFER("After, oc_setreg OCI2C_CMD.\n"); - FPGA_I2C_SPIN_UNLOCK(i2c->process_lock, flags); - - ret = wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) || - (i2c->state == STATE_DONE), HZ); - - if (ret == 0) { - ocores_process_timeout(i2c); - FPGA_I2C_MUTEX_UNLOCK(i2c->xfer_lock); - return -ETIMEDOUT; - } - xfer_ret = i2c->state; - FPGA_I2C_MUTEX_UNLOCK(i2c->xfer_lock); - return (xfer_ret == STATE_DONE) ? num : -EIO; -} - -static void ocores_init(struct ocores_i2c *i2c) -{ - int prescale; - u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL); - - mutex_init(&i2c->xfer_lock); - spin_lock_init(&i2c->process_lock); - - /* make sure the device is disabled */ - oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN)); - - prescale = oc_set_scl_clk(i2c, DEFAULT_I2C_SCL); - FPGA_I2C_DEBUG_VERBOSE("i2c->base 0x%p, i2c->clock_khz %d, prescale 0x%x.\n", i2c->base, i2c->clock_khz, prescale); - - /* Init the device */ - oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK); - oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_IEN | OCI2C_CTRL_EN); -} - - -static u32 ocores_func(struct i2c_adapter *adap) -{ - return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; -} - -static const struct i2c_algorithm ocores_algorithm = { - .master_xfer = ocores_xfer, - .functionality = ocores_func, -}; - -static struct i2c_adapter ocores_adapter = { - .owner = THIS_MODULE, - .name = "rg-i2c-ocores", - .class = I2C_CLASS_HWMON | I2C_CLASS_SPD | I2C_CLASS_DEPRECATED, - .algo = &ocores_algorithm, -}; - -static const struct of_device_id ocores_i2c_match[] = { - { - .compatible = "opencores,rg-i2c-ocores", - .data = (void *)TYPE_OCORES, - }, - { - .compatible = "aeroflexgaisler,i2cmst", - .data = (void *)TYPE_GRLIB, - }, - {}, -}; -MODULE_DEVICE_TABLE(of, ocores_i2c_match); - -#ifdef CONFIG_OF -/* Read and write functions for the GRLIB port of the controller. Registers are - * 32-bit big endian and the PRELOW and PREHIGH registers are merged into one - * register. The subsequent registers has their offset decreased accordingly. */ -static u8 oc_getreg_grlib(struct ocores_i2c *i2c, int reg) -{ - u32 rd; - int rreg = reg; - if (reg != OCI2C_PRELOW) - rreg--; - rd = ioread32be(i2c->base + (rreg << i2c->reg_shift)); - if (reg == OCI2C_PREHIGH) - return (u8)(rd >> 8); - else - return (u8)rd; -} - -static void oc_setreg_grlib(struct ocores_i2c *i2c, int reg, u8 value) -{ - u32 curr, wr; - int rreg = reg; - if (reg != OCI2C_PRELOW) - rreg--; - if (reg == OCI2C_PRELOW || reg == OCI2C_PREHIGH) { - curr = ioread32be(i2c->base + (rreg << i2c->reg_shift)); - if (reg == OCI2C_PRELOW) - wr = (curr & 0xff00) | value; - else - wr = (((u32)value) << 8) | (curr & 0xff); - } else { - wr = value; - } - iowrite32be(wr, i2c->base + (rreg << i2c->reg_shift)); -} - -static int ocores_i2c_of_probe(struct platform_device *pdev, - struct ocores_i2c *i2c) -{ - struct device_node *np = pdev->dev.of_node; - const struct of_device_id *match; - u32 val; - - if (of_property_read_u32(np, "reg-shift", &i2c->reg_shift)) { - /* no 'reg-shift', check for deprecated 'regstep' */ - if (!of_property_read_u32(np, "regstep", &val)) { - if (!is_power_of_2(val)) { - dev_err(&pdev->dev, "invalid regstep %d\n", - val); - return -EINVAL; - } - i2c->reg_shift = ilog2(val); - dev_warn(&pdev->dev, - "regstep property deprecated, use reg-shift\n"); - } - } - - if (of_property_read_u32(np, "clock-frequency", &val)) { - dev_err(&pdev->dev, - "Missing required parameter 'clock-frequency'\n"); - return -ENODEV; - } - i2c->clock_khz = val / 1000; - - of_property_read_u32(pdev->dev.of_node, "reg-io-width", - &i2c->reg_io_width); - - match = of_match_node(ocores_i2c_match, pdev->dev.of_node); - if (match && (long)match->data == TYPE_GRLIB) { - dev_dbg(&pdev->dev, "GRLIB variant of i2c-ocores\n"); - i2c->setreg = oc_setreg_grlib; - i2c->getreg = oc_getreg_grlib; - } - - return 0; -} -#else -#define ocores_i2c_of_probe(pdev,i2c) -ENODEV -#endif - - -static void oc_debug_dump_reg_dump(struct ocores_i2c *i2c) -{ - if (i2c) { - FPGA_I2C_DEBUG("base: %p.\n", i2c->base); - FPGA_I2C_DEBUG("reg_shift: %d.\n", i2c->reg_shift); - FPGA_I2C_DEBUG("reg_io_width: %d.\n", i2c->reg_io_width); - FPGA_I2C_DEBUG("adap.nr: %d.\n", i2c->adap.nr); - FPGA_I2C_DEBUG("msg: %p.\n", i2c->msg); - if (i2c->msg) { - FPGA_I2C_DEBUG("msg->buf: %p.\n", i2c->msg->buf); - FPGA_I2C_DEBUG("msg->addr: 0x%x.\n", i2c->msg->addr); - FPGA_I2C_DEBUG("msg->flags: 0x%x.\n", i2c->msg->flags); - FPGA_I2C_DEBUG("msg->len: %d.\n", i2c->msg->len); - } else { - FPGA_I2C_DEBUG("msg: %p is null.\n", i2c->msg); - } - - FPGA_I2C_DEBUG("pos: %d.\n", i2c->pos); - FPGA_I2C_DEBUG("nmsgs: %d.\n", i2c->nmsgs); - FPGA_I2C_DEBUG("state: %d.\n", i2c->state); - FPGA_I2C_DEBUG("clock_khz: %d.\n", i2c->clock_khz); - FPGA_I2C_DEBUG("setreg: %p.\n", i2c->setreg); - FPGA_I2C_DEBUG("getreg: %p.\n", i2c->getreg); - if (i2c->getreg) { - FPGA_I2C_DEBUG("OCI2C_PRELOW: 0x%02x.\n", oc_getreg(i2c, OCI2C_PRELOW)); - FPGA_I2C_DEBUG("OCI2C_PREHIGH: 0x%02x.\n", oc_getreg(i2c, OCI2C_PREHIGH)); - FPGA_I2C_DEBUG("OCI2C_CONTROL: 0x%02x.\n", oc_getreg(i2c, OCI2C_CONTROL)); - FPGA_I2C_DEBUG("OCI2C_DATA: 0x%02x.\n", oc_getreg(i2c, OCI2C_DATA)); - FPGA_I2C_DEBUG("OCI2C_CMD: 0x%02x.\n", oc_getreg(i2c, OCI2C_CMD)); - FPGA_I2C_DEBUG("OCI2C_STATUS: 0x%02x.\n", oc_getreg(i2c, OCI2C_STATUS)); - } else { - FPGA_I2C_DEBUG("getreg: %p is null.\n", i2c->getreg); - } - } else { - FPGA_I2C_DEBUG("i2c %p is null.\n", i2c); - } -} - - -static void oc_debug_dump_reg(struct ocores_i2c *i2c) -{ - if (i2c) { - FPGA_I2C_DEBUG_DUMP("base: %p.\n", i2c->base); - FPGA_I2C_DEBUG_DUMP("reg_shift: %d.\n", i2c->reg_shift); - FPGA_I2C_DEBUG_DUMP("reg_io_width: %d.\n", i2c->reg_io_width); - FPGA_I2C_DEBUG_DUMP("adap.nr: %d.\n", i2c->adap.nr); - FPGA_I2C_DEBUG_DUMP("msg: %p.\n", i2c->msg); - if (i2c->msg) { - FPGA_I2C_DEBUG_DUMP("msg->buf: %p.\n", i2c->msg->buf); - FPGA_I2C_DEBUG_DUMP("msg->addr: 0x%x.\n", i2c->msg->addr); - FPGA_I2C_DEBUG_DUMP("msg->flags: 0x%x.\n", i2c->msg->flags); - FPGA_I2C_DEBUG_DUMP("msg->len: %d.\n", i2c->msg->len); - } else { - FPGA_I2C_DEBUG_DUMP("msg: %p is null.\n", i2c->msg); - } - - FPGA_I2C_DEBUG_DUMP("pos: %d.\n", i2c->pos); - FPGA_I2C_DEBUG_DUMP("nmsgs: %d.\n", i2c->nmsgs); - FPGA_I2C_DEBUG_DUMP("state: %d.\n", i2c->state); - FPGA_I2C_DEBUG_DUMP("clock_khz: %d.\n", i2c->clock_khz); - FPGA_I2C_DEBUG_DUMP("setreg: %p.\n", i2c->setreg); - FPGA_I2C_DEBUG_DUMP("getreg: %p.\n", i2c->getreg); - if (i2c->getreg) { - FPGA_I2C_DEBUG_DUMP("OCI2C_PRELOW: 0x%02x.\n", oc_getreg(i2c, OCI2C_PRELOW)); - FPGA_I2C_DEBUG_DUMP("OCI2C_PREHIGH: 0x%02x.\n", oc_getreg(i2c, OCI2C_PREHIGH)); - FPGA_I2C_DEBUG_DUMP("OCI2C_CONTROL: 0x%02x.\n", oc_getreg(i2c, OCI2C_CONTROL)); - FPGA_I2C_DEBUG_DUMP("OCI2C_DATA: 0x%02x.\n", oc_getreg(i2c, OCI2C_DATA)); - FPGA_I2C_DEBUG_DUMP("OCI2C_CMD: 0x%02x.\n", oc_getreg(i2c, OCI2C_CMD)); - FPGA_I2C_DEBUG_DUMP("OCI2C_STATUS: 0x%02x.\n", oc_getreg(i2c, OCI2C_STATUS)); - } else { - FPGA_I2C_DEBUG_DUMP("getreg: %p is null.\n", i2c->getreg); - } - } else { - FPGA_I2C_DEBUG_DUMP("i2c %p is null.\n", i2c); - } -} - -void oc_debug_dump_reg_exception(void) -{ - int bus_beg, bus_end, bus; - struct i2c_adapter *adap; - struct ocores_i2c *adap_data; - - bus_beg = 1; - bus_end = 14; - for (bus = bus_beg; bus <= bus_end; bus++) { - adap = i2c_get_adapter(bus); - if (adap) { - adap_data = (struct ocores_i2c *)i2c_get_adapdata(adap); - if (adap_data) { - FPGA_I2C_DEBUG_DUMP("bus %d call oc_debug_dump_reg begin.\n", bus); - oc_debug_dump_reg(adap_data); - FPGA_I2C_DEBUG_DUMP("bus %d call oc_debug_dump_reg end.\n", bus); - } else { - FPGA_I2C_DEBUG_DUMP("bus %d i2c_get_adapdata null.\n", bus); - } - i2c_put_adapter(adap); - } else { - FPGA_I2C_DEBUG_DUMP("bus %d i2c_get_adapter null.\n", bus); - } - } -} - -static int oc_calculate_prescale(struct ocores_i2c *i2c, int val) { - if (val <= 0) { - FPGA_I2C_DEBUG_ERROR("input scl clock error, set to default clock: %d.\n", val); - val = DEFAULT_I2C_SCL; - } - return (i2c->clock_khz / (5 * val)) - 1; -} - -static int oc_calculate_scl_clk(struct ocores_i2c *i2c, int prescale) { - if (prescale <= -1) { - FPGA_I2C_DEBUG_ERROR("input prescale error, set to default prescale: %d.\n", prescale); - prescale = DEFAULT_I2C_PRE; - } - return (i2c->clock_khz / (prescale + 1)) / 5; -} - -static int oc_set_scl_clk(struct ocores_i2c *i2c, int val) { - int prescale; - - prescale = oc_calculate_prescale(i2c, val); - oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff); - oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8); - return prescale; -} - -static int oc_get_scl_clk(struct ocores_i2c *i2c) { - int prescale, prescale_high, prescale_low; - - prescale_low = oc_getreg(i2c, OCI2C_PRELOW); - prescale_high = oc_getreg(i2c, OCI2C_PREHIGH); - prescale = (prescale_high << 8) + (prescale_low & 0xff); - - return oc_calculate_scl_clk(i2c, prescale); -} - -static ssize_t oc_sysfs_show_scl_clk(struct device *dev, struct device_attribute *attr, char *buf) -{ - struct i2c_adapter *adapter; - struct ocores_i2c *i2c; - int scl_clk; - - adapter = to_i2c_adapter(dev); - i2c = (struct ocores_i2c *)i2c_get_adapdata(adapter); - scl_clk = oc_get_scl_clk(i2c); - return snprintf(buf, BUF_SIZE, "%d\n", scl_clk); -} - -static ssize_t oc_sysfs_set_scl_clk(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) -{ - struct i2c_adapter *adapter; - struct ocores_i2c *i2c; - int val; - int ret; - int prescale; - - adapter = to_i2c_adapter(dev); - i2c = (struct ocores_i2c *)i2c_get_adapdata(adapter); - ret = kstrtoint(buf, 0, &val); - if (ret) { - return ret; - } - FPGA_I2C_MUTEX_LOCK(i2c->xfer_lock); - prescale = oc_set_scl_clk(i2c, val); - FPGA_I2C_DEBUG_VERBOSE("i2c->base 0x%p, i2c->clock_khz %d, scl clk 0x%x.\n", i2c->base, i2c->clock_khz, prescale); - FPGA_I2C_MUTEX_UNLOCK(i2c->xfer_lock); - return count; -} -static ssize_t show_oc_debug_value(struct device *dev, struct device_attribute *da, char *buf) -{ - oc_debug_dump_reg_exception(); - return 0; -} - -static SENSOR_DEVICE_ATTR(oc_debug, S_IRUGO | S_IWUSR, show_oc_debug_value, NULL, 0x15); -static SENSOR_DEVICE_ATTR(oc_scl_clk, S_IRUGO | S_IWUSR, oc_sysfs_show_scl_clk, oc_sysfs_set_scl_clk, 0); - -static struct attribute *oc_debug_sysfs_attrs[] = { - &sensor_dev_attr_oc_debug.dev_attr.attr, - NULL -}; - -static struct attribute *oc_scl_clk_sysfs_attrs[] = { - &sensor_dev_attr_oc_scl_clk.dev_attr.attr, - NULL -}; - -static const struct attribute_group oc_debug_sysfs_group = { - .attrs = oc_debug_sysfs_attrs, -}; - -static const struct attribute_group oc_scl_clk_sysfs_group = { - .attrs = oc_scl_clk_sysfs_attrs, -}; - -static void oc_scl_clk_sysfs_init(struct i2c_adapter *adap) -{ - int ret; - - ret = sysfs_create_group(&adap->dev.kobj, &oc_scl_clk_sysfs_group); - FPGA_I2C_DEBUG_VERBOSE("sysfs_create_group ret %d.\n", ret); - return; -} - -static void oc_scl_clk_sysfs_exit(struct i2c_adapter *adap) -{ - sysfs_remove_group(&adap->dev.kobj, (const struct attribute_group *)&oc_scl_clk_sysfs_group); - FPGA_I2C_DEBUG_VERBOSE("sysfs_remove_group.\n"); - return; -} - -static void oc_debug_sysfs_init(struct platform_device *pdev) -{ - int ret; - - ret = sysfs_create_group(&pdev->dev.kobj, &oc_debug_sysfs_group); - FPGA_I2C_DEBUG_VERBOSE("sysfs_create_group ret %d.\n", ret); - return; -} - -static void oc_debug_sysfs_exit(struct platform_device *pdev) -{ - sysfs_remove_group(&pdev->dev.kobj, (const struct attribute_group *)&oc_debug_sysfs_group); - FPGA_I2C_DEBUG_VERBOSE("sysfs_remove_group.\n"); - return; -} - -static int rg_ocores_i2c_probe(struct platform_device *pdev) -{ - struct ocores_i2c *i2c; - struct rg_ocores_i2c_platform_data *pdata; - struct resource *res; - int irq; - int ret; - int i; - - FPGA_I2C_DEBUG_VERBOSE("Enter.\n"); - irq = platform_get_irq(pdev, 0); - if (irq < 0) { - FPGA_I2C_DEBUG_ERROR("platform_get_irq failed irq %d.\n", irq); - return irq; - } - - i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); - if (!i2c) { - FPGA_I2C_DEBUG_ERROR("devm_kzalloc failed.\n"); - return -ENOMEM; - } - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - i2c->base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(i2c->base)) { - FPGA_I2C_DEBUG_ERROR("devm_ioremap_resource failed.\n"); - return PTR_ERR(i2c->base); - } - - pdata = dev_get_platdata(&pdev->dev); - if (pdata) { - i2c->reg_shift = pdata->reg_shift; - i2c->reg_io_width = pdata->reg_io_width; - i2c->clock_khz = pdata->clock_khz; - } else { - ret = ocores_i2c_of_probe(pdev, i2c); - if (ret) - return ret; - } - - if (i2c->reg_io_width == 0) - i2c->reg_io_width = 1; /* Set to default value */ - - - if (!i2c->setreg || !i2c->getreg) { - switch (i2c->reg_io_width) { - case 1: - i2c->setreg = oc_setreg_8; - i2c->getreg = oc_getreg_8; - break; - - case 2: - i2c->setreg = oc_setreg_16; - i2c->getreg = oc_getreg_16; - break; - - case 4: - i2c->setreg = oc_setreg_32; - i2c->getreg = oc_getreg_32; - break; - - default: - dev_err(&pdev->dev, "Unsupported I/O width (%d)\n", - i2c->reg_io_width); - return -EINVAL; - } - } - - ocores_init(i2c); - - init_waitqueue_head(&i2c->wait); - ret = devm_request_irq(&pdev->dev, irq, ocores_isr, 0, - pdev->name, i2c); - if (ret) { - dev_err(&pdev->dev, "Cannot claim IRQ\n"); - return ret; - } - - /* hook up driver to tree */ - platform_set_drvdata(pdev, i2c); - i2c->adap = ocores_adapter; - if (pdata->nr) { - i2c->adap.nr = pdata->nr; - dev_info(&pdev->dev, "fpga ocores nr is (%d), irq %d \n", i2c->adap.nr, irq); - } - i2c_set_adapdata(&i2c->adap, i2c); - i2c->adap.dev.parent = &pdev->dev; - i2c->adap.dev.of_node = pdev->dev.of_node; - - /* add i2c adapter to i2c tree */ - ret = i2c_add_numbered_adapter(&i2c->adap); - if (ret) { - dev_err(&pdev->dev, "Failed to add adapter\n"); - return ret; - } - - /* add in known devices to the bus */ - if (pdata) { - for (i = 0; i < pdata->num_devices; i++) { -#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0) - i2c_new_client_device(&i2c->adap, pdata->devices + i); -#else - i2c_new_device(&i2c->adap, pdata->devices + i); -#endif - } - } - - oc_debug_sysfs_init(pdev); - oc_scl_clk_sysfs_init(&i2c->adap); - return 0; -} - -static int rg_ocores_i2c_remove(struct platform_device *pdev) -{ - struct ocores_i2c *i2c = platform_get_drvdata(pdev); - - /* disable i2c logic */ - oc_setreg(i2c, OCI2C_CONTROL, oc_getreg(i2c, OCI2C_CONTROL) - & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN)); - - /* remove adapter & data */ - oc_scl_clk_sysfs_exit(&i2c->adap); - i2c_del_adapter(&i2c->adap); - oc_debug_sysfs_exit(pdev); - - return 0; -} - -#ifdef CONFIG_PM_SLEEP -static int ocores_i2c_suspend(struct device *dev) -{ - struct ocores_i2c *i2c = dev_get_drvdata(dev); - u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL); - - /* make sure the device is disabled */ - oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN)); - - return 0; -} - -static int ocores_i2c_resume(struct device *dev) -{ - struct ocores_i2c *i2c = dev_get_drvdata(dev); - - ocores_init(i2c); - - return 0; -} - -static SIMPLE_DEV_PM_OPS(ocores_i2c_pm, ocores_i2c_suspend, ocores_i2c_resume); -#define OCORES_I2C_PM (&ocores_i2c_pm) -#else -#define OCORES_I2C_PM NULL -#endif - -static struct platform_driver ocores_i2c_driver = { - .probe = rg_ocores_i2c_probe, - .remove = rg_ocores_i2c_remove, - .driver = { - .owner = THIS_MODULE, - .name = "rg-i2c-ocores", - .of_match_table = ocores_i2c_match, - .pm = OCORES_I2C_PM, - }, -}; - -module_platform_driver(ocores_i2c_driver); - -MODULE_AUTHOR("Peter Korsgaard "); -MODULE_DESCRIPTION("OpenCores I2C bus driver"); -MODULE_LICENSE("GPL"); -MODULE_ALIAS("platform:ocores-i2c"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/fpga_i2c_ocores.h b/platform/broadcom/sonic-platform-modules-ragile/common/modules/fpga_i2c_ocores.h deleted file mode 100755 index 1aedd7793c77..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/common/modules/fpga_i2c_ocores.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef _FPGA_I2C_OCORES_H -#define _FPGA_I2C_OCORES_H - -struct rg_ocores_i2c_platform_data { - u32 reg_shift; /* register offset shift value */ - u32 reg_io_width; /* register io read/write width */ - u32 clock_khz; /* input clock in kHz */ - u8 num_devices; /* number of devices in the devices list */ - struct i2c_board_info const *devices; /* devices connected to the bus */ - int nr; /* i2c bus num */ -}; - -#endif /* _FPGA_I2C_OCORES_H */ diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/fpga_pcie_i2c.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/fpga_pcie_i2c.c deleted file mode 100755 index 669198ca59fd..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/common/modules/fpga_pcie_i2c.c +++ /dev/null @@ -1,1144 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "fpga_i2c_ocores.h" -#include "fpga_pcie_i2c.h" -#include "fpga_reg_defs.h" - -#include -#include -#if LINUX_VERSION_CODE > KERNEL_VERSION(4, 15, 0) -#include -#else -#include -#endif -#include -#include -#include - - -#ifdef FPGA_PCIE_I2C_DEBUG -#include -#include -#include -#include -#include - -char *enum_log="/home/pciuio-log"; - -void filewrite(char* filename, char* data) -{ - struct file *filp; - mm_segment_t fs; - filp = filp_open(filename, O_RDWR|O_APPEND|O_CREAT, 0644); - if(IS_ERR(filp)) - { - printk("<0>""open file error...\n"); - return; - } - - fs=get_fs(); - set_fs(KERNEL_DS); - filp->f_op->write(filp, data, strlen(data),&filp->f_pos); - set_fs(fs); - filp_close(filp,NULL); -} - -void enum_time_log(char *log) -{ - struct timex txc; - struct rtc_time tm; - char time_str[64]; - int ret = 0; - - do_gettimeofday(&(txc.time)); - rtc_time_to_tm(txc.time.tv_sec,&tm); - memset(time_str, 0x0, 64); - ret = sprintf(time_str, "UTC time:%d-%d-%d %d:%d:%d ", - tm.tm_year+1900, tm.tm_mon, tm.tm_mday, tm.tm_hour, tm.tm_min, tm.tm_sec); - - filewrite(enum_log, time_str); - filewrite(enum_log, log); -} - -void enum_notime_log(char *log) -{ - filewrite(enum_log, log); -} -#else -void enum_time_log(char *log) -{ - return; -} -void enum_notime_log(char *log) -{ - return; -} -#endif - - -static void __iomem *g_fpga_pcie_mem_base = NULL; - -int g_fpga_pcie_debug = 0; -int g_fpga_pcie_error = 0; -int g_fpga_pcie_reset_en = 0; -int ocore_ctl_startbus = 1; -int ocore_ctl_numbers = 14; -module_param(g_fpga_pcie_reset_en, int, S_IRUGO | S_IWUSR); -module_param(g_fpga_pcie_debug, int, S_IRUGO | S_IWUSR); -module_param(g_fpga_pcie_error, int, S_IRUGO | S_IWUSR); -module_param(ocore_ctl_startbus, int, S_IRUGO | S_IWUSR); -module_param(ocore_ctl_numbers, int, S_IRUGO | S_IWUSR); - - -#define FPGA_PCIE_DEBUG_VERBOSE(fmt, args...) do { \ - if (g_fpga_pcie_debug) { \ - printk(KERN_ERR "[FPGA_PCIE][VER][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ - } \ -} while (0) - -#define FPGA_PCIE_DEBUG_ERROR(fmt, args...) do { \ - if (g_fpga_pcie_error) { \ - printk(KERN_ERR "[FPGA_PCIE][ERR][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ - } \ -} while (0) - -#define FPGA_MSI_IRQ_NUM (ocore_ctl_numbers) -#define FPGA_MSI_IRQ_BEGIN (0) -#define FPGA_MSI_IRQ_END ((FPGA_MSI_IRQ_BEGIN) + (FPGA_MSI_IRQ_NUM)) -#define FPGA_I2C_OCORE_START_BASE (0x800) -#define FPGA_I2C_OCORE_END_BASE (0x81f) -#define FPGA_I2C_OCORE_CTRL_SIZE (0x20) -#define FPGA_I2C_OCORE_CTRL_START(id) ((FPGA_I2C_OCORE_START_BASE) + (id) * (FPGA_I2C_OCORE_CTRL_SIZE)) -#define FPGA_I2C_OCORE_CTRL_END(id) ((FPGA_I2C_OCORE_END_BASE) + (id) * (FPGA_I2C_OCORE_CTRL_SIZE)) -#define FPGA_I2C_OCORE_CTRL_IRQ(id) (id) - - -#define DEFINE_FPGA_PCIE_OCORE_DATA(_id) \ - static struct rg_ocores_i2c_platform_data rg_i2c_ocore_pdata_##_id = { \ - .reg_shift = 0, \ - .reg_io_width = 4, \ - .clock_khz = 125000, \ - .num_devices = 0, \ - }; - -DEFINE_FPGA_PCIE_OCORE_DATA(0); -DEFINE_FPGA_PCIE_OCORE_DATA(1); -DEFINE_FPGA_PCIE_OCORE_DATA(2); -DEFINE_FPGA_PCIE_OCORE_DATA(3); -DEFINE_FPGA_PCIE_OCORE_DATA(4); -DEFINE_FPGA_PCIE_OCORE_DATA(5); -DEFINE_FPGA_PCIE_OCORE_DATA(6); -DEFINE_FPGA_PCIE_OCORE_DATA(7); -DEFINE_FPGA_PCIE_OCORE_DATA(8); -DEFINE_FPGA_PCIE_OCORE_DATA(9); -DEFINE_FPGA_PCIE_OCORE_DATA(10); -DEFINE_FPGA_PCIE_OCORE_DATA(11); -DEFINE_FPGA_PCIE_OCORE_DATA(12); -DEFINE_FPGA_PCIE_OCORE_DATA(13); -DEFINE_FPGA_PCIE_OCORE_DATA(14); -DEFINE_FPGA_PCIE_OCORE_DATA(15); -DEFINE_FPGA_PCIE_OCORE_DATA(16); -DEFINE_FPGA_PCIE_OCORE_DATA(17); -DEFINE_FPGA_PCIE_OCORE_DATA(18); -DEFINE_FPGA_PCIE_OCORE_DATA(19); -DEFINE_FPGA_PCIE_OCORE_DATA(20); -DEFINE_FPGA_PCIE_OCORE_DATA(21); -DEFINE_FPGA_PCIE_OCORE_DATA(22); -DEFINE_FPGA_PCIE_OCORE_DATA(23); -DEFINE_FPGA_PCIE_OCORE_DATA(24); -DEFINE_FPGA_PCIE_OCORE_DATA(25); -DEFINE_FPGA_PCIE_OCORE_DATA(26); -DEFINE_FPGA_PCIE_OCORE_DATA(27); - -#define DEFINE_FPGA_PCIE_I2C_OCORE_RESOURCES(_id) \ - static const struct resource fpga_pcie_i2c_ocores_resources_##_id[] = { \ - { \ - .start = FPGA_I2C_OCORE_CTRL_START(_id), \ - .end = FPGA_I2C_OCORE_CTRL_END(_id), \ - .flags = IORESOURCE_MEM, \ - }, \ - { \ - .start = FPGA_I2C_OCORE_CTRL_IRQ(_id), \ - .end = FPGA_I2C_OCORE_CTRL_IRQ(_id), \ - .flags = IORESOURCE_IRQ, \ - }, \ - } - -DEFINE_FPGA_PCIE_I2C_OCORE_RESOURCES(0); -DEFINE_FPGA_PCIE_I2C_OCORE_RESOURCES(1); -DEFINE_FPGA_PCIE_I2C_OCORE_RESOURCES(2); -DEFINE_FPGA_PCIE_I2C_OCORE_RESOURCES(3); -DEFINE_FPGA_PCIE_I2C_OCORE_RESOURCES(4); -DEFINE_FPGA_PCIE_I2C_OCORE_RESOURCES(5); -DEFINE_FPGA_PCIE_I2C_OCORE_RESOURCES(6); -DEFINE_FPGA_PCIE_I2C_OCORE_RESOURCES(7); -DEFINE_FPGA_PCIE_I2C_OCORE_RESOURCES(8); -DEFINE_FPGA_PCIE_I2C_OCORE_RESOURCES(9); -DEFINE_FPGA_PCIE_I2C_OCORE_RESOURCES(10); -DEFINE_FPGA_PCIE_I2C_OCORE_RESOURCES(11); -DEFINE_FPGA_PCIE_I2C_OCORE_RESOURCES(12); -DEFINE_FPGA_PCIE_I2C_OCORE_RESOURCES(13); -DEFINE_FPGA_PCIE_I2C_OCORE_RESOURCES(14); -DEFINE_FPGA_PCIE_I2C_OCORE_RESOURCES(15); -DEFINE_FPGA_PCIE_I2C_OCORE_RESOURCES(16); -DEFINE_FPGA_PCIE_I2C_OCORE_RESOURCES(17); -DEFINE_FPGA_PCIE_I2C_OCORE_RESOURCES(18); -DEFINE_FPGA_PCIE_I2C_OCORE_RESOURCES(19); -DEFINE_FPGA_PCIE_I2C_OCORE_RESOURCES(20); -DEFINE_FPGA_PCIE_I2C_OCORE_RESOURCES(21); -DEFINE_FPGA_PCIE_I2C_OCORE_RESOURCES(22); -DEFINE_FPGA_PCIE_I2C_OCORE_RESOURCES(23); -DEFINE_FPGA_PCIE_I2C_OCORE_RESOURCES(24); -DEFINE_FPGA_PCIE_I2C_OCORE_RESOURCES(25); -DEFINE_FPGA_PCIE_I2C_OCORE_RESOURCES(26); -DEFINE_FPGA_PCIE_I2C_OCORE_RESOURCES(27); - -#define DEFINE_FPGA_PCIE_MFD_CELL_CFG(_id) \ -{ \ - .name = "rg-i2c-ocores", \ - .id = (_id), \ - .num_resources = ARRAY_SIZE(fpga_pcie_i2c_ocores_resources_##_id), \ - .resources = fpga_pcie_i2c_ocores_resources_##_id, \ - .platform_data = &rg_i2c_ocore_pdata_##_id, \ - .pdata_size = sizeof(rg_i2c_ocore_pdata_##_id), \ -} - - -static const struct mfd_cell fpga_pcie_cells_bar0_cfg0[] = { - DEFINE_FPGA_PCIE_MFD_CELL_CFG(0), - DEFINE_FPGA_PCIE_MFD_CELL_CFG(1), - DEFINE_FPGA_PCIE_MFD_CELL_CFG(2), - DEFINE_FPGA_PCIE_MFD_CELL_CFG(3), - DEFINE_FPGA_PCIE_MFD_CELL_CFG(4), - DEFINE_FPGA_PCIE_MFD_CELL_CFG(5), - DEFINE_FPGA_PCIE_MFD_CELL_CFG(6), - DEFINE_FPGA_PCIE_MFD_CELL_CFG(7), - DEFINE_FPGA_PCIE_MFD_CELL_CFG(8), - DEFINE_FPGA_PCIE_MFD_CELL_CFG(9), - DEFINE_FPGA_PCIE_MFD_CELL_CFG(10), - DEFINE_FPGA_PCIE_MFD_CELL_CFG(11), - DEFINE_FPGA_PCIE_MFD_CELL_CFG(12), - DEFINE_FPGA_PCIE_MFD_CELL_CFG(13), - DEFINE_FPGA_PCIE_MFD_CELL_CFG(14), - DEFINE_FPGA_PCIE_MFD_CELL_CFG(15), - DEFINE_FPGA_PCIE_MFD_CELL_CFG(16), - DEFINE_FPGA_PCIE_MFD_CELL_CFG(17), - DEFINE_FPGA_PCIE_MFD_CELL_CFG(18), - DEFINE_FPGA_PCIE_MFD_CELL_CFG(19), - DEFINE_FPGA_PCIE_MFD_CELL_CFG(20), - DEFINE_FPGA_PCIE_MFD_CELL_CFG(21), - DEFINE_FPGA_PCIE_MFD_CELL_CFG(22), - DEFINE_FPGA_PCIE_MFD_CELL_CFG(23), - DEFINE_FPGA_PCIE_MFD_CELL_CFG(24), - DEFINE_FPGA_PCIE_MFD_CELL_CFG(25), - DEFINE_FPGA_PCIE_MFD_CELL_CFG(26), - DEFINE_FPGA_PCIE_MFD_CELL_CFG(27), -}; - -struct rgde_dev { - struct uio_info info; - struct pci_dev *pdev; - struct list_head list; - enum xdk_intr_mode mode; -}; - -#if LINUX_VERSION_CODE < KERNEL_VERSION(4,0,36) -/* XXX taken from uio.c, just for dumping */ -struct uio_device { - struct module *owner; - struct device *dev; - int minor; - atomic_t event; - struct fasync_struct *async_queue; - wait_queue_head_t wait; - struct uio_info *info; - struct kobject *map_dir; - struct kobject *portio_dir; -}; -#else -/* do noting add tjm */ -#endif - - -static char *intr_mode; -static enum xdk_intr_mode intr_mode_preferred = XDK_INTR_MODE_MSIX; - - -static struct list_head rgde_dev_que; - -static int rgde_dev_list_dump(void) -{ - char str[256]; - struct rgde_dev *node, *tmp; - struct uio_device *udev; - - list_for_each_entry_safe(node, tmp, &rgde_dev_que, list) { - udev = node->info.uio_dev; - memset(str, 0x0, 256); - sprintf(str, "pciuio device minor:%d\n", udev->minor); - enum_notime_log(str); - } - return 0; -} - -void rgde_dev_que_add(struct rgde_dev *uiodev) -{ - struct rgde_dev *node, *tmp; - - if (uiodev == NULL) { - return; - } - - if (list_empty(&rgde_dev_que)) { - list_add(&uiodev->list, &rgde_dev_que); - return; - } - - list_for_each_entry_safe(node, tmp, &rgde_dev_que, list) { - if (((node->info).uio_dev)->minor > ((uiodev->info).uio_dev)->minor) { - break; - } - } - list_add_tail(&uiodev->list, &node->list); - - return; -} - - -void rgde_dev_que_del(struct rgde_dev *uiodev) -{ - struct rgde_dev *node, *tmp; - - if (uiodev == NULL) { - return; - } - - list_for_each_entry_safe(node, tmp, &rgde_dev_que, list) { - if (((node->info).uio_dev)->minor == ((uiodev->info).uio_dev)->minor) { - list_del(&node->list); - break; - } - } - - return; -} - - -struct pci_dev *rgde_to_pci_device(int minor) -{ - - struct rgde_dev *node, *tmp; - - list_for_each_entry_safe(node, tmp, &rgde_dev_que, list) { - if (node->info.uio_dev->minor == minor) { - return node->pdev; - } - - if (node->info.uio_dev->minor < minor) { - return NULL; - } - } - - return NULL; -} -EXPORT_SYMBOL(rgde_to_pci_device); - -int pkt_get_mod(int logic_dev, int *mod) -{ - *mod = 0; - return 0; -} -EXPORT_SYMBOL(pkt_get_mod); - -int pkt_get_port(int logic_dev, int *port) -{ - *port = 1; - return 0; -} -EXPORT_SYMBOL(pkt_get_port); - -static int rgde_intr_mode_config(char *intr_str) -{ -#if 0 - /* default intr mode : msix */ - if (!intr_str) { - return 0; - } - - if (!strcmp(intr_str, INTR_MODE_MSIX_NAME)) { - intr_mode_preferred = XDK_INTR_MODE_MSIX; - return 0; - } - - if (!strcmp(intr_str, INTR_MODE_LEGACY_NAME)) { - intr_mode_preferred = XDK_INTR_MODE_LEGACY; - return 0; - } - - /* For now, msix & legacy mode supported only. */ - printk("<0>""Error: bad parameter - %s\n", intr_str); - return -EINVAL; -#else - intr_mode_preferred = XDK_INTR_MODE_LEGACY; - return 0; -#endif -} - -/* Remap pci resources described by bar #pci_bar in uio resource n. */ -static int rgde_setup_iomem(struct pci_dev *dev, struct uio_info *info, - int n, int pci_bar, const char *name) -{ - unsigned long addr, len; - void *internal_addr; - - if (n >= ARRAY_SIZE(info->mem)) { - return -EINVAL; - } - - addr = pci_resource_start(dev, pci_bar); - FPGA_PCIE_DEBUG_VERBOSE("iomem phys addr:%lx\n", addr); - len = pci_resource_len(dev, pci_bar); - if (addr == 0 || len == 0) { - return -1; - } - - - internal_addr = ioremap(addr, len); - FPGA_PCIE_DEBUG_VERBOSE("iomem phys addr:0x%lx, len 0x%lx, internal_addr %p.\n", addr, len, internal_addr); - - if (internal_addr == NULL) { - return -1; - } - - FPGA_PCIE_DEBUG_VERBOSE("iomem internal_addr:%p\n", internal_addr); - if (pci_bar == 0) { - - g_fpga_pcie_mem_base = internal_addr; - FPGA_PCIE_DEBUG_VERBOSE("pci_bar %d, set g_fpga_pcie_mem_base %p\n", pci_bar, g_fpga_pcie_mem_base); - } - info->mem[n].name = name; - info->mem[n].addr = addr; - info->mem[n].internal_addr = internal_addr; - info->mem[n].size = len; - info->mem[n].memtype = UIO_MEM_PHYS; - - return 0; -} - -/* Unmap previously ioremap'd resources */ -static void rgde_release_iomem(struct uio_info *info) -{ - int i; - - for (i = 0; i < MAX_UIO_MAPS; i++) { - if (info->mem[i].internal_addr) { - iounmap(info->mem[i].internal_addr); - } - } -} - -/* Get pci port io resources described by bar #pci_bar in uio resource n. */ -static int rgde_setup_ioport(struct pci_dev *dev, struct uio_info *info, - int n, int pci_bar, const char *name) -{ - unsigned long addr, len; - - if (n >= ARRAY_SIZE(info->port)) { - return -EINVAL; - } - - addr = pci_resource_start(dev, pci_bar); - len = pci_resource_len(dev, pci_bar); - if (addr == 0 || len == 0) { - return -EINVAL; - } - - info->port[n].name = name; - info->port[n].start = addr; - info->port[n].size = len; - /* skl : FIX me */ - info->port[n].porttype = UIO_PORT_X86; - - return 0; -} - -static int rgde_setup_bars(struct pci_dev *dev, struct uio_info *info) -{ - int i, iom, iop, ret; - unsigned long flags; - static const char *bar_names[PCI_STD_RESOURCE_END + 1] = { - "BAR0", "BAR1", "BAR2", "BAR3", "BAR4", "BAR5", - }; - iom = 0; - iop = 0; - - for (i = 0; i < ARRAY_SIZE(bar_names); i++) { - if (pci_resource_len(dev, i) != 0 && pci_resource_start(dev, i) != 0) { - - flags = pci_resource_flags(dev, i); - FPGA_PCIE_DEBUG_VERBOSE("flags:%lx\n", flags); - if (flags & IORESOURCE_MEM) { - ret = rgde_setup_iomem(dev, info, iom, i, bar_names[i]); - if (ret != 0) { - return ret; - } - iom++; - } else if (flags & IORESOURCE_IO) { - ret = rgde_setup_ioport(dev, info, iop, i, bar_names[i]); - if (ret != 0) { - return ret; - } - iop++; - } - } - } - - return (iom != 0 || iop != 0) ? ret : -ENOENT; -} - -/** - * This is interrupt handler which will check if the interrupt is for the right device. - * If yes, disable it here and will be enable later. - */ -static irqreturn_t rgde_irqhandler(int irq, struct uio_info *info) -{ - struct rgde_dev *udev = info->priv; - - if (udev->mode == XDK_INTR_MODE_LEGACY /*&& !pci_check_and_mask_intx(udev->pdev)*/) { - return IRQ_NONE; - } - - return IRQ_HANDLED; -} - -/* - * It masks the msix on/off of generating MSI-X messages. - */ -static void rgde_msix_mask_irq(struct msi_desc *desc, int32_t state) -{ - u32 mask_bits = desc->masked; - unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE + - PCI_MSIX_ENTRY_VECTOR_CTRL; - - if (state != 0) { - mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT; - } else { - mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT; - } - - if (mask_bits != desc->masked) { - writel(mask_bits, desc->mask_base + offset); - readl(desc->mask_base); - desc->masked = mask_bits; - } -} - -/** - * This is the irqcontrol callback to be registered to uio_info. - * It can be used to disable/enable interrupt from user space processes. - * - * @param info - * pointer to uio_info. - * @param irq_state - * state value. 1 to enable interrupt, 0 to disable interrupt. - * - * @return - * - On success, 0. - * - On failure, a negative value. - */ -static int rgde_irqcontrol(struct uio_info *info, s32 irq_state) -{ - struct rgde_dev *udev = info->priv; - struct pci_dev *pdev = udev->pdev; - - /* pci_cfg_access_lock(pdev); */ - - if (udev->mode == XDK_INTR_MODE_LEGACY) { - pci_intx(pdev, !!irq_state); - } else if (udev->mode == XDK_INTR_MODE_MSIX) { - struct msi_desc *desc; -#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 3, 0)) - list_for_each_entry(desc, &pdev->msi_list, list) { - rgde_msix_mask_irq(desc, irq_state); - } -#else - list_for_each_entry(desc, &pdev->dev.msi_list, list) { - rgde_msix_mask_irq(desc, irq_state); - } -#endif - } - - //pci_cfg_access_unlock(pdev); - - return 0; -} - -int rgde_reg32_read(int minor, uint64_t offset, uint32_t *data) -{ - struct rgde_dev *node, *tmp; - struct rgde_dev *uiodev; - - FPGA_PCIE_DEBUG_VERBOSE("enter rgde_reg32_read\n"); - uiodev = NULL; - list_for_each_entry_safe(node, tmp, &rgde_dev_que, list) { - if (((node->info).uio_dev)->minor == minor) { - uiodev = node; - break; - } - } - - if (uiodev == NULL) { - return -1; - } - - if (uiodev->info.mem[0].internal_addr == NULL) { - return -1; - } - -#if 0 - FPGA_PCIE_DEBUG_VERBOSE("internal_addr:%x\n", uiodev->info.mem[0].internal_addr); - - memcpy(ioval, (uint8_t *)uiodev->info.mem[0].internal_addr + offset, sizeof(ioval)); - for (i = 0; i < sizeof(ioval); i++) { - FPGA_PCIE_DEBUG_VERBOSE("mem[%x]:%02x\n", (uint32_t)(offset + i), ioval[i]); - } -#endif - - *data = (*((uint32_t *)((uint8_t *)(uiodev->info.mem[0].internal_addr) + offset))); - return 0; -} -EXPORT_SYMBOL(rgde_reg32_read); - -int rgde_reg32_write(int minor, uint64_t offset, uint32_t data) -{ - struct rgde_dev *node, *tmp; - struct rgde_dev *uiodev; - - uiodev = NULL; - list_for_each_entry_safe(node, tmp, &rgde_dev_que, list) { - if (((node->info).uio_dev)->minor == minor) { - uiodev = node; - break; - } - } - - if (uiodev == NULL) { - return -1; - } - - if (uiodev->info.mem[0].internal_addr == NULL) { - return -1; - } - - FPGA_PCIE_DEBUG_VERBOSE("enter rgde_reg32_write\n"); - FPGA_PCIE_DEBUG_VERBOSE("internal_addr:%p,offset:%llx,data:%x\n", uiodev->info.mem[0].internal_addr, offset, data); - - *((uint32_t *)((uint8_t *)(uiodev->info.mem[0].internal_addr) + offset)) = (data); - FPGA_PCIE_DEBUG_VERBOSE("rgde_reg32_write ok!\n"); - return 0; -} -EXPORT_SYMBOL(rgde_reg32_write); - -#if 0 -static void rgde_dump_global_regs(int minor) -{ - struct rgde_dev *node, *tmp; - struct rgde_dev *uiodev; - uint8_t ioval[4]; - int i, j; - - - uiodev = NULL; - list_for_each_entry_safe(node, tmp, &rgde_dev_que, list) { - if (((node->info).uio_dev)->minor == minor) { - uiodev = node; - break; - } - } - - if (uiodev == NULL) { - return ; - } - - if (uiodev->info.mem[0].internal_addr == NULL) { - return ; - } - - FPGA_PCIE_DEBUG_VERBOSE("internal_addr:%p\n", uiodev->info.mem[0].internal_addr); - for (j = 0; j < sizeof(uint32_t) * 6; j += sizeof(uint32_t)) { - memcpy(ioval, (uint8_t *)uiodev->info.mem[0].internal_addr + j, sizeof(ioval)); - for (i = 0; i < sizeof(ioval); i++) { - FPGA_PCIE_DEBUG_VERBOSE("mem[%d]:%02x\n", (uint32_t)(j + i), ioval[i]); - } - } - - return; -} -#endif - -#if 1 - -#define FPGA_PCIE_TEST_REG (0x08) -#define FPGA_PCIE_TEST_VAL (0x5A) - -#define FPGA_PCIE_RESET_PCA9548_BASE (0x20) -#define FPGA_PCIE_RESET_PCA9548_NUM (0x4) -#define FPGA_PCIE_RESET_OCORE_BASE (0x100) -#define FPGA_PCIE_RESET_OCORE_NUM (ocore_ctl_numbers) - -#define FPGA_PCIE_RESET_CPLD_I2C_BASE (0x40) -#define FPGA_PCIE_RESET_CPLD_I2C_NUM (0x4) - - -#define FPGA_PCIE_REG_STEP (0x4) - -#define DFD_CPLD_I2C_RETRY_TIMES 3 -#define DFD_CPLD_I2C_RETRY_DELAY 100 /* ms */ - -#define PCA9548_MAX_CPLD_NUM (32) - -typedef struct fpga_pcie_pca9548_cfg_info_s { - int pca9548_bus; - int pca9548_addr; - int cfg_offset; -} fpga_pcie_pca9548_cfg_info_t; - -typedef struct fpga_pcie_card_info_s { - int dev_type; - fpga_pcie_pca9548_cfg_info_t pca9548_cfg_info[PCA9548_MAX_CPLD_NUM]; -} fpga_pcie_card_info_t; - -static fpga_pcie_card_info_t g_fpga_pcie_card_info[] = { - { - /* RA-B6510-32C */ - .dev_type = 0x404b, - .pca9548_cfg_info = { - { - .pca9548_bus = 12, - .pca9548_addr = 0x70, - .cfg_offset = 0x20, - }, - { - .pca9548_bus = 12, - .pca9548_addr = 0x71, - .cfg_offset = 0x20, - }, - { - .pca9548_bus = 12, - .pca9548_addr = 0x72, - .cfg_offset = 0x20, - }, - { - .pca9548_bus = 12, - .pca9548_addr = 0x73, - .cfg_offset = 0x20, - }, - }, - }, -}; - -extern void pca954x_hw_do_reset_func_register(void* func); -extern int dfd_get_my_card_type(void); - -static void fpga_pcie_setreg_32(int offset, u32 data) -{ - if (g_fpga_pcie_mem_base) { - *((uint32_t *)((uint8_t *)(g_fpga_pcie_mem_base) + offset)) = (data); - } else { - FPGA_PCIE_DEBUG_ERROR("g_fpga_pcie_mem_base is null.\n"); - } - return; -} - - -static inline u32 fpga_pcie_getreg_32(int offset) -{ - u32 data = 0; - - if (g_fpga_pcie_mem_base) { - data = (*((uint32_t *)((uint8_t *)(g_fpga_pcie_mem_base) + offset))); - } else { - FPGA_PCIE_DEBUG_ERROR("g_fpga_pcie_mem_base is null.\n"); - } - return data; -} - -static void fpga_do_cpld_i2c_ctrl(int en) -{ -#if 0 - int i; - int offset; - - for (i = 0; i < FPGA_PCIE_RESET_CPLD_I2C_NUM; i++) { - offset = FPGA_PCIE_RESET_CPLD_I2C_BASE + i * FPGA_PCIE_REG_STEP; - FPGA_PCIE_DEBUG_VERBOSE("offset 0x%x, write en 0x%x.\n", offset, en); - fpga_pcie_setreg_32(offset, en); - } -#endif - return; -} - - -static void fpga_do_ocore_ctrl(int en) -{ - int i; - int offset; - - for (i = 0; i < FPGA_PCIE_RESET_OCORE_NUM; i++) { - offset = FPGA_PCIE_RESET_OCORE_BASE + i * FPGA_PCIE_REG_STEP; - FPGA_PCIE_DEBUG_VERBOSE("offset 0x%x, write en 0x%x.\n", offset, en); - fpga_pcie_setreg_32(offset, en); - } -} - -static void fpga_do_9548_ctrl(int en) -{ - int i; - int offset; - - for (i = 0; i < FPGA_PCIE_RESET_PCA9548_NUM; i++) { - offset = FPGA_PCIE_RESET_PCA9548_BASE + i * FPGA_PCIE_REG_STEP; - FPGA_PCIE_DEBUG_VERBOSE("offset 0x%x, write en 0x%x.\n", offset, en); - fpga_pcie_setreg_32(offset, en); - } - -} - -static void fpga_reset_ocore_i2c(void) -{ - u32 data; - - - if (g_fpga_pcie_reset_en == 0) { - FPGA_PCIE_DEBUG_VERBOSE("g_fpga_pcie_reset_en is 0, do nothing.\n"); - return; - } - - data = fpga_pcie_getreg_32(FPGA_PCIE_TEST_REG); - FPGA_PCIE_DEBUG_VERBOSE("BEGIN FPGA_PCIE_TEST_REG=[0x%x], write 0x%x.\n", data, FPGA_PCIE_TEST_VAL); - fpga_pcie_setreg_32(FPGA_PCIE_TEST_REG, FPGA_PCIE_TEST_VAL); - data = fpga_pcie_getreg_32(FPGA_PCIE_TEST_REG); - FPGA_PCIE_DEBUG_VERBOSE("END FPGA_PCIE_TEST_REG=[0x%x].\n", data); - - - - fpga_do_9548_ctrl(0); - fpga_do_ocore_ctrl(0); - fpga_do_cpld_i2c_ctrl(0); - - mdelay(500); - - - fpga_do_9548_ctrl(1); - fpga_do_ocore_ctrl(1); - fpga_do_cpld_i2c_ctrl(1); - - return; -} - -static void fpga_do_pca9548_reset_ctrl(int offset, int en) -{ - FPGA_PCIE_DEBUG_VERBOSE("offset 0x%x, write en 0x%x.\n", offset, en); - fpga_pcie_setreg_32(offset, en); -} - -fpga_pcie_card_info_t* fpga_pcie_get_card_info(int dev_type) -{ - int i; - int size; - - size = ARRAY_SIZE(g_fpga_pcie_card_info); - - FPGA_PCIE_DEBUG_VERBOSE("Enter dev_type 0x%x size %d.\n", dev_type, size); - for (i = 0; i < size; i++) { - if (g_fpga_pcie_card_info[i].dev_type == dev_type) { - FPGA_PCIE_DEBUG_VERBOSE("match dev_type 0x%x.\n", dev_type); - return &g_fpga_pcie_card_info[i]; - } - } - - FPGA_PCIE_DEBUG_VERBOSE("dismatch dev_type 0x%x.\n", dev_type); - return NULL; -} - -fpga_pcie_pca9548_cfg_info_t* fpga_pcie_get_pca9548_cfg_info(int bus, int addr) -{ - int dev_type; - fpga_pcie_card_info_t *info; - fpga_pcie_pca9548_cfg_info_t *pca9548_cfg_info; - int i; - int size; - - dev_type = dfd_get_my_card_type(); - if (dev_type < 0) { - FPGA_PCIE_DEBUG_ERROR("drv_get_my_dev_type failed ret %d.\n", dev_type); - return NULL; - } - - info = fpga_pcie_get_card_info(dev_type); - if (info == NULL) { - FPGA_PCIE_DEBUG_ERROR("fpga_pcie_get_card_info dev_type %d failed.\n", dev_type); - return NULL; - } - - size = PCA9548_MAX_CPLD_NUM; - for (i = 0; i < size; i++) { - pca9548_cfg_info = &(info->pca9548_cfg_info[i]); - if ((pca9548_cfg_info->pca9548_bus == bus) && (pca9548_cfg_info->pca9548_addr == addr)) { - FPGA_PCIE_DEBUG_VERBOSE("match dev_type 0x%x bus %d addr 0x%x.\n", dev_type, bus, addr); - return pca9548_cfg_info; - } - } - - FPGA_PCIE_DEBUG_VERBOSE("dismatch dev_type 0x%x bus %d addr 0x%x.\n", dev_type, bus, addr); - return NULL; -} - - -void fpga_do_pca954x_reset_func(int bus, int addr) -{ - fpga_pcie_pca9548_cfg_info_t *cfg_info; - - cfg_info = fpga_pcie_get_pca9548_cfg_info(bus, addr); - if (cfg_info == NULL) { - FPGA_PCIE_DEBUG_VERBOSE("fpga_do_pca954x_reset_func do nothing.\n"); - return; - } - - FPGA_PCIE_DEBUG_VERBOSE("bus %d addr 0x%x, cfg_info.offset:0x%x.\n", bus, addr, cfg_info->cfg_offset); - - fpga_do_pca9548_reset_ctrl(cfg_info->cfg_offset, 0); - mdelay(250); - fpga_do_pca9548_reset_ctrl(cfg_info->cfg_offset, 1); -} - -static void fpga_do_pca954x_reset_func_reg(void) -{ - pca954x_hw_do_reset_func_register(fpga_do_pca954x_reset_func); -} - -#endif - - -static int fpga_i2c_ocore_device_init(struct pci_dev *pdev, const struct pci_device_id *id) -{ - int ret, index; - struct rg_ocores_i2c_platform_data *init_nr_ocores; - - for (index = 0 ; index < ARRAY_SIZE(fpga_pcie_cells_bar0_cfg0); index++) { - init_nr_ocores = fpga_pcie_cells_bar0_cfg0[index].platform_data; - init_nr_ocores->nr = ocore_ctl_startbus + index; - } - FPGA_PCIE_DEBUG_VERBOSE("Enter.\n"); - FPGA_PCIE_DEBUG_VERBOSE("Begin mfd_add_devices.\n"); - ret = mfd_add_devices(&pdev->dev, 0, - fpga_pcie_cells_bar0_cfg0, - ocore_ctl_numbers > ARRAY_SIZE(fpga_pcie_cells_bar0_cfg0) ? ARRAY_SIZE(fpga_pcie_cells_bar0_cfg0) : ocore_ctl_numbers , - &pdev->resource[0], pdev->irq, NULL); - FPGA_PCIE_DEBUG_VERBOSE("End mfd_add_devices ret %d.\n", ret); - if (ret) { - dev_err(&pdev->dev, "mfd_add_devices failed: %d\n", ret); - return -1; - } - - fpga_do_pca954x_reset_func_reg(); - FPGA_PCIE_DEBUG_VERBOSE("Call fpga_do_pca954x_reset_func_reg.\n"); - return 0; -} - -static void fpga_pcie_recover(struct pci_dev *pdev, const struct pci_device_id *id) -{ - struct resource *mem_base; - u32 bar0_val; - int ret; - - mem_base = &pdev->resource[0]; - ret = pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &bar0_val); - if (ret) { - FPGA_PCIE_DEBUG_ERROR("pci_read_config_dword failed ret %d.\n", ret); - return; - } - FPGA_PCIE_DEBUG_VERBOSE("mem_base->start[0x%llx], bar0_val[0x%x], ret %d.\n", - mem_base->start, bar0_val, ret); - - if (bar0_val != mem_base->start) { - ret = pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, mem_base->start); - if (ret) { - FPGA_PCIE_DEBUG_ERROR("pci_write_config_dword mem_base->start[0x%llx], failed ret %d.\n", mem_base->start, ret); - return; - } - FPGA_PCIE_DEBUG_VERBOSE("pci_write_config_dword mem_base->start[0x%llx] success.\n", mem_base->start); - } else { - FPGA_PCIE_DEBUG_VERBOSE("mem_base->start[0x%llx], bar0_val[0x%x], do nothing.\n", - mem_base->start, bar0_val); - } -} - -static int fpga_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id) -{ - int err; - struct rgde_dev *rdev = NULL; - - FPGA_PCIE_DEBUG_VERBOSE("Enter vendor 0x%x, subsystem_vendor 0x%x.\n", pdev->vendor, pdev->subsystem_vendor); - - /* skl : FIX me */ - /* - if ((pdev->vendor != ) || (pdev->subsystem_vendor != )) { - err = -ENODEV; - goto dev_suppport_err:; - }*/ - - - fpga_pcie_recover(pdev, id); - - /* enable device: ask low-level code to enable I/O and memory */ - FPGA_PCIE_DEBUG_VERBOSE("start pci_enable_device!\n"); - err = pci_enable_device(pdev); - if (err) { - FPGA_PCIE_DEBUG_ERROR("pci_enable_device failed: %d\n", err); - goto dev_ebable_err; - } - - FPGA_PCIE_DEBUG_VERBOSE("start pci_set_master!\n"); - pci_set_master(pdev); - - rdev = kzalloc(sizeof(struct rgde_dev), GFP_KERNEL); - if (!rdev) { - err = -ENOMEM; - goto kzalloc_err; - } - - - FPGA_PCIE_DEBUG_VERBOSE("start rgde_setup_bars!\n"); - err = rgde_setup_bars(pdev, &rdev->info); - if (err != 0) { - goto setup_bars_err; - } - - rdev->info.name = "fpga_pcie"; - rdev->info.version = "0.1"; - rdev->info.handler = rgde_irqhandler; - rdev->info.irqcontrol = rgde_irqcontrol; - rdev->info.priv = rdev; - rdev->pdev = pdev; - -#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0) - err = pci_alloc_irq_vectors(pdev,FPGA_MSI_IRQ_BEGIN + 1, ocore_ctl_numbers, PCI_IRQ_MSI); -#else - err = pci_enable_msi_range(pdev, FPGA_MSI_IRQ_BEGIN + 1, ocore_ctl_numbers); -#endif - if (err != ocore_ctl_numbers) { - FPGA_PCIE_DEBUG_ERROR("pci_enable_msi_block err %d FPGA_MSI_IRQ_NUM %d.\n", err, - ocore_ctl_numbers); - goto uio_register_err; - } - - FPGA_PCIE_DEBUG_VERBOSE("before pci_set_drvdata.\n"); - - pci_set_drvdata(pdev, rdev); - FPGA_PCIE_DEBUG_VERBOSE("after pci_set_drvdata.\n"); - enum_time_log("rgde_dev_que_add\n"); - - mdelay(100); - - fpga_reset_ocore_i2c(); - - fpga_i2c_ocore_device_init(pdev, id); - return 0; - -uio_register_err: - /* udev_irq_err: */ -setup_bars_err: - rgde_release_iomem(&rdev->info); - pci_disable_msi(rdev->pdev); - pci_release_regions(pdev); - kfree(rdev); -kzalloc_err: - /* request_region_err: */ - pci_disable_device(pdev); -dev_ebable_err: - /* dev_suppport_err: */ - return err; -} - -static void fpga_pcie_remove(struct pci_dev *pdev) -{ - struct rgde_dev *rdev = pci_get_drvdata(pdev); - - FPGA_PCIE_DEBUG_VERBOSE("fpga_pcie_remove.\n"); -#if 0 - enum_time_log("rgde_dev_que_del\n"); - printk("<0>""uio device %d del.\n", rdev->info.uio_dev->minor); -#endif - rgde_dev_que_del(rdev); - rgde_dev_list_dump(); -#if 0 - uio_unregister_device(&rdev->info); -#endif - mfd_remove_devices(&pdev->dev); - rgde_release_iomem(&rdev->info); - pci_disable_msi(rdev->pdev); - //pci_release_regions(pdev); - pci_disable_device(pdev); - kfree(rdev); -} - -/* static DEFINE_PCI_DEVICE_TABLE(fpga_pci_ids) = { */ - -static const struct pci_device_id fpga_pci_ids[] = { - { PCI_DEVICE(0x10ee, 0x7022)}, - {0} -}; -MODULE_DEVICE_TABLE(pci, fpga_pci_ids); - - -static struct pci_driver fpga_pcie_driver = { - .name = "fpga_pcie", - .id_table = fpga_pci_ids,/* only dynamic id's */ - .probe = fpga_pcie_probe, - .remove = fpga_pcie_remove, -}; - -static int __init fpga_pcie_init(void) -{ - int ret; - - FPGA_PCIE_DEBUG_VERBOSE("fpga_pcie_init enter!\n"); - ret = rgde_intr_mode_config(intr_mode); - if (ret < 0) { - return ret; - } - - INIT_LIST_HEAD(&rgde_dev_que); - - return pci_register_driver(&fpga_pcie_driver); -} - -static void __exit fpga_pcie_exit(void) -{ - FPGA_PCIE_DEBUG_VERBOSE("fpga_pcie_exit enter!\n"); - pci_unregister_driver(&fpga_pcie_driver); -} - -module_init(fpga_pcie_init); -module_exit(fpga_pcie_exit); -module_param(intr_mode, charp, S_IRUGO); -MODULE_PARM_DESC(intr_mode, - "pci_uio interrupt mode (default=msix):\n" - " " INTR_MODE_MSIX_NAME " Use MSIX interrupt\n" - " " INTR_MODE_LEGACY_NAME " Use Legacy interrupt\n" - "\n"); -MODULE_DESCRIPTION("UIO Driver for PCI Devices"); -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("support "); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/fpga_pcie_i2c.h b/platform/broadcom/sonic-platform-modules-ragile/common/modules/fpga_pcie_i2c.h deleted file mode 100755 index 1ea970cc2206..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/common/modules/fpga_pcie_i2c.h +++ /dev/null @@ -1,107 +0,0 @@ -#ifndef _FPGA_PCIE_I2C_H_ -#define _FPGA_PCIE_I2C_H_ - -#ifdef __KERNEL__ -#include -#else -#include -#endif - -#define ENUM_MAX_DEVS (255) - -typedef enum { - CHIP_NONE, - CHIP_PC, -} chiptype_t; - -/* bitmap for ports, 256 ports for now. */ -typedef struct portbitmap_s { - uint8_t bit[32]; -} portbitmap_t; - -typedef struct pc_info_s { - uint8_t ntables; /* number of flow tables */ - uint8_t ncores; /* number of cores */ - uint8_t npipelines; /* number of pipelines */ - uint8_t nports; /* number of ports */ - portbitmap_t pbm_caui; /* bitmap for CAUI ports */ - portbitmap_t pbm_ge; /* bitmap for GE ports */ -} pc_info_t; - -/** - * A structure describing a PCI resource. - */ -struct pci_resource { - uint64_t phys_addr; /**< Physical address, 0 if no resource. */ - uint64_t len; /**< Length of the resource. */ - void *addr; /**< Virtual address, NULL when not mapped. */ -}; - -/** Maximum number of PCI resources. */ -#define PCI_MAX_RESOURCE 6 - -/** Nb. of values in PCI resource format. */ -#define PCI_RESOURCE_FMT_NVAL 3 - -#if 0 -/** IO resource type: memory address space */ -#define IORESOURCE_MEM 0x00000200 -#endif - -typedef struct chipinfo_s { - /* PCI ID */ - uint16_t vendor; - uint16_t dev; - uint8_t rev; - - /* chip properties */ - chiptype_t type; - pc_info_t pc_info; /* if type == CHIP_PC */ -} chipinfo_t; - -typedef struct devinfo_s { - /* static info */ - chipinfo_t chipinfo; - - /* running states */ - uint32_t uiono; /* the "X" in /dev/uioX */ - char *pci_conf_file; /* /sys/devices/ */ - char *dev_file; /* /dev/uioX */ - - struct pci_resource mem_resource[PCI_MAX_RESOURCE]; /**< PCI Memory Resource */ - - uint32_t n_mems; /* no of mem-mapped regions, MUST BE 1 for now */ - uint32_t n_ports;/* no of port-maped regions, MUST BE 0 for now */ -} devinfo_t; - - -#ifdef __KERNEL__ -#include - -struct pci_dev *rgde_to_pci_device(int index); - -int rgde_reg32_read(int minor, uint64_t offset, uint32_t *data); - -int rgde_reg32_write(int minor, uint64_t offset, uint32_t data); - -int pkt_get_mod(int logic_dev, int *mod); - -int pkt_get_port(int logic_dev, int *port); - -/* interrupt mode */ -enum xdk_intr_mode { - XDK_INTR_MODE_NONE = 0, - XDK_INTR_MODE_LEGACY, - XDK_INTR_MODE_MSI, - XDK_INTR_MODE_MSIX -}; - -#define INTR_MODE_NONE_NAME "none" -#define INTR_MODE_LEGACY_NAME "legacy" -#define INTR_MODE_MSI_NAME "msi" -#define INTR_MODE_MSIX_NAME "msix" - -#endif /*__KERNEL__ */ - - -#endif /* _FPGA_PCIE_I2C_H_ */ diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/fpga_reg_defs.h b/platform/broadcom/sonic-platform-modules-ragile/common/modules/fpga_reg_defs.h deleted file mode 100755 index f80c6318564c..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/common/modules/fpga_reg_defs.h +++ /dev/null @@ -1,174 +0,0 @@ -#ifndef _FPGA_REG_DEFS_H_ -#define _FPGA_REG_DEFS_H_ - -/** Define Registers */ -/* Global Registers */ -#define RGDE_REG_GLOBAL_BASE 0x00000000 -#define RGDE_REG_VERSION (RGDE_REG_GLOBAL_BASE + 0x00) -#define RGDE_REG_DATE (RGDE_REG_GLOBAL_BASE + 0x04) -#define RGDE_REG_TEST (RGDE_REG_GLOBAL_BASE + 0x08) -#define RGDE_REG_INT_ENABLE (RGDE_REG_GLOBAL_BASE + 0x10) -#define RGDE_REG_INT_STATUS (RGDE_REG_GLOBAL_BASE + 0x14) - -/* MDIO Registers */ -#define RGDE_REG_MDIO_BASE 0x00000100 -#define RGDE_REG_MDIO_CFG_DT (RGDE_REG_MDIO_BASE + 0x00) -#define RGDE_REG_MDIO_CFG_SPEED (RGDE_REG_MDIO_BASE + 0x04) -#define RGDE_REG_MDIO_CFG_START (RGDE_REG_MDIO_BASE + 0x08) -#define RGDE_REG_MDIO_RDAT (RGDE_REG_MDIO_BASE + 0x10) -#define RGDE_REG_MDIO_STATUS (RGDE_REG_MDIO_BASE + 0x14) - -/* GE0 PORT Registers */ -#define RGDE_REG_GE0_PORT_BASE 0x00001000 -#define RGDE_REG_GE0_PORT_CTL (RGDE_REG_GE0_PORT_BASE + 0x00) -#define RGDE_REG_GE0_PORT_STA (RGDE_REG_GE0_PORT_BASE + 0x04) -#define RGDE_REG_GE0_PORT_MTU (RGDE_REG_GE0_PORT_BASE + 0x08) -#define RGDE_REG_GE0_PORT_RXPKTS (RGDE_REG_GE0_PORT_BASE + 0x10) -#define RGDE_REG_GE0_PORT_RXBYTE (RGDE_REG_GE0_PORT_BASE + 0x18) -#define RGDE_REG_GE0_PORT_RXERR (RGDE_REG_GE0_PORT_BASE + 0x20) -#define RGDE_REG_GE0_PORT_RXDROP (RGDE_REG_GE0_PORT_BASE + 0x28) -#define RGDE_REG_GE0_PORT_RXMULTI (RGDE_REG_GE0_PORT_BASE + 0x30) -#define RGDE_REG_GE0_PORT_RXBRO (RGDE_REG_GE0_PORT_BASE + 0x38) -#define RGDE_REG_GE0_PORT_TXPKTS (RGDE_REG_GE0_PORT_BASE + 0x40) -#define RGDE_REG_GE0_PORT_TXBYTE (RGDE_REG_GE0_PORT_BASE + 0x48) -#define RGDE_REG_GE0_PORT_TXERR (RGDE_REG_GE0_PORT_BASE + 0x50) -#define RGDE_REG_GE0_PORT_TXDROP (RGDE_REG_GE0_PORT_BASE + 0x58) -#define RGDE_REG_GE0_PORT_TXMULT (RGDE_REG_GE0_PORT_BASE + 0x60) -#define RGDE_REG_GE0_PORT_TXBRO (RGDE_REG_GE0_PORT_BASE + 0x68) - -/* GE1 PORT Registers */ -#define RGDE_REG_GE1_PORT_BASE 0x00001100 -#define RGDE_REG_GE1_PORT_CTL (RGDE_REG_GE1_PORT_BASE + 0x00) -#define RGDE_REG_GE1_PORT_STA (RGDE_REG_GE1_PORT_BASE + 0x04) -#define RGDE_REG_GE1_PORT_MTU (RGDE_REG_GE1_PORT_BASE + 0x08) -#define RGDE_REG_GE1_PORT_RXPKTS (RGDE_REG_GE1_PORT_BASE + 0x10) -#define RGDE_REG_GE1_PORT_RXBYTE (RGDE_REG_GE1_PORT_BASE + 0x18) -#define RGDE_REG_GE1_PORT_RXERR (RGDE_REG_GE1_PORT_BASE + 0x20) -#define RGDE_REG_GE1_PORT_RXDROP (RGDE_REG_GE1_PORT_BASE + 0x28) -#define RGDE_REG_GE1_PORT_RXMULTI (RGDE_REG_GE1_PORT_BASE + 0x30) -#define RGDE_REG_GE1_PORT_RXBRO (RGDE_REG_GE1_PORT_BASE + 0x38) -#define RGDE_REG_GE1_PORT_TXPKTS (RGDE_REG_GE1_PORT_BASE + 0x40) -#define RGDE_REG_GE1_PORT_TXBYTE (RGDE_REG_GE1_PORT_BASE + 0x48) -#define RGDE_REG_GE1_PORT_TXERR (RGDE_REG_GE1_PORT_BASE + 0x50) -#define RGDE_REG_GE1_PORT_TXDROP (RGDE_REG_GE1_PORT_BASE + 0x58) -#define RGDE_REG_GE1_PORT_TXMULT (RGDE_REG_GE1_PORT_BASE + 0x60) -#define RGDE_REG_GE1_PORT_TXBRO (RGDE_REG_GE1_PORT_BASE + 0x68) - -/* GE2 PORT Registers */ -#define RGDE_REG_GE2_PORT_BASE 0x00001200 -#define RGDE_REG_GE2_PORT_CTL (RGDE_REG_GE2_PORT_BASE + 0x00) -#define RGDE_REG_GE2_PORT_STA (RGDE_REG_GE2_PORT_BASE + 0x04) -#define RGDE_REG_GE2_PORT_MTU (RGDE_REG_GE2_PORT_BASE + 0x08) -#define RGDE_REG_GE2_PORT_RXPKTS (RGDE_REG_GE2_PORT_BASE + 0x10) -#define RGDE_REG_GE2_PORT_RXBYTE (RGDE_REG_GE2_PORT_BASE + 0x18) -#define RGDE_REG_GE2_PORT_RXERR (RGDE_REG_GE2_PORT_BASE + 0x20) -#define RGDE_REG_GE2_PORT_RXDROP (RGDE_REG_GE2_PORT_BASE + 0x28) -#define RGDE_REG_GE2_PORT_RXMULTI (RGDE_REG_GE2_PORT_BASE + 0x30) -#define RGDE_REG_GE2_PORT_RXBRO (RGDE_REG_GE2_PORT_BASE + 0x38) -#define RGDE_REG_GE2_PORT_TXPKTS (RGDE_REG_GE2_PORT_BASE + 0x40) -#define RGDE_REG_GE2_PORT_TXBYTE (RGDE_REG_GE2_PORT_BASE + 0x48) -#define RGDE_REG_GE2_PORT_TXERR (RGDE_REG_GE2_PORT_BASE + 0x50) -#define RGDE_REG_GE2_PORT_TXDROP (RGDE_REG_GE2_PORT_BASE + 0x58) -#define RGDE_REG_GE2_PORT_TXMULT (RGDE_REG_GE2_PORT_BASE + 0x60) -#define RGDE_REG_GE2_PORT_TXBRO (RGDE_REG_GE2_PORT_BASE + 0x68) - -/* GE3 PORT Registers */ -#define RGDE_REG_GE3_PORT_BASE 0x00001300 -#define RGDE_REG_GE3_PORT_CTL (RGDE_REG_GE3_PORT_BASE + 0x00) -#define RGDE_REG_GE3_PORT_STA (RGDE_REG_GE3_PORT_BASE + 0x04) -#define RGDE_REG_GE3_PORT_MTU (RGDE_REG_GE3_PORT_BASE + 0x08) -#define RGDE_REG_GE3_PORT_RXPKTS (RGDE_REG_GE3_PORT_BASE + 0x10) -#define RGDE_REG_GE3_PORT_RXBYTE (RGDE_REG_GE3_PORT_BASE + 0x18) -#define RGDE_REG_GE3_PORT_RXERR (RGDE_REG_GE3_PORT_BASE + 0x20) -#define RGDE_REG_GE3_PORT_RXDROP (RGDE_REG_GE3_PORT_BASE + 0x28) -#define RGDE_REG_GE3_PORT_RXMULTI (RGDE_REG_GE3_PORT_BASE + 0x30) -#define RGDE_REG_GE3_PORT_RXBRO (RGDE_REG_GE3_PORT_BASE + 0x38) -#define RGDE_REG_GE3_PORT_TXPKTS (RGDE_REG_GE3_PORT_BASE + 0x40) -#define RGDE_REG_GE3_PORT_TXBYTE (RGDE_REG_GE3_PORT_BASE + 0x48) -#define RGDE_REG_GE3_PORT_TXERR (RGDE_REG_GE3_PORT_BASE + 0x50) -#define RGDE_REG_GE3_PORT_TXDROP (RGDE_REG_GE3_PORT_BASE + 0x58) -#define RGDE_REG_GE3_PORT_TXMULT (RGDE_REG_GE3_PORT_BASE + 0x60) -#define RGDE_REG_GE3_PORT_TXBRO (RGDE_REG_GE3_PORT_BASE + 0x68) - -/* GE4 PORT Registers */ -#define RGDE_REG_XGE0_PORT_BASE 0x00001400 -#define RGDE_REG_XGE0_PORT_CTL (RGDE_REG_XGE0_PORT_BASE + 0x00) -#define RGDE_REG_XGE0_PORT_STA (RGDE_REG_XGE0_PORT_BASE + 0x04) -#define RGDE_REG_XGE0_PORT_MTU (RGDE_REG_XGE0_PORT_BASE + 0x08) -#define RGDE_REG_XGE0_PORT_RXPKTS (RGDE_REG_XGE0_PORT_BASE + 0x10) -#define RGDE_REG_XGE0_PORT_RXBYTE (RGDE_REG_XGE0_PORT_BASE + 0x18) -#define RGDE_REG_XGE0_PORT_RXERR (RGDE_REG_XGE0_PORT_BASE + 0x20) -#define RGDE_REG_XGE0_PORT_RXDROP (RGDE_REG_XGE0_PORT_BASE + 0x28) -#define RGDE_REG_XGE0_PORT_RXMULTI (RGDE_REG_XGE0_PORT_BASE + 0x30) -#define RGDE_REG_XGE0_PORT_RXBRO (RGDE_REG_XGE0_PORT_BASE + 0x38) -#define RGDE_REG_XGE0_PORT_TXPKTS (RGDE_REG_XGE0_PORT_BASE + 0x40) -#define RGDE_REG_XGE0_PORT_TXBYTE (RGDE_REG_XGE0_PORT_BASE + 0x48) -#define RGDE_REG_XGE0_PORT_TXERR (RGDE_REG_XGE0_PORT_BASE + 0x50) -#define RGDE_REG_XGE0_PORT_TXDROP (RGDE_REG_XGE0_PORT_BASE + 0x58) -#define RGDE_REG_XGE0_PORT_TXMULT (RGDE_REG_XGE0_PORT_BASE + 0x60) -#define RGDE_REG_XGE0_PORT_TXBRO (RGDE_REG_XGE0_PORT_BASE + 0x68) - -/* GE5 PORT Registers */ -#define RGDE_REG_XGE1_PORT_BASE 0x00001500 -#define RGDE_REG_XGE1_PORT_CTL (RGDE_REG_XGE1_PORT_BASE + 0x00) -#define RGDE_REG_XGE1_PORT_STA (RGDE_REG_XGE1_PORT_BASE + 0x04) -#define RGDE_REG_XGE1_PORT_MTU (RGDE_REG_XGE1_PORT_BASE + 0x08) -#define RGDE_REG_XGE1_PORT_RXPKTS (RGDE_REG_XGE1_PORT_BASE + 0x10) -#define RGDE_REG_XGE1_PORT_RXBYTE (RGDE_REG_XGE1_PORT_BASE + 0x18) -#define RGDE_REG_XGE1_PORT_RXERR (RGDE_REG_XGE1_PORT_BASE + 0x20) -#define RGDE_REG_XGE1_PORT_RXDROP (RGDE_REG_XGE1_PORT_BASE + 0x28) -#define RGDE_REG_XGE1_PORT_RXMULTI (RGDE_REG_XGE1_PORT_BASE + 0x30) -#define RGDE_REG_XGE1_PORT_RXBRO (RGDE_REG_XGE1_PORT_BASE + 0x38) -#define RGDE_REG_XGE1_PORT_TXPKTS (RGDE_REG_XGE1_PORT_BASE + 0x40) -#define RGDE_REG_XGE1_PORT_TXBYTE (RGDE_REG_XGE1_PORT_BASE + 0x48) -#define RGDE_REG_XGE1_PORT_TXERR (RGDE_REG_XGE1_PORT_BASE + 0x50) -#define RGDE_REG_XGE1_PORT_TXDROP (RGDE_REG_XGE1_PORT_BASE + 0x58) -#define RGDE_REG_XGE1_PORT_TXMULT (RGDE_REG_XGE1_PORT_BASE + 0x60) -#define RGDE_REG_XGE1_PORT_TXBRO (RGDE_REG_XGE1_PORT_BASE + 0x68) - -#define RGDE_REG_CPU_BASE 0x00002100 -#define RGDE_REG_PCIE_ENDIAN_CNTR (RGDE_REG_CPU_BASE + 0x08) - -/* DMA Registers */ -#define RGDE_REG_DMA_BASE 0x00004000 -#define RGDE_REG_BD_WR_OVERTIME (RGDE_REG_DMA_BASE + 0x00) -#define RGDE_REG_BD_DEEP (RGDE_REG_DMA_BASE + 0x04) - -/* TX0 Registers */ -#define RGDE_REG_TX0_BASE 0x00005000 -#define RGDE_REG_TX0_CHN_EN (RGDE_REG_TX0_BASE + 0x00) -#define RGDE_REG_TX0_BD_BASE (RGDE_REG_TX0_BASE + 0x04) -#define RGDE_REG_TX0_BD_TAIL (RGDE_REG_TX0_BASE + 0x08) -#define RGDE_REG_TX0_BD_READY_NUM (RGDE_REG_TX0_BASE + 0x0c) -#define RGDE_REG_TX0_CPU2FPGA_BD_NUM (RGDE_REG_TX0_BASE + 0x30) -#define RGDE_REG_TX0_FPGA2CPU_BD_NUM (RGDE_REG_TX0_BASE + 0x34) - -/* TX1 Registers */ -#define RGDE_REG_TX1_BASE 0x00005100 -#define RGDE_REG_TX1_CHN_EN (RGDE_REG_TX1_BASE + 0x00) -#define RGDE_REG_TX1_BD_BASE (RGDE_REG_TX1_BASE + 0x04) -#define RGDE_REG_TX1_BD_TAIL (RGDE_REG_TX1_BASE + 0x08) -#define RGDE_REG_TX1_BD_READY_NUM (RGDE_REG_TX1_BASE + 0x0c) -#define RGDE_REG_TX1_CPU2FPGA_BD_NUM (RGDE_REG_TX1_BASE + 0x30) -#define RGDE_REG_TX1_FPGA2CPU_BD_NUM (RGDE_REG_TX1_BASE + 0x34) - -/* RX0 Registers */ -#define RGDE_REG_RX0_BASE 0x00006400 -#define RGDE_REG_RX0_CHN_EN (RGDE_REG_RX0_BASE + 0x00) -#define RGDE_REG_RX0_BD_BASE (RGDE_REG_RX0_BASE + 0x04) -#define RGDE_REG_RX0_BD_TAIL (RGDE_REG_RX0_BASE + 0x08) -#define RGDE_REG_RX0_BD_READY_NUM (RGDE_REG_RX0_BASE + 0x0c) -#define RGDE_REG_RX0_CPU2FPGA_BD_NUM (RGDE_REG_RX0_BASE + 0x30) -#define RGDE_REG_RX0_FPGA2CPU_BD_NUM (RGDE_REG_RX0_BASE + 0x34) - -/* RX1 Registers */ -#define RGDE_REG_RX1_BASE 0x00006500 -#define RGDE_REG_RX1_CHN_EN (RGDE_REG_RX1_BASE + 0x00) -#define RGDE_REG_RX1_BD_BASE (RGDE_REG_RX1_BASE + 0x04) -#define RGDE_REG_RX1_BD_TAIL (RGDE_REG_RX1_BASE + 0x08) -#define RGDE_REG_RX1_BD_READY_NUM (RGDE_REG_RX1_BASE + 0x0c) -#define RGDE_REG_RX1_CPU2FPGA_BD_NUM (RGDE_REG_RX1_BASE + 0x30) -#define RGDE_REG_RX1_FPGA2CPU_BD_NUM (RGDE_REG_RX1_BASE + 0x34) - - -#endif /* _FPGA_REG_DEFS_H_ */ diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/i2c-mux-pca954x.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/i2c-mux-pca954x.c deleted file mode 100755 index 76270a94ec8b..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/common/modules/i2c-mux-pca954x.c +++ /dev/null @@ -1,1676 +0,0 @@ -/* - * Copyright (c) 2008-2009 Rodolfo Giometti - * Copyright (c) 2008-2009 Eurotech S.p.A. - * Copyright (c) 2019 - * - * I2C multiplexer - * - * This module supports the PCA954x series of I2C multiplexer/switch chips - * made by Philips Semiconductors. - * This includes the: - * PCA9540, PCA9542, PCA9543, PCA9544, PCA9545, PCA9546, PCA9547 - * and PCA9548. - * - * These chips are all controlled via the I2C bus itself, and all have a - * single 8-bit register. The upstream "parent" bus fans out to two, - * four, or eight downstream busses or channels; which of these - * are selected is determined by the chip type and register contents. A - * mux can select only one sub-bus at a time; a switch can select any - * combination simultaneously. - * - * Based on: - * pca954x.c from Kumar Gala - * Copyright (C) 2006 - * - * Based on: - * pca954x.c from Ken Harrenstien - * Copyright (C) 2004 Google, Inc. (Ken Harrenstien) - * - * Based on: - * i2c-virtual_cb.c from Brian Kuschak - * and - * pca9540.c from Jean Delvare . - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0) -#include -#include -#else -#include -#endif -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - - -#define PCA954X_MAX_NCHANS 8 - -#define PCA954X_IRQ_OFFSET 4 - -extern int pca9641_setmuxflag(int nr, int flag); - -int force_create_bus = 0; -static int close_chan_force_reset = 0; -static int select_chan_check = 0; - -module_param(force_create_bus, int, S_IRUGO | S_IWUSR); -module_param(close_chan_force_reset, int, S_IRUGO | S_IWUSR); -module_param(select_chan_check, int, S_IRUGO | S_IWUSR); - -enum pca_type { - pca_9540, - pca_9542, - pca_9543, - pca_9544, - pca_9545, - pca_9546, - pca_9547, - pca_9548, -}; - -struct chip_desc { - u8 nchans; - u8 enable; /* used for muxes only */ - u8 has_irq; - enum muxtype { - pca954x_ismux = 0, - pca954x_isswi - } muxtype; -}; - -struct pca954x { - const struct chip_desc *chip; - - u8 last_chan; /* last register value */ -#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0) - s32 idle_state; -#else - u8 deselect; -#endif - struct i2c_client *client; - - struct irq_domain *irq; - unsigned int irq_mask; - raw_spinlock_t lock; -}; - -/* Provide specs for the PCA954x types we know about */ -static const struct chip_desc chips[] = { - [pca_9540] = { - .nchans = 2, - .enable = 0x4, - .muxtype = pca954x_ismux, - }, - [pca_9542] = { - .nchans = 2, - .enable = 0x4, - .has_irq = 1, - .muxtype = pca954x_ismux, - }, - [pca_9543] = { - .nchans = 2, - .has_irq = 1, - .muxtype = pca954x_isswi, - }, - [pca_9544] = { - .nchans = 4, - .enable = 0x4, - .has_irq = 1, - .muxtype = pca954x_ismux, - }, - [pca_9545] = { - .nchans = 4, - .has_irq = 1, - .muxtype = pca954x_isswi, - }, - [pca_9546] = { - .nchans = 4, - .muxtype = pca954x_isswi, - }, - [pca_9547] = { - .nchans = 8, - .enable = 0x8, - .muxtype = pca954x_ismux, - }, - [pca_9548] = { - .nchans = 8, - .muxtype = pca954x_isswi, - }, -}; - -static const struct i2c_device_id pca954x_id[] = { - { "pca9540", pca_9540 }, - { "pca9542", pca_9542 }, - { "pca9543", pca_9543 }, - { "pca9544", pca_9544 }, - { "pca9545", pca_9545 }, - { "pca9546", pca_9546 }, - { "pca9547", pca_9547 }, - { "pca9548", pca_9548 }, - { } -}; -MODULE_DEVICE_TABLE(i2c, pca954x_id); -#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0) -static const struct of_device_id pca954x_of_match[] = { - { .compatible = "nxp,pca9540", .data = &chips[pca_9540] }, - { .compatible = "nxp,pca9542", .data = &chips[pca_9542] }, - { .compatible = "nxp,pca9543", .data = &chips[pca_9543] }, - { .compatible = "nxp,pca9544", .data = &chips[pca_9544] }, - { .compatible = "nxp,pca9545", .data = &chips[pca_9545] }, - { .compatible = "nxp,pca9546", .data = &chips[pca_9546] }, - { .compatible = "nxp,pca9547", .data = &chips[pca_9547] }, - { .compatible = "nxp,pca9548", .data = &chips[pca_9548] }, - {} -}; -MODULE_DEVICE_TABLE(of, pca954x_of_match); -#else -#ifdef CONFIG_OF -static const struct of_device_id pca954x_of_match[] = { - { .compatible = "nxp,pca9540", .data = &chips[pca_9540] }, - { .compatible = "nxp,pca9542", .data = &chips[pca_9542] }, - { .compatible = "nxp,pca9543", .data = &chips[pca_9543] }, - { .compatible = "nxp,pca9544", .data = &chips[pca_9544] }, - { .compatible = "nxp,pca9545", .data = &chips[pca_9545] }, - { .compatible = "nxp,pca9546", .data = &chips[pca_9546] }, - { .compatible = "nxp,pca9547", .data = &chips[pca_9547] }, - { .compatible = "nxp,pca9548", .data = &chips[pca_9548] }, - {} -}; -MODULE_DEVICE_TABLE(of, pca954x_of_match); -#endif -#endif - -/* Write to mux register. Don't use i2c_transfer()/i2c_smbus_xfer() - for this as they will try to lock adapter a second time */ -static int pca954x_reg_write(struct i2c_adapter *adap, - struct i2c_client *client, u8 val) -{ - int ret = -ENODEV; - - if (adap->algo->master_xfer) { - struct i2c_msg msg; - char buf[1]; - - msg.addr = client->addr; - msg.flags = 0; - msg.len = 1; - buf[0] = val; - msg.buf = buf; - ret = __i2c_transfer(adap, &msg, 1); - - if (ret >= 0 && ret != 1) - ret = -EREMOTEIO; - } else { - union i2c_smbus_data data; - ret = adap->algo->smbus_xfer(adap, client->addr, - client->flags, - I2C_SMBUS_WRITE, - val, I2C_SMBUS_BYTE, &data); - } - - return ret; -} - -static int pca954x_reg_read(struct i2c_adapter *adap, - struct i2c_client *client, u8 *val) -{ - int ret = -ENODEV; - u8 tmp_val; - - if (adap->algo->master_xfer) { - struct i2c_msg msg; - - msg.addr = client->addr; - msg.flags = I2C_M_RD; - msg.len = 1; - msg.buf = &tmp_val; - ret = __i2c_transfer(adap, &msg, 1); - - if (ret >= 0 && ret != 1) { - ret = -EREMOTEIO; - } else { - *val = tmp_val; - } - } else { - union i2c_smbus_data data; - ret = adap->algo->smbus_xfer(adap, client->addr, - client->flags, - I2C_SMBUS_READ, - 0, I2C_SMBUS_BYTE, &data); - - if (!ret) { - tmp_val = data.byte; - *val = tmp_val; - } - } - - return ret; -} - -#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0) -static u8 pca954x_regval(struct pca954x *data, u8 chan) -{ - /* We make switches look like muxes, not sure how to be smarter. */ - if (data->chip->muxtype == pca954x_ismux) - return chan | data->chip->enable; - else - return 1 << chan; -} -#endif - -static int pca954x_setmuxflag(struct i2c_client *client, int flag) -{ - struct i2c_adapter *adap = to_i2c_adapter(client->dev.parent); - pca9641_setmuxflag(adap->nr, flag); - return 0; -} - -typedef void (*pca954x_hw_do_reset_func_t)(int busid, int addr); -pca954x_hw_do_reset_func_t g_notify_to_do_reset = NULL; - -void pca954x_hw_do_reset_func_register(void* func) -{ - if (func == NULL) { - return ; - } - g_notify_to_do_reset = func; - return; -} -EXPORT_SYMBOL(pca954x_hw_do_reset_func_register); - -static int pca954x_hw_do_reset(int busid, int addr) -{ - if (g_notify_to_do_reset != NULL) { - (*g_notify_to_do_reset)(busid, addr); - return 0; - } - - return 0; -} -/***************************************9548 reset*****************************************/ -#define DEV_TYPE 0x404a -#define PCA9548_MAX_CPLD_NUM (32) /* PCA9548 max number */ -#define PCA9548_MAX_CPLD_LAYER (8) /* PCA9548 max layer */ -#define DFD_PID_BUF_LEN (32) -#define DFD_PRODUCT_ID_LENGTH (8) -#define CPLD_PCA9548_RESET 0x023500b0 /* bus:2, addr:0x35, offset:0xb0 */ -#define B6510_32CQ_CPLD_PCA9548_RESET 0x060d0060 /* bus:6, addr:0x0d, offset:0x60 */ - -#define DFD_PUB_CARDTYPE_FILE "/sys/module/ragile_common/parameters/dfd_my_type" -#define DFD_MAX_PRODUCT_NUM (32) - - -#define I2C_RETRY_TIMES 5 -#define I2C_RETRY_WAIT_TIMES 10 /*delay 10ms*/ - -#define PCA9548_I2C_GET_BUS(addr) (((addr) >> 24) & 0x00ff) -#define PCA9548_I2C_GET_CLIENT(addr) (((addr) >> 16) & 0x00ff) -#define PCA9548_I2C_GET_OFFSET(addr) (addr & 0xffff) - -typedef enum pca9548_reset_type { - PCA9548_RESET_FUNC = 0, - PCA9548_RESET_GPIO = 1, -} pca9548_reset_type_t; - -typedef void (*pca954x_hw_do_reset_func_t_new)(int io_port, u8 value); -typedef u8 (*pca954x_get_umask_func_t)(int io_port); - -void pca954x_hw_do_reset_by_i2c(int addr, u8 value); -u8 pca954x_get_umask_by_i2c(int addr); -void pca954x_hw_do_reset_by_lpc(int io_port, u8 value); -u8 pca954x_get_umask_by_lpc(int io_port); - - -typedef struct func_attr_s { - int cfg_offset[PCA9548_MAX_CPLD_LAYER]; - int umask[PCA9548_MAX_CPLD_LAYER]; - pca954x_hw_do_reset_func_t_new reset_func; /* 9548 reset function */ - pca954x_get_umask_func_t get_umask_func; /* get reset mask */ -} func_attr_t; - -typedef struct gpio_attr_s { - int gpio; - int gpio_init; - u8 reset_on; - u8 reset_off; -} gpio_attr_t; - -typedef struct pca9548_cfg_info_s { - int pca9548_reset_type; - int pca9548_bus; - int pca9548_addr; - int rst_delay_b; /* delay time before reset(us) */ - int rst_delay; /* reset time(us) */ - int rst_delay_a; /* delay time after reset(us) */ - union { - func_attr_t func_attr; - gpio_attr_t gpio_attr; - } attr; -} pca9548_cfg_info_t; - -typedef struct fpga_pcie_card_info_s { - int dev_type[DFD_MAX_PRODUCT_NUM]; /* dev type */ - pca9548_cfg_info_t pca9548_cfg_info[PCA9548_MAX_CPLD_NUM]; -} pca9548_card_info_t; - -static pca9548_card_info_t g_pca9548_card_info[] = { - { - .dev_type = {0x404a}, /* RA-B6510-48V8C */ - .pca9548_cfg_info = { - /* psu fan */ - { - .pca9548_reset_type = PCA9548_RESET_GPIO, - .pca9548_bus = 2, - .pca9548_addr = 0x70, - .rst_delay_b = 0, - .rst_delay = 1000, - .rst_delay_a = 1000, - .attr = { - .gpio_attr.gpio = 7, - .gpio_attr.gpio_init = 0, - .gpio_attr.reset_on = 1, - .gpio_attr.reset_off = 0, - }, - }, - /* sff1 */ - { - .pca9548_reset_type = PCA9548_RESET_FUNC, - .pca9548_bus = 1, - .pca9548_addr = 0x70, - .rst_delay_b = 0, - .rst_delay = 1000, - .rst_delay_a = 1000, - .attr = { - .func_attr.reset_func = pca954x_hw_do_reset_by_i2c, - .func_attr.get_umask_func = pca954x_get_umask_by_i2c, - .func_attr.cfg_offset = {CPLD_PCA9548_RESET, -1}, - .func_attr.umask = {BIT(0), -1}, - }, - }, - /* sff2 */ - { - .pca9548_reset_type = PCA9548_RESET_FUNC, - .pca9548_bus = 1, - .pca9548_addr = 0x71, - .rst_delay_b = 0, - .rst_delay = 1000, - .rst_delay_a = 1000, - .attr = { - .func_attr.reset_func = pca954x_hw_do_reset_by_i2c, - .func_attr.get_umask_func = pca954x_get_umask_by_i2c, - .func_attr.cfg_offset = {CPLD_PCA9548_RESET, -1}, - .func_attr.umask = {BIT(1), -1}, - }, - }, - /* sff3 */ - { - .pca9548_reset_type = PCA9548_RESET_FUNC, - .pca9548_bus = 1, - .pca9548_addr = 0x72, - .rst_delay_b = 0, - .rst_delay = 1000, - .rst_delay_a = 1000, - .attr = { - .func_attr.reset_func = pca954x_hw_do_reset_by_i2c, - .func_attr.get_umask_func = pca954x_get_umask_by_i2c, - .func_attr.cfg_offset = {CPLD_PCA9548_RESET, -1}, - .func_attr.umask = {BIT(2), -1}, - }, - }, - /* sff4 */ - { - .pca9548_reset_type = PCA9548_RESET_FUNC, - .pca9548_bus = 1, - .pca9548_addr = 0x73, - .rst_delay_b = 0, - .rst_delay = 1000, - .rst_delay_a = 1000, - .attr = { - .func_attr.reset_func = pca954x_hw_do_reset_by_i2c, - .func_attr.get_umask_func = pca954x_get_umask_by_i2c, - .func_attr.cfg_offset = {CPLD_PCA9548_RESET, -1}, - .func_attr.umask = {BIT(3), -1}, - }, - }, - /* sff5 */ - { - .pca9548_reset_type = PCA9548_RESET_FUNC, - .pca9548_bus = 1, - .pca9548_addr = 0x74, - .rst_delay_b = 0, - .rst_delay = 1000, - .rst_delay_a = 1000, - .attr = { - .func_attr.reset_func = pca954x_hw_do_reset_by_i2c, - .func_attr.get_umask_func = pca954x_get_umask_by_i2c, - .func_attr.cfg_offset = {CPLD_PCA9548_RESET, -1}, - .func_attr.umask = {BIT(4), -1}, - }, - }, - /* sff6 */ - { - .pca9548_reset_type = PCA9548_RESET_FUNC, - .pca9548_bus = 1, - .pca9548_addr = 0x75, - .rst_delay_b = 0, - .rst_delay = 1000, - .rst_delay_a = 1000, - .attr = { - .func_attr.reset_func = pca954x_hw_do_reset_by_i2c, - .func_attr.get_umask_func = pca954x_get_umask_by_i2c, - .func_attr.cfg_offset = {CPLD_PCA9548_RESET, -1}, - .func_attr.umask = {BIT(5), -1}, - }, - }, - /* sff7 */ - { - .pca9548_reset_type = PCA9548_RESET_FUNC, - .pca9548_bus = 1, - .pca9548_addr = 0x76, - .rst_delay_b = 0, - .rst_delay = 1000, - .rst_delay_a = 1000, - .attr = { - .func_attr.reset_func = pca954x_hw_do_reset_by_i2c, - .func_attr.get_umask_func = pca954x_get_umask_by_i2c, - .func_attr.cfg_offset = {CPLD_PCA9548_RESET, -1}, - .func_attr.umask = {BIT(6), -1}, - }, - }, - }, - }, - { - /*RA-B6910-64C*/ - .dev_type = {0x404c}, - .pca9548_cfg_info = { - /* psu fan */ - { - .pca9548_reset_type = PCA9548_RESET_GPIO, - .pca9548_bus = 2, - .pca9548_addr = 0x70, - .rst_delay_b = 0, - .rst_delay = 1000, - .rst_delay_a = 1000, - .attr = { - .gpio_attr.gpio = 7, - .gpio_attr.gpio_init = 0, - .gpio_attr.reset_on = 1, - .gpio_attr.reset_off = 0, - }, - }, - /* sff1 */ - { - .pca9548_reset_type = PCA9548_RESET_FUNC, - .pca9548_bus = 1, - .pca9548_addr = 0x70, - .rst_delay_b = 0, - .rst_delay = 1000, - .rst_delay_a = 1000, - .attr = { - .func_attr.reset_func = pca954x_hw_do_reset_by_i2c, - .func_attr.get_umask_func = pca954x_get_umask_by_i2c, - .func_attr.cfg_offset = {CPLD_PCA9548_RESET, -1}, - .func_attr.umask = {BIT(0), -1}, - }, - }, - /* sff2 */ - { - .pca9548_reset_type = PCA9548_RESET_FUNC, - .pca9548_bus = 1, - .pca9548_addr = 0x71, - .rst_delay_b = 0, - .rst_delay = 1000, - .rst_delay_a = 1000, - .attr = { - .func_attr.reset_func = pca954x_hw_do_reset_by_i2c, - .func_attr.get_umask_func = pca954x_get_umask_by_i2c, - .func_attr.cfg_offset = {CPLD_PCA9548_RESET, -1}, - .func_attr.umask = {BIT(1), -1}, - }, - }, - /* sff3 */ - { - .pca9548_reset_type = PCA9548_RESET_FUNC, - .pca9548_bus = 1, - .pca9548_addr = 0x72, - .rst_delay_b = 0, - .rst_delay = 1000, - .rst_delay_a = 1000, - .attr = { - .func_attr.reset_func = pca954x_hw_do_reset_by_i2c, - .func_attr.get_umask_func = pca954x_get_umask_by_i2c, - .func_attr.cfg_offset = {CPLD_PCA9548_RESET, -1}, - .func_attr.umask = {BIT(2), -1}, - }, - }, - /* sff4 */ - { - .pca9548_reset_type = PCA9548_RESET_FUNC, - .pca9548_bus = 1, - .pca9548_addr = 0x73, - .rst_delay_b = 0, - .rst_delay = 1000, - .rst_delay_a = 1000, - .attr = { - .func_attr.reset_func = pca954x_hw_do_reset_by_i2c, - .func_attr.get_umask_func = pca954x_get_umask_by_i2c, - .func_attr.cfg_offset = {CPLD_PCA9548_RESET, -1}, - .func_attr.umask = {BIT(3), -1}, - }, - }, - /* sff5 */ - { - .pca9548_reset_type = PCA9548_RESET_FUNC, - .pca9548_bus = 1, - .pca9548_addr = 0x74, - .rst_delay_b = 0, - .rst_delay = 1000, - .rst_delay_a = 1000, - .attr = { - .func_attr.reset_func = pca954x_hw_do_reset_by_i2c, - .func_attr.get_umask_func = pca954x_get_umask_by_i2c, - .func_attr.cfg_offset = {CPLD_PCA9548_RESET, -1}, - .func_attr.umask = {BIT(4), -1}, - }, - }, - /* sff6 */ - { - .pca9548_reset_type = PCA9548_RESET_FUNC, - .pca9548_bus = 1, - .pca9548_addr = 0x75, - .rst_delay_b = 0, - .rst_delay = 1000, - .rst_delay_a = 1000, - .attr = { - .func_attr.reset_func = pca954x_hw_do_reset_by_i2c, - .func_attr.get_umask_func = pca954x_get_umask_by_i2c, - .func_attr.cfg_offset = {CPLD_PCA9548_RESET, -1}, - .func_attr.umask = {BIT(5), -1}, - }, - }, - /* sff7 */ - { - .pca9548_reset_type = PCA9548_RESET_FUNC, - .pca9548_bus = 1, - .pca9548_addr = 0x76, - .rst_delay_b = 0, - .rst_delay = 1000, - .rst_delay_a = 1000, - .attr = { - .func_attr.reset_func = pca954x_hw_do_reset_by_i2c, - .func_attr.get_umask_func = pca954x_get_umask_by_i2c, - .func_attr.cfg_offset = {CPLD_PCA9548_RESET, -1}, - .func_attr.umask = {BIT(6), -1}, - }, - }, - /* sff8 */ - { - .pca9548_reset_type = PCA9548_RESET_FUNC, - .pca9548_bus = 1, - .pca9548_addr = 0x77, - .rst_delay_b = 0, - .rst_delay = 1000, - .rst_delay_a = 1000, - .attr = { - .func_attr.reset_func = pca954x_hw_do_reset_by_i2c, - .func_attr.get_umask_func = pca954x_get_umask_by_i2c, - .func_attr.cfg_offset = {CPLD_PCA9548_RESET, -1}, - .func_attr.umask = {BIT(7), -1}, - }, - }, - }, - }, - { - /* RA-B6510-32C */ - .dev_type = {0x404b}, - .pca9548_cfg_info = { - /* psu */ - { - .pca9548_reset_type = PCA9548_RESET_FUNC, - .pca9548_bus = 4, - .pca9548_addr = 0x77, - .rst_delay_b = 0, - .rst_delay = 1000, - .rst_delay_a = 1000, - .attr = { - .func_attr.reset_func = pca954x_hw_do_reset_by_lpc, - .func_attr.get_umask_func = pca954x_get_umask_by_lpc, - .func_attr.cfg_offset = {0x960, -1}, - .func_attr.umask = {BIT(0), -1}, - }, - }, - /* fan */ - { - .pca9548_reset_type = PCA9548_RESET_FUNC, - .pca9548_bus = 2, - .pca9548_addr = 0x77, - .rst_delay_b = 0, - .rst_delay = 1000, - .rst_delay_a = 1000, - .attr = { - .func_attr.reset_func = pca954x_hw_do_reset_by_lpc, - .func_attr.get_umask_func = pca954x_get_umask_by_lpc, - .func_attr.cfg_offset = {0x960, -1}, - .func_attr.umask = {BIT(1), -1}, - }, - }, - }, - }, -}; -int g_pca954x_debug = 0; -module_param(g_pca954x_debug, int, S_IRUGO | S_IWUSR); - -#define PCA954X_DEBUG(fmt, args...) do { \ - if (g_pca954x_debug) { \ - printk(KERN_ERR "[PCA95x][VER][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ - } \ -} while (0) - - -static int dfd_get_my_dev_type_by_file(void) -{ - struct file *fp; - /* mm_segment_t fs;*/ - loff_t pos; - static int card_type; - char buf[DFD_PID_BUF_LEN]; - - if (card_type != 0) { - return card_type; - } - - fp= filp_open(DFD_PUB_CARDTYPE_FILE, O_RDONLY, 0); - if (IS_ERR(fp)) { - PCA954X_DEBUG("open file fail!\r\n"); - return -1; - } - /* fs = get_fs(); */ - /* set_fs(KERNEL_DS); */ - memset(buf, 0, DFD_PID_BUF_LEN); - pos = 0; - kernel_read(fp, buf, DFD_PRODUCT_ID_LENGTH + 1, &pos); - // kernel_read(fp, pos, buf, DFD_PRODUCT_ID_LENGTH + 1 ); - if (pos < 0) { - PCA954X_DEBUG("read file fail!\r\n"); - goto exit; - } - - card_type = simple_strtoul(buf, NULL, 10); - PCA954X_DEBUG("card_type 0x%x.\n", card_type); - -exit: - /* set_fs(fs); */ - filp_close(fp, NULL); - return card_type; -} - -static int drv_get_my_dev_type(void) -{ - static int type = -1; - - if (type > 0) { - return type; - } - type = dfd_get_my_dev_type_by_file(); - PCA954X_DEBUG("ko board type %d\r\n", type); - - return type; -} - -pca9548_card_info_t* pca9548_get_card_info(int dev_type) -{ - int i, j; - int size; - - size = ARRAY_SIZE(g_pca9548_card_info); - - PCA954X_DEBUG("Enter dev_type 0x%x size %d.\n", dev_type, size); - for (i = 0; i < size; i++) { - for(j = 0; j < DFD_MAX_PRODUCT_NUM; j++) { - if (g_pca9548_card_info[i].dev_type[j] == dev_type) { - PCA954X_DEBUG("match dev_type 0x%x.\n", dev_type); - return &g_pca9548_card_info[i]; - } - } - } - - PCA954X_DEBUG("dismatch dev_type 0x%x.\n", dev_type); - return NULL; -} - -pca9548_cfg_info_t* get_pca9548_cfg_info(int bus, int addr) -{ - int dev_type; - pca9548_card_info_t *info; - pca9548_cfg_info_t *pca9548_cfg_info; - int i; - int size; - - dev_type = drv_get_my_dev_type(); - if (dev_type < 0) { - PCA954X_DEBUG("drv_get_my_dev_type failed ret %d.\n", dev_type); - return NULL; - } - - info = pca9548_get_card_info(dev_type); - if (info == NULL) { - PCA954X_DEBUG("fpga_pcie_get_card_info dev_type %d failed.\n", dev_type); - return NULL; - } - - size = PCA9548_MAX_CPLD_NUM; - for (i = 0; i < size; i++) { - pca9548_cfg_info = &(info->pca9548_cfg_info[i]); - if ((pca9548_cfg_info->pca9548_bus == bus) && (pca9548_cfg_info->pca9548_addr == addr)) { - PCA954X_DEBUG("match dev_type 0x%x bus %d addr 0x%x.\n", dev_type, bus, addr); - return pca9548_cfg_info; - } - } - - PCA954X_DEBUG("dismatch dev_type 0x%x bus %d addr 0x%x.\n", dev_type, bus, addr); - return NULL; -} - -static void pca9548_gpio_init(gpio_attr_t *gpio_attr) -{ - if (gpio_attr->gpio_init == 0) { - PCA954X_DEBUG("gpio%d init.\n", gpio_attr->gpio); - gpio_request(gpio_attr->gpio, "pca9548_reset"); - gpio_direction_output(gpio_attr->gpio, gpio_attr->reset_off); - gpio_attr->gpio_init = 1; - } -} - -static void pca9548_gpio_free(gpio_attr_t *gpio_attr) -{ - if (gpio_attr == NULL) { - PCA954X_DEBUG("pca9548_gpio_free,params error\n"); - return ; - } - if (gpio_attr->gpio_init == 1) { - PCA954X_DEBUG("gpio%d release.\n", gpio_attr->gpio); - gpio_free(gpio_attr->gpio); - gpio_attr->gpio_init = 0; - } -} - -static int pca954x_do_gpio_reset(pca9548_cfg_info_t *cfg_info, struct i2c_adapter *adap, - struct i2c_client *client, u32 chan) -{ - struct i2c_mux_core *muxc = i2c_get_clientdata(client); - struct pca954x *data = i2c_mux_priv(muxc); - int ret = -1; - gpio_attr_t *tmp_gpio_attr; - int timeout; - int val; - struct i2c_adapter *adapter; - int adapter_timeout; - - if (cfg_info == NULL) { - PCA954X_DEBUG("pca9548 cfg info is null.\n"); - return ret; - } - - if (cfg_info->pca9548_reset_type == PCA9548_RESET_GPIO) { - tmp_gpio_attr = &(cfg_info->attr.gpio_attr); - timeout = cfg_info->rst_delay_a; - - pca9548_gpio_init(tmp_gpio_attr); - udelay(cfg_info->rst_delay_b); - /* reset on */ - PCA954X_DEBUG("set gpio%d %d.\n", tmp_gpio_attr->gpio, tmp_gpio_attr->reset_on); - __gpio_set_value(tmp_gpio_attr->gpio, tmp_gpio_attr->reset_on); - udelay(cfg_info->rst_delay); - /* reset off */ - PCA954X_DEBUG("set gpio%d %d.\n", tmp_gpio_attr->gpio, tmp_gpio_attr->reset_off); - __gpio_set_value(tmp_gpio_attr->gpio, tmp_gpio_attr->reset_off); - - while (timeout > 0) { - udelay(1); - val = __gpio_get_value(tmp_gpio_attr->gpio); - if (val == tmp_gpio_attr->reset_off) { - adapter = adap; - /* get bus info */ - while(i2c_parent_is_i2c_adapter(adapter)){ - adapter = to_i2c_adapter(adapter->dev.parent); - } - - adapter_timeout = adapter->timeout; - adapter->timeout = msecs_to_jiffies(50); - pca954x_reg_write(adap, client, data->last_chan); - adapter->timeout = adapter_timeout; - ret = 0; - PCA954X_DEBUG("pca954x_do_gpio_reset success.\n"); - break; - } - - if (timeout >= 1000 && (timeout % 1000 == 0)) { - /* 1MS schedule*/ - schedule(); - } - timeout--; - } - - if (ret) { - PCA954X_DEBUG("pca954x_do_gpio_reset failed.\n"); - } - pca9548_gpio_free(&(cfg_info->attr.gpio_attr)); - } else { - PCA954X_DEBUG("pca9548_reset_type invalid, pca954x_do_gpio_reset failed.\n"); - } - - return ret; -} - -static int pca954x_do_func_reset(pca9548_cfg_info_t *cfg_info, struct i2c_adapter *adap, - struct i2c_client *client, u32 chan) -{ - struct i2c_mux_core *muxc = i2c_get_clientdata(client); - struct pca954x *data = i2c_mux_priv(muxc); - int ret = -1; - func_attr_t *tmp_func_attr; - int timeout; - int val; - struct i2c_adapter *adapter; - int adapter_timeout; - int i; - u8 old_value; - - if (cfg_info == NULL) { - PCA954X_DEBUG("pca9548 cfg info is null.\n"); - return ret; - } - - if (cfg_info->pca9548_reset_type == PCA9548_RESET_FUNC) { - tmp_func_attr = &(cfg_info->attr.func_attr); - timeout = cfg_info->rst_delay_a; - - if ((tmp_func_attr->reset_func == NULL) || (tmp_func_attr->get_umask_func == NULL)) { - PCA954X_DEBUG("pca954x hw do reset func or get umask func is null.\n"); - return ret; - } - - for(i = 0; (i < PCA9548_MAX_CPLD_LAYER) && (tmp_func_attr->cfg_offset[i] != -1) - && (tmp_func_attr->umask[i] != -1); i++) { - old_value = (*tmp_func_attr->get_umask_func)(tmp_func_attr->cfg_offset[i]); - PCA954X_DEBUG("cfg info: offset:0x%x umask:0x%x, old_value:0x%x\n", - tmp_func_attr->cfg_offset[i], tmp_func_attr->umask[i],old_value); - (*tmp_func_attr->reset_func)(tmp_func_attr->cfg_offset[i], old_value & ~tmp_func_attr->umask[i]); - udelay(cfg_info->rst_delay); - (*tmp_func_attr->reset_func)(tmp_func_attr->cfg_offset[i], old_value | tmp_func_attr->umask[i]); - } - - while (timeout > 0) { - udelay(1); - val = (*tmp_func_attr->get_umask_func)(tmp_func_attr->cfg_offset[i - 1]); - val &= (tmp_func_attr->umask[i - 1]); - if (val == tmp_func_attr->umask[i - 1]) { - adapter = adap; - /* get bus info */ - while(i2c_parent_is_i2c_adapter(adapter)){ - adapter = to_i2c_adapter(adapter->dev.parent); - } - - adapter_timeout = adapter->timeout; - adapter->timeout = msecs_to_jiffies(50); - pca954x_reg_write(adap, client, data->last_chan); - adapter->timeout = adapter_timeout; - ret = 0; - PCA954X_DEBUG("pca954x_do_func_reset success.\n"); - break; - } - - if (timeout >= 1000 && (timeout % 1000 == 0)) { - /* 1MS schedule*/ - schedule(); - } - timeout--; - } - - if (ret) { - PCA954X_DEBUG("pca954x_do_func_reset failed.\n"); - } - } else { - PCA954X_DEBUG("pca9548_reset_type invalid, pca954x_do_func_reset failed.\n"); - } - - return ret; -} - -static int pca9548_reset_ctrl(pca9548_cfg_info_t *cfg_info, struct i2c_adapter *adap, - struct i2c_client *client, u32 chan) -{ - int ret = -1; - - if (cfg_info == NULL) { - PCA954X_DEBUG("pca9548 cfg info is null.\n"); - return ret; - } - - if (cfg_info->pca9548_reset_type == PCA9548_RESET_FUNC) { - ret = pca954x_do_func_reset(cfg_info, adap, client, chan); - } else if (cfg_info->pca9548_reset_type == PCA9548_RESET_GPIO) { - ret = pca954x_do_gpio_reset(cfg_info, adap, client, chan); - } - - if (ret < 0) { - PCA954X_DEBUG("pca9548_reset_ctrl failed.\n"); - } - return ret; -} - -static int pca954x_reset_i2c_read(uint32_t bus, uint32_t addr, uint32_t offset_addr, - unsigned char *buf, uint32_t size) -{ - struct file *fp; - /* mm_segment_t fs; */ - struct i2c_client client; - char i2c_path[32]; - int i ,j ; - int rv; - - rv = 0; - memset(i2c_path, 0, 32); - snprintf(i2c_path, sizeof(i2c_path), "/dev/i2c-%d", bus); - fp = filp_open(i2c_path, O_RDWR, S_IRUSR | S_IWUSR); - if (IS_ERR(fp)) { - PCA954X_DEBUG("i2c open fail.\n"); - return -1; - } - memcpy(&client, fp->private_data, sizeof(struct i2c_client)); - client.addr = addr; - /* fs = get_fs(); */ - /* set_fs(KERNEL_DS); */ - for (j = 0 ;j < size ;j++){ - for (i = 0; i < I2C_RETRY_TIMES; i++) { - rv = i2c_smbus_read_byte_data(&client, (offset_addr + j)); - if (rv < 0) { - PCA954X_DEBUG("i2c read failed, try again.\n"); - msleep(I2C_RETRY_WAIT_TIMES); - if (i >= (I2C_RETRY_TIMES - 1)) { - goto out; - } - continue; - } - *(buf + j) = (unsigned char)rv; - break; - } - } -out: - filp_close(fp, NULL); - /* set_fs(fs); */ - return rv; -} - -static int pca954x_reset_i2c_write(uint32_t bus, uint32_t dev_addr, uint32_t offset_addr, - uint8_t write_buf) -{ - struct file *fp; - /* mm_segment_t fs; */ - struct i2c_client client; - char i2c_path[32]; - int i; - int rv; - - rv = 0; - memset(i2c_path, 0, 32); - snprintf(i2c_path, sizeof(i2c_path), "/dev/i2c-%d", bus); - fp = filp_open(i2c_path, O_RDWR, S_IRUSR | S_IWUSR); - if (IS_ERR(fp)) { - PCA954X_DEBUG("i2c open fail.\n"); - return -1; - } - memcpy(&client, fp->private_data, sizeof(struct i2c_client)); - client.addr = dev_addr; - /* fs = get_fs(); */ - /* set_fs(KERNEL_DS); */ - for (i = 0; i < I2C_RETRY_TIMES; i++) { - rv = i2c_smbus_write_byte_data(&client, offset_addr, write_buf); - if (rv < 0) { - PCA954X_DEBUG("i2c write failed, try again.\n"); - msleep(I2C_RETRY_WAIT_TIMES); - if (i >= (I2C_RETRY_TIMES - 1)) { - goto out; - } - continue; - } - break; - } -out: - filp_close(fp, NULL); - /* set_fs(fs); */ - return rv; -} - -int pca954x_reset_reg_i2c_read_byte(int addr, u8 *value) -{ - int bus; - int client_addr; - int offset; - int ret; - - bus = PCA9548_I2C_GET_BUS(addr); - client_addr = PCA9548_I2C_GET_CLIENT(addr); - offset = PCA9548_I2C_GET_OFFSET(addr); - - ret = pca954x_reset_i2c_read(bus, client_addr, offset, value, 1); - if (ret < 0) { - PCA954X_DEBUG(" 0x%x read fail\r\n", addr); - goto end; - } -end: - return ret; -} - -int pca954x_reset_reg_i2c_write_byte(int addr, u8 value) -{ - int bus; - int client_addr; - int offset; - int ret; - - bus = PCA9548_I2C_GET_BUS(addr); - client_addr = PCA9548_I2C_GET_CLIENT(addr); - offset = PCA9548_I2C_GET_OFFSET(addr); - - ret = pca954x_reset_i2c_write(bus, client_addr, offset, value); - if (ret < 0) { - PCA954X_DEBUG(" 0x%x write fail\r\n", addr); - goto end; - } -end: - return ret; -} - -void pca954x_hw_do_reset_by_i2c(int addr, u8 value) -{ - int ret; - - PCA954X_DEBUG("write i2c cpld[0x%x], value[%d]\n", addr, value); - ret = pca954x_reset_reg_i2c_write_byte(addr, value); - if (ret < 0) { - PCA954X_DEBUG("write cpld pca9548 reset reg failed, ret = %d \n", ret); - } -} - -u8 pca954x_get_umask_by_i2c(int addr) -{ - u8 value = 0xFF; - int ret; - - ret = pca954x_reset_reg_i2c_read_byte(addr, &value); - PCA954X_DEBUG("read i2c cpld[0x%x], value[%d], ret = %d\n", addr, value, ret); - - return value; -} - -void pca954x_hw_do_reset_by_lpc(int io_port, u8 value) -{ - PCA954X_DEBUG("write lpc offset[0x%x], value[%d]\n", (u16)io_port, value); - outb(value, (u16)io_port); -} - -u8 pca954x_get_umask_by_lpc(int io_port) -{ - u8 value; - - value = inb(io_port); - PCA954X_DEBUG("read lpc offset[0x%x], value[%d]\n", (u16)io_port, value); - - return value; -} - -int pca954x_hw_do_reset_new(struct i2c_adapter *adap, - struct i2c_client *client, u32 chan) -{ - pca9548_cfg_info_t *cfg_info; - int ret = -1; - - cfg_info = get_pca9548_cfg_info(adap->nr, client->addr); - if (cfg_info == NULL && g_notify_to_do_reset == NULL) { - PCA954X_DEBUG("fpga_do_pca954x_reset_func do nothing.\n"); - return ret; - } - if(cfg_info != NULL) { - ret = pca9548_reset_ctrl(cfg_info, adap, client, chan); - } else { - ret = pca954x_hw_do_reset(adap->nr, client->addr); - } - if (ret < 0) { - PCA954X_DEBUG("pca954x_hw_do_reset failed.\n"); - } - return ret; -} -/******************************end 9548 reset***********************************/ - -static int pca954x_do_reset(struct i2c_adapter *adap, - void *client, u32 chan) -{ - struct i2c_client *new_client; - int ret = -1; - - PCA954X_DEBUG("do pca954x reset x86\n"); - new_client =(struct i2c_client *) client; - ret = pca954x_hw_do_reset_new(adap, new_client, chan); - if (ret < 0) { - PCA954X_DEBUG("pca954x_do_reset failed.\n"); - return ret; - } - - PCA954X_DEBUG("pca954x_do_reset success.\n"); - ret = 0; - return ret; -} - -static int pca954x_select_chan(struct i2c_mux_core *muxc, u32 chan) -{ - struct pca954x *data = i2c_mux_priv(muxc); - struct i2c_client *client = data->client; - const struct chip_desc *chip = data->chip; - u8 regval; - int ret = 0; - u8 read_val; - int rv; - - read_val = 0; -#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0) - regval = pca954x_regval(data, chan); -#else - /* we make switches look like muxes, not sure how to be smarter */ - if (chip->muxtype == pca954x_ismux) - regval = chan | chip->enable; - else - regval = 1 << chan; -#endif - - /* Only select the channel if its different from the last channel */ - if (data->last_chan != regval) { - pca954x_setmuxflag(client, 0); - ret = pca954x_reg_write(muxc->parent, client, regval); - data->last_chan = ret < 0 ? 0 : regval; - } - - if (select_chan_check) { /* check chan */ - ret = pca954x_reg_read(muxc->parent, client, &read_val); - /* read failed or chan not open, reset pca9548 */ - if ((ret < 0) || (read_val != data->last_chan)) { - dev_warn(&client->dev, "pca954x open channle %u failed, do reset.\n", chan); - PCA954X_DEBUG("ret = %d, read_val = %d, last_chan = %d.\n", ret, read_val, data->last_chan); - rv = pca954x_do_reset(client->adapter, client, chan); - if (rv >= 0) { - PCA954X_DEBUG("pca954x_do_reset success, rv = %d.\n", rv); - } else { - PCA954X_DEBUG("pca954x_do_reset failed, rv = %d.\n", rv); - } - if (ret >= 0) { - ret = -EIO; /* chan not match, return IO error */ - } - } - } - - return ret; -} - -#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0) -static int pca954x_deselect_mux(struct i2c_mux_core *muxc, u32 chan) -{ - struct pca954x *data = i2c_mux_priv(muxc); - struct i2c_client *client = data->client; - s32 idle_state; - int ret, rv; - struct i2c_client * new_client; - - if (close_chan_force_reset) { - data->last_chan = 0; - ret = pca954x_do_reset(client->adapter, client, chan); - if (ret < 0) { - dev_warn(&client->dev, "pca954x do reset failed %d.\n", ret); - } - return ret; - } else { - idle_state = READ_ONCE(data->idle_state); - if (idle_state >= 0) - /* Set the mux back to a predetermined channel */ - return pca954x_select_chan(muxc, idle_state); - if (idle_state == MUX_IDLE_DISCONNECT) { - /* Deselect active channel */ - data->last_chan = 0; - ret = pca954x_reg_write(muxc->parent, client, - data->last_chan); - if (ret < 0) { - new_client =(struct i2c_client *) client; - dev_warn(&new_client->dev, "pca954x close chn failed, do reset.\n"); - rv = pca954x_do_reset(client->adapter, client, chan); - if (rv == 0) { - ret = 0; - } - } - return ret; - } - } - - /* otherwise leave as-is */ - - return 0; -} - -static ssize_t idle_state_show(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - struct i2c_client *client = to_i2c_client(dev); - struct i2c_mux_core *muxc = i2c_get_clientdata(client); - struct pca954x *data = i2c_mux_priv(muxc); - - return sprintf(buf, "%d\n", READ_ONCE(data->idle_state)); -} - -static ssize_t idle_state_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) -{ - struct i2c_client *client = to_i2c_client(dev); - struct i2c_mux_core *muxc = i2c_get_clientdata(client); - struct pca954x *data = i2c_mux_priv(muxc); - int val; - int ret; - - ret = kstrtoint(buf, 0, &val); - if (ret < 0) - return ret; - - if (val != MUX_IDLE_AS_IS && val != MUX_IDLE_DISCONNECT && - (val < 0 || val >= data->chip->nchans)) - return -EINVAL; - - i2c_lock_bus(muxc->parent, I2C_LOCK_SEGMENT); - - WRITE_ONCE(data->idle_state, val); - /* - * Set the mux into a state consistent with the new - * idle_state. - */ - if (data->last_chan || val != MUX_IDLE_DISCONNECT) - ret = pca954x_deselect_mux(muxc, 0); - - i2c_unlock_bus(muxc->parent, I2C_LOCK_SEGMENT); - - return ret < 0 ? ret : count; -} - -static DEVICE_ATTR_RW(idle_state); - -static irqreturn_t pca954x_irq_handler(int irq, void *dev_id) -{ - struct pca954x *data = dev_id; - unsigned long pending; - int ret, i; - - ret = i2c_smbus_read_byte(data->client); - if (ret < 0) - return IRQ_NONE; - - pending = (ret >> PCA954X_IRQ_OFFSET) & (BIT(data->chip->nchans) - 1); - for_each_set_bit(i, &pending, data->chip->nchans) - handle_nested_irq(irq_linear_revmap(data->irq, i)); - - return IRQ_RETVAL(pending); -} - -static int pca954x_init(struct i2c_client *client, struct pca954x *data) -{ - int ret; - - if (data->idle_state >= 0) - data->last_chan = pca954x_regval(data, data->idle_state); - else - data->last_chan = 0; /* Disconnect multiplexer */ - - ret = i2c_smbus_write_byte(client, data->last_chan); - if (ret < 0) - data->last_chan = 0; - - return ret; -} - -#else -static int pca954x_deselect_mux(struct i2c_mux_core *muxc, u32 chan) -{ - struct pca954x *data = i2c_mux_priv(muxc); - struct i2c_client *client = data->client; - int ret, rv; - struct i2c_client * new_client; - - /* Deselect active channel */ - data->last_chan = 0; - - ret = pca954x_reg_write(muxc->parent, client, data->last_chan); - if (ret < 0) { - new_client =(struct i2c_client *) client; - dev_warn(&new_client->dev, "pca954x close chn failed, do reset.\n"); - rv = pca954x_do_reset(client->adapter, client, chan); - if (rv == 0) { - ret = 0; - } - - } - pca954x_setmuxflag(client, 1); - (void)pca954x_reg_write(muxc->parent, client, data->last_chan); - - return ret; - -} - -static irqreturn_t pca954x_irq_handler(int irq, void *dev_id) -{ - struct pca954x *data = dev_id; - unsigned int child_irq; - int ret, i, handled = 0; - - ret = i2c_smbus_read_byte(data->client); - if (ret < 0) - return IRQ_NONE; - - for (i = 0; i < data->chip->nchans; i++) { - if (ret & BIT(PCA954X_IRQ_OFFSET + i)) { - child_irq = irq_linear_revmap(data->irq, i); - handle_nested_irq(child_irq); - handled++; - } - } - return handled ? IRQ_HANDLED : IRQ_NONE; -} -#endif - -static void pca954x_irq_mask(struct irq_data *idata) -{ - struct pca954x *data = irq_data_get_irq_chip_data(idata); - unsigned int pos = idata->hwirq; - unsigned long flags; - - raw_spin_lock_irqsave(&data->lock, flags); - - data->irq_mask &= ~BIT(pos); - if (!data->irq_mask) - disable_irq(data->client->irq); - - raw_spin_unlock_irqrestore(&data->lock, flags); -} - -static void pca954x_irq_unmask(struct irq_data *idata) -{ - struct pca954x *data = irq_data_get_irq_chip_data(idata); - unsigned int pos = idata->hwirq; - unsigned long flags; - - raw_spin_lock_irqsave(&data->lock, flags); - - if (!data->irq_mask) - enable_irq(data->client->irq); - data->irq_mask |= BIT(pos); - - raw_spin_unlock_irqrestore(&data->lock, flags); -} - -static int pca954x_irq_set_type(struct irq_data *idata, unsigned int type) -{ - if ((type & IRQ_TYPE_SENSE_MASK) != IRQ_TYPE_LEVEL_LOW) - return -EINVAL; - return 0; -} - -static struct irq_chip pca954x_irq_chip = { - .name = "i2c-mux-pca954x", - .irq_mask = pca954x_irq_mask, - .irq_unmask = pca954x_irq_unmask, - .irq_set_type = pca954x_irq_set_type, -}; - -static int pca954x_irq_setup(struct i2c_mux_core *muxc) -{ - struct pca954x *data = i2c_mux_priv(muxc); - struct i2c_client *client = data->client; - int c, err, irq; - - if (!data->chip->has_irq || client->irq <= 0) - return 0; - - raw_spin_lock_init(&data->lock); - - data->irq = irq_domain_add_linear(client->dev.of_node, - data->chip->nchans, - &irq_domain_simple_ops, data); - if (!data->irq) - return -ENODEV; - - for (c = 0; c < data->chip->nchans; c++) { - irq = irq_create_mapping(data->irq, c); - irq_set_chip_data(irq, data); - irq_set_chip_and_handler(irq, &pca954x_irq_chip, - handle_simple_irq); - } - - err = devm_request_threaded_irq(&client->dev, data->client->irq, NULL, - pca954x_irq_handler, - IRQF_ONESHOT | IRQF_SHARED, - "pca954x", data); - if (err) - goto err_req_irq; - - disable_irq(data->client->irq); - - return 0; -err_req_irq: - for (c = 0; c < data->chip->nchans; c++) { - irq = irq_find_mapping(data->irq, c); - irq_dispose_mapping(irq); - } - irq_domain_remove(data->irq); - - return err; -} - -/* - * I2C init/probing/exit functions - */ -static int pca954x_probe(struct i2c_client *client, - const struct i2c_device_id *id) -{ - struct i2c_adapter *adap = to_i2c_adapter(client->dev.parent); -#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0) - struct pca954x_platform_data *pdata = dev_get_platdata(&client->dev); -#endif - struct device_node *of_node = client->dev.of_node; - bool idle_disconnect_dt; - struct gpio_desc *gpio; - int num, force, class; - struct i2c_mux_core *muxc; - struct pca954x *data; - const struct of_device_id *match; - int ret; - - - if (!i2c_check_functionality(adap, I2C_FUNC_SMBUS_BYTE)) - return -ENODEV; - - muxc = i2c_mux_alloc(adap, &client->dev, - PCA954X_MAX_NCHANS, sizeof(*data), 0, - pca954x_select_chan, pca954x_deselect_mux); - if (!muxc) - return -ENOMEM; - data = i2c_mux_priv(muxc); - - i2c_set_clientdata(client, muxc); - data->client = client; - - /* Get the mux out of reset if a reset GPIO is specified. */ - gpio = devm_gpiod_get_optional(&client->dev, "reset", GPIOD_OUT_LOW); - if (IS_ERR(gpio)) - return PTR_ERR(gpio); -#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0) - data->idle_state = MUX_IDLE_AS_IS; - if (device_property_read_u32(&client->dev, "idle-state", &data->idle_state)) { - if (device_property_read_bool(&client->dev, "i2c-mux-idle-disconnect")) - data->idle_state = MUX_IDLE_DISCONNECT; - } - - /* - * Write the mux register at addr to verify - * that the mux is in fact present. This also - * initializes the mux to a channel - * or disconnected state. - */ - ret = pca954x_init(client, data); - if (ret < 0) { - dev_warn(&client->dev, "probe failed\n"); - return -ENODEV; - } -#else - /* Write the mux register at addr to verify - * that the mux is in fact present. This also - * initializes the mux to disconnected state. - */ - if ((i2c_smbus_write_byte(client, 0) < 0) && (force_create_bus == 0)) { - dev_warn(&client->dev, "probe failed\n"); - return -ENODEV; - } -#endif - match = of_match_device(of_match_ptr(pca954x_of_match), &client->dev); - if (match) - data->chip = of_device_get_match_data(&client->dev); - else - data->chip = &chips[id->driver_data]; - - data->last_chan = 0; /* force the first selection */ - - idle_disconnect_dt = of_node && - of_property_read_bool(of_node, "i2c-mux-idle-disconnect"); - - ret = pca954x_irq_setup(muxc); - if (ret) - goto fail_del_adapters; - - /* Now create an adapter for each channel */ - for (num = 0; num < data->chip->nchans; num++) { -#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0) - ret = i2c_mux_add_adapter(muxc, 0, num, 0); -#else - bool idle_disconnect_pd = false; - - force = 0; /* dynamic adap number */ - class = 0; /* no class by default */ - if (pdata) { - if (num < pdata->num_modes) { - /* force static number */ - force = pdata->modes[num].adap_id; - class = pdata->modes[num].class; - } else - /* discard unconfigured channels */ - break; - idle_disconnect_pd = pdata->modes[num].deselect_on_exit; - } - data->deselect |= (idle_disconnect_pd || - idle_disconnect_dt) << num; - - ret = i2c_mux_add_adapter(muxc, force, num, class); -#endif - if (ret) - goto fail_del_adapters; - } -#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0) - /* - * The attr probably isn't going to be needed in most cases, - * so don't fail completely on error. - */ - device_create_file(&client->dev, &dev_attr_idle_state); -#endif - dev_info(&client->dev, - "registered %d multiplexed busses for I2C %s %s\n", - num, data->chip->muxtype == pca954x_ismux - ? "mux" : "switch", client->name); - - return 0; - -fail_del_adapters: - i2c_mux_del_adapters(muxc); - return ret; -} - -static int pca954x_remove(struct i2c_client *client) -{ - struct i2c_mux_core *muxc = i2c_get_clientdata(client); - struct pca954x *data = i2c_mux_priv(muxc); - int c, irq; - - if (data->irq) { - for (c = 0; c < data->chip->nchans; c++) { - irq = irq_find_mapping(data->irq, c); - irq_dispose_mapping(irq); - } - irq_domain_remove(data->irq); - } -#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0) - device_remove_file(&client->dev, &dev_attr_idle_state); -#endif - i2c_mux_del_adapters(muxc); - return 0; -} - -#ifdef CONFIG_PM_SLEEP -static int pca954x_resume(struct device *dev) -{ - struct i2c_client *client = to_i2c_client(dev); - struct i2c_mux_core *muxc = i2c_get_clientdata(client); - struct pca954x *data = i2c_mux_priv(muxc); -#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0) - int ret; - - ret = pca954x_init(client, data); - if (ret < 0) - dev_err(&client->dev, "failed to verify mux presence\n"); - - return ret; -#else - data->last_chan = 0; - return i2c_smbus_write_byte(client, 0); -#endif -} -#endif - -static SIMPLE_DEV_PM_OPS(pca954x_pm, NULL, pca954x_resume); - -static struct i2c_driver pca954x_driver = { - .driver = { - .name = "pca954x", - .pm = &pca954x_pm, - .of_match_table = of_match_ptr(pca954x_of_match), - }, - .probe = pca954x_probe, - .remove = pca954x_remove, - .id_table = pca954x_id, -}; - -module_i2c_driver(pca954x_driver); - -MODULE_AUTHOR("support support@ragile.com"); -MODULE_DESCRIPTION("PCA954x I2C mux/switch driver"); -MODULE_LICENSE("GPL"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/i2c-mux-pca9641.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/i2c-mux-pca9641.c deleted file mode 100755 index 4988fcc7f2c3..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/common/modules/i2c-mux-pca9641.c +++ /dev/null @@ -1,653 +0,0 @@ -/* - * I2C multiplexer driver for PCA9541 bus master selector - * - * Copyright (c) 2010 Ericsson AB. - * Copyright (c) 2019 - * Author: Guenter Roeck - * - * Derived from: - * pca954x.c - * - * Copyright (c) 2008-2009 Rodolfo Giometti - * Copyright (c) 2008-2009 Eurotech S.p.A. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0) -#include -#else -#include -#endif - -/* - * The PCA9541 is a bus master selector. It supports two I2C masters connected - * to a single slave bus. - * - * Before each bus transaction, a master has to acquire bus ownership. After the - * transaction is complete, bus ownership has to be released. This fits well - * into the I2C multiplexer framework, which provides select and release - * functions for this purpose. For this reason, this driver is modeled as - * single-channel I2C bus multiplexer. - * - * This driver assumes that the two bus masters are controlled by two different - * hosts. If a single host controls both masters, platform code has to ensure - * that only one of the masters is instantiated at any given time. - */ - -#define PCA9541_CONTROL 0x01 -#define PCA9541_ISTAT 0x02 - -#define PCA9541_CTL_MYBUS (1 << 0) -#define PCA9541_CTL_NMYBUS (1 << 1) -#define PCA9541_CTL_BUSON (1 << 2) -#define PCA9541_CTL_NBUSON (1 << 3) -#define PCA9541_CTL_BUSINIT (1 << 4) -#define PCA9541_CTL_TESTON (1 << 6) -#define PCA9541_CTL_NTESTON (1 << 7) -#define PCA9541_ISTAT_INTIN (1 << 0) -#define PCA9541_ISTAT_BUSINIT (1 << 1) -#define PCA9541_ISTAT_BUSOK (1 << 2) -#define PCA9541_ISTAT_BUSLOST (1 << 3) -#define PCA9541_ISTAT_MYTEST (1 << 6) -#define PCA9541_ISTAT_NMYTEST (1 << 7) -#define PCA9641_ID 0x00 -#define PCA9641_ID_MAGIC 0x38 -#define PCA9641_CONTROL 0x01 -#define PCA9641_STATUS 0x02 -#define PCA9641_TIME 0x03 -#define PCA9641_CTL_LOCK_REQ BIT(0) -#define PCA9641_CTL_LOCK_GRANT BIT(1) -#define PCA9641_CTL_BUS_CONNECT BIT(2) -#define PCA9641_CTL_BUS_INIT BIT(3) -#define PCA9641_CTL_SMBUS_SWRST BIT(4) -#define PCA9641_CTL_IDLE_TIMER_DIS BIT(5) -#define PCA9641_CTL_SMBUS_DIS BIT(6) -#define PCA9641_CTL_PRIORITY BIT(7) -#define PCA9641_STS_OTHER_LOCK BIT(0) -#define PCA9641_STS_BUS_INIT_FAIL BIT(1) -#define PCA9641_STS_BUS_HUNG BIT(2) -#define PCA9641_STS_MBOX_EMPTY BIT(3) -#define PCA9641_STS_MBOX_FULL BIT(4) -#define PCA9641_STS_TEST_INT BIT(5) -#define PCA9641_STS_SCL_IO BIT(6) -#define PCA9641_STS_SDA_IO BIT(7) -#define PCA9641_RES_TIME 0x03 -#define BUSON (PCA9541_CTL_BUSON | PCA9541_CTL_NBUSON) -#define MYBUS (PCA9541_CTL_MYBUS | PCA9541_CTL_NMYBUS) -#define mybus(x) (!((x) & MYBUS) || ((x) & MYBUS) == MYBUS) -#define busoff(x) (!((x) & BUSON) || ((x) & BUSON) == BUSON) -#define BUSOFF(x, y) (!((x) & PCA9641_CTL_LOCK_GRANT) && \ - !((y) & PCA9641_STS_OTHER_LOCK)) -#define other_lock(x) ((x) & PCA9641_STS_OTHER_LOCK) -#define lock_grant(x) ((x) & PCA9641_CTL_LOCK_GRANT) - -#define PCA9641_RETRY_TIME 8 - -typedef struct i2c_muxs_struct_flag -{ - int nr; - char name[48]; - struct mutex update_lock; - int flag; -}i2c_mux_flag; - -i2c_mux_flag pca_flag = { - .flag = -1, -}; - -int pca9641_setmuxflag(int nr, int flag) -{ - if (pca_flag.nr == nr) { - pca_flag.flag = flag; - } - return 0; -} -EXPORT_SYMBOL(pca9641_setmuxflag); - -int g_debug = 0; -module_param(g_debug, int, S_IRUGO | S_IWUSR); - -#define PCA_DEBUG(fmt, args...) do { \ - if (g_debug) { \ - printk(KERN_ERR "[pca9641][VER][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ - } \ -} while (0) - - -/* arbitration timeouts, in jiffies */ -#define ARB_TIMEOUT (HZ / 8) /* 125 ms until forcing bus ownership */ -#define ARB2_TIMEOUT (HZ / 4) /* 250 ms until acquisition failure */ - -/* arbitration retry delays, in us */ -#define SELECT_DELAY_SHORT 50 -#define SELECT_DELAY_LONG 1000 - -struct pca9541 { - struct i2c_client *client; - unsigned long select_timeout; - unsigned long arb_timeout; -}; - -static const struct i2c_device_id pca9541_id[] = { - {"pca9541", 0}, - {"pca9641", 1}, - {} -}; - -MODULE_DEVICE_TABLE(i2c, pca9541_id); - -#ifdef CONFIG_OF -static const struct of_device_id pca9541_of_match[] = { - { .compatible = "nxp,pca9541" }, - { .compatible = "nxp,pca9641" }, - {} -}; -MODULE_DEVICE_TABLE(of, pca9541_of_match); -#endif - - -/* - * Write to chip register. Don't use i2c_transfer()/i2c_smbus_xfer() - * as they will try to lock the adapter a second time. - */ -static int pca9541_reg_write(struct i2c_client *client, u8 command, u8 val) -{ - struct i2c_adapter *adap = client->adapter; - int ret; - - if (adap->algo->master_xfer) { - struct i2c_msg msg; - char buf[2]; - - msg.addr = client->addr; - msg.flags = 0; - msg.len = 2; - buf[0] = command; - buf[1] = val; - msg.buf = buf; - ret = __i2c_transfer(adap, &msg, 1); - } else { - union i2c_smbus_data data; - - data.byte = val; - ret = adap->algo->smbus_xfer(adap, client->addr, - client->flags, - I2C_SMBUS_WRITE, - command, - I2C_SMBUS_BYTE_DATA, &data); - } - - return ret; -} - -/* - * Read from chip register. Don't use i2c_transfer()/i2c_smbus_xfer() - * as they will try to lock adapter a second time. - */ -static int pca9541_reg_read(struct i2c_client *client, u8 command) -{ - struct i2c_adapter *adap = client->adapter; - int ret; - u8 val; - - if (adap->algo->master_xfer) { - struct i2c_msg msg[2] = { - { - .addr = client->addr, - .flags = 0, - .len = 1, - .buf = &command - }, - { - .addr = client->addr, - .flags = I2C_M_RD, - .len = 1, - .buf = &val - } - }; - ret = __i2c_transfer(adap, msg, 2); - if (ret == 2) - ret = val; - else if (ret >= 0) - ret = -EIO; - } else { - union i2c_smbus_data data; - - ret = adap->algo->smbus_xfer(adap, client->addr, - client->flags, - I2C_SMBUS_READ, - command, - I2C_SMBUS_BYTE_DATA, &data); - if (!ret) - ret = data.byte; - } - return ret; -} - -/* - * Arbitration management functions - */ - -/* Release bus. Also reset NTESTON and BUSINIT if it was set. */ -static void pca9541_release_bus(struct i2c_client *client) -{ - int reg; - - reg = pca9541_reg_read(client, PCA9541_CONTROL); - if (reg >= 0 && !busoff(reg) && mybus(reg)) - pca9541_reg_write(client, PCA9541_CONTROL, - (reg & PCA9541_CTL_NBUSON) >> 1); -} - -/* - * Arbitration is defined as a two-step process. A bus master can only activate - * the slave bus if it owns it; otherwise it has to request ownership first. - * This multi-step process ensures that access contention is resolved - * gracefully. - * - * Bus Ownership Other master Action - * state requested access - * ---------------------------------------------------- - * off - yes wait for arbitration timeout or - * for other master to drop request - * off no no take ownership - * off yes no turn on bus - * on yes - done - * on no - wait for arbitration timeout or - * for other master to release bus - * - * The main contention point occurs if the slave bus is off and both masters - * request ownership at the same time. In this case, one master will turn on - * the slave bus, believing that it owns it. The other master will request - * bus ownership. Result is that the bus is turned on, and master which did - * _not_ own the slave bus before ends up owning it. - */ - -/* Control commands per PCA9541 datasheet */ -static const u8 pca9541_control[16] = { - 4, 0, 1, 5, 4, 4, 5, 5, 0, 0, 1, 1, 0, 4, 5, 1 -}; - -/* - * Channel arbitration - * - * Return values: - * <0: error - * 0 : bus not acquired - * 1 : bus acquired - */ -static int pca9541_arbitrate(struct i2c_client *client) -{ - struct i2c_mux_core *muxc = i2c_get_clientdata(client); - struct pca9541 *data = i2c_mux_priv(muxc); - int reg; - - reg = pca9541_reg_read(client, PCA9541_CONTROL); - if (reg < 0) - return reg; - - if (busoff(reg)) { - int istat; - /* - * Bus is off. Request ownership or turn it on unless - * other master requested ownership. - */ - istat = pca9541_reg_read(client, PCA9541_ISTAT); - if (!(istat & PCA9541_ISTAT_NMYTEST) - || time_is_before_eq_jiffies(data->arb_timeout)) { - /* - * Other master did not request ownership, - * or arbitration timeout expired. Take the bus. - */ - pca9541_reg_write(client, - PCA9541_CONTROL, - pca9541_control[reg & 0x0f] - | PCA9541_CTL_NTESTON); - data->select_timeout = SELECT_DELAY_SHORT; - } else { - /* - * Other master requested ownership. - * Set extra long timeout to give it time to acquire it. - */ - data->select_timeout = SELECT_DELAY_LONG * 2; - } - } else if (mybus(reg)) { - /* - * Bus is on, and we own it. We are done with acquisition. - * Reset NTESTON and BUSINIT, then return success. - */ - if (reg & (PCA9541_CTL_NTESTON | PCA9541_CTL_BUSINIT)) - pca9541_reg_write(client, - PCA9541_CONTROL, - reg & ~(PCA9541_CTL_NTESTON - | PCA9541_CTL_BUSINIT)); - return 1; - } else { - /* - * Other master owns the bus. - * If arbitration timeout has expired, force ownership. - * Otherwise request it. - */ - data->select_timeout = SELECT_DELAY_LONG; - if (time_is_before_eq_jiffies(data->arb_timeout)) { - /* Time is up, take the bus and reset it. */ - pca9541_reg_write(client, - PCA9541_CONTROL, - pca9541_control[reg & 0x0f] - | PCA9541_CTL_BUSINIT - | PCA9541_CTL_NTESTON); - } else { - /* Request bus ownership if needed */ - if (!(reg & PCA9541_CTL_NTESTON)) - pca9541_reg_write(client, - PCA9541_CONTROL, - reg | PCA9541_CTL_NTESTON); - } - } - return 0; -} - -static int pca9541_select_chan(struct i2c_mux_core *muxc, u32 chan) -{ - struct pca9541 *data = i2c_mux_priv(muxc); - struct i2c_client *client = data->client; - int ret; - unsigned long timeout = jiffies + ARB2_TIMEOUT; - /* give up after this time */ - - data->arb_timeout = jiffies + ARB_TIMEOUT; - /* force bus ownership after this time */ - - do { - ret = pca9541_arbitrate(client); - if (ret) - return ret < 0 ? ret : 0; - - if (data->select_timeout == SELECT_DELAY_SHORT) - udelay(data->select_timeout); - else - msleep(data->select_timeout / 1000); - } while (time_is_after_eq_jiffies(timeout)); - - return -ETIMEDOUT; -} - -static int pca9541_release_chan(struct i2c_mux_core *muxc, u32 chan) -{ - struct pca9541 *data = i2c_mux_priv(muxc); - struct i2c_client *client = data->client; - pca9541_release_bus(client); - return 0; -} - -/* - * Arbitration management functions - */ -static void pca9641_release_bus(struct i2c_client *client) -{ - pca9541_reg_write(client, PCA9641_CONTROL, 0x80); //master 0x80 -} - -/* - * Channel arbitration - * - * Return values: - * <0: error - * 0 : bus not acquired - * 1 : bus acquired - */ -static int pca9641_arbitrate(struct i2c_client *client) -{ - struct i2c_mux_core *muxc = i2c_get_clientdata(client); - struct pca9541 *data = i2c_mux_priv(muxc); - int reg_ctl, reg_sts; - - reg_ctl = pca9541_reg_read(client, PCA9641_CONTROL); - if (reg_ctl < 0) - return reg_ctl; - reg_sts = pca9541_reg_read(client, PCA9641_STATUS); - - if (BUSOFF(reg_ctl, reg_sts)) { - /* - * Bus is off. Request ownership or turn it on unless - * other master requested ownership. - */ - reg_ctl |= PCA9641_CTL_LOCK_REQ; - pca9541_reg_write(client, PCA9641_CONTROL, reg_ctl); - reg_ctl = pca9541_reg_read(client, PCA9641_CONTROL); - - if (lock_grant(reg_ctl)) { - /* - * Other master did not request ownership, - * or arbitration timeout expired. Take the bus. - */ - reg_ctl |= PCA9641_CTL_BUS_CONNECT - | PCA9641_CTL_LOCK_REQ; - pca9541_reg_write(client, PCA9641_CONTROL, reg_ctl); - data->select_timeout = SELECT_DELAY_SHORT; - - return 1; - } else { - /* - * Other master requested ownership. - * Set extra long timeout to give it time to acquire it. - */ - data->select_timeout = SELECT_DELAY_LONG * 2; - } - } else if (lock_grant(reg_ctl)) { - /* - * Bus is on, and we own it. We are done with acquisition. - */ - reg_ctl |= PCA9641_CTL_BUS_CONNECT | PCA9641_CTL_LOCK_REQ; - pca9541_reg_write(client, PCA9641_CONTROL, reg_ctl); - - return 1; - } else if (other_lock(reg_sts)) { - /* - * Other master owns the bus. - * If arbitration timeout has expired, force ownership. - * Otherwise request it. - */ - data->select_timeout = SELECT_DELAY_LONG; - reg_ctl |= PCA9641_CTL_LOCK_REQ; - pca9541_reg_write(client, PCA9641_CONTROL, reg_ctl); - } - return 0; -} - - -int pca9641_select_chan(struct i2c_mux_core *muxc, u32 chan) -{ - struct pca9541 *data = i2c_mux_priv(muxc); - struct i2c_client *client = data->client; - int ret; - int result; - unsigned long timeout = jiffies + ARB2_TIMEOUT; - /* give up after this time */ - data->arb_timeout = jiffies + ARB_TIMEOUT; - /* force bus ownership after this time */ - for (result = 0 ; result < PCA9641_RETRY_TIME ; result ++) { - do { - ret = pca9641_arbitrate(client); - if (ret == 1) { - return 0; - } - if (data->select_timeout == SELECT_DELAY_SHORT) - udelay(data->select_timeout); - else - msleep(data->select_timeout / 1000); - } while (time_is_after_eq_jiffies(timeout)); - timeout = jiffies + ARB2_TIMEOUT; - } - return -ETIMEDOUT; -} -EXPORT_SYMBOL(pca9641_select_chan); - -static int pca9641_release_chan(struct i2c_mux_core *muxc, u32 chan) -{ - struct pca9541 *data = i2c_mux_priv(muxc); - struct i2c_client *client = data->client; - if (pca_flag.flag) { - pca9641_release_bus(client); - } - return 0; -} - -static int pca9641_detect_id(struct i2c_client *client) -{ - int reg; - - reg = pca9541_reg_read(client, PCA9641_ID); - if (reg == PCA9641_ID_MAGIC) - return 1; - else - return 0; -} - - -static int pca9641_recordflag(struct i2c_adapter *adap) { - if (pca_flag.flag != -1) { - pr_err(" %s %d has init already!!!", __func__, __LINE__); - return -1 ; - } - pca_flag.nr = adap->nr; - PCA_DEBUG(" adap->nr:%d\n", adap->nr); - snprintf(pca_flag.name, sizeof(pca_flag.name),adap->name); - return 0; -} - -static void i2c_lock_adapter(struct i2c_adapter *adapter){ - struct i2c_adapter *parent = i2c_parent_is_i2c_adapter(adapter); - if (parent) - i2c_lock_adapter(parent); - else - rt_mutex_lock(&adapter->bus_lock); -} - -void i2c_unlock_adapter(struct i2c_adapter *adapter) -{ - struct i2c_adapter *parent = i2c_parent_is_i2c_adapter(adapter); - - if (parent) - i2c_unlock_adapter(parent); - else - rt_mutex_unlock(&adapter->bus_lock); -} -/* - * I2C init/probing/exit functions - */ -static int pca9541_probe(struct i2c_client *client, - const struct i2c_device_id *id) -{ - struct i2c_adapter *adap = client->adapter; -#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0) - struct pca954x_platform_data *pdata = dev_get_platdata(&client->dev); -#endif - struct i2c_mux_core *muxc; - struct pca9541 *data; - int force; - int ret = -ENODEV; - int detect_id; - - if (!i2c_check_functionality(adap, I2C_FUNC_SMBUS_BYTE_DATA)) - return -ENODEV; - - detect_id = pca9641_detect_id(client); - - /* - * I2C accesses are unprotected here. - * We have to lock the adapter before releasing the bus. - */ - if (detect_id == 0) { - i2c_lock_adapter(adap); - pca9541_release_bus(client); - i2c_unlock_adapter(adap); - } else { - i2c_lock_adapter(adap); - pca9641_release_bus(client); - i2c_unlock_adapter(adap); - } - - /* Create mux adapter */ -#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0) - force = 0; - if (pdata) - force = pdata->modes[0].adap_id; -#endif - if (detect_id == 0) { - muxc = i2c_mux_alloc(adap, &client->dev, 1, sizeof(*data), - I2C_MUX_ARBITRATOR, - pca9541_select_chan, pca9541_release_chan); - if (!muxc) - return -ENOMEM; - - data = i2c_mux_priv(muxc); - data->client = client; - - i2c_set_clientdata(client, muxc); -#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0) - ret = i2c_mux_add_adapter(muxc, 0, 0, 0); -#else - ret = i2c_mux_add_adapter(muxc, force, 0, 0); -#endif - if (ret) - return ret; - } else { - muxc = i2c_mux_alloc(adap, &client->dev, 1, sizeof(*data), - I2C_MUX_ARBITRATOR, - pca9641_select_chan, pca9641_release_chan); - if (!muxc) - return -ENOMEM; - - data = i2c_mux_priv(muxc); - data->client = client; - - i2c_set_clientdata(client, muxc); - - ret = i2c_mux_add_adapter(muxc, force, 0, 0); - if (ret) - return ret; - } - pca9641_recordflag(muxc->adapter[0]); - - dev_info(&client->dev, "registered master selector for I2C %s\n", - client->name); - - return 0; - -} - -static int pca9541_remove(struct i2c_client *client) -{ - struct i2c_mux_core *muxc = i2c_get_clientdata(client); - - i2c_mux_del_adapters(muxc); - return 0; -} - -static struct i2c_driver pca9641_driver = { - .driver = { - .name = "pca9641", - .of_match_table = of_match_ptr(pca9541_of_match), - }, - .probe = pca9541_probe, - .remove = pca9541_remove, - .id_table = pca9541_id, -}; - -module_i2c_driver(pca9641_driver); - -MODULE_AUTHOR("support support@ragile.com"); -MODULE_DESCRIPTION("PCA9541 I2C master selector driver"); -MODULE_LICENSE("GPL v2"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/intel_spi/Makefile b/platform/broadcom/sonic-platform-modules-ragile/common/modules/intel_spi/Makefile new file mode 100644 index 000000000000..269e95019cba --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/intel_spi/Makefile @@ -0,0 +1,21 @@ +PWD = $(shell pwd) + +EXTRA_CFLAGS:= -I$(M)/include +EXTRA_CFLAGS+= -Wall +#ifdef ENABLE_GCOV +#ifeq ($(ENABLE_GCOV), y) +#EXTRA_CFLAGS+= -fprofile-arcs -ftest-coverage -lgcov +#endif +#endif # ENABLE_GCOV + +obj-m := intel_spi.o +obj-m += intel_spi_platform.o + +all: + $(MAKE) -C $(KERNEL_SRC)/build M=$(PWD) modules + @if [ ! -d $(module_out_put_dir) ]; then mkdir -p $(module_out_put_dir) ;fi + cp -p $(PWD)/*.ko $(module_out_put_dir) +clean: + rm -f $(PWD)/*.o $(PWD)/*.ko $(PWD)/*.mod.c $(PWD)/.*.cmd + rm -f $(PWD)/Module.markers $(PWD)/Module.symvers $(PWD)/modules.order + rm -rf $(PWD)/.tmp_versions diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/intel_spi/include/intel_spi.h b/platform/broadcom/sonic-platform-modules-ragile/common/modules/intel_spi/include/intel_spi.h new file mode 100644 index 000000000000..d0a570b1f3b0 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/intel_spi/include/intel_spi.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Intel PCH/PCU SPI flash driver. + * + * Copyright (C) 2016, Intel Corporation + * Author: Mika Westerberg + */ + +#ifndef INTEL_SPI_H +#define INTEL_SPI_H + +#include +#include + +#define mem_clear(data, size) memset((data), 0, (size)) +struct intel_spi; +struct resource; + +struct intel_spi *intel_spi_probe(struct device *dev, + struct resource *mem, const struct intel_spi_boardinfo *info); +int intel_spi_remove(struct intel_spi *ispi); + +#endif /* INTEL_SPI_H */ diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/intel_spi/intel_spi.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/intel_spi/intel_spi.c new file mode 100644 index 000000000000..98de90f0c0b2 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/intel_spi/intel_spi.c @@ -0,0 +1,969 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Intel PCH/PCU SPI flash driver. + * + * Copyright (C) 2016, Intel Corporation + * Author: Mika Westerberg + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "intel_spi.h" + +/* Offsets are from @ispi->base */ +#define BFPREG 0x00 + +#define HSFSTS_CTL 0x04 +#define HSFSTS_CTL_FSMIE BIT(31) +#define HSFSTS_CTL_FDBC_SHIFT 24 +#define HSFSTS_CTL_FDBC_MASK (0x3f << HSFSTS_CTL_FDBC_SHIFT) + +#define HSFSTS_CTL_FCYCLE_SHIFT 17 +#define HSFSTS_CTL_FCYCLE_MASK (0x0f << HSFSTS_CTL_FCYCLE_SHIFT) +/* HW sequencer opcodes */ +#define HSFSTS_CTL_FCYCLE_READ (0x00 << HSFSTS_CTL_FCYCLE_SHIFT) +#define HSFSTS_CTL_FCYCLE_WRITE (0x02 << HSFSTS_CTL_FCYCLE_SHIFT) +#define HSFSTS_CTL_FCYCLE_ERASE (0x03 << HSFSTS_CTL_FCYCLE_SHIFT) +#define HSFSTS_CTL_FCYCLE_ERASE_64K (0x04 << HSFSTS_CTL_FCYCLE_SHIFT) +#define HSFSTS_CTL_FCYCLE_RDID (0x06 << HSFSTS_CTL_FCYCLE_SHIFT) +#define HSFSTS_CTL_FCYCLE_WRSR (0x07 << HSFSTS_CTL_FCYCLE_SHIFT) +#define HSFSTS_CTL_FCYCLE_RDSR (0x08 << HSFSTS_CTL_FCYCLE_SHIFT) + +#define HSFSTS_CTL_FGO BIT(16) +#define HSFSTS_CTL_FLOCKDN BIT(15) +#define HSFSTS_CTL_FDV BIT(14) +#define HSFSTS_CTL_SCIP BIT(5) +#define HSFSTS_CTL_AEL BIT(2) +#define HSFSTS_CTL_FCERR BIT(1) +#define HSFSTS_CTL_FDONE BIT(0) + +#define FADDR 0x08 +#define DLOCK 0x0c +#define FDATA(n) (0x10 + ((n) * 4)) + +#define FRACC 0x50 + +#define FREG(n) (0x54 + ((n) * 4)) +#define FREG_BASE_MASK 0x3fff +#define FREG_LIMIT_SHIFT 16 +#define FREG_LIMIT_MASK (0x03fff << FREG_LIMIT_SHIFT) + +/* Offset is from @ispi->pregs */ +#define PR(n) ((n) * 4) +#define PR_WPE BIT(31) +#define PR_LIMIT_SHIFT 16 +#define PR_LIMIT_MASK (0x3fff << PR_LIMIT_SHIFT) +#define PR_RPE BIT(15) +#define PR_BASE_MASK 0x3fff + +/* Offsets are from @ispi->sregs */ +#define SSFSTS_CTL 0x00 +#define SSFSTS_CTL_FSMIE BIT(23) +#define SSFSTS_CTL_DS BIT(22) +#define SSFSTS_CTL_DBC_SHIFT 16 +#define SSFSTS_CTL_SPOP BIT(11) +#define SSFSTS_CTL_ACS BIT(10) +#define SSFSTS_CTL_SCGO BIT(9) +#define SSFSTS_CTL_COP_SHIFT 12 +#define SSFSTS_CTL_FRS BIT(7) +#define SSFSTS_CTL_DOFRS BIT(6) +#define SSFSTS_CTL_AEL BIT(4) +#define SSFSTS_CTL_FCERR BIT(3) +#define SSFSTS_CTL_FDONE BIT(2) +#define SSFSTS_CTL_SCIP BIT(0) + +#define PREOP_OPTYPE 0x04 +#define OPMENU0 0x08 +#define OPMENU1 0x0c + +#define OPTYPE_READ_NO_ADDR 0 +#define OPTYPE_WRITE_NO_ADDR 1 +#define OPTYPE_READ_WITH_ADDR 2 +#define OPTYPE_WRITE_WITH_ADDR 3 + +/* CPU specifics */ +#define BYT_PR 0x74 +#define BYT_SSFSTS_CTL 0x90 +#define BYT_BCR 0xfc +#define BYT_BCR_WPD BIT(0) +#define BYT_FREG_NUM 5 +#define BYT_PR_NUM 5 + +#define LPT_PR 0x74 +#define LPT_SSFSTS_CTL 0x90 +#define LPT_FREG_NUM 5 +#define LPT_PR_NUM 5 + +#define BXT_PR 0x84 +#define BXT_SSFSTS_CTL 0xa0 +#define BXT_FREG_NUM 12 +#define BXT_PR_NUM 6 + +#define CNL_PR 0x84 +#define CNL_FREG_NUM 6 +#define CNL_PR_NUM 5 + +#define LVSCC 0xc4 +#define UVSCC 0xc8 +#define ERASE_OPCODE_SHIFT 8 +#define ERASE_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT) +#define ERASE_64K_OPCODE_SHIFT 16 +#define ERASE_64K_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT) + +#define INTEL_SPI_TIMEOUT 5000 /* ms */ +#define INTEL_SPI_FIFO_SZ 64 + +/** + * struct intel_spi - Driver private data + * @dev: Device pointer + * @info: Pointer to board specific info + * @nor: SPI NOR layer structure + * @base: Beginning of MMIO space + * @pregs: Start of protection registers + * @sregs: Start of software sequencer registers + * @nregions: Maximum number of regions + * @pr_num: Maximum number of protected range registers + * @writeable: Is the chip writeable + * @locked: Is SPI setting locked + * @swseq_reg: Use SW sequencer in register reads/writes + * @swseq_erase: Use SW sequencer in erase operation + * @erase_64k: 64k erase supported + * @atomic_preopcode: Holds preopcode when atomic sequence is requested + * @opcodes: Opcodes which are supported. This are programmed by BIOS + * before it locks down the controller. + */ +struct intel_spi { + struct device *dev; + const struct intel_spi_boardinfo *info; + struct spi_nor nor; + void __iomem *base; + void __iomem *pregs; + void __iomem *sregs; + size_t nregions; + size_t pr_num; + bool writeable; + bool locked; + bool swseq_reg; + bool swseq_erase; + bool erase_64k; + u8 atomic_preopcode; + u8 opcodes[8]; +}; + +static bool writeable; +module_param(writeable, bool, 0); +MODULE_PARM_DESC(writeable, "Enable write access to SPI flash chip (default=0)"); + +static void intel_spi_dump_regs(struct intel_spi *ispi) +{ + u32 value; + int i; + + dev_dbg(ispi->dev, "BFPREG=0x%08x\n", readl(ispi->base + BFPREG)); + + value = readl(ispi->base + HSFSTS_CTL); + dev_dbg(ispi->dev, "HSFSTS_CTL=0x%08x\n", value); + if (value & HSFSTS_CTL_FLOCKDN) + dev_dbg(ispi->dev, "-> Locked\n"); + + dev_dbg(ispi->dev, "FADDR=0x%08x\n", readl(ispi->base + FADDR)); + dev_dbg(ispi->dev, "DLOCK=0x%08x\n", readl(ispi->base + DLOCK)); + + for (i = 0; i < 16; i++) + dev_dbg(ispi->dev, "FDATA(%d)=0x%08x\n", + i, readl(ispi->base + FDATA(i))); + + dev_dbg(ispi->dev, "FRACC=0x%08x\n", readl(ispi->base + FRACC)); + + for (i = 0; i < ispi->nregions; i++) + dev_dbg(ispi->dev, "FREG(%d)=0x%08x\n", i, + readl(ispi->base + FREG(i))); + for (i = 0; i < ispi->pr_num; i++) + dev_dbg(ispi->dev, "PR(%d)=0x%08x\n", i, + readl(ispi->pregs + PR(i))); + + if (ispi->sregs) { + value = readl(ispi->sregs + SSFSTS_CTL); + dev_dbg(ispi->dev, "SSFSTS_CTL=0x%08x\n", value); + dev_dbg(ispi->dev, "PREOP_OPTYPE=0x%08x\n", + readl(ispi->sregs + PREOP_OPTYPE)); + dev_dbg(ispi->dev, "OPMENU0=0x%08x\n", + readl(ispi->sregs + OPMENU0)); + dev_dbg(ispi->dev, "OPMENU1=0x%08x\n", + readl(ispi->sregs + OPMENU1)); + } + + if (ispi->info->type == INTEL_SPI_BYT) + dev_dbg(ispi->dev, "BCR=0x%08x\n", readl(ispi->base + BYT_BCR)); + + dev_dbg(ispi->dev, "LVSCC=0x%08x\n", readl(ispi->base + LVSCC)); + dev_dbg(ispi->dev, "UVSCC=0x%08x\n", readl(ispi->base + UVSCC)); + + dev_dbg(ispi->dev, "Protected regions:\n"); + for (i = 0; i < ispi->pr_num; i++) { + u32 base, limit; + + value = readl(ispi->pregs + PR(i)); + if (!(value & (PR_WPE | PR_RPE))) + continue; + + limit = (value & PR_LIMIT_MASK) >> PR_LIMIT_SHIFT; + base = value & PR_BASE_MASK; + + dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x [%c%c]\n", + i, base << 12, (limit << 12) | 0xfff, + value & PR_WPE ? 'W' : '.', + value & PR_RPE ? 'R' : '.'); + } + + dev_dbg(ispi->dev, "Flash regions:\n"); + for (i = 0; i < ispi->nregions; i++) { + u32 region, base, limit; + + region = readl(ispi->base + FREG(i)); + base = region & FREG_BASE_MASK; + limit = (region & FREG_LIMIT_MASK) >> FREG_LIMIT_SHIFT; + + if (base >= limit || (i > 0 && limit == 0)) + dev_dbg(ispi->dev, " %02d disabled\n", i); + else + dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x\n", + i, base << 12, (limit << 12) | 0xfff); + } + + dev_dbg(ispi->dev, "Using %cW sequencer for register access\n", + ispi->swseq_reg ? 'S' : 'H'); + dev_dbg(ispi->dev, "Using %cW sequencer for erase operation\n", + ispi->swseq_erase ? 'S' : 'H'); +} + +/* Reads max INTEL_SPI_FIFO_SZ bytes from the device fifo */ +static int intel_spi_read_block(struct intel_spi *ispi, void *buf, size_t size) +{ + size_t bytes; + int i = 0; + + if (size > INTEL_SPI_FIFO_SZ) + return -EINVAL; + + while (size > 0) { + bytes = min_t(size_t, size, 4); + memcpy_fromio(buf, ispi->base + FDATA(i), bytes); + size -= bytes; + buf += bytes; + i++; + } + + return 0; +} + +/* Writes max INTEL_SPI_FIFO_SZ bytes to the device fifo */ +static int intel_spi_write_block(struct intel_spi *ispi, const void *buf, + size_t size) +{ + size_t bytes; + int i = 0; + + if (size > INTEL_SPI_FIFO_SZ) + return -EINVAL; + + while (size > 0) { + bytes = min_t(size_t, size, 4); + memcpy_toio(ispi->base + FDATA(i), buf, bytes); + size -= bytes; + buf += bytes; + i++; + } + + return 0; +} + +static int intel_spi_wait_hw_busy(struct intel_spi *ispi) +{ + u32 val; + + return readl_poll_timeout(ispi->base + HSFSTS_CTL, val, + !(val & HSFSTS_CTL_SCIP), 0, + INTEL_SPI_TIMEOUT * 1000); +} + +static int intel_spi_wait_sw_busy(struct intel_spi *ispi) +{ + u32 val; + + return readl_poll_timeout(ispi->sregs + SSFSTS_CTL, val, + !(val & SSFSTS_CTL_SCIP), 0, + INTEL_SPI_TIMEOUT * 1000); +} + +static int intel_spi_init(struct intel_spi *ispi) +{ + u32 opmenu0, opmenu1, lvscc, uvscc, val; + int i; + + switch (ispi->info->type) { + case INTEL_SPI_BYT: + ispi->sregs = ispi->base + BYT_SSFSTS_CTL; + ispi->pregs = ispi->base + BYT_PR; + ispi->nregions = BYT_FREG_NUM; + ispi->pr_num = BYT_PR_NUM; + ispi->swseq_reg = true; + + if (writeable) { + /* Disable write protection */ + val = readl(ispi->base + BYT_BCR); + if (!(val & BYT_BCR_WPD)) { + val |= BYT_BCR_WPD; + writel(val, ispi->base + BYT_BCR); + val = readl(ispi->base + BYT_BCR); + } + + ispi->writeable = !!(val & BYT_BCR_WPD); + } + + break; + + case INTEL_SPI_LPT: + ispi->sregs = ispi->base + LPT_SSFSTS_CTL; + ispi->pregs = ispi->base + LPT_PR; + ispi->nregions = LPT_FREG_NUM; + ispi->pr_num = LPT_PR_NUM; + ispi->swseq_reg = true; + break; + + case INTEL_SPI_BXT: + ispi->sregs = ispi->base + BXT_SSFSTS_CTL; + ispi->pregs = ispi->base + BXT_PR; + ispi->nregions = BXT_FREG_NUM; + ispi->pr_num = BXT_PR_NUM; + ispi->erase_64k = true; + break; + + case INTEL_SPI_CNL: + ispi->sregs = NULL; + ispi->pregs = ispi->base + CNL_PR; + ispi->nregions = CNL_FREG_NUM; + ispi->pr_num = CNL_PR_NUM; + break; + + default: + return -EINVAL; + } + + /* Disable #SMI generation from HW sequencer */ + val = readl(ispi->base + HSFSTS_CTL); + val &= ~HSFSTS_CTL_FSMIE; + writel(val, ispi->base + HSFSTS_CTL); + + /* + * Determine whether erase operation should use HW or SW sequencer. + * + * The HW sequencer has a predefined list of opcodes, with only the + * erase opcode being programmable in LVSCC and UVSCC registers. + * If these registers don't contain a valid erase opcode, erase + * cannot be done using HW sequencer. + */ + lvscc = readl(ispi->base + LVSCC); + uvscc = readl(ispi->base + UVSCC); + if (!(lvscc & ERASE_OPCODE_MASK) || !(uvscc & ERASE_OPCODE_MASK)) + ispi->swseq_erase = true; + /* SPI controller on Intel BXT supports 64K erase opcode */ + if (ispi->info->type == INTEL_SPI_BXT && !ispi->swseq_erase) + if (!(lvscc & ERASE_64K_OPCODE_MASK) || + !(uvscc & ERASE_64K_OPCODE_MASK)) + ispi->erase_64k = false; + + if (ispi->sregs == NULL && (ispi->swseq_reg || ispi->swseq_erase)) { + dev_err(ispi->dev, "software sequencer not supported, but required\n"); + return -EINVAL; + } + + /* + * Some controllers can only do basic operations using hardware + * sequencer. All other operations are supposed to be carried out + * using software sequencer. + */ + if (ispi->swseq_reg) { + /* Disable #SMI generation from SW sequencer */ + val = readl(ispi->sregs + SSFSTS_CTL); + val &= ~SSFSTS_CTL_FSMIE; + writel(val, ispi->sregs + SSFSTS_CTL); + } + + /* Check controller's lock status */ + val = readl(ispi->base + HSFSTS_CTL); + ispi->locked = !!(val & HSFSTS_CTL_FLOCKDN); + + if (ispi->locked && ispi->sregs) { + /* + * BIOS programs allowed opcodes and then locks down the + * register. So read back what opcodes it decided to support. + * That's the set we are going to support as well. + */ + opmenu0 = readl(ispi->sregs + OPMENU0); + opmenu1 = readl(ispi->sregs + OPMENU1); + + if (opmenu0 && opmenu1) { + for (i = 0; i < ARRAY_SIZE(ispi->opcodes) / 2; i++) { + ispi->opcodes[i] = opmenu0 >> i * 8; + ispi->opcodes[i + 4] = opmenu1 >> i * 8; + } + } + } + + intel_spi_dump_regs(ispi); + + return 0; +} + +static int intel_spi_opcode_index(struct intel_spi *ispi, u8 opcode, int optype) +{ + int i; + int preop; + + if (ispi->locked) { + for (i = 0; i < ARRAY_SIZE(ispi->opcodes); i++) + if (ispi->opcodes[i] == opcode) + return i; + + return -EINVAL; + } + + /* The lock is off, so just use index 0 */ + writel(opcode, ispi->sregs + OPMENU0); + preop = readw(ispi->sregs + PREOP_OPTYPE); + writel(optype << 16 | preop, ispi->sregs + PREOP_OPTYPE); + + return 0; +} + +static int intel_spi_hw_cycle(struct intel_spi *ispi, u8 opcode, size_t len) +{ + u32 val, status; + int ret; + + val = readl(ispi->base + HSFSTS_CTL); + val &= ~(HSFSTS_CTL_FCYCLE_MASK | HSFSTS_CTL_FDBC_MASK); + + switch (opcode) { + case SPINOR_OP_RDID: + val |= HSFSTS_CTL_FCYCLE_RDID; + break; + case SPINOR_OP_WRSR: + val |= HSFSTS_CTL_FCYCLE_WRSR; + break; + case SPINOR_OP_RDSR: + val |= HSFSTS_CTL_FCYCLE_RDSR; + break; + default: + return -EINVAL; + } + + if (len > INTEL_SPI_FIFO_SZ) + return -EINVAL; + + val |= (len - 1) << HSFSTS_CTL_FDBC_SHIFT; + val |= HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE; + val |= HSFSTS_CTL_FGO; + writel(val, ispi->base + HSFSTS_CTL); + + ret = intel_spi_wait_hw_busy(ispi); + if (ret) + return ret; + + status = readl(ispi->base + HSFSTS_CTL); + if (status & HSFSTS_CTL_FCERR) + return -EIO; + else if (status & HSFSTS_CTL_AEL) + return -EACCES; + + return 0; +} + +static int intel_spi_sw_cycle(struct intel_spi *ispi, u8 opcode, size_t len, + int optype) +{ + u32 val = 0, status; + u8 atomic_preopcode; + int ret; + + ret = intel_spi_opcode_index(ispi, opcode, optype); + if (ret < 0) + return ret; + + if (len > INTEL_SPI_FIFO_SZ) + return -EINVAL; + + /* + * Always clear it after each SW sequencer operation regardless + * of whether it is successful or not. + */ + atomic_preopcode = ispi->atomic_preopcode; + ispi->atomic_preopcode = 0; + + /* Only mark 'Data Cycle' bit when there is data to be transferred */ + if (len > 0) + val = ((len - 1) << SSFSTS_CTL_DBC_SHIFT) | SSFSTS_CTL_DS; + val |= ret << SSFSTS_CTL_COP_SHIFT; + val |= SSFSTS_CTL_FCERR | SSFSTS_CTL_FDONE; + val |= SSFSTS_CTL_SCGO; + if (atomic_preopcode) { + u16 preop; + + switch (optype) { + case OPTYPE_WRITE_NO_ADDR: + case OPTYPE_WRITE_WITH_ADDR: + /* Pick matching preopcode for the atomic sequence */ + preop = readw(ispi->sregs + PREOP_OPTYPE); + if ((preop & 0xff) == atomic_preopcode) + ; /* Do nothing */ + else if ((preop >> 8) == atomic_preopcode) + val |= SSFSTS_CTL_SPOP; + else + return -EINVAL; + + /* Enable atomic sequence */ + val |= SSFSTS_CTL_ACS; + break; + + default: + return -EINVAL; + } + + } + writel(val, ispi->sregs + SSFSTS_CTL); + + ret = intel_spi_wait_sw_busy(ispi); + if (ret) + return ret; + + status = readl(ispi->sregs + SSFSTS_CTL); + if (status & SSFSTS_CTL_FCERR) + return -EIO; + else if (status & SSFSTS_CTL_AEL) + return -EACCES; + + return 0; +} + +static int intel_spi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, + size_t len) +{ + struct intel_spi *ispi = nor->priv; + int ret; + + /* Address of the first chip */ + writel(0, ispi->base + FADDR); + + if (ispi->swseq_reg) + ret = intel_spi_sw_cycle(ispi, opcode, len, + OPTYPE_READ_NO_ADDR); + else + ret = intel_spi_hw_cycle(ispi, opcode, len); + + if (ret) + return ret; + + return intel_spi_read_block(ispi, buf, len); +} + +static int intel_spi_write_reg(struct spi_nor *nor, u8 opcode, const u8 *buf, + size_t len) +{ + struct intel_spi *ispi = nor->priv; + int ret; + + /* + * This is handled with atomic operation and preop code in Intel + * controller so we only verify that it is available. If the + * controller is not locked, program the opcode to the PREOP + * register for later use. + * + * When hardware sequencer is used there is no need to program + * any opcodes (it handles them automatically as part of a command). + */ + if (opcode == SPINOR_OP_WREN) { + u16 preop; + + if (!ispi->swseq_reg) + return 0; + + preop = readw(ispi->sregs + PREOP_OPTYPE); + if ((preop & 0xff) != opcode && (preop >> 8) != opcode) { + if (ispi->locked) + return -EINVAL; + writel(opcode, ispi->sregs + PREOP_OPTYPE); + } + + /* + * This enables atomic sequence on next SW sycle. Will + * be cleared after next operation. + */ + ispi->atomic_preopcode = opcode; + return 0; + } + + /* + * We hope that HW sequencer will do the right thing automatically and + * with the SW sequencer we cannot use preopcode anyway, so just ignore + * the Write Disable operation and pretend it was completed + * successfully. + */ + if (opcode == SPINOR_OP_WRDI) + return 0; + + writel(0, ispi->base + FADDR); + + /* Write the value beforehand */ + ret = intel_spi_write_block(ispi, buf, len); + if (ret) + return ret; + + if (ispi->swseq_reg) + return intel_spi_sw_cycle(ispi, opcode, len, + OPTYPE_WRITE_NO_ADDR); + return intel_spi_hw_cycle(ispi, opcode, len); +} + +static ssize_t intel_spi_read(struct spi_nor *nor, loff_t from, size_t len, + u_char *read_buf) +{ + struct intel_spi *ispi = nor->priv; + size_t block_size, retlen = 0; + u32 val, status; + ssize_t ret; + + /* + * Atomic sequence is not expected with HW sequencer reads. Make + * sure it is cleared regardless. + */ + if (WARN_ON_ONCE(ispi->atomic_preopcode)) + ispi->atomic_preopcode = 0; + + switch (nor->read_opcode) { + case SPINOR_OP_READ: + case SPINOR_OP_READ_FAST: + case SPINOR_OP_READ_4B: + case SPINOR_OP_READ_FAST_4B: + break; + default: + return -EINVAL; + } + + while (len > 0) { + block_size = min_t(size_t, len, INTEL_SPI_FIFO_SZ); + + /* Read cannot cross 4K boundary */ + block_size = min_t(loff_t, from + block_size, + round_up(from + 1, SZ_4K)) - from; + + writel(from, ispi->base + FADDR); + + val = readl(ispi->base + HSFSTS_CTL); + val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK); + val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE; + val |= (block_size - 1) << HSFSTS_CTL_FDBC_SHIFT; + val |= HSFSTS_CTL_FCYCLE_READ; + val |= HSFSTS_CTL_FGO; + writel(val, ispi->base + HSFSTS_CTL); + + ret = intel_spi_wait_hw_busy(ispi); + if (ret) + return ret; + + status = readl(ispi->base + HSFSTS_CTL); + if (status & HSFSTS_CTL_FCERR) + ret = -EIO; + else if (status & HSFSTS_CTL_AEL) + ret = -EACCES; + + if (ret < 0) { + dev_err(ispi->dev, "read error: %llx: %#x\n", from, + status); + return ret; + } + + ret = intel_spi_read_block(ispi, read_buf, block_size); + if (ret) + return ret; + + len -= block_size; + from += block_size; + retlen += block_size; + read_buf += block_size; + } + + return retlen; +} + +static ssize_t intel_spi_write(struct spi_nor *nor, loff_t to, size_t len, + const u_char *write_buf) +{ + struct intel_spi *ispi = nor->priv; + size_t block_size, retlen = 0; + u32 val, status; + ssize_t ret; + + /* Not needed with HW sequencer write, make sure it is cleared */ + ispi->atomic_preopcode = 0; + + while (len > 0) { + block_size = min_t(size_t, len, INTEL_SPI_FIFO_SZ); + + /* Write cannot cross 4K boundary */ + block_size = min_t(loff_t, to + block_size, + round_up(to + 1, SZ_4K)) - to; + + writel(to, ispi->base + FADDR); + + val = readl(ispi->base + HSFSTS_CTL); + val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK); + val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE; + val |= (block_size - 1) << HSFSTS_CTL_FDBC_SHIFT; + val |= HSFSTS_CTL_FCYCLE_WRITE; + + ret = intel_spi_write_block(ispi, write_buf, block_size); + if (ret) { + dev_err(ispi->dev, "failed to write block\n"); + return ret; + } + + /* Start the write now */ + val |= HSFSTS_CTL_FGO; + writel(val, ispi->base + HSFSTS_CTL); + + ret = intel_spi_wait_hw_busy(ispi); + if (ret) { + dev_err(ispi->dev, "timeout\n"); + return ret; + } + + status = readl(ispi->base + HSFSTS_CTL); + if (status & HSFSTS_CTL_FCERR) + ret = -EIO; + else if (status & HSFSTS_CTL_AEL) + ret = -EACCES; + + if (ret < 0) { + dev_err(ispi->dev, "write error: %llx: %#x\n", to, + status); + return ret; + } + + len -= block_size; + to += block_size; + retlen += block_size; + write_buf += block_size; + } + + return retlen; +} + +static int intel_spi_erase(struct spi_nor *nor, loff_t offs) +{ + size_t erase_size, len = nor->mtd.erasesize; + struct intel_spi *ispi = nor->priv; + u32 val, status, cmd; + int ret; + + /* If the hardware can do 64k erase use that when possible */ + if (len >= SZ_64K && ispi->erase_64k) { + cmd = HSFSTS_CTL_FCYCLE_ERASE_64K; + erase_size = SZ_64K; + } else { + cmd = HSFSTS_CTL_FCYCLE_ERASE; + erase_size = SZ_4K; + } + + if (ispi->swseq_erase) { + while (len > 0) { + writel(offs, ispi->base + FADDR); + + ret = intel_spi_sw_cycle(ispi, nor->erase_opcode, + 0, OPTYPE_WRITE_WITH_ADDR); + if (ret) + return ret; + + offs += erase_size; + len -= erase_size; + } + + return 0; + } + + /* Not needed with HW sequencer erase, make sure it is cleared */ + ispi->atomic_preopcode = 0; + + while (len > 0) { + writel(offs, ispi->base + FADDR); + + val = readl(ispi->base + HSFSTS_CTL); + val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK); + val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE; + val |= cmd; + val |= HSFSTS_CTL_FGO; + writel(val, ispi->base + HSFSTS_CTL); + + ret = intel_spi_wait_hw_busy(ispi); + if (ret) + return ret; + + status = readl(ispi->base + HSFSTS_CTL); + if (status & HSFSTS_CTL_FCERR) + return -EIO; + else if (status & HSFSTS_CTL_AEL) + return -EACCES; + + offs += erase_size; + len -= erase_size; + } + + return 0; +} + +static bool intel_spi_is_protected(const struct intel_spi *ispi, + unsigned int base, unsigned int limit) +{ + int i; + + for (i = 0; i < ispi->pr_num; i++) { + u32 pr_base, pr_limit, pr_value; + + pr_value = readl(ispi->pregs + PR(i)); + if (!(pr_value & (PR_WPE | PR_RPE))) + continue; + + pr_limit = (pr_value & PR_LIMIT_MASK) >> PR_LIMIT_SHIFT; + pr_base = pr_value & PR_BASE_MASK; + + if (pr_base >= base && pr_limit <= limit) + return true; + } + + return false; +} + +/* + * There will be a single partition holding all enabled flash regions. We + * call this "BIOS". + */ +static void intel_spi_fill_partition(struct intel_spi *ispi, + struct mtd_partition *part) +{ + u64 end; + int i; + + mem_clear(part, sizeof(*part)); + + /* Start from the mandatory descriptor region */ + part->size = 4096; + part->name = "BIOS"; + + /* + * Now try to find where this partition ends based on the flash + * region registers. + */ + for (i = 1; i < ispi->nregions; i++) { + u32 region, base, limit; + + region = readl(ispi->base + FREG(i)); + base = region & FREG_BASE_MASK; + limit = (region & FREG_LIMIT_MASK) >> FREG_LIMIT_SHIFT; + + if (base >= limit || limit == 0) + continue; + + /* + * If any of the regions have protection bits set, make the + * whole partition read-only to be on the safe side. + */ + if (intel_spi_is_protected(ispi, base, limit)) + ispi->writeable = false; + + end = (limit << 12) + 4096; + if (end > part->size) + part->size = end; + } +} + +static const struct spi_nor_controller_ops intel_spi_controller_ops = { + .read_reg = intel_spi_read_reg, + .write_reg = intel_spi_write_reg, + .read = intel_spi_read, + .write = intel_spi_write, + .erase = intel_spi_erase, +}; + +struct intel_spi *intel_spi_probe(struct device *dev, + struct resource *mem, const struct intel_spi_boardinfo *info) +{ + const struct spi_nor_hwcaps hwcaps = { + .mask = SNOR_HWCAPS_READ | + SNOR_HWCAPS_READ_FAST | + SNOR_HWCAPS_PP, + }; + struct mtd_partition part; + struct intel_spi *ispi; + int ret; + + if (!info || !mem) + return ERR_PTR(-EINVAL); + + ispi = devm_kzalloc(dev, sizeof(*ispi), GFP_KERNEL); + if (!ispi) + return ERR_PTR(-ENOMEM); + + ispi->base = devm_ioremap_resource(dev, mem); + if (IS_ERR(ispi->base)) + return ERR_CAST(ispi->base); + + ispi->dev = dev; + ispi->info = info; + ispi->writeable = info->writeable; + + ret = intel_spi_init(ispi); + if (ret) + return ERR_PTR(ret); + + ispi->nor.dev = ispi->dev; + ispi->nor.priv = ispi; + ispi->nor.controller_ops = &intel_spi_controller_ops; + + ret = spi_nor_scan(&ispi->nor, NULL, &hwcaps); + if (ret) { + dev_info(dev, "failed to locate the chip\n"); + return ERR_PTR(ret); + } + + intel_spi_fill_partition(ispi, &part); + + /* Prevent writes if not explicitly enabled */ + if (!ispi->writeable || !writeable) + ispi->nor.mtd.flags &= ~MTD_WRITEABLE; + + ret = mtd_device_register(&ispi->nor.mtd, &part, 1); + if (ret) + return ERR_PTR(ret); + + return ispi; +} +EXPORT_SYMBOL_GPL(intel_spi_probe); + +int intel_spi_remove(struct intel_spi *ispi) +{ + return mtd_device_unregister(&ispi->nor.mtd); +} +EXPORT_SYMBOL_GPL(intel_spi_remove); + +MODULE_DESCRIPTION("Intel PCH/PCU SPI flash core driver"); +MODULE_AUTHOR("support"); +MODULE_LICENSE("GPL v2"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/intel_spi/intel_spi_platform.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/intel_spi/intel_spi_platform.c new file mode 100644 index 000000000000..b9f294860ce4 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/intel_spi/intel_spi_platform.c @@ -0,0 +1,167 @@ +/* + * Intel PCH/PCU SPI flash platform driver. + * + * Copyright (C) 2016, Intel Corporation + * Author: Mika Westerberg + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#include "intel_spi.h" + +#define PCI_VENDOR_ID_D1527_LPC (0x8c54) + +#define BIOS_CNTL (0xdc) +#define BIOS_CNTL_SRC_SHIFT 2 +#define BIOS_CNTL_WN BIT(0) +#define BIOS_CNTL_BLE BIT(1) +#define BIOS_CNTL_SMM_BMP BIT(5) + +#define RCBABASE 0xf0 + +int intel_spi_platform_debug = 0; +module_param(intel_spi_platform_debug, int, S_IRUGO | S_IWUSR); +int intel_spi_platform_error = 0; +module_param(intel_spi_platform_error, int, S_IRUGO | S_IWUSR); + +static bool writeable; +module_param(writeable, bool, 0); +MODULE_PARM_DESC(writeable, "Enable write access to BIOS (default=0)"); + +#define INTEL_SPI_PLATFORM_VERBOSE(fmt, args...) do { \ + if (intel_spi_platform_debug) { \ + printk(KERN_INFO "[INTEL_SPI_PLATFORM][VER][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ + } while (0) + +#define INTEL_SPI_PLATFORM_ERROR(fmt, args...) do { \ + if (intel_spi_platform_error) { \ + printk(KERN_ERR "[INTEL_SPI_PLATFORM][ERR][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ + } while (0) + +static void intel_spi_enable_bios_write(struct pci_dev *pci_dev, struct intel_spi_boardinfo *info) +{ + u8 bios_cntl, value, want, new; + + if (writeable) { + pci_read_config_byte(pci_dev, BIOS_CNTL, &bios_cntl); + want = bios_cntl; + value = (bios_cntl >> BIOS_CNTL_SRC_SHIFT) & 0x3 ; + if (value == 0x3) { + INTEL_SPI_PLATFORM_VERBOSE("invalid prefetching/caching settings, "); + } else { + INTEL_SPI_PLATFORM_VERBOSE("prefetching %sabled, caching %sabled, ", + (value & 0x2) ? "en" : "dis", + (value & 0x1) ? "dis" : "en"); + } + + /* writeable regardless */ + want &= ~BIOS_CNTL_SMM_BMP; + /* write enable */ + want |= BIOS_CNTL_WN; + /* BIOS lock disabled */ + want &= ~BIOS_CNTL_BLE; + INTEL_SPI_PLATFORM_VERBOSE("bios cntl is:0x%x, want is:0x%x\n", bios_cntl, want); + pci_write_config_byte(pci_dev, BIOS_CNTL, want); + pci_read_config_byte(pci_dev, BIOS_CNTL, &new); + INTEL_SPI_PLATFORM_VERBOSE("\nBIOS_CNTL = 0x%02x: ", new); + INTEL_SPI_PLATFORM_VERBOSE("BIOS Lock Enable: %sabled, ", (new & BIOS_CNTL_BLE) ? "en" : "dis"); + INTEL_SPI_PLATFORM_VERBOSE("BIOS Write Enable: %sabled\n", (new & BIOS_CNTL_WN) ? "en" : "dis"); + + if (new & BIOS_CNTL_SMM_BMP) { + INTEL_SPI_PLATFORM_VERBOSE("BIOS region SMM protection is enabled!\n"); + } + + if (new != want) { + INTEL_SPI_PLATFORM_VERBOSE("Warning: Setting Bios Control at 0x%x from 0x%02x to 0x%02x failed.\n" + "New value is 0x%02x.\n", BIOS_CNTL, value, want, new); + } else { + info->writeable = !!(new & BIOS_CNTL_WN); + } + INTEL_SPI_PLATFORM_VERBOSE("Bios Control is 0x%x\n", new); + } else { + INTEL_SPI_PLATFORM_VERBOSE("Bios don't write\n"); + } + + return ; +} + +static int intel_spi_platform_probe(struct platform_device *pdev) +{ + struct intel_spi_boardinfo *info; + struct intel_spi *ispi; + struct resource *mem; + struct pci_dev *pci_dev = NULL; + u32 rcba; + + info = dev_get_platdata(&pdev->dev); + if (!info) + return -EINVAL; + + pci_dev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_VENDOR_ID_D1527_LPC, pci_dev); + if (!pci_dev) { + INTEL_SPI_PLATFORM_ERROR("pci_get_device(0x8086, 0x8c54) failed!\n"); + return -1; + } + + switch (info->type) { + case INTEL_SPI_LPT: + pci_read_config_dword(pci_dev, RCBABASE, &rcba); + if (rcba & 1) { + intel_spi_enable_bios_write(pci_dev, info); + } + break; + default: + INTEL_SPI_PLATFORM_ERROR("info type[%d] not need set writeable.\n",info->type); + break; + } + INTEL_SPI_PLATFORM_VERBOSE("intel spi boardinfo writeable is %sabled\n", + info->writeable ? "en" : "dis"); + + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + ispi = intel_spi_probe(&pdev->dev, mem, info); + if (IS_ERR(ispi)) + return PTR_ERR(ispi); + + platform_set_drvdata(pdev, ispi); + return 0; +} + +static int intel_spi_platform_remove(struct platform_device *pdev) +{ + struct intel_spi *ispi = platform_get_drvdata(pdev); + + return intel_spi_remove(ispi); +} + +static struct of_device_id intel_spi_match[] = { + { + .compatible = "spi-c224", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, intel_spi_match); + +static struct platform_driver intel_spi_platform_driver = { + .probe = intel_spi_platform_probe, + .remove = intel_spi_platform_remove, + .driver = { + .name = "intel-spi", + .of_match_table = intel_spi_match, + }, +}; + +module_platform_driver(intel_spi_platform_driver); + +MODULE_DESCRIPTION("Intel PCH/PCU SPI flash platform driver"); +MODULE_AUTHOR("support"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:intel-spi"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/Makefile b/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/Makefile new file mode 100644 index 000000000000..4226f2734275 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/Makefile @@ -0,0 +1,34 @@ +PWD = $(shell pwd) + +EXTRA_CFLAGS:= -I$(M)/include +EXTRA_CFLAGS+= -Wall +#ifdef ENABLE_GCOV +#ifeq ($(ENABLE_GCOV), y) +#EXTRA_CFLAGS+= -fprofile-arcs -ftest-coverage -lgcov +#endif +#endif # ENABLE_GCOV + +obj-m := wb_lm75.o +obj-m += wb_tmp401.o +obj-m += wb_i2c_mux_pca9641.o +obj-m += wb_i2c_mux_pca954x.o +obj-m += wb_i2c_i801.o +obj-m += wb_i2c_algo_bit.o +obj-m += wb_i2c_gpio.o +obj-m += wb_i2c_gpio_device.o +obj-m += wb_at24.o +obj-m += wb_pmbus_core.o +obj-m += wb_csu550.o +obj-m += wb_ina3221.o +obj-m += wb_isl68137.o +obj-m += wb_tps53622.o +obj-m += wb_ucd9000.o + +all: + $(MAKE) -C $(KERNEL_SRC)/build M=$(PWD) modules + @if [ ! -d $(module_out_put_dir) ]; then mkdir -p $(module_out_put_dir) ;fi + cp -p $(PWD)/*.ko $(module_out_put_dir) +clean: + rm -f $(PWD)/*.o $(PWD)/*.ko $(PWD)/*.mod.c $(PWD)/.*.cmd $(PWD)/*.mod + rm -f $(PWD)/Module.markers $(PWD)/Module.symvers $(PWD)/modules.order + rm -rf $(PWD)/.tmp_versions diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_at24.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_at24.c new file mode 100644 index 000000000000..1075e6ef18de --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_at24.c @@ -0,0 +1,861 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * at24.c - handle most I2C EEPROMs + * + * Copyright (C) 2005-2007 David Brownell + * Copyright (C) 2008 Wolfram Sang, Pengutronix + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Address pointer is 16 bit. */ +#define AT24_FLAG_ADDR16 BIT(7) +/* sysfs-entry will be read-only. */ +#define AT24_FLAG_READONLY BIT(6) +/* sysfs-entry will be world-readable. */ +#define AT24_FLAG_IRUGO BIT(5) +/* Take always 8 addresses (24c00). */ +#define AT24_FLAG_TAKE8ADDR BIT(4) +/* Factory-programmed serial number. */ +#define AT24_FLAG_SERIAL BIT(3) +/* Factory-programmed mac address. */ +#define AT24_FLAG_MAC BIT(2) +/* Does not auto-rollover reads to the next slave address. */ +#define AT24_FLAG_NO_RDROL BIT(1) + +/* + * I2C EEPROMs from most vendors are inexpensive and mostly interchangeable. + * Differences between different vendor product lines (like Atmel AT24C or + * MicroChip 24LC, etc) won't much matter for typical read/write access. + * There are also I2C RAM chips, likewise interchangeable. One example + * would be the PCF8570, which acts like a 24c02 EEPROM (256 bytes). + * + * However, misconfiguration can lose data. "Set 16-bit memory address" + * to a part with 8-bit addressing will overwrite data. Writing with too + * big a page size also loses data. And it's not safe to assume that the + * conventional addresses 0x50..0x57 only hold eeproms; a PCF8563 RTC + * uses 0x51, for just one example. + * + * Accordingly, explicit board-specific configuration data should be used + * in almost all cases. (One partial exception is an SMBus used to access + * "SPD" data for DRAM sticks. Those only use 24c02 EEPROMs.) + * + * So this driver uses "new style" I2C driver binding, expecting to be + * told what devices exist. That may be in arch/X/mach-Y/board-Z.c or + * similar kernel-resident tables; or, configuration data coming from + * a bootloader. + * + * Other than binding model, current differences from "eeprom" driver are + * that this one handles write access and isn't restricted to 24c02 devices. + * It also handles larger devices (32 kbit and up) with two-byte addresses, + * which won't work on pure SMBus systems. + */ + +struct at24_client { + struct i2c_client *client; + struct regmap *regmap; +}; + +struct at24_data { + /* + * Lock protects against activities from other Linux tasks, + * but not from changes by other I2C masters. + */ + struct mutex lock; + + unsigned int write_max; + unsigned int num_addresses; + unsigned int offset_adj; + + u32 byte_len; + u16 page_size; + u8 flags; + + struct nvmem_device *nvmem; + struct regulator *vcc_reg; + void (*read_post)(unsigned int off, char *buf, size_t count); + + /* + * Some chips tie up multiple I2C addresses; dummy devices reserve + * them for us, and we'll use them with SMBus calls. + */ + struct at24_client client[]; +}; + +/* + * This parameter is to help this driver avoid blocking other drivers out + * of I2C for potentially troublesome amounts of time. With a 100 kHz I2C + * clock, one 256 byte read takes about 1/43 second which is excessive; + * but the 1/170 second it takes at 400 kHz may be quite reasonable; and + * at 1 MHz (Fm+) a 1/430 second delay could easily be invisible. + * + * This value is forced to be a power of two so that writes align on pages. + */ +static unsigned int at24_io_limit = 128; +module_param_named(io_limit, at24_io_limit, uint, 0); +MODULE_PARM_DESC(at24_io_limit, "Maximum bytes per I/O (default 128)"); + +/* + * Specs often allow 5 msec for a page write, sometimes 20 msec; + * it's important to recover from write timeouts. + */ +static unsigned int at24_write_timeout = 25; +module_param_named(write_timeout, at24_write_timeout, uint, 0); +MODULE_PARM_DESC(at24_write_timeout, "Time (in ms) to try writes (default 25)"); + +struct at24_chip_data { + u32 byte_len; + u8 flags; + void (*read_post)(unsigned int off, char *buf, size_t count); +}; + +#define AT24_CHIP_DATA(_name, _len, _flags) \ + static const struct at24_chip_data _name = { \ + .byte_len = _len, .flags = _flags, \ + } + +#define AT24_CHIP_DATA_CB(_name, _len, _flags, _read_post) \ + static const struct at24_chip_data _name = { \ + .byte_len = _len, .flags = _flags, \ + .read_post = _read_post, \ + } + +static void at24_read_post_vaio(unsigned int off, char *buf, size_t count) +{ + int i; + + if (capable(CAP_SYS_ADMIN)) + return; + + /* + * Hide VAIO private settings to regular users: + * - BIOS passwords: bytes 0x00 to 0x0f + * - UUID: bytes 0x10 to 0x1f + * - Serial number: 0xc0 to 0xdf + */ + for (i = 0; i < count; i++) { + if ((off + i <= 0x1f) || + (off + i >= 0xc0 && off + i <= 0xdf)) + buf[i] = 0; + } +} + +/* needs 8 addresses as A0-A2 are ignored */ +AT24_CHIP_DATA(at24_data_24c00, 128 / 8, AT24_FLAG_TAKE8ADDR); +/* old variants can't be handled with this generic entry! */ +AT24_CHIP_DATA(at24_data_24c01, 1024 / 8, 0); +AT24_CHIP_DATA(at24_data_24cs01, 16, + AT24_FLAG_SERIAL | AT24_FLAG_READONLY); +AT24_CHIP_DATA(at24_data_24c02, 2048 / 8, AT24_FLAG_IRUGO); +AT24_CHIP_DATA(at24_data_24cs02, 16, + AT24_FLAG_SERIAL | AT24_FLAG_READONLY); +AT24_CHIP_DATA(at24_data_24mac402, 48 / 8, + AT24_FLAG_MAC | AT24_FLAG_READONLY); +AT24_CHIP_DATA(at24_data_24mac602, 64 / 8, + AT24_FLAG_MAC | AT24_FLAG_READONLY); +/* spd is a 24c02 in memory DIMMs */ +AT24_CHIP_DATA(at24_data_spd, 2048 / 8, + AT24_FLAG_READONLY | AT24_FLAG_IRUGO); +/* 24c02_vaio is a 24c02 on some Sony laptops */ +AT24_CHIP_DATA_CB(at24_data_24c02_vaio, 2048 / 8, + AT24_FLAG_READONLY | AT24_FLAG_IRUGO, + at24_read_post_vaio); +AT24_CHIP_DATA(at24_data_24c04, 4096 / 8, 0); +AT24_CHIP_DATA(at24_data_24cs04, 16, + AT24_FLAG_SERIAL | AT24_FLAG_READONLY); +/* 24rf08 quirk is handled at i2c-core */ +AT24_CHIP_DATA(at24_data_24c08, 8192 / 8, 0); +AT24_CHIP_DATA(at24_data_24cs08, 16, + AT24_FLAG_SERIAL | AT24_FLAG_READONLY); +AT24_CHIP_DATA(at24_data_24c16, 16384 / 8, 0); +AT24_CHIP_DATA(at24_data_24cs16, 16, + AT24_FLAG_SERIAL | AT24_FLAG_READONLY); +AT24_CHIP_DATA(at24_data_24c32, 32768 / 8, AT24_FLAG_ADDR16); +AT24_CHIP_DATA(at24_data_24cs32, 16, + AT24_FLAG_ADDR16 | AT24_FLAG_SERIAL | AT24_FLAG_READONLY); +AT24_CHIP_DATA(at24_data_24c64, 65536 / 8, AT24_FLAG_ADDR16 | AT24_FLAG_IRUGO); +AT24_CHIP_DATA(at24_data_24cs64, 16, + AT24_FLAG_ADDR16 | AT24_FLAG_SERIAL | AT24_FLAG_READONLY); +AT24_CHIP_DATA(at24_data_24c128, 131072 / 8, AT24_FLAG_ADDR16); +AT24_CHIP_DATA(at24_data_24c256, 262144 / 8, AT24_FLAG_ADDR16); +AT24_CHIP_DATA(at24_data_24c512, 524288 / 8, AT24_FLAG_ADDR16); +AT24_CHIP_DATA(at24_data_24c1024, 1048576 / 8, AT24_FLAG_ADDR16); +AT24_CHIP_DATA(at24_data_24c2048, 2097152 / 8, AT24_FLAG_ADDR16); +/* identical to 24c08 ? */ +AT24_CHIP_DATA(at24_data_INT3499, 8192 / 8, 0); + +static const struct i2c_device_id at24_ids[] = { + { "wb_24c00", (kernel_ulong_t)&at24_data_24c00 }, + { "wb_24c01", (kernel_ulong_t)&at24_data_24c01 }, + { "wb_24cs01", (kernel_ulong_t)&at24_data_24cs01 }, + { "wb_24c02", (kernel_ulong_t)&at24_data_24c02 }, + { "wb_24cs02", (kernel_ulong_t)&at24_data_24cs02 }, + { "wb_24mac402", (kernel_ulong_t)&at24_data_24mac402 }, + { "wb_24mac602", (kernel_ulong_t)&at24_data_24mac602 }, + { "wb_spd", (kernel_ulong_t)&at24_data_spd }, + { "wb_24c02-vaio", (kernel_ulong_t)&at24_data_24c02_vaio }, + { "wb_24c04", (kernel_ulong_t)&at24_data_24c04 }, + { "wb_24cs04", (kernel_ulong_t)&at24_data_24cs04 }, + { "wb_24c08", (kernel_ulong_t)&at24_data_24c08 }, + { "wb_24cs08", (kernel_ulong_t)&at24_data_24cs08 }, + { "wb_24c16", (kernel_ulong_t)&at24_data_24c16 }, + { "wb_24cs16", (kernel_ulong_t)&at24_data_24cs16 }, + { "wb_24c32", (kernel_ulong_t)&at24_data_24c32 }, + { "wb_24cs32", (kernel_ulong_t)&at24_data_24cs32 }, + { "wb_24c64", (kernel_ulong_t)&at24_data_24c64 }, + { "wb_24cs64", (kernel_ulong_t)&at24_data_24cs64 }, + { "wb_24c128", (kernel_ulong_t)&at24_data_24c128 }, + { "wb_24c256", (kernel_ulong_t)&at24_data_24c256 }, + { "wb_24c512", (kernel_ulong_t)&at24_data_24c512 }, + { "wb_24c1024", (kernel_ulong_t)&at24_data_24c1024 }, + { "wb_24c2048", (kernel_ulong_t)&at24_data_24c2048 }, + { "wb_at24", 0 }, + { /* END OF LIST */ } +}; +MODULE_DEVICE_TABLE(i2c, at24_ids); + +static const struct of_device_id at24_of_match[] = { + { .compatible = "atmel,24c00", .data = &at24_data_24c00 }, + { .compatible = "atmel,24c01", .data = &at24_data_24c01 }, + { .compatible = "atmel,24cs01", .data = &at24_data_24cs01 }, + { .compatible = "atmel,24c02", .data = &at24_data_24c02 }, + { .compatible = "atmel,24cs02", .data = &at24_data_24cs02 }, + { .compatible = "atmel,24mac402", .data = &at24_data_24mac402 }, + { .compatible = "atmel,24mac602", .data = &at24_data_24mac602 }, + { .compatible = "atmel,spd", .data = &at24_data_spd }, + { .compatible = "atmel,24c04", .data = &at24_data_24c04 }, + { .compatible = "atmel,24cs04", .data = &at24_data_24cs04 }, + { .compatible = "atmel,24c08", .data = &at24_data_24c08 }, + { .compatible = "atmel,24cs08", .data = &at24_data_24cs08 }, + { .compatible = "atmel,24c16", .data = &at24_data_24c16 }, + { .compatible = "atmel,24cs16", .data = &at24_data_24cs16 }, + { .compatible = "atmel,24c32", .data = &at24_data_24c32 }, + { .compatible = "atmel,24cs32", .data = &at24_data_24cs32 }, + { .compatible = "atmel,24c64", .data = &at24_data_24c64 }, + { .compatible = "atmel,24cs64", .data = &at24_data_24cs64 }, + { .compatible = "atmel,24c128", .data = &at24_data_24c128 }, + { .compatible = "atmel,24c256", .data = &at24_data_24c256 }, + { .compatible = "atmel,24c512", .data = &at24_data_24c512 }, + { .compatible = "atmel,24c1024", .data = &at24_data_24c1024 }, + { .compatible = "atmel,24c2048", .data = &at24_data_24c2048 }, + { /* END OF LIST */ }, +}; +MODULE_DEVICE_TABLE(of, at24_of_match); + +static const struct acpi_device_id __maybe_unused at24_acpi_ids[] = { + { "INT3499", (kernel_ulong_t)&at24_data_INT3499 }, + { "TPF0001", (kernel_ulong_t)&at24_data_24c1024 }, + { /* END OF LIST */ } +}; +MODULE_DEVICE_TABLE(acpi, at24_acpi_ids); + +/* + * This routine supports chips which consume multiple I2C addresses. It + * computes the addressing information to be used for a given r/w request. + * Assumes that sanity checks for offset happened at sysfs-layer. + * + * Slave address and byte offset derive from the offset. Always + * set the byte address; on a multi-master board, another master + * may have changed the chip's "current" address pointer. + */ +static struct at24_client *at24_translate_offset(struct at24_data *at24, + unsigned int *offset) +{ + unsigned int i; + + if (at24->flags & AT24_FLAG_ADDR16) { + i = *offset >> 16; + *offset &= 0xffff; + } else { + i = *offset >> 8; + *offset &= 0xff; + } + + return &at24->client[i]; +} + +static struct device *at24_base_client_dev(struct at24_data *at24) +{ + return &at24->client[0].client->dev; +} + +static size_t at24_adjust_read_count(struct at24_data *at24, + unsigned int offset, size_t count) +{ + unsigned int bits; + size_t remainder; + + /* + * In case of multi-address chips that don't rollover reads to + * the next slave address: truncate the count to the slave boundary, + * so that the read never straddles slaves. + */ + if (at24->flags & AT24_FLAG_NO_RDROL) { + bits = (at24->flags & AT24_FLAG_ADDR16) ? 16 : 8; + remainder = BIT(bits) - offset; + if (count > remainder) + count = remainder; + } + + if (count > at24_io_limit) + count = at24_io_limit; + + return count; +} + +static ssize_t at24_regmap_read(struct at24_data *at24, char *buf, + unsigned int offset, size_t count) +{ + unsigned long timeout, read_time; + struct at24_client *at24_client; + struct i2c_client *client; + struct regmap *regmap; + int ret; + + at24_client = at24_translate_offset(at24, &offset); + regmap = at24_client->regmap; + client = at24_client->client; + count = at24_adjust_read_count(at24, offset, count); + + /* adjust offset for mac and serial read ops */ + offset += at24->offset_adj; + + timeout = jiffies + msecs_to_jiffies(at24_write_timeout); + do { + /* + * The timestamp shall be taken before the actual operation + * to avoid a premature timeout in case of high CPU load. + */ + read_time = jiffies; + + ret = regmap_bulk_read(regmap, offset, buf, count); + dev_dbg(&client->dev, "read %zu@%d --> %d (%ld)\n", + count, offset, ret, jiffies); + if (!ret) + return count; + + usleep_range(1000, 1500); + } while (time_before(read_time, timeout)); + + return -ETIMEDOUT; +} + +/* + * Note that if the hardware write-protect pin is pulled high, the whole + * chip is normally write protected. But there are plenty of product + * variants here, including OTP fuses and partial chip protect. + * + * We only use page mode writes; the alternative is sloooow. These routines + * write at most one page. + */ + +static size_t at24_adjust_write_count(struct at24_data *at24, + unsigned int offset, size_t count) +{ + unsigned int next_page; + + /* write_max is at most a page */ + if (count > at24->write_max) + count = at24->write_max; + + /* Never roll over backwards, to the start of this page */ + next_page = roundup(offset + 1, at24->page_size); + if (offset + count > next_page) + count = next_page - offset; + + return count; +} + +static ssize_t at24_regmap_write(struct at24_data *at24, const char *buf, + unsigned int offset, size_t count) +{ + unsigned long timeout, write_time; + struct at24_client *at24_client; + struct i2c_client *client; + struct regmap *regmap; + int ret; + + at24_client = at24_translate_offset(at24, &offset); + regmap = at24_client->regmap; + client = at24_client->client; + count = at24_adjust_write_count(at24, offset, count); + timeout = jiffies + msecs_to_jiffies(at24_write_timeout); + + do { + /* + * The timestamp shall be taken before the actual operation + * to avoid a premature timeout in case of high CPU load. + */ + write_time = jiffies; + + ret = regmap_bulk_write(regmap, offset, buf, count); + dev_dbg(&client->dev, "write %zu@%d --> %d (%ld)\n", + count, offset, ret, jiffies); + if (!ret) + return count; + + usleep_range(1000, 1500); + } while (time_before(write_time, timeout)); + + return -ETIMEDOUT; +} + +static int at24_read(void *priv, unsigned int off, void *val, size_t count) +{ + struct at24_data *at24; + struct device *dev; + char *buf = val; + int i, ret; + + at24 = priv; + dev = at24_base_client_dev(at24); + + if (unlikely(!count)) + return count; + + if (off + count > at24->byte_len) + return -EINVAL; + + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + pm_runtime_put_noidle(dev); + return ret; + } + + /* + * Read data from chip, protecting against concurrent updates + * from this host, but not from other I2C masters. + */ + mutex_lock(&at24->lock); + + for (i = 0; count; i += ret, count -= ret) { + ret = at24_regmap_read(at24, buf + i, off + i, count); + if (ret < 0) { + mutex_unlock(&at24->lock); + pm_runtime_put(dev); + return ret; + } + } + + mutex_unlock(&at24->lock); + + pm_runtime_put(dev); + + if (unlikely(at24->read_post)) + at24->read_post(off, buf, i); + + return 0; +} + +static int at24_write(void *priv, unsigned int off, void *val, size_t count) +{ + struct at24_data *at24; + struct device *dev; + char *buf = val; + int ret; + + at24 = priv; + dev = at24_base_client_dev(at24); + + if (unlikely(!count)) + return -EINVAL; + + if (off + count > at24->byte_len) + return -EINVAL; + + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + pm_runtime_put_noidle(dev); + return ret; + } + + /* + * Write data to chip, protecting against concurrent updates + * from this host, but not from other I2C masters. + */ + mutex_lock(&at24->lock); + + while (count) { + ret = at24_regmap_write(at24, buf, off, count); + if (ret < 0) { + mutex_unlock(&at24->lock); + pm_runtime_put(dev); + return ret; + } + buf += ret; + off += ret; + count -= ret; + } + + mutex_unlock(&at24->lock); + + pm_runtime_put(dev); + + return 0; +} + +static const struct at24_chip_data *at24_get_chip_data(struct device *dev) +{ + struct device_node *of_node = dev->of_node; + const struct at24_chip_data *cdata; + const struct i2c_device_id *id; + + id = i2c_match_id(at24_ids, to_i2c_client(dev)); + + /* + * The I2C core allows OF nodes compatibles to match against the + * I2C device ID table as a fallback, so check not only if an OF + * node is present but also if it matches an OF device ID entry. + */ + if (of_node && of_match_device(at24_of_match, dev)) + cdata = of_device_get_match_data(dev); + else if (id) + cdata = (void *)id->driver_data; + else + cdata = acpi_device_get_match_data(dev); + + if (!cdata) + return ERR_PTR(-ENODEV); + + return cdata; +} + +static int at24_make_dummy_client(struct at24_data *at24, unsigned int index, + struct regmap_config *regmap_config) +{ + struct i2c_client *base_client, *dummy_client; + struct regmap *regmap; + struct device *dev; + + base_client = at24->client[0].client; + dev = &base_client->dev; + + dummy_client = devm_i2c_new_dummy_device(dev, base_client->adapter, + base_client->addr + index); + if (IS_ERR(dummy_client)) + return PTR_ERR(dummy_client); + + regmap = devm_regmap_init_i2c(dummy_client, regmap_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + at24->client[index].client = dummy_client; + at24->client[index].regmap = regmap; + + return 0; +} + +static unsigned int at24_get_offset_adj(u8 flags, unsigned int byte_len) +{ + if (flags & AT24_FLAG_MAC) { + /* EUI-48 starts from 0x9a, EUI-64 from 0x98 */ + return 0xa0 - byte_len; + } else if (flags & AT24_FLAG_SERIAL && flags & AT24_FLAG_ADDR16) { + /* + * For 16 bit address pointers, the word address must contain + * a '10' sequence in bits 11 and 10 regardless of the + * intended position of the address pointer. + */ + return 0x0800; + } else if (flags & AT24_FLAG_SERIAL) { + /* + * Otherwise the word address must begin with a '10' sequence, + * regardless of the intended address. + */ + return 0x0080; + } else { + return 0; + } +} + +static int at24_probe(struct i2c_client *client) +{ + struct regmap_config regmap_config = { }; + struct nvmem_config nvmem_config = { }; + u32 byte_len, page_size, flags, addrw; + const struct at24_chip_data *cdata; + struct device *dev = &client->dev; + bool i2c_fn_i2c, i2c_fn_block; + unsigned int i, num_addresses; + struct at24_data *at24; + struct regmap *regmap; + bool writable; + u8 test_byte; + int err; + + i2c_fn_i2c = i2c_check_functionality(client->adapter, I2C_FUNC_I2C); + i2c_fn_block = i2c_check_functionality(client->adapter, + I2C_FUNC_SMBUS_WRITE_I2C_BLOCK); + + cdata = at24_get_chip_data(dev); + if (IS_ERR(cdata)) + return PTR_ERR(cdata); + + err = device_property_read_u32(dev, "pagesize", &page_size); + if (err) + /* + * This is slow, but we can't know all eeproms, so we better + * play safe. Specifying custom eeprom-types via device tree + * or properties is recommended anyhow. + */ + page_size = 1; + + flags = cdata->flags; + if (device_property_present(dev, "read-only")) + flags |= AT24_FLAG_READONLY; + if (device_property_present(dev, "no-read-rollover")) + flags |= AT24_FLAG_NO_RDROL; + + err = device_property_read_u32(dev, "address-width", &addrw); + if (!err) { + switch (addrw) { + case 8: + if (flags & AT24_FLAG_ADDR16) + dev_warn(dev, + "Override address width to be 8, while default is 16\n"); + flags &= ~AT24_FLAG_ADDR16; + break; + case 16: + flags |= AT24_FLAG_ADDR16; + break; + default: + dev_warn(dev, "Bad \"address-width\" property: %u\n", + addrw); + } + } + + err = device_property_read_u32(dev, "size", &byte_len); + if (err) + byte_len = cdata->byte_len; + + if (!i2c_fn_i2c && !i2c_fn_block) + page_size = 1; + + if (!page_size) { + dev_err(dev, "page_size must not be 0!\n"); + return -EINVAL; + } + + if (!is_power_of_2(page_size)) + dev_warn(dev, "page_size looks suspicious (no power of 2)!\n"); + + err = device_property_read_u32(dev, "num-addresses", &num_addresses); + if (err) { + if (flags & AT24_FLAG_TAKE8ADDR) + num_addresses = 8; + else + num_addresses = DIV_ROUND_UP(byte_len, + (flags & AT24_FLAG_ADDR16) ? 65536 : 256); + } + + if ((flags & AT24_FLAG_SERIAL) && (flags & AT24_FLAG_MAC)) { + dev_err(dev, + "invalid device data - cannot have both AT24_FLAG_SERIAL & AT24_FLAG_MAC."); + return -EINVAL; + } + + regmap_config.val_bits = 8; + regmap_config.reg_bits = (flags & AT24_FLAG_ADDR16) ? 16 : 8; + regmap_config.disable_locking = true; + + regmap = devm_regmap_init_i2c(client, ®map_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + at24 = devm_kzalloc(dev, struct_size(at24, client, num_addresses), + GFP_KERNEL); + if (!at24) + return -ENOMEM; + + mutex_init(&at24->lock); + at24->byte_len = byte_len; + at24->page_size = page_size; + at24->flags = flags; + at24->read_post = cdata->read_post; + at24->num_addresses = num_addresses; + at24->offset_adj = at24_get_offset_adj(flags, byte_len); + at24->client[0].client = client; + at24->client[0].regmap = regmap; + + at24->vcc_reg = devm_regulator_get(dev, "vcc"); + if (IS_ERR(at24->vcc_reg)) + return PTR_ERR(at24->vcc_reg); + + writable = !(flags & AT24_FLAG_READONLY); + if (writable) { + at24->write_max = min_t(unsigned int, + page_size, at24_io_limit); + if (!i2c_fn_i2c && at24->write_max > I2C_SMBUS_BLOCK_MAX) + at24->write_max = I2C_SMBUS_BLOCK_MAX; + } + + /* use dummy devices for multiple-address chips */ + for (i = 1; i < num_addresses; i++) { + err = at24_make_dummy_client(at24, i, ®map_config); + if (err) + return err; + } + + /* + * If the 'label' property is not present for the AT24 EEPROM, + * then nvmem_config.id is initialised to NVMEM_DEVID_AUTO, + * and this will append the 'devid' to the name of the NVMEM + * device. This is purely legacy and the AT24 driver has always + * defaulted to this. However, if the 'label' property is + * present then this means that the name is specified by the + * firmware and this name should be used verbatim and so it is + * not necessary to append the 'devid'. + */ + if (device_property_present(dev, "label")) { + nvmem_config.id = NVMEM_DEVID_NONE; + err = device_property_read_string(dev, "label", + &nvmem_config.name); + if (err) + return err; + } else { + nvmem_config.id = NVMEM_DEVID_AUTO; + nvmem_config.name = dev_name(dev); + } + + nvmem_config.type = NVMEM_TYPE_EEPROM; + nvmem_config.dev = dev; + nvmem_config.read_only = !writable; + nvmem_config.root_only = !(flags & AT24_FLAG_IRUGO); + nvmem_config.owner = THIS_MODULE; + nvmem_config.compat = true; + nvmem_config.base_dev = dev; + nvmem_config.reg_read = at24_read; + nvmem_config.reg_write = at24_write; + nvmem_config.priv = at24; + nvmem_config.stride = 1; + nvmem_config.word_size = 1; + nvmem_config.size = byte_len; + + i2c_set_clientdata(client, at24); + + err = regulator_enable(at24->vcc_reg); + if (err) { + dev_err(dev, "Failed to enable vcc regulator\n"); + return err; + } + + /* enable runtime pm */ + pm_runtime_set_active(dev); + pm_runtime_enable(dev); + + at24->nvmem = devm_nvmem_register(dev, &nvmem_config); + if (IS_ERR(at24->nvmem)) { + pm_runtime_disable(dev); + if (!pm_runtime_status_suspended(dev)) + regulator_disable(at24->vcc_reg); + return PTR_ERR(at24->nvmem); + } + + /* + * Perform a one-byte test read to verify that the + * chip is functional. + */ + err = at24_read(at24, 0, &test_byte, 1); + if (err) { + pm_runtime_disable(dev); + if (!pm_runtime_status_suspended(dev)) + regulator_disable(at24->vcc_reg); + return -ENODEV; + } + + pm_runtime_idle(dev); + + if (writable) + dev_info(dev, "%u byte %s EEPROM, writable, %u bytes/write\n", + byte_len, client->name, at24->write_max); + else + dev_info(dev, "%u byte %s EEPROM, read-only\n", + byte_len, client->name); + + return 0; +} + +static int at24_remove(struct i2c_client *client) +{ + struct at24_data *at24 = i2c_get_clientdata(client); + + pm_runtime_disable(&client->dev); + if (!pm_runtime_status_suspended(&client->dev)) + regulator_disable(at24->vcc_reg); + pm_runtime_set_suspended(&client->dev); + + return 0; +} + +static int __maybe_unused at24_suspend(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct at24_data *at24 = i2c_get_clientdata(client); + + return regulator_disable(at24->vcc_reg); +} + +static int __maybe_unused at24_resume(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct at24_data *at24 = i2c_get_clientdata(client); + + return regulator_enable(at24->vcc_reg); +} + +static const struct dev_pm_ops at24_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) + SET_RUNTIME_PM_OPS(at24_suspend, at24_resume, NULL) +}; + +static struct i2c_driver at24_driver = { + .driver = { + .name = "wb_at24", + .pm = &at24_pm_ops, + .of_match_table = at24_of_match, + .acpi_match_table = ACPI_PTR(at24_acpi_ids), + }, + .probe_new = at24_probe, + .remove = at24_remove, + .id_table = at24_ids, +}; + +static int __init at24_init(void) +{ + if (!at24_io_limit) { + pr_err("at24: at24_io_limit must not be 0!\n"); + return -EINVAL; + } + + at24_io_limit = rounddown_pow_of_two(at24_io_limit); + return i2c_add_driver(&at24_driver); +} +module_init(at24_init); + +static void __exit at24_exit(void) +{ + i2c_del_driver(&at24_driver); +} +module_exit(at24_exit); + +MODULE_DESCRIPTION("Driver for most I2C EEPROMs"); +MODULE_AUTHOR("support"); +MODULE_LICENSE("GPL"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_csu550.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_csu550.c new file mode 100644 index 000000000000..36d07f071a71 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_csu550.c @@ -0,0 +1,236 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Hardware monitoring driver for PMBus devices + * + * Copyright (c) 2010, 2011 Ericsson AB. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "wb_pmbus.h" + +struct pmbus_device_info { + int pages; + u32 flags; +}; + +static const struct i2c_device_id pmbus_id[]; + +/* + * Find sensor groups and status registers on each page. + */ +static void pmbus_find_sensor_groups(struct i2c_client *client, + struct pmbus_driver_info *info) +{ + int page; + + /* Sensors detected on page 0 only */ + if (wb_pmbus_check_word_register(client, 0, PMBUS_READ_VIN)) + info->func[0] |= PMBUS_HAVE_VIN; + if (wb_pmbus_check_word_register(client, 0, PMBUS_READ_IIN)) + info->func[0] |= PMBUS_HAVE_IIN; + if (wb_pmbus_check_word_register(client, 0, PMBUS_READ_PIN)) + info->func[0] |= PMBUS_HAVE_PIN; + if (info->func[0] + && wb_pmbus_check_byte_register(client, 0, PMBUS_STATUS_INPUT)) + info->func[0] |= PMBUS_HAVE_STATUS_INPUT; + if (wb_pmbus_check_byte_register(client, 0, PMBUS_FAN_CONFIG_12) && + wb_pmbus_check_word_register(client, 0, PMBUS_READ_FAN_SPEED_1)) { + info->func[0] |= PMBUS_HAVE_FAN12; + if (wb_pmbus_check_byte_register(client, 0, PMBUS_STATUS_FAN_12)) + info->func[0] |= PMBUS_HAVE_STATUS_FAN12; + } + if (wb_pmbus_check_byte_register(client, 0, PMBUS_FAN_CONFIG_34) && + wb_pmbus_check_word_register(client, 0, PMBUS_READ_FAN_SPEED_3)) { + info->func[0] |= PMBUS_HAVE_FAN34; + if (wb_pmbus_check_byte_register(client, 0, PMBUS_STATUS_FAN_34)) + info->func[0] |= PMBUS_HAVE_STATUS_FAN34; + } + if (wb_pmbus_check_word_register(client, 0, PMBUS_READ_TEMPERATURE_1)) + info->func[0] |= PMBUS_HAVE_TEMP; + if (wb_pmbus_check_word_register(client, 0, PMBUS_READ_TEMPERATURE_2)) + info->func[0] |= PMBUS_HAVE_TEMP2; + if (wb_pmbus_check_word_register(client, 0, PMBUS_READ_TEMPERATURE_3)) + info->func[0] |= PMBUS_HAVE_TEMP3; + if (info->func[0] & (PMBUS_HAVE_TEMP | PMBUS_HAVE_TEMP2 + | PMBUS_HAVE_TEMP3) + && wb_pmbus_check_byte_register(client, 0, + PMBUS_STATUS_TEMPERATURE)) + info->func[0] |= PMBUS_HAVE_STATUS_TEMP; + + /* Sensors detected on all pages */ + for (page = 0; page < info->pages; page++) { + if (wb_pmbus_check_word_register(client, page, PMBUS_READ_VOUT)) { + info->func[page] |= PMBUS_HAVE_VOUT; + if (wb_pmbus_check_byte_register(client, page, + PMBUS_STATUS_VOUT)) + info->func[page] |= PMBUS_HAVE_STATUS_VOUT; + } + if (wb_pmbus_check_word_register(client, page, PMBUS_READ_IOUT)) { + info->func[page] |= PMBUS_HAVE_IOUT; + if (wb_pmbus_check_byte_register(client, 0, + PMBUS_STATUS_IOUT)) + info->func[page] |= PMBUS_HAVE_STATUS_IOUT; + } + if (wb_pmbus_check_word_register(client, page, PMBUS_READ_POUT)) + info->func[page] |= PMBUS_HAVE_POUT; + } +} + +/* + * Identify chip parameters. + */ +static int pmbus_identify(struct i2c_client *client, + struct pmbus_driver_info *info) +{ + int ret = 0; + + if (!info->pages) { + /* + * Check if the PAGE command is supported. If it is, + * keep setting the page number until it fails or until the + * maximum number of pages has been reached. Assume that + * this is the number of pages supported by the chip. + */ + if (wb_pmbus_check_byte_register(client, 0, PMBUS_PAGE)) { + int page; + + for (page = 1; page < PMBUS_PAGES; page++) { + if (wb_pmbus_set_page(client, page, 0xff) < 0) + break; + } + wb_pmbus_set_page(client, 0, 0xff); + info->pages = page; + } else { + info->pages = 1; + } + + wb_pmbus_clear_faults(client); + } + + if (wb_pmbus_check_byte_register(client, 0, PMBUS_VOUT_MODE)) { + int vout_mode, i; + + vout_mode = wb_pmbus_read_byte_data(client, 0, PMBUS_VOUT_MODE); + if (vout_mode >= 0 && vout_mode != 0xff) { + switch (vout_mode >> 5) { + case 0: + break; + case 1: + info->format[PSC_VOLTAGE_OUT] = vid; + for (i = 0; i < info->pages; i++) + info->vrm_version[i] = vr11; + break; + case 2: + info->format[PSC_VOLTAGE_OUT] = direct; + break; + default: + ret = -ENODEV; + goto abort; + } + } + } + + /* + * We should check if the COEFFICIENTS register is supported. + * If it is, and the chip is configured for direct mode, we can read + * the coefficients from the chip, one set per group of sensor + * registers. + * + * To do this, we will need access to a chip which actually supports the + * COEFFICIENTS command, since the command is too complex to implement + * without testing it. Until then, abort if a chip configured for direct + * mode was detected. + */ + if (info->format[PSC_VOLTAGE_OUT] == direct) { + ret = -ENODEV; + goto abort; + } + + /* Try to find sensor groups */ + pmbus_find_sensor_groups(client, info); +abort: + return ret; +} + +static int pmbus_probe(struct i2c_client *client) +{ + struct pmbus_driver_info *info; + struct pmbus_platform_data *pdata = NULL; + struct device *dev = &client->dev; + struct pmbus_device_info *device_info; + + info = devm_kzalloc(dev, sizeof(struct pmbus_driver_info), GFP_KERNEL); + if (!info) + return -ENOMEM; + + device_info = (struct pmbus_device_info *)i2c_match_id(pmbus_id, client)->driver_data; + if (device_info->flags & PMBUS_SKIP_STATUS_CHECK) { + pdata = devm_kzalloc(dev, sizeof(struct pmbus_platform_data), + GFP_KERNEL); + if (!pdata) + return -ENOMEM; + + pdata->flags = PMBUS_SKIP_STATUS_CHECK; + } + + info->pages = device_info->pages; + info->identify = pmbus_identify; + dev->platform_data = pdata; + + return wb_pmbus_do_probe(client, info); +} + +static const struct pmbus_device_info pmbus_info_one = { + .pages = 1, + .flags = 0 +}; + +static const struct pmbus_device_info pmbus_info_zero = { + .pages = 0, + .flags = 0 +}; + +static const struct pmbus_device_info pmbus_info_one_skip = { + .pages = 1, + .flags = PMBUS_SKIP_STATUS_CHECK +}; + +static const struct pmbus_device_info pmbus_info_zero_skip = { + .pages = 0, + .flags = PMBUS_SKIP_STATUS_CHECK +}; +/* + * Use driver_data to set the number of pages supported by the chip. + */ +static const struct i2c_device_id pmbus_id[] = { + {"wb_csu550", (kernel_ulong_t)&pmbus_info_zero_skip}, + {"wb_csu800", (kernel_ulong_t)&pmbus_info_one_skip}, + {"wb_fsp1200", (kernel_ulong_t)&pmbus_info_one_skip}, + {"wb_dps550", (kernel_ulong_t)&pmbus_info_one_skip}, + {} +}; + +MODULE_DEVICE_TABLE(i2c, pmbus_id); + +/* This is the driver that will be inserted */ +static struct i2c_driver pmbus_driver = { + .driver = { + .name = "wb_pmbus", + }, + .probe_new = pmbus_probe, + .remove = wb_pmbus_do_remove, + .id_table = pmbus_id, +}; + +module_i2c_driver(pmbus_driver); + +MODULE_AUTHOR("support"); +MODULE_DESCRIPTION("Generic PMBus driver"); +MODULE_LICENSE("GPL"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_i2c_algo_bit.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_i2c_algo_bit.c new file mode 100644 index 000000000000..c98ac7a1c5b6 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_i2c_algo_bit.c @@ -0,0 +1,725 @@ +/* ------------------------------------------------------------------------- + * i2c-algo-bit.c i2c driver algorithms for bit-shift adapters + * ------------------------------------------------------------------------- + * Copyright (C) 1995-2000 Simon G. Vogl + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + * ------------------------------------------------------------------------- */ + +#include +#include +#include +#include +#include +#include +#include + +static int g_i2c_algo_bit_debug = 0; +static int g_i2c_algo_bit_error = 0; + +module_param(g_i2c_algo_bit_debug, int, S_IRUGO | S_IWUSR); +module_param(g_i2c_algo_bit_error, int, S_IRUGO | S_IWUSR); + +#define I2C_ALGO_BIT_DEBUG(fmt, args...) do { \ + if (g_i2c_algo_bit_debug) { \ + printk(KERN_INFO "[I2C_ALGO_BIT][VER][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +#define I2C_ALGO_BIT_ERROR(fmt, args...) do { \ + if (g_i2c_algo_bit_error) { \ + printk(KERN_ERR "[I2C_ALGO_BIT][ERR][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +/* ----- global defines ----------------------------------------------- */ + +#ifdef DEBUG +#define bit_dbg(level, dev, format, args...) \ + do { \ + if (i2c_debug >= level) \ + dev_dbg(dev, format, ##args); \ + } while (0) +#else +#define bit_dbg(level, dev, format, args...) \ + do {} while (0) +#endif /* DEBUG */ + +/* ----- global variables --------------------------------------------- */ + +static int bit_test; /* see if the line-setting functions work */ +module_param(bit_test, int, S_IRUGO); +MODULE_PARM_DESC(bit_test, "lines testing - 0 off; 1 report; 2 fail if stuck"); + +#ifdef DEBUG +static int i2c_debug = 1; +module_param(i2c_debug, int, S_IRUGO | S_IWUSR); +MODULE_PARM_DESC(i2c_debug, + "debug level - 0 off; 1 normal; 2 verbose; 3 very verbose"); +#endif + +/* --- setting states on the bus with the right timing: --------------- */ + +#define setsda(adap, val) adap->setsda(adap->data, val) +#define setscl(adap, val) adap->setscl(adap->data, val) +#define getsda(adap) adap->getsda(adap->data) +#define getscl(adap) adap->getscl(adap->data) + +static inline void sdalo(struct i2c_algo_bit_data *adap) +{ + setsda(adap, 0); + udelay((adap->udelay + 1) / 2); +} + +static inline void sdahi(struct i2c_algo_bit_data *adap) +{ + setsda(adap, 1); + udelay((adap->udelay + 1) / 2); +} + +static inline void scllo(struct i2c_algo_bit_data *adap) +{ + setscl(adap, 0); + udelay(adap->udelay / 2); +} + +/* + * Raise scl line, and do checking for delays. This is necessary for slower + * devices. + */ +static int sclhi(struct i2c_algo_bit_data *adap) +{ + unsigned long start; + + setscl(adap, 1); + + /* Not all adapters have scl sense line... */ + if (!adap->getscl) + goto done; + + start = jiffies; + while (!getscl(adap)) { + /* This hw knows how to read the clock line, so we wait + * until it actually gets high. This is safer as some + * chips may hold it low ("clock stretching") while they + * are processing data internally. + */ + if (time_after(jiffies, start + adap->timeout)) { + /* Test one last time, as we may have been preempted + * between last check and timeout test. + */ + if (getscl(adap)) + break; + return -ETIMEDOUT; + } + cpu_relax(); + } +#ifdef DEBUG + if (jiffies != start && i2c_debug >= 3) + pr_debug("i2c-algo-bit: needed %ld jiffies for SCL to go " + "high\n", jiffies - start); +#endif + +done: + udelay(adap->udelay); + return 0; +} + +/* --- other auxiliary functions -------------------------------------- */ +static void i2c_start(struct i2c_algo_bit_data *adap) +{ + /* assert: scl, sda are high */ + setsda(adap, 0); + udelay(adap->udelay); + scllo(adap); +} + +static void i2c_repstart(struct i2c_algo_bit_data *adap) +{ + /* assert: scl is low */ + sdahi(adap); + sclhi(adap); + setsda(adap, 0); + udelay(adap->udelay); + scllo(adap); +} + +static void i2c_stop(struct i2c_algo_bit_data *adap) +{ + /* assert: scl is low */ + sdalo(adap); + sclhi(adap); + setsda(adap, 1); + udelay(adap->udelay); +} + +/* send a byte without start cond., look for arbitration, + check ackn. from slave */ +/* returns: + * 1 if the device acknowledged + * 0 if the device did not ack + * -ETIMEDOUT if an error occurred (while raising the scl line) + */ +static int i2c_outb(struct i2c_adapter *i2c_adap, unsigned char c) +{ + int i; + int sb; + int ack; + struct i2c_algo_bit_data *adap = i2c_adap->algo_data; + + /* assert: scl is low */ + for (i = 7; i >= 0; i--) { + sb = (c >> i) & 1; + setsda(adap, sb); + udelay((adap->udelay + 1) / 2); + if (sclhi(adap) < 0) { /* timed out */ + bit_dbg(1, &i2c_adap->dev, "i2c_outb: 0x%02x, " + "timeout at bit #%d\n", (int)c, i); + return -ETIMEDOUT; + } + /* FIXME do arbitration here: + * if (sb && !getsda(adap)) -> ouch! Get out of here. + * + * Report a unique code, so higher level code can retry + * the whole (combined) message and *NOT* issue STOP. + */ + scllo(adap); + } + sdahi(adap); + if (sclhi(adap) < 0) { /* timeout */ + bit_dbg(1, &i2c_adap->dev, "i2c_outb: 0x%02x, " + "timeout at ack\n", (int)c); + return -ETIMEDOUT; + } + + /* read ack: SDA should be pulled down by slave, or it may + * NAK (usually to report problems with the data we wrote). + */ + ack = !getsda(adap); /* ack: sda is pulled low -> success */ + bit_dbg(2, &i2c_adap->dev, "i2c_outb: 0x%02x %s\n", (int)c, + ack ? "A" : "NA"); + + scllo(adap); + return ack; + /* assert: scl is low (sda undef) */ +} + +static int i2c_inb(struct i2c_adapter *i2c_adap) +{ + /* read byte via i2c port, without start/stop sequence */ + /* acknowledge is sent in i2c_read. */ + int i; + unsigned char indata = 0; + struct i2c_algo_bit_data *adap = i2c_adap->algo_data; + + /* assert: scl is low */ + sdahi(adap); + for (i = 0; i < 8; i++) { + if (sclhi(adap) < 0) { /* timeout */ + bit_dbg(1, &i2c_adap->dev, "i2c_inb: timeout at bit " + "#%d\n", 7 - i); + return -ETIMEDOUT; + } + indata *= 2; + if (getsda(adap)) + indata |= 0x01; + setscl(adap, 0); + udelay(i == 7 ? adap->udelay / 2 : adap->udelay); + } + /* assert: scl is low */ + return indata; +} + +/* + * Sanity check for the adapter hardware - check the reaction of + * the bus lines only if it seems to be idle. + */ +static int test_bus(struct i2c_adapter *i2c_adap) +{ + struct i2c_algo_bit_data *adap = i2c_adap->algo_data; + const char *name = i2c_adap->name; + int scl, sda, ret; + + if (adap->pre_xfer) { + ret = adap->pre_xfer(i2c_adap); + if (ret < 0) + return -ENODEV; + } + + if (adap->getscl == NULL) + pr_info("%s: Testing SDA only, SCL is not readable\n", name); + + sda = getsda(adap); + scl = (adap->getscl == NULL) ? 1 : getscl(adap); + if (!scl || !sda) { + printk(KERN_WARNING + "%s: bus seems to be busy (scl=%d, sda=%d)\n", + name, scl, sda); + goto bailout; + } + + sdalo(adap); + sda = getsda(adap); + scl = (adap->getscl == NULL) ? 1 : getscl(adap); + if (sda) { + printk(KERN_WARNING "%s: SDA stuck high!\n", name); + goto bailout; + } + if (!scl) { + printk(KERN_WARNING "%s: SCL unexpected low " + "while pulling SDA low!\n", name); + goto bailout; + } + + sdahi(adap); + sda = getsda(adap); + scl = (adap->getscl == NULL) ? 1 : getscl(adap); + if (!sda) { + printk(KERN_WARNING "%s: SDA stuck low!\n", name); + goto bailout; + } + if (!scl) { + printk(KERN_WARNING "%s: SCL unexpected low " + "while pulling SDA high!\n", name); + goto bailout; + } + + scllo(adap); + sda = getsda(adap); + scl = (adap->getscl == NULL) ? 0 : getscl(adap); + if (scl) { + printk(KERN_WARNING "%s: SCL stuck high!\n", name); + goto bailout; + } + if (!sda) { + printk(KERN_WARNING "%s: SDA unexpected low " + "while pulling SCL low!\n", name); + goto bailout; + } + + sclhi(adap); + sda = getsda(adap); + scl = (adap->getscl == NULL) ? 1 : getscl(adap); + if (!scl) { + printk(KERN_WARNING "%s: SCL stuck low!\n", name); + goto bailout; + } + if (!sda) { + printk(KERN_WARNING "%s: SDA unexpected low " + "while pulling SCL high!\n", name); + goto bailout; + } + + if (adap->post_xfer) + adap->post_xfer(i2c_adap); + + pr_info("%s: Test OK\n", name); + return 0; +bailout: + sdahi(adap); + sclhi(adap); + + if (adap->post_xfer) + adap->post_xfer(i2c_adap); + + return -ENODEV; +} + +/* ----- Utility functions + */ + +/* try_address tries to contact a chip for a number of + * times before it gives up. + * return values: + * 1 chip answered + * 0 chip did not answer + * -x transmission error + */ +static int try_address(struct i2c_adapter *i2c_adap, + unsigned char addr, int retries) +{ + struct i2c_algo_bit_data *adap = i2c_adap->algo_data; + int i, ret = 0; + + for (i = 0; i <= retries; i++) { + ret = i2c_outb(i2c_adap, addr); + if (ret == 1 || i == retries) + break; + bit_dbg(3, &i2c_adap->dev, "emitting stop condition\n"); + i2c_stop(adap); + udelay(adap->udelay); + yield(); + bit_dbg(3, &i2c_adap->dev, "emitting start condition\n"); + i2c_start(adap); + } + if (i && ret) + bit_dbg(1, &i2c_adap->dev, "Used %d tries to %s client at " + "0x%02x: %s\n", i + 1, + addr & 1 ? "read from" : "write to", addr >> 1, + ret == 1 ? "success" : "failed, timeout?"); + return ret; +} + +static int sendbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msg) +{ + const unsigned char *temp = msg->buf; + int count = msg->len; + unsigned short nak_ok = msg->flags & I2C_M_IGNORE_NAK; + int retval; + int wrcount = 0; + + while (count > 0) { + retval = i2c_outb(i2c_adap, *temp); + + /* OK/ACK; or ignored NAK */ + if ((retval > 0) || (nak_ok && (retval == 0))) { + count--; + temp++; + wrcount++; + + /* A slave NAKing the master means the slave didn't like + * something about the data it saw. For example, maybe + * the SMBus PEC was wrong. + */ + } else if (retval == 0) { + dev_err(&i2c_adap->dev, "sendbytes: NAK bailout.\n"); + return -EIO; + + /* Timeout; or (someday) lost arbitration + * + * FIXME Lost ARB implies retrying the transaction from + * the first message, after the "winning" master issues + * its STOP. As a rule, upper layer code has no reason + * to know or care about this ... it is *NOT* an error. + */ + } else { + dev_err(&i2c_adap->dev, "sendbytes: error %d\n", + retval); + return retval; + } + } + return wrcount; +} + +static int acknak(struct i2c_adapter *i2c_adap, int is_ack) +{ + struct i2c_algo_bit_data *adap = i2c_adap->algo_data; + + /* assert: sda is high */ + if (is_ack) /* send ack */ + setsda(adap, 0); + udelay((adap->udelay + 1) / 2); + if (sclhi(adap) < 0) { /* timeout */ + dev_err(&i2c_adap->dev, "readbytes: ack/nak timeout\n"); + return -ETIMEDOUT; + } + scllo(adap); + return 0; +} + +static int readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msg) +{ + int inval; + int rdcount = 0; /* counts bytes read */ + unsigned char *temp = msg->buf; + int count = msg->len; + const unsigned flags = msg->flags; + + while (count > 0) { + inval = i2c_inb(i2c_adap); + if (inval >= 0) { + *temp = inval; + rdcount++; + } else { /* read timed out */ + break; + } + + temp++; + count--; + + /* Some SMBus transactions require that we receive the + transaction length as the first read byte. */ + if (rdcount == 1 && (flags & I2C_M_RECV_LEN)) { + if (inval <= 0 || inval > I2C_SMBUS_BLOCK_MAX) { + if (!(flags & I2C_M_NO_RD_ACK)) + acknak(i2c_adap, 0); + dev_err(&i2c_adap->dev, "readbytes: invalid " + "block length (%d)\n", inval); + return -EPROTO; + } + /* The original count value accounts for the extra + bytes, that is, either 1 for a regular transaction, + or 2 for a PEC transaction. */ + count += inval; + msg->len += inval; + } + + bit_dbg(2, &i2c_adap->dev, "readbytes: 0x%02x %s\n", + inval, + (flags & I2C_M_NO_RD_ACK) + ? "(no ack/nak)" + : (count ? "A" : "NA")); + + if (!(flags & I2C_M_NO_RD_ACK)) { + inval = acknak(i2c_adap, count); + if (inval < 0) + return inval; + } + } + return rdcount; +} + +/* doAddress initiates the transfer by generating the start condition (in + * try_address) and transmits the address in the necessary format to handle + * reads, writes as well as 10bit-addresses. + * returns: + * 0 everything went okay, the chip ack'ed, or IGNORE_NAK flag was set + * -x an error occurred (like: -ENXIO if the device did not answer, or + * -ETIMEDOUT, for example if the lines are stuck...) + */ +static int bit_doAddress(struct i2c_adapter *i2c_adap, struct i2c_msg *msg) +{ + unsigned short flags = msg->flags; + unsigned short nak_ok = msg->flags & I2C_M_IGNORE_NAK; + struct i2c_algo_bit_data *adap = i2c_adap->algo_data; + + unsigned char addr; + int ret, retries; + + retries = nak_ok ? 0 : i2c_adap->retries; + + if (flags & I2C_M_TEN) { + /* a ten bit address */ + addr = 0xf0 | ((msg->addr >> 7) & 0x06); + bit_dbg(2, &i2c_adap->dev, "addr0: %d\n", addr); + /* try extended address code...*/ + ret = try_address(i2c_adap, addr, retries); + if ((ret != 1) && !nak_ok) { + dev_err(&i2c_adap->dev, + "died at extended address code\n"); + return -ENXIO; + } + /* the remaining 8 bit address */ + ret = i2c_outb(i2c_adap, msg->addr & 0xff); + if ((ret != 1) && !nak_ok) { + /* the chip did not ack / xmission error occurred */ + dev_err(&i2c_adap->dev, "died at 2nd address code\n"); + return -ENXIO; + } + if (flags & I2C_M_RD) { + bit_dbg(3, &i2c_adap->dev, "emitting repeated " + "start condition\n"); + i2c_repstart(adap); + /* okay, now switch into reading mode */ + addr |= 0x01; + ret = try_address(i2c_adap, addr, retries); + if ((ret != 1) && !nak_ok) { + dev_err(&i2c_adap->dev, + "died at repeated address code\n"); + return -EIO; + } + } + } else { /* normal 7bit address */ + addr = msg->addr << 1; + if (flags & I2C_M_RD) + addr |= 1; + if (flags & I2C_M_REV_DIR_ADDR) + addr ^= 1; + ret = try_address(i2c_adap, addr, retries); + if ((ret != 1) && !nak_ok) + return -ENXIO; + } + + return 0; +} + +static void bit_i2c_unblock(struct i2c_adapter *i2c_adap) +{ + int i; + struct i2c_algo_bit_data *adap = i2c_adap->algo_data; + + for (i = 0; i < 9; i++) { + setscl(adap, 0); + udelay(5); + setscl(adap, 1); + udelay(5); + } + setscl(adap, 0); + setsda(adap, 0); + udelay(5); + setscl(adap, 1); + udelay(5); + setsda(adap, 1); +} + +static int check_bit_i2c_unblock(struct i2c_adapter *i2c_adap) +{ + struct i2c_algo_bit_data *adap = i2c_adap->algo_data; + int sda, scl; + + sda = getsda(adap); + scl = getscl(adap); + if ((sda == 0) && scl) { + I2C_ALGO_BIT_ERROR("SCL is high and SDA is low, send 9 clock to device.\n"); + bit_i2c_unblock(i2c_adap); + } + + sda = getsda(adap); + scl = getscl(adap); + if (sda && scl) { + I2C_ALGO_BIT_DEBUG("SCL and SDA are both high, i2c level check ok.\n"); + return 0; + } + dev_warn(&i2c_adap->dev, "Check i2c level failed, SCL %s, SDA %s.\n", scl ? "high" : "low", sda ? "high" : "low"); + return -EIO; +} + +static int bit_xfer(struct i2c_adapter *i2c_adap, + struct i2c_msg msgs[], int num) +{ + struct i2c_msg *pmsg; + struct i2c_algo_bit_data *adap = i2c_adap->algo_data; + int i, ret; + unsigned short nak_ok; + + if (adap->pre_xfer) { + ret = adap->pre_xfer(i2c_adap); + if (ret < 0) + return ret; + } + + if (check_bit_i2c_unblock(i2c_adap) < 0) { + I2C_ALGO_BIT_ERROR("check i2c is block.\n"); + return -EIO; + } + + bit_dbg(3, &i2c_adap->dev, "emitting start condition\n"); + i2c_start(adap); + for (i = 0; i < num; i++) { + pmsg = &msgs[i]; + nak_ok = pmsg->flags & I2C_M_IGNORE_NAK; + if (!(pmsg->flags & I2C_M_NOSTART)) { + if (i) { + bit_dbg(3, &i2c_adap->dev, "emitting " + "repeated start condition\n"); + i2c_repstart(adap); + } + ret = bit_doAddress(i2c_adap, pmsg); + if ((ret != 0) && !nak_ok) { + bit_dbg(1, &i2c_adap->dev, "NAK from " + "device addr 0x%02x msg #%d\n", + msgs[i].addr, i); + goto bailout; + } + } + if (pmsg->flags & I2C_M_RD) { + /* read bytes into buffer*/ + ret = readbytes(i2c_adap, pmsg); + if (ret >= 1) + bit_dbg(2, &i2c_adap->dev, "read %d byte%s\n", + ret, ret == 1 ? "" : "s"); + if (ret < pmsg->len) { + if (ret >= 0) + ret = -EIO; + goto bailout; + } + } else { + /* write bytes from buffer */ + ret = sendbytes(i2c_adap, pmsg); + if (ret >= 1) + bit_dbg(2, &i2c_adap->dev, "wrote %d byte%s\n", + ret, ret == 1 ? "" : "s"); + if (ret < pmsg->len) { + if (ret >= 0) + ret = -EIO; + goto bailout; + } + } + } + ret = i; + +bailout: + bit_dbg(3, &i2c_adap->dev, "emitting stop condition\n"); + i2c_stop(adap); + + if (adap->post_xfer) + adap->post_xfer(i2c_adap); + return ret; +} + +static u32 bit_func(struct i2c_adapter *adap) +{ + return I2C_FUNC_I2C | I2C_FUNC_NOSTART | I2C_FUNC_SMBUS_EMUL | + I2C_FUNC_SMBUS_READ_BLOCK_DATA | + I2C_FUNC_SMBUS_BLOCK_PROC_CALL | + I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING; +} + +/* -----exported algorithm data: ------------------------------------- */ + +const struct i2c_algorithm wb_i2c_bit_algo = { + .master_xfer = bit_xfer, + .functionality = bit_func, +}; +EXPORT_SYMBOL(wb_i2c_bit_algo); + +static const struct i2c_adapter_quirks i2c_bit_quirk_no_clk_stretch = { + .flags = I2C_AQ_NO_CLK_STRETCH, +}; + +/* + * registering functions to load algorithms at runtime + */ +static int __i2c_bit_add_bus(struct i2c_adapter *adap, + int (*add_adapter)(struct i2c_adapter *)) +{ + struct i2c_algo_bit_data *bit_adap = adap->algo_data; + int ret; + + if (bit_test) { + ret = test_bus(adap); + if (bit_test >= 2 && ret < 0) + return -ENODEV; + } + + /* register new adapter to i2c module... */ + adap->algo = &wb_i2c_bit_algo; + adap->retries = 3; + if (bit_adap->getscl == NULL) + adap->quirks = &i2c_bit_quirk_no_clk_stretch; + + ret = add_adapter(adap); + if (ret < 0) + return ret; + + /* Complain if SCL can't be read */ + if (bit_adap->getscl == NULL) { + dev_warn(&adap->dev, "Not I2C compliant: can't read SCL\n"); + dev_warn(&adap->dev, "Bus may be unreliable\n"); + } + return 0; +} + +int wb_i2c_bit_add_bus(struct i2c_adapter *adap) +{ + return __i2c_bit_add_bus(adap, i2c_add_adapter); +} +EXPORT_SYMBOL(wb_i2c_bit_add_bus); + +int wb_i2c_bit_add_numbered_bus(struct i2c_adapter *adap) +{ + return __i2c_bit_add_bus(adap, i2c_add_numbered_adapter); +} +EXPORT_SYMBOL(wb_i2c_bit_add_numbered_bus); + +MODULE_AUTHOR("support"); +MODULE_DESCRIPTION("I2C-Bus bit-banging algorithm"); +MODULE_LICENSE("GPL"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_i2c_gpio.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_i2c_gpio.c new file mode 100644 index 000000000000..0362e905fddb --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_i2c_gpio.c @@ -0,0 +1,431 @@ +/* + * Bitbanging I2C bus driver using the GPIO API + * + * Copyright (C) 2007 Atmel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern int wb_i2c_bit_add_numbered_bus(struct i2c_adapter *adap); + +struct i2c_gpio_private_data { + struct gpio_desc *sda; + struct gpio_desc *scl; + struct i2c_adapter adap; + struct i2c_algo_bit_data bit_data; + struct i2c_gpio_platform_data pdata; +#ifdef CONFIG_I2C_GPIO_FAULT_INJECTOR + struct dentry *debug_dir; +#endif +}; + +/* + * Toggle SDA by changing the output value of the pin. This is only + * valid for pins configured as open drain (i.e. setting the value + * high effectively turns off the output driver.) + */ +static void i2c_gpio_setsda_val(void *data, int state) +{ + struct i2c_gpio_private_data *priv = data; + + gpiod_set_value_cansleep(priv->sda, state); +} + +/* + * Toggle SCL by changing the output value of the pin. This is used + * for pins that are configured as open drain and for output-only + * pins. The latter case will break the i2c protocol, but it will + * often work in practice. + */ +static void i2c_gpio_setscl_val(void *data, int state) +{ + struct i2c_gpio_private_data *priv = data; + + gpiod_set_value_cansleep(priv->scl, state); +} + +static int i2c_gpio_getsda(void *data) +{ + struct i2c_gpio_private_data *priv = data; + + return gpiod_get_value_cansleep(priv->sda); +} + +static int i2c_gpio_getscl(void *data) +{ + struct i2c_gpio_private_data *priv = data; + + return gpiod_get_value_cansleep(priv->scl); +} + +#ifdef CONFIG_I2C_GPIO_FAULT_INJECTOR +static struct dentry *i2c_gpio_debug_dir; + +#define setsda(bd, val) ((bd)->setsda((bd)->data, val)) +#define setscl(bd, val) ((bd)->setscl((bd)->data, val)) +#define getsda(bd) ((bd)->getsda((bd)->data)) +#define getscl(bd) ((bd)->getscl((bd)->data)) + +#define WIRE_ATTRIBUTE(wire) \ +static int fops_##wire##_get(void *data, u64 *val) \ +{ \ + struct i2c_gpio_private_data *priv = data; \ + \ + i2c_lock_bus(&priv->adap, I2C_LOCK_ROOT_ADAPTER); \ + *val = get##wire(&priv->bit_data); \ + i2c_unlock_bus(&priv->adap, I2C_LOCK_ROOT_ADAPTER); \ + return 0; \ +} \ +static int fops_##wire##_set(void *data, u64 val) \ +{ \ + struct i2c_gpio_private_data *priv = data; \ + \ + i2c_lock_bus(&priv->adap, I2C_LOCK_ROOT_ADAPTER); \ + set##wire(&priv->bit_data, val); \ + i2c_unlock_bus(&priv->adap, I2C_LOCK_ROOT_ADAPTER); \ + return 0; \ +} \ +DEFINE_DEBUGFS_ATTRIBUTE(fops_##wire, fops_##wire##_get, fops_##wire##_set, "%llu\n") + +WIRE_ATTRIBUTE(scl); +WIRE_ATTRIBUTE(sda); + +static void i2c_gpio_incomplete_transfer(struct i2c_gpio_private_data *priv, + u32 pattern, u8 pattern_size) +{ + struct i2c_algo_bit_data *bit_data = &priv->bit_data; + int i; + + i2c_lock_bus(&priv->adap, I2C_LOCK_ROOT_ADAPTER); + + /* START condition */ + setsda(bit_data, 0); + udelay(bit_data->udelay); + + /* Send pattern, request ACK, don't send STOP */ + for (i = pattern_size - 1; i >= 0; i--) { + setscl(bit_data, 0); + udelay(bit_data->udelay / 2); + setsda(bit_data, (pattern >> i) & 1); + udelay((bit_data->udelay + 1) / 2); + setscl(bit_data, 1); + udelay(bit_data->udelay); + } + + i2c_unlock_bus(&priv->adap, I2C_LOCK_ROOT_ADAPTER); +} + +static int fops_incomplete_addr_phase_set(void *data, u64 addr) +{ + struct i2c_gpio_private_data *priv = data; + u32 pattern; + + if (addr > 0x7f) + return -EINVAL; + + /* ADDR (7 bit) + RD (1 bit) + Client ACK, keep SDA hi (1 bit) */ + pattern = (addr << 2) | 3; + + i2c_gpio_incomplete_transfer(priv, pattern, 9); + + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(fops_incomplete_addr_phase, NULL, fops_incomplete_addr_phase_set, "%llu\n"); + +static int fops_incomplete_write_byte_set(void *data, u64 addr) +{ + struct i2c_gpio_private_data *priv = data; + u32 pattern; + + if (addr > 0x7f) + return -EINVAL; + + /* ADDR (7 bit) + WR (1 bit) + Client ACK (1 bit) */ + pattern = (addr << 2) | 1; + /* 0x00 (8 bit) + Client ACK, keep SDA hi (1 bit) */ + pattern = (pattern << 9) | 1; + + i2c_gpio_incomplete_transfer(priv, pattern, 18); + + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(fops_incomplete_write_byte, NULL, fops_incomplete_write_byte_set, "%llu\n"); + +static void i2c_gpio_fault_injector_init(struct platform_device *pdev) +{ + struct i2c_gpio_private_data *priv = platform_get_drvdata(pdev); + + /* + * If there will be a debugfs-dir per i2c adapter somewhen, put the + * 'fault-injector' dir there. Until then, we have a global dir with + * all adapters as subdirs. + */ + if (!i2c_gpio_debug_dir) { + i2c_gpio_debug_dir = debugfs_create_dir("i2c-fault-injector", NULL); + if (!i2c_gpio_debug_dir) + return; + } + + priv->debug_dir = debugfs_create_dir(pdev->name, i2c_gpio_debug_dir); + if (!priv->debug_dir) + return; + + debugfs_create_file_unsafe("scl", 0600, priv->debug_dir, priv, &fops_scl); + debugfs_create_file_unsafe("sda", 0600, priv->debug_dir, priv, &fops_sda); + debugfs_create_file_unsafe("incomplete_address_phase", 0200, priv->debug_dir, + priv, &fops_incomplete_addr_phase); + debugfs_create_file_unsafe("incomplete_write_byte", 0200, priv->debug_dir, + priv, &fops_incomplete_write_byte); +} + +static void i2c_gpio_fault_injector_exit(struct platform_device *pdev) +{ + struct i2c_gpio_private_data *priv = platform_get_drvdata(pdev); + + debugfs_remove_recursive(priv->debug_dir); +} +#else +static inline void i2c_gpio_fault_injector_init(struct platform_device *pdev) {} +static inline void i2c_gpio_fault_injector_exit(struct platform_device *pdev) {} +#endif /* CONFIG_I2C_GPIO_FAULT_INJECTOR*/ + +static void of_i2c_gpio_get_props(struct device_node *np, + struct i2c_gpio_platform_data *pdata) +{ + u32 reg; + + of_property_read_u32(np, "i2c-gpio,delay-us", &pdata->udelay); + + if (!of_property_read_u32(np, "i2c-gpio,timeout-ms", ®)) + pdata->timeout = msecs_to_jiffies(reg); + + pdata->sda_is_open_drain = + of_property_read_bool(np, "i2c-gpio,sda-open-drain"); + pdata->scl_is_open_drain = + of_property_read_bool(np, "i2c-gpio,scl-open-drain"); + pdata->scl_is_output_only = + of_property_read_bool(np, "i2c-gpio,scl-output-only"); +} + +static struct gpio_desc *i2c_gpio_get_desc(struct device *dev, + const char *con_id, + unsigned int index, + enum gpiod_flags gflags) +{ + struct gpio_desc *retdesc; + int ret; + + retdesc = devm_gpiod_get(dev, con_id, gflags); + if (!IS_ERR(retdesc)) { + dev_dbg(dev, "got GPIO from name %s\n", con_id); + return retdesc; + } + + retdesc = devm_gpiod_get_index(dev, NULL, index, gflags); + if (!IS_ERR(retdesc)) { + dev_dbg(dev, "got GPIO from index %u\n", index); + return retdesc; + } + + ret = PTR_ERR(retdesc); + + /* FIXME: hack in the old code, is this really necessary? */ + if (ret == -EINVAL) + retdesc = ERR_PTR(-EPROBE_DEFER); + + /* This happens if the GPIO driver is not yet probed, let's defer */ + if (ret == -ENOENT) + retdesc = ERR_PTR(-EPROBE_DEFER); + + if (PTR_ERR(retdesc) != -EPROBE_DEFER) + dev_err(dev, "error trying to get descriptor: %d\n", ret); + + return retdesc; +} + +static int i2c_gpio_probe(struct platform_device *pdev) +{ + struct i2c_gpio_private_data *priv; + struct i2c_gpio_platform_data *pdata; + struct i2c_algo_bit_data *bit_data; + struct i2c_adapter *adap; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + enum gpiod_flags gflags; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + adap = &priv->adap; + bit_data = &priv->bit_data; + pdata = &priv->pdata; + + if (np) { + of_i2c_gpio_get_props(np, pdata); + } else { + /* + * If all platform data settings are zero it is OK + * to not provide any platform data from the board. + */ + if (dev_get_platdata(dev)) + memcpy(pdata, dev_get_platdata(dev), sizeof(*pdata)); + } + + /* + * First get the GPIO pins; if it fails, we'll defer the probe. + * If the SDA line is marked from platform data or device tree as + * "open drain" it means something outside of our control is making + * this line being handled as open drain, and we should just handle + * it as any other output. Else we enforce open drain as this is + * required for an I2C bus. + */ + if (pdata->sda_is_open_drain) + gflags = GPIOD_OUT_HIGH; + else + gflags = GPIOD_OUT_HIGH_OPEN_DRAIN; + priv->sda = i2c_gpio_get_desc(dev, "sda", 0, gflags); + if (IS_ERR(priv->sda)) + return PTR_ERR(priv->sda); + + /* + * If the SCL line is marked from platform data or device tree as + * "open drain" it means something outside of our control is making + * this line being handled as open drain, and we should just handle + * it as any other output. Else we enforce open drain as this is + * required for an I2C bus. + */ + if (pdata->scl_is_open_drain) + gflags = GPIOD_OUT_HIGH; + else + gflags = GPIOD_OUT_HIGH_OPEN_DRAIN; + priv->scl = i2c_gpio_get_desc(dev, "scl", 1, gflags); + if (IS_ERR(priv->scl)) + return PTR_ERR(priv->scl); + + if (gpiod_cansleep(priv->sda) || gpiod_cansleep(priv->scl)) + dev_warn(dev, "Slow GPIO pins might wreak havoc into I2C/SMBus bus timing"); + + bit_data->setsda = i2c_gpio_setsda_val; + bit_data->setscl = i2c_gpio_setscl_val; + + if (!pdata->scl_is_output_only) + bit_data->getscl = i2c_gpio_getscl; + bit_data->getsda = i2c_gpio_getsda; + + if (pdata->udelay) + bit_data->udelay = pdata->udelay; + else if (pdata->scl_is_output_only) + bit_data->udelay = 50; /* 10 kHz */ + else + bit_data->udelay = 5; /* 100 kHz */ + + if (pdata->timeout) + bit_data->timeout = pdata->timeout; + else + bit_data->timeout = HZ / 10; /* 100 ms */ + + bit_data->data = priv; + + adap->owner = THIS_MODULE; + if (np) + strlcpy(adap->name, dev_name(dev), sizeof(adap->name)); + else + snprintf(adap->name, sizeof(adap->name), "i2c-gpio%d", pdev->id); + + adap->algo_data = bit_data; + adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; + adap->dev.parent = dev; + adap->dev.of_node = np; + + adap->nr = pdev->id; + ret = wb_i2c_bit_add_numbered_bus(adap); + if (ret) + return ret; + + platform_set_drvdata(pdev, priv); + + /* + * FIXME: using global GPIO numbers is not helpful. If/when we + * get accessors to get the actual name of the GPIO line, + * from the descriptor, then provide that instead. + */ + dev_info(dev, "using lines %u (SDA) and %u (SCL%s)\n", + desc_to_gpio(priv->sda), desc_to_gpio(priv->scl), + pdata->scl_is_output_only + ? ", no clock stretching" : ""); + + i2c_gpio_fault_injector_init(pdev); + + return 0; +} + +static int i2c_gpio_remove(struct platform_device *pdev) +{ + struct i2c_gpio_private_data *priv; + struct i2c_adapter *adap; + + i2c_gpio_fault_injector_exit(pdev); + + priv = platform_get_drvdata(pdev); + adap = &priv->adap; + + i2c_del_adapter(adap); + + return 0; +} + +#if defined(CONFIG_OF) +static const struct of_device_id i2c_gpio_dt_ids[] = { + { .compatible = "wb-i2c-gpio", }, + { /* sentinel */ } +}; + +MODULE_DEVICE_TABLE(of, i2c_gpio_dt_ids); +#endif + +static struct platform_driver i2c_gpio_driver = { + .driver = { + .name = "wb-i2c-gpio", + .of_match_table = of_match_ptr(i2c_gpio_dt_ids), + }, + .probe = i2c_gpio_probe, + .remove = i2c_gpio_remove, +}; + +static int __init i2c_gpio_init(void) +{ + int ret; + + ret = platform_driver_register(&i2c_gpio_driver); + if (ret) + printk(KERN_ERR "i2c-gpio: probe failed: %d\n", ret); + + return ret; +} +subsys_initcall(i2c_gpio_init); + +static void __exit i2c_gpio_exit(void) +{ + platform_driver_unregister(&i2c_gpio_driver); +} +module_exit(i2c_gpio_exit); + +MODULE_AUTHOR("support"); +MODULE_DESCRIPTION("Platform-independent bitbanging I2C driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:i2c-gpio"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_i2c_gpio_device.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_i2c_gpio_device.c new file mode 100644 index 000000000000..5cf949d70ef8 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_i2c_gpio_device.c @@ -0,0 +1,110 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static int gpio_sda = 17; +module_param(gpio_sda, int, S_IRUGO | S_IWUSR); + +static int gpio_scl = 1; +module_param(gpio_scl, int, S_IRUGO | S_IWUSR); + +static int gpio_udelay = 2; +module_param(gpio_udelay, int, S_IRUGO | S_IWUSR); + +static int g_wb_i2c_gpio_device_debug = 0; +static int g_wb_i2c_gpio_device_error = 0; + +module_param(g_wb_i2c_gpio_device_debug, int, S_IRUGO | S_IWUSR); +module_param(g_wb_i2c_gpio_device_error, int, S_IRUGO | S_IWUSR); + +#define WB_I2C_GPIO_DEVICE_VERBOSE(fmt, args...) do { \ + if (g_wb_i2c_gpio_device_debug) { \ + printk(KERN_INFO "[WB_I2C_GPIO_DEVICE][VER][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +#define WB_I2C_GPIO_DEVICE_ERROR(fmt, args...) do { \ + if (g_wb_i2c_gpio_device_error) { \ + printk(KERN_ERR "[WB_I2C_GPIO_DEVICE][ERR][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +/****************** i2c adapter with gpio ***********************/ +static struct i2c_gpio_platform_data i2c_pdata = { + .udelay = 2, + .scl_is_output_only = 0, + .sda_is_open_drain = 0, + .scl_is_open_drain = 0, +}; + +static void i2c_gpio_release(struct device *dev) +{ + return; +} + +static struct platform_device wb_i2c_gpio_device = { + .name = "wb-i2c-gpio", + .id = -1, + .num_resources = 0, + .resource = NULL, + .dev = { + .platform_data = &i2c_pdata, + .release = i2c_gpio_release, + }, +}; + +/* + * i2c + */ +static struct gpiod_lookup_table wb_i2c_gpio_table = { + .dev_id = "wb-i2c-gpio", + .table = { + GPIO_LOOKUP_IDX("wb_gpio_d1500", 17, NULL, 0, + GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN), + GPIO_LOOKUP_IDX("wb_gpio_d1500", 1, NULL, 1, + GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN), + }, +}; + +static int __init wb_i2c_gpio_device_init(void) +{ + int err; + + WB_I2C_GPIO_DEVICE_VERBOSE("wb_i2c_gpio_device_init enter!\n"); + wb_i2c_gpio_table.table[0].chip_hwnum = gpio_sda; + wb_i2c_gpio_table.table[1].chip_hwnum = gpio_scl; + i2c_pdata.udelay = gpio_udelay; + gpiod_add_lookup_table(&wb_i2c_gpio_table); + + err = platform_device_register(&wb_i2c_gpio_device); + if (err < 0) { + printk(KERN_ERR "register i2c gpio device fail(%d). \n", err); + gpiod_remove_lookup_table(&wb_i2c_gpio_table); + return -1; + } + return 0; +} + +static void __exit wb_i2c_gpio_device_exit(void) +{ + WB_I2C_GPIO_DEVICE_VERBOSE("wb_i2c_gpio_device_exit enter!\n"); + platform_device_unregister(&wb_i2c_gpio_device); + gpiod_remove_lookup_table(&wb_i2c_gpio_table); +} + +module_init(wb_i2c_gpio_device_init); +module_exit(wb_i2c_gpio_device_exit); +MODULE_DESCRIPTION("I2C GPIO Devices"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("support"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_i2c_i801.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_i2c_i801.c new file mode 100644 index 000000000000..a733c115487e --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_i2c_i801.c @@ -0,0 +1,2114 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + Copyright (c) 1998 - 2002 Frodo Looijaard , + Philip Edelbrock , and Mark D. Studebaker + + Copyright (C) 2007 - 2014 Jean Delvare + Copyright (C) 2010 Intel Corporation, + David Woodhouse + +*/ + +/* + * Supports the following Intel I/O Controller Hubs (ICH): + * + * I/O Block I2C + * region SMBus Block proc. block + * Chip name PCI ID size PEC buffer call read + * --------------------------------------------------------------------------- + * 82801AA (ICH) 0x2413 16 no no no no + * 82801AB (ICH0) 0x2423 16 no no no no + * 82801BA (ICH2) 0x2443 16 no no no no + * 82801CA (ICH3) 0x2483 32 soft no no no + * 82801DB (ICH4) 0x24c3 32 hard yes no no + * 82801E (ICH5) 0x24d3 32 hard yes yes yes + * 6300ESB 0x25a4 32 hard yes yes yes + * 82801F (ICH6) 0x266a 32 hard yes yes yes + * 6310ESB/6320ESB 0x269b 32 hard yes yes yes + * 82801G (ICH7) 0x27da 32 hard yes yes yes + * 82801H (ICH8) 0x283e 32 hard yes yes yes + * 82801I (ICH9) 0x2930 32 hard yes yes yes + * EP80579 (Tolapai) 0x5032 32 hard yes yes yes + * ICH10 0x3a30 32 hard yes yes yes + * ICH10 0x3a60 32 hard yes yes yes + * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes + * 6 Series (PCH) 0x1c22 32 hard yes yes yes + * Patsburg (PCH) 0x1d22 32 hard yes yes yes + * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes + * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes + * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes + * DH89xxCC (PCH) 0x2330 32 hard yes yes yes + * Panther Point (PCH) 0x1e22 32 hard yes yes yes + * Lynx Point (PCH) 0x8c22 32 hard yes yes yes + * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes + * Avoton (SOC) 0x1f3c 32 hard yes yes yes + * Wellsburg (PCH) 0x8d22 32 hard yes yes yes + * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes + * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes + * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes + * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes + * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes + * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes + * BayTrail (SOC) 0x0f12 32 hard yes yes yes + * Braswell (SOC) 0x2292 32 hard yes yes yes + * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes + * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes + * DNV (SOC) 0x19df 32 hard yes yes yes + * Emmitsburg (PCH) 0x1bc9 32 hard yes yes yes + * Broxton (SOC) 0x5ad4 32 hard yes yes yes + * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes + * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes + * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes + * Gemini Lake (SOC) 0x31d4 32 hard yes yes yes + * Cannon Lake-H (PCH) 0xa323 32 hard yes yes yes + * Cannon Lake-LP (PCH) 0x9da3 32 hard yes yes yes + * Cedar Fork (PCH) 0x18df 32 hard yes yes yes + * Ice Lake-LP (PCH) 0x34a3 32 hard yes yes yes + * Comet Lake (PCH) 0x02a3 32 hard yes yes yes + * Comet Lake-H (PCH) 0x06a3 32 hard yes yes yes + * Elkhart Lake (PCH) 0x4b23 32 hard yes yes yes + * Tiger Lake-LP (PCH) 0xa0a3 32 hard yes yes yes + * Tiger Lake-H (PCH) 0x43a3 32 hard yes yes yes + * Jasper Lake (SOC) 0x4da3 32 hard yes yes yes + * Comet Lake-V (PCH) 0xa3a3 32 hard yes yes yes + * Alder Lake-S (PCH) 0x7aa3 32 hard yes yes yes + * + * Features supported by this driver: + * Software PEC no + * Hardware PEC yes + * Block buffer yes + * Block process call transaction yes + * I2C block read transaction yes (doesn't use the block buffer) + * Slave mode no + * SMBus Host Notify yes + * Interrupt processing yes + * + * See the file Documentation/i2c/busses/i2c-i801.rst for details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI +#include +#include +#endif + +#define mem_clear(data, size) memset((data), 0, (size)) + +/* I801 SMBus address offsets */ +#define SMBHSTSTS(p) (0 + (p)->smba) +#define SMBHSTCNT(p) (2 + (p)->smba) +#define SMBHSTCMD(p) (3 + (p)->smba) +#define SMBHSTADD(p) (4 + (p)->smba) +#define SMBHSTDAT0(p) (5 + (p)->smba) +#define SMBHSTDAT1(p) (6 + (p)->smba) +#define SMBBLKDAT(p) (7 + (p)->smba) +#define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */ +#define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */ +#define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */ +#define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */ +#define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */ +#define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */ +#define SMBPINCTL(p) (15 + (p)->smba) /* SMBus Pin Control Register */ + +/* PCI Address Constants */ +#define SMBBAR 4 +#define SMBPCICTL 0x004 +#define SMBPCISTS 0x006 +#define SMBHSTCFG 0x040 +#define TCOBASE 0x050 +#define TCOCTL 0x054 + +#define SBREG_BAR 0x10 +#define SBREG_SMBCTRL 0xc6000c +#define SBREG_SMBCTRL_DNV 0xcf000c + +/* Host status bits for SMBPCISTS */ +#define SMBPCISTS_INTS BIT(3) + +/* Control bits for SMBPCICTL */ +#define SMBPCICTL_INTDIS BIT(10) + +/* Host configuration bits for SMBHSTCFG */ +#define SMBHSTCFG_HST_EN BIT(0) +#define SMBHSTCFG_SMB_SMI_EN BIT(1) +#define SMBHSTCFG_I2C_EN BIT(2) +#define SMBHSTCFG_SSRESET BIT(3) +#define SSRESET_SLEEP_TIME 1 /* 1us */ +#define SSRESET_RETRY_TIME (1000 / SSRESET_SLEEP_TIME) + +/* Pin status for SMBPINCTL */ +#define SMBPINCTL_CLK_STS 1 /* bit0 SMBCLK_CUR_STS*/ +#define SMBPINCTL_SDA_STS 2 /* bit1 SMBDATA_CUR_STS*/ +#define SMBPINCTL_CLK_CTL 4 /* bit2 SMBCLK_CTL */ + +#define SMBHSTCFG_SPD_WD BIT(4) + +/* TCO configuration bits for TCOCTL */ +#define TCOCTL_EN BIT(8) + +/* Auxiliary status register bits, ICH4+ only */ +#define SMBAUXSTS_CRCE BIT(0) +#define SMBAUXSTS_STCO BIT(1) + +/* Auxiliary control register bits, ICH4+ only */ +#define SMBAUXCTL_CRC BIT(0) +#define SMBAUXCTL_E32B BIT(1) + +/* Other settings */ +#define MAX_RETRIES 400 + +/* I801 command constants */ +#define I801_QUICK 0x00 +#define I801_BYTE 0x04 +#define I801_BYTE_DATA 0x08 +#define I801_WORD_DATA 0x0C +#define I801_PROC_CALL 0x10 /* unimplemented */ +#define I801_BLOCK_DATA 0x14 +#define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */ +#define I801_BLOCK_PROC_CALL 0x1C + +/* I801 Host Control register bits */ +#define SMBHSTCNT_INTREN BIT(0) +#define SMBHSTCNT_KILL BIT(1) +#define SMBHSTCNT_LAST_BYTE BIT(5) +#define SMBHSTCNT_START BIT(6) +#define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */ + +/* I801 Hosts Status register bits */ +#define SMBHSTSTS_BYTE_DONE BIT(7) +#define SMBHSTSTS_INUSE_STS BIT(6) +#define SMBHSTSTS_SMBALERT_STS BIT(5) +#define SMBHSTSTS_FAILED BIT(4) +#define SMBHSTSTS_BUS_ERR BIT(3) +#define SMBHSTSTS_DEV_ERR BIT(2) +#define SMBHSTSTS_INTR BIT(1) +#define SMBHSTSTS_HOST_BUSY BIT(0) + +/* Host Notify Status register bits */ +#define SMBSLVSTS_HST_NTFY_STS BIT(0) + +/* Host Notify Command register bits */ +#define SMBSLVCMD_HST_NTFY_INTREN BIT(0) + +#define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \ + SMBHSTSTS_DEV_ERR) + +#define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \ + STATUS_ERROR_FLAGS) + +/* Older devices have their ID defined in */ +#define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS 0x02a3 +#define PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS 0x06a3 +#define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12 +#define PCI_DEVICE_ID_INTEL_CDF_SMBUS 0x18df +#define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df +#define PCI_DEVICE_ID_INTEL_EBG_SMBUS 0x1bc9 +#define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22 +#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22 +/* Patsburg also has three 'Integrated Device Function' SMBus controllers */ +#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70 +#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71 +#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72 +#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22 +#define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c +#define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292 +#define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330 +#define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0 +#define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4 +#define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS 0x34a3 +#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 +#define PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS 0x43a3 +#define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS 0x4b23 +#define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS 0x4da3 +#define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4 +#define PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS 0x7aa3 +#define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22 +#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2 +#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22 +#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d +#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e +#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f +#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22 +#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23 +#define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS 0x9da3 +#define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS 0xa0a3 +#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123 +#define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3 +#define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223 +#define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3 +#define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS 0xa323 +#define PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS 0xa3a3 + +struct i801_mux_config { + char *gpio_chip; + unsigned values[3]; + int n_values; + unsigned classes[3]; + unsigned gpios[2]; /* Relative to gpio_chip->base */ + int n_gpios; +}; + +struct i801_priv { + struct i2c_adapter adapter; + unsigned long smba; + unsigned char original_hstcfg; + unsigned char original_slvcmd; + struct pci_dev *pci_dev; + unsigned int features; + + /* isr processing */ + wait_queue_head_t waitq; + u8 status; + + /* Command state used by isr for byte-by-byte block transactions */ + u8 cmd; + bool is_read; + int count; + int len; + u8 *data; + +#if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI + const struct i801_mux_config *mux_drvdata; + struct platform_device *mux_pdev; + struct gpiod_lookup_table *lookup; +#endif + struct platform_device *tco_pdev; + + /* + * If set to true the host controller registers are reserved for + * ACPI AML use. Protected by acpi_lock. + */ + bool acpi_reserved; + struct mutex acpi_lock; +}; + +#define FEATURE_SMBUS_PEC BIT(0) +#define FEATURE_BLOCK_BUFFER BIT(1) +#define FEATURE_BLOCK_PROC BIT(2) +#define FEATURE_I2C_BLOCK_READ BIT(3) +#define FEATURE_IRQ BIT(4) +#define FEATURE_HOST_NOTIFY BIT(5) +/* Not really a feature, but it's convenient to handle it as such */ +#define FEATURE_IDF BIT(15) +#define FEATURE_TCO_SPT BIT(16) +#define FEATURE_TCO_CNL BIT(17) + +static const char *i801_feature_names[] = { + "SMBus PEC", + "Block buffer", + "Block process call", + "I2C block read", + "Interrupt", + "SMBus Host Notify", +}; + +static unsigned int disable_features; +module_param(disable_features, uint, S_IRUGO | S_IWUSR); +MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n" + "\t\t 0x01 disable SMBus PEC\n" + "\t\t 0x02 disable the block buffer\n" + "\t\t 0x08 disable the I2C block read functionality\n" + "\t\t 0x10 don't use interrupts\n" + "\t\t 0x20 disable SMBus Host Notify "); + +static void i801_setscl(struct i801_priv *priv, unsigned int level) +{ + int pin_status; + pin_status = inb_p(SMBPINCTL(priv)); + if (level == 0) { + pin_status &= (~SMBPINCTL_CLK_CTL); + } + else { + pin_status |= SMBPINCTL_CLK_CTL; + } + outb_p(pin_status, SMBPINCTL(priv)); + return; +} + +static void i801_i2c_unblock(struct i801_priv *priv) +{ + int i; + for (i = 0; i < 10; i++) { + i801_setscl(priv, 0); + udelay(5); + i801_setscl(priv, 1); + udelay(5); + } + return; +} + +static int i801_check_i2c_unblock(struct i801_priv *priv) +{ + int pin_status; + + pin_status = inb_p(SMBPINCTL(priv)); + if ( (!(pin_status & SMBPINCTL_SDA_STS) ) && (pin_status & SMBPINCTL_CLK_STS) ) { + dev_dbg(&priv->pci_dev->dev, "SDA is low, send 9 clock to device!\n"); + i801_i2c_unblock(priv); + } + return 0; +} + +static void i801_do_reset(struct i801_priv *priv) +{ + unsigned char tmp; + unsigned int retry_count = 0; + + pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &tmp); + tmp |= SMBHSTCFG_SSRESET; + pci_write_config_byte(priv->pci_dev, SMBHSTCFG, tmp); + pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &tmp); + + while( ((tmp & SMBHSTCFG_SSRESET) != 0) && (retry_count < SSRESET_RETRY_TIME)) { + usleep_range(SSRESET_SLEEP_TIME, SSRESET_SLEEP_TIME + 1); + retry_count++; + pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &tmp); + } + + return ; +} + +static int i801_check_i2c_scl(struct i801_priv *priv) +{ + int pin_status; + + pin_status = inb_p(SMBPINCTL(priv)); + if ( (pin_status & SMBPINCTL_SDA_STS) && (pin_status & SMBPINCTL_CLK_STS) ) { + return 0; + } + + dev_dbg(&priv->pci_dev->dev, "SDA or SCL is low, begin to reset SMBus adapter, pin_status: 0x%x\n",pin_status); + i801_do_reset(priv); + pin_status = inb_p(SMBPINCTL(priv)); + if ( (pin_status & SMBPINCTL_SDA_STS) && (pin_status & SMBPINCTL_CLK_STS) ) { + return 0; + } + dev_warn(&priv->pci_dev->dev, "SDA or SCL is low.pin_status:0x%x\n",pin_status); + return -1; +} + +/* Make sure the SMBus host is ready to start transmitting. + Return 0 if it is, -EBUSY if it is not. */ +static int i801_check_pre(struct i801_priv *priv) +{ + int status; + + i801_check_i2c_unblock(priv); + + if (i801_check_i2c_scl(priv)) { + return -EIO; + } + + status = inb_p(SMBHSTSTS(priv)); + if (status & SMBHSTSTS_HOST_BUSY) { + dev_dbg(&priv->pci_dev->dev, "SMBus is busy, begin to reset SMBus adapter!\n"); + + i801_do_reset(priv); + + status = inb_p(SMBHSTSTS(priv)); + if (status & SMBHSTSTS_HOST_BUSY) { + dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n"); + return -EBUSY; + } + } + + status &= STATUS_FLAGS; + if (status) { + dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n", + status); + outb_p(status, SMBHSTSTS(priv)); + status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS; + if (status) { + dev_err(&priv->pci_dev->dev, + "Failed clearing status flags (%02x)\n", + status); + return -EBUSY; + } + } + + /* + * Clear CRC status if needed. + * During normal operation, i801_check_post() takes care + * of it after every operation. We do it here only in case + * the hardware was already in this state when the driver + * started. + */ + if (priv->features & FEATURE_SMBUS_PEC) { + status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE; + if (status) { + dev_dbg(&priv->pci_dev->dev, + "Clearing aux status flags (%02x)\n", status); + outb_p(status, SMBAUXSTS(priv)); + status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE; + if (status) { + dev_err(&priv->pci_dev->dev, + "Failed clearing aux status flags (%02x)\n", + status); + return -EBUSY; + } + } + } + + return 0; +} + +/* + * Convert the status register to an error code, and clear it. + * Note that status only contains the bits we want to clear, not the + * actual register value. + */ +static int i801_check_post(struct i801_priv *priv, int status) +{ + int result = 0; + + /* + * If the SMBus is still busy, we give up + * Note: This timeout condition only happens when using polling + * transactions. For interrupt operation, NAK/timeout is indicated by + * DEV_ERR. + */ + if (unlikely(status < 0)) { + dev_err(&priv->pci_dev->dev, "Transaction timeout\n"); + /* try to stop the current command */ + dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n"); + outb_p(SMBHSTCNT_KILL, SMBHSTCNT(priv)); + usleep_range(1000, 2000); + outb_p(0, SMBHSTCNT(priv)); + + /* Check if it worked */ + status = inb_p(SMBHSTSTS(priv)); + if ((status & SMBHSTSTS_HOST_BUSY) || + !(status & SMBHSTSTS_FAILED)) + dev_err(&priv->pci_dev->dev, + "Failed terminating the transaction\n"); + outb_p(STATUS_FLAGS, SMBHSTSTS(priv)); + return -ETIMEDOUT; + } + + if (status & SMBHSTSTS_FAILED) { + result = -EIO; + dev_err(&priv->pci_dev->dev, "Transaction failed\n"); + } + if (status & SMBHSTSTS_DEV_ERR) { + /* + * This may be a PEC error, check and clear it. + * + * AUXSTS is handled differently from HSTSTS. + * For HSTSTS, i801_isr() or i801_wait_intr() + * has already cleared the error bits in hardware, + * and we are passed a copy of the original value + * in "status". + * For AUXSTS, the hardware register is left + * for us to handle here. + * This is asymmetric, slightly iffy, but safe, + * since all this code is serialized and the CRCE + * bit is harmless as long as it's cleared before + * the next operation. + */ + if ((priv->features & FEATURE_SMBUS_PEC) && + (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) { + outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv)); + result = -EBADMSG; + dev_dbg(&priv->pci_dev->dev, "PEC error\n"); + } else { + result = -ENXIO; + dev_dbg(&priv->pci_dev->dev, "No response\n"); + } + } + if (status & SMBHSTSTS_BUS_ERR) { + result = -EAGAIN; + dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n"); + } + + /* Clear status flags except BYTE_DONE, to be cleared by caller */ + outb_p(status, SMBHSTSTS(priv)); + + return result; +} + +/* Wait for BUSY being cleared and either INTR or an error flag being set */ +static int i801_wait_intr(struct i801_priv *priv) +{ + int timeout = 0; + int status; + + /* We will always wait for a fraction of a second! */ + do { + usleep_range(250, 500); + status = inb_p(SMBHSTSTS(priv)); + } while (((status & SMBHSTSTS_HOST_BUSY) || + !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) && + (timeout++ < MAX_RETRIES)); + + if (timeout > MAX_RETRIES) { + dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n"); + return -ETIMEDOUT; + } + return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR); +} + +/* Wait for either BYTE_DONE or an error flag being set */ +static int i801_wait_byte_done(struct i801_priv *priv) +{ + int timeout = 0; + int status; + + /* We will always wait for a fraction of a second! */ + do { + usleep_range(250, 500); + status = inb_p(SMBHSTSTS(priv)); + } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) && + (timeout++ < MAX_RETRIES)); + + if (timeout > MAX_RETRIES) { + dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n"); + return -ETIMEDOUT; + } + return status & STATUS_ERROR_FLAGS; +} + +static int i801_transaction(struct i801_priv *priv, int xact) +{ + int status; + int result; + const struct i2c_adapter *adap = &priv->adapter; + + result = i801_check_pre(priv); + if (result < 0) + return result; + + if (priv->features & FEATURE_IRQ) { + outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START, + SMBHSTCNT(priv)); + result = wait_event_timeout(priv->waitq, + (status = priv->status), + adap->timeout); + if (!result) { + status = -ETIMEDOUT; + dev_warn(&priv->pci_dev->dev, + "Timeout waiting for interrupt!\n"); + } + priv->status = 0; + return i801_check_post(priv, status); + } + + /* the current contents of SMBHSTCNT can be overwritten, since PEC, + * SMBSCMD are passed in xact */ + outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv)); + + status = i801_wait_intr(priv); + return i801_check_post(priv, status); +} + +static int i801_block_transaction_by_block(struct i801_priv *priv, + union i2c_smbus_data *data, + char read_write, int command, + int hwpec) +{ + int i, len; + int status; + int xact = hwpec ? SMBHSTCNT_PEC_EN : 0; + + switch (command) { + case I2C_SMBUS_BLOCK_PROC_CALL: + xact |= I801_BLOCK_PROC_CALL; + break; + case I2C_SMBUS_BLOCK_DATA: + xact |= I801_BLOCK_DATA; + break; + default: + return -EOPNOTSUPP; + } + + inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */ + + /* Use 32-byte buffer to process this transaction */ + if (read_write == I2C_SMBUS_WRITE) { + len = data->block[0]; + outb_p(len, SMBHSTDAT0(priv)); + for (i = 0; i < len; i++) + outb_p(data->block[i+1], SMBBLKDAT(priv)); + } + + status = i801_transaction(priv, xact); + if (status) + return status; + + if (read_write == I2C_SMBUS_READ || + command == I2C_SMBUS_BLOCK_PROC_CALL) { + len = inb_p(SMBHSTDAT0(priv)); + if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) + return -EPROTO; + + data->block[0] = len; + for (i = 0; i < len; i++) + data->block[i + 1] = inb_p(SMBBLKDAT(priv)); + } + return 0; +} + +static void i801_isr_byte_done(struct i801_priv *priv) +{ + if (priv->is_read) { + /* For SMBus block reads, length is received with first byte */ + if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) && + (priv->count == 0)) { + priv->len = inb_p(SMBHSTDAT0(priv)); + if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) { + dev_err(&priv->pci_dev->dev, + "Illegal SMBus block read size %d\n", + priv->len); + /* FIXME: Recover */ + priv->len = I2C_SMBUS_BLOCK_MAX; + } else { + dev_dbg(&priv->pci_dev->dev, + "SMBus block read size is %d\n", + priv->len); + } + priv->data[-1] = priv->len; + } + + /* Read next byte */ + if (priv->count < priv->len) + priv->data[priv->count++] = inb(SMBBLKDAT(priv)); + else + dev_dbg(&priv->pci_dev->dev, + "Discarding extra byte on block read\n"); + + /* Set LAST_BYTE for last byte of read transaction */ + if (priv->count == priv->len - 1) + outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE, + SMBHSTCNT(priv)); + } else if (priv->count < priv->len - 1) { + /* Write next byte, except for IRQ after last byte */ + outb_p(priv->data[++priv->count], SMBBLKDAT(priv)); + } + + /* Clear BYTE_DONE to continue with next byte */ + outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); +} + +static irqreturn_t i801_host_notify_isr(struct i801_priv *priv) +{ + unsigned short addr; + + addr = inb_p(SMBNTFDADD(priv)) >> 1; + + /* + * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba) + * always returns 0. Our current implementation doesn't provide + * data, so we just ignore it. + */ + i2c_handle_smbus_host_notify(&priv->adapter, addr); + + /* clear Host Notify bit and return */ + outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); + return IRQ_HANDLED; +} + +/* + * There are three kinds of interrupts: + * + * 1) i801 signals transaction completion with one of these interrupts: + * INTR - Success + * DEV_ERR - Invalid command, NAK or communication timeout + * BUS_ERR - SMI# transaction collision + * FAILED - transaction was canceled due to a KILL request + * When any of these occur, update ->status and wake up the waitq. + * ->status must be cleared before kicking off the next transaction. + * + * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt + * occurs for each byte of a byte-by-byte to prepare the next byte. + * + * 3) Host Notify interrupts + */ +static irqreturn_t i801_isr(int irq, void *dev_id) +{ + struct i801_priv *priv = dev_id; + u16 pcists; + u8 status; + + /* Confirm this is our interrupt */ + pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists); + if (!(pcists & SMBPCISTS_INTS)) + return IRQ_NONE; + + if (priv->features & FEATURE_HOST_NOTIFY) { + status = inb_p(SMBSLVSTS(priv)); + if (status & SMBSLVSTS_HST_NTFY_STS) + return i801_host_notify_isr(priv); + } + + status = inb_p(SMBHSTSTS(priv)); + if (status & SMBHSTSTS_BYTE_DONE) + i801_isr_byte_done(priv); + + /* + * Clear irq sources and report transaction result. + * ->status must be cleared before the next transaction is started. + */ + status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS; + if (status) { + outb_p(status, SMBHSTSTS(priv)); + priv->status = status; + wake_up(&priv->waitq); + } + + return IRQ_HANDLED; +} + +/* + * For "byte-by-byte" block transactions: + * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1 + * I2C read uses cmd=I801_I2C_BLOCK_DATA + */ +static int i801_block_transaction_byte_by_byte(struct i801_priv *priv, + union i2c_smbus_data *data, + char read_write, int command, + int hwpec) +{ + int i, len; + int smbcmd; + int status; + int result; + const struct i2c_adapter *adap = &priv->adapter; + + if (command == I2C_SMBUS_BLOCK_PROC_CALL) + return -EOPNOTSUPP; + + result = i801_check_pre(priv); + if (result < 0) + return result; + + len = data->block[0]; + + if (read_write == I2C_SMBUS_WRITE) { + outb_p(len, SMBHSTDAT0(priv)); + outb_p(data->block[1], SMBBLKDAT(priv)); + } + + if (command == I2C_SMBUS_I2C_BLOCK_DATA && + read_write == I2C_SMBUS_READ) + smbcmd = I801_I2C_BLOCK_DATA; + else + smbcmd = I801_BLOCK_DATA; + + if (priv->features & FEATURE_IRQ) { + priv->is_read = (read_write == I2C_SMBUS_READ); + if (len == 1 && priv->is_read) + smbcmd |= SMBHSTCNT_LAST_BYTE; + priv->cmd = smbcmd | SMBHSTCNT_INTREN; + priv->len = len; + priv->count = 0; + priv->data = &data->block[1]; + + outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv)); + result = wait_event_timeout(priv->waitq, + (status = priv->status), + adap->timeout); + if (!result) { + status = -ETIMEDOUT; + dev_warn(&priv->pci_dev->dev, + "Timeout waiting for interrupt!\n"); + } + priv->status = 0; + return i801_check_post(priv, status); + } + + for (i = 1; i <= len; i++) { + if (i == len && read_write == I2C_SMBUS_READ) + smbcmd |= SMBHSTCNT_LAST_BYTE; + outb_p(smbcmd, SMBHSTCNT(priv)); + + if (i == 1) + outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START, + SMBHSTCNT(priv)); + + status = i801_wait_byte_done(priv); + if (status) + goto exit; + + if (i == 1 && read_write == I2C_SMBUS_READ + && command != I2C_SMBUS_I2C_BLOCK_DATA) { + len = inb_p(SMBHSTDAT0(priv)); + if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { + dev_err(&priv->pci_dev->dev, + "Illegal SMBus block read size %d\n", + len); + /* Recover */ + while (inb_p(SMBHSTSTS(priv)) & + SMBHSTSTS_HOST_BUSY) + outb_p(SMBHSTSTS_BYTE_DONE, + SMBHSTSTS(priv)); + outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv)); + return -EPROTO; + } + data->block[0] = len; + } + + /* Retrieve/store value in SMBBLKDAT */ + if (read_write == I2C_SMBUS_READ) + data->block[i] = inb_p(SMBBLKDAT(priv)); + if (read_write == I2C_SMBUS_WRITE && i+1 <= len) + outb_p(data->block[i+1], SMBBLKDAT(priv)); + + /* signals SMBBLKDAT ready */ + outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); + } + + status = i801_wait_intr(priv); +exit: + return i801_check_post(priv, status); +} + +static int i801_set_block_buffer_mode(struct i801_priv *priv) +{ + outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv)); + if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0) + return -EIO; + return 0; +} + +/* Block transaction function */ +static int i801_block_transaction(struct i801_priv *priv, + union i2c_smbus_data *data, char read_write, + int command, int hwpec) +{ + int result = 0; + unsigned char hostc; + + if (command == I2C_SMBUS_I2C_BLOCK_DATA) { + if (read_write == I2C_SMBUS_WRITE) { + /* set I2C_EN bit in configuration register */ + pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc); + pci_write_config_byte(priv->pci_dev, SMBHSTCFG, + hostc | SMBHSTCFG_I2C_EN); + } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) { + dev_err(&priv->pci_dev->dev, + "I2C block read is unsupported!\n"); + return -EOPNOTSUPP; + } + } + + if (read_write == I2C_SMBUS_WRITE + || command == I2C_SMBUS_I2C_BLOCK_DATA) { + if (data->block[0] < 1) + data->block[0] = 1; + if (data->block[0] > I2C_SMBUS_BLOCK_MAX) + data->block[0] = I2C_SMBUS_BLOCK_MAX; + } else { + data->block[0] = 32; /* max for SMBus block reads */ + } + + /* Experience has shown that the block buffer can only be used for + SMBus (not I2C) block transactions, even though the datasheet + doesn't mention this limitation. */ + if ((priv->features & FEATURE_BLOCK_BUFFER) + && command != I2C_SMBUS_I2C_BLOCK_DATA + && i801_set_block_buffer_mode(priv) == 0) + result = i801_block_transaction_by_block(priv, data, + read_write, + command, hwpec); + else + result = i801_block_transaction_byte_by_byte(priv, data, + read_write, + command, hwpec); + + if (command == I2C_SMBUS_I2C_BLOCK_DATA + && read_write == I2C_SMBUS_WRITE) { + /* restore saved configuration register value */ + pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc); + } + return result; +} + +/* Return negative errno on error. */ +static s32 i801_access(struct i2c_adapter *adap, u16 addr, + unsigned short flags, char read_write, u8 command, + int size, union i2c_smbus_data *data) +{ + int hwpec; + int block = 0; + int ret = 0, xact = 0; + struct i801_priv *priv = i2c_get_adapdata(adap); + + mutex_lock(&priv->acpi_lock); + if (priv->acpi_reserved) { + mutex_unlock(&priv->acpi_lock); + return -EBUSY; + } + + pm_runtime_get_sync(&priv->pci_dev->dev); + + hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC) + && size != I2C_SMBUS_QUICK + && size != I2C_SMBUS_I2C_BLOCK_DATA; + + switch (size) { + case I2C_SMBUS_QUICK: + outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), + SMBHSTADD(priv)); + xact = I801_QUICK; + break; + case I2C_SMBUS_BYTE: + outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), + SMBHSTADD(priv)); + if (read_write == I2C_SMBUS_WRITE) + outb_p(command, SMBHSTCMD(priv)); + xact = I801_BYTE; + break; + case I2C_SMBUS_BYTE_DATA: + outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), + SMBHSTADD(priv)); + outb_p(command, SMBHSTCMD(priv)); + if (read_write == I2C_SMBUS_WRITE) + outb_p(data->byte, SMBHSTDAT0(priv)); + xact = I801_BYTE_DATA; + break; + case I2C_SMBUS_WORD_DATA: + outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), + SMBHSTADD(priv)); + outb_p(command, SMBHSTCMD(priv)); + if (read_write == I2C_SMBUS_WRITE) { + outb_p(data->word & 0xff, SMBHSTDAT0(priv)); + outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); + } + xact = I801_WORD_DATA; + break; + case I2C_SMBUS_BLOCK_DATA: + outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), + SMBHSTADD(priv)); + outb_p(command, SMBHSTCMD(priv)); + block = 1; + break; + case I2C_SMBUS_I2C_BLOCK_DATA: + /* + * NB: page 240 of ICH5 datasheet shows that the R/#W + * bit should be cleared here, even when reading. + * However if SPD Write Disable is set (Lynx Point and later), + * the read will fail if we don't set the R/#W bit. + */ + outb_p(((addr & 0x7f) << 1) | + ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ? + (read_write & 0x01) : 0), + SMBHSTADD(priv)); + if (read_write == I2C_SMBUS_READ) { + /* NB: page 240 of ICH5 datasheet also shows + * that DATA1 is the cmd field when reading */ + outb_p(command, SMBHSTDAT1(priv)); + } else + outb_p(command, SMBHSTCMD(priv)); + block = 1; + break; + case I2C_SMBUS_BLOCK_PROC_CALL: + /* + * Bit 0 of the slave address register always indicate a write + * command. + */ + outb_p((addr & 0x7f) << 1, SMBHSTADD(priv)); + outb_p(command, SMBHSTCMD(priv)); + block = 1; + break; + default: + dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n", + size); + ret = -EOPNOTSUPP; + goto out; + } + + if (hwpec) /* enable/disable hardware PEC */ + outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv)); + else + outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC), + SMBAUXCTL(priv)); + + if (block) + ret = i801_block_transaction(priv, data, read_write, size, + hwpec); + else + ret = i801_transaction(priv, xact); + + /* Some BIOSes don't like it when PEC is enabled at reboot or resume + time, so we forcibly disable it after every transaction. Turn off + E32B for the same reason. */ + if (hwpec || block) + outb_p(inb_p(SMBAUXCTL(priv)) & + ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); + + if (block) + goto out; + if (ret) + goto out; + if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK)) + goto out; + + switch (xact & 0x7f) { + case I801_BYTE: /* Result put in SMBHSTDAT0 */ + case I801_BYTE_DATA: + data->byte = inb_p(SMBHSTDAT0(priv)); + break; + case I801_WORD_DATA: + data->word = inb_p(SMBHSTDAT0(priv)) + + (inb_p(SMBHSTDAT1(priv)) << 8); + break; + } + +out: + pm_runtime_mark_last_busy(&priv->pci_dev->dev); + pm_runtime_put_autosuspend(&priv->pci_dev->dev); + mutex_unlock(&priv->acpi_lock); + return ret; +} + +static u32 i801_func(struct i2c_adapter *adapter) +{ + struct i801_priv *priv = i2c_get_adapdata(adapter); + + return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | + I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | + I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK | + ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) | + ((priv->features & FEATURE_BLOCK_PROC) ? + I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) | + ((priv->features & FEATURE_I2C_BLOCK_READ) ? + I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) | + ((priv->features & FEATURE_HOST_NOTIFY) ? + I2C_FUNC_SMBUS_HOST_NOTIFY : 0); +} + +static void i801_enable_host_notify(struct i2c_adapter *adapter) +{ + struct i801_priv *priv = i2c_get_adapdata(adapter); + + if (!(priv->features & FEATURE_HOST_NOTIFY)) + return; + + if (!(SMBSLVCMD_HST_NTFY_INTREN & priv->original_slvcmd)) + outb_p(SMBSLVCMD_HST_NTFY_INTREN | priv->original_slvcmd, + SMBSLVCMD(priv)); + + /* clear Host Notify bit to allow a new notification */ + outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); +} + +static void i801_disable_host_notify(struct i801_priv *priv) +{ + if (!(priv->features & FEATURE_HOST_NOTIFY)) + return; + + outb_p(priv->original_slvcmd, SMBSLVCMD(priv)); +} + +static const struct i2c_algorithm smbus_algorithm = { + .smbus_xfer = i801_access, + .functionality = i801_func, +}; + +static const struct pci_device_id i801_ids[] = { + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMBUS) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EBG_SMBUS) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS) }, + { 0, } +}; + +MODULE_DEVICE_TABLE(pci, i801_ids); + +#if defined CONFIG_X86 && defined CONFIG_DMI +static unsigned char apanel_addr; + +/* Scan the system ROM for the signature "FJKEYINF" */ +static __init const void __iomem *bios_signature(const void __iomem *bios) +{ + ssize_t offset; + const unsigned char signature[] = "FJKEYINF"; + + for (offset = 0; offset < 0x10000; offset += 0x10) { + if (check_signature(bios + offset, signature, + sizeof(signature)-1)) + return bios + offset; + } + return NULL; +} + +static void __init input_apanel_init(void) +{ + void __iomem *bios; + const void __iomem *p; + + bios = ioremap(0xF0000, 0x10000); /* Can't fail */ + p = bios_signature(bios); + if (p) { + /* just use the first address */ + apanel_addr = readb(p + 8 + 3) >> 1; + } + iounmap(bios); +} + +struct dmi_onboard_device_info { + const char *name; + u8 type; + unsigned short i2c_addr; + const char *i2c_type; +}; + +static const struct dmi_onboard_device_info dmi_devices[] = { + { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" }, + { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" }, + { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" }, +}; + +static void dmi_check_onboard_device(u8 type, const char *name, + struct i2c_adapter *adap) +{ + int i; + struct i2c_board_info info; + + for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) { + /* & ~0x80, ignore enabled/disabled bit */ + if ((type & ~0x80) != dmi_devices[i].type) + continue; + if (strcasecmp(name, dmi_devices[i].name)) + continue; + + mem_clear(&info, sizeof(struct i2c_board_info)); + info.addr = dmi_devices[i].i2c_addr; + strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); + i2c_new_client_device(adap, &info); + break; + } +} + +/* We use our own function to check for onboard devices instead of + dmi_find_device() as some buggy BIOS's have the devices we are interested + in marked as disabled */ +static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap) +{ + int i, count; + + if (dm->type != 10) + return; + + count = (dm->length - sizeof(struct dmi_header)) / 2; + for (i = 0; i < count; i++) { + const u8 *d = (char *)(dm + 1) + (i * 2); + const char *name = ((char *) dm) + dm->length; + u8 type = d[0]; + u8 s = d[1]; + + if (!s) + continue; + s--; + while (s > 0 && name[0]) { + name += strlen(name) + 1; + s--; + } + if (name[0] == 0) /* Bogus string reference */ + continue; + + dmi_check_onboard_device(type, name, adap); + } +} + +/* NOTE: Keep this list in sync with drivers/platform/x86/dell-smo8800.c */ +static const char *const acpi_smo8800_ids[] = { + "SMO8800", + "SMO8801", + "SMO8810", + "SMO8811", + "SMO8820", + "SMO8821", + "SMO8830", + "SMO8831", +}; + +static acpi_status check_acpi_smo88xx_device(acpi_handle obj_handle, + u32 nesting_level, + void *context, + void **return_value) +{ + struct acpi_device_info *info; + acpi_status status; + char *hid; + int i; + + status = acpi_get_object_info(obj_handle, &info); + if (ACPI_FAILURE(status)) + return AE_OK; + + if (!(info->valid & ACPI_VALID_HID)) + goto smo88xx_not_found; + + hid = info->hardware_id.string; + if (!hid) + goto smo88xx_not_found; + + i = match_string(acpi_smo8800_ids, ARRAY_SIZE(acpi_smo8800_ids), hid); + if (i < 0) + goto smo88xx_not_found; + + kfree(info); + + *((bool *)return_value) = true; + return AE_CTRL_TERMINATE; + +smo88xx_not_found: + kfree(info); + return AE_OK; +} + +static bool is_dell_system_with_lis3lv02d(void) +{ + bool found; + const char *vendor; + + vendor = dmi_get_system_info(DMI_SYS_VENDOR); + if (!vendor || strcmp(vendor, "Dell Inc.")) + return false; + + /* + * Check that ACPI device SMO88xx is present and is functioning. + * Function acpi_get_devices() already filters all ACPI devices + * which are not present or are not functioning. + * ACPI device SMO88xx represents our ST microelectronics lis3lv02d + * accelerometer but unfortunately ACPI does not provide any other + * information (like I2C address). + */ + found = false; + acpi_get_devices(NULL, check_acpi_smo88xx_device, NULL, + (void **)&found); + + return found; +} + +/* + * Accelerometer's I2C address is not specified in DMI nor ACPI, + * so it is needed to define mapping table based on DMI product names. + */ +static const struct { + const char *dmi_product_name; + unsigned short i2c_addr; +} dell_lis3lv02d_devices[] = { + /* + * Dell platform team told us that these Latitude devices have + * ST microelectronics accelerometer at I2C address 0x29. + */ + { "Latitude E5250", 0x29 }, + { "Latitude E5450", 0x29 }, + { "Latitude E5550", 0x29 }, + { "Latitude E6440", 0x29 }, + { "Latitude E6440 ATG", 0x29 }, + { "Latitude E6540", 0x29 }, + /* + * Additional individual entries were added after verification. + */ + { "Latitude 5480", 0x29 }, + { "Vostro V131", 0x1d }, +}; + +static void register_dell_lis3lv02d_i2c_device(struct i801_priv *priv) +{ + struct i2c_board_info info; + const char *dmi_product_name; + int i; + + dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME); + for (i = 0; i < ARRAY_SIZE(dell_lis3lv02d_devices); ++i) { + if (strcmp(dmi_product_name, + dell_lis3lv02d_devices[i].dmi_product_name) == 0) + break; + } + + if (i == ARRAY_SIZE(dell_lis3lv02d_devices)) { + dev_warn(&priv->pci_dev->dev, + "Accelerometer lis3lv02d is present on SMBus but its" + " address is unknown, skipping registration\n"); + return; + } + + mem_clear(&info, sizeof(struct i2c_board_info)); + info.addr = dell_lis3lv02d_devices[i].i2c_addr; + strlcpy(info.type, "lis3lv02d", I2C_NAME_SIZE); + i2c_new_client_device(&priv->adapter, &info); +} + +/* Register optional slaves */ +static void i801_probe_optional_slaves(struct i801_priv *priv) +{ + /* Only register slaves on main SMBus channel */ + if (priv->features & FEATURE_IDF) + return; + + if (apanel_addr) { + struct i2c_board_info info; + + mem_clear(&info, sizeof(struct i2c_board_info)); + info.addr = apanel_addr; + strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE); + i2c_new_client_device(&priv->adapter, &info); + } + + if (dmi_name_in_vendors("FUJITSU")) + dmi_walk(dmi_check_onboard_devices, &priv->adapter); + + if (is_dell_system_with_lis3lv02d()) + register_dell_lis3lv02d_i2c_device(priv); + + /* Instantiate SPD EEPROMs unless the SMBus is multiplexed */ +#if IS_ENABLED(CONFIG_I2C_MUX_GPIO) + if (!priv->mux_drvdata) +#endif + i2c_register_spd(&priv->adapter); +} +#else +static void __init input_apanel_init(void) {} +static void i801_probe_optional_slaves(struct i801_priv *priv) {} +#endif /* CONFIG_X86 && CONFIG_DMI */ + +#if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI +static struct i801_mux_config i801_mux_config_asus_z8_d12 = { + .gpio_chip = "gpio_ich", + .values = { 0x02, 0x03 }, + .n_values = 2, + .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD }, + .gpios = { 52, 53 }, + .n_gpios = 2, +}; + +static struct i801_mux_config i801_mux_config_asus_z8_d18 = { + .gpio_chip = "gpio_ich", + .values = { 0x02, 0x03, 0x01 }, + .n_values = 3, + .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD }, + .gpios = { 52, 53 }, + .n_gpios = 2, +}; + +static const struct dmi_system_id mux_dmi_table[] = { + { + .matches = { + DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), + DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"), + }, + .driver_data = &i801_mux_config_asus_z8_d12, + }, + { + .matches = { + DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), + DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"), + }, + .driver_data = &i801_mux_config_asus_z8_d12, + }, + { + .matches = { + DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), + DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"), + }, + .driver_data = &i801_mux_config_asus_z8_d12, + }, + { + .matches = { + DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), + DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"), + }, + .driver_data = &i801_mux_config_asus_z8_d12, + }, + { + .matches = { + DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), + DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"), + }, + .driver_data = &i801_mux_config_asus_z8_d12, + }, + { + .matches = { + DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), + DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"), + }, + .driver_data = &i801_mux_config_asus_z8_d12, + }, + { + .matches = { + DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), + DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"), + }, + .driver_data = &i801_mux_config_asus_z8_d18, + }, + { + .matches = { + DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), + DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"), + }, + .driver_data = &i801_mux_config_asus_z8_d18, + }, + { + .matches = { + DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), + DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"), + }, + .driver_data = &i801_mux_config_asus_z8_d12, + }, + { } +}; + +/* Setup multiplexing if needed */ +static int i801_add_mux(struct i801_priv *priv) +{ + struct device *dev = &priv->adapter.dev; + const struct i801_mux_config *mux_config; + struct i2c_mux_gpio_platform_data gpio_data; + struct gpiod_lookup_table *lookup; + int err, i; + + if (!priv->mux_drvdata) + return 0; + mux_config = priv->mux_drvdata; + + /* Prepare the platform data */ + mem_clear(&gpio_data, sizeof(struct i2c_mux_gpio_platform_data)); + gpio_data.parent = priv->adapter.nr; + gpio_data.values = mux_config->values; + gpio_data.n_values = mux_config->n_values; + gpio_data.classes = mux_config->classes; + gpio_data.idle = I2C_MUX_GPIO_NO_IDLE; + + /* Register GPIO descriptor lookup table */ + lookup = devm_kzalloc(dev, + struct_size(lookup, table, mux_config->n_gpios + 1), + GFP_KERNEL); + if (!lookup) + return -ENOMEM; + lookup->dev_id = "i2c-mux-gpio"; + for (i = 0; i < mux_config->n_gpios; i++) { + lookup->table[i] = (struct gpiod_lookup) + GPIO_LOOKUP(mux_config->gpio_chip, + mux_config->gpios[i], "mux", 0); + } + gpiod_add_lookup_table(lookup); + priv->lookup = lookup; + + /* + * Register the mux device, we use PLATFORM_DEVID_NONE here + * because since we are referring to the GPIO chip by name we are + * anyways in deep trouble if there is more than one of these + * devices, and there should likely only be one platform controller + * hub. + */ + priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio", + PLATFORM_DEVID_NONE, &gpio_data, + sizeof(struct i2c_mux_gpio_platform_data)); + if (IS_ERR(priv->mux_pdev)) { + err = PTR_ERR(priv->mux_pdev); + gpiod_remove_lookup_table(lookup); + priv->mux_pdev = NULL; + dev_err(dev, "Failed to register i2c-mux-gpio device\n"); + return err; + } + + return 0; +} + +static void i801_del_mux(struct i801_priv *priv) +{ + if (priv->mux_pdev) + platform_device_unregister(priv->mux_pdev); + if (priv->lookup) + gpiod_remove_lookup_table(priv->lookup); +} + +static unsigned int i801_get_adapter_class(struct i801_priv *priv) +{ + const struct dmi_system_id *id; + const struct i801_mux_config *mux_config; + unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD; + int i; + + id = dmi_first_match(mux_dmi_table); + if (id) { + /* Remove branch classes from trunk */ + mux_config = id->driver_data; + for (i = 0; i < mux_config->n_values; i++) + class &= ~mux_config->classes[i]; + + /* Remember for later */ + priv->mux_drvdata = mux_config; + } + + return class; +} +#else +static inline int i801_add_mux(struct i801_priv *priv) { return 0; } +static inline void i801_del_mux(struct i801_priv *priv) { } + +static inline unsigned int i801_get_adapter_class(struct i801_priv *priv) +{ + return I2C_CLASS_HWMON | I2C_CLASS_SPD; +} +#endif + +static const struct itco_wdt_platform_data spt_tco_platform_data = { + .name = "Intel PCH", + .version = 4, +}; + +static DEFINE_SPINLOCK(p2sb_spinlock); + +static struct platform_device * +i801_add_tco_spt(struct i801_priv *priv, struct pci_dev *pci_dev, + struct resource *tco_res) +{ + struct resource *res; + unsigned int devfn; + u64 base64_addr; + u32 base_addr; + u8 hidden; + + /* + * We must access the NO_REBOOT bit over the Primary to Sideband + * bridge (P2SB). The BIOS prevents the P2SB device from being + * enumerated by the PCI subsystem, so we need to unhide/hide it + * to lookup the P2SB BAR. + */ + spin_lock(&p2sb_spinlock); + + devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1); + + /* Unhide the P2SB device, if it is hidden */ + pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden); + if (hidden) + pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0); + + pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr); + base64_addr = base_addr & 0xfffffff0; + + pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr); + base64_addr |= (u64)base_addr << 32; + + /* Hide the P2SB device, if it was hidden before */ + if (hidden) + pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden); + spin_unlock(&p2sb_spinlock); + + res = &tco_res[1]; + if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS) + res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV; + else + res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL; + + res->end = res->start + 3; + res->flags = IORESOURCE_MEM; + + return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1, + tco_res, 2, &spt_tco_platform_data, + sizeof(spt_tco_platform_data)); +} + +static const struct itco_wdt_platform_data cnl_tco_platform_data = { + .name = "Intel PCH", + .version = 6, +}; + +static struct platform_device * +i801_add_tco_cnl(struct i801_priv *priv, struct pci_dev *pci_dev, + struct resource *tco_res) +{ + return platform_device_register_resndata(&pci_dev->dev, + "iTCO_wdt", -1, tco_res, 1, &cnl_tco_platform_data, + sizeof(cnl_tco_platform_data)); +} + +static void i801_add_tco(struct i801_priv *priv) +{ + struct pci_dev *pci_dev = priv->pci_dev; + struct resource tco_res[2], *res; + u32 tco_base, tco_ctl; + + /* If we have ACPI based watchdog use that instead */ + if (acpi_has_watchdog()) + return; + + if (!(priv->features & (FEATURE_TCO_SPT | FEATURE_TCO_CNL))) + return; + + pci_read_config_dword(pci_dev, TCOBASE, &tco_base); + pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl); + if (!(tco_ctl & TCOCTL_EN)) + return; + + mem_clear(tco_res, sizeof(tco_res)); + /* + * Always populate the main iTCO IO resource here. The second entry + * for NO_REBOOT MMIO is filled by the SPT specific function. + */ + res = &tco_res[0]; + res->start = tco_base & ~1; + res->end = res->start + 32 - 1; + res->flags = IORESOURCE_IO; + + if (priv->features & FEATURE_TCO_CNL) + priv->tco_pdev = i801_add_tco_cnl(priv, pci_dev, tco_res); + else + priv->tco_pdev = i801_add_tco_spt(priv, pci_dev, tco_res); + + if (IS_ERR(priv->tco_pdev)) + dev_warn(&pci_dev->dev, "failed to create iTCO device\n"); +} + +#ifdef CONFIG_ACPI +static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv, + acpi_physical_address address) +{ + return address >= priv->smba && + address <= pci_resource_end(priv->pci_dev, SMBBAR); +} + +static acpi_status +i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits, + u64 *value, void *handler_context, void *region_context) +{ + struct i801_priv *priv = handler_context; + struct pci_dev *pdev = priv->pci_dev; + acpi_status status; + + /* + * Once BIOS AML code touches the OpRegion we warn and inhibit any + * further access from the driver itself. This device is now owned + * by the system firmware. + */ + mutex_lock(&priv->acpi_lock); + + if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) { + priv->acpi_reserved = true; + + dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n"); + dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n"); + + /* + * BIOS is accessing the host controller so prevent it from + * suspending automatically from now on. + */ + pm_runtime_get_sync(&pdev->dev); + } + + if ((function & ACPI_IO_MASK) == ACPI_READ) + status = acpi_os_read_port(address, (u32 *)value, bits); + else + status = acpi_os_write_port(address, (u32)*value, bits); + + mutex_unlock(&priv->acpi_lock); + + return status; +} + +static int i801_acpi_probe(struct i801_priv *priv) +{ + struct acpi_device *adev; + acpi_status status; + + adev = ACPI_COMPANION(&priv->pci_dev->dev); + if (adev) { + status = acpi_install_address_space_handler(adev->handle, + ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler, + NULL, priv); + if (ACPI_SUCCESS(status)) + return 0; + } + + return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]); +} + +static void i801_acpi_remove(struct i801_priv *priv) +{ + struct acpi_device *adev; + + adev = ACPI_COMPANION(&priv->pci_dev->dev); + if (!adev) + return; + + acpi_remove_address_space_handler(adev->handle, + ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler); + + mutex_lock(&priv->acpi_lock); + if (priv->acpi_reserved) + pm_runtime_put(&priv->pci_dev->dev); + mutex_unlock(&priv->acpi_lock); +} +#else +static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; } +static inline void i801_acpi_remove(struct i801_priv *priv) { } +#endif + +static unsigned char i801_setup_hstcfg(struct i801_priv *priv) +{ + unsigned char hstcfg = priv->original_hstcfg; + + hstcfg &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ + hstcfg |= SMBHSTCFG_HST_EN; + pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hstcfg); + return hstcfg; +} + +static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id) +{ + unsigned char temp; + int err, i; + struct i801_priv *priv; + + priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + i2c_set_adapdata(&priv->adapter, priv); + priv->adapter.owner = THIS_MODULE; + priv->adapter.class = i801_get_adapter_class(priv); + priv->adapter.algo = &smbus_algorithm; + priv->adapter.dev.parent = &dev->dev; + ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev)); + priv->adapter.retries = 3; + mutex_init(&priv->acpi_lock); + + priv->pci_dev = dev; + switch (dev->device) { + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS: + case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS: + case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS: + case PCI_DEVICE_ID_INTEL_DNV_SMBUS: + case PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS: + case PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS: + priv->features |= FEATURE_BLOCK_PROC; + priv->features |= FEATURE_I2C_BLOCK_READ; + priv->features |= FEATURE_IRQ; + priv->features |= FEATURE_SMBUS_PEC; + priv->features |= FEATURE_BLOCK_BUFFER; + priv->features |= FEATURE_TCO_SPT; + priv->features |= FEATURE_HOST_NOTIFY; + break; + + case PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS: + case PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS: + case PCI_DEVICE_ID_INTEL_CDF_SMBUS: + case PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS: + case PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS: + case PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS: + case PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS: + case PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS: + case PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS: + case PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS: + case PCI_DEVICE_ID_INTEL_EBG_SMBUS: + case PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS: + priv->features |= FEATURE_BLOCK_PROC; + priv->features |= FEATURE_I2C_BLOCK_READ; + priv->features |= FEATURE_IRQ; + priv->features |= FEATURE_SMBUS_PEC; + priv->features |= FEATURE_BLOCK_BUFFER; + priv->features |= FEATURE_TCO_CNL; + priv->features |= FEATURE_HOST_NOTIFY; + break; + + case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0: + case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1: + case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2: + case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0: + case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1: + case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2: + priv->features |= FEATURE_IDF; + fallthrough; + default: + priv->features |= FEATURE_BLOCK_PROC; + priv->features |= FEATURE_I2C_BLOCK_READ; + priv->features |= FEATURE_IRQ; + fallthrough; + case PCI_DEVICE_ID_INTEL_82801DB_3: + priv->features |= FEATURE_SMBUS_PEC; + priv->features |= FEATURE_BLOCK_BUFFER; + fallthrough; + case PCI_DEVICE_ID_INTEL_82801CA_3: + priv->features |= FEATURE_HOST_NOTIFY; + fallthrough; + case PCI_DEVICE_ID_INTEL_82801BA_2: + case PCI_DEVICE_ID_INTEL_82801AB_3: + case PCI_DEVICE_ID_INTEL_82801AA_3: + break; + } + + /* Disable features on user request */ + for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) { + if (priv->features & disable_features & (1 << i)) + dev_notice(&dev->dev, "%s disabled by user\n", + i801_feature_names[i]); + } + priv->features &= ~disable_features; + + err = pcim_enable_device(dev); + if (err) { + dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n", + err); + return err; + } + pcim_pin_device(dev); + + /* Determine the address of the SMBus area */ + priv->smba = pci_resource_start(dev, SMBBAR); + if (!priv->smba) { + dev_err(&dev->dev, + "SMBus base address uninitialized, upgrade BIOS\n"); + return -ENODEV; + } + + if (i801_acpi_probe(priv)) + return -ENODEV; + + err = pcim_iomap_regions(dev, 1 << SMBBAR, + dev_driver_string(&dev->dev)); + if (err) { + dev_err(&dev->dev, + "Failed to request SMBus region 0x%lx-0x%Lx\n", + priv->smba, + (unsigned long long)pci_resource_end(dev, SMBBAR)); + i801_acpi_remove(priv); + return err; + } + + pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &priv->original_hstcfg); + temp = i801_setup_hstcfg(priv); + if (!(priv->original_hstcfg & SMBHSTCFG_HST_EN)) + dev_info(&dev->dev, "Enabling SMBus device\n"); + + if (temp & SMBHSTCFG_SMB_SMI_EN) { + dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n"); + /* Disable SMBus interrupt feature if SMBus using SMI# */ + priv->features &= ~FEATURE_IRQ; + } + if (temp & SMBHSTCFG_SPD_WD) + dev_info(&dev->dev, "SPD Write Disable is set\n"); + + /* Clear special mode bits */ + if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER)) + outb_p(inb_p(SMBAUXCTL(priv)) & + ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); + + /* Remember original Host Notify setting */ + if (priv->features & FEATURE_HOST_NOTIFY) + priv->original_slvcmd = inb_p(SMBSLVCMD(priv)); + + /* Default timeout in interrupt mode: 200 ms */ + priv->adapter.timeout = HZ / 5; + + if (dev->irq == IRQ_NOTCONNECTED) + priv->features &= ~FEATURE_IRQ; + + if (priv->features & FEATURE_IRQ) { + u16 pcictl, pcists; + + /* Complain if an interrupt is already pending */ + pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists); + if (pcists & SMBPCISTS_INTS) + dev_warn(&dev->dev, "An interrupt is pending!\n"); + + /* Check if interrupts have been disabled */ + pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl); + if (pcictl & SMBPCICTL_INTDIS) { + dev_info(&dev->dev, "Interrupts are disabled\n"); + priv->features &= ~FEATURE_IRQ; + } + } + + if (priv->features & FEATURE_IRQ) { + init_waitqueue_head(&priv->waitq); + + err = devm_request_irq(&dev->dev, dev->irq, i801_isr, + IRQF_SHARED, + dev_driver_string(&dev->dev), priv); + if (err) { + dev_err(&dev->dev, "Failed to allocate irq %d: %d\n", + dev->irq, err); + priv->features &= ~FEATURE_IRQ; + } + } + dev_info(&dev->dev, "SMBus using %s\n", + priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling"); + + i801_add_tco(priv); + + snprintf(priv->adapter.name, sizeof(priv->adapter.name), + "SMBus I801 adapter at %04lx", priv->smba); + err = i2c_add_adapter(&priv->adapter); + if (err) { + i801_acpi_remove(priv); + return err; + } + + i801_enable_host_notify(&priv->adapter); + + i801_probe_optional_slaves(priv); + /* We ignore errors - multiplexing is optional */ + i801_add_mux(priv); + + pci_set_drvdata(dev, priv); + + dev_pm_set_driver_flags(&dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); + pm_runtime_set_autosuspend_delay(&dev->dev, 1000); + pm_runtime_use_autosuspend(&dev->dev); + pm_runtime_put_autosuspend(&dev->dev); + pm_runtime_allow(&dev->dev); + dev_info(&dev->dev, "wb-i2c-i801 probe ok.\n"); + + return 0; +} + +static void i801_remove(struct pci_dev *dev) +{ + struct i801_priv *priv = pci_get_drvdata(dev); + + pm_runtime_forbid(&dev->dev); + pm_runtime_get_noresume(&dev->dev); + + i801_disable_host_notify(priv); + i801_del_mux(priv); + i2c_del_adapter(&priv->adapter); + i801_acpi_remove(priv); + pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); + + platform_device_unregister(priv->tco_pdev); + + /* + * do not call pci_disable_device(dev) since it can cause hard hangs on + * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) + */ +} + +static void i801_shutdown(struct pci_dev *dev) +{ + struct i801_priv *priv = pci_get_drvdata(dev); + + /* Restore config registers to avoid hard hang on some systems */ + i801_disable_host_notify(priv); + pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); +} + +#ifdef CONFIG_PM_SLEEP +static int i801_suspend(struct device *dev) +{ + struct i801_priv *priv = dev_get_drvdata(dev); + + pci_write_config_byte(priv->pci_dev, SMBHSTCFG, priv->original_hstcfg); + return 0; +} + +static int i801_resume(struct device *dev) +{ + struct i801_priv *priv = dev_get_drvdata(dev); + + i801_setup_hstcfg(priv); + i801_enable_host_notify(&priv->adapter); + + return 0; +} +#endif + +static SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume); + +static struct pci_driver i801_driver = { + .name = "wb_i801_smbus", + .id_table = i801_ids, + .probe = i801_probe, + .remove = i801_remove, + .shutdown = i801_shutdown, + .driver = { + .pm = &i801_pm_ops, + }, +}; + +static int __init i2c_i801_init(void) +{ + if (dmi_name_in_vendors("FUJITSU")) + input_apanel_init(); + return pci_register_driver(&i801_driver); +} + +static void __exit i2c_i801_exit(void) +{ + pci_unregister_driver(&i801_driver); +} + +MODULE_AUTHOR("support"); +MODULE_DESCRIPTION("I801 SMBus driver"); +MODULE_LICENSE("GPL"); + +module_init(i2c_i801_init); +module_exit(i2c_i801_exit); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_i2c_mux_pca954x.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_i2c_mux_pca954x.c new file mode 100644 index 000000000000..0859cf16539e --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_i2c_mux_pca954x.c @@ -0,0 +1,1343 @@ +/* + * I2C multiplexer + * + * Copyright (c) 2008-2009 Rodolfo Giometti + * Copyright (c) 2008-2009 Eurotech S.p.A. + * + * This module supports the PCA954x series of I2C multiplexer/switch chips + * made by Philips Semiconductors. + * This includes the: + * PCA9540, PCA9542, PCA9543, PCA9544, PCA9545, PCA9546, PCA9547 + * and PCA9548. + * + * These chips are all controlled via the I2C bus itself, and all have a + * single 8-bit register. The upstream "parent" bus fans out to two, + * four, or eight downstream busses or channels; which of these + * are selected is determined by the chip type and register contents. A + * mux can select only one sub-bus at a time; a switch can select any + * combination simultaneously. + * + * Based on: + * pca954x.c from Kumar Gala + * Copyright (C) 2006 + * + * Based on: + * pca954x.c from Ken Harrenstien + * Copyright (C) 2004 Google, Inc. (Ken Harrenstien) + * + * Based on: + * i2c-virtual_cb.c from Brian Kuschak + * and + * pca9540.c from Jean Delvare . + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "wb_i2c_mux_pca954x.h" + +#define PCA954X_MAX_NCHANS 8 +#define PCA954X_IRQ_OFFSET 4 + +#define I2C_RETRY_TIMES 5 +#define I2C_RETRY_WAIT_TIMES 10 /*delay 10ms*/ + +typedef struct pca9548_cfg_info_s { + uint32_t pca9548_base_nr; + uint32_t pca9548_reset_type; + uint32_t rst_delay_b; /* delay time before reset(us) */ + uint32_t rst_delay; /* reset time(us) */ + uint32_t rst_delay_a; /* delay time after reset(us) */ + union { + i2c_attr_t i2c_attr; + gpio_attr_t gpio_attr; + io_attr_t io_attr; + file_attr_t file_attr; + } attr; + bool select_chan_check; + bool close_chan_force_reset; +} pca9548_cfg_info_t; + +int g_pca954x_debug = 0; +int g_pca954x_error = 0; + +module_param(g_pca954x_debug, int, S_IRUGO | S_IWUSR); +module_param(g_pca954x_error, int, S_IRUGO | S_IWUSR); + +#define PCA954X_DEBUG(fmt, args...) do { \ + if (g_pca954x_debug) { \ + printk(KERN_INFO "[PCA95x][VER][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +#define PCA954X_ERROR(fmt, args...) do { \ + if (g_pca954x_error) { \ + printk(KERN_ERR "[PCA95x][ERR][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +extern int pca9641_setmuxflag(int nr, int flag); +enum pca_type { + pca_9540, + pca_9542, + pca_9543, + pca_9544, + pca_9545, + pca_9546, + pca_9547, + pca_9548, +}; + +struct chip_desc { + u8 nchans; + u8 enable; /* used for muxes only */ + u8 has_irq; + enum muxtype { + pca954x_ismux = 0, + pca954x_isswi + } muxtype; +}; + +struct pca954x { + const struct chip_desc *chip; + u8 last_chan; /* last register value */ + u8 deselect; + struct i2c_client *client; + struct irq_domain *irq; + unsigned int irq_mask; + raw_spinlock_t lock; + pca9548_cfg_info_t pca9548_cfg_info; /* pca9548 reset cfg */ +}; + +/* Provide specs for the PCA954x types we know about */ +static const struct chip_desc chips[] = { + [pca_9540] = { + .nchans = 2, + .enable = 0x4, + .muxtype = pca954x_ismux, + }, + [pca_9542] = { + .nchans = 2, + .enable = 0x4, + .has_irq = 1, + .muxtype = pca954x_ismux, + }, + [pca_9543] = { + .nchans = 2, + .has_irq = 1, + .muxtype = pca954x_isswi, + }, + [pca_9544] = { + .nchans = 4, + .enable = 0x4, + .has_irq = 1, + .muxtype = pca954x_ismux, + }, + [pca_9545] = { + .nchans = 4, + .has_irq = 1, + .muxtype = pca954x_isswi, + }, + [pca_9546] = { + .nchans = 4, + .muxtype = pca954x_isswi, + }, + [pca_9547] = { + .nchans = 8, + .enable = 0x8, + .muxtype = pca954x_ismux, + }, + [pca_9548] = { + .nchans = 8, + .muxtype = pca954x_isswi, + }, +}; + +static const struct i2c_device_id pca954x_id[] = { + { "wb_pca9540", pca_9540 }, + { "wb_pca9542", pca_9542 }, + { "wb_pca9543", pca_9543 }, + { "wb_pca9544", pca_9544 }, + { "wb_pca9545", pca_9545 }, + { "wb_pca9546", pca_9546 }, + { "wb_pca9547", pca_9547 }, + { "wb_pca9548", pca_9548 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, pca954x_id); + +#ifdef CONFIG_OF +static const struct of_device_id pca954x_of_match[] = { + { .compatible = "nxp,wb_pca9540", .data = &chips[pca_9540] }, + { .compatible = "nxp,wb_pca9542", .data = &chips[pca_9542] }, + { .compatible = "nxp,wb_pca9543", .data = &chips[pca_9543] }, + { .compatible = "nxp,wb_pca9544", .data = &chips[pca_9544] }, + { .compatible = "nxp,wb_pca9545", .data = &chips[pca_9545] }, + { .compatible = "nxp,wb_pca9546", .data = &chips[pca_9546] }, + { .compatible = "nxp,wb_pca9547", .data = &chips[pca_9547] }, + { .compatible = "nxp,wb_pca9548", .data = &chips[pca_9548] }, + {} +}; +MODULE_DEVICE_TABLE(of, pca954x_of_match); +#endif + +/* Write to mux register. Don't use i2c_transfer()/i2c_smbus_xfer() + for this as they will try to lock adapter a second time */ +static int pca954x_reg_write(struct i2c_adapter *adap, + struct i2c_client *client, u8 val) +{ + int ret = -ENODEV; + + if (adap->algo->master_xfer) { + struct i2c_msg msg; + char buf[1]; + + msg.addr = client->addr; + msg.flags = 0; + msg.len = 1; + buf[0] = val; + msg.buf = buf; + ret = __i2c_transfer(adap, &msg, 1); + + if (ret >= 0 && ret != 1) + ret = -EREMOTEIO; + } else { + union i2c_smbus_data data; + ret = adap->algo->smbus_xfer(adap, client->addr, + client->flags, + I2C_SMBUS_WRITE, + val, I2C_SMBUS_BYTE, &data); + } + return ret; +} + + static int pca954x_reg_read(struct i2c_adapter *adap, + struct i2c_client *client, u8 *val) + { + int ret = -ENODEV; + u8 tmp_val; + + if (adap->algo->master_xfer) { + struct i2c_msg msg; + + msg.addr = client->addr; + msg.flags = I2C_M_RD; + msg.len = 1; + msg.buf = &tmp_val; + ret = __i2c_transfer(adap, &msg, 1); + + if (ret >= 0 && ret != 1) + ret = -EREMOTEIO; + } else { + union i2c_smbus_data data; + ret = adap->algo->smbus_xfer(adap, client->addr, + client->flags, + I2C_SMBUS_READ, + 0, I2C_SMBUS_BYTE, &data); + + if (!ret) { + tmp_val = data.byte; + } + } + + *val = tmp_val; + return ret; + } + +static int pca954x_setmuxflag(struct i2c_client *client, int flag) +{ + struct i2c_adapter *adap = to_i2c_adapter(client->dev.parent); + + pca9641_setmuxflag(adap->nr, flag); + return 0; +} + +static int pca9548_gpio_init(gpio_attr_t *gpio_attr) +{ + int err; + + if (gpio_attr->gpio_init) { + PCA954X_DEBUG("gpio%d already init, do nothing.\n", gpio_attr->gpio); + return 0; + } + + PCA954X_DEBUG("gpio%d init.\n", gpio_attr->gpio); + err = gpio_request(gpio_attr->gpio, "pca9548_reset"); + if (err) { + goto error; + } + err = gpio_direction_output(gpio_attr->gpio, gpio_attr->reset_off); + if (err) { + gpio_free(gpio_attr->gpio); + goto error; + } + gpio_attr->gpio_init = 1; + return 0; +error: + PCA954X_ERROR("pca9548_gpio_init failed, ret:%d.\n", err); + return err; +} + +static void pca9548_gpio_free(gpio_attr_t *gpio_attr) +{ + if (gpio_attr->gpio_init == 1) { + PCA954X_DEBUG("gpio%d release.\n", gpio_attr->gpio); + gpio_free(gpio_attr->gpio); + gpio_attr->gpio_init = 0; + } +} + +static int pca954x_reset_file_read(const char *path, uint32_t pos, uint8_t *val, size_t size) +{ + int ret; + struct file *filp; + loff_t tmp_pos; + + filp = filp_open(path, O_RDONLY, 0); + if (IS_ERR(filp)) { + PCA954X_ERROR("read open failed errno = %ld\r\n", -PTR_ERR(filp)); + filp = NULL; + goto exit; + } + + tmp_pos = (loff_t)pos; + ret = kernel_read(filp, val, size, &tmp_pos); + if (ret < 0) { + PCA954X_ERROR("kernel_read failed, path=%s, addr=0x%x, size=%ld, ret=%d\r\n", path, pos, size, ret); + goto exit; + } + + filp_close(filp, NULL); + + return ret; + +exit: + if (filp != NULL) { + filp_close(filp, NULL); + } + + return -1; +} + +static int pca954x_reset_file_write(const char *path, uint32_t pos, uint8_t *val, size_t size) +{ + int ret; + struct file *filp; + loff_t tmp_pos; + + filp = filp_open(path, O_RDWR, 777); + if (IS_ERR(filp)) { + PCA954X_ERROR("write open failed errno = %ld\r\n", -PTR_ERR(filp)); + filp = NULL; + goto exit; + } + + tmp_pos = (loff_t)pos; + ret = kernel_write(filp, val, size, &tmp_pos); + if (ret < 0) { + PCA954X_ERROR("kernel_write failed, path=%s, addr=0x%x, size=%ld, ret=%d\r\n", path, pos, size, ret); + goto exit; + } + + vfs_fsync(filp, 1); + filp_close(filp, NULL); + + return ret; + +exit: + if (filp != NULL) { + filp_close(filp, NULL); + } + + return -1; +} + +static int pca954x_reset_i2c_read(uint32_t bus, uint32_t addr, uint32_t offset_addr, + unsigned char *buf, uint32_t size) +{ + struct file *fp; + struct i2c_client client; + char i2c_path[32]; + int i ,j ; + int rv; + + rv = 0; + mem_clear(i2c_path, sizeof(i2c_path)); + snprintf(i2c_path, sizeof(i2c_path), "/dev/i2c-%d", bus); + fp = filp_open(i2c_path, O_RDWR, S_IRUSR | S_IWUSR); + if (IS_ERR(fp)) { + PCA954X_ERROR("i2c open fail.\n"); + return -1; + } + memcpy(&client, fp->private_data, sizeof(struct i2c_client)); + client.addr = addr; + for (j = 0 ;j < size ;j++) { + for (i = 0; i < I2C_RETRY_TIMES; i++) { + rv = i2c_smbus_read_byte_data(&client, (offset_addr + j)); + if (rv < 0) { + PCA954X_ERROR("i2c read failed, try again.\n"); + msleep(I2C_RETRY_WAIT_TIMES); + if (i >= (I2C_RETRY_TIMES - 1)) { + goto out; + } + continue; + } + *(buf + j) = (unsigned char)rv; + break; + } + } +out: + filp_close(fp, NULL); + return rv; +} + +static int pca954x_reset_i2c_write(uint32_t bus, uint32_t dev_addr, uint32_t offset_addr, + uint8_t write_buf) +{ + struct file *fp; + struct i2c_client client; + char i2c_path[32]; + int i; + int rv; + + rv = 0; + mem_clear(i2c_path, sizeof(i2c_path)); + snprintf(i2c_path, sizeof(i2c_path), "/dev/i2c-%d", bus); + fp = filp_open(i2c_path, O_RDWR, S_IRUSR | S_IWUSR); + if (IS_ERR(fp)) { + PCA954X_ERROR("i2c open fail.\n"); + return -1; + } + memcpy(&client, fp->private_data, sizeof(struct i2c_client)); + client.addr = dev_addr; + for (i = 0; i < I2C_RETRY_TIMES; i++) { + rv = i2c_smbus_write_byte_data(&client, offset_addr, write_buf); + if (rv < 0) { + PCA954X_ERROR("i2c write failed, try again.\n"); + msleep(I2C_RETRY_WAIT_TIMES); + if (i >= (I2C_RETRY_TIMES - 1)) { + goto out; + } + continue; + } + break; + } +out: + filp_close(fp, NULL); + return rv; +} + +static void pca954x_close_chan_finally(struct i2c_mux_core * muxc) +{ + struct pca954x *data; + struct i2c_adapter *adapter; + struct i2c_client *client; + int adapter_timeout; + + data = i2c_mux_priv(muxc); + client = data->client; + adapter = muxc->parent; + /* get bus info */ + while (i2c_parent_is_i2c_adapter(adapter)) { + adapter = to_i2c_adapter(adapter->dev.parent); + } + adapter_timeout = adapter->timeout; + adapter->timeout = msecs_to_jiffies(50); + pca954x_reg_write(muxc->parent, client, data->last_chan); + adapter->timeout = adapter_timeout; + + return; +} + +static int pca954x_do_file_reset(struct i2c_mux_core *muxc) +{ + int ret, timeout, err; + struct pca954x *data; + struct i2c_client *client; + pca9548_cfg_info_t *reset_cfg; + file_attr_t *file_attr; + u8 val; + + data = i2c_mux_priv(muxc); + client = data->client; + reset_cfg = &data->pca9548_cfg_info; + file_attr = &reset_cfg->attr.file_attr; + ret = -1; + + PCA954X_DEBUG("rst_delay_b:%u, rst_delay:%u, rst_delay_a:%u.\n", + reset_cfg->rst_delay_b, reset_cfg->rst_delay, reset_cfg->rst_delay_a); + PCA954X_DEBUG("dev_name:%s, offset:0x%x, mask:0x%x, on:0x%x, off:0x%x.\n", + file_attr->dev_name, file_attr->offset, file_attr->mask, + file_attr->reset_on, file_attr->reset_off); + + if (reset_cfg->rst_delay_b) { + udelay(reset_cfg->rst_delay_b); + } + + err = pca954x_reset_file_read(file_attr->dev_name, file_attr->offset, &val, sizeof(val)); + if (err < 0) { + goto out; + } + val &= ~(file_attr->mask); + val |= file_attr->reset_on; + err = pca954x_reset_file_write(file_attr->dev_name, file_attr->offset, &val, sizeof(val)); + if (err < 0) { + goto out; + } + + if (reset_cfg->rst_delay) { + udelay(reset_cfg->rst_delay); + } + + val &= ~(file_attr->mask); + val |= file_attr->reset_off; + err = pca954x_reset_file_write(file_attr->dev_name, file_attr->offset, &val, sizeof(val)); + if (err < 0) { + goto out; + } + + timeout = reset_cfg->rst_delay_a; + while (timeout > 0) { + udelay(1); + err = pca954x_reset_file_read(file_attr->dev_name, file_attr->offset, &val, sizeof(val)); + if (err < 0) { + goto out; + } + val &= (file_attr->mask); + if (val == file_attr->reset_off) { + ret = 0; + pca954x_close_chan_finally(muxc); + PCA954X_DEBUG("pca954x_do_file_reset success.\n"); + break; + } + if (timeout >= 1000 && (timeout % 1000 == 0)) { + schedule(); + } + timeout--; + } + if (ret < 0) { + PCA954X_ERROR("pca954x_do_file_reset timeout.\n"); + } +out: + if (err < 0) { + PCA954X_ERROR("pca954x_do_file_reset file rd/wr failed, ret:%d.\n", err); + } + + return ret; +} + +static int pca954x_do_io_reset(struct i2c_mux_core *muxc) +{ + int ret, timeout; + struct pca954x *data; + struct i2c_client *client; + pca9548_cfg_info_t *reset_cfg; + io_attr_t *io_attr; + u8 val; + + data = i2c_mux_priv(muxc); + client = data->client; + reset_cfg = &data->pca9548_cfg_info; + io_attr = &reset_cfg->attr.io_attr; + + PCA954X_DEBUG("rst_delay_b:%u, rst_delay:%u, rst_delay_a:%u.\n", + reset_cfg->rst_delay_b, reset_cfg->rst_delay, reset_cfg->rst_delay_a); + PCA954X_DEBUG("io_addr:0x%x, mask:0x%x, on:0x%x, off:0x%x.\n", + io_attr->io_addr, io_attr->mask, io_attr->reset_on, io_attr->reset_off); + + if (reset_cfg->rst_delay_b) { + udelay(reset_cfg->rst_delay_b); + } + + val = inb(io_attr->io_addr); + val &= ~(io_attr->mask); + val |= io_attr->reset_on; + outb(val, io_attr->io_addr); + + if (reset_cfg->rst_delay) { + udelay(reset_cfg->rst_delay); + } + + val &= ~(io_attr->mask); + val |= io_attr->reset_off; + outb(val, io_attr->io_addr); + + ret = -1; + timeout = reset_cfg->rst_delay_a; + while (timeout > 0) { + udelay(1); + val = inb(io_attr->io_addr); + val &= (io_attr->mask); + if (val == io_attr->reset_off) { + ret = 0; + pca954x_close_chan_finally(muxc); + PCA954X_DEBUG("pca954x_do_io_reset success.\n"); + break; + } + if (timeout >= 1000 && (timeout % 1000 == 0)) { + schedule(); + } + timeout--; + } + + if (ret < 0) { + PCA954X_ERROR("pca954x_do_io_reset timeout.\n"); + } + + return ret; +} + +static int pca954x_do_gpio_reset(struct i2c_mux_core *muxc) +{ + int ret, timeout; + struct pca954x *data; + struct i2c_client *client; + pca9548_cfg_info_t *reset_cfg; + gpio_attr_t *gpio_attr; + u8 val; + + data = i2c_mux_priv(muxc); + client = data->client; + reset_cfg = &data->pca9548_cfg_info; + gpio_attr = &reset_cfg->attr.gpio_attr; + + ret = pca9548_gpio_init(gpio_attr); + if (ret) { + return -1; + } + + if (reset_cfg->rst_delay_b) { + udelay(reset_cfg->rst_delay_b); + } + + /* reset on */ + __gpio_set_value(gpio_attr->gpio, gpio_attr->reset_on); + + if (reset_cfg->rst_delay) { + udelay(reset_cfg->rst_delay); + } + + /* reset off */ + __gpio_set_value(gpio_attr->gpio, gpio_attr->reset_off); + ret = -1; + timeout = reset_cfg->rst_delay_a; + while (timeout > 0) { + udelay(1); + val = __gpio_get_value(gpio_attr->gpio); + if (val == gpio_attr->reset_off) { + ret = 0; + pca954x_close_chan_finally(muxc); + PCA954X_DEBUG("pca954x_do_gpio_reset success.\n"); + break; + } + if (timeout >= 1000 && (timeout % 1000 == 0)) { + /* 1MS schedule*/ + schedule(); + } + timeout--; + } + + if (ret < 0) { + PCA954X_ERROR("pca954x_do_gpio_reset timeout.\n"); + } + + pca9548_gpio_free(gpio_attr); + return ret; +} + +static int pca954x_do_i2c_reset(struct i2c_mux_core *muxc) +{ + int ret, timeout, err; + struct pca954x *data; + struct i2c_client *client; + pca9548_cfg_info_t *reset_cfg; + i2c_attr_t *i2c_attr; + u8 val; + + data = i2c_mux_priv(muxc); + client = data->client; + reset_cfg = &data->pca9548_cfg_info; + i2c_attr = &reset_cfg->attr.i2c_attr; + ret = -1; + + PCA954X_DEBUG("rst_delay_b:%u, rst_delay:%u, rst_delay_a:%u.\n", + reset_cfg->rst_delay_b, reset_cfg->rst_delay, reset_cfg->rst_delay_a); + PCA954X_DEBUG("bus:0x%x, addr:0x%x, reg:0x%x, mask:0x%x, on:0x%x, off:0x%x.\n", + i2c_attr->i2c_bus, i2c_attr->i2c_addr, i2c_attr->reg_offset, + i2c_attr->mask, i2c_attr->reset_on, i2c_attr->reset_off); + + if (reset_cfg->rst_delay_b) { + udelay(reset_cfg->rst_delay_b); + } + + err = pca954x_reset_i2c_read(i2c_attr->i2c_bus, i2c_attr->i2c_addr, + i2c_attr->reg_offset, &val, sizeof(val)); + if (err < 0) { + goto out; + } + val &= ~(i2c_attr->mask); + val |= i2c_attr->reset_on; + err = pca954x_reset_i2c_write(i2c_attr->i2c_bus, i2c_attr->i2c_addr, + i2c_attr->reg_offset, val); + if (err < 0) { + goto out; + } + + if (reset_cfg->rst_delay) { + udelay(reset_cfg->rst_delay); + } + + val &= ~(i2c_attr->mask); + val |= i2c_attr->reset_off; + err = pca954x_reset_i2c_write(i2c_attr->i2c_bus, i2c_attr->i2c_addr, + i2c_attr->reg_offset, val); + if (err < 0) { + goto out; + } + + timeout = reset_cfg->rst_delay_a; + while (timeout > 0) { + udelay(1); + err = pca954x_reset_i2c_read(i2c_attr->i2c_bus, i2c_attr->i2c_addr, + i2c_attr->reg_offset, &val, sizeof(val)); + if (err < 0) { + goto out; + } + val &= (i2c_attr->mask); + if (val == i2c_attr->reset_off) { + ret = 0; + pca954x_close_chan_finally(muxc); + PCA954X_DEBUG("pca954x_do_i2c_reset success.\n"); + break; + } + if (timeout >= 1000 && (timeout % 1000 == 0)) { + schedule(); + } + timeout--; + } + if (ret < 0) { + PCA954X_ERROR("pca954x_do_i2c_reset timeout.\n"); + } +out: + if (err < 0) { + PCA954X_ERROR("pca954x_do_i2c_reset i2c op failed, ret:%d.\n", err); + } + return ret; +} + +static int pca954x_do_reset(struct i2c_mux_core *muxc) +{ + int ret; + struct pca954x *data; + + data = i2c_mux_priv(muxc); + if (data->pca9548_cfg_info.pca9548_reset_type == PCA9548_RESET_NONE) { + ret = -1; + PCA954X_DEBUG("Don't need to reset.\n"); + } else if (data->pca9548_cfg_info.pca9548_reset_type == PCA9548_RESET_I2C) { + ret = pca954x_do_i2c_reset(muxc); + } else if (data->pca9548_cfg_info.pca9548_reset_type == PCA9548_RESET_GPIO) { + ret = pca954x_do_gpio_reset(muxc); + } else if (data->pca9548_cfg_info.pca9548_reset_type == PCA9548_RESET_IO) { + ret = pca954x_do_io_reset(muxc); + } else if (data->pca9548_cfg_info.pca9548_reset_type == PCA9548_RESET_FILE) { + ret = pca954x_do_file_reset(muxc); + } else { + ret = -1; + PCA954X_ERROR("Unsupport reset type:0x%x.\n", + data->pca9548_cfg_info.pca9548_reset_type); + } + + if (ret < 0) { + PCA954X_ERROR("pca9548_reset_ctrl failed, reset type:%u, ret:%d.\n", + data->pca9548_cfg_info.pca9548_reset_type, ret); + } + return ret; +} + +static int pca954x_select_chan(struct i2c_mux_core *muxc, u32 chan) +{ + struct pca954x *data = i2c_mux_priv(muxc); + struct i2c_client *client = data->client; + const struct chip_desc *chip = data->chip; + u8 regval; + int ret = 0; + u8 read_val = 0; + int rv; + + /* we make switches look like muxes, not sure how to be smarter */ + if (chip->muxtype == pca954x_ismux) + regval = chan | chip->enable; + else + regval = 1 << chan; + + /* Only select the channel if its different from the last channel */ + if (data->last_chan != regval) { + pca954x_setmuxflag(client, 0); + ret = pca954x_reg_write(muxc->parent, client, regval); + data->last_chan = ret < 0 ? 0 : regval; + } + + if (data->pca9548_cfg_info.select_chan_check) { /* check chan */ + ret = pca954x_reg_read(muxc->parent, client, &read_val); + /* read failed or chan not open, reset pca9548 */ + if ((ret < 0) || (read_val != data->last_chan)) { + dev_warn(&client->dev, "pca954x open channle %u failed, do reset.\n", chan); + PCA954X_DEBUG("ret = %d, read_val = %d, last_chan = %d.\n", ret, read_val, data->last_chan); + rv = pca954x_do_reset(muxc); + if (rv >= 0) { + PCA954X_DEBUG("pca954x_do_reset success, rv = %d.\n", rv); + } else { + PCA954X_DEBUG("pca954x_do_reset failed, rv = %d.\n", rv); + } + if (ret >= 0) { + ret = -EIO; /* chan not match, return IO error */ + } + } + } + + return ret; +} + +static int pca954x_deselect_mux(struct i2c_mux_core *muxc, u32 chan) +{ + struct pca954x *data = i2c_mux_priv(muxc); + struct i2c_client *client = data->client; + int ret, rv; + + /* Deselect active channel */ + data->last_chan = 0; + if (data->pca9548_cfg_info.close_chan_force_reset) { + ret = pca954x_do_reset(muxc); + } else { + ret = pca954x_reg_write(muxc->parent, client, data->last_chan); + if (ret < 0 ) { + + dev_warn(&client->dev, "pca954x close channel %u failed, do reset.\n", chan); + rv = pca954x_do_reset(muxc); + if (rv == 0) { + ret = 0; + } + } + } + + pca954x_setmuxflag(client, 1); + (void)pca954x_reg_write(muxc->parent, client, data->last_chan); + + return ret; + +} + +static irqreturn_t pca954x_irq_handler(int irq, void *dev_id) +{ + struct pca954x *data = dev_id; + unsigned int child_irq; + int ret, i, handled = 0; + + ret = i2c_smbus_read_byte(data->client); + if (ret < 0) + return IRQ_NONE; + + for (i = 0; i < data->chip->nchans; i++) { + if (ret & BIT(PCA954X_IRQ_OFFSET + i)) { + child_irq = irq_linear_revmap(data->irq, i); + handle_nested_irq(child_irq); + handled++; + } + } + return handled ? IRQ_HANDLED : IRQ_NONE; +} + +static void pca954x_irq_mask(struct irq_data *idata) +{ + struct pca954x *data = irq_data_get_irq_chip_data(idata); + unsigned int pos = idata->hwirq; + unsigned long flags; + + raw_spin_lock_irqsave(&data->lock, flags); + + data->irq_mask &= ~BIT(pos); + if (!data->irq_mask) + disable_irq(data->client->irq); + + raw_spin_unlock_irqrestore(&data->lock, flags); +} + +static void pca954x_irq_unmask(struct irq_data *idata) +{ + struct pca954x *data = irq_data_get_irq_chip_data(idata); + unsigned int pos = idata->hwirq; + unsigned long flags; + + raw_spin_lock_irqsave(&data->lock, flags); + + if (!data->irq_mask) + enable_irq(data->client->irq); + data->irq_mask |= BIT(pos); + + raw_spin_unlock_irqrestore(&data->lock, flags); +} + +static int pca954x_irq_set_type(struct irq_data *idata, unsigned int type) +{ + if ((type & IRQ_TYPE_SENSE_MASK) != IRQ_TYPE_LEVEL_LOW) + return -EINVAL; + return 0; +} + +static struct irq_chip pca954x_irq_chip = { + .name = "i2c-mux-pca954x", + .irq_mask = pca954x_irq_mask, + .irq_unmask = pca954x_irq_unmask, + .irq_set_type = pca954x_irq_set_type, +}; + +static int of_pca954x_irq_setup(struct i2c_mux_core *muxc) +{ + struct pca954x *data = i2c_mux_priv(muxc); + struct i2c_client *client = data->client; + int c, err, irq; + + if (!data->chip->has_irq || client->irq <= 0) + return 0; + + raw_spin_lock_init(&data->lock); + + data->irq = irq_domain_add_linear(client->dev.of_node, + data->chip->nchans, + &irq_domain_simple_ops, data); + if (!data->irq) + return -ENODEV; + + for (c = 0; c < data->chip->nchans; c++) { + irq = irq_create_mapping(data->irq, c); + irq_set_chip_data(irq, data); + irq_set_chip_and_handler(irq, &pca954x_irq_chip, + handle_simple_irq); + } + + err = devm_request_threaded_irq(&client->dev, data->client->irq, NULL, + pca954x_irq_handler, + IRQF_ONESHOT | IRQF_SHARED, + "pca954x", data); + if (err) + goto err_req_irq; + + disable_irq(data->client->irq); + + return 0; +err_req_irq: + for (c = 0; c < data->chip->nchans; c++) { + irq = irq_find_mapping(data->irq, c); + irq_dispose_mapping(irq); + } + irq_domain_remove(data->irq); + + return err; +} + +static int pca954x_irq_setup(struct i2c_mux_core *muxc) +{ + return 0; +} + +static int of_pca954x_reset_data_init(struct pca954x *data) +{ + int err; + struct device *dev = &data->client->dev; + pca9548_cfg_info_t *reset_cfg; + + reset_cfg = &data->pca9548_cfg_info; + if (dev == NULL || dev->of_node == NULL) { + PCA954X_DEBUG("dev or dev->of_node is NUll, no reset.\n"); + reset_cfg->pca9548_reset_type = PCA9548_RESET_NONE; + return 0; + } + + reset_cfg->select_chan_check = of_property_read_bool(dev->of_node, "select_chan_check"); + reset_cfg->close_chan_force_reset = of_property_read_bool(dev->of_node, "close_chan_force_reset"); + PCA954X_DEBUG("select_chan_check:%d, close_chan_force_reset:%d.\n", reset_cfg->select_chan_check, + reset_cfg->close_chan_force_reset); + + if (of_property_read_u32(dev->of_node, "pca9548_reset_type", &reset_cfg->pca9548_reset_type)) { + + PCA954X_DEBUG("pca9548_reset_type not found, no reset.\n"); + reset_cfg->pca9548_reset_type = PCA9548_RESET_NONE; + return 0; + } + err = of_property_read_u32(dev->of_node, "rst_delay_b", &reset_cfg->rst_delay_b); + err |= of_property_read_u32(dev->of_node, "rst_delay", &reset_cfg->rst_delay); + err |= of_property_read_u32(dev->of_node, "rst_delay_a", &reset_cfg->rst_delay_a); + + if (err) { + goto dts_config_err; + } + PCA954X_DEBUG("reset_type:0x%x, rst_delay_b:0x%x, rst_delay:0x%x, rst_delay_a:0x%x.\n", + reset_cfg->pca9548_reset_type, reset_cfg->rst_delay_b, + reset_cfg->rst_delay, reset_cfg->rst_delay_a); + + if (reset_cfg->pca9548_reset_type == PCA9548_RESET_I2C) { + + PCA954X_DEBUG("reset by i2c.\n"); + err = of_property_read_u32(dev->of_node, "i2c_bus", &reset_cfg->attr.i2c_attr.i2c_bus); + err |=of_property_read_u32(dev->of_node, "i2c_addr", &reset_cfg->attr.i2c_attr.i2c_addr); + err |=of_property_read_u32(dev->of_node, "reg_offset", &reset_cfg->attr.i2c_attr.reg_offset); + err |=of_property_read_u32(dev->of_node, "mask", &reset_cfg->attr.i2c_attr.mask); + err |=of_property_read_u32(dev->of_node, "reset_on", &reset_cfg->attr.i2c_attr.reset_on); + err |=of_property_read_u32(dev->of_node, "reset_off", &reset_cfg->attr.i2c_attr.reset_off); + if (err) { + goto dts_config_err; + } + PCA954X_DEBUG("bus:%u, addr:0x%x, offset:0x%x, mask:0x%x, on:0x%x, off:0x%x.\n", + reset_cfg->attr.i2c_attr.i2c_bus, reset_cfg->attr.i2c_attr.i2c_addr, + reset_cfg->attr.i2c_attr.reg_offset, reset_cfg->attr.i2c_attr.mask, + reset_cfg->attr.i2c_attr.reset_on, reset_cfg->attr.i2c_attr.reset_off); + } else if (reset_cfg->pca9548_reset_type == PCA9548_RESET_GPIO) { + + PCA954X_DEBUG("reset by gpio.\n"); + err = of_property_read_u32(dev->of_node, "gpio", &reset_cfg->attr.gpio_attr.gpio); + err |=of_property_read_u32(dev->of_node, "reset_on", &reset_cfg->attr.gpio_attr.reset_on); + err |=of_property_read_u32(dev->of_node, "reset_off", &reset_cfg->attr.gpio_attr.reset_off); + if (err) { + goto dts_config_err; + } + PCA954X_DEBUG("gpio number:%u, reset_on:0x%x, reset_off:0x%x.\n", + reset_cfg->attr.gpio_attr.gpio, reset_cfg->attr.gpio_attr.reset_on, + reset_cfg->attr.gpio_attr.reset_off); + reset_cfg->attr.gpio_attr.gpio_init = 0; + } else if (reset_cfg->pca9548_reset_type == PCA9548_RESET_IO) { + + PCA954X_DEBUG("reset by io.\n"); + err = of_property_read_u32(dev->of_node, "io_addr", &reset_cfg->attr.io_attr.io_addr); + err |=of_property_read_u32(dev->of_node, "mask", &reset_cfg->attr.io_attr.mask); + err |=of_property_read_u32(dev->of_node, "reset_on", &reset_cfg->attr.io_attr.reset_on); + err |=of_property_read_u32(dev->of_node, "reset_off", &reset_cfg->attr.io_attr.reset_off); + if (err) { + goto dts_config_err; + } + PCA954X_DEBUG("io_addr:0x%x, mask:0x%x, reset_on:0x%x, reset_off:0x%x.\n", + reset_cfg->attr.io_attr.io_addr, reset_cfg->attr.io_attr.mask, + reset_cfg->attr.io_attr.reset_on, reset_cfg->attr.io_attr.reset_off); + } else if (reset_cfg->pca9548_reset_type == PCA9548_RESET_FILE) { + + PCA954X_DEBUG("reset by file.\n"); + err = of_property_read_string(dev->of_node, "dev_name", &reset_cfg->attr.file_attr.dev_name); + err |=of_property_read_u32(dev->of_node, "offset", &reset_cfg->attr.file_attr.offset); + err |=of_property_read_u32(dev->of_node, "mask", &reset_cfg->attr.file_attr.mask); + err |=of_property_read_u32(dev->of_node, "reset_on", &reset_cfg->attr.file_attr.reset_on); + err |=of_property_read_u32(dev->of_node, "reset_off", &reset_cfg->attr.file_attr.reset_off); + if (err) { + goto dts_config_err; + } + PCA954X_DEBUG("dev_name:%s, mask:0x%x, reset_on:0x%x, reset_off:0x%x.\n", + reset_cfg->attr.file_attr.dev_name, reset_cfg->attr.file_attr.mask, + reset_cfg->attr.file_attr.reset_on, reset_cfg->attr.file_attr.reset_off); + } else { + PCA954X_ERROR("Unsupport reset type:%d.\n", reset_cfg->pca9548_reset_type); + goto dts_config_err; + } + return 0; +dts_config_err: + PCA954X_ERROR("dts config error, ret:%d.\n", err); + return -EINVAL; +} + +static int pca954x_reset_data_init(struct pca954x *data) +{ + pca9548_cfg_info_t *reset_cfg; + i2c_mux_pca954x_device_t *i2c_mux_pca954x_device; + + if (data->client->dev.platform_data == NULL) { + PCA954X_DEBUG("pca954x has no reset platform data config.\n"); + return 0; + } + reset_cfg = &data->pca9548_cfg_info; + i2c_mux_pca954x_device = data->client->dev.platform_data; + reset_cfg->select_chan_check = i2c_mux_pca954x_device->select_chan_check; + reset_cfg->close_chan_force_reset = i2c_mux_pca954x_device->close_chan_force_reset; + PCA954X_DEBUG("select_chan_check:%d, close_chan_force_reset:%d.\n", reset_cfg->select_chan_check, + reset_cfg->close_chan_force_reset); + + reset_cfg->pca9548_reset_type = i2c_mux_pca954x_device->pca9548_reset_type; + if (reset_cfg->pca9548_reset_type == PCA9548_RESET_NONE) { + PCA954X_DEBUG("pca9548_reset_type not found, no reset.\n"); + return 0; + } + + reset_cfg->rst_delay_b = i2c_mux_pca954x_device->rst_delay_b; + reset_cfg->rst_delay = i2c_mux_pca954x_device->rst_delay; + reset_cfg->rst_delay_a = i2c_mux_pca954x_device->rst_delay_a; + PCA954X_DEBUG("reset_type:0x%x, rst_delay_b:0x%x, rst_delay:0x%x, rst_delay_a:0x%x.\n", + reset_cfg->pca9548_reset_type, reset_cfg->rst_delay_b, + reset_cfg->rst_delay, reset_cfg->rst_delay_a); + + if (reset_cfg->pca9548_reset_type == PCA9548_RESET_I2C) { + + PCA954X_DEBUG("reset by i2c.\n"); + reset_cfg->attr.i2c_attr.i2c_bus = i2c_mux_pca954x_device->attr.i2c_attr.i2c_bus; + reset_cfg->attr.i2c_attr.i2c_addr = i2c_mux_pca954x_device->attr.i2c_attr.i2c_addr; + reset_cfg->attr.i2c_attr.reg_offset = i2c_mux_pca954x_device->attr.i2c_attr.reg_offset; + reset_cfg->attr.i2c_attr.mask = i2c_mux_pca954x_device->attr.i2c_attr.mask; + reset_cfg->attr.i2c_attr.reset_on = i2c_mux_pca954x_device->attr.i2c_attr.reset_on; + reset_cfg->attr.i2c_attr.reset_off = i2c_mux_pca954x_device->attr.i2c_attr.reset_off; + PCA954X_DEBUG("bus:%u, addr:0x%x, offset:0x%x, mask:0x%x, on:0x%x, off:0x%x.\n", + reset_cfg->attr.i2c_attr.i2c_bus, reset_cfg->attr.i2c_attr.i2c_addr, + reset_cfg->attr.i2c_attr.reg_offset, reset_cfg->attr.i2c_attr.mask, + reset_cfg->attr.i2c_attr.reset_on, reset_cfg->attr.i2c_attr.reset_off); + } else if (reset_cfg->pca9548_reset_type == PCA9548_RESET_GPIO) { + + PCA954X_DEBUG("reset by gpio.\n"); + reset_cfg->attr.gpio_attr.gpio = i2c_mux_pca954x_device->attr.gpio_attr.gpio; + reset_cfg->attr.gpio_attr.reset_on = i2c_mux_pca954x_device->attr.gpio_attr.reset_on; + reset_cfg->attr.gpio_attr.reset_off = i2c_mux_pca954x_device->attr.gpio_attr.reset_off; + PCA954X_DEBUG("gpio number:%u, reset_on:0x%x, reset_off:0x%x.\n", + reset_cfg->attr.gpio_attr.gpio, reset_cfg->attr.gpio_attr.reset_on, + reset_cfg->attr.gpio_attr.reset_off); + reset_cfg->attr.gpio_attr.gpio_init = 0; + } else if (reset_cfg->pca9548_reset_type == PCA9548_RESET_IO) { + + PCA954X_DEBUG("reset by io.\n"); + reset_cfg->attr.io_attr.io_addr = i2c_mux_pca954x_device->attr.io_attr.io_addr; + reset_cfg->attr.io_attr.mask = i2c_mux_pca954x_device->attr.io_attr.mask; + reset_cfg->attr.io_attr.reset_on = i2c_mux_pca954x_device->attr.io_attr.reset_on; + reset_cfg->attr.io_attr.reset_off = i2c_mux_pca954x_device->attr.io_attr.reset_off; + PCA954X_DEBUG("io_addr:0x%x, mask:0x%x, reset_on:0x%x, reset_off:0x%x.\n", + reset_cfg->attr.io_attr.io_addr, reset_cfg->attr.io_attr.mask, + reset_cfg->attr.io_attr.reset_on, reset_cfg->attr.io_attr.reset_off); + } else if (reset_cfg->pca9548_reset_type == PCA9548_RESET_FILE) { + + reset_cfg->attr.file_attr.dev_name = i2c_mux_pca954x_device->attr.file_attr.dev_name; + reset_cfg->attr.file_attr.offset = i2c_mux_pca954x_device->attr.file_attr.offset; + reset_cfg->attr.file_attr.mask = i2c_mux_pca954x_device->attr.file_attr.mask; + reset_cfg->attr.file_attr.reset_on = i2c_mux_pca954x_device->attr.file_attr.reset_on; + reset_cfg->attr.file_attr.reset_off = i2c_mux_pca954x_device->attr.file_attr.reset_off; + PCA954X_DEBUG("dev_name:%s, mask:0x%x, reset_on:0x%x, reset_off:0x%x.\n", + reset_cfg->attr.file_attr.dev_name, reset_cfg->attr.file_attr.mask, + reset_cfg->attr.file_attr.reset_on, reset_cfg->attr.file_attr.reset_off); + } else { + PCA954X_ERROR("Unsupport reset type:%d.\n", reset_cfg->pca9548_reset_type); + return -EINVAL; + } + return 0; +} + +/* + * I2C init/probing/exit functions + */ +static int pca954x_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct i2c_adapter *adap = to_i2c_adapter(client->dev.parent); + struct device_node *of_node = client->dev.of_node; + bool idle_disconnect_dt; + struct gpio_desc *gpio; + int num, force, class; + struct i2c_mux_core *muxc; + struct pca954x *data; + const struct of_device_id *match; + unsigned int probe_disable; + int ret, dynamic_nr; + i2c_mux_pca954x_device_t *i2c_mux_pca954x_device; + + PCA954X_DEBUG("pca954x_probe, parent bus: %d, 9548 addr:0x%x.\n", adap->nr, client->addr); + + if (!i2c_check_functionality(adap, I2C_FUNC_SMBUS_BYTE)) + return -ENODEV; + + muxc = i2c_mux_alloc(adap, &client->dev, + PCA954X_MAX_NCHANS, sizeof(*data), 0, + pca954x_select_chan, pca954x_deselect_mux); + if (!muxc) + return -ENOMEM; + data = i2c_mux_priv(muxc); + + i2c_set_clientdata(client, muxc); + data->client = client; + + /* Get the mux out of reset if a reset GPIO is specified. */ + gpio = devm_gpiod_get_optional(&client->dev, "reset", GPIOD_OUT_LOW); + if (IS_ERR(gpio)) + return PTR_ERR(gpio); + + /* check device connection status */ + + if (client->dev.of_node == NULL) { + if (client->dev.platform_data == NULL) { + probe_disable = 1; + PCA954X_DEBUG("has no platform data config, set probe_disable = 1.\n"); + } else { + i2c_mux_pca954x_device = client->dev.platform_data; + probe_disable = i2c_mux_pca954x_device->probe_disable; + } + } else { + probe_disable = of_property_read_bool(of_node, "probe_disable"); + } + + /* Write the mux register at addr to verify + * that the mux is in fact present. This also + * initializes the mux to disconnected state. + */ + if (!probe_disable && (i2c_smbus_write_byte(client, 0) < 0)) { + dev_warn(&client->dev, "probe failed\n"); + return -ENODEV; + } + + match = of_match_device(of_match_ptr(pca954x_of_match), &client->dev); + if (match) + data->chip = of_device_get_match_data(&client->dev); + else + data->chip = &chips[id->driver_data]; + + data->last_chan = 0; /* force the first selection */ + + if (client->dev.of_node == NULL) { + idle_disconnect_dt = false; + } else { + idle_disconnect_dt = of_node && + of_property_read_bool(of_node, "i2c-mux-idle-disconnect"); + } + + if (client->dev.of_node) { + ret= of_pca954x_reset_data_init(data); + } else { + ret= pca954x_reset_data_init(data); + } + if (ret < 0) { + dev_err(&client->dev, "pca954x reset config err, ret:%d.\n", ret); + return ret; + } + + if (client->dev.of_node) { + ret = of_pca954x_irq_setup(muxc); + } else { + ret = pca954x_irq_setup(muxc); + } + if (ret) { + goto fail_del_adapters; + } + + if (client->dev.of_node == NULL) { + if (client->dev.platform_data == NULL) { + dynamic_nr = 1; + PCA954X_DEBUG("platform data is NULL, use dynamic adap number.\n"); + } else { + i2c_mux_pca954x_device = client->dev.platform_data; + data->pca9548_cfg_info.pca9548_base_nr = i2c_mux_pca954x_device->pca9548_base_nr; + if (data->pca9548_cfg_info.pca9548_base_nr == 0) { + dynamic_nr = 1; + PCA954X_DEBUG("pca9548_base_nr = 0, use dynamic adap number.\n"); + } else { + dynamic_nr = 0; + PCA954X_DEBUG("pca9548_base_nr:%u.\n", data->pca9548_cfg_info.pca9548_base_nr); + } + } + } else { + if (of_property_read_u32(of_node, "pca9548_base_nr", &data->pca9548_cfg_info.pca9548_base_nr)) { + + dynamic_nr = 1; + PCA954X_DEBUG("pca9548_base_nr not found, use dynamic adap number"); + } else { + dynamic_nr = 0; + PCA954X_DEBUG("pca9548_base_nr:%u.\n", data->pca9548_cfg_info.pca9548_base_nr); + } + } + + /* Now create an adapter for each channel */ + for (num = 0; num < data->chip->nchans; num++) { + bool idle_disconnect_pd = false; + if (dynamic_nr == 1) { + force = 0; /* dynamic adap number */ + } else { + force = data->pca9548_cfg_info.pca9548_base_nr + num; + } + + class = 0; /* no class by default */ + data->deselect |= (idle_disconnect_pd || + idle_disconnect_dt) << num; + + ret = i2c_mux_add_adapter(muxc, force, num, class); + if (ret) + goto fail_del_adapters; + } + + dev_info(&client->dev, + "registered %d multiplexed busses for I2C %s %s\n", + num, data->chip->muxtype == pca954x_ismux + ? "mux" : "switch", client->name); + + return 0; + +fail_del_adapters: + i2c_mux_del_adapters(muxc); + return ret; +} + +static int pca954x_remove(struct i2c_client *client) +{ + struct i2c_mux_core *muxc = i2c_get_clientdata(client); + struct pca954x *data = i2c_mux_priv(muxc); + int c, irq; + + if (data->irq) { + for (c = 0; c < data->chip->nchans; c++) { + irq = irq_find_mapping(data->irq, c); + irq_dispose_mapping(irq); + } + irq_domain_remove(data->irq); + } + + i2c_mux_del_adapters(muxc); + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static int pca954x_resume(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct i2c_mux_core *muxc = i2c_get_clientdata(client); + struct pca954x *data = i2c_mux_priv(muxc); + + data->last_chan = 0; + return i2c_smbus_write_byte(client, 0); +} +#endif + +static SIMPLE_DEV_PM_OPS(pca954x_pm, NULL, pca954x_resume); + +static struct i2c_driver pca954x_driver = { + .driver = { + .name = "wb_pca954x", + .pm = &pca954x_pm, + .of_match_table = of_match_ptr(pca954x_of_match), + }, + .probe = pca954x_probe, + .remove = pca954x_remove, + .id_table = pca954x_id, +}; + +module_i2c_driver(pca954x_driver); + +MODULE_AUTHOR("support"); +MODULE_DESCRIPTION("PCA954x I2C mux/switch driver"); +MODULE_LICENSE("GPL"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_i2c_mux_pca954x.h b/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_i2c_mux_pca954x.h new file mode 100644 index 000000000000..9cbe162782c5 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_i2c_mux_pca954x.h @@ -0,0 +1,67 @@ +#ifndef __WB_I2C_MUX_PCA954X_H__ +#define __WB_I2C_MUX_PCA954X_H__ + +#include + +#define mem_clear(data, size) memset((data), 0, (size)) + +typedef enum pca9548_reset_type_s { + PCA9548_RESET_NONE = 0, + PCA9548_RESET_I2C = 1, + PCA9548_RESET_GPIO = 2, + PCA9548_RESET_IO = 3, + PCA9548_RESET_FILE = 4, +} pca9548_reset_type_t; + +typedef struct i2c_attr_s { + uint32_t i2c_bus; + uint32_t i2c_addr; + uint32_t reg_offset; + uint32_t mask; + uint32_t reset_on; + uint32_t reset_off; +} i2c_attr_t; + +typedef struct io_attr_s { + uint32_t io_addr; + uint32_t mask; + uint32_t reset_on; + uint32_t reset_off; +} io_attr_t; + +typedef struct file_attr_s { + const char *dev_name; + uint32_t offset; + uint32_t mask; + uint32_t reset_on; + uint32_t reset_off; +} file_attr_t; + +typedef struct gpio_attr_s { + int gpio_init; + uint32_t gpio; + uint32_t reset_on; + uint32_t reset_off; +} gpio_attr_t; + +typedef struct i2c_mux_pca954x_device_s { + struct i2c_client *client; + uint32_t i2c_bus; + uint32_t i2c_addr; + uint32_t pca9548_base_nr; + uint32_t pca9548_reset_type; + uint32_t rst_delay_b; /* delay time before reset(us) */ + uint32_t rst_delay; /* reset time(us) */ + uint32_t rst_delay_a; /* delay time after reset(us) */ + bool probe_disable; + bool select_chan_check; + bool close_chan_force_reset; + union { + i2c_attr_t i2c_attr; + gpio_attr_t gpio_attr; + io_attr_t io_attr; + file_attr_t file_attr; + } attr; +} i2c_mux_pca954x_device_t; + +#endif diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_i2c_mux_pca9641.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_i2c_mux_pca9641.c new file mode 100644 index 000000000000..9945f6fcad25 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_i2c_mux_pca9641.c @@ -0,0 +1,1375 @@ +/* + * I2C multiplexer driver for PCA9541 bus master selector + * + * Copyright (c) 2010 Ericsson AB. + * + * Author: Guenter Roeck + * + * Derived from: + * pca954x.c + * + * Copyright (c) 2008-2009 Rodolfo Giometti + * Copyright (c) 2008-2009 Eurotech S.p.A. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "wb_i2c_mux_pca9641.h" + +/* + * The PCA9541 is a bus master selector. It supports two I2C masters connected + * to a single slave bus. + * + * Before each bus transaction, a master has to acquire bus ownership. After the + * transaction is complete, bus ownership has to be released. This fits well + * into the I2C multiplexer framework, which provides select and release + * functions for this purpose. For this reason, this driver is modeled as + * single-channel I2C bus multiplexer. + * + * This driver assumes that the two bus masters are controlled by two different + * hosts. If a single host controls both masters, platform code has to ensure + * that only one of the masters is instantiated at any given time. + */ + +#define PCA9541_CONTROL 0x01 +#define PCA9541_ISTAT 0x02 + +#define PCA9541_CTL_MYBUS (1 << 0) +#define PCA9541_CTL_NMYBUS (1 << 1) +#define PCA9541_CTL_BUSON (1 << 2) +#define PCA9541_CTL_NBUSON (1 << 3) +#define PCA9541_CTL_BUSINIT (1 << 4) +#define PCA9541_CTL_TESTON (1 << 6) +#define PCA9541_CTL_NTESTON (1 << 7) +#define PCA9541_ISTAT_INTIN (1 << 0) +#define PCA9541_ISTAT_BUSINIT (1 << 1) +#define PCA9541_ISTAT_BUSOK (1 << 2) +#define PCA9541_ISTAT_BUSLOST (1 << 3) +#define PCA9541_ISTAT_MYTEST (1 << 6) +#define PCA9541_ISTAT_NMYTEST (1 << 7) +#define PCA9641_ID 0x00 +#define PCA9641_ID_MAGIC 0x38 +#define PCA9641_CONTROL 0x01 +#define PCA9641_STATUS 0x02 +#define PCA9641_TIME 0x03 +#define PCA9641_CTL_LOCK_REQ BIT(0) +#define PCA9641_CTL_LOCK_GRANT BIT(1) +#define PCA9641_CTL_BUS_CONNECT BIT(2) +#define PCA9641_CTL_BUS_INIT BIT(3) +#define PCA9641_CTL_SMBUS_SWRST BIT(4) +#define PCA9641_CTL_IDLE_TIMER_DIS BIT(5) +#define PCA9641_CTL_SMBUS_DIS BIT(6) +#define PCA9641_CTL_PRIORITY BIT(7) +#define PCA9641_STS_OTHER_LOCK BIT(0) +#define PCA9641_STS_BUS_INIT_FAIL BIT(1) +#define PCA9641_STS_BUS_HUNG BIT(2) +#define PCA9641_STS_MBOX_EMPTY BIT(3) +#define PCA9641_STS_MBOX_FULL BIT(4) +#define PCA9641_STS_TEST_INT BIT(5) +#define PCA9641_STS_SCL_IO BIT(6) +#define PCA9641_STS_SDA_IO BIT(7) +#define PCA9641_RES_TIME 0x03 +#define BUSON (PCA9541_CTL_BUSON | PCA9541_CTL_NBUSON) +#define MYBUS (PCA9541_CTL_MYBUS | PCA9541_CTL_NMYBUS) +#define mybus(x) (!((x) & MYBUS) || ((x) & MYBUS) == MYBUS) +#define busoff(x) (!((x) & BUSON) || ((x) & BUSON) == BUSON) +#define BUSOFF(x, y) (!((x) & PCA9641_CTL_LOCK_GRANT) && \ + !((y) & PCA9641_STS_OTHER_LOCK)) +#define other_lock(x) ((x) & PCA9641_STS_OTHER_LOCK) +#define lock_grant(x) ((x) & PCA9641_CTL_LOCK_GRANT) + +#define PCA9641_RETRY_TIME (8) +#define PCA9641_RESET_DELAY (150) + +typedef struct i2c_muxs_struct_flag +{ + int nr; + char name[48]; + struct mutex update_lock; + int flag; +}i2c_mux_flag; + +i2c_mux_flag pca_flag = { + .flag = -1, +}; + +int pca9641_setmuxflag(int nr, int flag) +{ + if (pca_flag.nr == nr) { + pca_flag.flag = flag; + } + return 0; +} +EXPORT_SYMBOL(pca9641_setmuxflag); + +static int g_debug_info = 0; +static int g_debug_err = 0; + +module_param(g_debug_info, int, S_IRUGO | S_IWUSR); +module_param(g_debug_err, int, S_IRUGO | S_IWUSR); + +#define PCA_DEBUG(fmt, args...) do { \ + if (g_debug_info) { \ + printk(KERN_INFO "[pca9641][VER][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +#define PCA_DEBUG_ERR(fmt, args...) do { \ + if (g_debug_err) { \ + printk(KERN_ERR "[pca9641][ERR][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +/* arbitration timeouts, in jiffies */ +#define ARB_TIMEOUT (HZ / 8) /* 125 ms until forcing bus ownership */ +#define ARB2_TIMEOUT (HZ / 4) /* 250 ms until acquisition failure */ + +/* arbitration retry delays, in us */ +#define SELECT_DELAY_SHORT 50 +#define SELECT_DELAY_LONG 1000 +#define I2C_RETRY_TIMES (5) +#define I2C_RETRY_WAIT_TIMES (10) /*delay 10ms*/ + +typedef struct pca9641_cfg_info_s { + uint32_t pca9641_reset_type; + uint32_t rst_delay_b; /* delay time before reset(us) */ + uint32_t rst_delay; /* reset time(us) */ + uint32_t rst_delay_a; /* delay time after reset(us) */ + union { + i2c_attr_t i2c_attr; + gpio_attr_t gpio_attr; + io_attr_t io_attr; + file_attr_t file_attr; + } attr; +} pca9641_cfg_info_t; + +struct pca9541 { + struct i2c_client *client; + unsigned long select_timeout; + unsigned long arb_timeout; + uint32_t pca9641_nr; + pca9641_cfg_info_t pca9641_cfg_info; /* pca9641 reset cfg */ +}; + +static const struct i2c_device_id pca9541_id[] = { + {"wb_pca9541", 0}, + {"wb_pca9641", 1}, + {} +}; + +MODULE_DEVICE_TABLE(i2c, pca9541_id); + +#ifdef CONFIG_OF +static const struct of_device_id pca9541_of_match[] = { + { .compatible = "nxp,wb_pca9541" }, + { .compatible = "nxp,wb_pca9641" }, + {} +}; +MODULE_DEVICE_TABLE(of, pca9541_of_match); +#endif + +static int pca9641_gpio_init(gpio_attr_t *gpio_attr) +{ + int err; + + if (gpio_attr->gpio_init) { + PCA_DEBUG("gpio%d already init, do nothing.\n", gpio_attr->gpio); + return 0; + } + + PCA_DEBUG("gpio%d init.\n", gpio_attr->gpio); + err = gpio_request(gpio_attr->gpio, "pca9641_reset"); + if (err) { + goto error; + } + err = gpio_direction_output(gpio_attr->gpio, gpio_attr->reset_off); + if (err) { + gpio_free(gpio_attr->gpio); + goto error; + } + gpio_attr->gpio_init = 1; + return 0; +error: + PCA_DEBUG_ERR("pca9641_gpio_init failed, ret:%d.\n", err); + return err; +} + +static void pca9641_gpio_free(gpio_attr_t *gpio_attr) +{ + if (gpio_attr->gpio_init == 1) { + PCA_DEBUG("gpio%d release.\n", gpio_attr->gpio); + gpio_free(gpio_attr->gpio); + gpio_attr->gpio_init = 0; + } + return; +} + +static int pca9641_reset_file_read(const char *path, uint32_t pos, uint8_t *val, size_t size) +{ + int ret; + struct file *filp; + loff_t tmp_pos; + + filp = filp_open(path, O_RDONLY, 0); + if (IS_ERR(filp)) { + PCA_DEBUG_ERR("read open failed errno = %ld\r\n", -PTR_ERR(filp)); + filp = NULL; + goto exit; + } + + tmp_pos = (loff_t)pos; + ret = kernel_read(filp, val, size, &tmp_pos); + if (ret < 0) { + PCA_DEBUG_ERR("kernel_read failed, path=%s, addr=0x%x, size=%ld, ret=%d\r\n", path, pos, size, ret); + goto exit; + } + + filp_close(filp, NULL); + + return ret; + +exit: + if (filp != NULL) { + filp_close(filp, NULL); + } + + return -1; +} + +static int pca9641_reset_file_write(const char *path, uint32_t pos, uint8_t *val, size_t size) +{ + + int ret; + struct file *filp; + loff_t tmp_pos; + + filp = filp_open(path, O_RDWR, 777); + if (IS_ERR(filp)) { + PCA_DEBUG_ERR("write open failed errno = %ld\r\n", -PTR_ERR(filp)); + filp = NULL; + goto exit; + } + + tmp_pos = (loff_t)pos; + ret = kernel_write(filp, val, size, &tmp_pos); + if (ret < 0) { + PCA_DEBUG_ERR("kernel_write failed, path=%s, addr=0x%x, size=%ld, ret=%d\r\n", path, pos, size, ret); + goto exit; + } + + vfs_fsync(filp, 1); + filp_close(filp, NULL); + + return ret; + +exit: + if (filp != NULL) { + filp_close(filp, NULL); + } + + return -1; +} + +static int pca9641_reset_i2c_read(uint32_t bus, uint32_t addr, uint32_t offset_addr, + unsigned char *buf, uint32_t size) +{ + struct file *fp; + struct i2c_client client; + char i2c_path[32]; + int i, j; + int rv; + + rv = 0; + mem_clear(i2c_path, sizeof(i2c_path)); + snprintf(i2c_path, sizeof(i2c_path), "/dev/i2c-%d", bus); + fp = filp_open(i2c_path, O_RDWR, S_IRUSR | S_IWUSR); + if (IS_ERR(fp)) { + PCA_DEBUG_ERR("i2c open fail.\n"); + return -1; + } + memcpy(&client, fp->private_data, sizeof(struct i2c_client)); + client.addr = addr; + for (j = 0; j < size; j++) { + for (i = 0; i < I2C_RETRY_TIMES; i++) { + rv = i2c_smbus_read_byte_data(&client, (offset_addr + j)); + if (rv < 0) { + PCA_DEBUG_ERR("i2c read failed, try again.\n"); + msleep(I2C_RETRY_WAIT_TIMES); + if (i >= (I2C_RETRY_TIMES - 1)) { + goto out; + } + continue; + } + *(buf + j) = (unsigned char)rv; + break; + } + } +out: + filp_close(fp, NULL); + return rv; +} + +static int pca9641_reset_i2c_write(uint32_t bus, uint32_t dev_addr, uint32_t offset_addr, + uint8_t write_buf) +{ + struct file *fp; + struct i2c_client client; + char i2c_path[32]; + int i; + int rv; + + rv = 0; + mem_clear(i2c_path, sizeof(i2c_path)); + snprintf(i2c_path, sizeof(i2c_path), "/dev/i2c-%d", bus); + fp = filp_open(i2c_path, O_RDWR, S_IRUSR | S_IWUSR); + if (IS_ERR(fp)) { + PCA_DEBUG_ERR("i2c open fail.\n"); + return -1; + } + memcpy(&client, fp->private_data, sizeof(struct i2c_client)); + client.addr = dev_addr; + for (i = 0; i < I2C_RETRY_TIMES; i++) { + rv = i2c_smbus_write_byte_data(&client, offset_addr, write_buf); + if (rv < 0) { + PCA_DEBUG_ERR("i2c write failed, try again.\n"); + msleep(I2C_RETRY_WAIT_TIMES); + if (i >= (I2C_RETRY_TIMES - 1)) { + goto out; + } + continue; + } + break; + } +out: + filp_close(fp, NULL); + return rv; +} + +static int pca9641_do_file_reset(struct i2c_mux_core *muxc) +{ + int ret, timeout, err; + struct pca9541 *data; + pca9641_cfg_info_t *reset_cfg; + file_attr_t *file_attr; + u8 val; + + data = i2c_mux_priv(muxc); + reset_cfg = &data->pca9641_cfg_info; + file_attr = &reset_cfg->attr.file_attr; + ret = -1; + + PCA_DEBUG("rst_delay_b:%u, rst_delay:%u, rst_delay_a:%u.\n", + reset_cfg->rst_delay_b, reset_cfg->rst_delay, reset_cfg->rst_delay_a); + PCA_DEBUG("dev_name:%s, offset:0x%x, mask:0x%x, on:0x%x, off:0x%x.\n", + file_attr->dev_name, file_attr->offset, file_attr->mask, + file_attr->reset_on, file_attr->reset_off); + + if (reset_cfg->rst_delay_b) { + udelay(reset_cfg->rst_delay_b); + } + + err = pca9641_reset_file_read(file_attr->dev_name, file_attr->offset, &val, sizeof(val)); + if (err < 0) { + goto out; + } + + val &= ~(file_attr->mask); + val |= file_attr->reset_on; + err = pca9641_reset_file_write(file_attr->dev_name, file_attr->offset, &val, sizeof(val)); + if (err < 0) { + goto out; + } + + if (reset_cfg->rst_delay) { + udelay(reset_cfg->rst_delay); + } + + val &= ~(file_attr->mask); + val |= file_attr->reset_off; + err = pca9641_reset_file_write(file_attr->dev_name, file_attr->offset, &val, sizeof(val)); + if (err < 0) { + goto out; + } + + timeout = reset_cfg->rst_delay_a; + while (timeout > 0) { + udelay(1); + err = pca9641_reset_file_read(file_attr->dev_name, file_attr->offset, &val, sizeof(val)); + if (err < 0) { + goto out; + } + val &= (file_attr->mask); + if (val == file_attr->reset_off) { + ret = 0; + PCA_DEBUG("pca9641_do_file_reset success.\n"); + break; + } + if (timeout >= 1000 && (timeout % 1000 == 0)) { + schedule(); + } + timeout--; + } + if (ret < 0) { + PCA_DEBUG_ERR("pca9641_do_file_reset timeout.\n"); + } +out: + if (err < 0) { + PCA_DEBUG_ERR("pca9641_do_file_reset file rd/wr failed, ret:%d.\n", err); + } + + return ret; +} + +static int pca9641_do_io_reset(struct i2c_mux_core *muxc) +{ + int ret, timeout; + struct pca9541 *data; + pca9641_cfg_info_t *reset_cfg; + io_attr_t *io_attr; + u8 val; + + data = i2c_mux_priv(muxc); + reset_cfg = &data->pca9641_cfg_info; + io_attr = &reset_cfg->attr.io_attr; + + PCA_DEBUG("rst_delay_b:%u, rst_delay:%u, rst_delay_a:%u.\n", + reset_cfg->rst_delay_b, reset_cfg->rst_delay, reset_cfg->rst_delay_a); + PCA_DEBUG("io_addr:0x%x, mask:0x%x, on:0x%x, off:0x%x.\n", + io_attr->io_addr, io_attr->mask, io_attr->reset_on, io_attr->reset_off); + + if (reset_cfg->rst_delay_b) { + udelay(reset_cfg->rst_delay_b); + } + + val = inb(io_attr->io_addr); + val &= ~(io_attr->mask); + val |= io_attr->reset_on; + outb(val, io_attr->io_addr); + + if (reset_cfg->rst_delay) { + udelay(reset_cfg->rst_delay); + } + + val &= ~(io_attr->mask); + val |= io_attr->reset_off; + outb(val, io_attr->io_addr); + + ret = -1; + timeout = reset_cfg->rst_delay_a; + while (timeout > 0) { + udelay(1); + val = inb(io_attr->io_addr); + val &= (io_attr->mask); + if (val == io_attr->reset_off) { + ret = 0; + PCA_DEBUG("pca9641_do_io_reset success.\n"); + break; + } + if (timeout >= 1000 && (timeout % 1000 == 0)) { + schedule(); + } + timeout--; + } + + if (ret < 0) { + PCA_DEBUG_ERR("pca9641_do_io_reset timeout.\n"); + } + + return ret; +} + +static int pca9641_do_gpio_reset(struct i2c_mux_core *muxc) +{ + int ret, timeout; + struct pca9541 *data; + pca9641_cfg_info_t *reset_cfg; + gpio_attr_t *gpio_attr; + u8 val; + + data = i2c_mux_priv(muxc); + reset_cfg = &data->pca9641_cfg_info; + gpio_attr = &reset_cfg->attr.gpio_attr; + + ret = pca9641_gpio_init(gpio_attr); + if (ret) { + return -1; + } + + if (reset_cfg->rst_delay_b) { + udelay(reset_cfg->rst_delay_b); + } + + __gpio_set_value(gpio_attr->gpio, gpio_attr->reset_on); + + if (reset_cfg->rst_delay) { + udelay(reset_cfg->rst_delay); + } + + __gpio_set_value(gpio_attr->gpio, gpio_attr->reset_off); + ret = -1; + timeout = reset_cfg->rst_delay_a; + while (timeout > 0) { + udelay(1); + val = __gpio_get_value(gpio_attr->gpio); + if (val == gpio_attr->reset_off) { + ret = 0; + PCA_DEBUG("pca9641_do_gpio_reset success.\n"); + break; + } + if (timeout >= 1000 && (timeout % 1000 == 0)) { + /* 1MS schedule*/ + schedule(); + } + timeout--; + } + + if (ret < 0) { + PCA_DEBUG_ERR("pca9641_do_gpio_reset timeout.\n"); + } + + pca9641_gpio_free(gpio_attr); + return ret; +} + +static int pca9641_do_i2c_reset(struct i2c_mux_core *muxc) +{ + int ret, timeout, err; + struct pca9541 *data; + pca9641_cfg_info_t *reset_cfg; + i2c_attr_t *i2c_attr; + u8 val; + + data = i2c_mux_priv(muxc); + reset_cfg = &data->pca9641_cfg_info; + i2c_attr = &reset_cfg->attr.i2c_attr; + ret = -1; + + PCA_DEBUG("rst_delay_b:%u, rst_delay:%u, rst_delay_a:%u.\n", + reset_cfg->rst_delay_b, reset_cfg->rst_delay, reset_cfg->rst_delay_a); + PCA_DEBUG("bus:0x%x, addr:0x%x, reg:0x%x, mask:0x%x, on:0x%x, off:0x%x.\n", + i2c_attr->i2c_bus, i2c_attr->i2c_addr, i2c_attr->reg_offset, + i2c_attr->mask, i2c_attr->reset_on, i2c_attr->reset_off); + + if (reset_cfg->rst_delay_b) { + udelay(reset_cfg->rst_delay_b); + } + + err = pca9641_reset_i2c_read(i2c_attr->i2c_bus, i2c_attr->i2c_addr, + i2c_attr->reg_offset, &val, sizeof(val)); + if (err < 0) { + goto out; + } + + val &= ~(i2c_attr->mask); + val |= i2c_attr->reset_on; + err = pca9641_reset_i2c_write(i2c_attr->i2c_bus, i2c_attr->i2c_addr, + i2c_attr->reg_offset, val); + if (err < 0) { + goto out; + } + + if (reset_cfg->rst_delay) { + udelay(reset_cfg->rst_delay); + } + + val &= ~(i2c_attr->mask); + val |= i2c_attr->reset_off; + err = pca9641_reset_i2c_write(i2c_attr->i2c_bus, i2c_attr->i2c_addr, + i2c_attr->reg_offset, val); + if (err < 0) { + goto out; + } + + timeout = reset_cfg->rst_delay_a; + while (timeout > 0) { + udelay(1); + err = pca9641_reset_i2c_read(i2c_attr->i2c_bus, i2c_attr->i2c_addr, + i2c_attr->reg_offset, &val, sizeof(val)); + if (err < 0) { + goto out; + } + val &= (i2c_attr->mask); + if (val == i2c_attr->reset_off) { + ret = 0; + PCA_DEBUG("pca9641_do_i2c_reset success.\n"); + break; + } + if (timeout >= 1000 && (timeout % 1000 == 0)) { + schedule(); + } + timeout--; + } + if (ret < 0) { + PCA_DEBUG_ERR("pca9641_do_i2c_reset timeout.\n"); + } +out: + if (err < 0) { + PCA_DEBUG_ERR("pca9641_do_i2c_reset i2c op failed, ret:%d.\n", err); + } + return ret; +} + +static int pca9641_do_reset(struct i2c_mux_core *muxc) +{ + int ret; + struct pca9541 *data; + + data = i2c_mux_priv(muxc); + if (data->pca9641_cfg_info.pca9641_reset_type == PCA9641_RESET_NONE) { + ret = -1; + PCA_DEBUG("Don't need to reset.\n"); + } else if (data->pca9641_cfg_info.pca9641_reset_type == PCA9641_RESET_I2C) { + ret = pca9641_do_i2c_reset(muxc); + } else if (data->pca9641_cfg_info.pca9641_reset_type == PCA9641_RESET_GPIO) { + ret = pca9641_do_gpio_reset(muxc); + } else if (data->pca9641_cfg_info.pca9641_reset_type == PCA9641_RESET_IO) { + ret = pca9641_do_io_reset(muxc); + } else if (data->pca9641_cfg_info.pca9641_reset_type == PCA9641_RESET_FILE) { + ret = pca9641_do_file_reset(muxc); + } else { + ret = -1; + PCA_DEBUG_ERR("Unsupport reset type:0x%x.\n", + data->pca9641_cfg_info.pca9641_reset_type); + } + + if (ret < 0) { + PCA_DEBUG_ERR("pca9641_reset_ctrl failed, reset type:%u, ret:%d.\n", + data->pca9641_cfg_info.pca9641_reset_type, ret); + } else { + udelay(PCA9641_RESET_DELAY); + } + return ret; +} + +/* + * Write to chip register. Don't use i2c_transfer()/i2c_smbus_xfer() + * as they will try to lock the adapter a second time. + */ +static int pca9541_reg_write(struct i2c_client *client, u8 command, u8 val) +{ + struct i2c_adapter *adap = client->adapter; + int ret; + + if (adap->algo->master_xfer) { + struct i2c_msg msg; + char buf[2]; + + msg.addr = client->addr; + msg.flags = 0; + msg.len = 2; + buf[0] = command; + buf[1] = val; + msg.buf = buf; + ret = __i2c_transfer(adap, &msg, 1); + } else { + union i2c_smbus_data data; + + data.byte = val; + ret = adap->algo->smbus_xfer(adap, client->addr, + client->flags, + I2C_SMBUS_WRITE, + command, + I2C_SMBUS_BYTE_DATA, &data); + } + + return ret; +} + +/* + * Read from chip register. Don't use i2c_transfer()/i2c_smbus_xfer() + * as they will try to lock adapter a second time. + */ +static int pca9541_reg_read(struct i2c_client *client, u8 command) +{ + struct i2c_adapter *adap = client->adapter; + int ret; + u8 val; + + if (adap->algo->master_xfer) { + struct i2c_msg msg[2] = { + { + .addr = client->addr, + .flags = 0, + .len = 1, + .buf = &command + }, + { + .addr = client->addr, + .flags = I2C_M_RD, + .len = 1, + .buf = &val + } + }; + ret = __i2c_transfer(adap, msg, 2); + if (ret == 2) + ret = val; + else if (ret >= 0) + ret = -EIO; + } else { + union i2c_smbus_data data; + + ret = adap->algo->smbus_xfer(adap, client->addr, + client->flags, + I2C_SMBUS_READ, + command, + I2C_SMBUS_BYTE_DATA, &data); + if (!ret) + ret = data.byte; + } + return ret; +} + +/* + * Arbitration management functions + */ + +/* Release bus. Also reset NTESTON and BUSINIT if it was set. */ +static void pca9541_release_bus(struct i2c_client *client) +{ + int reg; + + reg = pca9541_reg_read(client, PCA9541_CONTROL); + if (reg >= 0 && !busoff(reg) && mybus(reg)) + pca9541_reg_write(client, PCA9541_CONTROL, + (reg & PCA9541_CTL_NBUSON) >> 1); +} + +/* + * Arbitration is defined as a two-step process. A bus master can only activate + * the slave bus if it owns it; otherwise it has to request ownership first. + * This multi-step process ensures that access contention is resolved + * gracefully. + * + * Bus Ownership Other master Action + * state requested access + * ---------------------------------------------------- + * off - yes wait for arbitration timeout or + * for other master to drop request + * off no no take ownership + * off yes no turn on bus + * on yes - done + * on no - wait for arbitration timeout or + * for other master to release bus + * + * The main contention point occurs if the slave bus is off and both masters + * request ownership at the same time. In this case, one master will turn on + * the slave bus, believing that it owns it. The other master will request + * bus ownership. Result is that the bus is turned on, and master which did + * _not_ own the slave bus before ends up owning it. + */ + +/* Control commands per PCA9541 datasheet */ +static const u8 pca9541_control[16] = { + 4, 0, 1, 5, 4, 4, 5, 5, 0, 0, 1, 1, 0, 4, 5, 1 +}; + +/* + * Channel arbitration + * + * Return values: + * <0: error + * 0 : bus not acquired + * 1 : bus acquired + */ +static int pca9541_arbitrate(struct i2c_client *client) +{ + struct i2c_mux_core *muxc = i2c_get_clientdata(client); + struct pca9541 *data = i2c_mux_priv(muxc); + int reg; + + reg = pca9541_reg_read(client, PCA9541_CONTROL); + if (reg < 0) + return reg; + + if (busoff(reg)) { + int istat; + /* + * Bus is off. Request ownership or turn it on unless + * other master requested ownership. + */ + istat = pca9541_reg_read(client, PCA9541_ISTAT); + if (!(istat & PCA9541_ISTAT_NMYTEST) + || time_is_before_eq_jiffies(data->arb_timeout)) { + /* + * Other master did not request ownership, + * or arbitration timeout expired. Take the bus. + */ + pca9541_reg_write(client, + PCA9541_CONTROL, + pca9541_control[reg & 0x0f] + | PCA9541_CTL_NTESTON); + data->select_timeout = SELECT_DELAY_SHORT; + } else { + /* + * Other master requested ownership. + * Set extra long timeout to give it time to acquire it. + */ + data->select_timeout = SELECT_DELAY_LONG * 2; + } + } else if (mybus(reg)) { + /* + * Bus is on, and we own it. We are done with acquisition. + * Reset NTESTON and BUSINIT, then return success. + */ + if (reg & (PCA9541_CTL_NTESTON | PCA9541_CTL_BUSINIT)) + pca9541_reg_write(client, + PCA9541_CONTROL, + reg & ~(PCA9541_CTL_NTESTON + | PCA9541_CTL_BUSINIT)); + return 1; + } else { + /* + * Other master owns the bus. + * If arbitration timeout has expired, force ownership. + * Otherwise request it. + */ + data->select_timeout = SELECT_DELAY_LONG; + if (time_is_before_eq_jiffies(data->arb_timeout)) { + /* Time is up, take the bus and reset it. */ + pca9541_reg_write(client, + PCA9541_CONTROL, + pca9541_control[reg & 0x0f] + | PCA9541_CTL_BUSINIT + | PCA9541_CTL_NTESTON); + } else { + /* Request bus ownership if needed */ + if (!(reg & PCA9541_CTL_NTESTON)) + pca9541_reg_write(client, + PCA9541_CONTROL, + reg | PCA9541_CTL_NTESTON); + } + } + return 0; +} + +static int pca9541_select_chan(struct i2c_mux_core *muxc, u32 chan) +{ + struct pca9541 *data = i2c_mux_priv(muxc); + struct i2c_client *client = data->client; + int ret; + unsigned long timeout = jiffies + ARB2_TIMEOUT; + /* give up after this time */ + + data->arb_timeout = jiffies + ARB_TIMEOUT; + /* force bus ownership after this time */ + + do { + ret = pca9541_arbitrate(client); + if (ret) + return ret < 0 ? ret : 0; + + if (data->select_timeout == SELECT_DELAY_SHORT) + udelay(data->select_timeout); + else + msleep(data->select_timeout / 1000); + } while (time_is_after_eq_jiffies(timeout)); + + dev_warn(&client->dev, "pca9541 select channel timeout.\n"); + return -ETIMEDOUT; +} + +static int pca9541_release_chan(struct i2c_mux_core *muxc, u32 chan) +{ + struct pca9541 *data = i2c_mux_priv(muxc); + struct i2c_client *client = data->client; + pca9541_release_bus(client); + return 0; +} + +/* +* Arbitration management functions +*/ +static void pca9641_release_bus(struct i2c_client *client) +{ + pca9541_reg_write(client, PCA9641_CONTROL, 0x80); //master 0x80 +} + +/* +* Channel arbitration +* +* Return values: +* <0: error +* 0 : bus not acquired +* 1 : bus acquired +*/ +static int pca9641_arbitrate(struct i2c_client *client) +{ + struct i2c_mux_core *muxc = i2c_get_clientdata(client); + struct pca9541 *data = i2c_mux_priv(muxc); + int reg_ctl, reg_sts; + + reg_ctl = pca9541_reg_read(client, PCA9641_CONTROL); + if (reg_ctl < 0) { + PCA_DEBUG_ERR("pca9641 read control register failed, ret:%d.\n", reg_ctl); + return reg_ctl; + } + + reg_sts = pca9541_reg_read(client, PCA9641_STATUS); + if (reg_sts < 0) { + PCA_DEBUG_ERR("pca9641 read status register failed, ret:%d.\n", reg_sts); + return reg_sts; + } + + if (BUSOFF(reg_ctl, reg_sts)) { + /* + * Bus is off. Request ownership or turn it on unless + * other master requested ownership. + */ + reg_ctl |= PCA9641_CTL_LOCK_REQ; + pca9541_reg_write(client, PCA9641_CONTROL, reg_ctl); + reg_ctl = pca9541_reg_read(client, PCA9641_CONTROL); + if (reg_ctl < 0) { + PCA_DEBUG_ERR("Bus is off, but read control register failed, ret:%d.\n", reg_ctl); + return reg_ctl; + } + + if (lock_grant(reg_ctl)) { + /* + * Other master did not request ownership, + * or arbitration timeout expired. Take the bus. + */ + PCA_DEBUG("Bus is off, get pca9641 arbitration success.\n"); + reg_ctl |= PCA9641_CTL_BUS_CONNECT | PCA9641_CTL_LOCK_REQ; + pca9541_reg_write(client, PCA9641_CONTROL, reg_ctl); + return 1; + } else { + /* + * Other master requested ownership. + * Set extra long timeout to give it time to acquire it. + */ + PCA_DEBUG("Bus is off, but get pca9641 arbitration failed.\n"); + data->select_timeout = SELECT_DELAY_LONG * 2; + } + } else if (lock_grant(reg_ctl)) { + /* + * Bus is on, and we own it. We are done with acquisition. + */ + PCA_DEBUG("Bus is on, get pca9641 arbitration success.\n"); + reg_ctl |= PCA9641_CTL_BUS_CONNECT | PCA9641_CTL_LOCK_REQ; + pca9541_reg_write(client, PCA9641_CONTROL, reg_ctl); + return 1; + } else if (other_lock(reg_sts)) { + /* + * Other master owns the bus. + * If arbitration timeout has expired, force ownership. + * Otherwise request it. + */ + PCA_DEBUG("Other master owns the bus, try to request it.\n"); + data->select_timeout = SELECT_DELAY_LONG; + reg_ctl |= PCA9641_CTL_LOCK_REQ; + pca9541_reg_write(client, PCA9641_CONTROL, reg_ctl); + } + return 0; +} + +int pca9641_select_chan_single(struct i2c_mux_core *muxc, u32 chan) +{ + struct pca9541 *data = i2c_mux_priv(muxc); + struct i2c_client *client = data->client; + int ret; + int result; + unsigned long msleep_time; + unsigned long timeout = jiffies + ARB2_TIMEOUT; + /* give up after this time */ + data->arb_timeout = jiffies + ARB_TIMEOUT; + /* force bus ownership after this time */ + for (result = 0 ; result < PCA9641_RETRY_TIME ; result ++) { + do { + ret = pca9641_arbitrate(client); + if (ret) { + return ret < 0 ? -EIO : 0; + } + msleep_time = data->select_timeout / 1000; + if (msleep_time < 1) { + msleep(1); + } else { + msleep(msleep_time); + } + } while (time_is_after_eq_jiffies(timeout)); + timeout = jiffies + ARB2_TIMEOUT; + } + dev_warn(&client->dev, "pca9641 select channel timeout.\n"); + return -ETIMEDOUT; +} + +static int pca9641_select_chan(struct i2c_mux_core *muxc, u32 chan) +{ + int ret, rv; + + ret = pca9641_select_chan_single(muxc, chan); + if (ret < 0) { + PCA_DEBUG_ERR("pca9641 select channel failed, ret:%d, try to reset pca9641.\n", ret); + rv = pca9641_do_reset(muxc); + + if (rv < 0) { + PCA_DEBUG_ERR("pca9641 reset failed, rv:%d.\n", rv); + return ret; + } + + ret = pca9641_select_chan_single(muxc, chan); + if (ret < 0) { + PCA_DEBUG_ERR("after pca9641 reset, select channel still failed, ret:%d.\n", ret); + } + } + return ret; +} + +static int pca9641_release_chan(struct i2c_mux_core *muxc, u32 chan) +{ + struct pca9541 *data = i2c_mux_priv(muxc); + struct i2c_client *client = data->client; + if (pca_flag.flag) { + pca9641_release_bus(client); + } + return 0; +} + +static int pca9641_detect_id(struct i2c_client *client) +{ + int reg; + + reg = pca9541_reg_read(client, PCA9641_ID); + if (reg == PCA9641_ID_MAGIC) + return 1; + else + return 0; +} + +static int pca9641_recordflag(struct i2c_adapter *adap) { + if (pca_flag.flag != -1) { + pr_err(" %s %d has init already!!!", __func__, __LINE__); + return -1 ; + } + pca_flag.nr = adap->nr; + PCA_DEBUG(" adap->nr:%d\n", adap->nr); + snprintf(pca_flag.name, sizeof(pca_flag.name),adap->name); + return 0; +} + +static int of_pca9641_reset_data_init(struct pca9541 *data) +{ + int err; + struct device *dev = &data->client->dev; + pca9641_cfg_info_t *reset_cfg; + + reset_cfg = &data->pca9641_cfg_info; + if (dev == NULL || dev->of_node == NULL) { + PCA_DEBUG("dev or dev->of_node is NUll, no reset.\n"); + reset_cfg->pca9641_reset_type = PCA9641_RESET_NONE; + return 0; + } + + if (of_property_read_u32(dev->of_node, "pca9641_reset_type", &reset_cfg->pca9641_reset_type)) { + + PCA_DEBUG("pca9641_reset_type not found, no reset.\n"); + reset_cfg->pca9641_reset_type = PCA9641_RESET_NONE; + return 0; + } + err = of_property_read_u32(dev->of_node, "rst_delay_b", &reset_cfg->rst_delay_b); + err |= of_property_read_u32(dev->of_node, "rst_delay", &reset_cfg->rst_delay); + err |= of_property_read_u32(dev->of_node, "rst_delay_a", &reset_cfg->rst_delay_a); + + if (err) { + goto dts_config_err; + } + PCA_DEBUG("reset_type:0x%x, rst_delay_b:0x%x, rst_delay:0x%x, rst_delay_a:0x%x.\n", + reset_cfg->pca9641_reset_type, reset_cfg->rst_delay_b, + reset_cfg->rst_delay, reset_cfg->rst_delay_a); + + if (reset_cfg->pca9641_reset_type == PCA9641_RESET_I2C) { + + PCA_DEBUG("reset by i2c.\n"); + err = of_property_read_u32(dev->of_node, "i2c_bus", &reset_cfg->attr.i2c_attr.i2c_bus); + err |=of_property_read_u32(dev->of_node, "i2c_addr", &reset_cfg->attr.i2c_attr.i2c_addr); + err |=of_property_read_u32(dev->of_node, "reg_offset", &reset_cfg->attr.i2c_attr.reg_offset); + err |=of_property_read_u32(dev->of_node, "mask", &reset_cfg->attr.i2c_attr.mask); + err |=of_property_read_u32(dev->of_node, "reset_on", &reset_cfg->attr.i2c_attr.reset_on); + err |=of_property_read_u32(dev->of_node, "reset_off", &reset_cfg->attr.i2c_attr.reset_off); + if (err) { + goto dts_config_err; + } + PCA_DEBUG("bus:%u, addr:0x%x, offset:0x%x, mask:0x%x, on:0x%x, off:0x%x.\n", + reset_cfg->attr.i2c_attr.i2c_bus, reset_cfg->attr.i2c_attr.i2c_addr, + reset_cfg->attr.i2c_attr.reg_offset, reset_cfg->attr.i2c_attr.mask, + reset_cfg->attr.i2c_attr.reset_on, reset_cfg->attr.i2c_attr.reset_off); + } else if (reset_cfg->pca9641_reset_type == PCA9641_RESET_GPIO) { + + PCA_DEBUG("reset by gpio.\n"); + err = of_property_read_u32(dev->of_node, "gpio", &reset_cfg->attr.gpio_attr.gpio); + err |=of_property_read_u32(dev->of_node, "reset_on", &reset_cfg->attr.gpio_attr.reset_on); + err |=of_property_read_u32(dev->of_node, "reset_off", &reset_cfg->attr.gpio_attr.reset_off); + if (err) { + goto dts_config_err; + } + PCA_DEBUG("gpio number:%u, reset_on:0x%x, reset_off:0x%x.\n", + reset_cfg->attr.gpio_attr.gpio, reset_cfg->attr.gpio_attr.reset_on, + reset_cfg->attr.gpio_attr.reset_off); + reset_cfg->attr.gpio_attr.gpio_init = 0; + } else if (reset_cfg->pca9641_reset_type == PCA9641_RESET_IO) { + + PCA_DEBUG("reset by io.\n"); + err = of_property_read_u32(dev->of_node, "io_addr", &reset_cfg->attr.io_attr.io_addr); + err |=of_property_read_u32(dev->of_node, "mask", &reset_cfg->attr.io_attr.mask); + err |=of_property_read_u32(dev->of_node, "reset_on", &reset_cfg->attr.io_attr.reset_on); + err |=of_property_read_u32(dev->of_node, "reset_off", &reset_cfg->attr.io_attr.reset_off); + if (err) { + goto dts_config_err; + } + PCA_DEBUG("io_addr:0x%x, mask:0x%x, reset_on:0x%x, reset_off:0x%x.\n", + reset_cfg->attr.io_attr.io_addr, reset_cfg->attr.io_attr.mask, + reset_cfg->attr.io_attr.reset_on, reset_cfg->attr.io_attr.reset_off); + } else if (reset_cfg->pca9641_reset_type == PCA9641_RESET_FILE) { + + PCA_DEBUG("reset by file.\n"); + err = of_property_read_string(dev->of_node, "dev_name", &reset_cfg->attr.file_attr.dev_name); + err |=of_property_read_u32(dev->of_node, "offset", &reset_cfg->attr.file_attr.offset); + err |=of_property_read_u32(dev->of_node, "mask", &reset_cfg->attr.file_attr.mask); + err |=of_property_read_u32(dev->of_node, "reset_on", &reset_cfg->attr.file_attr.reset_on); + err |=of_property_read_u32(dev->of_node, "reset_off", &reset_cfg->attr.file_attr.reset_off); + if (err) { + goto dts_config_err; + } + PCA_DEBUG("dev_name:%s, mask:0x%x, reset_on:0x%x, reset_off:0x%x.\n", + reset_cfg->attr.file_attr.dev_name, reset_cfg->attr.file_attr.mask, + reset_cfg->attr.file_attr.reset_on, reset_cfg->attr.file_attr.reset_off); + } else { + PCA_DEBUG_ERR("Unsupport reset type:%d.\n", reset_cfg->pca9641_reset_type); + goto dts_config_err; + } + return 0; +dts_config_err: + PCA_DEBUG_ERR("dts config error, ret:%d.\n", err); + return -EINVAL; +} + +static int pca9641_reset_data_init(struct pca9541 *data) +{ + pca9641_cfg_info_t *reset_cfg; + i2c_mux_pca9641_device_t *i2c_mux_pca9641_device; + + if (data->client->dev.platform_data == NULL) { + PCA_DEBUG("pca9641 has no reset platform data config.\n"); + return 0; + } + reset_cfg = &data->pca9641_cfg_info; + i2c_mux_pca9641_device = data->client->dev.platform_data; + reset_cfg->pca9641_reset_type = i2c_mux_pca9641_device->pca9641_reset_type; + if (reset_cfg->pca9641_reset_type == PCA9641_RESET_NONE) { + PCA_DEBUG("pca9641 has no reset function.\n"); + return 0; + } + + reset_cfg->rst_delay_b = i2c_mux_pca9641_device->rst_delay_b; + reset_cfg->rst_delay = i2c_mux_pca9641_device->rst_delay; + reset_cfg->rst_delay_a = i2c_mux_pca9641_device->rst_delay_a; + PCA_DEBUG("reset_type:0x%x, rst_delay_b:0x%x, rst_delay:0x%x, rst_delay_a:0x%x.\n", + reset_cfg->pca9641_reset_type, reset_cfg->rst_delay_b, + reset_cfg->rst_delay, reset_cfg->rst_delay_a); + + if (reset_cfg->pca9641_reset_type == PCA9641_RESET_I2C) { + + PCA_DEBUG("reset by i2c.\n"); + reset_cfg->attr.i2c_attr.i2c_bus = i2c_mux_pca9641_device->attr.i2c_attr.i2c_bus; + reset_cfg->attr.i2c_attr.i2c_addr = i2c_mux_pca9641_device->attr.i2c_attr.i2c_addr; + reset_cfg->attr.i2c_attr.reg_offset = i2c_mux_pca9641_device->attr.i2c_attr.reg_offset; + reset_cfg->attr.i2c_attr.mask = i2c_mux_pca9641_device->attr.i2c_attr.mask; + reset_cfg->attr.i2c_attr.reset_on = i2c_mux_pca9641_device->attr.i2c_attr.reset_on; + reset_cfg->attr.i2c_attr.reset_off = i2c_mux_pca9641_device->attr.i2c_attr.reset_off; + PCA_DEBUG("bus:%u, addr:0x%x, offset:0x%x, mask:0x%x, on:0x%x, off:0x%x.\n", + reset_cfg->attr.i2c_attr.i2c_bus, reset_cfg->attr.i2c_attr.i2c_addr, + reset_cfg->attr.i2c_attr.reg_offset, reset_cfg->attr.i2c_attr.mask, + reset_cfg->attr.i2c_attr.reset_on, reset_cfg->attr.i2c_attr.reset_off); + } else if (reset_cfg->pca9641_reset_type == PCA9641_RESET_GPIO) { + + PCA_DEBUG("reset by gpio.\n"); + reset_cfg->attr.gpio_attr.gpio = i2c_mux_pca9641_device->attr.gpio_attr.gpio; + reset_cfg->attr.gpio_attr.reset_on = i2c_mux_pca9641_device->attr.gpio_attr.reset_on; + reset_cfg->attr.gpio_attr.reset_off = i2c_mux_pca9641_device->attr.gpio_attr.reset_off; + PCA_DEBUG("gpio number:%u, reset_on:0x%x, reset_off:0x%x.\n", + reset_cfg->attr.gpio_attr.gpio, reset_cfg->attr.gpio_attr.reset_on, + reset_cfg->attr.gpio_attr.reset_off); + reset_cfg->attr.gpio_attr.gpio_init = 0; + } else if (reset_cfg->pca9641_reset_type == PCA9641_RESET_IO) { + + PCA_DEBUG("reset by io.\n"); + reset_cfg->attr.io_attr.io_addr = i2c_mux_pca9641_device->attr.io_attr.io_addr; + reset_cfg->attr.io_attr.mask = i2c_mux_pca9641_device->attr.io_attr.mask; + reset_cfg->attr.io_attr.reset_on = i2c_mux_pca9641_device->attr.io_attr.reset_on; + reset_cfg->attr.io_attr.reset_off = i2c_mux_pca9641_device->attr.io_attr.reset_off; + PCA_DEBUG("io_addr:0x%x, mask:0x%x, reset_on:0x%x, reset_off:0x%x.\n", + reset_cfg->attr.io_attr.io_addr, reset_cfg->attr.io_attr.mask, + reset_cfg->attr.io_attr.reset_on, reset_cfg->attr.io_attr.reset_off); + } else if (reset_cfg->pca9641_reset_type == PCA9641_RESET_FILE) { + + PCA_DEBUG("reset by file.\n"); + reset_cfg->attr.file_attr.dev_name = i2c_mux_pca9641_device->attr.file_attr.dev_name; + reset_cfg->attr.file_attr.offset = i2c_mux_pca9641_device->attr.file_attr.offset; + reset_cfg->attr.file_attr.mask = i2c_mux_pca9641_device->attr.file_attr.mask; + reset_cfg->attr.file_attr.reset_on = i2c_mux_pca9641_device->attr.file_attr.reset_on; + reset_cfg->attr.file_attr.reset_off = i2c_mux_pca9641_device->attr.file_attr.reset_off; + PCA_DEBUG("dev_name:%s, mask:0x%x, reset_on:0x%x, reset_off:0x%x.\n", + reset_cfg->attr.file_attr.dev_name, reset_cfg->attr.file_attr.mask, + reset_cfg->attr.file_attr.reset_on, reset_cfg->attr.file_attr.reset_off); + } else { + PCA_DEBUG_ERR("Unsupport reset type:%d.\n", reset_cfg->pca9641_reset_type); + return -EINVAL; + } + return 0; +} + +/* + * I2C init/probing/exit functions + */ +static int pca9541_probe(struct i2c_client *client, const struct i2c_device_id *id) +{ + struct i2c_adapter *adap = client->adapter; + struct i2c_mux_core *muxc; + struct pca9541 *data; + int force; + int ret = -ENODEV; + int detect_id; + i2c_mux_pca9641_device_t *i2c_mux_pca9641_device; + + if (!i2c_check_functionality(adap, I2C_FUNC_SMBUS_BYTE_DATA)) + return -ENODEV; + + detect_id = pca9641_detect_id(client); + + /* + * I2C accesses are unprotected here. + * We have to lock the adapter before releasing the bus. + */ + if (detect_id == 0) { + i2c_lock_bus(adap, I2C_LOCK_ROOT_ADAPTER); + pca9541_release_bus(client); + i2c_unlock_bus(adap, I2C_LOCK_ROOT_ADAPTER); + } else { + i2c_lock_bus(adap, I2C_LOCK_ROOT_ADAPTER); + pca9641_release_bus(client); + i2c_unlock_bus(adap, I2C_LOCK_ROOT_ADAPTER); + } + + if (detect_id == 0) { /* pca9541 */ + muxc = i2c_mux_alloc(adap, &client->dev, 1, sizeof(*data), + I2C_MUX_ARBITRATOR, + pca9541_select_chan, pca9541_release_chan); + if (!muxc) + return -ENOMEM; + + data = i2c_mux_priv(muxc); + data->client = client; + + i2c_set_clientdata(client, muxc); + /* Create mux adapter */ + if (of_property_read_u32(client->dev.of_node, "pca9641_nr", &data->pca9641_nr)) { + + force = 0; + PCA_DEBUG("pca9641_nr not found, use dynamic adap number.\n"); + } else { + force = data->pca9641_nr; + PCA_DEBUG("pca9641_nr: %d.\n", force); + } + + ret = i2c_mux_add_adapter(muxc, force, 0, 0); + if (ret) + return ret; + } else { + muxc = i2c_mux_alloc(adap, &client->dev, 1, sizeof(*data), I2C_MUX_ARBITRATOR, + pca9641_select_chan, pca9641_release_chan); + if (!muxc) { + dev_err(&client->dev, "i2c_mux_alloc failed, out of memory.\n"); + return -ENOMEM; + } + + data = i2c_mux_priv(muxc); + data->client = client; + + i2c_set_clientdata(client, muxc); + + if (client->dev.of_node) { + ret= of_pca9641_reset_data_init(data); + } else { + ret= pca9641_reset_data_init(data); + } + if (ret < 0) { + dev_err(&client->dev, "pca9641 reset config err, ret:%d.\n", ret); + return ret; + } + + if (client->dev.of_node == NULL) { + if (client->dev.platform_data == NULL) { + force = 0; + PCA_DEBUG("platform data is NULL, use dynamic adap number.\n"); + } else { + i2c_mux_pca9641_device = client->dev.platform_data; + data->pca9641_nr = i2c_mux_pca9641_device->pca9641_nr; + if (data->pca9641_nr == 0) { + force = 0; + PCA_DEBUG("pca9641_nr = 0, use dynamic adap number.\n"); + } else { + force = data->pca9641_nr; + PCA_DEBUG("pca9641_nr: %d.\n", force); + } + } + } else { + /* Create mux adapter */ + if (of_property_read_u32(client->dev.of_node, "pca9641_nr", &data->pca9641_nr)) { + + force = 0; + PCA_DEBUG("pca9641_nr not found, use dynamic adap number.\n"); + } else { + force = data->pca9641_nr; + PCA_DEBUG("pca9641_nr: %d.\n", force); + } + } + + ret = i2c_mux_add_adapter(muxc, force, 0, 0); + if (ret) { + dev_err(&client->dev, "Failed to register master selector.\n"); + return ret; + } + } + pca9641_recordflag(muxc->adapter[0]); + + dev_info(&client->dev, "registered master selector for I2C %s\n", client->name); + + return 0; +} + +static int pca9541_remove(struct i2c_client *client) +{ + struct i2c_mux_core *muxc = i2c_get_clientdata(client); + + i2c_mux_del_adapters(muxc); + return 0; +} + +static struct i2c_driver pca9641_driver = { + .driver = { + .name = "wb_pca9641", + .of_match_table = of_match_ptr(pca9541_of_match), + }, + .probe = pca9541_probe, + .remove = pca9541_remove, + .id_table = pca9541_id, +}; + +module_i2c_driver(pca9641_driver); +MODULE_AUTHOR("support"); +MODULE_DESCRIPTION("PCA9541 I2C master selector driver"); +MODULE_LICENSE("GPL v2"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_i2c_mux_pca9641.h b/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_i2c_mux_pca9641.h new file mode 100644 index 000000000000..b87f7585567b --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_i2c_mux_pca9641.h @@ -0,0 +1,64 @@ +#ifndef __WB_I2C_MUX_PCA9641_H__ +#define __WB_I2C_MUX_PCA9641_H__ + +#include + +#define mem_clear(data, size) memset((data), 0, (size)) + +typedef enum pca9641_reset_type_s { + PCA9641_RESET_NONE = 0, + PCA9641_RESET_I2C = 1, + PCA9641_RESET_GPIO = 2, + PCA9641_RESET_IO = 3, + PCA9641_RESET_FILE = 4, +} pca9641_reset_type_t; + +typedef struct i2c_attr_s { + uint32_t i2c_bus; + uint32_t i2c_addr; + uint32_t reg_offset; + uint32_t mask; + uint32_t reset_on; + uint32_t reset_off; +} i2c_attr_t; + +typedef struct io_attr_s { + uint32_t io_addr; + uint32_t mask; + uint32_t reset_on; + uint32_t reset_off; +} io_attr_t; + +typedef struct file_attr_s { + const char *dev_name; + uint32_t offset; + uint32_t mask; + uint32_t reset_on; + uint32_t reset_off; +} file_attr_t; + +typedef struct gpio_attr_s { + int gpio_init; + uint32_t gpio; + uint32_t reset_on; + uint32_t reset_off; +} gpio_attr_t; + +typedef struct i2c_mux_pca9641_device_s { + struct i2c_client *client; + uint32_t i2c_bus; + uint32_t i2c_addr; + uint32_t pca9641_nr; + uint32_t pca9641_reset_type; + uint32_t rst_delay_b; /* delay time before reset(us) */ + uint32_t rst_delay; /* reset time(us) */ + uint32_t rst_delay_a; /* delay time after reset(us) */ + union { + i2c_attr_t i2c_attr; + gpio_attr_t gpio_attr; + io_attr_t io_attr; + file_attr_t file_attr; + } attr; +} i2c_mux_pca9641_device_t; + +#endif diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_ina3221.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_ina3221.c new file mode 100644 index 000000000000..fba2c4e3a68e --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_ina3221.c @@ -0,0 +1,1031 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * INA3221 Triple Current/Voltage Monitor + * + * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/ + * Andrew F. Davis + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define INA3221_DRIVER_NAME "wb_ina3221" + +#define INA3221_CONFIG 0x00 +#define INA3221_SHUNT1 0x01 +#define INA3221_BUS1 0x02 +#define INA3221_SHUNT2 0x03 +#define INA3221_BUS2 0x04 +#define INA3221_SHUNT3 0x05 +#define INA3221_BUS3 0x06 +#define INA3221_CRIT1 0x07 +#define INA3221_WARN1 0x08 +#define INA3221_CRIT2 0x09 +#define INA3221_WARN2 0x0a +#define INA3221_CRIT3 0x0b +#define INA3221_WARN3 0x0c +#define INA3221_SHUNT_SUM 0x0d +#define INA3221_CRIT_SUM 0x0e +#define INA3221_MASK_ENABLE 0x0f + +#define INA3221_CONFIG_MODE_MASK GENMASK(2, 0) +#define INA3221_CONFIG_MODE_POWERDOWN 0 +#define INA3221_CONFIG_MODE_SHUNT BIT(0) +#define INA3221_CONFIG_MODE_BUS BIT(1) +#define INA3221_CONFIG_MODE_CONTINUOUS BIT(2) +#define INA3221_CONFIG_VSH_CT_SHIFT 3 +#define INA3221_CONFIG_VSH_CT_MASK GENMASK(5, 3) +#define INA3221_CONFIG_VSH_CT(x) (((x) & GENMASK(5, 3)) >> 3) +#define INA3221_CONFIG_VBUS_CT_SHIFT 6 +#define INA3221_CONFIG_VBUS_CT_MASK GENMASK(8, 6) +#define INA3221_CONFIG_VBUS_CT(x) (((x) & GENMASK(8, 6)) >> 6) +#define INA3221_CONFIG_AVG_SHIFT 9 +#define INA3221_CONFIG_AVG_MASK GENMASK(11, 9) +#define INA3221_CONFIG_AVG(x) (((x) & GENMASK(11, 9)) >> 9) +#define INA3221_CONFIG_CHs_EN_MASK GENMASK(14, 12) +#define INA3221_CONFIG_CHx_EN(x) BIT(14 - (x)) + +#define INA3221_MASK_ENABLE_SCC_MASK GENMASK(14, 12) + +#define INA3221_CONFIG_DEFAULT 0x7127 +#define INA3221_RSHUNT_DEFAULT 10000 + +enum ina3221_fields { + /* Configuration */ + F_RST, + + /* Status Flags */ + F_CVRF, + + /* Warning Flags */ + F_WF3, F_WF2, F_WF1, + + /* Alert Flags: SF is the summation-alert flag */ + F_SF, F_CF3, F_CF2, F_CF1, + + /* sentinel */ + F_MAX_FIELDS +}; + +static const struct reg_field ina3221_reg_fields[] = { + [F_RST] = REG_FIELD(INA3221_CONFIG, 15, 15), + + [F_CVRF] = REG_FIELD(INA3221_MASK_ENABLE, 0, 0), + [F_WF3] = REG_FIELD(INA3221_MASK_ENABLE, 3, 3), + [F_WF2] = REG_FIELD(INA3221_MASK_ENABLE, 4, 4), + [F_WF1] = REG_FIELD(INA3221_MASK_ENABLE, 5, 5), + [F_SF] = REG_FIELD(INA3221_MASK_ENABLE, 6, 6), + [F_CF3] = REG_FIELD(INA3221_MASK_ENABLE, 7, 7), + [F_CF2] = REG_FIELD(INA3221_MASK_ENABLE, 8, 8), + [F_CF1] = REG_FIELD(INA3221_MASK_ENABLE, 9, 9), +}; + +enum ina3221_channels { + INA3221_CHANNEL1, + INA3221_CHANNEL2, + INA3221_CHANNEL3, + INA3221_NUM_CHANNELS +}; + +/** + * struct ina3221_input - channel input source specific information + * @label: label of channel input source + * @shunt_resistor: shunt resistor value of channel input source + * @disconnected: connection status of channel input source + */ +struct ina3221_input { + const char *label; + int shunt_resistor; + bool disconnected; +}; + +/** + * struct ina3221_data - device specific information + * @pm_dev: Device pointer for pm runtime + * @regmap: Register map of the device + * @fields: Register fields of the device + * @inputs: Array of channel input source specific structures + * @lock: mutex lock to serialize sysfs attribute accesses + * @reg_config: Register value of INA3221_CONFIG + * @summation_shunt_resistor: equivalent shunt resistor value for summation + * @single_shot: running in single-shot operating mode + */ +struct ina3221_data { + struct device *pm_dev; + struct regmap *regmap; + struct regmap_field *fields[F_MAX_FIELDS]; + struct ina3221_input inputs[INA3221_NUM_CHANNELS]; + struct mutex lock; + u32 reg_config; + int summation_shunt_resistor; + + bool single_shot; +}; + +static inline bool ina3221_is_enabled(struct ina3221_data *ina, int channel) +{ + /* Summation channel checks shunt resistor values */ + if (channel > INA3221_CHANNEL3) + return ina->summation_shunt_resistor != 0; + + return pm_runtime_active(ina->pm_dev) && + (ina->reg_config & INA3221_CONFIG_CHx_EN(channel)); +} + +/** + * Helper function to return the resistor value for current summation. + * + * There is a condition to calculate current summation -- all the shunt + * resistor values should be the same, so as to simply fit the formula: + * current summation = shunt voltage summation / shunt resistor + * + * Returns the equivalent shunt resistor value on success or 0 on failure + */ +static inline int ina3221_summation_shunt_resistor(struct ina3221_data *ina) +{ + struct ina3221_input *input = ina->inputs; + int i, shunt_resistor = 0; + + for (i = 0; i < INA3221_NUM_CHANNELS; i++) { + if (input[i].disconnected || !input[i].shunt_resistor) + continue; + if (!shunt_resistor) { + /* Found the reference shunt resistor value */ + shunt_resistor = input[i].shunt_resistor; + } else { + /* No summation if resistor values are different */ + if (shunt_resistor != input[i].shunt_resistor) + return 0; + } + } + + return shunt_resistor; +} + +/* Lookup table for Bus and Shunt conversion times in usec */ +static const u16 ina3221_conv_time[] = { + 140, 204, 332, 588, 1100, 2116, 4156, 8244, +}; + +/* Lookup table for number of samples using in averaging mode */ +static const int ina3221_avg_samples[] = { + 1, 4, 16, 64, 128, 256, 512, 1024, +}; + +/* Converting update_interval in msec to conversion time in usec */ +static inline u32 ina3221_interval_ms_to_conv_time(u16 config, int interval) +{ + u32 channels = hweight16(config & INA3221_CONFIG_CHs_EN_MASK); + u32 samples_idx = INA3221_CONFIG_AVG(config); + u32 samples = ina3221_avg_samples[samples_idx]; + + /* Bisect the result to Bus and Shunt conversion times */ + return DIV_ROUND_CLOSEST(interval * 1000 / 2, channels * samples); +} + +/* Converting CONFIG register value to update_interval in usec */ +static inline u32 ina3221_reg_to_interval_us(u16 config) +{ + u32 channels = hweight16(config & INA3221_CONFIG_CHs_EN_MASK); + u32 vbus_ct_idx = INA3221_CONFIG_VBUS_CT(config); + u32 vsh_ct_idx = INA3221_CONFIG_VSH_CT(config); + u32 samples_idx = INA3221_CONFIG_AVG(config); + u32 samples = ina3221_avg_samples[samples_idx]; + u32 vbus_ct = ina3221_conv_time[vbus_ct_idx]; + u32 vsh_ct = ina3221_conv_time[vsh_ct_idx]; + + /* Calculate total conversion time */ + return channels * (vbus_ct + vsh_ct) * samples; +} + +static inline int ina3221_wait_for_data(struct ina3221_data *ina) +{ + u32 wait, cvrf; + + wait = ina3221_reg_to_interval_us(ina->reg_config); + + /* Polling the CVRF bit to make sure read data is ready */ + return regmap_field_read_poll_timeout(ina->fields[F_CVRF], + cvrf, cvrf, wait, wait * 2); +} + +static int ina3221_read_value(struct ina3221_data *ina, unsigned int reg, + int *val) +{ + unsigned int regval; + int ret; + + ret = regmap_read(ina->regmap, reg, ®val); + if (ret) + return ret; + + /* + * Shunt Voltage Sum register has 14-bit value with 1-bit shift + * Other Shunt Voltage registers have 12 bits with 3-bit shift + */ + if (reg == INA3221_SHUNT_SUM) + *val = sign_extend32(regval >> 1, 14); + else + *val = sign_extend32(regval >> 3, 12); + + return 0; +} + +static const u8 ina3221_in_reg[] = { + INA3221_BUS1, + INA3221_BUS2, + INA3221_BUS3, + INA3221_SHUNT1, + INA3221_SHUNT2, + INA3221_SHUNT3, + INA3221_SHUNT_SUM, +}; + +static int ina3221_read_chip(struct device *dev, u32 attr, long *val) +{ + struct ina3221_data *ina = dev_get_drvdata(dev); + int regval; + + switch (attr) { + case hwmon_chip_samples: + regval = INA3221_CONFIG_AVG(ina->reg_config); + *val = ina3221_avg_samples[regval]; + return 0; + case hwmon_chip_update_interval: + /* Return in msec */ + *val = ina3221_reg_to_interval_us(ina->reg_config); + *val = DIV_ROUND_CLOSEST(*val, 1000); + return 0; + default: + return -EOPNOTSUPP; + } +} + +static int ina3221_read_in(struct device *dev, u32 attr, int channel, long *val) +{ + const bool is_shunt = channel > INA3221_CHANNEL3; + struct ina3221_data *ina = dev_get_drvdata(dev); + u8 reg = ina3221_in_reg[channel]; + int regval, ret; + + /* + * Translate shunt channel index to sensor channel index except + * the 7th channel (6 since being 0-aligned) is for summation. + */ + if (channel != 6) + channel %= INA3221_NUM_CHANNELS; + + switch (attr) { + case hwmon_in_input: + if (!ina3221_is_enabled(ina, channel)) + return -ENODATA; + + /* Write CONFIG register to trigger a single-shot measurement */ + if (ina->single_shot) + regmap_write(ina->regmap, INA3221_CONFIG, + ina->reg_config); + + ret = ina3221_wait_for_data(ina); + if (ret) + return ret; + + ret = ina3221_read_value(ina, reg, ®val); + if (ret) + return ret; + + /* + * Scale of shunt voltage (uV): LSB is 40uV + * Scale of bus voltage (mV): LSB is 8mV + */ + *val = regval * (is_shunt ? 40 : 8); + return 0; + case hwmon_in_enable: + *val = ina3221_is_enabled(ina, channel); + return 0; + default: + return -EOPNOTSUPP; + } +} + +static const u8 ina3221_curr_reg[][INA3221_NUM_CHANNELS + 1] = { + [hwmon_curr_input] = { INA3221_SHUNT1, INA3221_SHUNT2, + INA3221_SHUNT3, INA3221_SHUNT_SUM }, + [hwmon_curr_max] = { INA3221_WARN1, INA3221_WARN2, INA3221_WARN3, 0 }, + [hwmon_curr_crit] = { INA3221_CRIT1, INA3221_CRIT2, + INA3221_CRIT3, INA3221_CRIT_SUM }, + [hwmon_curr_max_alarm] = { F_WF1, F_WF2, F_WF3, 0 }, + [hwmon_curr_crit_alarm] = { F_CF1, F_CF2, F_CF3, F_SF }, +}; + +static int ina3221_read_curr(struct device *dev, u32 attr, + int channel, long *val) +{ + struct ina3221_data *ina = dev_get_drvdata(dev); + struct ina3221_input *input = ina->inputs; + u8 reg = ina3221_curr_reg[attr][channel]; + int resistance_uo, voltage_nv; + int regval, ret; + + if (channel > INA3221_CHANNEL3) + resistance_uo = ina->summation_shunt_resistor; + else + resistance_uo = input[channel].shunt_resistor; + + switch (attr) { + case hwmon_curr_input: + if (!ina3221_is_enabled(ina, channel)) + return -ENODATA; + + /* Write CONFIG register to trigger a single-shot measurement */ + if (ina->single_shot) + regmap_write(ina->regmap, INA3221_CONFIG, + ina->reg_config); + + ret = ina3221_wait_for_data(ina); + if (ret) + return ret; + + fallthrough; + case hwmon_curr_crit: + case hwmon_curr_max: + if (!resistance_uo) + return -ENODATA; + + ret = ina3221_read_value(ina, reg, ®val); + if (ret) + return ret; + + /* Scale of shunt voltage: LSB is 40uV (40000nV) */ + voltage_nv = regval * 40000; + /* Return current in mA */ + *val = DIV_ROUND_CLOSEST(voltage_nv, resistance_uo); + return 0; + case hwmon_curr_crit_alarm: + case hwmon_curr_max_alarm: + /* No actual register read if channel is disabled */ + if (!ina3221_is_enabled(ina, channel)) { + /* Return 0 for alert flags */ + *val = 0; + return 0; + } + ret = regmap_field_read(ina->fields[reg], ®val); + if (ret) + return ret; + *val = regval; + return 0; + default: + return -EOPNOTSUPP; + } +} + +static int ina3221_write_chip(struct device *dev, u32 attr, long val) +{ + struct ina3221_data *ina = dev_get_drvdata(dev); + int ret, idx; + u32 tmp; + + switch (attr) { + case hwmon_chip_samples: + idx = find_closest(val, ina3221_avg_samples, + ARRAY_SIZE(ina3221_avg_samples)); + + tmp = (ina->reg_config & ~INA3221_CONFIG_AVG_MASK) | + (idx << INA3221_CONFIG_AVG_SHIFT); + ret = regmap_write(ina->regmap, INA3221_CONFIG, tmp); + if (ret) + return ret; + + /* Update reg_config accordingly */ + ina->reg_config = tmp; + return 0; + case hwmon_chip_update_interval: + tmp = ina3221_interval_ms_to_conv_time(ina->reg_config, val); + idx = find_closest(tmp, ina3221_conv_time, + ARRAY_SIZE(ina3221_conv_time)); + + /* Update Bus and Shunt voltage conversion times */ + tmp = INA3221_CONFIG_VBUS_CT_MASK | INA3221_CONFIG_VSH_CT_MASK; + tmp = (ina->reg_config & ~tmp) | + (idx << INA3221_CONFIG_VBUS_CT_SHIFT) | + (idx << INA3221_CONFIG_VSH_CT_SHIFT); + ret = regmap_write(ina->regmap, INA3221_CONFIG, tmp); + if (ret) + return ret; + + /* Update reg_config accordingly */ + ina->reg_config = tmp; + return 0; + default: + return -EOPNOTSUPP; + } +} + +static int ina3221_write_curr(struct device *dev, u32 attr, + int channel, long val) +{ + struct ina3221_data *ina = dev_get_drvdata(dev); + struct ina3221_input *input = ina->inputs; + u8 reg = ina3221_curr_reg[attr][channel]; + int resistance_uo, current_ma, voltage_uv; + int regval; + + if (channel > INA3221_CHANNEL3) + resistance_uo = ina->summation_shunt_resistor; + else + resistance_uo = input[channel].shunt_resistor; + + if (!resistance_uo) + return -EOPNOTSUPP; + + /* clamp current */ + current_ma = clamp_val(val, + INT_MIN / resistance_uo, + INT_MAX / resistance_uo); + + voltage_uv = DIV_ROUND_CLOSEST(current_ma * resistance_uo, 1000); + + /* clamp voltage */ + voltage_uv = clamp_val(voltage_uv, -163800, 163800); + + /* + * Formula to convert voltage_uv to register value: + * regval = (voltage_uv / scale) << shift + * Note: + * The scale is 40uV for all shunt voltage registers + * Shunt Voltage Sum register left-shifts 1 bit + * All other Shunt Voltage registers shift 3 bits + * Results: + * SHUNT_SUM: (1 / 40uV) << 1 = 1 / 20uV + * SHUNT[1-3]: (1 / 40uV) << 3 = 1 / 5uV + */ + if (reg == INA3221_SHUNT_SUM) + regval = DIV_ROUND_CLOSEST(voltage_uv, 20) & 0xfffe; + else + regval = DIV_ROUND_CLOSEST(voltage_uv, 5) & 0xfff8; + + return regmap_write(ina->regmap, reg, regval); +} + +static int ina3221_write_enable(struct device *dev, int channel, bool enable) +{ + struct ina3221_data *ina = dev_get_drvdata(dev); + u16 config, mask = INA3221_CONFIG_CHx_EN(channel); + u16 config_old = ina->reg_config & mask; + u32 tmp; + int ret; + + config = enable ? mask : 0; + + /* Bypass if enable status is not being changed */ + if (config_old == config) + return 0; + + /* For enabling routine, increase refcount and resume() at first */ + if (enable) { + ret = pm_runtime_resume_and_get(ina->pm_dev); + if (ret < 0) { + dev_err(dev, "Failed to get PM runtime\n"); + return ret; + } + } + + /* Enable or disable the channel */ + tmp = (ina->reg_config & ~mask) | (config & mask); + ret = regmap_write(ina->regmap, INA3221_CONFIG, tmp); + if (ret) + goto fail; + + /* Cache the latest config register value */ + ina->reg_config = tmp; + + /* For disabling routine, decrease refcount or suspend() at last */ + if (!enable) + pm_runtime_put_sync(ina->pm_dev); + + return 0; + +fail: + if (enable) { + dev_err(dev, "Failed to enable channel %d: error %d\n", + channel, ret); + pm_runtime_put_sync(ina->pm_dev); + } + + return ret; +} + +static int ina3221_read(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long *val) +{ + struct ina3221_data *ina = dev_get_drvdata(dev); + int ret; + + mutex_lock(&ina->lock); + + switch (type) { + case hwmon_chip: + ret = ina3221_read_chip(dev, attr, val); + break; + case hwmon_in: + /* 0-align channel ID */ + ret = ina3221_read_in(dev, attr, channel - 1, val); + break; + case hwmon_curr: + ret = ina3221_read_curr(dev, attr, channel, val); + break; + default: + ret = -EOPNOTSUPP; + break; + } + + mutex_unlock(&ina->lock); + + return ret; +} + +static int ina3221_write(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long val) +{ + struct ina3221_data *ina = dev_get_drvdata(dev); + int ret; + + mutex_lock(&ina->lock); + + switch (type) { + case hwmon_chip: + ret = ina3221_write_chip(dev, attr, val); + break; + case hwmon_in: + /* 0-align channel ID */ + ret = ina3221_write_enable(dev, channel - 1, val); + break; + case hwmon_curr: + ret = ina3221_write_curr(dev, attr, channel, val); + break; + default: + ret = -EOPNOTSUPP; + break; + } + + mutex_unlock(&ina->lock); + + return ret; +} + +static int ina3221_read_string(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, const char **str) +{ + struct ina3221_data *ina = dev_get_drvdata(dev); + int index = channel - 1; + + if (channel == 7) + *str = "sum of shunt voltages"; + else + *str = ina->inputs[index].label; + + return 0; +} + +static umode_t ina3221_is_visible(const void *drvdata, + enum hwmon_sensor_types type, + u32 attr, int channel) +{ + const struct ina3221_data *ina = drvdata; + const struct ina3221_input *input = NULL; + + switch (type) { + case hwmon_chip: + switch (attr) { + case hwmon_chip_samples: + case hwmon_chip_update_interval: + return 0644; + default: + return 0; + } + case hwmon_in: + /* Ignore in0_ */ + if (channel == 0) + return 0; + + switch (attr) { + case hwmon_in_label: + if (channel - 1 <= INA3221_CHANNEL3) + input = &ina->inputs[channel - 1]; + else if (channel == 7) + return 0444; + /* Hide label node if label is not provided */ + return (input && input->label) ? 0444 : 0; + case hwmon_in_input: + return 0444; + case hwmon_in_enable: + return 0644; + default: + return 0; + } + case hwmon_curr: + switch (attr) { + case hwmon_curr_input: + case hwmon_curr_crit_alarm: + case hwmon_curr_max_alarm: + return 0444; + case hwmon_curr_crit: + case hwmon_curr_max: + return 0644; + default: + return 0; + } + default: + return 0; + } +} + +#define INA3221_HWMON_CURR_CONFIG (HWMON_C_INPUT | \ + HWMON_C_CRIT | HWMON_C_CRIT_ALARM | \ + HWMON_C_MAX | HWMON_C_MAX_ALARM) + +static const struct hwmon_channel_info *ina3221_info[] = { + HWMON_CHANNEL_INFO(chip, + HWMON_C_SAMPLES, + HWMON_C_UPDATE_INTERVAL), + HWMON_CHANNEL_INFO(in, + /* 0: dummy, skipped in is_visible */ + HWMON_I_INPUT, + /* 1-3: input voltage Channels */ + HWMON_I_INPUT | HWMON_I_ENABLE | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_ENABLE | HWMON_I_LABEL, + HWMON_I_INPUT | HWMON_I_ENABLE | HWMON_I_LABEL, + /* 4-6: shunt voltage Channels */ + HWMON_I_INPUT, + HWMON_I_INPUT, + HWMON_I_INPUT, + /* 7: summation of shunt voltage channels */ + HWMON_I_INPUT | HWMON_I_LABEL), + HWMON_CHANNEL_INFO(curr, + /* 1-3: current channels*/ + INA3221_HWMON_CURR_CONFIG, + INA3221_HWMON_CURR_CONFIG, + INA3221_HWMON_CURR_CONFIG, + /* 4: summation of current channels */ + HWMON_C_INPUT | HWMON_C_CRIT | HWMON_C_CRIT_ALARM), + NULL +}; + +static const struct hwmon_ops ina3221_hwmon_ops = { + .is_visible = ina3221_is_visible, + .read_string = ina3221_read_string, + .read = ina3221_read, + .write = ina3221_write, +}; + +static const struct hwmon_chip_info ina3221_chip_info = { + .ops = &ina3221_hwmon_ops, + .info = ina3221_info, +}; + +/* Extra attribute groups */ +static ssize_t ina3221_shunt_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct sensor_device_attribute *sd_attr = to_sensor_dev_attr(attr); + struct ina3221_data *ina = dev_get_drvdata(dev); + unsigned int channel = sd_attr->index; + struct ina3221_input *input = &ina->inputs[channel]; + + return snprintf(buf, PAGE_SIZE, "%d\n", input->shunt_resistor); +} + +static ssize_t ina3221_shunt_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct sensor_device_attribute *sd_attr = to_sensor_dev_attr(attr); + struct ina3221_data *ina = dev_get_drvdata(dev); + unsigned int channel = sd_attr->index; + struct ina3221_input *input = &ina->inputs[channel]; + int val; + int ret; + + ret = kstrtoint(buf, 0, &val); + if (ret) + return ret; + + val = clamp_val(val, 1, INT_MAX); + + input->shunt_resistor = val; + + /* Update summation_shunt_resistor for summation channel */ + ina->summation_shunt_resistor = ina3221_summation_shunt_resistor(ina); + + return count; +} + +/* shunt resistance */ +static SENSOR_DEVICE_ATTR_RW(shunt1_resistor, ina3221_shunt, INA3221_CHANNEL1); +static SENSOR_DEVICE_ATTR_RW(shunt2_resistor, ina3221_shunt, INA3221_CHANNEL2); +static SENSOR_DEVICE_ATTR_RW(shunt3_resistor, ina3221_shunt, INA3221_CHANNEL3); + +static struct attribute *ina3221_attrs[] = { + &sensor_dev_attr_shunt1_resistor.dev_attr.attr, + &sensor_dev_attr_shunt2_resistor.dev_attr.attr, + &sensor_dev_attr_shunt3_resistor.dev_attr.attr, + NULL, +}; +ATTRIBUTE_GROUPS(ina3221); + +static const struct regmap_range ina3221_yes_ranges[] = { + regmap_reg_range(INA3221_CONFIG, INA3221_BUS3), + regmap_reg_range(INA3221_SHUNT_SUM, INA3221_SHUNT_SUM), + regmap_reg_range(INA3221_MASK_ENABLE, INA3221_MASK_ENABLE), +}; + +static const struct regmap_access_table ina3221_volatile_table = { + .yes_ranges = ina3221_yes_ranges, + .n_yes_ranges = ARRAY_SIZE(ina3221_yes_ranges), +}; + +static const struct regmap_config ina3221_regmap_config = { + .reg_bits = 8, + .val_bits = 16, + + .cache_type = REGCACHE_RBTREE, + .volatile_table = &ina3221_volatile_table, +}; + +static int ina3221_probe_child_from_dt(struct device *dev, + struct device_node *child, + struct ina3221_data *ina) +{ + struct ina3221_input *input; + u32 val; + int ret; + + ret = of_property_read_u32(child, "reg", &val); + if (ret) { + dev_err(dev, "missing reg property of %pOFn\n", child); + return ret; + } else if (val > INA3221_CHANNEL3) { + dev_err(dev, "invalid reg %d of %pOFn\n", val, child); + return ret; + } + + input = &ina->inputs[val]; + + /* Log the disconnected channel input */ + if (!of_device_is_available(child)) { + input->disconnected = true; + return 0; + } + + /* Save the connected input label if available */ + of_property_read_string(child, "label", &input->label); + + /* Overwrite default shunt resistor value optionally */ + if (!of_property_read_u32(child, "shunt-resistor-micro-ohms", &val)) { + if (val < 1 || val > INT_MAX) { + dev_err(dev, "invalid shunt resistor value %u of %pOFn\n", + val, child); + return -EINVAL; + } + input->shunt_resistor = val; + } + + return 0; +} + +static int ina3221_probe_from_dt(struct device *dev, struct ina3221_data *ina) +{ + const struct device_node *np = dev->of_node; + struct device_node *child; + int ret; + + /* Compatible with non-DT platforms */ + if (!np) + return 0; + + ina->single_shot = of_property_read_bool(np, "ti,single-shot"); + + for_each_child_of_node(np, child) { + ret = ina3221_probe_child_from_dt(dev, child, ina); + if (ret) { + of_node_put(child); + return ret; + } + } + + return 0; +} + +static int ina3221_probe(struct i2c_client *client) +{ + struct device *dev = &client->dev; + struct ina3221_data *ina; + struct device *hwmon_dev; + int i, ret; + + ina = devm_kzalloc(dev, sizeof(*ina), GFP_KERNEL); + if (!ina) + return -ENOMEM; + + ina->regmap = devm_regmap_init_i2c(client, &ina3221_regmap_config); + if (IS_ERR(ina->regmap)) { + dev_err(dev, "Unable to allocate register map\n"); + return PTR_ERR(ina->regmap); + } + + for (i = 0; i < F_MAX_FIELDS; i++) { + ina->fields[i] = devm_regmap_field_alloc(dev, + ina->regmap, + ina3221_reg_fields[i]); + if (IS_ERR(ina->fields[i])) { + dev_err(dev, "Unable to allocate regmap fields\n"); + return PTR_ERR(ina->fields[i]); + } + } + + for (i = 0; i < INA3221_NUM_CHANNELS; i++) + ina->inputs[i].shunt_resistor = INA3221_RSHUNT_DEFAULT; + + ret = ina3221_probe_from_dt(dev, ina); + if (ret) { + dev_err(dev, "Unable to probe from device tree\n"); + return ret; + } + + /* The driver will be reset, so use reset value */ + ina->reg_config = INA3221_CONFIG_DEFAULT; + + /* Clear continuous bit to use single-shot mode */ + if (ina->single_shot) + ina->reg_config &= ~INA3221_CONFIG_MODE_CONTINUOUS; + + /* Disable channels if their inputs are disconnected */ + for (i = 0; i < INA3221_NUM_CHANNELS; i++) { + if (ina->inputs[i].disconnected) + ina->reg_config &= ~INA3221_CONFIG_CHx_EN(i); + } + + /* Initialize summation_shunt_resistor for summation channel control */ + ina->summation_shunt_resistor = ina3221_summation_shunt_resistor(ina); + + ina->pm_dev = dev; + mutex_init(&ina->lock); + dev_set_drvdata(dev, ina); + + /* Enable PM runtime -- status is suspended by default */ + pm_runtime_enable(ina->pm_dev); + + /* Initialize (resume) the device */ + for (i = 0; i < INA3221_NUM_CHANNELS; i++) { + if (ina->inputs[i].disconnected) + continue; + /* Match the refcount with number of enabled channels */ + ret = pm_runtime_get_sync(ina->pm_dev); + if (ret < 0) + goto fail; + } + + hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name, ina, + &ina3221_chip_info, + ina3221_groups); + if (IS_ERR(hwmon_dev)) { + dev_err(dev, "Unable to register hwmon device\n"); + ret = PTR_ERR(hwmon_dev); + goto fail; + } + + return 0; + +fail: + pm_runtime_disable(ina->pm_dev); + pm_runtime_set_suspended(ina->pm_dev); + /* pm_runtime_put_noidle() will decrease the PM refcount until 0 */ + for (i = 0; i < INA3221_NUM_CHANNELS; i++) + pm_runtime_put_noidle(ina->pm_dev); + mutex_destroy(&ina->lock); + + return ret; +} + +static int ina3221_remove(struct i2c_client *client) +{ + struct ina3221_data *ina = dev_get_drvdata(&client->dev); + int i; + + pm_runtime_disable(ina->pm_dev); + pm_runtime_set_suspended(ina->pm_dev); + + /* pm_runtime_put_noidle() will decrease the PM refcount until 0 */ + for (i = 0; i < INA3221_NUM_CHANNELS; i++) + pm_runtime_put_noidle(ina->pm_dev); + + mutex_destroy(&ina->lock); + + return 0; +} + +static int __maybe_unused ina3221_suspend(struct device *dev) +{ + struct ina3221_data *ina = dev_get_drvdata(dev); + int ret; + + /* Save config register value and enable cache-only */ + ret = regmap_read(ina->regmap, INA3221_CONFIG, &ina->reg_config); + if (ret) + return ret; + + /* Set to power-down mode for power saving */ + ret = regmap_update_bits(ina->regmap, INA3221_CONFIG, + INA3221_CONFIG_MODE_MASK, + INA3221_CONFIG_MODE_POWERDOWN); + if (ret) + return ret; + + regcache_cache_only(ina->regmap, true); + regcache_mark_dirty(ina->regmap); + + return 0; +} + +static int __maybe_unused ina3221_resume(struct device *dev) +{ + struct ina3221_data *ina = dev_get_drvdata(dev); + int ret; + + regcache_cache_only(ina->regmap, false); + + /* Software reset the chip */ + ret = regmap_field_write(ina->fields[F_RST], true); + if (ret) { + dev_err(dev, "Unable to reset device\n"); + return ret; + } + + /* Restore cached register values to hardware */ + ret = regcache_sync(ina->regmap); + if (ret) + return ret; + + /* Restore config register value to hardware */ + ret = regmap_write(ina->regmap, INA3221_CONFIG, ina->reg_config); + if (ret) + return ret; + + /* Initialize summation channel control */ + if (ina->summation_shunt_resistor) { + /* + * Take all three channels into summation by default + * Shunt measurements of disconnected channels should + * be 0, so it does not matter for summation. + */ + ret = regmap_update_bits(ina->regmap, INA3221_MASK_ENABLE, + INA3221_MASK_ENABLE_SCC_MASK, + INA3221_MASK_ENABLE_SCC_MASK); + if (ret) { + dev_err(dev, "Unable to control summation channel\n"); + return ret; + } + } + + return 0; +} + +static const struct dev_pm_ops ina3221_pm = { + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) + SET_RUNTIME_PM_OPS(ina3221_suspend, ina3221_resume, NULL) +}; + +static const struct of_device_id ina3221_of_match_table[] = { + { .compatible = "ti,wb_ina3221", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, ina3221_of_match_table); + +static const struct i2c_device_id ina3221_ids[] = { + { "wb_ina3221", 0 }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(i2c, ina3221_ids); + +static struct i2c_driver ina3221_i2c_driver = { + .probe_new = ina3221_probe, + .remove = ina3221_remove, + .driver = { + .name = INA3221_DRIVER_NAME, + .of_match_table = ina3221_of_match_table, + .pm = &ina3221_pm, + }, + .id_table = ina3221_ids, +}; +module_i2c_driver(ina3221_i2c_driver); + +MODULE_AUTHOR("support"); +MODULE_DESCRIPTION("Texas Instruments INA3221 HWMon Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_isl68137.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_isl68137.c new file mode 100644 index 000000000000..2797a831bd66 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_isl68137.c @@ -0,0 +1,572 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Hardware monitoring driver for Renesas Digital Multiphase Voltage Regulators + * + * Copyright (c) 2017 Google Inc + * Copyright (c) 2020 Renesas Electronics America + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "wb_pmbus.h" + +#define ISL68137_VOUT_AVS (0x30) +#define RAA_DMPVR2_READ_VMON (0xc8) +#define WRITE_PROTECT_CLOSE (0x00) +#define WRITE_PROTECT_OPEN (0x40) + +static int g_wb_isl68137_debug = 0; +static int g_wb_isl68137_error = 0; + +module_param(g_wb_isl68137_debug, int, S_IRUGO | S_IWUSR); +module_param(g_wb_isl68137_error, int, S_IRUGO | S_IWUSR); + +#define WB_ISL68137_VERBOSE(fmt, args...) do { \ + if (g_wb_isl68137_debug) { \ + printk(KERN_INFO "[WB_ISL68137][VER][func:%s line:%d]\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +#define WB_ISL68137_ERROR(fmt, args...) do { \ + if (g_wb_isl68137_error) { \ + printk(KERN_ERR "[WB_ISL68137][ERR][func:%s line:%d]\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +enum chips { + isl68137, + isl68220, + isl68221, + isl68222, + isl68223, + isl68224, + isl68225, + isl68226, + isl68227, + isl68229, + isl68233, + isl68239, + isl69222, + isl69223, + isl69224, + isl69225, + isl69227, + isl69228, + isl69234, + isl69236, + isl69239, + isl69242, + isl69243, + isl69247, + isl69248, + isl69254, + isl69255, + isl69256, + isl69259, + isl69260, + isl69268, + isl69269, + isl69298, + raa228000, + raa228004, + raa228006, + raa228228, + raa229001, + raa229004, +}; + +enum variants { + raa_dmpvr1_2rail, + raa_dmpvr2_1rail, + raa_dmpvr2_2rail, + raa_dmpvr2_2rail_nontc, + raa_dmpvr2_3rail, + raa_dmpvr2_hv, +}; + +static const struct i2c_device_id raa_dmpvr_id[]; + +static ssize_t isl68137_avs_enable_show_page(struct i2c_client *client, + int page, + char *buf) +{ + int val = wb_pmbus_read_byte_data(client, page, PMBUS_OPERATION); + + return sprintf(buf, "%d\n", + (val & ISL68137_VOUT_AVS) == ISL68137_VOUT_AVS ? 1 : 0); +} + +static ssize_t isl68137_avs_enable_store_page(struct i2c_client *client, + int page, + const char *buf, size_t count) +{ + int rc, op_val; + bool result; + + rc = kstrtobool(buf, &result); + if (rc) + return rc; + + op_val = result ? ISL68137_VOUT_AVS : 0; + + /* + * Writes to VOUT setpoint over AVSBus will persist after the VRM is + * switched to PMBus control. Switching back to AVSBus control + * restores this persisted setpoint rather than re-initializing to + * PMBus VOUT_COMMAND. Writing VOUT_COMMAND first over PMBus before + * enabling AVS control is the workaround. + */ + if (op_val == ISL68137_VOUT_AVS) { + rc = wb_pmbus_read_word_data(client, page, 0xff, + PMBUS_VOUT_COMMAND); + if (rc < 0) + return rc; + + rc = wb_pmbus_write_word_data(client, page, PMBUS_VOUT_COMMAND, + rc); + if (rc < 0) + return rc; + } + + rc = wb_pmbus_update_byte_data(client, page, PMBUS_OPERATION, + ISL68137_VOUT_AVS, op_val); + + return (rc < 0) ? rc : count; +} + +static ssize_t isl68137_avs_enable_show(struct device *dev, + struct device_attribute *devattr, + char *buf) +{ + struct i2c_client *client = to_i2c_client(dev->parent); + struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); + + return isl68137_avs_enable_show_page(client, attr->index, buf); +} + +static ssize_t isl68137_avs_enable_store(struct device *dev, + struct device_attribute *devattr, + const char *buf, size_t count) +{ + struct i2c_client *client = to_i2c_client(dev->parent); + struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); + + return isl68137_avs_enable_store_page(client, attr->index, buf, count); +} + +static ssize_t isl68137_avs_vout_show(struct device *dev, struct device_attribute *devattr, + char *buf) +{ + struct i2c_client *client = to_i2c_client(dev->parent); + struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); + struct pmbus_data *data = i2c_get_clientdata(client); + int ret, vout_cmd, vout; + + mutex_lock(&data->update_lock); + vout_cmd = wb_pmbus_read_word_data(client, attr->index, 0xff, PMBUS_VOUT_COMMAND); + if (vout_cmd < 0) { + WB_ISL68137_ERROR("%d-%04x: read page%d vout command reg: 0x%x failed, ret: %d\n", + client->adapter->nr, client->addr, attr->index, PMBUS_VOUT_COMMAND, ret); + mutex_unlock(&data->update_lock); + return vout_cmd; + } + vout = vout_cmd * 1000; + WB_ISL68137_VERBOSE("%d-%04x: page%d, vout: %d, vout_cmd: 0x%x\n", client->adapter->nr, + client->addr, attr->index, vout, vout_cmd); + mutex_unlock(&data->update_lock); + return snprintf(buf, PAGE_SIZE, "%d\n", vout); +} + +static ssize_t isl68137_avs_vout_store(struct device *dev, struct device_attribute *devattr, + const char *buf, size_t count) +{ + struct i2c_client *client = to_i2c_client(dev->parent); + struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); + struct pmbus_data *data = i2c_get_clientdata(client); + int vout, vout_max, vout_min; + int ret, vout_cmd, vout_cmd_set; + + if ((attr->index < 0) || (attr->index >= PMBUS_PAGES)) { + WB_ISL68137_ERROR("%d-%04x: invalid index: %d \n", client->adapter->nr, client->addr, + attr->index); + return -EINVAL; + } + + ret = kstrtoint(buf, 0, &vout); + if (ret) { + WB_ISL68137_ERROR("%d-%04x: invalid value: %s \n", client->adapter->nr, client->addr, buf); + return -EINVAL; + } + + vout_max = data->vout_max[attr->index]; + vout_min = data->vout_min[attr->index]; + if ((vout > vout_max) || (vout < vout_min)) { + WB_ISL68137_ERROR("%d-%04x: vout value: %d, out of range [%d, %d] \n", client->adapter->nr, + client->addr, vout, vout_min, vout_max); + return -EINVAL; + } + + /* calc VOUT_COMMAND set value */ + vout_cmd_set = vout / 1000; + if (vout_cmd_set > 0xffff) { + WB_ISL68137_ERROR("%d-%04x: invalid value, vout %d, vout_cmd_set: 0x%x\n", + client->adapter->nr, client->addr, vout, vout_cmd_set); + return -EINVAL; + } + + mutex_lock(&data->update_lock); + + /* close write protect */ + ret = wb_pmbus_write_byte_data(client, attr->index, PMBUS_WRITE_PROTECT, WRITE_PROTECT_CLOSE); + if (ret < 0) { + WB_ISL68137_ERROR("%d-%04x: close page%d write protect failed, ret: %d\n", client->adapter->nr, + client->addr, attr->index, ret); + mutex_unlock(&data->update_lock); + return ret; + } + + /* set VOUT_COMMAND */ + ret = wb_pmbus_write_word_data(client, attr->index, PMBUS_VOUT_COMMAND, vout_cmd_set); + if (ret < 0) { + WB_ISL68137_ERROR("%d-%04x: set page%d vout cmd reg: 0x%x, value: 0x%x failed, ret: %d\n", + client->adapter->nr, client->addr, attr->index, PMBUS_VOUT_COMMAND, vout_cmd_set, ret); + goto error; + } + + /* read back VOUT_COMMAND */ + vout_cmd = wb_pmbus_read_word_data(client, attr->index, 0xff, PMBUS_VOUT_COMMAND); + if (vout_cmd < 0) { + ret = vout_cmd; + WB_ISL68137_ERROR("%d-%04x: read page%d vout command reg: 0x%x failed, ret: %d\n", + client->adapter->nr, client->addr, attr->index, PMBUS_VOUT_COMMAND, ret); + goto error; + } + + /* compare vout_cmd and vout_cmd_set */ + if (vout_cmd != vout_cmd_set) { + ret = -EIO; + WB_ISL68137_ERROR("%d-%04x: vout cmd value check error, vout cmd read: 0x%x, vout cmd set: 0x%x\n", + client->adapter->nr, client->addr, vout_cmd, vout_cmd_set); + goto error; + } + + /* open write protect */ + wb_pmbus_write_byte_data(client, attr->index, PMBUS_WRITE_PROTECT, WRITE_PROTECT_OPEN); + mutex_unlock(&data->update_lock); + WB_ISL68137_VERBOSE("%d-%04x: set page%d vout cmd success, vout %d, vout_cmd_set: 0x%x\n", + client->adapter->nr, client->addr, attr->index, vout, vout_cmd_set); + return count; +error: + wb_pmbus_write_byte_data(client, attr->index, PMBUS_WRITE_PROTECT, WRITE_PROTECT_OPEN); + mutex_unlock(&data->update_lock); + return ret; +} + +static ssize_t isl68137_avs_vout_max_store(struct device *dev, + struct device_attribute *devattr, const char *buf, size_t count) +{ + struct i2c_client *client = to_i2c_client(dev->parent); + struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); + struct pmbus_data *data = i2c_get_clientdata(client); + int ret, vout_threshold; + + if ((attr->index < 0) || (attr->index >= PMBUS_PAGES)) { + WB_ISL68137_ERROR("%d-%04x: invalid index: %d \n", client->adapter->nr, client->addr, + attr->index); + return -EINVAL; + } + + ret = kstrtoint(buf, 0, &vout_threshold); + if (ret) { + WB_ISL68137_ERROR("%d-%04x: invalid value: %s \n", client->adapter->nr, client->addr, buf); + return -EINVAL; + } + + WB_ISL68137_VERBOSE("%d-%04x: vout%d max threshold: %d", client->adapter->nr, client->addr, + attr->index, vout_threshold); + + data->vout_max[attr->index] = vout_threshold; + return count; +} + +static ssize_t isl68137_avs_vout_max_show(struct device *dev, + struct device_attribute *devattr, char *buf) +{ + struct i2c_client *client = to_i2c_client(dev->parent); + struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); + struct pmbus_data *data = i2c_get_clientdata(client); + + if ((attr->index < 0) || (attr->index >= PMBUS_PAGES)) { + WB_ISL68137_ERROR("%d-%04x: invalid index: %d \n", client->adapter->nr, client->addr, + attr->index); + return -EINVAL; + } + + return snprintf(buf, PAGE_SIZE, "%d\n", data->vout_max[attr->index]); +} + +static ssize_t isl68137_avs_vout_min_store(struct device *dev, + struct device_attribute *devattr, const char *buf, size_t count) +{ + struct i2c_client *client = to_i2c_client(dev->parent); + struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); + struct pmbus_data *data = i2c_get_clientdata(client); + int ret, vout_threshold; + + if ((attr->index < 0) || (attr->index >= PMBUS_PAGES)) { + WB_ISL68137_ERROR("%d-%04x: invalid index: %d \n", client->adapter->nr, client->addr, + attr->index); + return -EINVAL; + } + + ret = kstrtoint(buf, 0, &vout_threshold); + if (ret) { + WB_ISL68137_ERROR("%d-%04x: invalid value: %s \n", client->adapter->nr, client->addr, buf); + return -EINVAL; + } + + WB_ISL68137_VERBOSE("%d-%04x: vout%d min threshold: %d", client->adapter->nr, client->addr, + attr->index, vout_threshold); + + data->vout_min[attr->index] = vout_threshold; + return count; +} + +static ssize_t isl68137_avs_vout_min_show(struct device *dev, + struct device_attribute *devattr, char *buf) +{ + struct i2c_client *client = to_i2c_client(dev->parent); + struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr); + struct pmbus_data *data = i2c_get_clientdata(client); + + if ((attr->index < 0) || (attr->index >= PMBUS_PAGES)) { + WB_ISL68137_ERROR("%d-%04x: invalid index: %d \n", client->adapter->nr, client->addr, + attr->index); + return -EINVAL; + } + + return snprintf(buf, PAGE_SIZE, "%d\n", data->vout_min[attr->index]); +} + +static SENSOR_DEVICE_ATTR_RW(avs0_enable, isl68137_avs_enable, 0); +static SENSOR_DEVICE_ATTR_RW(avs1_enable, isl68137_avs_enable, 1); + +static SENSOR_DEVICE_ATTR_RW(avs0_vout, isl68137_avs_vout, 0); +static SENSOR_DEVICE_ATTR_RW(avs1_vout, isl68137_avs_vout, 1); +static SENSOR_DEVICE_ATTR_RW(avs0_vout_max, isl68137_avs_vout_max, 0); +static SENSOR_DEVICE_ATTR_RW(avs0_vout_min, isl68137_avs_vout_min, 0); +static SENSOR_DEVICE_ATTR_RW(avs1_vout_max, isl68137_avs_vout_max, 1); +static SENSOR_DEVICE_ATTR_RW(avs1_vout_min, isl68137_avs_vout_min, 1); + +static struct attribute *enable_attrs[] = { + &sensor_dev_attr_avs0_enable.dev_attr.attr, + &sensor_dev_attr_avs1_enable.dev_attr.attr, + NULL, +}; + +static struct attribute *avs_ctrl_attrs[] = { + &sensor_dev_attr_avs0_vout.dev_attr.attr, + &sensor_dev_attr_avs1_vout.dev_attr.attr, + &sensor_dev_attr_avs0_vout_max.dev_attr.attr, + &sensor_dev_attr_avs0_vout_min.dev_attr.attr, + &sensor_dev_attr_avs1_vout_max.dev_attr.attr, + &sensor_dev_attr_avs1_vout_min.dev_attr.attr, + NULL, +}; + +static const struct attribute_group enable_group = { + .attrs = enable_attrs, +}; + +static const struct attribute_group avs_ctrl_group = { + .attrs = avs_ctrl_attrs, +}; + +static const struct attribute_group *isl68137_attribute_groups[] = { + &enable_group, + &avs_ctrl_group, + NULL, +}; + +static int raa_dmpvr2_read_word_data(struct i2c_client *client, int page, + int phase, int reg) +{ + int ret; + + switch (reg) { + case PMBUS_VIRT_READ_VMON: + ret = wb_pmbus_read_word_data(client, page, phase, + RAA_DMPVR2_READ_VMON); + break; + default: + ret = -ENODATA; + break; + } + + return ret; +} + +static struct pmbus_driver_info raa_dmpvr_info = { + .pages = 3, + .format[PSC_VOLTAGE_IN] = direct, + .format[PSC_VOLTAGE_OUT] = direct, + .format[PSC_CURRENT_IN] = direct, + .format[PSC_CURRENT_OUT] = direct, + .format[PSC_POWER] = direct, + .format[PSC_TEMPERATURE] = direct, + .m[PSC_VOLTAGE_IN] = 1, + .b[PSC_VOLTAGE_IN] = 0, + .R[PSC_VOLTAGE_IN] = 2, + .m[PSC_VOLTAGE_OUT] = 1, + .b[PSC_VOLTAGE_OUT] = 0, + .R[PSC_VOLTAGE_OUT] = 3, + .m[PSC_CURRENT_IN] = 1, + .b[PSC_CURRENT_IN] = 0, + .R[PSC_CURRENT_IN] = 2, + .m[PSC_CURRENT_OUT] = 1, + .b[PSC_CURRENT_OUT] = 0, + .R[PSC_CURRENT_OUT] = 1, + .m[PSC_POWER] = 1, + .b[PSC_POWER] = 0, + .R[PSC_POWER] = 0, + .m[PSC_TEMPERATURE] = 1, + .b[PSC_TEMPERATURE] = 0, + .R[PSC_TEMPERATURE] = 0, + .func[0] = PMBUS_HAVE_VIN | PMBUS_HAVE_IIN | PMBUS_HAVE_PIN + | PMBUS_HAVE_STATUS_INPUT | PMBUS_HAVE_TEMP | PMBUS_HAVE_TEMP2 + | PMBUS_HAVE_TEMP3 | PMBUS_HAVE_STATUS_TEMP + | PMBUS_HAVE_VOUT | PMBUS_HAVE_STATUS_VOUT + | PMBUS_HAVE_IOUT | PMBUS_HAVE_STATUS_IOUT | PMBUS_HAVE_POUT + | PMBUS_HAVE_VMON, + .func[1] = PMBUS_HAVE_IIN | PMBUS_HAVE_PIN | PMBUS_HAVE_STATUS_INPUT + | PMBUS_HAVE_TEMP | PMBUS_HAVE_TEMP3 | PMBUS_HAVE_STATUS_TEMP + | PMBUS_HAVE_VOUT | PMBUS_HAVE_STATUS_VOUT | PMBUS_HAVE_IOUT + | PMBUS_HAVE_STATUS_IOUT | PMBUS_HAVE_POUT, + .func[2] = PMBUS_HAVE_IIN | PMBUS_HAVE_PIN | PMBUS_HAVE_STATUS_INPUT + | PMBUS_HAVE_TEMP | PMBUS_HAVE_TEMP3 | PMBUS_HAVE_STATUS_TEMP + | PMBUS_HAVE_VOUT | PMBUS_HAVE_STATUS_VOUT | PMBUS_HAVE_IOUT + | PMBUS_HAVE_STATUS_IOUT | PMBUS_HAVE_POUT, +}; + +static int isl68137_probe(struct i2c_client *client) +{ + struct pmbus_driver_info *info; + + info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL); + if (!info) + return -ENOMEM; + memcpy(info, &raa_dmpvr_info, sizeof(*info)); + + switch (i2c_match_id(raa_dmpvr_id, client)->driver_data) { + case raa_dmpvr1_2rail: + info->pages = 2; + info->R[PSC_VOLTAGE_IN] = 3; + info->func[0] &= ~PMBUS_HAVE_VMON; + info->func[1] = PMBUS_HAVE_VOUT | PMBUS_HAVE_STATUS_VOUT + | PMBUS_HAVE_IOUT | PMBUS_HAVE_STATUS_IOUT + | PMBUS_HAVE_POUT; + info->groups = isl68137_attribute_groups; + break; + case raa_dmpvr2_1rail: + info->pages = 1; + info->read_word_data = raa_dmpvr2_read_word_data; + break; + case raa_dmpvr2_2rail_nontc: + info->func[0] &= ~PMBUS_HAVE_TEMP3; + info->func[1] &= ~PMBUS_HAVE_TEMP3; + fallthrough; + case raa_dmpvr2_2rail: + info->pages = 2; + info->read_word_data = raa_dmpvr2_read_word_data; + break; + case raa_dmpvr2_3rail: + info->read_word_data = raa_dmpvr2_read_word_data; + break; + case raa_dmpvr2_hv: + info->pages = 1; + info->R[PSC_VOLTAGE_IN] = 1; + info->m[PSC_VOLTAGE_OUT] = 2; + info->R[PSC_VOLTAGE_OUT] = 2; + info->m[PSC_CURRENT_IN] = 2; + info->m[PSC_POWER] = 2; + info->R[PSC_POWER] = -1; + info->read_word_data = raa_dmpvr2_read_word_data; + break; + default: + return -ENODEV; + } + + return wb_pmbus_do_probe(client, info); +} + +static const struct i2c_device_id raa_dmpvr_id[] = { + {"wb_isl68127", raa_dmpvr1_2rail}, + {"wb_isl68137", raa_dmpvr1_2rail}, + {"wb_isl68220", raa_dmpvr2_2rail}, + {"wb_isl68221", raa_dmpvr2_3rail}, + {"wb_isl68222", raa_dmpvr2_2rail}, + {"wb_isl68223", raa_dmpvr2_2rail}, + {"wb_isl68224", raa_dmpvr2_3rail}, + {"wb_isl68225", raa_dmpvr2_2rail}, + {"wb_isl68226", raa_dmpvr2_3rail}, + {"wb_isl68227", raa_dmpvr2_1rail}, + {"wb_isl68229", raa_dmpvr2_3rail}, + {"wb_isl68233", raa_dmpvr2_2rail}, + {"wb_isl68239", raa_dmpvr2_3rail}, + + {"wb_isl69222", raa_dmpvr2_2rail}, + {"wb_isl69223", raa_dmpvr2_3rail}, + {"wb_isl69224", raa_dmpvr2_2rail}, + {"wb_isl69225", raa_dmpvr2_2rail}, + {"wb_isl69227", raa_dmpvr2_3rail}, + {"wb_isl69228", raa_dmpvr2_3rail}, + {"wb_isl69234", raa_dmpvr2_2rail}, + {"wb_isl69236", raa_dmpvr2_2rail}, + {"wb_isl69239", raa_dmpvr2_3rail}, + {"wb_isl69242", raa_dmpvr2_2rail}, + {"wb_isl69243", raa_dmpvr2_1rail}, + {"wb_isl69247", raa_dmpvr2_2rail}, + {"wb_isl69248", raa_dmpvr2_2rail}, + {"wb_isl69254", raa_dmpvr2_2rail}, + {"wb_isl69255", raa_dmpvr2_2rail}, + {"wb_isl69256", raa_dmpvr2_2rail}, + {"wb_isl69259", raa_dmpvr2_2rail}, + {"wb_isl69260", raa_dmpvr2_2rail}, + {"wb_isl69268", raa_dmpvr2_2rail}, + {"wb_isl69269", raa_dmpvr2_3rail}, + {"wb_isl69298", raa_dmpvr2_2rail}, + + {"wb_raa228000", raa_dmpvr2_hv}, + {"wb_raa228004", raa_dmpvr2_hv}, + {"wb_raa228006", raa_dmpvr2_hv}, + {"wb_raa228228", raa_dmpvr2_2rail_nontc}, + {"wb_raa229001", raa_dmpvr2_2rail}, + {"wb_raa229004", raa_dmpvr2_2rail}, + {} +}; + +MODULE_DEVICE_TABLE(i2c, raa_dmpvr_id); + +/* This is the driver that will be inserted */ +static struct i2c_driver isl68137_driver = { + .driver = { + .name = "wb_isl68137", + }, + .probe_new = isl68137_probe, + .remove = wb_pmbus_do_remove, + .id_table = raa_dmpvr_id, +}; + +module_i2c_driver(isl68137_driver); + +MODULE_AUTHOR("support"); +MODULE_DESCRIPTION("PMBus driver for Renesas digital multiphase voltage regulators"); +MODULE_LICENSE("GPL"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_lm75.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_lm75.c new file mode 100644 index 000000000000..b8291c553688 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_lm75.c @@ -0,0 +1,987 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * lm75.c - Part of lm_sensors, Linux kernel modules for hardware + * monitoring + * Copyright (c) 1998, 1999 Frodo Looijaard + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "wb_lm75.h" + +/* + * This driver handles the LM75 and compatible digital temperature sensors. + */ + +enum lm75_type { /* keep sorted in alphabetical order */ + adt75, + ds1775, + ds75, + ds7505, + g751, + lm75, + lm75a, + lm75b, + max6625, + max6626, + max31725, + mcp980x, + pct2075, + stds75, + stlm75, + tcn75, + tmp100, + tmp101, + tmp105, + tmp112, + tmp175, + tmp275, + tmp75, + tmp75b, + tmp75c, +}; + +/** + * struct lm75_params - lm75 configuration parameters. + * @set_mask: Bits to set in configuration register when configuring + * the chip. + * @clr_mask: Bits to clear in configuration register when configuring + * the chip. + * @default_resolution: Default number of bits to represent the temperature + * value. + * @resolution_limits: Limit register resolution. Optional. Should be set if + * the resolution of limit registers does not match the + * resolution of the temperature register. + * @resolutions: List of resolutions associated with sample times. + * Optional. Should be set if num_sample_times is larger + * than 1, and if the resolution changes with sample times. + * If set, number of entries must match num_sample_times. + * @default_sample_time:Sample time to be set by default. + * @num_sample_times: Number of possible sample times to be set. Optional. + * Should be set if the number of sample times is larger + * than one. + * @sample_times: All the possible sample times to be set. Mandatory if + * num_sample_times is larger than 1. If set, number of + * entries must match num_sample_times. + */ + +struct lm75_params { + u8 set_mask; + u8 clr_mask; + u8 default_resolution; + u8 resolution_limits; + const u8 *resolutions; + unsigned int default_sample_time; + u8 num_sample_times; + const unsigned int *sample_times; +}; +#if 0 +/* Addresses scanned */ +static const unsigned short normal_i2c[] = { 0x48, 0x49, 0x4a, 0x4b, 0x4c, + 0x4d, 0x4e, 0x4f, I2C_CLIENT_END }; +#endif +/* The LM75 registers */ +#define LM75_REG_TEMP 0x00 +#define LM75_REG_CONF 0x01 +#define LM75_REG_HYST 0x02 +#define LM75_REG_MAX 0x03 +#define PCT2075_REG_IDLE 0x04 +#define LM75_TEMP_INVALID_RETRY_TIMES (3) + +/* Each client has this additional data */ +struct lm75_data { + struct i2c_client *client; + struct regmap *regmap; + struct regulator *vs; + u8 orig_conf; + u8 current_conf; + u8 resolution; /* In bits, 9 to 16 */ + unsigned int sample_time; /* In ms */ + enum lm75_type kind; + const struct lm75_params *params; +}; + +/*-----------------------------------------------------------------------*/ + +static const u8 lm75_sample_set_masks[] = { 0 << 5, 1 << 5, 2 << 5, 3 << 5 }; + +#define LM75_SAMPLE_CLEAR_MASK (3 << 5) + +/* The structure below stores the configuration values of the supported devices. + * In case of being supported multiple configurations, the default one must + * always be the first element of the array + */ +static const struct lm75_params device_params[] = { + [adt75] = { + .clr_mask = 1 << 5, /* not one-shot mode */ + .default_resolution = 12, + .default_sample_time = MSEC_PER_SEC / 10, + }, + [ds1775] = { + .clr_mask = 3 << 5, + .set_mask = 2 << 5, /* 11-bit mode */ + .default_resolution = 11, + .default_sample_time = 500, + .num_sample_times = 4, + .sample_times = (unsigned int []){ 125, 250, 500, 1000 }, + .resolutions = (u8 []) {9, 10, 11, 12 }, + }, + [ds75] = { + .clr_mask = 3 << 5, + .set_mask = 2 << 5, /* 11-bit mode */ + .default_resolution = 11, + .default_sample_time = 600, + .num_sample_times = 4, + .sample_times = (unsigned int []){ 150, 300, 600, 1200 }, + .resolutions = (u8 []) {9, 10, 11, 12 }, + }, + [stds75] = { + .clr_mask = 3 << 5, + .set_mask = 2 << 5, /* 11-bit mode */ + .default_resolution = 11, + .default_sample_time = 600, + .num_sample_times = 4, + .sample_times = (unsigned int []){ 150, 300, 600, 1200 }, + .resolutions = (u8 []) {9, 10, 11, 12 }, + }, + [stlm75] = { + .default_resolution = 9, + .default_sample_time = MSEC_PER_SEC / 6, + }, + [ds7505] = { + .set_mask = 3 << 5, /* 12-bit mode*/ + .default_resolution = 12, + .default_sample_time = 200, + .num_sample_times = 4, + .sample_times = (unsigned int []){ 25, 50, 100, 200 }, + .resolutions = (u8 []) {9, 10, 11, 12 }, + }, + [g751] = { + .default_resolution = 9, + .default_sample_time = MSEC_PER_SEC / 10, + }, + [lm75] = { + .default_resolution = 9, + .default_sample_time = MSEC_PER_SEC / 10, + }, + [lm75a] = { + .default_resolution = 9, + .default_sample_time = MSEC_PER_SEC / 10, + }, + [lm75b] = { + .default_resolution = 11, + .default_sample_time = MSEC_PER_SEC / 10, + }, + [max6625] = { + .default_resolution = 9, + .default_sample_time = MSEC_PER_SEC / 7, + }, + [max6626] = { + .default_resolution = 12, + .default_sample_time = MSEC_PER_SEC / 7, + .resolution_limits = 9, + }, + [max31725] = { + .default_resolution = 16, + .default_sample_time = MSEC_PER_SEC / 20, + }, + [tcn75] = { + .default_resolution = 9, + .default_sample_time = MSEC_PER_SEC / 18, + }, + [pct2075] = { + .default_resolution = 11, + .default_sample_time = MSEC_PER_SEC / 10, + .num_sample_times = 31, + .sample_times = (unsigned int []){ 100, 200, 300, 400, 500, 600, + 700, 800, 900, 1000, 1100, 1200, 1300, 1400, 1500, 1600, 1700, + 1800, 1900, 2000, 2100, 2200, 2300, 2400, 2500, 2600, 2700, + 2800, 2900, 3000, 3100 }, + }, + [mcp980x] = { + .set_mask = 3 << 5, /* 12-bit mode */ + .clr_mask = 1 << 7, /* not one-shot mode */ + .default_resolution = 12, + .resolution_limits = 9, + .default_sample_time = 240, + .num_sample_times = 4, + .sample_times = (unsigned int []){ 30, 60, 120, 240 }, + .resolutions = (u8 []) {9, 10, 11, 12 }, + }, + [tmp100] = { + .set_mask = 3 << 5, /* 12-bit mode */ + .clr_mask = 1 << 7, /* not one-shot mode */ + .default_resolution = 12, + .default_sample_time = 320, + .num_sample_times = 4, + .sample_times = (unsigned int []){ 40, 80, 160, 320 }, + .resolutions = (u8 []) {9, 10, 11, 12 }, + }, + [tmp101] = { + .set_mask = 3 << 5, /* 12-bit mode */ + .clr_mask = 1 << 7, /* not one-shot mode */ + .default_resolution = 12, + .default_sample_time = 320, + .num_sample_times = 4, + .sample_times = (unsigned int []){ 40, 80, 160, 320 }, + .resolutions = (u8 []) {9, 10, 11, 12 }, + }, + [tmp105] = { + .set_mask = 3 << 5, /* 12-bit mode */ + .clr_mask = 1 << 7, /* not one-shot mode*/ + .default_resolution = 12, + .default_sample_time = 220, + .num_sample_times = 4, + .sample_times = (unsigned int []){ 28, 55, 110, 220 }, + .resolutions = (u8 []) {9, 10, 11, 12 }, + }, + [tmp112] = { + .set_mask = 3 << 5, /* 8 samples / second */ + .clr_mask = 1 << 7, /* no one-shot mode*/ + .default_resolution = 12, + .default_sample_time = 125, + .num_sample_times = 4, + .sample_times = (unsigned int []){ 125, 250, 1000, 4000 }, + }, + [tmp175] = { + .set_mask = 3 << 5, /* 12-bit mode */ + .clr_mask = 1 << 7, /* not one-shot mode*/ + .default_resolution = 12, + .default_sample_time = 220, + .num_sample_times = 4, + .sample_times = (unsigned int []){ 28, 55, 110, 220 }, + .resolutions = (u8 []) {9, 10, 11, 12 }, + }, + [tmp275] = { + .set_mask = 3 << 5, /* 12-bit mode */ + .clr_mask = 1 << 7, /* not one-shot mode*/ + .default_resolution = 12, + .default_sample_time = 220, + .num_sample_times = 4, + .sample_times = (unsigned int []){ 28, 55, 110, 220 }, + .resolutions = (u8 []) {9, 10, 11, 12 }, + }, + [tmp75] = { + .set_mask = 3 << 5, /* 12-bit mode */ + .clr_mask = 1 << 7, /* not one-shot mode*/ + .default_resolution = 12, + .default_sample_time = 220, + .num_sample_times = 4, + .sample_times = (unsigned int []){ 28, 55, 110, 220 }, + .resolutions = (u8 []) {9, 10, 11, 12 }, + }, + [tmp75b] = { /* not one-shot mode, Conversion rate 37Hz */ + .clr_mask = 1 << 7 | 3 << 5, + .default_resolution = 12, + .default_sample_time = MSEC_PER_SEC / 37, + .sample_times = (unsigned int []){ MSEC_PER_SEC / 37, + MSEC_PER_SEC / 18, + MSEC_PER_SEC / 9, MSEC_PER_SEC / 4 }, + .num_sample_times = 4, + }, + [tmp75c] = { + .clr_mask = 1 << 5, /*not one-shot mode*/ + .default_resolution = 12, + .default_sample_time = MSEC_PER_SEC / 12, + } +}; + +/* input temp threshold check */ +typedef struct lm75_temp_threshold_s { + int chip_type; + int temp_max; + int temp_min; +} lm75_temp_threshold_t; + +static lm75_temp_threshold_t g_lm75_temp_threshold_info[] = { + { + .chip_type = lm75, + .temp_max = 125000, + .temp_min = -55000, + }, +}; + +/*-----------------------------------------------------------------------*/ +static int lm75_input_temp_check(struct lm75_data *data, int input_val) +{ + int i, size; + + size = ARRAY_SIZE(g_lm75_temp_threshold_info); + + for (i = 0; i < size; i++) { + if (g_lm75_temp_threshold_info[i].chip_type == data->kind) { + if ((input_val > g_lm75_temp_threshold_info[i].temp_max) + || (input_val < g_lm75_temp_threshold_info[i].temp_min)) { + dev_dbg(&data->client->dev, "input temp: %d not in range[%d, %d]\n", + input_val, g_lm75_temp_threshold_info[i].temp_min, + g_lm75_temp_threshold_info[i].temp_max); + return -EINVAL; + } + dev_dbg(&data->client->dev, "input temp: %d in range[%d, %d]", input_val, + g_lm75_temp_threshold_info[i].temp_min, g_lm75_temp_threshold_info[i].temp_max); + return 0; + } + } + return 0; +} + +static inline long lm75_reg_to_mc(s16 temp, u8 resolution) +{ + return ((temp >> (16 - resolution)) * 1000) >> (resolution - 8); +} + +static int lm75_write_config(struct lm75_data *data, u8 set_mask, + u8 clr_mask) +{ + u8 value; + + clr_mask |= LM75_SHUTDOWN; + value = data->current_conf & ~clr_mask; + value |= set_mask; + + if (data->current_conf != value) { + s32 err; + + err = i2c_smbus_write_byte_data(data->client, LM75_REG_CONF, + value); + if (err) + return err; + data->current_conf = value; + } + return 0; +} + +static int lm75_read(struct device *dev, enum hwmon_sensor_types type, u32 attr, int channel, + long *val) +{ + struct lm75_data *data = dev_get_drvdata(dev); + unsigned int regval; + int err, reg, i, ret; + + switch (type) { + case hwmon_chip: + switch (attr) { + case hwmon_chip_update_interval: + *val = data->sample_time; + break; + default: + return -EINVAL; + } + break; + case hwmon_temp: + switch (attr) { + case hwmon_temp_input: + reg = LM75_REG_TEMP; + break; + case hwmon_temp_max: + reg = LM75_REG_MAX; + break; + case hwmon_temp_max_hyst: + reg = LM75_REG_HYST; + break; + default: + return -EINVAL; + } + for (i = 0; i < LM75_TEMP_INVALID_RETRY_TIMES; i++) { + err = regmap_read(data->regmap, reg, ®val); + if (err < 0) { + return err; + } + *val = lm75_reg_to_mc(regval, data->resolution); + if (attr != LM75_REG_TEMP) { + return 0; + } + /* do input_temp_check */ + ret = lm75_input_temp_check(data, *val); + if (ret == 0) { /* input temp check ok */ + return 0; + } + if ((i + 1) < LM75_TEMP_INVALID_RETRY_TIMES) { + msleep(data->sample_time); + } + } + dev_info(&data->client->dev, "temp_input value: %ld invalid\n", *val); + return -EINVAL; + default: + return -EINVAL; + } + return 0; +} + +static int lm75_write_temp(struct device *dev, u32 attr, long temp) +{ + struct lm75_data *data = dev_get_drvdata(dev); + u8 resolution; + int reg; + + switch (attr) { + case hwmon_temp_max: + reg = LM75_REG_MAX; + break; + case hwmon_temp_max_hyst: + reg = LM75_REG_HYST; + break; + default: + return -EINVAL; + } + + /* + * Resolution of limit registers is assumed to be the same as the + * temperature input register resolution unless given explicitly. + */ + if (data->params->resolution_limits) + resolution = data->params->resolution_limits; + else + resolution = data->resolution; + + temp = clamp_val(temp, LM75_TEMP_MIN, LM75_TEMP_MAX); + temp = DIV_ROUND_CLOSEST(temp << (resolution - 8), + 1000) << (16 - resolution); + + return regmap_write(data->regmap, reg, (u16)temp); +} + +static int lm75_update_interval(struct device *dev, long val) +{ + struct lm75_data *data = dev_get_drvdata(dev); + unsigned int reg; + u8 index; + s32 err; + + index = find_closest(val, data->params->sample_times, + (int)data->params->num_sample_times); + + switch (data->kind) { + default: + err = lm75_write_config(data, lm75_sample_set_masks[index], + LM75_SAMPLE_CLEAR_MASK); + if (err) + return err; + + data->sample_time = data->params->sample_times[index]; + if (data->params->resolutions) + data->resolution = data->params->resolutions[index]; + break; + case tmp112: + err = regmap_read(data->regmap, LM75_REG_CONF, ®); + if (err < 0) + return err; + reg &= ~0x00c0; + reg |= (3 - index) << 6; + err = regmap_write(data->regmap, LM75_REG_CONF, reg); + if (err < 0) + return err; + data->sample_time = data->params->sample_times[index]; + break; + case pct2075: + err = i2c_smbus_write_byte_data(data->client, PCT2075_REG_IDLE, + index + 1); + if (err) + return err; + data->sample_time = data->params->sample_times[index]; + break; + } + return 0; +} + +static int lm75_write_chip(struct device *dev, u32 attr, long val) +{ + switch (attr) { + case hwmon_chip_update_interval: + return lm75_update_interval(dev, val); + default: + return -EINVAL; + } + return 0; +} + +static int lm75_write(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long val) +{ + switch (type) { + case hwmon_chip: + return lm75_write_chip(dev, attr, val); + case hwmon_temp: + return lm75_write_temp(dev, attr, val); + default: + return -EINVAL; + } + return 0; +} + +static umode_t lm75_is_visible(const void *data, enum hwmon_sensor_types type, + u32 attr, int channel) +{ + const struct lm75_data *config_data = data; + + switch (type) { + case hwmon_chip: + switch (attr) { + case hwmon_chip_update_interval: + if (config_data->params->num_sample_times > 1) + return 0644; + return 0444; + } + break; + case hwmon_temp: + switch (attr) { + case hwmon_temp_input: + return 0444; + case hwmon_temp_max: + case hwmon_temp_max_hyst: + return 0644; + } + break; + default: + break; + } + return 0; +} + +static const struct hwmon_channel_info *lm75_info[] = { + HWMON_CHANNEL_INFO(chip, + HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL), + HWMON_CHANNEL_INFO(temp, + HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_MAX_HYST), + NULL +}; + +static const struct hwmon_ops lm75_hwmon_ops = { + .is_visible = lm75_is_visible, + .read = lm75_read, + .write = lm75_write, +}; + +static const struct hwmon_chip_info lm75_chip_info = { + .ops = &lm75_hwmon_ops, + .info = lm75_info, +}; + +static bool lm75_is_writeable_reg(struct device *dev, unsigned int reg) +{ + return reg != LM75_REG_TEMP; +} + +static bool lm75_is_volatile_reg(struct device *dev, unsigned int reg) +{ + return reg == LM75_REG_TEMP || reg == LM75_REG_CONF; +} + +static const struct regmap_config lm75_regmap_config = { + .reg_bits = 8, + .val_bits = 16, + .max_register = PCT2075_REG_IDLE, + .writeable_reg = lm75_is_writeable_reg, + .volatile_reg = lm75_is_volatile_reg, + .val_format_endian = REGMAP_ENDIAN_BIG, + .cache_type = REGCACHE_RBTREE, + .use_single_read = true, + .use_single_write = true, +}; + +static void lm75_disable_regulator(void *data) +{ + struct lm75_data *lm75 = data; + + regulator_disable(lm75->vs); +} + +static void lm75_remove(void *data) +{ + struct lm75_data *lm75 = data; + struct i2c_client *client = lm75->client; + + i2c_smbus_write_byte_data(client, LM75_REG_CONF, lm75->orig_conf); +} + +static const struct i2c_device_id lm75_ids[]; + +static int lm75_probe(struct i2c_client *client) +{ + struct device *dev = &client->dev; + struct device *hwmon_dev; + struct lm75_data *data; + int status, err; + enum lm75_type kind; + + if (client->dev.of_node) + kind = (enum lm75_type)of_device_get_match_data(&client->dev); + else + kind = i2c_match_id(lm75_ids, client)->driver_data; + + if (!i2c_check_functionality(client->adapter, + I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA)) + return -EIO; + + data = devm_kzalloc(dev, sizeof(struct lm75_data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->client = client; + data->kind = kind; + + data->vs = devm_regulator_get(dev, "vs"); + if (IS_ERR(data->vs)) + return PTR_ERR(data->vs); + + data->regmap = devm_regmap_init_i2c(client, &lm75_regmap_config); + if (IS_ERR(data->regmap)) + return PTR_ERR(data->regmap); + + /* Set to LM75 resolution (9 bits, 1/2 degree C) and range. + * Then tweak to be more precise when appropriate. + */ + + data->params = &device_params[data->kind]; + + /* Save default sample time and resolution*/ + data->sample_time = data->params->default_sample_time; + data->resolution = data->params->default_resolution; + + /* Enable the power */ + err = regulator_enable(data->vs); + if (err) { + dev_err(dev, "failed to enable regulator: %d\n", err); + return err; + } + + err = devm_add_action_or_reset(dev, lm75_disable_regulator, data); + if (err) + return err; + + /* Cache original configuration */ + status = i2c_smbus_read_byte_data(client, LM75_REG_CONF); + if (status < 0) { + dev_dbg(dev, "Can't read config? %d\n", status); + return status; + } + data->orig_conf = status; + data->current_conf = status; + + err = lm75_write_config(data, data->params->set_mask, + data->params->clr_mask); + if (err) + return err; + + err = devm_add_action_or_reset(dev, lm75_remove, data); + if (err) + return err; + + hwmon_dev = devm_hwmon_device_register_with_info(dev, client->name, + data, &lm75_chip_info, + NULL); + if (IS_ERR(hwmon_dev)) + return PTR_ERR(hwmon_dev); + + dev_info(dev, "%s: sensor '%s'\n", dev_name(hwmon_dev), client->name); + + return 0; +} + +static const struct i2c_device_id lm75_ids[] = { + { "wb_adt75", adt75, }, + { "wb_ds1775", ds1775, }, + { "wb_ds75", ds75, }, + { "wb_ds7505", ds7505, }, + { "wb_g751", g751, }, + { "wb_lm75", lm75, }, + { "wb_lm75a", lm75a, }, + { "wb_lm75b", lm75b, }, + { "wb_max6625", max6625, }, + { "wb_max6626", max6626, }, + { "wb_max31725", max31725, }, + { "wb_max31726", max31725, }, + { "wb_mcp980x", mcp980x, }, + { "wb_pct2075", pct2075, }, + { "wb_stds75", stds75, }, + { "wb_stlm75", stlm75, }, + { "wb_tcn75", tcn75, }, + { "wb_tmp100", tmp100, }, + { "wb_tmp101", tmp101, }, + { "wb_tmp105", tmp105, }, + { "wb_tmp112", tmp112, }, + { "wb_tmp175", tmp175, }, + { "wb_tmp275", tmp275, }, + { "wb_tmp75", tmp75, }, + { "wb_tmp75b", tmp75b, }, + { "wb_tmp75c", tmp75c, }, + { /* LIST END */ } +}; +MODULE_DEVICE_TABLE(i2c, lm75_ids); + +static const struct of_device_id __maybe_unused lm75_of_match[] = { + { + .compatible = "adi,adt75", + .data = (void *)adt75 + }, + { + .compatible = "dallas,ds1775", + .data = (void *)ds1775 + }, + { + .compatible = "dallas,ds75", + .data = (void *)ds75 + }, + { + .compatible = "dallas,ds7505", + .data = (void *)ds7505 + }, + { + .compatible = "gmt,g751", + .data = (void *)g751 + }, + { + .compatible = "national,lm75", + .data = (void *)lm75 + }, + { + .compatible = "national,lm75a", + .data = (void *)lm75a + }, + { + .compatible = "national,lm75b", + .data = (void *)lm75b + }, + { + .compatible = "maxim,max6625", + .data = (void *)max6625 + }, + { + .compatible = "maxim,max6626", + .data = (void *)max6626 + }, + { + .compatible = "maxim,max31725", + .data = (void *)max31725 + }, + { + .compatible = "maxim,max31726", + .data = (void *)max31725 + }, + { + .compatible = "maxim,mcp980x", + .data = (void *)mcp980x + }, + { + .compatible = "nxp,pct2075", + .data = (void *)pct2075 + }, + { + .compatible = "st,stds75", + .data = (void *)stds75 + }, + { + .compatible = "st,stlm75", + .data = (void *)stlm75 + }, + { + .compatible = "microchip,tcn75", + .data = (void *)tcn75 + }, + { + .compatible = "ti,tmp100", + .data = (void *)tmp100 + }, + { + .compatible = "ti,tmp101", + .data = (void *)tmp101 + }, + { + .compatible = "ti,tmp105", + .data = (void *)tmp105 + }, + { + .compatible = "ti,tmp112", + .data = (void *)tmp112 + }, + { + .compatible = "ti,tmp175", + .data = (void *)tmp175 + }, + { + .compatible = "ti,tmp275", + .data = (void *)tmp275 + }, + { + .compatible = "ti,tmp75", + .data = (void *)tmp75 + }, + { + .compatible = "ti,tmp75b", + .data = (void *)tmp75b + }, + { + .compatible = "ti,tmp75c", + .data = (void *)tmp75c + }, + { }, +}; +MODULE_DEVICE_TABLE(of, lm75_of_match); + +#define LM75A_ID 0xA1 +#if 0 +/* Return 0 if detection is successful, -ENODEV otherwise */ +static int lm75_detect(struct i2c_client *new_client, + struct i2c_board_info *info) +{ + struct i2c_adapter *adapter = new_client->adapter; + int i; + int conf, hyst, os; + bool is_lm75a = 0; + + if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA | + I2C_FUNC_SMBUS_WORD_DATA)) + return -ENODEV; + + /* + * Now, we do the remaining detection. There is no identification- + * dedicated register so we have to rely on several tricks: + * unused bits, registers cycling over 8-address boundaries, + * addresses 0x04-0x07 returning the last read value. + * The cycling+unused addresses combination is not tested, + * since it would significantly slow the detection down and would + * hardly add any value. + * + * The National Semiconductor LM75A is different than earlier + * LM75s. It has an ID byte of 0xaX (where X is the chip + * revision, with 1 being the only revision in existence) in + * register 7, and unused registers return 0xff rather than the + * last read value. + * + * Note that this function only detects the original National + * Semiconductor LM75 and the LM75A. Clones from other vendors + * aren't detected, on purpose, because they are typically never + * found on PC hardware. They are found on embedded designs where + * they can be instantiated explicitly so detection is not needed. + * The absence of identification registers on all these clones + * would make their exhaustive detection very difficult and weak, + * and odds are that the driver would bind to unsupported devices. + */ + + /* Unused bits */ + conf = i2c_smbus_read_byte_data(new_client, 1); + if (conf & 0xe0) + return -ENODEV; + + /* First check for LM75A */ + if (i2c_smbus_read_byte_data(new_client, 7) == LM75A_ID) { + /* + * LM75A returns 0xff on unused registers so + * just to be sure we check for that too. + */ + if (i2c_smbus_read_byte_data(new_client, 4) != 0xff + || i2c_smbus_read_byte_data(new_client, 5) != 0xff + || i2c_smbus_read_byte_data(new_client, 6) != 0xff) + return -ENODEV; + is_lm75a = 1; + hyst = i2c_smbus_read_byte_data(new_client, 2); + os = i2c_smbus_read_byte_data(new_client, 3); + } else { /* Traditional style LM75 detection */ + /* Unused addresses */ + hyst = i2c_smbus_read_byte_data(new_client, 2); + if (i2c_smbus_read_byte_data(new_client, 4) != hyst + || i2c_smbus_read_byte_data(new_client, 5) != hyst + || i2c_smbus_read_byte_data(new_client, 6) != hyst + || i2c_smbus_read_byte_data(new_client, 7) != hyst) + return -ENODEV; + os = i2c_smbus_read_byte_data(new_client, 3); + if (i2c_smbus_read_byte_data(new_client, 4) != os + || i2c_smbus_read_byte_data(new_client, 5) != os + || i2c_smbus_read_byte_data(new_client, 6) != os + || i2c_smbus_read_byte_data(new_client, 7) != os) + return -ENODEV; + } + /* + * It is very unlikely that this is a LM75 if both + * hysteresis and temperature limit registers are 0. + */ + if (hyst == 0 && os == 0) + return -ENODEV; + + /* Addresses cycling */ + for (i = 8; i <= 248; i += 40) { + if (i2c_smbus_read_byte_data(new_client, i + 1) != conf + || i2c_smbus_read_byte_data(new_client, i + 2) != hyst + || i2c_smbus_read_byte_data(new_client, i + 3) != os) + return -ENODEV; + if (is_lm75a && i2c_smbus_read_byte_data(new_client, i + 7) + != LM75A_ID) + return -ENODEV; + } + + strlcpy(info->type, is_lm75a ? "lm75a" : "lm75", I2C_NAME_SIZE); + + return 0; +} +#endif + +#ifdef CONFIG_PM +static int lm75_suspend(struct device *dev) +{ + int status; + struct i2c_client *client = to_i2c_client(dev); + + status = i2c_smbus_read_byte_data(client, LM75_REG_CONF); + if (status < 0) { + dev_dbg(&client->dev, "Can't read config? %d\n", status); + return status; + } + status = status | LM75_SHUTDOWN; + i2c_smbus_write_byte_data(client, LM75_REG_CONF, status); + return 0; +} + +static int lm75_resume(struct device *dev) +{ + int status; + struct i2c_client *client = to_i2c_client(dev); + + status = i2c_smbus_read_byte_data(client, LM75_REG_CONF); + if (status < 0) { + dev_dbg(&client->dev, "Can't read config? %d\n", status); + return status; + } + status = status & ~LM75_SHUTDOWN; + i2c_smbus_write_byte_data(client, LM75_REG_CONF, status); + return 0; +} + +static const struct dev_pm_ops lm75_dev_pm_ops = { + .suspend = lm75_suspend, + .resume = lm75_resume, +}; +#define LM75_DEV_PM_OPS (&lm75_dev_pm_ops) +#else +#define LM75_DEV_PM_OPS NULL +#endif /* CONFIG_PM */ + +static struct i2c_driver lm75_driver = { + .class = I2C_CLASS_HWMON, + .driver = { + .name = "wb_lm75", + .of_match_table = of_match_ptr(lm75_of_match), + .pm = LM75_DEV_PM_OPS, + }, + .probe_new = lm75_probe, + .id_table = lm75_ids, + /* .detect = lm75_detect, */ + /* .address_list = normal_i2c, */ +}; + +module_i2c_driver(lm75_driver); + +MODULE_AUTHOR("support"); +MODULE_DESCRIPTION("LM75 driver"); +MODULE_LICENSE("GPL"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_lm75.h b/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_lm75.h new file mode 100644 index 000000000000..a398171162a8 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_lm75.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * lm75.h - Part of lm_sensors, Linux kernel modules for hardware monitoring + * Copyright (c) 2003 Mark M. Hoffman + */ + +/* + * This file contains common code for encoding/decoding LM75 type + * temperature readings, which are emulated by many of the chips + * we support. As the user is unlikely to load more than one driver + * which contains this code, we don't worry about the wasted space. + */ + +#include + +/* straight from the datasheet */ +#define LM75_TEMP_MIN (-55000) +#define LM75_TEMP_MAX 125000 +#define LM75_SHUTDOWN 0x01 + +/* + * TEMP: 0.001C/bit (-55C to +125C) + * REG: (0.5C/bit, two's complement) << 7 + */ +static inline u16 LM75_TEMP_TO_REG(long temp) +{ + int ntemp = clamp_val(temp, LM75_TEMP_MIN, LM75_TEMP_MAX); + + ntemp += (ntemp < 0 ? -250 : 250); + return (u16)((ntemp / 500) << 7); +} + +static inline int LM75_TEMP_FROM_REG(u16 reg) +{ + /* + * use integer division instead of equivalent right shift to + * guarantee arithmetic shift and preserve the sign + */ + return ((s16)reg / 128) * 500; +} diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_pmbus.h b/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_pmbus.h new file mode 100644 index 000000000000..9fb2c9017ae6 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_pmbus.h @@ -0,0 +1,535 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * wb_pmbus.h - Common defines and structures for PMBus devices + * + * Copyright (c) 2010, 2011 Ericsson AB. + * Copyright (c) 2012 Guenter Roeck + */ + +#ifndef WB_PMBUS_H +#define WB_PMBUS_H + +#include +#include +#include + +#define mem_clear(data, size) memset((data), 0, (size)) + +/* + * Registers + */ +enum pmbus_regs { + PMBUS_PAGE = 0x00, + PMBUS_OPERATION = 0x01, + PMBUS_ON_OFF_CONFIG = 0x02, + PMBUS_CLEAR_FAULTS = 0x03, + PMBUS_PHASE = 0x04, + + PMBUS_WRITE_PROTECT = 0x10, + + PMBUS_CAPABILITY = 0x19, + PMBUS_QUERY = 0x1A, + + PMBUS_VOUT_MODE = 0x20, + PMBUS_VOUT_COMMAND = 0x21, + PMBUS_VOUT_TRIM = 0x22, + PMBUS_VOUT_CAL_OFFSET = 0x23, + PMBUS_VOUT_MAX = 0x24, + PMBUS_VOUT_MARGIN_HIGH = 0x25, + PMBUS_VOUT_MARGIN_LOW = 0x26, + PMBUS_VOUT_TRANSITION_RATE = 0x27, + PMBUS_VOUT_DROOP = 0x28, + PMBUS_VOUT_SCALE_LOOP = 0x29, + PMBUS_VOUT_SCALE_MONITOR = 0x2A, + + PMBUS_COEFFICIENTS = 0x30, + PMBUS_POUT_MAX = 0x31, + + PMBUS_FAN_CONFIG_12 = 0x3A, + PMBUS_FAN_COMMAND_1 = 0x3B, + PMBUS_FAN_COMMAND_2 = 0x3C, + PMBUS_FAN_CONFIG_34 = 0x3D, + PMBUS_FAN_COMMAND_3 = 0x3E, + PMBUS_FAN_COMMAND_4 = 0x3F, + + PMBUS_VOUT_OV_FAULT_LIMIT = 0x40, + PMBUS_VOUT_OV_FAULT_RESPONSE = 0x41, + PMBUS_VOUT_OV_WARN_LIMIT = 0x42, + PMBUS_VOUT_UV_WARN_LIMIT = 0x43, + PMBUS_VOUT_UV_FAULT_LIMIT = 0x44, + PMBUS_VOUT_UV_FAULT_RESPONSE = 0x45, + PMBUS_IOUT_OC_FAULT_LIMIT = 0x46, + PMBUS_IOUT_OC_FAULT_RESPONSE = 0x47, + PMBUS_IOUT_OC_LV_FAULT_LIMIT = 0x48, + PMBUS_IOUT_OC_LV_FAULT_RESPONSE = 0x49, + PMBUS_IOUT_OC_WARN_LIMIT = 0x4A, + PMBUS_IOUT_UC_FAULT_LIMIT = 0x4B, + PMBUS_IOUT_UC_FAULT_RESPONSE = 0x4C, + + PMBUS_OT_FAULT_LIMIT = 0x4F, + PMBUS_OT_FAULT_RESPONSE = 0x50, + PMBUS_OT_WARN_LIMIT = 0x51, + PMBUS_UT_WARN_LIMIT = 0x52, + PMBUS_UT_FAULT_LIMIT = 0x53, + PMBUS_UT_FAULT_RESPONSE = 0x54, + PMBUS_VIN_OV_FAULT_LIMIT = 0x55, + PMBUS_VIN_OV_FAULT_RESPONSE = 0x56, + PMBUS_VIN_OV_WARN_LIMIT = 0x57, + PMBUS_VIN_UV_WARN_LIMIT = 0x58, + PMBUS_VIN_UV_FAULT_LIMIT = 0x59, + + PMBUS_IIN_OC_FAULT_LIMIT = 0x5B, + PMBUS_IIN_OC_WARN_LIMIT = 0x5D, + + PMBUS_POUT_OP_FAULT_LIMIT = 0x68, + PMBUS_POUT_OP_WARN_LIMIT = 0x6A, + PMBUS_PIN_OP_WARN_LIMIT = 0x6B, + + PMBUS_STATUS_BYTE = 0x78, + PMBUS_STATUS_WORD = 0x79, + PMBUS_STATUS_VOUT = 0x7A, + PMBUS_STATUS_IOUT = 0x7B, + PMBUS_STATUS_INPUT = 0x7C, + PMBUS_STATUS_TEMPERATURE = 0x7D, + PMBUS_STATUS_CML = 0x7E, + PMBUS_STATUS_OTHER = 0x7F, + PMBUS_STATUS_MFR_SPECIFIC = 0x80, + PMBUS_STATUS_FAN_12 = 0x81, + PMBUS_STATUS_FAN_34 = 0x82, + + PMBUS_READ_VIN = 0x88, + PMBUS_READ_IIN = 0x89, + PMBUS_READ_VCAP = 0x8A, + PMBUS_READ_VOUT = 0x8B, + PMBUS_READ_IOUT = 0x8C, + PMBUS_READ_TEMPERATURE_1 = 0x8D, + PMBUS_READ_TEMPERATURE_2 = 0x8E, + PMBUS_READ_TEMPERATURE_3 = 0x8F, + PMBUS_READ_FAN_SPEED_1 = 0x90, + PMBUS_READ_FAN_SPEED_2 = 0x91, + PMBUS_READ_FAN_SPEED_3 = 0x92, + PMBUS_READ_FAN_SPEED_4 = 0x93, + PMBUS_READ_DUTY_CYCLE = 0x94, + PMBUS_READ_FREQUENCY = 0x95, + PMBUS_READ_POUT = 0x96, + PMBUS_READ_PIN = 0x97, + + PMBUS_REVISION = 0x98, + PMBUS_MFR_ID = 0x99, + PMBUS_MFR_MODEL = 0x9A, + PMBUS_MFR_REVISION = 0x9B, + PMBUS_MFR_LOCATION = 0x9C, + PMBUS_MFR_DATE = 0x9D, + PMBUS_MFR_SERIAL = 0x9E, + + PMBUS_MFR_VIN_MIN = 0xA0, + PMBUS_MFR_VIN_MAX = 0xA1, + PMBUS_MFR_IIN_MAX = 0xA2, + PMBUS_MFR_PIN_MAX = 0xA3, + PMBUS_MFR_VOUT_MIN = 0xA4, + PMBUS_MFR_VOUT_MAX = 0xA5, + PMBUS_MFR_IOUT_MAX = 0xA6, + PMBUS_MFR_POUT_MAX = 0xA7, + + PMBUS_IC_DEVICE_ID = 0xAD, + PMBUS_IC_DEVICE_REV = 0xAE, + + PMBUS_MFR_MAX_TEMP_1 = 0xC0, + PMBUS_MFR_MAX_TEMP_2 = 0xC1, + PMBUS_MFR_MAX_TEMP_3 = 0xC2, + +/* + * Virtual registers. + * Useful to support attributes which are not supported by standard PMBus + * registers but exist as manufacturer specific registers on individual chips. + * Must be mapped to real registers in device specific code. + * + * Semantics: + * Virtual registers are all word size. + * READ registers are read-only; writes are either ignored or return an error. + * RESET registers are read/write. Reading reset registers returns zero + * (used for detection), writing any value causes the associated history to be + * reset. + * Virtual registers have to be handled in device specific driver code. Chip + * driver code returns non-negative register values if a virtual register is + * supported, or a negative error code if not. The chip driver may return + * -ENODATA or any other error code in this case, though an error code other + * than -ENODATA is handled more efficiently and thus preferred. Either case, + * the calling PMBus core code will abort if the chip driver returns an error + * code when reading or writing virtual registers. + */ + PMBUS_VIRT_BASE = 0x100, + PMBUS_VIRT_READ_TEMP_AVG, + PMBUS_VIRT_READ_TEMP_MIN, + PMBUS_VIRT_READ_TEMP_MAX, + PMBUS_VIRT_RESET_TEMP_HISTORY, + PMBUS_VIRT_READ_VIN_AVG, + PMBUS_VIRT_READ_VIN_MIN, + PMBUS_VIRT_READ_VIN_MAX, + PMBUS_VIRT_RESET_VIN_HISTORY, + PMBUS_VIRT_READ_IIN_AVG, + PMBUS_VIRT_READ_IIN_MIN, + PMBUS_VIRT_READ_IIN_MAX, + PMBUS_VIRT_RESET_IIN_HISTORY, + PMBUS_VIRT_READ_PIN_AVG, + PMBUS_VIRT_READ_PIN_MIN, + PMBUS_VIRT_READ_PIN_MAX, + PMBUS_VIRT_RESET_PIN_HISTORY, + PMBUS_VIRT_READ_POUT_AVG, + PMBUS_VIRT_READ_POUT_MIN, + PMBUS_VIRT_READ_POUT_MAX, + PMBUS_VIRT_RESET_POUT_HISTORY, + PMBUS_VIRT_READ_VOUT_AVG, + PMBUS_VIRT_READ_VOUT_MIN, + PMBUS_VIRT_READ_VOUT_MAX, + PMBUS_VIRT_RESET_VOUT_HISTORY, + PMBUS_VIRT_READ_IOUT_AVG, + PMBUS_VIRT_READ_IOUT_MIN, + PMBUS_VIRT_READ_IOUT_MAX, + PMBUS_VIRT_RESET_IOUT_HISTORY, + PMBUS_VIRT_READ_TEMP2_AVG, + PMBUS_VIRT_READ_TEMP2_MIN, + PMBUS_VIRT_READ_TEMP2_MAX, + PMBUS_VIRT_RESET_TEMP2_HISTORY, + + PMBUS_VIRT_READ_VMON, + PMBUS_VIRT_VMON_UV_WARN_LIMIT, + PMBUS_VIRT_VMON_OV_WARN_LIMIT, + PMBUS_VIRT_VMON_UV_FAULT_LIMIT, + PMBUS_VIRT_VMON_OV_FAULT_LIMIT, + PMBUS_VIRT_STATUS_VMON, + + /* + * RPM and PWM Fan control + * + * Drivers wanting to expose PWM control must define the behaviour of + * PMBUS_VIRT_PWM_[1-4] and PMBUS_VIRT_PWM_ENABLE_[1-4] in the + * {read,write}_word_data callback. + * + * pmbus core provides a default implementation for + * PMBUS_VIRT_FAN_TARGET_[1-4]. + * + * TARGET, PWM and PWM_ENABLE members must be defined sequentially; + * pmbus core uses the difference between the provided register and + * it's _1 counterpart to calculate the FAN/PWM ID. + */ + PMBUS_VIRT_FAN_TARGET_1, + PMBUS_VIRT_FAN_TARGET_2, + PMBUS_VIRT_FAN_TARGET_3, + PMBUS_VIRT_FAN_TARGET_4, + PMBUS_VIRT_PWM_1, + PMBUS_VIRT_PWM_2, + PMBUS_VIRT_PWM_3, + PMBUS_VIRT_PWM_4, + PMBUS_VIRT_PWM_ENABLE_1, + PMBUS_VIRT_PWM_ENABLE_2, + PMBUS_VIRT_PWM_ENABLE_3, + PMBUS_VIRT_PWM_ENABLE_4, + + /* Samples for average + * + * Drivers wanting to expose functionality for changing the number of + * samples used for average values should implement support in + * {read,write}_word_data callback for either PMBUS_VIRT_SAMPLES if it + * applies to all types of measurements, or any number of specific + * PMBUS_VIRT_*_SAMPLES registers to allow for individual control. + */ + PMBUS_VIRT_SAMPLES, + PMBUS_VIRT_IN_SAMPLES, + PMBUS_VIRT_CURR_SAMPLES, + PMBUS_VIRT_POWER_SAMPLES, + PMBUS_VIRT_TEMP_SAMPLES, +}; + +/* + * OPERATION + */ +#define PB_OPERATION_CONTROL_ON BIT(7) + +/* + * WRITE_PROTECT + */ +#define PB_WP_ALL BIT(7) /* all but WRITE_PROTECT */ +#define PB_WP_OP BIT(6) /* all but WP, OPERATION, PAGE */ +#define PB_WP_VOUT BIT(5) /* all but WP, OPERATION, PAGE, VOUT, ON_OFF */ + +#define PB_WP_ANY (PB_WP_ALL | PB_WP_OP | PB_WP_VOUT) + +/* + * CAPABILITY + */ +#define PB_CAPABILITY_SMBALERT BIT(4) +#define PB_CAPABILITY_ERROR_CHECK BIT(7) + +/* + * VOUT_MODE + */ +#define PB_VOUT_MODE_MODE_MASK 0xe0 +#define PB_VOUT_MODE_PARAM_MASK 0x1f + +#define PB_VOUT_MODE_LINEAR 0x00 +#define PB_VOUT_MODE_VID 0x20 +#define PB_VOUT_MODE_DIRECT 0x40 + +/* + * Fan configuration + */ +#define PB_FAN_2_PULSE_MASK (BIT(0) | BIT(1)) +#define PB_FAN_2_RPM BIT(2) +#define PB_FAN_2_INSTALLED BIT(3) +#define PB_FAN_1_PULSE_MASK (BIT(4) | BIT(5)) +#define PB_FAN_1_RPM BIT(6) +#define PB_FAN_1_INSTALLED BIT(7) + +enum pmbus_fan_mode { percent = 0, rpm }; + +/* + * STATUS_BYTE, STATUS_WORD (lower) + */ +#define PB_STATUS_NONE_ABOVE BIT(0) +#define PB_STATUS_CML BIT(1) +#define PB_STATUS_TEMPERATURE BIT(2) +#define PB_STATUS_VIN_UV BIT(3) +#define PB_STATUS_IOUT_OC BIT(4) +#define PB_STATUS_VOUT_OV BIT(5) +#define PB_STATUS_OFF BIT(6) +#define PB_STATUS_BUSY BIT(7) + +/* + * STATUS_WORD (upper) + */ +#define PB_STATUS_UNKNOWN BIT(8) +#define PB_STATUS_OTHER BIT(9) +#define PB_STATUS_FANS BIT(10) +#define PB_STATUS_POWER_GOOD_N BIT(11) +#define PB_STATUS_WORD_MFR BIT(12) +#define PB_STATUS_INPUT BIT(13) +#define PB_STATUS_IOUT_POUT BIT(14) +#define PB_STATUS_VOUT BIT(15) + +/* + * STATUS_IOUT + */ +#define PB_POUT_OP_WARNING BIT(0) +#define PB_POUT_OP_FAULT BIT(1) +#define PB_POWER_LIMITING BIT(2) +#define PB_CURRENT_SHARE_FAULT BIT(3) +#define PB_IOUT_UC_FAULT BIT(4) +#define PB_IOUT_OC_WARNING BIT(5) +#define PB_IOUT_OC_LV_FAULT BIT(6) +#define PB_IOUT_OC_FAULT BIT(7) + +/* + * STATUS_VOUT, STATUS_INPUT + */ +#define PB_VOLTAGE_UV_FAULT BIT(4) +#define PB_VOLTAGE_UV_WARNING BIT(5) +#define PB_VOLTAGE_OV_WARNING BIT(6) +#define PB_VOLTAGE_OV_FAULT BIT(7) + +/* + * STATUS_INPUT + */ +#define PB_PIN_OP_WARNING BIT(0) +#define PB_IIN_OC_WARNING BIT(1) +#define PB_IIN_OC_FAULT BIT(2) + +/* + * STATUS_TEMPERATURE + */ +#define PB_TEMP_UT_FAULT BIT(4) +#define PB_TEMP_UT_WARNING BIT(5) +#define PB_TEMP_OT_WARNING BIT(6) +#define PB_TEMP_OT_FAULT BIT(7) + +/* + * STATUS_FAN + */ +#define PB_FAN_AIRFLOW_WARNING BIT(0) +#define PB_FAN_AIRFLOW_FAULT BIT(1) +#define PB_FAN_FAN2_SPEED_OVERRIDE BIT(2) +#define PB_FAN_FAN1_SPEED_OVERRIDE BIT(3) +#define PB_FAN_FAN2_WARNING BIT(4) +#define PB_FAN_FAN1_WARNING BIT(5) +#define PB_FAN_FAN2_FAULT BIT(6) +#define PB_FAN_FAN1_FAULT BIT(7) + +/* + * CML_FAULT_STATUS + */ +#define PB_CML_FAULT_OTHER_MEM_LOGIC BIT(0) +#define PB_CML_FAULT_OTHER_COMM BIT(1) +#define PB_CML_FAULT_PROCESSOR BIT(3) +#define PB_CML_FAULT_MEMORY BIT(4) +#define PB_CML_FAULT_PACKET_ERROR BIT(5) +#define PB_CML_FAULT_INVALID_DATA BIT(6) +#define PB_CML_FAULT_INVALID_COMMAND BIT(7) + +enum pmbus_sensor_classes { + PSC_VOLTAGE_IN = 0, + PSC_VOLTAGE_OUT, + PSC_CURRENT_IN, + PSC_CURRENT_OUT, + PSC_POWER, + PSC_TEMPERATURE, + PSC_FAN, + PSC_PWM, + PSC_NUM_CLASSES /* Number of power sensor classes */ +}; + +#define PMBUS_PAGES 32 /* Per PMBus specification */ +#define PMBUS_PHASES 8 /* Maximum number of phases per page */ + +/* Functionality bit mask */ +#define PMBUS_HAVE_VIN BIT(0) +#define PMBUS_HAVE_VCAP BIT(1) +#define PMBUS_HAVE_VOUT BIT(2) +#define PMBUS_HAVE_IIN BIT(3) +#define PMBUS_HAVE_IOUT BIT(4) +#define PMBUS_HAVE_PIN BIT(5) +#define PMBUS_HAVE_POUT BIT(6) +#define PMBUS_HAVE_FAN12 BIT(7) +#define PMBUS_HAVE_FAN34 BIT(8) +#define PMBUS_HAVE_TEMP BIT(9) +#define PMBUS_HAVE_TEMP2 BIT(10) +#define PMBUS_HAVE_TEMP3 BIT(11) +#define PMBUS_HAVE_STATUS_VOUT BIT(12) +#define PMBUS_HAVE_STATUS_IOUT BIT(13) +#define PMBUS_HAVE_STATUS_INPUT BIT(14) +#define PMBUS_HAVE_STATUS_TEMP BIT(15) +#define PMBUS_HAVE_STATUS_FAN12 BIT(16) +#define PMBUS_HAVE_STATUS_FAN34 BIT(17) +#define PMBUS_HAVE_VMON BIT(18) +#define PMBUS_HAVE_STATUS_VMON BIT(19) +#define PMBUS_HAVE_PWM12 BIT(20) +#define PMBUS_HAVE_PWM34 BIT(21) +#define PMBUS_HAVE_SAMPLES BIT(22) + +#define PMBUS_PHASE_VIRTUAL BIT(30) /* Phases on this page are virtual */ +#define PMBUS_PAGE_VIRTUAL BIT(31) /* Page is virtual */ + +enum pmbus_data_format { linear = 0, direct, vid }; +enum vrm_version { vr11 = 0, vr12, vr13, imvp9, amd625mv }; + +struct pmbus_driver_info { + int pages; /* Total number of pages */ + u8 phases[PMBUS_PAGES]; /* Number of phases per page */ + enum pmbus_data_format format[PSC_NUM_CLASSES]; + enum vrm_version vrm_version[PMBUS_PAGES]; /* vrm version per page */ + /* + * Support one set of coefficients for each sensor type + * Used for chips providing data in direct mode. + */ + int m[PSC_NUM_CLASSES]; /* mantissa for direct data format */ + int b[PSC_NUM_CLASSES]; /* offset */ + int R[PSC_NUM_CLASSES]; /* exponent */ + + u32 func[PMBUS_PAGES]; /* Functionality, per page */ + u32 pfunc[PMBUS_PHASES];/* Functionality, per phase */ + /* + * The following functions map manufacturing specific register values + * to PMBus standard register values. Specify only if mapping is + * necessary. + * Functions return the register value (read) or zero (write) if + * successful. A return value of -ENODATA indicates that there is no + * manufacturer specific register, but that a standard PMBus register + * may exist. Any other negative return value indicates that the + * register does not exist, and that no attempt should be made to read + * the standard register. + */ + int (*read_byte_data)(struct i2c_client *client, int page, int reg); + int (*read_word_data)(struct i2c_client *client, int page, int phase, + int reg); + int (*write_word_data)(struct i2c_client *client, int page, int reg, + u16 word); + int (*write_byte)(struct i2c_client *client, int page, u8 value); + /* + * The identify function determines supported PMBus functionality. + * This function is only necessary if a chip driver supports multiple + * chips, and the chip functionality is not pre-determined. + */ + int (*identify)(struct i2c_client *client, + struct pmbus_driver_info *info); + + /* Regulator functionality, if supported by this chip driver. */ + int num_regulators; + const struct regulator_desc *reg_desc; + + /* custom attributes */ + const struct attribute_group **groups; +}; + +/* Regulator ops */ + +extern const struct regulator_ops wb_pmbus_regulator_ops; + +/* Macro for filling in array of struct regulator_desc */ +#define PMBUS_REGULATOR(_name, _id) \ + [_id] = { \ + .name = (_name # _id), \ + .id = (_id), \ + .of_match = of_match_ptr(_name # _id), \ + .regulators_node = of_match_ptr("regulators"), \ + .ops = &wb_pmbus_regulator_ops, \ + .type = REGULATOR_VOLTAGE, \ + .owner = THIS_MODULE, \ + } + +struct pmbus_data { + struct device *dev; + struct device *hwmon_dev; + + u32 flags; /* from platform data */ + + int exponent[PMBUS_PAGES]; /* linear mode: exponent for output voltages */ + + const struct pmbus_driver_info *info; + + int max_attributes; + int num_attributes; + struct attribute_group group; + const struct attribute_group **groups; + struct dentry *debugfs; /* debugfs device directory */ + + struct pmbus_sensor *sensors; + + struct mutex update_lock; + + bool has_status_word; /* device uses STATUS_WORD register */ + int (*read_status)(struct i2c_client *client, int page); + + s16 currpage; /* current page, -1 for unknown/unset */ + s16 currphase; /* current phase, 0xff for all, -1 for unknown/unset */ + int vout_max[PMBUS_PAGES]; /* pmbus maximum output voltage */ + int vout_min[PMBUS_PAGES]; /* pmbus minimum output voltage */ +}; + +/* Function declarations */ +void wb_pmbus_clear_cache(struct i2c_client *client); +int wb_pmbus_set_page(struct i2c_client *client, int page, int phase); +int wb_pmbus_read_word_data(struct i2c_client *client, int page, int phase, + u8 reg); +int wb_pmbus_write_word_data(struct i2c_client *client, int page, u8 reg, + u16 word); +int wb_pmbus_read_byte_data(struct i2c_client *client, int page, u8 reg); +int wb_pmbus_write_byte(struct i2c_client *client, int page, u8 value); +int wb_pmbus_write_byte_data(struct i2c_client *client, int page, u8 reg, + u8 value); +int wb_pmbus_update_byte_data(struct i2c_client *client, int page, u8 reg, + u8 mask, u8 value); +void wb_pmbus_clear_faults(struct i2c_client *client); +bool wb_pmbus_check_byte_register(struct i2c_client *client, int page, int reg); +bool wb_pmbus_check_word_register(struct i2c_client *client, int page, int reg); +int wb_pmbus_do_probe(struct i2c_client *client, struct pmbus_driver_info *info); +int wb_pmbus_do_remove(struct i2c_client *client); +const struct pmbus_driver_info *wb_pmbus_get_driver_info(struct i2c_client + *client); +int wb_pmbus_get_fan_rate_device(struct i2c_client *client, int page, int id, + enum pmbus_fan_mode mode); +int wb_pmbus_get_fan_rate_cached(struct i2c_client *client, int page, int id, + enum pmbus_fan_mode mode); +int wb_pmbus_update_fan(struct i2c_client *client, int page, int id, + u8 config, u8 mask, u16 command); +struct dentry *wb_pmbus_get_debugfs_dir(struct i2c_client *client); + +#endif /* WB_PMBUS_H */ diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_pmbus_core.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_pmbus_core.c new file mode 100644 index 000000000000..bba6ca39cd3c --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_pmbus_core.c @@ -0,0 +1,2780 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Hardware monitoring driver for PMBus devices + * + * Copyright (c) 2010, 2011 Ericsson AB. + * Copyright (c) 2012 Guenter Roeck + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "wb_pmbus.h" + +/* + * Number of additional attribute pointers to allocate + * with each call to krealloc + */ +#define PMBUS_ATTR_ALLOC_SIZE (32) +#define PMBUS_NAME_SIZE (24) +#define PMBUS_RETRY_SLEEP_TIME (10000) /* 10ms */ +#define PMBUS_RETRY_TIME (3) + +struct pmbus_sensor { + struct pmbus_sensor *next; + char name[PMBUS_NAME_SIZE]; /* sysfs sensor name */ + struct device_attribute attribute; + u8 page; /* page number */ + u8 phase; /* phase number, 0xff for all phases */ + u16 reg; /* register */ + enum pmbus_sensor_classes class; /* sensor class */ + bool update; /* runtime sensor update needed */ + bool convert; /* Whether or not to apply linear/vid/direct */ + int data; /* Sensor data. + Negative if there was a read error */ +}; +#define to_pmbus_sensor(_attr) \ + container_of(_attr, struct pmbus_sensor, attribute) + +struct pmbus_boolean { + char name[PMBUS_NAME_SIZE]; /* sysfs boolean name */ + struct sensor_device_attribute attribute; + struct pmbus_sensor *s1; + struct pmbus_sensor *s2; +}; +#define to_pmbus_boolean(_attr) \ + container_of(_attr, struct pmbus_boolean, attribute) + +struct pmbus_label { + char name[PMBUS_NAME_SIZE]; /* sysfs label name */ + struct device_attribute attribute; + char label[PMBUS_NAME_SIZE]; /* label */ +}; +#define to_pmbus_label(_attr) \ + container_of(_attr, struct pmbus_label, attribute) + +/* Macros for converting between sensor index and register/page/status mask */ + +#define PB_STATUS_MASK 0xffff +#define PB_REG_SHIFT 16 +#define PB_REG_MASK 0x3ff +#define PB_PAGE_SHIFT 26 +#define PB_PAGE_MASK 0x3f + +#define pb_reg_to_index(page, reg, mask) (((page) << PB_PAGE_SHIFT) | \ + ((reg) << PB_REG_SHIFT) | (mask)) + +#define pb_index_to_page(index) (((index) >> PB_PAGE_SHIFT) & PB_PAGE_MASK) +#define pb_index_to_reg(index) (((index) >> PB_REG_SHIFT) & PB_REG_MASK) +#define pb_index_to_mask(index) ((index) & PB_STATUS_MASK) + +struct pmbus_debugfs_entry { + struct i2c_client *client; + u8 page; + u8 reg; +}; + +static const int pmbus_fan_rpm_mask[] = { + PB_FAN_1_RPM, + PB_FAN_2_RPM, + PB_FAN_1_RPM, + PB_FAN_2_RPM, +}; + +static const int pmbus_fan_config_registers[] = { + PMBUS_FAN_CONFIG_12, + PMBUS_FAN_CONFIG_12, + PMBUS_FAN_CONFIG_34, + PMBUS_FAN_CONFIG_34 +}; + +static const int pmbus_fan_command_registers[] = { + PMBUS_FAN_COMMAND_1, + PMBUS_FAN_COMMAND_2, + PMBUS_FAN_COMMAND_3, + PMBUS_FAN_COMMAND_4, +}; + +void wb_pmbus_clear_cache(struct i2c_client *client) +{ + struct pmbus_data *data = i2c_get_clientdata(client); + struct pmbus_sensor *sensor; + + for (sensor = data->sensors; sensor; sensor = sensor->next) + sensor->data = -ENODATA; +} +EXPORT_SYMBOL_GPL(wb_pmbus_clear_cache); + +static int wb_pmbus_set_page_tmp(struct i2c_client *client, int page, int phase) +{ + struct pmbus_data *data = i2c_get_clientdata(client); + int rv; + + if (page < 0) + return 0; + + if (!(data->info->func[page] & PMBUS_PAGE_VIRTUAL) && + data->info->pages > 1 && page != data->currpage) { + rv = i2c_smbus_write_byte_data(client, PMBUS_PAGE, page); + if (rv < 0) + return rv; + + rv = i2c_smbus_read_byte_data(client, PMBUS_PAGE); + if (rv < 0) + return rv; + + if (rv != page) + return -EIO; + } + data->currpage = page; + + if (data->info->phases[page] && data->currphase != phase && + !(data->info->func[page] & PMBUS_PHASE_VIRTUAL)) { + rv = i2c_smbus_write_byte_data(client, PMBUS_PHASE, + phase); + if (rv) + return rv; + } + data->currphase = phase; + + return 0; +} + +int wb_pmbus_set_page(struct i2c_client *client, int page, int phase) +{ + int rv, i; + struct device *dev = &client->dev; + + for (i = 0; i < PMBUS_RETRY_TIME; i++) { + rv = wb_pmbus_set_page_tmp(client, page, phase); + if(rv >= 0){ + return rv; + } + if ((i + 1) < PMBUS_RETRY_TIME) { + usleep_range(PMBUS_RETRY_SLEEP_TIME, PMBUS_RETRY_SLEEP_TIME + 1); + } + } + dev_dbg(dev, "wb_pmbus_set_page failed, page=%d, phase=%d, rv=%d\n", + page, phase, rv); + return rv; +} +EXPORT_SYMBOL_GPL(wb_pmbus_set_page); + +static int wb_pmbus_write_byte_tmp(struct i2c_client *client, int page, u8 value) +{ + int rv; + + rv = wb_pmbus_set_page(client, page, 0xff); + if (rv < 0) + return rv; + + return i2c_smbus_write_byte(client, value); +} + +int wb_pmbus_write_byte(struct i2c_client *client, int page, u8 value) +{ + int rv, i; + struct device *dev = &client->dev; + + for (i = 0; i < PMBUS_RETRY_TIME; i++) { + rv = wb_pmbus_write_byte_tmp(client, page, value); + if(rv >= 0){ + return rv; + } + if ((i + 1) < PMBUS_RETRY_TIME) { + usleep_range(PMBUS_RETRY_SLEEP_TIME, PMBUS_RETRY_SLEEP_TIME + 1); + } + } + dev_dbg(dev, "wb_pmbus_write_byte failed, page=%d, value=0x%x, rv: %d\n", + page, value, rv); + return rv; +} + +EXPORT_SYMBOL_GPL(wb_pmbus_write_byte); + +/* + * _pmbus_write_byte() is similar to pmbus_write_byte(), but checks if + * a device specific mapping function exists and calls it if necessary. + */ +static int _pmbus_write_byte(struct i2c_client *client, int page, u8 value) +{ + struct pmbus_data *data = i2c_get_clientdata(client); + const struct pmbus_driver_info *info = data->info; + int status; + + if (info->write_byte) { + status = info->write_byte(client, page, value); + if (status != -ENODATA) + return status; + } + return wb_pmbus_write_byte(client, page, value); +} + +static int wb_pmbus_write_word_data_tmp(struct i2c_client *client, int page, u8 reg, + u16 word) +{ + int rv; + + rv = wb_pmbus_set_page(client, page, 0xff); + if (rv < 0) + return rv; + + return i2c_smbus_write_word_data(client, reg, word); +} + +int wb_pmbus_write_word_data(struct i2c_client *client, int page, u8 reg, + u16 word) +{ + int rv, i; + struct device *dev = &client->dev; + + for (i = 0; i < PMBUS_RETRY_TIME; i++) { + rv = wb_pmbus_write_word_data_tmp(client, page, reg, word); + if(rv >= 0){ + return rv; + } + if ((i + 1) < PMBUS_RETRY_TIME) { + usleep_range(PMBUS_RETRY_SLEEP_TIME, PMBUS_RETRY_SLEEP_TIME + 1); + } + } + dev_dbg(dev, "wb_pmbus_write_word_data failed, page: %d, reg: 0x%x, value: 0x%x, rv: %d\n", + page, reg, word, rv); + return rv; + +} +EXPORT_SYMBOL_GPL(wb_pmbus_write_word_data); + +static int pmbus_write_virt_reg(struct i2c_client *client, int page, int reg, + u16 word) +{ + int bit; + int id; + int rv; + + switch (reg) { + case PMBUS_VIRT_FAN_TARGET_1 ... PMBUS_VIRT_FAN_TARGET_4: + id = reg - PMBUS_VIRT_FAN_TARGET_1; + bit = pmbus_fan_rpm_mask[id]; + rv = wb_pmbus_update_fan(client, page, id, bit, bit, word); + break; + default: + rv = -ENXIO; + break; + } + + return rv; +} + +/* + * _pmbus_write_word_data() is similar to pmbus_write_word_data(), but checks if + * a device specific mapping function exists and calls it if necessary. + */ +static int _pmbus_write_word_data(struct i2c_client *client, int page, int reg, + u16 word) +{ + struct pmbus_data *data = i2c_get_clientdata(client); + const struct pmbus_driver_info *info = data->info; + int status; + + if (info->write_word_data) { + status = info->write_word_data(client, page, reg, word); + if (status != -ENODATA) + return status; + } + + if (reg >= PMBUS_VIRT_BASE) + return pmbus_write_virt_reg(client, page, reg, word); + + return wb_pmbus_write_word_data(client, page, reg, word); +} + +int wb_pmbus_update_fan(struct i2c_client *client, int page, int id, + u8 config, u8 mask, u16 command) +{ + int from; + int rv; + u8 to; + + from = wb_pmbus_read_byte_data(client, page, + pmbus_fan_config_registers[id]); + if (from < 0) + return from; + + to = (from & ~mask) | (config & mask); + if (to != from) { + rv = wb_pmbus_write_byte_data(client, page, + pmbus_fan_config_registers[id], to); + if (rv < 0) + return rv; + } + + return _pmbus_write_word_data(client, page, + pmbus_fan_command_registers[id], command); +} +EXPORT_SYMBOL_GPL(wb_pmbus_update_fan); + +static int wb_pmbus_read_word_data_tmp(struct i2c_client *client, int page, int phase, u8 reg) +{ + int rv; + + rv = wb_pmbus_set_page(client, page, phase); + if (rv < 0) + return rv; + + return i2c_smbus_read_word_data(client, reg); +} + +int wb_pmbus_read_word_data(struct i2c_client *client, int page, int phase, u8 reg) +{ + int rv, i; + struct device *dev = &client->dev; + + for (i = 0; i < PMBUS_RETRY_TIME; i++) { + rv = wb_pmbus_read_word_data_tmp(client, page, phase, reg); + if(rv >= 0){ + return rv; + } + if ((i + 1) < PMBUS_RETRY_TIME) { + usleep_range(PMBUS_RETRY_SLEEP_TIME, PMBUS_RETRY_SLEEP_TIME + 1); + } + } + dev_dbg(dev, "wb_pmbus_read_word_data failed, page: %d, phase: %d, reg: 0x%x, rv: %d\n", + page, phase, reg, rv); + return rv; +} +EXPORT_SYMBOL_GPL(wb_pmbus_read_word_data); + +static int pmbus_read_virt_reg(struct i2c_client *client, int page, int reg) +{ + int rv; + int id; + + switch (reg) { + case PMBUS_VIRT_FAN_TARGET_1 ... PMBUS_VIRT_FAN_TARGET_4: + id = reg - PMBUS_VIRT_FAN_TARGET_1; + rv = wb_pmbus_get_fan_rate_device(client, page, id, rpm); + break; + default: + rv = -ENXIO; + break; + } + + return rv; +} + +/* + * _pmbus_read_word_data() is similar to wb_pmbus_read_word_data(), but checks if + * a device specific mapping function exists and calls it if necessary. + */ +static int _pmbus_read_word_data(struct i2c_client *client, int page, + int phase, int reg) +{ + struct pmbus_data *data = i2c_get_clientdata(client); + const struct pmbus_driver_info *info = data->info; + int status; + + if (info->read_word_data) { + status = info->read_word_data(client, page, phase, reg); + if (status != -ENODATA) + return status; + } + + if (reg >= PMBUS_VIRT_BASE) + return pmbus_read_virt_reg(client, page, reg); + + return wb_pmbus_read_word_data(client, page, phase, reg); +} + +/* Same as above, but without phase parameter, for use in check functions */ +static int __pmbus_read_word_data(struct i2c_client *client, int page, int reg) +{ + return _pmbus_read_word_data(client, page, 0xff, reg); +} + +static int wb_pmbus_read_byte_data_tmp(struct i2c_client *client, int page, u8 reg) +{ + int rv; + + rv = wb_pmbus_set_page(client, page, 0xff); + if (rv < 0) + return rv; + + return i2c_smbus_read_byte_data(client, reg); +} + +int wb_pmbus_read_byte_data(struct i2c_client *client, int page, u8 reg) +{ + int rv, i; + struct device *dev = &client->dev; + + for (i = 0; i < PMBUS_RETRY_TIME; i++) { + rv = wb_pmbus_read_byte_data_tmp(client, page, reg); + if(rv >= 0){ + return rv; + } + if ((i + 1) < PMBUS_RETRY_TIME) { + usleep_range(PMBUS_RETRY_SLEEP_TIME, PMBUS_RETRY_SLEEP_TIME + 1); + } + } + dev_dbg(dev, "wb_pmbus_read_byte_data failed, page: %d, reg: 0x%x, rv: %d\n", + page, reg, rv); + return rv; +} +EXPORT_SYMBOL_GPL(wb_pmbus_read_byte_data); + +static int wb_pmbus_write_byte_data_tmp(struct i2c_client *client, int page, u8 reg, u8 value) +{ + int rv; + + rv = wb_pmbus_set_page(client, page, 0xff); + if (rv < 0) + return rv; + + return i2c_smbus_write_byte_data(client, reg, value); +} + +int wb_pmbus_write_byte_data(struct i2c_client *client, int page, u8 reg, u8 value) +{ + int rv, i; + struct device *dev = &client->dev; + + for (i = 0; i < PMBUS_RETRY_TIME; i++) { + rv = wb_pmbus_write_byte_data_tmp(client, page, reg, value); + if(rv >= 0){ + return rv; + } + if ((i + 1) < PMBUS_RETRY_TIME) { + usleep_range(PMBUS_RETRY_SLEEP_TIME, PMBUS_RETRY_SLEEP_TIME + 1); + } + } + dev_dbg(dev, "wb_pmbus_write_byte_data failed, page: %d, reg: 0x%x, value: 0x%x, rv: %d\n", + page, reg, value, rv); + return rv; +} +EXPORT_SYMBOL_GPL(wb_pmbus_write_byte_data); + +int wb_pmbus_update_byte_data(struct i2c_client *client, int page, u8 reg, + u8 mask, u8 value) +{ + unsigned int tmp; + int rv; + + rv = wb_pmbus_read_byte_data(client, page, reg); + if (rv < 0) + return rv; + + tmp = (rv & ~mask) | (value & mask); + + if (tmp != rv) + rv = wb_pmbus_write_byte_data(client, page, reg, tmp); + + return rv; +} +EXPORT_SYMBOL_GPL(wb_pmbus_update_byte_data); + +/* + * _pmbus_read_byte_data() is similar to wb_pmbus_read_byte_data(), but checks if + * a device specific mapping function exists and calls it if necessary. + */ +static int _pmbus_read_byte_data(struct i2c_client *client, int page, int reg) +{ + struct pmbus_data *data = i2c_get_clientdata(client); + const struct pmbus_driver_info *info = data->info; + int status; + + if (info->read_byte_data) { + status = info->read_byte_data(client, page, reg); + if (status != -ENODATA) + return status; + } + return wb_pmbus_read_byte_data(client, page, reg); +} + +static struct pmbus_sensor *pmbus_find_sensor(struct pmbus_data *data, int page, + int reg) +{ + struct pmbus_sensor *sensor; + + for (sensor = data->sensors; sensor; sensor = sensor->next) { + if (sensor->page == page && sensor->reg == reg) + return sensor; + } + + return ERR_PTR(-EINVAL); +} + +static int pmbus_get_fan_rate(struct i2c_client *client, int page, int id, + enum pmbus_fan_mode mode, + bool from_cache) +{ + struct pmbus_data *data = i2c_get_clientdata(client); + bool want_rpm, have_rpm; + struct pmbus_sensor *s; + int config; + int reg; + + want_rpm = (mode == rpm); + + if (from_cache) { + reg = want_rpm ? PMBUS_VIRT_FAN_TARGET_1 : PMBUS_VIRT_PWM_1; + s = pmbus_find_sensor(data, page, reg + id); + if (IS_ERR(s)) + return PTR_ERR(s); + + return s->data; + } + + config = wb_pmbus_read_byte_data(client, page, + pmbus_fan_config_registers[id]); + if (config < 0) + return config; + + have_rpm = !!(config & pmbus_fan_rpm_mask[id]); + if (want_rpm == have_rpm) + return wb_pmbus_read_word_data(client, page, 0xff, + pmbus_fan_command_registers[id]); + + /* Can't sensibly map between RPM and PWM, just return zero */ + return 0; +} + +int wb_pmbus_get_fan_rate_device(struct i2c_client *client, int page, int id, + enum pmbus_fan_mode mode) +{ + return pmbus_get_fan_rate(client, page, id, mode, false); +} +EXPORT_SYMBOL_GPL(wb_pmbus_get_fan_rate_device); + +int wb_pmbus_get_fan_rate_cached(struct i2c_client *client, int page, int id, + enum pmbus_fan_mode mode) +{ + return pmbus_get_fan_rate(client, page, id, mode, true); +} +EXPORT_SYMBOL_GPL(wb_pmbus_get_fan_rate_cached); + +static void pmbus_clear_fault_page(struct i2c_client *client, int page) +{ + _pmbus_write_byte(client, page, PMBUS_CLEAR_FAULTS); +} + +void wb_pmbus_clear_faults(struct i2c_client *client) +{ + struct pmbus_data *data = i2c_get_clientdata(client); + int i; + + for (i = 0; i < data->info->pages; i++) + pmbus_clear_fault_page(client, i); +} +EXPORT_SYMBOL_GPL(wb_pmbus_clear_faults); + +static int pmbus_check_status_cml(struct i2c_client *client) +{ + struct pmbus_data *data = i2c_get_clientdata(client); + int status, status2; + + status = data->read_status(client, -1); + if (status < 0 || (status & PB_STATUS_CML)) { + status2 = _pmbus_read_byte_data(client, -1, PMBUS_STATUS_CML); + if (status2 < 0 || (status2 & PB_CML_FAULT_INVALID_COMMAND)) + return -EIO; + } + return 0; +} + +static bool pmbus_check_register(struct i2c_client *client, + int (*func)(struct i2c_client *client, + int page, int reg), + int page, int reg) +{ + int rv; + struct pmbus_data *data = i2c_get_clientdata(client); + + rv = func(client, page, reg); + if (rv >= 0 && !(data->flags & PMBUS_SKIP_STATUS_CHECK)) + rv = pmbus_check_status_cml(client); + pmbus_clear_fault_page(client, -1); + return rv >= 0; +} + +static bool pmbus_check_status_register(struct i2c_client *client, int page) +{ + int status; + struct pmbus_data *data = i2c_get_clientdata(client); + + status = data->read_status(client, page); + if (status >= 0 && !(data->flags & PMBUS_SKIP_STATUS_CHECK) && + (status & PB_STATUS_CML)) { + status = _pmbus_read_byte_data(client, -1, PMBUS_STATUS_CML); + if (status < 0 || (status & PB_CML_FAULT_INVALID_COMMAND)) + status = -EIO; + } + + pmbus_clear_fault_page(client, -1); + return status >= 0; +} + +bool wb_pmbus_check_byte_register(struct i2c_client *client, int page, int reg) +{ + return pmbus_check_register(client, _pmbus_read_byte_data, page, reg); +} +EXPORT_SYMBOL_GPL(wb_pmbus_check_byte_register); + +bool wb_pmbus_check_word_register(struct i2c_client *client, int page, int reg) +{ + return pmbus_check_register(client, __pmbus_read_word_data, page, reg); +} +EXPORT_SYMBOL_GPL(wb_pmbus_check_word_register); + +const struct pmbus_driver_info *wb_pmbus_get_driver_info(struct i2c_client *client) +{ + struct pmbus_data *data = i2c_get_clientdata(client); + + return data->info; +} +EXPORT_SYMBOL_GPL(wb_pmbus_get_driver_info); + +static int pmbus_read_status_byte(struct i2c_client *client, int page) +{ + return _pmbus_read_byte_data(client, page, PMBUS_STATUS_BYTE); +} + +static int pmbus_read_status_word(struct i2c_client *client, int page) +{ + return _pmbus_read_word_data(client, page, 0xff, PMBUS_STATUS_WORD); +} + +static int pmbus_get_status(struct i2c_client *client, int page, int reg) +{ + struct pmbus_data *data = i2c_get_clientdata(client); + int status; + + switch (reg) { + case PMBUS_STATUS_WORD: + status = data->read_status(client, page); + if ((status < 0) || (data->has_status_word && (status == 0xffff)) + || (!data->has_status_word && (status == 0xff))) { + if (data->has_status_word) { + data->read_status = pmbus_read_status_byte; + } else { + data->read_status = pmbus_read_status_word; + } + data->has_status_word = !data->has_status_word; + status = data->read_status(client, page); + } + break; + default: + status = _pmbus_read_byte_data(client, page, reg); + break; + } + if (status < 0) + wb_pmbus_clear_faults(client); + return status; +} + +static void pmbus_update_sensor_data(struct i2c_client *client, struct pmbus_sensor *sensor) +{ + if (sensor->data < 0 || sensor->update) + sensor->data = _pmbus_read_word_data(client, sensor->page, + sensor->phase, sensor->reg); +} + +/* + * Convert linear sensor values to milli- or micro-units + * depending on sensor type. + */ +static s64 pmbus_reg2data_linear(struct pmbus_data *data, + struct pmbus_sensor *sensor) +{ + s16 exponent; + s32 mantissa; + s64 val; + + if (sensor->class == PSC_VOLTAGE_OUT) { /* LINEAR16 */ + exponent = data->exponent[sensor->page]; + mantissa = (u16) sensor->data; + } else { /* LINEAR11 */ + exponent = ((s16)sensor->data) >> 11; + mantissa = ((s16)((sensor->data & 0x7ff) << 5)) >> 5; + } + + val = mantissa; + + /* scale result to milli-units for all sensors except fans */ + if (sensor->class != PSC_FAN) + val = val * 1000LL; + + /* scale result to micro-units for power sensors */ + if (sensor->class == PSC_POWER) + val = val * 1000LL; + + if (exponent >= 0) + val <<= exponent; + else + val >>= -exponent; + + return val; +} + +/* + * Convert direct sensor values to milli- or micro-units + * depending on sensor type. + */ +static s64 pmbus_reg2data_direct(struct pmbus_data *data, + struct pmbus_sensor *sensor) +{ + s64 b, val = (s16)sensor->data; + s32 m, R; + + m = data->info->m[sensor->class]; + b = data->info->b[sensor->class]; + R = data->info->R[sensor->class]; + + if (m == 0) + return 0; + + /* X = 1/m * (Y * 10^-R - b) */ + R = -R; + /* scale result to milli-units for everything but fans */ + if (!(sensor->class == PSC_FAN || sensor->class == PSC_PWM)) { + R += 3; + b *= 1000; + } + + /* scale result to micro-units for power sensors */ + if (sensor->class == PSC_POWER) { + R += 3; + b *= 1000; + } + + while (R > 0) { + val *= 10; + R--; + } + while (R < 0) { + val = div_s64(val + 5LL, 10L); /* round closest */ + R++; + } + + val = div_s64(val - b, m); + return val; +} + +/* + * Convert VID sensor values to milli- or micro-units + * depending on sensor type. + */ +static s64 pmbus_reg2data_vid(struct pmbus_data *data, + struct pmbus_sensor *sensor) +{ + long val = sensor->data; + long rv = 0; + + switch (data->info->vrm_version[sensor->page]) { + case vr11: + if (val >= 0x02 && val <= 0xb2) + rv = DIV_ROUND_CLOSEST(160000 - (val - 2) * 625, 100); + break; + case vr12: + if (val >= 0x01) + rv = 250 + (val - 1) * 5; + break; + case vr13: + if (val >= 0x01) + rv = 500 + (val - 1) * 10; + break; + case imvp9: + if (val >= 0x01) + rv = 200 + (val - 1) * 10; + break; + case amd625mv: + if (val >= 0x0 && val <= 0xd8) + rv = DIV_ROUND_CLOSEST(155000 - val * 625, 100); + break; + } + return rv; +} + +static s64 pmbus_reg2data(struct pmbus_data *data, struct pmbus_sensor *sensor) +{ + s64 val; + + if (!sensor->convert) + return sensor->data; + + switch (data->info->format[sensor->class]) { + case direct: + val = pmbus_reg2data_direct(data, sensor); + break; + case vid: + val = pmbus_reg2data_vid(data, sensor); + break; + case linear: + default: + val = pmbus_reg2data_linear(data, sensor); + break; + } + return val; +} + +#define MAX_MANTISSA (1023 * 1000) +#define MIN_MANTISSA (511 * 1000) + +static u16 pmbus_data2reg_linear(struct pmbus_data *data, + struct pmbus_sensor *sensor, s64 val) +{ + s16 exponent = 0, mantissa; + bool negative = false; + + /* simple case */ + if (val == 0) + return 0; + + if (sensor->class == PSC_VOLTAGE_OUT) { + /* LINEAR16 does not support negative voltages */ + if (val < 0) + return 0; + + /* + * For a static exponents, we don't have a choice + * but to adjust the value to it. + */ + if (data->exponent[sensor->page] < 0) + val <<= -data->exponent[sensor->page]; + else + val >>= data->exponent[sensor->page]; + val = DIV_ROUND_CLOSEST_ULL(val, 1000); + return clamp_val(val, 0, 0xffff); + } + + if (val < 0) { + negative = true; + val = -val; + } + + /* Power is in uW. Convert to mW before converting. */ + if (sensor->class == PSC_POWER) + val = DIV_ROUND_CLOSEST_ULL(val, 1000); + + /* + * For simplicity, convert fan data to milli-units + * before calculating the exponent. + */ + if (sensor->class == PSC_FAN) + val = val * 1000LL; + + /* Reduce large mantissa until it fits into 10 bit */ + while (val >= MAX_MANTISSA && exponent < 15) { + exponent++; + val >>= 1; + } + /* Increase small mantissa to improve precision */ + while (val < MIN_MANTISSA && exponent > -15) { + exponent--; + val <<= 1; + } + + /* Convert mantissa from milli-units to units */ + mantissa = clamp_val(DIV_ROUND_CLOSEST_ULL(val, 1000), 0, 0x3ff); + + /* restore sign */ + if (negative) + mantissa = -mantissa; + + /* Convert to 5 bit exponent, 11 bit mantissa */ + return (mantissa & 0x7ff) | ((exponent << 11) & 0xf800); +} + +static u16 pmbus_data2reg_direct(struct pmbus_data *data, + struct pmbus_sensor *sensor, s64 val) +{ + s64 b; + s32 m, R; + + m = data->info->m[sensor->class]; + b = data->info->b[sensor->class]; + R = data->info->R[sensor->class]; + + /* Power is in uW. Adjust R and b. */ + if (sensor->class == PSC_POWER) { + R -= 3; + b *= 1000; + } + + /* Calculate Y = (m * X + b) * 10^R */ + if (!(sensor->class == PSC_FAN || sensor->class == PSC_PWM)) { + R -= 3; /* Adjust R and b for data in milli-units */ + b *= 1000; + } + val = val * m + b; + + while (R > 0) { + val *= 10; + R--; + } + while (R < 0) { + val = div_s64(val + 5LL, 10L); /* round closest */ + R++; + } + + return (u16)clamp_val(val, S16_MIN, S16_MAX); +} + +static u16 pmbus_data2reg_vid(struct pmbus_data *data, + struct pmbus_sensor *sensor, s64 val) +{ + val = clamp_val(val, 500, 1600); + + return 2 + DIV_ROUND_CLOSEST_ULL((1600LL - val) * 100LL, 625); +} + +static u16 pmbus_data2reg(struct pmbus_data *data, + struct pmbus_sensor *sensor, s64 val) +{ + u16 regval; + + if (!sensor->convert) + return val; + + switch (data->info->format[sensor->class]) { + case direct: + regval = pmbus_data2reg_direct(data, sensor, val); + break; + case vid: + regval = pmbus_data2reg_vid(data, sensor, val); + break; + case linear: + default: + regval = pmbus_data2reg_linear(data, sensor, val); + break; + } + return regval; +} + +/* + * Return boolean calculated from converted data. + * defines a status register index and mask. + * The mask is in the lower 8 bits, the register index is in bits 8..23. + * + * The associated pmbus_boolean structure contains optional pointers to two + * sensor attributes. If specified, those attributes are compared against each + * other to determine if a limit has been exceeded. + * + * If the sensor attribute pointers are NULL, the function returns true if + * (status[reg] & mask) is true. + * + * If sensor attribute pointers are provided, a comparison against a specified + * limit has to be performed to determine the boolean result. + * In this case, the function returns true if v1 >= v2 (where v1 and v2 are + * sensor values referenced by sensor attribute pointers s1 and s2). + * + * To determine if an object exceeds upper limits, specify = . + * To determine if an object exceeds lower limits, specify = . + * + * If a negative value is stored in any of the referenced registers, this value + * reflects an error code which will be returned. + */ +static int pmbus_get_boolean(struct i2c_client *client, struct pmbus_boolean *b, + int index) +{ + struct pmbus_data *data = i2c_get_clientdata(client); + struct pmbus_sensor *s1 = b->s1; + struct pmbus_sensor *s2 = b->s2; + u16 mask = pb_index_to_mask(index); + u8 page = pb_index_to_page(index); + u16 reg = pb_index_to_reg(index); + int ret, status; + u16 regval; + + mutex_lock(&data->update_lock); + status = pmbus_get_status(client, page, reg); + if (status < 0) { + ret = status; + goto unlock; + } + + if (s1) + pmbus_update_sensor_data(client, s1); + if (s2) + pmbus_update_sensor_data(client, s2); + + regval = status & mask; + if (s1 && s2) { + s64 v1, v2; + + if (s1->data < 0) { + ret = s1->data; + goto unlock; + } + if (s2->data < 0) { + ret = s2->data; + goto unlock; + } + + v1 = pmbus_reg2data(data, s1); + v2 = pmbus_reg2data(data, s2); + ret = !!(regval && v1 >= v2); + } else { + ret = !!regval; + } +unlock: + mutex_unlock(&data->update_lock); + return ret; +} + +static ssize_t pmbus_show_boolean(struct device *dev, + struct device_attribute *da, char *buf) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + struct pmbus_boolean *boolean = to_pmbus_boolean(attr); + struct i2c_client *client = to_i2c_client(dev->parent); + int val; + + val = pmbus_get_boolean(client, boolean, attr->index); + if (val < 0) + return val; + return snprintf(buf, PAGE_SIZE, "%d\n", val); +} + +static ssize_t pmbus_show_sensor(struct device *dev, + struct device_attribute *devattr, char *buf) +{ + struct i2c_client *client = to_i2c_client(dev->parent); + struct pmbus_sensor *sensor = to_pmbus_sensor(devattr); + struct pmbus_data *data = i2c_get_clientdata(client); + ssize_t ret; + + mutex_lock(&data->update_lock); + pmbus_update_sensor_data(client, sensor); + if (sensor->data < 0) + ret = sensor->data; + else + ret = snprintf(buf, PAGE_SIZE, "%lld\n", pmbus_reg2data(data, sensor)); + mutex_unlock(&data->update_lock); + return ret; +} + +static ssize_t pmbus_set_sensor(struct device *dev, + struct device_attribute *devattr, + const char *buf, size_t count) +{ + struct i2c_client *client = to_i2c_client(dev->parent); + struct pmbus_data *data = i2c_get_clientdata(client); + struct pmbus_sensor *sensor = to_pmbus_sensor(devattr); + ssize_t rv = count; + s64 val; + int ret; + u16 regval; + + if (kstrtos64(buf, 10, &val) < 0) + return -EINVAL; + + mutex_lock(&data->update_lock); + regval = pmbus_data2reg(data, sensor, val); + ret = _pmbus_write_word_data(client, sensor->page, sensor->reg, regval); + if (ret < 0) + rv = ret; + else + sensor->data = regval; + mutex_unlock(&data->update_lock); + return rv; +} + +static ssize_t pmbus_show_label(struct device *dev, + struct device_attribute *da, char *buf) +{ + struct pmbus_label *label = to_pmbus_label(da); + + return snprintf(buf, PAGE_SIZE, "%s\n", label->label); +} + +static int pmbus_add_attribute(struct pmbus_data *data, struct attribute *attr) +{ + if (data->num_attributes >= data->max_attributes - 1) { + int new_max_attrs = data->max_attributes + PMBUS_ATTR_ALLOC_SIZE; + void *new_attrs = devm_krealloc(data->dev, data->group.attrs, + new_max_attrs * sizeof(void *), + GFP_KERNEL); + if (!new_attrs) + return -ENOMEM; + data->group.attrs = new_attrs; + data->max_attributes = new_max_attrs; + } + + data->group.attrs[data->num_attributes++] = attr; + data->group.attrs[data->num_attributes] = NULL; + return 0; +} + +static void pmbus_dev_attr_init(struct device_attribute *dev_attr, + const char *name, + umode_t mode, + ssize_t (*show)(struct device *dev, + struct device_attribute *attr, + char *buf), + ssize_t (*store)(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count)) +{ + sysfs_attr_init(&dev_attr->attr); + dev_attr->attr.name = name; + dev_attr->attr.mode = mode; + dev_attr->show = show; + dev_attr->store = store; +} + +static void pmbus_attr_init(struct sensor_device_attribute *a, + const char *name, + umode_t mode, + ssize_t (*show)(struct device *dev, + struct device_attribute *attr, + char *buf), + ssize_t (*store)(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count), + int idx) +{ + pmbus_dev_attr_init(&a->dev_attr, name, mode, show, store); + a->index = idx; +} + +static int pmbus_add_boolean(struct pmbus_data *data, + const char *name, const char *type, int seq, + struct pmbus_sensor *s1, + struct pmbus_sensor *s2, + u8 page, u16 reg, u16 mask) +{ + struct pmbus_boolean *boolean; + struct sensor_device_attribute *a; + + if (WARN((s1 && !s2) || (!s1 && s2), "Bad s1/s2 parameters\n")) + return -EINVAL; + + boolean = devm_kzalloc(data->dev, sizeof(*boolean), GFP_KERNEL); + if (!boolean) + return -ENOMEM; + + a = &boolean->attribute; + + snprintf(boolean->name, sizeof(boolean->name), "%s%d_%s", + name, seq, type); + boolean->s1 = s1; + boolean->s2 = s2; + pmbus_attr_init(a, boolean->name, 0444, pmbus_show_boolean, NULL, + pb_reg_to_index(page, reg, mask)); + + return pmbus_add_attribute(data, &a->dev_attr.attr); +} + +static struct pmbus_sensor *pmbus_add_sensor(struct pmbus_data *data, + const char *name, const char *type, + int seq, int page, int phase, + int reg, + enum pmbus_sensor_classes class, + bool update, bool readonly, + bool convert) +{ + struct pmbus_sensor *sensor; + struct device_attribute *a; + + sensor = devm_kzalloc(data->dev, sizeof(*sensor), GFP_KERNEL); + if (!sensor) + return NULL; + a = &sensor->attribute; + + if (type) + snprintf(sensor->name, sizeof(sensor->name), "%s%d_%s", + name, seq, type); + else + snprintf(sensor->name, sizeof(sensor->name), "%s%d", + name, seq); + + if (data->flags & PMBUS_WRITE_PROTECTED) + readonly = true; + + sensor->page = page; + sensor->phase = phase; + sensor->reg = reg; + sensor->class = class; + sensor->update = update; + sensor->convert = convert; + sensor->data = -ENODATA; + pmbus_dev_attr_init(a, sensor->name, + readonly ? 0444 : 0644, + pmbus_show_sensor, pmbus_set_sensor); + + if (pmbus_add_attribute(data, &a->attr)) + return NULL; + + sensor->next = data->sensors; + data->sensors = sensor; + + return sensor; +} + +static int pmbus_add_label(struct pmbus_data *data, + const char *name, int seq, + const char *lstring, int index, int phase) +{ + struct pmbus_label *label; + struct device_attribute *a; + + label = devm_kzalloc(data->dev, sizeof(*label), GFP_KERNEL); + if (!label) + return -ENOMEM; + + a = &label->attribute; + + snprintf(label->name, sizeof(label->name), "%s%d_label", name, seq); + if (!index) { + if (phase == 0xff) + strncpy(label->label, lstring, + sizeof(label->label) - 1); + else + snprintf(label->label, sizeof(label->label), "%s.%d", + lstring, phase); + } else { + if (phase == 0xff) + snprintf(label->label, sizeof(label->label), "%s%d", + lstring, index); + else + snprintf(label->label, sizeof(label->label), "%s%d.%d", + lstring, index, phase); + } + + pmbus_dev_attr_init(a, label->name, 0444, pmbus_show_label, NULL); + return pmbus_add_attribute(data, &a->attr); +} + +/* + * Search for attributes. Allocate sensors, booleans, and labels as needed. + */ + +/* + * The pmbus_limit_attr structure describes a single limit attribute + * and its associated alarm attribute. + */ +struct pmbus_limit_attr { + u16 reg; /* Limit register */ + u16 sbit; /* Alarm attribute status bit */ + bool update; /* True if register needs updates */ + bool low; /* True if low limit; for limits with compare + functions only */ + const char *attr; /* Attribute name */ + const char *alarm; /* Alarm attribute name */ +}; + +/* + * The pmbus_sensor_attr structure describes one sensor attribute. This + * description includes a reference to the associated limit attributes. + */ +struct pmbus_sensor_attr { + u16 reg; /* sensor register */ + u16 gbit; /* generic status bit */ + u8 nlimit; /* # of limit registers */ + enum pmbus_sensor_classes class;/* sensor class */ + const char *label; /* sensor label */ + bool paged; /* true if paged sensor */ + bool update; /* true if update needed */ + bool compare; /* true if compare function needed */ + u32 func; /* sensor mask */ + u32 sfunc; /* sensor status mask */ + int sreg; /* status register */ + const struct pmbus_limit_attr *limit;/* limit registers */ +}; + +/* + * Add a set of limit attributes and, if supported, the associated + * alarm attributes. + * returns 0 if no alarm register found, 1 if an alarm register was found, + * < 0 on errors. + */ +static int pmbus_add_limit_attrs(struct i2c_client *client, + struct pmbus_data *data, + const struct pmbus_driver_info *info, + const char *name, int index, int page, + struct pmbus_sensor *base, + const struct pmbus_sensor_attr *attr) +{ + const struct pmbus_limit_attr *l = attr->limit; + int nlimit = attr->nlimit; + int have_alarm = 0; + int i, ret; + struct pmbus_sensor *curr; + + for (i = 0; i < nlimit; i++) { + if (wb_pmbus_check_word_register(client, page, l->reg)) { + curr = pmbus_add_sensor(data, name, l->attr, index, + page, 0xff, l->reg, attr->class, + attr->update || l->update, + false, true); + if (!curr) + return -ENOMEM; + if (l->sbit && (info->func[page] & attr->sfunc)) { + ret = pmbus_add_boolean(data, name, + l->alarm, index, + attr->compare ? l->low ? curr : base + : NULL, + attr->compare ? l->low ? base : curr + : NULL, + page, attr->sreg, l->sbit); + if (ret) + return ret; + have_alarm = 1; + } + } + l++; + } + return have_alarm; +} + +static int pmbus_add_sensor_attrs_one(struct i2c_client *client, + struct pmbus_data *data, + const struct pmbus_driver_info *info, + const char *name, + int index, int page, int phase, + const struct pmbus_sensor_attr *attr, + bool paged) +{ + struct pmbus_sensor *base; + bool upper = !!(attr->gbit & 0xff00); /* need to check STATUS_WORD */ + int ret; + + if (attr->label) { + ret = pmbus_add_label(data, name, index, attr->label, + paged ? page + 1 : 0, phase); + if (ret) + return ret; + } + base = pmbus_add_sensor(data, name, "input", index, page, phase, + attr->reg, attr->class, true, true, true); + if (!base) + return -ENOMEM; + /* No limit and alarm attributes for phase specific sensors */ + if (attr->sfunc && phase == 0xff) { + ret = pmbus_add_limit_attrs(client, data, info, name, + index, page, base, attr); + if (ret < 0) + return ret; + /* + * Add generic alarm attribute only if there are no individual + * alarm attributes, if there is a global alarm bit, and if + * the generic status register (word or byte, depending on + * which global bit is set) for this page is accessible. + */ + if (!ret && attr->gbit && + (!upper || (upper && data->has_status_word)) && + pmbus_check_status_register(client, page)) { + ret = pmbus_add_boolean(data, name, "alarm", index, + NULL, NULL, + page, PMBUS_STATUS_WORD, + attr->gbit); + if (ret) + return ret; + } + } + return 0; +} + +static bool pmbus_sensor_is_paged(const struct pmbus_driver_info *info, + const struct pmbus_sensor_attr *attr) +{ + int p; + + if (attr->paged) + return true; + + /* + * Some attributes may be present on more than one page despite + * not being marked with the paged attribute. If that is the case, + * then treat the sensor as being paged and add the page suffix to the + * attribute name. + * We don't just add the paged attribute to all such attributes, in + * order to maintain the un-suffixed labels in the case where the + * attribute is only on page 0. + */ + for (p = 1; p < info->pages; p++) { + if (info->func[p] & attr->func) + return true; + } + return false; +} + +static int pmbus_add_sensor_attrs(struct i2c_client *client, + struct pmbus_data *data, + const char *name, + const struct pmbus_sensor_attr *attrs, + int nattrs) +{ + const struct pmbus_driver_info *info = data->info; + int index, i; + int ret; + + index = 1; + for (i = 0; i < nattrs; i++) { + int page, pages; + bool paged = pmbus_sensor_is_paged(info, attrs); + + pages = paged ? info->pages : 1; + for (page = 0; page < pages; page++) { + if (!(info->func[page] & attrs->func)) + continue; + ret = pmbus_add_sensor_attrs_one(client, data, info, + name, index, page, + 0xff, attrs, paged); + if (ret) + return ret; + index++; + if (info->phases[page]) { + int phase; + + for (phase = 0; phase < info->phases[page]; + phase++) { + if (!(info->pfunc[phase] & attrs->func)) + continue; + ret = pmbus_add_sensor_attrs_one(client, + data, info, name, index, page, + phase, attrs, paged); + if (ret) + return ret; + index++; + } + } + } + attrs++; + } + return 0; +} + +static const struct pmbus_limit_attr vin_limit_attrs[] = { + { + .reg = PMBUS_VIN_UV_WARN_LIMIT, + .attr = "min", + .alarm = "min_alarm", + .sbit = PB_VOLTAGE_UV_WARNING, + }, { + .reg = PMBUS_VIN_UV_FAULT_LIMIT, + .attr = "lcrit", + .alarm = "lcrit_alarm", + .sbit = PB_VOLTAGE_UV_FAULT, + }, { + .reg = PMBUS_VIN_OV_WARN_LIMIT, + .attr = "max", + .alarm = "max_alarm", + .sbit = PB_VOLTAGE_OV_WARNING, + }, { + .reg = PMBUS_VIN_OV_FAULT_LIMIT, + .attr = "crit", + .alarm = "crit_alarm", + .sbit = PB_VOLTAGE_OV_FAULT, + }, { + .reg = PMBUS_VIRT_READ_VIN_AVG, + .update = true, + .attr = "average", + }, { + .reg = PMBUS_VIRT_READ_VIN_MIN, + .update = true, + .attr = "lowest", + }, { + .reg = PMBUS_VIRT_READ_VIN_MAX, + .update = true, + .attr = "highest", + }, { + .reg = PMBUS_VIRT_RESET_VIN_HISTORY, + .attr = "reset_history", + }, { + .reg = PMBUS_MFR_VIN_MIN, + .attr = "rated_min", + }, { + .reg = PMBUS_MFR_VIN_MAX, + .attr = "rated_max", + }, +}; + +static const struct pmbus_limit_attr vmon_limit_attrs[] = { + { + .reg = PMBUS_VIRT_VMON_UV_WARN_LIMIT, + .attr = "min", + .alarm = "min_alarm", + .sbit = PB_VOLTAGE_UV_WARNING, + }, { + .reg = PMBUS_VIRT_VMON_UV_FAULT_LIMIT, + .attr = "lcrit", + .alarm = "lcrit_alarm", + .sbit = PB_VOLTAGE_UV_FAULT, + }, { + .reg = PMBUS_VIRT_VMON_OV_WARN_LIMIT, + .attr = "max", + .alarm = "max_alarm", + .sbit = PB_VOLTAGE_OV_WARNING, + }, { + .reg = PMBUS_VIRT_VMON_OV_FAULT_LIMIT, + .attr = "crit", + .alarm = "crit_alarm", + .sbit = PB_VOLTAGE_OV_FAULT, + } +}; + +static const struct pmbus_limit_attr vout_limit_attrs[] = { + { + .reg = PMBUS_VOUT_UV_WARN_LIMIT, + .attr = "min", + .alarm = "min_alarm", + .sbit = PB_VOLTAGE_UV_WARNING, + }, { + .reg = PMBUS_VOUT_UV_FAULT_LIMIT, + .attr = "lcrit", + .alarm = "lcrit_alarm", + .sbit = PB_VOLTAGE_UV_FAULT, + }, { + .reg = PMBUS_VOUT_OV_WARN_LIMIT, + .attr = "max", + .alarm = "max_alarm", + .sbit = PB_VOLTAGE_OV_WARNING, + }, { + .reg = PMBUS_VOUT_OV_FAULT_LIMIT, + .attr = "crit", + .alarm = "crit_alarm", + .sbit = PB_VOLTAGE_OV_FAULT, + }, { + .reg = PMBUS_VIRT_READ_VOUT_AVG, + .update = true, + .attr = "average", + }, { + .reg = PMBUS_VIRT_READ_VOUT_MIN, + .update = true, + .attr = "lowest", + }, { + .reg = PMBUS_VIRT_READ_VOUT_MAX, + .update = true, + .attr = "highest", + }, { + .reg = PMBUS_VIRT_RESET_VOUT_HISTORY, + .attr = "reset_history", + }, { + .reg = PMBUS_MFR_VOUT_MIN, + .attr = "rated_min", + }, { + .reg = PMBUS_MFR_VOUT_MAX, + .attr = "rated_max", + }, +}; + +static const struct pmbus_sensor_attr voltage_attributes[] = { + { + .reg = PMBUS_READ_VIN, + .class = PSC_VOLTAGE_IN, + .label = "vin", + .func = PMBUS_HAVE_VIN, + .sfunc = PMBUS_HAVE_STATUS_INPUT, + .sreg = PMBUS_STATUS_INPUT, + .gbit = PB_STATUS_VIN_UV, + .limit = vin_limit_attrs, + .nlimit = ARRAY_SIZE(vin_limit_attrs), + }, { + .reg = PMBUS_VIRT_READ_VMON, + .class = PSC_VOLTAGE_IN, + .label = "vmon", + .func = PMBUS_HAVE_VMON, + .sfunc = PMBUS_HAVE_STATUS_VMON, + .sreg = PMBUS_VIRT_STATUS_VMON, + .limit = vmon_limit_attrs, + .nlimit = ARRAY_SIZE(vmon_limit_attrs), + }, { + .reg = PMBUS_READ_VCAP, + .class = PSC_VOLTAGE_IN, + .label = "vcap", + .func = PMBUS_HAVE_VCAP, + }, { + .reg = PMBUS_READ_VOUT, + .class = PSC_VOLTAGE_OUT, + .label = "vout", + .paged = true, + .func = PMBUS_HAVE_VOUT, + .sfunc = PMBUS_HAVE_STATUS_VOUT, + .sreg = PMBUS_STATUS_VOUT, + .gbit = PB_STATUS_VOUT_OV, + .limit = vout_limit_attrs, + .nlimit = ARRAY_SIZE(vout_limit_attrs), + } +}; + +/* Current attributes */ + +static const struct pmbus_limit_attr iin_limit_attrs[] = { + { + .reg = PMBUS_IIN_OC_WARN_LIMIT, + .attr = "max", + .alarm = "max_alarm", + .sbit = PB_IIN_OC_WARNING, + }, { + .reg = PMBUS_IIN_OC_FAULT_LIMIT, + .attr = "crit", + .alarm = "crit_alarm", + .sbit = PB_IIN_OC_FAULT, + }, { + .reg = PMBUS_VIRT_READ_IIN_AVG, + .update = true, + .attr = "average", + }, { + .reg = PMBUS_VIRT_READ_IIN_MIN, + .update = true, + .attr = "lowest", + }, { + .reg = PMBUS_VIRT_READ_IIN_MAX, + .update = true, + .attr = "highest", + }, { + .reg = PMBUS_VIRT_RESET_IIN_HISTORY, + .attr = "reset_history", + }, { + .reg = PMBUS_MFR_IIN_MAX, + .attr = "rated_max", + }, +}; + +static const struct pmbus_limit_attr iout_limit_attrs[] = { + { + .reg = PMBUS_IOUT_OC_WARN_LIMIT, + .attr = "max", + .alarm = "max_alarm", + .sbit = PB_IOUT_OC_WARNING, + }, { + .reg = PMBUS_IOUT_UC_FAULT_LIMIT, + .attr = "lcrit", + .alarm = "lcrit_alarm", + .sbit = PB_IOUT_UC_FAULT, + }, { + .reg = PMBUS_IOUT_OC_FAULT_LIMIT, + .attr = "crit", + .alarm = "crit_alarm", + .sbit = PB_IOUT_OC_FAULT, + }, { + .reg = PMBUS_VIRT_READ_IOUT_AVG, + .update = true, + .attr = "average", + }, { + .reg = PMBUS_VIRT_READ_IOUT_MIN, + .update = true, + .attr = "lowest", + }, { + .reg = PMBUS_VIRT_READ_IOUT_MAX, + .update = true, + .attr = "highest", + }, { + .reg = PMBUS_VIRT_RESET_IOUT_HISTORY, + .attr = "reset_history", + }, { + .reg = PMBUS_MFR_IOUT_MAX, + .attr = "rated_max", + }, +}; + +static const struct pmbus_sensor_attr current_attributes[] = { + { + .reg = PMBUS_READ_IIN, + .class = PSC_CURRENT_IN, + .label = "iin", + .func = PMBUS_HAVE_IIN, + .sfunc = PMBUS_HAVE_STATUS_INPUT, + .sreg = PMBUS_STATUS_INPUT, + .gbit = PB_STATUS_INPUT, + .limit = iin_limit_attrs, + .nlimit = ARRAY_SIZE(iin_limit_attrs), + }, { + .reg = PMBUS_READ_IOUT, + .class = PSC_CURRENT_OUT, + .label = "iout", + .paged = true, + .func = PMBUS_HAVE_IOUT, + .sfunc = PMBUS_HAVE_STATUS_IOUT, + .sreg = PMBUS_STATUS_IOUT, + .gbit = PB_STATUS_IOUT_OC, + .limit = iout_limit_attrs, + .nlimit = ARRAY_SIZE(iout_limit_attrs), + } +}; + +/* Power attributes */ + +static const struct pmbus_limit_attr pin_limit_attrs[] = { + { + .reg = PMBUS_PIN_OP_WARN_LIMIT, + .attr = "max", + .alarm = "alarm", + .sbit = PB_PIN_OP_WARNING, + }, { + .reg = PMBUS_VIRT_READ_PIN_AVG, + .update = true, + .attr = "average", + }, { + .reg = PMBUS_VIRT_READ_PIN_MIN, + .update = true, + .attr = "input_lowest", + }, { + .reg = PMBUS_VIRT_READ_PIN_MAX, + .update = true, + .attr = "input_highest", + }, { + .reg = PMBUS_VIRT_RESET_PIN_HISTORY, + .attr = "reset_history", + }, { + .reg = PMBUS_MFR_PIN_MAX, + .attr = "rated_max", + }, +}; + +static const struct pmbus_limit_attr pout_limit_attrs[] = { + { + .reg = PMBUS_POUT_MAX, + .attr = "cap", + .alarm = "cap_alarm", + .sbit = PB_POWER_LIMITING, + }, { + .reg = PMBUS_POUT_OP_WARN_LIMIT, + .attr = "max", + .alarm = "max_alarm", + .sbit = PB_POUT_OP_WARNING, + }, { + .reg = PMBUS_POUT_OP_FAULT_LIMIT, + .attr = "crit", + .alarm = "crit_alarm", + .sbit = PB_POUT_OP_FAULT, + }, { + .reg = PMBUS_VIRT_READ_POUT_AVG, + .update = true, + .attr = "average", + }, { + .reg = PMBUS_VIRT_READ_POUT_MIN, + .update = true, + .attr = "input_lowest", + }, { + .reg = PMBUS_VIRT_READ_POUT_MAX, + .update = true, + .attr = "input_highest", + }, { + .reg = PMBUS_VIRT_RESET_POUT_HISTORY, + .attr = "reset_history", + }, { + .reg = PMBUS_MFR_POUT_MAX, + .attr = "rated_max", + }, +}; + +static const struct pmbus_sensor_attr power_attributes[] = { + { + .reg = PMBUS_READ_PIN, + .class = PSC_POWER, + .label = "pin", + .func = PMBUS_HAVE_PIN, + .sfunc = PMBUS_HAVE_STATUS_INPUT, + .sreg = PMBUS_STATUS_INPUT, + .gbit = PB_STATUS_INPUT, + .limit = pin_limit_attrs, + .nlimit = ARRAY_SIZE(pin_limit_attrs), + }, { + .reg = PMBUS_READ_POUT, + .class = PSC_POWER, + .label = "pout", + .paged = true, + .func = PMBUS_HAVE_POUT, + .sfunc = PMBUS_HAVE_STATUS_IOUT, + .sreg = PMBUS_STATUS_IOUT, + .limit = pout_limit_attrs, + .nlimit = ARRAY_SIZE(pout_limit_attrs), + } +}; + +/* Temperature atributes */ + +static const struct pmbus_limit_attr temp_limit_attrs[] = { + { + .reg = PMBUS_UT_WARN_LIMIT, + .low = true, + .attr = "min", + .alarm = "min_alarm", + .sbit = PB_TEMP_UT_WARNING, + }, { + .reg = PMBUS_UT_FAULT_LIMIT, + .low = true, + .attr = "lcrit", + .alarm = "lcrit_alarm", + .sbit = PB_TEMP_UT_FAULT, + }, { + .reg = PMBUS_OT_WARN_LIMIT, + .attr = "max", + .alarm = "max_alarm", + .sbit = PB_TEMP_OT_WARNING, + }, { + .reg = PMBUS_OT_FAULT_LIMIT, + .attr = "crit", + .alarm = "crit_alarm", + .sbit = PB_TEMP_OT_FAULT, + }, { + .reg = PMBUS_VIRT_READ_TEMP_MIN, + .attr = "lowest", + }, { + .reg = PMBUS_VIRT_READ_TEMP_AVG, + .attr = "average", + }, { + .reg = PMBUS_VIRT_READ_TEMP_MAX, + .attr = "highest", + }, { + .reg = PMBUS_VIRT_RESET_TEMP_HISTORY, + .attr = "reset_history", + }, { + .reg = PMBUS_MFR_MAX_TEMP_1, + .attr = "rated_max", + }, +}; + +static const struct pmbus_limit_attr temp_limit_attrs2[] = { + { + .reg = PMBUS_UT_WARN_LIMIT, + .low = true, + .attr = "min", + .alarm = "min_alarm", + .sbit = PB_TEMP_UT_WARNING, + }, { + .reg = PMBUS_UT_FAULT_LIMIT, + .low = true, + .attr = "lcrit", + .alarm = "lcrit_alarm", + .sbit = PB_TEMP_UT_FAULT, + }, { + .reg = PMBUS_OT_WARN_LIMIT, + .attr = "max", + .alarm = "max_alarm", + .sbit = PB_TEMP_OT_WARNING, + }, { + .reg = PMBUS_OT_FAULT_LIMIT, + .attr = "crit", + .alarm = "crit_alarm", + .sbit = PB_TEMP_OT_FAULT, + }, { + .reg = PMBUS_VIRT_READ_TEMP2_MIN, + .attr = "lowest", + }, { + .reg = PMBUS_VIRT_READ_TEMP2_AVG, + .attr = "average", + }, { + .reg = PMBUS_VIRT_READ_TEMP2_MAX, + .attr = "highest", + }, { + .reg = PMBUS_VIRT_RESET_TEMP2_HISTORY, + .attr = "reset_history", + }, { + .reg = PMBUS_MFR_MAX_TEMP_2, + .attr = "rated_max", + }, +}; + +static const struct pmbus_limit_attr temp_limit_attrs3[] = { + { + .reg = PMBUS_UT_WARN_LIMIT, + .low = true, + .attr = "min", + .alarm = "min_alarm", + .sbit = PB_TEMP_UT_WARNING, + }, { + .reg = PMBUS_UT_FAULT_LIMIT, + .low = true, + .attr = "lcrit", + .alarm = "lcrit_alarm", + .sbit = PB_TEMP_UT_FAULT, + }, { + .reg = PMBUS_OT_WARN_LIMIT, + .attr = "max", + .alarm = "max_alarm", + .sbit = PB_TEMP_OT_WARNING, + }, { + .reg = PMBUS_OT_FAULT_LIMIT, + .attr = "crit", + .alarm = "crit_alarm", + .sbit = PB_TEMP_OT_FAULT, + }, { + .reg = PMBUS_MFR_MAX_TEMP_3, + .attr = "rated_max", + }, +}; + +static const struct pmbus_sensor_attr temp_attributes[] = { + { + .reg = PMBUS_READ_TEMPERATURE_1, + .class = PSC_TEMPERATURE, + .paged = true, + .update = true, + .compare = true, + .func = PMBUS_HAVE_TEMP, + .sfunc = PMBUS_HAVE_STATUS_TEMP, + .sreg = PMBUS_STATUS_TEMPERATURE, + .gbit = PB_STATUS_TEMPERATURE, + .limit = temp_limit_attrs, + .nlimit = ARRAY_SIZE(temp_limit_attrs), + }, { + .reg = PMBUS_READ_TEMPERATURE_2, + .class = PSC_TEMPERATURE, + .paged = true, + .update = true, + .compare = true, + .func = PMBUS_HAVE_TEMP2, + .sfunc = PMBUS_HAVE_STATUS_TEMP, + .sreg = PMBUS_STATUS_TEMPERATURE, + .gbit = PB_STATUS_TEMPERATURE, + .limit = temp_limit_attrs2, + .nlimit = ARRAY_SIZE(temp_limit_attrs2), + }, { + .reg = PMBUS_READ_TEMPERATURE_3, + .class = PSC_TEMPERATURE, + .paged = true, + .update = true, + .compare = true, + .func = PMBUS_HAVE_TEMP3, + .sfunc = PMBUS_HAVE_STATUS_TEMP, + .sreg = PMBUS_STATUS_TEMPERATURE, + .gbit = PB_STATUS_TEMPERATURE, + .limit = temp_limit_attrs3, + .nlimit = ARRAY_SIZE(temp_limit_attrs3), + } +}; + +static const int pmbus_fan_registers[] = { + PMBUS_READ_FAN_SPEED_1, + PMBUS_READ_FAN_SPEED_2, + PMBUS_READ_FAN_SPEED_3, + PMBUS_READ_FAN_SPEED_4 +}; + +static const int pmbus_fan_status_registers[] = { + PMBUS_STATUS_FAN_12, + PMBUS_STATUS_FAN_12, + PMBUS_STATUS_FAN_34, + PMBUS_STATUS_FAN_34 +}; + +static const u32 pmbus_fan_flags[] = { + PMBUS_HAVE_FAN12, + PMBUS_HAVE_FAN12, + PMBUS_HAVE_FAN34, + PMBUS_HAVE_FAN34 +}; + +static const u32 pmbus_fan_status_flags[] = { + PMBUS_HAVE_STATUS_FAN12, + PMBUS_HAVE_STATUS_FAN12, + PMBUS_HAVE_STATUS_FAN34, + PMBUS_HAVE_STATUS_FAN34 +}; + +/* Fans */ + +/* Precondition: FAN_CONFIG_x_y and FAN_COMMAND_x must exist for the fan ID */ +static int pmbus_add_fan_ctrl(struct i2c_client *client, + struct pmbus_data *data, int index, int page, int id, + u8 config) +{ + struct pmbus_sensor *sensor; + + sensor = pmbus_add_sensor(data, "fan", "target", index, page, + 0xff, PMBUS_VIRT_FAN_TARGET_1 + id, PSC_FAN, + false, false, true); + + if (!sensor) + return -ENOMEM; + + if (!((data->info->func[page] & PMBUS_HAVE_PWM12) || + (data->info->func[page] & PMBUS_HAVE_PWM34))) + return 0; + + sensor = pmbus_add_sensor(data, "pwm", NULL, index, page, + 0xff, PMBUS_VIRT_PWM_1 + id, PSC_PWM, + false, false, true); + + if (!sensor) + return -ENOMEM; + + sensor = pmbus_add_sensor(data, "pwm", "enable", index, page, + 0xff, PMBUS_VIRT_PWM_ENABLE_1 + id, PSC_PWM, + true, false, false); + + if (!sensor) + return -ENOMEM; + + return 0; +} + +static int pmbus_add_fan_attributes(struct i2c_client *client, + struct pmbus_data *data) +{ + const struct pmbus_driver_info *info = data->info; + int index = 1; + int page; + int ret; + + for (page = 0; page < info->pages; page++) { + int f; + + for (f = 0; f < ARRAY_SIZE(pmbus_fan_registers); f++) { + int regval; + + if (!(info->func[page] & pmbus_fan_flags[f])) + break; + + if (!wb_pmbus_check_word_register(client, page, + pmbus_fan_registers[f])) + break; + + /* + * Skip fan if not installed. + * Each fan configuration register covers multiple fans, + * so we have to do some magic. + */ + regval = _pmbus_read_byte_data(client, page, + pmbus_fan_config_registers[f]); + if (regval < 0 || + (!(regval & (PB_FAN_1_INSTALLED >> ((f & 1) * 4))))) + continue; + + if (pmbus_add_sensor(data, "fan", "input", index, + page, 0xff, pmbus_fan_registers[f], + PSC_FAN, true, true, true) == NULL) + return -ENOMEM; + + /* Fan control */ + if (wb_pmbus_check_word_register(client, page, + pmbus_fan_command_registers[f])) { + ret = pmbus_add_fan_ctrl(client, data, index, + page, f, regval); + if (ret < 0) + return ret; + } + + /* + * Each fan status register covers multiple fans, + * so we have to do some magic. + */ + if ((info->func[page] & pmbus_fan_status_flags[f]) && + wb_pmbus_check_byte_register(client, + page, pmbus_fan_status_registers[f])) { + int reg; + + if (f > 1) /* fan 3, 4 */ + reg = PMBUS_STATUS_FAN_34; + else + reg = PMBUS_STATUS_FAN_12; + ret = pmbus_add_boolean(data, "fan", + "alarm", index, NULL, NULL, page, reg, + PB_FAN_FAN1_WARNING >> (f & 1)); + if (ret) + return ret; + ret = pmbus_add_boolean(data, "fan", + "fault", index, NULL, NULL, page, reg, + PB_FAN_FAN1_FAULT >> (f & 1)); + if (ret) + return ret; + } + index++; + } + } + return 0; +} + +struct pmbus_samples_attr { + int reg; + char *name; +}; + +struct pmbus_samples_reg { + int page; + struct pmbus_samples_attr *attr; + struct device_attribute dev_attr; +}; + +static struct pmbus_samples_attr pmbus_samples_registers[] = { + { + .reg = PMBUS_VIRT_SAMPLES, + .name = "samples", + }, { + .reg = PMBUS_VIRT_IN_SAMPLES, + .name = "in_samples", + }, { + .reg = PMBUS_VIRT_CURR_SAMPLES, + .name = "curr_samples", + }, { + .reg = PMBUS_VIRT_POWER_SAMPLES, + .name = "power_samples", + }, { + .reg = PMBUS_VIRT_TEMP_SAMPLES, + .name = "temp_samples", + } +}; + +#define to_samples_reg(x) container_of(x, struct pmbus_samples_reg, dev_attr) + +static ssize_t pmbus_show_samples(struct device *dev, + struct device_attribute *devattr, char *buf) +{ + int val; + struct i2c_client *client = to_i2c_client(dev->parent); + struct pmbus_samples_reg *reg = to_samples_reg(devattr); + struct pmbus_data *data = i2c_get_clientdata(client); + + mutex_lock(&data->update_lock); + val = _pmbus_read_word_data(client, reg->page, 0xff, reg->attr->reg); + mutex_unlock(&data->update_lock); + if (val < 0) + return val; + + return snprintf(buf, PAGE_SIZE, "%d\n", val); +} + +static ssize_t pmbus_set_samples(struct device *dev, + struct device_attribute *devattr, + const char *buf, size_t count) +{ + int ret; + long val; + struct i2c_client *client = to_i2c_client(dev->parent); + struct pmbus_samples_reg *reg = to_samples_reg(devattr); + struct pmbus_data *data = i2c_get_clientdata(client); + + if (kstrtol(buf, 0, &val) < 0) + return -EINVAL; + + mutex_lock(&data->update_lock); + ret = _pmbus_write_word_data(client, reg->page, reg->attr->reg, val); + mutex_unlock(&data->update_lock); + + return ret ? : count; +} + +static int pmbus_add_samples_attr(struct pmbus_data *data, int page, + struct pmbus_samples_attr *attr) +{ + struct pmbus_samples_reg *reg; + + reg = devm_kzalloc(data->dev, sizeof(*reg), GFP_KERNEL); + if (!reg) + return -ENOMEM; + + reg->attr = attr; + reg->page = page; + + pmbus_dev_attr_init(®->dev_attr, attr->name, 0644, + pmbus_show_samples, pmbus_set_samples); + + return pmbus_add_attribute(data, ®->dev_attr.attr); +} + +static int pmbus_add_samples_attributes(struct i2c_client *client, + struct pmbus_data *data) +{ + const struct pmbus_driver_info *info = data->info; + int s; + + if (!(info->func[0] & PMBUS_HAVE_SAMPLES)) + return 0; + + for (s = 0; s < ARRAY_SIZE(pmbus_samples_registers); s++) { + struct pmbus_samples_attr *attr; + int ret; + + attr = &pmbus_samples_registers[s]; + if (!wb_pmbus_check_word_register(client, 0, attr->reg)) + continue; + + ret = pmbus_add_samples_attr(data, 0, attr); + if (ret) + return ret; + } + + return 0; +} + +static int pmbus_find_attributes(struct i2c_client *client, + struct pmbus_data *data) +{ + int ret; + + /* Voltage sensors */ + ret = pmbus_add_sensor_attrs(client, data, "in", voltage_attributes, + ARRAY_SIZE(voltage_attributes)); + if (ret) + return ret; + + /* Current sensors */ + ret = pmbus_add_sensor_attrs(client, data, "curr", current_attributes, + ARRAY_SIZE(current_attributes)); + if (ret) + return ret; + + /* Power sensors */ + ret = pmbus_add_sensor_attrs(client, data, "power", power_attributes, + ARRAY_SIZE(power_attributes)); + if (ret) + return ret; + + /* Temperature sensors */ + ret = pmbus_add_sensor_attrs(client, data, "temp", temp_attributes, + ARRAY_SIZE(temp_attributes)); + if (ret) + return ret; + + /* Fans */ + ret = pmbus_add_fan_attributes(client, data); + if (ret) + return ret; + + ret = pmbus_add_samples_attributes(client, data); + return ret; +} + +/* + * Identify chip parameters. + * This function is called for all chips. + */ +static int pmbus_identify_common(struct i2c_client *client, + struct pmbus_data *data, int page) +{ + int vout_mode = -1; + + if (wb_pmbus_check_byte_register(client, page, PMBUS_VOUT_MODE)) + vout_mode = _pmbus_read_byte_data(client, page, + PMBUS_VOUT_MODE); + if (vout_mode >= 0 && vout_mode != 0xff) { + /* + * Not all chips support the VOUT_MODE command, + * so a failure to read it is not an error. + */ + switch (vout_mode >> 5) { + case 0: /* linear mode */ + if (data->info->format[PSC_VOLTAGE_OUT] != linear) + return -ENODEV; + + data->exponent[page] = ((s8)(vout_mode << 3)) >> 3; + break; + case 1: /* VID mode */ + if (data->info->format[PSC_VOLTAGE_OUT] != vid) + return -ENODEV; + break; + case 2: /* direct mode */ + if (data->info->format[PSC_VOLTAGE_OUT] != direct) + return -ENODEV; + break; + default: + return -ENODEV; + } + } + + pmbus_clear_fault_page(client, page); + return 0; +} + +static int pmbus_init_common(struct i2c_client *client, struct pmbus_data *data, + struct pmbus_driver_info *info) +{ + struct device *dev = &client->dev; + int page, ret, i; + + /* + * Some PMBus chips don't support PMBUS_STATUS_WORD, so try + * to use PMBUS_STATUS_BYTE instead if that is the case. + * Bail out if both registers are not supported. + */ + for(i = 0; i < PMBUS_RETRY_TIME; i++) { + data->read_status = pmbus_read_status_word; + ret = i2c_smbus_read_word_data(client, PMBUS_STATUS_WORD); + if (ret < 0 || ret == 0xffff) { + data->read_status = pmbus_read_status_byte; + ret = i2c_smbus_read_byte_data(client, PMBUS_STATUS_BYTE); + if (ret < 0 || ret == 0xff) { + usleep_range(PMBUS_RETRY_SLEEP_TIME, PMBUS_RETRY_SLEEP_TIME + 1); + continue; + } + } else { + data->has_status_word = true; + } + break; + } + + if(i == PMBUS_RETRY_TIME) { + dev_err(dev, "PMBus status register not found\n"); + return -ENODEV; + } + + /* Enable PEC if the controller supports it */ + for(i = 0; i < PMBUS_RETRY_TIME; i++) { + ret = i2c_smbus_read_byte_data(client, PMBUS_CAPABILITY); + if (ret >= 0) { + break; + } + usleep_range(PMBUS_RETRY_SLEEP_TIME, PMBUS_RETRY_SLEEP_TIME + 1); + } + + if (ret >= 0 && (ret & PB_CAPABILITY_ERROR_CHECK)) + client->flags |= I2C_CLIENT_PEC; + + /* + * Check if the chip is write protected. If it is, we can not clear + * faults, and we should not try it. Also, in that case, writes into + * limit registers need to be disabled. + */ + for(i = 0; i < PMBUS_RETRY_TIME; i++) { + ret = i2c_smbus_read_byte_data(client, PMBUS_WRITE_PROTECT); + if (ret >= 0) { + break; + } + usleep_range(PMBUS_RETRY_SLEEP_TIME, PMBUS_RETRY_SLEEP_TIME + 1); + } + + if (ret > 0 && (ret & PB_WP_ANY)) + data->flags |= PMBUS_WRITE_PROTECTED | PMBUS_SKIP_STATUS_CHECK; + + if (data->info->pages) + wb_pmbus_clear_faults(client); + else + pmbus_clear_fault_page(client, -1); + + if (info->identify) { + ret = (*info->identify)(client, info); + if (ret < 0) { + dev_err(dev, "Chip identification failed\n"); + return ret; + } + } + + if (info->pages <= 0 || info->pages > PMBUS_PAGES) { + dev_err(dev, "Bad number of PMBus pages: %d\n", info->pages); + return -ENODEV; + } + + for (page = 0; page < info->pages; page++) { + ret = pmbus_identify_common(client, data, page); + if (ret < 0) { + dev_err(dev, "Failed to identify chip capabilities\n"); + return ret; + } + } + return 0; +} + +#if IS_ENABLED(CONFIG_REGULATOR) +static int pmbus_regulator_is_enabled(struct regulator_dev *rdev) +{ + struct device *dev = rdev_get_dev(rdev); + struct i2c_client *client = to_i2c_client(dev->parent); + u8 page = rdev_get_id(rdev); + int ret; + + ret = wb_pmbus_read_byte_data(client, page, PMBUS_OPERATION); + if (ret < 0) + return ret; + + return !!(ret & PB_OPERATION_CONTROL_ON); +} + +static int _pmbus_regulator_on_off(struct regulator_dev *rdev, bool enable) +{ + struct device *dev = rdev_get_dev(rdev); + struct i2c_client *client = to_i2c_client(dev->parent); + u8 page = rdev_get_id(rdev); + + return wb_pmbus_update_byte_data(client, page, PMBUS_OPERATION, + PB_OPERATION_CONTROL_ON, + enable ? PB_OPERATION_CONTROL_ON : 0); +} + +static int pmbus_regulator_enable(struct regulator_dev *rdev) +{ + return _pmbus_regulator_on_off(rdev, 1); +} + +static int pmbus_regulator_disable(struct regulator_dev *rdev) +{ + return _pmbus_regulator_on_off(rdev, 0); +} + +const struct regulator_ops wb_pmbus_regulator_ops = { + .enable = pmbus_regulator_enable, + .disable = pmbus_regulator_disable, + .is_enabled = pmbus_regulator_is_enabled, +}; +EXPORT_SYMBOL_GPL(wb_pmbus_regulator_ops); + +static int pmbus_regulator_register(struct pmbus_data *data) +{ + struct device *dev = data->dev; + const struct pmbus_driver_info *info = data->info; + const struct pmbus_platform_data *pdata = dev_get_platdata(dev); + struct regulator_dev *rdev; + int i; + + for (i = 0; i < info->num_regulators; i++) { + struct regulator_config config = { }; + + config.dev = dev; + config.driver_data = data; + + if (pdata && pdata->reg_init_data) + config.init_data = &pdata->reg_init_data[i]; + + rdev = devm_regulator_register(dev, &info->reg_desc[i], + &config); + if (IS_ERR(rdev)) { + dev_err(dev, "Failed to register %s regulator\n", + info->reg_desc[i].name); + return PTR_ERR(rdev); + } + } + + return 0; +} +#else +static int pmbus_regulator_register(struct pmbus_data *data) +{ + return 0; +} +#endif + +static struct dentry *pmbus_debugfs_dir; /* pmbus debugfs directory */ + +#if IS_ENABLED(CONFIG_DEBUG_FS) +static int pmbus_debugfs_get(void *data, u64 *val) +{ + int rc; + struct pmbus_debugfs_entry *entry = data; + + rc = _pmbus_read_byte_data(entry->client, entry->page, entry->reg); + if (rc < 0) + return rc; + + *val = rc; + + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(pmbus_debugfs_ops, pmbus_debugfs_get, NULL, + "0x%02llx\n"); + +static int pmbus_debugfs_get_status(void *data, u64 *val) +{ + int rc; + struct pmbus_debugfs_entry *entry = data; + struct pmbus_data *pdata = i2c_get_clientdata(entry->client); + + rc = pdata->read_status(entry->client, entry->page); + if (rc < 0) + return rc; + + *val = rc; + + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(pmbus_debugfs_ops_status, pmbus_debugfs_get_status, + NULL, "0x%04llx\n"); + +static int pmbus_debugfs_get_pec(void *data, u64 *val) +{ + struct i2c_client *client = data; + + *val = !!(client->flags & I2C_CLIENT_PEC); + + return 0; +} + +static int pmbus_debugfs_set_pec(void *data, u64 val) +{ + int rc; + struct i2c_client *client = data; + + if (!val) { + client->flags &= ~I2C_CLIENT_PEC; + return 0; + } + + if (val != 1) + return -EINVAL; + + rc = i2c_smbus_read_byte_data(client, PMBUS_CAPABILITY); + if (rc < 0) + return rc; + + if (!(rc & PB_CAPABILITY_ERROR_CHECK)) + return -EOPNOTSUPP; + + client->flags |= I2C_CLIENT_PEC; + + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(pmbus_debugfs_ops_pec, pmbus_debugfs_get_pec, + pmbus_debugfs_set_pec, "%llu\n"); + +static int pmbus_init_debugfs(struct i2c_client *client, + struct pmbus_data *data) +{ + int i, idx = 0; + char name[PMBUS_NAME_SIZE]; + struct pmbus_debugfs_entry *entries; + + if (!pmbus_debugfs_dir) + return -ENODEV; + + /* + * Create the debugfs directory for this device. Use the hwmon device + * name to avoid conflicts (hwmon numbers are globally unique). + */ + data->debugfs = debugfs_create_dir(dev_name(data->hwmon_dev), + pmbus_debugfs_dir); + if (IS_ERR_OR_NULL(data->debugfs)) { + data->debugfs = NULL; + return -ENODEV; + } + + /* Allocate the max possible entries we need. */ + entries = devm_kcalloc(data->dev, + data->info->pages * 10, sizeof(*entries), + GFP_KERNEL); + if (!entries) + return -ENOMEM; + + debugfs_create_file("pec", 0664, data->debugfs, client, + &pmbus_debugfs_ops_pec); + + for (i = 0; i < data->info->pages; ++i) { + /* Check accessibility of status register if it's not page 0 */ + if (!i || pmbus_check_status_register(client, i)) { + /* No need to set reg as we have special read op. */ + entries[idx].client = client; + entries[idx].page = i; + scnprintf(name, PMBUS_NAME_SIZE, "status%d", i); + debugfs_create_file(name, 0444, data->debugfs, + &entries[idx++], + &pmbus_debugfs_ops_status); + } + + if (data->info->func[i] & PMBUS_HAVE_STATUS_VOUT) { + entries[idx].client = client; + entries[idx].page = i; + entries[idx].reg = PMBUS_STATUS_VOUT; + scnprintf(name, PMBUS_NAME_SIZE, "status%d_vout", i); + debugfs_create_file(name, 0444, data->debugfs, + &entries[idx++], + &pmbus_debugfs_ops); + } + + if (data->info->func[i] & PMBUS_HAVE_STATUS_IOUT) { + entries[idx].client = client; + entries[idx].page = i; + entries[idx].reg = PMBUS_STATUS_IOUT; + scnprintf(name, PMBUS_NAME_SIZE, "status%d_iout", i); + debugfs_create_file(name, 0444, data->debugfs, + &entries[idx++], + &pmbus_debugfs_ops); + } + + if (data->info->func[i] & PMBUS_HAVE_STATUS_INPUT) { + entries[idx].client = client; + entries[idx].page = i; + entries[idx].reg = PMBUS_STATUS_INPUT; + scnprintf(name, PMBUS_NAME_SIZE, "status%d_input", i); + debugfs_create_file(name, 0444, data->debugfs, + &entries[idx++], + &pmbus_debugfs_ops); + } + + if (data->info->func[i] & PMBUS_HAVE_STATUS_TEMP) { + entries[idx].client = client; + entries[idx].page = i; + entries[idx].reg = PMBUS_STATUS_TEMPERATURE; + scnprintf(name, PMBUS_NAME_SIZE, "status%d_temp", i); + debugfs_create_file(name, 0444, data->debugfs, + &entries[idx++], + &pmbus_debugfs_ops); + } + + if (wb_pmbus_check_byte_register(client, i, PMBUS_STATUS_CML)) { + entries[idx].client = client; + entries[idx].page = i; + entries[idx].reg = PMBUS_STATUS_CML; + scnprintf(name, PMBUS_NAME_SIZE, "status%d_cml", i); + debugfs_create_file(name, 0444, data->debugfs, + &entries[idx++], + &pmbus_debugfs_ops); + } + + if (wb_pmbus_check_byte_register(client, i, PMBUS_STATUS_OTHER)) { + entries[idx].client = client; + entries[idx].page = i; + entries[idx].reg = PMBUS_STATUS_OTHER; + scnprintf(name, PMBUS_NAME_SIZE, "status%d_other", i); + debugfs_create_file(name, 0444, data->debugfs, + &entries[idx++], + &pmbus_debugfs_ops); + } + + if (wb_pmbus_check_byte_register(client, i, + PMBUS_STATUS_MFR_SPECIFIC)) { + entries[idx].client = client; + entries[idx].page = i; + entries[idx].reg = PMBUS_STATUS_MFR_SPECIFIC; + scnprintf(name, PMBUS_NAME_SIZE, "status%d_mfr", i); + debugfs_create_file(name, 0444, data->debugfs, + &entries[idx++], + &pmbus_debugfs_ops); + } + + if (data->info->func[i] & PMBUS_HAVE_STATUS_FAN12) { + entries[idx].client = client; + entries[idx].page = i; + entries[idx].reg = PMBUS_STATUS_FAN_12; + scnprintf(name, PMBUS_NAME_SIZE, "status%d_fan12", i); + debugfs_create_file(name, 0444, data->debugfs, + &entries[idx++], + &pmbus_debugfs_ops); + } + + if (data->info->func[i] & PMBUS_HAVE_STATUS_FAN34) { + entries[idx].client = client; + entries[idx].page = i; + entries[idx].reg = PMBUS_STATUS_FAN_34; + scnprintf(name, PMBUS_NAME_SIZE, "status%d_fan34", i); + debugfs_create_file(name, 0444, data->debugfs, + &entries[idx++], + &pmbus_debugfs_ops); + } + } + + return 0; +} +#else +static int pmbus_init_debugfs(struct i2c_client *client, + struct pmbus_data *data) +{ + return 0; +} +#endif /* IS_ENABLED(CONFIG_DEBUG_FS) */ + +int wb_pmbus_do_probe(struct i2c_client *client, struct pmbus_driver_info *info) +{ + struct device *dev = &client->dev; + const struct pmbus_platform_data *pdata = dev_get_platdata(dev); + struct pmbus_data *data; + size_t groups_num = 0; + int ret; + + if (!info) + return -ENODEV; + + if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_WRITE_BYTE + | I2C_FUNC_SMBUS_BYTE_DATA + | I2C_FUNC_SMBUS_WORD_DATA)) + return -ENODEV; + + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + if (info->groups) + while (info->groups[groups_num]) + groups_num++; + + data->groups = devm_kcalloc(dev, groups_num + 2, sizeof(void *), + GFP_KERNEL); + if (!data->groups) + return -ENOMEM; + + i2c_set_clientdata(client, data); + mutex_init(&data->update_lock); + data->dev = dev; + + if (pdata) + data->flags = pdata->flags; + data->info = info; + data->currpage = -1; + data->currphase = -1; + + ret = pmbus_init_common(client, data, info); + if (ret < 0) + return ret; + + ret = pmbus_find_attributes(client, data); + if (ret) + return ret; + + /* + * If there are no attributes, something is wrong. + * Bail out instead of trying to register nothing. + */ + if (!data->num_attributes) { + dev_err(dev, "No attributes found\n"); + return -ENODEV; + } + + data->groups[0] = &data->group; + memcpy(data->groups + 1, info->groups, sizeof(void *) * groups_num); + data->hwmon_dev = devm_hwmon_device_register_with_groups(dev, + client->name, data, data->groups); + if (IS_ERR(data->hwmon_dev)) { + dev_err(dev, "Failed to register hwmon device\n"); + return PTR_ERR(data->hwmon_dev); + } + + ret = pmbus_regulator_register(data); + if (ret) + return ret; + + ret = pmbus_init_debugfs(client, data); + if (ret) + dev_warn(dev, "Failed to register debugfs\n"); + + return 0; +} +EXPORT_SYMBOL_GPL(wb_pmbus_do_probe); + +int wb_pmbus_do_remove(struct i2c_client *client) +{ + struct pmbus_data *data = i2c_get_clientdata(client); + + debugfs_remove_recursive(data->debugfs); + + return 0; +} +EXPORT_SYMBOL_GPL(wb_pmbus_do_remove); + +struct dentry *wb_pmbus_get_debugfs_dir(struct i2c_client *client) +{ + struct pmbus_data *data = i2c_get_clientdata(client); + + return data->debugfs; +} +EXPORT_SYMBOL_GPL(wb_pmbus_get_debugfs_dir); + +static int __init pmbus_core_init(void) +{ + pmbus_debugfs_dir = debugfs_create_dir("pmbus", NULL); + if (IS_ERR(pmbus_debugfs_dir)) + pmbus_debugfs_dir = NULL; + + return 0; +} + +static void __exit pmbus_core_exit(void) +{ + debugfs_remove_recursive(pmbus_debugfs_dir); +} + +module_init(pmbus_core_init); +module_exit(pmbus_core_exit); + +MODULE_AUTHOR("support"); +MODULE_DESCRIPTION("PMBus core driver"); +MODULE_LICENSE("GPL"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_tmp401.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_tmp401.c new file mode 100644 index 000000000000..4118510b1006 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_tmp401.c @@ -0,0 +1,798 @@ +/* tmp401.c + * + * Copyright (C) 2007,2008 Hans de Goede + * Preliminary tmp411 support by: + * Gabriel Konat, Sander Leget, Wouter Willems + * Copyright (C) 2009 Andre Prendel + * + * Cleanup and support for TMP431 and TMP432 by Guenter Roeck + * Copyright (c) 2013 Guenter Roeck + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * Driver for the Texas Instruments TMP401 SMBUS temperature sensor IC. + * + * Note this IC is in some aspect similar to the LM90, but it has quite a + * few differences too, for example the local temp has a higher resolution + * and thus has 16 bits registers for its value and limit instead of 8 bits. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Addresses to scan */ +/* static const unsigned short normal_i2c[] = { 0x48, 0x49, 0x4a, 0x4c, 0x4d, + 0x4e, 0x4f, I2C_CLIENT_END }; */ + +enum chips { tmp401, tmp411, tmp431, tmp432, tmp435, tmp461 }; + +/* + * The TMP401 registers, note some registers have different addresses for + * reading and writing + */ +#define TMP401_STATUS 0x02 +#define TMP401_CONFIG_READ 0x03 +#define TMP401_CONFIG_WRITE 0x09 +#define TMP401_CONVERSION_RATE_READ 0x04 +#define TMP401_CONVERSION_RATE_WRITE 0x0A +#define TMP401_TEMP_CRIT_HYST 0x21 +#define TMP401_MANUFACTURER_ID_REG 0xFE +#define TMP401_DEVICE_ID_REG 0xFF + +static const u8 TMP401_TEMP_MSB_READ[7][2] = { + { 0x00, 0x01 }, /* temp */ + { 0x06, 0x08 }, /* low limit */ + { 0x05, 0x07 }, /* high limit */ + { 0x20, 0x19 }, /* therm (crit) limit */ + { 0x30, 0x34 }, /* lowest */ + { 0x32, 0x36 }, /* highest */ + { 0, 0x11 }, /* offset */ +}; + +static const u8 TMP401_TEMP_MSB_WRITE[7][2] = { + { 0, 0 }, /* temp (unused) */ + { 0x0C, 0x0E }, /* low limit */ + { 0x0B, 0x0D }, /* high limit */ + { 0x20, 0x19 }, /* therm (crit) limit */ + { 0x30, 0x34 }, /* lowest */ + { 0x32, 0x36 }, /* highest */ + { 0, 0x11 }, /* offset */ +}; + +static const u8 TMP401_TEMP_LSB[7][2] = { + { 0x15, 0x10 }, /* temp */ + { 0x17, 0x14 }, /* low limit */ + { 0x16, 0x13 }, /* high limit */ + { 0, 0 }, /* therm (crit) limit (unused) */ + { 0x31, 0x35 }, /* lowest */ + { 0x33, 0x37 }, /* highest */ + { 0, 0x12 }, /* offset */ +}; + +static const u8 TMP432_TEMP_MSB_READ[4][3] = { + { 0x00, 0x01, 0x23 }, /* temp */ + { 0x06, 0x08, 0x16 }, /* low limit */ + { 0x05, 0x07, 0x15 }, /* high limit */ + { 0x20, 0x19, 0x1A }, /* therm (crit) limit */ +}; + +static const u8 TMP432_TEMP_MSB_WRITE[4][3] = { + { 0, 0, 0 }, /* temp - unused */ + { 0x0C, 0x0E, 0x16 }, /* low limit */ + { 0x0B, 0x0D, 0x15 }, /* high limit */ + { 0x20, 0x19, 0x1A }, /* therm (crit) limit */ +}; + +static const u8 TMP432_TEMP_LSB[3][3] = { + { 0x29, 0x10, 0x24 }, /* temp */ + { 0x3E, 0x14, 0x18 }, /* low limit */ + { 0x3D, 0x13, 0x17 }, /* high limit */ +}; + +/* [0] = fault, [1] = low, [2] = high, [3] = therm/crit */ +static const u8 TMP432_STATUS_REG[] = { + 0x1b, 0x36, 0x35, 0x37 }; + +/* Flags */ +#define TMP401_CONFIG_RANGE BIT(2) +#define TMP401_CONFIG_SHUTDOWN BIT(6) +#define TMP401_STATUS_LOCAL_CRIT BIT(0) +#define TMP401_STATUS_REMOTE_CRIT BIT(1) +#define TMP401_STATUS_REMOTE_OPEN BIT(2) +#define TMP401_STATUS_REMOTE_LOW BIT(3) +#define TMP401_STATUS_REMOTE_HIGH BIT(4) +#define TMP401_STATUS_LOCAL_LOW BIT(5) +#define TMP401_STATUS_LOCAL_HIGH BIT(6) + +/* On TMP432, each status has its own register */ +#define TMP432_STATUS_LOCAL BIT(0) +#define TMP432_STATUS_REMOTE1 BIT(1) +#define TMP432_STATUS_REMOTE2 BIT(2) + +/* Manufacturer / Device ID's */ +#define TMP401_MANUFACTURER_ID 0x55 +#define TMP401_DEVICE_ID 0x11 +#define TMP411A_DEVICE_ID 0x12 +#define TMP411B_DEVICE_ID 0x13 +#define TMP411C_DEVICE_ID 0x10 +#define TMP431_DEVICE_ID 0x31 +#define TMP432_DEVICE_ID 0x32 +#define TMP435_DEVICE_ID 0x35 + +/* + * Driver data (common to all clients) + */ + +static const struct i2c_device_id tmp401_id[] = { + { "wb_tmp401", tmp401 }, + { "wb_tmp411", tmp411 }, + { "wb_tmp431", tmp431 }, + { "wb_tmp432", tmp432 }, + { "wb_tmp435", tmp435 }, + { "wb_tmp461", tmp461 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, tmp401_id); + +/* + * Client data (each client gets its own) + */ + +struct tmp401_data { + struct i2c_client *client; + const struct attribute_group *groups[3]; + struct mutex update_lock; + char valid; /* zero until following fields are valid */ + unsigned long last_updated; /* in jiffies */ + enum chips kind; + + unsigned int update_interval; /* in milliseconds */ + + /* register values */ + u8 status[4]; + u8 config; + u16 temp[7][3]; + u8 temp_crit_hyst; +}; + +/* + * Sysfs attr show / store functions + */ + +static int tmp401_register_to_temp(u16 reg, u8 config) +{ + int temp = reg; + + if (config & TMP401_CONFIG_RANGE) + temp -= 64 * 256; + + return DIV_ROUND_CLOSEST(temp * 125, 32); +} + +static u16 tmp401_temp_to_register(long temp, u8 config, int zbits) +{ + if (config & TMP401_CONFIG_RANGE) { + temp = clamp_val(temp, -64000, 191000); + temp += 64000; + } else + temp = clamp_val(temp, 0, 127000); + + return DIV_ROUND_CLOSEST(temp * (1 << (8 - zbits)), 1000) << zbits; +} + +static int tmp401_update_device_reg16(struct i2c_client *client, + struct tmp401_data *data) +{ + int i, j, val; + int num_regs = data->kind == tmp411 ? 6 : 4; + int num_sensors = data->kind == tmp432 ? 3 : 2; + + for (i = 0; i < num_sensors; i++) { /* local / r1 / r2 */ + for (j = 0; j < num_regs; j++) { /* temp / low / ... */ + u8 regaddr; + /* + * High byte must be read first immediately followed + * by the low byte + */ + regaddr = data->kind == tmp432 ? + TMP432_TEMP_MSB_READ[j][i] : + TMP401_TEMP_MSB_READ[j][i]; + val = i2c_smbus_read_byte_data(client, regaddr); + if (val < 0) + return val; + data->temp[j][i] = val << 8; + if (j == 3) /* crit is msb only */ + continue; + regaddr = data->kind == tmp432 ? TMP432_TEMP_LSB[j][i] + : TMP401_TEMP_LSB[j][i]; + val = i2c_smbus_read_byte_data(client, regaddr); + if (val < 0) + return val; + data->temp[j][i] |= val; + } + } + return 0; +} + +static struct tmp401_data *tmp401_update_device(struct device *dev) +{ + struct tmp401_data *data = dev_get_drvdata(dev); + struct i2c_client *client = data->client; + struct tmp401_data *ret = data; + int i, val; + unsigned long next_update; + + mutex_lock(&data->update_lock); + + next_update = data->last_updated + + msecs_to_jiffies(data->update_interval); + if (time_after(jiffies, next_update) || !data->valid) { + if (data->kind != tmp432) { + /* + * The driver uses the TMP432 status format internally. + * Convert status to TMP432 format for other chips. + */ + val = i2c_smbus_read_byte_data(client, TMP401_STATUS); + if (val < 0) { + ret = ERR_PTR(val); + goto abort; + } + data->status[0] = + (val & TMP401_STATUS_REMOTE_OPEN) >> 1; + data->status[1] = + ((val & TMP401_STATUS_REMOTE_LOW) >> 2) | + ((val & TMP401_STATUS_LOCAL_LOW) >> 5); + data->status[2] = + ((val & TMP401_STATUS_REMOTE_HIGH) >> 3) | + ((val & TMP401_STATUS_LOCAL_HIGH) >> 6); + data->status[3] = val & (TMP401_STATUS_LOCAL_CRIT + | TMP401_STATUS_REMOTE_CRIT); + } else { + for (i = 0; i < ARRAY_SIZE(data->status); i++) { + val = i2c_smbus_read_byte_data(client, + TMP432_STATUS_REG[i]); + if (val < 0) { + ret = ERR_PTR(val); + goto abort; + } + data->status[i] = val; + } + } + + val = i2c_smbus_read_byte_data(client, TMP401_CONFIG_READ); + if (val < 0) { + ret = ERR_PTR(val); + goto abort; + } + data->config = val; + val = tmp401_update_device_reg16(client, data); + if (val < 0) { + ret = ERR_PTR(val); + goto abort; + } + val = i2c_smbus_read_byte_data(client, TMP401_TEMP_CRIT_HYST); + if (val < 0) { + ret = ERR_PTR(val); + goto abort; + } + data->temp_crit_hyst = val; + + data->last_updated = jiffies; + data->valid = 1; + } + +abort: + mutex_unlock(&data->update_lock); + return ret; +} + +static ssize_t show_temp(struct device *dev, + struct device_attribute *devattr, char *buf) +{ + int nr = to_sensor_dev_attr_2(devattr)->nr; + int index = to_sensor_dev_attr_2(devattr)->index; + struct tmp401_data *data = tmp401_update_device(dev); + + if (IS_ERR(data)) + return PTR_ERR(data); + + return sprintf(buf, "%d\n", + tmp401_register_to_temp(data->temp[nr][index], data->config)); +} + +static ssize_t show_temp_crit_hyst(struct device *dev, + struct device_attribute *devattr, char *buf) +{ + int temp, index = to_sensor_dev_attr(devattr)->index; + struct tmp401_data *data = tmp401_update_device(dev); + + if (IS_ERR(data)) + return PTR_ERR(data); + + mutex_lock(&data->update_lock); + temp = tmp401_register_to_temp(data->temp[3][index], data->config); + temp -= data->temp_crit_hyst * 1000; + mutex_unlock(&data->update_lock); + + return sprintf(buf, "%d\n", temp); +} + +static ssize_t show_status(struct device *dev, + struct device_attribute *devattr, char *buf) +{ + int nr = to_sensor_dev_attr_2(devattr)->nr; + int mask = to_sensor_dev_attr_2(devattr)->index; + struct tmp401_data *data = tmp401_update_device(dev); + + if (IS_ERR(data)) + return PTR_ERR(data); + + return sprintf(buf, "%d\n", !!(data->status[nr] & mask)); +} + +static ssize_t store_temp(struct device *dev, struct device_attribute *devattr, + const char *buf, size_t count) +{ + int nr = to_sensor_dev_attr_2(devattr)->nr; + int index = to_sensor_dev_attr_2(devattr)->index; + struct tmp401_data *data = dev_get_drvdata(dev); + struct i2c_client *client = data->client; + long val; + u16 reg; + u8 regaddr; + + if (kstrtol(buf, 10, &val)) + return -EINVAL; + + reg = tmp401_temp_to_register(val, data->config, nr == 3 ? 8 : 4); + + mutex_lock(&data->update_lock); + + regaddr = data->kind == tmp432 ? TMP432_TEMP_MSB_WRITE[nr][index] + : TMP401_TEMP_MSB_WRITE[nr][index]; + i2c_smbus_write_byte_data(client, regaddr, reg >> 8); + if (nr != 3) { + regaddr = data->kind == tmp432 ? TMP432_TEMP_LSB[nr][index] + : TMP401_TEMP_LSB[nr][index]; + i2c_smbus_write_byte_data(client, regaddr, reg & 0xFF); + } + data->temp[nr][index] = reg; + + mutex_unlock(&data->update_lock); + + return count; +} + +static ssize_t store_temp_crit_hyst(struct device *dev, struct device_attribute + *devattr, const char *buf, size_t count) +{ + int temp, index = to_sensor_dev_attr(devattr)->index; + struct tmp401_data *data = tmp401_update_device(dev); + long val; + u8 reg; + + if (IS_ERR(data)) + return PTR_ERR(data); + + if (kstrtol(buf, 10, &val)) + return -EINVAL; + + if (data->config & TMP401_CONFIG_RANGE) + val = clamp_val(val, -64000, 191000); + else + val = clamp_val(val, 0, 127000); + + mutex_lock(&data->update_lock); + temp = tmp401_register_to_temp(data->temp[3][index], data->config); + val = clamp_val(val, temp - 255000, temp); + reg = ((temp - val) + 500) / 1000; + + i2c_smbus_write_byte_data(data->client, TMP401_TEMP_CRIT_HYST, + reg); + + data->temp_crit_hyst = reg; + + mutex_unlock(&data->update_lock); + + return count; +} + +/* + * Resets the historical measurements of minimum and maximum temperatures. + * This is done by writing any value to any of the minimum/maximum registers + * (0x30-0x37). + */ +static ssize_t reset_temp_history(struct device *dev, + struct device_attribute *devattr, const char *buf, size_t count) +{ + struct tmp401_data *data = dev_get_drvdata(dev); + struct i2c_client *client = data->client; + long val; + + if (kstrtol(buf, 10, &val)) + return -EINVAL; + + if (val != 1) { + dev_err(dev, + "temp_reset_history value %ld not supported. Use 1 to reset the history!\n", + val); + return -EINVAL; + } + mutex_lock(&data->update_lock); + i2c_smbus_write_byte_data(client, TMP401_TEMP_MSB_WRITE[5][0], val); + data->valid = 0; + mutex_unlock(&data->update_lock); + + return count; +} + +static ssize_t show_update_interval(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct tmp401_data *data = dev_get_drvdata(dev); + + return sprintf(buf, "%u\n", data->update_interval); +} + +static ssize_t set_update_interval(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct tmp401_data *data = dev_get_drvdata(dev); + struct i2c_client *client = data->client; + unsigned long val; + int err, rate; + + err = kstrtoul(buf, 10, &val); + if (err) + return err; + + /* + * For valid rates, interval can be calculated as + * interval = (1 << (7 - rate)) * 125; + * Rounded rate is therefore + * rate = 7 - __fls(interval * 4 / (125 * 3)); + * Use clamp_val() to avoid overflows, and to ensure valid input + * for __fls. + */ + val = clamp_val(val, 125, 16000); + rate = 7 - __fls(val * 4 / (125 * 3)); + mutex_lock(&data->update_lock); + i2c_smbus_write_byte_data(client, TMP401_CONVERSION_RATE_WRITE, rate); + data->update_interval = (1 << (7 - rate)) * 125; + mutex_unlock(&data->update_lock); + + return count; +} + +static SENSOR_DEVICE_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0); +static SENSOR_DEVICE_ATTR_2(temp1_min, S_IWUSR | S_IRUGO, show_temp, + store_temp, 1, 0); +static SENSOR_DEVICE_ATTR_2(temp1_max, S_IWUSR | S_IRUGO, show_temp, + store_temp, 2, 0); +static SENSOR_DEVICE_ATTR_2(temp1_crit, S_IWUSR | S_IRUGO, show_temp, + store_temp, 3, 0); +static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IWUSR | S_IRUGO, + show_temp_crit_hyst, store_temp_crit_hyst, 0); +static SENSOR_DEVICE_ATTR_2(temp1_min_alarm, S_IRUGO, show_status, NULL, + 1, TMP432_STATUS_LOCAL); +static SENSOR_DEVICE_ATTR_2(temp1_max_alarm, S_IRUGO, show_status, NULL, + 2, TMP432_STATUS_LOCAL); +static SENSOR_DEVICE_ATTR_2(temp1_crit_alarm, S_IRUGO, show_status, NULL, + 3, TMP432_STATUS_LOCAL); +static SENSOR_DEVICE_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 0, 1); +static SENSOR_DEVICE_ATTR_2(temp2_min, S_IWUSR | S_IRUGO, show_temp, + store_temp, 1, 1); +static SENSOR_DEVICE_ATTR_2(temp2_max, S_IWUSR | S_IRUGO, show_temp, + store_temp, 2, 1); +static SENSOR_DEVICE_ATTR_2(temp2_crit, S_IWUSR | S_IRUGO, show_temp, + store_temp, 3, 1); +static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, show_temp_crit_hyst, + NULL, 1); +static SENSOR_DEVICE_ATTR_2(temp2_fault, S_IRUGO, show_status, NULL, + 0, TMP432_STATUS_REMOTE1); +static SENSOR_DEVICE_ATTR_2(temp2_min_alarm, S_IRUGO, show_status, NULL, + 1, TMP432_STATUS_REMOTE1); +static SENSOR_DEVICE_ATTR_2(temp2_max_alarm, S_IRUGO, show_status, NULL, + 2, TMP432_STATUS_REMOTE1); +static SENSOR_DEVICE_ATTR_2(temp2_crit_alarm, S_IRUGO, show_status, NULL, + 3, TMP432_STATUS_REMOTE1); + +static DEVICE_ATTR(update_interval, S_IRUGO | S_IWUSR, show_update_interval, + set_update_interval); + +static struct attribute *tmp401_attributes[] = { + &sensor_dev_attr_temp1_input.dev_attr.attr, + &sensor_dev_attr_temp1_min.dev_attr.attr, + &sensor_dev_attr_temp1_max.dev_attr.attr, + &sensor_dev_attr_temp1_crit.dev_attr.attr, + &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr, + &sensor_dev_attr_temp1_max_alarm.dev_attr.attr, + &sensor_dev_attr_temp1_min_alarm.dev_attr.attr, + &sensor_dev_attr_temp1_crit_alarm.dev_attr.attr, + + &sensor_dev_attr_temp2_input.dev_attr.attr, + &sensor_dev_attr_temp2_min.dev_attr.attr, + &sensor_dev_attr_temp2_max.dev_attr.attr, + &sensor_dev_attr_temp2_crit.dev_attr.attr, + &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr, + &sensor_dev_attr_temp2_fault.dev_attr.attr, + &sensor_dev_attr_temp2_max_alarm.dev_attr.attr, + &sensor_dev_attr_temp2_min_alarm.dev_attr.attr, + &sensor_dev_attr_temp2_crit_alarm.dev_attr.attr, + + &dev_attr_update_interval.attr, + + NULL +}; + +static const struct attribute_group tmp401_group = { + .attrs = tmp401_attributes, +}; + +/* + * Additional features of the TMP411 chip. + * The TMP411 stores the minimum and maximum + * temperature measured since power-on, chip-reset, or + * minimum and maximum register reset for both the local + * and remote channels. + */ +static SENSOR_DEVICE_ATTR_2(temp1_lowest, S_IRUGO, show_temp, NULL, 4, 0); +static SENSOR_DEVICE_ATTR_2(temp1_highest, S_IRUGO, show_temp, NULL, 5, 0); +static SENSOR_DEVICE_ATTR_2(temp2_lowest, S_IRUGO, show_temp, NULL, 4, 1); +static SENSOR_DEVICE_ATTR_2(temp2_highest, S_IRUGO, show_temp, NULL, 5, 1); +static SENSOR_DEVICE_ATTR(temp_reset_history, S_IWUSR, NULL, reset_temp_history, + 0); + +static struct attribute *tmp411_attributes[] = { + &sensor_dev_attr_temp1_highest.dev_attr.attr, + &sensor_dev_attr_temp1_lowest.dev_attr.attr, + &sensor_dev_attr_temp2_highest.dev_attr.attr, + &sensor_dev_attr_temp2_lowest.dev_attr.attr, + &sensor_dev_attr_temp_reset_history.dev_attr.attr, + NULL +}; + +static const struct attribute_group tmp411_group = { + .attrs = tmp411_attributes, +}; + +static SENSOR_DEVICE_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 0, 2); +static SENSOR_DEVICE_ATTR_2(temp3_min, S_IWUSR | S_IRUGO, show_temp, + store_temp, 1, 2); +static SENSOR_DEVICE_ATTR_2(temp3_max, S_IWUSR | S_IRUGO, show_temp, + store_temp, 2, 2); +static SENSOR_DEVICE_ATTR_2(temp3_crit, S_IWUSR | S_IRUGO, show_temp, + store_temp, 3, 2); +static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, show_temp_crit_hyst, + NULL, 2); +static SENSOR_DEVICE_ATTR_2(temp3_fault, S_IRUGO, show_status, NULL, + 0, TMP432_STATUS_REMOTE2); +static SENSOR_DEVICE_ATTR_2(temp3_min_alarm, S_IRUGO, show_status, NULL, + 1, TMP432_STATUS_REMOTE2); +static SENSOR_DEVICE_ATTR_2(temp3_max_alarm, S_IRUGO, show_status, NULL, + 2, TMP432_STATUS_REMOTE2); +static SENSOR_DEVICE_ATTR_2(temp3_crit_alarm, S_IRUGO, show_status, NULL, + 3, TMP432_STATUS_REMOTE2); + +static struct attribute *tmp432_attributes[] = { + &sensor_dev_attr_temp3_input.dev_attr.attr, + &sensor_dev_attr_temp3_min.dev_attr.attr, + &sensor_dev_attr_temp3_max.dev_attr.attr, + &sensor_dev_attr_temp3_crit.dev_attr.attr, + &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr, + &sensor_dev_attr_temp3_fault.dev_attr.attr, + &sensor_dev_attr_temp3_max_alarm.dev_attr.attr, + &sensor_dev_attr_temp3_min_alarm.dev_attr.attr, + &sensor_dev_attr_temp3_crit_alarm.dev_attr.attr, + + NULL +}; + +static const struct attribute_group tmp432_group = { + .attrs = tmp432_attributes, +}; + +/* + * Additional features of the TMP461 chip. + * The TMP461 temperature offset for the remote channel. + */ +static SENSOR_DEVICE_ATTR_2(temp2_offset, S_IWUSR | S_IRUGO, show_temp, + store_temp, 6, 1); + +static struct attribute *tmp461_attributes[] = { + &sensor_dev_attr_temp2_offset.dev_attr.attr, + NULL +}; + +static const struct attribute_group tmp461_group = { + .attrs = tmp461_attributes, +}; + +/* + * Begin non sysfs callback code (aka Real code) + */ + +static int tmp401_init_client(struct tmp401_data *data, + struct i2c_client *client) +{ + int config, config_orig, status = 0; + + /* Set the conversion rate to 2 Hz */ + i2c_smbus_write_byte_data(client, TMP401_CONVERSION_RATE_WRITE, 5); + data->update_interval = 500; + + /* Start conversions (disable shutdown if necessary) */ + config = i2c_smbus_read_byte_data(client, TMP401_CONFIG_READ); + if (config < 0) + return config; + + config_orig = config; + config &= ~TMP401_CONFIG_SHUTDOWN; + + if (config != config_orig) + status = i2c_smbus_write_byte_data(client, + TMP401_CONFIG_WRITE, + config); + + return status; +} + +#if 0 +static int tmp401_detect(struct i2c_client *client, + struct i2c_board_info *info) +{ + enum chips kind; + struct i2c_adapter *adapter = client->adapter; + u8 reg; + + if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) + return -ENODEV; + + /* Detect and identify the chip */ + reg = i2c_smbus_read_byte_data(client, TMP401_MANUFACTURER_ID_REG); + if (reg != TMP401_MANUFACTURER_ID) + return -ENODEV; + + reg = i2c_smbus_read_byte_data(client, TMP401_DEVICE_ID_REG); + + switch (reg) { + case TMP401_DEVICE_ID: + if (client->addr != 0x4c) + return -ENODEV; + kind = tmp401; + break; + case TMP411A_DEVICE_ID: + if (client->addr != 0x4c) + return -ENODEV; + kind = tmp411; + break; + case TMP411B_DEVICE_ID: + if (client->addr != 0x4d) + return -ENODEV; + kind = tmp411; + break; + case TMP411C_DEVICE_ID: + if (client->addr != 0x4e) + return -ENODEV; + kind = tmp411; + break; + case TMP431_DEVICE_ID: + if (client->addr != 0x4c && client->addr != 0x4d) + return -ENODEV; + kind = tmp431; + break; + case TMP432_DEVICE_ID: + if (client->addr != 0x4c && client->addr != 0x4d) + return -ENODEV; + kind = tmp432; + break; + case TMP435_DEVICE_ID: + kind = tmp435; + break; + default: + return -ENODEV; + } + + reg = i2c_smbus_read_byte_data(client, TMP401_CONFIG_READ); + if (reg & 0x1b) + return -ENODEV; + + reg = i2c_smbus_read_byte_data(client, TMP401_CONVERSION_RATE_READ); + /* Datasheet says: 0x1-0x6 */ + if (reg > 15) + return -ENODEV; + + strlcpy(info->type, tmp401_id[kind].name, I2C_NAME_SIZE); + + return 0; +} +#endif + +static int tmp401_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + static const char * const names[] = { + "TMP401", "TMP411", "TMP431", "TMP432", "TMP435", "TMP461" + }; + struct device *dev = &client->dev; + struct device *hwmon_dev; + struct tmp401_data *data; + int groups = 0, status; + + data = devm_kzalloc(dev, sizeof(struct tmp401_data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->client = client; + mutex_init(&data->update_lock); + data->kind = id->driver_data; + + /* Initialize the TMP401 chip */ + status = tmp401_init_client(data, client); + if (status < 0) + return status; + + /* Register sysfs hooks */ + data->groups[groups++] = &tmp401_group; + + /* Register additional tmp411 sysfs hooks */ + if (data->kind == tmp411) + data->groups[groups++] = &tmp411_group; + + /* Register additional tmp432 sysfs hooks */ + if (data->kind == tmp432) + data->groups[groups++] = &tmp432_group; + + if (data->kind == tmp461) + data->groups[groups++] = &tmp461_group; + + hwmon_dev = devm_hwmon_device_register_with_groups(dev, client->name, + data, data->groups); + if (IS_ERR(hwmon_dev)) + return PTR_ERR(hwmon_dev); + + dev_info(dev, "Detected TI %s chip\n", names[data->kind]); + + return 0; +} + +static struct i2c_driver tmp401_driver = { + .class = I2C_CLASS_HWMON, + .driver = { + .name = "wb_tmp401", + }, + .probe = tmp401_probe, + .id_table = tmp401_id, + /* .detect = tmp401_detect, */ + /* .address_list = normal_i2c, */ +}; + +module_i2c_driver(tmp401_driver); + +MODULE_AUTHOR("support"); +MODULE_DESCRIPTION("Texas Instruments TMP401 temperature sensor driver"); +MODULE_LICENSE("GPL"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_tps53622.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_tps53622.c new file mode 100644 index 000000000000..b68196d9f57c --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_tps53622.c @@ -0,0 +1,265 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Hardware monitoring driver for Texas Instruments TPS53679 + * + * Copyright (c) 2017 Mellanox Technologies. All rights reserved. + * Copyright (c) 2017 Vadim Pasternak + */ + +#include +#include +#include +#include +#include +#include +#include +#include "wb_pmbus.h" + +enum chips { + tps53647, tps53667, tps53679, tps53681, tps53688, tps53622 +}; + +#define TPS53647_PAGE_NUM 1 + +#define TPS53679_PROT_VR12_5MV 0x01 /* VR12.0 mode, 5-mV DAC */ +#define TPS53679_PROT_VR12_5_10MV 0x02 /* VR12.5 mode, 10-mV DAC */ +#define TPS53679_PROT_VR13_10MV 0x04 /* VR13.0 mode, 10-mV DAC */ +#define TPS53679_PROT_IMVP8_5MV 0x05 /* IMVP8 mode, 5-mV DAC */ +#define TPS53679_PROT_VR13_5MV 0x07 /* VR13.0 mode, 5-mV DAC */ +#define TPS53679_PAGE_NUM 2 + +#define TPS53681_DEVICE_ID 0x81 + +#define TPS53681_PMBUS_REVISION 0x33 + +#define TPS53681_MFR_SPECIFIC_20 0xe4 /* Number of phases, per page */ + +static const struct i2c_device_id tps53679_id[]; + +static int tps53679_identify_mode(struct i2c_client *client, + struct pmbus_driver_info *info) +{ + u8 vout_params; + int i, ret; + + for (i = 0; i < info->pages; i++) { + /* Read the register with VOUT scaling value.*/ + ret = wb_pmbus_read_byte_data(client, i, PMBUS_VOUT_MODE); + if (ret < 0) + return ret; + + vout_params = ret & GENMASK(4, 0); + + switch (vout_params) { + case TPS53679_PROT_VR13_10MV: + case TPS53679_PROT_VR12_5_10MV: + info->vrm_version[i] = vr13; + break; + case TPS53679_PROT_VR13_5MV: + case TPS53679_PROT_VR12_5MV: + case TPS53679_PROT_IMVP8_5MV: + info->vrm_version[i] = vr12; + break; + default: + return -EINVAL; + } + } + + return 0; +} + +static int tps53679_identify_phases(struct i2c_client *client, + struct pmbus_driver_info *info) +{ + int ret; + + /* On TPS53681, only channel A provides per-phase output current */ + ret = wb_pmbus_read_byte_data(client, 0, TPS53681_MFR_SPECIFIC_20); + if (ret < 0) + return ret; + info->phases[0] = (ret & 0x07) + 1; + + return 0; +} + +static int tps53679_identify_chip(struct i2c_client *client, + u8 revision, u16 id) +{ + u8 buf[I2C_SMBUS_BLOCK_MAX]; + int ret; + + ret = wb_pmbus_read_byte_data(client, 0, PMBUS_REVISION); + if (ret < 0) + return ret; + if (ret != revision) { + dev_err(&client->dev, "Unexpected PMBus revision 0x%x\n", ret); + return -ENODEV; + } + + ret = i2c_smbus_read_block_data(client, PMBUS_IC_DEVICE_ID, buf); + if (ret < 0) + return ret; + if (ret != 1 || buf[0] != id) { + dev_err(&client->dev, "Unexpected device ID 0x%x\n", buf[0]); + return -ENODEV; + } + return 0; +} + +/* + * Common identification function for chips with multi-phase support. + * Since those chips have special configuration registers, we want to have + * some level of reassurance that we are really talking with the chip + * being probed. Check PMBus revision and chip ID. + */ +static int tps53679_identify_multiphase(struct i2c_client *client, + struct pmbus_driver_info *info, + int pmbus_rev, int device_id) +{ + int ret; + + ret = tps53679_identify_chip(client, pmbus_rev, device_id); + if (ret < 0) + return ret; + + ret = tps53679_identify_mode(client, info); + if (ret < 0) + return ret; + + return tps53679_identify_phases(client, info); +} + +static int tps53679_identify(struct i2c_client *client, + struct pmbus_driver_info *info) +{ + return tps53679_identify_mode(client, info); +} + +static int tps53681_identify(struct i2c_client *client, + struct pmbus_driver_info *info) +{ + return tps53679_identify_multiphase(client, info, + TPS53681_PMBUS_REVISION, + TPS53681_DEVICE_ID); +} + +static int tps53681_read_word_data(struct i2c_client *client, int page, + int phase, int reg) +{ + /* + * For reading the total output current (READ_IOUT) for all phases, + * the chip datasheet is a bit vague. It says "PHASE must be set to + * FFh to access all phases simultaneously. PHASE may also be set to + * 80h readack (!) the total phase current". + * Experiments show that the command does _not_ report the total + * current for all phases if the phase is set to 0xff. Instead, it + * appears to report the current of one of the phases. Override phase + * parameter with 0x80 when reading the total output current on page 0. + */ + if (reg == PMBUS_READ_IOUT && page == 0 && phase == 0xff) + return wb_pmbus_read_word_data(client, page, 0x80, reg); + return -ENODATA; +} + +static struct pmbus_driver_info tps53679_info = { + .format[PSC_VOLTAGE_IN] = linear, + .format[PSC_VOLTAGE_OUT] = vid, + .format[PSC_TEMPERATURE] = linear, + .format[PSC_CURRENT_OUT] = linear, + .format[PSC_POWER] = linear, + .func[0] = PMBUS_HAVE_VIN | PMBUS_HAVE_IIN | PMBUS_HAVE_PIN | + PMBUS_HAVE_STATUS_INPUT | + PMBUS_HAVE_VOUT | PMBUS_HAVE_STATUS_VOUT | + PMBUS_HAVE_IOUT | PMBUS_HAVE_STATUS_IOUT | + PMBUS_HAVE_TEMP | PMBUS_HAVE_STATUS_TEMP | + PMBUS_HAVE_POUT, + .func[1] = PMBUS_HAVE_VOUT | PMBUS_HAVE_STATUS_VOUT | + PMBUS_HAVE_IOUT | PMBUS_HAVE_STATUS_IOUT | + PMBUS_HAVE_TEMP | PMBUS_HAVE_STATUS_TEMP | + PMBUS_HAVE_POUT, + .pfunc[0] = PMBUS_HAVE_IOUT, + .pfunc[1] = PMBUS_HAVE_IOUT, + .pfunc[2] = PMBUS_HAVE_IOUT, + .pfunc[3] = PMBUS_HAVE_IOUT, + .pfunc[4] = PMBUS_HAVE_IOUT, + .pfunc[5] = PMBUS_HAVE_IOUT, +}; + +static int tps53679_probe(struct i2c_client *client) +{ + struct device *dev = &client->dev; + struct pmbus_driver_info *info; + enum chips chip_id; + + if (dev->of_node) + chip_id = (enum chips)of_device_get_match_data(dev); + else + chip_id = i2c_match_id(tps53679_id, client)->driver_data; + + info = devm_kmemdup(dev, &tps53679_info, sizeof(*info), GFP_KERNEL); + if (!info) + return -ENOMEM; + + switch (chip_id) { + case tps53647: + case tps53667: + info->pages = TPS53647_PAGE_NUM; + info->identify = tps53679_identify; + break; + case tps53679: + case tps53688: + case tps53622: + info->pages = TPS53679_PAGE_NUM; + info->identify = tps53679_identify; + break; + case tps53681: + info->pages = TPS53679_PAGE_NUM; + info->phases[0] = 6; + info->identify = tps53681_identify; + info->read_word_data = tps53681_read_word_data; + break; + default: + return -ENODEV; + } + + return wb_pmbus_do_probe(client, info); +} + +static const struct i2c_device_id tps53679_id[] = { + {"wb_tps53647", tps53647}, + {"wb_tps53667", tps53667}, + {"wb_tps53679", tps53679}, + {"wb_tps53681", tps53681}, + {"wb_tps53688", tps53688}, + {"wb_tps53622", tps53622}, + {} +}; + +MODULE_DEVICE_TABLE(i2c, tps53679_id); + +static const struct of_device_id __maybe_unused tps53679_of_match[] = { + {.compatible = "ti,wb_tps53647", .data = (void *)tps53647}, + {.compatible = "ti,wb_tps53667", .data = (void *)tps53667}, + {.compatible = "ti,wb_tps53679", .data = (void *)tps53679}, + {.compatible = "ti,wb_tps53681", .data = (void *)tps53681}, + {.compatible = "ti,wb_tps53688", .data = (void *)tps53688}, + {.compatible = "ti,wb_tps53622", .data = (void *)tps53622}, + {} +}; +MODULE_DEVICE_TABLE(of, tps53679_of_match); + +static struct i2c_driver tps53679_driver = { + .driver = { + .name = "wb_tps53622", + .of_match_table = of_match_ptr(tps53679_of_match), + }, + .probe_new = tps53679_probe, + .remove = wb_pmbus_do_remove, + .id_table = tps53679_id, +}; + +module_i2c_driver(tps53679_driver); + +MODULE_AUTHOR("support"); +MODULE_DESCRIPTION("PMBus driver for Texas Instruments TPS53679"); +MODULE_LICENSE("GPL"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_ucd9000.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_ucd9000.c new file mode 100644 index 000000000000..9b967f141a86 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/linux-5.10/wb_ucd9000.c @@ -0,0 +1,675 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Hardware monitoring driver for UCD90xxx Sequencer and System Health + * Controller series + * + * Copyright (C) 2011 Ericsson AB. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "wb_pmbus.h" + +enum chips { ucd9000, ucd90120, ucd90124, ucd90160, ucd90320, ucd9090, + ucd90910 }; + +#define UCD9000_MONITOR_CONFIG 0xd5 +#define UCD9000_NUM_PAGES 0xd6 +#define UCD9000_FAN_CONFIG_INDEX 0xe7 +#define UCD9000_FAN_CONFIG 0xe8 +#define UCD9000_MFR_STATUS 0xf3 +#define UCD9000_GPIO_SELECT 0xfa +#define UCD9000_GPIO_CONFIG 0xfb +#define UCD9000_DEVICE_ID 0xfd + +/* GPIO CONFIG bits */ +#define UCD9000_GPIO_CONFIG_ENABLE BIT(0) +#define UCD9000_GPIO_CONFIG_OUT_ENABLE BIT(1) +#define UCD9000_GPIO_CONFIG_OUT_VALUE BIT(2) +#define UCD9000_GPIO_CONFIG_STATUS BIT(3) +#define UCD9000_GPIO_INPUT 0 +#define UCD9000_GPIO_OUTPUT 1 + +#define UCD9000_MON_TYPE(x) (((x) >> 5) & 0x07) +#define UCD9000_MON_PAGE(x) ((x) & 0x1f) + +#define UCD9000_MON_VOLTAGE 1 +#define UCD9000_MON_TEMPERATURE 2 +#define UCD9000_MON_CURRENT 3 +#define UCD9000_MON_VOLTAGE_HW 4 + +#define UCD9000_NUM_FAN 4 + +#define UCD9000_GPIO_NAME_LEN 16 +#define UCD9090_NUM_GPIOS 23 +#define UCD901XX_NUM_GPIOS 26 +#define UCD90320_NUM_GPIOS 84 +#define UCD90910_NUM_GPIOS 26 + +#define UCD9000_DEBUGFS_NAME_LEN 24 +#define UCD9000_GPI_COUNT 8 +#define UCD90320_GPI_COUNT 32 + +#define UCD9000_RETRY_SLEEP_TIME (10000) /* 10ms */ +#define UCD9000_RETRY_TIME (3) +#define WB_DEV_NAME_MAX_LEN (64) + +static int g_wb_ucd9000_debug = 0; +static int g_wb_ucd9000_error = 0; + +module_param(g_wb_ucd9000_debug, int, S_IRUGO | S_IWUSR); +module_param(g_wb_ucd9000_error, int, S_IRUGO | S_IWUSR); + +#define WB_UDC9000_VERBOSE(fmt, args...) do { \ + if (g_wb_ucd9000_debug) { \ + printk(KERN_INFO "[WB_UCD9000][VER][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +#define WB_UDC9000_ERROR(fmt, args...) do { \ + if (g_wb_ucd9000_error) { \ + printk(KERN_ERR "[WB_UCD9000][ERR][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +struct ucd9000_data { + u8 fan_data[UCD9000_NUM_FAN][I2C_SMBUS_BLOCK_MAX]; + struct pmbus_driver_info info; +#ifdef CONFIG_GPIOLIB + struct gpio_chip gpio; +#endif + struct dentry *debugfs; +}; +#define to_ucd9000_data(_info) container_of(_info, struct ucd9000_data, info) + +struct ucd9000_debugfs_entry { + struct i2c_client *client; + u8 index; +}; + +static int wb_i2c_smbus_read_block_data(const struct i2c_client *client, u8 command, u8 *values) +{ + int rv, i; + + for(i = 0; i < UCD9000_RETRY_TIME; i++) { + rv = i2c_smbus_read_block_data(client, command, values); + if(rv >= 0){ + return rv; + } + usleep_range(UCD9000_RETRY_SLEEP_TIME, UCD9000_RETRY_SLEEP_TIME + 1); + } + WB_UDC9000_ERROR("read_block_data failed. nr:%d, addr:0x%x, reg:0x%x, rv:%d.", + client->adapter->nr, client->addr, command, rv); + return rv; +} + +static int ucd9000_get_fan_config(struct i2c_client *client, int fan) +{ + int fan_config = 0; + struct ucd9000_data *data + = to_ucd9000_data(wb_pmbus_get_driver_info(client)); + + if (data->fan_data[fan][3] & 1) + fan_config |= PB_FAN_2_INSTALLED; /* Use lower bit position */ + + /* Pulses/revolution */ + fan_config |= (data->fan_data[fan][3] & 0x06) >> 1; + + return fan_config; +} + +static int ucd9000_read_byte_data(struct i2c_client *client, int page, int reg) +{ + int ret = 0; + int fan_config; + + switch (reg) { + case PMBUS_FAN_CONFIG_12: + if (page > 0) + return -ENXIO; + + ret = ucd9000_get_fan_config(client, 0); + if (ret < 0) + return ret; + fan_config = ret << 4; + ret = ucd9000_get_fan_config(client, 1); + if (ret < 0) + return ret; + fan_config |= ret; + ret = fan_config; + break; + case PMBUS_FAN_CONFIG_34: + if (page > 0) + return -ENXIO; + + ret = ucd9000_get_fan_config(client, 2); + if (ret < 0) + return ret; + fan_config = ret << 4; + ret = ucd9000_get_fan_config(client, 3); + if (ret < 0) + return ret; + fan_config |= ret; + ret = fan_config; + break; + default: + ret = -ENODATA; + break; + } + return ret; +} + +static const struct i2c_device_id ucd9000_id[] = { + {"wb_ucd9000", ucd9000}, + {"wb_ucd90120", ucd90120}, + {"wb_ucd90124", ucd90124}, + {"wb_ucd90160", ucd90160}, + {"wb_ucd90320", ucd90320}, + {"wb_ucd9090", ucd9090}, + {"wb_ucd90910", ucd90910}, + {} +}; +MODULE_DEVICE_TABLE(i2c, ucd9000_id); + +static const struct of_device_id __maybe_unused ucd9000_of_match[] = { + { + .compatible = "ti,wb_ucd9000", + .data = (void *)ucd9000 + }, + { + .compatible = "ti,wb_ucd90120", + .data = (void *)ucd90120 + }, + { + .compatible = "ti,wb_ucd90124", + .data = (void *)ucd90124 + }, + { + .compatible = "ti,wb_ucd90160", + .data = (void *)ucd90160 + }, + { + .compatible = "ti,wb_ucd90320", + .data = (void *)ucd90320 + }, + { + .compatible = "ti,wb_ucd9090", + .data = (void *)ucd9090 + }, + { + .compatible = "ti,wb_ucd90910", + .data = (void *)ucd90910 + }, + { }, +}; +MODULE_DEVICE_TABLE(of, ucd9000_of_match); + +#ifdef CONFIG_GPIOLIB +static int ucd9000_gpio_read_config(struct i2c_client *client, + unsigned int offset) +{ + int ret; + + /* No page set required */ + ret = i2c_smbus_write_byte_data(client, UCD9000_GPIO_SELECT, offset); + if (ret < 0) + return ret; + + return i2c_smbus_read_byte_data(client, UCD9000_GPIO_CONFIG); +} + +static int ucd9000_gpio_get(struct gpio_chip *gc, unsigned int offset) +{ + struct i2c_client *client = gpiochip_get_data(gc); + int ret; + + ret = ucd9000_gpio_read_config(client, offset); + if (ret < 0) + return ret; + + return !!(ret & UCD9000_GPIO_CONFIG_STATUS); +} + +static void ucd9000_gpio_set(struct gpio_chip *gc, unsigned int offset, + int value) +{ + struct i2c_client *client = gpiochip_get_data(gc); + int ret; + + ret = ucd9000_gpio_read_config(client, offset); + if (ret < 0) { + dev_dbg(&client->dev, "failed to read GPIO %d config: %d\n", + offset, ret); + return; + } + + if (value) { + if (ret & UCD9000_GPIO_CONFIG_STATUS) + return; + + ret |= UCD9000_GPIO_CONFIG_STATUS; + } else { + if (!(ret & UCD9000_GPIO_CONFIG_STATUS)) + return; + + ret &= ~UCD9000_GPIO_CONFIG_STATUS; + } + + ret |= UCD9000_GPIO_CONFIG_ENABLE; + + /* Page set not required */ + ret = i2c_smbus_write_byte_data(client, UCD9000_GPIO_CONFIG, ret); + if (ret < 0) { + dev_dbg(&client->dev, "Failed to write GPIO %d config: %d\n", + offset, ret); + return; + } + + ret &= ~UCD9000_GPIO_CONFIG_ENABLE; + + ret = i2c_smbus_write_byte_data(client, UCD9000_GPIO_CONFIG, ret); + if (ret < 0) + dev_dbg(&client->dev, "Failed to write GPIO %d config: %d\n", + offset, ret); +} + +static int ucd9000_gpio_get_direction(struct gpio_chip *gc, + unsigned int offset) +{ + struct i2c_client *client = gpiochip_get_data(gc); + int ret; + + ret = ucd9000_gpio_read_config(client, offset); + if (ret < 0) + return ret; + + return !(ret & UCD9000_GPIO_CONFIG_OUT_ENABLE); +} + +static int ucd9000_gpio_set_direction(struct gpio_chip *gc, + unsigned int offset, bool direction_out, + int requested_out) +{ + struct i2c_client *client = gpiochip_get_data(gc); + int ret, config, out_val; + + ret = ucd9000_gpio_read_config(client, offset); + if (ret < 0) + return ret; + + if (direction_out) { + out_val = requested_out ? UCD9000_GPIO_CONFIG_OUT_VALUE : 0; + + if (ret & UCD9000_GPIO_CONFIG_OUT_ENABLE) { + if ((ret & UCD9000_GPIO_CONFIG_OUT_VALUE) == out_val) + return 0; + } else { + ret |= UCD9000_GPIO_CONFIG_OUT_ENABLE; + } + + if (out_val) + ret |= UCD9000_GPIO_CONFIG_OUT_VALUE; + else + ret &= ~UCD9000_GPIO_CONFIG_OUT_VALUE; + + } else { + if (!(ret & UCD9000_GPIO_CONFIG_OUT_ENABLE)) + return 0; + + ret &= ~UCD9000_GPIO_CONFIG_OUT_ENABLE; + } + + ret |= UCD9000_GPIO_CONFIG_ENABLE; + config = ret; + + /* Page set not required */ + ret = i2c_smbus_write_byte_data(client, UCD9000_GPIO_CONFIG, config); + if (ret < 0) + return ret; + + config &= ~UCD9000_GPIO_CONFIG_ENABLE; + + return i2c_smbus_write_byte_data(client, UCD9000_GPIO_CONFIG, config); +} + +static int ucd9000_gpio_direction_input(struct gpio_chip *gc, + unsigned int offset) +{ + return ucd9000_gpio_set_direction(gc, offset, UCD9000_GPIO_INPUT, 0); +} + +static int ucd9000_gpio_direction_output(struct gpio_chip *gc, + unsigned int offset, int val) +{ + return ucd9000_gpio_set_direction(gc, offset, UCD9000_GPIO_OUTPUT, + val); +} + +static void ucd9000_probe_gpio(struct i2c_client *client, + const struct i2c_device_id *mid, + struct ucd9000_data *data) +{ + int rc; + + switch (mid->driver_data) { + case ucd9090: + data->gpio.ngpio = UCD9090_NUM_GPIOS; + break; + case ucd90120: + case ucd90124: + case ucd90160: + data->gpio.ngpio = UCD901XX_NUM_GPIOS; + break; + case ucd90320: + data->gpio.ngpio = UCD90320_NUM_GPIOS; + break; + case ucd90910: + data->gpio.ngpio = UCD90910_NUM_GPIOS; + break; + default: + return; /* GPIO support is optional. */ + } + + /* + * Pinmux support has not been added to the new gpio_chip. + * This support should be added when possible given the mux + * behavior of these IO devices. + */ + data->gpio.label = client->name; + data->gpio.get_direction = ucd9000_gpio_get_direction; + data->gpio.direction_input = ucd9000_gpio_direction_input; + data->gpio.direction_output = ucd9000_gpio_direction_output; + data->gpio.get = ucd9000_gpio_get; + data->gpio.set = ucd9000_gpio_set; + data->gpio.can_sleep = true; + data->gpio.base = -1; + data->gpio.parent = &client->dev; + + rc = devm_gpiochip_add_data(&client->dev, &data->gpio, client); + if (rc) + dev_warn(&client->dev, "Could not add gpiochip: %d\n", rc); +} +#else +static void ucd9000_probe_gpio(struct i2c_client *client, + const struct i2c_device_id *mid, + struct ucd9000_data *data) +{ +} +#endif /* CONFIG_GPIOLIB */ + +#ifdef CONFIG_DEBUG_FS +static int ucd9000_get_mfr_status(struct i2c_client *client, u8 *buffer) +{ + int ret = wb_pmbus_set_page(client, 0, 0xff); + + if (ret < 0) + return ret; + + return wb_i2c_smbus_read_block_data(client, UCD9000_MFR_STATUS, buffer); +} + +static int ucd9000_debugfs_show_mfr_status_bit(void *data, u64 *val) +{ + struct ucd9000_debugfs_entry *entry = data; + struct i2c_client *client = entry->client; + u8 buffer[I2C_SMBUS_BLOCK_MAX]; + int ret, i; + + ret = ucd9000_get_mfr_status(client, buffer); + if (ret < 0) + return ret; + + /* + * GPI fault bits are in sets of 8, two bytes from end of response. + */ + i = ret - 3 - entry->index / 8; + if (i >= 0) + *val = !!(buffer[i] & BIT(entry->index % 8)); + + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(ucd9000_debugfs_mfr_status_bit, + ucd9000_debugfs_show_mfr_status_bit, NULL, "%1lld\n"); + +static ssize_t ucd9000_debugfs_read_mfr_status(struct file *file, + char __user *buf, size_t count, + loff_t *ppos) +{ + struct i2c_client *client = file->private_data; + u8 buffer[I2C_SMBUS_BLOCK_MAX]; + char str[(I2C_SMBUS_BLOCK_MAX * 2) + 2]; + char *res; + int rc; + + rc = ucd9000_get_mfr_status(client, buffer); + if (rc < 0) + return rc; + + res = bin2hex(str, buffer, min(rc, I2C_SMBUS_BLOCK_MAX)); + *res++ = '\n'; + *res = 0; + + return simple_read_from_buffer(buf, count, ppos, str, res - str); +} + +static const struct file_operations ucd9000_debugfs_show_mfr_status_fops = { + .llseek = noop_llseek, + .read = ucd9000_debugfs_read_mfr_status, + .open = simple_open, +}; + +static int ucd9000_init_debugfs(struct i2c_client *client, + const struct i2c_device_id *mid, + struct ucd9000_data *data) +{ + struct dentry *debugfs; + struct ucd9000_debugfs_entry *entries; + int i, gpi_count; + char name[UCD9000_DEBUGFS_NAME_LEN]; + + debugfs = wb_pmbus_get_debugfs_dir(client); + if (!debugfs) + return -ENOENT; + + data->debugfs = debugfs_create_dir(client->name, debugfs); + if (!data->debugfs) + return -ENOENT; + + /* + * Of the chips this driver supports, only the UCD9090, UCD90160, + * UCD90320, and UCD90910 report GPI faults in their MFR_STATUS + * register, so only create the GPI fault debugfs attributes for those + * chips. + */ + if (mid->driver_data == ucd9090 || mid->driver_data == ucd90160 || + mid->driver_data == ucd90320 || mid->driver_data == ucd90910) { + gpi_count = mid->driver_data == ucd90320 ? UCD90320_GPI_COUNT + : UCD9000_GPI_COUNT; + entries = devm_kcalloc(&client->dev, + gpi_count, sizeof(*entries), + GFP_KERNEL); + if (!entries) + return -ENOMEM; + + for (i = 0; i < gpi_count; i++) { + entries[i].client = client; + entries[i].index = i; + scnprintf(name, UCD9000_DEBUGFS_NAME_LEN, + "gpi%d_alarm", i + 1); + debugfs_create_file(name, 0444, data->debugfs, + &entries[i], + &ucd9000_debugfs_mfr_status_bit); + } + } + + scnprintf(name, UCD9000_DEBUGFS_NAME_LEN, "mfr_status"); + debugfs_create_file(name, 0444, data->debugfs, client, + &ucd9000_debugfs_show_mfr_status_fops); + + return 0; +} +#else +static int ucd9000_init_debugfs(struct i2c_client *client, + const struct i2c_device_id *mid, + struct ucd9000_data *data) +{ + return 0; +} +#endif /* CONFIG_DEBUG_FS */ + +static int ucd9000_probe(struct i2c_client *client) +{ + u8 block_buffer[I2C_SMBUS_BLOCK_MAX + 1]; + char wb_device_name[WB_DEV_NAME_MAX_LEN]; + struct ucd9000_data *data; + struct pmbus_driver_info *info; + const struct i2c_device_id *mid; + enum chips chip; + int i, ret; + + if (!i2c_check_functionality(client->adapter, + I2C_FUNC_SMBUS_BYTE_DATA | + I2C_FUNC_SMBUS_BLOCK_DATA)) + return -ENODEV; + + ret = wb_i2c_smbus_read_block_data(client, UCD9000_DEVICE_ID, + block_buffer); + if (ret < 0) { + dev_err(&client->dev, "Failed to read device ID\n"); + return ret; + } + block_buffer[ret] = '\0'; + dev_info(&client->dev, "Device ID %s\n", block_buffer); + + mem_clear(wb_device_name, sizeof(wb_device_name)); + snprintf(wb_device_name, sizeof(wb_device_name), "wb_%s", block_buffer); + + for (mid = ucd9000_id; mid->name[0]; mid++) { + if (!strncasecmp(mid->name, wb_device_name, strlen(mid->name))) + break; + } + if (!mid->name[0]) { + dev_err(&client->dev, "Unsupported device\n"); + return -ENODEV; + } + + if (client->dev.of_node) + chip = (enum chips)of_device_get_match_data(&client->dev); + else + chip = mid->driver_data; + + if (chip != ucd9000 && strcmp(client->name, mid->name) != 0) + dev_notice(&client->dev, + "Device mismatch: Configured %s, detected %s\n", + client->name, mid->name); + + data = devm_kzalloc(&client->dev, sizeof(struct ucd9000_data), + GFP_KERNEL); + if (!data) + return -ENOMEM; + info = &data->info; + + ret = i2c_smbus_read_byte_data(client, UCD9000_NUM_PAGES); + if (ret < 0) { + dev_err(&client->dev, + "Failed to read number of active pages\n"); + return ret; + } + info->pages = ret; + if (!info->pages) { + dev_err(&client->dev, "No pages configured\n"); + return -ENODEV; + } + + /* The internal temperature sensor is always active */ + info->func[0] = PMBUS_HAVE_TEMP; + + /* Everything else is configurable */ + ret = wb_i2c_smbus_read_block_data(client, UCD9000_MONITOR_CONFIG, + block_buffer); + if (ret <= 0) { + dev_err(&client->dev, "Failed to read configuration data\n"); + return -ENODEV; + } + for (i = 0; i < ret; i++) { + int page = UCD9000_MON_PAGE(block_buffer[i]); + + if (page >= info->pages) + continue; + + switch (UCD9000_MON_TYPE(block_buffer[i])) { + case UCD9000_MON_VOLTAGE: + case UCD9000_MON_VOLTAGE_HW: + info->func[page] |= PMBUS_HAVE_VOUT + | PMBUS_HAVE_STATUS_VOUT; + break; + case UCD9000_MON_TEMPERATURE: + info->func[page] |= PMBUS_HAVE_TEMP2 + | PMBUS_HAVE_STATUS_TEMP; + break; + case UCD9000_MON_CURRENT: + info->func[page] |= PMBUS_HAVE_IOUT + | PMBUS_HAVE_STATUS_IOUT; + break; + default: + break; + } + } + + /* Fan configuration */ + if (mid->driver_data == ucd90124) { + for (i = 0; i < UCD9000_NUM_FAN; i++) { + i2c_smbus_write_byte_data(client, + UCD9000_FAN_CONFIG_INDEX, i); + ret = wb_i2c_smbus_read_block_data(client, + UCD9000_FAN_CONFIG, + data->fan_data[i]); + if (ret < 0) + return ret; + } + i2c_smbus_write_byte_data(client, UCD9000_FAN_CONFIG_INDEX, 0); + + info->read_byte_data = ucd9000_read_byte_data; + info->func[0] |= PMBUS_HAVE_FAN12 | PMBUS_HAVE_STATUS_FAN12 + | PMBUS_HAVE_FAN34 | PMBUS_HAVE_STATUS_FAN34; + } + + ucd9000_probe_gpio(client, mid, data); + + ret = wb_pmbus_do_probe(client, info); + if (ret) + return ret; + + ret = ucd9000_init_debugfs(client, mid, data); + if (ret) + dev_warn(&client->dev, "Failed to register debugfs: %d\n", + ret); + + return 0; +} + +/* This is the driver that will be inserted */ +static struct i2c_driver ucd9000_driver = { + .driver = { + .name = "wb_ucd9000", + .of_match_table = of_match_ptr(ucd9000_of_match), + }, + .probe_new = ucd9000_probe, + .remove = wb_pmbus_do_remove, + .id_table = ucd9000_id, +}; + +module_i2c_driver(ucd9000_driver); + +MODULE_AUTHOR("support"); +MODULE_DESCRIPTION("PMBus driver for TI UCD90xxx"); +MODULE_LICENSE("GPL"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/lpc_cpld_i2c_ocores.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/lpc_cpld_i2c_ocores.c deleted file mode 100755 index e15bed475d2f..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/common/modules/lpc_cpld_i2c_ocores.c +++ /dev/null @@ -1,843 +0,0 @@ -/* - * i2c-ocores.c: I2C bus driver for OpenCores I2C controller - * (http://www.opencores.org/projects.cgi/web/i2c/overview). - * - * Peter Korsgaard - * - * Support for the GRLIB port of the controller by - * Andreas Larsson - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "lpc_cpld_i2c_ocores.h" -#include -#include -#include -#include - -#define OCORES_FLAG_POLL BIT(0) - -struct ocores_i2c { - void __iomem *base; - u32 reg_shift; - u32 reg_io_width; - unsigned long flags; - wait_queue_head_t wait; - struct i2c_adapter adap; - struct i2c_msg *msg; - int pos; - int nmsgs; - int state; /* see STATE_ */ - spinlock_t process_lock; - int clock_khz; - void (*setreg)(struct ocores_i2c *i2c, int reg, u8 value); - u8 (*getreg)(struct ocores_i2c *i2c, int reg); -}; - -/* registers */ -#define OCI2C_PRELOW 0x0 -#define OCI2C_PREHIGH 0x1 -#define OCI2C_CONTROL 0x2 -#define OCI2C_DATA 0x3 -#define OCI2C_CMD 0x4 /* write only */ -#define OCI2C_STATUS 0x4 /* read only, same address as OCI2C_CMD */ - -#define OCI2C_TRAN_REV 0x14 -#define OCI2C_CMD_REV 0x18 - - -#define OCI2C_CTRL_IEN 0x40 -#define OCI2C_CTRL_EN 0x80 - -#define OCI2C_CMD_START 0x91 -#define OCI2C_CMD_STOP 0x41 -#define OCI2C_CMD_READ 0x21 -#define OCI2C_CMD_WRITE 0x11 -#define OCI2C_CMD_READ_ACK 0x21 -#define OCI2C_CMD_READ_NACK 0x29 -#define OCI2C_CMD_IACK 0x01 - -#define OCI2C_STAT_IF 0x01 -#define OCI2C_STAT_TIP 0x02 -#define OCI2C_STAT_ARBLOST 0x20 -#define OCI2C_STAT_BUSY 0x40 -#define OCI2C_STAT_NACK 0x80 - -#define STATE_DONE 0 -#define STATE_START 1 -#define STATE_WRITE 2 -#define STATE_READ 3 -#define STATE_ERROR 4 - -#define TYPE_OCORES 0 -#define TYPE_GRLIB 1 -#define OCI2C_WAIT_SLEEP 40 - -int g_lpc_cpld_i2c_debug = 0; -int g_lpc_cpld_i2c_irq = 0; -int g_lpc_cpld_i2c_error = 0; - -module_param(g_lpc_cpld_i2c_debug, int, S_IRUGO | S_IWUSR); -module_param(g_lpc_cpld_i2c_error, int, S_IRUGO | S_IWUSR); -module_param(g_lpc_cpld_i2c_irq, int, S_IRUGO | S_IWUSR); - -int g_irq_dump_debug = 0; -module_param(g_irq_dump_debug, int, S_IRUGO | S_IWUSR); -#define LPC_CPLD_I2C_DEBUG_DUMP(fmt, args...) do { \ - if (g_irq_dump_debug) { \ - printk(KERN_ERR ""fmt, ## args); \ - } \ -} while (0) -int g_irq_invalid_cnt = 0; -module_param(g_irq_invalid_cnt, int, S_IRUGO | S_IWUSR); -#define LPC_CPLD_I2C_DEBUG_XFER(fmt, args...) do { \ - if (g_lpc_cpld_i2c_irq) { \ - printk(KERN_ERR "[LPC_CPLD_I2C_OCORES][XFER][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ - } \ -} while (0) - -#define LPC_CPLD_I2C_DEBUG_VERBOSE(fmt, args...) do { \ - if (g_lpc_cpld_i2c_debug) { \ - printk(KERN_ERR "[LPC_CPLD_I2C_OCORES][VER][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ - } \ -} while (0) - -#define LPC_CPLD_I2C_DEBUG_ERROR(fmt, args...) do { \ - if (g_lpc_cpld_i2c_error) { \ - printk(KERN_ERR "[LPC_CPLD_I2C_OCORES][ERR][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ - } \ -} while (0) - -static int g_lpc_cpld_i2c_irq_flag = 1; - -module_param(g_lpc_cpld_i2c_irq_flag, int, S_IRUGO | S_IWUSR); - -static void oc_debug_dump_reg(struct ocores_i2c *i2c); -static void oc_setreg_8(struct ocores_i2c *i2c, int reg, u8 value) -{ - u64 base = (u64)i2c->base; - - outb(value, (u16)base + reg); -} - -static inline u8 oc_getreg_8(struct ocores_i2c *i2c, int reg) -{ - u64 base = (u64)i2c->base; - - return inb((u16)base + reg); -} - -static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value) -{ - i2c->setreg(i2c, reg, value); -} - -static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg) -{ - u8 status; - - status = i2c->getreg(i2c, reg); - return status; -} - -#define LPC_CPLD_I2C_SPIN_LOCK(lock, flags) spin_lock_irqsave(&(lock), (flags)) -#define LPC_CPLD_I2C_SPIN_UNLOCK(lock, flags) spin_unlock_irqrestore(&(lock), (flags)) - -static void ocores_process(struct ocores_i2c *i2c, u8 stat) -{ - struct i2c_msg *msg = i2c->msg; - - LPC_CPLD_I2C_DEBUG_XFER("Enter nr %d.\n", i2c->adap.nr); - - /* - * If we spin here is because we are in timeout, so we are going - * to be in STATE_ERROR. See ocores_process_timeout() - */ - if ((i2c->state == STATE_DONE) || (i2c->state == STATE_ERROR)) { - /* stop has been sent */ - oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK); - wake_up(&i2c->wait); - LPC_CPLD_I2C_DEBUG_XFER("stop has been sent, exit.\n"); - goto out; - } - - /* error */ - if (stat & OCI2C_STAT_ARBLOST) { - i2c->state = STATE_ERROR; - oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); - LPC_CPLD_I2C_DEBUG_XFER("error, exit.\n"); - goto out; - } - - if ((i2c->state == STATE_START) || (i2c->state == STATE_WRITE)) { - i2c->state = - (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE; - - if (stat & OCI2C_STAT_NACK) { - i2c->state = STATE_ERROR; - oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); - LPC_CPLD_I2C_DEBUG_XFER("OCI2C_STAT_NACK, exit.\n"); - goto out; - } - } else - msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA); - - /* end of msg */ - if (i2c->pos == msg->len) { - LPC_CPLD_I2C_DEBUG_XFER("Enter end of msg.\n"); - i2c->nmsgs--; - i2c->msg++; - i2c->pos = 0; - msg = i2c->msg; - - if (i2c->nmsgs) { /* end? */ - /* send start */ - if (!(msg->flags & I2C_M_NOSTART)) { - u8 addr = (msg->addr << 1); - - if (msg->flags & I2C_M_RD) - addr |= 1; - - i2c->state = STATE_START; - - oc_setreg(i2c, OCI2C_DATA, addr); - oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START); - LPC_CPLD_I2C_DEBUG_XFER("send start, exit.\n"); - goto out; - } - - i2c->state = (msg->flags & I2C_M_RD) - ? STATE_READ : STATE_WRITE; - } else { - i2c->state = STATE_DONE; - oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); - LPC_CPLD_I2C_DEBUG_XFER("send OCI2C_CMD_STOP, exit.\n"); - goto out; - } - } - - if (i2c->state == STATE_READ) { - oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len-1) ? - OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK); - } else { - oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]); - oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE); - } - -out: - LPC_CPLD_I2C_DEBUG_XFER("normal, exit nr %d.\n", i2c->adap.nr); -} - -static irqreturn_t ocores_isr(int irq, void *dev_id) -{ - struct ocores_i2c *i2c = dev_id; - unsigned long flags; - u8 stat; - if (!i2c) { - return IRQ_NONE; - } - - LPC_CPLD_I2C_SPIN_LOCK(i2c->process_lock, flags); - stat = oc_getreg(i2c, OCI2C_STATUS); - - if (!(stat & OCI2C_STAT_IF)) { - g_irq_invalid_cnt++; - LPC_CPLD_I2C_SPIN_UNLOCK(i2c->process_lock, flags); - return IRQ_NONE; - } - - LPC_CPLD_I2C_DEBUG_XFER("Enter, irq %d nr %d addr 0x%x.\n", irq, i2c->adap.nr, i2c->msg->addr); - ocores_process(i2c, stat); - LPC_CPLD_I2C_DEBUG_XFER("Leave, irq %d nr %d addr 0x%x.\n", irq, i2c->adap.nr, i2c->msg->addr); - LPC_CPLD_I2C_SPIN_UNLOCK(i2c->process_lock, flags); - - return IRQ_HANDLED; -} - -/** - * Process timeout event - * @i2c: ocores I2C device instance - */ -static void ocores_process_timeout(struct ocores_i2c *i2c) -{ - unsigned long flags; - - LPC_CPLD_I2C_SPIN_LOCK(i2c->process_lock, flags); - i2c->state = STATE_ERROR; - oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); - mdelay(1); - LPC_CPLD_I2C_SPIN_UNLOCK(i2c->process_lock, flags); - -} - -/** - * Wait until something change in a given register - * @i2c: ocores I2C device instance - * @reg: register to query - * @mask: bitmask to apply on register value - * @val: expected result - * @timeout: timeout in jiffies - * - * Timeout is necessary to avoid to stay here forever when the chip - * does not answer correctly. - * - * Return: 0 on success, -ETIMEDOUT on timeout - */ -static int ocores_wait(struct ocores_i2c *i2c, - int reg, u8 mask, u8 val, - const unsigned long timeout) -{ - u8 status; - unsigned long j, jiffies_tmp; - unsigned int usleep; - usleep = OCI2C_WAIT_SLEEP; - j = jiffies + timeout; - while (1) { - jiffies_tmp = jiffies; - status = oc_getreg(i2c, reg); - - if ((status & mask) == val) - break; - - if (time_after(jiffies_tmp, j)) { - LPC_CPLD_I2C_DEBUG_XFER("STATUS timeout, mask[0x%x] val[0x%x] status[0x%x]\n", mask, val, status); - return -ETIMEDOUT; - } - usleep_range(usleep,usleep + 1); - } - return 0; -} - -/** - * Wait until is possible to process some data - * @i2c: ocores I2C device instance - * - * Used when the device is in polling mode (interrupts disabled). - * - * Return: 0 on success, -ETIMEDOUT on timeout - */ -static int ocores_poll_wait(struct ocores_i2c *i2c) -{ - u8 mask; - int err; - - if (i2c->state == STATE_DONE || i2c->state == STATE_ERROR) { - /* transfer is over */ - mask = OCI2C_STAT_BUSY; - } else { - /* on going transfer */ - mask = OCI2C_STAT_TIP; - udelay((8 * 1000) / i2c->clock_khz); - } - - /* - * once we are here we expect to get the expected result immediately - * so if after 1ms we timeout then something is broken. - */ - err = ocores_wait(i2c, OCI2C_STATUS, mask, 0, msecs_to_jiffies(100)); - if (err) { - LPC_CPLD_I2C_DEBUG_XFER("STATUS timeout, bit 0x%x did not clear in 1ms, err %d\n", mask, err); - } - - return err; -} - - -/** - * It handles an IRQ-less transfer - * @i2c: ocores I2C device instance - * - * Even if IRQ are disabled, the I2C OpenCore IP behavior is exactly the same - * (only that IRQ are not produced). This means that we can re-use entirely - * ocores_isr(), we just add our polling code around it. - * - * It can run in atomic context - */ -static int ocores_process_polling(struct ocores_i2c *i2c) -{ - irqreturn_t ret; - int err; - while (1) { - err = ocores_poll_wait(i2c); - if (err) { - i2c->state = STATE_ERROR; - break; /* timeout */ - } - - ret = ocores_isr(-1, i2c); - if (ret == IRQ_NONE) - break; /* all messages have been transfered */ - } - return err; -} - -static int ocores_xfer_core(struct ocores_i2c *i2c, - struct i2c_msg *msgs, int num, - bool polling) -{ - int ret; - unsigned long flags; - u8 ctrl; - - LPC_CPLD_I2C_DEBUG_XFER("Enter.polling %d\n", polling); - LPC_CPLD_I2C_SPIN_LOCK(i2c->process_lock, flags); - ctrl = oc_getreg(i2c, OCI2C_CONTROL); - if (polling) - oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~OCI2C_CTRL_IEN); - else - oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_IEN); - - i2c->msg = msgs; - i2c->pos = 0; - i2c->nmsgs = num; - i2c->state = STATE_START; - - oc_setreg(i2c, OCI2C_DATA, - (i2c->msg->addr << 1) | - ((i2c->msg->flags & I2C_M_RD) ? 1:0)); - - oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START); - LPC_CPLD_I2C_SPIN_UNLOCK(i2c->process_lock, flags); - - if (polling) { - ret = ocores_process_polling(i2c); - if (ret) { /* timeout */ - ocores_process_timeout(i2c); - return -ETIMEDOUT; - } - } else { - ret = wait_event_timeout(i2c->wait, - (i2c->state == STATE_ERROR) || - (i2c->state == STATE_DONE), HZ); - if (ret == 0) { - ocores_process_timeout(i2c); - return -ETIMEDOUT; - } - } - - return (i2c->state == STATE_DONE) ? num : -EIO; -} - -static int ocores_xfer_polling(struct i2c_adapter *adap, - struct i2c_msg *msgs, int num) -{ - LPC_CPLD_I2C_DEBUG_XFER("Enter.\n"); - return ocores_xfer_core(i2c_get_adapdata(adap), msgs, num, true); -} - -static int ocores_xfer(struct i2c_adapter *adap, - struct i2c_msg *msgs, int num) -{ - struct ocores_i2c *i2c = i2c_get_adapdata(adap); - - if (i2c->flags & OCORES_FLAG_POLL) - return ocores_xfer_polling(adap, msgs, num); - return ocores_xfer_core(i2c, msgs, num, false); -} - -static void ocores_init(struct ocores_i2c *i2c) -{ - int prescale; - u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL); - - LPC_CPLD_I2C_DEBUG_XFER("Enter.\n"); - spin_lock_init(&i2c->process_lock); - - /* make sure the device is disabled */ - oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN)); - - prescale = (i2c->clock_khz / (5*100)) - 1; - oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff); - oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8); - LPC_CPLD_I2C_DEBUG_VERBOSE("i2c->base 0x%p, i2c->clock_khz %d, prescale 0x%x.\n", i2c->base, i2c->clock_khz, prescale); - - /* Init the device */ - oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK); - oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_EN); -} - - -static u32 ocores_func(struct i2c_adapter *adap) -{ - return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; -} - -static const struct i2c_algorithm ocores_algorithm = { - .master_xfer = ocores_xfer, - .functionality = ocores_func, -}; - -static struct i2c_adapter ocores_adapter = { - .owner = THIS_MODULE, - .name = "rg-cpld-ocrore-i2c", - .class = I2C_CLASS_HWMON | I2C_CLASS_SPD | I2C_CLASS_DEPRECATED, - .algo = &ocores_algorithm, -}; - -static const struct of_device_id ocores_i2c_match[] = { - { - .compatible = "opencores,rg-cpld-ocrore-i2c", - .data = (void *)TYPE_OCORES, - }, - {}, -}; -MODULE_DEVICE_TABLE(of, ocores_i2c_match); - -#ifdef CONFIG_OF -/* Read and write functions for the GRLIB port of the controller. Registers are - * 32-bit big endian and the PRELOW and PREHIGH registers are merged into one - * register. The subsequent registers has their offset decreased accordingly. */ -static u8 oc_getreg_grlib(struct ocores_i2c *i2c, int reg) -{ - u32 rd; - int rreg = reg; - if (reg != OCI2C_PRELOW) - rreg--; - rd = ioread32be(i2c->base + (rreg << i2c->reg_shift)); - if (reg == OCI2C_PREHIGH) - return (u8)(rd >> 8); - else - return (u8)rd; -} - -static void oc_setreg_grlib(struct ocores_i2c *i2c, int reg, u8 value) -{ - u32 curr, wr; - int rreg = reg; - if (reg != OCI2C_PRELOW) - rreg--; - if (reg == OCI2C_PRELOW || reg == OCI2C_PREHIGH) { - curr = ioread32be(i2c->base + (rreg << i2c->reg_shift)); - if (reg == OCI2C_PRELOW) - wr = (curr & 0xff00) | value; - else - wr = (((u32)value) << 8) | (curr & 0xff); - } else { - wr = value; - } - iowrite32be(wr, i2c->base + (rreg << i2c->reg_shift)); -} - -static int ocores_i2c_of_probe(struct platform_device *pdev, - struct ocores_i2c *i2c) -{ - struct device_node *np = pdev->dev.of_node; - const struct of_device_id *match; - u32 val; - - LPC_CPLD_I2C_DEBUG_VERBOSE("Enter ocores_i2c_of_probe.\n"); - if (of_property_read_u32(np, "reg-shift", &i2c->reg_shift)) { - /* no 'reg-shift', check for deprecated 'regstep' */ - if (!of_property_read_u32(np, "regstep", &val)) { - if (!is_power_of_2(val)) { - dev_err(&pdev->dev, "invalid regstep %d\n", - val); - return -EINVAL; - } - i2c->reg_shift = ilog2(val); - dev_warn(&pdev->dev, - "regstep property deprecated, use reg-shift\n"); - } - } - - if (of_property_read_u32(np, "clock-frequency", &val)) { - dev_err(&pdev->dev, - "Missing required parameter 'clock-frequency'\n"); - return -ENODEV; - } - i2c->clock_khz = val / 1000; - - of_property_read_u32(pdev->dev.of_node, "reg-io-width", - &i2c->reg_io_width); - - match = of_match_node(ocores_i2c_match, pdev->dev.of_node); - if (match && (long)match->data == TYPE_GRLIB) { - dev_dbg(&pdev->dev, "GRLIB variant of i2c-ocores\n"); - i2c->setreg = oc_setreg_grlib; - i2c->getreg = oc_getreg_grlib; - } - - return 0; -} -#else -#define ocores_i2c_of_probe(pdev,i2c) -ENODEV -#endif - -static void oc_debug_dump_reg(struct ocores_i2c *i2c) -{ - if (i2c) { - LPC_CPLD_I2C_DEBUG_DUMP("base: %p.\n", i2c->base); - LPC_CPLD_I2C_DEBUG_DUMP("reg_shift: %d.\n", i2c->reg_shift); - LPC_CPLD_I2C_DEBUG_DUMP("reg_io_width: %d.\n", i2c->reg_io_width); - LPC_CPLD_I2C_DEBUG_DUMP("adap.nr: %d.\n", i2c->adap.nr); - LPC_CPLD_I2C_DEBUG_DUMP("msg: %p.\n", i2c->msg); - if (i2c->msg) { - LPC_CPLD_I2C_DEBUG_DUMP("msg->buf: %p.\n", i2c->msg->buf); - LPC_CPLD_I2C_DEBUG_DUMP("msg->addr: 0x%x.\n", i2c->msg->addr); - LPC_CPLD_I2C_DEBUG_DUMP("msg->flags: 0x%x.\n", i2c->msg->flags); - LPC_CPLD_I2C_DEBUG_DUMP("msg->len: %d.\n", i2c->msg->len); - } else { - LPC_CPLD_I2C_DEBUG_DUMP("msg: %p is null.\n", i2c->msg); - } - - LPC_CPLD_I2C_DEBUG_DUMP("pos: %d.\n", i2c->pos); - LPC_CPLD_I2C_DEBUG_DUMP("nmsgs: %d.\n", i2c->nmsgs); - LPC_CPLD_I2C_DEBUG_DUMP("state: %d.\n", i2c->state); - LPC_CPLD_I2C_DEBUG_DUMP("clock_khz: %d.\n", i2c->clock_khz); - LPC_CPLD_I2C_DEBUG_DUMP("setreg: %p.\n", i2c->setreg); - LPC_CPLD_I2C_DEBUG_DUMP("getreg: %p.\n", i2c->getreg); - if (i2c->getreg) { - LPC_CPLD_I2C_DEBUG_DUMP("OCI2C_PRELOW: 0x%02x.\n", oc_getreg(i2c, OCI2C_PRELOW)); - LPC_CPLD_I2C_DEBUG_DUMP("OCI2C_PREHIGH: 0x%02x.\n", oc_getreg(i2c, OCI2C_PREHIGH)); - LPC_CPLD_I2C_DEBUG_DUMP("OCI2C_CONTROL: 0x%02x.\n", oc_getreg(i2c, OCI2C_CONTROL)); - LPC_CPLD_I2C_DEBUG_DUMP("OCI2C_DATA: 0x%02x.\n", oc_getreg(i2c, OCI2C_DATA)); - LPC_CPLD_I2C_DEBUG_DUMP("OCI2C_CMD: 0x%02x.\n", oc_getreg(i2c, OCI2C_CMD)); - LPC_CPLD_I2C_DEBUG_DUMP("OCI2C_STATUS: 0x%02x.\n", oc_getreg(i2c, OCI2C_STATUS)); - } else { - LPC_CPLD_I2C_DEBUG_DUMP("getreg: %p is null.\n", i2c->getreg); - } - } else { - LPC_CPLD_I2C_DEBUG_DUMP("i2c %p is null.\n", i2c); - } -} - -void oc_debug_dump_reg_exception(void) -{ - int bus_beg, bus_end, bus; - struct i2c_adapter *adap; - struct ocores_i2c *adap_data; - - bus_beg = 1; - bus_end = 14; - for (bus = bus_beg; bus <= bus_end; bus++) { - adap = i2c_get_adapter(bus); - if (adap) { - adap_data = (struct ocores_i2c *)i2c_get_adapdata(adap); - if (adap_data) { - LPC_CPLD_I2C_DEBUG_DUMP("bus %d call oc_debug_dump_reg begin.\n", bus); - oc_debug_dump_reg(adap_data); - LPC_CPLD_I2C_DEBUG_DUMP("bus %d call oc_debug_dump_reg end.\n", bus); - } else { - LPC_CPLD_I2C_DEBUG_DUMP("bus %d i2c_get_adapdata null.\n", bus); - } - i2c_put_adapter(adap); - } else { - LPC_CPLD_I2C_DEBUG_DUMP("bus %d i2c_get_adapter null.\n", bus); - } - } -} - -static ssize_t show_oc_debug_value(struct device *dev, struct device_attribute *da, char *buf) -{ - oc_debug_dump_reg_exception(); - return 0; -} - -static SENSOR_DEVICE_ATTR(oc_debug, S_IRUGO | S_IWUSR, show_oc_debug_value, NULL, 0x15); - -static struct attribute *oc_debug_sysfs_attrs[] = { - &sensor_dev_attr_oc_debug.dev_attr.attr, - NULL -}; - -static const struct attribute_group oc_debug_sysfs_group = { - .attrs = oc_debug_sysfs_attrs, -}; - -static void oc_debug_sysfs_init(struct platform_device *pdev) -{ - int ret; - - ret = sysfs_create_group(&pdev->dev.kobj, &oc_debug_sysfs_group); - LPC_CPLD_I2C_DEBUG_VERBOSE("sysfs_create_group ret %d.\n", ret); - return; -} - -static void oc_debug_sysfs_exit(struct platform_device *pdev) -{ - sysfs_remove_group(&pdev->dev.kobj, (const struct attribute_group *)&oc_debug_sysfs_group); - LPC_CPLD_I2C_DEBUG_VERBOSE("sysfs_remove_group.\n"); - return; -} - -static int rg_ocores_i2c_probe(struct platform_device *pdev) -{ - struct ocores_i2c *i2c; - struct rg_ocores_cpld_i2c_platform_data *pdata; - struct resource *res; - int irq; - int ret; - int i; - - LPC_CPLD_I2C_DEBUG_VERBOSE("Enter.\n"); - - i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); - if (!i2c) { - LPC_CPLD_I2C_DEBUG_ERROR("devm_kzalloc failed.\n"); - return -ENOMEM; - } - res = platform_get_resource(pdev, IORESOURCE_IO, 0); - if (!res) { - LPC_CPLD_I2C_DEBUG_ERROR("can't fetch device resource info\n"); - return -ENOMEM; - } - - i2c->base = (void __iomem *)res->start; - LPC_CPLD_I2C_DEBUG_VERBOSE("i2c->base is %p., res->end[%d]\n", i2c->base, (int)res->end); - - pdata = dev_get_platdata(&pdev->dev); - if (pdata) { - i2c->reg_shift = pdata->reg_shift; - i2c->reg_io_width = pdata->reg_io_width; - i2c->clock_khz = pdata->clock_khz; - } else { - ret = ocores_i2c_of_probe(pdev, i2c); - if (ret) - return ret; - } - - LPC_CPLD_I2C_DEBUG_VERBOSE("data: shift[%d], width[%d], clock_khz[%d] i2c_irq_flag=%d\n", - pdata->reg_shift, pdata->reg_io_width, pdata->clock_khz, pdata->i2c_irq_flag); - - if (i2c->reg_io_width == 0) - i2c->reg_io_width = 1; /* Set to default value */ - - - if (!i2c->setreg || !i2c->getreg) { - switch (i2c->reg_io_width) { - case 1: - i2c->setreg = oc_setreg_8; - i2c->getreg = oc_getreg_8; - break; - default: - dev_err(&pdev->dev, "Unsupported I/O width (%d)\n", - i2c->reg_io_width); - return -EINVAL; - } - } - - init_waitqueue_head(&i2c->wait); - - irq = platform_get_irq(pdev, 0); - LPC_CPLD_I2C_DEBUG_VERBOSE("get irq %d, ENXIO[%d]", irq, ENXIO); - if (irq == -ENXIO) { - i2c->flags |= OCORES_FLAG_POLL; - } else if(g_lpc_cpld_i2c_irq_flag){ - ret = devm_request_irq(&pdev->dev, irq, ocores_isr, 0, - pdev->name, i2c); - if (ret) { - dev_err(&pdev->dev, "Cannot claim IRQ\n"); - } - - if(pdata->i2c_irq_flag) { - g_lpc_cpld_i2c_irq_flag = 0; - } - } - - ocores_init(i2c); - - /* hook up driver to tree */ - platform_set_drvdata(pdev, i2c); - i2c->adap = ocores_adapter; - i2c_set_adapdata(&i2c->adap, i2c); - i2c->adap.dev.parent = &pdev->dev; - i2c->adap.dev.of_node = pdev->dev.of_node; - - /* add i2c adapter to i2c tree */ - ret = i2c_add_adapter(&i2c->adap); - if (ret) { - dev_err(&pdev->dev, "Failed to add adapter\n"); - return ret; - } - - /* add in known devices to the bus */ - if (pdata) { - LPC_CPLD_I2C_DEBUG_VERBOSE("i2c device %d.\n", pdata->num_devices); - for (i = 0; i < pdata->num_devices; i++) { -#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0) - i2c_new_client_device(&i2c->adap, pdata->devices + i); -#else - i2c_new_device(&i2c->adap, pdata->devices + i); -#endif - } - } - - oc_debug_sysfs_init(pdev); - return 0; -} - -static int rg_ocores_i2c_remove(struct platform_device *pdev) -{ - struct ocores_i2c *i2c = platform_get_drvdata(pdev); - - /* disable i2c logic */ - oc_setreg(i2c, OCI2C_CONTROL, oc_getreg(i2c, OCI2C_CONTROL) - & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN)); - - /* remove adapter & data */ - i2c_del_adapter(&i2c->adap); - oc_debug_sysfs_exit(pdev); - - return 0; -} - -#ifdef CONFIG_PM_SLEEP -static int ocores_i2c_suspend(struct device *dev) -{ - struct ocores_i2c *i2c = dev_get_drvdata(dev); - u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL); - - /* make sure the device is disabled */ - oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN)); - - return 0; -} - -static int ocores_i2c_resume(struct device *dev) -{ - struct ocores_i2c *i2c = dev_get_drvdata(dev); - - ocores_init(i2c); - - return 0; -} - -static SIMPLE_DEV_PM_OPS(ocores_i2c_pm, ocores_i2c_suspend, ocores_i2c_resume); -#define OCORES_I2C_PM (&ocores_i2c_pm) -#else -#define OCORES_I2C_PM NULL -#endif - -static struct platform_driver ocores_i2c_driver = { - .probe = rg_ocores_i2c_probe, - .remove = rg_ocores_i2c_remove, - .driver = { - .owner = THIS_MODULE, - .name = "rg-cpld-ocrore-i2c", - .of_match_table = ocores_i2c_match, - .pm = OCORES_I2C_PM, - }, -}; - -module_platform_driver(ocores_i2c_driver); - -MODULE_AUTHOR("Peter Korsgaard "); -MODULE_DESCRIPTION("OpenCores I2C bus driver"); -MODULE_LICENSE("GPL"); -MODULE_ALIAS("platform:ocores-i2c"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/lpc_cpld_i2c_ocores.h b/platform/broadcom/sonic-platform-modules-ragile/common/modules/lpc_cpld_i2c_ocores.h deleted file mode 100755 index baf6a916b11a..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/common/modules/lpc_cpld_i2c_ocores.h +++ /dev/null @@ -1,13 +0,0 @@ -#ifndef _LPC_CPLD_I2C_OCORES_H -#define _LPC_CPLD_I2C_OCORES_H - -struct rg_ocores_cpld_i2c_platform_data { - u32 reg_shift; /* register offset shift value */ - u32 reg_io_width; /* register io read/write width */ - u32 clock_khz; /* input clock in kHz */ - u8 num_devices; /* number of devices in the devices list */ - u8 i2c_irq_flag; - struct i2c_board_info const *devices; /* devices connected to the bus */ -}; - -#endif /* _LPC_CPLD_I2C_OCORES_H */ diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/lpc_dbg.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/lpc_dbg.c deleted file mode 100755 index 9c43bcee5c4a..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/common/modules/lpc_dbg.c +++ /dev/null @@ -1,534 +0,0 @@ -#include -#if LINUX_VERSION_CODE > KERNEL_VERSION(4, 19, 0) -#include -#endif - -#include -#include /* Wd're doing kernel work */ -#include /* specifically, a module */ -#include -#include /* Need for the macros */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "lpc_dbg.h" - -typedef struct rg_lpc_device_s { - u16 base; - u16 size; - u8 type; - u8 id; - u8 lpc_pci_addr; -} rg_lpc_device_t; - -typedef enum rg_lpc_dev_type_s { - LPC_DEVICE_CPLD = 1, - LPC_DEVICE_FPGA = 2, -} rg_lpc_dev_type_t; - -#define MAX_LPC_DEV_NUM (4) -#define LPC_PCI_CFG_BASE(__lgir) ((0x84) + ((__lgir) * 4)) -#define MAX_CPLD_REG_SIZE (0x100) -#define MAX_FPGA_REG_SIZE (0x100) //# fix compile actual value 0x10000 -#define LPC_GET_CPLD_ID(addr) ((addr >> 16) & 0xff) -#define LPC_GET_CPLD_OFFSET(addr) ((addr) & 0xff) - -int lpc_dbg_verbose = 0; -int lpc_dbg_error = 0; -int lpc_dbg_info = 0; -module_param(lpc_dbg_verbose, int, S_IRUGO | S_IWUSR); -module_param(lpc_dbg_error, int, S_IRUGO | S_IWUSR); -module_param(lpc_dbg_info, int, S_IRUGO | S_IWUSR); - - -#define LPC_DBG_VERBOSE(fmt, args...) do { \ - if (lpc_dbg_verbose) { \ - printk(KERN_ERR "[LPC_DBG][VERBOSE][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ - } \ -} while (0) - -#define LPC_DBG_ERROR(fmt, args...) do { \ - if (lpc_dbg_error) { \ - printk(KERN_ERR "[LPC_DBG][ERROR][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ - } \ -} while (0) - -#define LPC_DBG_INFO(fmt, args...) do { \ - if (lpc_dbg_info) { \ - printk(KERN_ERR ""fmt, ## args); \ - } \ -} while (0) - -static rg_lpc_device_t g_rg_lpc_dev_default[] = { - {.base = 0x700, .size = MAX_CPLD_REG_SIZE, .type = LPC_DEVICE_CPLD, .id = 0, .lpc_pci_addr = 0x84}, - {.base = 0x900, .size = MAX_CPLD_REG_SIZE, .type = LPC_DEVICE_CPLD, .id = 1, .lpc_pci_addr = 0x88}, - {.base = 0xb00, .size = MAX_CPLD_REG_SIZE, .type = LPC_DEVICE_CPLD, .id = 2, .lpc_pci_addr = 0x90}, -}; - -static rg_lpc_device_t *g_rg_lpc_dev = g_rg_lpc_dev_default; - -static rg_lpc_device_t* lpc_get_device_info(int type, int id) -{ - int i; - int size; - - size = ARRAY_SIZE(g_rg_lpc_dev_default); - for (i = 0; i < size; i++) { - if ((g_rg_lpc_dev[i].type == type) && (g_rg_lpc_dev[i].id == id)) { - return &g_rg_lpc_dev[i]; - } - } - - return NULL; -} - - -int lpc_cpld_read(int address, u8 *val) -{ - int cpld_id; - rg_lpc_device_t *info; - - cpld_id = LPC_GET_CPLD_ID(address); - info = lpc_get_device_info(LPC_DEVICE_CPLD, cpld_id); - if (info == NULL) { - LPC_DBG_ERROR("lpc_get_device_info addr 0x%x id %d failed.\r\n", address, cpld_id); - return -1; - } - - *val = inb(info->base + LPC_GET_CPLD_OFFSET(address)); - LPC_DBG_VERBOSE("Leave info->base 0x%x, addr 0x%x, cpld_id %d, val 0x%x.\r\n", info->base, address, cpld_id, *val); - return 0; -} - -int lpc_cpld_write(int address, u8 reg_val) -{ - int cpld_id; - rg_lpc_device_t *info; - - cpld_id = LPC_GET_CPLD_ID(address); - info = lpc_get_device_info(LPC_DEVICE_CPLD, cpld_id); - if (info == NULL) { - LPC_DBG_ERROR("lpc_get_device_info addr 0x%x id %d failed.\r\n", address, cpld_id); - return -1; - } - - outb(reg_val, info->base + LPC_GET_CPLD_OFFSET(address)); - LPC_DBG_VERBOSE("Leave info->base 0x%x, addr 0x%x, cpld_id %d, val 0x%x.\r\n", info->base, address, cpld_id, reg_val); - return 0; -} - -int lpc_fpga_read(int address, u8 *val) -{ - return -1; -} - -int lpc_fpga_write(int address, u8 reg_val) -{ - return -1; -} - -static ssize_t lpc_misc_cpld_dev_read (struct file *file, char __user *buf, size_t count, - loff_t *offset) -{ - int ret; - u8 value8[MAX_CPLD_REG_SIZE]; - int i; - - if ((count > MAX_CPLD_REG_SIZE) - || ((LPC_GET_CPLD_OFFSET(file->f_pos) + count) > MAX_CPLD_REG_SIZE)) { - return -EFAULT; - } - - for (i = 0; i < count; i++) { - ret = lpc_cpld_read((int)(file->f_pos + i), &value8[i]); - if (ret) { - LPC_DBG_ERROR("lpc_cpld_read i %d addr 0x%x failed ret %d.\n", - i, ((unsigned int)file->f_pos + i), ret); - return i; - } - } - - if (copy_to_user(buf, value8, count)) { - return -EFAULT; - } - - return count; -} - - -static ssize_t lpc_misc_cpld_dev_write (struct file *file, const char __user *buf, size_t count, - loff_t *offset) -{ - u8 value8[MAX_CPLD_REG_SIZE]; - int i; - int ret; - - if ((count > MAX_CPLD_REG_SIZE) - || ((LPC_GET_CPLD_OFFSET(file->f_pos) + count) > MAX_CPLD_REG_SIZE)) { - return -EFAULT; - } - - if (copy_from_user(value8, buf, count)) { - return -EFAULT; - } - - for (i = 0; i < count; i++) { - ret = lpc_cpld_write((int)(file->f_pos + i), value8[i]); - if (ret) { - LPC_DBG_ERROR("lpc_cpld_write i %d addr 0x%x value 0x%x failed ret %d.\n", - i, (unsigned int)file->f_pos + i, value8[i], ret); - return i; - } - } - - return count; -} - - -static loff_t lpc_misc_cpld_dev_llseek(struct file *file, loff_t offset, int origin) -{ - loff_t ret; - -#if LINUX_VERSION_CODE < KERNEL_VERSION(4,0,36) - mutex_lock(&file->f_path.dentry->d_inode->i_mutex); -#else - /* do noting add tjm */ - inode_lock(file_inode(file)); -#endif - - switch (origin) { - case 0: - file->f_pos = offset; - ret = file->f_pos; - break; - case 1: - file->f_pos += offset; - ret = file->f_pos; - break; - default: - ret = -EINVAL; - } - -#if LINUX_VERSION_CODE < KERNEL_VERSION(4,0,36) - mutex_unlock(&file->f_path.dentry->d_inode->i_mutex); -#else - /* do noting add tjm */ - inode_unlock(file_inode(file)); -#endif - - - return ret; -} - - -static long lpc_misc_cpld_dev_ioctl(struct file *file, unsigned int cmd, unsigned long arg) -{ - return -1; -} - -static int lpc_misc_cpld_dev_open(struct inode *inode, struct file *file) -{ - file->private_data = NULL; - file->f_pos = 0; - return 0; - -} - -static int lpc_misc_cpld_dev_release(struct inode *inode, struct file *file) -{ - file->private_data = NULL; - file->f_pos = 0; - return 0; -} - -static const struct file_operations lpc_misc_cpld_dev_fops = { - .owner = THIS_MODULE, - .llseek = lpc_misc_cpld_dev_llseek, - .read = lpc_misc_cpld_dev_read, - .write = lpc_misc_cpld_dev_write, - .unlocked_ioctl = lpc_misc_cpld_dev_ioctl, - .open = lpc_misc_cpld_dev_open, - .release = lpc_misc_cpld_dev_release, -}; - -static ssize_t lpc_misc_fpga_dev_read (struct file *file, char __user *buf, size_t count, - loff_t *offset) -{ - int ret; - u8 value8[MAX_FPGA_REG_SIZE]; - int i; - - if ((count > MAX_FPGA_REG_SIZE) || ((file->f_pos + count) > MAX_FPGA_REG_SIZE)) { - return -EFAULT; - } - - for (i = 0; i < count; i++) { - ret = lpc_fpga_read((int)(file->f_pos + i), &value8[i]); - if (ret) { - LPC_DBG_ERROR("lpc_fpga_read i %d addr 0x%x failed ret %d.\n", - i, ((unsigned int)file->f_pos + i), ret); - return i; - } - - } - - if (copy_to_user(buf, value8, count)) { - return -EFAULT; - } - - return count; -} - - -static ssize_t lpc_misc_fpga_dev_write (struct file *file, const char __user *buf, size_t count, - loff_t *offset) -{ - int ret; - u8 value8[MAX_FPGA_REG_SIZE]; - int i; - - if ((count > MAX_FPGA_REG_SIZE) || ((file->f_pos + count) > MAX_FPGA_REG_SIZE)) { - return -EFAULT; - } - - if (copy_from_user(value8, buf, count)) { - return -EFAULT; - } - - for (i = 0; i < count; i++) { - ret = lpc_fpga_write((int)(file->f_pos + i), value8[i]); - if (ret) { - LPC_DBG_ERROR("lpc_fpga_write i %d addr 0x%x value 0x%x failed ret %d.\n", - i, (int)(file->f_pos + i), value8[i], ret); - return i; - } - } - - return count; -} - - -static loff_t lpc_misc_fpga_dev_llseek(struct file *file, loff_t offset, int origin) -{ - loff_t ret; - -#if LINUX_VERSION_CODE < KERNEL_VERSION(4,0,36) - mutex_lock(&file->f_path.dentry->d_inode->i_mutex); -#else - /* do noting add tjm */ - inode_lock(file_inode(file)); -#endif - - switch (origin) { - case 0: - file->f_pos = offset; - ret = file->f_pos; - break; - case 1: - file->f_pos += offset; - ret = file->f_pos; - break; - default: - ret = -EINVAL; - } - -#if LINUX_VERSION_CODE < KERNEL_VERSION(4,0,36) - mutex_unlock(&file->f_path.dentry->d_inode->i_mutex); -#else - /* do noting add tjm */ - inode_unlock(file_inode(file)); -#endif - - - return ret; -} - - -static long lpc_misc_fpga_dev_ioctl(struct file *file, unsigned int cmd, unsigned long arg) -{ - return -1; -} - -static int lpc_misc_fpga_dev_open(struct inode *inode, struct file *file) -{ - file->private_data = NULL; - file->f_pos = 0; - return 0; - -} - -static int lpc_misc_fpga_dev_release(struct inode *inode, struct file *file) -{ - file->private_data = NULL; - file->f_pos = 0; - return 0; -} - -static const struct file_operations lpc_misc_fpga_dev_fops = { - .owner = THIS_MODULE, - .llseek = lpc_misc_fpga_dev_llseek, - .read = lpc_misc_fpga_dev_read, - .write = lpc_misc_fpga_dev_write, - .unlocked_ioctl = lpc_misc_fpga_dev_ioctl, - .open = lpc_misc_fpga_dev_open, - .release = lpc_misc_fpga_dev_release, -}; - -static struct miscdevice lpc_misc_cpld_dev = { - .minor = MISC_DYNAMIC_MINOR, - .name = "lpc_cpld", - .fops = &lpc_misc_cpld_dev_fops, -}; - -static struct miscdevice lpc_misc_fpga_dev = { - .minor = MISC_DYNAMIC_MINOR, - .name = "lpc_fpga", - .fops = &lpc_misc_fpga_dev_fops, -}; - -static int lpc_misc_drv_init(void) -{ - if (misc_register(&lpc_misc_cpld_dev) != 0) { - LPC_DBG_ERROR("Register %s failed.\r\n", lpc_misc_cpld_dev.name); - return -ENXIO; - } - - if (misc_register(&lpc_misc_fpga_dev) != 0) { - LPC_DBG_ERROR("Register %s failed.\r\n", lpc_misc_fpga_dev.name); - return -ENXIO; - } - return 0; -} - -static void lpc_misc_drv_exit(void) -{ - misc_deregister(&lpc_misc_cpld_dev); - misc_deregister(&lpc_misc_fpga_dev); -} - -#define LPC_MAKE_PCI_IO_RANGE(__base) ((0xfc0001) | ((__base) & (0xFFFC))) - -static int lpc_pci_cfg_init(struct pci_dev *pdev, - const struct pci_device_id *id) -{ - int i; - int size; - - size = ARRAY_SIZE(g_rg_lpc_dev_default); - - for (i = 0; i < size; i++) { - pci_write_config_dword(pdev, g_rg_lpc_dev[i].lpc_pci_addr, LPC_MAKE_PCI_IO_RANGE(g_rg_lpc_dev[i].base)); - LPC_DBG_VERBOSE("set lpc pci cfg[addr: 0x%x, value:0x%x].\n", LPC_PCI_CFG_BASE(i), LPC_MAKE_PCI_IO_RANGE(g_rg_lpc_dev[i].base)); - if (!request_region(g_rg_lpc_dev[i].base, g_rg_lpc_dev[i].size, "rg_lpc")) { - LPC_DBG_ERROR("request_region [0x%x][0x%x] failed!\n", g_rg_lpc_dev[i].base, g_rg_lpc_dev[i].size); - return -EBUSY; - } - } - - return 0; -} - -static void lpc_pci_cfg_exit(void) -{ - int i; - int size; - - size = ARRAY_SIZE(g_rg_lpc_dev_default); - for (i = 0; i < size; i++) { - release_region(g_rg_lpc_dev[i].base, g_rg_lpc_dev[i].size); - } - return; -} - -static int rg_lpc_cpld_probe(struct pci_dev *pdev, - const struct pci_device_id *id) -{ - int ret; - - LPC_DBG_VERBOSE("Enter.\n"); - ret = lpc_pci_cfg_init(pdev, id); - if (ret) { - LPC_DBG_ERROR("lpc_pci_cfg_init failed ret %d.\n", ret); - return ret; - } - - ret = lpc_misc_drv_init(); - if (ret) { - LPC_DBG_ERROR("lpc_misc_drv_init failed ret %d.\n", ret); - return ret; - } - LPC_DBG_VERBOSE("Leave success\n"); - - return 0; -} - -static void rg_lpc_cpld_remove(struct pci_dev *pdev) -{ - LPC_DBG_VERBOSE("Enter.\n"); - lpc_misc_drv_exit(); - lpc_pci_cfg_exit(); - LPC_DBG_VERBOSE("Leave.\n"); -} - - -#define PCI_VENDOR_ID_D1527_LPC (0x8c54) -#define PCI_VENDOR_ID_C3000_LPC (0x19dc) - -#if 0 -static const struct pci_device_id rg_lpc_cpld_pcidev_id[] = { - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_VENDOR_ID_C3000_LPC) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_VENDOR_ID_D1527_LPC) }, - { 0, } -}; -MODULE_DEVICE_TABLE(pci, rg_lpc_cpld_pcidev_id); - -static struct pci_driver rg_lpc_driver = { - .name = "rg_lpc", - .id_table = rg_lpc_cpld_pcidev_id, - .probe = rg_lpc_cpld_probe, - .remove = rg_lpc_cpld_remove, -}; - -module_pci_driver(rg_lpc_driver); -#else -static int __init lpc_dbg_init(void) -{ - struct pci_dev *pdev = NULL; - int ret; - - LPC_DBG_VERBOSE("Enter.\n"); - - pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_VENDOR_ID_D1527_LPC, pdev); - if (!pdev) { - LPC_DBG_ERROR("pci_get_device(0x8086, 0x8c54) failed!\n"); - return 0; - } - - ret = rg_lpc_cpld_probe(pdev, NULL); - LPC_DBG_VERBOSE("Leave ret %d.\n", ret); - return ret; -} - -static void __exit lpc_dbg_exit(void) -{ - LPC_DBG_VERBOSE("Enter.\n"); - rg_lpc_cpld_remove(NULL); - LPC_DBG_VERBOSE("Leave.\n"); -} - - - -module_init(lpc_dbg_init); -module_exit(lpc_dbg_exit); - -#endif -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("support "); - diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/lpc_dbg.h b/platform/broadcom/sonic-platform-modules-ragile/common/modules/lpc_dbg.h deleted file mode 100755 index d1aad9c90751..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/common/modules/lpc_dbg.h +++ /dev/null @@ -1,39 +0,0 @@ -#ifndef __ETH_CMD_TYPES_H__ -#define __ETH_CMD_TYPES_H__ - -typedef enum { - ETH_START = 1, - ETH_SHOW, - ETH_SET, - ETH_TEST, - ETH_MAC_REG, - ETH_PHY_REG, -} ether_dbg_top_cmd_t; - -typedef enum { - ETH_MAC_REG_READ = 1, - ETH_MAC_REG_WRITE, - ETH_MAC_REG_CHECK, - ETH_MAC_REG_DUMP_ALL, - ETH_MAC_REG_DUMP_PCI_CFG_ALL, -} ether_mac_reg_cmd_t; - - -#define ETH_DBG_TYPE(cmd1, cmd2, cmd3, cmd4) \ - ((cmd1) | ((cmd2) << 8) | ((cmd3) << 16) | ((cmd4) << 24)) -#define ETH_DBG_PARSE_TYPE(type, cmd1, cmd2, cmd3, cmd4) \ - do {\ - (cmd1) = (type) & 0xff;\ - (cmd2) = ((type) >> 8) & 0xff;\ - (cmd3) = ((type) >> 16) & 0xff;\ - (cmd4) = ((type) >> 24) & 0xff;\ - } while (0) - -typedef struct { - int type; - int length; - unsigned char value[128]; -} ether_msg_t; - - -#endif /* __ETH_CMD_TYPES_H__ */ diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/Makefile b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/Makefile new file mode 100644 index 000000000000..369b64605dd3 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/Makefile @@ -0,0 +1,20 @@ +pes_parent_dir:=$(shell pwd)/$(lastword $(MAKEFILE_LIST)) +pes_parent_dir:=$(shell dirname $(pes_parent_dir)) + +SUBDIRS=$(shell ls -l | grep ^d | awk '{if($$9 != "build") print $$9}') +INC = -I./inc + +all : CHECK $(SUBDIRS) +CHECK : + @echo $(pes_parent_dir) + +$(SUBDIRS):ECHO + #@echo $@ + make -C $@ + +ECHO: + @echo $(SUBDIRS) + +.PHONY : clean +clean : + -rm -rf $(SYSFS_OUT_PUT) diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/Makefile b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/Makefile new file mode 100644 index 000000000000..e516b70b3d92 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/Makefile @@ -0,0 +1,25 @@ +PWD = $(shell pwd) + +EXTRA_CFLAGS:= -I$(M)/include +EXTRA_CFLAGS+= -Wall +SUBDIR_CFG = cfg +plat_dfd-objs := dfd_module.o dfd_fan_driver.o \ +dfd_slot_driver.o \ +dfd_sensors_driver.o \ +dfd_psu_driver.o \ +dfd_sff_driver.o \ +$(SUBDIR_CFG)/dfd_cfg.o \ +$(SUBDIR_CFG)/dfd_cfg_adapter.o \ +$(SUBDIR_CFG)/dfd_cfg_file.o \ +$(SUBDIR_CFG)/dfd_cfg_info.o \ +$(SUBDIR_CFG)/dfd_cfg_listnode.o \ + +obj-m := plat_dfd.o +all: + $(MAKE) -C $(KERNEL_SRC)/build M=$(PWD) modules + @if [ ! -d $(module_out_put_dir) ]; then mkdir -p $(module_out_put_dir) ;fi + cp -p $(PWD)/*.ko $(module_out_put_dir) +clean: + rm -f $(PWD)/*.o $(PWD)/$(SUBDIR_CFG)/*.o $(PWD)/*.ko $(PWD)/*.mod.c $(PWD)/.*.cmd $(PWD)/$(SUBDIR_CFG)/.*.cmd $(PWD)/*.mod + rm -f $(PWD)/Module.markers $(PWD)/Module.symvers $(PWD)/modules.order + rm -rf $(PWD)/.tmp_versions diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/cfg/dfd_cfg.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/cfg/dfd_cfg.c new file mode 100644 index 000000000000..b0c9e9f6e723 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/cfg/dfd_cfg.c @@ -0,0 +1,812 @@ +#include +#include +#include +#include +#include +#include + +#include "../include/dfd_module.h" +#include "../include/dfd_cfg_file.h" +#include "../include/dfd_cfg_listnode.h" +#include "../include/dfd_cfg_info.h" +#include "../include/dfd_cfg_adapter.h" +#include "../include/dfd_cfg.h" +#include "../../dev_sysfs/include/sysfs_common.h" + +#ifdef DFD_CFG_ITEM +#undef DFD_CFG_ITEM +#endif +#define DFD_CFG_ITEM(_id, _name, _index_min, _index_max) _name, +static char *dfd_cfg_item_name[] = { + DFD_CFG_ITEM_ALL +}; + +#ifdef DFD_CFG_ITEM +#undef DFD_CFG_ITEM +#endif +#define DFD_CFG_ITEM(_id, _name, _index_min, _index_max) {_index_min, _index_max}, +static index_range_t dfd_cfg_item_index_range[] = { + DFD_CFG_ITEM_ALL +}; + +static lnode_root_t dfd_ko_cfg_list_root; + +static void dfd_ko_cfg_del_space_lf_cr(char *str) +{ + int i, j; + int len; + + len = strlen(str); + for (i = 0; i < len; i++) { + if (str[i] == '\r' || str[i] == '\n' || str[i] == ' ') { + for (j = i; j < len - 1; j++) { + str[j] = str[j + 1]; + } + str[j] = '\0'; + len--; + i--; + } + } +} + +static int dfd_ko_cfg_get_value_from_char(char *value_str, int32_t *value, int line_num) +{ + int value_tmp = 0; + + if (strlen(value_str) == 0) { + DBG_DEBUG(DBG_WARN, "line%d: value str is empty\n", line_num); + *value = DFD_CFG_EMPTY_VALUE; + return 0; + } + + if ((strlen(value_str) > 2) && (value_str[0] == '0') + && (value_str[1] == 'x' || value_str[1] == 'X')) { + value_tmp = (int32_t)simple_strtol(value_str, NULL, 16); + } else { + value_tmp = (int32_t)simple_strtol(value_str, NULL, 10); + } + + *value = value_tmp; + return 0; +} + +static int dfd_ko_cfg_analyse_index(char *index_str, int *index1, int *index2, int line_num) +{ + int rv; + char *index1_begin_char, *index2_begin_char; + + if (index_str[0] != '_') { + DBG_DEBUG(DBG_ERROR, "line%d: no '-' between name and index1\n", line_num); + return -1; + } + + index1_begin_char = index_str; + rv = dfd_ko_cfg_get_value_from_char(++index1_begin_char, index1, line_num); + if (rv < 0) { + return -1; + } + + if (index2 == NULL) { + return 0; + } + + index2_begin_char = strchr(index1_begin_char, '_'); + if (index2_begin_char == NULL) { + DBG_DEBUG(DBG_ERROR, "line%d: no '-' between index1 and index2\n", line_num); + return -1; + } else { + rv = dfd_ko_cfg_get_value_from_char(++index2_begin_char, index2, line_num); + if (rv < 0) { + return -1; + } + } + + return 0; +} + +static int dfd_ko_cfg_check_array_index(index_range_t *index_range, int *index1, int *index2, + int line_num) +{ + + if ((*index1 < 0) || (*index1 > index_range->index1_max)) { + DBG_DEBUG(DBG_ERROR, "line%d: index1[%d] invalid, max=%d\n", line_num, *index1, + index_range->index1_max); + return -1; + } + + if (index2 == NULL) { + return 0; + } + + if ((*index2 < 0) || (*index2 > index_range->index2_max)) { + DBG_DEBUG(DBG_ERROR, "line%d: index2[%d] invalid, max=%d\n", line_num, *index2, + index_range->index2_max); + return -1; + } + + return 0; +} + +static int dfd_ko_cfg_get_index(char *index_str, index_range_t *index_range, int *index1, + int *index2, int line_num) +{ + int rv; + + if (index_range->index2_max == INDEX_NOT_EXIST) { + index2 = NULL; + } + + rv = dfd_ko_cfg_analyse_index(index_str, index1, index2, line_num); + if (rv < 0) { + return -1; + } + + rv = dfd_ko_cfg_check_array_index(index_range, index1, index2, line_num); + if (rv < 0) { + return -1; + } + + return 0; +} + +static int dfd_ko_cfg_add_int_item(int key, int value, int line_num) +{ + int rv; + int *int_cfg; + + int_cfg = lnode_find_node(&dfd_ko_cfg_list_root, key); + if (int_cfg == NULL) { + + int_cfg = (int *)kmalloc(sizeof(int), GFP_KERNEL); + if (int_cfg == NULL) { + DBG_DEBUG(DBG_ERROR, "line%d: kmalloc int fail\n", line_num); + return -1; + } + + *int_cfg = value; + rv = lnode_insert_node(&dfd_ko_cfg_list_root, key, int_cfg); + if (rv == 0) { + DBG_DEBUG(DBG_VERBOSE, "line%d: add int item[%d] success, key=0x%08x\n", line_num, value, key); + } else { + kfree(int_cfg); + int_cfg = NULL; + DBG_DEBUG(DBG_ERROR, "line%d: add int item[%d] fail, key=0x%08x rv=%d \n", line_num, value, key, rv); + return -1; + } + } else { + + DBG_DEBUG(DBG_WARN, "line%d: replace int item[%d->%d], key=0x%08x\n", line_num, *int_cfg, value, key); + *int_cfg = value; + } + + return 0; +} + +static int dfd_ko_cfg_analyse_int_item(dfd_cfg_item_id_t cfg_item_id, char *arg_name, char *arg_value, + char *cfg_pre, index_range_t *index_range, int line_num) +{ + int rv; + int index1 = 0, index2 = 0; + int value, key; + char *arg_name_tmp; + + if (index_range->index1_max != INDEX_NOT_EXIST) { + arg_name_tmp = arg_name + strlen(cfg_pre); + rv = dfd_ko_cfg_get_index(arg_name_tmp, index_range, &index1, &index2, line_num); + if (rv < 0) { + return -1; + } + } + + rv = dfd_ko_cfg_get_value_from_char(arg_value, &value, line_num); + if (rv < 0) { + return -1; + } + + key = DFD_CFG_KEY(cfg_item_id, index1, index2); + rv = dfd_ko_cfg_add_int_item(key, value, line_num); + if (rv < 0) { + return -1; + } + + return 0; +} + +static int dfd_ko_cfg_add_str_item(int key, char *str, int line_num) +{ + int rv; + char *str_cfg; + + str_cfg = lnode_find_node(&dfd_ko_cfg_list_root, key); + if (str_cfg == NULL) { + + str_cfg = (char *)kmalloc(DFD_CFG_STR_MAX_LEN, GFP_KERNEL); + if (str_cfg == NULL) { + DBG_DEBUG(DBG_ERROR, "line%d: kmalloc str[%lu] fail\n", line_num, strlen(str)); + return -1; + } + mem_clear(str_cfg, DFD_CFG_STR_MAX_LEN); + strncpy(str_cfg, str, DFD_CFG_STR_MAX_LEN - 1); + + rv = lnode_insert_node(&dfd_ko_cfg_list_root, key, str_cfg); + if (rv == 0) { + DBG_DEBUG(DBG_VERBOSE, "line%d: add string item[%s] success, key=0x%08x\n", line_num, str_cfg, key); + } else { + kfree(str_cfg); + str_cfg = NULL; + DBG_DEBUG(DBG_ERROR, "line%d: add string item[%s] fail, key=0x%08x rv=%d \n", line_num, str_cfg, key, rv); + return -1; + } + } else { + DBG_DEBUG(DBG_WARN, "line%d: replace string item[%s->%s], key=0x%08x\n", line_num, str_cfg, str, key); + mem_clear(str_cfg, DFD_CFG_STR_MAX_LEN); + strncpy(str_cfg, str, DFD_CFG_STR_MAX_LEN - 1); + } + + return 0; +} + +static int dfd_ko_cfg_analyse_str_item(dfd_cfg_item_id_t cfg_item_id, char *arg_name, char *arg_value, + char *cfg_pre, index_range_t *index_range, int line_num) +{ + int rv; + int index1 = 0, index2 = 0; + int btree_key; + char *arg_name_tmp; + + if (index_range->index1_max != INDEX_NOT_EXIST) { + arg_name_tmp = arg_name + strlen(cfg_pre); + rv = dfd_ko_cfg_get_index(arg_name_tmp, index_range, &index1, &index2, line_num); + if (rv < 0) { + return -1; + } + } + + if (strlen(arg_value) >= DFD_CFG_STR_MAX_LEN) { + DBG_DEBUG(DBG_ERROR, "line%d: string item[%s] is too long \n", line_num, arg_value); + return -1; + } + + btree_key = DFD_CFG_KEY(cfg_item_id, index1, index2); + rv = dfd_ko_cfg_add_str_item(btree_key, arg_value, line_num); + if (rv < 0) { + return -1; + } + + return 0; +} + +static int dfd_ko_cfg_get_i2c_dev_member(char *member_str, dfd_i2c_dev_mem_t *member, int line_num) +{ + dfd_i2c_dev_mem_t mem_index; + + for (mem_index = DFD_I2C_DEV_MEM_BUS; mem_index < DFD_I2C_DEV_MEM_END; mem_index++) { + if (memcmp(member_str, g_dfd_i2c_dev_mem_str[mem_index], + strlen(g_dfd_i2c_dev_mem_str[mem_index])) == 0) { + *member = mem_index; + return 0; + } + } + + DBG_DEBUG(DBG_ERROR, "line%d: i2c dev member[%s] invalid\n", line_num, member_str); + return -1; +} + +static void dfd_ko_cfg_set_i2c_dev_mem_value(dfd_i2c_dev_t *i2c_dev, dfd_i2c_dev_mem_t member, + int value) +{ + switch (member) { + case DFD_I2C_DEV_MEM_BUS: + i2c_dev->bus = value; + break; + case DFD_I2C_DEV_MEM_ADDR: + i2c_dev->addr = value; + break; + default: + break; + } +} + +static int dfd_ko_cfg_add_i2c_dev_item(int key, dfd_i2c_dev_mem_t member, int value, int line_num) +{ + int rv; + dfd_i2c_dev_t *i2c_dev_cfg; + + i2c_dev_cfg = lnode_find_node(&dfd_ko_cfg_list_root, key); + if (i2c_dev_cfg == NULL) { + + i2c_dev_cfg = (dfd_i2c_dev_t *)kmalloc(sizeof(dfd_i2c_dev_t), GFP_KERNEL); + if (i2c_dev_cfg == NULL) { + DBG_DEBUG(DBG_ERROR, "line%d: kmalloc i2c_dev fail\n", line_num); + return -1; + } + mem_clear(i2c_dev_cfg, sizeof(dfd_i2c_dev_t)); + + dfd_ko_cfg_set_i2c_dev_mem_value(i2c_dev_cfg, member, value); + rv = lnode_insert_node(&dfd_ko_cfg_list_root, key, i2c_dev_cfg); + if (rv == 0) { + DBG_DEBUG(DBG_VERBOSE, "line%d: add i2c_dev item[%s=%d] success, key=0x%08x\n", line_num, + g_dfd_i2c_dev_mem_str[member], value, key); + } else { + kfree(i2c_dev_cfg); + i2c_dev_cfg = NULL; + DBG_DEBUG(DBG_ERROR, "line%d: add i2c_dev item[%s=%d] fail, key=0x%08x rv=%d\n", line_num, + g_dfd_i2c_dev_mem_str[member], value, key, rv); + return -1; + } + } else { + + DBG_DEBUG(DBG_VERBOSE, "line%d: replace i2c_dev item[%s=%d], key=0x%08x\n", line_num, + g_dfd_i2c_dev_mem_str[member], value, key); + dfd_ko_cfg_set_i2c_dev_mem_value(i2c_dev_cfg, member, value); + } + + return 0; +} + +static int dfd_ko_cfg_analyse_i2c_dev_item(dfd_cfg_item_id_t cfg_item_id, char *arg_name, + char *arg_value, char *cfg_pre, index_range_t *index_range, int line_num) +{ + int rv; + int index1 = 0, index2 = 0; + int value, key; + char *arg_name_tmp; + dfd_i2c_dev_mem_t member; + + arg_name_tmp = arg_name + strlen(cfg_pre); + rv = dfd_ko_cfg_get_i2c_dev_member(arg_name_tmp, &member, line_num); + if (rv < 0) { + return -1; + } + + if (index_range->index1_max != INDEX_NOT_EXIST) { + arg_name_tmp += strlen(g_dfd_i2c_dev_mem_str[member]); + rv = dfd_ko_cfg_get_index(arg_name_tmp, index_range, &index1, &index2, line_num); + if (rv < 0) { + return -1; + } + } + + rv = dfd_ko_cfg_get_value_from_char(arg_value, &value, line_num); + if (rv < 0) { + return -1; + } + + key = DFD_CFG_KEY(cfg_item_id, index1, index2); + rv = dfd_ko_cfg_add_i2c_dev_item(key, member, value, line_num); + if (rv < 0) { + return -1; + } + + return 0; +} + +static int dfd_ko_cfg_get_enum_value_by_str(char *enum_val_str[], int enum_val_end, char *buf) +{ + int i; + int enum_val; + + enum_val = DFD_CFG_INVALID_VALUE; + for (i = 0; i < enum_val_end; i++) { + if (memcmp(buf, enum_val_str[i], strlen(enum_val_str[i])) == 0) { + enum_val = i; + break; + } + } + + return enum_val; +} + +static int dfd_ko_cfg_get_info_ctrl_member(char *member_str, info_ctrl_mem_t *member, int line_num) +{ + info_ctrl_mem_t mem_index; + + for (mem_index = INFO_CTRL_MEM_MODE; mem_index < INFO_CTRL_MEM_END; mem_index++) { + if (memcmp(member_str, g_info_ctrl_mem_str[mem_index], + strlen(g_info_ctrl_mem_str[mem_index])) == 0) { + *member = mem_index; + return 0; + } + } + + DBG_DEBUG(DBG_ERROR, "line%d: info ctrl member[%s] invalid\n", line_num, member_str); + return -1; +} + +static void dfd_ko_cfg_set_info_ctrl_mem_value(info_ctrl_t *info_ctrl, info_ctrl_mem_t member, + char *buf_val, int line_num) +{ + switch (member) { + case INFO_CTRL_MEM_MODE: + info_ctrl->mode = dfd_ko_cfg_get_enum_value_by_str(g_info_ctrl_mode_str, INFO_CTRL_MODE_END, buf_val);; + break; + case INFO_CTRL_MEM_INT_CONS: + dfd_ko_cfg_get_value_from_char(buf_val, &(info_ctrl->int_cons), line_num); + break; + case INFO_CTRL_MEM_SRC: + info_ctrl->src = dfd_ko_cfg_get_enum_value_by_str(g_info_src_str, INFO_SRC_END, buf_val); + break; + case INFO_CTRL_MEM_FRMT: + info_ctrl->frmt = dfd_ko_cfg_get_enum_value_by_str(g_info_frmt_str, INFO_FRMT_END, buf_val); + break; + case INFO_CTRL_MEM_POLA: + info_ctrl->pola = dfd_ko_cfg_get_enum_value_by_str(g_info_pola_str, INFO_POLA_END, buf_val); + break; + case INFO_CTRL_MEM_FPATH: + mem_clear(info_ctrl->fpath, sizeof(info_ctrl->fpath)); + strncpy(info_ctrl->fpath, buf_val, sizeof(info_ctrl->fpath) - 1); + break; + case INFO_CTRL_MEM_ADDR: + dfd_ko_cfg_get_value_from_char(buf_val, &(info_ctrl->addr), line_num); + break; + case INFO_CTRL_MEM_LEN: + dfd_ko_cfg_get_value_from_char(buf_val, &(info_ctrl->len), line_num); + break; + case INFO_CTRL_MEM_BIT_OFFSET: + dfd_ko_cfg_get_value_from_char(buf_val, &(info_ctrl->bit_offset), line_num); + break; + case INFO_CTRL_MEM_STR_CONS: + mem_clear(info_ctrl->str_cons, sizeof(info_ctrl->str_cons)); + strncpy(info_ctrl->str_cons, buf_val, sizeof(info_ctrl->str_cons) - 1); + break; + case INFO_CTRL_MEM_INT_EXTRA1: + dfd_ko_cfg_get_value_from_char(buf_val, &(info_ctrl->int_extra1), line_num); + break; + case INFO_CTRL_MEM_INT_EXTRA2: + dfd_ko_cfg_get_value_from_char(buf_val, &(info_ctrl->int_extra2), line_num); + break; + default: + break; + } +} + +static int dfd_ko_cfg_add_info_ctrl_item(int key, info_ctrl_mem_t member, char *buf_val, + int line_num) +{ + int rv; + info_ctrl_t *info_ctrl_cfg; + + info_ctrl_cfg = lnode_find_node(&dfd_ko_cfg_list_root, key); + if (info_ctrl_cfg == NULL) { + + info_ctrl_cfg = (info_ctrl_t *)kmalloc(sizeof(info_ctrl_t), GFP_KERNEL); + if (info_ctrl_cfg == NULL) { + DBG_DEBUG(DBG_ERROR, "line%d: kmalloc info_ctrl fail\n", line_num); + return -1; + } + mem_clear(info_ctrl_cfg, sizeof(info_ctrl_t)); + + dfd_ko_cfg_set_info_ctrl_mem_value(info_ctrl_cfg, member, buf_val, line_num); + rv = lnode_insert_node(&dfd_ko_cfg_list_root, key, info_ctrl_cfg); + if (rv == 0) { + DBG_DEBUG(DBG_VERBOSE, "line%d: add info_ctrl item[%s=%s] success, key=0x%08x\n", line_num, + g_info_ctrl_mem_str[member], buf_val, key); + } else { + kfree(info_ctrl_cfg); + info_ctrl_cfg = NULL; + DBG_DEBUG(DBG_ERROR, "line%d: add info_ctrl item[%s=%s] fail, key=0x%08x rv=%d\n", line_num, + g_info_ctrl_mem_str[member], buf_val, key, rv); + return -1; + } + } else { + + DBG_DEBUG(DBG_VERBOSE, "line%d: replace info_ctrl item[%s=%s], key=0x%08x\n", line_num, + g_info_ctrl_mem_str[member], buf_val, key); + dfd_ko_cfg_set_info_ctrl_mem_value(info_ctrl_cfg, member, buf_val, line_num); + } + + return 0; +} + +static int dfd_ko_cfg_analyse_info_ctrl_item(dfd_cfg_item_id_t cfg_item_id, char *arg_name, + char *arg_value, char *cfg_pre, index_range_t *index_range, int line_num) +{ + int rv; + int index1 = 0, index2 = 0; + int key; + char *arg_name_tmp; + info_ctrl_mem_t member; + + arg_name_tmp = arg_name + strlen(cfg_pre); + rv = dfd_ko_cfg_get_info_ctrl_member(arg_name_tmp, &member, line_num); + if (rv < 0) { + return -1; + } + + if (index_range->index1_max != INDEX_NOT_EXIST) { + arg_name_tmp += strlen(g_info_ctrl_mem_str[member]); + rv = dfd_ko_cfg_get_index(arg_name_tmp, index_range, &index1, &index2, line_num); + if (rv < 0) { + return -1; + } + } + + key = DFD_CFG_KEY(cfg_item_id, index1, index2); + rv = dfd_ko_cfg_add_info_ctrl_item(key, member, arg_value, line_num); + if (rv < 0) { + return -1; + } + + return 0; +} + +static int dfd_ko_cfg_analyse_config(char *arg_name, char*arg_value, int line_num) +{ + int i, rv = 0; + int cfg_item_num; + + cfg_item_num = sizeof(dfd_cfg_item_name) / sizeof(dfd_cfg_item_name[0]); + for (i = 0; i < cfg_item_num; i++) { + if (memcmp(arg_name, dfd_cfg_item_name[i], strlen(dfd_cfg_item_name[i])) == 0){ + if (DFD_CFG_ITEM_IS_INT(i)) { + rv = dfd_ko_cfg_analyse_int_item(i, arg_name, arg_value, dfd_cfg_item_name[i], + &(dfd_cfg_item_index_range[i]), line_num); + } else if (DFD_CFG_ITEM_IS_STRING(i)) { + rv = dfd_ko_cfg_analyse_str_item(i, arg_name, arg_value, dfd_cfg_item_name[i], + &(dfd_cfg_item_index_range[i]), line_num); + } else if (DFD_CFG_ITEM_IS_I2C_DEV(i)) { + rv = dfd_ko_cfg_analyse_i2c_dev_item(i, arg_name, arg_value, dfd_cfg_item_name[i], + &(dfd_cfg_item_index_range[i]), line_num); + } else if (DFD_CFG_ITEM_IS_INFO_CTRL(i)) { + rv = dfd_ko_cfg_analyse_info_ctrl_item(i, arg_name, arg_value, dfd_cfg_item_name[i], + &(dfd_cfg_item_index_range[i]), line_num); + } else { + rv = -1; + } + break; + } + } + + return rv; +} + +static int dfd_ko_cfg_cut_config_line(char *config_line, char *arg_name, char *arg_value) +{ + int i, j = 0, k = 0; + int len, name_value_flag = 0; + + len = strlen(config_line); + for (i = 0; i < len; i++) { + if (config_line[i] == '=') { + name_value_flag = 1; + continue; + } + + if (name_value_flag == 0) { + arg_name[j++] = config_line[i]; + } else { + arg_value[k++] = config_line[i]; + } + } + + if (name_value_flag == 0) { + return -1; + } else { + return 0; + } +} + +static int dfd_ko_cfg_analyse_config_line(char *config_line, int line_num) +{ + int rv; + char arg_name[DFD_CFG_NAME_MAX_LEN] = {0}; + char arg_value[DFD_CFG_VALUE_MAX_LEN] = {0}; + + dfd_ko_cfg_del_space_lf_cr(config_line); + + if (strlen(config_line) == 0) { + DBG_DEBUG(DBG_VERBOSE, "line%d: space line\n", line_num); + return 0; + } + + if (config_line[0] == '#') { + DBG_DEBUG(DBG_VERBOSE, "line%d: comment line[%s]\n", line_num, config_line); + return 0; + } + + rv = dfd_ko_cfg_cut_config_line(config_line, arg_name, arg_value); + if (rv < 0) { + DBG_DEBUG(DBG_VERBOSE, "line%d: [%s]no '=' between name and value\n", line_num, config_line); + return -1; + } + + DBG_DEBUG(DBG_VERBOSE, "line%d: config_line[%s] name[%s] value[%s]\n", line_num, config_line, arg_name, arg_value); + return dfd_ko_cfg_analyse_config(arg_name, arg_value, line_num); +} + +static int dfd_ko_cfg_analyse_config_file(char *fpath) +{ + int rv; + int line_num = 1; + kfile_ctrl_t kfile_ctrl; + char config_line[DFD_CFG_CMDLINE_MAX_LEN] = {0}; + + rv = kfile_open(fpath, &kfile_ctrl); + if (rv != KFILE_RV_OK) { + DBG_DEBUG(DBG_ERROR, "open config file[%s] fail, rv=%d\n", fpath, rv); + return -1; + } + + while(kfile_gets(config_line, sizeof(config_line), &kfile_ctrl) > 0){ + rv = dfd_ko_cfg_analyse_config_line(config_line, line_num++); + if (rv < 0) { + DBG_DEBUG(DBG_ERROR, "!!!!file[%s] config line[%d %s] analyse fail\n", fpath, line_num - 1, + config_line); + break; + } + + (void)mem_clear(config_line, sizeof(config_line)); + + } + kfile_close(&kfile_ctrl); + + return rv; +} + +void *dfd_ko_cfg_get_item(int key) +{ + return lnode_find_node(&dfd_ko_cfg_list_root, key); +} + +static void dfd_ko_cfg_print_item(int key, const void *cfg) +{ + int item_id; + dfd_i2c_dev_t *i2c_dev; + info_ctrl_t *info_ctrl; + + if (cfg == NULL) { + DBG_DEBUG(DBG_ERROR, "input arguments error\n"); + return; + } + printk(KERN_INFO "**************************\n"); + printk(KERN_INFO "key=0x%08x\n", key); + + item_id = DFD_CFG_ITEM_ID(key); + if (DFD_CFG_ITEM_IS_INT(item_id)) { + printk(KERN_INFO "int=%d\n", *((int *)cfg)); + } else if (DFD_CFG_ITEM_IS_I2C_DEV(item_id)) { + i2c_dev = (dfd_i2c_dev_t *)cfg; + printk(KERN_INFO ".bus=0x%02x\n", i2c_dev->bus); + printk(KERN_INFO ".addr=0x%02x\n", i2c_dev->addr); + } else if (DFD_CFG_ITEM_IS_INFO_CTRL(item_id)) { + info_ctrl = (info_ctrl_t *)cfg; + printk(KERN_INFO ".mode=%s\n", g_info_ctrl_mode_str[info_ctrl->mode]); + printk(KERN_INFO ".int_cons=%d\n", info_ctrl->int_cons); + printk(KERN_INFO ".src=%s\n", g_info_src_str[info_ctrl->src]); + printk(KERN_INFO ".frmt=%s\n", g_info_frmt_str[info_ctrl->frmt]); + printk(KERN_INFO ".pola=%s\n", g_info_pola_str[info_ctrl->pola]); + printk(KERN_INFO ".fpath=%s\n", info_ctrl->fpath); + printk(KERN_INFO ".addr=0x%02x\n", info_ctrl->addr); + printk(KERN_INFO ".len=%d\n", info_ctrl->len); + printk(KERN_INFO ".bit_offset=%d\n", info_ctrl->bit_offset); + } else { + printk(KERN_INFO "item[%d] error!\n", item_id); + } +} + +void dfd_ko_cfg_show_item(int key) +{ + void *cfg; + + cfg = lnode_find_node(&dfd_ko_cfg_list_root, key); + if (cfg == 0) { + printk(KERN_INFO "item[0x%08x] not exist\n", key); + return; + } + + dfd_ko_cfg_print_item(key, cfg); +} + +static int dfd_get_my_dev_type_by_file(void) +{ + struct file *fp; + loff_t pos; + int card_type; + char buf[DFD_PID_BUF_LEN]; + int ret; + + fp= filp_open(DFD_PUB_CARDTYPE_FILE, O_RDONLY, 0); + if (IS_ERR(fp)) { + DBG_DEBUG(DBG_VERBOSE, "open file fail!\n"); + return -1; + } + mem_clear(buf, DFD_PID_BUF_LEN); + pos = 0; + ret = kernel_read(fp, buf, DFD_PRODUCT_ID_LENGTH + 1, &pos); + if (ret < 0) { + DBG_DEBUG(DBG_VERBOSE, "kernel_read failed, path=%s, addr=0, size=%d, ret=%d\n", + DFD_PUB_CARDTYPE_FILE, DFD_PRODUCT_ID_LENGTH + 1, ret); + filp_close(fp, NULL); + return -1; + } + + card_type = simple_strtoul(buf, NULL, 10); + DBG_DEBUG(DBG_VERBOSE, "card_type 0x%x.\n", card_type); + + filp_close(fp, NULL); + return card_type; +} + +static int drv_get_my_dev_type(void) +{ + static int type = -1; + + if (type > 0) { + return type; + } + type = dfd_get_my_dev_type_by_file(); + DBG_DEBUG(DBG_VERBOSE, "ko board type %d\n", type); + return type; +} + +static int dfd_ko_cfg_init(void) +{ + int rv; + int card_type; + char file_name[32] = {0}; + char fpath[128] = {0}; + kfile_ctrl_t kfile_ctrl; + + rv = lnode_init_root(&dfd_ko_cfg_list_root); + if (rv < 0) { + DBG_DEBUG(DBG_ERROR, "init list root fail, rv=%d\n", rv); + return -1; + } + + card_type = drv_get_my_dev_type(); + if (card_type > 0) { + snprintf(fpath, sizeof(fpath), "%s0x%x", DFD_KO_CFG_FILE_DIR, card_type); + rv = kfile_open(fpath, &kfile_ctrl); + if (rv != KFILE_RV_OK) { + DBG_DEBUG(DBG_VERBOSE, "open config file[%s] fail, rv=%d, maybe not exist\n", + fpath, rv); + + rv = kfile_open(DFD_KO_CFG_FILE_NAME, &kfile_ctrl); + if (rv != KFILE_RV_OK) { + DBG_DEBUG(DBG_ERROR, "open config file[%s] fail, rv=%d\n", DFD_KO_CFG_FILE_NAME, + rv); + return -1; + } + DBG_DEBUG(DBG_ERROR, "get config file from: %s, success.\n", DFD_KO_CFG_FILE_NAME); + } else { + DBG_DEBUG(DBG_VERBOSE, "get config file from: %s, success.\n", fpath); + } + } else { + DBG_DEBUG(DBG_VERBOSE, "get board id failed, try to get config file from: %s\n", + DFD_KO_CFG_FILE_NAME); + + rv = kfile_open(DFD_KO_CFG_FILE_NAME, &kfile_ctrl); + if (rv != KFILE_RV_OK) { + DBG_DEBUG(DBG_ERROR, "open config file[%s] fail, rv=%d\n", DFD_KO_CFG_FILE_NAME, rv); + return -1; + } + DBG_DEBUG(DBG_ERROR, "get config file from: %s, success.\n", DFD_KO_CFG_FILE_NAME); + } + + while (kfile_gets(file_name, sizeof(file_name), &kfile_ctrl) > 0) { + + dfd_ko_cfg_del_space_lf_cr(file_name); + mem_clear(fpath, sizeof(fpath)); + snprintf(fpath, sizeof(fpath), "%s%s.cfg", DFD_KO_CFG_FILE_DIR, file_name); + DBG_DEBUG(DBG_VERBOSE, ">>>>start parsing config file[%s]\n", fpath); + + rv = dfd_ko_cfg_analyse_config_file(fpath); + if (rv < 0) { + break; + } + } + kfile_close(&kfile_ctrl); + + return 0; +} + +int32_t dfd_dev_cfg_init(void) +{ + return dfd_ko_cfg_init(); +} + +void dfd_dev_cfg_exit(void) +{ + lnode_free_list(&dfd_ko_cfg_list_root); + return; +} diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/cfg/dfd_cfg_adapter.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/cfg/dfd_cfg_adapter.c new file mode 100644 index 000000000000..1d5ca7072f8f --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/cfg/dfd_cfg_adapter.c @@ -0,0 +1,351 @@ +#include +#include +#include +#include +#include +#include +#include + +#include "../include/dfd_module.h" +#include "../include/dfd_cfg_file.h" +#include "../include/dfd_cfg.h" +#include "../include/dfd_cfg_adapter.h" +#include "../../dev_sysfs/include/sysfs_common.h" + +char *g_dfd_i2c_dev_mem_str[DFD_I2C_DEV_MEM_END] = { + ".bus", + ".addr", +}; + +static dfd_i2c_dev_t* dfd_ko_get_cpld_i2c_dev(int sub_slot, int cpld_id) +{ + int key; + dfd_i2c_dev_t *i2c_dev; + + key = DFD_CFG_KEY(DFD_CFG_ITEM_CPLD_I2C_DEV, sub_slot, cpld_id); + i2c_dev = dfd_ko_cfg_get_item(key); + if (i2c_dev == NULL) { + DBG_DEBUG(DBG_ERROR, "get cpld[%d] i2c dev config fail, key=0x%08x\n", cpld_id, key); + return NULL; + } + + return i2c_dev; +} + +static int32_t dfd_ko_i2c_smbus_transfer(int read_write, int bus, int addr, int offset, uint8_t *buf, uint32_t size) +{ + int rv; + struct i2c_adapter *i2c_adap; + union i2c_smbus_data data; + + i2c_adap = i2c_get_adapter(bus); + if (i2c_adap == NULL) { + DBG_DEBUG(DBG_ERROR, "get i2c bus[%d] adapter fail\n", bus); + return -DFD_RV_DEV_FAIL; + } + + if (read_write == I2C_SMBUS_WRITE) { + data.byte = *buf; + } else { + data.byte = 0; + } + rv = i2c_smbus_xfer(i2c_adap, addr, 0, read_write, offset, I2C_SMBUS_BYTE_DATA, &data); + if (rv < 0) { + DBG_DEBUG(DBG_ERROR, "i2c dev[bus=%d addr=0x%x offset=0x%x size=%d rw=%d] transfer fail, rv=%d\n", + bus, addr, offset, size, read_write, rv); + rv = -DFD_RV_DEV_FAIL; + } else { + DBG_DEBUG(DBG_VERBOSE, "i2c dev[bus=%d addr=0x%x offset=0x%x size=%d rw=%d] transfer success\n", + bus, addr, offset, size, read_write); + rv = DFD_RV_OK; + } + + if (read_write == I2C_SMBUS_READ) { + if (rv == DFD_RV_OK) { + *buf = data.byte; + } else { + *buf = 0; + } + } + + i2c_put_adapter(i2c_adap); + return rv; +} + +static int32_t dfd_ko_i2c_read_data(int bus, int addr, int offset, uint8_t *buf, uint32_t size) +{ + int i, rv; + for (i = 0; i < DFD_KO_CPLD_I2C_RETRY_TIMES; i++) { + rv = dfd_ko_i2c_smbus_transfer(I2C_SMBUS_READ, bus, addr, offset, buf, size); + if (rv < 0) { + DBG_DEBUG(DBG_ERROR, "[%d]cpld read[offset=0x%x] fail, rv %d\n", i, addr, rv); + msleep(DFD_KO_CPLD_I2C_RETRY_SLEEP); + } else { + DBG_DEBUG(DBG_VERBOSE, "[%d]cpld read[offset=0x%x] success, value=0x%x\n", + i, addr, *buf); + break; + } + } + return rv; +} + +static int32_t dfd_ko_i2c_write_data(int bus, int addr, int offset, uint8_t data, uint32_t size) +{ + int i, rv; + for (i = 0; i < DFD_KO_CPLD_I2C_RETRY_TIMES; i++) { + rv = dfd_ko_i2c_smbus_transfer(I2C_SMBUS_WRITE, bus, addr, offset, &data, size); + if (rv < 0) { + DBG_DEBUG(DBG_ERROR, "[%d]cpld write[offset=0x%x] fail, rv=%d\n", i, addr, rv); + msleep(DFD_KO_CPLD_I2C_RETRY_SLEEP); + } else { + DBG_DEBUG(DBG_VERBOSE, "[%d]cpld write[offset=0x%x, data=%d] success\n", i, addr, data); + break; + } + } + + return rv; +} + +static int32_t dfd_ko_cpld_i2c_read(int32_t addr, uint8_t *buf) +{ + int rv; + int sub_slot, cpld_id, cpld_addr; + dfd_i2c_dev_t *i2c_dev; + + if (buf == NULL) { + DBG_DEBUG(DBG_ERROR, "input arguments error\n"); + return -DFD_RV_INDEX_INVALID; + } + + sub_slot = DFD_KO_CPLD_GET_SLOT(addr); + cpld_id = DFD_KO_CPLD_GET_ID(addr); + cpld_addr = DFD_KO_CPLD_GET_INDEX(addr); + + i2c_dev = dfd_ko_get_cpld_i2c_dev(sub_slot, cpld_id); + if (i2c_dev == NULL) { + return -DFD_RV_DEV_NOTSUPPORT; + } + rv = dfd_ko_i2c_read_data(i2c_dev->bus, i2c_dev->addr, cpld_addr, buf, sizeof(uint8_t)); + + return rv; +} + +static int32_t dfd_ko_cpld_i2c_write(int32_t addr, uint8_t data) +{ + int rv; + int sub_slot, cpld_id, cpld_addr; + dfd_i2c_dev_t *i2c_dev; + + sub_slot = DFD_KO_CPLD_GET_SLOT(addr); + cpld_id = DFD_KO_CPLD_GET_ID(addr); + cpld_addr = DFD_KO_CPLD_GET_INDEX(addr); + + i2c_dev = dfd_ko_get_cpld_i2c_dev(sub_slot, cpld_id); + if (i2c_dev == NULL) { + return -DFD_RV_DEV_NOTSUPPORT; + } + + rv = dfd_ko_i2c_write_data(i2c_dev->bus, i2c_dev->addr, cpld_addr, data, sizeof(uint8_t)); + + return rv; +} + +static int32_t dfd_ko_cpld_io_read(int32_t addr, uint8_t *buf) +{ + int cpld_id, sub_slot, offset; + int key; + int *tmp; + uint16_t io_port; + + sub_slot = DFD_KO_CPLD_GET_SLOT(addr); + cpld_id = DFD_KO_CPLD_GET_ID(addr); + offset = DFD_KO_CPLD_GET_INDEX(addr); + + key = DFD_CFG_KEY(DFD_CFG_ITEM_CPLD_LPC_DEV, sub_slot, cpld_id); + tmp = dfd_ko_cfg_get_item(key); + if (tmp == NULL) { + DBG_DEBUG(DBG_ERROR,"get cpld io base config fail, key=0x%08x\n", key); + return -1; + } + + io_port = (u16)(*tmp) + offset; + *buf = inb(io_port); + DBG_DEBUG(DBG_VERBOSE, "read cpld io port addr 0x%x, data 0x%x\n", io_port, *buf); + + return DFD_RV_OK; + +} + +static int32_t dfd_ko_cpld_io_write(int32_t addr, uint8_t data) +{ + int cpld_id, sub_slot, offset; + int key; + int *tmp; + uint16_t io_port; + + sub_slot = DFD_KO_CPLD_GET_SLOT(addr); + cpld_id = DFD_KO_CPLD_GET_ID(addr); + offset = DFD_KO_CPLD_GET_INDEX(addr); + + key = DFD_CFG_KEY(DFD_CFG_ITEM_CPLD_LPC_DEV, sub_slot, cpld_id); + tmp = dfd_ko_cfg_get_item(key); + if (tmp == NULL) { + DBG_DEBUG(DBG_ERROR, "get cpld io base config fail, key=0x%08x\n", key); + return -1; + } + + io_port = (u16)(*tmp) + offset; + DBG_DEBUG(DBG_VERBOSE, "write cpld io port addr 0x%x, data 0x%x\n", io_port, data); + outb(data, (u16)io_port); + + return DFD_RV_OK; +} + +static int dfd_cfg_get_cpld_mode(int sub_slot, int cpld_id, int *mode) +{ + int key; + char *name; + + if (mode == NULL) { + DBG_DEBUG(DBG_ERROR, "input arguments error\n"); + return -DFD_RV_TYPE_ERR; + } + + key = DFD_CFG_KEY(DFD_CFG_ITEM_CPLD_MODE, sub_slot, cpld_id); + name = dfd_ko_cfg_get_item(key); + if (name == NULL) { + DBG_DEBUG(DBG_ERROR, "get cpld[%d] mode info ctrl fail, key=0x%08x\n", cpld_id, key); + return -DFD_RV_NODE_FAIL; + } + + DBG_DEBUG(DBG_VERBOSE, "cpld_id %d mode_name %s.\n", cpld_id, name); + if (!strncmp(name, DFD_KO_CPLD_MODE_I2C_STRING, strlen(DFD_KO_CPLD_MODE_I2C_STRING))) { + *mode = DFD_CPLD_MODE_I2C; + } else if (!strncmp(name, DFD_KO_CPLD_MODE_LPC_STRING, strlen(DFD_KO_CPLD_MODE_LPC_STRING))) { + *mode = DFD_CPLD_MODE_LPC; + } else { + + *mode = DFD_CPLD_MODE_I2C; + } + + DBG_DEBUG(DBG_VERBOSE, "cpld_id %d mode %d.\n", cpld_id, *mode); + return 0; +} + +int32_t dfd_ko_cpld_read(int32_t addr, uint8_t *buf) +{ + int ret; + int sub_slot, cpld_id; + int cpld_mode; + + sub_slot = DFD_KO_CPLD_GET_SLOT(addr); + cpld_id = DFD_KO_CPLD_GET_ID(addr); + + ret = dfd_cfg_get_cpld_mode(sub_slot, cpld_id, &cpld_mode); + if (ret) { + DBG_DEBUG(DBG_WARN, "drv_get_cpld_mode sub_slot %d cpldid %d faile, set default i2c mode.\n", sub_slot, cpld_id); + cpld_mode = DFD_CPLD_MODE_I2C; + } + + if (cpld_mode == DFD_CPLD_MODE_I2C) { + ret = dfd_ko_cpld_i2c_read(addr, buf); + } else if (cpld_mode == DFD_CPLD_MODE_LPC) { + ret = dfd_ko_cpld_io_read(addr, buf); + } else { + DBG_DEBUG(DBG_ERROR, "cpld_mode %d invalid.\n", cpld_mode); + ret = -DFD_RV_DEV_NOTSUPPORT; + } + + DBG_DEBUG(DBG_VERBOSE, "addr 0x%x val 0x%x ret %d\n", addr, *buf, ret); + return ret; +} + +int32_t dfd_ko_cpld_write(int32_t addr, uint8_t val) +{ + int ret; + int sub_slot, cpld_id, cpld_mode; + + sub_slot = DFD_KO_CPLD_GET_SLOT(addr); + cpld_id = DFD_KO_CPLD_GET_ID(addr); + + ret = dfd_cfg_get_cpld_mode(sub_slot, cpld_id, &cpld_mode); + if (ret) { + DBG_DEBUG(DBG_ERROR, "drv_get_cpld_mode sub_slot %d cpldid %d faile, set default local_bus mode.\n", sub_slot, cpld_id); + cpld_mode = DFD_CPLD_MODE_I2C; + } + + if (cpld_mode == DFD_CPLD_MODE_I2C) { + ret = dfd_ko_cpld_i2c_write(addr, val); + } else if (cpld_mode == DFD_CPLD_MODE_LPC) { + ret = dfd_ko_cpld_io_write(addr, val); + } else { + DBG_DEBUG(DBG_ERROR, "cpld_mode %d invalid.\n", cpld_mode); + ret = -DFD_RV_DEV_NOTSUPPORT; + } + + DBG_DEBUG(DBG_VERBOSE, "addr 0x%x val 0x%x ret %d\n", addr, val, ret); + return ret; +} + +int32_t dfd_ko_i2c_read(int bus, int addr, int offset, uint8_t *buf, uint32_t size) +{ + int i, rv; + + for (i = 0; i < size; i++) { + rv = dfd_ko_i2c_read_data(bus, addr, offset, &buf[i], sizeof(uint8_t)); + if (rv < 0) { + DBG_DEBUG(DBG_ERROR, "dfd_ko_i2c_read[bus=%d addr=0x%x offset=0x%x]fail, rv=%d\n", + bus, addr, offset, rv); + return rv; + } + offset++; + } + + return size; +} + +int32_t dfd_ko_i2c_write(int bus, int addr, int offset, uint8_t *buf, uint32_t size) +{ + int i, rv; + + for (i = 0; i < size; i++) { + rv = dfd_ko_i2c_write_data(bus, addr, offset, buf[i], sizeof(uint8_t)); + if (rv < 0) { + DBG_DEBUG(DBG_ERROR, "dfd_ko_i2c_write[bus=%d addr=0x%x offset=0x%x]fail, rv=%d\n", + bus, addr, offset, rv); + return rv; + } + offset++; + } + + return size; + +} + +int32_t dfd_ko_read_file(char *fpath, int32_t addr, uint8_t *val, int32_t read_bytes) +{ + int32_t ret; + struct file *filp; + loff_t pos; + + if ((fpath == NULL) || (val == NULL) || (addr < 0) || (read_bytes < 0)) { + DBG_DEBUG(DBG_ERROR, "input arguments error, addr=%d read_bytes=%d\n", addr, read_bytes); + return -DFD_RV_INDEX_INVALID; + } + + filp = filp_open(fpath, O_RDONLY, 0); + if (IS_ERR(filp)){ + DBG_DEBUG(DBG_ERROR, "open file[%s] fail\n", fpath); + return -DFD_RV_DEV_FAIL; + } + + pos = addr; + ret = kernel_read(filp, val, read_bytes, &pos); + if (ret < 0) { + DBG_DEBUG(DBG_ERROR, "kernel_read failed, path=%s, addr=%d, size=%d, ret=%d\n", fpath, addr, read_bytes, ret); + ret = -DFD_RV_DEV_FAIL; + } + + filp_close(filp, NULL); + return ret; +} diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/cfg/dfd_cfg_file.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/cfg/dfd_cfg_file.c new file mode 100644 index 000000000000..8d77759ba7e0 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/cfg/dfd_cfg_file.c @@ -0,0 +1,236 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../include/dfd_cfg_file.h" +#include "../include/dfd_module.h" +#include "../../dev_sysfs/include/sysfs_common.h" + +struct getdents_callback { + struct dir_context ctx; + const char *obj_name; + char *match_name; + int dir_len; + int found; +}; + +int kfile_open(char *fname, kfile_ctrl_t *kfile_ctrl) +{ + int ret; + struct file *filp; + loff_t pos; + + if ((fname == NULL) || (kfile_ctrl == NULL)) { + return KFILE_RV_INPUT_ERR; + } + + filp = filp_open(fname, O_RDONLY, 0); + if (IS_ERR(filp)){ + return KFILE_RV_OPEN_FAIL; + } + + kfile_ctrl->size = filp->f_inode->i_size; + + kfile_ctrl->buf = kmalloc(kfile_ctrl->size, GFP_KERNEL); + if (kfile_ctrl->buf == NULL) { + ret = KFILE_RV_MALLOC_FAIL; + goto close_fp; + } + mem_clear(kfile_ctrl->buf, kfile_ctrl->size); + + pos = 0; + ret = kernel_read(filp, kfile_ctrl->buf, kfile_ctrl->size, &pos); + if (ret < 0) { + ret = KFILE_RV_RD_FAIL; + goto free_buf; + } + + kfile_ctrl->pos = 0; + + ret = KFILE_RV_OK; + goto close_fp; + +free_buf: + kfree(kfile_ctrl->buf); + kfile_ctrl->buf = NULL; + +close_fp: + filp_close(filp, NULL); + return ret; +} + +void kfile_close(kfile_ctrl_t *kfile_ctrl) +{ + if (kfile_ctrl == NULL) { + return; + } + + kfile_ctrl->size = 0; + kfile_ctrl->pos = 0; + if (kfile_ctrl->buf) { + kfree(kfile_ctrl->buf); + kfile_ctrl->buf = NULL; + } +} + +int kfile_gets(char *buf, int buf_size, kfile_ctrl_t *kfile_ctrl) +{ + int i; + int has_cr = 0; + + if ((buf == NULL) || (buf_size <= 0) || (kfile_ctrl == NULL) || (kfile_ctrl->buf == NULL) + || (kfile_ctrl->size <= 0)) { + return KFILE_RV_INPUT_ERR; + } + + mem_clear(buf, buf_size); + for (i = 0; i < buf_size; i++) { + + if (kfile_ctrl->pos >= kfile_ctrl->size) { + break; + } + + if (has_cr) { + break; + } + + if (IS_CR(kfile_ctrl->buf[kfile_ctrl->pos])) { + has_cr = 1; + } + + buf[i] = kfile_ctrl->buf[kfile_ctrl->pos]; + kfile_ctrl->pos++; + } + + return i; +} + +int kfile_read(int32_t addr, char *buf, int buf_size, kfile_ctrl_t *kfile_ctrl) +{ + int i; + + if ((buf == NULL) || (buf_size <= 0) || (kfile_ctrl == NULL) || (kfile_ctrl->buf == NULL) + || (kfile_ctrl->size <= 0)) { + return KFILE_RV_INPUT_ERR; + } + + if ((addr < 0) || (addr >= kfile_ctrl->size)) { + return KFILE_RV_ADDR_ERR; + } + + mem_clear(buf, buf_size); + + kfile_ctrl->pos = addr; + for (i = 0; i < buf_size; i++) { + + if (kfile_ctrl->pos >= kfile_ctrl->size) { + break; + } + + buf[i] = kfile_ctrl->buf[kfile_ctrl->pos]; + kfile_ctrl->pos++; + } + + return i; +} + +static int kfile_filldir_one(struct dir_context *ctx, const char * name, int len, + loff_t pos, u64 ino, unsigned int d_type) +{ + struct getdents_callback *buf ; + int result; + buf = container_of(ctx, struct getdents_callback, ctx); + result = 0; + if (strncmp(buf->obj_name, name, strlen(buf->obj_name)) == 0) { + if (buf->dir_len < len) { + DBG_DEBUG(DBG_ERROR, "match ok. dir name:%s, but buf_len %d small than dir len %d.\n", + name, buf->dir_len, len); + buf->found = 0; + return -1; + } + mem_clear(buf->match_name, buf->dir_len); + memcpy(buf->match_name, name, len); + buf->found = 1; + result = -1; + } + return result; +} + +int kfile_iterate_dir(const char *dir_path, const char *obj_name, char *match_name, int len) +{ + int ret; + struct file *dir; + struct getdents_callback buffer = { + .ctx.actor = kfile_filldir_one, + }; + + if(!dir_path || !obj_name || !match_name) { + DBG_DEBUG(DBG_ERROR, "params error. \n"); + return KFILE_RV_INPUT_ERR; + } + buffer.obj_name = obj_name; + buffer.match_name = match_name; + buffer.dir_len = len; + buffer.found = 0; + + dir = filp_open(dir_path, O_RDONLY, 0); + if (IS_ERR(dir)) { + DBG_DEBUG(DBG_ERROR, "filp_open error, dir path:%s\n", dir_path); + return KFILE_RV_OPEN_FAIL; + } + ret = iterate_dir(dir, &buffer.ctx); + if (buffer.found) { + DBG_DEBUG(DBG_VERBOSE, "match ok, dir name:%s\n", match_name); + filp_close(dir, NULL); + return DFD_RV_OK; + } + filp_close(dir, NULL); + return -DFD_RV_NODE_FAIL; +} + +#if 0 + +int kfile_write(char *fpath, int32_t addr, char *buf, int buf_size) +{ + int ret = KFILE_RV_OK; + struct file *filp; + mm_segment_t old_fs; + int wlen; + + if ((fpath == NULL) || (buf == NULL) || (buf_size <= 0)) { + return KFILE_RV_INPUT_ERR; + } + + if (addr < 0) { + return KFILE_RV_ADDR_ERR; + } + + filp = filp_open(fpath, O_RDWR, 0); + if (IS_ERR(filp)){ + return KFILE_RV_OPEN_FAIL; + } + + old_fs = get_fs(); + set_fs(KERNEL_DS); + + filp->f_op->llseek(filp,0,0); + filp->f_pos = addr; + + wlen = filp->f_op->write(filp, buf, buf_size, &(filp->f_pos)); + if (wlen < 0) { + ret = KFILE_RV_WR_FAIL; + } + + filp->f_op->llseek(filp,0,0); + set_fs(old_fs); + filp_close(filp, NULL); + + return ret; +} +#endif diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/cfg/dfd_cfg_info.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/cfg/dfd_cfg_info.c new file mode 100644 index 000000000000..5dae1539a116 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/cfg/dfd_cfg_info.c @@ -0,0 +1,587 @@ +#include +#include +#include + +#include "../include/dfd_module.h" +#include "../include/dfd_cfg_adapter.h" +#include "../include/dfd_cfg.h" +#include "../include/dfd_cfg_info.h" +#include "../include/dfd_cfg_file.h" +#include "../../dev_sysfs/include/sysfs_common.h" + +#define DFD_HWMON_NAME "hwmon" +#define DFD_GET_CPLD_VOLATGE_CODE_VALUE(value) ((value >> 4)& 0xfff) +#define DFD_GET_CPLD_VOLATGE_REAL_VALUE(code_val, k) ((code_val * 16 * 33 * k) / ((65536 - 5000) * 10)) + +char *g_info_ctrl_mem_str[INFO_CTRL_MEM_END] = { + ".mode", + ".int_cons", + ".src", + ".frmt", + ".pola", + ".fpath", + ".addr", + ".len", + ".bit_offset", + ".str_cons", + ".int_extra1", + ".int_extra2", +}; + +char *g_info_ctrl_mode_str[INFO_CTRL_MODE_END] = { + "none", + "config", + "constant", + "tlv", + "str_constant", +}; + +char *g_info_src_str[INFO_SRC_END] = { + "none", + "cpld", + "fpga", + "other_i2c", + "file", +}; + +char *g_info_frmt_str[INFO_FRMT_END] = { + "none", + "bit", + "byte", + "num_bytes", + "num_str", + "num_buf", + "buf", +}; + +char *g_info_pola_str[INFO_POLA_END] = { + "none", + "positive", + "negative", +}; + +static int dfd_read_info_from_cpld(int32_t addr, int read_bytes, uint8_t *val) +{ + int i, rv; + + for (i = 0; i < read_bytes; i++) { + rv = dfd_ko_cpld_read(addr, &(val[i])); + if (rv < 0) { + DBG_DEBUG(DBG_ERROR, "read info[addr=0x%x read_bytes=%d] from cpld fail, reading_byte=%d rv=%d\n", + addr, read_bytes, i, rv); + return rv; + } + addr++; + } + + return read_bytes; +} + +static int dfd_write_info_to_cpld(int32_t addr, int write_bytes, uint8_t *val, uint8_t bit_mask) +{ + int rv; + uint8_t val_tmp; + + if (bit_mask != 0xff) { + rv = dfd_ko_cpld_read(addr, &val_tmp); + if (rv < 0) { + DBG_DEBUG(DBG_ERROR, "read original info[addr=0x%x] from cpld fail, rv=%d\n", addr, rv); + return -1; + } + + val_tmp = (val_tmp & (~bit_mask)) | (val[0] & bit_mask); + } else { + val_tmp = val[0]; + } + + rv = dfd_ko_cpld_write(addr, val_tmp); + if (rv < 0) { + DBG_DEBUG(DBG_ERROR, "write info[addr=0x%x val=0x%x] to cpld fail, rv=%d\n", addr, val_tmp, rv); + return -1; + } + + return 0; +} + +static int dfd_read_info(info_src_t src, char *fpath, int32_t addr, int read_bytes, uint8_t *val) +{ + int rv = 0; + + switch (src) { + case INFO_SRC_CPLD: + rv = dfd_read_info_from_cpld(addr, read_bytes, val); + break; + case INFO_SRC_FPGA: + rv = -1; + DBG_DEBUG(DBG_ERROR, "not support read info from fpga\n"); + break; + case INFO_SRC_OTHER_I2C: + rv = -1; + DBG_DEBUG(DBG_ERROR, "not support read info from other i2c\n"); + break; + case INFO_SRC_FILE: + rv = dfd_ko_read_file(fpath, addr, val, read_bytes); + break; + default: + rv = -1; + DBG_DEBUG(DBG_ERROR, "info src[%d] error\n", src); + break; + } + + return rv; +} + +static int dfd_write_info(info_src_t src, char *fpath, int32_t addr, int write_bytes, uint8_t *val, uint8_t bit_mask) +{ + int rv = 0; + + switch (src) { + case INFO_SRC_CPLD: + rv = dfd_write_info_to_cpld(addr, write_bytes, val, bit_mask); + break; + case INFO_SRC_FPGA: + rv = -1; + DBG_DEBUG(DBG_ERROR, "not support write info to fpga\n"); + break; + case INFO_SRC_OTHER_I2C: + rv = -1; + DBG_DEBUG(DBG_ERROR, "not support write info to other i2c\n"); + break; + case INFO_SRC_FILE: + rv = -1; + DBG_DEBUG(DBG_ERROR, "not support write info to file\n"); + break; + default: + rv = -1; + DBG_DEBUG(DBG_ERROR, "info src[%d] error\n", src); + break; + } + + return rv; +} + +int dfd_info_get_int(int key, int *ret, info_num_buf_to_value_f pfun) +{ + int i, rv; + int read_bytes, readed_bytes, int_tmp; + uint8_t byte_tmp, val[INFO_INT_MAX_LEN + 1] = {0}; + info_ctrl_t *info_ctrl; + + if (!DFD_CFG_ITEM_IS_INFO_CTRL(DFD_CFG_ITEM_ID(key)) || (ret == NULL)) { + DBG_DEBUG(DBG_ERROR, "input arguments error, key=0x%08x\n", key); + return -DFD_RV_INDEX_INVALID; + } + + info_ctrl = dfd_ko_cfg_get_item(key); + if (info_ctrl == NULL) { + DBG_DEBUG(DBG_WARN, "get info ctrl fail, key=0x%08x\n", key); + return -DFD_RV_DEV_NOTSUPPORT; + } + + if (info_ctrl->mode == INFO_CTRL_MODE_CONS) { + *ret = info_ctrl->int_cons; + return DFD_RV_OK; + } else if (info_ctrl->mode == INFO_CTRL_MODE_TLV) { + return INFO_CTRL_MODE_TLV; + } + + if (IS_INFO_FRMT_BIT(info_ctrl->frmt)) { + + if (!INFO_BIT_OFFSET_VALID(info_ctrl->bit_offset)) { + DBG_DEBUG(DBG_ERROR, "info ctrl[key=0x%08x] bit_offsest[%d] invalid\n", + key, info_ctrl->bit_offset); + return -DFD_RV_TYPE_ERR; + } + + read_bytes = 1; + } else if (IS_INFO_FRMT_BYTE(info_ctrl->frmt) || IS_INFO_FRMT_NUM_STR(info_ctrl->frmt) + || IS_INFO_FRMT_NUM_BUF(info_ctrl->frmt)) { + + if (!INFO_INT_LEN_VALAID(info_ctrl->len)) { + DBG_DEBUG(DBG_ERROR, "info ctrl[key=0x%08x] len[%d] invalid\n", key, info_ctrl->len); + return -DFD_RV_TYPE_ERR; + } + read_bytes = info_ctrl->len; + } else { + DBG_DEBUG(DBG_ERROR, "info ctrl[key=0x%08x] info format[%d] error\n", key, info_ctrl->frmt); + return -DFD_RV_TYPE_ERR; + } + + readed_bytes = dfd_read_info(info_ctrl->src, info_ctrl->fpath, info_ctrl->addr, read_bytes, &(val[0])); + if (readed_bytes <= 0) { + DBG_DEBUG(DBG_ERROR, "read int info[key=0x%08x src=%s frmt=%s fpath=%s addr=0x%x read_bytes=%d] fail, rv=%d\n", + key, g_info_src_str[info_ctrl->src], g_info_frmt_str[info_ctrl->frmt], info_ctrl->fpath, + info_ctrl->addr, read_bytes, readed_bytes); + return -DFD_RV_DEV_FAIL; + } + + if (IS_INFO_FRMT_BIT(info_ctrl->frmt)) { + + if (info_ctrl->pola == INFO_POLA_NEGA) { + val[0] = ~val[0]; + } + + byte_tmp = (val[0] >> info_ctrl->bit_offset) & (~(0xff << info_ctrl->len)); + + if (pfun) { + rv = pfun(&byte_tmp, sizeof(byte_tmp), &int_tmp); + if (rv < 0) { + DBG_DEBUG(DBG_ERROR, "info ctrl[key=0x%08x] bit process fail, rv=%d\n", key, rv); + return rv; + } + } else { + int_tmp = (int)byte_tmp; + } + } else if (IS_INFO_FRMT_BYTE(info_ctrl->frmt)) { + + int_tmp = 0; + for (i = 0; i < info_ctrl->len; i++) { + if (info_ctrl->pola == INFO_POLA_NEGA) { + int_tmp |= val[info_ctrl->len - i - 1]; + } else { + int_tmp |= val[i]; + } + + if (i != (info_ctrl->len - 1)) { + int_tmp <<= 8; + } + } + } else if (IS_INFO_FRMT_NUM_STR(info_ctrl->frmt)) { + + val[readed_bytes] = '\0'; + int_tmp = simple_strtol((char *)(&(val[0])), NULL, 10); + } else { + if (pfun == NULL) { + DBG_DEBUG(DBG_ERROR, "info ctrl[key=0x%08x] number buf process function is null\n", key); + return -DFD_RV_INDEX_INVALID; + } + + rv = pfun(val, readed_bytes, &int_tmp); + if (rv < 0) { + DBG_DEBUG(DBG_ERROR, "info ctrl[key=0x%08x] number buf process fail, rv=%d\n", key, rv); + return rv; + } + } + + *ret = int_tmp; + DBG_DEBUG(DBG_VERBOSE, "read int info[key=0x%08x src=%s frmt=%s pola=%s fpath=%s addr=0x%x len=%d bit_offset=%d] success, ret=%d\n", + key, g_info_src_str[info_ctrl->src], g_info_frmt_str[info_ctrl->frmt], g_info_pola_str[info_ctrl->pola], + info_ctrl->fpath, info_ctrl->addr, info_ctrl->len, info_ctrl->bit_offset, *ret); + return DFD_RV_OK; +} + +int dfd_info_get_buf(int key, uint8_t *buf, int buf_len, info_buf_to_buf_f pfun) +{ + int rv; + int read_bytes, buf_real_len; + uint8_t buf_tmp[INFO_BUF_MAX_LEN]; + info_ctrl_t *info_ctrl; + + if (!DFD_CFG_ITEM_IS_INFO_CTRL(DFD_CFG_ITEM_ID(key)) || (buf == NULL)) { + DBG_DEBUG(DBG_ERROR, "input arguments error, key=0x%08x\n", key); + return -DFD_RV_INDEX_INVALID; + } + + info_ctrl = dfd_ko_cfg_get_item(key); + if (info_ctrl == NULL) { + DBG_DEBUG(DBG_WARN, "get info ctrl fail, key=0x%08x\n", key); + return -DFD_RV_DEV_NOTSUPPORT; + } + + if (info_ctrl->mode != INFO_CTRL_MODE_CFG) { + DBG_DEBUG(DBG_ERROR, "info ctrl[key=0x%08x] mode[%d] invalid\n", key, info_ctrl->mode); + return -DFD_RV_TYPE_ERR; + } + + if (!IS_INFO_FRMT_BUF(info_ctrl->frmt) || !INFO_BUF_LEN_VALAID(info_ctrl->len) + || (buf_len <= info_ctrl->len)) { + DBG_DEBUG(DBG_ERROR, "info ctrl[key=0x%08x] format=%d or len=%d invlaid, buf_len=%d\n", + key, info_ctrl->frmt, info_ctrl->len, buf_len); + return -DFD_RV_TYPE_ERR; + } + + read_bytes = dfd_read_info(info_ctrl->src, info_ctrl->fpath, info_ctrl->addr, info_ctrl->len, buf_tmp); + if (read_bytes <= 0) { + DBG_DEBUG(DBG_ERROR, "read buf info[key=0x%08x src=%s frmt=%s fpath=%s addr=0x%x len=%d] fail, rv=%d\n", + key, g_info_src_str[info_ctrl->src], g_info_frmt_str[info_ctrl->frmt], info_ctrl->fpath, + info_ctrl->addr, info_ctrl->len, read_bytes); + return -DFD_RV_DEV_FAIL; + } + + if (pfun) { + buf_real_len = buf_len; + rv = pfun(buf_tmp, read_bytes, buf, &buf_real_len); + if (rv < 0) { + DBG_DEBUG(DBG_ERROR, "info ctrl[key=0x%08x] buf process fail, rv=%d\n", key, rv); + return -DFD_RV_DEV_NOTSUPPORT; + } + } else { + buf_real_len = read_bytes; + memcpy(buf, buf_tmp, read_bytes); + } + + return buf_real_len; +} + +static int dfd_2key_info_get_buf(info_ctrl_t *info_ctrl, uint8_t *buf, int buf_len, info_hwmon_buf_f pfun) +{ + int rv; + int read_bytes, buf_real_len; + uint8_t buf_tmp[INFO_BUF_MAX_LEN]; + char temp_fpath[INFO_FPATH_MAX_LEN]; + + if (!IS_INFO_FRMT_BUF(info_ctrl->frmt) || !INFO_BUF_LEN_VALAID(info_ctrl->len) + || (buf_len <= info_ctrl->len)) { + DBG_DEBUG(DBG_ERROR, "key_path info ctrl format=%d or len=%d invlaid, buf_len=%d\n", + info_ctrl->frmt, info_ctrl->len, buf_len); + return -DFD_RV_TYPE_ERR; + } + + mem_clear(buf_tmp, sizeof(buf_tmp)); + rv = kfile_iterate_dir(info_ctrl->fpath, DFD_HWMON_NAME, buf_tmp, INFO_BUF_MAX_LEN); + if (rv < 0) { + DBG_DEBUG(DBG_ERROR, "dir patch:%s ,can find name %s dir \n", + info_ctrl->fpath, DFD_HWMON_NAME); + return -DFD_RV_NO_NODE; + } + mem_clear(temp_fpath, sizeof(temp_fpath)); + snprintf(temp_fpath, sizeof(temp_fpath), "%s%s/%s", + info_ctrl->fpath, buf_tmp, info_ctrl->str_cons); + DBG_DEBUG(DBG_VERBOSE, "match ok path = %s \n", temp_fpath); + + mem_clear(buf_tmp, sizeof(buf_tmp)); + + read_bytes = dfd_read_info(info_ctrl->src, temp_fpath, info_ctrl->addr, info_ctrl->len, buf_tmp); + if (read_bytes <= 0) { + DBG_DEBUG(DBG_ERROR, "read buf info[src=%s frmt=%s fpath=%s addr=0x%x len=%d] fail, rv=%d\n", + g_info_src_str[info_ctrl->src], g_info_src_str[info_ctrl->frmt], temp_fpath, + info_ctrl->addr, info_ctrl->len, read_bytes); + return -DFD_RV_DEV_FAIL; + } + + if (pfun) { + buf_real_len = buf_len; + rv = pfun(buf_tmp, read_bytes, buf, &buf_real_len, info_ctrl); + if (rv < 0) { + DBG_DEBUG(DBG_ERROR, "info ctrl buf process fail, rv=%d\n", rv); + return -DFD_RV_DEV_NOTSUPPORT; + } + } else { + buf_real_len = read_bytes; + memcpy(buf, buf_tmp, buf_real_len); + } + return buf_real_len; +} + +int dfd_info_set_int(int key, int val) +{ + int rv; + int write_bytes; + uint8_t byte_tmp, bit_mask; + info_ctrl_t *info_ctrl; + + if (!DFD_CFG_ITEM_IS_INFO_CTRL(DFD_CFG_ITEM_ID(key))) { + DBG_DEBUG(DBG_ERROR, "input arguments error, key=0x%08x\n", key); + return -DFD_RV_INDEX_INVALID; + } + + info_ctrl = dfd_ko_cfg_get_item(key); + if (info_ctrl == NULL) { + DBG_DEBUG(DBG_WARN, "get info ctrl fail, key=0x%08x\n", key); + return -DFD_RV_DEV_NOTSUPPORT; + } + + if (info_ctrl->mode != INFO_CTRL_MODE_CFG) { + DBG_DEBUG(DBG_ERROR, "info ctrl[key=0x%08x] mode[%d] warnning\n", key, info_ctrl->mode); + return -DFD_RV_TYPE_ERR; + } + + if (IS_INFO_FRMT_BIT(info_ctrl->frmt)) { + + if (!INFO_BIT_OFFSET_VALID(info_ctrl->bit_offset)) { + DBG_DEBUG(DBG_ERROR, "info ctrl[key=0x%08x] bit_offsest[%d] invalid\n", + key, info_ctrl->bit_offset); + return -DFD_RV_TYPE_ERR; + } + + write_bytes = 1; + + byte_tmp = (uint8_t)(val & 0xff); + byte_tmp <<= info_ctrl->bit_offset; + if (info_ctrl->pola == INFO_POLA_NEGA) { + byte_tmp = ~byte_tmp; + } + + bit_mask = (~(0xff << info_ctrl->len)) << info_ctrl->bit_offset; + } else if (IS_INFO_FRMT_BYTE(info_ctrl->frmt)) { + + if (!INFO_INT_LEN_VALAID(info_ctrl->len)) { + DBG_DEBUG(DBG_ERROR, "info ctrl[key=0x%08x] len[%d] invalid\n", key, info_ctrl->len); + return -DFD_RV_TYPE_ERR; + } + + write_bytes = 1; + + byte_tmp = (uint8_t)(val & 0xff); + + bit_mask = 0xff; + } else if (IS_INFO_FRMT_NUM_STR(info_ctrl->frmt)) { + + DBG_DEBUG(DBG_ERROR, "not support str int set\n"); + return -1; + } else if (IS_INFO_FRMT_NUM_BUF(info_ctrl->frmt)) { + + if (!INFO_INT_LEN_VALAID(info_ctrl->len)) { + DBG_DEBUG(DBG_ERROR, "info ctrl[key=0x%08x] len[%d] invalid\n", key, info_ctrl->len); + return -DFD_RV_TYPE_ERR; + } + + write_bytes = 1; + + byte_tmp = (uint8_t)(val & 0xff); + + bit_mask = 0xff; + } else { + DBG_DEBUG(DBG_ERROR, "info ctrl[key=0x%08x] format[%d] error\n", key, info_ctrl->frmt); + return -DFD_RV_TYPE_ERR; + } + + rv = dfd_write_info(info_ctrl->src, info_ctrl->fpath, info_ctrl->addr, write_bytes, + &byte_tmp, bit_mask); + if (rv < 0) { + DBG_DEBUG(DBG_ERROR, "write int info[src=%s frmt=%s fpath=%s addr=0x%x len=%d val=%d] fail, rv=%d\n", + g_info_src_str[info_ctrl->src], g_info_frmt_str[info_ctrl->frmt], info_ctrl->fpath, + info_ctrl->addr, info_ctrl->len, val, rv); + return -DFD_RV_DEV_FAIL; + } + + DBG_DEBUG(DBG_VERBOSE, "write int info[src=%s frmt=%s pola=%s fpath=%s addr=0x%x len=%d bit_offset=%d val=%d] success\n", + g_info_src_str[info_ctrl->src], g_info_frmt_str[info_ctrl->frmt], g_info_pola_str[info_ctrl->pola], + info_ctrl->fpath, info_ctrl->addr, info_ctrl->len, info_ctrl->bit_offset, val); + return DFD_RV_OK; +} + +static int dfd_info_get_cpld_voltage(int key, int *value) +{ + int rv, addr_tmp; + int vol_ref_tmp, vol_ref; + int vol_curr_tmp, vol_curr; + info_ctrl_t *info_ctrl; + + info_ctrl = dfd_ko_cfg_get_item(key); + if (info_ctrl == NULL) { + DBG_DEBUG(DBG_WARN, "get info ctrl fail, key=0x%08x\n", key); + return -DFD_RV_DEV_NOTSUPPORT; + } + + rv = dfd_info_get_int(key, &vol_curr_tmp, NULL); + if(rv < 0) { + DBG_DEBUG(DBG_ERROR, "get cpld current voltage error, addr:0x%x, rv =%d\n", info_ctrl->addr, rv); + return rv; + } + vol_curr_tmp = DFD_GET_CPLD_VOLATGE_CODE_VALUE(vol_curr_tmp); + if(info_ctrl->addr == info_ctrl->int_extra1) { + + vol_curr = DFD_GET_CPLD_VOLATGE_REAL_VALUE(vol_curr_tmp, info_ctrl->int_extra2); + } else { + + addr_tmp = info_ctrl->addr; + info_ctrl->addr = info_ctrl->int_extra1; + rv = dfd_info_get_int(key, &vol_ref_tmp, NULL); + info_ctrl->addr = addr_tmp; + if(rv < 0) { + DBG_DEBUG(DBG_ERROR, "get cpld reference voltage error, addr:0x%x rv:%d\n", info_ctrl->addr, rv); + return rv; + } + vol_ref = DFD_GET_CPLD_VOLATGE_CODE_VALUE(vol_ref_tmp); + vol_curr = (vol_curr_tmp * info_ctrl->int_extra2) / vol_ref; + } + *value = vol_curr; + return DFD_RV_OK; +} + +static int dfd_info_get_sensor_value(int key, uint8_t *buf, int buf_len, info_hwmon_buf_f pfun) +{ + int rv, buf_real_len; + int value; + uint8_t buf_tmp[INFO_BUF_MAX_LEN]; + info_ctrl_t *info_ctrl; + + info_ctrl = dfd_ko_cfg_get_item(key); + if (info_ctrl == NULL) { + DBG_DEBUG(DBG_ERROR, "get info ctrl fail, key=0x%08x\n", key); + return -DFD_RV_DEV_NOTSUPPORT; + } + + if ( DFD_CFG_ITEM_ID(key) == DFD_CFG_ITEM_HWMON_IN && info_ctrl->src == INFO_SRC_CPLD) { + + rv = dfd_info_get_cpld_voltage(key, &value); + if(rv < 0) { + DBG_DEBUG(DBG_ERROR, "get cpld voltage failed.key=0x%08x, rv:%d\n", key, rv); + return -DFD_RV_DEV_NOTSUPPORT; + } + DBG_DEBUG(DBG_VERBOSE, "get cpld voltage ok, value:%d\n", value); + mem_clear(buf_tmp, sizeof(buf_tmp)); + snprintf(buf_tmp, sizeof(buf_tmp), "%d\n", value); + buf_real_len = strlen(buf_tmp); + if(buf_len <= buf_real_len) { + DBG_DEBUG(DBG_ERROR, "length not enough.buf_len:%d,need length:%d\n", buf_len, buf_real_len); + return -DFD_RV_DEV_FAIL; + } + if (pfun) { + buf_real_len = buf_len; + rv = pfun(buf_tmp, strlen(buf_tmp), buf, &buf_real_len, info_ctrl); + if (rv < 0) { + DBG_DEBUG(DBG_ERROR, "deal date error.org value:%s, buf_len:%d, rv=%d\n", + buf_tmp, buf_len, rv); + return -DFD_RV_DEV_NOTSUPPORT; + } + } else { + memcpy(buf, buf_tmp, buf_real_len); + } + return buf_real_len; + } + + DBG_DEBUG(DBG_ERROR, "not support mode. key:0x%08x\n", key); + return -DFD_RV_MODE_NOTSUPPORT; +} + +int dfd_info_get_sensor(uint32_t key, char *buf, int buf_len, info_hwmon_buf_f pfun) +{ + info_ctrl_t *key_info_ctrl; + int rv; + + if (!DFD_CFG_ITEM_IS_INFO_CTRL(DFD_CFG_ITEM_ID(key)) || + (buf == NULL) || buf_len <= 0) { + DBG_DEBUG(DBG_ERROR, "input arguments error, key_path=0x%08x, buf_len:%d.\n", + key, buf_len); + return -DFD_RV_INVALID_VALUE; + } + + key_info_ctrl = dfd_ko_cfg_get_item(key); + if (key_info_ctrl == NULL) { + DBG_DEBUG(DBG_ERROR, "key_path info error, key=0x%08x\n", key); + return -DFD_RV_DEV_NOTSUPPORT; + } + mem_clear(buf, buf_len); + + if (key_info_ctrl->mode == INFO_CTRL_MODE_SRT_CONS) { + snprintf(buf, buf_len, "%s\n", key_info_ctrl->str_cons); + DBG_DEBUG(DBG_VERBOSE, "get sensor value through string config, key=0x%08x, value:%s\n", key, buf); + return strlen(buf); + } + + if (key_info_ctrl->mode == INFO_CTRL_MODE_CFG && key_info_ctrl->src == INFO_SRC_FILE) { + DBG_DEBUG(DBG_VERBOSE, "get sensor value through hwmon, key:0x%08x\n", key); + rv = dfd_2key_info_get_buf(key_info_ctrl, buf, buf_len, pfun); + if (rv < 0) { + DBG_DEBUG(DBG_VERBOSE, "get sensor value through hwmon failed, key:0x%08x, rv:%d\n", key, rv); + } + return rv; + } + rv = dfd_info_get_sensor_value(key, buf, buf_len, pfun); + if( rv < 0) { + DBG_DEBUG(DBG_ERROR, "get sensor value failed, key=0x%08x, rv:%d.\n", key, rv); + } + return rv; +} diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/cfg/dfd_cfg_listnode.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/cfg/dfd_cfg_listnode.c new file mode 100644 index 000000000000..d6fd7e104c9f --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/cfg/dfd_cfg_listnode.c @@ -0,0 +1,82 @@ +#include +#include + +#include "../include/dfd_cfg_listnode.h" +#include "../../dev_sysfs/include/sysfs_common.h" + +void *lnode_find_node(lnode_root_t *root, int key) +{ + lnode_node_t *lnode; + + if (root == NULL){ + return NULL; + } + + list_for_each_entry(lnode, &(root->root), lst) { + if (lnode->key == key) { + return lnode->data; + } + } + + return NULL; +} + +int lnode_insert_node(lnode_root_t *root, int key, void *data) +{ + lnode_node_t *lnode; + void *data_tmp; + + if ((root == NULL) || (data == NULL)) { + return LNODE_RV_INPUT_ERR; + } + + data_tmp = lnode_find_node(root, key); + if (data_tmp != NULL) { + return LNODE_RV_NODE_EXIST; + } + + lnode = kmalloc(sizeof(lnode_node_t), GFP_KERNEL); + if (lnode == NULL) { + return LNODE_RV_NOMEM; + } + + lnode->key = key; + lnode->data = data; + list_add_tail(&(lnode->lst), &(root->root)); + + return LNODE_RV_OK; +} + +int lnode_init_root(lnode_root_t *root) +{ + if (root == NULL) { + return LNODE_RV_INPUT_ERR; + } + + INIT_LIST_HEAD(&(root->root)); + + return LNODE_RV_OK; +} + +void lnode_free_list(lnode_root_t *root) +{ + lnode_node_t *lnode, *lnode_next; + + if (root == NULL){ + return ; + } + + list_for_each_entry_safe(lnode, lnode_next, &(root->root), lst) { + if ( lnode->data ) { + kfree(lnode->data); + lnode->data = NULL; + lnode->key = 0; + } + list_del(&lnode->lst); + kfree(lnode); + lnode = NULL; + } + + return ; + +} diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/dfd_fan_driver.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/dfd_fan_driver.c new file mode 100644 index 000000000000..efc322046c07 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/dfd_fan_driver.c @@ -0,0 +1,170 @@ +#include +#include + +#include "./include/dfd_module.h" +#include "./include/dfd_cfg.h" +#include "./include/dfd_cfg_adapter.h" +#include "./include/dfd_cfg_info.h" +#include "../dev_sysfs/include/sysfs_common.h" + +#define FAN_SIZE (256) + +int g_dfd_fan_dbg_level = 0; +module_param(g_dfd_fan_dbg_level, int, S_IRUGO | S_IWUSR); + +int dfd_get_fan_roll_status(unsigned int fan_index, unsigned int motor_index) +{ + int key, ret; + int status; + + key = DFD_CFG_KEY(DFD_CFG_ITEM_FAN_ROLL_STATUS, fan_index, motor_index); + ret = dfd_info_get_int(key, &status, NULL); + if (ret < 0) { + DFD_FAN_DEBUG(DBG_ERROR, "get fan roll status error, fan:%d,motor:%d\n", + fan_index, motor_index); + return ret; + } + + DFD_FAN_DEBUG(DBG_VERBOSE, "fan%u motor%u get fan roll status success, status:%d.\n", + fan_index, motor_index, status); + return status; +} + +int dfd_get_fan_present_status(unsigned int fan_index) +{ + int key, ret; + int status; + + key = DFD_CFG_KEY(DFD_CFG_ITEM_DEV_PRESENT_STATUS, WB_MAIN_DEV_FAN, fan_index); + ret = dfd_info_get_int(key, &status, NULL); + if (ret < 0) { + DFD_FAN_DEBUG(DBG_ERROR, "fan%u get present status error, key:0x%x\n", fan_index, key); + return ret; + } + + DFD_FAN_DEBUG(DBG_VERBOSE, "fan%u get present status success, status:%d.\n", fan_index, status); + return status; +} + +ssize_t dfd_get_fan_speed(unsigned int fan_index, unsigned int motor_index,unsigned int *speed) +{ + int key, ret, speed_tmp; + + if (speed == NULL) { + DFD_FAN_DEBUG(DBG_ERROR, "param error. fan index:%d, motor index:%d.\n", + fan_index, motor_index); + return -DFD_RV_INVALID_VALUE; + } + + key = DFD_CFG_KEY(DFD_CFG_ITEM_FAN_SPEED, fan_index, motor_index); + ret = dfd_info_get_int(key, &speed_tmp, NULL); + if (ret < 0) { + DFD_FAN_DEBUG(DBG_ERROR, "get fan speed error, key:0x%x,ret:%d\n",key, ret); + return ret; + } + + if (speed_tmp == 0 || speed_tmp == 0xffff) { + *speed = 0; + } else { + *speed = 15000000 / speed_tmp; + } + return DFD_RV_OK; +} + +int dfd_set_fan_speed_level(unsigned int fan_index, unsigned int motor_index, int level) +{ + int key, ret; + + if (level < 0 || level > 0xff) { + DFD_FAN_DEBUG(DBG_ERROR, "fan:%u, motor:%u, can not set fan speed level: %d.\n", + fan_index, motor_index, level); + return -DFD_RV_INVALID_VALUE; + } + + key = DFD_CFG_KEY(DFD_CFG_ITEM_FAN_RATIO, fan_index, motor_index); + ret = dfd_info_set_int(key, level); + if (ret < 0) { + DFD_FAN_DEBUG(DBG_ERROR, "fan:%u, motor:%u, set fan level 0x%02x error, key:0x%x,ret:%d\n", + fan_index, motor_index, level, key, ret); + return ret; + } + + DFD_FAN_DEBUG(DBG_VERBOSE, "fan:%u, motor:%u, set fan speed level 0x%02x success.\n", + fan_index, motor_index, level); + return DFD_RV_OK; +} + +int dfd_set_fan_pwm(unsigned int fan_index, unsigned int motor_index, int pwm) +{ + int ret, data; + + if (pwm < 0 || pwm > 100) { + DFD_FAN_DEBUG(DBG_ERROR, "fan:%u, motor:%u, can't set pwm: %d.\n", + fan_index, motor_index, pwm); + return -DFD_RV_INVALID_VALUE; + } + + data = pwm * 255 / 100; + ret = dfd_set_fan_speed_level(fan_index, motor_index, data); + if (ret < 0) { + DFD_FAN_DEBUG(DBG_ERROR, "fan:%u, motor:%u, set fan ratio:%d error, ret:%d\n", + fan_index, motor_index, data, ret); + return ret; + } + + DFD_FAN_DEBUG(DBG_VERBOSE, "fan:%u, motor:%u, set fan ratio %d success.\n", + fan_index, motor_index, data); + return DFD_RV_OK; +} + +int dfd_get_fan_speed_level(unsigned int fan_index, unsigned int motor_index, int *level) +{ + int key, ret, speed_level; + + if (level == NULL) { + DFD_FAN_DEBUG(DBG_ERROR, "param error. fan index:%d, motor index:%d.\n", + fan_index, motor_index); + return -DFD_RV_INVALID_VALUE; + } + + key = DFD_CFG_KEY(DFD_CFG_ITEM_FAN_RATIO, fan_index, motor_index); + ret = dfd_info_get_int(key, &speed_level, NULL); + if (ret < 0) { + DFD_FAN_DEBUG(DBG_ERROR, "fan:%u, motor:%u, get fan speed level error, key:0x%x,ret:%d\n", + fan_index, motor_index, key, ret); + return ret; + } + + DFD_FAN_DEBUG(DBG_VERBOSE, "fan:%u, motor:%u, get fan speed level success, value:0x%02x.\n", + fan_index, motor_index, speed_level); + *level = speed_level; + return DFD_RV_OK; +} + +int dfd_get_fan_pwm(unsigned int fan_index, unsigned int motor_index, int *pwm) +{ + int ret, level; + + if (pwm == NULL) { + DFD_FAN_DEBUG(DBG_ERROR, "param error. fan index:%d, motor index:%d.\n", + fan_index, motor_index); + return -DFD_RV_INVALID_VALUE; + } + + ret = dfd_get_fan_speed_level(fan_index, motor_index, &level); + if (ret < 0) { + DFD_FAN_DEBUG(DBG_ERROR, "fan:%u, motor:%u, get fan pwm error, ret:%d\n", + fan_index, motor_index, ret); + return ret; + } + + if ((level * 100) % 255 > 0) { + *pwm = level * 100 / 255 + 1; + } else { + *pwm = level * 100 / 255; + } + + DFD_FAN_DEBUG(DBG_VERBOSE, "fan:%u, motor:%u, get fan pwm success, value:%d.\n", + fan_index, motor_index, *pwm); + return DFD_RV_OK; +} diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/dfd_module.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/dfd_module.c new file mode 100644 index 000000000000..9e5b00b795de --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/dfd_module.c @@ -0,0 +1,95 @@ +#include + +#include "../dev_sysfs/include/sysfs_common.h" +#include "./include/dfd_module.h" +#include "./include/dfd_cfg.h" +#include "./include/dfd_fan_driver.h" +#include "./include/dfd_slot_driver.h" +#include "./include/dfd_sensors_driver.h" +#include "./include/dfd_psu_driver.h" +#include "./include/dfd_sff_driver.h" + +typedef enum dfd_dev_init_fail_s { + DFD_KO_INIT_CPLD_FAIL = 1, + DFD_KO_INIT_FPGA_FAIL = 2, + DFD_KO_INIT_IRQ_FAIL = 3, + DFD_KO_INIT_CFG_FAIL = 4, + DFD_KO_INIT_DATA_FAIL = 5, +} dfd_dev_init_fail_t; + +int g_dfd_dbg_level = 0; + +int dfd_get_dev_number(unsigned int main_dev_id, unsigned int minor_dev_id) +{ + int key,dev_num; + int *p_dev_num; + + key = DFD_CFG_KEY(DFD_CFG_ITEM_DEV_NUM, main_dev_id, minor_dev_id); + p_dev_num = dfd_ko_cfg_get_item(key); + if (p_dev_num == NULL) { + DBG_DEBUG(DBG_ERROR, "get device number failed, key:0x%x\n",key); + return -DFD_RV_DEV_NOTSUPPORT; + } + dev_num = *p_dev_num; + DBG_DEBUG(DBG_VERBOSE, "get device number ok, number:%d\n",dev_num); + return dev_num; +} + +static struct switch_drivers_t switch_drivers= { + .get_dev_number = dfd_get_dev_number, + /* fan */ + .get_fan_speed = dfd_get_fan_speed, + .get_fan_pwm = dfd_get_fan_pwm, + .set_fan_pwm = dfd_set_fan_pwm, + .get_fan_present_status = dfd_get_fan_present_status, + .get_fan_roll_status = dfd_get_fan_roll_status, + .get_fan_speed_level = dfd_get_fan_speed_level, + .set_fan_speed_level = dfd_set_fan_speed_level, + /* slot */ + .get_slot_present_status = dfd_get_slot_present_status, + /* sensors */ + .get_temp_info = dfd_get_temp_info, + .get_voltage_info = dfd_get_voltage_info, + /* psu */ + .get_psu_present_status = dfd_get_psu_present_status, + .get_psu_output_status = dfd_get_psu_output_status, + .get_psu_alert_status = dfd_get_psu_alert_status, + /* sff */ + .get_sff_cpld_info = dfd_get_sff_cpld_info, + .get_sff_dir_name = dfd_get_sff_dir_name, +}; + +struct switch_drivers_t * dfd_plat_driver_get(void) { + return &switch_drivers; +} + +static int32_t __init dfd_dev_init(void) +{ + int ret; + + DBG_DEBUG(DBG_VERBOSE, "Enter.\n"); + + ret = dfd_dev_cfg_init(); + if (ret != 0) { + DBG_DEBUG(DBG_ERROR, "dfd_dev_cfg_init failed ret %d.\n", ret); + ret = -DFD_KO_INIT_CFG_FAIL; + return ret; + } + + DBG_DEBUG(DBG_VERBOSE, "success.\n"); + return 0; +} + +static void __exit dfd_dev_exit(void) +{ + DBG_DEBUG(DBG_VERBOSE, "dfd_dev_exit.\n"); + dfd_dev_cfg_exit(); + return ; +} + +module_init(dfd_dev_init); +module_exit(dfd_dev_exit); +module_param(g_dfd_dbg_level, int, S_IRUGO | S_IWUSR); +EXPORT_SYMBOL(dfd_plat_driver_get); +MODULE_AUTHOR("support"); +MODULE_LICENSE("GPL"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/dfd_psu_driver.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/dfd_psu_driver.c new file mode 100644 index 000000000000..55e2e4339ae7 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/dfd_psu_driver.c @@ -0,0 +1,70 @@ +#include +#include + +#include "./include/dfd_module.h" +#include "./include/dfd_cfg.h" +#include "./include/dfd_cfg_adapter.h" +#include "./include/dfd_cfg_info.h" +#include "../dev_sysfs/include/sysfs_common.h" + +#define PSU_SIZE (256) + +typedef enum dfd_psu_status_e { + DFD_PSU_PRESENT_STATUS = 0, + DFD_PSU_OUTPUT_STATUS = 1, + DFD_PSU_ALERT_STATUS = 2, +} dfd_psu_status_t; + +int g_dfd_psu_dbg_level = 0; +module_param(g_dfd_psu_dbg_level, int, S_IRUGO | S_IWUSR); + +int dfd_get_psu_present_status(unsigned int psu_index) +{ + int ret, present_key, present_status; + + present_key = DFD_CFG_KEY(DFD_CFG_ITEM_PSU_STATUS, psu_index, DFD_PSU_PRESENT_STATUS); + ret = dfd_info_get_int(present_key, &present_status, NULL); + if (ret < 0) { + DFD_PSU_DEBUG(DBG_ERROR, "dfd_get_psu_present_status error. psu_index:%d, ret:%d\n", + psu_index, ret); + return ret; + } + + DFD_PSU_DEBUG(DBG_VERBOSE, "dfd_get_psu_present_status success. psu_index:%d, status:%d\n", + psu_index, present_status); + return present_status; +} + +int dfd_get_psu_output_status(unsigned int psu_index) +{ + int ret, output_key, output_status; + + output_key = DFD_CFG_KEY(DFD_CFG_ITEM_PSU_STATUS, psu_index, DFD_PSU_OUTPUT_STATUS); + ret = dfd_info_get_int(output_key, &output_status, NULL); + if (ret < 0) { + DFD_PSU_DEBUG(DBG_ERROR, "dfd_get_psu_output_status error. psu_index:%d, ret:%d\n", + psu_index, ret); + return ret; + } + + DFD_PSU_DEBUG(DBG_VERBOSE, "dfd_get_psu_output_status success. psu_index:%d, status:%d\n", + psu_index, output_status); + return output_status; +} + +int dfd_get_psu_alert_status(unsigned int psu_index) +{ + int ret, alert_key, alert_status; + + alert_key = DFD_CFG_KEY(DFD_CFG_ITEM_PSU_STATUS, psu_index, DFD_PSU_ALERT_STATUS); + ret = dfd_info_get_int(alert_key, &alert_status, NULL); + if (ret < 0) { + DFD_PSU_DEBUG(DBG_ERROR, "dfd_get_psu_alert_status error. psu_index:%d, ret:%d\n", + psu_index, ret); + return ret; + } + + DFD_PSU_DEBUG(DBG_VERBOSE, "dfd_get_psu_alert_status success. psu_index:%d, status:%d\n", + psu_index, alert_status); + return alert_status; +} diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/dfd_sensors_driver.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/dfd_sensors_driver.c new file mode 100644 index 000000000000..bfca20290efb --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/dfd_sensors_driver.c @@ -0,0 +1,149 @@ +#include +#include + +#include "./include/dfd_module.h" +#include "./include/dfd_cfg.h" +#include "./include/dfd_cfg_adapter.h" +#include "./include/dfd_cfg_info.h" +#include "./include/dfd_cfg_file.h" +#include "../dev_sysfs/include/sysfs_common.h" + +#define DFD_GET_TEMP_SENSOR_KEY1(dev_index, temp_index) \ + (((dev_index & 0xff) << 8) | (temp_index & 0xff)) +#define DFD_GET_TEMP_SENSOR_KEY2(main_dev_id, temp_type) \ + (((main_dev_id & 0x0f) << 4) | (temp_type & 0x0f)) +#define DFD_FORMAT_STR_MAX_LEN (32) + +int g_dfd_sensor_dbg_level = 0; +module_param(g_dfd_sensor_dbg_level, int, S_IRUGO | S_IWUSR); + +static int dfd_deal_hwmon_buf(uint8_t *buf, int buf_len, uint8_t *buf_new, int *buf_len_new, info_ctrl_t *info_ctrl) +{ + int i, tmp_len; + int exp, decimal, divisor; + int org_value, tmp_value; + int div_result, div_mod; + char fmt_str[DFD_FORMAT_STR_MAX_LEN]; + + exp = info_ctrl->int_cons; + decimal = info_ctrl->bit_offset; + + if (exp <= 0) { + DBG_DEBUG(DBG_VERBOSE, "exponent %d, don't need transform. buf_len:%d, buf_len_new:%d\n", + exp, buf_len, *buf_len_new); + snprintf(buf_new, *buf_len_new, "%s", buf); + *buf_len_new = strlen(buf_new); + return DFD_RV_OK; + } + divisor = 1; + for (i = 0; i < exp; i++) { + divisor *= 10; + } + org_value = simple_strtol(buf, NULL, 10); + if (org_value < 0) { + tmp_value = 0 - org_value; + } else { + tmp_value = org_value; + } + div_result = tmp_value / divisor; + div_mod = tmp_value % divisor; + DBG_DEBUG(DBG_VERBOSE, "exp:%d, decimal:%d, original value:%d, divisor:%d, result :%d, mod:%d\n", + exp, decimal, org_value, divisor, div_result, div_mod); + + mem_clear(fmt_str, sizeof(fmt_str)); + if (org_value < 0) { + snprintf(fmt_str, sizeof(fmt_str), "-%%d.%%0%dd\n",exp); + } else { + snprintf(fmt_str, sizeof(fmt_str), "%%d.%%0%dd\n",exp); + } + DBG_DEBUG(DBG_VERBOSE, "format string:%s",fmt_str); + snprintf(buf_new, *buf_len_new, fmt_str, div_result, div_mod); + *buf_len_new = strlen(buf_new); + tmp_len = *buf_len_new; + + if ( decimal > 0) { + for(i = 0; i < *buf_len_new; i++) { + if (buf_new[i] == '.') { + if( i + decimal + 2 <= *buf_len_new ) { + buf_new[i + decimal + 1 ] = '\n'; + buf_new[i + decimal + 2 ] = '\0'; + *buf_len_new = strlen(buf_new); + DBG_DEBUG(DBG_VERBOSE, "deal decimal[%d] ok, str len:%d, value:%s\n", + decimal, *buf_len_new, buf_new); + } + break; + } + } + if (tmp_len == *buf_len_new) { + DBG_DEBUG(DBG_WARN, "deal decimal[%d] failed, use original value:%s\n", decimal, buf_new); + } + } + return DFD_RV_OK; +} + +static int dfd_get_sensor_info(uint8_t main_dev_id, uint8_t dev_index, uint8_t sensor_type, + uint8_t sensor_index, uint8_t sensor_attr, char *buf) +{ + uint32_t key; + uint16_t key_index1; + uint8_t key_index2; + int rv; + info_hwmon_buf_f pfunc; + + key_index1 = DFD_GET_TEMP_SENSOR_KEY1(dev_index, sensor_index); + key_index2 = DFD_GET_TEMP_SENSOR_KEY2(main_dev_id, sensor_attr); + if (sensor_type == WB_MINOR_DEV_TEMP ) { + key = DFD_CFG_KEY(DFD_CFG_ITEM_HWMON_TEMP, key_index1, key_index2); + } else if (sensor_type == WB_MINOR_DEV_IN) { + key = DFD_CFG_KEY(DFD_CFG_ITEM_HWMON_IN, key_index1, key_index2); + } else { + DFD_SENSOR_DEBUG(DBG_ERROR, "unknow sensor type:%d.\n",sensor_type); + return -DFD_RV_INVALID_VALUE; + } + + DFD_SENSOR_DEBUG(DBG_VERBOSE, "get sensor info.main_dev_id:%d, dev_index:0x%x, sensor_index:0x%x, sensor_attr:0x%x, key:0x%x,\n", + main_dev_id, dev_index, sensor_index, sensor_attr, key); + + pfunc = dfd_deal_hwmon_buf; + mem_clear(buf, PAGE_SIZE); + rv = dfd_info_get_sensor(key, buf, PAGE_SIZE, pfunc); + return rv; +} + +ssize_t dfd_get_temp_info(uint8_t main_dev_id, uint8_t dev_index, + uint8_t temp_index, uint8_t temp_attr, char *buf) +{ + int rv; + + if (buf == NULL) { + DFD_SENSOR_DEBUG(DBG_ERROR, "param error. buf is NULL.\n"); + return -DFD_RV_INVALID_VALUE; + } + + rv = dfd_get_sensor_info(main_dev_id, dev_index, WB_MINOR_DEV_TEMP, temp_index, temp_attr, buf); + if (rv < 0) { + DFD_SENSOR_DEBUG(DBG_ERROR, "get temp info error. rv:%d\n", rv); + } else { + DFD_SENSOR_DEBUG(DBG_VERBOSE, "get temp info ok.value:%s\n", buf); + } + return rv; +} + +ssize_t dfd_get_voltage_info(uint8_t main_dev_id, uint8_t dev_index, + uint8_t in_index, uint8_t in_attr, char *buf) +{ + int rv; + + if (buf == NULL) { + DFD_SENSOR_DEBUG(DBG_ERROR, "param error. buf is NULL.\n"); + return -DFD_RV_INVALID_VALUE; + } + + rv = dfd_get_sensor_info(main_dev_id, dev_index, WB_MINOR_DEV_IN, in_index, in_attr, buf); + if (rv < 0) { + DFD_SENSOR_DEBUG(DBG_ERROR, "get voltage info error. rv:%d\n", rv); + } else { + DFD_SENSOR_DEBUG(DBG_VERBOSE, "get voltage info ok.value:%s\n", buf); + } + return rv; +} diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/dfd_sff_driver.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/dfd_sff_driver.c new file mode 100644 index 000000000000..5c1faff975b1 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/dfd_sff_driver.c @@ -0,0 +1,56 @@ +#include + +#include "./include/dfd_module.h" +#include "./include/dfd_cfg.h" +#include "./include/dfd_cfg_info.h" +#include "./include/dfd_cfg_adapter.h" +#include "../dev_sysfs/include/sysfs_common.h" + +int g_dfd_sff_dbg_level = 0; +module_param(g_dfd_sff_dbg_level, int, S_IRUGO | S_IWUSR); + +ssize_t dfd_get_sff_cpld_info(unsigned int sff_index, int cpld_reg_type, char *buf, int len) +{ + int key, ret, value; + + if(buf == NULL) { + DFD_SFF_DEBUG(DBG_ERROR, "param error, buf is NULL. sff_index:%d, cpld_reg_type:%d.\n", + sff_index, cpld_reg_type); + return -DFD_RV_INVALID_VALUE; + } + + key = DFD_CFG_KEY(DFD_CFG_ITEM_SFF_CPLD_REG, sff_index, cpld_reg_type); + ret = dfd_info_get_int(key, &value, NULL); + if (ret < 0) { + DFD_SFF_DEBUG(DBG_ERROR, "get sff cpld reg error, key:0x%x,ret:%d.\n", key, ret); + return ret; + } + + mem_clear(buf, len); + return (ssize_t)snprintf(buf, len, "%d\n", value); +} + +ssize_t dfd_get_sff_dir_name(unsigned int sff_index, char *buf, int buf_len) +{ + int key; + char *sff_dir_name; + + if (buf == NULL) { + DFD_SFF_DEBUG(DBG_ERROR, "param error. buf is NULL.sff index:%d", sff_index); + return -DFD_RV_INVALID_VALUE; + } + + mem_clear(buf, buf_len); + + key = DFD_CFG_KEY(DFD_CFG_ITEM_SFF_DIR_NAME, sff_index, 0); + sff_dir_name = dfd_ko_cfg_get_item(key); + if (sff_dir_name == NULL) { + DFD_SFF_DEBUG(DBG_ERROR, "sff dir name config error, key=0x%08x\n", key); + return -DFD_RV_NODE_FAIL; + } + + DFD_SFF_DEBUG(DBG_VERBOSE, "%s\n", sff_dir_name); + snprintf(buf, buf_len, "%s", sff_dir_name); + return strlen(buf); + +} diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/dfd_slot_driver.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/dfd_slot_driver.c new file mode 100644 index 000000000000..69c82adabef0 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/dfd_slot_driver.c @@ -0,0 +1,27 @@ +#include +#include + +#include "./include/dfd_module.h" +#include "./include/dfd_cfg.h" +#include "./include/dfd_cfg_adapter.h" +#include "./include/dfd_cfg_info.h" +#include "../dev_sysfs/include/sysfs_common.h" + +#define SLOT_SIZE (256) + +int g_dfd_slot_dbg_level = 0; +module_param(g_dfd_slot_dbg_level, int, S_IRUGO | S_IWUSR); + +int dfd_get_slot_present_status(unsigned int slot_index) +{ + int key, ret; + int status; + + key = DFD_CFG_KEY(DFD_CFG_ITEM_DEV_PRESENT_STATUS, WB_MAIN_DEV_SLOT, slot_index); + ret = dfd_info_get_int(key, &status, NULL); + if (ret < 0) { + DFD_SLOT_DEBUG(DBG_ERROR, "get slot status error, key:0x%x\n",key); + return ret; + } + return status; +} diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/include/dfd_cfg.h b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/include/dfd_cfg.h new file mode 100644 index 000000000000..062654d01504 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/include/dfd_cfg.h @@ -0,0 +1,97 @@ +#ifndef __DFD_CFG_H__ +#define __DFD_CFG_H__ + +#include + +#define DFD_KO_CFG_FILE_NAME "/etc/plat_sysfs_cfg/cfg_file_name" +#define DFD_KO_CFG_FILE_DIR "/etc/plat_sysfs_cfg/" +#define DFD_PUB_CARDTYPE_FILE "/sys/module/platform_common/parameters/dfd_my_type" + +#define DFD_CFG_CMDLINE_MAX_LEN (256) +#define DFD_CFG_NAME_MAX_LEN (256) +#define DFD_CFG_VALUE_MAX_LEN (256) +#define DFD_CFG_STR_MAX_LEN (64) +#define DFD_CFG_CPLD_NUM_MAX (16) +#define DFD_PRODUCT_ID_LENGTH (8) +#define DFD_PID_BUF_LEN (32) +#define DFD_TEMP_NAME_BUF_LEN (32) + +#define DFD_CFG_EMPTY_VALUE (-1) +#define DFD_CFG_INVALID_VALUE (0) + +#define DFD_CFG_KEY(item, index1, index2) \ + ((((item) & 0xff) << 24) | (((index1) & 0xffff) << 8) | ((index2) & 0xff)) +#define DFD_CFG_ITEM_ID(key) (((key) >> 24) & 0xff) +#define DFD_CFG_INDEX1(key) (((key) >> 8) & 0xffff) +#define DFD_CFG_INDEX2(key) ((key)& 0xff) + +#define INDEX_NOT_EXIST (-1) +#define INDEX1_MAX (0xffff) +#define INDEX2_MAX (0xff) + +#define DFD_CFG_ITEM_ALL \ + DFD_CFG_ITEM(DFD_CFG_ITEM_NONE, "none", INDEX_NOT_EXIST, INDEX_NOT_EXIST) \ + DFD_CFG_ITEM(DFD_CFG_ITEM_DEV_NUM, "dev_num", INDEX1_MAX, INDEX2_MAX) \ + DFD_CFG_ITEM(DFD_CFG_ITEM_CPLD_LPC_DEV, "cpld_lpc_dev", INDEX1_MAX, DFD_CFG_CPLD_NUM_MAX) \ + DFD_CFG_ITEM(DFD_CFG_ITEM_INT_END, "end_int", INDEX_NOT_EXIST, INDEX_NOT_EXIST) \ + \ + DFD_CFG_ITEM(DFD_CFG_ITEM_CPLD_MODE, "mode_cpld", INDEX1_MAX, DFD_CFG_CPLD_NUM_MAX) \ + DFD_CFG_ITEM(DFD_CFG_ITEM_SFF_DIR_NAME, "sff_dir_name", INDEX1_MAX, INDEX_NOT_EXIST) \ + DFD_CFG_ITEM(DFD_CFG_ITEM_STRING_END, "end_string", INDEX_NOT_EXIST, INDEX_NOT_EXIST) \ + \ + DFD_CFG_ITEM(DFD_CFG_ITEM_CPLD_I2C_DEV, "cpld_i2c_dev", INDEX1_MAX, INDEX2_MAX) \ + DFD_CFG_ITEM(DFD_CFG_ITEM_OTHER_I2C_DEV, "other_i2c_dev", INDEX1_MAX, INDEX2_MAX) \ + DFD_CFG_ITEM(DFD_CFG_ITEM_I2C_DEV_END, "end_i2c_dev", INDEX_NOT_EXIST, INDEX_NOT_EXIST) \ + \ + DFD_CFG_ITEM(DFD_CFG_ITEM_FAN_ROLL_STATUS, "fan_roll_status", INDEX1_MAX, INDEX2_MAX) \ + DFD_CFG_ITEM(DFD_CFG_ITEM_FAN_SPEED, "fan_speed", INDEX1_MAX, INDEX2_MAX) \ + DFD_CFG_ITEM(DFD_CFG_ITEM_FAN_RATIO, "fan_ratio", INDEX1_MAX, INDEX2_MAX) \ + DFD_CFG_ITEM(DFD_CFG_ITEM_DEV_PRESENT_STATUS, "dev_present_status", INDEX1_MAX, INDEX2_MAX) \ + DFD_CFG_ITEM(DFD_CFG_ITEM_PSU_STATUS, "psu_status", INDEX1_MAX, INDEX2_MAX) \ + DFD_CFG_ITEM(DFD_CFG_ITEM_HWMON_TEMP, "hwmon_temp", INDEX1_MAX, INDEX2_MAX) \ + DFD_CFG_ITEM(DFD_CFG_ITEM_HWMON_IN, "hwmon_in", INDEX1_MAX, INDEX2_MAX) \ + DFD_CFG_ITEM(DFD_CFG_ITEM_SFF_CPLD_REG, "sff_cpld_reg", INDEX1_MAX, INDEX2_MAX) \ + DFD_CFG_ITEM(DFD_CFG_ITEM_INFO_CTRL_END, "end_info_ctrl", INDEX_NOT_EXIST, INDEX_NOT_EXIST) \ + +#ifdef DFD_CFG_ITEM +#undef DFD_CFG_ITEM +#endif +#define DFD_CFG_ITEM(_id, _name, _index_min, _index_max) _id, +typedef enum dfd_cfg_item_id_s { + DFD_CFG_ITEM_ALL +} dfd_cfg_item_id_t; + +#define DFD_CFG_ITEM_IS_INT(item_id) \ + (((item_id) > DFD_CFG_ITEM_NONE) && ((item_id) < DFD_CFG_ITEM_INT_END)) + +#define DFD_CFG_ITEM_IS_STRING(item_id) \ + (((item_id) > DFD_CFG_ITEM_INT_END) && ((item_id) < DFD_CFG_ITEM_STRING_END)) + +#define DFD_CFG_ITEM_IS_I2C_DEV(item_id) \ + (((item_id) > DFD_CFG_ITEM_STRING_END) && ((item_id) < DFD_CFG_ITEM_I2C_DEV_END)) + +#define DFD_CFG_ITEM_IS_INFO_CTRL(item_id) \ + (((item_id) > DFD_CFG_ITEM_I2C_DEV_END) && ((item_id) < DFD_CFG_ITEM_INFO_CTRL_END)) + +typedef struct index_range_s { + int index1_max; + int index2_max; +} index_range_t; + +typedef struct val_convert_node_s { + struct list_head lst; + int int_val; + char str_val[DFD_CFG_STR_MAX_LEN]; + int index1; + int index2; +} val_convert_node_t; + +void *dfd_ko_cfg_get_item(int key); + +void dfd_ko_cfg_show_item(int key); + +int32_t dfd_dev_cfg_init(void); + +void dfd_dev_cfg_exit(void); + +#endif /* __DFD_CFG_H__ */ diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/include/dfd_cfg_adapter.h b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/include/dfd_cfg_adapter.h new file mode 100644 index 000000000000..70d8b536c437 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/include/dfd_cfg_adapter.h @@ -0,0 +1,46 @@ +#ifndef __DFD_CFG_ADAPTER_H__ +#define __DFD_CFG_ADAPTER_H__ + +#define DFD_KO_CPLD_I2C_RETRY_SLEEP (10) /* ms */ +#define DFD_KO_CPLD_I2C_RETRY_TIMES (50 / DFD_KO_CPLD_I2C_RETRY_SLEEP) + +#define DFD_KO_CPLD_GET_SLOT(addr) ((addr >> 24) & 0xff) +#define DFD_KO_CPLD_GET_ID(addr) ((addr >> 16) & 0xff) +#define DFD_KO_CPLD_GET_INDEX(addr) (addr & 0xffff) +#define DFD_KO_CPLD_MODE_I2C_STRING "i2c" +#define DFD_KO_CPLD_MODE_LPC_STRING "lpc" + +typedef struct dfd_i2c_dev_s { + int bus; + int addr; +} dfd_i2c_dev_t; + +typedef enum dfd_i2c_dev_mem_s { + DFD_I2C_DEV_MEM_BUS, + DFD_I2C_DEV_MEM_ADDR, + DFD_I2C_DEV_MEM_END +} dfd_i2c_dev_mem_t; + +typedef enum cpld_mode_e { + DFD_CPLD_MODE_I2C, + DFD_CPLD_MODE_LPC, +} cpld_mode_t; + +typedef enum i2c_mode_e { + DFD_I2C_MODE_NORMAL_I2C, + DFD_I2C_MODE_SMBUS, +} i2c_mode_t; + +extern char *g_dfd_i2c_dev_mem_str[DFD_I2C_DEV_MEM_END]; + +int32_t dfd_ko_cpld_read(int32_t addr, uint8_t *buf); + +int32_t dfd_ko_cpld_write(int32_t addr, uint8_t val); + +int32_t dfd_ko_i2c_read(int bus, int addr, int offset, uint8_t *buf, uint32_t size); + +int32_t dfd_ko_i2c_write(int bus, int addr, int offset, uint8_t *buf, uint32_t size); + +int32_t dfd_ko_read_file(char *fpath, int32_t addr, uint8_t *val, int32_t read_bytes); + +#endif /* __DFD_CFG_ADAPTER_H__ */ diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/include/dfd_cfg_file.h b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/include/dfd_cfg_file.h new file mode 100644 index 000000000000..50d7a42d5564 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/include/dfd_cfg_file.h @@ -0,0 +1,37 @@ +#ifndef __DFD_CFG_FILE_H__ +#define __DFD_CFG_FILE_H__ + +#include + +#define KFILE_RV_OK (0) +#define KFILE_RV_INPUT_ERR (-1) +#define KFILE_RV_STAT_FAIL (-2) +#define KFILE_RV_OPEN_FAIL (-3) +#define KFILE_RV_MALLOC_FAIL (-4) +#define KFILE_RV_RD_FAIL (-5) +#define KFILE_RV_ADDR_ERR (-6) +#define KFILE_RV_WR_FAIL (-7) + +#define IS_CR(c) ((c) == '\n') + +typedef struct kfile_ctrl_s { + int32_t size; + int32_t pos; + char *buf; +} kfile_ctrl_t; + +int kfile_open(char *fname, kfile_ctrl_t *kfile_ctrl); + +void kfile_close(kfile_ctrl_t *kfile_ctrl); + +int kfile_gets(char *buf, int buf_size, kfile_ctrl_t *kfile_ctrl); + +int kfile_read(int32_t addr, char *buf, int buf_size, kfile_ctrl_t *kfile_ctrl); + +int kfile_iterate_dir(const char *dir_path, const char *obj_name, char *match_name, int len); + +#if 0 + +int kfile_write(char *fpath, int32_t addr, char *buf, int buf_size); +#endif +#endif /* __DFD_CFG_FILE_H__ */ diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/include/dfd_cfg_info.h b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/include/dfd_cfg_info.h new file mode 100644 index 000000000000..dc1ed17651b9 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/include/dfd_cfg_info.h @@ -0,0 +1,109 @@ +#ifndef __DFD_CFG_INFO_H__ +#define __DFD_CFG_INFO_H__ + +#include + +typedef int (*info_num_buf_to_value_f)(uint8_t *num_buf, int buf_len, int *num_val); + +typedef int (*info_buf_to_buf_f)(uint8_t *buf, int buf_len, uint8_t *buf_new, int *buf_len_new); + +#define IS_INFO_FRMT_BIT(frmt) ((frmt) == INFO_FRMT_BIT) +#define IS_INFO_FRMT_BYTE(frmt) (((frmt) == INFO_FRMT_BYTE) || ((frmt) == INFO_FRMT_NUM_BYTES)) +#define IS_INFO_FRMT_NUM_STR(frmt) ((frmt) == INFO_FRMT_NUM_STR) +#define IS_INFO_FRMT_NUM_BUF(frmt) ((frmt) == INFO_FRMT_NUM_BUF) +#define IS_INFO_FRMT_BUF(frmt) ((frmt) == INFO_FRMT_BUF) + +#define INFO_INT_MAX_LEN (32) +#define INFO_INT_LEN_VALAID(len) (((len) > 0) && ((len) < INFO_INT_MAX_LEN)) + +#define INFO_BUF_MAX_LEN (128) +#define INFO_BUF_LEN_VALAID(len) (((len) > 0) && ((len) < INFO_BUF_MAX_LEN)) + +#define INFO_BIT_OFFSET_VALID(bit_offset) (((bit_offset) >= 0) && ((bit_offset) < 8)) + +typedef enum info_ctrl_mode_e { + INFO_CTRL_MODE_NONE, + INFO_CTRL_MODE_CFG, + INFO_CTRL_MODE_CONS, + INFO_CTRL_MODE_TLV, + INFO_CTRL_MODE_SRT_CONS, + INFO_CTRL_MODE_END +} info_ctrl_mode_t; + +typedef enum info_frmt_e { + INFO_FRMT_NONE, + INFO_FRMT_BIT, + INFO_FRMT_BYTE, + INFO_FRMT_NUM_BYTES, + INFO_FRMT_NUM_STR, + INFO_FRMT_NUM_BUF, + INFO_FRMT_BUF, + INFO_FRMT_END +} info_frmt_t; + +typedef enum info_src_e { + INFO_SRC_NONE, + INFO_SRC_CPLD, + INFO_SRC_FPGA, + INFO_SRC_OTHER_I2C, + INFO_SRC_FILE, + INFO_SRC_END +} info_src_t; + +typedef enum info_pola_e { + INFO_POLA_NONE, + INFO_POLA_POSI, + INFO_POLA_NEGA, + INFO_POLA_END +} info_pola_t; + +#define INFO_FPATH_MAX_LEN (128) +#define INFO_STR_CONS_MAX_LEN (64) +typedef struct info_ctrl_s { + info_ctrl_mode_t mode; + int32_t int_cons; + info_src_t src; + info_frmt_t frmt; + info_pola_t pola; + char fpath[INFO_FPATH_MAX_LEN]; + int32_t addr; + int32_t len; + int32_t bit_offset; + char str_cons[INFO_STR_CONS_MAX_LEN]; + int32_t int_extra1; + int32_t int_extra2; +} info_ctrl_t; + +typedef enum info_ctrl_mem_s { + INFO_CTRL_MEM_MODE, + INFO_CTRL_MEM_INT_CONS, + INFO_CTRL_MEM_SRC, + INFO_CTRL_MEM_FRMT, + INFO_CTRL_MEM_POLA, + INFO_CTRL_MEM_FPATH, + INFO_CTRL_MEM_ADDR, + INFO_CTRL_MEM_LEN, + INFO_CTRL_MEM_BIT_OFFSET, + INFO_CTRL_MEM_STR_CONS, + INFO_CTRL_MEM_INT_EXTRA1, + INFO_CTRL_MEM_INT_EXTRA2, + INFO_CTRL_MEM_END +} info_ctrl_mem_t; + +typedef int (*info_hwmon_buf_f)(uint8_t *buf, int buf_len, uint8_t *buf_new, int *buf_len_new, info_ctrl_t *info_ctrl); + +extern char *g_info_ctrl_mem_str[INFO_CTRL_MEM_END]; +extern char *g_info_src_str[INFO_SRC_END]; +extern char *g_info_frmt_str[INFO_FRMT_END]; +extern char *g_info_pola_str[INFO_POLA_END]; +extern char *g_info_ctrl_mode_str[INFO_CTRL_MODE_END]; + +int dfd_info_get_int(int key, int *ret, info_num_buf_to_value_f pfun); + +int dfd_info_get_buf(int key, uint8_t *buf, int buf_len, info_buf_to_buf_f pfun); + +int dfd_info_set_int(int key, int val); + +int dfd_info_get_sensor(uint32_t key, char *buf, int buf_len, info_hwmon_buf_f pfun); + +#endif /* __DFD_CFG_INFO_H__ */ diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/include/dfd_cfg_listnode.h b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/include/dfd_cfg_listnode.h new file mode 100644 index 000000000000..955dfa96e42e --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/include/dfd_cfg_listnode.h @@ -0,0 +1,30 @@ +#ifndef __DFD_CFG_LISTNODE_H__ +#define __DFD_CFG_LISTNODE_H__ + +#include + +#define LNODE_RV_OK (0) +#define LNODE_RV_INPUT_ERR (-1) +#define LNODE_RV_NODE_EXIST (-2) +#define LNODE_RV_NOMEM (-3) + +typedef struct lnode_root_s { + struct list_head root; +} lnode_root_t; + +typedef struct lnode_node_s { + struct list_head lst; + + int key; + void *data; +} lnode_node_t; + +void *lnode_find_node(lnode_root_t *root, int key); + +int lnode_insert_node(lnode_root_t *root, int key, void *data); + +int lnode_init_root(lnode_root_t *root); + +void lnode_free_list(lnode_root_t *root); + +#endif /* __DFD_CFG_LISTNODE_H__ */ diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/include/dfd_fan_driver.h b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/include/dfd_fan_driver.h new file mode 100644 index 000000000000..1065fd9eed3f --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/include/dfd_fan_driver.h @@ -0,0 +1,18 @@ +#ifndef _DFD_FAN_DRIVER_H_ +#define _DFD_FAN_DRIVER_H_ + +ssize_t dfd_get_fan_speed(unsigned int fan_index, unsigned int motor_index,unsigned int *speed); + +int dfd_set_fan_pwm(unsigned int fan_index, unsigned int motor_index, int pwm); + +int dfd_get_fan_pwm(unsigned int fan_index, unsigned int motor_index, int *pwm); + +int dfd_get_fan_present_status(unsigned int fan_index); + +int dfd_get_fan_roll_status(unsigned int fan_index, unsigned int motor_index); + +int dfd_get_fan_speed_level(unsigned int fan_index, unsigned int motor_index, int *level); + +int dfd_set_fan_speed_level(unsigned int fan_index, unsigned int motor_index, int level); + +#endif /* _DFD_FAN_DRIVER_H_ */ diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/include/dfd_module.h b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/include/dfd_module.h new file mode 100644 index 000000000000..a547255cf3ab --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/include/dfd_module.h @@ -0,0 +1,96 @@ +#ifndef __DFD_MODULE_H__ +#define __DFD_MODULE_H__ + +typedef enum dfd_rv_s { + DFD_RV_OK = 0, + DFD_RV_INIT_ERR = 1, + DFD_RV_SLOT_INVALID = 2, + DFD_RV_MODE_INVALID = 3, + DFD_RV_MODE_NOTSUPPORT = 4, + DFD_RV_TYPE_ERR = 5, + DFD_RV_DEV_NOTSUPPORT = 6, + DFD_RV_DEV_FAIL = 7, + DFD_RV_INDEX_INVALID = 8, + DFD_RV_NO_INTF = 9, + DFD_RV_NO_NODE = 10, + DFD_RV_NODE_FAIL = 11, + DFD_RV_INVALID_VALUE = 12, + DFD_RV_NO_MEMORY = 13, +} dfd_rv_t; + +typedef enum { + DBG_VERBOSE = 0x01, + DBG_WARN = 0x02, + DBG_ERROR = 0x04, +} dbg_level_t; + +extern int g_dfd_dbg_level; +extern int g_dfd_fan_dbg_level; +extern int g_dfd_slot_dbg_level; +extern int g_dfd_sensor_dbg_level; +extern int g_dfd_psu_dbg_level; +extern int g_dfd_sff_dbg_level; + +#define DBG_DEBUG(level, fmt, arg...) do { \ + if (g_dfd_dbg_level & level) { \ + if(level >= DBG_ERROR) { \ + printk(KERN_ERR "[DBG-%d]:<%s, %d>:"fmt, level, __FUNCTION__, __LINE__, ##arg); \ + } else { \ + printk(KERN_INFO "[DBG-%d]:<%s, %d>:"fmt, level, __FUNCTION__, __LINE__, ##arg); \ + } \ + } \ +} while (0) + +#define DFD_FAN_DEBUG(level, fmt, arg...) do { \ + if (g_dfd_fan_dbg_level & level) { \ + if(level >= DBG_ERROR) { \ + printk(KERN_ERR "[DBG-%d]:<%s, %d>:"fmt, level, __FUNCTION__, __LINE__, ##arg); \ + } else { \ + printk(KERN_INFO "[DBG-%d]:<%s, %d>:"fmt, level, __FUNCTION__, __LINE__, ##arg); \ + } \ + } \ +} while (0) + +#define DFD_SLOT_DEBUG(level, fmt, arg...) do { \ + if (g_dfd_slot_dbg_level & level) { \ + if(level >= DBG_ERROR) { \ + printk(KERN_ERR "[DBG-%d]:<%s, %d>:"fmt, level, __FUNCTION__, __LINE__, ##arg); \ + } else { \ + printk(KERN_INFO "[DBG-%d]:<%s, %d>:"fmt, level, __FUNCTION__, __LINE__, ##arg); \ + } \ + } \ +} while (0) + +#define DFD_SENSOR_DEBUG(level, fmt, arg...) do { \ + if (g_dfd_sensor_dbg_level & level) { \ + if(level >= DBG_ERROR) { \ + printk(KERN_ERR "[DBG-%d]:<%s, %d>:"fmt, level, __FUNCTION__, __LINE__, ##arg); \ + } else { \ + printk(KERN_INFO "[DBG-%d]:<%s, %d>:"fmt, level, __FUNCTION__, __LINE__, ##arg); \ + } \ + } \ +} while (0) + +#define DFD_PSU_DEBUG(level, fmt, arg...) do { \ + if (g_dfd_psu_dbg_level & level) { \ + if(level >= DBG_ERROR) { \ + printk(KERN_ERR "[DBG-%d]:<%s, %d>:"fmt, level, __FUNCTION__, __LINE__, ##arg); \ + } else { \ + printk(KERN_INFO "[DBG-%d]:<%s, %d>:"fmt, level, __FUNCTION__, __LINE__, ##arg); \ + } \ + } \ +} while (0) + +#define DFD_SFF_DEBUG(level, fmt, arg...) do { \ + if (g_dfd_sff_dbg_level & level) { \ + if(level >= DBG_ERROR) { \ + printk(KERN_ERR "[DBG-%d]:<%s, %d>:"fmt, level, __FUNCTION__, __LINE__, ##arg); \ + } else { \ + printk(KERN_INFO "[DBG-%d]:<%s, %d>:"fmt, level, __FUNCTION__, __LINE__, ##arg); \ + } \ + } \ +} while (0) + +int dfd_get_dev_number(unsigned int main_dev_id, unsigned int minor_dev_id); + +#endif /* __DFD_MODULE_H__ */ diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/include/dfd_psu_driver.h b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/include/dfd_psu_driver.h new file mode 100644 index 000000000000..ce7199660557 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/include/dfd_psu_driver.h @@ -0,0 +1,10 @@ +#ifndef _DFD_PSU_DRIVER_H_ +#define _DFD_PSU_DRIVER_H_ + +int dfd_get_psu_present_status(unsigned int psu_index); + +int dfd_get_psu_output_status(unsigned int psu_index); + +int dfd_get_psu_alert_status(unsigned int psu_index); + +#endif /* _DFD_PSU_DRIVER_H_ */ diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/include/dfd_sensors_driver.h b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/include/dfd_sensors_driver.h new file mode 100644 index 000000000000..16733b26029f --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/include/dfd_sensors_driver.h @@ -0,0 +1,10 @@ +#ifndef _DFD_SENSORS_DRIVER_H_ +#define _DFD_SENSORS_DRIVER_H_ + +ssize_t dfd_get_temp_info(uint8_t main_dev_id, uint8_t dev_index, + uint8_t temp_index, uint8_t temp_attr, char *buf); + +ssize_t dfd_get_voltage_info(uint8_t main_dev_id, uint8_t dev_index, + uint8_t in_index, uint8_t in_attr, char *buf); + +#endif /* _DFD_SENSORS_DRIVER_H_ */ diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/include/dfd_sff_driver.h b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/include/dfd_sff_driver.h new file mode 100644 index 000000000000..7107b72ee4b2 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/include/dfd_sff_driver.h @@ -0,0 +1,8 @@ +#ifndef _DFD_SFF_DRIVER_H_ +#define _DFD_SFF_DRIVER_H_ + +ssize_t dfd_get_sff_cpld_info(unsigned int sff_index, int cpld_reg_type, char *buf, int len); + +ssize_t dfd_get_sff_dir_name(unsigned int sff_index, char *buf, int buf_len); + +#endif /* _DFD_SFF_DRIVER_H_ */ diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/include/dfd_slot_driver.h b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/include/dfd_slot_driver.h new file mode 100644 index 000000000000..c68caecd2e66 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_cfg/include/dfd_slot_driver.h @@ -0,0 +1,6 @@ +#ifndef _DFD_SLOT_DRIVER_H_ +#define _DFD_SLOT_DRIVER_H_ + +int dfd_get_slot_present_status(unsigned int slot_index); + +#endif /* _DFD_SLOT_DRIVER_H_ */ diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_sysfs/Makefile b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_sysfs/Makefile new file mode 100644 index 000000000000..1a1044bb1fe8 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_sysfs/Makefile @@ -0,0 +1,21 @@ +PWD = $(shell pwd) + +EXTRA_CFLAGS:= -I$(M)/include +EXTRA_CFLAGS+= -Wall +KBUILD_EXTRA_SYMBOLS += $(PLAT_SYSFS_DIR)/dev_cfg/Module.symvers + +obj-m := plat_switch.o +obj-m += plat_fan.o +obj-m += plat_psu.o +obj-m += plat_sff.o +obj-m += plat_sensor.o +obj-m += plat_slot.o + +all: + $(MAKE) -C $(KERNEL_SRC)/build M=$(PWD) modules + @if [ ! -d $(module_out_put_dir) ]; then mkdir -p $(module_out_put_dir) ;fi + cp -p $(PWD)/*.ko $(module_out_put_dir) +clean: + rm -f $(PWD)/*.o $(PWD)/*.ko $(PWD)/*.mod.c $(PWD)/.*.cmd $(PWD)/*.mod + rm -f $(PWD)/Module.markers $(PWD)/Module.symvers $(PWD)/modules.order + rm -rf $(PWD)/.tmp_versions diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_sysfs/include/plat_switch.h b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_sysfs/include/plat_switch.h new file mode 100644 index 000000000000..bbd813e87114 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_sysfs/include/plat_switch.h @@ -0,0 +1,86 @@ +#ifndef _PLAT_SWITCH_H_ +#define _PLAT_SWITCH_H_ + +#include +#include +#include +#include +#include +#include +#include +#include + +enum LOG_LEVEL{ + INFO = 0x1, + ERR = 0x2, + DBG = 0x4, + ALL = 0xf +}; + +#define LOG_INFO(_prefix, fmt, args...) \ + do { \ + if (g_loglevel & INFO) \ + { \ + printk( KERN_INFO _prefix "%s "fmt, __FUNCTION__, ##args); \ + } \ + } while (0) + +#define LOG_ERR(_prefix, fmt, args...) \ + do { \ + if (g_loglevel & ERR) \ + { \ + printk( KERN_ERR _prefix "%s "fmt, __FUNCTION__, ##args); \ + } \ + } while (0) + +#define LOG_DBG(_prefix, fmt, args...) \ + do { \ + if (g_loglevel & DBG) \ + { \ + printk( KERN_DEBUG _prefix "%s "fmt, __FUNCTION__, ##args); \ + } \ + } while (0) + +#define check_pfun(p) \ + do { \ + if (p == NULL) { \ + printk( KERN_ERR "%s, %s = NULL.\n", __FUNCTION__, #p); \ + return -ENOSYS; \ + } \ + }while(0) + +#define check_p(p) check_pfun(p) + +#define to_switch_obj(x) container_of(x, struct switch_obj, kobj) +#define to_switch_attr(x) container_of(x, struct switch_attribute, attr) +#define to_switch_device_attr(x) container_of(x, struct switch_device_attribute, switch_attr) + +#define SWITCH_ATTR(_name, _mode, _show, _store, _type) \ + { .switch_attr = __ATTR(_name, _mode, _show, _store), \ + .type = _type } + +#define SWITCH_DEVICE_ATTR(_name, _mode, _show, _store, _type) \ +struct switch_device_attribute switch_dev_attr_##_name \ + = SWITCH_ATTR(_name, _mode, _show, _store, _type) + +struct switch_obj { + struct kobject kobj; + unsigned int index; +}; + +/* a custom attribute that works just for a struct switch_obj. */ +struct switch_attribute { + struct attribute attr; + ssize_t (*show)(struct switch_obj *foo, struct switch_attribute *attr, char *buf); + ssize_t (*store)(struct switch_obj *foo, struct switch_attribute *attr, const char *buf, size_t count); +}; + +struct switch_device_attribute { + struct switch_attribute switch_attr; + int type; +}; + +extern struct switch_obj *wb_plat_kobject_create(const char *name, struct kobject *parent); +extern void wb_plat_kobject_delete(struct switch_obj **obj); + +#endif /* _PLAT_SWITCH_H_ */ diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_sysfs/include/sysfs_common.h b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_sysfs/include/sysfs_common.h new file mode 100644 index 000000000000..5b73731e1fbf --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_sysfs/include/sysfs_common.h @@ -0,0 +1,90 @@ +#ifndef _SYSFS_COMMON_H_ +#define _SYSFS_COMMON_H_ + +#include + +#define mem_clear(data, size) memset((data), 0, (size)) + +#define DIR_NAME_MAX_LEN (64) + +#define WB_SYSFS_DEV_ERROR "NA" +/* sysfs directory name */ +#define FAN_SYSFS_NAME "fan" +#define PSU_SYSFS_NAME "psu" +#define SLOT_SYSFS_NAME "slot" +#define VOLTAGE_SYSFS_NAME "in" +#define TEMP_SYSFS_NAME "temp" +#define SFF_SYSFS_NAME "sff" + +typedef enum wb_main_dev_type_e { + WB_MAIN_DEV_MAINBOARD = 0, + WB_MAIN_DEV_FAN = 1, + WB_MAIN_DEV_PSU = 2, + WB_MAIN_DEV_SFF = 3, + WB_MAIN_DEV_CPLD = 4, + WB_MAIN_DEV_SLOT = 5, +} wb_main_dev_type_t; + +typedef enum wb_minor_dev_type_e { + WB_MINOR_DEV_NONE = 0, /* None */ + WB_MINOR_DEV_TEMP = 1, + WB_MINOR_DEV_IN = 2, + WB_MINOR_DEV_CURR = 3, + WB_MINOR_DEV_POWER = 4, + WB_MINOR_DEV_MOTOR = 5, + WB_MINOR_DEV_PSU = 6, +} wb_minor_dev_type_t; + +typedef enum wb_sensor_type_e { + WB_SENSOR_INPUT = 0, + WB_SENSOR_ALIAS = 1, + WB_SENSOR_TYPE = 2, + WB_SENSOR_MAX = 3, + WB_SENSOR_MAX_HYST = 4, + WB_SENSOR_MIN = 5, + WB_SENSOR_CRIT = 6, +} wb_sensor_type_t; + +typedef enum wb_sff_cpld_attr_e { + WB_SFF_POWER_ON = 0x01, + WB_SFF_TX_FAULT, + WB_SFF_TX_DIS, + WB_SFF_PRE_N, + WB_SFF_RX_LOS, + WB_SFF_RESET, + WB_SFF_LPMODE, + WB_SFF_MODULE_PRESENT, + WB_SFF_INTERRUPT, +} wb_sff_cpld_attr_t; + +struct switch_drivers_t{ + /* device */ + int (*get_dev_number) (unsigned int main_dev_id, unsigned int minor_dev_id); + /* fan */ + int (*get_fan_number) (void); + ssize_t (*get_fan_speed) (unsigned int fan_index, unsigned int motor_index, unsigned int *speed); + int (*get_fan_pwm) (unsigned int fan_index, unsigned int motor_index, int *pwm); + int (*set_fan_pwm) (unsigned int fan_index, unsigned int motor_index, int pwm); + int (*get_fan_present_status)(unsigned int fan_index); + int (*get_fan_roll_status)(unsigned int fan_index, unsigned int motor_index); + int (*get_fan_speed_level)(unsigned int fan_index, unsigned int motor_index, int *level); + int (*set_fan_speed_level)(unsigned int fan_index, unsigned int motor_index, int level); + /* slot */ + int (*get_slot_present_status) (unsigned int slot_index); + /* sensors */ + ssize_t (*get_temp_info)( uint8_t main_dev_id, uint8_t dev_index, + uint8_t temp_index, uint8_t temp_attr, char *buf); + ssize_t (*get_voltage_info)( uint8_t main_dev_id, uint8_t dev_index, + uint8_t in_index, uint8_t in_attr, char *buf); + /* psu */ + int (*get_psu_present_status)(unsigned int psu_index); + int (*get_psu_output_status)(unsigned int psu_index); + int (*get_psu_alert_status)(unsigned int psu_index); + /* sff */ + ssize_t (*get_sff_cpld_info)( unsigned int sff_index, int cpld_reg_type, char *buf, int len); + ssize_t (*get_sff_dir_name)(unsigned int sff_index, char *buf, int buf_len); +}; + +extern struct switch_drivers_t * dfd_plat_driver_get(void); + +#endif /*_SYSFS_COMMON_H_ */ diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_sysfs/plat_fan.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_sysfs/plat_fan.c new file mode 100644 index 000000000000..d841f2547b6f --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_sysfs/plat_fan.c @@ -0,0 +1,505 @@ +/* + * plat_fan.c + * Original Author: support 2020-02-17 + * + * This module create fan kobjects and attributes in /sys/wb_plat/fan + * + * History + * [Version] [Author] [Date] [Description] + * * v1.0 support 2020-02-17 Initial version + */ + +#include + +#include "./include/plat_switch.h" +#include "./include/sysfs_common.h" + +#define FAN_INFO(fmt, args...) LOG_INFO("fan: ", fmt, ##args) +#define FAN_ERR(fmt, args...) LOG_ERR("fan: ", fmt, ##args) +#define FAN_DBG(fmt, args...) LOG_DBG("fan: ", fmt, ##args) + +struct motor_obj_t{ + struct switch_obj *obj; +}; + +struct fan_obj_t{ + unsigned int motor_number; + struct motor_obj_t *motor; + struct switch_obj *obj; +}; + +struct fan_t{ + unsigned int fan_number; + struct fan_obj_t *fan; +}; + +static int g_loglevel = 0; +static struct fan_t g_fan; +static struct switch_obj *g_fan_obj = NULL; +static struct switch_drivers_t *g_drv = NULL; + +static ssize_t fan_number_show(struct switch_obj *obj, struct switch_attribute *attr, char *buf) +{ + return (ssize_t)snprintf(buf, PAGE_SIZE, "%d\n", g_fan.fan_number); +} + +static ssize_t fan_motor_number_show(struct switch_obj *obj, struct switch_attribute *attr, char *buf) +{ + unsigned int index; + + index = obj->index; + FAN_DBG("fan_motor_number_show,fan index:%d\n",index); + + return (ssize_t)snprintf(buf, PAGE_SIZE, "%d\n", g_fan.fan[index-1].motor_number); +} + +static ssize_t fan_roll_status_show(struct switch_obj *obj, struct switch_attribute *attr, char *buf) +{ + unsigned int fan_index, motor_index; + struct switch_obj *p_obj; + int ret; + + check_p(g_drv); + check_p(g_drv->get_fan_roll_status); + + p_obj = to_switch_obj(obj->kobj.parent); + check_p(p_obj); + + fan_index = p_obj->index; + motor_index = obj->index; + + ret = g_drv->get_fan_roll_status(fan_index, motor_index); + if (ret < 0 ) { + return (ssize_t)snprintf(buf, PAGE_SIZE, "%s\n", WB_SYSFS_DEV_ERROR); + } + + return (ssize_t)snprintf(buf, PAGE_SIZE, "%d\n", ret); +} + +static ssize_t fan_present_status_show(struct switch_obj *obj, struct switch_attribute *attr, char *buf) +{ + unsigned int fan_index; + int ret; + + fan_index = obj->index; + FAN_DBG("fan_present_status_show, fan index:%d\n",fan_index); + check_p(g_drv); + check_p(g_drv->get_fan_present_status); + + ret = g_drv->get_fan_present_status(fan_index); + if(ret < 0) { + return (ssize_t)snprintf(buf, PAGE_SIZE, "%s\n", WB_SYSFS_DEV_ERROR); + } + + return (ssize_t)snprintf(buf, PAGE_SIZE, "%d\n", ret); +} + +static ssize_t fan_speed_show(struct switch_obj *obj, struct switch_attribute *attr, char *buf) +{ + unsigned int fan_index, motor_index, speed; + int ret; + struct switch_obj *p_obj; + + check_p(g_drv); + check_p(g_drv->get_fan_speed); + + p_obj = to_switch_obj(obj->kobj.parent); + check_p(p_obj); + + fan_index = p_obj->index; + motor_index = obj->index; + + ret = g_drv->get_fan_speed(fan_index, motor_index, &speed); + if(ret < 0) { + return (ssize_t)snprintf(buf, PAGE_SIZE, "%s\n", WB_SYSFS_DEV_ERROR); + } + return (ssize_t)snprintf(buf, PAGE_SIZE, "%d\n", speed); +} + +static ssize_t fan_motor_ratio_show(struct switch_obj *obj, struct switch_attribute *attr, char *buf) +{ + unsigned int fan_index, motor_index; + struct switch_obj *p_obj; + int ret, pwm; + + check_p(g_drv); + check_p(g_drv->get_fan_pwm); + + p_obj = to_switch_obj(obj->kobj.parent); + check_p(p_obj); + fan_index = p_obj->index; + motor_index = obj->index; + ret = g_drv->get_fan_pwm(fan_index, motor_index, &pwm); + + if (ret < 0 ) { + return (ssize_t)snprintf(buf, PAGE_SIZE, "%s\n", WB_SYSFS_DEV_ERROR); + } + return (ssize_t)snprintf(buf, PAGE_SIZE, "%d\n", pwm); +} + +static ssize_t fan_motor_ratio_store(struct switch_obj *obj, struct switch_attribute *attr, + const char* buf, size_t count) +{ + unsigned int fan_index, motor_index; + struct switch_obj *p_obj; + int ret, pwm; + + check_p(g_drv); + check_p(g_drv->set_fan_pwm); + + p_obj = to_switch_obj(obj->kobj.parent); + check_p(p_obj); + + fan_index = p_obj->index; + motor_index = obj->index; + sscanf(buf, "%d", &pwm); + + if (pwm < 0 || pwm > 100) { + FAN_ERR("can not set pwm = %d.\n", pwm); + return -EINVAL; + } + ret = g_drv->set_fan_pwm(fan_index, motor_index, pwm); + if (ret < 0) { + FAN_ERR("can not set pwm = %d.\n", pwm); + return -EIO; + } + return count; +} + +/************************************fan dir and attrs*******************************************/ +static struct switch_attribute fan_number_att = __ATTR(num_fans, S_IRUGO, fan_number_show, NULL); + +static struct attribute *fan_dir_attrs[] = { + &fan_number_att.attr, + NULL, +}; + +static struct attribute_group fan_root_attr_group = { + .attrs = fan_dir_attrs, +}; + +/*******************************fan1 fan2 dir and attrs*******************************************/ +static struct switch_attribute fan_num_motors_att = __ATTR(num_motors, S_IRUGO, fan_motor_number_show, NULL); +static struct switch_attribute fan_present_att = __ATTR(present, S_IRUGO, fan_present_status_show, NULL); + +static struct attribute *fan_attrs[] = { + &fan_num_motors_att.attr, + &fan_present_att.attr, + NULL, +}; + +static struct attribute_group fan_attr_group = { + .attrs = fan_attrs, +}; + +/*******************************motor0 motor1 dir and attrs*******************************************/ +static struct switch_attribute motor_speed_att = __ATTR(speed, S_IRUGO, fan_speed_show, NULL); +static struct switch_attribute motor_status_att = __ATTR(status, S_IRUGO, fan_roll_status_show, NULL); +static struct switch_attribute motor_ratio_att = __ATTR(ratio, S_IRUGO | S_IWUSR, fan_motor_ratio_show, fan_motor_ratio_store); + +static struct attribute *motor_attrs[] = { + &motor_speed_att.attr, + &motor_status_att.attr, + &motor_ratio_att.attr, + NULL, +}; + +static struct attribute_group motor_attr_group = { + .attrs = motor_attrs, +}; + +static void fanindex_single_motor_remove_kobj_and_attrs(struct fan_obj_t * curr_fan, unsigned int motor_index) +{ + struct motor_obj_t *curr_motor; /* point to motor0 motor1...*/ + + curr_motor = &curr_fan->motor[motor_index]; + if (curr_motor->obj) { + sysfs_remove_group(&curr_motor->obj->kobj, &motor_attr_group); + wb_plat_kobject_delete(&curr_motor->obj); + FAN_DBG("delete fan:%d motor%d.\n", curr_fan->obj->index, motor_index); + } + return; +} + +static int fanindex_single_motor_create_kobj_and_attrs(struct fan_obj_t * curr_fan, unsigned int motor_index) +{ + char name[DIR_NAME_MAX_LEN]; + struct motor_obj_t *curr_motor; /* point to motor0 motor1...*/ + + FAN_DBG("create fan_index:%d, motor%d ...\n", curr_fan->obj->index, motor_index); + + curr_motor = &curr_fan->motor[motor_index]; + mem_clear(name, sizeof(name)); + snprintf(name, sizeof(name), "motor%d", motor_index); + curr_motor->obj = wb_plat_kobject_create(name, &curr_fan->obj->kobj); + if (!curr_motor->obj) { + FAN_ERR("create fan_index:%d, motor%d object error!\n", curr_fan->obj->index, motor_index); + return -EBADRQC; + } + curr_motor->obj->index = motor_index; + if (sysfs_create_group(&curr_motor->obj->kobj, &motor_attr_group) != 0) { + FAN_ERR("create fan_index:%d, motor%d attrs error.\n", curr_fan->obj->index, motor_index); + wb_plat_kobject_delete(&curr_motor->obj); + return -EBADRQC; + } + FAN_DBG("create fan_index:%d, motor%d ok.\n", curr_fan->obj->index, motor_index); + return 0; +} + +static int fanindex_motor_create_kobj_and_attrs(struct fan_obj_t * curr_fan, int motor_num) +{ + int motor_index, i; + + curr_fan->motor = kzalloc(sizeof(struct motor_obj_t) * motor_num, GFP_KERNEL); + if (!curr_fan->motor) { + FAN_ERR("kzalloc motor error, fan index = %d, motor number = %d.\n", curr_fan->obj->index, motor_num); + return -ENOMEM; + } + curr_fan->motor_number = motor_num; + for (motor_index = 0; motor_index < motor_num; motor_index++) { + if (fanindex_single_motor_create_kobj_and_attrs(curr_fan, motor_index) != 0) { + goto motor_error; + } + } + return 0; +motor_error: + for(i = motor_index - 1; i >= 0; i--) { + fanindex_single_motor_remove_kobj_and_attrs(curr_fan, i); + } + if(curr_fan->motor) { + kfree(curr_fan->motor); + curr_fan->motor = NULL; + } + return -EBADRQC; +} + +static void fanindex_motor_remove_kobj_and_attrs(struct fan_obj_t *curr_fan, int motor_num) +{ + int motor_index; + + for (motor_index = motor_num - 1; motor_index >= 0; motor_index--) { + fanindex_single_motor_remove_kobj_and_attrs(curr_fan, motor_index); + } + return; +} + +static int fan_motor_create(void) +{ + int fan_num, motor_num; + unsigned int fan_index, i; + struct fan_obj_t *curr_fan; /* point to fan1 fan2...*/ + + check_p(g_drv->get_dev_number); + + motor_num = g_drv->get_dev_number(WB_MAIN_DEV_FAN, WB_MINOR_DEV_MOTOR); + if (motor_num <= 0) { + FAN_ERR("get fan motor number error, motor_num:%d error.\n", motor_num); + return -ENODEV; + } + + fan_num = g_fan.fan_number; + for (fan_index = 1; fan_index <= fan_num; fan_index++) { + curr_fan = &g_fan.fan[fan_index - 1]; + if (fanindex_motor_create_kobj_and_attrs(curr_fan, motor_num) != 0) { + goto error; + } + } + return 0; +error: + for (i = fan_index - 1; i > 0; i--) { + curr_fan = &g_fan.fan[i - 1]; + motor_num = curr_fan->motor_number; + fanindex_motor_remove_kobj_and_attrs(curr_fan, motor_num); + } + return -EBADRQC; +} + +static void fan_motor_remove(void) +{ + unsigned int fan_index; + struct fan_obj_t *curr_fan; + + if (g_fan.fan) { + for (fan_index = g_fan.fan_number; fan_index > 0; fan_index--) { + curr_fan = &g_fan.fan[fan_index - 1]; + if (curr_fan->motor) { + fanindex_motor_remove_kobj_and_attrs(curr_fan, curr_fan->motor_number); + kfree(curr_fan->motor); + curr_fan->motor = NULL; + curr_fan->motor_number = 0; + } + } + } + return; +} + +static void fan_sub_single_remove_kobj_and_attrs(unsigned int index) +{ + struct fan_obj_t *curr_fan; + + curr_fan = &g_fan.fan[index - 1]; + if (curr_fan->obj) { + sysfs_remove_group(&curr_fan->obj->kobj, &fan_attr_group); + wb_plat_kobject_delete(&curr_fan->obj); + FAN_DBG("delete fan%d.\n", index); + } + return; +} + +static int fan_sub_single_create_kobj_and_attrs(struct kobject *parent, unsigned int index) +{ + char name[DIR_NAME_MAX_LEN]; + struct fan_obj_t *curr_fan; + + curr_fan = &g_fan.fan[index - 1]; + FAN_DBG("create fan%d ...\n", index); + mem_clear(name, sizeof(name)); + snprintf(name, sizeof(name), "fan%d", index); + curr_fan->obj = wb_plat_kobject_create(name, parent); + if (!curr_fan->obj) { + FAN_ERR("create fan%d object error!\n", index); + return -EBADRQC; + } + curr_fan->obj->index = index; + if (sysfs_create_group(&curr_fan->obj->kobj, &fan_attr_group) != 0) { + FAN_ERR("create fan%d attrs error.\n", index); + wb_plat_kobject_delete(&curr_fan->obj); + return -EBADRQC; + } + FAN_DBG("create fan%d ok.\n", index); + return 0; +} + +static int fan_sub_create_kobj_and_attrs(struct kobject *parent, int fan_num) +{ + unsigned int fan_index, i; + + g_fan.fan = kzalloc(sizeof(struct fan_obj_t) * fan_num, GFP_KERNEL); + if (!g_fan.fan) { + FAN_ERR("kzalloc fan.fan error, fan number = %d.\n", fan_num); + return -ENOMEM; + } + + for (fan_index = 1; fan_index <= fan_num; fan_index++) { + if(fan_sub_single_create_kobj_and_attrs(parent, fan_index) != 0 ) { + goto error; + } + } + return 0; +error: + for (i = fan_index - 1; i > 0; i--) { + fan_sub_single_remove_kobj_and_attrs(i); + } + if (g_fan.fan) { + kfree(g_fan.fan); + g_fan.fan = NULL; + } + return -EBADRQC; +} + +static int fan_sub_create(void) +{ + int ret, fan_num; + + check_p(g_drv->get_dev_number); + fan_num = g_drv->get_dev_number(WB_MAIN_DEV_FAN, WB_MINOR_DEV_NONE); + if (fan_num < 0) { + FAN_ERR("fan number = %d error.\n", fan_num); + return -EINVAL; + } + g_fan.fan_number = fan_num; + ret = fan_sub_create_kobj_and_attrs(&g_fan_obj->kobj, fan_num); + return ret; +} + +static void fan_sub_remove(void) +{ + unsigned int fan_index; + + if (g_fan.fan) { + for (fan_index = g_fan.fan_number; fan_index > 0; fan_index--) { + fan_sub_single_remove_kobj_and_attrs(fan_index); + } + kfree(g_fan.fan); + } + mem_clear(&g_fan, sizeof(struct fan_t)); + return; +} + +static int fan_root_create(void) +{ + g_fan_obj = wb_plat_kobject_create("fan", NULL); + if (!g_fan_obj) { + FAN_ERR("wb_plat_kobject_create fan error!\n"); + return -ENOMEM; + } + + if (sysfs_create_group(&g_fan_obj->kobj, &fan_root_attr_group) != 0) { + wb_plat_kobject_delete(&g_fan_obj); + FAN_ERR("create fan dir attrs error!\n"); + return -EBADRQC; + } + FAN_DBG("wb_plat_kobject_create fan directory and attribute success.\n"); + return 0; +} + +static void fan_root_remove(void) +{ + if (g_fan_obj) { + sysfs_remove_group(&g_fan_obj->kobj, &fan_root_attr_group); + wb_plat_kobject_delete(&g_fan_obj); + FAN_DBG("delete fan root success\n"); + } + + return; +} + +static int fan_init(void) +{ + int ret; + + FAN_INFO("fan_init...\n"); + g_drv = dfd_plat_driver_get(); + check_p(g_drv); + + ret = fan_root_create(); + if (ret < 0) { + goto fan_root_error; + } + + ret = fan_sub_create(); + if (ret < 0) { + goto fan_sub_error; + } + + ret = fan_motor_create(); + if (ret < 0) { + goto fan_motor_error; + } + + FAN_INFO("fan_init ok.\n"); + return 0; +fan_motor_error: + fan_sub_remove(); +fan_sub_error: + fan_root_remove(); +fan_root_error: + return ret; +} + +static void fan_exit(void) +{ + fan_motor_remove(); + fan_sub_remove(); + fan_root_remove(); + FAN_INFO("fan_exit ok.\n"); + return ; +} + +module_init(fan_init); +module_exit(fan_exit); +module_param(g_loglevel, int, 0644); +MODULE_PARM_DESC(g_loglevel, "the log level(info=0x1, err=0x2, dbg=0x4).\n"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("support"); +MODULE_DESCRIPTION("fan sysfs driver"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_sysfs/plat_psu.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_sysfs/plat_psu.c new file mode 100644 index 000000000000..af3b414314ff --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_sysfs/plat_psu.c @@ -0,0 +1,430 @@ +/* + * plat_psu.c + * Original Author: support 2020-02-17 + * + * This module create psu kobjects and attributes in /sys/wb_plat/psu + * + * History + * [Version] [Author] [Date] [Description] + * * v1.0 support 2020-02-17 Initial version + */ + +#include + +#include "./include/plat_switch.h" +#include "./include/sysfs_common.h" + +#define PSU_INFO(fmt, args...) LOG_INFO("psu: ", fmt, ##args) +#define PSU_ERR(fmt, args...) LOG_ERR("psu: ", fmt, ##args) +#define PSU_DBG(fmt, args...) LOG_DBG("psu: ", fmt, ##args) + +struct temp_obj_t{ + struct switch_obj *obj; +}; + +struct psu_obj_t{ + unsigned int temp_number; + struct temp_obj_t *temp; + struct switch_obj *obj; +}; + +struct psu_t{ + unsigned int psu_number; + struct psu_obj_t *psu; +}; + +static int g_loglevel = 0; +static struct psu_t g_psu; +static struct switch_obj *g_psu_obj = NULL; +static struct switch_drivers_t *g_drv = NULL; + +static ssize_t psu_number_show(struct switch_obj *obj, struct switch_attribute *attr, char *buf) +{ + return (ssize_t)snprintf(buf, PAGE_SIZE, "%d\n", g_psu.psu_number); +} + +static ssize_t psu_present_status_show(struct switch_obj *obj, struct switch_attribute *attr, char *buf) +{ + unsigned int psu_index; + int ret; + + psu_index = obj->index; + PSU_DBG("psu_present_status_show, psu index:%d\n",psu_index); + check_p(g_drv); + check_p(g_drv->get_psu_present_status); + + ret = g_drv->get_psu_present_status(psu_index); + if(ret < 0) { + return (ssize_t)snprintf(buf, PAGE_SIZE, "%s\n", WB_SYSFS_DEV_ERROR); + } + + return (ssize_t)snprintf(buf, PAGE_SIZE, "%d\n", ret); +} + +static ssize_t psu_output_status_show(struct switch_obj *obj, struct switch_attribute *attr, char *buf) +{ + unsigned int psu_index; + int ret; + + psu_index = obj->index; + PSU_DBG("psu_output_status_show, psu index:%d\n",psu_index); + check_p(g_drv); + check_p(g_drv->get_psu_output_status); + + ret = g_drv->get_psu_output_status(psu_index); + if(ret < 0) { + return (ssize_t)snprintf(buf, PAGE_SIZE, "%s\n", WB_SYSFS_DEV_ERROR); + } + + return (ssize_t)snprintf(buf, PAGE_SIZE, "%d\n", ret); +} + +static ssize_t psu_alert_status_show(struct switch_obj *obj, struct switch_attribute *attr, char *buf) +{ + unsigned int psu_index; + int ret; + + psu_index = obj->index; + PSU_DBG("psu_alert_status_show, psu index:%d\n",psu_index); + check_p(g_drv); + check_p(g_drv->get_psu_alert_status); + + ret = g_drv->get_psu_alert_status(psu_index); + if(ret < 0) { + return (ssize_t)snprintf(buf, PAGE_SIZE, "%s\n", WB_SYSFS_DEV_ERROR); + } + + return (ssize_t)snprintf(buf, PAGE_SIZE, "%d\n", ret); +} + +/************************************psu dir and attrs*******************************************/ +static struct switch_attribute psu_number_att = __ATTR(num_psus, S_IRUGO, psu_number_show, NULL); + +static struct attribute *psu_dir_attrs[] = { + &psu_number_att.attr, + NULL, +}; + +static struct attribute_group psu_root_attr_group = { + .attrs = psu_dir_attrs, +}; + +/*******************************psu1 psu2 dir and attrs*******************************************/ +static struct switch_attribute psu_present_status_att = __ATTR(present, S_IRUGO, psu_present_status_show, NULL); +static struct switch_attribute psu_output_status_att = __ATTR(output, S_IRUGO, psu_output_status_show, NULL); +static struct switch_attribute psu_alert_status_att = __ATTR(alert, S_IRUGO, psu_alert_status_show, NULL); + +static struct attribute *psu_attrs[] = { + &psu_present_status_att.attr, + &psu_output_status_att.attr, + &psu_alert_status_att.attr, + NULL, +}; + +static struct attribute_group psu_attr_group = { + .attrs = psu_attrs, +}; + +/*******************************psu temp0 temp1 dir and attrs*******************************************/ +static struct attribute *psu_temp_attrs[] = { + NULL, +}; + +static struct attribute_group psu_temp_attr_group = { + .attrs = psu_temp_attrs, +}; + +static void psuindex_single_temp_remove_kobj_and_attrs(struct psu_obj_t * curr_psu, unsigned int temp_index) +{ + + struct temp_obj_t *curr_temp; /* point to temp0 temp1...*/ + + curr_temp = &curr_psu->temp[temp_index]; + if (curr_temp->obj) { + sysfs_remove_group(&curr_temp->obj->kobj, &psu_temp_attr_group); + wb_plat_kobject_delete(&curr_temp->obj); + PSU_DBG("delete psu:%d temp%d.\n", curr_psu->obj->index, temp_index); + } + return; +} + +static int psuindex_single_temp_create_kobj_and_attrs(struct psu_obj_t * curr_psu, unsigned int temp_index) +{ + char name[DIR_NAME_MAX_LEN]; + struct temp_obj_t *curr_temp; /* point to temp0 temp1...*/ + + PSU_DBG("create psu_index:%d, temp%d ...\n", curr_psu->obj->index, temp_index); + + curr_temp = &curr_psu->temp[temp_index]; + mem_clear(name, sizeof(name)); + snprintf(name, sizeof(name), "temp%d", temp_index); + curr_temp->obj = wb_plat_kobject_create(name, &curr_psu->obj->kobj); + if (!curr_temp->obj) { + PSU_ERR("create psu_index:%d, temp%d object error!\n", curr_psu->obj->index, temp_index); + return -EBADRQC; + } + curr_temp->obj->index = temp_index; + if (sysfs_create_group(&curr_temp->obj->kobj, &psu_temp_attr_group) != 0) { + PSU_ERR("create psu_index:%d, temp%d attrs error.\n", curr_psu->obj->index, temp_index); + wb_plat_kobject_delete(&curr_temp->obj); + return -EBADRQC; + } + PSU_DBG("create psu_index:%d, temp%d ok.\n", curr_psu->obj->index, temp_index); + return 0; +} + +static int psuindex_temp_create_kobj_and_attrs(struct psu_obj_t * curr_psu, int temp_num) +{ + int temp_index, i; + + curr_psu->temp = kzalloc(sizeof(struct temp_obj_t) * temp_num, GFP_KERNEL); + if (!curr_psu->temp) { + PSU_ERR("kzalloc temp error, psu index = %d, temp number = %d.\n", curr_psu->obj->index, temp_num); + return -ENOMEM; + } + curr_psu->temp_number = temp_num; + for (temp_index = 0; temp_index < temp_num; temp_index++) { + if (psuindex_single_temp_create_kobj_and_attrs(curr_psu, temp_index) != 0) { + goto temp_error; + } + } + return 0; +temp_error: + for (i = temp_index - 1; i >= 0; i--) { + psuindex_single_temp_remove_kobj_and_attrs(curr_psu, i); + } + if (curr_psu->temp) { + kfree(curr_psu->temp); + curr_psu->temp = NULL; + } + return -EBADRQC; +} + +static void psuindex_temp_remove_kobj_and_attrs(struct psu_obj_t * curr_psu, int temp_num) +{ + unsigned int temp_index; + + for (temp_index = temp_num - 1; temp_index >= 0; temp_index--) { + psuindex_single_temp_remove_kobj_and_attrs(curr_psu, temp_index); + } + return; +} + +static int psu_temp_create(void) +{ + int psu_num, temp_num; + unsigned int psu_index, i; + struct psu_obj_t *curr_psu; /* point to psu1 psu2...*/ + + check_p(g_drv->get_dev_number); + temp_num = g_drv->get_dev_number(WB_MAIN_DEV_PSU, WB_MINOR_DEV_TEMP); + if (temp_num <= 0) { + PSU_INFO("psu temp_num:%d, don't need creat temp directory.\n", temp_num); + return 0; + } + + psu_num = g_psu.psu_number; + for(psu_index = 1; psu_index <= psu_num; psu_index++) { + curr_psu = &g_psu.psu[psu_index - 1]; + if(psuindex_temp_create_kobj_and_attrs(curr_psu, temp_num) != 0) { + goto error; + } + } + return 0; +error: + for(i = psu_index - 1; i > 0; i--) { + curr_psu = &g_psu.psu[i - 1]; + temp_num = curr_psu->temp_number; + psuindex_temp_remove_kobj_and_attrs(curr_psu, temp_num); + } + return -EBADRQC; +} + +static void psu_temp_remove(void) +{ + unsigned int psu_index; + struct psu_obj_t *curr_psu; + + if (g_psu.psu) { + for (psu_index = g_psu.psu_number; psu_index > 0; psu_index--) { + curr_psu = &g_psu.psu[psu_index - 1]; + if (curr_psu->temp) { + psuindex_temp_remove_kobj_and_attrs(curr_psu,curr_psu->temp_number); + kfree(curr_psu->temp); + curr_psu->temp = NULL; + curr_psu->temp_number = 0; + } + } + } + return; +} + +static void psu_sub_single_remove_kobj_and_attrs(unsigned int index) +{ + struct psu_obj_t *curr_psu; + + curr_psu = &g_psu.psu[index - 1]; + if (curr_psu->obj) { + sysfs_remove_group(&curr_psu->obj->kobj, &psu_attr_group); + wb_plat_kobject_delete(&curr_psu->obj); + PSU_DBG("delete psu%d.\n", index); + } + return; +} + +static int psu_sub_single_create_kobj_and_attrs(struct kobject *parent, unsigned int index) +{ + char name[DIR_NAME_MAX_LEN]; + struct psu_obj_t *curr_psu; + + curr_psu = &g_psu.psu[index-1]; + PSU_DBG("create psu%d ...\n", index); + mem_clear(name, sizeof(name)); + snprintf(name, sizeof(name), "%s%d",PSU_SYSFS_NAME, index); + curr_psu->obj = wb_plat_kobject_create(name, parent); + if (!curr_psu->obj) { + PSU_ERR("create psu%d object error!\n", index); + return -EBADRQC; + } + curr_psu->obj->index = index; + if (sysfs_create_group(&curr_psu->obj->kobj, &psu_attr_group) != 0) { + PSU_ERR("create psu%d attrs error.\n", index); + wb_plat_kobject_delete(&curr_psu->obj); + return -EBADRQC; + } + PSU_DBG("create psu%d ok.\n", index); + return 0; +} + +static int psu_sub_create_kobj_and_attrs(struct kobject *parent, int psu_num) +{ + unsigned int psu_index, i; + + g_psu.psu = kzalloc(sizeof(struct psu_obj_t) * psu_num, GFP_KERNEL); + if (!g_psu.psu) { + PSU_ERR("kzalloc psu.psu error, psu number = %d.\n", psu_num); + return -ENOMEM; + } + + for (psu_index = 1; psu_index <= psu_num; psu_index++) { + if (psu_sub_single_create_kobj_and_attrs(parent, psu_index) != 0) { + goto error; + } + } + return 0; +error: + for(i = psu_index - 1; i > 0; i--) { + psu_sub_single_remove_kobj_and_attrs(i); + } + if(g_psu.psu) { + kfree(g_psu.psu); + g_psu.psu = NULL; + } + return -EBADRQC; +} + +static int psu_sub_create(void) +{ + int ret, psu_num; + + check_p(g_drv->get_dev_number); + psu_num = g_drv->get_dev_number(WB_MAIN_DEV_PSU, WB_MINOR_DEV_NONE); + if (psu_num < 0) { + PSU_ERR("psu number = %d error.\n", psu_num); + return -EINVAL; + } + g_psu.psu_number = psu_num; + ret = psu_sub_create_kobj_and_attrs(&g_psu_obj->kobj, psu_num); + return ret; +} + +static void psu_sub_remove(void) +{ + unsigned int psu_index; + + if (g_psu.psu) { + for (psu_index = g_psu.psu_number; psu_index > 0; psu_index--) { + psu_sub_single_remove_kobj_and_attrs(psu_index); + } + kfree(g_psu.psu); + } + mem_clear(&g_psu, sizeof(struct psu_t)); + return ; +} + +static int psu_root_create(void) +{ + g_psu_obj = wb_plat_kobject_create(PSU_SYSFS_NAME, NULL); + if (!g_psu_obj) { + PSU_ERR("wb_plat_kobject_create psu error!\n"); + return -ENOMEM; + } + + if (sysfs_create_group(&g_psu_obj->kobj, &psu_root_attr_group) != 0) { + wb_plat_kobject_delete(&g_psu_obj); + PSU_ERR("create psu dir attrs error!\n"); + return -EBADRQC; + } + PSU_DBG("wb_plat_kobject_create psu directory and attribute success.\n"); + return 0; +} + +static void psu_root_remove(void) +{ + if (g_psu_obj) { + sysfs_remove_group(&g_psu_obj->kobj, &psu_root_attr_group); + wb_plat_kobject_delete(&g_psu_obj); + PSU_DBG("delete psu root success\n"); + } + return; +} + +static int wb_psu_init(void) +{ + int ret; + + PSU_INFO("wb_psu_init...\n"); + g_drv = dfd_plat_driver_get(); + check_p(g_drv); + + ret = psu_root_create(); + if (ret < 0) { + goto psu_root_error; + } + + ret = psu_sub_create(); + if (ret < 0) { + goto psu_sub_error; + } + + ret = psu_temp_create(); + if (ret < 0) { + goto psu_temp_error; + } + + PSU_INFO("wb_psu_init ok.\n"); + return 0; +psu_temp_error: + psu_sub_remove(); +psu_sub_error: + psu_root_remove(); +psu_root_error: + return ret; +} + +static void wb_psu_exit(void) +{ + psu_temp_remove(); + psu_sub_remove(); + psu_root_remove(); + PSU_INFO("wb_psu_exit ok.\n"); + return ; +} + +module_init(wb_psu_init); +module_exit(wb_psu_exit); +module_param(g_loglevel, int, 0644); +MODULE_PARM_DESC(g_loglevel, "the log level(info=0x1, err=0x2, dbg=0x4).\n"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("support"); +MODULE_DESCRIPTION("psu sysfs driver"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_sysfs/plat_sensor.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_sysfs/plat_sensor.c new file mode 100644 index 000000000000..04b764e82df9 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_sysfs/plat_sensor.c @@ -0,0 +1,457 @@ +/* + * plat_sensor.c + * Original Author: support 2020-02-17 + * + * This module create sensor kobjects and attributes in /sys/wb_plat/sensor + * + * History + * [Version] [Author] [Date] [Description] + * * v1.0 support 2020-02-17 Initial version + */ + +#include + +#include "./include/plat_switch.h" +#include "./include/sysfs_common.h" + +#define SENSOR_INFO(fmt, args...) LOG_INFO("sensor: ", fmt, ##args) +#define SENSOR_ERR(fmt, args...) LOG_ERR("sensor: ", fmt, ##args) +#define SENSOR_DBG(fmt, args...) LOG_DBG("sensor: ", fmt, ##args) + +struct sensor_t { + unsigned int in_number; + unsigned int temp_number; + struct sensor_in_t *in; + struct sensor_temp_t *temp; +}; + +struct sensor_temp_t { + struct switch_obj *obj; +}; + +struct sensor_in_t { + struct switch_obj *obj; +}; + +static int g_loglevel = 0; +static struct switch_drivers_t *g_drv = NULL; +static struct sensor_t g_sensor; +static struct switch_obj *g_sensor_obj = NULL; + +static ssize_t sensor_temp_number_show(struct switch_obj *obj, struct switch_attribute *attr, char *buf) +{ + return (ssize_t)snprintf(buf, PAGE_SIZE, "%d\n", g_sensor.temp_number); +} + +static ssize_t sensor_in_number_show(struct switch_obj *obj, struct switch_attribute *attr, char *buf) +{ + return (ssize_t)snprintf(buf, PAGE_SIZE, "%d\n", g_sensor.in_number); +} + +static ssize_t sensor_voltage_show(struct switch_obj *obj, struct switch_attribute *attr, char *buf) +{ + unsigned int in_index; + int ret; + struct switch_device_attribute *in_attr; + + check_p(g_drv); + check_p(g_drv->get_voltage_info); + in_index = obj->index; + + in_attr = to_switch_device_attr(attr); + check_p(in_attr); + SENSOR_DBG("sensor_in_show, in index:0x%x, in type:0x%x\n",in_index, in_attr->type); + ret = g_drv->get_voltage_info(WB_MAIN_DEV_MAINBOARD, WB_MINOR_DEV_NONE, in_index, in_attr->type, buf); + if (ret < 0) { + return (ssize_t)snprintf(buf, PAGE_SIZE, "%s\n", WB_SYSFS_DEV_ERROR); + } + return ret; +} + +static ssize_t sensor_temp_show(struct switch_obj *obj, struct switch_attribute *attr, char *buf) +{ + unsigned int temp_index; + int ret; + struct switch_device_attribute *temp_attr; + + check_p(g_drv); + check_p(g_drv->get_temp_info); + temp_index = obj->index; + + temp_attr = to_switch_device_attr(attr); + check_p(temp_attr); + SENSOR_DBG("sensor_temp_show, temp index:0x%x, temp type:0x%x\n", temp_index, temp_attr->type); + ret = g_drv->get_temp_info(WB_MAIN_DEV_MAINBOARD, WB_MINOR_DEV_NONE, temp_index, temp_attr->type, buf); + if (ret < 0) { + return (ssize_t)snprintf(buf, PAGE_SIZE, "%s\n", WB_SYSFS_DEV_ERROR); + } + return ret; +} + +/************************************sensor dir and attrs*******************************************/ +static struct switch_attribute num_temp_att = __ATTR(num_temp_sensors, S_IRUGO, sensor_temp_number_show, NULL); +static struct switch_attribute num_in_att = __ATTR(num_in_sensors, S_IRUGO, sensor_in_number_show, NULL); + +static struct attribute *sensor_dir_attrs[] = { + &num_temp_att.attr, + &num_in_att.attr, + NULL, +}; + +static struct attribute_group sensor_root_attr_group = { + .attrs = sensor_dir_attrs, +}; + +/*******************************temp0 temp1 dir and attrs*******************************************/ +static SWITCH_DEVICE_ATTR(temp_input, S_IRUGO, sensor_temp_show, NULL, WB_SENSOR_INPUT); +static SWITCH_DEVICE_ATTR(temp_alias, S_IRUGO, sensor_temp_show, NULL, WB_SENSOR_ALIAS); +static SWITCH_DEVICE_ATTR(temp_type, S_IRUGO, sensor_temp_show, NULL, WB_SENSOR_TYPE); +static SWITCH_DEVICE_ATTR(temp_max, S_IRUGO, sensor_temp_show, NULL, WB_SENSOR_MAX); +static SWITCH_DEVICE_ATTR(temp_max_hyst, S_IRUGO, sensor_temp_show, NULL, WB_SENSOR_MAX_HYST); +static SWITCH_DEVICE_ATTR(temp_min, S_IRUGO, sensor_temp_show, NULL, WB_SENSOR_MIN); + +static struct attribute *sensor_temp_attrs[] = { + &switch_dev_attr_temp_input.switch_attr.attr, + &switch_dev_attr_temp_alias.switch_attr.attr, + &switch_dev_attr_temp_type.switch_attr.attr, + &switch_dev_attr_temp_max.switch_attr.attr, + &switch_dev_attr_temp_max_hyst.switch_attr.attr, + &switch_dev_attr_temp_min.switch_attr.attr, + NULL, +}; + +static struct attribute_group sensor_temp_attr_group = { + .attrs = sensor_temp_attrs, +}; + +/*******************************in0 in1 dir and attrs*******************************************/ +static SWITCH_DEVICE_ATTR(in_input, S_IRUGO, sensor_voltage_show, NULL, WB_SENSOR_INPUT); +static SWITCH_DEVICE_ATTR(in_alias, S_IRUGO, sensor_voltage_show, NULL, WB_SENSOR_ALIAS); +static SWITCH_DEVICE_ATTR(in_type, S_IRUGO, sensor_voltage_show, NULL, WB_SENSOR_TYPE); +static SWITCH_DEVICE_ATTR(in_max, S_IRUGO, sensor_voltage_show, NULL, WB_SENSOR_MAX); +static SWITCH_DEVICE_ATTR(in_min, S_IRUGO, sensor_voltage_show, NULL, WB_SENSOR_MIN); +static SWITCH_DEVICE_ATTR(in_crit, S_IRUGO, sensor_voltage_show, NULL, WB_SENSOR_CRIT); + +static struct attribute *sensor_in_attrs[] = { + &switch_dev_attr_in_input.switch_attr.attr, + &switch_dev_attr_in_alias.switch_attr.attr, + &switch_dev_attr_in_type.switch_attr.attr, + &switch_dev_attr_in_max.switch_attr.attr, + &switch_dev_attr_in_min.switch_attr.attr, + &switch_dev_attr_in_crit.switch_attr.attr, + NULL, +}; + +static struct attribute_group sensor_in_attr_group = { + .attrs = sensor_in_attrs, +}; + +static int sensor_in_sub_single_create_kobj_and_attrs(struct kobject *parent, unsigned int index) +{ + char name[DIR_NAME_MAX_LEN]; + struct sensor_in_t *curr_sensor; + + curr_sensor = &g_sensor.in[index - 1]; + SENSOR_DBG("create sensor in%d ...\n", index); + mem_clear(name, sizeof(name)); + snprintf(name, sizeof(name), "in%d", index); + curr_sensor->obj = wb_plat_kobject_create(name, parent); + if (!curr_sensor->obj) { + SENSOR_ERR("create sensor in%d object error!\n", index); + return -EBADRQC; + } + curr_sensor->obj->index = index; + if (sysfs_create_group(&curr_sensor->obj->kobj, &sensor_in_attr_group) != 0) { + SENSOR_ERR("create sensor in%d attrs error.\n", index); + wb_plat_kobject_delete(&curr_sensor->obj); + return -EBADRQC; + } + SENSOR_DBG("create sensor in%d ok.\n", index); + return 0; + +} + +static void sensor_in_sub_single_remove_kobj_and_attrs(unsigned int index) +{ + struct sensor_in_t *curr_in; + + curr_in = &g_sensor.in[index - 1]; + if (curr_in->obj) { + sysfs_remove_group(&curr_in->obj->kobj, &sensor_in_attr_group); + wb_plat_kobject_delete(&curr_in->obj); + SENSOR_DBG("delete in%d.\n", index); + } + return; +} + +static int sensor_temp_sub_single_create_kobj_and_attrs(struct kobject *parent, unsigned int index) +{ + char name[DIR_NAME_MAX_LEN]; + struct sensor_temp_t *curr_sensor; + + curr_sensor = &g_sensor.temp[index - 1]; + SENSOR_DBG("create sensor temp%d ...\n", index); + mem_clear(name, sizeof(name)); + snprintf(name, sizeof(name), "temp%d", index); + curr_sensor->obj = wb_plat_kobject_create(name, parent); + if (!curr_sensor->obj) { + SENSOR_ERR("create sensor temp%d object error!\n", index); + return -EBADRQC; + } + curr_sensor->obj->index = index; + if (sysfs_create_group(&curr_sensor->obj->kobj, &sensor_temp_attr_group) != 0) { + SENSOR_ERR("create sensor temp%d attrs error.\n", index); + wb_plat_kobject_delete(&curr_sensor->obj); + return -EBADRQC; + } + SENSOR_DBG("create sensor temp%d ok.\n", index); + return 0; + +} + +static void sensor_temp_sub_single_remove_kobj_and_attrs(unsigned int index) +{ + struct sensor_temp_t *curr_temp; + + curr_temp = &g_sensor.temp[index - 1]; + if (curr_temp->obj) { + sysfs_remove_group(&curr_temp->obj->kobj, &sensor_temp_attr_group); + wb_plat_kobject_delete(&curr_temp->obj); + SENSOR_DBG("delete temp%d.\n", index); + } + return; +} + +static int sensor_temp_sub_create_kobj_and_attrs(struct kobject *parent, int temp_num) +{ + unsigned int temp_index, i; + + g_sensor.temp = kzalloc(sizeof(struct sensor_temp_t) * temp_num, GFP_KERNEL); + if (!g_sensor.temp ) { + SENSOR_ERR("kzalloc g_sensor.temp error, temp number = %d.\n", temp_num); + return -ENOMEM; + } + for (temp_index = 1; temp_index <= temp_num; temp_index++) { + if (sensor_temp_sub_single_create_kobj_and_attrs(parent, temp_index) != 0 ) { + goto error; + } + } + return 0; +error: + for (i = temp_index - 1; i > 0; i--) { + sensor_temp_sub_single_remove_kobj_and_attrs(i); + } + + if (g_sensor.temp) { + kfree(g_sensor.temp); + g_sensor.temp = NULL; + } + return -EBADRQC; +} + +static int sensor_in_sub_create_kobj_and_attrs(struct kobject *parent, int in_num) +{ + unsigned int in_index, i; + + g_sensor.in = kzalloc(sizeof(struct sensor_in_t) * in_num, GFP_KERNEL); + if (!g_sensor.in) { + SENSOR_ERR("kzalloc g_sensor.in error, in number = %d.\n", in_num); + return -ENOMEM; + } + + for (in_index = 1; in_index <= in_num; in_index++) { + if (sensor_in_sub_single_create_kobj_and_attrs(parent, in_index) != 0 ) { + goto error; + } + } + return 0; +error: + for (i = in_index - 1; i > 0; i--) { + sensor_in_sub_single_remove_kobj_and_attrs(i); + } + + if (g_sensor.in) { + kfree(g_sensor.in); + g_sensor.in = NULL; + } + return -EBADRQC; +} + +static int sensor_temp_sub_create(void) +{ + int ret, temp_num; + + check_p(g_drv->get_dev_number); + temp_num = g_drv->get_dev_number(WB_MAIN_DEV_MAINBOARD, WB_MINOR_DEV_TEMP); + g_sensor.temp_number = temp_num; + if (temp_num <= 0) { + SENSOR_DBG("Warning:sensor temp number = %d \n", temp_num); + return 0; + } + ret = sensor_temp_sub_create_kobj_and_attrs(&g_sensor_obj->kobj, temp_num); + return ret; +} + +static int sensor_in_sub_create(void) +{ + int ret, in_num; + + check_p(g_drv->get_dev_number); + in_num = g_drv->get_dev_number(WB_MAIN_DEV_MAINBOARD, WB_MINOR_DEV_IN); + g_sensor.in_number = in_num; + + if (in_num <= 0) { + SENSOR_DBG("Warning:sensor in number = %d \n", in_num); + return 0; + } + ret = sensor_in_sub_create_kobj_and_attrs(&g_sensor_obj->kobj, in_num); + return ret; +} + +static void temp_sub_single_remove_kobj_and_attrs(unsigned int index) +{ + struct sensor_temp_t * curr_temp; + + curr_temp = &g_sensor.temp[index - 1]; + if (curr_temp->obj) { + sysfs_remove_group(&curr_temp->obj->kobj, &sensor_temp_attr_group); + wb_plat_kobject_delete(&curr_temp->obj); + SENSOR_DBG("delete sensor temp%d.\n", index); + } + return; +} + +static void in_sub_single_remove_kobj_and_attrs(unsigned int index) +{ + struct sensor_in_t * curr_in; + + curr_in = &g_sensor.in[index - 1]; + if (curr_in->obj) { + sysfs_remove_group(&curr_in->obj->kobj, &sensor_in_attr_group); + wb_plat_kobject_delete(&curr_in->obj); + SENSOR_DBG("delete sensor in%d.\n", index); + } + return; +} + +static void sensor_temp_sub_remove(void) +{ + unsigned int temp_index; + + if (g_sensor.temp) { + for (temp_index = g_sensor.temp_number; temp_index > 0; temp_index--) { + temp_sub_single_remove_kobj_and_attrs(temp_index); + } + kfree(g_sensor.temp); + g_sensor.temp = NULL; + } + return; +} + +static void sensor_in_sub_remove(void) +{ + unsigned int in_index; + + if (g_sensor.in) { + for (in_index = g_sensor.in_number; in_index > 0; in_index--) { + in_sub_single_remove_kobj_and_attrs(in_index); + } + kfree(g_sensor.in); + g_sensor.in = NULL; + } + return; +} + +static void sensor_sub_remove(void) +{ + sensor_temp_sub_remove(); + sensor_in_sub_remove(); +} + +static int sensor_sub_create(void) +{ + int ret; + /* temp creat */ + ret = sensor_temp_sub_create(); + if (ret < 0) { + goto temp_err; + } + /* Voltage creat */ + ret = sensor_in_sub_create(); + if (ret < 0) { + goto in_err; + } + return 0; +in_err: + sensor_temp_sub_remove(); +temp_err: + return ret; +} +static void sensor_root_remove(void) +{ + if (g_sensor_obj) { + sysfs_remove_group(&g_sensor_obj->kobj, &sensor_root_attr_group); + wb_plat_kobject_delete(&g_sensor_obj); + SENSOR_DBG("delete sensor root success\n"); + } + + return; +} + +static int sensor_root_create(void) +{ + g_sensor_obj = wb_plat_kobject_create("sensor", NULL); + if (!g_sensor_obj) { + SENSOR_ERR("wb_plat_kobject_create sensor error!\n"); + return -ENOMEM; + } + + if (sysfs_create_group(&g_sensor_obj->kobj, &sensor_root_attr_group) != 0) { + wb_plat_kobject_delete(&g_sensor_obj); + SENSOR_ERR("create sensor dir attrs error!\n"); + return -EBADRQC; + } + SENSOR_DBG("wb_plat_kobject_create sensor directory and attribute success.\n"); + return 0; +} + +static int wb_sensor_init(void) +{ + int ret; + + SENSOR_INFO("wb_sensor_init...\n"); + g_drv = dfd_plat_driver_get(); + check_p(g_drv); + + ret = sensor_root_create(); + if (ret < 0) { + goto sensor_root_error; + } + + ret = sensor_sub_create(); + if (ret < 0) { + goto sensor_sub_error; + } + SENSOR_INFO("sensor_init ok.\n"); + return 0; +sensor_sub_error: + sensor_root_remove(); +sensor_root_error: + return ret; +} + +static void wb_sensor_exit(void) +{ + sensor_sub_remove(); + sensor_root_remove(); + SENSOR_INFO("sensor_exit ok.\n"); + return; +} + +module_init(wb_sensor_init); +module_exit(wb_sensor_exit); +module_param(g_loglevel, int, 0644); +MODULE_PARM_DESC(g_loglevel, "the log level(info=0x1, err=0x2, dbg=0x4).\n"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("support"); +MODULE_DESCRIPTION("sensors sysfs driver"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_sysfs/plat_sff.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_sysfs/plat_sff.c new file mode 100644 index 000000000000..8f09c551f62c --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_sysfs/plat_sff.c @@ -0,0 +1,291 @@ +/* + * plat_sff.c + * Original Author: support 2020-02-17 + * + * This module create sff kobjects and attributes in /sys/wb_plat/sff + * + * History + * [Version] [Author] [Date] [Description] + * * v1.0 support 2020-02-17 Initial version + */ + +#include + +#include "./include/plat_switch.h" +#include "./include/sysfs_common.h" + +#define SFF_INFO(fmt, args...) LOG_INFO("sff: ", fmt, ##args) +#define SFF_ERR(fmt, args...) LOG_ERR("sff: ", fmt, ##args) +#define SFF_DBG(fmt, args...) LOG_DBG("sff: ", fmt, ##args) + +struct sff_obj_t{ + struct switch_obj *sff_obj; + struct bin_attribute bin; + int sff_creat_bin_flag; +}; + +struct sff_t{ + unsigned int sff_number; + struct sff_obj_t *sff; +}; + +static int g_loglevel = 0; +static struct sff_t g_sff; +static struct switch_obj *g_sff_obj = NULL; +static struct switch_drivers_t *g_drv = NULL; + +static ssize_t sff_cpld_info_show(struct switch_obj *obj, struct switch_attribute *attr, char *buf) +{ + unsigned int sff_index; + int ret; + struct switch_device_attribute *sff_cpld_attr; + + check_p(g_drv); + check_p(g_drv->get_sff_cpld_info); + + sff_index = obj->index; + sff_cpld_attr = to_switch_device_attr(attr); + check_p(sff_cpld_attr); + SFF_DBG("sff_cpld_info_show, sff index:0x%x, sff cpld attr type:0x%x\n", sff_index, sff_cpld_attr->type); + ret = g_drv->get_sff_cpld_info(sff_index, sff_cpld_attr->type, buf, PAGE_SIZE); + if(ret < 0) { + SFF_ERR("sff_cpld_info_show error. sff index:0x%x, sff cpld attr type:0x%x, ret:%d\n", + sff_index, sff_cpld_attr->type,ret ); + return (ssize_t)snprintf(buf, PAGE_SIZE, "%s\n", WB_SYSFS_DEV_ERROR); + } + SFF_DBG("sff_cpld_info_show ok. sff index:0x%x, sff cpld attr type:0x%x, ret:%d\n", sff_index, sff_cpld_attr->type, ret); + return ret; +} + +static ssize_t sff_number_show(struct switch_obj *obj, struct switch_attribute *attr, char *buf) +{ + return (ssize_t)snprintf(buf, PAGE_SIZE, "%d\n", g_sff.sff_number); +} + +/************************************sff attrs*******************************************/ +static struct switch_attribute sff_number_att = __ATTR(num_sffs, S_IRUGO, sff_number_show, NULL); +static SWITCH_DEVICE_ATTR(present, S_IRUGO, sff_cpld_info_show, NULL, WB_SFF_MODULE_PRESENT); + +/*******************************xcvr dir and attrs*******************************************/ +static struct attribute *xcvr_dir_attrs[] = { + &sff_number_att.attr, + NULL, +}; + +static struct attribute_group sff_xcvr_attr_group = { + .attrs = xcvr_dir_attrs, +}; + +/*******************************sff dir and attrs*******************************************/ +static struct attribute *sff_attrs[] = { + &switch_dev_attr_present.switch_attr.attr, + NULL, +}; + +static struct attribute_group sff_attr_group = { + .attrs = sff_attrs, +}; + +static int sff_sub_single_create_attrs(unsigned int index) +{ + struct sff_obj_t *curr_sff; + + curr_sff = &g_sff.sff[index-1]; + if (sysfs_create_group(&curr_sff->sff_obj->kobj, &sff_attr_group) != 0) { + SFF_ERR("create sff%d dir attrs error!\n", index); + wb_plat_kobject_delete(&curr_sff->sff_obj); + return -EBADRQC; + } + SFF_DBG("create sff%d dir attrs ok!\n", index); + return 0; +} + +static int sff_sub_single_create_kobj(struct kobject *parent, unsigned int index) +{ + struct sff_obj_t *curr_sff; + char sff_dir_name[DIR_NAME_MAX_LEN]; + int ret; + + check_p(g_drv->get_sff_dir_name); + ret = g_drv->get_sff_dir_name(index, sff_dir_name, sizeof(sff_dir_name)); + if (ret < 0) { + SFF_ERR("sff index:%d, get sff dir name error. please check sff config.\n", index); + return -ENOSYS; + } + + curr_sff = &g_sff.sff[index - 1]; + + curr_sff->sff_obj = wb_plat_kobject_create(sff_dir_name, parent); + if (!curr_sff->sff_obj) { + SFF_ERR("sff index:%d, create %s object error! \n", index, sff_dir_name); + return -EBADRQC; + } + + SFF_DBG("create sff kobj ok. sff index:%d, dir name:%s\n",index, sff_dir_name); + curr_sff->sff_obj->index = index; + + return 0; +} + +static void sff_sub_single_remove_kobj_and_attrs(unsigned int index) +{ + struct sff_obj_t *curr_sff; + + curr_sff = &g_sff.sff[index - 1]; + /* remove sff dir and attr */ + if (curr_sff->sff_obj) { + SFF_DBG("delete sff%d attrs.\n", curr_sff->sff_obj->index); + curr_sff->sff_obj->index = 0; + sysfs_remove_group(&curr_sff->sff_obj->kobj, &sff_attr_group); + wb_plat_kobject_delete(&curr_sff->sff_obj); + } + + return; +} + +static int sff_sub_single_create_kobj_and_attrs(struct kobject *parent, unsigned int index) +{ + int ret; + + ret = sff_sub_single_create_kobj(parent, index); + if (ret < 0) { + SFF_ERR("sff index:%d, create sff dir error.\n", index); + return ret; + } + + ret = sff_sub_single_create_attrs(index); + if (ret < 0) { + SFF_ERR("sff index:%d, create sff attr error.\n", index); + return ret; + } + return 0; +} + +static int sff_sub_create_kobj_and_attrs(struct kobject *parent, int sff_num) +{ + unsigned int sff_index, i; + + g_sff.sff = kzalloc(sizeof(struct sff_obj_t) * sff_num, GFP_KERNEL); + if (!g_sff.sff) { + SFF_ERR("kzalloc g_sff.sff error, sff number = %d.\n", sff_num); + return -ENOMEM; + } + + for (sff_index = 1; sff_index <= sff_num; sff_index++) { + if (sff_sub_single_create_kobj_and_attrs(parent, sff_index) != 0 ) { + goto error; + } + } + return 0; +error: + for (i = sff_index - 1; i > 0; i--) { + sff_sub_single_remove_kobj_and_attrs(i); + } + if (g_sff.sff) { + kfree(g_sff.sff); + g_sff.sff = NULL; + } + return -EBADRQC; +} + +static int sff_sub_create(void) +{ + int ret, sff_num; + + check_p(g_drv->get_dev_number); + sff_num = g_drv->get_dev_number(WB_MAIN_DEV_SFF, WB_MINOR_DEV_NONE); + g_sff.sff_number = sff_num; + if (sff_num <= 0) { + SFF_ERR("ERROR. port number:%d\n", sff_num); + return -EINVAL; + } + + ret = sff_sub_create_kobj_and_attrs(&g_sff_obj->kobj, sff_num); + + return ret; +} + +static void sff_sub_remove(void) +{ + unsigned int sff_index; + + if (g_sff.sff) { + for (sff_index = g_sff.sff_number; sff_index > 0; sff_index--) { + sff_sub_single_remove_kobj_and_attrs(sff_index); + } + kfree(g_sff.sff); + } + mem_clear(&g_sff, sizeof(struct sff_t)); + return ; +} + +static int sff_xcvr_create(void) +{ + g_sff_obj = wb_plat_kobject_create(SFF_SYSFS_NAME, NULL); + if (!g_sff_obj) { + SFF_ERR("wb_plat_kobject_create sff error!\n"); + return -ENOMEM; + } + + g_sff_obj->index = 0; + if (sysfs_create_group(&g_sff_obj->kobj, &sff_xcvr_attr_group) != 0) { + wb_plat_kobject_delete(&g_sff_obj); + SFF_ERR("create sff dir attrs error!\n"); + return -EBADRQC; + } + SFF_DBG("wb_plat_kobject_create sff directory and attribute success.\n"); + return 0; +} + +static void sff_xcvr_remove(void) +{ + if (g_sff_obj) { + sysfs_remove_group(&g_sff_obj->kobj, &sff_xcvr_attr_group); + wb_plat_kobject_delete(&g_sff_obj); + SFF_DBG("delete sff root success\n"); + } + + return; +} + +static int wb_sff_init(void) +{ + int ret; + + SFF_INFO("wb_sff_init...\n"); + g_drv = dfd_plat_driver_get(); + check_p(g_drv); + + ret = sff_xcvr_create(); + if (ret < 0) { + goto sff_root_error; + } + + ret = sff_sub_create(); + if (ret < 0) { + goto sff_sub_error; + } + SFF_INFO("wb_sff_init ok.\n"); + return 0; + +sff_sub_error: + sff_xcvr_remove(); +sff_root_error: + return ret; +} + +static void wb_sff_exit(void) +{ + sff_sub_remove(); + sff_xcvr_remove(); + SFF_INFO("wb_sff_exit ok.\n"); + return ; +} + +module_init(wb_sff_init); +module_exit(wb_sff_exit); +module_param(g_loglevel, int, 0644); +MODULE_PARM_DESC(g_loglevel, "the log level(info=0x1, err=0x2, dbg=0x4).\n"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("support"); +MODULE_DESCRIPTION("sff sysfs driver"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_sysfs/plat_slot.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_sysfs/plat_slot.c new file mode 100644 index 000000000000..97539a4c24cc --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_sysfs/plat_slot.c @@ -0,0 +1,667 @@ +/* + * plat_slot.c + * Original Author: support 2020-02-17 + * + * This module create sff kobjects and attributes in /sys/wb_plat/slot + * + * History + * [Version] [Author] [Date] [Description] + * * v1.0 support 2020-02-17 Initial version + */ + +#include + +#include "./include/plat_switch.h" +#include "./include/sysfs_common.h" + +#define SLOT_INFO(fmt, args...) LOG_INFO("slot: ", fmt, ##args) +#define SLOT_ERR(fmt, args...) LOG_ERR("slot: ", fmt, ##args) +#define SLOT_DBG(fmt, args...) LOG_DBG("slot: ", fmt, ##args) + +struct slot_temp_obj_t{ + struct switch_obj *obj; +}; + +struct slot_in_obj_t{ + struct switch_obj *obj; +}; + +struct slot_obj_t{ + unsigned int temp_number; + unsigned int in_number; + struct slot_temp_obj_t *temp; + struct slot_in_obj_t *in; + struct switch_obj *obj; +}; + +struct slot_t{ + unsigned int slot_number; + struct slot_obj_t *slot; +}; + +static int g_loglevel = 0; +static struct slot_t g_slot; +static struct switch_obj *g_slot_obj = NULL; +static struct switch_drivers_t *g_drv = NULL; + +static ssize_t slot_number_show(struct switch_obj *obj, struct switch_attribute *attr, char *buf) +{ + return (ssize_t)snprintf(buf, PAGE_SIZE, "%d\n", g_slot.slot_number); +} + +static ssize_t slot_temp_number_show(struct switch_obj *obj, struct switch_attribute *attr, char *buf) +{ + unsigned int index; + + index = obj->index; + SLOT_DBG("slot_temp_number_show,slot index:%d\n",index); + + return (ssize_t)snprintf(buf, PAGE_SIZE, "%d\n", g_slot.slot[index-1].temp_number); +} + +static ssize_t slot_in_number_show(struct switch_obj *obj, struct switch_attribute *attr, char *buf) +{ + unsigned int index; + + index = obj->index; + SLOT_DBG("slot_in_number_show,slot index:%d\n",index); + + return (ssize_t)snprintf(buf, PAGE_SIZE, "%d\n", g_slot.slot[index-1].in_number); +} + +static ssize_t slot_present_status_show(struct switch_obj *obj, struct switch_attribute *attr, char *buf) +{ + unsigned int slot_index; + int ret; + + slot_index = obj->index; + SLOT_DBG("slot_present_status_show, slot index:%d\n",slot_index); + check_p(g_drv); + check_p(g_drv->get_slot_present_status); + + ret = g_drv->get_slot_present_status(slot_index); + if(ret < 0) { + return (ssize_t)snprintf(buf, PAGE_SIZE, "%s\n", WB_SYSFS_DEV_ERROR); + } + + return (ssize_t)snprintf(buf, PAGE_SIZE, "%d\n", ret); +} + +static ssize_t slot_voltage_show(struct switch_obj *obj, struct switch_attribute *attr, char *buf) +{ + unsigned int slot_index, in_index; + int ret; + struct switch_obj *p_obj; + struct switch_device_attribute *in_attr; + + check_p(g_drv); + check_p(g_drv->get_voltage_info); + + p_obj = to_switch_obj(obj->kobj.parent); + check_p(p_obj); + + slot_index = p_obj->index; + in_index = obj->index; + + in_attr = to_switch_device_attr(attr); + check_p(in_attr); + SLOT_DBG("slot_voltage_show, slot index:0x%x, temp index:0x%x, temp type:0x%x\n",slot_index, in_index, in_attr->type); + ret = g_drv->get_voltage_info(WB_MAIN_DEV_SLOT, slot_index, in_index, in_attr->type, buf); + if(ret < 0) { + return (ssize_t)snprintf(buf, PAGE_SIZE, "%s\n", WB_SYSFS_DEV_ERROR); + } + return ret; +} + +static ssize_t slot_temp_show(struct switch_obj *obj, struct switch_attribute *attr, char *buf) +{ + unsigned int slot_index, temp_index; + int ret; + struct switch_obj *p_obj; + struct switch_device_attribute *temp_attr; + + check_p(g_drv); + check_p(g_drv->get_temp_info); + + p_obj = to_switch_obj(obj->kobj.parent); + check_p(p_obj); + + slot_index = p_obj->index; + temp_index = obj->index; + + temp_attr = to_switch_device_attr(attr); + check_p(temp_attr); + SLOT_DBG("slot_temp_show, slot index:0x%x, temp index:0x%x, temp type:0x%x\n",slot_index, temp_index, temp_attr->type); + ret = g_drv->get_temp_info(WB_MAIN_DEV_SLOT, slot_index, temp_index, temp_attr->type, buf); + if(ret < 0) { + return (ssize_t)snprintf(buf, PAGE_SIZE, "%s\n", WB_SYSFS_DEV_ERROR); + } + return ret; +} + +/************************************slot dir and attrs*******************************************/ +static struct switch_attribute slot_number_att = __ATTR(num_slots, S_IRUGO, slot_number_show, NULL); + +static struct attribute *slot_dir_attrs[] = { + &slot_number_att.attr, + NULL, +}; + +static struct attribute_group slot_root_attr_group = { + .attrs = slot_dir_attrs, +}; + +/*******************************slot1 slot2 dir and attrs*******************************************/ +static struct switch_attribute num_temp_sensors_att = __ATTR(num_temp_sensors, S_IRUGO, slot_temp_number_show, NULL); +static struct switch_attribute num_in_sensors_att = __ATTR(num_in_sensors, S_IRUGO, slot_in_number_show, NULL); +static struct switch_attribute slot_present_status_att = __ATTR(present, S_IRUGO, slot_present_status_show, NULL); + +static struct attribute *slot_attrs[] = { + &num_temp_sensors_att.attr, + &num_in_sensors_att.attr, + &slot_present_status_att.attr, + NULL, +}; + +static struct attribute_group slot_attr_group = { + .attrs = slot_attrs, +}; + +/*******************************temp dir and attrs*******************************************/ +static SWITCH_DEVICE_ATTR(temp_alias, S_IRUGO, slot_temp_show, NULL, WB_SENSOR_ALIAS); +static SWITCH_DEVICE_ATTR(temp_type, S_IRUGO, slot_temp_show, NULL, WB_SENSOR_TYPE); +static SWITCH_DEVICE_ATTR(temp_max, S_IRUGO, slot_temp_show, NULL, WB_SENSOR_MAX); +static SWITCH_DEVICE_ATTR(temp_max_hyst, S_IRUGO, slot_temp_show, NULL, WB_SENSOR_MAX_HYST); +static SWITCH_DEVICE_ATTR(temp_min, S_IRUGO, slot_temp_show, NULL, WB_SENSOR_MIN); +static SWITCH_DEVICE_ATTR(temp_input, S_IRUGO, slot_temp_show, NULL, WB_SENSOR_INPUT); + +static struct attribute *temp_attrs[] = { + &switch_dev_attr_temp_alias.switch_attr.attr, + &switch_dev_attr_temp_type.switch_attr.attr, + &switch_dev_attr_temp_max.switch_attr.attr, + &switch_dev_attr_temp_max_hyst.switch_attr.attr, + &switch_dev_attr_temp_min.switch_attr.attr, + &switch_dev_attr_temp_input.switch_attr.attr, + NULL, +}; + +static struct attribute_group temp_attr_group = { + .attrs = temp_attrs, +}; + +/*******************************Voltage dir and attrs*******************************************/ +static SWITCH_DEVICE_ATTR(in_alias, S_IRUGO, slot_voltage_show, NULL, WB_SENSOR_ALIAS); +static SWITCH_DEVICE_ATTR(in_type, S_IRUGO, slot_voltage_show, NULL, WB_SENSOR_TYPE); +static SWITCH_DEVICE_ATTR(in_max, S_IRUGO, slot_voltage_show, NULL, WB_SENSOR_MAX); +static SWITCH_DEVICE_ATTR(in_crit, S_IRUGO, slot_voltage_show, NULL, WB_SENSOR_CRIT); +static SWITCH_DEVICE_ATTR(in_min, S_IRUGO, slot_voltage_show, NULL, WB_SENSOR_MIN); +static SWITCH_DEVICE_ATTR(in_input, S_IRUGO, slot_voltage_show, NULL, WB_SENSOR_INPUT); + +static struct attribute *in_attrs[] = { + &switch_dev_attr_in_alias.switch_attr.attr, + &switch_dev_attr_in_type.switch_attr.attr, + &switch_dev_attr_in_max.switch_attr.attr, + &switch_dev_attr_in_crit.switch_attr.attr, + &switch_dev_attr_in_min.switch_attr.attr, + &switch_dev_attr_in_input.switch_attr.attr, + NULL, +}; + +static struct attribute_group in_attr_group = { + .attrs = in_attrs, +}; + +static void slotindex_single_temp_remove_kobj_and_attrs(struct slot_obj_t * curr_slot, unsigned int temp_index) +{ + + struct slot_temp_obj_t *curr_temp; /* point to temp1 temp2...*/ + + curr_temp = &curr_slot->temp[temp_index - 1]; + if (curr_temp->obj) { + sysfs_remove_group(&curr_temp->obj->kobj, &temp_attr_group); + wb_plat_kobject_delete(&curr_temp->obj); + SLOT_DBG("delete slot:%d temp%d.\n", curr_slot->obj->index, temp_index); + } + return; +} + +static int slotindex_single_temp_create_kobj_and_attrs(struct slot_obj_t * curr_slot, unsigned int temp_index) +{ + char name[DIR_NAME_MAX_LEN]; + struct slot_temp_obj_t *curr_temp; /* point to temp1 temp2...*/ + + curr_temp = &curr_slot->temp[temp_index - 1]; + mem_clear(name, sizeof(name)); + snprintf(name, sizeof(name), "%s%d", TEMP_SYSFS_NAME, temp_index); + + curr_temp->obj = wb_plat_kobject_create(name, &curr_slot->obj->kobj); + if (!curr_temp->obj) { + SLOT_ERR("create slot_index:%d, temp%d object error!\n", curr_slot->obj->index, temp_index); + return -EBADRQC; + } + curr_temp->obj->index = temp_index; + if (sysfs_create_group(&curr_temp->obj->kobj, &temp_attr_group) != 0) { + SLOT_ERR("create slot_index:%d, temp%d attrs error.\n", curr_slot->obj->index, temp_index); + wb_plat_kobject_delete(&curr_temp->obj); + return -EBADRQC; + } + SLOT_DBG("create slot_index:%d, temp%d ok.\n", curr_slot->obj->index, temp_index); + return 0; +} + +static void slotindex_temp_remove_kobj_and_attrs(struct slot_obj_t * curr_slot) +{ + int temp_index; + + for(temp_index = curr_slot->temp_number; temp_index > 0; temp_index--) { + slotindex_single_temp_remove_kobj_and_attrs(curr_slot, temp_index); + } + + if(curr_slot->temp) { + kfree(curr_slot->temp); + curr_slot->temp = NULL; + curr_slot->temp_number = 0; + } + return; +} + +static int slotindex_temp_create_kobj_and_attrs(struct slot_obj_t * curr_slot, int temp_num) +{ + int temp_index, i; + + curr_slot->temp_number = temp_num; + curr_slot->temp = kzalloc(sizeof(struct slot_temp_obj_t) * temp_num, GFP_KERNEL); + if (!curr_slot->temp) { + SLOT_ERR("kzalloc slot temp error, slot index = %d, temp number = %d.\n", curr_slot->obj->index, temp_num); + return -ENOMEM; + } + + for (temp_index = 1; temp_index <= temp_num; temp_index++) { + if (slotindex_single_temp_create_kobj_and_attrs(curr_slot, temp_index) != 0) { + goto error; + } + } + return 0; +error: + for (i = temp_index - 1; i > 0; i--) { + slotindex_single_temp_remove_kobj_and_attrs(curr_slot, i); + } + + if (curr_slot->temp) { + kfree(curr_slot->temp); + curr_slot->temp = NULL; + curr_slot->temp_number = 0; + } + return -EBADRQC; +} + +static void slotindex_single_in_remove_kobj_and_attrs(struct slot_obj_t * curr_slot, unsigned int in_index) +{ + + struct slot_in_obj_t *curr_in; /* point to in1 in2...*/ + + curr_in = &curr_slot->in[in_index - 1]; + if (curr_in->obj) { + sysfs_remove_group(&curr_in->obj->kobj, &in_attr_group); + wb_plat_kobject_delete(&curr_in->obj); + SLOT_DBG("delete slot:%d in%d.\n", curr_slot->obj->index, in_index); + } + return; +} + +static int slotindex_single_in_create_kobj_and_attrs(struct slot_obj_t * curr_slot, unsigned int in_index) +{ + char name[DIR_NAME_MAX_LEN]; + struct slot_in_obj_t *curr_in; /* point to in1 in2...*/ + + curr_in = &curr_slot->in[in_index - 1]; + mem_clear(name, sizeof(name)); + snprintf(name, sizeof(name), "%s%d", VOLTAGE_SYSFS_NAME, in_index); + curr_in->obj = wb_plat_kobject_create(name, &curr_slot->obj->kobj); + if (!curr_in->obj) { + SLOT_ERR("create slot_index:%d, in%d object error!\n", curr_slot->obj->index, in_index); + return -EBADRQC; + } + curr_in->obj->index = in_index; + if (sysfs_create_group(&curr_in->obj->kobj, &in_attr_group) != 0) { + SLOT_ERR("create slot_index:%d, in%d attrs error.\n", curr_slot->obj->index, in_index); + wb_plat_kobject_delete(&curr_in->obj); + return -EBADRQC; + } + SLOT_DBG("create slot_index:%d, in%d ok.\n", curr_slot->obj->index, in_index); + return 0; +} + +static void slotindex_in_remove_kobj_and_attrs(struct slot_obj_t * curr_slot) +{ + int in_index; + + for(in_index = curr_slot->in_number; in_index > 0; in_index--) { + slotindex_single_in_remove_kobj_and_attrs(curr_slot, in_index); + } + + if(curr_slot->in) { + kfree(curr_slot->in); + curr_slot->in = NULL; + curr_slot->in_number = 0; + } + return; +} + +static int slotindex_in_create_kobj_and_attrs(struct slot_obj_t * curr_slot, int in_num) +{ + int in_index, i; + + curr_slot->in_number = in_num; + curr_slot->in = kzalloc(sizeof(struct slot_in_obj_t) * in_num, GFP_KERNEL); + if (!curr_slot->in) { + SLOT_ERR("kzalloc slot Voltage error, slot index = %d, Voltage number = %d.\n", curr_slot->obj->index, in_num); + return -ENOMEM; + } + + for (in_index = 1; in_index <= in_num; in_index++) { + if (slotindex_single_in_create_kobj_and_attrs(curr_slot, in_index) != 0 ) { + goto error; + } + } + return 0; +error: + for (i = in_index - 1; i > 0; i++) { + slotindex_single_in_remove_kobj_and_attrs(curr_slot, i); + } + + if (curr_slot->in) { + kfree(curr_slot->in); + curr_slot->in = NULL; + curr_slot->in_number = 0; + } + return -EBADRQC; +} + +static void slotindex_obj_remove_kobj_and_attrs(struct slot_obj_t * curr_slot, unsigned int obj_id) +{ + switch (obj_id) { + case WB_MINOR_DEV_TEMP: + slotindex_temp_remove_kobj_and_attrs(curr_slot); + break; + case WB_MINOR_DEV_IN: + slotindex_in_remove_kobj_and_attrs(curr_slot); + break; + default: + SLOT_ERR("Unknow obj id:%d\n", obj_id); + } + return ; +} + +static int slotindex_obj_create_kobj_and_attrs(struct slot_obj_t * curr_slot, unsigned int obj_id, int obj_num) +{ + int ret; + + switch (obj_id) { + case WB_MINOR_DEV_TEMP: + ret = slotindex_temp_create_kobj_and_attrs(curr_slot, obj_num); + break; + case WB_MINOR_DEV_IN: + ret = slotindex_in_create_kobj_and_attrs(curr_slot, obj_num); + break; + default: + SLOT_ERR("Unknow obj id:%d\n", obj_id); + ret = -EINVAL; + } + return ret; +} + +static void slot_child_obj_remove_by_id(unsigned int obj_id) +{ + int slot_num; + unsigned int slot_index; + struct slot_obj_t *curr_slot; /* point to slot1 slot2...*/ + + slot_num = g_slot.slot_number; + if (slot_num <= 0 || !g_slot.slot) { + SLOT_DBG("Warning:slot number = %d\n", slot_num); + return; + } + + for(slot_index = slot_num; slot_index > 0; slot_index--) { + curr_slot = &g_slot.slot[slot_index - 1]; + slotindex_obj_remove_kobj_and_attrs(curr_slot, obj_id); + } + return; +} + +static int slot_child_obj_create_by_id(unsigned int obj_id) +{ + int slot_num, obj_num; + unsigned int slot_index, i; + struct slot_obj_t *curr_slot; /* point to slot1 slot2...*/ + + check_p(g_drv->get_dev_number); + obj_num = g_drv->get_dev_number(WB_MAIN_DEV_SLOT,obj_id); + slot_num = g_slot.slot_number; + if (obj_num <= 0 || slot_num <= 0 || !g_slot.slot) { + SLOT_DBG("Warning:slot number = %d, object number:%d.obj_id:%d\n", slot_num, obj_num, obj_id); + return 0; + } + + for (slot_index = 1; slot_index <= slot_num; slot_index++) { + curr_slot = &g_slot.slot[slot_index - 1]; + if (slotindex_obj_create_kobj_and_attrs(curr_slot, obj_id, obj_num) != 0) { + goto error; + } + } + return 0; +error: + for(i = slot_index - 1; i > 0; i++) { + curr_slot = &g_slot.slot[i - 1]; + slotindex_obj_remove_kobj_and_attrs(curr_slot, obj_id); + } + return -EBADRQC; +} + +static void slot_child_obj_remove(void) +{ + /* temp remove */ + slot_child_obj_remove_by_id(WB_MINOR_DEV_TEMP); + + /* in creat */ + slot_child_obj_remove_by_id(WB_MINOR_DEV_IN); + return; +} + +static int slot_child_obj_create(void) +{ + int ret; + + /* temp creat */ + ret = slot_child_obj_create_by_id(WB_MINOR_DEV_TEMP); + if (ret < 0) { + goto temp_err; + } + /* Voltage creat */ + ret = slot_child_obj_create_by_id(WB_MINOR_DEV_IN); + if(ret < 0) { + goto in_err; + } + return 0; +in_err: + slot_child_obj_remove_by_id(WB_MINOR_DEV_TEMP); +temp_err: + return ret; +} + +static void slot_sub_single_remove_kobj_and_attrs(unsigned int index) +{ + struct slot_obj_t *curr_slot; + + curr_slot = &g_slot.slot[index - 1]; + if (curr_slot->obj) { + sysfs_remove_group(&curr_slot->obj->kobj, &slot_attr_group); + wb_plat_kobject_delete(&curr_slot->obj); + SLOT_DBG("delete slot%d.\n", index); + } + return; +} + +static int slot_sub_single_create_kobj_and_attrs(struct kobject *parent, unsigned int index) +{ + char name[DIR_NAME_MAX_LEN]; + struct slot_obj_t *curr_slot; + + curr_slot = &g_slot.slot[index - 1]; + SLOT_DBG("create %s%d ...\n", SLOT_SYSFS_NAME, index); + mem_clear(name, sizeof(name)); + snprintf(name, sizeof(name), "%s%d", SLOT_SYSFS_NAME, index); + curr_slot->obj = wb_plat_kobject_create(name, parent); + if (!curr_slot->obj) { + SLOT_ERR("create slot%d object error!\n", index); + return -EBADRQC; + } + curr_slot->obj->index = index; + if (sysfs_create_group(&curr_slot->obj->kobj, &slot_attr_group) != 0) { + SLOT_ERR("create slot%d attrs error.\n", index); + wb_plat_kobject_delete(&curr_slot->obj); + return -EBADRQC; + } + SLOT_DBG("create slot%d ok.\n", index); + return 0; +} + +static int slot_sub_create_kobj_and_attrs(struct kobject *parent, int slot_num) +{ + unsigned int slot_index, i; + + g_slot.slot = kzalloc(sizeof(struct slot_obj_t) * slot_num, GFP_KERNEL); + if (!g_slot.slot) { + SLOT_ERR("kzalloc slot.slot error, slot number = %d.\n", slot_num); + return -ENOMEM; + } + + for (slot_index = 1; slot_index <= slot_num; slot_index++) { + if (slot_sub_single_create_kobj_and_attrs(parent, slot_index) != 0) { + goto error; + } + } + return 0; +error: + for (i = slot_index - 1; i > 0; i--) { + slot_sub_single_remove_kobj_and_attrs(i); + } + if (g_slot.slot) { + kfree(g_slot.slot); + g_slot.slot = NULL; + } + return -EBADRQC; +} + +/* create slot1 slot2...dir and attrs */ +static int slot_sub_create(void) +{ + int ret, slot_num; + + check_p(g_drv->get_dev_number); + slot_num = g_drv->get_dev_number(WB_MAIN_DEV_SLOT, WB_MINOR_DEV_NONE); + g_slot.slot_number = slot_num; + if (slot_num <= 0) { + SLOT_DBG("Warning:slot number = %d \n", slot_num); + return 0; + } + ret = slot_sub_create_kobj_and_attrs(&g_slot_obj->kobj, slot_num); + return ret; +} + +/** + * slot_sub_remove - delete slot1 slot2...dir and attrs + */ +static void slot_sub_remove(void) +{ + unsigned int slot_index; + + if (g_slot.slot) { + for (slot_index = g_slot.slot_number; slot_index > 0; slot_index--) { + slot_sub_single_remove_kobj_and_attrs(slot_index); + } + kfree(g_slot.slot); + } + mem_clear(&g_slot, sizeof(struct slot_t)); + return ; +} + +/* create slot dir and num_slots attr */ +static int slot_root_create(void) +{ + g_slot_obj = wb_plat_kobject_create(SLOT_SYSFS_NAME, NULL); + if (!g_slot_obj) { + SLOT_ERR("wb_plat_kobject_create slot error!\n"); + return -ENOMEM; + } + + if (sysfs_create_group(&g_slot_obj->kobj, &slot_root_attr_group) != 0) { + wb_plat_kobject_delete(&g_slot_obj); + SLOT_ERR("create slot dir attrs error!\n"); + return -EBADRQC; + } + SLOT_DBG("wb_plat_kobject_create slot directory and attribute success.\n"); + return 0; +} + +static void slot_root_remove(void) +{ + if (g_slot_obj) { + sysfs_remove_group(&g_slot_obj->kobj, &slot_root_attr_group); + wb_plat_kobject_delete(&g_slot_obj); + SLOT_DBG("delete slot root success\n"); + } + + return; +} + +static int wb_slot_init(void) +{ + int ret; + + SLOT_INFO("wb_slot_init...\n"); + g_drv = dfd_plat_driver_get(); + check_p(g_drv); + + ret = slot_root_create(); + if (ret < 0) { + goto slot_root_error; + } + + ret = slot_sub_create(); + if (ret < 0) { + goto slot_sub_error; + } + + ret = slot_child_obj_create(); + if (ret < 0) { + goto slot_child_obj_error; + } + + SLOT_INFO("wb_slot_init ok.\n"); + return 0; +slot_child_obj_error: + slot_sub_remove(); +slot_sub_error: + slot_root_remove(); +slot_root_error: + return ret; +} + +static void wb_slot_exit(void) +{ + slot_child_obj_remove(); + slot_sub_remove(); + slot_root_remove(); + SLOT_INFO("wb_slot_exit ok.\n"); + return ; +} + +module_init(wb_slot_init); +module_exit(wb_slot_exit); +module_param(g_loglevel, int, 0644); +MODULE_PARM_DESC(g_loglevel, "the log level(info=0x1, err=0x2, dbg=0x4).\n"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("support"); +MODULE_DESCRIPTION("slot sysfs driver"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_sysfs/plat_switch.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_sysfs/plat_switch.c new file mode 100644 index 000000000000..7c71fdb3bd62 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/plat_sysfs/dev_sysfs/plat_switch.c @@ -0,0 +1,135 @@ +/* + * plat_switch.c + * Original Author: support 2020-02-17 + * + * This module create a kset in sysfs called /sys/wb_plat + * Then other switch kobjects are created and assigned to this kset, + * such as "board", "cpld", "fan", "psu", "sff", ... + * + * History + * [Version] [Author] [Date] [Description] + * * v1.0 support 2020-02-17 Initial version + */ +#include "./include/plat_switch.h" + +#define SWITCH_INFO(fmt, args...) LOG_INFO("switch: ", fmt, ##args) +#define SWITCH_ERR(fmt, args...) LOG_ERR("switch: ", fmt, ##args) +#define SWITCH_DBG(fmt, args...) LOG_DBG("switch: ", fmt, ##args) + +static int g_loglevel = 0; + +static ssize_t switch_attr_show(struct kobject *kobj, + struct attribute *attr, char *buf) +{ + struct switch_attribute *attribute; + struct switch_obj *device; + + attribute = to_switch_attr(attr); + device = to_switch_obj(kobj); + + if (!attribute->show) + return -ENOSYS; + + return attribute->show(device, attribute, buf); +} + +static ssize_t switch_attr_store(struct kobject *kobj, + struct attribute *attr, const char *buf, size_t len) +{ + struct switch_attribute *attribute; + struct switch_obj *obj; + + attribute = to_switch_attr(attr); + obj = to_switch_obj(kobj); + + if (!attribute->store) + return -ENOSYS; + + return attribute->store(obj, attribute, buf, len); +} + +static const struct sysfs_ops switch_sysfs_ops = { + .show = switch_attr_show, + .store = switch_attr_store, +}; + +static void switch_obj_release(struct kobject *kobj) +{ + struct switch_obj *obj; + + obj = to_switch_obj(kobj); + kfree(obj); +} + +static struct kobj_type switch_ktype = { + .sysfs_ops = &switch_sysfs_ops, + .release = switch_obj_release, + .default_attrs = NULL, +}; + +static struct kset *switch_kset; + +struct switch_obj *wb_plat_kobject_create(const char *name, struct kobject *parent) +{ + struct switch_obj *obj = NULL; + int ret = 0; + + obj = kzalloc(sizeof(*obj), GFP_KERNEL); + if (!obj) { + SWITCH_DBG("wb_plat_kobject_create %s kzalloc error", name); + return NULL; + } + + obj->kobj.kset = switch_kset; + + ret = kobject_init_and_add(&obj->kobj, &switch_ktype, parent, "%s", name); + if (ret) { + kobject_put(&obj->kobj); + SWITCH_DBG("kobject_init_and_add %s error", name); + return NULL; + } + + return obj; +} + +void wb_plat_kobject_delete(struct switch_obj **obj) +{ + if (*obj) { + SWITCH_DBG("%s delete %s.\n", (*obj)->kobj.parent->name, (*obj)->kobj.name); + kobject_put(&((*obj)->kobj)); + *obj = NULL; + } +} + +static int __init switch_init(void) +{ + SWITCH_INFO("...\n"); + + switch_kset = kset_create_and_add("wb_plat", NULL, NULL); + if (!switch_kset) { + SWITCH_ERR("create switch_kset error.\n"); + return -ENOMEM; + } + + SWITCH_INFO("ok.\n"); + return 0; +} + +static void __exit switch_exit(void) +{ + if (switch_kset) { + kset_unregister(switch_kset); + } + + SWITCH_INFO("ok.\n"); +} + +module_init(switch_init); +module_exit(switch_exit); +EXPORT_SYMBOL(wb_plat_kobject_create); +EXPORT_SYMBOL(wb_plat_kobject_delete); +module_param(g_loglevel, int, 0644); +MODULE_PARM_DESC(g_loglevel, "the log level(info=0x1, err=0x2, dbg=0x4).\n"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("support"); +MODULE_DESCRIPTION("Switch driver"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/platform_common.h b/platform/broadcom/sonic-platform-modules-ragile/common/modules/platform_common.h new file mode 100644 index 000000000000..9e4a4fae00c1 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/platform_common.h @@ -0,0 +1,74 @@ +#ifndef __PLATFORM_COMMON_H__ +#define __PLATFORM_COMMON_H__ + +#include +#include +#include +#include + +#define mem_clear(data, size) memset((data), 0, (size)) + +typedef enum { + DBG_START, + DBG_VERBOSE, + DBG_KEY, + DBG_WARN, + DBG_ERROR, + DBG_END, +} dbg_level_t; + + typedef struct dfd_i2c_dev_s { + int bus; + int addr; + } dfd_i2c_dev_t; + +typedef struct dfd_dev_head_info_s { + uint8_t ver; + uint8_t flag; + uint8_t hw_ver; + uint8_t type; + int16_t tlv_len; +} dfd_dev_head_info_t; + +typedef struct dfd_dev_tlv_info_s { + uint8_t type; + uint8_t len; + uint8_t data[0]; +} dfd_dev_tlv_info_t; + +typedef enum dfd_dev_info_type_e { + DFD_DEV_INFO_TYPE_MAC = 1, + DFD_DEV_INFO_TYPE_NAME = 2, + DFD_DEV_INFO_TYPE_SN = 3, + DFD_DEV_INFO_TYPE_PWR_CONS = 4, + DFD_DEV_INFO_TYPE_HW_INFO = 5, + DFD_DEV_INFO_TYPE_DEV_TYPE = 6, +} dfd_dev_tlv_type_t; + +extern int debuglevel; +extern s32 platform_i2c_smbus_read_byte_data(const struct i2c_client *client, u8 command); +extern s32 platform_i2c_smbus_read_i2c_block_data(const struct i2c_client *client, + u8 command, u8 length, u8 *values); +extern s32 platform_i2c_smbus_read_word_data(const struct i2c_client *client, u8 command); + +#define DBG_DEBUG(fmt, arg...) do { \ + if ( debuglevel > DBG_START && debuglevel < DBG_ERROR) { \ + printk(KERN_INFO "[DEBUG]:<%s, %d>:"fmt, __FUNCTION__, __LINE__, ##arg); \ + } else if ( debuglevel >= DBG_ERROR ) { \ + printk(KERN_ERR "[DEBUG]:<%s, %d>:"fmt, __FUNCTION__, __LINE__, ##arg); \ + } else { } \ +} while (0) + +#define DBG_INFO(fmt, arg...) do { \ + if ( debuglevel > DBG_KEY) { \ + printk(KERN_INFO "[INFO]:<%s, %d>:"fmt, __FUNCTION__, __LINE__, ##arg); \ + } \ + } while (0) + +#define DBG_ERROR(fmt, arg...) do { \ + if ( debuglevel > DBG_START) { \ + printk(KERN_ERR "[ERROR]:<%s, %d>:"fmt, __FUNCTION__, __LINE__, ##arg); \ + } \ + } while (0) + +#endif diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/platform_common_module.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/platform_common_module.c new file mode 100644 index 000000000000..62e04b7db837 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/platform_common_module.c @@ -0,0 +1,210 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if LINUX_VERSION_CODE < KERNEL_VERSION(4,19,152) +#include +#else +#include +#endif +#include +#include +#include +#include +#include "platform_common.h" +#include "dfd_tlveeprom.h" + +#define PLATFORM_I2C_RETRY_TIMES 3 + +#define DFD_TLVEEPROM_I2C_BUS (0) +#define DFD_TLVEEPROM_I2C_ADDR (0x56) +#define DFD_E2PROM_MAX_LEN (256) +#define DFD_CARDTYPE_EXT_TLVLEN (4) + +#define PLATFORM_CARDTYPE_RETRY_CNT (10) +#define PLATFORM_CARDTYPE_RETRY_TIMES (1000) + +int debuglevel = 0; +module_param(debuglevel, int, S_IRUGO | S_IWUSR); + +static int dfd_my_type = 0; +module_param(dfd_my_type, int, S_IRUGO | S_IWUSR); + +int g_common_debug_error = 0; +module_param(g_common_debug_error, int, S_IRUGO | S_IWUSR); + +int g_common_debug_verbose = 0; +module_param(g_common_debug_verbose, int, S_IRUGO | S_IWUSR); + +uint32_t dfd_my_type_i2c_bus = 0; +module_param(dfd_my_type_i2c_bus, int, S_IRUGO | S_IWUSR); + +uint32_t dfd_my_type_i2c_addr = 0; +module_param(dfd_my_type_i2c_addr, int, S_IRUGO | S_IWUSR); + +#define RUJIE_COMMON_DEBUG_VERBOSE(fmt, args...) do { \ + if (g_common_debug_verbose) { \ + printk(KERN_ERR "[PLATFORM_COMMON][VER][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +#define RUJIE_COMMON_DEBUG_ERROR(fmt, args...) do { \ + if (g_common_debug_error) { \ + printk(KERN_ERR "[PLATFORM_COMMON][ERROR][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +static int32_t dfd_i2c_read(char *dev, uint32_t addr, uint32_t offset_addr, unsigned char * +buf, int32_t size) +{ + struct file *fp; + struct i2c_client client; + int i ,j; + int rv; + s32 val_t; + + val_t = -1; + rv = 0; + fp = filp_open(dev, O_RDWR, S_IRUSR | S_IWUSR); + if (IS_ERR(fp)) { + DBG_ERROR("i2c open fail.\n"); + RUJIE_COMMON_DEBUG_ERROR("i2c open fail.\n"); + return -1; + } + memcpy(&client, fp->private_data, sizeof(struct i2c_client)); + client.addr = addr; + for (j = 0 ;j < size ;j++){ + for (i = 0; i < PLATFORM_I2C_RETRY_TIMES; i++) { + if ((val_t = i2c_smbus_read_byte_data(&client, (offset_addr + j)))< 0) { + DBG_DEBUG("read try(%d)time offset_addr:%x \n", i, offset_addr); + continue; + } else { + * (buf + j) = val_t; + break; + } + } + if (val_t < 0) { + rv = -1; + break; + } + } + filp_close(fp, NULL); + return rv; +} + +static int dfd_tlvinfo_get_cardtype(void) +{ + char i2c_path[16] = {0}; + int ret; + int cardtype; + u_int8_t eeprom[DFD_E2PROM_MAX_LEN]; + dfd_i2c_dev_t i2c_dev; + uint8_t buf[DFD_CARDTYPE_EXT_TLVLEN]; + uint8_t len; + dfd_tlv_type_t tlv_type; + + if (dfd_my_type_i2c_bus != 0) { + i2c_dev.bus = dfd_my_type_i2c_bus; + } else { + i2c_dev.bus = DFD_TLVEEPROM_I2C_BUS; + } + + if (dfd_my_type_i2c_addr != 0) { + i2c_dev.addr = dfd_my_type_i2c_addr; + } else { + i2c_dev.addr = DFD_TLVEEPROM_I2C_ADDR; + } + snprintf(i2c_path, sizeof(i2c_path), "/dev/i2c-%d", i2c_dev.bus); + RUJIE_COMMON_DEBUG_VERBOSE("Read device eeprom info:(dev:%s, addr:%02x).\n", i2c_path, i2c_dev.addr); + + ret = dfd_i2c_read(i2c_path, i2c_dev.addr, 0, eeprom, DFD_E2PROM_MAX_LEN); + if (ret != 0) { + DBG_ERROR("Read eeprom info error(dev: %s, addr: %02x).\n", i2c_path, i2c_dev.addr); + RUJIE_COMMON_DEBUG_ERROR("Read eeprom info error(dev: %s, addr: %02x).\n", i2c_path, i2c_dev.addr); + return ret; + } + + tlv_type.main_type = TLV_CODE_VENDOR_EXT; + tlv_type.ext_type = DFD_TLVINFO_EXT_TLV_TYPE_DEV_TYPE; + len = sizeof(buf); + mem_clear(buf, len); + ret = dfd_tlvinfo_get_e2prom_info(eeprom, DFD_E2PROM_MAX_LEN, &tlv_type, buf, &len); + if (ret) { + DBG_ERROR("dfd_tlvinfo_get_e2prom_info failed ret %d.\n", ret); + return -1; + } + for (ret = 0; ret < 4; ret++) { + DBG_DEBUG("buf 0x%02x.\n", buf[ret]); + } + + cardtype = ntohl(*((uint32_t *)buf)); + DBG_DEBUG("cardtype 0x%x.\n", cardtype); + return cardtype; +} + +static int __dfd_get_my_card_type(void) +{ + return dfd_tlvinfo_get_cardtype(); +} + +int dfd_get_my_card_type(void) +{ + int type; + int cnt; + + if (dfd_my_type != 0) { + DBG_DEBUG("my_type = 0x%x\r\n", dfd_my_type); + return dfd_my_type; + } + + cnt = PLATFORM_CARDTYPE_RETRY_CNT; + while (cnt--) { + type = __dfd_get_my_card_type(); + if (type < 0) { + RUJIE_COMMON_DEBUG_ERROR("__dfd_get_my_card_type fail cnt %d, ret %d.\n", cnt, type); + msleep(PLATFORM_CARDTYPE_RETRY_TIMES); + continue; + } + RUJIE_COMMON_DEBUG_VERBOSE("success to get type 0x%x.\n", type); + break; + } + + dfd_my_type = type; + return dfd_my_type; +} +EXPORT_SYMBOL(dfd_get_my_card_type); + +static int __init platform_common_init(void) +{ + int ret; + + RUJIE_COMMON_DEBUG_VERBOSE("Enter.\n"); + ret = dfd_get_my_card_type(); + if (ret <= 0) { + RUJIE_COMMON_DEBUG_ERROR("dfd_get_my_card_type failed, ret %d.\n", ret); + printk(KERN_ERR "Warning: Device type get failed, please check the TLV-EEPROM!\n"); + return -1; + } + + RUJIE_COMMON_DEBUG_VERBOSE("Leave success type 0x%x.\n", ret); + return 0; +} + +static void __exit platform_common_exit(void) +{ + RUJIE_COMMON_DEBUG_VERBOSE("Exit.\n"); +} + +module_init(platform_common_init); +module_exit(platform_common_exit); + +MODULE_DESCRIPTION("Platform Support"); +MODULE_AUTHOR("support"); +MODULE_LICENSE("GPL"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/pmbus.h b/platform/broadcom/sonic-platform-modules-ragile/common/modules/pmbus.h deleted file mode 100755 index cd5550ab41b3..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/common/modules/pmbus.h +++ /dev/null @@ -1,520 +0,0 @@ -/* - * pmbus.h - Common defines and structures for PMBus devices - * - * Copyright (c) 2010, 2011 Ericsson AB. - * Copyright (c) 2012 Guenter Roeck - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef PMBUS_H -#define PMBUS_H - -#include -#include -#include - -/* - * Registers - */ -enum pmbus_regs { - PMBUS_PAGE = 0x00, - PMBUS_OPERATION = 0x01, - PMBUS_ON_OFF_CONFIG = 0x02, - PMBUS_CLEAR_FAULTS = 0x03, - PMBUS_PHASE = 0x04, - - PMBUS_WRITE_PROTECT = 0x10, - - PMBUS_CAPABILITY = 0x19, - PMBUS_QUERY = 0x1A, - - PMBUS_VOUT_MODE = 0x20, - PMBUS_VOUT_COMMAND = 0x21, - PMBUS_VOUT_TRIM = 0x22, - PMBUS_VOUT_CAL_OFFSET = 0x23, - PMBUS_VOUT_MAX = 0x24, - PMBUS_VOUT_MARGIN_HIGH = 0x25, - PMBUS_VOUT_MARGIN_LOW = 0x26, - PMBUS_VOUT_TRANSITION_RATE = 0x27, - PMBUS_VOUT_DROOP = 0x28, - PMBUS_VOUT_SCALE_LOOP = 0x29, - PMBUS_VOUT_SCALE_MONITOR = 0x2A, - - PMBUS_COEFFICIENTS = 0x30, - PMBUS_POUT_MAX = 0x31, - - PMBUS_FAN_CONFIG_12 = 0x3A, - PMBUS_FAN_COMMAND_1 = 0x3B, - PMBUS_FAN_COMMAND_2 = 0x3C, - PMBUS_FAN_CONFIG_34 = 0x3D, - PMBUS_FAN_COMMAND_3 = 0x3E, - PMBUS_FAN_COMMAND_4 = 0x3F, - - PMBUS_VOUT_OV_FAULT_LIMIT = 0x40, - PMBUS_VOUT_OV_FAULT_RESPONSE = 0x41, - PMBUS_VOUT_OV_WARN_LIMIT = 0x42, - PMBUS_VOUT_UV_WARN_LIMIT = 0x43, - PMBUS_VOUT_UV_FAULT_LIMIT = 0x44, - PMBUS_VOUT_UV_FAULT_RESPONSE = 0x45, - PMBUS_IOUT_OC_FAULT_LIMIT = 0x46, - PMBUS_IOUT_OC_FAULT_RESPONSE = 0x47, - PMBUS_IOUT_OC_LV_FAULT_LIMIT = 0x48, - PMBUS_IOUT_OC_LV_FAULT_RESPONSE = 0x49, - PMBUS_IOUT_OC_WARN_LIMIT = 0x4A, - PMBUS_IOUT_UC_FAULT_LIMIT = 0x4B, - PMBUS_IOUT_UC_FAULT_RESPONSE = 0x4C, - - PMBUS_OT_FAULT_LIMIT = 0x4F, - PMBUS_OT_FAULT_RESPONSE = 0x50, - PMBUS_OT_WARN_LIMIT = 0x51, - PMBUS_UT_WARN_LIMIT = 0x52, - PMBUS_UT_FAULT_LIMIT = 0x53, - PMBUS_UT_FAULT_RESPONSE = 0x54, - PMBUS_VIN_OV_FAULT_LIMIT = 0x55, - PMBUS_VIN_OV_FAULT_RESPONSE = 0x56, - PMBUS_VIN_OV_WARN_LIMIT = 0x57, - PMBUS_VIN_UV_WARN_LIMIT = 0x58, - PMBUS_VIN_UV_FAULT_LIMIT = 0x59, - - PMBUS_IIN_OC_FAULT_LIMIT = 0x5B, - PMBUS_IIN_OC_WARN_LIMIT = 0x5D, - - PMBUS_POUT_OP_FAULT_LIMIT = 0x68, - PMBUS_POUT_OP_WARN_LIMIT = 0x6A, - PMBUS_PIN_OP_WARN_LIMIT = 0x6B, - - PMBUS_STATUS_BYTE = 0x78, - PMBUS_STATUS_WORD = 0x79, - PMBUS_STATUS_VOUT = 0x7A, - PMBUS_STATUS_IOUT = 0x7B, - PMBUS_STATUS_INPUT = 0x7C, - PMBUS_STATUS_TEMPERATURE = 0x7D, - PMBUS_STATUS_CML = 0x7E, - PMBUS_STATUS_OTHER = 0x7F, - PMBUS_STATUS_MFR_SPECIFIC = 0x80, - PMBUS_STATUS_FAN_12 = 0x81, - PMBUS_STATUS_FAN_34 = 0x82, - - PMBUS_READ_VIN = 0x88, - PMBUS_READ_IIN = 0x89, - PMBUS_READ_VCAP = 0x8A, - PMBUS_READ_VOUT = 0x8B, - PMBUS_READ_IOUT = 0x8C, - PMBUS_READ_TEMPERATURE_1 = 0x8D, - PMBUS_READ_TEMPERATURE_2 = 0x8E, - PMBUS_READ_TEMPERATURE_3 = 0x8F, - PMBUS_READ_FAN_SPEED_1 = 0x90, - PMBUS_READ_FAN_SPEED_2 = 0x91, - PMBUS_READ_FAN_SPEED_3 = 0x92, - PMBUS_READ_FAN_SPEED_4 = 0x93, - PMBUS_READ_DUTY_CYCLE = 0x94, - PMBUS_READ_FREQUENCY = 0x95, - PMBUS_READ_POUT = 0x96, - PMBUS_READ_PIN = 0x97, - - PMBUS_REVISION = 0x98, - PMBUS_MFR_ID = 0x99, - PMBUS_MFR_MODEL = 0x9A, - PMBUS_MFR_REVISION = 0x9B, - PMBUS_MFR_LOCATION = 0x9C, - PMBUS_MFR_DATE = 0x9D, - PMBUS_MFR_SERIAL = 0x9E, - - PMBUS_MFR_VIN_MIN = 0xA0, - PMBUS_MFR_VIN_MAX = 0xA1, - PMBUS_MFR_IIN_MAX = 0xA2, - PMBUS_MFR_PIN_MAX = 0xA3, - PMBUS_MFR_VOUT_MIN = 0xA4, - PMBUS_MFR_VOUT_MAX = 0xA5, - PMBUS_MFR_IOUT_MAX = 0xA6, - PMBUS_MFR_POUT_MAX = 0xA7, - - PMBUS_IC_DEVICE_ID = 0xAD, - PMBUS_IC_DEVICE_REV = 0xAE, - - PMBUS_MFR_MAX_TEMP_1 = 0xC0, - PMBUS_MFR_MAX_TEMP_2 = 0xC1, - PMBUS_MFR_MAX_TEMP_3 = 0xC2, - - - /* - * Virtual registers. - * Useful to support attributes which are not supported by standard PMBus - * registers but exist as manufacturer specific registers on individual chips. - * Must be mapped to real registers in device specific code. - * - * Semantics: - * Virtual registers are all word size. - * READ registers are read-only; writes are either ignored or return an error. - * RESET registers are read/write. Reading reset registers returns zero - * (used for detection), writing any value causes the associated history to be - * reset. - * Virtual registers have to be handled in device specific driver code. Chip - * driver code returns non-negative register values if a virtual register is - * supported, or a negative error code if not. The chip driver may return - * -ENODATA or any other error code in this case, though an error code other - * than -ENODATA is handled more efficiently and thus preferred. Either case, - * the calling PMBus core code will abort if the chip driver returns an error - * code when reading or writing virtual registers. - */ - PMBUS_VIRT_BASE = 0x100, - PMBUS_VIRT_READ_TEMP_AVG, - PMBUS_VIRT_READ_TEMP_MIN, - PMBUS_VIRT_READ_TEMP_MAX, - PMBUS_VIRT_RESET_TEMP_HISTORY, - PMBUS_VIRT_READ_VIN_AVG, - PMBUS_VIRT_READ_VIN_MIN, - PMBUS_VIRT_READ_VIN_MAX, - PMBUS_VIRT_RESET_VIN_HISTORY, - PMBUS_VIRT_READ_IIN_AVG, - PMBUS_VIRT_READ_IIN_MIN, - PMBUS_VIRT_READ_IIN_MAX, - PMBUS_VIRT_RESET_IIN_HISTORY, - PMBUS_VIRT_READ_PIN_AVG, - PMBUS_VIRT_READ_PIN_MIN, - PMBUS_VIRT_READ_PIN_MAX, - PMBUS_VIRT_RESET_PIN_HISTORY, - PMBUS_VIRT_READ_POUT_AVG, - PMBUS_VIRT_READ_POUT_MIN, - PMBUS_VIRT_READ_POUT_MAX, - PMBUS_VIRT_RESET_POUT_HISTORY, - PMBUS_VIRT_READ_VOUT_AVG, - PMBUS_VIRT_READ_VOUT_MIN, - PMBUS_VIRT_READ_VOUT_MAX, - PMBUS_VIRT_RESET_VOUT_HISTORY, - PMBUS_VIRT_READ_IOUT_AVG, - PMBUS_VIRT_READ_IOUT_MIN, - PMBUS_VIRT_READ_IOUT_MAX, - PMBUS_VIRT_RESET_IOUT_HISTORY, - PMBUS_VIRT_READ_TEMP2_AVG, - PMBUS_VIRT_READ_TEMP2_MIN, - PMBUS_VIRT_READ_TEMP2_MAX, - PMBUS_VIRT_RESET_TEMP2_HISTORY, - - PMBUS_VIRT_READ_VMON, - PMBUS_VIRT_VMON_UV_WARN_LIMIT, - PMBUS_VIRT_VMON_OV_WARN_LIMIT, - PMBUS_VIRT_VMON_UV_FAULT_LIMIT, - PMBUS_VIRT_VMON_OV_FAULT_LIMIT, - PMBUS_VIRT_STATUS_VMON, - - /* - * RPM and PWM Fan control - * - * Drivers wanting to expose PWM control must define the behaviour of - * PMBUS_VIRT_PWM_[1-4] and PMBUS_VIRT_PWM_ENABLE_[1-4] in the - * {read,write}_word_data callback. - * - * pmbus core provides a default implementation for - * PMBUS_VIRT_FAN_TARGET_[1-4]. - * - * TARGET, PWM and PWM_ENABLE members must be defined sequentially; - * pmbus core uses the difference between the provided register and - * it's _1 counterpart to calculate the FAN/PWM ID. - */ - PMBUS_VIRT_FAN_TARGET_1, - PMBUS_VIRT_FAN_TARGET_2, - PMBUS_VIRT_FAN_TARGET_3, - PMBUS_VIRT_FAN_TARGET_4, - PMBUS_VIRT_PWM_1, - PMBUS_VIRT_PWM_2, - PMBUS_VIRT_PWM_3, - PMBUS_VIRT_PWM_4, - PMBUS_VIRT_PWM_ENABLE_1, - PMBUS_VIRT_PWM_ENABLE_2, - PMBUS_VIRT_PWM_ENABLE_3, - PMBUS_VIRT_PWM_ENABLE_4, - /* Samples for average - * - * Drivers wanting to expose functionality for changing the number of - * samples used for average values should implement support in - * {read,write}_word_data callback for either PMBUS_VIRT_SAMPLES if it - * applies to all types of measurements, or any number of specific - * PMBUS_VIRT_*_SAMPLES registers to allow for individual control. - */ - PMBUS_VIRT_SAMPLES, - PMBUS_VIRT_IN_SAMPLES, - PMBUS_VIRT_CURR_SAMPLES, - PMBUS_VIRT_POWER_SAMPLES, - PMBUS_VIRT_TEMP_SAMPLES, -}; - -/* - * OPERATION - */ -#define PB_OPERATION_CONTROL_ON BIT(7) - -/* - * WRITE_PROTECT - */ -#define PB_WP_ALL BIT(7) /* all but WRITE_PROTECT */ -#define PB_WP_OP BIT(6) /* all but WP, OPERATION, PAGE */ -#define PB_WP_VOUT BIT(5) /* all but WP, OPERATION, PAGE, VOUT, ON_OFF */ - -#define PB_WP_ANY (PB_WP_ALL | PB_WP_OP | PB_WP_VOUT) - -/* - * CAPABILITY - */ -#define PB_CAPABILITY_SMBALERT BIT(4) -#define PB_CAPABILITY_ERROR_CHECK BIT(7) - -/* - * VOUT_MODE - */ -#define PB_VOUT_MODE_MODE_MASK 0xe0 -#define PB_VOUT_MODE_PARAM_MASK 0x1f - -#define PB_VOUT_MODE_LINEAR 0x00 -#define PB_VOUT_MODE_VID 0x20 -#define PB_VOUT_MODE_DIRECT 0x40 - -/* - * Fan configuration - */ -#define PB_FAN_2_PULSE_MASK (BIT(0) | BIT(1)) -#define PB_FAN_2_RPM BIT(2) -#define PB_FAN_2_INSTALLED BIT(3) -#define PB_FAN_1_PULSE_MASK (BIT(4) | BIT(5)) -#define PB_FAN_1_RPM BIT(6) -#define PB_FAN_1_INSTALLED BIT(7) - -enum pmbus_fan_mode { percent = 0, rpm }; - -/* - * STATUS_BYTE, STATUS_WORD (lower) - */ -#define PB_STATUS_NONE_ABOVE BIT(0) -#define PB_STATUS_CML BIT(1) -#define PB_STATUS_TEMPERATURE BIT(2) -#define PB_STATUS_VIN_UV BIT(3) -#define PB_STATUS_IOUT_OC BIT(4) -#define PB_STATUS_VOUT_OV BIT(5) -#define PB_STATUS_OFF BIT(6) -#define PB_STATUS_BUSY BIT(7) - -/* - * STATUS_WORD (upper) - */ -#define PB_STATUS_UNKNOWN BIT(8) -#define PB_STATUS_OTHER BIT(9) -#define PB_STATUS_FANS BIT(10) -#define PB_STATUS_POWER_GOOD_N BIT(11) -#define PB_STATUS_WORD_MFR BIT(12) -#define PB_STATUS_INPUT BIT(13) -#define PB_STATUS_IOUT_POUT BIT(14) -#define PB_STATUS_VOUT BIT(15) - -/* - * STATUS_IOUT - */ -#define PB_POUT_OP_WARNING BIT(0) -#define PB_POUT_OP_FAULT BIT(1) -#define PB_POWER_LIMITING BIT(2) -#define PB_CURRENT_SHARE_FAULT BIT(3) -#define PB_IOUT_UC_FAULT BIT(4) -#define PB_IOUT_OC_WARNING BIT(5) -#define PB_IOUT_OC_LV_FAULT BIT(6) -#define PB_IOUT_OC_FAULT BIT(7) - -/* - * STATUS_VOUT, STATUS_INPUT - */ -#define PB_VOLTAGE_UV_FAULT BIT(4) -#define PB_VOLTAGE_UV_WARNING BIT(5) -#define PB_VOLTAGE_OV_WARNING BIT(6) -#define PB_VOLTAGE_OV_FAULT BIT(7) - -/* - * STATUS_INPUT - */ -#define PB_PIN_OP_WARNING BIT(0) -#define PB_IIN_OC_WARNING BIT(1) -#define PB_IIN_OC_FAULT BIT(2) - -/* - * STATUS_TEMPERATURE - */ -#define PB_TEMP_UT_FAULT BIT(4) -#define PB_TEMP_UT_WARNING BIT(5) -#define PB_TEMP_OT_WARNING BIT(6) -#define PB_TEMP_OT_FAULT BIT(7) - -/* - * STATUS_FAN - */ -#define PB_FAN_AIRFLOW_WARNING BIT(0) -#define PB_FAN_AIRFLOW_FAULT BIT(1) -#define PB_FAN_FAN2_SPEED_OVERRIDE BIT(2) -#define PB_FAN_FAN1_SPEED_OVERRIDE BIT(3) -#define PB_FAN_FAN2_WARNING BIT(4) -#define PB_FAN_FAN1_WARNING BIT(5) -#define PB_FAN_FAN2_FAULT BIT(6) -#define PB_FAN_FAN1_FAULT BIT(7) - -/* - * CML_FAULT_STATUS - */ -#define PB_CML_FAULT_OTHER_MEM_LOGIC BIT(0) -#define PB_CML_FAULT_OTHER_COMM BIT(1) -#define PB_CML_FAULT_PROCESSOR BIT(3) -#define PB_CML_FAULT_MEMORY BIT(4) -#define PB_CML_FAULT_PACKET_ERROR BIT(5) -#define PB_CML_FAULT_INVALID_DATA BIT(6) -#define PB_CML_FAULT_INVALID_COMMAND BIT(7) - -enum pmbus_sensor_classes { - PSC_VOLTAGE_IN = 0, - PSC_VOLTAGE_OUT, - PSC_CURRENT_IN, - PSC_CURRENT_OUT, - PSC_POWER, - PSC_TEMPERATURE, - PSC_FAN, - PSC_PWM, - PSC_NUM_CLASSES /* Number of power sensor classes */ -}; - -#define PMBUS_PAGES 32 /* Per PMBus specification */ -#define PMBUS_PHASES 8 /* Maximum number of phases per page */ -/* Functionality bit mask */ -#define PMBUS_HAVE_VIN BIT(0) -#define PMBUS_HAVE_VCAP BIT(1) -#define PMBUS_HAVE_VOUT BIT(2) -#define PMBUS_HAVE_IIN BIT(3) -#define PMBUS_HAVE_IOUT BIT(4) -#define PMBUS_HAVE_PIN BIT(5) -#define PMBUS_HAVE_POUT BIT(6) -#define PMBUS_HAVE_FAN12 BIT(7) -#define PMBUS_HAVE_FAN34 BIT(8) -#define PMBUS_HAVE_TEMP BIT(9) -#define PMBUS_HAVE_TEMP2 BIT(10) -#define PMBUS_HAVE_TEMP3 BIT(11) -#define PMBUS_HAVE_STATUS_VOUT BIT(12) -#define PMBUS_HAVE_STATUS_IOUT BIT(13) -#define PMBUS_HAVE_STATUS_INPUT BIT(14) -#define PMBUS_HAVE_STATUS_TEMP BIT(15) -#define PMBUS_HAVE_STATUS_FAN12 BIT(16) -#define PMBUS_HAVE_STATUS_FAN34 BIT(17) -#define PMBUS_HAVE_VMON BIT(18) -#define PMBUS_HAVE_STATUS_VMON BIT(19) -#define PMBUS_HAVE_PWM12 BIT(20) -#define PMBUS_HAVE_PWM34 BIT(21) -#define PMBUS_HAVE_SAMPLES BIT(22) -#define PMBUS_PHASE_VIRTUAL BIT(30) -#define PMBUS_PAGE_VIRTUAL BIT(31) - -enum pmbus_data_format { linear = 0, direct, vid }; -#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0) -enum vrm_version { vr11 = 0, vr12, vr13, imvp9, amd625mv }; -#else -enum vrm_version { vr11 = 0, vr12, vr13 }; -#endif - -struct pmbus_driver_info { - int pages; /* Total number of pages */ - enum pmbus_data_format format[PSC_NUM_CLASSES]; - enum vrm_version vrm_version[PMBUS_PAGES]; - u8 phases[PMBUS_PAGES];/* Number of phases per page */ - u32 pfunc[PMBUS_PHASES];/* Functionality, per phase */ - /* - * Support one set of coefficients for each sensor type - * Used for chips providing data in direct mode. - */ - int m[PSC_NUM_CLASSES]; /* mantissa for direct data format */ - int b[PSC_NUM_CLASSES]; /* offset */ - int R[PSC_NUM_CLASSES]; /* exponent */ - - u32 func[PMBUS_PAGES]; /* Functionality, per page */ - /* - * The following functions map manufacturing specific register values - * to PMBus standard register values. Specify only if mapping is - * necessary. - * Functions return the register value (read) or zero (write) if - * successful. A return value of -ENODATA indicates that there is no - * manufacturer specific register, but that a standard PMBus register - * may exist. Any other negative return value indicates that the - * register does not exist, and that no attempt should be made to read - * the standard register. - */ - int (*read_byte_data)(struct i2c_client *client, int page, int reg); - int (*read_word_data)(struct i2c_client *client, int page, int reg); - int (*write_word_data)(struct i2c_client *client, int page, int reg, - u16 word); - int (*write_byte)(struct i2c_client *client, int page, u8 value); - /* - * The identify function determines supported PMBus functionality. - * This function is only necessary if a chip driver supports multiple - * chips, and the chip functionality is not pre-determined. - */ - int (*identify)(struct i2c_client *client, - struct pmbus_driver_info *info); - - /* Regulator functionality, if supported by this chip driver. */ - int num_regulators; - const struct regulator_desc *reg_desc; - const struct attribute_group **groups; -}; - -/* Regulator ops */ - -extern const struct regulator_ops pmbus_regulator_ops; - -/* Macro for filling in array of struct regulator_desc */ -#define PMBUS_REGULATOR(_name, _id) \ - [_id] = { \ - .name = (_name # _id), \ - .id = (_id), \ - .of_match = of_match_ptr(_name # _id), \ - .regulators_node = of_match_ptr("regulators"), \ - .ops = &pmbus_regulator_ops, \ - .type = REGULATOR_VOLTAGE, \ - .owner = THIS_MODULE, \ - } - -/* Function declarations */ - -void pmbus_clear_cache(struct i2c_client *client); -int pmbus_set_page(struct i2c_client *client, int page); -int pmbus_read_word_data(struct i2c_client *client, int page, u8 reg); -int pmbus_write_word_data(struct i2c_client *client, int page, u8 reg, u16 word); -int pmbus_read_byte_data(struct i2c_client *client, int page, u8 reg); -int pmbus_write_byte(struct i2c_client *client, int page, u8 value); -int pmbus_write_byte_data(struct i2c_client *client, int page, u8 reg, - u8 value); -int pmbus_update_byte_data(struct i2c_client *client, int page, u8 reg, - u8 mask, u8 value); -void pmbus_clear_faults(struct i2c_client *client); -bool pmbus_check_byte_register(struct i2c_client *client, int page, int reg); -bool pmbus_check_word_register(struct i2c_client *client, int page, int reg); -#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0) -int pmbus_do_probe(struct i2c_client *client, struct pmbus_driver_info *info); -#else -int pmbus_do_probe(struct i2c_client *client, const struct i2c_device_id *id, - struct pmbus_driver_info *info); -#endif -int pmbus_do_remove(struct i2c_client *client); -const struct pmbus_driver_info *pmbus_get_driver_info(struct i2c_client - *client); -int pmbus_get_fan_rate_device(struct i2c_client *client, int page, int id, - enum pmbus_fan_mode mode); -int pmbus_get_fan_rate_cached(struct i2c_client *client, int page, int id, - enum pmbus_fan_mode mode); -int pmbus_update_fan(struct i2c_client *client, int page, int id, - u8 config, u8 mask, u16 command); -struct dentry *pmbus_get_debugfs_dir(struct i2c_client *client); - -#endif /* PMBUS_H */ diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/ragile_common_module.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/ragile_common_module.c deleted file mode 100755 index f28852ec3317..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/common/modules/ragile_common_module.c +++ /dev/null @@ -1,76 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static int dfd_my_type = 0; -module_param(dfd_my_type, int, S_IRUGO | S_IWUSR); - -int g_common_debug_error = 0; -module_param(g_common_debug_error, int, S_IRUGO | S_IWUSR); - -int g_common_debug_verbose = 0; -module_param(g_common_debug_verbose, int, S_IRUGO | S_IWUSR); - -#define RAGILE_COMMON_DEBUG_VERBOSE(fmt, args...) do { \ - if (g_common_debug_verbose) { \ - printk(KERN_ERR "[RAGILE_COMMON][VER][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ - } \ -} while (0) - -#define RAGILE_COMMON_DEBUG_ERROR(fmt, args...) do { \ - if (g_common_debug_error) { \ - printk(KERN_ERR "[RAGILE_COMMON][ERROR][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ - } \ -} while (0) - - -int dfd_get_my_card_type(void) -{ - if (dfd_my_type != 0) { - RAGILE_COMMON_DEBUG_VERBOSE("my_type = 0x%x\r\n", dfd_my_type); - return dfd_my_type; - } - - return -1; -} -EXPORT_SYMBOL(dfd_get_my_card_type); - -static int __init ragile_common_init(void) -{ - int ret; - - RAGILE_COMMON_DEBUG_VERBOSE("Enter.\n"); - ret = dfd_get_my_card_type(); - if (ret <= 0) { - RAGILE_COMMON_DEBUG_ERROR("dfd_get_my_card_type failed, ret %d.\n", ret); - printk(KERN_ERR "Warning: Device type get failed, please check the TLV-EEPROM!\n"); - return -1; - } - - RAGILE_COMMON_DEBUG_VERBOSE("Leave success type 0x%x.\n", ret); - return 0; -} - -static void __exit ragile_common_exit(void) -{ - RAGILE_COMMON_DEBUG_VERBOSE("Exit.\n"); -} - -module_init(ragile_common_init); -module_exit(ragile_common_exit); - -MODULE_DESCRIPTION("ragile Platform Support"); -MODULE_AUTHOR("support "); -MODULE_LICENSE("GPL"); - diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/ragile_platform.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/ragile_platform.c deleted file mode 100755 index 5d9908f8c3e2..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/common/modules/ragile_platform.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * ragile_platform.c - A driver for ragile platform module - * - * Copyright (c) 2019 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define PLATFORM_I2C_RETRY_TIMES (3) - -s32 platform_i2c_smbus_read_byte_data(const struct i2c_client *client, u8 command) -{ - int try; - s32 ret; - - ret = -1; - for (try = 0; try < PLATFORM_I2C_RETRY_TIMES; try ++) { - if ((ret = i2c_smbus_read_byte_data(client, command)) >= 0) - break; - } - return ret; -} -EXPORT_SYMBOL(platform_i2c_smbus_read_byte_data); - -s32 platform_i2c_smbus_read_i2c_block_data(const struct i2c_client *client, - u8 command, u8 length, u8 *values) -{ - int try ; - s32 ret; - - ret = -1; - for (try = 0; try < PLATFORM_I2C_RETRY_TIMES; try ++) { - if ((ret = i2c_smbus_read_i2c_block_data(client, command, length, values)) >= 0) - break; - } - return ret; -} -EXPORT_SYMBOL(platform_i2c_smbus_read_i2c_block_data); - -s32 platform_i2c_smbus_read_word_data(const struct i2c_client *client, u8 command) -{ - int try; - s32 ret; - - ret = -1; - for (try = 0; try < PLATFORM_I2C_RETRY_TIMES; try ++) { - if ((ret = i2c_smbus_read_word_data(client, command)) >= 0) - break; - } - return ret; -} -EXPORT_SYMBOL(platform_i2c_smbus_read_word_data); - -static int __init ragile_platform_init(void) -{ - return 0; -} - -static void __exit ragile_platform_exit(void) -{ - return; -} - -module_init(ragile_platform_init); -module_exit(ragile_platform_exit); - -MODULE_DESCRIPTION("ragile Platform Support"); -MODULE_AUTHOR("support "); -MODULE_LICENSE("GPL"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/rg-gpio-xeon.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/rg-gpio-xeon.c deleted file mode 100755 index 84b62c50ab0b..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/common/modules/rg-gpio-xeon.c +++ /dev/null @@ -1,357 +0,0 @@ -/* - * GPIO interface for XEON Super I/O chip - * - * Author: support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License 2 as published - * by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; see the file COPYING. If not, write to - * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define GPIO_NAME "xeon-gpio" -#define GPIO_IOSIZE 7 -#define GPIO_BASE 0x500 - -#define GPIO_USE_SEL GPIO_BASE -#define GP_IO_SEL (GPIO_BASE+0x4) -#define GP_LVL (GPIO_BASE+0xC) - -#define GPIO_USE_SEL2 (GPIO_BASE+0x30) -#define GP_IO_SEL2 (GPIO_BASE+0x34) -#define GP_LVL2 (GPIO_BASE+0x38) - -#define GPIO_USE_SEL3 (GPIO_BASE+0x40) -#define GP_IO_SEL3 (GPIO_BASE+0x44) -#define GP_LVL3 (GPIO_BASE+0x48) - - -#define GPIO_BASE_ID 0 -#define BANKSIZE 32 - -#define GPIO_SDA 17 -#define GPIO_SCL 1 - -#define GPIO_XEON_SPIN_LOCK(lock, flags) spin_lock_irqsave(&(lock), (flags)) -#define GPIO_XEON_SPIN_UNLOCK(lock, flags) spin_unlock_irqrestore(&(lock), (flags)) -static DEFINE_SPINLOCK(sio_lock); - -/****************** i2c adapter with gpio ***********************/ - -static struct i2c_gpio_platform_data i2c_pdata = { - .timeout = 200, - .udelay = 10, - .scl_is_output_only = 0, - .sda_is_open_drain = 0, - .scl_is_open_drain = 0, -}; - -static struct gpiod_lookup_table rg_gpio_lookup_table = { - .dev_id = "i2c-gpio", - .table = { - GPIO_LOOKUP(GPIO_NAME, GPIO_SDA, "sda", - GPIO_ACTIVE_HIGH), - GPIO_LOOKUP(GPIO_NAME, GPIO_SCL, "scl", - GPIO_ACTIVE_HIGH), - }, -}; - -static void i2c_gpio_release(struct device *dev) -{ - return; -} - -static struct platform_device i2c_gpio = { - .name = "i2c-gpio", - .num_resources = 0, - .id = -1, - - .dev = { - .platform_data = &i2c_pdata, - .release = i2c_gpio_release, - } -}; - -static int xeon_gpio_get(struct gpio_chip *gc, unsigned gpio_num) -{ - unsigned int data; - unsigned int bank, offset; - unsigned long flags; - - data = 0; - bank = gpio_num / BANKSIZE; - offset = gpio_num % BANKSIZE; - - GPIO_XEON_SPIN_LOCK(sio_lock, flags); - if (bank == 0) { - data = inl(GP_LVL) & (1 << offset); - if (data) { - data = 1; - } - } else if (bank == 1) { - data = inl(GP_LVL2) & (1 << offset); - if (data) { - data = 1; - } - } else if (bank == 2) { - data = inl(GP_LVL3) & (1 << offset); - if (data) { - data = 1; - } - } - GPIO_XEON_SPIN_UNLOCK(sio_lock, flags); - - return data; -} - -static int xeon_gpio_direction_in(struct gpio_chip *gc, unsigned gpio_num) -{ - unsigned int data; - unsigned int bank, offset; - unsigned long flags; - - bank = gpio_num / BANKSIZE; - offset = gpio_num % BANKSIZE; - - GPIO_XEON_SPIN_LOCK(sio_lock, flags); - if (bank == 0) { - data = inl(GP_IO_SEL); - data = data | (1 << offset); - outl(data, GP_IO_SEL); - } else if (bank == 1) { - data = inl(GP_IO_SEL2); - data = data | (1 << offset); - outl(data, GP_IO_SEL2); - } else if (bank == 2) { - data = inl(GP_IO_SEL3); - data = data | (1 << offset); - outl(data, GP_IO_SEL3); - } - GPIO_XEON_SPIN_UNLOCK(sio_lock, flags); - - return 0; -} - -static void xeon_gpio_set(struct gpio_chip *gc, - unsigned gpio_num, int val) -{ - unsigned int data; - unsigned int bank, offset; - unsigned long flags; - - bank = gpio_num / BANKSIZE; - offset = gpio_num % BANKSIZE; - - GPIO_XEON_SPIN_LOCK(sio_lock, flags); - if (bank == 0) { - data = inl(GP_LVL); - if (val) { - data = data | (1 << offset); - } else { - data = data & ~(1 << offset); - } - outl(data, GP_LVL); - } else if (bank == 1) { - data = inl(GP_LVL2); - if (val) { - data = data | (1 << offset); - } else { - data = data & ~(1 << offset); - } - outl(data, GP_LVL2); - } else if (bank == 2) { - data = inl(GP_LVL3); - if (val) { - data = data | (1 << offset); - } else { - data = data & ~(1 << offset); - } - outl(data, GP_LVL3); - } - GPIO_XEON_SPIN_UNLOCK(sio_lock, flags); -} - -static int xeon_gpio_direction_out(struct gpio_chip *gc, - unsigned gpio_num, int val) -{ - unsigned int data; - unsigned int bank, offset; - unsigned long flags; - - bank = gpio_num / BANKSIZE; - offset = gpio_num % BANKSIZE; - - GPIO_XEON_SPIN_LOCK(sio_lock, flags); - if (bank == 0) { - data = inl(GP_IO_SEL); - data = data & ~(1 << offset); - outl(data, GP_IO_SEL); - - data = inl(GP_LVL); - if (val) { - data = data | (1 << offset); - } else { - data = data & ~(1 << offset); - } - outl(data, GP_LVL); - } else if (bank == 1) { - data = inl(GP_IO_SEL2); - data = data & ~(1 << offset); - outl(data, GP_IO_SEL2); - - data = inl(GP_LVL2); - if (val) { - data = data | (1 << offset); - } else { - data = data & ~(1 << offset); - } - outl(data, GP_LVL2); - } else if (bank == 2) { - data = inl(GP_IO_SEL3); - data = data & ~(1 << offset); - outl(data, GP_IO_SEL3); - - data = inl(GP_LVL3); - if (val) { - data = data | (1 << offset); - } else { - data = data & ~(1 << offset); - } - outl(data, GP_LVL3); - } - GPIO_XEON_SPIN_UNLOCK(sio_lock, flags); - - return 0; -} - -static int xeon_gpio_request(struct gpio_chip *chip, unsigned int offset) -{ - unsigned int data; - unsigned int bank, tmp_offset; - unsigned long flags; - - bank = offset / BANKSIZE; - tmp_offset = offset % BANKSIZE; - - GPIO_XEON_SPIN_LOCK(sio_lock, flags); - if (bank == 0) { - data = inl(GPIO_USE_SEL); - data = data | (1 << tmp_offset); - outl(data, GPIO_USE_SEL); - } else if (bank == 1) { - data = inl(GPIO_USE_SEL2); - data = data | (1 << tmp_offset); - outl(data, GPIO_USE_SEL2); - } else if (bank == 2) { - data = inl(GPIO_USE_SEL3); - data = data | (1 << tmp_offset); - outl(data, GPIO_USE_SEL3); - } - GPIO_XEON_SPIN_UNLOCK(sio_lock, flags); - return 0; -} - -static void xeon_gpio_free(struct gpio_chip *chip, unsigned int offset) -{ - unsigned int data; - unsigned int bank, tmp_offset; - unsigned long flags; - - bank = offset / BANKSIZE; - tmp_offset = offset % BANKSIZE; - - GPIO_XEON_SPIN_LOCK(sio_lock, flags); - if (bank == 0) { - data = inl(GPIO_USE_SEL); - data = data & ~(1 << tmp_offset); - outl(data, GPIO_USE_SEL); - } else if (bank == 1) { - data = inl(GPIO_USE_SEL2); - data = data & ~(1 << tmp_offset); - outl(data, GPIO_USE_SEL2); - } else if (bank == 2) { - data = inl(GPIO_USE_SEL3); - data = data & ~(1 << tmp_offset); - outl(data, GPIO_USE_SEL3); - } - GPIO_XEON_SPIN_UNLOCK(sio_lock, flags); -} - -static struct gpio_chip xeon_gpio_chip = { - .label = GPIO_NAME, - .owner = THIS_MODULE, - .get = xeon_gpio_get, - .direction_input = xeon_gpio_direction_in, - .set = xeon_gpio_set, - .direction_output = xeon_gpio_direction_out, - .request = xeon_gpio_request, - .free = xeon_gpio_free, -}; - -static int __init xeon_gpio_init(void) -{ - int err; - if (!request_region(GPIO_BASE, GPIO_IOSIZE, GPIO_NAME)) - return -EBUSY; - - xeon_gpio_chip.base = GPIO_BASE_ID; - xeon_gpio_chip.ngpio = 96; - - err = gpiochip_add_data(&xeon_gpio_chip, NULL); - if (err < 0) - goto gpiochip_add_err; - gpiod_add_lookup_table(&rg_gpio_lookup_table); - err = platform_device_register(&i2c_gpio); - if (err < 0) { - goto i2c_get_adapter_err; - } - return 0; - -i2c_get_adapter_err: - gpiod_remove_lookup_table(&rg_gpio_lookup_table); - platform_device_unregister(&i2c_gpio); - gpiochip_remove(&xeon_gpio_chip); - -gpiochip_add_err: - release_region(GPIO_BASE, GPIO_IOSIZE); - return -1; -} - -static void __exit xeon_gpio_exit(void) -{ - gpiod_remove_lookup_table(&rg_gpio_lookup_table); - platform_device_unregister(&i2c_gpio); - mdelay(100); - gpiochip_remove(&xeon_gpio_chip); - release_region(GPIO_BASE, GPIO_IOSIZE); -} - -module_init(xeon_gpio_init); -module_exit(xeon_gpio_exit); - -MODULE_AUTHOR("support "); -MODULE_DESCRIPTION("GPIO interface for XEON Super I/O chip"); -MODULE_LICENSE("GPL"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/rg-i2c-algo-bit.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/rg-i2c-algo-bit.c deleted file mode 100644 index 5e8f2c29d2a0..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/common/modules/rg-i2c-algo-bit.c +++ /dev/null @@ -1,734 +0,0 @@ -/* ------------------------------------------------------------------------- - * i2c-algo-bit.c i2c driver algorithms for bit-shift adapters - * ------------------------------------------------------------------------- - * Copyright (C) 1995-2000 Simon G. Vogl - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - * ------------------------------------------------------------------------- */ - -/* With some changes from Frodo Looijaard , Kyösti Mälkki - and Jean Delvare */ - -#include -#include -#include -#include -#include -#include -#include - - -/* ----- global defines ----------------------------------------------- */ - -#ifdef DEBUG -#define bit_dbg(level, dev, format, args...) \ - do { \ - if (i2c_debug >= level) \ - dev_dbg(dev, format, ##args); \ - } while (0) -#else -#define bit_dbg(level, dev, format, args...) \ - do {} while (0) -#endif /* DEBUG */ - -/* ----- global variables --------------------------------------------- */ - -static int bit_test; /* see if the line-setting functions work */ -module_param(bit_test, int, S_IRUGO); -MODULE_PARM_DESC(bit_test, "lines testing - 0 off; 1 report; 2 fail if stuck"); - -#ifdef DEBUG -static int i2c_debug = 1; -module_param(i2c_debug, int, S_IRUGO | S_IWUSR); -MODULE_PARM_DESC(i2c_debug, - "debug level - 0 off; 1 normal; 2 verbose; 3 very verbose"); -#endif - -/* --- setting states on the bus with the right timing: --------------- */ - -#define setsda(adap, val) adap->setsda(adap->data, val) -#define setscl(adap, val) adap->setscl(adap->data, val) -#define getsda(adap) adap->getsda(adap->data) -#define getscl(adap) adap->getscl(adap->data) - -static inline void sdalo(struct i2c_algo_bit_data *adap) -{ - setsda(adap, 0); - udelay((adap->udelay + 1) / 2); -} - -static inline void sdahi(struct i2c_algo_bit_data *adap) -{ - setsda(adap, 1); - udelay((adap->udelay + 1) / 2); -} - -static inline void scllo(struct i2c_algo_bit_data *adap) -{ - setscl(adap, 0); - udelay(adap->udelay / 2); -} - -/* - * Raise scl line, and do checking for delays. This is necessary for slower - * devices. - */ -static int sclhi(struct i2c_algo_bit_data *adap) -{ - unsigned long start; - - setscl(adap, 1); - - /* Not all adapters have scl sense line... */ - if (!adap->getscl) - goto done; - - start = jiffies; - while (!getscl(adap)) { - /* This hw knows how to read the clock line, so we wait - * until it actually gets high. This is safer as some - * chips may hold it low ("clock stretching") while they - * are processing data internally. - */ - if (time_after(jiffies, start + adap->timeout)) { - /* Test one last time, as we may have been preempted - * between last check and timeout test. - */ - if (getscl(adap)) - break; - return -ETIMEDOUT; - } - cpu_relax(); - } -#ifdef DEBUG - if (jiffies != start && i2c_debug >= 3) - pr_debug("i2c-algo-bit: needed %ld jiffies for SCL to go high\n", - jiffies - start); -#endif - -done: - udelay(adap->udelay); - return 0; -} - - -/* --- other auxiliary functions -------------------------------------- */ -static void i2c_start(struct i2c_algo_bit_data *adap) -{ - /* assert: scl, sda are high */ - setsda(adap, 0); - udelay(adap->udelay); - scllo(adap); -} - -static void i2c_repstart(struct i2c_algo_bit_data *adap) -{ - /* assert: scl is low */ - sdahi(adap); - sclhi(adap); - setsda(adap, 0); - udelay(adap->udelay); - scllo(adap); -} - - -static void i2c_stop(struct i2c_algo_bit_data *adap) -{ - /* assert: scl is low */ - sdalo(adap); - sclhi(adap); - setsda(adap, 1); - udelay(adap->udelay); -} - - - -/* send a byte without start cond., look for arbitration, - check ackn. from slave */ -/* returns: - * 1 if the device acknowledged - * 0 if the device did not ack - * -ETIMEDOUT if an error occurred (while raising the scl line) - */ -static int i2c_outb(struct i2c_adapter *i2c_adap, unsigned char c) -{ - int i; - int sb; - int ack; - struct i2c_algo_bit_data *adap = i2c_adap->algo_data; - - /* assert: scl is low */ - for (i = 7; i >= 0; i--) { - sb = (c >> i) & 1; - setsda(adap, sb); - udelay((adap->udelay + 1) / 2); - if (sclhi(adap) < 0) { /* timed out */ - bit_dbg(1, &i2c_adap->dev, - "i2c_outb: 0x%02x, timeout at bit #%d\n", - (int)c, i); - return -ETIMEDOUT; - } - /* FIXME do arbitration here: - * if (sb && !getsda(adap)) -> ouch! Get out of here. - * - * Report a unique code, so higher level code can retry - * the whole (combined) message and *NOT* issue STOP. - */ - scllo(adap); - } - sdahi(adap); - if (sclhi(adap) < 0) { /* timeout */ - bit_dbg(1, &i2c_adap->dev, - "i2c_outb: 0x%02x, timeout at ack\n", (int)c); - return -ETIMEDOUT; - } - - /* read ack: SDA should be pulled down by slave, or it may - * NAK (usually to report problems with the data we wrote). - */ - ack = !getsda(adap); /* ack: sda is pulled low -> success */ - bit_dbg(2, &i2c_adap->dev, "i2c_outb: 0x%02x %s\n", (int)c, - ack ? "A" : "NA"); - - scllo(adap); - return ack; - /* assert: scl is low (sda undef) */ -} - - -static int i2c_inb(struct i2c_adapter *i2c_adap) -{ - /* read byte via i2c port, without start/stop sequence */ - /* acknowledge is sent in i2c_read. */ - int i; - unsigned char indata = 0; - struct i2c_algo_bit_data *adap = i2c_adap->algo_data; - - /* assert: scl is low */ - sdahi(adap); - for (i = 0; i < 8; i++) { - if (sclhi(adap) < 0) { /* timeout */ - bit_dbg(1, &i2c_adap->dev, - "i2c_inb: timeout at bit #%d\n", - 7 - i); - return -ETIMEDOUT; - } - indata *= 2; - if (getsda(adap)) - indata |= 0x01; - setscl(adap, 0); - udelay(i == 7 ? adap->udelay / 2 : adap->udelay); - } - /* assert: scl is low */ - return indata; -} - -/* - * Sanity check for the adapter hardware - check the reaction of - * the bus lines only if it seems to be idle. - */ -static int test_bus(struct i2c_adapter *i2c_adap) -{ - struct i2c_algo_bit_data *adap = i2c_adap->algo_data; - const char *name = i2c_adap->name; - int scl, sda, ret; - - if (adap->pre_xfer) { - ret = adap->pre_xfer(i2c_adap); - if (ret < 0) - return -ENODEV; - } - - if (adap->getscl == NULL) - pr_info("%s: Testing SDA only, SCL is not readable\n", name); - - sda = getsda(adap); - scl = (adap->getscl == NULL) ? 1 : getscl(adap); - if (!scl || !sda) { - printk(KERN_WARNING - "%s: bus seems to be busy (scl=%d, sda=%d)\n", - name, scl, sda); - goto bailout; - } - - sdalo(adap); - sda = getsda(adap); - scl = (adap->getscl == NULL) ? 1 : getscl(adap); - if (sda) { - printk(KERN_WARNING "%s: SDA stuck high!\n", name); - goto bailout; - } - if (!scl) { - printk(KERN_WARNING - "%s: SCL unexpected low while pulling SDA low!\n", - name); - goto bailout; - } - - sdahi(adap); - sda = getsda(adap); - scl = (adap->getscl == NULL) ? 1 : getscl(adap); - if (!sda) { - printk(KERN_WARNING "%s: SDA stuck low!\n", name); - goto bailout; - } - if (!scl) { - printk(KERN_WARNING - "%s: SCL unexpected low while pulling SDA high!\n", - name); - goto bailout; - } - - scllo(adap); - sda = getsda(adap); - scl = (adap->getscl == NULL) ? 0 : getscl(adap); - if (scl) { - printk(KERN_WARNING "%s: SCL stuck high!\n", name); - goto bailout; - } - if (!sda) { - printk(KERN_WARNING - "%s: SDA unexpected low while pulling SCL low!\n", - name); - goto bailout; - } - - sclhi(adap); - sda = getsda(adap); - scl = (adap->getscl == NULL) ? 1 : getscl(adap); - if (!scl) { - printk(KERN_WARNING "%s: SCL stuck low!\n", name); - goto bailout; - } - if (!sda) { - printk(KERN_WARNING - "%s: SDA unexpected low while pulling SCL high!\n", - name); - goto bailout; - } - - if (adap->post_xfer) - adap->post_xfer(i2c_adap); - - pr_info("%s: Test OK\n", name); - return 0; -bailout: - sdahi(adap); - sclhi(adap); - - if (adap->post_xfer) - adap->post_xfer(i2c_adap); - - return -ENODEV; -} - -/* ----- Utility functions -*/ - -/* try_address tries to contact a chip for a number of - * times before it gives up. - * return values: - * 1 chip answered - * 0 chip did not answer - * -x transmission error - */ -static int try_address(struct i2c_adapter *i2c_adap, - unsigned char addr, int retries) -{ - struct i2c_algo_bit_data *adap = i2c_adap->algo_data; - int i, ret = 0; - - for (i = 0; i <= retries; i++) { - ret = i2c_outb(i2c_adap, addr); - if (ret == 1 || i == retries) - break; - bit_dbg(3, &i2c_adap->dev, "emitting stop condition\n"); - i2c_stop(adap); - udelay(adap->udelay); - yield(); - bit_dbg(3, &i2c_adap->dev, "emitting start condition\n"); - i2c_start(adap); - } - if (i && ret) - bit_dbg(1, &i2c_adap->dev, - "Used %d tries to %s client at 0x%02x: %s\n", i + 1, - addr & 1 ? "read from" : "write to", addr >> 1, - ret == 1 ? "success" : "failed, timeout?"); - return ret; -} - -static int sendbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msg) -{ - const unsigned char *temp = msg->buf; - int count = msg->len; - unsigned short nak_ok = msg->flags & I2C_M_IGNORE_NAK; - int retval; - int wrcount = 0; - - while (count > 0) { - retval = i2c_outb(i2c_adap, *temp); - - /* OK/ACK; or ignored NAK */ - if ((retval > 0) || (nak_ok && (retval == 0))) { - count--; - temp++; - wrcount++; - - /* A slave NAKing the master means the slave didn't like - * something about the data it saw. For example, maybe - * the SMBus PEC was wrong. - */ - } else if (retval == 0) { - dev_err(&i2c_adap->dev, "sendbytes: NAK bailout.\n"); - return -EIO; - - /* Timeout; or (someday) lost arbitration - * - * FIXME Lost ARB implies retrying the transaction from - * the first message, after the "winning" master issues - * its STOP. As a rule, upper layer code has no reason - * to know or care about this ... it is *NOT* an error. - */ - } else { - dev_err(&i2c_adap->dev, "sendbytes: error %d\n", - retval); - return retval; - } - } - return wrcount; -} - -static int acknak(struct i2c_adapter *i2c_adap, int is_ack) -{ - struct i2c_algo_bit_data *adap = i2c_adap->algo_data; - - /* assert: sda is high */ - if (is_ack) /* send ack */ - setsda(adap, 0); - udelay((adap->udelay + 1) / 2); - if (sclhi(adap) < 0) { /* timeout */ - dev_err(&i2c_adap->dev, "readbytes: ack/nak timeout\n"); - return -ETIMEDOUT; - } - scllo(adap); - return 0; -} - -static int readbytes(struct i2c_adapter *i2c_adap, struct i2c_msg *msg) -{ - int inval; - int rdcount = 0; /* counts bytes read */ - unsigned char *temp = msg->buf; - int count = msg->len; - const unsigned flags = msg->flags; - - while (count > 0) { - inval = i2c_inb(i2c_adap); - if (inval >= 0) { - *temp = inval; - rdcount++; - } else { /* read timed out */ - break; - } - - temp++; - count--; - - /* Some SMBus transactions require that we receive the - transaction length as the first read byte. */ - if (rdcount == 1 && (flags & I2C_M_RECV_LEN)) { - if (inval <= 0 || inval > I2C_SMBUS_BLOCK_MAX) { - if (!(flags & I2C_M_NO_RD_ACK)) - acknak(i2c_adap, 0); - dev_err(&i2c_adap->dev, - "readbytes: invalid block length (%d)\n", - inval); - return -EPROTO; - } - /* The original count value accounts for the extra - bytes, that is, either 1 for a regular transaction, - or 2 for a PEC transaction. */ - count += inval; - msg->len += inval; - } - - bit_dbg(2, &i2c_adap->dev, "readbytes: 0x%02x %s\n", - inval, - (flags & I2C_M_NO_RD_ACK) - ? "(no ack/nak)" - : (count ? "A" : "NA")); - - if (!(flags & I2C_M_NO_RD_ACK)) { - inval = acknak(i2c_adap, count); - if (inval < 0) - return inval; - } - } - return rdcount; -} - -/* doAddress initiates the transfer by generating the start condition (in - * try_address) and transmits the address in the necessary format to handle - * reads, writes as well as 10bit-addresses. - * returns: - * 0 everything went okay, the chip ack'ed, or IGNORE_NAK flag was set - * -x an error occurred (like: -ENXIO if the device did not answer, or - * -ETIMEDOUT, for example if the lines are stuck...) - */ -static int bit_doAddress(struct i2c_adapter *i2c_adap, struct i2c_msg *msg) -{ - unsigned short flags = msg->flags; - unsigned short nak_ok = msg->flags & I2C_M_IGNORE_NAK; - struct i2c_algo_bit_data *adap = i2c_adap->algo_data; - - unsigned char addr; - int ret, retries; - - retries = nak_ok ? 0 : i2c_adap->retries; - - if (flags & I2C_M_TEN) { - /* a ten bit address */ - addr = 0xf0 | ((msg->addr >> 7) & 0x06); - bit_dbg(2, &i2c_adap->dev, "addr0: %d\n", addr); - /* try extended address code...*/ - ret = try_address(i2c_adap, addr, retries); - if ((ret != 1) && !nak_ok) { - dev_err(&i2c_adap->dev, - "died at extended address code\n"); - return -ENXIO; - } - /* the remaining 8 bit address */ - ret = i2c_outb(i2c_adap, msg->addr & 0xff); - if ((ret != 1) && !nak_ok) { - /* the chip did not ack / xmission error occurred */ - dev_err(&i2c_adap->dev, "died at 2nd address code\n"); - return -ENXIO; - } - if (flags & I2C_M_RD) { - bit_dbg(3, &i2c_adap->dev, - "emitting repeated start condition\n"); - i2c_repstart(adap); - /* okay, now switch into reading mode */ - addr |= 0x01; - ret = try_address(i2c_adap, addr, retries); - if ((ret != 1) && !nak_ok) { - dev_err(&i2c_adap->dev, - "died at repeated address code\n"); - return -EIO; - } - } - } else { /* normal 7bit address */ - addr = i2c_8bit_addr_from_msg(msg); - if (flags & I2C_M_REV_DIR_ADDR) - addr ^= 1; - ret = try_address(i2c_adap, addr, retries); - if ((ret != 1) && !nak_ok) - return -ENXIO; - } - - return 0; -} - -static void bit_i2c_unblock(struct i2c_adapter *i2c_adap) -{ - int i; - struct i2c_algo_bit_data *adap = i2c_adap->algo_data; - - for (i = 0; i < 9; i++) { - setscl(adap, 0); - udelay(5); - setscl(adap, 1); - udelay(5); - } - setscl(adap, 0); - setsda(adap, 0); - udelay(5); - setscl(adap, 1); - udelay(5); - setsda(adap, 1); -} - -static int check_bit_i2c_unblock(struct i2c_adapter *i2c_adap) -{ - struct i2c_algo_bit_data *adap = i2c_adap->algo_data; - int sda, scl; - - sda = getsda(adap); - scl = getscl(adap); - if ((sda == 0) && scl) { - // I2C_ALGO_BIT_ERROR("SCL is high and SDA is low, send 9 clock to device.\n"); - bit_i2c_unblock(i2c_adap); - } - - sda = getsda(adap); - scl = getscl(adap); - if (sda && scl) { - // I2C_ALGO_BIT_DEBUG("SCL and SDA are both high, i2c level check ok.\n"); - return 0; - } - dev_warn(&i2c_adap->dev, "Check i2c level failed, SCL %s, SDA %s.\n", scl ? "high" : "low", sda ? "high" : "low"); - return -EIO; -} - -static int bit_xfer(struct i2c_adapter *i2c_adap, - struct i2c_msg msgs[], int num) -{ - struct i2c_msg *pmsg; - struct i2c_algo_bit_data *adap = i2c_adap->algo_data; - int i, ret; - unsigned short nak_ok; - - if (adap->pre_xfer) { - ret = adap->pre_xfer(i2c_adap); - if (ret < 0) - return ret; - } - - if (check_bit_i2c_unblock(i2c_adap) < 0) { - // I2C_ALGO_BIT_ERROR("check i2c is block.\n"); - return -EIO; - } - - bit_dbg(3, &i2c_adap->dev, "emitting start condition\n"); - i2c_start(adap); - for (i = 0; i < num; i++) { - pmsg = &msgs[i]; - nak_ok = pmsg->flags & I2C_M_IGNORE_NAK; - if (!(pmsg->flags & I2C_M_NOSTART)) { - if (i) { - if (msgs[i - 1].flags & I2C_M_STOP) { - bit_dbg(3, &i2c_adap->dev, - "emitting enforced stop/start condition\n"); - i2c_stop(adap); - i2c_start(adap); - } else { - bit_dbg(3, &i2c_adap->dev, - "emitting repeated start condition\n"); - i2c_repstart(adap); - } - } - ret = bit_doAddress(i2c_adap, pmsg); - if ((ret != 0) && !nak_ok) { - bit_dbg(1, &i2c_adap->dev, - "NAK from device addr 0x%02x msg #%d\n", - msgs[i].addr, i); - goto bailout; - } - } - if (pmsg->flags & I2C_M_RD) { - /* read bytes into buffer*/ - ret = readbytes(i2c_adap, pmsg); - if (ret >= 1) - bit_dbg(2, &i2c_adap->dev, "read %d byte%s\n", - ret, ret == 1 ? "" : "s"); - if (ret < pmsg->len) { - if (ret >= 0) - ret = -EIO; - goto bailout; - } - } else { - /* write bytes from buffer */ - ret = sendbytes(i2c_adap, pmsg); - if (ret >= 1) - bit_dbg(2, &i2c_adap->dev, "wrote %d byte%s\n", - ret, ret == 1 ? "" : "s"); - if (ret < pmsg->len) { - if (ret >= 0) - ret = -EIO; - goto bailout; - } - } - } - ret = i; - -bailout: - bit_dbg(3, &i2c_adap->dev, "emitting stop condition\n"); - i2c_stop(adap); - - if (adap->post_xfer) - adap->post_xfer(i2c_adap); - return ret; -} - -static u32 bit_func(struct i2c_adapter *adap) -{ - return I2C_FUNC_I2C | I2C_FUNC_NOSTART | I2C_FUNC_SMBUS_EMUL | - I2C_FUNC_SMBUS_READ_BLOCK_DATA | - I2C_FUNC_SMBUS_BLOCK_PROC_CALL | - I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING; -} - - -/* -----exported algorithm data: ------------------------------------- */ - -const struct i2c_algorithm rg_i2c_bit_algo = { - .master_xfer = bit_xfer, - .functionality = bit_func, -}; -EXPORT_SYMBOL(rg_i2c_bit_algo); - -static const struct i2c_adapter_quirks i2c_bit_quirk_no_clk_stretch = { - .flags = I2C_AQ_NO_CLK_STRETCH, -}; - -/* - * registering functions to load algorithms at runtime - */ -static int __i2c_bit_add_bus(struct i2c_adapter *adap, - int (*add_adapter)(struct i2c_adapter *)) -{ - struct i2c_algo_bit_data *bit_adap = adap->algo_data; - int ret; - - if (bit_test) { - ret = test_bus(adap); - if (bit_test >= 2 && ret < 0) - return -ENODEV; - } - - /* register new adapter to i2c module... */ - adap->algo = &rg_i2c_bit_algo; - adap->retries = 3; - if (bit_adap->getscl == NULL) - adap->quirks = &i2c_bit_quirk_no_clk_stretch; - - /* - * We tried forcing SCL/SDA to an initial state here. But that caused a - * regression, sadly. Check Bugzilla #200045 for details. - */ - - ret = add_adapter(adap); - if (ret < 0) - return ret; - - /* Complain if SCL can't be read */ - if (bit_adap->getscl == NULL) { - dev_warn(&adap->dev, "Not I2C compliant: can't read SCL\n"); - dev_warn(&adap->dev, "Bus may be unreliable\n"); - } - return 0; -} - -int rg_i2c_bit_add_bus(struct i2c_adapter *adap) -{ - return __i2c_bit_add_bus(adap, i2c_add_adapter); -} -EXPORT_SYMBOL(rg_i2c_bit_add_bus); - -int rg_i2c_bit_add_numbered_bus(struct i2c_adapter *adap) -{ - return __i2c_bit_add_bus(adap, i2c_add_numbered_adapter); -} -EXPORT_SYMBOL(rg_i2c_bit_add_numbered_bus); - -MODULE_AUTHOR("Simon G. Vogl "); -MODULE_DESCRIPTION("I2C-Bus bit-banging algorithm"); -MODULE_LICENSE("GPL"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/rg-i2c-gpio.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/rg-i2c-gpio.c deleted file mode 100644 index bce3afac61a5..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/common/modules/rg-i2c-gpio.c +++ /dev/null @@ -1,431 +0,0 @@ -/* - * Bitbanging I2C bus driver using the GPIO API - * - * Copyright (C) 2007 Atmel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -extern int rg_i2c_bit_add_numbered_bus(struct i2c_adapter *adap); - -struct i2c_gpio_private_data { - struct gpio_desc *sda; - struct gpio_desc *scl; - struct i2c_adapter adap; - struct i2c_algo_bit_data bit_data; - struct i2c_gpio_platform_data pdata; -#ifdef CONFIG_I2C_GPIO_FAULT_INJECTOR - struct dentry *debug_dir; -#endif -}; - -/* - * Toggle SDA by changing the output value of the pin. This is only - * valid for pins configured as open drain (i.e. setting the value - * high effectively turns off the output driver.) - */ -static void i2c_gpio_setsda_val(void *data, int state) -{ - struct i2c_gpio_private_data *priv = data; - - gpiod_set_value_cansleep(priv->sda, state); -} - -/* - * Toggle SCL by changing the output value of the pin. This is used - * for pins that are configured as open drain and for output-only - * pins. The latter case will break the i2c protocol, but it will - * often work in practice. - */ -static void i2c_gpio_setscl_val(void *data, int state) -{ - struct i2c_gpio_private_data *priv = data; - - gpiod_set_value_cansleep(priv->scl, state); -} - -static int i2c_gpio_getsda(void *data) -{ - struct i2c_gpio_private_data *priv = data; - - return gpiod_get_value_cansleep(priv->sda); -} - -static int i2c_gpio_getscl(void *data) -{ - struct i2c_gpio_private_data *priv = data; - - return gpiod_get_value_cansleep(priv->scl); -} - -#ifdef CONFIG_I2C_GPIO_FAULT_INJECTOR -static struct dentry *i2c_gpio_debug_dir; - -#define setsda(bd, val) ((bd)->setsda((bd)->data, val)) -#define setscl(bd, val) ((bd)->setscl((bd)->data, val)) -#define getsda(bd) ((bd)->getsda((bd)->data)) -#define getscl(bd) ((bd)->getscl((bd)->data)) - -#define WIRE_ATTRIBUTE(wire) \ - static int fops_##wire##_get(void *data, u64 *val) \ -{ \ - struct i2c_gpio_private_data *priv = data; \ - \ - i2c_lock_bus(&priv->adap, I2C_LOCK_ROOT_ADAPTER); \ - *val = get##wire(&priv->bit_data); \ - i2c_unlock_bus(&priv->adap, I2C_LOCK_ROOT_ADAPTER); \ - return 0; \ -} \ -static int fops_##wire##_set(void *data, u64 val) \ -{ \ - struct i2c_gpio_private_data *priv = data; \ - \ - i2c_lock_bus(&priv->adap, I2C_LOCK_ROOT_ADAPTER); \ - set##wire(&priv->bit_data, val); \ - i2c_unlock_bus(&priv->adap, I2C_LOCK_ROOT_ADAPTER); \ - return 0; \ -} \ -DEFINE_DEBUGFS_ATTRIBUTE(fops_##wire, fops_##wire##_get, fops_##wire##_set, "%llu\n") - -WIRE_ATTRIBUTE(scl); -WIRE_ATTRIBUTE(sda); - -static void i2c_gpio_incomplete_transfer(struct i2c_gpio_private_data *priv, - u32 pattern, u8 pattern_size) -{ - struct i2c_algo_bit_data *bit_data = &priv->bit_data; - int i; - - i2c_lock_bus(&priv->adap, I2C_LOCK_ROOT_ADAPTER); - - /* START condition */ - setsda(bit_data, 0); - udelay(bit_data->udelay); - - /* Send pattern, request ACK, don't send STOP */ - for (i = pattern_size - 1; i >= 0; i--) { - setscl(bit_data, 0); - udelay(bit_data->udelay / 2); - setsda(bit_data, (pattern >> i) & 1); - udelay((bit_data->udelay + 1) / 2); - setscl(bit_data, 1); - udelay(bit_data->udelay); - } - - i2c_unlock_bus(&priv->adap, I2C_LOCK_ROOT_ADAPTER); -} - -static int fops_incomplete_addr_phase_set(void *data, u64 addr) -{ - struct i2c_gpio_private_data *priv = data; - u32 pattern; - - if (addr > 0x7f) - return -EINVAL; - - /* ADDR (7 bit) + RD (1 bit) + Client ACK, keep SDA hi (1 bit) */ - pattern = (addr << 2) | 3; - - i2c_gpio_incomplete_transfer(priv, pattern, 9); - - return 0; -} -DEFINE_DEBUGFS_ATTRIBUTE(fops_incomplete_addr_phase, NULL, fops_incomplete_addr_phase_set, "%llu\n"); - -static int fops_incomplete_write_byte_set(void *data, u64 addr) -{ - struct i2c_gpio_private_data *priv = data; - u32 pattern; - - if (addr > 0x7f) - return -EINVAL; - - /* ADDR (7 bit) + WR (1 bit) + Client ACK (1 bit) */ - pattern = (addr << 2) | 1; - /* 0x00 (8 bit) + Client ACK, keep SDA hi (1 bit) */ - pattern = (pattern << 9) | 1; - - i2c_gpio_incomplete_transfer(priv, pattern, 18); - - return 0; -} -DEFINE_DEBUGFS_ATTRIBUTE(fops_incomplete_write_byte, NULL, fops_incomplete_write_byte_set, "%llu\n"); - -static void i2c_gpio_fault_injector_init(struct platform_device *pdev) -{ - struct i2c_gpio_private_data *priv = platform_get_drvdata(pdev); - - /* - * If there will be a debugfs-dir per i2c adapter somewhen, put the - * 'fault-injector' dir there. Until then, we have a global dir with - * all adapters as subdirs. - */ - if (!i2c_gpio_debug_dir) { - i2c_gpio_debug_dir = debugfs_create_dir("i2c-fault-injector", NULL); - if (!i2c_gpio_debug_dir) - return; - } - - priv->debug_dir = debugfs_create_dir(pdev->name, i2c_gpio_debug_dir); - if (!priv->debug_dir) - return; - - debugfs_create_file_unsafe("scl", 0600, priv->debug_dir, priv, &fops_scl); - debugfs_create_file_unsafe("sda", 0600, priv->debug_dir, priv, &fops_sda); - debugfs_create_file_unsafe("incomplete_address_phase", 0200, priv->debug_dir, - priv, &fops_incomplete_addr_phase); - debugfs_create_file_unsafe("incomplete_write_byte", 0200, priv->debug_dir, - priv, &fops_incomplete_write_byte); -} - -static void i2c_gpio_fault_injector_exit(struct platform_device *pdev) -{ - struct i2c_gpio_private_data *priv = platform_get_drvdata(pdev); - - debugfs_remove_recursive(priv->debug_dir); -} -#else -static inline void i2c_gpio_fault_injector_init(struct platform_device *pdev) {} -static inline void i2c_gpio_fault_injector_exit(struct platform_device *pdev) {} -#endif /* CONFIG_I2C_GPIO_FAULT_INJECTOR*/ - -static void of_i2c_gpio_get_props(struct device_node *np, - struct i2c_gpio_platform_data *pdata) -{ - u32 reg; - - of_property_read_u32(np, "i2c-gpio,delay-us", &pdata->udelay); - - if (!of_property_read_u32(np, "i2c-gpio,timeout-ms", ®)) - pdata->timeout = msecs_to_jiffies(reg); - - pdata->sda_is_open_drain = - of_property_read_bool(np, "i2c-gpio,sda-open-drain"); - pdata->scl_is_open_drain = - of_property_read_bool(np, "i2c-gpio,scl-open-drain"); - pdata->scl_is_output_only = - of_property_read_bool(np, "i2c-gpio,scl-output-only"); -} - -static struct gpio_desc *i2c_gpio_get_desc(struct device *dev, - const char *con_id, - unsigned int index, - enum gpiod_flags gflags) -{ - struct gpio_desc *retdesc; - int ret; - - retdesc = devm_gpiod_get(dev, con_id, gflags); - if (!IS_ERR(retdesc)) { - dev_dbg(dev, "got GPIO from name %s\n", con_id); - return retdesc; - } - - retdesc = devm_gpiod_get_index(dev, NULL, index, gflags); - if (!IS_ERR(retdesc)) { - dev_dbg(dev, "got GPIO from index %u\n", index); - return retdesc; - } - - ret = PTR_ERR(retdesc); - - /* FIXME: hack in the old code, is this really necessary? */ - if (ret == -EINVAL) - retdesc = ERR_PTR(-EPROBE_DEFER); - - /* This happens if the GPIO driver is not yet probed, let's defer */ - if (ret == -ENOENT) - retdesc = ERR_PTR(-EPROBE_DEFER); - - if (PTR_ERR(retdesc) != -EPROBE_DEFER) - dev_err(dev, "error trying to get descriptor: %d\n", ret); - - return retdesc; -} - -static int i2c_gpio_probe(struct platform_device *pdev) -{ - struct i2c_gpio_private_data *priv; - struct i2c_gpio_platform_data *pdata; - struct i2c_algo_bit_data *bit_data; - struct i2c_adapter *adap; - struct device *dev = &pdev->dev; - struct device_node *np = dev->of_node; - enum gpiod_flags gflags; - int ret; - - priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); - if (!priv) - return -ENOMEM; - - adap = &priv->adap; - bit_data = &priv->bit_data; - pdata = &priv->pdata; - - if (np) { - of_i2c_gpio_get_props(np, pdata); - } else { - /* - * If all platform data settings are zero it is OK - * to not provide any platform data from the board. - */ - if (dev_get_platdata(dev)) - memcpy(pdata, dev_get_platdata(dev), sizeof(*pdata)); - } - - /* - * First get the GPIO pins; if it fails, we'll defer the probe. - * If the SDA line is marked from platform data or device tree as - * "open drain" it means something outside of our control is making - * this line being handled as open drain, and we should just handle - * it as any other output. Else we enforce open drain as this is - * required for an I2C bus. - */ - if (pdata->sda_is_open_drain) - gflags = GPIOD_OUT_HIGH; - else - gflags = GPIOD_OUT_HIGH_OPEN_DRAIN; - priv->sda = i2c_gpio_get_desc(dev, "sda", 0, gflags); - if (IS_ERR(priv->sda)) - return PTR_ERR(priv->sda); - - /* - * If the SCL line is marked from platform data or device tree as - * "open drain" it means something outside of our control is making - * this line being handled as open drain, and we should just handle - * it as any other output. Else we enforce open drain as this is - * required for an I2C bus. - */ - if (pdata->scl_is_open_drain) - gflags = GPIOD_OUT_HIGH; - else - gflags = GPIOD_OUT_HIGH_OPEN_DRAIN; - priv->scl = i2c_gpio_get_desc(dev, "scl", 1, gflags); - if (IS_ERR(priv->scl)) - return PTR_ERR(priv->scl); - - if (gpiod_cansleep(priv->sda) || gpiod_cansleep(priv->scl)) - dev_warn(dev, "Slow GPIO pins might wreak havoc into I2C/SMBus bus timing"); - - bit_data->setsda = i2c_gpio_setsda_val; - bit_data->setscl = i2c_gpio_setscl_val; - - if (!pdata->scl_is_output_only) - bit_data->getscl = i2c_gpio_getscl; - bit_data->getsda = i2c_gpio_getsda; - - if (pdata->udelay) - bit_data->udelay = pdata->udelay; - else if (pdata->scl_is_output_only) - bit_data->udelay = 50; /* 10 kHz */ - else - bit_data->udelay = 5; /* 100 kHz */ - - if (pdata->timeout) - bit_data->timeout = pdata->timeout; - else - bit_data->timeout = HZ / 10; /* 100 ms */ - - bit_data->data = priv; - - adap->owner = THIS_MODULE; - if (np) - strlcpy(adap->name, dev_name(dev), sizeof(adap->name)); - else - snprintf(adap->name, sizeof(adap->name), "i2c-gpio%d", pdev->id); - - adap->algo_data = bit_data; - adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; - adap->dev.parent = dev; - adap->dev.of_node = np; - - adap->nr = pdev->id; - ret = rg_i2c_bit_add_numbered_bus(adap); - if (ret) - return ret; - - platform_set_drvdata(pdev, priv); - - /* - * FIXME: using global GPIO numbers is not helpful. If/when we - * get accessors to get the actual name of the GPIO line, - * from the descriptor, then provide that instead. - */ - dev_info(dev, "using lines %u (SDA) and %u (SCL%s)\n", - desc_to_gpio(priv->sda), desc_to_gpio(priv->scl), - pdata->scl_is_output_only - ? ", no clock stretching" : ""); - - i2c_gpio_fault_injector_init(pdev); - - return 0; -} - -static int i2c_gpio_remove(struct platform_device *pdev) -{ - struct i2c_gpio_private_data *priv; - struct i2c_adapter *adap; - - i2c_gpio_fault_injector_exit(pdev); - - priv = platform_get_drvdata(pdev); - adap = &priv->adap; - - i2c_del_adapter(adap); - - return 0; -} - -#if defined(CONFIG_OF) -static const struct of_device_id i2c_gpio_dt_ids[] = { - { .compatible = "rg-i2c-gpio", }, - { /* sentinel */ } -}; - -MODULE_DEVICE_TABLE(of, i2c_gpio_dt_ids); -#endif - -static struct platform_driver i2c_gpio_driver = { - .driver = { - .name = "rg-i2c-gpio", - .of_match_table = of_match_ptr(i2c_gpio_dt_ids), - }, - .probe = i2c_gpio_probe, - .remove = i2c_gpio_remove, -}; - -static int __init i2c_gpio_init(void) -{ - int ret; - - ret = platform_driver_register(&i2c_gpio_driver); - if (ret) - printk(KERN_ERR "i2c-gpio: probe failed: %d\n", ret); - - return ret; -} -subsys_initcall(i2c_gpio_init); - -static void __exit i2c_gpio_exit(void) -{ - platform_driver_unregister(&i2c_gpio_driver); -} -module_exit(i2c_gpio_exit); - -MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); -MODULE_DESCRIPTION("Platform-independent bitbanging I2C driver"); -MODULE_LICENSE("GPL"); -MODULE_ALIAS("platform:i2c-gpio"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/rg_fan.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/rg_fan.c deleted file mode 100755 index f8a70adeee27..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/common/modules/rg_fan.c +++ /dev/null @@ -1,266 +0,0 @@ -/* - * rg_fan.c - A driver for control rg_fan base on rg_fan.c - * - * Copyright (c) 1998, 1999 Frodo Looijaard - * Copyright (c) 2019 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define FAN_SIZE (256) -#define SYS_FAN_BUF_LEN (64) - -typedef enum { - DBG_START, - DBG_VERBOSE, - DBG_KEY, - DBG_WARN, - DBG_ERROR, - DBG_END, -} dbg_level_t; - -static int debuglevel = 0; - -#define DBG_DEBUG(fmt, arg...) \ - do { \ - if (debuglevel > DBG_START && debuglevel < DBG_ERROR) { \ - printk(KERN_INFO "[DEBUG]:<%s, %d>:" fmt, \ - __FUNCTION__, __LINE__, ##arg); \ - } else if (debuglevel >= DBG_ERROR) { \ - printk(KERN_ERR "[DEBUG]:<%s, %d>:" fmt, __FUNCTION__, \ - __LINE__, ##arg); \ - } else { \ - } \ - } while (0) - -#define DBG_ERROR(fmt, arg...) \ - do { \ - if (debuglevel > DBG_START) { \ - printk(KERN_ERR "[ERROR]:<%s, %d>:" fmt, __FUNCTION__, \ - __LINE__, ##arg); \ - } \ - } while (0) - -extern s32 platform_i2c_smbus_read_byte_data(const struct i2c_client *client, u8 command); -extern s32 platform_i2c_smbus_read_i2c_block_data( - const struct i2c_client *client, u8 command, u8 length, u8 *values); -extern s32 platform_i2c_smbus_read_word_data(const struct i2c_client *client, u8 command); - -typedef enum dfd_dev_info_type_e { - DFD_DEV_INFO_TYPE_MAC = 1, - DFD_DEV_INFO_TYPE_NAME = 2, - DFD_DEV_INFO_TYPE_SN = 3, - DFD_DEV_INFO_TYPE_PWR_CONS = 4, - DFD_DEV_INFO_TYPE_HW_INFO = 5, - DFD_DEV_INFO_TYPE_DEV_TYPE = 6, -} dfd_dev_tlv_type_t; - -typedef struct dfd_dev_head_info_s { - uint8_t ver; /* define E2PROM version，default is 0x01 */ - uint8_t flag; /* flag is 0x7E in new version E2PROM */ - uint8_t hw_ver; /* consists of main version and revise version */ - uint8_t type; /* HW type */ - int16_t tlv_len; /* 16 bits */ -} dfd_dev_head_info_t; - -typedef struct dfd_dev_tlv_info_s { - uint8_t type; - uint8_t len; - uint8_t data[0]; -} dfd_dev_tlv_info_t; - -struct fan_data { - struct i2c_client *client; - struct mutex update_lock; - char valid; /* !=0 if registers are valid */ - unsigned long last_updated[8]; /* In jiffies */ - u8 data[FAN_SIZE]; /* Register value */ -}; - -static ssize_t show_fan_sysfs_tlv_value(struct device *dev, - struct device_attribute *da, char *buf) -{ - struct sensor_device_attribute *attr = to_sensor_dev_attr(da); - struct i2c_client *client = to_i2c_client(dev); - struct fan_data *data = i2c_get_clientdata(client); - - dfd_dev_head_info_t info; - uint8_t tmp_tlv_len[sizeof(uint16_t)]; - uint8_t *tlv_data; - dfd_dev_tlv_info_t *tlv; - int type; - int buf_len = SYS_FAN_BUF_LEN - 1; - u8 sysfs_buf[SYS_FAN_BUF_LEN]; - int i; - int ret = 0; - - mutex_lock(&data->update_lock); - memset(sysfs_buf, 0, SYS_FAN_BUF_LEN); - ret = platform_i2c_smbus_read_i2c_block_data( - client, 0, sizeof(dfd_dev_head_info_t), (uint8_t *)&info); - if (ret != sizeof(dfd_dev_head_info_t)) { - DBG_ERROR("fan maybe not set mac or not present0"); - goto exit; - } - - /* transform TLV_LEN */ - memcpy(tmp_tlv_len, (uint8_t *)&info.tlv_len, sizeof(int16_t)); - info.tlv_len = (tmp_tlv_len[0] << 8) + tmp_tlv_len[1]; - - if ((info.tlv_len <= 0) || (info.tlv_len > 0xFF)) { - DBG_ERROR("fan maybe not set mac or not present1"); - goto exit; - } - - type = attr->index; - tlv_data = (uint8_t *)kmalloc(info.tlv_len, GFP_KERNEL); - memset(tlv_data, 0, info.tlv_len); - - if (i2c_check_functionality(client->adapter, - I2C_FUNC_SMBUS_READ_I2C_BLOCK)) { - for (i = 0; i < info.tlv_len; i += 32) - if (platform_i2c_smbus_read_i2c_block_data(client, - sizeof(dfd_dev_head_info_t) + i, - 32, tlv_data + i) != 32) - break; - } - - DBG_DEBUG("TLV Len:%d\n", (int)sizeof(dfd_dev_tlv_info_t)); - for (tlv = (dfd_dev_tlv_info_t *)tlv_data; - (ulong)tlv < (ulong)tlv_data + info.tlv_len;) { - DBG_DEBUG( - "tlv: %p, tlv->type: 0x%x, tlv->len: 0x%x info->tlv_len: 0x%x\n", - tlv, tlv->type, tlv->len, info.tlv_len); - if (tlv->type == type && buf_len >= tlv->len) { - memcpy((uint8_t *)sysfs_buf, (uint8_t *)tlv->data, - tlv->len); - buf_len = (uint32_t)tlv->len; - break; - } - tlv = (dfd_dev_tlv_info_t *)((uint8_t *)tlv + - sizeof(dfd_dev_tlv_info_t) + - tlv->len); - } - - kfree(tlv_data); - DBG_DEBUG("value: %s \n", sysfs_buf); -exit: - mutex_unlock(&data->update_lock); - return sprintf(buf, "%s\n", sysfs_buf); -} - -static ssize_t show_fan_value(struct device *dev, struct device_attribute *da, char *buf) -{ - struct fan_data *data = dev_get_drvdata(dev); - struct i2c_client *client = data->client; - int i; - - mutex_lock(&data->update_lock); - - if (i2c_check_functionality(client->adapter, - I2C_FUNC_SMBUS_READ_I2C_BLOCK)) { - for (i = 0; i < FAN_SIZE; i += 32) { - if (platform_i2c_smbus_read_i2c_block_data( - client, i, 32, data->data + i) != 32) - goto exit; - } - } else { - for (i = 0; i < FAN_SIZE; i += 2) { - int word = platform_i2c_smbus_read_word_data(client, i); - if (word < 0) - goto exit; - data->data[i] = word & 0xff; - data->data[i + 1] = word >> 8; - } - } - memcpy(buf, &data->data[0], FAN_SIZE); -exit: - mutex_unlock(&data->update_lock); - return FAN_SIZE; -} - -static SENSOR_DEVICE_ATTR(fan_hw_version, S_IRUGO, show_fan_sysfs_tlv_value, NULL, DFD_DEV_INFO_TYPE_HW_INFO); -static SENSOR_DEVICE_ATTR(fan_sn, S_IRUGO, show_fan_sysfs_tlv_value, NULL, DFD_DEV_INFO_TYPE_SN); -static SENSOR_DEVICE_ATTR(fan_type, S_IRUGO, show_fan_sysfs_tlv_value, NULL, DFD_DEV_INFO_TYPE_NAME); -static SENSOR_DEVICE_ATTR(fan, S_IRUGO, show_fan_value, NULL, 0); - -static struct attribute *fan_sysfs_attrs[] = { - &sensor_dev_attr_fan_hw_version.dev_attr.attr, - &sensor_dev_attr_fan_sn.dev_attr.attr, - &sensor_dev_attr_fan_type.dev_attr.attr, - &sensor_dev_attr_fan.dev_attr.attr, - NULL -}; - -static const struct attribute_group fan_sysfs_group = { - .attrs = fan_sysfs_attrs, -}; - -static int fan_probe(struct i2c_client *client, const struct i2c_device_id *id) -{ - struct fan_data *data; - int status; - - status = -1; - DBG_DEBUG("fan_probe(0x%02x)\n", client->addr); - data = devm_kzalloc(&client->dev, sizeof(struct fan_data), GFP_KERNEL); - if (!data) { - return -ENOMEM; - } - - data->client = client; - i2c_set_clientdata(client, data); - mutex_init(&data->update_lock); - - status = sysfs_create_group(&client->dev.kobj, &fan_sysfs_group); - if (status != 0) { - DBG_ERROR(" sysfs_create_group err\n"); - return status; - } - return 0; -} - -static int fan_remove(struct i2c_client *client) -{ - sysfs_remove_group(&client->dev.kobj, &fan_sysfs_group); - return 0; -} - -static const struct i2c_device_id fan_id[] = { { "rg_fan", 0 }, {} }; -MODULE_DEVICE_TABLE(i2c, fan_id); - -static struct i2c_driver rg_fan_driver = { - .driver = { - .name = "rg_fan", - }, - .probe = fan_probe, - .remove = fan_remove, - .id_table = fan_id, -}; - -module_i2c_driver(rg_fan_driver); -MODULE_AUTHOR("support "); -MODULE_DESCRIPTION("ragile fan driver"); -MODULE_LICENSE("GPL"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/rg_psu.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/rg_psu.c deleted file mode 100755 index 78abd41cf525..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/common/modules/rg_psu.c +++ /dev/null @@ -1,340 +0,0 @@ -/* - * rg_cpld.c - A driver for pmbus psu - * - * Copyright (c) 2019 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define MAGIC_PSU_RATE (0xA7) -#define MAGIC_PSU_OUT_CURRENT (0x8C) -#define MAGIC_PSU_OUT_VOLTAGE (0x8B) -#define MAGIC_PSU_IN_VOLTAGE (0x88) -#define MAGIC_PSU_IN_CURRENT (0x89) -#define MAGIC_PSU_TEMP (0x8D) -#define MAGIC_PSU_TYPE (0x25) -#define MAGIC_PSU_SN (0x38) -#define MAGIC_PSU_HW (0x35) -#define PSU_SIZE (256) - -typedef enum { - DBG_START, - DBG_VERBOSE, - DBG_KEY, - DBG_WARN, - DBG_ERROR, - DBG_END, -} dbg_level_t; - -static int debuglevel = 0; - -#define DBG_DEBUG(fmt, arg...) \ - do { \ - if (debuglevel > DBG_START && debuglevel < DBG_ERROR) { \ - printk(KERN_INFO "[DEBUG]:<%s, %d>:" fmt, \ - __FUNCTION__, __LINE__, ##arg); \ - } else if (debuglevel >= DBG_ERROR) { \ - printk(KERN_ERR "[DEBUG]:<%s, %d>:" fmt, __FUNCTION__, \ - __LINE__, ##arg); \ - } else { \ - } \ - } while (0) - -#define DBG_INFO(fmt, arg...) \ - do { \ - if (debuglevel > DBG_KEY) { \ - printk(KERN_INFO "[INFO]:<%s, %d>:" fmt, __FUNCTION__, \ - __LINE__, ##arg); \ - } \ - } while (0) - -#define DBG_ERROR(fmt, arg...) \ - do { \ - if (debuglevel > DBG_START) { \ - printk(KERN_ERR "[ERROR]:<%s, %d>:" fmt, __FUNCTION__, \ - __LINE__, ##arg); \ - } \ - } while (0) - -static const unsigned short rg_i2c_psu[] = { 0x50, 0x53, 0x58, 0x5b, I2C_CLIENT_END }; - -extern s32 platform_i2c_smbus_read_byte_data(const struct i2c_client *client, u8 command); -extern s32 platform_i2c_smbus_read_i2c_block_data(const struct i2c_client *client, - u8 command, u8 length, u8 *values); - -struct psu_data { - struct i2c_client *client; - struct device *hwmon_dev; - struct mutex update_lock; - char valid; /* !=0 if registers are valid */ - unsigned long last_updated; /* In jiffies */ - u8 data[PSU_SIZE]; /* Register value */ -}; - -static ssize_t show_psu_sysfs_value(struct device *dev, struct device_attribute *da, char *buf); -static ssize_t show_sysfs_15_value(struct device *dev, struct device_attribute *da, char *buf); -static ssize_t show_psu_value(struct device *dev, struct device_attribute *da, char *buf); - -static SENSOR_DEVICE_ATTR(psu_rate, S_IRUGO, show_psu_sysfs_value, NULL, MAGIC_PSU_RATE); -static SENSOR_DEVICE_ATTR(psu_out_current, S_IRUGO, show_psu_sysfs_value, NULL, MAGIC_PSU_OUT_CURRENT); -static SENSOR_DEVICE_ATTR(psu_out_voltage, S_IRUGO, show_psu_sysfs_value, NULL, MAGIC_PSU_OUT_VOLTAGE); -static SENSOR_DEVICE_ATTR(psu_in_voltage, S_IRUGO, show_psu_sysfs_value, NULL, MAGIC_PSU_IN_VOLTAGE); -static SENSOR_DEVICE_ATTR(psu_in_current, S_IRUGO, show_psu_sysfs_value, NULL, MAGIC_PSU_IN_CURRENT); -static SENSOR_DEVICE_ATTR(psu_temp, S_IRUGO, show_psu_sysfs_value, NULL, MAGIC_PSU_TEMP); -static SENSOR_DEVICE_ATTR(psu_type, S_IRUGO, show_sysfs_15_value, NULL, MAGIC_PSU_TYPE); -static SENSOR_DEVICE_ATTR(psu_sn, S_IRUGO, show_sysfs_15_value, NULL, MAGIC_PSU_SN); -static SENSOR_DEVICE_ATTR(psu_hw, S_IRUGO, show_psu_value, NULL, MAGIC_PSU_HW); - -static struct attribute *psu_pmbus_sysfs_attrs[] = { - &sensor_dev_attr_psu_rate.dev_attr.attr, - &sensor_dev_attr_psu_out_current.dev_attr.attr, - &sensor_dev_attr_psu_out_voltage.dev_attr.attr, - &sensor_dev_attr_psu_in_voltage.dev_attr.attr, - &sensor_dev_attr_psu_in_current.dev_attr.attr, - &sensor_dev_attr_psu_temp.dev_attr.attr, - NULL -}; - -static struct attribute *psu_fru_sysfs_attrs[] = { - &sensor_dev_attr_psu_type.dev_attr.attr, - &sensor_dev_attr_psu_sn.dev_attr.attr, - &sensor_dev_attr_psu_hw.dev_attr.attr, - NULL -}; - -static const struct attribute_group psu_pmbus_sysfs_attrs_group = { - .attrs = psu_pmbus_sysfs_attrs, -}; - -static const struct attribute_group psu_fru_sysfs_attrs_group = { - .attrs = psu_fru_sysfs_attrs, -}; - -static ssize_t show_psu_value(struct device *dev, struct device_attribute *da, char *buf) -{ - struct sensor_device_attribute *attr = to_sensor_dev_attr(da); - struct i2c_client *client = to_i2c_client(dev); - struct psu_data *data = i2c_get_clientdata(client); - int ret; - char psu_buf[PSU_SIZE]; - memset(psu_buf, 0, PSU_SIZE); - mutex_lock(&data->update_lock); - ret = platform_i2c_smbus_read_i2c_block_data(client, attr->index, 2, psu_buf); - if (ret < 0) { - DBG_ERROR("Failed to read psu\n"); - } - DBG_DEBUG("cpld reg pos:0x%x value:0x%02x\n", attr->index, data->data[0]); - mutex_unlock(&data->update_lock); - return snprintf(buf, 3, "%s\n", psu_buf); -} - -static int linear_to_value(short reg, bool v_out) -{ - short exponent; - int mantissa; - long val; - - if (v_out) { - exponent = -9; - mantissa = reg; - } else { - exponent = reg >> 11; - mantissa = (((reg & 0x7ff) << 5)) >> 5; - } - val = mantissa; - val = val * 1000L; - if (exponent >= 0) { - val <<= exponent; - } else { - val >>= -exponent; - } - - return val; -} - -static ssize_t show_psu_sysfs_value(struct device *dev, - struct device_attribute *da, char *buf) -{ - struct sensor_device_attribute *attr = to_sensor_dev_attr(da); - struct i2c_client *client = to_i2c_client(dev); - struct psu_data *data = i2c_get_clientdata(client); - int ret; - u8 smbud_buf[PSU_SIZE]; - uint16_t value; - int result; - - ret = -1; - memset(smbud_buf, 0, PSU_SIZE); - mutex_lock(&data->update_lock); - DBG_DEBUG("ret:%d", ret); - ret = platform_i2c_smbus_read_i2c_block_data(client, attr->index, 2, smbud_buf); - if (ret < 0) { - DBG_ERROR("Failed to read psu \n"); - } - value = smbud_buf[1]; - value = value << 8; - value |= smbud_buf[0]; - - if (attr->index == 0x8b) { - result = linear_to_value(value, true); - } else { - result = linear_to_value(value, false); - } - mutex_unlock(&data->update_lock); - return snprintf(buf, PSU_SIZE, "%d\n", result); -} - -static ssize_t show_sysfs_15_value(struct device *dev, - struct device_attribute *da, char *buf) -{ - struct sensor_device_attribute *attr = to_sensor_dev_attr(da); - struct i2c_client *client = to_i2c_client(dev); - struct psu_data *data = i2c_get_clientdata(client); - int ret; - u8 smbud_buf[PSU_SIZE]; - - memset(smbud_buf, 0, PSU_SIZE); - mutex_lock(&data->update_lock); - ret = platform_i2c_smbus_read_i2c_block_data(client, attr->index, 15, smbud_buf); - if (ret < 0) { - DBG_ERROR("Failed to read psu\n"); - } - mutex_unlock(&data->update_lock); - return snprintf(buf, PSU_SIZE, "%s\n", smbud_buf); -} - -static ssize_t show_sysfs_13_value(struct device *dev, struct device_attribute *da, char *buf) -{ - struct sensor_device_attribute *attr = to_sensor_dev_attr(da); - struct i2c_client *client = to_i2c_client(dev); - struct psu_data *data = i2c_get_clientdata(client); - int ret; - u8 smbud_buf[PSU_SIZE]; - - memset(smbud_buf, 0, PSU_SIZE); - mutex_lock(&data->update_lock); - ret = platform_i2c_smbus_read_i2c_block_data(client, attr->index, 13, smbud_buf); - if (ret < 0) { - DBG_ERROR("Failed to read psu \n"); - } - mutex_unlock(&data->update_lock); - return snprintf(buf, PSU_SIZE, "%s\n", smbud_buf); -} - -static int psu_detect(struct i2c_client *new_client, - struct i2c_board_info *info) -{ - struct i2c_adapter *adapter = new_client->adapter; - int conf; - - if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA | - I2C_FUNC_SMBUS_WORD_DATA)) - return -ENODEV; - conf = platform_i2c_smbus_read_byte_data(new_client, 0); - if (!conf) - return -ENODEV; - - return 0; -} - -static int psu_probe(struct i2c_client *client, const struct i2c_device_id *id) -{ - struct psu_data *data; - int status; - - status = -1; - data = devm_kzalloc(&client->dev, sizeof(struct psu_data), GFP_KERNEL); - if (!data) - return -ENOMEM; - - data->client = client; - i2c_set_clientdata(client, data); - mutex_init(&data->update_lock); - - switch (client->addr) { - case 0x50: - case 0x53: - status = sysfs_create_group(&client->dev.kobj, - &psu_fru_sysfs_attrs_group); - if (status != 0) { - DBG_ERROR("%s %d sysfs_create_group err\n", __func__, __LINE__); - } - break; - case 0x58: - case 0x5b: - status = sysfs_create_group(&client->dev.kobj, - &psu_pmbus_sysfs_attrs_group); - if (status != 0) { - DBG_ERROR("%s %d sysfs_create_group err\n", __func__, __LINE__); - break; - } - break; - default: - break; - } - - return status; -} - -static int psu_remove(struct i2c_client *client) -{ - switch (client->addr) { - case 0x50: - case 0x53: - sysfs_remove_group(&client->dev.kobj, &psu_fru_sysfs_attrs_group); - break; - case 0x58: - case 0x5b: - sysfs_remove_group(&client->dev.kobj, &psu_pmbus_sysfs_attrs_group); - break; - default: - break; - } - return 0; -} - -static const struct i2c_device_id psu_id[] = { - { "rg_psu", 0 }, - {} -}; -MODULE_DEVICE_TABLE(i2c, psu_id); - -static struct i2c_driver rg_psu_driver = { - .class = I2C_CLASS_HWMON, - .driver = { - .name = "rg_psu", - }, - .probe = psu_probe, - .remove = psu_remove, - .id_table = psu_id, - .detect = psu_detect, - .address_list = rg_i2c_psu, -}; - -module_i2c_driver(rg_psu_driver); - -MODULE_AUTHOR("support "); -MODULE_DESCRIPTION("ragile pmbus psu driver"); -MODULE_LICENSE("GPL"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/spi-bitbang-txrx.h b/platform/broadcom/sonic-platform-modules-ragile/common/modules/spi-bitbang-txrx.h new file mode 100644 index 000000000000..47bb9b898dfd --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/spi-bitbang-txrx.h @@ -0,0 +1,107 @@ +/* + * Mix this utility code with some glue code to get one of several types of + * simple SPI master driver. Two do polled word-at-a-time I/O: + * + * - GPIO/parport bitbangers. Provide chipselect() and txrx_word[](), + * expanding the per-word routines from the inline templates below. + * + * - Drivers for controllers resembling bare shift registers. Provide + * chipselect() and txrx_word[](), with custom setup()/cleanup() methods + * that use your controller's clock and chipselect registers. + * + * Some hardware works well with requests at spi_transfer scope: + * + * - Drivers leveraging smarter hardware, with fifos or DMA; or for half + * duplex (MicroWire) controllers. Provide chipselect() and txrx_bufs(), + * and custom setup()/cleanup() methods. + */ + +/* + * The code that knows what GPIO pins do what should have declared four + * functions, ideally as inlines, before including this header: + * + * void setsck(struct spi_device *, int is_on); + * void setmosi(struct spi_device *, int is_on); + * int getmiso(struct spi_device *); + * void spidelay(unsigned); + * + * setsck()'s is_on parameter is a zero/nonzero boolean. + * + * setmosi()'s is_on parameter is a zero/nonzero boolean. + * + * getmiso() is required to return 0 or 1 only. Any other value is invalid + * and will result in improper operation. + * + * A non-inlined routine would call bitbang_txrx_*() routines. The + * main loop could easily compile down to a handful of instructions, + * especially if the delay is a NOP (to run at peak speed). + * + * Since this is software, the timings may not be exactly what your board's + * chips need ... there may be several reasons you'd need to tweak timings + * in these routines, not just to make it faster or slower to match a + * particular CPU clock rate. + */ + +static inline u32 +bitbang_txrx_be_cpha0(struct spi_device *spi, + unsigned nsecs, unsigned cpol, unsigned flags, + u32 word, u8 bits) +{ + /* if (cpol == 0) this is SPI_MODE_0; else this is SPI_MODE_2 */ + + u32 oldbit = (!(word & (1<<(bits-1)))) << 31; + /* clock starts at inactive polarity */ + for (word <<= (32 - bits); likely(bits); bits--) { + + /* setup MSB (to slave) on trailing edge */ + if ((flags & SPI_MASTER_NO_TX) == 0) { + if ((word & (1 << 31)) != oldbit) { + setmosi(spi, word & (1 << 31)); + oldbit = word & (1 << 31); + } + } + spidelay(nsecs); /* T(setup) */ + + setsck(spi, !cpol); + spidelay(nsecs); + + /* sample MSB (from slave) on leading edge */ + word <<= 1; + if ((flags & SPI_MASTER_NO_RX) == 0) + word |= getmiso(spi); + setsck(spi, cpol); + } + return word; +} + +static inline u32 +bitbang_txrx_be_cpha1(struct spi_device *spi, + unsigned nsecs, unsigned cpol, unsigned flags, + u32 word, u8 bits) +{ + /* if (cpol == 0) this is SPI_MODE_1; else this is SPI_MODE_3 */ + + u32 oldbit = (!(word & (1<<(bits-1)))) << 31; + /* clock starts at inactive polarity */ + for (word <<= (32 - bits); likely(bits); bits--) { + + /* setup MSB (to slave) on leading edge */ + setsck(spi, !cpol); + if ((flags & SPI_MASTER_NO_TX) == 0) { + if ((word & (1 << 31)) != oldbit) { + setmosi(spi, word & (1 << 31)); + oldbit = word & (1 << 31); + } + } + spidelay(nsecs); /* T(setup) */ + + setsck(spi, cpol); + spidelay(nsecs); + + /* sample MSB (from slave) on trailing edge */ + word <<= 1; + if ((flags & SPI_MASTER_NO_RX) == 0) + word |= getmiso(spi); + } + return word; +} diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_eeprom_93xx46.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_eeprom_93xx46.c new file mode 100644 index 000000000000..2ba7e7912ed5 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_eeprom_93xx46.c @@ -0,0 +1,558 @@ +/* + * Driver for 93xx46 EEPROMs + * + * (C) 2011 DENX Software Engineering, Anatolij Gustschin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define mem_clear(data, size) memset((data), 0, (size)) + +#define OP_START 0x4 +#define OP_WRITE (OP_START | 0x1) +#define OP_READ (OP_START | 0x2) +#define ADDR_EWDS 0x00 +#define ADDR_ERAL 0x20 +#define ADDR_EWEN 0x30 + +static int g_wb_eeprom_93xx46_debug = 0; + +module_param(g_wb_eeprom_93xx46_debug, int, S_IRUGO | S_IWUSR); + +#define SPI_93xx46_DEBUG_VERBOSE(fmt, args...) do { \ + if (g_wb_eeprom_93xx46_debug) { \ + printk(KERN_INFO "[EEPROM-93xx46][VER][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +struct eeprom_93xx46_devtype_data { + unsigned int quirks; +}; + +static const struct eeprom_93xx46_devtype_data atmel_at93c46d_data = { + .quirks = EEPROM_93XX46_QUIRK_SINGLE_WORD_READ | + EEPROM_93XX46_QUIRK_INSTRUCTION_LENGTH, +}; + +struct eeprom_93xx46_dev { + struct spi_device *spi; + struct eeprom_93xx46_platform_data *pdata; + struct mutex lock; + struct nvmem_config nvmem_config; + struct nvmem_device *nvmem; + int addrlen; + int size; +}; + +static inline bool has_quirk_single_word_read(struct eeprom_93xx46_dev *edev) +{ + return edev->pdata->quirks & EEPROM_93XX46_QUIRK_SINGLE_WORD_READ; +} + +static inline bool has_quirk_instruction_length(struct eeprom_93xx46_dev *edev) +{ + return edev->pdata->quirks & EEPROM_93XX46_QUIRK_INSTRUCTION_LENGTH; +} + +static int eeprom_93xx46_read(void *priv, unsigned int off, + void *val, size_t count) +{ + struct eeprom_93xx46_dev *edev = priv; + char *buf = val; + int err = 0; + + if (unlikely(off >= edev->size)) + return 0; + if ((off + count) > edev->size) + count = edev->size - off; + if (unlikely(!count)) + return count; + + mutex_lock(&edev->lock); + + if (edev->pdata->prepare) + edev->pdata->prepare(edev); + + while (count) { + struct spi_message m; + struct spi_transfer t[2] = { { 0 } }; + u16 cmd_addr = OP_READ << edev->addrlen; + size_t nbytes = count; + int bits; + int data_bit; + + if (edev->addrlen == 7) { + cmd_addr |= off & 0x7f; + bits = 10; + data_bit = 8; + if (has_quirk_single_word_read(edev)) + nbytes = 1; + } else { + cmd_addr |= (off >> 1) & 0x3f; + bits = 9; + data_bit = 16; + if (has_quirk_single_word_read(edev)) + nbytes = 2; + } + + dev_dbg(&edev->spi->dev, "read cmd 0x%x, %d Hz\n", + cmd_addr, edev->spi->max_speed_hz); + + spi_message_init(&m); + + t[0].tx_buf = (char *)&cmd_addr; + t[0].len = 2; + t[0].bits_per_word = bits; + spi_message_add_tail(&t[0], &m); + + t[1].rx_buf = buf; + t[1].len = nbytes; + t[1].bits_per_word = data_bit; + spi_message_add_tail(&t[1], &m); + + err = spi_sync(edev->spi, &m); + /* have to wait at least Tcsl ns */ + ndelay(250); + + if (err) { + dev_err(&edev->spi->dev, "read %zu bytes at %d: err. %d\n", + nbytes, (int)off, err); + break; + } + + buf += nbytes; + off += nbytes; + count -= nbytes; + } + + if (edev->pdata->finish) + edev->pdata->finish(edev); + + mutex_unlock(&edev->lock); + + return err; +} + +static int eeprom_93xx46_ew(struct eeprom_93xx46_dev *edev, int is_on) +{ + struct spi_message m; + struct spi_transfer t; + int bits, ret; + u16 cmd_addr; + + cmd_addr = OP_START << edev->addrlen; + if (edev->addrlen == 7) { + cmd_addr |= (is_on ? ADDR_EWEN : ADDR_EWDS) << 1; + bits = 10; + } else { + cmd_addr |= (is_on ? ADDR_EWEN : ADDR_EWDS); + bits = 9; + } + + if (has_quirk_instruction_length(edev)) { + cmd_addr <<= 2; + bits += 2; + } + + dev_dbg(&edev->spi->dev, "ew%s cmd 0x%04x, %d bits\n", + is_on ? "en" : "ds", cmd_addr, bits); + + spi_message_init(&m); + mem_clear(&t, sizeof(t)); + + t.tx_buf = &cmd_addr; + t.len = 2; + t.bits_per_word = bits; + spi_message_add_tail(&t, &m); + + mutex_lock(&edev->lock); + + if (edev->pdata->prepare) + edev->pdata->prepare(edev); + + ret = spi_sync(edev->spi, &m); + /* have to wait at least Tcsl ns */ + ndelay(250); + if (ret) + dev_err(&edev->spi->dev, "erase/write %sable error %d\n", + is_on ? "en" : "dis", ret); + + if (edev->pdata->finish) + edev->pdata->finish(edev); + + mutex_unlock(&edev->lock); + return ret; +} + +static ssize_t +eeprom_93xx46_write_word(struct eeprom_93xx46_dev *edev, + char *buf, unsigned off) +{ + struct spi_message m; + struct spi_transfer t[2]; + int bits, data_len, ret; + u16 cmd_addr; + int data_bit; + + cmd_addr = OP_WRITE << edev->addrlen; + + if (edev->addrlen == 7) { + cmd_addr |= off & 0x7f; + bits = 10; + data_len = 1; + data_bit = 8; + } else { + cmd_addr |= (off >> 1) & 0x3f; + bits = 9; + data_len = 2; + data_bit = 16; + } + + dev_dbg(&edev->spi->dev, "write cmd 0x%x\n", cmd_addr); + + spi_message_init(&m); + mem_clear(t, sizeof(t)); + + t[0].tx_buf = (char *)&cmd_addr; + t[0].len = 2; + t[0].bits_per_word = bits; + spi_message_add_tail(&t[0], &m); + + t[1].tx_buf = buf; + t[1].len = data_len; + t[1].bits_per_word = data_bit; + spi_message_add_tail(&t[1], &m); + + ret = spi_sync(edev->spi, &m); + /* have to wait program cycle time Twc ms */ + mdelay(6); + return ret; +} + +static int eeprom_93xx46_write(void *priv, unsigned int off, + void *val, size_t count) +{ + struct eeprom_93xx46_dev *edev = priv; + char *buf = val; + int i, ret, step = 1; + + if (unlikely(off >= edev->size)) + return -EFBIG; + if ((off + count) > edev->size) + count = edev->size - off; + if (unlikely(!count)) + return count; + + /* only write even number of bytes on 16-bit devices */ + if (edev->addrlen == 6) { + step = 2; + count &= ~1; + } + + /* erase/write enable */ + ret = eeprom_93xx46_ew(edev, 1); + if (ret) + return ret; + + mutex_lock(&edev->lock); + + if (edev->pdata->prepare) + edev->pdata->prepare(edev); + + for (i = 0; i < count; i += step) { + ret = eeprom_93xx46_write_word(edev, &buf[i], off + i); + if (ret) { + dev_err(&edev->spi->dev, "write failed at %d: %d\n", + (int)off + i, ret); + break; + } + } + + if (edev->pdata->finish) + edev->pdata->finish(edev); + + mutex_unlock(&edev->lock); + + /* erase/write disable */ + eeprom_93xx46_ew(edev, 0); + return ret; +} + +static int eeprom_93xx46_eral(struct eeprom_93xx46_dev *edev) +{ + struct eeprom_93xx46_platform_data *pd = edev->pdata; + struct spi_message m; + struct spi_transfer t; + int bits, ret; + u16 cmd_addr; + + cmd_addr = OP_START << edev->addrlen; + if (edev->addrlen == 7) { + cmd_addr |= ADDR_ERAL << 1; + bits = 10; + } else { + cmd_addr |= ADDR_ERAL; + bits = 9; + } + + if (has_quirk_instruction_length(edev)) { + cmd_addr <<= 2; + bits += 2; + } + + dev_dbg(&edev->spi->dev, "eral cmd 0x%04x, %d bits\n", cmd_addr, bits); + + spi_message_init(&m); + mem_clear(&t, sizeof(t)); + + t.tx_buf = &cmd_addr; + t.len = 2; + t.bits_per_word = bits; + spi_message_add_tail(&t, &m); + + mutex_lock(&edev->lock); + + if (edev->pdata->prepare) + edev->pdata->prepare(edev); + + ret = spi_sync(edev->spi, &m); + if (ret) + dev_err(&edev->spi->dev, "erase error %d\n", ret); + /* have to wait erase cycle time Tec ms */ + mdelay(6); + + if (pd->finish) + pd->finish(edev); + + mutex_unlock(&edev->lock); + return ret; +} + +static ssize_t eeprom_93xx46_store_erase(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct eeprom_93xx46_dev *edev = dev_get_drvdata(dev); + int erase = 0, ret; + + sscanf(buf, "%d", &erase); + if (erase) { + ret = eeprom_93xx46_ew(edev, 1); + if (ret) + return ret; + ret = eeprom_93xx46_eral(edev); + if (ret) + return ret; + ret = eeprom_93xx46_ew(edev, 0); + if (ret) + return ret; + } + return count; +} +static DEVICE_ATTR(erase, S_IWUSR, NULL, eeprom_93xx46_store_erase); + +static void select_assert(void *context) +{ + struct eeprom_93xx46_dev *edev = context; + + gpiod_set_value_cansleep(edev->pdata->select, 1); +} + +static void select_deassert(void *context) +{ + struct eeprom_93xx46_dev *edev = context; + + gpiod_set_value_cansleep(edev->pdata->select, 0); +} + +static const struct of_device_id eeprom_93xx46_of_table[] = { + { .compatible = "eeprom-93xx46", }, + { .compatible = "atmel,at93c46d", .data = &atmel_at93c46d_data, }, + {} +}; +MODULE_DEVICE_TABLE(of, eeprom_93xx46_of_table); + +static int eeprom_93xx46_probe_dt(struct spi_device *spi) +{ + const struct of_device_id *of_id = + of_match_device(eeprom_93xx46_of_table, &spi->dev); + struct device_node *np = spi->dev.of_node; + struct eeprom_93xx46_platform_data *pd; + u32 tmp; + int gpio; + enum of_gpio_flags of_flags; + int ret; + + pd = devm_kzalloc(&spi->dev, sizeof(*pd), GFP_KERNEL); + if (!pd) + return -ENOMEM; + + ret = of_property_read_u32(np, "data-size", &tmp); + if (ret < 0) { + dev_err(&spi->dev, "data-size property not found\n"); + return ret; + } + + if (tmp == 8) { + pd->flags |= EE_ADDR8; + } else if (tmp == 16) { + pd->flags |= EE_ADDR16; + } else { + dev_err(&spi->dev, "invalid data-size (%d)\n", tmp); + return -EINVAL; + } + + if (of_property_read_bool(np, "read-only")) + pd->flags |= EE_READONLY; + + gpio = of_get_named_gpio_flags(np, "select-gpios", 0, &of_flags); + if (gpio_is_valid(gpio)) { + unsigned long flags = + of_flags == OF_GPIO_ACTIVE_LOW ? GPIOF_ACTIVE_LOW : 0; + + ret = devm_gpio_request_one(&spi->dev, gpio, flags, + "eeprom_93xx46_select"); + if (ret) + return ret; + + pd->select = gpio_to_desc(gpio); + pd->prepare = select_assert; + pd->finish = select_deassert; + + gpiod_direction_output(pd->select, 0); + } + + if (of_id) { + if (of_id->data) { + const struct eeprom_93xx46_devtype_data *data = of_id->data; + + pd->quirks = data->quirks; + } + } + + spi->dev.platform_data = pd; + + return 0; +} + +static int eeprom_93xx46_probe(struct spi_device *spi) +{ + struct eeprom_93xx46_platform_data *pd; + struct eeprom_93xx46_dev *edev; + int err; + + if (spi->dev.of_node) { + err = eeprom_93xx46_probe_dt(spi); + if (err < 0) + return err; + } + + pd = spi->dev.platform_data; + if (!pd) { + dev_err(&spi->dev, "missing platform data\n"); + return -ENODEV; + } + + edev = kzalloc(sizeof(*edev), GFP_KERNEL); + if (!edev) + return -ENOMEM; + + if (pd->flags & EE_ADDR8) + edev->addrlen = 7; + else if (pd->flags & EE_ADDR16) + edev->addrlen = 6; + else { + dev_err(&spi->dev, "unspecified address type\n"); + err = -EINVAL; + goto fail; + } + + mutex_init(&edev->lock); + + edev->spi = spi; + edev->pdata = pd; + + edev->size = 128; + edev->nvmem_config.name = dev_name(&spi->dev); + edev->nvmem_config.dev = &spi->dev; + edev->nvmem_config.read_only = pd->flags & EE_READONLY; + edev->nvmem_config.root_only = true; + edev->nvmem_config.owner = THIS_MODULE; + edev->nvmem_config.compat = true; + edev->nvmem_config.base_dev = &spi->dev; + edev->nvmem_config.reg_read = eeprom_93xx46_read; + edev->nvmem_config.reg_write = eeprom_93xx46_write; + edev->nvmem_config.priv = edev; + edev->nvmem_config.stride = 4; + edev->nvmem_config.word_size = 1; + edev->nvmem_config.size = edev->size; + + edev->nvmem = nvmem_register(&edev->nvmem_config); + if (IS_ERR(edev->nvmem)) { + err = PTR_ERR(edev->nvmem); + goto fail; + } + + if (g_wb_eeprom_93xx46_debug) { + dev_info(&spi->dev, "%d-bit eeprom %s\n", + (pd->flags & EE_ADDR8) ? 8 : 16, + (pd->flags & EE_READONLY) ? "(readonly)" : ""); + } + + if (!(pd->flags & EE_READONLY)) { + if (device_create_file(&spi->dev, &dev_attr_erase)) + dev_err(&spi->dev, "can't create erase interface\n"); + } + + spi_set_drvdata(spi, edev); + return 0; +fail: + kfree(edev); + return err; +} + +static int eeprom_93xx46_remove(struct spi_device *spi) +{ + struct eeprom_93xx46_dev *edev = spi_get_drvdata(spi); + + nvmem_unregister(edev->nvmem); + + if (!(edev->pdata->flags & EE_READONLY)) + device_remove_file(&spi->dev, &dev_attr_erase); + + kfree(edev); + return 0; +} + +static struct spi_driver wb_eeprom_93xx46_driver = { + .driver = { + .name = "wb_93xx46", + .of_match_table = of_match_ptr(eeprom_93xx46_of_table), + }, + .probe = eeprom_93xx46_probe, + .remove = eeprom_93xx46_remove, +}; + +module_spi_driver(wb_eeprom_93xx46_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Driver for 93xx46 EEPROMs"); +MODULE_AUTHOR("support"); +MODULE_ALIAS("spi:93xx46"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_fpga_i2c_bus_drv.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_fpga_i2c_bus_drv.c new file mode 100644 index 000000000000..e46663514e06 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_fpga_i2c_bus_drv.c @@ -0,0 +1,1121 @@ +/* + * fpga_i2c_bus_drv.c + * ko to create fpga i2c adapter + */ +#include +#include +#include +#include +#include +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,12,0) +#include +#endif +#include +#include +#include +#include +#include +#include +#include "fpga_i2c.h" + +#include +#include + +#define DRV_NAME "wb-fpga-i2c" +#define DRV_VERSION "1.0" +#define DTS_NO_CFG_FLAG (0) + +extern int i2c_device_func_write(const char *path, uint32_t pos, uint8_t *val, size_t size); +extern int i2c_device_func_read(const char *path, uint32_t pos, uint8_t *val, size_t size); +extern int pcie_device_func_read(const char *path, uint32_t offset, uint8_t *buf, size_t count); +extern int pcie_device_func_write(const char *path, uint32_t offset, uint8_t *buf, size_t count); +extern int io_device_func_write(const char *path, uint32_t pos, uint8_t *val, size_t size); +extern int io_device_func_read(const char *path, uint32_t pos, uint8_t *val, size_t size); +extern int spi_device_func_read(const char *path, uint32_t offset, uint8_t *buf, size_t count); +extern int spi_device_func_write(const char *path, uint32_t offset, uint8_t *buf, size_t count); + + +#define FPGA_I2C_STRETCH_TIMEOUT (0x01) +#define FPGA_I2C_DEADLOCK_FAILED (0x02) +#define FPGA_I2C_SLAVE_NO_RESPOND (0x03) +#define FPGA_I2C_STA_FAIL (0x01) +#define FPGA_I2C_STA_BUSY (0x02) +#define FPGA_I2C_CTL_BG (0x01 << 1) +#define FPGA_I2C_CTL_NO_REG (0x01 << 2) +#define FPGA_I2C_CTL_RD (0x01) +#define FPGA_I2C_CTL_WR (0x00) +#define I2C_READ_MSG_NUM (0x02) +#define I2C_WRITE_MSG_NUM (0x01) +#define FPGA_REG_WIDTH (4) + +#define SYMBOL_I2C_DEV_MODE (1) +#define FILE_MODE (2) +#define SYMBOL_PCIE_DEV_MODE (3) +#define SYMBOL_IO_DEV_MODE (4) +#define SYMBOL_SPI_DEV_MODE (5) + +int g_wb_fpga_i2c_debug = 0; +int g_wb_fpga_i2c_error = 0; + +module_param(g_wb_fpga_i2c_debug, int, S_IRUGO | S_IWUSR); +module_param(g_wb_fpga_i2c_error, int, S_IRUGO | S_IWUSR); + +#define FPGA_I2C_VERBOSE(fmt, args...) do { \ + if (g_wb_fpga_i2c_debug) { \ + printk(KERN_INFO "[FPFA_I2C_BUS][VER][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +#define FPGA_I2C_ERROR(fmt, args...) do { \ + if (g_wb_fpga_i2c_error) { \ + printk(KERN_ERR "[FPFA_I2C_BUS][ERR][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +static int fpga_file_read(const char *path, uint32_t pos, uint8_t *val, size_t size) +{ + int ret; + struct file *filp; + loff_t tmp_pos; + + filp = filp_open(path, O_RDONLY, 0); + if (IS_ERR(filp)) { + FPGA_I2C_ERROR("read open failed errno = %ld\r\n", -PTR_ERR(filp)); + filp = NULL; + goto exit; + } + + tmp_pos = (loff_t)pos; + ret = kernel_read(filp, val, size, &tmp_pos); + if (ret < 0) { + FPGA_I2C_ERROR("kernel_read failed, path=%s, addr=0x%x, size=%ld, ret=%d\r\n", path, pos, size, ret); + goto exit; + } + + filp_close(filp, NULL); + + return ret; + +exit: + if (filp != NULL) { + filp_close(filp, NULL); + } + + return -1; +} + +static int fpga_file_write(const char *path, uint32_t pos, uint8_t *val, size_t size) +{ + int ret; + struct file *filp; + loff_t tmp_pos; + + filp = filp_open(path, O_RDWR, 777); + if (IS_ERR(filp)) { + FPGA_I2C_ERROR("write open failed errno = %ld\r\n", -PTR_ERR(filp)); + filp = NULL; + goto exit; + } + + tmp_pos = (loff_t)pos; + ret = kernel_write(filp, val, size, &tmp_pos); + if (ret < 0) { + FPGA_I2C_ERROR("kernel_write failed, path=%s, addr=0x%x, size=%ld, ret=%d\r\n", path, pos, size, ret); + goto exit; + } + vfs_fsync(filp, 1); + filp_close(filp, NULL); + + return ret; + +exit: + if (filp != NULL) { + filp_close(filp, NULL); + } + + return -1; +} + +static int fpga_device_write(fpga_i2c_dev_t *fpga_i2c, uint32_t pos, uint8_t *val, size_t size) +{ + int ret; + + switch (fpga_i2c->i2c_func_mode) { + case SYMBOL_I2C_DEV_MODE: + ret = i2c_device_func_write(fpga_i2c->dev_name, pos, val, size); + break; + case FILE_MODE: + ret = fpga_file_write(fpga_i2c->dev_name, pos, val, size); + break; + case SYMBOL_PCIE_DEV_MODE: + ret = pcie_device_func_write(fpga_i2c->dev_name, pos, val, size); + break; + case SYMBOL_IO_DEV_MODE: + ret = io_device_func_write(fpga_i2c->dev_name, pos, val, size); + break; + case SYMBOL_SPI_DEV_MODE: + ret = spi_device_func_write(fpga_i2c->dev_name, pos, val, size); + break; + default: + FPGA_I2C_ERROR("err func_mode, write failed.\n"); + return -EINVAL; + } + return ret; + +} + +static int fpga_device_read(fpga_i2c_dev_t *fpga_i2c, uint32_t pos, uint8_t *val, size_t size) +{ + int ret; + + switch (fpga_i2c->i2c_func_mode) { + case SYMBOL_I2C_DEV_MODE: + ret = i2c_device_func_read(fpga_i2c->dev_name, pos, val, size); + break; + case FILE_MODE: + ret = fpga_file_read(fpga_i2c->dev_name, pos, val, size); + break; + case SYMBOL_PCIE_DEV_MODE: + ret = pcie_device_func_read(fpga_i2c->dev_name, pos, val, size); + break; + case SYMBOL_IO_DEV_MODE: + ret = io_device_func_read(fpga_i2c->dev_name, pos, val, size); + break; + case SYMBOL_SPI_DEV_MODE: + ret = spi_device_func_read(fpga_i2c->dev_name, pos, val, size); + break; + default: + FPGA_I2C_ERROR("err func_mode, read failed.\n"); + return -EINVAL; + } + + return ret; +} + +static int little_endian_dword_to_buf(uint8_t *buf, int len, uint32_t dword) +{ + uint8_t tmp_buf[FPGA_REG_WIDTH]; + + if (len < 4) { + FPGA_I2C_ERROR("Not enough buf, dword to buf: len[%d], dword[0x%x]\n", len, dword); + return -1; + } + + mem_clear(tmp_buf, sizeof(tmp_buf)); + tmp_buf[0] = dword & 0xff; + tmp_buf[1] = (dword >> 8) & 0xff; + tmp_buf[2] = (dword >> 16) & 0xff; + tmp_buf[3] = (dword >> 24) & 0xff; + + memcpy(buf, tmp_buf, sizeof(tmp_buf)); + + return 0; +} + +static int little_endian_buf_to_dword(uint8_t *buf, int len, uint32_t *dword) +{ + int i; + uint32_t dword_tmp; + + if (len != FPGA_REG_WIDTH) { + FPGA_I2C_ERROR("buf length %d error, can't convert to dowrd.\n", len); + return -1; + } + dword_tmp = 0; + for (i = 0; i < FPGA_REG_WIDTH; i++) { + dword_tmp |= (buf[i] << (i * 8)); + } + *dword = dword_tmp; + return 0; +} + +static int fpga_reg_write(fpga_i2c_dev_t *fpga_i2c, uint32_t addr, uint8_t val) +{ + int ret; + + ret = fpga_device_write(fpga_i2c, addr, &val, sizeof(uint8_t)); + if (ret < 0) { + FPGA_I2C_ERROR("fpga reg write failed, dev name:%s, offset:0x%x, value:0x%x.\n", + fpga_i2c->dev_name, addr, val); + return -EIO; + } + + FPGA_I2C_VERBOSE("fpga reg write success, dev name:%s, offset:0x%x, value:0x%x.\n", + fpga_i2c->dev_name, addr, val); + return 0; +} + +static int fpga_reg_read(fpga_i2c_dev_t *fpga_i2c, uint32_t addr, uint8_t *val) +{ + int ret; + + ret = fpga_device_read(fpga_i2c, addr, val, sizeof(uint8_t)); + if (ret < 0) { + FPGA_I2C_ERROR("fpga reg read failed, dev name:%s, offset:0x%x\n", + fpga_i2c->dev_name, addr); + return -EIO; + } + + FPGA_I2C_VERBOSE("fpga reg read success, dev name:%s, offset:0x%x, value:0x%x.\n", + fpga_i2c->dev_name, addr, *val); + return 0; +} + +static int fpga_data_write(fpga_i2c_dev_t *fpga_i2c, uint32_t addr, uint8_t *val, size_t size) +{ + int ret; + + ret = fpga_device_write(fpga_i2c, addr, val, size); + if (ret < 0) { + FPGA_I2C_ERROR("fpga data write failed, dev name:%s, offset:0x%x, size:%lu.\n", + fpga_i2c->dev_name, addr, size); + return -EIO; + } + + FPGA_I2C_VERBOSE("fpga data write success, dev name:%s, offset:0x%x, size:%lu.\n", + fpga_i2c->dev_name, addr, size); + return 0; +} + +static int fpga_data_read(fpga_i2c_dev_t *fpga_i2c, uint32_t addr, uint8_t *val, size_t size) +{ + int ret; + + ret = fpga_device_read(fpga_i2c, addr, val, size); + if (ret < 0) { + FPGA_I2C_ERROR("fpga data read failed, dev name:%s, offset:0x%x, size:%lu.\n", + fpga_i2c->dev_name, addr, size); + return -EIO; + } + + FPGA_I2C_VERBOSE("fpga data read success, dev name:%s, offset:0x%x, size:%lu.\n", + fpga_i2c->dev_name, addr, size); + return 0; +} + +static int fpga_reg_write_32(fpga_i2c_dev_t *fpga_i2c, uint32_t addr, uint32_t val) +{ + int ret; + uint8_t buf[FPGA_REG_WIDTH]; + + mem_clear(buf, sizeof(buf)); + little_endian_dword_to_buf(buf, sizeof(buf), val); + ret = fpga_device_write(fpga_i2c, addr, buf, sizeof(buf)); + if (ret < 0) { + FPGA_I2C_ERROR("fpga reg write failed, dev name: %s, offset: 0x%x, value: 0x%x.\n", + fpga_i2c->dev_name, addr, val); + return -EIO; + } + + FPGA_I2C_VERBOSE("fpga reg write success, dev name: %s, offset: 0x%x, value: 0x%x.\n", + fpga_i2c->dev_name, addr, val); + return 0; +} + +static int fpga_reg_read_32(fpga_i2c_dev_t *fpga_i2c, uint32_t addr, uint32_t *val) +{ + int ret; + uint8_t buf[FPGA_REG_WIDTH]; + + mem_clear(buf, sizeof(buf)); + ret = fpga_device_read(fpga_i2c, addr, buf, sizeof(buf)); + if (ret < 0) { + FPGA_I2C_ERROR("fpga reg read failed, dev name: %s, offset: 0x%x, ret: %d\n", + fpga_i2c->dev_name, addr, ret); + return -EIO; + } + little_endian_buf_to_dword(buf, sizeof(buf), val); + FPGA_I2C_VERBOSE("fpga reg read success, dev name: %s, offset: 0x%x, value: 0x%x.\n", + fpga_i2c->dev_name, addr, *val); + return 0; +} + +static int fpga_i2c_is_busy(fpga_i2c_dev_t *fpga_i2c) +{ + uint8_t val; + int ret; + fpga_i2c_reg_t *reg; + + reg = &fpga_i2c->reg; + ret = fpga_reg_read(fpga_i2c, reg->i2c_status, &val); + if (ret < 0 ) { + FPGA_I2C_ERROR("read fpga i2c status reg failed, reg addr:0x%x, ret:%d.\n", + reg->i2c_status, ret); + return 1; + } + if (val & FPGA_I2C_STA_BUSY) { + FPGA_I2C_ERROR("fpga i2c status busy, reg addr:0x%x, value:0x%x.\n", + reg->i2c_status, val); + return 1; + } else { + return 0; + } +} + +static int fpga_i2c_wait(fpga_i2c_dev_t *fpga_i2c) +{ + int retry_cnt; + + retry_cnt = FPGA_I2C_XFER_TIME_OUT/FPGA_I2C_SLEEP_TIME; + while (retry_cnt--) { + if (fpga_i2c_is_busy(fpga_i2c)) { + usleep_range(FPGA_I2C_SLEEP_TIME, FPGA_I2C_SLEEP_TIME + 1); + } else { + return 0; + } + } + + return -EBUSY; +} + +static int fpga_i2c_check_status(fpga_i2c_dev_t *fpga_i2c) +{ + uint8_t data; + int ret; + fpga_i2c_reg_t *reg; + + reg = &fpga_i2c->reg; + + ret = fpga_reg_read(fpga_i2c, reg->i2c_status, &data); + if (ret) { + FPGA_I2C_ERROR("read fpga i2c status reg failed, reg addr:0x%x, ret:%d.\n", + reg->i2c_status, ret); + return ret; + } + + if (data & FPGA_I2C_STA_FAIL) { + FPGA_I2C_ERROR("fpga i2c status error, reg addr:0x%x, value:%d.\n", + reg->i2c_status, data); + + /* read i2c_err_vec to confirm err type*/ + if (reg->i2c_err_vec != DTS_NO_CFG_FLAG) { + /* read i2c_err_vec reg */ + ret = fpga_reg_read(fpga_i2c, reg->i2c_err_vec, &data); + if (ret) { + FPGA_I2C_ERROR("read fpga i2c err vec reg failed, reg addr:0x%x, ret:%d.\n", + reg->i2c_err_vec, ret); + return ret; + } + FPGA_I2C_VERBOSE("get i2c err vec, reg addr:0x%x, read value:0x%x\n", reg->i2c_err_vec, data); + + /* match i2c_err_vec reg value and err type*/ + switch (data) { + case FPGA_I2C_STRETCH_TIMEOUT: + ret = -ETIMEDOUT; + break; + case FPGA_I2C_DEADLOCK_FAILED: + ret = -EDEADLK; + break; + case FPGA_I2C_SLAVE_NO_RESPOND: + ret = -ENXIO; + break; + default: + FPGA_I2C_ERROR("get i2c err vec value out of range, reg addr:0x%x, read value:0x%x\n", + reg->i2c_err_vec, data); + ret = -EREMOTEIO; + break; + } + return ret; + } else { + FPGA_I2C_VERBOSE("i2c err vec not config, fpga i2c status check return -1\n"); + return -EREMOTEIO; + } + } + return 0; +} + +static int fpga_i2c_do_work(fpga_i2c_dev_t *fpga_i2c, int i2c_addr, + unsigned char *data, uint32_t length, int is_read) +{ + int ret, i; + uint8_t op, i2c_reg_addr_len; + uint8_t *i2c_read_addr_buf; + fpga_i2c_reg_t *reg; + fpga_i2c_reg_addr_t *i2c_addr_desc; + + reg = &fpga_i2c->reg; + + ret = fpga_reg_write(fpga_i2c, reg->i2c_slave, i2c_addr); + if (ret) { + FPGA_I2C_ERROR("write fpga i2c slave reg failed, reg addr:0x%x, value:0x%x, ret:%d.\n", + reg->i2c_slave, i2c_addr, ret); + goto exit; + } + + i2c_addr_desc = &fpga_i2c->i2c_addr_desc; + i2c_reg_addr_len = i2c_addr_desc->reg_addr_len; + i2c_read_addr_buf = &i2c_addr_desc->read_reg_addr[0]; + + if (i2c_reg_addr_len > 0 && i2c_reg_addr_len <= I2C_REG_MAX_WIDTH) { + ret = fpga_data_write(fpga_i2c, reg->i2c_reg, i2c_read_addr_buf, i2c_reg_addr_len); + if (ret) { + FPGA_I2C_ERROR("write fpga i2c offset reg failed, fpga addr:0x%x, reg len:%d, ret:%d\n", + reg->i2c_reg, i2c_reg_addr_len, ret); + for (i = 0; i < i2c_reg_addr_len; i++) { + FPGA_I2C_ERROR("%02d : %02x\n", i, i2c_read_addr_buf[i]); + } + goto exit; + } + } + + ret = fpga_reg_write_32(fpga_i2c, reg->i2c_data_len, length); + if (ret) { + FPGA_I2C_ERROR("write fpga i2c date len reg failed, reg addr:0x%x, value:0x%x, ret:%d.\n", + reg->i2c_data_len, length, ret); + goto exit; + } + + ret = fpga_reg_write(fpga_i2c, reg->i2c_reg_len, i2c_reg_addr_len); + if (ret) { + FPGA_I2C_ERROR("write fpga i2c reg len reg failed, reg addr:0x%x, value:0x%x, ret:%d.\n", + reg->i2c_reg_len, i2c_reg_addr_len, ret); + goto exit; + } + + if (is_read) { + op = FPGA_I2C_CTL_RD | FPGA_I2C_CTL_BG; + } else { + + ret = fpga_data_write(fpga_i2c, reg->i2c_data_buf, data, length); + if (ret) { + FPGA_I2C_ERROR("write fpga i2c date buf failed, reg addr:0x%x, write len:%d, ret:%d.\n", + reg->i2c_data_buf, length, ret); + goto exit; + } + op = FPGA_I2C_CTL_WR | FPGA_I2C_CTL_BG ; + } + + ret = fpga_reg_write(fpga_i2c, reg->i2c_ctrl, op); + if (ret) { + FPGA_I2C_ERROR("write fpga i2c control reg failed, reg addr:0x%x, value:%d, ret:%d.\n", + reg->i2c_ctrl, op, ret); + goto exit; + } + + ret = fpga_i2c_wait(fpga_i2c); + if (ret) { + FPGA_I2C_ERROR("wait fpga i2c status timeout.\n"); + goto exit; + } + + ret = fpga_i2c_check_status(fpga_i2c); + if (ret) { + FPGA_I2C_ERROR("check fpga i2c status error.\n"); + goto exit; + } + + if (is_read) { + + ret = fpga_data_read(fpga_i2c, reg->i2c_data_buf, data, length); + if (ret) { + FPGA_I2C_ERROR("read fpga i2c data buf failed, reg addr:0x%x, read len:%d, ret:%d.\n", + reg->i2c_data_buf, length, ret); + goto exit; + } + } + +exit: + return ret; +} + +static int fpga_i2c_write(fpga_i2c_dev_t *fpga_i2c, int target, + u8 *data, int length, int i2c_msg_num) +{ + int ret, i; + fpga_i2c_reg_addr_t *i2c_addr_desc; + + if (i2c_msg_num == I2C_READ_MSG_NUM) { + + if (length > I2C_REG_MAX_WIDTH) { + FPGA_I2C_ERROR("read reg addr len %d, more than max length.\n", length); + return -EINVAL; + } + + i2c_addr_desc = &fpga_i2c->i2c_addr_desc; + for (i = 0; i < length; i++) { + i2c_addr_desc->read_reg_addr[i] = data[length -i -1]; + FPGA_I2C_VERBOSE("%02d : %02x\n", i, i2c_addr_desc->read_reg_addr[i]); + } + i2c_addr_desc->reg_addr_len = length; + ret = 0; + } else { + + ret = fpga_i2c_do_work(fpga_i2c, target, data, length, 0); + } + + return ret; +} + +/** + * fpga_i2c_read - receive data from the bus. + * @i2c: The struct fpga_i2c_dev_t. + * @target: Target address. + * @data: Pointer to the location to store the datae . + * @length: Length of the data. + * + * The address is sent over the bus, then the data is read. + * + * Returns 0 on success, otherwise a negative errno. + */ +static int fpga_i2c_read(fpga_i2c_dev_t *fpga_i2c, int target, + u8 *data, int length) +{ + int ret, offset_size; + int i, tmp_val; + fpga_i2c_reg_addr_t *i2c_addr_desc; + uint8_t i2c_reg_addr_len; + uint8_t *i2c_read_addr_buf; + + offset_size = 0; + i2c_addr_desc = &fpga_i2c->i2c_addr_desc; + i2c_reg_addr_len = i2c_addr_desc->reg_addr_len; + i2c_read_addr_buf = &i2c_addr_desc->read_reg_addr[0]; + + while (1) { + if (length <= fpga_i2c->reg.i2c_data_buf_len) { + return fpga_i2c_do_work(fpga_i2c, target, data + offset_size, length, 1); + } + + ret = fpga_i2c_do_work(fpga_i2c, target, data + offset_size, fpga_i2c->reg.i2c_data_buf_len, 1); + if (ret != 0) { + FPGA_I2C_ERROR("fpga_i2c_read failed, i2c addr:0x%x, offset:0x%x, ret:%d.\n", + target, offset_size, ret); + return ret; + } + + tmp_val = i2c_read_addr_buf[0]; + tmp_val += fpga_i2c->reg.i2c_data_buf_len; + if (tmp_val > 0xff) { + i2c_read_addr_buf[0] = tmp_val & 0xff; + for (i = 1; i < i2c_reg_addr_len; i++) { + if (i2c_read_addr_buf[i] == 0xff) { + i2c_read_addr_buf[i] = 0; + } else { + i2c_read_addr_buf[i]++; + break; + } + } + } else { + i2c_read_addr_buf[0] = tmp_val & 0xff; + } + offset_size += fpga_i2c->reg.i2c_data_buf_len; + length -= fpga_i2c->reg.i2c_data_buf_len; + } + + return ret; +} + +static void fpga_i2c_reset(fpga_i2c_dev_t *fpga_i2c) { + fpga_i2c_reset_cfg_t *reset_cfg; + uint32_t reset_addr; + + reset_cfg = &fpga_i2c->reset_cfg; + reset_addr = reset_cfg->reset_addr; + if (reset_cfg->reset_delay_b) { + usleep_range(reset_cfg->reset_delay_b, reset_cfg->reset_delay_b + 1); + } + + fpga_reg_write_32(fpga_i2c, reset_addr, reset_cfg->reset_on); + if (reset_cfg->reset_delay) { + usleep_range(reset_cfg->reset_delay, reset_cfg->reset_delay + 1); + } + + fpga_reg_write_32(fpga_i2c, reset_addr, reset_cfg->reset_off); + if (reset_cfg->reset_delay_a) { + usleep_range(reset_cfg->reset_delay_a, reset_cfg->reset_delay_a + 1); + } + + return; +} + +/** + * fpga_i2c_xfer - The driver's master_xfer function. + * @adap: Pointer to the i2c_adapter structure. + * @msgs: Pointer to the messages to be processed. + * @num: Length of the MSGS array. + * + * Returns the number of messages processed, or a negative errno on + * failure. + */ +static int fpga_i2c_adapter_init(fpga_i2c_dev_t *fpga_i2c) +{ + int ret; + fpga_i2c_reg_t *reg; + + reg = &fpga_i2c->reg; + + ret = 0; + ret += fpga_reg_write(fpga_i2c, reg->i2c_scale, fpga_i2c->i2c_scale_value); + ret += fpga_reg_write(fpga_i2c, reg->i2c_filter, fpga_i2c->i2c_filter_value); + ret += fpga_reg_write(fpga_i2c, reg->i2c_stretch, fpga_i2c->i2c_stretch_value); + if (ret < 0) { + FPGA_I2C_ERROR("fpga_i2c_init failed.\n"); + return ret; + } + + FPGA_I2C_VERBOSE("fpga_i2c_init ok.\n"); + return 0; +} + +static int fpga_i2c_params_check(fpga_i2c_dev_t *fpga_i2c) +{ + int ret; + fpga_i2c_reg_t *reg; + uint8_t i2c_scale_value, i2c_filter_value, i2c_stretch_value; + + reg = &fpga_i2c->reg; + ret = 0; + ret += fpga_reg_read(fpga_i2c, reg->i2c_scale, &i2c_scale_value); + ret += fpga_reg_read(fpga_i2c, reg->i2c_filter, &i2c_filter_value); + ret += fpga_reg_read(fpga_i2c, reg->i2c_stretch, &i2c_stretch_value); + if (ret < 0) { + FPGA_I2C_ERROR("read fpga i2c params failed.\n"); + return 1; + } + + if ((i2c_scale_value != fpga_i2c->i2c_scale_value) + || (i2c_filter_value != fpga_i2c->i2c_filter_value) + || (i2c_stretch_value != fpga_i2c->i2c_stretch_value)) { + FPGA_I2C_ERROR("fpga i2c params check error, read value: i2c_scale 0x%x, i2c_filter:0x%x, i2c_stretch:0x%x.\n", + i2c_scale_value, i2c_filter_value, i2c_stretch_value); + FPGA_I2C_ERROR("fpga i2c params check error, config value: i2c_scale 0x%x, i2c_filter:0x%x, i2c_stretch:0x%x.\n", + fpga_i2c->i2c_scale_value, fpga_i2c->i2c_filter_value, fpga_i2c->i2c_stretch_value); + return 1; + } + + FPGA_I2C_VERBOSE("fpga i2c params check ok.\n"); + return 0; +} + +static int fpga_i2c_xfer(struct i2c_adapter *adap, + struct i2c_msg *msgs, int num) +{ + struct i2c_msg *pmsg; + int i; + int ret; + fpga_i2c_dev_t *fpga_i2c; + fpga_i2c_reg_addr_t *i2c_addr_desc; + + fpga_i2c = i2c_get_adapdata(adap); + + if (num != I2C_READ_MSG_NUM && num != I2C_WRITE_MSG_NUM) { + FPGA_I2C_ERROR("unsupport i2c_msg len:%d.\n", num); + return -EINVAL; + } + + if ((num == I2C_WRITE_MSG_NUM) && (msgs[0].len > fpga_i2c->reg.i2c_data_buf_len)) { + FPGA_I2C_ERROR("unsupport i2c_msg type:msg[0].flag:0x%x, buf len:0x%x.\n", + msgs[0].flags, msgs[0].len); + return -EINVAL; + } + + if (num == I2C_READ_MSG_NUM ) { + if ((msgs[0].flags & I2C_M_RD) ||!(msgs[1].flags & I2C_M_RD)) { + FPGA_I2C_ERROR("unsupport i2c_msg type:msg[0].flag:0x%x, msg[1].flag:0x%x.\n", + msgs[0].flags, msgs[1].flags); + return -EINVAL; + } + } + + if (fpga_i2c_is_busy(fpga_i2c)) { + FPGA_I2C_ERROR("fpga i2c adapter %d is busy, do reset.\n", adap->nr); + if (fpga_i2c->reset_cfg.i2c_adap_reset_flag == 1) { + + fpga_i2c_reset(fpga_i2c); + + fpga_i2c_adapter_init(fpga_i2c); + } + return -EAGAIN; + } + + if (fpga_i2c->i2c_params_check && fpga_i2c_params_check(fpga_i2c)) { + FPGA_I2C_ERROR("fpga i2c params check failed, try to reinitialize.\n"); + fpga_i2c_adapter_init(fpga_i2c); + } + + ret = 0; + i2c_addr_desc = &fpga_i2c->i2c_addr_desc; + i2c_addr_desc->reg_addr_len = 0; + mem_clear(i2c_addr_desc->read_reg_addr, sizeof(i2c_addr_desc->read_reg_addr)); + + for (i = 0; ret == 0 && i < num; i++) { + pmsg = &msgs[i]; + FPGA_I2C_VERBOSE("Doing %s %d byte(s) to/from 0x%02x - %d of %d messages\n", + pmsg->flags & I2C_M_RD ? "read" : "write", pmsg->len, pmsg->addr, i + 1, num); + + if (pmsg->flags & I2C_M_RD) { + ret = fpga_i2c_read(fpga_i2c, pmsg->addr, pmsg->buf, pmsg->len); + + if ((pmsg->len == 1) && (pmsg->flags & I2C_M_RECV_LEN)) { + if ((ret != 0) || (pmsg->buf[0] > I2C_SMBUS_BLOCK_MAX)) { + FPGA_I2C_ERROR("smbus block data read failed, ret:%d, read len:%u.\n", + ret, pmsg->buf[0]); + return -EPROTO; + } + pmsg->len = 1 + pmsg->buf[0]; + FPGA_I2C_VERBOSE("smbus block data read, read len:%d.\n", pmsg->len); + ret = fpga_i2c_read(fpga_i2c, pmsg->addr, pmsg->buf, pmsg->len); + } + } else { + ret = fpga_i2c_write(fpga_i2c, pmsg->addr, pmsg->buf, pmsg->len, num); + } + } + + return (ret != 0) ? ret : num; +} + +static u32 fpga_i2c_functionality(struct i2c_adapter *adap) +{ + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA; +} + +static const struct i2c_algorithm fpga_i2c_algo = { + .master_xfer = fpga_i2c_xfer, + .functionality = fpga_i2c_functionality, +}; + +static struct i2c_adapter fpga_i2c_ops = { + .owner = THIS_MODULE, + .name = "wb_fpga_i2c", + .algo = &fpga_i2c_algo, +}; + +static int fpga_i2c_config_init(fpga_i2c_dev_t *fpga_i2c) +{ + int ret = 0, rv = 0; + fpga_i2c_reg_t *reg; + fpga_i2c_reset_cfg_t *reset_cfg; + struct device *dev; + uint32_t i2c_offset_reg, i2c_data_buf_len_reg; + int32_t i2c_offset_val; + + fpga_i2c_bus_device_t *fpga_i2c_bus_device; + + dev = fpga_i2c->dev; + reg = &fpga_i2c->reg; + reset_cfg = &fpga_i2c->reset_cfg; + + i2c_offset_val = 0; + + if (dev->of_node) { + ret = 0; + ret += of_property_read_u32(dev->of_node, "i2c_ext_9548_addr", ®->i2c_ext_9548_addr); + ret += of_property_read_u32(dev->of_node, "i2c_ext_9548_chan", ®->i2c_ext_9548_chan); + ret += of_property_read_u32(dev->of_node, "i2c_slave", ®->i2c_slave); + ret += of_property_read_u32(dev->of_node, "i2c_reg", ®->i2c_reg); + ret += of_property_read_u32(dev->of_node, "i2c_data_len", ®->i2c_data_len); + ret += of_property_read_u32(dev->of_node, "i2c_ctrl", ®->i2c_ctrl); + ret += of_property_read_u32(dev->of_node, "i2c_status", ®->i2c_status); + ret += of_property_read_u32(dev->of_node, "i2c_scale", ®->i2c_scale); + ret += of_property_read_u32(dev->of_node, "i2c_filter", ®->i2c_filter); + ret += of_property_read_u32(dev->of_node, "i2c_stretch", ®->i2c_stretch); + ret += of_property_read_u32(dev->of_node, "i2c_ext_9548_exits_flag", ®->i2c_ext_9548_exits_flag); + ret += of_property_read_u32(dev->of_node, "i2c_reg_len", ®->i2c_reg_len); + ret += of_property_read_u32(dev->of_node, "i2c_in_9548_chan", ®->i2c_in_9548_chan); + ret += of_property_read_u32(dev->of_node, "i2c_data_buf", ®->i2c_data_buf); + ret += of_property_read_string(dev->of_node, "dev_name", &fpga_i2c->dev_name); + ret += of_property_read_u32(dev->of_node, "i2c_scale_value", &fpga_i2c->i2c_scale_value); + ret += of_property_read_u32(dev->of_node, "i2c_filter_value", &fpga_i2c->i2c_filter_value); + ret += of_property_read_u32(dev->of_node, "i2c_stretch_value", &fpga_i2c->i2c_stretch_value); + ret += of_property_read_u32(dev->of_node, "i2c_timeout", &fpga_i2c->i2c_timeout); + ret += of_property_read_u32(dev->of_node, "i2c_func_mode", &fpga_i2c->i2c_func_mode); + ret += of_property_read_u32(dev->of_node, "i2c_reset_addr", &reset_cfg->reset_addr); + ret += of_property_read_u32(dev->of_node, "i2c_reset_on", &reset_cfg->reset_on); + ret += of_property_read_u32(dev->of_node, "i2c_reset_off", &reset_cfg->reset_off); + ret += of_property_read_u32(dev->of_node, "i2c_rst_delay_b", &reset_cfg->reset_delay_b); + ret += of_property_read_u32(dev->of_node, "i2c_rst_delay", &reset_cfg->reset_delay); + ret += of_property_read_u32(dev->of_node, "i2c_rst_delay_a", &reset_cfg->reset_delay_a); + ret += of_property_read_u32(dev->of_node, "i2c_adap_reset_flag", &reset_cfg->i2c_adap_reset_flag); + + if (ret != 0) { + FPGA_I2C_ERROR("dts config error, ret:%d.\n", ret); + ret = -ENXIO; + return ret; + } + + rv = of_property_read_u32(dev->of_node, "i2c_data_buf_len_reg", &i2c_data_buf_len_reg); + if (rv == 0) { + ret = fpga_reg_read_32(fpga_i2c, i2c_data_buf_len_reg, ®->i2c_data_buf_len); + if (ret < 0) { + dev_err(fpga_i2c->dev, "Failed to get fpga i2c data buf length, reg addr: 0x%x, ret: %d\n", + i2c_data_buf_len_reg, ret); + return ret; + } + FPGA_I2C_VERBOSE("fpga i2c data buf length reg addr: 0x%x, value: %d\n", + i2c_data_buf_len_reg, reg->i2c_data_buf_len); + if (reg->i2c_data_buf_len == 0) { + reg->i2c_data_buf_len = FPGA_I2C_RDWR_MAX_LEN_DEFAULT; + } + } else { + ret = of_property_read_u32(dev->of_node, "i2c_data_buf_len", ®->i2c_data_buf_len); + if (ret != 0) { + reg->i2c_data_buf_len = FPGA_I2C_RDWR_MAX_LEN_DEFAULT; + ret = 0; + } + } + + rv = of_property_read_u32(dev->of_node, "i2c_offset_reg", &i2c_offset_reg); + if (rv == 0) { + ret = fpga_reg_read_32(fpga_i2c, i2c_offset_reg, &i2c_offset_val); + if (ret < 0) { + dev_err(fpga_i2c->dev, "Failed to get fpga i2c adapter offset value, reg addr: 0x%x, ret: %d\n", + i2c_offset_reg, ret); + return ret; + } + FPGA_I2C_VERBOSE("fpga i2c adapter offset reg addr: 0x%x, value: %d\n", + i2c_offset_reg, i2c_offset_val); + reg->i2c_scale +=i2c_offset_val; + reg->i2c_filter += i2c_offset_val; + reg->i2c_stretch += i2c_offset_val; + reg->i2c_ext_9548_exits_flag += i2c_offset_val; + reg->i2c_ext_9548_addr += i2c_offset_val; + reg->i2c_ext_9548_chan += i2c_offset_val; + reg->i2c_in_9548_chan += i2c_offset_val; + reg->i2c_slave += i2c_offset_val; + reg->i2c_reg += i2c_offset_val; + reg->i2c_reg_len += i2c_offset_val; + reg->i2c_data_len += i2c_offset_val; + reg->i2c_ctrl += i2c_offset_val; + reg->i2c_status += i2c_offset_val; + reg->i2c_data_buf += i2c_offset_val; + } + + ret = of_property_read_u32(dev->of_node, "i2c_err_vec", ®->i2c_err_vec); + if (ret != 0) { + reg->i2c_err_vec = DTS_NO_CFG_FLAG; + FPGA_I2C_VERBOSE("not support i2c_err_vec cfg. ret: %d, set DTS_NO_CFG_FLAG: %d\n", + ret, reg->i2c_err_vec); + ret = 0; /* Not configuring i2c_err_vec is not an error */ + } else { + if (i2c_offset_val != 0) { + reg->i2c_err_vec += i2c_offset_val; + } + } + } else { + if (dev->platform_data == NULL) { + dev_err(fpga_i2c->dev, "Failed to get platform data config.\n"); + ret = -ENXIO; + return ret; + } + fpga_i2c_bus_device = dev->platform_data; + fpga_i2c->dev_name = fpga_i2c_bus_device->dev_name; + fpga_i2c->adap_nr = fpga_i2c_bus_device->adap_nr; + fpga_i2c->i2c_scale_value = fpga_i2c_bus_device->i2c_scale_value; + fpga_i2c->i2c_filter_value = fpga_i2c_bus_device->i2c_filter_value; + fpga_i2c->i2c_stretch_value = fpga_i2c_bus_device->i2c_stretch_value; + fpga_i2c->i2c_timeout = fpga_i2c_bus_device->i2c_timeout; + fpga_i2c->i2c_func_mode = fpga_i2c_bus_device->i2c_func_mode; + fpga_i2c->i2c_params_check = fpga_i2c_bus_device->i2c_func_mode; + + reset_cfg->reset_addr = fpga_i2c_bus_device->i2c_reset_addr; + reset_cfg->reset_on = fpga_i2c_bus_device->i2c_reset_on; + reset_cfg->reset_off = fpga_i2c_bus_device->i2c_reset_off; + reset_cfg->reset_delay_b = fpga_i2c_bus_device->i2c_rst_delay_b; + reset_cfg->reset_delay = fpga_i2c_bus_device->i2c_rst_delay; + reset_cfg->reset_delay_a = fpga_i2c_bus_device->i2c_rst_delay_a; + reset_cfg->i2c_adap_reset_flag = fpga_i2c_bus_device->i2c_adap_reset_flag; + + reg->i2c_ext_9548_addr = fpga_i2c_bus_device->i2c_ext_9548_addr; + reg->i2c_ext_9548_chan = fpga_i2c_bus_device->i2c_ext_9548_chan; + reg->i2c_slave = fpga_i2c_bus_device->i2c_slave; + reg->i2c_reg = fpga_i2c_bus_device->i2c_reg; + reg->i2c_data_len = fpga_i2c_bus_device->i2c_data_len; + reg->i2c_ctrl = fpga_i2c_bus_device->i2c_ctrl; + reg->i2c_status = fpga_i2c_bus_device->i2c_status; + reg->i2c_scale = fpga_i2c_bus_device->i2c_scale; + reg->i2c_filter = fpga_i2c_bus_device->i2c_filter; + reg->i2c_stretch = fpga_i2c_bus_device->i2c_stretch; + reg->i2c_ext_9548_exits_flag = fpga_i2c_bus_device->i2c_ext_9548_exits_flag; + reg->i2c_reg_len = fpga_i2c_bus_device->i2c_reg_len; + reg->i2c_in_9548_chan = fpga_i2c_bus_device->i2c_in_9548_chan; + reg->i2c_data_buf = fpga_i2c_bus_device->i2c_data_buf; + + i2c_data_buf_len_reg = fpga_i2c_bus_device->i2c_data_buf_len_reg; + if (i2c_data_buf_len_reg > 0) { + ret = fpga_reg_read_32(fpga_i2c, i2c_data_buf_len_reg, ®->i2c_data_buf_len); + if (ret < 0) { + dev_err(fpga_i2c->dev, "Failed to get fpga i2c data buf length, reg addr: 0x%x, ret: %d\n", + i2c_data_buf_len_reg, ret); + return ret; + } + FPGA_I2C_VERBOSE("fpga i2c data buf length reg addr: 0x%x, value: %d\n", + i2c_data_buf_len_reg, reg->i2c_data_buf_len); + if (reg->i2c_data_buf_len == 0) { + reg->i2c_data_buf_len = FPGA_I2C_RDWR_MAX_LEN_DEFAULT; + } + } else { + if (fpga_i2c_bus_device->i2c_data_buf_len == 0) { + reg->i2c_data_buf_len = FPGA_I2C_RDWR_MAX_LEN_DEFAULT; + FPGA_I2C_VERBOSE("not support i2c_data_buf_len cfg, set default_val:%d\n", + reg->i2c_data_buf_len); + } else { + reg->i2c_data_buf_len = fpga_i2c_bus_device->i2c_data_buf_len; + } + } + + i2c_offset_reg = fpga_i2c_bus_device->i2c_offset_reg; + if (i2c_offset_reg > 0) { + rv = fpga_reg_read_32(fpga_i2c, i2c_offset_reg, &i2c_offset_val); + if (rv < 0) { + dev_err(fpga_i2c->dev, "Failed to get fpga i2c adapter offset value, reg addr: 0x%x, rv: %d\n", + i2c_offset_reg, rv); + return rv; + } + FPGA_I2C_VERBOSE("fpga i2c adapter offset reg addr: 0x%x, value: %d\n", + i2c_offset_reg, i2c_offset_val); + reg->i2c_scale +=i2c_offset_val; + reg->i2c_filter += i2c_offset_val; + reg->i2c_stretch += i2c_offset_val; + reg->i2c_ext_9548_exits_flag += i2c_offset_val; + reg->i2c_ext_9548_addr += i2c_offset_val; + reg->i2c_ext_9548_chan += i2c_offset_val; + reg->i2c_in_9548_chan += i2c_offset_val; + reg->i2c_slave += i2c_offset_val; + reg->i2c_reg += i2c_offset_val; + reg->i2c_reg_len += i2c_offset_val; + reg->i2c_data_len += i2c_offset_val; + reg->i2c_ctrl += i2c_offset_val; + reg->i2c_status += i2c_offset_val; + reg->i2c_data_buf += i2c_offset_val; + } + + if (fpga_i2c_bus_device->i2c_err_vec == 0) { + reg->i2c_err_vec = DTS_NO_CFG_FLAG; + FPGA_I2C_VERBOSE("not support i2c_err_vec cfg, set DTS_NO_CFG_FLAG:%d\n", + reg->i2c_err_vec); + } else { + reg->i2c_err_vec = fpga_i2c_bus_device->i2c_err_vec; + if (i2c_offset_val != 0) { + reg->i2c_err_vec += i2c_offset_val; + } + } + } + + FPGA_I2C_VERBOSE("i2c_ext_9548_addr:0x%x, i2c_ext_9548_chan:0x%x, i2c_slave:0x%x, i2c_reg:0x%x, i2c_data_len:0x%x.\n", + reg->i2c_ext_9548_addr, reg->i2c_ext_9548_chan, reg->i2c_slave, reg->i2c_reg, reg->i2c_data_len); + FPGA_I2C_VERBOSE("i2c_ctrl:0x%x, i2c_status:0x%x, i2c_scale:0x%x, i2c_filter:0x%x, i2c_stretch:0x%x.\n", + reg->i2c_ctrl, reg->i2c_status, reg->i2c_scale, reg->i2c_filter, reg->i2c_stretch); + FPGA_I2C_VERBOSE("i2c_ext_9548_exits_flag:0x%x, i2c_in_9548_chan:0x%x, i2c_data_buf:0x%x, i2c_reg_len:0x%x, i2c_data_buf_len:0x%x.\n", + reg->i2c_ext_9548_exits_flag, reg->i2c_in_9548_chan, reg->i2c_data_buf, reg->i2c_reg_len, reg->i2c_data_buf_len); + FPGA_I2C_VERBOSE("dev_name:%s, i2c_scale_value:0x%x, i2c_filter_value:0x%x, i2c_stretch_value:0x%x, i2c_timeout:0x%x.\n", + fpga_i2c->dev_name, fpga_i2c->i2c_scale_value, fpga_i2c->i2c_filter_value, fpga_i2c->i2c_stretch_value, fpga_i2c->i2c_timeout); + FPGA_I2C_VERBOSE("i2c_reset_addr:0x%x, i2c_reset_on:0x%x, i2c_reset_off:0x%x, i2c_rst_delay_b:0x%x, i2c_rst_delay:0x%x, i2c_rst_delay_a:0x%x.\n", + reset_cfg->reset_addr, reset_cfg->reset_on, reset_cfg->reset_off, reset_cfg->reset_delay_b, reset_cfg->reset_delay, reset_cfg->reset_delay_a); + FPGA_I2C_VERBOSE("i2c_adap_reset_flag:0x%x.\n", reset_cfg->i2c_adap_reset_flag); + FPGA_I2C_VERBOSE("i2c_err_vec:0x%x\n", reg->i2c_err_vec); + + return ret; +} + +static int fpga_i2c_probe(struct platform_device *pdev) +{ + int ret; + fpga_i2c_dev_t *fpga_i2c; + struct device *dev; + + fpga_i2c = devm_kzalloc(&pdev->dev, sizeof(fpga_i2c_dev_t), GFP_KERNEL); + if (!fpga_i2c) { + dev_err(&pdev->dev, "devm_kzalloc failed.\n"); + ret = -ENOMEM; + goto out; + } + + fpga_i2c->dev = &pdev->dev; + + ret = fpga_i2c_config_init(fpga_i2c); + if (ret !=0) { + dev_err(fpga_i2c->dev, "Failed to get fpga i2c dts config.\n"); + goto out; + } + + ret = fpga_i2c_adapter_init(fpga_i2c); + if (ret !=0) { + dev_err(fpga_i2c->dev, "Failed to init fpga i2c adapter.\n"); + goto out; + } + + if (fpga_i2c->dev->of_node) { + fpga_i2c->i2c_params_check = of_property_read_bool(fpga_i2c->dev->of_node, "i2c_params_check"); + } + FPGA_I2C_VERBOSE("fpga i2c params check flag:%d.\n", fpga_i2c->i2c_params_check); + + init_waitqueue_head(&fpga_i2c->queue); + + dev = fpga_i2c->dev; + fpga_i2c->adap = fpga_i2c_ops; + fpga_i2c->adap.timeout = msecs_to_jiffies(fpga_i2c->i2c_timeout); + fpga_i2c->adap.dev.parent = &pdev->dev; + fpga_i2c->adap.dev.of_node = pdev->dev.of_node; + i2c_set_adapdata(&fpga_i2c->adap, fpga_i2c); + platform_set_drvdata(pdev, fpga_i2c); + + if (fpga_i2c->dev->of_node) { + /* adap.nr get from dts aliases */ + ret = i2c_add_adapter(&fpga_i2c->adap); + } else { + fpga_i2c->adap.nr = fpga_i2c->adap_nr; + ret = i2c_add_numbered_adapter(&fpga_i2c->adap); + } + + if (ret < 0) { + dev_info(fpga_i2c->dev, "Failed to add adapter.\n"); + goto fail_add; + } + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,12,0) + of_i2c_register_devices(&fpga_i2c->adap); +#endif + dev_info(fpga_i2c->dev, "registered i2c-%d for %s using mode %d with base address:0x%x, data buf len: %d success.\n", + fpga_i2c->adap.nr, fpga_i2c->dev_name, fpga_i2c->i2c_func_mode, fpga_i2c->reg.i2c_scale, + fpga_i2c->reg.i2c_data_buf_len); + return 0; + +fail_add: + platform_set_drvdata(pdev, NULL); +out: + return ret; +}; + +static int fpga_i2c_remove(struct platform_device *pdev) +{ + fpga_i2c_dev_t *fpga_i2c; + + fpga_i2c = platform_get_drvdata(pdev); + i2c_del_adapter(&fpga_i2c->adap); + platform_set_drvdata(pdev, NULL); + return 0; +}; + +static struct of_device_id fpga_i2c_match[] = { + { + .compatible = "wb-fpga-i2c", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, fpga_i2c_match); + +static struct platform_driver wb_fpga_i2c_driver = { + .probe = fpga_i2c_probe, + .remove = fpga_i2c_remove, + .driver = { + .owner = THIS_MODULE, + .name = DRV_NAME, + .of_match_table = fpga_i2c_match, + }, +}; + +static int __init wb_fpga_i2c_init(void) +{ + return platform_driver_register(&wb_fpga_i2c_driver); +} + +static void __exit wb_fpga_i2c_exit(void) +{ + platform_driver_unregister(&wb_fpga_i2c_driver); +} + +module_init(wb_fpga_i2c_init); +module_exit(wb_fpga_i2c_exit); +MODULE_DESCRIPTION("fpga i2c adapter driver"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("support"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_fpga_pca954x_drv.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_fpga_pca954x_drv.c new file mode 100644 index 000000000000..5845195bb310 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_fpga_pca954x_drv.c @@ -0,0 +1,525 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "fpga_i2c.h" + +extern int i2c_device_func_write(const char *path, uint32_t pos, uint8_t *val, size_t size); +extern int pcie_device_func_write(const char *path, uint32_t offset, uint8_t *buf, size_t count); + +#define PCA954X_MAX_NCHANS (8) +#define FPGA_INTERNAL_PCA9548 (1) +#define FPGA_EXTERNAL_PCA9548 (2) +#define FPGA_I2C_EXT_9548_EXITS (0x01 << 0) +#define FPGA_I2C_9548_NO_RESET (0x01 << 1) + +#define SYMBOL_I2C_DEV_MODE (1) +#define FILE_MODE (2) +#define SYMBOL_PCIE_DEV_MODE (3) +#define SYMBOL_IO_DEV_MODE (4) + +int g_fpga_pca954x_debug = 0; +int g_fpga_pca954x_error = 0; + +module_param(g_fpga_pca954x_debug, int, S_IRUGO | S_IWUSR); +module_param(g_fpga_pca954x_error, int, S_IRUGO | S_IWUSR); + +#define FPGA_PCA954X_VERBOSE(fmt, args...) do { \ + if (g_fpga_pca954x_debug) { \ + printk(KERN_INFO "[FPGA_PCA954X][VER][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +#define FPGA_PCA954X_ERROR(fmt, args...) do { \ + if (g_fpga_pca954x_error) { \ + printk(KERN_ERR "[FPGA_PCA954X][ERR][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +enum pca_type { + pca_9540, + pca_9541, + pca_9542, + pca_9543, + pca_9544, + pca_9545, + pca_9546, + pca_9547, + pca_9548, +}; + +struct pca954x { + enum pca_type type; + struct i2c_adapter *virt_adaps[PCA954X_MAX_NCHANS]; + u8 last_chan; /* last register value */ + uint32_t fpga_9548_flag; + uint32_t fpga_9548_reset_flag; + uint32_t pca9548_base_nr; + struct i2c_client *client; +}; + +struct chip_desc { + u8 nchans; + u8 enable; /* used for muxes only */ + enum muxtype { + pca954x_ismux = 0, + pca954x_isswi + } muxtype; +}; + +/* Provide specs for the PCA954x types we know about */ +static const struct chip_desc chips[] = { + [pca_9540] = { + .nchans = 2, + .enable = 0x4, + .muxtype = pca954x_ismux, + }, + [pca_9541] = { + .nchans = 1, + .muxtype = pca954x_isswi, + }, + [pca_9543] = { + .nchans = 2, + .muxtype = pca954x_isswi, + }, + [pca_9544] = { + .nchans = 4, + .enable = 0x4, + .muxtype = pca954x_ismux, + }, + [pca_9545] = { + .nchans = 4, + .muxtype = pca954x_isswi, + }, + [pca_9547] = { + .nchans = 8, + .enable = 0x8, + .muxtype = pca954x_ismux, + }, + [pca_9548] = { + .nchans = 8, + .muxtype = pca954x_isswi, + }, +}; + +static const struct i2c_device_id fpga_pca954x_id[] = { + { "wb_fpga_pca9540", pca_9540 }, + { "wb_fpga_pca9541", pca_9541 }, + { "wb_fpga_pca9542", pca_9543 }, + { "wb_fpga_pca9543", pca_9543 }, + { "wb_fpga_pca9544", pca_9544 }, + { "wb_fpga_pca9545", pca_9545 }, + { "wb_fpga_pca9546", pca_9545 }, + { "wb_fpga_pca9547", pca_9547 }, + { "wb_fpga_pca9548", pca_9548 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, fpga_pca954x_id); + +static int fpga_file_write(const char *path, int pos, unsigned char *val, size_t size) +{ + int ret; + struct file *filp; + loff_t tmp_pos; + + filp = filp_open(path, O_RDWR, 777); + if (IS_ERR(filp)) { + FPGA_PCA954X_ERROR("write open failed errno = %ld\r\n", -PTR_ERR(filp)); + filp = NULL; + goto exit; + } + + tmp_pos = (loff_t)pos; + ret = kernel_write(filp, val, size, &tmp_pos); + if (ret < 0) { + FPGA_PCA954X_ERROR("kernel_write failed, path=%s, addr=%d, size=%ld, ret=%d\r\n", path, pos, size, ret); + goto exit; + } + + vfs_fsync(filp, 1); + filp_close(filp, NULL); + + return ret; + +exit: + if (filp != NULL) { + filp_close(filp, NULL); + } + + return -1; + +} +static int fpga_device_write(fpga_i2c_dev_t *fpga_i2c, int pos, unsigned char *val, size_t size) +{ + int ret; + + switch (fpga_i2c->i2c_func_mode) { + case SYMBOL_I2C_DEV_MODE: + ret = i2c_device_func_write(fpga_i2c->dev_name, pos, val, size); + break; + case FILE_MODE: + ret = fpga_file_write(fpga_i2c->dev_name, pos, val, size); + break; + case SYMBOL_PCIE_DEV_MODE: + ret = pcie_device_func_write(fpga_i2c->dev_name, pos, val, size); + break; + default: + FPGA_PCA954X_ERROR("err func mode, write failed.\n"); + return -EINVAL; + } + + return ret; +} + +static int fpga_reg_write(fpga_i2c_dev_t *fpga_i2c, uint32_t addr, uint8_t val) +{ + int ret; + + ret = fpga_device_write(fpga_i2c, addr, &val, sizeof(uint8_t)); + if (ret < 0) { + FPGA_PCA954X_ERROR("fpga_device_write failed. name:%s, addr:0x%x, value:0x%x.\n", + fpga_i2c->dev_name, addr, val); + return ret; + } + + FPGA_PCA954X_VERBOSE("fpga reg write success, dev name:%s, offset:0x%x, value:0x%x.\n", + fpga_i2c->dev_name, addr, val); + return 0; +} + +#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,7) +static int pca954x_select_chan(struct i2c_adapter *adap, void *client, u32 chan) +{ + struct pca954x *data = i2c_get_clientdata(client); + fpga_i2c_dev_t *fpga_i2c; + fpga_i2c_reg_t *reg; + int ret; + u8 regval, i2c_9548_opt; + + while(i2c_parent_is_i2c_adapter(adap)){ + adap = to_i2c_adapter(adap->dev.parent); + } + + FPGA_PCA954X_VERBOSE("root bus:%d, chan:0x%x, 9548 flag:0x%x, 9548 addr:0x%x.\n", + adap->nr, chan, data->fpga_9548_flag, client->addr); + fpga_i2c = i2c_get_adapdata(adap); + reg = &fpga_i2c->reg; + + regval = 1 << chan; + if (data->fpga_9548_flag == FPGA_INTERNAL_PCA9548) { + ret = fpga_reg_write(fpga_i2c, reg->i2c_in_9548_chan, regval); + } else { + if (data->fpga_9548_reset_flag == 1) { + i2c_9548_opt = FPGA_I2C_EXT_9548_EXITS & ~(FPGA_I2C_9548_NO_RESET); + } else { + i2c_9548_opt = FPGA_I2C_EXT_9548_EXITS | FPGA_I2C_9548_NO_RESET; + } + FPGA_PCA954X_VERBOSE("fpga pca9548 reset flag:0x%x, opt:0x%x.\n", + data->fpga_9548_reset_flag, i2c_9548_opt); + ret = fpga_reg_write(fpga_i2c, reg->i2c_ext_9548_exits_flag, i2c_9548_opt); + ret += fpga_reg_write(fpga_i2c, reg->i2c_ext_9548_addr, client->addr); + ret += fpga_reg_write(fpga_i2c, reg->i2c_ext_9548_chan, regval); + } + + return ret; +} + +static int pca954x_deselect_mux(struct i2c_adapter *adap, void *client, u32 chan) +{ + struct pca954x *data = i2c_get_clientdata(client); + fpga_i2c_dev_t *fpga_i2c; + fpga_i2c_reg_t *reg; + int ret; + + while(i2c_parent_is_i2c_adapter(adap)){ + adap = to_i2c_adapter(adap->dev.parent); + } + + fpga_i2c = i2c_get_adapdata(adap); + reg = &fpga_i2c->reg; + /* Deselect active channel */ + data->last_chan = 0; + if (data->fpga_9548_flag == FPGA_INTERNAL_PCA9548) { + ret = fpga_reg_write(fpga_i2c, reg->i2c_in_9548_chan, 0); + } else { + + ret = fpga_reg_write(fpga_i2c, reg->i2c_ext_9548_exits_flag, FPGA_I2C_9548_NO_RESET); + ret += fpga_reg_write(fpga_i2c, reg->i2c_ext_9548_chan, 0); + } + + return ret; +} +#else +static int pca954x_select_chan(struct i2c_mux_core *muxc, u32 chan) +{ + struct pca954x *data = i2c_mux_priv(muxc); + struct i2c_client *client = data->client; + struct i2c_adapter *adap; + fpga_i2c_dev_t *fpga_i2c; + fpga_i2c_reg_t *reg; + int ret; + u8 regval, i2c_9548_opt; + + adap = muxc->parent; + while(i2c_parent_is_i2c_adapter(adap)){ + adap = to_i2c_adapter(adap->dev.parent); + } + + FPGA_PCA954X_VERBOSE("root bus:%d, chan:0x%x, 9548 flag:0x%x, 9548 addr:0x%x.\n", + adap->nr, chan, data->fpga_9548_flag, client->addr); + fpga_i2c = i2c_get_adapdata(adap); + reg = &fpga_i2c->reg; + + regval = 1 << chan; + if (data->fpga_9548_flag == FPGA_INTERNAL_PCA9548) { + ret = fpga_reg_write(fpga_i2c, reg->i2c_in_9548_chan, regval); + } else { + if (data->fpga_9548_reset_flag == 1) { + i2c_9548_opt = FPGA_I2C_EXT_9548_EXITS & ~(FPGA_I2C_9548_NO_RESET); + } else { + i2c_9548_opt = FPGA_I2C_EXT_9548_EXITS | FPGA_I2C_9548_NO_RESET; + } + FPGA_PCA954X_VERBOSE("fpga pca9548 reset flag:0x%x, opt:0x%x.\n", + data->fpga_9548_reset_flag, i2c_9548_opt); + ret = fpga_reg_write(fpga_i2c, reg->i2c_ext_9548_exits_flag, i2c_9548_opt); + ret += fpga_reg_write(fpga_i2c, reg->i2c_ext_9548_addr, client->addr); + ret += fpga_reg_write(fpga_i2c, reg->i2c_ext_9548_chan, regval); + } + + return ret; +} + +static int pca954x_deselect_mux(struct i2c_mux_core *muxc, u32 chan) +{ + struct pca954x *data = i2c_mux_priv(muxc); + struct i2c_adapter *adap; + fpga_i2c_dev_t *fpga_i2c; + fpga_i2c_reg_t *reg; + int ret; + + adap = muxc->parent; + while(i2c_parent_is_i2c_adapter(adap)){ + adap = to_i2c_adapter(adap->dev.parent); + } + + fpga_i2c = i2c_get_adapdata(adap); + reg = &fpga_i2c->reg; + ret = 0; + /* Deselect active channel */ + data->last_chan = 0; + + if (data->fpga_9548_flag == FPGA_INTERNAL_PCA9548) { + ret = fpga_reg_write(fpga_i2c, reg->i2c_in_9548_chan, 0); + } else { + + ret = fpga_reg_write(fpga_i2c, reg->i2c_ext_9548_exits_flag, FPGA_I2C_9548_NO_RESET); + ret += fpga_reg_write(fpga_i2c, reg->i2c_ext_9548_chan, 0); + } + + return ret; +} +#endif +/* + * I2C init/probing/exit functions + */ +static int fpga_i2c_pca954x_probe(struct i2c_client *client, const struct i2c_device_id *id) +{ + struct i2c_adapter *adap = to_i2c_adapter(client->dev.parent); + int num, force, class; + struct pca954x *data; + int ret = -ENODEV; + struct device *dev; + int dynamic_nr = 1; + fpga_pca954x_device_t *fpga_pca954x_device; + +#if LINUX_VERSION_CODE > KERNEL_VERSION(4,6,7) + struct i2c_mux_core *muxc; +#endif + + if (!i2c_check_functionality(adap, I2C_FUNC_SMBUS_BYTE)) { + dev_err(&client->dev, "i2c adapter:%d, unsupport I2C_FUNC_SMBUS_BYTE.\n", adap->nr); + goto err; + } + +#if LINUX_VERSION_CODE <= KERNEL_VERSION(4,6,7) + data = kzalloc(sizeof(struct pca954x), GFP_KERNEL); + if (!data) { + dev_err(&client->dev, "kzalloc failed.\n"); + ret = -ENOMEM; + goto err; + } + + i2c_set_clientdata(client, data); +#else + muxc = i2c_mux_alloc(adap, &client->dev, + PCA954X_MAX_NCHANS, sizeof(*data), 0, + pca954x_select_chan, pca954x_deselect_mux); + if (!muxc) { + dev_err(&client->dev, "i2c_mux_alloc failed.\n"); + return -ENOMEM; + } + data = i2c_mux_priv(muxc); + i2c_set_clientdata(client, muxc); + data->client = client; +#endif + + dev = &client->dev; + if (dev == NULL) { + dev_err(&client->dev, "dev is NULL.\n"); + ret = -ENODEV; + goto exit_free; + } + + if (dev->of_node == NULL) { + if (client->dev.platform_data == NULL) { + dev_err(&client->dev, "Failed to get 954x platform data config.\n"); + ret = -EINVAL; + goto exit_free; + } + fpga_pca954x_device = client->dev.platform_data; + data->fpga_9548_flag = fpga_pca954x_device->fpga_9548_flag; + data->fpga_9548_reset_flag = fpga_pca954x_device->fpga_9548_reset_flag; + data->pca9548_base_nr = fpga_pca954x_device->pca9548_base_nr; + if (data->pca9548_base_nr == 0) { + + dynamic_nr = 1; + } else { + dynamic_nr = 0; + FPGA_PCA954X_VERBOSE("pca9548_base_nr:%u.\n", data->pca9548_base_nr); + } + } else { + data->type = id->driver_data; + /* BUS ID */ + ret = of_property_read_u32(dev->of_node, "fpga_9548_flag", &data->fpga_9548_flag); + ret += of_property_read_u32(dev->of_node, "fpga_9548_reset_flag", &data->fpga_9548_reset_flag); + if (ret != 0) { + dev_err(&client->dev, "Failed to get 954x dts config, ret:%d.\n", ret); + ret = -EINVAL; + goto exit_free; + } + if (of_property_read_u32(dev->of_node, "pca9548_base_nr", &data->pca9548_base_nr)) { + + dynamic_nr = 1; + FPGA_PCA954X_VERBOSE("pca9548_base_nr not found, use dynamic adap number"); + } else { + dynamic_nr = 0; + FPGA_PCA954X_VERBOSE("pca9548_base_nr:%u.\n", data->pca9548_base_nr); + } + } + + if (data->fpga_9548_flag != FPGA_EXTERNAL_PCA9548 && data->fpga_9548_flag != FPGA_INTERNAL_PCA9548) { + dev_err(&client->dev, "Error: fpga 954x flag config error, value:0x%x.\n", data->fpga_9548_flag); + ret = -EINVAL; + goto exit_free; + } + + data->type = id->driver_data; + data->last_chan = 0; /* force the first selection */ + + /* Now create an adapter for each channel */ + for (num = 0; num < chips[data->type].nchans; num++) { + if (dynamic_nr == 1) { + force = 0; /* dynamic adap number */ + } else { + force = data->pca9548_base_nr + num; + } + class = 0; /* no class by default */ +#if LINUX_VERSION_CODE <= KERNEL_VERSION(4,6,7) + data->virt_adaps[num] = + i2c_add_mux_adapter(adap, &client->dev, client, + force, num, class, pca954x_select_chan, pca954x_deselect_mux); + + if (data->virt_adaps[num] == NULL) { + ret = -ENODEV; + dev_err(&client->dev, "Failed to register multiplexed adapter %d as bus %d\n", + num, force); + goto virt_reg_failed; + } +#else + ret = i2c_mux_add_adapter(muxc, force, num, class); + if (ret) { + dev_err(&client->dev, "Failed to register multiplexed adapter %d as bus %d\n", + num, force); + goto virt_reg_failed; + } +#endif + } /* end for num = 0; num < chips[data->type].nchans... */ + + dev_info(&client->dev, "registered %d multiplexed busses for I2C %s %s\n", + num, chips[data->type].muxtype == pca954x_ismux ? "mux" : "switch", client->name); + + return 0; + +virt_reg_failed: +#if LINUX_VERSION_CODE <= KERNEL_VERSION(4,6,7) + for (num--; num >= 0; num--) + i2c_del_mux_adapter(data->virt_adaps[num]); +exit_free: + kfree(data); +#else +exit_free: + i2c_mux_del_adapters(muxc); +#endif +err: + return ret; +} + +static int fpga_i2c_pca954x_remove(struct i2c_client *client) +{ +#if LINUX_VERSION_CODE <= KERNEL_VERSION(4,6,7) + struct pca954x *data = i2c_get_clientdata(client); + const struct chip_desc *chip = &chips[data->type]; + int i; + + for (i = 0; i < chip->nchans; ++i) + if (data->virt_adaps[i]) { + i2c_del_mux_adapter(data->virt_adaps[i]); + data->virt_adaps[i] = NULL; + } + + kfree(data); +#else + struct i2c_mux_core *muxc = i2c_get_clientdata(client); + + i2c_mux_del_adapters(muxc); +#endif + + return 0; +} + +static struct i2c_driver fpga_i2c_pca954x_driver = { + .driver = { + .name = "wb_fpga_pca954x", + .owner = THIS_MODULE, + }, + .probe = fpga_i2c_pca954x_probe, + .remove = fpga_i2c_pca954x_remove, + .id_table = fpga_pca954x_id, +}; + +static int __init fpga_i2c_pca954x_init(void) +{ + int ret; + + ret = i2c_add_driver(&fpga_i2c_pca954x_driver); + return ret; +} + +static void __exit fpga_i2c_pca954x_exit(void) +{ + i2c_del_driver(&fpga_i2c_pca954x_driver); +} + +module_init(fpga_i2c_pca954x_init); +module_exit(fpga_i2c_pca954x_exit); +MODULE_DESCRIPTION("fpga pca954x driver"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("support"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_fpga_pcie.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_fpga_pcie.c new file mode 100644 index 000000000000..aedcc78dab90 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_fpga_pcie.c @@ -0,0 +1,164 @@ +/* + * wb_fpga_pcie.c + * ko to enable fpga pcie + */ +#include +#include +#include +#include +#include + +#define FPGA_MSI_IRQ_NUM (14) +#define FPGA_MSI_IRQ_BEGIN (0) +#define XILINX_FPGA_USE_MSI (0) +#define XILINX_FPGA_NUSE_MSI (1) + +int g_fpga_pcie_dev_debug = 0; +int g_fpga_pcie_dev_error = 0; +module_param(g_fpga_pcie_dev_debug, int, S_IRUGO | S_IWUSR); +module_param(g_fpga_pcie_dev_error, int, S_IRUGO | S_IWUSR); + +#define FPGA_PCIE_DEV_VERBOSE(fmt, args...) do { \ + if (g_fpga_pcie_dev_debug) { \ + printk(KERN_INFO "[FPGA_PCIE][VER][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +#define FPGA_PCIE_DEV_ERROR(fmt, args...) do { \ + if (g_fpga_pcie_dev_error) { \ + printk(KERN_ERR "[FPGA_PCIE][ERR][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +typedef struct wb_fpga_pcie_s { + struct pci_dev *pci_dev; + int driver_data; +} wb_fpga_pcie_t; + +static void fpga_pcie_recover(struct pci_dev *pdev, const struct pci_device_id *id) +{ + struct resource *mem_base; + u32 bar0_val; + int ret; + + mem_base = &pdev->resource[0]; + ret = pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &bar0_val); + if (ret) { + FPGA_PCIE_DEV_ERROR("pci_read_config_dword failed ret %d.\n", ret); + return; + } + FPGA_PCIE_DEV_VERBOSE("mem_base->start[0x%llx], bar0_val[0x%x], ret %d.\n", + mem_base->start, bar0_val, ret); + + if (bar0_val != mem_base->start) { + ret = pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, mem_base->start); + if (ret) { + FPGA_PCIE_DEV_ERROR("pci_write_config_dword mem_base->start[0x%llx], failed ret %d.\n", mem_base->start, ret); + return; + } + FPGA_PCIE_DEV_VERBOSE("pci_write_config_dword mem_base->start[0x%llx] success.\n", mem_base->start); + } else { + FPGA_PCIE_DEV_VERBOSE("mem_base->start[0x%llx], bar0_val[0x%x], do nothing.\n", + mem_base->start, bar0_val); + } +} + +static int fpga_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id) +{ + int err; + wb_fpga_pcie_t *wb_fpga_pcie; + + FPGA_PCIE_DEV_VERBOSE("Enter vendor 0x%x, subsystem_vendor 0x%x.\n", pdev->vendor, pdev->subsystem_vendor); + + wb_fpga_pcie = devm_kzalloc(&pdev->dev, sizeof(wb_fpga_pcie_t), GFP_KERNEL); + if (!wb_fpga_pcie) { + dev_err(&pdev->dev, "devm_kzalloc failed.\n"); + return -ENOMEM; + } + + fpga_pcie_recover(pdev, id); + + /* enable device: ask low-level code to enable I/O and memory */ + FPGA_PCIE_DEV_VERBOSE("start pci_enable_device!\n"); + err = pci_enable_device(pdev); + if (err) { + dev_err(&pdev->dev, "Failed to enable pci device, ret:%d.\n", err); + return err; + } + + FPGA_PCIE_DEV_VERBOSE("start pci_set_master!\n"); + pci_set_master(pdev); + + wb_fpga_pcie->driver_data = id->driver_data; + wb_fpga_pcie->pci_dev = pdev; + pci_set_drvdata(pdev, wb_fpga_pcie); + + if (wb_fpga_pcie->driver_data == XILINX_FPGA_USE_MSI) { + FPGA_PCIE_DEV_VERBOSE("start pci_enable_msi_range!\n"); +#if LINUX_VERSION_CODE < KERNEL_VERSION(4,19,152) + err = pci_enable_msi_range(pdev, FPGA_MSI_IRQ_BEGIN + 1, FPGA_MSI_IRQ_NUM); +#else + err = pci_alloc_irq_vectors_affinity(pdev, FPGA_MSI_IRQ_BEGIN + 1, + FPGA_MSI_IRQ_NUM, PCI_IRQ_MSI, NULL); +#endif + if (err != FPGA_MSI_IRQ_NUM) { + FPGA_PCIE_DEV_ERROR("pci_enable_msi_block err %d FPGA_MSI_IRQ_NUM %d.\n", err, + FPGA_MSI_IRQ_NUM); + dev_err(&pdev->dev, "Failed to enable pci msi, ret:%d.\n", err); + return -EINVAL; + } + } + + dev_info(&pdev->dev, "fpga pci device init success.\n"); + return 0; +} + +static void fpga_pcie_remove(struct pci_dev *pdev) +{ + wb_fpga_pcie_t *wb_fpga_pcie; + + FPGA_PCIE_DEV_VERBOSE("fpga_pcie_remove.\n"); + + wb_fpga_pcie = pci_get_drvdata(pdev); + if (wb_fpga_pcie->driver_data == XILINX_FPGA_USE_MSI) { + FPGA_PCIE_DEV_VERBOSE("start pci_disable_msi!\n"); + pci_disable_msi(pdev); + } + + pci_disable_device(pdev); + return; +} + +static const struct pci_device_id fpga_pci_ids[] = { + { PCI_DEVICE(0x10ee, 0x7022), .driver_data = XILINX_FPGA_USE_MSI}, + { PCI_DEVICE(0x10ee, 0x7011), .driver_data = XILINX_FPGA_NUSE_MSI}, + {0} +}; +MODULE_DEVICE_TABLE(pci, fpga_pci_ids); + +static struct pci_driver wb_fpga_pcie_driver = { + .name = "wb_fpga_pcie", + .id_table = fpga_pci_ids,/* only dynamic id's */ + .probe = fpga_pcie_probe, + .remove = fpga_pcie_remove, +}; + +static int __init wb_fpga_pcie_init(void) +{ + + FPGA_PCIE_DEV_VERBOSE("wb_fpga_pcie_init enter!\n"); + return pci_register_driver(&wb_fpga_pcie_driver); +} + +static void __exit wb_fpga_pcie_exit(void) +{ + FPGA_PCIE_DEV_VERBOSE("wb_fpga_pcie_exit enter!\n"); + pci_unregister_driver(&wb_fpga_pcie_driver); + return; +} + +module_init(wb_fpga_pcie_init); +module_exit(wb_fpga_pcie_exit); +MODULE_DESCRIPTION("fpga pcie driver"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("support"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_gpio_d1500.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_gpio_d1500.c new file mode 100644 index 000000000000..7d5d5da87ea7 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_gpio_d1500.c @@ -0,0 +1,367 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2011, 2012 Cavium Inc. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define GPIO_NAME "wb_gpio_d1500" + +#define GPIO_BASE (0x500) +#define GP_IO_SEL (GPIO_BASE + 0x4) +#define GP_LVL (GPIO_BASE + 0xC) +#define GPI_NMI_EN (GPIO_BASE + 0x28) +#define GPI_NMI_STS (GPIO_BASE + 0x2a) +#define GPI_INV (GPIO_BASE + 0x2c) +#define GPIO_USE_SEL2 (GPIO_BASE + 0x30) +#define GP_IO_SEL2 (GPIO_BASE + 0x34) +#define GP_LVL2 (GPIO_BASE + 0x38) +#define GPI_NMI_EN_2 (GPIO_BASE + 0x3c) +#define GPI_NMI_STS_2 (GPIO_BASE + 0x3e) +#define GPIO_USE_SEL3 (GPIO_BASE + 0x40) +#define GP_IO_SEL3 (GPIO_BASE + 0x44) +#define GP_LVL3 (GPIO_BASE + 0x48) +#define GPI_NMI_EN_3 (GPIO_BASE + 0x50) +#define GPI_NMI_STS_3 (GPIO_BASE + 0x54) + +#define GPIO_BASE_ID (0) +#define BANKSIZE (32) +#define D1500_GPIO_PIN_NUM (96) +#define CELL_NUM (2) + +int g_gpio_d1500_debug = 0; +int g_gpio_d1500_error = 0; +module_param(g_gpio_d1500_debug, int, S_IRUGO | S_IWUSR); +module_param(g_gpio_d1500_error, int, S_IRUGO | S_IWUSR); + +#define GPIO_DEBUG_VERBOSE(fmt, args...) do { \ + if (g_gpio_d1500_debug) { \ + printk(KERN_ERR "[GPIO-D1500][VER][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +#define GPIO_DEBUG_ERROR(fmt, args...) do { \ + if (g_gpio_d1500_error) { \ + printk(KERN_ERR "[GPIO-D1500][ERR][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +static DEFINE_SPINLOCK(sio_lock); + +struct gpio_d1500_t { + struct gpio_chip chip; + u64 register_base; +}; + +static int wb_gpio_get(struct gpio_chip *gc, unsigned gpio_num) +{ + u32 data = 0; + unsigned int bank, offset; + unsigned long flags; + + bank = gpio_num / BANKSIZE; + offset = gpio_num % BANKSIZE; + + spin_lock_irqsave(&sio_lock, flags); + if (bank == 0) { + data = inl(GP_LVL) & (1 << offset); + if (data) { + data = 1; + } + } else if (bank == 1) { + data = inl(GP_LVL2) & (1 << offset); + if (data) { + data = 1; + } + } else if (bank == 2) { + data = inl(GP_LVL3) & (1 << offset); + if (data) { + data = 1; + } + } + spin_unlock_irqrestore(&sio_lock, flags); + + return data; +} + +static int wb_gpio_direction_in(struct gpio_chip *gc, unsigned gpio_num) +{ + u32 data; + unsigned int bank, offset; + unsigned long flags; + + bank = gpio_num / BANKSIZE; + offset = gpio_num % BANKSIZE; + + spin_lock_irqsave(&sio_lock, flags); + if (bank == 0) { + data = inl(GP_IO_SEL); + data = data | (1 << offset); + outl(data, GP_IO_SEL); + } else if (bank == 1) { + data = inl(GP_IO_SEL2); + data = data | (1 << offset); + outl(data, GP_IO_SEL2); + } else if (bank == 2) { + data = inl(GP_IO_SEL3); + data = data | (1 << offset); + outl(data, GP_IO_SEL3); + } + spin_unlock_irqrestore(&sio_lock, flags); + + return 0; +} + +static void wb_gpio_set(struct gpio_chip *gc, + unsigned gpio_num, int val) +{ + u32 data; + unsigned int bank, offset; + unsigned long flags; + + bank = gpio_num / BANKSIZE; + offset = gpio_num % BANKSIZE; + + spin_lock_irqsave(&sio_lock, flags); + if (bank == 0) { + data = inl(GP_LVL); + if (val) { + data = data | (1 << offset); + } else { + data = data & ~(1 << offset); + } + outl(data, GP_LVL); + } else if (bank == 1) { + data = inl(GP_LVL2); + if (val) { + data = data | (1 << offset); + } else { + data = data & ~(1 << offset); + } + outl(data, GP_LVL2); + } else if (bank == 2) { + data = inl(GP_LVL3); + if (val) { + data = data | (1 << offset); + } else { + data = data & ~(1 << offset); + } + outl(data, GP_LVL3); + } + spin_unlock_irqrestore(&sio_lock, flags); + + return; +} + +static int wb_gpio_direction_out(struct gpio_chip *gc, + unsigned gpio_num, int val) +{ + u32 data; + unsigned int bank, offset; + unsigned long flags; + + bank = gpio_num / BANKSIZE; + offset = gpio_num % BANKSIZE; + + spin_lock_irqsave(&sio_lock, flags); + if (bank == 0) { + data = inl(GP_IO_SEL); + data = data & ~(1 << offset); + outl(data, GP_IO_SEL); + + data = inl(GP_LVL); + if (val) { + data = data | (1 << offset); + } else { + data = data & ~(1 << offset); + } + outl(data, GP_LVL); + } else if (bank == 1) { + data = inl(GP_IO_SEL2); + data = data & ~(1 << offset); + outl(data, GP_IO_SEL2); + + data = inl(GP_LVL2); + if (val) { + data = data | (1 << offset); + } else { + data = data & ~(1 << offset); + } + outl(data, GP_LVL2); + } else if (bank == 2) { + data = inl(GP_IO_SEL3); + data = data & ~(1 << offset); + outl(data, GP_IO_SEL3); + + data = inl(GP_LVL3); + if (val) { + data = data | (1 << offset); + } else { + data = data & ~(1 << offset); + } + outl(data, GP_LVL3); + } + spin_unlock_irqrestore(&sio_lock, flags); + + return 0; +} + +#ifdef CONFIG_OF +static int wb_gpio_of_xlate(struct gpio_chip *chip, + const struct of_phandle_args *gpio_desc, + u32 *flags) +{ + if (chip->of_gpio_n_cells < 2) { + return -EINVAL; + } + + if (flags) { + *flags = gpio_desc->args[1]; + } + + return gpio_desc->args[0]; +} +#endif + +static int wb_gpio_request(struct gpio_chip *chip, unsigned int offset) +{ + u32 data; + unsigned int bank, tmp_offset; + unsigned long flags; + + bank = offset / BANKSIZE; + tmp_offset = offset % BANKSIZE; + + spin_lock_irqsave(&sio_lock, flags); + if (bank == 0) { + data = inl(GPIO_BASE); + data = data | (1 << tmp_offset); + outl(data, GPIO_BASE); + } else if (bank == 1) { + data = inl(GPIO_USE_SEL2); + data = data | (1 << tmp_offset); + outl(data, GPIO_USE_SEL2); + } else if (bank == 2) { + data = inl(GPIO_USE_SEL3); + data = data | (1 << tmp_offset); + outl(data, GPIO_USE_SEL3); + } + spin_unlock_irqrestore(&sio_lock, flags); + + return 0; +} + +#if 0 +static void wb_gpio_free(struct gpio_chip *chip, unsigned int offset) +{ + u32 data; + unsigned int bank, tmp_offset; + unsigned long flags; + + bank = offset / BANKSIZE; + tmp_offset = offset % BANKSIZE; + + spin_lock_irqsave(&sio_lock, flags); + if (bank == 0) { + data = inl(GPIO_BASE); + data = data & ~(1 << tmp_offset); + outl(data, GPIO_BASE); + } else if (bank == 1) { + data = inl(GPIO_USE_SEL2); + data = data & ~(1 << tmp_offset); + outl(data, GPIO_USE_SEL2); + } else if (bank == 2) { + data = inl(GPIO_USE_SEL3); + data = data & ~(1 << tmp_offset); + outl(data, GPIO_USE_SEL3); + } + + spin_unlock_irqrestore(&sio_lock, flags); + + return; +} +#endif + +static struct gpio_chip wb_gpio_chip = { + .label = GPIO_NAME, + .owner = THIS_MODULE, + .base = GPIO_BASE_ID, + .get = wb_gpio_get, + .direction_input = wb_gpio_direction_in, + .set = wb_gpio_set, + .direction_output = wb_gpio_direction_out, +#ifdef CONFIG_OF + .of_xlate = wb_gpio_of_xlate, +#endif + .request = wb_gpio_request, + .ngpio = D1500_GPIO_PIN_NUM, +#ifdef CONFIG_OF + .of_gpio_n_cells = CELL_NUM, +#endif + .can_sleep = false, +}; + +static int wb_gpio_probe(struct platform_device *pdev) +{ + struct gpio_d1500_t *gpio; + int err; + + gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); + if (!gpio) { + dev_err(&pdev->dev, "gpio kzalloc failed\n"); + return -ENOMEM; + } + + wb_gpio_chip.parent = &pdev->dev; + gpio->register_base = GPIO_BASE; + gpio->chip = wb_gpio_chip; + pdev->dev.platform_data = &wb_gpio_chip; + err = devm_gpiochip_add_data(&pdev->dev, &wb_gpio_chip, gpio); + if (err) { + dev_err(&pdev->dev, "gpiochip add failed\n"); + return err; + } + + dev_info(&pdev->dev, "register %llu gpio success.\n", gpio->register_base); + + return 0; +} + +static int wb_gpio_remove(struct platform_device *pdev) +{ + dev_info(&pdev->dev, "unregister d1500 gpio success\n"); + return 0; +} + +static const struct of_device_id gpio_d1500_match[] = { + { + .compatible = "wb_gpio_d1500", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, gpio_d1500_match); + +static struct platform_driver wb_gpio_driver = { + .driver = { + .name = GPIO_NAME, + .of_match_table = gpio_d1500_match, + }, + .probe = wb_gpio_probe, + .remove = wb_gpio_remove, +}; + +module_platform_driver(wb_gpio_driver); + +MODULE_DESCRIPTION("d1500 gpio driver"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("support"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_gpio_device.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_gpio_device.c new file mode 100644 index 000000000000..75f883b5909d --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_gpio_device.c @@ -0,0 +1,54 @@ +#include +#include +#include +#include +#include + +static int g_wb_gpio_device_debug = 0; +static int g_wb_gpio_device_error = 0; + +module_param(g_wb_gpio_device_debug, int, S_IRUGO | S_IWUSR); +module_param(g_wb_gpio_device_error, int, S_IRUGO | S_IWUSR); + +#define WB_GPIO_DEVICE_VERBOSE(fmt, args...) do { \ + if (g_wb_gpio_device_debug) { \ + printk(KERN_INFO "[WB_GPIO_DEVICE][VER][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +#define WB_GPIO_DEVICE_ERROR(fmt, args...) do { \ + if (g_wb_gpio_device_error) { \ + printk(KERN_ERR "[WB_GPIO_DEVICE][ERR][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +static void wb_gpio_device_release(struct device *dev) +{ + return; +} + +static struct platform_device wb_gpio_d1500_device = { + .name = "wb_gpio_d1500", + .id = -1, + .dev = { + .release = wb_gpio_device_release, + }, +}; + +static int __init wb_gpio_device_init(void) +{ + WB_GPIO_DEVICE_VERBOSE("wb_gpio_device_init enter!\n"); + return platform_device_register(&wb_gpio_d1500_device); +} + +static void __exit wb_gpio_device_exit(void) +{ + WB_GPIO_DEVICE_VERBOSE("wb_gpio_device_exit enter!\n"); + return platform_device_unregister(&wb_gpio_d1500_device); +} + +module_init(wb_gpio_device_init); +module_exit(wb_gpio_device_exit); +MODULE_DESCRIPTION("GPIO Devices"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("support"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_i2c_dev.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_i2c_dev.c new file mode 100644 index 000000000000..14f85f33f572 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_i2c_dev.c @@ -0,0 +1,774 @@ +/* + * wb_io_dev.c + * ko to read/write i2c client through /dev/XXX device + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "wb_i2c_dev.h" + +#define MAX_I2C_DEV_NUM (256) +#define FPGA_MAX_LEN (256) +#define MAX_NAME_SIZE (20) +#define MAX_BUS_WIDTH (16) +#define TRANSFER_WRITE_BUFF (FPGA_MAX_LEN + MAX_BUS_WIDTH) + +#define WIDTH_1Byte (1) +#define WIDTH_2Byte (2) +#define WIDTH_4Byte (4) + +static int g_i2c_dev_debug = 0; +static int g_i2c_dev_error = 0; + +module_param(g_i2c_dev_debug, int, S_IRUGO | S_IWUSR); +module_param(g_i2c_dev_error, int, S_IRUGO | S_IWUSR); + +#define I2C_DEV_DEBUG_DMESG(fmt, args...) do { \ + if (g_i2c_dev_debug) { \ + printk(KERN_ERR "[I2C_DEV][DEBUG][func:%s line:%d]\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +#define I2C_DEV_DEBUG_ERROR(fmt, args...) do { \ + if (g_i2c_dev_error) { \ + printk(KERN_ERR "[I2C_DEV][ERR][func:%s line:%d]\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +static struct i2c_dev_info* i2c_dev_arry[MAX_I2C_DEV_NUM]; + +struct i2c_dev_info { + const char *name; + uint32_t data_bus_width; + uint32_t addr_bus_width; + uint32_t per_rd_len; + uint32_t per_wr_len; + uint32_t i2c_len; + struct miscdevice misc; + struct i2c_client *client; +}; + +static int transfer_read(struct i2c_client *client, u8 *buf, loff_t regaddr, size_t count) +{ + struct i2c_adapter *adap; + int i; + u8 offset_buf[MAX_BUS_WIDTH]; + struct i2c_msg msgs[2]; + int msgs_num, ret; + struct i2c_dev_info *i2c_dev; + + if (!client) { + I2C_DEV_DEBUG_ERROR("can't get read client\n"); + return -ENODEV; + } + + adap = client->adapter; + if (!adap) { + I2C_DEV_DEBUG_ERROR("can't get read adap\n"); + return -ENODEV; + } + + i2c_dev = i2c_get_clientdata(client); + if (!i2c_dev) { + I2C_DEV_DEBUG_ERROR("can't get read i2c_dev\n"); + return -ENODEV; + } + + i = 0; + + mem_clear(offset_buf, sizeof(offset_buf)); + + switch (i2c_dev->addr_bus_width) { + case WIDTH_4Byte: + offset_buf[i++] = (regaddr >> 24) & 0xFF; + offset_buf[i++] = (regaddr >> 16) & 0xFF; + offset_buf[i++] = (regaddr >> 8) & 0xFF; + offset_buf[i++] = regaddr & 0xFF; + break; + case WIDTH_2Byte: + offset_buf[i++] = (regaddr >> 8) & 0xFF; + offset_buf[i++] = regaddr & 0xFF; + break; + case WIDTH_1Byte: + offset_buf[i++] = regaddr & 0xFF; + break; + default: + I2C_DEV_DEBUG_ERROR("Only support 1,2,4 Byte Address Width,but set width = %u\n", + i2c_dev->addr_bus_width); + return -EINVAL; + } + + if (adap->algo->master_xfer) { + mem_clear(msgs, sizeof(msgs)); + msgs[0].addr = client->addr; + msgs[0].flags = 0; + msgs[0].len = i2c_dev->addr_bus_width; + msgs[0].buf = offset_buf; + + msgs[1].addr = client->addr; + msgs[1].flags = I2C_M_RD; + msgs[1].len = count; + msgs[1].buf = buf; + + msgs_num = 2; + ret = i2c_transfer(client->adapter, msgs, msgs_num); + if (ret != msgs_num) { + I2C_DEV_DEBUG_ERROR("i2c_transfer read error\n"); + return -EINVAL; + } + } else { + I2C_DEV_DEBUG_ERROR("don't find read master_xfer\n"); + return -EINVAL; + + } + return 0; +} + +static int transfer_write(struct i2c_client *client, u8 *buf, loff_t regaddr, size_t count) +{ + struct i2c_adapter *adap; + int i; + u8 offset_buf[TRANSFER_WRITE_BUFF]; + struct i2c_msg msgs[1]; + int msgs_num, ret; + struct i2c_dev_info *i2c_dev; + + if (!client) { + I2C_DEV_DEBUG_ERROR("can't get write client\n"); + return -ENODEV; + } + + adap = client->adapter; + if (!adap) { + I2C_DEV_DEBUG_ERROR("can't get write adap\n"); + return -ENODEV; + } + + i2c_dev = i2c_get_clientdata(client); + if (!i2c_dev) { + I2C_DEV_DEBUG_ERROR("can't get read i2c_dev\n"); + return -ENODEV; + } + + i = 0; + + mem_clear(offset_buf, sizeof(offset_buf)); + + switch (i2c_dev->addr_bus_width) { + case WIDTH_4Byte: + offset_buf[i++] = (regaddr >> 24) & 0xFF; + offset_buf[i++] = (regaddr >> 16) & 0xFF; + offset_buf[i++] = (regaddr >> 8) & 0xFF; + offset_buf[i++] = regaddr & 0xFF; + break; + case WIDTH_2Byte: + offset_buf[i++] = (regaddr >> 8) & 0xFF; + offset_buf[i++] = regaddr & 0xFF; + break; + case WIDTH_1Byte: + offset_buf[i++] = regaddr & 0xFF; + break; + default: + I2C_DEV_DEBUG_ERROR("Only support 1,2,4 Byte Address Width,but set width = %u\n", + i2c_dev->addr_bus_width); + return -EINVAL; + } + + memcpy(offset_buf + i2c_dev->addr_bus_width, buf, count); + + if (adap->algo->master_xfer) { + mem_clear(msgs, sizeof(msgs)); + + msgs[0].addr = client->addr; + msgs[0].flags = 0; + msgs[0].len = i2c_dev->addr_bus_width + count; + msgs[0].buf = offset_buf; + + msgs_num = 1; + ret = i2c_transfer(adap, msgs, msgs_num); + if (ret != msgs_num) { + I2C_DEV_DEBUG_ERROR("i2c_transfer write error\n"); + return -EINVAL; + } + } else { + I2C_DEV_DEBUG_ERROR("don't find write master_xfer\n"); + return -EINVAL; + } + + return 0; +} + +static long i2c_dev_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + return 0; +} + +static int i2c_dev_open(struct inode *inode, struct file *file) +{ + unsigned int minor = iminor(inode); + struct i2c_dev_info *i2c_dev; + + i2c_dev = i2c_dev_arry[minor]; + if (i2c_dev == NULL) { + return -ENODEV; + } + + file->private_data = i2c_dev; + + return 0; +} + +static int i2c_dev_release(struct inode *inode, struct file *file) +{ + file->private_data = NULL; + + return 0; +} + +static int device_read(struct i2c_dev_info *i2c_dev, uint32_t offset, uint8_t *buf, size_t count) +{ + int i, j, ret; + u8 tmp_offset; + u8 val[FPGA_MAX_LEN]; + u32 width, rd_len, per_len, tmp; + u32 max_per_len; + + if (offset > i2c_dev->i2c_len) { + I2C_DEV_DEBUG_DMESG("offset: 0x%x, i2c len: 0x%x, count: %lu, EOF.\n", + offset, i2c_dev->i2c_len, count); + return 0; + } + + if (count > (i2c_dev->i2c_len - offset)) { + I2C_DEV_DEBUG_DMESG("read count out of range. input len:%lu, read len:%u.\n", + count, i2c_dev->i2c_len - offset); + count = i2c_dev->i2c_len - offset; + } + + if (count == 0) { + I2C_DEV_DEBUG_DMESG("offset: 0x%x, i2c len: 0x%x, read len: %lu, EOF.\n", + offset, i2c_dev->i2c_len, count); + return 0; + } + + width = i2c_dev->data_bus_width; + switch (width) { + case WIDTH_4Byte: + tmp_offset = offset & 0x3; + if (tmp_offset) { + I2C_DEV_DEBUG_ERROR("data bus width:%u, offset:%u, read size %lu invalid.\n", + width, offset, count); + return -EINVAL; + } + break; + case WIDTH_2Byte: + tmp_offset = offset & 0x1; + if (tmp_offset) { + I2C_DEV_DEBUG_ERROR("data bus width:%u, offset:%u, read size %lu invalid.\n", + width, offset, count); + return -EINVAL; + } + break; + case WIDTH_1Byte: + break; + default: + I2C_DEV_DEBUG_ERROR("Only support 1,2,4 Byte Data Width,but set width = %u\n", width); + return -EINVAL; + } + + max_per_len = i2c_dev->per_rd_len; + tmp = (width - 1) & count; + rd_len = (tmp == 0) ? count : count + width - tmp; + per_len = (rd_len > max_per_len) ? (max_per_len) : (rd_len); + + mem_clear(val, sizeof(val)); + for (i = 0; i < rd_len; i += per_len) { + ret = transfer_read(i2c_dev->client, val + i, offset + i, per_len); + if (ret < 0) { + I2C_DEV_DEBUG_ERROR("read error.read offset = %u\n", (offset + i)); + return -EFAULT; + } + } + + if (width == WIDTH_1Byte) { + memcpy(buf, val, count); + } else { + for (i = 0; i < count; i += width) { + for (j = 0; (j < width) && (i + j < count); j++) { + buf[i + j] = val[i + width - j - 1]; + } + } + } + + return count; +} + +static int device_write(struct i2c_dev_info *i2c_dev, uint32_t offset, uint8_t *buf, size_t count) +{ + int i, j, ret; + u8 tmp_offset; + u32 width; + u8 val[FPGA_MAX_LEN]; + u32 wr_len, per_len, tmp; + u32 max_per_len; + + if (offset > i2c_dev->i2c_len) { + I2C_DEV_DEBUG_DMESG("offset: 0x%x, i2c len: 0x%x, count: %lu, EOF.\n", + offset, i2c_dev->i2c_len, count); + return 0; + } + + if (count > (i2c_dev->i2c_len - offset)) { + I2C_DEV_DEBUG_DMESG("read count out of range. input len:%lu, read len:%u.\n", + count, i2c_dev->i2c_len - offset); + count = i2c_dev->i2c_len - offset; + } + + if (count == 0) { + I2C_DEV_DEBUG_DMESG("offset: 0x%x, i2c len: 0x%x, read len: %lu, EOF.\n", + offset, i2c_dev->i2c_len, count); + return 0; + } + + width = i2c_dev->data_bus_width; + switch (width) { + case WIDTH_4Byte: + tmp_offset = offset & 0x3; + if (tmp_offset) { + I2C_DEV_DEBUG_ERROR("data bus width:%u, offset:%u, read size %lu invalid.\n", + width, offset, count); + return -EINVAL; + } + break; + case WIDTH_2Byte: + tmp_offset = offset & 0x1; + if (tmp_offset) { + I2C_DEV_DEBUG_ERROR("data bus width:%u, offset:%u, read size %lu invalid.\n", + width, offset, count); + return -EINVAL; + } + break; + case WIDTH_1Byte: + break; + default: + I2C_DEV_DEBUG_ERROR("Only support 1,2,4 Byte Data Width,but set width = %u\n", width); + return -EINVAL; + } + + mem_clear(val, sizeof(val)); + + if (width == WIDTH_1Byte) { + memcpy(val, buf, count); + } else { + for (i = 0; i < count; i += width) { + for (j = 0; (j < width) && (i + j < count); j++) { + val[i + width - j - 1] = buf[i + j]; + } + } + } + + max_per_len = i2c_dev->per_wr_len; + tmp = (width - 1) & count; + wr_len = (tmp == 0) ? count : count + width - tmp; + per_len = (wr_len > max_per_len) ? (max_per_len) : (wr_len); + + for (i = 0; i < wr_len; i += per_len) { + ret = transfer_write(i2c_dev->client, val + i, offset + i, per_len); + if (ret < 0) { + I2C_DEV_DEBUG_ERROR("write error.offset = %u\n", (offset + i)); + return -EFAULT; + } + } + return count; +} + +static ssize_t i2c_dev_read(struct file *file, char __user *buf, size_t count, loff_t *offset) +{ + u8 val[FPGA_MAX_LEN]; + int ret, read_len; + struct i2c_dev_info *i2c_dev; + + i2c_dev = file->private_data; + if (i2c_dev == NULL) { + I2C_DEV_DEBUG_ERROR("can't get read private_data.n"); + return -EINVAL; + } + + if (count == 0) { + I2C_DEV_DEBUG_ERROR("Invalid params, read count is 0.n"); + return -EINVAL; + } + + if (count > sizeof(val)) { + I2C_DEV_DEBUG_DMESG("read conut %lu exceed max %lu.\n", count, sizeof(val)); + count = sizeof(val); + } + + mem_clear(val, sizeof(val)); + read_len = device_read(i2c_dev, (uint32_t)*offset, val, count); + if (read_len < 0) { + I2C_DEV_DEBUG_ERROR("i2c dev read failed, dev name:%s, offset:0x%x, len:%lu.\n", + i2c_dev->name, (uint32_t)*offset, count); + return read_len; + } + + if (access_ok(buf, read_len)) { + I2C_DEV_DEBUG_DMESG("user space read, buf: %p, offset: %lld, read conut %lu.\n", + buf, *offset, count); + if (copy_to_user(buf, val, read_len)) { + I2C_DEV_DEBUG_ERROR("copy_to_user failed.\n"); + return -EFAULT; + } + } else { + I2C_DEV_DEBUG_DMESG("kernel space read, buf: %p, offset: %lld, read conut %lu.\n", + buf, *offset, count); + memcpy(buf, val, read_len); + } + + *offset += read_len; + ret = read_len; + return ret; +} + +static ssize_t i2c_dev_read_iter(struct kiocb *iocb, struct iov_iter *to) +{ + int ret; + + I2C_DEV_DEBUG_DMESG("i2c_dev_read_iter, file: %p, count: %lu, offset: %lld\n", + iocb->ki_filp, to->count, iocb->ki_pos); + ret = i2c_dev_read(iocb->ki_filp, to->kvec->iov_base, to->count, &iocb->ki_pos); + return ret; +} + +static ssize_t i2c_dev_write(struct file *file, const char __user *buf, size_t count, loff_t *offset) +{ + u8 val[FPGA_MAX_LEN]; + int write_len; + struct i2c_dev_info *i2c_dev; + + i2c_dev = file->private_data; + if (i2c_dev == NULL) { + I2C_DEV_DEBUG_ERROR("get write private_data error.\n"); + return -EINVAL; + } + + if (count == 0) { + I2C_DEV_DEBUG_ERROR("Invalid params, write count is 0.\n"); + return -EINVAL; + } + + if (count > sizeof(val)) { + I2C_DEV_DEBUG_DMESG("write conut %lu exceed max %lu.\n", count, sizeof(val)); + count = sizeof(val); + } + + mem_clear(val, sizeof(val)); + if (access_ok(buf, count)) { + I2C_DEV_DEBUG_DMESG("user space write, buf: %p, offset: %lld, write conut %lu.\n", + buf, *offset, count); + if (copy_from_user(val, buf, count)) { + I2C_DEV_DEBUG_ERROR("copy_from_user failed.\n"); + return -EFAULT; + } + } else { + I2C_DEV_DEBUG_DMESG("kernel space write, buf: %p, offset: %lld, write conut %lu.\n", + buf, *offset, count); + memcpy(val, buf, count); + } + + write_len = device_write(i2c_dev, (uint32_t)*offset, val, count); + if (write_len < 0) { + I2C_DEV_DEBUG_ERROR("i2c dev write failed, dev name:%s, offset:0x%llx, len:%lu.\n", + i2c_dev->name, *offset, count); + return write_len; + } + + *offset += write_len; + return write_len; +} + +static ssize_t i2c_dev_write_iter(struct kiocb *iocb, struct iov_iter *from) +{ + int ret; + + I2C_DEV_DEBUG_DMESG("i2c_dev_write_iter, file: %p, count: %lu, offset: %lld\n", + iocb->ki_filp, from->count, iocb->ki_pos); + ret = i2c_dev_write(iocb->ki_filp, from->kvec->iov_base, from->count, &iocb->ki_pos); + return ret; +} + +static loff_t i2c_dev_llseek(struct file *file, loff_t offset, int origin) +{ + loff_t ret = 0; + struct i2c_dev_info *i2c_dev; + + i2c_dev = file->private_data; + if (i2c_dev == NULL) { + I2C_DEV_DEBUG_ERROR("i2c_dev is NULL, llseek failed.\n"); + return -EINVAL; + } + + switch (origin) { + case SEEK_SET: + if (offset < 0) { + I2C_DEV_DEBUG_ERROR("SEEK_SET, offset:%lld, invalid.\n", offset); + ret = -EINVAL; + break; + } + if (offset > i2c_dev->i2c_len) { + I2C_DEV_DEBUG_ERROR("SEEK_SET out of range, offset:%lld, i2c_len:0x%x.\n", + offset, i2c_dev->i2c_len); + ret = - EINVAL; + break; + } + file->f_pos = offset; + ret = file->f_pos; + break; + case SEEK_CUR: + if (((file->f_pos + offset) > i2c_dev->i2c_len) || ((file->f_pos + offset) < 0)) { + I2C_DEV_DEBUG_ERROR("SEEK_CUR out of range, f_ops:%lld, offset:%lld, i2c_len:0x%x.\n", + file->f_pos, offset, i2c_dev->i2c_len); + ret = - EINVAL; + break; + } + file->f_pos += offset; + ret = file->f_pos; + break; + default: + I2C_DEV_DEBUG_ERROR("unsupport llseek type:%d.\n", origin); + ret = -EINVAL; + break; + } + return ret; +} + +static const struct file_operations i2c_dev_fops = { + .owner = THIS_MODULE, + .llseek = i2c_dev_llseek, + .read_iter = i2c_dev_read_iter, + .write_iter = i2c_dev_write_iter, + .unlocked_ioctl = i2c_dev_ioctl, + .open = i2c_dev_open, + .release = i2c_dev_release, +}; + +static struct i2c_dev_info * dev_match(const char *path) +{ + struct i2c_dev_info * i2c_dev; + char dev_name[MAX_NAME_SIZE]; + int i; + for (i = 0; i < MAX_I2C_DEV_NUM; i++) { + if (i2c_dev_arry[ i ] == NULL) { + continue; + } + i2c_dev = i2c_dev_arry[ i ]; + snprintf(dev_name, MAX_NAME_SIZE,"/dev/%s", i2c_dev->name); + if (!strcmp(path, dev_name)) { + I2C_DEV_DEBUG_DMESG("get dev_name = %s, minor = %d\n", dev_name, i); + return i2c_dev; + } + } + + return NULL; +} + +int i2c_device_func_read(const char *path, uint32_t offset, uint8_t *buf, size_t count) +{ + struct i2c_dev_info *i2c_dev = NULL; + int ret; + + if(path == NULL){ + I2C_DEV_DEBUG_ERROR("path NULL"); + return -EINVAL; + } + + if(buf == NULL){ + I2C_DEV_DEBUG_ERROR("buf NULL"); + return -EINVAL; + } + + if (count > FPGA_MAX_LEN) { + I2C_DEV_DEBUG_ERROR("read conut %lu, beyond max:%d.\n", count, FPGA_MAX_LEN); + return -EINVAL; + } + + i2c_dev = dev_match(path); + if (i2c_dev == NULL) { + I2C_DEV_DEBUG_ERROR("i2c_dev match failed. dev path = %s", path); + return -EINVAL; + } + + ret = device_read(i2c_dev, offset, buf, count); + if (ret < 0) { + I2C_DEV_DEBUG_ERROR("fpga i2c dev read failed, dev name:%s, offset:0x%x, len:%lu.\n", + i2c_dev->name, offset, count); + return -EINVAL; + } + + return count; +} +EXPORT_SYMBOL(i2c_device_func_read); + +int i2c_device_func_write(const char *path, uint32_t offset, uint8_t *buf, size_t count) +{ + struct i2c_dev_info *i2c_dev = NULL; + int ret; + + if(path == NULL){ + I2C_DEV_DEBUG_ERROR("path NULL"); + return -EINVAL; + } + + if(buf == NULL){ + I2C_DEV_DEBUG_ERROR("buf NULL"); + return -EINVAL; + } + + if (count > FPGA_MAX_LEN) { + I2C_DEV_DEBUG_ERROR("write conut %lu, beyond max:%d.\n", count, FPGA_MAX_LEN); + return -EINVAL; + } + + i2c_dev = dev_match(path); + if (i2c_dev == NULL) { + I2C_DEV_DEBUG_ERROR("i2c_dev match failed. dev path = %s", path); + return -EINVAL; + } + + ret = device_write (i2c_dev, offset, buf, count); + if (ret < 0) { + I2C_DEV_DEBUG_ERROR("i2c dev write failed, dev name:%s, offset:0x%x, len:%lu.\n", + i2c_dev->name, offset, count); + return -EINVAL; + } + + return count; +} +EXPORT_SYMBOL(i2c_device_func_write); + +static int i2c_dev_probe(struct i2c_client *client, const struct i2c_device_id *id) +{ + int ret = 0; + struct i2c_dev_info *i2c_dev; + struct miscdevice *misc; + i2c_dev_device_t *i2c_dev_device; + + i2c_dev = devm_kzalloc(&client->dev, sizeof(struct i2c_dev_info), GFP_KERNEL); + if (!i2c_dev) { + dev_err(&client->dev, "devm_kzalloc error. \n"); + return -ENOMEM; + } + + i2c_set_clientdata(client, i2c_dev); + i2c_dev->client = client; + + if (client->dev.of_node) { + + ret += of_property_read_string(client->dev.of_node, "i2c_name", &i2c_dev->name); + ret += of_property_read_u32(client->dev.of_node, "data_bus_width", &i2c_dev->data_bus_width); + ret += of_property_read_u32(client->dev.of_node, "addr_bus_width", &i2c_dev->addr_bus_width); + ret += of_property_read_u32(client->dev.of_node, "per_rd_len", &i2c_dev->per_rd_len); + ret += of_property_read_u32(client->dev.of_node, "per_wr_len", &i2c_dev->per_wr_len); + ret += of_property_read_u32(client->dev.of_node, "i2c_len", &i2c_dev->i2c_len); + if (ret != 0) { + dev_err(&client->dev, "dts config error.ret:%d.\n", ret); + return -ENXIO; + } + } else { + if (client->dev.platform_data == NULL) { + dev_err(&client->dev, "Failed to get platform data config.\n"); + return -ENXIO; + } + i2c_dev_device = client->dev.platform_data; + i2c_dev->name = i2c_dev_device->i2c_name; + i2c_dev->data_bus_width = i2c_dev_device->data_bus_width; + i2c_dev->addr_bus_width = i2c_dev_device->addr_bus_width; + i2c_dev->per_rd_len = i2c_dev_device->per_rd_len; + i2c_dev->per_wr_len = i2c_dev_device->per_wr_len; + i2c_dev->i2c_len = i2c_dev_device->i2c_len; + } + + if ((i2c_dev->per_rd_len & (i2c_dev->data_bus_width - 1)) || + (i2c_dev->per_wr_len & (i2c_dev->data_bus_width - 1))) { + dev_err(&client->dev, "Invalid config per_rd_len %d per_wr_len %d data bus_width %d.\n", + i2c_dev->per_rd_len, i2c_dev->per_wr_len, i2c_dev->data_bus_width); + return -ENXIO; + } + + if ((i2c_dev->i2c_len == 0) || (i2c_dev->i2c_len & (i2c_dev->data_bus_width - 1))) { + dev_err(&client->dev, "Invalid config i2c_len %d, data bus_width %d.\n", + i2c_dev->i2c_len, i2c_dev->data_bus_width); + return -ENXIO; + } + + misc = &i2c_dev->misc; + misc->minor = MISC_DYNAMIC_MINOR; + misc->name = i2c_dev->name; + misc->fops = &i2c_dev_fops; + misc->mode = 0666; + if (misc_register(misc) != 0) { + dev_err(&client->dev, "register %s faild.\n", misc->name); + return -ENXIO; + } + + if (misc->minor >= MAX_I2C_DEV_NUM) { + dev_err(&client->dev, "minor number beyond the limit! is %d.\n", misc->minor); + misc_deregister(misc); + return -ENXIO; + } + i2c_dev_arry[misc->minor] = i2c_dev; + + dev_info(&client->dev, "register %u addr_bus_width %u data_bus_width 0x%x i2c_len device %s with %u per_rd_len %u per_wr_len success.\n", + i2c_dev->addr_bus_width, i2c_dev->data_bus_width, i2c_dev->i2c_len, i2c_dev->name, i2c_dev->per_rd_len, i2c_dev->per_wr_len); + + return 0; +} + +static int i2c_dev_remove(struct i2c_client *client) +{ + int i; + for (i = 0; i < MAX_I2C_DEV_NUM; i++) { + if (i2c_dev_arry[i] != NULL) { + misc_deregister(&i2c_dev_arry[i]->misc); + i2c_dev_arry[i] = NULL; + } + } + return 0; +} + +static const struct i2c_device_id i2c_dev_id[] = { + { "wb-i2c-dev", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, i2c_dev_id); + +static const struct of_device_id i2c_dev_of_match[] = { + { .compatible = "wb-i2c-dev" }, + { }, +}; +MODULE_DEVICE_TABLE(of, i2c_dev_of_match); + +static struct i2c_driver i2c_dev_driver = { + .driver = { + .name = "wb-i2c-dev", + .of_match_table = i2c_dev_of_match, + }, + .probe = i2c_dev_probe, + .remove = i2c_dev_remove, + .id_table = i2c_dev_id, +}; +module_i2c_driver(i2c_dev_driver); + +MODULE_DESCRIPTION("i2c dev driver"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("support"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_i2c_dev.h b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_i2c_dev.h new file mode 100644 index 000000000000..9cc95d88e804 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_i2c_dev.h @@ -0,0 +1,20 @@ +#ifndef __WB_I2C_DEV_H__ +#define __WB_I2C_DEV_H__ +#include + +#define mem_clear(data, size) memset((data), 0, (size)) +#define I2C_DEV_NAME_MAX_LEN (64) + +typedef struct i2c_dev_device_s { + struct i2c_client *client; + uint32_t i2c_bus; + uint32_t i2c_addr; + char i2c_name[I2C_DEV_NAME_MAX_LEN]; + uint32_t data_bus_width; + uint32_t addr_bus_width; + uint32_t per_rd_len; + uint32_t per_wr_len; + uint32_t i2c_len; +} i2c_dev_device_t; + +#endif diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_i2c_ocores.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_i2c_ocores.c new file mode 100644 index 000000000000..1f69d96bad0b --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_i2c_ocores.c @@ -0,0 +1,1143 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * i2c-ocores.c: I2C bus driver for OpenCores I2C controller + * (https://opencores.org/project/i2c/overview) + * + * Peter Korsgaard + * + * Support for the GRLIB port of the controller by + * Andreas Larsson + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "wb_i2c_ocores.h" + +#define OCORES_FLAG_POLL BIT(0) + +/* registers */ +#define OCI2C_PRELOW (0) +#define OCI2C_PREHIGH (1) +#define OCI2C_CONTROL (2) +#define OCI2C_DATA (3) +#define OCI2C_CMD (4) /* write only */ +#define OCI2C_STATUS (4) /* read only, same address as OCI2C_CMD */ + +#define OCI2C_CTRL_IEN (0x40) +#define OCI2C_CTRL_EN (0x80) + +#define OCI2C_CMD_START (0x91) +#define OCI2C_CMD_STOP (0x41) +#define OCI2C_CMD_READ (0x21) +#define OCI2C_CMD_WRITE (0x11) +#define OCI2C_CMD_READ_ACK (0x21) +#define OCI2C_CMD_READ_NACK (0x29) +#define OCI2C_CMD_IACK (0x01) + +#define OCI2C_STAT_IF (0x01) +#define OCI2C_STAT_TIP (0x02) +#define OCI2C_STAT_ARBLOST (0x20) +#define OCI2C_STAT_BUSY (0x40) +#define OCI2C_STAT_NACK (0x80) + +#define STATE_DONE (0) +#define STATE_START (1) +#define STATE_WRITE (2) +#define STATE_READ (3) +#define STATE_ERROR (4) + +#define TYPE_OCORES (0) +#define TYPE_GRLIB (1) + +#define OCORE_WAIT_SCH (40) +#define REG_IO_WIDTH_1 (1) +#define REG_IO_WIDTH_2 (2) +#define REG_IO_WIDTH_4 (4) + +#define SYMBOL_I2C_DEV_MODE (1) +#define FILE_MODE (2) +#define SYMBOL_PCIE_DEV_MODE (3) +#define SYMBOL_IO_DEV_MODE (4) + +typedef struct wb_pci_dev_s { + uint32_t domain; + uint32_t bus; + uint32_t slot; + uint32_t fn; +} wb_pci_dev_t; + +/* + * 'process_lock' exists because ocores_process() and ocores_process_timeout() + * can't run in parallel. + */ +struct ocores_i2c { + uint32_t base_addr; + uint32_t reg_shift; + uint32_t reg_io_width; + unsigned long flags; + wait_queue_head_t wait; + struct i2c_adapter adap; + int adap_nr; + struct i2c_msg *msg; + int pos; + int nmsgs; + int state; + spinlock_t process_lock; + uint32_t ip_clock_khz; + uint32_t bus_clock_khz; + void (*setreg)(struct ocores_i2c *i2c, int reg, u32 value); + u32 (*getreg)(struct ocores_i2c *i2c, int reg); + const char *dev_name; + uint32_t reg_access_mode; + uint32_t big_endian; + uint32_t irq_offset; + wb_pci_dev_t wb_pci_dev; + struct device *dev; +}; + +int g_wb_ocores_i2c_debug = 0; +int g_wb_ocores_i2c_error = 0; +int g_wb_ocores_i2c_xfer = 0; + +module_param(g_wb_ocores_i2c_debug, int, S_IRUGO | S_IWUSR); +module_param(g_wb_ocores_i2c_error, int, S_IRUGO | S_IWUSR); +module_param(g_wb_ocores_i2c_xfer, int, S_IRUGO | S_IWUSR); + +#define OCORES_I2C_VERBOSE(fmt, args...) do { \ + if (g_wb_ocores_i2c_debug) { \ + printk(KERN_INFO "[OCORES_I2C][VER][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +#define OCORES_I2C_ERROR(fmt, args...) do { \ + if (g_wb_ocores_i2c_error) { \ + printk(KERN_ERR "[OCORES_I2C][ERR][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +#define OCORES_I2C_XFER(fmt, args...) do { \ + if (g_wb_ocores_i2c_xfer) { \ + printk(KERN_INFO "[OCORES_I2C][XFER][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +extern int i2c_device_func_write(const char *path, uint32_t offset, uint8_t *buf, size_t count); +extern int i2c_device_func_read(const char *path, uint32_t offset, uint8_t *buf, size_t count); +extern int pcie_device_func_read(const char *path, uint32_t offset, uint8_t *buf, size_t count); +extern int pcie_device_func_write(const char *path, uint32_t offset, uint8_t *buf, size_t count); +extern int io_device_func_read(const char *path, uint32_t offset, uint8_t *buf, size_t count); +extern int io_device_func_write(const char *path, uint32_t offset, uint8_t *buf, size_t count); +#if 0 +int __attribute__((weak)) i2c_device_func_read(const char *path, uint32_t offset, + uint8_t *buf, size_t count) +{ + OCORES_I2C_ERROR("enter __weak i2c func read\r\n"); + return -EINVAL; +} + +int __attribute__((weak)) i2c_device_func_write(const char *path, uint32_t offset, + uint8_t *buf, size_t count) +{ + OCORES_I2C_ERROR("enter __weak i2c func write\r\n"); + return -EINVAL; +} + +int __attribute__((weak)) pcie_device_func_read(const char *path, uint32_t offset, + uint8_t *buf, size_t count) +{ + OCORES_I2C_ERROR("enter __weak pcie func read\r\n"); + return -EINVAL; +} + +int __attribute__((weak)) pcie_device_func_write(const char *path, uint32_t offset, + uint8_t *buf, size_t count) +{ + OCORES_I2C_ERROR("enter __weak pcie func write\r\n"); + return -EINVAL; +} + +int __attribute__((weak)) io_device_func_read(const char *path, uint32_t offset, + uint8_t *buf, size_t count) +{ + OCORES_I2C_ERROR("enter __weak io func read\r\n"); + return -EINVAL; +} + +int __attribute__((weak)) io_device_func_write(const char *path, uint32_t offset, + uint8_t *buf, size_t count) +{ + OCORES_I2C_ERROR("enter __weak io func write\r\n"); + return -EINVAL; +} +#endif +static int ocores_i2c_file_read(const char *path, uint32_t pos, uint8_t *val, size_t size) +{ + int ret; + struct file *filp; + loff_t tmp_pos; + + filp = filp_open(path, O_RDONLY, 0); + if (IS_ERR(filp)) { + OCORES_I2C_ERROR("read open failed errno = %ld\r\n", -PTR_ERR(filp)); + filp = NULL; + goto exit; + } + + tmp_pos = (loff_t)pos; + ret = kernel_read(filp, val, size, &tmp_pos); + if (ret < 0) { + OCORES_I2C_ERROR("kernel_read failed, path=%s, addr=%d, size=%ld, ret=%d\r\n", path, pos, size, ret); + goto exit; + } + + filp_close(filp, NULL); + + return ret; + +exit: + if (filp != NULL) { + filp_close(filp, NULL); + } + + return -1; +} + +static int ocores_i2c_file_write(const char *path, uint32_t pos, uint8_t *val, size_t size) +{ + + int ret; + struct file *filp; + loff_t tmp_pos; + + filp = filp_open(path, O_RDWR, 777); + if (IS_ERR(filp)) { + OCORES_I2C_ERROR("write open failed errno = %ld\r\n", -PTR_ERR(filp)); + filp = NULL; + goto exit; + } + + tmp_pos = (loff_t)pos; + ret = kernel_write(filp, val, size, &tmp_pos); + if (ret < 0) { + OCORES_I2C_ERROR("kernel_write failed, path=%s, addr=%d, size=%ld, ret=%d\r\n", path, pos, size, ret); + goto exit; + } + + vfs_fsync(filp, 1); + filp_close(filp, NULL); + + return ret; + +exit: + if (filp != NULL) { + filp_close(filp, NULL); + } + + return -1; +} + +static int ocores_i2c_reg_write(struct ocores_i2c *i2c, uint32_t pos, uint8_t *val, size_t size) +{ + int ret; + + switch (i2c->reg_access_mode) { + case SYMBOL_I2C_DEV_MODE: + ret = i2c_device_func_write(i2c->dev_name, pos, val, size); + break; + case FILE_MODE: + ret = ocores_i2c_file_write(i2c->dev_name, pos, val, size); + break; + case SYMBOL_PCIE_DEV_MODE: + ret = pcie_device_func_write(i2c->dev_name, pos, val, size); + break; + case SYMBOL_IO_DEV_MODE: + ret = io_device_func_write(i2c->dev_name, pos, val, size); + break; + default: + OCORES_I2C_ERROR("err func_mode, write failed.\n"); + return -EINVAL; + } + + return ret; +} + +static int ocores_i2c_reg_read(struct ocores_i2c *i2c, uint32_t pos, uint8_t *val, size_t size) +{ + int ret; + + switch (i2c->reg_access_mode) { + case SYMBOL_I2C_DEV_MODE: + ret = i2c_device_func_read(i2c->dev_name, pos, val, size); + break; + case FILE_MODE: + ret = ocores_i2c_file_read(i2c->dev_name, pos, val, size); + break; + case SYMBOL_PCIE_DEV_MODE: + ret = pcie_device_func_read(i2c->dev_name, pos, val, size); + break; + case SYMBOL_IO_DEV_MODE: + ret = io_device_func_read(i2c->dev_name, pos, val, size); + break; + default: + OCORES_I2C_ERROR("err func_mode, read failed.\n"); + return -EINVAL; + } + + return ret; +} +static void oc_setreg_8(struct ocores_i2c *i2c, int reg, u32 value) +{ + u8 buf_tmp[REG_IO_WIDTH_1]; + u32 pos; + + pos = i2c->base_addr + (reg << i2c->reg_shift); + OCORES_I2C_VERBOSE("path:%s, access mode:%d, pos:0x%x, value0x%x.\n", + i2c->dev_name, i2c->reg_access_mode, pos, value); + + buf_tmp[0] = (value & 0Xff); + ocores_i2c_reg_write(i2c, pos, buf_tmp, REG_IO_WIDTH_1); + return; +} + +static void oc_setreg_16(struct ocores_i2c *i2c, int reg, u32 value) +{ + u8 buf_tmp[REG_IO_WIDTH_2]; + u32 pos; + + pos = i2c->base_addr + (reg << i2c->reg_shift); + OCORES_I2C_VERBOSE("path:%s, access mode:%d, pos:0x%x, value0x%x.\n", + i2c->dev_name, i2c->reg_access_mode, pos, value); + + buf_tmp[0] = (value & 0Xff); + buf_tmp[1] = (value >> 8) & 0xff; + ocores_i2c_reg_write(i2c, pos, buf_tmp, REG_IO_WIDTH_2); + return; +} + +static void oc_setreg_32(struct ocores_i2c *i2c, int reg, u32 value) +{ + u8 buf_tmp[REG_IO_WIDTH_4]; + u32 pos; + + pos = i2c->base_addr + (reg << i2c->reg_shift); + OCORES_I2C_VERBOSE("path:%s, access mode:%d, pos:0x%x, value0x%x.\n", + i2c->dev_name, i2c->reg_access_mode, pos, value); + + buf_tmp[0] = (value & 0xff); + buf_tmp[1] = (value >> 8) & 0xff; + buf_tmp[2] = (value >> 16) & 0xff; + buf_tmp[3] = (value >> 24) & 0xff; + + ocores_i2c_reg_write(i2c, pos, buf_tmp, REG_IO_WIDTH_4); + return; +} + +static void oc_setreg_16be(struct ocores_i2c *i2c, int reg, u32 value) +{ + u8 buf_tmp[REG_IO_WIDTH_2]; + u32 pos; + + pos = i2c->base_addr + (reg << i2c->reg_shift); + OCORES_I2C_VERBOSE("path:%s, access mode:%d, pos:0x%x, value0x%x.\n", + i2c->dev_name, i2c->reg_access_mode, pos, value); + + buf_tmp[0] = (value >> 8) & 0xff; + buf_tmp[1] = (value & 0Xff); + ocores_i2c_reg_write(i2c, pos, buf_tmp, REG_IO_WIDTH_2); + return; +} + +static void oc_setreg_32be(struct ocores_i2c *i2c, int reg, u32 value) +{ + u8 buf_tmp[REG_IO_WIDTH_4]; + u32 pos; + + pos = i2c->base_addr + (reg << i2c->reg_shift); + OCORES_I2C_VERBOSE("path:%s, access mode:%d, pos:0x%x, value0x%x.\n", + i2c->dev_name, i2c->reg_access_mode, pos, value); + + buf_tmp[0] = (value >> 24) & 0xff; + buf_tmp[1] = (value >> 16) & 0xff; + buf_tmp[2] = (value >> 8) & 0xff; + buf_tmp[3] = (value & 0xff); + ocores_i2c_reg_write(i2c, pos, buf_tmp, REG_IO_WIDTH_4); + return; +} + +static inline u32 oc_getreg_8(struct ocores_i2c *i2c, int reg) +{ + u8 buf_tmp[REG_IO_WIDTH_1]; + u32 value, pos; + + pos = i2c->base_addr + (reg << i2c->reg_shift); + ocores_i2c_reg_read(i2c, pos, buf_tmp, REG_IO_WIDTH_1); + value = buf_tmp[0]; + + OCORES_I2C_VERBOSE("path:%s, access mode:%d, pos:0x%x, value0x%x.\n", + i2c->dev_name, i2c->reg_access_mode, pos, value); + + return value; +} + +static inline u32 oc_getreg_16(struct ocores_i2c *i2c, int reg) +{ + u8 buf_tmp[REG_IO_WIDTH_2]; + u32 value, pos; + int i; + + pos = i2c->base_addr + (reg << i2c->reg_shift); + mem_clear(buf_tmp, sizeof(buf_tmp)); + ocores_i2c_reg_read(i2c, pos, buf_tmp, REG_IO_WIDTH_2); + + value = 0; + for (i = 0; i < REG_IO_WIDTH_2 ; i++) { + value |= buf_tmp[i] << (8 * i); + } + + OCORES_I2C_VERBOSE("path:%s, access mode:%d, pos:0x%x, value0x%x.\n", + i2c->dev_name, i2c->reg_access_mode, pos, value); + return value; +} + +static inline u32 oc_getreg_32(struct ocores_i2c *i2c, int reg) +{ + u8 buf_tmp[REG_IO_WIDTH_4]; + u32 value, pos; + int i; + + pos = i2c->base_addr + (reg << i2c->reg_shift); + mem_clear(buf_tmp, sizeof(buf_tmp)); + ocores_i2c_reg_read(i2c, pos, buf_tmp, REG_IO_WIDTH_4); + + value = 0; + for (i = 0; i < REG_IO_WIDTH_4 ; i++) { + value |= buf_tmp[i] << (8 * i); + } + OCORES_I2C_VERBOSE("path:%s, access mode:%d, pos:0x%x, value0x%x.\n", + i2c->dev_name, i2c->reg_access_mode, pos, value); + return value; +} + +static inline u32 oc_getreg_16be(struct ocores_i2c *i2c, int reg) +{ + u8 buf_tmp[REG_IO_WIDTH_2]; + u32 value, pos; + int i; + + pos = i2c->base_addr + (reg << i2c->reg_shift); + + mem_clear(buf_tmp, sizeof(buf_tmp)); + ocores_i2c_reg_read(i2c, pos, buf_tmp, REG_IO_WIDTH_2); + + value = 0; + for (i = 0; i < REG_IO_WIDTH_2 ; i++) { + value |= buf_tmp[i] << (8 * (REG_IO_WIDTH_2 -i - 1)); + } + + OCORES_I2C_VERBOSE("path:%s, access mode:%d, pos:0x%x, value0x%x.\n", + i2c->dev_name, i2c->reg_access_mode, pos, value); + return value; +} + +static inline u32 oc_getreg_32be(struct ocores_i2c *i2c, int reg) +{ + u8 buf_tmp[REG_IO_WIDTH_4]; + u32 value, pos; + int i; + + pos = i2c->base_addr + (reg << i2c->reg_shift); + + mem_clear(buf_tmp, sizeof(buf_tmp)); + ocores_i2c_reg_read(i2c, pos, buf_tmp, REG_IO_WIDTH_4); + + value = 0; + for (i = 0; i < REG_IO_WIDTH_4 ; i++) { + value |= buf_tmp[i] << (8 * (REG_IO_WIDTH_4 -i - 1)); + } + + OCORES_I2C_VERBOSE("path:%s, access mode:%d, pos:0x%x, value0x%x.\n", + i2c->dev_name, i2c->reg_access_mode, pos, value); + return value; + +} + +static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u32 value) +{ + i2c->setreg(i2c, reg, value); + return; +} + +static inline u32 oc_getreg(struct ocores_i2c *i2c, int reg) +{ + return i2c->getreg(i2c, reg); +} + +static int ocores_msg_check(struct i2c_msg *msgs, int num) +{ + int i, ret = 0; + + if (!msgs) { + ret = -EFAULT; + goto out; + } + + for (i = 0; i < num; ++i) { + if (!msgs[i].buf) { + ret = -EFAULT; + goto out; + } + } + +out: + return ret; +} + +static void ocores_process(struct ocores_i2c *i2c, u8 stat) +{ + struct i2c_msg *msg = i2c->msg; + + OCORES_I2C_XFER("Enter nr %d.\n", i2c->adap.nr); + if ((i2c->state == STATE_DONE) || (i2c->state == STATE_ERROR)) { + /* stop has been sent */ + oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK); + wake_up(&i2c->wait); + OCORES_I2C_XFER("stop has been sent, exit.\n"); + goto out; + } + + /* error? */ + if (stat & OCI2C_STAT_ARBLOST) { + i2c->state = STATE_ERROR; + oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); + OCORES_I2C_XFER("error exit, lose arbitration.\n"); + goto out; + } + + if (ocores_msg_check(i2c->msg, i2c->nmsgs) != 0) { + OCORES_I2C_XFER("msg buf is NULL\n"); + i2c->state = STATE_ERROR; + oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); + goto out; + } + + if ((i2c->state == STATE_START) || (i2c->state == STATE_WRITE)) { + i2c->state = + (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE; + + if (stat & OCI2C_STAT_NACK) { + i2c->state = STATE_ERROR; + oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); + OCORES_I2C_XFER("OCI2C_STAT_NACK, exit.\n"); + goto out; + } + } else { + msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA); + } + + /* end of msg? */ + if (i2c->pos == msg->len) { + OCORES_I2C_XFER("Enter end of msg.\n"); + i2c->nmsgs--; + i2c->msg++; + i2c->pos = 0; + msg = i2c->msg; + + if (i2c->nmsgs) { /* end? */ + /* send start? */ + if (!(msg->flags & I2C_M_NOSTART)) { + u8 addr = i2c_8bit_addr_from_msg(msg); + + i2c->state = STATE_START; + + oc_setreg(i2c, OCI2C_DATA, addr); + oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START); + OCORES_I2C_XFER("send start, exit.\n"); + goto out; + } + i2c->state = (msg->flags & I2C_M_RD) + ? STATE_READ : STATE_WRITE; + } else { + i2c->state = STATE_DONE; + oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); + OCORES_I2C_XFER("send OCI2C_CMD_STOP, exit.\n"); + goto out; + } + } + + if (i2c->state == STATE_READ) { + oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len-1) ? + OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK); + } else { + oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]); + oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE); + } + +out: + OCORES_I2C_XFER("normal, exit nr %d.\n", i2c->adap.nr); + return; +} + +static irqreturn_t ocores_isr(int irq, void *dev_id) +{ + struct ocores_i2c *i2c = dev_id; + u8 stat; + unsigned long flags; + + if (!i2c) { + return IRQ_NONE; + } + + spin_lock_irqsave(&i2c->process_lock, flags); + stat = oc_getreg(i2c, OCI2C_STATUS); + if (!(stat & OCI2C_STAT_IF)) { + spin_unlock_irqrestore(&i2c->process_lock, flags); + return IRQ_NONE; + } + OCORES_I2C_XFER("Enter, irq %d nr %d addr 0x%x.\n", irq, i2c->adap.nr, (!i2c->msg)? 0 : i2c->msg->addr); + ocores_process(i2c, stat); + OCORES_I2C_XFER("Leave, irq %d nr %d addr 0x%x.\n", irq, i2c->adap.nr, (!i2c->msg)? 0 : i2c->msg->addr); + spin_unlock_irqrestore(&i2c->process_lock, flags); + + return IRQ_HANDLED; +} + +/** + * Process timeout event + * @i2c: ocores I2C device instance + */ +static void ocores_process_timeout(struct ocores_i2c *i2c) +{ + unsigned long flags; + + spin_lock_irqsave(&i2c->process_lock, flags); + i2c->state = STATE_ERROR; + oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP); + mdelay(1); + spin_unlock_irqrestore(&i2c->process_lock, flags); + return; +} + +/** + * Wait until something change in a given register + * @i2c: ocores I2C device instance + * @reg: register to query + * @mask: bitmask to apply on register value + * @val: expected result + * @timeout: timeout in jiffies + * + * Timeout is necessary to avoid to stay here forever when the chip + * does not answer correctly. + * + * Return: 0 on success, -ETIMEDOUT on timeout + */ +static int ocores_wait(struct ocores_i2c *i2c, + int reg, u8 mask, u8 val, + const unsigned long timeout) +{ + u8 status; + unsigned long j, jiffies_tmp; + unsigned int usleep; + + usleep = OCORE_WAIT_SCH; + j = jiffies + timeout; + while (1) { + jiffies_tmp = jiffies; + status = oc_getreg(i2c, reg); + + if ((status & mask) == val) { + break; + } + + if (time_after(jiffies_tmp, j)) { + OCORES_I2C_XFER("STATUS timeout, mask[0x%x] val[0x%x] status[0x%x]\n", mask, val, status); + return -ETIMEDOUT; + } + usleep_range(usleep,usleep + 1); + } + return 0; + +} + +/** + * Wait until is possible to process some data + * @i2c: ocores I2C device instance + * + * Used when the device is in polling mode (interrupts disabled). + * + * Return: 0 on success, -ETIMEDOUT on timeout + */ +static int ocores_poll_wait(struct ocores_i2c *i2c) +{ + u8 mask; + int err; + + if (i2c->state == STATE_DONE || i2c->state == STATE_ERROR) { + /* transfer is over */ + mask = OCI2C_STAT_BUSY; + } else { + /* on going transfer */ + mask = OCI2C_STAT_TIP; + /* + * We wait for the data to be transferred (8bit), + * then we start polling on the ACK/NACK bit + */ + udelay((8 * 1000) / i2c->bus_clock_khz); + } + + /* + * once we are here we expect to get the expected result immediately + * so if after 100ms we timeout then something is broken. + */ + err = ocores_wait(i2c, OCI2C_STATUS, mask, 0, msecs_to_jiffies(100)); + if (err) { + OCORES_I2C_XFER("STATUS timeout, bit 0x%x did not clear in 100ms, err %d\n", mask, err); + } + return err; +} + +/** + * It handles an IRQ-less transfer + * @i2c: ocores I2C device instance + * + * Even if IRQ are disabled, the I2C OpenCore IP behavior is exactly the same + * (only that IRQ are not produced). This means that we can re-use entirely + * ocores_isr(), we just add our polling code around it. + * + * It can run in atomic context + */ +static int ocores_process_polling(struct ocores_i2c *i2c) +{ + irqreturn_t ret; + int err; + + while (1) { + err = ocores_poll_wait(i2c); + if (err) { + i2c->state = STATE_ERROR; + break; /* timeout */ + } + + ret = ocores_isr(-1, i2c); + if (ret == IRQ_NONE) { + break; /* all messages have been transferred */ + } + } + + return err; +} + +static int ocores_xfer_core(struct ocores_i2c *i2c, + struct i2c_msg *msgs, int num, + bool polling) +{ + int ret; + u8 ctrl; + unsigned long flags; + + OCORES_I2C_VERBOSE("Enter ocores_xfer_core. polling mode:%d.\n", polling); + spin_lock_irqsave(&i2c->process_lock, flags); + + ctrl = oc_getreg(i2c, OCI2C_CONTROL); + if (polling) { + oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~OCI2C_CTRL_IEN); + } else { + oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_IEN); + } + + i2c->msg = msgs; + i2c->pos = 0; + i2c->nmsgs = num; + i2c->state = STATE_START; + + oc_setreg(i2c, OCI2C_DATA, i2c_8bit_addr_from_msg(i2c->msg)); + oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START); + + spin_unlock_irqrestore(&i2c->process_lock, flags); + + if (polling) { + ret = ocores_process_polling(i2c); + if (ret) { + ocores_process_timeout(i2c); + return -ETIMEDOUT; + } + } else { + ret = wait_event_timeout(i2c->wait, + (i2c->state == STATE_ERROR) || + (i2c->state == STATE_DONE), HZ); + if (ret == 0) { + ocores_process_timeout(i2c); + return -ETIMEDOUT; + } + } + + return (i2c->state == STATE_DONE) ? num : -EIO; +} + +static int ocores_xfer(struct i2c_adapter *adap, + struct i2c_msg *msgs, int num) +{ + struct ocores_i2c *i2c; + int ret; + + OCORES_I2C_VERBOSE("Enter ocores_xfer.\n"); + if (!adap || ocores_msg_check(msgs, num)) { + OCORES_I2C_ERROR("[MAY BE USER SPACE ERROR]:msg buf is NULL\n"); + return -EFAULT; + } + OCORES_I2C_VERBOSE("i2c bus:%d, msgs num:%d.\n", adap->nr, num); + + i2c = i2c_get_adapdata(adap); + + if (i2c->flags & OCORES_FLAG_POLL) { + ret = ocores_xfer_core(i2c, msgs, num, true); + } else { + ret = ocores_xfer_core(i2c, msgs, num, false); + } + + return ret; +} + +static int ocores_init(struct device *dev, struct ocores_i2c *i2c) +{ + int prescale; + int diff; + u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL); + + /* make sure the device is disabled */ + ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN); + oc_setreg(i2c, OCI2C_CONTROL, ctrl); + + prescale = (i2c->ip_clock_khz / (5 * i2c->bus_clock_khz)) - 1; + prescale = clamp(prescale, 0, 0xffff); + + diff = i2c->ip_clock_khz / (5 * (prescale + 1)) - i2c->bus_clock_khz; + if (abs(diff) > i2c->bus_clock_khz / 10) { + dev_err(dev, "Unsupported clock settings: core: %d KHz, bus: %d KHz\n", + i2c->ip_clock_khz, i2c->bus_clock_khz); + return -EINVAL; + } + + oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff); + oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8); + + /* Init the device */ + oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK); + oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_EN); + + return 0; +} + +static u32 ocores_func(struct i2c_adapter *adap) +{ + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; +} + +static const struct i2c_algorithm ocores_algorithm = { + .master_xfer = ocores_xfer, + .functionality = ocores_func, +}; + +static const struct i2c_adapter ocores_adapter = { + .owner = THIS_MODULE, + .name = "wb-i2c-ocores", + .class = I2C_CLASS_DEPRECATED, + .algo = &ocores_algorithm, +}; + +static const struct of_device_id ocores_i2c_match[] = { + { + .compatible = "opencores,wb-i2c-ocores", + .data = (void *)TYPE_OCORES, + }, + {}, +}; +MODULE_DEVICE_TABLE(of, ocores_i2c_match); + +static int fpga_ocores_i2c_get_irq(struct ocores_i2c *i2c) +{ + int devfn, irq; + struct device *dev; + wb_pci_dev_t *wb_pci_dev; + struct pci_dev *pci_dev; + i2c_ocores_device_t *i2c_ocores_device; + int ret; + + dev = i2c->dev; + wb_pci_dev = &i2c->wb_pci_dev; + + if (dev->of_node) { + ret = 0; + ret += of_property_read_u32(dev->of_node, "pci_domain", &wb_pci_dev->domain); + ret += of_property_read_u32(dev->of_node, "pci_bus", &wb_pci_dev->bus); + ret += of_property_read_u32(dev->of_node, "pci_slot", &wb_pci_dev->slot); + ret += of_property_read_u32(dev->of_node, "pci_fn", &wb_pci_dev->fn); + + if (ret != 0) { + OCORES_I2C_ERROR("dts config error, ret:%d.\n", ret); + ret = -EINVAL; + return ret; + } + } else { + if (i2c->dev->platform_data == NULL) { + OCORES_I2C_ERROR("Failed to get platform data config.\n"); + ret = -EINVAL; + return ret; + } + i2c_ocores_device = i2c->dev->platform_data; + wb_pci_dev->domain = i2c_ocores_device->pci_domain; + wb_pci_dev->bus = i2c_ocores_device->pci_bus; + wb_pci_dev->slot = i2c_ocores_device->pci_slot; + wb_pci_dev->fn = i2c_ocores_device->pci_fn; + } + + OCORES_I2C_VERBOSE("pci_domain:0x%x, pci_bus:0x%x, pci_slot:0x%x, pci_fn:0x%x.\n", + wb_pci_dev->domain, wb_pci_dev->bus, wb_pci_dev->slot, wb_pci_dev->fn); + + devfn = PCI_DEVFN(wb_pci_dev->slot, wb_pci_dev->fn); + pci_dev = pci_get_domain_bus_and_slot(wb_pci_dev->domain, wb_pci_dev->bus, devfn); + if (pci_dev == NULL) { + OCORES_I2C_ERROR("Failed to find pci_dev, domain:0x%04x, bus:0x%02x, devfn:0x%x\n", + wb_pci_dev->domain, wb_pci_dev->bus, devfn); + return -ENODEV; + } + irq = pci_dev->irq + i2c->irq_offset; + OCORES_I2C_VERBOSE("get irq no:%d.\n", irq); + return irq; +} + +static int ocores_i2c_config_init(struct ocores_i2c *i2c) +{ + int ret; + struct device *dev; + i2c_ocores_device_t *i2c_ocores_device; + + dev = i2c->dev; + ret = 0; + + if (dev->of_node) { + ret += of_property_read_string(dev->of_node, "dev_name", &i2c->dev_name); + ret += of_property_read_u32(dev->of_node, "dev_base", &i2c->base_addr); + ret += of_property_read_u32(dev->of_node, "reg_shift", &i2c->reg_shift); + ret += of_property_read_u32(dev->of_node, "reg_io_width", &i2c->reg_io_width); + ret += of_property_read_u32(dev->of_node, "ip_clock_khz", &i2c->ip_clock_khz); + ret += of_property_read_u32(dev->of_node, "bus_clock_khz", &i2c->bus_clock_khz); + ret += of_property_read_u32(dev->of_node, "reg_access_mode", &i2c->reg_access_mode); + + if (ret != 0) { + OCORES_I2C_ERROR("dts config error, ret:%d.\n", ret); + ret = -ENXIO; + return ret; + } + } else { + if (i2c->dev->platform_data == NULL) { + OCORES_I2C_ERROR("Failed to get platform data config.\n"); + ret = -ENXIO; + return ret; + } + i2c_ocores_device = i2c->dev->platform_data; + i2c->dev_name = i2c_ocores_device->dev_name; + i2c->adap_nr = i2c_ocores_device->adap_nr; + i2c->big_endian = i2c_ocores_device->big_endian; + i2c->base_addr = i2c_ocores_device->dev_base; + i2c->reg_shift = i2c_ocores_device->reg_shift; + i2c->reg_io_width = i2c_ocores_device->reg_io_width; + i2c->ip_clock_khz = i2c_ocores_device->ip_clock_khz; + i2c->bus_clock_khz = i2c_ocores_device->bus_clock_khz; + i2c->reg_access_mode = i2c_ocores_device->reg_access_mode; + } + + OCORES_I2C_VERBOSE("name:%s, base:0x%x, reg_shift:0x%x, io_width:0x%x, ip_clock_khz:0x%x, bus_clock_khz:0x%x.\n", + i2c->dev_name, i2c->base_addr, i2c->reg_shift, i2c->reg_io_width, i2c->ip_clock_khz, i2c->bus_clock_khz); + OCORES_I2C_VERBOSE("reg access mode:%d.\n", i2c->reg_access_mode); + return ret; +} + +static int ocores_i2c_probe(struct platform_device *pdev) +{ + struct ocores_i2c *i2c; + int irq, ret; + bool be; + i2c_ocores_device_t *i2c_ocores_device; + + OCORES_I2C_VERBOSE("Enter main probe\n"); + + i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); + if (!i2c) { + dev_err(&pdev->dev, "devm_kzalloc failed.\n"); + return -ENOMEM; + } + + spin_lock_init(&i2c->process_lock); + + i2c->dev = &pdev->dev; + ret = ocores_i2c_config_init(i2c); + if (ret !=0) { + dev_err(i2c->dev, "Failed to get ocores i2c dts config.\n"); + goto out; + } + + if (i2c->dev->of_node) { + if (of_property_read_u32(i2c->dev->of_node, "big_endian", &i2c->big_endian)) { + + be = 0; + } else { + be = i2c->big_endian; + } + } else { + be = i2c->big_endian; + } + + if (i2c->reg_io_width == 0) { + i2c->reg_io_width = 1; /* Set to default value */ + } + + if (!i2c->setreg || !i2c->getreg) { + switch (i2c->reg_io_width) { + case REG_IO_WIDTH_1: + i2c->setreg = oc_setreg_8; + i2c->getreg = oc_getreg_8; + break; + + case REG_IO_WIDTH_2: + i2c->setreg = be ? oc_setreg_16be : oc_setreg_16; + i2c->getreg = be ? oc_getreg_16be : oc_getreg_16; + break; + + case REG_IO_WIDTH_4: + i2c->setreg = be ? oc_setreg_32be : oc_setreg_32; + i2c->getreg = be ? oc_getreg_32be : oc_getreg_32; + break; + + default: + dev_err(i2c->dev, "Unsupported I/O width (%d)\n", + i2c->reg_io_width); + ret = -EINVAL; + goto out; + } + } + + init_waitqueue_head(&i2c->wait); + irq = -1; + + if (i2c->dev->of_node) { + if (of_property_read_u32(i2c->dev->of_node, "irq_offset", &i2c->irq_offset)) { + + i2c->flags |= OCORES_FLAG_POLL; + } else { + + irq = fpga_ocores_i2c_get_irq(i2c); + if (irq < 0 ) { + dev_err(i2c->dev, "Failed to get ocores i2c irq number, ret: %d.\n", irq); + ret = irq; + goto out; + } + } + } else { + if (i2c->dev->platform_data == NULL) { + + i2c->flags |= OCORES_FLAG_POLL; + OCORES_I2C_VERBOSE("Failed to get platform data config, set OCORES_FLAG_POLL.\n"); + } else { + i2c_ocores_device = i2c->dev->platform_data; + if (i2c_ocores_device->irq_type == 0) { + + i2c->flags |= OCORES_FLAG_POLL; + } else { + + irq = fpga_ocores_i2c_get_irq(i2c); + if (irq < 0 ) { + dev_err(i2c->dev, "Failed to get ocores i2c irq number, ret: %d.\n", irq); + ret = irq; + goto out; + } + } + } + } + + if (!(i2c->flags & OCORES_FLAG_POLL)) { + ret = devm_request_irq(&pdev->dev, irq, ocores_isr, 0, + pdev->name, i2c); + if (ret) { + dev_err(i2c->dev, "Cannot claim IRQ\n"); + goto out; + } + } + + ret = ocores_init(i2c->dev, i2c); + if (ret) { + goto out; + } + + /* hook up driver to tree */ + platform_set_drvdata(pdev, i2c); + i2c->adap = ocores_adapter; + i2c_set_adapdata(&i2c->adap, i2c); + i2c->adap.dev.parent = &pdev->dev; + i2c->adap.dev.of_node = pdev->dev.of_node; + + if (i2c->dev->of_node) { + /* adap.nr get from dts aliases */ + ret = i2c_add_adapter(&i2c->adap); + } else { + i2c->adap.nr = i2c->adap_nr; + ret = i2c_add_numbered_adapter(&i2c->adap); + } + if (ret) { + goto fail_add; + } + OCORES_I2C_VERBOSE("Main probe out\n"); + dev_info(i2c->dev, "registered i2c-%d for %s with base address:0x%x success.\n", + i2c->adap.nr, i2c->dev_name, i2c->base_addr); + return 0; +fail_add: + platform_set_drvdata(pdev, NULL); +out: + return ret; +} + +static int ocores_i2c_remove(struct platform_device *pdev) +{ + struct ocores_i2c *i2c = platform_get_drvdata(pdev); + u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL); + + /* disable i2c logic */ + ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN); + oc_setreg(i2c, OCI2C_CONTROL, ctrl); + + /* remove adapter & data */ + i2c_del_adapter(&i2c->adap); + return 0; +} + +static struct platform_driver ocores_i2c_driver = { + .probe = ocores_i2c_probe, + .remove = ocores_i2c_remove, + .driver = { + .name = "wb-ocores-i2c", + .of_match_table = ocores_i2c_match, + }, +}; + +module_platform_driver(ocores_i2c_driver); + +MODULE_AUTHOR("support"); +MODULE_DESCRIPTION("OpenCores I2C bus driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:ocores-i2c"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_i2c_ocores.h b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_i2c_ocores.h new file mode 100644 index 000000000000..acd2710a92f0 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_i2c_ocores.h @@ -0,0 +1,28 @@ +#ifndef __WB_I2C_OCORES_H__ +#define __WB_I2C_OCORES_H__ +#include + +#define mem_clear(data, size) memset((data), 0, (size)) +#define I2C_OCORES_DEV_NAME_MAX_LEN (64) + +typedef struct i2c_ocores_device_s { + uint32_t big_endian; + char dev_name[I2C_OCORES_DEV_NAME_MAX_LEN]; + int adap_nr; + uint32_t dev_base; + uint32_t reg_shift; + uint32_t reg_io_width; + uint32_t ip_clock_khz; + uint32_t bus_clock_khz; + uint32_t reg_access_mode; + + uint32_t irq_type; + uint32_t irq_offset; + uint32_t pci_domain; + uint32_t pci_bus; + uint32_t pci_slot; + uint32_t pci_fn; + int device_flag; +} i2c_ocores_device_t; + +#endif diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_io_dev.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_io_dev.c new file mode 100644 index 000000000000..4a4bbba0ade5 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_io_dev.c @@ -0,0 +1,571 @@ +/* + * wb_io_dev.c + * ko to read/write ioports through /dev/XXX device + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "wb_io_dev.h" + +#define PROXY_NAME "wb-io-dev" +#define MAX_IO_DEV_NUM (256) +#define IO_RDWR_MAX_LEN (256) +#define MAX_NAME_SIZE (20) +#define IO_INDIRECT_ADDR_H(addr) ((addr >> 8) & 0xff) +#define IO_INDIRECT_ADDR_L(addr) ((addr) & 0xff) +#define IO_INDIRECT_OP_WRITE (0x2) +#define IO_INDIRECT_OP_READ (0X3) + +static int g_io_dev_debug = 0; +static int g_io_dev_error = 0; + +module_param(g_io_dev_debug, int, S_IRUGO | S_IWUSR); +module_param(g_io_dev_error, int, S_IRUGO | S_IWUSR); + +#define IO_DEV_DEBUG_VERBOSE(fmt, args...) do { \ + if (g_io_dev_debug) { \ + printk(KERN_INFO "[IO_DEV][VER][func:%s line:%d]\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +#define IO_DEV_DEBUG_ERROR(fmt, args...) do { \ + if (g_io_dev_error) { \ + printk(KERN_ERR "[IO_DEV][ERR][func:%s line:%d]\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +typedef struct wb_io_dev_s { + const char *name; + uint32_t io_base; + uint32_t io_len; + uint32_t indirect_addr; + uint32_t wr_data; + uint32_t addr_low; + uint32_t addr_high; + uint32_t rd_data; + uint32_t opt_ctl; + spinlock_t io_dev_lock; + struct miscdevice misc; +} wb_io_dev_t; + +static wb_io_dev_t* io_dev_arry[MAX_IO_DEV_NUM]; + +static int io_dev_open(struct inode *inode, struct file *file) +{ + unsigned int minor = iminor(inode); + wb_io_dev_t *wb_io_dev; + + if (minor >= MAX_IO_DEV_NUM) { + IO_DEV_DEBUG_ERROR("minor out of range, minor = %d.\n", minor); + return -ENODEV; + } + + wb_io_dev = io_dev_arry[minor]; + if (wb_io_dev == NULL) { + IO_DEV_DEBUG_ERROR("wb_io_dev is NULL, open failed, minor = %d\n", minor); + return -ENODEV; + } + + file->private_data = wb_io_dev; + return 0; +} + +static int io_dev_release(struct inode *inode, struct file *file) +{ + file->private_data = NULL; + return 0; +} + +uint8_t io_indirect_addressing_read(wb_io_dev_t *wb_io_dev, uint32_t address) +{ + uint8_t addr_l, addr_h, value; + unsigned long flags; + + addr_h = IO_INDIRECT_ADDR_H(address); + addr_l = IO_INDIRECT_ADDR_L(address); + IO_DEV_DEBUG_VERBOSE("read one count, addr = 0x%x\n", address); + + spin_lock_irqsave(&wb_io_dev->io_dev_lock, flags); + + outb(addr_l, wb_io_dev->io_base + wb_io_dev->addr_low); + + outb(addr_h, wb_io_dev->io_base + wb_io_dev->addr_high); + + outb(IO_INDIRECT_OP_READ, wb_io_dev->io_base + wb_io_dev->opt_ctl); + + value = inb(wb_io_dev->io_base + wb_io_dev->rd_data); + + spin_unlock_irqrestore(&wb_io_dev->io_dev_lock, flags); + + return value; +} + +static int io_dev_read_tmp(wb_io_dev_t *wb_io_dev, uint32_t offset, uint8_t *buf, size_t count) +{ + int i; + + if (offset > wb_io_dev->io_len) { + IO_DEV_DEBUG_VERBOSE("offset:0x%x, io len:0x%x, EOF.\n", offset, wb_io_dev->io_len); + return 0; + } + + if (count > wb_io_dev->io_len - offset) { + IO_DEV_DEBUG_VERBOSE("read count out of range. input len:%lu, read len:%u.\n", + count, wb_io_dev->io_len - offset); + count = wb_io_dev->io_len - offset; + } + if (wb_io_dev->indirect_addr) { + for (i = 0; i < count; i++) { + buf[i] = io_indirect_addressing_read(wb_io_dev, offset + i); + } + } else { + for (i = 0; i < count; i++) { + buf[i] = inb(wb_io_dev->io_base + offset + i); + } + } + + return count; +} + +static ssize_t io_dev_read(struct file *file, char __user *buf, size_t count, loff_t *offset) +{ + wb_io_dev_t *wb_io_dev; + int ret, read_len; + u8 buf_tmp[IO_RDWR_MAX_LEN]; + + wb_io_dev = file->private_data; + if (wb_io_dev == NULL) { + IO_DEV_DEBUG_ERROR("wb_io_dev is NULL, read failed.\n"); + return -EINVAL; + } + + if (count == 0) { + IO_DEV_DEBUG_ERROR("Invalid params, read count is 0.n"); + return -EINVAL; + } + + if (count > sizeof(buf_tmp)) { + IO_DEV_DEBUG_VERBOSE("read conut %lu exceed max %lu.\n", count, sizeof(buf_tmp)); + count = sizeof(buf_tmp); + } + + mem_clear(buf_tmp, sizeof(buf_tmp)); + read_len = io_dev_read_tmp(wb_io_dev, *offset, buf_tmp, count); + if (read_len < 0) { + IO_DEV_DEBUG_ERROR("io_dev_read_tmp failed, ret:%d.\n", read_len); + return read_len; + } + + if (access_ok(buf, read_len)) { + IO_DEV_DEBUG_VERBOSE("user space read, buf: %p, offset: %lld, read conut %lu.\n", + buf, *offset, count); + if (copy_to_user(buf, buf_tmp, read_len)) { + IO_DEV_DEBUG_ERROR("copy_to_user failed.\n"); + return -EFAULT; + } + } else { + IO_DEV_DEBUG_VERBOSE("kernel space read, buf: %p, offset: %lld, read conut %lu.\n", + buf, *offset, count); + memcpy(buf, buf_tmp, read_len); + } + *offset += read_len; + ret = read_len; + return ret; +} + +static ssize_t io_dev_read_iter(struct kiocb *iocb, struct iov_iter *to) +{ + int ret; + + IO_DEV_DEBUG_VERBOSE("io_dev_read_iter, file: %p, count: %lu, offset: %lld\n", + iocb->ki_filp, to->count, iocb->ki_pos); + ret = io_dev_read(iocb->ki_filp, to->kvec->iov_base, to->count, &iocb->ki_pos); + return ret; +} + +void io_indirect_addressing_write(wb_io_dev_t *wb_io_dev, uint32_t address, uint8_t reg_val) +{ + uint8_t addr_l, addr_h; + unsigned long flags; + + addr_h = IO_INDIRECT_ADDR_H(address); + addr_l = IO_INDIRECT_ADDR_L(address); + IO_DEV_DEBUG_VERBOSE("write one count, addr = 0x%x\n", address); + + spin_lock_irqsave(&wb_io_dev->io_dev_lock, flags); + + outb(reg_val, wb_io_dev->io_base + wb_io_dev->wr_data); + + outb(addr_l, wb_io_dev->io_base + wb_io_dev->addr_low); + + outb(addr_h, wb_io_dev->io_base + wb_io_dev->addr_high); + + outb(IO_INDIRECT_OP_WRITE, wb_io_dev->io_base + wb_io_dev->opt_ctl); + + spin_unlock_irqrestore(&wb_io_dev->io_dev_lock, flags); + + return; +} + +static int io_dev_write_tmp(wb_io_dev_t *wb_io_dev, uint32_t offset, uint8_t *buf, size_t count) +{ + int i; + + if (offset > wb_io_dev->io_len) { + IO_DEV_DEBUG_VERBOSE("offset:0x%x, io len:0x%x, EOF.\n", offset, wb_io_dev->io_len); + return 0; + } + + if (count > wb_io_dev->io_len - offset) { + IO_DEV_DEBUG_VERBOSE("write count out of range. input len:%lu, write len:%u.\n", + count, wb_io_dev->io_len - offset); + count = wb_io_dev->io_len - offset; + } + if (wb_io_dev->indirect_addr) { + for (i = 0; i < count; i++) { + io_indirect_addressing_write(wb_io_dev, offset + i, buf[i]); + } + } else { + for (i = 0; i < count; i++) { + outb(buf[i], wb_io_dev->io_base + offset + i); + } + } + + return count; +} + +static ssize_t io_dev_write(struct file *file, const char __user *buf, size_t count, loff_t *offset) +{ + wb_io_dev_t *wb_io_dev; + int write_len; + u8 buf_tmp[IO_RDWR_MAX_LEN]; + + wb_io_dev = file->private_data; + if (wb_io_dev == NULL) { + IO_DEV_DEBUG_ERROR("wb_io_dev is NULL, write failed.\n"); + return -EINVAL; + } + + if (count == 0) { + IO_DEV_DEBUG_ERROR("Invalid params, write count is 0.\n"); + return -EINVAL; + } + + if (count > sizeof(buf_tmp)) { + IO_DEV_DEBUG_VERBOSE("write conut %lu exceed max %lu.\n", count, sizeof(buf_tmp)); + count = sizeof(buf_tmp); + } + + mem_clear(buf_tmp, sizeof(buf_tmp)); + if (access_ok(buf, count)) { + IO_DEV_DEBUG_VERBOSE("user space write, buf: %p, offset: %lld, write conut %lu.\n", + buf, *offset, count); + if (copy_from_user(buf_tmp, buf, count)) { + IO_DEV_DEBUG_ERROR("copy_from_user failed.\n"); + return -EFAULT; + } + } else { + IO_DEV_DEBUG_VERBOSE("kernel space write, buf: %p, offset: %lld, write conut %lu.\n", + buf, *offset, count); + memcpy(buf_tmp, buf, count); + } + + write_len = io_dev_write_tmp(wb_io_dev, *offset, buf_tmp, count); + if (write_len < 0) { + IO_DEV_DEBUG_ERROR("io_dev_write_tmp failed, ret:%d.\n", write_len); + return write_len; + } + + *offset += write_len; + return write_len; +} + +static ssize_t io_dev_write_iter(struct kiocb *iocb, struct iov_iter *from) +{ + int ret; + + IO_DEV_DEBUG_VERBOSE("io_dev_write_iter, file: %p, count: %lu, offset: %lld\n", + iocb->ki_filp, from->count, iocb->ki_pos); + ret = io_dev_write(iocb->ki_filp, from->kvec->iov_base, from->count, &iocb->ki_pos); + return ret; +} + +static loff_t io_dev_llseek(struct file *file, loff_t offset, int origin) +{ + loff_t ret = 0; + wb_io_dev_t *wb_io_dev; + + wb_io_dev = file->private_data; + if (wb_io_dev == NULL) { + IO_DEV_DEBUG_ERROR("wb_io_dev is NULL, llseek failed.\n"); + return -EINVAL; + } + + switch (origin) { + case SEEK_SET: + if (offset < 0) { + IO_DEV_DEBUG_ERROR("SEEK_SET, offset:%lld, invalid.\n", offset); + ret = -EINVAL; + break; + } + if (offset > wb_io_dev->io_len) { + IO_DEV_DEBUG_ERROR("SEEK_SET out of range, offset:%lld, io_len:0x%x.\n", + offset, wb_io_dev->io_len); + ret = - EINVAL; + break; + } + file->f_pos = offset; + ret = file->f_pos; + break; + case SEEK_CUR: + if (((file->f_pos + offset) > wb_io_dev->io_len) || ((file->f_pos + offset) < 0)) { + IO_DEV_DEBUG_ERROR("SEEK_CUR out of range, f_ops:%lld, offset:%lld, io_len:0x%x.\n", + file->f_pos, offset, wb_io_dev->io_len); + ret = - EINVAL; + break; + } + file->f_pos += offset; + ret = file->f_pos; + break; + default: + IO_DEV_DEBUG_ERROR("unsupport llseek type:%d.\n", origin); + ret = -EINVAL; + break; + } + return ret; +} + +static long io_dev_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + return 0; +} + +static const struct file_operations io_dev_fops = { + .owner = THIS_MODULE, + .llseek = io_dev_llseek, + .read_iter = io_dev_read_iter, + .write_iter = io_dev_write_iter, + .unlocked_ioctl = io_dev_ioctl, + .open = io_dev_open, + .release = io_dev_release, +}; + +static wb_io_dev_t *dev_match(const char *path) +{ + wb_io_dev_t *wb_io_dev; + char dev_name[MAX_NAME_SIZE]; + int i; + + for (i = 0; i < MAX_IO_DEV_NUM; i++) { + if (io_dev_arry[i] == NULL) { + continue; + } + wb_io_dev = io_dev_arry[i]; + snprintf(dev_name, MAX_NAME_SIZE,"/dev/%s", wb_io_dev->name); + if (!strcmp(path, dev_name)) { + IO_DEV_DEBUG_VERBOSE("get dev_name = %s, minor = %d\n", dev_name, i); + return wb_io_dev; + } + } + + return NULL; +} + +int io_device_func_read(const char *path, uint32_t offset, uint8_t *buf, size_t count) +{ + wb_io_dev_t *wb_io_dev; + int read_len; + + if (path == NULL) { + IO_DEV_DEBUG_ERROR("path NULL"); + return -EINVAL; + } + + if (buf == NULL) { + IO_DEV_DEBUG_ERROR("buf NULL"); + return -EINVAL; + } + + wb_io_dev = dev_match(path); + if (wb_io_dev == NULL) { + IO_DEV_DEBUG_ERROR("io_dev match failed. dev path = %s", path); + return -EINVAL; + } + + read_len = io_dev_read_tmp(wb_io_dev, offset, buf, count); + if (read_len < 0) { + IO_DEV_DEBUG_ERROR("io_dev_read_tmp failed, ret:%d.\n", read_len); + } + return read_len; +} +EXPORT_SYMBOL(io_device_func_read); + +int io_device_func_write(const char *path, uint32_t offset, uint8_t *buf, size_t count) +{ + wb_io_dev_t *wb_io_dev; + int write_len; + + if (path == NULL) { + IO_DEV_DEBUG_ERROR("path NULL"); + return -EINVAL; + } + + if (buf == NULL) { + IO_DEV_DEBUG_ERROR("buf NULL"); + return -EINVAL; + } + + wb_io_dev = dev_match(path); + if (wb_io_dev == NULL) { + IO_DEV_DEBUG_ERROR("i2c_dev match failed. dev path = %s", path); + return -EINVAL; + } + + write_len = io_dev_write_tmp(wb_io_dev, offset, buf, count); + if (write_len < 0) { + IO_DEV_DEBUG_ERROR("io_dev_write_tmp failed, ret:%d.\n", write_len); + } + return write_len; +} +EXPORT_SYMBOL(io_device_func_write); + +static int io_dev_probe(struct platform_device *pdev) +{ + int ret; + wb_io_dev_t *wb_io_dev; + struct miscdevice *misc; + io_dev_device_t *io_dev_device; + + wb_io_dev = devm_kzalloc(&pdev->dev, sizeof(wb_io_dev_t), GFP_KERNEL); + if (!wb_io_dev) { + dev_err(&pdev->dev, "devm_kzalloc failed.\n"); + ret = -ENOMEM; + return ret; + } + spin_lock_init(&wb_io_dev->io_dev_lock); + + if (pdev->dev.of_node) { + ret = 0; + ret += of_property_read_string(pdev->dev.of_node, "io_dev_name", &wb_io_dev->name); + ret += of_property_read_u32(pdev->dev.of_node, "io_base", &wb_io_dev->io_base); + ret += of_property_read_u32(pdev->dev.of_node, "io_len", &wb_io_dev->io_len); + if (of_property_read_bool(pdev->dev.of_node, "indirect_addr")) { + + wb_io_dev->indirect_addr = 1; + ret += of_property_read_u32(pdev->dev.of_node, "wr_data", &wb_io_dev->wr_data); + ret += of_property_read_u32(pdev->dev.of_node, "addr_low", &wb_io_dev->addr_low); + ret += of_property_read_u32(pdev->dev.of_node, "addr_high", &wb_io_dev->addr_high); + ret += of_property_read_u32(pdev->dev.of_node, "rd_data", &wb_io_dev->rd_data); + ret += of_property_read_u32(pdev->dev.of_node, "opt_ctl", &wb_io_dev->opt_ctl); + } else { + + wb_io_dev->indirect_addr = 0; + } + if (ret != 0) { + dev_err(&pdev->dev, "Failed to get dts config, ret:%d.\n", ret); + return -ENXIO; + } + } else { + if (pdev->dev.platform_data == NULL) { + dev_err(&pdev->dev, "Failed to get platform data config.\n"); + return -ENXIO; + } + io_dev_device = pdev->dev.platform_data; + wb_io_dev->name = io_dev_device->io_dev_name; + wb_io_dev->io_base = io_dev_device->io_base; + wb_io_dev->io_len = io_dev_device->io_len; + wb_io_dev->indirect_addr = io_dev_device->indirect_addr; + if (wb_io_dev->indirect_addr == 1) { + wb_io_dev->wr_data = io_dev_device->wr_data; + wb_io_dev->addr_low = io_dev_device->addr_low; + wb_io_dev->addr_high = io_dev_device->addr_high; + wb_io_dev->rd_data = io_dev_device->rd_data; + wb_io_dev->opt_ctl = io_dev_device->opt_ctl; + } + } + + IO_DEV_DEBUG_VERBOSE("name:%s, io base:0x%x, io len:0x%x, addressing type:%s.\n", + wb_io_dev->name, wb_io_dev->io_base, wb_io_dev->io_len, + wb_io_dev->indirect_addr ? "indirect" : "direct"); + + misc = &wb_io_dev->misc; + misc->minor = MISC_DYNAMIC_MINOR; + misc->name = wb_io_dev->name; + misc->fops = &io_dev_fops; + misc->mode = 0666; + if (misc_register(misc) != 0) { + dev_err(&pdev->dev, "Failed to register %s device.\n", misc->name); + return -ENXIO; + } + if (misc->minor >= MAX_IO_DEV_NUM) { + dev_err(&pdev->dev, "Error: device minor[%d] more than max io device num[%d].\n", + misc->minor, MAX_IO_DEV_NUM); + misc_deregister(misc); + return -EINVAL; + } + io_dev_arry[misc->minor] = wb_io_dev; + dev_info(&pdev->dev, "register %s device [0x%x][0x%x] with minor %d using %s addressing success.\n", + misc->name, wb_io_dev->io_base, wb_io_dev->io_len, misc->minor, + wb_io_dev->indirect_addr ? "indirect" : "direct"); + + return 0; +} + +static int io_dev_remove(struct platform_device *pdev) +{ + int i; + + for (i = 0; i < MAX_IO_DEV_NUM ; i++) { + if (io_dev_arry[i] != NULL) { + misc_deregister(&io_dev_arry[i]->misc); + io_dev_arry[i] = NULL; + } + } + + return 0; +} + +static struct of_device_id io_dev_match[] = { + { + .compatible = "wb-io-dev", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, io_dev_match); + +static struct platform_driver wb_io_dev_driver = { + .probe = io_dev_probe, + .remove = io_dev_remove, + .driver = { + .owner = THIS_MODULE, + .name = PROXY_NAME, + .of_match_table = io_dev_match, + }, +}; + +static int __init wb_io_dev_init(void) +{ + return platform_driver_register(&wb_io_dev_driver); +} + +static void __exit wb_io_dev_exit(void) +{ + platform_driver_unregister(&wb_io_dev_driver); +} + +module_init(wb_io_dev_init); +module_exit(wb_io_dev_exit); +MODULE_DESCRIPTION("IO device driver"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("support"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_io_dev.h b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_io_dev.h new file mode 100644 index 000000000000..3a1a10f0f20c --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_io_dev.h @@ -0,0 +1,21 @@ +#ifndef __WB_IO_DEV_H__ +#define __WB_IO_DEV_H__ +#include + +#define mem_clear(data, size) memset((data), 0, (size)) +#define IO_DEV_NAME_MAX_LEN (64) + +typedef struct io_dev_device_s { + char io_dev_name[IO_DEV_NAME_MAX_LEN]; + uint32_t io_base; + uint32_t io_len; + uint32_t indirect_addr; + uint32_t wr_data; + uint32_t addr_low; + uint32_t addr_high; + uint32_t rd_data; + uint32_t opt_ctl; + int device_flag; +} io_dev_device_t; + +#endif diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_lpc_drv.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_lpc_drv.c new file mode 100644 index 000000000000..c079dc409696 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_lpc_drv.c @@ -0,0 +1,166 @@ +/* + * wb_lpc_drv.c + * ko to set lpc pcie config io addr and enable lpc + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "wb_lpc_drv.h" + +#define LPC_DRIVER_NAME "wb-lpc" +#define LPC_MAKE_PCI_IO_RANGE(__base) ((0xfc0001) | ((__base) & (0xFFFC))) + +int g_lpc_dev_debug = 0; +int g_lpc_dev_error = 0; + +module_param(g_lpc_dev_debug, int, S_IRUGO | S_IWUSR); +module_param(g_lpc_dev_error, int, S_IRUGO | S_IWUSR); + +#define LPC_DEV_DEBUG_VERBOSE(fmt, args...) do { \ + if (g_lpc_dev_debug) { \ + printk(KERN_INFO "[LPC_DEV][VER][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +#define LPC_DEV_DEBUG_ERROR(fmt, args...) do { \ + if (g_lpc_dev_error) { \ + printk(KERN_ERR "[LPC_DEV][ERR][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +typedef struct wb_lpc_dev_s { + const char *lpc_io_name; + uint32_t domain; + uint32_t bus; + uint32_t slot; + uint32_t fn; + uint32_t lpc_io_base; + uint32_t lpc_io_size; + uint32_t lpc_gen_dec; +} wb_lpc_dev_t; + +static int wb_lpc_probe(struct platform_device *pdev) +{ + int ret, devfn; + wb_lpc_dev_t *wb_lpc_dev; + struct pci_dev *pci_dev; + lpc_drv_device_t *lpc_drv_device; + + wb_lpc_dev = devm_kzalloc(&pdev->dev, sizeof(wb_lpc_dev_t), GFP_KERNEL); + if (!wb_lpc_dev) { + dev_err(&pdev->dev, "devm_kzalloc failed.\n"); + ret = -ENOMEM; + return ret; + } + + if (pdev->dev.of_node) { + ret = 0; + ret += of_property_read_string(pdev->dev.of_node, "lpc_io_name", &wb_lpc_dev->lpc_io_name); + ret += of_property_read_u32(pdev->dev.of_node, "pci_domain", &wb_lpc_dev->domain); + ret += of_property_read_u32(pdev->dev.of_node, "pci_bus", &wb_lpc_dev->bus); + ret += of_property_read_u32(pdev->dev.of_node, "pci_slot", &wb_lpc_dev->slot); + ret += of_property_read_u32(pdev->dev.of_node, "pci_fn", &wb_lpc_dev->fn); + ret += of_property_read_u32(pdev->dev.of_node, "lpc_io_base", &wb_lpc_dev->lpc_io_base); + ret += of_property_read_u32(pdev->dev.of_node, "lpc_io_size", &wb_lpc_dev->lpc_io_size); + ret += of_property_read_u32(pdev->dev.of_node, "lpc_gen_dec", &wb_lpc_dev->lpc_gen_dec); + if (ret != 0) { + dev_err(&pdev->dev, "Failed to get dts config, ret:%d.\n", ret); + return -ENXIO; + } + } else { + if (pdev->dev.platform_data == NULL) { + dev_err(&pdev->dev, "Failed to get platform data config.\n"); + return -ENXIO; + } + lpc_drv_device = pdev->dev.platform_data; + wb_lpc_dev->lpc_io_name = lpc_drv_device->lpc_io_name; + wb_lpc_dev->domain = lpc_drv_device->pci_domain; + wb_lpc_dev->bus = lpc_drv_device->pci_bus; + wb_lpc_dev->slot = lpc_drv_device->pci_slot; + wb_lpc_dev->fn = lpc_drv_device->pci_fn; + wb_lpc_dev->lpc_io_base = lpc_drv_device->lpc_io_base; + wb_lpc_dev->lpc_io_size = lpc_drv_device->lpc_io_size; + wb_lpc_dev->lpc_gen_dec = lpc_drv_device->lpc_gen_dec; + } + + LPC_DEV_DEBUG_VERBOSE("domain:0x%04x, bus:0x%02x, slot:0x%02x, fn:%u\n", + wb_lpc_dev->domain,wb_lpc_dev->bus, wb_lpc_dev->slot, wb_lpc_dev->fn); + LPC_DEV_DEBUG_VERBOSE("lpc_io_name:%s, lpc_io_base:0x%x, lpc_io_size:%u, lpc_gen_dec:0x%x.\n", + wb_lpc_dev->lpc_io_name, wb_lpc_dev->lpc_io_base, wb_lpc_dev->lpc_io_size, wb_lpc_dev->lpc_gen_dec); + + devfn = PCI_DEVFN(wb_lpc_dev->slot, wb_lpc_dev->fn); + pci_dev = pci_get_domain_bus_and_slot(wb_lpc_dev->domain, wb_lpc_dev->bus, devfn); + if (pci_dev == NULL) { + dev_err(&pdev->dev, "Failed to find pci_dev, domain:0x%04x, bus:0x%02x, devfn:0x%x\n", + wb_lpc_dev->domain, wb_lpc_dev->bus, devfn); + return -ENXIO; + } + + pci_write_config_dword(pci_dev, wb_lpc_dev->lpc_gen_dec, LPC_MAKE_PCI_IO_RANGE(wb_lpc_dev->lpc_io_base)); + if (!request_region(wb_lpc_dev->lpc_io_base, wb_lpc_dev->lpc_io_size, wb_lpc_dev->lpc_io_name)) { + dev_err(&pdev->dev, "Failed to request_region [0x%x][0x%x].\n", wb_lpc_dev->lpc_io_base, wb_lpc_dev->lpc_io_size); + return -EBUSY; + } + + platform_set_drvdata(pdev, wb_lpc_dev); + + dev_info(&pdev->dev, "lpc request_region [0x%x][0x%x] success.\n", wb_lpc_dev->lpc_io_base, wb_lpc_dev->lpc_io_size); + + return 0; +} + +static int wb_lpc_remove(struct platform_device *pdev) +{ + wb_lpc_dev_t *wb_lpc_dev; + + wb_lpc_dev = platform_get_drvdata(pdev); + if (wb_lpc_dev) { + release_region(wb_lpc_dev->lpc_io_base , wb_lpc_dev->lpc_io_size); + LPC_DEV_DEBUG_VERBOSE("lpc base:0x%x, len:0x%x.\n", wb_lpc_dev->lpc_io_base, wb_lpc_dev->lpc_io_size); + } + LPC_DEV_DEBUG_VERBOSE("lpc remove.\n"); + + return 0; +} + +static struct of_device_id lpc_dev_match[] = { + { + .compatible = "wb-lpc", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, lpc_dev_match); + +static struct platform_driver wb_lpc_driver = { + .probe = wb_lpc_probe, + .remove = wb_lpc_remove, + .driver = { + .owner = THIS_MODULE, + .name = LPC_DRIVER_NAME, + .of_match_table = lpc_dev_match, + }, +}; + +static int __init wb_lpc_init(void) +{ + return platform_driver_register(&wb_lpc_driver); +} + +static void __exit wb_lpc_exit(void) +{ + platform_driver_unregister(&wb_lpc_driver); +} + +module_init(wb_lpc_init); +module_exit(wb_lpc_exit); +MODULE_DESCRIPTION("lpc driver"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("support"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_lpc_drv.h b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_lpc_drv.h new file mode 100644 index 000000000000..76e8c32c12e9 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_lpc_drv.h @@ -0,0 +1,18 @@ +#ifndef __WB_LPC_DRV_H__ +#define __WB_LPC_DRV_H__ + +#define LPC_IO_NAME_MAX_LEN (64) + +typedef struct lpc_drv_device_s { + char lpc_io_name[LPC_IO_NAME_MAX_LEN]; + int pci_domain; + int pci_bus; + int pci_slot; + int pci_fn; + int lpc_io_base; + int lpc_io_size; + int lpc_gen_dec; + int device_flag; +} lpc_drv_device_t; + +#endif diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_mac_bsc.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_mac_bsc.c new file mode 100644 index 000000000000..1e84e65d7b11 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_mac_bsc.c @@ -0,0 +1,660 @@ +/* + * wb_mac_th3.c - A driver for control wb_mac_th3 base on wb_mac.c + * + * Copyright (c) 1998, 1999 Frodo Looijaard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define mem_clear(data, size) memset((data), 0, (size)) + +#define MAC_TEMP_INVALID (99999999) + +#define MAC_SIZE (256) +#define MAC_TEMP_NUM (16) + +#define MAC_ID_REG (0x02000000) + +typedef enum { + DBG_START, + DBG_VERBOSE, + DBG_KEY, + DBG_WARN, + DBG_ERROR, + DBG_END, +} dbg_level_t; + +typedef enum{ + MAC_TYPE_START, + TD4_X9 = 0xb780, + TD4_X9_8 = 0xb788, + TH3 = 0xb980, + TD3 = 0xb870, + TD4 = 0xb880, + TH4 = 0xb990, + MAC_TYPE_END, +} mac_type; + +typedef struct sensor_regs_s { + int id; + u32 reg; +} sensor_reg_t; + +typedef struct mac_temp_regs_s { + int mac_type; + sensor_reg_t sensor_reg[MAC_TEMP_NUM]; +} mac_temp_reg_t; + +typedef enum { + MAC_TEMP_START, + MAC_TEMP_INDEX1, + MAC_TEMP_INDEX2, + MAC_TEMP_INDEX3, + MAC_TEMP_INDEX4, + MAC_TEMP_INDEX5, + MAC_TEMP_INDEX6, + MAC_TEMP_INDEX7, + MAC_TEMP_INDEX8, + MAC_TEMP_INDEX9, + MAC_TEMP_INDEX10, + MAC_TEMP_INDEX11, + MAC_TEMP_INDEX12, + MAC_TEMP_INDEX13, + MAC_TEMP_INDEX14, + MAC_TEMP_INDEX15, + MAC_TEMP_END, +} mac_hwmon_index; + +static mac_temp_reg_t mac_temp_reg[] = { + { + /* TD3 */ + .mac_type = TD3, + .sensor_reg = { + {.id = MAC_TEMP_INDEX1, .reg = 0x02004700}, + {.id = MAC_TEMP_INDEX2, .reg = 0x02004800}, + {.id = MAC_TEMP_INDEX3, .reg = 0x02004900}, + {.id = MAC_TEMP_INDEX4, .reg = 0x02004a00}, + {.id = MAC_TEMP_INDEX5, .reg = 0x02004b00}, + {.id = MAC_TEMP_INDEX6, .reg = 0x02004c00}, + {.id = MAC_TEMP_INDEX7, .reg = 0x02004d00}, + {.id = MAC_TEMP_INDEX8, .reg = 0x02004e00}, + {.id = MAC_TEMP_INDEX9, .reg = 0x02005200}, + {.id = MAC_TEMP_INDEX10, .reg = 0x02005100}, + {.id = MAC_TEMP_INDEX11, .reg = 0x02005000}, + {.id = MAC_TEMP_INDEX12, .reg = 0x02004f00}, + }, + }, + { + /* TD4 */ + .mac_type = TD4, + .sensor_reg = { + {.id = MAC_TEMP_INDEX1, .reg = 0x02004900}, + {.id = MAC_TEMP_INDEX2, .reg = 0x02004b00}, + {.id = MAC_TEMP_INDEX3, .reg = 0x02004d00}, + {.id = MAC_TEMP_INDEX4, .reg = 0x02004f00}, + {.id = MAC_TEMP_INDEX5, .reg = 0x02005100}, + {.id = MAC_TEMP_INDEX6, .reg = 0x02005300}, + {.id = MAC_TEMP_INDEX7, .reg = 0x02005500}, + {.id = MAC_TEMP_INDEX8, .reg = 0x02005700}, + {.id = MAC_TEMP_INDEX9, .reg = 0x02005900}, + {.id = MAC_TEMP_INDEX10, .reg = 0x02005b00}, + {.id = MAC_TEMP_INDEX11, .reg = 0x02005d00}, + {.id = MAC_TEMP_INDEX12, .reg = 0x02005f00}, + {.id = MAC_TEMP_INDEX13, .reg = 0x02006100}, + {.id = MAC_TEMP_INDEX14, .reg = 0x02006300}, + {.id = MAC_TEMP_INDEX15, .reg = 0x02006500}, + }, + }, + { + /* TD4_X9 */ + .mac_type = TD4_X9, + .sensor_reg = { + {.id = MAC_TEMP_INDEX1, .reg = 0x02005a00}, + {.id = MAC_TEMP_INDEX2, .reg = 0x02005c00}, + {.id = MAC_TEMP_INDEX3, .reg = 0x02005e00}, + {.id = MAC_TEMP_INDEX4, .reg = 0x02006000}, + {.id = MAC_TEMP_INDEX5, .reg = 0x02006200}, + {.id = MAC_TEMP_INDEX6, .reg = 0x02006400}, + {.id = MAC_TEMP_INDEX7, .reg = 0x02006600}, + {.id = MAC_TEMP_INDEX8, .reg = 0x02006800}, + {.id = MAC_TEMP_INDEX9, .reg = 0x02006a00}, + }, + }, + { + /* TD4_X9_8 */ + .mac_type = TD4_X9_8, + .sensor_reg = { + {.id = MAC_TEMP_INDEX1, .reg = 0x02005a00}, + {.id = MAC_TEMP_INDEX2, .reg = 0x02005c00}, + {.id = MAC_TEMP_INDEX3, .reg = 0x02005e00}, + {.id = MAC_TEMP_INDEX4, .reg = 0x02006000}, + {.id = MAC_TEMP_INDEX5, .reg = 0x02006200}, + {.id = MAC_TEMP_INDEX6, .reg = 0x02006400}, + {.id = MAC_TEMP_INDEX7, .reg = 0x02006600}, + {.id = MAC_TEMP_INDEX8, .reg = 0x02006800}, + {.id = MAC_TEMP_INDEX9, .reg = 0x02006a00}, + }, + }, + { + /* TH3 */ + .mac_type = TH3, + .sensor_reg = { + {.id = MAC_TEMP_INDEX1, .reg = 0x02004a00}, + {.id = MAC_TEMP_INDEX2, .reg = 0x02004b00}, + {.id = MAC_TEMP_INDEX3, .reg = 0x02004c00}, + {.id = MAC_TEMP_INDEX4, .reg = 0x02004d00}, + {.id = MAC_TEMP_INDEX5, .reg = 0x02004e00}, + {.id = MAC_TEMP_INDEX6, .reg = 0x02004f00}, + {.id = MAC_TEMP_INDEX7, .reg = 0x02005000}, + {.id = MAC_TEMP_INDEX8, .reg = 0x02005100}, + {.id = MAC_TEMP_INDEX9, .reg = 0x02005200}, + {.id = MAC_TEMP_INDEX10, .reg = 0x02005300}, + {.id = MAC_TEMP_INDEX11, .reg = 0x02005400}, + {.id = MAC_TEMP_INDEX12, .reg = 0x02005500}, + {.id = MAC_TEMP_INDEX13, .reg = 0x02005600}, + {.id = MAC_TEMP_INDEX14, .reg = 0x02005700}, + {.id = MAC_TEMP_INDEX15, .reg = 0x02005800}, + }, + }, + { + /* TH4 */ + .mac_type = TH4, + .sensor_reg = { + {.id = MAC_TEMP_INDEX1, .reg = 0x0201d800}, + {.id = MAC_TEMP_INDEX2, .reg = 0x0201e000}, + {.id = MAC_TEMP_INDEX3, .reg = 0x0201e800}, + {.id = MAC_TEMP_INDEX4, .reg = 0x0201f000}, + {.id = MAC_TEMP_INDEX5, .reg = 0x0201f800}, + {.id = MAC_TEMP_INDEX6, .reg = 0x02020000}, + {.id = MAC_TEMP_INDEX7, .reg = 0x02020800}, + {.id = MAC_TEMP_INDEX8, .reg = 0x02021000}, + {.id = MAC_TEMP_INDEX9, .reg = 0x02021800}, + {.id = MAC_TEMP_INDEX10, .reg = 0x02022000}, + {.id = MAC_TEMP_INDEX11, .reg = 0x02022800}, + {.id = MAC_TEMP_INDEX12, .reg = 0x02023000}, + {.id = MAC_TEMP_INDEX13, .reg = 0x02023800}, + {.id = MAC_TEMP_INDEX14, .reg = 0x02024000}, + {.id = MAC_TEMP_INDEX15, .reg = 0x02024800}, + }, + }, +}; + +static int debuglevel = 0; +module_param(debuglevel, int, S_IRUGO | S_IWUSR); + +static int mac_pcie_id = MAC_TYPE_START; +module_param(mac_pcie_id, int, S_IRUGO | S_IWUSR); + +#define DBG_DEBUG(fmt, arg...) do { \ + if ( debuglevel > DBG_START && debuglevel < DBG_ERROR) { \ + printk(KERN_INFO "[DEBUG]:<%s, %d>:"fmt, __FUNCTION__, __LINE__, ##arg); \ + } else if ( debuglevel >= DBG_ERROR ) { \ + printk(KERN_ERR "[DEBUG]:<%s, %d>:"fmt, __FUNCTION__, __LINE__, ##arg); \ + } else { } \ +} while (0) + +#define DBG_ERROR(fmt, arg...) do { \ + if ( debuglevel > DBG_START) { \ + printk(KERN_ERR "[ERROR]:<%s, %d>:"fmt, __FUNCTION__, __LINE__, ##arg); \ + } \ + } while (0) + +struct mac_data { + struct i2c_client *client; + struct device *hwmon_dev; + struct mutex update_lock; + u8 data[MAC_SIZE]; /* Register value */ +}; + +static int wb_i2c_read_one_time(struct i2c_client *client, u8 *recv_buf, int size) +{ + struct i2c_msg msgs[2]; + int ret = 0; + + if ((client == NULL) || (recv_buf == NULL)) { + DBG_DEBUG("i2c_client || recv_buf = NULL\r\n"); + return -1; + } + + mem_clear(msgs, sizeof(msgs)); + + msgs[0].buf = recv_buf; + msgs[0].len = size; + msgs[0].addr = client->addr; + msgs[0].flags |= I2C_M_RD; + + ret = i2c_transfer(client->adapter, msgs, 1); + if (ret < 0) { + return ret; + } + DBG_DEBUG("i2c_transfer, dev_addr 0x%x, size %d.\n", client->addr, size); + + return 0; +} + +static int wb_i2c_write_one_time(struct i2c_client *client, u8 *write_buf, int size) +{ + struct i2c_msg msgs[2]; + int ret = 0; + + if ((client == NULL) || (write_buf == NULL)) { + DBG_DEBUG("i2c_client || write_buf = NULL\r\n"); + return -1; + } + + if ((size <= 0)) { + DBG_DEBUG("size invalid, size %d\n", size); + return -1; + } + + mem_clear(msgs, sizeof(msgs)); + + msgs[0].len = size; + msgs[0].buf = write_buf; + msgs[0].addr = client->addr; + + ret = i2c_transfer(client->adapter, msgs, 1); + if (ret < 0) { + return ret; + } + DBG_DEBUG("i2c_transfer, dev_addr 0x%x, size %d\n", client->addr, size); + + return 0; +} + +static u8 step2_buf1[8] = {0x03, 0x21, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00}; +static u8 step2_buf2[8] = {0x03, 0x21, 0x04, 0x0c, 0x2c, 0x38, 0x02, 0x00}; +static u8 step2_buf3[8] = {0x03, 0x21, 0x04, 0x10, 0x02, 0x00, 0x4a, 0x00}; +static u8 step2_buf4[8] = {0x03, 0x21, 0x04, 0x00, 0x00, 0x00, 0x00, 0x01}; +static u8 step2_buf5[4] = {0x03, 0x21, 0x04, 0x08}; +static u8 step2_buf6[4] = {0x03, 0x21, 0x04, 0x10}; + +static int getmac_register(struct i2c_client *client, u32 index, int *reg_value) +{ + int i; + int ret = 0; + int value = 0; + unsigned char read_buf[8]; + + if (index == 0) { + DBG_ERROR("invalid index\n"); + return -1; + } + + step2_buf3[7] = index & 0xff; + step2_buf3[6] = (index >> 8) & 0xff; + step2_buf3[5] = (index >> 16) & 0xff; + step2_buf3[4] = (index >> 24) & 0xff; + + ret = wb_i2c_write_one_time(client, step2_buf1, 8); + if (ret < 0) { + DBG_ERROR("write step2_buf1 failed, ret = %d\n", ret); + } + ret = wb_i2c_write_one_time(client, step2_buf2, 8); + if (ret < 0) { + DBG_ERROR("write step2_buf2 failed, ret = %d\n", ret); + } + ret = wb_i2c_write_one_time(client, step2_buf3, 8); + if (ret < 0) { + DBG_ERROR("write step2_buf3 failed, ret = %d\n", ret); + } + ret = wb_i2c_write_one_time(client, step2_buf4, 8); + if (ret < 0) { + DBG_ERROR("write step2_buf4 failed, ret = %d\n", ret); + } + + ret = wb_i2c_write_one_time(client, step2_buf5, 4); + if (ret < 0) { + DBG_ERROR("write step2_buf5 failed, ret = %d\n", ret); + } + ret = wb_i2c_read_one_time(client, read_buf, 4); + if (ret < 0) { + DBG_ERROR("read failed, ret = %d\n", ret); + } + for (i = 0; i < 4; i++) { + DBG_DEBUG("read_buf[%d] = 0x%x \n", i, read_buf[i]); + } + + ret = wb_i2c_write_one_time(client, step2_buf6, 4); + if (ret < 0) { + DBG_ERROR("write step2_buf6 failed, ret = %d\n", ret); + } + + ret = wb_i2c_read_one_time(client, read_buf, 4); + if (ret < 0) { + DBG_ERROR("read failed, ret = %d\n", ret); + return ret; + } + + value = (read_buf[0] << 24)| (read_buf[1] << 16) | (read_buf[2] << 8) | read_buf[3]; + *reg_value = value; + + return ret; +} + +static int mac_calcute(u32 reg, int *temp) +{ + int ret = 0; + u32 tmp = 0; + + switch(mac_pcie_id) { + case TD3: + case TH3: + tmp = reg & 0x3ff; + *temp = 434100 - (tmp * 535); + break; + case TD4: + case TH4: + case TD4_X9: + case TD4_X9_8: + tmp = reg & 0x7ff; + *temp = (356070 - (tmp * 237)); + break; + default: + ret = -1; + DBG_ERROR("read failed, ret = %d\n", ret); + break; + } + + if ((*temp / 1000 < -70) || (*temp / 1000 > 200)) { + ret = -1; + DBG_ERROR("mac temp invalid, temp = %d\n", *temp ); + } + + return ret; +} + +static int find_reg_type(int type, int *type_index) +{ + int i; + int size; + + size = ARRAY_SIZE(mac_temp_reg); + for (i = 0; i < size; i++) { + if (mac_temp_reg[i].mac_type == type) { + *type_index = i; + return 0; + } + } + + return -1; +} + +static sensor_reg_t * find_reg_offset(int type, int index) +{ + int i; + int type_index; + int ret; + + ret = find_reg_type(type, &type_index); + if (ret < 0) { + DBG_ERROR("find_reg_type failed, ret = %d\n", ret); + return NULL; + } + + for (i = 0; i < MAC_TEMP_NUM; i++) { + if (mac_temp_reg[type_index].sensor_reg[i].id == index) { + return &(mac_temp_reg[type_index].sensor_reg[i]); + } + } + + return NULL; +} + +static int get_mactemp(struct i2c_client *client, int index, int *temp) +{ + int ret; + int reg_value; + + if (index == 0) { + DBG_ERROR("invalid index\n"); + return -1; + } + + ret = getmac_register(client, index, ®_value); + if (ret < 0) { + DBG_ERROR("getmac_register failed, ret = %d\n", ret); + return ret; + } + DBG_DEBUG("reg_value = 0x%x \n", reg_value); + + ret = mac_calcute(reg_value, temp); + if (ret < 0) { + DBG_ERROR("mac_calcute failed, ret = %d\n", ret); + return ret; + } + + return 0; +} + +static ssize_t show_mac_temp(struct device *dev, struct device_attribute *da, char *buf) +{ + struct mac_data *data = dev_get_drvdata(dev); + struct i2c_client *client = data->client; + u32 index_value = to_sensor_dev_attr_2(da)->index; + sensor_reg_t *t; + int result = 0; + int temp = -MAC_TEMP_INVALID; + + mutex_lock(&data->update_lock); + t = find_reg_offset(mac_pcie_id, index_value); + if (t == NULL) { + temp = -MAC_TEMP_INVALID; + DBG_ERROR("find_reg_offset failed, mac_pcie_id = %d, index_value = %d\n", mac_pcie_id, index_value); + } else { + result = get_mactemp(client, t->reg, &temp); + if (result < 0) { + temp = -MAC_TEMP_INVALID; + DBG_ERROR("get_mactemp failed, ret = %d\n", result); + } + } + + mutex_unlock(&data->update_lock); + return snprintf(buf, MAC_SIZE, "%d\n", temp); +} + +static ssize_t show_mac_max_temp(struct device *dev, struct device_attribute *da, char *buf) +{ + struct mac_data *data = dev_get_drvdata(dev); + struct i2c_client *client = data->client; + int i; + int result; + int temp = -MAC_TEMP_INVALID; + int type_index; + int tmp; + + mutex_lock(&data->update_lock); + + result = find_reg_type(mac_pcie_id, &type_index); + if (result < 0) { + DBG_ERROR("find_reg_type failed, ret = %d\n", result); + goto exit; + } + + for (i = 0; i < MAC_TEMP_NUM; i++) { + result = get_mactemp(client, mac_temp_reg[type_index].sensor_reg[i].reg, &tmp); + if (result < 0) { + DBG_ERROR("get_mactemp failed, ret = %d\n", result); + tmp = -MAC_TEMP_INVALID; + } + + temp = (temp > tmp) ? temp : tmp; + } + +exit: + mutex_unlock(&data->update_lock); + return snprintf(buf, MAC_SIZE, "%d\n", temp); +} + +static int mac_bsc_init(struct i2c_client *client) +{ + int ret; + int reg_value; + int mac_id = 0; + + ret = getmac_register(client, MAC_ID_REG, ®_value); + if (ret < 0) { + DBG_ERROR("getmac_register failed, ret = %d\n", ret); + return ret; + } + + DBG_DEBUG("reg_value = 0x%x \n", reg_value); + mac_id = reg_value & 0xffff; + return mac_id; +} + +static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, show_mac_temp, NULL, MAC_TEMP_INDEX1); +static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, show_mac_temp, NULL, MAC_TEMP_INDEX2); +static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, show_mac_temp, NULL, MAC_TEMP_INDEX3); +static SENSOR_DEVICE_ATTR(temp4_input, S_IRUGO, show_mac_temp, NULL, MAC_TEMP_INDEX4); +static SENSOR_DEVICE_ATTR(temp5_input, S_IRUGO, show_mac_temp, NULL, MAC_TEMP_INDEX5); +static SENSOR_DEVICE_ATTR(temp6_input, S_IRUGO, show_mac_temp, NULL, MAC_TEMP_INDEX6); +static SENSOR_DEVICE_ATTR(temp7_input, S_IRUGO, show_mac_temp, NULL, MAC_TEMP_INDEX7); +static SENSOR_DEVICE_ATTR(temp8_input, S_IRUGO, show_mac_temp, NULL, MAC_TEMP_INDEX8); +static SENSOR_DEVICE_ATTR(temp9_input, S_IRUGO, show_mac_temp, NULL, MAC_TEMP_INDEX9); +static SENSOR_DEVICE_ATTR(temp10_input, S_IRUGO, show_mac_temp, NULL, MAC_TEMP_INDEX10); +static SENSOR_DEVICE_ATTR(temp11_input, S_IRUGO, show_mac_temp, NULL, MAC_TEMP_INDEX11); +static SENSOR_DEVICE_ATTR(temp12_input, S_IRUGO, show_mac_temp, NULL, MAC_TEMP_INDEX12); +static SENSOR_DEVICE_ATTR(temp13_input, S_IRUGO, show_mac_temp, NULL, MAC_TEMP_INDEX13); +static SENSOR_DEVICE_ATTR(temp14_input, S_IRUGO, show_mac_temp, NULL, MAC_TEMP_INDEX14); +static SENSOR_DEVICE_ATTR(temp15_input, S_IRUGO, show_mac_temp, NULL, MAC_TEMP_INDEX15); +static SENSOR_DEVICE_ATTR(temp99_input, S_IRUGO, show_mac_max_temp, NULL, 0); + +static struct attribute *mac_hwmon_attrs[] = { + &sensor_dev_attr_temp1_input.dev_attr.attr, + &sensor_dev_attr_temp2_input.dev_attr.attr, + &sensor_dev_attr_temp3_input.dev_attr.attr, + &sensor_dev_attr_temp4_input.dev_attr.attr, + &sensor_dev_attr_temp5_input.dev_attr.attr, + &sensor_dev_attr_temp6_input.dev_attr.attr, + &sensor_dev_attr_temp7_input.dev_attr.attr, + &sensor_dev_attr_temp8_input.dev_attr.attr, + &sensor_dev_attr_temp9_input.dev_attr.attr, + &sensor_dev_attr_temp10_input.dev_attr.attr, + &sensor_dev_attr_temp11_input.dev_attr.attr, + &sensor_dev_attr_temp12_input.dev_attr.attr, + &sensor_dev_attr_temp13_input.dev_attr.attr, + &sensor_dev_attr_temp14_input.dev_attr.attr, + &sensor_dev_attr_temp15_input.dev_attr.attr, + &sensor_dev_attr_temp99_input.dev_attr.attr, + NULL +}; +ATTRIBUTE_GROUPS(mac_hwmon); + +static int init_bcs_command(int mac_type) { + int ret; + + ret = 0; + switch (mac_type) { + case TD3: + step2_buf2[5] = 0x38; + break; + case TH3: + case TH4: + case TD4: + case TD4_X9: + case TD4_X9_8: + step2_buf2[5] = 0x40; + break; + default: + ret = -1; + break; + } + return ret; +} + +static int mac_probe(struct i2c_client *client, const struct i2c_device_id *id) +{ + struct mac_data *data; + int mac_type; + int ret; + + mac_type = id->driver_data; + mac_pcie_id = mac_type; + if (init_bcs_command(mac_type) < 0) { + DBG_ERROR("mactype[%x] not support \n", mac_type); + return -1; + }; + + if (mac_type == TD4) { + ret = mac_bsc_init(client); + if (ret < 0) { + DBG_ERROR("mac_bsc_init failed, ret = %d\n", ret); + return -1; + } + mac_type = ret; + mac_pcie_id = mac_type; + } + + DBG_DEBUG("=========mac_probe(%x)===========\n",client->addr); + DBG_DEBUG("mac_type: %x\n", mac_type); + data = devm_kzalloc(&client->dev, sizeof(struct mac_data), GFP_KERNEL); + if (!data) { + return -ENOMEM; + } + + data->client = client; + i2c_set_clientdata(client, data); + mutex_init(&data->update_lock); + + data->hwmon_dev = hwmon_device_register_with_groups(&client->dev, client->name, data, mac_hwmon_groups); + if (IS_ERR(data->hwmon_dev)) { + return PTR_ERR(data->hwmon_dev); + } + + return 0; +} + +static int mac_remove(struct i2c_client *client) +{ + struct mac_data *data = i2c_get_clientdata(client); + hwmon_device_unregister(data->hwmon_dev); + return 0; +} + +static const struct i2c_device_id mac_id[] = { + { "wb_mac_bsc_td3", TD3 }, + { "wb_mac_bsc_td4", TD4 }, + { "wb_mac_bsc_th3", TH3 }, + { "wb_mac_bsc_th4", TH4 }, + {} +}; +MODULE_DEVICE_TABLE(i2c, mac_id); + +static struct i2c_driver wb_mac_bsc_driver = { + .driver = { + .name = "wb_mac_bsc", + }, + .probe = mac_probe, + .remove = mac_remove, + .id_table = mac_id, +}; + +module_i2c_driver(wb_mac_bsc_driver); + +MODULE_AUTHOR("support"); +MODULE_DESCRIPTION("mac bsc driver"); +MODULE_LICENSE("GPL"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_optoe.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_optoe.c new file mode 100644 index 000000000000..c09162368ad0 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_optoe.c @@ -0,0 +1,1192 @@ +/* + * optoe.c - A driver to read and write the EEPROM on optical transceivers + * (SFP, QSFP and similar I2C based devices) + * + * Copyright (C) 2014 Cumulus networks Inc. + * Copyright (C) 2017 Finisar Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Freeoftware Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +/* + * Description: + * a) Optical transceiver EEPROM read/write transactions are just like + * the at24 eeproms managed by the at24.c i2c driver + * b) The register/memory layout is up to 256 128 byte pages defined by + * a "pages valid" register and switched via a "page select" + * register as explained in below diagram. + * c) 256 bytes are mapped at a time. 'Lower page 00h' is the first 128 + * bytes of address space, and always references the same + * location, independent of the page select register. + * All mapped pages are mapped into the upper 128 bytes + * (offset 128-255) of the i2c address. + * d) Devices with one I2C address (eg QSFP) use I2C address 0x50 + * (A0h in the spec), and map all pages in the upper 128 bytes + * of that address. + * e) Devices with two I2C addresses (eg SFP) have 256 bytes of data + * at I2C address 0x50, and 256 bytes of data at I2C address + * 0x51 (A2h in the spec). Page selection and paged access + * only apply to this second I2C address (0x51). + * e) The address space is presented, by the driver, as a linear + * address space. For devices with one I2C client at address + * 0x50 (eg QSFP), offset 0-127 are in the lower + * half of address 50/A0h/client[0]. Offset 128-255 are in + * page 0, 256-383 are page 1, etc. More generally, offset + * 'n' resides in page (n/128)-1. ('page -1' is the lower + * half, offset 0-127). + * f) For devices with two I2C clients at address 0x50 and 0x51 (eg SFP), + * the address space places offset 0-127 in the lower + * half of 50/A0/client[0], offset 128-255 in the upper + * half. Offset 256-383 is in the lower half of 51/A2/client[1]. + * Offset 384-511 is in page 0, in the upper half of 51/A2/... + * Offset 512-639 is in page 1, in the upper half of 51/A2/... + * Offset 'n' is in page (n/128)-3 (for n > 383) + * + * One I2c addressed (eg QSFP) Memory Map + * + * 2-Wire Serial Address: 1010000x + * + * Lower Page 00h (128 bytes) + * ===================== + * | | + * | | + * | | + * | | + * | | + * | | + * | | + * | | + * | | + * | | + * |Page Select Byte(127)| + * ===================== + * | + * | + * | + * | + * V + * ------------------------------------------------------------ + * | | | | + * | | | | + * | | | | + * | | | | + * | | | | + * | | | | + * | | | | + * | | | | + * | | | | + * V V V V + * ------------ -------------- --------------- -------------- + * | | | | | | | | + * | Upper | | Upper | | Upper | | Upper | + * | Page 00h | | Page 01h | | Page 02h | | Page 03h | + * | | | (Optional) | | (Optional) | | (Optional | + * | | | | | | | for Cable | + * | | | | | | | Assemblies) | + * | ID | | AST | | User | | | + * | Fields | | Table | | EEPROM Data | | | + * | | | | | | | | + * | | | | | | | | + * | | | | | | | | + * ------------ -------------- --------------- -------------- + * + * The SFF 8436 (QSFP) spec only defines the 4 pages described above. + * In anticipation of future applications and devices, this driver + * supports access to the full architected range, 256 pages. + * + * The CMIS (Common Management Interface Specification) defines use of + * considerably more pages (at least to page 0xAF), which this driver + * supports. + * + * NOTE: This version of the driver ONLY SUPPORTS BANK 0 PAGES on CMIS + * devices. + * + **/ + +/* #define DEBUG 1 */ + +#undef EEPROM_CLASS +#ifdef CONFIG_EEPROM_CLASS +#define EEPROM_CLASS +#endif +#ifdef CONFIG_EEPROM_CLASS_MODULE +#define EEPROM_CLASS +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define mem_clear(data, size) memset((data), 0, (size)) +#ifdef EEPROM_CLASS +#include +#endif + +#include + +/* The maximum length of a port name */ +#define MAX_PORT_NAME_LEN 20 + +struct optoe_platform_data { + u32 byte_len; /* size (sum of all addr) */ + u16 page_size; /* for writes */ + u8 flags; + void *dummy1; /* backward compatibility */ + void *dummy2; /* backward compatibility */ + +#ifdef EEPROM_CLASS + struct eeprom_platform_data *eeprom_data; +#endif + char port_name[MAX_PORT_NAME_LEN]; +}; + +/* fundamental unit of addressing for EEPROM */ +#define OPTOE_PAGE_SIZE 128 +/* + * Single address devices (eg QSFP) have 256 pages, plus the unpaged + * low 128 bytes. If the device does not support paging, it is + * only 2 'pages' long. + */ +#define OPTOE_ARCH_PAGES 256 +#define ONE_ADDR_EEPROM_SIZE ((1 + OPTOE_ARCH_PAGES) * OPTOE_PAGE_SIZE) +#define ONE_ADDR_EEPROM_UNPAGED_SIZE (2 * OPTOE_PAGE_SIZE) +/* + * Dual address devices (eg SFP) have 256 pages, plus the unpaged + * low 128 bytes, plus 256 bytes at 0x50. If the device does not + * support paging, it is 4 'pages' long. + */ +#define TWO_ADDR_EEPROM_SIZE ((3 + OPTOE_ARCH_PAGES) * OPTOE_PAGE_SIZE) +#define TWO_ADDR_EEPROM_UNPAGED_SIZE (4 * OPTOE_PAGE_SIZE) +#define TWO_ADDR_NO_0X51_SIZE (2 * OPTOE_PAGE_SIZE) + +/* a few constants to find our way around the EEPROM */ +#define OPTOE_PAGE_SELECT_REG 0x7F +#define ONE_ADDR_PAGEABLE_REG 0x02 +#define QSFP_NOT_PAGEABLE (1<<2) +#define CMIS_NOT_PAGEABLE (1<<7) +#define TWO_ADDR_PAGEABLE_REG 0x40 +#define TWO_ADDR_PAGEABLE (1<<4) +#define TWO_ADDR_0X51_REG 92 +#define TWO_ADDR_0X51_SUPP (1<<6) +#define OPTOE_ID_REG 0 +#define OPTOE_READ_OP 0 +#define OPTOE_WRITE_OP 1 +#define OPTOE_EOF 0 /* used for access beyond end of device */ + +struct optoe_data { + struct optoe_platform_data chip; + int use_smbus; + char port_name[MAX_PORT_NAME_LEN]; + + /* + * Lock protects against activities from other Linux tasks, + * but not from changes by other I2C masters. + */ + struct mutex lock; + struct bin_attribute bin; + struct attribute_group attr_group; + + u8 *writebuf; + unsigned int write_max; + + unsigned int num_addresses; + +#ifdef EEPROM_CLASS + struct eeprom_device *eeprom_dev; +#endif + + /* dev_class: ONE_ADDR (QSFP) or TWO_ADDR (SFP) */ + int dev_class; + + struct i2c_client *client[]; +}; + +/* + * This parameter is to help this driver avoid blocking other drivers out + * of I2C for potentially troublesome amounts of time. With a 100 kHz I2C + * clock, one 256 byte read takes about 1/43 second which is excessive; + * but the 1/170 second it takes at 400 kHz may be quite reasonable; and + * at 1 MHz (Fm+) a 1/430 second delay could easily be invisible. + * + * This value is forced to be a power of two so that writes align on pages. + */ +static unsigned int io_limit = OPTOE_PAGE_SIZE; + +/* + * specs often allow 5 msec for a page write, sometimes 20 msec; + * it's important to recover from write timeouts. + */ +static unsigned int write_timeout = 50; + +/* + * flags to distinguish one-address (QSFP family) from two-address (SFP family) + * If the family is not known, figure it out when the device is accessed + */ +#define ONE_ADDR 1 +#define TWO_ADDR 2 +#define CMIS_ADDR 3 + +static const struct i2c_device_id optoe_ids[] = { + { "wb_optoe1", ONE_ADDR }, + { "wb_optoe2", TWO_ADDR }, + { "wb_optoe3", CMIS_ADDR }, + { "wb_sff8436", ONE_ADDR }, + { "wb_24c04", TWO_ADDR }, + { /* END OF LIST */ } +}; +MODULE_DEVICE_TABLE(i2c, optoe_ids); + +/*-------------------------------------------------------------------------*/ +/* + * This routine computes the addressing information to be used for + * a given r/w request. + * + * Task is to calculate the client (0 = i2c addr 50, 1 = i2c addr 51), + * the page, and the offset. + * + * Handles both single address (eg QSFP) and two address (eg SFP). + * For SFP, offset 0-255 are on client[0], >255 is on client[1] + * Offset 256-383 are on the lower half of client[1] + * Pages are accessible on the upper half of client[1]. + * Offset >383 are in 128 byte pages mapped into the upper half + * + * For QSFP, all offsets are on client[0] + * offset 0-127 are on the lower half of client[0] (no paging) + * Pages are accessible on the upper half of client[1]. + * Offset >127 are in 128 byte pages mapped into the upper half + * + * Callers must not read/write beyond the end of a client or a page + * without recomputing the client/page. Hence offset (within page) + * plus length must be less than or equal to 128. (Note that this + * routine does not have access to the length of the call, hence + * cannot do the validity check.) + * + * Offset within Lower Page 00h and Upper Page 00h are not recomputed + */ + +static uint8_t optoe_translate_offset(struct optoe_data *optoe, + loff_t *offset, struct i2c_client **client) +{ + unsigned int page = 0; + + *client = optoe->client[0]; + + /* if SFP style, offset > 255, shift to i2c addr 0x51 */ + if (optoe->dev_class == TWO_ADDR) { + if (*offset > 255) { + /* like QSFP, but shifted to client[1] */ + *client = optoe->client[1]; + *offset -= 256; + } + } + + /* + * if offset is in the range 0-128... + * page doesn't matter (using lower half), return 0. + * offset is already correct (don't add 128 to get to paged area) + */ + if (*offset < OPTOE_PAGE_SIZE) + return page; + + /* note, page will always be positive since *offset >= 128 */ + page = (*offset >> 7)-1; + /* 0x80 places the offset in the top half, offset is last 7 bits */ + *offset = OPTOE_PAGE_SIZE + (*offset & 0x7f); + + return page; /* note also returning client and offset */ +} + +static ssize_t optoe_eeprom_read(struct optoe_data *optoe, + struct i2c_client *client, + char *buf, unsigned int offset, size_t count) +{ + struct i2c_msg msg[2]; + u8 msgbuf[2]; + unsigned long timeout, read_time; + int status, i; + + mem_clear(msg, sizeof(msg)); + + switch (optoe->use_smbus) { + case I2C_SMBUS_I2C_BLOCK_DATA: + /*smaller eeproms can work given some SMBus extension calls */ + if (count > I2C_SMBUS_BLOCK_MAX) + count = I2C_SMBUS_BLOCK_MAX; + break; + case I2C_SMBUS_WORD_DATA: + /* Check for odd length transaction */ + count = (count == 1) ? 1 : 2; + break; + case I2C_SMBUS_BYTE_DATA: + count = 1; + break; + default: + /* + * When we have a better choice than SMBus calls, use a + * combined I2C message. Write address; then read up to + * io_limit data bytes. msgbuf is u8 and will cast to our + * needs. + */ + i = 0; + msgbuf[i++] = offset; + + msg[0].addr = client->addr; + msg[0].buf = msgbuf; + msg[0].len = i; + + msg[1].addr = client->addr; + msg[1].flags = I2C_M_RD; + msg[1].buf = buf; + msg[1].len = count; + } + + /* + * Reads fail if the previous write didn't complete yet. We may + * loop a few times until this one succeeds, waiting at least + * long enough for one entire page write to work. + */ + timeout = jiffies + msecs_to_jiffies(write_timeout); + do { + read_time = jiffies; + + switch (optoe->use_smbus) { + case I2C_SMBUS_I2C_BLOCK_DATA: + status = i2c_smbus_read_i2c_block_data(client, offset, + count, buf); + break; + case I2C_SMBUS_WORD_DATA: + status = i2c_smbus_read_word_data(client, offset); + if (status >= 0) { + buf[0] = status & 0xff; + if (count == 2) + buf[1] = status >> 8; + status = count; + } + break; + case I2C_SMBUS_BYTE_DATA: + status = i2c_smbus_read_byte_data(client, offset); + if (status >= 0) { + buf[0] = status; + status = count; + } + break; + default: + status = i2c_transfer(client->adapter, msg, 2); + if (status == 2) + status = count; + } + + dev_dbg(&client->dev, "eeprom read %zu@%d --> %d (%ld)\n", + count, offset, status, jiffies); + + if (status == count) /* happy path */ + return count; + + /* REVISIT: at HZ=100, this is sloooow */ + usleep_range(1000, 2000); + } while (time_before(read_time, timeout)); + + return -ETIMEDOUT; +} + +static ssize_t optoe_eeprom_write(struct optoe_data *optoe, + struct i2c_client *client, + const char *buf, + unsigned int offset, size_t count) +{ + struct i2c_msg msg; + ssize_t status; + unsigned long timeout, write_time; + unsigned int next_page_start; + int i = 0; + + /* write max is at most a page + * (In this driver, write_max is actually one byte!) + */ + if (count > optoe->write_max) + count = optoe->write_max; + + /* shorten count if necessary to avoid crossing page boundary */ + next_page_start = roundup(offset + 1, OPTOE_PAGE_SIZE); + if (offset + count > next_page_start) + count = next_page_start - offset; + + switch (optoe->use_smbus) { + case I2C_SMBUS_I2C_BLOCK_DATA: + /*smaller eeproms can work given some SMBus extension calls */ + if (count > I2C_SMBUS_BLOCK_MAX) + count = I2C_SMBUS_BLOCK_MAX; + break; + case I2C_SMBUS_WORD_DATA: + /* Check for odd length transaction */ + count = (count == 1) ? 1 : 2; + break; + case I2C_SMBUS_BYTE_DATA: + count = 1; + break; + default: + /* If we'll use I2C calls for I/O, set up the message */ + msg.addr = client->addr; + msg.flags = 0; + + /* msg.buf is u8 and casts will mask the values */ + msg.buf = optoe->writebuf; + + msg.buf[i++] = offset; + memcpy(&msg.buf[i], buf, count); + msg.len = i + count; + break; + } + + /* + * Reads fail if the previous write didn't complete yet. We may + * loop a few times until this one succeeds, waiting at least + * long enough for one entire page write to work. + */ + timeout = jiffies + msecs_to_jiffies(write_timeout); + do { + write_time = jiffies; + + switch (optoe->use_smbus) { + case I2C_SMBUS_I2C_BLOCK_DATA: + status = i2c_smbus_write_i2c_block_data(client, + offset, count, buf); + if (status == 0) + status = count; + break; + case I2C_SMBUS_WORD_DATA: + if (count == 2) { + status = i2c_smbus_write_word_data(client, + offset, (u16)((buf[0])|(buf[1] << 8))); + } else { + /* count = 1 */ + status = i2c_smbus_write_byte_data(client, + offset, buf[0]); + } + if (status == 0) + status = count; + break; + case I2C_SMBUS_BYTE_DATA: + status = i2c_smbus_write_byte_data(client, offset, + buf[0]); + if (status == 0) + status = count; + break; + default: + status = i2c_transfer(client->adapter, &msg, 1); + if (status == 1) + status = count; + break; + } + + dev_dbg(&client->dev, "eeprom write %zu@%d --> %ld (%lu)\n", + count, offset, (long int) status, jiffies); + + if (status == count) + return count; + + /* REVISIT: at HZ=100, this is sloooow */ + usleep_range(1000, 2000); + } while (time_before(write_time, timeout)); + + return -ETIMEDOUT; +} + +static ssize_t optoe_eeprom_update_client(struct optoe_data *optoe, + char *buf, loff_t off, + size_t count, int opcode) +{ + struct i2c_client *client; + ssize_t retval = 0; + uint8_t page = 0; + uint8_t loc; + loff_t phy_offset = off; + int ret = 0; + + page = optoe_translate_offset(optoe, &phy_offset, &client); + dev_dbg(&client->dev, + "%s off %lld page:%d phy_offset:%lld, count:%ld, opcode:%d\n", + __func__, off, page, phy_offset, (long int) count, opcode); + + ret = optoe_eeprom_read(optoe, client, &loc, OPTOE_PAGE_SELECT_REG, 1); + if (ret < 0) { + dev_dbg(&client->dev, "Read page register for get now location page failed. ret:%d\n", ret); + return ret; + } + + /* Only when read and now location page is inconsistent, will doing switch page */ + if (loc != page) { + ret = optoe_eeprom_write(optoe, client, &page, + OPTOE_PAGE_SELECT_REG, 1); + if (ret < 0) { + dev_dbg(&client->dev, + "Write page register for page %d failed ret:%d!\n", + page, ret); + return ret; + } + } + + while (count) { + ssize_t status; + + if (opcode == OPTOE_READ_OP) { + status = optoe_eeprom_read(optoe, client, + buf, phy_offset, count); + } else { + status = optoe_eeprom_write(optoe, client, + buf, phy_offset, count); + } + if (status <= 0) { + if (retval == 0) + retval = status; + break; + } + buf += status; + phy_offset += status; + count -= status; + retval += status; + } + + return retval; +} + +/* + * Figure out if this access is within the range of supported pages. + * Note this is called on every access because we don't know if the + * module has been replaced since the last call. + * If/when modules support more pages, this is the routine to update + * to validate and allow access to additional pages. + * + * Returns updated len for this access: + * - entire access is legal, original len is returned. + * - access begins legal but is too long, len is truncated to fit. + * - initial offset exceeds supported pages, return OPTOE_EOF (zero) + */ +static ssize_t optoe_page_legal(struct optoe_data *optoe, + loff_t off, size_t len) +{ + struct i2c_client *client = optoe->client[0]; + u8 regval; + int not_pageable; + int status; + size_t maxlen; + + if (off < 0) + return -EINVAL; + if (optoe->dev_class == TWO_ADDR) { + /* SFP case */ + /* if only using addr 0x50 (first 256 bytes) we're good */ + if ((off + len) <= TWO_ADDR_NO_0X51_SIZE) + return len; + /* if offset exceeds possible pages, we're not good */ + if (off >= TWO_ADDR_EEPROM_SIZE) + return OPTOE_EOF; + /* in between, are pages supported? */ + status = optoe_eeprom_read(optoe, client, ®val, + TWO_ADDR_PAGEABLE_REG, 1); + if (status < 0) + return status; /* error out (no module?) */ + if (regval & TWO_ADDR_PAGEABLE) { + /* Pages supported, trim len to the end of pages */ + maxlen = TWO_ADDR_EEPROM_SIZE - off; + } else { + /* pages not supported, trim len to unpaged size */ + if (off >= TWO_ADDR_EEPROM_UNPAGED_SIZE) + return OPTOE_EOF; + + /* will be accessing addr 0x51, is that supported? */ + /* byte 92, bit 6 implies DDM support, 0x51 support */ + status = optoe_eeprom_read(optoe, client, ®val, + TWO_ADDR_0X51_REG, 1); + if (status < 0) + return status; + if (regval & TWO_ADDR_0X51_SUPP) { + /* addr 0x51 is OK */ + maxlen = TWO_ADDR_EEPROM_UNPAGED_SIZE - off; + } else { + /* addr 0x51 NOT supported, trim to 256 max */ + if (off >= TWO_ADDR_NO_0X51_SIZE) + return OPTOE_EOF; + maxlen = TWO_ADDR_NO_0X51_SIZE - off; + } + } + len = (len > maxlen) ? maxlen : len; + dev_dbg(&client->dev, + "page_legal, SFP, off %lld len %ld\n", + off, (long int) len); + } else { + /* QSFP case, CMIS case */ + /* if no pages needed, we're good */ + if ((off + len) <= ONE_ADDR_EEPROM_UNPAGED_SIZE) + return len; + /* if offset exceeds possible pages, we're not good */ + if (off >= ONE_ADDR_EEPROM_SIZE) + return OPTOE_EOF; + /* in between, are pages supported? */ + status = optoe_eeprom_read(optoe, client, ®val, + ONE_ADDR_PAGEABLE_REG, 1); + if (status < 0) + return status; /* error out (no module?) */ + + if (optoe->dev_class == ONE_ADDR) { + not_pageable = QSFP_NOT_PAGEABLE; + } else { + not_pageable = CMIS_NOT_PAGEABLE; + } + dev_dbg(&client->dev, + "Paging Register: 0x%x; not_pageable mask: 0x%x\n", + regval, not_pageable); + + if (regval & not_pageable) { + /* pages not supported, trim len to unpaged size */ + if (off >= ONE_ADDR_EEPROM_UNPAGED_SIZE) + return OPTOE_EOF; + maxlen = ONE_ADDR_EEPROM_UNPAGED_SIZE - off; + } else { + /* Pages supported, trim len to the end of pages */ + maxlen = ONE_ADDR_EEPROM_SIZE - off; + } + len = (len > maxlen) ? maxlen : len; + dev_dbg(&client->dev, + "page_legal, QSFP, off %lld len %ld\n", + off, (long int) len); + } + return len; +} + +static ssize_t optoe_read_write(struct optoe_data *optoe, + char *buf, loff_t off, size_t len, int opcode) +{ + struct i2c_client *client = optoe->client[0]; + int chunk; + int status = 0; + ssize_t retval; + size_t pending_len = 0, chunk_len = 0; + loff_t chunk_offset = 0, chunk_start_offset = 0; + loff_t chunk_end_offset = 0; + + dev_dbg(&client->dev, + "%s: off %lld len:%ld, opcode:%s\n", + __func__, off, (long int) len, + (opcode == OPTOE_READ_OP) ? "r" : "w"); + if (unlikely(!len)) + return len; + + /* + * Read data from chip, protecting against concurrent updates + * from this host, but not from other I2C masters. + */ + mutex_lock(&optoe->lock); + + /* + * Confirm this access fits within the device suppored addr range + */ + status = optoe_page_legal(optoe, off, len); + if ((status == OPTOE_EOF) || (status < 0)) { + mutex_unlock(&optoe->lock); + return status; + } + len = status; + + /* + * For each (128 byte) chunk involved in this request, issue a + * separate call to sff_eeprom_update_client(), to + * ensure that each access recalculates the client/page + * and writes the page register as needed. + * Note that chunk to page mapping is confusing, is different for + * QSFP and SFP, and never needs to be done. Don't try! + */ + pending_len = len; /* amount remaining to transfer */ + retval = 0; /* amount transferred */ + for (chunk = off >> 7; chunk <= (off + len - 1) >> 7; chunk++) { + + /* + * Compute the offset and number of bytes to be read/write + * + * 1. start at an offset not equal to 0 (within the chunk) + * and read/write less than the rest of the chunk + * 2. start at an offset not equal to 0 and read/write the rest + * of the chunk + * 3. start at offset 0 (within the chunk) and read/write less + * than entire chunk + * 4. start at offset 0 (within the chunk), and read/write + * the entire chunk + */ + chunk_start_offset = chunk * OPTOE_PAGE_SIZE; + chunk_end_offset = chunk_start_offset + OPTOE_PAGE_SIZE; + + if (chunk_start_offset < off) { + chunk_offset = off; + if ((off + pending_len) < chunk_end_offset) + chunk_len = pending_len; + else + chunk_len = chunk_end_offset - off; + } else { + chunk_offset = chunk_start_offset; + if (pending_len < OPTOE_PAGE_SIZE) + chunk_len = pending_len; + else + chunk_len = OPTOE_PAGE_SIZE; + } + + dev_dbg(&client->dev, + "sff_r/w: off %lld, len %ld, chunk_start_offset %lld, chunk_offset %lld, chunk_len %ld, pending_len %ld\n", + off, (long int) len, chunk_start_offset, chunk_offset, + (long int) chunk_len, (long int) pending_len); + + /* + * note: chunk_offset is from the start of the EEPROM, + * not the start of the chunk + */ + status = optoe_eeprom_update_client(optoe, buf, + chunk_offset, chunk_len, opcode); + if (status != chunk_len) { + /* This is another 'no device present' path */ + dev_dbg(&client->dev, + "o_u_c: chunk %d c_offset %lld c_len %ld failed %d!\n", + chunk, chunk_offset, (long int) chunk_len, status); + if (status > 0) + retval += status; + if (retval == 0) + retval = status; + break; + } + buf += status; + pending_len -= status; + retval += status; + } + mutex_unlock(&optoe->lock); + + return retval; +} + +static ssize_t optoe_bin_read(struct file *filp, struct kobject *kobj, + struct bin_attribute *attr, + char *buf, loff_t off, size_t count) +{ + struct i2c_client *client = to_i2c_client(container_of(kobj, + struct device, kobj)); + struct optoe_data *optoe = i2c_get_clientdata(client); + + return optoe_read_write(optoe, buf, off, count, OPTOE_READ_OP); +} + +static ssize_t optoe_bin_write(struct file *filp, struct kobject *kobj, + struct bin_attribute *attr, + char *buf, loff_t off, size_t count) +{ + struct i2c_client *client = to_i2c_client(container_of(kobj, + struct device, kobj)); + struct optoe_data *optoe = i2c_get_clientdata(client); + + return optoe_read_write(optoe, buf, off, count, OPTOE_WRITE_OP); +} + +static int optoe_remove(struct i2c_client *client) +{ + struct optoe_data *optoe; + int i; + + optoe = i2c_get_clientdata(client); + sysfs_remove_group(&client->dev.kobj, &optoe->attr_group); + sysfs_remove_bin_file(&client->dev.kobj, &optoe->bin); + + for (i = 1; i < optoe->num_addresses; i++) + i2c_unregister_device(optoe->client[i]); + +#ifdef EEPROM_CLASS + eeprom_device_unregister(optoe->eeprom_dev); +#endif + + kfree(optoe->writebuf); + kfree(optoe); + return 0; +} + +static ssize_t show_dev_class(struct device *dev, + struct device_attribute *dattr, char *buf) +{ + struct i2c_client *client = to_i2c_client(dev); + struct optoe_data *optoe = i2c_get_clientdata(client); + ssize_t count; + + mutex_lock(&optoe->lock); + count = sprintf(buf, "%d\n", optoe->dev_class); + mutex_unlock(&optoe->lock); + + return count; +} + +static ssize_t set_dev_class(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct i2c_client *client = to_i2c_client(dev); + struct optoe_data *optoe = i2c_get_clientdata(client); + int dev_class; + + /* + * dev_class is actually the number of i2c addresses used, thus + * legal values are "1" (QSFP class) and "2" (SFP class) + * And... CMIS spec is 1 i2c address, but puts the pageable + * bit in a different location, so CMIS devices are "3" + */ + + if (kstrtoint(buf, 0, &dev_class) != 0 || + dev_class < 1 || dev_class > 3) + return -EINVAL; + + mutex_lock(&optoe->lock); + if (dev_class == TWO_ADDR) { + /* SFP family */ + /* if it doesn't exist, create 0x51 i2c address */ + if (!optoe->client[1]) { + optoe->client[1] = i2c_new_dummy_device(client->adapter, 0x51); + if (!optoe->client[1]) { + dev_err(&client->dev, + "address 0x51 unavailable\n"); + mutex_unlock(&optoe->lock); + return -EADDRINUSE; + } + } + optoe->bin.size = TWO_ADDR_EEPROM_SIZE; + optoe->num_addresses = 2; + } else { + /* one-address (eg QSFP) and CMIS family */ + /* if it exists, remove 0x51 i2c address */ + if (optoe->client[1]) { + i2c_unregister_device(optoe->client[1]); + optoe->client[1] = NULL; + } + optoe->bin.size = ONE_ADDR_EEPROM_SIZE; + optoe->num_addresses = 1; + } + optoe->dev_class = dev_class; + mutex_unlock(&optoe->lock); + + return count; +} + +/* + * if using the EEPROM CLASS driver, we don't report a port_name, + * the EEPROM CLASS drive handles that. Hence all this code is + * only compiled if we are NOT using the EEPROM CLASS driver. + */ +#ifndef EEPROM_CLASS + +static ssize_t show_port_name(struct device *dev, + struct device_attribute *dattr, char *buf) +{ + struct i2c_client *client = to_i2c_client(dev); + struct optoe_data *optoe = i2c_get_clientdata(client); + ssize_t count; + + mutex_lock(&optoe->lock); + count = sprintf(buf, "%s\n", optoe->port_name); + mutex_unlock(&optoe->lock); + + return count; +} + +static ssize_t set_port_name(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct i2c_client *client = to_i2c_client(dev); + struct optoe_data *optoe = i2c_get_clientdata(client); + char port_name[MAX_PORT_NAME_LEN]; + + /* no checking, this value is not used except by show_port_name */ + + if (sscanf(buf, "%19s", port_name) != 1) + return -EINVAL; + + mutex_lock(&optoe->lock); + strcpy(optoe->port_name, port_name); + mutex_unlock(&optoe->lock); + + return count; +} + +static DEVICE_ATTR(port_name, 0644, show_port_name, set_port_name); +#endif /* if NOT defined EEPROM_CLASS, the common case */ + +static DEVICE_ATTR(dev_class, 0644, show_dev_class, set_dev_class); + +static struct attribute *optoe_attrs[] = { +#ifndef EEPROM_CLASS + &dev_attr_port_name.attr, +#endif + &dev_attr_dev_class.attr, + NULL, +}; + +static struct attribute_group optoe_attr_group = { + .attrs = optoe_attrs, +}; + +static int optoe_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int err; + int use_smbus = 0; + struct optoe_platform_data chip; + struct optoe_data *optoe; + int num_addresses = 0; + char port_name[MAX_PORT_NAME_LEN]; + + if (client->addr != 0x50) { + dev_dbg(&client->dev, "probe, bad i2c addr: 0x%x\n", + client->addr); + err = -EINVAL; + goto exit; + } + + if (client->dev.platform_data) { + chip = *(struct optoe_platform_data *)client->dev.platform_data; + /* take the port name from the supplied platform data */ +#ifdef EEPROM_CLASS + strncpy(port_name, chip.eeprom_data->label, MAX_PORT_NAME_LEN); +#else + memcpy(port_name, chip.port_name, MAX_PORT_NAME_LEN); +#endif + dev_dbg(&client->dev, + "probe, chip provided, flags:0x%x; name: %s\n", + chip.flags, client->name); + } else { + if (!id->driver_data) { + err = -ENODEV; + goto exit; + } + dev_dbg(&client->dev, "probe, building chip\n"); + strcpy(port_name, "unitialized"); + chip.flags = 0; +#ifdef EEPROM_CLASS + chip.eeprom_data = NULL; +#endif + } + + /* Use I2C operations unless we're stuck with SMBus extensions. */ + if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { + if (i2c_check_functionality(client->adapter, + I2C_FUNC_SMBUS_READ_I2C_BLOCK)) { + use_smbus = I2C_SMBUS_I2C_BLOCK_DATA; + } else if (i2c_check_functionality(client->adapter, + I2C_FUNC_SMBUS_READ_WORD_DATA)) { + use_smbus = I2C_SMBUS_WORD_DATA; + } else if (i2c_check_functionality(client->adapter, + I2C_FUNC_SMBUS_READ_BYTE_DATA)) { + use_smbus = I2C_SMBUS_BYTE_DATA; + } else { + err = -EPFNOSUPPORT; + goto exit; + } + } + + /* + * Make room for two i2c clients + */ + num_addresses = 2; + + optoe = kzalloc(sizeof(struct optoe_data) + + num_addresses * sizeof(struct i2c_client *), + GFP_KERNEL); + if (!optoe) { + err = -ENOMEM; + goto exit; + } + + mutex_init(&optoe->lock); + + /* determine whether this is a one-address or two-address module */ + if ((strcmp(client->name, "wb_optoe1") == 0) || + (strcmp(client->name, "wb_sff8436") == 0)) { + /* one-address (eg QSFP) family */ + optoe->dev_class = ONE_ADDR; + chip.byte_len = ONE_ADDR_EEPROM_SIZE; + num_addresses = 1; + } else if ((strcmp(client->name, "wb_optoe2") == 0) || + (strcmp(client->name, "wb_24c04") == 0)) { + /* SFP family */ + optoe->dev_class = TWO_ADDR; + chip.byte_len = TWO_ADDR_EEPROM_SIZE; + num_addresses = 2; + } else if (strcmp(client->name, "wb_optoe3") == 0) { + /* CMIS spec */ + optoe->dev_class = CMIS_ADDR; + chip.byte_len = ONE_ADDR_EEPROM_SIZE; + num_addresses = 1; + } else { /* those were the only choices */ + err = -EINVAL; + goto exit; + } + + dev_dbg(&client->dev, "dev_class: %d\n", optoe->dev_class); + optoe->use_smbus = use_smbus; + optoe->chip = chip; + optoe->num_addresses = num_addresses; + memcpy(optoe->port_name, port_name, MAX_PORT_NAME_LEN); + + /* + * Export the EEPROM bytes through sysfs, since that's convenient. + * By default, only root should see the data (maybe passwords etc) + */ + sysfs_bin_attr_init(&optoe->bin); + optoe->bin.attr.name = "eeprom"; + optoe->bin.attr.mode = 0444; + optoe->bin.read = optoe_bin_read; + optoe->bin.size = chip.byte_len; + + if (!use_smbus || + (i2c_check_functionality(client->adapter, + I2C_FUNC_SMBUS_WRITE_I2C_BLOCK)) || + i2c_check_functionality(client->adapter, + I2C_FUNC_SMBUS_WRITE_WORD_DATA) || + i2c_check_functionality(client->adapter, + I2C_FUNC_SMBUS_WRITE_BYTE_DATA)) { + /* + * NOTE: AN-2079 + * Finisar recommends that the host implement 1 byte writes + * only since this module only supports 32 byte page boundaries. + * 2 byte writes are acceptable for PE and Vout changes per + * Application Note AN-2071. + */ + unsigned int write_max = 1; + + optoe->bin.write = optoe_bin_write; + optoe->bin.attr.mode |= 0200; + + if (write_max > io_limit) + write_max = io_limit; + if (use_smbus && write_max > I2C_SMBUS_BLOCK_MAX) + write_max = I2C_SMBUS_BLOCK_MAX; + optoe->write_max = write_max; + + /* buffer (data + address at the beginning) */ + optoe->writebuf = kmalloc(write_max + 2, GFP_KERNEL); + if (!optoe->writebuf) { + err = -ENOMEM; + goto exit_kfree; + } + } else { + dev_warn(&client->dev, + "cannot write due to controller restrictions."); + } + + optoe->client[0] = client; + + /* SFF-8472 spec requires that the second I2C address be 0x51 */ + if (num_addresses == 2) { + optoe->client[1] = i2c_new_dummy_device(client->adapter, 0x51); + if (!optoe->client[1]) { + dev_err(&client->dev, "address 0x51 unavailable\n"); + err = -EADDRINUSE; + goto err_struct; + } + } + + /* create the sysfs eeprom file */ + err = sysfs_create_bin_file(&client->dev.kobj, &optoe->bin); + if (err) + goto err_struct; + + optoe->attr_group = optoe_attr_group; + + err = sysfs_create_group(&client->dev.kobj, &optoe->attr_group); + if (err) { + dev_err(&client->dev, "failed to create sysfs attribute group.\n"); + goto err_struct; + } + +#ifdef EEPROM_CLASS + optoe->eeprom_dev = eeprom_device_register(&client->dev, + chip.eeprom_data); + if (IS_ERR(optoe->eeprom_dev)) { + dev_err(&client->dev, "error registering eeprom device.\n"); + err = PTR_ERR(optoe->eeprom_dev); + goto err_sysfs_cleanup; + } +#endif + + i2c_set_clientdata(client, optoe); + + dev_info(&client->dev, "%zu byte %s EEPROM, %s\n", + optoe->bin.size, client->name, + optoe->bin.write ? "read/write" : "read-only"); + + if (use_smbus == I2C_SMBUS_WORD_DATA || + use_smbus == I2C_SMBUS_BYTE_DATA) { + dev_notice(&client->dev, + "Falling back to %s reads, performance will suffer\n", + use_smbus == I2C_SMBUS_WORD_DATA ? "word" : "byte"); + } + + return 0; + +#ifdef EEPROM_CLASS +err_sysfs_cleanup: + sysfs_remove_group(&client->dev.kobj, &optoe->attr_group); + sysfs_remove_bin_file(&client->dev.kobj, &optoe->bin); +#endif + +err_struct: + if (num_addresses == 2) { + if (optoe->client[1]) { + i2c_unregister_device(optoe->client[1]); + optoe->client[1] = NULL; + } + } + + kfree(optoe->writebuf); +exit_kfree: + kfree(optoe); +exit: + dev_dbg(&client->dev, "probe error %d\n", err); + + return err; +} + +/*-------------------------------------------------------------------------*/ + +static struct i2c_driver optoe_driver = { + .driver = { + .name = "wb_optoe", + .owner = THIS_MODULE, + }, + .probe = optoe_probe, + .remove = optoe_remove, + .id_table = optoe_ids, +}; + +static int __init optoe_init(void) +{ + + if (!io_limit) { + pr_err("optoe: io_limit must not be 0!\n"); + return -EINVAL; + } + + io_limit = rounddown_pow_of_two(io_limit); + return i2c_add_driver(&optoe_driver); +} +module_init(optoe_init); + +static void __exit optoe_exit(void) +{ + i2c_del_driver(&optoe_driver); +} +module_exit(optoe_exit); + +MODULE_DESCRIPTION("Driver for optical transceiver (SFP, QSFP, ...) EEPROMs"); +MODULE_AUTHOR("support"); +MODULE_LICENSE("GPL"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_pcie_dev.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_pcie_dev.c new file mode 100644 index 000000000000..1f5180ffccdc --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_pcie_dev.c @@ -0,0 +1,770 @@ +/* + * wb_pcie_dev.c + * ko to read/write pcie iomem and ioports through /dev/XXX device + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "wb_pcie_dev.h" + +#define PROXY_NAME "wb-pci-dev" +#define MAX_NAME_SIZE (20) +#define MAX_PCIE_NUM (256) +#define PCI_RDWR_MAX_LEN (256) +#define PCIE_BUS_WIDTH_1 (1) +#define PCIE_BUS_WIDTH_2 (2) +#define PCIE_BUS_WIDTH_4 (4) + +static int g_pcie_dev_debug = 0; +static int g_pcie_dev_error = 0; + +module_param(g_pcie_dev_debug, int, S_IRUGO | S_IWUSR); +module_param(g_pcie_dev_error, int, S_IRUGO | S_IWUSR); + +#define PCIE_DEV_DEBUG_VERBOSE(fmt, args...) do { \ + if (g_pcie_dev_debug) { \ + printk(KERN_INFO "[PCIE_DEV][VER][func:%s line:%d]\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +#define PCIE_DEV_DEBUG_ERROR(fmt, args...) do { \ + if (g_pcie_dev_error) { \ + printk(KERN_ERR "[PCIE_DEV][ERR][func:%s line:%d]\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +typedef struct firmware_upg_s { + int upg_ctrl_base; + int upg_flash_base; +} firmware_upg_t; + +typedef struct wb_pci_dev_s { + const char *name; + uint32_t domain; + uint32_t bus; + uint32_t slot; + uint32_t fn; + uint32_t bar; + void __iomem *pci_mem_base; + uint32_t pci_io_base; + uint32_t bar_len; + uint32_t bar_flag; + uint32_t bus_width; + struct miscdevice misc; + void (*setreg)(struct wb_pci_dev_s *wb_pci_dev, int reg, u32 value); + u32 (*getreg)(struct wb_pci_dev_s *wb_pci_dev, int reg); + firmware_upg_t firmware_upg; +} wb_pci_dev_t; + +static wb_pci_dev_t* pcie_dev_arry[MAX_PCIE_NUM]; + +static void pci_dev_setreg_8(wb_pci_dev_t *wb_pci_dev, int reg, u32 value) +{ + u8 w_value; + + w_value = (u8)(value & 0xff); + if (wb_pci_dev->bar_flag == IORESOURCE_MEM) { + writeb(w_value, wb_pci_dev->pci_mem_base + reg); + } else { + outb(w_value, wb_pci_dev->pci_io_base + reg); + } + return; +} + +static void pci_dev_setreg_16(wb_pci_dev_t *wb_pci_dev, int reg, u32 value) +{ + u16 w_value; + + w_value = (u16)(value & 0xffff); + if (wb_pci_dev->bar_flag == IORESOURCE_MEM) { + writew(w_value, wb_pci_dev->pci_mem_base + reg); + } else { + outw(w_value, wb_pci_dev->pci_io_base + reg); + } + + return; +} + +static void pci_dev_setreg_32(wb_pci_dev_t *wb_pci_dev, int reg, u32 value) +{ + + if (wb_pci_dev->bar_flag == IORESOURCE_MEM) { + writel(value, wb_pci_dev->pci_mem_base + reg); + } else { + outl(value, wb_pci_dev->pci_io_base + reg); + } + return; +} + +static inline u32 pci_dev_getreg_8(wb_pci_dev_t *wb_pci_dev, int reg) +{ + u32 value; + + if (wb_pci_dev->bar_flag == IORESOURCE_MEM) { + value = readb(wb_pci_dev->pci_mem_base + reg); + } else { + value = inb(wb_pci_dev->pci_io_base + reg); + } + + return value; +} + +static inline u32 pci_dev_getreg_16(wb_pci_dev_t *wb_pci_dev, int reg) +{ + u32 value; + + if (wb_pci_dev->bar_flag == IORESOURCE_MEM) { + value = readw(wb_pci_dev->pci_mem_base + reg); + } else { + value = inw(wb_pci_dev->pci_io_base + reg); + } + + return value; +} + +static inline u32 pci_dev_getreg_32(wb_pci_dev_t *wb_pci_dev, int reg) +{ + u32 value; + + if (wb_pci_dev->bar_flag == IORESOURCE_MEM) { + value = readl(wb_pci_dev->pci_mem_base + reg); + } else { + value = inl(wb_pci_dev->pci_io_base + reg); + } + + return value; +} + +static inline void pci_dev_setreg(wb_pci_dev_t *wb_pci_dev, int reg, u32 value) +{ + wb_pci_dev->setreg(wb_pci_dev, reg, value); +} + +static inline u32 pci_dev_getreg(wb_pci_dev_t *wb_pci_dev, int reg) +{ + return wb_pci_dev->getreg(wb_pci_dev, reg); +} + +static int pci_dev_open(struct inode *inode, struct file *file) +{ + unsigned int minor = iminor(inode); + wb_pci_dev_t *wb_pci_dev; + + PCIE_DEV_DEBUG_VERBOSE("inode: %p, file: %p, minor: %u", inode, file, minor); + + if (minor >= MAX_PCIE_NUM) { + PCIE_DEV_DEBUG_ERROR("minor out of range, minor = %d.\n", minor); + return -ENODEV; + } + + wb_pci_dev = pcie_dev_arry[minor]; + if (wb_pci_dev == NULL) { + PCIE_DEV_DEBUG_ERROR("wb_pci_dev is NULL, open failed, minor = %d\n", minor); + return -ENODEV; + } + + file->private_data = wb_pci_dev; + return 0; +} + +static int pci_dev_release(struct inode *inode, struct file *file) +{ + file->private_data = NULL; + return 0; +} + +static int pci_dev_read_tmp(wb_pci_dev_t *wb_pci_dev, uint32_t offset, uint8_t *buf, size_t count) +{ + int width, i, j; + u32 val; + + if (offset > wb_pci_dev->bar_len) { + PCIE_DEV_DEBUG_VERBOSE("offset:0x%x, bar len:0x%x, EOF.\n", offset, wb_pci_dev->bar_len); + return 0; + } + + width = wb_pci_dev->bus_width; + + if (offset % width) { + PCIE_DEV_DEBUG_ERROR("pci bus width:%d, offset:0x%x, read size %lu invalid.\n", + width, offset, count); + return -EINVAL; + } + + if (count > wb_pci_dev->bar_len - offset) { + PCIE_DEV_DEBUG_VERBOSE("read count out of range. input len:%lu, read len:%u.\n", + count, wb_pci_dev->bar_len - offset); + count = wb_pci_dev->bar_len - offset; + } + + for (i = 0; i < count; i += width) { + val = pci_dev_getreg(wb_pci_dev, offset + i); + for (j = 0; (j < width) && (i + j < count); j++) { + buf[i + j] = (val >> (8 * j)) & 0xff; + } + } + return count; +} + +static ssize_t pci_dev_read(struct file *file, char __user *buf, size_t count, loff_t *offset) +{ + wb_pci_dev_t *wb_pci_dev; + int ret, read_len; + u8 buf_tmp[PCI_RDWR_MAX_LEN]; + + wb_pci_dev = file->private_data; + if (wb_pci_dev == NULL) { + PCIE_DEV_DEBUG_ERROR("wb_pci_dev is NULL, read failed.\n"); + return -EINVAL; + } + + if (count == 0) { + PCIE_DEV_DEBUG_ERROR("Invalid params, read count is 0.n"); + return -EINVAL; + } + + if (count > sizeof(buf_tmp)) { + PCIE_DEV_DEBUG_VERBOSE("read conut %lu exceed max %lu.\n", count, sizeof(buf_tmp)); + count = sizeof(buf_tmp); + } + + mem_clear(buf_tmp, sizeof(buf_tmp)); + read_len = pci_dev_read_tmp(wb_pci_dev, *offset, buf_tmp, count); + if (read_len < 0) { + PCIE_DEV_DEBUG_ERROR("pci_dev_read_tmp failed, ret:%d.\n", read_len); + return read_len; + } + if (access_ok(buf, read_len)) { + PCIE_DEV_DEBUG_VERBOSE("user space read, buf: %p, offset: %lld, read conut %lu.\n", + buf, *offset, count); + if (copy_to_user(buf, buf_tmp, read_len)) { + PCIE_DEV_DEBUG_ERROR("copy_to_user failed.\n"); + return -EFAULT; + } + } else { + PCIE_DEV_DEBUG_VERBOSE("kernel space read, buf: %p, offset: %lld, read conut %lu.\n", + buf, *offset, count); + memcpy(buf, buf_tmp, read_len); + } + *offset += read_len; + ret = read_len; + return ret; +} + +static ssize_t pci_dev_read_iter(struct kiocb *iocb, struct iov_iter *to) +{ + int ret; + + PCIE_DEV_DEBUG_VERBOSE("pci_dev_read_iter, file: %p, count: %lu, offset: %lld\n", + iocb->ki_filp, to->count, iocb->ki_pos); + ret = pci_dev_read(iocb->ki_filp, to->kvec->iov_base, to->count, &iocb->ki_pos); + return ret; +} + +static int pci_dev_write_tmp(wb_pci_dev_t *wb_pci_dev, uint32_t offset, uint8_t *buf, size_t count) +{ + int width, i, j; + u32 val; + + if (offset > wb_pci_dev->bar_len) { + PCIE_DEV_DEBUG_VERBOSE("offset:0x%x, bar len:0x%x, EOF.\n", offset, wb_pci_dev->bar_len); + return 0; + } + + width = wb_pci_dev->bus_width; + + if (offset % width) { + PCIE_DEV_DEBUG_ERROR("pci bus width:%d, offset:0x%x, read size %lu invalid.\n", + width, offset, count); + return -EINVAL; + } + + if (count > wb_pci_dev->bar_len - offset) { + PCIE_DEV_DEBUG_VERBOSE("write count out of range. input len:%lu, write len:%u.\n", + count, wb_pci_dev->bar_len - offset); + count = wb_pci_dev->bar_len - offset; + } + + for (i = 0; i < count; i += width) { + val = 0; + for (j = 0; (j < width) && (i + j < count); j++) { + val |= buf[i + j] << (8 * j); + } + pci_dev_setreg(wb_pci_dev, i + offset, val); + } + + return count; +} + +static ssize_t pci_dev_write(struct file *file, const char __user *buf, size_t count, + loff_t *offset) +{ + wb_pci_dev_t *wb_pci_dev; + u8 buf_tmp[PCI_RDWR_MAX_LEN]; + int write_len; + + wb_pci_dev = file->private_data; + if (wb_pci_dev == NULL) { + PCIE_DEV_DEBUG_ERROR("wb_pci_dev is NULL, write failed.\n"); + return -EINVAL; + } + + if (count == 0) { + PCIE_DEV_DEBUG_ERROR("Invalid params, write count is 0.\n"); + return -EINVAL; + } + + if (count > sizeof(buf_tmp)) { + PCIE_DEV_DEBUG_VERBOSE("write conut %lu exceed max %lu.\n", count, sizeof(buf_tmp)); + count = sizeof(buf_tmp); + } + + mem_clear(buf_tmp, sizeof(buf_tmp)); + if (access_ok(buf, count)) { + PCIE_DEV_DEBUG_VERBOSE("user space write, buf: %p, offset: %lld, write conut %lu.\n", + buf, *offset, count); + if (copy_from_user(buf_tmp, buf, count)) { + PCIE_DEV_DEBUG_ERROR("copy_from_user failed.\n"); + return -EFAULT; + } + } else { + PCIE_DEV_DEBUG_VERBOSE("kernel space write, buf: %p, offset: %lld, write conut %lu.\n", + buf, *offset, count); + memcpy(buf_tmp, buf, count); + } + + write_len = pci_dev_write_tmp(wb_pci_dev, *offset, buf_tmp, count); + if (write_len < 0) { + PCIE_DEV_DEBUG_ERROR("pci_dev_write_tmp failed, ret:%d.\n", write_len); + return write_len; + } + + *offset += write_len; + return write_len; +} + +static ssize_t pci_dev_write_iter(struct kiocb *iocb, struct iov_iter *from) +{ + int ret; + + PCIE_DEV_DEBUG_VERBOSE("pci_dev_write_iter, file: %p, count: %lu, offset: %lld\n", + iocb->ki_filp, from->count, iocb->ki_pos); + ret = pci_dev_write(iocb->ki_filp, from->kvec->iov_base, from->count, &iocb->ki_pos); + return ret; +} + +static loff_t pci_dev_llseek(struct file *file, loff_t offset, int origin) +{ + loff_t ret = 0; + wb_pci_dev_t *wb_pci_dev; + + wb_pci_dev = file->private_data; + if (wb_pci_dev == NULL) { + PCIE_DEV_DEBUG_ERROR("wb_pci_dev is NULL, llseek failed.\n"); + return -EINVAL; + } + + switch (origin) { + case SEEK_SET: + if (offset < 0) { + PCIE_DEV_DEBUG_ERROR("SEEK_SET, offset:%lld, invalid.\n", offset); + ret = -EINVAL; + break; + } + if (offset > wb_pci_dev->bar_len) { + PCIE_DEV_DEBUG_ERROR("SEEK_SET out of range, offset:%lld, bar len:0x%x.\n", + offset, wb_pci_dev->bar_len); + ret = - EINVAL; + break; + } + file->f_pos = offset; + ret = file->f_pos; + break; + case SEEK_CUR: + if (((file->f_pos + offset) > wb_pci_dev->bar_len) || ((file->f_pos + offset) < 0)) { + PCIE_DEV_DEBUG_ERROR("SEEK_CUR out of range, f_ops:%lld, offset:%lld, bar len:0x%x.\n", + file->f_pos, offset, wb_pci_dev->bar_len); + ret = - EINVAL; + break; + } + file->f_pos += offset; + ret = file->f_pos; + break; + default: + PCIE_DEV_DEBUG_ERROR("unsupport llseek type:%d.\n", origin); + ret = -EINVAL; + break; + } + return ret; +} + +static long pci_dev_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + wb_pci_dev_t *wb_pci_dev; + void __user *argp; + firmware_upg_t *firmware_upg; + int upg_ctrl_base; + int upg_flash_base; + + PCIE_DEV_DEBUG_VERBOSE("ioctl, cmd=0x%02x, arg=0x%02lx\n",cmd, arg); + + wb_pci_dev = file->private_data; + if (wb_pci_dev == NULL) { + PCIE_DEV_DEBUG_ERROR("wb_pci_dev is NULL, ioctl failed.\n"); + return -EINVAL; + } + + firmware_upg = &wb_pci_dev->firmware_upg; + + argp = (void __user *)arg; + + switch (cmd) { + case GET_FPGA_UPG_CTL_BASE: + if (firmware_upg->upg_ctrl_base < 0) { + PCIE_DEV_DEBUG_ERROR("dts not adaptive upg_ctrl_base\n"); + return -EFAULT; + } else { + upg_ctrl_base = firmware_upg->upg_ctrl_base; + if (copy_to_user(argp, &upg_ctrl_base, sizeof(upg_ctrl_base))) { + PCIE_DEV_DEBUG_ERROR("upg_ctrl_base copy_from_user failed\n"); + return -EFAULT; + } + } + break; + case GET_FPGA_UPG_FLASH_BASE: + if (firmware_upg->upg_flash_base < 0) { + PCIE_DEV_DEBUG_ERROR("dts not adaptive upg_flash_base\n"); + return -EFAULT; + } else { + upg_flash_base = firmware_upg->upg_flash_base; + if (copy_to_user(argp, &upg_flash_base, sizeof(upg_flash_base))) { + PCIE_DEV_DEBUG_ERROR("upg_flash_base copy_from_user failed\n"); + return -EFAULT; + } + } + break; + default: + PCIE_DEV_DEBUG_ERROR("command unsupported \n"); + return -ENOTTY; + } + + return 0; +} + +static const struct file_operations pcie_dev_fops = { + .owner = THIS_MODULE, + .llseek = pci_dev_llseek, + .read_iter = pci_dev_read_iter, + .write_iter = pci_dev_write_iter, + .unlocked_ioctl = pci_dev_ioctl, + .open = pci_dev_open, + .release = pci_dev_release, +}; + +static wb_pci_dev_t *dev_match(const char *path) +{ + wb_pci_dev_t *wb_pci_dev; + char dev_name[MAX_NAME_SIZE]; + int i; + + for (i = 0; i < MAX_PCIE_NUM; i++) { + if (pcie_dev_arry[i] == NULL) { + continue; + } + wb_pci_dev = pcie_dev_arry[i]; + snprintf(dev_name, MAX_NAME_SIZE,"/dev/%s", wb_pci_dev->name); + if (!strcmp(path, dev_name)) { + PCIE_DEV_DEBUG_VERBOSE("get dev_name = %s, minor = %d\n", dev_name, i); + return wb_pci_dev; + } + } + + return NULL; +} + +int pcie_device_func_read(const char *path, uint32_t offset, uint8_t *buf, size_t count) +{ + wb_pci_dev_t *wb_pci_dev; + int read_len; + + if (path == NULL) { + PCIE_DEV_DEBUG_ERROR("path NULL"); + return -EINVAL; + } + + if (buf == NULL) { + PCIE_DEV_DEBUG_ERROR("buf NULL"); + return -EINVAL; + } + + wb_pci_dev = dev_match(path); + if (wb_pci_dev == NULL) { + PCIE_DEV_DEBUG_ERROR("i2c_dev match failed. dev path = %s", path); + return -EINVAL; + } + + read_len = pci_dev_read_tmp(wb_pci_dev, offset, buf, count); + if (read_len < 0) { + PCIE_DEV_DEBUG_ERROR("pci_dev_read_tmp failed, ret:%d.\n", read_len); + } + return read_len; +} +EXPORT_SYMBOL(pcie_device_func_read); + +int pcie_device_func_write(const char *path, uint32_t offset, uint8_t *buf, size_t count) +{ + wb_pci_dev_t *wb_pci_dev; + int write_len; + + if (path == NULL) { + PCIE_DEV_DEBUG_ERROR("path NULL"); + return -EINVAL; + } + + if (buf == NULL) { + PCIE_DEV_DEBUG_ERROR("buf NULL"); + return -EINVAL; + } + + wb_pci_dev = dev_match(path); + if (wb_pci_dev == NULL) { + PCIE_DEV_DEBUG_ERROR("i2c_dev match failed. dev path = %s", path); + return -EINVAL; + } + + write_len = pci_dev_write_tmp(wb_pci_dev, offset, buf, count); + if (write_len < 0) { + PCIE_DEV_DEBUG_ERROR("pci_dev_write_tmp failed, ret:%d.\n", write_len); + } + return write_len; +} +EXPORT_SYMBOL(pcie_device_func_write); + +static int pci_setup_bars(wb_pci_dev_t *wb_pci_dev, struct pci_dev *dev) +{ + int ret; + uint32_t addr, len, flags; + + ret = 0; + addr = pci_resource_start(dev, wb_pci_dev->bar); + len = pci_resource_len(dev, wb_pci_dev->bar); + if (addr == 0 || len == 0) { + PCIE_DEV_DEBUG_ERROR("get bar addr failed. bar:%d, addr:0x%x, len:0x%x.\n", + wb_pci_dev->bar, addr, len); + return -EFAULT; + } + wb_pci_dev->bar_len = len; + + flags = pci_resource_flags(dev, wb_pci_dev->bar); + PCIE_DEV_DEBUG_VERBOSE("bar:%d, flag:0x%08x, phys addr:0x%x, len:0x%x\n", + wb_pci_dev->bar, flags, addr, len); + if (flags & IORESOURCE_MEM) { + wb_pci_dev->bar_flag = IORESOURCE_MEM; + wb_pci_dev->pci_mem_base = ioremap(addr, len); + PCIE_DEV_DEBUG_VERBOSE("pci mem base:%p.\n", wb_pci_dev->pci_mem_base); + } else if (flags & IORESOURCE_IO) { + wb_pci_dev->bar_flag = IORESOURCE_IO; + wb_pci_dev->pci_io_base = addr; + PCIE_DEV_DEBUG_VERBOSE("pci io base:0x%x.\n", wb_pci_dev->pci_io_base); + } else { + PCIE_DEV_DEBUG_ERROR("unknow pci bar flag:0x%08x.\n", flags); + ret = -EINVAL; + } + + return ret; +} + +static int pci_dev_probe(struct platform_device *pdev) +{ + int ret, devfn; + wb_pci_dev_t *wb_pci_dev; + struct pci_dev *pci_dev; + struct miscdevice *misc; + firmware_upg_t *firmware_upg; + pci_dev_device_t *pci_dev_device; + + wb_pci_dev = devm_kzalloc(&pdev->dev, sizeof(wb_pci_dev_t), GFP_KERNEL); + if (!wb_pci_dev) { + dev_err(&pdev->dev, "devm_kzalloc failed.\n"); + ret = -ENOMEM; + return ret; + } + + firmware_upg = &wb_pci_dev->firmware_upg; + + if (pdev->dev.of_node) { + ret = 0; + ret += of_property_read_string(pdev->dev.of_node, "pci_dev_name", &wb_pci_dev->name); + ret += of_property_read_u32(pdev->dev.of_node, "pci_domain", &wb_pci_dev->domain); + ret += of_property_read_u32(pdev->dev.of_node, "pci_bus", &wb_pci_dev->bus); + ret += of_property_read_u32(pdev->dev.of_node, "pci_slot", &wb_pci_dev->slot); + ret += of_property_read_u32(pdev->dev.of_node, "pci_fn", &wb_pci_dev->fn); + ret += of_property_read_u32(pdev->dev.of_node, "pci_bar", &wb_pci_dev->bar); + ret += of_property_read_u32(pdev->dev.of_node, "bus_width", &wb_pci_dev->bus_width); + + if (ret != 0) { + dev_err(&pdev->dev, "Failed to get dts config, ret:%d.\n", ret); + return -ENXIO; + } + + ret = 0; + ret += of_property_read_u32(pdev->dev.of_node, "upg_ctrl_base", &firmware_upg->upg_ctrl_base); + ret += of_property_read_u32(pdev->dev.of_node, "upg_flash_base", &firmware_upg->upg_flash_base); + if (ret != 0) { + PCIE_DEV_DEBUG_VERBOSE("dts don't adaptive fpga upg related, ret:%d.\n", ret); + firmware_upg->upg_ctrl_base = -1; + firmware_upg->upg_flash_base = -1; + } else { + PCIE_DEV_DEBUG_VERBOSE("upg_ctrl_base:0x%04x, upg_flash_base:0x%02x.\n", + firmware_upg->upg_ctrl_base, firmware_upg->upg_flash_base); + } + } else { + if (pdev->dev.platform_data == NULL) { + dev_err(&pdev->dev, "Failed to get platform data config.\n"); + return -ENXIO; + } + pci_dev_device = pdev->dev.platform_data; + wb_pci_dev->name = pci_dev_device->pci_dev_name; + wb_pci_dev->domain = pci_dev_device->pci_domain; + wb_pci_dev->bus = pci_dev_device->pci_bus; + wb_pci_dev->slot = pci_dev_device->pci_slot; + wb_pci_dev->fn = pci_dev_device->pci_fn; + wb_pci_dev->bar = pci_dev_device->pci_bar; + wb_pci_dev->bus_width = pci_dev_device->bus_width; + firmware_upg->upg_ctrl_base = pci_dev_device->upg_ctrl_base; + firmware_upg->upg_flash_base = pci_dev_device->upg_flash_base; + PCIE_DEV_DEBUG_VERBOSE("upg_ctrl_base:0x%04x, upg_flash_base:0x%02x.\n", + firmware_upg->upg_ctrl_base, firmware_upg->upg_flash_base); + } + + PCIE_DEV_DEBUG_VERBOSE("name:%s, domain:0x%04x, bus:0x%02x, slot:0x%02x, fn:%u, bar:%u, bus_width:%d.\n", + wb_pci_dev->name, wb_pci_dev->domain, wb_pci_dev->bus, wb_pci_dev->slot, wb_pci_dev->fn, + wb_pci_dev->bar, wb_pci_dev->bus_width); + + devfn = PCI_DEVFN(wb_pci_dev->slot, wb_pci_dev->fn); + pci_dev = pci_get_domain_bus_and_slot(wb_pci_dev->domain, wb_pci_dev->bus, devfn); + if (pci_dev == NULL) { + dev_err(&pdev->dev, "Failed to find pci_dev, domain:0x%04x, bus:0x%02x, devfn:0x%x\n", + wb_pci_dev->domain, wb_pci_dev->bus, devfn); + return -ENXIO; + } + ret = pci_setup_bars(wb_pci_dev, pci_dev); + if (ret != 0) { + dev_err(&pdev->dev, "Failed to get pci bar address.\n"); + return ret; + } + + if (!wb_pci_dev->setreg || !wb_pci_dev->getreg) { + switch (wb_pci_dev->bus_width) { + case 1: + wb_pci_dev->setreg = pci_dev_setreg_8; + wb_pci_dev->getreg = pci_dev_getreg_8; + break; + + case 2: + wb_pci_dev->setreg = pci_dev_setreg_16; + wb_pci_dev->getreg = pci_dev_getreg_16; + break; + + case 4: + wb_pci_dev->setreg = pci_dev_setreg_32; + wb_pci_dev->getreg = pci_dev_getreg_32; + break; + default: + dev_err(&pdev->dev, "Error: unsupported I/O width (%d).\n", wb_pci_dev->bus_width); + ret = -EINVAL; + goto io_unmap; + } + } + + misc = &wb_pci_dev->misc; + misc->minor = MISC_DYNAMIC_MINOR; + misc->name = wb_pci_dev->name; + misc->fops = &pcie_dev_fops; + misc->mode = 0666; + if (misc_register(misc) != 0) { + dev_err(&pdev->dev, "Failed to register %s device.\n", misc->name); + ret = -ENXIO; + goto io_unmap; + } + if (misc->minor >= MAX_PCIE_NUM) { + dev_err(&pdev->dev, "Error: device minor[%d] more than max pcie num[%d].\n", + misc->minor, MAX_PCIE_NUM); + misc_deregister(misc); + ret = -EINVAL; + goto io_unmap; + } + pcie_dev_arry[misc->minor] = wb_pci_dev; + dev_info(&pdev->dev, "%04x:%02x:%02x.%d[bar%d: %s]: register %s device with minor:%d success.\n", + wb_pci_dev->domain, wb_pci_dev->bus, wb_pci_dev->slot, wb_pci_dev->fn, wb_pci_dev->bar, + wb_pci_dev->bar_flag == IORESOURCE_MEM ? "IORESOURCE_MEM" : "IORESOURCE_IO", + misc->name, misc->minor ); + return 0; + +io_unmap: + if (wb_pci_dev->pci_mem_base) { + iounmap(wb_pci_dev->pci_mem_base); + } + return ret; +} + +static int pci_dev_remove(struct platform_device *pdev) +{ + int i; + + for (i = 0; i < MAX_PCIE_NUM ; i++) { + if (pcie_dev_arry[i] != NULL) { + if (pcie_dev_arry[i]->pci_mem_base) { + iounmap(pcie_dev_arry[i]->pci_mem_base); + } + misc_deregister(&pcie_dev_arry[i]->misc); + pcie_dev_arry[i] = NULL; + } + } + + return 0; +} + +static struct of_device_id pci_dev_match[] = { + { + .compatible = "wb-pci-dev", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, pci_dev_match); + +static struct platform_driver wb_pci_dev_driver = { + .probe = pci_dev_probe, + .remove = pci_dev_remove, + .driver = { + .owner = THIS_MODULE, + .name = PROXY_NAME, + .of_match_table = pci_dev_match, + }, +}; + +static int __init wb_pci_dev_init(void) +{ + return platform_driver_register(&wb_pci_dev_driver); +} + +static void __exit wb_pci_dev_exit(void) +{ + platform_driver_unregister(&wb_pci_dev_driver); +} + +module_init(wb_pci_dev_init); +module_exit(wb_pci_dev_exit); +MODULE_DESCRIPTION("pcie device driver"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("support"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_pcie_dev.h b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_pcie_dev.h new file mode 100644 index 000000000000..9ba0f3b457ea --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_pcie_dev.h @@ -0,0 +1,26 @@ +#ifndef __WB_PCIE_DEV_H__ +#define __WB_PCIE_DEV_H__ +#include + +#define mem_clear(data, size) memset((data), 0, (size)) + +#define UPG_TYPE 'U' +#define GET_FPGA_UPG_CTL_BASE _IOR(UPG_TYPE, 0, int) +#define GET_FPGA_UPG_FLASH_BASE _IOR(UPG_TYPE, 1, int) + +#define PCI_DEV_NAME_MAX_LEN (64) + +typedef struct pci_dev_device_s { + char pci_dev_name[PCI_DEV_NAME_MAX_LEN]; + int pci_domain; + int pci_bus; + int pci_slot; + int pci_fn; + int pci_bar; + int bus_width; + int upg_ctrl_base; + int upg_flash_base; + int device_flag; +} pci_dev_device_t; + +#endif diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_platform_i2c_dev.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_platform_i2c_dev.c new file mode 100644 index 000000000000..3fe1c4aa10f5 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_platform_i2c_dev.c @@ -0,0 +1,749 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "wb_platform_i2c_dev.h" + +#define PROXY_NAME "wb-platform-i2c-dev" +#define MAX_I2C_DEV_NUM (256) +#define FPGA_MAX_LEN (256) +#define MAX_NAME_SIZE (20) +#define MAX_BUS_WIDTH (16) +#define TRANSFER_WRITE_BUFF (FPGA_MAX_LEN + MAX_BUS_WIDTH) + +#define WIDTH_1Byte (1) +#define WIDTH_2Byte (2) +#define WIDTH_4Byte (4) + +int g_i2c_dev_debug = 0; +int g_i2c_dev_error = 0; + +module_param(g_i2c_dev_debug, int, S_IRUGO | S_IWUSR); +module_param(g_i2c_dev_error, int, S_IRUGO | S_IWUSR); + +#define I2C_DEV_DEBUG_DMESG(fmt, args...) do { \ + if (g_i2c_dev_debug) { \ + printk(KERN_ERR "[I2C_DEV][DEBUG][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +#define I2C_DEV_DEBUG_ERROR(fmt, args...) do { \ + if (g_i2c_dev_error) { \ + printk(KERN_ERR "[I2C_DEV][ERR][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +static struct platform_i2c_dev_info* i2c_dev_arry[MAX_I2C_DEV_NUM]; + +struct platform_i2c_dev_info { + uint32_t i2c_bus; + uint32_t i2c_addr; + const char *name; + uint32_t data_bus_width; + uint32_t addr_bus_width; + uint32_t per_rd_len; + uint32_t per_wr_len; + struct miscdevice misc; +}; + +static int transfer_read(struct platform_i2c_dev_info *i2c_dev, u8 *buf, loff_t regaddr, size_t count) +{ + int i, j; + struct i2c_adapter *adap; + union i2c_smbus_data data; + u8 offset_buf[MAX_BUS_WIDTH]; + struct i2c_msg msgs[2]; + int msgs_num, ret; + u8 offset; + u8 length; + + if (!i2c_dev) { + I2C_DEV_DEBUG_ERROR("can't get read i2c_dev\r\n"); + return -ENODEV; + } + + i = 0; + + mem_clear(offset_buf, sizeof(offset_buf)); + + switch (i2c_dev->addr_bus_width) { + case WIDTH_4Byte: + offset_buf[i++] = (regaddr >> 24) & 0xFF; + offset_buf[i++] = (regaddr >> 16) & 0xFF; + offset_buf[i++] = (regaddr >> 8) & 0xFF; + offset_buf[i++] = regaddr & 0xFF; + break; + case WIDTH_2Byte: + offset_buf[i++] = (regaddr >> 8) & 0xFF; + offset_buf[i++] = regaddr & 0xFF; + break; + case WIDTH_1Byte: + offset_buf[i++] = regaddr & 0xFF; + break; + default: + I2C_DEV_DEBUG_ERROR("Only support 1,2,4 Byte Address Width,but set width = %u\r\n", i2c_dev->addr_bus_width); + return -EINVAL; + } + + adap = i2c_get_adapter(i2c_dev->i2c_bus); + if (adap == NULL) { + I2C_DEV_DEBUG_ERROR("get i2c adapter %d faild.\n", i2c_dev->i2c_bus); + return -ENXIO; + } + + if (adap->algo->master_xfer) { + mem_clear(msgs, sizeof(msgs)); + msgs[0].addr = i2c_dev->i2c_addr; + msgs[0].flags = 0; + msgs[0].len = i2c_dev->addr_bus_width; + msgs[0].buf = offset_buf; + + msgs[1].addr = i2c_dev->i2c_addr; + msgs[1].flags = I2C_M_RD; + msgs[1].len = count; + msgs[1].buf = buf; + + msgs_num = 2; + ret = i2c_transfer(adap, msgs, msgs_num); + if (ret != msgs_num) { + I2C_DEV_DEBUG_ERROR("i2c_transfer read error\r\n"); + ret = -EFAULT; + goto error_exit; + } + } else { + if (i2c_dev->addr_bus_width == WIDTH_1Byte) { + offset = regaddr & 0xFF; + if (i2c_check_functionality(adap, I2C_FUNC_SMBUS_READ_I2C_BLOCK)) { + for (j = 0; j < count; j += I2C_SMBUS_BLOCK_MAX) { + if (count - j > I2C_SMBUS_BLOCK_MAX) { + length = I2C_SMBUS_BLOCK_MAX; + } else { + length = count - j; + } + data.block[0] = length; + ret = adap->algo->smbus_xfer(adap, i2c_dev->i2c_addr, + 0, + I2C_SMBUS_READ, + offset, I2C_SMBUS_I2C_BLOCK_DATA, &data); + if (ret) { + I2C_DEV_DEBUG_ERROR("smbus_xfer read block error, ret = %d\r\n", ret); + ret = -EFAULT; + goto error_exit; + } + memcpy(buf + j, data.block + 1, length); + offset += length; + } + } else { + for (j = 0; j < count; j++) { + ret = adap->algo->smbus_xfer(adap, i2c_dev->i2c_addr, + 0, + I2C_SMBUS_READ, + offset, I2C_SMBUS_BYTE_DATA, &data); + + if (!ret) { + buf[j] = data.byte; + } else { + I2C_DEV_DEBUG_ERROR("smbus_xfer read byte error, ret = %d\r\n", ret); + ret = -EFAULT; + goto error_exit; + } + offset++; + } + } + } else { + I2C_DEV_DEBUG_ERROR("smbus_xfer not support addr_bus_width = %d\r\n", i2c_dev->addr_bus_width); + ret = -EINVAL; + goto error_exit; + } + } + + i2c_put_adapter(adap); + return 0; +error_exit: + i2c_put_adapter(adap); + return ret; +} + +static int transfer_write(struct platform_i2c_dev_info *i2c_dev, u8 *buf, loff_t regaddr, size_t count) +{ + int i, j; + struct i2c_adapter *adap; + union i2c_smbus_data data; + u8 offset_buf[TRANSFER_WRITE_BUFF]; + struct i2c_msg msgs[1]; + int msgs_num, ret; + u8 offset; + u8 length; + + if (!i2c_dev) { + I2C_DEV_DEBUG_ERROR("can't get read i2c_dev\r\n"); + return -ENODEV; + } + + i = 0; + + mem_clear(offset_buf, sizeof(offset_buf)); + + switch (i2c_dev->addr_bus_width) { + case WIDTH_4Byte: + offset_buf[i++] = (regaddr >> 24) & 0xFF; + offset_buf[i++] = (regaddr >> 16) & 0xFF; + offset_buf[i++] = (regaddr >> 8) & 0xFF; + offset_buf[i++] = regaddr & 0xFF; + break; + case WIDTH_2Byte: + offset_buf[i++] = (regaddr >> 8) & 0xFF; + offset_buf[i++] = regaddr & 0xFF; + break; + case WIDTH_1Byte: + offset_buf[i++] = regaddr & 0xFF; + break; + default: + I2C_DEV_DEBUG_ERROR("Only support 1,2,4 Byte Address Width,but set width = %u\r\n", i2c_dev->addr_bus_width); + return -EINVAL; + } + + memcpy(offset_buf + i2c_dev->addr_bus_width, buf, count); + + adap = i2c_get_adapter(i2c_dev->i2c_bus); + if (adap == NULL) { + I2C_DEV_DEBUG_ERROR("get i2c adapter %d faild.\n", i2c_dev->i2c_bus); + return -ENXIO; + } + + if (adap->algo->master_xfer) { + mem_clear(msgs, sizeof(msgs)); + + msgs[0].addr = i2c_dev->i2c_addr; + msgs[0].flags = 0; + msgs[0].len = i2c_dev->addr_bus_width + count; + msgs[0].buf = offset_buf; + + msgs_num = 1; + ret = i2c_transfer(adap, msgs, msgs_num); + if (ret != msgs_num) { + I2C_DEV_DEBUG_ERROR("i2c_transfer write error\r\n"); + ret = -EFAULT; + goto error_exit; + } + } else { + if (i2c_dev->addr_bus_width == WIDTH_1Byte) { + offset = regaddr & 0xFF; + if (i2c_check_functionality(adap, I2C_FUNC_SMBUS_WRITE_I2C_BLOCK)) { + for (j = 0; j < count; j += I2C_SMBUS_BLOCK_MAX) { + if (count - j > I2C_SMBUS_BLOCK_MAX) { + length = I2C_SMBUS_BLOCK_MAX; + } else { + length = count - j; + } + data.block[0] = length; + memcpy(data.block + 1, buf + j, length); + ret = adap->algo->smbus_xfer(adap, i2c_dev->i2c_addr, + 0, + I2C_SMBUS_WRITE, + offset, I2C_SMBUS_I2C_BLOCK_DATA, &data); + if (ret) { + I2C_DEV_DEBUG_ERROR("smbus_xfer write block error, ret = %d\r\n", ret); + ret = -EFAULT; + goto error_exit; + } + offset += length; + } + } else { + for (j = 0; j < count; j++) { + data.byte = buf[j]; + ret = adap->algo->smbus_xfer(adap, i2c_dev->i2c_addr, + 0, + I2C_SMBUS_WRITE, + offset, I2C_SMBUS_BYTE_DATA, &data); + if (ret) { + I2C_DEV_DEBUG_ERROR("smbus_xfer write byte error, ret = %d\r\n", ret); + ret = -EFAULT; + goto error_exit; + } + offset += 1; + } + } + } else { + I2C_DEV_DEBUG_ERROR("smbus_xfer not support addr_bus_width = %d\r\n", i2c_dev->addr_bus_width); + ret = -EINVAL; + goto error_exit; + } + } + + i2c_put_adapter(adap); + return 0; +error_exit: + i2c_put_adapter(adap); + return ret; +} + +static long i2c_dev_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + return 0; +} + +static int i2c_dev_open(struct inode *inode, struct file *file) +{ + unsigned int minor = iminor(inode); + struct platform_i2c_dev_info *i2c_dev; + + i2c_dev = i2c_dev_arry[minor]; + if (i2c_dev == NULL) { + return -ENODEV; + } + + file->private_data = i2c_dev; + + return 0; +} + +static int i2c_dev_release(struct inode *inode, struct file *file) +{ + file->private_data = NULL; + + return 0; +} + +static int device_read(struct platform_i2c_dev_info *i2c_dev, uint32_t offset, uint8_t *buf, int count) +{ + int i, j, ret; + u8 tmp_offset; + u8 val[FPGA_MAX_LEN]; + u32 width, rd_len, per_len, tmp; + u32 max_per_len; + + width = i2c_dev->data_bus_width; + switch (width) { + case WIDTH_4Byte: + tmp_offset = offset & 0x3; + if (tmp_offset) { + I2C_DEV_DEBUG_ERROR("data bus width:%u, offset:%u, read size %d invalid.\r\n", width, offset, count); + return -EINVAL; + } + break; + case WIDTH_2Byte: + tmp_offset = offset & 0x1; + if (tmp_offset) { + I2C_DEV_DEBUG_ERROR("data bus width:%u, offset:%u, read size %d invalid.\r\n", width, offset, count); + return -EINVAL; + } + break; + case WIDTH_1Byte: + break; + default: + I2C_DEV_DEBUG_ERROR("Only support 1,2,4 Byte Data Width,but set width = %u\r\n", width); + return -EINVAL; + } + + max_per_len = i2c_dev->per_rd_len; + tmp = (width - 1) & count; + rd_len = (tmp == 0) ? count : count + width - tmp; + per_len = (rd_len > max_per_len) ? (max_per_len) : (rd_len); + + mem_clear(val, sizeof(val)); + for (i = 0; i < rd_len; i += per_len) { + ret = transfer_read(i2c_dev, val + i, offset + i, per_len); + if (ret < 0) { + I2C_DEV_DEBUG_ERROR("read error.read offset = %u\r\n", (offset + i)); + return -EFAULT; + } + } + + if (width == WIDTH_1Byte) { + memcpy(buf, val, count); + } else { + for (i = 0; i < count; i += width) { + for (j = 0; (j < width) && (i + j < count); j++) { + buf[i + j] = val[i + width - j - 1]; + } + } + } + + return 0; +} + +static int device_write(struct platform_i2c_dev_info *i2c_dev, uint32_t offset, uint8_t *buf, size_t count) +{ + int i, j, ret; + u8 tmp_offset; + u32 width; + u8 val[FPGA_MAX_LEN]; + u32 wr_len, per_len, tmp; + u32 max_per_len; + + width = i2c_dev->data_bus_width; + switch (width) { + case WIDTH_4Byte: + tmp_offset = offset & 0x3; + if (tmp_offset) { + I2C_DEV_DEBUG_ERROR("data bus width:%u, offset:%u, read size %lu invalid.\r\n", width, offset, count); + return -EINVAL; + } + break; + case WIDTH_2Byte: + tmp_offset = offset & 0x1; + if (tmp_offset) { + I2C_DEV_DEBUG_ERROR("data bus width:%u, offset:%u, read size %lu invalid.\r\n", width, offset, count); + return -EINVAL; + } + break; + case WIDTH_1Byte: + break; + default: + I2C_DEV_DEBUG_ERROR("Only support 1,2,4 Byte Data Width,but set width = %u\r\n", width); + return -EINVAL; + } + + mem_clear(val, sizeof(val)); + + if (width == WIDTH_1Byte) { + memcpy(val, buf, count); + } else { + for (i = 0; i < count; i += width) { + for (j = 0; (j < width) && (i + j < count); j++) { + val[i + width - j - 1] = buf[i + j]; + } + } + } + + max_per_len = i2c_dev->per_wr_len; + tmp = (width - 1) & count; + wr_len = (tmp == 0) ? count : count + width - tmp; + per_len = (wr_len > max_per_len) ? (max_per_len) : (wr_len); + + for (i = 0; i < wr_len; i += per_len) { + ret = transfer_write(i2c_dev, val + i, offset + i, per_len); + if (ret < 0) { + I2C_DEV_DEBUG_ERROR("write error.offset = %u\r\n", (offset + i)); + return -EFAULT; + } + } + return 0; +} + +static ssize_t i2c_dev_read(struct file *file, char __user *buf, size_t count, loff_t *offset) +{ + u8 val[FPGA_MAX_LEN]; + int ret; + struct platform_i2c_dev_info *i2c_dev; + + if (count <= 0 || count > sizeof(val)) { + I2C_DEV_DEBUG_ERROR("read conut %lu , beyond max:%lu.\n", count, sizeof(val)); + return -EINVAL; + } + + i2c_dev = file->private_data; + if (i2c_dev == NULL) { + I2C_DEV_DEBUG_ERROR("can't get read private_data .\r\n"); + return -EINVAL; + } + + ret = device_read(i2c_dev, (uint32_t)*offset, val, count); + if (ret < 0) { + I2C_DEV_DEBUG_ERROR("i2c dev read failed, dev name:%s, offset:0x%x, len:%lu.\n", + i2c_dev->name, (uint32_t)*offset, count); + return -EINVAL; + } + + if (copy_to_user(buf, val, count)) { + I2C_DEV_DEBUG_ERROR("copy_to_user error \r\n"); + return -EFAULT; + } else{ + *offset += count; + } + + return count; +} + +static ssize_t i2c_dev_write(struct file *file, const char __user *buf, size_t count, loff_t *offset) +{ + u8 val[FPGA_MAX_LEN]; + int ret; + struct platform_i2c_dev_info *i2c_dev; + + if (count <= 0 || count > sizeof(val)) { + I2C_DEV_DEBUG_ERROR("write conut %lu, beyond max val:%lu.\n", count, sizeof(val)); + return -EINVAL; + } + + i2c_dev = file->private_data; + if (i2c_dev == NULL) { + I2C_DEV_DEBUG_ERROR("get write private_data error.\r\n"); + return -EINVAL; + } + + mem_clear(val, sizeof(val)); + if (copy_from_user(val, buf, count)) { + I2C_DEV_DEBUG_ERROR("copy_from_user error.\r\n"); + return -EFAULT; + } + + ret = device_write (i2c_dev, (uint32_t)*offset, val, count); + if (ret < 0) { + I2C_DEV_DEBUG_ERROR("i2c dev write failed, dev name:%s, offset:0x%llx, len:%lu.\n", + i2c_dev->name, *offset, count); + return -EINVAL; + } + + *offset += count; + return count; +} + +static loff_t i2c_dev_llseek(struct file *file, loff_t offset, int origin) +{ + loff_t ret = 0; + + switch (origin) { + case SEEK_SET: + if (offset < 0) { + I2C_DEV_DEBUG_ERROR("SEEK_SET, offset:%lld, invalid.\r\n", offset); + ret = -EINVAL; + break; + } + file->f_pos = offset; + ret = file->f_pos; + break; + case SEEK_CUR: + if (file->f_pos + offset < 0) { + I2C_DEV_DEBUG_ERROR("SEEK_CUR out of range, f_ops:%lld, offset:%lld.\n", + file->f_pos, offset); + } + file->f_pos += offset; + ret = file->f_pos; + break; + default: + I2C_DEV_DEBUG_ERROR("unsupport llseek type:%d.\n", origin); + ret = -EINVAL; + break; + } + return ret; +} + +static const struct file_operations i2c_dev_fops = { + .owner = THIS_MODULE, + .llseek = i2c_dev_llseek, + .read = i2c_dev_read, + .write = i2c_dev_write, + .unlocked_ioctl = i2c_dev_ioctl, + .open = i2c_dev_open, + .release = i2c_dev_release, +}; + +static struct platform_i2c_dev_info * dev_match(const char *path) +{ + struct platform_i2c_dev_info *i2c_dev; + char dev_name[MAX_NAME_SIZE]; + int i; + for (i = 0; i < MAX_I2C_DEV_NUM; i++) { + if (i2c_dev_arry[ i ] == NULL) { + continue; + } + i2c_dev = i2c_dev_arry[ i ]; + snprintf(dev_name, MAX_NAME_SIZE,"/dev/%s", i2c_dev->name); + if (!strcmp(path, dev_name)) { + I2C_DEV_DEBUG_DMESG("get dev_name = %s, minor = %d\n", dev_name, i); + return i2c_dev; + } + } + + return NULL; +} + +int platform_i2c_device_func_read(const char *path, uint32_t offset, uint8_t *buf, size_t count) +{ + struct platform_i2c_dev_info *i2c_dev = NULL; + int ret; + + if(path == NULL){ + I2C_DEV_DEBUG_ERROR("path NULL"); + return -EINVAL; + } + + if(buf == NULL){ + I2C_DEV_DEBUG_ERROR("buf NULL"); + return -EINVAL; + } + + if (count > FPGA_MAX_LEN) { + I2C_DEV_DEBUG_ERROR("read conut %lu, beyond max:%d.\n", count, FPGA_MAX_LEN); + return -EINVAL; + } + + i2c_dev = dev_match(path); + if (i2c_dev == NULL) { + I2C_DEV_DEBUG_ERROR("i2c_dev match failed. dev path = %s", path); + return -EINVAL; + } + + ret = device_read(i2c_dev, offset, buf, count); + if (ret < 0) { + I2C_DEV_DEBUG_ERROR("fpga i2c dev read failed, dev name:%s, offset:0x%x, len:%lu.\n", + i2c_dev->name, offset, count); + return -EINVAL; + } + + return count; +} +EXPORT_SYMBOL(platform_i2c_device_func_read); + +int platform_i2c_device_func_write(const char *path, uint32_t offset, uint8_t *buf, size_t count) +{ + struct platform_i2c_dev_info *i2c_dev = NULL; + int ret; + + if(path == NULL){ + I2C_DEV_DEBUG_ERROR("path NULL"); + return -EINVAL; + } + + if(buf == NULL){ + I2C_DEV_DEBUG_ERROR("buf NULL"); + return -EINVAL; + } + + if (count > FPGA_MAX_LEN) { + I2C_DEV_DEBUG_ERROR("write conut %lu, beyond max:%d.\n", count, FPGA_MAX_LEN); + return -EINVAL; + } + + i2c_dev = dev_match(path); + if (i2c_dev == NULL) { + I2C_DEV_DEBUG_ERROR("i2c_dev match failed. dev path = %s", path); + return -EINVAL; + } + + ret = device_write (i2c_dev, offset, buf, count); + if (ret < 0) { + I2C_DEV_DEBUG_ERROR("i2c dev write failed, dev name:%s, offset:0x%x, len:%lu.\n", + i2c_dev->name, offset, count); + return -EINVAL; + } + + return count; +} +EXPORT_SYMBOL(platform_i2c_device_func_write); + +static int platform_i2c_dev_probe(struct platform_device *pdev) +{ + int ret = 0; + struct platform_i2c_dev_info *i2c_dev; + struct miscdevice *misc; + platform_i2c_dev_device_t *platform_i2c_dev_device; + + i2c_dev = devm_kzalloc(&pdev->dev, sizeof(struct platform_i2c_dev_info), GFP_KERNEL); + if (!i2c_dev) { + dev_err(&pdev->dev, "devm_kzalloc error. \r\n"); + return -ENOMEM; + } + + if (pdev->dev.of_node) { + + ret += of_property_read_u32(pdev->dev.of_node, "i2c_bus", &i2c_dev->i2c_bus); + ret += of_property_read_u32(pdev->dev.of_node, "i2c_addr", &i2c_dev->i2c_addr); + ret += of_property_read_string(pdev->dev.of_node, "i2c_name", &i2c_dev->name); + ret += of_property_read_u32(pdev->dev.of_node, "data_bus_width", &i2c_dev->data_bus_width); + ret += of_property_read_u32(pdev->dev.of_node, "addr_bus_width", &i2c_dev->addr_bus_width); + ret += of_property_read_u32(pdev->dev.of_node, "per_rd_len", &i2c_dev->per_rd_len); + ret += of_property_read_u32(pdev->dev.of_node, "per_wr_len", &i2c_dev->per_wr_len); + if (ret != 0) { + dev_err(&pdev->dev, "dts config error.ret:%d.\r\n", ret); + return -ENXIO; + } + } else { + if (pdev->dev.platform_data == NULL) { + dev_err(&pdev->dev, "Failed to get platform data config.\n"); + return -ENXIO; + } + platform_i2c_dev_device = pdev->dev.platform_data; + i2c_dev->i2c_bus = platform_i2c_dev_device->i2c_bus; + i2c_dev->i2c_addr = platform_i2c_dev_device->i2c_addr; + i2c_dev->name = platform_i2c_dev_device->i2c_name; + i2c_dev->data_bus_width = platform_i2c_dev_device->data_bus_width; + i2c_dev->addr_bus_width = platform_i2c_dev_device->addr_bus_width; + i2c_dev->per_rd_len = platform_i2c_dev_device->per_rd_len; + i2c_dev->per_wr_len = platform_i2c_dev_device->per_wr_len; + } + + if ((i2c_dev->per_rd_len & (i2c_dev->data_bus_width - 1)) || (i2c_dev->per_wr_len & (i2c_dev->data_bus_width - 1))) { + dev_err(&pdev->dev, "Invalid config per_rd_len %d per_wr_len %d data bus_width %d.\r\n", i2c_dev->per_rd_len, + i2c_dev->per_wr_len, i2c_dev->data_bus_width); + return -ENXIO; + } + + misc = &i2c_dev->misc; + misc->minor = MISC_DYNAMIC_MINOR; + misc->name = i2c_dev->name; + misc->fops = &i2c_dev_fops; + if (misc_register(misc) != 0) { + dev_err(&pdev->dev, "register %s faild.\r\n", misc->name); + return -ENXIO; + } + + if (misc->minor >= MAX_I2C_DEV_NUM) { + dev_err(&pdev->dev, "minor number beyond the limit! is %d.\r\n", misc->minor); + misc_deregister(misc); + return -ENXIO; + } + i2c_dev_arry[misc->minor] = i2c_dev; + + dev_info(&pdev->dev, "register %u addr_bus_width %u data_bus_width device %s with %u per_rd_len %u per_wr_len success.\r\n", + i2c_dev->addr_bus_width, i2c_dev->data_bus_width, i2c_dev->name, i2c_dev->per_rd_len, i2c_dev->per_wr_len); + + return 0; +} + +static int platform_i2c_dev_remove(struct platform_device *pdev) +{ + int i; + + for (i = 0; i < MAX_I2C_DEV_NUM ; i++) { + if (i2c_dev_arry[i] != NULL) { + misc_deregister(&i2c_dev_arry[i]->misc); + i2c_dev_arry[i] = NULL; + } + } + + return 0; +} + +static const struct of_device_id platform_i2c_dev_of_match[] = { + { .compatible = "wb-platform-i2c-dev" }, + { }, +}; +MODULE_DEVICE_TABLE(of, platform_i2c_dev_of_match); + +static struct platform_driver wb_platform_i2c_dev_driver = { + .probe = platform_i2c_dev_probe, + .remove = platform_i2c_dev_remove, + .driver = { + .owner = THIS_MODULE, + .name = PROXY_NAME, + .of_match_table = platform_i2c_dev_of_match, + }, +}; + +static int __init wb_platform_i2c_dev_init(void) +{ + return platform_driver_register(&wb_platform_i2c_dev_driver); +} + +static void __exit wb_platform_i2c_dev_exit(void) +{ + platform_driver_unregister(&wb_platform_i2c_dev_driver); +} + +module_init(wb_platform_i2c_dev_init); +module_exit(wb_platform_i2c_dev_exit); + +MODULE_DESCRIPTION("platform i2c dev driver"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("support"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_platform_i2c_dev.h b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_platform_i2c_dev.h new file mode 100644 index 000000000000..b5158c9fec57 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_platform_i2c_dev.h @@ -0,0 +1,19 @@ +#ifndef __WB_PLATFORM_I2C_DEV_H__ +#define __WB_PLATFORM_I2C_DEV_H__ +#include + +#define mem_clear(data, size) memset((data), 0, (size)) +#define I2C_DEV_NAME_MAX_LEN (64) + +typedef struct platform_i2c_dev_device_s { + uint32_t i2c_bus; + uint32_t i2c_addr; + char i2c_name[I2C_DEV_NAME_MAX_LEN]; + uint32_t data_bus_width; + uint32_t addr_bus_width; + uint32_t per_rd_len; + uint32_t per_wr_len; + int device_flag; +} platform_i2c_dev_device_t; + +#endif diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_spi_93xx46.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_spi_93xx46.c new file mode 100644 index 000000000000..abc4f1567aec --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_spi_93xx46.c @@ -0,0 +1,111 @@ +/* + * EEPROMs access control driver for display configuration EEPROMs + * on DigsyMTC board. + * + * (C) 2011 DENX Software Engineering, Anatolij Gustschin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define DEFAULT_SPI_BUS_NUM (0) +#define DEFAULT_SPI_CS_NUM (0) +#define DEFAULT_SPI_HZ (100000) + +#define GPIO_EEPROM_CS (-1) + +int g_wb_spi_93xx46_debug = 0; +int g_wb_spi_93xx46_error = 0; +int spi_bus_num = DEFAULT_SPI_BUS_NUM; +int spi_cs_gpio = GPIO_EEPROM_CS; + +module_param(g_wb_spi_93xx46_debug, int, S_IRUGO | S_IWUSR); +module_param(g_wb_spi_93xx46_error, int, S_IRUGO | S_IWUSR); +module_param(spi_bus_num, int, S_IRUGO | S_IWUSR); +module_param(spi_cs_gpio, int, S_IRUGO | S_IWUSR); + +#define SPI_93xx46_DEBUG_VERBOSE(fmt, args...) do { \ + if (g_wb_spi_93xx46_debug) { \ + printk(KERN_INFO "[SPI-93xx46][VER][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +#define SPI_93xx46_DEBUG_ERROR(fmt, args...) do { \ + if (g_wb_spi_93xx46_error) { \ + printk(KERN_ERR "[SPI-93xx46][ERR][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +struct eeprom_93xx46_platform_data eeprom_data = { + .flags = EE_ADDR16, + .quirks = EEPROM_93XX46_QUIRK_SINGLE_WORD_READ, +}; + +struct spi_board_info eeprom_93xx46_info __initdata = { + .modalias = "wb_93xx46", + .max_speed_hz = DEFAULT_SPI_HZ, + .bus_num = DEFAULT_SPI_BUS_NUM, + .chip_select = DEFAULT_SPI_CS_NUM, + .mode = SPI_MODE_0 | SPI_CS_HIGH, + .controller_data = (void *)GPIO_EEPROM_CS, + .platform_data = &eeprom_data, +}; + +static struct spi_device *g_spi_device; + +static int __init wb_spi_93xx46_init(void) +{ + struct spi_master *master; + + SPI_93xx46_DEBUG_VERBOSE("Enter.\n"); + + eeprom_93xx46_info.bus_num = spi_bus_num; + eeprom_93xx46_info.controller_data = (void *)(long)spi_cs_gpio; + master = spi_busnum_to_master(eeprom_93xx46_info.bus_num); + if (!master) { + SPI_93xx46_DEBUG_ERROR("get bus_num %u spi master failed.\n", + eeprom_93xx46_info.bus_num); + return -EINVAL; + } + + g_spi_device = spi_new_device(master, &eeprom_93xx46_info); + put_device(&master->dev); + if (!g_spi_device) { + SPI_93xx46_DEBUG_ERROR("register spi new device failed.\n"); + return -EPERM; + } + + if (g_wb_spi_93xx46_debug) { + dev_info(&g_spi_device->dev, "register %u bus_num spi 93xx46 eeprom success\n", + eeprom_93xx46_info.bus_num); + } + + return 0; +} + +static void __exit wb_spi_93xx46_exit(void) +{ + spi_unregister_device(g_spi_device); + + if (g_wb_spi_93xx46_debug) { + dev_info(&g_spi_device->dev, "unregister spi 93xx46 eeprom success\n"); + } + + return; +} + +module_init(wb_spi_93xx46_init); +module_exit(wb_spi_93xx46_exit); + +MODULE_AUTHOR("support"); +MODULE_DESCRIPTION("create 93xx46 eeprom device"); +MODULE_LICENSE("GPL"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_spi_dev.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_spi_dev.c new file mode 100644 index 000000000000..807663592db4 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_spi_dev.c @@ -0,0 +1,583 @@ +/* + * wb_spi_dev.c + * ko to read/write spi device through /dev/XXX device + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "wb_spi_dev.h" + +#define MAX_SPI_DEV_NUM (256) +#define MAX_RW_LEN (256) +#define MAX_NAME_SIZE (20) +#define MAX_ADDR_BUS_WIDTH (4) + +#define TRANSFER_WRITE_BUFF (1 + MAX_ADDR_BUS_WIDTH + MAX_RW_LEN) + +#define WIDTH_1Byte (1) +#define WIDTH_2Byte (2) +#define WIDTH_4Byte (4) + +#define OP_READ (0x3) +#define OP_WRITE (0x2) + +int g_spi_dev_debug = 0; +int g_spi_dev_error = 0; + +module_param(g_spi_dev_debug, int, S_IRUGO | S_IWUSR); +module_param(g_spi_dev_error, int, S_IRUGO | S_IWUSR); + +#define SPI_DEV_DEBUG(fmt, args...) do { \ + if (g_spi_dev_debug) { \ + printk(KERN_ERR "[SPI_DEV][DEBUG][func:%s line:%d]\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +#define SPI_DEV_ERROR(fmt, args...) do { \ + if (g_spi_dev_error) { \ + printk(KERN_ERR "[SPI_DEV][ERR][func:%s line:%d]\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +static struct spi_dev_info* spi_dev_arry[MAX_SPI_DEV_NUM]; + +struct spi_dev_info { + const char *name; + uint32_t data_bus_width; + uint32_t addr_bus_width; + uint32_t per_rd_len; + uint32_t per_wr_len; + struct miscdevice misc; + struct spi_device *spi_device; +}; + +static int transfer_read(struct spi_dev_info *spi_dev, u8 *buf, uint32_t regaddr, size_t count) +{ + int i, ret; + u8 tx_buf[MAX_ADDR_BUS_WIDTH + 1]; + struct spi_message m; + struct spi_transfer xfer[2]; + + i = 0; + mem_clear(tx_buf, sizeof(tx_buf)); + tx_buf[i++] = OP_READ; + + switch (spi_dev->addr_bus_width) { + case WIDTH_4Byte: + tx_buf[i++] = (regaddr >> 24) & 0xFF; + tx_buf[i++] = (regaddr >> 16) & 0xFF; + tx_buf[i++] = (regaddr >> 8) & 0xFF; + tx_buf[i++] = regaddr & 0xFF; + break; + case WIDTH_2Byte: + tx_buf[i++] = (regaddr >> 8) & 0xFF; + tx_buf[i++] = regaddr & 0xFF; + break; + case WIDTH_1Byte: + tx_buf[i++] = regaddr & 0xFF; + break; + default: + SPI_DEV_ERROR("Only support 1,2,4 Byte Width,but set width = %u\n", + spi_dev->addr_bus_width); + return -EINVAL; + } + + mem_clear(xfer, sizeof(xfer)); + spi_message_init(&m); + xfer[0].tx_buf = tx_buf; + xfer[0].len = spi_dev->addr_bus_width + 1; + spi_message_add_tail(&xfer[0], &m); + + xfer[1].rx_buf = buf; + xfer[1].len = count; + spi_message_add_tail(&xfer[1], &m); + + ret = spi_sync(spi_dev->spi_device, &m); + if (ret) { + SPI_DEV_ERROR("transfer_read failed, reg addr:0x%x, len:%lu, ret:%d.\n", + regaddr, count, ret); + return -EIO; + } + return 0; +} + +static int transfer_write(struct spi_dev_info *spi_dev, u8 *buf, uint32_t regaddr, size_t count) +{ + int i, ret; + u8 tx_buf[TRANSFER_WRITE_BUFF]; + struct spi_message m; + struct spi_transfer xfer ; + + i = 0; + mem_clear(tx_buf, sizeof(tx_buf)); + tx_buf[i++] = OP_WRITE; + switch (spi_dev->addr_bus_width) { + case WIDTH_4Byte: + tx_buf[i++] = (regaddr >> 24) & 0xFF; + tx_buf[i++] = (regaddr >> 16) & 0xFF; + tx_buf[i++] = (regaddr >> 8) & 0xFF; + tx_buf[i++] = regaddr & 0xFF; + break; + case WIDTH_2Byte: + tx_buf[i++] = (regaddr >> 8) & 0xFF; + tx_buf[i++] = regaddr & 0xFF; + break; + case WIDTH_1Byte: + tx_buf[i++] = regaddr & 0xFF; + break; + default: + SPI_DEV_ERROR("Only support 1,2,4 Byte Width, but set width = %u\n", + spi_dev->addr_bus_width); + return -EINVAL; + } + + memcpy(tx_buf + i, buf, count); + + mem_clear(&xfer, sizeof(xfer)); + spi_message_init(&m); + xfer.tx_buf = tx_buf; + xfer.len = count + i; + spi_message_add_tail(&xfer, &m); + + ret = spi_sync(spi_dev->spi_device, &m); + if (ret) { + SPI_DEV_ERROR("transfer_write failed, reg addr:0x%x, len:%lu, ret:%d.\n", + regaddr, count, ret); + return -EIO; + } + return 0; +} + +static long spi_dev_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + return 0; +} + +static int spi_dev_open(struct inode *inode, struct file *file) +{ + unsigned int minor = iminor(inode); + struct spi_dev_info *spi_dev; + + if (minor >= MAX_SPI_DEV_NUM) { + SPI_DEV_ERROR("minor out of range, minor = %d.\n", minor); + return -ENODEV; + } + + spi_dev = spi_dev_arry[minor]; + if (spi_dev == NULL) { + SPI_DEV_ERROR("spi_dev is NULL, open failed, minor = %d\n", minor); + return -ENODEV; + } + + file->private_data = spi_dev; + + return 0; +} + +static int spi_dev_release(struct inode *inode, struct file *file) +{ + file->private_data = NULL; + + return 0; +} + +static int device_read(struct spi_dev_info *spi_dev, uint32_t offset, uint8_t *buf, size_t count) +{ + int i, j, ret; + u8 val[MAX_RW_LEN]; + u32 data_width, rd_len, per_len, tmp; + u32 max_per_len; + + data_width = spi_dev->data_bus_width; + + if (offset % data_width) { + SPI_DEV_ERROR("data bus width:%d, offset:0x%x, read size %lu invalid.\n", + data_width, offset, count); + return -EINVAL; + } + + max_per_len = spi_dev->per_rd_len; + tmp = (data_width - 1) & count; + rd_len = (tmp == 0) ? count : count + data_width - tmp; + per_len = (rd_len > max_per_len) ? (max_per_len) : (rd_len); + + mem_clear(val, sizeof(val)); + for (i = 0; i < rd_len; i += per_len) { + ret = transfer_read(spi_dev, val + i, offset + i, per_len); + if (ret < 0) { + SPI_DEV_ERROR("read error.read offset = %u\n", (offset + i)); + return -EFAULT; + } + } + + if (data_width == WIDTH_1Byte) { + memcpy(buf, val, count); + } else { + for (i = 0; i < count; i += data_width) { + for (j = 0; (j < data_width) && (i + j < count); j++) { + buf[i + j] = val[i + data_width - j - 1]; + } + } + } + + return 0; +} + +static int device_write(struct spi_dev_info *spi_dev, uint32_t offset, uint8_t *buf, size_t count) +{ + int i, j, ret; + u32 data_width; + u8 val[MAX_RW_LEN]; + u32 wr_len, per_len, tmp; + u32 max_per_len; + + data_width = spi_dev->data_bus_width; + + if (offset % data_width) { + SPI_DEV_ERROR("data bus width:%d, offset:0x%x, read size %lu invalid.\n", + data_width, offset, count); + return -EINVAL; + } + mem_clear(val, sizeof(val)); + + if (data_width == WIDTH_1Byte) { + memcpy(val, buf, count); + } else { + for (i = 0; i < count; i += data_width) { + for (j = 0; (j < data_width) && (i + j < count); j++) { + val[i + data_width - j - 1] = buf[i + j]; + } + } + } + + max_per_len = spi_dev->per_wr_len; + tmp = (data_width - 1) & count; + wr_len = (tmp == 0) ? count : count + data_width - tmp; + per_len = (wr_len > max_per_len) ? (max_per_len) : (wr_len); + + for (i = 0; i < wr_len; i += per_len) { + ret = transfer_write(spi_dev, val + i, offset + i, per_len); + if (ret < 0) { + SPI_DEV_ERROR("write error.offset = %u\n", (offset + i)); + return -EFAULT; + } + } + return 0; +} + +static ssize_t spi_dev_read(struct file *file, char __user *buf, size_t count, loff_t *offset) +{ + u8 val[MAX_RW_LEN]; + int ret; + struct spi_dev_info *spi_dev; + + if (count <= 0 || count > sizeof(val)) { + SPI_DEV_ERROR("read conut %lu , beyond max:%lu.\n", count, sizeof(val)); + return -EINVAL; + } + + spi_dev = file->private_data; + if (spi_dev == NULL) { + SPI_DEV_ERROR("can't get read private_data .\n"); + return -EINVAL; + } + + ret = device_read(spi_dev, (uint32_t)*offset, val, count); + if (ret < 0) { + SPI_DEV_ERROR("spi dev read failed, dev name:%s, offset:0x%x, len:%lu.\n", + spi_dev->name, (uint32_t)*offset, count); + return -EINVAL; + } + + if (copy_to_user(buf, val, count)) { + SPI_DEV_ERROR("copy_to_user error \n"); + return -EFAULT; + } else{ + *offset += count; + } + + return count; +} + +static ssize_t spi_dev_write(struct file *file, const char __user *buf, + size_t count, loff_t *offset) +{ + u8 val[MAX_RW_LEN]; + int ret; + struct spi_dev_info *spi_dev; + + if (count <= 0 || count > sizeof(val)) { + SPI_DEV_ERROR("write conut %lu, beyond max val:%lu.\n", count, sizeof(val)); + return -EINVAL; + } + + spi_dev = file->private_data; + if (spi_dev == NULL) { + SPI_DEV_ERROR("get write private_data error.\n"); + return -EINVAL; + } + + mem_clear(val, sizeof(val)); + if (copy_from_user(val, buf, count)) { + SPI_DEV_ERROR("copy_from_user error.\n"); + return -EFAULT; + } + + ret = device_write(spi_dev, (uint32_t)*offset, val, count); + if (ret < 0) { + SPI_DEV_ERROR("spi dev write failed, dev name:%s, offset:0x%llx, len:%lu.\n", + spi_dev->name, *offset, count); + return -EINVAL; + } + + *offset += count; + return count; +} + +static loff_t spi_dev_llseek(struct file *file, loff_t offset, int origin) +{ + loff_t ret = 0; + + switch (origin) { + case SEEK_SET: + if (offset < 0) { + SPI_DEV_ERROR("SEEK_SET, offset:%lld, invalid.\n", offset); + ret = -EINVAL; + break; + } + file->f_pos = offset; + ret = file->f_pos; + break; + case SEEK_CUR: + if (file->f_pos + offset < 0) { + SPI_DEV_ERROR("SEEK_CUR out of range, f_ops:%lld, offset:%lld.\n", + file->f_pos, offset); + } + file->f_pos += offset; + ret = file->f_pos; + break; + default: + SPI_DEV_ERROR("unsupport llseek type:%d.\n", origin); + ret = -EINVAL; + break; + } + return ret; +} + +static const struct file_operations spi_dev_fops = { + .owner = THIS_MODULE, + .llseek = spi_dev_llseek, + .read = spi_dev_read, + .write = spi_dev_write, + .unlocked_ioctl = spi_dev_ioctl, + .open = spi_dev_open, + .release = spi_dev_release, +}; + +static struct spi_dev_info * dev_match(const char *path) +{ + struct spi_dev_info * spi_dev; + char dev_name[MAX_NAME_SIZE]; + int i; + for (i = 0; i < MAX_SPI_DEV_NUM; i++) { + if (spi_dev_arry[ i ] == NULL) { + continue; + } + spi_dev = spi_dev_arry[ i ]; + snprintf(dev_name, MAX_NAME_SIZE,"/dev/%s", spi_dev->name); + if (!strcmp(path, dev_name)) { + SPI_DEV_DEBUG("get dev_name = %s, minor = %d\n", dev_name, i); + return spi_dev; + } + } + + return NULL; +} + +int spi_device_func_read(const char *path, uint32_t offset, uint8_t *buf, size_t count) +{ + struct spi_dev_info *spi_dev = NULL; + int ret; + + if(path == NULL){ + SPI_DEV_ERROR("path NULL"); + return -EINVAL; + } + + if(buf == NULL){ + SPI_DEV_ERROR("buf NULL"); + return -EINVAL; + } + + if (count > MAX_RW_LEN) { + SPI_DEV_ERROR("read conut %lu, beyond max:%d.\n", count, MAX_RW_LEN); + return -EINVAL; + } + + spi_dev = dev_match(path); + if (spi_dev == NULL) { + SPI_DEV_ERROR("spi_dev match failed. dev path = %s", path); + return -EINVAL; + } + + ret = device_read(spi_dev, offset, buf, count); + if (ret < 0) { + SPI_DEV_ERROR("spi dev read failed, dev name:%s, offset:0x%x, len:%lu.\n", + spi_dev->name, offset, count); + return -EINVAL; + } + + return count; +} +EXPORT_SYMBOL(spi_device_func_read); + +int spi_device_func_write(const char *path, uint32_t offset, uint8_t *buf, size_t count) +{ + struct spi_dev_info *spi_dev = NULL; + int ret; + + if(path == NULL){ + SPI_DEV_ERROR("path NULL"); + return -EINVAL; + } + + if(buf == NULL){ + SPI_DEV_ERROR("buf NULL"); + return -EINVAL; + } + + if (count > MAX_RW_LEN) { + SPI_DEV_ERROR("write conut %lu, beyond max:%d.\n", count, MAX_RW_LEN); + return -EINVAL; + } + + spi_dev = dev_match(path); + if (spi_dev == NULL) { + SPI_DEV_ERROR("i2c_dev match failed. dev path = %s", path); + return -EINVAL; + } + + ret = device_write (spi_dev, offset, buf, count); + if (ret < 0) { + SPI_DEV_ERROR("i2c dev write failed, dev name:%s, offset:0x%x, len:%lu.\n", + spi_dev->name, offset, count); + return -EINVAL; + } + + return count; +} +EXPORT_SYMBOL(spi_device_func_write); + +static int spi_dev_probe(struct spi_device *spi) +{ + int ret; + struct spi_dev_info *spi_dev; + struct miscdevice *misc; + spi_dev_device_t *spi_dev_device; + + spi_dev = devm_kzalloc(&spi->dev, sizeof(struct spi_dev_info), GFP_KERNEL); + if (!spi_dev) { + dev_err(&spi->dev, "devm_kzalloc error. \n"); + return -ENOMEM; + } + + spi_set_drvdata(spi, spi_dev); + spi_dev->spi_device = spi; + + if (spi->dev.of_node) { + + ret = 0; + ret += of_property_read_string(spi->dev.of_node, "spi_dev_name", &spi_dev->name); + ret += of_property_read_u32(spi->dev.of_node, "data_bus_width", &spi_dev->data_bus_width); + ret += of_property_read_u32(spi->dev.of_node, "addr_bus_width", &spi_dev->addr_bus_width); + ret += of_property_read_u32(spi->dev.of_node, "per_rd_len", &spi_dev->per_rd_len); + ret += of_property_read_u32(spi->dev.of_node, "per_wr_len", &spi_dev->per_wr_len); + if (ret != 0) { + dev_err(&spi->dev, "dts config error.ret:%d.\n", ret); + return -ENXIO; + } + } else { + if (spi->dev.platform_data == NULL) { + dev_err(&spi->dev, "Failed to get platform data config.\n"); + return -ENXIO; + } + spi_dev_device = spi->dev.platform_data; + spi_dev->name = spi_dev_device->spi_dev_name; + spi_dev->data_bus_width = spi_dev_device->data_bus_width; + spi_dev->addr_bus_width = spi_dev_device->addr_bus_width; + spi_dev->per_rd_len = spi_dev_device->per_rd_len; + spi_dev->per_wr_len = spi_dev_device->per_wr_len; + } + + if ((spi_dev->per_rd_len & (spi_dev->data_bus_width - 1)) + || (spi_dev->per_wr_len & (spi_dev->data_bus_width - 1))) { + dev_err(&spi->dev, "Invalid config per_rd_len [%u] per_wr_len [%u] data bus_width [%u], addr bus width [%u].\n", + spi_dev->per_rd_len, spi_dev->per_wr_len, spi_dev->data_bus_width, spi_dev->addr_bus_width); + return -ENXIO; + } + + misc = &spi_dev->misc; + misc->minor = MISC_DYNAMIC_MINOR; + misc->name = spi_dev->name; + misc->fops = &spi_dev_fops; + misc->mode = 0666; + if (misc_register(misc) != 0) { + dev_err(&spi->dev, "register %s faild.\n", misc->name); + return -ENXIO; + } + + if (misc->minor >= MAX_SPI_DEV_NUM) { + dev_err(&spi->dev, "minor number beyond the limit! is %d.\n", misc->minor); + misc_deregister(misc); + return -ENXIO; + } + spi_dev_arry[misc->minor] = spi_dev; + + dev_info(&spi->dev, "register %u data_bus_width %u addr_bus_witdh device %s with %u per_rd_len %u per_wr_len success.\n", + spi_dev->data_bus_width, spi_dev->addr_bus_width, spi_dev->name, spi_dev->per_rd_len, spi_dev->per_wr_len); + + return 0; +} + +static int spi_dev_remove(struct spi_device *spi) +{ + int i; + + for (i = 0; i < MAX_SPI_DEV_NUM; i++) { + if (spi_dev_arry[i] != NULL) { + misc_deregister(&spi_dev_arry[i]->misc); + spi_dev_arry[i] = NULL; + } + } + return 0; +} + +static const struct of_device_id spi_dev_of_match[] = { + { .compatible = "wb-spi-dev" }, + { }, +}; + +MODULE_DEVICE_TABLE(of, spi_dev_of_match); + +static struct spi_driver spi_dev_driver = { + .driver = { + .name = "wb-spi-dev", + .of_match_table = of_match_ptr(spi_dev_of_match), + }, + .probe = spi_dev_probe, + .remove = spi_dev_remove, +}; + +module_spi_driver(spi_dev_driver); + +MODULE_DESCRIPTION("spi dev driver"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("support"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_spi_dev.h b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_spi_dev.h new file mode 100644 index 000000000000..6afc0145638d --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_spi_dev.h @@ -0,0 +1,16 @@ +#ifndef __WB_SPI_DEV_H__ +#define __WB_SPI_DEV_H__ +#include + +#define mem_clear(data, size) memset((data), 0, (size)) +#define SPI_DEV_NAME_MAX_LEN (64) + +typedef struct spi_dev_device_s { + char spi_dev_name[SPI_DEV_NAME_MAX_LEN]; + uint32_t data_bus_width; + uint32_t addr_bus_width; + uint32_t per_rd_len; + uint32_t per_wr_len; +} spi_dev_device_t; + +#endif diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_spi_gpio.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_spi_gpio.c new file mode 100644 index 000000000000..16408f067be1 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_spi_gpio.c @@ -0,0 +1,477 @@ +/* + * SPI master driver using generic bitbanged GPIO + * + * Copyright (C) 2006,2008 David Brownell + * Copyright (C) 2017 Linus Walleij + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +/* + * This bitbanging SPI master driver should help make systems usable + * when a native hardware SPI engine is not available, perhaps because + * its driver isn't yet working or because the I/O pins it requires + * are used for other purposes. + * + * platform_device->driver_data ... points to spi_gpio + * + * spi->controller_state ... reserved for bitbang framework code + * spi->controller_data ... holds chipselect GPIO + * + * spi->master->dev.driver_data ... points to spi_gpio->bitbang + */ + +struct spi_gpio { + struct spi_bitbang bitbang; + struct spi_gpio_platform_data pdata; + struct platform_device *pdev; + struct gpio_desc *sck; + struct gpio_desc *miso; + struct gpio_desc *mosi; + struct gpio_desc **cs_gpios; + bool has_cs; +}; + +/*----------------------------------------------------------------------*/ + +/* + * Because the overhead of going through four GPIO procedure calls + * per transferred bit can make performance a problem, this code + * is set up so that you can use it in either of two ways: + * + * - The slow generic way: set up platform_data to hold the GPIO + * numbers used for MISO/MOSI/SCK, and issue procedure calls for + * each of them. This driver can handle several such busses. + * + * - The quicker inlined way: only helps with platform GPIO code + * that inlines operations for constant GPIOs. This can give + * you tight (fast!) inner loops, but each such bus needs a + * new driver. You'll define a new C file, with Makefile and + * Kconfig support; the C code can be a total of six lines: + * + * #define DRIVER_NAME "myboard_spi2" + * #define SPI_MISO_GPIO 119 + * #define SPI_MOSI_GPIO 120 + * #define SPI_SCK_GPIO 121 + * #define SPI_N_CHIPSEL 4 + * #include "spi-gpio.c" + */ + +#ifndef DRIVER_NAME +#define DRIVER_NAME "wb_spi_gpio" + +#define GENERIC_BITBANG /* vs tight inlines */ + +#endif + +/*----------------------------------------------------------------------*/ + +static inline struct spi_gpio *__pure +spi_to_spi_gpio(const struct spi_device *spi) +{ + const struct spi_bitbang *bang; + struct spi_gpio *spi_gpio; + + bang = spi_master_get_devdata(spi->master); + spi_gpio = container_of(bang, struct spi_gpio, bitbang); + return spi_gpio; +} + +static inline struct spi_gpio_platform_data *__pure +spi_to_pdata(const struct spi_device *spi) +{ + return &spi_to_spi_gpio(spi)->pdata; +} + +/* These helpers are in turn called by the bitbang inlines */ +static inline void setsck(const struct spi_device *spi, int is_on) +{ + struct spi_gpio *spi_gpio = spi_to_spi_gpio(spi); + + gpiod_set_value_cansleep(spi_gpio->sck, is_on); +} + +static inline void setmosi(const struct spi_device *spi, int is_on) +{ + struct spi_gpio *spi_gpio = spi_to_spi_gpio(spi); + + gpiod_set_value_cansleep(spi_gpio->mosi, is_on); +} + +static inline int getmiso(const struct spi_device *spi) +{ + struct spi_gpio *spi_gpio = spi_to_spi_gpio(spi); + + if (spi->mode & SPI_3WIRE) + return !!gpiod_get_value_cansleep(spi_gpio->mosi); + else + return !!gpiod_get_value_cansleep(spi_gpio->miso); +} + +/* + * NOTE: this clocks "as fast as we can". It "should" be a function of the + * requested device clock. Software overhead means we usually have trouble + * reaching even one Mbit/sec (except when we can inline bitops), so for now + * we'll just assume we never need additional per-bit slowdowns. + */ +#define spidelay(nsecs) do {} while (0) + +#include "spi-bitbang-txrx.h" + +/* + * These functions can leverage inline expansion of GPIO calls to shrink + * costs for a txrx bit, often by factors of around ten (by instruction + * count). That is particularly visible for larger word sizes, but helps + * even with default 8-bit words. + * + * REVISIT overheads calling these functions for each word also have + * significant performance costs. Having txrx_bufs() calls that inline + * the txrx_word() logic would help performance, e.g. on larger blocks + * used with flash storage or MMC/SD. There should also be ways to make + * GCC be less stupid about reloading registers inside the I/O loops, + * even without inlined GPIO calls; __attribute__((hot)) on GCC 4.3? + */ + +static u32 spi_gpio_txrx_word_mode0(struct spi_device *spi, + unsigned nsecs, u32 word, u8 bits, unsigned flags) +{ + return bitbang_txrx_be_cpha0(spi, nsecs, 0, flags, word, bits); +} + +static u32 spi_gpio_txrx_word_mode1(struct spi_device *spi, + unsigned nsecs, u32 word, u8 bits, unsigned flags) +{ + return bitbang_txrx_be_cpha1(spi, nsecs, 0, flags, word, bits); +} + +static u32 spi_gpio_txrx_word_mode2(struct spi_device *spi, + unsigned nsecs, u32 word, u8 bits, unsigned flags) +{ + return bitbang_txrx_be_cpha0(spi, nsecs, 1, flags, word, bits); +} + +static u32 spi_gpio_txrx_word_mode3(struct spi_device *spi, + unsigned nsecs, u32 word, u8 bits, unsigned flags) +{ + return bitbang_txrx_be_cpha1(spi, nsecs, 1, flags, word, bits); +} + +/* + * These functions do not call setmosi or getmiso if respective flag + * (SPI_MASTER_NO_RX or SPI_MASTER_NO_TX) is set, so they are safe to + * call when such pin is not present or defined in the controller. + * A separate set of callbacks is defined to get highest possible + * speed in the generic case (when both MISO and MOSI lines are + * available), as optimiser will remove the checks when argument is + * constant. + */ + +static u32 spi_gpio_spec_txrx_word_mode0(struct spi_device *spi, + unsigned nsecs, u32 word, u8 bits, unsigned flags) +{ + flags = spi->master->flags; + return bitbang_txrx_be_cpha0(spi, nsecs, 0, flags, word, bits); +} + +static u32 spi_gpio_spec_txrx_word_mode1(struct spi_device *spi, + unsigned nsecs, u32 word, u8 bits, unsigned flags) +{ + flags = spi->master->flags; + return bitbang_txrx_be_cpha1(spi, nsecs, 0, flags, word, bits); +} + +static u32 spi_gpio_spec_txrx_word_mode2(struct spi_device *spi, + unsigned nsecs, u32 word, u8 bits, unsigned flags) +{ + flags = spi->master->flags; + return bitbang_txrx_be_cpha0(spi, nsecs, 1, flags, word, bits); +} + +static u32 spi_gpio_spec_txrx_word_mode3(struct spi_device *spi, + unsigned nsecs, u32 word, u8 bits, unsigned flags) +{ + flags = spi->master->flags; + return bitbang_txrx_be_cpha1(spi, nsecs, 1, flags, word, bits); +} + +/*----------------------------------------------------------------------*/ + +static void spi_gpio_chipselect(struct spi_device *spi, int is_active) +{ + struct spi_gpio *spi_gpio = spi_to_spi_gpio(spi); + + /* set initial clock line level */ + if (is_active) + gpiod_set_value_cansleep(spi_gpio->sck, spi->mode & SPI_CPOL); + + /* Drive chip select line, if we have one */ + if (spi_gpio->has_cs) { + struct gpio_desc *cs = spi_gpio->cs_gpios[spi->chip_select]; + + /* SPI chip selects are normally active-low */ + gpiod_set_value_cansleep(cs, (spi->mode & SPI_CS_HIGH) ? is_active : !is_active); + } +} + +static int spi_gpio_setup(struct spi_device *spi) +{ + struct gpio_desc *cs; + int status = 0; + struct spi_gpio *spi_gpio = spi_to_spi_gpio(spi); + + /* + * The CS GPIOs have already been + * initialized from the descriptor lookup. + */ + cs = spi_gpio->cs_gpios[spi->chip_select]; + if (!spi->controller_state && cs) + status = gpiod_direction_output(cs, + !(spi->mode & SPI_CS_HIGH)); + + if (!status) + status = spi_bitbang_setup(spi); + + return status; +} + +static int spi_gpio_set_direction(struct spi_device *spi, bool output) +{ + struct spi_gpio *spi_gpio = spi_to_spi_gpio(spi); + + if (output) + return gpiod_direction_output(spi_gpio->mosi, 1); + else + return gpiod_direction_input(spi_gpio->mosi); +} + +static void spi_gpio_cleanup(struct spi_device *spi) +{ + spi_bitbang_cleanup(spi); +} + +/* + * It can be convenient to use this driver with pins that have alternate + * functions associated with a "native" SPI controller if a driver for that + * controller is not available, or is missing important functionality. + * + * On platforms which can do so, configure MISO with a weak pullup unless + * there's an external pullup on that signal. That saves power by avoiding + * floating signals. (A weak pulldown would save power too, but many + * drivers expect to see all-ones data as the no slave "response".) + */ +static int spi_gpio_request(struct device *dev, + struct spi_gpio *spi_gpio, + unsigned int num_chipselects, + u16 *mflags) +{ + int i; + + spi_gpio->mosi = devm_gpiod_get_optional(dev, "mosi", GPIOD_OUT_LOW); + if (IS_ERR(spi_gpio->mosi)) + return PTR_ERR(spi_gpio->mosi); + if (!spi_gpio->mosi) + /* HW configuration without MOSI pin */ + *mflags |= SPI_MASTER_NO_TX; + + spi_gpio->miso = devm_gpiod_get_optional(dev, "miso", GPIOD_IN); + if (IS_ERR(spi_gpio->miso)) + return PTR_ERR(spi_gpio->miso); + /* + * No setting SPI_MASTER_NO_RX here - if there is only a MOSI + * pin connected the host can still do RX by changing the + * direction of the line. + */ + + spi_gpio->sck = devm_gpiod_get(dev, "sck", GPIOD_OUT_LOW); + if (IS_ERR(spi_gpio->sck)) + return PTR_ERR(spi_gpio->sck); + + for (i = 0; i < num_chipselects; i++) { + spi_gpio->cs_gpios[i] = devm_gpiod_get_index(dev, "cs", + i, GPIOD_OUT_HIGH); + if (IS_ERR(spi_gpio->cs_gpios[i])) + return PTR_ERR(spi_gpio->cs_gpios[i]); + } + + return 0; +} + +#ifdef CONFIG_OF +static const struct of_device_id spi_gpio_dt_ids[] = { + { .compatible = "wb-spi-gpio" }, + {} +}; +MODULE_DEVICE_TABLE(of, spi_gpio_dt_ids); + +static int spi_gpio_probe_dt(struct platform_device *pdev) +{ + int ret; + u32 tmp; + struct spi_gpio_platform_data *pdata; + struct device_node *np = pdev->dev.of_node; + const struct of_device_id *of_id = + of_match_device(spi_gpio_dt_ids, &pdev->dev); + + if (!of_id) + return 0; + + pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); + if (!pdata) + return -ENOMEM; + + ret = of_property_read_u32(np, "num-chipselects", &tmp); + if (ret < 0) { + dev_err(&pdev->dev, "num-chipselects property not found\n"); + goto error_free; + } + + pdata->num_chipselect = tmp; + pdev->dev.platform_data = pdata; + + return 1; + +error_free: + devm_kfree(&pdev->dev, pdata); + return ret; +} +#else +static inline int spi_gpio_probe_dt(struct platform_device *pdev) +{ + return 0; +} +#endif + +static int spi_gpio_probe(struct platform_device *pdev) +{ + int status; + struct spi_master *master; + struct spi_gpio *spi_gpio; + struct spi_gpio_platform_data *pdata; + u16 master_flags = 0; + bool use_of = 0; + + status = spi_gpio_probe_dt(pdev); + if (status < 0) + return status; + if (status > 0) + use_of = 1; + + pdata = dev_get_platdata(&pdev->dev); +#ifdef GENERIC_BITBANG + if (!pdata || (!use_of && !pdata->num_chipselect)) + return -ENODEV; +#endif + + master = spi_alloc_master(&pdev->dev, sizeof(*spi_gpio)); + if (!master) + return -ENOMEM; + + spi_gpio = spi_master_get_devdata(master); + + spi_gpio->cs_gpios = devm_kcalloc(&pdev->dev, + pdata->num_chipselect, + sizeof(*spi_gpio->cs_gpios), + GFP_KERNEL); + if (!spi_gpio->cs_gpios) + return -ENOMEM; + + platform_set_drvdata(pdev, spi_gpio); + + /* Determine if we have chip selects connected */ + spi_gpio->has_cs = !!pdata->num_chipselect; + + spi_gpio->pdev = pdev; + if (pdata) + spi_gpio->pdata = *pdata; + + status = spi_gpio_request(&pdev->dev, spi_gpio, + pdata->num_chipselect, &master_flags); + if (status) + return status; + + master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); + master->mode_bits = SPI_3WIRE | SPI_CPHA | SPI_CPOL | SPI_CS_HIGH; + master->flags = master_flags; + master->bus_num = pdev->id; + /* The master needs to think there is a chipselect even if not connected */ + master->num_chipselect = spi_gpio->has_cs ? pdata->num_chipselect : 1; + master->setup = spi_gpio_setup; + master->cleanup = spi_gpio_cleanup; + + if (pdev->dev.of_node) { + master->dev.of_node = pdev->dev.of_node; + } + + spi_gpio->bitbang.master = master; + spi_gpio->bitbang.chipselect = spi_gpio_chipselect; + spi_gpio->bitbang.set_line_direction = spi_gpio_set_direction; + + if ((master_flags & SPI_MASTER_NO_TX) == 0) { + spi_gpio->bitbang.txrx_word[SPI_MODE_0] = spi_gpio_txrx_word_mode0; + spi_gpio->bitbang.txrx_word[SPI_MODE_1] = spi_gpio_txrx_word_mode1; + spi_gpio->bitbang.txrx_word[SPI_MODE_2] = spi_gpio_txrx_word_mode2; + spi_gpio->bitbang.txrx_word[SPI_MODE_3] = spi_gpio_txrx_word_mode3; + } else { + spi_gpio->bitbang.txrx_word[SPI_MODE_0] = spi_gpio_spec_txrx_word_mode0; + spi_gpio->bitbang.txrx_word[SPI_MODE_1] = spi_gpio_spec_txrx_word_mode1; + spi_gpio->bitbang.txrx_word[SPI_MODE_2] = spi_gpio_spec_txrx_word_mode2; + spi_gpio->bitbang.txrx_word[SPI_MODE_3] = spi_gpio_spec_txrx_word_mode3; + } + spi_gpio->bitbang.setup_transfer = spi_bitbang_setup_transfer; + + status = spi_bitbang_start(&spi_gpio->bitbang); + if (status) + spi_master_put(master); + + return status; +} + +static int spi_gpio_remove(struct platform_device *pdev) +{ + struct spi_gpio *spi_gpio; + struct spi_gpio_platform_data *pdata; + + spi_gpio = platform_get_drvdata(pdev); + pdata = dev_get_platdata(&pdev->dev); + + /* stop() unregisters child devices too */ + spi_bitbang_stop(&spi_gpio->bitbang); + + spi_master_put(spi_gpio->bitbang.master); + + return 0; +} + +MODULE_ALIAS("platform:" DRIVER_NAME); + +static struct platform_driver spi_gpio_driver = { + .driver = { + .name = DRIVER_NAME, + .of_match_table = of_match_ptr(spi_gpio_dt_ids), + }, + .probe = spi_gpio_probe, + .remove = spi_gpio_remove, +}; +module_platform_driver(spi_gpio_driver); + +MODULE_DESCRIPTION("SPI master driver using generic bitbanged GPIO "); +MODULE_AUTHOR("support"); +MODULE_LICENSE("GPL"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_spi_gpio_device.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_spi_gpio_device.c new file mode 100644 index 000000000000..e70c97b1af9d --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_spi_gpio_device.c @@ -0,0 +1,153 @@ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#define mem_clear(data, size) memset((data), 0, (size)) + +#define DEFAULT_GPIO_SCK (67) +#define DEFAULT_GPIO_MISO (32) +#define DEFAULT_GPIO_MOSI (65) +#define DEFAULT_GPIO_CS (6) +#define DEFAULT_SPI_BUS (0) + +static int sck = DEFAULT_GPIO_SCK; +module_param(sck, int, S_IRUGO | S_IWUSR); + +static int miso = DEFAULT_GPIO_MISO; +module_param(miso, int, S_IRUGO | S_IWUSR); + +static int mosi = DEFAULT_GPIO_MOSI; +module_param(mosi, int, S_IRUGO | S_IWUSR); + +static int cs = DEFAULT_GPIO_CS; +module_param(cs, int, S_IRUGO | S_IWUSR); + +static int bus = DEFAULT_SPI_BUS; +module_param(bus, int, S_IRUGO | S_IWUSR); + +static int g_wb_spi_gpio_device_debug = 0; +static int g_wb_spi_gpio_device_error = 0; + +module_param(g_wb_spi_gpio_device_debug, int, S_IRUGO | S_IWUSR); +module_param(g_wb_spi_gpio_device_error, int, S_IRUGO | S_IWUSR); + +static char gpiod_lookup_table_devid[64]; + +#define WB_SPI_GPIO_DEVICE_VERBOSE(fmt, args...) do { \ + if (g_wb_spi_gpio_device_debug) { \ + printk(KERN_INFO "[WB_SPI_GPIO_DEVICE][VER][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +#define WB_SPI_GPIO_DEVICE_ERROR(fmt, args...) do { \ + if (g_wb_spi_gpio_device_error) { \ + printk(KERN_ERR "[WB_SPI_GPIO_DEVICE][ERR][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +static struct gpiod_lookup_table wb_spi_gpio_table = { + .table = { + GPIO_LOOKUP("wb_gpio_d1500", DEFAULT_GPIO_SCK, + "sck", GPIO_ACTIVE_HIGH), + GPIO_LOOKUP("wb_gpio_d1500", DEFAULT_GPIO_MOSI, + "mosi", GPIO_ACTIVE_HIGH), + GPIO_LOOKUP("wb_gpio_d1500", DEFAULT_GPIO_MISO, + "miso", GPIO_ACTIVE_HIGH), + GPIO_LOOKUP("wb_gpio_d1500", DEFAULT_GPIO_CS, + "cs", GPIO_ACTIVE_HIGH), + { }, + }, +}; + +static struct spi_gpio_platform_data spi_pdata = { + .num_chipselect = 1, +}; + +static void spi_gpio_release(struct device *dev) +{ + return; +} + +static struct platform_device wb_spi_gpio_device = { + .name = "wb_spi_gpio", + .num_resources = 0, + .id = -1, + + .dev = { + .platform_data = &spi_pdata, + .release = spi_gpio_release, + } +}; + +static void wb_spi_gpio_table_devid_name_set(void) { + int size; + + size = sizeof(gpiod_lookup_table_devid); + wb_spi_gpio_device.id = bus; + + mem_clear(gpiod_lookup_table_devid, size); + switch (bus) { + case PLATFORM_DEVID_NONE: + snprintf(gpiod_lookup_table_devid, size, "%s", wb_spi_gpio_device.name); + break; + case PLATFORM_DEVID_AUTO: + snprintf(gpiod_lookup_table_devid, size, "%s.%d.auto", wb_spi_gpio_device.name, bus); + break; + default: + snprintf(gpiod_lookup_table_devid, size, "%s.%d", wb_spi_gpio_device.name, bus); + break; + } + + wb_spi_gpio_table.dev_id = gpiod_lookup_table_devid; + return ; +} +static int __init wb_spi_gpio_device_init(void) +{ + int err; + struct gpiod_lookup *p; + + WB_SPI_GPIO_DEVICE_VERBOSE("enter!\n"); + wb_spi_gpio_table.table[0].chip_hwnum = sck; + wb_spi_gpio_table.table[1].chip_hwnum = mosi; + wb_spi_gpio_table.table[2].chip_hwnum = miso; + wb_spi_gpio_table.table[3].chip_hwnum = cs; + wb_spi_gpio_table_devid_name_set(); + WB_SPI_GPIO_DEVICE_VERBOSE("spi gpi device table bus[%d] dev id[%s]\n", bus, wb_spi_gpio_table.dev_id); + for (p = &wb_spi_gpio_table.table[0]; p->key; p++) { + WB_SPI_GPIO_DEVICE_VERBOSE("con_id:%s gpio:%d\n", p->con_id, p->chip_hwnum); + } + + gpiod_add_lookup_table(&wb_spi_gpio_table); + err = platform_device_register(&wb_spi_gpio_device); + if (err < 0) { + printk(KERN_ERR "register spi gpio device fail(%d). \n", err); + gpiod_remove_lookup_table(&wb_spi_gpio_table); + return -1; + } + + return 0; +} + +static void __exit wb_spi_gpio_device_exit(void) +{ + WB_SPI_GPIO_DEVICE_VERBOSE("enter!\n"); + platform_device_unregister(&wb_spi_gpio_device); + gpiod_remove_lookup_table(&wb_spi_gpio_table); +} + +module_init(wb_spi_gpio_device_init); +module_exit(wb_spi_gpio_device_exit); +MODULE_DESCRIPTION("SPI GPIO Devices"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("support"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_spi_nor_device.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_spi_nor_device.c new file mode 100644 index 000000000000..4196601f717b --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_spi_nor_device.c @@ -0,0 +1,87 @@ +#include +#include +#include +#include +#include +#include + +/* The SPI Bus number that the device is mounted on can be specified manually when this module is loaded */ +#define DEFAULT_SPI_BUS_NUM (0) +#define DEFAULT_SPI_CS_NUM (0) +#define DEFAULT_SPI_HZ (100000) + +int g_wb_spi_nor_dev_debug = 0; +int g_wb_spi_nor_dev_error = 0; +int spi_bus_num = DEFAULT_SPI_BUS_NUM; + +module_param(g_wb_spi_nor_dev_debug, int, S_IRUGO | S_IWUSR); +module_param(g_wb_spi_nor_dev_error, int, S_IRUGO | S_IWUSR); +module_param(spi_bus_num, int, S_IRUGO | S_IWUSR); + +#define SPI_NOR_DEV_DEBUG_VERBOSE(fmt, args...) do { \ + if (g_wb_spi_nor_dev_debug) { \ + printk(KERN_INFO "[SPI_NOR_DEV][VER][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +#define SPI_NOR_DEV_DEBUG_ERROR(fmt, args...) do { \ + if (g_wb_spi_nor_dev_error) { \ + printk(KERN_ERR "[SPI_NOR_DEV][ERR][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +struct spi_board_info spi_nor_device_info __initdata= { + .modalias = "mx25l6405d", + .bus_num = DEFAULT_SPI_BUS_NUM, + .chip_select = DEFAULT_SPI_CS_NUM, + .max_speed_hz = 10 * 1000 * 1000, +}; + +static struct spi_device *g_spi_device; + +static int __init wb_spi_nor_dev_init(void) +{ + struct spi_master *master; + + SPI_NOR_DEV_DEBUG_VERBOSE("Enter.\n"); + + spi_nor_device_info.bus_num = spi_bus_num; + master = spi_busnum_to_master(spi_nor_device_info.bus_num); /* Get the controller according to the SPI Bus number */ + if (!master) { + SPI_NOR_DEV_DEBUG_ERROR("get bus_num %u spi master failed.\n", + spi_nor_device_info.bus_num); + return -EINVAL; + } + + g_spi_device = spi_new_device(master, &spi_nor_device_info); + put_device(&master->dev); + if (!g_spi_device) { + SPI_NOR_DEV_DEBUG_ERROR("register spi new device failed.\n"); + return -EPERM; + } + + if (g_wb_spi_nor_dev_debug) { + dev_info(&g_spi_device->dev, "register %u bus_num spi nor device success\n", + spi_nor_device_info.bus_num); + } + + return 0; +} + +static void __exit wb_spi_nor_dev_exit(void) +{ + spi_unregister_device(g_spi_device); + + if (g_wb_spi_nor_dev_debug) { + dev_info(&g_spi_device->dev, "unregister spi nor device success\n"); + } + + return; +} + +module_init(wb_spi_nor_dev_init); +module_exit(wb_spi_nor_dev_exit); + +MODULE_AUTHOR("support"); +MODULE_DESCRIPTION("create spi nor device"); +MODULE_LICENSE("GPL"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_spi_ocores.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_spi_ocores.c new file mode 100644 index 000000000000..a709427c5b73 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_spi_ocores.c @@ -0,0 +1,1025 @@ +/* + * wb_spi_ocores.c + * ko to create ocores spi adapter + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "wb_spi_ocores.h" + +#define SPIOC_WAIT_SCH (5) +#define SPIOC_CONF (0x00) +#define SPIOC_LSBF BIT(0) /* 0:MSB 1:LSB */ +#define SPIOC_IDLE_LOW BIT(1) +#define SPIOC_INTREN BIT(2) /* 0:enable 1:disabel */ +#define SPIOC_DIV_MASK (0xf0) +#define SPIOC_MAX_DIV (0x0E) +#define SPIOC_DIV(div) (((div) & 0x0f) << 4) + +#define SPIOC_STS (0x01) +#define SPIOC_INTR_STS BIT(0) +#define SPIOC_BUSY_STS BIT(1) +#define SPIOC_RXNUM_SHIFT (4) +#define SPIOC_RXNUM_MASK (0xf << SPIOC_RXNUM_SHIFT) +/* Just for read */ +#define SPIOC_RXNUM(reg) (((reg) & SPIOC_RXNUM_MASK) >> SPIOC_RXNUM_SHIFT ) + +#define SPIOC_TXTOT_NUM (0x02) +#define SPIOC_TXNUM(reg) ((reg) & 0x0f) +#define SPIOC_TOTNUM(reg) (((reg) & 0x0f) << 4) + +#define SPIOC_TXCTL (0x03) +#define SPIOC_CSLV BIT(0) /* 0:Deassert SPICS 1:Laeve SPICS */ +#define SPIOC_TRSTART BIT(1) +#define SPIOC_CSID_SHIFT (5) +#define SPIOC_CSID_MASK (0x7 << SPIOC_CSID_SHIFT) +/* Just for write */ +#define SPIOC_CSID(id) (((id) << SPIOC_CSID_SHIFT) & SPIOC_CSID_MASK) + +/* Just single byte */ +#define SPIOC_RX(i) ((0x4) + i) +#define SPIOC_TX(i) ((0x4) + i) + +#define SPIOC_MAX_LEN ((unsigned int)8) +#define SPIOC_TXRX_MAX_LEN ((unsigned int)7) + +#define MODEBITS (SPI_CPHA |SPI_CPOL | SPI_LSB_FIRST |SPI_CS_HIGH) + +#define REG_IO_WIDTH_1 (1) +#define REG_IO_WIDTH_2 (2) +#define REG_IO_WIDTH_4 (4) + +#define SYMBOL_I2C_DEV_MODE (1) +#define FILE_MODE (2) +#define SYMBOL_PCIE_DEV_MODE (3) +#define SYMBOL_IO_DEV_MODE (4) + +int g_spi_oc_debug = 0; +int g_spi_oc_error = 0; + +module_param(g_spi_oc_debug, int, S_IRUGO | S_IWUSR); +module_param(g_spi_oc_error, int, S_IRUGO | S_IWUSR); + +#define SPI_OC_VERBOSE(fmt, args...) do { \ + if (g_spi_oc_debug) { \ + printk(KERN_INFO "[OC_SPI_BUS][VER][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +#define SPI_OC_ERROR(fmt, args...) do { \ + if (g_spi_oc_error) { \ + printk(KERN_ERR "[OC_SPI_BUS][ERR][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +struct spioc { + /* bitbang has to be first */ + struct spi_bitbang bitbang; + int irq; + struct completion done; + unsigned int reamin_len; + unsigned int cur_pos; + unsigned int cur_len; + const u8 *txp; + u8 *rxp; + u8 chip_select; + void (*setreg)(struct spioc *spioc, int reg, u32 value); + u32 (*getreg)(struct spioc *spioc, int reg); + uint32_t bus_num; + const char *dev_name; + uint32_t reg_access_mode; + uint32_t base_addr; + uint32_t reg_shift; + uint32_t reg_io_width; + uint32_t num_chipselect; + uint32_t freq; + uint32_t big_endian; + struct device *dev; + int transfer_busy_flag; +}; + +extern int i2c_device_func_write(const char *path, uint32_t offset, uint8_t *buf, size_t count); +extern int i2c_device_func_read(const char *path, uint32_t offset, uint8_t *buf, size_t count); +extern int pcie_device_func_read(const char *path, uint32_t offset, uint8_t *buf, size_t count); +extern int pcie_device_func_write(const char *path, uint32_t offset, uint8_t *buf, size_t count); +extern int io_device_func_read(const char *path, uint32_t offset, uint8_t *buf, size_t count); +extern int io_device_func_write(const char *path, uint32_t offset, uint8_t *buf, size_t count); + +static int oc_spi_file_read(const char *path, uint32_t pos, uint8_t *val, size_t size) +{ + int ret; + struct file *filp; + loff_t tmp_pos; + + filp = filp_open(path, O_RDONLY, 0); + if (IS_ERR(filp)) { + SPI_OC_ERROR("read open failed errno = %ld\r\n", -PTR_ERR(filp)); + filp = NULL; + goto exit; + } + + tmp_pos = (loff_t)pos; + ret = kernel_read(filp, val, size, &tmp_pos); + if (ret < 0) { + SPI_OC_ERROR("kernel_read failed, path=%s, addr=%d, size=%ld, ret=%d\r\n", path, pos, size, ret); + goto exit; + } + + filp_close(filp, NULL); + + return ret; + +exit: + if (filp != NULL) { + filp_close(filp, NULL); + } + + return -1; +} + +static int oc_spi_file_write(const char *path, uint32_t pos, uint8_t *val, size_t size) +{ + + int ret; + struct file *filp; + loff_t tmp_pos; + + filp = filp_open(path, O_RDWR, 777); + if (IS_ERR(filp)) { + SPI_OC_ERROR("write open failed errno = %ld\r\n", -PTR_ERR(filp)); + filp = NULL; + goto exit; + } + + tmp_pos = (loff_t)pos; + ret = kernel_write(filp, val, size, &tmp_pos); + if (ret < 0) { + SPI_OC_ERROR("kernel_write failed, path=%s, addr=%d, size=%ld, ret=%d\r\n", path, pos, size, ret); + goto exit; + } + + vfs_fsync(filp, 1); + filp_close(filp, NULL); + + return ret; + +exit: + if (filp != NULL) { + filp_close(filp, NULL); + } + + return -1; +} + +static int oc_spi_reg_write(struct spioc *spioc, uint32_t pos, uint8_t *val, size_t size) +{ + int ret; + + switch (spioc->reg_access_mode) { + case SYMBOL_I2C_DEV_MODE: + ret = i2c_device_func_write(spioc->dev_name, pos, val, size); + break; + case FILE_MODE: + ret = oc_spi_file_write(spioc->dev_name, pos, val, size); + break; + case SYMBOL_PCIE_DEV_MODE: + ret = pcie_device_func_write(spioc->dev_name, pos, val, size); + break; + case SYMBOL_IO_DEV_MODE: + ret = io_device_func_write(spioc->dev_name, pos, val, size); + break; + default: + SPI_OC_ERROR("err func_mode, write failed.\n"); + return -EINVAL; + } + + return ret; +} + +static int oc_spi_reg_read(struct spioc *spioc, uint32_t pos, uint8_t *val, size_t size) +{ + int ret; + + switch (spioc->reg_access_mode) { + case SYMBOL_I2C_DEV_MODE: + ret = i2c_device_func_read(spioc->dev_name, pos, val, size); + break; + case FILE_MODE: + ret = oc_spi_file_read(spioc->dev_name, pos, val, size); + break; + case SYMBOL_PCIE_DEV_MODE: + ret = pcie_device_func_read(spioc->dev_name, pos, val, size); + break; + case SYMBOL_IO_DEV_MODE: + ret = io_device_func_read(spioc->dev_name, pos, val, size); + break; + default: + SPI_OC_ERROR("err func_mode, read failed.\n"); + return -EINVAL; + } + + return ret; +} + +static void oc_spi_setreg_8(struct spioc *spioc, int reg, u32 value) +{ + u8 buf_tmp[REG_IO_WIDTH_1]; + u32 pos; + + pos = spioc->base_addr + (reg << spioc->reg_shift); + SPI_OC_VERBOSE("path:%s, access mode:%d, pos:0x%x, value0x%x.\n", + spioc->dev_name, spioc->reg_access_mode, pos, value); + + buf_tmp[0] = (value & 0Xff); + oc_spi_reg_write(spioc, pos, buf_tmp, REG_IO_WIDTH_1); + return; +} + +static void oc_spi_setreg_16(struct spioc *spioc, int reg, u32 value) +{ + u8 buf_tmp[REG_IO_WIDTH_2]; + u32 pos; + + pos = spioc->base_addr + (reg << spioc->reg_shift); + SPI_OC_VERBOSE("path:%s, access mode:%d, pos:0x%x, value0x%x.\n", + spioc->dev_name, spioc->reg_access_mode, pos, value); + + buf_tmp[0] = (value & 0Xff); + buf_tmp[1] = (value >> 8) & 0xff; + oc_spi_reg_write(spioc, pos, buf_tmp, REG_IO_WIDTH_2); + return; +} + +static void oc_spi_setreg_32(struct spioc *spioc, int reg, u32 value) +{ + u8 buf_tmp[REG_IO_WIDTH_4]; + u32 pos; + + pos = spioc->base_addr + (reg << spioc->reg_shift); + SPI_OC_VERBOSE("path:%s, access mode:%d, pos:0x%x, value0x%x.\n", + spioc->dev_name, spioc->reg_access_mode, pos, value); + + buf_tmp[0] = (value & 0xff); + buf_tmp[1] = (value >> 8) & 0xff; + buf_tmp[2] = (value >> 16) & 0xff; + buf_tmp[3] = (value >> 24) & 0xff; + + oc_spi_reg_write(spioc, pos, buf_tmp, REG_IO_WIDTH_4); + return; +} + +static void oc_spi_setreg_16be(struct spioc *spioc, int reg, u32 value) +{ + u8 buf_tmp[REG_IO_WIDTH_2]; + u32 pos; + + pos = spioc->base_addr + (reg << spioc->reg_shift); + SPI_OC_VERBOSE("path:%s, access mode:%d, pos:0x%x, value0x%x.\n", + spioc->dev_name, spioc->reg_access_mode, pos, value); + + buf_tmp[0] = (value >> 8) & 0xff; + buf_tmp[1] = (value & 0Xff); + oc_spi_reg_write(spioc, pos, buf_tmp, REG_IO_WIDTH_2); + return; +} + +static void oc_spi_setreg_32be(struct spioc *spioc, int reg, u32 value) +{ + u8 buf_tmp[REG_IO_WIDTH_4]; + u32 pos; + + pos = spioc->base_addr + (reg << spioc->reg_shift); + SPI_OC_VERBOSE("path:%s, access mode:%d, pos:0x%x, value0x%x.\n", + spioc->dev_name, spioc->reg_access_mode, pos, value); + + buf_tmp[0] = (value >> 24) & 0xff; + buf_tmp[1] = (value >> 16) & 0xff; + buf_tmp[2] = (value >> 8) & 0xff; + buf_tmp[3] = (value & 0xff); + oc_spi_reg_write(spioc, pos, buf_tmp, REG_IO_WIDTH_4); + return; +} + +static inline u32 oc_spi_getreg_8(struct spioc *spioc, int reg) +{ + u8 buf_tmp[REG_IO_WIDTH_1]; + u32 value, pos; + + pos = spioc->base_addr + (reg << spioc->reg_shift); + oc_spi_reg_read(spioc, pos, buf_tmp, REG_IO_WIDTH_1); + value = buf_tmp[0]; + + SPI_OC_VERBOSE("path:%s, access mode:%d, pos:0x%x, value0x%x.\n", + spioc->dev_name, spioc->reg_access_mode, pos, value); + + return value; +} + +static inline u32 oc_spi_getreg_16(struct spioc *spioc, int reg) +{ + u8 buf_tmp[REG_IO_WIDTH_2]; + u32 value, pos; + int i; + + pos = spioc->base_addr + (reg << spioc->reg_shift); + mem_clear(buf_tmp, sizeof(buf_tmp)); + oc_spi_reg_read(spioc, pos, buf_tmp, REG_IO_WIDTH_2); + + value = 0; + for (i = 0; i < REG_IO_WIDTH_2 ; i++) { + value |= buf_tmp[i] << (8 * i); + } + + SPI_OC_VERBOSE("path:%s, access mode:%d, pos:0x%x, value0x%x.\n", + spioc->dev_name, spioc->reg_access_mode, pos, value); + return value; +} + +static inline u32 oc_spi_getreg_32(struct spioc *spioc, int reg) +{ + u8 buf_tmp[REG_IO_WIDTH_4]; + u32 value, pos; + int i; + + pos = spioc->base_addr + (reg << spioc->reg_shift); + mem_clear(buf_tmp, sizeof(buf_tmp)); + oc_spi_reg_read(spioc, pos, buf_tmp, REG_IO_WIDTH_4); + + value = 0; + for (i = 0; i < REG_IO_WIDTH_4 ; i++) { + value |= buf_tmp[i] << (8 * i); + } + SPI_OC_VERBOSE("path:%s, access mode:%d, pos:0x%x, value0x%x.\n", + spioc->dev_name, spioc->reg_access_mode, pos, value); + return value; +} + +static inline u32 oc_spi_getreg_16be(struct spioc *spioc, int reg) +{ + u8 buf_tmp[REG_IO_WIDTH_2]; + u32 value, pos; + int i; + + pos = spioc->base_addr + (reg << spioc->reg_shift); + + mem_clear(buf_tmp, sizeof(buf_tmp)); + oc_spi_reg_read(spioc, pos, buf_tmp, REG_IO_WIDTH_2); + + value = 0; + for (i = 0; i < REG_IO_WIDTH_2 ; i++) { + value |= buf_tmp[i] << (8 * (REG_IO_WIDTH_2 -i - 1)); + } + + SPI_OC_VERBOSE("path:%s, access mode:%d, pos:0x%x, value0x%x.\n", + spioc->dev_name, spioc->reg_access_mode, pos, value); + return value; +} + +static inline u32 oc_spi_getreg_32be(struct spioc *spioc, int reg) +{ + u8 buf_tmp[REG_IO_WIDTH_4]; + u32 value, pos; + int i; + + pos = spioc->base_addr + (reg << spioc->reg_shift); + + mem_clear(buf_tmp, sizeof(buf_tmp)); + oc_spi_reg_read(spioc, pos, buf_tmp, REG_IO_WIDTH_4); + + value = 0; + for (i = 0; i < REG_IO_WIDTH_4 ; i++) { + value |= buf_tmp[i] << (8 * (REG_IO_WIDTH_4 -i - 1)); + } + + SPI_OC_VERBOSE("path:%s, access mode:%d, pos:0x%x, value0x%x.\n", + spioc->dev_name, spioc->reg_access_mode, pos, value); + return value; + +} + +static inline void oc_spi_setreg(struct spioc *spioc, int reg, u32 value) +{ + spioc->setreg(spioc, reg, value); + return; +} + +static inline u32 oc_spi_getreg(struct spioc *spioc, int reg) +{ + return spioc->getreg(spioc, reg); +} + +static int spioc_get_clkdiv(struct spioc *spioc, u32 speed) +{ + u32 rate, div; + + rate = spioc->freq; + SPI_OC_VERBOSE("clk get rate:%u, speed:%u\n", rate, speed); + /* fs = fw/((DIV+2)*2) */ + + if (speed > (rate / 4)) { + div = 0; + SPI_OC_VERBOSE("spi device speed[%u] more than a quarter of clk rate[%u].\n", + speed, rate); + return div; + } + div = (rate/(2 * speed)) - 2; + if (div > SPIOC_MAX_DIV) { + SPI_OC_ERROR("Unsupport spi device speed, div:%u.\n", div); + return -1; + } + SPI_OC_VERBOSE("DIV is:0x%x\n", div); + return div; +} + +static inline int spioc_wait_trans(struct spioc *spioc, const unsigned long timeout) +{ + unsigned long j; + unsigned int sch_time; + u8 reg; + + j = jiffies + timeout; + sch_time = SPIOC_WAIT_SCH; + while (1) { + reg = oc_spi_getreg(spioc, SPIOC_STS); + if (!(reg & SPIOC_BUSY_STS)) { + SPI_OC_VERBOSE("wait ok!\n"); + break; + } + + if (time_after(jiffies, j)) { + return -ETIMEDOUT; + } + + usleep_range(sch_time, sch_time + 1); + } + + return 0; +} + +static void spioc_chipselect(struct spi_device *spi, int is_active) +{ + struct spioc *spioc; + u8 tx_conf; + int ret; + + spioc = spi_master_get_devdata(spi->master); + spioc->transfer_busy_flag = 0; + ret = spioc_wait_trans(spioc, msecs_to_jiffies(100)); + if (ret < 0) { + SPI_OC_ERROR("spi transfer is busy, ret=%d.\n", ret); + spioc->transfer_busy_flag = 1; + return; + } + spioc->chip_select = spi->chip_select; + SPI_OC_VERBOSE("spioc_chipselect:%u, value:%d.\n", spioc->chip_select, is_active); + tx_conf = 0; + tx_conf |= SPIOC_CSID(spioc->chip_select); + if (is_active) { + tx_conf |= SPIOC_CSLV; + } + + SPI_OC_VERBOSE("tx_config:[0x%x]\n", tx_conf); + oc_spi_setreg(spioc, SPIOC_TXCTL, tx_conf); + return; +} + +static void spioc_copy_tx(struct spioc *spioc) +{ + const u8 *src; + int i; + + if (!spioc->txp) { + SPI_OC_ERROR("spioc->txp is NULL.\n"); + return; + } + + src = (u8 *)spioc->txp + spioc->cur_pos; + SPI_OC_VERBOSE("current tx len:0x%x, tx pos:[0x%x]\n", spioc->cur_len, spioc->cur_pos); + + for (i = 0; i < spioc->cur_len; i++) { + SPI_OC_VERBOSE("write %d, val:[0x%x]\n", i, src[i]); + oc_spi_setreg(spioc, SPIOC_TX(i), src[i]); + } +} + +static void spioc_copy_rx(struct spioc *spioc) +{ + u8 *dest; + int i; + + if (!spioc->rxp) { + SPI_OC_ERROR("spioc->rxp is NULL.\n"); + return; + } + + dest = (u8 *)spioc->rxp + spioc->cur_pos; + SPI_OC_VERBOSE("current rx len:0x%x, rx pos:[0x%x]\n", spioc->cur_len, spioc->cur_pos); + + for (i = 0; i < spioc->cur_len; i++) { + dest[i] = oc_spi_getreg(spioc, SPIOC_RX(i)); + SPI_OC_VERBOSE("read %d, val:[0x%x]\n", i, dest[i]); + } +} + +static int spioc_setup_transfer(struct spi_device *spi, struct spi_transfer *transfer) +{ + struct spioc *spioc; + u8 ctrl; + u32 hz; + int div; + + spioc = spi_master_get_devdata(spi->master); + ctrl = 0; + + if (spi->mode & SPI_LSB_FIRST) { + ctrl |= SPIOC_LSBF; + } + + if (!(spi->mode & SPI_CPOL)) { + ctrl |= SPIOC_IDLE_LOW; + } + + if (spioc->irq < 0) { + + ctrl |= SPIOC_INTREN; + } + + if (transfer != NULL) { + hz = transfer->speed_hz; + + if (hz == 0) { + hz = spi->max_speed_hz; + } + } else { + hz = spi->max_speed_hz; + } + + if (hz == 0) { + SPI_OC_ERROR("Unsupport zero speed.\n"); + return -EINVAL; + } + + div = spioc_get_clkdiv(spioc, hz); + if (div < 0) { + SPI_OC_ERROR("get div error, div:%d.\n", div); + return -EINVAL; + } + ctrl |= SPIOC_DIV(div); + + SPI_OC_VERBOSE("ctrl:[0x%x].\n", ctrl); + + oc_spi_setreg(spioc, SPIOC_CONF, ctrl); + return 0; +} + +static int spioc_spi_setup(struct spi_device *spi) +{ + struct spioc *spioc; + + if (!(spi->mode & SPI_CPHA)) { + SPI_OC_ERROR("Unsupport spi device mde:0x%x, SPI_CPHA must be 1.\n", spi->mode); + return -EINVAL; + } + + spioc = spi_master_get_devdata(spi->master); + if (spi->chip_select >= spioc->num_chipselect) { + SPI_OC_ERROR("Spi device chipselect:%u, more than max chipselect:%u.\n", + spi->chip_select, spioc->num_chipselect); + return -EINVAL; + } + SPI_OC_VERBOSE("Support spi device mode:0x%x, chip_select:%u.\n", + spi->mode, spi->chip_select); + return 0; +} + +static int spioc_transfer_start(struct spioc *spioc) +{ + u8 tx_conf; + int ret; + + tx_conf = oc_spi_getreg(spioc, SPIOC_TXCTL); + tx_conf |= SPIOC_TRSTART; + + SPI_OC_VERBOSE("tx_config:[0x%x]\n", tx_conf); + oc_spi_setreg(spioc, SPIOC_TXCTL, tx_conf); + + ret = spioc_wait_trans(spioc, msecs_to_jiffies(100)); + return ret; +} + +static int spioc_tx_start_one(struct spioc *spioc) +{ + unsigned int txlen; + u8 txreg; + int ret; + + if (!spioc->reamin_len) { + SPI_OC_VERBOSE("spioc txlen:[0x0]\n"); + return 0; + } + + spioc->cur_len = spioc->reamin_len > SPIOC_MAX_LEN ? SPIOC_MAX_LEN : spioc->reamin_len; + + txlen = spioc->cur_len; + spioc->reamin_len -= txlen; + SPI_OC_VERBOSE("txlen:[0x%x], tx len remain:[0x%x]\n", txlen, spioc->reamin_len); + + spioc_copy_tx(spioc); + + /* when we only send, txlen == totlen */ + txreg = SPIOC_TXNUM(txlen) | SPIOC_TOTNUM(txlen); + SPI_OC_VERBOSE("txreg:[0x%x]\n", txreg); + oc_spi_setreg(spioc, SPIOC_TXTOT_NUM, txreg); + + ret = spioc_transfer_start(spioc); + if (ret) { + SPI_OC_ERROR("spioc tx rx poll wait for transfer timeout.\n"); + return ret; + } + + if (spioc->reamin_len) { + spioc->cur_pos += txlen; + SPI_OC_VERBOSE("cur_txpos:[0x%x]\n", spioc->cur_pos); + } + + return 0; +} + +static int spioc_rx_start_one(struct spioc *spioc) +{ + unsigned int rxlen; + u8 txtnum; + int ret; + + if (!spioc->reamin_len) { + SPI_OC_VERBOSE("spioc reamin_len:[0x0]\n"); + return 0; + } + + spioc->cur_len = spioc->reamin_len > SPIOC_MAX_LEN ? SPIOC_MAX_LEN : spioc->reamin_len; + + rxlen = spioc->cur_len; + spioc->reamin_len -= rxlen; + SPI_OC_VERBOSE("rxlen:[0x%x], rx len remain:[0x%x]\n", rxlen, spioc->reamin_len); + + /* when we only receive, rxnum=totnum. txnum=0 */ + txtnum = SPIOC_TOTNUM(rxlen); + SPI_OC_VERBOSE("tx total reg:0x%x\n", txtnum); + oc_spi_setreg(spioc, SPIOC_TXTOT_NUM, txtnum); + + ret = spioc_transfer_start(spioc); + if (ret) { + SPI_OC_ERROR("spioc tx rx poll wait for transfer timeout.\n"); + return ret; + } + + spioc_copy_rx(spioc); + + if (spioc->reamin_len) { + spioc->cur_pos += rxlen; + SPI_OC_VERBOSE("cur_rxpos:[0x%x]\n", spioc->cur_pos); + } + + return 0; +} + +static int spioc_tx_rx_start_one(struct spioc *spioc) +{ + unsigned int txlen, total_len; + u8 txreg; + int ret; + + if (!spioc->reamin_len) { + SPI_OC_VERBOSE("spioc reamin_len:[0x0]\n"); + return 0; + } + + spioc->cur_len = spioc->reamin_len > SPIOC_TXRX_MAX_LEN ? SPIOC_TXRX_MAX_LEN : spioc->reamin_len; + + txlen = spioc->cur_len; + spioc->reamin_len -= txlen; + SPI_OC_VERBOSE("tx len:[0x%x], tx len remain:[0x%x]\n", txlen, spioc->reamin_len); + + spioc_copy_tx(spioc); + + total_len = 2 * txlen; /* total_len=txlen + rxlen; rxlen=txlen */ + txreg = SPIOC_TXNUM(txlen) | SPIOC_TOTNUM(total_len); + SPI_OC_VERBOSE("txreg:[0x%x]\n", txreg); + oc_spi_setreg(spioc, SPIOC_TXTOT_NUM, txreg); + + ret = spioc_transfer_start(spioc); + if (ret) { + SPI_OC_ERROR("spioc tx rx poll wait for transfer timeout.\n"); + return ret; + } + + spioc_copy_rx(spioc); + if (spioc->reamin_len) { + spioc->cur_pos += txlen; + SPI_OC_VERBOSE("cur_txrx pos:[0x%x]\n", spioc->cur_pos); + } + return 0; +} + +static int spioc_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) +{ + struct spioc *spioc; + int ret , len; + + if(!t->len || (!t->tx_buf && !t->rx_buf)) { + SPI_OC_ERROR("params error, tx_buf and rx_buf may both NULL, transfer len:0x%x.\n", + t->len); + return 0; + } + + spioc = spi_master_get_devdata(spi->master); + if (spioc->transfer_busy_flag) { + ret = -EBUSY; + goto err; + } + + spioc->txp = t->tx_buf; + spioc->rxp = t->rx_buf; + spioc->reamin_len = t->len; + spioc->cur_len = 0; + spioc->cur_pos = 0; + len = t->len; + ret = 0; + if (spioc->irq >= 0) { + /* use interrupt driven data transfer */ + if (t->tx_buf && t->rx_buf) { + spioc_tx_rx_start_one(spioc); + wait_for_completion(&spioc->done); + } else if (t->tx_buf) { + spioc_tx_start_one(spioc); + wait_for_completion(&spioc->done); + + } else { + spioc_rx_start_one(spioc); + wait_for_completion(&spioc->done); + } + } else { + if (t->tx_buf && t->rx_buf) { + SPI_OC_VERBOSE("start tx rx, len:0x%x\n", t->len); + while (spioc->reamin_len) { + ret = spioc_tx_rx_start_one(spioc); + if (ret) { + goto err; + } + } + } else if (t->tx_buf) { + SPI_OC_VERBOSE("start tx, txlen:0x%x\n", t->len); + while (spioc->reamin_len) { + ret = spioc_tx_start_one(spioc); + if (ret) { + goto err; + } + } + } else { + SPI_OC_VERBOSE("start rx, rxlen:0x%x\n", t->len); + while (spioc->reamin_len) { + ret = spioc_rx_start_one(spioc); + if (ret) { + goto err; + } + } + } + } + SPI_OC_VERBOSE("return num: 0x%x\n", len); + return len; +err: + return ret; +} + +static irqreturn_t spioc_spi_irq(int irq, void *dev) +{ + struct spioc *spioc; + + spioc = dev; + /* gooooohi, interrupt status bit judgment is not done */ + + if (spioc->txp && spioc->rxp) { + if (!spioc->reamin_len) { + complete(&spioc->done); + } else { + spioc_tx_rx_start_one(spioc); + } + } else if (spioc->txp) { + if (!spioc->reamin_len) { + complete(&spioc->done); + } else { + spioc_tx_start_one(spioc); + } + } else if (spioc->rxp){ + if (!spioc->reamin_len) { + complete(&spioc->done); + } else { + spioc_rx_start_one(spioc); + } + } + + return IRQ_HANDLED; +} + +static int ocores_spi_config_init(struct spioc *spioc) +{ + int ret = 0; + struct device *dev; + spi_ocores_device_t *spi_ocores_device; + + dev = spioc->dev; + if (dev->of_node) { + ret += of_property_read_string(dev->of_node, "dev_name", &spioc->dev_name); + ret += of_property_read_u32(dev->of_node, "dev_base", &spioc->base_addr); + ret += of_property_read_u32(dev->of_node, "reg_shift", &spioc->reg_shift); + ret += of_property_read_u32(dev->of_node, "reg_io_width", &spioc->reg_io_width); + ret += of_property_read_u32(dev->of_node, "clock-frequency", &spioc->freq); + ret += of_property_read_u32(dev->of_node, "reg_access_mode", &spioc->reg_access_mode); + ret += of_property_read_u32(dev->of_node, "num_chipselect", &spioc->num_chipselect); + + if (ret != 0) { + SPI_OC_ERROR("dts config error, ret:%d.\n", ret); + ret = -ENXIO; + return ret; + } + } else { + if (spioc->dev->platform_data == NULL) { + SPI_OC_ERROR("platform data config error.\n"); + ret = -ENXIO; + return ret; + } + spi_ocores_device = spioc->dev->platform_data; + spioc->bus_num = spi_ocores_device->bus_num; + spioc->dev_name = spi_ocores_device->dev_name; + spioc->big_endian = spi_ocores_device->big_endian; + spioc->base_addr = spi_ocores_device->dev_base; + spioc->reg_shift = spi_ocores_device->reg_shift; + spioc->reg_io_width = spi_ocores_device->reg_io_width; + spioc->freq = spi_ocores_device->clock_frequency; + spioc->reg_access_mode = spi_ocores_device->reg_access_mode; + spioc->num_chipselect = spi_ocores_device->num_chipselect; + } + + SPI_OC_VERBOSE("name:%s, base:0x%x, reg_shift:0x%x, io_width:0x%x, clock-frequency:0x%x.\n", + spioc->dev_name, spioc->base_addr, spioc->reg_shift, spioc->reg_io_width, spioc->freq); + SPI_OC_VERBOSE("reg access mode:%u, num_chipselect:%u.\n", + spioc->reg_access_mode, spioc->num_chipselect); + return ret; +} + +static int spioc_probe(struct platform_device *pdev) +{ + struct spi_master *master; + struct spioc *spioc; + int ret; + bool be; + + ret = -1; + master = spi_alloc_master(&pdev->dev, sizeof(struct spioc)); + if (!master) { + dev_err(&pdev->dev, "Failed to alloc spi master.\n"); + goto out; + } + + spioc = spi_master_get_devdata(master); + platform_set_drvdata(pdev, spioc); + + spioc->dev = &pdev->dev; + ret = ocores_spi_config_init(spioc); + if (ret != 0) { + dev_err(spioc->dev, "Failed to get ocores spi dts config.\n"); + goto free; + } + + if (spioc->dev->of_node) { + if (of_property_read_u32(spioc->dev->of_node, "big_endian", &spioc->big_endian)) { + + be = 0; + } else { + be = spioc->big_endian; + } + } else { + be = spioc->big_endian; + } + + if (spioc->reg_io_width == 0) { + spioc->reg_io_width = 1; /* Set to default value */ + } + + if (!spioc->setreg || !spioc->getreg) { + switch (spioc->reg_io_width) { + case REG_IO_WIDTH_1: + spioc->setreg = oc_spi_setreg_8; + spioc->getreg = oc_spi_getreg_8; + break; + + case REG_IO_WIDTH_2: + spioc->setreg = be ? oc_spi_setreg_16be : oc_spi_setreg_16; + spioc->getreg = be ? oc_spi_getreg_16be : oc_spi_getreg_16; + break; + + case REG_IO_WIDTH_4: + spioc->setreg = be ? oc_spi_setreg_32be : oc_spi_setreg_32; + spioc->getreg = be ? oc_spi_getreg_32be : oc_spi_getreg_32; + break; + + default: + dev_err(spioc->dev, "Unsupported I/O width (%d)\n", spioc->reg_io_width); + ret = -EINVAL; + goto free; + } + } + + /* master state */ + master->num_chipselect = spioc->num_chipselect; + master->mode_bits = MODEBITS; + master->setup = spioc_spi_setup; + if (spioc->dev->of_node) { + master->dev.of_node = pdev->dev.of_node; + } else { + master->bus_num = spioc->bus_num; + } + + /* setup the state for the bitbang driver */ + spioc->bitbang.master = master; + spioc->bitbang.setup_transfer = spioc_setup_transfer; + spioc->bitbang.chipselect = spioc_chipselect; + spioc->bitbang.txrx_bufs = spioc_spi_txrx_bufs; + + /* gooooohi need revision */ + spioc->irq = platform_get_irq(pdev, 0); + if (spioc->irq >= 0) { + SPI_OC_VERBOSE("spi oc use irq, irq number:%d.\n", spioc->irq); + init_completion(&spioc->done); + ret = devm_request_irq(&pdev->dev, spioc->irq, spioc_spi_irq, 0, + pdev->name, spioc); + if (ret) { + dev_err(spioc->dev, "Failed to request irq:%d.\n", spioc->irq); + goto free; + } + } + + ret = spi_bitbang_start(&spioc->bitbang); + if (ret) { + dev_err(spioc->dev, "Failed to start spi bitbang, ret:%d.\n", ret); + goto free; + } + dev_info(spioc->dev, "registered spi-%d for %s with base address:0x%x success.\n", + master->bus_num, spioc->dev_name, spioc->base_addr); + + return ret; +free: + spi_master_put(master); +out: + return ret; +} + +static int spioc_remove(struct platform_device *pdev) +{ + struct spioc *spioc; + struct spi_master *master; + + spioc = platform_get_drvdata(pdev); + master = spioc->bitbang.master; + spi_bitbang_stop(&spioc->bitbang); + platform_set_drvdata(pdev, NULL); + spi_master_put(master); + + return 0; +} + +static const struct of_device_id spioc_match[] = { + { .compatible = "wb-spi-oc", }, + {}, +}; +MODULE_DEVICE_TABLE(of, spioc_match); + +static struct platform_driver spioc_driver = { + .probe = spioc_probe, + .remove = spioc_remove, + .driver = { + .name = "wb-spioc", + .owner = THIS_MODULE, + .of_match_table = spioc_match, + }, +}; + +module_platform_driver(spioc_driver); + +MODULE_DESCRIPTION("spi open core adapter driver"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("support"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_spi_ocores.h b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_spi_ocores.h new file mode 100644 index 000000000000..647ff0c5f9cf --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_spi_ocores.h @@ -0,0 +1,21 @@ +#ifndef __WB_SPI_OCORES_H__ +#define __WB_SPI_OCORES_H__ +#include + +#define mem_clear(data, size) memset((data), 0, (size)) +#define SPI_OCORES_DEV_NAME_MAX_LEN (64) + +typedef struct spi_ocores_device_s { + uint32_t bus_num; + uint32_t big_endian; + char dev_name[SPI_OCORES_DEV_NAME_MAX_LEN]; + uint32_t reg_access_mode; + uint32_t dev_base; + uint32_t reg_shift; + uint32_t reg_io_width; + uint32_t clock_frequency; + uint32_t num_chipselect; + int device_flag; +} spi_ocores_device_t; + +#endif diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_uio_irq.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_uio_irq.c new file mode 100644 index 000000000000..da2b582443b8 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_uio_irq.c @@ -0,0 +1,282 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +typedef struct dfd_irq_s { + int gpio; + int irq_type; + struct uio_info dfd_irq_info; + spinlock_t lock; + struct attribute_group attr_group; +} dfd_irq_t; + +#define DRV_NAME "uio-irq" +#define DRV_VERSION "1.0" +#define ENABLE_VAL (1) +#define DISABLE_VAL (0) + +#define DEBUG_ERR_LEVEL (0x1) +#define DEBUG_WARN_LEVEL (0x2) +#define DEBUG_INFO_LEVEL (0x4) +#define DEBUG_VER_LEVEL (0x8) + +static int debug = 0; +module_param(debug, int, S_IRUGO | S_IWUSR); +#define DEBUG_ERROR(fmt, args...) \ + do { \ + if (debug & DEBUG_ERR_LEVEL) { \ + printk(KERN_ERR "[ERR][func:%s line:%d] "fmt, __func__, __LINE__, ## args); \ + } else { \ + pr_debug(fmt, ## args); \ + } \ + } while(0) + +#define DEBUG_WARN(fmt, args...) \ + do { \ + if (debug & DEBUG_WARN_LEVEL) { \ + printk(KERN_WARNING "[WARN][func:%s line:%d] "fmt, __func__, __LINE__, ## args); \ + } else { \ + pr_debug(fmt, ## args); \ + } \ + } while(0) + +#define DEBUG_INFO(fmt, args...) \ + do { \ + if (debug & DEBUG_INFO_LEVEL) { \ + printk(KERN_INFO "[INFO][func:%s line:%d] "fmt, __func__, __LINE__, ## args); \ + } else { \ + pr_debug(fmt, ## args); \ + } \ + } while(0) + +#define DEBUG_VERBOSE(fmt, args...) \ + do { \ + if (debug & DEBUG_VER_LEVEL) { \ + printk(KERN_DEBUG "[VER][func:%s line:%d] "fmt, __func__, __LINE__, ## args); \ + } else { \ + pr_debug(fmt, ## args); \ + } \ + } while(0) + +static irqreturn_t dfd_genirq_handler(int irq, struct uio_info *dev_info) +{ + disable_irq_nosync(irq); + DEBUG_VERBOSE("handler disable irq"); + return IRQ_HANDLED; +} + +static int dfd_genirq_irqcontrol(struct uio_info *dev_info, s32 irq_on) +{ + struct irq_data *irqdata; + + irqdata = irq_get_irq_data(dev_info->irq); + + if (irqd_irq_disabled(irqdata) == !irq_on) { + DEBUG_VERBOSE("irq already disable"); + return 0; + } + if (irq_on) { + DEBUG_VERBOSE("irqcontrol enable irq"); + enable_irq(dev_info->irq); + } else { + DEBUG_VERBOSE("irqcontrol disable irq"); + disable_irq(dev_info->irq); + } + + return 0; +} + +static ssize_t set_irq_enable(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + dfd_irq_t *dfd_irq; + struct uio_info *dev_info; + unsigned long flags; + int ret, val; + + dfd_irq = dev_get_drvdata(dev); + dev_info = &dfd_irq->dfd_irq_info; + + spin_lock_irqsave(&dfd_irq->lock, flags); + + sscanf(buf, "%d", &val); + DEBUG_VERBOSE("set val:%d.\n", val); + + if ((val != ENABLE_VAL) && (val != DISABLE_VAL)) { + DEBUG_ERROR("unsupport val:%d ", val); + ret = -EINVAL; + goto fail; + } + + if (val) { + DEBUG_VERBOSE("sysfs enable irq"); + enable_irq(dev_info->irq); + } else { + DEBUG_VERBOSE("sysfs disable irq"); + disable_irq(dev_info->irq); + } + + spin_unlock_irqrestore(&dfd_irq->lock, flags); + return count; + +fail: + spin_unlock_irqrestore(&dfd_irq->lock, flags); + return ret; +} + +static DEVICE_ATTR(irq_enable, S_IWUSR, NULL, set_irq_enable); + +static struct attribute *irq_attrs[] = { + &dev_attr_irq_enable.attr, + NULL, +}; + +static struct attribute_group irq_attr_group = { + .attrs = irq_attrs, +}; + +static int dfd_irq_probe(struct platform_device *pdev) +{ + u32 gpio, irq_type, pirq_line; + int ret, ret1, ret2; + struct uio_info *dfd_irq_info; + dfd_irq_t *dfd_irq; + + dfd_irq = kzalloc(sizeof(dfd_irq_t), GFP_KERNEL); + if (!dfd_irq) { + dev_err(&pdev->dev, "dfd_irq_t kzalloc failed.\n"); + return -ENOMEM; + } + + dfd_irq_info = &dfd_irq->dfd_irq_info; + dfd_irq_info->version = "1.0"; + dfd_irq_info->name = "uio-irq"; + + /* get pirq line for x86 */ + ret1 = of_property_read_u32(pdev->dev.of_node, "pirq-line", &pirq_line); + if (!ret1) { + DEBUG_VERBOSE("use pirq-line method, pirq-line:%u", pirq_line); + dfd_irq_info->irq = pirq_line; + } + + ret2 = of_property_read_u32(pdev->dev.of_node, "gpio", &gpio); + if (!ret2 && ret1) { + dfd_irq->gpio = gpio; + gpio_request(dfd_irq->gpio, "GPIOA"); + dfd_irq_info->irq = gpio_to_irq(dfd_irq->gpio); + DEBUG_VERBOSE("use gpio:%u, irq num:%ld", gpio, dfd_irq_info->irq); + } else if (ret2 && ret1){ + ret = -ENXIO; + dev_err(&pdev->dev, "no define irq num. ret2:%d, ret1:%d.\n", ret2, ret1); + goto free_mem; + } + + ret = of_property_read_u32(pdev->dev.of_node, "irq_type", &irq_type); + if (!ret && ret1) { + DEBUG_VERBOSE("use irq_type:%u", irq_type); + dfd_irq->irq_type = irq_type; + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39) + irq_set_irq_type(dfd_irq_info->irq, dfd_irq->irq_type); +#else + set_irq_type(dfd_irq_info->irq, dfd_irq->irq_type); +#endif + } else if (ret && ret1){ + ret = -ENXIO; + dev_err(&pdev->dev, "no define irq type. ret:%d, ret1:%d.\n", ret, ret1); + goto free_mem; + } + + dfd_irq_info->irq_flags = IRQF_SHARED; + dfd_irq_info->handler = dfd_genirq_handler; + dfd_irq_info->irqcontrol = dfd_genirq_irqcontrol; + + if(uio_register_device(&pdev->dev, dfd_irq_info)){ + ret = -ENODEV; + dev_err(&pdev->dev, "uio register failed.\n"); + goto free_mem; + } + + spin_lock_init(&dfd_irq->lock); + + dfd_irq->attr_group = irq_attr_group; + ret = sysfs_create_group(&pdev->dev.kobj, &dfd_irq->attr_group); + if (ret != 0) { + dev_err(&pdev->dev, "sysfs_create_group failed. ret:%d.\n", ret); + goto free_mem; + } + DEBUG_VERBOSE("sysfs create group success\n"); + + platform_set_drvdata(pdev, dfd_irq); + + return 0; + +free_mem: + kfree(dfd_irq); + + return ret; +} + +static int dfd_irq_remove(struct platform_device *pdev) +{ + dfd_irq_t *dfd_irq; + struct uio_info *dfd_irq_info; + + dfd_irq = platform_get_drvdata(pdev); + dfd_irq_info = &dfd_irq->dfd_irq_info; + + uio_unregister_device(dfd_irq_info); + kfree(dfd_irq); + + sysfs_remove_group(&pdev->dev.kobj, &dfd_irq->attr_group); + + return 0; +} + +static struct of_device_id dfd_irq_match[] = { + { + .compatible = "uio-irq", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, dfd_irq_match); + +static struct platform_driver dfd_irq_driver = { + .probe = dfd_irq_probe, + .remove = dfd_irq_remove, + .driver = { + .owner = THIS_MODULE, + .name = DRV_NAME, + .of_match_table = dfd_irq_match, + }, +}; + +static int __init dfd_irq_init(void) +{ + int ret; + + ret = platform_driver_register(&dfd_irq_driver); + if (ret != 0 ) { + return ret; + } + + return 0; +} + +static void __exit dfd_irq_exit(void) +{ + platform_driver_unregister(&dfd_irq_driver); +} + +module_init(dfd_irq_init); +module_exit(dfd_irq_exit); +MODULE_LICENSE("GPL"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_wdt.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_wdt.c new file mode 100644 index 000000000000..8c02d981843a --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_wdt.c @@ -0,0 +1,1038 @@ +/* + * wb_wdt.c + * ko for watchdog function + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "wb_wdt.h" + +#define GPIO_FEED_WDT_MODE (1) +#define LOGIC_FEED_WDT_MODE (2) + +#define SYMBOL_I2C_DEV_MODE (1) +#define SYMBOL_PCIE_DEV_MODE (2) +#define SYMBOL_IO_DEV_MODE (3) +#define FILE_MODE (4) + +#define ONE_BYTE (1) + +#define WDT_OFF (0) +#define WDT_ON (1) + +#define MS_TO_S (1000) +#define MS_TO_NS (1000 * 1000) + +#define MAX_REG_VAL (255) + +extern int i2c_device_func_write(const char *path, uint32_t offset, uint8_t *buf, size_t count); +extern int i2c_device_func_read(const char *path, uint32_t offset, uint8_t *buf, size_t count); +extern int pcie_device_func_write(const char *path, uint32_t offset, uint8_t *buf, size_t count); +extern int pcie_device_func_read(const char *path, uint32_t offset, uint8_t *buf, size_t count); +extern int io_device_func_write(const char *path, uint32_t offset, uint8_t *buf, size_t count); +extern int io_device_func_read(const char *path, uint32_t offset, uint8_t *buf, size_t count); + +int g_wb_wdt_debug = 0; +int g_wb_wdt_error = 0; + +module_param(g_wb_wdt_debug, int, S_IRUGO | S_IWUSR); +module_param(g_wb_wdt_error, int, S_IRUGO | S_IWUSR); + +#define WDT_VERBOSE(fmt, args...) do { \ + if (g_wb_wdt_debug) { \ + printk(KERN_INFO "[WDT][VER][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +#define WDT_ERROR(fmt, args...) do { \ + if (g_wb_wdt_error) { \ + printk(KERN_ERR "[WDT][ERR][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +enum { + HW_ALGO_TOGGLE, + HW_ALGO_LEVEL, +}; + +enum { + WATCHDOG_DEVICE_TYPE = 0, + HRTIMER_TYPE, + THREAD_TYPE, +}; + +typedef struct wb_wdt_priv_s { + + struct task_struct *thread; + struct hrtimer hrtimer; + ktime_t m_kt; + const char *config_dev_name; + uint8_t config_mode; + uint8_t hw_algo; + uint8_t enable_val; + uint8_t disable_val; + uint8_t enable_mask; + uint8_t priv_func_mode; + uint8_t feed_wdt_type; + uint32_t enable_reg; + uint32_t timeout_cfg_reg; + uint32_t timeleft_cfg_reg; + uint32_t hw_margin; + uint32_t feed_time; + uint32_t timer_accuracy; + gpio_wdt_info_t gpio_wdt; + logic_wdt_info_t logic_wdt; + struct device *dev; + const struct attribute_group *sysfs_group; + uint8_t sysfs_index; + struct mutex update_lock; + struct watchdog_device wdd; +}wb_wdt_priv_t; + +static int wdt_file_read(const char *path, uint32_t pos, uint8_t *val, size_t size) +{ + int ret; + struct file *filp; + loff_t tmp_pos; + + filp = filp_open(path, O_RDONLY, 0); + if (IS_ERR(filp)) { + WDT_ERROR("read open failed errno = %ld\r\n", -PTR_ERR(filp)); + filp = NULL; + goto exit; + } + + tmp_pos = (loff_t)pos; + ret = kernel_read(filp, val, size, &tmp_pos); + if (ret < 0) { + WDT_ERROR("kernel_read failed, path=%s, addr=0x%x, size=%ld, ret=%d\r\n", path, pos, size, ret); + goto exit; + } + + filp_close(filp, NULL); + + return ret; + +exit: + if (filp != NULL) { + filp_close(filp, NULL); + } + + return -1; +} + +static int wdt_file_write(const char *path, uint32_t pos, uint8_t *val, size_t size) +{ + int ret; + struct file *filp; + loff_t tmp_pos; + + filp = filp_open(path, O_RDWR, 777); + if (IS_ERR(filp)) { + WDT_ERROR("write open failed errno = %ld\r\n", -PTR_ERR(filp)); + filp = NULL; + goto exit; + } + + tmp_pos = (loff_t)pos; + ret = kernel_write(filp, val, size, &tmp_pos); + if (ret < 0) { + WDT_ERROR("kernel_write failed, path=%s, addr=0x%x, size=%ld, ret=%d\r\n", path, pos, size, ret); + goto exit; + } + + vfs_fsync(filp, 1); + filp_close(filp, NULL); + + return ret; + +exit: + if (filp != NULL) { + filp_close(filp, NULL); + } + + return -1; +} + +static int wb_wdt_read(uint8_t mode, const char *path, + uint32_t offset, uint8_t *buf, size_t count) +{ + int ret; + + switch (mode) { + case SYMBOL_I2C_DEV_MODE: + ret = i2c_device_func_read(path, offset, buf, count); + break; + case SYMBOL_PCIE_DEV_MODE: + ret = pcie_device_func_read(path, offset, buf, count); + break; + case SYMBOL_IO_DEV_MODE: + ret = io_device_func_read(path, offset, buf, count); + break; + case FILE_MODE: + ret = wdt_file_read(path, offset, buf, count); + break; + default: + WDT_ERROR("mode %u error, wdt func read failed.\n", mode); + return -EINVAL; + } + + WDT_VERBOSE("wdt func read mode:%u,dev_nam:%s, offset:0x%x, read_val:0x%x, size:%lu.\n", + mode, path, offset, *buf, count); + + return ret; +} + +static int wb_wdt_write(uint8_t mode, const char *path, + uint32_t offset, uint8_t *buf, size_t count) +{ + int ret; + + switch (mode) { + case SYMBOL_I2C_DEV_MODE: + ret = i2c_device_func_write(path, offset, buf, count); + break; + case SYMBOL_PCIE_DEV_MODE: + ret = pcie_device_func_write(path, offset, buf, count); + break; + case SYMBOL_IO_DEV_MODE: + ret = io_device_func_write(path, offset, buf, count); + break; + case FILE_MODE: + ret = wdt_file_write(path, offset, buf, count); + break; + default: + WDT_ERROR("mode %u error, wdt func write failed.\n", mode); + return -EINVAL; + } + + WDT_VERBOSE("wdt func write mode:%u, dev_nam:%s, offset:0x%x, write_val:0x%x, size:%lu.\n", + mode, path, offset, *buf, count); + + return ret; +} + +static int wb_wdt_enable_ctrl(wb_wdt_priv_t *priv, uint8_t flag) +{ + int ret; + uint8_t val; + uint8_t ctrl_val; + + switch (flag) { + case WDT_ON: + ctrl_val = priv->enable_val; + break; + case WDT_OFF: + ctrl_val = priv->disable_val; + break; + default: + WDT_ERROR("unsupport wdt enable ctrl:%u.\n", flag); + return -EINVAL; + } + + ret = wb_wdt_read(priv->priv_func_mode, priv->config_dev_name, + priv->enable_reg, &val, ONE_BYTE); + if (ret < 0) { + dev_err(priv->dev, "read wdt control reg error.\n"); + return ret; + } + + val &= ~priv->enable_mask; + + val |= ctrl_val & priv->enable_mask; + + ret = wb_wdt_write(priv->priv_func_mode, priv->config_dev_name, + priv->enable_reg, &val, ONE_BYTE); + if (ret < 0) { + dev_err(priv->dev, "write wdt control reg error.\n"); + return ret; + } + + return 0; +} + +static void wdt_hwping(wb_wdt_priv_t *priv) +{ + gpio_wdt_info_t *gpio_wdt; + logic_wdt_info_t *logic_wdt; + uint8_t tmp_val; + int ret; + + if (priv->config_mode == GPIO_FEED_WDT_MODE) { + gpio_wdt = &priv->gpio_wdt; + switch (priv->hw_algo) { + case HW_ALGO_TOGGLE: + gpio_wdt = &priv->gpio_wdt; + gpio_wdt->state = !gpio_wdt->state; + gpio_set_value_cansleep(gpio_wdt->gpio, gpio_wdt->state); + WDT_VERBOSE("gpio toggle wdt work. val:%u\n", gpio_wdt->state); + break; + case HW_ALGO_LEVEL: + gpio_wdt = &priv->gpio_wdt; + /* Pulse */ + gpio_set_value_cansleep(gpio_wdt->gpio, !gpio_wdt->active_low); + udelay(1); + gpio_set_value_cansleep(gpio_wdt->gpio, gpio_wdt->active_low); + WDT_VERBOSE("gpio level wdt work.\n"); + break; + } + } else { + logic_wdt = &priv->logic_wdt; + switch (priv->hw_algo) { + case HW_ALGO_TOGGLE: + logic_wdt->active_val = !logic_wdt->active_val; + ret = wb_wdt_write(logic_wdt->logic_func_mode, logic_wdt->feed_dev_name, + logic_wdt->feed_reg, &logic_wdt->active_val, ONE_BYTE); + if (ret < 0) { + WDT_ERROR("logic toggle wdt write failed.ret = %d\n", ret); + } + WDT_VERBOSE("logic toggle wdt work.\n"); + break; + case HW_ALGO_LEVEL: + tmp_val = !logic_wdt->active_val; + ret = wb_wdt_write(logic_wdt->logic_func_mode, logic_wdt->feed_dev_name, + logic_wdt->feed_reg, &tmp_val, ONE_BYTE); + if (ret < 0) { + WDT_ERROR("logic level wdt write first failed.ret = %d\n", ret); + } + udelay(1); + ret = wb_wdt_write(logic_wdt->logic_func_mode, logic_wdt->feed_dev_name, + logic_wdt->feed_reg, &logic_wdt->active_val, ONE_BYTE); + if (ret < 0) { + WDT_ERROR("logic level wdt write second failed.ret = %d\n", ret); + } + WDT_VERBOSE("logic level wdt work.\n"); + break; + } + } + return; +} + +static enum hrtimer_restart hrtimer_hwping(struct hrtimer *timer) +{ + wb_wdt_priv_t *priv = container_of(timer, wb_wdt_priv_t, hrtimer); + + wdt_hwping(priv); + hrtimer_forward(timer, timer->base->get_time(), priv->m_kt); + return HRTIMER_RESTART; +} + +static int thread_timer_cfg(wb_wdt_priv_t *priv, wb_wdt_device_t *wb_wdt_device) +{ + struct device *dev; + uint32_t hw_margin; + uint32_t feed_time; + uint32_t accuracy; + uint8_t set_time_val; + int ret; + + dev = priv->dev; + + ret = 0; + if (dev->of_node) { + ret += of_property_read_u32(dev->of_node, "feed_time", &priv->feed_time); + if (ret != 0) { + dev_err(dev, "thread Failed to priv dts.\n"); + return -ENXIO; + } + } else { + priv->feed_time = wb_wdt_device->feed_time; + } + WDT_VERBOSE("thread priv->feed_time: %u.\n", priv->feed_time); + + hw_margin = priv->hw_margin; + feed_time = priv->feed_time; + accuracy = priv->timer_accuracy; + + if ((feed_time > (hw_margin / 2)) || (feed_time == 0)) { + dev_err(dev, "thread timer feed_time[%d] should be less than half hw_margin or zero.\n", feed_time); + return -EINVAL; + } + + set_time_val = hw_margin / accuracy; + ret = wb_wdt_write(priv->priv_func_mode, priv->config_dev_name, + priv->timeout_cfg_reg, &set_time_val, ONE_BYTE); + if (ret < 0) { + dev_err(dev, "set wdt thread timer reg error.\n"); + return ret; + } + return 0; +} + +static int wdt_thread_timer(void *data) +{ + wb_wdt_priv_t *priv = data; + + while (!kthread_should_stop()) { + schedule_timeout_uninterruptible(msecs_to_jiffies(priv->feed_time)); + wdt_hwping(priv); + } + return 0; +} + +static int thread_timer_create(wb_wdt_priv_t *priv, wb_wdt_device_t *wb_wdt_device) +{ + struct task_struct *p; + int ret; + + ret = thread_timer_cfg(priv, wb_wdt_device); + if (ret < 0) { + dev_err(priv->dev, "set wdt thread timer failed.\n"); + return ret; + } + + p = kthread_create(wdt_thread_timer, (void *)priv, "%s", "wb_wdt"); + if (!IS_ERR(p)) { + WDT_VERBOSE("timer thread create success.\n"); + priv->thread = p; + wake_up_process(p); + } else { + dev_err(priv->dev, "timer thread create failed.\n"); + return -ENXIO; + } + + ret = wb_wdt_enable_ctrl(priv, WDT_ON); + if (ret < 0) { + dev_err(priv->dev, "thread enable wdt failed.\n"); + return -ENXIO; + } + + return 0; +} + +static int hrtimer_cfg(wb_wdt_priv_t *priv, wb_wdt_device_t *wb_wdt_device) +{ + struct device *dev; + struct hrtimer *hrtimer; + uint8_t set_time_val; + uint8_t hrtimer_s; + uint32_t hrtimer_ns; + int ret; + uint32_t hw_margin; + uint32_t feed_time; + uint32_t accuracy; + uint32_t max_timeout; + + dev = priv->dev; + + ret = 0; + if (dev->of_node) { + ret += of_property_read_u32(dev->of_node, "feed_time", &priv->feed_time); + if (ret != 0) { + dev_err(dev, "hrtimer Failed to priv dts.\n"); + return -ENXIO; + } + } else { + priv->feed_time = wb_wdt_device->feed_time; + } + WDT_VERBOSE("hrtimer priv->feed_time: %u.\n", priv->feed_time); + + hrtimer = &priv->hrtimer; + hw_margin = priv->hw_margin; + feed_time = priv->feed_time; + accuracy = priv->timer_accuracy; + max_timeout = accuracy * 255; + + if (hw_margin < accuracy || hw_margin > max_timeout) { + dev_err(dev, "hrtimer_hw_margin should be between %u and %u.\n", + accuracy, max_timeout); + return -EINVAL; + } + if ((feed_time > (hw_margin / 2)) || (feed_time == 0)) { + dev_err(dev, "feed_time[%d] should be less than half hw_margin or zeor.\n", feed_time); + return -EINVAL; + } + + hrtimer_s = feed_time / MS_TO_S; + hrtimer_ns = (feed_time % MS_TO_S) * MS_TO_NS; + set_time_val = hw_margin / accuracy; + + ret = wb_wdt_write(priv->priv_func_mode, priv->config_dev_name, + priv->timeout_cfg_reg, &set_time_val, ONE_BYTE); + if (ret < 0) { + dev_err(dev, "set wdt time reg error.\n"); + return ret; + } + + priv->m_kt = ktime_set(hrtimer_s, hrtimer_ns); + hrtimer_init(hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + hrtimer->function = hrtimer_hwping; + hrtimer_start(hrtimer, priv->m_kt, HRTIMER_MODE_REL); + + ret = wb_wdt_enable_ctrl(priv, WDT_ON); + if (ret < 0) { + dev_err(dev, "hrtimer enable wdt failed.\n"); + return -ENXIO; + } + + return 0; +} + +static int wb_wdt_ping(struct watchdog_device *wdd) +{ + wb_wdt_priv_t *priv = watchdog_get_drvdata(wdd); + + wdt_hwping(priv); + return 0; +} + +static int wb_wdt_start(struct watchdog_device *wdd) +{ + wb_wdt_priv_t *priv = watchdog_get_drvdata(wdd); + int ret; + + ret = wb_wdt_enable_ctrl(priv, WDT_ON); + if (ret < 0) { + WDT_ERROR("start wdt enable failed.\n"); + return -ENXIO; + } + set_bit(WDOG_HW_RUNNING, &wdd->status); + return 0; +} + +static int wb_wdt_stop(struct watchdog_device *wdd) +{ + wb_wdt_priv_t *priv = watchdog_get_drvdata(wdd); + int ret; + + ret = wb_wdt_enable_ctrl(priv, WDT_OFF); + if (ret < 0) { + WDT_ERROR("stop wdt enable failed.\n"); + return -ENXIO; + } + clear_bit(WDOG_HW_RUNNING, &wdd->status); + return 0; +} + +static int wb_wdt_set_timeout(struct watchdog_device *wdd, unsigned int t) +{ + wb_wdt_priv_t *priv = watchdog_get_drvdata(wdd); + uint32_t timeout_ms; + uint32_t accuracy; + uint8_t set_time_val; + int ret; + + accuracy = priv->timer_accuracy; + timeout_ms = t * 1000; + if (timeout_ms > accuracy * 255) { + WDT_ERROR("set wdt timeout too larger error.timeout_ms:%u\n", timeout_ms); + return -EINVAL; + } + + set_time_val = timeout_ms / accuracy; + ret = wb_wdt_write(priv->priv_func_mode, priv->config_dev_name, + priv->timeout_cfg_reg, &set_time_val, ONE_BYTE); + if (ret < 0) { + WDT_ERROR("set wdt timeout reg error, set_time_val:%u ret:%d\n", set_time_val, ret); + return ret; + } + wdd->timeout = t; + + return 0; +} + +static unsigned int wb_wdt_get_timeleft(struct watchdog_device *wdd) +{ + wb_wdt_priv_t *priv = watchdog_get_drvdata(wdd); + unsigned int time_left; + uint32_t accuracy; + uint8_t get_time_val; + int ret; + + accuracy = priv->timer_accuracy; + + ret = wb_wdt_read(priv->priv_func_mode, priv->config_dev_name, + priv->timeleft_cfg_reg, &get_time_val, ONE_BYTE); + if (ret < 0) { + WDT_ERROR("get wdt timeout reg error.ret:%d\n", ret); + return ret; + } + time_left = get_time_val * accuracy / MS_TO_S; + + WDT_VERBOSE("get wdt timeleft %d get_time_val %d accuracy=%d\n", + time_left, get_time_val, accuracy); + return time_left; +} + +static const struct watchdog_info wb_wdt_ident = { + .options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT, + .firmware_version = 0, + .identity = "CPLD Watchdog", +}; + +static const struct watchdog_ops wb_wdt_ops = { + .owner = THIS_MODULE, + .start = wb_wdt_start, + .stop = wb_wdt_stop, + .ping = wb_wdt_ping, + .set_timeout = wb_wdt_set_timeout, + .get_timeleft = wb_wdt_get_timeleft, +}; + +static int watchdog_device_cfg(wb_wdt_priv_t *priv) +{ + int ret; + uint8_t set_time_val; + + ret = wb_wdt_enable_ctrl(priv, WDT_OFF); + if (ret < 0) { + dev_err(priv->dev, "probe disable wdt failed.\n"); + return -ENXIO; + } + + set_time_val = priv->hw_margin / priv->timer_accuracy; + ret = wb_wdt_write(priv->priv_func_mode, priv->config_dev_name, + priv->timeout_cfg_reg, &set_time_val, ONE_BYTE); + if (ret < 0) { + dev_err(priv->dev, "set wdt time reg error.\n"); + return ret; + } + + watchdog_set_drvdata(&priv->wdd, priv); + + priv->wdd.info = &wb_wdt_ident; + priv->wdd.ops = &wb_wdt_ops; + priv->wdd.bootstatus = 0; + priv->wdd.timeout = priv->hw_margin / MS_TO_S; + priv->wdd.min_timeout = priv->timer_accuracy / MS_TO_S; + priv->wdd.max_timeout = priv->timer_accuracy * MAX_REG_VAL / MS_TO_S; + priv->wdd.parent = priv->dev; + + watchdog_stop_on_reboot(&priv->wdd); + + ret = devm_watchdog_register_device(priv->dev, &priv->wdd); + if (ret != 0) { + dev_err(priv->dev, "cannot register watchdog device (err=%d)\n", ret); + return -ENXIO; + } + + return 0; +} + +static int logic_wdt_init(wb_wdt_priv_t *priv, wb_wdt_device_t *wb_wdt_device) +{ + struct device *dev; + logic_wdt_info_t *logic_wdt; + int ret; + + dev = priv->dev; + logic_wdt = &priv->logic_wdt; + + ret = 0; + if (dev->of_node) { + ret += of_property_read_string(dev->of_node, "feed_dev_name", &logic_wdt->feed_dev_name); + ret += of_property_read_u32(dev->of_node, "feed_reg", &logic_wdt->feed_reg); + ret += of_property_read_u8(dev->of_node, "active_val", &logic_wdt->active_val); + ret += of_property_read_u8(dev->of_node, "logic_func_mode", &logic_wdt->logic_func_mode); + if (ret != 0) { + dev_err(dev, "Failed to logic_wdt dts.\n"); + return -ENXIO; + } + } else { + logic_wdt->feed_dev_name = wb_wdt_device->wdt_config_mode.logic_wdt.feed_dev_name; + logic_wdt->feed_reg = wb_wdt_device->wdt_config_mode.logic_wdt.feed_reg; + logic_wdt->active_val = wb_wdt_device->wdt_config_mode.logic_wdt.active_val; + logic_wdt->logic_func_mode = wb_wdt_device->wdt_config_mode.logic_wdt.logic_func_mode; + } + + logic_wdt->state_val = logic_wdt->active_val; + + WDT_VERBOSE("feed_dev_name:%s, feed_reg:0x%x, active_val:%u, logic_func_mode:%u\n", + logic_wdt->feed_dev_name, logic_wdt->feed_reg, + logic_wdt->active_val, logic_wdt->logic_func_mode); + + return 0; +} + +static int gpio_wdt_init(wb_wdt_priv_t *priv, wb_wdt_device_t *wb_wdt_device) +{ + struct device *dev; + gpio_wdt_info_t *gpio_wdt; + enum of_gpio_flags flags; + uint32_t f = 0; + int ret; + + dev = priv->dev; + gpio_wdt = &priv->gpio_wdt; + + if (dev->of_node) { + gpio_wdt->gpio = of_get_gpio_flags(dev->of_node, 0, &flags); + } else { + gpio_wdt->gpio = wb_wdt_device->wdt_config_mode.gpio_wdt.gpio; + flags = wb_wdt_device->wdt_config_mode.gpio_wdt.flags; + } + if (!gpio_is_valid(gpio_wdt->gpio)) { + dev_err(dev, "gpio is invalid.\n"); + return gpio_wdt->gpio; + } + + gpio_wdt->active_low = flags & OF_GPIO_ACTIVE_LOW; + + if(priv->hw_algo == HW_ALGO_TOGGLE) { + f = GPIOF_IN; + } else { + f = gpio_wdt->active_low ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW; + } + + ret = devm_gpio_request_one(dev, gpio_wdt->gpio, f, + dev_name(dev)); + if (ret) { + dev_err(dev, "devm_gpio_request_one failed.\n"); + return ret; + } + + gpio_wdt->state = gpio_wdt->active_low; + gpio_direction_output(gpio_wdt->gpio, gpio_wdt->state); + + WDT_VERBOSE("active_low:%d\n", gpio_wdt->active_low); + return 0; +} + +static ssize_t set_wdt_sysfs_value(struct device *dev, struct device_attribute *da, + const char *buf, size_t count) +{ + wb_wdt_priv_t *priv = dev_get_drvdata(dev); + int ret, val; + + val = 0; + sscanf(buf, "%d", &val); + WDT_VERBOSE("set wdt, val:%d.\n", val); + + if (val < 0 || val > 255) { + WDT_ERROR("set wdt val %d failed.\n", val); + return -EINVAL; + } + + mutex_lock(&priv->update_lock); + + ret = wb_wdt_enable_ctrl(priv, val); + if (ret < 0) { + WDT_ERROR("set wdt sysfs value:%u failed.\n", val); + goto fail; + } + + WDT_VERBOSE("set wdt sysfs value:%u successed.\n", val); + mutex_unlock(&priv->update_lock); + return count; + +fail: + mutex_unlock(&priv->update_lock); + return ret; +} + +static ssize_t show_wdt_sysfs_value(struct device *dev, + struct device_attribute *da, char *buf) +{ + wb_wdt_priv_t *priv = dev_get_drvdata(dev); + uint8_t val, status; + int ret; + + mutex_lock(&priv->update_lock); + + ret = wb_wdt_read(priv->priv_func_mode, priv->config_dev_name, + priv->enable_reg, &val, ONE_BYTE); + if (ret < 0) { + dev_err(priv->dev, "read wdt enable reg val error.\n"); + goto fail; + } + + val &= priv->enable_mask; + if (val == priv->enable_val) { + status = WDT_ON; + } else if(val == priv->disable_val) { + status = WDT_OFF; + } else { + WDT_ERROR("enable reg read val not match set val, read val:%u, mask:%u, enable_val:%u, disable_val:%u", + val, priv->enable_mask, priv->enable_val, priv->disable_val); + ret = -EIO; + goto fail; + } + + WDT_VERBOSE("read_val:%u, mask:%u, enable_val:%u, disable_val:%u, status:%u", + val, priv->enable_mask, priv->enable_val, priv->disable_val, status); + + mutex_unlock(&priv->update_lock); + return sprintf(buf, "%u\n", status); + +fail: + mutex_unlock(&priv->update_lock); + return ret; +} + +static SENSOR_DEVICE_ATTR(wdt_status, S_IRUGO | S_IWUSR, show_wdt_sysfs_value, set_wdt_sysfs_value, 0); + +static struct attribute *wdt_sysfs_attrs[] = { + &sensor_dev_attr_wdt_status.dev_attr.attr, + NULL +}; + +static const struct attribute_group wdt_sysfs_group = { + .attrs = wdt_sysfs_attrs, +}; + +struct wdt_attr_match_group { + uint8_t index; + const struct attribute_group *attr_group_ptr; +}; + +static struct wdt_attr_match_group g_wdt_attr_match[] = { + {0, &wdt_sysfs_group}, +}; + +static const struct attribute_group *wdt_get_attr_group(uint32_t index) +{ + int i; + struct wdt_attr_match_group *group; + + for (i = 0; i < ARRAY_SIZE(g_wdt_attr_match); i++) { + group = &g_wdt_attr_match[i]; + if (index == group->index) { + WDT_VERBOSE("get wdt attr, index:%u.\n", index); + return group->attr_group_ptr; + } + } + + return NULL; +} + +static int wb_wdt_probe(struct platform_device *pdev) +{ + wb_wdt_priv_t *priv; + int ret; + const char *algo; + wb_wdt_device_t *wb_wdt_device; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) { + dev_err(&pdev->dev, "devm_kzalloc failed.\n"); + return -ENOMEM; + } + + platform_set_drvdata(pdev, priv); + + if (pdev->dev.of_node) { + ret = 0; + ret += of_property_read_string(pdev->dev.of_node, "config_dev_name", &priv->config_dev_name); + ret += of_property_read_string(pdev->dev.of_node, "hw_algo", &algo); + ret += of_property_read_u8(pdev->dev.of_node, "config_mode", &priv->config_mode); + ret += of_property_read_u8(pdev->dev.of_node, "priv_func_mode", &priv->priv_func_mode); + ret += of_property_read_u8(pdev->dev.of_node, "enable_val", &priv->enable_val); + ret += of_property_read_u8(pdev->dev.of_node, "disable_val", &priv->disable_val); + ret += of_property_read_u8(pdev->dev.of_node, "enable_mask", &priv->enable_mask); + ret += of_property_read_u32(pdev->dev.of_node, "enable_reg", &priv->enable_reg); + ret += of_property_read_u32(pdev->dev.of_node, "timeout_cfg_reg", &priv->timeout_cfg_reg); + ret += of_property_read_u32(pdev->dev.of_node,"hw_margin_ms", &priv->hw_margin); + ret += of_property_read_u8(pdev->dev.of_node,"feed_wdt_type", &priv->feed_wdt_type); + ret += of_property_read_u32(pdev->dev.of_node,"timer_accuracy", &priv->timer_accuracy); + if (ret != 0) { + dev_err(&pdev->dev, "Failed to priv dts.\n"); + return -ENXIO; + } + + priv->sysfs_index = SYSFS_NO_CFG; + of_property_read_u8(pdev->dev.of_node,"sysfs_index", &priv->sysfs_index); + + priv->timeleft_cfg_reg = priv->timeout_cfg_reg; + of_property_read_u32(pdev->dev.of_node,"timeleft_cfg_reg", &priv->timeleft_cfg_reg); + } else { + if (pdev->dev.platform_data == NULL) { + dev_err(&pdev->dev, "Failed to get platform data config.\n"); + return -ENXIO; + } + wb_wdt_device = pdev->dev.platform_data; + priv->config_dev_name = wb_wdt_device->config_dev_name; + algo = wb_wdt_device->hw_algo; + priv->config_mode = wb_wdt_device->config_mode; + priv->priv_func_mode = wb_wdt_device->priv_func_mode; + priv->enable_val = wb_wdt_device->enable_val; + priv->disable_val = wb_wdt_device->disable_val; + priv->enable_mask = wb_wdt_device->enable_mask; + priv->enable_reg = wb_wdt_device->enable_reg; + priv->timeout_cfg_reg = wb_wdt_device->timeout_cfg_reg; + priv->hw_margin = wb_wdt_device->hw_margin; + priv->timer_accuracy = wb_wdt_device->timer_accuracy; + priv->feed_wdt_type = wb_wdt_device->feed_wdt_type; + priv->sysfs_index = wb_wdt_device->sysfs_index; + priv->timeleft_cfg_reg = wb_wdt_device->timeleft_cfg_reg; + } + + if (!strcmp(algo, "toggle")) { + priv->hw_algo = HW_ALGO_TOGGLE; + } else if (!strcmp(algo, "level")) { + priv->hw_algo = HW_ALGO_LEVEL; + } else { + dev_err(&pdev->dev, "hw_algo config error.must be toggle or level.\n"); + return -EINVAL; + } + + WDT_VERBOSE("config_dev_name:%s, config_mode:%u, priv_func_mode:%u, enable_reg:0x%x, timeout_cfg_reg:0x%x\n", + priv->config_dev_name, priv->config_mode, priv->priv_func_mode, priv->enable_reg, priv->timeout_cfg_reg); + WDT_VERBOSE("timeout_cfg_reg:0x%x, enable_val:%u, disable_val:%u, enable_mask:%u, hw_margin:%u, feed_wdt_type:%u\n", + priv->timeleft_cfg_reg, priv->enable_val, priv->disable_val, priv->enable_mask, priv->hw_margin, priv->feed_wdt_type); + + priv->dev = &pdev->dev; + if (priv->config_mode == GPIO_FEED_WDT_MODE) { + ret = gpio_wdt_init(priv, wb_wdt_device); + if (ret < 0) { + dev_err(&pdev->dev, "init gpio mode wdt failed.\n"); + return -ENXIO; + } + } else if (priv->config_mode == LOGIC_FEED_WDT_MODE) { + ret = logic_wdt_init(priv, wb_wdt_device); + if (ret < 0) { + dev_err(&pdev->dev, "init func mode wdt failed.\n"); + return -ENXIO; + } + } else { + dev_err(&pdev->dev, "unsupport %u config_mode, dts configure error.\n", + priv->config_mode); + return -ENXIO; + } + + switch (priv->feed_wdt_type) { + case WATCHDOG_DEVICE_TYPE: + ret = watchdog_device_cfg(priv); + break; + case HRTIMER_TYPE: + ret = hrtimer_cfg(priv, wb_wdt_device); + break; + case THREAD_TYPE: + ret = thread_timer_create(priv, wb_wdt_device); + break; + default: + dev_err(&pdev->dev, "timer type %u unsupport.\n", priv->feed_wdt_type); + return -EINVAL; + } + if (ret < 0) { + dev_err(&pdev->dev, "init timer feed_wdt_type %u failed.\n", priv->feed_wdt_type); + return -ENXIO; + } + + dev_info(&pdev->dev, "register %s mode, config_mode %u, func_mode %u, %u ms overtime wdt success\n", + algo, priv->config_mode, priv->priv_func_mode, priv->hw_margin); + + if (priv->sysfs_index != SYSFS_NO_CFG) { + + priv->sysfs_group = wdt_get_attr_group(priv->sysfs_index); + if (priv->sysfs_group) { + ret = sysfs_create_group(&pdev->dev.kobj, priv->sysfs_group); + if (ret != 0) { + dev_err(&pdev->dev, "sysfs_create_group failed. ret:%d.\n", ret); + return -ENOMEM; + } + dev_info(&pdev->dev, "sysfs create group success\n"); + } else { + dev_err(&pdev->dev, "failed to find %u index wdt, return NULL.\n", priv->sysfs_index); + return -ENOMEM; + } + + mutex_init(&priv->update_lock); + + dev_info(&pdev->dev, "register %u index wdt sysfs success." ,priv->sysfs_index); + } + + return 0; +} + +static void unregister_action(struct platform_device *pdev) +{ + wb_wdt_priv_t *priv = platform_get_drvdata(pdev); + gpio_wdt_info_t *gpio_wdt; + logic_wdt_info_t *logic_wdt; + int ret; + + ret = wb_wdt_enable_ctrl(priv, WDT_OFF); + if (ret < 0) { + dev_err(&pdev->dev, "remove disable wdt failed.\n"); + } + + if (priv->sysfs_index != SYSFS_NO_CFG) { + sysfs_remove_group(&pdev->dev.kobj, priv->sysfs_group); + } + + if (priv->feed_wdt_type == HRTIMER_TYPE) { + hrtimer_cancel(&priv->hrtimer); + } else if (priv->feed_wdt_type == THREAD_TYPE) { + kthread_stop(priv->thread); + priv->thread = NULL; + } else { + WDT_VERBOSE("wdd type, do nothing.\n"); + } + + if (priv->config_mode == GPIO_FEED_WDT_MODE) { + gpio_wdt = &priv->gpio_wdt; + gpio_set_value_cansleep(gpio_wdt->gpio, !gpio_wdt->active_low); + + if (priv->hw_algo == HW_ALGO_TOGGLE) { + gpio_direction_input(gpio_wdt->gpio); + } + } else { + logic_wdt = &priv->logic_wdt; + logic_wdt->state_val = !logic_wdt->state_val; + ret = wb_wdt_write(logic_wdt->logic_func_mode, logic_wdt->feed_dev_name, + logic_wdt->feed_reg, &logic_wdt->state_val, ONE_BYTE); + if (ret < 0) { + dev_err(&pdev->dev, "set wdt control reg error.\n"); + } + } + + return; +} + +static int wb_wdt_remove(struct platform_device *pdev) +{ + WDT_VERBOSE("enter remove wdt.\n"); + unregister_action(pdev); + dev_info(&pdev->dev, "remove wdt finish.\n"); + + return 0; +} + +static void wb_wdt_shutdown(struct platform_device *pdev) +{ + WDT_VERBOSE("enter shutdown wdt.\n"); + unregister_action(pdev); + dev_info(&pdev->dev, "shutdown wdt finish.\n"); + + return; +} + +static const struct of_device_id wb_wdt_dt_ids[] = { + { .compatible = "wb_wdt", }, + { } +}; +MODULE_DEVICE_TABLE(of, wb_wdt_dt_ids); + +static struct platform_driver wb_wdt_driver = { + .driver = { + .name = "wb_wdt", + .of_match_table = wb_wdt_dt_ids, + }, + .probe = wb_wdt_probe, + .remove = wb_wdt_remove, + .shutdown = wb_wdt_shutdown, +}; + +#ifdef CONFIG_GPIO_WATCHDOG_ARCH_INITCALL +static int __init wb_wdt_init(void) +{ + return platform_driver_register(&wb_wdt_driver); +} +arch_initcall(wb_wdt_init); +#else +module_platform_driver(wb_wdt_driver); +#endif + +MODULE_AUTHOR("support"); +MODULE_DESCRIPTION("watchdog driver"); +MODULE_LICENSE("GPL"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_wdt.h b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_wdt.h new file mode 100644 index 000000000000..10c30e13f94c --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_wdt.h @@ -0,0 +1,46 @@ +#ifndef __WB_WDT_H__ +#define __WB_WDT_H__ + +#include + +#define SYSFS_NO_CFG (0xff) + +typedef struct gpio_wdt_info_s { + int gpio; + enum of_gpio_flags flags; + bool active_low; + bool state; +}gpio_wdt_info_t; + +typedef struct logic_wdt_info_s { + const char *feed_dev_name; + uint8_t logic_func_mode; + uint32_t feed_reg; + uint8_t active_val; + uint8_t state_val; +}logic_wdt_info_t; + +typedef struct wb_wdt_device_s { + int device_flag; + const char *config_dev_name; + uint8_t config_mode; + const char *hw_algo; + uint8_t enable_val; + uint8_t disable_val; + uint8_t enable_mask; + uint8_t priv_func_mode; + uint8_t feed_wdt_type; + uint32_t enable_reg; + uint32_t timeout_cfg_reg; + uint32_t timeleft_cfg_reg; + uint32_t hw_margin; + uint32_t feed_time; + uint32_t timer_accuracy; + union { + gpio_wdt_info_t gpio_wdt; + logic_wdt_info_t logic_wdt; + } wdt_config_mode; + uint8_t sysfs_index; +} wb_wdt_device_t; + +#endif diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_xdpe132g5c.c b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_xdpe132g5c.c new file mode 100644 index 000000000000..edc12d34b6e2 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/modules/wb_xdpe132g5c.c @@ -0,0 +1,574 @@ +/* + * xdpe132g5c_i2c_drv.c + * + * This module create sysfs to set AVS and create hwmon to get out power + * through xdpe132g5c I2C address. + * + * History + * [Version] [Date] [Description] + * * v1.0 2021-09-17 Initial version + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define WB_I2C_RETRY_SLEEP_TIME (10000) /* 10ms */ +#define WB_I2C_RETRY_TIME (10) +#define WB_XDPE_I2C_PAGE_ADDR (0xff) +#define WB_XDPE_I2C_VOUT_MODE (0x40) +#define WB_XDPE_I2C_VOUT_COMMAND (0x42) +#define WB_XDPE_I2C_VOUT_PAGE (0x06) +#define WB_XDPE_VOUT_MAX_THRESHOLD ((0xFFFF * 1000L * 1000L) / (256)) +#define WB_XDPE_VOUT_MIN_THRESHOLD (0) + +static int g_wb_xdpe_debug = 0; +static int g_wb_xdpe_error = 0; + +module_param(g_wb_xdpe_debug, int, S_IRUGO | S_IWUSR); +module_param(g_wb_xdpe_error, int, S_IRUGO | S_IWUSR); + +#define WB_XDPE_VERBOSE(fmt, args...) do { \ + if (g_wb_xdpe_debug) { \ + printk(KERN_INFO "[WB_XDPE][VER][func:%s line:%d]\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +#define WB_XDPE_ERROR(fmt, args...) do { \ + if (g_wb_xdpe_error) { \ + printk(KERN_ERR "[WB_XDPE][ERR][func:%s line:%d]\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +struct xdpe_data { + struct i2c_client *client; + struct device *hwmon_dev; + struct mutex update_lock; + long vout_max; + long vout_min; +}; + +typedef struct xdpe_vout_data_s { + u8 vout_mode; + int vout_precision; +} xdpe_vout_data_t; + +static xdpe_vout_data_t g_xdpe_vout_group[] = { + {.vout_mode = 0x18, .vout_precision = 256}, + {.vout_mode = 0x17, .vout_precision = 512}, + {.vout_mode = 0x16, .vout_precision = 1024}, + {.vout_mode = 0x15, .vout_precision = 2048}, + {.vout_mode = 0x14, .vout_precision = 4096}, +}; + +static s32 wb_i2c_smbus_read_byte_data(const struct i2c_client *client, u8 command) +{ + int i; + s32 ret; + + for (i = 0; i < WB_I2C_RETRY_TIME; i++) { + ret = i2c_smbus_read_byte_data(client, command); + if (ret >= 0) { + return ret; + } + usleep_range(WB_I2C_RETRY_SLEEP_TIME, WB_I2C_RETRY_SLEEP_TIME + 1); + } + return ret; +} + +static s32 wb_i2c_smbus_write_byte_data(const struct i2c_client *client, u8 command, u8 value) +{ + int i; + s32 ret; + + for (i = 0; i < WB_I2C_RETRY_TIME; i++) { + ret = i2c_smbus_write_byte_data(client, command, value); + if (ret >= 0) { + return ret; + } + usleep_range(WB_I2C_RETRY_SLEEP_TIME, WB_I2C_RETRY_SLEEP_TIME + 1); + } + return ret; +} + +static s32 wb_i2c_smbus_read_word_data(const struct i2c_client *client, u8 command) +{ + int i; + s32 ret; + + for (i = 0; i < WB_I2C_RETRY_TIME; i++) { + ret = i2c_smbus_read_word_data(client, command); + if (ret >= 0) { + return ret; + } + usleep_range(WB_I2C_RETRY_SLEEP_TIME, WB_I2C_RETRY_SLEEP_TIME + 1); + } + return ret; +} + +static s32 wb_i2c_smbus_write_word_data(const struct i2c_client *client, u8 command, + u16 value) +{ + int i; + s32 ret; + + for (i = 0; i < WB_I2C_RETRY_TIME; i++) { + ret = i2c_smbus_write_word_data(client, command, value); + if (ret >= 0) { + return ret; + } + usleep_range(WB_I2C_RETRY_SLEEP_TIME, WB_I2C_RETRY_SLEEP_TIME + 1); + } + return ret; +} + +static long calc_power_linear11_data(int data) +{ + s16 exponent; + s32 mantissa; + long val; + + exponent = ((s16)data) >> 11; + mantissa = ((s16)((data & 0x7ff) << 5)) >> 5; + val = mantissa; + val = val * 1000L * 1000L; + + if (exponent >= 0) { + val <<= exponent; + } else { + val >>= -exponent; + } + return val; +} + +static int read_xdpe_power_value(const struct i2c_client *client, u8 page, u8 reg, long *value) +{ + int ret, data; + + ret = wb_i2c_smbus_write_byte_data(client, WB_XDPE_I2C_PAGE_ADDR, page); + if (ret < 0) { + WB_XDPE_ERROR("%d-%04x: set xdpe page%u failed, ret: %d\n", client->adapter->nr, + client->addr, page, ret); + return ret; + } + data = wb_i2c_smbus_read_word_data(client, reg); + if (data < 0) { + WB_XDPE_ERROR("%d-%04x: read xdpe page%u reg: 0x%x failed, ret: %d\n", + client->adapter->nr, client->addr, page, reg, data); + return data; + } + *value = calc_power_linear11_data(data); + WB_XDPE_VERBOSE("%d-%04x: page%u reg: 0x%x rd_data: 0x%x, decode linear11 value: %ld\n", + client->adapter->nr, client->addr, page, reg, data, *value); + return 0; +} + +static ssize_t xdpe_power_value_show(struct device *dev, struct device_attribute *da, + char *buf) +{ + int ret, ori_page; + u16 sensor_h, sensor_l; + u8 page, reg; + struct sensor_device_attribute *attr; + struct i2c_client *client; + struct xdpe_data *data; + long value1, value2; + + data = dev_get_drvdata(dev); + client = data->client; + attr = to_sensor_dev_attr(da); + sensor_h = ((attr->index) >> 16) & 0xffff; + sensor_l = (attr->index) & 0xffff; + + mutex_lock(&data->update_lock); + + ori_page = wb_i2c_smbus_read_byte_data(client, WB_XDPE_I2C_PAGE_ADDR); + if (ori_page < 0) { + WB_XDPE_ERROR("%d-%04x: read xdpe origin page failed, ret: %d\n", client->adapter->nr, + client->addr, ori_page); + mutex_unlock(&data->update_lock); + return ori_page; + } + value1 = 0; + value2 = 0; + + if (sensor_h) { + page = (sensor_h >> 8) & 0xff; + reg = sensor_h & 0xff; + ret = read_xdpe_power_value(client, page, reg, &value1); + if (ret < 0) { + WB_XDPE_ERROR("%d-%04x: read xdpe sensor high sensor page%u reg: 0x%x failed, ret: %d\n", + client->adapter->nr, client->addr, page, reg, ret); + goto error; + } + WB_XDPE_VERBOSE("%d-%04x: read xdpe sensor high sensor page%u reg: 0x%x success, value: %ld\n", + client->adapter->nr, client->addr, page, reg, value1); + } + + page = (sensor_l >> 8) & 0xff; + reg = sensor_l & 0xff; + ret = read_xdpe_power_value(client, page, reg, &value2); + if (ret < 0) { + WB_XDPE_ERROR("%d-%04x: read xdpe sensor low sensor page%u reg: 0x%x failed, ret: %d\n", + client->adapter->nr, client->addr, page, reg, ret); + goto error; + } + WB_XDPE_VERBOSE("%d-%04x: read xdpe sensor low sensor page%u reg: 0x%x success, value: %ld\n", + client->adapter->nr, client->addr, page, reg, value2); + + wb_i2c_smbus_write_byte_data(client, WB_XDPE_I2C_PAGE_ADDR, ori_page); + mutex_unlock(&data->update_lock); + return snprintf(buf, PAGE_SIZE, "%ld\n", value1 + value2); +error: + wb_i2c_smbus_write_byte_data(client, WB_XDPE_I2C_PAGE_ADDR, ori_page); + mutex_unlock(&data->update_lock); + return ret; +} + +static int xdpe_get_vout_precision(const struct i2c_client *client, int *vout_precision) +{ + int i, vout_mode, a_size; + + vout_mode = wb_i2c_smbus_read_byte_data(client, WB_XDPE_I2C_VOUT_MODE); + if (vout_mode < 0) { + WB_XDPE_ERROR("%d-%04x: read xdpe vout mode reg: 0x%x failed, ret: %d\n", + client->adapter->nr, client->addr, WB_XDPE_I2C_VOUT_MODE, vout_mode); + return vout_mode; + } + + a_size = ARRAY_SIZE(g_xdpe_vout_group); + for (i = 0; i < a_size; i++) { + if (g_xdpe_vout_group[i].vout_mode == vout_mode) { + *vout_precision = g_xdpe_vout_group[i].vout_precision; + WB_XDPE_VERBOSE("%d-%04x: match, vout mode: 0x%x, precision: %d\n", + client->adapter->nr, client->addr, vout_mode, *vout_precision); + break; + } + } + if (i == a_size) { + WB_XDPE_ERROR("%d-%04x: invalid vout mode: 0x%x\n",client->adapter->nr, client->addr, + vout_mode); + return -EINVAL; + } + return 0; +} + +static ssize_t xdpe_avs_vout_show(struct device *dev, struct device_attribute *da, char *buf) +{ + int ret, ori_page, vout_cmd, vout_precision; + struct i2c_client *client; + struct xdpe_data *data; + long vout; + + client = to_i2c_client(dev); + data = i2c_get_clientdata(client); + + mutex_lock(&data->update_lock); + + ori_page = wb_i2c_smbus_read_byte_data(client, WB_XDPE_I2C_PAGE_ADDR); + if (ori_page < 0) { + WB_XDPE_ERROR("%d-%04x: read xdpe origin page failed, ret: %d\n", client->adapter->nr, + client->addr, ori_page); + mutex_unlock(&data->update_lock); + return ori_page; + } + + ret = wb_i2c_smbus_write_byte_data(client, WB_XDPE_I2C_PAGE_ADDR, WB_XDPE_I2C_VOUT_PAGE); + if (ret < 0) { + WB_XDPE_ERROR("%d-%04x: set xdpe avs vout page%u failed, ret: %d\n", client->adapter->nr, + client->addr, WB_XDPE_I2C_VOUT_PAGE, ret); + goto error; + } + + ret = xdpe_get_vout_precision(client, &vout_precision); + if (ret < 0) { + WB_XDPE_ERROR("%d-%04x: get xdpe avs vout precision failed, ret: %d\n", + client->adapter->nr, client->addr, ret); + goto error; + } + + vout_cmd = wb_i2c_smbus_read_word_data(client, WB_XDPE_I2C_VOUT_COMMAND); + if (vout_cmd < 0) { + ret = vout_cmd; + WB_XDPE_ERROR("%d-%04x: read xdpe vout command reg: 0x%x failed, ret: %d\n", + client->adapter->nr, client->addr, WB_XDPE_I2C_VOUT_COMMAND, ret); + goto error; + } + + wb_i2c_smbus_write_byte_data(client, WB_XDPE_I2C_PAGE_ADDR, ori_page); + mutex_unlock(&data->update_lock); + + vout = vout_cmd * 1000L * 1000L / vout_precision; + WB_XDPE_VERBOSE("%d-%04x: vout: %ld, vout_cmd: 0x%x, precision: %d\n", client->adapter->nr, + client->addr, vout, vout_cmd, vout_precision); + return snprintf(buf, PAGE_SIZE, "%ld\n", vout); +error: + wb_i2c_smbus_write_byte_data(client, WB_XDPE_I2C_PAGE_ADDR, ori_page); + mutex_unlock(&data->update_lock); + return ret; +} + +static ssize_t xdpe_avs_vout_store(struct device *dev, struct device_attribute *da, + const char *buf, size_t count) +{ + int ret, ori_page, vout_cmd, vout_cmd_set, vout_precision; + struct i2c_client *client; + struct xdpe_data *data; + long vout, vout_max, vout_min; + + client = to_i2c_client(dev); + ret = kstrtol(buf, 10, &vout); + if (ret) { + WB_XDPE_ERROR("%d-%04x: invalid value: %s \n", client->adapter->nr, client->addr, buf); + return -EINVAL; + } + + data = i2c_get_clientdata(client); + vout_max = data->vout_max; + vout_min = data->vout_min; + if ((vout > vout_max) || (vout < vout_min)) { + WB_XDPE_ERROR("%d-%04x: vout value: %ld, out of range [%ld, %ld] \n", client->adapter->nr, + client->addr, vout, vout_min, vout_max); + return -EINVAL; + } + + mutex_lock(&data->update_lock); + + ori_page = wb_i2c_smbus_read_byte_data(client, WB_XDPE_I2C_PAGE_ADDR); + if (ori_page < 0) { + WB_XDPE_ERROR("%d-%04x: read xdpe origin page failed, ret: %d\n", client->adapter->nr, + client->addr, ori_page); + mutex_unlock(&data->update_lock); + return ori_page; + } + + ret = wb_i2c_smbus_write_byte_data(client, WB_XDPE_I2C_PAGE_ADDR, WB_XDPE_I2C_VOUT_PAGE); + if (ret < 0) { + WB_XDPE_ERROR("%d-%04x: set xdpe avs vout page%u failed, ret: %d\n", client->adapter->nr, + client->addr, WB_XDPE_I2C_VOUT_PAGE, ret); + goto error; + } + + ret = xdpe_get_vout_precision(client, &vout_precision); + if (ret < 0) { + WB_XDPE_ERROR("%d-%04x: get xdpe avs vout precision failed, ret: %d\n", + client->adapter->nr, client->addr, ret); + goto error; + } + + vout_cmd_set = (vout * vout_precision) / (1000L * 1000L); + if (vout_cmd_set > 0xffff) { + WB_XDPE_ERROR("%d-%04x: invalid value, vout %ld, vout_precision: %d, vout_cmd_set: 0x%x\n", + client->adapter->nr, client->addr, vout, vout_precision, vout_cmd_set); + ret = -EINVAL; + goto error; + } + ret = wb_i2c_smbus_write_word_data(client, WB_XDPE_I2C_VOUT_COMMAND, vout_cmd_set); + if (ret < 0) { + WB_XDPE_ERROR("%d-%04x: set xdpe vout cmd reg: 0x%x, value: 0x%x failed, ret: %d\n", + client->adapter->nr, client->addr, WB_XDPE_I2C_VOUT_COMMAND, vout_cmd_set, ret); + goto error; + } + + vout_cmd = wb_i2c_smbus_read_word_data(client, WB_XDPE_I2C_VOUT_COMMAND); + if (vout_cmd < 0) { + ret = vout_cmd; + WB_XDPE_ERROR("%d-%04x: read xdpe vout command reg: 0x%x failed, ret: %d\n", + client->adapter->nr, client->addr, WB_XDPE_I2C_VOUT_COMMAND, ret); + goto error; + } + if (vout_cmd != vout_cmd_set) { + ret = -EIO; + WB_XDPE_ERROR("%d-%04x: vout cmd value check error, vout cmd read: 0x%x, vout cmd set: 0x%x\n", + client->adapter->nr, client->addr, vout_cmd, vout_cmd_set); + goto error; + + } + + wb_i2c_smbus_write_byte_data(client, WB_XDPE_I2C_PAGE_ADDR, ori_page); + mutex_unlock(&data->update_lock); + WB_XDPE_VERBOSE("%d-%04x: set vout cmd success, vout %ld, vout_precision: %d, vout_cmd_set: 0x%x\n", + client->adapter->nr, client->addr, vout, vout_precision, vout_cmd_set); + return count; +error: + wb_i2c_smbus_write_byte_data(client, WB_XDPE_I2C_PAGE_ADDR, ori_page); + mutex_unlock(&data->update_lock); + return ret; +} + +static ssize_t xdpe_avs_vout_max_show(struct device *dev, struct device_attribute *da, char *buf) +{ + struct i2c_client *client; + struct xdpe_data *data; + long vout_max; + + client = to_i2c_client(dev); + data = i2c_get_clientdata(client); + vout_max = data->vout_max; + return snprintf(buf, PAGE_SIZE, "%ld\n", vout_max); +} + +static ssize_t xdpe_avs_vout_max_store(struct device *dev, struct device_attribute *da, + const char *buf, size_t count) +{ + int ret; + struct i2c_client *client; + struct xdpe_data *data; + long vout_max; + + client = to_i2c_client(dev); + ret = kstrtol(buf, 10, &vout_max); + if (ret) { + WB_XDPE_ERROR("%d-%04x: invalid value: %s \n", client->adapter->nr, client->addr, buf); + return -EINVAL; + } + WB_XDPE_VERBOSE("%d-%04x: vout max threshold: %ld", client->adapter->nr, client->addr, + vout_max); + data = i2c_get_clientdata(client); + data->vout_max = vout_max; + return count; +} + +static ssize_t xdpe_avs_vout_min_show(struct device *dev, struct device_attribute *da, char *buf) +{ + struct i2c_client *client; + struct xdpe_data *data; + long vout_min; + + client = to_i2c_client(dev); + data = i2c_get_clientdata(client); + vout_min = data->vout_min; + return snprintf(buf, PAGE_SIZE, "%ld\n", vout_min); +} + +static ssize_t xdpe_avs_vout_min_store(struct device *dev, struct device_attribute *da, + const char *buf, size_t count) +{ + int ret; + struct i2c_client *client; + struct xdpe_data *data; + long vout_min; + + client = to_i2c_client(dev); + ret = kstrtol(buf, 10, &vout_min); + if (ret) { + WB_XDPE_ERROR("%d-%04x: invalid value: %s \n", client->adapter->nr, client->addr, buf); + return -EINVAL; + } + WB_XDPE_VERBOSE("%d-%04x: vout min threshold: %ld", client->adapter->nr, client->addr, + vout_min); + data = i2c_get_clientdata(client); + data->vout_min = vout_min; + return count; +} + +/* xdpe hwmon */ +static SENSOR_DEVICE_ATTR(power1_input, S_IRUGO ,xdpe_power_value_show, NULL, 0x072c); +static SENSOR_DEVICE_ATTR(power2_input, S_IRUGO ,xdpe_power_value_show, NULL, 0x0b2c); +static SENSOR_DEVICE_ATTR(power3_input, S_IRUGO ,xdpe_power_value_show, NULL, 0x072c0b2c); + +static struct attribute *xdpe_hwmon_attrs[] = { + &sensor_dev_attr_power1_input.dev_attr.attr, + &sensor_dev_attr_power2_input.dev_attr.attr, + &sensor_dev_attr_power3_input.dev_attr.attr, + NULL +}; +ATTRIBUTE_GROUPS(xdpe_hwmon); + +/* xdpe sysfs */ +static SENSOR_DEVICE_ATTR(avs_vout, S_IRUGO | S_IWUSR, xdpe_avs_vout_show, xdpe_avs_vout_store, 0); +static SENSOR_DEVICE_ATTR(avs_vout_max, S_IRUGO | S_IWUSR, xdpe_avs_vout_max_show, xdpe_avs_vout_max_store, 0); +static SENSOR_DEVICE_ATTR(avs_vout_min, S_IRUGO | S_IWUSR, xdpe_avs_vout_min_show, xdpe_avs_vout_min_store, 0); + +static struct attribute *xdpe132g5c_sysfs_attrs[] = { + &sensor_dev_attr_avs_vout.dev_attr.attr, + &sensor_dev_attr_avs_vout_max.dev_attr.attr, + &sensor_dev_attr_avs_vout_min.dev_attr.attr, + NULL, +}; + +static const struct attribute_group xdpe132g5c_sysfs_attrs_group = { + .attrs = xdpe132g5c_sysfs_attrs, +}; + +static int xdpe132g5c_probe(struct i2c_client *client, const struct i2c_device_id *id) +{ + struct xdpe_data *data; + int ret; + + WB_XDPE_VERBOSE("bus: %d, addr: 0x%02x do probe.\n", client->adapter->nr, client->addr); + data = devm_kzalloc(&client->dev, sizeof(struct xdpe_data), GFP_KERNEL); + if (!data) { + dev_err(&client->dev, "devm_kzalloc failed.\n"); + return -ENOMEM; + } + + data->client = client; + i2c_set_clientdata(client, data); + mutex_init(&data->update_lock); + + ret = sysfs_create_group(&client->dev.kobj, &xdpe132g5c_sysfs_attrs_group); + if (ret != 0) { + dev_err(&client->dev, "Create xdpe132g5c sysfs failed, ret: %d\n", ret); + return ret; + } + data->hwmon_dev = hwmon_device_register_with_groups(&client->dev, client->name, data, + xdpe_hwmon_groups); + if (IS_ERR(data->hwmon_dev)) { + ret = PTR_ERR(data->hwmon_dev); + sysfs_remove_group(&client->dev.kobj, &xdpe132g5c_sysfs_attrs_group); + dev_err(&client->dev, "Failed to register xdpe hwmon device, ret: %d\n", ret); + return ret; + } + data->vout_max = WB_XDPE_VOUT_MAX_THRESHOLD; + data->vout_min = WB_XDPE_VOUT_MIN_THRESHOLD; + dev_info(&client->dev, "xdpe132g5c probe success\n"); + return 0; +} + +static int xdpe132g5c_remove(struct i2c_client *client) +{ + struct xdpe_data *data; + + WB_XDPE_VERBOSE("bus: %d, addr: 0x%02x do remove\n", client->adapter->nr, client->addr); + data = i2c_get_clientdata(client); + hwmon_device_unregister(data->hwmon_dev); + sysfs_remove_group(&client->dev.kobj, &xdpe132g5c_sysfs_attrs_group); + return 0; +} + +static const struct i2c_device_id xdpe132g5c_id[] = { + {"wb_xdpe132g5c", 0}, + {} +}; + +MODULE_DEVICE_TABLE(i2c, xdpe132g5c_id); + +static const struct of_device_id __maybe_unused xdpe132g5c_of_match[] = { + {.compatible = "infineon,wb_xdpe132g5c"}, + {} +}; +MODULE_DEVICE_TABLE(of, xdpe132g5c_of_match); + +static struct i2c_driver wb_xdpe132g5c_driver = { + .driver = { + .name = "wb_xdpe132g5c", + .of_match_table = of_match_ptr(xdpe132g5c_of_match), + }, + .probe = xdpe132g5c_probe, + .remove = xdpe132g5c_remove, + .id_table = xdpe132g5c_id, +}; + +module_i2c_driver(wb_xdpe132g5c_driver); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("support"); +MODULE_DESCRIPTION("I2C driver for Infineon XDPE132 family"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/script/auto_update.py b/platform/broadcom/sonic-platform-modules-ragile/common/script/auto_update.py new file mode 100755 index 000000000000..838e64f6b417 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/script/auto_update.py @@ -0,0 +1,196 @@ +#!/usr/bin/env python3 + +try: + import os + import json + import logging + import sys + from sonic_py_common import device_info + from sonic_platform.platform import Platform +except ImportError as e: + raise ImportError(str(e) + "- required module not found") from e + +PLATFORM_COMPONENTS_FILE = "platform_components.json" +CHASSIS_KEY = "chassis" +COMPONENT_KEY = "component" +FIRMWARE_KEY = "firmware" +VERSION_KEY = "version" +chassis_component_map = {} +current_chassis_component_map = {} +current_chassis = Platform().get_chassis() + + +def parse_component_section(section, component): + if not isinstance(component, dict): + logging.error("dictionary is expected: key=%s", COMPONENT_KEY) + return False + + if not component: + return False + + missing_key = None + chassis_component_map[section] = {} + + for key1, value1 in component.items(): + if not isinstance(value1, dict): + logging.error("dictionary is expected: key=%s", key1) + return False + + if value1: + if len(value1) < 1 or len(value1) > 3: + logging.error("unexpected number of records: key=%s", key1) + return False + + if FIRMWARE_KEY not in value1: + missing_key = FIRMWARE_KEY + break + + for key2, value2 in value1.items(): + if not isinstance(value2, str): + logging.error("string is expected: key=%s", key2) + return False + + chassis_component_map[section][key1] = value1 + + if missing_key is not None: + logging.error("\"%s\" key hasn't been found", missing_key) + return False + + return True + + +def parse_chassis_section(chassis): + if not isinstance(chassis, dict): + logging.error("dictionary is expected: key=%s", CHASSIS_KEY) + return False + + if not chassis: + logging.error("dictionary is empty: key=%s", CHASSIS_KEY) + return False + + if len(chassis) != 1: + logging.error("unexpected number of records: key=%s", CHASSIS_KEY) + return False + + for key, value in chassis.items(): + if not isinstance(value, dict): + logging.error("dictionary is expected: key=%s", key) + return False + + if not value: + logging.error("dictionary is empty: key=%s", key) + return False + + if COMPONENT_KEY not in value: + logging.error("\"%s\" key hasn't been found", COMPONENT_KEY) + return False + + if len(value) != 1: + logging.error("unexpected number of records: key=%s", key) + return False + + return parse_component_section(key, value[COMPONENT_KEY]) + + return False + + +def get_platform_components_path(): + PLATFORM_COMPONENTS_PATH_TEMPLATE = "/usr/share/sonic/device/{}/{}" + PLATFORM_COMPONENTS_FILE_PATH = PLATFORM_COMPONENTS_PATH_TEMPLATE.format( + device_info.get_platform(), PLATFORM_COMPONENTS_FILE) + return PLATFORM_COMPONENTS_FILE_PATH + + +def parse_platform_components(): + platform_components_path = get_platform_components_path() + with open(platform_components_path) as platform_components: + data = json.load(platform_components) + + if not isinstance(data, dict): + logging.error("dictionary is expected: key=root") + return False + + if not data: + logging.error("dictionary is empty: key=root") + return False + + if CHASSIS_KEY not in data: + logging.error("\"%s\" key hasn't been found", CHASSIS_KEY) + return False + + return parse_chassis_section(data[CHASSIS_KEY]) + + +def get_current_chassis_component_map(): + chassis_name = current_chassis.get_name() + current_chassis_component_map[chassis_name] = {} + + component_list = current_chassis.get_all_components() + for component in component_list: + component_name = component.get_name() + current_chassis_component_map[chassis_name][component_name] = component + + return current_chassis_component_map + + +def get_upgrade_dict(): + upgrade_dict = {} + firmware_version_current = "" + firmware_version_available = "" + + if not parse_platform_components(): + logging.error("Reading platform_components.json i, ion exception") + sys.exit(1) + + if not get_current_chassis_component_map(): + logging.error("Reading firmware i, ion from the driver is abnormal") + sys.exit(1) + + chassis_name = current_chassis.get_name() + diff_keys = set(chassis_component_map.keys()) ^ set(current_chassis_component_map.keys()) + if diff_keys: + logging.error("%s names mismatch: keys=%s", chassis_name, str(list(diff_keys))) + return None + + for chassis_name, component_map in current_chassis_component_map.items(): + for component_name, component in component_map.items(): + firmware_version_current = component.get_firmware_version() + if component_name in chassis_component_map[chassis_name]: + firmware_version_available = chassis_component_map[chassis_name][component_name][VERSION_KEY] + else: + logging.warning("can't find %s in %s", component_name, PLATFORM_COMPONENTS_FILE) + break + + if not os.path.exists(chassis_component_map[chassis_name][component_name][FIRMWARE_KEY]): + logging.error("%s does not exist", chassis_component_map[chassis_name][component_name][FIRMWARE_KEY]) + break + + if firmware_version_available != firmware_version_current: + upgrade_dict[component_name] = chassis_component_map[chassis_name][component_name][FIRMWARE_KEY] + + return upgrade_dict + + +def auto_upgrade(): + upgrade_result_dict = {} + chassis_name = current_chassis.get_name() + + upgrade_dict = get_upgrade_dict() + if not upgrade_dict: + logging.info("No firmware found for automatic upgrade") + return None + + component_map = current_chassis_component_map[chassis_name] + for value, path in upgrade_dict.items(): + status = component_map[value].install_firmware(path) + if status: + upgrade_result_dict[value] = "success" + logging.info("%s Upgrade Success", value) + else: + upgrade_result_dict[value] = "failed" + logging.error("%s Upgrade Failed", value) + return upgrade_result_dict + + +if __name__ == '__main__': + auto_upgrade() diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/script/avscontrol.py b/platform/broadcom/sonic-platform-modules-ragile/common/script/avscontrol.py index 25874ddb8219..a0a2ccaac938 100755 --- a/platform/broadcom/sonic-platform-modules-ragile/common/script/avscontrol.py +++ b/platform/broadcom/sonic-platform-modules-ragile/common/script/avscontrol.py @@ -1,18 +1,22 @@ #!/usr/bin/env python3 -# -*- coding: UTF-8 -*- -import click +import sys +import os import time -import traceback -from ragileutil import wait_docker, STARTMODULE, AVSUTIL -from rgutil.logutil import Logger +import syslog +import glob +import click +from platform_config import MAC_DEFAULT_PARAM +from platform_util import getSdkReg, write_sysfs, get_value, get_format_value + + +AVSCTROL_DEBUG_FILE = "/etc/.avscontrol_debug_flag" -try: - from rest.rest import BMCMessage -except ImportError: - pass +AVSCTROLERROR = 1 +AVSCTROLDEBUG = 2 -CONTEXT_SETTINGS = dict(help_option_names=["-h", "--help"]) -logger = Logger("AVSCONTROL", syslog=True) +debuglevel = 0 + +CONTEXT_SETTINGS = {"help_option_names": ['-h', '--help']} class AliasedGroup(click.Group): @@ -20,72 +24,180 @@ def get_command(self, ctx, cmd_name): rv = click.Group.get_command(self, ctx, cmd_name) if rv is not None: return rv - matches = [x for x in self.list_commands(ctx) if x.startswith(cmd_name)] + matches = [x for x in self.list_commands(ctx) + if x.startswith(cmd_name)] if not matches: return None - elif len(matches) == 1: + if len(matches) == 1: return click.Group.get_command(self, ctx, matches[0]) - ctx.fail("Too many matches: %s" % ", ".join(sorted(matches))) - - -def do_avs_ctrl(): - index = 0 - url = "/xyz/openbmc_project/hostchannel/attr/MacRov" - while True: - if ( - "avscontrol_restful" in STARTMODULE - and STARTMODULE["avscontrol_restful"] == 1 - ): - try: - # for alibmc rest.py has define get_macrov_value function - get_macrov_value = getattr(BMCMessage(), "get_macrov_value", None) - if callable(get_macrov_value): - macrov_value = int(get_macrov_value()) - else: - macrov_value = int(BMCMessage().getBmcValue(url)) - if macrov_value >= 0: - break - except Exception as e: - time.sleep(2) - continue + ctx.fail('Too many matches: %s' % ', '.join(sorted(matches))) + return None + + +def avscontrol_debug(s): + if AVSCTROLDEBUG & debuglevel: + syslog.openlog("AVSCONTROL", syslog.LOG_PID) + syslog.syslog(syslog.LOG_DEBUG, s) + + +def avscontrol_error(s): + if AVSCTROLERROR & debuglevel: + syslog.openlog("AVSCONTROL", syslog.LOG_PID) + syslog.syslog(syslog.LOG_ERR, s) + + +def avserror(s): + # s = s.decode('utf-8').encode('gb2312') + syslog.openlog("AVSCONTROL", syslog.LOG_PID) + syslog.syslog(syslog.LOG_ERR, s) + + +def avsinfo(s): + syslog.openlog("AVSCONTROL", syslog.LOG_PID) + syslog.syslog(syslog.LOG_INFO, s) + + +def debug_init(): + global debuglevel + if os.path.exists(AVSCTROL_DEBUG_FILE): + debuglevel = debuglevel | AVSCTROLDEBUG | AVSCTROLERROR + else: + debuglevel = debuglevel & ~(AVSCTROLDEBUG | AVSCTROLERROR) + + +def set_avs_value_sysfs(conf, dcdc_value): + msg = "" + formula = conf.get("formula", None) + loc = conf.get("loc") + locations = glob.glob(loc) + if len(locations) == 0: + msg = "avs sysfs loc: %s not found" % loc + avscontrol_error(msg) + return False, msg + sysfs_loc = locations[0] + avscontrol_debug("set_avs_value_sysfs, loc: %s, origin dcdc value: %s, formula: %s" % + (sysfs_loc, dcdc_value, formula)) + if formula is not None: + dcdc_value = get_format_value(formula % (dcdc_value)) + wr_val = str(dcdc_value) + avscontrol_debug("set_avs_value_sysfs, write val: %s" % wr_val) + ret, log = write_sysfs(sysfs_loc, wr_val) + if ret is False: + msg = "set_avs_value_sysfs failed, msg: %s" % log + avscontrol_error(msg) + return ret, msg + + +def set_avs_value(avs_conf, dcdc_value): + set_avs_way = avs_conf.get("set_avs", {}).get("gettype") + if set_avs_way != "sysfs": + msg = "unsupport set avs value type: %s" % set_avs_way + avscontrol_error(msg) + return False, msg + ret, msg = set_avs_value_sysfs(avs_conf["set_avs"], dcdc_value) + return ret, msg + + +def get_dcdc_value(avs_conf, rov_value): + msg = "" + mac_avs_param = avs_conf.get("mac_avs_param", {}) + if rov_value not in mac_avs_param.keys(): + if avs_conf["type"] == 0: + msg = "VID:0x%x out of range, voltage regulate stop" % rov_value + avsinfo(msg) + return False, msg + dcdc_value = mac_avs_param[avs_conf["default"]] + avsinfo("VID:0x%x out of range, use default VID:0x%x" % (rov_value, dcdc_value)) + else: + dcdc_value = mac_avs_param[rov_value] + return True, dcdc_value + + +def get_rov_value_cpld(avs_conf): + cpld_avs_config = avs_conf["cpld_avs"] + return get_value(cpld_avs_config) + + +def get_rov_value_sdk(avs_conf): + name = avs_conf["sdkreg"] + ret, status = getSdkReg(name) + if ret is False: + return False, status + status = int(status, 16) + # shift operation + if avs_conf["sdktype"] != 0: + status = (status >> avs_conf["macregloc"]) & avs_conf["mask"] + macavs = status + return True, macavs + + +def doAvsCtrol_single(avs_conf): + try: + avs_name = avs_conf.get("name") + rov_source = avs_conf["rov_source"] + if rov_source == 0: + ret, rov_value = get_rov_value_cpld(avs_conf) # get rov from cpld reg else: - if AVSUTIL.mac_adj(): - break + ret, rov_value = get_rov_value_sdk(avs_conf) # get rov from sdk reg + if ret is False: + msg = "%s get rov_value failed, msg: %s" % (avs_name, rov_value) + avscontrol_error(msg) + return False, msg + avscontrol_debug("%s rov_value: 0x%x" % (avs_name, rov_value)) + ret, dcdc_value = get_dcdc_value(avs_conf, rov_value) + if ret is False: + msg = "%s get output voltage value failed, msg: %s" % (avs_name, dcdc_value) + avscontrol_error(msg) + return False, msg + ret, msg = set_avs_value(avs_conf, dcdc_value) + return ret, msg + except Exception as e: + msg = "%s avscontrol raise exception, msg: %s" % (avs_name, str(e)) + avscontrol_error(msg) + return False, msg + + +def doAvsCtrol(avs_conf): + retry_time = avs_conf.get("retry", 10) + for i in range(retry_time): + debug_init() + ret, log = doAvsCtrol_single(avs_conf) + if ret is True: + return True, log + time.sleep(1) + return False, log - index += 1 - if index >= 10: - logger.error("%%DEV_MONITOR-AVS: MAC Voltage adjust failed.") - exit(-1) - logger.info("%%AVSCONTROL success") - exit(0) +def run(): + # wait 30s for device steady + time.sleep(30) + errcnt = 0 + msg = "" + for item in MAC_DEFAULT_PARAM: + status, log = doAvsCtrol(item) + if status is False: + errcnt += 1 + msg += log -def run(interval): - while True: - try: - if wait_docker(timeout=0) == True: - time.sleep(10) # w10s - do_avs_ctrl() - time.sleep(interval) - except Exception as e: - traceback.print_exc() - print(e) + if errcnt == 0: + avsinfo("%%AVSCONTROL success") + sys.exit(0) + avserror("%%DEV_MONITOR-AVS: MAC Voltage adjust failed.") + avserror("%%DEV_MONITOR-AVS: errmsg: %s" % msg) + sys.exit(1) @click.group(cls=AliasedGroup, context_settings=CONTEXT_SETTINGS) def main(): - """device operator""" - pass + '''device operator''' @main.command() def start(): - """start AVS control""" - logger.info("%%AVSCONTROL start") - interval = 5 - run(interval) + '''start AVS control''' + avsinfo("%%AVSCONTROL start") + run() -##device_i2c operation -if __name__ == "__main__": +if __name__ == '__main__': main() diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/script/dev_monitor.py b/platform/broadcom/sonic-platform-modules-ragile/common/script/dev_monitor.py new file mode 100755 index 000000000000..e13377b80fe9 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/script/dev_monitor.py @@ -0,0 +1,303 @@ +#!/usr/bin/env python3 +import sys +import os +import time +import syslog +import traceback +import click +from platform_config import DEV_MONITOR_PARAM +from platform_util import io_rd, wbi2cget + + +CONTEXT_SETTINGS = {"help_option_names": ['-h', '--help']} + + +class AliasedGroup(click.Group): + def get_command(self, ctx, cmd_name): + rv = click.Group.get_command(self, ctx, cmd_name) + if rv is not None: + return rv + matches = [x for x in self.list_commands(ctx) + if x.startswith(cmd_name)] + if not matches: + return None + if len(matches) == 1: + return click.Group.get_command(self, ctx, matches[0]) + ctx.fail('Too many matches: %s' % ', '.join(sorted(matches))) + return None + + +DEVMONITOR_DEBUG_FILE = "/etc/.devmonitor_debug_flag" + +debuglevel = 0 + + +def debug_init(): + global debuglevel + if os.path.exists(DEVMONITOR_DEBUG_FILE): + debuglevel = 1 + else: + debuglevel = 0 + + +def devwarninglog(s): + # s = s.decode('utf-8').encode('gb2312') + syslog.openlog("DEVMONITOR", syslog.LOG_PID) + syslog.syslog(syslog.LOG_WARNING, s) + + +def devcriticallog(s): + # s = s.decode('utf-8').encode('gb2312') + syslog.openlog("DEVMONITOR", syslog.LOG_PID) + syslog.syslog(syslog.LOG_CRIT, s) + + +def deverror(s): + # s = s.decode('utf-8').encode('gb2312') + syslog.openlog("DEVMONITOR", syslog.LOG_PID) + syslog.syslog(syslog.LOG_ERR, s) + + +def devinfo(s): + # s = s.decode('utf-8').encode('gb2312') + syslog.openlog("DEVMONITOR", syslog.LOG_PID) + syslog.syslog(syslog.LOG_INFO, s) + + +def devdebuglog(s): + # s = s.decode('utf-8').encode('gb2312') + if debuglevel == 1: + syslog.openlog("DEVMONITOR", syslog.LOG_PID) + syslog.syslog(syslog.LOG_DEBUG, s) + + +class DevMonitor(): + + def getpresentstatus(self, param): + try: + ret = {} + ret["status"] = '' + gettype = param.get('gettype') + presentbit = param.get('presentbit') + okval = param.get('okval') + if gettype == "io": + io_addr = param.get('io_addr') + val = io_rd(io_addr) + if val is None: + ret["status"] = "NOT OK" + return ret + retval = val + else: + bus = param.get('bus') + loc = param.get('loc') + offset = param.get('offset') + ind, val = wbi2cget(bus, loc, offset) + if ind is not True: + ret["status"] = "NOT OK" + return ret + retval = val + val_t = (int(retval, 16) & (1 << presentbit)) >> presentbit + if val_t != okval: + ret["status"] = "ABSENT" + else: + ret["status"] = "PRESENT" + except Exception as e: + ret["status"] = "NOT OK" + deverror("getpresentstatus error") + deverror(str(e)) + return ret + + def removeDev(self, bus, loc): + cmd = "echo 0x%02x > /sys/bus/i2c/devices/i2c-%d/delete_device" % (loc, bus) + devpath = "/sys/bus/i2c/devices/%d-%04x" % (bus, loc) + if os.path.exists(devpath): + os.system(cmd) + + def addDev(self, name, bus, loc): + if name == "lm75": + time.sleep(0.1) + cmd = "echo %s 0x%02x > /sys/bus/i2c/devices/i2c-%d/new_device" % (name, loc, bus) + devpath = "/sys/bus/i2c/devices/%d-%04x" % (bus, loc) + if os.path.exists(devpath) is False: + os.system(cmd) + + def checkattr(self, bus, loc, attr): + try: + attrpath = "/sys/bus/i2c/devices/%d-%04x/%s" % (bus, loc, attr) + if os.path.exists(attrpath): + return True + except Exception as e: + deverror("checkattr error") + deverror(str(e)) + return False + + def monitor(self, ret): + totalerr = 0 + for item in ret: + try: + name = item.get('name') + itemattr = '%sattr' % name + val_t = getattr(DevMonitor, itemattr, None) + if val_t == 'OK': + continue + present = item.get('present', None) + devices = item.get('device') + err_t = 0 + for item_dev in devices: + item_devattr = '%s' % (item_dev['id']) + val_t = getattr(DevMonitor, item_devattr, None) + if val_t == 'OK': + continue + devname = item_dev.get('name') + bus = item_dev.get('bus') + loc = item_dev.get('loc') + attr = item_dev.get('attr') + if self.checkattr(bus, loc, attr) is False: + err_t -= 1 + setattr(DevMonitor, item_devattr, 'NOT OK') + if present is not None: + presentstatus = self.getpresentstatus(present) + devdebuglog("%s present status:%s" % (name, presentstatus.get('status'))) + if presentstatus.get('status') == 'PRESENT': + self.removeDev(bus, loc) + time.sleep(0.1) + self.addDev(devname, bus, loc) + else: + self.removeDev(bus, loc) + time.sleep(0.1) + self.addDev(devname, bus, loc) + else: + setattr(DevMonitor, item_devattr, 'OK') + val_t = getattr(DevMonitor, item_devattr, None) + devdebuglog("%s status %s" % (item_devattr, val_t)) + if err_t == 0: + setattr(DevMonitor, itemattr, 'OK') + else: + totalerr -= 1 + setattr(DevMonitor, itemattr, 'NOT OK') + val_t = getattr(DevMonitor, itemattr, None) + devdebuglog("%s status %s" % (itemattr, val_t)) + except Exception as e: + totalerr -= 1 + deverror("monitor error") + deverror(str(e)) + return totalerr + + def psusmonitor(self): + psus_conf = DEV_MONITOR_PARAM.get('psus') + if psus_conf is None: + return 0 + psusattr = 'psusattr' + val_t = getattr(DevMonitor, psusattr, None) + if val_t == 'OK': + return 0 + ret = self.monitor(psus_conf) + if ret == 0: + setattr(DevMonitor, psusattr, 'OK') + else: + setattr(DevMonitor, psusattr, 'NOT OK') + val_t = getattr(DevMonitor, psusattr, None) + devdebuglog("psusattr:value:%s" % (val_t)) + return ret + + def fansmonitor(self): + fans_conf = DEV_MONITOR_PARAM.get('fans') + if fans_conf is None: + return 0 + fansattr = 'fansattr' + val_t = getattr(DevMonitor, fansattr, None) + if val_t == 'OK': + return 0 + ret = self.monitor(fans_conf) + if ret == 0: + setattr(DevMonitor, fansattr, 'OK') + else: + setattr(DevMonitor, fansattr, 'NOT OK') + val_t = getattr(DevMonitor, fansattr, None) + devdebuglog("fansattr:value:%s" % (val_t)) + return ret + + def slotsmonitor(self): + slots_conf = DEV_MONITOR_PARAM.get('slots') + if slots_conf is None: + return 0 + slotsattr = 'slotsattr' + val_t = getattr(DevMonitor, slotsattr, None) + if val_t == 'OK': + return 0 + ret = self.monitor(slots_conf) + if ret == 0: + setattr(DevMonitor, slotsattr, 'OK') + else: + setattr(DevMonitor, slotsattr, 'NOT OK') + val_t = getattr(DevMonitor, slotsattr, None) + devdebuglog("slotsattr:value:%s" % (val_t)) + return ret + + def othersmonitor(self): + others_conf = DEV_MONITOR_PARAM.get('others') + if others_conf is None: + return 0 + othersattr = 'othersattr' + val_t = getattr(DevMonitor, othersattr, None) + if val_t == 'OK': + return 0 + ret = self.monitor(others_conf) + if ret == 0: + setattr(DevMonitor, othersattr, 'OK') + else: + setattr(DevMonitor, othersattr, 'NOT OK') + val_t = getattr(DevMonitor, othersattr, None) + devdebuglog("othersattr:value:%s" % (val_t)) + return ret + + +def doDevMonitor(devMonitor): + ret_t = 0 + ret_t += devMonitor.psusmonitor() + ret_t += devMonitor.fansmonitor() + ret_t += devMonitor.slotsmonitor() + ret_t += devMonitor.othersmonitor() + return ret_t + + +def run(interval, devMonitor): + # devMonitor.devattrinit() + while True: + try: + debug_init() + ret = doDevMonitor(devMonitor) + except Exception as e: + traceback.print_exc() + deverror(str(e)) + ret = -1 + if ret == 0: + time.sleep(5) + devinfo("dev_monitor finished!") + sys.exit(0) + time.sleep(interval) + + +@click.group(cls=AliasedGroup, context_settings=CONTEXT_SETTINGS) +def main(): + '''device operator''' + + +@main.command() +def start(): + '''start device monitor''' + devinfo("dev_monitor start") + devMonitor = DevMonitor() + interval = DEV_MONITOR_PARAM.get('polling_time', 10) + run(interval, devMonitor) + + +@main.command() +def stop(): + '''stop device monitor ''' + devinfo("stop") + + +# device_i2c operation +if __name__ == '__main__': + main() diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/script/device_i2c.py b/platform/broadcom/sonic-platform-modules-ragile/common/script/device_i2c.py deleted file mode 100755 index a30dd7d86a41..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/common/script/device_i2c.py +++ /dev/null @@ -1,327 +0,0 @@ -#!/usr/bin/env python3 -# -*- coding: UTF-8 -*- - -import click -import os -import time -import subprocess -from ragileconfig import * -from ragileutil import rgpciwr, rgi2cset, io_wr -from sonic_py_common.general import getstatusoutput_noshell, getstatusoutput_noshell_pipe - -CONTEXT_SETTINGS = dict(help_option_names=['-h', '--help']) - -class AliasedGroup(click.Group): - def get_command(self, ctx, cmd_name): - rv = click.Group.get_command(self, ctx, cmd_name) - if rv is not None: - return rv - matches = [x for x in self.list_commands(ctx) - if x.startswith(cmd_name)] - if not matches: - return None - elif len(matches) == 1: - return click.Group.get_command(self, ctx, matches[0]) - ctx.fail('Too many matches: %s' % ', '.join(sorted(matches))) - -def log_os_system(cmd): - u'''execute shell command''' - status, output = getstatusoutput_noshell(cmd) - if status: - print(output) - return status, output - -def write_sysfs_value(reg_name, value): - u'''write sysfs file''' - mb_reg_file = "/sys/bus/i2c/devices/" + reg_name - if (not os.path.isfile(mb_reg_file)): - print(mb_reg_file, 'not found !') - return False - try: - with open(mb_reg_file, 'w') as fd: - fd.write(value) - except Exception as error: - return False - return True - -def check_driver(): - u'''whether there is driver start with rg''' - status, output = getstatusoutput_noshell_pipe(["lsmod"], ["grep", "rg"], ["wc", "-l"]) - #System execution error - if status: - return False - if output.isdigit() and int(output) > 0: - return True - else: - return False - -def get_pid(name): - ret = [] - for dirname in os.listdir('/proc'): - if dirname == 'curproc': - continue - try: - with open('/proc/{}/cmdline'.format(dirname), mode='r') as fd: - content = fd.read() - except Exception: - continue - if name in content: - ret.append(dirname) - return ret - -def start_avs_ctrl(): - cmd = ["avscontrol.py", "start"] - rets = get_pid("avscontrol.py") - if len(rets) == 0: - subprocess.Popen(cmd) - -def start_fan_ctrl(): - if STARTMODULE['fancontrol'] == 1: - cmd = ["fancontrol.py", "start"] - rets = get_pid("fancontrol.py") - if len(rets) == 0: - subprocess.Popen(cmd) - -def starthal_fanctrl(): - if STARTMODULE.get('hal_fanctrl',0) == 1: - cmd = ["hal_fanctrl.py", "start"] - rets = get_pid("hal_fanctrl.py") - if len(rets) == 0: - subprocess.Popen(cmd) - -def starthal_ledctrl(): - if STARTMODULE.get('hal_ledctrl',0) == 1: - cmd = ["hal_ledctrl.py", "start"] - rets = get_pid("hal_ledctrl.py") - if len(rets) == 0: - subprocess.Popen(cmd) - -def start_slot_monitor(): - if STARTMODULE.get('slot_monitor',0) == 1: - cmd = ["slot_monitor.py", "start"] - rets = get_pid("slot_monitor.py") - if len(rets) == 0: - subprocess.Popen(cmd) - -def stop_fan_ctrl(): - u'''disable fan timer service''' - if STARTMODULE['fancontrol'] == 1: - rets = get_pid("fancontrol.py") # - for ret in rets: - cmd = ["kill", ret] - subprocess.call(cmd) - return True - -def stophal_ledctrl(): - if STARTMODULE.get('hal_ledctrl',0) == 1: - rets = get_pid("hal_ledctrl.py") - for ret in rets: - cmd = ["kill", ret] - subprocess.call(cmd) - return True - -def stop_slot_monitor(): - u'''disable slot timer service''' - if STARTMODULE.get('slot_monitor',0) == 1: - rets = get_pid("slot_monitor.py") # - for ret in rets: - cmd = ["kill", ret] - subprocess.call(cmd) - return True - -def rm_dev(bus, loc): - devpath = "/sys/bus/i2c/devices/%d-%04x"%(bus, loc) - if os.path.exists(devpath): - with open("/sys/bus/i2c/devices/i2c-%d/delete_device" % bus, 'w') as f: - f.write('0x%02x\n' % loc) - -def add_dev(name, bus, loc): - if name == "lm75": - time.sleep(0.1) - pdevpath = "/sys/bus/i2c/devices/i2c-%d/" % (bus) - for i in range(1, 100):#wait for mother-bus generation，maximum wait time is 10s - if os.path.exists(pdevpath) is True: - break - time.sleep(0.1) - if i % 10 == 0: - click.echo("%%DEVICE_I2C-INIT: %s not found, wait 0.1 second ! i %d " % (pdevpath,i)) - - devpath = "/sys/bus/i2c/devices/%d-%04x"%(bus, loc) - if os.path.exists(devpath) is False: - with open("/sys/bus/i2c/devices/i2c-%d/new_device" % bus, 'w') as f: - f.write('%s 0x%02x\n' % (name, loc)) - -def removedevs(): - devs = GLOBALCONFIG["DEVS"] - for index in range(len(devs)-1, -1, -1 ): - rm_dev(devs[index]["bus"] , devs[index]["loc"]) - -def adddevs(): - devs = GLOBALCONFIG["DEVS"] - for dev in range(0, devs.__len__()): - add_dev(devs[dev]["name"], devs[dev]["bus"] , devs[dev]["loc"]) - -def checksignaldriver(name): - status, output = getstatusoutput_noshell_pipe(["lsmod"], ["grep", name], ["wc", "-l"]) - #System execution error - if status: - return False - if output.isdigit() and int(output) > 0: - return True - else: - return False - -def adddriver(name, delay): - cmd = ["modprobe", name] - if delay != 0: - time.sleep(delay) - if not checksignaldriver(name): - getstatusoutput_noshell(cmd) - -def removedriver(name, delay): - realname = name.lstrip().split(" ")[0]; - cmd = ["rmmod", "-f", realname] - if checksignaldriver(realname): - getstatusoutput_noshell(cmd) - -def removedrivers(): - u'''remove all drivers''' - if GLOBALCONFIG is None: - click.echo("%%DEVICE_I2C-INIT: load global config failed.") - return - drivers = GLOBALCONFIG.get("DRIVERLISTS", None) - if drivers is None: - click.echo("%%DEVICE_I2C-INIT: load driver list failed.") - return - for index in range(len(drivers)-1, -1, -1 ): - delay = 0 - name = "" - if type(drivers[index]) == dict and "delay" in drivers[index]: - name = drivers[index].get("name") - delay = drivers[index]["delay"] - else: - name = drivers[index] - removedriver(name, delay) - -def adddrivers(): - u'''add drivers''' - if GLOBALCONFIG is None: - click.echo("%%DEVICE_I2C-INIT: load global config failed.") - return - drivers = GLOBALCONFIG.get("DRIVERLISTS", None) - if drivers is None: - click.echo("%%DEVICE_I2C-INIT: load driver list failed.") - return - for index in range(0 ,len(drivers)): - delay = 0 - name = "" - if type(drivers[index]) == dict and "delay" in drivers[index]: - name = drivers[index].get("name") - delay = drivers[index]["delay"] - else: - name = drivers[index] - adddriver(name, delay) - -def otherinit(): - for index in GLOBALINITPARAM: - index_type = index.get("type", None) - if index_type == "io": - ret = io_wr(index.get("offset"), index.get("val")) - else: - ret, _ = rgi2cset( - index.get("bus"), - index.get("devaddr"), - index.get("offset"), - index.get("val") - ) - if not ret: - click.echo("%%DEVICE_I2C-INIT: init param %s failed." % index.get("name")) - - for index in GLOBALINITCOMMAND: - log_os_system(index) - -def unload_driver(): - u'''remove devices and drivers''' - stop_fan_ctrl() # disable fan-control service - removedevs() # remove other devices - removedrivers() # remove drivers - -def reload_driver(): - u'''reload devices and drivers''' - removedevs() # remove other devices - removedrivers() # remove drivers - time.sleep(1) - adddrivers() - adddevs() - - -def i2c_check(bus,retrytime = 6): - try: - i2cpath = "/sys/bus/i2c/devices/" + bus - while retrytime and not os.path.exists(i2cpath): - click.echo("%%DEVICE_I2C-HA: i2c bus abnormal, last bus %s is not exist." % i2cpath) - reload_driver() - retrytime -= 1 - time.sleep(1) - except Exception as e: - click.echo("%%DEVICE_I2C-HA: %s" % str(e)) - return - -def set_mac_leds(data): - '''write pci register''' - pcibus = MAC_LED_RESET.get("pcibus") - slot = MAC_LED_RESET.get("slot") - fn = MAC_LED_RESET.get("fn") - bar = MAC_LED_RESET.get("bar") - offset = MAC_LED_RESET.get("offset") - val = MAC_LED_RESET.get(data, None) - if val is None: - click.echo("%%DEVICE_I2C-INIT: set_mac_leds wrong input") - return - rgpciwr(pcibus, slot, fn, bar, offset, val) - -def load_driver(): - u'''load devices and drivers''' - adddrivers() - adddevs() - if STARTMODULE.get("i2ccheck",0) == 1: #i2c HA - busend = i2ccheck_params.get("busend") - retrytime = i2ccheck_params.get("retrytime") - i2c_check(busend,retrytime) - start_fan_ctrl() # enable fan - starthal_fanctrl() # enable fan control - starthal_ledctrl() # enable LED control - if STARTMODULE['avscontrol'] == 1: - start_avs_ctrl() # avs voltage-adjustment - start_slot_monitor() # slot insertion and removal initialization monitor - otherinit(); # other initialization, QSFP initialization - if STARTMODULE.get("macledreset", 0) == 1: - set_mac_leds("reset") - -@click.group(cls=AliasedGroup, context_settings=CONTEXT_SETTINGS) -def main(): - '''device operator''' - pass - - -@main.command() -def start(): - '''load device ''' - if check_driver(): - unload_driver() - load_driver() - -@main.command() -def stop(): - '''stop device ''' - unload_driver() - -@main.command() -def restart(): - '''restart device''' - unload_driver() - load_driver() - -if __name__ == '__main__': - u'''device_i2c operation''' - main() diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/script/fancontrol.py b/platform/broadcom/sonic-platform-modules-ragile/common/script/fancontrol.py deleted file mode 100755 index f93e06aa865e..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/common/script/fancontrol.py +++ /dev/null @@ -1,994 +0,0 @@ -#!/usr/bin/env python3 -# -*- coding: UTF-8 -*- -import click -import os -import time -import traceback -import glob -import subprocess -from rgutil.logutil import Logger -from ragileutil import wait_docker - -from ragileconfig import ( - MONITOR_CONST, - FANCTROLDEBUG, - MONITOR_FANS_LED, - DEV_LEDS, - MONITOR_PSU_STATUS, - MONITOR_SYS_PSU_LED, - MONITOR_DEV_STATUS, - MONITOR_FAN_STATUS, - MONITOR_DEV_STATUS_DECODE, - MONITOR_SYS_FAN_LED, - MONITOR_SYS_LED, - fanloc, -) - -from ragileutil import ( - rgi2cget, - get_mac_temp_sysfs, - get_mac_temp, - write_sysfs_value, - get_sysfs_value, - strtoint, - rgi2cset, - io_rd, - rgsysset, -) - - -CONTEXT_SETTINGS = dict(help_option_names=["-h", "--help"]) - -DEBUG_COMMON = 0x01 -DEBUG_LEDCONTROL = 0x02 -DEBUG_FANCONTROL = 0x04 - -LOG_PREFIX = "FANCONTROL" -logger = Logger(LOG_PREFIX, syslog=True, dbg_mask=FANCTROLDEBUG) - - -class AliasedGroup(click.Group): - def get_command(self, ctx, cmd_name): - rv = click.Group.get_command(self, ctx, cmd_name) - if rv is not None: - return rv - matches = [x for x in self.list_commands(ctx) if x.startswith(cmd_name)] - if not matches: - return None - elif len(matches) == 1: - return click.Group.get_command(self, ctx, matches[0]) - ctx.fail("Too many matches: %s" % ", ".join(sorted(matches))) - - -class FanControl(object): - critnum = 0 - - def __init__(self): - self._normal_fans = 0 - self._normal_psus = 0 - self._intemp = -100.0 - self._mac_aver = -100.0 - self._mac_max = -100.0 - # previous temperature - self._pre_intemp = -100 - self._outtemp = -100 - self._boardtemp = -100 - self._cputemp = -1000 - - @property - def normal_fans(self): - return self._normal_fans - - @property - def normal_psus(self): - return self._normal_psus - - @property - def cputemp(self): - return self._cputemp - - @property - def intemp(self): - return self._intemp - - @property - def outtemp(self): - return self._outtemp - - @property - def boardtemp(self): - return self._boardtemp - - @property - def mac_aver(self): - return self._mac_aver - - @property - def preIntemp(self): - return self._pre_intemp - - @property - def mac_max(self): - return self._mac_max - - def sortCallback(self, element): - return element["id"] - - def gettemp(self, ret): - u"""get inlet, outlet, hot-point and cpu temperature""" - temp_conf = MONITOR_DEV_STATUS.get("temperature", None) - - if temp_conf is None: - logger.error("gettemp: config error") - return False - for item_temp in temp_conf: - try: - retval = "" - rval = None - name = item_temp.get("name") - location = item_temp.get("location") - if name == "cpu": - L = [] - for dirpath, dirnames, filenames in os.walk(location): - for file in filenames: - if file.endswith("input"): - L.append(os.path.join(dirpath, file)) - L = sorted(L, reverse=False) - for i in range(len(L)): - nameloc = "%s/temp%d_label" % (location, i + 1) - valloc = "%s/temp%d_input" % (location, i + 1) - with open(nameloc, "r") as fd1: - retval2 = fd1.read() - with open(valloc, "r") as fd2: - retval3 = fd2.read() - ret_t = {} - ret_t["name"] = retval2.strip() - ret_t["value"] = float(retval3) / 1000 - ret.append(ret_t) - logger.debug( - DEBUG_COMMON, - "gettemp %s : %f" % (ret_t["name"], ret_t["value"]), - ) - else: - locations = glob.glob(location) - with open(locations[0], "r") as fd1: - retval = fd1.read() - rval = float(retval) / 1000 - ret_t = {} - ret_t["name"] = name - ret_t["value"] = rval - ret.append(ret_t) - logger.debug( - DEBUG_COMMON, - "gettemp %s : %f" % (ret_t["name"], ret_t["value"]), - ) - except Exception as e: - logger.error("gettemp error:name:%s" % name) - logger.error(str(e)) - return True - - def checkslot(self, ret): - u"""get slot present status""" - slots_conf = MONITOR_DEV_STATUS.get("slots", None) - slotpresent = MONITOR_DEV_STATUS_DECODE.get("slotpresent", None) - - if slots_conf is None or slotpresent is None: - return False - for item_slot in slots_conf: - totalerr = 0 - try: - ret_t = {} - ret_t["id"] = item_slot.get("name") - ret_t["status"] = "" - gettype = item_slot.get("gettype") - presentbit = item_slot.get("presentbit") - if gettype == "io": - io_addr = item_slot.get("io_addr") - val = io_rd(io_addr) - if val is not None: - retval = val - else: - totalerr -= 1 - logger.error( - " %s %s" % (item_slot.get("name"), "lpc read failed"), - ) - else: - bus = item_slot.get("bus") - loc = item_slot.get("loc") - offset = item_slot.get("offset") - ind, val = rgi2cget(bus, loc, offset) - if ind is True: - retval = val - else: - totalerr -= 1 - logger.error( - " %s %s" % (item_slot.get("name"), "i2c read failed"), - ) - if totalerr < 0: - ret_t["status"] = "NOT OK" - ret.append(ret_t) - continue - val_t = (int(retval, 16) & (1 << presentbit)) >> presentbit - logger.debug( - DEBUG_COMMON, - "%s present:%s" % (item_slot.get("name"), slotpresent.get(val_t)), - ) - if val_t != slotpresent.get("okval"): - ret_t["status"] = "ABSENT" - else: - ret_t["status"] = "PRESENT" - except Exception as e: - ret_t["status"] = "NOT OK" - totalerr -= 1 - logger.error("checkslot error") - logger.error(str(e)) - ret.append(ret_t) - return True - - def checkpsu(self, ret): - u"""get psu status present, output and warning""" - psus_conf = MONITOR_DEV_STATUS.get("psus", None) - psupresent = MONITOR_DEV_STATUS_DECODE.get("psupresent", None) - psuoutput = MONITOR_DEV_STATUS_DECODE.get("psuoutput", None) - psualert = MONITOR_DEV_STATUS_DECODE.get("psualert", None) - - if psus_conf is None or psupresent is None or psuoutput is None: - logger.error("checkpsu: config error") - return False - for item_psu in psus_conf: - totalerr = 0 - try: - ret_t = {} - ret_t["id"] = item_psu.get("name") - ret_t["status"] = "" - gettype = item_psu.get("gettype") - presentbit = item_psu.get("presentbit") - statusbit = item_psu.get("statusbit") - alertbit = item_psu.get("alertbit") - if gettype == "io": - io_addr = item_psu.get("io_addr") - val = io_rd(io_addr) - if val is not None: - retval = val - else: - totalerr -= 1 - logger.error( - " %s %s" % (item_psu.get("name"), "lpc read failed"), - ) - else: - bus = item_psu.get("bus") - loc = item_psu.get("loc") - offset = item_psu.get("offset") - ind, val = rgi2cget(bus, loc, offset) - if ind is True: - retval = val - else: - totalerr -= 1 - logger.error( - " %s %s" % (item_psu.get("name"), "i2c read failed"), - ) - if totalerr < 0: - ret_t["status"] = "NOT OK" - ret.append(ret_t) - continue - val_t = (int(retval, 16) & (1 << presentbit)) >> presentbit - val_status = (int(retval, 16) & (1 << statusbit)) >> statusbit - val_alert = (int(retval, 16) & (1 << alertbit)) >> alertbit - logger.debug( - DEBUG_COMMON, - "%s present:%s output:%s alert:%s" - % ( - item_psu.get("name"), - psupresent.get(val_t), - psuoutput.get(val_status), - psualert.get(val_alert), - ), - ) - if ( - val_t != psupresent.get("okval") - or val_status != psuoutput.get("okval") - or val_alert != psualert.get("okval") - ): - totalerr -= 1 - except Exception as e: - totalerr -= 1 - logger.error("checkpsu error") - logger.error(str(e)) - if totalerr < 0: - ret_t["status"] = "NOT OK" - else: - ret_t["status"] = "OK" - ret.append(ret_t) - return True - - def checkfan(self, ret): - u"""get fan status present and roll""" - fans_conf = MONITOR_DEV_STATUS.get("fans", None) - fanpresent = MONITOR_DEV_STATUS_DECODE.get("fanpresent", None) - fanroll = MONITOR_DEV_STATUS_DECODE.get("fanroll", None) - - if fans_conf is None or fanpresent is None or fanroll is None: - logger.error("checkfan: config error") - return False - for item_fan in fans_conf: - totalerr = 0 - try: - ret_t = {} - ret_t["id"] = item_fan.get("name") - ret_t["status"] = "" - presentstatus = item_fan.get("presentstatus") - presentbus = presentstatus.get("bus") - presentloc = presentstatus.get("loc") - presentaddr = presentstatus.get("offset") - presentbit = presentstatus.get("bit") - ind, val = rgi2cget(presentbus, presentloc, presentaddr) - if ind is True: - val_t = (int(val, 16) & (1 << presentbit)) >> presentbit - logger.debug( - DEBUG_COMMON, - "checkfan:%s present status:%s" - % (item_fan.get("name"), fanpresent.get(val_t)), - ) - if val_t != fanpresent.get("okval"): - ret_t["status"] = "ABSENT" - ret.append(ret_t) - continue - else: - logger.error( - "checkfan: %s get present status error." % item_fan.get("name"), - ) - motors = item_fan.get("rollstatus") - for motor in motors: - statusbus = motor.get("bus", None) - statusloc = motor.get("loc", None) - statusaddr = motor.get("offset", None) - statusbit = motor.get("bit", None) - ind, val = rgi2cget(statusbus, statusloc, statusaddr) - if ind is True: - val_t = (int(val, 16) & (1 << statusbit)) >> statusbit - logger.debug( - DEBUG_COMMON, - "checkfan:%s roll status:%s" - % (motor.get("name"), fanroll.get(val_t)), - ) - if val_t != fanroll.get("okval"): - totalerr -= 1 - else: - totalerr -= 1 - logger.error("checkfan: %s " % item_fan.get("name")) - logger.error("get %s status error." % motor["name"]) - except Exception as e: - totalerr -= 1 - logger.error("checkfan error") - logger.error(str(e)) - if totalerr < 0: - ret_t["status"] = "NOT OK" - else: - ret_t["status"] = "OK" - ret.append(ret_t) - return True - - def get_curr_speed(self): - try: - loc = fanloc[0].get("location", "") - sped = get_sysfs_value(loc) - value = strtoint(sped) - return value - except Exception as e: - logger.error("%%policy: get current speedlevel error") - logger.error(str(e)) - return None - - # guarantee the speed is lowest when speed lower than lowest value after speed-adjustment - def check_curr_speed(self): - logger.debug( - DEBUG_FANCONTROL, - "%%policy: guarantee the lowest speed after speed-adjustment", - ) - value = self.get_curr_speed() - if value is None or value == 0: - raise Exception("%%policy: get_curr_speed None") - elif value < MONITOR_CONST.MIN_SPEED: - self.set_fan_speed(MONITOR_CONST.MIN_SPEED) - - def set_fan_speed(self, level): - if level >= MONITOR_CONST.MAX_SPEED: - level = MONITOR_CONST.MAX_SPEED - for item in fanloc: - try: - loc = item.get("location", "") - # write_sysfs_value(loc, "0x%02x" % level) - # pddf support dicimal number - write_sysfs_value(loc, "%d" % level) - except Exception as e: - logger.error(str(e)) - logger.error("%%policy: config fan runlevel error") - self.check_curr_speed() # guaranteed minimum - - def set_fan_max_speed(self): - try: - self.set_fan_speed(MONITOR_CONST.MAX_SPEED) - except Exception as e: - logger.error("%%policy:set_fan_max_speed failed") - logger.error(str(e)) - - def detect_fan_status(self): - """ - fan status check , max speed if fan error - """ - if self.normal_fans < MONITOR_CONST.FAN_TOTAL_NUM: - logger.warn( - "%%DEV_MONITOR-FAN: Normal fan number: %d" % (self.normal_fans), - ) - self.set_fan_max_speed() - return False - return True - - def set_fan_attr(self, val): - u"""set status of each fan""" - for item in val: - fanid = item.get("id") - fanattr = fanid + "status" - fanstatus = item.get("status") - setattr(FanControl, fanattr, fanstatus) - logger.debug( - DEBUG_COMMON, "fanattr:%s,fanstatus:%s" % (fanattr, fanstatus), - ) - - def fan_present_num(self, cur_fan_status): - fanoknum = 0 - for item in cur_fan_status: - if item["status"] == "OK": - fanoknum += 1 - self._normal_fans = fanoknum - logger.debug(DEBUG_COMMON, "normal_fans = %d" % self._normal_fans) - - def get_fan_status(self): - try: - cur_fan_status = [] - ret = self.checkfan(cur_fan_status) - if ret is True: - self.set_fan_attr(cur_fan_status) - self.fan_present_num(cur_fan_status) - logger.debug(DEBUG_COMMON, "%%policy:get_fan_status success") - return 0 - except AttributeError as e: - logger.error(str(e)) - except Exception as e: - logger.error(str(e)) - return -1 - - def normal_psu_num(self, curPsuStatus): - psuoknum = 0 - for item in curPsuStatus: - if item.get("status") == "OK": - psuoknum += 1 - self._normal_psus = psuoknum - logger.debug(DEBUG_COMMON, "normal_psus = %d" % self._normal_psus) - - def get_psu_status(self): - try: - curPsuStatus = [] - ret = self.checkpsu(curPsuStatus) - if ret is True: - self.normal_psu_num(curPsuStatus) - logger.debug(DEBUG_COMMON, "%%policy:get_psu_status success") - return 0 - except AttributeError as e: - logger.error(str(e)) - except Exception as e: - logger.error(str(e)) - return -1 - - def get_monitor_temp(self, temp): - for item in temp: - if item.get("name") == "lm75in": - self._intemp = item.get("value", self._intemp) - if item.get("name") == "lm75out": - self._outtemp = item.get("value", self._outtemp) - if item.get("name") == "lm75hot": - self._boardtemp = item.get("value", self._boardtemp) - if item.get("name") == "Physical id 0": - self._cputemp = item.get("value", self._cputemp) - logger.debug( - DEBUG_COMMON, - "intemp:%f, outtemp:%f, boadrtemp:%f, cputemp:%f" - % (self._intemp, self._outtemp, self._boardtemp, self._cputemp), - ) - - def get_temp_status(self): - try: - monitortemp = [] - ret = self.gettemp(monitortemp) - if ret is True: - self.get_monitor_temp(monitortemp) - logger.debug(DEBUG_COMMON, "%%policy:get_temp_status success") - return 0 - except AttributeError as e: - logger.error(str(e)) - except Exception as e: - logger.error(str(e)) - return -1 - - def get_mac_status_bcmcmd(self): - try: - if wait_docker(timeout=0) is True: - sta, ret = get_mac_temp() - if sta is True: - self._mac_aver = float(ret.get("average", self._mac_aver)) - self._mac_max = float(ret.get("maximum", self._mac_max)) - logger.debug( - DEBUG_COMMON, - "mac_aver:%f, mac_max:%f" % (self.mac_aver, self._mac_max), - ) - else: - logger.debug(DEBUG_COMMON, "%%policy:get_mac_status_bcmcmd failed") - else: - logger.debug(DEBUG_COMMON, "%%policy:get_mac_status_bcmcmd SDK not OK") - return 0 - except AttributeError as e: - logger.error(str(e)) - return -1 - - def get_mac_status_sysfs(self, conf): - try: - sta, ret = get_mac_temp_sysfs(conf) - if sta is True: - self._mac_aver = float(ret) / 1000 - self._mac_max = float(ret) / 1000 - logger.debug( - DEBUG_COMMON, - "mac_aver:%f, mac_max:%f" % (self.mac_aver, self._mac_max), - ) - elif conf.get("try_bcmcmd", 0) == 1: - logger.debug( - DEBUG_COMMON, "get sysfs mac temp failed.try to use bcmcmd", - ) - self.get_mac_status_bcmcmd() - else: - logger.debug(DEBUG_COMMON, "%%policy:get_mac_status_sysfs failed") - return 0 - except AttributeError as e: - logger.error(str(e)) - return -1 - - def get_mac_status(self): - try: - mactempconf = MONITOR_DEV_STATUS.get("mac_temp", None) - if mactempconf is not None: - self.get_mac_status_sysfs(mactempconf) - else: - self.get_mac_status_bcmcmd() - return 0 - except AttributeError as e: - logger.error(str(e)) - return -1 - - def set_slot_attr(self, val): - u"""set each slot present status attribute""" - for item in val: - slotid = item.get("id") - slotattr = slotid + "status" - slotstatus = item.get("status") - setattr(FanControl, slotattr, slotstatus) - logger.debug( - DEBUG_COMMON, "slotattr:%s,slotstatus:%s" % (slotattr, slotstatus), - ) - - def get_slot_status(self): - try: - curSlotStatus = [] - ret = self.checkslot(curSlotStatus) - if ret is True: - self.set_slot_attr(curSlotStatus) - logger.debug(DEBUG_COMMON, "%%policy:get_slot_status success") - except AttributeError as e: - logger.error(str(e)) - return 0 - - def fanctrol(self): # fan speed-adjustment - try: - if self.preIntemp <= -1000: - self.preIntemp = self.intemp - logger.debug( - DEBUG_FANCONTROL, - "%%policy:previous temperature[%.2f] , current temperature[%.2f]" - % (self.preIntemp, self.intemp), - ) - if self.intemp < MONITOR_CONST.TEMP_MIN: - logger.debug( - DEBUG_FANCONTROL, - "%%policy:inlet %.2f minimum temperature: %.2f" - % (self.intemp, MONITOR_CONST.TEMP_MIN), - ) - self.set_fan_speed(MONITOR_CONST.DEFAULT_SPEED) # default level - elif self.intemp >= MONITOR_CONST.TEMP_MIN and self.intemp > self.preIntemp: - logger.debug(DEBUG_FANCONTROL, "%%policy:increase temperature") - self.policy_speed(self.intemp) - elif ( - self.intemp >= MONITOR_CONST.TEMP_MIN - and (self.preIntemp - self.intemp) > MONITOR_CONST.MONITOR_FALL_TEMP - ): - logger.debug( - DEBUG_FANCONTROL, - "%%policy:temperature reduce over %d degree" - % MONITOR_CONST.MONITOR_FALL_TEMP, - ) - self.policy_speed(self.intemp) - else: - speed = ( - self.get_curr_speed() - ) # set according to current speed, prevent fan watch-dog - if speed is not None: - self.set_fan_speed(speed) - logger.debug(DEBUG_FANCONTROL, "%%policy:change nothing") - except Exception as e: - logger.error("%%policy: fancontrol error") - - def start_fan_ctrl(self): - """ - start speed-adjustment - """ - self.check_crit() - if ( - self.critnum == 0 - and self.check_warn() is False - and self.detect_fan_status() is True - ): - self.fanctrol() - self.check_dev_err() - logger.debug( - DEBUG_FANCONTROL, - "%%policy: speed after speed-adjustment is %0x" % (self.get_curr_speed()), - ) - - def policy_speed(self, temp): # fan speed-adjustment algorithm - logger.debug(DEBUG_FANCONTROL, "%%policy:fan speed-adjustment algorithm") - sped_level = MONITOR_CONST.DEFAULT_SPEED + MONITOR_CONST.K * ( - temp - MONITOR_CONST.TEMP_MIN - ) - self.set_fan_speed(sped_level) - self.preIntemp = self.intemp - - def board_moni_msg(self, ledcontrol=False): - ret_t = 0 - try: - ret_t += ( - self.get_fan_status() - ) # get fan status, get number of fan which status is OK - ret_t += ( - self.get_temp_status() - ) # get inlet, outlet, hot-point temperature, CPU temperature - ret_t += self.get_mac_status() # get MAC highest and average temperature - if ledcontrol == True: - ret_t += self.get_slot_status() # get slot present status - ret_t += self.get_psu_status() # get psu status - if ret_t == 0: - return True - except Exception as e: - logger.error(str(e)) - return False - - # device error algorithm Tmac-Tin≥50℃, or Tmac-Tin≤-50℃ - def check_dev_err(self): - try: - if (self.mac_aver - self.intemp) >= MONITOR_CONST.MAC_UP_TEMP or ( - self.mac_aver - self.intemp - ) <= MONITOR_CONST.MAC_LOWER_TEMP: - logger.debug( - DEBUG_FANCONTROL, "%%DEV_MONITOR-TEMP: MAC temp get failed.", - ) - value = self.get_curr_speed() - if MONITOR_CONST.MAC_ERROR_SPEED >= value: - self.set_fan_speed(MONITOR_CONST.MAC_ERROR_SPEED) - else: - self.set_fan_max_speed() - else: - pass - except Exception as e: - logger.error("%%policy:check_dev_err failed") - logger.error(str(e)) - - def check_temp_warn(self): - u"""check whether temperature above the normal alarm value""" - try: - if ( - self._mac_aver >= MONITOR_CONST.MAC_WARNING_THRESHOLD - or self._outtemp >= MONITOR_CONST.OUTTEMP_WARNING_THRESHOLD - or self._boardtemp >= MONITOR_CONST.BOARDTEMP_WARNING_THRESHOLD - or self._cputemp >= MONITOR_CONST.CPUTEMP_WARNING_THRESHOLD - or self._intemp >= MONITOR_CONST.INTEMP_WARNING_THRESHOLD - ): - logger.debug( - DEBUG_COMMON, - "check whether temperature above the normal alarm value", - ) - return True - except Exception as e: - logger.error("%%policy: check_temp_warn failed") - logger.error(str(e)) - return False - - def check_temp_crit(self): - u"""check whether temperature above the critical alarm value""" - try: - if self._mac_aver >= MONITOR_CONST.MAC_CRITICAL_THRESHOLD or ( - self._outtemp >= MONITOR_CONST.OUTTEMP_CRITICAL_THRESHOLD - and self._boardtemp >= MONITOR_CONST.BOARDTEMP_CRITICAL_THRESHOLD - and self._cputemp >= MONITOR_CONST.CPUTEMP_CRITICAL_THRESHOLD - and self._intemp >= MONITOR_CONST.INTEMP_CRITICAL_THRESHOLD - ): - logger.debug( - DEBUG_COMMON, "temperature above the critical alarm value", - ) - return True - except Exception as e: - logger.error("%%policy: check_temp_crit failed") - logger.error(str(e)) - return False - - def check_fan_status(self): - u"""check fan status""" - for item in MONITOR_FAN_STATUS: - maxoknum = item.get("maxOkNum") - minoknum = item.get("minOkNum") - status = item.get("status") - if self.normal_fans >= minoknum and self.normal_fans <= maxoknum: - logger.debug( - DEBUG_COMMON, - "check_fan_status:normal_fans:%d,status:%s" - % (self.normal_fans, status), - ) - return status - logger.debug( - DEBUG_COMMON, "check_fan_status Error:normal_fans:%d" % (self.normal_fans), - ) - return None - - def check_psu_status(self): - u"""check psu status""" - for item in MONITOR_PSU_STATUS: - maxoknum = item.get("maxOkNum") - minoknum = item.get("minOkNum") - status = item.get("status") - if self.normal_psus >= minoknum and self.normal_psus <= maxoknum: - logger.debug( - DEBUG_COMMON, - "check_psu_status:normal_psus:%d,status:%s" - % (self.normal_psus, status), - ) - return status - logger.debug( - DEBUG_COMMON, "check_psu_status Error:normal_psus:%d" % (self.normal_psus), - ) - return None - - def deal_sys_led_status(self): - u"""set up SYSLED according to temperature, fan and psu status""" - try: - fanstatus = self.check_fan_status() - psustatus = self.check_psu_status() - if ( - self.check_temp_crit() is True - or fanstatus == "red" - or psustatus == "red" - ): - status = "red" - elif ( - self.check_temp_warn() is True - or fanstatus == "yellow" - or psustatus == "yellow" - ): - status = "yellow" - else: - status = "green" - self.set_sys_leds(status) - logger.debug( - DEBUG_LEDCONTROL, - "%%ledcontrol:deal_sys_led_status success, status:%s," % status, - ) - except Exception as e: - logger.error(str(e)) - - def deal_sys_fan_led_status(self): - u"""light panel fan led according to status""" - try: - status = self.check_fan_status() - if status is not None: - self.set_sys_fan_leds(status) - logger.debug( - DEBUG_LEDCONTROL, - "%%ledcontrol:deal_sys_fan_led_status success, status:%s," % status, - ) - except Exception as e: - logger.error("%%ledcontrol:deal_sys_led_status error") - logger.error(str(e)) - - def deal_psu_led_status(self): - u"""set up PSU-LED according to psu status""" - try: - status = self.check_psu_status() - if status is not None: - self.set_sys_psu_leds(status) - logger.debug( - DEBUG_LEDCONTROL, - "%%ledcontrol:deal_psu_led_status success, status:%s," % status, - ) - except Exception as e: - logger.error("%%ledcontrol:deal_psu_led_status error") - logger.error(str(e)) - - def deal_fan_led_status(self): - u"""light fan led according to fan status""" - for item in MONITOR_FANS_LED: - try: - index = MONITOR_FANS_LED.index(item) + 1 - fanattr = "fan%dstatus" % index - val_t = getattr(FanControl, fanattr, None) - if val_t == "NOT OK": - rgi2cset(item["bus"], item["devno"], item["addr"], item["red"]) - elif val_t == "OK": - rgi2cset(item["bus"], item["devno"], item["addr"], item["green"]) - else: - pass - logger.debug( - DEBUG_LEDCONTROL, - "%%ledcontrol:dealLocFanLed success.fanattr:%s, status:%s" - % (fanattr, val_t), - ) - except Exception as e: - logger.error("%%ledcontrol:deal_fan_led_status error") - logger.error(str(e)) - - def dealSlotLedStatus(self): - u"""light slot status led according to slot present status""" - slotLedList = DEV_LEDS.get("SLOTLED", []) - for item in slotLedList: - try: - index = slotLedList.index(item) + 1 - slotattr = "slot%dstatus" % index - val_t = getattr(FanControl, slotattr, None) - if val_t == "PRESENT": - rgi2cset(item["bus"], item["devno"], item["addr"], item["green"]) - logger.debug( - DEBUG_LEDCONTROL, - "%%ledcontrol:dealSlotLedStatus success.slotattr:%s, status:%s" - % (slotattr, val_t), - ) - except Exception as e: - logger.error("%%ledcontrol:dealSlotLedStatus error") - logger.error(str(e)) - - def setled(self, item, color): - if item.get("type", "i2c") == "sysfs": - rgsysset(item["cmdstr"], item.get(color)) - else: - mask = item.get("mask", 0xFF) - ind, val = rgi2cget(item["bus"], item["devno"], item["addr"]) - if ind is True: - setval = (int(val, 16) & ~mask) | item.get(color) - rgi2cset(item["bus"], item["devno"], item["addr"], setval) - else: - logger.error("led %s" % "i2c read failed") - - def set_sys_leds(self, color): - for item in MONITOR_SYS_LED: - self.setled(item, color) - - def set_sys_fan_leds(self, color): - for item in MONITOR_SYS_FAN_LED: - self.setled(item, color) - - def set_sys_psu_leds(self, color): - for item in MONITOR_SYS_PSU_LED: - self.setled(item, color) - - def check_warn(self): - try: - if self.check_temp_warn() is True: - logger.debug(DEBUG_FANCONTROL, "anti-shake start") - time.sleep(MONITOR_CONST.SHAKE_TIME) - logger.debug(DEBUG_FANCONTROL, "anti-shake end") - self.board_moni_msg() # re-read - if self.check_temp_warn() is True: - logger.warn("%%DEV_MONITOR-TEMP:The temperature of device is over warning value.") - self.set_fan_max_speed() # fan full speed - return True - except Exception as e: - logger.error("%%policy: check_warn failed") - logger.error(str(e)) - return False - - def check_crit(self): - try: - if self.check_temp_crit() is True: - logger.debug(DEBUG_FANCONTROL, "anti-shake start") - time.sleep(MONITOR_CONST.SHAKE_TIME) - logger.debug(DEBUG_FANCONTROL, "anti-shake end") - self.board_moni_msg() # re-read - if self.check_temp_crit() is True: - logger.crit( - "%%DEV_MONITOR-TEMP:The temperature of device is over critical value.", - ) - self.set_fan_max_speed() # fan full speed - self.critnum += 1 # anti-shake - if self.critnum >= MONITOR_CONST.CRITICAL_NUM: - subprocess.call(["reboot"]) - logger.debug(DEBUG_FANCONTROL, "crit times:%d" % self.critnum) - else: - self.critnum = 0 - else: - self.critnum = 0 - except Exception as e: - logger.error("%%policy: check_crit failed") - logger.error(str(e)) - - -def callback(): - pass - - -def do_fan_ctrl(fanctrl): - ret = fanctrl.board_moni_msg() - if ret is True: - logger.debug(DEBUG_FANCONTROL, "%%policy:start_fan_ctrl") - fanctrl.start_fan_ctrl() - else: - fanctrl.set_fan_max_speed() - logger.debug(DEBUG_FANCONTROL, "%%policy:board_moni_msg error") - - -def do_led_ctrl(fanctrl): - fanctrl.board_moni_msg(ledcontrol=True) # get status - fanctrl.deal_sys_led_status() # light system led - fanctrl.deal_sys_fan_led_status() # light panel fan led - fanctrl.deal_fan_led_status() # light fan led - fanctrl.deal_psu_led_status() # light psu led - fanctrl.dealSlotLedStatus() # light slot status led - logger.debug(DEBUG_LEDCONTROL, "%%ledcontrol:do_led_ctrl success") - - -def run(interval, fanctrl): - loop = 0 - # waitForDocker() - while True: - try: - if loop % MONITOR_CONST.MONITOR_INTERVAL == 0: # fan speed-adjustment - logger.debug(DEBUG_FANCONTROL, "%%policy:fanctrl") - do_fan_ctrl(fanctrl) - else: - logger.debug( - DEBUG_LEDCONTROL, "%%ledcontrol:start ledctrol" - ) # LED control - do_led_ctrl(fanctrl) - time.sleep(interval) - loop += interval - except Exception as e: - traceback.print_exc() - logger.error(str(e)) - - -@click.group(cls=AliasedGroup, context_settings=CONTEXT_SETTINGS) -def main(): - """device operator""" - pass - - -@main.command() -def start(): - """start fan control""" - logger.info("FAN CTRL START") - fanctrl = FanControl() - interval = MONITOR_CONST.MONITOR_INTERVAL / 30 - run(interval, fanctrl) - - -@main.command() -def stop(): - """stop fan control """ - logger.info("FAN CTRL STOP") - - -##device_i2c operation -if __name__ == "__main__": - main() diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/script/generate_airflow.py b/platform/broadcom/sonic-platform-modules-ragile/common/script/generate_airflow.py new file mode 100755 index 000000000000..29d18e7b2688 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/script/generate_airflow.py @@ -0,0 +1,236 @@ +#!/usr/bin/env python +# -*- coding: UTF-8 -*- +''' +generate board air flow according to fan and psu air flow +write resulet to AIRFLOW_RESULT_FILE, file format: +{ + "FAN1": { + "model":"M1HFAN I-F", + "airflow":"intake", + }, + "PSU1": { + "model":"CSU550AP-3-500", + "airflow":"intake", + }, + "board":"intake" +} +''' +import os +import syslog +import json +from platform_config import AIR_FLOW_CONF, AIRFLOW_RESULT_FILE +from platform_util import dev_file_read, byteTostr +from eepromutil.fru import ipmifru +from eepromutil.fantlv import fan_tlv + + +AIRFLOW_DEBUG_FILE = "/etc/.airflow_debug_flag" + +AIRFLOWERROR = 1 +AIRFLOWDEBUG = 2 + +debuglevel = 0 + + +def airflow_info(s): + syslog.openlog("AIRFLOW", syslog.LOG_PID) + syslog.syslog(syslog.LOG_INFO, s) + + +def airflow_error(s): + syslog.openlog("AIRFLOW", syslog.LOG_PID) + syslog.syslog(syslog.LOG_ERR, s) + + +def airflow_debug(s): + if AIRFLOWDEBUG & debuglevel: + syslog.openlog("AIRFLOW", syslog.LOG_PID) + syslog.syslog(syslog.LOG_DEBUG, s) + + +def airflow_debug_error(s): + if AIRFLOWERROR & debuglevel: + syslog.openlog("AIRFLOW", syslog.LOG_PID) + syslog.syslog(syslog.LOG_ERR, s) + + +def debug_init(): + global debuglevel + try: + with open(AIRFLOW_DEBUG_FILE, "r") as fd: + value = fd.read() + debuglevel = int(value) + except Exception: + debuglevel = 0 + + +def get_model_fru(device, eeprom): + try: + fru = ipmifru() + fru.decodeBin(eeprom) + dev_name = device.get("name") + area = device.get("area") + field = device.get("field") + tmp_area = getattr(fru, area, None) + if tmp_area is None: + msg = "%s fru %s area config error" % (dev_name, area) + return False, msg + model = getattr(tmp_area, field, None) + if model is None: + msg = "%s get model error, area: %s, field: %s" % (dev_name, area, field) + return False, msg + airflow_debug("%s get model success, model: %s" % (dev_name, model)) + return True, model + except Exception as e: + return False, str(e) + + +def get_model_fantlv(device, eeprom): + try: + dev_name = device.get("name") + tlv = fan_tlv() + rets = tlv.decode(eeprom) + if len(rets) == 0: + msg = "%s decode fantlv eeprom info error" % dev_name + return False, msg + + field = device.get("field") + for fantlv_item in rets: + if fantlv_item.get("name") == field: + return True, fantlv_item["value"] + msg = "%s get model error, field: %s not found" % (dev_name, field) + return False, msg + except Exception as e: + return False, str(e) + + +def get_device_modele(device): + e2_type = device.get("e2_type") + dev_name = device.get("name") + support_e2_type = ("fru", "fantlv") + if e2_type not in support_e2_type: + msg = "%s unsupport e2_type: %s" % (dev_name, e2_type) + return False, msg + + e2_path = device.get("e2_path") + e2_size = device.get("e2_size", 256) + ret, binval_bytes = dev_file_read(e2_path, 0, e2_size) + if ret is False: + msg = "%s eeprom read error, eeprom path: %s, msg: %s" % (dev_name, e2_path, binval_bytes) + return False, msg + + binval = byteTostr(binval_bytes) + if e2_type == "fru": + return get_model_fru(device, binval) + return get_model_fantlv(device, binval) + + +def get_board_air_flow(fan_intake_num, fan_exhaust_num, psu_intake_num, psu_exhaust_num): + airflow_debug("fan_intake_num: %d, fan_exhaust_num: %d, psu_intake_num: %d, psu_exhaust_num: %d" % + (fan_intake_num, fan_exhaust_num, psu_intake_num, psu_exhaust_num)) + + if fan_intake_num == 0 and fan_exhaust_num == 0 and psu_intake_num == 0 and psu_exhaust_num == 0: + airflow_error("get all fans and psus air flow failed") + return "N/A" + + if fan_intake_num > fan_exhaust_num: + airflow_debug("fan intake number %d more than fan exhaust number %s, set board air flow: intake") + return "intake" + + if fan_intake_num < fan_exhaust_num: + airflow_debug("fan intake number less than fan exhaust number, set board air flow: exhaust") + return "exhaust" + + airflow_debug("fan intake number equal to exhaust number, check psu air flow") + + if psu_intake_num > psu_exhaust_num: + airflow_debug("psu intake number more than psu exhaust number, set board air flow: intake") + return "intake" + + if psu_intake_num < psu_exhaust_num: + airflow_debug("psu intake number less than psu exhaust number, set board air flow: exhaust") + return "exhaust" + + airflow_debug("fan and psu intake and exhaust number equal, return intake") + return "intake" + + +def generate_airflow(): + fan_intake_list = [] + fan_exhaust_list = [] + psu_intake_list = [] + psu_exhaust_list = [] + ret = {} + fans = AIR_FLOW_CONF.get("fans", []) + psus = AIR_FLOW_CONF.get("psus", []) + + for fan in fans: + dev_name = fan.get("name") + air_flow = "N/A" + status, model = get_device_modele(fan) + if status is False: + ret[dev_name] = {"model": "N/A", "airflow": "N/A"} + airflow_error(model) + continue + model = model.strip() + airflowconifg = AIR_FLOW_CONF[fan["decode"]] + for key, value in airflowconifg.items(): + if model in value: + air_flow = key + ret[dev_name] = {"model": model, "airflow": air_flow} + airflow_debug("%s model: %s, airflow: %s" % (dev_name, model, air_flow)) + if air_flow == "intake": + fan_intake_list.append(fan.get("name")) + elif air_flow == "exhaust": + fan_exhaust_list.append(fan.get("name")) + + airflow_debug("fan_intake_list: %s" % fan_intake_list) + airflow_debug("fan_exhaust_list: %s" % fan_exhaust_list) + + for psu in psus: + dev_name = psu.get("name") + air_flow = "N/A" + status, model = get_device_modele(psu) + if status is False: + ret[dev_name] = {"model": "N/A", "airflow": "N/A"} + airflow_error(model) + continue + model = model.strip() + airflowconifg = AIR_FLOW_CONF[psu["decode"]] + for key, value in airflowconifg.items(): + if model in value: + air_flow = key + ret[dev_name] = {"model": model, "airflow": air_flow} + airflow_debug("%s model: %s, airflow: %s" % (dev_name, model, air_flow)) + if air_flow == "intake": + psu_intake_list.append(psu.get("name")) + elif air_flow == "exhaust": + psu_exhaust_list.append(psu.get("name")) + + airflow_debug("psu_intake_list: %s" % psu_intake_list) + airflow_debug("psu_exhaust_list: %s" % psu_exhaust_list) + + fan_intake_num = len(fan_intake_list) + fan_exhaust_num = len(fan_exhaust_list) + psu_intake_num = len(psu_intake_list) + psu_exhaust_num = len(psu_exhaust_list) + + board_airflow = get_board_air_flow(fan_intake_num, fan_exhaust_num, psu_intake_num, psu_exhaust_num) + airflow_debug("board_airflow: %s" % board_airflow) + ret["board"] = board_airflow + ret_json = json.dumps(ret, ensure_ascii=False, indent=4) + + out_file_dir = os.path.dirname(AIRFLOW_RESULT_FILE) + if len(out_file_dir) != 0: + cmd = "mkdir -p %s" % out_file_dir + os.system(cmd) + os.system("sync") + with open(AIRFLOW_RESULT_FILE, "w") as fd: + fd.write(ret_json) + os.system("sync") + + +if __name__ == '__main__': + debug_init() + airflow_debug("enter main") + generate_airflow() diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/script/hal_fanctrl.py b/platform/broadcom/sonic-platform-modules-ragile/common/script/hal_fanctrl.py new file mode 100755 index 000000000000..7722b111f944 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/script/hal_fanctrl.py @@ -0,0 +1,1135 @@ +#!/usr/bin/env python3 +import os +import subprocess +import time +import syslog +import traceback +from plat_hal.interface import interface +from plat_hal.baseutil import baseutil +from algorithm.pid import pid +from algorithm.openloop import openloop +from algorithm.hysteresis import hysteresis + + +SWITCH_TEMP = "SWITCH_TEMP" +INLET_TEMP = "INLET_TEMP" +BOARD_TEMP = "BOARD_TEMP" +OUTLET_TEMP = "OUTLET_TEMP" +CPU_TEMP = "CPU_TEMP" + +FANCTROL_DEBUG_FILE = "/etc/.fancontrol_debug_flag" +# coordination with REBOOT_CAUSE_PARA +OTP_SWITCH_REBOOT_JUDGE_FILE = "/etc/.otp_reboot_flag" +OTP_OTHER_REBOOT_JUDGE_FILE = OTP_SWITCH_REBOOT_JUDGE_FILE + +FANCTROLERROR = 1 +FANCTROLDEBUG = 2 +FANAIRFLOWDEBUG = 4 + +debuglevel = 0 + +F2B_AIR_FLOW = "intake" +B2F_AIR_FLOW = "exhaust" +ONIE_E2_NAME = "ONIE_E2" + +TEMP_REBOOT_CRIT_SWITCH_FLAG = 1 +TEMP_REBOOT_CRIT_OTHER_FLAG = 2 + + +def fancontrol_debug(s): + if FANCTROLDEBUG & debuglevel: + syslog.openlog("FANCONTROL", syslog.LOG_PID) + syslog.syslog(syslog.LOG_DEBUG, s) + + +def fancontrol_error(s): + if FANCTROLERROR & debuglevel: + syslog.openlog("FANCONTROL", syslog.LOG_PID) + syslog.syslog(syslog.LOG_ERR, s) + + +def fanairflow_debug(s): + if FANAIRFLOWDEBUG & debuglevel: + syslog.openlog("AIR_FLOW_MONITOR", syslog.LOG_PID) + syslog.syslog(syslog.LOG_DEBUG, s) + + +def fancontrol_warn(s): + syslog.openlog("FANCONTROL", syslog.LOG_PID) + syslog.syslog(syslog.LOG_LOCAL1 | syslog.LOG_WARNING, s) + + +def fancontrol_crit(s): + syslog.openlog("FANCONTROL", syslog.LOG_PID) + syslog.syslog(syslog.LOG_LOCAL1 | syslog.LOG_CRIT, s) + + +def fancontrol_alert(s): + syslog.openlog("FANCONTROL", syslog.LOG_PID) + syslog.syslog(syslog.LOG_LOCAL1 | syslog.LOG_ALERT, s) + + +def fancontrol_emerg(s): + syslog.openlog("FANCONTROL", syslog.LOG_PID) + syslog.syslog(syslog.LOG_LOCAL1 | syslog.LOG_EMERG, s) + + +def exec_os_cmd(cmd): + status, output = subprocess.getstatusoutput(cmd) + if status: + print(output) + return status, output + + +def debug_init(): + global debuglevel + try: + with open(FANCTROL_DEBUG_FILE, "r") as fd: + value = fd.read() + debuglevel = int(value) + except Exception: + debuglevel = 0 + + +error_temp = -9999 # get temp error +invalid_temp = -10000 # get temp invalid +PRE_FAN_NOK_UNKNOWN = "UNKNOWN" + + +class DevFan(object): + + def __init__(self, name, hal_interface): + self.__name = name + self.origin_name = None + self.display_name = None + self.air_flow = None + self.air_flow_inconsistent = False + self.int_case = hal_interface + + @property + def name(self): + return self.__name + + def get_fan_rotor_number(self): + return self.int_case.get_fan_rotor_number(self.name) + + def get_fan_presence(self): + return self.int_case.get_fan_presence(self.name) + + def get_fan_rotor_status(self, rotor_name): + return self.int_case.get_fan_rotor_status(self.name, rotor_name) + + def get_fan_fru_info(self): + return self.int_case.get_fan_fru_info(self.name) + + @property + def na_ret(self): + return self.int_case.na_ret + + def update_fru_info(self): + try: + dic = self.get_fan_fru_info() + self.origin_name = dic["PN"] + self.air_flow = dic["AirFlow"] + self.display_name = dic["DisplayName"] + except Exception as e: + fanairflow_debug("update %s fru info error, msg: %s" % (self.name, str(e))) + self.origin_name = self.na_ret + self.air_flow = self.na_ret + self.display_name = self.na_ret + + +class DevPsu(object): + + def __init__(self, name, hal_interface): + self.__name = name + self.origin_name = None + self.display_name = None + self.air_flow = None + self.air_flow_inconsistent = False + self.int_case = hal_interface + + @property + def name(self): + return self.__name + + def get_psu_fru_info(self): + return self.int_case.get_psu_fru_info(self.name) + + @property + def na_ret(self): + return self.int_case.na_ret + + def update_fru_info(self): + try: + dic = self.get_psu_fru_info() + self.origin_name = dic["PN"] + self.air_flow = dic["AirFlow"] + self.display_name = dic["DisplayName"] + except Exception as e: + fanairflow_debug("update %s fru info error, msg: %s" % (self.name, str(e))) + self.origin_name = self.na_ret + self.air_flow = self.na_ret + self.display_name = self.na_ret + + +class fancontrol(object): + __int_case = None + + __pwm = 0x80 + + def __init__(self): + self.int_case = interface() + self.__config = baseutil.get_monitor_config() + self.__pid_config = self.__config["pid"] + self.__hyst_config = self.__config.get("hyst", {}) + self.__temps_threshold_config = self.__config["temps_threshold"] + for temp_threshold in self.__temps_threshold_config.values(): + temp_threshold['temp'] = 0 + temp_threshold['fail_num'] = 0 + temp_threshold['warning_num'] = 0 # temp warning times + temp_threshold['critical_num'] = 0 # temp critical times + temp_threshold['emergency_num'] = 0 # temp emergency times + temp_threshold.setdefault('ignore_threshold', 0) # default temp threshold on + temp_threshold.setdefault('invalid', invalid_temp) + temp_threshold.setdefault('error', error_temp) + + self.__otp_reboot_judge_file_config = self.__config.get("otp_reboot_judge_file", None) + if self.__otp_reboot_judge_file_config is None: + self.__otp_switch_reboot_judge_file = OTP_SWITCH_REBOOT_JUDGE_FILE + self.__otp_other_reboot_judge_file = OTP_OTHER_REBOOT_JUDGE_FILE + else: + self.__otp_switch_reboot_judge_file = self.__otp_reboot_judge_file_config.get( + "otp_switch_reboot_judge_file", OTP_SWITCH_REBOOT_JUDGE_FILE) + self.__otp_other_reboot_judge_file = self.__otp_reboot_judge_file_config.get( + "otp_other_reboot_judge_file", OTP_OTHER_REBOOT_JUDGE_FILE) + + self.__fan_rotor_error_num = {} + self.__fan_present_status = {} # {"FAN1":0, "FAN2":1...} 1:present, 0:absent + self.__fan_rotate_status = {} # {"FAN1":0, "FAN2":1...} 1:OK, 0:NOT OK + self.__fan_repair_flag = {} # {"FAN1":0, "FAN2":1...} 1:repair, 0:give up + fan_num = self.get_fan_total_number() + for i in range(fan_num): + fan_name = "FAN" + str(i + 1) + self.__fan_present_status[fan_name] = 1 # present + self.__fan_rotate_status[fan_name] = 1 # OK + self.__fan_repair_flag[fan_name] = 1 # repair + rotor_num = self.get_rotor_number(fan_name) + tmp_fan = {} + for j in range(rotor_num): + rotor_name = "Rotor" + str(j + 1) + tmp_fan[rotor_name] = 0 # not error + self.__fan_rotor_error_num[fan_name] = tmp_fan + + self.__fancontrol_para = self.__config["fancontrol_para"] + self.__interval = self.__fancontrol_para.get("interval", 5) + self.__fan_status_interval = self.__fancontrol_para.get("fan_status_interval", 0) + self.__max_pwm = self.__fancontrol_para.get("max_pwm", 0xff) + self.__min_pwm = self.__fancontrol_para.get("min_pwm", 0x80) + self.__abnormal_pwm = self.__fancontrol_para.get("abnormal_pwm", 0xbb) + self.__warning_pwm = self.__fancontrol_para.get("warning_pwm", 0xff) + self.__temp_invalid_pid_pwm = self.__fancontrol_para.get("temp_invalid_pid_pwm", 0x80) + self.__temp_error_pid_pwm = self.__fancontrol_para.get("temp_error_pid_pwm", 0x80) + self.__temp_fail_num = self.__fancontrol_para.get("temp_fail_num", 3) + self.__check_temp_fail = self.__fancontrol_para.get("check_temp_fail", []) + self.__temp_warning_num = self.__fancontrol_para.get("temp_warning_num", 3) + self.__temp_critical_num = self.__fancontrol_para.get("temp_critical_num", 3) + self.__temp_emergency_num = self.__fancontrol_para.get("temp_emergency_num", 3) + self.__temp_warning_countdown = self.__fancontrol_para.get("temp_warning_countdown", 60) + self.__temp_critical_countdown = self.__fancontrol_para.get("temp_critical_countdown", 60) + self.__temp_emergency_countdown = self.__fancontrol_para.get("temp_emergency_countdown", 60) + self.__rotor_error_count = self.__fancontrol_para.get("rotor_error_count", 6) + self.__inlet_mac_diff = self.__fancontrol_para.get("inlet_mac_diff", 50) + self.__check_crit_reboot_flag = self.__fancontrol_para.get("check_crit_reboot_flag", 1) + self.__check_emerg_reboot_flag = self.__fancontrol_para.get("check_emerg_reboot_flag", 1) + self.__check_crit_reboot_num = self.__fancontrol_para.get("check_crit_reboot_num", 3) + self.__check_crit_sleep_time = self.__fancontrol_para.get("check_crit_sleep_time", 20) + self.__check_emerg_reboot_num = self.__fancontrol_para.get("check_emerg_reboot_num", 3) + self.__check_emerg_sleep_time = self.__fancontrol_para.get("check_emerg_sleep_time", 20) + self.__check_temp_emergency = self.__fancontrol_para.get("check_temp_emergency", 0) + self.__check_temp_critical = self.__fancontrol_para.get("check_temp_critical", 1) + self.__check_temp_warning = self.__fancontrol_para.get("check_temp_warning", 1) + self.__check_temp_emergency_reboot = self.__fancontrol_para.get("check_temp_emergency_reboot", []) + self.__psu_absent_fullspeed_num = self.__fancontrol_para.get("psu_absent_fullspeed_num", 1) + self.__fan_absent_fullspeed_num = self.__fancontrol_para.get("fan_absent_fullspeed_num", 1) + self.__rotor_error_fullspeed_num = self.__fancontrol_para.get("rotor_error_fullspeed_num", 1) + self.__psu_fan_control = self.__fancontrol_para.get("psu_fan_control", 1) # default control psu fan + self.__fan_plug_in_pwm = self.__fancontrol_para.get("fan_plug_in_pwm", 0x80) + self.__fan_plug_in_default_countdown = self.__fancontrol_para.get("fan_plug_in_default_countdown", 0) + self.__deal_fan_error_policy = self.__fancontrol_para.get("deal_fan_error", 0) + self.__deal_fan_error_conf = self.__fancontrol_para.get("deal_fan_error_conf", {}) + self.__deal_fan_error_default_countdown = self.__deal_fan_error_conf.get("countdown", 0) + + self.__warning_countdown = 0 # temp warning flag for normal fancontrol + self.__critical_countdown = 0 # temp critical flag for normal fancontrol + self.__emergency_countdown = 0 # temp emergency flag for normal fancontrol + self.__fan_plug_in_countdown = 0 # fan plug in flag for normal fancontrol + self.__deal_fan_error_countdown = 0 + self.__fan_absent_num = 0 + self.__fan_nok_num = 0 + self.__pre_fan_nok = PRE_FAN_NOK_UNKNOWN + self.openloop = openloop() + self.pid = pid() + self.hyst = hysteresis() + self.__pwm = self.__min_pwm + + self.__board_air_flow = "" + self.__fan_air_flow_monitor = self.__fancontrol_para.get("fan_air_flow_monitor", 0) + self.__psu_air_flow_monitor = self.__fancontrol_para.get("psu_air_flow_monitor", 0) + self.__air_flow_correct_fan_pwm = self.__fancontrol_para.get("air_flow_correct_fan_pwm", 0xff) + self.__air_flow_correct_psu_pwm = self.__fancontrol_para.get("air_flow_correct_psu_pwm", 0xff) + self.__air_flow_error_fan_pwm = self.__fancontrol_para.get("air_flow_error_fan_pwm", 0) + self.__air_flow_error_psu_pwm = self.__fancontrol_para.get("air_flow_error_psu_pwm", 0) + self.fan_air_flow_inconsistent_flag = False + self.psu_air_flow_inconsistent_flag = False + self.air_flow_inconsistent_flag = False + self.fan_obj_list = [] + self.psu_obj_list = [] + + @property + def na_ret(self): + return self.int_case.na_ret + + def get_onie_e2_obj(self, name): + return self.int_case.get_onie_e2_obj(name) + + @property + def board_air_flow(self): + air_flow_tuple = (F2B_AIR_FLOW, B2F_AIR_FLOW) + if self.__board_air_flow not in air_flow_tuple: + self.__board_air_flow = self.int_case.get_device_airflow(ONIE_E2_NAME) + fanairflow_debug("board_air_flow: %s" % self.__board_air_flow) + return self.__board_air_flow + + @property + def fan_air_flow_monitor(self): + return self.__fan_air_flow_monitor + + @property + def psu_air_flow_monitor(self): + return self.__psu_air_flow_monitor + + @property + def air_flow_correct_fan_pwm(self): + return self.__air_flow_correct_fan_pwm + + @property + def air_flow_correct_psu_pwm(self): + return self.__air_flow_correct_psu_pwm + + @property + def air_flow_error_fan_pwm(self): + return self.__air_flow_error_fan_pwm + + @property + def air_flow_error_psu_pwm(self): + return self.__air_flow_error_psu_pwm + + def get_para(self, t): + para = self.__pid_config.get(t) + return para + + def update_over_temp_threshold_num(self): + for temp_threshold in self.__temps_threshold_config.values(): + if temp_threshold['ignore_threshold']: + continue + emergency_threshold = temp_threshold.get('emergency', None) + critical_threshold = temp_threshold.get('critical', None) + warning_threshold = temp_threshold.get('warning', None) + fancontrol_debug("%s warning = %s, critical = %s, emergency = %s" % + (temp_threshold['name'], warning_threshold, critical_threshold, emergency_threshold)) + + if emergency_threshold is not None and temp_threshold['temp'] >= emergency_threshold: + temp_threshold['emergency_num'] += 1 + else: + temp_threshold['emergency_num'] = 0 + + if critical_threshold is not None and temp_threshold['temp'] >= critical_threshold: + temp_threshold['critical_num'] += 1 + else: + temp_threshold['critical_num'] = 0 + + if warning_threshold is not None and temp_threshold['temp'] >= warning_threshold: + temp_threshold['warning_num'] += 1 + else: + temp_threshold['warning_num'] = 0 + + fancontrol_debug("%s warning_num = %d, critical_num = %d, emergency_num = %d" % + (temp_threshold['name'], temp_threshold['warning_num'], temp_threshold['critical_num'], temp_threshold.get("emergency_num"))) + + def get_monitor_temp(self): + sensorlist = self.int_case.get_temp_info() + + for temp_threshold in self.__temps_threshold_config.values(): + sensor = sensorlist.get(temp_threshold['name']) + if sensor["Value"] is None or int(sensor["Value"]) == self.int_case.error_ret: + temp_threshold['fail_num'] += 1 + fancontrol_error("get %s failed, fail_num = %d" % (temp_threshold['name'], temp_threshold['fail_num'])) + else: + temp_threshold['fail_num'] = 0 + temp_threshold.setdefault('fix', 0) + temp_threshold['temp'] = sensor["Value"] + temp_threshold['fix'] + fancontrol_debug("%s = %d" % (temp_threshold['name'], temp_threshold['temp'])) + self.update_over_temp_threshold_num() + + def is_temp_warning(self): + warning_flag = False + for temp_threshold in self.__temps_threshold_config.values(): + if temp_threshold['ignore_threshold']: + continue + if temp_threshold['warning_num'] >= self.__temp_warning_num: + warning_flag = True + fancontrol_warn("%%FANCONTROL-4-TEMP_HIGH: %s temperature %sC is larger than warning threshold %sC." % + (temp_threshold['name'], temp_threshold['temp'], temp_threshold.get('warning'))) + return warning_flag + + def checkTempWarning(self): + try: + if self.is_temp_warning(): + self.__warning_countdown = self.__temp_warning_countdown + fancontrol_debug("temp is over warning") + return True + if self.__warning_countdown > 0: + self.__warning_countdown -= 1 + return False + except Exception as e: + fancontrol_error("%%policy: checkTempWarning failed") + fancontrol_error(str(e)) + return False + + def checkTempWarningCountdown(self): + if self.__warning_countdown > 0: + return True + return False + + def is_temp_critical(self): + critical_flag = False + for temp_threshold in self.__temps_threshold_config.values(): + temp_threshold['critical_flag'] = False + if temp_threshold['ignore_threshold']: + continue + if temp_threshold['critical_num'] >= self.__temp_critical_num: + critical_flag = True + temp_threshold['critical_flag'] = True + fancontrol_crit("%%FANCONTROL-2-TEMP_HIGH: %s temperature %sC is larger than critical threshold %sC." % + (temp_threshold['name'], temp_threshold['temp'], temp_threshold.get('critical'))) + return critical_flag + + def checkTempCritical(self): + try: + if self.is_temp_critical(): + self.__critical_countdown = self.__temp_critical_countdown + fancontrol_debug("temp is over critical") + return True + if self.__critical_countdown > 0: + self.__critical_countdown -= 1 + return False + except Exception as e: + fancontrol_error("%%policy: checkTempCrit failed") + fancontrol_error(str(e)) + return False + + def is_temp_emergency(self): + emergency_flag = False + for temp_threshold in self.__temps_threshold_config.values(): + temp_threshold['emergency_flag'] = False + if temp_threshold['ignore_threshold']: + continue + if temp_threshold['emergency_num'] >= self.__temp_emergency_num: + emergency_flag = True + temp_threshold['emergency_flag'] = True + fancontrol_alert("%%FANCONTROL-1-TEMP_HIGH: %s temperature %sC is larger than emergency threshold %sC." % + (temp_threshold['name'], temp_threshold['temp'], temp_threshold.get('emergency'))) + return emergency_flag + + def checkTempEmergency(self): + try: + if self.is_temp_emergency(): + self.__emergency_countdown = self.__temp_emergency_countdown + fancontrol_debug("temp is over emergency") + return True + if self.__emergency_countdown > 0: + self.__emergency_countdown -= 1 + return False + except Exception as e: + fancontrol_error("%%policy: checkTempEmergency failed") + fancontrol_error(str(e)) + return False + + def checkTempCriticalCountdown(self): + if self.__critical_countdown > 0: + return True + return False + + def checkTempEmergencyCountdown(self): + if self.__emergency_countdown > 0: + return True + return False + + def checkTempRebootCrit(self): + try: + if self.is_temp_critical(): + temp_dict = dict(self.__temps_threshold_config) + tmp = temp_dict.get(SWITCH_TEMP) + if tmp['critical_flag'] is True: + fancontrol_debug("switch temp is over reboot critical") + return TEMP_REBOOT_CRIT_SWITCH_FLAG + del temp_dict[SWITCH_TEMP] + for temp_items in temp_dict.values(): + if temp_items['ignore_threshold']: + continue + if temp_items['critical_flag'] is False: + return 0 + + fancontrol_debug("other temp is over reboot critical") + return TEMP_REBOOT_CRIT_OTHER_FLAG + except Exception as e: + fancontrol_error("%%policy: checkTempRebootCrit failed") + fancontrol_error(str(e)) + return 0 + + def checkCritReboot(self): + try: + reboot_flag = self.checkTempRebootCrit() + if reboot_flag > 0: + self.set_all_fan_speed_pwm(self.__max_pwm) + for i in range(self.__check_crit_reboot_num): + time.sleep(self.__check_crit_sleep_time) + self.get_monitor_temp() + reboot_flag = self.checkTempRebootCrit() + if reboot_flag > 0: + fancontrol_emerg("%%FANCONTROL-0-TEMP_EMERG: The temperature of device over reboot critical value lasts for %d seconds." % + (self.__check_crit_sleep_time * (i + 1))) + continue + fancontrol_debug("The temperature of device is not over reboot critical value.") + break + if reboot_flag > 0: + fancontrol_emerg( + "%%FANCONTROL-0-TEMP_EMERG: The temperature of device over reboot critical value, system is going to reboot now.") + for temp_threshold in self.__temps_threshold_config.values(): + fancontrol_emerg( + "%%FANCONTROL-TEMP_EMERG: %s temperature: %sC." % + (temp_threshold['name'], temp_threshold['temp'])) + if reboot_flag == TEMP_REBOOT_CRIT_SWITCH_FLAG: + create_judge_file = "touch %s" % self.__otp_switch_reboot_judge_file + else: + create_judge_file = "touch %s" % self.__otp_other_reboot_judge_file + exec_os_cmd(create_judge_file) + exec_os_cmd("sync") + time.sleep(3) + os.system("/sbin/reboot") + except Exception as e: + fancontrol_error("%%policy: checkCritReboot failed") + fancontrol_error(str(e)) + + def checkTempRebootEmerg(self): + try: + if self.is_temp_emergency(): + temp_emerg_reboot_flag = False + for temp_list in self.__check_temp_emergency_reboot: + for temp in temp_list: + tmp = self.__temps_threshold_config.get(temp) + if tmp['emergency_flag'] is False: + fancontrol_debug("temp_list %s, temp: %s not emergency" % (temp_list, temp)) + temp_emerg_reboot_flag = False + break + temp_emerg_reboot_flag = True + if temp_emerg_reboot_flag is True: + fancontrol_debug("temp_list %s, all temp is over emergency reboot" % temp_list) + return True + except Exception as e: + fancontrol_error("%%policy: checkTempRebootEmerg failed") + fancontrol_error(str(e)) + return False + + def checkEmergReboot(self): + try: + reboot_flag = False + if self.checkTempRebootEmerg() is True: + self.set_all_fan_speed_pwm(self.__max_pwm) + for i in range(self.__check_emerg_reboot_num): + time.sleep(self.__check_emerg_sleep_time) + self.get_monitor_temp() + if self.checkTempRebootEmerg() is True: + fancontrol_emerg("%%FANCONTROL-0-TEMP_EMERG: The temperature of device over reboot emergency value lasts for %d seconds." % + (self.__check_emerg_sleep_time * (i + 1))) + reboot_flag = True + continue + fancontrol_debug("The temperature of device is not over reboot emergency value.") + reboot_flag = False + break + if reboot_flag is True: + fancontrol_emerg( + "%%FANCONTROL-0-TEMP_EMERG: The temperature of device over reboot emergency value, system is going to reboot now.") + for temp_threshold in self.__temps_threshold_config.values(): + fancontrol_emerg( + "%%FANCONTROL-0-TEMP_EMERG: %s temperature: %sC." % + (temp_threshold['name'], temp_threshold['temp'])) + create_judge_file = "touch %s" % OTP_SWITCH_REBOOT_JUDGE_FILE + exec_os_cmd(create_judge_file) + exec_os_cmd("sync") + time.sleep(3) + os.system("/sbin/reboot") + except Exception as e: + fancontrol_error("%%policy: checkEmergReboot failed") + fancontrol_error(str(e)) + + def get_fan_total_number(self): + return self.int_case.get_fan_total_number() + + def get_rotor_number(self, fan_name): + return self.int_case.get_fan_rotor_number(fan_name) + + def get_fan_presence(self, fan_name): + return self.int_case.get_fan_presence(fan_name) + + def get_fan_rotor_status(self, fan_name, rotor_name): + return self.int_case.get_fan_rotor_status(fan_name, rotor_name) + + def get_psu_total_number(self): + return self.int_case.get_psu_total_number() + + def get_psu_presence(self, psu_name): + return self.int_case.get_psu_presence(psu_name) + + def get_psu_input_output_status(self, psu_name): + return self.int_case.get_psu_input_output_status(psu_name) + + def checkFanPresence(self): + absent_num = 0 + + fan_num = self.get_fan_total_number() + for i in range(fan_num): + fan_name = "FAN" + str(i + 1) + rotor_num = self.get_rotor_number(fan_name) + tmp_fan = self.__fan_rotor_error_num.get(fan_name) + status = self.get_fan_presence(fan_name) + if status is False: + absent_num = absent_num + 1 + self.__fan_present_status[fan_name] = 0 + fancontrol_debug("%s absent" % fan_name) + else: + if self.__fan_present_status[fan_name] == 0: # absent -> present + self.__pre_fan_nok = PRE_FAN_NOK_UNKNOWN + self.__fan_plug_in_countdown = self.__fan_plug_in_default_countdown + self.__fan_repair_flag[fan_name] = 1 + for j in range(rotor_num): + rotor_name = "Rotor" + str(j + 1) + tmp_fan[rotor_name] = 0 + self.__fan_present_status[fan_name] = 1 + fancontrol_debug("%s presence" % fan_name) + return absent_num + + def checkFanRotorStatus(self): + err_num = 0 + self.__fan_nok_num = 0 + fan_num = self.get_fan_total_number() + for i in range(fan_num): + fan_name = "FAN" + str(i + 1) + rotor_num = self.get_rotor_number(fan_name) + tmp_fan = self.__fan_rotor_error_num.get(fan_name) + fan_rotor_err_cnt = 0 + for j in range(rotor_num): + rotor_name = "Rotor" + str(j + 1) + status = self.get_fan_rotor_status(fan_name, rotor_name) + if status is True: + tmp_fan[rotor_name] = 0 + fancontrol_debug("%s %s ok" % (fan_name, rotor_name)) + else: + tmp_fan[rotor_name] += 1 + if tmp_fan[rotor_name] >= self.__rotor_error_count: + err_num = err_num + 1 + fan_rotor_err_cnt += 1 + fancontrol_debug("%s %s error" % (fan_name, rotor_name)) + fancontrol_debug("%s %s error %d times" % (fan_name, rotor_name, tmp_fan[rotor_name])) + if fan_rotor_err_cnt == 0: + self.__fan_rotate_status[fan_name] = 1 # FAN is ok + else: + self.__fan_rotate_status[fan_name] = 0 # FAN is not ok + self.__fan_nok_num += 1 + fancontrol_debug("fan not ok number:%d." % self.__fan_nok_num) + return err_num + + def checkPsuPresence(self): + absent_num = 0 + psu_num = self.get_psu_total_number() + for i in range(psu_num): + psu_name = "PSU" + str(i + 1) + status = self.get_psu_presence(psu_name) + if status is False: + absent_num = absent_num + 1 + fancontrol_debug("%s absent" % psu_name) + else: + fancontrol_debug("%s presence" % psu_name) + return absent_num + + def checkPsuStatus(self): + err_num = 0 + psu_num = self.get_psu_total_number() + for i in range(psu_num): + psu_name = "PSU" + str(i + 1) + status = self.get_psu_input_output_status(psu_name) + if status is False: + err_num = err_num + 1 + fancontrol_debug("%s error" % psu_name) + else: + fancontrol_debug("%s ok" % psu_name) + return err_num + + def checkDevError(self): + pwm = self.__min_pwm + switchtemp = self.__temps_threshold_config.get(SWITCH_TEMP)['temp'] + inlettemp = self.__temps_threshold_config.get(INLET_TEMP)['temp'] + temp_diff = abs(switchtemp - inlettemp) + fancontrol_debug("|switchtemp - inlettemp| = %d" % temp_diff) + if temp_diff >= self.__inlet_mac_diff: + fancontrol_debug("temp_diff is over than inlet_mac_diff(%d)" % self.__inlet_mac_diff) + if self.__pwm > self.__abnormal_pwm: + pwm = self.__max_pwm + else: + pwm = self.__abnormal_pwm + return pwm + + def checktempfail(self): + pwm = self.__min_pwm + for temp in self.__check_temp_fail: + temp_name = temp.get("temp_name") + temp_fail_num = self.__temps_threshold_config.get(temp_name)['fail_num'] + if temp_fail_num >= self.__temp_fail_num: + pwm = self.__abnormal_pwm + fancontrol_debug("%s temp_fail_num = %d" % (temp_name, temp_fail_num)) + fancontrol_debug("self.__temp_fail_num = %d" % self.__temp_fail_num) + return pwm + + def abnormal_check(self): + pwm_list = [] + pwm_min = self.__min_pwm + pwm_list.append(pwm_min) + + if self.__check_temp_emergency == 1: + status = self.checkTempEmergency() + if status is True: + over_emerg_pwm = self.__max_pwm + pwm_list.append(over_emerg_pwm) + fancontrol_debug("over_emerg_pwm = 0x%x" % over_emerg_pwm) + # do reset check + if self.__check_emerg_reboot_flag == 1: + self.checkEmergReboot() + else: + if self.checkTempEmergencyCountdown() is True: # temp lower than emergency in 5 min + over_emerg_countdown_pwm = self.__max_pwm + pwm_list.append(over_emerg_countdown_pwm) + fancontrol_debug("TempEmergencyCountdown: %d, over_emerg_countdown_pwm = 0x%x" % + (self.__emergency_countdown, over_emerg_countdown_pwm)) + + if self.__check_temp_critical == 1: + status = self.checkTempCritical() + if status is True: + over_crit_pwm = self.__max_pwm + pwm_list.append(over_crit_pwm) + fancontrol_debug("over_crit_pwm = 0x%x" % over_crit_pwm) + # do reset check + if self.__check_crit_reboot_flag == 1: + self.checkCritReboot() + else: + if self.checkTempCriticalCountdown() is True: # temp lower than critical in 5 min + over_crit_countdown_pwm = self.__max_pwm + pwm_list.append(over_crit_countdown_pwm) + fancontrol_debug("TempCriticalCountdown: %d, over_crit_countdown_pwm = 0x%x" % + (self.__critical_countdown, over_crit_countdown_pwm)) + + if self.__check_temp_warning == 1: + status = self.checkTempWarning() + if status is True: + over_warn_pwm = self.__warning_pwm + pwm_list.append(over_warn_pwm) + fancontrol_debug("over_warn_pwm = 0x%x" % over_warn_pwm) + else: + if self.checkTempWarningCountdown() is True: # temp lower than warning in 5 min + over_warn_countdown_pwm = self.__warning_pwm + pwm_list.append(over_warn_countdown_pwm) + fancontrol_debug("TempWarningCountdown: %d, over_warn_countdown_pwm = 0x%x" % + (self.__warning_countdown, over_warn_countdown_pwm)) + + self.__fan_absent_num = self.checkFanPresence() + if self.__fan_absent_num >= self.__fan_absent_fullspeed_num: + fan_absent_pwm = self.__max_pwm + pwm_list.append(fan_absent_pwm) + fancontrol_debug("fan_absent_pwm = 0x%x" % fan_absent_pwm) + + rotor_err_num = self.checkFanRotorStatus() + if rotor_err_num >= self.__rotor_error_fullspeed_num: + rotor_err_pwm = self.__max_pwm + pwm_list.append(rotor_err_pwm) + fancontrol_debug("rotor_err_pwm = 0x%x" % rotor_err_pwm) + + psu_absent_num = self.checkPsuPresence() + if psu_absent_num >= self.__psu_absent_fullspeed_num: + psu_absent_pwm = self.__max_pwm + pwm_list.append(psu_absent_pwm) + fancontrol_debug("psu_absent_pwm = 0x%x" % psu_absent_pwm) + + dev_err_pwm = self.checkDevError() + pwm_list.append(dev_err_pwm) + fancontrol_debug("dev_err_pwm = 0x%x" % dev_err_pwm) + + temp_fail_pwm = self.checktempfail() + pwm_list.append(temp_fail_pwm) + fancontrol_debug("temp_fail_pwm = 0x%x" % temp_fail_pwm) + + pwm = max(pwm_list) + return pwm + + def get_error_fan(self): + fan_num = self.get_fan_total_number() + for i in range(fan_num): + fan_name = "FAN" + str(i + 1) + if self.__fan_rotate_status[fan_name] == 0: + return fan_name + return None + + def fan_error_update_pwm(self, fan_pwm_dict): + try: + fancontrol_debug("enter deal fan error policy") + ori_fan_pwm_dict = fan_pwm_dict.copy() + + err_fan_name = self.get_error_fan() + if err_fan_name is None: + fancontrol_debug("fan name is None, do nothing.") + return ori_fan_pwm_dict + + if self.__fan_repair_flag[err_fan_name] == 0: + fancontrol_debug("%s already repaired, do nothing." % err_fan_name) + return ori_fan_pwm_dict + + if self.__pre_fan_nok != err_fan_name: + fancontrol_debug( + "not ok fan change from %s to %s, update countdown." % + (self.__pre_fan_nok, err_fan_name)) + self.__deal_fan_error_countdown = self.__deal_fan_error_default_countdown + if self.__pre_fan_nok != PRE_FAN_NOK_UNKNOWN: + fancontrol_debug( + "%s repaire success, %s NOT OK, try to repaire." % + (self.__pre_fan_nok, err_fan_name)) + self.__fan_repair_flag[self.__pre_fan_nok] = 0 + self.__pre_fan_nok = err_fan_name + + if self.__deal_fan_error_countdown > 0: + self.__deal_fan_error_countdown -= 1 + fancontrol_debug("%s repaire, countdown %d." % (err_fan_name, self.__deal_fan_error_countdown)) + + if self.__deal_fan_error_countdown == 0: + self.__fan_repair_flag[err_fan_name] = 0 + fancontrol_debug("%s set repaire fail flag, use origin pwm." % err_fan_name) + return ori_fan_pwm_dict + + fan_err_pwm_conf_list = self.__deal_fan_error_conf[err_fan_name] + for item in fan_err_pwm_conf_list: + fan_pwm_dict[item["name"]] = item["pwm"] + fancontrol_debug("fan pwm update, fan pwm dict:%s" % fan_pwm_dict) + + return fan_pwm_dict + except Exception as e: + fancontrol_error("%%policy: deal_fan_error raise Exception:%s" % str(e)) + self.__pre_fan_nok = PRE_FAN_NOK_UNKNOWN + return ori_fan_pwm_dict + + def get_fan_pwm_dict(self, default_pwm): + fan_pwm_dict = {} + fan_num = self.get_fan_total_number() + for i in range(fan_num): + fan_name = "FAN" + str(i + 1) + fan_pwm_dict[fan_name] = default_pwm + if self.__deal_fan_error_policy: + if self.__fan_absent_num == 0 and self.__fan_nok_num == 1: + fan_pwm_dict = self.fan_error_update_pwm(fan_pwm_dict) + else: + if self.__pre_fan_nok != PRE_FAN_NOK_UNKNOWN and self.__fan_rotate_status[self.__pre_fan_nok] == 1: + fancontrol_debug("%s repaire success." % (self.__pre_fan_nok)) + self.__fan_repair_flag[self.__pre_fan_nok] = 0 + self.__pre_fan_nok = PRE_FAN_NOK_UNKNOWN + return fan_pwm_dict + + def get_psu_pwm_dict(self, default_pwm): + psu_pwm_dict = {} + psu_num = self.get_psu_total_number() + for i in range(psu_num): + psu_name = "PSU" + str(i + 1) + psu_pwm_dict[psu_name] = default_pwm + return psu_pwm_dict + + def check_board_air_flow(self): + board_air_flow = self.board_air_flow + air_flow_tuple = (F2B_AIR_FLOW, B2F_AIR_FLOW) + if board_air_flow not in air_flow_tuple: + fanairflow_debug("get board air flow error, value [%s]" % board_air_flow) + return False + fanairflow_debug("board air flow check ok: %s" % board_air_flow) + return True + + def check_fan_air_flow(self): + if self.fan_air_flow_monitor: + fanairflow_debug("open air flow monitor, check fan air flow") + ret = self.check_board_air_flow() + if ret is False: + fanairflow_debug("get board air flow error, set fan_air_flow_inconsistent_flag False") + self.fan_air_flow_inconsistent_flag = False + return + air_flow_inconsistent_flag_tmp = False + for fan_obj in self.fan_obj_list: + fan_obj.update_fru_info() + fanairflow_debug("%s origin name: [%s], display name: [%s] air flow [%s]" % + (fan_obj.name, fan_obj.origin_name, fan_obj.display_name, fan_obj.air_flow)) + if fan_obj.air_flow == self.na_ret: + fanairflow_debug("%s get air flow failed, set air_flow_inconsistent flag False" % fan_obj.name) + fan_obj.air_flow_inconsistent = False + continue + if fan_obj.air_flow != self.board_air_flow: + fanairflow_debug("%s air flow error, origin name: [%s], display name: [%s], fan air flow [%s], board air flow [%s]" % + (fan_obj.name, fan_obj.origin_name, fan_obj.display_name, fan_obj.air_flow, self.board_air_flow)) + air_flow_inconsistent_flag_tmp = True + fan_obj.air_flow_inconsistent = True + else: + fanairflow_debug("%s air flow check ok, origin name: [%s], display name: [%s], fan air flow: [%s], board air flow: [%s]" % + (fan_obj.name, fan_obj.origin_name, fan_obj.display_name, fan_obj.air_flow, self.board_air_flow)) + fan_obj.air_flow_inconsistent = False + self.fan_air_flow_inconsistent_flag = air_flow_inconsistent_flag_tmp + else: + fanairflow_debug("air flow monitor not open, set fan_air_flow_inconsistent_flag False") + self.fan_air_flow_inconsistent_flag = False + return + + def check_psu_air_flow(self): + if self.psu_air_flow_monitor: + fanairflow_debug("open air flow monitor, check psu air flow") + ret = self.check_board_air_flow() + if ret is False: + fanairflow_debug("get board air flow error, set psu_air_flow_inconsistent_flag False") + self.psu_air_flow_inconsistent_flag = False + return + air_flow_inconsistent_flag_tmp = False + for psu_obj in self.psu_obj_list: + psu_obj.update_fru_info() + fanairflow_debug("%s origin name: [%s], display name: [%s] air flow [%s]" % + (psu_obj.name, psu_obj.origin_name, psu_obj.display_name, psu_obj.air_flow)) + if psu_obj.air_flow == self.na_ret: + fanairflow_debug("%s get air flow failed, set air_flow_inconsistent flag False" % psu_obj.name) + psu_obj.air_flow_inconsistent = False + continue + if psu_obj.air_flow != self.board_air_flow: + fanairflow_debug("%s air flow error, origin name: [%s], display name: [%s], psu air flow [%s], board air flow [%s]" % + (psu_obj.name, psu_obj.origin_name, psu_obj.display_name, psu_obj.air_flow, self.board_air_flow)) + air_flow_inconsistent_flag_tmp = True + psu_obj.air_flow_inconsistent = True + else: + fanairflow_debug("%s air flow check ok, origin name: [%s], display name: [%s], psu air flow: [%s], board air flow: [%s]" % + (psu_obj.name, psu_obj.origin_name, psu_obj.display_name, psu_obj.air_flow, self.board_air_flow)) + psu_obj.air_flow_inconsistent = False + self.psu_air_flow_inconsistent_flag = air_flow_inconsistent_flag_tmp + else: + fanairflow_debug("air flow monitor not open, set psu_air_flow_inconsistent_flag False") + self.psu_air_flow_inconsistent_flag = False + return + + def do_fancontrol(self): + pwm_list = [] + pwm_min = self.__min_pwm + pwm_list.append(pwm_min) + + # first check air flow + self.check_fan_air_flow() + self.check_psu_air_flow() + if self.fan_air_flow_inconsistent_flag is True or self.psu_air_flow_inconsistent_flag is True: + self.air_flow_inconsistent_flag = True + else: + self.air_flow_inconsistent_flag = False + fanairflow_debug("check_air_flow, air_flow_inconsistent_flag: %s" % self.air_flow_inconsistent_flag) + # get_monitor_temp + self.get_monitor_temp() + fancontrol_debug("last_pwm = 0x%x" % self.__pwm) + # openloop + inlettemp = self.__temps_threshold_config.get(INLET_TEMP)['temp'] + linear_value = self.openloop.linear_cacl(inlettemp) + if linear_value is None: + linear_value = self.__min_pwm + pwm_list.append(linear_value) + fancontrol_debug("linear_value = 0x%x" % linear_value) + + curve_value = self.openloop.curve_cacl(inlettemp) + if curve_value is None: + curve_value = self.__min_pwm + pwm_list.append(curve_value) + fancontrol_debug("curve_value = 0x%x" % curve_value) + + # hyst + for hyst_index in self.__hyst_config.values(): + temp_name = hyst_index.get("name") + hyst_flag = hyst_index.get("flag", 0) + if hyst_flag == 0: + fancontrol_debug("%s hyst flag is 0, do nothing" % temp_name) + continue + tmp_temp = int(self.__temps_threshold_config.get(temp_name)['temp']) # make sure temp is int + hyst_value = self.hyst.cacl(temp_name, tmp_temp) + if hyst_value is None: + hyst_value = self.__min_pwm + pwm_list.append(hyst_value) + fancontrol_debug("%s hyst_value = 0x%x" % (temp_name, hyst_value)) + + # pid + for pid_index in self.__pid_config.values(): + temp_name = pid_index.get("name") + pid_flag = pid_index.get("flag", 0) + if pid_flag == 0: + fancontrol_debug("%s pid flag is 0, do nothing" % temp_name) + continue + tmp_temp = self.__temps_threshold_config.get(temp_name)['temp'] + if tmp_temp is not None: + tmp_temp = int(tmp_temp) # make sure temp is int + invalid_temp_val = self.__temps_threshold_config.get(temp_name)['invalid'] + error_temp_val = self.__temps_threshold_config.get(temp_name)['error'] + if tmp_temp == invalid_temp_val: # temp is invalid + temp = None + self.pid.cacl(self.__pwm, temp_name, temp) # temp invalid, PID need to record None + pid_value = self.__temp_invalid_pid_pwm + fancontrol_debug("%s is invalid, pid_value = 0x%x" % (temp_name, pid_value)) + fancontrol_debug("temp = %d, invalid_temp = %d" % (tmp_temp, invalid_temp_val)) + elif tmp_temp == error_temp_val: # temp is error + temp = None + self.pid.cacl(self.__pwm, temp_name, temp) # temp error, PID need to record None + pid_value = self.__temp_error_pid_pwm + fancontrol_debug("%s is error, pid_value = 0x%x" % (temp_name, pid_value)) + fancontrol_debug("temp = %d, error_temp = %d" % (tmp_temp, error_temp_val)) + else: + pid_value = self.pid.cacl(self.__pwm, temp_name, tmp_temp) + else: # temp get failed + pid_value = self.pid.cacl(self.__pwm, temp_name, tmp_temp) + if pid_value is None: + pid_value = self.__min_pwm + pwm_list.append(pid_value) + fancontrol_debug("%s pid_value = 0x%x" % (temp_name, pid_value)) + + # abnormal + abnormal_value = self.abnormal_check() + pwm_list.append(abnormal_value) + fancontrol_debug("abnormal_value = 0x%x" % abnormal_value) + + if self.__fan_plug_in_countdown > 0 and self.__fan_absent_num == 0: + fancontrol_debug("fan plug in countdown %d, set plug in pwm: 0x%x" % + (self.__fan_plug_in_countdown, self.__fan_plug_in_pwm)) + self.__pwm = self.__fan_plug_in_pwm + self.__fan_plug_in_countdown -= 1 + else: + self.__pwm = max(pwm_list) + fancontrol_debug("__pwm = 0x%x\n" % self.__pwm) + if self.air_flow_inconsistent_flag is True: + fanairflow_debug("air flow inconsistent, set all fan speed pwm") + self.set_all_fan_speed_pwm(self.__pwm) + else: + fanairflow_debug("air flow consistent, deal fan error policy") + fan_pwm_dict = self.get_fan_pwm_dict(self.__pwm) + psu_pwm_dict = self.get_psu_pwm_dict(self.__pwm) + self.set_fan_pwm_independent(fan_pwm_dict, psu_pwm_dict) + + def run(self): + start_time = time.time() + while True: + try: + debug_init() + if self.__fan_status_interval > 0 and self.__fan_status_interval < self.__interval: + delta_time = time.time() - start_time + if delta_time >= self.__interval or delta_time < 0: + self.do_fancontrol() + start_time = time.time() + else: + self.checkFanPresence() + time.sleep(self.__fan_status_interval) + else: + self.do_fancontrol() + time.sleep(self.__interval) + except Exception as e: + traceback.print_exc() + fancontrol_error(str(e)) + + def set_all_fan_speed_pwm(self, pwm): + fan_pwm_dict = {} + psu_pwm_dict = {} + fan_num = self.get_fan_total_number() + for i in range(fan_num): + fan_name = "FAN" + str(i + 1) + fan_pwm_dict[fan_name] = pwm + + psu_num = self.get_psu_total_number() + for i in range(psu_num): + psu_name = "PSU" + str(i + 1) + psu_pwm_dict[psu_name] = pwm + self.set_fan_pwm_independent(fan_pwm_dict, psu_pwm_dict) + + def set_fan_pwm_independent(self, fan_pwm_dict, psu_pwm_dict): + if self.air_flow_inconsistent_flag is True: + for psu_obj in self.psu_obj_list: + if psu_obj.air_flow_inconsistent is True: + psu_pwm_dict[psu_obj.name] = self.air_flow_error_psu_pwm + fanairflow_debug("%s air flow error, origin name: [%s], display name: [%s], psu air flow: [%s], board air flow: [%s], set psu pwm: 0x%x" % + (psu_obj.name, psu_obj.origin_name, psu_obj.display_name, psu_obj.air_flow, self.board_air_flow, self.air_flow_error_psu_pwm)) + else: + psu_pwm_dict[psu_obj.name] = self.air_flow_correct_psu_pwm + fanairflow_debug("%s air flow correct, origin name: [%s], display name: [%s], psu air flow: [%s], board air flow: [%s], set psu pwm: 0x%x" % + (psu_obj.name, psu_obj.origin_name, psu_obj.display_name, psu_obj.air_flow, self.board_air_flow, self.air_flow_correct_psu_pwm)) + + for fan_obj in self.fan_obj_list: + if fan_obj.air_flow_inconsistent is True: + fan_pwm_dict[fan_obj.name] = self.air_flow_error_fan_pwm + fanairflow_debug("%s air flow error, origin name: [%s], display name: [%s], fan air flow: [%s], board air flow: [%s], set fan pwm: 0x%x" % + (fan_obj.name, fan_obj.origin_name, fan_obj.display_name, fan_obj.air_flow, self.board_air_flow, self.air_flow_error_fan_pwm)) + else: + fan_pwm_dict[fan_obj.name] = self.air_flow_correct_fan_pwm + fanairflow_debug("%s air flow correct, origin name: [%s], display name: [%s], fan air flow: [%s], board air flow: [%s], set fan pwm: 0x%x" % + (fan_obj.name, fan_obj.origin_name, fan_obj.display_name, fan_obj.air_flow, self.board_air_flow, self.air_flow_correct_fan_pwm)) + fan_num = self.get_fan_total_number() + for i in range(fan_num): + fan_name = "FAN" + str(i + 1) + self.fan_set_speed_pwm_by_name(fan_name, fan_pwm_dict[fan_name]) + if self.__psu_fan_control == 1: + psu_num = self.get_psu_total_number() + for i in range(psu_num): + psu_name = "PSU" + str(i + 1) + self.psu_set_speed_pwm_by_name(psu_name, psu_pwm_dict[psu_name]) + + def fan_set_speed_pwm_by_name(self, fan_name, pwm): + duty = round(pwm * 100 / 255) + rotor_len = self.get_rotor_number(fan_name) + for i in range(rotor_len): + val = self.int_case.set_fan_speed_pwm(fan_name, i + 1, duty) + if val != 0: + fancontrol_error("%s rotor%d: %d" % (fan_name, i + 1, val)) + + def psu_set_speed_pwm_by_name(self, psu_name, pwm): + duty = round(pwm * 100 / 255) + status = self.int_case.set_psu_fan_speed_pwm(psu_name, int(duty)) + if status is not True: + fancontrol_error("set %s speed fail" % psu_name) + + def fan_obj_init(self): + fan_num = self.get_fan_total_number() + for i in range(fan_num): + fan_name = "FAN" + str(i + 1) + fan_obj = DevFan(fan_name, self.int_case) + self.fan_obj_list.append(fan_obj) + fanairflow_debug("fan object initialize success") + + def psu_obj_init(self): + psu_num = self.get_psu_total_number() + for i in range(psu_num): + psu_name = "PSU" + str(i + 1) + psu_obj = DevPsu(psu_name, self.int_case) + self.psu_obj_list.append(psu_obj) + fanairflow_debug("psu object initialize success") + + +if __name__ == '__main__': + debug_init() + fancontrol_debug("enter main") + fan_control = fancontrol() + fan_control.fan_obj_init() + fan_control.psu_obj_init() + fan_control.run() diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/script/hal_ledctrl.py b/platform/broadcom/sonic-platform-modules-ragile/common/script/hal_ledctrl.py new file mode 100755 index 000000000000..c21fd3c1f585 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/script/hal_ledctrl.py @@ -0,0 +1,830 @@ +#!/usr/bin/env python3 +import time +import syslog +import traceback +from plat_hal.interface import interface +from plat_hal.baseutil import baseutil +try: + import abc +except ImportError as error: + raise ImportError(str(error) + " - required module not found") from error + +SWITCH_TEMP = "SWITCH_TEMP" +F2B_AIR_FLOW = "intake" +B2F_AIR_FLOW = "exhaust" +ONIE_E2_NAME = "ONIE_E2" + +# status +STATUS_PRESENT = "PRESENT" +STATUS_ABSENT = "ABSENT" +STATUS_OK = "OK" +STATUS_NOT_OK = "NOT OK" +STATUS_FAILED = "FAILED" +STATUS_UNKNOWN = "UNKNOWN" + +LEDCTROL_DEBUG_FILE = "/etc/.ledcontrol_debug_flag" + +LEDCTROLERROR = 1 +LEDCTROLDEBUG = 2 + +debuglevel = 0 +# led status defined +COLOR_GREEN = 1 +COLOR_AMBER = 2 +COLOR_RED = 3 +LED_STATUS_DICT = {COLOR_GREEN: "green", COLOR_AMBER: "amber", COLOR_RED: "red"} + + +def ledcontrol_debug(s): + if LEDCTROLDEBUG & debuglevel: + syslog.openlog("LEDCONTROL", syslog.LOG_PID) + syslog.syslog(syslog.LOG_DEBUG, s) + + +def ledcontrol_error(s): + if LEDCTROLERROR & debuglevel: + syslog.openlog("LEDCONTROL", syslog.LOG_PID) + syslog.syslog(syslog.LOG_ERR, s) + + +def air_flow_warn(s): + syslog.openlog("AIR_FLOW_MONITOR", syslog.LOG_PID) + syslog.syslog(syslog.LOG_LOCAL1 | syslog.LOG_WARNING, s) + + +def air_flow_error(s): + syslog.openlog("AIR_FLOW_MONITOR", syslog.LOG_PID) + syslog.syslog(syslog.LOG_LOCAL1 | syslog.LOG_ERR, s) + + +def air_flow_emerg(s): + syslog.openlog("AIR_FLOW_MONITOR", syslog.LOG_PID) + syslog.syslog(syslog.LOG_LOCAL1 | syslog.LOG_EMERG, s) + + +def debug_init(): + global debuglevel + try: + with open(LEDCTROL_DEBUG_FILE, "r") as fd: + value = fd.read() + debuglevel = int(value) + except Exception: + debuglevel = 0 + + +class DevBase(object): + __metaclass__ = abc.ABCMeta + + def __init__(self, name, air_flow_monitor): + self.__name = name + self.__air_flow_monitor = air_flow_monitor + self.present = STATUS_UNKNOWN + self.status = STATUS_UNKNOWN + self.status_summary = STATUS_UNKNOWN + self.origin_name = STATUS_UNKNOWN + self.display_name = STATUS_UNKNOWN + self.air_flow = STATUS_UNKNOWN + self.led_status = COLOR_GREEN + + @property + def name(self): + return self.__name + + @property + def air_flow_monitor(self): + return self.__air_flow_monitor + + @abc.abstractmethod + def get_present(self): + """ + Gets the present status of PSU/FAN + + Returns: + A string, e.g. 'PRESENT, ABSENT, FAILED' + """ + raise NotImplementedError + + @abc.abstractmethod + def get_status(self): + """ + Gets the status of PSU/FAN + + Returns: + A string, e.g. 'OK, NOT OK, FAILED' + """ + raise NotImplementedError + + @abc.abstractmethod + def update_dev_info(self): + """ + update status and fru info of PSU/FAN + + include present, status, status_summary, part_model_name, product_name, air_flow + """ + raise NotImplementedError + + @abc.abstractmethod + def set_module_led(self, color): + """ + set PSU/FAN module LED status + + Args: + color: A string representing the color with which to set the + PSU/FAN module LED status + + Returns: + bool: True if status LED state is set successfully, False if not + """ + raise NotImplementedError + + +class DevPsu(DevBase): + + def __init__(self, name, air_flow_monitor, hal_interface): + super(DevPsu, self).__init__(name, air_flow_monitor) + self.int_case = hal_interface + + def get_psu_presence(self): + return self.int_case.get_psu_presence(self.name) + + def get_psu_input_output_status(self): + return self.int_case.get_psu_input_output_status(self.name) + + def get_psu_fru_info(self): + return self.int_case.get_psu_fru_info(self.name) + + @property + def na_ret(self): + return self.int_case.na_ret + + def get_present(self): + try: + status = self.get_psu_presence() + if status is True: + return STATUS_PRESENT + if status is False: + return STATUS_ABSENT + except Exception as e: + ledcontrol_error("get %s present status error, msg: %s" % (self.name, str(e))) + return STATUS_FAILED + + def get_status(self): + try: + status = self.get_psu_input_output_status() + if status is True: + return STATUS_OK + if status is False: + return STATUS_NOT_OK + except Exception as e: + ledcontrol_error("get %s status error, msg: %s" % (self.name, str(e))) + return STATUS_FAILED + + def update_dev_info(self): + try: + # update status + self.present = self.get_present() + if self.present != STATUS_PRESENT: + self.status = STATUS_UNKNOWN + self.status_summary = self.present + else: + self.status = self.get_status() + self.status_summary = self.status + # update fru info if need air flow monitor + if self.air_flow_monitor: + dic = self.get_psu_fru_info() + self.origin_name = dic["PN"] + self.air_flow = dic["AirFlow"] + self.display_name = dic["DisplayName"] + except Exception as e: + ledcontrol_error("update %s info error, msg: %s" % (self.name, str(e))) + self.present = STATUS_FAILED + self.status = STATUS_FAILED + self.status_summary = STATUS_FAILED + self.origin_name = self.na_ret + self.air_flow = self.na_ret + self.display_name = self.na_ret + + def set_module_led(self, color): + """ + set PSU module LED is not support, always return True + """ + return True + + +class DevFan(DevBase): + + def __init__(self, name, air_flow_monitor, hal_interface): + super(DevFan, self).__init__(name, air_flow_monitor) + self.int_case = hal_interface + + def get_fan_rotor_number(self): + return self.int_case.get_fan_rotor_number(self.name) + + def get_fan_presence(self): + return self.int_case.get_fan_presence(self.name) + + def get_fan_rotor_status(self, rotor_name): + return self.int_case.get_fan_rotor_status(self.name, rotor_name) + + def get_fan_fru_info(self): + return self.int_case.get_fan_fru_info(self.name) + + @property + def na_ret(self): + return self.int_case.na_ret + + def get_present(self): + try: + status = self.get_fan_presence() + if status is True: + return STATUS_PRESENT + if status is False: + return STATUS_ABSENT + except Exception as e: + ledcontrol_error("get %s present status error, msg: %s" % (self.name, str(e))) + return STATUS_FAILED + + def get_status(self): + try: + rotor_num = self.get_fan_rotor_number() + err_motor_num = 0 + for j in range(rotor_num): + rotor_name = "Rotor" + str(j + 1) + roll_status = self.get_fan_rotor_status(rotor_name) + if roll_status is not True: + err_motor_num += 1 + ledcontrol_debug("%s %s error, status %s" % (self.name, rotor_name, roll_status)) + else: + ledcontrol_debug("%s %s ok" % (self.name, rotor_name)) + if err_motor_num > 0: + return STATUS_NOT_OK + return STATUS_OK + except Exception as e: + ledcontrol_error("get %s status error, msg: %s" % (self.name, str(e))) + return STATUS_FAILED + + def update_dev_info(self): + try: + # update status + self.present = self.get_present() + if self.present != STATUS_PRESENT: + self.status = STATUS_UNKNOWN + self.status_summary = self.present + else: + self.status = self.get_status() + self.status_summary = self.status + # update fru info if need air flow monitor + if self.air_flow_monitor: + dic = self.get_fan_fru_info() + self.origin_name = dic["PN"] + self.air_flow = dic["AirFlow"] + self.display_name = dic["DisplayName"] + except Exception as e: + ledcontrol_error("update %s fru info error, msg: %s" % (self.name, str(e))) + self.present = STATUS_FAILED + self.status = STATUS_FAILED + self.status_summary = STATUS_FAILED + self.origin_name = self.na_ret + self.air_flow = self.na_ret + self.display_name = self.na_ret + + def set_module_led(self, color): + ret = self.int_case.set_fan_led(self.name, color) + if ret == 0: + return True + return False + + +class ledcontrol(object): + + def __init__(self): + self.fan_obj_list = [] + self.psu_obj_list = [] + self.board_psu_led_status = COLOR_GREEN + self.board_fan_led_status = COLOR_GREEN + self.__board_air_flow = "" + self.int_case = interface() + self.__config = baseutil.get_monitor_config() + self.__temps_threshold_config = self.__config["temps_threshold"] + for temp_threshold in self.__temps_threshold_config.values(): + temp_threshold['temp'] = 0 + temp_threshold['fail_num'] = 0 + self.__ledcontrol_para = self.__config["ledcontrol_para"] + self.__interval = self.__ledcontrol_para.get("interval", 5) + self.__checkpsu = self.__ledcontrol_para.get("checkpsu", 0) + self.__checkfan = self.__ledcontrol_para.get("checkfan", 0) + self.__psu_amber_num = self.__ledcontrol_para.get("psu_amber_num") + self.__fan_amber_num = self.__ledcontrol_para.get("fan_amber_num") + self.__psu_air_flow_amber_num = self.__ledcontrol_para.get("psu_air_flow_amber_num", 0) + self.__fan_air_flow_amber_num = self.__ledcontrol_para.get("fan_air_flow_amber_num", 0) + self.__board_sys_led = self.__ledcontrol_para.get("board_sys_led", []) + self.__board_psu_led = self.__ledcontrol_para.get("board_psu_led", []) + self.__board_fan_led = self.__ledcontrol_para.get("board_fan_led", []) + self.__psu_air_flow_monitor = self.__ledcontrol_para.get("psu_air_flow_monitor", 0) + self.__fan_air_flow_monitor = self.__ledcontrol_para.get("fan_air_flow_monitor", 0) + self.__fan_mix_list = self.__ledcontrol_para.get("fan_mix_list", []) + + @property + def na_ret(self): + return self.int_case.na_ret + + @property + def checkpsu(self): + return self.__checkpsu + + @property + def checkfan(self): + return self.__checkfan + + @property + def psu_amber_num(self): + return self.__psu_amber_num + + @property + def fan_amber_num(self): + return self.__fan_amber_num + + @property + def psu_air_flow_amber_num(self): + return self.__psu_air_flow_amber_num + + @property + def fan_air_flow_amber_num(self): + return self.__fan_air_flow_amber_num + + @property + def psu_air_flow_monitor(self): + return self.__psu_air_flow_monitor + + @property + def fan_air_flow_monitor(self): + return self.__fan_air_flow_monitor + + @property + def board_sys_led(self): + return self.__board_sys_led + + @property + def board_psu_led(self): + return self.__board_psu_led + + @property + def board_fan_led(self): + return self.__board_fan_led + + @property + def fan_mix_list(self): + return self.__fan_mix_list + + @property + def interval(self): + return self.__interval + + def get_fan_total_number(self): + return self.int_case.get_fan_total_number() + + def get_psu_total_number(self): + return self.int_case.get_psu_total_number() + + def get_onie_e2_obj(self, name): + return self.int_case.get_onie_e2_obj(name) + + def set_led_color(self, led_name, color): + try: + ret = self.int_case.set_led_color(led_name, color) + except Exception as e: + ledcontrol_error("set %s led %s error, msg: %s" % (led_name, color, str(e))) + ret = False + return ret + + def set_sys_led(self, color): + for led in self.board_sys_led: + led_name = led.get("led_name") + ret = self.set_led_color(led_name, color) + if ret is True: + ledcontrol_debug("set %s success, color:%s," % (led_name, color)) + else: + ledcontrol_debug("set %s failed, color:%s," % (led_name, color)) + + def set_psu_led(self, color): + for led in self.board_psu_led: + led_name = led.get("led_name") + ret = self.set_led_color(led_name, color) + if ret is True: + ledcontrol_debug("set %s success, color:%s," % (led_name, color)) + else: + ledcontrol_debug("set %s failed, color:%s," % (led_name, color)) + + def set_fan_led(self, color): + for led in self.board_fan_led: + led_name = led.get("led_name") + ret = self.set_led_color(led_name, color) + if ret is True: + ledcontrol_debug("set %s success, color:%s," % (led_name, color)) + else: + ledcontrol_debug("set %s failed, color:%s," % (led_name, color)) + + def set_fan_module_led(self): + for fan_obj in self.fan_obj_list: + color = LED_STATUS_DICT.get(fan_obj.led_status) + ret = fan_obj.set_module_led(color) + if ret is True: + ledcontrol_debug("set %s module led success, color: %s," % (fan_obj.name, color)) + else: + ledcontrol_debug("set %s module led failed, color: %s," % (fan_obj.name, color)) + + @property + def board_air_flow(self): + air_flow_tuple = (F2B_AIR_FLOW, B2F_AIR_FLOW) + if self.__board_air_flow not in air_flow_tuple: + self.__board_air_flow = self.int_case.get_device_airflow(ONIE_E2_NAME) + ledcontrol_debug("board_air_flow: %s" % self.__board_air_flow) + return self.__board_air_flow + + def update_psu_info(self): + for psu_obj in self.psu_obj_list: + psu_obj.update_dev_info() + ledcontrol_debug("%s present: [%s], status: [%s] status_summary [%s]" % + (psu_obj.name, psu_obj.present, psu_obj.status, psu_obj.status_summary)) + if psu_obj.air_flow_monitor: + ledcontrol_debug("%s origin name: [%s], display name: [%s] air flow [%s]" % + (psu_obj.name, psu_obj.origin_name, psu_obj.display_name, psu_obj.air_flow)) + + def update_fan_info(self): + for fan_obj in self.fan_obj_list: + fan_obj.update_dev_info() + ledcontrol_debug("%s present: [%s], status: [%s] status_summary [%s]" % + (fan_obj.name, fan_obj.present, fan_obj.status, fan_obj.status_summary)) + if fan_obj.air_flow_monitor: + ledcontrol_debug("%s origin name: [%s], display name: [%s] air flow [%s]" % + (fan_obj.name, fan_obj.origin_name, fan_obj.display_name, fan_obj.air_flow)) + + def get_monitor_temp(self): + sensorlist = self.int_case.get_temp_info() + + for temp_threshold in self.__temps_threshold_config.values(): + sensor = sensorlist.get(temp_threshold['name']) + if sensor["Value"] is None: + temp_threshold['fail_num'] += 1 + ledcontrol_error("get %s failed, fail_num = %d" % (temp_threshold['name'], temp_threshold['fail_num'])) + else: + temp_threshold['fail_num'] = 0 + temp_threshold.setdefault('fix', 0) + temp_threshold['temp'] = sensor["Value"] + temp_threshold['fix'] + ledcontrol_debug("%s = %d" % (temp_threshold['name'], temp_threshold['temp'])) + ledcontrol_debug("warning = %d, critical = %d" % (temp_threshold['warning'], temp_threshold['critical'])) + + def is_temp_warning(self): + warning_flag = False + for temp_threshold in self.__temps_threshold_config.values(): + if temp_threshold['temp'] >= temp_threshold['warning']: + warning_flag = True + ledcontrol_debug("%s is over warning" % temp_threshold['name']) + ledcontrol_debug( + "%s = %d, warning = %d" % + (temp_threshold['name'], + temp_threshold['temp'], + temp_threshold['warning'])) + return warning_flag + + def checkTempWarning(self): + try: + if self.is_temp_warning(): + ledcontrol_debug("temp is over warning") + return True + except Exception as e: + ledcontrol_error("%%policy: checkTempWarning failed") + ledcontrol_error(str(e)) + return False + + def is_temp_critical(self): + critical_flag = False + for temp_threshold in self.__temps_threshold_config.values(): + temp_threshold['critical_flag'] = False + if temp_threshold['temp'] >= temp_threshold['critical']: + critical_flag = True + temp_threshold['critical_flag'] = True + ledcontrol_debug("%s is over critical" % temp_threshold['name']) + ledcontrol_debug( + "%s = %d, critical = %d" % + (temp_threshold['name'], + temp_threshold['temp'], + temp_threshold['critical'])) + return critical_flag + + def checkTempCrit(self): + try: + if self.is_temp_critical(): + temp_dict = dict(self.__temps_threshold_config) + tmp = temp_dict.get(SWITCH_TEMP) + if tmp['critical_flag'] is True: + ledcontrol_debug("temp is over critical") + return True + + del temp_dict[SWITCH_TEMP] + for temp_items in temp_dict.values(): + if temp_items['critical_flag'] is False: + return False + + ledcontrol_debug("temp is over critical") + return True + except Exception as e: + ledcontrol_error("%%policy: checkTempCrit failed") + ledcontrol_error(str(e)) + return False + + def check_board_air_flow(self): + board_air_flow = self.board_air_flow + air_flow_tuple = (F2B_AIR_FLOW, B2F_AIR_FLOW) + if board_air_flow not in air_flow_tuple: + air_flow_error("%%AIR_FLOW_MONITOR-3-BOARD: Get board air flow failed, value: %s." % board_air_flow) + return False + ledcontrol_debug("board air flow check ok: %s" % board_air_flow) + return True + + def get_monitor_fan_status(self): + fanerrnum = 0 + for fan_obj in self.fan_obj_list: + status = fan_obj.status_summary + ledcontrol_debug("%s status: %s" % (fan_obj.name, status)) + if status != STATUS_OK: + fan_obj.led_status = COLOR_RED + fanerrnum += 1 + else: + fan_obj.led_status = COLOR_GREEN + ledcontrol_debug("fan error number: %d" % fanerrnum) + + if fanerrnum == 0: + fan_led_status = COLOR_GREEN + elif fanerrnum <= self.fan_amber_num: + fan_led_status = COLOR_AMBER + else: + fan_led_status = COLOR_RED + ledcontrol_debug("monitor fan status, set fan led: %s" % LED_STATUS_DICT.get(fan_led_status)) + return fan_led_status + + def get_monitor_psu_status(self): + psuerrnum = 0 + for psu_obj in self.psu_obj_list: + status = psu_obj.status_summary + ledcontrol_debug("%s status: %s" % (psu_obj.name, status)) + if status != STATUS_OK: + psu_obj.led_status = COLOR_RED + psuerrnum += 1 + else: + psu_obj.led_status = COLOR_GREEN + ledcontrol_debug("psu error number: %d" % psuerrnum) + + if psuerrnum == 0: + psu_led_status = COLOR_GREEN + elif psuerrnum <= self.psu_amber_num: + psu_led_status = COLOR_AMBER + else: + psu_led_status = COLOR_RED + ledcontrol_debug("monitor psu status, set psu led: %s" % LED_STATUS_DICT.get(psu_led_status)) + return psu_led_status + + def get_monitor_fan_air_flow(self): + if self.fan_air_flow_monitor == 0: + ledcontrol_debug("fan air flow monitor not open, default green") + return COLOR_GREEN + + ret = self.check_board_air_flow() + if ret is False: + ledcontrol_debug("check board air flow error, skip fan air flow monitor.") + return COLOR_GREEN + + fan_led_status_list = [] + fan_air_flow_ok_obj_list = [] + fan_air_flow_ok_set = set() + fan_module_led_list = [] + fan_air_flow_err_num = 0 + for fan_obj in self.fan_obj_list: + if fan_obj.present != STATUS_PRESENT: + fan_module_led_list.append(COLOR_GREEN) + continue + if fan_obj.air_flow == self.na_ret: + air_flow_warn("%%AIR_FLOW_MONITOR-4-FAN: %s get air flow failed, fan model: %s, air flow: %s." % + (fan_obj.name, fan_obj.display_name, fan_obj.air_flow)) + led_status = COLOR_AMBER + fan_module_led_list.append(led_status) + elif fan_obj.air_flow != self.board_air_flow: + air_flow_emerg("%%AIR_FLOW_MONITOR-0-FAN: %s air flow error, fan model: %s, fan air flow: %s, board air flow: %s." % + (fan_obj.name, fan_obj.display_name, fan_obj.air_flow, self.board_air_flow)) + led_status = COLOR_RED + fan_air_flow_err_num += 1 + else: + fan_air_flow_ok_obj_list.append(fan_obj) + fan_air_flow_ok_set.add(fan_obj.origin_name) + ledcontrol_debug("%s air flow check ok, origin name: [%s], display name: [%s], fan air flow: [%s], board air flow: [%s]" % + (fan_obj.name, fan_obj.origin_name, fan_obj.display_name, fan_obj.air_flow, self.board_air_flow)) + led_status = COLOR_GREEN + fan_module_led_list.append(led_status) + if led_status > fan_obj.led_status: + fan_obj.led_status = led_status + if len(fan_module_led_list) != 0: + fan_led_status = max(fan_module_led_list) + fan_led_status_list.append(fan_led_status) + # check fan mixing + if len(fan_air_flow_ok_set) > 1 and fan_air_flow_ok_set not in self.fan_mix_list: + for fan_obj in fan_air_flow_ok_obj_list: + air_flow_warn("%%AIR_FLOW_MONITOR-4-FAN: %s mixing, fan model: %s, air flow: %s." % + (fan_obj.name, fan_obj.origin_name, fan_obj.air_flow)) + fan_led_status = COLOR_AMBER + fan_led_status_list.append(fan_led_status) + # check fan air flow error number + if fan_air_flow_err_num == 0: + fan_led_status = COLOR_GREEN + elif fan_air_flow_err_num <= self.fan_air_flow_amber_num: + fan_led_status = COLOR_AMBER + else: + fan_led_status = COLOR_RED + fan_led_status_list.append(fan_led_status) + + fan_led_status = max(fan_led_status_list) + ledcontrol_debug("monitor fan air flow, set fan led: %s" % LED_STATUS_DICT.get(fan_led_status)) + return fan_led_status + + def get_monitor_psu_air_flow(self): + if self.psu_air_flow_monitor == 0: + ledcontrol_debug("psu air flow monitor not open, default green") + return COLOR_GREEN + + ret = self.check_board_air_flow() + if ret is False: + ledcontrol_debug("check board air flow error, skip psu air flow monitor.") + return COLOR_GREEN + + psu_led_status_list = [] + psu_module_led_list = [] + psu_air_flow_err_num = 0 + for psu_obj in self.psu_obj_list: + if psu_obj.present != STATUS_PRESENT: + psu_module_led_list.append(COLOR_GREEN) + continue + if psu_obj.air_flow == self.na_ret: + air_flow_warn("%%AIR_FLOW_MONITOR-4-PSU: %s get air flow failed, psu model: %s, air flow: %s." % + (psu_obj.name, psu_obj.display_name, psu_obj.air_flow)) + led_status = COLOR_AMBER + psu_module_led_list.append(led_status) + elif psu_obj.air_flow != self.board_air_flow: + air_flow_emerg("%%AIR_FLOW_MONITOR-0-PSU: %s air flow error, psu model: %s, psu air flow: %s, board air flow: %s." % + (psu_obj.name, psu_obj.display_name, psu_obj.air_flow, self.board_air_flow)) + led_status = COLOR_RED + psu_air_flow_err_num += 1 + else: + ledcontrol_debug("%s psu air flow check ok, origin name: [%s], display name: [%s], psu air flow: [%s], board air flow: [%s]" % + (psu_obj.name, psu_obj.origin_name, psu_obj.display_name, psu_obj.air_flow, self.board_air_flow)) + led_status = COLOR_GREEN + psu_module_led_list.append(led_status) + if led_status > psu_obj.led_status: + psu_obj.led_status = led_status + + if len(psu_module_led_list) != 0: + psu_led_status = max(psu_module_led_list) + psu_led_status_list.append(psu_led_status) + + # check fan air flow error number + if psu_air_flow_err_num == 0: + psu_led_status = COLOR_GREEN + elif psu_air_flow_err_num <= self.psu_air_flow_amber_num: + psu_led_status = COLOR_AMBER + else: + psu_led_status = COLOR_RED + psu_led_status_list.append(psu_led_status) + + psu_led_status = max(psu_led_status_list) + ledcontrol_debug("monitor psu air flow, set psu led: %s" % LED_STATUS_DICT.get(psu_led_status)) + return psu_led_status + + def get_temp_sys_led_status(self): + if self.checkTempCrit() is True: + sys_led_status = COLOR_RED + elif self.checkTempWarning() is True: + sys_led_status = COLOR_AMBER + else: + sys_led_status = COLOR_GREEN + ledcontrol_debug("monitor temperature, set sys led: %s" % LED_STATUS_DICT.get(sys_led_status)) + return sys_led_status + + def get_sys_led_follow_fan_status(self): + + if self.checkfan: + sys_led_status = self.board_fan_led_status + ledcontrol_debug("sys led follow fan led, set sys led: %s" % LED_STATUS_DICT.get(sys_led_status)) + else: + sys_led_status = COLOR_GREEN + ledcontrol_debug("sys led don't follow fan led, set default green") + return sys_led_status + + def get_sys_led_follow_psu_status(self): + if self.checkpsu: + sys_led_status = self.board_psu_led_status + ledcontrol_debug("sys led follow psu led, set sys led: %s" % LED_STATUS_DICT.get(sys_led_status)) + else: + sys_led_status = COLOR_GREEN + ledcontrol_debug("sys led don't follow psu led, set default green") + return sys_led_status + + def dealSysLedStatus(self): + sys_led_status_list = [] + # get_monitor_temp + self.get_monitor_temp() + + # monitor temp get sys led status + sys_led_status = self.get_temp_sys_led_status() + sys_led_status_list.append(sys_led_status) + + # check sys led follow fan led status + sys_led_status = self.get_sys_led_follow_fan_status() + sys_led_status_list.append(sys_led_status) + + # check sys led follow psu led status + sys_led_status = self.get_sys_led_follow_psu_status() + sys_led_status_list.append(sys_led_status) + + sys_led_status = max(sys_led_status_list) + sys_led_color = LED_STATUS_DICT.get(sys_led_status) + + # set sys led + self.set_sys_led(sys_led_color) + + def dealFanLedStatus(self): + fan_led_status_list = [] + # update fan info + self.update_fan_info() + + # monitor fan status first + fan_led_status = self.get_monitor_fan_status() + fan_led_status_list.append(fan_led_status) + + # monitor fan air flow + fan_led_status = self.get_monitor_fan_air_flow() + fan_led_status_list.append(fan_led_status) + + self.board_fan_led_status = max(fan_led_status_list) + fan_led_color = LED_STATUS_DICT.get(self.board_fan_led_status) + + # set fan led + self.set_fan_led(fan_led_color) + # set fan module led + self.set_fan_module_led() + + def dealPsuLedStatus(self): + psu_led_status_list = [] + # update psu info + self.update_psu_info() + + # monitor psu status first + psu_led_status = self.get_monitor_psu_status() + psu_led_status_list.append(psu_led_status) + + # monitor psu air flow + psu_led_status = self.get_monitor_psu_air_flow() + psu_led_status_list.append(psu_led_status) + + self.board_psu_led_status = max(psu_led_status_list) + psu_led_color = LED_STATUS_DICT.get(self.board_psu_led_status) + + # set psu led + self.set_psu_led(psu_led_color) + + def do_ledcontrol(self): + self.dealPsuLedStatus() + self.dealFanLedStatus() + self.dealSysLedStatus() + + def fan_obj_init(self): + fan_num = self.get_fan_total_number() + for i in range(fan_num): + fan_name = "FAN" + str(i + 1) + fan_obj = DevFan(fan_name, self.fan_air_flow_monitor, self.int_case) + self.fan_obj_list.append(fan_obj) + ledcontrol_debug("fan object initialize success") + + def psu_obj_init(self): + psu_num = self.get_psu_total_number() + for i in range(psu_num): + psu_name = "PSU" + str(i + 1) + psu_obj = DevPsu(psu_name, self.psu_air_flow_monitor, self.int_case) + self.psu_obj_list.append(psu_obj) + ledcontrol_debug("psu object initialize success") + + def run(self): + while True: + try: + debug_init() + self.do_ledcontrol() + time.sleep(self.interval) + except Exception as e: + traceback.print_exc() + ledcontrol_error(str(e)) + + +if __name__ == '__main__': + debug_init() + ledcontrol_debug("enter main") + led_control = ledcontrol() + led_control.fan_obj_init() + led_control.psu_obj_init() + led_control.run() diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/script/hal_pltfm.py b/platform/broadcom/sonic-platform-modules-ragile/common/script/hal_pltfm.py new file mode 100755 index 000000000000..766152256810 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/script/hal_pltfm.py @@ -0,0 +1,492 @@ +#!/usr/bin/env python3 +# -*- coding: UTF-8 -*- +import inspect +import sys +import json +import time +from plat_hal.interface import interface + + +class Command(): + def __init__(self, name, f): + self.name = name + self.f = f + self.paramcount = self.f.__code__.co_argcount + + def dofun(self, args): + fn = self.f.__call__ + fn(*args) + + +class Group(): + def __init__(self, name, f): + self.groups = [] + self.commands = [] + self.name = name + self.f = f + + def add_groups(self, command): + self.groups.append(command) + + def add_commands(self, commnad): + x = Command(commnad.__name__, commnad) + self.commands.append(x) + + def find_valuebyname(self, name): + for item in self.groups: + if name == item.name: + return item + for item in self.commands: + if name == item.name: + return item + return None + + def deal(self, args): + if len(args) <= 0: + return self.print_help() + funclevel = args[0] + val = self.find_valuebyname(funclevel) + if val is None: + return self.print_help() + if isinstance(val, Command): + if len(args) < (val.paramcount + 1): + return self.print_help() + inputargs = args[1: (1 + val.paramcount)] + return val.dofun(inputargs) + if isinstance(val, Group): + args = args[1:] + return val.deal(args) + return self.print_help() + + def get_max(self, arr): + lentmp = 0 + for ar in arr: + lentmp = len(ar) if (len(ar) > lentmp) else lentmp + return lentmp + + def print_help(self): + + namesize = [] + for item in self.groups: + namesize.append(item.name) + for item in self.commands: + namesize.append(item.name) + maxvalue = self.get_max(namesize) + + if len(self.groups) > 0: + print("Groups:") + for item in self.groups: + print(" %-*s %s" % (maxvalue, item.name, item.f.__doc__ or '')) + if len(self.commands) > 0: + print("Commands:") + for item in self.commands: + print(" %-*s %s" % (maxvalue, item.name, item.f.__doc__ or '')) + + +class clival(): + @staticmethod + def Fire(val=None): + group = Group("top", 'mainlevel') + clival.iterGroup(val, group) + # context = {} + # caller = inspect.stack()[1] + # caller_frame = caller[0] + # caller_globals = caller_frame.f_globals + # caller_locals = caller_frame.f_locals + # context.update(caller_globals) + # context.update(caller_locals) + args = sys.argv[1:] + group.deal(args) + + @staticmethod + def iterGroup(val, group): + for key, item in val.items(): + if item is None: # first level + if inspect.isfunction(key): + group.add_commands(key) + else: + group1 = Group(key.__name__, key) + clival.iterGroup(item, group1) + group.add_groups(group1) + + +def psu(): + r'''test psu ''' + + +def fan(): + r'''test fan ''' + + +def sensor(): + r'''test sensor ''' + + +def dcdc(): + r'''test dcdc ''' + + +def led(): + r'''test led ''' + + +def e2(): + r'''test onie eeprom ''' + + +def temps(): + r'''test temps sensor''' + +def cpu(): + r'''test cpu''' + + +int_case = interface() + + +def get_total_number(): + r'''psu get_total_number ''' + print("=================get_total_number======================") + print(int_case.get_psu_total_number()) + + +def get_presence(): + r'''psu get_presence ''' + print("=================get_presence======================") + psus = int_case.get_psus() + for psu_item in psus: + print(psu_item.name, end=' ') + print(int_case.get_psu_presence(psu_item.name)) + + +def get_fru_info(): + r'''psu get_fru_info ''' + print("=================get_fru_info======================") + psus = int_case.get_psus() + for psu_item in psus: + print(psu_item.name, end=' ') + print(json.dumps(int_case.get_psu_fru_info(psu_item.name), ensure_ascii=False, indent=4)) + + +def get_status(): + r'''psu get_status ''' + print("=================get_status======================") + psus = int_case.get_psus() + for psu_item in psus: + print(psu_item.name, end=' ') + print(json.dumps(int_case.get_psu_status(psu_item.name), ensure_ascii=False, indent=4)) + + +def set_psu_fan_speed_pwm(realspeed): + r'''set_psu_fan_speed_pwm''' + print("=================set_psu_fan_speed_pwm======================") + psus = int_case.get_psus() + for psu_item in psus: + print(psu_item.name, end=' ') + print(int_case.set_psu_fan_speed_pwm(psu_item.name, int(realspeed))) + + +def get_psu_fan_speed_pwm(): + r'''get_psu_fan_speed_pwm''' + print("=================get_psu_fan_speed_pwm======================") + psus = int_case.get_psus() + for psu_item in psus: + print(psu_item.name, end=' ') + print(json.dumps(int_case.get_psu_fan_speed_pwm(psu_item.name))) + + +def get_psu_power_status(): + r'''psu get_psu_power_status ''' + print("=================get_psu_power_status======================") + psus = int_case.get_psus() + for psu_item in psus: + print(psu_item.name, end=' ') + print(json.dumps(int_case.get_psu_power_status(psu_item.name), ensure_ascii=False, indent=4)) + + +def get_info_all(): + r'''psu get_info_all ''' + print("=================get_info_all======================") + print(json.dumps(int_case.get_psu_info_all(), ensure_ascii=False, indent=4)) + + +def fan_get_total_number(): + print("=================get_info_all======================") + print(json.dumps(int_case.get_fan_total_number(), ensure_ascii=False, indent=4)) + + +def fan_get_rotor_number(): + r'''fan_get_rotor_number''' + print("=================fan_get_rotor_number======================") + fans = int_case.get_fans() + for fan_item in fans: + print(fan_item.name, end=' ') + print(int_case.get_fan_rotor_number(fan_item.name)) + + +def fan_get_speed(): + r'''fan_get_speed''' + print("=================fan_get_speed======================") + fans = int_case.get_fans() + for fan_item in fans: + rotors = fan_item.rotor_list + for rotor in rotors: + index = rotors.index(rotor) + print("%s rotor%d" % (fan_item.name, index + 1), end=' ') + print(int_case.get_fan_speed(fan_item.name, index + 1)) + + +def fan_get_speed_pwm(): + r'''fan_get_speed_pwm''' + print("=================fan_get_speed_pwm======================") + fans = int_case.get_fans() + for fan_item in fans: + rotors = fan_item.rotor_list + for rotor in rotors: + index = rotors.index(rotor) + print("%s rotor%d" % (fan_item.name, index + 1), end=' ') + print(int_case.get_fan_speed_pwm(fan_item.name, index + 1)) + + +def fan_set_speed_pwm(pwm): + r'''fan_set_speed_pwm''' + print("=================fan_set_speed_pwm======================") + fans = int_case.get_fans() + for fan_item in fans: + rotors = fan_item.rotor_list + for rotor in rotors: + index = rotors.index(rotor) + print("%s %s" % (fan_item.name, rotor.name), end=' ') + val = int_case.set_fan_speed_pwm(fan_item.name, index + 1, pwm) + print(val) + + +def fan_get_watchdog_status(): + r'''fan_get_watchdog_status''' + print("=================fan_get_watchdog_status======================") + print(int_case.get_fan_watchdog_status()) + + +def fan_enable_watchdog(): + r'''fan_enable_watchdog''' + print("=================fan_enable_watchdog======================") + print('enable', int_case.enable_fan_watchdog()) + + +def fan_disable_watchdog(): + r'''fan_disable_watchdog''' + print("=================fan_disable_watchdog======================") + print('disable', int_case.enable_fan_watchdog(enable=False)) + + +def fan_get_speed1(): + r'''fan_get_speed''' + print("=================fan_get_speed======================") + fans = int_case.get_fans() + for fan_item in fans: + rotors = fan_item.rotor_list + for rotor in rotors: + print("%s %s" % (fan_item.name, rotor.name), end=' ') + print(int_case.get_fan_speed(fan_item.name, rotor.name)) + + +def fan_feed_watchdog(): + r'''fan_feed_watchdog''' + print("=================fan_feed_watchdog======================") + fan_get_speed() + print(int_case.feed_fan_watchdog()) + time.sleep(2) + fan_get_speed() + + +def fan_set_led(color): + r'''fan_set_led''' + print("=================fan_set_led======================") + fans = int_case.get_fans() + for fan_item in fans: + print("%s" % fan_item.name) + print(color, int_case.set_fan_led(fan_item.name, color)) + +def fan_get_led(): + r'''fan_get_led''' + print("=================fan_get_led======================") + fans = int_case.get_fans() + for fan_item in fans: + print("%s" % fan_item.name) + print(int_case.get_fan_led(fan_item.name)) + + +def fan_get_presence(): + r'''fan_get_presence''' + print("=================fan_get_presence======================") + fans = int_case.get_fans() + for fan_item in fans: + print("%s" % fan_item.name) + print(int_case.get_fan_presence(fan_item.name)) + + +def fan_get_fru_info(): + r'''fan_get_fru_info''' + print("=================fan_get_fru_info======================") + fans = int_case.get_fans() + for fan_item in fans: + print("%s" % fan_item.name) + print(json.dumps(int_case.get_fan_info(fan_item.name), ensure_ascii=False, indent=4)) + + +def fan_get_status(): + r'''fan_get_status''' + print("=================fan_get_status======================") + fans = int_case.get_fans() + for fan_item in fans: + print("%s" % fan_item.name) + print(json.dumps(int_case.get_fan_status(fan_item.name), ensure_ascii=False, indent=4)) + + +def fan_get_info_all(): + r'''fan_get_info_all''' + print("=================fan_get_info_all======================") + print(json.dumps(int_case.get_fan_info_all(), ensure_ascii=False, indent=4)) + + +def get_sensor_info(): + r'''get_sensor_info''' + print("=================get_sensor_info======================") + print(json.dumps(int_case.get_sensor_info(), ensure_ascii=False, indent=4)) + + +def get_dcdc_all_info(): + r'''get_dcdc_all_info''' + print("=================get_dcdc_all_info======================") + print(json.dumps(int_case.get_dcdc_all_info(), ensure_ascii=False, indent=4)) + + +def set_all_led_color(color): + r'''set_all_led_color color''' + print("=================set_all_led_color======================") + leds = int_case.get_leds() + for led_item in leds: + print("%s" % led_item.name) + print(color, int_case.set_led_color(led_item.name, color)) + + +def get_all_led_color(): + r'''get_all_led_color''' + print("=================get_all_led_color======================") + leds = int_case.get_leds() + for led_item in leds: + print("%s" % led_item.name) + print(int_case.get_led_color(led_item.name)) + + +def set_single_led_color(led_name, color): + r'''set_single_led_color led_name color''' + print("=================set_single_led_color======================") + leds = int_case.get_leds() + for led_item in leds: + if led_name == led_item.name: + print("%s" % led_item.name) + print(color, int_case.set_led_color(led_item.name, color)) + + +def get_single_led_color(led_name): + r'''get_single_led_color''' + print("=================get_single_led_color======================") + leds = int_case.get_leds() + for led_item in leds: + if led_name == led_item.name: + print("%s" % led_item.name) + print(int_case.get_led_color(led_item.name)) + + +def get_onie_e2_path(): + r'''get_onie_e2_path''' + print("=================get_onie_e2_path======================") + path = int_case.get_onie_e2_path("ONIE_E2") + print("%s" % path) + + +def get_device_airflow(): + r'''get_device_airflow''' + print("=================get_device_airflow======================") + airflow = int_case.get_device_airflow("ONIE_E2") + print("%s" % airflow) + + +def get_temps_sensor(): + r'''get_temps_sensor''' + print("=================get_temps_sensor======================") + temp_list = int_case.get_temps() + for temp in temp_list: + print("id: %s, name: %s, API name: %s, value: %s" % (temp.temp_id, temp.name, temp.api_name, temp.Value)) + +def get_cpu_reset_num(): + r'''get_cpu_reset_num''' + print("=================get_cpu_reset_num======================") + print(int_case.get_cpu_reset_num()) + +def get_cpu_reboot_cause(): + r'''get_cpu_reboot_cause''' + print("=================get_cpu_reboot_cause======================") + print(int_case.get_cpu_reboot_cause()) + + +def run_cli_man(): + clival.Fire( + { + psu: { + get_total_number: None, + get_presence: None, + get_fru_info: None, + set_psu_fan_speed_pwm: None, + get_psu_fan_speed_pwm: None, + get_status: None, + get_psu_power_status: None, + get_info_all: None + }, + fan: { + fan_get_total_number: None, + fan_get_rotor_number: None, + fan_get_speed: None, + fan_get_speed_pwm: None, + fan_set_speed_pwm: None, + fan_get_watchdog_status: None, + fan_enable_watchdog: None, + fan_disable_watchdog: None, + fan_feed_watchdog: None, + fan_set_led: None, + fan_get_led: None, + fan_get_presence: None, + fan_get_fru_info: None, + fan_get_status: None, + fan_get_info_all: None + }, + sensor: { + get_sensor_info: None + }, + dcdc: { + get_dcdc_all_info: None + }, + led: { + set_all_led_color: None, + set_single_led_color: None, + get_all_led_color: None, + get_single_led_color: None, + }, + e2: { + get_onie_e2_path: None, + get_device_airflow: None, + }, + temps: { + get_temps_sensor: None, + }, + cpu: { + get_cpu_reset_num: None, + get_cpu_reboot_cause: None, + } + } + ) + + +if __name__ == '__main__': + run_cli_man() diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/script/intelligent_monitor.py b/platform/broadcom/sonic-platform-modules-ragile/common/script/intelligent_monitor.py new file mode 100755 index 000000000000..33d5bfba64e6 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/script/intelligent_monitor.py @@ -0,0 +1,144 @@ +#!/usr/bin/python3 +# -*- coding: UTF-8 -*- + +import os +import time +import syslog +from plat_hal.interface import interface +from plat_hal.baseutil import baseutil +from platform_util import io_rd, wbi2cget + +INTELLIGENT_MONITOR_DEBUG_FILE = "/etc/.intelligent_monitor_debug" + +debuglevel = 0 + + +def monitor_syslog_debug(s): + if debuglevel: + syslog.openlog("INTELLIGENT_MONITOR_DEBUG", syslog.LOG_PID) + syslog.syslog(syslog.LOG_DEBUG, s) + + +def monitor_syslog(s): + syslog.openlog("INTELLIGENT_MONITOR", syslog.LOG_PID) + syslog.syslog(syslog.LOG_WARNING, s) + + +def pmon_syslog_notice(s): + syslog.openlog("PMON_SYSLOG", syslog.LOG_PID) + syslog.syslog(syslog.LOG_NOTICE, s) + + +class IntelligentMonitor(): + def __init__(self): + self.dcdc_dict = {} + self.int_case = interface() + self.__config = baseutil.get_monitor_config() + self.__intelligent_monitor_para = self.__config.get('intelligent_monitor_para', {}) + self.__interval = self.__intelligent_monitor_para.get('interval', 60) + self.__dcdc_whitelist = self.__config.get('dcdc_monitor_whitelist', {}) + self.__error_ret = self.int_case.error_ret + + @property + def error_ret(self): + return self.__error_ret + + @property + def interval(self): + return self.__interval + + def debug_init(self): + global debuglevel + if os.path.exists(INTELLIGENT_MONITOR_DEBUG_FILE): + debuglevel = 1 + else: + debuglevel = 0 + + def dcdc_whitelist_check(self, dcdc_name): + try: + check_item = self.__dcdc_whitelist.get(dcdc_name, {}) + if len(check_item) == 0: + return False + gettype = check_item.get("gettype", None) + checkbit = check_item.get("checkbit", None) + okval = check_item.get("okval", None) + if gettype is None or checkbit is None or okval is None: + monitor_syslog('%%INTELLIGENT_MONITOR-3-DCDC_WHITELIST_FAILED: %s config error. gettype:%s, checkbit:%s, okval:%s' % + (dcdc_name, gettype, checkbit, okval)) + return False + if gettype == "io": + io_addr = check_item.get('io_addr', None) + val = io_rd(io_addr) + if val is not None: + retval = val + else: + monitor_syslog( + '%%INTELLIGENT_MONITOR-3-DCDC_WHITELIST_FAILED: %s io_rd error. io_addr:%s' % + (dcdc_name, io_addr)) + return False + elif gettype == "i2c": + bus = check_item.get('bus', None) + addr = check_item.get('addr', None) + offset = check_item.get('offset', None) + ind, val = wbi2cget(bus, addr, offset) + if ind is True: + retval = val + else: + monitor_syslog('%%INTELLIGENT_MONITOR-3-DCDC_WHITELIST_FAILED: %s i2cget error. bus:%s, addr:%s, offset:%s' % + (dcdc_name, bus, addr, offset)) + return False + else: + monitor_syslog('%%INTELLIGENT_MONITOR-3-DCDC_WHITELIST_FAILED: %s gettype not support' % dcdc_name) + return False + + val_t = (int(retval, 16) & (1 << checkbit)) >> checkbit + if val_t != okval: + return False + return True + except Exception as e: + monitor_syslog('%%WHITELIST_CHECK: %s check error, msg: %s.' % (dcdc_name, str(e))) + return False + + def update_dcdc_status(self): + try: + self.dcdc_dict = self.int_case.get_dcdc_all_info() + for dcdc_name, item in self.dcdc_dict.items(): + ret = self.dcdc_whitelist_check(dcdc_name) + if ret is False: + if item['Value'] == self.error_ret: + monitor_syslog( + '%%INTELLIGENT_MONITOR-3-DCDC_SENSOR_FAILED: The value of %s read failed.' % + (dcdc_name)) + elif float(item['Value']) > float(item['Max']): + pmon_syslog_notice('%%PMON-5-VOLTAGE_HIGH: %s voltage %.3f%s is larger than max threshold %.3f%s.' % + (dcdc_name, float(item['Value']), item['Unit'], float(item['Max']), item['Unit'])) + elif float(item['Value']) < float(item['Min']): + pmon_syslog_notice('%%PMON-5-VOLTAGE_LOW: %s voltage %.3f%s is lower than min threshold %.3f%s.' % + (dcdc_name, float(item['Value']), item['Unit'], float(item['Min']), item['Unit'])) + else: + monitor_syslog_debug('%%INTELLIGENT_MONITOR-6-DCDC_SENSOR_OK: %s normal, value is %.3f%s.' % + (dcdc_name, item['Value'], item['Unit'])) + else: + monitor_syslog_debug( + '%%INTELLIGENT_MONITOR-6-DCDC_WHITELIST_CHECK: %s is in dcdc whitelist, not monitor voltage' % + dcdc_name) + continue + except Exception as e: + monitor_syslog('%%INTELLIGENT_MONITOR-3-EXCEPTION: update dcdc sensors status error, msg: %s.' % (str(e))) + + def doWork(self): + self.update_dcdc_status() + + def run(self): + while True: + try: + self.debug_init() + self.doWork() + time.sleep(self.interval) + except Exception as e: + monitor_syslog('%%INTELLIGENT_MONITOR-3-EXCEPTION: %s.' % (str(e))) + + +if __name__ == '__main__': + intelligent_monitor = IntelligentMonitor() + intelligent_monitor.run() diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/script/intelligent_monitor/monitor_fan.py b/platform/broadcom/sonic-platform-modules-ragile/common/script/intelligent_monitor/monitor_fan.py new file mode 100755 index 000000000000..c84319f3b798 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/script/intelligent_monitor/monitor_fan.py @@ -0,0 +1,284 @@ +#!/usr/bin/python3 +# -*- coding: UTF-8 -*- + +import os +import time +import logging +from logging.handlers import RotatingFileHandler + +from plat_hal.interface import interface +from plat_hal.baseutil import baseutil + + +DEBUG_FILE = "/etc/.monitor_fan_debug_flag" + +LOG_FILE = "/var/log/intelligent_monitor/monitor_fan_log" + +E2_NAME = "ONIE_E2" + + +def _init_logger(): + if not os.path.exists(LOG_FILE): + os.system("mkdir -p %s" % os.path.dirname(LOG_FILE)) + os.system("sync") + handler = RotatingFileHandler(filename=LOG_FILE, maxBytes=5 * 1024 * 1024, backupCount=1) + formatter = logging.Formatter("%(asctime)s %(levelname)s %(filename)s[%(funcName)s][%(lineno)s]: %(message)s") + handler.setFormatter(formatter) + logger = logging.getLogger(__name__) + logger.setLevel(logging.INFO) + logger.addHandler(handler) + return logger + + +class Fan(object): + + def __init__(self, name, hal_interface): + self.name = name + self.fan_dict = {} + self.int_case = hal_interface + self.update_time = 0 + self.pre_present = False + self.pre_status = True + self.plugin_cnt = 0 + self.plugout_cnt = 0 + self.status_normal_cnt = 0 + self.status_error_cnt = 0 + + def fan_dict_update(self): + local_time = time.time() + if not self.fan_dict or (local_time - self.update_time) >= 1: # update data every 1 seconds + self.update_time = local_time + self.fan_dict = self.int_case.get_fan_info(self.name) + + def get_model(self): + self.fan_dict_update() + return self.fan_dict["NAME"] + + def get_serial(self): + self.fan_dict_update() + return self.fan_dict["SN"] + + def get_presence(self): + return self.int_case.get_fan_presence(self.name) + + def get_rotor_speed(self, rotor_name): + """ + Retrieves the speed of fan as a percentage of full speed + + Returns: + An integer, the percentage of full fan speed, in the range 0 (off) + to 100 (full speed) + """ + fan_dir = {} + fan_dir = self.int_case.get_fan_info_rotor(self.name) + # get fan rotor pwm + value = fan_dir[rotor_name]["Speed"] + max_speed = fan_dir[rotor_name]["SpeedMax"] + + if isinstance(value, str) or value is None: + return 0 + pwm = value * 100 / max_speed + if pwm > 100: + pwm = 100 + elif pwm < 0: + pwm = 0 + return int(pwm) + + def get_rotor_speed_tolerance(self, rotor_name): + """ + Retrieves the speed tolerance of the fan + Returns: + An integer, the percentage of variance from target speed which is + considered tolerable + """ + # The default tolerance value is fixed as 30% + fan_dir = {} + fan_dir = self.int_case.get_fan_info_rotor(self.name) + # get fan rotor tolerance + tolerance = fan_dir[rotor_name]["Tolerance"] + + if isinstance(tolerance, str) or tolerance is None: + return 30 + return tolerance + + def get_target_speed(self): + """ + Retrieves the target (expected) speed of the fan + Returns: + An integer, the percentage of full fan speed, in the range 0 (off) + to 100 (full speed) + """ + pwm = self.int_case.get_fan_speed_pwm(self.name, 0) + return int(pwm) + + def get_status(self): + """ + Retrieves the operational status of the FAN + Returns: + bool: True if FAN is operating properly, False if not + """ + if not self.get_presence(): + return False + + rotor_num = self.int_case.get_fan_rotor_number(self.name) + for i in range(rotor_num): + rotor_name = "Rotor" + str(i + 1) + speed = self.get_rotor_speed(rotor_name) + tolerance = self.get_rotor_speed_tolerance(rotor_name) + target = self.get_target_speed() + if (speed - target) > target * tolerance / 100: + return False + if (target - speed) > target * tolerance / 100: + return False + + return True + + def get_direction(self): + """ + Retrieves the fan airflow direction + Returns: + A string, either FAN_DIRECTION_INTAKE or FAN_DIRECTION_EXHAUST + depending on fan direction + + Notes: + - Forward/Exhaust : Air flows from Port side to Fan side. + - Reverse/Intake : Air flows from Fan side to Port side. + """ + self.fan_dict_update() + return self.fan_dict["AirFlow"] + + +class MonitorFan(object): + + def __init__(self): + self.int_case = interface() + self.logger = _init_logger() + self.fan_obj_list = [] + self.__config = baseutil.get_monitor_config() + self.__monitor_fan_config = self.__config.get("monitor_fan_para", {}) + self.__present_interval = self.__monitor_fan_config.get("present_interval", 0.5) + self.__status_interval = self.__monitor_fan_config.get("status_interval", 5) + self.__present_check_cnt = self.__monitor_fan_config.get("present_check_cnt", 3) + self.__status_check_cnt = self.__monitor_fan_config.get("status_check_cnt", 3) + + def debug_init(self): + if os.path.exists(DEBUG_FILE): + self.logger.setLevel(logging.DEBUG) + else: + self.logger.setLevel(logging.INFO) + + def get_fan_total_number(self): + return self.int_case.get_fan_total_number() + + def get_device_airflow(self): + return self.int_case.get_device_airflow(E2_NAME) + + def fan_obj_init(self): + fan_num = self.get_fan_total_number() + for i in range(fan_num): + fan_name = "FAN" + str(i + 1) + fan_obj = Fan(fan_name, self.int_case) + self.fan_obj_list.append(fan_obj) + self.logger.info("fan object initialize success") + + def fan_airflow_check(self, fan_obj): + fan_airflow = fan_obj.get_direction() + device_airflow = self.get_device_airflow() + if fan_airflow != device_airflow: + self.logger.error("%s airflow[%s] not match device airflow[%s]", fan_obj.name, fan_airflow, device_airflow) + else: + self.logger.debug("%s airflow[%s] match device airflow[%s]", fan_obj.name, fan_airflow, device_airflow) + + def fan_plug_in_out_check(self, fan_obj): + present = fan_obj.get_presence() + if present is True: + self.logger.debug("%s is present", fan_obj.name) + else: + self.logger.debug("%s is absent", fan_obj.name) + + if present != fan_obj.pre_present: + if present is True: + fan_obj.plugin_cnt += 1 + fan_obj.plugout_cnt = 0 + if fan_obj.plugin_cnt >= self.__present_check_cnt: + fan_obj.pre_present = True + self.logger.info("%s [serial:%s] is plugin", fan_obj.name, fan_obj.get_serial()) + self.fan_airflow_check(fan_obj) + else: + fan_obj.plugin_cnt = 0 + fan_obj.plugout_cnt += 1 + if fan_obj.plugout_cnt >= self.__present_check_cnt: + fan_obj.pre_present = False + self.logger.info("%s is plugout", fan_obj.name) + else: + fan_obj.plugin_cnt = 0 + fan_obj.plugout_cnt = 0 + self.logger.debug("%s present status is not change", fan_obj.name) + + def fan_status_check(self, fan_obj): + status = fan_obj.get_status() + if status is True: + self.logger.debug("%s is normal", fan_obj.name) + else: + self.logger.debug("%s is error", fan_obj.name) + + if status != fan_obj.pre_status: + if status is True: + fan_obj.status_normal_cnt += 1 + fan_obj.status_error_cnt = 0 + if fan_obj.status_normal_cnt >= self.__status_check_cnt: + fan_obj.pre_status = True + self.logger.info( + "%s [serial:%s] is form error change to normal", + fan_obj.name, + fan_obj.get_serial()) + else: + fan_obj.status_normal_cnt = 0 + fan_obj.status_error_cnt += 1 + if fan_obj.status_error_cnt >= self.__status_check_cnt: + fan_obj.pre_status = False + self.logger.info( + "%s [serial:%s] is form normal change to error", + fan_obj.name, + fan_obj.get_serial()) + else: + fan_obj.status_normal_cnt = 0 + fan_obj.status_error_cnt = 0 + self.logger.debug("%s status is not change", fan_obj.name) + + def checkFanPresence(self): + for fan_obj in self.fan_obj_list: + self.fan_plug_in_out_check(fan_obj) + + def checkFanStatus(self): + for fan_obj in self.fan_obj_list: + self.fan_status_check(fan_obj) + + def run(self): + start_time = time.time() + while True: + try: + self.debug_init() + delta_time = time.time() - start_time + if self.__present_interval <= self.__status_interval: + if delta_time >= self.__status_interval or delta_time < 0: + self.checkFanStatus() + start_time = time.time() + else: + self.checkFanPresence() + time.sleep(self.__present_interval) + else: + if delta_time >= self.__present_interval or delta_time < 0: + self.checkFanPresence() + start_time = time.time() + else: + self.checkFanStatus() + time.sleep(self.__status_interval) + except Exception as e: + self.logger.error('EXCEPTION: %s.', str(e)) + + +if __name__ == '__main__': + monitor_fan = MonitorFan() + monitor_fan.fan_obj_init() + monitor_fan.run() diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/script/platform_common.py b/platform/broadcom/sonic-platform-modules-ragile/common/script/platform_common.py new file mode 100755 index 000000000000..4fe0beec44d5 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/script/platform_common.py @@ -0,0 +1,178 @@ +#!/usr/bin/python3 + +__all__ = [ + "BLACKLIST_DRIVERS", + "DRIVERLISTS", + "DEVICE", + "STARTMODULE", + "MAC_LED_RESET", + "MAC_DEFAULT_PARAM", + "DEV_MONITOR_PARAM", + "SLOT_MONITOR_PARAM", + "MANUINFO_CONF", + "REBOOT_CTRL_PARAM", + "PMON_SYSLOG_STATUS", + "OPTOE", + "REBOOT_CAUSE_PARA", + "UPGRADE_SUMMARY", + "WARM_UPGRADE_PARAM", + "WARM_UPG_FLAG", + "WARM_UPGRADE_STARTED_FLAG", + "PLATFORM_E2_CONF", + "AIR_FLOW_CONF", + "AIRFLOW_RESULT_FILE", + "INIT_PARAM_PRE", + "INIT_COMMAND_PRE", + "INIT_PARAM", + "INIT_COMMAND", + "MONITOR_TEMP_MIN", + "MONITOR_K", + "MONITOR_MAC_IN", + "MONITOR_DEFAULT_SPEED", + "MONITOR_MAX_SPEED", + "MONITOR_MIN_SPEED", + "MONITOR_MAC_ERROR_SPEED", + "MONITOR_FAN_TOTAL_NUM", + "MONITOR_MAC_UP_TEMP", + "MONITOR_MAC_LOWER_TEMP", + "MONITOR_MAC_MAX_TEMP", + "MONITOR_FALL_TEMP", + "MONITOR_MAC_WARNING_THRESHOLD", + "MONITOR_OUTTEMP_WARNING_THRESHOLD", + "MONITOR_BOARDTEMP_WARNING_THRESHOLD", + "MONITOR_CPUTEMP_WARNING_THRESHOLD", + "MONITOR_INTEMP_WARNING_THRESHOLD", + "MONITOR_MAC_CRITICAL_THRESHOLD", + "MONITOR_OUTTEMP_CRITICAL_THRESHOLD", + "MONITOR_BOARDTEMP_CRITICAL_THRESHOLD", + "MONITOR_CPUTEMP_CRITICAL_THRESHOLD", + "MONITOR_INTEMP_CRITICAL_THRESHOLD", + "MONITOR_CRITICAL_NUM", + "MONITOR_SHAKE_TIME", + "MONITOR_INTERVAL", + "MONITOR_LED_INTERVAL", + "MONITOR_PID_FLAG", + "MONITOR_MAC_SOURCE_SYSFS", + "MONITOR_MAC_SOURCE_PATH", + "MONITOR_PID_MODULE", + "PSU_FAN_FOLLOW", + "MONITOR_SYS_LED", + "MONITOR_SYS_FAN_LED", + "MONITOR_FANS_LED", + "MONITOR_SYS_PSU_LED", + "MONITOR_FAN_STATUS", + "MONITOR_PSU_STATUS", + "MONITOR_DEV_STATUS", + "MONITOR_DEV_STATUS_DECODE", + "DEV_LEDS", + "fanloc" +] + +# driver blacklist parameter +BLACKLIST_DRIVERS = [] + +# driver list parameter +DRIVERLISTS = [] + +# device list parameter +DEVICE = [] + +# start module parameters +STARTMODULE = {} + +# mac led reset parameter +MAC_LED_RESET = {} + +# avscontrol parameter +MAC_DEFAULT_PARAM = [] + +# dev_monitor parameter +DEV_MONITOR_PARAM = {} + +# slot_monitor parameter +SLOT_MONITOR_PARAM = {} + +# platform_manufacturer parameter +MANUINFO_CONF = {} + +# reboot_ctrl parameter +REBOOT_CTRL_PARAM = {} + +# pmon_syslog parameter +PMON_SYSLOG_STATUS = {} + +# sfp optoe device parameter +OPTOE = [] + +# reboot_cause parameter +REBOOT_CAUSE_PARA = [] + +# upgrade parameter +UPGRADE_SUMMARY = {} + +# warm_uprade parameter +WARM_UPGRADE_PARAM = {} +WARM_UPG_FLAG = "/etc/sonic/.warm_upg_flag" +WARM_UPGRADE_STARTED_FLAG = "/etc/sonic/.doing_warm_upg" + +# platform_e2 parameter +PLATFORM_E2_CONF = {} + +# generate_airflow parameter +AIR_FLOW_CONF = {} +AIRFLOW_RESULT_FILE = "/etc/sonic/.airflow" + +# Initialization parameters +INIT_PARAM_PRE = [] +INIT_COMMAND_PRE = [] +INIT_PARAM = [] +INIT_COMMAND = [] + +################################ fancontrol parameter################################### +MONITOR_TEMP_MIN = 38 +MONITOR_K = 11 +MONITOR_MAC_IN = 35 +MONITOR_DEFAULT_SPEED = 0x60 +MONITOR_MAX_SPEED = 0xFF +MONITOR_MIN_SPEED = 0x60 +MONITOR_MAC_ERROR_SPEED = 0XBB +MONITOR_FAN_TOTAL_NUM = 4 +MONITOR_MAC_UP_TEMP = 50 +MONITOR_MAC_LOWER_TEMP = -50 +MONITOR_MAC_MAX_TEMP = 100 # + +MONITOR_FALL_TEMP = 4 +MONITOR_MAC_WARNING_THRESHOLD = 100 +MONITOR_OUTTEMP_WARNING_THRESHOLD = 85 +MONITOR_BOARDTEMP_WARNING_THRESHOLD = 85 +MONITOR_CPUTEMP_WARNING_THRESHOLD = 85 +MONITOR_INTEMP_WARNING_THRESHOLD = 70 + +MONITOR_MAC_CRITICAL_THRESHOLD = 105 +MONITOR_OUTTEMP_CRITICAL_THRESHOLD = 90 +MONITOR_BOARDTEMP_CRITICAL_THRESHOLD = 90 +MONITOR_CPUTEMP_CRITICAL_THRESHOLD = 100 +MONITOR_INTEMP_CRITICAL_THRESHOLD = 80 +MONITOR_CRITICAL_NUM = 3 +MONITOR_SHAKE_TIME = 20 +MONITOR_INTERVAL = 60 +MONITOR_LED_INTERVAL = 2 +MONITOR_PID_FLAG = 0 + +MONITOR_MAC_SOURCE_SYSFS = 0 +MONITOR_MAC_SOURCE_PATH = None + +MONITOR_PID_MODULE = {} + +PSU_FAN_FOLLOW = {} + +MONITOR_SYS_LED = [] +MONITOR_SYS_FAN_LED = [] +MONITOR_FANS_LED = [] +MONITOR_SYS_PSU_LED = [] +MONITOR_FAN_STATUS = [] +MONITOR_PSU_STATUS = [] +MONITOR_DEV_STATUS = {} +MONITOR_DEV_STATUS_DECODE = {} +DEV_LEDS = {} +fanloc = [] diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/script/platform_config.py b/platform/broadcom/sonic-platform-modules-ragile/common/script/platform_config.py new file mode 100755 index 000000000000..004a64c72233 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/script/platform_config.py @@ -0,0 +1,184 @@ +#!/usr/bin/python3 + +import sys +import os +from wbutil.baseutil import get_machine_info +from wbutil.baseutil import get_platform_info +from wbutil.baseutil import get_board_id + +__all__ = [ + "MAILBOX_DIR", + "PLATFORM_GLOBALCONFIG", + "GLOBALCONFIG", + "STARTMODULE", + "MAC_LED_RESET", + "MAC_DEFAULT_PARAM", + "DEV_MONITOR_PARAM", + "SLOT_MONITOR_PARAM", + "MANUINFO_CONF", + "REBOOT_CTRL_PARAM", + "PMON_SYSLOG_STATUS", + "REBOOT_CAUSE_PARA", + "UPGRADE_SUMMARY", + "WARM_UPGRADE_PARAM", + "WARM_UPG_FLAG", + "WARM_UPGRADE_STARTED_FLAG", + "PLATFORM_E2_CONF", + "AIR_FLOW_CONF", + "AIRFLOW_RESULT_FILE", + "GLOBALINITPARAM", + "GLOBALINITCOMMAND", + "GLOBALINITPARAM_PRE", + "GLOBALINITCOMMAND_PRE", + "MONITOR_CONST", + "PSU_FAN_FOLLOW", + "MONITOR_SYS_LED", + "MONITOR_FANS_LED", + "MONITOR_SYS_FAN_LED", + "MONITOR_SYS_PSU_LED", + "MONITOR_FAN_STATUS", + "MONITOR_PSU_STATUS", + "MONITOR_DEV_STATUS", + "MONITOR_DEV_STATUS_DECODE", + "DEV_LEDS", + "fanloc" +] + + +def getdeviceplatform(): + x = get_platform_info(get_machine_info()) + if x is not None: + filepath = "/usr/share/sonic/device/" + x + return filepath + return None + + +platform = get_platform_info(get_machine_info()) +board_id = get_board_id(get_machine_info()) +platformpath = getdeviceplatform() +MAILBOX_DIR = "/sys/bus/i2c/devices/" +grtd_productfile = (platform + "_config").replace("-", "_") +common_productfile = "platform_common" +platform_configfile = (platform + "_" + board_id + "_config").replace("-", "_") # platfrom + board_id +configfile_pre = "/usr/local/bin/" +sys.path.append(platformpath) +sys.path.append(configfile_pre) + +############################################################################################ +if os.path.exists(configfile_pre + platform_configfile + ".py"): + module_product = __import__(platform_configfile, globals(), locals(), [], 0) +elif os.path.exists(configfile_pre + grtd_productfile + ".py"): + module_product = __import__(grtd_productfile, globals(), locals(), [], 0) +elif os.path.exists(configfile_pre + common_productfile + ".py"): + module_product = __import__(common_productfile, globals(), locals(), [], 0) +else: + print("config file not exist") + sys.exit(-1) +############################################################################################ + +PLATFORM_GLOBALCONFIG = { + "DRIVERLISTS": module_product.DRIVERLISTS, + "OPTOE": module_product.OPTOE, + "DEVS": module_product.DEVICE, + "BLACKLIST_DRIVERS": module_product.BLACKLIST_DRIVERS +} +GLOBALCONFIG = PLATFORM_GLOBALCONFIG + +# start module parameters +STARTMODULE = module_product.STARTMODULE + +# mac led reset parameter +MAC_LED_RESET = module_product.MAC_LED_RESET + +# avscontrol parameter +MAC_DEFAULT_PARAM = module_product.MAC_DEFAULT_PARAM + +# dev_monitor parameter +DEV_MONITOR_PARAM = module_product.DEV_MONITOR_PARAM + +# slot_monitor parameter +SLOT_MONITOR_PARAM = module_product.SLOT_MONITOR_PARAM + +# platform_manufacturer parameter +MANUINFO_CONF = module_product.MANUINFO_CONF + +# reboot_ctrl parameter +REBOOT_CTRL_PARAM = module_product.REBOOT_CTRL_PARAM + +# pmon_syslog parameter +PMON_SYSLOG_STATUS = module_product.PMON_SYSLOG_STATUS + +# reboot_cause parameter +REBOOT_CAUSE_PARA = module_product.REBOOT_CAUSE_PARA + +# upgrade parameter +UPGRADE_SUMMARY = module_product.UPGRADE_SUMMARY + +# warm_uprade parameter +WARM_UPGRADE_PARAM = module_product.WARM_UPGRADE_PARAM +WARM_UPG_FLAG = module_product.WARM_UPG_FLAG +WARM_UPGRADE_STARTED_FLAG = module_product.WARM_UPGRADE_STARTED_FLAG + +# platform_e2 parameter +PLATFORM_E2_CONF = module_product.PLATFORM_E2_CONF + +# generate_airflow parameter +AIR_FLOW_CONF = module_product.AIR_FLOW_CONF +AIRFLOW_RESULT_FILE = module_product.AIRFLOW_RESULT_FILE + +# Initialization parameters +GLOBALINITPARAM = module_product.INIT_PARAM +GLOBALINITCOMMAND = module_product.INIT_COMMAND +GLOBALINITPARAM_PRE = module_product.INIT_PARAM_PRE +GLOBALINITCOMMAND_PRE = module_product.INIT_COMMAND_PRE + +################################ fancontrol parameter################################### + + +class MONITOR_CONST: + TEMP_MIN = module_product.MONITOR_TEMP_MIN + K = module_product.MONITOR_K + MAC_IN = module_product.MONITOR_MAC_IN + DEFAULT_SPEED = module_product.MONITOR_DEFAULT_SPEED + MAX_SPEED = module_product.MONITOR_MAX_SPEED + MIN_SPEED = module_product.MONITOR_MIN_SPEED + MAC_ERROR_SPEED = module_product.MONITOR_MAC_ERROR_SPEED + FAN_TOTAL_NUM = module_product.MONITOR_FAN_TOTAL_NUM + MAC_UP_TEMP = module_product.MONITOR_MAC_UP_TEMP + MAC_LOWER_TEMP = module_product.MONITOR_MAC_LOWER_TEMP + MAC_MAX_TEMP = module_product.MONITOR_MAC_MAX_TEMP + + MAC_WARNING_THRESHOLD = module_product.MONITOR_MAC_WARNING_THRESHOLD + OUTTEMP_WARNING_THRESHOLD = module_product.MONITOR_OUTTEMP_WARNING_THRESHOLD + BOARDTEMP_WARNING_THRESHOLD = module_product.MONITOR_BOARDTEMP_WARNING_THRESHOLD + CPUTEMP_WARNING_THRESHOLD = module_product.MONITOR_CPUTEMP_WARNING_THRESHOLD + INTEMP_WARNING_THRESHOLD = module_product.MONITOR_INTEMP_WARNING_THRESHOLD + + MAC_CRITICAL_THRESHOLD = module_product.MONITOR_MAC_CRITICAL_THRESHOLD + OUTTEMP_CRITICAL_THRESHOLD = module_product.MONITOR_OUTTEMP_CRITICAL_THRESHOLD + BOARDTEMP_CRITICAL_THRESHOLD = module_product.MONITOR_BOARDTEMP_CRITICAL_THRESHOLD + CPUTEMP_CRITICAL_THRESHOLD = module_product.MONITOR_CPUTEMP_CRITICAL_THRESHOLD + INTEMP_CRITICAL_THRESHOLD = module_product.MONITOR_INTEMP_CRITICAL_THRESHOLD + CRITICAL_NUM = module_product.MONITOR_CRITICAL_NUM + SHAKE_TIME = module_product.MONITOR_SHAKE_TIME + MONITOR_INTERVAL = module_product.MONITOR_INTERVAL + MONITOR_LED_INTERVAL = module_product.MONITOR_LED_INTERVAL + MONITOR_FALL_TEMP = module_product.MONITOR_FALL_TEMP + MONITOR_PID_FLAG = module_product.MONITOR_PID_FLAG + MONITOR_PID_MODULE = module_product.MONITOR_PID_MODULE + + MONITOR_MAC_SOURCE_SYSFS = module_product.MONITOR_MAC_SOURCE_SYSFS + MONITOR_MAC_SOURCE_PATH = module_product.MONITOR_MAC_SOURCE_PATH + + +PSU_FAN_FOLLOW = module_product.PSU_FAN_FOLLOW +MONITOR_SYS_LED = module_product.MONITOR_SYS_LED +MONITOR_FANS_LED = module_product.MONITOR_FANS_LED +MONITOR_SYS_FAN_LED = module_product.MONITOR_SYS_FAN_LED +MONITOR_SYS_PSU_LED = module_product.MONITOR_SYS_PSU_LED +MONITOR_FAN_STATUS = module_product.MONITOR_FAN_STATUS +MONITOR_PSU_STATUS = module_product.MONITOR_PSU_STATUS +MONITOR_DEV_STATUS = module_product.MONITOR_DEV_STATUS +MONITOR_DEV_STATUS_DECODE = module_product.MONITOR_DEV_STATUS_DECODE +DEV_LEDS = module_product.DEV_LEDS +fanloc = module_product.fanloc diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/script/platform_driver.py b/platform/broadcom/sonic-platform-modules-ragile/common/script/platform_driver.py new file mode 100755 index 000000000000..6d2c6de653d9 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/script/platform_driver.py @@ -0,0 +1,258 @@ +#!/usr/bin/env python3 +import os +import subprocess +import time +import click +from platform_config import GLOBALCONFIG, WARM_UPGRADE_STARTED_FLAG, WARM_UPG_FLAG + + +CONTEXT_SETTINGS = {"help_option_names": ['-h', '--help']} + + +class AliasedGroup(click.Group): + def get_command(self, ctx, cmd_name): + rv = click.Group.get_command(self, ctx, cmd_name) + if rv is not None: + return rv + matches = [x for x in self.list_commands(ctx) + if x.startswith(cmd_name)] + if not matches: + return None + if len(matches) == 1: + return click.Group.get_command(self, ctx, matches[0]) + ctx.fail('Too many matches: %s' % ', '.join(sorted(matches))) + return None + + +def log_os_system(cmd): + status, output = subprocess.getstatusoutput(cmd) + if status: + print(output) + return status, output + + +def platform_process_file_check(): + # WARM_UPGRADE_STARTED_FLAG is used as warm_upgrade.py process start flag + if os.path.exists(WARM_UPGRADE_STARTED_FLAG): + os.remove(WARM_UPGRADE_STARTED_FLAG) + + # WARM_UPG_FLAG is used as port related service judgment flag + if os.path.exists(WARM_UPG_FLAG): + os.remove(WARM_UPG_FLAG) + + +def startCommon_operation(): + platform_process_file_check() + + +def check_driver(): + status, output = log_os_system("lsmod | grep wb | wc -l") + if status: + return False + if output.isdigit() and int(output) > 0: + return True + return False + + +def removeDev(bus, loc): + cmd = "echo 0x%02x > /sys/bus/i2c/devices/i2c-%d/delete_device" % (loc, bus) + devpath = "/sys/bus/i2c/devices/%d-%04x" % (bus, loc) + if os.path.exists(devpath): + log_os_system(cmd) + + +def addDev(name, bus, loc): + if name == "lm75": + time.sleep(0.1) + pdevpath = "/sys/bus/i2c/devices/i2c-%d/" % (bus) + for i in range(1, 100): + if os.path.exists(pdevpath) is True: + break + time.sleep(0.1) + if i % 10 == 0: + click.echo("%%WB_PLATFORM_DRIVER-INIT: %s not found, wait 0.1 second ! i %d " % (pdevpath, i)) + + cmd = "echo %s 0x%02x > /sys/bus/i2c/devices/i2c-%d/new_device" % (name, loc, bus) + devpath = "/sys/bus/i2c/devices/%d-%04x" % (bus, loc) + if os.path.exists(devpath) is False: + os.system(cmd) + + +def removeOPTOE(startbus, endbus): + for bus in range(endbus, startbus - 1, -1): + removeDev(bus, 0x50) + + +def addOPTOE(name, startbus, endbus): + for bus in range(startbus, endbus + 1): + addDev(name, bus, 0x50) + + +def removeoptoes(): + optoes = GLOBALCONFIG["OPTOE"] + for index in range(len(optoes) - 1, -1, -1): + removeOPTOE(optoes[index]["startbus"], optoes[index]["endbus"]) + + +def addoptoes(): + optoes = GLOBALCONFIG["OPTOE"] + for optoe in optoes: + addOPTOE(optoe["name"], optoe["startbus"], optoe["endbus"]) + + +def removedevs(): + devs = GLOBALCONFIG["DEVS"] + for index in range(len(devs) - 1, -1, -1): + removeDev(devs[index]["bus"], devs[index]["loc"]) + + +def adddevs(): + devs = GLOBALCONFIG["DEVS"] + for dev in devs: + addDev(dev["name"], dev["bus"], dev["loc"]) + + +def checksignaldriver(name): + modisexistcmd = "lsmod | grep -w %s | wc -l" % name + status, output = log_os_system(modisexistcmd) + if status: + return False + if output.isdigit() and int(output) > 0: + return True + return False + + +def adddriver(name, delay): + cmd = "modprobe %s" % name + if delay != 0: + time.sleep(delay) + if checksignaldriver(name) is not True: + log_os_system(cmd) + + +def removedriver(name, delay, removeable=1): + realname = name.lstrip().split(" ")[0] + cmd = "rmmod -f %s" % realname + if checksignaldriver(realname) and removeable: + log_os_system(cmd) + if delay > 0: + time.sleep(delay) + + +def removedrivers(): + if GLOBALCONFIG is None: + click.echo("%%WB_PLATFORM_DRIVER-INIT: load global config failed.") + return + drivers = GLOBALCONFIG.get("DRIVERLISTS", None) + if drivers is None: + click.echo("%%WB_PLATFORM_DRIVER-INIT: load driver list failed.") + return + for index in range(len(drivers) - 1, -1, -1): + delay = 0 + name = "" + removeable = drivers[index].get("removable", 1) + if isinstance(drivers[index], dict) and "delay" in drivers[index]: + name = drivers[index].get("name") + delay = drivers[index]["delay"] + else: + name = drivers[index] + removedriver(name, delay, removeable) + + +def adddrivers(): + if GLOBALCONFIG is None: + click.echo("%%WB_PLATFORM_DRIVER-INIT: load global config failed.") + return + drivers = GLOBALCONFIG.get("DRIVERLISTS", None) + if drivers is None: + click.echo("%%WB_PLATFORM_DRIVER-INIT: load driver list failed.") + return + for driver in drivers: + delay = 0 + name = "" + if isinstance(driver, dict) and "delay" in driver: + name = driver.get("name") + delay = driver["delay"] + else: + name = driver + adddriver(name, delay) + + +def blacklist_driver_remove(): + if GLOBALCONFIG is None: + click.echo("%%WB_PLATFORM_DRIVER-INIT: load global config failed.") + return + blacklist_drivers = GLOBALCONFIG.get("BLACKLIST_DRIVERS", []) + for driver in blacklist_drivers: + delay = 0 + name = "" + if isinstance(driver, dict) and "delay" in driver: + name = driver.get("name") + delay = driver["delay"] + else: + name = driver + removedriver(name, delay) + + +def unload_driver(): + removeoptoes() + removedevs() + removedrivers() + + +def reload_driver(): + removedevs() + removedrivers() + time.sleep(1) + adddrivers() + adddevs() + + +def i2c_check(bus, retrytime=6): + try: + i2cpath = "/sys/bus/i2c/devices/" + bus + while retrytime and not os.path.exists(i2cpath): + click.echo("%%WB_PLATFORM_DRIVER-HA: i2c bus abnormal, last bus %s is not exist." % i2cpath) + reload_driver() + retrytime -= 1 + time.sleep(1) + except Exception as e: + click.echo("%%WB_PLATFORM_DRIVER-HA: %s" % str(e)) + + +def load_driver(): + startCommon_operation() + adddrivers() + adddevs() + addoptoes() + + +@click.group(cls=AliasedGroup, context_settings=CONTEXT_SETTINGS) +def main(): + '''device operator''' + + +@main.command() +def start(): + '''load drivers and device ''' + blacklist_driver_remove() + if check_driver(): + unload_driver() + load_driver() + + +@main.command() +def stop(): + '''stop drivers device ''' + unload_driver() + + +@main.command() +def restart(): + '''restart drivers and device''' + unload_driver() + load_driver() + + +if __name__ == '__main__': + main() diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/script/platform_e2.py b/platform/broadcom/sonic-platform-modules-ragile/common/script/platform_e2.py new file mode 100755 index 000000000000..808d93216210 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/script/platform_e2.py @@ -0,0 +1,434 @@ +#!/usr/bin/env python3 +# -*- coding: UTF-8 -*- +import click + +from eepromutil.fru import ipmifru +from eepromutil.fantlv import fan_tlv +import eepromutil.onietlv as ot +from platform_config import PLATFORM_E2_CONF +from platform_util import byteTostr, dev_file_read + +CONTEXT_SETTINGS = {"help_option_names": ['-h', '--help']} + + +class AliasedGroup(click.Group): + def get_command(self, ctx, cmd_name): + rv = click.Group.get_command(self, ctx, cmd_name) + if rv is not None: + return rv + matches = [x for x in self.list_commands(ctx) + if x.startswith(cmd_name)] + if not matches: + return None + if len(matches) == 1: + return click.Group.get_command(self, ctx, matches[0]) + ctx.fail('Too many matches: %s' % ', '.join(sorted(matches))) + return None + + +class ExtraFunc(object): + @staticmethod + def decode_mac(encodedata): + if encodedata is None: + return None + ret = ":".join("%02x" % ord(data) for data in encodedata) + return ret.upper() + + @staticmethod + def decode_mac_number(encodedata): + if encodedata is None: + return None + return (ord(encodedata[0]) << 8) | (ord(encodedata[1]) & 0x00ff) + + @staticmethod + @staticmethod + def fru_decode_mac_number(params): + ipmi_fru = params.get("fru") + area = params.get("area") + field = params.get("field") + area_info = getattr(ipmi_fru, area, None) + if area_info is not None: + raw_mac_number = getattr(area_info, field, None) + mac_number = decode_mac_number(raw_mac_number) + ipmi_fru.setValue(area, field, mac_number) + + @staticmethod + def fru_decode_mac(params): + ipmi_fru = params.get("fru") + area = params.get("area") + field = params.get("field") + area_info = getattr(ipmi_fru, area, None) + if area_info is not None: + raw_mac = getattr(area_info, field, None) + decoded_mac = decode_mac(raw_mac) + ipmi_fru.setValue(area, field, decoded_mac) + + @staticmethod + def fru_decode_hw(params): + ipmi_fru = params.get("fru") + area = params.get("area") + field = params.get("field") + area_info = getattr(ipmi_fru, area, None) + if area_info is not None: + raw_hw = getattr(area_info, field, None) + decode_hw = str(int(raw_hw, 16)) + ipmi_fru.setValue(area, field, decode_hw) + + +def set_onie_value(params): + onie = params.get("onie") + field = params.get("field") + config_value = params.get("config_value") + for index, onie_item in enumerate(onie): + if onie_item.get("name") == field: + if "value" in onie_item.keys(): + onie[index]["value"] = config_value + + +def onie_eeprom_decode(onie, e2_decode): + for e2_decode_item in e2_decode: + field = e2_decode_item.get("field") + decode_type = e2_decode_item.get("decode_type") + if decode_type == 'func': + params = { + "onie": onie, + "field": field + } + func_name = e2_decode_item.get("func_name") + if func_name is not None: + run_func(func_name, params) + elif decode_type == 'config': + config_value = e2_decode_item.get("config_value") + if config_value is not None: + params = { + "onie": onie, + "field": field, + "config_value": config_value + } + set_onie_value(params) + else: + print("unsupport decode type") + continue + + +def onie_eeprom_show(eeprom, e2_decode=None): + try: + onietlv = ot.onie_tlv() + rets = onietlv.decode(eeprom) + if e2_decode is not None: + onie_eeprom_decode(rets, e2_decode) + print("%-20s %-5s %-5s %-20s" % ("TLV name", "Code", "lens", "Value")) + for item in rets: + if item["code"] == 0xfd: + print("%-20s 0x%-02X %-5s" % (item["name"], item["code"], item["lens"])) + else: + print("%-20s 0x%-02X %-5s %-20s" % (item["name"], item["code"], item["lens"], item["value"])) + except Exception as e: + print(str(e)) + + +def set_fantlv_value(params): + fantlv_dict = params.get("fantlv") + field = params.get("field") + config_value = params.get("config_value") + for index, fantlv_item in enumerate(fantlv_dict): + if fantlv_item.get("name") == field: + if "value" in fantlv_item.keys(): + fantlv_dict[index]["value"] = config_value + + +def fantlv_eeprom_decode(fantlv_dict, e2_decode): + for e2_decode_item in e2_decode: + field = e2_decode_item.get("field") + decode_type = e2_decode_item.get("decode_type") + if decode_type == 'func': + params = { + "fantlv": fantlv_dict, + "field": field + } + func_name = e2_decode_item.get("func_name") + if func_name is not None: + run_func(func_name, params) + elif decode_type == 'config': + config_value = e2_decode_item.get("config_value") + if config_value is not None: + params = { + "fantlv": fantlv_dict, + "field": field, + "config_value": config_value + } + set_fantlv_value(params) + else: + print("unsupport decode type") + continue + + +def fantlv_eeprom_show(eeprom, e2_decode=None): + try: + tlv = fan_tlv() + rets = tlv.decode(eeprom) + if len(rets) == 0: + print("fan tlv eeprom info error.!") + return + if e2_decode is not None: + fantlv_eeprom_decode(rets, e2_decode) + print("%-15s %-5s %-5s %-20s" % ("TLV name", "Code", "lens", "Value")) + for item in rets: + print("%-15s 0x%-02X %-5s %-20s" % (item["name"], item["code"], item["lens"], item["value"])) + except Exception as e: + print(str(e)) + return + + +def run_func(funcname, params): + try: + func = getattr(ExtraFunc, funcname) + func(params) + except Exception as e: + print(str(e)) + +def set_fru_value(params): + ipmi_fru = params.get("fru") + area = params.get("area") + field = params.get("field") + config_value = params.get("config_value") + ipmi_fru.setValue(area, field, config_value) + + +def fru_eeprom_decode(ipmi_fru, e2_decode): + for e2_decode_item in e2_decode: + area = e2_decode_item.get("area") + field = e2_decode_item.get("field") + decode_type = e2_decode_item.get("decode_type") + if decode_type == 'func': + params = { + "fru": ipmi_fru, + "area": area, + "field": field + } + func_name = e2_decode_item.get("func_name") + if func_name is not None: + run_func(func_name, params) + elif decode_type == 'config': + config_value = e2_decode_item.get("config_value") + if config_value is not None: + params = { + "fru": ipmi_fru, + "area": area, + "field": field, + "config_value": config_value + } + set_fru_value(params) + else: + print("unsupport decode type") + continue + + +def fru_eeprom_show(eeprom, e2_decode=None): + try: + ipmi_fru = ipmifru() + ipmi_fru.decodeBin(eeprom) + if e2_decode is not None: + fru_eeprom_decode(ipmi_fru, e2_decode) + print("=================board=================") + print(ipmi_fru.boardInfoArea) + print("=================product=================") + print(ipmi_fru.productInfoArea) + except Exception as e: + print(str(e)) + + +def eeprom_parase(eeprom_conf): + name = eeprom_conf.get("name") + e2_type = eeprom_conf.get("e2_type") + e2_path = eeprom_conf.get("e2_path") + e2_size = eeprom_conf.get("e2_size", 256) + e2_decode = eeprom_conf.get("e2_decode") + print("===================%s===================" % name) + ret, binval_bytes = dev_file_read(e2_path, 0, e2_size) + if ret is False: + print("eeprom read error, eeprom path: %s, msg: %s" % (e2_path, binval_bytes)) + return + binval = byteTostr(binval_bytes) + if e2_type == "onie_tlv": + onie_eeprom_show(binval, e2_decode) + elif e2_type == "fru": + fru_eeprom_show(binval, e2_decode) + elif e2_type == "fantlv": + fantlv_eeprom_show(binval, e2_decode) + else: + print("Unknow eeprom type: %s" % e2_type) + return + + +def get_fans_eeprom_info(param): + fan_eeprom_conf = PLATFORM_E2_CONF.get("fan", []) + fan_num = len(fan_eeprom_conf) + if fan_num == 0: + print("fan number is 0, can't get fan eeprom info") + return + if param == 'all': + for conf in fan_eeprom_conf: + eeprom_parase(conf) + return + if not param.isdigit(): + print("param error, %s is not digital or 'all'" % param) + return + fan_index = int(param, 10) - 1 + if fan_index < 0 or fan_index >= fan_num: + print("param error, total fan number: %d, fan index: %d" % (fan_num, fan_index + 1)) + return + eeprom_parase(fan_eeprom_conf[fan_index]) + return + + +def get_psus_eeprom_info(param): + psu_eeprom_conf = PLATFORM_E2_CONF.get("psu", []) + psu_num = len(psu_eeprom_conf) + if psu_num == 0: + print("psu number is 0, can't get psu eeprom info") + return + if param == 'all': + for conf in psu_eeprom_conf: + eeprom_parase(conf) + return + if not param.isdigit(): + print("param error, %s is not digital or 'all'" % param) + return + psu_index = int(param, 10) - 1 + if psu_index < 0 or psu_index >= psu_num: + print("param error, total psu number: %d, psu index: %d" % (psu_num, psu_index + 1)) + return + eeprom_parase(psu_eeprom_conf[psu_index]) + return + + +def get_slots_eeprom_info(param): + slot_eeprom_conf = PLATFORM_E2_CONF.get("slot", []) + slot_num = len(slot_eeprom_conf) + if slot_num == 0: + print("slot number is 0, can't get slot eeprom info") + return + if param == 'all': + for conf in slot_eeprom_conf: + eeprom_parase(conf) + return + if not param.isdigit(): + print("param error, %s is not digital or 'all'" % param) + return + slot_index = int(param, 10) - 1 + if slot_index < 0 or slot_index >= slot_num: + print("param error, total slot number: %d, slot index: %d" % (slot_num, slot_index + 1)) + return + eeprom_parase(slot_eeprom_conf[slot_index]) + return + + +def get_syseeprom_info(param): + syseeprom_conf = PLATFORM_E2_CONF.get("syseeprom", []) + syseeprom_num = len(syseeprom_conf) + if syseeprom_num == 0: + print("syseeprom number is 0, can't get syseeprom info") + return + if param == 'all': + for conf in syseeprom_conf: + eeprom_parase(conf) + return + if not param.isdigit(): + print("param error, %s is not digital or 'all'" % param) + return + syseeprom_index = int(param, 10) - 1 + if syseeprom_index < 0 or syseeprom_index >= syseeprom_num: + print("param error, total syseeprom number: %d, syseeprom index: %d" % (syseeprom_num, syseeprom_index + 1)) + return + eeprom_parase(syseeprom_conf[syseeprom_index]) + return + + +def decode_eeprom_info(e2_type, e2_path, e2_size): + if not e2_size.isdigit(): + print("param error, e2_size %s is not digital" % e2_size) + return + e2_size = int(e2_size, 10) + eeprom_conf = {} + eeprom_conf["name"] = e2_type + eeprom_conf["e2_type"] = e2_type + eeprom_conf["e2_path"] = e2_path + eeprom_conf["e2_size"] = e2_size + eeprom_parase(eeprom_conf) + return + + +@click.group(cls=AliasedGroup, context_settings=CONTEXT_SETTINGS) +def main(): + '''platform eeprom display script''' + +# fan eeprom info display + + +@main.command() +@click.argument('fan_index', required=True) +def fan(fan_index): + '''fan_index(1, 2, 3...)/all''' + get_fans_eeprom_info(fan_index) + +# psu eeprom info display + + +@main.command() +@click.argument('psu_index', required=True) +def psu(psu_index): + '''psu_index(1, 2, 3...)/all''' + get_psus_eeprom_info(psu_index) + +# slot eeprom info display + + +@main.command() +@click.argument('slot_index', required=True) +def slot(slot_index): + '''slot_index(1, 2, 3...)/all''' + get_slots_eeprom_info(slot_index) + +# syseeprom info display + + +@main.command() +@click.argument('syseeprom_index', required=True) +def syseeprom(syseeprom_index): + '''syseeprom_index(1, 2, 3...)/all''' + get_syseeprom_info(syseeprom_index) + +# fru eeprom info decode + + +@main.command() +@click.argument('e2_path', required=True) +@click.argument('e2_size', required=False, default="256") +def fru(e2_path, e2_size): + '''e2_path''' + decode_eeprom_info("fru", e2_path, e2_size) + +# fantlv eeprom info decode + + +@main.command() +@click.argument('e2_path', required=True) +@click.argument('e2_size', required=False, default="256") +def fantlv(e2_path, e2_size): + '''e2_path''' + decode_eeprom_info("fantlv", e2_path, e2_size) + +# onie_tlv eeprom info decode + + +@main.command() +@click.argument('e2_path', required=True) +@click.argument('e2_size', required=False, default="256") +def onie_tlv(e2_path, e2_size): + '''e2_path''' + decode_eeprom_info("onie_tlv", e2_path, e2_size) + + +if __name__ == '__main__': + main() diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/script/platform_intf.py b/platform/broadcom/sonic-platform-modules-ragile/common/script/platform_intf.py new file mode 100755 index 000000000000..2143b9420cd3 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/script/platform_intf.py @@ -0,0 +1,367 @@ +#!/usr/bin/env python3 +import os +import syslog +import importlib.machinery +from platform_util import getplatform_name, dev_file_read, dev_file_write, write_sysfs, read_sysfs + +__all__ = [ + "platform_reg_read", + "platform_reg_write", + "platform_set_optoe_type", + "platform_get_optoe_type", + "platform_sfp_read", + "platform_sfp_write", +] + +CPLD = 0 +FPGA = 1 +CPLD_PATH = "/dev/cpld%d" +FPGA_PATH = "/dev/fpga%d" + + +OPTOE_PATH = "/sys/bus/i2c/devices/%d-0050/" +OPTOE_DEV_CLASS = "dev_class" +OPTOE_EEPROM = "eeprom" + + +PLATFORM_INTF_DEBUG_FILE = "/etc/.platform_intf_debug_flag" + + +CONFIG_FILE_LIST = [ + "/usr/local/bin/", + "/usr/local/lib/python3/dist-packages/config/", + "/usr/local/lib/python3.7/dist-packages/config/", + "/usr/local/lib/python3.9/dist-packages/config/"] + + +def platform_intf_debug(s): + if os.path.exists(PLATFORM_INTF_DEBUG_FILE): + syslog.openlog("PLATFORM_INTF_DEBUG", syslog.LOG_PID) + syslog.syslog(syslog.LOG_DEBUG, s) + + +def platform_intf_error(s): + if os.path.exists(PLATFORM_INTF_DEBUG_FILE): + syslog.openlog("PLATFORM_INTF_ERROR", syslog.LOG_PID) + syslog.syslog(syslog.LOG_ERR, s) + + +class IntfPlatform: + CONFIG_NAME = 'PLATFORM_INTF_OPTOE' + __port_optoe_dict = {} + + def __init__(self): + real_path = None + platform_name = (getplatform_name()).replace("-", "_") + for configfile_path in CONFIG_FILE_LIST: + configfile = configfile_path + platform_name + "_port_config.py" + if os.path.exists(configfile): + real_path = configfile + break + if real_path is None: + raise Exception("get port config error") + config = importlib.machinery.SourceFileLoader(self.CONFIG_NAME, real_path).load_module() + self.__port_optoe_dict = config.PLATFORM_INTF_OPTOE + + def get_dev_path(self, dev_type, dev_id): + if dev_type == CPLD: + path = CPLD_PATH % dev_id + elif dev_type == FPGA: + path = FPGA_PATH % dev_id + else: + msg = "dev_type error!" + return False, msg + platform_intf_debug("path:%s" % path) + return True, path + + def get_port_path(self, port): + port_num = self.__port_optoe_dict.get("port_num", 0) + optoe_start_bus = self.__port_optoe_dict.get("optoe_start_bus", 0) + if port_num <= 0 or optoe_start_bus <= 0: + msg = "PLATFORM_INTF_OPTOE config error!" + return False, msg + if port <= 0 or port > port_num: + msg = "port out of range !" + return False, msg + path = OPTOE_PATH % (port + optoe_start_bus - 1) + platform_intf_debug("path:%s" % path) + return True, path + + ########################################### + # reg_read - read logic device register + # @dev_type: 0: CPLD, 1: FPGA + # @dev_id: device ID, start from 0 + # @offset: register offset + # @size: read length + # return: + # @ret: True if read success, False if not + # @info: The read value list if read success, otherwise the detail error message + ########################################### + def reg_read(self, dev_type, dev_id, offset, size): + ret, path = self.get_dev_path(dev_type, dev_id) + if ret is False: + return False, path + ret, info = dev_file_read(path, offset, size) + return ret, info + + ########################################### + # platform_reg_write - write logic device register + # @dev_type: 0: CPLD, 1: FPGA + # @dev_id: device ID, start from 0 + # @offset: register offset + # @val_list: The write value list + # return: + # @ret: True if write success, False if not + # @info: The write value length if write success, otherwise the detail error message + ########################################### + def reg_write(self, dev_type, dev_id, offset, val_list): + ret, path = self.get_dev_path(dev_type, dev_id) + if ret is False: + return False, path + ret, info = dev_file_write(path, offset, val_list) + return ret, info + + ########################################### + # set_optoe_type - set port optoe type + # @port: port index start from 1 + # @optoe_type: optoe type, including the following values + # 1: OPTOE1 + # 2: OPTOE2 + # 3: OPTOE3 + # return: + # @ret: True if set optoe type success, False if not + # @info: None if set optoe type success, otherwise the detail error message + ########################################### + def set_optoe_type(self, port, optoe_type): + ret, path = self.get_port_path(port) + if ret is False: + return False, path + optoe_type_path = path + OPTOE_DEV_CLASS + ret, info = write_sysfs(optoe_type_path, "%d" % optoe_type) + if ret is False: + return False, info + return True, None + + ########################################### + # get_optoe_type - get port optoe type + # @port: port index start from 1 + # return: + # @ret: True if set optoe type success, False if not + # @info: Optoe type value if get optoe type success, otherwise the detail error message + # optoe type including the following values + # 1: OPTOE1 + # 2: OPTOE2 + # 3: OPTOE3 + ########################################### + def get_optoe_type(self, port): + ret, path = self.get_port_path(port) + if ret is False: + return False, path + optoe_type_path = path + OPTOE_DEV_CLASS + ret, info = read_sysfs(optoe_type_path) + if ret is False: + return False, info + return True, int(info) + + ########################################### + # sfp_read -read sfp eeprom + # @port_id: port index start from 1 + # @offset: sfp eeprom offset + # @size: read sfp eeprom length + # return: + # @ret: True if read success, False if not + # @info: The read value list if read success, otherwise the detail error message + ########################################### + def sfp_read(self, port_id, offset, size): + ret, path = self.get_port_path(port_id) + if ret is False: + return False, path + optoe_eeprom_path = path + OPTOE_EEPROM + ret, info = dev_file_read(optoe_eeprom_path, offset, size) + return ret, info + + ########################################### + # sfp_write -write sfp eeprom + # @port_id: port index start from 1 + # @offset: sfp eeprom offset + # @val_list: The write value list + # return: + # @ret: True if read success, False if not + # @info: The write value length if write success, otherwise the detail error message + ########################################### + def sfp_write(self, port_id, offset, val_list): + ret, path = self.get_port_path(port_id) + if ret is False: + return False, path + optoe_eeprom_path = path + OPTOE_EEPROM + ret, info = dev_file_write(optoe_eeprom_path, offset, val_list) + return ret, info + + +platform = IntfPlatform() + + +########################################### +# platform_reg_read - read logic device register +# @dev_type: 0: CPLD, 1: FPGA +# @dev_id: device ID, start from 0 +# @offset: register offset +# @size: read length +# return: +# @ret: True if read success, False if not +# @info: The read value list if read success, otherwise the detail error message +########################################### +def platform_reg_read(dev_type, dev_id, offset, size): + ret = False + info = None + + # params check + if (isinstance(dev_type, int) is False or isinstance(dev_id, int) is False or + isinstance(offset, int) is False or isinstance(size, int) is False): + info = "params type check fail in platform_reg_read" + return ret, info + if dev_id < 0 or offset < 0 or size <= 0: + info = "params value check fail in platform_reg_read" + return ret, info + support_dev_type = (CPLD, FPGA) + if dev_type not in support_dev_type: + info = "dev_type match erro, fail in platform_reg_read" + return ret, info + + # call the solve func + return platform.reg_read(dev_type, dev_id, offset, size) + + +########################################### +# platform_reg_write - write logic device register +# @dev_type: 0: CPLD, 1: FPGA +# @dev_id: device ID, start from 0 +# @offset: register offset +# @val_list: The write value list +# return: +# @ret: True if write success, False if not +# @info: The write value length if write success, otherwise the detail error message +########################################### +def platform_reg_write(dev_type, dev_id, offset, val_list): + ret = False + info = None + + # params check + if (isinstance(dev_type, int) is False or isinstance(dev_id, int) is False or + isinstance(offset, int) is False or isinstance(val_list, list) is False): + info = "params type check fail in platform_reg_write" + return ret, info + if dev_id < 0 or offset < 0 or len(val_list) <= 0: + info = "params value check fail in platform_reg_write" + return ret, info + support_dev_type = (CPLD, FPGA) + if dev_type not in support_dev_type: + info = "dev_type match erro, fail in platform_reg_write" + return ret, info + + # call the solve func + return platform.reg_write(dev_type, dev_id, offset, val_list) + + +########################################### +# platform_set_optoe_type - set port optoe type +# @port: port index start from 1 +# @optoe_type: optoe type, including the following values +# 1: OPTOE1 +# 2: OPTOE2 +# 3: OPTOE3 +# return: +# @ret: True if set optoe type success, False if not +# @info: None if set optoe type success, otherwise the detail error message +########################################### +def platform_set_optoe_type(port, optoe_type): + ret = False + info = None + + # params check + if isinstance(port, int) is False or isinstance(optoe_type, int) is False: + info = "params type check fail in platform_set_optoe_type" + return ret, info + if port < 0 or optoe_type < 1 or optoe_type > 3: + info = "params value check fail in platform_set_optoe_type" + return ret, info + + # call the solve func + return platform.set_optoe_type(port, optoe_type) + + +########################################### +# platform_get_optoe_type - get port optoe type +# @port: port index start from 1 +# return: +# @ret: True if set optoe type success, False if not +# @info: Optoe type value if get optoe type success, otherwise the detail error message +# optoe type including the following values +# 1: OPTOE1 +# 2: OPTOE2 +# 3: OPTOE3 +########################################### +def platform_get_optoe_type(port): + ret = False + info = None + + # params check + if isinstance(port, int) is False: + info = "params type check fail in platform_get_optoe_type" + return ret, info + if port < 0: + info = "params value check fail in platform_get_optoe_type" + return ret, info + + # call the solve func + return platform.get_optoe_type(port) + + +########################################### +# platform_sfp_read -read sfp eeprom +# @port_id: port index start from 1 +# @offset: sfp eeprom offset +# @size: read sfp eeprom length +# return: +# @ret: True if read success, False if not +# @info: The read value list if read success, otherwise the detail error message +########################################### +def platform_sfp_read(port_id, offset, size): + ret = False + info = None + + # params check + if isinstance(port_id, int) is False or isinstance(offset, int) is False or isinstance(size, int) is False: + info = "params type check fail in platform_sfp_read" + return ret, info + if port_id < 0 or offset < 0 or size <= 0: + info = "params value check fail in platform_sfp_read" + return ret, info + + # call the solve func + return platform.sfp_read(port_id, offset, size) + + +########################################### +# platform_sfp_write -write sfp eeprom +# @port_id: port index start from 1 +# @offset: sfp eeprom offset +# @val_list: The write value list +# return: +# @ret: True if read success, False if not +# @info: The write value length if write success, otherwise the detail error message +########################################### +def platform_sfp_write(port_id, offset, val_list): + ret = False + info = None + + # params check + if isinstance(port_id, int) is False or isinstance(offset, int) is False or isinstance(val_list, list) is False: + info = "params type check fail in platform_sfp_write" + return ret, info + if port_id < 0 or offset < 0 or len(val_list) <= 0: + info = "params value check fail in platform_sfp_write" + return ret, info + + # call the solve func + return platform.sfp_write(port_id, offset, val_list) diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/script/platform_ipmi.py b/platform/broadcom/sonic-platform-modules-ragile/common/script/platform_ipmi.py new file mode 100755 index 000000000000..c9b72c99cca9 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/script/platform_ipmi.py @@ -0,0 +1,92 @@ +#!/usr/bin/env python3 +# -*- coding: utf-8 -*- +import sys +import os +import syslog +import click +from platform_util import exec_os_cmd + + +IPMITOOL_CMD = "ipmitool raw 0x32 0x04" # All products are the same command + +PLATFORM_IPMI_DEBUG_FILE = "/etc/.platform_ipmi_debug_flag" +UPGRADEDEBUG = 1 +debuglevel = 0 + + +def debug_init(): + global debuglevel + if os.path.exists(PLATFORM_IPMI_DEBUG_FILE): + debuglevel = debuglevel | UPGRADEDEBUG + else: + debuglevel = debuglevel & ~(UPGRADEDEBUG) + + +def ipmidebuglog(s): + # s = s.decode('utf-8').encode('gb2312') + if UPGRADEDEBUG & debuglevel: + syslog.openlog("PLATFORM_IPMI", syslog.LOG_PID) + syslog.syslog(syslog.LOG_DEBUG, s) + + +def ipmierror(s): + # s = s.decode('utf-8').encode('gb2312') + syslog.openlog("PLATFORM_IPMI", syslog.LOG_PID) + syslog.syslog(syslog.LOG_ERR, s) + + +@click.command() +@click.argument('cmd', required=True) +def platform_ipmi_main(cmd): + '''Send command to BMC through ipmi''' + try: + # Convert string command to ASCII + user_cmd = "" + for ch in cmd: + user_cmd += " " + str(ord(ch)) + + final_cmd = IPMITOOL_CMD + user_cmd + ipmidebuglog("final cmd:%s" % final_cmd) + + # exec ipmitool cmd + status, output = exec_os_cmd(final_cmd) + if status: + ipmierror("exec ipmitool_cmd:%s user_cmd:%s failed" % (IPMITOOL_CMD, cmd)) + ipmierror("failed log: %s" % output) + return False, "exec final_cmd failed" + + # the data read by ipmitool is hex value, needs transformation + data_list = output.replace("\n", "").strip(' ').split(' ') + ipmidebuglog("data_list: %s" % data_list) + result = "" + for data in data_list: + result += chr(int(data, 16)) + + # 'result' string include ret and log, separated by , + result_list = result.split(',', 2) + if len(result_list) != 2: + log = "split failed. len(result) != 2. result:%s" % result + ipmierror(log) + return False, log + if int(result_list[0]) != 0: + ipmierror("finally analy ipmitool_cmd:%s user_cmd:%s exec failed" % (IPMITOOL_CMD, cmd)) + ipmierror("failed return log: %s" % result_list[1]) + print(result_list[1]) + return False, result_list[1] + + ipmidebuglog("finally exec ipmitool_cmd:%s user_cmd:%s success" % (IPMITOOL_CMD, cmd)) + print(result_list[1]) + return True, result_list[1] + + except Exception as e: + log = "An exception occurred, exception log:%s" % str(e) + ipmierror(log) + return False, log + + +if __name__ == '__main__': + debug_init() + ret, msg = platform_ipmi_main() + if ret is False: + sys.exit(1) + sys.exit(0) diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/script/platform_manufacturer.py b/platform/broadcom/sonic-platform-modules-ragile/common/script/platform_manufacturer.py new file mode 100755 index 000000000000..1404692bc93b --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/script/platform_manufacturer.py @@ -0,0 +1,591 @@ +#!/usr/bin/env python3 + +import re +import mmap +import fcntl +import subprocess +import shlex +import signal +import os +import time +import sys +from platform_config import MANUINFO_CONF +from monitor import status + + +INDENT = 4 + + +def printerr(vchar): + sys.stderr.write(vchar + '\n') + + +g_extra_cache = {} +g_meminfo_cache = {} +g_exphy_cache = {} + + +def exec_os_cmd(cmd, timeout = None): + status, output = subprocess.getstatusoutput(cmd) + return status, output + + +def exphyfwsplit(): + # improve performance + global g_exphy_cache + if g_exphy_cache: + return + cmd = "bcmcmd -t 1 \"phy control xe,ce fw_get\" |grep fw_version" + ret, output = exec_os_cmd(cmd) + if ret or len(output) == 0: + raise Exception("run cmd: {} error, status: {}, msg: {}".format(cmd, ret, output)) + exphyfwstr = output.strip() + portlist = exphyfwstr.split("\n") + for port in portlist: + phy_addr_str = get_regular_val(port, r"phy_addr\s*=\s*\w+", 0) + if phy_addr_str.startswith("ERR"): + continue + phy_addr_key = phy_addr_str.replace(" ", "") + if phy_addr_key in g_exphy_cache: + continue + + g_exphy_cache[phy_addr_key] = {} + + fw_version_str = get_regular_val(port, r"fw_version\s*=\s*\w+", 0) + if fw_version_str.startswith("ERR"): + del g_exphy_cache[phy_addr_key] + continue + + fw_version = fw_version_str.split("=")[1].strip() + g_exphy_cache[phy_addr_key]["fw_version"] = fw_version + + if "success" in port: + ret = "OK" + else: + ret = "Unexpected" + g_exphy_cache[phy_addr_key]["status"] = ret + return + + +def lshwmemorysplit(): + # improve performance + global g_meminfo_cache + if g_meminfo_cache: + return + cmd = "lshw -c memory" + ret, output = exec_os_cmd(cmd) + if ret or len(output) == 0: + raise Exception("run cmd: {} error, status: {}, msg: {}".format(cmd, ret, output)) + memstr = output.strip() + memlist = memstr.split("*-") + for item in memlist: + if item.strip().startswith("memory") and "System Memory" not in item: + continue + line_index = 0 + for line in item.splitlines(): + line_index += 1 + if line_index == 1: + memdict_key = line + g_meminfo_cache[memdict_key] = {} + else: + if ":" not in line: + continue + key = line.split(":", 1)[0].strip() + value = line.split(":", 1)[1].strip() + g_meminfo_cache[memdict_key][key] = value + if "empty" in item: + break + return + + +def run_extra_func(funcname): + # improve performance + if funcname in g_extra_cache: + return g_extra_cache.get(funcname) + func = getattr(status, funcname) + ret = [] + func(ret) + if ret: + g_extra_cache[funcname] = ret + return ret + + +def get_extra_value(funcname, itemid, key): + for item in run_extra_func(funcname): + if item.get("id") == itemid: + return item.get(key, "NA") + return "NA" + + +def io_wr(reg_addr, reg_data): + try: + regdata = 0 + regaddr = 0 + if isinstance(reg_addr, int): + regaddr = reg_addr + else: + regaddr = int(reg_addr, 16) + if isinstance(reg_data, int): + regdata = reg_data + else: + regdata = int(reg_data, 16) + devfile = "/dev/port" + fd = os.open(devfile, os.O_RDWR | os.O_CREAT) + os.lseek(fd, regaddr, os.SEEK_SET) + os.write(fd, regdata.to_bytes(1, 'little')) + return True + except ValueError as e: + print(e) + return False + except Exception as e: + print(e) + return False + finally: + os.close(fd) + + +def checksignaldriver(name): + modisexistcmd = "lsmod | grep -w %s | wc -l" % name + ret, output = exec_os_cmd(modisexistcmd) + if ret: + return False + if output.isdigit() and int(output) > 0: + return True + return False + + +def adddriver(name): + cmd = "modprobe %s" % name + if checksignaldriver(name) is not True: + ret, log = exec_os_cmd(cmd) + if ret != 0 or len(log) > 0: + return False + return True + return True + + +def removedriver(name): + cmd = "rmmod %s" % name + if checksignaldriver(name): + exec_os_cmd(cmd) + + +def add_5387_driver(): + errmsg = "" + spi_gpio = "wb_spi_gpio" + ret = adddriver(spi_gpio) + if ret is False: + errmsg = "modprobe wb_spi_gpio driver failed." + return False, errmsg + spi_5387_device = "wb_spi_93xx46 spi_bus_num=0" + ret = adddriver(spi_5387_device) + if ret is False: + errmsg = "modprobe wb_spi_93xx46 driver failed." + return ret, errmsg + return True, "" + + +def remove_5387_driver(): + spi_5387_device = "wb_spi_93xx46" + removedriver(spi_5387_device) + spi_gpio = "wb_spi_gpio" + removedriver(spi_gpio) + + +def deal_itmes(item_list): + for item in item_list: + dealtype = item.get("dealtype") + if dealtype == "shell": + cmd = item.get("cmd") + timeout = item.get("timeout", 10) + exec_os_cmd(cmd, timeout) + elif dealtype == "io_wr": + io_addr = item.get("io_addr") + wr_value = item.get("value") + io_wr(io_addr, wr_value) + + +def get_func_value(funcname, params): + func = getattr(ExtraFunc, funcname) + ret = func(params) + return ret + + +def read_pci_reg(pcibus, slot, fn, resource, offset): + '''read pci register''' + if offset % 4 != 0: + return "ERR offset: %d not 4 bytes align" + filename = "/sys/bus/pci/devices/0000:%02x:%02x.%x/resource%d" % (int(pcibus), int(slot), int(fn), int(resource)) + size = os.path.getsize(filename) + with open(filename, "r+") as file: + data = mmap.mmap(file.fileno(), size) + result = data[offset: offset + 4] + s = result[::-1] + val = 0 + for value in s: + val = val << 8 | value + data.close() + return "%08x" % val + + +def devfileread(path, offset, length, bit_width): + ret = "" + val_str = '' + val_list = [] + fd = -1 + if not os.path.exists(path): + return "%s not found !" % path + if length % bit_width != 0: + return "only support read by bit_width" + if length < bit_width: + return "len needs to greater than or equal to bit_width" + + try: + fd = os.open(path, os.O_RDONLY) + os.lseek(fd, offset, os.SEEK_SET) + ret = os.read(fd, length) + for item in ret: + val_list.append(item) + + for i in range(0, length, bit_width): + val_str += " 0x" + for j in range(0, bit_width): + val_str += "%02x" % val_list[i + bit_width - j - 1] + except Exception as e: + return str(e) + finally: + if fd > 0: + os.close(fd) + return val_str + + +def read_reg(loc, offset, size): + with open(loc, 'rb') as file: + file.seek(offset) + return ' '.join(["%02x" % item for item in file.read(size)]) + + +def std_match(stdout, pattern): + if pattern is None: + return stdout.strip() + for line in stdout.splitlines(): + if re.match(pattern, line): + return line.strip() + raise EOFError("pattern: {} does not match anything in stdout {}".format( + pattern, stdout)) + + +def i2c_rd(bus, loc, offset): + ''' + read i2c with i2cget command + ''' + cmd = "i2cget -f -y {} {} {}".format(bus, loc, offset) + retrytime = 6 + for i in range(retrytime): + ret, stdout = subprocess.getstatusoutput(cmd) + if ret == 0: + return stdout + time.sleep(0.1) + raise RuntimeError("run cmd: {} error, status {}".format(cmd, ret)) + + +def i2c_rd_bytes(bus, loc, offset, size): + blist = [] + for i in range(size): + ret = i2c_rd(bus, loc, offset + i) + blist.append(ret) + + return blist + + +def get_pair_val(source, separator): + try: + value = source.split(separator, 1)[1] + except (ValueError, IndexError): + return "ERR separator: {} does not match in source: {}".format(separator, source) + return value.strip() + + +def get_regular_val(source, pattern, group): + try: + value = re.findall(pattern, source)[group] + except Exception: + return "ERR pattern: {} does not match in source: {} with group: {}".format(pattern, source, group) + return value.strip() + + +def find_match(file2read, pattern): + with open(file2read, 'r') as file: + for line in file: + if not re.match(pattern, line): + continue + return line.strip() + return "ERR pattern %s not match in %s" % (pattern, file2read) + + +def readaline(file2read): + with open(file2read, 'r') as file: + return file.readline() + + +def sort_key(e): + return e.arrt_index + + +class ExtraFunc(object): + @staticmethod + def get_bcm5387_version(params): + version = "" + try: + ret, msg = add_5387_driver() + if ret is False: + raise Exception(msg) + + before_deal_list = params.get("before", []) + deal_itmes(before_deal_list) + + ret, version = exec_os_cmd(params["get_version"]) + if ret != 0: + version = "ERR " + version + + after_deal_list = params.get("after", []) + deal_itmes(after_deal_list) + + except Exception as e: + version = "ERR %s" % (str(e)) + finally: + finally_deal_list = params.get("finally", []) + deal_itmes(finally_deal_list) + remove_5387_driver() + return version + + @staticmethod + def get_memory_value(params): + root_key = params.get("root_key") + sub_key = params.get("sub_key") + lshwmemorysplit() + return g_meminfo_cache.get(root_key, {}).get(sub_key, "NA") + + @staticmethod + def get_memory_bank_value(params): + lshwmemorysplit() + bank = params.get("bankid") + if g_meminfo_cache.get(bank, {}): + return True + return False + + @staticmethod + def get_exphy_fw(phyid): + exphyfwsplit() + if phyid not in g_exphy_cache: + return "ERR %s not found." % phyid + fw_version = g_exphy_cache.get(phyid).get("fw_version") + ret = g_exphy_cache.get(phyid).get("status") + msg = "%s %s" % (fw_version, ret) + return msg + +class CallbackSet: + def cpld_format(self, blist): + if isinstance(blist, str): + blist = blist.split() + elif not isinstance(blist, list) or len(blist) != 4: + raise ValueError("cpld format: wrong parameter: {}".format(blist)) + + return "{}{}{}{}".format(*blist).replace("0x", "") + + +class VersionHunter: + call = CallbackSet() + + def __init__(self, entires): + self.head = None + self.next = None + self.key = None + self.cmd = None + self.file = None + self.reg = None + self.i2c = None + self.extra = None + self.pattern = None + self.separator = None + self.parent = None + self.ignore = False + self.children = [] + self.level = 0 + self.callback = None + self.delspace = None + self.arrt_index = None + self.config = None + self.precheck = None + self.func = None + self.regular = None + self.group = 0 + self.pci = None + self.devfile = None + self.decode = None + self.timeout = 10 + self.__dict__.update(entires) + + def check_para(self): + if self.pattern is None: + return False + if self.cmd is None or self.file is None: + return False + return True + + def get_version(self): + ret = "NA" + try: + if self.cmd is not None: + ret, output = exec_os_cmd(self.cmd, self.timeout) + if ret or len(output) == 0: + raise RuntimeError("run cmd: {} error, status: {}, msg: {}".format(self.cmd, ret, output)) + ret = std_match(output, self.pattern) + elif self.file is not None: + ret = self.read_file() + elif self.reg is not None: + ret = read_reg(self.reg.get("loc"), self.reg.get("offset"), + self.reg.get("size")) + elif self.extra: + ret = get_extra_value(self.extra.get("funcname"), + self.extra.get("id"), + self.extra.get("key")) + elif self.i2c: + ret = i2c_rd_bytes(self.i2c.get("bus"), self.i2c.get("loc"), + self.i2c.get("offset"), + self.i2c.get("size")) + elif self.config: + ret = self.config + elif self.func: + ret = get_func_value(self.func.get("funcname"), + self.func.get("params")) + elif self.pci: + ret = read_pci_reg(self.pci.get("bus"), self.pci.get("slot"), + self.pci.get("fn"), self.pci.get("bar"), self.pci.get("offset")) + elif self.devfile: + ret = devfileread(self.devfile.get("loc"), self.devfile.get("offset"), + self.devfile.get("len"), self.devfile.get("bit_width")) + + except Exception as e: + # printerr(e.message) + return "ERR %s" % str(e) + return self.exe_callback(ret) + + def exe_callback(self, data): + try: + if self.callback: + method = getattr(self.call, self.callback) + return method(data) + except Exception: + return "ERR run callback method: {} error, data: {}".format(self.callback, data) + return data + + def read_file(self): + if self.pattern is not None: + return find_match(self.file, self.pattern) + return readaline(self.file) + + def hunt(self): + if self.ignore: + return + indent = self.level * INDENT * " " + + if self.precheck: + try: + ret = get_func_value(self.precheck.get("funcname"), self.precheck.get("params")) + if ret is not True: + return + except Exception as e: + err_msg = "ERR %s" % str(e) + format_str = "{}{:<{}}{}".format(indent, self.key + ':', + (30 - len(indent)), err_msg) + print(format_str) + return + # has children + if self.children: + self.children.sort(key=sort_key) + format_str = "{}{}:".format(indent, self.key) + print(format_str) + for child in self.children: + if not isinstance(child, VersionHunter): + continue + child.level = self.level + 1 + child.hunt() + else: + version = self.get_version() or "" + if not version.startswith("ERR"): + version = version.replace("\x00", "").strip() + if self.separator is not None: + version = get_pair_val(version, self.separator) + if self.delspace is not None: + version = version.replace(" ", "") + if self.regular is not None: + version = get_regular_val(version, self.regular, self.group) + if self.decode is not None: + tmp_version = self.decode.get(version) + if tmp_version is None: + version = "ERR decode %s failed" % version + else: + version = tmp_version + format_str = "{}{:<{}}{}".format(indent, self.key + ':', + (30 - len(indent)), version) + print(format_str) + + if self.next: + print("") + self.next.hunt() + + +pidfile = 0 + + +def ApplicationInstance(): + global pidfile + pidfile = open(os.path.realpath(__file__), "r") + try: + fcntl.flock(pidfile, fcntl.LOCK_EX | fcntl.LOCK_NB) + return True + except Exception: + return False + + +def run(): + if os.geteuid() != 0: + print("Root privileges are required for this operation") + sys.exit(1) + + start_time = time.time() + while True: + ret = ApplicationInstance() + if ret is True: + break + if time.time() - start_time > 10: + printerr("manufacturer is running.") + sys.exit(1) + time.sleep(0.5) + + objmap = {} + + try: + target = {} + target.update(MANUINFO_CONF) + for objname, value in target.items(): + objmap[objname] = VersionHunter(value) + except Exception as e: + printerr(str(e)) + sys.exit(1) + + head = None + for objname, obj in objmap.items(): + if head is None and obj.head: + head = obj + if obj.parent: + objmap.get(obj.parent).children.append(obj) + if obj.next: + obj.next = objmap.get(obj.next) + + head.hunt() + + +if __name__ == "__main__": + run() diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/script/platform_process.py b/platform/broadcom/sonic-platform-modules-ragile/common/script/platform_process.py new file mode 100755 index 000000000000..75bc95975520 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/script/platform_process.py @@ -0,0 +1,396 @@ +#!/usr/bin/env python3 +import os +import subprocess +import glob +import time +import click +from platform_config import STARTMODULE, MAC_LED_RESET, AIRFLOW_RESULT_FILE +from platform_config import GLOBALINITPARAM, GLOBALINITCOMMAND, GLOBALINITPARAM_PRE, GLOBALINITCOMMAND_PRE +from platform_util import wbpciwr + + +CONTEXT_SETTINGS = {"help_option_names": ['-h', '--help']} + + +class AliasedGroup(click.Group): + def get_command(self, ctx, cmd_name): + rv = click.Group.get_command(self, ctx, cmd_name) + if rv is not None: + return rv + matches = [x for x in self.list_commands(ctx) + if x.startswith(cmd_name)] + if not matches: + return None + if len(matches) == 1: + return click.Group.get_command(self, ctx, matches[0]) + ctx.fail('Too many matches: %s' % ', '.join(sorted(matches))) + return None + + +def log_os_system(cmd): + status, output = subprocess.getstatusoutput(cmd) + if status: + print(output) + return status, output + + +def write_sysfs_value(reg_name, value): + mb_reg_file = "/sys/bus/i2c/devices/" + reg_name + locations = glob.glob(mb_reg_file) + if len(locations) == 0: + print("%s not found" % mb_reg_file) + return False + sysfs_loc = locations[0] + try: + with open(sysfs_loc, 'w') as fd: + fd.write(value) + except Exception: + return False + return True + + +def getPid(name): + ret = [] + for dirname in os.listdir('/proc'): + if dirname == 'curproc': + continue + try: + with open('/proc/{}/cmdline'.format(dirname), mode='r') as fd: + content = fd.read() + except Exception: + continue + if name in content: + ret.append(dirname) + return ret + + +def startAvscontrol(): + if STARTMODULE.get('avscontrol', 0) == 1: + cmd = "nohup avscontrol.py start >/dev/null 2>&1 &" + rets = getPid("avscontrol.py") + if len(rets) == 0: + os.system(cmd) + + +def startFanctrol(): + if STARTMODULE.get('fancontrol', 0) == 1: + cmd = "nohup fancontrol.py start >/dev/null 2>&1 &" + rets = getPid("fancontrol.py") + if len(rets) == 0: + os.system(cmd) + + +def starthal_fanctrl(): + if STARTMODULE.get('hal_fanctrl', 0) == 1: + cmd = "nohup hal_fanctrl.py start >/dev/null 2>&1 &" + rets = getPid("hal_fanctrl.py") + if len(rets) == 0: + os.system(cmd) + + +def starthal_ledctrl(): + if STARTMODULE.get('hal_ledctrl', 0) == 1: + cmd = "nohup hal_ledctrl.py start >/dev/null 2>&1 &" + rets = getPid("hal_ledctrl.py") + if len(rets) == 0: + os.system(cmd) + + +def startDevmonitor(): + if STARTMODULE.get('dev_monitor', 0) == 1: + cmd = "nohup dev_monitor.py start >/dev/null 2>&1 &" + rets = getPid("dev_monitor.py") + if len(rets) == 0: + os.system(cmd) + + +def startSlotmonitor(): + if STARTMODULE.get('slot_monitor', 0) == 1: + cmd = "nohup slot_monitor.py start >/dev/null 2>&1 &" + rets = getPid("slot_monitor.py") + if len(rets) == 0: + os.system(cmd) + + +def startIntelligentmonitor(): + if STARTMODULE.get('intelligent_monitor', 0) == 1: + cmd = "nohup intelligent_monitor.py >/dev/null 2>&1 &" + rets = getPid("intelligent_monitor.py") + if len(rets) == 0: + os.system(cmd) + + +def startSignalmonitor(): + if STARTMODULE.get('signal_monitor', 0) == 1: + cmd = "nohup signal_monitor.py start >/dev/null 2>&1 &" + rets = getPid("signal_monitor.py") + if len(rets) == 0: + os.system(cmd) + + +def startSff_temp_polling(): + if STARTMODULE.get('sff_temp_polling', 0) == 1: + cmd = "nohup sfp_highest_temperatue.py >/dev/null 2>&1 &" + rets = getPid("sfp_highest_temperatue.py") + if len(rets) == 0: + os.system(cmd) + + +def startRebootCause(): + if STARTMODULE.get('reboot_cause', 0) == 1: + cmd = "nohup reboot_cause.py >/dev/null 2>&1 &" + rets = getPid("reboot_cause.py") + if len(rets) == 0: + os.system(cmd) + + +def startPMON_sys(): + if STARTMODULE.get('pmon_syslog', 0) == 1: + cmd = "nohup pmon_syslog.py >/dev/null 2>&1 &" + rets = getPid("pmon_syslog.py") + if len(rets) == 0: + os.system(cmd) + + +def startSff_polling(): + if STARTMODULE.get('sff_polling', 0) == 1: + cmd = "nohup sff_polling.py start > /dev/null 2>&1 &" + rets = getPid("sff_polling.py") + if len(rets) == 0: + os.system(cmd) + + +def generate_air_flow(): + cmd = "nohup generate_airflow.py > /dev/null 2>&1 &" + rets = getPid("generate_airflow.py") + if len(rets) == 0: + os.system(cmd) + time.sleep(1) + + +def startGenerate_air_flow(): + if STARTMODULE.get('generate_airflow', 0) == 1: + for i in range(10): + generate_air_flow() + if os.path.exists(AIRFLOW_RESULT_FILE): + click.echo("%%WB_PLATFORM_PROCESS: generate air flow success") + return + time.sleep(1) + click.echo("%%WB_PLATFORM_PROCESS: generate air flow,failed, %s not exits" % AIRFLOW_RESULT_FILE) + return + + +def start_tty_console(): + if STARTMODULE.get('tty_console', 0) == 1: + cmd = "nohup tty_console.py > /dev/null 2>&1 &" + rets = getPid("tty_console.py") + if len(rets) == 0: + os.system(cmd) + + +def stopAvscontrol(): + if STARTMODULE.get('avscontrol', 0) == 1: + rets = getPid("avscontrol.py") + for ret in rets: + cmd = "kill " + ret + os.system(cmd) + + +def stopFanctrol(): + if STARTMODULE.get('fancontrol', 0) == 1: + rets = getPid("fancontrol.py") # + for ret in rets: + cmd = "kill " + ret + os.system(cmd) + + +def stophal_fanctrl(): + if STARTMODULE.get('hal_fanctrl', 0) == 1: + rets = getPid("hal_fanctrl.py") + for ret in rets: + cmd = "kill " + ret + os.system(cmd) + + +def stophal_ledctrl(): + if STARTMODULE.get('hal_ledctrl', 0) == 1: + rets = getPid("hal_ledctrl.py") + for ret in rets: + cmd = "kill " + ret + os.system(cmd) + + +def stopDevmonitor(): + if STARTMODULE.get('dev_monitor', 0) == 1: + rets = getPid("dev_monitor.py") # + for ret in rets: + cmd = "kill " + ret + os.system(cmd) + + +def stopSlotmonitor(): + if STARTMODULE.get('slot_monitor', 0) == 1: + rets = getPid("slot_monitor.py") # + for ret in rets: + cmd = "kill " + ret + os.system(cmd) + + +def stopIntelligentmonitor(): + if STARTMODULE.get('intelligent_monitor', 0) == 1: + rets = getPid("intelligent_monitor.py") + for ret in rets: + cmd = "kill " + ret + os.system(cmd) + + +def stopSignalmonitor(): + if STARTMODULE.get('signal_monitor', 0) == 1: + rets = getPid("signal_monitor.py") # + for ret in rets: + cmd = "kill " + ret + os.system(cmd) + + +def stopSff_temp_polling(): + if STARTMODULE.get('sff_temp_polling', 0) == 1: + rets = getPid("sfp_highest_temperatue.py") + for ret in rets: + cmd = "kill " + ret + os.system(cmd) + + +def stopPMON_sys(): + if STARTMODULE.get('pmon_syslog', 0) == 1: + rets = getPid("pmon_syslog.py") + for ret in rets: + cmd = "kill " + ret + os.system(cmd) + + +def stopRebootCause(): + if STARTMODULE.get('reboot_cause', 0) == 1: + rets = getPid("reboot_cause.py") + for ret in rets: + cmd = "kill " + ret + os.system(cmd) + + +def stopSff_polling(): + if STARTMODULE.get('sff_polling', 0) == 1: + rets = getPid("sff_polling.py") + for ret in rets: + cmd = "kill " + ret + os.system(cmd) + + +def stopGenerate_air_flow(): + if STARTMODULE.get('generate_airflow', 0) == 1: + rets = getPid("generate_airflow.py") + for ret in rets: + cmd = "kill " + ret + os.system(cmd) + + +def stop_tty_console(): + if STARTMODULE.get('tty_console', 0) == 1: + rets = getPid("tty_console.py") + for ret in rets: + cmd = "kill " + ret + os.system(cmd) + + +def otherinit(): + for index in GLOBALINITPARAM: + write_sysfs_value(index["loc"], index["value"]) + + for index in GLOBALINITCOMMAND: + log_os_system(index) + + +def otherinit_pre(): + for index in GLOBALINITPARAM_PRE: + write_sysfs_value(index["loc"], index["value"]) + + for index in GLOBALINITCOMMAND_PRE: + log_os_system(index) + + +def unload_apps(): + stopSff_polling() + stopPMON_sys() + stopSignalmonitor() + stopIntelligentmonitor() + stopSlotmonitor() + stopDevmonitor() + stopAvscontrol() + stophal_ledctrl() + stophal_fanctrl() + stopFanctrol() + stopSff_temp_polling() + stopRebootCause() + stop_tty_console() + stopGenerate_air_flow() + + +def MacLedSet(data): + '''write pci register''' + pcibus = MAC_LED_RESET.get("pcibus") + slot = MAC_LED_RESET.get("slot") + fn = MAC_LED_RESET.get("fn") + resource = MAC_LED_RESET.get("bar") + offset = MAC_LED_RESET.get("offset") + val = MAC_LED_RESET.get(data, None) + if val is None: + click.echo("%%WB_PLATFORM_PROCESS-INIT: MacLedSet wrong input") + return + wbpciwr(pcibus, slot, fn, resource, offset, val) + + +def load_apps(): + otherinit_pre() + startGenerate_air_flow() + start_tty_console() + startRebootCause() + startSff_temp_polling() + startFanctrol() + starthal_fanctrl() + starthal_ledctrl() + startAvscontrol() + startDevmonitor() + startSlotmonitor() + startIntelligentmonitor() + startSignalmonitor() + startPMON_sys() + startSff_polling() + otherinit() + if STARTMODULE.get("macledreset", 0) == 1: + MacLedSet("reset") + + +@click.group(cls=AliasedGroup, context_settings=CONTEXT_SETTINGS) +def main(): + '''device operator''' + + +@main.command() +def start(): + '''load process ''' + load_apps() + + +@main.command() +def stop(): + '''stop process ''' + unload_apps() + + +@main.command() +def restart(): + '''restart process''' + unload_apps() + load_apps() + + +if __name__ == '__main__': + main() diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/script/platform_sensors.py b/platform/broadcom/sonic-platform-modules-ragile/common/script/platform_sensors.py new file mode 100755 index 000000000000..1727242b74b9 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/script/platform_sensors.py @@ -0,0 +1,253 @@ +#!/usr/bin/python3 + +import os +import sys +import importlib.machinery + + +def get_machine_info(): + if not os.path.isfile('/host/machine.conf'): + return None + machine_vars = {} + with open('/host/machine.conf') as machine_file: + for line in machine_file: + tokens = line.split('=') + if len(tokens) < 2: + continue + machine_vars[tokens[0]] = tokens[1].strip() + return machine_vars + + +def get_platform_info(machine_info): + if machine_info is not None: + if 'onie_platform' in machine_info: + return machine_info['onie_platform'] + if 'aboot_platform' in machine_info: + return machine_info['aboot_platform'] + return None + + +PLATFORM_ROOT_PATH = '/usr/share/sonic/device' +PLATFORM_SPECIFIC_MODULE_NAME = 'monitor' +PLATFORM_SPECIFIC_CLASS_NAME = 'status' +platform_status_class = None +platform = None + + +def get_platform_name(): + global platform + platform = get_platform_info(get_machine_info()) + return platform + + +val = get_platform_name() +sys.path.append("/".join([PLATFORM_ROOT_PATH, platform])) + +# Loads platform specific sfputil module from source + + +def load_platform_monitor(): + global platform_status_class + platform_name = get_platform_info(get_machine_info()) + platform_path = "/".join([PLATFORM_ROOT_PATH, platform_name]) + try: + module_file = "/".join([platform_path, PLATFORM_SPECIFIC_MODULE_NAME + ".py"]) + module = importlib.machinery.SourceFileLoader(PLATFORM_SPECIFIC_MODULE_NAME, module_file).load_module() + except IOError: + return -1 + try: + platform_status_class = getattr(module, PLATFORM_SPECIFIC_CLASS_NAME) + except AttributeError: + return -2 + return 0 + + +def printerr(msg): + print("\033[0;31m%s\033[0m" % msg) + + +def print_console(msg): + print(msg) + + +val_t = load_platform_monitor() +if val_t != 0: + raise Exception("load monitor.py error") + + +def print_platform(): + platform_info = get_platform_name() + print_console(platform_info) + print_console("") + + +def print_cputemp_sensors(): + val_ret = get_call_value_by_function("getcputemp") + print_info_str = "" + toptile = "Onboard coretemp Sensors:" + formatstr = " {name:<20} : {temp} C (high = {max} C , crit = {crit} C )" + + if len(val_ret) != 0: + print_info_str += toptile + '\n' + for item in val_ret: + print_info_str += formatstr.format(**item) + '\n' + print_console(print_info_str) + + +def print_boardtemp(): + val_ret = get_call_value_by_function("getTemp") + print_info_str = "" + toptile = "Onboard Temperature Sensors:" + errformat = " {id:<20} : {errmsg}" + formatstr = " {id:<20} : {temp1_input} C (high = {temp1_max} C, hyst = {temp1_max_hyst} C)" + + if len(val_ret) != 0: + print_info_str += toptile + '\n' + for item in val_ret: + realformat = formatstr if item.get('errcode', 0) == 0 else errformat + print_info_str += realformat.format(**item) + '\n' + print_console(print_info_str) + + +def print_mactemp_sensors(): + val_ret = get_call_value_by_function("getmactemp") + print_info_str = "" + toptile = "Onboard MAC Temperature Sensors:" + errformat = " {id:<20} : {errmsg}" + formatstr = " {id:<20} : {temp_input} C" + + if len(val_ret) != 0: + print_info_str += toptile + '\n' + for item in val_ret: + realformat = formatstr if item.get('errcode', 0) == 0 else errformat + print_info_str += realformat.format(**item) + '\n' + print_console(print_info_str) + + +def print_macpower_sensors(): + val_ret = get_call_value_by_function("getmacpower") + print_info_str = "" + toptile = "Onboard MAC Power Sensors:" + errformat = " {id:<20} : {errmsg}" + formatstr = " {id:<20} : {power_input} W" + + if len(val_ret) != 0: + print_info_str += toptile + '\n' + for item in val_ret: + realformat = formatstr if item.get('errcode', 0) == 0 else errformat + print_info_str += realformat.format(**item) + '\n' + print_console(print_info_str) + + +def print_fan_sensor(): + val_ret = get_call_value_by_function("checkFan") + print_info_str = "" + toptile = "Onboard fan Sensors:" + errformat = " {id} : {errmsg}\n" # " {id:<20} : {errmsg}" + fan_signle_rotor_format = " {id} : \n" \ + " fan_type :{fan_type}\n" \ + " sn :{sn}\n" \ + " hw_version:{hw_version}\n" \ + " Speed :{Speed} RPM\n" \ + " status :{errmsg} \n" + fan_double_rotor_format = " {id} : \n" \ + " fan_type :{fan_type}\n" \ + " sn :{sn}\n" \ + " hw_version:{hw_version}\n" \ + " Speed :\n" \ + " speed_front :{rotor1_speed:<5} RPM\n" \ + " speed_rear :{rotor2_speed:<5} RPM\n" \ + " status :{errmsg} \n" + + if len(val_ret) != 0: + print_info_str += toptile + '\n' + for item in val_ret: + if item.get('Speed', None) is None: + realformat = fan_double_rotor_format if item.get('errcode', 0) == 0 else errformat + else: + realformat = fan_signle_rotor_format if item.get('errcode', 0) == 0 else errformat + print_info_str += realformat.format(**item) + print_console(print_info_str) + + +def print_psu_sensor(): + val_ret = get_call_value_by_function("getPsu") + print_info_str = "" + toptile = "Onboard Power Supply Unit Sensors:" + errformat = " {id} : {errmsg}\n" # " {id:<20} : {errmsg}" + psuformat = " {id} : \n" \ + " type :{type1}\n" \ + " sn :{sn}\n" \ + " in_current :{in_current} A\n" \ + " in_voltage :{in_voltage} V\n" \ + " out_current:{out_current} A\n" \ + " out_voltage:{out_voltage} V\n" \ + " temp :{temp} C \n" \ + " fan_speed :{fan_speed} RPM\n" \ + " in_power :{in_power} W\n" \ + " out_power :{out_power} W\n" + + if len(val_ret) != 0: + print_info_str += toptile + '\r\n' + for item in val_ret: + realformat = psuformat if item.get('errcode', 0) == 0 else errformat + print_info_str += realformat.format(**item) + print_console(print_info_str) + + +def print_slot_sensor(): + val_ret = get_call_value_by_function("checkSlot") + print_info_str = "" + toptile = "Onboard slot Sensors:" + errformat = " {id} : {errmsg}\n" # " {id:<20} : {errmsg}" + psuformat = " {id} : \n" \ + " slot_type :{slot_type}\n" \ + " sn :{sn}\n" \ + " hw_version :{hw_version} \n" \ + " status :{errmsg}\n" + + if len(val_ret) != 0: + print_info_str += toptile + '\r\n' + for item in val_ret: + realformat = psuformat if item.get('errcode', 0) == 0 else errformat + print_info_str += realformat.format(**item) + print_console(print_info_str) + + +def print_boarddcdc(): + val_ret = get_call_value_by_function("getDcdc") + print_info_str = "" + toptile = "Onboard DCDC Sensors:" + errformat = " {id:<26} : {errmsg}" + formatstr = " {id:<26} : {dcdc_input:<6} {dcdc_unit:<1} (Min = {dcdc_min:<6} {dcdc_unit:<1}, Max = {dcdc_max:<6} {dcdc_unit:<1})" + + if len(val_ret) != 0: + print_info_str += toptile + '\n' + for item in val_ret: + realformat = formatstr if item.get('errcode', 0) == 0 else errformat + print_info_str += realformat.format(**item) + '\n' + print_console(print_info_str) + + +def get_call_value_by_function(function_name): + valtemp = [] + if hasattr(platform_status_class, function_name): + test2_func = getattr(platform_status_class, function_name) + test2_func(valtemp) + return valtemp + + +def getsensors(): + print_platform() + print_cputemp_sensors() + print_boardtemp() + print_mactemp_sensors() + print_macpower_sensors() + print_fan_sensor() + print_psu_sensor() + print_slot_sensor() + print_boarddcdc() + + +if __name__ == "__main__": + getsensors() diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/script/platform_test.py b/platform/broadcom/sonic-platform-modules-ragile/common/script/platform_test.py new file mode 100755 index 000000000000..da7119a9ce49 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/script/platform_test.py @@ -0,0 +1,142 @@ +#!/usr/bin/env python3 +# -*- coding: UTF-8 -*- + +try: + import click + from platform_intf import platform_reg_read, platform_reg_write, platform_get_optoe_type + from platform_intf import platform_set_optoe_type, platform_sfp_read, platform_sfp_write +except ImportError as error: + raise ImportError('%s - required module not found' % str(error)) from error + + +CONTEXT_SETTINGS = {"help_option_names": ['-h', '--help']} + + +class AliasedGroup(click.Group): + def get_command(self, ctx, cmd_name): + rv = click.Group.get_command(self, ctx, cmd_name) + if rv is not None: + return rv + matches = [x for x in self.list_commands(ctx) + if x.startswith(cmd_name)] + if not matches: + return None + if len(matches) == 1: + return click.Group.get_command(self, ctx, matches[0]) + ctx.fail('Too many matches: %s' % ', '.join(sorted(matches))) + return None + + +def print_reg(info, offset): + try: + size = len(info) + j = offset % 16 + tmp = j + offset -= j + print_buf = "\n " + + for i in range(16): + print_buf = print_buf + "%2x " % i + print(print_buf) + + print_buf = None + for i in range(size + j): + if i % 16 == 0: + print_buf = "" + print_buf = "0x%08x " % offset + offset = offset + 16 + if tmp: + print_buf = print_buf + " " + tmp = tmp - 1 + else: + print_buf = print_buf + "%02x " % info[i - j] + if (i + 1) % 16 == 0 or i == size + j - 1: + print(print_buf) + except Exception as e: + msg = str(e) + print("i = %d, j = %d," % (i, j)) + print(msg) + + +@click.group(cls=AliasedGroup, context_settings=CONTEXT_SETTINGS) +def main(): + '''platform_test main''' + + +@main.command() +@click.argument('dev_type', required=True) +@click.argument('dev_id', required=True) +@click.argument('offset', required=True) +@click.argument('size', required=True) +def reg_rd(dev_type, dev_id, offset, size): + '''read cpld/fpga reg''' + ret, info = platform_reg_read(int(dev_type), int(dev_id), int(offset), int(size)) + print(ret) + if ret is True: + print_reg(info, int(offset)) + else: + print(info) + + +@main.command() +@click.argument('dev_type', required=True) +@click.argument('dev_id', required=True) +@click.argument('offset', required=True) +@click.argument('value', required=True) +def reg_wr(dev_type, dev_id, offset, value): + '''write cpld/fpga reg''' + value_list = [] + value_list.append(int(value)) + ret, info = platform_reg_write(int(dev_type), int(dev_id), int(offset), value_list) + print(ret) + print(info) + + +@main.command() +@click.argument('port', required=True) +def get_optoe_type(port): + '''get optoe type''' + ret, info = platform_get_optoe_type(int(port)) + print(ret) + print(info) + + +@main.command() +@click.argument('port', required=True) +@click.argument('optoe_type', required=True) +def set_optoe_type(port, optoe_type): + '''set optoe type''' + ret, info = platform_set_optoe_type(int(port), int(optoe_type)) + print(ret) + print(info) + + +@main.command() +@click.argument('port_id', required=True) +@click.argument('offset', required=True) +@click.argument('size', required=True) +def sfp_rd(port_id, offset, size): + '''read sfp''' + ret, info = platform_sfp_read(int(port_id), int(offset), int(size)) + print(ret) + if ret is True: + print_reg(info, int(offset)) + else: + print(info) + + +@main.command() +@click.argument('port_id', required=True) +@click.argument('offset', required=True) +@click.argument('value', required=True) +def sfp_wr(port_id, offset, value): + '''write sfp''' + value_list = [] + value_list.append(int(value)) + ret, info = platform_sfp_write(int(port_id), int(offset), value_list) + print(ret) + print(info) + + +if __name__ == '__main__': + main() diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/script/platform_util.py b/platform/broadcom/sonic-platform-modules-ragile/common/script/platform_util.py new file mode 100755 index 000000000000..e7e6c8b1d6eb --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/script/platform_util.py @@ -0,0 +1,845 @@ +#!/usr/bin/python3 + +import sys +import os +import re +import subprocess +import shlex +import time +import mmap +import glob +import logging.handlers +import shutil +import gzip +import ast + + +CONFIG_DB_PATH = "/etc/sonic/config_db.json" +MAILBOX_DIR = "/sys/bus/i2c/devices/" + + +__all__ = [ + "strtoint", + "byteTostr", + "getplatform_name", + "wbi2cget", + "wbi2cset", + "wbpcird", + "wbpciwr", + "wbi2cgetWord", + "wbi2csetWord", + "wbi2cset_pec", + "wbi2cset_wordpec", + "wbsysset", + "dev_file_read", + "dev_file_write", + "wb_os_system", + "io_rd", + "io_wr", + "exec_os_cmd", + "exec_os_cmd_log", + "write_sysfs", + "read_sysfs", + "get_sysfs_value", + "write_sysfs_value", + "get_value", + "set_value", + "getSdkReg", + "getMacTemp", + "getMacTemp_sysfs", + "get_format_value" +] + +class CodeVisitor(ast.NodeVisitor): + + def __init__(self): + self.value = None + + def get_value(self): + return self.value + + def get_op_value(self, node): + if isinstance(node, ast.Call): # node is func call + value = self.visit_Call(node) + elif isinstance(node, ast.BinOp): # node is BinOp + value = self.visit_BinOp(node) + elif isinstance(node, ast.UnaryOp): # node is UnaryOp + value = self.visit_UnaryOp(node) + elif isinstance(node, ast.Num): # node is Num Constant + value = node.n + elif isinstance(node, ast.Str): # node is Str Constant + value = node.s + else: + raise NotImplementedError("Unsupport operand type: %s" % type(node)) + return value + + def visit_UnaryOp(self, node): + ''' + node.op: operand type, only support ast.UAdd/ast.USub + node.operand: only support ast.Call/ast.Constant(ast.Num/ast.Str)/ast.BinOp/ast.UnaryOp + ''' + + operand_value = self.get_op_value(node.operand) + if isinstance(node.op, ast.UAdd): + self.value = operand_value + elif isinstance(node.op, ast.USub): + self.value = 0 - operand_value + else: + raise NotImplementedError("Unsupport arithmetic methods %s" % type(node.op)) + return self.value + + def visit_BinOp(self, node): + ''' + node.left: left operand, only support ast.Call/ast.Constant(ast.Num)/ast.BinOp + node.op: operand type, only support ast.Add/ast.Sub/ast.Mult/ast.Div + node.right: right operan, only support ast.Call/ast.Constant(ast.Num/ast.Str)/ast.BinOp + ''' + left_value = self.get_op_value(node.left) + right_value = self.get_op_value(node.right) + + if isinstance(node.op, ast.Add): + self.value = left_value + right_value + elif isinstance(node.op, ast.Sub): + self.value = left_value - right_value + elif isinstance(node.op, ast.Mult): + self.value = left_value * right_value + elif isinstance(node.op, ast.Div): + self.value = left_value / right_value + else: + raise NotImplementedError("Unsupport arithmetic methods %s" % type(node.op)) + return self.value + + def visit_Call(self, node): + ''' + node.func.id: func name, only support 'float', 'int', 'str' + node.args: func args list,only support ast.Constant(ast.Num/ast.Str)/ast.BinOp/ast.Call + str/float only support one parameter, eg: float(XXX), str(xxx) + int support one or two parameters, eg: int(xxx) or int(xxx, 16) + xxx can be ast.Call/ast.Constant(ast.Num/ast.Str)/ast.BinOp + ''' + calc_tuple = ("float", "int", "str") + + if node.func.id not in calc_tuple: + raise NotImplementedError("Unsupport function call type: %s" % node.func.id) + + args_val_list = [] + for item in node.args: + ret = self.get_op_value(item) + args_val_list.append(ret) + + if node.func.id == "str": + if len(args_val_list) != 1: + raise TypeError("str() takes 1 positional argument but %s were given" % len(args_val_list)) + value = str(args_val_list[0]) + self.value = value + return value + + if node.func.id == "float": + if len(args_val_list) != 1: + raise TypeError("float() takes 1 positional argument but %s were given" % len(args_val_list)) + value = float(args_val_list[0]) + self.value = value + return value + # int + if len(args_val_list) == 1: + value = int(args_val_list[0]) + self.value = value + return value + if len(args_val_list) == 2: + value = int(args_val_list[0], args_val_list[1]) + self.value = value + return value + raise TypeError("int() takes 1 or 2 arguments (%s given)" % len(args_val_list)) + +def inttostr(vl, length): + if not isinstance(vl, int): + raise Exception(" type error") + index = 0 + ret_t = "" + while index < length: + ret = 0xff & (vl >> index * 8) + ret_t += chr(ret) + index += 1 + return ret_t + + +def strtoint(str_tmp): + value = 0 + rest_v = str_tmp.replace("0X", "").replace("0x", "") + str_len = len(rest_v) + for index, val in enumerate(rest_v): + value |= int(val, 16) << ((str_len - index - 1) * 4) + return value + + +def inttobytes(val, length): + if not isinstance(val, int): + raise Exception("type error") + data_array = bytearray() + index = 0 + while index < length: + ret = 0xff & (val >> index * 8) + data_array.append(ret) + index += 1 + return data_array + + +def byteTostr(val): + strtmp = '' + for value in val: + strtmp += chr(value) + return strtmp + + +def typeTostr(val): + strtmp = '' + if isinstance(val, bytes): + strtmp = byteTostr(val) + return strtmp + + +def getonieplatform(path): + if not os.path.isfile(path): + return "" + machine_vars = {} + with open(path) as machine_file: + for line in machine_file: + tokens = line.split('=') + if len(tokens) < 2: + continue + machine_vars[tokens[0]] = tokens[1].strip() + return machine_vars.get("onie_platform") + + +def getplatform_config_db(): + if not os.path.isfile(CONFIG_DB_PATH): + return "" + val = os.popen("sonic-cfggen -j %s -v DEVICE_METADATA.localhost.platform" % CONFIG_DB_PATH).read().strip() + if len(val) <= 0: + return "" + return val + + +def getplatform_name(): + if os.path.isfile('/host/machine.conf'): + return getonieplatform('/host/machine.conf') + if os.path.isfile('/usr/share/sonic/hwsku/machine.conf'): + return getonieplatform('/usr/share/sonic/hwsku/machine.conf') + return getplatform_config_db() + + +def wbi2cget(bus, devno, address, word=None): + if word is None: + command_line = "i2cget -f -y %d 0x%02x 0x%02x " % (bus, devno, address) + else: + command_line = "i2cget -f -y %d 0x%02x 0x%02x %s" % (bus, devno, address, word) + retrytime = 6 + ret_t = "" + for i in range(retrytime): + ret, ret_t = wb_os_system(command_line) + if ret == 0: + return True, ret_t + time.sleep(0.1) + return False, ret_t + + +def wbi2cset(bus, devno, address, byte): + command_line = "i2cset -f -y %d 0x%02x 0x%02x 0x%02x" % ( + bus, devno, address, byte) + retrytime = 6 + ret_t = "" + for i in range(retrytime): + ret, ret_t = wb_os_system(command_line) + if ret == 0: + return True, ret_t + return False, ret_t + + +def wbpcird(pcibus, slot, fn, resource, offset): + '''read pci register''' + if offset % 4 != 0: + return "ERR offset: %d not 4 bytes align" + filename = "/sys/bus/pci/devices/0000:%02x:%02x.%x/resource%d" % (int(pcibus), int(slot), int(fn), int(resource)) + with open(filename, "r+") as file: + size = os.path.getsize(filename) + data = mmap.mmap(file.fileno(), size) + result = data[offset: offset + 4] + s = result[::-1] + val = 0 + for value in s: + val = val << 8 | value + data.close() + return "0x%08x" % val + + +def wbpciwr(pcibus, slot, fn, resource, offset, data): + '''write pci register''' + ret = inttobytes(data, 4) + filename = "/sys/bus/pci/devices/0000:%02x:%02x.%x/resource%d" % (int(pcibus), int(slot), int(fn), int(resource)) + with open(filename, "r+") as file: + size = os.path.getsize(filename) + data = mmap.mmap(file.fileno(), size) + data[offset: offset + 4] = ret + result = data[offset: offset + 4] + s = result[::-1] + val = 0 + for value in s: + val = val << 8 | value + data.close() + + +def wbi2cgetWord(bus, devno, address): + command_line = "i2cget -f -y %d 0x%02x 0x%02x w" % (bus, devno, address) + retrytime = 3 + ret_t = "" + for i in range(retrytime): + ret, ret_t = wb_os_system(command_line) + if ret == 0: + return True, ret_t + return False, ret_t + + +def wbi2csetWord(bus, devno, address, byte): + command_line = "i2cset -f -y %d 0x%02x 0x%02x 0x%x w" % ( + bus, devno, address, byte) + retrytime = 6 + ret_t = "" + for i in range(retrytime): + ret, ret_t = wb_os_system(command_line) + if ret == 0: + return True, ret_t + return False, ret_t + + +def wbi2cset_pec(bus, devno, address, byte): + command_line = "i2cset -f -y %d 0x%02x 0x%02x 0x%02x bp" % ( + bus, devno, address, byte) + retrytime = 6 + ret_t = "" + for i in range(retrytime): + ret, ret_t = wb_os_system(command_line) + if ret == 0: + return True, ret_t + return False, ret_t + + +def wbi2cset_wordpec(bus, devno, address, byte): + command_line = "i2cset -f -y %d 0x%02x 0x%02x 0x%02x wp" % ( + bus, devno, address, byte) + retrytime = 6 + ret_t = "" + for i in range(retrytime): + ret, ret_t = wb_os_system(command_line) + if ret == 0: + return True, ret_t + return False, ret_t + + +def wbsysset(location, value): + command_line = "echo 0x%02x > %s" % (value, location) + retrytime = 6 + ret_t = "" + for i in range(retrytime): + ret, ret_t = wb_os_system(command_line) + if ret == 0: + return True, ret_t + return False, ret_t + + +def dev_file_read(path, offset, read_len): + val_list = [] + msg = "" + ret = "" + fd = -1 + + if not os.path.exists(path): + msg = path + " not found !" + return False, msg + + try: + fd = os.open(path, os.O_RDONLY) + os.lseek(fd, offset, os.SEEK_SET) + ret = os.read(fd, read_len) + for item in ret: + val_list.append(item) + except Exception as e: + msg = str(e) + return False, msg + finally: + if fd > 0: + os.close(fd) + return True, val_list + + +def dev_file_write(path, offset, buf_list): + msg = "" + fd = -1 + + if not isinstance(buf_list, list) or len(buf_list) == 0: + msg = "buf:%s is not list type or is NONE !" % buf_list + return False, msg + + if not os.path.exists(path): + msg = path + " not found !" + return False, msg + + try: + fd = os.open(path, os.O_WRONLY) + os.lseek(fd, offset, os.SEEK_SET) + ret = os.write(fd, bytes(buf_list)) + except Exception as e: + msg = str(e) + return False, msg + finally: + if fd > 0: + os.close(fd) + + return True, ret + + +def wb_os_system(cmd): + status, output = subprocess.getstatusoutput(cmd) + return status, output + + +def io_rd(reg_addr, read_len=1): + try: + regaddr = 0 + if isinstance(reg_addr, int): + regaddr = reg_addr + else: + regaddr = int(reg_addr, 16) + devfile = "/dev/port" + fd = os.open(devfile, os.O_RDWR | os.O_CREAT) + os.lseek(fd, regaddr, os.SEEK_SET) + val = os.read(fd, read_len) + return "".join(["%02x" % item for item in val]) + except ValueError: + return None + except Exception as e: + print(e) + return None + finally: + os.close(fd) + + +def io_wr(reg_addr, reg_data): + try: + regdata = 0 + regaddr = 0 + if isinstance(reg_addr, int): + regaddr = reg_addr + else: + regaddr = int(reg_addr, 16) + if isinstance(reg_data, int): + regdata = reg_data + else: + regdata = int(reg_data, 16) + devfile = "/dev/port" + fd = os.open(devfile, os.O_RDWR | os.O_CREAT) + os.lseek(fd, regaddr, os.SEEK_SET) + os.write(fd, regdata.to_bytes(1, 'little')) + return True + except ValueError as e: + print(e) + return False + except Exception as e: + print(e) + return False + finally: + os.close(fd) + + +def exec_os_cmd(cmd): + cmds = cmd.split('|') + procs = [] + for i, c in enumerate(cmds): + stdin = None if i == 0 else procs[i-1].stdout + p = subprocess.Popen(shlex.split(c), stdin=stdin, stdout=subprocess.PIPE, shell=False, stderr=subprocess.STDOUT) + procs.append(p) + for proc in procs: + proc.wait() + return procs[-1].returncode, typeTostr(procs[-1].communicate()[0]) + + +def exec_os_cmd_log(cmd): + proc = subprocess.Popen(shlex.split(cmd), stdin=subprocess.PIPE, shell=False, stderr=sys.stderr, close_fds=True, + stdout=sys.stdout, universal_newlines=True, bufsize=1) + proc.wait() + stdout = proc.communicate()[0] + stdout = typeTostr(stdout) + return proc.returncode, stdout + + +def write_sysfs(location, value): + try: + if not os.path.isfile(location): + return False, ("location[%s] not found !" % location) + with open(location, 'w') as fd1: + fd1.write(value) + except Exception as e: + return False, (str(e) + " location[%s]" % location) + return True, ("set location[%s] %s success !" % (location, value)) + + +def read_sysfs(location): + try: + locations = glob.glob(location) + with open(locations[0], 'rb') as fd1: + retval = fd1.read() + retval = typeTostr(retval) + retval = retval.rstrip('\r\n') + retval = retval.lstrip(" ") + except Exception as e: + return False, (str(e) + "location[%s]" % location) + return True, retval + + +def get_pmc_register(reg_name): + retval = 'ERR' + mb_reg_file = MAILBOX_DIR + reg_name + filepath = glob.glob(mb_reg_file) + if len(filepath) == 0: + return "%s %s notfound" % (retval, mb_reg_file) + mb_reg_file = filepath[0] + if not os.path.isfile(mb_reg_file): + return "%s %s notfound" % (retval, mb_reg_file) + try: + with open(mb_reg_file, 'r') as fd: + retval = fd.read() + except Exception as error: + retval = retval + str(error) + retval = retval.rstrip('\r\n') + retval = retval.lstrip(" ") + return retval + + +def get_sysfs_value(location): + pos_t = str(location) + name = get_pmc_register(pos_t) + return name + + +def write_sysfs_value(reg_name, value): + fileLoc = MAILBOX_DIR + reg_name + try: + if not os.path.isfile(fileLoc): + print(fileLoc, 'not found !') + return False + with open(fileLoc, 'w') as fd: + fd.write(value) + except Exception: + print("Unable to open " + fileLoc + "file !") + return False + return True + + +def get_value_once(config): + try: + way = config.get("gettype") + int_decode = config.get("int_decode", 16) + if way == 'sysfs': + loc = config.get("loc") + ret, val = read_sysfs(loc) + if ret is True: + return True, int(val, int_decode) + return False, ("sysfs read %s failed. log:%s" % (loc, val)) + if way == "i2c": + bus = config.get("bus") + addr = config.get("loc") + offset = config.get("offset", 0) + ret, val = wbi2cget(bus, addr, offset) + if ret is True: + return True, int(val, int_decode) + return False, ("i2c read failed. bus:%d , addr:0x%x, offset:0x%x" % (bus, addr, offset)) + if way == "io": + io_addr = config.get('io_addr') + val = io_rd(io_addr) + if len(val) != 0: + return True, int(val, int_decode) + return False, ("io_addr read 0x%x failed" % io_addr) + if way == "i2cword": + bus = config.get("bus") + addr = config.get("loc") + offset = config.get("offset") + ret, val = wbi2cgetWord(bus, addr, offset) + if ret is True: + return True, int(val, int_decode) + return False, ("i2cword read failed. bus:%d, addr:0x%x, offset:0x%x" % (bus, addr, offset)) + if way == "devfile": + path = config.get("path") + offset = config.get("offset") + read_len = config.get("read_len") + ret, val_list = dev_file_read(path, offset, read_len) + if ret is True: + return True, val_list + return False, ("devfile read failed. path:%s, offset:0x%x, read_len:%d" % (path, offset, read_len)) + if way == 'cmd': + cmd = config.get("cmd") + ret, val = exec_os_cmd(cmd) + if ret: + return False, ("cmd read exec %s failed, log: %s" % (cmd, val)) + return True, int(val, int_decode) + if way == 'file_exist': + judge_file = config.get('judge_file', None) + if os.path.exists(judge_file): + return True, True + return True, False + return False, "not support read type" + except Exception as e: + return False, ("get_value_once exception:%s happen" % str(e)) + + +def set_value_once(config): + try: + delay_time = config.get("delay", None) + if delay_time is not None: + time.sleep(delay_time) + + way = config.get("gettype") + if way == 'sysfs': + loc = config.get("loc") + value = config.get("value") + mask = config.get("mask", 0xff) + mask_tuple = (0xff, 0) + if mask not in mask_tuple: + ret, read_value = read_sysfs(loc) + if ret is True: + read_value = int(read_value, base=16) + value = (read_value & mask) | value + else: + return False, ("sysfs read %s failed. log:%s" % (loc, read_value)) + ret, log = write_sysfs(loc, "0x%02x" % value) + if ret is not True: + return False, ("sysfs %s write 0x%x failed" % (loc, value)) + return True, ("sysfs write 0x%x success" % value) + if way == "i2c": + bus = config.get("bus") + addr = config.get("loc") + offset = config.get("offset") + value = config.get("value") + mask = config.get("mask", 0xff) + mask_tuple = (0xff, 0) + if mask not in mask_tuple: + ret, read_value = wbi2cget(bus, addr, offset) + if ret is True: + read_value = int(read_value, base=16) + value = (read_value & mask) | value + else: + return False, ("i2c read failed. bus:%d , addr:0x%x, offset:0x%x" % (bus, addr, offset)) + ret, log = wbi2cset(bus, addr, offset, value) + if ret is not True: + return False, ("i2c write bus:%d, addr:0x%x, offset:0x%x, value:0x%x failed" % + (bus, addr, offset, value)) + return True, ("i2c write bus:%d, addr:0x%x, offset:0x%x, value:0x%x success" % + (bus, addr, offset, value)) + if way == "io": + io_addr = config.get('io_addr') + value = config.get('value') + mask = config.get("mask", 0xff) + mask_tuple = (0xff, 0) + if mask not in mask_tuple: + read_value = io_rd(io_addr) + if read_value is None: + return False, ("io_addr 0x%x read failed" % (io_addr)) + read_value = int(read_value, base=16) + value = (read_value & mask) | value + ret = io_wr(io_addr, value) + if ret is not True: + return False, ("io_addr 0x%x write 0x%x failed" % (io_addr, value)) + return True, ("io_addr 0x%x write 0x%x success" % (io_addr, value)) + if way == 'i2cword': + bus = config.get("bus") + addr = config.get("loc") + offset = config.get("offset") + value = config.get("value") + mask = config.get("mask", 0xff) + mask_tuple = (0xff, 0) + if mask not in mask_tuple: + ret, read_value = wbi2cgetWord(bus, addr, offset) + if ret is True: + read_value = int(read_value, base=16) + value = (read_value & mask) | value + else: + return False, ("i2c read word failed. bus:%d , addr:0x%x, offset:0x%x" % (bus, addr, offset)) + ret, log = wbi2csetWord(bus, addr, offset, value) + if ret is not True: + return False, ("i2cword write bus:%d, addr:0x%x, offset:0x%x, value:0x%x failed" % + (bus, addr, offset, value)) + return True, ("i2cword write bus:%d, addr:0x%x, offset:0x%x, value:0x%x success" % + (bus, addr, offset, value)) + if way == "devfile": + path = config.get("path") + offset = config.get("offset") + buf_list = config.get("value") + ret, log = dev_file_write(path, offset, buf_list) + if ret is True: + return True, ("devfile write path:%s, offset:0x%x, buf_list:%s success." % (path, offset, buf_list)) + return False, ("devfile read path:%s, offset:0x%x, buf_list:%s failed.log:%s" % + (path, offset, buf_list, log)) + if way == 'cmd': + cmd = config.get("cmd") + ret, log = exec_os_cmd(cmd) + if ret: + return False, ("cmd write exec %s failed, log: %s" % (cmd, log)) + return True, ("cmd write exec %s success" % cmd) + if way == 'bit_wr': + mask = config.get("mask") + bit_val = config.get("value") + val_config = config.get("val_config") + ret, rd_value = get_value_once(val_config) + if ret is False: + return False, ("bit_wr read failed, log: %s" % rd_value) + wr_val = (rd_value & mask) | bit_val + val_config["value"] = wr_val + ret, log = set_value_once(val_config) + if ret is False: + return False, ("bit_wr failed, log: %s" % log) + return True, ("bit_wr success, log: %s" % log) + if way == 'creat_file': + file_name = config.get("file") + ret, log = exec_os_cmd("touch %s" % file_name) + if ret: + return False, ("creat file %s failed, log: %s" % (file_name, log)) + exec_os_cmd("sync") + return True, ("creat file %s success" % file_name) + if way == 'remove_file': + file_name = config.get("file") + ret, log = exec_os_cmd("rm -rf %s" % file_name) + if ret: + return False, ("remove file %s failed, log: %s" % (file_name, log)) + exec_os_cmd("sync") + return True, ("remove file %s success" % file_name) + return False, "not support write type" + except Exception as e: + return False, ("set_value_once exception:%s happen" % str(e)) + + +def get_value(config): + retrytime = 6 + for i in range(retrytime): + ret, val = get_value_once(config) + if ret is True: + return True, val + time.sleep(0.1) + return False, val + + +def set_value(config): + retrytime = 6 + ignore_result_flag = config.get("ignore_result", 0) + for i in range(retrytime): + ret, log = set_value_once(config) + if ret is True: + return True, log + if ignore_result_flag == 1: + return True, log + time.sleep(0.1) + return False, log + + +class CompressedRotatingFileHandler(logging.handlers.RotatingFileHandler): + def doRollover(self): + """ + Do a rollover, as described in __init__(). + """ + if self.stream: + self.stream.close() + self.stream = None + if self.backupCount > 0: + for i in range(self.backupCount - 1, 0, -1): + sfn = "%s.%d.gz" % (self.baseFilename, i) + dfn = "%s.%d.gz" % (self.baseFilename, i + 1) + if os.path.exists(sfn): + if os.path.exists(dfn): + os.remove(dfn) + os.rename(sfn, dfn) + dfn = self.baseFilename + ".1.gz" + if os.path.exists(dfn): + os.remove(dfn) + # These two lines below are the only new lines. I commented out the os.rename(self.baseFilename, dfn) and + # replaced it with these two lines. + with open(self.baseFilename, 'rb') as f_in, gzip.open(dfn, 'wb') as f_out: + shutil.copyfileobj(f_in, f_out) + self.mode = 'w' + self.stream = self._open() + + +def getSdkReg(reg): + try: + cmd = "bcmcmd -t 1 'getr %s ' < /dev/null" % reg + ret, result = wb_os_system(cmd) + result_t = result.strip().replace("\r", "").replace("\n", "") + if ret != 0 or "Error:" in result_t: + return False, result + patt = r"%s.(.*):(.*)>drivshell" % reg + rt = re.findall(patt, result_t, re.S) + test = re.findall("=(.*)", rt[0][0])[0] + except Exception: + return False, 'getsdk register error' + return True, test + + +def getMacTemp(): + result = {} + wb_os_system("bcmcmd -t 1 \"show temp\" < /dev/null") + ret, log = wb_os_system("bcmcmd -t 1 \"show temp\" < /dev/null") + if ret: + return False, result + logs = log.splitlines() + for line in logs: + if "average" in line: + b = re.findall(r'\d+.\d+', line) + result["average"] = b[0] + elif "maximum" in line: + b = re.findall(r'\d+.\d+', line) + result["maximum"] = b[0] + return True, result + + +def getMacTemp_sysfs(mactempconf): + temp = -1000000 + try: + temp_list = [] + mac_temp_loc = mactempconf.get("loc", []) + mac_temp_flag = mactempconf.get("flag", None) + if mac_temp_flag is not None: + gettype = mac_temp_flag.get('gettype') + okbit = mac_temp_flag.get('okbit') + okval = mac_temp_flag.get('okval') + if gettype == "io": + io_addr = mac_temp_flag.get('io_addr') + val = io_rd(io_addr) + if val is None: + raise Exception("get mac_flag by io failed.") + else: + bus = mac_temp_flag.get('bus') + loc = mac_temp_flag.get('loc') + offset = mac_temp_flag.get('offset') + ind, val = wbi2cget(bus, loc, offset) + if ind is not True: + raise Exception("get mac_flag by i2c failed.") + val_t = (int(val, 16) & (1 << okbit)) >> okbit + if val_t != okval: + raise Exception("mac_flag invalid, val_t:%d." % val_t) + for loc in mac_temp_loc: + temp_s = get_sysfs_value(loc) + if isinstance(temp_s, str) and temp_s.startswith("ERR"): + raise Exception("get mac temp error. loc:%s" % loc) + temp_t = int(temp_s) + if temp_t == -1000000: + raise Exception("mac temp invalid.loc:%s" % loc) + temp_list.append(temp_t) + temp_list.sort(reverse=True) + temp = temp_list[0] + except Exception: + return False, temp + return True, temp + +def get_format_value(format_str): + ast_obj = ast.parse(format_str, mode='eval') + visitor = CodeVisitor() + visitor.visit(ast_obj) + ret = visitor.get_value() + return ret + diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/script/pmon_syslog.py b/platform/broadcom/sonic-platform-modules-ragile/common/script/pmon_syslog.py new file mode 100755 index 000000000000..8bdceef8c1b5 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/script/pmon_syslog.py @@ -0,0 +1,519 @@ +#!/usr/bin/python3 +# * onboard interval check +# * FAN trays +# * PSU +# * SFF +import time +import syslog +import traceback +import glob +from platform_config import PMON_SYSLOG_STATUS + +PMON_DEBUG_FILE = "/etc/.pmon_syslog_debug_flag" +debuglevel = 0 +PMONERROR = 1 +PMONDEBUG = 2 + + +def pmon_debug(s): + if PMONDEBUG & debuglevel: + syslog.openlog("PMON_SYSLOG", syslog.LOG_PID) + syslog.syslog(syslog.LOG_DEBUG, s) + + +def pmon_error(s): + if PMONERROR & debuglevel: + syslog.openlog("PMON_SYSLOG", syslog.LOG_PID) + syslog.syslog(syslog.LOG_ERR, s) + + +def dev_syslog(s): + syslog.openlog("PMON_SYSLOG", syslog.LOG_PID) + syslog.syslog(syslog.LOG_LOCAL1 | syslog.LOG_NOTICE, s) + + +# status +STATUS_PRESENT = 'PRESENT' +STATUS_ABSENT = 'ABSENT' +STATUS_OK = 'OK' +STATUS_NOT_OK = 'NOT OK' +STATUS_FAILED = 'FAILED' + + +class checkBase(object): + def __init__(self, path, dev_name, display_name, obj_type, config): + self._peroid_syslog = None + self._peroid_failed_syslog = None # exception + self._preDevStatus = None + self._path = path + self._name = dev_name + self._display_name = display_name + self._type = obj_type + self._config = config + + def getCurstatus(self): + # get ok/not ok/absent status + status, log = self.getPresent() + if status == STATUS_PRESENT: + # check status + property_status, log = self.getStatus() + if property_status is not None: + status = property_status + return status, log + + def getPresent(self): + presentFilepath = self.getPath() + try: + # get ok/not ok/absent status + presentConfig = self._config["present"] + mask = presentConfig.get("mask", 0xff) + absent_val = presentConfig.get("ABSENT", None) + absent_val = absent_val & mask + with open(presentFilepath, "r") as fd: + retval = fd.read() + if int(retval) == absent_val: + return STATUS_ABSENT, None + return STATUS_PRESENT, None + except Exception as e: + return STATUS_FAILED, (str(e) + " location[%s]" % presentFilepath) + + def getStatus(self): + if "status" in self._config: + statusConfig = self._config["status"] + for itemConfig in statusConfig: + mask = itemConfig.get("mask", 0xff) + ok_val = itemConfig.get("okval", None) + ok_val = ok_val & mask + Filepath = itemConfig["path"] % self._name + try: + with open(Filepath, "r") as fd1: + retval = fd1.read() + if int(retval) != ok_val: + return STATUS_NOT_OK, None + except Exception as e: + return STATUS_FAILED, (str(e) + " location[%s]" % Filepath) + return STATUS_OK, None + return None, None + + def getPath(self): + return self._path + + def getName(self): + return self._name + + def getType(self): + return self._type + + def getDisplayName(self): + return self._display_name + + def getnochangedMsgFlag(self): + return self._config["nochangedmsgflag"] + + def getnochangedMsgTime(self): + return self._config["nochangedmsgtime"] + + def getnoprintFirstTimeFlag(self): + return self._config["noprintfirsttimeflag"] + + def checkStatus(self): + # syslog msg + dev_type = self.getType() + display_name = self.getDisplayName() + nochangedMsgTime = self.getnochangedMsgTime() + getnochangedMsgFlag = self.getnochangedMsgFlag() + noprintFirstTimeFlag = self.getnoprintFirstTimeFlag() + MSG_IN = '%%PMON-5-' + dev_type + '_PLUG_IN: %s is PRESENT.' + MSG_OUT = '%%PMON-5-' + dev_type + '_PLUG_OUT: %s is ABSENT.' + MSG_OK = '%%PMON-5-' + dev_type + '_OK: %s is OK.' + MSG_NOT_OK = '%%PMON-5-' + dev_type + '_FAILED: %s is NOT OK.' + MSG_ABSENT = '%%PMON-5-' + dev_type + '_ABSENT: %s is ABSENT.' + MSG_UNKNOWN = '%%PMON-5-' + dev_type + '_UNKNOWN: %s is UNKNOWN.%s' + MSG_RECOVER = '%%PMON-5-' + dev_type + '_OK: %s is OK. Recover from ' + dev_type + ' FAILED.' + + curStatus, log = self.getCurstatus() + pmon_debug("%s: current status %s" % (display_name, curStatus)) + pmon_debug("%s: pre status %s" % (display_name, self._preDevStatus)) + pmon_debug("%s: peroid_syslog %s" % (display_name, self._peroid_syslog)) + + if curStatus == STATUS_FAILED: + # get status failed + if self._peroid_failed_syslog is not None: + if getnochangedMsgFlag and time.time() - self._peroid_failed_syslog >= nochangedMsgTime: + # absent as before for some time, notice + dev_syslog(MSG_UNKNOWN % (display_name, log)) + self._peroid_failed_syslog = time.time() + else: # first time failed + dev_syslog(MSG_UNKNOWN % (display_name, log)) + self._peroid_failed_syslog = time.time() + return + self._peroid_failed_syslog = time.time() + + if self._preDevStatus is None: + # 1st time + if noprintFirstTimeFlag == 1: + self._peroid_syslog = time.time() + else: + if curStatus == STATUS_PRESENT: + # present + dev_syslog(MSG_IN % display_name) + elif curStatus == STATUS_OK: + # ok + dev_syslog(MSG_OK % display_name) + elif curStatus == STATUS_NOT_OK: + # not ok + dev_syslog(MSG_NOT_OK % display_name) + self._peroid_syslog = time.time() + else: + # absent + dev_syslog(MSG_ABSENT % display_name) + self._peroid_syslog = time.time() + else: + # from 2nd time... + if self._preDevStatus == curStatus: + # status not changed + if self._preDevStatus == STATUS_ABSENT: + if self._peroid_syslog is not None: + if getnochangedMsgFlag and time.time() - self._peroid_syslog >= nochangedMsgTime: + # absent as before for some time, notice + dev_syslog(MSG_ABSENT % display_name) + self._peroid_syslog = time.time() + elif self._preDevStatus == STATUS_NOT_OK: + if self._peroid_syslog is not None: + if getnochangedMsgFlag and time.time() - self._peroid_syslog >= nochangedMsgTime: + # not ok as before for some time, notice + dev_syslog(MSG_NOT_OK % display_name) + self._peroid_syslog = time.time() + else: + # status changed + if self._preDevStatus == STATUS_ABSENT: + if curStatus == STATUS_NOT_OK: + # absent -> not ok + dev_syslog(MSG_IN % display_name) + dev_syslog(MSG_NOT_OK % display_name) + self._peroid_syslog = time.time() + elif curStatus == STATUS_OK: + # absent -> ok + dev_syslog(MSG_IN % display_name) + dev_syslog(MSG_OK % display_name) + else: + # absent -> prsent + dev_syslog(MSG_IN % display_name) + + elif self._preDevStatus == STATUS_OK: + if curStatus == STATUS_NOT_OK: + # ok -> not ok + dev_syslog(MSG_NOT_OK % display_name) + self._peroid_syslog = time.time() + elif curStatus == STATUS_ABSENT: + # ok -> absent + dev_syslog(MSG_OUT % display_name) + self._peroid_syslog = time.time() + elif self._preDevStatus == STATUS_PRESENT: + # present -> absent + dev_syslog(MSG_OUT % display_name) + self._peroid_syslog = time.time() + else: # not ok + if curStatus == STATUS_OK: + # not ok -> ok + dev_syslog(MSG_RECOVER % display_name) + dev_syslog(MSG_OK % display_name) + else: + # not ok -> absent + dev_syslog(MSG_OUT % display_name) + self._peroid_syslog = time.time() + self._preDevStatus = curStatus + + +class checkSfp(checkBase): + def __init__(self, path, dev_name, display_name, config): + super(checkSfp, self).__init__(path, dev_name, display_name, 'XCVR', config) + + def getPath(self): + super(checkSfp, self).getPath() + return self._path + + def getName(self): + super(checkSfp, self).getName() + return self._name + + def getType(self): + super(checkSfp, self).getType() + return self._type + + +class checkSlot(checkBase): + def __init__(self, path, dev_name, display_name, config): + super(checkSlot, self).__init__(path, dev_name, display_name, 'SLOT', config) + + def getPath(self): + super(checkSlot, self).getPath() + return self._path + + def getName(self): + super(checkSlot, self).getName() + return self._name + + def getType(self): + super(checkSlot, self).getType() + return self._type + + +class checkPSU(checkBase): + def __init__(self, path, dev_name, display_name, config): + super(checkPSU, self).__init__(path, dev_name, display_name, 'PSU', config) + + def getPath(self): + super(checkPSU, self).getPath() + return self._path + + def getName(self): + super(checkPSU, self).getName() + return self._name + + def getType(self): + super(checkPSU, self).getType() + return self._type + + +class checkFAN(checkBase): + def __init__(self, path, dev_name, display_name, config): + super(checkFAN, self).__init__(path, dev_name, display_name, 'FAN', config) + + def getPath(self): + super(checkFAN, self).getPath() + return self._path + + def getName(self): + super(checkFAN, self).getName() + return self._name + + def getType(self): + super(checkFAN, self).getType() + return self._type + + +class platformSyslog(): + def __init__(self): + self.__sfp_checklist = [] + self.__fan_checklist = [] + self.__psu_checklist = [] + self.__slot_checklist = [] + self.__temp_checklist = [] + self.temps_peroid_syslog = {} + self.normal_status = 0 + self.warning_status = 1 + self.critical_status = 2 + self.poweron_flag = 0 + + self.pmon_syslog_config = PMON_SYSLOG_STATUS.copy() + self.__pollingtime = self.pmon_syslog_config.get('polling_time', 3) + + tmpconfig = self.pmon_syslog_config.get('sffs', None) + if tmpconfig is not None: + preset_item = tmpconfig.get("present", {}) + path = preset_item.get("path", []) + for location in path: + if '*' not in location: + pmon_error("sff location config error: %s" % location) + continue + dev_name_index = 0 + loc_split_list = location.split('/') + for i, item in enumerate(loc_split_list): + if '*' in item: + dev_name_index = i + break + locations = glob.glob(location) + for dev_path in locations: + dev_name_list = dev_path.split('/') + # explame:get eth1 from /sys_switch/transceiver/eth1/present + dev_name = dev_name_list[dev_name_index] + dev_name_alias = tmpconfig.get("alias", {}) + display_name = dev_name_alias.get(dev_name, dev_name) + dev = checkSfp(dev_path, dev_name, display_name, tmpconfig) + self.__sfp_checklist.append(dev) + + tmpconfig = self.pmon_syslog_config.get('fans', None) + if tmpconfig is not None: + preset_item = tmpconfig.get("present", {}) + path = preset_item.get("path", []) + for location in path: + if '*' not in location: + pmon_error("fan location config error: %s" % location) + continue + dev_name_index = 0 + loc_split_list = location.split('/') + for i, item in enumerate(loc_split_list): + if '*' in item: + dev_name_index = i + break + locations = glob.glob(location) + for dev_path in locations: + dev_name_list = dev_path.split('/') + dev_name = dev_name_list[dev_name_index] + dev_name_alias = tmpconfig.get("alias", {}) + display_name = dev_name_alias.get(dev_name, dev_name) + dev = checkFAN(dev_path, dev_name, display_name, tmpconfig) + self.__fan_checklist.append(dev) + + tmpconfig = self.pmon_syslog_config.get('psus', None) + if tmpconfig is not None: + preset_item = tmpconfig.get("present", {}) + path = preset_item.get("path", []) + for location in path: + if '*' not in location: + pmon_error("psu location config error: %s" % location) + continue + dev_name_index = 0 + loc_split_list = location.split('/') + for i, item in enumerate(loc_split_list): + if '*' in item: + dev_name_index = i + break + locations = glob.glob(location) + for dev_path in locations: + dev_name_list = dev_path.split('/') + dev_name = dev_name_list[dev_name_index] + dev_name_alias = tmpconfig.get("alias", {}) + display_name = dev_name_alias.get(dev_name, dev_name) + dev = checkPSU(dev_path, dev_name, display_name, tmpconfig) + self.__psu_checklist.append(dev) + + tmpconfig = self.pmon_syslog_config.get('slots', None) + if tmpconfig is not None: + preset_item = tmpconfig.get("present", {}) + path = preset_item.get("path", []) + for location in path: + if '*' not in location: + pmon_error("slot location config error: %s" % location) + continue + dev_name_index = 0 + loc_split_list = location.split('/') + for i, item in enumerate(loc_split_list): + if '*' in item: + dev_name_index = i + break + locations = glob.glob(location) + for dev_path in locations: + dev_name_list = dev_path.split('/') + dev_name = dev_name_list[dev_name_index] + dev_name_alias = tmpconfig.get("alias", {}) + display_name = dev_name_alias.get(dev_name, dev_name) + dev = checkSlot(dev_path, dev_name, display_name, tmpconfig) + self.__slot_checklist.append(dev) + + tmpconfig = self.pmon_syslog_config.get('temps', None) + if tmpconfig is not None: + self.__temp_checklist = tmpconfig.get('temps_list', []) + self.__temps_pollingseconds = tmpconfig.get('over_temps_polling_seconds', None) + + def checkTempStaus(self, temp_item): + temp_name = temp_item.get('name', None) + input_path = temp_item.get('input_path', None) + warning_temp = temp_item.get('warning', None) + critical_temp = temp_item.get('critical', None) + input_accuracy = temp_item.get('input_accuracy', None) + if temp_name is None or input_path is None or warning_temp is None or critical_temp is None: + dev_syslog('%%PMON-5-TEMP_NOTICE: get temperature config parament failed.') + return + try: + locations = glob.glob(input_path) + with open(locations[0], "r") as fd: + input_temp = fd.read() + input_temp = float(input_temp) / float(input_accuracy) + + if 'time' not in temp_item: + temp_item['time'] = time.time() + temp_item['status'] = self.normal_status + if float(input_temp) >= float(warning_temp): + if float(input_temp) >= float(critical_temp): + if time.time() - \ + temp_item['time'] >= self.__temps_pollingseconds or temp_item['status'] != self.critical_status: + dev_syslog('%%PMON-5-TEMP_HIGH: %s temperature %sC is larger than max critical threshold %sC.' + % (temp_name, input_temp, critical_temp)) + temp_item['status'] = self.critical_status + temp_item['time'] = time.time() + else: + if time.time() - \ + temp_item['time'] >= self.__temps_pollingseconds or temp_item['status'] != self.warning_status: + dev_syslog('%%PMON-5-TEMP_HIGH: %s temperature %sC is larger than max warning threshold %sC.' + % (temp_name, input_temp, warning_temp)) + temp_item['status'] = self.warning_status + temp_item['time'] = time.time() + else: + pmon_debug( + "%s temperature %sC is in range [%s, %s]" % + (temp_name, input_temp, warning_temp, critical_temp)) + temp_item['status'] = self.normal_status + temp_item['time'] = time.time() + except Exception as e: + dev_syslog('%%PMON-5-TEMP_NOTICE: Cannot get %s temperature. Exception log: %s' % (temp_name, str(e))) + return + + def sysfs_precondition_check(self, check_module, check_project): + try: + tmpconfig = self.pmon_syslog_config.get(check_module, None) + if tmpconfig is not None: + check_list = tmpconfig.get(check_project, []) + for check_item in check_list: + location = check_item.get("path", None) + ok_val = check_item.get("ok_val", None) + mask = check_item.get("mask", 0xff) + ok_val = ok_val & mask + locations = glob.glob(location) + for power_path in locations: + with open(power_path, "r") as fd: + retval = fd.read() + if int(retval) != ok_val: + return + self.poweron_flag = 1 + except Exception as e: + dev_syslog('%%PMON-5-TEMP_NOTICE: Cannot check power status. Exception log: %s' % str(e)) + return + + def updateSysDeviceStatus(self): + if self.poweron_flag == 1: + for dev in self.__sfp_checklist: + dev.checkStatus() + else: + self.sysfs_precondition_check('sffs', 'power') + + for dev in self.__fan_checklist: + dev.checkStatus() + for dev in self.__psu_checklist: + dev.checkStatus() + for dev in self.__slot_checklist: + dev.checkStatus() + for temp_item in self.__temp_checklist: + self.checkTempStaus(temp_item) + + def getPollingtime(self): + return self.__pollingtime + + def debug_init(self): + global debuglevel + try: + with open(PMON_DEBUG_FILE, "r") as fd: + value = fd.read() + debuglevel = int(value) + except Exception: + debuglevel = 0 + + def doWork(self): + try: + self.debug_init() + self.updateSysDeviceStatus() + except Exception as e: + MSG_EXCEPTION = '%%PMON-5-NOTICE: Exception happened! info:%s' % str(e) + pmon_error(MSG_EXCEPTION % traceback.format_exc()) + + +def run(): + platform = platformSyslog() + while True: + platform.doWork() + time.sleep(platform.getPollingtime()) + + +if __name__ == '__main__': + run() diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/script/ragilecommon.py b/platform/broadcom/sonic-platform-modules-ragile/common/script/ragilecommon.py deleted file mode 100755 index 0adad9d74659..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/common/script/ragilecommon.py +++ /dev/null @@ -1,1365 +0,0 @@ -# -*- coding: UTF-8 -*- -# ------------------------------------------------------------------------------- -# Name: Ragile python common module -# Purpose: called by other modules -# -# Author: support -# -# Created: 02/07/2018 -# Copyright: (c) rd 2018 -# ------------------------------------------------------------------------------- - -################################driver-load-adaption####################################################### -# need to export interface -################################################################################################### - -__all__ = [ - "fancontrol_loc", - "fancontrol_config_loc", - "GLOBALCONFIG", - "MONITOR_CONST", - "RAGILE_PART_NUMBER", - "RAGILE_LABEL_REVISION", - "RAGILE_ONIE_VERSION", - "RAGILE_MAC_SIZE", - "RAGILE_MANUF_NAME", - "RAGILE_MANUF_COUNTRY", - "RAGILE_VENDOR_NAME", - "RAGILE_DIAG_VERSION", - "RAGILE_SERVICE_TAG", - "DEV_LEDS", - "MEM_SLOTS", - "LOCAL_LED_CONTROL", - "FIRMWARE_TOOLS", - "STARTMODULE", - "i2ccheck_params", - "FANS_DEF", - "factest_module", - "MONITOR_TEMP_MIN", - "MONITOR_K", - "MONITOR_MAC_IN", - "MONITOR_DEFAULT_SPEED", - "MONITOR_MAX_SPEED", - "MONITOR_MIN_SPEED", - "MONITOR_MAC_ERROR_SPEED", - "MONITOR_FAN_TOTAL_NUM", - "MONITOR_MAC_UP_TEMP", - "MONITOR_MAC_LOWER_TEMP", - "MONITOR_MAC_MAX_TEMP", - "MONITOR_FALL_TEMP", - "MONITOR_MAC_WARNING_THRESHOLD", - "MONITOR_OUTTEMP_WARNING_THRESHOLD", - "MONITOR_BOARDTEMP_WARNING_THRESHOLD", - "MONITOR_CPUTEMP_WARNING_THRESHOLD", - "MONITOR_INTEMP_WARNING_THRESHOLD", - "MONITOR_MAC_CRITICAL_THRESHOLD", - "MONITOR_OUTTEMP_CRITICAL_THRESHOLD", - "MONITOR_BOARDTEMP_CRITICAL_THRESHOLD", - "MONITOR_CPUTEMP_CRITICAL_THRESHOLD", - "MONITOR_INTEMP_CRITICAL_THRESHOLD", - "MONITOR_CRITICAL_NUM", - "MONITOR_SHAKE_TIME", - "MONITOR_INTERVAL", - "MONITOR_MAC_SOURCE_SYSFS", - "MONITOR_MAC_SOURCE_PATH", - "MAC_AVS_PARAM", - "MAC_DEFAULT_PARAM", - "MONITOR_SYS_LED", - "MONITOR_SYS_FAN_LED", - "MONITOR_FANS_LED", - "MONITOR_SYS_PSU_LED", - "MONITOR_FAN_STATUS", - "MONITOR_PSU_STATUS", - "MONITOR_DEV_STATUS", - "MONITOR_DEV_STATUS_DECODE", - "DEV_MONITOR_PARAM", - "SLOT_MONITOR_PARAM", - "fanloc", - "PCA9548START", - "PCA9548BUSEND", - "RAGILE_CARDID", - "RAGILE_PRODUCTNAME", - "FAN_PROTECT", - "rg_eeprom", - "E2_LOC", - "E2_PROTECT", - "MAC_LED_RESET", - "INIT_PARAM", - "INIT_COMMAND", - "CPLDVERSIONS", - "DRIVERLISTS", - "DEVICE", - "E2TYPE", - "FRULISTS", - "fanlevel_6510", - "fanlevel_6520", - "fanlevel", - "TEMPIDCHANGE", - "FACTESTMODULE", - "item1", - "test_sys_reload_item", - "test_sys_item", - "test_temp_item", - "test_mem_item", - "test_hd_item", - "test_rtc_item", - "test_i2c_item", - "test_cpld_item", - "test_portframe_item", - "test_sysled_item", - "test_fan_item", - "test_power_item", - "test_usb_item", - "test_prbs_item", - "test_portbroadcast_item", - "test_debug_level", - "test_log_level", - "test_setmac", - "test_setrtc", - "log_level_critical", - "log_level_debug", - "log_level_error", - "log_level_info", - "log_level_notset", - "log_level_warning", - "test_e2_setmac_item", - "test_bmc_setmac_item", - "test_fan_setmac_item", - "alltest", - "looptest", - "diagtestall", - "menuList", - "TESTCASE", - "PCIe_DEV_LIST", - "PCIe_SPEED_ITEM", -] - -fancontrol_loc = "/usr/local/bin" -fancontrol_config_loc = "/usr/local/bin" - -GLOBALCONFIG = "GLOBALCONFIG" -MONITOR_CONST = "MONITOR_CONST" - -RAGILE_PART_NUMBER = "RJ000001" -RAGILE_LABEL_REVISION = "R01" -RAGILE_ONIE_VERSION = "2018.02" -RAGILE_MAC_SIZE = 3 -RAGILE_MANUF_NAME = "Ragile" -RAGILE_MANUF_COUNTRY = "CHN" -RAGILE_VENDOR_NAME = "Ragile" -RAGILE_DIAG_VERSION = "0.1.0.15" -RAGILE_SERVICE_TAG = "www.ragile.com" - -DEV_LEDS = {} -MEM_SLOTS = [] - -LOCAL_LED_CONTROL = {"CLOSE": {}, "OPEN": {}} - -FIRMWARE_TOOLS = {} -# start-up module -STARTMODULE = {"fancontrol": 1, "avscontrol": 1} - -i2ccheck_params = {"busend": "i2c-66", "retrytime": 6} - -################################################################################################### -##### fan board ID reference -################################################################################################### -FANS_DEF = { - 0x8100: "M6500-FAN-F", - 0x8101: "M6510-FAN-F", - 0x8102: "M6520-FAN-F", - 0x8103: "M6510-FAN-R", -} - -factest_module = { - "sysinfo_showfanmsg": 1, - "sysinfo_showPsumsg": 1, - "sysinfo_showrestfanmsg": 0, - "sysinfo_showrestpsumsg": 0, -} - -#################fan adjustment parameters ############################## -MONITOR_TEMP_MIN = 38 # temperature before speed-adjustment -MONITOR_K = 11 # adjustment algorithm -MONITOR_MAC_IN = 35 # temperature difference between mac and chip(backup) -MONITOR_DEFAULT_SPEED = 0x60 # default speed -MONITOR_MAX_SPEED = 0xFF # maximum speed -MONITOR_MIN_SPEED = 0x33 # minimum speed -MONITOR_MAC_ERROR_SPEED = 0xBB # MAC abnormal speed -MONITOR_FAN_TOTAL_NUM = 4 # 3+1 redundancy design, report to syslog if there is a error -MONITOR_MAC_UP_TEMP = 50 # MAC compared with inlet up -MONITOR_MAC_LOWER_TEMP = -50 # MAC compared with outlet down -MONITOR_MAC_MAX_TEMP = 100 # - -MONITOR_FALL_TEMP = 4 # adjustment reduced temperature -MONITOR_MAC_WARNING_THRESHOLD = 100 # 100 -MONITOR_OUTTEMP_WARNING_THRESHOLD = 85 -MONITOR_BOARDTEMP_WARNING_THRESHOLD = 85 -MONITOR_CPUTEMP_WARNING_THRESHOLD = 85 -MONITOR_INTEMP_WARNING_THRESHOLD = 70 # 70 - -MONITOR_MAC_CRITICAL_THRESHOLD = 105 # 105 -MONITOR_OUTTEMP_CRITICAL_THRESHOLD = 90 # 90 -MONITOR_BOARDTEMP_CRITICAL_THRESHOLD = 90 # 90 -MONITOR_CPUTEMP_CRITICAL_THRESHOLD = 100 # 100 -MONITOR_INTEMP_CRITICAL_THRESHOLD = 80 # 80 -MONITOR_CRITICAL_NUM = 3 # retry times -MONITOR_SHAKE_TIME = 20 # anti-shake times -MONITOR_INTERVAL = 60 - -# 1 get mac temperature from sysfs ,0 get mac temperature from bcmcmd -MONITOR_MAC_SOURCE_SYSFS = (0) -MONITOR_MAC_SOURCE_PATH = None # sysfs path - - -# default MAC AVS parameters -MAC_AVS_PARAM = { - 0x72: 0x0384, - 0x73: 0x037E, - 0x74: 0x0378, - 0x75: 0x0372, - 0x76: 0x036B, - 0x77: 0x0365, - 0x78: 0x035F, - 0x79: 0x0359, - 0x7A: 0x0352, - 0x7B: 0x034C, - 0x7C: 0x0346, - 0x7D: 0x0340, - 0x7E: 0x0339, - 0x7F: 0x0333, - 0x80: 0x032D, - 0x81: 0x0327, - 0x82: 0x0320, - 0x83: 0x031A, - 0x84: 0x0314, - 0x85: 0x030E, - 0x86: 0x0307, - 0x87: 0x0301, - 0x88: 0x02FB, - 0x89: 0x02F5, - 0x8A: 0x02EE, -} - -# default 6520 configuration -MAC_DEFAULT_PARAM = { - "type": 1, # type 1 represents default if out of range / 0 represents no voltage-adjustment if out of range - "default": 0x74, # should be used with type - "loopaddr": 0x00, # AVS loop address - "loop": 0x00, # AVS loop value - "open": 0x00, # diasble write-protection value - "close": 0x40, # enable write-protection value - "bus": 2, # AVSI2C bus address - "devno": 0x60, # AVS address - "addr": 0x21, # AVS voltage-adjustment address - "protectaddr": 0x10, # AVS write-protection address - "sdkreg": "DMU_PCU_OTP_CONFIG_8", # SDK register name - "sdktype": 1, # type 0 represents no shift operation / 1 represents shift operation - "macregloc": 24, # shift operation - "mask": 0xFF, # mask after shift -} - -MONITOR_SYS_LED = [ - {"bus": 2, "devno": 0x33, "addr": 0xB2, "yellow": 0x06, "red": 0x02, "green": 0x04}, - {"bus": 2, "devno": 0x32, "addr": 0x72, "yellow": 0x06, "red": 0x02, "green": 0x04}, -] - -MONITOR_SYS_FAN_LED = [ - {"bus": 2, "devno": 0x33, "addr": 0xB4, "yellow": 0x06, "red": 0x02, "green": 0x04}, -] - -MONITOR_FANS_LED = [ - {"bus": 2, "devno": 0x32, "addr": 0x23, "green": 0x09, "red": 0x0A}, - {"bus": 2, "devno": 0x32, "addr": 0x24, "green": 0x09, "red": 0x0A}, - {"bus": 2, "devno": 0x32, "addr": 0x25, "green": 0x09, "red": 0x0A}, - {"bus": 2, "devno": 0x32, "addr": 0x26, "green": 0x09, "red": 0x0A}, -] - - -MONITOR_SYS_PSU_LED = [ - {"bus": 2, "devno": 0x33, "addr": 0xB3, "yellow": 0x06, "red": 0x02, "green": 0x04}, -] - -MONITOR_FAN_STATUS = [ - {"status": "green", "minOkNum": 4, "maxOkNum": 4}, - {"status": "yellow", "minOkNum": 3, "maxOkNum": 3}, - {"status": "red", "minOkNum": 0, "maxOkNum": 2}, -] - -MONITOR_PSU_STATUS = [ - {"status": "green", "minOkNum": 2, "maxOkNum": 2}, - {"status": "yellow", "minOkNum": 1, "maxOkNum": 1}, - {"status": "red", "minOkNum": 0, "maxOkNum": 0}, -] - -MONITOR_DEV_STATUS = {} -MONITOR_DEV_STATUS_DECODE = {} -DEV_MONITOR_PARAM = {} -SLOT_MONITOR_PARAM = {} - - -fanloc = {"name": "fanset", "location": "0-0032/fan_speed_set"} -#####################MAC-Voltage-Adjustment-Parameters#################################### - - -####================================Adaption-Area================================ -#### RAGILE_COMMON common configuration head -#### “platform” specific configuration head -#### -PCA9548START = 11 -PCA9548BUSEND = 74 - -RAGILE_CARDID = 0x00004040 -RAGILE_PRODUCTNAME = "ragile_ra-b6510" - -FAN_PROTECT = {"bus": 0, "devno": 0x32, "addr": 0x19, "open": 0x00, "close": 0x0F} -rg_eeprom = "2-0057/eeprom" -E2_LOC = {"bus": 2, "devno": 0x57} -E2_PROTECT = {"bus": 2, "devno": 0x33, "addr": 0xB0, "open": 0, "close": 1} -MAC_LED_RESET = {"pcibus": 8, "slot": 0, "fn": 0, "bar": 0, "offset": 64, "reset": 0x98} - -INIT_PARAM = [ - {"loc": "1-0034/sfp_enable", "value": "01"}, - {"loc": "2-0035/sfp_enable2", "value": "ff"}, - {"loc": "2-0033/mac_led", "value": "ff"}, - {"loc": "1-0034/sfp_txdis1", "value": "00"}, - {"loc": "1-0034/sfp_txdis2", "value": "00"}, - {"loc": "1-0034/sfp_txdis3", "value": "00"}, - {"loc": "1-0036/sfp_txdis4", "value": "00"}, - {"loc": "1-0036/sfp_txdis5", "value": "00"}, - {"loc": "1-0036/sfp_txdis6", "value": "00"}, - {"loc": fanloc["location"], "value": "80"}, -] - -INIT_COMMAND = [] - -CPLDVERSIONS = [ - {"loc": "2-0033/cpld_version", "des": "MAC Board CPLDA"}, - {"loc": "2-0035/cpld_version", "des": "MAC Board CPLDB"}, - {"loc": "2-0037/cpld_version", "des": "CPU Board CPLD"}, -] - -## Driver List -## - -DRIVERLISTS = [] -DEVICE = [] -""" -DRIVERLISTS = [ - "i2c_dev", - "i2c_algo_bit", - "i2c_gpio", - "i2c_mux", - "i2c_mux_pca9641", - "i2c_mux_pca954x", # force_deselect_on_exit=1 - "eeprom", - "at24", - "ragile_platform", - "rg_cpld", - "rg_fan", - "rg_psu", - "csu550", - "rg_gpio_xeon", - #IPMIdriver - "ipmi_msghandler", - "ipmi_devintf", - "ipmi_si", -] - -DEVICE = [ - {"name":"pca9641","bus":0 ,"loc":0x10 }, - {"name":"pca9548","bus":2 ,"loc":0x70 }, - {"name":"lm75","bus": 2, "loc":0x48 }, - {"name":"lm75","bus": 2, "loc":0x49 }, - {"name":"lm75","bus": 2, "loc":0x4a }, - {"name":"24c02","bus":2 , "loc":0x57 }, - {"name":"rg_cpld","bus":2 ,"loc":0x33 }, - {"name":"rg_cpld","bus":2 ,"loc":0x35 }, - {"name":"rg_cpld","bus":2 ,"loc":0x37 }, - {"name":"pca9548","bus":1,"loc":0x70 }, - {"name":"pca9548","bus":1,"loc":0x71 }, - {"name":"pca9548","bus":1,"loc":0x72 }, - {"name":"pca9548","bus":1,"loc":0x73 }, - {"name":"pca9548","bus":1,"loc":0x74 }, - {"name":"pca9548","bus":1,"loc":0x75 }, - {"name":"pca9548","bus":1,"loc":0x76 }, - {"name":"pca9548","bus":1,"loc":0x77 }, - {"name":"rg_fan","bus":3,"loc":0x53 }, - {"name":"rg_fan","bus":4,"loc":0x53 }, - {"name":"rg_fan","bus":5,"loc":0x53 }, - #{"name":"rg_fan","bus":6,"loc":0x53 }, #specific fan - {"name":"rg_psu","bus":7 ,"loc":0x50 }, - {"name":"csu550","bus":7 ,"loc":0x58 }, - {"name":"rg_psu","bus":8 ,"loc":0x53 }, - {"name":"csu550","bus":8 ,"loc":0x5b }, -] -""" - -#####################FRU-Info-Adaption################################# -E2TYPE = { - "1": "tlveeprom", - "2": "x86cpueeprom", - "3": "bmceeprom", - "4": "cpueeprom", - "5": "maceeprom", - "6": "sloteeprom", - "7": "fanconnecteeprom", - "8": "M1HFANI-F", - "9": "M1HFANI-R", - "A": "M2HFANI-F", - "B": "M2HFANI-R", - "C": "psu", -} -FRULISTS = [] -################################Manufacturing-Test-Adaption-Area####################################################### -# need to export interface -fanlevel_6510 = { - "level": [51, 150, 255], - "low_speed": [500, 7500, 17000], - "high_speed": [11000, 22500, 28500], -} - -fanlevel_6520 = { - "level": [75, 150, 255], - "low_speed": [750, 4250, 6750], - "high_speed": [4500, 7500, 10000], -} - -fanlevel = fanlevel_6520 - -TEMPIDCHANGE = { - "lm75in": "inlet", - "lm75out": "outlet", - "lm75hot": "hot-point", - "inlet": "lm75in", - "outlet": "lm75out", - "hot-point": "lm75hot", -} - -# Manufacturing-Test module -FACTESTMODULE = {} - -##################################Manufacturing-Test-Menu -item1 = {"name": "Single Test", "deal": "test_signal", "childid": 1} -test_sys_reload_item = {"name": "reset-system", "deal": "test_sys_reload"} - -test_sys_item = {"name": "Product information test", "deal": "test_sysinfo"} -test_temp_item = {"name": "temperature test", "deal": "test_tempinfo"} -test_mem_item = {"name": "Memory test", "deal": "test_cpumemoryinfo"} -test_hd_item = {"name": "Hard disk test", "deal": "test_hard"} -test_rtc_item = {"name": "RTC test ", "deal": "test_rtc"} -test_i2c_item = {"name": "I2c test ", "deal": "test_i2c"} -test_cpld_item = {"name": "CPLD test", "deal": "test_cpld"} -test_portframe_item = { - "name": "Port transmit-receive frame test", - "deal": "test_portframe", -} -test_sysled_item = {"name": "System led test", "deal": "test_led"} -test_fan_item = {"name": "Fan status test", "deal": "test_fan"} -test_power_item = {"name": "PSU status test", "deal": "test_power"} -test_usb_item = {"name": "USB test", "deal": "test_usb"} -test_prbs_item = {"name": "PRBS test", "deal": "test_prbs"} -test_portbroadcast_item = {"name": "Port broadcast", "deal": "test_portbroadcast"} - -test_debug_level = {"name": "Change debug level", "deal": "test_setdebug"} -test_log_level = {"name": "Log output level", "deal": "test_loginfolevel"} -test_setmac = {"name": "setmac", "deal": "test_setmac"} -test_setrtc = {"name": "Set RTC", "deal": "test_set_rtc"} - -log_level_critical = {"name": "CRITICAL", "deal": "test_log_critical"} -log_level_debug = {"name": "DEBUG", "deal": "test_log_debug"} -log_level_error = {"name": "ERROR", "deal": "test_log_error"} -log_level_info = {"name": "INFO", "deal": "test_log_info"} -log_level_notset = {"name": "NOTSET", "deal": "test_log_notset"} -log_level_warning = {"name": "WARNING", "deal": "test_log_warning"} - - -test_e2_setmac_item = {"name": "E2SETMAC", "deal": "test_e2_setmac"} -test_bmc_setmac_item = {"name": "BMCSETMAC", "deal": "test_bmc_setmac"} -test_fan_setmac_item = {"name": "fan SETMAC", "deal": "test_fan_setmac"} - -alltest = [ - test_sys_item, - test_temp_item, - test_mem_item, - test_hd_item, - test_rtc_item, - test_i2c_item, - test_cpld_item, - test_portframe_item, - test_sysled_item, - test_fan_item, - test_power_item, - test_usb_item, - test_prbs_item, - test_portbroadcast_item, -] - -looptest = [ - test_sys_item, - test_temp_item, - test_mem_item, - test_hd_item, - test_rtc_item, - test_i2c_item, - test_cpld_item, - test_portframe_item, - test_fan_item, - test_power_item, - test_usb_item, - test_prbs_item, - test_portbroadcast_item, -] - -diagtestall = [] - -menuList = [ - { - "menuid": 0, - "value": [ - {"name": "Single test", "deal": "test_signal", "childid": 1}, - {"name": "All test", "deal": "test_all"}, - {"name": "Loop test", "deal": "test_loop"}, - # {"name":"Check loop-test result", "deal" :"test_loop_read"}, - # {"name":"Delete loop-test result", "deal" :"test_loop_delete"}, - # {"name":"Load configuration", "deal" :"test_config"}, - test_sys_reload_item, - {"name": "System Configuration", "deal": "test_sysconfig", "childid": 2}, - ], - }, - { - "menuid": 1, - "parentid": 0, - "value": [ - test_sys_item, - test_temp_item, - test_mem_item, - test_hd_item, - test_rtc_item, - test_i2c_item, - test_cpld_item, - test_portframe_item, - test_sysled_item, - test_fan_item, - test_power_item, - test_usb_item, - test_prbs_item, - test_portbroadcast_item, - ], - }, - { - "menuid": 2, - "parentid": 0, - "value": [test_debug_level, test_log_level, test_setmac, test_setrtc,], - }, - { - "menuid": 3, - "parentid": 2, - "value": [ - log_level_critical, - log_level_debug, - log_level_error, - log_level_info, - log_level_notset, - log_level_warning, - ], - }, - { - "menuid": 4, - "parentid": 2, - "value": [test_e2_setmac_item, test_bmc_setmac_item, test_fan_setmac_item,], - }, -] - - -TESTCASE = { - "CPLD": [ - { - "name": "CONNECT BOARD CPLD-A", - "cases": [ - {"name": "cpld32", "cmd": "grtd_test.py cpld_check 0 0x32 0xAA"}, - {"name": "cpld37", "cmd": "grtd_test.py cpld_check 2 0x37 0xAC"}, - ], - }, - { - "name": "MAC BOARD CPLD-A", - "cases": [ - {"name": "cpld33", "cmd": "grtd_test.py cpld_check 2 0x33 0xAB"}, - {"name": "cpld34", "cmd": "grtd_test.py cpld_check 1 0x34 0xAA"}, - ], - }, - { - "name": "MAC BOARD CPLD-B", - "cases": [ - {"name": "cpld36", "cmd": "grtd_test.py cpld_check 1 0x36 0xAA"}, - {"name": "cpld35", "cmd": "grtd_test.py cpld_check 2 0x35 0xAB"}, - ], - }, - ], - "TEMPERATURE": [ - { - "name": "-->temperature test", - "cases": [ - { - "name": "inlet", - "cmd": "grtd_test.py temp 2-0048/hwmon/hwmon1/temp1_input", - }, - { - "name": "outlet", - "cmd": "grtd_test.py temp 2-0049/hwmon/hwmon2/temp1_input", - }, - { - "name": "hot-point", - "cmd": "grtd_test.py temp 2-004a/hwmon/hwmon3/temp1_input", - }, - ], - } - ], - "MEMTORY": { - "cases": [ - {"name": "->memory test 1M", "cmd": "memtester 1M 1"}, - {"name": "->memory test 2M", "cmd": "memtester 2M 1"}, - {"name": "->memory test 8M", "cmd": "memtester 8M 1"}, - # {"name":"->memory test 16M","cmd":"memtester 16M 1"}, - # {"name":"->memory test 256M","cmd":"memtester 256M 1"}, - ] - }, - "SMARTCTLCMDS": { - "cases": [ - {"name": "->Check Hard Disk Info", "cmd": "smartctl -i /dev/sda"}, - {"name": "->Check Hard Disk Monitor Status", "cmd": "smartctl -H /dev/sda"}, - ] - }, - "LED": [ - { - "name": "Light Port Led test", - "cases": [ - { - "name": "-> Red Led Off", - "cmd": "grtd_test.py led loc 1-0034/sfp_led1_red,1-0034/sfp_led2_red,1-0034/sfp_led3_red,1-0034/sfp_led8_red,1-0036/sfp_led4_red,1-0036/sfp_led5_red,1-0036/sfp_led6_red,1-0036/sfp_led7_red 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00", - }, - { - "name": "-> Red Led On", - "cmd": "grtd_test.py led loc 1-0034/sfp_led1_red,1-0034/sfp_led2_red,1-0034/sfp_led3_red,1-0034/sfp_led8_red,1-0036/sfp_led4_red,1-0036/sfp_led5_red,1-0036/sfp_led6_red,1-0036/sfp_led7_red 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff", - }, - { - "name": "-> Recovery Red Led Off", - "cmd": "grtd_test.py led loc 1-0034/sfp_led1_red,1-0034/sfp_led2_red,1-0034/sfp_led3_red,1-0034/sfp_led8_red,1-0036/sfp_led4_red,1-0036/sfp_led5_red,1-0036/sfp_led6_red,1-0036/sfp_led7_red 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00", - }, - { - "name": "-> Yellow Led Off", - "cmd": "grtd_test.py led loc 1-0034/sfp_led1_yellow,1-0034/sfp_led2_yellow,1-0034/sfp_led3_yellow,1-0034/sfp_led8_yellow,1-0036/sfp_led4_yellow,1-0036/sfp_led5_yellow,1-0036/sfp_led6_yellow,1-0036/sfp_led7_yellow 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00", - }, - { - "name": "-> Yellow Led On", - "cmd": "grtd_test.py led loc 1-0034/sfp_led1_yellow,1-0034/sfp_led2_yellow,1-0034/sfp_led3_yellow,1-0034/sfp_led8_yellow,1-0036/sfp_led4_yellow,1-0036/sfp_led5_yellow,1-0036/sfp_led6_yellow,1-0036/sfp_led7_yellow 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff", - }, - { - "name": "-> Recovery Yellow Led Off", - "cmd": "grtd_test.py led loc 1-0034/sfp_led1_yellow,1-0034/sfp_led2_yellow,1-0034/sfp_led3_yellow,1-0034/sfp_led8_yellow,1-0036/sfp_led4_yellow,1-0036/sfp_led5_yellow,1-0036/sfp_led6_yellow,1-0036/sfp_led7_yellow 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00", - }, - ], - }, - { - "name": "fan 1 Led", - "cases": [ - { - "name": "-> LedOff", - "cmd": "grtd_test.py led loc 0-0032/fan0_led 0x0b", - }, - { - "name": "-> Red Led ", - "cmd": "grtd_test.py led loc 0-0032/fan0_led 0x0a", - }, - { - "name": "-> Green Led ", - "cmd": "grtd_test.py led loc 0-0032/fan0_led 0x09", - }, - { - "name": "-> Yellow Led ", - "cmd": "grtd_test.py led loc 0-0032/fan0_led 0x08", - }, - { - "name": "-> Red Led Flashing", - "cmd": "grtd_test.py led loc 0-0032/fan0_led 0x0e", - }, - { - "name": "-> Green Led Flashing", - "cmd": "grtd_test.py led loc 0-0032/fan0_led 0x0d", - }, - { - "name": "-> Yellow Led Flashing", - "cmd": "grtd_test.py led loc 0-0032/fan0_led 0x0c", - }, - { - "name": "-> Recovery Green Led ", - "cmd": "grtd_test.py led loc 0-0032/fan0_led 0x09", - }, - ], - }, - { - "name": "fan 2 Led", - "cases": [ - { - "name": "-> LedOff", - "cmd": "grtd_test.py led loc 0-0032/fan1_led 0x0b", - }, - { - "name": "-> Red Led ", - "cmd": "grtd_test.py led loc 0-0032/fan1_led 0x0a", - }, - { - "name": "-> Green Led ", - "cmd": "grtd_test.py led loc 0-0032/fan1_led 0x09", - }, - { - "name": "-> Yellow Led ", - "cmd": "grtd_test.py led loc 0-0032/fan1_led 0x08", - }, - { - "name": "-> Red Led Flashing", - "cmd": "grtd_test.py led loc 0-0032/fan1_led 0x0e", - }, - { - "name": "-> Green Led Flashing", - "cmd": "grtd_test.py led loc 0-0032/fan1_led 0x0d", - }, - { - "name": "-> Yellow Led Flashing", - "cmd": "grtd_test.py led loc 0-0032/fan1_led 0x0c", - }, - { - "name": "-> Recovery Green Led ", - "cmd": "grtd_test.py led loc 0-0032/fan1_led 0x09", - }, - ], - }, - { - "name": "fan 3 Led", - "cases": [ - { - "name": "-> LedOff", - "cmd": "grtd_test.py led loc 0-0032/fan2_led 0x0b", - }, - { - "name": "-> Red Led ", - "cmd": "grtd_test.py led loc 0-0032/fan2_led 0x0a", - }, - { - "name": "-> Green Led ", - "cmd": "grtd_test.py led loc 0-0032/fan2_led 0x09", - }, - { - "name": "-> Yellow Led ", - "cmd": "grtd_test.py led loc 0-0032/fan2_led 0x08", - }, - { - "name": "-> Red Led Flashing", - "cmd": "grtd_test.py led loc 0-0032/fan2_led 0x0e", - }, - { - "name": "-> Green Led Flashing", - "cmd": "grtd_test.py led loc 0-0032/fan2_led 0x0d", - }, - { - "name": "-> Yellow Led Flashing", - "cmd": "grtd_test.py led loc 0-0032/fan2_led 0x0c", - }, - { - "name": "-> Recovery Green Led ", - "cmd": "grtd_test.py led loc 0-0032/fan2_led 0x09", - }, - ], - }, - { - "name": "Front panel CPU Led", - "cases": [ - { - "name": "-> LedOff", - "cmd": "grtd_test.py led loc 2-0035/broad_front_cpu 0x00", - }, - { - "name": "-> Green Led not Flashing", - "cmd": "grtd_test.py led loc 2-0035/broad_front_cpu 0x01", - }, - { - "name": "-> Red Led not Flashing", - "cmd": "grtd_test.py led loc 2-0035/broad_front_cpu 0x02", - }, - { - "name": "-> Yellow Led not Flashing", - "cmd": "grtd_test.py led loc 2-0035/broad_front_cpu 0x03", - }, - { - "name": "-> Green Led 1/4sFlashing ", - "cmd": "grtd_test.py led loc 2-0035/broad_front_cpu 0x11", - }, - { - "name": "-> Green Led 1/2sFlashing ", - "cmd": "grtd_test.py led loc 2-0035/broad_front_cpu 0x21", - }, - { - "name": "-> Green Led 1sFlashing ", - "cmd": "grtd_test.py led loc 2-0035/broad_front_cpu 0x41", - }, - { - "name": "-> Green Led 2sFlashing ", - "cmd": "grtd_test.py led loc 2-0035/broad_front_cpu 0x81", - }, - { - "name": "-> Red Led 1/4sFlashing ", - "cmd": "grtd_test.py led loc 2-0035/broad_front_cpu 0x12", - }, - { - "name": "-> Red Led 1/2sFlashing ", - "cmd": "grtd_test.py led loc 2-0035/broad_front_cpu 0x22", - }, - { - "name": "-> Red Led 1sFlashing ", - "cmd": "grtd_test.py led loc 2-0035/broad_front_cpu 0x42", - }, - { - "name": "-> Red Led 2sFlashing ", - "cmd": "grtd_test.py led loc 2-0035/broad_front_cpu 0x82", - }, - { - "name": "-> Yellow Led 1/4sFlashing ", - "cmd": "grtd_test.py led loc 2-0035/broad_front_cpu 0x13", - }, - { - "name": "-> Yellow Led 1/2sFlashing ", - "cmd": "grtd_test.py led loc 2-0035/broad_front_cpu 0x23", - }, - { - "name": "-> Yellow Led 1sFlashing ", - "cmd": "grtd_test.py led loc 2-0035/broad_front_cpu 0x43", - }, - { - "name": "-> Yellow Led 2sFlashing ", - "cmd": "grtd_test.py led loc 2-0035/broad_front_cpu 0x83", - }, - { - "name": "-> Recovery Green Led ", - "cmd": "grtd_test.py led loc 2-0035/broad_front_cpu 0x01", - }, - ], - }, - { - "name": "Front panel BMC Led", - "cases": [ - { - "name": "-> LedOff", - "cmd": "grtd_test.py led loc 2-0035/broad_front_bmc 0x00", - }, - { - "name": "-> Red Led Flashing", - "cmd": "grtd_test.py led loc 2-0035/broad_front_bmc 0x01", - }, - { - "name": "-> Red Led not Flashing", - "cmd": "grtd_test.py led loc 2-0035/broad_front_bmc 0x02", - }, - { - "name": "-> Green Led Flashing", - "cmd": "grtd_test.py led loc 2-0035/broad_front_bmc 0x03", - }, - { - "name": "-> Green Led not Flashing", - "cmd": "grtd_test.py led loc 2-0035/broad_front_bmc 0x04", - }, - { - "name": "-> Yellow Led Flashing", - "cmd": "grtd_test.py led loc 2-0035/broad_front_bmc 0x05", - }, - { - "name": "-> Yellow Led not Flashing", - "cmd": "grtd_test.py led loc 2-0035/broad_front_bmc 0x06", - }, - { - "name": "-> Recovery Green Led ", - "cmd": "grtd_test.py led loc 2-0035/broad_front_bmc 0x04", - }, - ], - }, - { - "name": "Front panel location Led", - "cases": [ - { - "name": "-> LedOff", - "cmd": "grtd_test.py led loc 2-0035/broad_front_lct 0xff", - }, - { - "name": "-> LedOn", - "cmd": "grtd_test.py led loc 2-0035/broad_front_lct 0xfe", - }, - { - "name": "->Recovery LedOff", - "cmd": "grtd_test.py led loc 2-0035/broad_front_lct 0xff", - }, - ], - }, - { - "name": "Front panel pwr Led", - "cases": [ - { - "name": "-> LedOff", - "cmd": "grtd_test.py led loc 2-0035/broad_front_pwr 0x00", - }, - { - "name": "-> Red Led Flashing", - "cmd": "grtd_test.py led loc 2-0035/broad_front_pwr 0x01", - }, - { - "name": "-> Red Led not Flashing", - "cmd": "grtd_test.py led loc 2-0035/broad_front_pwr 0x02", - }, - { - "name": "-> Green Led Flashing", - "cmd": "grtd_test.py led loc 2-0035/broad_front_pwr 0x03", - }, - { - "name": "-> Green Led not Flashing", - "cmd": "grtd_test.py led loc 2-0035/broad_front_pwr 0x04", - }, - { - "name": "-> Yellow Led Flashing", - "cmd": "grtd_test.py led loc 2-0035/broad_front_pwr 0x05", - }, - { - "name": "-> Yellow Led not Flashing", - "cmd": "grtd_test.py led loc 2-0035/broad_front_pwr 0x06", - }, - { - "name": "-> Recovery Green Led ", - "cmd": "grtd_test.py led loc 2-0035/broad_front_pwr 0x04", - }, - ], - }, - { - "name": "Front panel fan Led", - "cases": [ - { - "name": "-> LedOff", - "cmd": "grtd_test.py led loc 2-0035/broad_front_fan 0x00", - }, - { - "name": "-> Red Led Flashing", - "cmd": "grtd_test.py led loc 2-0035/broad_front_fan 0x01", - }, - { - "name": "-> Red Led not Flashing", - "cmd": "grtd_test.py led loc 2-0035/broad_front_fan 0x02", - }, - { - "name": "-> Green Led Flashing", - "cmd": "grtd_test.py led loc 2-0035/broad_front_fan 0x03", - }, - { - "name": "-> Green Led not Flashing", - "cmd": "grtd_test.py led loc 2-0035/broad_front_fan 0x04", - }, - { - "name": "-> Yellow Led Flashing", - "cmd": "grtd_test.py led loc 2-0035/broad_front_fan 0x05", - }, - { - "name": "-> Yellow Led not Flashing", - "cmd": "grtd_test.py led loc 2-0035/broad_front_fan 0x06", - }, - { - "name": "-> Recovery Green Led ", - "cmd": "grtd_test.py led loc 2-0035/broad_front_fan 0x04", - }, - ], - }, - ], - "I2C": [ - ####type 1 represents value obtained compated with value - ####type 2 represents return True or False - { - "name": "I2C device test", - "cases": [ - { - "name": " PCA9641 test", - "cmd": "grtd_test.py dev_rd 0 10 0", - "deal_type": 2, - }, - { - "name": " cpld32 test", - "cmd": "grtd_test.py dev_rd 0 32 0", - "deal_type": 2, - }, - { - "name": " cpld33 test", - "cmd": "grtd_test.py dev_rd 0 32 0", - "deal_type": 2, - }, - { - "name": " cpld34 test", - "cmd": "grtd_test.py dev_rd 0 32 0", - "deal_type": 2, - }, - { - "name": " cpld35 test", - "cmd": "grtd_test.py dev_rd 0 32 0", - "deal_type": 2, - }, - { - "name": " cpld36 test", - "cmd": "grtd_test.py dev_rd 0 32 0", - "deal_type": 2, - }, - { - "name": " cpld37 test", - "cmd": "grtd_test.py dev_rd 0 32 0", - "deal_type": 2, - }, - { - "name": " inlet LM75", - "cmd": "grtd_test.py dev_rd 0 32 0", - "deal_type": 2, - }, - { - "name": " outlet LM75", - "cmd": "grtd_test.py dev_rd 0 32 0", - "deal_type": 2, - }, - { - "name": " hot-point LM75", - "cmd": "grtd_test.py dev_rd 0 32 0", - "deal_type": 2, - }, - { - "name": " EEPROM", - "cmd": "grtd_test.py dev_rd 0 32 0", - "deal_type": 2, - }, - { - "name": " Port 1", - "cmd": "grtd_test.py dev_rd 11 0050 0", - "deal_type": 2, - }, - { - "name": " Port 2", - "cmd": "grtd_test.py dev_rd 12 0050 0", - "deal_type": 2, - }, - { - "name": " Port 3", - "cmd": "grtd_test.py dev_rd 13 0050 0", - "deal_type": 2, - }, - { - "name": " Port 4", - "cmd": "grtd_test.py dev_rd 14 0050 0", - "deal_type": 2, - }, - { - "name": " Port 5", - "cmd": "grtd_test.py dev_rd 15 0050 0", - "deal_type": 2, - }, - { - "name": " Port 6", - "cmd": "grtd_test.py dev_rd 16 0050 0", - "deal_type": 2, - }, - { - "name": " Port 7", - "cmd": "grtd_test.py dev_rd 17 0050 0", - "deal_type": 2, - }, - { - "name": " Port 8", - "cmd": "grtd_test.py dev_rd 18 0050 0", - "deal_type": 2, - }, - { - "name": " Port 9", - "cmd": "grtd_test.py dev_rd 19 0050 0", - "deal_type": 2, - }, - { - "name": " Port 10", - "cmd": "grtd_test.py dev_rd 20 0050 0", - "deal_type": 2, - }, - { - "name": " Port 11", - "cmd": "grtd_test.py dev_rd 21 0050 0", - "deal_type": 2, - }, - { - "name": " Port 12", - "cmd": "grtd_test.py dev_rd 22 0050 0", - "deal_type": 2, - }, - { - "name": " Port 13", - "cmd": "grtd_test.py dev_rd 23 0050 0", - "deal_type": 2, - }, - { - "name": " Port 14", - "cmd": "grtd_test.py dev_rd 24 0050 0", - "deal_type": 2, - }, - { - "name": " Port 15", - "cmd": "grtd_test.py dev_rd 25 0050 0", - "deal_type": 2, - }, - { - "name": " Port 16", - "cmd": "grtd_test.py dev_rd 26 0050 0", - "deal_type": 2, - }, - { - "name": " Port 17", - "cmd": "grtd_test.py dev_rd 27 0050 0", - "deal_type": 2, - }, - { - "name": " Port 18", - "cmd": "grtd_test.py dev_rd 28 0050 0", - "deal_type": 2, - }, - { - "name": " Port 19", - "cmd": "grtd_test.py dev_rd 29 0050 0", - "deal_type": 2, - }, - { - "name": " Port 20", - "cmd": "grtd_test.py dev_rd 30 0050 0", - "deal_type": 2, - }, - { - "name": " Port 21", - "cmd": "grtd_test.py dev_rd 31 0050 0", - "deal_type": 2, - }, - { - "name": " Port 22", - "cmd": "grtd_test.py dev_rd 32 0050 0", - "deal_type": 2, - }, - { - "name": " Port 23", - "cmd": "grtd_test.py dev_rd 33 0050 0", - "deal_type": 2, - }, - { - "name": " Port 24", - "cmd": "grtd_test.py dev_rd 34 0050 0", - "deal_type": 2, - }, - { - "name": " Port 25", - "cmd": "grtd_test.py dev_rd 35 0050 0", - "deal_type": 2, - }, - { - "name": " Port 26", - "cmd": "grtd_test.py dev_rd 36 0050 0", - "deal_type": 2, - }, - { - "name": " Port 27", - "cmd": "grtd_test.py dev_rd 37 0050 0", - "deal_type": 2, - }, - { - "name": " Port 28", - "cmd": "grtd_test.py dev_rd 38 0050 0", - "deal_type": 2, - }, - { - "name": " Port 29", - "cmd": "grtd_test.py dev_rd 39 0050 0", - "deal_type": 2, - }, - { - "name": " Port 30", - "cmd": "grtd_test.py dev_rd 40 0050 0", - "deal_type": 2, - }, - { - "name": " Port 31", - "cmd": "grtd_test.py dev_rd 41 0050 0", - "deal_type": 2, - }, - { - "name": " Port 32", - "cmd": "grtd_test.py dev_rd 42 0050 0", - "deal_type": 2, - }, - { - "name": " Port 33", - "cmd": "grtd_test.py dev_rd 43 0050 0", - "deal_type": 2, - }, - { - "name": " Port 34", - "cmd": "grtd_test.py dev_rd 44 0050 0", - "deal_type": 2, - }, - { - "name": " Port 35", - "cmd": "grtd_test.py dev_rd 45 0050 0", - "deal_type": 2, - }, - { - "name": " Port 36", - "cmd": "grtd_test.py dev_rd 46 0050 0", - "deal_type": 2, - }, - { - "name": " Port 37", - "cmd": "grtd_test.py dev_rd 47 0050 0", - "deal_type": 2, - }, - { - "name": " Port 38", - "cmd": "grtd_test.py dev_rd 48 0050 0", - "deal_type": 2, - }, - { - "name": " Port 39", - "cmd": "grtd_test.py dev_rd 49 0050 0", - "deal_type": 2, - }, - { - "name": " Port 40", - "cmd": "grtd_test.py dev_rd 50 0050 0", - "deal_type": 2, - }, - { - "name": " Port 41", - "cmd": "grtd_test.py dev_rd 51 0050 0", - "deal_type": 2, - }, - { - "name": " Port 42", - "cmd": "grtd_test.py dev_rd 52 0050 0", - "deal_type": 2, - }, - { - "name": " Port 43", - "cmd": "grtd_test.py dev_rd 53 0050 0", - "deal_type": 2, - }, - { - "name": " Port 44", - "cmd": "grtd_test.py dev_rd 54 0050 0", - "deal_type": 2, - }, - { - "name": " Port 45", - "cmd": "grtd_test.py dev_rd 55 0050 0", - "deal_type": 2, - }, - { - "name": " Port 46", - "cmd": "grtd_test.py dev_rd 56 0050 0", - "deal_type": 2, - }, - { - "name": " Port 47", - "cmd": "grtd_test.py dev_rd 57 0050 0", - "deal_type": 2, - }, - { - "name": " Port 48", - "cmd": "grtd_test.py dev_rd 58 0050 0", - "deal_type": 2, - }, - { - "name": " Port 49", - "cmd": "grtd_test.py dev_rd 59 0050 0", - "deal_type": 2, - }, - { - "name": " Port 50", - "cmd": "grtd_test.py dev_rd 60 0050 0", - "deal_type": 2, - }, - { - "name": " Port 51", - "cmd": "grtd_test.py dev_rd 61 0050 0", - "deal_type": 2, - }, - { - "name": " Port 52", - "cmd": "grtd_test.py dev_rd 62 0050 0", - "deal_type": 2, - }, - { - "name": " Port 53", - "cmd": "grtd_test.py dev_rd 63 0050 0", - "deal_type": 2, - }, - { - "name": " Port 54", - "cmd": "grtd_test.py dev_rd 64 0050 0", - "deal_type": 2, - }, - { - "name": " Port 55", - "cmd": "grtd_test.py dev_rd 65 0050 0", - "deal_type": 2, - }, - { - "name": " Port 56", - "cmd": "grtd_test.py dev_rd 66 0050 0", - "deal_type": 2, - }, - { - "name": " Port 57", - "cmd": "grtd_test.py dev_rd 67 0050 0", - "deal_type": 2, - }, - { - "name": " Port 58", - "cmd": "grtd_test.py dev_rd 68 0050 0", - "deal_type": 2, - }, - { - "name": " Port 59", - "cmd": "grtd_test.py dev_rd 69 0050 0", - "deal_type": 2, - }, - { - "name": " Port 60", - "cmd": "grtd_test.py dev_rd 70 0050 0", - "deal_type": 2, - }, - { - "name": " Port 61", - "cmd": "grtd_test.py dev_rd 71 0050 0", - "deal_type": 2, - }, - { - "name": " Port 62", - "cmd": "grtd_test.py dev_rd 72 0050 0", - "deal_type": 2, - }, - { - "name": " Port 63", - "cmd": "grtd_test.py dev_rd 73 0050 0", - "deal_type": 2, - }, - { - "name": " Port 64", - "cmd": "grtd_test.py dev_rd 74 0050 0", - "deal_type": 2, - }, - ], - }, - ], -} - -PCIe_DEV_LIST = [] -PCIe_SPEED_ITEM = [] - -################################Manufacturing-Test-Adaption-Area####################################################### diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/script/ragileconfig.py b/platform/broadcom/sonic-platform-modules-ragile/common/script/ragileconfig.py deleted file mode 100755 index 4a3a321d6e42..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/common/script/ragileconfig.py +++ /dev/null @@ -1,225 +0,0 @@ -#!/usr/bin/python3 -# -*- coding: UTF-8 -*- -# ------------------------------------------------------------------------------- -# Name: ragileconfig.py -# Purpose: block the difference between various product/onie version for other module -# -# Author: rd -# -# Created: 02/07/2018 -# Copyright: (c) rd 2018 -# ------------------------------------------------------------------------------- -import sys -import os -from rgutil.baseutil import get_machine_info -from rgutil.baseutil import get_platform_info - -__all__ = [ - "getdeviceplatform", - "get_rjconfig_info", - "MONITOR_CONST", - "MAILBOX_DIR", - "DEVICE", - "GLOBALCONFIG", - "GLOBALINITPARAM", - "GLOBALINITCOMMAND", - "MAC_LED_RESET", - "STARTMODULE", - "fanloc", - "RAGILE_CARDID", - "RAGILE_PRODUCTNAME", - "RAGILE_PART_NUMBER", - "RAGILE_LABEL_REVISION", - "RAGILE_MAC_SIZE", - "RAGILE_MANUF_NAME", - "RAGILE_MANUF_COUNTRY", - "RAGILE_VENDOR_NAME", - "RAGILE_DIAG_VERSION", - "RAGILE_SERVICE_TAG", - "E2_PROTECT", - "E2_LOC", - "FAN_PROTECT", - "FANS_DEF", - "MONITOR_FANS_LED", - "MONITOR_SYS_FAN_LED", - "MONITOR_SYS_PSU_LED", - "MONITOR_FAN_STATUS", - "MONITOR_PSU_STATUS", - "MONITOR_DEV_STATUS", - "MONITOR_DEV_STATUS_DECODE", - "DEV_LEDS", - "MAC_AVS_PARAM", - "MAC_DEFAULT_PARAM", - "FRULISTS", - "rg_eeprom", - "i2ccheck_params", - "FANCTROLDEBUG", - "DEVMONITORDEBUG", -] - - -def getdeviceplatform(): - x = get_platform_info(get_machine_info()) - if x != None: - filepath = "/usr/share/sonic/device/" + x - return filepath - - -platform = get_platform_info(get_machine_info()) -platformpath = getdeviceplatform() -MAILBOX_DIR = "/sys/bus/i2c/devices/" -grtd_productfile = (platform + "_config").replace("-", "_") -common_productfile = "ragilecommon" -configfile_pre = "/usr/local/bin/" - -sys.path.append(platformpath) -sys.path.append(configfile_pre) - - -def get_rjconfig_info(attr_key): - rjconf_filename = platformpath + "/plugins" + "/rj.conf" - if not os.path.isfile(rjconf_filename): - return None - with open(rjconf_filename) as rjconf_file: - for line in rjconf_file: - tokens = line.split("=") - if len(tokens) < 2: - continue - if tokens[0] == attr_key: - return tokens[1].strip() - return None - - -#####BMC-Password### -OPENBMC_PASSWORD = get_rjconfig_info("OPENBMC_PASSWORD") -OPENBMC_PASSWORD = OPENBMC_PASSWORD if (OPENBMC_PASSWORD != None) else "0penBmc" - -############################################################################################ -## if there is no specific file, use common file -module_product = None -if os.path.exists(configfile_pre + grtd_productfile + ".py"): - module_product = __import__(grtd_productfile, globals(), locals(), [], 0) -elif os.path.exists(configfile_pre + common_productfile + ".py"): - module_product = __import__(common_productfile, globals(), locals(), [], 0) -else: - print("No Configuration existed, quit") - exit(-1) -############################################################################################ - -DEVICE = module_product.DEVICE - -##########Driver loading needs parameters -# get different product configuration -RAGILE_GLOBALCONFIG = { - "DRIVERLISTS": module_product.DRIVERLISTS, - "QSFP": { - "startbus": module_product.PCA9548START, - "endbus": module_product.PCA9548BUSEND, - }, - "DEVS": DEVICE, -} -GLOBALCONFIG = RAGILE_GLOBALCONFIG -GLOBALINITPARAM = module_product.INIT_PARAM -GLOBALINITCOMMAND = module_product.INIT_COMMAND - -fancontrol_loc = module_product.fancontrol_loc -fancontrol_config_loc = module_product.fancontrol_config_loc -MAC_LED_RESET = module_product.MAC_LED_RESET -###########Stat-up module parameters -STARTMODULE = module_product.STARTMODULE -FIRMWARE_TOOLS = module_product.FIRMWARE_TOOLS - - -##########Manufacturing-Test need parameters -FACTESTMODULE = module_product.FACTESTMODULE -TESTCASE = module_product.TESTCASE -menuList = module_product.menuList -alltest = module_product.alltest -diagtestall = module_product.diagtestall -looptest = module_product.looptest -fanloc = module_product.fanloc -fanlevel = module_product.fanlevel # fan adjustment level -TEMPIDCHANGE = module_product.TEMPIDCHANGE -CPLDVERSIONS = module_product.CPLDVERSIONS -RAGILE_CARDID = module_product.RAGILE_CARDID -RAGILE_PRODUCTNAME = module_product.RAGILE_PRODUCTNAME - -RAGILE_PART_NUMBER = module_product.RAGILE_PART_NUMBER -RAGILE_LABEL_REVISION = module_product.RAGILE_LABEL_REVISION -RAGILE_ONIE_VERSION = module_product.RAGILE_ONIE_VERSION -RAGILE_MAC_SIZE = module_product.RAGILE_MAC_SIZE -RAGILE_MANUF_NAME = module_product.RAGILE_MANUF_NAME -RAGILE_MANUF_COUNTRY = module_product.RAGILE_MANUF_COUNTRY -RAGILE_VENDOR_NAME = module_product.RAGILE_VENDOR_NAME -RAGILE_DIAG_VERSION = module_product.RAGILE_DIAG_VERSION -RAGILE_SERVICE_TAG = module_product.RAGILE_SERVICE_TAG - -E2_PROTECT = module_product.E2_PROTECT -E2_LOC = module_product.E2_LOC -FAN_PROTECT = module_product.FAN_PROTECT - -FANS_DEF = module_product.FANS_DEF -MONITOR_SYS_LED = module_product.MONITOR_SYS_LED -MONITOR_FANS_LED = module_product.MONITOR_FANS_LED -MONITOR_SYS_FAN_LED = module_product.MONITOR_SYS_FAN_LED -MONITOR_SYS_PSU_LED = module_product.MONITOR_SYS_PSU_LED -MONITOR_FAN_STATUS = module_product.MONITOR_FAN_STATUS -MONITOR_PSU_STATUS = module_product.MONITOR_PSU_STATUS -MONITOR_DEV_STATUS = module_product.MONITOR_DEV_STATUS -MONITOR_DEV_STATUS_DECODE = module_product.MONITOR_DEV_STATUS_DECODE -DEV_MONITOR_PARAM = module_product.DEV_MONITOR_PARAM -SLOT_MONITOR_PARAM = module_product.SLOT_MONITOR_PARAM - - -DEV_LEDS = module_product.DEV_LEDS -MEM_SLOTS = module_product.MEM_SLOTS - -MAC_AVS_PARAM = module_product.MAC_AVS_PARAM -MAC_DEFAULT_PARAM = module_product.MAC_DEFAULT_PARAM -E2TYPE = module_product.E2TYPE -FRULISTS = module_product.FRULISTS -rg_eeprom = "%d-%04x/eeprom" % (E2_LOC["bus"], E2_LOC["devno"]) -factest_module = module_product.factest_module - -LOCAL_LED_CONTROL = module_product.LOCAL_LED_CONTROL - -PCIe_DEV_LIST = module_product.PCIe_DEV_LIST -PCIe_SPEED_ITEM = module_product.PCIe_SPEED_ITEM -i2ccheck_params = module_product.i2ccheck_params - - -class MONITOR_CONST: - TEMP_MIN = module_product.MONITOR_TEMP_MIN - K = module_product.MONITOR_K - MAC_IN = module_product.MONITOR_MAC_IN - DEFAULT_SPEED = module_product.MONITOR_DEFAULT_SPEED - MAX_SPEED = module_product.MONITOR_MAX_SPEED - MIN_SPEED = module_product.MONITOR_MIN_SPEED - MAC_ERROR_SPEED = module_product.MONITOR_MAC_ERROR_SPEED - FAN_TOTAL_NUM = module_product.MONITOR_FAN_TOTAL_NUM - MAC_UP_TEMP = module_product.MONITOR_MAC_UP_TEMP - MAC_LOWER_TEMP = module_product.MONITOR_MAC_LOWER_TEMP - MAC_MAX_TEMP = module_product.MONITOR_MAC_MAX_TEMP - - MAC_WARNING_THRESHOLD = module_product.MONITOR_MAC_WARNING_THRESHOLD - OUTTEMP_WARNING_THRESHOLD = module_product.MONITOR_OUTTEMP_WARNING_THRESHOLD - BOARDTEMP_WARNING_THRESHOLD = module_product.MONITOR_BOARDTEMP_WARNING_THRESHOLD - CPUTEMP_WARNING_THRESHOLD = module_product.MONITOR_CPUTEMP_WARNING_THRESHOLD - INTEMP_WARNING_THRESHOLD = module_product.MONITOR_INTEMP_WARNING_THRESHOLD - - MAC_CRITICAL_THRESHOLD = module_product.MONITOR_MAC_CRITICAL_THRESHOLD - OUTTEMP_CRITICAL_THRESHOLD = module_product.MONITOR_OUTTEMP_CRITICAL_THRESHOLD - BOARDTEMP_CRITICAL_THRESHOLD = module_product.MONITOR_BOARDTEMP_CRITICAL_THRESHOLD - CPUTEMP_CRITICAL_THRESHOLD = module_product.MONITOR_CPUTEMP_CRITICAL_THRESHOLD - INTEMP_CRITICAL_THRESHOLD = module_product.MONITOR_INTEMP_CRITICAL_THRESHOLD - CRITICAL_NUM = module_product.MONITOR_CRITICAL_NUM - SHAKE_TIME = module_product.MONITOR_SHAKE_TIME - MONITOR_INTERVAL = module_product.MONITOR_INTERVAL - MONITOR_FALL_TEMP = module_product.MONITOR_FALL_TEMP - - MONITOR_MAC_SOURCE_SYSFS = module_product.MONITOR_MAC_SOURCE_SYSFS - MONITOR_MAC_SOURCE_PATH = module_product.MONITOR_MAC_SOURCE_PATH - - -FANCTROLDEBUG = 0 # 1 means enable -DEVMONITORDEBUG = 0 # 1 means enable diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/script/ragileutil.py b/platform/broadcom/sonic-platform-modules-ragile/common/script/ragileutil.py deleted file mode 100755 index 72ff74c2daa1..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/common/script/ragileutil.py +++ /dev/null @@ -1,2099 +0,0 @@ -# -*- coding: UTF-8 -*- -# ------------------------------------------------------------------------- -# Name: ragileutil -# Purpose: common configuration and api -# -# Author: rd -# -# Created: 02/07/2018 -# Copyright: (c) rd 2018 -# ------------------------------------------------------------------------- -import sys -import os -import re -import syslog -import time -import binascii -import tty -import termios -import threading -import click -import mmap -from ragileconfig import ( - rg_eeprom, - FRULISTS, - MAC_DEFAULT_PARAM, - MAC_AVS_PARAM, - FANS_DEF, - FAN_PROTECT, - E2_LOC, - E2_PROTECT, - RAGILE_SERVICE_TAG, - RAGILE_DIAG_VERSION, - STARTMODULE, - RAGILE_CARDID, - RAGILE_PRODUCTNAME, - RAGILE_PART_NUMBER, - RAGILE_LABEL_REVISION, - RAGILE_MAC_SIZE, - RAGILE_MANUF_NAME, - RAGILE_MANUF_COUNTRY, - RAGILE_VENDOR_NAME, - MAILBOX_DIR, -) - -try: - from eepromutil.fru import ipmifru - from sonic_py_common.general import getstatusoutput_noshell, getstatusoutput_noshell_pipe - -except Exception or SystemExit: - pass - -import logging.handlers -import shutil -import gzip -import glob - -__all__ = [ - "MENUID", - "MENUPARENT", - "MENUVALUE", - "CHILDID", - "MENUITEMNAME", - "MENUITEMDEAL", - "GOBACK", - "GOQUIT", - "file_name", - "CRITICAL", - "FATAL", - "ERROR", - "WARNING", - "WARN", - "INFO", - "DEBUG", - "NOTSET", - "levelNames", - "TLV_INFO_ID_STRING", - "TLV_INFO_VERSION", - "TLV_INFO_LENGTH", - "TLV_INFO_LENGTH_VALUE", - "TLV_CODE_PRODUCT_NAME", - "TLV_CODE_PART_NUMBER", - "TLV_CODE_SERIAL_NUMBER", - "TLV_CODE_MAC_BASE", - "TLV_CODE_MANUF_DATE", - "TLV_CODE_DEVICE_VERSION", - "TLV_CODE_LABEL_REVISION", - "TLV_CODE_PLATFORM_NAME", - "TLV_CODE_ONIE_VERSION", - "TLV_CODE_MAC_SIZE", - "TLV_CODE_MANUF_NAME", - "TLV_CODE_MANUF_COUNTRY", - "TLV_CODE_VENDOR_NAME", - "TLV_CODE_DIAG_VERSION", - "TLV_CODE_SERVICE_TAG", - "TLV_CODE_VENDOR_EXT", - "TLV_CODE_CRC_32", - "_TLV_DISPLAY_VENDOR_EXT", - "TLV_CODE_RJ_CARID", - "_TLV_INFO_HDR_LEN", - "SYSLOG_IDENTIFIER", - "log_info", - "log_debug", - "log_warning", - "log_error", - "CompressedRotatingFileHandler", - "SETMACException", - "checkinput", - "checkinputproduct", - "getInputSetmac", - "fan_tlv", - "AVSUTIL", - "I2CUTIL", - "BMC", - "getSdkReg", - "getfilevalue", - "get_sysfs_value", - "write_sysfs_value", - "RJPRINTERR", - "strtoint", - "inttostr", - "str_to_hex", - "hex_to_str", - "str_to_bin", - "bin_to_str", - "get_mac_temp", - "get_mac_temp_sysfs", - "restartDockerService", - "wait_dhcp", - "wait_sdk", - "wait_docker", - "getTLV_BODY", - "_crc32", - "printvalue", - "generate_value", - "getsyseeprombyId", - "fac_init_cardidcheck", - "isValidMac", - "util_setmac", - "getInputCheck", - "getrawch", - "upper_input", - "changeTypeValue", - "astrcmp", - "generate_ext", - "rgi2cget", - "rgi2cset", - "rgpcird", - "rgpciwr", - "rgsysset", - "rgi2cget_word", - "rgi2cset_word", - "fan_setmac", - "checkfansninput", - "checkfanhwinput", - "util_show_fanse2", - "get_fane2_sysfs", - "util_show_fane2", - "getPid", - "fac_fans_setmac_tlv", - "fac_fan_setmac_fru", - "fac_fans_setmac", - "fac_fan_setmac", - "writeToEEprom", - "get_local_eth0_mac", - "getonieversion", - "createbmcMac", - "fac_board_setmac", - "ipmi_set_mac", - "getInputValue", - "bmc_setmac", - "closeProtocol", - "checkSdkMem", - "getch", - "get_raw_input", - "getsysvalue", - "get_pmc_register", - "decoder", - "decode_eeprom", - "get_sys_eeprom", - "getCardId", - "getsysmeminfo", - "getsysmeminfo_detail", - "getDmiSysByType", - "gethwsys", - "getsysbios", - "searchDirByName", - "getUsbLocation", - "getusbinfo", - "get_cpu_info", - "get_version_config_info", - "io_rd", - "io_wr", -] - -MENUID = "menuid" -MENUPARENT = "parentid" -MENUVALUE = "value" -CHILDID = "childid" -MENUITEMNAME = "name" -MENUITEMDEAL = "deal" -GOBACK = "goBack" -GOQUIT = "quit" - -file_name = "/etc/init.d/opennsl-modules-3.16.0-5-amd64" -########################################################################## -# ERROR LOG LEVEL -########################################################################## -CRITICAL = 50 -FATAL = CRITICAL -ERROR = 40 -WARNING = 30 -WARN = WARNING -INFO = 20 -DEBUG = 10 -NOTSET = 0 - -levelNames = { - CRITICAL: "CRITICAL", - ERROR: "ERROR", - WARNING: "WARNING", - INFO: "INFO", - DEBUG: "DEBUG", - NOTSET: "NOTSET", - "CRITICAL": CRITICAL, - "ERROR": ERROR, - "WARN": WARNING, - "WARNING": WARNING, - "INFO": INFO, - "DEBUG": DEBUG, - "NOTSET": NOTSET, -} - -TLV_INFO_ID_STRING = "TlvInfo\x00" -TLV_INFO_VERSION = 0x01 -TLV_INFO_LENGTH = 0x00 -TLV_INFO_LENGTH_VALUE = 0xBA - -########################################################################## -# eeprom info -########################################################################## -TLV_CODE_PRODUCT_NAME = 0x21 -TLV_CODE_PART_NUMBER = 0x22 -TLV_CODE_SERIAL_NUMBER = 0x23 -TLV_CODE_MAC_BASE = 0x24 -TLV_CODE_MANUF_DATE = 0x25 -TLV_CODE_DEVICE_VERSION = 0x26 -TLV_CODE_LABEL_REVISION = 0x27 -TLV_CODE_PLATFORM_NAME = 0x28 -TLV_CODE_ONIE_VERSION = 0x29 -TLV_CODE_MAC_SIZE = 0x2A -TLV_CODE_MANUF_NAME = 0x2B -TLV_CODE_MANUF_COUNTRY = 0x2C -TLV_CODE_VENDOR_NAME = 0x2D -TLV_CODE_DIAG_VERSION = 0x2E -TLV_CODE_SERVICE_TAG = 0x2F -TLV_CODE_VENDOR_EXT = 0xFD -TLV_CODE_CRC_32 = 0xFE -_TLV_DISPLAY_VENDOR_EXT = 1 -TLV_CODE_RJ_CARID = 0x01 -_TLV_INFO_HDR_LEN = 11 - - -SYSLOG_IDENTIFIER = "UTILTOOL" - -# ========================== Syslog wrappers ========================== - - -def log_info(msg, also_print_to_console=False): - syslog.openlog(SYSLOG_IDENTIFIER) - syslog.syslog(syslog.LOG_INFO, msg) - syslog.closelog() - - if also_print_to_console: - click.echo(msg) - - -def log_debug(msg, also_print_to_console=False): - try: - syslog.openlog(SYSLOG_IDENTIFIER) - syslog.syslog(syslog.LOG_DEBUG, msg) - syslog.closelog() - - if also_print_to_console: - click.echo(msg) - except Exception as e: - pass - - -def log_warning(msg, also_print_to_console=False): - syslog.openlog(SYSLOG_IDENTIFIER) - syslog.syslog(syslog.LOG_WARNING, msg) - syslog.closelog() - - if also_print_to_console: - click.echo(msg) - - -def log_error(msg, also_print_to_console=False): - syslog.openlog(SYSLOG_IDENTIFIER) - syslog.syslog(syslog.LOG_ERR, msg) - syslog.closelog() - - if also_print_to_console: - click.echo(msg) - - -class CompressedRotatingFileHandler(logging.handlers.RotatingFileHandler): - def doRollover(self): - """ - Do a rollover, as described in __init__(). - """ - if self.stream: - self.stream.close() - self.stream = None - if self.backupCount > 0: - for i in range(self.backupCount - 1, 0, -1): - sfn = "%s.%d.gz" % (self.baseFilename, i) - dfn = "%s.%d.gz" % (self.baseFilename, i + 1) - if os.path.exists(sfn): - if os.path.exists(dfn): - os.remove(dfn) - os.rename(sfn, dfn) - dfn = self.baseFilename + ".1.gz" - if os.path.exists(dfn): - os.remove(dfn) - # These two lines below are the only new lines. I commented out the os.rename(self.baseFilename, dfn) and - # replaced it with these two lines. - with open(self.baseFilename, "rb") as f_in, gzip.open(dfn, "wb") as f_out: - shutil.copyfileobj(f_in, f_out) - self.mode = "w" - self.stream = self._open() - - -class SETMACException(Exception): - def __init__(self, param="ERROR", errno="-1"): - err = "Setmac fail[%s]: %s" % (errno, param) - Exception.__init__(self, err) - self.param = param - self.errno = errno - - -def checkinput(b): - if b.isdigit() is False: - raise Exception("Ivalid Number") - if int(b) > 0xFF or int(b) < 0: - raise Exception("Out of area") - - -def checkinputproduct(b): - if b.isalnum() is False: - raise Exception("Invalid string") - - -def getInputSetmac(val): - bia = val.boardInfoArea - pia = val.productInfoArea - if bia is not None: - a = raw_input("[Board Card]Product Serial Number:") - if len(a) != 13: - raise Exception("Invalid Serial Number length") - checkinputproduct(a) - bia.boardSerialNumber = a - b = raw_input("[Board Card]Product Version:(from 1-255)") - checkinput(b) - b = "%0x" % int(b) - bia.boardextra1 = b.upper() - if pia is not None: - a = raw_input("[Product Area]Product Serial Number:") - if len(a) != 13: - raise Exception("Invalid Serial Number") - checkinputproduct(a) - pia.productSerialNumber = a - b = raw_input("[Product Area]Product Version:(from 1-255)") - checkinput(b) - b = "%0x" % int(b) - pia.productVersion = b.upper() - return val - - -class fan_tlv(object): - VERSION = 0x01 # E2PROM Version，start from 0x01 - FLAG = 0x7E # New E2PROM version flag is 0x7E - HW_VER = 0x01 # compose by master version and fixed version - TYPE = 0xF1 # hw type defination - TLV_LEN = 00 # data length (16bit) - _FAN_TLV_HDR_LEN = 6 - _FAN_TLV_CRC_LEN = 2 - - _FAN_TLV_TYPE_NAME = 0x02 - _FAN_TLV_TYPE_SN = 0x03 - _FAN_TLV_TYPE_HW_INFO = 0x05 - _FAN_TLV_TYPE_DEV_TYPE = 0x06 - - _fandecodetime = 0 - - @property - def dstatus(self): - return self._dstatus - - @property - def typename(self): - return self._typename - - @property - def typesn(self): - return self._typesn - - @property - def typehwinfo(self): - return self._typehwinfo - - @property - def typedevtype(self): - return self._typedevtype - - @property - def fanbus(self): - return self._fanbus - - @property - def fanloc(self): - return self._fanloc - - @property - def fandecodetime(self): - return self._fandecodetime - - def __init__(self): - self._typename = "" - self._typesn = "" - self._typehwinfo = "" - self._typedevtype = "" - self._dstatus = 0 - - def strtoarr(self, str): - s = [] - if str is not None: - for index in range(len(str)): - s.append(str[index]) - return s - - def generate_fan_value(self): - bin_buffer = [chr(0xFF)] * 256 - bin_buffer[0] = chr(self.VERSION) - bin_buffer[1] = chr(self.FLAG) - bin_buffer[2] = chr(self.HW_VER) - bin_buffer[3] = chr(self.TYPE) - - temp_t = "%08x" % self.typedevtype # handle devtype first - typedevtype_t = hex_to_str(temp_t) - total_len = ( - len(self.typename) - + len(self.typesn) - + len(self.typehwinfo) - + len(typedevtype_t) - + 8 - ) - - bin_buffer[4] = chr(total_len >> 8) - bin_buffer[5] = chr(total_len & 0x00FF) - - index_start = 6 - bin_buffer[index_start] = chr(self._FAN_TLV_TYPE_NAME) - bin_buffer[index_start + 1] = chr(len(self.typename)) - bin_buffer[ - index_start + 2 : index_start + 2 + len(self.typename) - ] = self.strtoarr(self.typename) - index_start = index_start + 2 + len(self.typename) - - bin_buffer[index_start] = chr(self._FAN_TLV_TYPE_SN) - bin_buffer[index_start + 1] = chr(len(self.typesn)) - bin_buffer[ - index_start + 2 : index_start + 2 + len(self.typesn) - ] = self.strtoarr(self.typesn) - index_start = index_start + 2 + len(self.typesn) - - bin_buffer[index_start] = chr(self._FAN_TLV_TYPE_HW_INFO) - bin_buffer[index_start + 1] = chr(len(self.typehwinfo)) - bin_buffer[ - index_start + 2 : index_start + 2 + len(self.typehwinfo) - ] = self.strtoarr(self.typehwinfo) - index_start = index_start + 2 + len(self.typehwinfo) - - bin_buffer[index_start] = chr(self._FAN_TLV_TYPE_DEV_TYPE) - bin_buffer[index_start + 1] = chr(len(typedevtype_t)) - bin_buffer[ - index_start + 2 : index_start + 2 + len(typedevtype_t) - ] = self.strtoarr(typedevtype_t) - index_start = index_start + 2 + len(typedevtype_t) - - crcs = fan_tlv.fancrc("".join(bin_buffer[0:index_start])) # check 2bytes - bin_buffer[index_start] = chr(crcs >> 8) - bin_buffer[index_start + 1] = chr(crcs & 0x00FF) - return bin_buffer - - def decode(self, e2): - ret = [] - self.VERSION = ord(e2[0]) - self.FLAG = ord(e2[1]) - self.HW_VER = ord(e2[2]) - self.TYPE = ord(e2[3]) - self.TLV_LEN = (ord(e2[4]) << 8) | ord(e2[5]) - - tlv_index = self._FAN_TLV_HDR_LEN - tlv_end = self._FAN_TLV_HDR_LEN + self.TLV_LEN - - # check checksum - if len(e2) < self._FAN_TLV_HDR_LEN + self.TLV_LEN + 2: - self._dstatus = -2 - return ret - sumcrc = fan_tlv.fancrc(e2[0 : self._FAN_TLV_HDR_LEN + self.TLV_LEN]) - readcrc = ord(e2[self._FAN_TLV_HDR_LEN + self.TLV_LEN]) << 8 | ord( - e2[self._FAN_TLV_HDR_LEN + self.TLV_LEN + 1] - ) - if sumcrc != readcrc: - self._dstatus = -1 - return ret - else: - self._dstatus = 0 - while (tlv_index + 2) < len(e2) and tlv_index < tlv_end: - s = self.decoder(e2[tlv_index : tlv_index + 2 + ord(e2[tlv_index + 1])]) - tlv_index += ord(e2[tlv_index + 1]) + 2 - ret.append(s) - - return ret - - @staticmethod - def fancrc(t): - sum = 0 - for index in range(len(t)): - sum += ord(t[index]) - return sum - - def decoder(self, t): - try: - name = "" - value = "" - if ord(t[0]) == self._FAN_TLV_TYPE_NAME: - name = "Product Name" - value = str(t[2 : 2 + ord(t[1])]) - self._typename = value - elif ord(t[0]) == self._FAN_TLV_TYPE_SN: - name = "serial Number" - value = str(t[2 : 2 + ord(t[1])]) - self._typesn = value - elif ord(t[0]) == self._FAN_TLV_TYPE_HW_INFO: - name = "hardware info" - value = str(t[2 : 2 + ord(t[1])]) - self._typehwinfo = value - elif ord(t[0]) == self._FAN_TLV_TYPE_DEV_TYPE: - name = "dev type" - value = str(t[2 : 2 + ord(t[1])]) - value = str_to_hex(value) - self._typedevtype = value - value = "0x08%x" % value - except Exception as e: - print(e) - return {"name": name, "code": ord(t[0]), "value": value} - - def __str__(self): - formatstr = ( - "VERSION : 0x%02x \n" - " FLAG : 0x%02x \n" - " HW_VER : 0x%02x \n" - " TYPE : 0x%02x \n" - "typename : %s \n" - "typesn : %s \n" - "typehwinfo : %s \n" - ) - return formatstr % ( - self.VERSION, - self.FLAG, - self.HW_VER, - self.TYPE, - self.typename, - self.typesn, - self.typehwinfo, - ) - - -class AVSUTIL: - @staticmethod - def mac_avs_chip(bus, devno, loc, open, close, loop, protectaddr, level, loopaddr): - # disable protection - rgi2cset(bus, devno, protectaddr, open) - rgi2cset(bus, devno, loopaddr, loop) - rgi2cset_word(bus, devno, loc, level) - ret, value = rgi2cget_word(bus, devno, loc) - if strtoint(value) == level: - ret = 0 - # enable protection - rgi2cset(bus, devno, protectaddr, close) - if ret == 0: - return True - return False - - @staticmethod - def macPressure_adj(macavs, avs_param, mac_def_param): - # check whether it within range - max_adj = max(avs_param.keys()) - min_adj = min(avs_param.keys()) - type = mac_def_param["type"] - level = 0 - if type == 0: - if macavs not in range(min_adj, max_adj + 1): - return False - else: - level = macavs - else: - if macavs not in range(min_adj, max_adj + 1): - level = mac_def_param["default"] - else: - level = macavs - ret = AVSUTIL.mac_avs_chip( - mac_def_param["bus"], - mac_def_param["devno"], - mac_def_param["addr"], - mac_def_param["open"], - mac_def_param["close"], - mac_def_param["loop"], - mac_def_param["protectaddr"], - avs_param[level], - mac_def_param["loopaddr"], - ) - return ret - - @staticmethod - def mac_adj(): - macavs = 0 - name = MAC_DEFAULT_PARAM["sdkreg"] - ret, status = getSdkReg(name) - if ret is False: - return False - status = strtoint(status) - # shift operation - if MAC_DEFAULT_PARAM["sdktype"] != 0: - status = (status >> MAC_DEFAULT_PARAM["macregloc"]) & MAC_DEFAULT_PARAM[ - "mask" - ] - macavs = status - ret = AVSUTIL.macPressure_adj(macavs, MAC_AVS_PARAM, MAC_DEFAULT_PARAM) - return ret - - -class I2CUTIL: - @staticmethod - def getvaluefromdevice(name): - ret = [] - for item in DEVICE: - if item["name"] == name: - ret.append(item) - return ret - - @staticmethod - def openFanE2Protect(): - rgi2cset( - FAN_PROTECT["bus"], - FAN_PROTECT["devno"], - FAN_PROTECT["addr"], - FAN_PROTECT["open"], - ) - - @staticmethod - def closeFanE2Protect(): - rgi2cset( - FAN_PROTECT["bus"], - FAN_PROTECT["devno"], - FAN_PROTECT["addr"], - FAN_PROTECT["close"], - ) - - @staticmethod - def writeToFanE2(bus, loc, rst_arr): - index = 0 - for item in rst_arr: - rgi2cset(bus, loc, index, ord(item)) - index += 1 - - @staticmethod - def writeToE2(bus, loc, rst_arr): - index = 0 - for item in rst_arr: - rgi2cset(bus, loc, index, ord(item)) - index += 1 - - @staticmethod - def getE2File(bus, loc): - return "/sys/bus/i2c/devices/%d-00%02x/eeprom" % (bus, loc) - - -class BMC: - _instance_lock = threading.Lock() - - def __init__(self): - pass - - def __new__(cls, *args, **kwargs): - if not hasattr(Singleton, "_instance"): - with Singleton._instance_lock: - if not hasattr(Singleton, "_instance"): - Singleton._instance = object.__new__(cls) - return Singleton._instance - - -# Internal interface - - -def getSdkReg(reg): - try: - cmd = ["bcmcmd", "-t", "1", 'getr '+str(reg)] - ret, result = getstatusoutput_noshell(cmd) - result_t = result.strip().replace("\r", "").replace("\n", "") - if ret != 0 or "Error:" in result_t: - return False, result - patt = r"%s.(.*):(.*)>drivshell" % reg - rt = re.findall(patt, result_t, re.S) - test = re.findall("=(.*)", rt[0][0])[0] - except Exception as e: - return False, "getsdk register error" - return True, test - - -def getfilevalue(location): - try: - with open(location, "r") as fd: - value = fd.read() - return True, value.strip() - except Exception as e: - return False, "error" - - -def get_sysfs_value(location): - pos_t = str(location) - name = get_pmc_register(pos_t) - return name - - -def write_sysfs_value(reg_name, value): - fileLoc = MAILBOX_DIR + reg_name - try: - if not os.path.isfile(fileLoc): - print(fileLoc, "not found !") - return False - with open(fileLoc, "w") as fd: - fd.write(value) - except Exception as error: - log_error("Unable to open " + fileLoc + "file !") - return False - return True - - -def RJPRINTERR(str): - print("\033[0;31m%s\033[0m" % str) - - -def strtoint(str): # convert Hex string to int such as "4040"/"0x4040"/"0X4040" = 16448 - value = 0 - rest_v = str.replace("0X", "").replace("0x", "") - for index in range(len(rest_v)): - print(rest_v[index]) - value |= int(rest_v[index], 16) << ((len(rest_v) - index - 1) * 4) - return value - - -def inttostr(vl, len): # convert int to string such as 0x3030 = 00 - if type(vl) != int: - raise Exception(" type error") - index = 0 - ret_t = "" - while index < len: - ret = 0xFF & (vl >> index * 8) - ret_t += chr(ret) - index += 1 - return ret_t - - -def str_to_hex(rest_v): - value = 0 - for index in range(len(rest_v)): - value |= ord(rest_v[index]) << ((len(rest_v) - index - 1) * 8) - return value - - -def hex_to_str(s): - len_t = len(s) - if len_t % 2 != 0: - return 0 - ret = "" - for t in range(0, int(len_t / 2)): - ret += chr(int(s[2 * t : 2 * t + 2], 16)) - return ret - - -def str_to_bin(s): - return " ".join([bin(ord(c)).replace("0b", "") for c in s]) - - -def bin_to_str(s): - return "".join([chr(i) for i in [int(b, 2) for b in s.split(" ")]]) - - -def get_mac_temp(): - result = {} - # wait_docker() - # exec twice, get the second result - getstatusoutput_noshell(["bcmcmd", "-t", "1", "show temp"]) - ret, log = getstatusoutput_noshell(["bcmcmd", "-t", "1", "show temp"]) - if ret: - return False, result - else: - # decode obtained info - logs = log.splitlines() - for line in logs: - if "average" in line: - b = re.findall(r"\d+.\d+", line) - result["average"] = b[0] - elif "maximum" in line: - b = re.findall(r"\d+.\d+", line) - result["maximum"] = b[0] - return True, result - - -def get_mac_temp_sysfs(mactempconf): - try: - temp = -1000000 - temp_list = [] - mac_temp_loc = mactempconf.get("loc", []) - mac_temp_flag = mactempconf.get("flag", None) - if mac_temp_flag is not None: # check mac temperature vaild flag - gettype = mac_temp_flag.get("gettype") - okbit = mac_temp_flag.get("okbit") - okval = mac_temp_flag.get("okval") - if gettype == "io": - io_addr = mac_temp_flag.get("io_addr") - val = io_rd(io_addr) - if val is None: - raise Exception("get mac_flag by io failed.") - else: - bus = mac_temp_flag.get("bus") - loc = mac_temp_flag.get("loc") - offset = mac_temp_flag.get("offset") - ind, val = rgi2cget(bus, loc, offset) - if ind is not True: - raise Exception("get mac_flag by i2c failed.") - val_t = (int(val, 16) & (1 << okbit)) >> okbit - if val_t != okval: - raise Exception("mac_flag invalid, val_t:%d." % val_t) - for loc in mac_temp_loc: - temp_s = get_sysfs_value(loc) - if isinstance(temp_s, str) and temp_s.startswith("ERR"): - raise Exception("get mac temp error. loc:%s" % loc) - temp_t = int(temp_s) - if temp_t == -1000000: - raise Exception("mac temp invalid.loc:%s" % loc) - temp_list.append(temp_t) - temp_list.sort(reverse=True) - temp = temp_list[0] - except Exception as e: - return False, temp - return True, temp - - -def restartDockerService(force=False): - container_name = [ - "database", - "snmp", - "syncd", - "swss", - "dhcp_relay", - "radv", - "teamd", - "pmon", - ] - ret, status = getstatusoutput_noshell(["docker", "ps"]) - if ret == 0: - for tmpname in container_name: - if tmpname not in status: - if force == True: - getstatusoutput_noshell(["docker", "restart", tmpname]) - else: - getstatusoutput_noshell(["systemctl", "restart", tmpname]) - - -def wait_dhcp(timeout): - time_cnt = 0 - while True: - try: - ret, status = getstatusoutput_noshell(["systemctl", "status", "dhcp_relay.service"]) - if (ret == 0 and "running" in status) or "SUCCESS" in status: - break - else: - sys.stdout.write(".") - sys.stdout.flush() - time_cnt = time_cnt + 1 - if time_cnt > timeout: - raise Exception("wait_dhcp timeout") - time.sleep(1) - except Exception as e: - return False - return True - - -def wait_sdk(sdk_fpath, timeout): - time_cnt = 0 - while True: - try: - if os.path.exists(sdk_fpath): - break - else: - sys.stdout.write(".") - sys.stdout.flush() - time_cnt = time_cnt + 1 - if time_cnt > timeout: - raise Exception("wait_sdk timeout") - time.sleep(1) - except Exception as e: - return False - return True - - -def wait_docker(need_restart=False, timeout=180): - sdkcheck_params = STARTMODULE.get("sdkcheck", {}) - if sdkcheck_params.get("checktype") == "file": # pass file check - sdk_fpath = sdkcheck_params.get("sdk_fpath") - return wait_sdk(sdk_fpath, timeout) - return wait_dhcp(timeout) - - -def getTLV_BODY(type, productname): - x = [] - temp_t = "" - if type == TLV_CODE_MAC_BASE: - arr = productname.split(":") - for tt in arr: - temp_t += chr(int(tt, 16)) - elif type == TLV_CODE_DEVICE_VERSION: - temp_t = chr(productname) - elif type == TLV_CODE_MAC_SIZE: - temp_t = chr(productname >> 8) + chr(productname & 0x00FF) - else: - temp_t = productname - x.append(chr(type)) - x.append(chr(len(temp_t))) - for i in temp_t: - x.append(i) - return x - - -def _crc32(v): - return "0x%08x" % ( - binascii.crc32(v) & 0xFFFFFFFF - ) # get 8 bytes of crc32 %x return hex - - -def printvalue(b): - index = 0 - for i in range(0, len(b)): - if index % 16 == 0: - print(" ") - print("%02x " % ord(b[i])) - index += 1 - print("\n") - - -def generate_value(_t): - ret = [] - for i in TLV_INFO_ID_STRING: - ret.append(i) - ret.append(chr(TLV_INFO_VERSION)) - ret.append(chr(TLV_INFO_LENGTH)) - ret.append(chr(TLV_INFO_LENGTH_VALUE)) - - total_len = 0 - for key in _t: - x = getTLV_BODY(key, _t[key]) - ret += x - total_len += len(x) - ret[10] = chr(total_len + 6) - - ret.append(chr(0xFE)) - ret.append(chr(0x04)) - s = _crc32("".join(ret)) - for t in range(0, 4): - ret.append(chr(int(s[2 * t + 2 : 2 * t + 4], 16))) - totallen = len(ret) - if totallen < 256: - for left_t in range(0, 256 - totallen): - ret.append(chr(0x00)) - return (ret, True) - - -def getsyseeprombyId(id): - ret = get_sys_eeprom() - for item in ret: - if item["code"] == id: - return item - return None - - -def fac_init_cardidcheck(): - rest = getsyseeprombyId(TLV_CODE_RJ_CARID) # check cardId same or not - if rest is None: - print("need to program write bin file") - return False - else: - rest_v = rest["value"] - value = strtoint(rest_v) - if value == RAGILE_CARDID: - log_debug("check card ID pass") - else: - log_debug("check card ID error") - return False - return True - - -def isValidMac(mac): - if re.match(r"^\s*([0-9a-fA-F]{2,2}:){5,5}[0-9a-fA-F]{2,2}\s*$", mac): - return True - return False - - -# Internet cardsetmac - - -def util_setmac(eth, mac): - rulefile = "/etc/udev/rules.d/70-persistent-net.rules" - if isValidMac(mac) is False: - return False, "MAC invaild" - cmd1 = ["ethtool", "-e", eth] - cmd2 = ["grep", "0x0010"] - cmd3 = ["awk", '{print \"0x\"$13$12$15$14}'] - ret, log = getstatusoutput_noshell_pipe(cmd1, cmd2, cmd3) - log_debug(log) - magic = "" - if ret == 0 and len(log): - magic = log - macs = mac.upper().split(":") - - # chage ETH0 to value after setmac - ifconfigcmd = ["ifconfig", "eth0", "hw", "ether", mac] - log_debug(ifconfigcmd) - ret, status = getstatusoutput_noshell(ifconfigcmd) - if ret: - raise SETMACException("software set Internet card MAC error") - index = 0 - for item in macs: - cmd = ["ethtool", "-E", eth, "magic", magic, "offset", str(offset), "value", "0x"+str(item)] - log_debug(cmd) - index += 1 - ret, log = getstatusoutput_noshell(cmd) - if ret != 0: - raise SETMACException("set hardware Internet card MAC error") - # get value after setting - cmd_t = ["ethtool", "-e", "eth0", "offset", "0", "length", "6"] - ret, log = getstatusoutput_noshell(cmd_t) - m = re.split(":", log)[-1].strip().upper() - mac_result = m.upper().split(" ") - - for ind, s in enumerate(macs): - if s != mac_result[ind]: - RJPRINTERR("MAC comparison error") - if os.path.exists(rulefile): - os.remove(rulefile) - print("MGMT MAC[%s]" % mac) - return True - - -def getInputCheck(tips): - str = raw_input(tips) - if ( - astrcmp(str, "y") - or astrcmp(str, "ye") - or astrcmp(str, "yes") - or astrcmp(str, "") - ): - return True - else: - return False - - -def getrawch(): - fd = sys.stdin.fileno() - old_settings = termios.tcgetattr(fd) - try: - tty.setraw(sys.stdin.fileno()) - ch = sys.stdin.read(1) - finally: - termios.tcsetattr(fd, termios.TCSADRAIN, old_settings) - return ch - - -def upper_input(tips): - sys.stdout.write(tips) - sys.stdout.flush() - passwd = [] - while True: - ch = getrawch().upper() - if ch == "\r" or ch == "\n": - return "".join(passwd) - elif ch == "\b" or ord(ch) == 127: - if passwd: - del passwd[-1] - sys.stdout.write("\b \b") - else: - sys.stdout.write(ch) - passwd.append(ch) - - -def changeTypeValue(_value, type1, tips, example): - if type1 == TLV_CODE_PRODUCT_NAME: - while True: - print( - "please check (1)air from forward to backward/(2)air from backward to forward:" - ) - option = raw_input() - if option == "1": - _value[type1] = example + "-F-RJ" - print( - "check Product is air from forward to backward device,Product Name:%s" - % _value[type1] - ) - break - elif option == "2": - _value[type1] = example + "-R-RJ" - print( - "check Product is air from backward to forward device,Product Name:%s" - % _value[type1] - ) - break - else: - print("input incorrect, check please") - return True - print("Please input[%s]such as(%s):" % (tips, example)) - name = upper_input("") - if type1 == TLV_CODE_MAC_BASE: - if len(name) != 12: - raise SETMACException("MAC address length incorrect, check please") - release_mac = "" - for i in range(int(len(name) / 2)): - if i == 0: - release_mac += name[i * 2 : i * 2 + 2] - else: - release_mac += ":" + name[i * 2 : i * 2 + 2] - if isValidMac(release_mac) is True: - _value[type1] = release_mac - else: - raise SETMACException("MAC address invaild, check please") - elif type1 == TLV_CODE_DEVICE_VERSION: - if name.isdigit(): - _value[type1] = int(name) - else: - raise SETMACException("Version is not number, check please") - elif type1 == TLV_CODE_MAC_SIZE: - if name.isdigit(): - _value[type1] = int(name, 16) - else: - raise SETMACException("Version is not number, check please") - elif type1 == TLV_CODE_SERIAL_NUMBER: - if name.isalnum() is False: - raise SETMACException("Serial Number invaild string, check please") - elif len(name) != 13: - raise SETMACException("Serial Number length incorrect, check please") - else: - _value[type1] = name - elif type1 == TLV_CODE_VENDOR_EXT: - _value[type1] = name - else: - _value[type1] = name - return True - - -def astrcmp(str1, str2): - return str1.lower() == str2.lower() - - -def generate_ext(cardid): - s = "%08x" % cardid - ret = "" - for t in range(0, 4): - ret += chr(int(s[2 * t : 2 * t + 2], 16)) - ret = chr(0x01) + chr(len(ret)) + ret - return ret - - -def rgi2cget(bus, devno, address): - command_line = ["i2cget", "-f", "-y", str(bus), "0x%02x"%devno, "0x%02x"%address] - retrytime = 6 - ret_t = "" - for i in range(retrytime): - ret, ret_t = getstatusoutput_noshell(command_line) - if ret == 0: - return True, ret_t - time.sleep(0.1) - return False, ret_t - - -def rgi2cset(bus, devno, address, byte): - command_line = ["i2cset", "-f", "-y", str(bus), "0x%02x"%devno, "0x%02x"%address, "0x%02x"%byte] - retrytime = 6 - ret_t = "" - for i in range(retrytime): - ret, ret_t = getstatusoutput_noshell(command_line) - if ret == 0: - return True, ret_t - return False, ret_t - - -def rgpcird(pcibus, slot, fn, bar, offset): - """read pci register""" - if offset % 4 != 0: - return - filename = "/sys/bus/pci/devices/0000:%02x:%02x.%x/resource%d" % ( - int(pcibus), - int(slot), - int(fn), - int(bar), - ) - file = open(filename, "r+") - size = os.path.getsize(filename) - data = mmap.mmap(file.fileno(), size) - result = data[offset : offset + 4] - s = result[::-1] - val = 0 - for i in range(0, len(s)): - val = val << 8 | s[i] - return "0x%08x" % val - - -def rgpciwr(pcibus, slot, fn, bar, offset, data): - """write pci register""" - ret = inttostr(data, 4) - ret = str.encode(ret) - ret = ret.strip(b'\xc2') - filename = "/sys/bus/pci/devices/0000:%02x:%02x.%x/resource%d" % ( - int(pcibus), - int(slot), - int(fn), - int(bar), - ) - file = open(filename, "r+") - size = os.path.getsize(filename) - data = mmap.mmap(file.fileno(), size) - data[offset : offset + 4] = ret - result = data[offset : offset + 4] - s = result[::-1] - val = 0 - for i in range(0, len(s)): - val = val << 8 | s[i] - data.close() - - -def rgsysset(location, value): - retrytime = 6 - for i in range(retrytime): - try: - with open(location, 'w') as f: - f.write('0x%02x\n' % value) - except (IOError, FileNotFoundError) as e: - return False, str(e) - return True, '' - - -def rgi2cget_word(bus, devno, address): - command_line = ["i2cget", "-f", "-y", str(bus), "0x%02x"%devno, "0x%02x"%address, 'w'] - retrytime = 3 - ret_t = "" - for i in range(retrytime): - ret, ret_t = getstatusoutput_noshell(command_line) - if ret == 0: - return True, ret_t - return False, ret_t - - -def rgi2cset_word(bus, devno, address, byte): - command_line = ["i2cset", "-f", "-y", str(bus), "0x%02x"%devno, "0x%02x"%address, "0x%02x"%byte, 'w'] - getstatusoutput_noshell(command_line) - - -def fan_setmac(): - rgi2cset( - FAN_PROTECT["bus"], - FAN_PROTECT["devno"], - FAN_PROTECT["addr"], - FAN_PROTECT["open"], - ) - rgi2cset( - FAN_PROTECT["bus"], - FAN_PROTECT["devno"], - FAN_PROTECT["addr"], - FAN_PROTECT["close"], - ) - - -def checkfansninput(fan_sn, fansntemp): - if fan_sn in fansntemp: - RJPRINTERR("exist same Serial Number，please input again") - return False - if len(fan_sn) != 13: - RJPRINTERR("Serial Number length incorrect，please input again") - return False - return True - - -# check hw version -def checkfanhwinput(hw): - if len(hw) != 4: - RJPRINTERR("hardware version length incorrect, please input again") - return False - if hw.find(".") != 1: - RJPRINTERR("hardware version incorrect, please input again") - return False - return True - - -def util_show_fanse2(fans): - formatstr = "%-8s %-20s %-20s %-20s %-20s" - print(formatstr % ("id", "Name", "hardware version", "Serial Number", "Time")) - print( - formatstr - % ("------", "---------------", "---------------", "---------------", "----") - ) - for fan in fans: - # print fan.dstatus - if fan.dstatus < 0: - print("%-8s" % ("FAN%d" % (fans.index(fan) + 1))) - RJPRINTERR(" decode e2 error") - else: - print( - formatstr - % ( - "FAN%d" % (fans.index(fan) + 1), - fan.typename.replace(chr(0x00), ""), - fan.typehwinfo.replace(chr(0x00), ""), - fan.typesn.replace(chr(0x00), ""), - fan.fandecodetime, - ) - ) - - -def get_fane2_sysfs(bus, loc): - rg_fan_e2 = "%d-%04x/fan" % (bus, loc) - eeprom = get_sysfs_value(rg_fan_e2) - return eeprom - - -def util_show_fane2(): - ret = sorted(I2CUTIL.getvaluefromdevice("rg_fan")) - if len(ret) <= 0: - return None - fans = [] - for index in range(len(ret)): - t1 = int(round(time.time() * 1000)) - eeprom = get_fane2_sysfs(ret[index]["bus"], ret[index]["loc"]) - t2 = int(round(time.time() * 1000)) - fane2 = fan_tlv() - fane2.fandecodetime = t2 - t1 - fane2.decode(eeprom) - fans.append(fane2) - util_show_fanse2(fans) - - -def getPid(name): - ret = [] - for dirname in os.listdir("/proc"): - if dirname == "curproc": - continue - try: - with open("/proc/{}/cmdline".format(dirname), mode="rb") as fd: - content = fd.read() - except Exception: - continue - if name in content: - ret.append(dirname) - return ret - - -def fac_fans_setmac_tlv(ret): - if len(ret) <= 0: - return None - fans = [] - fansntemp = [] - for index in range(len(ret)): - item = ret[index] - log_debug(item) - eeprom = get_fane2_sysfs(item["bus"], item["loc"]) - fane2 = fan_tlv() - fane2.decode(eeprom) - fane2.fanbus = item["bus"] - fane2.fanloc = item["loc"] - log_debug("decode eeprom success") - - print("Fan[%d]-[%s]setmac" % ((index + 1), FANS_DEF[fane2.typedevtype])) - while True: - print("Please input[%s]:" % "Serial Number") - fan_sn = raw_input() - if checkfansninput(fan_sn, fansntemp) is False: - continue - fansntemp.append(fan_sn) - fan_sn = fan_sn + chr(0x00) - fane2.typesn = fan_sn + chr(0x00) - break - while True: - print("Please input[%s]:" % "hardware version") - hwinfo = raw_input() - if checkfanhwinput(hwinfo) is False: - continue - fan_hwinfo = hwinfo + chr(0x00) - fane2.typehwinfo = fan_hwinfo + chr(0x00) - break - log_debug(fane2.typedevtype) - fane2.typename = FANS_DEF[fane2.typedevtype] + chr(0x00) - fans.append(fane2) - print("\n") - print("\n*******************************\n") - - util_show_fanse2(fans) - if getInputCheck("check input correctly or not（Yes/No):") is True: - for fan in fans: - log_debug("ouput fan") - fac_fan_setmac(fan) - else: - print("setmac quit") - return False - - -def fac_fan_setmac_fru(ret): - fans = FRULISTS.get("fans") - - fanfrus = {} - newfrus = {} - - # getmsg - try: - for fan in fans: - print("===============%s ================getmessage" % fan.get("name")) - eeprom = getsysvalue(I2CUTIL.getE2File(fan.get("bus"), fan.get("loc"))) - fru = ipmifru() - fru.decodeBin(eeprom) - fanfrus[fan.get("name")] = fru - except Exception as e: - print(str(e)) - return False - - # setmsg - for fan in fans: - print("===============%s ================setmac" % fan.get("name")) - fruold = fanfrus.get(fan.get("name")) - newfru = getInputSetmac(fruold) - newfru.recalcute() - newfrus[fan.get("name")] = newfru - # writemsg - for fan in fans: - print("===============%s ================writeToE2" % fan.get("name")) - ret_t = newfrus.get(fan.get("name")) - I2CUTIL.openFanE2Protect() - I2CUTIL.writeToFanE2(fan.get("bus"), fan.get("loc"), ret_t.bindata) - I2CUTIL.closeFanE2Protect() - # check - try: - for fan in fans: - print("===============%s ================getmessage" % fan.get("name")) - eeprom = getsysvalue(I2CUTIL.getE2File(fan.get("bus"), fan.get("loc"))) - fru = ipmifru() - fru.decodeBin(eeprom) - except Exception as e: - print(str(e)) - return False - return True - - -def fac_fans_setmac(): - ret = I2CUTIL.getvaluefromdevice("rg_fan") - if ret is not None and len(ret) > 0: - return fac_fans_setmac_tlv(ret) - fans = FRULISTS.get("fans", None) - if fans is not None and len(fans) > 0: - return fac_fan_setmac_fru(ret) - return False - - -def fac_fan_setmac(item): - I2CUTIL.openFanE2Protect() - I2CUTIL.writeToFanE2(item.fanbus, item.fanloc, item.generate_fan_value()) - I2CUTIL.closeFanE2Protect() - - -def writeToEEprom(rst_arr): - dealtype = E2_PROTECT.get("gettype", None) - if dealtype is None: - rgi2cset( - E2_PROTECT["bus"], - E2_PROTECT["devno"], - E2_PROTECT["addr"], - E2_PROTECT["open"], - ) - elif dealtype == "io": - io_wr(E2_PROTECT["io_addr"], E2_PROTECT["open"]) - index = 0 - for item in rst_arr: - rgi2cset(E2_LOC["bus"], E2_LOC["devno"], index, ord(item)) - index += 1 - - if dealtype is None: - rgi2cset( - E2_PROTECT["bus"], - E2_PROTECT["devno"], - E2_PROTECT["addr"], - E2_PROTECT["close"], - ) - elif dealtype == "io": - io_wr(E2_PROTECT["io_addr"], E2_PROTECT["close"]) - # deal last drivers - subprocess.call(["rmmod", "at24"]) - subprocess.call(["modprobe", "at24"]) - subprocess.call(["rm", "-f", "/var/cache/sonic/decode-syseeprom/syseeprom_cache"]) - - -def get_local_eth0_mac(): - cmd1 = ["ifconfig", "eth0"] - cmd2 = ["grep", "HWaddr"] - print(getstatusoutput_noshell_pipe(cmd1, cmd2)) - - -def getonieversion(): - if not os.path.isfile("/host/machine.conf"): - return "" - machine_vars = {} - with open("/host/machine.conf") as machine_file: - for line in machine_file: - tokens = line.split("=") - if len(tokens) < 2: - continue - machine_vars[tokens[0]] = tokens[1].strip() - return machine_vars.get("onie_version") - - -def createbmcMac(cpumac, num=2): - bcmvalue = strtoint(cpumac[cpumac.rindex(":") + 1 : len(cpumac)]) + num - # bmcmac = - t = cpumac.split(":") - t[5] = "%02x" % bcmvalue - bmcmac = ":".join(t) - return bmcmac.upper() - - -def fac_board_setmac(): - _value = {} - # default value - _value[TLV_CODE_VENDOR_EXT] = generate_ext(RAGILE_CARDID) # generate id - _value[TLV_CODE_PRODUCT_NAME] = RAGILE_PRODUCTNAME - _value[TLV_CODE_PART_NUMBER] = RAGILE_PART_NUMBER - _value[TLV_CODE_LABEL_REVISION] = RAGILE_LABEL_REVISION - _value[TLV_CODE_PLATFORM_NAME] = platform - _value[TLV_CODE_ONIE_VERSION] = getonieversion() - _value[TLV_CODE_MAC_SIZE] = RAGILE_MAC_SIZE - _value[TLV_CODE_MANUF_NAME] = RAGILE_MANUF_NAME - _value[TLV_CODE_MANUF_COUNTRY] = RAGILE_MANUF_COUNTRY - _value[TLV_CODE_VENDOR_NAME] = RAGILE_VENDOR_NAME - _value[TLV_CODE_DIAG_VERSION] = RAGILE_DIAG_VERSION - _value[TLV_CODE_SERVICE_TAG] = RAGILE_SERVICE_TAG - try: - if 0x00004052 == RAGILE_CARDID: - _value[TLV_CODE_PRODUCT_NAME] = RAGILE_PRODUCTNAME + "-RJ" - elif 0x00004051 == RAGILE_CARDID or 0x00004050 == RAGILE_CARDID: - changeTypeValue( - _value, TLV_CODE_PRODUCT_NAME, "Product name", RAGILE_PRODUCTNAME - ) - - changeTypeValue( - _value, TLV_CODE_SERIAL_NUMBER, "SN", "0000000000000" - ) # add serial number - changeTypeValue( - _value, TLV_CODE_DEVICE_VERSION, "hardware version", "101" - ) # hardware version - changeTypeValue( - _value, TLV_CODE_MAC_BASE, "MAC address", "58696cfb2108" - ) # MAC address - _value[TLV_CODE_MANUF_DATE] = time.strftime( - "%m/%d/%Y %H:%M:%S", time.localtime() - ) # add setmac time - rst, ret = generate_value(_value) - if ( - util_setmac("eth0", _value[TLV_CODE_MAC_BASE]) is True - ): # set Internet cardIP - writeToEEprom(rst) # write to e2 - # set BMC MAC - if "bmcsetmac" in FACTESTMODULE and FACTESTMODULE["bmcsetmac"] == 1: - bmcmac = createbmcMac(_value[TLV_CODE_MAC_BASE]) - if ipmi_set_mac(bmcmac) is True: - print("BMC MAC[%s]" % bmcmac) - else: - print("SET BMC MAC FAILED") - return False - else: - return False - except SETMACException as e: - # print(e) - RJPRINTERR("\n\n%s\n\n" % e) - return False - except ValueError as e: - return False - return True - - -def ipmi_set_mac(mac): - macs = mac.split(":") - cmdinit = ["ipmitool", "raw", "0x0c", "0x01", "0x01", "0xc2", "0x00"] - cmdset = ["ipmitool", "raw", "0x0c", "0x01", "0x01", "0x05"] - for ind in range(len(macs)): - cmdset.append("0x%02x" % int(macs[ind], 16)) - getstatusoutput_noshell(cmdinit) - ret, status = getstatusoutput_noshell(cmdset) - if ret: - RJPRINTERR("\n\n%s\n\n" % status) - return False - return True - - -def getInputValue(title, tips): - print("Please input[%s]such as(%s):" % (title, tips)) - name = raw_input() - - return name - - -def bmc_setmac(): - tips = "BMC MAC" - print("Please input value you want to change[%s]:" % tips) - name = raw_input() - if len(name) != 12: - RJPRINTERR("\nMAC address invaild, try again\n") - return False - release_mac = "" - for i in range(int(len(name) / 2)): - if i == 0: - release_mac += name[i * 2 : i * 2 + 2] - else: - release_mac += ":" + name[i * 2 : i * 2 + 2] - if isValidMac(release_mac) is True: - if ipmi_set_mac(release_mac) is True: - return True - else: - RJPRINTERR("\nMAC address invaild, try again\n") - return False - - -def closeProtocol(): - # disable LLDP - log_info("disable LLDP") - sys.stdout.write(".") - sys.stdout.flush() - getstatusoutput_noshell(["systemctl", "stop", "lldp.service"]) - log_info("disable lldp service") - sys.stdout.write(".") - sys.stdout.flush() - getstatusoutput_noshell(["systemctl", "stop", "bgp.service"]) - log_info("disable bgp service") - sys.stdout.write(".") - sys.stdout.flush() - # ret, status = os_system('bcmcmd "port ce,xe stp=disable"') - - -# check SDK memory must be 256M - - -def checkSdkMem(): - ind = 0 - file_data = "" - with open(file_name, "r") as f: - for line in f: - if "dmasize=16M" in line: - line = line.replace("dmasize=16M", "dmasize=256M") - ind = -1 - file_data += line - if ind == 0: - return - with open(file_name, "w") as f: - f.write(file_data) - print("change SDK memory to 256, reboot required") - getstatusoutput_noshell(["sync"]) - getstatusoutput_noshell(["reboot"]) - - -########################################################################## -# receives a character setting -########################################################################## - - -def getch(msg): - ret = "" - fd = sys.stdin.fileno() - old_ttyinfo = termios.tcgetattr(fd) - new_ttyinfo = old_ttyinfo[:] - new_ttyinfo[3] &= ~termios.ICANON - new_ttyinfo[3] &= ~termios.ECHO - sys.stdout.write(msg) - sys.stdout.flush() - try: - termios.tcsetattr(fd, termios.TCSANOW, new_ttyinfo) - ret = os.read(fd, 1) - finally: - # print "try to setting" - termios.tcsetattr(fd, termios.TCSANOW, old_ttyinfo) - return ret - - -def get_raw_input(): - ret = "" - fd = sys.stdin.fileno() - old_ttyinfo = termios.tcgetattr(fd) - new_ttyinfo = old_ttyinfo[:] - new_ttyinfo[3] &= ~termios.ICANON - new_ttyinfo[3] &= ~termios.ECHO - try: - termios.tcsetattr(fd, termios.TCSANOW, new_ttyinfo) - ret = raw_input("") - except Exception as e: - print(e) - finally: - termios.tcsetattr(fd, termios.TCSANOW, old_ttyinfo) - return ret - - -def getsysvalue(location): - retval = None - mb_reg_file = location - if not os.path.isfile(mb_reg_file): - print(mb_reg_file, "not found !") - return retval - try: - if not os.path.isfile(mb_reg_file): - print(mb_reg_file, "not found !") - return retval - with open(mb_reg_file, "r") as fd: - retval = fd.read() - except Exception as error: - log_error("Unable to open " + mb_reg_file + "file !") - retval = retval.rstrip("\r\n") - retval = retval.lstrip(" ") - # log_debug(retval) - return retval - - -# get file value - - -def get_pmc_register(reg_name): - retval = "ERR" - mb_reg_file = MAILBOX_DIR + reg_name - filepath = glob.glob(mb_reg_file) - if len(filepath) == 0: - return "%s %s notfound" % (retval, mb_reg_file) - mb_reg_file = filepath[0] - if not os.path.isfile(mb_reg_file): - return "%s %s notfound" % (retval, mb_reg_file) - try: - with open(mb_reg_file, "r") as fd: - retval = fd.read() - except Exception as error: - pass - retval = retval.rstrip("\r\n") - retval = retval.lstrip(" ") - return retval - - -# decode EEPROM - - -def decoder(s, t): - if ord(t[0]) == TLV_CODE_PRODUCT_NAME: - name = "Product Name" - value = str(t[2 : 2 + ord(t[1])]) - elif ord(t[0]) == TLV_CODE_PART_NUMBER: - name = "Part Number" - value = t[2 : 2 + ord(t[1])] - elif ord(t[0]) == TLV_CODE_SERIAL_NUMBER: - name = "Serial Number" - value = t[2 : 2 + ord(t[1])] - elif ord(t[0]) == TLV_CODE_MAC_BASE: - name = "Base MAC Address" - value = ":".join([binascii.b2a_hex(T) for T in t[2:8]]).upper() - elif ord(t[0]) == TLV_CODE_MANUF_DATE: - name = "Manufacture Date" - value = t[2 : 2 + ord(t[1])] - elif ord(t[0]) == TLV_CODE_DEVICE_VERSION: - name = "Device Version" - value = str(ord(t[2])) - elif ord(t[0]) == TLV_CODE_LABEL_REVISION: - name = "Label Revision" - value = t[2 : 2 + ord(t[1])] - elif ord(t[0]) == TLV_CODE_PLATFORM_NAME: - name = "Platform Name" - value = t[2 : 2 + ord(t[1])] - elif ord(t[0]) == TLV_CODE_ONIE_VERSION: - name = "ONIE Version" - value = t[2 : 2 + ord(t[1])] - elif ord(t[0]) == TLV_CODE_MAC_SIZE: - name = "MAC Addresses" - value = str((ord(t[2]) << 8) | ord(t[3])) - elif ord(t[0]) == TLV_CODE_MANUF_NAME: - name = "Manufacturer" - value = t[2 : 2 + ord(t[1])] - elif ord(t[0]) == TLV_CODE_MANUF_COUNTRY: - name = "Manufacture Country" - value = t[2 : 2 + ord(t[1])] - elif ord(t[0]) == TLV_CODE_VENDOR_NAME: - name = "Vendor Name" - value = t[2 : 2 + ord(t[1])] - elif ord(t[0]) == TLV_CODE_DIAG_VERSION: - name = "Diag Version" - value = t[2 : 2 + ord(t[1])] - elif ord(t[0]) == TLV_CODE_SERVICE_TAG: - name = "Service Tag" - value = t[2 : 2 + ord(t[1])] - elif ord(t[0]) == TLV_CODE_VENDOR_EXT: - name = "Vendor Extension" - value = "" - if _TLV_DISPLAY_VENDOR_EXT: - value = t[2 : 2 + ord(t[1])] - elif ord(t[0]) == TLV_CODE_CRC_32 and len(t) == 6: - name = "CRC-32" - value = "0x%08X" % ( - ((ord(t[2]) << 24) | (ord(t[3]) << 16) | (ord(t[4]) << 8) | ord(t[5])), - ) - elif ord(t[0]) == TLV_CODE_RJ_CARID: - name = "rj_cardid" - value = "" - for c in t[2 : 2 + ord(t[1])]: - value += "%02X" % (ord(c),) - else: - name = "Unknown" - value = "" - for c in t[2 : 2 + ord(t[1])]: - value += "0x%02X " % (ord(c),) - return {"name": name, "code": ord(t[0]), "value": value} - - -def decode_eeprom(e): - total_len = (ord(e[9]) << 8) | ord(e[10]) - tlv_index = _TLV_INFO_HDR_LEN - tlv_end = _TLV_INFO_HDR_LEN + total_len - ret = [] - while (tlv_index + 2) < len(e) and tlv_index < tlv_end: - rt = decoder(None, e[tlv_index : tlv_index + 2 + ord(e[tlv_index + 1])]) - ret.append(rt) - if ord(e[tlv_index]) == TLV_CODE_CRC_32: - break - tlv_index += ord(e[tlv_index + 1]) + 2 - for item in ret: - if item["code"] == TLV_CODE_VENDOR_EXT: - rt = decoder(None, item["value"][0 : 0 + 2 + ord(item["value"][0 + 1])]) - ret.append(rt) - return ret - - -def get_sys_eeprom(): - eeprom = get_sysfs_value(rg_eeprom) - return decode_eeprom(eeprom) - - -# get card ID -def getCardId(): - ret = get_sys_eeprom() - for item in ret: - if item["code"] == TLV_CODE_RJ_CARID: - return item.get("value", None) - return None - - -########################################### -# get memory slot and number via DMI command -########################################### -def getsysmeminfo(): - ret, log = getstatusoutput_noshell(["which", "dmidecode"]) - if ret != 0 or len(log) <= 0: - error = "cmd find dmidecode" - return False, error - cmd1 = [log] - cmd2 = ['grep', '-P', '-A5', "Memory\s+Device"] - cmd3 = ['grep', 'Size'] - cmd4 = ['grep', '-v', 'Range'] - # get total number first - result = [] - ret1, log1 = getstatusoutput_noshell_pipe(cmd1, cmd2, cmd3, cmd4) - if ret1 == 0 and len(log1): - log1 = log1.lstrip() - arr = log1.split("\n") - # total = len(arr) # total slot number - for i in range(len(arr)): - val = re.sub("\D", "", arr[i]) - if val == "": - val = arr[i].lstrip() - val = re.sub("Size:", "", val).lstrip() - # print val - result.append({"slot": i + 1, "size": val}) - return True, result - return False, "error" - - -########################################### -# get memory slot and number via DMI command -# return various arrays -########################################### -def getsysmeminfo_detail(): - ret, log = getstatusoutput_noshell(["which", "dmidecode"]) - if ret != 0 or len(log) <= 0: - error = "cmd find dmidecode" - return False, error - cmd1 = [log] - cmd2 = ['-t', '17'] - cmd3 = ['grep', '-A21', "Memory Device"] # 17 - cmd = ' '.join(cmd1) + ' '.join(cmd2) + ' '.join(cmd3) - # get total number - ret1, log1 = getstatusoutput_noshell_pipe(cmd1, cmd2, cmd3) - if ret1 != 0 or len(log1) <= 0: - return False, "command execution error[%s]" % cmd - result_t = log1.split("--") - mem_rets = [] - for item in result_t: - its = item.replace("\t", "").strip().split("\n") - ret = {} - for it in its: - if ":" in it: - key = it.split(":")[0].lstrip() - value = it.split(":")[1].lstrip() - ret[key] = value - mem_rets.append(ret) - return True, mem_rets - - -########################################### -# get BIOS info via DMI command -########################################### -def getDmiSysByType(type_t): - ret, log = getstatusoutput_noshell(["which", "dmidecode"]) - if ret != 0 or len(log) <= 0: - error = "cmd find dmidecode" - return False, error - cmd = [log] + ["-t", type_t] - # get total number - ret1, log1 = getstatusoutput_noshell(cmd) - if ret1 != 0 or len(log1) <= 0: - return False, "command execution error[%s]" % cmd - its = log1.replace("\t", "").strip().split("\n") - ret = {} - for it in its: - if ":" in it: - key = it.split(":")[0].lstrip() - value = it.split(":")[1].lstrip() - ret[key] = value - return True, ret - - -def gethwsys(): - return getDmiSysByType(1) - - -########################################### -# get BIOS info via DMI command - - -def getsysbios(): - return getDmiSysByType(0) - - -def searchDirByName(name, dir): - result = [] - try: - files = os.listdir(dir) - for file in files: - if name in file: - result.append(os.path.join(dir, file)) - except Exception as e: - pass - return result - - -def getUsbLocation(): - dir = "/sys/block/" - spect = "sd" - usbpath = "" - result = searchDirByName(spect, dir) - if len(result) <= 0: - return False - for item in result: - with open(os.path.join(item, "removable"), "r") as fd: - value = fd.read() - if value.strip() == "1": # U-Disk found - usbpath = item - break - if usbpath == "": # no U-Disk found - log_debug("no usb found") - return False, usbpath - return True, usbpath - - -# judge USB file -def getusbinfo(): - ret, path = getUsbLocation() - if ret is False: - return False, "not usb exists" - str = os.path.join(path, "size") - ret, value = getfilevalue(str) - if ret is True: - return ( - True, - { - "id": os.path.basename(path), - "size": float(value) * 512 / 1024 / 1024 / 1024, - }, - ) - else: - return False, "Err" - - -def get_cpu_info(): - cmd1 = ["cat", "/proc/cpuinfo"] - cmd2 = ["grep", "processor", "-A18"] # 17 - cmd = ' '.join(cmd1) + ' '.join(cmd2) - ret, log1 = getstatusoutput_noshell_pipe(cmd1, cmd2) - if ret != 0 or len(log1) <= 0: - return False, "command execution error[%s]" % cmd - result_t = log1.split("--") - mem_rets = [] - for item in result_t: - its = item.replace("\t", "").strip().split("\n") - ret = {} - for it in its: - if ":" in it: - key = it.split(":")[0].lstrip() - value = it.split(":")[1].lstrip() - ret[key] = value - mem_rets.append(ret) - return True, mem_rets - - -# read file -def get_version_config_info(attr_key, file_name=None): - if file_name is None: - version_conf_filename = "/root/version.json" - else: - version_conf_filename = file_name - if not os.path.isfile(version_conf_filename): - return None - with open(version_conf_filename) as rjconf_file: - for line in rjconf_file: - tokens = line.split("=") - if len(tokens) < 2: - continue - if tokens[0] == attr_key: - return tokens[1].strip() - return None - - -def io_rd(reg_addr, size=1): - path = "/dev/port" - ret = "" - fd = None - try: - reg_addr = int(reg_addr) - fd = os.open(path, os.O_RDWR|os.O_CREAT) - for i in range(size): - os.lseek(fd, reg_addr+i, os.SEEK_SET) - ret+="{:02x}".format(ord(os.read(fd, 1).decode('latin-1'))) - return ret - except Exception as e: - print(str(e)) - return None - finally: - if fd: os.close(fd) - - -def io_wr(reg_addr, reg_data): - u"""io write""" - fd = None - try: - regdata = 0 - regaddr = 0 - if type(reg_addr) == int: - regaddr = reg_addr - else: - regaddr = int(reg_addr, 16) - if type(reg_data) == int: - regdata = reg_data - else: - regdata = int(reg_data, 16) - devfile = "/dev/port" - fd = os.open(devfile, os.O_RDWR | os.O_CREAT) - os.lseek(fd, regaddr, os.SEEK_SET) - os.write(fd, regdata.to_bytes(2, 'little')) - return True - except ValueError as e: - print(e) - return False - except Exception as e: - print(e) - return False - finally: - if fd: os.close(fd) diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/script/reboot_cause.py b/platform/broadcom/sonic-platform-modules-ragile/common/script/reboot_cause.py new file mode 100755 index 000000000000..2f125c5084c2 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/script/reboot_cause.py @@ -0,0 +1,183 @@ +#!/usr/bin/python3 +# -*- coding: UTF-8 -*- +import sys +import os +import time +import syslog +from platform_util import get_value, set_value, exec_os_cmd, wb_os_system +from platform_config import REBOOT_CAUSE_PARA + +REBOOT_CAUSE_DEBUG_FILE = "/etc/.reboot_cause_debug" +REBOOT_CAUSE_STARTED_FLAG = "/tmp/.reboot_cause_started_flag" + +debuglevel = 0 + + +def record_syslog_debug(s): + if debuglevel: + syslog.openlog("REBOOT_CAUSE_DEBUG", syslog.LOG_PID) + syslog.syslog(syslog.LOG_DEBUG, s) + + +def record_syslog(s): + syslog.openlog("REBOOT_CAUSE", syslog.LOG_PID) + syslog.syslog(syslog.LOG_WARNING, s) + + +class RebootCause(): + def __init__(self): + self.reboot_cause_para = REBOOT_CAUSE_PARA.copy() + self.reboot_cause_list = self.reboot_cause_para.get('reboot_cause_list', None) + self.other_reboot_cause_record = self.reboot_cause_para.get('other_reboot_cause_record', None) + + def debug_init(self): + global debuglevel + if os.path.exists(REBOOT_CAUSE_DEBUG_FILE): + debuglevel = 1 + else: + debuglevel = 0 + + def monitor_point_check(self, item): + try: + gettype = item.get('gettype', None) + okval = item.get('okval', None) + compare_mode = item.get('compare_mode', "equal") + ret, value = get_value(item) + if ret is True: + if compare_mode == "equal": + if value == okval: + return True + elif compare_mode == "great": + if value > okval: + return True + elif compare_mode == "ignore": + return True + else: + record_syslog('%%REBOOT_CAUSE-3-EXCEPTION: compare_mode %s not match error.' % (compare_mode)) + else: + record_syslog('%%REBOOT_CAUSE-3-EXCEPTION: base point check type:%s not support.' % gettype) + except Exception as e: + record_syslog('%%REBOOT_CAUSE-3-EXCEPTION: base point check error. msg: %s.' % (str(e))) + return False + + def reboot_cause_record(self, item_list): + RET = {"RETURN_KEY1": 0} + try: + for item in item_list: + record_type = item.get('record_type', None) + if record_type == 'file': + file_mode = item.get('mode', None) + file_log = item.get('log', None) + file_path = item.get('path', None) + file_max_size = item.get('file_max_size', 0) + + if file_path is None: + record_syslog('%%REBOOT_CAUSE-3-EXCEPTION: record type is file, but path is none.') + continue + + if file_max_size > 0: + file_size = 0 + if os.path.exists(file_path): + file_size = os.path.getsize(file_path) // file_max_size + if file_size >= 1: + reocrd_cmd = "mv %s %s_bak" % (file_path, file_path) + status, output = exec_os_cmd(reocrd_cmd) + if status: + record_syslog( + '%%REBOOT_CAUSE-3-EXCEPTION: exec cmd %s failed, %s' % + (reocrd_cmd, output)) + + if file_mode == 'cover': + operate_cmd = ">" + elif file_mode == 'add': + operate_cmd = ">>" + else: + RET["RETURN_KEY1"] = -1 + record_syslog('%%REBOOT_CAUSE-3-EXCEPTION: file record mode:%s not support.' % file_mode) + continue + + create_dir = "mkdir -p %s" % os.path.dirname(file_path) + status, ret_t = wb_os_system(create_dir) + if status != 0: + RET["RETURN_KEY1"] = -1 + record_syslog( + '%%REBOOT_CAUSE-3-EXCEPTION: create %s failed, msg: %s' % + (os.path.dirname(file_path), ret_t)) + continue + + status, date = wb_os_system("date") + if status != 0 or len(date) == 0: + RET["RETURN_KEY1"] = -1 + record_syslog('%%REBOOT_CAUSE-3-EXCEPTION: get date failed.') + continue + + reocrd_cmd = "echo %s %s %s %s" % (file_log, date, operate_cmd, file_path) + status, ret_t = wb_os_system(reocrd_cmd) + if status != 0: + RET["RETURN_KEY1"] = -1 + record_syslog('%%REBOOT_CAUSE-3-EXCEPTION: get date failed, msg: %s' % ret_t) + continue + wb_os_system('sync') + else: + RET["RETURN_KEY1"] = -1 + record_syslog('%%REBOOT_CAUSE-3-EXCEPTION: record_type:%s not support.' % record_type) + continue + except Exception as e: + RET["RETURN_KEY1"] = -1 + record_syslog('%%REBOOT_CAUSE-3-EXCEPTION: reboot cause record error. msg: %s.' % (str(e))) + if RET["RETURN_KEY1"] == 0: + return True + return False + + def reboot_cause_check(self): + try: + reboot_cause_flag = False + if self.reboot_cause_list is None: + record_syslog_debug('%%REBOOT_CAUSE-6-DEBUG: reboot cause check config not found') + return + for item in self.reboot_cause_list: + name = item.get('name', None) + monitor_point = item.get('monitor_point', None) + record = item.get('record', None) + finish_operation_list = item.get('finish_operation', []) + if name is None or monitor_point is None or record is None: + record_syslog('%%REBOOT_CAUSE-3-EXCEPTION: reboot cause check get config failed.name:%s, monitor_point:%s, record:%s' % + (name, monitor_point, record)) + return + ret = self.monitor_point_check(monitor_point) + if ret is True: + record_syslog_debug('%%REBOOT_CAUSE-6-DEBUG: %s reboot cause is happen' % name) + self.reboot_cause_record(record) + reboot_cause_flag = True + for finish_operation_item in finish_operation_list: + ret, log = set_value(finish_operation_item) + if ret is False: + log = "%%REBOOT_CAUSE-3-EXCEPTION: " + log + record_syslog(log) + + if reboot_cause_flag is False and self.other_reboot_cause_record is not None: + record_syslog_debug('%%REBOOT_CAUSE-6-DEBUG: other reboot cause is happen') + self.reboot_cause_record(self.other_reboot_cause_record) + except Exception as e: + record_syslog('%%REBOOT_CAUSE-3-EXCEPTION: reboot cause check error. msg: %s.' % (str(e))) + return + + def run(self): + try: + self.debug_init() + if os.path.exists(REBOOT_CAUSE_STARTED_FLAG): + record_syslog_debug( + '%%REBOOT_CAUSE-6-DEBUG: Reboot cause has been started and will not be started again') + sys.exit(0) + self.reboot_cause_check() + wb_os_system("touch %s" % REBOOT_CAUSE_STARTED_FLAG) + wb_os_system("sync") + time.sleep(5) + sys.exit(0) + except Exception as e: + record_syslog('%%REBOOT_CAUSE-3-EXCEPTION: %s.' % (str(e))) + + +if __name__ == '__main__': + reboot_cause = RebootCause() + reboot_cause.run() diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/script/reboot_ctrl.py b/platform/broadcom/sonic-platform-modules-ragile/common/script/reboot_ctrl.py new file mode 100755 index 000000000000..17d3f5902b9d --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/script/reboot_ctrl.py @@ -0,0 +1,150 @@ +#!/usr/bin/env python3 +# -*- coding: UTF-8 -*- +import time +import syslog +import click +from platform_util import write_sysfs, wbi2cset, io_wr, wbi2csetWord +from platform_config import REBOOT_CTRL_PARAM + + +REBOOTCTLDEBUG = 0 + +CONTEXT_SETTINGS = {"help_option_names": ['-h', '--help']} + + +class AliasedGroup(click.Group): + def get_command(self, ctx, cmd_name): + rv = click.Group.get_command(self, ctx, cmd_name) + if rv is not None: + return rv + matches = [x for x in self.list_commands(ctx) + if x.startswith(cmd_name)] + if not matches: + return None + if len(matches) == 1: + return click.Group.get_command(self, ctx, matches[0]) + ctx.fail('Too many matches: %s' % ', '.join(sorted(matches))) + return None + + +def rebootctrlwarning(s): + # s = s.decode('utf-8').encode('gb2312') + syslog.openlog("REBOOTCTRL", syslog.LOG_PID) + syslog.syslog(syslog.LOG_WARNING, s) + + +def rebootctrlcritical(s): + # s = s.decode('utf-8').encode('gb2312') + syslog.openlog("REBOOTCTRL", syslog.LOG_PID) + syslog.syslog(syslog.LOG_CRIT, s) + + +def rebootctrlerror(s): + # s = s.decode('utf-8').encode('gb2312') + syslog.openlog("REBOOTCTRL", syslog.LOG_PID) + syslog.syslog(syslog.LOG_ERR, s) + + +def rebootctrldebug(s): + # s = s.decode('utf-8').encode('gb2312') + if REBOOTCTLDEBUG == 1: + syslog.openlog("REBOOTCTRL", syslog.LOG_PID) + syslog.syslog(syslog.LOG_DEBUG, s) + + +class RebootCtrl(): + def __init__(self): + self.config = REBOOT_CTRL_PARAM.copy() + + def set_value(self, config, val): + way = config.get("gettype") + if way == 'sysfs': + loc = config.get("loc") + value = config.get(val) + rebootctrldebug("sysfs type.loc:0x%x, value:0x%x" % (loc, value)) + return write_sysfs(loc, "0x%02x" % value) + if way == "i2c": + bus = config.get("bus") + addr = config.get("loc") + offset = config.get("offset") + value = config.get(val) + rebootctrldebug("i2c type.bus:0x%x, addr:0x%x, offset:0x%x, value:0x%x" % (bus, addr, offset, value)) + return wbi2cset(bus, addr, offset, value) + if way == "io": + io_addr = config.get('io_addr') + value = config.get(val) + rebootctrldebug("io type.io_addr:0x%x, value:0x%x" % (io_addr, value)) + ret = io_wr(io_addr, value) + if ret is not True: + return False, ("write 0x%x failed" % io_addr) + return True, ("write 0x%x success" % io_addr) + if way == 'i2cword': + bus = config.get("bus") + addr = config.get("loc") + offset = config.get("offset") + value = config.get(val) + rebootctrldebug("i2cword type.bus:0x%x, addr:0x%x, offset:0x%x, value:0x%x" % (bus, addr, offset, value)) + return wbi2csetWord(bus, addr, offset, value) + return False, "unsupport way: %s" % way + + def reset_operate(self, config): + ret, log = self.set_value(config, "rst_val") + rst_delay = config.get("rst_delay", 0) + time.sleep(rst_delay) + return ret, log + + def unlock_reset_operate(self, config): + ret, log = self.set_value(config, "unlock_rst_val") + unlock_rst_delay = config.get("unlock_rst_delay", 0) + time.sleep(unlock_rst_delay) + return ret, log + + def do_rebootctrl(self, option): + if self.config is None: + rebootctrlerror("Reset failed, REBOOT_CTRL_PARAM cfg get failed.") + return + try: + name_conf = self.config.get(option, None) + if name_conf is None: + print("Reset %s not support" % option) + return + try: + click.confirm("Are you sure you want to reset " + option + "?", + default=False, abort=True, show_default=True) + except Exception as e: + print("Aborted, msg: %s" % str(e)) + return + print("Reset %s start" % option) + ret, log = self.reset_operate(name_conf) + if ret is False: + rebootctrlerror(log) + print("Reset %s failed" % option) + return + if "unlock_rst_val" in name_conf: + ret, log = self.unlock_reset_operate(name_conf) + if ret is False: + rebootctrlerror(log) + print("%s unlock reset failed" % option) + return + print("Reset %s success" % option) + except Exception: + rebootctrlerror("do_rebootctrl Exception error") + return + + +@click.group(cls=AliasedGroup, context_settings=CONTEXT_SETTINGS) +def main(): + '''reboot_ctrl reset [option]''' + + +@main.command() +@click.argument('option', required=True) +def reset(option): + '''reset device''' + rebootctrldebug("reboot ctrl option %s" % option) + rebootctrl = RebootCtrl() + rebootctrl.do_rebootctrl(option) + + +if __name__ == '__main__': + main() diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/script/sensors b/platform/broadcom/sonic-platform-modules-ragile/common/script/sensors new file mode 100755 index 000000000000..a2c72b123a43 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/script/sensors @@ -0,0 +1,8 @@ +#!/bin/bash +#docker exec -i pmon sensors "$@" + + +#To probe sensors not part of lm-sensors +if [ -r /usr/local/bin/platform_sensors.py ]; then + python /usr/local/bin/platform_sensors.py +fi diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/script/sfp_highest_temperatue.py b/platform/broadcom/sonic-platform-modules-ragile/common/script/sfp_highest_temperatue.py new file mode 100755 index 000000000000..4dd98f3a36b3 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/script/sfp_highest_temperatue.py @@ -0,0 +1,148 @@ +#!/usr/bin/python3 +import os +import importlib.machinery +import time +import syslog +import subprocess +import fcntl + +sfp_temperature_file = "/tmp/highest_sff_temp" + +SFP_TEMP_DEBUG_FILE = "/etc/.sfp_temp_debug_flag" +SFP_TEMP_RECORD_DEBUG = 1 +SFP_TEMP_RECORD_ERROR = 2 +debuglevel = 0 + + +def sfp_temp_debug(s): + if SFP_TEMP_RECORD_DEBUG & debuglevel: + syslog.openlog("SFP_TEMP_DEBUG", syslog.LOG_PID) + syslog.syslog(syslog.LOG_DEBUG, s) + + +def sfp_temp_error(s): + if SFP_TEMP_RECORD_ERROR & debuglevel: + syslog.openlog("SFP_TEMP_ERROR", syslog.LOG_PID) + syslog.syslog(syslog.LOG_ERR, s) + + +pidfile = None + + +def file_rw_lock(): + global pidfile + pidfile = open(sfp_temperature_file, "r") + try: + fcntl.flock(pidfile, fcntl.LOCK_EX | fcntl.LOCK_NB) + sfp_temp_debug("file lock success") + return True + except Exception: + if pidfile is not None: + pidfile.close() + pidfile = None + return False + + +def file_rw_unlock(): + try: + global pidfile + + if pidfile is not None: + fcntl.flock(pidfile, fcntl.LOCK_UN) + pidfile.close() + pidfile = None + sfp_temp_debug("file unlock success") + else: + sfp_temp_debug("pidfile is invalid, do nothing") + return True + except Exception as e: + sfp_temp_error("file unlock err, msg:%s" % (str(e))) + return False + + +def get_sfp_highest_temperature(): + highest_temperature = 0 + platform_sfputil = None + + sfputil_dir = "/usr/share/sonic/device/" + try: + if not os.path.exists(sfputil_dir): + sfputil_dir = "/usr/share/sonic/platform/" + sfputil_path = sfputil_dir + "/plugins/sfputil.py" + else: + cmd = "cat /host/machine.conf | grep onie_build_platform" + ret, output = subprocess.getstatusoutput(cmd) + if ret != 0: + sfp_temp_error("cmd: %s execution fail, output: %s" % (cmd, output)) + + onie_platform = output.split("=")[1] + sfputil_path = sfputil_dir + onie_platform + "/plugins/sfputil.py" + + module = importlib.machinery.SourceFileLoader("sfputil", sfputil_path).load_module() + platform_sfputil_class = getattr(module, "SfpUtil") + platform_sfputil = platform_sfputil_class() + + temperature = platform_sfputil.get_highest_temperature() + highest_temperature = int(temperature) * 1000 + except Exception as e: + sfp_temp_error("get sfp temperature error, msg:%s" % str(e)) + highest_temperature = -9999000 + + return highest_temperature + + +def write_sfp_highest_temperature(temperature): + + loop = 1000 + ret = False + try: + if os.path.exists(sfp_temperature_file) is False: + with open(sfp_temperature_file, 'w') as sfp_f: + pass + for i in range(0, loop): + ret = file_rw_lock() + if ret is True: + break + time.sleep(0.001) + + if ret is False: + sfp_temp_error("take file lock timeout") + return + + with open(sfp_temperature_file, 'w') as sfp_f: + sfp_f.write("%s\n" % str(temperature)) + + file_rw_unlock() + return + except Exception as e: + sfp_temp_error("write sfp temperature error, msg:%s" % str(e)) + file_rw_unlock() + return + + +def debug_init(): + global debuglevel + + try: + with open(SFP_TEMP_DEBUG_FILE, "r") as fd: + value = fd.read() + debuglevel = int(value) + except Exception: + debuglevel = 0 + + +def main(): + while True: + debug_init() + temperature = 0 + try: + temperature = get_sfp_highest_temperature() + write_sfp_highest_temperature(temperature) + except Exception as e: + sfp_temp_error("get/write sfp temperature error, msg:%s" % str(e)) + write_sfp_highest_temperature(-9999000) + time.sleep(5) + + +if __name__ == '__main__': + main() diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/script/slot_monitor.py b/platform/broadcom/sonic-platform-modules-ragile/common/script/slot_monitor.py new file mode 100755 index 000000000000..b8b774c8b726 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/script/slot_monitor.py @@ -0,0 +1,242 @@ +#!/usr/bin/env python3 +# -*- coding: UTF-8 -*- +import time +import syslog +import traceback +import operator +import click +from platform_config import SLOT_MONITOR_PARAM, MONITOR_DEV_STATUS_DECODE +from platform_util import io_rd, io_wr, wbi2cget, wbi2cset + + +SLOTMONITORDEBUG = 0 + +CONTEXT_SETTINGS = {"help_option_names": ['-h', '--help']} + + +class AliasedGroup(click.Group): + def get_command(self, ctx, cmd_name): + rv = click.Group.get_command(self, ctx, cmd_name) + if rv is not None: + return rv + matches = [x for x in self.list_commands(ctx) + if x.startswith(cmd_name)] + if not matches: + return None + if len(matches) == 1: + return click.Group.get_command(self, ctx, matches[0]) + ctx.fail('Too many matches: %s' % ', '.join(sorted(matches))) + return None + + +def slotwarninglog(s): + # s = s.decode('utf-8').encode('gb2312') + syslog.openlog("SLOTMONITOR", syslog.LOG_PID) + syslog.syslog(syslog.LOG_WARNING, s) + + +def slotcriticallog(s): + # s = s.decode('utf-8').encode('gb2312') + syslog.openlog("SLOTMONITOR", syslog.LOG_PID) + syslog.syslog(syslog.LOG_CRIT, s) + + +def sloterror(s): + # s = s.decode('utf-8').encode('gb2312') + syslog.openlog("SLOTMONITOR", syslog.LOG_PID) + syslog.syslog(syslog.LOG_ERR, s) + + +def slotinfo(s): + # s = s.decode('utf-8').encode('gb2312') + syslog.openlog("SLOTMONITOR", syslog.LOG_PID) + syslog.syslog(syslog.LOG_INFO, s) + + +def slotdebuglog(s): + # s = s.decode('utf-8').encode('gb2312') + if SLOTMONITORDEBUG == 1: + syslog.openlog("SLOTMONITOR", syslog.LOG_PID) + syslog.syslog(syslog.LOG_DEBUG, s) + + +class SlotMonitor(): + def __init__(self): + self.preSlotStatus = [] + + def checkslot(self, ret): + slots_conf = SLOT_MONITOR_PARAM.get('slots', None) + slotpresent = MONITOR_DEV_STATUS_DECODE.get('slotpresent', None) + + if slots_conf is None or slotpresent is None: + return False + for item_slot in slots_conf: + totalerr = 0 + try: + ret_t = {} + ret_t["id"] = item_slot.get('name') + ret_t["status"] = "" + presentattr = item_slot.get('present') + gettype = presentattr.get('gettype') + presentbit = presentattr.get('presentbit') + if gettype == "io": + io_addr = presentattr.get('io_addr') + val = io_rd(io_addr) + if val is not None: + retval = val + else: + totalerr -= 1 + sloterror(" %s %s" % (item_slot.get('name'), "lpc read failed")) + else: + bus = presentattr.get('bus') + loc = presentattr.get('loc') + offset = presentattr.get('offset') + ind, val = wbi2cget(bus, loc, offset) + if ind is True: + retval = val + else: + totalerr -= 1 + sloterror(" %s %s" % (item_slot.get('name'), "i2c read failed")) + if totalerr < 0: + ret_t["status"] = "NOT OK" + ret.append(ret_t) + continue + val_t = (int(retval, 16) & (1 << presentbit)) >> presentbit + slotdebuglog("%s present:%s" % (item_slot.get('name'), slotpresent.get(val_t))) + if val_t != slotpresent.get('okval'): + ret_t["status"] = "ABSENT" + else: + ret_t["status"] = "PRESENT" + except Exception as e: + ret_t["status"] = "NOT OK" + totalerr -= 1 + sloterror("checkslot error") + sloterror(str(e)) + ret.append(ret_t) + return True + + def dealslotplugin(self, name): + slotdebuglog("enter dealslotplugin %s" % name) + # wait for slot stable + time.sleep(5) + slots_conf = SLOT_MONITOR_PARAM.get('slots', None) + if slots_conf is None: + return False + for item_slot in slots_conf: + try: + slotdebuglog("name %s, item_slot.get('name') %s" % (name, item_slot.get('name'))) + if name == item_slot.get('name'): + actattr = item_slot.get('act') + for item_act in actattr: + gettype = item_act.get('gettype') + if gettype == "io": + io_addr = item_act.get('io_addr') + value = item_act.get('value') + mask = item_act.get('mask') + val = io_rd(io_addr) + if val is None: + sloterror(" %s %s" % (name, "lpc read failed")) + continue + set_val = (int(val, 16) & mask) | value + ret = io_wr(io_addr, set_val) + if ret is not True: + sloterror(" %s %s" % (name, "lpc write failed")) + continue + slotdebuglog("io set io_addr:0x%x value:0x%x success" % (io_addr, set_val)) + elif gettype == "i2c": + bus = item_act.get('bus') + loc = item_act.get('loc') + offset = item_act.get('offset') + value = item_act.get('value') + ret, log = wbi2cset(bus, loc, offset, value) + if ret is not True: + sloterror(" %s %s %s" % (name, "i2c write failed", log)) + continue + slotdebuglog( + "i2c set bus:%d loc:0x%x offset:0x%x value:0x%x success" % + (bus, loc, offset, value)) + else: + sloterror("gettype error") + break + except Exception as e: + sloterror("dealslotplugin failed") + sloterror(str(e)) + return False + return True + + def updateSlotStatus(self): + ''' + Only two status: PRESENT and ABSENT + ''' + curSlotStatus = [] + self.checkslot(curSlotStatus) + slotdebuglog('curSlotStatus: {}\n preSlotStatus: {}'.format(curSlotStatus, self.preSlotStatus)) + if operator.eq(self.preSlotStatus, curSlotStatus) is False: + if len(self.preSlotStatus) == 0: + # first time + for i, item in enumerate(curSlotStatus): + if item['status'] == 'PRESENT': + slotdebuglog('SLOT_PLUG_IN: %s' % (item['id'])) + elif item['status'] == 'ABSENT': + slotdebuglog('SLOT_ABSENT: %s' % (item['id'])) + else: + slotdebuglog('SLOT_FAILED: %s status %s not support yet' % (item['id'], item['status'])) + self.preSlotStatus.append(item) + else: + for i, item in enumerate(curSlotStatus): + if item['status'] == self.preSlotStatus[i]['status']: + continue + if item['status'] == 'PRESENT' and self.preSlotStatus[i]['status'] == 'ABSENT': + self.dealslotplugin(item['id']) + slotinfo('SLOT_PLUG_IN: %s' % (item['id'])) + elif item['status'] == 'ABSENT' and self.preSlotStatus[i]['status'] == 'PRESENT': + slotwarninglog('SLOT_PLUG_OUT: %s' % (item['id'])) + else: + slotwarninglog('SLOT_PLUG_OUT: %s status change from %s to %s not support' % + (item['id'], self.preSlotStatus[i]['status'], item['status'])) + self.preSlotStatus.remove(self.preSlotStatus[i]) + self.preSlotStatus.insert(i, item) + + def slotmonitor(self): + self.updateSlotStatus() + return 0 + + +def doSlotMonitor(slotMonitor): + slotMonitor.slotmonitor() + + +def run(interval, slotMonitor): + # slotMonitor.devattrinit() + while True: + try: + doSlotMonitor(slotMonitor) + except Exception as e: + traceback.print_exc() + sloterror(str(e)) + time.sleep(interval) + + +@click.group(cls=AliasedGroup, context_settings=CONTEXT_SETTINGS) +def main(): + '''slot monitor operator''' + + +@main.command() +def start(): + '''start slot monitor''' + slotinfo("slot_monitor start") + slotMonitor = SlotMonitor() + interval = SLOT_MONITOR_PARAM.get('polling_time', 1) + run(interval, slotMonitor) + + +@main.command() +def stop(): + '''stop slot monitor ''' + slotinfo("stop") + + +# device_i2c operation +if __name__ == '__main__': + main() diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/script/ssdmon b/platform/broadcom/sonic-platform-modules-ragile/common/script/ssdmon new file mode 100755 index 000000000000..4290b0a68725 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/script/ssdmon @@ -0,0 +1,82 @@ +#!/usr/bin/env python3 +# +# ssdmon +# +# Command-line utility to check SSD health and parameters +# + +try: + import argparse + import os + import sys + + from sonic_py_common import device_info, logger +except ImportError as e: + raise ImportError("%s - required module not found" % str(e)) + +DEFAULT_DEVICE = "/dev/sda" +SYSLOG_IDENTIFIER = "ssdmon" + +# Global logger instance +log = logger.Logger(SYSLOG_IDENTIFIER) + +def import_ssd_api(diskdev): + """ + Loads platform specific or generic ssd_mon module from source + Raises an ImportError exception if none of above available + + Returns: + Instance of the class with SSD API implementation (vendor or generic) + """ + + # try to load platform specific module + try: + platform_path, _ = device_info.get_paths_to_platform_and_hwsku_dirs() + platform_plugins_path = os.path.join(platform_path, "plugins") + sys.path.append(os.path.abspath(platform_plugins_path)) + from ssd_util import SsdUtil + except ImportError as e: + log.log_warning("Platform specific SsdMon module not found.") + + return SsdUtil(diskdev) + +def is_number(s): + try: + float(s) + return True + except ValueError: + return False + +# ==================== Entry point ==================== +def ssdmon(): + if os.geteuid() != 0: + print("Root privileges are required for this operation") + sys.exit(1) + + parser = argparse.ArgumentParser() + parser.add_argument("-d", "--device", help="Device name to show health info", default=DEFAULT_DEVICE) + parser.add_argument("-t", "--temperature", action="store_true", default=False, help="Show only temperature") + parser.add_argument("-j", "--health", action="store_true", default=False, help="Show only health") + + args = parser.parse_args() + + ssd = import_ssd_api(args.device) + + if args.temperature: + print(ssd.get_temperature()) + return + + if args.health: + print(ssd.get_health()) + return + + print("Device Model : {}".format(ssd.get_model())) + print("Firmware : {}".format(ssd.get_firmware())) + print("Serial : {}".format(ssd.get_serial())) + print("Health : {}{}".format(ssd.get_health(), "%" if is_number(ssd.get_health()) else "")) + print("Remain Life : {}{}".format(ssd.get_remaining_life(), "%" if is_number(ssd.get_remaining_life()) else "")) + print("Temperature : {}{}".format(ssd.get_temperature(), "C" if is_number(ssd.get_temperature()) else "")) + print("SATA Rate : {}".format(ssd.get_sata_rate())) + +if __name__ == '__main__': + ssdmon() diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/script/tty_console.py b/platform/broadcom/sonic-platform-modules-ragile/common/script/tty_console.py new file mode 100755 index 000000000000..4fae02f5128e --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/script/tty_console.py @@ -0,0 +1,91 @@ +#!/usr/bin/python3 +# -*- coding: UTF-8 -*- + +import logging.handlers +import subprocess +import shlex +import time +import sys +import os +from platform_util import CompressedRotatingFileHandler, exec_os_cmd + +console_file = "/dev/ttyS1" +console_logfile = "/var/log/bmc-console.log" +MAX_LOG_BYTES = 20 * 1024 * 1024 +BACKUP_COUNT = 9 + +READ_SIZE = 1024 + +logger = logging.getLogger("cpu_monitor_bmc") +logger.setLevel(logging.DEBUG) +fh = CompressedRotatingFileHandler( + console_logfile, + mode='a', + maxBytes=MAX_LOG_BYTES, + backupCount=BACKUP_COUNT, + encoding=None, + delay=0) +fh.setLevel(logging.DEBUG) + +formatter = logging.Formatter("%(asctime)s - %(levelname)s - %(message)s") +fh.setFormatter(formatter) +logger.addHandler(fh) + + +def tty_system_cmd(cmd, print_log=True): + if print_log: + logger.debug("command: %s", cmd) + status, output = exec_os_cmd(cmd) + logger.debug("command status %s", status) + logger.debug("command output:\n%s", output) + else: + status, output = exec_os_cmd(cmd) + return status, output + + +if __name__ == '__main__': + try_times = 0 + while try_times < 3: + try_times = try_times + 1 + ret, log = tty_system_cmd("stty -F /dev/ttyS1 | grep 115200", True) + if len(log) != 0 and "115200" in log: + break + tty_system_cmd("stty -F /dev/ttyS1 115200", True) + if try_times > 1: + logger.error("The %d time try to set SONiC /dev/ttyS1 115200", try_times) + + if not os.path.exists(console_file): + logger.error("device %s not exist", console_file) + sys.exit(1) + + nopen = 3 + while nopen > 0: + try: + console_fd = os.open(console_file, os.O_RDONLY) + break + except Exception as e: + logger.error(e) + logger.error("open %s failed", console_file) + nopen = nopen - 1 + time.sleep(1) + if nopen == 0: + sys.exit(1) + + try: + tmp_read = "" + while True: + dev_read = os.read(console_fd, READ_SIZE) + dev_read = str(dev_read, encoding='utf-8') + if len(dev_read) == 1 and dev_read == "\n": + continue + if dev_read[len(dev_read) - 1] == '\n': + tmp_read = tmp_read + dev_read[0:(len(dev_read) - 1)] + logger.info(tmp_read) + tmp_read = "" + else: + tmp_read = tmp_read + dev_read + + except Exception as e: + if console_fd is not None: + os.close(console_fd) + logger.error(e) diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/script/upgrade.py b/platform/broadcom/sonic-platform-modules-ragile/common/script/upgrade.py new file mode 100755 index 000000000000..f56712e471b6 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/script/upgrade.py @@ -0,0 +1,991 @@ +#!/usr/bin/env python3 +# -*- coding: UTF-8 -*- +import sys +import os +import time +import syslog +import signal +import click +from platform_util import get_value, set_value, exec_os_cmd, exec_os_cmd_log +from platform_config import UPGRADE_SUMMARY, WARM_UPGRADE_STARTED_FLAG +from warm_upgrade import WarmBasePlatform + + +############################# Error code defined ############################# +ERR_FW_CHECK_CPLD_UPGRADE = -601 # "Failed to check the device CPLD information" +ERR_FW_CHECK_FPGA_UPGRADE = -602 # "Failed to check the device FPGA information" +ERR_FW_MATCH_CPLD_UPGRADE = -603 # "Not found upgrade CPLD file." +ERR_FW_MATCH_FPGA_UPGRADE = -604 # "Not found upgrade FPGA file." +ERR_FW_SAMEVER_CPLD_UPGRADE = -605 # "The CPLD version in device is same" +ERR_FW_SAMEVER_FPGA_UPGRADE = -606 # "The FPGA version in device is same" +ERR_FW_DO_CPLD_UPGRADE = -607 # "Doing upgrade CPLD is failed." +ERR_FW_DO_FPGA_UPGRADE = -608 # "Doing upgrade FPGA is failed." +ERR_FW_UPGRADE = -609 # "Failed to upgrade firmware" +FIRMWARE_PROGRAM_EXEC_ERR = -610 # "Firmware program run error!" +ERR_FW_FILE_FOUND = -701 # "Failed to find upgrade file" +ERR_FW_HEAD_PARSE = -702 # "Failed to parse upgrade firmware head info" +ERR_FW_CONFIG_FOUND = -703 # "Failed to find config item" +ERR_FW_NOSUPPORT_HOT = -704 # "No support hot upgrade" +ERR_FW_CHECK_SIZE = -705 # "Failed to check file size" +ERR_FW_DEVICE_ACCESS = -706 # "Failed to access device" +ERR_FW_NO_FILE_SUCCESS = -707 # "No files were successfully upgraded" +ERR_FW_CARD_ABSENT = -708 # "The subcard not present" +ERR_FW_HEAD_CHECK = -709 # "Failed to check head info" +ERR_FW_FOOL_PROOF = -710 # "Failed to fool proof verification" +ERR_FW_RAISE_EXCEPTION = -711 # Code raise exception +ERR_FW_INVALID_PARAM = -712 # Invalid parameter +ERR_FW_UNZIP_FAILED = -713 # Unzip firmware failed + +FIRMWARE_SUCCESS = 0 +CHECK_OK = 0 + + +UPGRADE_DEBUG_FILE = "/etc/.upgrade_debug_flag" +UPGRADE_FILE_DIR = "/tmp/firmware/" + +UPGRADEDEBUG = 1 + +debuglevel = 0 + +COLD_UPGRADE = 1 +WARM_UPGRADE = 2 +TEST_UPGRADE = 3 +BMC_UPGRADE = 4 + +CONTEXT_SETTINGS = {"help_option_names": ['-h', '--help']} + + +class AliasedGroup(click.Group): + + def get_command(self, ctx, cmd_name): + rv = click.Group.get_command(self, ctx, cmd_name) + if rv is not None: + return rv + matches = [x for x in self.list_commands(ctx) + if x.startswith(cmd_name)] + if not matches: + return None + if len(matches) == 1: + return click.Group.get_command(self, ctx, matches[0]) + ctx.fail('Too many matches: %s' % ', '.join(sorted(matches))) + return None + + +def debug_init(): + global debuglevel + if os.path.exists(UPGRADE_DEBUG_FILE): + debuglevel = debuglevel | UPGRADEDEBUG + else: + debuglevel = debuglevel & ~(UPGRADEDEBUG) + + +def upgradewarninglog(s): + # s = s.decode('utf-8').encode('gb2312') + syslog.openlog("UPGRADE", syslog.LOG_PID) + syslog.syslog(syslog.LOG_WARNING, s) + + +def upgradecriticallog(s): + # s = s.decode('utf-8').encode('gb2312') + syslog.openlog("UPGRADE", syslog.LOG_PID) + syslog.syslog(syslog.LOG_CRIT, s) + + +def upgradeerror(s): + # s = s.decode('utf-8').encode('gb2312') + syslog.openlog("UPGRADE", syslog.LOG_PID) + syslog.syslog(syslog.LOG_ERR, s) + + +def upgradedebuglog(s): + # s = s.decode('utf-8').encode('gb2312') + if UPGRADEDEBUG & debuglevel: + syslog.openlog("UPGRADE", syslog.LOG_PID) + syslog.syslog(syslog.LOG_DEBUG, s) + + +def signal_init(): + signal.signal(signal.SIGINT, signal.SIG_IGN) # ignore ctrl+c signal + signal.signal(signal.SIGTERM, signal.SIG_IGN) # ignore kill signal + signal.signal(signal.SIGTSTP, signal.SIG_IGN) # ignore ctrl+z signal + + +class BasePlatform(): + + def __init__(self): + self.upgrade_param = UPGRADE_SUMMARY.copy() + self.devtype = self.upgrade_param.get('devtype', None) + self.max_slot_num = self.upgrade_param.get("max_slot_num", 0) + self.head_info_config = {} + self.slot_config = {} + self.cold_chain_config = {} + self.subtype = None + self.chain = None + self.filetype = None + self.DEVTYPE = None + self.SUBTYPE = '0' + self.TYPE = None + self.CHAIN = None + self.CHIPNAME = None + self.VERSION = None + self.FILETYPE = None + self.CRC = None + self.SUBTYPE_LIST = None + + def save_and_set_value(self, cfg_list): + for config in cfg_list: + ret, val = get_value(config) + if ret: + config["save_value"] = val + else: + upgradeerror(val) + return False, "get save value fail" + + set_val = config.get("set_value", None) + if set_val is None: + log = "save_and_set_value lack of set_val config" + upgradeerror(log) + return log + + gettype = config.get("gettype", None) + set_cmd = config.get("set_cmd", None) + if gettype == "cmd": + if set_cmd is None: + log = "save_and_set_value lack of set_cmd config" + upgradeerror(log) + return False, log + config["cmd"] = set_cmd % set_val + upgradedebuglog("save_and_set_value modify set cmd to %s" % config["cmd"]) + else: + config["value"] = set_val + upgradedebuglog("save_and_set_value modify set val to %s" % config["value"]) + + ret, log = set_value(config) + if ret is False: + upgradeerror(log) + return False, log + return True, "save and set value success" + + def recover_save_value(self, cfg_list): + total_err = 0 + for config in cfg_list: + upgradedebuglog("config: %s, recover save value" % config) + val = config.get("save_value", None) + if val is None: + upgradeerror("recover_save_value lack of save_value config") + total_err -= 1 + continue + gettype = config.get("gettype", None) + set_cmd = config.get("set_cmd", None) + if gettype == "cmd": + config["cmd"] = set_cmd % val + upgradedebuglog("recover_save_value modify set cmd to %s" % config["cmd"]) + else: + config["value"] = val + upgradedebuglog("recover_save_value modify set val to %s" % config["value"]) + + ret, log = set_value(config) + if ret is False: + upgradeerror("recover save value write failed, log: %s" % log) + total_err -= 1 + else: + upgradedebuglog("recover save value success") + if total_err < 0: + return False, "recover save value failed" + return True, "recover save value success" + + def check_slot_present(self, slot_present_config): + presentbit = slot_present_config.get('presentbit') + ret, value = get_value(slot_present_config) + if ret is False: + return "NOT OK" + if isinstance(value, str): + val_t = int(value, 16) + else: + val_t = value + val_t = (val_t & (1 << presentbit)) >> presentbit + if val_t != slot_present_config.get('okval'): + status = "ABSENT" + else: + status = "PRESENT" + return status + + def linecard_present_check(self, slot_present_config): + present_status = self.check_slot_present(slot_present_config) + if present_status == "NOT OK": + return ERR_FW_DEVICE_ACCESS, "get slot present status failed." + if present_status == "ABSENT": + return ERR_FW_CARD_ABSENT, "slot absent" + return CHECK_OK, "slot present" + + def subprocess_warm_upgrade(self, config, file, main_type, sub_type, slot): + dev_name = config.get("name", None) + status, output = self.subprocess_firmware_upgrade(config, file, main_type, sub_type, slot) + if status is False: + upgradeerror("%s warm upgrade failed" % dev_name) + return False, output + command = "warm_upgrade.py %s 0x%x 0x%x %s %s %s" % (file, main_type, sub_type, slot, self.filetype, self.chain) + upgradedebuglog("warm upgrade cmd: %s" % command) + if os.path.exists(UPGRADE_DEBUG_FILE): + status, output = exec_os_cmd_log(command) + else: + status, output = exec_os_cmd(command) + if status: + upgradeerror("%s warm upgrade failed" % dev_name) + return False, output + upgradedebuglog("%s warm upgrade success" % dev_name) + return True, "upgrade success" + + def do_fw_upg_init_cmd(self, dev_name, init_cmd_list): + # pre operation + try: + for init_cmd_config in init_cmd_list: + ret, log = set_value(init_cmd_config) + if ret is False: + upgradeerror("%s do init cmd: %s failed, msg: %s" % (dev_name, init_cmd_config, log)) + return False, log + msg = "%s firmware init cmd all set success" % dev_name + upgradedebuglog(msg) + return True, msg + except Exception as e: + return False, str(e) + + def do_fw_upg_finish_cmd(self, dev_name, finish_cmd_list): + # end operation + ret = 0 + for finish_cmd_config in finish_cmd_list: + ret_t, log = set_value(finish_cmd_config) + if ret_t is False: + upgradeerror("%s do finish cmd: %s failed, msg: %s" % (dev_name, finish_cmd_config, log)) + ret = -1 + if ret != 0: + msg = "%s firmware finish cmd exec failed" % dev_name + upgradeerror(msg) + return False, msg + msg = "%s firmware finish cmd all set success" % dev_name + upgradedebuglog(msg) + return True, msg + + def subprocess_firmware_upgrade(self, config, file, main_type, sub_type, slot): + dev_name = config.get("name", None) + init_cmd_list = config.get("init_cmd", []) + finish_cmd_list = config.get("finish_cmd", []) + try: + ret, log = self.do_fw_upg_init_cmd(dev_name, init_cmd_list) + if ret is False: + self.do_fw_upg_finish_cmd(dev_name, finish_cmd_list) + return False, log + time.sleep(0.5) # delay 0.5s after execute init_cmd + command = "firmware_upgrade %s 0x%x 0x%x %s" % (file, main_type, sub_type, slot) + upgradedebuglog("firmware upgrade cmd: %s" % command) + if os.path.exists(UPGRADE_DEBUG_FILE): + status, output = exec_os_cmd_log(command) + else: + status, output = exec_os_cmd(command) + if status: + self.do_fw_upg_finish_cmd(dev_name, finish_cmd_list) + upgradeerror("%s firmware upgrade failed, msg: %s" % (dev_name, output)) + return False, output + upgradedebuglog("%s firmware upgrade success" % dev_name) + ret, log = self.do_fw_upg_finish_cmd(dev_name, init_cmd_list) + if ret is False: + return False, log + return True, "upgrade success" + except Exception as e: + self.do_fw_upg_finish_cmd(dev_name, finish_cmd_list) + return False, str(e) + + def subprocess_test_upgrade(self, config, file, main_type, sub_type, slot): + dev_name = config.get("name", None) + init_cmd_list = config.get("init_cmd", []) + finish_cmd_list = config.get("finish_cmd", []) + try: + ret, log = self.do_fw_upg_init_cmd(dev_name, init_cmd_list) + if ret is False: + self.do_fw_upg_finish_cmd(dev_name, finish_cmd_list) + return False, log + time.sleep(0.5) # delay 0.5s after execute init_cmd + command = "firmware_upgrade test %s 0x%x 0x%x %s" % (file, main_type, sub_type, slot) + upgradedebuglog("firmware upgrade cmd: %s" % command) + if os.path.exists(UPGRADE_DEBUG_FILE): + status, output = exec_os_cmd_log(command) + else: + status, output = exec_os_cmd(command) + if status: + self.do_fw_upg_finish_cmd(dev_name, finish_cmd_list) + upgradeerror("%s test upgrade failed, msg: %s" % (dev_name, output)) + return False, output + upgradedebuglog("%s test upgrade success" % dev_name) + ret, log = self.do_fw_upg_finish_cmd(dev_name, init_cmd_list) + if ret is False: + return False, log + return True, "upgrade success" + except Exception as e: + self.do_fw_upg_finish_cmd(dev_name, finish_cmd_list) + return False, str(e) + + def subprocess_bmc_upgrade(self, config, file, chip_select, erase_type): + dev_name = config.get("name", None) + init_cmd_list = config.get("init_cmd", []) + finish_cmd_list = config.get("finish_cmd", []) + save_set_reg_list = config.get("save_set_reg", []) + try: + # save and set reg + ret, log = self.save_and_set_value(save_set_reg_list) + if ret is False: + upgradeerror(log) + self.recover_save_value(save_set_reg_list) + self.do_fw_upg_finish_cmd(dev_name, finish_cmd_list) + return False, log + upgradedebuglog("%s save and set cmd all set success" % dev_name) + time.sleep(0.5) # delay 0.5s after execute save and set reg + + # pre operation + ret, log = self.do_fw_upg_init_cmd(dev_name, init_cmd_list) + if ret is False: + self.recover_save_value(save_set_reg_list) + self.do_fw_upg_finish_cmd(dev_name, finish_cmd_list) + return False, log + + upgradedebuglog("%s bmc init cmd all set success" % dev_name) + time.sleep(0.5) # delay 0.5s after execute init_cmd + + command = "fw_upgrade upgrade %s %s %s" % (file, chip_select, erase_type) + upgradedebuglog("fw_upgrade upgrade cmd: %s" % command) + status, output = exec_os_cmd_log(command) + if status: + upgradeerror("%s bmc upgrade failed" % dev_name) + self.recover_save_value(save_set_reg_list) + self.do_fw_upg_finish_cmd(dev_name, finish_cmd_list) + return False, output + upgradedebuglog("%s bmc upgrade success" % dev_name) + + ret1, log1 = self.recover_save_value(save_set_reg_list) + if ret1 is False: + upgradeerror("bmc upgrade recover save value failed, msg: %s" % log1) + ret2, log2 = self.do_fw_upg_finish_cmd(dev_name, finish_cmd_list) + if ret2 is False: + upgradeerror("bmc upgrade do finish command failed, msg: %s" % log2) + if ret1 is False or ret2 is False: + return False, "bmc upgrade do recover save value or finish command failed" + return True, "upgrade success" + + except Exception as e: + self.recover_save_value(save_set_reg_list) + self.do_fw_upg_finish_cmd(dev_name, finish_cmd_list) + return False, str(e) + + def file_head_param_check(self, head_info_config): + try: + self.DEVTYPE = head_info_config.get('DEVTYPE', None) + self.SUBTYPE = head_info_config.get('SUBTYPE', '0') + self.TYPE = head_info_config.get('TYPE', None) + self.CHAIN = head_info_config.get('CHAIN', None) + self.CHIPNAME = head_info_config.get('CHIPNAME', None) + self.VERSION = head_info_config.get('VERSION', None) + self.FILETYPE = head_info_config.get('FILETYPE', None) + self.CRC = head_info_config.get('CRC', None) + + if self.devtype != int(self.DEVTYPE, 16): + return ERR_FW_HEAD_CHECK, ("no support %s devtype" % self.DEVTYPE) + + if self.SUBTYPE is not None: + self.SUBTYPE_LIST = self.SUBTYPE.split(',') + self.SUBTYPE_LIST = [int(tmp_subtype, base=16) for tmp_subtype in self.SUBTYPE_LIST] + if len(self.SUBTYPE) != 0 and self.subtype not in self.SUBTYPE_LIST: + return ERR_FW_HEAD_CHECK, ("no support %s SUBTYPE" % self.SUBTYPE) + + if len(self.CHAIN) == 0 or len(self.FILETYPE) == 0: + return ERR_FW_HEAD_CHECK, ("CHAIN:%s, FILETYPE:%s get failed" % (self.CHAIN, self.FILETYPE)) + self.chain = int(self.CHAIN) + self.filetype = self.FILETYPE + upgradedebuglog("file head param: devtype:0x%x, subtype:0x%x, chain:%s, filetype:%s" + % (self.devtype, self.subtype, self.chain, self.filetype)) + return CHECK_OK, "SUCCESS" + except Exception as e: + return ERR_FW_RAISE_EXCEPTION, str(e) + + def parse_file_head(self, file): + try: + self.head_info_config = {} + with open(file, 'r', errors='ignore') as fd: + rdbuf = fd.read() + upgradedebuglog("start parse upgrade file head") + file_head_start = rdbuf.index('FILEHEADER(\n') # ponit to F + file_head_start += rdbuf[file_head_start:].index('\n') # ponit to \n + file_head_end = rdbuf.index(')\n') + header_buf = rdbuf[file_head_start + 1: file_head_end - 1] + upgradedebuglog("upgrade file head find FILEHEADER") + for line in header_buf.split('\n'): + head_list = line.split('=', 1) + head_key = head_list[0] + head_val = head_list[1] + self.head_info_config[head_key] = head_val + upgradedebuglog("file: %s head_info_config: %s" % (file, self.head_info_config)) + return CHECK_OK, "SUCCESS" + except Exception as e: + msg = "parse %s head failed, msg: %s" % (file, str(e)) + upgradeerror(msg) + return ERR_FW_RAISE_EXCEPTION, msg + + def get_file_size_k(self, file): + fsize = os.path.getsize(file) + fsize = fsize / float(1024) + return round(fsize, 2) + + def get_device_model(self, conf): + ret, val = get_value(conf) + if ret is False: + msg = "get device model failed, msg: %s" % val + return False, msg + decode_val = conf.get("decode") + if decode_val is None: + return True, val + for k, v in decode_val.items(): + if val == v: + return True, k + msg = "device model decode error, val: %s" % val + return False, msg + + def upgrade_fool_proofing(self, conf): + try: + status, dev_model = self.get_device_model(conf) + if status is False: + msg = "upgrade fool proofing get device model failed, msg: %s" % dev_model + upgradeerror(msg) + return False, msg + upgradedebuglog("get device model success, device model: %s" % dev_model) + if dev_model != self.VERSION: + msg = "upgrade fool proofing failed, device model: %s, upgrade file version: %s" % ( + dev_model, self.VERSION) + upgradedebuglog(msg) + return False, msg + msg = "upgrade fool proofing pass, device model: %s, upgrade file version: %s" % (dev_model, self.VERSION) + upgradedebuglog(msg) + return True, msg + except Exception as e: + upgradeerror(str(e)) + return False, str(e) + + def upgrading(self, config, file, devtype, subtype, slot, option_flag, erase_type=None): + dev_name = config.get("name", None) + if option_flag == COLD_UPGRADE: + status, output = self.subprocess_firmware_upgrade(config, file, devtype, subtype, slot) + elif option_flag == WARM_UPGRADE: + status, output = self.subprocess_warm_upgrade(config, file, devtype, subtype, slot) + elif option_flag == TEST_UPGRADE: + status, output = self.subprocess_test_upgrade(config, file, devtype, subtype, slot) + elif option_flag == BMC_UPGRADE: + status, output = self.subprocess_bmc_upgrade(config, file, slot, erase_type) + else: + log = "%s set error option flag" % dev_name + upgradeerror(log) + return False, log + + if status is False: + upgradeerror("%s upgrade failed" % dev_name) + return False, output + upgradedebuglog("%s upgrade success" % dev_name) + return True, "upgrade success" + + def initial_check(self, file, slot, upg_type): + try: + upgradedebuglog("BasePlatform initial_check, file: %s, slot: %s, upg_type: %s" % + (file, slot, upg_type)) + + upgradedebuglog("do file exist check...") + if not os.path.isfile(file): + msg = "%s not found" % file + upgradedebuglog(msg) + return ERR_FW_FILE_FOUND, msg + upgradedebuglog("file exist check ok") + + slot_name = "slot%d" % slot + slot_config = self.upgrade_param.get(slot_name, {}) + slot_present_config = slot_config.get("present", {}) + if len(slot_present_config) != 0: + upgradedebuglog("do %s present check..." % slot_name) + ret, log = self.linecard_present_check(slot_present_config) + if ret != CHECK_OK: + msg = "check %s present error, msg: %s" % (slot_name, log) + upgradedebuglog(msg) + return ret, msg + upgradedebuglog("%s present check ok" % slot_name) + + upgradedebuglog("do file head parse...") + self.subtype = slot_config.get("subtype", 0) + ret, log = self.parse_file_head(file) + if ret != CHECK_OK: + return ret, log + upgradedebuglog("file head parse success") + + upgradedebuglog("do file head check...") + ret, log = self.file_head_param_check(self.head_info_config) + if ret != CHECK_OK: + msg = "file: %s, head check failed, msg: %s" % (file, log) + upgradedebuglog(msg) + return ret, msg + upgradedebuglog("file head check ok") + + upgradedebuglog("get upgrade chain config...") + filetype_config = slot_config.get(self.filetype, {}) + if len(filetype_config) == 0: + msg = "file: %s filetype: %s no support" % (file, self.filetype) + upgradedebuglog(msg) + return ERR_FW_CONFIG_FOUND, msg + chain_num = "chain%s" % self.chain + chain_config = filetype_config.get(chain_num, {}) + if len(chain_config) == 0: + msg = "file: %s get %s config failed" % (file, chain_num) + upgradedebuglog(msg) + return ERR_FW_CONFIG_FOUND, msg + self.cold_chain_config = chain_config + upgradedebuglog("get %s filetype: %s %s config success" % (slot_name, self.filetype, chain_num)) + + fool_proofing = chain_config.get("fool_proofing") + if fool_proofing is not None: + upgradedebuglog("do fool proofing check...") + status, log = self.upgrade_fool_proofing(fool_proofing) + if status is False: + msg = "upgrade fool proofing check failed, msg: %s" % log + upgradedebuglog(msg) + return ERR_FW_FOOL_PROOF, msg + upgradedebuglog("do fool proofing check ok") + + if upg_type == WARM_UPGRADE: + upgradedebuglog("do support warm upgrade check...") + if chain_config.get("is_support_warm_upg", 0) != 1: + msg = "file: %s %s chain config not support warm upgrade" % (file, slot_name) + upgradedebuglog(msg) + return ERR_FW_NOSUPPORT_HOT, msg + upgradedebuglog("file: %s %s chain config support warm upgrade" % (file, slot_name)) + + filesizecheck = chain_config.get("filesizecheck", 0) + if filesizecheck != 0: + upgradedebuglog("do file size check...") + file_size = self.get_file_size_k(file) + if file_size > filesizecheck: + msg = "file: %s size: %s exceed %s" % (file, file_size, filesizecheck) + upgradedebuglog(msg) + return ERR_FW_CHECK_SIZE, msg + msg = "file: %s size: %s check ok" % (file, file_size) + upgradedebuglog(msg) + + msg = "file: %s slot: %s upgrade type: %s check ok" % (file, slot, upg_type) + upgradedebuglog(msg) + return CHECK_OK, msg + except Exception as e: + return ERR_FW_RAISE_EXCEPTION, str(e) + + def do_upgrade(self, file, slot, upg_type): + try: + ret, log = self.initial_check(file, slot, upg_type) + if ret != CHECK_OK: + return ret, log + + # start upgrading + upgradedebuglog("start upgrading") + ret, log = self.upgrading(self.cold_chain_config, file, self.devtype, self.subtype, slot, upg_type) + if ret is False: + upgradeerror("upgrade failed") + return ERR_FW_UPGRADE, log + upgradedebuglog("upgrade success") + return FIRMWARE_SUCCESS, "SUCCESS" + except Exception as e: + return ERR_FW_RAISE_EXCEPTION, str(e) + + def do_pre_check(self, conf): + ret, val = get_value(conf) + if ret is False: + msg = "pre check get value failed, msg: %s" % val + return False, msg + ok_val = conf.get("ok_val") + if val == ok_val: + msg = "pre check success, ok_val: %s, get value: %s" % (ok_val, val) + return True, msg + msg = "pre check failed, ok_val: %s, get value: %s" % (ok_val, val) + return False, msg + + def do_test(self, device, slot): + try: + # slot present check + slot_name = "slot%d" % slot + slot_config = self.upgrade_param.get(slot_name, {}) + slot_present_config = slot_config.get("present", {}) + if len(slot_present_config) != 0: + ret, log = self.linecard_present_check(slot_present_config) + if ret != CHECK_OK: + msg = "check %s present error, msg: %s" % (slot_name, log) + upgradedebuglog(msg) + return ret, msg + upgradedebuglog("%s present" % slot_name) + + # get list of devices to be tested + test_config = slot_config.get("TEST", {}) + if len(test_config) == 0: + return ERR_FW_CONFIG_FOUND, "test config no found" + device_list = test_config.get(device, []) + if len(device_list) == 0: + return ERR_FW_CONFIG_FOUND, ("logic device %s test config list not found" % device) + + # test_file existence check + for test_config in device_list: + chain_num = test_config.get("chain", None) + test_file = test_config.get("file", None) + display_name = test_config.get("display_name", None) + if chain_num is None or test_file is None or display_name is None: + log = "test_config:%s lack of config" % test_config + upgradeerror(log) + return ERR_FW_CONFIG_FOUND, log + if not os.path.isfile(test_file): + return ERR_FW_FILE_FOUND, ("%s not found" % test_file) + + # start testing + RET = 0 + pre_check_failed = 0 + pre_check_failed_summary = "" + failed_summary = "chain test failed.\ntest fail chain:" + success_summary = "test success chain:" + for test_config in device_list: + chain_num = test_config.get("chain", None) + test_file = test_config.get("file", None) + display_name = test_config.get("display_name", None) + pre_check_conf = test_config.get("pre_check", None) + if pre_check_conf is not None: + status, msg = self.do_pre_check(pre_check_conf) + if status is False: + pre_check_failed += 1 + log = "\nchain:%d, name:%s, pre check failed, msg: %s" % (chain_num, display_name, msg) + upgradedebuglog(log) + pre_check_failed_summary += log + continue + upgradedebuglog("chain:%d, name:%s, pre check ok, msg: %s" % (chain_num, display_name, msg)) + ret, log = self.do_upgrade(test_file, slot, TEST_UPGRADE) + if ret != FIRMWARE_SUCCESS: + RET = -1 + upgradeerror("chain:%d, name:%s test failed" % (chain_num, display_name)) + failed_summary += "\n chain:%d, name:%s;" % (chain_num, display_name) + else: + upgradedebuglog("chain:%d, name:%s test success" % (chain_num, display_name)) + success_summary += "\n chain:%d, name:%s;" % (chain_num, display_name) + if RET != 0: + return ERR_FW_UPGRADE, failed_summary + if pre_check_failed == len(device_list): + return ERR_FW_NO_FILE_SUCCESS, failed_summary + pre_check_failed_summary + return FIRMWARE_SUCCESS, success_summary + except Exception as e: + return ERR_FW_RAISE_EXCEPTION, str(e) + + def do_test_main(self, device, slot): + print("+================================+") + print("|Doing upgrade test, please wait.|") + ret, log = self.do_test(device, slot) + if ret == FIRMWARE_SUCCESS: + print("| test succeeded! |") + print("+================================+") + print(log) + sys.exit(0) + else: + print("| test failed! |") + print("+================================+") + print("FAILED REASON:") + print(log) + sys.exit(1) + + def do_bmc_upgrade_main(self, file, chip_select, erase_type): + bmc_upgrade_config = self.upgrade_param.get("BMC", {}) + ret, log = self.upgrading(bmc_upgrade_config, file, self.devtype, + self.subtype, chip_select, BMC_UPGRADE, erase_type) + if ret is True: + print("===========upgrade succeeded!============") + sys.exit(0) + else: + print("============upgrade failed!==============") + print("FAILED REASON:") + print("%s" % log) + sys.exit(1) + + +class FileUpg(object): + def __init__(self, config, file, devtype, subtype, slot, filetype, chain, upg_type): + self.config = config + self.file = file + self.devtype = devtype + self.subtype = subtype + self.slot = slot + self.filetype = filetype + self.chain = chain + self.upg_type = upg_type + + def __repr__(self): + return "file:%s slot:%d" % (self.file, self.slot) + + +class FwUpg(object): + def __init__(self): + self.upg_platform = BasePlatform() + self.warm_upg_platform = WarmBasePlatform() + self.max_slot_num = self.upg_platform.max_slot_num + self.file_list = [] + + def do_file_refresh(self, fw_upg_instance): + fw_upg_config = fw_upg_instance.config + fw_upg_file = fw_upg_instance.file + fw_upg_devtype = fw_upg_instance.devtype + fw_upg_subype = fw_upg_instance.subtype + fw_upg_slot = fw_upg_instance.slot + fw_upg_filetype = fw_upg_instance.filetype + fw_upg_chain = fw_upg_instance.chain + dev_name = fw_upg_config.get("name", None) + upgradedebuglog("%s start warm upgrade, file: %s, devtype:0x%x, subype: 0x%x, slot: %d, filetype: %s, chain: %d" % + (dev_name, fw_upg_file, fw_upg_devtype, fw_upg_subype, fw_upg_slot, fw_upg_filetype, fw_upg_chain)) + status, output = self.warm_upg_platform.do_warmupgrade(fw_upg_file, fw_upg_devtype, fw_upg_subype, fw_upg_slot, + fw_upg_filetype, fw_upg_chain) + if status is False: + upgradeerror("%s warm upgrade failed, msg: %s" % (dev_name, output)) + return False, output + upgradedebuglog("%s warm upgrade success" % dev_name) + return True, "upgrade success" + + def do_refresh(self): + try: + exec_os_cmd("touch %s" % WARM_UPGRADE_STARTED_FLAG) + exec_os_cmd("sync") + + # stop upper layer services access + ret, log = self.warm_upg_platform.stop_services_access() + if ret is False: + upgradeerror("stop upper layer services access failed") + upgradeerror(log) + return ERR_FW_UPGRADE, log + upgradedebuglog("stop upper layer services access success") + + for file_instance in self.file_list: + file_info = repr(file_instance) + ret, log = self.do_file_refresh(file_instance) + if ret is False: + msg = "%s refresh failed, ret:%s, \n log:%s." % (file_info, ret, log) + upgradeerror(msg) + return ERR_FW_UPGRADE, msg + upgradedebuglog("%s refresh success." % file_info) + msg = "all files refresh success." + return FIRMWARE_SUCCESS, msg + except Exception as e: + msg = "do warm upg exception happend. log:%s" % str(e) + upgradeerror(msg) + return ERR_FW_UPGRADE, msg + finally: + self.warm_upg_platform.start_services_access() + if os.path.isfile(WARM_UPGRADE_STARTED_FLAG): + exec_os_cmd("rm -rf %s" % WARM_UPGRADE_STARTED_FLAG) + exec_os_cmd("sync") + + def do_file_cold_upg(self, fw_upg_instance): + try: + upgradedebuglog("start cold upgrade") + fw_upg_config = fw_upg_instance.config + fw_upg_file = fw_upg_instance.file + fw_upg_devtype = fw_upg_instance.devtype + fw_upg_subype = fw_upg_instance.subtype + fw_upg_slot = fw_upg_instance.slot + ret, log = self.upg_platform.upgrading( + fw_upg_config, fw_upg_file, fw_upg_devtype, fw_upg_subype, fw_upg_slot, COLD_UPGRADE) + if ret is False: + upgradeerror("cold upgrade %s slot%d failed, log:%s" % (fw_upg_file, fw_upg_slot, log)) + return ERR_FW_UPGRADE, log + log = "cold upgrade %s slot%d success" % (fw_upg_file, fw_upg_slot) + upgradedebuglog(log) + return FIRMWARE_SUCCESS, log + except Exception as e: + msg = "do cold upg exception happend. log:%s" % str(e) + upgradeerror(msg) + return ERR_FW_UPGRADE, msg + + def do_file_init_check(self, file_path, slot, upg_type): + upgradedebuglog("do_file_init_check, file_path: %s, slot: %s, upg_type: %s" % (file_path, slot, upg_type)) + + if slot is None: # traverse all slots + for i in range(0, self.max_slot_num + 1): + ret, log = self.upg_platform.initial_check(file_path, i, upg_type) + if ret != CHECK_OK: + upgradedebuglog( + "file: %s, slot%d initial check not ok, ret: %d, msg: %s" % + (file_path, i, ret, log)) + accept_error = (ERR_FW_CARD_ABSENT, ERR_FW_HEAD_CHECK, ERR_FW_FOOL_PROOF) + if ret in accept_error: + msg = "file: %s, slot%d initial check ret: %d, acceptable error." % (file_path, i, ret) + upgradedebuglog(msg) + continue + return ret, log + file_instance = FileUpg(self.upg_platform.cold_chain_config, file_path, self.upg_platform.devtype, + self.upg_platform.subtype, i, self.upg_platform.filetype, self.upg_platform.chain, upg_type) + self.file_list.append(file_instance) + else: + slot = int(slot, 10) + ret, log = self.upg_platform.initial_check(file_path, slot, upg_type) + if ret != CHECK_OK: + msg = "file: %s, slot%d initial check not ok, ret: %d, msg: %s" % (file_path, slot, ret, log) + return ret, msg + file_instance = FileUpg(self.upg_platform.cold_chain_config, file_path, self.upg_platform.devtype, + self.upg_platform.subtype, slot, self.upg_platform.filetype, self.upg_platform.chain, upg_type) + self.file_list.append(file_instance) + msg = "file: %s all slots init check ok" % file_path + return CHECK_OK, msg + + def do_dir_init_check(self, path, slot, upg_type): + for root, dirs, names in os.walk(path): + # root: directory absolute path + # dirs: folder path collection under directory + # names: file path collection under directory + for filename in names: + # file_path is file absolute path + file_path = os.path.join(root, filename) + ret, log = self.do_file_init_check(file_path, slot, upg_type) + if ret != CHECK_OK: + return ret, log + msg = "all files in dir have been check ok" + upgradedebuglog(msg) + return CHECK_OK, msg + + def do_fw_upg(self, path, slot, upg_type): + match_zip_file_flag = False + try: + upgradedebuglog("do_fw_upg, path: %s, slot: %s, upg_type: %s" % (path, slot, upg_type)) + if slot is not None and not slot.isdigit(): + msg = "invalid slot param: %s" % slot + upgradeerror(msg) + return ERR_FW_INVALID_PARAM, msg + + upgradedebuglog("start init check") + if os.path.isfile(path) and path.endswith(".zip"): + upgradedebuglog("firmware upgrade via compressed package: %s" % path) + # remove origin firmware upgrade file + exec_os_cmd("rm -rf %s" % UPGRADE_FILE_DIR) + cmd = "unzip -o %s -d /tmp/" % path + if os.path.exists(UPGRADE_DEBUG_FILE): + status, output = exec_os_cmd_log(cmd) + else: + status, output = exec_os_cmd(cmd) + if status: + msg = "unzip %s failed, log: %s" % (path, output) + upgradeerror(msg) + return ERR_FW_UNZIP_FAILED, msg + match_zip_file_flag = True + path = UPGRADE_FILE_DIR + + if os.path.isdir(path): + ret, msg = self.do_dir_init_check(path, slot, upg_type) + elif os.path.isfile(path): + ret, msg = self.do_file_init_check(path, slot, upg_type) + else: + ret = ERR_FW_FILE_FOUND + msg = "path: %s not found" % path + upgradeerror(msg) + + if ret != CHECK_OK: + return ret, msg + + # self.file_list is a collection of all check ok files + if len(self.file_list) == 0: + msg = "all file upgrade check not be satisfied." + upgradeerror(msg) + return ERR_FW_NO_FILE_SUCCESS, msg + + SUCCUSS_FILE_SUMMARY = "SUCCESS FILE: \n" + # file cold upgrade + upgradedebuglog("start all files cold upgrade") + for file_instance in self.file_list: + file_info = repr(file_instance) + ret, log = self.do_file_cold_upg(file_instance) + if ret != FIRMWARE_SUCCESS: + msg = "%s cold upgrade failed, ret:%d, \n log:\n%s." % (file_info, ret, log) + upgradeerror(msg) + return ret, msg + SUCCUSS_FILE_SUMMARY += "%s \n" % file_info + upgradedebuglog("%s cold upgrade success." % file_info) + + # file refresh upgrade + if upg_type == WARM_UPGRADE: + upgradedebuglog("start all files refresh upgrade") + ret, log = self.do_refresh() + if ret != FIRMWARE_SUCCESS: + return ret, log + + msg = "all file upgrade success" + upgradedebuglog(msg) + return FIRMWARE_SUCCESS, SUCCUSS_FILE_SUMMARY + except Exception as e: + msg = "do dir upgrade exception happend. log: %s" % str(e) + upgradeerror(msg) + return ERR_FW_UPGRADE, msg + finally: + if match_zip_file_flag is True: + exec_os_cmd("rm -rf %s" % UPGRADE_FILE_DIR) + + def fw_upg(self, path, slot, upg_type): + print("+================================+") + print("| Doing upgrade, please wait... |") + ret, log = self.do_fw_upg(path, slot, upg_type) + if ret == FIRMWARE_SUCCESS: + print("| upgrade succeeded! |") + print("+================================+") + print(log) + sys.exit(0) + else: + print("| upgrade failed! |") + print("+================================+") + print("FAILED REASON:") + print("%s" % log) + sys.exit(1) + + +@click.group(cls=AliasedGroup, context_settings=CONTEXT_SETTINGS) +def main(): + '''upgrade script''' + + +# cold upgrade +@main.command() +@click.argument('file_name', required=True) +@click.argument('slot_num', required=False, default=None) +def cold(file_name, slot_num): + '''cold upgrade''' + fwupg = FwUpg() + fwupg.fw_upg(file_name, slot_num, COLD_UPGRADE) + + +# warm upgrade +@main.command() +@click.argument('file_name', required=True) +@click.argument('slot_num', required=False, default=None) +def warm(file_name, slot_num): + '''warm upgrade''' + fwupg = FwUpg() + fwupg.fw_upg(file_name, slot_num, WARM_UPGRADE) + + +# test upgrade +@main.command() +@click.argument('device', required=True) +@click.argument('slot_num', required=True) +def test(device, slot_num): + '''upgrade test''' + platform = BasePlatform() + platform.do_test_main(device, int(slot_num)) + + +# BMC upgrade +@main.command() +@click.argument('file_name', required=True) +@click.argument('chip_select', required=False, default="2") +@click.argument('erase_type', required=False, default="full") +def bmc(file_name, chip_select, erase_type): + '''BMC upgrade''' + platform = BasePlatform() + platform.do_bmc_upgrade_main(file_name, chip_select, erase_type) + + +if __name__ == '__main__': + signal_init() + debug_init() + main() diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/script/warm_upgrade.py b/platform/broadcom/sonic-platform-modules-ragile/common/script/warm_upgrade.py new file mode 100755 index 000000000000..69a310faa606 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/script/warm_upgrade.py @@ -0,0 +1,514 @@ +#!/usr/bin/env python3 +# -*- coding: UTF-8 -*- +import sys +import os +import time +import syslog +import signal +import click +from platform_util import get_value, set_value, exec_os_cmd, exec_os_cmd_log +from platform_config import WARM_UPGRADE_PARAM + + +WARM_UPGRADE_DEBUG_FILE = "/etc/.warm_upgrade_debug_flag" + +WARMUPGRADEDEBUG = 1 + +debuglevel = 0 + +CONTEXT_SETTINGS = {"help_option_names": ['-h', '--help']} + + +class AliasedGroup(click.Group): + + def get_command(self, ctx, cmd_name): + rv = click.Group.get_command(self, ctx, cmd_name) + if rv is not None: + return rv + matches = [x for x in self.list_commands(ctx) + if x.startswith(cmd_name)] + if not matches: + return None + if len(matches) == 1: + return click.Group.get_command(self, ctx, matches[0]) + ctx.fail('Too many matches: %s' % ', '.join(sorted(matches))) + return None + + +def debug_init(): + global debuglevel + if os.path.exists(WARM_UPGRADE_DEBUG_FILE): + debuglevel = debuglevel | WARMUPGRADEDEBUG + else: + debuglevel = debuglevel & ~(WARMUPGRADEDEBUG) + + +def warmupgradewarninglog(s): + # s = s.decode('utf-8').encode('gb2312') + syslog.openlog("WARMUPGRADE", syslog.LOG_PID) + syslog.syslog(syslog.LOG_WARNING, s) + + +def warmupgradecriticallog(s): + # s = s.decode('utf-8').encode('gb2312') + syslog.openlog("WARMUPGRADE", syslog.LOG_PID) + syslog.syslog(syslog.LOG_CRIT, s) + + +def warmupgradeerror(s): + # s = s.decode('utf-8').encode('gb2312') + syslog.openlog("WARMUPGRADE", syslog.LOG_PID) + syslog.syslog(syslog.LOG_ERR, s) + + +def warmupgradedebuglog(s): + # s = s.decode('utf-8').encode('gb2312') + if WARMUPGRADEDEBUG & debuglevel: + syslog.openlog("WARMUPGRADE", syslog.LOG_PID) + syslog.syslog(syslog.LOG_DEBUG, s) + + +def subprocess_warm_upgrade(file, main_type, sub_type, slot): + command = "firmware_upgrade %s 0x%x 0x%x %s" % (file, main_type, sub_type, slot) + warmupgradedebuglog("warm upgrade firmware cmd:%s" % command) + if os.path.exists(WARM_UPGRADE_DEBUG_FILE): + return exec_os_cmd_log(command) + return exec_os_cmd(command) + + +def signal_init(): + signal.signal(signal.SIGINT, signal.SIG_IGN) # ignore ctrl+c signal + signal.signal(signal.SIGTERM, signal.SIG_IGN) # ignore kill signal + signal.signal(signal.SIGTSTP, signal.SIG_IGN) # ignore ctrl+z signal + + +class RefreshUpgradeBase(object): + + def __init__(self, config, slot_num, devtype, subtype): + self._config = config + self._slot_num = slot_num + self._devtype = devtype + self._subtype = subtype + self.device_name = self._config.get("name", None) + self.refresh_file = self._config.get("refresh_file", None) + self.init_cmd_list = self._config.get("init_cmd", []) + self.save_set_reg_list = self._config.get("save_set_reg", []) + self.rw_recover_reg_list = self._config.get("rw_recover_reg", []) + self.after_upgrade_delay = self._config.get("after_upgrade_delay", None) + self.after_upgrade_delay_timeout = self._config.get("after_upgrade_delay_timeout", None) + self.refresh_finish_flag_check_config = self._config.get("refresh_finish_flag_check", None) + self.access_check_reg_config = self._config.get("access_check_reg", {}) + self.time_delay = 0 + self.finish_cmd_list = self._config.get("finish_cmd", []) + + def get_config(self): + pass + + def get_slot_num(self): + pass + + def save_value(self, cfg_list): + for config in cfg_list: + ret, val = get_value(config) + if ret: + config["value"] = val + else: + warmupgradeerror(val) + return False, val + return True, "save value success" + + def save_and_set_value(self, cfg_list): + for config in cfg_list: + ret, val = get_value(config) + if ret: + config["save_value"] = val + else: + warmupgradeerror(val) + return False, "get save value fail" + set_val = config.get("set_value", None) + if set_val is not None: + config["value"] = set_val + else: + warmupgradeerror("save_and_set_value lack of set_val config") + return False, "set value is not config" + ret, log = set_value(config) + if ret is False: + warmupgradeerror(log) + return False, log + return True, "save value success" + + def recover_value(self, cfg_list): + fail_flag = 0 + for config in cfg_list: + ret, log = set_value(config) + if ret is False: + fail_flag = -1 + warmupgradeerror("recover_value set_value failed, log: %s" % log) + if fail_flag != 0: + warmupgradeerror("recover_value write failed") + return False, "recover write failed" + return True, "recover write success" + + def recover_save_value(self, cfg_list): + total_err = 0 + for config in cfg_list: + val = config.get("save_value", None) + if val is None: + warmupgradeerror("recover_save_value lack of save_value config") + total_err -= 1 + continue + config["value"] = val + ret, log = set_value(config) + if ret is False: + total_err -= 1 + warmupgradeerror("recover save value write failed, log: %s" % log) + else: + warmupgradedebuglog("recover save value success") + if total_err < 0: + return False, "recover save value failed" + return True, "recover save value success" + + def do_fw_upg_init_cmd(self, init_cmd_list): + # pre operation + try: + for init_cmd_config in init_cmd_list: + ret, log = set_value(init_cmd_config) + if ret is False: + warmupgradeerror("%s do init cmd: %s failed, msg: %s" % (self.device_name, init_cmd_config, log)) + return False, log + msg = "%s warm upgrade init cmd all set success" % self.device_name + warmupgradedebuglog(msg) + return True, msg + except Exception as e: + return False, str(e) + + def do_fw_upg_finish_cmd(self, finish_cmd_list): + # end operation + total_err = 0 + for finish_cmd_config in finish_cmd_list: + ret_t, log = set_value(finish_cmd_config) + if ret_t is False: + warmupgradeerror("%s do finish cmd: %s failed, msg: %s" % (self.device_name, finish_cmd_config, log)) + total_err -= 1 + if total_err < 0: + msg = "%s warm upgrade finish cmd exec failed" % self.device_name + warmupgradeerror(msg) + return False, msg + msg = "%s warm upgrade finish cmd all set success" % self.device_name + warmupgradedebuglog(msg) + return True, msg + + def access_test(self, config): + # polling execute command + polling_cmd_list = config.get("polling_cmd", []) + for polling_cmd_config in polling_cmd_list: + ret, log = set_value(polling_cmd_config) + if ret is False: + warmupgradeerror(log) + return False + polling_delay = config.get("polling_delay", None) + if polling_delay is not None: + time.sleep(polling_delay) + + # record check val + check_val = config.get("value", None) + # write value + ret, log = set_value(config) + if ret is False: + warmupgradeerror(log) + return False + # read value + ret, val = get_value(config) + if ret is False: + warmupgradeerror(val) + return False + + # compare write and read val + warmupgradedebuglog("check_val:%s" % check_val) + warmupgradedebuglog("get_value:%s" % val) + if val != check_val: + warmupgradeerror("check_val:%s != get_value:%s" % (check_val, val)) + return False + return True + + def check_value(self, config): + # record check val + check_val = config.get("value", None) + ret, val = get_value(config) + if ret is False: + warmupgradeerror(val) + return False + # compare write and read val + warmupgradedebuglog("check_val:%s" % check_val) + warmupgradedebuglog("get_value:%s" % val) + if val != check_val: + warmupgradeerror("check_val:%s != get_value:%s" % (check_val, val)) + return False + return True + + def refresh_file_upgrade(self): + try: + warmupgradedebuglog("start %s warm upgrading" % self.device_name) + + # save and set reg + ret, log = self.save_and_set_value(self.save_set_reg_list) + if ret is False: + warmupgradeerror(log) + self.recover_save_value(self.save_set_reg_list) + self.do_fw_upg_finish_cmd(self.finish_cmd_list) + return False, log + warmupgradedebuglog("%s save and set reg cmd all set success" % self.device_name) + time.sleep(0.5) # delay 0.5s after execute save and set reg + + # pre operation + ret, log = self.do_fw_upg_init_cmd(self.init_cmd_list) + if ret is False: + warmupgradeerror(log) + self.recover_save_value(self.save_set_reg_list) + self.do_fw_upg_finish_cmd(self.finish_cmd_list) + return False, log + time.sleep(0.5) # delay 0.5s after execute init_cmd + + # save reg + ret, log = self.save_value(self.rw_recover_reg_list) + if ret is False: + warmupgradeerror("%s save reg failed" % self.device_name) + self.recover_save_value(self.save_set_reg_list) + self.do_fw_upg_finish_cmd(self.finish_cmd_list) + return False, log + warmupgradedebuglog("%s all reg save success" % self.device_name) + + # upgrade refresh file + if self.refresh_file is not None: + status, output = subprocess_warm_upgrade( + self.refresh_file, self._devtype, self._subtype, self._slot_num) + if status: + log = "%s refresh file upg failed, msg: %s" % (self.device_name, output) + warmupgradeerror(log) + self.recover_save_value(self.save_set_reg_list) + self.do_fw_upg_finish_cmd(self.finish_cmd_list) + return False, log + warmupgradedebuglog("%s refresh file upg success" % self.device_name) + + # delay the preset time after the upgrade is complete + if self.after_upgrade_delay is not None: + time.sleep(self.after_upgrade_delay) + + # check something in the timeout period + if self.after_upgrade_delay_timeout is not None: + while self.time_delay < self.after_upgrade_delay_timeout: + + # check refresh finish flag + if self.refresh_finish_flag_check_config is not None: + ret = self.check_value(self.refresh_finish_flag_check_config) + if ret is False: + time.sleep(1) + self.time_delay = self.time_delay + 1 + warmupgradedebuglog("doing refresh_finish_flag_check, time_delay:%s" % self.time_delay) + continue + warmupgradedebuglog("%s upgrade_finish_flag_check success. self.time_delay:%d" + % (self.device_name, self.time_delay)) + + # doing logic device rw access test + ret = self.access_test(self.access_check_reg_config) + if ret: + warmupgradedebuglog( + "%s rw test success. self.time_delay:%d" % + (self.device_name, self.time_delay)) + break + time.sleep(1) + self.time_delay = self.time_delay + 1 + warmupgradedebuglog("doing access_test, self.time_delay:%s" % self.time_delay) + + if self.time_delay >= self.after_upgrade_delay_timeout: + log = "wait %s access test timeout" % self.device_name + warmupgradeerror(log) + self.recover_save_value(self.save_set_reg_list) + self.do_fw_upg_finish_cmd(self.finish_cmd_list) + return False, log + warmupgradedebuglog("%s access test success" % self.device_name) + + # recover reg + ret, log = self.recover_value(self.rw_recover_reg_list) + if ret is False: + warmupgradeerror("recover %s reg failed" % self.device_name) + self.recover_save_value(self.save_set_reg_list) + self.do_fw_upg_finish_cmd(self.finish_cmd_list) + return False, log + warmupgradedebuglog("recover %s reg success" % self.device_name) + # finally + ret1, log1 = self.recover_save_value(self.save_set_reg_list) + if ret1 is False: + warmupgradeerror("bmc upgrade recover save value failed, msg: %s" % log1) + ret2, log2 = self.do_fw_upg_finish_cmd(self.finish_cmd_list) + if ret2 is False: + warmupgradeerror("bmc upgrade do finish command failed, msg: %s" % log2) + if ret1 is False or ret2 is False: + return False, "upgrading %s recover save value or finish command failed" % self.device_name + return True, "upgrading %s success" % self.device_name + + except Exception as e: + log = "refresh file upgrade Exception happend, error log : %s" % str(e) + self.recover_save_value(self.save_set_reg_list) + self.do_fw_upg_finish_cmd(self.finish_cmd_list) + return False, log + + +class RefreshUpgrade(RefreshUpgradeBase): + + def __init__(self, config, slot_num, devtype, subtype): + super(RefreshUpgrade, self).__init__(config, slot_num, devtype, subtype) + + def get_config(self): + super(RefreshUpgrade, self).get_config() + return self._config + + def get_slot_num(self): + super(RefreshUpgrade, self).get_slot_num() + return self._slot_num + + +class WarmBasePlatform(): + + def __init__(self): + signal_init() + debug_init() + self.warm_upgrade_param = WARM_UPGRADE_PARAM.copy() + self.stop_services_cmd_list = self.warm_upgrade_param.get("stop_services_cmd", []) + self.start_services_cmd_list = self.warm_upgrade_param.get("start_services_cmd", []) + self.__warm_upgrade_config_list = [] + + def execute_command_list(self, cmd_list): + for cmd_item in cmd_list: + warmupgradedebuglog("execute cmd: %s" % cmd_item) + status, output = exec_os_cmd(cmd_item) + if status: + log = "execute %s failed, msg: %s" % (cmd_item, output) + warmupgradeerror(log) + return False, log + return True, "execute success" + + def stop_services_access(self): + return self.execute_command_list(self.stop_services_cmd_list) + + def start_services_access(self): + return self.execute_command_list(self.start_services_cmd_list) + + def check_slot_present(self, slot_present_config): + totalerr = 0 + presentbit = slot_present_config.get('presentbit') + ret, value = get_value(slot_present_config) + if ret is False: + return "NOT OK" + if isinstance(value, str): + val_t = int(value, 16) + else: + val_t = value + val_t = (val_t & (1 << presentbit)) >> presentbit + if val_t != slot_present_config.get('okval'): + status = "ABSENT" + else: + status = "PRESENT" + return status + + def linecard_present_check(self, slot_name, slot_present_config): + present_status = self.check_slot_present(slot_present_config) + present_status_tuple = ("ABSENT", "NOT OK") + if present_status in present_status_tuple: + return False, ("%s not present, warm upgrade exit" % slot_name) + warmupgradedebuglog("%s present" % slot_name) + return True, ("%s present" % slot_name) + + def start_warmupgrade(self): + try: + # start refresh file upgrade process + for dev in self.__warm_upgrade_config_list: + ret, log = dev.refresh_file_upgrade() + if ret is False: + return ret, log + return True, "all success" + except Exception as e: + log = "Exception happend, error log : %s" % str(e) + return False, log + + def do_warmupgrade(self, file, main_type, sub_type, slot, file_type, chain): + try: + # upgrade file existence check + if not os.path.isfile(file): + return False, "%s not found" % file + + # get slot config + slot_name = "slot%d" % slot + slot_config = self.warm_upgrade_param.get(slot_name, {}) + if len(slot_config) == 0: + return False, ("%s config not found" % slot_name) + + # linecard present check + slot_present_config = slot_config.get("present", {}) + if len(slot_present_config) != 0: + ret, log = self.linecard_present_check(slot_name, slot_present_config) + if ret is False: + return False, log + + # match file_type and chain_num get chain_config + file_type_config = slot_config.get(file_type, {}) + chain_name = "chain%d" % chain + chain_list = file_type_config.get(chain_name, []) + self.__warm_upgrade_config_list = [] + for refresh_config in chain_list: + # refresh_file existence check + refresh_file_judge_flag = refresh_config.get("refresh_file_judge_flag", 0) + if refresh_file_judge_flag == 1: + refresh_file = refresh_config.get("refresh_file", None) + if not os.path.isfile(refresh_file): + log = "%s not found" % refresh_file + return False, log + # each refresh_config add as an instance of RefreshUpgrade Class + refresh_instance = RefreshUpgrade(refresh_config, slot, main_type, sub_type) + self.__warm_upgrade_config_list.append(refresh_instance) + + ret, log = self.start_warmupgrade() + if ret is False: + warmupgradeerror("doing warm upgrade failed") + warmupgradeerror(log) + return ret, log + + except Exception as e: + log = "Exception happend, error log : %s" % str(e) + return False, log + return True, "all success" + + def do_warm_upgrade(self, file, main_type, sub_type, slot, file_type, chain): + print("+================================+") + print("|Begin warm upgrade, please wait..|") + ret, log = self.do_warmupgrade(file, main_type, sub_type, slot, file_type, chain) + if ret: + print("| warm upgrade succeeded! |") + print("+================================+") + sys.exit(0) + else: + print("| warm upgrade failed! |") + print("+================================+") + print("FAILED REASON:") + print("%s" % log) + sys.exit(1) + + +@click.group(invoke_without_command=True, context_settings=CONTEXT_SETTINGS) +@click.argument('file', required=True) +@click.argument('main_type', required=True) +@click.argument('sub_type', required=True) +@click.argument('slot', required=True) +@click.argument('file_type', required=True) +@click.argument('chain', required=True) +def main(file, main_type, sub_type, slot, file_type, chain): + '''warm upgrade''' + signal_init() + debug_init() + platform = WarmBasePlatform() + platform.do_warm_upgrade(file, int(main_type, 16), int(sub_type, 16), int(slot), file_type, int(chain)) + + +# warm upgrade +if __name__ == '__main__': + main() diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/service/device_i2c.service b/platform/broadcom/sonic-platform-modules-ragile/common/service/device_i2c.service deleted file mode 100755 index 136034900aaf..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/common/service/device_i2c.service +++ /dev/null @@ -1,15 +0,0 @@ -[Unit] -Description= ragile Global Initialize I2c drivers. -After=pddf-platform-init.service -Before=pmon.service -DefaultDependencies=no - -[Service] -Type=oneshot -ExecStart=/usr/local/bin/device_i2c.py start -ExecStop=/usr/local/bin/device_i2c.py stop -RemainAfterExit=yes - -[Install] -WantedBy=multi-user.target - diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/service/platform_driver.service b/platform/broadcom/sonic-platform-modules-ragile/common/service/platform_driver.service new file mode 100644 index 000000000000..08a49d695c92 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/service/platform_driver.service @@ -0,0 +1,15 @@ +[Unit] +Description= Global Initialize platform drivers. +After=local-fs.target +Before=pmon.service platform_process.service +#DefaultDependencies=no + +[Service] +Type=oneshot +ExecStart=/usr/local/bin/platform_driver.py start +ExecStop=/usr/local/bin/platform_driver.py stop +RemainAfterExit=yes + +[Install] +WantedBy=multi-user.target + diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/service/platform_process.service b/platform/broadcom/sonic-platform-modules-ragile/common/service/platform_process.service new file mode 100644 index 000000000000..1ef246156353 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/service/platform_process.service @@ -0,0 +1,16 @@ +[Unit] +Description= Global Load process. +After=platform_driver.service +Before=determine-reboot-cause.service +Requires=platform_driver.service +#DefaultDependencies=no + +[Service] +Type=oneshot +ExecStart=/usr/local/bin/platform_process.py start +ExecStop=/usr/local/bin/platform_process.py stop +RemainAfterExit=yes + +[Install] +WantedBy=multi-user.target + diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/sonic_platform/__init__.py b/platform/broadcom/sonic-platform-modules-ragile/common/sonic_platform/__init__.py new file mode 100644 index 000000000000..b70995a582fc --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/sonic_platform/__init__.py @@ -0,0 +1,2 @@ +__all__ = ["platform", "chassis", "sfp", "eeprom", "component", "thermal", "psu", "fan", "fan_drawer", "watchdog"] +from . import platform diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/sonic_platform/chassis.py b/platform/broadcom/sonic-platform-modules-ragile/common/sonic_platform/chassis.py new file mode 100644 index 000000000000..b0ddc8691f2e --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/sonic_platform/chassis.py @@ -0,0 +1,530 @@ +#!/usr/bin/env python3 + +############################################################################# +# +# +# Module contains an implementation of SONiC Platform Base API and +# provides the platform information +# +############################################################################# + +try: + import time + import sys + from sonic_platform_base.chassis_base import ChassisBase + from sonic_platform.sfp import Sfp + from sonic_platform.psu import Psu + # from sonic_platform.fan import Fan + from sonic_platform.fan_drawer import FanDrawer + from sonic_platform.thermal import Thermal + # from sonic_platform.watchdog import Watchdog + from sonic_platform.component import Component + from sonic_platform.eeprom import Eeprom + from sonic_platform.dcdc import Dcdc + from plat_hal.baseutil import baseutil + + from plat_hal.interface import interface + +except ImportError as error: + raise ImportError(str(error) + "- required module not found")from error + + +class Chassis(ChassisBase): + """ + Platform-specific Chassis class + """ + # List of Dcdc objects representing all dcdc + # available on the chassis + _dcdc_list = None + + STATUS_INSERTED = "1" + STATUS_REMOVED = "0" + STATUS_NORMAL = "0" + STATUS_ABNORMAL = "1" + sfp_present_dict = {} + fan_present_dict = {} + voltage_status_dict = {} + + def __init__(self): + ChassisBase.__init__(self) + self._dcdc_list = [] + self.int_case = interface() + # Initialize SFP list + + # sfp.py will read eeprom contents and retrive the eeprom data. + # It will also provide support sfp controls like reset and setting + # low power mode. + # We pass the eeprom path and sfp control path from chassis.py + # So that sfp.py implementation can be generic to all platforms + try: + self._sfp_list = [] + self.port_num = baseutil.get_config().get("sfps", None).get("port_num", 0) + self.port_start_index = baseutil.get_config().get("sfps", None).get("port_index_start", 0) + # fix problem with first index is 1, we add a fake sfp node + if self.port_start_index == 1: + self._sfp_list.append(Sfp(1)) + + # sfp id always start at 1 + for index in range(1, self.port_num + 1): + self._sfp_list.append(Sfp(index)) + + for i in range(self.port_start_index, self.port_start_index + self.port_num): + self.sfp_present_dict[i] = self.STATUS_REMOVED + + except Exception as err: + print("SFP init error: %s" % str(err)) + + try: + self._eeprom = Eeprom(self.int_case) + except Exception as err: + print("EEPROM INIT ERROR %s" % str(err)) + + # Initialize watchdog + # self._watchdog = Watchdog() + fantray_num = self.int_case.get_fan_total_number() + for index in range(fantray_num): + fandrawer = FanDrawer(self.int_case, index + 1) + self._fan_drawer_list.append(fandrawer) + self._fan_list.extend(fandrawer._fan_list) + + psu_num = self.int_case.get_psu_total_number() + for index in range(psu_num): + psuobj = Psu(self.int_case, index + 1) + self._psu_list.append(psuobj) + + thermal_num = self.int_case.get_temp_id_number() + for index in range(thermal_num): + thermalobj = Thermal(self.int_case, index + 1) + self._thermal_list.append(thermalobj) + + component_num = self.int_case.get_cpld_total_number() + for index in range(component_num): + componentobj = Component(self.int_case, index + 1) + self._component_list.append(componentobj) + + dcdc_num = self.int_case.get_dcdc_total_number() + for index in range(dcdc_num): + dcdcobj = Dcdc(self.int_case, index + 1) + self._dcdc_list.append(dcdcobj) + + def get_name(self): + """ + Retrieves the name of the chassis + Returns: + string: The name of the chassis + """ + name = '' + sys_eeprom = self.get_eeprom() + if sys_eeprom is None: + return '' + + e = sys_eeprom.read_eeprom() + name = sys_eeprom.modelstr(e) + if name is None: + return '' + return name + + def get_presence(self): + """ + Retrieves the presence of the chassis + Returns: + bool: True if chassis is present, False if not + """ + return True + + def get_model(self): + """ + Retrieves the model number (or part number) of the chassis + Returns: + string: Model/part number of chassis + """ + model = '' + sys_eeprom = self.get_eeprom() + if sys_eeprom is None: + return '' + + e = sys_eeprom.read_eeprom() + model = sys_eeprom.modelnumber(e) + if model is None: + return '' + return model + + def get_serial_number(self): + """ + Retrieves the hardware serial number for the chassis + + Returns: + A string containing the hardware serial number for this chassis. + """ + serial_number = '' + sys_eeprom = self.get_eeprom() + if sys_eeprom is None: + return '' + + e = sys_eeprom.read_eeprom() + serial_number = sys_eeprom.serial_number_str(e) + if serial_number is None: + return '' + + return serial_number + + def get_revision(self): + """ + Retrieves the hardware revision of the device + + Returns: + string: Revision value of device + """ + device_version = '' + sys_eeprom = self.get_eeprom() + if sys_eeprom is None: + return '' + + e = sys_eeprom.read_eeprom() + device_version = sys_eeprom.deviceversion(e) + if device_version is None: + return '' + + return device_version + + def get_serial(self): + """ + Retrieves the serial number of the chassis (Service tag) + Returns: + string: Serial number of chassis + """ + return self.get_serial_number() + + def get_status(self): + """ + Retrieves the operational status of the chassis + Returns: + bool: A boolean value, True if chassis is operating properly + False if not + """ + return True + + def get_position_in_parent(self): + """ + Retrieves 1-based relative physical position in parent device. If the agent cannot determine the parent-relative position + for some reason, or if the associated value of entPhysicalContainedIn is '0', then the value '-1' is returned + Returns: + integer: The 1-based relative physical position in parent device or -1 if cannot determine the position + """ + return -1 + + def is_replaceable(self): + """ + Indicate whether this device is replaceable. + Returns: + bool: True if it is replaceable. + """ + return False + + def initizalize_system_led(self): + return True + + def set_status_led(self, color): + return False + + def get_status_led(self): + """ + Gets the state of the system LED + + Returns: + A string, one of the valid LED color strings which could be vendor + specified. + """ + ret, color = self.int_case.get_led_color_by_type('SYS_LED') + if ret is True: + return color + return 'N/A' + + def get_base_mac(self): + """ + Retrieves the base MAC address for the chassis + + Returns: + A string containing the MAC address in the format + 'XX:XX:XX:XX:XX:XX' + """ + base_mac = '' + sys_eeprom = self.get_eeprom() + if sys_eeprom is None: + return '' + + e = sys_eeprom.read_eeprom() + base_mac = sys_eeprom.base_mac_addr(e) + if base_mac is None: + return '' + + return base_mac.upper() + + def get_system_eeprom_info(self): + """ + Retrieves the full content of system EEPROM information for the chassis + + Returns: + A dictionary where keys are the type code defined in + OCP ONIE TlvInfo EEPROM format and values are their corresponding + values. + Ex. { '0x21':'AG9064', '0x22':'V1.0', '0x23':'AG9064-0109867821', + '0x24':'001c0f000fcd0a', '0x25':'02/03/2018 16:22:00', + '0x26':'01', '0x27':'REV01', '0x28':'AG9064-C2358-16G'} + """ + sys_eeprom = self.get_eeprom() + if sys_eeprom is None: + return {} + return sys_eeprom.system_eeprom_info() + + def get_thermal_manager(self): + """ + Retrieves thermal manager class on this chassis + :return: A class derived from ThermalManagerBase representing the + specified thermal manager. ThermalManagerBase is returned as default + """ + return False + + def get_reboot_cause(self): + """ + Retrieves the cause of the previous reboot + Returns: + A tuple (string, string) where the first element is a string + containing the cause of the previous reboot. This string must be + one of the predefined strings in this class. If the first string + is "REBOOT_CAUSE_HARDWARE_OTHER", the second string can be used + to pass a description of the reboot cause. + """ + reboot_cause_msg = self.int_case.get_cpu_reboot_cause() + if "Power Loss" in reboot_cause_msg: + reboot_cause_type = self.REBOOT_CAUSE_POWER_LOSS + elif "Watchdog" in reboot_cause_msg: + reboot_cause_type = self.REBOOT_CAUSE_WATCHDOG + elif "BMC reboot" in reboot_cause_msg or "BMC powerdown" in reboot_cause_msg: + reboot_cause_type = self.REBOOT_CAUSE_HARDWARE_OTHER + elif "Thermal Overload: ASIC" in reboot_cause_msg: + reboot_cause_type = self.REBOOT_CAUSE_THERMAL_OVERLOAD_ASIC + elif "Thermal Overload: Other" in reboot_cause_msg: + reboot_cause_type = self.REBOOT_CAUSE_THERMAL_OVERLOAD_OTHER + elif "Other" in reboot_cause_msg: + reboot_cause_type = self.REBOOT_CAUSE_NON_HARDWARE + else: + reboot_cause_type = self.REBOOT_CAUSE_NON_HARDWARE + return (reboot_cause_type, reboot_cause_msg) + + def get_module(self, index): + """ + Retrieves module represented by (0-based) index + + Args: + index: An integer, the index (0-based) of the module to + retrieve + + Returns: + An object dervied from ModuleBase representing the specified + module + """ + module = None + + try: + if self.get_num_modules(): + module = self._module_list[index] + except IndexError: + sys.stderr.write("Module index {} out of range (0-{})\n".format( + index, len(self._module_list) - 1)) + + return module + + def get_fan_drawer(self, index): + """ + Retrieves fan drawers represented by (0-based) index + + Args: + index: An integer, the index (0-based) of the fan drawer to + retrieve + + Returns: + An object dervied from FanDrawerBase representing the specified fan + drawer + """ + fan_drawer = None + + try: + if self.get_num_fan_drawers(): + fan_drawer = self._fan_drawer_list[index] + except IndexError: + sys.stderr.write("Fan drawer index {} out of range (0-{})\n".format( + index, len(self._fan_drawer_list) - 1)) + + return fan_drawer + + def get_change_event(self, timeout=0): + """ + Returns a nested dictionary containing all devices which have + experienced a change at chassis level + + Args: + timeout: Timeout in milliseconds (optional). If timeout == 0, + this method will block until a change is detected. + + Returns: + (bool, dict): + - bool: True if call successful, False if not; + - dict: A nested dictionary where key is a device type, + value is a dictionary with key:value pairs in the format of + {'device_id':'device_event'}, where device_id is the device ID + for this device and device_event. + The known devices's device_id and device_event was defined as table below. + ----------------------------------------------------------------- + device | device_id | device_event | annotate + ----------------------------------------------------------------- + 'fan' '' '0' Fan removed + '1' Fan inserted + + 'sfp' '' '0' Sfp removed + '1' Sfp inserted + '2' I2C bus stuck + '3' Bad eeprom + '4' Unsupported cable + '5' High Temperature + '6' Bad cable + + 'voltage' '' '0' Vout normal + '1' Vout abnormal + -------------------------------------------------------------------- + Ex. {'fan':{'0':'0', '2':'1'}, 'sfp':{'11':'0', '12':'1'}, + 'voltage':{'U20':'0', 'U21':'1'}} + Indicates that: + fan 0 has been removed, fan 2 has been inserted. + sfp 11 has been removed, sfp 12 has been inserted. + monitored voltage U20 became normal, voltage U21 became abnormal. + Note: For sfp, when event 3-6 happened, the module will not be avalaible, + XCVRD shall stop to read eeprom before SFP recovered from error status. + """ + + change_event_dict = {"fan": {}, "sfp": {}, "voltage": {}} + + start_time = time.time() + forever = False + + if timeout == 0: + forever = True + elif timeout > 0: + timeout = timeout / float(1000) # Convert to secs + else: + print("get_change_event:Invalid timeout value: %s" % timeout) + return False, change_event_dict + + end_time = start_time + timeout + if start_time > end_time: + print("get_change_event:time wrap / invalid timeout value: %s" % timeout) + return False, change_event_dict # Time wrap or possibly incorrect timeout + try: + while timeout >= 0: + # check for sfp + sfp_change_dict = self.get_transceiver_change_event() + # check for fan + fan_change_dict = self.get_fan_change_event() + # check for voltage + voltage_change_dict = self.get_voltage_change_event() + + if sfp_change_dict or fan_change_dict or voltage_change_dict: + change_event_dict["sfp"] = sfp_change_dict + change_event_dict["fan"] = fan_change_dict + change_event_dict["voltage"] = voltage_change_dict + return True, change_event_dict + if forever: + time.sleep(1) + else: + timeout = end_time - time.time() + if timeout >= 1: + time.sleep(1) # We poll at 1 second granularity + else: + if timeout > 0: + time.sleep(timeout) + return True, change_event_dict + except Exception as e: + print(e) + print("get_change_event: Should not reach here.") + return False, change_event_dict + + def get_transceiver_change_event(self): + current_sfp_present_dict = {} + ret_dict = {} + + # Check for OIR events and return ret_dict + for i in range(self.port_start_index, self.port_start_index + self.port_num): + sfp = self._sfp_list[i] + if sfp.get_presence(): + current_sfp_present_dict[i] = self.STATUS_INSERTED + + else: + current_sfp_present_dict[i] = self.STATUS_REMOVED + + # Update reg value + if current_sfp_present_dict == self.sfp_present_dict: + return ret_dict + + for index, status in current_sfp_present_dict.items(): + if self.sfp_present_dict[index] != status: + ret_dict[index] = status + + self.sfp_present_dict = current_sfp_present_dict + + return ret_dict + + def get_fan_change_event(self): + current_fan_present_dict = {} + ret_dict = {} + + # Check for OIR events and return ret_dict + for index, fan in enumerate(self._fan_list): + if fan.get_presence() is True: + current_fan_present_dict[index] = self.STATUS_INSERTED + else: + current_fan_present_dict[index] = self.STATUS_REMOVED + + if len(self.fan_present_dict) == 0: # first time + self.fan_present_dict = current_fan_present_dict + return {} + + if current_fan_present_dict == self.fan_present_dict: + return {} + + # updated fan_present_dict + for index, status in current_fan_present_dict.items(): + if self.fan_present_dict[index] != status: + ret_dict[str(index)] = status + self.fan_present_dict = current_fan_present_dict + return ret_dict + + def get_voltage_change_event(self): + current_voltage_status_dict = {} + ret_dict = {} + + # Check for OIR events and return ret_dict + for index, dcdc in enumerate(self._dcdc_list): + name = dcdc.get_name() + value = dcdc.get_value() + high = dcdc.get_high_threshold() + low = dcdc.get_low_threshold() + if (value is None) or (value > high) or (value < low): + current_voltage_status_dict[name] = self.STATUS_ABNORMAL + else: + current_voltage_status_dict[name] = self.STATUS_NORMAL + + if len(self.voltage_status_dict) == 0: # first time + self.voltage_status_dict = current_voltage_status_dict + return {} + + if current_voltage_status_dict == self.voltage_status_dict: + return {} + + # updated voltage_status_dict + for name, status in current_voltage_status_dict.items(): + if self.voltage_status_dict[name] != status: + ret_dict[name] = status + self.voltage_status_dict = current_voltage_status_dict + return ret_dict + + diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/sonic_platform/component.py b/platform/broadcom/sonic-platform-modules-ragile/common/sonic_platform/component.py new file mode 100644 index 000000000000..fa674a98a6bf --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/sonic_platform/component.py @@ -0,0 +1,226 @@ +#!/usr/bin/env python3 + +######################################################################## +# +# Module contains an implementation of SONiC Platform Base API and +# provides the Components' (e.g., BIOS, CPLD, FPGA, etc.) available in +# the platform +# +######################################################################## + +try: + import time + import subprocess + import os + from sonic_platform_base.component_base import ComponentBase +except ImportError as e: + raise ImportError(str(e) + "- required module not found") from e + + +FIRMWARE_UPDATE_DIR = "/tmp/.firmwareupdate/" + +class Component(ComponentBase): + """Platform-specific Component class""" + + def __init__(self, interface_obj, index): + self.cpld_dict = {} + self.int_case = interface_obj + self.index = index + self.update_time = 0 + self.cpld_id = "CPLD" + str(index) + + def cpld_dict_update(self): + local_time = time.time() + if not self.cpld_dict or (local_time - self.update_time) >= 1: # update data every 1 seconds + self.update_time = local_time + self.cpld_dict = self.int_case.get_cpld_version_by_id(self.cpld_id) + + def get_slot(self): + self.cpld_dict_update() + return self.cpld_dict["Slot"] + + def get_warm_upgrade_flag(self): + self.cpld_dict_update() + return self.cpld_dict["Warm"] + + def get_name(self): + """ + Retrieves the name of the component + + Returns: + A string containing the name of the component + """ + self.cpld_dict_update() + return self.cpld_dict["Name"] + + def get_description(self): + """ + Retrieves the description of the component + + Returns: + A string containing the description of the component + """ + self.cpld_dict_update() + return self.cpld_dict["Desc"] + + def get_firmware_version(self): + """ + Retrieves the firmware version of the component + + Note: the firmware version will be read from HW + + Returns: + A string containing the firmware version of the component + """ + self.cpld_dict_update() + return self.cpld_dict["Version"] + + def get_available_firmware_version(self, image_path): + """ + Retrieves the available firmware version of the component + + Note: the firmware version will be read from image + + Args: + image_path: A string, path to firmware image + + Returns: + A string containing the available firmware version of the component + """ + raise NotImplementedError + + def get_firmware_update_notification(self, image_path): + """ + Retrieves a notification on what should be done in order to complete + the component firmware update + + Args: + image_path: A string, path to firmware image + + Returns: + A string containing the component firmware update notification if required. + By default 'None' value will be used, which indicates that no actions are required + """ + return None + + def install_firmware(self, image_path): + """ + Installs firmware to the component + + This API performs firmware installation only: this may/may not be the same as firmware update. + In case platform component requires some extra steps (apart from calling Low Level Utility) + to load the installed firmware (e.g, reboot, power cycle, etc.) - this must be done manually by user + + Note: in case immediate actions are required to complete the component firmware update + (e.g., reboot, power cycle, etc.) - will be done automatically by API and no return value provided + + Args: + image_path: A string, path to firmware image + + Returns: + A boolean, True if install was successful, False if not + """ + if not os.path.isfile(image_path): + print("ERROR: %s not found" % image_path) + return False + cmdstr = "upgrade.py cold %s %d" % (image_path, self.get_slot()) + status, output = subprocess.getstatusoutput(cmdstr) + if status == 0: + print("INFO: %s firmware install succeeded" % self.get_name()) + return True + print("%s install failed. status:%d, output:\n%s" % (self.get_name(), status, output)) + return False + + def update_firmware(self, image_path): + """ + Updates firmware of the component + + This API performs firmware update: it assumes firmware installation and loading in a single call. + In case platform component requires some extra steps (apart from calling Low Level Utility) + to load the installed firmware (e.g, reboot, power cycle, etc.) - this will be done automatically by API + + Args: + image_path: A string, path to firmware image + + Raises: + RuntimeError: update failed + """ + if not os.path.isfile(image_path): + raise RuntimeError("ERROR: %s not found" % image_path) + + if self.get_warm_upgrade_flag() == 1: # use warm upgrade + cmdstr = "upgrade.py warm %s %d" % (image_path, self.get_slot()) + else: + cmdstr = "upgrade.py cold %s %d" % (image_path, self.get_slot()) + status, output = subprocess.getstatusoutput(cmdstr) + if status == 0: + if self.get_warm_upgrade_flag() != 1: # not support warm upgrade, need to cold reboot + print("INFO: %s firmware install succeeded" % self.get_name()) + print("INFO: please cold reboot to make the %s firmware up-to-date" % self.get_name()) + else: + print("INFO: %s firmware update succeeded" % self.get_name()) + print("INFO: %s firmware version up-to-date" % self.get_name()) + return None + raise RuntimeError(output) + + def auto_update_firmware(self, image_path, boot_type): + """ + Updates firmware of the component + + This API performs firmware update automatically based on boot_type: it assumes firmware installation + and/or creating a loading task during the reboot, if needed, in a single call. + In case platform component requires some extra steps (apart from calling Low Level Utility) + to load the installed firmware (e.g, reboot, power cycle, etc.) - this will be done automatically during the reboot. + The loading task will be created by API. + + Args: + image_path: A string, path to firmware image + boot_type: A string, reboot type following the upgrade + - none/fast/warm/cold + + Returns: + Output: A return code + return_code: An integer number, status of component firmware auto-update + - return code of a positive number indicates successful auto-update + - status_installed = 1 + - status_updated = 2 + - status_scheduled = 3 + - return_code of a negative number indicates failed auto-update + - status_err_boot_type = -1 + - status_err_image = -2 + - status_err_unknown = -3 + + Raises: + RuntimeError: auto-update failure cause + """ + if not os.path.isfile(image_path): + print("ERROR: %s not found" % image_path) + return -2 + + if not os.path.isdir(FIRMWARE_UPDATE_DIR): + os.mkdir(FIRMWARE_UPDATE_DIR) + + warm_upgrade_flag = self.get_warm_upgrade_flag() + file_name = os.path.basename(image_path) + file_path = os.path.join(FIRMWARE_UPDATE_DIR, file_name) + if os.path.exists(file_path): # firmware already update + if warm_upgrade_flag == 1: + print("INFO: %s firmware update succeeded, firmware version up-to-date" % self.get_name()) + return 2 + print("INFO: %s firmware install succeeded, please cold reboot to make it up-to-date" % self.get_name()) + return 1 + + if warm_upgrade_flag == 1: # use warm upgrade + cmdstr = "upgrade.py warm %s %d" % (image_path, self.get_slot()) + else: + cmdstr = "upgrade.py cold %s %d" % (image_path, self.get_slot()) + status, output = subprocess.getstatusoutput(cmdstr) + if status == 0: + os.mknod(file_path) + if warm_upgrade_flag == 1: + print("INFO: %s firmware update succeeded, firmware version up-to-date" % self.get_name()) + return 2 + print("INFO: %s firmware install succeeded, please cold reboot to make it up-to-date" % self.get_name()) + return 1 + print("%s update failed, status:%d, output:\n%s" % (self.get_name(), status, output)) + return -3 diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/sonic_platform/dcdc.py b/platform/broadcom/sonic-platform-modules-ragile/common/sonic_platform/dcdc.py new file mode 100644 index 000000000000..494d4aa610dc --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/sonic_platform/dcdc.py @@ -0,0 +1,85 @@ +#!/usr/bin/env python3 + +######################################################################## +# +# Module contains an implementation of SONiC Platform Base API and +# provides the Thermals' information which are available in the platform +# +######################################################################## +import time + + +class Dcdc(object): + + def __init__(self, interface_obj, index): + self.dcdc_dict = {} + self.int_case = interface_obj + self.index = index + self.update_time = 0 + self.dcdc_id = "DCDC" + str(index) + + def dcdc_dict_update(self): + local_time = time.time() + if not self.dcdc_dict or (local_time - self.update_time) >= 1: # update data every 1 seconds + self.update_time = local_time + self.dcdc_dict = self.int_case.get_dcdc_by_id(self.dcdc_id) + + def get_name(self): + """ + Retrieves the name of the sensor + + Returns: + string: The name of the sensor + """ + self.dcdc_dict_update() + return self.dcdc_dict["Name"] + + def get_value(self): + """ + Retrieves current value reading from sensor + """ + self.dcdc_dict_update() + value = self.dcdc_dict["Value"] + if value is None: + value = 0 + return round(float(value), 3) + + def get_high_threshold(self): + """ + Retrieves the high threshold temperature of sensor + """ + self.dcdc_dict_update() + value = self.dcdc_dict["High"] + if value is None: + value = 0 + return round(float(value), 3) + + def get_low_threshold(self): + """ + Retrieves the low threshold temperature of sensor + """ + self.dcdc_dict_update() + value = self.dcdc_dict["Low"] + if value is None: + value = 0 + return round(float(value), 3) + + def get_high_critical_threshold(self): + """ + Retrieves the high critical threshold temperature of sensor + """ + self.dcdc_dict_update() + value = self.dcdc_dict["Max"] + if value is None: + value = 0 + return round(float(value), 3) + + def get_low_critical_threshold(self): + """ + Retrieves the low critical threshold temperature of sensor + """ + self.dcdc_dict_update() + value = self.dcdc_dict["Min"] + if value is None: + value = 0 + return round(float(value), 3) diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/sonic_platform/eeprom.py b/platform/broadcom/sonic-platform-modules-ragile/common/sonic_platform/eeprom.py new file mode 100644 index 000000000000..05fcc3c25678 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/sonic_platform/eeprom.py @@ -0,0 +1,92 @@ +#!/usr/bin/env python3 +######################################################################## +# +# Module contains platform specific implementation of SONiC Platform +# Base API and provides the EEPROMs' information. +# +# The different EEPROMs available are as follows: +# - System EEPROM : Contains Serial number, Service tag, Base MA +# address, etc. in ONIE TlvInfo EEPROM format. +# - PSU EEPROM : Contains Serial number, Part number, Service Tag, +# PSU type, Revision. +# - Fan EEPROM : Contains Serial number, Part number, Service Tag, +# Fan type, Number of Fans in Fantray, Revision. +######################################################################## + +try: + from sonic_eeprom import eeprom_tlvinfo +except ImportError as error: + raise ImportError(str(error) + "- required module not found") from error + + +class Eeprom(eeprom_tlvinfo.TlvInfoDecoder): + + def __init__(self, interface_obj): + self.int_case = interface_obj + self.name = "ONIE_E2" + + eeprom_path = self.int_case.get_onie_e2_path(self.name) + if eeprom_path is None: + raise ValueError("get eeprom path failed") + + super().__init__(eeprom_path, 0, "", True) + + def modelnumber(self, e): + ''' + Returns the value field of the model(part) number TLV as a string + ''' + (is_valid, t) = self.get_tlv_field(e, self._TLV_CODE_PART_NUMBER) + if not is_valid: + return super().part_number_str(e) + + return t[2].decode("ascii") + + def deviceversion(self, e): + ''' + Returns the value field of the Device Version as a string + ''' + (is_valid, t) = self.get_tlv_field(e, self._TLV_CODE_DEVICE_VERSION) + if not is_valid: + return "N/A" + + return str(ord(t[2])) + + def system_eeprom_info(self): + ''' + Retrieves the full content of system EEPROM information for the chassis + + Returns: + A dictionary where keys are the type code defined in + OCP ONIE TlvInfo EEPROM format and values are their corresponding + values. + Ex. { '0x21':'AG9064', '0x22':'V1.0', '0x23':'AG9064-0109867821', + '0x24':'001c0f000fcd0a', '0x25':'02/03/2018 16:22:00', + '0x26':'01', '0x27':'REV01', '0x28':'AG9064-C2358-16G'} + ''' + sys_eeprom_dict = {} + e = self.read_eeprom() + if self._TLV_HDR_ENABLED: + if not self.is_valid_tlvinfo_header(e): + return {} + total_len = (e[9] << 8) | e[10] + tlv_index = self._TLV_INFO_HDR_LEN + tlv_end = self._TLV_INFO_HDR_LEN + total_len + else: + tlv_index = self.eeprom_start + tlv_end = self._TLV_INFO_MAX_LEN + + while (tlv_index + 2) < len(e) and tlv_index < tlv_end: + if not self.is_valid_tlv(e[tlv_index:]): + break + + tlv = e[tlv_index:tlv_index + 2 + e[tlv_index + 1]] + code = "0x%02X" % tlv[0] + name, value = self.decoder(None, tlv) + sys_eeprom_dict[code] = value + + if e[tlv_index] == self._TLV_CODE_QUANTA_CRC or \ + e[tlv_index] == self._TLV_CODE_CRC_32: + break + tlv_index += e[tlv_index + 1] + 2 + + return sys_eeprom_dict diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/sonic_platform/fan.py b/platform/broadcom/sonic-platform-modules-ragile/common/sonic_platform/fan.py new file mode 100644 index 000000000000..9499e721a0f9 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/sonic_platform/fan.py @@ -0,0 +1,308 @@ +#!/usr/bin/env python3 +######################################################################## +# +# Module contains an implementation of SONiC Platform Base API and +# provides the Fans' information which are available in the platform. +# +######################################################################## + +try: + import time + from sonic_platform_base.fan_base import FanBase +except ImportError as e: + raise ImportError(str(e) + "- required module not found") from e + + +class Fan(FanBase): + """Platform-specific Fan class""" + + def __init__(self, interface_obj, fantray_index, fan_index, psu_fan=False, psu_index=0): + self.fan_dict = {} + self.int_case = interface_obj + self.fantray_index = fantray_index + self.fan_index = fan_index + self.psu_index = psu_index + self.is_psu_fan = psu_fan + self.update_time = 0 + if not self.is_psu_fan: + self.name = "FAN" + str(fantray_index) + else: + self.name = "PSU" + str(psu_index) + + def fan_dict_update(self): + local_time = time.time() + if not self.fan_dict or (local_time - self.update_time) >= 1: # update data every 1 seconds + self.update_time = local_time + if not self.is_psu_fan: + self.fan_dict = self.int_case.get_fan_info(self.name) + else: + self.fan_dict = self.int_case.get_psu_fru_info(self.name) + + def get_name(self): + """ + Retrieves the fan name + Returns: + string: The name of the device + """ + if not self.is_psu_fan: + return "Fantray{}_{}".format(self.fantray_index, self.fan_index) + return "PSU{}_FAN{}".format(self.psu_index, self.fan_index) + + def get_model(self): + """ + Retrieves the part number of the FAN + Returns: + string: Part number of FAN + """ + if not self.is_psu_fan: + self.fan_dict_update() + return self.fan_dict["NAME"] + return 'N/A' + + def get_serial(self): + """ + Retrieves the serial number of the FAN + Returns: + string: Serial number of FAN + """ + if not self.is_psu_fan: + self.fan_dict_update() + return self.fan_dict["SN"] + return 'N/A' + + def get_presence(self): + """ + Retrieves the presence of the FAN + Returns: + bool: True if fan is present, False if not + """ + if not self.is_psu_fan: + return self.int_case.get_fan_presence(self.name) + return self.int_case.get_psu_presence(self.name) + + def get_status(self): + """ + Retrieves the operational status of the FAN + Returns: + bool: True if FAN is operating properly, False if not + """ + if not self.get_presence(): + return False + + if not self.is_psu_fan: + fan_dir = {} + fan_dir = self.int_case.get_fan_info_rotor(self.name) + # get fan rotor pwm + rotor_name = "Rotor" + str(self.fan_index) + value = fan_dir[rotor_name]["Speed"] + min_speed = fan_dir[rotor_name]["SpeedMin"] + max_speed = fan_dir[rotor_name]["SpeedMax"] + tolerance = fan_dir[rotor_name]["Tolerance"] + else: + psu_status_dict = self.int_case.get_psu_status(self.name) + value = psu_status_dict["FanSpeed"]["Value"] + min_speed = psu_status_dict["FanSpeed"]["Min"] + max_speed = psu_status_dict["FanSpeed"]["Max"] + tolerance = psu_status_dict["FanSpeed"]["Tolerance"] + + if isinstance(tolerance, str) or tolerance is None: + tolerance = 30 + + if isinstance(value, str) or value is None: + return False + + if value < min_speed: + return False + + speed = int(value * 100 / max_speed) + if speed > 100: + speed = 100 + elif speed < 0: + speed = 0 + target = self.get_target_speed() + + if (speed - target) > target * tolerance / 100: + return False + if (target - speed) > target * tolerance / 100: + return False + + return True + + def get_position_in_parent(self): + """ + Retrieves 1-based relative physical position in parent device. If the agent cannot determine the parent-relative position + for some reason, or if the associated value of entPhysicalContainedIn is '0', then the value '-1' is returned + Returns: + integer: The 1-based relative physical position in parent device or -1 if cannot determine the position + """ + return -1 + + def is_replaceable(self): + """ + Indicate whether this device is replaceable. + Returns: + bool: True if it is replaceable. + """ + return True + + def get_direction(self): + """ + Retrieves the fan airflow direction + Returns: + A string, either FAN_DIRECTION_INTAKE or FAN_DIRECTION_EXHAUST + depending on fan direction + + Notes: + - Forward/Exhaust : Air flows from Port side to Fan side. + - Reverse/Intake : Air flows from Fan side to Port side. + """ + self.fan_dict_update() + air_flow = self.fan_dict["AirFlow"] + if air_flow is not None: + return air_flow + return self.FAN_DIRECTION_NOT_APPLICABLE + + def get_speed(self): + """ + Retrieves the speed of fan as a percentage of full speed + + Returns: + An integer, the percentage of full fan speed, in the range 0 (off) + to 100 (full speed) + """ + if not self.get_presence(): + return 0 + + if not self.is_psu_fan: + fan_dir = {} + fan_dir = self.int_case.get_fan_info_rotor(self.name) + # get fan rotor pwm + rotor_name = "Rotor" + str(self.fan_index) + value = fan_dir[rotor_name]["Speed"] + max_speed = fan_dir[rotor_name]["SpeedMax"] + else: + psu_status_dict = self.int_case.get_psu_status(self.name) + value = psu_status_dict["FanSpeed"]["Value"] + max_speed = psu_status_dict["FanSpeed"]["Max"] + + if isinstance(value, str) or value is None: + return 0 + pwm = value * 100 / max_speed + if pwm > 100: + pwm = 100 + elif pwm < 0: + pwm = 0 + return int(pwm) + + def get_speed_tolerance(self): + """ + Retrieves the speed tolerance of the fan + Returns: + An integer, the percentage of variance from target speed which is + considered tolerable + """ + # The default tolerance value is fixed as 30% + if not self.is_psu_fan: + fan_dir = {} + fan_dir = self.int_case.get_fan_info_rotor(self.name) + # get fan rotor tolerance + rotor_name = "Rotor" + str(self.fan_index) + tolerance = fan_dir[rotor_name]["Tolerance"] + else: + psu_status_dict = self.int_case.get_psu_status(self.name) + tolerance = psu_status_dict["FanSpeed"]["Tolerance"] + + if isinstance(tolerance, str) or tolerance is None: + return 30 + return tolerance + + def fan_set_speed_pwm(self, pwm): + status = self.int_case.set_fan_speed_pwm(self.name, self.fan_index, pwm) + if status == -1: + return False + return True + + def set_speed(self, speed): + """ + Set fan speed to expected value + Args: + speed: An integer, the percentage of full fan speed to set fan to, + in the range 0 (off) to 100 (full speed) + Returns: + bool: True if set success, False if fail. + """ + if not self.is_psu_fan: + return self.fan_set_speed_pwm(speed) + return self.int_case.set_psu_fan_speed_pwm(self.name, int(speed)) + + def set_status_led(self, color): + """ + Set led to expected color + Args: + color: A string representing the color with which to set the + fan module status LED + Returns: + bool: True if set success, False if fail. + """ + # not supported + return False + + def get_status_led(self): + """ + Gets the state of the Fan status LED + + Returns: + A string, one of the predefined STATUS_LED_COLOR_* strings. + """ + if self.is_psu_fan: + # No LED available for PSU Fan + return 'N/A' + + if not self.get_presence(): + return 'N/A' + + ret, color = self.int_case.get_fan_led(self.name) + if ret is True: + return color + return 'N/A' + + def get_target_speed(self): + """ + Retrieves the target (expected) speed of the fan + Returns: + An integer, the percentage of full fan speed, in the range 0 (off) + to 100 (full speed) + """ + if not self.is_psu_fan: + # get fan rotor pwm + pwm = int(self.int_case.get_fan_speed_pwm(self.name, self.fan_index)) + else: + psu_status_dict = self.int_case.get_psu_status(self.name) + if psu_status_dict["InputStatus"] is False: + pwm = 0 + else: + pwm = self.get_speed() # target equal to real pwm, to avoid alarm + return int(pwm) + + def get_vendor(self): + """ + Retrieves the vendor name of the fan + + Returns: + string: Vendor name of fan + """ + if not self.is_psu_fan: + return "WB" + return 'N/A' + + def get_revision(self): + """ + Retrieves the hardware revision of the device + + Returns: + string: Revision value of device + """ + if not self.is_psu_fan: + self.fan_dict_update() + return self.fan_dict["HW"] + return 'N/A' diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/sonic_platform/fan_drawer.py b/platform/broadcom/sonic-platform-modules-ragile/common/sonic_platform/fan_drawer.py new file mode 100644 index 000000000000..f0b039648158 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/sonic_platform/fan_drawer.py @@ -0,0 +1,167 @@ +#!/usr/bin/env python3 +# +# fan_drawer_base.py +# +# Abstract base class for implementing a platform-specific class with which +# to interact with a fan drawer module in SONiC +# + +try: + import time + from sonic_platform_base.fan_drawer_base import FanDrawerBase + from sonic_platform.fan import Fan +except ImportError as e: + raise ImportError(str(e) + "- required module not found") from e + + +class FanDrawer(FanDrawerBase): + """ + Abstract base class for interfacing with a fan drawer + """ + # Device type definition. Note, this is a constant. + DEVICE_TYPE = "fan_drawer" + + def __init__(self, interface_obj, fantray_index): + FanDrawerBase.__init__(self) + self.fantray_dict = {} + self.fantray_update_time = 0 + self.fantray_index = fantray_index + self.int_case = interface_obj + self.fantrayname = "FAN" + str(fantray_index) + self.num_fans_per_fantray = self.int_case.get_fan_rotor_number(self.fantrayname) + for i in range(self.num_fans_per_fantray): + self._fan_list.append(Fan(interface_obj, fantray_index, i + 1)) + + def fantray_dict_update(self): + local_time = time.time() + # update data every 1 seconds + if not self.fantray_dict or (local_time - self.fantray_update_time) >= 1: + self.fantray_update_time = local_time + self.fantray_dict = self.int_case.get_fan_info(self.fantrayname) + + def get_name(self): + """ + Retrieves the name of the device + Returns: + string: The name of the device + """ + return "Fantray{}".format(self.fantray_index) + + def get_presence(self): + """ + Retrieves the presence of the FAN + Returns: + bool: True if fan is present, False if not + """ + return self.int_case.get_fan_presence(self.fantrayname) + + def get_model(self): + """ + Retrieves the part number of the FAN + Returns: + string: Part number of FAN + """ + self.fantray_dict_update() + return self.fantray_dict["NAME"] + + def get_serial(self): + """ + Retrieves the serial number of the FAN + Returns: + string: Serial number of FAN + """ + self.fantray_dict_update() + return self.fantray_dict["SN"] + + def get_revision(self): + """ + Retrieves the hardware revision of the device + + Returns: + string: Revision value of device + """ + self.fantray_dict_update() + return self.fantray_dict["HW"] + + def get_status(self): + """ + Retrieves the operational status of the FAN + Returns: + bool: True if FAN is operating properly, False if not + """ + for i in range(self.num_fans_per_fantray): + if self._fan_list[i].get_status() is False: + return False + return True + + def get_position_in_parent(self): + """ + Retrieves 1-based relative physical position in parent device. If the agent cannot determine the parent-relative position + for some reason, or if the associated value of entPhysicalContainedIn is '0', then the value '-1' is returned + Returns: + integer: The 1-based relative physical position in parent device or -1 if cannot determine the position + """ + return -1 + + def is_replaceable(self): + """ + Indicate whether this device is replaceable. + Returns: + bool: True if it is replaceable. + """ + return True + + def get_num_fans(self): + """ + Retrieves the number of fans available on this fan drawer + Returns: + An integer, the number of fan modules available on this fan drawer + """ + return len(self._fan_list) + + def get_all_fans(self): + """ + Retrieves all fan modules available on this fan drawer + Returns: + A list of objects derived from FanBase representing all fan + modules available on this fan drawer + """ + return self._fan_list + + def set_status_led(self, color): + """ + Sets the state of the fan drawer status LED + Args: + color: A string representing the color with which to set the + fan drawer status LED + Returns: + bool: True if status LED state is set successfully, False if not + """ + # not supported + return False + + def get_status_led(self): + """ + Gets the state of the Fan status LED + + Returns: + A string, one of the predefined STATUS_LED_COLOR_* strings. + """ + if not self.get_presence(): + return 'N/A' + + ret, color = self.int_case.get_fan_led(self.fantrayname) + if ret is True: + return color + return 'N/A' + + def get_maximum_consumed_power(self): + """ + Retrives the maximum power drawn by Fan Drawer + + Returns: + A float, with value of the maximum consumable power of the + component. + """ + self.fantray_dict_update() + return self.fantray_dict["PowerMax"] diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/sonic_platform/pcie.py b/platform/broadcom/sonic-platform-modules-ragile/common/sonic_platform/pcie.py new file mode 100644 index 000000000000..8ea66f339e96 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/sonic_platform/pcie.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# -*- coding: utf-8 -*- + +######################################################################## +# +# Module contains a platform specific implementation of SONiC Platform +# Base PCIe class +# +######################################################################## + +try: + from sonic_platform_base.sonic_pcie.pcie_common import PcieUtil +except ImportError as e: + raise ImportError(str(e) + "- required module not found") from e + + +class Pcie(PcieUtil): + """Platform-specific Pcie class""" + + def __init__(self, platform_path): + PcieUtil.__init__(self, platform_path) diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/sonic_platform/platform.py b/platform/broadcom/sonic-platform-modules-ragile/common/sonic_platform/platform.py new file mode 100644 index 000000000000..4d6fe03d93ac --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/sonic_platform/platform.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 + +############################################################################# +# +# Module contains an implementation of SONiC Platform Base API and +# provides the platform information +# +############################################################################# + +try: + from sonic_platform_base.platform_base import PlatformBase + from sonic_platform.chassis import Chassis +except ImportError as e: + raise ImportError(str(e) + "- required module not found") from e + + +class Platform(PlatformBase): + """ + Platform-specific class + """ + + def __init__(self): + PlatformBase.__init__(self) + self._chassis = Chassis() diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/sonic_platform/psu.py b/platform/broadcom/sonic-platform-modules-ragile/common/sonic_platform/psu.py new file mode 100644 index 000000000000..a9f7e87d2027 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/sonic_platform/psu.py @@ -0,0 +1,359 @@ +#!/usr/bin/env python3 +######################################################################## +# +# Module contains an implementation of SONiC Platform Base API and +# provides the PSUs' information which are available in the platform +# +######################################################################## + + +try: + import time + from sonic_platform_base.psu_base import PsuBase + from sonic_platform.fan import Fan +except ImportError as e: + raise ImportError(str(e) + "- required module not found") from e + + +class Psu(PsuBase): + """Platform-specific PSU class""" + + def __init__(self, interface_obj, index): + self.psu_dict = {} + self.psu_status_dict = {} + self.psu_power_dict = {} + self._fan_list = [] + self._thermal_list = [] + self.int_case = interface_obj + self.index = index + self.name = "PSU" + str(index) + + self.psu_dict_update_time = 0 + self.psu_status_dict_update_time = 0 + self.psu_power_dict_update_time = 0 + + self._fan_list.append(Fan(self.int_case, 1, 1, psu_fan=True, psu_index=index)) + + def psu_dict_update(self): + local_time = time.time() + if not self.psu_dict or (local_time - self.psu_dict_update_time) >= 1: # update data every 1 seconds + self.psu_dict_update_time = local_time + self.psu_dict = self.int_case.get_psu_fru_info(self.name) + + def psu_status_dict_update(self): + local_time = time.time() + if not self.psu_status_dict or ( + local_time - self.psu_status_dict_update_time) >= 1: # update data every 1 seconds + self.psu_status_dict_update_time = local_time + self.psu_status_dict = self.int_case.get_psu_status(self.name) + + def psu_power_dict_update(self): + local_time = time.time() + if not self.psu_power_dict or ( + local_time - self.psu_power_dict_update_time) >= 1: # update data every 1 seconds + self.psu_power_dict_update_time = local_time + self.psu_power_dict = self.int_case.get_psu_power_status(self.name) + + def get_name(self): + """ + Retrieves the name of the device + + Returns: + string: The name of the device + """ + return "Psu{}".format(self.index) + + def get_presence(self): + """ + Retrieves the presence of the Power Supply Unit (PSU) + + Returns: + bool: True if PSU is present, False if not + """ + return self.int_case.get_psu_presence(self.name) + + def get_model(self): + """ + Retrieves the part number of the PSU + + Returns: + string: Part number of PSU + """ + self.psu_dict_update() + return self.psu_dict["DisplayName"] + + def get_serial(self): + """ + Retrieves the serial number of the PSU + + Returns: + string: Serial number of PSU + """ + self.psu_dict_update() + return self.psu_dict["SN"] + + def get_status(self): + """ + Retrieves the operational status of the PSU + + Returns: + bool: True if PSU is operating properly, False if not + """ + return self.int_case.get_psu_input_output_status(self.name) + + def get_position_in_parent(self): + """ + Retrieves 1-based relative physical position in parent device. If the agent cannot determine the parent-relative position + for some reason, or if the associated value of entPhysicalContainedIn is '0', then the value '-1' is returned + Returns: + integer: The 1-based relative physical position in parent device or -1 if cannot determine the position + """ + return -1 + + def is_replaceable(self): + """ + Indicate whether this device is replaceable. + Returns: + bool: True if it is replaceable. + """ + return True + + def get_voltage(self): + """ + Retrieves current PSU voltage output + + Returns: + A float number, the output voltage in volts, + e.g. 12.1 + """ + self.psu_status_dict_update() + if self.psu_status_dict["InputStatus"] is False: + value = 0 + else: + self.psu_power_dict_update() + value = self.psu_power_dict["Outputs"]["Voltage"]["Value"] + if value is None: + value = 0 + return round(float(value), 1) + + def get_current(self): + """ + Retrieves present electric current supplied by PSU + + Returns: + A float number, electric current in amperes, + e.g. 15.4 + """ + self.psu_status_dict_update() + if self.psu_status_dict["InputStatus"] is False: + value = 0 + else: + self.psu_power_dict_update() + value = self.psu_power_dict["Outputs"]["Current"]["Value"] + if value is None: + value = 0 + return round(float(value), 1) + + def get_power(self): + """ + Retrieves current energy supplied by PSU + + Returns: + A float number, the power in watts, + e.g. 302.6 + """ + self.psu_status_dict_update() + if self.psu_status_dict["InputStatus"] is False: + value = 0 + else: + self.psu_power_dict_update() + value = self.psu_power_dict["Outputs"]["Power"]["Value"] + if value is None: + value = 0 + return round(float(value), 1) + + def get_powergood_status(self): + """ + Retrieves the powergood status of PSU + + Returns: + A boolean, True if PSU has stablized its output voltages and + passed all its internal self-tests, False if not. + """ + return self.int_case.get_psu_input_output_status(self.name) + + def get_status_led(self): + """ + Gets the state of the PSU status LED + + Returns: + A string, one of the predefined STATUS_LED_COLOR_* strings. + """ + if not self.get_presence(): + return "N/A" + if self.int_case.get_psu_input_output_status(self.name): + return self.STATUS_LED_COLOR_GREEN + return self.STATUS_LED_COLOR_RED + + def set_status_led(self, color): + """ + Sets the state of the PSU status LED + Args: + color: A string representing the color with which to set the + PSU status LED + Returns: + bool: True if status LED state is set successfully, False if + not + """ + # not supported + return False + + def get_temperature(self): + """ + Retrieves current temperature reading from PSU + + Returns: + A float number of current temperature in Celsius up to nearest thousandth + of one degree Celsius, e.g. 30.125 + """ + self.psu_status_dict_update() + value = self.psu_status_dict["Temperature"]["Value"] + if value is None: + value = 0 + return round(float(value), 1) + + def get_temperature_high_threshold(self): + """ + Retrieves the high threshold temperature of PSU + + Returns: + A float number, the high threshold temperature of PSU in Celsius + up to nearest thousandth of one degree Celsius, e.g. 30.125 + """ + self.psu_status_dict_update() + value = self.psu_status_dict["Temperature"]["Max"] + if value is None: + value = 0 + return round(float(value), 1) + + def get_voltage_high_threshold(self): + """ + Retrieves the high threshold PSU voltage output + + Returns: + A float number, the high threshold output voltage in volts, + e.g. 12.1 + """ + self.psu_power_dict_update() + value = self.psu_power_dict["Outputs"]["Voltage"]["HighAlarm"] + if value is None: + value = 0 + return round(float(value), 1) + + def get_voltage_low_threshold(self): + """ + Retrieves the low threshold PSU voltage output + + Returns: + A float number, the low threshold output voltage in volts, + e.g. 12.1 + """ + self.psu_power_dict_update() + value = self.psu_power_dict["Outputs"]["Voltage"]["LowAlarm"] + if value is None: + value = 0 + return round(float(value), 1) + + def get_input_voltage(self): + """ + Get the input voltage of the PSU + + Returns: + A float number, the input voltage in volts, + """ + self.psu_status_dict_update() + if self.psu_status_dict["InputStatus"] is False: + value = 0 + else: + self.psu_power_dict_update() + value = self.psu_power_dict["Inputs"]["Voltage"]["Value"] + if value is None: + value = 0 + return round(float(value), 1) + + def get_input_current(self): + """ + Get the input electric current of the PSU + + Returns: + A float number, the input current in amperes, e.g 220.3 + """ + self.psu_status_dict_update() + if self.psu_status_dict["InputStatus"] is False: + value = 0 + else: + self.psu_power_dict_update() + value = self.psu_power_dict["Inputs"]["Current"]["Value"] + if value is None: + value = 0 + return round(float(value), 1) + + def get_input_power(self): + """ + Get the input current energy of the PSU + + Returns: + A float number, the input power in watts, e.g. 302.6 + """ + self.psu_status_dict_update() + if self.psu_status_dict["InputStatus"] is False: + value = 0 + else: + self.psu_power_dict_update() + value = self.psu_power_dict["Inputs"]["Power"]["Value"] + if value is None: + value = 0 + return round(float(value), 1) + + def get_revision(self): + """ + Retrieves the hardware revision of the device + + Returns: + string: Revision value of device + """ + self.psu_dict_update() + return self.psu_dict["HW"] + + def get_vendor(self): + """ + Retrieves the vendor name of the psu + + Returns: + string: Vendor name of psu + """ + self.psu_dict_update() + return self.psu_dict["VENDOR"] + + def get_maximum_supplied_power(self): + """ + Retrieves the maximum supplied power by PSU + + Returns: + A float number, the maximum power output in Watts. + e.g. 1200.1 + """ + return False + + def get_thermal(self, index): + """ + Retrieves thermal unit represented by (0-based) index + + Args: + index: An integer, the index (0-based) of the thermal to + retrieve + + Returns: + An object dervied from ThermalBase representing the specified thermal + """ + return False diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/sfp.py b/platform/broadcom/sonic-platform-modules-ragile/common/sonic_platform/sfp.py similarity index 74% rename from platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/sfp.py rename to platform/broadcom/sonic-platform-modules-ragile/common/sonic_platform/sfp.py index c1d4cb998a6e..4667d3efcd7c 100644 --- a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/sfp.py +++ b/platform/broadcom/sonic-platform-modules-ragile/common/sonic_platform/sfp.py @@ -27,10 +27,10 @@ # } # } # } -# ver 2.0 - rg_plat: -# "presence_path": "/xx/rg_plat/xx[port_id]/present" +# ver 2.0 - wb_plat: +# "presence_path": "/xx/wb_plat/xx[port_id]/present" # "eeprom_path": "/sys/bus/i2c/devices/i2c-[bus]/[bus]-0050/eeprom" -# "reset_path": "/xx/rg_plat/xx[port_id]/reset" +# "reset_path": "/xx/wb_plat/xx[port_id]/reset" ############################################################################# import sys import time @@ -38,52 +38,21 @@ import traceback from abc import abstractmethod +configfile_pre = "/usr/local/bin/" +sys.path.append(configfile_pre) + try: - import os + from platform_intf import * from sonic_platform_base.sonic_xcvr.sfp_optoe_base import SfpOptoeBase - from .sfp_config import * - -except ImportError as e: - raise ImportError (str(e) + "- required module not found") - -LOG_DEBUG_LEVEL = 1 -LOG_WARNING_LEVEL = 2 -LOG_ERROR_LEVEL = 3 - -CONFIG_DB_PATH = "/etc/sonic/config_db.json" - -def getonieplatform(path): - if not os.path.isfile(path): - return "" - machine_vars = {} - with open(path) as machine_file: - for line in machine_file: - tokens = line.split('=') - if len(tokens) < 2: - continue - machine_vars[tokens[0]] = tokens[1].strip() - return machine_vars.get("onie_platform") - -def getplatform_config_db(): - if not os.path.isfile(CONFIG_DB_PATH): - return "" - val = os.popen("sonic-cfggen -j %s -v DEVICE_METADATA.localhost.platform" % CONFIG_DB_PATH).read().strip() - if len(val) <= 0: - return "" - else: - return val - -def getplatform_name(): - if os.path.isfile('/host/machine.conf'): - return getonieplatform('/host/machine.conf') - elif os.path.isfile('/usr/share/sonic/hwsku/machine.conf'): - return getonieplatform('/usr/share/sonic/hwsku/machine.conf') - else: - return getplatform_config_db() - -def get_sfp_config(): - dev = getplatform_name() - return cust_sfp_cfg.get(dev, None) + from plat_hal.baseutil import baseutil + +except ImportError as error: + raise ImportError(str(error) + "- required module not found") from error + +LOG_DEBUG_LEVEL = 1 +LOG_WARNING_LEVEL = 2 +LOG_ERROR_LEVEL = 3 + class Sfp(SfpOptoeBase): @@ -92,10 +61,10 @@ class Sfp(SfpOptoeBase): OPTOE_DRV_TYPE3 = 3 # index must start at 1 - def __init__(self, index, a=None, b=None): + def __init__(self, index): SfpOptoeBase.__init__(self) self.sfp_type = None - sfp_config = get_sfp_config() + sfp_config = baseutil.get_config().get("sfps", None) self.log_level_config = sfp_config.get("log_level", LOG_WARNING_LEVEL) # Init instance of SfpCust ver = sfp_config.get("ver", None) @@ -127,9 +96,10 @@ def get_transceiver_info(self): try: if transceiver_info["vendor_rev"] is not None: transceiver_info["hardware_rev"] = transceiver_info["vendor_rev"] - return transceiver_info - except Exception as e: + except BaseException: print(traceback.format_exc()) + return None + return transceiver_info def reset(self): if self.get_presence() is False: @@ -161,7 +131,7 @@ def get_lpmode(self): self._sfplog(LOG_WARNING_LEVEL, 'SFP does not support lpmode') return False - #implement in future + # implement in future return False @@ -174,14 +144,12 @@ def set_lpmode(self, lpmode): if self.sfp_type == 'QSFP-DD': return SfpOptoeBase.set_lpmode(self, lpmode) - elif self.sfp_type == 'QSFP': + if self.sfp_type == 'QSFP': if lpmode: return self._xcvr_api.set_power_override(True, lpmode) - else: - return self._xcvr_api.set_power_override(False, lpmode) - else: - self._sfplog(LOG_WARNING_LEVEL, 'SFP does not support lpmode') - return False + return self._xcvr_api.set_power_override(False, lpmode) + self._sfplog(LOG_WARNING_LEVEL, 'SFP does not support lpmode') + return False def set_optoe_write_max(self, write_max): """ @@ -189,7 +157,6 @@ def set_optoe_write_max(self, write_max): so override it as NotImplemented """ self._sfplog(LOG_DEBUG_LEVEL, "set_optoe_write_max NotImplemented") - pass def refresh_xcvr_api(self): """ @@ -199,18 +166,17 @@ def refresh_xcvr_api(self): class_name = self._xcvr_api.__class__.__name__ optoe_type = None # set sfp_type - if (class_name == 'CmisApi'): + if 'CmisApi' in class_name: self.sfp_type = 'QSFP-DD' optoe_type = self.OPTOE_DRV_TYPE3 - elif (class_name == 'Sff8472Api'): + elif 'Sff8472Api' in class_name: self.sfp_type = 'SFP' optoe_type = self.OPTOE_DRV_TYPE2 - elif (class_name == 'Sff8636Api' or class_name == 'Sff8436Api'): + elif ('Sff8636Api' in class_name or 'Sff8436Api' in class_name): self.sfp_type = 'QSFP' optoe_type = self.OPTOE_DRV_TYPE1 - + # set optoe driver if optoe_type is not None: - # set optoe driver self._sfp_api.set_optoe_type(optoe_type) def _sfplog(self, log_level, msg): @@ -225,31 +191,22 @@ def _sfplog(self, log_level, msg): syslog.syslog(syslog.LOG_ERR, msg) syslog.closelog() - except Exception as e: + except BaseException: print(traceback.format_exc()) + class SfpCust(): def __init__(self, index): self.eeprom_path = None self._init_config(index) def _init_config(self, index): - sfp_config = get_sfp_config() + sfp_config = baseutil.get_config().get("sfps", None) self.log_level_config = sfp_config.get("log_level", LOG_WARNING_LEVEL) self._port_id = index self.eeprom_retry_times = sfp_config.get("eeprom_retry_times", 0) self.eeprom_retry_break_sec = sfp_config.get("eeprom_retry_break_sec", 0) - def combine_format_str(self, str, key): - count_format = str.count('%') - if count_format > 0: - args_k = [] - for i in range(count_format): - args_k.append(key) - return str % (tuple(args_k)) - else: - return str - def _get_eeprom_path(self): return self.eeprom_path or None @@ -266,18 +223,15 @@ def read_eeprom(self, offset, num_bytes): # temporary solution for a sonic202111 bug if len(result) < num_bytes: result = result[::-1].zfill(num_bytes)[::-1] - if result != None: + if result is not None: return bytearray(result) - else: - time.sleep(self.eeprom_retry_break_sec) - continue + time.sleep(self.eeprom_retry_break_sec) + continue - except Exception as e: + except BaseException: self._sfplog(LOG_ERROR_LEVEL, traceback.format_exc()) - return None - def write_eeprom(self, offset, num_bytes, write_buffer): try: for i in range(self.eeprom_retry_times): @@ -288,13 +242,12 @@ def write_eeprom(self, offset, num_bytes, write_buffer): break return ret - - except Exception as e: + except BaseException: self._sfplog(LOG_ERROR_LEVEL, traceback.format_exc()) - + return False @abstractmethod - def set_optoe_type(self, class_name): + def set_optoe_type(self, optoe_type): pass @abstractmethod @@ -331,15 +284,15 @@ def _sfplog(self, log_level, msg): syslog.syslog(syslog.LOG_ERR, msg) syslog.closelog() - except Exception as e: + except BaseException: print(traceback.format_exc()) + class SfpV1(SfpCust): def _init_config(self, index): super()._init_config(index) - sfp_config = get_sfp_config() - # init presence path + sfp_config = baseutil.get_config().get("sfps", None) self.presence_cpld = sfp_config.get("presence_cpld", None) self.presence_val_is_present = sfp_config.get("presence_val_is_present", 0) self._sfplog(LOG_DEBUG_LEVEL, "Done init presence path") @@ -356,16 +309,20 @@ def get_presence(self): try: dev_id, offset, offset_bit = self._get_sfp_cpld_info(self.presence_cpld) ret, info = platform_reg_read(0, dev_id, offset, 1) - return (info[0] & (1 << offset_bit) == self.presence_val_is_present) - except Exception as err: + if (ret is False + or info is None): + return False + return info[0] & (1 << offset_bit) == self.presence_val_is_present + except BaseException: self._sfplog(LOG_ERROR_LEVEL, traceback.format_exc()) + return False def read_eeprom(self, offset, num_bytes): try: for i in range(self.eeprom_retry_times): ret, info = platform_sfp_read(self._port_id, offset, num_bytes) if (ret is False - or info is None): + or info is None): time.sleep(self.eeprom_retry_break_sec) continue eeprom_raw = [] @@ -377,7 +334,7 @@ def read_eeprom(self, offset, num_bytes): if len(eeprom_raw) < num_bytes: eeprom_raw = eeprom_raw[::-1].zfill(num_bytes)[::-1] return bytearray(eeprom_raw) - except Exception as e: + except BaseException: self._sfplog(LOG_ERROR_LEVEL, traceback.format_exc()) return None @@ -391,18 +348,19 @@ def write_eeprom(self, offset, num_bytes, write_buffer): else: val_list.append(write_buffer) ret, info = platform_sfp_write(self._port_id, offset, val_list) - if ret is False: + if (ret is False + or info is None): time.sleep(self.eeprom_retry_break_sec) continue return True - except Exception as e: + except BaseException: self._sfplog(LOG_ERROR_LEVEL, traceback.format_exc()) return False def set_optoe_type(self, optoe_type): ret, info = platform_get_optoe_type(self._port_id) - if info != optoe_type: + if ret is True and info != optoe_type: try: ret, _ = platform_set_optoe_type(self._port_id, optoe_type) except Exception as err: @@ -432,7 +390,7 @@ def set_reset(self, reset): self._sfplog(LOG_ERROR_LEVEL, "platform_reg_write error!") return False - except Exception as err: + except BaseException: self._sfplog(LOG_ERROR_LEVEL, traceback.format_exc()) return False @@ -454,45 +412,39 @@ def _get_sfp_cpld_info(self, cpld_config): return dev_id, offset, offset_bit + class SfpV2(SfpCust): def _init_config(self, index): super()._init_config(index) - sfp_config = get_sfp_config() - # init eeprom path + sfp_config = baseutil.get_config().get("sfps", None) eeprom_path_config = sfp_config.get("eeprom_path", None) eeprom_path_key = sfp_config.get("eeprom_path_key")[self._port_id - 1] - self.eeprom_path = self.combine_format_str(eeprom_path_config, eeprom_path_key) + self.eeprom_path = None if eeprom_path_config is None else eeprom_path_config % ( + eeprom_path_key, eeprom_path_key) self._sfplog(LOG_DEBUG_LEVEL, "Done init eeprom path: %s" % self.eeprom_path) # init presence path - presence_path_config = sfp_config.get("presence_path", None) - presence_path_key = sfp_config.get("presence_path_key")[self._port_id - 1] - self.presence_path = self.combine_format_str(presence_path_config, presence_path_key) + self.presence_path = None if sfp_config.get("presence_path", + None) is None else sfp_config.get("presence_path") % self._port_id self.presence_val_is_present = sfp_config.get("presence_val_is_present", 0) self._sfplog(LOG_DEBUG_LEVEL, "Done init presence path: %s" % self.presence_path) # init optoe driver path - optoe_driver_path_config = sfp_config.get("optoe_driver_path", None) + optoe_driver_path = sfp_config.get("optoe_driver_path", None) optoe_driver_key = sfp_config.get("optoe_driver_key")[self._port_id - 1] - self.dev_class_path = self.combine_format_str(optoe_driver_path_config, optoe_driver_key) + self.dev_class_path = None if optoe_driver_path is None else optoe_driver_path % ( + optoe_driver_key, optoe_driver_key) self._sfplog(LOG_DEBUG_LEVEL, "Done init optoe driver path: %s" % self.dev_class_path) - # init txdisable path - txdisable_path_config = sfp_config.get("txdisable_path", None) - if txdisable_path_config is not None: - txdisable_path_key = sfp_config.get("txdisable_path_key")[self._port_id - 1] - self.txdisable_path = self.combine_format_str(txdisable_path_config, txdisable_path_key) - self.txdisable_val_is_on = sfp_config.get("txdisable_val_is_on", 0) - self._sfplog(LOG_DEBUG_LEVEL, "Done init optoe driver path: %s" % self.dev_class_path) - # init reset path - reset_path_config = sfp_config.get("reset_path", None) - if reset_path_config is not None: - reset_path_key = sfp_config.get("reset_path_key")[self._port_id - 1] - self.reset_path = self.combine_format_str(reset_path_config, reset_path_key) - self.reset_val_is_on = sfp_config.get("reset_val_is_on", 0) - self._sfplog(LOG_DEBUG_LEVEL, "Done init reset path: %s" % self.reset_path) + self.reset_path = None if sfp_config.get( + "reset_path", + None) is None else sfp_config.get( + "reset_path", + None) % self._port_id + self.reset_val_is_reset = sfp_config.get("reset_val_is_reset", 0) + self._sfplog(LOG_DEBUG_LEVEL, "Done init reset path: %s" % self.reset_path) def get_presence(self): if self.presence_path is None: @@ -504,8 +456,9 @@ def get_presence(self): if sysfs_data != "": result = int(sysfs_data, 16) return result == self.presence_val_is_present - except Exception as err: + except BaseException: self._sfplog(LOG_ERROR_LEVEL, traceback.format_exc()) + return False def set_reset(self, reset): return True @@ -515,11 +468,13 @@ def set_optoe_type(self, optoe_type): self._sfplog(LOG_ERROR_LEVEL, "dev_class_path is None!") return False try: - dc_file = open(self.dev_class_path, "r+") - dc_file_val = dc_file.read(1) - if int(dc_file_val) != optoe_type: - dc_str = "%s" % str(optoe_type) - dc_file.write(dc_str) - dc_file.close() - except Exception as err: + with open(self.dev_class_path, "r+") as dc_file: + dc_file_val = dc_file.read(1) + if int(dc_file_val) != optoe_type: + dc_str = "%s" % str(optoe_type) + dc_file.write(dc_str) + # dc_file.close() + except BaseException: self._sfplog(LOG_ERROR_LEVEL, traceback.format_exc()) + return False + return True diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/sonic_platform/thermal.py b/platform/broadcom/sonic-platform-modules-ragile/common/sonic_platform/thermal.py new file mode 100644 index 000000000000..4632de3bc1e4 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/sonic_platform/thermal.py @@ -0,0 +1,234 @@ +#!/usr/bin/env python3 + +######################################################################## +# +# Module contains an implementation of SONiC Platform Base API and +# provides the Thermals' information which are available in the platform +# +######################################################################## + + +try: + import time + from sonic_platform_base.thermal_base import ThermalBase +except ImportError as e: + raise ImportError(str(e) + "- required module not found") from e + + +class Thermal(ThermalBase): + + def __init__(self, interface_obj, index): + self.temp_dict = {} + self.temperature_list = [] + self.int_case = interface_obj + self.index = index + self.update_time = 0 + self.temp_id = "TEMP" + str(index) + + def temp_dict_update(self): + local_time = time.time() + if not self.temp_dict or (local_time - self.update_time) >= 1: # update data every 1 seconds + self.update_time = local_time + self.temp_dict = self.int_case.get_monitor_temp_by_id(self.temp_id) + + def get_name(self): + """ + Retrieves the name of the thermal + + Returns: + string: The name of the thermal + """ + self.temp_dict_update() + return self.temp_dict["Api_name"] + + def get_presence(self): + """ + Retrieves the presence of the thermal + + Returns: + bool: True if thermal is present, False if not + """ + return True + + def get_model(self): + """ + Retrieves the model number (or part number) of the Thermal + + Returns: + string: Model/part number of Thermal + """ + return "N/A" + + def get_serial(self): + """ + Retrieves the serial number of the Thermal + + Returns: + string: Serial number of Thermal + """ + return "N/A" + + def get_revision(self): + """ + Retrieves the hardware revision of the device + + Returns: + string: Revision value of device + """ + return "N/A" + + def get_status(self): + """ + Retrieves the operational status of the thermal + + Returns: + A boolean value, True if thermal is operating properly, + False if not + """ + self.temp_dict_update() + if (self.temp_dict["Value"] >= self.temp_dict["High"]) or (self.temp_dict["Value"] <= self.temp_dict["Low"]): + return False + + return True + + def get_position_in_parent(self): + """ + Retrieves 1-based relative physical position in parent device. If the agent cannot determine the parent-relative position + for some reason, or if the associated value of entPhysicalContainedIn is '0', then the value '-1' is returned + Returns: + integer: The 1-based relative physical position in parent device or -1 if cannot determine the position + """ + return -1 + + def is_replaceable(self): + """ + Indicate whether this device is replaceable. + Returns: + bool: True if it is replaceable. + """ + return False + + def get_temperature(self): + """ + Retrieves current temperature reading from thermal + + Returns: + A float number of current temperature in Celsius up to nearest thousandth + of one degree Celsius, e.g. 30.125 + """ + self.temp_dict_update() + value = self.temp_dict["Value"] + if value is None or value == self.int_case.error_ret: + return "N/A" + if len(self.temperature_list) >= 1000: + del self.temperature_list[0] + self.temperature_list.append(float(value)) + return round(float(value), 1) + + def get_high_threshold(self): + """ + Retrieves the high threshold temperature of thermal + + Returns: + A float number, the high threshold temperature of thermal in Celsius + up to nearest thousandth of one degree Celsius, e.g. 30.125 + """ + self.temp_dict_update() + value = self.temp_dict["High"] + if value is None or value == self.int_case.error_ret: + return "N/A" + return round(float(value), 1) + + def get_low_threshold(self): + """ + Retrieves the low threshold temperature of thermal + + Returns: + A float number, the low threshold temperature of thermal in Celsius + up to nearest thousandth of one degree Celsius, e.g. 30.125 + """ + self.temp_dict_update() + value = self.temp_dict["Low"] + if value is None or value == self.int_case.error_ret: + return "N/A" + return round(float(value), 1) + + def set_high_threshold(self, temperature): + """ + Sets the high threshold temperature of thermal + + Args : + temperature: A float number up to nearest thousandth of one degree Celsius, + e.g. 30.125 + + Returns: + A boolean, True if threshold is set successfully, False if not + """ + # not supported + return False + + def set_low_threshold(self, temperature): + """ + Sets the low threshold temperature of thermal + + Args : + temperature: A float number up to nearest thousandth of one degree Celsius, + e.g. 30.125 + + Returns: + A boolean, True if threshold is set successfully, False if not + """ + # not supported + return False + + def get_high_critical_threshold(self): + """ + Retrieves the high critical threshold temperature of thermal + + Returns: + A float number, the high critical threshold temperature of thermal in Celsius + up to nearest thousandth of one degree Celsius, e.g. 30.125 + """ + self.temp_dict_update() + value = self.temp_dict["Max"] + if value is None or value == self.int_case.error_ret: + return "N/A" + return round(float(value), 1) + + def get_low_critical_threshold(self): + """ + Retrieves the low critical threshold temperature of thermal + + Returns: + A float number, the low critical threshold temperature of thermal in Celsius + up to nearest thousandth of one degree Celsius, e.g. 30.125 + """ + self.temp_dict_update() + value = self.temp_dict["Min"] + if value is None or value == self.int_case.error_ret: + return "N/A" + return round(float(value), 1) + + def get_minimum_recorded(self): + """ + Retrieves the minimum recorded temperature of thermal + + Returns: + A float number, the minimum recorded temperature of thermal in Celsius + up to nearest thousandth of one degree Celsius, e.g. 30.125 + """ + if len(self.temperature_list) == 0: + return "N/A" + return round(float(min(self.temperature_list)), 1) + + def get_maximum_recorded(self): + """ + Retrieves the maximum recorded temperature of thermal + + Returns: + A float number, the maximum recorded temperature of thermal in Celsius + up to nearest thousandth of one degree Celsius, e.g. 30.125 + """ + if len(self.temperature_list) == 0: + return "N/A" + return round(float(max(self.temperature_list)), 1) diff --git a/platform/broadcom/sonic-platform-modules-ragile/common/sonic_platform/watchdog.py b/platform/broadcom/sonic-platform-modules-ragile/common/sonic_platform/watchdog.py new file mode 100644 index 000000000000..948337f47a9a --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/common/sonic_platform/watchdog.py @@ -0,0 +1,236 @@ +#!/usr/bin/env python3 + +######################################################################## +# +# +# Abstract base class for implementing a platform-specific class with +# which to interact with a hardware watchdog module in SONiC +# +######################################################################## + +import fcntl +import os +import array + +try: + from sonic_platform_base.watchdog_base import WatchdogBase +except ImportError as error: + raise ImportError(str(error) + "- required module not found") from error + + +# ioctl constants +IO_WRITE = 0x40000000 +IO_READ = 0x80000000 +IO_READ_WRITE = 0xC0000000 +IO_SIZE_INT = 0x00040000 +IO_SIZE_40 = 0x00280000 +IO_TYPE_WATCHDOG = ord('W') << 8 + +WDR_INT = IO_READ | IO_SIZE_INT | IO_TYPE_WATCHDOG +WDR_40 = IO_READ | IO_SIZE_40 | IO_TYPE_WATCHDOG +WDWR_INT = IO_READ_WRITE | IO_SIZE_INT | IO_TYPE_WATCHDOG + +# Watchdog ioctl command +WDIOC_GETSUPPORT = 0 | WDR_40 +WDIOC_GETSTATUS = 1 | WDR_INT +WDIOC_GETBOOTSTATUS = 2 | WDR_INT +WDIOC_GETTEMP = 3 | WDR_INT +WDIOC_SETOPTIONS = 4 | WDR_INT +WDIOC_KEEPALIVE = 5 | WDR_INT +WDIOC_SETTIMEOUT = 6 | WDWR_INT +WDIOC_GETTIMEOUT = 7 | WDR_INT +WDIOC_SETPRETIMEOUT = 8 | WDWR_INT +WDIOC_GETPRETIMEOUT = 9 | WDR_INT +WDIOC_GETTIMELEFT = 10 | WDR_INT + +# Watchdog status constants +WDIOS_DISABLECARD = 0x0001 +WDIOS_ENABLECARD = 0x0002 + +WDT_COMMON_ERROR = -1 +WDT_IDENTITY = "CPLD Watchdog" +WDT_SYSFS_PATH = "/sys/class/watchdog/" + +DEFAULT_TIMEOUT = 180 + + +class Watchdog(WatchdogBase): + """ + Abstract base class for interfacing with a hardware watchdog module + """ + + def __init__(self): + self.watchdog, self.wdt_main_dev_name = self._get_wdt() + self.status_path = "/sys/class/watchdog/%s/status" % self.wdt_main_dev_name + self.state_path = "/sys/class/watchdog/%s/state" % self.wdt_main_dev_name + self.timeout_path = "/sys/class/watchdog/%s/timeout" % self.wdt_main_dev_name + # Set default value + self._disable() + self.armed = False + self.timeout = self._gettimeout() + + def _is_wd_main(self, dev): + """ + Checks watchdog identity + """ + identity = self._read_file( + "{}/{}/identity".format(WDT_SYSFS_PATH, dev)) + return identity == WDT_IDENTITY + + def _get_wdt(self): + """ + Retrieves watchdog device + """ + wdt_main_dev_list = [dev for dev in os.listdir( + "/dev/") if dev.startswith("watchdog") and self._is_wd_main(dev)] + if not wdt_main_dev_list: + return None + wdt_main_dev_name = wdt_main_dev_list[0] + watchdog_device_path = "/dev/{}".format(wdt_main_dev_name) + watchdog = os.open(watchdog_device_path, os.O_RDWR) + return watchdog, wdt_main_dev_name + + def _read_file(self, file_path): + """ + Read text file + """ + try: + with open(file_path, "r") as fd: + txt = fd.read() + except IOError: + return WDT_COMMON_ERROR + return txt.strip() + + def _enable(self): + """ + Turn on the watchdog timer + """ + req = array.array('h', [WDIOS_ENABLECARD]) + fcntl.ioctl(self.watchdog, WDIOC_SETOPTIONS, req, False) + + def _disable(self): + """ + Turn off the watchdog timer + """ + req = array.array('h', [WDIOS_DISABLECARD]) + fcntl.ioctl(self.watchdog, WDIOC_SETOPTIONS, req, False) + + def _keepalive(self): + """ + Keep alive watchdog timer + """ + fcntl.ioctl(self.watchdog, WDIOC_KEEPALIVE) + + def _settimeout(self, seconds): + """ + Set watchdog timer timeout + @param seconds - timeout in seconds + @return is the actual set timeout + """ + req = array.array('I', [seconds]) + fcntl.ioctl(self.watchdog, WDIOC_SETTIMEOUT, req, True) + return int(req[0]) + + def _gettimeout(self): + """ + Get watchdog timeout + @return watchdog timeout + """ + req = array.array('I', [0]) + fcntl.ioctl(self.watchdog, WDIOC_GETTIMEOUT, req, True) + + return int(req[0]) + + def _gettimeleft(self): + """ + Get time left before watchdog timer expires + @return time left in seconds + """ + req = array.array('I', [0]) + fcntl.ioctl(self.watchdog, WDIOC_GETTIMELEFT, req, True) + + return int(req[0]) + + def arm(self, seconds): + """ + Arm the hardware watchdog with a timeout of seconds. + If the watchdog is currently armed, calling this function will + simply reset the timer to the provided value. If the underlying + hardware does not support the value provided in , this + method should arm the watchdog with the *next greater* available + value. + + Returns: + An integer specifying the *actual* number of seconds the watchdog + was armed with. On failure returns -1. + """ + ret = WDT_COMMON_ERROR + if seconds < 0: + return ret + + try: + if self.timeout != seconds: + self.timeout = self._settimeout(seconds) + if self.armed: + self._keepalive() + else: + self._settimeout(seconds) + self._enable() + self.armed = True + ret = self.timeout + except IOError: + pass + + return ret + + def disarm(self): + """ + Disarm the hardware watchdog + + Returns: + A boolean, True if watchdog is disarmed successfully, False if not + """ + disarmed = False + if self.is_armed(): + try: + self._disable() + self.armed = False + disarmed = True + except IOError: + pass + + return disarmed + + def is_armed(self): + """ + Retrieves the armed state of the hardware watchdog. + + Returns: + A boolean, True if watchdog is armed, False if not + """ + return self.armed + + def get_remaining_time(self): + """ + If the watchdog is armed, retrieve the number of seconds remaining on + the watchdog timer + + Returns: + An integer specifying the number of seconds remaining on thei + watchdog timer. If the watchdog is not armed, returns -1. + """ + timeleft = WDT_COMMON_ERROR + + if self.armed: + try: + timeleft = self._gettimeleft() + except IOError: + pass + + return timeleft + + def __del__(self): + """ + Close watchdog + """ + os.close(self.watchdog) diff --git a/platform/broadcom/sonic-platform-modules-ragile/debian/compat b/platform/broadcom/sonic-platform-modules-ragile/debian/compat index 45a4fb75db86..f599e28b8ab0 100755 --- a/platform/broadcom/sonic-platform-modules-ragile/debian/compat +++ b/platform/broadcom/sonic-platform-modules-ragile/debian/compat @@ -1 +1 @@ -8 +10 diff --git a/platform/broadcom/sonic-platform-modules-ragile/debian/control b/platform/broadcom/sonic-platform-modules-ragile/debian/control index 795c8219a61e..ae30aee8c0b5 100755 --- a/platform/broadcom/sonic-platform-modules-ragile/debian/control +++ b/platform/broadcom/sonic-platform-modules-ragile/debian/control @@ -1,18 +1,18 @@ Source: sonic-ragile-platform-modules Section: main Priority: extra -Maintainer: support +Maintainer: support Standards-Version: 3.9.3 Package: platform-modules-ragile-ra-b6510-48v8c Architecture: amd64 Description: kernel modules for platform devices such as fan, led, sfp -Package: platform-modules-ragile-ra-b6910-64c +Package: platform-modules-ragile-ra-b6510-32c Architecture: amd64 Description: kernel modules for platform devices such as fan, led, sfp -Package: platform-modules-ragile-ra-b6510-32c +Package: platform-modules-ragile-ra-b6910-64c Architecture: amd64 Description: kernel modules for platform devices such as fan, led, sfp diff --git a/platform/broadcom/sonic-platform-modules-ragile/debian/copyright b/platform/broadcom/sonic-platform-modules-ragile/debian/copyright index 1e4fc20a1672..676cdeec726b 100755 --- a/platform/broadcom/sonic-platform-modules-ragile/debian/copyright +++ b/platform/broadcom/sonic-platform-modules-ragile/debian/copyright @@ -1,5 +1,4 @@ Copyright (C) 2016 Microsoft, Inc -Copyright (C) 2018 Ragile Network Corporation This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License diff --git a/platform/broadcom/sonic-platform-modules-ragile/debian/platform-modules-ragile-ra-b6510-48v8c.install b/platform/broadcom/sonic-platform-modules-ragile/debian/platform-modules-ragile-ra-b6510-48v8c.install index 568190dca044..a63d409ace41 100644 --- a/platform/broadcom/sonic-platform-modules-ragile/debian/platform-modules-ragile-ra-b6510-48v8c.install +++ b/platform/broadcom/sonic-platform-modules-ragile/debian/platform-modules-ragile-ra-b6510-48v8c.install @@ -1 +1 @@ -ra-b6510-48v8c/scripts/pddf_post_driver_install.sh /usr/local/bin +ra-b6510-48v8c/modules/sonic_platform-1.0-py3-none-any.whl /usr/share/sonic/device/x86_64-ragile_ra-b6510-48v8c-r0 diff --git a/platform/broadcom/sonic-platform-modules-ragile/debian/platform-modules-ragile-ra-b6510-48v8c.postinst b/platform/broadcom/sonic-platform-modules-ragile/debian/platform-modules-ragile-ra-b6510-48v8c.postinst index 0d9d6a34d2a5..a8132f4f65a9 100755 --- a/platform/broadcom/sonic-platform-modules-ragile/debian/platform-modules-ragile-ra-b6510-48v8c.postinst +++ b/platform/broadcom/sonic-platform-modules-ragile/debian/platform-modules-ragile-ra-b6510-48v8c.postinst @@ -7,11 +7,4 @@ if [ -e /boot/System.map-${kernel_version} ]; then depmod -a -F /boot/System.map-${kernel_version} ${kernel_version} || true fi -# enable platform-service -depmod -a -# systemctl enable platform-modules-ra-b6510-48v8c.service -# systemctl start platform-modules-ra-b6510-48v8c.service -systemctl enable pddf-platform-init.service -systemctl start pddf-platform-init.service - #DEBHELPER# diff --git a/platform/broadcom/sonic-platform-modules-ragile/debian/rule-ragile.mk b/platform/broadcom/sonic-platform-modules-ragile/debian/rule-ragile.mk deleted file mode 100755 index 6620b8762f86..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/debian/rule-ragile.mk +++ /dev/null @@ -1,8 +0,0 @@ -currentdir = $(shell pwd) - -MODULE_DIRS := ra-b6510-48v8c -MODULE_DIRS += ra-b6910-64c -MODULE_DIRS += ra-b6510-32c -MODULE_DIRS += ra-b6920-4s - -export MODULE_DIRS diff --git a/platform/broadcom/sonic-platform-modules-ragile/debian/rule.mk b/platform/broadcom/sonic-platform-modules-ragile/debian/rule.mk new file mode 100644 index 000000000000..912668c199b3 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/debian/rule.mk @@ -0,0 +1,5 @@ +currentdir = $(shell pwd) + +MODULE_DIRS := ra-b6510-48v8c + +export MODULE_DIRS diff --git a/platform/broadcom/sonic-platform-modules-ragile/debian/rules b/platform/broadcom/sonic-platform-modules-ragile/debian/rules index 7e5aa13b2e04..0177d5072684 100755 --- a/platform/broadcom/sonic-platform-modules-ragile/debian/rules +++ b/platform/broadcom/sonic-platform-modules-ragile/debian/rules @@ -6,33 +6,27 @@ KERNEL_SRC := /lib/modules/$(KVERSION) MOD_SRC_DIR:= $(shell pwd) KBUILD_OUTPUT=$(KERNEL_SRC)/build -LIB_DIR = usr/lib/python3.7/dist-packages +LIB_DIR = usr/lib/python3/dist-packages CUSTOM_RULES_DIR := $(shell pwd)/debian -PLATFORM_PREFIX = "x86_64-ragile" -PLATFORM_VER = "r0" -BDIST_DIR = "dist" -BDIST_TARGET = "bdist_t" +export INSTALL_MOD_DIR top_srcdir KVERSION KERNEL_SRC CC KBUILD_OUTPUT CUSTOM_RULES_DIR -export INSTALL_MOD_DIR top_srcdir KVERSION KERNEL_SRC CC KBUILD_OUTPUT +include $(CUSTOM_RULES_DIR)/rule.mk -include $(CUSTOM_RULES_DIR)/rule-ragile.mk - -#all products need common +#all product need common COMPILE_DIRS = $(MODULE_DIRS) clean_dirs = $(MODULE_DIRS) clean_dirs += common -custom_clean_dirs := $(addprefix _clean_,$(clean_dirs) ) - +complie_clean_dirs := $(addprefix _clean_,$(clean_dirs) ) %: dh $@ -build: $(COMPILE_DIRS) +build: COMPILE_WHL @echo "build success" -$(custom_clean_dirs): +$(complie_clean_dirs): $(MAKE) -C $(patsubst _clean_%,%,$@) clean common_build : @@ -42,29 +36,32 @@ $(COMPILE_DIRS): common_build $(MAKE) -C $(MOD_SRC_DIR)/$@ dh_testdir dh_installdirs - # - # wheel pcakage - @cp -r \ - $(MOD_SRC_DIR)/common/lib/rgutil \ - $(MOD_SRC_DIR)/common/lib/eepromutil \ - $(MOD_SRC_DIR)/$@/; \ - cd $(MOD_SRC_DIR)/$@; \ - python3 setup.py bdist_wheel --bdist-dir $(BDIST_DIR) -d $(BDIST_TARGET); \ - mkdir -p build/usr/share/sonic/device/$(PLATFORM_PREFIX)_$@-$(PLATFORM_VER); \ - mkdir -p build/usr/share/sonic/device/$(PLATFORM_PREFIX)_$@-$(PLATFORM_VER)/pddf; \ - cp $(BDIST_TARGET)/*.whl build/usr/share/sonic/device/$(PLATFORM_PREFIX)_$@-$(PLATFORM_VER); \ - cp $(BDIST_TARGET)/*.whl build/usr/share/sonic/device/$(PLATFORM_PREFIX)_$@-$(PLATFORM_VER)/pddf/; \ - cd $(MOD_SRC_DIR); \ - rm -rf \ - $(MOD_SRC_DIR)/$@/rgutil \ - $(MOD_SRC_DIR)/$@/eepromutil \ - $(MOD_SRC_DIR)/$@/$(BDIST_TARGET) - - cp -r $(MOD_SRC_DIR)/common/build/* debian/platform-modules-ragile-$@/ - cp -r $(MOD_SRC_DIR)/$@/build/* debian/platform-modules-ragile-$@/ + cp -r $(MOD_SRC_DIR)/common/build/* debian/platform-modules-ragile-$@/; \ + cp -r $(MOD_SRC_DIR)/$@/build/* debian/platform-modules-ragile-$@/; \ + +COMPILE_WHL: $(COMPILE_DIRS) + @(for mod in $(MODULE_DIRS); do \ + cd $(MOD_SRC_DIR)/$${mod}; \ + cp -r $(MOD_SRC_DIR)/common/lib/plat_hal $(MOD_SRC_DIR)/$${mod}/; \ + cp -r $(MOD_SRC_DIR)/common/lib/wbutil $(MOD_SRC_DIR)/$${mod}/; \ + cp -r $(MOD_SRC_DIR)/common/lib/eepromutil $(MOD_SRC_DIR)/$${mod}/; \ + cp -r $(MOD_SRC_DIR)/common/sonic_platform $(MOD_SRC_DIR)/$${mod}/; \ + cp $(MOD_SRC_DIR)/common/script/hal_pltfm.py $(MOD_SRC_DIR)/$${mod}/hal_pltfm.py; \ + cp $(MOD_SRC_DIR)/common/script/platform_util.py $(MOD_SRC_DIR)/$${mod}/platform_util.py; \ + cp $(MOD_SRC_DIR)/common/script/platform_intf.py $(MOD_SRC_DIR)/$${mod}/platform_intf.py; \ + python3 setup.py bdist_wheel -d $(MOD_SRC_DIR)/$${mod}/modules; \ + rm -rf $(MOD_SRC_DIR)/$${mod}/plat_hal; \ + rm -rf $(MOD_SRC_DIR)/$${mod}/wbutil; \ + rm -rf $(MOD_SRC_DIR)/$${mod}/eepromutil; \ + rm -rf $(MOD_SRC_DIR)/$${mod}/sonic_platform; \ + rm -rf $(MOD_SRC_DIR)/$${mod}/hal_pltfm.py; \ + rm -rf $(MOD_SRC_DIR)/$${mod}/platform_intf.py; \ + rm -rf $(MOD_SRC_DIR)/$${mod}/platform_util.py; \ + cd $(MOD_SRC_DIR); \ + done) binary: binary-indep - @echo "======================================================" + @echo "=======================================================" binary-indep: # Resuming debhelper scripts @@ -87,7 +84,7 @@ override_dh_usrlocal: override_dh_pysupport: -clean: $(custom_clean_dirs) +clean: $(complie_clean_dirs) dh_testdir dh_testroot dh_clean diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/LICENSE b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/LICENSE deleted file mode 100755 index d37122689f3e..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/LICENSE +++ /dev/null @@ -1,15 +0,0 @@ -Copyright (C) 2016 Microsoft, Inc -Copyright (C) 2018 Ragile Network Corporation -This program is free software; you can redistribute it and/or -modify it under the terms of the GNU General Public License -as published by the Free Software Foundation; either version 2 -of the License, or (at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/MAINTAINERS b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/MAINTAINERS deleted file mode 100755 index ec8222405085..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/MAINTAINERS +++ /dev/null @@ -1,5 +0,0 @@ -# See the SONiC project governance document for more information - -Name = "support" -Email = "support@ragile.com" -Mailinglist = sonicproject@googlegroups.com diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/Makefile b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/Makefile old mode 100755 new mode 100644 index bc2010b78e3f..1b84abef410a --- a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/Makefile +++ b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/Makefile @@ -5,13 +5,9 @@ EXTRA_CFLAGS+= -Wall SUB_BUILD_DIR = $(PWD)/build INSTALL_DIR = $(SUB_BUILD_DIR)/$(KERNEL_SRC)/$(INSTALL_MOD_DIR) INSTALL_SCRIPT_DIR = $(SUB_BUILD_DIR)/usr/local/bin -INSTALL_SERVICE_DIR = $(SUB_BUILD_DIR)/lib/systemd/system/ - -KBUILD_EXTRA_SYMBOLS += $(DIR_KERNEL_SRC)/Module.symvers -ifeq "5.10.0" "$(word 1, $(sort 5.10.0 $(KERNEL_VERSION)))" -KBUILD_EXTRA_SYMBOLS += $(PWD)/../../../pddf/i2c/Module.symvers.PDDF -endif -export KBUILD_EXTRA_SYMBOLS +INSTALL_LIB_DIR = $(SUB_BUILD_DIR)/usr/lib/python3/dist-packages +INSTALL_SYSFS_CFG_DIR = $(SUB_BUILD_DIR)/etc/plat_sysfs_cfg +INSTALL_UPGRADE_TEST_DIR = $(SUB_BUILD_DIR)/etc/.upgrade_test all: $(MAKE) -C $(KBUILD_OUTPUT) M=$(DIR_KERNEL_SRC) modules @@ -19,8 +15,12 @@ all: cp -r $(DIR_KERNEL_SRC)/*.ko $(INSTALL_DIR) @if [ ! -d ${INSTALL_SCRIPT_DIR} ]; then mkdir -p ${INSTALL_SCRIPT_DIR} ;fi cp -r $(PWD)/config/* $(INSTALL_SCRIPT_DIR) - @if [ ! -d ${INSTALL_SERVICE_DIR} ]; then mkdir -p ${INSTALL_SERVICE_DIR} ;fi - cp $(PWD)/systemd/*.service $(INSTALL_SERVICE_DIR) + @if [ ! -d ${INSTALL_LIB_DIR} ]; then mkdir -p ${INSTALL_LIB_DIR} ;fi + @if [ -d $(PWD)/hal-config/ ]; then cp -r $(PWD)/hal-config/* ${INSTALL_LIB_DIR} ;fi + @if [ ! -d ${INSTALL_SYSFS_CFG_DIR} ]; then mkdir -p ${INSTALL_SYSFS_CFG_DIR} ;fi + @if [ -d $(PWD)/plat_sysfs_cfg/ ]; then cp -r $(PWD)/plat_sysfs_cfg/* ${INSTALL_SYSFS_CFG_DIR} ;fi + @if [ ! -d ${INSTALL_UPGRADE_TEST_DIR} ]; then mkdir -p ${INSTALL_UPGRADE_TEST_DIR} ;fi + @if [ -d $(PWD)/.upgrade_test/ ]; then cp -r $(PWD)/.upgrade_test/* ${INSTALL_UPGRADE_TEST_DIR} ;fi clean: rm -f ${DIR_KERNEL_SRC}/*.o ${DIR_KERNEL_SRC}/*.ko ${DIR_KERNEL_SRC}/*.mod.c ${DIR_KERNEL_SRC}/.*.cmd rm -f ${DIR_KERNEL_SRC}/Module.markers ${DIR_KERNEL_SRC}/Module.symvers ${DIR_KERNEL_SRC}/modules.order diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/README.md b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/README.md deleted file mode 100755 index 787636c4ad20..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/README.md +++ /dev/null @@ -1 +0,0 @@ -Device drivers for support of ragile platform for the SONiC project diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/config/x86_64_ragile_ra_b6510_48v8c_r0_config.py b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/config/x86_64_ragile_ra_b6510_48v8c_r0_config.py index 5fe30ea12848..66ca2ddb1922 100755 --- a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/config/x86_64_ragile_ra_b6510_48v8c_r0_config.py +++ b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/config/x86_64_ragile_ra_b6510_48v8c_r0_config.py @@ -1,484 +1,1110 @@ #!/usr/bin/python # -*- coding: UTF-8 -*- -from ragilecommon import * -PCA9548START = -1 -PCA9548BUSEND = -2 +from platform_common import * +STARTMODULE = { + "hal_fanctrl": 1, + "hal_ledctrl": 1, + "avscontrol": 1, + "dev_monitor": 1, + "pmon_syslog": 1, + "tty_console": 1, + "macledreset": 1, + "sff_temp_polling": 1, + "generate_airflow": 1, + "reboot_cause": 1, +} + +MAC_LED_RESET = {"pcibus": 8, "slot": 0, "fn": 0, "bar": 0, "offset": 64, "reset": 0x98} + +MANUINFO_CONF = { + "bios": { + "key": "BIOS", + "head": True, + "next": "onie" + }, + "bios_vendor": { + "parent": "bios", + "key": "Vendor", + "cmd": "dmidecode -t 0 |grep Vendor", + "pattern": r".*Vendor", + "separator": ":", + "arrt_index": 1, + }, + "bios_version": { + "parent": "bios", + "key": "Version", + "cmd": "dmidecode -t 0 |grep Version", + "pattern": r".*Version", + "separator": ":", + "arrt_index": 2, + }, + "bios_date": { + "parent": "bios", + "key": "Release Date", + "cmd": "dmidecode -t 0 |grep Release", + "pattern": r".*Release Date", + "separator": ":", + "arrt_index": 3, + }, + "onie": { + "key": "ONIE", + "next": "cpu" + }, + "onie_date": { + "parent": "onie", + "key": "Build Date", + "file": "/host/machine.conf", + "pattern": r"^onie_build_date", + "separator": "=", + "arrt_index": 1, + }, + "onie_version": { + "parent": "onie", + "key": "Version", + "file": "/host/machine.conf", + "pattern": r"^onie_version", + "separator": "=", + "arrt_index": 2, + }, + + "cpu": { + "key": "CPU", + "next": "ssd" + }, + "cpu_vendor": { + "parent": "cpu", + "key": "Vendor", + "cmd": "dmidecode --type processor |grep Manufacturer", + "pattern": r".*Manufacturer", + "separator": ":", + "arrt_index": 1, + }, + "cpu_model": { + "parent": "cpu", + "key": "Device Model", + "cmd": "dmidecode --type processor | grep Version", + "pattern": r".*Version", + "separator": ":", + "arrt_index": 2, + }, + "cpu_core": { + "parent": "cpu", + "key": "Core Count", + "cmd": "dmidecode --type processor | grep \"Core Count\"", + "pattern": r".*Core Count", + "separator": ":", + "arrt_index": 3, + }, + "cpu_thread": { + "parent": "cpu", + "key": "Thread Count", + "cmd": "dmidecode --type processor | grep \"Thread Count\"", + "pattern": r".*Thread Count", + "separator": ":", + "arrt_index": 4, + }, + "ssd": { + "key": "SSD", + "next": "cpld" + }, + "ssd_model": { + "parent": "ssd", + "key": "Device Model", + "cmd": "smartctl -i /dev/sda |grep \"Device Model\"", + "pattern": r".*Device Model", + "separator": ":", + "arrt_index": 1, + }, + "ssd_fw": { + "parent": "ssd", + "key": "Firmware Version", + "cmd": "smartctl -i /dev/sda |grep \"Firmware Version\"", + "pattern": r".*Firmware Version", + "separator": ":", + "arrt_index": 2, + }, + "ssd_user_cap": { + "parent": "ssd", + "key": "User Capacity", + "cmd": "smartctl -i /dev/sda |grep \"User Capacity\"", + "pattern": r".*User Capacity", + "separator": ":", + "arrt_index": 3, + }, + + "cpld": { + "key": "CPLD", + "next": "psu" + }, + + "cpld1": { + "key": "CPLD1", + "parent": "cpld", + "arrt_index": 1, + }, + "cpld1_model": { + "key": "Device Model", + "parent": "cpld1", + "config": "LCMXO3LF-2100C-5BG256C", + "arrt_index": 1, + }, + "cpld1_vender": { + "key": "Vendor", + "parent": "cpld1", + "config": "LATTICE", + "arrt_index": 2, + }, + "cpld1_desc": { + "key": "Description", + "parent": "cpld1", + "config": "CPU_CPLD", + "arrt_index": 3, + }, + "cpld1_version": { + "key": "Firmware Version", + "parent": "cpld1", + "reg": { + "loc": "/dev/port", + "offset": 0x700, + "size": 4 + }, + "callback": "cpld_format", + "arrt_index": 4, + }, + + "cpld2": { + "key": "CPLD2", + "parent": "cpld", + "arrt_index": 2, + }, + "cpld2_model": { + "key": "Device Model", + "parent": "cpld2", + "config": "LCMXO3LF-2100C-5BG256C", + "arrt_index": 1, + }, + "cpld2_vender": { + "key": "Vendor", + "parent": "cpld2", + "config": "LATTICE", + "arrt_index": 2, + }, + "cpld2_desc": { + "key": "Description", + "parent": "cpld2", + "config": "CONNECT_CPLD", + "arrt_index": 3, + }, + "cpld2_version": { + "key": "Firmware Version", + "parent": "cpld2", + "reg": { + "loc": "/dev/port", + "offset": 0x900, + "size": 4 + }, + "callback": "cpld_format", + "arrt_index": 4, + }, + + "cpld3": { + "key": "CPLD3", + "parent": "cpld", + "arrt_index": 3, + }, + "cpld3_model": { + "key": "Device Model", + "parent": "cpld3", + "config": "LCMXO3LF-2100C-5BG256C", + "arrt_index": 1, + }, + "cpld3_vender": { + "key": "Vendor", + "parent": "cpld3", + "config": "LATTICE", + "arrt_index": 2, + }, + "cpld3_desc": { + "key": "Description", + "parent": "cpld3", + "config": "CONNECT_CPLD-FAN", + "arrt_index": 3, + }, + "cpld3_version": { + "key": "Firmware Version", + "parent": "cpld3", + "i2c": { + "bus": "2", + "loc": "0x0d", + "offset": 0, + "size": 4 + }, + "callback": "cpld_format", + "arrt_index": 4, + }, + + "cpld4": { + "key": "CPLD4", + "parent": "cpld", + "arrt_index": 4, + }, + "cpld4_model": { + "key": "Device Model", + "parent": "cpld4", + "config": "LCMXO3LF-2100C-5BG256C", + "arrt_index": 1, + }, + "cpld4_vender": { + "key": "Vendor", + "parent": "cpld4", + "config": "LATTICE", + "arrt_index": 2, + }, + "cpld4_desc": { + "key": "Description", + "parent": "cpld4", + "config": "MAC_CPLD1", + "arrt_index": 3, + }, + "cpld4_version": { + "key": "Firmware Version", + "parent": "cpld4", + "i2c": { + "bus": "8", + "loc": "0x30", + "offset": 0, + "size": 4 + }, + "callback": "cpld_format", + "arrt_index": 4, + }, + + "cpld5": { + "key": "CPLD5", + "parent": "cpld", + "arrt_index": 5, + }, + "cpld5_model": { + "key": "Device Model", + "parent": "cpld5", + "config": "LCMXO3LF-2100C-5BG256C", + "arrt_index": 1, + }, + "cpld5_vender": { + "key": "Vendor", + "parent": "cpld5", + "config": "LATTICE", + "arrt_index": 2, + }, + "cpld5_desc": { + "key": "Description", + "parent": "cpld5", + "config": "MAC_CPLD2", + "arrt_index": 3, + }, + "cpld5_version": { + "key": "Firmware Version", + "parent": "cpld5", + "i2c": { + "bus": "8", + "loc": "0x31", + "offset": 0, + "size": 4 + }, + "callback": "cpld_format", + "arrt_index": 4, + }, + + "psu": { + "key": "PSU", + "next": "fan" + }, + + "psu1": { + "parent": "psu", + "key": "PSU1", + "arrt_index": 1, + }, + "psu1_hw_version": { + "key": "Hardware Version", + "parent": "psu1", + "extra": { + "funcname": "getPsu", + "id": "psu1", + "key": "hw_version" + }, + "arrt_index": 1, + }, + "psu1_fw_version": { + "key": "Firmware Version", + "parent": "psu1", + "config": "NA", + "arrt_index": 2, + }, + + "psu2": { + "parent": "psu", + "key": "PSU2", + "arrt_index": 2, + }, + "psu2_hw_version": { + "key": "Hardware Version", + "parent": "psu2", + "extra": { + "funcname": "getPsu", + "id": "psu2", + "key": "hw_version" + }, + "arrt_index": 1, + }, + "psu2_fw_version": { + "key": "Firmware Version", + "parent": "psu2", + "config": "NA", + "arrt_index": 2, + }, + + "fan": { + "key": "FAN", + "next": "i210" + }, + + "fan1": { + "key": "FAN1", + "parent": "fan", + "arrt_index": 1, + }, + "fan1_hw_version": { + "key": "Hardware Version", + "parent": "fan1", + "extra": { + "funcname": "checkFan", + "id": "fan1", + "key": "hw_version" + }, + "arrt_index": 1, + }, + "fan1_fw_version": { + "key": "Firmware Version", + "parent": "fan1", + "config": "NA", + "arrt_index": 2, + }, + + "fan2": { + "key": "FAN2", + "parent": "fan", + "arrt_index": 2, + }, + "fan2_hw_version": { + "key": "Hardware Version", + "parent": "fan2", + "extra": { + "funcname": "checkFan", + "id": "fan2", + "key": "hw_version" + }, + "arrt_index": 1, + }, + "fan2_fw_version": { + "key": "Firmware Version", + "parent": "fan2", + "config": "NA", + "arrt_index": 2, + }, -RAGILE_CARDID = 0x0000404a -RAGILE_PRODUCTNAME = "RA-B6510-48V8C" + "fan3": { + "key": "FAN3", + "parent": "fan", + "arrt_index": 3, + }, + "fan3_hw_version": { + "key": "Hardware Version", + "parent": "fan3", + "extra": { + "funcname": "checkFan", + "id": "fan3", + "key": "hw_version" + }, + "arrt_index": 1, + }, + "fan3_fw_version": { + "key": "Firmware Version", + "parent": "fan3", + "config": "NA", + "arrt_index": 2, + }, + + "fan4": { + "key": "FAN4", + "parent": "fan", + "arrt_index": 4, + }, + "fan4_hw_version": { + "key": "Hardware Version", + "parent": "fan4", + "extra": { + "funcname": "checkFan", + "id": "fan4", + "key": "hw_version" + }, + "arrt_index": 1, + }, + "fan4_fw_version": { + "key": "Firmware Version", + "parent": "fan4", + "config": "NA", + "arrt_index": 2, + }, + + "i210": { + "key": "NIC", + "next": "fpga" + }, + "i210_model": { + "parent": "i210", + "config": "NA", + "key": "Device Model", + "arrt_index": 1, + }, + "i210_vendor": { + "parent": "i210", + "config": "INTEL", + "key": "Vendor", + "arrt_index": 2, + }, + "i210_version": { + "parent": "i210", + "cmd": "ethtool -i eth0", + "pattern": r"firmware-version", + "separator": ":", + "key": "Firmware Version", + "arrt_index": 3, + }, -STARTMODULE = { - "fancontrol":1, - "avscontrol":1, - "dev_monitor":1 + "fpga": { + "key": "FPGA", + "next": "asic" + }, + "fpga_model": { + "parent": "fpga", + "config": "XC7A15T-2FGG484C", + "key": "Device Model", + "arrt_index": 1, + }, + "fpga_vendor": { + "parent": "fpga", + "config": "XILINX", + "key": "Vendor", + "arrt_index": 2, + }, + "fpga_desc": { + "parent": "fpga", + "config": "NA", + "key": "Description", + "arrt_index": 3, + }, + "fpga_hw_version": { + "parent": "fpga", + "config": "NA", + "key": "Hardware Version", + "arrt_index": 4, + }, + "fpga_fw_version": { + "parent": "fpga", + "pci": { + "bus": 8, + "slot": 0, + "fn": 0, + "bar": 0, + "offset": 0 + }, + "key": "Firmware Version", + "arrt_index": 5, + }, + "fpga_date": { + "parent": "fpga", + "pci": { + "bus": 8, + "slot": 0, + "fn": 0, + "bar": 0, + "offset": 4 + }, + "key": "Build Date", + "arrt_index": 6, + }, + "asic": { + "key": "ASIC", + }, + "sdk_model": { + "parent": "asic", + "cmd": "bcmcmd -t 1 att", + "pattern": r"^Attach", + "regular": r"(?<=\()[^)]*(?=\))", + "key": "Device Model", + "arrt_index": 1, + }, + "sdk_version": { + "parent": "asic", + "cmd": "bcmcmd -t 1 version | grep Release", + "pattern": r".*Release", + "separator": ":", + "key": "SDK Version", + "arrt_index": 2, + }, + "pci_version": { + "parent": "asic", + "cmd": "bcmcmd -t 1 \"pciephy fw version\" |grep \"PCIe FW version\"", + "pattern": r".*PCIe FW version", + "separator": ":", + "key": "PCIe Firmware Version", + "arrt_index": 3, + }, } -i2ccheck_params = {"busend":"i2c-66","retrytime":6} +PMON_SYSLOG_STATUS = { + "polling_time": 3, + "sffs": { + "present": {"path": ["/sys/wb_plat/sff/*/present"], "ABSENT": 0}, + "nochangedmsgflag": 0, + "nochangedmsgtime": 60, + "noprintfirsttimeflag": 1, + "alias": { + "sff1": "Ethernet1", + "sff2": "Ethernet2", + "sff3": "Ethernet3", + "sff4": "Ethernet4", + "sff5": "Ethernet5", + "sff6": "Ethernet6", + "sff7": "Ethernet7", + "sff8": "Ethernet8", + "sff9": "Ethernet9", + "sff10": "Ethernet10", + "sff11": "Ethernet11", + "sff12": "Ethernet12", + "sff13": "Ethernet13", + "sff14": "Ethernet14", + "sff15": "Ethernet15", + "sff16": "Ethernet16", + "sff17": "Ethernet17", + "sff18": "Ethernet18", + "sff19": "Ethernet19", + "sff20": "Ethernet20", + "sff21": "Ethernet21", + "sff22": "Ethernet22", + "sff23": "Ethernet23", + "sff24": "Ethernet24", + "sff25": "Ethernet25", + "sff26": "Ethernet26", + "sff27": "Ethernet27", + "sff28": "Ethernet28", + "sff29": "Ethernet29", + "sff30": "Ethernet30", + "sff31": "Ethernet31", + "sff32": "Ethernet32", + "sff33": "Ethernet33", + "sff34": "Ethernet34", + "sff35": "Ethernet35", + "sff36": "Ethernet36", + "sff37": "Ethernet37", + "sff38": "Ethernet38", + "sff39": "Ethernet39", + "sff40": "Ethernet40", + "sff41": "Ethernet41", + "sff42": "Ethernet42", + "sff43": "Ethernet43", + "sff44": "Ethernet44", + "sff45": "Ethernet45", + "sff46": "Ethernet46", + "sff47": "Ethernet47", + "sff48": "Ethernet48", + "sff49": "Ethernet49", + "sff50": "Ethernet50", + "sff51": "Ethernet51", + "sff52": "Ethernet52", + "sff53": "Ethernet53", + "sff54": "Ethernet54", + "sff55": "Ethernet55", + "sff56": "Ethernet56", + } + }, + "fans": { + "present": {"path": ["/sys/wb_plat/fan/*/present"], "ABSENT": 0}, + "status": [ + {"path": "/sys/wb_plat/fan/%s/motor0/status", 'okval': 1}, + {"path": "/sys/wb_plat/fan/%s/motor1/status", 'okval': 1}, + ], + "nochangedmsgflag": 1, + "nochangedmsgtime": 60, + "noprintfirsttimeflag": 0, + "alias": { + "fan1": "FAN1", + "fan2": "FAN2", + "fan3": "FAN3", + "fan4": "FAN4" + } + }, + "psus": { + "present": {"path": ["/sys/wb_plat/psu/*/present"], "ABSENT": 0}, + "status": [ + {"path": "/sys/wb_plat/psu/%s/output", "okval": 1}, + {"path": "/sys/wb_plat/psu/%s/alert", "okval": 0}, + ], + "nochangedmsgflag": 1, + "nochangedmsgtime": 60, + "noprintfirsttimeflag": 0, + "alias": { + "psu1": "PSU1", + "psu2": "PSU2" + } + } +} + +##################### MAC Voltage adjust#################################### +MAC_DEFAULT_PARAM = [ + { + "name": "mac_core", # AVS name + "type": 1, # 1: used default value, if rov value not in range. 0: do nothing, if rov value not in range + "default": 0x74, # default value, if rov value not in range + "sdkreg": "TOP_AVS_SEL_REG", # SDK register name + "sdktype": 0, # 0: No shift operation required, 1: shift operation required + "macregloc": 24, # Shift right 24 bits + "mask": 0xff, # Use with macregloc + "rov_source": 1, # 0:get rov value from cpld, 1: get rov value from SDK + "cpld_avs": {"bus": 6, "loc": 0x0d, "offset": 0xc3, "gettype": "i2c"}, + "set_avs": { + "loc": "/sys/bus/i2c/devices/7-0064/hwmon/hwmon*/avs0_vout", + "gettype": "sysfs", "formula": "int((%f)*1000000)" + }, + "mac_avs_param": { + 0x08: 0.888, + 0x72: 0.900, + 0x73: 0.894, + 0x74: 0.888, + 0x75: 0.882, + 0x76: 0.875, + 0x77: 0.869, + 0x78: 0.863, + 0x79: 0.857, + 0x7a: 0.850, + 0x7b: 0.844, + 0x7c: 0.838, + 0x7d: 0.832, + 0x7e: 0.825, + 0x7f: 0.819, + 0x80: 0.813, + 0x81: 0.807, + 0x82: 0.800, + 0x83: 0.794, + 0x84: 0.788, + 0x85: 0.782, + 0x86: 0.775, + 0x87: 0.769, + 0x88: 0.763, + 0x89: 0.757, + 0x8A: 0.750 + } + } +] + +BLACKLIST_DRIVERS = [ + {"name": "i2c_i801", "delay": 0}, +] + +DRIVERLISTS = [ + {"name": "wb_i2c_i801", "delay": 0}, + {"name": "wb_gpio_d1500", "delay": 0}, + {"name": "i2c_dev", "delay": 0}, + {"name": "wb_i2c_algo_bit", "delay": 0}, + {"name": "wb_i2c_gpio", "delay": 0}, + {"name": "i2c_mux", "delay": 0}, + {"name": "wb_gpio_device", "delay": 0}, + {"name": "wb_i2c_gpio_device gpio_sda=17 gpio_scl=1 gpio_udelay=2", "delay": 0}, + {"name": "platform_common dfd_my_type=0x404a", "delay": 0}, + {"name": "wb_lpc_drv", "delay": 0}, + {"name": "wb_lpc_drv_device", "delay": 0}, + {"name": "wb_io_dev", "delay": 0}, + {"name": "wb_io_dev_device", "delay": 0}, + {"name": "wb_fpga_pcie", "delay": 0}, + {"name": "wb_pcie_dev", "delay": 0}, + {"name": "wb_pcie_dev_device", "delay": 0}, + {"name": "wb_i2c_dev", "delay": 0}, + {"name": "wb_i2c_ocores", "delay": 0}, + {"name": "wb_i2c_ocores_device", "delay": 0}, + {"name": "wb_i2c_mux_pca9641", "delay": 0}, + {"name": "wb_i2c_mux_pca954x", "delay": 0}, + {"name": "wb_i2c_mux_pca954x_device", "delay": 0}, + {"name": "wb_i2c_dev_device", "delay": 0}, + {"name": "wb_lm75", "delay": 0}, + {"name": "wb_optoe", "delay": 0}, + {"name": "wb_at24", "delay": 0}, + {"name": "wb_mac_bsc", "delay": 0}, + {"name": "wb_pmbus_core", "delay": 0}, + {"name": "wb_isl68137", "delay": 0}, + {"name": "wb_csu550", "delay": 0}, + {"name": "wb_ina3221", "delay": 0}, + {"name": "wb_tps53622", "delay": 0}, + {"name": "firmware_driver_cpld", "delay": 0}, + {"name": "firmware_driver_ispvme", "delay": 0}, + {"name": "firmware_driver_sysfs", "delay": 0}, + {"name": "wb_firmware_upgrade_device", "delay": 0}, + {"name": "plat_dfd", "delay": 0}, + {"name": "plat_switch", "delay": 0}, + {"name": "plat_fan", "delay": 0}, + {"name": "plat_psu", "delay": 0}, + {"name": "plat_sff", "delay": 0}, +] + +DEVICE = [ + {"name": "wb_24c02", "bus": 0, "loc": 0x56}, + {"name": "wb_mac_bsc_td3", "bus": 3, "loc": 0x44}, + # fan + {"name": "wb_24c02", "bus": 16, "loc": 0x50}, + {"name": "wb_24c02", "bus": 17, "loc": 0x50}, + {"name": "wb_24c02", "bus": 18, "loc": 0x50}, + {"name": "wb_24c02", "bus": 19, "loc": 0x50}, + # psu + {"name": "wb_24c02", "bus": 24, "loc": 0x50}, + {"name": "wb_dps550", "bus": 24, "loc": 0x58}, + {"name": "wb_24c02", "bus": 25, "loc": 0x50}, + {"name": "wb_dps550", "bus": 25, "loc": 0x58}, + # temp + {"name": "wb_lm75", "bus": 3, "loc": 0x48}, + {"name": "wb_lm75", "bus": 3, "loc": 0x49}, + {"name": "wb_lm75", "bus": 3, "loc": 0x4a}, + {"name": "wb_lm75", "bus": 3, "loc": 0x4b}, + {"name": "wb_lm75", "bus": 3, "loc": 0x4c}, + # dcdc + {"name": "wb_ina3221", "bus": 7, "loc": 0x40}, + {"name": "wb_ina3221", "bus": 7, "loc": 0x41}, + {"name": "wb_ina3221", "bus": 7, "loc": 0x42}, + {"name": "wb_ina3221", "bus": 7, "loc": 0x43}, + {"name": "wb_tps53622", "bus": 7, "loc": 0x60}, + {"name": "wb_tps53622", "bus": 7, "loc": 0x6c}, + {"name": "wb_isl68127", "bus": 7, "loc": 0x64}, +] + +OPTOE = [ + {"name": "wb_optoe2", "startbus": 32, "endbus": 79}, + {"name": "wb_optoe1", "startbus": 80, "endbus": 87}, +] DEV_MONITOR_PARAM = { "polling_time": 10, "psus": [ { "name": "psu1", - "present": { - "gettype": "i2c", - "bus": 2, - "loc": 0x37, - "offset": 0x51, - "presentbit": 0, - "okval": 0, - }, + "present": {"gettype": "i2c", "bus": 6, "loc": 0x0d, "offset": 0x51, "presentbit": 0, "okval": 0}, "device": [ - { - "id": "psu1pmbus", - "name": "dps550", - "bus": 7, - "loc": 0x58, - "attr": "hwmon", - }, + {"id": "psu1pmbus", "name": "wb_dps550", "bus": 24, "loc": 0x58, "attr": "hwmon"}, + {"id": "psu1frue2", "name": "wb_24c02", "bus": 24, "loc": 0x50, "attr": "eeprom"}, ], }, { "name": "psu2", - "present": { - "gettype": "i2c", - "bus": 2, - "loc": 0x37, - "offset": 0x51, - "presentbit": 4, - "okval": 0, - }, + "present": {"gettype": "i2c", "bus": 6, "loc": 0x0d, "offset": 0x51, "presentbit": 4, "okval": 0}, "device": [ - { - "id": "psu2pmbus", - "name": "dps550", - "bus": 8, - "loc": 0x5B, - "attr": "hwmon", - }, + {"id": "psu2pmbus", "name": "wb_dps550", "bus": 25, "loc": 0x58, "attr": "hwmon"}, + {"id": "psu2frue2", "name": "wb_24c02", "bus": 25, "loc": 0x50, "attr": "eeprom"}, ], }, ], + "fans": [ + { + "name": "fan1", + "present": {"gettype": "i2c", "bus": 2, "loc": 0x0d, "offset": 0x30, "presentbit": 0, "okval": 0}, + "device": [ + {"id": "fan1frue2", "name": "24c02", "bus": 16, "loc": 0x50, "attr": "eeprom"}, + ], + }, + { + "name": "fan2", + "present": {"gettype": "i2c", "bus": 2, "loc": 0x0d, "offset": 0x30, "presentbit": 1, "okval": 0}, + "device": [ + {"id": "fan2frue2", "name": "24c02", "bus": 17, "loc": 0x50, "attr": "eeprom"}, + ], + }, + { + "name": "fan3", + "present": {"gettype": "i2c", "bus": 2, "loc": 0x0d, "offset": 0x30, "presentbit": 2, "okval": 0}, + "device": [ + {"id": "fan3frue2", "name": "24c02", "bus": 18, "loc": 0x50, "attr": "eeprom"}, + ], + }, + { + "name": "fan4", + "present": {"gettype": "i2c", "bus": 2, "loc": 0x0d, "offset": 0x30, "presentbit": 3, "okval": 0}, + "device": [ + {"id": "fan4frue2", "name": "24c02", "bus": 19, "loc": 0x50, "attr": "eeprom"}, + ], + }, + ], + "others": [ + { + "name": "eeprom", + "device": [ + {"id": "eeprom_1", "name": "wb_24c02", "bus": 0, "loc": 0x56, "attr": "eeprom"}, + ], + }, + { + "name": "lm75", + "device": [ + {"id": "lm75_1", "name": "wb_lm75", "bus": 3, "loc": 0x48, "attr": "hwmon"}, + {"id": "lm75_2", "name": "wb_lm75", "bus": 3, "loc": 0x49, "attr": "hwmon"}, + {"id": "lm75_3", "name": "wb_lm75", "bus": 3, "loc": 0x4a, "attr": "hwmon"}, + {"id": "lm75_4", "name": "wb_lm75", "bus": 3, "loc": 0x4b, "attr": "hwmon"}, + {"id": "lm75_5", "name": "wb_lm75", "bus": 3, "loc": 0x4c, "attr": "hwmon"}, + ], + }, + { + "name": "mac_bsc", + "device": [ + {"id": "mac_bsc_1", "name": "wb_mac_bsc_td3", "bus": 3, "loc": 0x44, "attr": "hwmon"}, + ], + }, + { + "name": "ina3221", + "device": [ + {"id": "ina3221_1", "name": "wb_ina3221", "bus": 7, "loc": 0x40, "attr": "hwmon"}, + {"id": "ina3221_2", "name": "wb_ina3221", "bus": 7, "loc": 0x41, "attr": "hwmon"}, + {"id": "ina3221_3", "name": "wb_ina3221", "bus": 7, "loc": 0x42, "attr": "hwmon"}, + {"id": "ina3221_4", "name": "wb_ina3221", "bus": 7, "loc": 0x43, "attr": "hwmon"}, + ], + }, + { + "name": "tps53622", + "device": [ + {"id": "tps53622_1", "name": "wb_tps53622", "bus": 7, "loc": 0x60, "attr": "hwmon"}, + {"id": "tps53622_2", "name": "wb_tps53622", "bus": 7, "loc": 0x6c, "attr": "hwmon"}, + ], + }, + { + "name": "isl68127", + "device": [ + {"id": "isl68127_1", "name": "wb_isl68127", "bus": 7, "loc": 0x64, "attr": "hwmon"}, + ], + } + ], } -fanlevel = { - "tips":["LOW","MEDIUM","HIGH"], - "level":[51,150,255], - "low_speed":[500,7500,17000], - "high_speed":[11000,22500,28500] -} - -# fit with pddf -fanloc = [ - { - "name": "FAN1/FAN2/FAN3/FAN4", - "location": "2-0066/fan1_pwm", - "childfans": [ - {"name": "FAN1", "location": "2-0066/fan1_input"}, - {"name": "FAN2", "location": "2-0066/fan2_input"}, - {"name": "FAN3", "location": "2-0066/fan3_input"}, - {"name": "FAN4", "location": "2-0066/fan4_input"}, - ], - }, +INIT_PARAM_PRE = [ + {"loc": "7-0064/hwmon/hwmon*/avs0_vout_max", "value": "900000"}, + {"loc": "7-0064/hwmon/hwmon*/avs0_vout_min", "value": "750000"}, ] - - - -MONITOR_TEMP_MIN = 38 -MONITOR_K = 11 -MONITOR_MAC_IN = 35 -MONITOR_DEFAULT_SPEED = 0x60 -MONITOR_MAX_SPEED = 0xFF -MONITOR_MIN_SPEED = 0x33 -MONITOR_MAC_ERROR_SPEED = 0XBB -MONITOR_FAN_TOTAL_NUM = 4 -MONITOR_MAC_UP_TEMP = 50 -MONITOR_MAC_LOWER_TEMP = -50 -MONITOR_MAC_MAX_TEMP = 100 - -MONITOR_FALL_TEMP = 4 -MONITOR_MAC_WARNING_THRESHOLD = 100 -MONITOR_OUTTEMP_WARNING_THRESHOLD = 85 -MONITOR_BOARDTEMP_WARNING_THRESHOLD = 85 -MONITOR_CPUTEMP_WARNING_THRESHOLD = 85 -MONITOR_INTEMP_WARNING_THRESHOLD = 70 - -MONITOR_MAC_CRITICAL_THRESHOLD = 105 -MONITOR_OUTTEMP_CRITICAL_THRESHOLD = 90 -MONITOR_BOARDTEMP_CRITICAL_THRESHOLD = 90 -MONITOR_CPUTEMP_CRITICAL_THRESHOLD = 100 -MONITOR_INTEMP_CRITICAL_THRESHOLD = 80 -MONITOR_CRITICAL_NUM = 3 -MONITOR_SHAKE_TIME = 20 -MONITOR_INTERVAL = 60 - -MONITOR_SYS_LED = [ - {"bus":2,"devno":0x33, "addr":0xb2, "yellow":0x03, "red":0x02,"green":0x01}, - {"bus":2,"devno":0x37, "addr":0xb2, "yellow":0x03, "red":0x02,"green":0x01}] - -MONITOR_SYS_FAN_LED =[ - {"bus":2,"devno":0x33, "addr":0xb4, "yellow":0x06, "red":0x02,"green":0x04}, - ] -MONITOR_FANS_LED = [ - {"bus":2,"devno":0x32, "addr":0x23, "green":0x09, "red":0x0a}, - {"bus":2,"devno":0x32, "addr":0x24, "green":0x09, "red":0x0a}, - {"bus":2,"devno":0x32, "addr":0x25, "green":0x09, "red":0x0a}, - {"bus":2,"devno":0x32, "addr":0x26, "green":0x09, "red":0x0a}] - - -CPLDVERSIONS = [ - {"bus":2, "devno":0x33, "name":"MAC BOARD CPLD-A"}, - {"bus":2, "devno":0x35, "name":"MAC BOARD CPLD-B"}, - {"bus":2, "devno":0x37, "name":"CONNECT BOARD CPLD-A"}, - {"bus":0, "devno":0x0d, "name":"CPU BOARD CPLD"}, +INIT_COMMAND_PRE = [ + "i2cset -y -f 6 0x0d 0x91 0x48", + "i2cset -y -f 6 0x0d 0x92 0x01", # MAC_PWR_EN + "i2cset -y -f 6 0x0d 0x94 0x01", # SFF_PWR_EN + "i2cset -y -f 6 0x0d 0xbf 0x01", # enbale tty_console monitor ] -MONITOR_SYS_PSU_LED =[ - {"bus":2,"devno":0x33, "addr":0xb3, "yellow":0x06, "red":0x02,"green":0x04}, - ] - -MONITOR_FAN_STATUS = [ - {'status':'green' , 'minOkNum':4,'maxOkNum':4}, - {'status':'yellow', 'minOkNum':3,'maxOkNum':3}, - {'status':'red' , 'minOkNum':0,'maxOkNum':2}, - ] - -MONITOR_PSU_STATUS = [ - {'status':'green' , 'minOkNum':2,'maxOkNum':2}, - {'status':'yellow', 'minOkNum':1,'maxOkNum':1}, - {'status':'red' , 'minOkNum':0,'maxOkNum':0}, - ] +INIT_PARAM = [] +INIT_COMMAND = [ + "i2cset -y -f 8 0x30 0x60 0x00", # enable txdis[1~8] + "i2cset -y -f 8 0x30 0x61 0x00", # enable txdis[9~16] + "i2cset -y -f 8 0x30 0x62 0x00", # enable txdis[17~24] + "i2cset -y -f 8 0x31 0x60 0x00", # enable txdis[24~32] + "i2cset -y -f 8 0x31 0x61 0x00", # enable txdis[33~40] + "i2cset -y -f 8 0x31 0x62 0x00", # enable txdis[41~48] +] -MONITOR_DEV_STATUS = { - "temperature": [ - {"name":"lm75in", "location":"/sys/bus/i2c/devices/2-0048/hwmon/*/temp1_input"}, - {"name":"lm75out", "location":"/sys/bus/i2c/devices/2-0049/hwmon/*/temp1_input"}, - {"name":"lm75hot", "location":"/sys/bus/i2c/devices/2-004a/hwmon/*/temp1_input"}, - {"name":"cpu", "location":"/sys/class/hwmon/hwmon0"}, - ], - "fans": [ - { - "name":"fan1", - "presentstatus":{"bus":2, "loc":0x37, "offset":0x30, 'bit':0}, - "rollstatus": [ - {"name":"motor1","bus":2, "loc":0x37, "offset":0x31, 'bit':0}, - ] - }, - { - "name":"fan2", - "presentstatus":{"bus":2, "loc":0x37, "offset":0x30, 'bit':1}, - "rollstatus":[ - {"name":"motor1","bus":2, "loc":0x37, "offset":0x31, 'bit':1}, - ] - }, +REBOOT_CAUSE_PARA = { + "reboot_cause_list": [ { - "name":"fan3", - "presentstatus":{"bus":2, "loc":0x37, "offset":0x30, 'bit':2}, - "rollstatus":[ - {"name":"motor1","bus":2, "loc":0x37, "offset":0x31, 'bit':2}, + "name": "otp_switch_reboot", + "monitor_point": {"gettype": "file_exist", "judge_file": "/etc/.otp_switch_reboot_flag", "okval": True}, + "record": [ + {"record_type": "file", "mode": "cover", "log": "Thermal Overload: ASIC, ", + "path": "/etc/sonic/.reboot/.previous-reboot-cause.txt"}, + {"record_type": "file", "mode": "add", "log": "Thermal Overload: ASIC, ", + "path": "/etc/sonic/.reboot/.history-reboot-cause.txt", "file_max_size": 1 * 1024 * 1024} + ], + "finish_operation": [ + {"gettype": "cmd", "cmd": "rm -rf /etc/.otp_switch_reboot_flag"}, ] }, { - "name":"fan4", - "presentstatus":{"bus":2, "loc":0x37, "offset":0x30, 'bit':3}, - "rollstatus":[ - {"name":"motor1","bus":2, "loc":0x37, "offset":0x31, 'bit':3}, + "name": "otp_other_reboot", + "monitor_point": {"gettype": "file_exist", "judge_file": "/etc/.otp_other_reboot_flag", "okval": True}, + "record": [ + {"record_type": "file", "mode": "cover", "log": "Thermal Overload: Other, ", + "path": "/etc/sonic/.reboot/.previous-reboot-cause.txt"}, + {"record_type": "file", "mode": "add", "log": "Thermal Overload: Other, ", + "path": "/etc/sonic/.reboot/.history-reboot-cause.txt", "file_max_size": 1 * 1024 * 1024} + ], + "finish_operation": [ + {"gettype": "cmd", "cmd": "rm -rf /etc/.otp_other_reboot_flag"}, ] }, ], - "psus": [ - {"name":"psu1", "bus":2, "loc":0x37, "offset":0x51, "gettype":"i2c", 'presentbit': 0, 'statusbit':1,'alertbit':2}, - {"name":"psu2", "bus":2, "loc":0x37, "offset":0x51, "gettype":"i2c", 'presentbit': 4, 'statusbit':5,'alertbit':6}, - ], - "mac_temp" : { - "flag" : {"bus":2, "loc":0x33, "offset":0xd4, "gettype":"i2c", 'okbit': 0, 'okval':1}, - "loc" : [ - "2-0035/mac_temp_input", - ], - "try_bcmcmd" : 0, - }, + "other_reboot_cause_record": [ + {"record_type": "file", "mode": "cover", "log": "Other, ", "path": "/etc/sonic/.reboot/.previous-reboot-cause.txt"}, + {"record_type": "file", "mode": "add", "log": "Other, ", "path": "/etc/sonic/.reboot/.history-reboot-cause.txt"} + ], } -MONITOR_DEV_STATUS_DECODE = { - 'fanpresent': {0:'PRESENT', 1:'ABSENT', 'okval':0}, - 'fanroll' : {0:'STALL' , 1:'ROLL', 'okval':1}, - 'psupresent': {0:'PRESENT', 1:'ABSENT', 'okval':0}, - 'psuoutput' : {0:'FAULT' , 1:'NORMAL', 'okval':1}, - 'psualert' : {0:'FAULT' , 1:'NORMAL', 'okval':1}, -} -################################################################### - - - -MAC_AVS_PARAM ={ - 0x72:0x0384, - 0x73:0x037e, - 0x74:0x0378, - 0x75:0x0372, - 0x76:0x036b, - 0x77:0x0365, - 0x78:0x035f, - 0x79:0x0359, - 0x7a:0x0352, - 0x7b:0x034c, - 0x7c:0x0346, - 0x7d:0x0340, - 0x7e:0x0339, - 0x7f:0x0333, - 0x80:0x032d, - 0x81:0x0327, - 0x82:0x0320, - 0x83:0x031a, - 0x84:0x0314, - 0x85:0x030e, - 0x86:0x0307, - 0x87:0x0301, - 0x88:0x02fb, - 0x89:0x02f5, - 0x8A:0x02ee -} +UPGRADE_SUMMARY = { + "devtype": 0x404a, -MAC_DEFAULT_PARAM = { - "type": 1, - "default":0x74, - "loopaddr":0x00, - "loop":0x00, - "open":0x00, - "close":0x40, - "bus":2, - "devno":0x60, - "addr":0x21, - "protectaddr":0x10, - "sdkreg":"TOP_AVS_SEL_REG", - "sdkcmd": "scdcmd", - "sdkcmdargs": ["-t", 5], - "sdktype": 0, - "macregloc":24 , - "mask": 0xff -} + "slot0": { + "subtype": 0, + "VME": { + "chain1": { + "name": "VME_CPLD", + "is_support_warm_upg": 0, + }, + }, + "SPI-LOGIC-DEV": { + "chain3": { + "name": "FPGA", + "is_support_warm_upg": 0, + }, + }, + "MTD": { + "chain2": { + "name": "BIOS", + "is_support_warm_upg": 0, + "filesizecheck": 10240, # bios check file size, Unit: K + "init_cmd": [ + {"io_addr": 0x722, "value": 0x02, "gettype": "io"}, + {"cmd": "modprobe mtd", "gettype": "cmd"}, + {"cmd": "modprobe spi_nor", "gettype": "cmd"}, + {"cmd": "modprobe ofpart", "gettype": "cmd"}, + {"cmd": "modprobe intel_spi writeable=1", "gettype": "cmd"}, + {"cmd": "modprobe intel_spi_platform writeable=1", "gettype": "cmd"}, + ], + "finish_cmd": [ + {"cmd": "rmmod intel_spi_platform", "gettype": "cmd"}, + {"cmd": "rmmod intel_spi", "gettype": "cmd"}, + {"cmd": "rmmod ofpart", "gettype": "cmd"}, + {"cmd": "rmmod spi_nor", "gettype": "cmd"}, + {"cmd": "rmmod mtd", "gettype": "cmd"}, + ], + }, + }, -DEVICE = [] -DRIVERLISTS = [] + "TEST": { + "cpld": [ + {"chain": 1, "file": "/etc/.upgrade_test/cpld_test_header.vme", "display_name": "CPLD"}, + ], + "fpga": [ + { + "chain": 3, + "file": "/etc/.upgrade_test/fpga_test_header.bin", + "display_name": "FPGA", + }, + ], + }, + }, -""" -## -DRIVERLISTS = [ - {"name":"i2c_dev", "delay":0}, - {"name":"i2c_algo_bit","delay":0}, - {"name":"i2c_gpio", "delay":0}, - {"name":"i2c_mux", "delay":0}, - {"name":"i2c_mux_pca9641", "delay":0}, - {"name":"i2c_mux_pca954x force_create_bus=1", "delay":0},# force_deselect_on_exit=1 - {"name":"lm75", "delay":0}, - {"name":"optoe", "delay":0}, - {"name":"at24", "delay":0}, - {"name":"rg_sff", "delay":0}, - {"name":"ragile_b6510_platform", "delay":0}, - {"name":"ragile_platform", "delay":0}, - {"name":"rg_avs", "delay":0}, - {"name":"rg_cpld", "delay":0}, - {"name":"rg_fan", "delay":0}, - {"name":"rg_psu", "delay":0}, - {"name":"pmbus_core", "delay":0}, - {"name":"csu550", "delay":0}, - {"name":"rg_gpio_xeon", "delay":0}, - {"name":"firmware_driver", "delay":0}, - {"name":"firmware_bin", "delay":0}, - {"name":"ragile_b6510_sfputil", "delay":0}, - {"name":"ragile_common dfd_my_type=0x404a", "delay":0}, - {"name":"lpc_dbg", "delay":0}, -] + "BMC": { + "name": "BMC", + "init_cmd": [ + ], + "finish_cmd": [], + }, +} -DEVICE = [ - {"name":"pca9641","bus":0 ,"loc":0x10 }, - {"name":"pca9548","bus":2 ,"loc":0x70 }, - {"name":"lm75","bus": 2, "loc":0x48 }, - {"name":"lm75","bus": 2, "loc":0x49 }, - {"name":"lm75","bus": 2, "loc":0x4a }, - {"name":"24c02","bus":2 , "loc":0x57 }, - {"name":"rg_cpld","bus":0 ,"loc":0x32 }, - {"name":"rg_cpld","bus":1 ,"loc":0x34 }, - {"name":"rg_cpld","bus":1 ,"loc":0x36 }, - {"name":"rg_cpld","bus":2 ,"loc":0x33 }, - {"name":"rg_cpld","bus":2 ,"loc":0x35 }, - {"name":"rg_cpld","bus":2 ,"loc":0x37 }, - {"name":"rg_avs","bus": 2 ,"loc":0x60 }, - {"name":"pca9548","bus":1,"loc":0x70 }, - {"name":"pca9548","bus":1,"loc":0x71 }, - {"name":"pca9548","bus":1,"loc":0x72 }, - {"name":"pca9548","bus":1,"loc":0x73 }, - {"name":"pca9548","bus":1,"loc":0x74 }, - {"name":"pca9548","bus":1,"loc":0x75 }, - {"name":"pca9548","bus":1,"loc":0x76 }, - {"name":"rg_fan","bus":3,"loc":0x53 }, - {"name":"rg_fan","bus":4,"loc":0x53 }, - {"name":"rg_fan","bus":5,"loc":0x53 }, - {"name":"rg_fan","bus":6,"loc":0x53 }, - {"name":"rg_psu","bus":7 ,"loc":0x50 }, - {"name":"dps550","bus":7 ,"loc":0x58 }, - {"name":"rg_psu","bus":8 ,"loc":0x53 }, - {"name":"dps550","bus":8 ,"loc":0x5b }, - {"name": "optoe2", "bus": 11, "loc": 0x50}, - {"name": "optoe2", "bus": 12, "loc": 0x50}, - {"name": "optoe2", "bus": 13, "loc": 0x50}, - {"name": "optoe2", "bus": 14, "loc": 0x50}, - {"name": "optoe2", "bus": 15, "loc": 0x50}, - {"name": "optoe2", "bus": 16, "loc": 0x50}, - {"name": "optoe2", "bus": 17, "loc": 0x50}, - {"name": "optoe2", "bus": 18, "loc": 0x50}, - {"name": "optoe2", "bus": 19, "loc": 0x50}, - {"name": "optoe2", "bus": 20, "loc": 0x50}, - {"name": "optoe2", "bus": 21, "loc": 0x50}, - {"name": "optoe2", "bus": 22, "loc": 0x50}, - {"name": "optoe2", "bus": 23, "loc": 0x50}, - {"name": "optoe2", "bus": 24, "loc": 0x50}, - {"name": "optoe2", "bus": 25, "loc": 0x50}, - {"name": "optoe2", "bus": 26, "loc": 0x50}, - {"name": "optoe2", "bus": 27, "loc": 0x50}, - {"name": "optoe2", "bus": 28, "loc": 0x50}, - {"name": "optoe2", "bus": 29, "loc": 0x50}, - {"name": "optoe2", "bus": 30, "loc": 0x50}, - {"name": "optoe2", "bus": 31, "loc": 0x50}, - {"name": "optoe2", "bus": 32, "loc": 0x50}, - {"name": "optoe2", "bus": 33, "loc": 0x50}, - {"name": "optoe2", "bus": 34, "loc": 0x50}, - {"name": "optoe2", "bus": 35, "loc": 0x50}, - {"name": "optoe2", "bus": 36, "loc": 0x50}, - {"name": "optoe2", "bus": 37, "loc": 0x50}, - {"name": "optoe2", "bus": 38, "loc": 0x50}, - {"name": "optoe2", "bus": 39, "loc": 0x50}, - {"name": "optoe2", "bus": 40, "loc": 0x50}, - {"name": "optoe2", "bus": 41, "loc": 0x50}, - {"name": "optoe2", "bus": 42, "loc": 0x50}, - {"name": "optoe2", "bus": 43, "loc": 0x50}, - {"name": "optoe2", "bus": 44, "loc": 0x50}, - {"name": "optoe2", "bus": 45, "loc": 0x50}, - {"name": "optoe2", "bus": 46, "loc": 0x50}, - {"name": "optoe2", "bus": 47, "loc": 0x50}, - {"name": "optoe2", "bus": 48, "loc": 0x50}, - {"name": "optoe2", "bus": 49, "loc": 0x50}, - {"name": "optoe2", "bus": 50, "loc": 0x50}, - {"name": "optoe2", "bus": 51, "loc": 0x50}, - {"name": "optoe2", "bus": 52, "loc": 0x50}, - {"name": "optoe2", "bus": 53, "loc": 0x50}, - {"name": "optoe2", "bus": 54, "loc": 0x50}, - {"name": "optoe2", "bus": 55, "loc": 0x50}, - {"name": "optoe2", "bus": 56, "loc": 0x50}, - {"name": "optoe2", "bus": 57, "loc": 0x50}, - {"name": "optoe2", "bus": 58, "loc": 0x50}, - {"name": "optoe1", "bus": 59, "loc": 0x50}, - {"name": "optoe1", "bus": 60, "loc": 0x50}, - {"name": "optoe1", "bus": 61, "loc": 0x50}, - {"name": "optoe1", "bus": 62, "loc": 0x50}, - {"name": "optoe1", "bus": 63, "loc": 0x50}, - {"name": "optoe1", "bus": 64, "loc": 0x50}, - {"name": "optoe1", "bus": 65, "loc": 0x50}, - {"name": "optoe1", "bus": 66, "loc": 0x50}, -] -INIT_PARAM = [ - {"loc":"1-0034/sfp_enable","value": "01"}, - {"loc":"2-0035/sfp_enable2","value":"ff"}, - {"loc":"2-0033/mac_led", "value":"ff"}, - {"loc":"1-0034/sfp_txdis1","value":"00"}, - {"loc":"1-0034/sfp_txdis2","value":"00"}, - {"loc":"1-0034/sfp_txdis3","value":"00"}, - {"loc":"1-0036/sfp_txdis4","value":"00"}, - {"loc":"1-0036/sfp_txdis5","value":"00"}, - {"loc":"1-0036/sfp_txdis6","value":"00"}, - {"loc":fanloc[0]["location"], "value":"80"}, - {"loc":"2-0033/sfp_led1_yellow","value":"ad"}, - {"loc":"2-0035/sfp_led2_yellow","value":"ad"}, -] -""" +PLATFORM_E2_CONF = { + "fan": [ + { + "name": "fan1", "e2_type": "fru", "e2_path": "/sys/bus/i2c/devices/16-0050/eeprom", + "e2_decode": [ + { + "area": "productInfoArea", "field": "productVersion", "decode_type": "func", "func_name": "fru_decode_hw" + }, + { + "area": "boardInfoArea", "field": "boardextra1", "decode_type": "func", "func_name": "fru_decode_hw" + }, + ], + }, + { + "name": "fan2", "e2_type": "fru", "e2_path": "/sys/bus/i2c/devices/17-0050/eeprom", + "e2_decode": [ + { + "area": "productInfoArea", "field": "productVersion", "decode_type": "func", "func_name": "fru_decode_hw" + }, + { + "area": "boardInfoArea", "field": "boardextra1", "decode_type": "func", "func_name": "fru_decode_hw" + }, + ], + }, + { + "name": "fan3", "e2_type": "fru", "e2_path": "/sys/bus/i2c/devices/18-0050/eeprom", + "e2_decode": [ + { + "area": "productInfoArea", "field": "productVersion", "decode_type": "func", "func_name": "fru_decode_hw" + }, + { + "area": "boardInfoArea", "field": "boardextra1", "decode_type": "func", "func_name": "fru_decode_hw" + }, + ], + }, + { + "name": "fan4", "e2_type": "fru", "e2_path": "/sys/bus/i2c/devices/19-0050/eeprom", + "e2_decode": [ + { + "area": "productInfoArea", "field": "productVersion", "decode_type": "func", "func_name": "fru_decode_hw" + }, + { + "area": "boardInfoArea", "field": "boardextra1", "decode_type": "func", "func_name": "fru_decode_hw" + }, + ], + }, + ], + "psu": [ + {"name": "psu1", "e2_type": "fru", "e2_path": "/sys/bus/i2c/devices/24-0050/eeprom"}, + {"name": "psu2", "e2_type": "fru", "e2_path": "/sys/bus/i2c/devices/25-0050/eeprom"}, + ], + "syseeprom": [ + {"name": "syseeprom", "e2_type": "onie_tlv", "e2_path": "/sys/bus/i2c/devices/0-0056/eeprom"}, + ], +} -INIT_PARAM = [ - { - "name": "sfp_enable", - "bus": 1, - "devaddr": 0x34, - "offset": 0xa1, - "val": 0x01, - }, - { - "name": "sfp_eanble2", - "bus": 2, - "devaddr": 0x35, - "offset": 0xa0, - "val": 0xff, - }, - { - "name": "mac_led", - "bus": 2, - "devaddr": 0x33, - "offset": 0xa0, - "val": 0xff, - }, - { - "name": "sfp_txdis1", - "bus": 1, - "devaddr": 0x34, - "offset": 0x60, - "val": 0x00, - }, - { - "name": "sfp_txdis2", - "bus": 1, - "devaddr": 0x34, - "offset": 0x61, - "val": 0x00, +AIR_FLOW_CONF = { + "psu_fan_airflow": { + "intake": ['CSU550AP-3-500', 'DPS-550AB-39 A', 'GW-CRPS550N2C', 'CSU550AP-3-300', 'DPS-550AB-39 B', 'CSU550AP-3'], + "exhaust": ['CSU550AP-3-501', 'DPS-550AB-40 A', 'GW-CRPS550N2RC'] }, - { - "name": "sfp_txdis3", - "bus": 1, - "devaddr": 0x34, - "offset": 0x62, - "val": 0x00, - }, - { - "name": "sfp_txdis4", - "bus": 1, - "devaddr": 0x36, - "offset": 0x60, - "val": 0x00, - }, - { - "name": "sfp_txdis5", - "bus": 1, - "devaddr": 0x36, - "offset": 0x61, - "val": 0x00, - }, - { - "name": "sfp_txdis6", - "bus": 1, - "devaddr": 0x36, - "offset": 0x62, - "val": 0x00, - }, - { - "name": "sfp_led1_yellow", - "bus": 2, - "devaddr": 0x33, - "offset": 0xad, - "val": 0xad, - }, - { - "name": "sfp_led2_yellow", - "bus": 2, - "devaddr": 0x35, - "offset": 0xad, - "val": 0xad, - }, - { - "name": "fan_speed_set", - "bus": 0, - "devaddr": 0x32, - "offset": 0x15, - "val": 0x80, + + "fanairflow": { + "intake": ['M1HFAN I-F'], + "exhaust": ['M1HFAN I-R'] }, -] + + "fans": [ + { + "name": "FAN1", "e2_type": "fru", "e2_path": "/sys/bus/i2c/devices/16-0050/eeprom", + "area": "productInfoArea", "field": "productName", "decode": "fanairflow" + }, + { + "name": "FAN2", "e2_type": "fru", "e2_path": "/sys/bus/i2c/devices/17-0050/eeprom", + "area": "productInfoArea", "field": "productName", "decode": "fanairflow" + }, + { + "name": "FAN3", "e2_type": "fru", "e2_path": "/sys/bus/i2c/devices/18-0050/eeprom", + "area": "productInfoArea", "field": "productName", "decode": "fanairflow" + }, + { + "name": "FAN4", "e2_type": "fru", "e2_path": "/sys/bus/i2c/devices/19-0050/eeprom", + "area": "productInfoArea", "field": "productName", "decode": "fanairflow" + } + ], + + "psus": [ + { + "name": "PSU1", "e2_type": "fru", "e2_path": "/sys/bus/i2c/devices/24-0050/eeprom", + "area": "productInfoArea", "field": "productPartModelName", "decode": "psu_fan_airflow" + }, + { + "name": "PSU2", "e2_type": "fru", "e2_path": "/sys/bus/i2c/devices/25-0050/eeprom", + "area": "productInfoArea", "field": "productPartModelName", "decode": "psu_fan_airflow" + } + ] +} diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/config/x86_64_ragile_ra_b6510_48v8c_r0_port_config.py b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/config/x86_64_ragile_ra_b6510_48v8c_r0_port_config.py new file mode 100644 index 000000000000..26f92a77a020 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/config/x86_64_ragile_ra_b6510_48v8c_r0_port_config.py @@ -0,0 +1,7 @@ +#!/usr/bin/python3 +# -*- coding: UTF-8 -*- + +PLATFORM_INTF_OPTOE = { + "port_num": 56, + "optoe_start_bus": 32, +} diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/hal-config/x86_64_ragile_ra_b6510_48v8c_r0_device.py b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/hal-config/x86_64_ragile_ra_b6510_48v8c_r0_device.py new file mode 100644 index 000000000000..ba1a8dea0b51 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/hal-config/x86_64_ragile_ra_b6510_48v8c_r0_device.py @@ -0,0 +1,1234 @@ +#!/usr/bin/python3 + +psu_fan_airflow = { + "intake": ['CSU550AP-3-500', 'DPS-550AB-39 A', 'GW-CRPS550N2C', 'CSU550AP-3-300', 'DPS-550AB-39 B', 'CSU550AP-3'], + "exhaust": ['CSU550AP-3-501', 'DPS-550AB-40 A', 'GW-CRPS550N2RC'] +} + +fanairflow = { + "intake": ['M1HFAN I-F'], + "exhaust": ['M1HFAN I-R'], +} + +psu_display_name = { + "PA550II-F": ['CSU550AP-3-500', 'DPS-550AB-39 A', 'GW-CRPS550N2C', 'CSU550AP-3-300', 'DPS-550AB-39 B', 'CSU550AP-3'], + "PA550II-R": ['CSU550AP-3-501', 'DPS-550AB-40 A', 'GW-CRPS550N2RC'] +} + +psutypedecode = { + 0x00: 'N/A', + 0x01: 'AC', + 0x02: 'DC', +} + + +class Unit: + Temperature = "C" + Voltage = "V" + Current = "A" + Power = "W" + Speed = "RPM" + + +PSU_NOT_PRESENT_PWM = 100 + + +class threshold: + PSU_TEMP_MIN = -20 * 1000 + PSU_TEMP_MAX = 60 * 1000 + + PSU_FAN_SPEED_MIN = 2000 + PSU_FAN_SPEED_MAX = 18000 + + PSU_OUTPUT_VOLTAGE_MIN = 11 * 1000 + PSU_OUTPUT_VOLTAGE_MAX = 14 * 1000 + + PSU_AC_INPUT_VOLTAGE_MIN = 200 * 1000 + PSU_AC_INPUT_VOLTAGE_MAX = 240 * 1000 + + PSU_DC_INPUT_VOLTAGE_MIN = 190 * 1000 + PSU_DC_INPUT_VOLTAGE_MAX = 290 * 1000 + + ERR_VALUE = -9999999 + + PSU_OUTPUT_POWER_MIN = 10 * 1000 * 1000 + PSU_OUTPUT_POWER_MAX = 560 * 1000 * 1000 + + PSU_INPUT_POWER_MIN = 10 * 1000 * 1000 + PSU_INPUT_POWER_MAX = 625 * 1000 * 1000 + + PSU_OUTPUT_CURRENT_MIN = 1 * 1000 + PSU_OUTPUT_CURRENT_MAX = 45 * 1000 + + PSU_INPUT_CURRENT_MIN = 0 * 1000 + PSU_INPUT_CURRENT_MAX = 7 * 1000 + + FRONT_FAN_SPEED_MAX = 24000 + REAR_FAN_SPEED_MAX = 22500 + FAN_SPEED_MIN = 5000 + + +class Description: + CPLD = "Used for managing IO modules, SFP+ modules and system LEDs" + BIOS = "Performs initialization of hardware components during booting" + FPGA = "Platform management controller for on-board temperature monitoring, in-chassis power" + + +devices = { + "onie_e2": [ + { + "name": "ONIE_E2", + "e2loc": {"loc": "/sys/bus/i2c/devices/0-0056/eeprom", "way": "sysfs"}, + "airflow": "intake" + }, + ], + "psus": [ + { + "e2loc": {"loc": "/sys/bus/i2c/devices/24-0050/eeprom", "way": "sysfs"}, + "pmbusloc": {"bus": 24, "addr": 0x58, "way": "i2c"}, + "present": {"loc": "/sys/wb_plat/psu/psu1/present", "way": "sysfs", "mask": 0x01, "okval": 1}, + "name": "PSU1", + "psu_display_name": psu_display_name, + "airflow": psu_fan_airflow, + "TempStatus": {"bus": 24, "addr": 0x58, "offset": 0x79, "way": "i2cword", "mask": 0x0004}, + "Temperature": { + "value": {"loc": "/sys/bus/i2c/devices/i2c-24/24-0058/hwmon/hwmon*/temp1_input", "way": "sysfs"}, + "Min": threshold.PSU_TEMP_MIN, + "Max": threshold.PSU_TEMP_MAX, + "Unit": Unit.Temperature, + "format": "float(float(%s)/1000)" + }, + "FanStatus": {"bus": 24, "addr": 0x58, "offset": 0x79, "way": "i2cword", "mask": 0x0400}, + "FanSpeed": { + "value": {"loc": "/sys/bus/i2c/devices/i2c-24/24-0058/hwmon/hwmon*/fan1_input", "way": "sysfs"}, + "Min": threshold.PSU_FAN_SPEED_MIN, + "Max": threshold.PSU_FAN_SPEED_MAX, + "Unit": Unit.Speed + }, + "psu_fan_tolerance": 40, + "InputsStatus": {"bus": 24, "addr": 0x58, "offset": 0x79, "way": "i2cword", "mask": 0x2000}, + "InputsType": {"bus": 24, "addr": 0x58, "offset": 0x80, "way": "i2c", 'psutypedecode': psutypedecode}, + "InputsVoltage": { + 'AC': { + "value": {"loc": "/sys/bus/i2c/devices/i2c-24/24-0058/hwmon/hwmon*/in1_input", "way": "sysfs"}, + "Min": threshold.PSU_AC_INPUT_VOLTAGE_MIN, + "Max": threshold.PSU_AC_INPUT_VOLTAGE_MAX, + "Unit": Unit.Voltage, + "format": "float(float(%s)/1000)" + + }, + 'DC': { + "value": {"loc": "/sys/bus/i2c/devices/i2c-24/24-0058/hwmon/hwmon*/in1_input", "way": "sysfs"}, + "Min": threshold.PSU_DC_INPUT_VOLTAGE_MIN, + "Max": threshold.PSU_DC_INPUT_VOLTAGE_MAX, + "Unit": Unit.Voltage, + "format": "float(float(%s)/1000)" + }, + 'other': { + "value": {"loc": "/sys/bus/i2c/devices/i2c-24/24-0058/hwmon/hwmon*/in1_input", "way": "sysfs"}, + "Min": threshold.ERR_VALUE, + "Max": threshold.ERR_VALUE, + "Unit": Unit.Voltage, + "format": "float(float(%s)/1000)" + } + }, + "InputsCurrent": { + "value": {"loc": "/sys/bus/i2c/devices/i2c-24/24-0058/hwmon/hwmon*/curr1_input", "way": "sysfs"}, + "Min": threshold.PSU_INPUT_CURRENT_MIN, + "Max": threshold.PSU_INPUT_CURRENT_MAX, + "Unit": Unit.Current, + "format": "float(float(%s)/1000)" + }, + "InputsPower": { + "value": {"loc": "/sys/bus/i2c/devices/i2c-24/24-0058/hwmon/hwmon*/power1_input", "way": "sysfs"}, + "Min": threshold.PSU_INPUT_POWER_MIN, + "Max": threshold.PSU_INPUT_POWER_MAX, + "Unit": Unit.Power, + "format": "float(float(%s)/1000000)" + }, + "OutputsStatus": {"bus": 24, "addr": 0x58, "offset": 0x79, "way": "i2cword", "mask": 0x8800}, + "OutputsVoltage": { + "value": {"loc": "/sys/bus/i2c/devices/i2c-24/24-0058/hwmon/hwmon*/in2_input", "way": "sysfs"}, + "Min": threshold.PSU_OUTPUT_VOLTAGE_MIN, + "Max": threshold.PSU_OUTPUT_VOLTAGE_MAX, + "Unit": Unit.Voltage, + "format": "float(float(%s)/1000)" + }, + "OutputsCurrent": { + "value": {"loc": "/sys/bus/i2c/devices/i2c-24/24-0058/hwmon/hwmon*/curr2_input", "way": "sysfs"}, + "Min": threshold.PSU_OUTPUT_CURRENT_MIN, + "Max": threshold.PSU_OUTPUT_CURRENT_MAX, + "Unit": Unit.Current, + "format": "float(float(%s)/1000)" + }, + "OutputsPower": { + "value": {"loc": "/sys/bus/i2c/devices/i2c-24/24-0058/hwmon/hwmon*/power2_input", "way": "sysfs"}, + "Min": threshold.PSU_OUTPUT_POWER_MIN, + "Max": threshold.PSU_OUTPUT_POWER_MAX, + "Unit": Unit.Power, + "format": "float(float(%s)/1000000)" + }, + }, + { + "e2loc": {"loc": "/sys/bus/i2c/devices/25-0050/eeprom", "way": "sysfs"}, + "pmbusloc": {"bus": 25, "addr": 0x58, "way": "i2c"}, + "present": {"loc": "/sys/wb_plat/psu/psu2/present", "way": "sysfs", "mask": 0x01, "okval": 1}, + "name": "PSU2", + "psu_display_name": psu_display_name, + "airflow": psu_fan_airflow, + "TempStatus": {"bus": 25, "addr": 0x58, "offset": 0x79, "way": "i2cword", "mask": 0x0004}, + "Temperature": { + "value": {"loc": "/sys/bus/i2c/devices/i2c-25/25-0058/hwmon/hwmon*/temp1_input", "way": "sysfs"}, + "Min": threshold.PSU_TEMP_MIN, + "Max": threshold.PSU_TEMP_MAX, + "Unit": Unit.Temperature, + "format": "float(float(%s)/1000)" + }, + "FanStatus": {"bus": 25, "addr": 0x58, "offset": 0x79, "way": "i2cword", "mask": 0x0400}, + "FanSpeed": { + "value": {"loc": "/sys/bus/i2c/devices/i2c-25/25-0058/hwmon/hwmon*/fan1_input", "way": "sysfs"}, + "Min": threshold.PSU_FAN_SPEED_MIN, + "Max": threshold.PSU_FAN_SPEED_MAX, + "Unit": Unit.Speed + }, + "psu_fan_tolerance": 40, + "InputsStatus": {"bus": 25, "addr": 0x58, "offset": 0x79, "way": "i2cword", "mask": 0x2000}, + "InputsType": {"bus": 25, "addr": 0x58, "offset": 0x80, "way": "i2c", 'psutypedecode': psutypedecode}, + "InputsVoltage": { + 'AC': { + "value": {"loc": "/sys/bus/i2c/devices/i2c-25/25-0058/hwmon/hwmon*/in1_input", "way": "sysfs"}, + "Min": threshold.PSU_AC_INPUT_VOLTAGE_MIN, + "Max": threshold.PSU_AC_INPUT_VOLTAGE_MAX, + "Unit": Unit.Voltage, + "format": "float(float(%s)/1000)" + + }, + 'DC': { + "value": {"loc": "/sys/bus/i2c/devices/i2c-25/25-0058/hwmon/hwmon*/in1_input", "way": "sysfs"}, + "Min": threshold.PSU_DC_INPUT_VOLTAGE_MIN, + "Max": threshold.PSU_DC_INPUT_VOLTAGE_MAX, + "Unit": Unit.Voltage, + "format": "float(float(%s)/1000)" + }, + 'other': { + "value": {"loc": "/sys/bus/i2c/devices/i2c-25/25-0058/hwmon/hwmon*/in1_input", "way": "sysfs"}, + "Min": threshold.ERR_VALUE, + "Max": threshold.ERR_VALUE, + "Unit": Unit.Voltage, + "format": "float(float(%s)/1000)" + } + }, + "InputsCurrent": { + "value": {"loc": "/sys/bus/i2c/devices/i2c-25/25-0058/hwmon/hwmon*/curr1_input", "way": "sysfs"}, + "Min": threshold.PSU_INPUT_CURRENT_MIN, + "Max": threshold.PSU_INPUT_CURRENT_MAX, + "Unit": Unit.Current, + "format": "float(float(%s)/1000)" + }, + "InputsPower": { + "value": {"loc": "/sys/bus/i2c/devices/i2c-25/25-0058/hwmon/hwmon*/power1_input", "way": "sysfs"}, + "Min": threshold.PSU_INPUT_POWER_MIN, + "Max": threshold.PSU_INPUT_POWER_MAX, + "Unit": Unit.Power, + "format": "float(float(%s)/1000000)" + }, + "OutputsStatus": {"bus": 25, "addr": 0x58, "offset": 0x79, "way": "i2cword", "mask": 0x8800}, + "OutputsVoltage": { + "value": {"loc": "/sys/bus/i2c/devices/i2c-25/25-0058/hwmon/hwmon*/in2_input", "way": "sysfs"}, + "Min": threshold.PSU_OUTPUT_VOLTAGE_MIN, + "Max": threshold.PSU_OUTPUT_VOLTAGE_MAX, + "Unit": Unit.Voltage, + "format": "float(float(%s)/1000)" + }, + "OutputsCurrent": { + "value": {"loc": "/sys/bus/i2c/devices/i2c-25/25-0058/hwmon/hwmon*/curr2_input", "way": "sysfs"}, + "Min": threshold.PSU_OUTPUT_CURRENT_MIN, + "Max": threshold.PSU_OUTPUT_CURRENT_MAX, + "Unit": Unit.Current, + "format": "float(float(%s)/1000)" + }, + "OutputsPower": { + "value": {"loc": "/sys/bus/i2c/devices/i2c-25/25-0058/hwmon/hwmon*/power2_input", "way": "sysfs"}, + "Min": threshold.PSU_OUTPUT_POWER_MIN, + "Max": threshold.PSU_OUTPUT_POWER_MAX, + "Unit": Unit.Power, + "format": "float(float(%s)/1000000)" + }, + } + ], + "temps": [ + { + "name": "SWITCH_TEMP", + "temp_id": "TEMP1", + "api_name": "ASIC_TEMP", + "Temperature": { + "value": {"loc": "/sys/bus/i2c/devices/3-0044/hwmon/hwmon*/temp99_input", "way": "sysfs"}, + "Min": -30000, + "Low": 0, + "High": 105000, + "Max": 110000, + "Unit": Unit.Temperature, + "format": "float(float(%s)/1000)" + } + }, + { + "name": "CPU_TEMP", + "temp_id": "TEMP2", + "Temperature": { + "value": {"loc": "/sys/bus/platform/devices/coretemp.0/hwmon/hwmon*/temp1_input", "way": "sysfs"}, + "Min": -15000, + "Low": 0, + "High": 100000, + "Max": 102000, + "Unit": Unit.Temperature, + "format": "float(float(%s)/1000)" + } + }, + { + "name": "INLET_TEMP", + "temp_id": "TEMP3", + "Temperature": { + "value": {"loc": "/sys/bus/i2c/devices/3-0048/hwmon/hwmon*/temp1_input", "way": "sysfs"}, + "Min": -30000, + "Low": 0, + "High": 55000, + "Max": 60000, + "Unit": Unit.Temperature, + "format": "float(float(%s)/1000)" + }, + "fix_value": { + "fix_type": "config", + "addend": -3, + } + }, + { + "name": "OUTLET_TEMP", + "temp_id": "TEMP4", + "Temperature": { + "value": {"loc": "/sys/bus/i2c/devices/3-004c/hwmon/hwmon*/temp1_input", "way": "sysfs"}, + "Min": -30000, + "Low": 0, + "High": 75000, + "Max": 80000, + "Unit": Unit.Temperature, + "format": "float(float(%s)/1000)" + } + }, + { + "name": "BOARD_TEMP", + "temp_id": "TEMP5", + "api_name": "MAC_OUT_TEMP", + "Temperature": { + "value": {"loc": "/sys/bus/i2c/devices/3-004a/hwmon/hwmon*/temp1_input", "way": "sysfs"}, + "Min": -30000, + "Low": 0, + "High": 75000, + "Max": 80000, + "Unit": Unit.Temperature, + "format": "float(float(%s)/1000)" + } + }, + { + "name": "MAC_IN_TEMP", + "temp_id": "TEMP6", + "Temperature": { + "value": {"loc": "/sys/bus/i2c/devices/3-0049/hwmon/hwmon*/temp1_input", "way": "sysfs"}, + "Min": -30000, + "Low": 0, + "High": 75000, + "Max": 80000, + "Unit": Unit.Temperature, + "format": "float(float(%s)/1000)" + } + }, + { + "name": "PSU1_TEMP", + "temp_id": "TEMP7", + "Temperature": { + "value": {"loc": "/sys/bus/i2c/devices/i2c-24/24-0058/hwmon/hwmon*/temp1_input", "way": "sysfs"}, + "Min": -20000, + "Low": 0, + "High": 55000, + "Max": 60000, + "Unit": Unit.Temperature, + "format": "float(float(%s)/1000)" + } + }, + { + "name": "PSU2_TEMP", + "temp_id": "TEMP8", + "Temperature": { + "value": {"loc": "/sys/bus/i2c/devices/i2c-25/25-0058/hwmon/hwmon*/temp1_input", "way": "sysfs"}, + "Min": -20000, + "Low": 0, + "High": 55000, + "Max": 60000, + "Unit": Unit.Temperature, + "format": "float(float(%s)/1000)" + } + }, + { + "name": "SFF_TEMP", + "Temperature": { + "value": {"loc": "/tmp/highest_sff_temp", "way": "sysfs", "flock_path": "/tmp/highest_sff_temp"}, + "Min": -30000, + "Low": 0, + "High": 90000, + "Max": 100000, + "Unit": Unit.Temperature, + "format": "float(float(%s)/1000)" + }, + "invalid": -10000, + "error": -9999, + } + ], + "leds": [ + { + "name": "FRONT_SYS_LED", + "led_type": "SYS_LED", + "led": {"bus": 6, "addr": 0x0d, "offset": 0x72, "way": "i2c"}, + "led_attrs": { + "off": 0x00, "red_flash": 0x01, "red": 0x02, + "green_flash": 0x03, "green": 0x04, "amber_flash": 0x05, + "amber": 0x06, "mask": 0x07 + }, + }, + { + "name": "FRONT_PSU_LED", + "led_type": "PSU_LED", + "led": {"bus": 6, "addr": 0x0d, "offset": 0x73, "way": "i2c"}, + "led_attrs": { + "off": 0x10, "red_flash": 0x11, "red": 0x12, + "green_flash": 0x13, "green": 0x14, "amber_flash": 0x15, + "amber": 0x16, "mask": 0x17 + }, + }, + { + "name": "FRONT_FAN_LED", + "led_type": "FAN_LED", + "led": {"bus": 6, "addr": 0x0d, "offset": 0x74, "way": "i2c"}, + "led_attrs": { + "off": 0x10, "red_flash": 0x11, "red": 0x12, + "green_flash": 0x13, "green": 0x14, "amber_flash": 0x15, + "amber": 0x16, "mask": 0x17 + }, + }, + ], + "fans": [ + { + "name": "FAN1", + "airflow": fanairflow, + "e2loc": {'loc': '/sys/bus/i2c/devices/i2c-16/16-0050/eeprom', 'way': 'sysfs'}, + "present": {"loc": "/sys/wb_plat/fan/fan1/present", "way": "sysfs", "mask": 0x01, "okval": 1}, + "SpeedMin": threshold.FAN_SPEED_MIN, + "SpeedMax": threshold.FRONT_FAN_SPEED_MAX, + "led": {"bus": 2, "addr": 0x0d, "offset": 0x3b, "way": "i2c"}, + "led_attrs": { + "off": 0x0b, "red_flash": 0x0e, "red": 0x0a, + "green_flash": 0x0d, "green": 0x09, "amber_flash": 0x07, + "amber": 0x03, "mask": 0x0f + }, + "PowerMax": 38.4, + "Rotor": { + "Rotor1_config": { + "name": "Rotor1", + "Set_speed": {"bus": 2, "addr": 0x0d, "offset": 0x14, "way": "i2c"}, + "Running": {"loc": "/sys/wb_plat/fan/fan1/motor1/status", "way": "sysfs", "mask": 0x01, "is_runing": 1}, + "HwAlarm": {"loc": "/sys/wb_plat/fan/fan1/motor1/status", "way": "sysfs", "mask": 0x01, "no_alarm": 1}, + "SpeedMin": threshold.FAN_SPEED_MIN, + "SpeedMax": threshold.FRONT_FAN_SPEED_MAX, + "Speed": { + "value": {"loc": "/sys/wb_plat/fan/fan1/motor1/speed", "way": "sysfs"}, + "Min": threshold.FAN_SPEED_MIN, + "Max": threshold.FRONT_FAN_SPEED_MAX, + "Unit": Unit.Speed, + }, + }, + "Rotor2_config": { + "name": "Rotor2", + "Set_speed": {"bus": 2, "addr": 0x0d, "offset": 0x14, "way": "i2c"}, + "Running": {"loc": "/sys/wb_plat/fan/fan1/motor0/status", "way": "sysfs", "mask": 0x01, "is_runing": 1}, + "HwAlarm": {"loc": "/sys/wb_plat/fan/fan1/motor0/status", "way": "sysfs", "mask": 0x01, "no_alarm": 1}, + "SpeedMin": threshold.FAN_SPEED_MIN, + "SpeedMax": threshold.REAR_FAN_SPEED_MAX, + "Speed": { + "value": {"loc": "/sys/wb_plat/fan/fan1/motor0/speed", "way": "sysfs"}, + "Min": threshold.FAN_SPEED_MIN, + "Max": threshold.REAR_FAN_SPEED_MAX, + "Unit": Unit.Speed, + }, + }, + }, + }, + { + "name": "FAN2", + "airflow": fanairflow, + "e2loc": {'loc': '/sys/bus/i2c/devices/i2c-17/17-0050/eeprom', 'way': 'sysfs'}, + "present": {"loc": "/sys/wb_plat/fan/fan2/present", "way": "sysfs", "mask": 0x01, "okval": 1}, + "SpeedMin": threshold.FAN_SPEED_MIN, + "SpeedMax": threshold.FRONT_FAN_SPEED_MAX, + "led": {"bus": 2, "addr": 0x0d, "offset": 0x3c, "way": "i2c"}, + "led_attrs": { + "off": 0x0b, "red_flash": 0x0e, "red": 0x0a, + "green_flash": 0x0d, "green": 0x09, "amber_flash": 0x07, + "amber": 0x03, "mask": 0x0f + }, + "PowerMax": 38.4, + "Rotor": { + "Rotor1_config": { + "name": "Rotor1", + "Set_speed": {"bus": 2, "addr": 0x0d, "offset": 0x15, "way": "i2c"}, + "Running": {"loc": "/sys/wb_plat/fan/fan2/motor1/status", "way": "sysfs", "mask": 0x01, "is_runing": 1}, + "HwAlarm": {"loc": "/sys/wb_plat/fan/fan2/motor1/status", "way": "sysfs", "mask": 0x01, "no_alarm": 1}, + "SpeedMin": threshold.FAN_SPEED_MIN, + "SpeedMax": threshold.FRONT_FAN_SPEED_MAX, + "Speed": { + "value": {"loc": "/sys/wb_plat/fan/fan2/motor1/speed", "way": "sysfs"}, + "Min": threshold.FAN_SPEED_MIN, + "Max": threshold.FRONT_FAN_SPEED_MAX, + "Unit": Unit.Speed, + }, + }, + "Rotor2_config": { + "name": "Rotor2", + "Set_speed": {"bus": 2, "addr": 0x0d, "offset": 0x15, "way": "i2c"}, + "Running": {"loc": "/sys/wb_plat/fan/fan2/motor0/status", "way": "sysfs", "mask": 0x01, "is_runing": 1}, + "HwAlarm": {"loc": "/sys/wb_plat/fan/fan2/motor0/status", "way": "sysfs", "mask": 0x01, "no_alarm": 1}, + "SpeedMin": threshold.FAN_SPEED_MIN, + "SpeedMax": threshold.REAR_FAN_SPEED_MAX, + "Speed": { + "value": {"loc": "/sys/wb_plat/fan/fan2/motor0/speed", "way": "sysfs"}, + "Min": threshold.FAN_SPEED_MIN, + "Max": threshold.REAR_FAN_SPEED_MAX, + "Unit": Unit.Speed, + }, + }, + }, + }, + { + "name": "FAN3", + "airflow": fanairflow, + "e2loc": {'loc': '/sys/bus/i2c/devices/i2c-18/18-0050/eeprom', 'way': 'sysfs'}, + "present": {"loc": "/sys/wb_plat/fan/fan3/present", "way": "sysfs", "mask": 0x01, "okval": 1}, + "SpeedMin": threshold.FAN_SPEED_MIN, + "SpeedMax": threshold.FRONT_FAN_SPEED_MAX, + "led": {"bus": 2, "addr": 0x0d, "offset": 0x3d, "way": "i2c"}, + "led_attrs": { + "off": 0x0b, "red_flash": 0x0e, "red": 0x0a, + "green_flash": 0x0d, "green": 0x09, "amber_flash": 0x07, + "amber": 0x03, "mask": 0x0f + }, + "PowerMax": 38.4, + "Rotor": { + "Rotor1_config": { + "name": "Rotor1", + "Set_speed": {"bus": 2, "addr": 0x0d, "offset": 0x16, "way": "i2c"}, + "Running": {"loc": "/sys/wb_plat/fan/fan3/motor1/status", "way": "sysfs", "mask": 0x01, "is_runing": 1}, + "HwAlarm": {"loc": "/sys/wb_plat/fan/fan3/motor1/status", "way": "sysfs", "mask": 0x01, "no_alarm": 1}, + "SpeedMin": threshold.FAN_SPEED_MIN, + "SpeedMax": threshold.FRONT_FAN_SPEED_MAX, + "Speed": { + "value": {"loc": "/sys/wb_plat/fan/fan3/motor1/speed", "way": "sysfs"}, + "Min": threshold.FAN_SPEED_MIN, + "Max": threshold.FRONT_FAN_SPEED_MAX, + "Unit": Unit.Speed, + }, + }, + "Rotor2_config": { + "name": "Rotor2", + "Set_speed": {"bus": 2, "addr": 0x0d, "offset": 0x16, "way": "i2c"}, + "Running": {"loc": "/sys/wb_plat/fan/fan3/motor0/status", "way": "sysfs", "mask": 0x01, "is_runing": 1}, + "HwAlarm": {"loc": "/sys/wb_plat/fan/fan3/motor0/status", "way": "sysfs", "mask": 0x01, "no_alarm": 1}, + "SpeedMin": threshold.FAN_SPEED_MIN, + "SpeedMax": threshold.REAR_FAN_SPEED_MAX, + "Speed": { + "value": {"loc": "/sys/wb_plat/fan/fan3/motor0/speed", "way": "sysfs"}, + "Min": threshold.FAN_SPEED_MIN, + "Max": threshold.REAR_FAN_SPEED_MAX, + "Unit": Unit.Speed, + }, + }, + }, + }, + + { + "name": "FAN4", + "airflow": fanairflow, + "e2loc": {'loc': '/sys/bus/i2c/devices/i2c-19/19-0050/eeprom', 'way': 'sysfs'}, + "present": {"loc": "/sys/wb_plat/fan/fan4/present", "way": "sysfs", "mask": 0x01, "okval": 1}, + "SpeedMin": threshold.FAN_SPEED_MIN, + "SpeedMax": threshold.FRONT_FAN_SPEED_MAX, + "led": {"bus": 2, "addr": 0x0d, "offset": 0x3e, "way": "i2c"}, + "led_attrs": { + "off": 0x0b, "red_flash": 0x0e, "red": 0x0a, + "green_flash": 0x0d, "green": 0x09, "amber_flash": 0x07, + "amber": 0x03, "mask": 0x0f + }, + "PowerMax": 38.4, + "Rotor": { + "Rotor1_config": { + "name": "Rotor1", + "Set_speed": {"bus": 2, "addr": 0x0d, "offset": 0x17, "way": "i2c"}, + "Running": {"loc": "/sys/wb_plat/fan/fan4/motor1/status", "way": "sysfs", "mask": 0x01, "is_runing": 1}, + "HwAlarm": {"loc": "/sys/wb_plat/fan/fan4/motor1/status", "way": "sysfs", "mask": 0x01, "no_alarm": 1}, + "SpeedMin": threshold.FAN_SPEED_MIN, + "SpeedMax": threshold.FRONT_FAN_SPEED_MAX, + "Speed": { + "value": {"loc": "/sys/wb_plat/fan/fan4/motor1/speed", "way": "sysfs"}, + "Min": threshold.FAN_SPEED_MIN, + "Max": threshold.FRONT_FAN_SPEED_MAX, + "Unit": Unit.Speed, + }, + }, + "Rotor2_config": { + "name": "Rotor2", + "Set_speed": {"bus": 2, "addr": 0x0d, "offset": 0x17, "way": "i2c"}, + "Running": {"loc": "/sys/wb_plat/fan/fan4/motor0/status", "way": "sysfs", "mask": 0x01, "is_runing": 1}, + "HwAlarm": {"loc": "/sys/wb_plat/fan/fan4/motor0/status", "way": "sysfs", "mask": 0x01, "no_alarm": 1}, + "SpeedMin": threshold.FAN_SPEED_MIN, + "SpeedMax": threshold.REAR_FAN_SPEED_MAX, + "Speed": { + "value": {"loc": "/sys/wb_plat/fan/fan4/motor0/speed", "way": "sysfs"}, + "Min": threshold.FAN_SPEED_MIN, + "Max": threshold.REAR_FAN_SPEED_MAX, + "Unit": Unit.Speed, + }, + }, + }, + }, + + ], + "cplds": [ + { + "name": "CPU_CPLD", + "cpld_id": "CPLD1", + "VersionFile": {"loc": "/dev/cpld0", "offset": 0, "len": 4, "way": "devfile_ascii"}, + "desc": "Used for system power", + "slot": 0, + "warm": 0, + + }, + { + "name": "CONNECT_CPLD", + "cpld_id": "CPLD2", + "VersionFile": {"loc": "/dev/cpld1", "offset": 0, "len": 4, "way": "devfile_ascii"}, + "desc": "Used for base functions", + "slot": 0, + "warm": 0, + }, + { + "name": "CONNECT_CPLD-FAN", + "cpld_id": "CPLD3", + "VersionFile": {"loc": "/dev/cpld2", "offset": 0, "len": 4, "way": "devfile_ascii"}, + "desc": "Used for fan modules", + "slot": 0, + "warm": 0, + }, + { + "name": "MAC_CPLD1", + "cpld_id": "CPLD4", + "VersionFile": {"loc": "/dev/cpld3", "offset": 0, "len": 4, "way": "devfile_ascii"}, + "desc": "Used for sff modules", + "slot": 0, + "warm": 0, + }, + { + "name": "MAC_CPLD2", + "cpld_id": "CPLD5", + "VersionFile": {"loc": "/dev/cpld4", "offset": 0, "len": 4, "way": "devfile_ascii"}, + "desc": "Used for sff modules", + "slot": 0, + "warm": 0, + }, + { + "name": "FPGA", + "cpld_id": "CPLD6", + "VersionFile": {"loc": "/dev/fpga0", "offset": 0, "len": 4, "way": "devfile_ascii"}, + "desc": "Used for base functions", + "slot": 0, + "format": "little_endian", + "warm": 0, + }, + { + "name": "BIOS", + "cpld_id": "CPLD7", + "VersionFile": {"cmd": "dmidecode -s bios-version", "way": "cmd"}, + "desc": "Performs initialization of hardware components during booting", + "slot": 0, + "type": "str", + "warm": 0, + }, + ], + "dcdc": [ + { + "name": "Switch_ZSFP1_3v3_C", + "dcdc_id": "DCDC1", + "Min": -1000, + "value": { + "loc": "/sys/bus/i2c/devices/7-0040/hwmon/hwmon*/curr1_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "A", + "Max": 22000, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Switch_QSFP1_3v3_C", + "dcdc_id": "DCDC2", + "Min": -1000, + "value": { + "loc": "/sys/bus/i2c/devices/7-0040/hwmon/hwmon*/curr3_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "A", + "Max": 22000, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Switch_5v0_C", + "dcdc_id": "DCDC3", + "Min": -1000, + "value": { + "loc": "/sys/bus/i2c/devices/7-0040/hwmon/hwmon*/curr2_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "A", + "Max": 1000, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Switch_ZSFP1_3v3_V", + "dcdc_id": "DCDC4", + "Min": 2640, + "value": { + "loc": "/sys/bus/i2c/devices/7-0040/hwmon/hwmon*/in1_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "V", + "Max": 3960, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Switch_QSFP1_3v3_V", + "dcdc_id": "DCDC5", + "Min": 2640, + "value": { + "loc": "/sys/bus/i2c/devices/7-0040/hwmon/hwmon*/in3_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "V", + "Max": 3960, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Switch_5v0_V", + "dcdc_id": "DCDC6", + "Min": 4000, + "value": { + "loc": "/sys/bus/i2c/devices/7-0040/hwmon/hwmon*/in2_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "V", + "Max": 6000, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Switch_1v2_C", + "dcdc_id": "DCDC7", + "Min": -1000, + "value": { + "loc": "/sys/bus/i2c/devices/7-0041/hwmon/hwmon*/curr1_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "A", + "Max": 2000, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Switch_3v3_C", + "dcdc_id": "DCDC8", + "Min": -1000, + "value": { + "loc": "/sys/bus/i2c/devices/7-0041/hwmon/hwmon*/curr2_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "A", + "Max": 1000, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Switch_Cpld_3v3_C", + "dcdc_id": "DCDC9", + "Min": -1000, + "value": { + "loc": "/sys/bus/i2c/devices/7-0041/hwmon/hwmon*/curr3_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "A", + "Max": 2000, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Switch_1v2_V", + "dcdc_id": "DCDC10", + "Min": 960, + "value": { + "loc": "/sys/bus/i2c/devices/7-0041/hwmon/hwmon*/in1_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "V", + "Max": 1440, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Switch_3v3_V", + "dcdc_id": "DCDC11", + "Min": 2640, + "value": { + "loc": "/sys/bus/i2c/devices/7-0041/hwmon/hwmon*/in2_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "V", + "Max": 3960, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Switch_Cpld_3v3_V", + "dcdc_id": "DCDC12", + "Min": 2640, + "value": { + "loc": "/sys/bus/i2c/devices/7-0041/hwmon/hwmon*/in3_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "V", + "Max": 3960, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Con_1v2_C", + "dcdc_id": "DCDC13", + "Min": -1000, + "value": { + "loc": "/sys/bus/i2c/devices/7-0042/hwmon/hwmon*/curr1_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "A", + "Max": 1300, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Con_3v3_C", + "dcdc_id": "DCDC14", + "Min": -1000, + "value": { + "loc": "/sys/bus/i2c/devices/7-0042/hwmon/hwmon*/curr2_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "A", + "Max": 2800, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Con_SSD_3v3_C", + "dcdc_id": "DCDC15", + "Min": -1000, + "value": { + "loc": "/sys/bus/i2c/devices/7-0042/hwmon/hwmon*/curr3_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "A", + "Max": 4500, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Con_1v2_V", + "dcdc_id": "DCDC16", + "Min": 960, + "value": { + "loc": "/sys/bus/i2c/devices/7-0042/hwmon/hwmon*/in1_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "V", + "Max": 1440, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Con_3v3_V", + "dcdc_id": "DCDC17", + "Min": 2640, + "value": { + "loc": "/sys/bus/i2c/devices/7-0042/hwmon/hwmon*/in2_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "V", + "Max": 3960, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Con_SSD_3v3_V", + "dcdc_id": "DCDC18", + "Min": 2640, + "value": { + "loc": "/sys/bus/i2c/devices/7-0042/hwmon/hwmon*/in3_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "V", + "Max": 3960, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Cpu_3v3_C", + "dcdc_id": "DCDC19", + "Min": -1000, + "value": { + "loc": "/sys/bus/i2c/devices/7-0043/hwmon/hwmon*/curr1_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "A", + "Max": 4686, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Cpu_5v_C", + "dcdc_id": "DCDC20", + "Min": -1000, + "value": { + "loc": "/sys/bus/i2c/devices/7-0043/hwmon/hwmon*/curr2_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "A", + "Max": 2200, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Cpu_1v7_C", + "dcdc_id": "DCDC21", + "Min": -1000, + "value": { + "loc": "/sys/bus/i2c/devices/7-0043/hwmon/hwmon*/curr3_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "A", + "Max": 2200, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Cpu_3v3_V", + "dcdc_id": "DCDC22", + "Min": 2640, + "value": { + "loc": "/sys/bus/i2c/devices/7-0043/hwmon/hwmon*/in1_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "V", + "Max": 3960, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Cpu_5v_V", + "dcdc_id": "DCDC23", + "Min": 4000, + "value": { + "loc": "/sys/bus/i2c/devices/7-0043/hwmon/hwmon*/in2_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "V", + "Max": 6000, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Cpu_1v7_V", + "dcdc_id": "DCDC24", + "Min": 1360, + "value": { + "loc": "/sys/bus/i2c/devices/7-0043/hwmon/hwmon*/in3_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "V", + "Max": 2040, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Cpu_CORE_C", + "dcdc_id": "DCDC25", + "Min": -1000, + "value": { + "loc": "/sys/bus/i2c/devices/7-0060/hwmon/hwmon*/curr1_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "A", + "Max": 47300, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Cpu_1v05_C", + "dcdc_id": "DCDC26", + "Min": -1000, + "value": { + "loc": "/sys/bus/i2c/devices/7-0060/hwmon/hwmon*/curr2_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "A", + "Max": 15400, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Cpu_CORE_V", + "dcdc_id": "DCDC27", + "Min": 1456, + "value": { + "loc": "/sys/bus/i2c/devices/7-0060/hwmon/hwmon*/in2_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "V", + "Max": 2184, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Cpu_1v05_V", + "dcdc_id": "DCDC28", + "Min": 840, + "value": { + "loc": "/sys/bus/i2c/devices/7-0060/hwmon/hwmon*/in3_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "V", + "Max": 1260, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Switch_CORE_C", + "dcdc_id": "DCDC29", + "Min": -1000, + "value": { + "loc": "/sys/bus/i2c/devices/7-0064/hwmon/hwmon*/curr2_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "A", + "Max": 220000, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Switch_ANALOG_C", + "dcdc_id": "DCDC30", + "Min": -1000, + "value": { + "loc": "/sys/bus/i2c/devices/7-0064/hwmon/hwmon*/curr3_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "A", + "Max": 18000, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Switch_CORE_V", + "dcdc_id": "DCDC31", + "Min": 600, + "value": { + "loc": "/sys/bus/i2c/devices/7-0064/hwmon/hwmon*/in2_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "V", + "Max": 1200, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Switch_ANALOG_V", + "dcdc_id": "DCDC32", + "Min": 640, + "value": { + "loc": "/sys/bus/i2c/devices/7-0064/hwmon/hwmon*/in3_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "V", + "Max": 960, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Cpu_1v2_C", + "dcdc_id": "DCDC33", + "Min": -1000, + "value": { + "loc": "/sys/bus/i2c/devices/7-006c/hwmon/hwmon*/curr1_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "A", + "Max": 9900, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Cpu_2v23_C", + "dcdc_id": "DCDC34", + "Min": -1000, + "value": { + "loc": "/sys/bus/i2c/devices/7-006c/hwmon/hwmon*/curr2_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "A", + "Max": 2200, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Cpu_1v2_V", + "dcdc_id": "DCDC35", + "Min": 960, + "value": { + "loc": "/sys/bus/i2c/devices/7-006c/hwmon/hwmon*/in2_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "V", + "Max": 1440, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Cpu_2v23_V", + "dcdc_id": "DCDC36", + "Min": 1784, + "value": { + "loc": "/sys/bus/i2c/devices/7-006c/hwmon/hwmon*/in3_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "V", + "Max": 2676, + "format": "float(float(%s)/1000)", + }, + ], + "cpu": [ + { + "name": "cpu", + "reboot_cause_path": "/etc/sonic/.reboot/.previous-reboot-cause.txt" + } + ], + "sfps": { + "ver": '1.0', + "port_index_start": 1, + "port_num": 56, + "log_level": 2, + "eeprom_retry_times": 5, + "eeprom_retry_break_sec": 0.2, + "presence_cpld": { + "dev_id": { + 3: { + "offset": { + 0x30: "1-8", + 0x31: "9-16", + 0x32: "17-24", + }, + }, + 4: { + "offset": { + 0x30: "25-32", + 0x31: "33-40", + 0x32: "41-48", + 0x33: "49-56", + }, + }, + }, + }, + "presence_val_is_present": 0, + "eeprom_path": "/sys/bus/i2c/devices/i2c-%d/%d-0050/eeprom", + "eeprom_path_key": list(range(32, 88)), + "optoe_driver_path": "/sys/bus/i2c/devices/i2c-%d/%d-0050/dev_class", + "optoe_driver_key": list(range(32, 88)), + "txdis_cpld": { + "dev_id": { + 3: { + "offset": { + 0x60: "1-8", + 0x61: "9-16", + 0x62: "17-24", + }, + }, + 4: { + "offset": { + 0x60: "25-32", + 0x61: "33-40", + 0x62: "41-48", + }, + }, + }, + }, + "txdisable_val_is_on": 0, + "reset_cpld": { + "dev_id": { + 4: { + "offset": { + 0xb9: "49-56", + }, + }, + }, + }, + "reset_val_is_reset": 0, + } +} diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/hal-config/x86_64_ragile_ra_b6510_48v8c_r0_exhaust_device.py b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/hal-config/x86_64_ragile_ra_b6510_48v8c_r0_exhaust_device.py new file mode 100644 index 000000000000..0b5d750dd449 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/hal-config/x86_64_ragile_ra_b6510_48v8c_r0_exhaust_device.py @@ -0,0 +1,1232 @@ +#!/usr/bin/python3 + +psu_fan_airflow = { + "intake": ['CSU550AP-3-500', 'DPS-550AB-39 A', 'GW-CRPS550N2C', 'CSU550AP-3-300', 'DPS-550AB-39 B', 'CSU550AP-3'], + "exhaust": ['CSU550AP-3-501', 'DPS-550AB-40 A', 'GW-CRPS550N2RC'] +} + +fanairflow = { + "intake": ['M1HFAN I-F'], + "exhaust": ['M1HFAN I-R'], +} + +psu_display_name = { + "PA550II-F": ['CSU550AP-3-500', 'DPS-550AB-39 A', 'GW-CRPS550N2C', 'CSU550AP-3-300', 'DPS-550AB-39 B', 'CSU550AP-3'], + "PA550II-R": ['CSU550AP-3-501', 'DPS-550AB-40 A', 'GW-CRPS550N2RC'] +} + +psutypedecode = { + 0x00: 'N/A', + 0x01: 'AC', + 0x02: 'DC', +} + + +class Unit: + Temperature = "C" + Voltage = "V" + Current = "A" + Power = "W" + Speed = "RPM" + + +PSU_NOT_PRESENT_PWM = 100 + + +class threshold: + PSU_TEMP_MIN = -20 * 1000 + PSU_TEMP_MAX = 60 * 1000 + + PSU_FAN_SPEED_MIN = 2000 + PSU_FAN_SPEED_MAX = 18000 + + PSU_OUTPUT_VOLTAGE_MIN = 11 * 1000 + PSU_OUTPUT_VOLTAGE_MAX = 14 * 1000 + + PSU_AC_INPUT_VOLTAGE_MIN = 200 * 1000 + PSU_AC_INPUT_VOLTAGE_MAX = 240 * 1000 + + PSU_DC_INPUT_VOLTAGE_MIN = 190 * 1000 + PSU_DC_INPUT_VOLTAGE_MAX = 290 * 1000 + + ERR_VALUE = -9999999 + + PSU_OUTPUT_POWER_MIN = 10 * 1000 * 1000 + PSU_OUTPUT_POWER_MAX = 560 * 1000 * 1000 + + PSU_INPUT_POWER_MIN = 10 * 1000 * 1000 + PSU_INPUT_POWER_MAX = 625 * 1000 * 1000 + + PSU_OUTPUT_CURRENT_MIN = 1 * 1000 + PSU_OUTPUT_CURRENT_MAX = 45 * 1000 + + PSU_INPUT_CURRENT_MIN = 0 * 1000 + PSU_INPUT_CURRENT_MAX = 7 * 1000 + + FRONT_FAN_SPEED_MAX = 24000 + REAR_FAN_SPEED_MAX = 22500 + FAN_SPEED_MIN = 5000 + + +class Description: + CPLD = "Used for managing IO modules, SFP+ modules and system LEDs" + BIOS = "Performs initialization of hardware components during booting" + FPGA = "Platform management controller for on-board temperature monitoring, in-chassis power" + + +devices = { + "onie_e2": [ + { + "name": "ONIE_E2", + "e2loc": {"loc": "/sys/bus/i2c/devices/0-0056/eeprom", "way": "sysfs"}, + "airflow": "exhaust" + }, + ], + "psus": [ + { + "e2loc": {"loc": "/sys/bus/i2c/devices/24-0050/eeprom", "way": "sysfs"}, + "pmbusloc": {"bus": 24, "addr": 0x58, "way": "i2c"}, + "present": {"loc": "/sys/wb_plat/psu/psu1/present", "way": "sysfs", "mask": 0x01, "okval": 1}, + "name": "PSU1", + "psu_display_name": psu_display_name, + "airflow": psu_fan_airflow, + "TempStatus": {"bus": 24, "addr": 0x58, "offset": 0x79, "way": "i2cword", "mask": 0x0004}, + "Temperature": { + "value": {"loc": "/sys/bus/i2c/devices/i2c-24/24-0058/hwmon/hwmon*/temp1_input", "way": "sysfs"}, + "Min": threshold.PSU_TEMP_MIN, + "Max": threshold.PSU_TEMP_MAX, + "Unit": Unit.Temperature, + "format": "float(float(%s)/1000)" + }, + "FanStatus": {"bus": 24, "addr": 0x58, "offset": 0x79, "way": "i2cword", "mask": 0x0400}, + "FanSpeed": { + "value": {"loc": "/sys/bus/i2c/devices/i2c-24/24-0058/hwmon/hwmon*/fan1_input", "way": "sysfs"}, + "Min": threshold.PSU_FAN_SPEED_MIN, + "Max": threshold.PSU_FAN_SPEED_MAX, + "Unit": Unit.Speed + }, + "psu_fan_tolerance": 40, + "InputsStatus": {"bus": 24, "addr": 0x58, "offset": 0x79, "way": "i2cword", "mask": 0x2000}, + "InputsType": {"bus": 24, "addr": 0x58, "offset": 0x80, "way": "i2c", 'psutypedecode': psutypedecode}, + "InputsVoltage": { + 'AC': { + "value": {"loc": "/sys/bus/i2c/devices/i2c-24/24-0058/hwmon/hwmon*/in1_input", "way": "sysfs"}, + "Min": threshold.PSU_AC_INPUT_VOLTAGE_MIN, + "Max": threshold.PSU_AC_INPUT_VOLTAGE_MAX, + "Unit": Unit.Voltage, + "format": "float(float(%s)/1000)" + + }, + 'DC': { + "value": {"loc": "/sys/bus/i2c/devices/i2c-24/24-0058/hwmon/hwmon*/in1_input", "way": "sysfs"}, + "Min": threshold.PSU_DC_INPUT_VOLTAGE_MIN, + "Max": threshold.PSU_DC_INPUT_VOLTAGE_MAX, + "Unit": Unit.Voltage, + "format": "float(float(%s)/1000)" + }, + 'other': { + "value": {"loc": "/sys/bus/i2c/devices/i2c-24/24-0058/hwmon/hwmon*/in1_input", "way": "sysfs"}, + "Min": threshold.ERR_VALUE, + "Max": threshold.ERR_VALUE, + "Unit": Unit.Voltage, + "format": "float(float(%s)/1000)" + } + }, + "InputsCurrent": { + "value": {"loc": "/sys/bus/i2c/devices/i2c-24/24-0058/hwmon/hwmon*/curr1_input", "way": "sysfs"}, + "Min": threshold.PSU_INPUT_CURRENT_MIN, + "Max": threshold.PSU_INPUT_CURRENT_MAX, + "Unit": Unit.Current, + "format": "float(float(%s)/1000)" + }, + "InputsPower": { + "value": {"loc": "/sys/bus/i2c/devices/i2c-24/24-0058/hwmon/hwmon*/power1_input", "way": "sysfs"}, + "Min": threshold.PSU_INPUT_POWER_MIN, + "Max": threshold.PSU_INPUT_POWER_MAX, + "Unit": Unit.Power, + "format": "float(float(%s)/1000000)" + }, + "OutputsStatus": {"bus": 24, "addr": 0x58, "offset": 0x79, "way": "i2cword", "mask": 0x8800}, + "OutputsVoltage": { + "value": {"loc": "/sys/bus/i2c/devices/i2c-24/24-0058/hwmon/hwmon*/in2_input", "way": "sysfs"}, + "Min": threshold.PSU_OUTPUT_VOLTAGE_MIN, + "Max": threshold.PSU_OUTPUT_VOLTAGE_MAX, + "Unit": Unit.Voltage, + "format": "float(float(%s)/1000)" + }, + "OutputsCurrent": { + "value": {"loc": "/sys/bus/i2c/devices/i2c-24/24-0058/hwmon/hwmon*/curr2_input", "way": "sysfs"}, + "Min": threshold.PSU_OUTPUT_CURRENT_MIN, + "Max": threshold.PSU_OUTPUT_CURRENT_MAX, + "Unit": Unit.Current, + "format": "float(float(%s)/1000)" + }, + "OutputsPower": { + "value": {"loc": "/sys/bus/i2c/devices/i2c-24/24-0058/hwmon/hwmon*/power2_input", "way": "sysfs"}, + "Min": threshold.PSU_OUTPUT_POWER_MIN, + "Max": threshold.PSU_OUTPUT_POWER_MAX, + "Unit": Unit.Power, + "format": "float(float(%s)/1000000)" + }, + }, + { + "e2loc": {"loc": "/sys/bus/i2c/devices/25-0050/eeprom", "way": "sysfs"}, + "pmbusloc": {"bus": 25, "addr": 0x58, "way": "i2c"}, + "present": {"loc": "/sys/wb_plat/psu/psu2/present", "way": "sysfs", "mask": 0x01, "okval": 1}, + "name": "PSU2", + "psu_display_name": psu_display_name, + "airflow": psu_fan_airflow, + "TempStatus": {"bus": 25, "addr": 0x58, "offset": 0x79, "way": "i2cword", "mask": 0x0004}, + "Temperature": { + "value": {"loc": "/sys/bus/i2c/devices/i2c-25/25-0058/hwmon/hwmon*/temp1_input", "way": "sysfs"}, + "Min": threshold.PSU_TEMP_MIN, + "Max": threshold.PSU_TEMP_MAX, + "Unit": Unit.Temperature, + "format": "float(float(%s)/1000)" + }, + "FanStatus": {"bus": 25, "addr": 0x58, "offset": 0x79, "way": "i2cword", "mask": 0x0400}, + "FanSpeed": { + "value": {"loc": "/sys/bus/i2c/devices/i2c-25/25-0058/hwmon/hwmon*/fan1_input", "way": "sysfs"}, + "Min": threshold.PSU_FAN_SPEED_MIN, + "Max": threshold.PSU_FAN_SPEED_MAX, + "Unit": Unit.Speed + }, + "psu_fan_tolerance": 40, + "InputsStatus": {"bus": 25, "addr": 0x58, "offset": 0x79, "way": "i2cword", "mask": 0x2000}, + "InputsType": {"bus": 25, "addr": 0x58, "offset": 0x80, "way": "i2c", 'psutypedecode': psutypedecode}, + "InputsVoltage": { + 'AC': { + "value": {"loc": "/sys/bus/i2c/devices/i2c-25/25-0058/hwmon/hwmon*/in1_input", "way": "sysfs"}, + "Min": threshold.PSU_AC_INPUT_VOLTAGE_MIN, + "Max": threshold.PSU_AC_INPUT_VOLTAGE_MAX, + "Unit": Unit.Voltage, + "format": "float(float(%s)/1000)" + + }, + 'DC': { + "value": {"loc": "/sys/bus/i2c/devices/i2c-25/25-0058/hwmon/hwmon*/in1_input", "way": "sysfs"}, + "Min": threshold.PSU_DC_INPUT_VOLTAGE_MIN, + "Max": threshold.PSU_DC_INPUT_VOLTAGE_MAX, + "Unit": Unit.Voltage, + "format": "float(float(%s)/1000)" + }, + 'other': { + "value": {"loc": "/sys/bus/i2c/devices/i2c-25/25-0058/hwmon/hwmon*/in1_input", "way": "sysfs"}, + "Min": threshold.ERR_VALUE, + "Max": threshold.ERR_VALUE, + "Unit": Unit.Voltage, + "format": "float(float(%s)/1000)" + } + }, + "InputsCurrent": { + "value": {"loc": "/sys/bus/i2c/devices/i2c-25/25-0058/hwmon/hwmon*/curr1_input", "way": "sysfs"}, + "Min": threshold.PSU_INPUT_CURRENT_MIN, + "Max": threshold.PSU_INPUT_CURRENT_MAX, + "Unit": Unit.Current, + "format": "float(float(%s)/1000)" + }, + "InputsPower": { + "value": {"loc": "/sys/bus/i2c/devices/i2c-25/25-0058/hwmon/hwmon*/power1_input", "way": "sysfs"}, + "Min": threshold.PSU_INPUT_POWER_MIN, + "Max": threshold.PSU_INPUT_POWER_MAX, + "Unit": Unit.Power, + "format": "float(float(%s)/1000000)" + }, + "OutputsStatus": {"bus": 25, "addr": 0x58, "offset": 0x79, "way": "i2cword", "mask": 0x8800}, + "OutputsVoltage": { + "value": {"loc": "/sys/bus/i2c/devices/i2c-25/25-0058/hwmon/hwmon*/in2_input", "way": "sysfs"}, + "Min": threshold.PSU_OUTPUT_VOLTAGE_MIN, + "Max": threshold.PSU_OUTPUT_VOLTAGE_MAX, + "Unit": Unit.Voltage, + "format": "float(float(%s)/1000)" + }, + "OutputsCurrent": { + "value": {"loc": "/sys/bus/i2c/devices/i2c-25/25-0058/hwmon/hwmon*/curr2_input", "way": "sysfs"}, + "Min": threshold.PSU_OUTPUT_CURRENT_MIN, + "Max": threshold.PSU_OUTPUT_CURRENT_MAX, + "Unit": Unit.Current, + "format": "float(float(%s)/1000)" + }, + "OutputsPower": { + "value": {"loc": "/sys/bus/i2c/devices/i2c-25/25-0058/hwmon/hwmon*/power2_input", "way": "sysfs"}, + "Min": threshold.PSU_OUTPUT_POWER_MIN, + "Max": threshold.PSU_OUTPUT_POWER_MAX, + "Unit": Unit.Power, + "format": "float(float(%s)/1000000)" + }, + } + ], + "temps": [ + { + "name": "SWITCH_TEMP", + "temp_id": "TEMP1", + "Temperature": { + "value": {"loc": "/sys/bus/i2c/devices/3-0044/hwmon/hwmon*/temp99_input", "way": "sysfs"}, + "Min": -30000, + "Low": 0, + "High": 105000, + "Max": 110000, + "Unit": Unit.Temperature, + "format": "float(float(%s)/1000)" + } + }, + { + "name": "CPU_TEMP", + "temp_id": "TEMP2", + "Temperature": { + "value": {"loc": "/sys/bus/platform/devices/coretemp.0/hwmon/hwmon*/temp1_input", "way": "sysfs"}, + "Min": -15000, + "Low": 0, + "High": 100000, + "Max": 102000, + "Unit": Unit.Temperature, + "format": "float(float(%s)/1000)" + } + }, + { + "name": "INLET_TEMP", + "temp_id": "TEMP3", + "Temperature": { + "value": {"loc": "/sys/bus/i2c/devices/3-004c/hwmon/hwmon*/temp1_input", "way": "sysfs"}, + "Min": -30000, + "Low": 0, + "High": 55000, + "Max": 60000, + "Unit": Unit.Temperature, + "format": "float(float(%s)/1000)" + }, + "fix_value": { + "fix_type": "config", + "addend": -3, + } + }, + { + "name": "OUTLET_TEMP", + "temp_id": "TEMP4", + "Temperature": { + "value": {"loc": "/sys/bus/i2c/devices/3-0048/hwmon/hwmon*/temp1_input", "way": "sysfs"}, + "Min": -30000, + "Low": 0, + "High": 75000, + "Max": 80000, + "Unit": Unit.Temperature, + "format": "float(float(%s)/1000)" + } + }, + { + "name": "BOARD_TEMP", + "temp_id": "TEMP5", + "api_name": "MAC_OUT_TEMP", + "Temperature": { + "value": {"loc": "/sys/bus/i2c/devices/3-0049/hwmon/hwmon*/temp1_input", "way": "sysfs"}, + "Min": -30000, + "Low": 0, + "High": 75000, + "Max": 80000, + "Unit": Unit.Temperature, + "format": "float(float(%s)/1000)" + } + }, + { + "name": "MAC_IN_TEMP", + "temp_id": "TEMP6", + "Temperature": { + "value": {"loc": "/sys/bus/i2c/devices/3-004a/hwmon/hwmon*/temp1_input", "way": "sysfs"}, + "Min": -30000, + "Low": 0, + "High": 75000, + "Max": 80000, + "Unit": Unit.Temperature, + "format": "float(float(%s)/1000)" + } + }, + { + "name": "PSU1_TEMP", + "temp_id": "TEMP7", + "Temperature": { + "value": {"loc": "/sys/bus/i2c/devices/i2c-24/24-0058/hwmon/hwmon*/temp1_input", "way": "sysfs"}, + "Min": -20000, + "Low": 0, + "High": 55000, + "Max": 60000, + "Unit": Unit.Temperature, + "format": "float(float(%s)/1000)" + } + }, + { + "name": "PSU2_TEMP", + "temp_id": "TEMP8", + "Temperature": { + "value": {"loc": "/sys/bus/i2c/devices/i2c-25/25-0058/hwmon/hwmon*/temp1_input", "way": "sysfs"}, + "Min": -20000, + "Low": 0, + "High": 55000, + "Max": 60000, + "Unit": Unit.Temperature, + "format": "float(float(%s)/1000)" + } + }, + { + "name": "SFF_TEMP", + "Temperature": { + "value": {"loc": "/tmp/highest_sff_temp", "way": "sysfs", "flock_path": "/tmp/highest_sff_temp"}, + "Min": -30000, + "Low": 0, + "High": 90000, + "Max": 100000, + "Unit": Unit.Temperature, + "format": "float(float(%s)/1000)" + }, + "invalid": -10000, + "error": -9999, + } + ], + "leds": [ + { + "name": "FRONT_SYS_LED", + "led_type": "SYS_LED", + "led": {"bus": 6, "addr": 0x0d, "offset": 0x72, "way": "i2c"}, + "led_attrs": { + "off": 0x00, "red_flash": 0x01, "red": 0x02, + "green_flash": 0x03, "green": 0x04, "amber_flash": 0x05, + "amber": 0x06, "mask": 0x07 + }, + }, + { + "name": "FRONT_PSU_LED", + "led_type": "PSU_LED", + "led": {"bus": 6, "addr": 0x0d, "offset": 0x73, "way": "i2c"}, + "led_attrs": { + "off": 0x10, "red_flash": 0x11, "red": 0x12, + "green_flash": 0x13, "green": 0x14, "amber_flash": 0x15, + "amber": 0x16, "mask": 0x17 + }, + }, + { + "name": "FRONT_FAN_LED", + "led_type": "FAN_LED", + "led": {"bus": 6, "addr": 0x0d, "offset": 0x74, "way": "i2c"}, + "led_attrs": { + "off": 0x10, "red_flash": 0x11, "red": 0x12, + "green_flash": 0x13, "green": 0x14, "amber_flash": 0x15, + "amber": 0x16, "mask": 0x17 + }, + }, + ], + "fans": [ + { + "name": "FAN1", + "airflow": fanairflow, + "e2loc": {'loc': '/sys/bus/i2c/devices/i2c-16/16-0050/eeprom', 'way': 'sysfs'}, + "present": {"loc": "/sys/wb_plat/fan/fan1/present", "way": "sysfs", "mask": 0x01, "okval": 1}, + "SpeedMin": threshold.FAN_SPEED_MIN, + "SpeedMax": threshold.FRONT_FAN_SPEED_MAX, + "led": {"bus": 2, "addr": 0x0d, "offset": 0x3b, "way": "i2c"}, + "led_attrs": { + "off": 0x0b, "red_flash": 0x0e, "red": 0x0a, + "green_flash": 0x0d, "green": 0x09, "amber_flash": 0x07, + "amber": 0x03, "mask": 0x0f + }, + "PowerMax": 38.4, + "Rotor": { + "Rotor1_config": { + "name": "Rotor1", + "Set_speed": {"bus": 2, "addr": 0x0d, "offset": 0x14, "way": "i2c"}, + "Running": {"loc": "/sys/wb_plat/fan/fan1/motor1/status", "way": "sysfs", "mask": 0x01, "is_runing": 1}, + "HwAlarm": {"loc": "/sys/wb_plat/fan/fan1/motor1/status", "way": "sysfs", "mask": 0x01, "no_alarm": 1}, + "SpeedMin": threshold.FAN_SPEED_MIN, + "SpeedMax": threshold.FRONT_FAN_SPEED_MAX, + "Speed": { + "value": {"loc": "/sys/wb_plat/fan/fan1/motor1/speed", "way": "sysfs"}, + "Min": threshold.FAN_SPEED_MIN, + "Max": threshold.FRONT_FAN_SPEED_MAX, + "Unit": Unit.Speed, + }, + }, + "Rotor2_config": { + "name": "Rotor2", + "Set_speed": {"bus": 2, "addr": 0x0d, "offset": 0x14, "way": "i2c"}, + "Running": {"loc": "/sys/wb_plat/fan/fan1/motor0/status", "way": "sysfs", "mask": 0x01, "is_runing": 1}, + "HwAlarm": {"loc": "/sys/wb_plat/fan/fan1/motor0/status", "way": "sysfs", "mask": 0x01, "no_alarm": 1}, + "SpeedMin": threshold.FAN_SPEED_MIN, + "SpeedMax": threshold.REAR_FAN_SPEED_MAX, + "Speed": { + "value": {"loc": "/sys/wb_plat/fan/fan1/motor0/speed", "way": "sysfs"}, + "Min": threshold.FAN_SPEED_MIN, + "Max": threshold.REAR_FAN_SPEED_MAX, + "Unit": Unit.Speed, + }, + }, + }, + }, + { + "name": "FAN2", + "airflow": fanairflow, + "e2loc": {'loc': '/sys/bus/i2c/devices/i2c-17/17-0050/eeprom', 'way': 'sysfs'}, + "present": {"loc": "/sys/wb_plat/fan/fan2/present", "way": "sysfs", "mask": 0x01, "okval": 1}, + "SpeedMin": threshold.FAN_SPEED_MIN, + "SpeedMax": threshold.FRONT_FAN_SPEED_MAX, + "led": {"bus": 2, "addr": 0x0d, "offset": 0x3c, "way": "i2c"}, + "led_attrs": { + "off": 0x0b, "red_flash": 0x0e, "red": 0x0a, + "green_flash": 0x0d, "green": 0x09, "amber_flash": 0x07, + "amber": 0x03, "mask": 0x0f + }, + "PowerMax": 38.4, + "Rotor": { + "Rotor1_config": { + "name": "Rotor1", + "Set_speed": {"bus": 2, "addr": 0x0d, "offset": 0x15, "way": "i2c"}, + "Running": {"loc": "/sys/wb_plat/fan/fan2/motor1/status", "way": "sysfs", "mask": 0x01, "is_runing": 1}, + "HwAlarm": {"loc": "/sys/wb_plat/fan/fan2/motor1/status", "way": "sysfs", "mask": 0x01, "no_alarm": 1}, + "SpeedMin": threshold.FAN_SPEED_MIN, + "SpeedMax": threshold.FRONT_FAN_SPEED_MAX, + "Speed": { + "value": {"loc": "/sys/wb_plat/fan/fan2/motor1/speed", "way": "sysfs"}, + "Min": threshold.FAN_SPEED_MIN, + "Max": threshold.FRONT_FAN_SPEED_MAX, + "Unit": Unit.Speed, + }, + }, + "Rotor2_config": { + "name": "Rotor2", + "Set_speed": {"bus": 2, "addr": 0x0d, "offset": 0x15, "way": "i2c"}, + "Running": {"loc": "/sys/wb_plat/fan/fan2/motor0/status", "way": "sysfs", "mask": 0x01, "is_runing": 1}, + "HwAlarm": {"loc": "/sys/wb_plat/fan/fan2/motor0/status", "way": "sysfs", "mask": 0x01, "no_alarm": 1}, + "SpeedMin": threshold.FAN_SPEED_MIN, + "SpeedMax": threshold.REAR_FAN_SPEED_MAX, + "Speed": { + "value": {"loc": "/sys/wb_plat/fan/fan2/motor0/speed", "way": "sysfs"}, + "Min": threshold.FAN_SPEED_MIN, + "Max": threshold.REAR_FAN_SPEED_MAX, + "Unit": Unit.Speed, + }, + }, + }, + }, + { + "name": "FAN3", + "airflow": fanairflow, + "e2loc": {'loc': '/sys/bus/i2c/devices/i2c-18/18-0050/eeprom', 'way': 'sysfs'}, + "present": {"loc": "/sys/wb_plat/fan/fan3/present", "way": "sysfs", "mask": 0x01, "okval": 1}, + "SpeedMin": threshold.FAN_SPEED_MIN, + "SpeedMax": threshold.FRONT_FAN_SPEED_MAX, + "led": {"bus": 2, "addr": 0x0d, "offset": 0x3d, "way": "i2c"}, + "led_attrs": { + "off": 0x0b, "red_flash": 0x0e, "red": 0x0a, + "green_flash": 0x0d, "green": 0x09, "amber_flash": 0x07, + "amber": 0x03, "mask": 0x0f + }, + "PowerMax": 38.4, + "Rotor": { + "Rotor1_config": { + "name": "Rotor1", + "Set_speed": {"bus": 2, "addr": 0x0d, "offset": 0x16, "way": "i2c"}, + "Running": {"loc": "/sys/wb_plat/fan/fan3/motor1/status", "way": "sysfs", "mask": 0x01, "is_runing": 1}, + "HwAlarm": {"loc": "/sys/wb_plat/fan/fan3/motor1/status", "way": "sysfs", "mask": 0x01, "no_alarm": 1}, + "SpeedMin": threshold.FAN_SPEED_MIN, + "SpeedMax": threshold.FRONT_FAN_SPEED_MAX, + "Speed": { + "value": {"loc": "/sys/wb_plat/fan/fan3/motor1/speed", "way": "sysfs"}, + "Min": threshold.FAN_SPEED_MIN, + "Max": threshold.FRONT_FAN_SPEED_MAX, + "Unit": Unit.Speed, + }, + }, + "Rotor2_config": { + "name": "Rotor2", + "Set_speed": {"bus": 2, "addr": 0x0d, "offset": 0x16, "way": "i2c"}, + "Running": {"loc": "/sys/wb_plat/fan/fan3/motor0/status", "way": "sysfs", "mask": 0x01, "is_runing": 1}, + "HwAlarm": {"loc": "/sys/wb_plat/fan/fan3/motor0/status", "way": "sysfs", "mask": 0x01, "no_alarm": 1}, + "SpeedMin": threshold.FAN_SPEED_MIN, + "SpeedMax": threshold.REAR_FAN_SPEED_MAX, + "Speed": { + "value": {"loc": "/sys/wb_plat/fan/fan3/motor0/speed", "way": "sysfs"}, + "Min": threshold.FAN_SPEED_MIN, + "Max": threshold.REAR_FAN_SPEED_MAX, + "Unit": Unit.Speed, + }, + }, + }, + }, + + { + "name": "FAN4", + "airflow": fanairflow, + "e2loc": {'loc': '/sys/bus/i2c/devices/i2c-19/19-0050/eeprom', 'way': 'sysfs'}, + "present": {"loc": "/sys/wb_plat/fan/fan4/present", "way": "sysfs", "mask": 0x01, "okval": 1}, + "SpeedMin": threshold.FAN_SPEED_MIN, + "SpeedMax": threshold.FRONT_FAN_SPEED_MAX, + "led": {"bus": 2, "addr": 0x0d, "offset": 0x3e, "way": "i2c"}, + "led_attrs": { + "off": 0x0b, "red_flash": 0x0e, "red": 0x0a, + "green_flash": 0x0d, "green": 0x09, "amber_flash": 0x07, + "amber": 0x03, "mask": 0x0f + }, + "PowerMax": 38.4, + "Rotor": { + "Rotor1_config": { + "name": "Rotor1", + "Set_speed": {"bus": 2, "addr": 0x0d, "offset": 0x17, "way": "i2c"}, + "Running": {"loc": "/sys/wb_plat/fan/fan4/motor1/status", "way": "sysfs", "mask": 0x01, "is_runing": 1}, + "HwAlarm": {"loc": "/sys/wb_plat/fan/fan4/motor1/status", "way": "sysfs", "mask": 0x01, "no_alarm": 1}, + "SpeedMin": threshold.FAN_SPEED_MIN, + "SpeedMax": threshold.FRONT_FAN_SPEED_MAX, + "Speed": { + "value": {"loc": "/sys/wb_plat/fan/fan4/motor1/speed", "way": "sysfs"}, + "Min": threshold.FAN_SPEED_MIN, + "Max": threshold.FRONT_FAN_SPEED_MAX, + "Unit": Unit.Speed, + }, + }, + "Rotor2_config": { + "name": "Rotor2", + "Set_speed": {"bus": 2, "addr": 0x0d, "offset": 0x17, "way": "i2c"}, + "Running": {"loc": "/sys/wb_plat/fan/fan4/motor0/status", "way": "sysfs", "mask": 0x01, "is_runing": 1}, + "HwAlarm": {"loc": "/sys/wb_plat/fan/fan4/motor0/status", "way": "sysfs", "mask": 0x01, "no_alarm": 1}, + "SpeedMin": threshold.FAN_SPEED_MIN, + "SpeedMax": threshold.REAR_FAN_SPEED_MAX, + "Speed": { + "value": {"loc": "/sys/wb_plat/fan/fan4/motor0/speed", "way": "sysfs"}, + "Min": threshold.FAN_SPEED_MIN, + "Max": threshold.REAR_FAN_SPEED_MAX, + "Unit": Unit.Speed, + }, + }, + }, + }, + + ], + "cplds": [ + { + "name": "CPU_CPLD", + "cpld_id": "CPLD1", + "VersionFile": {"loc": "/dev/cpld0", "offset": 0, "len": 4, "way": "devfile_ascii"}, + "desc": "Used for system power", + "slot": 0, + "warm": 0, + }, + { + "name": "CONNECT_CPLD", + "cpld_id": "CPLD2", + "VersionFile": {"loc": "/dev/cpld1", "offset": 0, "len": 4, "way": "devfile_ascii"}, + "desc": "Used for base functions", + "slot": 0, + "warm": 0, + }, + { + "name": "CONNECT_CPLD-FAN", + "cpld_id": "CPLD3", + "VersionFile": {"loc": "/dev/cpld2", "offset": 0, "len": 4, "way": "devfile_ascii"}, + "desc": "Used for fan modules", + "slot": 0, + "warm": 0, + }, + { + "name": "MAC_CPLD1", + "cpld_id": "CPLD4", + "VersionFile": {"loc": "/dev/cpld3", "offset": 0, "len": 4, "way": "devfile_ascii"}, + "desc": "Used for sff modules", + "slot": 0, + "warm": 0, + }, + { + "name": "MAC_CPLD2", + "cpld_id": "CPLD5", + "VersionFile": {"loc": "/dev/cpld4", "offset": 0, "len": 4, "way": "devfile_ascii"}, + "desc": "Used for sff modules", + "slot": 0, + "warm": 0, + }, + { + "name": "FPGA", + "cpld_id": "CPLD6", + "VersionFile": {"loc": "/dev/fpga0", "offset": 0, "len": 4, "way": "devfile_ascii"}, + "desc": "Used for base functions", + "slot": 0, + "format": "little_endian", + "warm": 0, + }, + { + "name": "BIOS", + "cpld_id": "CPLD7", + "VersionFile": {"cmd": "dmidecode -s bios-version", "way": "cmd"}, + "desc": "Performs initialization of hardware components during booting", + "slot": 0, + "type": "str", + "warm": 0, + }, + ], + "dcdc": [ + { + "name": "Switch_ZSFP1_3v3_C", + "dcdc_id": "DCDC1", + "Min": -1000, + "value": { + "loc": "/sys/bus/i2c/devices/7-0040/hwmon/hwmon*/curr1_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "A", + "Max": 22000, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Switch_QSFP1_3v3_C", + "dcdc_id": "DCDC2", + "Min": -1000, + "value": { + "loc": "/sys/bus/i2c/devices/7-0040/hwmon/hwmon*/curr3_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "A", + "Max": 22000, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Switch_5v0_C", + "dcdc_id": "DCDC3", + "Min": -1000, + "value": { + "loc": "/sys/bus/i2c/devices/7-0040/hwmon/hwmon*/curr2_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "A", + "Max": 1000, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Switch_ZSFP1_3v3_V", + "dcdc_id": "DCDC4", + "Min": 2640, + "value": { + "loc": "/sys/bus/i2c/devices/7-0040/hwmon/hwmon*/in1_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "V", + "Max": 3960, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Switch_QSFP1_3v3_V", + "dcdc_id": "DCDC5", + "Min": 2640, + "value": { + "loc": "/sys/bus/i2c/devices/7-0040/hwmon/hwmon*/in3_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "V", + "Max": 3960, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Switch_5v0_V", + "dcdc_id": "DCDC6", + "Min": 4000, + "value": { + "loc": "/sys/bus/i2c/devices/7-0040/hwmon/hwmon*/in2_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "V", + "Max": 6000, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Switch_1v2_C", + "dcdc_id": "DCDC7", + "Min": -1000, + "value": { + "loc": "/sys/bus/i2c/devices/7-0041/hwmon/hwmon*/curr1_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "A", + "Max": 2000, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Switch_3v3_C", + "dcdc_id": "DCDC8", + "Min": -1000, + "value": { + "loc": "/sys/bus/i2c/devices/7-0041/hwmon/hwmon*/curr2_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "A", + "Max": 1000, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Switch_Cpld_3v3_C", + "dcdc_id": "DCDC9", + "Min": -1000, + "value": { + "loc": "/sys/bus/i2c/devices/7-0041/hwmon/hwmon*/curr3_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "A", + "Max": 2000, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Switch_1v2_V", + "dcdc_id": "DCDC10", + "Min": 960, + "value": { + "loc": "/sys/bus/i2c/devices/7-0041/hwmon/hwmon*/in1_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "V", + "Max": 1440, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Switch_3v3_V", + "dcdc_id": "DCDC11", + "Min": 2640, + "value": { + "loc": "/sys/bus/i2c/devices/7-0041/hwmon/hwmon*/in2_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "V", + "Max": 3960, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Switch_Cpld_3v3_V", + "dcdc_id": "DCDC12", + "Min": 2640, + "value": { + "loc": "/sys/bus/i2c/devices/7-0041/hwmon/hwmon*/in3_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "V", + "Max": 3960, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Con_1v2_C", + "dcdc_id": "DCDC13", + "Min": -1000, + "value": { + "loc": "/sys/bus/i2c/devices/7-0042/hwmon/hwmon*/curr1_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "A", + "Max": 1300, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Con_3v3_C", + "dcdc_id": "DCDC14", + "Min": -1000, + "value": { + "loc": "/sys/bus/i2c/devices/7-0042/hwmon/hwmon*/curr2_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "A", + "Max": 2800, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Con_SSD_3v3_C", + "dcdc_id": "DCDC15", + "Min": -1000, + "value": { + "loc": "/sys/bus/i2c/devices/7-0042/hwmon/hwmon*/curr3_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "A", + "Max": 4500, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Con_1v2_V", + "dcdc_id": "DCDC16", + "Min": 960, + "value": { + "loc": "/sys/bus/i2c/devices/7-0042/hwmon/hwmon*/in1_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "V", + "Max": 1440, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Con_3v3_V", + "dcdc_id": "DCDC17", + "Min": 2640, + "value": { + "loc": "/sys/bus/i2c/devices/7-0042/hwmon/hwmon*/in2_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "V", + "Max": 3960, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Con_SSD_3v3_V", + "dcdc_id": "DCDC18", + "Min": 2640, + "value": { + "loc": "/sys/bus/i2c/devices/7-0042/hwmon/hwmon*/in3_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "V", + "Max": 3960, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Cpu_3v3_C", + "dcdc_id": "DCDC19", + "Min": -1000, + "value": { + "loc": "/sys/bus/i2c/devices/7-0043/hwmon/hwmon*/curr1_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "A", + "Max": 4686, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Cpu_5v_C", + "dcdc_id": "DCDC20", + "Min": -1000, + "value": { + "loc": "/sys/bus/i2c/devices/7-0043/hwmon/hwmon*/curr2_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "A", + "Max": 2200, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Cpu_1v7_C", + "dcdc_id": "DCDC21", + "Min": -1000, + "value": { + "loc": "/sys/bus/i2c/devices/7-0043/hwmon/hwmon*/curr3_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "A", + "Max": 2200, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Cpu_3v3_V", + "dcdc_id": "DCDC22", + "Min": 2640, + "value": { + "loc": "/sys/bus/i2c/devices/7-0043/hwmon/hwmon*/in1_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "V", + "Max": 3960, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Cpu_5v_V", + "dcdc_id": "DCDC23", + "Min": 4000, + "value": { + "loc": "/sys/bus/i2c/devices/7-0043/hwmon/hwmon*/in2_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "V", + "Max": 6000, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Cpu_1v7_V", + "dcdc_id": "DCDC24", + "Min": 1360, + "value": { + "loc": "/sys/bus/i2c/devices/7-0043/hwmon/hwmon*/in3_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "V", + "Max": 2040, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Cpu_CORE_C", + "dcdc_id": "DCDC25", + "Min": -1000, + "value": { + "loc": "/sys/bus/i2c/devices/7-0060/hwmon/hwmon*/curr1_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "A", + "Max": 47300, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Cpu_1v05_C", + "dcdc_id": "DCDC26", + "Min": -1000, + "value": { + "loc": "/sys/bus/i2c/devices/7-0060/hwmon/hwmon*/curr2_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "A", + "Max": 15400, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Cpu_CORE_V", + "dcdc_id": "DCDC27", + "Min": 1456, + "value": { + "loc": "/sys/bus/i2c/devices/7-0060/hwmon/hwmon*/in2_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "V", + "Max": 2184, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Cpu_1v05_V", + "dcdc_id": "DCDC28", + "Min": 840, + "value": { + "loc": "/sys/bus/i2c/devices/7-0060/hwmon/hwmon*/in3_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "V", + "Max": 1260, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Switch_CORE_C", + "dcdc_id": "DCDC29", + "Min": -1000, + "value": { + "loc": "/sys/bus/i2c/devices/7-0064/hwmon/hwmon*/curr2_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "A", + "Max": 220000, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Switch_ANALOG_C", + "dcdc_id": "DCDC30", + "Min": -1000, + "value": { + "loc": "/sys/bus/i2c/devices/7-0064/hwmon/hwmon*/curr3_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "A", + "Max": 18000, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Switch_CORE_V", + "dcdc_id": "DCDC31", + "Min": 600, + "value": { + "loc": "/sys/bus/i2c/devices/7-0064/hwmon/hwmon*/in2_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "V", + "Max": 1200, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Switch_ANALOG_V", + "dcdc_id": "DCDC32", + "Min": 640, + "value": { + "loc": "/sys/bus/i2c/devices/7-0064/hwmon/hwmon*/in3_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "V", + "Max": 960, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Cpu_1v2_C", + "dcdc_id": "DCDC33", + "Min": -1000, + "value": { + "loc": "/sys/bus/i2c/devices/7-006c/hwmon/hwmon*/curr1_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "A", + "Max": 9900, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Cpu_2v23_C", + "dcdc_id": "DCDC34", + "Min": -1000, + "value": { + "loc": "/sys/bus/i2c/devices/7-006c/hwmon/hwmon*/curr2_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "A", + "Max": 2200, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Cpu_1v2_V", + "dcdc_id": "DCDC35", + "Min": 960, + "value": { + "loc": "/sys/bus/i2c/devices/7-006c/hwmon/hwmon*/in2_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "V", + "Max": 1440, + "format": "float(float(%s)/1000)", + }, + + { + "name": "Cpu_2v23_V", + "dcdc_id": "DCDC36", + "Min": 1784, + "value": { + "loc": "/sys/bus/i2c/devices/7-006c/hwmon/hwmon*/in3_input", + "way": "sysfs", + }, + "read_times": 5, + "Unit": "V", + "Max": 2676, + "format": "float(float(%s)/1000)", + }, + ], + "cpu": [ + { + "name": "cpu", + "reboot_cause_path": "/etc/sonic/.reboot/.previous-reboot-cause.txt" + } + ], + "sfps": { + "ver": '1.0', + "port_index_start": 1, + "port_num": 56, + "log_level": 2, + "eeprom_retry_times": 5, + "eeprom_retry_break_sec": 0.2, + "presence_cpld": { + "dev_id": { + 3: { + "offset": { + 0x30: "1-8", + 0x31: "9-16", + 0x32: "17-24", + }, + }, + 4: { + "offset": { + 0x30: "25-32", + 0x31: "33-40", + 0x32: "41-48", + 0x33: "49-56", + }, + }, + }, + }, + "presence_val_is_present": 0, + "eeprom_path": "/sys/bus/i2c/devices/i2c-%d/%d-0050/eeprom", + "eeprom_path_key": list(range(32, 88)), + "optoe_driver_path": "/sys/bus/i2c/devices/i2c-%d/%d-0050/dev_class", + "optoe_driver_key": list(range(32, 88)), + "txdis_cpld": { + "dev_id": { + 3: { + "offset": { + 0x60: "1-8", + 0x61: "9-16", + 0x62: "17-24", + }, + }, + 4: { + "offset": { + 0x60: "25-32", + 0x61: "33-40", + 0x62: "41-48", + }, + }, + }, + }, + "txdisable_val_is_on": 0, + "reset_cpld": { + "dev_id": { + 4: { + "offset": { + 0xb9: "49-56", + }, + }, + }, + }, + "reset_val_is_reset": 0, + } +} diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/hal-config/x86_64_ragile_ra_b6510_48v8c_r0_monitor.py b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/hal-config/x86_64_ragile_ra_b6510_48v8c_r0_monitor.py new file mode 100644 index 000000000000..aab279a21da2 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/hal-config/x86_64_ragile_ra_b6510_48v8c_r0_monitor.py @@ -0,0 +1,206 @@ +# coding:utf-8 + + +monitor = { + "openloop": { + "linear": { + "name": "linear", + "flag": 0, + "pwm_min": 0x80, + "pwm_max": 0xff, + "K": 11, + "tin_min": 38, + }, + "curve": { + "name": "curve", + "flag": 0, + "pwm_min": 0x5a, + "pwm_max": 0xff, + "a": 0.086, + "b": 0.318, + "c": 28, + "tin_min": 25, + }, + }, + + "pid": { + "CPU_TEMP": { + "name": "CPU_TEMP", + "flag": 1, + "type": "duty", + "pwm_min": 0x80, + "pwm_max": 0xff, + "Kp": 3, + "Ki": 0.5, + "Kd": 0.5, + "target": 89, + "value": [None, None, None], + }, + "SWITCH_TEMP": { + "name": "SWITCH_TEMP", + "flag": 1, + "type": "duty", + "pwm_min": 0x80, + "pwm_max": 0xff, + "Kp": 3, + "Ki": 0.4, + "Kd": 0.4, + "target": 82, + "value": [None, None, None], + }, + "OUTLET_TEMP": { + "name": "OUTLET_TEMP", + "flag": 0, + "type": "duty", + "pwm_min": 0x80, + "pwm_max": 0xff, + "Kp": 2, + "Ki": 0.4, + "Kd": 0.3, + "target": 65, + "value": [None, None, None], + }, + "BOARD_TEMP": { + "name": "BOARD_TEMP", + "flag": 0, + "type": "duty", + "pwm_min": 0x80, + "pwm_max": 0xff, + "Kp": 2, + "Ki": 0.4, + "Kd": 0.3, + "target": 65, + "value": [None, None, None], + }, + "SFF_TEMP": { + "name": "SFF_TEMP", + "flag": 1, + "type": "duty", + "pwm_min": 0x80, + "pwm_max": 0xff, + "Kp": 0.1, + "Ki": 0.4, + "Kd": 0, + "target": 60, + "value": [None, None, None], + }, + }, + + "hyst": { + "INLET_TEMP": { + "name": "INLET_TEMP", + "flag": 1, + "type": "duty", + "hyst_min": 50, # duty + "hyst_max": 100, # duty + "last_hyst_value": 50, # duty + "temp_min": 23, + "temp_max": 40, + "value": [None, None], + "rising": { + 23: 50, + 24: 50, + 25: 50, + 26: 53, + 27: 56, + 28: 59, + 29: 62, + 30: 65, + 31: 68, + 32: 71, + 33: 74, + 34: 77, + 35: 80, + 36: 84, + 37: 88, + 38: 92, + 39: 96, + 40: 100, + }, + "descending": { + 23: 50, + 24: 53, + 25: 56, + 26: 59, + 27: 62, + 28: 65, + 29: 68, + 30: 71, + 31: 74, + 32: 77, + 33: 80, + 34: 84, + 35: 88, + 36: 92, + 37: 96, + 38: 100, + 39: 100, + 40: 100, + }, + } + }, + + "temps_threshold": { + "SWITCH_TEMP": {"name": "SWITCH_TEMP", "warning": 100, "critical": 105}, + "INLET_TEMP": {"name": "INLET_TEMP", "warning": 40, "critical": 50}, + "BOARD_TEMP": {"name": "BOARD_TEMP", "warning": 70, "critical": 80}, + "OUTLET_TEMP": {"name": "OUTLET_TEMP", "warning": 70, "critical": 80}, + "CPU_TEMP": {"name": "CPU_TEMP", "warning": 100, "critical": 102}, + "SFF_TEMP": {"name": "SFF_TEMP", "warning": 999, "critical": 1000, "ignore_threshold": 1, "invalid": -10000, "error": -9999}, + }, + + "fancontrol_para": { + "interval": 5, + "fan_air_flow_monitor": 1, + "psu_air_flow_monitor": 1, + "max_pwm": 0xff, + "min_pwm": 0x80, + "abnormal_pwm": 0xff, + "warning_pwm": 0xff, + "temp_invalid_pid_pwm": 0x80, + "temp_error_pid_pwm": 0x80, + "temp_fail_num": 3, + "check_temp_fail": [ + {"temp_name": "INLET_TEMP"}, + {"temp_name": "SWITCH_TEMP"}, + {"temp_name": "CPU_TEMP"}, + ], + "temp_warning_num": 3, # temp over warning 3 times continuously + "temp_critical_num": 3, # temp over critical 3 times continuously + "temp_warning_countdown": 60, # 5 min warning speed after not warning + "temp_critical_countdown": 60, # 5 min full speed after not critical + "rotor_error_count": 6, # fan rotor error 6 times continuously + "inlet_mac_diff": 999, + "check_crit_reboot_flag": 1, + "check_crit_reboot_num": 3, + "check_crit_sleep_time": 20, + "psu_absent_fullspeed_num": 0xFF, + "fan_absent_fullspeed_num": 1, + "rotor_error_fullspeed_num": 1, + }, + + "ledcontrol_para": { + "interval": 5, + "checkpsu": 0, # 0: sys led don't follow psu led + "checkfan": 0, # 0: sys led don't follow fan led + "psu_amber_num": 1, + "fan_amber_num": 1, + "board_sys_led": [ + {"led_name": "FRONT_SYS_LED"}, + ], + "board_psu_led": [ + {"led_name": "FRONT_PSU_LED"}, + ], + "board_fan_led": [ + {"led_name": "FRONT_FAN_LED"}, + ], + "psu_air_flow_monitor": 1, + "fan_air_flow_monitor": 1, + "psu_air_flow_amber_num": 1, + "fan_air_flow_amber_num": 1, + }, + "otp_reboot_judge_file": { + "otp_switch_reboot_judge_file": "/etc/.otp_switch_reboot_flag", + "otp_other_reboot_judge_file": "/etc/.otp_other_reboot_flag", + }, +} diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/modules/driver/Makefile b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/modules/driver/Makefile index f10216ec4d5a..e59ffd7ee67d 100755 --- a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/modules/driver/Makefile +++ b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/modules/driver/Makefile @@ -1 +1,15 @@ -obj-m := rg_cpld.o +MAKEFILE_FILE_PATH = $(abspath $(lastword $(MAKEFILE_LIST))) +MODULES_DIR = $(abspath $(MAKEFILE_FILE_PATH)/../../../../common/modules) +FIRMWARE_UPGRADE_PATH = $(abspath $(MAKEFILE_FILE_PATH)/../../../../common/app/firmware_upgrade/firmware_driver/include) + +EXTRA_CFLAGS+= -I$(MODULES_DIR) +EXTRA_CFLAGS+= -I$(MODULES_DIR)/linux-5.10 +EXTRA_CFLAGS+= -I$(FIRMWARE_UPGRADE_PATH) + +obj-m := wb_pcie_dev_device.o +obj-m += wb_i2c_mux_pca954x_device.o +obj-m += wb_i2c_ocores_device.o +obj-m += wb_lpc_drv_device.o +obj-m += wb_i2c_dev_device.o +obj-m += wb_io_dev_device.o +obj-m += wb_firmware_upgrade_device.o diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/modules/driver/rg_cpld.c b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/modules/driver/rg_cpld.c deleted file mode 100755 index 885a727be683..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/modules/driver/rg_cpld.c +++ /dev/null @@ -1,602 +0,0 @@ -/* - * rg_cpld.c - A driver for cpld - * - * Copyright (c) 2019 - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - - -/* debug level */ -typedef enum { - DBG_START, - DBG_VERBOSE, - DBG_KEY, - DBG_WARN, - DBG_ERROR, - DBG_END, -} dbg_level_t; - -static int debuglevel = 0; -module_param(debuglevel, int, S_IRUGO); - -#define DBG_DEBUG(fmt, arg...) do { \ - if ( debuglevel > DBG_START && debuglevel < DBG_ERROR) { \ - printk(KERN_INFO "[DEBUG]:<%s, %d>:"fmt, __FUNCTION__, __LINE__, ##arg); \ - } else if ( debuglevel >= DBG_ERROR ) { \ - printk(KERN_ERR "[DEBUG]:<%s, %d>:"fmt, __FUNCTION__, __LINE__, ##arg); \ - } else { } \ -} while (0) - -#define DBG_ERROR(fmt, arg...) do { \ - if ( debuglevel > DBG_START) { \ - printk(KERN_ERR "[ERROR]:<%s, %d>:"fmt, __FUNCTION__, __LINE__, ##arg); \ - } \ -} while (0) - -static const unsigned short rg_i2c_cpld[] = { 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, I2C_CLIENT_END }; - -#define CPLD_SIZE 256 -#define CPLD_I2C_RETRY_TIMES 3 -#define READ_TEMP_FAIL 1000000 - -struct cpld_data { - struct i2c_client *client; - struct device *hwmon_dev; - struct mutex update_lock; - char valid; /* !=0 if registers are valid */ - unsigned long last_updated; /* In jiffies */ - u8 data[CPLD_SIZE]; /* Register value */ -}; - -static s32 cpld_i2c_smbus_read_byte_data(const struct i2c_client *client, u8 command) -{ - int try; - s32 ret; - - ret = -1; - for (try = 0; try < CPLD_I2C_RETRY_TIMES; try++) { - if ((ret = i2c_smbus_read_byte_data(client, command) ) >= 0 ) - break; - } - return ret; -} - -static s32 cpld_i2c_smbus_read_i2c_block_data(const struct i2c_client *client, - u8 command, u8 length, u8 *values) -{ - int try; - s32 ret; - - ret = -1; - for (try = 0; try < CPLD_I2C_RETRY_TIMES; try++) { - if ((ret = i2c_smbus_read_i2c_block_data(client, command, length, values) ) >= 0 ) - break; - } - return ret; -} - -static ssize_t show_fan_rpm_value(struct device *dev, struct device_attribute *da, char *buf) -{ - struct cpld_data *data = dev_get_drvdata(dev); - struct i2c_client *client = data->client; - int index = to_sensor_dev_attr_2(da)->index; - uint8_t size; - s32 status; - s32 ret_t; - - ret_t = 0; - status = -1; - size = 0; - mutex_lock(&data->update_lock); - status = cpld_i2c_smbus_read_byte_data(client, index); - if (status < 0) { - mutex_unlock(&data->update_lock); - return 0; - } - data->data[0] = status; - status = cpld_i2c_smbus_read_byte_data(client, index + 1); - if (status < 0) { - mutex_unlock(&data->update_lock); - return 0; - } - data->data[1] = status; - DBG_DEBUG("cpld reg pos:0x%x value:0x%x\n", index, data->data[0]); - DBG_DEBUG("cpld reg pos:0x%x value:0x%x\n", index + 1, data->data[1]); - ret_t = (data->data[1] << 8) + data->data[0] ; - if (ret_t == 0 ) { - size = snprintf(buf, CPLD_SIZE, "%d\n", ret_t); - } else if (ret_t == 0xffff) { - size = snprintf(buf, CPLD_SIZE, "%d\n", 0); - } else { - size = snprintf(buf, CPLD_SIZE, "%d\n", 15000000 / ret_t); - } - mutex_unlock(&data->update_lock); - return size; -} - -static ssize_t set_cpld_sysfs_value(struct device *dev, struct device_attribute *da, const char *buf, size_t -count) -{ - struct sensor_device_attribute *attr = to_sensor_dev_attr(da); - struct i2c_client *client = to_i2c_client(dev); - struct cpld_data *data = i2c_get_clientdata(client); - unsigned long val; - int err; - - err = kstrtoul(buf, 16, &val); - if (err) - return err; - if ((val < 0) || (val > 0xff)) { - DBG_ERROR("please enter 0x00 ~ 0xff\n"); - return -1; - } - mutex_lock(&data->update_lock); - data->data[0] = (u8)val; - DBG_DEBUG("pos: 0x%02x count = %ld, data = 0x%02x\n", attr->index, count, data->data[0]); - i2c_smbus_write_byte_data(client, attr->index, data->data[0]); - mutex_unlock(&data->update_lock); - - return count; -} - -static ssize_t show_cpld_version(struct device *dev, struct device_attribute *da, char *buf) -{ - struct i2c_client *client = to_i2c_client(dev); - struct cpld_data *data = i2c_get_clientdata(client); - s32 status; - - status = -1; - mutex_lock(&data->update_lock); - status = cpld_i2c_smbus_read_i2c_block_data(client, 0, 4, data->data); - if (status < 0) { - mutex_unlock(&data->update_lock); - return 0; - } - mutex_unlock(&data->update_lock); - return sprintf(buf, "%02x %02x %02x %02x \n", data->data[0], data->data[1], data->data[2], - data->data[3]); -} - -static ssize_t show_cpld_sysfs_value(struct device *dev, struct device_attribute *da, char *buf) -{ - struct sensor_device_attribute *attr = to_sensor_dev_attr(da); - struct i2c_client *client = to_i2c_client(dev); - struct cpld_data *data = i2c_get_clientdata(client); - s32 status; - - status = -1; - mutex_lock(&data->update_lock); - status = cpld_i2c_smbus_read_byte_data(client, attr->index); - if (status < 0) { - mutex_unlock(&data->update_lock); - return 0; - } - data->data[0] = status; - DBG_DEBUG("cpld reg pos:0x%x value:0x%02x\n", attr->index, data->data[0]); - mutex_unlock(&data->update_lock); - return sprintf(buf, "%02x\n", data->data[0]); -} - -static ssize_t show_mac_temp_value(struct device *dev, struct device_attribute *da, char *buf) -{ - struct cpld_data *data = dev_get_drvdata(dev); - struct i2c_client *client = data->client; - int index = to_sensor_dev_attr_2(da)->index; - int tmp_value, value; - s32 status; - - status = -1; - mutex_lock(&data->update_lock); - - status = cpld_i2c_smbus_read_byte_data(client, index); - if (status < 0) { - mutex_unlock(&data->update_lock); - return snprintf(buf, CPLD_SIZE, "%d\n", -READ_TEMP_FAIL); - } - data->data[0] = status; - status = cpld_i2c_smbus_read_byte_data(client, index + 1); - if (status < 0) { - mutex_unlock(&data->update_lock); - return snprintf(buf, CPLD_SIZE, "%d\n", -READ_TEMP_FAIL); - } - data->data[1] = status; - DBG_DEBUG("cpld reg pos:0x%x value:0x%x\n", index, data->data[0]); - DBG_DEBUG("cpld reg pos:0x%x value:0x%x\n", index + 1, data->data[1]); - mutex_unlock(&data->update_lock); - - tmp_value = (data->data[1] << 8) + data->data[0]; - if (tmp_value == 0) { - DBG_ERROR("invalid cpld value : %d.\n", tmp_value); - return snprintf(buf, CPLD_SIZE, "%d\n", -READ_TEMP_FAIL); - } - - DBG_DEBUG("tmp_value = 0x%x\n", tmp_value); - value = 434100 - (12500000 / (tmp_value * 100 - 1) *535); - if ((value / 1000 < -70) || (value / 1000 > 200)) { - return snprintf(buf, CPLD_SIZE, "%d\n", -READ_TEMP_FAIL); - } - - return snprintf(buf, CPLD_SIZE, "%d\n", value); - -} - -/* common */ -static SENSOR_DEVICE_ATTR(cpld_version, S_IRUGO | S_IWUSR, show_cpld_version, NULL, 0); - -/*0x37 hwmon*/ -static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO | S_IWUSR ,show_fan_rpm_value, NULL, 0x1B); -static SENSOR_DEVICE_ATTR(fan2_input, S_IRUGO | S_IWUSR ,show_fan_rpm_value, NULL, 0x1D); -static SENSOR_DEVICE_ATTR(fan3_input, S_IRUGO | S_IWUSR ,show_fan_rpm_value, NULL, 0x1F); -static SENSOR_DEVICE_ATTR(fan4_input, S_IRUGO | S_IWUSR ,show_fan_rpm_value, NULL, 0x21); - -/* 0x32 */ -static SENSOR_DEVICE_ATTR(fan_speed_set, S_IRUGO | S_IWUSR, show_cpld_sysfs_value, set_cpld_sysfs_value, 0x15); -static SENSOR_DEVICE_ATTR(fan0_led, S_IRUGO | S_IWUSR, show_cpld_sysfs_value, set_cpld_sysfs_value, 0x23); -static SENSOR_DEVICE_ATTR(fan1_led, S_IRUGO | S_IWUSR, show_cpld_sysfs_value, set_cpld_sysfs_value, 0x24); -static SENSOR_DEVICE_ATTR(fan2_led, S_IRUGO | S_IWUSR, show_cpld_sysfs_value, set_cpld_sysfs_value, 0x25); -static SENSOR_DEVICE_ATTR(fan3_led, S_IRUGO | S_IWUSR, show_cpld_sysfs_value, set_cpld_sysfs_value, 0x26); - -/* 0x37 */ -static SENSOR_DEVICE_ATTR(fan_present, S_IRUGO | S_IWUSR, show_cpld_sysfs_value, NULL, 0x30); -static SENSOR_DEVICE_ATTR(fan_status, S_IRUGO | S_IWUSR, show_cpld_sysfs_value, NULL, 0x31); -static SENSOR_DEVICE_ATTR(psu_status, S_IRUGO | S_IWUSR, show_cpld_sysfs_value, NULL, 0x51); -static SENSOR_DEVICE_ATTR(broad_back_lct, S_IRUGO | S_IWUSR, show_cpld_sysfs_value, set_cpld_sysfs_value, 0x2a); -static SENSOR_DEVICE_ATTR(broad_back_sys, S_IRUGO | S_IWUSR, show_cpld_sysfs_value, set_cpld_sysfs_value, 0xb2); - -/* 0x33 */ -static SENSOR_DEVICE_ATTR(mac_led, S_IRUGO | S_IWUSR, show_cpld_sysfs_value, set_cpld_sysfs_value, 0xa0); -static SENSOR_DEVICE_ATTR(broad_front_lct, S_IRUGO | S_IWUSR, show_cpld_sysfs_value, set_cpld_sysfs_value, 0x2a); -static SENSOR_DEVICE_ATTR(broad_front_bmc, S_IRUGO| S_IWUSR, show_cpld_sysfs_value, set_cpld_sysfs_value, 0xb1); -static SENSOR_DEVICE_ATTR(broad_front_cpu, S_IRUGO| S_IWUSR, show_cpld_sysfs_value, set_cpld_sysfs_value, 0xb2); -static SENSOR_DEVICE_ATTR(broad_front_pwr, S_IRUGO| S_IWUSR, show_cpld_sysfs_value, set_cpld_sysfs_value, 0xb3); -static SENSOR_DEVICE_ATTR(broad_front_fan, S_IRUGO| S_IWUSR, show_cpld_sysfs_value, set_cpld_sysfs_value, 0xb4); -static SENSOR_DEVICE_ATTR(sfp_led1_yellow, S_IRUGO| S_IWUSR, show_cpld_sysfs_value, set_cpld_sysfs_value, 0xad); -static SENSOR_DEVICE_ATTR(mac_temp_flag, S_IRUGO, show_cpld_sysfs_value, NULL, 0xd4); - -/* 0x34 */ -static SENSOR_DEVICE_ATTR(sfp_presence1, S_IRUGO| S_IWUSR, show_cpld_sysfs_value, NULL, 0x30); -static SENSOR_DEVICE_ATTR(sfp_presence2, S_IRUGO| S_IWUSR, show_cpld_sysfs_value, NULL, 0x31); -static SENSOR_DEVICE_ATTR(sfp_presence3, S_IRUGO| S_IWUSR, show_cpld_sysfs_value, NULL, 0x32); - -static SENSOR_DEVICE_ATTR(sfp_enable, S_IRUGO| S_IWUSR, show_cpld_sysfs_value, set_cpld_sysfs_value, 0xa1); -static SENSOR_DEVICE_ATTR(sfp_led1, S_IRUGO | S_IWUSR, show_cpld_sysfs_value, set_cpld_sysfs_value, 0xa2); -static SENSOR_DEVICE_ATTR(sfp_led2, S_IRUGO | S_IWUSR, show_cpld_sysfs_value, set_cpld_sysfs_value, 0xa3); -static SENSOR_DEVICE_ATTR(sfp_led3, S_IRUGO | S_IWUSR, show_cpld_sysfs_value, set_cpld_sysfs_value, 0xa4); -static SENSOR_DEVICE_ATTR(sfp_led_flash1, S_IRUGO | S_IWUSR, show_cpld_sysfs_value, set_cpld_sysfs_value, 0xa5); -static SENSOR_DEVICE_ATTR(sfp_led_flash2, S_IRUGO | S_IWUSR, show_cpld_sysfs_value, set_cpld_sysfs_value, 0xa6); -static SENSOR_DEVICE_ATTR(sfp_led_flash3, S_IRUGO | S_IWUSR, show_cpld_sysfs_value, set_cpld_sysfs_value, 0xa7); -static SENSOR_DEVICE_ATTR(sfp_txdis1, S_IRUGO| S_IWUSR, show_cpld_sysfs_value, set_cpld_sysfs_value, 0x60); -static SENSOR_DEVICE_ATTR(sfp_txdis2, S_IRUGO| S_IWUSR, show_cpld_sysfs_value, set_cpld_sysfs_value, 0x61); -static SENSOR_DEVICE_ATTR(sfp_txdis3, S_IRUGO| S_IWUSR, show_cpld_sysfs_value, set_cpld_sysfs_value, 0x62); - -static SENSOR_DEVICE_ATTR(port_speed1, S_IRUGO| S_IWUSR, show_cpld_sysfs_value, set_cpld_sysfs_value, 0xc0); -static SENSOR_DEVICE_ATTR(port_speed2, S_IRUGO| S_IWUSR, show_cpld_sysfs_value, set_cpld_sysfs_value, 0xc1); -static SENSOR_DEVICE_ATTR(port_speed3, S_IRUGO| S_IWUSR, show_cpld_sysfs_value, set_cpld_sysfs_value, 0xc2); -static SENSOR_DEVICE_ATTR(port_speed4, S_IRUGO| S_IWUSR, show_cpld_sysfs_value, set_cpld_sysfs_value, 0xc3); -static SENSOR_DEVICE_ATTR(port_speed5, S_IRUGO| S_IWUSR, show_cpld_sysfs_value, set_cpld_sysfs_value, 0xc4); -static SENSOR_DEVICE_ATTR(port_speed6, S_IRUGO| S_IWUSR, show_cpld_sysfs_value, set_cpld_sysfs_value, 0xc5); - -/* 0x35 */ -static SENSOR_DEVICE_ATTR(sfp_enable2, S_IRUGO | S_IWUSR ,show_cpld_sysfs_value, set_cpld_sysfs_value, 0xa0); -static SENSOR_DEVICE_ATTR(sfp_led2_yellow, S_IRUGO| S_IWUSR, show_cpld_sysfs_value, set_cpld_sysfs_value, 0xad); -static SENSOR_DEVICE_ATTR(mac_temp_input, S_IRUGO, show_mac_temp_value, NULL, 0xca); - -/* 0x36 */ -static SENSOR_DEVICE_ATTR(sfp_presence4, S_IRUGO | S_IWUSR ,show_cpld_sysfs_value, NULL, 0x30); -static SENSOR_DEVICE_ATTR(sfp_presence5, S_IRUGO | S_IWUSR ,show_cpld_sysfs_value, NULL, 0x31); -static SENSOR_DEVICE_ATTR(sfp_presence6, S_IRUGO | S_IWUSR ,show_cpld_sysfs_value, NULL, 0x32); -static SENSOR_DEVICE_ATTR(sfp_presence7, S_IRUGO | S_IWUSR ,show_cpld_sysfs_value, NULL, 0x33); -static SENSOR_DEVICE_ATTR(sfp_led4, S_IRUGO | S_IWUSR ,show_cpld_sysfs_value, set_cpld_sysfs_value, 0xa2); -static SENSOR_DEVICE_ATTR(sfp_led5, S_IRUGO | S_IWUSR ,show_cpld_sysfs_value, set_cpld_sysfs_value, 0xa3); -static SENSOR_DEVICE_ATTR(sfp_led6, S_IRUGO | S_IWUSR ,show_cpld_sysfs_value, set_cpld_sysfs_value, 0xa4); -static SENSOR_DEVICE_ATTR(sfp_led7, S_IRUGO | S_IWUSR ,show_cpld_sysfs_value, set_cpld_sysfs_value, 0xa5); -static SENSOR_DEVICE_ATTR(sfp_led_flash4, S_IRUGO | S_IWUSR ,show_cpld_sysfs_value, set_cpld_sysfs_value, 0xa6); -static SENSOR_DEVICE_ATTR(sfp_led_flash5, S_IRUGO | S_IWUSR ,show_cpld_sysfs_value, set_cpld_sysfs_value, 0xa7); -static SENSOR_DEVICE_ATTR(sfp_led_flash6, S_IRUGO | S_IWUSR ,show_cpld_sysfs_value, set_cpld_sysfs_value, 0xa8); -static SENSOR_DEVICE_ATTR(sfp_led_flash7, S_IRUGO | S_IWUSR ,show_cpld_sysfs_value, set_cpld_sysfs_value, 0xa9); - -static SENSOR_DEVICE_ATTR(sfp_txdis4, S_IRUGO | S_IWUSR ,show_cpld_sysfs_value, set_cpld_sysfs_value, 0x60); -static SENSOR_DEVICE_ATTR(sfp_txdis5, S_IRUGO | S_IWUSR ,show_cpld_sysfs_value, set_cpld_sysfs_value, 0x61); -static SENSOR_DEVICE_ATTR(sfp_txdis6, S_IRUGO | S_IWUSR ,show_cpld_sysfs_value, set_cpld_sysfs_value, 0x62); - -static SENSOR_DEVICE_ATTR(port_speed7, S_IRUGO| S_IWUSR, show_cpld_sysfs_value, set_cpld_sysfs_value, 0xc0); -static SENSOR_DEVICE_ATTR(port_speed8, S_IRUGO| S_IWUSR, show_cpld_sysfs_value, set_cpld_sysfs_value, 0xc1); -static SENSOR_DEVICE_ATTR(port_speed9, S_IRUGO| S_IWUSR, show_cpld_sysfs_value, set_cpld_sysfs_value, 0xc2); -static SENSOR_DEVICE_ATTR(port_speed10, S_IRUGO| S_IWUSR, show_cpld_sysfs_value, set_cpld_sysfs_value, 0xc3); -static SENSOR_DEVICE_ATTR(port_speed11, S_IRUGO| S_IWUSR, show_cpld_sysfs_value, set_cpld_sysfs_value, 0xc4); -static SENSOR_DEVICE_ATTR(port_speed12, S_IRUGO| S_IWUSR, show_cpld_sysfs_value, set_cpld_sysfs_value, 0xc5); -static SENSOR_DEVICE_ATTR(port_speed13, S_IRUGO| S_IWUSR, show_cpld_sysfs_value, set_cpld_sysfs_value, 0xc6); -static SENSOR_DEVICE_ATTR(port_speed14, S_IRUGO| S_IWUSR, show_cpld_sysfs_value, set_cpld_sysfs_value, 0xc7); - -static struct attribute *cpld32_sysfs_attrs[] = { - &sensor_dev_attr_fan_speed_set.dev_attr.attr, - &sensor_dev_attr_fan0_led.dev_attr.attr, - &sensor_dev_attr_fan1_led.dev_attr.attr, - &sensor_dev_attr_fan2_led.dev_attr.attr, - &sensor_dev_attr_fan3_led.dev_attr.attr, - NULL -}; - -static struct attribute *cpld37_sysfs_attrs[] = { - &sensor_dev_attr_fan_present.dev_attr.attr, - &sensor_dev_attr_fan_status.dev_attr.attr, - &sensor_dev_attr_psu_status.dev_attr.attr, - &sensor_dev_attr_broad_back_lct.dev_attr.attr, - &sensor_dev_attr_broad_back_sys.dev_attr.attr, - &sensor_dev_attr_cpld_version.dev_attr.attr, - NULL -}; - -static struct attribute *cpld33_sysfs_attrs[] = { - &sensor_dev_attr_mac_led.dev_attr.attr, - &sensor_dev_attr_broad_front_lct.dev_attr.attr, - &sensor_dev_attr_broad_front_bmc.dev_attr.attr, - &sensor_dev_attr_broad_front_cpu.dev_attr.attr, - &sensor_dev_attr_broad_front_pwr.dev_attr.attr, - &sensor_dev_attr_broad_front_fan.dev_attr.attr, - &sensor_dev_attr_sfp_led1_yellow.dev_attr.attr, - &sensor_dev_attr_mac_temp_flag.dev_attr.attr, - &sensor_dev_attr_cpld_version.dev_attr.attr, - NULL -}; - -static struct attribute *cpld34_sysfs_attrs[] = { - &sensor_dev_attr_sfp_presence1.dev_attr.attr, - &sensor_dev_attr_sfp_presence2.dev_attr.attr, - &sensor_dev_attr_sfp_presence3.dev_attr.attr, - &sensor_dev_attr_sfp_enable.dev_attr.attr, - &sensor_dev_attr_sfp_led1.dev_attr.attr, - &sensor_dev_attr_sfp_led2.dev_attr.attr, - &sensor_dev_attr_sfp_led3.dev_attr.attr, - &sensor_dev_attr_sfp_led_flash1.dev_attr.attr, - &sensor_dev_attr_sfp_led_flash2.dev_attr.attr, - &sensor_dev_attr_sfp_led_flash3.dev_attr.attr, - &sensor_dev_attr_sfp_txdis1.dev_attr.attr, - &sensor_dev_attr_sfp_txdis2.dev_attr.attr, - &sensor_dev_attr_sfp_txdis3.dev_attr.attr, - &sensor_dev_attr_port_speed1.dev_attr.attr, - &sensor_dev_attr_port_speed2.dev_attr.attr, - &sensor_dev_attr_port_speed3.dev_attr.attr, - &sensor_dev_attr_port_speed4.dev_attr.attr, - &sensor_dev_attr_port_speed5.dev_attr.attr, - &sensor_dev_attr_port_speed6.dev_attr.attr, - NULL -}; - -static struct attribute *cpld36_sysfs_attrs[] = { - &sensor_dev_attr_sfp_presence4.dev_attr.attr, - &sensor_dev_attr_sfp_presence5.dev_attr.attr, - &sensor_dev_attr_sfp_presence6.dev_attr.attr, - &sensor_dev_attr_sfp_presence7.dev_attr.attr, - &sensor_dev_attr_sfp_led4.dev_attr.attr, - &sensor_dev_attr_sfp_led5.dev_attr.attr, - &sensor_dev_attr_sfp_led6.dev_attr.attr, - &sensor_dev_attr_sfp_led7.dev_attr.attr, - &sensor_dev_attr_sfp_led_flash4.dev_attr.attr, - &sensor_dev_attr_sfp_led_flash5.dev_attr.attr, - &sensor_dev_attr_sfp_led_flash6.dev_attr.attr, - &sensor_dev_attr_sfp_led_flash7.dev_attr.attr, - &sensor_dev_attr_sfp_txdis4.dev_attr.attr, - &sensor_dev_attr_sfp_txdis5.dev_attr.attr, - &sensor_dev_attr_sfp_txdis6.dev_attr.attr, - &sensor_dev_attr_port_speed7.dev_attr.attr, - &sensor_dev_attr_port_speed8.dev_attr.attr, - &sensor_dev_attr_port_speed9.dev_attr.attr, - &sensor_dev_attr_port_speed10.dev_attr.attr, - &sensor_dev_attr_port_speed11.dev_attr.attr, - &sensor_dev_attr_port_speed12.dev_attr.attr, - &sensor_dev_attr_port_speed13.dev_attr.attr, - &sensor_dev_attr_port_speed14.dev_attr.attr, - NULL -}; - -static struct attribute *cpld35_sysfs_attrs[] = { - &sensor_dev_attr_sfp_enable2.dev_attr.attr, - &sensor_dev_attr_broad_front_lct.dev_attr.attr, - &sensor_dev_attr_broad_front_bmc.dev_attr.attr, - &sensor_dev_attr_broad_front_cpu.dev_attr.attr, - &sensor_dev_attr_broad_front_pwr.dev_attr.attr, - &sensor_dev_attr_broad_front_fan.dev_attr.attr, - &sensor_dev_attr_sfp_led2_yellow.dev_attr.attr, - &sensor_dev_attr_mac_temp_input.dev_attr.attr, - &sensor_dev_attr_cpld_version.dev_attr.attr, - NULL -}; - -static const struct attribute_group cpld32_sysfs_group = { - .attrs = cpld32_sysfs_attrs, -}; - -static const struct attribute_group cpld37_sysfs_group = { - .attrs = cpld37_sysfs_attrs, -}; - -static const struct attribute_group cpld33_sysfs_group = { - .attrs = cpld33_sysfs_attrs, -}; - -static const struct attribute_group cpld34_sysfs_group = { - .attrs = cpld34_sysfs_attrs, -}; - -static const struct attribute_group cpld36_sysfs_group = { - .attrs = cpld36_sysfs_attrs, -}; - -static const struct attribute_group cpld35_sysfs_group = { - .attrs = cpld35_sysfs_attrs, -}; - -static struct attribute *cpld_hwmon_attrs[] = { - &sensor_dev_attr_fan1_input.dev_attr.attr, - &sensor_dev_attr_fan2_input.dev_attr.attr, - &sensor_dev_attr_fan3_input.dev_attr.attr, - &sensor_dev_attr_fan4_input.dev_attr.attr, - NULL -}; -ATTRIBUTE_GROUPS(cpld_hwmon); - -struct cpld_attr_match_group { - int bus_nr; /* I2C BUS */ - unsigned short addr; /* slave addr*/ - const struct attribute_group *attr_group_ptr; - const struct attribute_group *attr_hwmon_ptr; -}; - -static struct cpld_attr_match_group g_cpld_attr_match[] = { - {0, 0x32, &cpld32_sysfs_group, NULL}, - {2, 0x37, &cpld37_sysfs_group, (struct attribute_group *)cpld_hwmon_groups}, - {2, 0x33, &cpld33_sysfs_group, NULL}, - {1, 0x34, &cpld34_sysfs_group, NULL}, - {1, 0x36, &cpld36_sysfs_group, NULL}, - {2, 0x35, &cpld35_sysfs_group, NULL}, -}; - -static const struct attribute_group *cpld_get_attr_group(struct i2c_client *client, int is_hwmon) -{ - int i; - struct cpld_attr_match_group *group; - - for (i = 0; i < ARRAY_SIZE(g_cpld_attr_match); i++) { - group = &g_cpld_attr_match[i]; - DBG_DEBUG("is_hwmon %d i %d client(nr:%d,addr:0x%x), group(nr:%d,addr:0x0%x).\n", is_hwmon, - i, client->adapter->nr, client->addr, group->bus_nr, group->addr); - if ((client->addr == group->addr) && (client->adapter->nr == group->bus_nr)) { - DBG_DEBUG("is_hwmon %d i %d nr %d addr %d .\n", is_hwmon, i, client->adapter->nr, client->addr); - return (is_hwmon) ? (group->attr_hwmon_ptr) : (group->attr_group_ptr); - } - } - - DBG_DEBUG("is_hwmon %d nr %d addr %d dismatch, return NULL.\n", is_hwmon, client->adapter->nr, client->addr); - return NULL; -} - -static int cpld_probe(struct i2c_client *client, const struct i2c_device_id *id) -{ - struct cpld_data *data; - int status; - const struct attribute_group *sysfs_group, *hwmon_group; - - status = -1; - DBG_DEBUG("=========cpld_probe(addr:0x%x, nr:%d)===========\n", client->addr, client->adapter->nr); - data = devm_kzalloc(&client->dev, sizeof(struct cpld_data), GFP_KERNEL); - if (!data) { - return -ENOMEM; - } - - data->client = client; - i2c_set_clientdata(client, data); - mutex_init(&data->update_lock); - - sysfs_group = NULL; - sysfs_group = cpld_get_attr_group(client, 0); - if (sysfs_group) { - status = sysfs_create_group(&client->dev.kobj, sysfs_group); - DBG_DEBUG("=========(addr:0x%x, nr:%d) sysfs_create_group status %d===========\n", client->addr, client->adapter->nr, status); - if (status != 0) { - DBG_ERROR("sysfs_create_group status %d.\n", status); - goto error; - } - } else { - DBG_DEBUG("=========(addr:0x%x, nr:%d) no sysfs_create_group \n", client->addr, client->adapter->nr); - } - - hwmon_group = NULL; - hwmon_group = cpld_get_attr_group(client, 1); - if (hwmon_group) { - data->hwmon_dev = hwmon_device_register_with_groups(&client->dev, client->name, data, (const struct attribute_group **)hwmon_group); - if (IS_ERR(data->hwmon_dev)) { - sysfs_remove_group(&client->dev.kobj, (const struct attribute_group *)sysfs_group); - DBG_ERROR("hwmon_device_register_with_groups failed ret %ld.\n", PTR_ERR(data->hwmon_dev)); - return PTR_ERR(data->hwmon_dev); - } - DBG_DEBUG("=========(addr:0x%x, nr:%d) hwmon_device_register_with_groups success===========\n", client->addr, client->adapter->nr); - if (status != 0) { - DBG_ERROR("sysfs_create_group status %d.\n", status); - goto error; - } - } else { - DBG_DEBUG("=========(addr:0x%x, nr:%d) no hwmon_device_register_with_groups \n", client->addr, client->adapter->nr); - } - -error: - return status; - -} - -static int cpld_remove(struct i2c_client *client) -{ - struct cpld_data *data = i2c_get_clientdata(client); - const struct attribute_group *sysfs_group, *hwmon_group; - - DBG_DEBUG("=========cpld_remove(addr:0x%x, nr:%d)===========\n", client->addr, client->adapter->nr); - - sysfs_group = NULL; - sysfs_group = cpld_get_attr_group(client, 0); - if (sysfs_group) { - DBG_DEBUG("=========(addr:0x%x, nr:%d) do sysfs_remove_group \n", client->addr, client->adapter->nr); - sysfs_remove_group(&client->dev.kobj, (const struct attribute_group *)sysfs_group); - } else { - DBG_DEBUG("=========(addr:0x%x, nr:%d) no sysfs_remove_group \n", client->addr, client->adapter->nr); - } - - hwmon_group = NULL; - hwmon_group = cpld_get_attr_group(client, 1); - if (hwmon_group) { - DBG_DEBUG("=========(addr:0x%x, nr:%d) do hwmon_device_unregister \n", client->addr, client->adapter->nr); - hwmon_device_unregister(data->hwmon_dev); - } else { - DBG_DEBUG("=========(addr:0x%x, nr:%d) no hwmon_device_unregister \n", client->addr, client->adapter->nr); - } - - return 0; -} - - -static const struct i2c_device_id cpld_id[] = { - { "rg_cpld", 0 }, - {} -}; - -MODULE_DEVICE_TABLE(i2c, cpld_id); - -static struct i2c_driver rg_cpld_driver = { - .class = I2C_CLASS_HWMON, - .driver = { - .name = "rg_cpld", - }, - .probe = cpld_probe, - .remove = cpld_remove, - .id_table = cpld_id, -}; - -module_i2c_driver(rg_cpld_driver); - -MODULE_AUTHOR("support "); -MODULE_DESCRIPTION("ragile CPLD driver"); -MODULE_LICENSE("GPL"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/modules/driver/wb_firmware_upgrade_device.c b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/modules/driver/wb_firmware_upgrade_device.c new file mode 100644 index 000000000000..5fcaa8da1963 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/modules/driver/wb_firmware_upgrade_device.c @@ -0,0 +1,178 @@ +/* + * wb_firmware_upgrade.c + * Original Author: support 2021-03-17 + * + * ko for firmware device + * History + * [Version] [Author] [Date] [Description] + * v1.0 support 2021-05-07 Initial version + */ +#include +#include +#include +#include +#include +#include + +static int g_wb_firmware_upgrade_debug = 0; +static int g_wb_firmware_upgrade_error = 0; + +module_param(g_wb_firmware_upgrade_debug, int, S_IRUGO | S_IWUSR); +module_param(g_wb_firmware_upgrade_error, int, S_IRUGO | S_IWUSR); + +#define WB_FIRMWARE_UPGRADE_DEBUG_VERBOSE(fmt, args...) do { \ + if (g_wb_firmware_upgrade_debug) { \ + printk(KERN_INFO "[WB_FIRMWARE_UPGRADE][VER][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +#define WB_FIRMWARE_UPGRADE_DEBUG_ERROR(fmt, args...) do { \ + if (g_wb_firmware_upgrade_error) { \ + printk(KERN_ERR "[WB_FIRMWARE_UPGRADE][ERR][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +/* cpld */ +static firmware_upgrade_device_t firmware_upgrade_device_data0 = { + .type = "JTAG", + .upg_type.jtag = { + .tdi = 67, + .tck = 65, + .tms = 6, + .tdo = 32, + }, + .en_gpio[0] = 50, + .en_level[0] = 1, + .en_gpio[1] = 48, + .en_level[1] = 1, + .chain = 1, + .chip_index = 1, + + .en_gpio_num = 2, + .en_logic_num = 0, +}; + +/* fpga */ +static firmware_upgrade_device_t firmware_upgrade_device_data1 = { + .type = "SPI_LOGIC", + .chain = 3, + .chip_index = 1, + .upg_type.sysfs = { + .dev_name = "/dev/fpga0", + .ctrl_base = 0xa00, + .flash_base = 0x1A0000, + .test_base = 0x7F0000, + .test_size = 0x10000, + }, + .en_gpio_num = 0, + .en_logic_num = 0, +}; + +static firmware_upgrade_device_t firmware_upgrade_device_data2 = { + .type = "SPI_LOGIC", + .chain = 4, + .chip_index = 1, + .upg_type.sysfs = { + .dev_name = "/dev/fpga0", + .ctrl_base = 0xa00, + .flash_base = 0x0, + .test_base = 0x7F0000, + .test_size = 0x10000, + }, + .en_gpio_num = 0, + .en_logic_num = 0, +}; + +/* bios */ +static firmware_upgrade_device_t firmware_upgrade_device_data3 = { + .type = "MTD_DEV", + .chain = 2, + .chip_index = 1, + .upg_type.sysfs = { + .mtd_name = "BIOS", + .flash_base = 0x800000, + }, + + .en_gpio_num = 0, + .en_logic_num = 0, +}; + +static void firmware_device_release(struct device *dev) +{ + return; +} + +static struct platform_device firmware_upgrade_device[] = { + { + .name = "firmware_cpld_ispvme", + .id = 1, + .dev = { + .platform_data = &firmware_upgrade_device_data0, + .release = firmware_device_release, + }, + }, + { + .name = "firmware_sysfs", + .id = 2, + .dev = { + .platform_data = &firmware_upgrade_device_data1, + .release = firmware_device_release, + }, + }, + { + .name = "firmware_sysfs", + .id = 3, + .dev = { + .platform_data = &firmware_upgrade_device_data2, + .release = firmware_device_release, + }, + }, + { + .name = "firmware_sysfs", + .id = 4, + .dev = { + .platform_data = &firmware_upgrade_device_data3, + .release = firmware_device_release, + }, + }, + }; + + static int __init firmware_upgrade_device_init(void) + { + int i; + int ret = 0; + firmware_upgrade_device_t *firmware_upgrade_device_data; + + WB_FIRMWARE_UPGRADE_DEBUG_VERBOSE("enter!\n"); + for (i = 0; i < ARRAY_SIZE(firmware_upgrade_device); i++) { + firmware_upgrade_device_data = firmware_upgrade_device[i].dev.platform_data; + ret = platform_device_register(&firmware_upgrade_device[i]); + if (ret < 0) { + firmware_upgrade_device_data->device_flag = -1; /* device register failed, set flag -1 */ + printk(KERN_ERR "firmware_upgrade_device id%d register failed!\n", i + 1); + } else { + firmware_upgrade_device_data->device_flag = 0; /* device register suucess, set flag 0 */ + } + } + return 0; + } + + static void __exit firmware_upgrade_device_exit(void) + { + int i; + firmware_upgrade_device_t *firmware_upgrade_device_data; + + WB_FIRMWARE_UPGRADE_DEBUG_VERBOSE("enter!\n"); + for (i = ARRAY_SIZE(firmware_upgrade_device) - 1; i >= 0; i--) { + firmware_upgrade_device_data = firmware_upgrade_device[i].dev.platform_data; + if (firmware_upgrade_device_data->device_flag == 0) { /* device register success, need unregister */ + platform_device_unregister(&firmware_upgrade_device[i]); + } + } + } + + module_init(firmware_upgrade_device_init); + module_exit(firmware_upgrade_device_exit); + MODULE_DESCRIPTION("FIRMWARE UPGRADE Devices"); + MODULE_LICENSE("GPL"); + MODULE_AUTHOR("support"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/modules/driver/wb_i2c_dev_device.c b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/modules/driver/wb_i2c_dev_device.c new file mode 100644 index 000000000000..865e7afea44c --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/modules/driver/wb_i2c_dev_device.c @@ -0,0 +1,140 @@ +#include +#include +#include +#include +#include +#include + +#include + +static int g_wb_i2c_dev_device_debug = 0; +static int g_wb_i2c_dev_device_error = 0; + +module_param(g_wb_i2c_dev_device_debug, int, S_IRUGO | S_IWUSR); +module_param(g_wb_i2c_dev_device_error, int, S_IRUGO | S_IWUSR); + +#define WB_I2C_DEV_DEVICE_DEBUG_VERBOSE(fmt, args...) do { \ + if (g_wb_i2c_dev_device_debug) { \ + printk(KERN_INFO "[WB_I2C_DEV_DEVICE][VER][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +#define WB_I2C_DEV_DEVICE_DEBUG_ERROR(fmt, args...) do { \ + if (g_wb_i2c_dev_device_error) { \ + printk(KERN_ERR "[WB_I2C_DEV_DEVICE][ERR][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +static i2c_dev_device_t i2c_dev_device_data0 = { + .i2c_bus = 2, + .i2c_addr = 0x0d, + .i2c_name = "cpld2", + .data_bus_width = 1, + .addr_bus_width = 1, + .per_rd_len = 256, + .per_wr_len = 256, + .i2c_len = 256, +}; + +static i2c_dev_device_t i2c_dev_device_data1 = { + .i2c_bus = 8, + .i2c_addr = 0x30, + .i2c_name = "cpld3", + .data_bus_width = 1, + .addr_bus_width = 1, + .per_rd_len = 256, + .per_wr_len = 256, + .i2c_len = 256, +}; + +static i2c_dev_device_t i2c_dev_device_data2 = { + .i2c_bus = 8, + .i2c_addr = 0x31, + .i2c_name = "cpld4", + .data_bus_width = 1, + .addr_bus_width = 1, + .per_rd_len = 256, + .per_wr_len = 256, + .i2c_len = 256, +}; + +static i2c_dev_device_t i2c_dev_device_data3 = { + .i2c_bus = 6, + .i2c_addr = 0x0d, + .i2c_name = "cpld5", + .data_bus_width = 1, + .addr_bus_width = 1, + .per_rd_len = 256, + .per_wr_len = 256, + .i2c_len = 256, +}; + +struct i2c_board_info i2c_dev_device_info[] = { + { + .type = "wb-i2c-dev", + .platform_data = &i2c_dev_device_data0, + }, + { + .type = "wb-i2c-dev", + .platform_data = &i2c_dev_device_data1, + }, + { + .type = "wb-i2c-dev", + .platform_data = &i2c_dev_device_data2, + }, + { + .type = "wb-i2c-dev", + .platform_data = &i2c_dev_device_data3, + }, +}; + +static int __init wb_i2c_dev_device_init(void) +{ + int i; + struct i2c_adapter *adap; + struct i2c_client *client; + i2c_dev_device_t *i2c_dev_device_data; + + WB_I2C_DEV_DEVICE_DEBUG_VERBOSE("enter!\n"); + for (i = 0; i < ARRAY_SIZE(i2c_dev_device_info); i++) { + i2c_dev_device_data = i2c_dev_device_info[i].platform_data; + i2c_dev_device_info[i].addr = i2c_dev_device_data->i2c_addr; + adap = i2c_get_adapter(i2c_dev_device_data->i2c_bus); + if (adap == NULL) { + i2c_dev_device_data->client = NULL; + printk(KERN_ERR "get i2c bus %d adapter fail.\n", i2c_dev_device_data->i2c_bus); + continue; + } + client = i2c_new_client_device(adap, &i2c_dev_device_info[i]); + if (!client) { + i2c_dev_device_data->client = NULL; + printk(KERN_ERR "Failed to register i2c dev device %d at bus %d!\n", + i2c_dev_device_data->i2c_addr, i2c_dev_device_data->i2c_bus); + } else { + i2c_dev_device_data->client = client; + } + i2c_put_adapter(adap); + } + return 0; +} + +static void __exit wb_i2c_dev_device_exit(void) +{ + int i; + i2c_dev_device_t *i2c_dev_device_data; + + WB_I2C_DEV_DEVICE_DEBUG_VERBOSE("enter!\n"); + for (i = ARRAY_SIZE(i2c_dev_device_info) - 1; i >= 0; i--) { + i2c_dev_device_data = i2c_dev_device_info[i].platform_data; + if (i2c_dev_device_data->client) { + i2c_unregister_device(i2c_dev_device_data->client); + i2c_dev_device_data->client = NULL; + } + } +} + +module_init(wb_i2c_dev_device_init); +module_exit(wb_i2c_dev_device_exit); +MODULE_DESCRIPTION("I2C DEV Devices"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("support"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/modules/driver/wb_i2c_mux_pca954x_device.c b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/modules/driver/wb_i2c_mux_pca954x_device.c new file mode 100644 index 000000000000..f12a71013451 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/modules/driver/wb_i2c_mux_pca954x_device.c @@ -0,0 +1,296 @@ +#include +#include +#include +#include +#include +#include + +#include + +static int g_wb_i2c_mux_pca954x_device_debug = 0; +static int g_wb_i2c_mux_pca954x_device_error = 0; + +module_param(g_wb_i2c_mux_pca954x_device_debug, int, S_IRUGO | S_IWUSR); +module_param(g_wb_i2c_mux_pca954x_device_error, int, S_IRUGO | S_IWUSR); + +#define WB_I2C_MUX_PCA954X_DEVICE_DEBUG_VERBOSE(fmt, args...) do { \ + if (g_wb_i2c_mux_pca954x_device_debug) { \ + printk(KERN_INFO "[WB_I2C_MUX_PCA954X_DEVICE][VER][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +#define WB_I2C_MUX_PCA954X_DEVICE_DEBUG_ERROR(fmt, args...) do { \ + if (g_wb_i2c_mux_pca954x_device_error) { \ + printk(KERN_ERR "[WB_I2C_MUX_PCA954X_DEVICE][ERR][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +static i2c_mux_pca954x_device_t i2c_mux_pca954x_device_data0 = { + .i2c_bus = 2, + .i2c_addr = 0x77, + .probe_disable = 1, + .select_chan_check = 0, + .close_chan_force_reset = 0, + .pca9548_base_nr = 16, + .pca9548_reset_type = PCA9548_RESET_FILE, + .rst_delay_b = 0, + .rst_delay = 1000, + .rst_delay_a = 1000, + .attr = { + .file_attr.dev_name = "/dev/cpld5", + .file_attr.offset = 0x60, + .file_attr.mask = 0x02, + .file_attr.reset_on = 0x00, + .file_attr.reset_off = 0x02, + }, +}; + +static i2c_mux_pca954x_device_t i2c_mux_pca954x_device_data1 = { + .i2c_bus = 4, + .i2c_addr = 0x77, + .probe_disable = 1, + .select_chan_check = 0, + .close_chan_force_reset = 0, + .pca9548_base_nr = 24, + .pca9548_reset_type = PCA9548_RESET_FILE, + .rst_delay_b = 0, + .rst_delay = 1000, + .rst_delay_a = 1000, + .attr = { + .file_attr.dev_name = "/dev/cpld5", + .file_attr.offset = 0x60, + .file_attr.mask = 0x01, + .file_attr.reset_on = 0x00, + .file_attr.reset_off = 0x01, + }, +}; + +static i2c_mux_pca954x_device_t i2c_mux_pca954x_device_data2 = { + .i2c_bus = 12, + .i2c_addr = 0x70, + .probe_disable = 1, + .select_chan_check = 0, + .close_chan_force_reset = 0, + .pca9548_base_nr = 32, + .pca9548_reset_type = PCA9548_RESET_FILE, + .rst_delay_b = 0, + .rst_delay = 1000, + .rst_delay_a = 1000, + .attr = { + .file_attr.dev_name = "/dev/fpga0", + .file_attr.offset = 0x20, + .file_attr.mask = 0x01, + .file_attr.reset_on = 0x00, + .file_attr.reset_off = 0x01, + }, +}; + +static i2c_mux_pca954x_device_t i2c_mux_pca954x_device_data3 = { + .i2c_bus = 12, + .i2c_addr = 0x71, + .probe_disable = 1, + .select_chan_check = 0, + .close_chan_force_reset = 0, + .pca9548_base_nr = 40, + .pca9548_reset_type = PCA9548_RESET_FILE, + .rst_delay_b = 0, + .rst_delay = 1000, + .rst_delay_a = 1000, + .attr = { + .file_attr.dev_name = "/dev/fpga0", + .file_attr.offset = 0x20, + .file_attr.mask = 0x01, + .file_attr.reset_on = 0x00, + .file_attr.reset_off = 0x01, + }, +}; + +static i2c_mux_pca954x_device_t i2c_mux_pca954x_device_data4 = { + .i2c_bus = 12, + .i2c_addr = 0x72, + .probe_disable = 1, + .select_chan_check = 0, + .close_chan_force_reset = 0, + .pca9548_base_nr = 48, + .pca9548_reset_type = PCA9548_RESET_FILE, + .rst_delay_b = 0, + .rst_delay = 1000, + .rst_delay_a = 1000, + .attr = { + .file_attr.dev_name = "/dev/fpga0", + .file_attr.offset = 0x20, + .file_attr.mask = 0x01, + .file_attr.reset_on = 0x00, + .file_attr.reset_off = 0x01, + }, +}; + +static i2c_mux_pca954x_device_t i2c_mux_pca954x_device_data5 = { + .i2c_bus = 12, + .i2c_addr = 0x73, + .probe_disable = 1, + .select_chan_check = 0, + .close_chan_force_reset = 0, + .pca9548_base_nr = 56, + .pca9548_reset_type = PCA9548_RESET_FILE, + .rst_delay_b = 0, + .rst_delay = 1000, + .rst_delay_a = 1000, + .attr = { + .file_attr.dev_name = "/dev/fpga0", + .file_attr.offset = 0x20, + .file_attr.mask = 0x01, + .file_attr.reset_on = 0x00, + .file_attr.reset_off = 0x01, + }, +}; + +static i2c_mux_pca954x_device_t i2c_mux_pca954x_device_data6 = { + .i2c_bus = 13, + .i2c_addr = 0x70, + .probe_disable = 1, + .select_chan_check = 0, + .close_chan_force_reset = 0, + .pca9548_base_nr = 64, + .pca9548_reset_type = PCA9548_RESET_FILE, + .rst_delay_b = 0, + .rst_delay = 1000, + .rst_delay_a = 1000, + .attr = { + .file_attr.dev_name = "/dev/fpga0", + .file_attr.offset = 0x20, + .file_attr.mask = 0x01, + .file_attr.reset_on = 0x00, + .file_attr.reset_off = 0x01, + }, +}; + +static i2c_mux_pca954x_device_t i2c_mux_pca954x_device_data7 = { + .i2c_bus = 13, + .i2c_addr = 0x71, + .probe_disable = 1, + .select_chan_check = 0, + .close_chan_force_reset = 0, + .pca9548_base_nr = 72, + .pca9548_reset_type = PCA9548_RESET_FILE, + .rst_delay_b = 0, + .rst_delay = 1000, + .rst_delay_a = 1000, + .attr = { + .file_attr.dev_name = "/dev/fpga0", + .file_attr.offset = 0x20, + .file_attr.mask = 0x01, + .file_attr.reset_on = 0x00, + .file_attr.reset_off = 0x01, + }, +}; + +static i2c_mux_pca954x_device_t i2c_mux_pca954x_device_data8 = { + .i2c_bus = 13, + .i2c_addr = 0x72, + .probe_disable = 1, + .select_chan_check = 0, + .close_chan_force_reset = 0, + .pca9548_base_nr = 80, + .pca9548_reset_type = PCA9548_RESET_FILE, + .rst_delay_b = 0, + .rst_delay = 1000, + .rst_delay_a = 1000, + .attr = { + .file_attr.dev_name = "/dev/fpga0", + .file_attr.offset = 0x20, + .file_attr.mask = 0x01, + .file_attr.reset_on = 0x00, + .file_attr.reset_off = 0x01, + }, +}; + +struct i2c_board_info i2c_mux_pca954x_device_info[] = { + { + .type = "wb_pca9548", + .platform_data = &i2c_mux_pca954x_device_data0, + }, + { + .type = "wb_pca9548", + .platform_data = &i2c_mux_pca954x_device_data1, + }, + { + .type = "wb_pca9548", + .platform_data = &i2c_mux_pca954x_device_data2, + }, + { + .type = "wb_pca9548", + .platform_data = &i2c_mux_pca954x_device_data3, + }, + { + .type = "wb_pca9548", + .platform_data = &i2c_mux_pca954x_device_data4, + }, + { + .type = "wb_pca9548", + .platform_data = &i2c_mux_pca954x_device_data5, + }, + { + .type = "wb_pca9548", + .platform_data = &i2c_mux_pca954x_device_data6, + }, + { + .type = "wb_pca9548", + .platform_data = &i2c_mux_pca954x_device_data7, + }, + { + .type = "wb_pca9548", + .platform_data = &i2c_mux_pca954x_device_data8, + }, +}; + +static int __init wb_i2c_mux_pca954x_device_init(void) +{ + int i; + struct i2c_adapter *adap; + struct i2c_client *client; + i2c_mux_pca954x_device_t *i2c_mux_pca954x_device_data; + + WB_I2C_MUX_PCA954X_DEVICE_DEBUG_VERBOSE("enter!\n"); + for (i = 0; i < ARRAY_SIZE(i2c_mux_pca954x_device_info); i++) { + i2c_mux_pca954x_device_data = i2c_mux_pca954x_device_info[i].platform_data; + i2c_mux_pca954x_device_info[i].addr = i2c_mux_pca954x_device_data->i2c_addr; + adap = i2c_get_adapter(i2c_mux_pca954x_device_data->i2c_bus); + if (adap == NULL) { + i2c_mux_pca954x_device_data->client = NULL; + printk(KERN_ERR "get i2c bus %d adapter fail.\n", i2c_mux_pca954x_device_data->i2c_bus); + continue; + } + client = i2c_new_client_device(adap, &i2c_mux_pca954x_device_info[i]); + if (!client) { + i2c_mux_pca954x_device_data->client = NULL; + printk(KERN_ERR "Failed to register pca954x device %d at bus %d!\n", + i2c_mux_pca954x_device_data->i2c_addr, i2c_mux_pca954x_device_data->i2c_bus); + } else { + i2c_mux_pca954x_device_data->client = client; + } + i2c_put_adapter(adap); + } + return 0; +} + +static void __exit wb_i2c_mux_pca954x_device_exit(void) +{ + int i; + i2c_mux_pca954x_device_t *i2c_mux_pca954x_device_data; + + WB_I2C_MUX_PCA954X_DEVICE_DEBUG_VERBOSE("enter!\n"); + for (i = ARRAY_SIZE(i2c_mux_pca954x_device_info) - 1; i >= 0; i--) { + i2c_mux_pca954x_device_data = i2c_mux_pca954x_device_info[i].platform_data; + if (i2c_mux_pca954x_device_data->client) { + i2c_unregister_device(i2c_mux_pca954x_device_data->client); + i2c_mux_pca954x_device_data->client = NULL; + } + } +} + +module_init(wb_i2c_mux_pca954x_device_init); +module_exit(wb_i2c_mux_pca954x_device_exit); +MODULE_DESCRIPTION("I2C MUX PCA954X Devices"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("support"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/modules/driver/wb_i2c_ocores_device.c b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/modules/driver/wb_i2c_ocores_device.c new file mode 100644 index 000000000000..ff7ba9d26fbc --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/modules/driver/wb_i2c_ocores_device.c @@ -0,0 +1,423 @@ +#include +#include +#include +#include +#include + +#include + +static int g_wb_i2c_ocores_device_debug = 0; +static int g_wb_i2c_ocores_device_error = 0; + +module_param(g_wb_i2c_ocores_device_debug, int, S_IRUGO | S_IWUSR); +module_param(g_wb_i2c_ocores_device_error, int, S_IRUGO | S_IWUSR); + +#define WB_I2C_OCORE_DEVICE_DEBUG_VERBOSE(fmt, args...) do { \ + if (g_wb_i2c_ocores_device_debug) { \ + printk(KERN_INFO "[WB_I2C_OCORE_DEVICE][VER][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +#define WB_I2C_OCORE_DEVICE_DEBUG_ERROR(fmt, args...) do { \ + if (g_wb_i2c_ocores_device_error) { \ + printk(KERN_ERR "[WB_I2C_OCORE_DEVICE][ERR][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +static i2c_ocores_device_t i2c_ocores_device_data0 = { + .adap_nr = 2, + .big_endian = 0, + .dev_name = "/dev/fpga0", + .reg_access_mode = 3, + .dev_base = 0x0800, + .reg_shift = 2, + .reg_io_width = 4, + .ip_clock_khz = 125000, + .bus_clock_khz = 100, + .irq_offset = 0, + .pci_domain = 0, + .pci_bus = 8, + .pci_slot = 0, + .pci_fn = 0, +}; + +static i2c_ocores_device_t i2c_ocores_device_data1 = { + .adap_nr = 3, + .big_endian = 0, + .dev_name = "/dev/fpga0", + .reg_access_mode = 3, + .dev_base = 0x0820, + .reg_shift = 2, + .reg_io_width = 4, + .ip_clock_khz = 125000, + .bus_clock_khz = 100, + .irq_offset = 1, + .pci_domain = 0, + .pci_bus = 8, + .pci_slot = 0, + .pci_fn = 0, +}; + +static i2c_ocores_device_t i2c_ocores_device_data2 = { + .adap_nr = 4, + .big_endian = 0, + .dev_name = "/dev/fpga0", + .reg_access_mode = 3, + .dev_base = 0x0840, + .reg_shift = 2, + .reg_io_width = 4, + .ip_clock_khz = 125000, + .bus_clock_khz = 100, + .irq_offset = 2, + .pci_domain = 0, + .pci_bus = 8, + .pci_slot = 0, + .pci_fn = 0, +}; + +static i2c_ocores_device_t i2c_ocores_device_data3 = { + .adap_nr = 5, + .big_endian = 0, + .dev_name = "/dev/fpga0", + .reg_access_mode = 3, + .dev_base = 0x0860, + .reg_shift = 2, + .reg_io_width = 4, + .ip_clock_khz = 125000, + .bus_clock_khz = 100, + .irq_offset = 3, + .pci_domain = 0, + .pci_bus = 8, + .pci_slot = 0, + .pci_fn = 0, +}; + +static i2c_ocores_device_t i2c_ocores_device_data4 = { + .adap_nr = 6, + .big_endian = 0, + .dev_name = "/dev/fpga0", + .reg_access_mode = 3, + .dev_base = 0x0880, + .reg_shift = 2, + .reg_io_width = 4, + .ip_clock_khz = 125000, + .bus_clock_khz = 100, + .irq_offset = 4, + .pci_domain = 0, + .pci_bus = 8, + .pci_slot = 0, + .pci_fn = 0, +}; + +static i2c_ocores_device_t i2c_ocores_device_data5 = { + .adap_nr = 7, + .big_endian = 0, + .dev_name = "/dev/fpga0", + .reg_access_mode = 3, + .dev_base = 0x08a0, + .reg_shift = 2, + .reg_io_width = 4, + .ip_clock_khz = 125000, + .bus_clock_khz = 100, + .irq_offset = 5, + .pci_domain = 0, + .pci_bus = 8, + .pci_slot = 0, + .pci_fn = 0, +}; + +static i2c_ocores_device_t i2c_ocores_device_data6 = { + .adap_nr = 8, + .big_endian = 0, + .dev_name = "/dev/fpga0", + .reg_access_mode = 3, + .dev_base = 0x08c0, + .reg_shift = 2, + .reg_io_width = 4, + .ip_clock_khz = 125000, + .bus_clock_khz = 100, + .irq_offset = 6, + .pci_domain = 0, + .pci_bus = 8, + .pci_slot = 0, + .pci_fn = 0, +}; + +static i2c_ocores_device_t i2c_ocores_device_data7 = { + .adap_nr = 9, + .big_endian = 0, + .dev_name = "/dev/fpga0", + .reg_access_mode = 3, + .dev_base = 0x08e0, + .reg_shift = 2, + .reg_io_width = 4, + .ip_clock_khz = 125000, + .bus_clock_khz = 100, + .irq_offset = 7, + .pci_domain = 0, + .pci_bus = 8, + .pci_slot = 0, + .pci_fn = 0, +}; + +static i2c_ocores_device_t i2c_ocores_device_data8 = { + .adap_nr = 10, + .big_endian = 0, + .dev_name = "/dev/fpga0", + .reg_access_mode = 3, + .dev_base = 0x0900, + .reg_shift = 2, + .reg_io_width = 4, + .ip_clock_khz = 125000, + .bus_clock_khz = 100, + .irq_offset = 8, + .pci_domain = 0, + .pci_bus = 8, + .pci_slot = 0, + .pci_fn = 0, +}; + +static i2c_ocores_device_t i2c_ocores_device_data9 = { + .adap_nr = 11, + .big_endian = 0, + .dev_name = "/dev/fpga0", + .reg_access_mode = 3, + .dev_base = 0x0920, + .reg_shift = 2, + .reg_io_width = 4, + .ip_clock_khz = 125000, + .bus_clock_khz = 100, + .irq_offset = 9, + .pci_domain = 0, + .pci_bus = 8, + .pci_slot = 0, + .pci_fn = 0, +}; + +static i2c_ocores_device_t i2c_ocores_device_data10 = { + .adap_nr = 12, + .big_endian = 0, + .dev_name = "/dev/fpga0", + .reg_access_mode = 3, + .dev_base = 0x0940, + .reg_shift = 2, + .reg_io_width = 4, + .ip_clock_khz = 125000, + .bus_clock_khz = 100, + .irq_offset = 10, + .pci_domain = 0, + .pci_bus = 8, + .pci_slot = 0, + .pci_fn = 0, +}; + +static i2c_ocores_device_t i2c_ocores_device_data11 = { + .adap_nr = 13, + .big_endian = 0, + .dev_name = "/dev/fpga0", + .reg_access_mode = 3, + .dev_base = 0x0960, + .reg_shift = 2, + .reg_io_width = 4, + .ip_clock_khz = 125000, + .bus_clock_khz = 100, + .irq_offset = 11, + .pci_domain = 0, + .pci_bus = 8, + .pci_slot = 0, + .pci_fn = 0, +}; + +static i2c_ocores_device_t i2c_ocores_device_data12 = { + .adap_nr = 14, + .big_endian = 0, + .dev_name = "/dev/fpga0", + .reg_access_mode = 3, + .dev_base = 0x0980, + .reg_shift = 2, + .reg_io_width = 4, + .ip_clock_khz = 125000, + .bus_clock_khz = 100, + .irq_offset = 12, + .pci_domain = 0, + .pci_bus = 8, + .pci_slot = 0, + .pci_fn = 0, +}; + +static i2c_ocores_device_t i2c_ocores_device_data13 = { + .adap_nr = 15, + .big_endian = 0, + .dev_name = "/dev/fpga0", + .reg_access_mode = 3, + .dev_base = 0x09a0, + .reg_shift = 2, + .reg_io_width = 4, + .ip_clock_khz = 125000, + .bus_clock_khz = 100, + .irq_offset = 13, + .pci_domain = 0, + .pci_bus = 8, + .pci_slot = 0, + .pci_fn = 0, +}; + +static void wb_i2c_ocores_device_release(struct device *dev) +{ + return; +} + +static struct platform_device i2c_ocores_device[] = { + { + .name = "wb-ocores-i2c", + .id = 1, + .dev = { + .platform_data = &i2c_ocores_device_data0, + .release = wb_i2c_ocores_device_release, + }, + }, + { + .name = "wb-ocores-i2c", + .id = 2, + .dev = { + .platform_data = &i2c_ocores_device_data1, + .release = wb_i2c_ocores_device_release, + }, + }, + { + .name = "wb-ocores-i2c", + .id = 3, + .dev = { + .platform_data = &i2c_ocores_device_data2, + .release = wb_i2c_ocores_device_release, + }, + }, + { + .name = "wb-ocores-i2c", + .id = 4, + .dev = { + .platform_data = &i2c_ocores_device_data3, + .release = wb_i2c_ocores_device_release, + }, + }, + { + .name = "wb-ocores-i2c", + .id = 5, + .dev = { + .platform_data = &i2c_ocores_device_data4, + .release = wb_i2c_ocores_device_release, + }, + }, + { + .name = "wb-ocores-i2c", + .id = 6, + .dev = { + .platform_data = &i2c_ocores_device_data5, + .release = wb_i2c_ocores_device_release, + }, + }, + { + .name = "wb-ocores-i2c", + .id = 7, + .dev = { + .platform_data = &i2c_ocores_device_data6, + .release = wb_i2c_ocores_device_release, + }, + }, + { + .name = "wb-ocores-i2c", + .id = 8, + .dev = { + .platform_data = &i2c_ocores_device_data7, + .release = wb_i2c_ocores_device_release, + }, + }, + { + .name = "wb-ocores-i2c", + .id = 9, + .dev = { + .platform_data = &i2c_ocores_device_data8, + .release = wb_i2c_ocores_device_release, + }, + }, + { + .name = "wb-ocores-i2c", + .id = 10, + .dev = { + .platform_data = &i2c_ocores_device_data9, + .release = wb_i2c_ocores_device_release, + }, + }, + { + .name = "wb-ocores-i2c", + .id = 11, + .dev = { + .platform_data = &i2c_ocores_device_data10, + .release = wb_i2c_ocores_device_release, + }, + }, + { + .name = "wb-ocores-i2c", + .id = 12, + .dev = { + .platform_data = &i2c_ocores_device_data11, + .release = wb_i2c_ocores_device_release, + }, + }, + { + .name = "wb-ocores-i2c", + .id = 13, + .dev = { + .platform_data = &i2c_ocores_device_data12, + .release = wb_i2c_ocores_device_release, + }, + }, + { + .name = "wb-ocores-i2c", + .id = 14, + .dev = { + .platform_data = &i2c_ocores_device_data13, + .release = wb_i2c_ocores_device_release, + }, + }, +}; + +static int __init wb_i2c_ocores_device_init(void) +{ + int i; + int ret = 0; + i2c_ocores_device_t *i2c_ocores_device_data; + + WB_I2C_OCORE_DEVICE_DEBUG_VERBOSE("enter!\n"); + for (i = 0; i < ARRAY_SIZE(i2c_ocores_device); i++) { + i2c_ocores_device_data = i2c_ocores_device[i].dev.platform_data; + ret = platform_device_register(&i2c_ocores_device[i]); + if (ret < 0) { + i2c_ocores_device_data->device_flag = -1; /* device register failed, set flag -1 */ + printk(KERN_ERR "wb-ocores-i2c.%d register failed!\n", i + 1); + } else { + i2c_ocores_device_data->device_flag = 0; /* device register suucess, set flag 0 */ + } + } + return 0; +} + +static void __exit wb_i2c_ocores_device_exit(void) +{ + int i; + i2c_ocores_device_t *i2c_ocores_device_data; + + WB_I2C_OCORE_DEVICE_DEBUG_VERBOSE("enter!\n"); + for (i = ARRAY_SIZE(i2c_ocores_device) - 1; i >= 0; i--) { + i2c_ocores_device_data = i2c_ocores_device[i].dev.platform_data; + if (i2c_ocores_device_data->device_flag == 0) { /* device register success, need unregister */ + platform_device_unregister(&i2c_ocores_device[i]); + } + } +} + +module_init(wb_i2c_ocores_device_init); +module_exit(wb_i2c_ocores_device_exit); +MODULE_DESCRIPTION("I2C OCORES Devices"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("support"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/modules/driver/wb_io_dev_device.c b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/modules/driver/wb_io_dev_device.c new file mode 100644 index 000000000000..cc84938fff0e --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/modules/driver/wb_io_dev_device.c @@ -0,0 +1,103 @@ +#include +#include +#include +#include +#include + +#include + +static int g_wb_io_dev_device_debug = 0; +static int g_wb_io_dev_device_error = 0; + +module_param(g_wb_io_dev_device_debug, int, S_IRUGO | S_IWUSR); +module_param(g_wb_io_dev_device_error, int, S_IRUGO | S_IWUSR); + +#define WB_IO_DEV_DEVICE_DEBUG_VERBOSE(fmt, args...) do { \ + if (g_wb_io_dev_device_debug) { \ + printk(KERN_INFO "[WB_IO_DEV_DEVICE][VER][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +#define WB_IO_DEV_DEVICE_DEBUG_ERROR(fmt, args...) do { \ + if (g_wb_io_dev_device_error) { \ + printk(KERN_ERR "[WB_IO_DEV_DEVICE][ERR][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +static io_dev_device_t io_dev_device_data0 = { + .io_dev_name = "cpld0", + .io_base = 0x700, + .io_len = 0x100, + .indirect_addr = 0, +}; + +static io_dev_device_t io_dev_device_data1 = { + .io_dev_name = "cpld1", + .io_base = 0x900, + .io_len = 0x100, + .indirect_addr = 0, +}; + +static void wb_io_dev_device_release(struct device *dev) +{ + return; +} + +static struct platform_device io_dev_device[] = { + { + .name = "wb-io-dev", + .id = 1, + .dev = { + .platform_data = &io_dev_device_data0, + .release = wb_io_dev_device_release, + }, + }, + { + .name = "wb-io-dev", + .id = 2, + .dev = { + .platform_data = &io_dev_device_data1, + .release = wb_io_dev_device_release, + }, + }, +}; + +static int __init wb_io_dev_device_init(void) +{ + int i; + int ret = 0; + io_dev_device_t *io_dev_device_data; + + WB_IO_DEV_DEVICE_DEBUG_VERBOSE("enter!\n"); + for (i = 0; i < ARRAY_SIZE(io_dev_device); i++) { + io_dev_device_data = io_dev_device[i].dev.platform_data; + ret = platform_device_register(&io_dev_device[i]); + if (ret < 0) { + io_dev_device_data->device_flag = -1; /* device register failed, set flag -1 */ + printk(KERN_ERR "wb-io-dev.%d register failed!\n", i + 1); + } else { + io_dev_device_data->device_flag = 0; /* device register suucess, set flag 0 */ + } + } + return 0; +} + +static void __exit wb_io_dev_device_exit(void) +{ + int i; + io_dev_device_t *io_dev_device_data; + + WB_IO_DEV_DEVICE_DEBUG_VERBOSE("enter!\n"); + for (i = ARRAY_SIZE(io_dev_device) - 1; i >= 0; i--) { + io_dev_device_data = io_dev_device[i].dev.platform_data; + if (io_dev_device_data->device_flag == 0) { /* device register success, need unregister */ + platform_device_unregister(&io_dev_device[i]); + } + } +} + +module_init(wb_io_dev_device_init); +module_exit(wb_io_dev_device_exit); +MODULE_DESCRIPTION("IO DEV Devices"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("support"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/modules/driver/wb_lpc_drv_device.c b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/modules/driver/wb_lpc_drv_device.c new file mode 100644 index 000000000000..9b6b61a51735 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/modules/driver/wb_lpc_drv_device.c @@ -0,0 +1,130 @@ +#include +#include +#include +#include +#include + +#include + +static int g_wb_lpc_drv_device_debug = 0; +static int g_wb_lpc_drv_device_error = 0; + +module_param(g_wb_lpc_drv_device_debug, int, S_IRUGO | S_IWUSR); +module_param(g_wb_lpc_drv_device_error, int, S_IRUGO | S_IWUSR); + +#define WB_LPC_DRV_DEVICE_DEBUG_VERBOSE(fmt, args...) do { \ + if (g_wb_lpc_drv_device_debug) { \ + printk(KERN_INFO "[WB_LPC_DRV_DEVICE][VER][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +#define WB_LPC_DRV_DEVICE_DEBUG_ERROR(fmt, args...) do { \ + if (g_wb_lpc_drv_device_error) { \ + printk(KERN_ERR "[WB_LPC_DRV_DEVICE][ERR][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +static lpc_drv_device_t lpc_drv_device_data_0 = { + .lpc_io_name = "wb_lpc", + .pci_domain = 0x0000, + .pci_bus = 0x00, + .pci_slot = 0x1f, + .pci_fn = 0, + .lpc_io_base = 0x700, + .lpc_io_size = 0x100, + .lpc_gen_dec = 0x84, +}; + +static lpc_drv_device_t lpc_drv_device_data_1 = { + .lpc_io_name = "wb_lpc", + .pci_domain = 0x0000, + .pci_bus = 0x00, + .pci_slot = 0x1f, + .pci_fn = 0, + .lpc_io_base = 0x900, + .lpc_io_size = 0x100, + .lpc_gen_dec = 0x88, +}; + +static lpc_drv_device_t lpc_drv_device_data_2 = { + .lpc_io_name = "wb_lpc", + .pci_domain = 0x0000, + .pci_bus = 0x00, + .pci_slot = 0x1f, + .pci_fn = 0, + .lpc_io_base = 0xb00, + .lpc_io_size = 0x100, + .lpc_gen_dec = 0x90, +}; + +static void wb_lpc_drv_device_release(struct device *dev) +{ + return; +} + +static struct platform_device lpc_drv_device[] = { + { + .name = "wb-lpc", + .id = 1, + .dev = { + .platform_data = &lpc_drv_device_data_0, + .release = wb_lpc_drv_device_release, + }, + }, + { + .name = "wb-lpc", + .id = 2, + .dev = { + .platform_data = &lpc_drv_device_data_1, + .release = wb_lpc_drv_device_release, + }, + }, + { + .name = "wb-lpc", + .id = 3, + .dev = { + .platform_data = &lpc_drv_device_data_2, + .release = wb_lpc_drv_device_release, + }, + }, +}; + +static int __init wb_lpc_drv_device_init(void) +{ + int i; + int ret = 0; + lpc_drv_device_t *lpc_drv_device_data; + + WB_LPC_DRV_DEVICE_DEBUG_VERBOSE("enter!\n"); + for (i = 0; i < ARRAY_SIZE(lpc_drv_device); i++) { + lpc_drv_device_data = lpc_drv_device[i].dev.platform_data; + ret = platform_device_register(&lpc_drv_device[i]); + if (ret < 0) { + lpc_drv_device_data->device_flag = -1; /* device register failed, set flag -1 */ + printk(KERN_ERR "wb-lpc.%d register failed!\n", i + 1); + } else { + lpc_drv_device_data->device_flag = 0; /* device register suucess, set flag 0 */ + } + } + return 0; +} + +static void __exit wb_lpc_drv_device_exit(void) +{ + int i; + lpc_drv_device_t *lpc_drv_device_data; + + WB_LPC_DRV_DEVICE_DEBUG_VERBOSE("enter!\n"); + for (i = ARRAY_SIZE(lpc_drv_device) - 1; i >= 0; i--) { + lpc_drv_device_data = lpc_drv_device[i].dev.platform_data; + if (lpc_drv_device_data->device_flag == 0) { /* device register success, need unregister */ + platform_device_unregister(&lpc_drv_device[i]); + } + } +} + +module_init(wb_lpc_drv_device_init); +module_exit(wb_lpc_drv_device_exit); +MODULE_DESCRIPTION("LPC DRV Devices"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("support"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/modules/driver/wb_pcie_dev_device.c b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/modules/driver/wb_pcie_dev_device.c new file mode 100644 index 000000000000..f79b29770d29 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/modules/driver/wb_pcie_dev_device.c @@ -0,0 +1,93 @@ +#include +#include +#include +#include +#include + +#include + +static int g_wb_pcie_dev_device_debug = 0; +static int g_wb_pcie_dev_device_error = 0; + +module_param(g_wb_pcie_dev_device_debug, int, S_IRUGO | S_IWUSR); +module_param(g_wb_pcie_dev_device_error, int, S_IRUGO | S_IWUSR); + +#define WB_PCIE_DEV_DEVICE_DEBUG_VERBOSE(fmt, args...) do { \ + if (g_wb_pcie_dev_device_debug) { \ + printk(KERN_INFO "[WB_PCIE_DEV_DEVICE][VER][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +#define WB_PCIE_DEV_DEVICE_DEBUG_ERROR(fmt, args...) do { \ + if (g_wb_pcie_dev_device_error) { \ + printk(KERN_ERR "[WB_PCIE_DEV_DEVICE][ERR][func:%s line:%d]\r\n"fmt, __func__, __LINE__, ## args); \ + } \ +} while (0) + +static pci_dev_device_t pcie_dev_device_data0 = { + .pci_dev_name = "fpga0", + .pci_domain = 0x0000, + .pci_bus = 0x08, + .pci_slot = 0x00, + .pci_fn = 0, + .pci_bar = 0, + .bus_width = 4, + .upg_ctrl_base = 0xa00, + .upg_flash_base = 0x1a0000, +}; + +static void wb_pcie_dev_device_release(struct device *dev) +{ + return; +} + +static struct platform_device pcie_dev_device[] = { + { + .name = "wb-pci-dev", + .id = 1, + .dev = { + .platform_data = &pcie_dev_device_data0, + .release = wb_pcie_dev_device_release, + }, + }, +}; + +static int __init wb_pcie_dev_device_init(void) +{ + int i; + int ret = 0; + pci_dev_device_t *pcie_dev_device_data; + + WB_PCIE_DEV_DEVICE_DEBUG_VERBOSE("enter!\n"); + for (i = 0; i < ARRAY_SIZE(pcie_dev_device); i++) { + pcie_dev_device_data = pcie_dev_device[i].dev.platform_data; + ret = platform_device_register(&pcie_dev_device[i]); + if (ret < 0) { + pcie_dev_device_data->device_flag = -1; /* device register failed, set flag -1 */ + printk(KERN_ERR "wb-pci-dev.%d register failed!\n", i + 1); + } else { + pcie_dev_device_data->device_flag = 0; /* device register suucess, set flag 0 */ + } + } + return 0; +} + +static void __exit wb_pcie_dev_device_exit(void) +{ + int i; + pci_dev_device_t *pcie_dev_device_data; + + WB_PCIE_DEV_DEVICE_DEBUG_VERBOSE("enter!\n"); + for (i = ARRAY_SIZE(pcie_dev_device) - 1; i >= 0; i--) { + pcie_dev_device_data = pcie_dev_device[i].dev.platform_data; + if (pcie_dev_device_data->device_flag == 0) { /* device register success, need unregister */ + platform_device_unregister(&pcie_dev_device[i]); + } + } +} + +module_init(wb_pcie_dev_device_init); +module_exit(wb_pcie_dev_device_exit); +MODULE_DESCRIPTION("PCIE DEV Devices"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("support"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/plat_sysfs_cfg/WB_PLAT_CPLD.cfg b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/plat_sysfs_cfg/WB_PLAT_CPLD.cfg new file mode 100644 index 000000000000..98d1da1750c3 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/plat_sysfs_cfg/WB_PLAT_CPLD.cfg @@ -0,0 +1,41 @@ +# configuration item: I2C address of CPLD +# format: cpld_i2c_dev.bus_[cpld_slot]_[cpld_id] cpld_i2c_dev.addr_[cpld_slot]_[cpld_id] +# cpld_slot: Main card: 0, linear card: start from 1 +# cpld_id: start from 0 +# bus: I2C bus number of CPLD +# addr: I2C address of CPLD +cpld_i2c_dev.bus_0_2=2 +cpld_i2c_dev.addr_0_2=0x0d +cpld_i2c_dev.bus_0_3=8 +cpld_i2c_dev.addr_0_3=0x30 +cpld_i2c_dev.bus_0_4=8 +cpld_i2c_dev.addr_0_4=0x31 +cpld_i2c_dev.bus_0_5=6 +cpld_i2c_dev.addr_0_5=0x0d + + +# configuration item: LPC address of CPLD +# format: cpld_lpc_addr_[cpld_slot]_[cpld_id] +# cpld_slot: Main card: 0, linear card: start from 1 +# cpld_id: start from 0 +cpld_lpc_dev_0_0=0x700 +cpld_lpc_dev_0_1=0x900 + + +# configuration item: CPLD access method, lpc or i2c +# format: mode_cpld_[cpld_slot][cpld_slot]=lpc/i2c +# cpld_slot: Main card: 0, linear card: start from 1 +# cpld_id: start from 0 +mode_cpld_0_0=lpc +mode_cpld_0_1=lpc +mode_cpld_0_2=i2c +mode_cpld_0_3=i2c +mode_cpld_0_4=i2c +mode_cpld_0_5=i2c + + +# configuration item: the number of CPLD +# format: dev_num_[main_dev]_[minor_dev] +# main_dev: CPLD main_dev is 4 +# minor_dev: CPLD minor_dev not exist +dev_num_4_0=6 diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/plat_sysfs_cfg/WB_PLAT_FAN.cfg b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/plat_sysfs_cfg/WB_PLAT_FAN.cfg new file mode 100644 index 000000000000..2350b74eb8bc --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/plat_sysfs_cfg/WB_PLAT_FAN.cfg @@ -0,0 +1,304 @@ +# configuration item: the number of fans +# format: dev_num_[main_dev]_[minor_dev] +# main_dev: fan main_dev is 1 +# minor_dev: fan minor_dev not exist(0) +dev_num_1_0=4 + + +# configuration item: the number of rotors +# format: dev_num_[main_dev]_[minor_dev] +# main_dev: rotor main_dev is 1 +# minor_dev: rotor minor_dev is 5 +dev_num_1_5=2 + + +# configuration item: fan presence status +# format: dev_present_status_[main_dev_id][fan_index] +# main_dev_id: fan main_dev_id is 1 +# fan_index: start from 1 +dev_present_status.mode_1_1=config +dev_present_status.src_1_1=cpld +dev_present_status.frmt_1_1=bit +dev_present_status.pola_1_1=negative +dev_present_status.addr_1_1=0x00020030 +dev_present_status.len_1_1=1 +dev_present_status.bit_offset_1_1=0 + +dev_present_status.mode_1_2=config +dev_present_status.src_1_2=cpld +dev_present_status.frmt_1_2=bit +dev_present_status.pola_1_2=negative +dev_present_status.addr_1_2=0x00020030 +dev_present_status.len_1_2=1 +dev_present_status.bit_offset_1_2=1 + +dev_present_status.mode_1_3=config +dev_present_status.src_1_3=cpld +dev_present_status.frmt_1_3=bit +dev_present_status.pola_1_3=negative +dev_present_status.addr_1_3=0x00020030 +dev_present_status.len_1_3=1 +dev_present_status.bit_offset_1_3=2 + +dev_present_status.mode_1_4=config +dev_present_status.src_1_4=cpld +dev_present_status.frmt_1_4=bit +dev_present_status.pola_1_4=negative +dev_present_status.addr_1_4=0x00020030 +dev_present_status.len_1_4=1 +dev_present_status.bit_offset_1_4=3 + + +# configuration item: fan rotor status +# format: fan_roll_status_[fan_id]_[motor_id] +# fan_id: start from 1 +# motor_id: start from 0 +fan_roll_status.mode_1_0=config +fan_roll_status.int_cons_1_0= +fan_roll_status.src_1_0=cpld +fan_roll_status.frmt_1_0=bit +fan_roll_status.pola_1_0=positive +fan_roll_status.fpath_1_0= +fan_roll_status.addr_1_0=0x00020031 +fan_roll_status.len_1_0=1 +fan_roll_status.bit_offset_1_0=0 + +fan_roll_status.mode_1_1=config +fan_roll_status.int_cons_1_1= +fan_roll_status.src_1_1=cpld +fan_roll_status.frmt_1_1=bit +fan_roll_status.pola_1_1=positive +fan_roll_status.fpath_1_1= +fan_roll_status.addr_1_1=0x00020034 +fan_roll_status.len_1_1=1 +fan_roll_status.bit_offset_1_1=0 + +fan_roll_status.mode_2_0=config +fan_roll_status.int_cons_2_0= +fan_roll_status.src_2_0=cpld +fan_roll_status.frmt_2_0=bit +fan_roll_status.pola_2_0=positive +fan_roll_status.fpath_2_0= +fan_roll_status.addr_2_0=0x00020031 +fan_roll_status.len_2_0=1 +fan_roll_status.bit_offset_2_0=1 + +fan_roll_status.mode_2_1=config +fan_roll_status.int_cons_2_1= +fan_roll_status.src_2_1=cpld +fan_roll_status.frmt_2_1=bit +fan_roll_status.pola_2_1=positive +fan_roll_status.fpath_2_1= +fan_roll_status.addr_2_1=0x00020034 +fan_roll_status.len_2_1=1 +fan_roll_status.bit_offset_2_1=1 + +fan_roll_status.mode_3_0=config +fan_roll_status.int_cons_3_0= +fan_roll_status.src_3_0=cpld +fan_roll_status.frmt_3_0=bit +fan_roll_status.pola_3_0=positive +fan_roll_status.fpath_3_0= +fan_roll_status.addr_3_0=0x00020031 +fan_roll_status.len_3_0=1 +fan_roll_status.bit_offset_3_0=2 + +fan_roll_status.mode_3_1=config +fan_roll_status.int_cons_3_1= +fan_roll_status.src_3_1=cpld +fan_roll_status.frmt_3_1=bit +fan_roll_status.pola_3_1=positive +fan_roll_status.fpath_3_1= +fan_roll_status.addr_3_1=0x00020034 +fan_roll_status.len_3_1=1 +fan_roll_status.bit_offset_3_1=2 + +fan_roll_status.mode_4_0=config +fan_roll_status.int_cons_4_0= +fan_roll_status.src_4_0=cpld +fan_roll_status.frmt_4_0=bit +fan_roll_status.pola_4_0=positive +fan_roll_status.fpath_4_0= +fan_roll_status.addr_4_0=0x00020031 +fan_roll_status.len_4_0=1 +fan_roll_status.bit_offset_4_0=3 + +fan_roll_status.mode_4_1=config +fan_roll_status.int_cons_4_1= +fan_roll_status.src_4_1=cpld +fan_roll_status.frmt_4_1=bit +fan_roll_status.pola_4_1=positive +fan_roll_status.fpath_4_1= +fan_roll_status.addr_4_1=0x00020034 +fan_roll_status.len_4_1=1 +fan_roll_status.bit_offset_4_1=3 + + +# configuration item: fan speed +# format: fan_speed_[fan_id]_[motor_id] +# fan_id: start from 1 +# motor_id: start from 0 +fan_speed.mode_1_0=config +fan_speed.int_cons_1_0= +fan_speed.src_1_0=cpld +fan_speed.frmt_1_0=num_bytes +fan_speed.pola_1_0=negative +fan_speed.fpath_1_0= +fan_speed.addr_1_0=0x0002001b +fan_speed.len_1_0=2 +fan_speed.bit_offset_1_0= + +fan_speed.mode_1_1=config +fan_speed.int_cons_1_1= +fan_speed.src_1_1=cpld +fan_speed.frmt_1_1=num_bytes +fan_speed.pola_1_1=negative +fan_speed.fpath_1_1= +fan_speed.addr_1_1=0x00020025 +fan_speed.len_1_1=2 +fan_speed.bit_offset_1_1= + +fan_speed.mode_2_0=config +fan_speed.int_cons_2_0= +fan_speed.src_2_0=cpld +fan_speed.frmt_2_0=num_bytes +fan_speed.pola_2_0=negative +fan_speed.fpath_2_0= +fan_speed.addr_2_0=0x0002001d +fan_speed.len_2_0=2 +fan_speed.bit_offset_2_0= + +fan_speed.mode_2_1=config +fan_speed.int_cons_2_1= +fan_speed.src_2_1=cpld +fan_speed.frmt_2_1=num_bytes +fan_speed.pola_2_1=negative +fan_speed.fpath_2_1= +fan_speed.addr_2_1=0x00020027 +fan_speed.len_2_1=2 +fan_speed.bit_offset_2_1= + +fan_speed.mode_3_0=config +fan_speed.int_cons_3_0= +fan_speed.src_3_0=cpld +fan_speed.frmt_3_0=num_bytes +fan_speed.pola_3_0=negative +fan_speed.fpath_3_0= +fan_speed.addr_3_0=0x0002001f +fan_speed.len_3_0=2 +fan_speed.bit_offset_3_0= + +fan_speed.mode_3_1=config +fan_speed.int_cons_3_1= +fan_speed.src_3_1=cpld +fan_speed.frmt_3_1=num_bytes +fan_speed.pola_3_1=negative +fan_speed.fpath_3_1= +fan_speed.addr_3_1=0x00020029 +fan_speed.len_3_1=2 +fan_speed.bit_offset_3_1= + +fan_speed.mode_4_0=config +fan_speed.int_cons_4_0= +fan_speed.src_4_0=cpld +fan_speed.frmt_4_0=num_bytes +fan_speed.pola_4_0=negative +fan_speed.fpath_4_0= +fan_speed.addr_4_0=0x00020021 +fan_speed.len_4_0=2 +fan_speed.bit_offset_4_0= + +fan_speed.mode_4_1=config +fan_speed.int_cons_4_1= +fan_speed.src_4_1=cpld +fan_speed.frmt_4_1=num_bytes +fan_speed.pola_4_1=negative +fan_speed.fpath_4_1= +fan_speed.addr_4_1=0x0002002b +fan_speed.len_4_1=2 +fan_speed.bit_offset_4_1= + + +# configuration item: fan pwm +# format: fan_ratio_[fan_id]_[motor_id] +# fan_id: start from 1 +# motor_id: start from 0 +fan_ratio.mode_1_0=config +fan_ratio.int_cons_1_0= +fan_ratio.src_1_0=cpld +fan_ratio.frmt_1_0=byte +fan_ratio.pola_1_0= +fan_ratio.fpath_1_0= +fan_ratio.addr_1_0=0x00020014 +fan_ratio.len_1_0=1 +fan_ratio.bit_offset_1_0= + +fan_ratio.mode_1_1=config +fan_ratio.int_cons_1_1= +fan_ratio.src_1_1=cpld +fan_ratio.frmt_1_1=byte +fan_ratio.pola_1_1= +fan_ratio.fpath_1_1= +fan_ratio.addr_1_1=0x00020014 +fan_ratio.len_1_1=1 +fan_ratio.bit_offset_1_1= + +fan_ratio.mode_2_0=config +fan_ratio.int_cons_2_0= +fan_ratio.src_2_0=cpld +fan_ratio.frmt_2_0=byte +fan_ratio.pola_2_0= +fan_ratio.fpath_2_0= +fan_ratio.addr_2_0=0x00020015 +fan_ratio.len_2_0=1 +fan_ratio.bit_offset_2_0= + +fan_ratio.mode_2_1=config +fan_ratio.int_cons_2_1= +fan_ratio.src_2_1=cpld +fan_ratio.frmt_2_1=byte +fan_ratio.pola_2_1= +fan_ratio.fpath_2_1= +fan_ratio.addr_2_1=0x00020015 +fan_ratio.len_2_1=1 +fan_ratio.bit_offset_2_1= + +fan_ratio.mode_3_0=config +fan_ratio.int_cons_3_0= +fan_ratio.src_3_0=cpld +fan_ratio.frmt_3_0=byte +fan_ratio.pola_3_0= +fan_ratio.fpath_3_0= +fan_ratio.addr_3_0=0x00020016 +fan_ratio.len_3_0=1 +fan_ratio.bit_offset_3_0= + +fan_ratio.mode_3_1=config +fan_ratio.int_cons_3_1= +fan_ratio.src_3_1=cpld +fan_ratio.frmt_3_1=byte +fan_ratio.pola_3_1= +fan_ratio.fpath_3_1= +fan_ratio.addr_3_1=0x00020016 +fan_ratio.len_3_1=1 +fan_ratio.bit_offset_3_1= + +fan_ratio.mode_4_0=config +fan_ratio.int_cons_4_0= +fan_ratio.src_4_0=cpld +fan_ratio.frmt_4_0=byte +fan_ratio.pola_4_0= +fan_ratio.fpath_4_0= +fan_ratio.addr_4_0=0x00020017 +fan_ratio.len_4_0=1 +fan_ratio.bit_offset_4_0= + +fan_ratio.mode_4_1=config +fan_ratio.int_cons_4_1= +fan_ratio.src_4_1=cpld +fan_ratio.frmt_4_1=byte +fan_ratio.pola_4_1= +fan_ratio.fpath_4_1= +fan_ratio.addr_4_1=0x00020017 +fan_ratio.len_4_1=1 +fan_ratio.bit_offset_4_1= diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/plat_sysfs_cfg/WB_PLAT_PSU.cfg b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/plat_sysfs_cfg/WB_PLAT_PSU.cfg new file mode 100644 index 000000000000..082ef20fe97f --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/plat_sysfs_cfg/WB_PLAT_PSU.cfg @@ -0,0 +1,64 @@ +# configuration item: the number of psus +# format: dev_num_[main_dev]_[minor_dev] +# main_dev: psu main_dev is 2 +# minor_dev: psu minor_dev not exist(0) +dev_num_2_0=2 + + +# configuration item: psu status +# format: psu_status_[psu_index]_[status_id] +# psu_index: start from 1 +# status_id: 0: presence 1: output 2: alert +# psu1 presence status +psu_status.mode_1_0=config +psu_status.src_1_0=cpld +psu_status.frmt_1_0=bit +psu_status.pola_1_0=negative +psu_status.addr_1_0=0x00050051 +psu_status.len_1_0=1 +psu_status.bit_offset_1_0=0 + +# psu1 output status +psu_status.mode_1_1=config +psu_status.src_1_1=cpld +psu_status.frmt_1_1=bit +psu_status.pola_1_1=positive +psu_status.addr_1_1=0x00050051 +psu_status.len_1_1=1 +psu_status.bit_offset_1_1=1 + +# psu1 alert status +psu_status.mode_1_2=config +psu_status.src_1_2=cpld +psu_status.frmt_1_2=bit +psu_status.pola_1_2=negative +psu_status.addr_1_2=0x00050051 +psu_status.len_1_2=1 +psu_status.bit_offset_1_2=2 + +# psu2 presence status +psu_status.mode_2_0=config +psu_status.src_2_0=cpld +psu_status.frmt_2_0=bit +psu_status.pola_2_0=negative +psu_status.addr_2_0=0x00050051 +psu_status.len_2_0=1 +psu_status.bit_offset_2_0=4 + +# psu2 output status +psu_status.mode_2_1=config +psu_status.src_2_1=cpld +psu_status.frmt_2_1=bit +psu_status.pola_2_1=positive +psu_status.addr_2_1=0x00050051 +psu_status.len_2_1=1 +psu_status.bit_offset_2_1=5 + +# psu2 alert status +psu_status.mode_2_2=config +psu_status.src_2_2=cpld +psu_status.frmt_2_2=bit +psu_status.pola_2_2=negative +psu_status.addr_2_2=0x00050051 +psu_status.len_2_2=1 +psu_status.bit_offset_2_2=6 diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/plat_sysfs_cfg/WB_PLAT_SFF.cfg b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/plat_sysfs_cfg/WB_PLAT_SFF.cfg new file mode 100644 index 000000000000..7f57dfd93c5b --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/plat_sysfs_cfg/WB_PLAT_SFF.cfg @@ -0,0 +1,521 @@ +# configuration item: the number of sffs +# format: dev_num_[main_dev]_[minor_dev] +# main_dev: sff main_dev is 3 +# minor_dev: sff minor_dev not exist(0) +dev_num_3_0=56 + +# configuration item: The directory name of sff sysfs +# format: sff_dir_name_[sff_index] +# sff_index: start from 1 +sff_dir_name_1 =sff1 +sff_dir_name_2 =sff2 +sff_dir_name_3 =sff3 +sff_dir_name_4 =sff4 +sff_dir_name_5 =sff5 +sff_dir_name_6 =sff6 +sff_dir_name_7 =sff7 +sff_dir_name_8 =sff8 +sff_dir_name_9 =sff9 +sff_dir_name_10 =sff10 +sff_dir_name_11 =sff11 +sff_dir_name_12 =sff12 +sff_dir_name_13 =sff13 +sff_dir_name_14 =sff14 +sff_dir_name_15 =sff15 +sff_dir_name_16 =sff16 +sff_dir_name_17 =sff17 +sff_dir_name_18 =sff18 +sff_dir_name_19 =sff19 +sff_dir_name_20 =sff20 +sff_dir_name_21 =sff21 +sff_dir_name_22 =sff22 +sff_dir_name_23 =sff23 +sff_dir_name_24 =sff24 +sff_dir_name_25 =sff25 +sff_dir_name_26 =sff26 +sff_dir_name_27 =sff27 +sff_dir_name_28 =sff28 +sff_dir_name_29 =sff29 +sff_dir_name_30 =sff30 +sff_dir_name_31 =sff31 +sff_dir_name_32 =sff32 +sff_dir_name_33 =sff33 +sff_dir_name_34 =sff34 +sff_dir_name_35 =sff35 +sff_dir_name_36 =sff36 +sff_dir_name_37 =sff37 +sff_dir_name_38 =sff38 +sff_dir_name_39 =sff39 +sff_dir_name_40 =sff40 +sff_dir_name_41 =sff41 +sff_dir_name_42 =sff42 +sff_dir_name_43 =sff43 +sff_dir_name_44 =sff44 +sff_dir_name_45 =sff45 +sff_dir_name_46 =sff46 +sff_dir_name_47 =sff47 +sff_dir_name_48 =sff48 +sff_dir_name_49 =sff49 +sff_dir_name_50 =sff50 +sff_dir_name_51 =sff51 +sff_dir_name_52 =sff52 +sff_dir_name_53 =sff53 +sff_dir_name_54 =sff54 +sff_dir_name_55 =sff55 +sff_dir_name_56 =sff56 + + +# configuration item: sff cpld register status +# format: sff_cpld_reg_[sff_index]_[cpld_reg] +# sff_index: start from 1 +# cpld_reg: 1: power_on, 2: tx_fault, 3: tx_dis, 4:pre_n, 5:rx_los +# 6: reset, 7: lpmode, 8: module_present, 9: interrupt + +# sff cpld presence status +sff_cpld_reg.mode_1_8=config +sff_cpld_reg.src_1_8=cpld +sff_cpld_reg.frmt_1_8=bit +sff_cpld_reg.pola_1_8=negative +sff_cpld_reg.addr_1_8=0x00030030 +sff_cpld_reg.len_1_8=1 +sff_cpld_reg.bit_offset_1_8=0 + +sff_cpld_reg.mode_2_8=config +sff_cpld_reg.src_2_8=cpld +sff_cpld_reg.frmt_2_8=bit +sff_cpld_reg.pola_2_8=negative +sff_cpld_reg.addr_2_8=0x00030030 +sff_cpld_reg.len_2_8=1 +sff_cpld_reg.bit_offset_2_8=1 + +sff_cpld_reg.mode_3_8=config +sff_cpld_reg.src_3_8=cpld +sff_cpld_reg.frmt_3_8=bit +sff_cpld_reg.pola_3_8=negative +sff_cpld_reg.addr_3_8=0x00030030 +sff_cpld_reg.len_3_8=1 +sff_cpld_reg.bit_offset_3_8=2 + +sff_cpld_reg.mode_4_8=config +sff_cpld_reg.src_4_8=cpld +sff_cpld_reg.frmt_4_8=bit +sff_cpld_reg.pola_4_8=negative +sff_cpld_reg.addr_4_8=0x00030030 +sff_cpld_reg.len_4_8=1 +sff_cpld_reg.bit_offset_4_8=3 + +sff_cpld_reg.mode_5_8=config +sff_cpld_reg.src_5_8=cpld +sff_cpld_reg.frmt_5_8=bit +sff_cpld_reg.pola_5_8=negative +sff_cpld_reg.addr_5_8=0x00030030 +sff_cpld_reg.len_5_8=1 +sff_cpld_reg.bit_offset_5_8=4 + +sff_cpld_reg.mode_6_8=config +sff_cpld_reg.src_6_8=cpld +sff_cpld_reg.frmt_6_8=bit +sff_cpld_reg.pola_6_8=negative +sff_cpld_reg.addr_6_8=0x00030030 +sff_cpld_reg.len_6_8=1 +sff_cpld_reg.bit_offset_6_8=5 + +sff_cpld_reg.mode_7_8=config +sff_cpld_reg.src_7_8=cpld +sff_cpld_reg.frmt_7_8=bit +sff_cpld_reg.pola_7_8=negative +sff_cpld_reg.addr_7_8=0x00030030 +sff_cpld_reg.len_7_8=1 +sff_cpld_reg.bit_offset_7_8=6 + +sff_cpld_reg.mode_8_8=config +sff_cpld_reg.src_8_8=cpld +sff_cpld_reg.frmt_8_8=bit +sff_cpld_reg.pola_8_8=negative +sff_cpld_reg.addr_8_8=0x00030030 +sff_cpld_reg.len_8_8=1 +sff_cpld_reg.bit_offset_8_8=7 + +sff_cpld_reg.mode_9_8=config +sff_cpld_reg.src_9_8=cpld +sff_cpld_reg.frmt_9_8=bit +sff_cpld_reg.pola_9_8=negative +sff_cpld_reg.addr_9_8=0x00030031 +sff_cpld_reg.len_9_8=1 +sff_cpld_reg.bit_offset_9_8=0 + +sff_cpld_reg.mode_10_8=config +sff_cpld_reg.src_10_8=cpld +sff_cpld_reg.frmt_10_8=bit +sff_cpld_reg.pola_10_8=negative +sff_cpld_reg.addr_10_8=0x00030031 +sff_cpld_reg.len_10_8=1 +sff_cpld_reg.bit_offset_10_8=1 + +sff_cpld_reg.mode_11_8=config +sff_cpld_reg.src_11_8=cpld +sff_cpld_reg.frmt_11_8=bit +sff_cpld_reg.pola_11_8=negative +sff_cpld_reg.addr_11_8=0x00030031 +sff_cpld_reg.len_11_8=1 +sff_cpld_reg.bit_offset_11_8=2 + +sff_cpld_reg.mode_12_8=config +sff_cpld_reg.src_12_8=cpld +sff_cpld_reg.frmt_12_8=bit +sff_cpld_reg.pola_12_8=negative +sff_cpld_reg.addr_12_8=0x00030031 +sff_cpld_reg.len_12_8=1 +sff_cpld_reg.bit_offset_12_8=3 + +sff_cpld_reg.mode_13_8=config +sff_cpld_reg.src_13_8=cpld +sff_cpld_reg.frmt_13_8=bit +sff_cpld_reg.pola_13_8=negative +sff_cpld_reg.addr_13_8=0x00030031 +sff_cpld_reg.len_13_8=1 +sff_cpld_reg.bit_offset_13_8=4 + +sff_cpld_reg.mode_14_8=config +sff_cpld_reg.src_14_8=cpld +sff_cpld_reg.frmt_14_8=bit +sff_cpld_reg.pola_14_8=negative +sff_cpld_reg.addr_14_8=0x00030031 +sff_cpld_reg.len_14_8=1 +sff_cpld_reg.bit_offset_14_8=5 + +sff_cpld_reg.mode_15_8=config +sff_cpld_reg.src_15_8=cpld +sff_cpld_reg.frmt_15_8=bit +sff_cpld_reg.pola_15_8=negative +sff_cpld_reg.addr_15_8=0x00030031 +sff_cpld_reg.len_15_8=1 +sff_cpld_reg.bit_offset_15_8=6 + +sff_cpld_reg.mode_16_8=config +sff_cpld_reg.src_16_8=cpld +sff_cpld_reg.frmt_16_8=bit +sff_cpld_reg.pola_16_8=negative +sff_cpld_reg.addr_16_8=0x00030031 +sff_cpld_reg.len_16_8=1 +sff_cpld_reg.bit_offset_16_8=7 + +sff_cpld_reg.mode_17_8=config +sff_cpld_reg.src_17_8=cpld +sff_cpld_reg.frmt_17_8=bit +sff_cpld_reg.pola_17_8=negative +sff_cpld_reg.addr_17_8=0x00030032 +sff_cpld_reg.len_17_8=1 +sff_cpld_reg.bit_offset_17_8=0 + +sff_cpld_reg.mode_18_8=config +sff_cpld_reg.src_18_8=cpld +sff_cpld_reg.frmt_18_8=bit +sff_cpld_reg.pola_18_8=negative +sff_cpld_reg.addr_18_8=0x00030032 +sff_cpld_reg.len_18_8=1 +sff_cpld_reg.bit_offset_18_8=1 + +sff_cpld_reg.mode_19_8=config +sff_cpld_reg.src_19_8=cpld +sff_cpld_reg.frmt_19_8=bit +sff_cpld_reg.pola_19_8=negative +sff_cpld_reg.addr_19_8=0x00030032 +sff_cpld_reg.len_19_8=1 +sff_cpld_reg.bit_offset_19_8=2 + +sff_cpld_reg.mode_20_8=config +sff_cpld_reg.src_20_8=cpld +sff_cpld_reg.frmt_20_8=bit +sff_cpld_reg.pola_20_8=negative +sff_cpld_reg.addr_20_8=0x00030032 +sff_cpld_reg.len_20_8=1 +sff_cpld_reg.bit_offset_20_8=3 + +sff_cpld_reg.mode_21_8=config +sff_cpld_reg.src_21_8=cpld +sff_cpld_reg.frmt_21_8=bit +sff_cpld_reg.pola_21_8=negative +sff_cpld_reg.addr_21_8=0x00030032 +sff_cpld_reg.len_21_8=1 +sff_cpld_reg.bit_offset_21_8=4 + +sff_cpld_reg.mode_22_8=config +sff_cpld_reg.src_22_8=cpld +sff_cpld_reg.frmt_22_8=bit +sff_cpld_reg.pola_22_8=negative +sff_cpld_reg.addr_22_8=0x00030032 +sff_cpld_reg.len_22_8=1 +sff_cpld_reg.bit_offset_22_8=5 + +sff_cpld_reg.mode_23_8=config +sff_cpld_reg.src_23_8=cpld +sff_cpld_reg.frmt_23_8=bit +sff_cpld_reg.pola_23_8=negative +sff_cpld_reg.addr_23_8=0x00030032 +sff_cpld_reg.len_23_8=1 +sff_cpld_reg.bit_offset_23_8=6 + +sff_cpld_reg.mode_24_8=config +sff_cpld_reg.src_24_8=cpld +sff_cpld_reg.frmt_24_8=bit +sff_cpld_reg.pola_24_8=negative +sff_cpld_reg.addr_24_8=0x00030032 +sff_cpld_reg.len_24_8=1 +sff_cpld_reg.bit_offset_24_8=7 + +sff_cpld_reg.mode_25_8=config +sff_cpld_reg.src_25_8=cpld +sff_cpld_reg.frmt_25_8=bit +sff_cpld_reg.pola_25_8=negative +sff_cpld_reg.addr_25_8=0x00040030 +sff_cpld_reg.len_25_8=1 +sff_cpld_reg.bit_offset_25_8=0 + +sff_cpld_reg.mode_26_8=config +sff_cpld_reg.src_26_8=cpld +sff_cpld_reg.frmt_26_8=bit +sff_cpld_reg.pola_26_8=negative +sff_cpld_reg.addr_26_8=0x00040030 +sff_cpld_reg.len_26_8=1 +sff_cpld_reg.bit_offset_26_8=1 + +sff_cpld_reg.mode_27_8=config +sff_cpld_reg.src_27_8=cpld +sff_cpld_reg.frmt_27_8=bit +sff_cpld_reg.pola_27_8=negative +sff_cpld_reg.addr_27_8=0x00040030 +sff_cpld_reg.len_27_8=1 +sff_cpld_reg.bit_offset_27_8=2 + +sff_cpld_reg.mode_28_8=config +sff_cpld_reg.src_28_8=cpld +sff_cpld_reg.frmt_28_8=bit +sff_cpld_reg.pola_28_8=negative +sff_cpld_reg.addr_28_8=0x00040030 +sff_cpld_reg.len_28_8=1 +sff_cpld_reg.bit_offset_28_8=3 + +sff_cpld_reg.mode_29_8=config +sff_cpld_reg.src_29_8=cpld +sff_cpld_reg.frmt_29_8=bit +sff_cpld_reg.pola_29_8=negative +sff_cpld_reg.addr_29_8=0x00040030 +sff_cpld_reg.len_29_8=1 +sff_cpld_reg.bit_offset_29_8=4 + +sff_cpld_reg.mode_30_8=config +sff_cpld_reg.src_30_8=cpld +sff_cpld_reg.frmt_30_8=bit +sff_cpld_reg.pola_30_8=negative +sff_cpld_reg.addr_30_8=0x00040030 +sff_cpld_reg.len_30_8=1 +sff_cpld_reg.bit_offset_30_8=5 + +sff_cpld_reg.mode_31_8=config +sff_cpld_reg.src_31_8=cpld +sff_cpld_reg.frmt_31_8=bit +sff_cpld_reg.pola_31_8=negative +sff_cpld_reg.addr_31_8=0x00040030 +sff_cpld_reg.len_31_8=1 +sff_cpld_reg.bit_offset_31_8=6 + +sff_cpld_reg.mode_32_8=config +sff_cpld_reg.src_32_8=cpld +sff_cpld_reg.frmt_32_8=bit +sff_cpld_reg.pola_32_8=negative +sff_cpld_reg.addr_32_8=0x00040030 +sff_cpld_reg.len_32_8=1 +sff_cpld_reg.bit_offset_32_8=7 + +sff_cpld_reg.mode_33_8=config +sff_cpld_reg.src_33_8=cpld +sff_cpld_reg.frmt_33_8=bit +sff_cpld_reg.pola_33_8=negative +sff_cpld_reg.addr_33_8=0x00040031 +sff_cpld_reg.len_33_8=1 +sff_cpld_reg.bit_offset_33_8=0 + +sff_cpld_reg.mode_34_8=config +sff_cpld_reg.src_34_8=cpld +sff_cpld_reg.frmt_34_8=bit +sff_cpld_reg.pola_34_8=negative +sff_cpld_reg.addr_34_8=0x00040031 +sff_cpld_reg.len_34_8=1 +sff_cpld_reg.bit_offset_34_8=1 + +sff_cpld_reg.mode_35_8=config +sff_cpld_reg.src_35_8=cpld +sff_cpld_reg.frmt_35_8=bit +sff_cpld_reg.pola_35_8=negative +sff_cpld_reg.addr_35_8=0x00040031 +sff_cpld_reg.len_35_8=1 +sff_cpld_reg.bit_offset_35_8=2 + +sff_cpld_reg.mode_36_8=config +sff_cpld_reg.src_36_8=cpld +sff_cpld_reg.frmt_36_8=bit +sff_cpld_reg.pola_36_8=negative +sff_cpld_reg.addr_36_8=0x00040031 +sff_cpld_reg.len_36_8=1 +sff_cpld_reg.bit_offset_36_8=3 + +sff_cpld_reg.mode_37_8=config +sff_cpld_reg.src_37_8=cpld +sff_cpld_reg.frmt_37_8=bit +sff_cpld_reg.pola_37_8=negative +sff_cpld_reg.addr_37_8=0x00040031 +sff_cpld_reg.len_37_8=1 +sff_cpld_reg.bit_offset_37_8=4 + +sff_cpld_reg.mode_38_8=config +sff_cpld_reg.src_38_8=cpld +sff_cpld_reg.frmt_38_8=bit +sff_cpld_reg.pola_38_8=negative +sff_cpld_reg.addr_38_8=0x00040031 +sff_cpld_reg.len_38_8=1 +sff_cpld_reg.bit_offset_38_8=5 + +sff_cpld_reg.mode_39_8=config +sff_cpld_reg.src_39_8=cpld +sff_cpld_reg.frmt_39_8=bit +sff_cpld_reg.pola_39_8=negative +sff_cpld_reg.addr_39_8=0x00040031 +sff_cpld_reg.len_39_8=1 +sff_cpld_reg.bit_offset_39_8=6 + +sff_cpld_reg.mode_40_8=config +sff_cpld_reg.src_40_8=cpld +sff_cpld_reg.frmt_40_8=bit +sff_cpld_reg.pola_40_8=negative +sff_cpld_reg.addr_40_8=0x00040031 +sff_cpld_reg.len_40_8=1 +sff_cpld_reg.bit_offset_40_8=7 + +sff_cpld_reg.mode_41_8=config +sff_cpld_reg.src_41_8=cpld +sff_cpld_reg.frmt_41_8=bit +sff_cpld_reg.pola_41_8=negative +sff_cpld_reg.addr_41_8=0x00040032 +sff_cpld_reg.len_41_8=1 +sff_cpld_reg.bit_offset_41_8=0 + +sff_cpld_reg.mode_42_8=config +sff_cpld_reg.src_42_8=cpld +sff_cpld_reg.frmt_42_8=bit +sff_cpld_reg.pola_42_8=negative +sff_cpld_reg.addr_42_8=0x00040032 +sff_cpld_reg.len_42_8=1 +sff_cpld_reg.bit_offset_42_8=1 + +sff_cpld_reg.mode_43_8=config +sff_cpld_reg.src_43_8=cpld +sff_cpld_reg.frmt_43_8=bit +sff_cpld_reg.pola_43_8=negative +sff_cpld_reg.addr_43_8=0x00040032 +sff_cpld_reg.len_43_8=1 +sff_cpld_reg.bit_offset_43_8=2 + +sff_cpld_reg.mode_44_8=config +sff_cpld_reg.src_44_8=cpld +sff_cpld_reg.frmt_44_8=bit +sff_cpld_reg.pola_44_8=negative +sff_cpld_reg.addr_44_8=0x00040032 +sff_cpld_reg.len_44_8=1 +sff_cpld_reg.bit_offset_44_8=3 + +sff_cpld_reg.mode_45_8=config +sff_cpld_reg.src_45_8=cpld +sff_cpld_reg.frmt_45_8=bit +sff_cpld_reg.pola_45_8=negative +sff_cpld_reg.addr_45_8=0x00040032 +sff_cpld_reg.len_45_8=1 +sff_cpld_reg.bit_offset_45_8=4 + +sff_cpld_reg.mode_46_8=config +sff_cpld_reg.src_46_8=cpld +sff_cpld_reg.frmt_46_8=bit +sff_cpld_reg.pola_46_8=negative +sff_cpld_reg.addr_46_8=0x00040032 +sff_cpld_reg.len_46_8=1 +sff_cpld_reg.bit_offset_46_8=5 + +sff_cpld_reg.mode_47_8=config +sff_cpld_reg.src_47_8=cpld +sff_cpld_reg.frmt_47_8=bit +sff_cpld_reg.pola_47_8=negative +sff_cpld_reg.addr_47_8=0x00040032 +sff_cpld_reg.len_47_8=1 +sff_cpld_reg.bit_offset_47_8=6 + +sff_cpld_reg.mode_48_8=config +sff_cpld_reg.src_48_8=cpld +sff_cpld_reg.frmt_48_8=bit +sff_cpld_reg.pola_48_8=negative +sff_cpld_reg.addr_48_8=0x00040032 +sff_cpld_reg.len_48_8=1 +sff_cpld_reg.bit_offset_48_8=7 + +sff_cpld_reg.mode_49_8=config +sff_cpld_reg.src_49_8=cpld +sff_cpld_reg.frmt_49_8=bit +sff_cpld_reg.pola_49_8=negative +sff_cpld_reg.addr_49_8=0x00040033 +sff_cpld_reg.len_49_8=1 +sff_cpld_reg.bit_offset_49_8=0 + +sff_cpld_reg.mode_50_8=config +sff_cpld_reg.src_50_8=cpld +sff_cpld_reg.frmt_50_8=bit +sff_cpld_reg.pola_50_8=negative +sff_cpld_reg.addr_50_8=0x00040033 +sff_cpld_reg.len_50_8=1 +sff_cpld_reg.bit_offset_50_8=1 + +sff_cpld_reg.mode_51_8=config +sff_cpld_reg.src_51_8=cpld +sff_cpld_reg.frmt_51_8=bit +sff_cpld_reg.pola_51_8=negative +sff_cpld_reg.addr_51_8=0x00040033 +sff_cpld_reg.len_51_8=1 +sff_cpld_reg.bit_offset_51_8=2 + +sff_cpld_reg.mode_52_8=config +sff_cpld_reg.src_52_8=cpld +sff_cpld_reg.frmt_52_8=bit +sff_cpld_reg.pola_52_8=negative +sff_cpld_reg.addr_52_8=0x00040033 +sff_cpld_reg.len_52_8=1 +sff_cpld_reg.bit_offset_52_8=3 + +sff_cpld_reg.mode_53_8=config +sff_cpld_reg.src_53_8=cpld +sff_cpld_reg.frmt_53_8=bit +sff_cpld_reg.pola_53_8=negative +sff_cpld_reg.addr_53_8=0x00040033 +sff_cpld_reg.len_53_8=1 +sff_cpld_reg.bit_offset_53_8=4 + +sff_cpld_reg.mode_54_8=config +sff_cpld_reg.src_54_8=cpld +sff_cpld_reg.frmt_54_8=bit +sff_cpld_reg.pola_54_8=negative +sff_cpld_reg.addr_54_8=0x00040033 +sff_cpld_reg.len_54_8=1 +sff_cpld_reg.bit_offset_54_8=5 + +sff_cpld_reg.mode_55_8=config +sff_cpld_reg.src_55_8=cpld +sff_cpld_reg.frmt_55_8=bit +sff_cpld_reg.pola_55_8=negative +sff_cpld_reg.addr_55_8=0x00040033 +sff_cpld_reg.len_55_8=1 +sff_cpld_reg.bit_offset_55_8=6 + +sff_cpld_reg.mode_56_8=config +sff_cpld_reg.src_56_8=cpld +sff_cpld_reg.frmt_56_8=bit +sff_cpld_reg.pola_56_8=negative +sff_cpld_reg.addr_56_8=0x00040033 +sff_cpld_reg.len_56_8=1 +sff_cpld_reg.bit_offset_56_8=7 diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/plat_sysfs_cfg/cfg_file_name b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/plat_sysfs_cfg/cfg_file_name new file mode 100644 index 000000000000..5f49420441a5 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/plat_sysfs_cfg/cfg_file_name @@ -0,0 +1,4 @@ +WB_PLAT_CPLD +WB_PLAT_FAN +WB_PLAT_PSU +WB_PLAT_SFF diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/scripts/pddf_post_driver_install.sh b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/scripts/pddf_post_driver_install.sh deleted file mode 100755 index badbce25589d..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/scripts/pddf_post_driver_install.sh +++ /dev/null @@ -1,31 +0,0 @@ -#!/bin/bash - -count=10 -while [ $count -gt 0 ] -do - lsmod | grep 9641 >/dev/null 2>&1 - if [ $? -eq 0 ] - then - break - fi - count=$(( count - 1 )) - sleep 1 -done - -if [ $count -eq 0 ] -then - # mod not loaded - exit 1 -fi - -if [ ! -d "/sys/bus/i2c/devices/i2c-2" ] -then - echo pca9541 0x10 > /sys/bus/i2c/devices/i2c-0/new_device - if [ $? -ne 0 ] - then - exit $? - fi -fi - -exit 0 - diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/setup.py b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/setup.py index f36055fb4e6d..6c3916921abb 100644 --- a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/setup.py +++ b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/setup.py @@ -3,18 +3,25 @@ setup( name='sonic-platform', version='1.0', - description='SONiC platform API implementation on RAGILE Platforms', + description='SONiC platform API implementation', license='Apache 2.0', author='SONiC Team', - author_email='support@ragile.com', + author_email='support', url='', - maintainer='RAGILE SUPPORT TEAM', + maintainer='support', maintainer_email='', packages=[ 'sonic_platform', - 'rgutil', + 'plat_hal', + 'wbutil', 'eepromutil', - 'sonic_pcie', + 'hal-config', + 'config', + ], + py_modules=[ + 'hal_pltfm', + 'platform_util', + 'platform_intf', ], classifiers=[ 'Development Status :: 3 - Alpha', @@ -30,4 +37,3 @@ ], keywords='sonic SONiC platform PLATFORM', ) - diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_pcie/__init__.py b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_pcie/__init__.py deleted file mode 100644 index 73e2a89c8d74..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_pcie/__init__.py +++ /dev/null @@ -1 +0,0 @@ -__all__ = ["pcie_common"] \ No newline at end of file diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_pcie/pcie_common.py b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_pcie/pcie_common.py deleted file mode 100644 index 12f1cc8ed7b9..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_pcie/pcie_common.py +++ /dev/null @@ -1,107 +0,0 @@ -# pcie_common.py -# Common PCIE check interfaces for SONIC -# - -import os -import yaml -import subprocess -import re -import sys -from copy import deepcopy -try: - from .pcie import PcieBase -except ImportError as e: - raise ImportError(str(e) + "- required module not found") - - -class PcieUtil(PcieBase): - """Platform-specific PCIEutil class""" - # got the config file path - def __init__(self, path): - self.config_path = path - - # load the config file - def load_config_file(self): - config_file = self.config_path + "/" + "pcie.yaml" - try: - with open(config_file) as conf_file: - self.confInfo = yaml.load(conf_file) - except IOError as e: - print("Error: {}".format(str(e))) - print("Not found config file, please add a config file manually, or generate it by running [pcieutil pcie_generate]") - sys.exit() - - # load current PCIe device - def get_pcie_device(self): - pciDict = {} - pciList = [] - p1 = "^(\w+):(\w+)\.(\w)\s(.*)\s*\(*.*\)*" - p2 = "^.*:.*:.*:(\w+)\s*\(*.*\)*" - command1 = ["sudo", "lspci"] - command2 = ["sudo", "lspci", "-n"] - # run command 1 - proc1 = subprocess.Popen(command1, universal_newlines=True, stdout=subprocess.PIPE) - output1 = proc1.stdout.readlines() - proc1.communicate() - # run command 2 - proc2 = subprocess.Popen(command2, universal_newlines=True, stdout=subprocess.PIPE) - output2 = proc2.stdout.readlines() - proc2.communicate() - - if proc1.returncode > 0: - for line1 in output1: - print(line1.strip()) - return - elif proc2.returncode > 0: - for line2 in output2: - print(line2.strip()) - return - else: - for (line1, line2) in zip(output1, output2): - pciDict.clear() - match1 = re.search(p1, line1.strip()) - match2 = re.search(p2, line2.strip()) - if match1 and match2: - Bus = match1.group(1) - Dev = match1.group(2) - Fn = match1.group(3) - Name = match1.group(4) - Id = match2.group(1) - pciDict["name"] = Name - pciDict["bus"] = Bus - pciDict["dev"] = Dev - pciDict["fn"] = Fn - pciDict["id"] = Id - pciList.append(pciDict) - pciDict = deepcopy(pciDict) - else: - print("CAN NOT MATCH PCIe DEVICE") - return pciList - - # check the sysfs tree for each PCIe device - def check_pcie_sysfs(self, domain=0, bus=0, device=0, func=0): - dev_path = os.path.join('/sys/bus/pci/devices', '%04x:%02x:%02x.%d' % (domain, bus, device, func)) - if os.path.exists(dev_path): - return True - return False - - # check the current PCIe device with config file and return the result - def get_pcie_check(self): - self.load_config_file() - for item_conf in self.confInfo: - bus_conf = item_conf["bus"] - dev_conf = item_conf["dev"] - fn_conf = item_conf["fn"] - if self.check_pcie_sysfs(bus=int(bus_conf, base=16), device=int(dev_conf, base=16), func=int(fn_conf, base=16)): - item_conf["result"] = "Passed" - else: - item_conf["result"] = "Failed" - return self.confInfo - - # generate the config file with current pci device - def dump_conf_yaml(self): - curInfo = self.get_pcie_device() - with open(self.config_path + "/" + "pcie.yaml", "w") as conf_file: - yaml.dump(curInfo, conf_file, default_flow_style=False) - return - diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/chassis.py b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/chassis.py deleted file mode 100644 index f179b279cc13..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/chassis.py +++ /dev/null @@ -1,134 +0,0 @@ -############################################################################# -# PDDF -# Module contains an implementation of SONiC Chassis API -# -############################################################################# - -try: - import time - from sonic_platform_pddf_base.pddf_chassis import PddfChassis - from .component import Component - from sonic_platform.sfp import * - from .sfp_config import * -except ImportError as e: - raise ImportError(str(e) + "- required module not found") - -class Chassis(PddfChassis): - """ - PDDF Platform-specific Chassis class - """ - - STATUS_INSERTED = "1" - STATUS_REMOVED = "0" - sfp_present_dict = {} - - def __init__(self, pddf_data=None, pddf_plugin_data=None): - PddfChassis.__init__(self, pddf_data, pddf_plugin_data) - for i in range(0,3): - self._component_list.append(Component(i)) - - try: - self._sfp_list = [] - sfp_config = get_sfp_config() - self.port_start_index = sfp_config.get("port_index_start", 0) - self.port_num = sfp_config.get("port_num", 0) - # fix problem with first index is 1, we add a fake sfp node - if self.port_start_index == 1: - self._sfp_list.append(Sfp(1)) - - # sfp id always start at 1 - for index in range(1, self.port_num + 1): - self._sfp_list.append(Sfp(index)) - - for i in range(self.port_start_index, self.port_start_index + self.port_num): - self.sfp_present_dict[i] = self.STATUS_REMOVED - - except Exception as err: - print("SFP init error: %s" % str(err)) - - def get_revision(self): - val = ord(self._eeprom.revision_str()) - test = "{}".format(val) - return test - - def get_reboot_cause(self): - """ - Retrieves the cause of the previous reboot - Returns: - A tuple (string, string) where the first element is a string - containing the cause of the previous reboot. This string must be - one of the predefined strings in this class. If the first string - is "REBOOT_CAUSE_HARDWARE_OTHER", the second string can be used - to pass a description of the reboot cause. - """ - - return (self.REBOOT_CAUSE_NON_HARDWARE, None) - - def get_change_event(self, timeout=0): - change_event_dict = {"sfp": {}} - - start_time = time.time() - forever = False - - if timeout == 0: - forever = True - elif timeout > 0: - timeout = timeout / float(1000) # Convert to secs - else: - print("get_change_event:Invalid timeout value", timeout) - return False, change_event_dict - - end_time = start_time + timeout - if start_time > end_time: - print( - "get_change_event:" "time wrap / invalid timeout value", - timeout, - ) - return False, change_event_dict # Time wrap or possibly incorrect timeout - try: - while timeout >= 0: - # check for sfp - sfp_change_dict = self.get_transceiver_change_event() - if sfp_change_dict : - change_event_dict["sfp"] = sfp_change_dict - return True, change_event_dict - if forever: - time.sleep(1) - else: - timeout = end_time - time.time() - if timeout >= 1: - time.sleep(1) # We poll at 1 second granularity - else: - if timeout > 0: - time.sleep(timeout) - return True, change_event_dict - except Exception as e: - print(e) - print("get_change_event: Should not reach here.") - return False, change_event_dict - - def get_transceiver_change_event(self): - cur_sfp_present_dict = {} - ret_dict = {} - - # Check for OIR events and return ret_dict - for i in range(self.port_start_index, self.port_start_index + self.port_num): - sfp = self._sfp_list[i] - if sfp.get_presence(): - cur_sfp_present_dict[i] = self.STATUS_INSERTED - - else: - cur_sfp_present_dict[i] = self.STATUS_REMOVED - - # Update reg value - if cur_sfp_present_dict == self.sfp_present_dict: - return ret_dict - - for index, status in cur_sfp_present_dict.items(): - if self.sfp_present_dict[index] != status: - ret_dict[index] = status - - self.sfp_present_dict = cur_sfp_present_dict - - return ret_dict - diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/common.py b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/common.py deleted file mode 100644 index e1bef19c24d7..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/common.py +++ /dev/null @@ -1,44 +0,0 @@ -import os -import yaml -import subprocess -from sonic_py_common import device_info - - -class Common: - - DEVICE_PATH = '/usr/share/sonic/device/' - PMON_PLATFORM_PATH = '/usr/share/sonic/platform/' - CONFIG_DIR = 'sonic_platform_config' - - HOST_CHK_CMD = ["docker"] - - def __init__(self): - (self.platform, self.hwsku) = device_info.get_platform_and_hwsku() - - def is_host(self): - return subprocess.call(self.HOST_CHK_CMD) == 0 - - def load_json_file(self, path): - """ - Retrieves the json object from json file path - - Returns: - A json object - """ - with open(path, 'r') as f: - json_data = yaml.safe_load(f) - - return json_data - - def get_config_path(self, config_name): - """ - Retrieves the path to platform api config directory - - Args: - config_name: A string containing the name of config file. - - Returns: - A string containing the path to json file - """ - return os.path.join(self.DEVICE_PATH, self.platform, self.CONFIG_DIR, config_name) if self.is_host() else os.path.join(self.PMON_PLATFORM_PATH, self.CONFIG_DIR, config_name) - diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/component.py b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/component.py deleted file mode 100644 index 0fd19ccf99b5..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/component.py +++ /dev/null @@ -1,110 +0,0 @@ -######################################################################## -# Ragile RA-B6510-48v8c -# -# Module contains an implementation of SONiC Platform Base API and -# provides the Components' (e.g., BIOS, CPLD, FPGA, etc.) available in -# the platform -# -######################################################################## - -try: - from sonic_platform_base.component_base import ComponentBase - from sonic_py_common.general import getstatusoutput_noshell - import sonic_platform.hwaccess as hwaccess -except ImportError as e: - raise ImportError(str(e) + "- required module not found") - -def get_cpld_version(bus, i2caddr): - return '{}{}{}{}'.format(hwaccess.i2c_get(bus, i2caddr, 1), - hwaccess.i2c_get(bus, i2caddr, 2), - hwaccess.i2c_get(bus, i2caddr, 3), - hwaccess.i2c_get(bus, i2caddr, 0) - ) - -def get_cpu_cpld_version(): - return get_cpld_version(0, 0x0d) - -def get_cpld1_version(): - return get_cpld_version(2, 0x33) - -def get_cpld2_version(): - return get_cpld_version(2, 0x35) - -COMPONENT_LIST= [ - ['CPU CPLD', - 'cpu board', - get_cpu_cpld_version - ], - - ['MAC1 CPLD', - 'mac1 board', - get_cpld1_version - ], - - ['MAC2 CPLD', - 'mac2 board', - get_cpld2_version - ] - ] - - - -class Component(ComponentBase): - """ Ragile Platform-specific Component class""" - - def __init__(self, component_index=0): - ComponentBase.__init__(self) - self.index = component_index - - def get_name(self): - """ - Retrieves the name of the component - - Returns: - A string containing the name of the component - """ - return COMPONENT_LIST[self.index][0] - - def get_description(self): - """ - Retrieves the description of the component - - Returns: - A string containing the description of the component - """ - return COMPONENT_LIST[self.index][1] - - def get_firmware_version(self): - """ - Retrieves the firmware version of the component - - Returns: - A string containing the firmware version of the component - """ - return COMPONENT_LIST[self.index][2]() - - def install_firmware(self, image_path): - """ - Installs firmware to the component - - Args: - image_path: A string, path to firmware image - - Returns: - A boolean, True if install was successful, False if not - """ - try: - successtips = "CPLD Upgrade succeeded!" - status, output = getstatusoutput_noshell(["which", "firmware_upgrade"]) - if status or len(output) <= 0: - logger.error("no upgrade tool.") - return False - cmdstr = [output, image_path, "cpld", str(self.slot), "cpld"] - ret, log = getstatusoutput_noshell(cmdstr) - if ret == 0 and successtips in log: - return True - logger.error("upgrade failed. ret:%d, log:\n%s" % (ret, log)) - except Exception as e: - logger.error(str(e)) - return False - diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/config.py b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/config.py deleted file mode 100644 index 162f01680ad0..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/config.py +++ /dev/null @@ -1,558 +0,0 @@ -# -*- coding: utf-8 -*- - -PSU_FAN_AIRFLOW = { - "CSU550AP-3-300": "F2B", - "AS-40FAN-01-F-RJ": "F2B", - "CSU550AP-3-500": "F2B", - "DPS-550AB-39 A": "F2B", - "DPS-1300AB-6 S": "F2B", - "FSP1200-20ERM": "F2B", - "CSU800AP-3-300": "F2B", - "CSU550AP-3-501": "B2F", - "DPS-550AB-40 A": "B2F", -} - -FAN_AIRFLOW = { - "AS-80FAN-01-F-RJ": "F2B", - "AS-40FAN-01-F-RJ": "F2B", - "AS-80FAN-01-R-RJ": "B2F", - "AS-40FAN-01-R-RJ": "B2F", -} - -psutypedecode = { - 0x00: "N/A", - 0x01: "AC", - 0x02: "DC", -} - - -class Unit: - Temperature = "C" - Voltage = "V" - Current = "A" - Power = "W" - Speed = "RPM" - - -class Threshold: - PSU_TEMP_MIN = -10 * 1000 - PSU_TEMP_MAX = 60 * 1000 - - PSU_FAN_SPEED_MIN = 2000 - PSU_FAN_SPEED_MAX = 28000 - - PSU_OUTPUT_VOLTAGE_MIN = 11 * 1000 - PSU_OUTPUT_VOLTAGE_MAX = 14 * 1000 - - PSU_AC_INPUT_VOLTAGE_MIN = 200 * 1000 - PSU_AC_INPUT_VOLTAGE_MAX = 240 * 1000 - - PSU_DC_INPUT_VOLTAGE_MIN = 190 * 1000 - PSU_DC_INPUT_VOLTAGE_MAX = 290 * 1000 - - ERR_VALUE = -9999999 - - PSU_OUTPUT_POWER_MIN = 10 * 1000 - PSU_OUTPUT_POWER_MAX = 1300 * 1000 - - PSU_INPUT_POWER_MIN = 10 * 1000 - PSU_INPUT_POWER_MAX = 1444 * 1000 - - PSU_OUTPUT_CURRENT_MIN = 2 * 1000 - PSU_OUTPUT_CURRENT_MAX = 107 * 1000 - - PSU_INPUT_CURRENT_MIN = 0.2 * 1000 - PSU_INPUT_CURRENT_MAX = 7 * 1000 - - FAN_SPEED_MAX = 23000 - FAN_SPEED_MIN = 500 - - -class DecodeFormat: - TEXT = 0 - DECIMAL = 1 - ONE_BIT_HEX = 2 - HUNDREDTH = 3 - THOUSANDTH = 4 - MILLIONTH = 5 - AND = 6 - JOIN = 7 - - -class DecodeMethod: - SYSFS = 0 - I2C = 1 - I2C_WORD = 2 - DEVMEM = 3 - SDK = 4 - - -class Description: - CPLD = "Used for managing IO modules, SFP+ modules and system LEDs" - BIOS = "Performs initialization of hardware components during booting" - FPGA = "Platform management controller for on-board temperature monitoring, in-chassis power, Fan and LED control" - - -FAN_LED_COLORS = { - "green": 0b1001, - "red": 0b1010, - "amber": 0b0011, -} - - -DEVICE_CONF = { - "eeprom": {"bus": 2, "loc": "0057"}, - "components": [ - { - "name": "CPLD1 (MAC Board A)", - "firmware_version": { - "bus": 2, - "addr": 0x33, - "offset": 0, - "size": 4, - "way": DecodeMethod.I2C, - "format": DecodeFormat.JOIN, - "sep": "/", - }, - "desc": Description.CPLD, - "slot": 0, - }, - { - "name": "CPLD2 (MAC Board B)", - "firmware_version": { - "bus": 2, - "addr": 0x35, - "offset": 0, - "size": 4, - "way": DecodeMethod.I2C, - "format": DecodeFormat.JOIN, - "sep": "/", - }, - "desc": Description.CPLD, - "slot": 0, - }, - { - "name": "CPLD3 (CONNECT Board A)", - "firmware_version": { - "bus": 2, - "addr": 0x37, - "offset": 0, - "size": 4, - "way": DecodeMethod.I2C, - "format": DecodeFormat.JOIN, - "sep": "/", - }, - "desc": Description.CPLD, - "slot": 0, - }, - { - "name": "CPLD4 (CPU Board)", - "firmware_version": { - "bus": 0, - "addr": 0x0D, - "offset": 0, - "size": 4, - "way": DecodeMethod.I2C, - "format": DecodeFormat.JOIN, - "sep": "/", - }, - "desc": Description.CPLD, - "slot": 1, - }, - ], - "thermals": [ - { - "name": "INLET TEMP", - "high": { - "loc": "/sys/bus/i2c/devices/2-0048/hwmon/*/temp1_max", - "format": DecodeFormat.THOUSANDTH, - }, - "low": None, - "crit_low": None, - "crit_high": None, - "temperature": { - "loc": "/sys/bus/i2c/devices/2-0048/hwmon/*/temp1_input", - "format": DecodeFormat.THOUSANDTH, - }, - }, - { - "name": "OUTLET TEMP", - "high": { - "loc": "/sys/bus/i2c/devices/2-0049/hwmon/*/temp1_max", - "format": DecodeFormat.THOUSANDTH, - }, - "low": None, - "crit_low": None, - "crit_high": None, - "temperature": { - "loc": "/sys/bus/i2c/devices/2-0049/hwmon/*/temp1_input", - "format": DecodeFormat.THOUSANDTH, - }, - }, - { - "name": "BOARD TEMP", - "high": { - "loc": "/sys/bus/i2c/devices/2-004a/hwmon/*/temp1_max", - "format": DecodeFormat.THOUSANDTH, - }, - "low": None, - "crit_low": None, - "crit_high": None, - "temperature": { - "loc": "/sys/bus/i2c/devices/2-004a/hwmon/*/temp1_input", - "format": DecodeFormat.THOUSANDTH, - }, - }, - { - "name": "PHYSICAL ID 0", - "high": { - "loc": "/sys/class/hwmon/hwmon0/temp1_max", - "format": DecodeFormat.THOUSANDTH, - }, - "low": None, - "crit_low": None, - "crit_high": { - "loc": "/sys/class/hwmon/hwmon0/temp1_crit", - "format": DecodeFormat.THOUSANDTH, - }, - "temperature": { - "loc": "/sys/class/hwmon/hwmon0/temp1_input", - "format": DecodeFormat.THOUSANDTH, - }, - }, - { - "name": "CPU CORE 0", - "high": { - "loc": "/sys/class/hwmon/hwmon0/temp2_max", - "format": DecodeFormat.THOUSANDTH, - }, - "low": None, - "crit_low": None, - "crit_high": { - "loc": "/sys/class/hwmon/hwmon0/temp2_crit", - "format": DecodeFormat.THOUSANDTH, - }, - "temperature": { - "loc": "/sys/class/hwmon/hwmon0/temp2_input", - "format": DecodeFormat.THOUSANDTH, - }, - }, - { - "name": "CPU CORE 1", - "high": { - "loc": "/sys/class/hwmon/hwmon0/temp3_max", - "format": DecodeFormat.THOUSANDTH, - }, - "low": None, - "crit_low": None, - "crit_high": { - "loc": "/sys/class/hwmon/hwmon0/temp3_crit", - "format": DecodeFormat.THOUSANDTH, - }, - "temperature": { - "loc": "/sys/class/hwmon/hwmon0/temp3_input", - "format": DecodeFormat.THOUSANDTH, - }, - }, - { - "name": "CPU CORE 2", - "high": { - "loc": "/sys/class/hwmon/hwmon0/temp4_max", - "format": DecodeFormat.THOUSANDTH, - }, - "low": None, - "crit_low": None, - "crit_high": { - "loc": "/sys/class/hwmon/hwmon0/temp4_crit", - "format": DecodeFormat.THOUSANDTH, - }, - "temperature": { - "loc": "/sys/class/hwmon/hwmon0/temp4_input", - "format": DecodeFormat.THOUSANDTH, - }, - }, - { - "name": "CPU CORE 3", - "high": { - "loc": "/sys/class/hwmon/hwmon0/temp5_max", - "format": DecodeFormat.THOUSANDTH, - }, - "low": None, - "crit_low": None, - "crit_high": { - "loc": "/sys/class/hwmon/hwmon0/temp5_crit", - "format": DecodeFormat.THOUSANDTH, - }, - "temperature": { - "loc": "/sys/class/hwmon/hwmon0/temp5_input", - "format": DecodeFormat.THOUSANDTH, - }, - }, - ], - "fans": [ - { - "name": "fan1", - "e2loc": {"bus": 3, "addr": 0x53, "way": "i2c", "size": "256"}, - "present": { - "loc": "/sys/bus/i2c/devices/2-0037/fan_present", - "format": DecodeFormat.ONE_BIT_HEX, - "bit": 0, - }, - "status": { - "loc": "/sys/bus/i2c/devices/2-0037/fan_status", - "format": DecodeFormat.ONE_BIT_HEX, - "bit": 0, - }, - "hw_version": {"loc": "/sys/bus/i2c/devices/3-0053/fan_hw_version"}, - "sn": {"loc": "/sys/bus/i2c/devices/3-0053/fan_sn"}, - "led": { - "loc": "/sys/bus/i2c/devices/0-0032/fan0_led", - "format": DecodeFormat.AND, - "mask": 0b1011, - }, - "led_colors": FAN_LED_COLORS, - "rotors": [ - { - "speed_getter": { - "loc": "/sys/bus/i2c/devices/2-0037/hwmon/*/fan1_input" - }, - "speed_setter": { - "loc": "/sys/bus/i2c/devices/0-0032/fan_speed_set" - }, - "speed_max": Threshold.FAN_SPEED_MAX, - } - ], - }, - { - "name": "fan2", - "e2loc": {"bus": 4, "addr": 0x53, "way": "i2c", "size": "256"}, - "present": { - "loc": "/sys/bus/i2c/devices/2-0037/fan_present", - "format": DecodeFormat.ONE_BIT_HEX, - "bit": 1, - }, - "status": { - "loc": "/sys/bus/i2c/devices/2-0037/fan_status", - "format": DecodeFormat.ONE_BIT_HEX, - "bit": 1, - }, - "hw_version": {"loc": "/sys/bus/i2c/devices/4-0053/fan_hw_version"}, - "sn": {"loc": "/sys/bus/i2c/devices/4-0053/fan_sn"}, - "led": { - "loc": "/sys/bus/i2c/devices/0-0032/fan1_led", - "format": DecodeFormat.AND, - "mask": 0b1011, - }, - "led_colors": FAN_LED_COLORS, - "rotors": [ - { - "speed_getter": { - "loc": "/sys/bus/i2c/devices/2-0037/hwmon/*/fan2_input" - }, - "speed_setter": { - "loc": "/sys/bus/i2c/devices/0-0032/fan_speed_set" - }, - "speed_max": Threshold.FAN_SPEED_MAX, - } - ], - }, - { - "name": "fan3", - "e2loc": {"bus": 3, "addr": 0x53, "way": "i2c", "size": "256"}, - "present": { - "loc": "/sys/bus/i2c/devices/2-0037/fan_present", - "format": DecodeFormat.ONE_BIT_HEX, - "bit": 2, - }, - "status": { - "loc": "/sys/bus/i2c/devices/2-0037/fan_status", - "format": DecodeFormat.ONE_BIT_HEX, - "bit": 2, - }, - "hw_version": {"loc": "/sys/bus/i2c/devices/5-0053/fan_hw_version"}, - "sn": {"loc": "/sys/bus/i2c/devices/5-0053/fan_sn"}, - "led": { - "loc": "/sys/bus/i2c/devices/0-0032/fan2_led", - "format": DecodeFormat.AND, - "mask": 0b1011, - }, - "led_colors": FAN_LED_COLORS, - "rotors": [ - { - "speed_getter": { - "loc": "/sys/bus/i2c/devices/2-0037/hwmon/*/fan3_input" - }, - "speed_setter": { - "loc": "/sys/bus/i2c/devices/0-0032/fan_speed_set" - }, - "speed_max": Threshold.FAN_SPEED_MAX, - } - ], - }, - { - "name": "fan4", - "e2loc": {"bus": 3, "addr": 0x53, "way": "i2c", "size": "256"}, - "present": { - "loc": "/sys/bus/i2c/devices/2-0037/fan_present", - "format": DecodeFormat.ONE_BIT_HEX, - "bit": 3, - }, - "status": { - "loc": "/sys/bus/i2c/devices/2-0037/fan_status", - "format": DecodeFormat.ONE_BIT_HEX, - "bit": 3, - }, - "hw_version": {"loc": "/sys/bus/i2c/devices/6-0053/fan_hw_version"}, - "sn": {"loc": "/sys/bus/i2c/devices/6-0053/fan_sn"}, - "led": { - "loc": "/sys/bus/i2c/devices/0-0032/fan3_led", - "format": DecodeFormat.AND, - "mask": 0b1011, - }, - "led_colors": FAN_LED_COLORS, - "rotors": [ - { - "speed_getter": { - "loc": "/sys/bus/i2c/devices/2-0037/hwmon/*/fan4_input" - }, - "speed_setter": { - "loc": "/sys/bus/i2c/devices/0-0032/fan_speed_set" - }, - "speed_max": Threshold.FAN_SPEED_MAX, - } - ], - }, - ], - "psus": [ - { - "name": "psu1", - "present": { - "loc": "/sys/bus/i2c/devices/2-0037/psu_status", - "format": DecodeFormat.ONE_BIT_HEX, - "bit": 0, - }, - "status": { - "loc": "/sys/bus/i2c/devices/2-0037/psu_status", - "format": DecodeFormat.ONE_BIT_HEX, - "bit": 1, - }, - "sn": {"loc": "/sys/bus/i2c/devices/7-0050/psu_sn"}, - "in_current": { - "loc": "/sys/bus/i2c/devices/7-0058/hwmon/*/curr1_input", - "format": DecodeFormat.THOUSANDTH, - }, - "in_voltage": { - "loc": "/sys/bus/i2c/devices/7-0058/hwmon/*/in1_input", - "format": DecodeFormat.THOUSANDTH, - }, - "out_voltage": { - "loc": "/sys/bus/i2c/devices/7-0058/hwmon/*/in2_input", - "format": DecodeFormat.THOUSANDTH, - }, - "out_current": { - "loc": "/sys/bus/i2c/devices/7-0058/hwmon/*/curr2_input", - "format": DecodeFormat.THOUSANDTH, - }, - "temperature": { - "loc": "/sys/bus/i2c/devices/7-0058/hwmon/*/temp1_input", - "format": DecodeFormat.THOUSANDTH, - }, - "hw_version": {"loc": "/sys/bus/i2c/devices/7-0050/psu_hw"}, - "psu_type": {"loc": "/sys/bus/i2c/devices/7-0050/psu_type"}, - "fans": [ - { - "name": "psu_fan1", - "present": { - "loc": "/sys/bus/i2c/devices/7-0058/hwmon/*/fan1_fault", - }, - "status": { - "loc": "/sys/bus/i2c/devices/2-0037/psu_status", - "format": DecodeFormat.ONE_BIT_HEX, - "bit": 1, - }, - "rotors": [ - { - "speed_getter": { - "loc": "/sys/bus/i2c/devices/7-0058/hwmon/*/fan1_input" - }, - "speed_max": Threshold.PSU_FAN_SPEED_MAX, - } - ], - } - ], - "in_power": { - "loc": "/sys/bus/i2c/devices/7-0058/hwmon/*/power1_input", - "format": DecodeFormat.MILLIONTH, - }, - "out_power": { - "loc": "/sys/bus/i2c/devices/7-0058/hwmon/*/power2_input", - "format": DecodeFormat.MILLIONTH, - }, - }, - { - "name": "psu2", - "present": { - "loc": "/sys/bus/i2c/devices/2-0037/psu_status", - "format": DecodeFormat.ONE_BIT_HEX, - "bit": 4, - }, - "status": { - "loc": "/sys/bus/i2c/devices/2-0037/psu_status", - "format": DecodeFormat.ONE_BIT_HEX, - "bit": 5, - }, - "sn": {"loc": "/sys/bus/i2c/devices/8-0053/psu_sn"}, - "in_current": { - "loc": "/sys/bus/i2c/devices/8-005b/hwmon/*/curr1_input", - "format": DecodeFormat.THOUSANDTH, - }, - "in_voltage": { - "loc": "/sys/bus/i2c/devices/8-005b/hwmon/*/in1_input", - "format": DecodeFormat.THOUSANDTH, - }, - "out_voltage": { - "loc": "/sys/bus/i2c/devices/8-005b/hwmon/*/in2_input", - "format": DecodeFormat.THOUSANDTH, - }, - "out_current": { - "loc": "/sys/bus/i2c/devices/8-005b/hwmon/*/curr2_input", - "format": DecodeFormat.THOUSANDTH, - }, - "temperature": { - "loc": "/sys/bus/i2c/devices/8-005b/hwmon/*/temp1_input", - "format": DecodeFormat.THOUSANDTH, - }, - "hw_version": {"loc": "/sys/bus/i2c/devices/8-0053/psu_hw"}, - "psu_type": {"loc": "/sys/bus/i2c/devices/8-0053/psu_type"}, - "fans": [ - { - "name": "psu_fan1", - "present": { - "loc": "/sys/bus/i2c/devices/8-005b/hwmon/*/fan1_fault", - }, - "status": { - "loc": "/sys/bus/i2c/devices/2-0037/psu_status", - "format": DecodeFormat.ONE_BIT_HEX, - "bit": 5, - }, - "rotors": [ - { - "speed_getter": { - "loc": "/sys/bus/i2c/devices/8-005b/hwmon/*/fan1_input" - }, - "speed_max": Threshold.PSU_FAN_SPEED_MAX, - } - ], - } - ], - "in_power": { - "loc": "/sys/bus/i2c/devices/8-005b/hwmon/*/power1_input", - "format": DecodeFormat.MILLIONTH, - }, - "out_power": { - "loc": "/sys/bus/i2c/devices/8-005b/hwmon/*/power2_input", - "format": DecodeFormat.MILLIONTH, - }, - }, - ], -} diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/fan.py b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/fan.py deleted file mode 100644 index 47b5a9629c46..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/fan.py +++ /dev/null @@ -1,36 +0,0 @@ -try: - from sonic_platform_pddf_base.pddf_fan import PddfFan -except ImportError as e: - raise ImportError(str(e) + "- required module not found") - - -class Fan(PddfFan): - """PDDF Platform-Specific Fan class""" - - def __init__(self, tray_idx, fan_idx=0, pddf_data=None, pddf_plugin_data=None, is_psu_fan=False, psu_index=0): - # idx is 0-based - PddfFan.__init__(self, tray_idx, fan_idx, pddf_data, pddf_plugin_data, is_psu_fan, psu_index) - - # Provide the functions/variables below for which implementation is to be overwritten - # Since psu_fan airflow direction cant be read from sysfs, it is fixed as 'F2B' or 'intake' - def get_direction(self): - """ - Retrieves the direction of fan - - Returns: - A string, either FAN_DIRECTION_INTAKE or FAN_DIRECTION_EXHAUST - depending on fan direction - """ - return self.FAN_DIRECTION_EXHAUST - - def get_speed_rpm(self): - if self.is_psu_fan: - return super().get_speed_rpm() - else: - divisor = 15000000 - mask_low = 0xff - ret = super().get_speed_rpm() - # revert ret - ret = (ret >> 8) + ((ret & mask_low) << 8) - return int(divisor/ret) - diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/hwaccess.py b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/hwaccess.py deleted file mode 100755 index c604d9c61164..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/hwaccess.py +++ /dev/null @@ -1,47 +0,0 @@ -# Helper functions to access hardware - -import os -import struct -import mmap -import subprocess - -# Read PCI device - -def pci_mem_read(mm, offset): - mm.seek(offset) - read_data_stream = mm.read(4) - return struct.unpack('I',read_data_stream)[0] - -def pci_get_value(resource, offset): - with open(resource, 'r+b') as fd: - mm = mmap.mmap(fd.fileno(), 0) - val = pci_mem_read(mm, offset) - mm.close() - return val - -def pci_mem_write(memmap, offset, data): - """ Write PCI device """ - memmap.seek(offset) - memmap.write(struct.pack('I', data)) - -def pci_set_value(resource, val, offset): - """ Set a value to PCI device """ - with open(resource, 'w+b') as filed: - memmap = None - try: - memmap = mmap.mmap(filed.fileno(), 0) - pci_mem_write(memmap, offset, val) - except EnvironmentError: - pass - if memmap is not None: - memmap.close() - -# Read I2C device - -def i2c_get(bus, i2caddr, ofs): - try: - valx = int(subprocess.check_output(['/usr/sbin/i2cget','-f', '-y', str(bus), str(i2caddr), str(ofs)]), 16) - return "{:02x}".format(valx) - except (FileNotFoundError, subprocess.CalledProcessError): - return -1 - diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/logger.py b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/logger.py deleted file mode 100644 index 5969781bf9a9..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/logger.py +++ /dev/null @@ -1,19 +0,0 @@ -# -*- coding: utf-8 -*- - -import logging - - -def _init_logger(): - formatter = logging.Formatter( - "%(asctime)s %(levelname)s %(filename)s[%(funcName)s][%(lineno)s]: %(message)s" - ) - handler = logging.FileHandler("/var/log/syslog") - handler.setFormatter(formatter) - - logger = logging.getLogger(__name__) - logger.setLevel(logging.DEBUG) - logger.addHandler(handler) - return logger - - -logger = _init_logger() diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/pcie.py b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/pcie.py deleted file mode 100644 index 5a66997d33d0..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/pcie.py +++ /dev/null @@ -1,43 +0,0 @@ -# -# pcie_base.py -# -# Abstract base class for implementing platform-specific -# PCIE functionality for SONiC -# - -try: - import abc - from sonic_pcie import PcieUtil -except ImportError as e: - raise ImportError (str(e) + " - required module not found") - -class PcieBase(object): - def __init__(self, path): - """ - Constructor - Args: - pcieutil file and config file path - """ - self.pcie_util = PcieUtil(path) - - - @abc.abstractmethod - def get_pcie_device(self): - """ - get current device pcie info - - Returns: - A list including pcie device info - """ - return self.pcie_util.get_pcie_device() - - - @abc.abstractmethod - def get_pcie_check(self): - """ - Check Pcie device with config file - Returns: - A list including pcie device and test result info - """ - return self.pcie_util.get_pcie_check() - diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/psu.py b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/psu.py deleted file mode 100644 index 71eacf763ff1..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/psu.py +++ /dev/null @@ -1,104 +0,0 @@ -try: - from sonic_platform_pddf_base.pddf_psu import PddfPsu - from sonic_py_common.general import getstatusoutput_noshell - import time -except ImportError as e: - raise ImportError (str(e) + "- required module not found") - - -class Psu(PddfPsu): - """PDDF Platform-Specific PSU class""" - - PLATFORM_PSU_CAPACITY = 1200 - - def __init__(self, index, pddf_data=None, pddf_plugin_data=None): - PddfPsu.__init__(self, index, pddf_data, pddf_plugin_data) - - # Provide the functions/variables below for which implementation is to be overwritten - def get_maximum_supplied_power(self): - """ - Retrieves the maximum supplied power by PSU (or PSU capacity) - Returns: - A float number, the maximum power output in Watts. - e.g. 1200.1 - """ - return float(self.PLATFORM_PSU_CAPACITY) - - def get_type(self): - """ - Gets the type of the PSU - Returns: - A string, the type of PSU (AC/DC) - """ - return "DC" - - def runcmd(self, cmd): - time_retry = 6 - result_msg = "" - time_delay = 0.01 - while time_retry: - try: - val, result_msg = getstatusoutput_noshell(cmd.split(" ")) - if val is False: - time_retry -=1 - time.sleep(time_delay) - continue - else: - return val, result_msg - except Exception as e: - time_retry -= 1 - result_msg = str(e) - time.sleep(time_delay) - - return False, result_msg - - def get_voltage(self): - """ - Retrieves current PSU voltage output - - Returns: - A float number, the output voltage in volts, - e.g. 12.1 - """ - - v_out = 0 - label_t = "psu_v_out" - device = "PSU{}".format(self.psu_index) - #print(device) - pddf_obj_data = self.pddf_obj.data - - if device in pddf_obj_data.keys(): - pmbusloc = pddf_obj_data[device]['i2c']['interface'] - - for val in pmbusloc: - dev_name = val['dev'] - pmbus_loc = pddf_obj_data[dev_name] - i2cloc = pmbus_loc['i2c']['attr_list'] - parentbus = pmbus_loc['i2c']['topo_info'] - - for item_t in i2cloc: - if item_t['attr_name'] == label_t: - parentbus_id = int(parentbus['parent_bus'], 16) - vout_mode_cmd = "i2cget -f -y {} {} 0x20 bp".format(parentbus_id, parentbus['dev_addr']) - ret_t, val_voutmode = self.runcmd(vout_mode_cmd) - if ret_t is False: - return 0.0 - v_out_cmd = "i2cget -f -y {} {} {} wp".format(parentbus_id, parentbus['dev_addr'], item_t['attr_offset']) - ret_t, val_p_out = self.runcmd(v_out_cmd) - if ret_t is False: - return 0.0 - val_voutmode_t = int(val_voutmode, 16) - val_p_out_t = int(val_p_out, 16) * 1000 - - import ctypes - val_voutmode_t_t = ctypes.c_int8(val_voutmode_t << 3).value >>3 - - if (val_voutmode_t_t) < 0: - val_p_out_t_f = val_p_out_t>> (-val_voutmode_t_t) - else: - val_p_out_t_f = val_p_out_t << val_voutmode_t_t - - return float(val_p_out_t_f)/1000 - - return float(v_out)/1000 - diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/regutil.py b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/regutil.py deleted file mode 100644 index bff2bd41ea55..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/regutil.py +++ /dev/null @@ -1,245 +0,0 @@ -# -*- coding: utf-8 -*- -from glob import glob -from plat_hal.osutil import osutil - -try: - from sonic_platform.config import DecodeFormat, DecodeMethod - - DECODE_FORMAT = DecodeFormat - DECODE_METHOD = DecodeMethod -except ImportError: - raise ImportError(str(e) + "- required module not found") - -ERR_CODE = "ERR" - - -class Reg(object): - """ - "e2loc": {"bus": 3, "addr": 0x53, "way": "i2c"} - "value": { - "loc": "/sys/bus/i2c/devices/2-0048/hwmon/hwmon*/temp1_input", - "way": "sysfs", - - "InputsStatus": { - "bus": 8, - "addr": 0x5B, - "offset": 0x79, - "way": "i2cword", - "mask": 0x0200, - }, - """ - - def __new__(cls, *args): - if args[0] is None or not isinstance(args[0], dict): - return None - return super(Reg, cls).__new__(cls) - - def __init__(self, data): - - self.loc = None - self.way = DECODE_METHOD.SYSFS - self.addr = None - self.bus = None - self.offset = None - self.size = 1 - self.bit = None - self.mask = None - self.digit = None - self.sdk_type = None - self.sep = None - self.format = DECODE_FORMAT.TEXT - self.__dict__.update(data) - - def _read_reg_val(self): - ret = None - try: - if self.way == DECODE_METHOD.SYSFS: - ret = self.get_sysfs() - elif self.way == DECODE_METHOD.I2C: - ret = self.get_i2c() - elif self.way == DECODE_METHOD.I2C_WORD: - ret = self.get_i2cword() - elif self.way == DECODE_METHOD.DEVMEM: - ret = self.get_devmem() - elif self.way == DECODE_METHOD.SDK: - # TODO - pass - else: - pass - except Exception as e: - raise e - - return ret - - def _write_reg_val(self, val): - try: - if self.way == DECODE_METHOD.SYSFS: - return self._write_sysfs(val) - except Exception as e: - raise e - - return False - - def _write_sysfs(self, val): - try: - with open(glob(self.loc)[0], "w") as f: - f.write(val) - f.flush() - return True - except Exception as e: - raise e - - def _format_val(self, val): - try: - if isinstance(val, str): - val = val.strip() - if self.format == DECODE_FORMAT.THOUSANDTH: - return float("%.1f" % (float(val) / 1000)) - elif self.format == DECODE_FORMAT.HUNDREDTH: - return float("%.1f" % (float(val) / 100)) - elif self.format == DECODE_FORMAT.ONE_BIT_HEX: - return (int(val, 16) & (1 << self.bit)) >> self.bit - elif self.format == DECODE_FORMAT.DECIMAL: - return int(val, 10) - elif self.format == DECODE_FORMAT.MILLIONTH: - return float("%.1f" % (float(val) / 1000 / 1000)) - elif self.format == DECODE_FORMAT.AND: - return (int(val, 16)) & self.mask - elif isinstance(val, list): - if self.format == DECODE_FORMAT.JOIN: - return self.sep.join(val) - except Exception as e: - raise e - else: - return val - - def decode(self): - """ - get value by config way - way i2c/sysfs/lpc - """ - if self.way is None: - raise ValueError("cannot found way to deal") - - ret = self._read_reg_val() - - ret = self._format_val(ret) - return ret - - def encode(self, val): - if self.way is None: - raise ValueError("cannot found way to deal") - - return self._write_reg_val(val) - - def get_sdk(self): - # TODO - pass - - def get_sysfs(self): - if self.loc is None: - raise ValueError("Not Enough Attr: loc: {}".format(self.loc)) - - ret, val = osutil.readsysfs(self.loc) - - if not ret: - raise IOError(val) - - return val - - def get_devmem(self): - if self.addr is None or self.digit is None or self.mask is None: - raise ValueError( - "Not Enough Attr: addr: {}, digit: {}, mask: {}".format( - self.addr, self.digit, self.mask - ) - ) - - ret, val = osutil.getdevmem(self.addr, self.digit, self.mask) - - if not ret: - raise IOError(val) - - return val - - def get_i2cword(self): - if self.bus is None or self.addr is None or self.offset is None: - raise ValueError( - "Not Enough Attr: bus: {}, addr: {}, offset: {}".format( - self.bus, self.addr, self.offset - ) - ) - - ret, val = osutil.geti2cword(self.bus, self.addr, self.offset) - - if not ret: - raise IOError(val) - - return val - - def get_i2c(self): - if ( - self.bus is None - or self.addr is None - or self.offset is None - or self.size is None - ): - raise ValueError( - "Not Enough Attr: bus: {}, addr: {}, offset: {}".format( - self.bus, self.addr, self.offset - ) - ) - - value = [] - for i in range(self.size): - ofs = self.offset + i - ret, val = osutil.rji2cget(self.bus, self.addr, ofs) - - if not ret: - raise IOError(val) - else: - value.append(repr(chr(val)).translate(None, r"\\x").replace("'", "")) - - return value - - def set_i2cword(self, bus, addr, offset, byte): - return self.seti2cword(bus, addr, offset, byte) - - def seti2cword(self, bus, addr, offset, byte): - return osutil.seti2cword(bus, addr, offset, byte) - - def set_i2c(self, bus, addr, offset, byte): - return self.seti2c(bus, addr, offset, byte) - - def seti2c(self, bus, addr, offset, byte): - ret, val = osutil.rji2cset(bus, addr, offset, byte) - return ret, val - - def getbcmtemp(self): - try: - sta, ret = osutil.getmactemp() - if sta == True: - mac_aver = float(ret.get("average", self.__error_ret)) - #mac_max = float(ret.get("maximum", self.__error_ret)) - mac_aver = mac_aver * 1000 - #mac_max = mac_max * 1000 - else: - return False, ret - except AttributeError as e: - return False, str(e) - return True, mac_aver - - def getbcmreg(self, reg): - ret, val = osutil.getsdkreg(reg) - return ret, val - - def logger_debug(self, msg): - baseutil.logger_debug(msg) - - def command(self, cmd): - ret, output = osutil.command(cmd) - return ret, output - - def set_val(self, val): - # TODO - pass diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/rotor.py b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/rotor.py deleted file mode 100644 index 3e5bcc5b9b9a..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/rotor.py +++ /dev/null @@ -1,41 +0,0 @@ -# -*- coding: utf-8 -*- - -try: - from sonic_platform.regutil import Reg - from sonic_platform.logger import logger -except ImportError: - raise ImportError(str(e) + "- required module not found") - -class Rotor: - def __init__(self, config): - if config is not None and isinstance(config, dict): - self.__reg_speed_getter = Reg(config.get("speed_getter")) - self.__reg_speed_setter = Reg(config.get("speed_setter")) - self.__speed_max = config.get("speed_max") - else: - raise ValueError("init rotor Error: {}".format(config)) - - def get_speed(self): - try: - return int(self.__reg_speed_getter.decode()) - except Exception as e: - logger.error(str(e)) - - return 0 - - def set_speed(self, speed): - try: - return self.__reg_speed_setter.encode(speed) - except Exception as e: - logger.error(str(e)) - - return False - - def get_speed_percentage(self): - try: - speed = self.get_speed() - return (100 * speed) / self.__speed_max - except Exception as e: - logger.error(str(e)) - - return 0 diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/sfp_config.py b/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/sfp_config.py deleted file mode 100644 index d468912fdda3..000000000000 --- a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/sfp_config.py +++ /dev/null @@ -1,23 +0,0 @@ -cust_sfp_cfg = { - 'x86_64-ragile_ra-b6510-48v8c-r0': { - "ver": '2.1', - "port_index_start": 0, - "port_num": 56, - "log_level": 2, - "eeprom_retry_times": 5, - "eeprom_retry_break_sec": 0.2, - "presence_path": "/sys/bus/i2c/devices/%d-0053/xcvr_present", - "presence_path_key": list(range(11, 67)), - "presence_val_is_present": 1, - "eeprom_path": "/sys/bus/i2c/devices/%d-0050/eeprom", - "eeprom_path_key": list(range(11, 67)), - "optoe_driver_path": "/sys/bus/i2c/devices/%d-0050/dev_class", - "optoe_driver_key": list(range(11, 67)), - "txdisable_path": "/sys/bus/i2c/devices/%d-0053/xcvr_txdisable", - "txdisable_path_key": list(range(11, 59)) + [0] * 8, - "txdisable_val_is_on": 0, - "reset_path": "/sys/bus/i2c/devices/%d-0053/xcvr_reset", - "reset_path_key": [0]* 48 + list(range(59, 67)), - "reset_val_is_on": 0, - }, -} diff --git a/platform/broadcom/sonic-platform-modules-ufispace/debian/changelog b/platform/broadcom/sonic-platform-modules-ufispace/debian/changelog index a4e712e2a1aa..029c0374df67 100644 --- a/platform/broadcom/sonic-platform-modules-ufispace/debian/changelog +++ b/platform/broadcom/sonic-platform-modules-ufispace/debian/changelog @@ -1,3 +1,27 @@ +sonic-ufispace-platform-modules (1.0.0) unstable; urgency=low + + * Add support for S6301-56ST + + -- Ufispace Thu, 27 Jul 2023 15:50:23 +0800 + +sonic-ufispace-platform-modules (1.0.0) unstable; urgency=low + + * Add support for S7801-54XS + + -- Ufispace Thu, 27 Jul 2023 11:49:07 +0800 + +sonic-ufispace-platform-modules (1.0.0) unstable; urgency=low + + * Add support for S8901-54XC + + -- Ufispace Thu, 27 Jul 2023 11:12:21 +0800 + +sonic-ufispace-platform-modules (1.0.0) unstable; urgency=low + + * Add support for S9110-32X. + + -- Ufispace Wed, 26 Jul 2023 18:03:14 +0800 + sonic-ufispace-platform-modules (1.0.0) unstable; urgency=low * Add support for S9300-32D. diff --git a/platform/broadcom/sonic-platform-modules-ufispace/debian/control b/platform/broadcom/sonic-platform-modules-ufispace/debian/control index afee144752e2..798179f6e394 100644 --- a/platform/broadcom/sonic-platform-modules-ufispace/debian/control +++ b/platform/broadcom/sonic-platform-modules-ufispace/debian/control @@ -1,7 +1,7 @@ Source: sonic-ufispace-platform-modules Section: main Priority: extra -Maintainer: Leo Lin +Maintainer: Leo Lin , Nonodark Huang , Jason Tsai Build-Depends: debhelper (>= 9), bzip2 Standards-Version: 1.0.0 @@ -9,3 +9,18 @@ Package: sonic-platform-ufispace-s9300-32d Architecture: amd64 Description: This package contains s9300-32d platform driver utility for SONiC project. +Package: sonic-platform-ufispace-s9110-32x +Architecture: amd64 +Description: This package contains s9110-32x platform driver utility for SONiC project. + +Package: sonic-platform-ufispace-s8901-54xc +Architecture: amd64 +Description: This package contains s8901-54xc platform driver utility for SONiC project. + +Package: sonic-platform-ufispace-s7801-54xs +Architecture: amd64 +Description: This package contains s7801-54xs platform driver utility for SONiC project. + +Package: sonic-platform-ufispace-s6301-56st +Architecture: amd64 +Description: This package contains s6301-56st platform driver utility for SONiC project. \ No newline at end of file diff --git a/platform/broadcom/sonic-platform-modules-ufispace/debian/rules b/platform/broadcom/sonic-platform-modules-ufispace/debian/rules index 78a77f9b5b69..d36b48dbc53c 100755 --- a/platform/broadcom/sonic-platform-modules-ufispace/debian/rules +++ b/platform/broadcom/sonic-platform-modules-ufispace/debian/rules @@ -20,6 +20,10 @@ KVERSION ?= $(shell uname -r) KERNEL_SRC := /lib/modules/$(KVERSION) MOD_SRC_DIR:= $(shell pwd) MODULE_DIRS:= s9300-32d +MODULE_DIRS += s9110-32x +MODULE_DIRS += s8901-54xc +MODULE_DIRS += s7801-54xs +MODULE_DIRS += s6301-56st MODULE_DIR := modules UTILS_DIR := utils SERVICE_DIR := service diff --git a/platform/broadcom/sonic-platform-modules-ufispace/debian/sonic-platform-ufispace-s6301-56st.install b/platform/broadcom/sonic-platform-modules-ufispace/debian/sonic-platform-ufispace-s6301-56st.install new file mode 100644 index 000000000000..869c48e4a1ea --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/debian/sonic-platform-ufispace-s6301-56st.install @@ -0,0 +1 @@ +s6301-56st/sonic_platform-1.0-py3-none-any.whl usr/share/sonic/device/x86_64-ufispace_s6301_56st-r0/pddf diff --git a/platform/broadcom/sonic-platform-modules-ufispace/debian/sonic-platform-ufispace-s6301-56st.postinst b/platform/broadcom/sonic-platform-modules-ufispace/debian/sonic-platform-ufispace-s6301-56st.postinst new file mode 100644 index 000000000000..01666039ca26 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/debian/sonic-platform-ufispace-s6301-56st.postinst @@ -0,0 +1,3 @@ +depmod -a +systemctl enable pddf-platform-init.service +systemctl start pddf-platform-init.service diff --git a/platform/broadcom/sonic-platform-modules-ufispace/debian/sonic-platform-ufispace-s6301-56st.prerm b/platform/broadcom/sonic-platform-modules-ufispace/debian/sonic-platform-ufispace-s6301-56st.prerm new file mode 100644 index 000000000000..f9fe8c017ab0 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/debian/sonic-platform-ufispace-s6301-56st.prerm @@ -0,0 +1,2 @@ +systemctl stop pddf-platform-init.service +systemctl disable pddf-platform-init.service diff --git a/platform/broadcom/sonic-platform-modules-ufispace/debian/sonic-platform-ufispace-s7801-54xs.install b/platform/broadcom/sonic-platform-modules-ufispace/debian/sonic-platform-ufispace-s7801-54xs.install new file mode 100644 index 000000000000..3c1b791bbf56 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/debian/sonic-platform-ufispace-s7801-54xs.install @@ -0,0 +1 @@ +s7801-54xs/sonic_platform-1.0-py3-none-any.whl usr/share/sonic/device/x86_64-ufispace_s7801_54xs-r0/pddf diff --git a/platform/broadcom/sonic-platform-modules-ufispace/debian/sonic-platform-ufispace-s7801-54xs.postinst b/platform/broadcom/sonic-platform-modules-ufispace/debian/sonic-platform-ufispace-s7801-54xs.postinst new file mode 100644 index 000000000000..01666039ca26 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/debian/sonic-platform-ufispace-s7801-54xs.postinst @@ -0,0 +1,3 @@ +depmod -a +systemctl enable pddf-platform-init.service +systemctl start pddf-platform-init.service diff --git a/platform/broadcom/sonic-platform-modules-ufispace/debian/sonic-platform-ufispace-s7801-54xs.prerm b/platform/broadcom/sonic-platform-modules-ufispace/debian/sonic-platform-ufispace-s7801-54xs.prerm new file mode 100644 index 000000000000..4b887ab38a28 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/debian/sonic-platform-ufispace-s7801-54xs.prerm @@ -0,0 +1,2 @@ +systemctl stop pddf-platform-init.service +systemctl disable pddf-platform-init.service \ No newline at end of file diff --git a/platform/broadcom/sonic-platform-modules-ufispace/debian/sonic-platform-ufispace-s8901-54xc.install b/platform/broadcom/sonic-platform-modules-ufispace/debian/sonic-platform-ufispace-s8901-54xc.install new file mode 100644 index 000000000000..685e023830d3 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/debian/sonic-platform-ufispace-s8901-54xc.install @@ -0,0 +1 @@ +s8901-54xc/sonic_platform-1.0-py3-none-any.whl usr/share/sonic/device/x86_64-ufispace_s8901_54xc-r0/pddf diff --git a/platform/broadcom/sonic-platform-modules-ufispace/debian/sonic-platform-ufispace-s8901-54xc.postinst b/platform/broadcom/sonic-platform-modules-ufispace/debian/sonic-platform-ufispace-s8901-54xc.postinst new file mode 100644 index 000000000000..01666039ca26 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/debian/sonic-platform-ufispace-s8901-54xc.postinst @@ -0,0 +1,3 @@ +depmod -a +systemctl enable pddf-platform-init.service +systemctl start pddf-platform-init.service diff --git a/platform/broadcom/sonic-platform-modules-ufispace/debian/sonic-platform-ufispace-s8901-54xc.prerm b/platform/broadcom/sonic-platform-modules-ufispace/debian/sonic-platform-ufispace-s8901-54xc.prerm new file mode 100644 index 000000000000..4b887ab38a28 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/debian/sonic-platform-ufispace-s8901-54xc.prerm @@ -0,0 +1,2 @@ +systemctl stop pddf-platform-init.service +systemctl disable pddf-platform-init.service \ No newline at end of file diff --git a/platform/broadcom/sonic-platform-modules-ufispace/debian/sonic-platform-ufispace-s9110-32x.install b/platform/broadcom/sonic-platform-modules-ufispace/debian/sonic-platform-ufispace-s9110-32x.install new file mode 100644 index 000000000000..6982e6b1965d --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/debian/sonic-platform-ufispace-s9110-32x.install @@ -0,0 +1 @@ +s9110-32x/sonic_platform-1.0-py3-none-any.whl usr/share/sonic/device/x86_64-ufispace_s9110_32x-r0/pddf diff --git a/platform/broadcom/sonic-platform-modules-ufispace/debian/sonic-platform-ufispace-s9110-32x.postinst b/platform/broadcom/sonic-platform-modules-ufispace/debian/sonic-platform-ufispace-s9110-32x.postinst new file mode 100644 index 000000000000..01666039ca26 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/debian/sonic-platform-ufispace-s9110-32x.postinst @@ -0,0 +1,3 @@ +depmod -a +systemctl enable pddf-platform-init.service +systemctl start pddf-platform-init.service diff --git a/platform/broadcom/sonic-platform-modules-ufispace/debian/sonic-platform-ufispace-s9110-32x.prerm b/platform/broadcom/sonic-platform-modules-ufispace/debian/sonic-platform-ufispace-s9110-32x.prerm new file mode 100644 index 000000000000..4b887ab38a28 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/debian/sonic-platform-ufispace-s9110-32x.prerm @@ -0,0 +1,2 @@ +systemctl stop pddf-platform-init.service +systemctl disable pddf-platform-init.service \ No newline at end of file diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/modules/Makefile b/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/modules/Makefile new file mode 100644 index 000000000000..7c2273d0063b --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/modules/Makefile @@ -0,0 +1,6 @@ + +MODULE_NAME = x86-64-ufispace-s6301-56st-sys-eeprom.o x86-64-ufispace-s6301-56st-lpc.o +obj-m := $(MODULE_NAME) + +CFLAGS_pddf_custom_sysstatus_module.o := -I$(M)/../../../../pddf/i2c/modules/include +KBUILD_EXTRA_SYMBOLS := $(M)/../../../../pddf/i2c/Module.symvers.PDDF diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/modules/x86-64-ufispace-s6301-56st-lpc.c b/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/modules/x86-64-ufispace-s6301-56st-lpc.c new file mode 100644 index 000000000000..9b42c8f2b88f --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/modules/x86-64-ufispace-s6301-56st-lpc.c @@ -0,0 +1,829 @@ +/* + * A lpc driver for the ufispace_s6301_56st + * + * Copyright (C) 2017-2020 UfiSpace Technology Corporation. + * Jason Tsai + * Leo Lin + * + * Based on ad7414.c + * Copyright 2006 Stefan Roese , DENX Software Engineering + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include + +#define BSP_LOG_R(fmt, args...) \ + _bsp_log (LOG_READ, KERN_INFO "%s:%s[%d]: " fmt "\r\n", \ + __FILE__, __func__, __LINE__, ##args) +#define BSP_LOG_W(fmt, args...) \ + _bsp_log (LOG_WRITE, KERN_INFO "%s:%s[%d]: " fmt "\r\n", \ + __FILE__, __func__, __LINE__, ##args) + +#define BSP_PR(level, fmt, args...) _bsp_log (LOG_SYS, level "[BSP]" fmt "\r\n", ##args) +#define DRIVER_NAME "x86_64_ufispace_s6301_56st_lpc" + +/* LPC registers */ + +#define REG_BASE_CPU 0x600 +#define REG_BASE_MB 0x700 + +//MB CPLD +#define REG_MB_BRD_ID_0 (REG_BASE_MB + 0x00) +#define REG_MB_BRD_ID_1 (REG_BASE_MB + 0x01) +#define REG_MB_CPLD_VERSION (REG_BASE_MB + 0x02) +#define REG_MB_CPLD_BUILD (REG_BASE_MB + 0x04) +#define REG_MB_EXTEND_ID (REG_BASE_MB + 0x06) +#define REG_MB_MUX_RESET (REG_BASE_MB + 0x43) +#define REG_MB_FAN_STATUS (REG_BASE_MB + 0x55) +#define REG_MB_PSU_STATUS (REG_BASE_MB + 0x59) +#define REG_MB_PORT_LED_CLR (REG_BASE_MB + 0x80) +#define REG_MB_SYS_LED_CTRL_1 (REG_BASE_MB + 0x81) +#define REG_MB_SYS_LED_STATUS_1 (REG_BASE_MB + 0x82) +#define REG_MB_SYS_LED_STATUS_2 (REG_BASE_MB + 0x83) +#define REG_MB_SYS_LED_STATUS_3 (REG_BASE_MB + 0x84) + +#define MASK_ALL (0xFF) + +#define MDELAY_LPC (5) +#define MDELAY_RESET_INTERVAL (100) +#define MDELAY_RESET_FINISH (500) + +#define MULTIBIT_SET(addr, mask, value) (((addr)&((0xff)^(mask)))|((value)&(mask))) + + +/* LPC sysfs attributes index */ +enum lpc_sysfs_attributes { + //MB CPLD + ATT_MB_BRD_ID_0, + ATT_MB_BRD_ID_1, + ATT_MB_CPLD_1_VERSION, + ATT_MB_CPLD_1_VERSION_H, + ATT_MB_BRD_SKU_ID, + ATT_MB_BRD_HW_ID, + ATT_MB_BRD_ID_TYPE, + ATT_MB_BRD_BUILD_ID, + ATT_MB_BRD_DEPH_ID, + ATT_MB_BRD_EXT_ID, + ATT_MB_MUX_RESET, + ATT_MB_FAN_STATUS, + ATT_MB_PSU_STATUS, + ATT_MB_PORT_LED_CLR, + ATT_MB_LED_SYS, + ATT_MB_LED_ID, + ATT_MB_LED_POE, + ATT_MB_LED_SPD, + ATT_MB_LED_FAN, + ATT_MB_LED_LNK, + ATT_MB_LED_PWR0, + ATT_MB_LED_PWR1, + //BSP + ATT_BSP_VERSION, + ATT_BSP_DEBUG, + ATT_BSP_PR_INFO, + ATT_BSP_PR_ERR, + ATT_BSP_REG, + ATT_BSP_REG_VALUE, + ATT_BSP_GPIO_MAX, + ATT_MAX +}; + +enum bases { + BASE_DEC, + BASE_HEX, + BASE_NONE + +}; + +enum bsp_log_types { + LOG_NONE, + LOG_RW, + LOG_READ, + LOG_WRITE, + LOG_SYS +}; + +enum bsp_log_ctrl { + LOG_DISABLE, + LOG_ENABLE +}; + +struct lpc_data_s { + struct mutex access_lock; +}; + +struct lpc_data_s *lpc_data; +char bsp_version[16]; +char bsp_debug[32]; +char bsp_reg[8]="0x0"; +u8 enable_log_read=LOG_DISABLE; +u8 enable_log_write=LOG_DISABLE; +u8 enable_log_sys=LOG_ENABLE; + +/* mask len and shift */ +static void _get_len_shift(u8 mask, u8 *len, u8 *shift) +{ + int i; + bool found=false; + *len=0; + *shift=0; + + for(i=0; i<8; ++i) { + if(mask & 1) { + *len = *len + 1; + if(!found) { + *shift = i; + found = true; + } + } + mask >>= 1; + } +} + +/* reg mask and shift */ +static u8 _mask_shift(u8 val, u8 mask) +{ + u8 shift=0; + u8 len; + + _get_len_shift(mask, &len, &shift); + + return (val & mask) >> shift; +} + +static u8 _bit_operation(u8 reg_val, u8 bit, u8 bit_val) +{ + if(bit_val == 0) + reg_val = reg_val & ~(1 << bit); + else + reg_val = reg_val | (1 << bit); + return reg_val; +} + +static int _bsp_log(u8 log_type, char *fmt, ...) +{ + if((log_type==LOG_READ && enable_log_read) || + (log_type==LOG_WRITE && enable_log_write) || + (log_type==LOG_SYS && enable_log_sys) ) { + va_list args; + int r; + + va_start(args, fmt); + r = vprintk(fmt, args); + va_end(args); + + return r; + } else { + return 0; + } +} + +static int _config_bsp_log(u8 log_type) +{ + switch(log_type) { + case LOG_NONE: + enable_log_read = LOG_DISABLE; + enable_log_write = LOG_DISABLE; + break; + case LOG_RW: + enable_log_read = LOG_ENABLE; + enable_log_write = LOG_ENABLE; + break; + case LOG_READ: + enable_log_read = LOG_ENABLE; + enable_log_write = LOG_DISABLE; + break; + case LOG_WRITE: + enable_log_read = LOG_DISABLE; + enable_log_write = LOG_ENABLE; + break; + default: + return -EINVAL; + } + return 0; +} + +/* get lpc register value */ +static u8 _read_lpc_reg(u16 reg, u8 mask) +{ + u8 reg_val=0x0, reg_mk_shf_val=0x0; + + mutex_lock(&lpc_data->access_lock); + reg_val = inb(reg); + mutex_unlock(&lpc_data->access_lock); + + reg_mk_shf_val = _mask_shift(reg_val, mask); + + BSP_LOG_R("reg=0x%03x, reg_val=0x%02x, mask=0x%02x, reg_mk_shf_val=0x%02x", reg, reg_val, mask, reg_mk_shf_val); + + return reg_mk_shf_val; +} + +/* get lpc register value */ +static ssize_t read_lpc_reg(u16 reg, u8 mask, u8 base, char *buf) +{ + u8 reg_val; + int len=0; + + reg_val = _read_lpc_reg(reg, mask); + if(base == BASE_HEX) { + len=sprintf(buf, "0x%02x\n", reg_val); + } else { + len=sprintf(buf,"%d\n", reg_val); + } + + return len; +} + +/* set lpc register value */ +static ssize_t write_lpc_reg(u16 reg, u8 mask, const char *buf, size_t count) +{ + u8 reg_val, reg_val_now, shift, mask_len; + + if(kstrtou8(buf, 0, ®_val) < 0) + return -EINVAL; + + _get_len_shift(mask, &mask_len, &shift); + + // set signal bit + if(mask_len == 1) { + reg_val_now = _read_lpc_reg(reg, MASK_ALL); + reg_val = _bit_operation(reg_val_now, shift, reg_val); + // set multi bit + } else if (mask_len > 1) { + reg_val_now = _read_lpc_reg(reg, MASK_ALL); + reg_val = MULTIBIT_SET(reg_val_now, mask, reg_val<access_lock); + + outb(reg_val, reg); + mdelay(MDELAY_LPC); + + mutex_unlock(&lpc_data->access_lock); + + BSP_LOG_W("reg=0x%03x, reg_val=0x%02x, mask=0x%02x", reg, reg_val, mask); + + return count; +} + +/* get bsp value */ +static ssize_t read_bsp(char *buf, char *str) +{ + ssize_t len=0; + + mutex_lock(&lpc_data->access_lock); + len=sprintf(buf, "%s", str); + mutex_unlock(&lpc_data->access_lock); + + BSP_LOG_R("reg_val=%s", str); + + return len; +} + +/* set bsp value */ +static ssize_t write_bsp(const char *buf, char *str, size_t str_len, size_t count) +{ + mutex_lock(&lpc_data->access_lock); + snprintf(str, str_len, "%s", buf); + mutex_unlock(&lpc_data->access_lock); + + BSP_LOG_W("reg_val=%s", str); + + return count; +} + +/* get mb cpld version in human readable format */ +static ssize_t read_mb_cpld_1_version_h(struct device *dev, + struct device_attribute *da, char *buf) +{ + ssize_t len=0; + u16 reg = REG_MB_CPLD_VERSION; + u8 mask = MASK_ALL; + u8 mask_major = 0b11000000; + u8 mask_minor = 0b00111111; + u8 reg_val; + u8 major, minor, build; + + mutex_lock(&lpc_data->access_lock); + reg_val = _mask_shift(inb(reg), mask); + mutex_unlock(&lpc_data->access_lock); + major = _mask_shift(reg_val, mask_major); + minor = _mask_shift(reg_val, mask_minor); + BSP_LOG_R("reg=0x%03x, reg_val=0x%02x", reg, reg_val); + + reg = REG_MB_CPLD_BUILD; + mutex_lock(&lpc_data->access_lock); + reg_val = _mask_shift(inb(reg), mask); + mutex_unlock(&lpc_data->access_lock); + build = reg_val; + BSP_LOG_R("reg=0x%03x, reg_val=0x%02x", reg, reg_val); + + len=sprintf(buf, "%d.%02d.%03d\n", major, minor, build); + return len; +} + +/* set mb_mux_reset register value */ +static ssize_t write_mb_mux_reset(struct device *dev, + struct device_attribute *da, const char *buf, size_t count) +{ + u8 val = 0; + u8 reg_val = 0; + static int mux_reset_flag = 0; + + if(kstrtou8(buf, 0, &val) < 0) + return -EINVAL; + + if(mux_reset_flag == 0) { + if(val == 0) { + mutex_lock(&lpc_data->access_lock); + mux_reset_flag = 1; + printk(KERN_INFO "i2c mux reset is triggered...\n"); + reg_val = inb(REG_MB_MUX_RESET); + outb((reg_val & 0b11111000), REG_MB_MUX_RESET); + mdelay(100); + outb((reg_val | 0b00000111), REG_MB_MUX_RESET); + mdelay(500); + mux_reset_flag = 0; + mutex_unlock(&lpc_data->access_lock); + } else { + return -EINVAL; + } + } else { + printk(KERN_INFO "i2c mux is resetting... (ignore)\n"); + mutex_lock(&lpc_data->access_lock); + mutex_unlock(&lpc_data->access_lock); + } + + return count; +} + +/* get lpc register value */ +static ssize_t read_lpc_callback(struct device *dev, + struct device_attribute *da, char *buf) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + u16 reg = 0; + u8 mask = MASK_ALL; + u8 base = BASE_DEC; + + switch (attr->index) { + //MB CPLD + case ATT_MB_BRD_ID_0: + reg = REG_MB_BRD_ID_0; + break; + case ATT_MB_BRD_ID_1: + reg = REG_MB_BRD_ID_1; + break; + case ATT_MB_CPLD_1_VERSION: + reg = REG_MB_CPLD_VERSION; + break; + case ATT_MB_BRD_SKU_ID: + reg = REG_MB_BRD_ID_0; + mask = 0xFF; + break; + case ATT_MB_BRD_HW_ID: + reg = REG_MB_BRD_ID_1; + mask = 0x3; + break; + case ATT_MB_BRD_ID_TYPE: + reg = REG_MB_BRD_ID_1; + mask = 0x80; + break; + case ATT_MB_BRD_BUILD_ID: + reg = REG_MB_BRD_ID_1; + mask = 0x18; + break; + case ATT_MB_BRD_DEPH_ID: + reg = REG_MB_BRD_ID_1; + mask = 0x4; + break; + case ATT_MB_BRD_EXT_ID: + reg = REG_MB_EXTEND_ID; + mask = 0x07; + break; + case ATT_MB_MUX_RESET: + reg = REG_MB_MUX_RESET; + mask = 0x07; + base = BASE_HEX; + break; + case ATT_MB_FAN_STATUS: + reg = REG_MB_FAN_STATUS; + base = BASE_HEX; + break; + case ATT_MB_PSU_STATUS: + reg = REG_MB_PSU_STATUS; + base = BASE_HEX; + break; + case ATT_MB_PORT_LED_CLR: + reg = REG_MB_PORT_LED_CLR; + mask = 0x1; + base = BASE_HEX; + break; + case ATT_MB_LED_SYS: + reg = REG_MB_SYS_LED_CTRL_1; + mask = 0xF0; + base = BASE_HEX; + break; + case ATT_MB_LED_ID: + reg = REG_MB_SYS_LED_CTRL_1; + mask = 0xF; + base = BASE_HEX; + break; + case ATT_MB_LED_POE: + reg = REG_MB_SYS_LED_STATUS_1; + mask = 0xF0; + base = BASE_HEX; + break; + case ATT_MB_LED_SPD: + reg = REG_MB_SYS_LED_STATUS_1; + mask = 0xF; + base = BASE_HEX; + break; + case ATT_MB_LED_FAN: + reg = REG_MB_SYS_LED_STATUS_2; + mask = 0xF0; + base = BASE_HEX; + break; + case ATT_MB_LED_LNK: + reg = REG_MB_SYS_LED_STATUS_2; + mask = 0xF; + base = BASE_HEX; + break; + case ATT_MB_LED_PWR1: + reg = REG_MB_SYS_LED_STATUS_3; + mask = 0xF0; + base = BASE_HEX; + break; + case ATT_MB_LED_PWR0: + reg = REG_MB_SYS_LED_STATUS_3; + mask = 0xF; + base = BASE_HEX; + break; + //BSP + case ATT_BSP_REG_VALUE: + if (kstrtou16(bsp_reg, 0, ®) < 0) + return -EINVAL; + + mask = MASK_ALL; + break; + default: + return -EINVAL; + } + return read_lpc_reg(reg, mask, base, buf); +} + +/* set lpc register value */ +static ssize_t write_lpc_callback(struct device *dev, + struct device_attribute *da, const char *buf, size_t count) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + u16 reg = 0; + u8 mask = MASK_ALL; + + switch (attr->index) { + case ATT_MB_PORT_LED_CLR: + reg = REG_MB_PORT_LED_CLR; + mask = 0x1; + break; + case ATT_MB_LED_SYS: + reg = REG_MB_SYS_LED_CTRL_1; + mask = 0xF0; + break; + case ATT_MB_LED_ID: + reg = REG_MB_SYS_LED_CTRL_1; + mask = 0xF; + break; + default: + return -EINVAL; + } + return write_lpc_reg(reg, mask, buf, count); +} + +/* get bsp parameter value */ +static ssize_t read_bsp_callback(struct device *dev, + struct device_attribute *da, char *buf) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + int str_len=0; + char *str=NULL; + + switch (attr->index) { + case ATT_BSP_VERSION: + str = bsp_version; + str_len = sizeof(bsp_version); + break; + case ATT_BSP_DEBUG: + str = bsp_debug; + str_len = sizeof(bsp_debug); + break; + case ATT_BSP_REG: + str = bsp_reg; + str_len = sizeof(bsp_reg); + break; + default: + return -EINVAL; + } + return read_bsp(buf, str); +} + +/* set bsp parameter value */ +static ssize_t write_bsp_callback(struct device *dev, + struct device_attribute *da, const char *buf, size_t count) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + int str_len=0; + char *str=NULL; + u16 reg = 0; + u8 bsp_debug_u8 = 0; + + switch (attr->index) { + case ATT_BSP_VERSION: + str = bsp_version; + str_len = sizeof(str); + break; + case ATT_BSP_DEBUG: + str = bsp_debug; + str_len = sizeof(str); + break; + case ATT_BSP_REG: + if(kstrtou16(buf, 0, ®) < 0) + return -EINVAL; + + str = bsp_reg; + str_len = sizeof(str); + break; + default: + return -EINVAL; + } + + if(attr->index == ATT_BSP_DEBUG) { + if(kstrtou8(buf, 0, &bsp_debug_u8) < 0) { + return -EINVAL; + } else if (_config_bsp_log(bsp_debug_u8) < 0) { + return -EINVAL; + } + } + + return write_bsp(buf, str, str_len, count); +} + +static ssize_t write_bsp_pr_callback(struct device *dev, + struct device_attribute *da, const char *buf, size_t count) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + int str_len = strlen(buf); + + if(str_len <= 0) + return str_len; + + switch (attr->index) { + case ATT_BSP_PR_INFO: + BSP_PR(KERN_INFO, "%s", buf); + break; + case ATT_BSP_PR_ERR: + BSP_PR(KERN_ERR, "%s", buf); + break; + default: + return -EINVAL; + } + + return str_len; +} + +/* get gpio max value */ +static ssize_t read_gpio_max_callback(struct device *dev, + struct device_attribute *da, + char *buf) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + + if (attr->index == ATT_BSP_GPIO_MAX) { + return sprintf(buf, "%d\n", ARCH_NR_GPIOS-1); + } + return -1; +} + +//SENSOR_DEVICE_ATTR - MB +static SENSOR_DEVICE_ATTR(board_id_0, S_IRUGO, read_lpc_callback, NULL, ATT_MB_BRD_ID_0); +static SENSOR_DEVICE_ATTR(board_id_1, S_IRUGO, read_lpc_callback, NULL, ATT_MB_BRD_ID_1); +static SENSOR_DEVICE_ATTR(mb_cpld_1_version, S_IRUGO, read_lpc_callback, NULL, ATT_MB_CPLD_1_VERSION); +static SENSOR_DEVICE_ATTR(mb_cpld_1_version_h, S_IRUGO, read_mb_cpld_1_version_h, NULL, ATT_MB_CPLD_1_VERSION_H); +static SENSOR_DEVICE_ATTR(board_sku_id, S_IRUGO, read_lpc_callback, NULL, ATT_MB_BRD_SKU_ID); +static SENSOR_DEVICE_ATTR(board_hw_id, S_IRUGO, read_lpc_callback, NULL, ATT_MB_BRD_HW_ID); +static SENSOR_DEVICE_ATTR(board_id_type, S_IRUGO, read_lpc_callback, NULL, ATT_MB_BRD_ID_TYPE); +static SENSOR_DEVICE_ATTR(board_build_id, S_IRUGO, read_lpc_callback, NULL, ATT_MB_BRD_BUILD_ID); +static SENSOR_DEVICE_ATTR(board_deph_id, S_IRUGO, read_lpc_callback, NULL, ATT_MB_BRD_DEPH_ID); +static SENSOR_DEVICE_ATTR(board_ext_id, S_IRUGO, read_lpc_callback, NULL, ATT_MB_BRD_EXT_ID); +static SENSOR_DEVICE_ATTR(mux_reset, S_IRUGO | S_IWUSR, read_lpc_callback, write_mb_mux_reset, ATT_MB_MUX_RESET); +static SENSOR_DEVICE_ATTR(fan_status, S_IRUGO, read_lpc_callback, NULL, ATT_MB_FAN_STATUS); +static SENSOR_DEVICE_ATTR(psu_status, S_IRUGO, read_lpc_callback, NULL, ATT_MB_PSU_STATUS); +static SENSOR_DEVICE_ATTR(port_led_clear, S_IRUGO | S_IWUSR, read_lpc_callback, write_lpc_callback, ATT_MB_PORT_LED_CLR); +static SENSOR_DEVICE_ATTR(led_sys, S_IRUGO | S_IWUSR, read_lpc_callback, write_lpc_callback, ATT_MB_LED_SYS); +static SENSOR_DEVICE_ATTR(led_id, S_IRUGO | S_IWUSR, read_lpc_callback, write_lpc_callback, ATT_MB_LED_ID); +static SENSOR_DEVICE_ATTR(led_poe, S_IRUGO, read_lpc_callback, NULL, ATT_MB_LED_POE); +static SENSOR_DEVICE_ATTR(led_spd, S_IRUGO, read_lpc_callback, NULL, ATT_MB_LED_SPD); +static SENSOR_DEVICE_ATTR(led_fan, S_IRUGO, read_lpc_callback, NULL, ATT_MB_LED_FAN); +static SENSOR_DEVICE_ATTR(led_lnk, S_IRUGO, read_lpc_callback, NULL, ATT_MB_LED_LNK); +static SENSOR_DEVICE_ATTR(led_pwr1, S_IRUGO, read_lpc_callback, NULL, ATT_MB_LED_PWR1); +static SENSOR_DEVICE_ATTR(led_pwr0, S_IRUGO, read_lpc_callback, NULL, ATT_MB_LED_PWR0); + +//SENSOR_DEVICE_ATTR - BSP +static SENSOR_DEVICE_ATTR(bsp_version , S_IRUGO | S_IWUSR, read_bsp_callback, write_bsp_callback, ATT_BSP_VERSION); +static SENSOR_DEVICE_ATTR(bsp_debug , S_IRUGO | S_IWUSR, read_bsp_callback, write_bsp_callback, ATT_BSP_DEBUG); +static SENSOR_DEVICE_ATTR(bsp_pr_info , S_IWUSR , NULL , write_bsp_pr_callback, ATT_BSP_PR_INFO); +static SENSOR_DEVICE_ATTR(bsp_pr_err , S_IWUSR , NULL , write_bsp_pr_callback, ATT_BSP_PR_ERR); +static SENSOR_DEVICE_ATTR(bsp_reg , S_IRUGO | S_IWUSR, read_lpc_callback, write_bsp_callback, ATT_BSP_REG); +static SENSOR_DEVICE_ATTR(bsp_reg_value, S_IRUGO , read_lpc_callback, NULL, ATT_BSP_REG_VALUE); +static SENSOR_DEVICE_ATTR(bsp_gpio_max, S_IRUGO , read_gpio_max_callback, NULL, ATT_BSP_GPIO_MAX); + + +static struct attribute *mb_cpld_attrs[] = { + &sensor_dev_attr_board_id_0.dev_attr.attr, + &sensor_dev_attr_board_id_1.dev_attr.attr, + &sensor_dev_attr_mb_cpld_1_version.dev_attr.attr, + &sensor_dev_attr_mb_cpld_1_version_h.dev_attr.attr, + &sensor_dev_attr_board_sku_id.dev_attr.attr, + &sensor_dev_attr_board_hw_id.dev_attr.attr, + &sensor_dev_attr_board_id_type.dev_attr.attr, + &sensor_dev_attr_board_build_id.dev_attr.attr, + &sensor_dev_attr_board_deph_id.dev_attr.attr, + &sensor_dev_attr_board_ext_id.dev_attr.attr, + &sensor_dev_attr_mux_reset.dev_attr.attr, + &sensor_dev_attr_fan_status.dev_attr.attr, + &sensor_dev_attr_psu_status.dev_attr.attr, + &sensor_dev_attr_port_led_clear.dev_attr.attr, + &sensor_dev_attr_led_sys.dev_attr.attr, + &sensor_dev_attr_led_id.dev_attr.attr, + &sensor_dev_attr_led_poe.dev_attr.attr, + &sensor_dev_attr_led_spd.dev_attr.attr, + &sensor_dev_attr_led_fan.dev_attr.attr, + &sensor_dev_attr_led_lnk.dev_attr.attr, + &sensor_dev_attr_led_pwr0.dev_attr.attr, + &sensor_dev_attr_led_pwr1.dev_attr.attr, + NULL, +}; + +static struct attribute *bsp_attrs[] = { + &sensor_dev_attr_bsp_version.dev_attr.attr, + &sensor_dev_attr_bsp_debug.dev_attr.attr, + &sensor_dev_attr_bsp_pr_info.dev_attr.attr, + &sensor_dev_attr_bsp_pr_err.dev_attr.attr, + &sensor_dev_attr_bsp_reg.dev_attr.attr, + &sensor_dev_attr_bsp_reg_value.dev_attr.attr, + &sensor_dev_attr_bsp_gpio_max.dev_attr.attr, + NULL, +}; + +static struct attribute_group mb_cpld_attr_grp = { + .name = "mb_cpld", + .attrs = mb_cpld_attrs, +}; + +static struct attribute_group bsp_attr_grp = { + .name = "bsp", + .attrs = bsp_attrs, +}; + +static void lpc_dev_release( struct device * dev) +{ + return; +} + +static struct platform_device lpc_dev = { + .name = DRIVER_NAME, + .id = -1, + .dev = { + .release = lpc_dev_release, + } +}; + +static int lpc_drv_probe(struct platform_device *pdev) +{ + int i = 0, grp_num = 2; + int err[5] = {0}; + struct attribute_group *grp; + + lpc_data = devm_kzalloc(&pdev->dev, sizeof(struct lpc_data_s), + GFP_KERNEL); + if(!lpc_data) + return -ENOMEM; + + mutex_init(&lpc_data->access_lock); + + for (i=0; idev.kobj, grp); + if(err[i]) { + printk(KERN_ERR "Cannot create sysfs for group %s\n", grp->name); + goto exit; + } else { + continue; + } + } + + return 0; + +exit: + for (i=0; idev.kobj, grp); + if(!err[i]) { + //remove previous successful cases + continue; + } else { + //remove first failed case, then return + return err[i]; + } + } + return 0; +} + +static int lpc_drv_remove(struct platform_device *pdev) +{ + sysfs_remove_group(&pdev->dev.kobj, &mb_cpld_attr_grp); + sysfs_remove_group(&pdev->dev.kobj, &bsp_attr_grp); + + return 0; +} + +static struct platform_driver lpc_drv = { + .probe = lpc_drv_probe, + .remove = __exit_p(lpc_drv_remove), + .driver = { + .name = DRIVER_NAME, + }, +}; + +int lpc_init(void) +{ + int err = 0; + + err = platform_driver_register(&lpc_drv); + if(err) { + printk(KERN_ERR "%s(#%d): platform_driver_register failed(%d)\n", + __func__, __LINE__, err); + + return err; + } + + err = platform_device_register(&lpc_dev); + if(err) { + printk(KERN_ERR "%s(#%d): platform_device_register failed(%d)\n", + __func__, __LINE__, err); + platform_driver_unregister(&lpc_drv); + return err; + } + + return err; +} + +void lpc_exit(void) +{ + platform_driver_unregister(&lpc_drv); + platform_device_unregister(&lpc_dev); +} + +MODULE_AUTHOR("Leo Lin "); +MODULE_DESCRIPTION("x86_64_ufispace_s6301_56st_lpc driver"); +MODULE_LICENSE("GPL"); + +module_init(lpc_init); +module_exit(lpc_exit); diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/modules/x86-64-ufispace-s6301-56st-sys-eeprom.c b/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/modules/x86-64-ufispace-s6301-56st-sys-eeprom.c new file mode 100644 index 000000000000..5c6dec193ef6 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/modules/x86-64-ufispace-s6301-56st-sys-eeprom.c @@ -0,0 +1,273 @@ +/* + * Copyright (C) 1998, 1999 Frodo Looijaard and + * Philip Edelbrock + * Copyright (C) 2003 Greg Kroah-Hartman + * Copyright (C) 2003 IBM Corp. + * Copyright (C) 2004 Jean Delvare + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* enable dev_dbg print out */ +//#define DEBUG + +#define __STDC_WANT_LIB_EXT1__ 1 +#include +#include +#include +#include +#include +#include +#include + +/* Addresses to scan */ +static const unsigned short normal_i2c[] = { /*0x50, 0x51, 0x52, 0x53, 0x54, + 0x55, 0x56, 0x57,*/ I2C_CLIENT_END }; + +/* Size of EEPROM in bytes */ +#define EEPROM_SIZE 512 + +#define SLICE_BITS (6) +#define SLICE_SIZE (1 << SLICE_BITS) +#define SLICE_NUM (EEPROM_SIZE/SLICE_SIZE) + +/* Each client has this additional data */ +struct eeprom_data { + struct mutex update_lock; + u8 valid; /* bitfield, bit!=0 if slice is valid */ + unsigned long last_updated[SLICE_NUM]; /* In jiffies, 8 slices */ + u8 data[EEPROM_SIZE]; /* Register values */ +}; + + +static void sys_eeprom_update_client(struct i2c_client *client, u8 slice) +{ + struct eeprom_data *data = i2c_get_clientdata(client); + int i, j; + int ret; + int addr; + + mutex_lock(&data->update_lock); + + if (!(data->valid & (1 << slice)) || + time_after(jiffies, data->last_updated[slice] + 300 * HZ)) { + dev_dbg(&client->dev, "Starting eeprom update, slice %u\n", slice); + + addr = slice << SLICE_BITS; + + ret = i2c_smbus_write_byte_data(client, (u8)((addr >> 8) & 0xFF), (u8)(addr & 0xFF)); + /* select the eeprom address */ + if (ret < 0) { + dev_err(&client->dev, "address set failed\n"); + goto exit; + } + + if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_READ_BYTE)) { + goto exit; + } + + for (i = slice << SLICE_BITS; i < (slice + 1) << SLICE_BITS; i+= SLICE_SIZE) { + for (j = i; j < (i+SLICE_SIZE); j++) { + int res; + + res = i2c_smbus_read_byte(client); + if (res < 0) { + goto exit; + } + + data->data[j] = res & 0xFF; + } + } + + data->last_updated[slice] = jiffies; + data->valid |= (1 << slice); + } +exit: + mutex_unlock(&data->update_lock); +} + +static ssize_t sys_eeprom_read(struct file *filp, struct kobject *kobj, + struct bin_attribute *bin_attr, + char *buf, loff_t off, size_t count) +{ + struct i2c_client *client = to_i2c_client(container_of(kobj, struct device, kobj)); + struct eeprom_data *data = i2c_get_clientdata(client); + u8 slice; + + if (off > EEPROM_SIZE) { + return 0; + } + if (off + count > EEPROM_SIZE) { + count = EEPROM_SIZE - off; + } + if (count == 0) { + return 0; + } + + /* Only refresh slices which contain requested bytes */ + for (slice = off >> SLICE_BITS; slice <= (off + count - 1) >> SLICE_BITS; slice++) { + sys_eeprom_update_client(client, slice); + } + + memcpy(buf, &data->data[off], count); + + return count; +} + +static ssize_t sys_eeprom_write(struct file *filp, struct kobject *kobj, + struct bin_attribute *bin_attr, + char *buf, loff_t off, size_t count) +{ + struct i2c_client *client = to_i2c_client(container_of(kobj, struct device, kobj)); + struct eeprom_data *data = i2c_get_clientdata(client); + int ret; + int i; + u8 cmd; + u16 value16; + + dev_dbg(&client->dev, "sys_eeprom_write off=%d, count=%d\n", (int)off, (int)count); + + if (off > EEPROM_SIZE) { + return 0; + } + if (off + count > EEPROM_SIZE) { + count = EEPROM_SIZE - off; + } + if (count == 0) { + return 0; + } + + mutex_lock(&data->update_lock); + + for(i=0; i < count; i++) { + /* write command */ + cmd = (off >> 8) & 0xff; + value16 = off & 0xff; + value16 |= buf[i] << 8; + ret = i2c_smbus_write_word_data(client, cmd, value16); + + if (ret < 0) { + dev_err(&client->dev, "write address failed at %d \n", (int)off); + goto exit; + } + + off++; + + /* need to wait for write complete */ + udelay(10000); + } +exit: + mutex_unlock(&data->update_lock); + /* force to update client when reading */ + for(i=0; i < SLICE_NUM; i++) { + data->last_updated[i] = 0; + } + + return count; +} + +static struct bin_attribute sys_eeprom_attr = { + .attr = { + .name = "eeprom", + .mode = S_IRUGO | S_IWUSR, + }, + .size = EEPROM_SIZE, + .read = sys_eeprom_read, + .write = sys_eeprom_write, +}; + +/* Return 0 if detection is successful, -ENODEV otherwise */ +static int sys_eeprom_detect(struct i2c_client *client, struct i2c_board_info *info) +{ + struct i2c_adapter *adapter = client->adapter; + + /* EDID EEPROMs are often 24C00 EEPROMs, which answer to all + addresses 0x50-0x57, but we only care about 0x51 and 0x55. So decline + attaching to addresses >= 0x56 on DDC buses */ + if (!(adapter->class & I2C_CLASS_SPD) && client->addr >= 0x56) { + return -ENODEV; + } + + if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_READ_BYTE) + && !i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WRITE_BYTE_DATA)) { + return -ENODEV; + } + + strlcpy(info->type, "eeprom", I2C_NAME_SIZE); + + return 0; +} + +static int sys_eeprom_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct eeprom_data *data; + int err; + + if (!(data = kzalloc(sizeof(struct eeprom_data), GFP_KERNEL))) { + err = -ENOMEM; + goto exit; + } + +#ifdef __STDC_LIB_EXT1__ + memset_s(data->data, EEPROM_SIZE, 0xff, EEPROM_SIZE); +#else + memset(data->data, 0xff, EEPROM_SIZE); +#endif + + i2c_set_clientdata(client, data); + mutex_init(&data->update_lock); + + /* create the sysfs eeprom file */ + err = sysfs_create_bin_file(&client->dev.kobj, &sys_eeprom_attr); + if (err) { + goto exit_kfree; + } + + return 0; + +exit_kfree: + kfree(data); +exit: + return err; +} + +static int sys_eeprom_remove(struct i2c_client *client) +{ + sysfs_remove_bin_file(&client->dev.kobj, &sys_eeprom_attr); + kfree(i2c_get_clientdata(client)); + + return 0; +} + +static const struct i2c_device_id sys_eeprom_id[] = { + { "sys_eeprom", 0 }, + { } +}; + +static struct i2c_driver sys_eeprom_driver = { + .driver = { + .name = "sys_eeprom", + }, + .probe = sys_eeprom_probe, + .remove = sys_eeprom_remove, + .id_table = sys_eeprom_id, + + .class = I2C_CLASS_DDC | I2C_CLASS_SPD, + .detect = sys_eeprom_detect, + .address_list = normal_i2c, +}; + +module_i2c_driver(sys_eeprom_driver); + +MODULE_AUTHOR("Leo Lin "); +MODULE_DESCRIPTION("UfiSpace System EEPROM driver"); +MODULE_LICENSE("GPL"); diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/systemd/pddf-platform-init.service b/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/service/pddf-platform-init.service similarity index 100% rename from platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/systemd/pddf-platform-init.service rename to platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/service/pddf-platform-init.service diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/__init__.py b/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/sonic_platform/__init__.py similarity index 100% rename from platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/__init__.py rename to platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/sonic_platform/__init__.py diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/sonic_platform/chassis.py b/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/sonic_platform/chassis.py new file mode 100644 index 000000000000..ab3e44f74432 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/sonic_platform/chassis.py @@ -0,0 +1,220 @@ +#!/usr/bin/env python + +############################################################################# +# PDDF +# Module contains an implementation of SONiC Chassis API +# +############################################################################# + +try: + import time + from sonic_platform_pddf_base.pddf_chassis import PddfChassis + from sonic_py_common import device_info +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + +NUM_COMPONENT = 2 + +class Chassis(PddfChassis): + """ + PDDF Platform-specific Chassis class + """ + + port_dict = {} + + def __init__(self, pddf_data=None, pddf_plugin_data=None): + PddfChassis.__init__(self, pddf_data, pddf_plugin_data) + self._initialize_components() + + def _initialize_components(self): + from sonic_platform.component import Component + for index in range(NUM_COMPONENT): + component = Component(index) + self._component_list.append(component) + + # Provide the functions/variables below for which implementation is to be overwritten + def get_name(self): + """ + Retrieves the name of the chassis + Returns: + string: The name of the chassis + """ + return device_info.get_platform() + + def initizalize_system_led(self): + return True + + def get_status_led(self): + return self.get_system_led("SYS_LED") + + def get_change_event(self, timeout=0): + """ + Returns a nested dictionary containing all devices which have + experienced a change at chassis level + Args: + timeout: Timeout in milliseconds (optional). If timeout == 0, + this method will block until a change is detected. + Returns: + (bool, dict): + - bool: True if call successful, False if not; + - dict: A nested dictionary where key is a device type, + value is a dictionary with key:value pairs in the format of + {'device_id':'device_event'}, where device_id is the device ID + for this device and device_event. + The known devices's device_id and device_event was defined as table below. + ----------------------------------------------------------------- + device | device_id | device_event | annotate + ----------------------------------------------------------------- + 'sfp' '' '0' Sfp removed + '1' Sfp inserted + '2' I2C bus stuck + '3' Bad eeprom + '4' Unsupported cable + '5' High Temperature + '6' Bad cable + -------------------------------------------------------------------- + Ex. 'sfp':{'11':'0', '12':'1'}, + Indicates that: + sfp 11 has been removed, sfp 12 has been inserted. + Note: For sfp, when event 3-6 happened, the module will not be avalaible, + XCVRD shall stop to read eeprom before SFP recovered from error status. + """ + + change_event_dict = {"sfp": {}} + + start_time = time.time() + forever = False + + if timeout == 0: + forever = True + elif timeout > 0: + timeout = timeout / float(1000) # Convert to secs + else: + print("get_change_event:Invalid timeout value", timeout) + return False, change_event_dict + + end_time = start_time + timeout + if start_time > end_time: + print( + "get_change_event:" "time wrap / invalid timeout value", + timeout, + ) + return False, change_event_dict # Time wrap or possibly incorrect timeout + try: + while timeout >= 0: + # check for sfp + sfp_change_dict = self.get_transceiver_change_event() + + if sfp_change_dict: + change_event_dict["sfp"] = sfp_change_dict + return True, change_event_dict + if forever: + time.sleep(1) + else: + timeout = end_time - time.time() + if timeout >= 1: + time.sleep(1) # We poll at 1 second granularity + else: + if timeout > 0: + time.sleep(timeout) + return True, change_event_dict + except Exception as e: + print(e) + print("get_change_event: Should not reach here.") + return False, change_event_dict + + def get_transceiver_change_event(self, timeout=0): + current_port_dict = {} + ret_dict = {} + + # Check for OIR events and return ret_dict + for index in range(self.platform_inventory['num_ports']): + if self._sfp_list[index].get_presence(): + current_port_dict[index] = self.plugin_data['XCVR']['plug_status']['inserted'] + else: + current_port_dict[index] = self.plugin_data['XCVR']['plug_status']['removed'] + + if len(self.port_dict) == 0: # first time + self.port_dict = current_port_dict + return {} + + if current_port_dict == self.port_dict: + return {} + + # Update reg value + for index, status in current_port_dict.items(): + if self.port_dict[index] != status: + ret_dict[index] = status + #ret_dict[str(index)] = status + self.port_dict = current_port_dict + for index, status in ret_dict.items(): + if int(status) == 1: + pass + #self._sfp_list[int(index)].check_sfp_optoe_type() + return ret_dict + + def get_sfp(self, index): + """ + Retrieves sfp represented by (1-based) index + + Args: + index: An integer, the index (1-based) of the sfp to retrieve. + The index should be the sequence of a physical port in a chassis, + starting from 1. + For example, 1 for Ethernet0, 2 for Ethernet4 and so on. + + Returns: + An object derived from SfpBase representing the specified sfp + """ + sfp = None + + try: + # The index will start from 1 + # sfputil already convert to physical port index according to config + sfp = self._sfp_list[index] + except IndexError: + sys.stderr.write("SFP index {} out of range (1-{})\n".format( + index, len(self._sfp_list))) + return sfp + + def set_system_led(self, led_device_name, color): + """ + Sets the color of an System LED device + Args: + led_device_name: a pre-defined LED device name list used in pddf-device.json. + color: A string representing the color with which to set a LED + Returns: + bool: True if the LED state is set successfully, False if not + """ + + if led_device_name in self.plugin_data['LED']['capability']['rw']: + result, msg = self.pddf_obj.set_system_led_color(led_device_name, color) + if not result and msg: + print(msg) + return (result) + else: + print("Not Support") + return False + + def get_reboot_cause(self): + """ + Retrieves the cause of the previous reboot + + Returns: + A tuple (string, string) where the first element is a string + containing the cause of the previous reboot. This string must be + one of the predefined strings in this class. If the first string + is "REBOOT_CAUSE_HARDWARE_OTHER", the second string can be used + to pass a description of the reboot cause. + """ + + reboot_cause_path = self.plugin_data['REBOOT_CAUSE']['reboot_cause_file'] + + try: + with open(reboot_cause_path, 'r', errors='replace') as fd: + data = fd.read() + sw_reboot_cause = data.strip() + except IOError: + sw_reboot_cause = "Unknown" + + return ('REBOOT_CAUSE_NON_HARDWARE', sw_reboot_cause) \ No newline at end of file diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/sonic_platform/component.py b/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/sonic_platform/component.py new file mode 100644 index 000000000000..c0b7816d4a82 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/sonic_platform/component.py @@ -0,0 +1,108 @@ +############################################################################# +# +# Component contains an implementation of SONiC Platform Base API and +# provides the components firmware management function +# +############################################################################# + +try: + import subprocess + from sonic_platform_base.component_base import ComponentBase +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + +CPLD_SYSFS = { + "CPLD1": "/sys/devices/platform/x86_64_ufispace_s6301_56st_lpc/mb_cpld/mb_cpld_1_version_h", +} + +BIOS_VERSION_PATH = "/sys/class/dmi/id/bios_version" +COMPONENT_LIST= [ + ("CPLD1", "CPLD 1"), + ("BIOS", "Basic Input/Output System"), +] + +class Component(ComponentBase): + """Platform-specific Component class""" + + DEVICE_TYPE = "component" + + def __init__(self, component_index=0): + self.index = component_index + self.name = self.get_name() + + def _run_command(self, command): + # Run bash command and print output to stdout + try: + process = subprocess.Popen( + shlex.split(command), stdout=subprocess.PIPE) + while True: + output = process.stdout.readline() + if output == '' and process.poll() is not None: + break + rc = process.poll() + if rc != 0: + return False + except Exception: + return False + return True + + def _get_bios_version(self): + # Retrieves the BIOS firmware version + try: + with open(BIOS_VERSION_PATH, 'r') as fd: + bios_version = fd.read() + return bios_version.strip() + except Exception as e: + return None + + def _get_cpld_version(self): + # Retrieves the CPLD firmware version + cpld_version = dict() + for cpld_name in CPLD_SYSFS: + cmd = "cat {}".format(CPLD_SYSFS[cpld_name]) + status, value = subprocess.getstatusoutput(cmd) + if not status: + cpld_version[cpld_name] = value.rstrip() + + return cpld_version + + def get_name(self): + """ + Retrieves the name of the component + Returns: + A string containing the name of the component + """ + return COMPONENT_LIST[self.index][0] + + def get_description(self): + """ + Retrieves the description of the component + Returns: + A string containing the description of the component + """ + return COMPONENT_LIST[self.index][1] + + def get_firmware_version(self): + """ + Retrieves the firmware version of module + Returns: + string: The firmware versions of the module + """ + fw_version = None + + if self.name == "BIOS": + fw_version = self._get_bios_version() + elif "CPLD" in self.name: + cpld_version = self._get_cpld_version() + fw_version = cpld_version.get(self.name) + return fw_version + + def install_firmware(self, image_path): + """ + Install firmware to module + Args: + image_path: A string, path to firmware image + Returns: + A boolean, True if install successfully, False if not + """ + raise NotImplementedError diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/eeprom.py b/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/sonic_platform/eeprom.py similarity index 62% rename from platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/eeprom.py rename to platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/sonic_platform/eeprom.py index c25d711354f5..90ab1c779a48 100644 --- a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/eeprom.py +++ b/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/sonic_platform/eeprom.py @@ -1,3 +1,5 @@ +#!/usr/bin/env python + try: from sonic_platform_pddf_base.pddf_eeprom import PddfEeprom except ImportError as e: @@ -10,3 +12,10 @@ def __init__(self, pddf_data=None, pddf_plugin_data=None): PddfEeprom.__init__(self, pddf_data, pddf_plugin_data) # Provide the functions/variables below for which implementation is to be overwritten + + def platform_name_str(self): + (is_valid, results) = self.get_tlv_field(self.eeprom_data, self._TLV_CODE_PLATFORM_NAME) + if not is_valid: + return "N/A" + + return results[2].decode('ascii') \ No newline at end of file diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/sonic_platform/fan.py b/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/sonic_platform/fan.py new file mode 100644 index 000000000000..2eadfd0a465a --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/sonic_platform/fan.py @@ -0,0 +1,153 @@ +#!/usr/bin/env python + +import os + +try: + from sonic_platform_pddf_base.pddf_fan import PddfFan + from sonic_platform.psu_fru import PsuFru +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + + +class Fan(PddfFan): + """PDDF Platform-Specific Fan class""" + + def __init__(self, tray_idx, fan_idx=0, pddf_data=None, pddf_plugin_data=None, is_psu_fan=False, psu_index=0): + # idx is 0-based + PddfFan.__init__(self, tray_idx, fan_idx, pddf_data, pddf_plugin_data, is_psu_fan, psu_index) + + # Provide the functions/variables below for which implementation is to be overwritten + # Since psu_fan airflow direction cant be read from sysfs, it is fixed as 'F2B' or 'intake' + + def get_speed(self): + """ + Retrieves the speed of fan as a percentage of full speed + + Returns: + An integer, the percentage of full fan speed, in the range 0 (off) + to 100 (full speed) + """ + speed_percentage = 0 + if self.is_psu_fan: + max_speed = int(self.plugin_data['PSU']['PSU_FAN_MAX_SPEED']) + else: + max_speed = int(self.plugin_data['FAN']['FAN_MAX_SPEED']) + + speed = int(self.get_speed_rpm()) + + + speed_percentage = round((speed*100)/max_speed) + return min(speed_percentage, 100) + + def get_speed_rpm(self): + """ + Retrieves the speed of fan in RPM + + Returns: + An integer, Speed of fan in RPM + """ + rpm_speed = 0 + if self.is_psu_fan: + attr = "psu_fan{}_speed_rpm".format(self.fan_index) + device = "PSU{}".format(self.fans_psu_index) + output = self.pddf_obj.get_attr_name_output(device, attr) + if output is None: + return rpm_speed + + output['status'] = output['status'].rstrip() + if output['status'].isalpha(): + return rpm_speed + else: + rpm_speed = int(float(output['status'])) + else: + ucd_path = "/sys/bus/i2c/devices/5-0034/hwmon/" + if os.path.exists(ucd_path): + hwmon_dir = os.listdir(ucd_path) + with open("{}/{}/temp{}_input".format(ucd_path, hwmon_dir[0], self.fantray_index), "rb") as f: + rpm_speed = int(f.read().strip()) + + return rpm_speed + + def get_direction(self): + """ + Retrieves the direction of fan + Returns: + A string, either FAN_DIRECTION_INTAKE or FAN_DIRECTION_EXHAUST + depending on fan direction + """ + direction = self.FAN_DIRECTION_NOT_APPLICABLE + if self.is_psu_fan: + psu_fru = PsuFru(self.fans_psu_index) + if psu_fru.mfr_id == "not available": + return direction + for dev in self.plugin_data['PSU']['psu_support_list']: + if dev['Mfr_id'] == psu_fru.mfr_id and dev['Model'] == psu_fru.model: + dir = dev['Dir'] + break + else: + attr = "fan{}_direction".format(self.fantray_index) + device = "FAN-CTRL" + output = self.pddf_obj.get_attr_name_output(device, attr) + if not output: + return direction + mode = output['mode'] + val = output['status'].strip() + vmap = self.plugin_data['FAN']['direction'][mode]['valmap'] + if val in vmap: + dir = vmap[val] + + return dir + + def get_presence(self): + """ + Retrieves the presence of the device + Returns: + bool: True if device is present, False if not + """ + presence = False + if self.is_psu_fan: + attr = "psu_present" + device = "PSU{}".format(self.fans_psu_index) + else: + attr = "fan{}_present".format(self.fantray_index) + device = "FAN-CTRL" + + output = self.pddf_obj.get_attr_name_output(device, attr) + if not output: + return presence + + + mode = output['mode'] + val = output['status'].strip() + vmap = self.plugin_data['FAN']['present'][mode]['valmap'] + + if val in vmap: + presence = vmap[val] + + return presence + + def get_target_speed(self): + """ + Retrieves the target (expected) speed of the fan + Returns: + An integer, the percentage of full fan speed, in the range 0 (off) + to 100 (full speed) + """ + + return self.get_speed() + + def set_speed(self, speed): + """ + Sets the fan speed + + Args: + speed: An integer, the percentage of full fan speed to set fan to, + in the range 0 (off) to 100 (full speed) + + Returns: + A boolean, True if speed is set successfully, False if not + """ + + print("Setting Fan speed is not allowed") + return False + diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/fan_drawer.py b/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/sonic_platform/fan_drawer.py similarity index 95% rename from platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/fan_drawer.py rename to platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/sonic_platform/fan_drawer.py index d03fd656f4d7..3b9bb607f632 100644 --- a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/fan_drawer.py +++ b/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/sonic_platform/fan_drawer.py @@ -14,4 +14,4 @@ def __init__(self, tray_idx, pddf_data=None, pddf_plugin_data=None): # idx is 0-based PddfFanDrawer.__init__(self, tray_idx, pddf_data, pddf_plugin_data) - # Provide the functions/variables below for which implementation is to be overwritten \ No newline at end of file + # Provide the functions/variables below for which implementation is to be overwritten diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/platform.py b/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/sonic_platform/platform.py similarity index 96% rename from platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/platform.py rename to platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/sonic_platform/platform.py index 6ff9446b951c..406b1179ae1b 100644 --- a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/platform.py +++ b/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/sonic_platform/platform.py @@ -1,3 +1,5 @@ +#!/usr/bin/env python + ############################################################################# # PDDF # Module contains an implementation of SONiC Platform Base API and @@ -5,6 +7,7 @@ # ############################################################################# + try: from sonic_platform_pddf_base.pddf_platform import PddfPlatform except ImportError as e: diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/sonic_platform/psu.py b/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/sonic_platform/psu.py new file mode 100644 index 000000000000..008aa600cdf8 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/sonic_platform/psu.py @@ -0,0 +1,67 @@ +#!/usr/bin/env python + + +try: + from sonic_platform_pddf_base.pddf_psu import PddfPsu + from sonic_platform.psu_fru import PsuFru +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + + +class Psu(PddfPsu): + """PDDF Platform-Specific PSU class""" + + PLATFORM_PSU_CAPACITY = 750 + + def __init__(self, index, pddf_data=None, pddf_plugin_data=None): + PddfPsu.__init__(self, index, pddf_data, pddf_plugin_data) + self.psu_fru = PsuFru(self.psu_index) + + # Provide the functions/variables below for which implementation is to be overwritten + def get_maximum_supplied_power(self): + """ + Retrieves the maximum supplied power by PSU (or PSU capacity) + Returns: + A float number, the maximum power output in Watts. + e.g. 1200.1 + """ + return float(self.PLATFORM_PSU_CAPACITY) + + def get_power(self): + """ + Retrieves current energy supplied by PSU + + Returns: + A float number, the power in watts, + e.g. 302.6 + """ + + # power is returned in micro watts + return round(float(self.get_voltage()*self.get_current()), 2) + + def get_mfr_id(self): + """ + Retrieves the manufacturer's name (or id) of the device + + Returns: + string: Manufacturer's id of device + """ + return self.psu_fru.mfr_id.rstrip() + + def get_model(self): + """ + Retrieves the model number (or part number) of the device + + Returns: + string: Model/part number of device + """ + return self.psu_fru.model.rstrip() + + def get_serial(self): + """ + Retrieves the serial number of the device + + Returns: + string: Serial number of device + """ + return self.psu_fru.serial.rstrip() diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/sonic_platform/psu_fru.py b/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/sonic_platform/psu_fru.py new file mode 100644 index 000000000000..7f640352be7f --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/sonic_platform/psu_fru.py @@ -0,0 +1,52 @@ +#!/usr/bin/env python + +class PsuFru: + """PSU FRU class""" + eeprom = "" + mfr_id = "not available" + model = "not available" + serial = "not available" + + def __init__(self, psu_index): + self.psu_index = psu_index + self.eeprom = "/sys/bus/i2c/devices/2-00{}/eeprom".format(49 + psu_index) + self._parse_fru_eeprom() + + def _parse_fru_eeprom(self): + """ + Parsing eeprom fru content of PSU + """ + try: + with open(self.eeprom, 'rb') as eeprom: + data = eeprom.read() + + # check if dummy content + if data[0] == 0xff: + return + + i = 11 + + data_len = (data[i]&0x3f) + i += 1 + self.mfr_id = data[i:i+data_len].decode('utf-8') + i += data_len + + data_len = (data[i]&0x3f) + i += 1 + i += data_len + + data_len = (data[i]&0x3f) + i += 1 + self.model = data[i:i+data_len].decode('utf-8') + i += data_len + + data_len = (data[i]&0x3f) + i += 1 + i += data_len + + data_len = (data[i]&0x3f) + i += 1 + self.serial = data[i:i+data_len].decode('utf-8') + except Exception as e: + return + diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/sonic_platform/sfp.py b/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/sonic_platform/sfp.py new file mode 100644 index 000000000000..22229484ae60 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/sonic_platform/sfp.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python + +try: + from sonic_platform_pddf_base.pddf_sfp import PddfSfp +except ImportError as e: + raise ImportError (str(e) + "- required module not found") + + +class Sfp(PddfSfp): + """ + PDDF Platform-Specific Sfp class + """ + + def __init__(self, index, pddf_data=None, pddf_plugin_data=None): + PddfSfp.__init__(self, index, pddf_data, pddf_plugin_data) + self.index = index + + # Provide the functions/variables below for which implementation is to be overwritten + + def get_error_description(self): + """ + Retrives the error descriptions of the SFP module + Returns: + String that represents the current error descriptions of vendor specific errors + In case there are multiple errors, they should be joined by '|', + like: "Bad EEPROM|Unsupported cable" + """ + if not self.get_presence(): + return self.SFP_STATUS_UNPLUGGED + + return self.SFP_STATUS_OK + + def get_lpmode(self): + return False + + def set_lpmode(self, lpmode): + return False + + def reset(self): + return False diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/thermal.py b/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/sonic_platform/thermal.py similarity index 95% rename from platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/thermal.py rename to platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/sonic_platform/thermal.py index f2a73e5f5db8..77d6ec7ae886 100644 --- a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/thermal.py +++ b/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/sonic_platform/thermal.py @@ -1,3 +1,6 @@ +#!/usr/bin/env python + + try: from sonic_platform_pddf_base.pddf_thermal import PddfThermal except ImportError as e: diff --git a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/watchdog.py b/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/sonic_platform/watchdog.py similarity index 96% rename from platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/watchdog.py rename to platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/sonic_platform/watchdog.py index 37788c2c821e..88660b1a1faa 100644 --- a/platform/broadcom/sonic-platform-modules-ragile/ra-b6510-48v8c/sonic_platform/watchdog.py +++ b/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/sonic_platform/watchdog.py @@ -1,3 +1,5 @@ +#!/usr/bin/env python + ############################################################################# # # Module contains an implementation of platform specific watchdog API's diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/sonic_platform_setup.py b/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/sonic_platform_setup.py new file mode 100644 index 000000000000..3661c84a0cd6 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/sonic_platform_setup.py @@ -0,0 +1,27 @@ +from setuptools import setup + +setup( + name='sonic-platform', + version='1.0', + description='SONiC platform API implementation on ufispace platform', + license='Apache 2.0', + author='SONiC Team', + author_email='linuxnetdev@microsoft.com', + url='https://github.com/Azure/sonic-buildimage', + maintainer='Leo Lin', + maintainer_email='leo.yt.lin@ufispace.com', + packages=['sonic_platform'], + classifiers=[ + 'Development Status :: 3 - Alpha', + 'Environment :: Plugins', + 'Intended Audience :: Developers', + 'Intended Audience :: Information Technology', + 'Intended Audience :: System Administrators', + 'License :: OSI Approved :: Apache Software License', + 'Natural Language :: English', + 'Operating System :: POSIX :: Linux', + 'Programming Language :: Python :: 3.7', + 'Topic :: Utilities', + ], + keywords='sonic SONiC platform PLATFORM', +) diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/utils/pddf_post_device_create.sh b/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/utils/pddf_post_device_create.sh new file mode 100755 index 000000000000..5905a4e14b9b --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/utils/pddf_post_device_create.sh @@ -0,0 +1,11 @@ +#!/bin/bash +echo "Reset port led" +echo 0 > /sys/devices/platform/x86_64_ufispace_s6301_56st_lpc//mb_cpld/port_led_clear +sleep 0.5 +echo 1 > /sys/devices/platform/x86_64_ufispace_s6301_56st_lpc//mb_cpld/port_led_clear + +curr_led=$(pddf_ledutil getstatusled SYS_LED) +pddf_ledutil setstatusled SYS_LED green +echo "Set System $curr_led to green" + +echo "PDDF device post-create completed" diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/utils/pddf_post_driver_install.sh b/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/utils/pddf_post_driver_install.sh new file mode 100755 index 000000000000..ed2559977e42 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/utils/pddf_post_driver_install.sh @@ -0,0 +1,2 @@ +#!/bin/bash +echo "PDDF driver post-install completed" diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/utils/pddf_pre_driver_install.sh b/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/utils/pddf_pre_driver_install.sh new file mode 100755 index 000000000000..187943061e6c --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/utils/pddf_pre_driver_install.sh @@ -0,0 +1,11 @@ +#!/bin/bash +#rmmod gpio_ich +if [ ! -f /tmp/._pddf_pre_driver_init_completion ]; then + # make sure igb/i40e init in correct order + rmmod i2c-i801 + rmmod i2c_ismt + modprobe -r i2c-i801 + modprobe -r i2c_ismt + date > /tmp/._pddf_pre_driver_init_completion +fi +echo "PDDF driver pre-install completed" diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/utils/pddf_switch_svc.py b/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/utils/pddf_switch_svc.py new file mode 100644 index 000000000000..88c1a3b3e572 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s6301-56st/utils/pddf_switch_svc.py @@ -0,0 +1,86 @@ +#!/usr/bin/env python +# Script to stop and start the respective platforms default services. +# This will be used while switching the pddf->non-pddf mode and vice versa +import commands + +def check_pddf_support(): + return True + +def stop_platform_svc(): + + ''' + status, output = commands.getstatusoutput("systemctl stop s6301-56st-platform-monitor-fan.service") + if status: + print "Stop s6301-56st-platform-fan.service failed %d"%status + return False + + status, output = commands.getstatusoutput("systemctl stop s6301-56st-platform-monitor-psu.service") + if status: + print "Stop s6301-56st-platform-psu.service failed %d"%status + return False + + status, output = commands.getstatusoutput("systemctl stop s6301-56st-platform-monitor.service") + if status: + print "Stop s6301-56st-platform-init.service failed %d"%status + return False + status, output = commands.getstatusoutput("systemctl disable s6301-56st-platform-monitor.service") + if status: + print "Disable s6301-56st-platform-monitor.service failed %d"%status + return False + ''' + + status, output = commands.getstatusoutput("/usr/local/bin/platform_utility.py deinit") + if status: + print "platform_utility.py deinit command failed %d"%status + return False + + # HACK , stop the pddf-platform-init service if it is active + status, output = commands.getstatusoutput("systemctl stop pddf-platform-init.service") + if status: + print "Stop pddf-platform-init.service along with other platform serives failed %d"%status + return False + + return True + +def start_platform_svc(): + + status, output = commands.getstatusoutput("/usr/local/bin/platform_utility.py init") + if status: + print "platform_utility.py init command failed %d"%status + return False + + ''' + status, output = commands.getstatusoutput("systemctl enable s6301-56st-platform-monitor.service") + if status: + print "Enable s6301-56st-platform-monitor.service failed %d"%status + return False + status, output = commands.getstatusoutput("systemctl start s6301-56st-platform-monitor-fan.service") + if status: + print "Start s6301-56st-platform-monitor-fan.service failed %d"%status + return False + + status, output = commands.getstatusoutput("systemctl start s6301-56st-platform-monitor-psu.service") + if status: + print "Start s6301-56st-platform-monitor-psu.service failed %d"%status + return False + ''' + return True + +def start_platform_pddf(): + + status, output = commands.getstatusoutput("systemctl start pddf-platform-init.service") + if status: + print "Start pddf-platform-init.service failed %d"%status + return False + + return True + +def stop_platform_pddf(): + + status, output = commands.getstatusoutput("systemctl stop pddf-platform-init.service") + if status: + print "Stop pddf-platform-init.service failed %d"%status + return False + + return True + diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/modules/Makefile b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/modules/Makefile new file mode 100644 index 000000000000..f399cd24e23a --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/modules/Makefile @@ -0,0 +1,6 @@ + +MODULE_NAME = x86-64-ufispace-s7801-54xs-cpld.o x86-64-ufispace-s7801-54xs-sys-eeprom.o x86-64-ufispace-s7801-54xs-lpc.o pddf_custom_sysstatus_module.o +obj-m := $(MODULE_NAME) + +CFLAGS_pddf_custom_sysstatus_module.o := -I$(M)/../../../../pddf/i2c/modules/include +KBUILD_EXTRA_SYMBOLS := $(M)/../../../../pddf/i2c/Module.symvers.PDDF diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/modules/pddf_custom_sysstatus_module.c b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/modules/pddf_custom_sysstatus_module.c new file mode 100644 index 000000000000..b50bb428000a --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/modules/pddf_custom_sysstatus_module.c @@ -0,0 +1,276 @@ +/* + * Copyright 2019 Broadcom. + * The term ��Broadcom�� refers to Broadcom Inc. and/or its subsidiaries. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * A pddf kernel module for system status registers + */ + +#define __STDC_WANT_LIB_EXT1__ 1 +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../../../../pddf/i2c/modules/include/pddf_client_defs.h" +#include "../../../../pddf/i2c/modules/include/pddf_sysstatus_defs.h" + + +SYSSTATUS_DATA sysstatus_data = {0}; + +extern int board_i2c_cpld_read(unsigned short cpld_addr, u8 reg); +extern int board_i2c_cpld_write(unsigned short cpld_addr, u8 reg, u8 value); + +static ssize_t do_attr_operation(struct device *dev, struct device_attribute *da, const char *buf, size_t count); +ssize_t show_sysstatus_data(struct device *dev, struct device_attribute *da, char *buf); +ssize_t store_sysstatus_data(struct device *dev, struct device_attribute *da, const char *buf, size_t count); + + +PDDF_DATA_ATTR(attr_name, S_IWUSR|S_IRUGO, show_pddf_data, store_pddf_data, PDDF_CHAR, 32, + (void*)&sysstatus_data.sysstatus_addr_attr.aname, NULL); +PDDF_DATA_ATTR(attr_devaddr, S_IWUSR|S_IRUGO, show_pddf_data, store_pddf_data, PDDF_UINT32, + sizeof(uint32_t), (void*)&sysstatus_data.sysstatus_addr_attr.devaddr , NULL); +PDDF_DATA_ATTR(attr_offset, S_IWUSR|S_IRUGO, show_pddf_data, store_pddf_data, PDDF_UINT32, + sizeof(uint32_t), (void*)&sysstatus_data.sysstatus_addr_attr.offset, NULL); +PDDF_DATA_ATTR(attr_mask, S_IWUSR|S_IRUGO, show_pddf_data, store_pddf_data, PDDF_UINT32, + sizeof(uint32_t), (void*)&sysstatus_data.sysstatus_addr_attr.mask , NULL); +PDDF_DATA_ATTR(attr_len, S_IWUSR|S_IRUGO, show_pddf_data, store_pddf_data, PDDF_UINT32, + sizeof(uint32_t), (void*)&sysstatus_data.sysstatus_addr_attr.len , NULL); +PDDF_DATA_ATTR(attr_ops, S_IWUSR, NULL, do_attr_operation, PDDF_CHAR, 8, (void*)&sysstatus_data, NULL); + + + +static struct attribute *sysstatus_addr_attributes[] = { + &attr_attr_name.dev_attr.attr, + &attr_attr_devaddr.dev_attr.attr, + &attr_attr_offset.dev_attr.attr, + &attr_attr_mask.dev_attr.attr, + &attr_attr_len.dev_attr.attr, + &attr_attr_ops.dev_attr.attr, + NULL +}; + +PDDF_DATA_ATTR(board_sku_id , S_IRUGO, show_sysstatus_data, NULL, PDDF_UCHAR, sizeof(u8), NULL, NULL); +PDDF_DATA_ATTR(board_hw_id , S_IRUGO, show_sysstatus_data, NULL, PDDF_UCHAR, sizeof(u8), NULL, NULL); +PDDF_DATA_ATTR(board_deph_id , S_IRUGO, show_sysstatus_data, NULL, PDDF_UCHAR, sizeof(u8), NULL, NULL); +PDDF_DATA_ATTR(board_build_id , S_IRUGO, show_sysstatus_data, NULL, PDDF_UCHAR, sizeof(u8), NULL, NULL); +PDDF_DATA_ATTR(cpld1_major_ver, S_IRUGO, show_sysstatus_data, NULL, PDDF_UCHAR, sizeof(u8), NULL, NULL); +PDDF_DATA_ATTR(cpld1_minor_ver, S_IRUGO, show_sysstatus_data, NULL, PDDF_UCHAR, sizeof(u8), NULL, NULL); +PDDF_DATA_ATTR(cpld1_build , S_IRUGO, show_sysstatus_data, NULL, PDDF_UCHAR, sizeof(u8), NULL, NULL); +PDDF_DATA_ATTR(cpld2_major_ver, S_IRUGO, show_sysstatus_data, NULL, PDDF_UCHAR, sizeof(u8), NULL, NULL); +PDDF_DATA_ATTR(cpld2_minor_ver, S_IRUGO, show_sysstatus_data, NULL, PDDF_UCHAR, sizeof(u8), NULL, NULL); +PDDF_DATA_ATTR(cpld2_build , S_IRUGO, show_sysstatus_data, NULL, PDDF_UCHAR, sizeof(u8), NULL, NULL); +PDDF_DATA_ATTR(psu_status , S_IRUGO, show_sysstatus_data, NULL, PDDF_UCHAR, sizeof(u8), NULL, NULL); +PDDF_DATA_ATTR(system_led_psu , S_IRUGO, show_sysstatus_data, NULL, PDDF_UCHAR, sizeof(u8), NULL, NULL); +PDDF_DATA_ATTR(system_led_sys , S_IWUSR|S_IRUGO, show_sysstatus_data, store_sysstatus_data, PDDF_UCHAR, sizeof(u8), NULL, NULL); +PDDF_DATA_ATTR(system_led_sync, S_IRUGO, show_sysstatus_data, NULL, PDDF_UCHAR, sizeof(u8), NULL, NULL); +PDDF_DATA_ATTR(system_led_fan , S_IRUGO, show_sysstatus_data, NULL, PDDF_UCHAR, sizeof(u8), NULL, NULL); +PDDF_DATA_ATTR(system_led_id , S_IWUSR|S_IRUGO, show_sysstatus_data, store_sysstatus_data, PDDF_UCHAR, sizeof(u8), NULL, NULL); + +static struct attribute *sysstatus_data_attributes[] = { + &attr_board_sku_id.dev_attr.attr, + &attr_board_hw_id.dev_attr.attr, + &attr_board_deph_id.dev_attr.attr, + &attr_board_build_id.dev_attr.attr, + &attr_cpld1_major_ver.dev_attr.attr, + &attr_cpld1_minor_ver.dev_attr.attr, + &attr_cpld1_build.dev_attr.attr, + &attr_cpld2_major_ver.dev_attr.attr, + &attr_cpld2_minor_ver.dev_attr.attr, + &attr_cpld2_build.dev_attr.attr, + &attr_psu_status.dev_attr.attr, + &attr_system_led_psu.dev_attr.attr, + &attr_system_led_sys.dev_attr.attr, + &attr_system_led_sync.dev_attr.attr, + &attr_system_led_fan.dev_attr.attr, + &attr_system_led_id.dev_attr.attr, + NULL +}; + + +static const struct attribute_group pddf_sysstatus_addr_group = { + .attrs = sysstatus_addr_attributes, +}; + + +static const struct attribute_group pddf_sysstatus_data_group = { + .attrs = sysstatus_data_attributes, +}; + + +static struct kobject *sysstatus_addr_kobj; +static struct kobject *sysstatus_data_kobj; + + + +ssize_t show_sysstatus_data(struct device *dev, struct device_attribute *da, char *buf) +{ + + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + + SYSSTATUS_DATA *data = &sysstatus_data; + struct SYSSTATUS_ADDR_ATTR *sysstatus_addr_attrs = NULL; + int i, status ; + + + for (i=0;isysstatus_addr_attrs[i].aname, attr->dev_attr.attr.name) == 0 ) + { + sysstatus_addr_attrs = &data->sysstatus_addr_attrs[i]; + + } + } + + if (sysstatus_addr_attrs==NULL ) + { + printk(KERN_DEBUG "%s is not supported attribute for this client\n",data->sysstatus_addr_attrs[i].aname); + status = 0; + } + else + { + status = board_i2c_cpld_read( sysstatus_addr_attrs->devaddr, sysstatus_addr_attrs->offset); + } + + return sprintf(buf, "0x%x\n", (status&sysstatus_addr_attrs->mask)); + +} + +ssize_t store_sysstatus_data(struct device *dev, struct device_attribute *da, const char *buf, size_t count) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + + SYSSTATUS_DATA *data = &sysstatus_data; + struct SYSSTATUS_ADDR_ATTR *sysstatus_addr_attrs = NULL; + int i, status ; + u8 reg_val; + + for (i=0;isysstatus_addr_attrs[i].aname, attr->dev_attr.attr.name) == 0 ) + { + sysstatus_addr_attrs = &data->sysstatus_addr_attrs[i]; + } + } + + if (sysstatus_addr_attrs==NULL) + { + printk(KERN_DEBUG "%s is not supported attribute for this client\n",data->sysstatus_addr_attrs[i].aname); + return -EINVAL; + } + else + { + if (kstrtou8(buf, 0, ®_val) < 0) + return -EINVAL; + + status = board_i2c_cpld_write(sysstatus_addr_attrs->devaddr, sysstatus_addr_attrs->offset, reg_val); + + if (status!=0) + { + printk(KERN_DEBUG "store_sysstatus_data() %s failed, status=%d\n",data->sysstatus_addr_attrs[i].aname, status); + return status; + } + } + + return count; +} + + + +static ssize_t do_attr_operation(struct device *dev, struct device_attribute *da, const char *buf, size_t count) +{ + PDDF_ATTR *ptr = (PDDF_ATTR *)da; + SYSSTATUS_DATA *pdata = (SYSSTATUS_DATA *)(ptr->addr); + + pdata->sysstatus_addr_attrs[pdata->len] = pdata->sysstatus_addr_attr; + pdata->len++; + pddf_dbg(SYSSTATUS, KERN_ERR "%s: Populating the data for %s\n", __FUNCTION__, pdata->sysstatus_addr_attr.aname); + +#ifdef __STDC_LIB_EXT1__ + memset_s(&pdata->sysstatus_addr_attr, sizeof(pdata->sysstatus_addr_attr, 0, sizeof(pdata->sysstatus_addr_attr)); +#else + memset(&pdata->sysstatus_addr_attr, 0, sizeof(pdata->sysstatus_addr_attr)); +#endif + + return count; +} + + + + +int __init sysstatus_data_init(void) +{ + struct kobject *device_kobj; + int ret = 0; + + + pddf_dbg(SYSSTATUS, "PDDF SYSSTATUS MODULE.. init\n"); + + device_kobj = get_device_i2c_kobj(); + if(!device_kobj) + return -ENOMEM; + + sysstatus_addr_kobj = kobject_create_and_add("sysstatus", device_kobj); + if(!sysstatus_addr_kobj) + return -ENOMEM; + + sysstatus_data_kobj = kobject_create_and_add("sysstatus_data", sysstatus_addr_kobj); + if(!sysstatus_data_kobj) + return -ENOMEM; + + + ret = sysfs_create_group(sysstatus_addr_kobj, &pddf_sysstatus_addr_group); + if (ret) + { + kobject_put(sysstatus_addr_kobj); + return ret; + } + + ret = sysfs_create_group(sysstatus_data_kobj, &pddf_sysstatus_data_group); + if (ret) + { + sysfs_remove_group(sysstatus_addr_kobj, &pddf_sysstatus_addr_group); + kobject_put(sysstatus_data_kobj); + kobject_put(sysstatus_addr_kobj); + return ret; + } + + + return ret; +} + +void __exit sysstatus_data_exit(void) +{ + pddf_dbg(SYSSTATUS, "PDDF SYSSTATUS MODULE.. exit\n"); + sysfs_remove_group(sysstatus_data_kobj, &pddf_sysstatus_data_group); + sysfs_remove_group(sysstatus_addr_kobj, &pddf_sysstatus_addr_group); + kobject_put(sysstatus_data_kobj); + kobject_put(sysstatus_addr_kobj); + pddf_dbg(SYSSTATUS, KERN_ERR "%s: Removed the kobjects for 'SYSSTATUS'\n",__FUNCTION__); + return; +} + +module_init(sysstatus_data_init); +module_exit(sysstatus_data_exit); + +MODULE_AUTHOR("Broadcom"); +MODULE_DESCRIPTION("SYSSTATUS platform data"); +MODULE_LICENSE("GPL"); diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/modules/x86-64-ufispace-s7801-54xs-cpld.c b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/modules/x86-64-ufispace-s7801-54xs-cpld.c new file mode 100644 index 000000000000..0cefcb8aac5f --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/modules/x86-64-ufispace-s7801-54xs-cpld.c @@ -0,0 +1,1512 @@ +/* + * A i2c cpld driver for the ufispace_s7801_54xs + * + * Copyright (C) 2017-2022 UfiSpace Technology Corporation. + * Jason Tsai + * + * Based on ad7414.c + * Copyright 2006 Stefan Roese , DENX Software Engineering + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "x86-64-ufispace-s7801-54xs-cpld.h" + +#ifdef DEBUG +#define DEBUG_PRINT(fmt, args...) \ + printk(KERN_INFO "%s:%s[%d]: " fmt "\r\n", \ + __FILE__, __func__, __LINE__, ##args) +#else +#define DEBUG_PRINT(fmt, args...) +#endif + +#define BSP_LOG_R(fmt, args...) \ + _bsp_log (LOG_READ, KERN_INFO "%s:%s[%d]: " fmt "\r\n", \ + __FILE__, __func__, __LINE__, ##args) +#define BSP_LOG_W(fmt, args...) \ + _bsp_log (LOG_WRITE, KERN_INFO "%s:%s[%d]: " fmt "\r\n", \ + __FILE__, __func__, __LINE__, ##args) + +#define I2C_READ_BYTE_DATA(ret, lock, i2c_client, reg) \ +{ \ + mutex_lock(lock); \ + ret = i2c_smbus_read_byte_data(i2c_client, reg); \ + mutex_unlock(lock); \ + BSP_LOG_R("cpld[%d], reg=0x%03x, reg_val=0x%02x", data->index, reg, ret); \ +} + +#define I2C_WRITE_BYTE_DATA(ret, lock, i2c_client, reg, val) \ +{ \ + mutex_lock(lock); \ + ret = i2c_smbus_write_byte_data(i2c_client, reg, val); \ + mutex_unlock(lock); \ + BSP_LOG_W("cpld[%d], reg=0x%03x, reg_val=0x%02x", data->index, reg, val); \ +} + +#define _SENSOR_DEVICE_ATTR_RO(_name, _func, _index) \ + SENSOR_DEVICE_ATTR(_name, S_IRUGO, read_##_func, NULL, _index) + +#define _SENSOR_DEVICE_ATTR_WO(_name, _func, _index) \ + SENSOR_DEVICE_ATTR(_name, S_IWUSR, NULL, write_##_func, _index) + +#define _SENSOR_DEVICE_ATTR_RW(_name, _func, _index) \ + SENSOR_DEVICE_ATTR(_name, S_IRUGO | S_IWUSR, read_##_func, write_##_func, _index) + +#define _DEVICE_ATTR(_name) \ + &sensor_dev_attr_##_name.dev_attr.attr + +#define I2C_RW_RETRY_COUNT 3 +#define I2C_RW_RETRY_INTERVAL 60 + +/* CPLD sysfs attributes index */ +enum cpld_sysfs_attributes { + //CPLD 1 + + CPLD_BOARD_ID_0, + CPLD_BOARD_ID_1, + CPLD_ID, + CPLD_CHIP, + CPLD_SKU_EXT, + + CPLD_MAJOR_VER, + CPLD_MINOR_VER, + CPLD_BUILD_VER, + CPLD_VERSION_H, + + CPLD_MAC_INTR, + CPLD_HWM_INTR, + CPLD_CPLD2_INTR, + CPLD_NTM_INTR, + CPLD_FAN_PSU_INTR, + CPLD_SFP_IOEXP_INTR, + CPLD_CPU_NMI_INTR, + CPLD_PTP_INTR, + CPLD_SYSTEM_INTR, + + CPLD_MAC_MASK, + CPLD_HWM_MASK, + CPLD_CPLD2_MASK, + CPLD_NTM_MASK, + CPLD_FAN_PSU_MASK, + CPLD_SFP_IOEXP_MASK, + CPLD_CPU_NMI_MASK, + CPLD_PTP_MASK, + CPLD_SYSTEM_MASK, + + CPLD_MAC_EVT, + CPLD_HWM_EVT, + CPLD_CPLD2_EVT, + CPLD_NTM_EVT, + CPLD_FAN_PSU_EVT, + CPLD_SFP_IOEXP_EVT, + CPLD_CPU_NMI_EVT, + CPLD_PTP_EVT, + + CPLD_EVT_CTRL, + + CPLD_MAC_RESET, + CPLD_SYSTEM_RESET, + CPLD_BMC_NTM_RESET, + CPLD_USB_RESET, + CPLD_I2C_MUX_RESET, + CPLD_I2C_MUX_RESET_2, + CPLD_MISC_RESET, + + CPLD_BRD_PRESENT, + CPLD_PSU_STATUS, + CPLD_SYSTEM_PWR, + CPLD_MAC_SYNCE, + CPLD_MAC_AVS, + CPLD_SYSTEM_STATUS, + CPLD_FAN_PRESENT, + CPLD_WATCHDOG, + CPLD_BOOT_SELECT, + CPLD_MUX_CTRL, + CPLD_MISC_CTRL_1, + CPLD_MISC_CTRL_2, + CPLD_TIMING_CTRL, + + CPLD_MAC_TEMP, + + CPLD_SYSTEM_LED_SYNC, + CPLD_SYSTEM_LED_SYS, + CPLD_SYSTEM_LED_FAN, + CPLD_SYSTEM_LED_PSU_0, + CPLD_SYSTEM_LED_PSU_1, + CPLD_SYSTEM_LED_ID, + + DBG_CPLD_MAC_INTR, + DBG_CPLD_HWM_INTR, + DBG_CPLD_CPLD2_INTR, + DBG_CPLD_NTM_INTR, + DBG_CPLD_FAN_PSU_INTR, + DBG_CPLD_SFP_IOEXP_INTR, + DBG_CPLD_PTP_INTR, + + //CPLD 2 + + //interrupt status + CPLD_SFP_INTR_PRESENT_0_7, + CPLD_SFP_INTR_PRESENT_8_15, + CPLD_SFP_INTR_PRESENT_16_23, + CPLD_SFP_INTR_PRESENT_24_31, + CPLD_SFP_INTR_PRESENT_32_39, + CPLD_SFP_INTR_PRESENT_40_47, + CPLD_QSFP_INTR_PRESENT_48_53, + CPLD_QSFP_INTR_PORT_48_53, + + //interrupt mask + CPLD_SFP_MASK_PRESENT_0_7, + CPLD_SFP_MASK_PRESENT_8_15, + CPLD_SFP_MASK_PRESENT_16_23, + CPLD_SFP_MASK_PRESENT_24_31, + CPLD_SFP_MASK_PRESENT_32_39, + CPLD_SFP_MASK_PRESENT_40_47, + CPLD_QSFP_MASK_PRESENT_48_53, + CPLD_QSFP_MASK_PORT_48_53, + + //interrupt event + CPLD_SFP_EVT_PRESENT_0_7, + CPLD_SFP_EVT_PRESENT_8_15, + CPLD_SFP_EVT_PRESENT_16_23, + CPLD_SFP_EVT_PRESENT_24_31, + CPLD_SFP_EVT_PRESENT_32_39, + CPLD_SFP_EVT_PRESENT_40_47, + CPLD_QSFP_EVT_PRESENT_48_53, + CPLD_QSFP_EVT_PORT_48_53, + + CPLD_SFP_INTR_RX_LOS_0_7, + CPLD_SFP_INTR_RX_LOS_8_15, + CPLD_SFP_INTR_RX_LOS_16_23, + CPLD_SFP_INTR_RX_LOS_24_31, + CPLD_SFP_INTR_RX_LOS_32_39, + CPLD_SFP_INTR_RX_LOS_40_47, + + CPLD_SFP_INTR_TX_FAULT_0_7, + CPLD_SFP_INTR_TX_FAULT_8_15, + CPLD_SFP_INTR_TX_FAULT_16_23, + CPLD_SFP_INTR_TX_FAULT_24_31, + CPLD_SFP_INTR_TX_FAULT_32_39, + CPLD_SFP_INTR_TX_FAULT_40_47, + + CPLD_SFP_MASK_RX_LOS_0_7, + CPLD_SFP_MASK_RX_LOS_8_15, + CPLD_SFP_MASK_RX_LOS_16_23, + CPLD_SFP_MASK_RX_LOS_24_31, + CPLD_SFP_MASK_RX_LOS_32_39, + CPLD_SFP_MASK_RX_LOS_40_47, + + CPLD_SFP_MASK_TX_FAULT_0_7, + CPLD_SFP_MASK_TX_FAULT_8_15, + CPLD_SFP_MASK_TX_FAULT_16_23, + CPLD_SFP_MASK_TX_FAULT_24_31, + CPLD_SFP_MASK_TX_FAULT_32_39, + CPLD_SFP_MASK_TX_FAULT_40_47, + + CPLD_SFP_EVT_RX_LOS_0_7, + CPLD_SFP_EVT_RX_LOS_8_15, + CPLD_SFP_EVT_RX_LOS_16_23, + CPLD_SFP_EVT_RX_LOS_24_31, + CPLD_SFP_EVT_RX_LOS_32_39, + CPLD_SFP_EVT_RX_LOS_40_47, + + CPLD_SFP_EVT_TX_FAULT_0_7, + CPLD_SFP_EVT_TX_FAULT_8_15, + CPLD_SFP_EVT_TX_FAULT_16_23, + CPLD_SFP_EVT_TX_FAULT_24_31, + CPLD_SFP_EVT_TX_FAULT_32_39, + CPLD_SFP_EVT_TX_FAULT_40_47, + + CPLD_SFP_TX_DISABLE_0_7, + CPLD_SFP_TX_DISABLE_8_15, + CPLD_SFP_TX_DISABLE_16_23, + CPLD_SFP_TX_DISABLE_24_31, + CPLD_SFP_TX_DISABLE_32_39, + CPLD_SFP_TX_DISABLE_40_47, + + CPLD_QSFP_RESET_48_53, + CPLD_QSFP_LPMODE_48_53, + + //debug interrupt status + DBG_CPLD_SFP_INTR_PRESENT_0_7, + DBG_CPLD_SFP_INTR_PRESENT_8_15, + DBG_CPLD_SFP_INTR_PRESENT_16_23, + DBG_CPLD_SFP_INTR_PRESENT_24_31, + DBG_CPLD_SFP_INTR_PRESENT_32_39, + DBG_CPLD_SFP_INTR_PRESENT_40_47, + DBG_CPLD_QSFP_INTR_PRESENT_48_53, + DBG_CPLD_QSFP_INTR_PORT_48_53, + + //debug interrupt mask + DBG_CPLD_SFP_INTR_RX_LOS_0_7, + DBG_CPLD_SFP_INTR_RX_LOS_8_15, + DBG_CPLD_SFP_INTR_RX_LOS_16_23, + DBG_CPLD_SFP_INTR_RX_LOS_24_31, + DBG_CPLD_SFP_INTR_RX_LOS_32_39, + DBG_CPLD_SFP_INTR_RX_LOS_40_47, + + DBG_CPLD_SFP_INTR_TX_FAULT_0_7, + DBG_CPLD_SFP_INTR_TX_FAULT_8_15, + DBG_CPLD_SFP_INTR_TX_FAULT_16_23, + DBG_CPLD_SFP_INTR_TX_FAULT_24_31, + DBG_CPLD_SFP_INTR_TX_FAULT_32_39, + DBG_CPLD_SFP_INTR_TX_FAULT_40_47, + + //BSP DEBUG + BSP_DEBUG +}; + +enum bsp_log_types { + LOG_NONE, + LOG_RW, + LOG_READ, + LOG_WRITE +}; + +enum bsp_log_ctrl { + LOG_DISABLE, + LOG_ENABLE +}; + +/* CPLD sysfs attributes hook functions */ +static ssize_t read_cpld_callback(struct device *dev, + struct device_attribute *da, char *buf); +static ssize_t write_cpld_callback(struct device *dev, + struct device_attribute *da, const char *buf, size_t count); +static u8 _read_cpld_reg(struct device *dev, u8 reg, u8 mask); +static ssize_t read_cpld_reg(struct device *dev, char *buf, u8 reg, u8 mask); +static ssize_t write_cpld_reg(struct device *dev, const char *buf, size_t count, u8 reg, u8 mask); +static ssize_t read_bsp(char *buf, char *str); +static ssize_t write_bsp(const char *buf, char *str, size_t str_len, size_t count); +static ssize_t read_bsp_callback(struct device *dev, + struct device_attribute *da, char *buf); +static ssize_t write_bsp_callback(struct device *dev, + struct device_attribute *da, const char *buf, size_t count); +static ssize_t read_cpld_version_h(struct device *dev, + struct device_attribute *da, + char *buf); + +static LIST_HEAD(cpld_client_list); /* client list for cpld */ +static struct mutex list_lock; /* mutex for client list */ + +struct cpld_client_node { + struct i2c_client *client; + struct list_head list; +}; + +struct cpld_data { + int index; /* CPLD index */ + struct mutex access_lock; /* mutex for cpld access */ + u8 access_reg; /* register to access */ +}; + +typedef struct sysfs_info_s +{ + u8 reg; + u8 mask; + u8 permission; +} sysfs_info_t; + +static sysfs_info_t sysfs_info[] = { + //CPLD 1 + + [CPLD_BOARD_ID_0] = {CPLD_BOARD_ID_0_REG, MASK_ALL, PERM_R}, + [CPLD_BOARD_ID_1] = {CPLD_BOARD_ID_1_REG, MASK_ALL, PERM_R}, + [CPLD_ID] = {CPLD_ID_REG, MASK_ALL, PERM_R}, + [CPLD_CHIP] = {CPLD_CHIP_REG, MASK_ALL, PERM_R}, + [CPLD_SKU_EXT] = {CPLD_SKU_EXT_REG, MASK_ALL, PERM_R}, + + [CPLD_MAJOR_VER] = {CPLD_VERSION_REG, MASK_CPLD_MAJOR_VER, PERM_R}, + [CPLD_MINOR_VER] = {CPLD_VERSION_REG, MASK_CPLD_MINOR_VER, PERM_R}, + [CPLD_BUILD_VER] = {CPLD_BUILD_REG, MASK_ALL, PERM_R}, + [CPLD_VERSION_H] = {CPLD_VERSION_REG, MASK_ALL, PERM_R}, + + [CPLD_MAC_INTR] = {CPLD_MAC_INTR_REG, MASK_ALL, PERM_R}, + [CPLD_HWM_INTR] = {CPLD_HWM_INTR_REG, MASK_ALL, PERM_R}, + [CPLD_CPLD2_INTR] = {CPLD_CPLD2_INTR_REG, MASK_ALL, PERM_R}, + [CPLD_NTM_INTR] = {CPLD_NTM_INTR_REG, MASK_ALL, PERM_R}, + [CPLD_FAN_PSU_INTR] = {CPLD_FAN_PSU_INTR_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_IOEXP_INTR] = {CPLD_SFP_IOEXP_INTR_REG, MASK_ALL, PERM_R}, + [CPLD_CPU_NMI_INTR] = {CPLD_CPU_NMI_INTR_REG, MASK_ALL, PERM_R}, + [CPLD_PTP_INTR] = {CPLD_PTP_INTR_REG, MASK_ALL, PERM_R}, + [CPLD_SYSTEM_INTR] = {CPLD_SYSTEM_INTR_REG, MASK_ALL, PERM_R}, + + [CPLD_MAC_MASK] = {CPLD_MAC_MASK_REG, MASK_ALL, PERM_RW}, + [CPLD_HWM_MASK] = {CPLD_HWM_MASK_REG, MASK_ALL, PERM_RW}, + [CPLD_CPLD2_MASK] = {CPLD_CPLD2_MASK_REG, MASK_ALL, PERM_RW}, + [CPLD_NTM_MASK] = {CPLD_NTM_MASK_REG, MASK_ALL, PERM_RW}, + [CPLD_FAN_PSU_MASK] = {CPLD_FAN_PSU_MASK_REG, MASK_ALL, PERM_RW}, + [CPLD_SFP_IOEXP_MASK] = {CPLD_SFP_IOEXP_MASK_REG, MASK_ALL, PERM_RW}, + [CPLD_CPU_NMI_MASK] = {CPLD_CPU_NMI_MASK_REG, MASK_ALL, PERM_RW}, + [CPLD_PTP_MASK] = {CPLD_PTP_MASK_REG, MASK_ALL, PERM_RW}, + [CPLD_SYSTEM_MASK] = {CPLD_SYSTEM_MASK_REG, MASK_ALL, PERM_RW}, + + [CPLD_MAC_EVT] = {CPLD_MAC_EVT_REG, MASK_ALL, PERM_R}, + [CPLD_HWM_EVT] = {CPLD_HWM_EVT_REG, MASK_ALL, PERM_R}, + [CPLD_CPLD2_EVT] = {CPLD_CPLD2_EVT_REG, MASK_ALL, PERM_R}, + [CPLD_NTM_EVT] = {CPLD_NTM_EVT_REG, MASK_ALL, PERM_R}, + [CPLD_FAN_PSU_EVT] = {CPLD_FAN_PSU_EVT_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_IOEXP_EVT] = {CPLD_SFP_IOEXP_EVT_REG, MASK_ALL, PERM_R}, + [CPLD_CPU_NMI_EVT] = {CPLD_CPU_NMI_EVT_REG, MASK_ALL, PERM_R}, + [CPLD_PTP_EVT] = {CPLD_PTP_EVT_REG, MASK_ALL, PERM_R}, + + [CPLD_EVT_CTRL] = {CPLD_EVT_CTRL_REG, MASK_ALL, PERM_RW}, + + [CPLD_MAC_RESET] = {CPLD_MAC_RESET_REG, MASK_ALL, PERM_RW}, + [CPLD_SYSTEM_RESET] = {CPLD_SYSTEM_RESET_REG, MASK_ALL, PERM_RW}, + [CPLD_BMC_NTM_RESET] = {CPLD_BMC_NTM_RESET_REG, MASK_ALL, PERM_RW}, + [CPLD_USB_RESET] = {CPLD_USB_RESET_REG, MASK_ALL, PERM_RW}, + [CPLD_I2C_MUX_RESET] = {CPLD_I2C_MUX_RESET_REG, MASK_ALL, PERM_RW}, + [CPLD_I2C_MUX_RESET_2] = {CPLD_I2C_MUX_RESET_2_REG, MASK_ALL, PERM_RW}, + [CPLD_MISC_RESET] = {CPLD_MISC_RESET_REG, MASK_ALL, PERM_RW}, + + [CPLD_BRD_PRESENT] = {CPLD_BRD_PRESENT_REG, MASK_ALL, PERM_R}, + [CPLD_PSU_STATUS] = {CPLD_PSU_STATUS_REG, MASK_ALL, PERM_R}, + [CPLD_SYSTEM_PWR] = {CPLD_SYSTEM_PWR_REG, MASK_ALL, PERM_R}, + [CPLD_MAC_SYNCE] = {CPLD_MAC_SYNCE_REG, MASK_ALL, PERM_R}, + [CPLD_MAC_AVS] = {CPLD_MAC_AVS_REG, MASK_ALL, PERM_R}, + [CPLD_SYSTEM_STATUS] = {CPLD_SYSTEM_STATUS_REG, MASK_ALL, PERM_R}, + [CPLD_FAN_PRESENT] = {CPLD_FAN_PRESENT_REG, MASK_ALL, PERM_R}, + [CPLD_WATCHDOG] = {CPLD_WATCHDOG_REG, MASK_ALL, PERM_RW}, + [CPLD_BOOT_SELECT] = {CPLD_BOOT_SELECT_REG, MASK_ALL, PERM_RW}, + [CPLD_MUX_CTRL] = {CPLD_MUX_CTRL_REG, MASK_ALL, PERM_RW}, + [CPLD_MISC_CTRL_1] = {CPLD_MISC_CTRL_1_REG, MASK_ALL, PERM_RW}, + [CPLD_MISC_CTRL_2] = {CPLD_MISC_CTRL_2_REG, MASK_ALL, PERM_RW}, + [CPLD_TIMING_CTRL] = {CPLD_TIMING_CTRL_REG, MASK_ALL, PERM_RW}, + + [CPLD_MAC_TEMP] = {CPLD_MAC_TEMP_REG, MASK_ALL, PERM_R}, + + [CPLD_SYSTEM_LED_SYNC] = {CPLD_SYSTEM_LED_SYNC_REG, CPLD_SYSTEM_LED_SYNC_MASK, PERM_RW}, + [CPLD_SYSTEM_LED_SYS] = {CPLD_SYSTEM_LED_SYS_REG, CPLD_SYSTEM_LED_SYS_MASK, PERM_RW}, + [CPLD_SYSTEM_LED_FAN] = {CPLD_SYSTEM_LED_FAN_REG, CPLD_SYSTEM_LED_FAN_MASK, PERM_RW}, + [CPLD_SYSTEM_LED_PSU_0] = {CPLD_SYSTEM_LED_PSU_REG, CPLD_SYSTEM_LED_PSU_0_MASK, PERM_RW}, + [CPLD_SYSTEM_LED_PSU_1] = {CPLD_SYSTEM_LED_PSU_REG, CPLD_SYSTEM_LED_PSU_1_MASK, PERM_RW}, + [CPLD_SYSTEM_LED_ID] = {CPLD_SYSTEM_LED_ID_REG, CPLD_SYSTEM_LED_ID_MASK, PERM_RW}, + + [DBG_CPLD_MAC_INTR] = {DBG_CPLD_MAC_INTR_REG, MASK_ALL, PERM_RW}, + [DBG_CPLD_HWM_INTR] = {DBG_CPLD_HWM_INTR_REG, MASK_ALL, PERM_RW}, + [DBG_CPLD_CPLD2_INTR] = {DBG_CPLD_CPLD2_INTR_REG, MASK_ALL, PERM_RW}, + [DBG_CPLD_NTM_INTR] = {DBG_CPLD_NTM_INTR_REG, MASK_ALL, PERM_RW}, + [DBG_CPLD_FAN_PSU_INTR] = {DBG_CPLD_FAN_PSU_INTR_REG, MASK_ALL, PERM_RW}, + [DBG_CPLD_SFP_IOEXP_INTR] = {DBG_CPLD_SFP_IOEXP_INTR_REG, MASK_ALL, PERM_RW}, + [DBG_CPLD_PTP_INTR] = {DBG_CPLD_PTP_INTR_REG, MASK_ALL, PERM_RW}, + + //CPLD 2 + + //interrupt status + [CPLD_SFP_INTR_PRESENT_0_7] = {CPLD_SFP_INTR_PRESENT_0_7_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_INTR_PRESENT_8_15] = {CPLD_SFP_INTR_PRESENT_8_15_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_INTR_PRESENT_16_23] = {CPLD_SFP_INTR_PRESENT_16_23_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_INTR_PRESENT_24_31] = {CPLD_SFP_INTR_PRESENT_24_31_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_INTR_PRESENT_32_39] = {CPLD_SFP_INTR_PRESENT_32_39_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_INTR_PRESENT_40_47] = {CPLD_SFP_INTR_PRESENT_40_47_REG, MASK_ALL, PERM_R}, + [CPLD_QSFP_INTR_PRESENT_48_53] = {CPLD_QSFP_INTR_PRESENT_48_53_REG, MASK_ALL, PERM_R}, + [CPLD_QSFP_INTR_PORT_48_53] = {CPLD_QSFP_INTR_PORT_48_53_REG, MASK_ALL, PERM_R}, + + //interrupt mask + [CPLD_SFP_MASK_PRESENT_0_7] = {CPLD_SFP_MASK_PRESENT_0_7_REG, MASK_ALL, PERM_RW}, + [CPLD_SFP_MASK_PRESENT_8_15] = {CPLD_SFP_MASK_PRESENT_8_15_REG, MASK_ALL, PERM_RW}, + [CPLD_SFP_MASK_PRESENT_16_23] = {CPLD_SFP_MASK_PRESENT_16_23_REG, MASK_ALL, PERM_RW}, + [CPLD_SFP_MASK_PRESENT_24_31] = {CPLD_SFP_MASK_PRESENT_24_31_REG, MASK_ALL, PERM_RW}, + [CPLD_SFP_MASK_PRESENT_32_39] = {CPLD_SFP_MASK_PRESENT_32_39_REG, MASK_ALL, PERM_RW}, + [CPLD_SFP_MASK_PRESENT_40_47] = {CPLD_SFP_MASK_PRESENT_40_47_REG, MASK_ALL, PERM_RW}, + [CPLD_QSFP_MASK_PRESENT_48_53] = {CPLD_QSFP_MASK_PRESENT_48_53_REG, MASK_ALL, PERM_RW}, + [CPLD_QSFP_MASK_PORT_48_53] = {CPLD_QSFP_MASK_PORT_48_53_REG, MASK_ALL, PERM_RW}, + + //interrupt event + [CPLD_SFP_EVT_PRESENT_0_7] = {CPLD_SFP_EVT_PRESENT_0_7_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_EVT_PRESENT_8_15] = {CPLD_SFP_EVT_PRESENT_8_15_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_EVT_PRESENT_16_23] = {CPLD_SFP_EVT_PRESENT_16_23_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_EVT_PRESENT_24_31] = {CPLD_SFP_EVT_PRESENT_24_31_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_EVT_PRESENT_32_39] = {CPLD_SFP_EVT_PRESENT_32_39_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_EVT_PRESENT_40_47] = {CPLD_SFP_EVT_PRESENT_40_47_REG, MASK_ALL, PERM_R}, + [CPLD_QSFP_EVT_PRESENT_48_53] = {CPLD_QSFP_EVT_PRESENT_48_53_REG, MASK_ALL, PERM_R}, + [CPLD_QSFP_EVT_PORT_48_53] = {CPLD_QSFP_EVT_PORT_48_53_REG, MASK_ALL, PERM_R}, + + [CPLD_SFP_INTR_RX_LOS_0_7] = {CPLD_SFP_INTR_RX_LOS_0_7_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_INTR_RX_LOS_8_15] = {CPLD_SFP_INTR_RX_LOS_8_15_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_INTR_RX_LOS_16_23] = {CPLD_SFP_INTR_RX_LOS_16_23_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_INTR_RX_LOS_24_31] = {CPLD_SFP_INTR_RX_LOS_24_31_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_INTR_RX_LOS_32_39] = {CPLD_SFP_INTR_RX_LOS_32_39_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_INTR_RX_LOS_40_47] = {CPLD_SFP_INTR_RX_LOS_40_47_REG, MASK_ALL, PERM_R}, + + [CPLD_SFP_INTR_TX_FAULT_0_7] = {CPLD_SFP_INTR_TX_FAULT_0_7_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_INTR_TX_FAULT_8_15] = {CPLD_SFP_INTR_TX_FAULT_8_15_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_INTR_TX_FAULT_16_23] = {CPLD_SFP_INTR_TX_FAULT_16_23_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_INTR_TX_FAULT_24_31] = {CPLD_SFP_INTR_TX_FAULT_24_31_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_INTR_TX_FAULT_32_39] = {CPLD_SFP_INTR_TX_FAULT_32_39_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_INTR_TX_FAULT_40_47] = {CPLD_SFP_INTR_TX_FAULT_40_47_REG, MASK_ALL, PERM_R}, + + [CPLD_SFP_MASK_RX_LOS_0_7] = {CPLD_SFP_MASK_RX_LOS_0_7_REG, MASK_ALL, PERM_RW}, + [CPLD_SFP_MASK_RX_LOS_8_15] = {CPLD_SFP_MASK_RX_LOS_8_15_REG, MASK_ALL, PERM_RW}, + [CPLD_SFP_MASK_RX_LOS_16_23] = {CPLD_SFP_MASK_RX_LOS_16_23_REG, MASK_ALL, PERM_RW}, + [CPLD_SFP_MASK_RX_LOS_24_31] = {CPLD_SFP_MASK_RX_LOS_24_31_REG, MASK_ALL, PERM_RW}, + [CPLD_SFP_MASK_RX_LOS_32_39] = {CPLD_SFP_MASK_RX_LOS_32_39_REG, MASK_ALL, PERM_RW}, + [CPLD_SFP_MASK_RX_LOS_40_47] = {CPLD_SFP_MASK_RX_LOS_40_47_REG, MASK_ALL, PERM_RW}, + + [CPLD_SFP_MASK_TX_FAULT_0_7] = {CPLD_SFP_MASK_TX_FAULT_0_7_REG, MASK_ALL, PERM_RW}, + [CPLD_SFP_MASK_TX_FAULT_8_15] = {CPLD_SFP_MASK_TX_FAULT_8_15_REG, MASK_ALL, PERM_RW}, + [CPLD_SFP_MASK_TX_FAULT_16_23] = {CPLD_SFP_MASK_TX_FAULT_16_23_REG, MASK_ALL, PERM_RW}, + [CPLD_SFP_MASK_TX_FAULT_24_31] = {CPLD_SFP_MASK_TX_FAULT_24_31_REG, MASK_ALL, PERM_RW}, + [CPLD_SFP_MASK_TX_FAULT_32_39] = {CPLD_SFP_MASK_TX_FAULT_32_39_REG, MASK_ALL, PERM_RW}, + [CPLD_SFP_MASK_TX_FAULT_40_47] = {CPLD_SFP_MASK_TX_FAULT_40_47_REG, MASK_ALL, PERM_RW}, + + [CPLD_SFP_EVT_RX_LOS_0_7] = {CPLD_SFP_EVT_RX_LOS_0_7_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_EVT_RX_LOS_8_15] = {CPLD_SFP_EVT_RX_LOS_8_15_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_EVT_RX_LOS_16_23] = {CPLD_SFP_EVT_RX_LOS_16_23_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_EVT_RX_LOS_24_31] = {CPLD_SFP_EVT_RX_LOS_24_31_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_EVT_RX_LOS_32_39] = {CPLD_SFP_EVT_RX_LOS_32_39_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_EVT_RX_LOS_40_47] = {CPLD_SFP_EVT_RX_LOS_40_47_REG, MASK_ALL, PERM_R}, + + [CPLD_SFP_EVT_TX_FAULT_0_7] = {CPLD_SFP_EVT_TX_FAULT_0_7_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_EVT_TX_FAULT_8_15] = {CPLD_SFP_EVT_TX_FAULT_8_15_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_EVT_TX_FAULT_16_23] = {CPLD_SFP_EVT_TX_FAULT_16_23_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_EVT_TX_FAULT_24_31] = {CPLD_SFP_EVT_TX_FAULT_24_31_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_EVT_TX_FAULT_32_39] = {CPLD_SFP_EVT_TX_FAULT_32_39_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_EVT_TX_FAULT_40_47] = {CPLD_SFP_EVT_TX_FAULT_40_47_REG, MASK_ALL, PERM_R}, + + [CPLD_SFP_TX_DISABLE_0_7] = {CPLD_SFP_TX_DISABLE_0_7_REG, MASK_ALL, PERM_RW}, + [CPLD_SFP_TX_DISABLE_8_15] = {CPLD_SFP_TX_DISABLE_8_15_REG, MASK_ALL, PERM_RW}, + [CPLD_SFP_TX_DISABLE_16_23] = {CPLD_SFP_TX_DISABLE_16_23_REG, MASK_ALL, PERM_RW}, + [CPLD_SFP_TX_DISABLE_24_31] = {CPLD_SFP_TX_DISABLE_24_31_REG, MASK_ALL, PERM_RW}, + [CPLD_SFP_TX_DISABLE_32_39] = {CPLD_SFP_TX_DISABLE_32_39_REG, MASK_ALL, PERM_RW}, + [CPLD_SFP_TX_DISABLE_40_47] = {CPLD_SFP_TX_DISABLE_40_47_REG, MASK_ALL, PERM_RW}, + + [CPLD_QSFP_RESET_48_53] = {CPLD_QSFP_RESET_48_53_REG, MASK_ALL, PERM_RW}, + [CPLD_QSFP_LPMODE_48_53] = {CPLD_QSFP_LPMODE_48_53_REG, MASK_ALL, PERM_RW}, + + //debug interrupt status + [DBG_CPLD_SFP_INTR_PRESENT_0_7] = {DBG_CPLD_SFP_INTR_PRESENT_0_7_REG, MASK_ALL, PERM_R}, + [DBG_CPLD_SFP_INTR_PRESENT_8_15] = {DBG_CPLD_SFP_INTR_PRESENT_8_15_REG, MASK_ALL, PERM_R}, + [DBG_CPLD_SFP_INTR_PRESENT_16_23] = {DBG_CPLD_SFP_INTR_PRESENT_16_23_REG, MASK_ALL, PERM_R}, + [DBG_CPLD_SFP_INTR_PRESENT_24_31] = {DBG_CPLD_SFP_INTR_PRESENT_24_31_REG, MASK_ALL, PERM_R}, + [DBG_CPLD_SFP_INTR_PRESENT_32_39] = {DBG_CPLD_SFP_INTR_PRESENT_32_39_REG, MASK_ALL, PERM_R}, + [DBG_CPLD_SFP_INTR_PRESENT_40_47] = {DBG_CPLD_SFP_INTR_PRESENT_40_47_REG, MASK_ALL, PERM_R}, + [DBG_CPLD_QSFP_INTR_PRESENT_48_53] = {DBG_CPLD_QSFP_INTR_PRESENT_48_53_REG, MASK_ALL, PERM_R}, + [DBG_CPLD_QSFP_INTR_PORT_48_53] = {DBG_CPLD_QSFP_INTR_PORT_48_53_REG, MASK_ALL, PERM_R}, + + //debug interrupt mask + [DBG_CPLD_SFP_INTR_RX_LOS_0_7] = {DBG_CPLD_SFP_INTR_RX_LOS_0_7_REG, MASK_ALL, PERM_R}, + [DBG_CPLD_SFP_INTR_RX_LOS_8_15] = {DBG_CPLD_SFP_INTR_RX_LOS_8_15_REG, MASK_ALL, PERM_R}, + [DBG_CPLD_SFP_INTR_RX_LOS_16_23] = {DBG_CPLD_SFP_INTR_RX_LOS_16_23_REG, MASK_ALL, PERM_R}, + [DBG_CPLD_SFP_INTR_RX_LOS_24_31] = {DBG_CPLD_SFP_INTR_RX_LOS_24_31_REG, MASK_ALL, PERM_R}, + [DBG_CPLD_SFP_INTR_RX_LOS_32_39] = {DBG_CPLD_SFP_INTR_RX_LOS_32_39_REG, MASK_ALL, PERM_R}, + [DBG_CPLD_SFP_INTR_RX_LOS_40_47] = {DBG_CPLD_SFP_INTR_RX_LOS_40_47_REG, MASK_ALL, PERM_R}, + + [DBG_CPLD_SFP_INTR_TX_FAULT_0_7] = {DBG_CPLD_SFP_INTR_TX_FAULT_0_7_REG, MASK_ALL, PERM_R}, + [DBG_CPLD_SFP_INTR_TX_FAULT_8_15] = {DBG_CPLD_SFP_INTR_TX_FAULT_8_15_REG, MASK_ALL, PERM_R}, + [DBG_CPLD_SFP_INTR_TX_FAULT_16_23] = {DBG_CPLD_SFP_INTR_TX_FAULT_16_23_REG, MASK_ALL, PERM_R}, + [DBG_CPLD_SFP_INTR_TX_FAULT_24_31] = {DBG_CPLD_SFP_INTR_TX_FAULT_24_31_REG, MASK_ALL, PERM_R}, + [DBG_CPLD_SFP_INTR_TX_FAULT_32_39] = {DBG_CPLD_SFP_INTR_TX_FAULT_32_39_REG, MASK_ALL, PERM_R}, + [DBG_CPLD_SFP_INTR_TX_FAULT_40_47] = {DBG_CPLD_SFP_INTR_TX_FAULT_40_47_REG, MASK_ALL, PERM_R}, +}; + +/* CPLD device id and data */ +static const struct i2c_device_id cpld_id[] = { + { "s7801_54xs_cpld1", cpld1 }, + { "s7801_54xs_cpld2", cpld2 }, + {} +}; + +char bsp_debug[2]="0"; +u8 enable_log_read=LOG_DISABLE; +u8 enable_log_write=LOG_DISABLE; + +/* Addresses scanned for cpld */ +static const unsigned short cpld_i2c_addr[] = { 0x30, 0x31, I2C_CLIENT_END }; + +/* define all support register access of cpld in attribute */ + +// CPLD common +static _SENSOR_DEVICE_ATTR_RO(cpld_board_id_0, cpld_callback, CPLD_BOARD_ID_0); +static _SENSOR_DEVICE_ATTR_RO(cpld_board_id_1, cpld_callback, CPLD_BOARD_ID_1); +static _SENSOR_DEVICE_ATTR_RO(cpld_id, cpld_callback, CPLD_ID); +static _SENSOR_DEVICE_ATTR_RO(cpld_chip, cpld_callback, CPLD_CHIP); +static _SENSOR_DEVICE_ATTR_RO(cpld_sku_ext, cpld_callback, CPLD_SKU_EXT); + +static _SENSOR_DEVICE_ATTR_RO(cpld_major_ver, cpld_callback, CPLD_MAJOR_VER); +static _SENSOR_DEVICE_ATTR_RO(cpld_minor_ver, cpld_callback, CPLD_MINOR_VER); +static _SENSOR_DEVICE_ATTR_RO(cpld_build_ver, cpld_callback, CPLD_BUILD_VER); +static _SENSOR_DEVICE_ATTR_RO(cpld_version_h, cpld_version_h, CPLD_VERSION_H); + +static _SENSOR_DEVICE_ATTR_RW(cpld_evt_ctrl, cpld_callback, CPLD_EVT_CTRL); + +//CPLD 1 +static _SENSOR_DEVICE_ATTR_RO(cpld_mac_intr, cpld_callback, CPLD_MAC_INTR); +static _SENSOR_DEVICE_ATTR_RO(cpld_hwm_intr, cpld_callback, CPLD_HWM_INTR); +static _SENSOR_DEVICE_ATTR_RO(cpld_cpld2_intr, cpld_callback, CPLD_CPLD2_INTR); +static _SENSOR_DEVICE_ATTR_RO(cpld_ntm_intr, cpld_callback, CPLD_NTM_INTR); +static _SENSOR_DEVICE_ATTR_RO(cpld_fan_psu_intr, cpld_callback, CPLD_FAN_PSU_INTR); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_ioexp_intr, cpld_callback, CPLD_SFP_IOEXP_INTR); +static _SENSOR_DEVICE_ATTR_RO(cpld_cpu_nmi_intr, cpld_callback, CPLD_CPU_NMI_INTR); +static _SENSOR_DEVICE_ATTR_RO(cpld_ptp_intr, cpld_callback, CPLD_PTP_INTR); +static _SENSOR_DEVICE_ATTR_RO(cpld_system_intr, cpld_callback, CPLD_SYSTEM_INTR); + +static _SENSOR_DEVICE_ATTR_RW(cpld_mac_mask, cpld_callback, CPLD_MAC_MASK); +static _SENSOR_DEVICE_ATTR_RW(cpld_hwm_mask, cpld_callback, CPLD_HWM_MASK); +static _SENSOR_DEVICE_ATTR_RW(cpld_cpld2_mask, cpld_callback, CPLD_CPLD2_MASK); +static _SENSOR_DEVICE_ATTR_RW(cpld_ntm_mask, cpld_callback, CPLD_NTM_MASK); +static _SENSOR_DEVICE_ATTR_RW(cpld_fan_psu_mask, cpld_callback, CPLD_FAN_PSU_MASK); +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_ioexp_mask, cpld_callback, CPLD_SFP_IOEXP_MASK); +static _SENSOR_DEVICE_ATTR_RW(cpld_cpu_nmi_mask, cpld_callback, CPLD_CPU_NMI_MASK); +static _SENSOR_DEVICE_ATTR_RW(cpld_ptp_mask, cpld_callback, CPLD_PTP_MASK); +static _SENSOR_DEVICE_ATTR_RW(cpld_system_mask, cpld_callback, CPLD_SYSTEM_MASK); + +static _SENSOR_DEVICE_ATTR_RO(cpld_mac_evt, cpld_callback, CPLD_MAC_EVT); +static _SENSOR_DEVICE_ATTR_RO(cpld_hwm_evt, cpld_callback, CPLD_HWM_EVT); +static _SENSOR_DEVICE_ATTR_RO(cpld_cpld2_evt, cpld_callback, CPLD_CPLD2_EVT); +static _SENSOR_DEVICE_ATTR_RO(cpld_ntm_evt, cpld_callback, CPLD_NTM_EVT); +static _SENSOR_DEVICE_ATTR_RO(cpld_fan_psu_evt, cpld_callback, CPLD_FAN_PSU_EVT); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_ioexp_evt, cpld_callback, CPLD_SFP_IOEXP_EVT); +static _SENSOR_DEVICE_ATTR_RO(cpld_cpu_nmi_evt, cpld_callback, CPLD_CPU_NMI_EVT); +static _SENSOR_DEVICE_ATTR_RO(cpld_ptp_evt, cpld_callback, CPLD_PTP_EVT); + +static _SENSOR_DEVICE_ATTR_RW(cpld_mac_reset, cpld_callback, CPLD_MAC_RESET); +static _SENSOR_DEVICE_ATTR_RW(cpld_system_reset, cpld_callback, CPLD_SYSTEM_RESET); +static _SENSOR_DEVICE_ATTR_RW(cpld_bmc_ntm_reset, cpld_callback, CPLD_BMC_NTM_RESET); +static _SENSOR_DEVICE_ATTR_RW(cpld_usb_reset, cpld_callback, CPLD_USB_RESET); +static _SENSOR_DEVICE_ATTR_RW(cpld_i2c_mux_reset, cpld_callback, CPLD_I2C_MUX_RESET); +static _SENSOR_DEVICE_ATTR_RW(cpld_i2c_mux_reset_2, cpld_callback, CPLD_I2C_MUX_RESET_2); +static _SENSOR_DEVICE_ATTR_RW(cpld_misc_reset, cpld_callback, CPLD_MISC_RESET); + +static _SENSOR_DEVICE_ATTR_RO(cpld_psu_status, cpld_callback, CPLD_PSU_STATUS); +static _SENSOR_DEVICE_ATTR_RO(cpld_mac_synce, cpld_callback, CPLD_MAC_SYNCE); +static _SENSOR_DEVICE_ATTR_RO(cpld_fan_present, cpld_callback, CPLD_FAN_PRESENT); +static _SENSOR_DEVICE_ATTR_RW(cpld_mux_ctrl, cpld_callback, CPLD_MUX_CTRL); + +static _SENSOR_DEVICE_ATTR_RW(cpld_system_led_sync, cpld_callback, CPLD_SYSTEM_LED_SYNC); +static _SENSOR_DEVICE_ATTR_RW(cpld_system_led_sys, cpld_callback, CPLD_SYSTEM_LED_SYS); +static _SENSOR_DEVICE_ATTR_RW(cpld_system_led_fan, cpld_callback, CPLD_SYSTEM_LED_FAN); +static _SENSOR_DEVICE_ATTR_RW(cpld_system_led_psu_0, cpld_callback, CPLD_SYSTEM_LED_PSU_0); +static _SENSOR_DEVICE_ATTR_RW(cpld_system_led_psu_1, cpld_callback, CPLD_SYSTEM_LED_PSU_1); +static _SENSOR_DEVICE_ATTR_RW(cpld_system_led_id, cpld_callback, CPLD_SYSTEM_LED_ID); + +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_mac_intr, cpld_callback, DBG_CPLD_MAC_INTR); +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_hwm_intr, cpld_callback, DBG_CPLD_HWM_INTR); +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_cpld2_intr, cpld_callback, DBG_CPLD_CPLD2_INTR); +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_ntm_intr, cpld_callback, DBG_CPLD_NTM_INTR); +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_fan_psu_intr, cpld_callback, DBG_CPLD_FAN_PSU_INTR); +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_sfp_ioexp_intr, cpld_callback, DBG_CPLD_SFP_IOEXP_INTR); +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_ptp_intr, cpld_callback, DBG_CPLD_PTP_INTR); + +//CPLD 2 +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_intr_present_0_7, cpld_callback, CPLD_SFP_INTR_PRESENT_0_7); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_intr_present_8_15, cpld_callback, CPLD_SFP_INTR_PRESENT_8_15); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_intr_present_16_23, cpld_callback, CPLD_SFP_INTR_PRESENT_16_23); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_intr_present_24_31, cpld_callback, CPLD_SFP_INTR_PRESENT_24_31); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_intr_present_32_39, cpld_callback, CPLD_SFP_INTR_PRESENT_32_39); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_intr_present_40_47, cpld_callback, CPLD_SFP_INTR_PRESENT_40_47); + +static _SENSOR_DEVICE_ATTR_RO(cpld_qsfp_intr_present_48_53, cpld_callback, CPLD_QSFP_INTR_PRESENT_48_53); +static _SENSOR_DEVICE_ATTR_RO(cpld_qsfp_intr_port_48_53, cpld_callback, CPLD_QSFP_INTR_PORT_48_53); + +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_mask_present_0_7, cpld_callback, CPLD_SFP_MASK_PRESENT_0_7); +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_mask_present_8_15, cpld_callback, CPLD_SFP_MASK_PRESENT_8_15); +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_mask_present_16_23, cpld_callback, CPLD_SFP_MASK_PRESENT_16_23); +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_mask_present_24_31, cpld_callback, CPLD_SFP_MASK_PRESENT_24_31); +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_mask_present_32_39, cpld_callback, CPLD_SFP_MASK_PRESENT_32_39); +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_mask_present_40_47, cpld_callback, CPLD_SFP_MASK_PRESENT_40_47); + +static _SENSOR_DEVICE_ATTR_RW(cpld_qsfp_mask_present_48_53, cpld_callback, CPLD_QSFP_MASK_PRESENT_48_53); +static _SENSOR_DEVICE_ATTR_RW(cpld_qsfp_mask_port_48_53, cpld_callback, CPLD_QSFP_MASK_PORT_48_53); + +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_evt_present_0_7, cpld_callback, CPLD_SFP_EVT_PRESENT_0_7); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_evt_present_8_15, cpld_callback, CPLD_SFP_EVT_PRESENT_8_15); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_evt_present_16_23, cpld_callback, CPLD_SFP_EVT_PRESENT_16_23); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_evt_present_24_31, cpld_callback, CPLD_SFP_EVT_PRESENT_24_31); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_evt_present_32_39, cpld_callback, CPLD_SFP_EVT_PRESENT_32_39); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_evt_present_40_47, cpld_callback, CPLD_SFP_EVT_PRESENT_40_47); + +static _SENSOR_DEVICE_ATTR_RO(cpld_qsfp_evt_present_48_53, cpld_callback, CPLD_QSFP_EVT_PRESENT_48_53); +static _SENSOR_DEVICE_ATTR_RO(cpld_qsfp_evt_port_48_53, cpld_callback, CPLD_QSFP_EVT_PORT_48_53); + +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_intr_rx_los_0_7, cpld_callback, CPLD_SFP_INTR_RX_LOS_0_7); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_intr_rx_los_8_15, cpld_callback, CPLD_SFP_INTR_RX_LOS_8_15); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_intr_rx_los_16_23, cpld_callback, CPLD_SFP_INTR_RX_LOS_16_23); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_intr_rx_los_24_31, cpld_callback, CPLD_SFP_INTR_RX_LOS_24_31); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_intr_rx_los_32_39, cpld_callback, CPLD_SFP_INTR_RX_LOS_32_39); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_intr_rx_los_40_47, cpld_callback, CPLD_SFP_INTR_RX_LOS_40_47); + +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_intr_tx_fault_0_7, cpld_callback, CPLD_SFP_INTR_TX_FAULT_0_7); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_intr_tx_fault_8_15, cpld_callback, CPLD_SFP_INTR_TX_FAULT_8_15); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_intr_tx_fault_16_23, cpld_callback, CPLD_SFP_INTR_TX_FAULT_16_23); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_intr_tx_fault_24_31, cpld_callback, CPLD_SFP_INTR_TX_FAULT_24_31); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_intr_tx_fault_32_39, cpld_callback, CPLD_SFP_INTR_TX_FAULT_32_39); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_intr_tx_fault_40_47, cpld_callback, CPLD_SFP_INTR_TX_FAULT_40_47); + +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_mask_rx_los_0_7, cpld_callback, CPLD_SFP_MASK_RX_LOS_0_7); +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_mask_rx_los_8_15, cpld_callback, CPLD_SFP_MASK_RX_LOS_8_15); +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_mask_rx_los_16_23, cpld_callback, CPLD_SFP_MASK_RX_LOS_16_23); +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_mask_rx_los_24_31, cpld_callback, CPLD_SFP_MASK_RX_LOS_24_31); +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_mask_rx_los_32_39, cpld_callback, CPLD_SFP_MASK_RX_LOS_32_39); +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_mask_rx_los_40_47, cpld_callback, CPLD_SFP_MASK_RX_LOS_40_47); + +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_mask_tx_fault_0_7, cpld_callback, CPLD_SFP_MASK_TX_FAULT_0_7); +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_mask_tx_fault_8_15, cpld_callback, CPLD_SFP_MASK_TX_FAULT_8_15); +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_mask_tx_fault_16_23, cpld_callback, CPLD_SFP_MASK_TX_FAULT_16_23); +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_mask_tx_fault_24_31, cpld_callback, CPLD_SFP_MASK_TX_FAULT_24_31); +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_mask_tx_fault_32_39, cpld_callback, CPLD_SFP_MASK_TX_FAULT_32_39); +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_mask_tx_fault_40_47, cpld_callback, CPLD_SFP_MASK_TX_FAULT_40_47); + +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_evt_rx_los_0_7, cpld_callback, CPLD_SFP_EVT_RX_LOS_0_7); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_evt_rx_los_8_15, cpld_callback, CPLD_SFP_EVT_RX_LOS_8_15); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_evt_rx_los_16_23, cpld_callback, CPLD_SFP_EVT_RX_LOS_16_23); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_evt_rx_los_24_31, cpld_callback, CPLD_SFP_EVT_RX_LOS_24_31); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_evt_rx_los_32_39, cpld_callback, CPLD_SFP_EVT_RX_LOS_32_39); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_evt_rx_los_40_47, cpld_callback, CPLD_SFP_EVT_RX_LOS_40_47); + +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_evt_tx_fault_0_7, cpld_callback, CPLD_SFP_EVT_TX_FAULT_0_7); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_evt_tx_fault_8_15, cpld_callback, CPLD_SFP_EVT_TX_FAULT_8_15); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_evt_tx_fault_16_23, cpld_callback, CPLD_SFP_EVT_TX_FAULT_16_23); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_evt_tx_fault_24_31, cpld_callback, CPLD_SFP_EVT_TX_FAULT_24_31); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_evt_tx_fault_32_39, cpld_callback, CPLD_SFP_EVT_TX_FAULT_32_39); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_evt_tx_fault_40_47, cpld_callback, CPLD_SFP_EVT_TX_FAULT_40_47); + +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_tx_disable_0_7, cpld_callback, CPLD_SFP_TX_DISABLE_0_7); +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_tx_disable_8_15, cpld_callback, CPLD_SFP_TX_DISABLE_8_15); +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_tx_disable_16_23, cpld_callback, CPLD_SFP_TX_DISABLE_16_23); +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_tx_disable_24_31, cpld_callback, CPLD_SFP_TX_DISABLE_24_31); +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_tx_disable_32_39, cpld_callback, CPLD_SFP_TX_DISABLE_32_39); +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_tx_disable_40_47, cpld_callback, CPLD_SFP_TX_DISABLE_40_47); + +static _SENSOR_DEVICE_ATTR_RW(cpld_qsfp_reset_48_53, cpld_callback, CPLD_QSFP_RESET_48_53); +static _SENSOR_DEVICE_ATTR_RW(cpld_qsfp_lpmode_48_53, cpld_callback, CPLD_QSFP_LPMODE_48_53); + +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_sfp_intr_present_0_7, cpld_callback, DBG_CPLD_SFP_INTR_PRESENT_0_7); +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_sfp_intr_present_8_15, cpld_callback, DBG_CPLD_SFP_INTR_PRESENT_8_15); +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_sfp_intr_present_16_23, cpld_callback, DBG_CPLD_SFP_INTR_PRESENT_16_23); +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_sfp_intr_present_24_31, cpld_callback, DBG_CPLD_SFP_INTR_PRESENT_24_31); +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_sfp_intr_present_32_39, cpld_callback, DBG_CPLD_SFP_INTR_PRESENT_32_39); +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_sfp_intr_present_40_47, cpld_callback, DBG_CPLD_SFP_INTR_PRESENT_40_47); + +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_qsfp_intr_present_48_53, cpld_callback, DBG_CPLD_QSFP_INTR_PRESENT_48_53); +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_qsfp_intr_port_48_53, cpld_callback, DBG_CPLD_QSFP_INTR_PORT_48_53); + +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_sfp_intr_rx_los_0_7, cpld_callback, DBG_CPLD_SFP_INTR_RX_LOS_0_7); +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_sfp_intr_rx_los_8_15, cpld_callback, DBG_CPLD_SFP_INTR_RX_LOS_8_15); +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_sfp_intr_rx_los_16_23, cpld_callback, DBG_CPLD_SFP_INTR_RX_LOS_16_23); +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_sfp_intr_rx_los_24_31, cpld_callback, DBG_CPLD_SFP_INTR_RX_LOS_24_31); +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_sfp_intr_rx_los_32_39, cpld_callback, DBG_CPLD_SFP_INTR_RX_LOS_32_39); +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_sfp_intr_rx_los_40_47, cpld_callback, DBG_CPLD_SFP_INTR_RX_LOS_40_47); + +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_sfp_intr_tx_fault_0_7, cpld_callback, DBG_CPLD_SFP_INTR_TX_FAULT_0_7); +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_sfp_intr_tx_fault_8_15, cpld_callback, DBG_CPLD_SFP_INTR_TX_FAULT_8_15); +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_sfp_intr_tx_fault_16_23, cpld_callback, DBG_CPLD_SFP_INTR_TX_FAULT_16_23); +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_sfp_intr_tx_fault_24_31, cpld_callback, DBG_CPLD_SFP_INTR_TX_FAULT_24_31); +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_sfp_intr_tx_fault_32_39, cpld_callback, DBG_CPLD_SFP_INTR_TX_FAULT_32_39); +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_sfp_intr_tx_fault_40_47, cpld_callback, DBG_CPLD_SFP_INTR_TX_FAULT_40_47); + +//BSP DEBUG +static _SENSOR_DEVICE_ATTR_RW(bsp_debug, bsp_callback, BSP_DEBUG); + +/* define support attributes of cpldx */ + +/* cpld 1 */ +static struct attribute *cpld1_attributes[] = { + _DEVICE_ATTR(cpld_board_id_0), + _DEVICE_ATTR(cpld_board_id_1), + + _DEVICE_ATTR(cpld_id), + _DEVICE_ATTR(cpld_chip), + _DEVICE_ATTR(cpld_sku_ext), + + _DEVICE_ATTR(cpld_major_ver), + _DEVICE_ATTR(cpld_minor_ver), + _DEVICE_ATTR(cpld_build_ver), + _DEVICE_ATTR(cpld_version_h), + + _DEVICE_ATTR(cpld_mac_intr), + _DEVICE_ATTR(cpld_hwm_intr), + _DEVICE_ATTR(cpld_cpld2_intr), + _DEVICE_ATTR(cpld_ntm_intr), + _DEVICE_ATTR(cpld_fan_psu_intr), + _DEVICE_ATTR(cpld_sfp_ioexp_intr), + _DEVICE_ATTR(cpld_cpu_nmi_intr), + _DEVICE_ATTR(cpld_ptp_intr), + _DEVICE_ATTR(cpld_system_intr), + + _DEVICE_ATTR(cpld_mac_mask), + _DEVICE_ATTR(cpld_hwm_mask), + _DEVICE_ATTR(cpld_cpld2_mask), + _DEVICE_ATTR(cpld_ntm_mask), + _DEVICE_ATTR(cpld_fan_psu_mask), + _DEVICE_ATTR(cpld_sfp_ioexp_mask), + _DEVICE_ATTR(cpld_cpu_nmi_mask), + _DEVICE_ATTR(cpld_ptp_mask), + _DEVICE_ATTR(cpld_system_mask), + + _DEVICE_ATTR(cpld_mac_evt), + _DEVICE_ATTR(cpld_hwm_evt), + _DEVICE_ATTR(cpld_cpld2_evt), + _DEVICE_ATTR(cpld_ntm_evt), + _DEVICE_ATTR(cpld_fan_psu_evt), + _DEVICE_ATTR(cpld_sfp_ioexp_evt), + _DEVICE_ATTR(cpld_cpu_nmi_evt), + _DEVICE_ATTR(cpld_ptp_evt), + + _DEVICE_ATTR(cpld_evt_ctrl), + + _DEVICE_ATTR(cpld_mac_reset), + _DEVICE_ATTR(cpld_system_reset), + _DEVICE_ATTR(cpld_bmc_ntm_reset), + _DEVICE_ATTR(cpld_usb_reset), + _DEVICE_ATTR(cpld_i2c_mux_reset), + _DEVICE_ATTR(cpld_i2c_mux_reset_2), + _DEVICE_ATTR(cpld_misc_reset), + + _DEVICE_ATTR(cpld_psu_status), + _DEVICE_ATTR(cpld_mac_synce), + _DEVICE_ATTR(cpld_fan_present), + _DEVICE_ATTR(cpld_mux_ctrl), + + _DEVICE_ATTR(cpld_system_led_sync), + _DEVICE_ATTR(cpld_system_led_sys), + _DEVICE_ATTR(cpld_system_led_fan), + _DEVICE_ATTR(cpld_system_led_psu_0), + _DEVICE_ATTR(cpld_system_led_psu_1), + _DEVICE_ATTR(cpld_system_led_id), + + _DEVICE_ATTR(dbg_cpld_mac_intr), + _DEVICE_ATTR(dbg_cpld_hwm_intr), + _DEVICE_ATTR(dbg_cpld_cpld2_intr), + _DEVICE_ATTR(dbg_cpld_ntm_intr), + _DEVICE_ATTR(dbg_cpld_fan_psu_intr), + _DEVICE_ATTR(dbg_cpld_sfp_ioexp_intr), + _DEVICE_ATTR(dbg_cpld_ptp_intr), + + _DEVICE_ATTR(bsp_debug), + + NULL +}; + +/* cpld 2 */ +static struct attribute *cpld2_attributes[] = { + _DEVICE_ATTR(cpld_id), + _DEVICE_ATTR(cpld_chip), + + _DEVICE_ATTR(cpld_major_ver), + _DEVICE_ATTR(cpld_minor_ver), + _DEVICE_ATTR(cpld_build_ver), + _DEVICE_ATTR(cpld_version_h), + + _DEVICE_ATTR(cpld_sfp_intr_present_0_7), + _DEVICE_ATTR(cpld_sfp_intr_present_8_15), + _DEVICE_ATTR(cpld_sfp_intr_present_16_23), + _DEVICE_ATTR(cpld_sfp_intr_present_24_31), + _DEVICE_ATTR(cpld_sfp_intr_present_32_39), + _DEVICE_ATTR(cpld_sfp_intr_present_40_47), + + _DEVICE_ATTR(cpld_qsfp_intr_present_48_53), + _DEVICE_ATTR(cpld_qsfp_intr_port_48_53), + + _DEVICE_ATTR(cpld_sfp_mask_present_0_7), + _DEVICE_ATTR(cpld_sfp_mask_present_8_15), + _DEVICE_ATTR(cpld_sfp_mask_present_16_23), + _DEVICE_ATTR(cpld_sfp_mask_present_24_31), + _DEVICE_ATTR(cpld_sfp_mask_present_32_39), + _DEVICE_ATTR(cpld_sfp_mask_present_40_47), + + _DEVICE_ATTR(cpld_qsfp_mask_present_48_53), + _DEVICE_ATTR(cpld_qsfp_mask_port_48_53), + + _DEVICE_ATTR(cpld_sfp_evt_present_0_7), + _DEVICE_ATTR(cpld_sfp_evt_present_8_15), + _DEVICE_ATTR(cpld_sfp_evt_present_16_23), + _DEVICE_ATTR(cpld_sfp_evt_present_24_31), + _DEVICE_ATTR(cpld_sfp_evt_present_32_39), + _DEVICE_ATTR(cpld_sfp_evt_present_40_47), + + _DEVICE_ATTR(cpld_qsfp_evt_present_48_53), + _DEVICE_ATTR(cpld_qsfp_evt_port_48_53), + + _DEVICE_ATTR(cpld_evt_ctrl), + + _DEVICE_ATTR(cpld_sfp_intr_rx_los_0_7), + _DEVICE_ATTR(cpld_sfp_intr_rx_los_8_15), + _DEVICE_ATTR(cpld_sfp_intr_rx_los_16_23), + _DEVICE_ATTR(cpld_sfp_intr_rx_los_24_31), + _DEVICE_ATTR(cpld_sfp_intr_rx_los_32_39), + _DEVICE_ATTR(cpld_sfp_intr_rx_los_40_47), + + _DEVICE_ATTR(cpld_sfp_intr_tx_fault_0_7), + _DEVICE_ATTR(cpld_sfp_intr_tx_fault_8_15), + _DEVICE_ATTR(cpld_sfp_intr_tx_fault_16_23), + _DEVICE_ATTR(cpld_sfp_intr_tx_fault_24_31), + _DEVICE_ATTR(cpld_sfp_intr_tx_fault_32_39), + _DEVICE_ATTR(cpld_sfp_intr_tx_fault_40_47), + + _DEVICE_ATTR(cpld_sfp_mask_rx_los_0_7), + _DEVICE_ATTR(cpld_sfp_mask_rx_los_8_15), + _DEVICE_ATTR(cpld_sfp_mask_rx_los_16_23), + _DEVICE_ATTR(cpld_sfp_mask_rx_los_24_31), + _DEVICE_ATTR(cpld_sfp_mask_rx_los_32_39), + _DEVICE_ATTR(cpld_sfp_mask_rx_los_40_47), + + _DEVICE_ATTR(cpld_sfp_mask_tx_fault_0_7), + _DEVICE_ATTR(cpld_sfp_mask_tx_fault_8_15), + _DEVICE_ATTR(cpld_sfp_mask_tx_fault_16_23), + _DEVICE_ATTR(cpld_sfp_mask_tx_fault_24_31), + _DEVICE_ATTR(cpld_sfp_mask_tx_fault_32_39), + _DEVICE_ATTR(cpld_sfp_mask_tx_fault_40_47), + + _DEVICE_ATTR(cpld_sfp_evt_rx_los_0_7), + _DEVICE_ATTR(cpld_sfp_evt_rx_los_8_15), + _DEVICE_ATTR(cpld_sfp_evt_rx_los_16_23), + _DEVICE_ATTR(cpld_sfp_evt_rx_los_24_31), + _DEVICE_ATTR(cpld_sfp_evt_rx_los_32_39), + _DEVICE_ATTR(cpld_sfp_evt_rx_los_40_47), + + _DEVICE_ATTR(cpld_sfp_evt_tx_fault_0_7), + _DEVICE_ATTR(cpld_sfp_evt_tx_fault_8_15), + _DEVICE_ATTR(cpld_sfp_evt_tx_fault_16_23), + _DEVICE_ATTR(cpld_sfp_evt_tx_fault_24_31), + _DEVICE_ATTR(cpld_sfp_evt_tx_fault_32_39), + _DEVICE_ATTR(cpld_sfp_evt_tx_fault_40_47), + + _DEVICE_ATTR(cpld_sfp_tx_disable_0_7), + _DEVICE_ATTR(cpld_sfp_tx_disable_8_15), + _DEVICE_ATTR(cpld_sfp_tx_disable_16_23), + _DEVICE_ATTR(cpld_sfp_tx_disable_24_31), + _DEVICE_ATTR(cpld_sfp_tx_disable_32_39), + _DEVICE_ATTR(cpld_sfp_tx_disable_40_47), + + _DEVICE_ATTR(cpld_qsfp_reset_48_53), + _DEVICE_ATTR(cpld_qsfp_lpmode_48_53), + + _DEVICE_ATTR(dbg_cpld_sfp_intr_present_0_7), + _DEVICE_ATTR(dbg_cpld_sfp_intr_present_8_15), + _DEVICE_ATTR(dbg_cpld_sfp_intr_present_16_23), + _DEVICE_ATTR(dbg_cpld_sfp_intr_present_24_31), + _DEVICE_ATTR(dbg_cpld_sfp_intr_present_32_39), + _DEVICE_ATTR(dbg_cpld_sfp_intr_present_40_47), + + _DEVICE_ATTR(dbg_cpld_qsfp_intr_present_48_53), + _DEVICE_ATTR(dbg_cpld_qsfp_intr_port_48_53), + + _DEVICE_ATTR(dbg_cpld_sfp_intr_rx_los_0_7), + _DEVICE_ATTR(dbg_cpld_sfp_intr_rx_los_8_15), + _DEVICE_ATTR(dbg_cpld_sfp_intr_rx_los_16_23), + _DEVICE_ATTR(dbg_cpld_sfp_intr_rx_los_24_31), + _DEVICE_ATTR(dbg_cpld_sfp_intr_rx_los_32_39), + _DEVICE_ATTR(dbg_cpld_sfp_intr_rx_los_40_47), + + _DEVICE_ATTR(dbg_cpld_sfp_intr_tx_fault_0_7), + _DEVICE_ATTR(dbg_cpld_sfp_intr_tx_fault_8_15), + _DEVICE_ATTR(dbg_cpld_sfp_intr_tx_fault_16_23), + _DEVICE_ATTR(dbg_cpld_sfp_intr_tx_fault_24_31), + _DEVICE_ATTR(dbg_cpld_sfp_intr_tx_fault_32_39), + _DEVICE_ATTR(dbg_cpld_sfp_intr_tx_fault_40_47), + + NULL +}; + +/* cpld 1 attributes group */ +static const struct attribute_group cpld1_group = { + .attrs = cpld1_attributes, +}; + +/* cpld 2 attributes group */ +static const struct attribute_group cpld2_group = { + .attrs = cpld2_attributes, +}; + +/* reg shift */ +static u8 _shift(u8 mask) +{ + int i=0, mask_one=1; + + for(i=0; i<8; ++i) { + if ((mask & mask_one) == 1) + return i; + else + mask >>= 1; + } + + return -1; +} + +/* reg mask and shift */ +static u8 _mask_shift(u8 val, u8 mask) +{ + int shift=0; + + shift = _shift(mask); + + return (val & mask) >> shift; +} + +static int _bsp_log(u8 log_type, char *fmt, ...) +{ + if ((log_type==LOG_READ && enable_log_read) || + (log_type==LOG_WRITE && enable_log_write)) { + va_list args; + int r; + + va_start(args, fmt); + r = vprintk(fmt, args); + va_end(args); + + return r; + } else { + return 0; + } +} + +static int _config_bsp_log(u8 log_type) +{ + switch(log_type) { + case LOG_NONE: + enable_log_read = LOG_DISABLE; + enable_log_write = LOG_DISABLE; + break; + case LOG_RW: + enable_log_read = LOG_ENABLE; + enable_log_write = LOG_ENABLE; + break; + case LOG_READ: + enable_log_read = LOG_ENABLE; + enable_log_write = LOG_DISABLE; + break; + case LOG_WRITE: + enable_log_read = LOG_DISABLE; + enable_log_write = LOG_ENABLE; + break; + default: + return -EINVAL; + } + return 0; +} + +/* get bsp value */ +static ssize_t read_bsp(char *buf, char *str) +{ + ssize_t len=0; + + len=sprintf(buf, "%s", str); + BSP_LOG_R("reg_val=%s", str); + + return len; +} + +/* set bsp value */ +static ssize_t write_bsp(const char *buf, char *str, size_t str_len, size_t count) +{ + snprintf(str, str_len, "%s", buf); + BSP_LOG_W("reg_val=%s", str); + + return count; +} + +/* get bsp parameter value */ +static ssize_t read_bsp_callback(struct device *dev, + struct device_attribute *da, char *buf) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + int str_len=0; + char *str=NULL; + + switch (attr->index) { + case BSP_DEBUG: + str = bsp_debug; + str_len = sizeof(bsp_debug); + break; + default: + return -EINVAL; + } + return read_bsp(buf, str); +} + +/* set bsp parameter value */ +static ssize_t write_bsp_callback(struct device *dev, + struct device_attribute *da, const char *buf, size_t count) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + int str_len=0; + char *str=NULL; + ssize_t ret = 0; + u8 bsp_debug_u8 = 0; + + switch (attr->index) { + case BSP_DEBUG: + str = bsp_debug; + str_len = sizeof(str); + ret = write_bsp(buf, str, str_len, count); + + if (kstrtou8(buf, 0, &bsp_debug_u8) < 0) { + return -EINVAL; + } else if (_config_bsp_log(bsp_debug_u8) < 0) { + return -EINVAL; + } + return ret; + default: + return -EINVAL; + } + return 0; +} + +/* get cpld register value */ +static ssize_t read_cpld_callback(struct device *dev, + struct device_attribute *da, char *buf) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + u8 reg = 0; + u8 mask = MASK_ALL; + + if (IS_PERM_R(sysfs_info[attr->index].permission)) { + reg = sysfs_info[attr->index].reg; + mask = sysfs_info[attr->index].mask; + } else { + dev_err(dev, "%s() error, attr->index=%d\n", __func__, attr->index); + return -EINVAL; + } + + return read_cpld_reg(dev, buf, reg, mask); +} + +/* set cpld register value */ +static ssize_t write_cpld_callback(struct device *dev, + struct device_attribute *da, const char *buf, size_t count) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + u8 reg = 0; + u8 mask = MASK_ALL; + + if (IS_PERM_W(sysfs_info[attr->index].permission)) { + reg = sysfs_info[attr->index].reg; + mask = sysfs_info[attr->index].mask; + } else { + dev_err(dev, "%s() error, attr->index=%d\n", __func__, attr->index); + return -EINVAL; + } + + return write_cpld_reg(dev, buf, count, reg, mask); +} + +/* get cpld register value */ +static u8 _read_cpld_reg(struct device *dev, + u8 reg, + u8 mask) +{ + struct i2c_client *client = to_i2c_client(dev); + struct cpld_data *data = i2c_get_clientdata(client); + int reg_val; + + I2C_READ_BYTE_DATA(reg_val, &data->access_lock, client, reg); + + if (unlikely(reg_val < 0)) { + return reg_val; + } else { + reg_val=_mask_shift(reg_val, mask); + return reg_val; + } +} + +/* get cpld register value */ +static ssize_t read_cpld_reg(struct device *dev, + char *buf, + u8 reg, + u8 mask) +{ + int reg_val; + + reg_val = _read_cpld_reg(dev, reg, mask); + if (unlikely(reg_val < 0)) { + dev_err(dev, "read_cpld_reg() error, reg_val=%d\n", reg_val); + return reg_val; + } else { + return sprintf(buf, "0x%02x\n", reg_val); + } +} + +/* set cpld register value */ +static ssize_t write_cpld_reg(struct device *dev, + const char *buf, + size_t count, + u8 reg, + u8 mask) +{ + struct i2c_client *client = to_i2c_client(dev); + struct cpld_data *data = i2c_get_clientdata(client); + u8 reg_val, reg_val_now, shift; + int ret = 0; + + if (kstrtou8(buf, 0, ®_val) < 0) + return -EINVAL; + + //apply continuous bits operation if mask is specified, discontinuous bits are not supported + if (mask != MASK_ALL) { + reg_val_now = _read_cpld_reg(dev, reg, MASK_ALL); + if (unlikely(reg_val_now < 0)) { + dev_err(dev, "write_cpld_reg() error, reg_val_now=%d\n", reg_val_now); + return reg_val_now; + } else { + //clear bits in reg_val_now by the mask + reg_val_now &= ~mask; + //get bit shift by the mask + shift = _shift(mask); + //calculate new reg_val + reg_val = reg_val_now | (reg_val << shift); + } + } + + I2C_WRITE_BYTE_DATA(ret, &data->access_lock, + client, reg, reg_val); + + if (unlikely(ret < 0)) { + dev_err(dev, "write_cpld_reg() error, return=%d\n", ret); + return ret; + } + + return count; +} + +/* get qsfp port config register value */ +static ssize_t read_cpld_version_h(struct device *dev, + struct device_attribute *da, + char *buf) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + + if (attr->index >= CPLD_VERSION_H) { + return sprintf(buf, "%d.%02d.%03d", + _read_cpld_reg(dev, CPLD_VERSION_REG, MASK_CPLD_MAJOR_VER), + _read_cpld_reg(dev, CPLD_VERSION_REG, MASK_CPLD_MINOR_VER), + _read_cpld_reg(dev, CPLD_BUILD_REG, MASK_ALL)); + } + return -1; +} + +/* add valid cpld client to list */ +static void cpld_add_client(struct i2c_client *client) +{ + struct cpld_client_node *node = NULL; + + node = kzalloc(sizeof(struct cpld_client_node), GFP_KERNEL); + if (!node) { + dev_info(&client->dev, + "Can't allocate cpld_client_node for index %d\n", + client->addr); + return; + } + + node->client = client; + + mutex_lock(&list_lock); + list_add(&node->list, &cpld_client_list); + mutex_unlock(&list_lock); +} + +/* remove exist cpld client in list */ +static void cpld_remove_client(struct i2c_client *client) +{ + struct list_head *list_node = NULL; + struct cpld_client_node *cpld_node = NULL; + int found = 0; + + mutex_lock(&list_lock); + list_for_each(list_node, &cpld_client_list) { + cpld_node = list_entry(list_node, + struct cpld_client_node, list); + + if (cpld_node->client == client) { + found = 1; + break; + } + } + + if (found) { + list_del(list_node); + kfree(cpld_node); + } + mutex_unlock(&list_lock); +} + +/* cpld drvier probe */ +static int cpld_probe(struct i2c_client *client, + const struct i2c_device_id *dev_id) +{ + int status; + struct cpld_data *data = NULL; + int ret = -EPERM; + + data = kzalloc(sizeof(struct cpld_data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + /* init cpld data for client */ + i2c_set_clientdata(client, data); + mutex_init(&data->access_lock); + + if (!i2c_check_functionality(client->adapter, + I2C_FUNC_SMBUS_BYTE_DATA)) { + dev_info(&client->dev, + "i2c_check_functionality failed (0x%x)\n", + client->addr); + status = -EIO; + goto exit; + } + + /* get cpld id from device */ + ret = i2c_smbus_read_byte_data(client, CPLD_ID_REG); + + if (ret < 0) { + dev_info(&client->dev, + "fail to get cpld id (0x%x) at addr (0x%x)\n", + CPLD_ID_REG, client->addr); + status = -EIO; + goto exit; + } + + if (INVALID(ret, cpld1, cpld2)) { + dev_info(&client->dev, + "cpld id %d(device) not valid\n", ret); + //status = -EPERM; + //goto exit; + } + +#if 0 + /* change client name for each cpld with index */ + snprintf(client->name, sizeof(client->name), "%s_%d", client->name, + data->index); +#endif + + data->index = dev_id->driver_data; + + /* register sysfs hooks for different cpld group */ + dev_info(&client->dev, "probe cpld with index %d\n", data->index); + switch (data->index) { + case cpld1: + status = sysfs_create_group(&client->dev.kobj, + &cpld1_group); + break; + case cpld2: + status = sysfs_create_group(&client->dev.kobj, + &cpld2_group); + break; + default: + status = -EINVAL; + } + + if (status) + goto exit; + + dev_info(&client->dev, "chip found\n"); + + /* add probe chip to client list */ + cpld_add_client(client); + + return 0; +exit: + switch (data->index) { + case cpld1: + sysfs_remove_group(&client->dev.kobj, &cpld1_group); + break; + case cpld2: + sysfs_remove_group(&client->dev.kobj, &cpld2_group); + break; + default: + break; + } + return status; +} + +/* cpld drvier remove */ +static int cpld_remove(struct i2c_client *client) +{ + struct cpld_data *data = i2c_get_clientdata(client); + + switch (data->index) { + case cpld1: + sysfs_remove_group(&client->dev.kobj, &cpld1_group); + break; + case cpld2: + sysfs_remove_group(&client->dev.kobj, &cpld2_group); + break; + } + + cpld_remove_client(client); + return 0; +} + +static int s7801_54xs_cpld_read_internal(struct i2c_client *client, u8 reg) +{ + int retry = I2C_RW_RETRY_COUNT; + int reg_val = 0; + struct cpld_data *data = i2c_get_clientdata(client); + + while (retry) { + I2C_READ_BYTE_DATA(reg_val, &data->access_lock, client, reg); + if (unlikely(reg_val < 0)) { + msleep(I2C_RW_RETRY_INTERVAL); + retry--; + + if (retry == 0) { + dev_err(&client->dev, "%s() retry %d times but still failed, reg=%x\n", __func__, I2C_RW_RETRY_COUNT, reg); + } + + continue; + } + + break; + } + + return reg_val; +} + +static int s7801_54xs_cpld_write_internal(struct i2c_client *client, u8 reg, u8 value) +{ + int ret = 0, retry = I2C_RW_RETRY_COUNT; + struct cpld_data *data = i2c_get_clientdata(client); + + while (retry) { + I2C_WRITE_BYTE_DATA(ret, &data->access_lock, client, reg, value); + if (unlikely(ret < 0)) { + msleep(I2C_RW_RETRY_INTERVAL); + retry--; + + if (retry == 0) { + dev_err(&client->dev, "%s() retry %d times but still failed, reg=%x\n", __func__, I2C_RW_RETRY_COUNT, reg); + } + + continue; + } + break; + } + + return ret; +} + +/* +int s7801_54xs_cpld_write(unsigned short cpld_addr, u8 reg, u8 value) +{ + struct list_head *list_node = NULL; + struct cpld_client_node *cpld_node = NULL; + int ret = -EIO; + + mutex_lock(&list_lock); + + list_for_each(list_node, &cpld_client_list) + { + cpld_node = list_entry(list_node, struct cpld_client_node, list); + + if (cpld_node->client->addr == cpld_addr) { + ret = s7801_54xs_cpld_write_internal(cpld_node->client, reg, value); + break; + } else { + pr_err("cpld_node->client->addr=%x, cpld_addr=%x\n", cpld_node->client->addr, cpld_addr); + } + } + + mutex_unlock(&list_lock); + + return ret; +} +EXPORT_SYMBOL(s7801_54xs_cpld_write); +*/ + +int s7801_54xs_cpld_psu_mux_sel(u8 mux_sel) +{ + unsigned short cpld_addr = cpld_i2c_addr[0]; + u8 reg = CPLD_MUX_CTRL_REG; + u8 reg_val = 0; + u8 psu_mux_mask = 0x06; + u8 mux_sel_val = 0; + + struct list_head *list_node = NULL; + struct cpld_client_node *cpld_node = NULL; + int ret = -EIO; + + switch(mux_sel) { + case 0: + //psu 0 + mux_sel_val = 0x04; + break; + case 1: + //psu 1 + mux_sel_val = 0x02; + break; + default: + //bmc + mux_sel_val = psu_mux_mask; + break; + } + + mutex_lock(&list_lock); + + list_for_each(list_node, &cpld_client_list) + { + cpld_node = list_entry(list_node, struct cpld_client_node, list); + + if (cpld_node->client->addr == cpld_addr) { + //read current reg value + reg_val = s7801_54xs_cpld_read_internal(cpld_node->client, reg); + //clear psu_mux_sel bits (bit 1 and 2) + reg_val &= ~psu_mux_mask; + //modify psu_mux_sel bits (bit 1 and 2) + reg_val |= mux_sel_val; + //write reg value + s7801_54xs_cpld_write_internal(cpld_node->client, reg, reg_val); + + break; + } else { + pr_err("cpld_node->client->addr=%x, cpld_addr=%x\n", cpld_node->client->addr, cpld_addr); + } + } + + mutex_unlock(&list_lock); + + return ret; +} +EXPORT_SYMBOL(s7801_54xs_cpld_psu_mux_sel); + +MODULE_DEVICE_TABLE(i2c, cpld_id); + +static struct i2c_driver cpld_driver = { + .class = I2C_CLASS_HWMON, + .driver = { + .name = "x86_64_ufispace_s7801_54xs_cpld", + }, + .probe = cpld_probe, + .remove = cpld_remove, + .id_table = cpld_id, + .address_list = cpld_i2c_addr, +}; + +static int __init cpld_init(void) +{ + mutex_init(&list_lock); + return i2c_add_driver(&cpld_driver); +} + +static void __exit cpld_exit(void) +{ + i2c_del_driver(&cpld_driver); +} + +MODULE_AUTHOR("Jason Tsai "); +MODULE_DESCRIPTION("x86_64_ufispace_s7801_54xs_cpld driver"); +MODULE_LICENSE("GPL"); + +module_init(cpld_init); +module_exit(cpld_exit); diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/modules/x86-64-ufispace-s7801-54xs-cpld.h b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/modules/x86-64-ufispace-s7801-54xs-cpld.h new file mode 100644 index 000000000000..3e9c457095cc --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/modules/x86-64-ufispace-s7801-54xs-cpld.h @@ -0,0 +1,269 @@ +/* header file for i2c cpld driver of ufispace_s7801_54xs + * + * Copyright (C) 2022 UfiSpace Technology Corporation. + * Jason Tsai + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef UFISPACE_s7801_54xs_CPLD_H +#define UFISPACE_s7801_54xs_CPLD_H + +/* CPLD device index value */ +enum cpld_id { + cpld1, + cpld2 +}; + +/* CPLD common registers */ +#define CPLD_VERSION_REG 0x02 +#define CPLD_ID_REG 0x03 +#define CPLD_BUILD_REG 0x04 +#define CPLD_CHIP_REG 0x05 + +#define CPLD_EVT_CTRL_REG 0x3F + +/* CPLD 1 registers */ +#define CPLD_BOARD_ID_0_REG 0x00 +#define CPLD_BOARD_ID_1_REG 0x01 +#define CPLD_SKU_EXT_REG 0x06 + +#define CPLD_MAC_INTR_REG 0x10 +#define CPLD_HWM_INTR_REG 0x13 +#define CPLD_CPLD2_INTR_REG 0x14 +#define CPLD_NTM_INTR_REG 0x15 +#define CPLD_FAN_PSU_INTR_REG 0x16 +#define CPLD_SFP_IOEXP_INTR_REG 0x18 +#define CPLD_CPU_NMI_INTR_REG 0x19 +#define CPLD_PTP_INTR_REG 0x1B +#define CPLD_SYSTEM_INTR_REG 0x1C + +#define CPLD_MAC_MASK_REG 0x20 +#define CPLD_HWM_MASK_REG 0x23 +#define CPLD_CPLD2_MASK_REG 0x24 +#define CPLD_NTM_MASK_REG 0x25 +#define CPLD_FAN_PSU_MASK_REG 0x26 +#define CPLD_SFP_IOEXP_MASK_REG 0x28 +#define CPLD_CPU_NMI_MASK_REG 0x29 +#define CPLD_PTP_MASK_REG 0x2B +#define CPLD_SYSTEM_MASK_REG 0x2C + +#define CPLD_MAC_EVT_REG 0x30 +#define CPLD_HWM_EVT_REG 0x33 +#define CPLD_CPLD2_EVT_REG 0x34 +#define CPLD_NTM_EVT_REG 0x35 +#define CPLD_FAN_PSU_EVT_REG 0x36 +#define CPLD_SFP_IOEXP_EVT_REG 0x38 +#define CPLD_CPU_NMI_EVT_REG 0x39 +#define CPLD_PTP_EVT_REG 0x3B + +#define CPLD_MAC_RESET_REG 0x40 +#define CPLD_SYSTEM_RESET_REG 0x41 +#define CPLD_BMC_NTM_RESET_REG 0x43 +#define CPLD_USB_RESET_REG 0x44 +#define CPLD_I2C_MUX_RESET_REG 0x46 +#define CPLD_I2C_MUX_RESET_2_REG 0x47 +#define CPLD_MISC_RESET_REG 0x48 + +#define CPLD_BRD_PRESENT_REG 0x50 +#define CPLD_PSU_STATUS_REG 0x51 +#define CPLD_SYSTEM_PWR_REG 0x52 +#define CPLD_MAC_SYNCE_REG 0x53 +#define CPLD_MAC_AVS_REG 0x54 +#define CPLD_SYSTEM_STATUS_REG 0x55 +#define CPLD_FAN_PRESENT_REG 0x56 +#define CPLD_WATCHDOG_REG 0x5A +#define CPLD_BOOT_SELECT_REG 0x5B +#define CPLD_MUX_CTRL_REG 0x5C +#define CPLD_MISC_CTRL_1_REG 0x5D +#define CPLD_MISC_CTRL_2_REG 0x5E +#define CPLD_TIMING_CTRL_REG 0x5F + +#define CPLD_MAC_TEMP_REG 0x61 + +/* +#define CPLD_SYSTEM_LED_SYS_FAN_REG 0x80 +#define CPLD_SYSTEM_LED_PSU_REG 0x81 +#define CPLD_SYSTEM_LED_SYNC_REG 0x82 +#define CPLD_SYSTEM_LED_ID_REG 0x84 +*/ +#define CPLD_SYSTEM_LED_PSU_REG 0x80 +#define CPLD_SYSTEM_LED_SYS_REG 0x81 +#define CPLD_SYSTEM_LED_SYNC_REG 0x82 +#define CPLD_SYSTEM_LED_FAN_REG 0x83 +#define CPLD_SYSTEM_LED_ID_REG 0x84 + +#define CPLD_MAC_PG_REG 0x90 +#define CPLD_MISC_PG_REG 0x92 +#define CPLD_MAC_PG_EN_REG 0x93 +#define CPLD_MISC_PG_EN_REG 0x95 + +#define DBG_CPLD_MAC_INTR_REG 0xE0 +#define DBG_CPLD_HWM_INTR_REG 0xE3 +#define DBG_CPLD_CPLD2_INTR_REG 0xE4 +#define DBG_CPLD_NTM_INTR_REG 0xE5 +#define DBG_CPLD_FAN_PSU_INTR_REG 0xE6 +#define DBG_CPLD_SFP_IOEXP_INTR_REG 0xE8 +#define DBG_CPLD_PTP_INTR_REG 0xEB + +#define CPLD_UPG_RESET_REG 0xF0 + +/* CPLD 2*/ + +//interrupt status +#define CPLD_SFP_INTR_PRESENT_0_7_REG 0x10 +#define CPLD_SFP_INTR_PRESENT_8_15_REG 0x11 +#define CPLD_SFP_INTR_PRESENT_16_23_REG 0x12 +#define CPLD_SFP_INTR_PRESENT_24_31_REG 0x13 +#define CPLD_SFP_INTR_PRESENT_32_39_REG 0x14 +#define CPLD_SFP_INTR_PRESENT_40_47_REG 0x15 +#define CPLD_QSFP_INTR_PRESENT_48_53_REG 0x16 +#define CPLD_QSFP_INTR_PORT_48_53_REG 0x17 + +//interrupt mask +#define CPLD_SFP_MASK_PRESENT_0_7_REG 0x20 +#define CPLD_SFP_MASK_PRESENT_8_15_REG 0x21 +#define CPLD_SFP_MASK_PRESENT_16_23_REG 0x22 +#define CPLD_SFP_MASK_PRESENT_24_31_REG 0x23 +#define CPLD_SFP_MASK_PRESENT_32_39_REG 0x24 +#define CPLD_SFP_MASK_PRESENT_40_47_REG 0x25 +#define CPLD_QSFP_MASK_PRESENT_48_53_REG 0x26 +#define CPLD_QSFP_MASK_PORT_48_53_REG 0x27 + +//interrupt event +#define CPLD_SFP_EVT_PRESENT_0_7_REG 0x30 +#define CPLD_SFP_EVT_PRESENT_8_15_REG 0x31 +#define CPLD_SFP_EVT_PRESENT_16_23_REG 0x32 +#define CPLD_SFP_EVT_PRESENT_24_31_REG 0x33 +#define CPLD_SFP_EVT_PRESENT_32_39_REG 0x34 +#define CPLD_SFP_EVT_PRESENT_40_47_REG 0x35 +#define CPLD_QSFP_EVT_PRESENT_48_53_REG 0x36 +#define CPLD_QSFP_EVT_PORT_48_53_REG 0x37 + +#define CPLD_SFP_INTR_RX_LOS_0_7_REG 0x40 +#define CPLD_SFP_INTR_RX_LOS_8_15_REG 0x41 +#define CPLD_SFP_INTR_RX_LOS_16_23_REG 0x42 +#define CPLD_SFP_INTR_RX_LOS_24_31_REG 0x43 +#define CPLD_SFP_INTR_RX_LOS_32_39_REG 0x44 +#define CPLD_SFP_INTR_RX_LOS_40_47_REG 0x45 + +#define CPLD_SFP_INTR_TX_FAULT_0_7_REG 0x46 +#define CPLD_SFP_INTR_TX_FAULT_8_15_REG 0x47 +#define CPLD_SFP_INTR_TX_FAULT_16_23_REG 0x48 +#define CPLD_SFP_INTR_TX_FAULT_24_31_REG 0x49 +#define CPLD_SFP_INTR_TX_FAULT_32_39_REG 0x4A +#define CPLD_SFP_INTR_TX_FAULT_40_47_REG 0x4B + +//#define CPLD_SFP_RX_LOS_BASE_REG 0x40 +//#define CPLD_SFP_TX_FAULT_BASE_REG 0x46 + +#define CPLD_SFP_MASK_RX_LOS_0_7_REG 0x50 +#define CPLD_SFP_MASK_RX_LOS_8_15_REG 0x51 +#define CPLD_SFP_MASK_RX_LOS_16_23_REG 0x52 +#define CPLD_SFP_MASK_RX_LOS_24_31_REG 0x53 +#define CPLD_SFP_MASK_RX_LOS_32_39_REG 0x54 +#define CPLD_SFP_MASK_RX_LOS_40_47_REG 0x55 + +#define CPLD_SFP_MASK_TX_FAULT_0_7_REG 0x56 +#define CPLD_SFP_MASK_TX_FAULT_8_15_REG 0x57 +#define CPLD_SFP_MASK_TX_FAULT_16_23_REG 0x58 +#define CPLD_SFP_MASK_TX_FAULT_24_31_REG 0x59 +#define CPLD_SFP_MASK_TX_FAULT_32_39_REG 0x5A +#define CPLD_SFP_MASK_TX_FAULT_40_47_REG 0x5B + +//#define CPLD_SFP_RX_LOS_MASK_BASE_REG 0x50 +//#define CPLD_SFP_TX_FAULT_MASK_BASE_REG 0x56 + +#define CPLD_SFP_EVT_RX_LOS_0_7_REG 0x60 +#define CPLD_SFP_EVT_RX_LOS_8_15_REG 0x61 +#define CPLD_SFP_EVT_RX_LOS_16_23_REG 0x62 +#define CPLD_SFP_EVT_RX_LOS_24_31_REG 0x63 +#define CPLD_SFP_EVT_RX_LOS_32_39_REG 0x64 +#define CPLD_SFP_EVT_RX_LOS_40_47_REG 0x65 + +#define CPLD_SFP_EVT_TX_FAULT_0_7_REG 0x66 +#define CPLD_SFP_EVT_TX_FAULT_8_15_REG 0x67 +#define CPLD_SFP_EVT_TX_FAULT_16_23_REG 0x68 +#define CPLD_SFP_EVT_TX_FAULT_24_31_REG 0x69 +#define CPLD_SFP_EVT_TX_FAULT_32_39_REG 0x6A +#define CPLD_SFP_EVT_TX_FAULT_40_47_REG 0x6B + +//#define CPLD_SFP_RX_LOS_EVT_BASE_REG 0x60 +//#define CPLD_SFP_TX_FAULT_EVT_BASE_REG 0x66 + +#define CPLD_SFP_TX_DISABLE_0_7_REG 0x70 +#define CPLD_SFP_TX_DISABLE_8_15_REG 0x71 +#define CPLD_SFP_TX_DISABLE_16_23_REG 0x72 +#define CPLD_SFP_TX_DISABLE_24_31_REG 0x73 +#define CPLD_SFP_TX_DISABLE_32_39_REG 0x74 +#define CPLD_SFP_TX_DISABLE_40_47_REG 0x75 + +//#define CPLD_SFP_TX_DISABLE_BASE_REG 0x70 +#define CPLD_QSFP_RESET_48_53_REG 0x76 +#define CPLD_QSFP_LPMODE_48_53_REG 0x77 + +//debug interrupt status +#define DBG_CPLD_SFP_INTR_PRESENT_BASE_REG 0xD0 +#define DBG_CPLD_SFP_INTR_PRESENT_0_7_REG 0xD0 +#define DBG_CPLD_SFP_INTR_PRESENT_8_15_REG 0xD1 +#define DBG_CPLD_SFP_INTR_PRESENT_16_23_REG 0xD2 +#define DBG_CPLD_SFP_INTR_PRESENT_24_31_REG 0xD3 +#define DBG_CPLD_SFP_INTR_PRESENT_32_39_REG 0xD4 +#define DBG_CPLD_SFP_INTR_PRESENT_40_47_REG 0xD5 +#define DBG_CPLD_QSFP_INTR_PRESENT_48_53_REG 0xD6 +#define DBG_CPLD_QSFP_INTR_PORT_48_53_REG 0xD7 + +//debug interrupt mask +#define DBG_CPLD_SFP_INTR_RX_LOS_0_7_REG 0xE0 +#define DBG_CPLD_SFP_INTR_RX_LOS_8_15_REG 0xE1 +#define DBG_CPLD_SFP_INTR_RX_LOS_16_23_REG 0xE2 +#define DBG_CPLD_SFP_INTR_RX_LOS_24_31_REG 0xE3 +#define DBG_CPLD_SFP_INTR_RX_LOS_32_39_REG 0xE4 +#define DBG_CPLD_SFP_INTR_RX_LOS_40_47_REG 0xE5 + +#define DBG_CPLD_SFP_INTR_TX_FAULT_0_7_REG 0xE6 +#define DBG_CPLD_SFP_INTR_TX_FAULT_8_15_REG 0xE7 +#define DBG_CPLD_SFP_INTR_TX_FAULT_16_23_REG 0xE8 +#define DBG_CPLD_SFP_INTR_TX_FAULT_24_31_REG 0xE9 +#define DBG_CPLD_SFP_INTR_TX_FAULT_32_39_REG 0xEA +#define DBG_CPLD_SFP_INTR_TX_FAULT_40_47_REG 0xEB + +//#define DBG_CPLD_SFP_RX_LOS_BASE_REG 0xE0 +//#define DBG_CPLD_SFP_TX_FAULT_BASE_REG 0xE6 + +//MASK +#define MASK_ALL (0xFF) +#define MASK_HB (0b11110000) +#define MASK_LB (0b00001111) +#define MASK_CPLD_MAJOR_VER (0b11000000) +#define MASK_CPLD_MINOR_VER (0b00111111) +#define CPLD_SYSTEM_LED_SYS_MASK MASK_HB +#define CPLD_SYSTEM_LED_FAN_MASK MASK_LB +#define CPLD_SYSTEM_LED_PSU_0_MASK MASK_LB +#define CPLD_SYSTEM_LED_PSU_1_MASK MASK_HB +#define CPLD_SYSTEM_LED_SYNC_MASK MASK_LB +#define CPLD_SYSTEM_LED_ID_MASK MASK_LB +#define CPLD_SFP_LED_MASK_0 (0b00000011) +#define CPLD_SFP_LED_MASK_1 (0b00001100) +#define PERM_R (0b00000001) +#define PERM_W (0b00000010) +#define PERM_RW (PERM_R | PERM_W) +#define IS_PERM_R(perm) (perm & PERM_R ? 1u : 0u) +#define IS_PERM_W(perm) (perm & PERM_W ? 1u : 0u) + +/* common manipulation */ +#define INVALID(i, min, max) ((i < min) || (i > max) ? 1u : 0u) + +#endif diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/modules/x86-64-ufispace-s7801-54xs-lpc.c b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/modules/x86-64-ufispace-s7801-54xs-lpc.c new file mode 100644 index 000000000000..397604f6deb4 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/modules/x86-64-ufispace-s7801-54xs-lpc.c @@ -0,0 +1,883 @@ +/* + * A lpc driver for the ufispace_s7801_54xs + * + * Copyright (C) 2017-2022 UfiSpace Technology Corporation. + * Jason Tsai + * + * Based on ad7414.c + * Copyright 2006 Stefan Roese , DENX Software Engineering + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include + +#define BSP_LOG_R(fmt, args...) \ + _bsp_log (LOG_READ, KERN_INFO "%s:%s[%d]: " fmt "\r\n", \ + __FILE__, __func__, __LINE__, ##args) +#define BSP_LOG_W(fmt, args...) \ + _bsp_log (LOG_WRITE, KERN_INFO "%s:%s[%d]: " fmt "\r\n", \ + __FILE__, __func__, __LINE__, ##args) +#define BSP_PR(level, fmt, args...) _bsp_log (LOG_SYS, level "[BSP]" fmt "\r\n", ##args) + +#define _SENSOR_DEVICE_ATTR_RO(_name, _func, _index) \ + SENSOR_DEVICE_ATTR(_name, S_IRUGO, read_##_func, NULL, _index) + +#define _SENSOR_DEVICE_ATTR_WO(_name, _func, _index) \ + SENSOR_DEVICE_ATTR(_name, S_IWUSR, NULL, write_##_func, _index) + +#define _SENSOR_DEVICE_ATTR_RW(_name, _func, _index) \ + SENSOR_DEVICE_ATTR(_name, S_IRUGO | S_IWUSR, read_##_func, write_##_func, _index) + +#define _DEVICE_ATTR(_name) \ + &sensor_dev_attr_##_name.dev_attr.attr + +#define BSP_PR(level, fmt, args...) _bsp_log (LOG_SYS, level "[BSP]" fmt "\r\n", ##args) + +#define DRIVER_NAME "x86_64_ufispace_s7801_54xs_lpc" + +/* LPC registers */ + +#define REG_BASE_MB 0x700 +#define REG_BASE_EC 0xE300 + +#define REG_NONE 0x00 +//MB CPLD +#define REG_BRD_ID_0 (REG_BASE_MB + 0x00) +#define REG_BRD_ID_1 (REG_BASE_MB + 0x01) +#define REG_CPLD_VERSION (REG_BASE_MB + 0x02) +#define REG_CPLD_ID (REG_BASE_MB + 0x03) +#define REG_CPLD_BUILD (REG_BASE_MB + 0x04) +#define REG_CPLD_CHIP (REG_BASE_MB + 0x05) +#define REG_BRD_EXT_ID (REG_BASE_MB + 0x06) +#define REG_I2C_MUX_RESET (REG_BASE_MB + 0x46) +#define REG_I2C_MUX_RESET_2 (REG_BASE_MB + 0x47) +#define REG_MUX_CTRL (REG_BASE_MB + 0x5C) +#define REG_MISC_CTRL (REG_BASE_MB + 0x5D) +#define REG_MISC_CTRL_2 (REG_BASE_MB + 0x5E) + +//EC +#define REG_BIOS_BOOT (REG_BASE_EC + 0x0C) +#define REG_CPU_REV (REG_BASE_EC + 0x17) + +// BMC mailbox +#define REG_TEMP_MAC_HWM (REG_BASE_MB + 0xC0) + +//MASK +#define MASK_ALL (0xFF) +#define MASK_CPLD_MAJOR_VER (0b11000000) +#define MASK_CPLD_MINOR_VER (0b00111111) +#define MASK_HW_ID (0b00000011) +#define MASK_DEPH_ID (0b00000100) +#define MASK_BUILD_ID (0b00011000) +#define MASK_EXT_ID (0b00000111) +#define MASK_MUX_RESET_ALL (0x37) // 2#00110111 +#define MASK_MUX_RESET (MASK_ALL) +#define MASK_BIOS_BOOT_ROM (0b01000000) + +#define LPC_MDELAY (5) +#define MDELAY_RESET_INTERVAL (100) +#define MDELAY_RESET_FINISH (500) + +/* LPC sysfs attributes index */ +enum lpc_sysfs_attributes { + //MB CPLD + ATT_BRD_ID_0, + ATT_BRD_ID_1, + ATT_BRD_SKU_ID, + ATT_BRD_HW_ID, + ATT_BRD_DEPH_ID, + ATT_BRD_BUILD_ID, + ATT_BRD_EXT_ID, + + ATT_CPLD_ID, + ATT_CPLD_BUILD, + ATT_CPLD_CHIP, + + ATT_CPLD_VERSION_MAJOR, + ATT_CPLD_VERSION_MINOR, + ATT_CPLD_VERSION_BUILD, + ATT_CPLD_VERSION_H, + + ATT_MUX_RESET, + ATT_MUX_CTRL, + + //EC + ATT_CPU_HW_ID, + ATT_CPU_DEPH_ID, + ATT_CPU_BUILD_ID, + ATT_BIOS_BOOT_ROM, + //BMC mailbox + ATT_TEMP_MAC_HWM, + + //BSP + ATT_BSP_VERSION, + ATT_BSP_DEBUG, + ATT_BSP_PR_INFO, + ATT_BSP_PR_ERR, + ATT_BSP_REG, + ATT_BSP_GPIO_MAX, + ATT_MAX +}; + +enum data_type { + DATA_HEX, + DATA_DEC, + DATA_S_DEC, + DATA_UNK, +}; + +enum bsp_log_types { + LOG_NONE, + LOG_RW, + LOG_READ, + LOG_WRITE, + LOG_SYS +}; + +enum bsp_log_ctrl { + LOG_DISABLE, + LOG_ENABLE +}; + +struct lpc_data_s { + struct mutex access_lock; +}; + +typedef struct sysfs_info_s +{ + u16 reg; + u8 mask; + u8 data_type; +} sysfs_info_t; + +static sysfs_info_t sysfs_info[] = { + [ATT_BRD_ID_0] = {REG_BRD_ID_0, MASK_ALL, DATA_HEX}, + [ATT_BRD_ID_1] = {REG_BRD_ID_1, MASK_ALL, DATA_HEX}, + [ATT_BRD_SKU_ID] = {REG_BRD_ID_0, MASK_ALL, DATA_DEC}, + [ATT_BRD_HW_ID] = {REG_BRD_ID_1, MASK_HW_ID, DATA_DEC}, + [ATT_BRD_DEPH_ID] = {REG_BRD_ID_1, MASK_DEPH_ID, DATA_DEC}, + [ATT_BRD_BUILD_ID] = {REG_BRD_ID_1, MASK_BUILD_ID, DATA_DEC}, + [ATT_BRD_EXT_ID] = {REG_BRD_EXT_ID, MASK_EXT_ID, DATA_DEC}, + + [ATT_CPLD_ID] = {REG_CPLD_ID, MASK_ALL, DATA_DEC}, + [ATT_CPLD_BUILD] = {REG_CPLD_BUILD, MASK_ALL, DATA_DEC}, + [ATT_CPLD_CHIP] = {REG_CPLD_CHIP, MASK_ALL, DATA_DEC}, + + [ATT_CPLD_VERSION_MAJOR] = {REG_CPLD_VERSION, MASK_CPLD_MAJOR_VER, DATA_DEC}, + [ATT_CPLD_VERSION_MINOR] = {REG_CPLD_VERSION, MASK_CPLD_MINOR_VER, DATA_DEC}, + [ATT_CPLD_VERSION_BUILD] = {REG_CPLD_BUILD, MASK_ALL, DATA_DEC}, + [ATT_CPLD_VERSION_H] = {REG_CPLD_VERSION, MASK_ALL, DATA_UNK}, + + [ATT_MUX_RESET] = {REG_NONE, MASK_ALL, DATA_DEC}, + [ATT_MUX_CTRL] = {REG_MUX_CTRL, MASK_ALL, DATA_HEX}, + + //EC + [ATT_CPU_HW_ID] = {REG_CPU_REV, MASK_HW_ID, DATA_DEC}, + [ATT_CPU_DEPH_ID] = {REG_CPU_REV, MASK_DEPH_ID, DATA_DEC}, + [ATT_CPU_BUILD_ID] = {REG_CPU_REV, MASK_BUILD_ID, DATA_DEC}, + [ATT_BIOS_BOOT_ROM] = {REG_BIOS_BOOT, MASK_BIOS_BOOT_ROM, DATA_DEC}, + + //BMC mailbox + [ATT_TEMP_MAC_HWM] = {REG_TEMP_MAC_HWM , MASK_ALL, DATA_S_DEC}, + + //BSP + [ATT_BSP_VERSION] = {REG_NONE, MASK_ALL, DATA_UNK}, + [ATT_BSP_DEBUG] = {REG_NONE, MASK_ALL, DATA_UNK}, + [ATT_BSP_PR_INFO] = {REG_NONE, MASK_ALL, DATA_UNK}, + [ATT_BSP_PR_ERR] = {REG_NONE, MASK_ALL, DATA_UNK}, + [ATT_BSP_REG] = {REG_NONE, MASK_ALL, DATA_HEX}, +}; + +struct lpc_data_s *lpc_data; +char bsp_version[16]=""; +char bsp_debug[2]="0"; +char bsp_reg[8]="0x0"; +u8 enable_log_read = LOG_DISABLE; +u8 enable_log_write = LOG_DISABLE; +u8 enable_log_sys = LOG_ENABLE; +u8 mailbox_inited=0; + +/* reg shift */ +static u8 _shift(u8 mask) +{ + int i=0, mask_one=1; + + for(i=0; i<8; ++i) { + if ((mask & mask_one) == 1) + return i; + else + mask >>= 1; + } + + return -1; +} + +/* reg mask and shift */ +static u8 _mask_shift(u8 val, u8 mask) +{ + int shift=0; + + shift = _shift(mask); + + return (val & mask) >> shift; +} + +static u8 _parse_data(char *buf, unsigned int data, u8 data_type) +{ + if(buf == NULL) { + return -1; + } + + if(data_type == DATA_HEX) { + return sprintf(buf, "0x%02x", data); + } else if(data_type == DATA_DEC) { + return sprintf(buf, "%u", data); + } else { + return -1; + } + return 0; +} + +static int _bsp_log(u8 log_type, char *fmt, ...) +{ + if ((log_type==LOG_READ && enable_log_read) || + (log_type==LOG_WRITE && enable_log_write) || + (log_type==LOG_SYS && enable_log_sys) ) { + va_list args; + int r; + + va_start(args, fmt); + r = vprintk(fmt, args); + va_end(args); + + return r; + } else { + return 0; + } +} + +static int _config_bsp_log(u8 log_type) +{ + switch(log_type) { + case LOG_NONE: + enable_log_read = LOG_DISABLE; + enable_log_write = LOG_DISABLE; + break; + case LOG_RW: + enable_log_read = LOG_ENABLE; + enable_log_write = LOG_ENABLE; + break; + case LOG_READ: + enable_log_read = LOG_ENABLE; + enable_log_write = LOG_DISABLE; + break; + case LOG_WRITE: + enable_log_read = LOG_DISABLE; + enable_log_write = LOG_ENABLE; + break; + default: + return -EINVAL; + } + return 0; +} + +static void _outb(u8 data, u16 port) +{ + outb(data, port); + mdelay(LPC_MDELAY); +} + +/* init bmc mailbox, get from BMC team */ +static int bmc_mailbox_init(void) +{ + if (mailbox_inited) { + return mailbox_inited; + } + + //Enable super io writing + _outb(0xa5, 0x2e); + _outb(0xa5, 0x2e); + + //Logic device number + _outb(0x07, 0x2e); + _outb(0x0e, 0x2f); + + //Disable mailbox + _outb(0x30, 0x2e); + _outb(0x00, 0x2f); + + //Set base address bit + _outb(0x60, 0x2e); + _outb(0x07, 0x2f); + _outb(0x61, 0x2e); + _outb(0xc0, 0x2f); + + //Select bit[3:0] of SIRQ + _outb(0x70, 0x2e); + _outb(0x07, 0x2f); + + //Low level trigger + _outb(0x71, 0x2e); + _outb(0x01, 0x2f); + + //Enable mailbox + _outb(0x30, 0x2e); + _outb(0x01, 0x2f); + + //Disable super io writing + _outb(0xaa, 0x2e); + + //Mailbox initial + _outb(0x00, 0x786); + _outb(0x00, 0x787); + + //set mailbox_inited + mailbox_inited = 1; + + return mailbox_inited; +} + +/* get lpc register value */ +static u8 _read_lpc_reg(u16 reg, u8 mask) +{ + u8 reg_val=0x0, reg_mk_shf_val = 0x0; + + mutex_lock(&lpc_data->access_lock); + reg_val = inb(reg); + mutex_unlock(&lpc_data->access_lock); + + reg_mk_shf_val = _mask_shift(reg_val, mask); + + BSP_LOG_R("reg=0x%03x, reg_val=0x%02x, mask=0x%02x, reg_mk_shf_val=0x%02x", reg, reg_val, mask, reg_mk_shf_val); + + return reg_mk_shf_val; +} + +/* get lpc register value */ +static ssize_t read_lpc_reg(u16 reg, u8 mask, char *buf, u8 data_type) +{ + u8 reg_val; + int len=0; + + reg_val = _read_lpc_reg(reg, mask); + + // may need to change to hex value ? + len=_parse_data(buf, reg_val, data_type); + + return len; +} + +/* set lpc register value */ +static ssize_t write_lpc_reg(u16 reg, u8 mask, const char *buf, size_t count, u8 data_type) +{ + u8 reg_val, reg_val_now, shift; + + if (kstrtou8(buf, 0, ®_val) < 0) { + if(data_type == DATA_S_DEC) { + if (kstrtos8(buf, 0, ®_val) < 0) { + return -EINVAL; + } + } else { + return -EINVAL; + } + } + + //apply continuous bits operation if mask is specified, discontinuous bits are not supported + if (mask != MASK_ALL) { + reg_val_now = _read_lpc_reg(reg, MASK_ALL); + //clear bits in reg_val_now by the mask + reg_val_now &= ~mask; + //get bit shift by the mask + shift = _shift(mask); + //calculate new reg_val + reg_val = reg_val_now | (reg_val << shift); + } + + mutex_lock(&lpc_data->access_lock); + + _outb(reg_val, reg); + + mutex_unlock(&lpc_data->access_lock); + + BSP_LOG_W("reg=0x%03x, reg_val=0x%02x, mask=0x%02x", reg, reg_val, mask); + + return count; +} + +/* get bsp value */ +static ssize_t read_bsp(char *buf, char *str) +{ + ssize_t len=0; + + mutex_lock(&lpc_data->access_lock); + len=sprintf(buf, "%s", str); + mutex_unlock(&lpc_data->access_lock); + + BSP_LOG_R("reg_val=%s", str); + + return len; +} + +/* set bsp value */ +static ssize_t write_bsp(const char *buf, char *str, size_t str_len, size_t count) +{ + mutex_lock(&lpc_data->access_lock); + snprintf(str, str_len, "%s", buf); + mutex_unlock(&lpc_data->access_lock); + + BSP_LOG_W("reg_val=%s", str); + + return count; +} + +/* get gpio max value */ +static ssize_t read_gpio_max(struct device *dev, + struct device_attribute *da, + char *buf) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + + if (attr->index == ATT_BSP_GPIO_MAX) { + return sprintf(buf, "%d\n", ARCH_NR_GPIOS-1); + } + return -1; +} + +/* get mb cpld version in human readable format */ +static ssize_t read_mb_cpld_version_h(struct device *dev, + struct device_attribute *da, char *buf) +{ + ssize_t len=0; + u8 major = 0, minor = 0, build = 0; + major = _read_lpc_reg(REG_CPLD_VERSION, MASK_CPLD_MAJOR_VER); + minor = _read_lpc_reg(REG_CPLD_VERSION, MASK_CPLD_MINOR_VER); + build = _read_lpc_reg(REG_CPLD_BUILD, MASK_ALL); + len=sprintf(buf, "%u.%02u.%03u", major, minor, build); + + return len; +} + +/* get lpc register value */ +static ssize_t read_lpc_callback(struct device *dev, + struct device_attribute *da, char *buf) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + u16 reg = 0; + u8 mask = MASK_ALL; + u8 data_type = DATA_UNK; + + if (attr->index == ATT_BSP_REG) { + //copy value from bsp_reg + if (kstrtou16(bsp_reg, 0, ®) < 0) + return -EINVAL; + + data_type = sysfs_info[attr->index].data_type; + } else { + reg = sysfs_info[attr->index].reg; + mask = sysfs_info[attr->index].mask; + data_type = sysfs_info[attr->index].data_type; + } + + return read_lpc_reg(reg, mask, buf, data_type); +} + +/* set lpc register value */ +static ssize_t write_lpc_callback(struct device *dev, + struct device_attribute *da, const char *buf, size_t count) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + u16 reg = 0; + u8 mask = MASK_ALL; + u8 data_type = DATA_UNK; + + reg = sysfs_info[attr->index].reg; + mask = sysfs_info[attr->index].mask; + data_type = sysfs_info[attr->index].data_type; + + if(attr->index == ATT_TEMP_MAC_HWM) { + bmc_mailbox_init(); + } + + return write_lpc_reg(reg, mask, buf, count, data_type); +} + +/* get bsp parameter value */ +static ssize_t read_bsp_callback(struct device *dev, + struct device_attribute *da, char *buf) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + char *str=NULL; + + switch (attr->index) { + case ATT_BSP_VERSION: + str = bsp_version; + break; + case ATT_BSP_DEBUG: + str = bsp_debug; + break; + case ATT_BSP_REG: + str = bsp_reg; + break; + default: + return -EINVAL; + } + return read_bsp(buf, str); +} + +/* set bsp parameter value */ +static ssize_t write_bsp_callback(struct device *dev, + struct device_attribute *da, const char *buf, size_t count) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + int str_len=0; + char *str=NULL; + u16 reg = 0; + u8 bsp_debug_u8 = 0; + + switch (attr->index) { + case ATT_BSP_VERSION: + str = bsp_version; + str_len = sizeof(bsp_version); + break; + case ATT_BSP_DEBUG: + str = bsp_debug; + str_len = sizeof(bsp_debug); + break; + case ATT_BSP_REG: + if (kstrtou16(buf, 0, ®) < 0) + return -EINVAL; + + str = bsp_reg; + str_len = sizeof(bsp_reg); + break; + default: + return -EINVAL; + } + + if (attr->index == ATT_BSP_DEBUG) { + if (kstrtou8(buf, 0, &bsp_debug_u8) < 0) { + return -EINVAL; + } else if (_config_bsp_log(bsp_debug_u8) < 0) { + return -EINVAL; + } + } + + return write_bsp(buf, str, str_len, count); +} + +static ssize_t write_bsp_pr_callback(struct device *dev, + struct device_attribute *da, const char *buf, size_t count) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + int str_len = strlen(buf); + + if(str_len <= 0) + return str_len; + + switch (attr->index) { + case ATT_BSP_PR_INFO: + BSP_PR(KERN_INFO, "%s", buf); + break; + case ATT_BSP_PR_ERR: + BSP_PR(KERN_ERR, "%s", buf); + break; + default: + return -EINVAL; + } + + return str_len; +} + +/* set mux_reset register value */ +static ssize_t write_mux_reset(struct device *dev, + struct device_attribute *da, const char *buf, size_t count) +{ + u16 reg = REG_I2C_MUX_RESET; + u8 val = 0; + u8 mux_reset_reg_val = 0; + static int mux_reset_flag = 0; + + if (kstrtou8(buf, 0, &val) < 0) + return -EINVAL; + + if (mux_reset_flag == 0) { + if (val == 0) { + mutex_lock(&lpc_data->access_lock); + mux_reset_flag = 1; + BSP_LOG_W("i2c mux reset is triggered..."); + + //reset mux on SFP/QSFP ports + mux_reset_reg_val = inb(reg); + _outb((mux_reset_reg_val & (u8) (~MASK_MUX_RESET)), reg); + BSP_LOG_W("reg=0x%03x, reg_val=0x%02x", reg, mux_reset_reg_val & 0x0); + + //unset mux on SFP/QSFP ports + outb((mux_reset_reg_val | MASK_MUX_RESET), reg); + mdelay(500); + BSP_LOG_W("reg=0x%03x, reg_val=0x%02x", reg, mux_reset_reg_val | 0xFF); + + mux_reset_flag = 0; + mutex_unlock(&lpc_data->access_lock); + } else { + return -EINVAL; + } + } else { + BSP_LOG_W("i2c mux is resetting... (ignore)"); + mutex_lock(&lpc_data->access_lock); + mutex_unlock(&lpc_data->access_lock); + } + + return count; +} + +//SENSOR_DEVICE_ATTR - MB +static _SENSOR_DEVICE_ATTR_RO(board_id_0, lpc_callback, ATT_BRD_ID_0); +static _SENSOR_DEVICE_ATTR_RO(board_id_1, lpc_callback, ATT_BRD_ID_1); +static _SENSOR_DEVICE_ATTR_RO(board_sku_id, lpc_callback, ATT_BRD_SKU_ID); +static _SENSOR_DEVICE_ATTR_RO(board_hw_id, lpc_callback, ATT_BRD_HW_ID); +static _SENSOR_DEVICE_ATTR_RO(board_deph_id, lpc_callback, ATT_BRD_DEPH_ID); +static _SENSOR_DEVICE_ATTR_RO(board_build_id, lpc_callback, ATT_BRD_BUILD_ID); +static _SENSOR_DEVICE_ATTR_RO(board_ext_id, lpc_callback, ATT_BRD_EXT_ID); +static _SENSOR_DEVICE_ATTR_RO(cpld_version_major, lpc_callback, ATT_CPLD_VERSION_MAJOR); +static _SENSOR_DEVICE_ATTR_RO(cpld_version_minor, lpc_callback, ATT_CPLD_VERSION_MINOR); +static _SENSOR_DEVICE_ATTR_RO(cpld_version_build, lpc_callback, ATT_CPLD_VERSION_BUILD); +static _SENSOR_DEVICE_ATTR_RO(cpld_version_h, mb_cpld_version_h, ATT_CPLD_VERSION_H); +static _SENSOR_DEVICE_ATTR_RO(cpld_id, lpc_callback, ATT_CPLD_ID); + +static _SENSOR_DEVICE_ATTR_WO(mux_reset, mux_reset, ATT_MUX_RESET); +static _SENSOR_DEVICE_ATTR_RW(mux_ctrl, lpc_callback, ATT_MUX_CTRL); + +//SENSOR_DEVICE_ATTR - BMC mailbox +static _SENSOR_DEVICE_ATTR_WO(temp_mac_hwm , lpc_callback , ATT_TEMP_MAC_HWM); + +//SENSOR_DEVICE_ATTR - EC +static _SENSOR_DEVICE_ATTR_RO(cpu_hw_id, lpc_callback, ATT_CPU_HW_ID); +static _SENSOR_DEVICE_ATTR_RO(cpu_deph_id, lpc_callback, ATT_CPU_DEPH_ID); +static _SENSOR_DEVICE_ATTR_RO(cpu_build_id, lpc_callback, ATT_CPU_BUILD_ID); +static _SENSOR_DEVICE_ATTR_RO(bios_boot_rom, lpc_callback, ATT_BIOS_BOOT_ROM); + +//SENSOR_DEVICE_ATTR - BSP +static _SENSOR_DEVICE_ATTR_RW(bsp_version, bsp_callback, ATT_BSP_VERSION); +static _SENSOR_DEVICE_ATTR_RW(bsp_debug, bsp_callback, ATT_BSP_DEBUG); +static _SENSOR_DEVICE_ATTR_WO(bsp_pr_info, bsp_pr_callback, ATT_BSP_PR_INFO); +static _SENSOR_DEVICE_ATTR_WO(bsp_pr_err, bsp_pr_callback, ATT_BSP_PR_ERR); +static SENSOR_DEVICE_ATTR(bsp_reg, S_IRUGO | S_IWUSR, read_lpc_callback, write_bsp_callback, ATT_BSP_REG); +static SENSOR_DEVICE_ATTR(bsp_gpio_max, S_IRUGO, read_gpio_max, NULL, ATT_BSP_GPIO_MAX); + +static struct attribute *mb_cpld_attrs[] = { + _DEVICE_ATTR(board_id_0), + _DEVICE_ATTR(board_id_1), + _DEVICE_ATTR(board_sku_id), + _DEVICE_ATTR(board_hw_id), + _DEVICE_ATTR(board_deph_id), + _DEVICE_ATTR(board_build_id), + _DEVICE_ATTR(board_ext_id), + _DEVICE_ATTR(cpld_version_major), + _DEVICE_ATTR(cpld_version_minor), + _DEVICE_ATTR(cpld_version_build), + _DEVICE_ATTR(cpld_version_h), + _DEVICE_ATTR(cpld_id), + _DEVICE_ATTR(mux_reset), + _DEVICE_ATTR(mux_ctrl), + NULL, +}; + +static struct attribute *bsp_attrs[] = { + _DEVICE_ATTR(bsp_version), + _DEVICE_ATTR(bsp_debug), + _DEVICE_ATTR(bsp_pr_info), + _DEVICE_ATTR(bsp_pr_err), + _DEVICE_ATTR(bsp_reg), + _DEVICE_ATTR(bsp_gpio_max), + NULL, +}; + +static struct attribute *ec_attrs[] = { + _DEVICE_ATTR(cpu_hw_id), + _DEVICE_ATTR(cpu_deph_id), + _DEVICE_ATTR(cpu_build_id), + _DEVICE_ATTR(bios_boot_rom), + NULL, +}; + +static struct attribute *bmc_mailbox_attrs[] = { + _DEVICE_ATTR(temp_mac_hwm), + NULL, +}; + +static struct attribute_group mb_cpld_attr_grp = { + .name = "mb_cpld", + .attrs = mb_cpld_attrs, +}; + +static struct attribute_group bsp_attr_grp = { + .name = "bsp", + .attrs = bsp_attrs, +}; + +static struct attribute_group ec_attr_grp = { + .name = "ec", + .attrs = ec_attrs, +}; + +static struct attribute_group bmc_mailbox_attr_grp = { + .name = "bmc_mailbox", + .attrs = bmc_mailbox_attrs, +}; + +static void lpc_dev_release( struct device * dev) +{ + return; +} + +static struct platform_device lpc_dev = { + .name = DRIVER_NAME, + .id = -1, + .dev = { + .release = lpc_dev_release, + } +}; + +static int lpc_drv_probe(struct platform_device *pdev) +{ + int i = 0, grp_num = 4; + int err[4] = {0}; + struct attribute_group *grp; + + lpc_data = devm_kzalloc(&pdev->dev, sizeof(struct lpc_data_s), + GFP_KERNEL); + if (!lpc_data) + return -ENOMEM; + + mutex_init(&lpc_data->access_lock); + + for (i=0; idev.kobj, grp); + if (err[i]) { + printk(KERN_ERR "Cannot create sysfs for group %s\n", grp->name); + goto exit; + } else { + continue; + } + } + + return 0; + +exit: + for (i=0; idev.kobj, grp); + if (!err[i]) { + //remove previous successful cases + continue; + } else { + //remove first failed case, then return + return err[i]; + } + } + return 0; +} + +static int lpc_drv_remove(struct platform_device *pdev) +{ + sysfs_remove_group(&pdev->dev.kobj, &mb_cpld_attr_grp); + sysfs_remove_group(&pdev->dev.kobj, &bmc_mailbox_attr_grp); + sysfs_remove_group(&pdev->dev.kobj, &bsp_attr_grp); + sysfs_remove_group(&pdev->dev.kobj, &ec_attr_grp); + + return 0; +} + +static struct platform_driver lpc_drv = { + .probe = lpc_drv_probe, + .remove = __exit_p(lpc_drv_remove), + .driver = { + .name = DRIVER_NAME, + }, +}; + +int lpc_init(void) +{ + int err = 0; + + err = platform_driver_register(&lpc_drv); + if (err) { + printk(KERN_ERR "%s(#%d): platform_driver_register failed(%d)\n", + __func__, __LINE__, err); + + return err; + } + + err = platform_device_register(&lpc_dev); + if (err) { + printk(KERN_ERR "%s(#%d): platform_device_register failed(%d)\n", + __func__, __LINE__, err); + platform_driver_unregister(&lpc_drv); + return err; + } + + return err; +} + +void lpc_exit(void) +{ + platform_driver_unregister(&lpc_drv); + platform_device_unregister(&lpc_dev); +} + +MODULE_AUTHOR("Jason Tsai "); +MODULE_DESCRIPTION("x86_64_ufispace_s7801_54xs_lpc driver"); +MODULE_LICENSE("GPL"); + +module_init(lpc_init); +module_exit(lpc_exit); diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/modules/x86-64-ufispace-s7801-54xs-sys-eeprom.c b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/modules/x86-64-ufispace-s7801-54xs-sys-eeprom.c new file mode 100644 index 000000000000..f9f7728deb3d --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/modules/x86-64-ufispace-s7801-54xs-sys-eeprom.c @@ -0,0 +1,272 @@ +/* + * Copyright (C) 1998, 1999 Frodo Looijaard and + * Philip Edelbrock + * Copyright (C) 2003 Greg Kroah-Hartman + * Copyright (C) 2003 IBM Corp. + * Copyright (C) 2004 Jean Delvare + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* enable dev_dbg print out */ +//#define DEBUG + +#define __STDC_WANT_LIB_EXT1__ 1 +#include +#include +#include +#include +#include +#include +#include + +/* Addresses to scan */ +static const unsigned short normal_i2c[] = { /*0x50, 0x51, 0x52, 0x53, 0x54, + 0x55, 0x56, 0x57,*/ I2C_CLIENT_END }; + +/* Size of EEPROM in bytes */ +#define EEPROM_SIZE 512 + +#define SLICE_BITS (6) +#define SLICE_SIZE (1 << SLICE_BITS) +#define SLICE_NUM (EEPROM_SIZE/SLICE_SIZE) + +/* Each client has this additional data */ +struct eeprom_data { + struct mutex update_lock; + u8 valid; /* bitfield, bit!=0 if slice is valid */ + unsigned long last_updated[SLICE_NUM]; /* In jiffies, 8 slices */ + u8 data[EEPROM_SIZE]; /* Register values */ +}; + + +static void sys_eeprom_update_client(struct i2c_client *client, u8 slice) +{ + struct eeprom_data *data = i2c_get_clientdata(client); + int i, j; + int ret; + int addr; + + mutex_lock(&data->update_lock); + + if (!(data->valid & (1 << slice)) || + time_after(jiffies, data->last_updated[slice] + 300 * HZ)) { + dev_dbg(&client->dev, "Starting eeprom update, slice %u\n", slice); + + addr = slice << SLICE_BITS; + + ret = i2c_smbus_write_byte_data(client, (u8)((addr >> 8) & 0xFF), (u8)(addr & 0xFF)); + /* select the eeprom address */ + if (ret < 0) { + dev_err(&client->dev, "address set failed\n"); + goto exit; + } + + if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_READ_BYTE)) { + goto exit; + } + + for (i = slice << SLICE_BITS; i < (slice + 1) << SLICE_BITS; i+= SLICE_SIZE) { + for (j = i; j < (i+SLICE_SIZE); j++) { + int res; + + res = i2c_smbus_read_byte(client); + if (res < 0) { + goto exit; + } + + data->data[j] = res & 0xFF; + } + } + + data->last_updated[slice] = jiffies; + data->valid |= (1 << slice); + } +exit: + mutex_unlock(&data->update_lock); +} + +static ssize_t sys_eeprom_read(struct file *filp, struct kobject *kobj, + struct bin_attribute *bin_attr, + char *buf, loff_t off, size_t count) +{ + struct i2c_client *client = to_i2c_client(container_of(kobj, struct device, kobj)); + struct eeprom_data *data = i2c_get_clientdata(client); + u8 slice; + + if (off > EEPROM_SIZE) { + return 0; + } + if (off + count > EEPROM_SIZE) { + count = EEPROM_SIZE - off; + } + if (count == 0) { + return 0; + } + + /* Only refresh slices which contain requested bytes */ + for (slice = off >> SLICE_BITS; slice <= (off + count - 1) >> SLICE_BITS; slice++) { + sys_eeprom_update_client(client, slice); + } + + memcpy(buf, &data->data[off], count); + + return count; +} + +static ssize_t sys_eeprom_write(struct file *filp, struct kobject *kobj, + struct bin_attribute *bin_attr, + char *buf, loff_t off, size_t count) +{ + struct i2c_client *client = to_i2c_client(container_of(kobj, struct device, kobj)); + struct eeprom_data *data = i2c_get_clientdata(client); + int ret; + int i; + u8 cmd; + u16 value16; + + dev_dbg(&client->dev, "sys_eeprom_write off=%d, count=%d\n", (int)off, (int)count); + + if (off > EEPROM_SIZE) { + return 0; + } + if (off + count > EEPROM_SIZE) { + count = EEPROM_SIZE - off; + } + if (count == 0) { + return 0; + } + + mutex_lock(&data->update_lock); + + for(i=0; i < count; i++) { + /* write command */ + cmd = (off >> 8) & 0xff; + value16 = off & 0xff; + value16 |= buf[i] << 8; + ret = i2c_smbus_write_word_data(client, cmd, value16); + + if (ret < 0) { + dev_err(&client->dev, "write address failed at %d \n", (int)off); + goto exit; + } + + off++; + + /* need to wait for write complete */ + udelay(10000); + } +exit: + mutex_unlock(&data->update_lock); + /* force to update client when reading */ + for(i=0; i < SLICE_NUM; i++) { + data->last_updated[i] = 0; + } + + return count; +} + +static struct bin_attribute sys_eeprom_attr = { + .attr = { + .name = "eeprom", + .mode = S_IRUGO | S_IWUSR, + }, + .size = EEPROM_SIZE, + .read = sys_eeprom_read, + .write = sys_eeprom_write, +}; + +/* Return 0 if detection is successful, -ENODEV otherwise */ +static int sys_eeprom_detect(struct i2c_client *client, struct i2c_board_info *info) +{ + struct i2c_adapter *adapter = client->adapter; + + /* EDID EEPROMs are often 24C00 EEPROMs, which answer to all + addresses 0x50-0x57, but we only care about 0x51 and 0x55. So decline + attaching to addresses >= 0x56 on DDC buses */ + if (!(adapter->class & I2C_CLASS_SPD) && client->addr >= 0x56) { + return -ENODEV; + } + + if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_READ_BYTE) + && !i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WRITE_BYTE_DATA)) { + return -ENODEV; + } + + strlcpy(info->type, "eeprom", I2C_NAME_SIZE); + + return 0; +} + +static int sys_eeprom_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct eeprom_data *data; + int err; + + if (!(data = kzalloc(sizeof(struct eeprom_data), GFP_KERNEL))) { + err = -ENOMEM; + goto exit; + } + +#ifdef __STDC_LIB_EXT1__ + memset_s(data->data, EEPROM_SIZE, 0xff, EEPROM_SIZE); +#else + memset(data->data, 0xff, EEPROM_SIZE); +#endif + i2c_set_clientdata(client, data); + mutex_init(&data->update_lock); + + /* create the sysfs eeprom file */ + err = sysfs_create_bin_file(&client->dev.kobj, &sys_eeprom_attr); + if (err) { + goto exit_kfree; + } + + return 0; + +exit_kfree: + kfree(data); +exit: + return err; +} + +static int sys_eeprom_remove(struct i2c_client *client) +{ + sysfs_remove_bin_file(&client->dev.kobj, &sys_eeprom_attr); + kfree(i2c_get_clientdata(client)); + + return 0; +} + +static const struct i2c_device_id sys_eeprom_id[] = { + { "sys_eeprom", 0 }, + { } +}; + +static struct i2c_driver sys_eeprom_driver = { + .driver = { + .name = "sys_eeprom", + }, + .probe = sys_eeprom_probe, + .remove = sys_eeprom_remove, + .id_table = sys_eeprom_id, + + .class = I2C_CLASS_DDC | I2C_CLASS_SPD, + .detect = sys_eeprom_detect, + .address_list = normal_i2c, +}; + +module_i2c_driver(sys_eeprom_driver); + +MODULE_AUTHOR("Jason "); +MODULE_DESCRIPTION("UfiSpace System EEPROM driver"); +MODULE_LICENSE("GPL"); diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/service/pddf-platform-init.service b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/service/pddf-platform-init.service new file mode 120000 index 000000000000..0fd9f25b6c5e --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/service/pddf-platform-init.service @@ -0,0 +1 @@ +../../../../pddf/i2c/service/pddf-platform-init.service \ No newline at end of file diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/sonic_platform/__init__.py b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/sonic_platform/__init__.py new file mode 100644 index 000000000000..593867d31c9d --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/sonic_platform/__init__.py @@ -0,0 +1,4 @@ +# All the derived classes for PDDF +__all__ = ["platform", "chassis", "sfp", "psu", "thermal", "fan"] +from . import platform + diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/sonic_platform/chassis.py b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/sonic_platform/chassis.py new file mode 100644 index 000000000000..085f2af2ff85 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/sonic_platform/chassis.py @@ -0,0 +1,193 @@ +#!/usr/bin/env python + +############################################################################# +# PDDF +# Module contains an implementation of SONiC Chassis API +# +############################################################################# + +try: + import time + from sonic_platform_pddf_base.pddf_chassis import PddfChassis +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + +NUM_COMPONENT = 4 + +class Chassis(PddfChassis): + """ + PDDF Platform-specific Chassis class + """ + + SYSLED_DEV_NAME = "SYS_LED" + port_dict = {} + + def __init__(self, pddf_data=None, pddf_plugin_data=None): + PddfChassis.__init__(self, pddf_data, pddf_plugin_data) + self._initialize_components() + + def _initialize_components(self): + from sonic_platform.component import Component + for index in range(NUM_COMPONENT): + component = Component(index) + self._component_list.append(component) + + # Provide the functions/variables below for which implementation is to be overwritten + def get_name(self): + """ + Retrieves the name of the chassis + Returns: + string: The name of the chassis + """ + # return device_info.get_hwsku() + return self._eeprom.platform_name_str() + + def initizalize_system_led(self): + return True + + def get_status_led(self): + return self.get_system_led(self.SYSLED_DEV_NAME) + + def get_change_event(self, timeout=0): + """ + Returns a nested dictionary containing all devices which have + experienced a change at chassis level + Args: + timeout: Timeout in milliseconds (optional). If timeout == 0, + this method will block until a change is detected. + Returns: + (bool, dict): + - bool: True if call successful, False if not; + - dict: A nested dictionary where key is a device type, + value is a dictionary with key:value pairs in the format of + {'device_id':'device_event'}, where device_id is the device ID + for this device and device_event. + The known devices's device_id and device_event was defined as table below. + ----------------------------------------------------------------- + device | device_id | device_event | annotate + ----------------------------------------------------------------- + 'fan' '' '0' Fan removed + '1' Fan inserted + 'sfp' '' '0' Sfp removed + '1' Sfp inserted + '2' I2C bus stuck + '3' Bad eeprom + '4' Unsupported cable + '5' High Temperature + '6' Bad cable + 'voltage' '' '0' Vout normal + '1' Vout abnormal + -------------------------------------------------------------------- + Ex. {'fan':{'0':'0', '2':'1'}, 'sfp':{'11':'0', '12':'1'}, + 'voltage':{'U20':'0', 'U21':'1'}} + Indicates that: + fan 0 has been removed, fan 2 has been inserted. + sfp 11 has been removed, sfp 12 has been inserted. + monitored voltage U20 became normal, voltage U21 became abnormal. + Note: For sfp, when event 3-6 happened, the module will not be avalaible, + XCVRD shall stop to read eeprom before SFP recovered from error status. + """ + + change_event_dict = {"fan": {}, "sfp": {}, "voltage": {}} + + start_time = time.time() + forever = False + + if timeout == 0: + forever = True + elif timeout > 0: + timeout = timeout / float(1000) # Convert to secs + else: + print("get_change_event:Invalid timeout value", timeout) + return False, change_event_dict + + end_time = start_time + timeout + if start_time > end_time: + print( + "get_change_event:" "time wrap / invalid timeout value", + timeout, + ) + return False, change_event_dict # Time wrap or possibly incorrect timeout + try: + while timeout >= 0: + # check for sfp + sfp_change_dict = self.get_transceiver_change_event() + # check for fan + # fan_change_dict = self.get_fan_change_event() + # check for voltage + # voltage_change_dict = self.get_voltage_change_event() + + if sfp_change_dict: + change_event_dict["sfp"] = sfp_change_dict + # change_event_dict["fan"] = fan_change_dict + # change_event_dict["voltage"] = voltage_change_dict + return True, change_event_dict + if forever: + time.sleep(1) + else: + timeout = end_time - time.time() + if timeout >= 1: + time.sleep(1) # We poll at 1 second granularity + else: + if timeout > 0: + time.sleep(timeout) + return True, change_event_dict + except Exception as e: + print(e) + print("get_change_event: Should not reach here.") + return False, change_event_dict + + def get_transceiver_change_event(self): + current_port_dict = {} + ret_dict = {} + + # Check for OIR events and return ret_dict + for index in range(self.platform_inventory['num_ports']): + if self._sfp_list[index].get_presence(): + #current_port_dict[index] = self.STATUS_INSERTED + current_port_dict[index] = self.plugin_data['XCVR']['plug_status']['inserted'] + else: + #current_port_dict[index] = self.STATUS_REMOVED + current_port_dict[index] = self.plugin_data['XCVR']['plug_status']['removed'] + + if len(self.port_dict) == 0: # first time + self.port_dict = current_port_dict + return {} + + if current_port_dict == self.port_dict: + return {} + + # Update reg value + for index, status in current_port_dict.items(): + if self.port_dict[index] != status: + ret_dict[index] = status + #ret_dict[str(index)] = status + self.port_dict = current_port_dict + for index, status in ret_dict.items(): + if int(status) == 1: + pass + #self._sfp_list[int(index)].check_sfp_optoe_type() + return ret_dict + + def get_reboot_cause(self): + """ + Retrieves the cause of the previous reboot + + Returns: + A tuple (string, string) where the first element is a string + containing the cause of the previous reboot. This string must be + one of the predefined strings in this class. If the first string + is "REBOOT_CAUSE_HARDWARE_OTHER", the second string can be used + to pass a description of the reboot cause. + """ + + reboot_cause_path = self.plugin_data['REBOOT_CAUSE']['reboot_cause_file'] + + try: + with open(reboot_cause_path, 'r', errors='replace') as fd: + data = fd.read() + sw_reboot_cause = data.strip() + except IOError: + sw_reboot_cause = "Unknown" + + return ('REBOOT_CAUSE_NON_HARDWARE', sw_reboot_cause) diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/sonic_platform/component.py b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/sonic_platform/component.py new file mode 100644 index 000000000000..1c583079f8c2 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/sonic_platform/component.py @@ -0,0 +1,125 @@ +############################################################################# +# +# Component contains an implementation of SONiC Platform Base API and +# provides the components firmware management function +# +############################################################################# + +try: + import subprocess + from sonic_platform_base.component_base import ComponentBase + from sonic_platform_pddf_base import pddfapi +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + +CPLD_SYSFS = { + "CPLD1": {"major": "cpld1_major_ver", "minor": "cpld1_minor_ver", "build": "cpld1_build"}, + "CPLD2": {"major": "cpld2_major_ver", "minor": "cpld2_minor_ver", "build": "cpld2_build"}, +} + +BMC_CMDS = { + "VER1": "ipmitool mc info | grep 'Firmware Revision' | cut -d':' -f2 | cut -d'.' -f1", + "VER2": "ipmitool mc info | grep 'Firmware Revision' | cut -d':' -f2 | cut -d'.' -f2", + "VER3": "echo $((`ipmitool mc info | grep 'Aux Firmware Rev Info' -A 2 | sed -n '2p'` + 0))", +} + +BIOS_VERSION_PATH = "/sys/class/dmi/id/bios_version" +COMPONENT_LIST= [ + ("CPLD1", "CPLD 1"), + ("CPLD2", "CPLD 2"), + ("BIOS", "Basic Input/Output System"), + ("BMC", "BMC"), +] + +class Component(ComponentBase): + """Platform-specific Component class""" + + DEVICE_TYPE = "component" + + def __init__(self, component_index=0): + self.pddf_obj = pddfapi.PddfApi() + self.index = component_index + self.name = self.get_name() + + def _get_bios_version(self): + # Retrieves the BIOS firmware version + try: + with open(BIOS_VERSION_PATH, 'r') as fd: + bios_version = fd.read() + return bios_version.strip() + except Exception as e: + return None + + def _get_cpld_version(self): + # Retrieves the CPLD firmware version + cpld_version = dict() + for cpld_name, elem in CPLD_SYSFS.items(): + device = "SYSSTATUS" + major = self.pddf_obj.get_attr_name_output(device, elem["major"]) + minor = self.pddf_obj.get_attr_name_output(device, elem["minor"]) + build = self.pddf_obj.get_attr_name_output(device, elem["build"]) + if major and minor and build: + major = int(major['status'].rstrip(),0) + minor = int(minor['status'].rstrip(),0) + build = int(build['status'].rstrip(),0) + cpld_version[cpld_name] = "{}.{:02d}.{:03d}".format(major, minor, build) + else: + cpld_version[cpld_name] = "N/A" + return cpld_version + + def _get_bmc_version(self): + # Retrieves the BMC firmware version + bmc_ver = dict() + for ver in BMC_CMDS: + status, value = subprocess.getstatusoutput(BMC_CMDS[ver]) + if not status: + bmc_ver[ver] = int(value.rstrip()) + else: + return None + + bmc_version = "{}.{}.{}".format(bmc_ver["VER1"], bmc_ver["VER2"], bmc_ver["VER3"]) + + return bmc_version + + def get_name(self): + """ + Retrieves the name of the component + Returns: + A string containing the name of the component + """ + return COMPONENT_LIST[self.index][0] + + def get_description(self): + """ + Retrieves the description of the component + Returns: + A string containing the description of the component + """ + return COMPONENT_LIST[self.index][1] + + def get_firmware_version(self): + """ + Retrieves the firmware version of module + Returns: + string: The firmware versions of the module + """ + fw_version = None + + if self.name == "BIOS": + fw_version = self._get_bios_version() + elif "CPLD" in self.name: + cpld_version = self._get_cpld_version() + fw_version = cpld_version.get(self.name) + elif self.name == "BMC": + fw_version = self._get_bmc_version() + return fw_version + + def install_firmware(self, image_path): + """ + Install firmware to module + Args: + image_path: A string, path to firmware image + Returns: + A boolean, True if install successfully, False if not + """ + raise NotImplementedError diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/sonic_platform/eeprom.py b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/sonic_platform/eeprom.py new file mode 100644 index 000000000000..90ab1c779a48 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/sonic_platform/eeprom.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python + +try: + from sonic_platform_pddf_base.pddf_eeprom import PddfEeprom +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + + +class Eeprom(PddfEeprom): + + def __init__(self, pddf_data=None, pddf_plugin_data=None): + PddfEeprom.__init__(self, pddf_data, pddf_plugin_data) + + # Provide the functions/variables below for which implementation is to be overwritten + + def platform_name_str(self): + (is_valid, results) = self.get_tlv_field(self.eeprom_data, self._TLV_CODE_PLATFORM_NAME) + if not is_valid: + return "N/A" + + return results[2].decode('ascii') \ No newline at end of file diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/sonic_platform/fan.py b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/sonic_platform/fan.py new file mode 100644 index 000000000000..c3cb875646b0 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/sonic_platform/fan.py @@ -0,0 +1,158 @@ +#!/usr/bin/env python + + +try: + from sonic_platform_pddf_base.pddf_fan import PddfFan +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + + +class Fan(PddfFan): + """PDDF Platform-Specific Fan class""" + + def __init__(self, tray_idx, fan_idx=0, pddf_data=None, pddf_plugin_data=None, is_psu_fan=False, psu_index=0): + # idx is 0-based + PddfFan.__init__(self, tray_idx, fan_idx, pddf_data, pddf_plugin_data, is_psu_fan, psu_index) + + # Provide the functions/variables below for which implementation is to be overwritten + # Since psu_fan airflow direction cant be read from sysfs, it is fixed as 'F2B' or 'intake' + + def get_mfr_id(self): + """ + Retrieves the manufacturer id of the device + + Returns: + string: Manufacturer Id of device + """ + if self.is_psu_fan: + device = "PSU{}".format(self.fans_psu_index) + output = self.pddf_obj.get_attr_name_output(device, "psu_mfr_id") + else: + raise NotImplementedError + + if not output: + return None + + mfr = output['status'] + + # strip_non_ascii + stripped = (c for c in mfr if 0 < ord(c) < 127) + mfr = ''.join(stripped) + + return mfr.rstrip('\n') + + def get_model(self): + """ + Retrieves the model number (or part number) of the device + + Returns: + string: Model/part number of device + """ + if self.is_psu_fan: + device = "PSU{}".format(self.fans_psu_index) + output = self.pddf_obj.get_attr_name_output(device, "psu_model_name") + else: + raise NotImplementedError + + if not output: + return None + + model = output['status'] + + # strip_non_ascii + stripped = (c for c in model if 0 < ord(c) < 127) + model = ''.join(stripped) + + return model.rstrip('\n') + + def get_max_speed(self): + """ + Retrieves the max speed + + Returns: + An Integer, the max speed + """ + if self.is_psu_fan: + mfr = self.get_mfr_id() + model = self.get_model() + + max_speed = int(self.plugin_data['PSU']['valmap']['PSU_FAN_MAX_SPEED_AC']) + if mfr and model : + for dev in self.plugin_data['PSU']['psu_support_list']: + if dev['Manufacturer'] == mfr and dev['Name'] == model: + max_speed = int(self.plugin_data['PSU']['valmap'][dev['MaxSpd']]) + break + else: + max_speed = int(self.plugin_data['FAN']['FAN_MAX_SPEED']) + + return max_speed + + def get_speed(self): + """ + Retrieves the speed of fan as a percentage of full speed + + Returns: + An integer, the percentage of full fan speed, in the range 0 (off) + to 100 (full speed) + """ + speed_percentage = 0 + + max_speed = self.get_max_speed() + rpm_speed = self.get_speed_rpm() + + speed_percentage = round((rpm_speed*100)/max_speed) + + return min(speed_percentage, 100) + + def get_presence(self): + """ + Retrieves the presence of the device + Returns: + bool: True if device is present, False if not + """ + if self.is_psu_fan: + attr_name = "psu_present" + device = "PSU{}".format(self.fans_psu_index) + else: + idx = (self.fantray_index-1)*self.platform['num_fans_pertray'] + self.fan_index + attr_name = "fan" + str(idx) + "_present" + device = "FAN-CTRL" + + output = self.pddf_obj.get_attr_name_output(device, attr_name) + if not output: + return False + + mode = output['mode'] + presence = output['status'].rstrip() + vmap = self.plugin_data['FAN']['present'][mode]['valmap'] + + if presence in vmap: + status = vmap[presence] + else: + status = False + + return status + + def get_target_speed(self): + """ + Retrieves the target (expected) speed of the fan + Returns: + An integer, the percentage of full fan speed, in the range 0 (off) + to 100 (full speed) + """ + return self.get_speed() + + def set_speed(self, speed): + """ + Sets the fan speed + + Args: + speed: An integer, the percentage of full fan speed to set fan to, + in the range 0 (off) to 100 (full speed) + + Returns: + A boolean, True if speed is set successfully, False if not + """ + + print("Setting Fan speed is not allowed") + return False diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/sonic_platform/fan_drawer.py b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/sonic_platform/fan_drawer.py new file mode 100644 index 000000000000..3b9bb607f632 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/sonic_platform/fan_drawer.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python + + +try: + from sonic_platform_pddf_base.pddf_fan_drawer import PddfFanDrawer +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + + +class FanDrawer(PddfFanDrawer): + """PDDF Platform-Specific Fan-Drawer class""" + + def __init__(self, tray_idx, pddf_data=None, pddf_plugin_data=None): + # idx is 0-based + PddfFanDrawer.__init__(self, tray_idx, pddf_data, pddf_plugin_data) + + # Provide the functions/variables below for which implementation is to be overwritten diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/sonic_platform/platform.py b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/sonic_platform/platform.py new file mode 100644 index 000000000000..406b1179ae1b --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/sonic_platform/platform.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python + +############################################################################# +# PDDF +# Module contains an implementation of SONiC Platform Base API and +# provides the platform information +# +############################################################################# + + +try: + from sonic_platform_pddf_base.pddf_platform import PddfPlatform +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + + +class Platform(PddfPlatform): + """ + PDDF Platform-Specific Platform Class + """ + + def __init__(self): + PddfPlatform.__init__(self) + + # Provide the functions/variables below for which implementation is to be overwritten diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/sonic_platform/psu.py b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/sonic_platform/psu.py new file mode 100644 index 000000000000..38b32412d024 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/sonic_platform/psu.py @@ -0,0 +1,38 @@ +#!/usr/bin/env python + + +try: + from sonic_platform_pddf_base.pddf_psu import PddfPsu +except ImportError as e: + raise ImportError (str(e) + "- required module not found") + + +class Psu(PddfPsu): + """PDDF Platform-Specific PSU class""" + + PLATFORM_PSU_CAPACITY = 450 + + def __init__(self, index, pddf_data=None, pddf_plugin_data=None): + PddfPsu.__init__(self, index, pddf_data, pddf_plugin_data) + + # Provide the functions/variables below for which implementation is to be overwritten + def get_maximum_supplied_power(self): + """ + Retrieves the maximum supplied power by PSU (or PSU capacity) + Returns: + A float number, the maximum power output in Watts. + e.g. 1200.1 + """ + return float(self.PLATFORM_PSU_CAPACITY) + + def get_power(self): + """ + Retrieves current energy supplied by PSU + + Returns: + A float number, the power in watts, + e.g. 302.6 + """ + + # power is returned in micro watts + return round(float(self.get_voltage()*self.get_current()), 2) diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/sonic_platform/sfp.py b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/sonic_platform/sfp.py new file mode 100644 index 000000000000..8ab43117d54c --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/sonic_platform/sfp.py @@ -0,0 +1,49 @@ +#!/usr/bin/env python + +try: + from sonic_platform_pddf_base.pddf_sfp import PddfSfp +except ImportError as e: + raise ImportError (str(e) + "- required module not found") + + +class Sfp(PddfSfp): + """ + PDDF Platform-Specific Sfp class + """ + + def __init__(self, index, pddf_data=None, pddf_plugin_data=None): + PddfSfp.__init__(self, index, pddf_data, pddf_plugin_data) + self.index = index + + # Provide the functions/variables below for which implementation is to be overwritten + + def get_lpmode(self): + if self.sfp_type == "QSFP28": + return super().get_lpmode() + else: + return False + + def set_lpmode(self, lpmode): + if self.sfp_type == "QSFP28": + return super().set_lpmode(lpmode) + else: + return False + + def reset(self): + if self.sfp_type == "QSFP28": + return super().reset() + else: + return False + + def get_error_description(self): + """ + Retrives the error descriptions of the SFP module + Returns: + String that represents the current error descriptions of vendor specific errors + In case there are multiple errors, they should be joined by '|', + like: "Bad EEPROM|Unsupported cable" + """ + if not self.get_presence(): + return self.SFP_STATUS_UNPLUGGED + + return self.SFP_STATUS_OK diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/sonic_platform/thermal.py b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/sonic_platform/thermal.py new file mode 100644 index 000000000000..77d6ec7ae886 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/sonic_platform/thermal.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python + + +try: + from sonic_platform_pddf_base.pddf_thermal import PddfThermal +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + + + +class Thermal(PddfThermal): + """PDDF Platform-Specific Thermal class""" + + def __init__(self, index, pddf_data=None, pddf_plugin_data=None, is_psu_thermal=False, psu_index=0): + PddfThermal.__init__(self, index, pddf_data, pddf_plugin_data, is_psu_thermal, psu_index) + + # Provide the functions/variables below for which implementation is to be overwritten diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/sonic_platform_setup.py b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/sonic_platform_setup.py new file mode 100644 index 000000000000..c0a485320cb7 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/sonic_platform_setup.py @@ -0,0 +1,27 @@ +from setuptools import setup + +setup( + name='sonic-platform', + version='1.0', + description='SONiC platform API implementation on ufispace platform', + license='Apache 2.0', + author='SONiC Team', + author_email='linuxnetdev@microsoft.com', + url='https://github.com/Azure/sonic-buildimage', + maintainer='Jason Tsai', + maintainer_email='jason.cy.tsai@ufispace.com', + packages=['sonic_platform'], + classifiers=[ + 'Development Status :: 3 - Alpha', + 'Environment :: Plugins', + 'Intended Audience :: Developers', + 'Intended Audience :: Information Technology', + 'Intended Audience :: System Administrators', + 'License :: OSI Approved :: Apache Software License', + 'Natural Language :: English', + 'Operating System :: POSIX :: Linux', + 'Programming Language :: Python :: 3.7', + 'Topic :: Utilities', + ], + keywords='sonic SONiC platform PLATFORM', +) diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/utils/pddf_post_device_create.sh b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/utils/pddf_post_device_create.sh new file mode 100755 index 000000000000..4a55252ea936 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/utils/pddf_post_device_create.sh @@ -0,0 +1,16 @@ +#!/bin/bash + +#disable bmc watchdog +echo "Disable BMC watchdog" +timeout 3 ipmitool mc watchdog off + +pddf_ledutil setstatusled SYNC_LED off +pddf_ledutil setstatusled SYS_LED off +pddf_ledutil setstatusled ID_LED off + +#set status led to green to indicate platform init done +curr_led=$(pddf_ledutil getstatusled SYS_LED) +pddf_ledutil setstatusled SYS_LED green +echo "Set SYS_LED from $curr_led to green" + +echo "PDDF device post-create completed" diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/utils/pddf_post_driver_install.sh b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/utils/pddf_post_driver_install.sh new file mode 100755 index 000000000000..ed2559977e42 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/utils/pddf_post_driver_install.sh @@ -0,0 +1,2 @@ +#!/bin/bash +echo "PDDF driver post-install completed" diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/utils/pddf_pre_driver_install.sh b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/utils/pddf_pre_driver_install.sh new file mode 100755 index 000000000000..9ada6c235c48 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/utils/pddf_pre_driver_install.sh @@ -0,0 +1,8 @@ +#!/bin/bash +#rmmod gpio_ich +if [ ! -f /tmp/._pddf_pre_driver_init_completion ]; then + rmmod i2c_i801 + rmmod i2c_ismt + date > /tmp/._pddf_pre_driver_init_completion +fi +echo "PDDF driver pre-install completed" diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/utils/pddf_switch_svc.py b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/utils/pddf_switch_svc.py new file mode 100755 index 000000000000..ca34fe9442c9 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/utils/pddf_switch_svc.py @@ -0,0 +1,50 @@ +#!/usr/bin/env python +# Script to stop and start the respective platforms default services. +# This will be used while switching the pddf->non-pddf mode and vice versa +import commands + +def check_pddf_support(): + return True + +def stop_platform_svc(): + + status, output = commands.getstatusoutput("/usr/local/bin/platform_utility.py deinit") + if status: + print "platform_utility.py deinit command failed %d"%status + return False + + # HACK , stop the pddf-platform-init service if it is active + status, output = commands.getstatusoutput("systemctl stop pddf-platform-init.service") + if status: + print "Stop pddf-platform-init.service along with other platform serives failed %d"%status + return False + + return True + +def start_platform_svc(): + + status, output = commands.getstatusoutput("/usr/local/bin/platform_utility.py init") + if status: + print "platform_utility.py init command failed %d"%status + return False + + return True + +def start_platform_pddf(): + + status, output = commands.getstatusoutput("systemctl start pddf-platform-init.service") + if status: + print "Start pddf-platform-init.service failed %d"%status + return False + + return True + +def stop_platform_pddf(): + + status, output = commands.getstatusoutput("systemctl stop pddf-platform-init.service") + if status: + print "Stop pddf-platform-init.service failed %d"%status + return False + + return True + diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/utils/pre_pddf_init.sh b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/utils/pre_pddf_init.sh new file mode 100755 index 000000000000..63a2e205808e --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s7801-54xs/utils/pre_pddf_init.sh @@ -0,0 +1,5 @@ +#!/bin/bash +#rmmod gpio_ich +modprobe -rq i2c_i801 +modprobe -rq i2c_smbus +echo "Pre PDDF init steps completed successully" diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/modules/Makefile b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/modules/Makefile new file mode 100644 index 000000000000..e441986ded77 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/modules/Makefile @@ -0,0 +1,6 @@ + +MODULE_NAME = x86-64-ufispace-s8901-54xc-cpld.o x86-64-ufispace-s8901-54xc-sys-eeprom.o x86-64-ufispace-s8901-54xc-lpc.o pddf_custom_sysstatus_module.o +obj-m := $(MODULE_NAME) + +CFLAGS_pddf_custom_sysstatus_module.o := -I$(M)/../../../../pddf/i2c/modules/include +KBUILD_EXTRA_SYMBOLS := $(M)/../../../../pddf/i2c/Module.symvers.PDDF diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/modules/pddf_custom_sysstatus_module.c b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/modules/pddf_custom_sysstatus_module.c new file mode 100644 index 000000000000..b50bb428000a --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/modules/pddf_custom_sysstatus_module.c @@ -0,0 +1,276 @@ +/* + * Copyright 2019 Broadcom. + * The term ��Broadcom�� refers to Broadcom Inc. and/or its subsidiaries. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * A pddf kernel module for system status registers + */ + +#define __STDC_WANT_LIB_EXT1__ 1 +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../../../../pddf/i2c/modules/include/pddf_client_defs.h" +#include "../../../../pddf/i2c/modules/include/pddf_sysstatus_defs.h" + + +SYSSTATUS_DATA sysstatus_data = {0}; + +extern int board_i2c_cpld_read(unsigned short cpld_addr, u8 reg); +extern int board_i2c_cpld_write(unsigned short cpld_addr, u8 reg, u8 value); + +static ssize_t do_attr_operation(struct device *dev, struct device_attribute *da, const char *buf, size_t count); +ssize_t show_sysstatus_data(struct device *dev, struct device_attribute *da, char *buf); +ssize_t store_sysstatus_data(struct device *dev, struct device_attribute *da, const char *buf, size_t count); + + +PDDF_DATA_ATTR(attr_name, S_IWUSR|S_IRUGO, show_pddf_data, store_pddf_data, PDDF_CHAR, 32, + (void*)&sysstatus_data.sysstatus_addr_attr.aname, NULL); +PDDF_DATA_ATTR(attr_devaddr, S_IWUSR|S_IRUGO, show_pddf_data, store_pddf_data, PDDF_UINT32, + sizeof(uint32_t), (void*)&sysstatus_data.sysstatus_addr_attr.devaddr , NULL); +PDDF_DATA_ATTR(attr_offset, S_IWUSR|S_IRUGO, show_pddf_data, store_pddf_data, PDDF_UINT32, + sizeof(uint32_t), (void*)&sysstatus_data.sysstatus_addr_attr.offset, NULL); +PDDF_DATA_ATTR(attr_mask, S_IWUSR|S_IRUGO, show_pddf_data, store_pddf_data, PDDF_UINT32, + sizeof(uint32_t), (void*)&sysstatus_data.sysstatus_addr_attr.mask , NULL); +PDDF_DATA_ATTR(attr_len, S_IWUSR|S_IRUGO, show_pddf_data, store_pddf_data, PDDF_UINT32, + sizeof(uint32_t), (void*)&sysstatus_data.sysstatus_addr_attr.len , NULL); +PDDF_DATA_ATTR(attr_ops, S_IWUSR, NULL, do_attr_operation, PDDF_CHAR, 8, (void*)&sysstatus_data, NULL); + + + +static struct attribute *sysstatus_addr_attributes[] = { + &attr_attr_name.dev_attr.attr, + &attr_attr_devaddr.dev_attr.attr, + &attr_attr_offset.dev_attr.attr, + &attr_attr_mask.dev_attr.attr, + &attr_attr_len.dev_attr.attr, + &attr_attr_ops.dev_attr.attr, + NULL +}; + +PDDF_DATA_ATTR(board_sku_id , S_IRUGO, show_sysstatus_data, NULL, PDDF_UCHAR, sizeof(u8), NULL, NULL); +PDDF_DATA_ATTR(board_hw_id , S_IRUGO, show_sysstatus_data, NULL, PDDF_UCHAR, sizeof(u8), NULL, NULL); +PDDF_DATA_ATTR(board_deph_id , S_IRUGO, show_sysstatus_data, NULL, PDDF_UCHAR, sizeof(u8), NULL, NULL); +PDDF_DATA_ATTR(board_build_id , S_IRUGO, show_sysstatus_data, NULL, PDDF_UCHAR, sizeof(u8), NULL, NULL); +PDDF_DATA_ATTR(cpld1_major_ver, S_IRUGO, show_sysstatus_data, NULL, PDDF_UCHAR, sizeof(u8), NULL, NULL); +PDDF_DATA_ATTR(cpld1_minor_ver, S_IRUGO, show_sysstatus_data, NULL, PDDF_UCHAR, sizeof(u8), NULL, NULL); +PDDF_DATA_ATTR(cpld1_build , S_IRUGO, show_sysstatus_data, NULL, PDDF_UCHAR, sizeof(u8), NULL, NULL); +PDDF_DATA_ATTR(cpld2_major_ver, S_IRUGO, show_sysstatus_data, NULL, PDDF_UCHAR, sizeof(u8), NULL, NULL); +PDDF_DATA_ATTR(cpld2_minor_ver, S_IRUGO, show_sysstatus_data, NULL, PDDF_UCHAR, sizeof(u8), NULL, NULL); +PDDF_DATA_ATTR(cpld2_build , S_IRUGO, show_sysstatus_data, NULL, PDDF_UCHAR, sizeof(u8), NULL, NULL); +PDDF_DATA_ATTR(psu_status , S_IRUGO, show_sysstatus_data, NULL, PDDF_UCHAR, sizeof(u8), NULL, NULL); +PDDF_DATA_ATTR(system_led_psu , S_IRUGO, show_sysstatus_data, NULL, PDDF_UCHAR, sizeof(u8), NULL, NULL); +PDDF_DATA_ATTR(system_led_sys , S_IWUSR|S_IRUGO, show_sysstatus_data, store_sysstatus_data, PDDF_UCHAR, sizeof(u8), NULL, NULL); +PDDF_DATA_ATTR(system_led_sync, S_IRUGO, show_sysstatus_data, NULL, PDDF_UCHAR, sizeof(u8), NULL, NULL); +PDDF_DATA_ATTR(system_led_fan , S_IRUGO, show_sysstatus_data, NULL, PDDF_UCHAR, sizeof(u8), NULL, NULL); +PDDF_DATA_ATTR(system_led_id , S_IWUSR|S_IRUGO, show_sysstatus_data, store_sysstatus_data, PDDF_UCHAR, sizeof(u8), NULL, NULL); + +static struct attribute *sysstatus_data_attributes[] = { + &attr_board_sku_id.dev_attr.attr, + &attr_board_hw_id.dev_attr.attr, + &attr_board_deph_id.dev_attr.attr, + &attr_board_build_id.dev_attr.attr, + &attr_cpld1_major_ver.dev_attr.attr, + &attr_cpld1_minor_ver.dev_attr.attr, + &attr_cpld1_build.dev_attr.attr, + &attr_cpld2_major_ver.dev_attr.attr, + &attr_cpld2_minor_ver.dev_attr.attr, + &attr_cpld2_build.dev_attr.attr, + &attr_psu_status.dev_attr.attr, + &attr_system_led_psu.dev_attr.attr, + &attr_system_led_sys.dev_attr.attr, + &attr_system_led_sync.dev_attr.attr, + &attr_system_led_fan.dev_attr.attr, + &attr_system_led_id.dev_attr.attr, + NULL +}; + + +static const struct attribute_group pddf_sysstatus_addr_group = { + .attrs = sysstatus_addr_attributes, +}; + + +static const struct attribute_group pddf_sysstatus_data_group = { + .attrs = sysstatus_data_attributes, +}; + + +static struct kobject *sysstatus_addr_kobj; +static struct kobject *sysstatus_data_kobj; + + + +ssize_t show_sysstatus_data(struct device *dev, struct device_attribute *da, char *buf) +{ + + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + + SYSSTATUS_DATA *data = &sysstatus_data; + struct SYSSTATUS_ADDR_ATTR *sysstatus_addr_attrs = NULL; + int i, status ; + + + for (i=0;isysstatus_addr_attrs[i].aname, attr->dev_attr.attr.name) == 0 ) + { + sysstatus_addr_attrs = &data->sysstatus_addr_attrs[i]; + + } + } + + if (sysstatus_addr_attrs==NULL ) + { + printk(KERN_DEBUG "%s is not supported attribute for this client\n",data->sysstatus_addr_attrs[i].aname); + status = 0; + } + else + { + status = board_i2c_cpld_read( sysstatus_addr_attrs->devaddr, sysstatus_addr_attrs->offset); + } + + return sprintf(buf, "0x%x\n", (status&sysstatus_addr_attrs->mask)); + +} + +ssize_t store_sysstatus_data(struct device *dev, struct device_attribute *da, const char *buf, size_t count) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + + SYSSTATUS_DATA *data = &sysstatus_data; + struct SYSSTATUS_ADDR_ATTR *sysstatus_addr_attrs = NULL; + int i, status ; + u8 reg_val; + + for (i=0;isysstatus_addr_attrs[i].aname, attr->dev_attr.attr.name) == 0 ) + { + sysstatus_addr_attrs = &data->sysstatus_addr_attrs[i]; + } + } + + if (sysstatus_addr_attrs==NULL) + { + printk(KERN_DEBUG "%s is not supported attribute for this client\n",data->sysstatus_addr_attrs[i].aname); + return -EINVAL; + } + else + { + if (kstrtou8(buf, 0, ®_val) < 0) + return -EINVAL; + + status = board_i2c_cpld_write(sysstatus_addr_attrs->devaddr, sysstatus_addr_attrs->offset, reg_val); + + if (status!=0) + { + printk(KERN_DEBUG "store_sysstatus_data() %s failed, status=%d\n",data->sysstatus_addr_attrs[i].aname, status); + return status; + } + } + + return count; +} + + + +static ssize_t do_attr_operation(struct device *dev, struct device_attribute *da, const char *buf, size_t count) +{ + PDDF_ATTR *ptr = (PDDF_ATTR *)da; + SYSSTATUS_DATA *pdata = (SYSSTATUS_DATA *)(ptr->addr); + + pdata->sysstatus_addr_attrs[pdata->len] = pdata->sysstatus_addr_attr; + pdata->len++; + pddf_dbg(SYSSTATUS, KERN_ERR "%s: Populating the data for %s\n", __FUNCTION__, pdata->sysstatus_addr_attr.aname); + +#ifdef __STDC_LIB_EXT1__ + memset_s(&pdata->sysstatus_addr_attr, sizeof(pdata->sysstatus_addr_attr, 0, sizeof(pdata->sysstatus_addr_attr)); +#else + memset(&pdata->sysstatus_addr_attr, 0, sizeof(pdata->sysstatus_addr_attr)); +#endif + + return count; +} + + + + +int __init sysstatus_data_init(void) +{ + struct kobject *device_kobj; + int ret = 0; + + + pddf_dbg(SYSSTATUS, "PDDF SYSSTATUS MODULE.. init\n"); + + device_kobj = get_device_i2c_kobj(); + if(!device_kobj) + return -ENOMEM; + + sysstatus_addr_kobj = kobject_create_and_add("sysstatus", device_kobj); + if(!sysstatus_addr_kobj) + return -ENOMEM; + + sysstatus_data_kobj = kobject_create_and_add("sysstatus_data", sysstatus_addr_kobj); + if(!sysstatus_data_kobj) + return -ENOMEM; + + + ret = sysfs_create_group(sysstatus_addr_kobj, &pddf_sysstatus_addr_group); + if (ret) + { + kobject_put(sysstatus_addr_kobj); + return ret; + } + + ret = sysfs_create_group(sysstatus_data_kobj, &pddf_sysstatus_data_group); + if (ret) + { + sysfs_remove_group(sysstatus_addr_kobj, &pddf_sysstatus_addr_group); + kobject_put(sysstatus_data_kobj); + kobject_put(sysstatus_addr_kobj); + return ret; + } + + + return ret; +} + +void __exit sysstatus_data_exit(void) +{ + pddf_dbg(SYSSTATUS, "PDDF SYSSTATUS MODULE.. exit\n"); + sysfs_remove_group(sysstatus_data_kobj, &pddf_sysstatus_data_group); + sysfs_remove_group(sysstatus_addr_kobj, &pddf_sysstatus_addr_group); + kobject_put(sysstatus_data_kobj); + kobject_put(sysstatus_addr_kobj); + pddf_dbg(SYSSTATUS, KERN_ERR "%s: Removed the kobjects for 'SYSSTATUS'\n",__FUNCTION__); + return; +} + +module_init(sysstatus_data_init); +module_exit(sysstatus_data_exit); + +MODULE_AUTHOR("Broadcom"); +MODULE_DESCRIPTION("SYSSTATUS platform data"); +MODULE_LICENSE("GPL"); diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/modules/x86-64-ufispace-s8901-54xc-cpld.c b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/modules/x86-64-ufispace-s8901-54xc-cpld.c new file mode 100644 index 000000000000..63eec91d4819 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/modules/x86-64-ufispace-s8901-54xc-cpld.c @@ -0,0 +1,1512 @@ +/* + * A i2c cpld driver for the ufispace_s8901_54xc + * + * Copyright (C) 2017-2022 UfiSpace Technology Corporation. + * Jason Tsai + * + * Based on ad7414.c + * Copyright 2006 Stefan Roese , DENX Software Engineering + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "x86-64-ufispace-s8901-54xc-cpld.h" + +#ifdef DEBUG +#define DEBUG_PRINT(fmt, args...) \ + printk(KERN_INFO "%s:%s[%d]: " fmt "\r\n", \ + __FILE__, __func__, __LINE__, ##args) +#else +#define DEBUG_PRINT(fmt, args...) +#endif + +#define BSP_LOG_R(fmt, args...) \ + _bsp_log (LOG_READ, KERN_INFO "%s:%s[%d]: " fmt "\r\n", \ + __FILE__, __func__, __LINE__, ##args) +#define BSP_LOG_W(fmt, args...) \ + _bsp_log (LOG_WRITE, KERN_INFO "%s:%s[%d]: " fmt "\r\n", \ + __FILE__, __func__, __LINE__, ##args) + +#define I2C_READ_BYTE_DATA(ret, lock, i2c_client, reg) \ +{ \ + mutex_lock(lock); \ + ret = i2c_smbus_read_byte_data(i2c_client, reg); \ + mutex_unlock(lock); \ + BSP_LOG_R("cpld[%d], reg=0x%03x, reg_val=0x%02x", data->index, reg, ret); \ +} + +#define I2C_WRITE_BYTE_DATA(ret, lock, i2c_client, reg, val) \ +{ \ + mutex_lock(lock); \ + ret = i2c_smbus_write_byte_data(i2c_client, reg, val); \ + mutex_unlock(lock); \ + BSP_LOG_W("cpld[%d], reg=0x%03x, reg_val=0x%02x", data->index, reg, val); \ +} + +#define _SENSOR_DEVICE_ATTR_RO(_name, _func, _index) \ + SENSOR_DEVICE_ATTR(_name, S_IRUGO, read_##_func, NULL, _index) + +#define _SENSOR_DEVICE_ATTR_WO(_name, _func, _index) \ + SENSOR_DEVICE_ATTR(_name, S_IWUSR, NULL, write_##_func, _index) + +#define _SENSOR_DEVICE_ATTR_RW(_name, _func, _index) \ + SENSOR_DEVICE_ATTR(_name, S_IRUGO | S_IWUSR, read_##_func, write_##_func, _index) + +#define _DEVICE_ATTR(_name) \ + &sensor_dev_attr_##_name.dev_attr.attr + +#define I2C_RW_RETRY_COUNT 3 +#define I2C_RW_RETRY_INTERVAL 60 + +/* CPLD sysfs attributes index */ +enum cpld_sysfs_attributes { + //CPLD 1 + + CPLD_BOARD_ID_0, + CPLD_BOARD_ID_1, + CPLD_ID, + CPLD_CHIP, + CPLD_SKU_EXT, + + CPLD_MAJOR_VER, + CPLD_MINOR_VER, + CPLD_BUILD_VER, + CPLD_VERSION_H, + + CPLD_MAC_INTR, + CPLD_HWM_INTR, + CPLD_CPLD2_INTR, + CPLD_NTM_INTR, + CPLD_FAN_PSU_INTR, + CPLD_SFP_IOEXP_INTR, + CPLD_CPU_NMI_INTR, + CPLD_PTP_INTR, + CPLD_SYSTEM_INTR, + + CPLD_MAC_MASK, + CPLD_HWM_MASK, + CPLD_CPLD2_MASK, + CPLD_NTM_MASK, + CPLD_FAN_PSU_MASK, + CPLD_SFP_IOEXP_MASK, + CPLD_CPU_NMI_MASK, + CPLD_PTP_MASK, + CPLD_SYSTEM_MASK, + + CPLD_MAC_EVT, + CPLD_HWM_EVT, + CPLD_CPLD2_EVT, + CPLD_NTM_EVT, + CPLD_FAN_PSU_EVT, + CPLD_SFP_IOEXP_EVT, + CPLD_CPU_NMI_EVT, + CPLD_PTP_EVT, + + CPLD_EVT_CTRL, + + CPLD_MAC_RESET, + CPLD_SYSTEM_RESET, + CPLD_BMC_NTM_RESET, + CPLD_USB_RESET, + CPLD_I2C_MUX_RESET, + CPLD_I2C_MUX_RESET_2, + CPLD_MISC_RESET, + + CPLD_BRD_PRESENT, + CPLD_PSU_STATUS, + CPLD_SYSTEM_PWR, + CPLD_MAC_SYNCE, + CPLD_MAC_AVS, + CPLD_SYSTEM_STATUS, + CPLD_FAN_PRESENT, + CPLD_WATCHDOG, + CPLD_BOOT_SELECT, + CPLD_MUX_CTRL, + CPLD_MISC_CTRL_1, + CPLD_MISC_CTRL_2, + CPLD_TIMING_CTRL, + + CPLD_MAC_TEMP, + + CPLD_SYSTEM_LED_SYNC, + CPLD_SYSTEM_LED_SYS, + CPLD_SYSTEM_LED_FAN, + CPLD_SYSTEM_LED_PSU_0, + CPLD_SYSTEM_LED_PSU_1, + CPLD_SYSTEM_LED_ID, + + DBG_CPLD_MAC_INTR, + DBG_CPLD_HWM_INTR, + DBG_CPLD_CPLD2_INTR, + DBG_CPLD_NTM_INTR, + DBG_CPLD_FAN_PSU_INTR, + DBG_CPLD_SFP_IOEXP_INTR, + DBG_CPLD_PTP_INTR, + + //CPLD 2 + + //interrupt status + CPLD_SFP_INTR_PRESENT_0_7, + CPLD_SFP_INTR_PRESENT_8_15, + CPLD_SFP_INTR_PRESENT_16_23, + CPLD_SFP_INTR_PRESENT_24_31, + CPLD_SFP_INTR_PRESENT_32_39, + CPLD_SFP_INTR_PRESENT_40_47, + CPLD_QSFP_INTR_PRESENT_48_53, + CPLD_QSFP_INTR_PORT_48_53, + + //interrupt mask + CPLD_SFP_MASK_PRESENT_0_7, + CPLD_SFP_MASK_PRESENT_8_15, + CPLD_SFP_MASK_PRESENT_16_23, + CPLD_SFP_MASK_PRESENT_24_31, + CPLD_SFP_MASK_PRESENT_32_39, + CPLD_SFP_MASK_PRESENT_40_47, + CPLD_QSFP_MASK_PRESENT_48_53, + CPLD_QSFP_MASK_PORT_48_53, + + //interrupt event + CPLD_SFP_EVT_PRESENT_0_7, + CPLD_SFP_EVT_PRESENT_8_15, + CPLD_SFP_EVT_PRESENT_16_23, + CPLD_SFP_EVT_PRESENT_24_31, + CPLD_SFP_EVT_PRESENT_32_39, + CPLD_SFP_EVT_PRESENT_40_47, + CPLD_QSFP_EVT_PRESENT_48_53, + CPLD_QSFP_EVT_PORT_48_53, + + CPLD_SFP_INTR_RX_LOS_0_7, + CPLD_SFP_INTR_RX_LOS_8_15, + CPLD_SFP_INTR_RX_LOS_16_23, + CPLD_SFP_INTR_RX_LOS_24_31, + CPLD_SFP_INTR_RX_LOS_32_39, + CPLD_SFP_INTR_RX_LOS_40_47, + + CPLD_SFP_INTR_TX_FAULT_0_7, + CPLD_SFP_INTR_TX_FAULT_8_15, + CPLD_SFP_INTR_TX_FAULT_16_23, + CPLD_SFP_INTR_TX_FAULT_24_31, + CPLD_SFP_INTR_TX_FAULT_32_39, + CPLD_SFP_INTR_TX_FAULT_40_47, + + CPLD_SFP_MASK_RX_LOS_0_7, + CPLD_SFP_MASK_RX_LOS_8_15, + CPLD_SFP_MASK_RX_LOS_16_23, + CPLD_SFP_MASK_RX_LOS_24_31, + CPLD_SFP_MASK_RX_LOS_32_39, + CPLD_SFP_MASK_RX_LOS_40_47, + + CPLD_SFP_MASK_TX_FAULT_0_7, + CPLD_SFP_MASK_TX_FAULT_8_15, + CPLD_SFP_MASK_TX_FAULT_16_23, + CPLD_SFP_MASK_TX_FAULT_24_31, + CPLD_SFP_MASK_TX_FAULT_32_39, + CPLD_SFP_MASK_TX_FAULT_40_47, + + CPLD_SFP_EVT_RX_LOS_0_7, + CPLD_SFP_EVT_RX_LOS_8_15, + CPLD_SFP_EVT_RX_LOS_16_23, + CPLD_SFP_EVT_RX_LOS_24_31, + CPLD_SFP_EVT_RX_LOS_32_39, + CPLD_SFP_EVT_RX_LOS_40_47, + + CPLD_SFP_EVT_TX_FAULT_0_7, + CPLD_SFP_EVT_TX_FAULT_8_15, + CPLD_SFP_EVT_TX_FAULT_16_23, + CPLD_SFP_EVT_TX_FAULT_24_31, + CPLD_SFP_EVT_TX_FAULT_32_39, + CPLD_SFP_EVT_TX_FAULT_40_47, + + CPLD_SFP_TX_DISABLE_0_7, + CPLD_SFP_TX_DISABLE_8_15, + CPLD_SFP_TX_DISABLE_16_23, + CPLD_SFP_TX_DISABLE_24_31, + CPLD_SFP_TX_DISABLE_32_39, + CPLD_SFP_TX_DISABLE_40_47, + + CPLD_QSFP_RESET_48_53, + CPLD_QSFP_LPMODE_48_53, + + //debug interrupt status + DBG_CPLD_SFP_INTR_PRESENT_0_7, + DBG_CPLD_SFP_INTR_PRESENT_8_15, + DBG_CPLD_SFP_INTR_PRESENT_16_23, + DBG_CPLD_SFP_INTR_PRESENT_24_31, + DBG_CPLD_SFP_INTR_PRESENT_32_39, + DBG_CPLD_SFP_INTR_PRESENT_40_47, + DBG_CPLD_QSFP_INTR_PRESENT_48_53, + DBG_CPLD_QSFP_INTR_PORT_48_53, + + //debug interrupt mask + DBG_CPLD_SFP_INTR_RX_LOS_0_7, + DBG_CPLD_SFP_INTR_RX_LOS_8_15, + DBG_CPLD_SFP_INTR_RX_LOS_16_23, + DBG_CPLD_SFP_INTR_RX_LOS_24_31, + DBG_CPLD_SFP_INTR_RX_LOS_32_39, + DBG_CPLD_SFP_INTR_RX_LOS_40_47, + + DBG_CPLD_SFP_INTR_TX_FAULT_0_7, + DBG_CPLD_SFP_INTR_TX_FAULT_8_15, + DBG_CPLD_SFP_INTR_TX_FAULT_16_23, + DBG_CPLD_SFP_INTR_TX_FAULT_24_31, + DBG_CPLD_SFP_INTR_TX_FAULT_32_39, + DBG_CPLD_SFP_INTR_TX_FAULT_40_47, + + //BSP DEBUG + BSP_DEBUG +}; + +enum bsp_log_types { + LOG_NONE, + LOG_RW, + LOG_READ, + LOG_WRITE +}; + +enum bsp_log_ctrl { + LOG_DISABLE, + LOG_ENABLE +}; + +/* CPLD sysfs attributes hook functions */ +static ssize_t read_cpld_callback(struct device *dev, + struct device_attribute *da, char *buf); +static ssize_t write_cpld_callback(struct device *dev, + struct device_attribute *da, const char *buf, size_t count); +static u8 _read_cpld_reg(struct device *dev, u8 reg, u8 mask); +static ssize_t read_cpld_reg(struct device *dev, char *buf, u8 reg, u8 mask); +static ssize_t write_cpld_reg(struct device *dev, const char *buf, size_t count, u8 reg, u8 mask); +static ssize_t read_bsp(char *buf, char *str); +static ssize_t write_bsp(const char *buf, char *str, size_t str_len, size_t count); +static ssize_t read_bsp_callback(struct device *dev, + struct device_attribute *da, char *buf); +static ssize_t write_bsp_callback(struct device *dev, + struct device_attribute *da, const char *buf, size_t count); +static ssize_t read_cpld_version_h(struct device *dev, + struct device_attribute *da, + char *buf); + +static LIST_HEAD(cpld_client_list); /* client list for cpld */ +static struct mutex list_lock; /* mutex for client list */ + +struct cpld_client_node { + struct i2c_client *client; + struct list_head list; +}; + +struct cpld_data { + int index; /* CPLD index */ + struct mutex access_lock; /* mutex for cpld access */ + u8 access_reg; /* register to access */ +}; + +typedef struct sysfs_info_s +{ + u8 reg; + u8 mask; + u8 permission; +} sysfs_info_t; + +static sysfs_info_t sysfs_info[] = { + //CPLD 1 + + [CPLD_BOARD_ID_0] = {CPLD_BOARD_ID_0_REG, MASK_ALL, PERM_R}, + [CPLD_BOARD_ID_1] = {CPLD_BOARD_ID_1_REG, MASK_ALL, PERM_R}, + [CPLD_ID] = {CPLD_ID_REG, MASK_ALL, PERM_R}, + [CPLD_CHIP] = {CPLD_CHIP_REG, MASK_ALL, PERM_R}, + [CPLD_SKU_EXT] = {CPLD_SKU_EXT_REG, MASK_ALL, PERM_R}, + + [CPLD_MAJOR_VER] = {CPLD_VERSION_REG, MASK_CPLD_MAJOR_VER, PERM_R}, + [CPLD_MINOR_VER] = {CPLD_VERSION_REG, MASK_CPLD_MINOR_VER, PERM_R}, + [CPLD_BUILD_VER] = {CPLD_BUILD_REG, MASK_ALL, PERM_R}, + [CPLD_VERSION_H] = {CPLD_VERSION_REG, MASK_ALL, PERM_R}, + + [CPLD_MAC_INTR] = {CPLD_MAC_INTR_REG, MASK_ALL, PERM_R}, + [CPLD_HWM_INTR] = {CPLD_HWM_INTR_REG, MASK_ALL, PERM_R}, + [CPLD_CPLD2_INTR] = {CPLD_CPLD2_INTR_REG, MASK_ALL, PERM_R}, + [CPLD_NTM_INTR] = {CPLD_NTM_INTR_REG, MASK_ALL, PERM_R}, + [CPLD_FAN_PSU_INTR] = {CPLD_FAN_PSU_INTR_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_IOEXP_INTR] = {CPLD_SFP_IOEXP_INTR_REG, MASK_ALL, PERM_R}, + [CPLD_CPU_NMI_INTR] = {CPLD_CPU_NMI_INTR_REG, MASK_ALL, PERM_R}, + [CPLD_PTP_INTR] = {CPLD_PTP_INTR_REG, MASK_ALL, PERM_R}, + [CPLD_SYSTEM_INTR] = {CPLD_SYSTEM_INTR_REG, MASK_ALL, PERM_R}, + + [CPLD_MAC_MASK] = {CPLD_MAC_MASK_REG, MASK_ALL, PERM_RW}, + [CPLD_HWM_MASK] = {CPLD_HWM_MASK_REG, MASK_ALL, PERM_RW}, + [CPLD_CPLD2_MASK] = {CPLD_CPLD2_MASK_REG, MASK_ALL, PERM_RW}, + [CPLD_NTM_MASK] = {CPLD_NTM_MASK_REG, MASK_ALL, PERM_RW}, + [CPLD_FAN_PSU_MASK] = {CPLD_FAN_PSU_MASK_REG, MASK_ALL, PERM_RW}, + [CPLD_SFP_IOEXP_MASK] = {CPLD_SFP_IOEXP_MASK_REG, MASK_ALL, PERM_RW}, + [CPLD_CPU_NMI_MASK] = {CPLD_CPU_NMI_MASK_REG, MASK_ALL, PERM_RW}, + [CPLD_PTP_MASK] = {CPLD_PTP_MASK_REG, MASK_ALL, PERM_RW}, + [CPLD_SYSTEM_MASK] = {CPLD_SYSTEM_MASK_REG, MASK_ALL, PERM_RW}, + + [CPLD_MAC_EVT] = {CPLD_MAC_EVT_REG, MASK_ALL, PERM_R}, + [CPLD_HWM_EVT] = {CPLD_HWM_EVT_REG, MASK_ALL, PERM_R}, + [CPLD_CPLD2_EVT] = {CPLD_CPLD2_EVT_REG, MASK_ALL, PERM_R}, + [CPLD_NTM_EVT] = {CPLD_NTM_EVT_REG, MASK_ALL, PERM_R}, + [CPLD_FAN_PSU_EVT] = {CPLD_FAN_PSU_EVT_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_IOEXP_EVT] = {CPLD_SFP_IOEXP_EVT_REG, MASK_ALL, PERM_R}, + [CPLD_CPU_NMI_EVT] = {CPLD_CPU_NMI_EVT_REG, MASK_ALL, PERM_R}, + [CPLD_PTP_EVT] = {CPLD_PTP_EVT_REG, MASK_ALL, PERM_R}, + + [CPLD_EVT_CTRL] = {CPLD_EVT_CTRL_REG, MASK_ALL, PERM_RW}, + + [CPLD_MAC_RESET] = {CPLD_MAC_RESET_REG, MASK_ALL, PERM_RW}, + [CPLD_SYSTEM_RESET] = {CPLD_SYSTEM_RESET_REG, MASK_ALL, PERM_RW}, + [CPLD_BMC_NTM_RESET] = {CPLD_BMC_NTM_RESET_REG, MASK_ALL, PERM_RW}, + [CPLD_USB_RESET] = {CPLD_USB_RESET_REG, MASK_ALL, PERM_RW}, + [CPLD_I2C_MUX_RESET] = {CPLD_I2C_MUX_RESET_REG, MASK_ALL, PERM_RW}, + [CPLD_I2C_MUX_RESET_2] = {CPLD_I2C_MUX_RESET_2_REG, MASK_ALL, PERM_RW}, + [CPLD_MISC_RESET] = {CPLD_MISC_RESET_REG, MASK_ALL, PERM_RW}, + + [CPLD_BRD_PRESENT] = {CPLD_BRD_PRESENT_REG, MASK_ALL, PERM_R}, + [CPLD_PSU_STATUS] = {CPLD_PSU_STATUS_REG, MASK_ALL, PERM_R}, + [CPLD_SYSTEM_PWR] = {CPLD_SYSTEM_PWR_REG, MASK_ALL, PERM_R}, + [CPLD_MAC_SYNCE] = {CPLD_MAC_SYNCE_REG, MASK_ALL, PERM_R}, + [CPLD_MAC_AVS] = {CPLD_MAC_AVS_REG, MASK_ALL, PERM_R}, + [CPLD_SYSTEM_STATUS] = {CPLD_SYSTEM_STATUS_REG, MASK_ALL, PERM_R}, + [CPLD_FAN_PRESENT] = {CPLD_FAN_PRESENT_REG, MASK_ALL, PERM_R}, + [CPLD_WATCHDOG] = {CPLD_WATCHDOG_REG, MASK_ALL, PERM_RW}, + [CPLD_BOOT_SELECT] = {CPLD_BOOT_SELECT_REG, MASK_ALL, PERM_RW}, + [CPLD_MUX_CTRL] = {CPLD_MUX_CTRL_REG, MASK_ALL, PERM_RW}, + [CPLD_MISC_CTRL_1] = {CPLD_MISC_CTRL_1_REG, MASK_ALL, PERM_RW}, + [CPLD_MISC_CTRL_2] = {CPLD_MISC_CTRL_2_REG, MASK_ALL, PERM_RW}, + [CPLD_TIMING_CTRL] = {CPLD_TIMING_CTRL_REG, MASK_ALL, PERM_RW}, + + [CPLD_MAC_TEMP] = {CPLD_MAC_TEMP_REG, MASK_ALL, PERM_R}, + + [CPLD_SYSTEM_LED_SYNC] = {CPLD_SYSTEM_LED_SYNC_REG, CPLD_SYSTEM_LED_SYNC_MASK, PERM_RW}, + [CPLD_SYSTEM_LED_SYS] = {CPLD_SYSTEM_LED_SYS_REG, CPLD_SYSTEM_LED_SYS_MASK, PERM_RW}, + [CPLD_SYSTEM_LED_FAN] = {CPLD_SYSTEM_LED_FAN_REG, CPLD_SYSTEM_LED_FAN_MASK, PERM_RW}, + [CPLD_SYSTEM_LED_PSU_0] = {CPLD_SYSTEM_LED_PSU_REG, CPLD_SYSTEM_LED_PSU_0_MASK, PERM_RW}, + [CPLD_SYSTEM_LED_PSU_1] = {CPLD_SYSTEM_LED_PSU_REG, CPLD_SYSTEM_LED_PSU_1_MASK, PERM_RW}, + [CPLD_SYSTEM_LED_ID] = {CPLD_SYSTEM_LED_ID_REG, CPLD_SYSTEM_LED_ID_MASK, PERM_RW}, + + [DBG_CPLD_MAC_INTR] = {DBG_CPLD_MAC_INTR_REG, MASK_ALL, PERM_RW}, + [DBG_CPLD_HWM_INTR] = {DBG_CPLD_HWM_INTR_REG, MASK_ALL, PERM_RW}, + [DBG_CPLD_CPLD2_INTR] = {DBG_CPLD_CPLD2_INTR_REG, MASK_ALL, PERM_RW}, + [DBG_CPLD_NTM_INTR] = {DBG_CPLD_NTM_INTR_REG, MASK_ALL, PERM_RW}, + [DBG_CPLD_FAN_PSU_INTR] = {DBG_CPLD_FAN_PSU_INTR_REG, MASK_ALL, PERM_RW}, + [DBG_CPLD_SFP_IOEXP_INTR] = {DBG_CPLD_SFP_IOEXP_INTR_REG, MASK_ALL, PERM_RW}, + [DBG_CPLD_PTP_INTR] = {DBG_CPLD_PTP_INTR_REG, MASK_ALL, PERM_RW}, + + //CPLD 2 + + //interrupt status + [CPLD_SFP_INTR_PRESENT_0_7] = {CPLD_SFP_INTR_PRESENT_0_7_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_INTR_PRESENT_8_15] = {CPLD_SFP_INTR_PRESENT_8_15_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_INTR_PRESENT_16_23] = {CPLD_SFP_INTR_PRESENT_16_23_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_INTR_PRESENT_24_31] = {CPLD_SFP_INTR_PRESENT_24_31_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_INTR_PRESENT_32_39] = {CPLD_SFP_INTR_PRESENT_32_39_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_INTR_PRESENT_40_47] = {CPLD_SFP_INTR_PRESENT_40_47_REG, MASK_ALL, PERM_R}, + [CPLD_QSFP_INTR_PRESENT_48_53] = {CPLD_QSFP_INTR_PRESENT_48_53_REG, MASK_ALL, PERM_R}, + [CPLD_QSFP_INTR_PORT_48_53] = {CPLD_QSFP_INTR_PORT_48_53_REG, MASK_ALL, PERM_R}, + + //interrupt mask + [CPLD_SFP_MASK_PRESENT_0_7] = {CPLD_SFP_MASK_PRESENT_0_7_REG, MASK_ALL, PERM_RW}, + [CPLD_SFP_MASK_PRESENT_8_15] = {CPLD_SFP_MASK_PRESENT_8_15_REG, MASK_ALL, PERM_RW}, + [CPLD_SFP_MASK_PRESENT_16_23] = {CPLD_SFP_MASK_PRESENT_16_23_REG, MASK_ALL, PERM_RW}, + [CPLD_SFP_MASK_PRESENT_24_31] = {CPLD_SFP_MASK_PRESENT_24_31_REG, MASK_ALL, PERM_RW}, + [CPLD_SFP_MASK_PRESENT_32_39] = {CPLD_SFP_MASK_PRESENT_32_39_REG, MASK_ALL, PERM_RW}, + [CPLD_SFP_MASK_PRESENT_40_47] = {CPLD_SFP_MASK_PRESENT_40_47_REG, MASK_ALL, PERM_RW}, + [CPLD_QSFP_MASK_PRESENT_48_53] = {CPLD_QSFP_MASK_PRESENT_48_53_REG, MASK_ALL, PERM_RW}, + [CPLD_QSFP_MASK_PORT_48_53] = {CPLD_QSFP_MASK_PORT_48_53_REG, MASK_ALL, PERM_RW}, + + //interrupt event + [CPLD_SFP_EVT_PRESENT_0_7] = {CPLD_SFP_EVT_PRESENT_0_7_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_EVT_PRESENT_8_15] = {CPLD_SFP_EVT_PRESENT_8_15_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_EVT_PRESENT_16_23] = {CPLD_SFP_EVT_PRESENT_16_23_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_EVT_PRESENT_24_31] = {CPLD_SFP_EVT_PRESENT_24_31_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_EVT_PRESENT_32_39] = {CPLD_SFP_EVT_PRESENT_32_39_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_EVT_PRESENT_40_47] = {CPLD_SFP_EVT_PRESENT_40_47_REG, MASK_ALL, PERM_R}, + [CPLD_QSFP_EVT_PRESENT_48_53] = {CPLD_QSFP_EVT_PRESENT_48_53_REG, MASK_ALL, PERM_R}, + [CPLD_QSFP_EVT_PORT_48_53] = {CPLD_QSFP_EVT_PORT_48_53_REG, MASK_ALL, PERM_R}, + + [CPLD_SFP_INTR_RX_LOS_0_7] = {CPLD_SFP_INTR_RX_LOS_0_7_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_INTR_RX_LOS_8_15] = {CPLD_SFP_INTR_RX_LOS_8_15_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_INTR_RX_LOS_16_23] = {CPLD_SFP_INTR_RX_LOS_16_23_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_INTR_RX_LOS_24_31] = {CPLD_SFP_INTR_RX_LOS_24_31_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_INTR_RX_LOS_32_39] = {CPLD_SFP_INTR_RX_LOS_32_39_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_INTR_RX_LOS_40_47] = {CPLD_SFP_INTR_RX_LOS_40_47_REG, MASK_ALL, PERM_R}, + + [CPLD_SFP_INTR_TX_FAULT_0_7] = {CPLD_SFP_INTR_TX_FAULT_0_7_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_INTR_TX_FAULT_8_15] = {CPLD_SFP_INTR_TX_FAULT_8_15_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_INTR_TX_FAULT_16_23] = {CPLD_SFP_INTR_TX_FAULT_16_23_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_INTR_TX_FAULT_24_31] = {CPLD_SFP_INTR_TX_FAULT_24_31_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_INTR_TX_FAULT_32_39] = {CPLD_SFP_INTR_TX_FAULT_32_39_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_INTR_TX_FAULT_40_47] = {CPLD_SFP_INTR_TX_FAULT_40_47_REG, MASK_ALL, PERM_R}, + + [CPLD_SFP_MASK_RX_LOS_0_7] = {CPLD_SFP_MASK_RX_LOS_0_7_REG, MASK_ALL, PERM_RW}, + [CPLD_SFP_MASK_RX_LOS_8_15] = {CPLD_SFP_MASK_RX_LOS_8_15_REG, MASK_ALL, PERM_RW}, + [CPLD_SFP_MASK_RX_LOS_16_23] = {CPLD_SFP_MASK_RX_LOS_16_23_REG, MASK_ALL, PERM_RW}, + [CPLD_SFP_MASK_RX_LOS_24_31] = {CPLD_SFP_MASK_RX_LOS_24_31_REG, MASK_ALL, PERM_RW}, + [CPLD_SFP_MASK_RX_LOS_32_39] = {CPLD_SFP_MASK_RX_LOS_32_39_REG, MASK_ALL, PERM_RW}, + [CPLD_SFP_MASK_RX_LOS_40_47] = {CPLD_SFP_MASK_RX_LOS_40_47_REG, MASK_ALL, PERM_RW}, + + [CPLD_SFP_MASK_TX_FAULT_0_7] = {CPLD_SFP_MASK_TX_FAULT_0_7_REG, MASK_ALL, PERM_RW}, + [CPLD_SFP_MASK_TX_FAULT_8_15] = {CPLD_SFP_MASK_TX_FAULT_8_15_REG, MASK_ALL, PERM_RW}, + [CPLD_SFP_MASK_TX_FAULT_16_23] = {CPLD_SFP_MASK_TX_FAULT_16_23_REG, MASK_ALL, PERM_RW}, + [CPLD_SFP_MASK_TX_FAULT_24_31] = {CPLD_SFP_MASK_TX_FAULT_24_31_REG, MASK_ALL, PERM_RW}, + [CPLD_SFP_MASK_TX_FAULT_32_39] = {CPLD_SFP_MASK_TX_FAULT_32_39_REG, MASK_ALL, PERM_RW}, + [CPLD_SFP_MASK_TX_FAULT_40_47] = {CPLD_SFP_MASK_TX_FAULT_40_47_REG, MASK_ALL, PERM_RW}, + + [CPLD_SFP_EVT_RX_LOS_0_7] = {CPLD_SFP_EVT_RX_LOS_0_7_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_EVT_RX_LOS_8_15] = {CPLD_SFP_EVT_RX_LOS_8_15_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_EVT_RX_LOS_16_23] = {CPLD_SFP_EVT_RX_LOS_16_23_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_EVT_RX_LOS_24_31] = {CPLD_SFP_EVT_RX_LOS_24_31_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_EVT_RX_LOS_32_39] = {CPLD_SFP_EVT_RX_LOS_32_39_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_EVT_RX_LOS_40_47] = {CPLD_SFP_EVT_RX_LOS_40_47_REG, MASK_ALL, PERM_R}, + + [CPLD_SFP_EVT_TX_FAULT_0_7] = {CPLD_SFP_EVT_TX_FAULT_0_7_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_EVT_TX_FAULT_8_15] = {CPLD_SFP_EVT_TX_FAULT_8_15_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_EVT_TX_FAULT_16_23] = {CPLD_SFP_EVT_TX_FAULT_16_23_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_EVT_TX_FAULT_24_31] = {CPLD_SFP_EVT_TX_FAULT_24_31_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_EVT_TX_FAULT_32_39] = {CPLD_SFP_EVT_TX_FAULT_32_39_REG, MASK_ALL, PERM_R}, + [CPLD_SFP_EVT_TX_FAULT_40_47] = {CPLD_SFP_EVT_TX_FAULT_40_47_REG, MASK_ALL, PERM_R}, + + [CPLD_SFP_TX_DISABLE_0_7] = {CPLD_SFP_TX_DISABLE_0_7_REG, MASK_ALL, PERM_RW}, + [CPLD_SFP_TX_DISABLE_8_15] = {CPLD_SFP_TX_DISABLE_8_15_REG, MASK_ALL, PERM_RW}, + [CPLD_SFP_TX_DISABLE_16_23] = {CPLD_SFP_TX_DISABLE_16_23_REG, MASK_ALL, PERM_RW}, + [CPLD_SFP_TX_DISABLE_24_31] = {CPLD_SFP_TX_DISABLE_24_31_REG, MASK_ALL, PERM_RW}, + [CPLD_SFP_TX_DISABLE_32_39] = {CPLD_SFP_TX_DISABLE_32_39_REG, MASK_ALL, PERM_RW}, + [CPLD_SFP_TX_DISABLE_40_47] = {CPLD_SFP_TX_DISABLE_40_47_REG, MASK_ALL, PERM_RW}, + + [CPLD_QSFP_RESET_48_53] = {CPLD_QSFP_RESET_48_53_REG, MASK_ALL, PERM_RW}, + [CPLD_QSFP_LPMODE_48_53] = {CPLD_QSFP_LPMODE_48_53_REG, MASK_ALL, PERM_RW}, + + //debug interrupt status + [DBG_CPLD_SFP_INTR_PRESENT_0_7] = {DBG_CPLD_SFP_INTR_PRESENT_0_7_REG, MASK_ALL, PERM_R}, + [DBG_CPLD_SFP_INTR_PRESENT_8_15] = {DBG_CPLD_SFP_INTR_PRESENT_8_15_REG, MASK_ALL, PERM_R}, + [DBG_CPLD_SFP_INTR_PRESENT_16_23] = {DBG_CPLD_SFP_INTR_PRESENT_16_23_REG, MASK_ALL, PERM_R}, + [DBG_CPLD_SFP_INTR_PRESENT_24_31] = {DBG_CPLD_SFP_INTR_PRESENT_24_31_REG, MASK_ALL, PERM_R}, + [DBG_CPLD_SFP_INTR_PRESENT_32_39] = {DBG_CPLD_SFP_INTR_PRESENT_32_39_REG, MASK_ALL, PERM_R}, + [DBG_CPLD_SFP_INTR_PRESENT_40_47] = {DBG_CPLD_SFP_INTR_PRESENT_40_47_REG, MASK_ALL, PERM_R}, + [DBG_CPLD_QSFP_INTR_PRESENT_48_53] = {DBG_CPLD_QSFP_INTR_PRESENT_48_53_REG, MASK_ALL, PERM_R}, + [DBG_CPLD_QSFP_INTR_PORT_48_53] = {DBG_CPLD_QSFP_INTR_PORT_48_53_REG, MASK_ALL, PERM_R}, + + //debug interrupt mask + [DBG_CPLD_SFP_INTR_RX_LOS_0_7] = {DBG_CPLD_SFP_INTR_RX_LOS_0_7_REG, MASK_ALL, PERM_R}, + [DBG_CPLD_SFP_INTR_RX_LOS_8_15] = {DBG_CPLD_SFP_INTR_RX_LOS_8_15_REG, MASK_ALL, PERM_R}, + [DBG_CPLD_SFP_INTR_RX_LOS_16_23] = {DBG_CPLD_SFP_INTR_RX_LOS_16_23_REG, MASK_ALL, PERM_R}, + [DBG_CPLD_SFP_INTR_RX_LOS_24_31] = {DBG_CPLD_SFP_INTR_RX_LOS_24_31_REG, MASK_ALL, PERM_R}, + [DBG_CPLD_SFP_INTR_RX_LOS_32_39] = {DBG_CPLD_SFP_INTR_RX_LOS_32_39_REG, MASK_ALL, PERM_R}, + [DBG_CPLD_SFP_INTR_RX_LOS_40_47] = {DBG_CPLD_SFP_INTR_RX_LOS_40_47_REG, MASK_ALL, PERM_R}, + + [DBG_CPLD_SFP_INTR_TX_FAULT_0_7] = {DBG_CPLD_SFP_INTR_TX_FAULT_0_7_REG, MASK_ALL, PERM_R}, + [DBG_CPLD_SFP_INTR_TX_FAULT_8_15] = {DBG_CPLD_SFP_INTR_TX_FAULT_8_15_REG, MASK_ALL, PERM_R}, + [DBG_CPLD_SFP_INTR_TX_FAULT_16_23] = {DBG_CPLD_SFP_INTR_TX_FAULT_16_23_REG, MASK_ALL, PERM_R}, + [DBG_CPLD_SFP_INTR_TX_FAULT_24_31] = {DBG_CPLD_SFP_INTR_TX_FAULT_24_31_REG, MASK_ALL, PERM_R}, + [DBG_CPLD_SFP_INTR_TX_FAULT_32_39] = {DBG_CPLD_SFP_INTR_TX_FAULT_32_39_REG, MASK_ALL, PERM_R}, + [DBG_CPLD_SFP_INTR_TX_FAULT_40_47] = {DBG_CPLD_SFP_INTR_TX_FAULT_40_47_REG, MASK_ALL, PERM_R}, +}; + +/* CPLD device id and data */ +static const struct i2c_device_id cpld_id[] = { + { "s8901_54xc_cpld1", cpld1 }, + { "s8901_54xc_cpld2", cpld2 }, + {} +}; + +char bsp_debug[2]="0"; +u8 enable_log_read=LOG_DISABLE; +u8 enable_log_write=LOG_DISABLE; + +/* Addresses scanned for cpld */ +static const unsigned short cpld_i2c_addr[] = { 0x30, 0x31, I2C_CLIENT_END }; + +/* define all support register access of cpld in attribute */ + +// CPLD common +static _SENSOR_DEVICE_ATTR_RO(cpld_board_id_0, cpld_callback, CPLD_BOARD_ID_0); +static _SENSOR_DEVICE_ATTR_RO(cpld_board_id_1, cpld_callback, CPLD_BOARD_ID_1); +static _SENSOR_DEVICE_ATTR_RO(cpld_id, cpld_callback, CPLD_ID); +static _SENSOR_DEVICE_ATTR_RO(cpld_chip, cpld_callback, CPLD_CHIP); +static _SENSOR_DEVICE_ATTR_RO(cpld_sku_ext, cpld_callback, CPLD_SKU_EXT); + +static _SENSOR_DEVICE_ATTR_RO(cpld_major_ver, cpld_callback, CPLD_MAJOR_VER); +static _SENSOR_DEVICE_ATTR_RO(cpld_minor_ver, cpld_callback, CPLD_MINOR_VER); +static _SENSOR_DEVICE_ATTR_RO(cpld_build_ver, cpld_callback, CPLD_BUILD_VER); +static _SENSOR_DEVICE_ATTR_RO(cpld_version_h, cpld_version_h, CPLD_VERSION_H); + +static _SENSOR_DEVICE_ATTR_RW(cpld_evt_ctrl, cpld_callback, CPLD_EVT_CTRL); + +//CPLD 1 +static _SENSOR_DEVICE_ATTR_RO(cpld_mac_intr, cpld_callback, CPLD_MAC_INTR); +static _SENSOR_DEVICE_ATTR_RO(cpld_hwm_intr, cpld_callback, CPLD_HWM_INTR); +static _SENSOR_DEVICE_ATTR_RO(cpld_cpld2_intr, cpld_callback, CPLD_CPLD2_INTR); +static _SENSOR_DEVICE_ATTR_RO(cpld_ntm_intr, cpld_callback, CPLD_NTM_INTR); +static _SENSOR_DEVICE_ATTR_RO(cpld_fan_psu_intr, cpld_callback, CPLD_FAN_PSU_INTR); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_ioexp_intr, cpld_callback, CPLD_SFP_IOEXP_INTR); +static _SENSOR_DEVICE_ATTR_RO(cpld_cpu_nmi_intr, cpld_callback, CPLD_CPU_NMI_INTR); +static _SENSOR_DEVICE_ATTR_RO(cpld_ptp_intr, cpld_callback, CPLD_PTP_INTR); +static _SENSOR_DEVICE_ATTR_RO(cpld_system_intr, cpld_callback, CPLD_SYSTEM_INTR); + +static _SENSOR_DEVICE_ATTR_RW(cpld_mac_mask, cpld_callback, CPLD_MAC_MASK); +static _SENSOR_DEVICE_ATTR_RW(cpld_hwm_mask, cpld_callback, CPLD_HWM_MASK); +static _SENSOR_DEVICE_ATTR_RW(cpld_cpld2_mask, cpld_callback, CPLD_CPLD2_MASK); +static _SENSOR_DEVICE_ATTR_RW(cpld_ntm_mask, cpld_callback, CPLD_NTM_MASK); +static _SENSOR_DEVICE_ATTR_RW(cpld_fan_psu_mask, cpld_callback, CPLD_FAN_PSU_MASK); +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_ioexp_mask, cpld_callback, CPLD_SFP_IOEXP_MASK); +static _SENSOR_DEVICE_ATTR_RW(cpld_cpu_nmi_mask, cpld_callback, CPLD_CPU_NMI_MASK); +static _SENSOR_DEVICE_ATTR_RW(cpld_ptp_mask, cpld_callback, CPLD_PTP_MASK); +static _SENSOR_DEVICE_ATTR_RW(cpld_system_mask, cpld_callback, CPLD_SYSTEM_MASK); + +static _SENSOR_DEVICE_ATTR_RO(cpld_mac_evt, cpld_callback, CPLD_MAC_EVT); +static _SENSOR_DEVICE_ATTR_RO(cpld_hwm_evt, cpld_callback, CPLD_HWM_EVT); +static _SENSOR_DEVICE_ATTR_RO(cpld_cpld2_evt, cpld_callback, CPLD_CPLD2_EVT); +static _SENSOR_DEVICE_ATTR_RO(cpld_ntm_evt, cpld_callback, CPLD_NTM_EVT); +static _SENSOR_DEVICE_ATTR_RO(cpld_fan_psu_evt, cpld_callback, CPLD_FAN_PSU_EVT); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_ioexp_evt, cpld_callback, CPLD_SFP_IOEXP_EVT); +static _SENSOR_DEVICE_ATTR_RO(cpld_cpu_nmi_evt, cpld_callback, CPLD_CPU_NMI_EVT); +static _SENSOR_DEVICE_ATTR_RO(cpld_ptp_evt, cpld_callback, CPLD_PTP_EVT); + +static _SENSOR_DEVICE_ATTR_RW(cpld_mac_reset, cpld_callback, CPLD_MAC_RESET); +static _SENSOR_DEVICE_ATTR_RW(cpld_system_reset, cpld_callback, CPLD_SYSTEM_RESET); +static _SENSOR_DEVICE_ATTR_RW(cpld_bmc_ntm_reset, cpld_callback, CPLD_BMC_NTM_RESET); +static _SENSOR_DEVICE_ATTR_RW(cpld_usb_reset, cpld_callback, CPLD_USB_RESET); +static _SENSOR_DEVICE_ATTR_RW(cpld_i2c_mux_reset, cpld_callback, CPLD_I2C_MUX_RESET); +static _SENSOR_DEVICE_ATTR_RW(cpld_i2c_mux_reset_2, cpld_callback, CPLD_I2C_MUX_RESET_2); +static _SENSOR_DEVICE_ATTR_RW(cpld_misc_reset, cpld_callback, CPLD_MISC_RESET); + +static _SENSOR_DEVICE_ATTR_RO(cpld_psu_status, cpld_callback, CPLD_PSU_STATUS); +static _SENSOR_DEVICE_ATTR_RO(cpld_mac_synce, cpld_callback, CPLD_MAC_SYNCE); +static _SENSOR_DEVICE_ATTR_RO(cpld_fan_present, cpld_callback, CPLD_FAN_PRESENT); +static _SENSOR_DEVICE_ATTR_RW(cpld_mux_ctrl, cpld_callback, CPLD_MUX_CTRL); + +static _SENSOR_DEVICE_ATTR_RW(cpld_system_led_sync, cpld_callback, CPLD_SYSTEM_LED_SYNC); +static _SENSOR_DEVICE_ATTR_RW(cpld_system_led_sys, cpld_callback, CPLD_SYSTEM_LED_SYS); +static _SENSOR_DEVICE_ATTR_RW(cpld_system_led_fan, cpld_callback, CPLD_SYSTEM_LED_FAN); +static _SENSOR_DEVICE_ATTR_RW(cpld_system_led_psu_0, cpld_callback, CPLD_SYSTEM_LED_PSU_0); +static _SENSOR_DEVICE_ATTR_RW(cpld_system_led_psu_1, cpld_callback, CPLD_SYSTEM_LED_PSU_1); +static _SENSOR_DEVICE_ATTR_RW(cpld_system_led_id, cpld_callback, CPLD_SYSTEM_LED_ID); + +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_mac_intr, cpld_callback, DBG_CPLD_MAC_INTR); +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_hwm_intr, cpld_callback, DBG_CPLD_HWM_INTR); +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_cpld2_intr, cpld_callback, DBG_CPLD_CPLD2_INTR); +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_ntm_intr, cpld_callback, DBG_CPLD_NTM_INTR); +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_fan_psu_intr, cpld_callback, DBG_CPLD_FAN_PSU_INTR); +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_sfp_ioexp_intr, cpld_callback, DBG_CPLD_SFP_IOEXP_INTR); +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_ptp_intr, cpld_callback, DBG_CPLD_PTP_INTR); + +//CPLD 2 +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_intr_present_0_7, cpld_callback, CPLD_SFP_INTR_PRESENT_0_7); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_intr_present_8_15, cpld_callback, CPLD_SFP_INTR_PRESENT_8_15); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_intr_present_16_23, cpld_callback, CPLD_SFP_INTR_PRESENT_16_23); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_intr_present_24_31, cpld_callback, CPLD_SFP_INTR_PRESENT_24_31); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_intr_present_32_39, cpld_callback, CPLD_SFP_INTR_PRESENT_32_39); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_intr_present_40_47, cpld_callback, CPLD_SFP_INTR_PRESENT_40_47); + +static _SENSOR_DEVICE_ATTR_RO(cpld_qsfp_intr_present_48_53, cpld_callback, CPLD_QSFP_INTR_PRESENT_48_53); +static _SENSOR_DEVICE_ATTR_RO(cpld_qsfp_intr_port_48_53, cpld_callback, CPLD_QSFP_INTR_PORT_48_53); + +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_mask_present_0_7, cpld_callback, CPLD_SFP_MASK_PRESENT_0_7); +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_mask_present_8_15, cpld_callback, CPLD_SFP_MASK_PRESENT_8_15); +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_mask_present_16_23, cpld_callback, CPLD_SFP_MASK_PRESENT_16_23); +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_mask_present_24_31, cpld_callback, CPLD_SFP_MASK_PRESENT_24_31); +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_mask_present_32_39, cpld_callback, CPLD_SFP_MASK_PRESENT_32_39); +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_mask_present_40_47, cpld_callback, CPLD_SFP_MASK_PRESENT_40_47); + +static _SENSOR_DEVICE_ATTR_RW(cpld_qsfp_mask_present_48_53, cpld_callback, CPLD_QSFP_MASK_PRESENT_48_53); +static _SENSOR_DEVICE_ATTR_RW(cpld_qsfp_mask_port_48_53, cpld_callback, CPLD_QSFP_MASK_PORT_48_53); + +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_evt_present_0_7, cpld_callback, CPLD_SFP_EVT_PRESENT_0_7); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_evt_present_8_15, cpld_callback, CPLD_SFP_EVT_PRESENT_8_15); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_evt_present_16_23, cpld_callback, CPLD_SFP_EVT_PRESENT_16_23); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_evt_present_24_31, cpld_callback, CPLD_SFP_EVT_PRESENT_24_31); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_evt_present_32_39, cpld_callback, CPLD_SFP_EVT_PRESENT_32_39); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_evt_present_40_47, cpld_callback, CPLD_SFP_EVT_PRESENT_40_47); + +static _SENSOR_DEVICE_ATTR_RO(cpld_qsfp_evt_present_48_53, cpld_callback, CPLD_QSFP_EVT_PRESENT_48_53); +static _SENSOR_DEVICE_ATTR_RO(cpld_qsfp_evt_port_48_53, cpld_callback, CPLD_QSFP_EVT_PORT_48_53); + +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_intr_rx_los_0_7, cpld_callback, CPLD_SFP_INTR_RX_LOS_0_7); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_intr_rx_los_8_15, cpld_callback, CPLD_SFP_INTR_RX_LOS_8_15); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_intr_rx_los_16_23, cpld_callback, CPLD_SFP_INTR_RX_LOS_16_23); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_intr_rx_los_24_31, cpld_callback, CPLD_SFP_INTR_RX_LOS_24_31); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_intr_rx_los_32_39, cpld_callback, CPLD_SFP_INTR_RX_LOS_32_39); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_intr_rx_los_40_47, cpld_callback, CPLD_SFP_INTR_RX_LOS_40_47); + +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_intr_tx_fault_0_7, cpld_callback, CPLD_SFP_INTR_TX_FAULT_0_7); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_intr_tx_fault_8_15, cpld_callback, CPLD_SFP_INTR_TX_FAULT_8_15); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_intr_tx_fault_16_23, cpld_callback, CPLD_SFP_INTR_TX_FAULT_16_23); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_intr_tx_fault_24_31, cpld_callback, CPLD_SFP_INTR_TX_FAULT_24_31); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_intr_tx_fault_32_39, cpld_callback, CPLD_SFP_INTR_TX_FAULT_32_39); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_intr_tx_fault_40_47, cpld_callback, CPLD_SFP_INTR_TX_FAULT_40_47); + +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_mask_rx_los_0_7, cpld_callback, CPLD_SFP_MASK_RX_LOS_0_7); +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_mask_rx_los_8_15, cpld_callback, CPLD_SFP_MASK_RX_LOS_8_15); +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_mask_rx_los_16_23, cpld_callback, CPLD_SFP_MASK_RX_LOS_16_23); +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_mask_rx_los_24_31, cpld_callback, CPLD_SFP_MASK_RX_LOS_24_31); +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_mask_rx_los_32_39, cpld_callback, CPLD_SFP_MASK_RX_LOS_32_39); +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_mask_rx_los_40_47, cpld_callback, CPLD_SFP_MASK_RX_LOS_40_47); + +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_mask_tx_fault_0_7, cpld_callback, CPLD_SFP_MASK_TX_FAULT_0_7); +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_mask_tx_fault_8_15, cpld_callback, CPLD_SFP_MASK_TX_FAULT_8_15); +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_mask_tx_fault_16_23, cpld_callback, CPLD_SFP_MASK_TX_FAULT_16_23); +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_mask_tx_fault_24_31, cpld_callback, CPLD_SFP_MASK_TX_FAULT_24_31); +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_mask_tx_fault_32_39, cpld_callback, CPLD_SFP_MASK_TX_FAULT_32_39); +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_mask_tx_fault_40_47, cpld_callback, CPLD_SFP_MASK_TX_FAULT_40_47); + +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_evt_rx_los_0_7, cpld_callback, CPLD_SFP_EVT_RX_LOS_0_7); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_evt_rx_los_8_15, cpld_callback, CPLD_SFP_EVT_RX_LOS_8_15); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_evt_rx_los_16_23, cpld_callback, CPLD_SFP_EVT_RX_LOS_16_23); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_evt_rx_los_24_31, cpld_callback, CPLD_SFP_EVT_RX_LOS_24_31); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_evt_rx_los_32_39, cpld_callback, CPLD_SFP_EVT_RX_LOS_32_39); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_evt_rx_los_40_47, cpld_callback, CPLD_SFP_EVT_RX_LOS_40_47); + +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_evt_tx_fault_0_7, cpld_callback, CPLD_SFP_EVT_TX_FAULT_0_7); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_evt_tx_fault_8_15, cpld_callback, CPLD_SFP_EVT_TX_FAULT_8_15); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_evt_tx_fault_16_23, cpld_callback, CPLD_SFP_EVT_TX_FAULT_16_23); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_evt_tx_fault_24_31, cpld_callback, CPLD_SFP_EVT_TX_FAULT_24_31); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_evt_tx_fault_32_39, cpld_callback, CPLD_SFP_EVT_TX_FAULT_32_39); +static _SENSOR_DEVICE_ATTR_RO(cpld_sfp_evt_tx_fault_40_47, cpld_callback, CPLD_SFP_EVT_TX_FAULT_40_47); + +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_tx_disable_0_7, cpld_callback, CPLD_SFP_TX_DISABLE_0_7); +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_tx_disable_8_15, cpld_callback, CPLD_SFP_TX_DISABLE_8_15); +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_tx_disable_16_23, cpld_callback, CPLD_SFP_TX_DISABLE_16_23); +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_tx_disable_24_31, cpld_callback, CPLD_SFP_TX_DISABLE_24_31); +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_tx_disable_32_39, cpld_callback, CPLD_SFP_TX_DISABLE_32_39); +static _SENSOR_DEVICE_ATTR_RW(cpld_sfp_tx_disable_40_47, cpld_callback, CPLD_SFP_TX_DISABLE_40_47); + +static _SENSOR_DEVICE_ATTR_RW(cpld_qsfp_reset_48_53, cpld_callback, CPLD_QSFP_RESET_48_53); +static _SENSOR_DEVICE_ATTR_RW(cpld_qsfp_lpmode_48_53, cpld_callback, CPLD_QSFP_LPMODE_48_53); + +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_sfp_intr_present_0_7, cpld_callback, DBG_CPLD_SFP_INTR_PRESENT_0_7); +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_sfp_intr_present_8_15, cpld_callback, DBG_CPLD_SFP_INTR_PRESENT_8_15); +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_sfp_intr_present_16_23, cpld_callback, DBG_CPLD_SFP_INTR_PRESENT_16_23); +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_sfp_intr_present_24_31, cpld_callback, DBG_CPLD_SFP_INTR_PRESENT_24_31); +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_sfp_intr_present_32_39, cpld_callback, DBG_CPLD_SFP_INTR_PRESENT_32_39); +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_sfp_intr_present_40_47, cpld_callback, DBG_CPLD_SFP_INTR_PRESENT_40_47); + +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_qsfp_intr_present_48_53, cpld_callback, DBG_CPLD_QSFP_INTR_PRESENT_48_53); +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_qsfp_intr_port_48_53, cpld_callback, DBG_CPLD_QSFP_INTR_PORT_48_53); + +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_sfp_intr_rx_los_0_7, cpld_callback, DBG_CPLD_SFP_INTR_RX_LOS_0_7); +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_sfp_intr_rx_los_8_15, cpld_callback, DBG_CPLD_SFP_INTR_RX_LOS_8_15); +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_sfp_intr_rx_los_16_23, cpld_callback, DBG_CPLD_SFP_INTR_RX_LOS_16_23); +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_sfp_intr_rx_los_24_31, cpld_callback, DBG_CPLD_SFP_INTR_RX_LOS_24_31); +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_sfp_intr_rx_los_32_39, cpld_callback, DBG_CPLD_SFP_INTR_RX_LOS_32_39); +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_sfp_intr_rx_los_40_47, cpld_callback, DBG_CPLD_SFP_INTR_RX_LOS_40_47); + +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_sfp_intr_tx_fault_0_7, cpld_callback, DBG_CPLD_SFP_INTR_TX_FAULT_0_7); +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_sfp_intr_tx_fault_8_15, cpld_callback, DBG_CPLD_SFP_INTR_TX_FAULT_8_15); +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_sfp_intr_tx_fault_16_23, cpld_callback, DBG_CPLD_SFP_INTR_TX_FAULT_16_23); +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_sfp_intr_tx_fault_24_31, cpld_callback, DBG_CPLD_SFP_INTR_TX_FAULT_24_31); +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_sfp_intr_tx_fault_32_39, cpld_callback, DBG_CPLD_SFP_INTR_TX_FAULT_32_39); +static _SENSOR_DEVICE_ATTR_RW(dbg_cpld_sfp_intr_tx_fault_40_47, cpld_callback, DBG_CPLD_SFP_INTR_TX_FAULT_40_47); + +//BSP DEBUG +static _SENSOR_DEVICE_ATTR_RW(bsp_debug, bsp_callback, BSP_DEBUG); + +/* define support attributes of cpldx */ + +/* cpld 1 */ +static struct attribute *cpld1_attributes[] = { + _DEVICE_ATTR(cpld_board_id_0), + _DEVICE_ATTR(cpld_board_id_1), + + _DEVICE_ATTR(cpld_id), + _DEVICE_ATTR(cpld_chip), + _DEVICE_ATTR(cpld_sku_ext), + + _DEVICE_ATTR(cpld_major_ver), + _DEVICE_ATTR(cpld_minor_ver), + _DEVICE_ATTR(cpld_build_ver), + _DEVICE_ATTR(cpld_version_h), + + _DEVICE_ATTR(cpld_mac_intr), + _DEVICE_ATTR(cpld_hwm_intr), + _DEVICE_ATTR(cpld_cpld2_intr), + _DEVICE_ATTR(cpld_ntm_intr), + _DEVICE_ATTR(cpld_fan_psu_intr), + _DEVICE_ATTR(cpld_sfp_ioexp_intr), + _DEVICE_ATTR(cpld_cpu_nmi_intr), + _DEVICE_ATTR(cpld_ptp_intr), + _DEVICE_ATTR(cpld_system_intr), + + _DEVICE_ATTR(cpld_mac_mask), + _DEVICE_ATTR(cpld_hwm_mask), + _DEVICE_ATTR(cpld_cpld2_mask), + _DEVICE_ATTR(cpld_ntm_mask), + _DEVICE_ATTR(cpld_fan_psu_mask), + _DEVICE_ATTR(cpld_sfp_ioexp_mask), + _DEVICE_ATTR(cpld_cpu_nmi_mask), + _DEVICE_ATTR(cpld_ptp_mask), + _DEVICE_ATTR(cpld_system_mask), + + _DEVICE_ATTR(cpld_mac_evt), + _DEVICE_ATTR(cpld_hwm_evt), + _DEVICE_ATTR(cpld_cpld2_evt), + _DEVICE_ATTR(cpld_ntm_evt), + _DEVICE_ATTR(cpld_fan_psu_evt), + _DEVICE_ATTR(cpld_sfp_ioexp_evt), + _DEVICE_ATTR(cpld_cpu_nmi_evt), + _DEVICE_ATTR(cpld_ptp_evt), + + _DEVICE_ATTR(cpld_evt_ctrl), + + _DEVICE_ATTR(cpld_mac_reset), + _DEVICE_ATTR(cpld_system_reset), + _DEVICE_ATTR(cpld_bmc_ntm_reset), + _DEVICE_ATTR(cpld_usb_reset), + _DEVICE_ATTR(cpld_i2c_mux_reset), + _DEVICE_ATTR(cpld_i2c_mux_reset_2), + _DEVICE_ATTR(cpld_misc_reset), + + _DEVICE_ATTR(cpld_psu_status), + _DEVICE_ATTR(cpld_mac_synce), + _DEVICE_ATTR(cpld_fan_present), + _DEVICE_ATTR(cpld_mux_ctrl), + + _DEVICE_ATTR(cpld_system_led_sync), + _DEVICE_ATTR(cpld_system_led_sys), + _DEVICE_ATTR(cpld_system_led_fan), + _DEVICE_ATTR(cpld_system_led_psu_0), + _DEVICE_ATTR(cpld_system_led_psu_1), + _DEVICE_ATTR(cpld_system_led_id), + + _DEVICE_ATTR(dbg_cpld_mac_intr), + _DEVICE_ATTR(dbg_cpld_hwm_intr), + _DEVICE_ATTR(dbg_cpld_cpld2_intr), + _DEVICE_ATTR(dbg_cpld_ntm_intr), + _DEVICE_ATTR(dbg_cpld_fan_psu_intr), + _DEVICE_ATTR(dbg_cpld_sfp_ioexp_intr), + _DEVICE_ATTR(dbg_cpld_ptp_intr), + + _DEVICE_ATTR(bsp_debug), + + NULL +}; + +/* cpld 2 */ +static struct attribute *cpld2_attributes[] = { + _DEVICE_ATTR(cpld_id), + _DEVICE_ATTR(cpld_chip), + + _DEVICE_ATTR(cpld_major_ver), + _DEVICE_ATTR(cpld_minor_ver), + _DEVICE_ATTR(cpld_build_ver), + _DEVICE_ATTR(cpld_version_h), + + _DEVICE_ATTR(cpld_sfp_intr_present_0_7), + _DEVICE_ATTR(cpld_sfp_intr_present_8_15), + _DEVICE_ATTR(cpld_sfp_intr_present_16_23), + _DEVICE_ATTR(cpld_sfp_intr_present_24_31), + _DEVICE_ATTR(cpld_sfp_intr_present_32_39), + _DEVICE_ATTR(cpld_sfp_intr_present_40_47), + + _DEVICE_ATTR(cpld_qsfp_intr_present_48_53), + _DEVICE_ATTR(cpld_qsfp_intr_port_48_53), + + _DEVICE_ATTR(cpld_sfp_mask_present_0_7), + _DEVICE_ATTR(cpld_sfp_mask_present_8_15), + _DEVICE_ATTR(cpld_sfp_mask_present_16_23), + _DEVICE_ATTR(cpld_sfp_mask_present_24_31), + _DEVICE_ATTR(cpld_sfp_mask_present_32_39), + _DEVICE_ATTR(cpld_sfp_mask_present_40_47), + + _DEVICE_ATTR(cpld_qsfp_mask_present_48_53), + _DEVICE_ATTR(cpld_qsfp_mask_port_48_53), + + _DEVICE_ATTR(cpld_sfp_evt_present_0_7), + _DEVICE_ATTR(cpld_sfp_evt_present_8_15), + _DEVICE_ATTR(cpld_sfp_evt_present_16_23), + _DEVICE_ATTR(cpld_sfp_evt_present_24_31), + _DEVICE_ATTR(cpld_sfp_evt_present_32_39), + _DEVICE_ATTR(cpld_sfp_evt_present_40_47), + + _DEVICE_ATTR(cpld_qsfp_evt_present_48_53), + _DEVICE_ATTR(cpld_qsfp_evt_port_48_53), + + _DEVICE_ATTR(cpld_evt_ctrl), + + _DEVICE_ATTR(cpld_sfp_intr_rx_los_0_7), + _DEVICE_ATTR(cpld_sfp_intr_rx_los_8_15), + _DEVICE_ATTR(cpld_sfp_intr_rx_los_16_23), + _DEVICE_ATTR(cpld_sfp_intr_rx_los_24_31), + _DEVICE_ATTR(cpld_sfp_intr_rx_los_32_39), + _DEVICE_ATTR(cpld_sfp_intr_rx_los_40_47), + + _DEVICE_ATTR(cpld_sfp_intr_tx_fault_0_7), + _DEVICE_ATTR(cpld_sfp_intr_tx_fault_8_15), + _DEVICE_ATTR(cpld_sfp_intr_tx_fault_16_23), + _DEVICE_ATTR(cpld_sfp_intr_tx_fault_24_31), + _DEVICE_ATTR(cpld_sfp_intr_tx_fault_32_39), + _DEVICE_ATTR(cpld_sfp_intr_tx_fault_40_47), + + _DEVICE_ATTR(cpld_sfp_mask_rx_los_0_7), + _DEVICE_ATTR(cpld_sfp_mask_rx_los_8_15), + _DEVICE_ATTR(cpld_sfp_mask_rx_los_16_23), + _DEVICE_ATTR(cpld_sfp_mask_rx_los_24_31), + _DEVICE_ATTR(cpld_sfp_mask_rx_los_32_39), + _DEVICE_ATTR(cpld_sfp_mask_rx_los_40_47), + + _DEVICE_ATTR(cpld_sfp_mask_tx_fault_0_7), + _DEVICE_ATTR(cpld_sfp_mask_tx_fault_8_15), + _DEVICE_ATTR(cpld_sfp_mask_tx_fault_16_23), + _DEVICE_ATTR(cpld_sfp_mask_tx_fault_24_31), + _DEVICE_ATTR(cpld_sfp_mask_tx_fault_32_39), + _DEVICE_ATTR(cpld_sfp_mask_tx_fault_40_47), + + _DEVICE_ATTR(cpld_sfp_evt_rx_los_0_7), + _DEVICE_ATTR(cpld_sfp_evt_rx_los_8_15), + _DEVICE_ATTR(cpld_sfp_evt_rx_los_16_23), + _DEVICE_ATTR(cpld_sfp_evt_rx_los_24_31), + _DEVICE_ATTR(cpld_sfp_evt_rx_los_32_39), + _DEVICE_ATTR(cpld_sfp_evt_rx_los_40_47), + + _DEVICE_ATTR(cpld_sfp_evt_tx_fault_0_7), + _DEVICE_ATTR(cpld_sfp_evt_tx_fault_8_15), + _DEVICE_ATTR(cpld_sfp_evt_tx_fault_16_23), + _DEVICE_ATTR(cpld_sfp_evt_tx_fault_24_31), + _DEVICE_ATTR(cpld_sfp_evt_tx_fault_32_39), + _DEVICE_ATTR(cpld_sfp_evt_tx_fault_40_47), + + _DEVICE_ATTR(cpld_sfp_tx_disable_0_7), + _DEVICE_ATTR(cpld_sfp_tx_disable_8_15), + _DEVICE_ATTR(cpld_sfp_tx_disable_16_23), + _DEVICE_ATTR(cpld_sfp_tx_disable_24_31), + _DEVICE_ATTR(cpld_sfp_tx_disable_32_39), + _DEVICE_ATTR(cpld_sfp_tx_disable_40_47), + + _DEVICE_ATTR(cpld_qsfp_reset_48_53), + _DEVICE_ATTR(cpld_qsfp_lpmode_48_53), + + _DEVICE_ATTR(dbg_cpld_sfp_intr_present_0_7), + _DEVICE_ATTR(dbg_cpld_sfp_intr_present_8_15), + _DEVICE_ATTR(dbg_cpld_sfp_intr_present_16_23), + _DEVICE_ATTR(dbg_cpld_sfp_intr_present_24_31), + _DEVICE_ATTR(dbg_cpld_sfp_intr_present_32_39), + _DEVICE_ATTR(dbg_cpld_sfp_intr_present_40_47), + + _DEVICE_ATTR(dbg_cpld_qsfp_intr_present_48_53), + _DEVICE_ATTR(dbg_cpld_qsfp_intr_port_48_53), + + _DEVICE_ATTR(dbg_cpld_sfp_intr_rx_los_0_7), + _DEVICE_ATTR(dbg_cpld_sfp_intr_rx_los_8_15), + _DEVICE_ATTR(dbg_cpld_sfp_intr_rx_los_16_23), + _DEVICE_ATTR(dbg_cpld_sfp_intr_rx_los_24_31), + _DEVICE_ATTR(dbg_cpld_sfp_intr_rx_los_32_39), + _DEVICE_ATTR(dbg_cpld_sfp_intr_rx_los_40_47), + + _DEVICE_ATTR(dbg_cpld_sfp_intr_tx_fault_0_7), + _DEVICE_ATTR(dbg_cpld_sfp_intr_tx_fault_8_15), + _DEVICE_ATTR(dbg_cpld_sfp_intr_tx_fault_16_23), + _DEVICE_ATTR(dbg_cpld_sfp_intr_tx_fault_24_31), + _DEVICE_ATTR(dbg_cpld_sfp_intr_tx_fault_32_39), + _DEVICE_ATTR(dbg_cpld_sfp_intr_tx_fault_40_47), + + NULL +}; + +/* cpld 1 attributes group */ +static const struct attribute_group cpld1_group = { + .attrs = cpld1_attributes, +}; + +/* cpld 2 attributes group */ +static const struct attribute_group cpld2_group = { + .attrs = cpld2_attributes, +}; + +/* reg shift */ +static u8 _shift(u8 mask) +{ + int i=0, mask_one=1; + + for(i=0; i<8; ++i) { + if ((mask & mask_one) == 1) + return i; + else + mask >>= 1; + } + + return -1; +} + +/* reg mask and shift */ +static u8 _mask_shift(u8 val, u8 mask) +{ + int shift=0; + + shift = _shift(mask); + + return (val & mask) >> shift; +} + +static int _bsp_log(u8 log_type, char *fmt, ...) +{ + if ((log_type==LOG_READ && enable_log_read) || + (log_type==LOG_WRITE && enable_log_write)) { + va_list args; + int r; + + va_start(args, fmt); + r = vprintk(fmt, args); + va_end(args); + + return r; + } else { + return 0; + } +} + +static int _config_bsp_log(u8 log_type) +{ + switch(log_type) { + case LOG_NONE: + enable_log_read = LOG_DISABLE; + enable_log_write = LOG_DISABLE; + break; + case LOG_RW: + enable_log_read = LOG_ENABLE; + enable_log_write = LOG_ENABLE; + break; + case LOG_READ: + enable_log_read = LOG_ENABLE; + enable_log_write = LOG_DISABLE; + break; + case LOG_WRITE: + enable_log_read = LOG_DISABLE; + enable_log_write = LOG_ENABLE; + break; + default: + return -EINVAL; + } + return 0; +} + +/* get bsp value */ +static ssize_t read_bsp(char *buf, char *str) +{ + ssize_t len=0; + + len=sprintf(buf, "%s", str); + BSP_LOG_R("reg_val=%s", str); + + return len; +} + +/* set bsp value */ +static ssize_t write_bsp(const char *buf, char *str, size_t str_len, size_t count) +{ + snprintf(str, str_len, "%s", buf); + BSP_LOG_W("reg_val=%s", str); + + return count; +} + +/* get bsp parameter value */ +static ssize_t read_bsp_callback(struct device *dev, + struct device_attribute *da, char *buf) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + int str_len=0; + char *str=NULL; + + switch (attr->index) { + case BSP_DEBUG: + str = bsp_debug; + str_len = sizeof(bsp_debug); + break; + default: + return -EINVAL; + } + return read_bsp(buf, str); +} + +/* set bsp parameter value */ +static ssize_t write_bsp_callback(struct device *dev, + struct device_attribute *da, const char *buf, size_t count) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + int str_len=0; + char *str=NULL; + ssize_t ret = 0; + u8 bsp_debug_u8 = 0; + + switch (attr->index) { + case BSP_DEBUG: + str = bsp_debug; + str_len = sizeof(str); + ret = write_bsp(buf, str, str_len, count); + + if (kstrtou8(buf, 0, &bsp_debug_u8) < 0) { + return -EINVAL; + } else if (_config_bsp_log(bsp_debug_u8) < 0) { + return -EINVAL; + } + return ret; + default: + return -EINVAL; + } + return 0; +} + +/* get cpld register value */ +static ssize_t read_cpld_callback(struct device *dev, + struct device_attribute *da, char *buf) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + u8 reg = 0; + u8 mask = MASK_ALL; + + if (IS_PERM_R(sysfs_info[attr->index].permission)) { + reg = sysfs_info[attr->index].reg; + mask = sysfs_info[attr->index].mask; + } else { + dev_err(dev, "%s() error, attr->index=%d\n", __func__, attr->index); + return -EINVAL; + } + + return read_cpld_reg(dev, buf, reg, mask); +} + +/* set cpld register value */ +static ssize_t write_cpld_callback(struct device *dev, + struct device_attribute *da, const char *buf, size_t count) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + u8 reg = 0; + u8 mask = MASK_ALL; + + if (IS_PERM_W(sysfs_info[attr->index].permission)) { + reg = sysfs_info[attr->index].reg; + mask = sysfs_info[attr->index].mask; + } else { + dev_err(dev, "%s() error, attr->index=%d\n", __func__, attr->index); + return -EINVAL; + } + + return write_cpld_reg(dev, buf, count, reg, mask); +} + +/* get cpld register value */ +static u8 _read_cpld_reg(struct device *dev, + u8 reg, + u8 mask) +{ + struct i2c_client *client = to_i2c_client(dev); + struct cpld_data *data = i2c_get_clientdata(client); + int reg_val; + + I2C_READ_BYTE_DATA(reg_val, &data->access_lock, client, reg); + + if (unlikely(reg_val < 0)) { + return reg_val; + } else { + reg_val=_mask_shift(reg_val, mask); + return reg_val; + } +} + +/* get cpld register value */ +static ssize_t read_cpld_reg(struct device *dev, + char *buf, + u8 reg, + u8 mask) +{ + int reg_val; + + reg_val = _read_cpld_reg(dev, reg, mask); + if (unlikely(reg_val < 0)) { + dev_err(dev, "read_cpld_reg() error, reg_val=%d\n", reg_val); + return reg_val; + } else { + return sprintf(buf, "0x%02x\n", reg_val); + } +} + +/* set cpld register value */ +static ssize_t write_cpld_reg(struct device *dev, + const char *buf, + size_t count, + u8 reg, + u8 mask) +{ + struct i2c_client *client = to_i2c_client(dev); + struct cpld_data *data = i2c_get_clientdata(client); + u8 reg_val, reg_val_now, shift; + int ret = 0; + + if (kstrtou8(buf, 0, ®_val) < 0) + return -EINVAL; + + //apply continuous bits operation if mask is specified, discontinuous bits are not supported + if (mask != MASK_ALL) { + reg_val_now = _read_cpld_reg(dev, reg, MASK_ALL); + if (unlikely(reg_val_now < 0)) { + dev_err(dev, "write_cpld_reg() error, reg_val_now=%d\n", reg_val_now); + return reg_val_now; + } else { + //clear bits in reg_val_now by the mask + reg_val_now &= ~mask; + //get bit shift by the mask + shift = _shift(mask); + //calculate new reg_val + reg_val = reg_val_now | (reg_val << shift); + } + } + + I2C_WRITE_BYTE_DATA(ret, &data->access_lock, + client, reg, reg_val); + + if (unlikely(ret < 0)) { + dev_err(dev, "write_cpld_reg() error, return=%d\n", ret); + return ret; + } + + return count; +} + +/* get qsfp port config register value */ +static ssize_t read_cpld_version_h(struct device *dev, + struct device_attribute *da, + char *buf) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + + if (attr->index >= CPLD_VERSION_H) { + return sprintf(buf, "%d.%02d.%03d", + _read_cpld_reg(dev, CPLD_VERSION_REG, MASK_CPLD_MAJOR_VER), + _read_cpld_reg(dev, CPLD_VERSION_REG, MASK_CPLD_MINOR_VER), + _read_cpld_reg(dev, CPLD_BUILD_REG, MASK_ALL)); + } + return -1; +} + +/* add valid cpld client to list */ +static void cpld_add_client(struct i2c_client *client) +{ + struct cpld_client_node *node = NULL; + + node = kzalloc(sizeof(struct cpld_client_node), GFP_KERNEL); + if (!node) { + dev_info(&client->dev, + "Can't allocate cpld_client_node for index %d\n", + client->addr); + return; + } + + node->client = client; + + mutex_lock(&list_lock); + list_add(&node->list, &cpld_client_list); + mutex_unlock(&list_lock); +} + +/* remove exist cpld client in list */ +static void cpld_remove_client(struct i2c_client *client) +{ + struct list_head *list_node = NULL; + struct cpld_client_node *cpld_node = NULL; + int found = 0; + + mutex_lock(&list_lock); + list_for_each(list_node, &cpld_client_list) { + cpld_node = list_entry(list_node, + struct cpld_client_node, list); + + if (cpld_node->client == client) { + found = 1; + break; + } + } + + if (found) { + list_del(list_node); + kfree(cpld_node); + } + mutex_unlock(&list_lock); +} + +/* cpld drvier probe */ +static int cpld_probe(struct i2c_client *client, + const struct i2c_device_id *dev_id) +{ + int status; + struct cpld_data *data = NULL; + int ret = -EPERM; + + data = kzalloc(sizeof(struct cpld_data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + /* init cpld data for client */ + i2c_set_clientdata(client, data); + mutex_init(&data->access_lock); + + if (!i2c_check_functionality(client->adapter, + I2C_FUNC_SMBUS_BYTE_DATA)) { + dev_info(&client->dev, + "i2c_check_functionality failed (0x%x)\n", + client->addr); + status = -EIO; + goto exit; + } + + /* get cpld id from device */ + ret = i2c_smbus_read_byte_data(client, CPLD_ID_REG); + + if (ret < 0) { + dev_info(&client->dev, + "fail to get cpld id (0x%x) at addr (0x%x)\n", + CPLD_ID_REG, client->addr); + status = -EIO; + goto exit; + } + + if (INVALID(ret, cpld1, cpld2)) { + dev_info(&client->dev, + "cpld id %d(device) not valid\n", ret); + //status = -EPERM; + //goto exit; + } + +#if 0 + /* change client name for each cpld with index */ + snprintf(client->name, sizeof(client->name), "%s_%d", client->name, + data->index); +#endif + + data->index = dev_id->driver_data; + + /* register sysfs hooks for different cpld group */ + dev_info(&client->dev, "probe cpld with index %d\n", data->index); + switch (data->index) { + case cpld1: + status = sysfs_create_group(&client->dev.kobj, + &cpld1_group); + break; + case cpld2: + status = sysfs_create_group(&client->dev.kobj, + &cpld2_group); + break; + default: + status = -EINVAL; + } + + if (status) + goto exit; + + dev_info(&client->dev, "chip found\n"); + + /* add probe chip to client list */ + cpld_add_client(client); + + return 0; +exit: + switch (data->index) { + case cpld1: + sysfs_remove_group(&client->dev.kobj, &cpld1_group); + break; + case cpld2: + sysfs_remove_group(&client->dev.kobj, &cpld2_group); + break; + default: + break; + } + return status; +} + +/* cpld drvier remove */ +static int cpld_remove(struct i2c_client *client) +{ + struct cpld_data *data = i2c_get_clientdata(client); + + switch (data->index) { + case cpld1: + sysfs_remove_group(&client->dev.kobj, &cpld1_group); + break; + case cpld2: + sysfs_remove_group(&client->dev.kobj, &cpld2_group); + break; + } + + cpld_remove_client(client); + return 0; +} + +static int s8901_54xc_cpld_read_internal(struct i2c_client *client, u8 reg) +{ + int retry = I2C_RW_RETRY_COUNT; + int reg_val = 0; + struct cpld_data *data = i2c_get_clientdata(client); + + while (retry) { + I2C_READ_BYTE_DATA(reg_val, &data->access_lock, client, reg); + if (unlikely(reg_val < 0)) { + msleep(I2C_RW_RETRY_INTERVAL); + retry--; + + if (retry == 0) { + dev_err(&client->dev, "%s() retry %d times but still failed, reg=%x\n", __func__, I2C_RW_RETRY_COUNT, reg); + } + + continue; + } + + break; + } + + return reg_val; +} + +static int s8901_54xc_cpld_write_internal(struct i2c_client *client, u8 reg, u8 value) +{ + int ret = 0, retry = I2C_RW_RETRY_COUNT; + struct cpld_data *data = i2c_get_clientdata(client); + + while (retry) { + I2C_WRITE_BYTE_DATA(ret, &data->access_lock, client, reg, value); + if (unlikely(ret < 0)) { + msleep(I2C_RW_RETRY_INTERVAL); + retry--; + + if (retry == 0) { + dev_err(&client->dev, "%s() retry %d times but still failed, reg=%x\n", __func__, I2C_RW_RETRY_COUNT, reg); + } + + continue; + } + break; + } + + return ret; +} + +/* +int s8901_54xc_cpld_write(unsigned short cpld_addr, u8 reg, u8 value) +{ + struct list_head *list_node = NULL; + struct cpld_client_node *cpld_node = NULL; + int ret = -EIO; + + mutex_lock(&list_lock); + + list_for_each(list_node, &cpld_client_list) + { + cpld_node = list_entry(list_node, struct cpld_client_node, list); + + if (cpld_node->client->addr == cpld_addr) { + ret = s8901_54xc_cpld_write_internal(cpld_node->client, reg, value); + break; + } else { + pr_err("cpld_node->client->addr=%x, cpld_addr=%x\n", cpld_node->client->addr, cpld_addr); + } + } + + mutex_unlock(&list_lock); + + return ret; +} +EXPORT_SYMBOL(s8901_54xc_cpld_write); +*/ + +int s8901_54xc_cpld_psu_mux_sel(u8 mux_sel) +{ + unsigned short cpld_addr = cpld_i2c_addr[0]; + u8 reg = CPLD_MUX_CTRL_REG; + u8 reg_val = 0; + u8 psu_mux_mask = 0x06; + u8 mux_sel_val = 0; + + struct list_head *list_node = NULL; + struct cpld_client_node *cpld_node = NULL; + int ret = -EIO; + + switch(mux_sel) { + case 0: + //psu 0 + mux_sel_val = 0x04; + break; + case 1: + //psu 1 + mux_sel_val = 0x02; + break; + default: + //bmc + mux_sel_val = psu_mux_mask; + break; + } + + mutex_lock(&list_lock); + + list_for_each(list_node, &cpld_client_list) + { + cpld_node = list_entry(list_node, struct cpld_client_node, list); + + if (cpld_node->client->addr == cpld_addr) { + //read current reg value + reg_val = s8901_54xc_cpld_read_internal(cpld_node->client, reg); + //clear psu_mux_sel bits (bit 1 and 2) + reg_val &= ~psu_mux_mask; + //modify psu_mux_sel bits (bit 1 and 2) + reg_val |= mux_sel_val; + //write reg value + s8901_54xc_cpld_write_internal(cpld_node->client, reg, reg_val); + + break; + } else { + pr_err("cpld_node->client->addr=%x, cpld_addr=%x\n", cpld_node->client->addr, cpld_addr); + } + } + + mutex_unlock(&list_lock); + + return ret; +} +EXPORT_SYMBOL(s8901_54xc_cpld_psu_mux_sel); + +MODULE_DEVICE_TABLE(i2c, cpld_id); + +static struct i2c_driver cpld_driver = { + .class = I2C_CLASS_HWMON, + .driver = { + .name = "x86_64_ufispace_s8901_54xc_cpld", + }, + .probe = cpld_probe, + .remove = cpld_remove, + .id_table = cpld_id, + .address_list = cpld_i2c_addr, +}; + +static int __init cpld_init(void) +{ + mutex_init(&list_lock); + return i2c_add_driver(&cpld_driver); +} + +static void __exit cpld_exit(void) +{ + i2c_del_driver(&cpld_driver); +} + +MODULE_AUTHOR("Jason Tsai "); +MODULE_DESCRIPTION("x86_64_ufispace_s8901_54xc_cpld driver"); +MODULE_LICENSE("GPL"); + +module_init(cpld_init); +module_exit(cpld_exit); diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/modules/x86-64-ufispace-s8901-54xc-cpld.h b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/modules/x86-64-ufispace-s8901-54xc-cpld.h new file mode 100644 index 000000000000..36521635fdc6 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/modules/x86-64-ufispace-s8901-54xc-cpld.h @@ -0,0 +1,269 @@ +/* header file for i2c cpld driver of ufispace_s8901_54xc + * + * Copyright (C) 2022 UfiSpace Technology Corporation. + * Jason Tsai + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef UFISPACE_S8901_54XC_CPLD_H +#define UFISPACE_S8901_54XC_CPLD_H + +/* CPLD device index value */ +enum cpld_id { + cpld1, + cpld2 +}; + +/* CPLD common registers */ +#define CPLD_VERSION_REG 0x02 +#define CPLD_ID_REG 0x03 +#define CPLD_BUILD_REG 0x04 +#define CPLD_CHIP_REG 0x05 + +#define CPLD_EVT_CTRL_REG 0x3F + +/* CPLD 1 registers */ +#define CPLD_BOARD_ID_0_REG 0x00 +#define CPLD_BOARD_ID_1_REG 0x01 +#define CPLD_SKU_EXT_REG 0x06 + +#define CPLD_MAC_INTR_REG 0x10 +#define CPLD_HWM_INTR_REG 0x13 +#define CPLD_CPLD2_INTR_REG 0x14 +#define CPLD_NTM_INTR_REG 0x15 +#define CPLD_FAN_PSU_INTR_REG 0x16 +#define CPLD_SFP_IOEXP_INTR_REG 0x18 +#define CPLD_CPU_NMI_INTR_REG 0x19 +#define CPLD_PTP_INTR_REG 0x1B +#define CPLD_SYSTEM_INTR_REG 0x1C + +#define CPLD_MAC_MASK_REG 0x20 +#define CPLD_HWM_MASK_REG 0x23 +#define CPLD_CPLD2_MASK_REG 0x24 +#define CPLD_NTM_MASK_REG 0x25 +#define CPLD_FAN_PSU_MASK_REG 0x26 +#define CPLD_SFP_IOEXP_MASK_REG 0x28 +#define CPLD_CPU_NMI_MASK_REG 0x29 +#define CPLD_PTP_MASK_REG 0x2B +#define CPLD_SYSTEM_MASK_REG 0x2C + +#define CPLD_MAC_EVT_REG 0x30 +#define CPLD_HWM_EVT_REG 0x33 +#define CPLD_CPLD2_EVT_REG 0x34 +#define CPLD_NTM_EVT_REG 0x35 +#define CPLD_FAN_PSU_EVT_REG 0x36 +#define CPLD_SFP_IOEXP_EVT_REG 0x38 +#define CPLD_CPU_NMI_EVT_REG 0x39 +#define CPLD_PTP_EVT_REG 0x3B + +#define CPLD_MAC_RESET_REG 0x40 +#define CPLD_SYSTEM_RESET_REG 0x41 +#define CPLD_BMC_NTM_RESET_REG 0x43 +#define CPLD_USB_RESET_REG 0x44 +#define CPLD_I2C_MUX_RESET_REG 0x46 +#define CPLD_I2C_MUX_RESET_2_REG 0x47 +#define CPLD_MISC_RESET_REG 0x48 + +#define CPLD_BRD_PRESENT_REG 0x50 +#define CPLD_PSU_STATUS_REG 0x51 +#define CPLD_SYSTEM_PWR_REG 0x52 +#define CPLD_MAC_SYNCE_REG 0x53 +#define CPLD_MAC_AVS_REG 0x54 +#define CPLD_SYSTEM_STATUS_REG 0x55 +#define CPLD_FAN_PRESENT_REG 0x56 +#define CPLD_WATCHDOG_REG 0x5A +#define CPLD_BOOT_SELECT_REG 0x5B +#define CPLD_MUX_CTRL_REG 0x5C +#define CPLD_MISC_CTRL_1_REG 0x5D +#define CPLD_MISC_CTRL_2_REG 0x5E +#define CPLD_TIMING_CTRL_REG 0x5F + +#define CPLD_MAC_TEMP_REG 0x61 + +/* +#define CPLD_SYSTEM_LED_SYS_FAN_REG 0x80 +#define CPLD_SYSTEM_LED_PSU_REG 0x81 +#define CPLD_SYSTEM_LED_SYNC_REG 0x82 +#define CPLD_SYSTEM_LED_ID_REG 0x84 +*/ +#define CPLD_SYSTEM_LED_PSU_REG 0x80 +#define CPLD_SYSTEM_LED_SYS_REG 0x81 +#define CPLD_SYSTEM_LED_SYNC_REG 0x82 +#define CPLD_SYSTEM_LED_FAN_REG 0x83 +#define CPLD_SYSTEM_LED_ID_REG 0x84 + +#define CPLD_MAC_PG_REG 0x90 +#define CPLD_MISC_PG_REG 0x92 +#define CPLD_MAC_PG_EN_REG 0x93 +#define CPLD_MISC_PG_EN_REG 0x95 + +#define DBG_CPLD_MAC_INTR_REG 0xE0 +#define DBG_CPLD_HWM_INTR_REG 0xE3 +#define DBG_CPLD_CPLD2_INTR_REG 0xE4 +#define DBG_CPLD_NTM_INTR_REG 0xE5 +#define DBG_CPLD_FAN_PSU_INTR_REG 0xE6 +#define DBG_CPLD_SFP_IOEXP_INTR_REG 0xE8 +#define DBG_CPLD_PTP_INTR_REG 0xEB + +#define CPLD_UPG_RESET_REG 0xF0 + +/* CPLD 2*/ + +//interrupt status +#define CPLD_SFP_INTR_PRESENT_0_7_REG 0x10 +#define CPLD_SFP_INTR_PRESENT_8_15_REG 0x11 +#define CPLD_SFP_INTR_PRESENT_16_23_REG 0x12 +#define CPLD_SFP_INTR_PRESENT_24_31_REG 0x13 +#define CPLD_SFP_INTR_PRESENT_32_39_REG 0x14 +#define CPLD_SFP_INTR_PRESENT_40_47_REG 0x15 +#define CPLD_QSFP_INTR_PRESENT_48_53_REG 0x16 +#define CPLD_QSFP_INTR_PORT_48_53_REG 0x17 + +//interrupt mask +#define CPLD_SFP_MASK_PRESENT_0_7_REG 0x20 +#define CPLD_SFP_MASK_PRESENT_8_15_REG 0x21 +#define CPLD_SFP_MASK_PRESENT_16_23_REG 0x22 +#define CPLD_SFP_MASK_PRESENT_24_31_REG 0x23 +#define CPLD_SFP_MASK_PRESENT_32_39_REG 0x24 +#define CPLD_SFP_MASK_PRESENT_40_47_REG 0x25 +#define CPLD_QSFP_MASK_PRESENT_48_53_REG 0x26 +#define CPLD_QSFP_MASK_PORT_48_53_REG 0x27 + +//interrupt event +#define CPLD_SFP_EVT_PRESENT_0_7_REG 0x30 +#define CPLD_SFP_EVT_PRESENT_8_15_REG 0x31 +#define CPLD_SFP_EVT_PRESENT_16_23_REG 0x32 +#define CPLD_SFP_EVT_PRESENT_24_31_REG 0x33 +#define CPLD_SFP_EVT_PRESENT_32_39_REG 0x34 +#define CPLD_SFP_EVT_PRESENT_40_47_REG 0x35 +#define CPLD_QSFP_EVT_PRESENT_48_53_REG 0x36 +#define CPLD_QSFP_EVT_PORT_48_53_REG 0x37 + +#define CPLD_SFP_INTR_RX_LOS_0_7_REG 0x40 +#define CPLD_SFP_INTR_RX_LOS_8_15_REG 0x41 +#define CPLD_SFP_INTR_RX_LOS_16_23_REG 0x42 +#define CPLD_SFP_INTR_RX_LOS_24_31_REG 0x43 +#define CPLD_SFP_INTR_RX_LOS_32_39_REG 0x44 +#define CPLD_SFP_INTR_RX_LOS_40_47_REG 0x45 + +#define CPLD_SFP_INTR_TX_FAULT_0_7_REG 0x46 +#define CPLD_SFP_INTR_TX_FAULT_8_15_REG 0x47 +#define CPLD_SFP_INTR_TX_FAULT_16_23_REG 0x48 +#define CPLD_SFP_INTR_TX_FAULT_24_31_REG 0x49 +#define CPLD_SFP_INTR_TX_FAULT_32_39_REG 0x4A +#define CPLD_SFP_INTR_TX_FAULT_40_47_REG 0x4B + +//#define CPLD_SFP_RX_LOS_BASE_REG 0x40 +//#define CPLD_SFP_TX_FAULT_BASE_REG 0x46 + +#define CPLD_SFP_MASK_RX_LOS_0_7_REG 0x50 +#define CPLD_SFP_MASK_RX_LOS_8_15_REG 0x51 +#define CPLD_SFP_MASK_RX_LOS_16_23_REG 0x52 +#define CPLD_SFP_MASK_RX_LOS_24_31_REG 0x53 +#define CPLD_SFP_MASK_RX_LOS_32_39_REG 0x54 +#define CPLD_SFP_MASK_RX_LOS_40_47_REG 0x55 + +#define CPLD_SFP_MASK_TX_FAULT_0_7_REG 0x56 +#define CPLD_SFP_MASK_TX_FAULT_8_15_REG 0x57 +#define CPLD_SFP_MASK_TX_FAULT_16_23_REG 0x58 +#define CPLD_SFP_MASK_TX_FAULT_24_31_REG 0x59 +#define CPLD_SFP_MASK_TX_FAULT_32_39_REG 0x5A +#define CPLD_SFP_MASK_TX_FAULT_40_47_REG 0x5B + +//#define CPLD_SFP_RX_LOS_MASK_BASE_REG 0x50 +//#define CPLD_SFP_TX_FAULT_MASK_BASE_REG 0x56 + +#define CPLD_SFP_EVT_RX_LOS_0_7_REG 0x60 +#define CPLD_SFP_EVT_RX_LOS_8_15_REG 0x61 +#define CPLD_SFP_EVT_RX_LOS_16_23_REG 0x62 +#define CPLD_SFP_EVT_RX_LOS_24_31_REG 0x63 +#define CPLD_SFP_EVT_RX_LOS_32_39_REG 0x64 +#define CPLD_SFP_EVT_RX_LOS_40_47_REG 0x65 + +#define CPLD_SFP_EVT_TX_FAULT_0_7_REG 0x66 +#define CPLD_SFP_EVT_TX_FAULT_8_15_REG 0x67 +#define CPLD_SFP_EVT_TX_FAULT_16_23_REG 0x68 +#define CPLD_SFP_EVT_TX_FAULT_24_31_REG 0x69 +#define CPLD_SFP_EVT_TX_FAULT_32_39_REG 0x6A +#define CPLD_SFP_EVT_TX_FAULT_40_47_REG 0x6B + +//#define CPLD_SFP_RX_LOS_EVT_BASE_REG 0x60 +//#define CPLD_SFP_TX_FAULT_EVT_BASE_REG 0x66 + +#define CPLD_SFP_TX_DISABLE_0_7_REG 0x70 +#define CPLD_SFP_TX_DISABLE_8_15_REG 0x71 +#define CPLD_SFP_TX_DISABLE_16_23_REG 0x72 +#define CPLD_SFP_TX_DISABLE_24_31_REG 0x73 +#define CPLD_SFP_TX_DISABLE_32_39_REG 0x74 +#define CPLD_SFP_TX_DISABLE_40_47_REG 0x75 + +//#define CPLD_SFP_TX_DISABLE_BASE_REG 0x70 +#define CPLD_QSFP_RESET_48_53_REG 0x76 +#define CPLD_QSFP_LPMODE_48_53_REG 0x77 + +//debug interrupt status +#define DBG_CPLD_SFP_INTR_PRESENT_BASE_REG 0xD0 +#define DBG_CPLD_SFP_INTR_PRESENT_0_7_REG 0xD0 +#define DBG_CPLD_SFP_INTR_PRESENT_8_15_REG 0xD1 +#define DBG_CPLD_SFP_INTR_PRESENT_16_23_REG 0xD2 +#define DBG_CPLD_SFP_INTR_PRESENT_24_31_REG 0xD3 +#define DBG_CPLD_SFP_INTR_PRESENT_32_39_REG 0xD4 +#define DBG_CPLD_SFP_INTR_PRESENT_40_47_REG 0xD5 +#define DBG_CPLD_QSFP_INTR_PRESENT_48_53_REG 0xD6 +#define DBG_CPLD_QSFP_INTR_PORT_48_53_REG 0xD7 + +//debug interrupt mask +#define DBG_CPLD_SFP_INTR_RX_LOS_0_7_REG 0xE0 +#define DBG_CPLD_SFP_INTR_RX_LOS_8_15_REG 0xE1 +#define DBG_CPLD_SFP_INTR_RX_LOS_16_23_REG 0xE2 +#define DBG_CPLD_SFP_INTR_RX_LOS_24_31_REG 0xE3 +#define DBG_CPLD_SFP_INTR_RX_LOS_32_39_REG 0xE4 +#define DBG_CPLD_SFP_INTR_RX_LOS_40_47_REG 0xE5 + +#define DBG_CPLD_SFP_INTR_TX_FAULT_0_7_REG 0xE6 +#define DBG_CPLD_SFP_INTR_TX_FAULT_8_15_REG 0xE7 +#define DBG_CPLD_SFP_INTR_TX_FAULT_16_23_REG 0xE8 +#define DBG_CPLD_SFP_INTR_TX_FAULT_24_31_REG 0xE9 +#define DBG_CPLD_SFP_INTR_TX_FAULT_32_39_REG 0xEA +#define DBG_CPLD_SFP_INTR_TX_FAULT_40_47_REG 0xEB + +//#define DBG_CPLD_SFP_RX_LOS_BASE_REG 0xE0 +//#define DBG_CPLD_SFP_TX_FAULT_BASE_REG 0xE6 + +//MASK +#define MASK_ALL (0xFF) +#define MASK_HB (0b11110000) +#define MASK_LB (0b00001111) +#define MASK_CPLD_MAJOR_VER (0b11000000) +#define MASK_CPLD_MINOR_VER (0b00111111) +#define CPLD_SYSTEM_LED_SYS_MASK MASK_HB +#define CPLD_SYSTEM_LED_FAN_MASK MASK_LB +#define CPLD_SYSTEM_LED_PSU_0_MASK MASK_LB +#define CPLD_SYSTEM_LED_PSU_1_MASK MASK_HB +#define CPLD_SYSTEM_LED_SYNC_MASK MASK_LB +#define CPLD_SYSTEM_LED_ID_MASK MASK_LB +#define CPLD_SFP_LED_MASK_0 (0b00000011) +#define CPLD_SFP_LED_MASK_1 (0b00001100) +#define PERM_R (0b00000001) +#define PERM_W (0b00000010) +#define PERM_RW (PERM_R | PERM_W) +#define IS_PERM_R(perm) (perm & PERM_R ? 1u : 0u) +#define IS_PERM_W(perm) (perm & PERM_W ? 1u : 0u) + +/* common manipulation */ +#define INVALID(i, min, max) ((i < min) || (i > max) ? 1u : 0u) + +#endif diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/modules/x86-64-ufispace-s8901-54xc-lpc.c b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/modules/x86-64-ufispace-s8901-54xc-lpc.c new file mode 100644 index 000000000000..72de01c48c4a --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/modules/x86-64-ufispace-s8901-54xc-lpc.c @@ -0,0 +1,883 @@ +/* + * A lpc driver for the ufispace_s8901_54xc + * + * Copyright (C) 2017-2022 UfiSpace Technology Corporation. + * Jason Tsai + * + * Based on ad7414.c + * Copyright 2006 Stefan Roese , DENX Software Engineering + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include + +#define BSP_LOG_R(fmt, args...) \ + _bsp_log (LOG_READ, KERN_INFO "%s:%s[%d]: " fmt "\r\n", \ + __FILE__, __func__, __LINE__, ##args) +#define BSP_LOG_W(fmt, args...) \ + _bsp_log (LOG_WRITE, KERN_INFO "%s:%s[%d]: " fmt "\r\n", \ + __FILE__, __func__, __LINE__, ##args) +#define BSP_PR(level, fmt, args...) _bsp_log (LOG_SYS, level "[BSP]" fmt "\r\n", ##args) + +#define _SENSOR_DEVICE_ATTR_RO(_name, _func, _index) \ + SENSOR_DEVICE_ATTR(_name, S_IRUGO, read_##_func, NULL, _index) + +#define _SENSOR_DEVICE_ATTR_WO(_name, _func, _index) \ + SENSOR_DEVICE_ATTR(_name, S_IWUSR, NULL, write_##_func, _index) + +#define _SENSOR_DEVICE_ATTR_RW(_name, _func, _index) \ + SENSOR_DEVICE_ATTR(_name, S_IRUGO | S_IWUSR, read_##_func, write_##_func, _index) + +#define _DEVICE_ATTR(_name) \ + &sensor_dev_attr_##_name.dev_attr.attr + +#define BSP_PR(level, fmt, args...) _bsp_log (LOG_SYS, level "[BSP]" fmt "\r\n", ##args) + +#define DRIVER_NAME "x86_64_ufispace_s8901_54xc_lpc" + +/* LPC registers */ + +#define REG_BASE_MB 0x700 +#define REG_BASE_EC 0xE300 + +#define REG_NONE 0x00 +//MB CPLD +#define REG_BRD_ID_0 (REG_BASE_MB + 0x00) +#define REG_BRD_ID_1 (REG_BASE_MB + 0x01) +#define REG_CPLD_VERSION (REG_BASE_MB + 0x02) +#define REG_CPLD_ID (REG_BASE_MB + 0x03) +#define REG_CPLD_BUILD (REG_BASE_MB + 0x04) +#define REG_CPLD_CHIP (REG_BASE_MB + 0x05) +#define REG_BRD_EXT_ID (REG_BASE_MB + 0x06) +#define REG_I2C_MUX_RESET (REG_BASE_MB + 0x46) +#define REG_I2C_MUX_RESET_2 (REG_BASE_MB + 0x47) +#define REG_MUX_CTRL (REG_BASE_MB + 0x5C) +#define REG_MISC_CTRL (REG_BASE_MB + 0x5D) +#define REG_MISC_CTRL_2 (REG_BASE_MB + 0x5E) + +//EC +#define REG_BIOS_BOOT (REG_BASE_EC + 0x0C) +#define REG_CPU_REV (REG_BASE_EC + 0x17) + +// BMC mailbox +#define REG_TEMP_MAC_HWM (REG_BASE_MB + 0xC0) + +//MASK +#define MASK_ALL (0xFF) +#define MASK_CPLD_MAJOR_VER (0b11000000) +#define MASK_CPLD_MINOR_VER (0b00111111) +#define MASK_HW_ID (0b00000011) +#define MASK_DEPH_ID (0b00000100) +#define MASK_BUILD_ID (0b00011000) +#define MASK_EXT_ID (0b00000111) +#define MASK_MUX_RESET_ALL (0x37) // 2#00110111 +#define MASK_MUX_RESET (MASK_ALL) +#define MASK_BIOS_BOOT_ROM (0b01000000) + +#define LPC_MDELAY (5) +#define MDELAY_RESET_INTERVAL (100) +#define MDELAY_RESET_FINISH (500) + +/* LPC sysfs attributes index */ +enum lpc_sysfs_attributes { + //MB CPLD + ATT_BRD_ID_0, + ATT_BRD_ID_1, + ATT_BRD_SKU_ID, + ATT_BRD_HW_ID, + ATT_BRD_DEPH_ID, + ATT_BRD_BUILD_ID, + ATT_BRD_EXT_ID, + + ATT_CPLD_ID, + ATT_CPLD_BUILD, + ATT_CPLD_CHIP, + + ATT_CPLD_VERSION_MAJOR, + ATT_CPLD_VERSION_MINOR, + ATT_CPLD_VERSION_BUILD, + ATT_CPLD_VERSION_H, + + ATT_MUX_RESET, + ATT_MUX_CTRL, + + //EC + ATT_CPU_HW_ID, + ATT_CPU_DEPH_ID, + ATT_CPU_BUILD_ID, + ATT_BIOS_BOOT_ROM, + //BMC mailbox + ATT_TEMP_MAC_HWM, + + //BSP + ATT_BSP_VERSION, + ATT_BSP_DEBUG, + ATT_BSP_PR_INFO, + ATT_BSP_PR_ERR, + ATT_BSP_REG, + ATT_BSP_GPIO_MAX, + ATT_MAX +}; + +enum data_type { + DATA_HEX, + DATA_DEC, + DATA_S_DEC, + DATA_UNK, +}; + +enum bsp_log_types { + LOG_NONE, + LOG_RW, + LOG_READ, + LOG_WRITE, + LOG_SYS +}; + +enum bsp_log_ctrl { + LOG_DISABLE, + LOG_ENABLE +}; + +struct lpc_data_s { + struct mutex access_lock; +}; + +typedef struct sysfs_info_s +{ + u16 reg; + u8 mask; + u8 data_type; +} sysfs_info_t; + +static sysfs_info_t sysfs_info[] = { + [ATT_BRD_ID_0] = {REG_BRD_ID_0, MASK_ALL, DATA_HEX}, + [ATT_BRD_ID_1] = {REG_BRD_ID_1, MASK_ALL, DATA_HEX}, + [ATT_BRD_SKU_ID] = {REG_BRD_ID_0, MASK_ALL, DATA_DEC}, + [ATT_BRD_HW_ID] = {REG_BRD_ID_1, MASK_HW_ID, DATA_DEC}, + [ATT_BRD_DEPH_ID] = {REG_BRD_ID_1, MASK_DEPH_ID, DATA_DEC}, + [ATT_BRD_BUILD_ID] = {REG_BRD_ID_1, MASK_BUILD_ID, DATA_DEC}, + [ATT_BRD_EXT_ID] = {REG_BRD_EXT_ID, MASK_EXT_ID, DATA_DEC}, + + [ATT_CPLD_ID] = {REG_CPLD_ID, MASK_ALL, DATA_DEC}, + [ATT_CPLD_BUILD] = {REG_CPLD_BUILD, MASK_ALL, DATA_DEC}, + [ATT_CPLD_CHIP] = {REG_CPLD_CHIP, MASK_ALL, DATA_DEC}, + + [ATT_CPLD_VERSION_MAJOR] = {REG_CPLD_VERSION, MASK_CPLD_MAJOR_VER, DATA_DEC}, + [ATT_CPLD_VERSION_MINOR] = {REG_CPLD_VERSION, MASK_CPLD_MINOR_VER, DATA_DEC}, + [ATT_CPLD_VERSION_BUILD] = {REG_CPLD_BUILD, MASK_ALL, DATA_DEC}, + [ATT_CPLD_VERSION_H] = {REG_CPLD_VERSION, MASK_ALL, DATA_UNK}, + + [ATT_MUX_RESET] = {REG_NONE, MASK_ALL, DATA_DEC}, + [ATT_MUX_CTRL] = {REG_MUX_CTRL, MASK_ALL, DATA_HEX}, + + //EC + [ATT_CPU_HW_ID] = {REG_CPU_REV, MASK_HW_ID, DATA_DEC}, + [ATT_CPU_DEPH_ID] = {REG_CPU_REV, MASK_DEPH_ID, DATA_DEC}, + [ATT_CPU_BUILD_ID] = {REG_CPU_REV, MASK_BUILD_ID, DATA_DEC}, + [ATT_BIOS_BOOT_ROM] = {REG_BIOS_BOOT, MASK_BIOS_BOOT_ROM, DATA_DEC}, + + //BMC mailbox + [ATT_TEMP_MAC_HWM] = {REG_TEMP_MAC_HWM , MASK_ALL, DATA_S_DEC}, + + //BSP + [ATT_BSP_VERSION] = {REG_NONE, MASK_ALL, DATA_UNK}, + [ATT_BSP_DEBUG] = {REG_NONE, MASK_ALL, DATA_UNK}, + [ATT_BSP_PR_INFO] = {REG_NONE, MASK_ALL, DATA_UNK}, + [ATT_BSP_PR_ERR] = {REG_NONE, MASK_ALL, DATA_UNK}, + [ATT_BSP_REG] = {REG_NONE, MASK_ALL, DATA_HEX}, +}; + +struct lpc_data_s *lpc_data; +char bsp_version[16]=""; +char bsp_debug[2]="0"; +char bsp_reg[8]="0x0"; +u8 enable_log_read = LOG_DISABLE; +u8 enable_log_write = LOG_DISABLE; +u8 enable_log_sys = LOG_ENABLE; +u8 mailbox_inited=0; + +/* reg shift */ +static u8 _shift(u8 mask) +{ + int i=0, mask_one=1; + + for(i=0; i<8; ++i) { + if ((mask & mask_one) == 1) + return i; + else + mask >>= 1; + } + + return -1; +} + +/* reg mask and shift */ +static u8 _mask_shift(u8 val, u8 mask) +{ + int shift=0; + + shift = _shift(mask); + + return (val & mask) >> shift; +} + +static u8 _parse_data(char *buf, unsigned int data, u8 data_type) +{ + if(buf == NULL) { + return -1; + } + + if(data_type == DATA_HEX) { + return sprintf(buf, "0x%02x", data); + } else if(data_type == DATA_DEC) { + return sprintf(buf, "%u", data); + } else { + return -1; + } + return 0; +} + +static int _bsp_log(u8 log_type, char *fmt, ...) +{ + if ((log_type==LOG_READ && enable_log_read) || + (log_type==LOG_WRITE && enable_log_write) || + (log_type==LOG_SYS && enable_log_sys) ) { + va_list args; + int r; + + va_start(args, fmt); + r = vprintk(fmt, args); + va_end(args); + + return r; + } else { + return 0; + } +} + +static int _config_bsp_log(u8 log_type) +{ + switch(log_type) { + case LOG_NONE: + enable_log_read = LOG_DISABLE; + enable_log_write = LOG_DISABLE; + break; + case LOG_RW: + enable_log_read = LOG_ENABLE; + enable_log_write = LOG_ENABLE; + break; + case LOG_READ: + enable_log_read = LOG_ENABLE; + enable_log_write = LOG_DISABLE; + break; + case LOG_WRITE: + enable_log_read = LOG_DISABLE; + enable_log_write = LOG_ENABLE; + break; + default: + return -EINVAL; + } + return 0; +} + +static void _outb(u8 data, u16 port) +{ + outb(data, port); + mdelay(LPC_MDELAY); +} + +/* init bmc mailbox, get from BMC team */ +static int bmc_mailbox_init(void) +{ + if (mailbox_inited) { + return mailbox_inited; + } + + //Enable super io writing + _outb(0xa5, 0x2e); + _outb(0xa5, 0x2e); + + //Logic device number + _outb(0x07, 0x2e); + _outb(0x0e, 0x2f); + + //Disable mailbox + _outb(0x30, 0x2e); + _outb(0x00, 0x2f); + + //Set base address bit + _outb(0x60, 0x2e); + _outb(0x07, 0x2f); + _outb(0x61, 0x2e); + _outb(0xc0, 0x2f); + + //Select bit[3:0] of SIRQ + _outb(0x70, 0x2e); + _outb(0x07, 0x2f); + + //Low level trigger + _outb(0x71, 0x2e); + _outb(0x01, 0x2f); + + //Enable mailbox + _outb(0x30, 0x2e); + _outb(0x01, 0x2f); + + //Disable super io writing + _outb(0xaa, 0x2e); + + //Mailbox initial + _outb(0x00, 0x786); + _outb(0x00, 0x787); + + //set mailbox_inited + mailbox_inited = 1; + + return mailbox_inited; +} + +/* get lpc register value */ +static u8 _read_lpc_reg(u16 reg, u8 mask) +{ + u8 reg_val=0x0, reg_mk_shf_val = 0x0; + + mutex_lock(&lpc_data->access_lock); + reg_val = inb(reg); + mutex_unlock(&lpc_data->access_lock); + + reg_mk_shf_val = _mask_shift(reg_val, mask); + + BSP_LOG_R("reg=0x%03x, reg_val=0x%02x, mask=0x%02x, reg_mk_shf_val=0x%02x", reg, reg_val, mask, reg_mk_shf_val); + + return reg_mk_shf_val; +} + +/* get lpc register value */ +static ssize_t read_lpc_reg(u16 reg, u8 mask, char *buf, u8 data_type) +{ + u8 reg_val; + int len=0; + + reg_val = _read_lpc_reg(reg, mask); + + // may need to change to hex value ? + len=_parse_data(buf, reg_val, data_type); + + return len; +} + +/* set lpc register value */ +static ssize_t write_lpc_reg(u16 reg, u8 mask, const char *buf, size_t count, u8 data_type) +{ + u8 reg_val, reg_val_now, shift; + + if (kstrtou8(buf, 0, ®_val) < 0) { + if(data_type == DATA_S_DEC) { + if (kstrtos8(buf, 0, ®_val) < 0) { + return -EINVAL; + } + } else { + return -EINVAL; + } + } + + //apply continuous bits operation if mask is specified, discontinuous bits are not supported + if (mask != MASK_ALL) { + reg_val_now = _read_lpc_reg(reg, MASK_ALL); + //clear bits in reg_val_now by the mask + reg_val_now &= ~mask; + //get bit shift by the mask + shift = _shift(mask); + //calculate new reg_val + reg_val = reg_val_now | (reg_val << shift); + } + + mutex_lock(&lpc_data->access_lock); + + _outb(reg_val, reg); + + mutex_unlock(&lpc_data->access_lock); + + BSP_LOG_W("reg=0x%03x, reg_val=0x%02x, mask=0x%02x", reg, reg_val, mask); + + return count; +} + +/* get bsp value */ +static ssize_t read_bsp(char *buf, char *str) +{ + ssize_t len=0; + + mutex_lock(&lpc_data->access_lock); + len=sprintf(buf, "%s", str); + mutex_unlock(&lpc_data->access_lock); + + BSP_LOG_R("reg_val=%s", str); + + return len; +} + +/* set bsp value */ +static ssize_t write_bsp(const char *buf, char *str, size_t str_len, size_t count) +{ + mutex_lock(&lpc_data->access_lock); + snprintf(str, str_len, "%s", buf); + mutex_unlock(&lpc_data->access_lock); + + BSP_LOG_W("reg_val=%s", str); + + return count; +} + +/* get gpio max value */ +static ssize_t read_gpio_max(struct device *dev, + struct device_attribute *da, + char *buf) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + + if (attr->index == ATT_BSP_GPIO_MAX) { + return sprintf(buf, "%d\n", ARCH_NR_GPIOS-1); + } + return -1; +} + +/* get mb cpld version in human readable format */ +static ssize_t read_mb_cpld_version_h(struct device *dev, + struct device_attribute *da, char *buf) +{ + ssize_t len=0; + u8 major = 0, minor = 0, build = 0; + major = _read_lpc_reg(REG_CPLD_VERSION, MASK_CPLD_MAJOR_VER); + minor = _read_lpc_reg(REG_CPLD_VERSION, MASK_CPLD_MINOR_VER); + build = _read_lpc_reg(REG_CPLD_BUILD, MASK_ALL); + len=sprintf(buf, "%u.%02u.%03u", major, minor, build); + + return len; +} + +/* get lpc register value */ +static ssize_t read_lpc_callback(struct device *dev, + struct device_attribute *da, char *buf) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + u16 reg = 0; + u8 mask = MASK_ALL; + u8 data_type = DATA_UNK; + + if (attr->index == ATT_BSP_REG) { + //copy value from bsp_reg + if (kstrtou16(bsp_reg, 0, ®) < 0) + return -EINVAL; + + data_type = sysfs_info[attr->index].data_type; + } else { + reg = sysfs_info[attr->index].reg; + mask = sysfs_info[attr->index].mask; + data_type = sysfs_info[attr->index].data_type; + } + + return read_lpc_reg(reg, mask, buf, data_type); +} + +/* set lpc register value */ +static ssize_t write_lpc_callback(struct device *dev, + struct device_attribute *da, const char *buf, size_t count) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + u16 reg = 0; + u8 mask = MASK_ALL; + u8 data_type = DATA_UNK; + + reg = sysfs_info[attr->index].reg; + mask = sysfs_info[attr->index].mask; + data_type = sysfs_info[attr->index].data_type; + + if(attr->index == ATT_TEMP_MAC_HWM) { + bmc_mailbox_init(); + } + + return write_lpc_reg(reg, mask, buf, count, data_type); +} + +/* get bsp parameter value */ +static ssize_t read_bsp_callback(struct device *dev, + struct device_attribute *da, char *buf) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + char *str=NULL; + + switch (attr->index) { + case ATT_BSP_VERSION: + str = bsp_version; + break; + case ATT_BSP_DEBUG: + str = bsp_debug; + break; + case ATT_BSP_REG: + str = bsp_reg; + break; + default: + return -EINVAL; + } + return read_bsp(buf, str); +} + +/* set bsp parameter value */ +static ssize_t write_bsp_callback(struct device *dev, + struct device_attribute *da, const char *buf, size_t count) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + int str_len=0; + char *str=NULL; + u16 reg = 0; + u8 bsp_debug_u8 = 0; + + switch (attr->index) { + case ATT_BSP_VERSION: + str = bsp_version; + str_len = sizeof(bsp_version); + break; + case ATT_BSP_DEBUG: + str = bsp_debug; + str_len = sizeof(bsp_debug); + break; + case ATT_BSP_REG: + if (kstrtou16(buf, 0, ®) < 0) + return -EINVAL; + + str = bsp_reg; + str_len = sizeof(bsp_reg); + break; + default: + return -EINVAL; + } + + if (attr->index == ATT_BSP_DEBUG) { + if (kstrtou8(buf, 0, &bsp_debug_u8) < 0) { + return -EINVAL; + } else if (_config_bsp_log(bsp_debug_u8) < 0) { + return -EINVAL; + } + } + + return write_bsp(buf, str, str_len, count); +} + +static ssize_t write_bsp_pr_callback(struct device *dev, + struct device_attribute *da, const char *buf, size_t count) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + int str_len = strlen(buf); + + if(str_len <= 0) + return str_len; + + switch (attr->index) { + case ATT_BSP_PR_INFO: + BSP_PR(KERN_INFO, "%s", buf); + break; + case ATT_BSP_PR_ERR: + BSP_PR(KERN_ERR, "%s", buf); + break; + default: + return -EINVAL; + } + + return str_len; +} + +/* set mux_reset register value */ +static ssize_t write_mux_reset(struct device *dev, + struct device_attribute *da, const char *buf, size_t count) +{ + u16 reg = REG_I2C_MUX_RESET; + u8 val = 0; + u8 mux_reset_reg_val = 0; + static int mux_reset_flag = 0; + + if (kstrtou8(buf, 0, &val) < 0) + return -EINVAL; + + if (mux_reset_flag == 0) { + if (val == 0) { + mutex_lock(&lpc_data->access_lock); + mux_reset_flag = 1; + BSP_LOG_W("i2c mux reset is triggered..."); + + //reset mux on SFP/QSFP ports + mux_reset_reg_val = inb(reg); + _outb((mux_reset_reg_val & (u8) (~MASK_MUX_RESET)), reg); + BSP_LOG_W("reg=0x%03x, reg_val=0x%02x", reg, mux_reset_reg_val & 0x0); + + //unset mux on SFP/QSFP ports + outb((mux_reset_reg_val | MASK_MUX_RESET), reg); + mdelay(500); + BSP_LOG_W("reg=0x%03x, reg_val=0x%02x", reg, mux_reset_reg_val | 0xFF); + + mux_reset_flag = 0; + mutex_unlock(&lpc_data->access_lock); + } else { + return -EINVAL; + } + } else { + BSP_LOG_W("i2c mux is resetting... (ignore)"); + mutex_lock(&lpc_data->access_lock); + mutex_unlock(&lpc_data->access_lock); + } + + return count; +} + +//SENSOR_DEVICE_ATTR - MB +static _SENSOR_DEVICE_ATTR_RO(board_id_0, lpc_callback, ATT_BRD_ID_0); +static _SENSOR_DEVICE_ATTR_RO(board_id_1, lpc_callback, ATT_BRD_ID_1); +static _SENSOR_DEVICE_ATTR_RO(board_sku_id, lpc_callback, ATT_BRD_SKU_ID); +static _SENSOR_DEVICE_ATTR_RO(board_hw_id, lpc_callback, ATT_BRD_HW_ID); +static _SENSOR_DEVICE_ATTR_RO(board_deph_id, lpc_callback, ATT_BRD_DEPH_ID); +static _SENSOR_DEVICE_ATTR_RO(board_build_id, lpc_callback, ATT_BRD_BUILD_ID); +static _SENSOR_DEVICE_ATTR_RO(board_ext_id, lpc_callback, ATT_BRD_EXT_ID); +static _SENSOR_DEVICE_ATTR_RO(cpld_version_major, lpc_callback, ATT_CPLD_VERSION_MAJOR); +static _SENSOR_DEVICE_ATTR_RO(cpld_version_minor, lpc_callback, ATT_CPLD_VERSION_MINOR); +static _SENSOR_DEVICE_ATTR_RO(cpld_version_build, lpc_callback, ATT_CPLD_VERSION_BUILD); +static _SENSOR_DEVICE_ATTR_RO(cpld_version_h, mb_cpld_version_h, ATT_CPLD_VERSION_H); +static _SENSOR_DEVICE_ATTR_RO(cpld_id, lpc_callback, ATT_CPLD_ID); + +static _SENSOR_DEVICE_ATTR_WO(mux_reset, mux_reset, ATT_MUX_RESET); +static _SENSOR_DEVICE_ATTR_RW(mux_ctrl, lpc_callback, ATT_MUX_CTRL); + +//SENSOR_DEVICE_ATTR - BMC mailbox +static _SENSOR_DEVICE_ATTR_WO(temp_mac_hwm , lpc_callback , ATT_TEMP_MAC_HWM); + +//SENSOR_DEVICE_ATTR - EC +static _SENSOR_DEVICE_ATTR_RO(cpu_hw_id, lpc_callback, ATT_CPU_HW_ID); +static _SENSOR_DEVICE_ATTR_RO(cpu_deph_id, lpc_callback, ATT_CPU_DEPH_ID); +static _SENSOR_DEVICE_ATTR_RO(cpu_build_id, lpc_callback, ATT_CPU_BUILD_ID); +static _SENSOR_DEVICE_ATTR_RO(bios_boot_rom, lpc_callback, ATT_BIOS_BOOT_ROM); + +//SENSOR_DEVICE_ATTR - BSP +static _SENSOR_DEVICE_ATTR_RW(bsp_version, bsp_callback, ATT_BSP_VERSION); +static _SENSOR_DEVICE_ATTR_RW(bsp_debug, bsp_callback, ATT_BSP_DEBUG); +static _SENSOR_DEVICE_ATTR_WO(bsp_pr_info, bsp_pr_callback, ATT_BSP_PR_INFO); +static _SENSOR_DEVICE_ATTR_WO(bsp_pr_err, bsp_pr_callback, ATT_BSP_PR_ERR); +static SENSOR_DEVICE_ATTR(bsp_reg, S_IRUGO | S_IWUSR, read_lpc_callback, write_bsp_callback, ATT_BSP_REG); +static SENSOR_DEVICE_ATTR(bsp_gpio_max, S_IRUGO, read_gpio_max, NULL, ATT_BSP_GPIO_MAX); + +static struct attribute *mb_cpld_attrs[] = { + _DEVICE_ATTR(board_id_0), + _DEVICE_ATTR(board_id_1), + _DEVICE_ATTR(board_sku_id), + _DEVICE_ATTR(board_hw_id), + _DEVICE_ATTR(board_deph_id), + _DEVICE_ATTR(board_build_id), + _DEVICE_ATTR(board_ext_id), + _DEVICE_ATTR(cpld_version_major), + _DEVICE_ATTR(cpld_version_minor), + _DEVICE_ATTR(cpld_version_build), + _DEVICE_ATTR(cpld_version_h), + _DEVICE_ATTR(cpld_id), + _DEVICE_ATTR(mux_reset), + _DEVICE_ATTR(mux_ctrl), + NULL, +}; + +static struct attribute *bsp_attrs[] = { + _DEVICE_ATTR(bsp_version), + _DEVICE_ATTR(bsp_debug), + _DEVICE_ATTR(bsp_pr_info), + _DEVICE_ATTR(bsp_pr_err), + _DEVICE_ATTR(bsp_reg), + _DEVICE_ATTR(bsp_gpio_max), + NULL, +}; + +static struct attribute *ec_attrs[] = { + _DEVICE_ATTR(cpu_hw_id), + _DEVICE_ATTR(cpu_deph_id), + _DEVICE_ATTR(cpu_build_id), + _DEVICE_ATTR(bios_boot_rom), + NULL, +}; + +static struct attribute *bmc_mailbox_attrs[] = { + _DEVICE_ATTR(temp_mac_hwm), + NULL, +}; + +static struct attribute_group mb_cpld_attr_grp = { + .name = "mb_cpld", + .attrs = mb_cpld_attrs, +}; + +static struct attribute_group bsp_attr_grp = { + .name = "bsp", + .attrs = bsp_attrs, +}; + +static struct attribute_group ec_attr_grp = { + .name = "ec", + .attrs = ec_attrs, +}; + +static struct attribute_group bmc_mailbox_attr_grp = { + .name = "bmc_mailbox", + .attrs = bmc_mailbox_attrs, +}; + +static void lpc_dev_release( struct device * dev) +{ + return; +} + +static struct platform_device lpc_dev = { + .name = DRIVER_NAME, + .id = -1, + .dev = { + .release = lpc_dev_release, + } +}; + +static int lpc_drv_probe(struct platform_device *pdev) +{ + int i = 0, grp_num = 4; + int err[4] = {0}; + struct attribute_group *grp; + + lpc_data = devm_kzalloc(&pdev->dev, sizeof(struct lpc_data_s), + GFP_KERNEL); + if (!lpc_data) + return -ENOMEM; + + mutex_init(&lpc_data->access_lock); + + for (i=0; idev.kobj, grp); + if (err[i]) { + printk(KERN_ERR "Cannot create sysfs for group %s\n", grp->name); + goto exit; + } else { + continue; + } + } + + return 0; + +exit: + for (i=0; idev.kobj, grp); + if (!err[i]) { + //remove previous successful cases + continue; + } else { + //remove first failed case, then return + return err[i]; + } + } + return 0; +} + +static int lpc_drv_remove(struct platform_device *pdev) +{ + sysfs_remove_group(&pdev->dev.kobj, &mb_cpld_attr_grp); + sysfs_remove_group(&pdev->dev.kobj, &bmc_mailbox_attr_grp); + sysfs_remove_group(&pdev->dev.kobj, &bsp_attr_grp); + sysfs_remove_group(&pdev->dev.kobj, &ec_attr_grp); + + return 0; +} + +static struct platform_driver lpc_drv = { + .probe = lpc_drv_probe, + .remove = __exit_p(lpc_drv_remove), + .driver = { + .name = DRIVER_NAME, + }, +}; + +int lpc_init(void) +{ + int err = 0; + + err = platform_driver_register(&lpc_drv); + if (err) { + printk(KERN_ERR "%s(#%d): platform_driver_register failed(%d)\n", + __func__, __LINE__, err); + + return err; + } + + err = platform_device_register(&lpc_dev); + if (err) { + printk(KERN_ERR "%s(#%d): platform_device_register failed(%d)\n", + __func__, __LINE__, err); + platform_driver_unregister(&lpc_drv); + return err; + } + + return err; +} + +void lpc_exit(void) +{ + platform_driver_unregister(&lpc_drv); + platform_device_unregister(&lpc_dev); +} + +MODULE_AUTHOR("Jason Tsai "); +MODULE_DESCRIPTION("x86_64_ufispace_s8901_54xc_lpc driver"); +MODULE_LICENSE("GPL"); + +module_init(lpc_init); +module_exit(lpc_exit); diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/modules/x86-64-ufispace-s8901-54xc-sys-eeprom.c b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/modules/x86-64-ufispace-s8901-54xc-sys-eeprom.c new file mode 100644 index 000000000000..f9f7728deb3d --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/modules/x86-64-ufispace-s8901-54xc-sys-eeprom.c @@ -0,0 +1,272 @@ +/* + * Copyright (C) 1998, 1999 Frodo Looijaard and + * Philip Edelbrock + * Copyright (C) 2003 Greg Kroah-Hartman + * Copyright (C) 2003 IBM Corp. + * Copyright (C) 2004 Jean Delvare + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* enable dev_dbg print out */ +//#define DEBUG + +#define __STDC_WANT_LIB_EXT1__ 1 +#include +#include +#include +#include +#include +#include +#include + +/* Addresses to scan */ +static const unsigned short normal_i2c[] = { /*0x50, 0x51, 0x52, 0x53, 0x54, + 0x55, 0x56, 0x57,*/ I2C_CLIENT_END }; + +/* Size of EEPROM in bytes */ +#define EEPROM_SIZE 512 + +#define SLICE_BITS (6) +#define SLICE_SIZE (1 << SLICE_BITS) +#define SLICE_NUM (EEPROM_SIZE/SLICE_SIZE) + +/* Each client has this additional data */ +struct eeprom_data { + struct mutex update_lock; + u8 valid; /* bitfield, bit!=0 if slice is valid */ + unsigned long last_updated[SLICE_NUM]; /* In jiffies, 8 slices */ + u8 data[EEPROM_SIZE]; /* Register values */ +}; + + +static void sys_eeprom_update_client(struct i2c_client *client, u8 slice) +{ + struct eeprom_data *data = i2c_get_clientdata(client); + int i, j; + int ret; + int addr; + + mutex_lock(&data->update_lock); + + if (!(data->valid & (1 << slice)) || + time_after(jiffies, data->last_updated[slice] + 300 * HZ)) { + dev_dbg(&client->dev, "Starting eeprom update, slice %u\n", slice); + + addr = slice << SLICE_BITS; + + ret = i2c_smbus_write_byte_data(client, (u8)((addr >> 8) & 0xFF), (u8)(addr & 0xFF)); + /* select the eeprom address */ + if (ret < 0) { + dev_err(&client->dev, "address set failed\n"); + goto exit; + } + + if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_READ_BYTE)) { + goto exit; + } + + for (i = slice << SLICE_BITS; i < (slice + 1) << SLICE_BITS; i+= SLICE_SIZE) { + for (j = i; j < (i+SLICE_SIZE); j++) { + int res; + + res = i2c_smbus_read_byte(client); + if (res < 0) { + goto exit; + } + + data->data[j] = res & 0xFF; + } + } + + data->last_updated[slice] = jiffies; + data->valid |= (1 << slice); + } +exit: + mutex_unlock(&data->update_lock); +} + +static ssize_t sys_eeprom_read(struct file *filp, struct kobject *kobj, + struct bin_attribute *bin_attr, + char *buf, loff_t off, size_t count) +{ + struct i2c_client *client = to_i2c_client(container_of(kobj, struct device, kobj)); + struct eeprom_data *data = i2c_get_clientdata(client); + u8 slice; + + if (off > EEPROM_SIZE) { + return 0; + } + if (off + count > EEPROM_SIZE) { + count = EEPROM_SIZE - off; + } + if (count == 0) { + return 0; + } + + /* Only refresh slices which contain requested bytes */ + for (slice = off >> SLICE_BITS; slice <= (off + count - 1) >> SLICE_BITS; slice++) { + sys_eeprom_update_client(client, slice); + } + + memcpy(buf, &data->data[off], count); + + return count; +} + +static ssize_t sys_eeprom_write(struct file *filp, struct kobject *kobj, + struct bin_attribute *bin_attr, + char *buf, loff_t off, size_t count) +{ + struct i2c_client *client = to_i2c_client(container_of(kobj, struct device, kobj)); + struct eeprom_data *data = i2c_get_clientdata(client); + int ret; + int i; + u8 cmd; + u16 value16; + + dev_dbg(&client->dev, "sys_eeprom_write off=%d, count=%d\n", (int)off, (int)count); + + if (off > EEPROM_SIZE) { + return 0; + } + if (off + count > EEPROM_SIZE) { + count = EEPROM_SIZE - off; + } + if (count == 0) { + return 0; + } + + mutex_lock(&data->update_lock); + + for(i=0; i < count; i++) { + /* write command */ + cmd = (off >> 8) & 0xff; + value16 = off & 0xff; + value16 |= buf[i] << 8; + ret = i2c_smbus_write_word_data(client, cmd, value16); + + if (ret < 0) { + dev_err(&client->dev, "write address failed at %d \n", (int)off); + goto exit; + } + + off++; + + /* need to wait for write complete */ + udelay(10000); + } +exit: + mutex_unlock(&data->update_lock); + /* force to update client when reading */ + for(i=0; i < SLICE_NUM; i++) { + data->last_updated[i] = 0; + } + + return count; +} + +static struct bin_attribute sys_eeprom_attr = { + .attr = { + .name = "eeprom", + .mode = S_IRUGO | S_IWUSR, + }, + .size = EEPROM_SIZE, + .read = sys_eeprom_read, + .write = sys_eeprom_write, +}; + +/* Return 0 if detection is successful, -ENODEV otherwise */ +static int sys_eeprom_detect(struct i2c_client *client, struct i2c_board_info *info) +{ + struct i2c_adapter *adapter = client->adapter; + + /* EDID EEPROMs are often 24C00 EEPROMs, which answer to all + addresses 0x50-0x57, but we only care about 0x51 and 0x55. So decline + attaching to addresses >= 0x56 on DDC buses */ + if (!(adapter->class & I2C_CLASS_SPD) && client->addr >= 0x56) { + return -ENODEV; + } + + if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_READ_BYTE) + && !i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WRITE_BYTE_DATA)) { + return -ENODEV; + } + + strlcpy(info->type, "eeprom", I2C_NAME_SIZE); + + return 0; +} + +static int sys_eeprom_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct eeprom_data *data; + int err; + + if (!(data = kzalloc(sizeof(struct eeprom_data), GFP_KERNEL))) { + err = -ENOMEM; + goto exit; + } + +#ifdef __STDC_LIB_EXT1__ + memset_s(data->data, EEPROM_SIZE, 0xff, EEPROM_SIZE); +#else + memset(data->data, 0xff, EEPROM_SIZE); +#endif + i2c_set_clientdata(client, data); + mutex_init(&data->update_lock); + + /* create the sysfs eeprom file */ + err = sysfs_create_bin_file(&client->dev.kobj, &sys_eeprom_attr); + if (err) { + goto exit_kfree; + } + + return 0; + +exit_kfree: + kfree(data); +exit: + return err; +} + +static int sys_eeprom_remove(struct i2c_client *client) +{ + sysfs_remove_bin_file(&client->dev.kobj, &sys_eeprom_attr); + kfree(i2c_get_clientdata(client)); + + return 0; +} + +static const struct i2c_device_id sys_eeprom_id[] = { + { "sys_eeprom", 0 }, + { } +}; + +static struct i2c_driver sys_eeprom_driver = { + .driver = { + .name = "sys_eeprom", + }, + .probe = sys_eeprom_probe, + .remove = sys_eeprom_remove, + .id_table = sys_eeprom_id, + + .class = I2C_CLASS_DDC | I2C_CLASS_SPD, + .detect = sys_eeprom_detect, + .address_list = normal_i2c, +}; + +module_i2c_driver(sys_eeprom_driver); + +MODULE_AUTHOR("Jason "); +MODULE_DESCRIPTION("UfiSpace System EEPROM driver"); +MODULE_LICENSE("GPL"); diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/service/pddf-platform-init.service b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/service/pddf-platform-init.service new file mode 120000 index 000000000000..0fd9f25b6c5e --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/service/pddf-platform-init.service @@ -0,0 +1 @@ +../../../../pddf/i2c/service/pddf-platform-init.service \ No newline at end of file diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/sonic_platform/__init__.py b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/sonic_platform/__init__.py new file mode 100644 index 000000000000..593867d31c9d --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/sonic_platform/__init__.py @@ -0,0 +1,4 @@ +# All the derived classes for PDDF +__all__ = ["platform", "chassis", "sfp", "psu", "thermal", "fan"] +from . import platform + diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/sonic_platform/chassis.py b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/sonic_platform/chassis.py new file mode 100644 index 000000000000..085f2af2ff85 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/sonic_platform/chassis.py @@ -0,0 +1,193 @@ +#!/usr/bin/env python + +############################################################################# +# PDDF +# Module contains an implementation of SONiC Chassis API +# +############################################################################# + +try: + import time + from sonic_platform_pddf_base.pddf_chassis import PddfChassis +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + +NUM_COMPONENT = 4 + +class Chassis(PddfChassis): + """ + PDDF Platform-specific Chassis class + """ + + SYSLED_DEV_NAME = "SYS_LED" + port_dict = {} + + def __init__(self, pddf_data=None, pddf_plugin_data=None): + PddfChassis.__init__(self, pddf_data, pddf_plugin_data) + self._initialize_components() + + def _initialize_components(self): + from sonic_platform.component import Component + for index in range(NUM_COMPONENT): + component = Component(index) + self._component_list.append(component) + + # Provide the functions/variables below for which implementation is to be overwritten + def get_name(self): + """ + Retrieves the name of the chassis + Returns: + string: The name of the chassis + """ + # return device_info.get_hwsku() + return self._eeprom.platform_name_str() + + def initizalize_system_led(self): + return True + + def get_status_led(self): + return self.get_system_led(self.SYSLED_DEV_NAME) + + def get_change_event(self, timeout=0): + """ + Returns a nested dictionary containing all devices which have + experienced a change at chassis level + Args: + timeout: Timeout in milliseconds (optional). If timeout == 0, + this method will block until a change is detected. + Returns: + (bool, dict): + - bool: True if call successful, False if not; + - dict: A nested dictionary where key is a device type, + value is a dictionary with key:value pairs in the format of + {'device_id':'device_event'}, where device_id is the device ID + for this device and device_event. + The known devices's device_id and device_event was defined as table below. + ----------------------------------------------------------------- + device | device_id | device_event | annotate + ----------------------------------------------------------------- + 'fan' '' '0' Fan removed + '1' Fan inserted + 'sfp' '' '0' Sfp removed + '1' Sfp inserted + '2' I2C bus stuck + '3' Bad eeprom + '4' Unsupported cable + '5' High Temperature + '6' Bad cable + 'voltage' '' '0' Vout normal + '1' Vout abnormal + -------------------------------------------------------------------- + Ex. {'fan':{'0':'0', '2':'1'}, 'sfp':{'11':'0', '12':'1'}, + 'voltage':{'U20':'0', 'U21':'1'}} + Indicates that: + fan 0 has been removed, fan 2 has been inserted. + sfp 11 has been removed, sfp 12 has been inserted. + monitored voltage U20 became normal, voltage U21 became abnormal. + Note: For sfp, when event 3-6 happened, the module will not be avalaible, + XCVRD shall stop to read eeprom before SFP recovered from error status. + """ + + change_event_dict = {"fan": {}, "sfp": {}, "voltage": {}} + + start_time = time.time() + forever = False + + if timeout == 0: + forever = True + elif timeout > 0: + timeout = timeout / float(1000) # Convert to secs + else: + print("get_change_event:Invalid timeout value", timeout) + return False, change_event_dict + + end_time = start_time + timeout + if start_time > end_time: + print( + "get_change_event:" "time wrap / invalid timeout value", + timeout, + ) + return False, change_event_dict # Time wrap or possibly incorrect timeout + try: + while timeout >= 0: + # check for sfp + sfp_change_dict = self.get_transceiver_change_event() + # check for fan + # fan_change_dict = self.get_fan_change_event() + # check for voltage + # voltage_change_dict = self.get_voltage_change_event() + + if sfp_change_dict: + change_event_dict["sfp"] = sfp_change_dict + # change_event_dict["fan"] = fan_change_dict + # change_event_dict["voltage"] = voltage_change_dict + return True, change_event_dict + if forever: + time.sleep(1) + else: + timeout = end_time - time.time() + if timeout >= 1: + time.sleep(1) # We poll at 1 second granularity + else: + if timeout > 0: + time.sleep(timeout) + return True, change_event_dict + except Exception as e: + print(e) + print("get_change_event: Should not reach here.") + return False, change_event_dict + + def get_transceiver_change_event(self): + current_port_dict = {} + ret_dict = {} + + # Check for OIR events and return ret_dict + for index in range(self.platform_inventory['num_ports']): + if self._sfp_list[index].get_presence(): + #current_port_dict[index] = self.STATUS_INSERTED + current_port_dict[index] = self.plugin_data['XCVR']['plug_status']['inserted'] + else: + #current_port_dict[index] = self.STATUS_REMOVED + current_port_dict[index] = self.plugin_data['XCVR']['plug_status']['removed'] + + if len(self.port_dict) == 0: # first time + self.port_dict = current_port_dict + return {} + + if current_port_dict == self.port_dict: + return {} + + # Update reg value + for index, status in current_port_dict.items(): + if self.port_dict[index] != status: + ret_dict[index] = status + #ret_dict[str(index)] = status + self.port_dict = current_port_dict + for index, status in ret_dict.items(): + if int(status) == 1: + pass + #self._sfp_list[int(index)].check_sfp_optoe_type() + return ret_dict + + def get_reboot_cause(self): + """ + Retrieves the cause of the previous reboot + + Returns: + A tuple (string, string) where the first element is a string + containing the cause of the previous reboot. This string must be + one of the predefined strings in this class. If the first string + is "REBOOT_CAUSE_HARDWARE_OTHER", the second string can be used + to pass a description of the reboot cause. + """ + + reboot_cause_path = self.plugin_data['REBOOT_CAUSE']['reboot_cause_file'] + + try: + with open(reboot_cause_path, 'r', errors='replace') as fd: + data = fd.read() + sw_reboot_cause = data.strip() + except IOError: + sw_reboot_cause = "Unknown" + + return ('REBOOT_CAUSE_NON_HARDWARE', sw_reboot_cause) diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/sonic_platform/component.py b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/sonic_platform/component.py new file mode 100644 index 000000000000..1c583079f8c2 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/sonic_platform/component.py @@ -0,0 +1,125 @@ +############################################################################# +# +# Component contains an implementation of SONiC Platform Base API and +# provides the components firmware management function +# +############################################################################# + +try: + import subprocess + from sonic_platform_base.component_base import ComponentBase + from sonic_platform_pddf_base import pddfapi +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + +CPLD_SYSFS = { + "CPLD1": {"major": "cpld1_major_ver", "minor": "cpld1_minor_ver", "build": "cpld1_build"}, + "CPLD2": {"major": "cpld2_major_ver", "minor": "cpld2_minor_ver", "build": "cpld2_build"}, +} + +BMC_CMDS = { + "VER1": "ipmitool mc info | grep 'Firmware Revision' | cut -d':' -f2 | cut -d'.' -f1", + "VER2": "ipmitool mc info | grep 'Firmware Revision' | cut -d':' -f2 | cut -d'.' -f2", + "VER3": "echo $((`ipmitool mc info | grep 'Aux Firmware Rev Info' -A 2 | sed -n '2p'` + 0))", +} + +BIOS_VERSION_PATH = "/sys/class/dmi/id/bios_version" +COMPONENT_LIST= [ + ("CPLD1", "CPLD 1"), + ("CPLD2", "CPLD 2"), + ("BIOS", "Basic Input/Output System"), + ("BMC", "BMC"), +] + +class Component(ComponentBase): + """Platform-specific Component class""" + + DEVICE_TYPE = "component" + + def __init__(self, component_index=0): + self.pddf_obj = pddfapi.PddfApi() + self.index = component_index + self.name = self.get_name() + + def _get_bios_version(self): + # Retrieves the BIOS firmware version + try: + with open(BIOS_VERSION_PATH, 'r') as fd: + bios_version = fd.read() + return bios_version.strip() + except Exception as e: + return None + + def _get_cpld_version(self): + # Retrieves the CPLD firmware version + cpld_version = dict() + for cpld_name, elem in CPLD_SYSFS.items(): + device = "SYSSTATUS" + major = self.pddf_obj.get_attr_name_output(device, elem["major"]) + minor = self.pddf_obj.get_attr_name_output(device, elem["minor"]) + build = self.pddf_obj.get_attr_name_output(device, elem["build"]) + if major and minor and build: + major = int(major['status'].rstrip(),0) + minor = int(minor['status'].rstrip(),0) + build = int(build['status'].rstrip(),0) + cpld_version[cpld_name] = "{}.{:02d}.{:03d}".format(major, minor, build) + else: + cpld_version[cpld_name] = "N/A" + return cpld_version + + def _get_bmc_version(self): + # Retrieves the BMC firmware version + bmc_ver = dict() + for ver in BMC_CMDS: + status, value = subprocess.getstatusoutput(BMC_CMDS[ver]) + if not status: + bmc_ver[ver] = int(value.rstrip()) + else: + return None + + bmc_version = "{}.{}.{}".format(bmc_ver["VER1"], bmc_ver["VER2"], bmc_ver["VER3"]) + + return bmc_version + + def get_name(self): + """ + Retrieves the name of the component + Returns: + A string containing the name of the component + """ + return COMPONENT_LIST[self.index][0] + + def get_description(self): + """ + Retrieves the description of the component + Returns: + A string containing the description of the component + """ + return COMPONENT_LIST[self.index][1] + + def get_firmware_version(self): + """ + Retrieves the firmware version of module + Returns: + string: The firmware versions of the module + """ + fw_version = None + + if self.name == "BIOS": + fw_version = self._get_bios_version() + elif "CPLD" in self.name: + cpld_version = self._get_cpld_version() + fw_version = cpld_version.get(self.name) + elif self.name == "BMC": + fw_version = self._get_bmc_version() + return fw_version + + def install_firmware(self, image_path): + """ + Install firmware to module + Args: + image_path: A string, path to firmware image + Returns: + A boolean, True if install successfully, False if not + """ + raise NotImplementedError diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/sonic_platform/eeprom.py b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/sonic_platform/eeprom.py new file mode 100644 index 000000000000..90ab1c779a48 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/sonic_platform/eeprom.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python + +try: + from sonic_platform_pddf_base.pddf_eeprom import PddfEeprom +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + + +class Eeprom(PddfEeprom): + + def __init__(self, pddf_data=None, pddf_plugin_data=None): + PddfEeprom.__init__(self, pddf_data, pddf_plugin_data) + + # Provide the functions/variables below for which implementation is to be overwritten + + def platform_name_str(self): + (is_valid, results) = self.get_tlv_field(self.eeprom_data, self._TLV_CODE_PLATFORM_NAME) + if not is_valid: + return "N/A" + + return results[2].decode('ascii') \ No newline at end of file diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/sonic_platform/fan.py b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/sonic_platform/fan.py new file mode 100644 index 000000000000..c3cb875646b0 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/sonic_platform/fan.py @@ -0,0 +1,158 @@ +#!/usr/bin/env python + + +try: + from sonic_platform_pddf_base.pddf_fan import PddfFan +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + + +class Fan(PddfFan): + """PDDF Platform-Specific Fan class""" + + def __init__(self, tray_idx, fan_idx=0, pddf_data=None, pddf_plugin_data=None, is_psu_fan=False, psu_index=0): + # idx is 0-based + PddfFan.__init__(self, tray_idx, fan_idx, pddf_data, pddf_plugin_data, is_psu_fan, psu_index) + + # Provide the functions/variables below for which implementation is to be overwritten + # Since psu_fan airflow direction cant be read from sysfs, it is fixed as 'F2B' or 'intake' + + def get_mfr_id(self): + """ + Retrieves the manufacturer id of the device + + Returns: + string: Manufacturer Id of device + """ + if self.is_psu_fan: + device = "PSU{}".format(self.fans_psu_index) + output = self.pddf_obj.get_attr_name_output(device, "psu_mfr_id") + else: + raise NotImplementedError + + if not output: + return None + + mfr = output['status'] + + # strip_non_ascii + stripped = (c for c in mfr if 0 < ord(c) < 127) + mfr = ''.join(stripped) + + return mfr.rstrip('\n') + + def get_model(self): + """ + Retrieves the model number (or part number) of the device + + Returns: + string: Model/part number of device + """ + if self.is_psu_fan: + device = "PSU{}".format(self.fans_psu_index) + output = self.pddf_obj.get_attr_name_output(device, "psu_model_name") + else: + raise NotImplementedError + + if not output: + return None + + model = output['status'] + + # strip_non_ascii + stripped = (c for c in model if 0 < ord(c) < 127) + model = ''.join(stripped) + + return model.rstrip('\n') + + def get_max_speed(self): + """ + Retrieves the max speed + + Returns: + An Integer, the max speed + """ + if self.is_psu_fan: + mfr = self.get_mfr_id() + model = self.get_model() + + max_speed = int(self.plugin_data['PSU']['valmap']['PSU_FAN_MAX_SPEED_AC']) + if mfr and model : + for dev in self.plugin_data['PSU']['psu_support_list']: + if dev['Manufacturer'] == mfr and dev['Name'] == model: + max_speed = int(self.plugin_data['PSU']['valmap'][dev['MaxSpd']]) + break + else: + max_speed = int(self.plugin_data['FAN']['FAN_MAX_SPEED']) + + return max_speed + + def get_speed(self): + """ + Retrieves the speed of fan as a percentage of full speed + + Returns: + An integer, the percentage of full fan speed, in the range 0 (off) + to 100 (full speed) + """ + speed_percentage = 0 + + max_speed = self.get_max_speed() + rpm_speed = self.get_speed_rpm() + + speed_percentage = round((rpm_speed*100)/max_speed) + + return min(speed_percentage, 100) + + def get_presence(self): + """ + Retrieves the presence of the device + Returns: + bool: True if device is present, False if not + """ + if self.is_psu_fan: + attr_name = "psu_present" + device = "PSU{}".format(self.fans_psu_index) + else: + idx = (self.fantray_index-1)*self.platform['num_fans_pertray'] + self.fan_index + attr_name = "fan" + str(idx) + "_present" + device = "FAN-CTRL" + + output = self.pddf_obj.get_attr_name_output(device, attr_name) + if not output: + return False + + mode = output['mode'] + presence = output['status'].rstrip() + vmap = self.plugin_data['FAN']['present'][mode]['valmap'] + + if presence in vmap: + status = vmap[presence] + else: + status = False + + return status + + def get_target_speed(self): + """ + Retrieves the target (expected) speed of the fan + Returns: + An integer, the percentage of full fan speed, in the range 0 (off) + to 100 (full speed) + """ + return self.get_speed() + + def set_speed(self, speed): + """ + Sets the fan speed + + Args: + speed: An integer, the percentage of full fan speed to set fan to, + in the range 0 (off) to 100 (full speed) + + Returns: + A boolean, True if speed is set successfully, False if not + """ + + print("Setting Fan speed is not allowed") + return False diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/sonic_platform/fan_drawer.py b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/sonic_platform/fan_drawer.py new file mode 100644 index 000000000000..3b9bb607f632 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/sonic_platform/fan_drawer.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python + + +try: + from sonic_platform_pddf_base.pddf_fan_drawer import PddfFanDrawer +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + + +class FanDrawer(PddfFanDrawer): + """PDDF Platform-Specific Fan-Drawer class""" + + def __init__(self, tray_idx, pddf_data=None, pddf_plugin_data=None): + # idx is 0-based + PddfFanDrawer.__init__(self, tray_idx, pddf_data, pddf_plugin_data) + + # Provide the functions/variables below for which implementation is to be overwritten diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/sonic_platform/platform.py b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/sonic_platform/platform.py new file mode 100644 index 000000000000..406b1179ae1b --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/sonic_platform/platform.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python + +############################################################################# +# PDDF +# Module contains an implementation of SONiC Platform Base API and +# provides the platform information +# +############################################################################# + + +try: + from sonic_platform_pddf_base.pddf_platform import PddfPlatform +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + + +class Platform(PddfPlatform): + """ + PDDF Platform-Specific Platform Class + """ + + def __init__(self): + PddfPlatform.__init__(self) + + # Provide the functions/variables below for which implementation is to be overwritten diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/sonic_platform/psu.py b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/sonic_platform/psu.py new file mode 100644 index 000000000000..38b32412d024 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/sonic_platform/psu.py @@ -0,0 +1,38 @@ +#!/usr/bin/env python + + +try: + from sonic_platform_pddf_base.pddf_psu import PddfPsu +except ImportError as e: + raise ImportError (str(e) + "- required module not found") + + +class Psu(PddfPsu): + """PDDF Platform-Specific PSU class""" + + PLATFORM_PSU_CAPACITY = 450 + + def __init__(self, index, pddf_data=None, pddf_plugin_data=None): + PddfPsu.__init__(self, index, pddf_data, pddf_plugin_data) + + # Provide the functions/variables below for which implementation is to be overwritten + def get_maximum_supplied_power(self): + """ + Retrieves the maximum supplied power by PSU (or PSU capacity) + Returns: + A float number, the maximum power output in Watts. + e.g. 1200.1 + """ + return float(self.PLATFORM_PSU_CAPACITY) + + def get_power(self): + """ + Retrieves current energy supplied by PSU + + Returns: + A float number, the power in watts, + e.g. 302.6 + """ + + # power is returned in micro watts + return round(float(self.get_voltage()*self.get_current()), 2) diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/sonic_platform/sfp.py b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/sonic_platform/sfp.py new file mode 100644 index 000000000000..8ab43117d54c --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/sonic_platform/sfp.py @@ -0,0 +1,49 @@ +#!/usr/bin/env python + +try: + from sonic_platform_pddf_base.pddf_sfp import PddfSfp +except ImportError as e: + raise ImportError (str(e) + "- required module not found") + + +class Sfp(PddfSfp): + """ + PDDF Platform-Specific Sfp class + """ + + def __init__(self, index, pddf_data=None, pddf_plugin_data=None): + PddfSfp.__init__(self, index, pddf_data, pddf_plugin_data) + self.index = index + + # Provide the functions/variables below for which implementation is to be overwritten + + def get_lpmode(self): + if self.sfp_type == "QSFP28": + return super().get_lpmode() + else: + return False + + def set_lpmode(self, lpmode): + if self.sfp_type == "QSFP28": + return super().set_lpmode(lpmode) + else: + return False + + def reset(self): + if self.sfp_type == "QSFP28": + return super().reset() + else: + return False + + def get_error_description(self): + """ + Retrives the error descriptions of the SFP module + Returns: + String that represents the current error descriptions of vendor specific errors + In case there are multiple errors, they should be joined by '|', + like: "Bad EEPROM|Unsupported cable" + """ + if not self.get_presence(): + return self.SFP_STATUS_UNPLUGGED + + return self.SFP_STATUS_OK diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/sonic_platform/thermal.py b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/sonic_platform/thermal.py new file mode 100644 index 000000000000..77d6ec7ae886 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/sonic_platform/thermal.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python + + +try: + from sonic_platform_pddf_base.pddf_thermal import PddfThermal +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + + + +class Thermal(PddfThermal): + """PDDF Platform-Specific Thermal class""" + + def __init__(self, index, pddf_data=None, pddf_plugin_data=None, is_psu_thermal=False, psu_index=0): + PddfThermal.__init__(self, index, pddf_data, pddf_plugin_data, is_psu_thermal, psu_index) + + # Provide the functions/variables below for which implementation is to be overwritten diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/sonic_platform_setup.py b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/sonic_platform_setup.py new file mode 100644 index 000000000000..c0a485320cb7 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/sonic_platform_setup.py @@ -0,0 +1,27 @@ +from setuptools import setup + +setup( + name='sonic-platform', + version='1.0', + description='SONiC platform API implementation on ufispace platform', + license='Apache 2.0', + author='SONiC Team', + author_email='linuxnetdev@microsoft.com', + url='https://github.com/Azure/sonic-buildimage', + maintainer='Jason Tsai', + maintainer_email='jason.cy.tsai@ufispace.com', + packages=['sonic_platform'], + classifiers=[ + 'Development Status :: 3 - Alpha', + 'Environment :: Plugins', + 'Intended Audience :: Developers', + 'Intended Audience :: Information Technology', + 'Intended Audience :: System Administrators', + 'License :: OSI Approved :: Apache Software License', + 'Natural Language :: English', + 'Operating System :: POSIX :: Linux', + 'Programming Language :: Python :: 3.7', + 'Topic :: Utilities', + ], + keywords='sonic SONiC platform PLATFORM', +) diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/utils/pddf_post_device_create.sh b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/utils/pddf_post_device_create.sh new file mode 100755 index 000000000000..4a55252ea936 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/utils/pddf_post_device_create.sh @@ -0,0 +1,16 @@ +#!/bin/bash + +#disable bmc watchdog +echo "Disable BMC watchdog" +timeout 3 ipmitool mc watchdog off + +pddf_ledutil setstatusled SYNC_LED off +pddf_ledutil setstatusled SYS_LED off +pddf_ledutil setstatusled ID_LED off + +#set status led to green to indicate platform init done +curr_led=$(pddf_ledutil getstatusled SYS_LED) +pddf_ledutil setstatusled SYS_LED green +echo "Set SYS_LED from $curr_led to green" + +echo "PDDF device post-create completed" diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/utils/pddf_post_driver_install.sh b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/utils/pddf_post_driver_install.sh new file mode 100755 index 000000000000..ed2559977e42 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/utils/pddf_post_driver_install.sh @@ -0,0 +1,2 @@ +#!/bin/bash +echo "PDDF driver post-install completed" diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/utils/pddf_pre_driver_install.sh b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/utils/pddf_pre_driver_install.sh new file mode 100755 index 000000000000..9ada6c235c48 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/utils/pddf_pre_driver_install.sh @@ -0,0 +1,8 @@ +#!/bin/bash +#rmmod gpio_ich +if [ ! -f /tmp/._pddf_pre_driver_init_completion ]; then + rmmod i2c_i801 + rmmod i2c_ismt + date > /tmp/._pddf_pre_driver_init_completion +fi +echo "PDDF driver pre-install completed" diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/utils/pddf_switch_svc.py b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/utils/pddf_switch_svc.py new file mode 100755 index 000000000000..ca34fe9442c9 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/utils/pddf_switch_svc.py @@ -0,0 +1,50 @@ +#!/usr/bin/env python +# Script to stop and start the respective platforms default services. +# This will be used while switching the pddf->non-pddf mode and vice versa +import commands + +def check_pddf_support(): + return True + +def stop_platform_svc(): + + status, output = commands.getstatusoutput("/usr/local/bin/platform_utility.py deinit") + if status: + print "platform_utility.py deinit command failed %d"%status + return False + + # HACK , stop the pddf-platform-init service if it is active + status, output = commands.getstatusoutput("systemctl stop pddf-platform-init.service") + if status: + print "Stop pddf-platform-init.service along with other platform serives failed %d"%status + return False + + return True + +def start_platform_svc(): + + status, output = commands.getstatusoutput("/usr/local/bin/platform_utility.py init") + if status: + print "platform_utility.py init command failed %d"%status + return False + + return True + +def start_platform_pddf(): + + status, output = commands.getstatusoutput("systemctl start pddf-platform-init.service") + if status: + print "Start pddf-platform-init.service failed %d"%status + return False + + return True + +def stop_platform_pddf(): + + status, output = commands.getstatusoutput("systemctl stop pddf-platform-init.service") + if status: + print "Stop pddf-platform-init.service failed %d"%status + return False + + return True + diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/utils/pre_pddf_init.sh b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/utils/pre_pddf_init.sh new file mode 100755 index 000000000000..63a2e205808e --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s8901-54xc/utils/pre_pddf_init.sh @@ -0,0 +1,5 @@ +#!/bin/bash +#rmmod gpio_ich +modprobe -rq i2c_i801 +modprobe -rq i2c_smbus +echo "Pre PDDF init steps completed successully" diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/modules/Makefile b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/modules/Makefile new file mode 100644 index 000000000000..93d0f3e46fdb --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/modules/Makefile @@ -0,0 +1,6 @@ + +MODULE_NAME = x86-64-ufispace-s9110-32x-cpld.o x86-64-ufispace-s9110-32x-sys-eeprom.o x86-64-ufispace-s9110-32x-lpc.o pddf_custom_sysstatus_module.o +obj-m := $(MODULE_NAME) + +CFLAGS_pddf_custom_sysstatus_module.o := -I$(M)/../../../../pddf/i2c/modules/include +KBUILD_EXTRA_SYMBOLS := $(M)/../../../../pddf/i2c/Module.symvers.PDDF diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/modules/pddf_custom_sysstatus_module.c b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/modules/pddf_custom_sysstatus_module.c new file mode 100644 index 000000000000..35a032f4277e --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/modules/pddf_custom_sysstatus_module.c @@ -0,0 +1,274 @@ +/* + * Copyright 2019 Broadcom. + * The term ��Broadcom�� refers to Broadcom Inc. and/or its subsidiaries. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * + * A pddf kernel module for system status registers + */ + +#define __STDC_WANT_LIB_EXT1__ 1 +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../../../../pddf/i2c/modules/include/pddf_client_defs.h" +#include "../../../../pddf/i2c/modules/include/pddf_sysstatus_defs.h" + + +SYSSTATUS_DATA sysstatus_data = {0}; + +extern int board_i2c_cpld_read(unsigned short cpld_addr, u8 reg); +extern int board_i2c_cpld_write(unsigned short cpld_addr, u8 reg, u8 value); + +static ssize_t do_attr_operation(struct device *dev, struct device_attribute *da, const char *buf, size_t count); +ssize_t show_sysstatus_data(struct device *dev, struct device_attribute *da, char *buf); +ssize_t store_sysstatus_data(struct device *dev, struct device_attribute *da, const char *buf, size_t count); + + +PDDF_DATA_ATTR(attr_name, S_IWUSR|S_IRUGO, show_pddf_data, store_pddf_data, PDDF_CHAR, 32, + (void*)&sysstatus_data.sysstatus_addr_attr.aname, NULL); +PDDF_DATA_ATTR(attr_devaddr, S_IWUSR|S_IRUGO, show_pddf_data, store_pddf_data, PDDF_UINT32, + sizeof(uint32_t), (void*)&sysstatus_data.sysstatus_addr_attr.devaddr , NULL); +PDDF_DATA_ATTR(attr_offset, S_IWUSR|S_IRUGO, show_pddf_data, store_pddf_data, PDDF_UINT32, + sizeof(uint32_t), (void*)&sysstatus_data.sysstatus_addr_attr.offset, NULL); +PDDF_DATA_ATTR(attr_mask, S_IWUSR|S_IRUGO, show_pddf_data, store_pddf_data, PDDF_UINT32, + sizeof(uint32_t), (void*)&sysstatus_data.sysstatus_addr_attr.mask , NULL); +PDDF_DATA_ATTR(attr_len, S_IWUSR|S_IRUGO, show_pddf_data, store_pddf_data, PDDF_UINT32, + sizeof(uint32_t), (void*)&sysstatus_data.sysstatus_addr_attr.len , NULL); +PDDF_DATA_ATTR(attr_ops, S_IWUSR, NULL, do_attr_operation, PDDF_CHAR, 8, (void*)&sysstatus_data, NULL); + + + +static struct attribute *sysstatus_addr_attributes[] = { + &attr_attr_name.dev_attr.attr, + &attr_attr_devaddr.dev_attr.attr, + &attr_attr_offset.dev_attr.attr, + &attr_attr_mask.dev_attr.attr, + &attr_attr_len.dev_attr.attr, + &attr_attr_ops.dev_attr.attr, + NULL +}; + +PDDF_DATA_ATTR(board_sku_id , S_IRUGO, show_sysstatus_data, NULL, PDDF_UCHAR, sizeof(u8), NULL, NULL); +PDDF_DATA_ATTR(board_hw_id , S_IRUGO, show_sysstatus_data, NULL, PDDF_UCHAR, sizeof(u8), NULL, NULL); +PDDF_DATA_ATTR(board_deph_id , S_IRUGO, show_sysstatus_data, NULL, PDDF_UCHAR, sizeof(u8), NULL, NULL); +PDDF_DATA_ATTR(board_build_id , S_IRUGO, show_sysstatus_data, NULL, PDDF_UCHAR, sizeof(u8), NULL, NULL); +PDDF_DATA_ATTR(cpld1_major_ver, S_IRUGO, show_sysstatus_data, NULL, PDDF_UCHAR, sizeof(u8), NULL, NULL); +PDDF_DATA_ATTR(cpld1_minor_ver, S_IRUGO, show_sysstatus_data, NULL, PDDF_UCHAR, sizeof(u8), NULL, NULL); +PDDF_DATA_ATTR(cpld1_build , S_IRUGO, show_sysstatus_data, NULL, PDDF_UCHAR, sizeof(u8), NULL, NULL); +PDDF_DATA_ATTR(cpld2_major_ver, S_IRUGO, show_sysstatus_data, NULL, PDDF_UCHAR, sizeof(u8), NULL, NULL); +PDDF_DATA_ATTR(cpld2_minor_ver, S_IRUGO, show_sysstatus_data, NULL, PDDF_UCHAR, sizeof(u8), NULL, NULL); +PDDF_DATA_ATTR(cpld2_build , S_IRUGO, show_sysstatus_data, NULL, PDDF_UCHAR, sizeof(u8), NULL, NULL); +PDDF_DATA_ATTR(psu_status , S_IRUGO, show_sysstatus_data, NULL, PDDF_UCHAR, sizeof(u8), NULL, NULL); +PDDF_DATA_ATTR(system_led_psu , S_IRUGO, show_sysstatus_data, NULL, PDDF_UCHAR, sizeof(u8), NULL, NULL); +PDDF_DATA_ATTR(system_led_sys , S_IWUSR|S_IRUGO, show_sysstatus_data, store_sysstatus_data, PDDF_UCHAR, sizeof(u8), NULL, NULL); +PDDF_DATA_ATTR(system_led_fan , S_IRUGO, show_sysstatus_data, NULL, PDDF_UCHAR, sizeof(u8), NULL, NULL); +PDDF_DATA_ATTR(system_led_id , S_IWUSR|S_IRUGO, show_sysstatus_data, store_sysstatus_data, PDDF_UCHAR, sizeof(u8), NULL, NULL); + +static struct attribute *sysstatus_data_attributes[] = { + &attr_board_sku_id.dev_attr.attr, + &attr_board_hw_id.dev_attr.attr, + &attr_board_deph_id.dev_attr.attr, + &attr_board_build_id.dev_attr.attr, + &attr_cpld1_major_ver.dev_attr.attr, + &attr_cpld1_minor_ver.dev_attr.attr, + &attr_cpld1_build.dev_attr.attr, + &attr_cpld2_major_ver.dev_attr.attr, + &attr_cpld2_minor_ver.dev_attr.attr, + &attr_cpld2_build.dev_attr.attr, + &attr_psu_status.dev_attr.attr, + &attr_system_led_psu.dev_attr.attr, + &attr_system_led_sys.dev_attr.attr, + &attr_system_led_fan.dev_attr.attr, + &attr_system_led_id.dev_attr.attr, + NULL +}; + + +static const struct attribute_group pddf_sysstatus_addr_group = { + .attrs = sysstatus_addr_attributes, +}; + + +static const struct attribute_group pddf_sysstatus_data_group = { + .attrs = sysstatus_data_attributes, +}; + + +static struct kobject *sysstatus_addr_kobj; +static struct kobject *sysstatus_data_kobj; + + + +ssize_t show_sysstatus_data(struct device *dev, struct device_attribute *da, char *buf) +{ + + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + + SYSSTATUS_DATA *data = &sysstatus_data; + struct SYSSTATUS_ADDR_ATTR *sysstatus_addr_attrs = NULL; + int i, status ; + + + for (i=0;isysstatus_addr_attrs[i].aname, attr->dev_attr.attr.name) == 0 ) + { + sysstatus_addr_attrs = &data->sysstatus_addr_attrs[i]; + + } + } + + if (sysstatus_addr_attrs==NULL ) + { + printk(KERN_DEBUG "%s is not supported attribute for this client\n",data->sysstatus_addr_attrs[i].aname); + status = 0; + } + else + { + status = board_i2c_cpld_read( sysstatus_addr_attrs->devaddr, sysstatus_addr_attrs->offset); + } + + return sprintf(buf, "0x%x\n", (status&sysstatus_addr_attrs->mask)); + +} + +ssize_t store_sysstatus_data(struct device *dev, struct device_attribute *da, const char *buf, size_t count) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + + SYSSTATUS_DATA *data = &sysstatus_data; + struct SYSSTATUS_ADDR_ATTR *sysstatus_addr_attrs = NULL; + int i, status ; + u8 reg_val; + + for (i=0;isysstatus_addr_attrs[i].aname, attr->dev_attr.attr.name) == 0 ) + { + sysstatus_addr_attrs = &data->sysstatus_addr_attrs[i]; + } + } + + if (sysstatus_addr_attrs==NULL) + { + printk(KERN_DEBUG "%s is not supported attribute for this client\n",data->sysstatus_addr_attrs[i].aname); + return -EINVAL; + } + else + { + if (kstrtou8(buf, 0, ®_val) < 0) + return -EINVAL; + + status = board_i2c_cpld_write(sysstatus_addr_attrs->devaddr, sysstatus_addr_attrs->offset, reg_val); + + if (status!=0) + { + printk(KERN_DEBUG "store_sysstatus_data() %s failed, status=%d\n",data->sysstatus_addr_attrs[i].aname, status); + return status; + } + } + + return count; +} + + + +static ssize_t do_attr_operation(struct device *dev, struct device_attribute *da, const char *buf, size_t count) +{ + PDDF_ATTR *ptr = (PDDF_ATTR *)da; + SYSSTATUS_DATA *pdata = (SYSSTATUS_DATA *)(ptr->addr); + + pdata->sysstatus_addr_attrs[pdata->len] = pdata->sysstatus_addr_attr; + pdata->len++; + pddf_dbg(SYSSTATUS, KERN_ERR "%s: Populating the data for %s\n", __FUNCTION__, pdata->sysstatus_addr_attr.aname); + +#ifdef __STDC_LIB_EXT1__ + memset_s(&pdata->sysstatus_addr_attr, sizeof(pdata->sysstatus_addr_attr, 0, sizeof(pdata->sysstatus_addr_attr)); +#else + memset(&pdata->sysstatus_addr_attr, 0, sizeof(pdata->sysstatus_addr_attr)); +#endif + + return count; +} + + + + +int __init sysstatus_data_init(void) +{ + struct kobject *device_kobj; + int ret = 0; + + + pddf_dbg(SYSSTATUS, "PDDF SYSSTATUS MODULE.. init\n"); + + device_kobj = get_device_i2c_kobj(); + if(!device_kobj) + return -ENOMEM; + + sysstatus_addr_kobj = kobject_create_and_add("sysstatus", device_kobj); + if(!sysstatus_addr_kobj) + return -ENOMEM; + + sysstatus_data_kobj = kobject_create_and_add("sysstatus_data", sysstatus_addr_kobj); + if(!sysstatus_data_kobj) + return -ENOMEM; + + + ret = sysfs_create_group(sysstatus_addr_kobj, &pddf_sysstatus_addr_group); + if (ret) + { + kobject_put(sysstatus_addr_kobj); + return ret; + } + + ret = sysfs_create_group(sysstatus_data_kobj, &pddf_sysstatus_data_group); + if (ret) + { + sysfs_remove_group(sysstatus_addr_kobj, &pddf_sysstatus_addr_group); + kobject_put(sysstatus_data_kobj); + kobject_put(sysstatus_addr_kobj); + return ret; + } + + + return ret; +} + +void __exit sysstatus_data_exit(void) +{ + pddf_dbg(SYSSTATUS, "PDDF SYSSTATUS MODULE.. exit\n"); + sysfs_remove_group(sysstatus_data_kobj, &pddf_sysstatus_data_group); + sysfs_remove_group(sysstatus_addr_kobj, &pddf_sysstatus_addr_group); + kobject_put(sysstatus_data_kobj); + kobject_put(sysstatus_addr_kobj); + pddf_dbg(SYSSTATUS, KERN_ERR "%s: Removed the kobjects for 'SYSSTATUS'\n",__FUNCTION__); + return; +} + +module_init(sysstatus_data_init); +module_exit(sysstatus_data_exit); + +MODULE_AUTHOR("Broadcom"); +MODULE_DESCRIPTION("SYSSTATUS platform data"); +MODULE_LICENSE("GPL"); diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/modules/x86-64-ufispace-s9110-32x-cpld.c b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/modules/x86-64-ufispace-s9110-32x-cpld.c new file mode 100644 index 000000000000..af54108ee1b3 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/modules/x86-64-ufispace-s9110-32x-cpld.c @@ -0,0 +1,1475 @@ +/* + * A i2c cpld driver for the ufispace_s9110_32x + * + * Copyright (C) 2022 UfiSpace Technology Corporation. + * Nonodark Huang + * + * Based on ad7414.c + * Copyright 2006 Stefan Roese , DENX Software Engineering + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "x86-64-ufispace-s9110-32x-cpld.h" + +#if !defined(SENSOR_DEVICE_ATTR_RO) +#define SENSOR_DEVICE_ATTR_RO(_name, _func, _index) \ + SENSOR_DEVICE_ATTR(_name, 0444, _func##_show, NULL, _index) +#endif + +#if !defined(SENSOR_DEVICE_ATTR_RW) +#define SENSOR_DEVICE_ATTR_RW(_name, _func, _index) \ + SENSOR_DEVICE_ATTR(_name, 0644, _func##_show, _func##_store, _index) + +#endif + +#if !defined(SENSOR_DEVICE_ATTR_WO) +#define SENSOR_DEVICE_ATTR_WO(_name, _func, _index) \ + SENSOR_DEVICE_ATTR(_name, 0200, NULL, _func##_store, _index) +#endif + + +#ifdef DEBUG +#define DEBUG_PRINT(fmt, args...) \ + printk(KERN_INFO "%s:%s[%d]: " fmt "\r\n", \ + __FILE__, __func__, __LINE__, ##args) +#else +#define DEBUG_PRINT(fmt, args...) +#endif + +#define BSP_LOG_R(fmt, args...) \ + _bsp_log (LOG_READ, KERN_INFO "%s:%s[%d]: " fmt "\r\n", \ + __FILE__, __func__, __LINE__, ##args) +#define BSP_LOG_W(fmt, args...) \ + _bsp_log (LOG_WRITE, KERN_INFO "%s:%s[%d]: " fmt "\r\n", \ + __FILE__, __func__, __LINE__, ##args) + +#define I2C_READ_BYTE_DATA(ret, lock, i2c_client, reg) \ +{ \ + mutex_lock(lock); \ + ret = i2c_smbus_read_byte_data(i2c_client, reg); \ + mutex_unlock(lock); \ + BSP_LOG_R("cpld[%d], reg=0x%03x, reg_val=0x%02x", data->index, reg, ret); \ +} + +#define I2C_WRITE_BYTE_DATA(ret, lock, i2c_client, reg, val) \ +{ \ + mutex_lock(lock); \ + ret = i2c_smbus_write_byte_data(i2c_client, reg, val); \ + mutex_unlock(lock); \ + BSP_LOG_W("cpld[%d], reg=0x%03x, reg_val=0x%02x", data->index, reg, val); \ +} + +#define _DEVICE_ATTR(_name) \ + &sensor_dev_attr_##_name.dev_attr.attr + + +/* CPLD sysfs attributes index */ +enum cpld_sysfs_attributes { + //CPLD 1 & CPLD 2 + CPLD_MAJOR_VER, + CPLD_MINOR_VER, + CPLD_ID, + CPLD_BUILD, + CPLD_VERSION_H, + CPLD_CHIP, + CPLD_EVT_CTRL, + + //CPLD 1 + CPLD_BOARD_ID_0, + CPLD_BOARD_ID_1, + CPLD_SKU_EXT, + + CPLD_MAC_INTR, + CPLD_HWM_INTR, + CPLD_CPLD2_INTR, + CPLD_PTP_INTR, + CPLD_SYSTEM_INTR, + + CPLD_MAC_MASK, + CPLD_HWM_MASK, + CPLD_CPLD2_MASK, + CPLD_PTP_MASK, + CPLD_SYSTEM_MASK, + + CPLD_MAC_EVT, + CPLD_HWM_EVT, + CPLD_CPLD2_EVT, + + CPLD_MAC_RESET, + CPLD_SYSTEM_RESET, + CPLD_BMC_NTM_RESET, + CPLD_USB_RESET, + CPLD_I2C_MUX_RESET, + CPLD_MISC_RESET, + + CPLD_BRD_PRESENT, + CPLD_PSU_STATUS, + CPLD_SYSTEM_PWR, + CPLD_MAC_SYNCE, + CPLD_MAC_AVS, + CPLD_SYSTEM_STATUS, + CPLD_WATCHDOG, + CPLD_BOOT_SELECT, + CPLD_MUX_CTRL, + CPLD_MISC_CTRL_1, + CPLD_MISC_CTRL_2, + CPLD_MAC_TEMP, + + CPLD_SYSTEM_LED_PSU, + CPLD_SYSTEM_LED_SYS, + CPLD_SYSTEM_LED_FAN, + CPLD_SYSTEM_LED_ID, + + DBG_CPLD_MAC_INTR, + DBG_CPLD_HWM_INTR, + DBG_CPLD_CPLD2_INTR, + DBG_CPLD_PTP_INTR, + + //CPLD 2 + CPLD_QSFP_ABS_0_7, + CPLD_QSFP_ABS_8_15, + CPLD_QSFP_ABS_16_23, + CPLD_QSFP_ABS_24_31, + + CPLD_QSFP_INTR_0_7, + CPLD_QSFP_INTR_8_15, + CPLD_QSFP_INTR_16_23, + CPLD_QSFP_INTR_24_31, + + CPLD_SFP_ABS_0_1, + CPLD_SFP_RXLOS_0_1, + CPLD_SFP_TXFLT_0_1, + + CPLD_QSFP_MASK_ABS_0_7, + CPLD_QSFP_MASK_ABS_8_15, + CPLD_QSFP_MASK_ABS_16_23, + CPLD_QSFP_MASK_ABS_24_31, + + CPLD_QSFP_MASK_INTR_0_7, + CPLD_QSFP_MASK_INTR_8_15, + CPLD_QSFP_MASK_INTR_16_23, + CPLD_QSFP_MASK_INTR_24_31, + + CPLD_SFP_MASK_ABS_0_1, + CPLD_SFP_MASK_RXLOS_0_1, + CPLD_SFP_MASK_TXFLT_0_1, + + CPLD_QSFP_EVT_ABS_0_7, + CPLD_QSFP_EVT_ABS_8_15, + CPLD_QSFP_EVT_ABS_16_23, + CPLD_QSFP_EVT_ABS_24_31, + + CPLD_QSFP_EVT_INTR_0_7, + CPLD_QSFP_EVT_INTR_8_15, + CPLD_QSFP_EVT_INTR_16_23, + CPLD_QSFP_EVT_INTR_24_31, + + CPLD_SFP_EVT_ABS_0_1, + CPLD_SFP_EVT_RXLOS_0_1, + CPLD_SFP_EVT_TXFLT_0_1, + + CPLD_QSFP_RESET_0_7, + CPLD_QSFP_RESET_8_15, + CPLD_QSFP_RESET_16_23, + CPLD_QSFP_RESET_24_31, + + CPLD_QSFP_LPMODE_0_7, + CPLD_QSFP_LPMODE_8_15, + CPLD_QSFP_LPMODE_16_23, + CPLD_QSFP_LPMODE_24_31, + + CPLD_SFP_TXDIS_0_1, + CPLD_SFP_TS_0_1, + CPLD_SFP_RS_0_1, + + DBG_CPLD_QSFP_ABS_0_7, + DBG_CPLD_QSFP_ABS_8_15, + DBG_CPLD_QSFP_ABS_16_23, + DBG_CPLD_QSFP_ABS_24_31, + + DBG_CPLD_QSFP_INTR_0_7, + DBG_CPLD_QSFP_INTR_8_15, + DBG_CPLD_QSFP_INTR_16_23, + DBG_CPLD_QSFP_INTR_24_31, + + DBG_CPLD_SFP_ABS_0_1, + DBG_CPLD_SFP_RXLOS_0_1, + DBG_CPLD_SFP_TXFLT_0_1, + + //BSP DEBUG + BSP_DEBUG +}; + +enum data_type { + DATA_HEX, + DATA_DEC, + DATA_UNK, +}; + +typedef struct { + u8 reg; + u8 mask; + u8 data_type; +} attr_reg_map_t; + +static attr_reg_map_t attr_reg[]= { + + //CPLD 1 & CPLD 2 + [CPLD_MAJOR_VER] = {CPLD_VERSION_REG , MASK_1100_0000, DATA_DEC}, + [CPLD_MINOR_VER] = {CPLD_VERSION_REG , MASK_0011_1111, DATA_DEC}, + [CPLD_ID] = {CPLD_ID_REG , MASK_0000_0111, DATA_DEC}, + [CPLD_BUILD] = {CPLD_BUILD_REG , MASK_ALL , DATA_DEC}, + [CPLD_VERSION_H] = {CPLD_NONE_REG , MASK_NONE , DATA_UNK}, + [CPLD_CHIP] = {CPLD_CHIP_REG , MASK_ALL , DATA_HEX}, + [CPLD_EVT_CTRL] = {CPLD_EVT_CTRL_REG , MASK_ALL , DATA_HEX}, + + //CPLD 1 + [CPLD_BOARD_ID_0] = {CPLD_BOARD_ID_0_REG , MASK_ALL , DATA_HEX}, + [CPLD_BOARD_ID_1] = {CPLD_BOARD_ID_1_REG , MASK_ALL , DATA_HEX}, + [CPLD_SKU_EXT] = {CPLD_SKU_EXT_REG , MASK_ALL , DATA_DEC}, + + [CPLD_MAC_INTR] = {CPLD_MAC_INTR_REG , MASK_ALL , DATA_HEX}, + [CPLD_HWM_INTR] = {CPLD_HWM_INTR_REG , MASK_ALL , DATA_HEX}, + [CPLD_CPLD2_INTR] = {CPLD_CPLD2_INTR_REG , MASK_ALL , DATA_HEX}, + [CPLD_PTP_INTR] = {CPLD_PTP_INTR_REG , MASK_ALL , DATA_HEX}, + [CPLD_SYSTEM_INTR] = {CPLD_SYSTEM_INTR_REG , MASK_ALL , DATA_HEX}, + + [CPLD_MAC_MASK] = {CPLD_MAC_MASK_REG , MASK_ALL , DATA_HEX}, + [CPLD_HWM_MASK] = {CPLD_HWM_MASK_REG , MASK_ALL , DATA_HEX}, + [CPLD_CPLD2_MASK] = {CPLD_CPLD2_MASK_REG , MASK_ALL , DATA_HEX}, + [CPLD_PTP_MASK] = {CPLD_PTP_MASK_REG , MASK_ALL , DATA_HEX}, + [CPLD_SYSTEM_MASK] = {CPLD_SYSTEM_MASK_REG , MASK_ALL , DATA_HEX}, + + [CPLD_MAC_EVT] = {CPLD_MAC_EVT_REG , MASK_ALL , DATA_HEX}, + [CPLD_HWM_EVT] = {CPLD_HWM_EVT_REG , MASK_ALL , DATA_HEX}, + [CPLD_CPLD2_EVT] = {CPLD_CPLD2_EVT_REG , MASK_ALL , DATA_HEX}, + + [CPLD_MAC_RESET] = {CPLD_MAC_RESET_REG , MASK_ALL , DATA_HEX}, + [CPLD_SYSTEM_RESET] = {CPLD_SYSTEM_RESET_REG , MASK_ALL , DATA_HEX}, + [CPLD_BMC_NTM_RESET] = {CPLD_BMC_NTM_RESET_REG , MASK_ALL , DATA_HEX}, + [CPLD_USB_RESET] = {CPLD_USB_RESET_REG , MASK_ALL , DATA_HEX}, + [CPLD_I2C_MUX_RESET] = {CPLD_I2C_MUX_RESET_REG , MASK_ALL , DATA_HEX}, + [CPLD_MISC_RESET] = {CPLD_MISC_RESET_REG , MASK_ALL , DATA_HEX}, + + [CPLD_BRD_PRESENT] = {CPLD_BRD_PRESENT_REG , MASK_ALL , DATA_HEX}, + [CPLD_PSU_STATUS] = {CPLD_PSU_STATUS_REG , MASK_ALL , DATA_HEX}, + [CPLD_SYSTEM_PWR] = {CPLD_SYSTEM_PWR_REG , MASK_ALL , DATA_HEX}, + [CPLD_MAC_SYNCE] = {CPLD_MAC_SYNCE_REG , MASK_ALL , DATA_HEX}, + [CPLD_MAC_AVS] = {CPLD_MAC_AVS_REG , MASK_ALL , DATA_HEX}, + [CPLD_SYSTEM_STATUS] = {CPLD_SYSTEM_STATUS_REG , MASK_ALL , DATA_HEX}, + [CPLD_WATCHDOG] = {CPLD_WATCHDOG_REG , MASK_ALL , DATA_HEX}, + [CPLD_BOOT_SELECT] = {CPLD_BOOT_SELECT_REG , MASK_ALL , DATA_HEX}, + [CPLD_MUX_CTRL] = {CPLD_MUX_CTRL_REG , MASK_ALL , DATA_HEX}, + [CPLD_MISC_CTRL_1] = {CPLD_MISC_CTRL_1_REG , MASK_ALL , DATA_HEX}, + [CPLD_MISC_CTRL_2] = {CPLD_MISC_CTRL_2_REG , MASK_ALL , DATA_HEX}, + [CPLD_MAC_TEMP] = {CPLD_MAC_TEMP_REG , MASK_ALL , DATA_HEX}, + + [CPLD_SYSTEM_LED_PSU] = {CPLD_SYSTEM_LED_PSU_REG , MASK_ALL , DATA_HEX}, + [CPLD_SYSTEM_LED_SYS] = {CPLD_SYSTEM_LED_SYS_REG , MASK_ALL , DATA_HEX}, + [CPLD_SYSTEM_LED_FAN] = {CPLD_SYSTEM_LED_FAN_REG , MASK_ALL , DATA_HEX}, + [CPLD_SYSTEM_LED_ID] = {CPLD_SYSTEM_LED_ID_REG , MASK_ALL , DATA_HEX}, + + [DBG_CPLD_MAC_INTR] = {DBG_CPLD_MAC_INTR_REG , MASK_ALL , DATA_HEX}, + [DBG_CPLD_HWM_INTR] = {DBG_CPLD_HWM_INTR_REG , MASK_ALL , DATA_HEX}, + [DBG_CPLD_CPLD2_INTR] = {DBG_CPLD_CPLD2_INTR_REG , MASK_ALL , DATA_HEX}, + [DBG_CPLD_PTP_INTR] = {DBG_CPLD_PTP_INTR_REG , MASK_ALL , DATA_HEX}, + + //CPLD 2 + [CPLD_QSFP_ABS_0_7] = {CPLD_QSFP_ABS_0_7_REG , MASK_ALL , DATA_HEX}, + [CPLD_QSFP_ABS_8_15] = {CPLD_QSFP_ABS_8_15_REG , MASK_ALL , DATA_HEX}, + [CPLD_QSFP_ABS_16_23] = {CPLD_QSFP_ABS_16_23_REG , MASK_ALL , DATA_HEX}, + [CPLD_QSFP_ABS_24_31] = {CPLD_QSFP_ABS_24_31_REG , MASK_ALL , DATA_HEX}, + + [CPLD_QSFP_INTR_0_7] = {CPLD_QSFP_INTR_0_7_REG , MASK_ALL , DATA_HEX}, + [CPLD_QSFP_INTR_8_15] = {CPLD_QSFP_INTR_8_15_REG , MASK_ALL , DATA_HEX}, + [CPLD_QSFP_INTR_16_23] = {CPLD_QSFP_INTR_16_23_REG , MASK_ALL , DATA_HEX}, + [CPLD_QSFP_INTR_24_31] = {CPLD_QSFP_INTR_24_31_REG , MASK_ALL , DATA_HEX}, + + [CPLD_SFP_ABS_0_1] = {CPLD_SFP_ABS_0_1_REG , MASK_ALL , DATA_HEX}, + [CPLD_SFP_RXLOS_0_1] = {CPLD_SFP_RXLOS_0_1_REG , MASK_ALL , DATA_HEX}, + [CPLD_SFP_TXFLT_0_1] = {CPLD_SFP_TXFLT_0_1_REG , MASK_ALL , DATA_HEX}, + + [CPLD_QSFP_MASK_ABS_0_7] = {CPLD_QSFP_MASK_ABS_0_7_REG , MASK_ALL , DATA_HEX}, + [CPLD_QSFP_MASK_ABS_8_15] = {CPLD_QSFP_MASK_ABS_8_15_REG , MASK_ALL , DATA_HEX}, + [CPLD_QSFP_MASK_ABS_16_23] = {CPLD_QSFP_MASK_ABS_16_23_REG , MASK_ALL , DATA_HEX}, + [CPLD_QSFP_MASK_ABS_24_31] = {CPLD_QSFP_MASK_ABS_24_31_REG , MASK_ALL , DATA_HEX}, + + [CPLD_QSFP_MASK_INTR_0_7] = {CPLD_QSFP_MASK_INTR_0_7_REG , MASK_ALL , DATA_HEX}, + [CPLD_QSFP_MASK_INTR_8_15] = {CPLD_QSFP_MASK_INTR_8_15_REG , MASK_ALL , DATA_HEX}, + [CPLD_QSFP_MASK_INTR_16_23]= {CPLD_QSFP_MASK_INTR_16_23_REG , MASK_ALL , DATA_HEX}, + [CPLD_QSFP_MASK_INTR_24_31]= {CPLD_QSFP_MASK_INTR_24_31_REG , MASK_ALL , DATA_HEX}, + + [CPLD_SFP_MASK_ABS_0_1] = {CPLD_SFP_MASK_ABS_0_1_REG , MASK_ALL , DATA_HEX}, + [CPLD_SFP_MASK_RXLOS_0_1] = {CPLD_SFP_MASK_RXLOS_0_1_REG , MASK_ALL , DATA_HEX}, + [CPLD_SFP_MASK_TXFLT_0_1] = {CPLD_SFP_MASK_TXFLT_0_1_REG , MASK_ALL , DATA_HEX}, + + [CPLD_QSFP_EVT_ABS_0_7] = {CPLD_QSFP_EVT_ABS_0_7_REG , MASK_ALL , DATA_HEX}, + [CPLD_QSFP_EVT_ABS_8_15] = {CPLD_QSFP_EVT_ABS_8_15_REG , MASK_ALL , DATA_HEX}, + [CPLD_QSFP_EVT_ABS_16_23] = {CPLD_QSFP_EVT_ABS_16_23_REG , MASK_ALL , DATA_HEX}, + [CPLD_QSFP_EVT_ABS_24_31] = {CPLD_QSFP_EVT_ABS_24_31_REG , MASK_ALL , DATA_HEX}, + + [CPLD_QSFP_EVT_INTR_0_7] = {CPLD_QSFP_EVT_INTR_0_7_REG , MASK_ALL , DATA_HEX}, + [CPLD_QSFP_EVT_INTR_8_15] = {CPLD_QSFP_EVT_INTR_8_15_REG , MASK_ALL , DATA_HEX}, + [CPLD_QSFP_EVT_INTR_16_23] = {CPLD_QSFP_EVT_INTR_16_23_REG , MASK_ALL , DATA_HEX}, + [CPLD_QSFP_EVT_INTR_24_31] = {CPLD_QSFP_EVT_INTR_24_31_REG , MASK_ALL , DATA_HEX}, + + [CPLD_SFP_EVT_ABS_0_1] = {CPLD_SFP_EVT_ABS_0_1_REG , MASK_ALL , DATA_HEX}, + [CPLD_SFP_EVT_RXLOS_0_1] = {CPLD_SFP_EVT_RXLOS_0_1_REG , MASK_ALL , DATA_HEX}, + [CPLD_SFP_EVT_TXFLT_0_1] = {CPLD_SFP_EVT_TXFLT_0_1_REG , MASK_ALL , DATA_HEX}, + + [CPLD_QSFP_RESET_0_7] = {CPLD_QSFP_RESET_0_7_REG , MASK_ALL , DATA_HEX}, + [CPLD_QSFP_RESET_8_15] = {CPLD_QSFP_RESET_8_15_REG , MASK_ALL , DATA_HEX}, + [CPLD_QSFP_RESET_16_23] = {CPLD_QSFP_RESET_16_23_REG , MASK_ALL , DATA_HEX}, + [CPLD_QSFP_RESET_24_31] = {CPLD_QSFP_RESET_24_31_REG , MASK_ALL , DATA_HEX}, + + [CPLD_QSFP_LPMODE_0_7] = {CPLD_QSFP_LPMODE_0_7_REG , MASK_ALL , DATA_HEX}, + [CPLD_QSFP_LPMODE_8_15] = {CPLD_QSFP_LPMODE_8_15_REG , MASK_ALL , DATA_HEX}, + [CPLD_QSFP_LPMODE_16_23] = {CPLD_QSFP_LPMODE_16_23_REG , MASK_ALL , DATA_HEX}, + [CPLD_QSFP_LPMODE_24_31] = {CPLD_QSFP_LPMODE_24_31_REG , MASK_ALL , DATA_HEX}, + + [CPLD_SFP_TXDIS_0_1] = {CPLD_SFP_TXDIS_0_1_REG , MASK_ALL , DATA_HEX}, + [CPLD_SFP_TS_0_1] = {CPLD_SFP_TS_0_1_REG , MASK_ALL , DATA_HEX}, + [CPLD_SFP_RS_0_1] = {CPLD_SFP_RS_0_1_REG , MASK_ALL , DATA_HEX}, + + [DBG_CPLD_QSFP_ABS_0_7] = {DBG_CPLD_QSFP_ABS_0_7_REG , MASK_ALL , DATA_HEX}, + [DBG_CPLD_QSFP_ABS_8_15] = {DBG_CPLD_QSFP_ABS_8_15_REG , MASK_ALL , DATA_HEX}, + [DBG_CPLD_QSFP_ABS_16_23] = {DBG_CPLD_QSFP_ABS_16_23_REG , MASK_ALL , DATA_HEX}, + [DBG_CPLD_QSFP_ABS_24_31] = {DBG_CPLD_QSFP_ABS_24_31_REG , MASK_ALL , DATA_HEX}, + + [DBG_CPLD_QSFP_INTR_0_7] = {DBG_CPLD_QSFP_INTR_0_7_REG , MASK_ALL , DATA_HEX}, + [DBG_CPLD_QSFP_INTR_8_15] = {DBG_CPLD_QSFP_INTR_8_15_REG , MASK_ALL , DATA_HEX}, + [DBG_CPLD_QSFP_INTR_16_23] = {DBG_CPLD_QSFP_INTR_16_23_REG , MASK_ALL , DATA_HEX}, + [DBG_CPLD_QSFP_INTR_24_31] = {DBG_CPLD_QSFP_INTR_24_31_REG , MASK_ALL , DATA_HEX}, + + [DBG_CPLD_SFP_ABS_0_1] = {DBG_CPLD_SFP_ABS_0_1_REG , MASK_ALL , DATA_HEX}, + [DBG_CPLD_SFP_RXLOS_0_1] = {DBG_CPLD_SFP_RXLOS_0_1_REG , MASK_ALL , DATA_HEX}, + [DBG_CPLD_SFP_TXFLT_0_1] = {DBG_CPLD_SFP_TXFLT_0_1_REG , MASK_ALL , DATA_HEX}, + + //BSP DEBUG + [BSP_DEBUG] = {CPLD_NONE_REG , MASK_NONE , DATA_UNK}, +}; + +enum bsp_log_types { + LOG_NONE, + LOG_RW, + LOG_READ, + LOG_WRITE +}; + +enum bsp_log_ctrl { + LOG_DISABLE, + LOG_ENABLE +}; + +/* CPLD sysfs attributes hook functions */ +static ssize_t cpld_show(struct device *dev, + struct device_attribute *da, char *buf); +static ssize_t cpld_store(struct device *dev, + struct device_attribute *da, const char *buf, size_t count); +static u8 _cpld_reg_read(struct device *dev, u8 reg, u8 mask); +static ssize_t cpld_reg_read(struct device *dev, char *buf, u8 reg, u8 mask, u8 data_type); +static ssize_t cpld_reg_write(struct device *dev, const char *buf, size_t count, u8 reg, u8 mask); +static ssize_t bsp_read(char *buf, char *str); +static ssize_t bsp_write(const char *buf, char *str, size_t str_len, size_t count); +static ssize_t bsp_callback_show(struct device *dev, + struct device_attribute *da, char *buf); +static ssize_t bsp_callback_store(struct device *dev, + struct device_attribute *da, const char *buf, size_t count); +static ssize_t cpld_version_h_show(struct device *dev, + struct device_attribute *da, + char *buf); + +static LIST_HEAD(cpld_client_list); /* client list for cpld */ +static struct mutex list_lock; /* mutex for client list */ + +struct cpld_client_node { + struct i2c_client *client; + struct list_head list; +}; + +struct cpld_data { + int index; /* CPLD index */ + struct mutex access_lock; /* mutex for cpld access */ + u8 access_reg; /* register to access */ +}; + +/* CPLD device id and data */ +static const struct i2c_device_id cpld_id[] = { + { "s9110_32x_cpld1", cpld1 }, + { "s9110_32x_cpld2", cpld2 }, + {} +}; + +char bsp_debug[2]="0"; +u8 enable_log_read=LOG_DISABLE; +u8 enable_log_write=LOG_DISABLE; + +/* Addresses scanned for cpld */ +static const unsigned short cpld_i2c_addr[] = { 0x30, 0x31, I2C_CLIENT_END }; + +/* define all support register access of cpld in attribute */ + +// CPLD 1 & CPLD2 +static SENSOR_DEVICE_ATTR_RO(cpld_major_ver , cpld, CPLD_MAJOR_VER); +static SENSOR_DEVICE_ATTR_RO(cpld_minor_ver , cpld, CPLD_MINOR_VER); +static SENSOR_DEVICE_ATTR_RO(cpld_id , cpld, CPLD_ID); +static SENSOR_DEVICE_ATTR_RO(cpld_build , cpld, CPLD_BUILD); +static SENSOR_DEVICE_ATTR_RO(cpld_version_h , cpld_version_h, CPLD_VERSION_H); +static SENSOR_DEVICE_ATTR_RO(cpld_chip , cpld, CPLD_CHIP); +static SENSOR_DEVICE_ATTR_RW(cpld_evt_ctrl , cpld, CPLD_EVT_CTRL); + +//CPLD 1 +static SENSOR_DEVICE_ATTR_RO(cpld_board_id_0 , cpld, CPLD_BOARD_ID_0); +static SENSOR_DEVICE_ATTR_RO(cpld_board_id_1 , cpld, CPLD_BOARD_ID_1); +static SENSOR_DEVICE_ATTR_RO(cpld_sku_ext , cpld, CPLD_SKU_EXT); + +static SENSOR_DEVICE_ATTR_RO(cpld_mac_intr , cpld, CPLD_MAC_INTR); +static SENSOR_DEVICE_ATTR_RO(cpld_hwm_intr , cpld, CPLD_HWM_INTR); +static SENSOR_DEVICE_ATTR_RO(cpld_cpld2_intr , cpld, CPLD_CPLD2_INTR); +static SENSOR_DEVICE_ATTR_RO(cpld_ptp_intr , cpld, CPLD_PTP_INTR); +static SENSOR_DEVICE_ATTR_RO(cpld_system_intr , cpld, CPLD_SYSTEM_INTR); + +static SENSOR_DEVICE_ATTR_RW(cpld_mac_mask , cpld, CPLD_MAC_MASK); +static SENSOR_DEVICE_ATTR_RW(cpld_hwm_mask , cpld, CPLD_HWM_MASK); +static SENSOR_DEVICE_ATTR_RW(cpld_cpld2_mask , cpld, CPLD_CPLD2_MASK); +static SENSOR_DEVICE_ATTR_RW(cpld_ptp_mask , cpld, CPLD_PTP_MASK); +static SENSOR_DEVICE_ATTR_RW(cpld_system_mask , cpld, CPLD_SYSTEM_MASK); + +static SENSOR_DEVICE_ATTR_RO(cpld_mac_evt , cpld, CPLD_MAC_EVT); +static SENSOR_DEVICE_ATTR_RO(cpld_hwm_evt , cpld, CPLD_HWM_EVT); +static SENSOR_DEVICE_ATTR_RO(cpld_cpld2_evt , cpld, CPLD_CPLD2_EVT); + +static SENSOR_DEVICE_ATTR_RW(cpld_mac_reset , cpld, CPLD_MAC_RESET); +static SENSOR_DEVICE_ATTR_RW(cpld_system_reset , cpld, CPLD_SYSTEM_RESET); +static SENSOR_DEVICE_ATTR_RW(cpld_bmc_ntm_reset , cpld, CPLD_BMC_NTM_RESET); +static SENSOR_DEVICE_ATTR_RW(cpld_usb_reset , cpld, CPLD_USB_RESET); +static SENSOR_DEVICE_ATTR_RW(cpld_i2c_mux_reset , cpld, CPLD_I2C_MUX_RESET); +static SENSOR_DEVICE_ATTR_RW(cpld_misc_reset , cpld, CPLD_MISC_RESET); + +static SENSOR_DEVICE_ATTR_RO(cpld_brd_present , cpld, CPLD_BRD_PRESENT); +static SENSOR_DEVICE_ATTR_RO(cpld_psu_status , cpld, CPLD_PSU_STATUS); +static SENSOR_DEVICE_ATTR_RO(cpld_system_pwr , cpld, CPLD_SYSTEM_PWR); +static SENSOR_DEVICE_ATTR_RO(cpld_mac_synce , cpld, CPLD_MAC_SYNCE); +static SENSOR_DEVICE_ATTR_RO(cpld_mac_avs , cpld, CPLD_MAC_AVS); +static SENSOR_DEVICE_ATTR_RO(cpld_system_status , cpld, CPLD_SYSTEM_STATUS); +static SENSOR_DEVICE_ATTR_RO(cpld_watchdog , cpld, CPLD_WATCHDOG); +static SENSOR_DEVICE_ATTR_RW(cpld_boot_select , cpld, CPLD_BOOT_SELECT); +static SENSOR_DEVICE_ATTR_RW(cpld_mux_ctrl , cpld, CPLD_MUX_CTRL); +static SENSOR_DEVICE_ATTR_RW(cpld_misc_ctrl_1 , cpld, CPLD_MISC_CTRL_1); +static SENSOR_DEVICE_ATTR_RW(cpld_misc_ctrl_2 , cpld, CPLD_MISC_CTRL_2); +static SENSOR_DEVICE_ATTR_RO(cpld_mac_temp , cpld, CPLD_MAC_TEMP); + +static SENSOR_DEVICE_ATTR_RO(cpld_system_led_psu , cpld, CPLD_SYSTEM_LED_PSU); +static SENSOR_DEVICE_ATTR_RW(cpld_system_led_sys , cpld, CPLD_SYSTEM_LED_SYS); +static SENSOR_DEVICE_ATTR_RO(cpld_system_led_fan , cpld, CPLD_SYSTEM_LED_FAN); +static SENSOR_DEVICE_ATTR_RW(cpld_system_led_id , cpld, CPLD_SYSTEM_LED_ID); + +static SENSOR_DEVICE_ATTR_RO(dbg_cpld_mac_intr , cpld, DBG_CPLD_MAC_INTR); +static SENSOR_DEVICE_ATTR_RO(dbg_cpld_hwm_intr , cpld, DBG_CPLD_HWM_INTR); +static SENSOR_DEVICE_ATTR_RO(dbg_cpld_cpld2_intr , cpld, DBG_CPLD_CPLD2_INTR); +static SENSOR_DEVICE_ATTR_RO(dbg_cpld_ptp_intr , cpld, DBG_CPLD_PTP_INTR); + +//CPLD 2 +static SENSOR_DEVICE_ATTR_RO(cpld_qsfp_abs_0_7 , cpld, CPLD_QSFP_ABS_0_7); +static SENSOR_DEVICE_ATTR_RO(cpld_qsfp_abs_8_15 , cpld, CPLD_QSFP_ABS_8_15); +static SENSOR_DEVICE_ATTR_RO(cpld_qsfp_abs_16_23 , cpld, CPLD_QSFP_ABS_16_23); +static SENSOR_DEVICE_ATTR_RO(cpld_qsfp_abs_24_31 , cpld, CPLD_QSFP_ABS_24_31); + +static SENSOR_DEVICE_ATTR_RO(cpld_qsfp_intr_0_7 , cpld, CPLD_QSFP_INTR_0_7); +static SENSOR_DEVICE_ATTR_RO(cpld_qsfp_intr_8_15 , cpld, CPLD_QSFP_INTR_8_15); +static SENSOR_DEVICE_ATTR_RO(cpld_qsfp_intr_16_23 , cpld, CPLD_QSFP_INTR_16_23); +static SENSOR_DEVICE_ATTR_RO(cpld_qsfp_intr_24_31 , cpld, CPLD_QSFP_INTR_24_31); + +static SENSOR_DEVICE_ATTR_RO(cpld_sfp_abs_0_1 , cpld, CPLD_SFP_ABS_0_1); +static SENSOR_DEVICE_ATTR_RO(cpld_sfp_rxlos_0_1 , cpld, CPLD_SFP_RXLOS_0_1); +static SENSOR_DEVICE_ATTR_RO(cpld_sfp_txflt_0_1 , cpld, CPLD_SFP_TXFLT_0_1); + +static SENSOR_DEVICE_ATTR_RW(cpld_qsfp_mask_abs_0_7 , cpld, CPLD_QSFP_MASK_ABS_0_7); +static SENSOR_DEVICE_ATTR_RW(cpld_qsfp_mask_abs_8_15 , cpld, CPLD_QSFP_MASK_ABS_8_15); +static SENSOR_DEVICE_ATTR_RW(cpld_qsfp_mask_abs_16_23 , cpld, CPLD_QSFP_MASK_ABS_16_23); +static SENSOR_DEVICE_ATTR_RW(cpld_qsfp_mask_abs_24_31 , cpld, CPLD_QSFP_MASK_ABS_24_31); + +static SENSOR_DEVICE_ATTR_RW(cpld_qsfp_mask_intr_0_7 , cpld, CPLD_QSFP_MASK_INTR_0_7); +static SENSOR_DEVICE_ATTR_RW(cpld_qsfp_mask_intr_8_15 , cpld, CPLD_QSFP_MASK_INTR_8_15); +static SENSOR_DEVICE_ATTR_RW(cpld_qsfp_mask_intr_16_23, cpld, CPLD_QSFP_MASK_INTR_16_23); +static SENSOR_DEVICE_ATTR_RW(cpld_qsfp_mask_intr_24_31, cpld, CPLD_QSFP_MASK_INTR_24_31); + +static SENSOR_DEVICE_ATTR_RW(cpld_sfp_mask_abs_0_1 , cpld, CPLD_SFP_MASK_ABS_0_1); +static SENSOR_DEVICE_ATTR_RW(cpld_sfp_mask_rxlos_0_1 , cpld, CPLD_SFP_MASK_RXLOS_0_1); +static SENSOR_DEVICE_ATTR_RW(cpld_sfp_mask_txflt_0_1 , cpld, CPLD_SFP_MASK_TXFLT_0_1); + +static SENSOR_DEVICE_ATTR_RO(cpld_qsfp_evt_abs_0_7 , cpld, CPLD_QSFP_EVT_ABS_0_7); +static SENSOR_DEVICE_ATTR_RO(cpld_qsfp_evt_abs_8_15 , cpld, CPLD_QSFP_EVT_ABS_8_15); +static SENSOR_DEVICE_ATTR_RO(cpld_qsfp_evt_abs_16_23 , cpld, CPLD_QSFP_EVT_ABS_16_23); +static SENSOR_DEVICE_ATTR_RO(cpld_qsfp_evt_abs_24_31 , cpld, CPLD_QSFP_EVT_ABS_24_31); + +static SENSOR_DEVICE_ATTR_RO(cpld_qsfp_evt_intr_0_7 , cpld, CPLD_QSFP_EVT_INTR_0_7); +static SENSOR_DEVICE_ATTR_RO(cpld_qsfp_evt_intr_8_15 , cpld, CPLD_QSFP_EVT_INTR_8_15); +static SENSOR_DEVICE_ATTR_RO(cpld_qsfp_evt_intr_16_23 , cpld, CPLD_QSFP_EVT_INTR_16_23); +static SENSOR_DEVICE_ATTR_RO(cpld_qsfp_evt_intr_24_31 , cpld, CPLD_QSFP_EVT_INTR_24_31); + +static SENSOR_DEVICE_ATTR_RO(cpld_sfp_evt_abs_0_1 , cpld, CPLD_SFP_EVT_ABS_0_1); +static SENSOR_DEVICE_ATTR_RO(cpld_sfp_evt_rxlos_0_1 , cpld, CPLD_SFP_EVT_RXLOS_0_1); +static SENSOR_DEVICE_ATTR_RO(cpld_sfp_evt_txflt_0_1 , cpld, CPLD_SFP_EVT_TXFLT_0_1); + +static SENSOR_DEVICE_ATTR_RW(cpld_qsfp_reset_0_7 , cpld, CPLD_QSFP_RESET_0_7); +static SENSOR_DEVICE_ATTR_RW(cpld_qsfp_reset_8_15 , cpld, CPLD_QSFP_RESET_8_15); +static SENSOR_DEVICE_ATTR_RW(cpld_qsfp_reset_16_23 , cpld, CPLD_QSFP_RESET_16_23); +static SENSOR_DEVICE_ATTR_RW(cpld_qsfp_reset_24_31 , cpld, CPLD_QSFP_RESET_24_31); + +static SENSOR_DEVICE_ATTR_RW(cpld_qsfp_lpmode_0_7 , cpld, CPLD_QSFP_LPMODE_0_7); +static SENSOR_DEVICE_ATTR_RW(cpld_qsfp_lpmode_8_15 , cpld, CPLD_QSFP_LPMODE_8_15); +static SENSOR_DEVICE_ATTR_RW(cpld_qsfp_lpmode_16_23 , cpld, CPLD_QSFP_LPMODE_16_23); +static SENSOR_DEVICE_ATTR_RW(cpld_qsfp_lpmode_24_31 , cpld, CPLD_QSFP_LPMODE_24_31); + +static SENSOR_DEVICE_ATTR_RW(cpld_sfp_txdis_0_1 , cpld, CPLD_SFP_TXDIS_0_1); +static SENSOR_DEVICE_ATTR_RW(cpld_sfp_ts_0_1 , cpld, CPLD_SFP_TS_0_1); +static SENSOR_DEVICE_ATTR_RW(cpld_sfp_rs_0_1 , cpld, CPLD_SFP_RS_0_1); + +static SENSOR_DEVICE_ATTR_RO(dbg_cpld_qsfp_abs_0_7 , cpld, DBG_CPLD_QSFP_ABS_0_7); +static SENSOR_DEVICE_ATTR_RO(dbg_cpld_qsfp_abs_8_15 , cpld, DBG_CPLD_QSFP_ABS_8_15); +static SENSOR_DEVICE_ATTR_RO(dbg_cpld_qsfp_abs_16_23 , cpld, DBG_CPLD_QSFP_ABS_16_23); +static SENSOR_DEVICE_ATTR_RO(dbg_cpld_qsfp_abs_24_31 , cpld, DBG_CPLD_QSFP_ABS_24_31); + +static SENSOR_DEVICE_ATTR_RO(dbg_cpld_qsfp_intr_0_7 , cpld, DBG_CPLD_QSFP_INTR_0_7); +static SENSOR_DEVICE_ATTR_RO(dbg_cpld_qsfp_intr_8_15 , cpld, DBG_CPLD_QSFP_INTR_8_15); +static SENSOR_DEVICE_ATTR_RO(dbg_cpld_qsfp_intr_16_23 , cpld, DBG_CPLD_QSFP_INTR_16_23); +static SENSOR_DEVICE_ATTR_RO(dbg_cpld_qsfp_intr_24_31 , cpld, DBG_CPLD_QSFP_INTR_24_31); + +static SENSOR_DEVICE_ATTR_RO(dbg_cpld_sfp_abs_0_1 , cpld, DBG_CPLD_SFP_ABS_0_1); +static SENSOR_DEVICE_ATTR_RO(dbg_cpld_sfp_rxlos_0_1 , cpld, DBG_CPLD_SFP_RXLOS_0_1); +static SENSOR_DEVICE_ATTR_RO(dbg_cpld_sfp_txflt_0_1 , cpld, DBG_CPLD_SFP_TXFLT_0_1); + +//BSP DEBUG +static SENSOR_DEVICE_ATTR_RW(bsp_debug , bsp_callback, BSP_DEBUG); + +/* define support attributes of cpldx */ + +/* cpld 1 */ +static struct attribute *cpld1_attributes[] = { + _DEVICE_ATTR(cpld_board_id_0), + _DEVICE_ATTR(cpld_board_id_1), + _DEVICE_ATTR(cpld_sku_ext), + + _DEVICE_ATTR(cpld_major_ver), + _DEVICE_ATTR(cpld_minor_ver), + _DEVICE_ATTR(cpld_id), + _DEVICE_ATTR(cpld_build), + _DEVICE_ATTR(cpld_version_h), + _DEVICE_ATTR(cpld_chip), + + _DEVICE_ATTR(cpld_mac_intr), + _DEVICE_ATTR(cpld_hwm_intr), + _DEVICE_ATTR(cpld_cpld2_intr), + _DEVICE_ATTR(cpld_ptp_intr), + _DEVICE_ATTR(cpld_system_intr), + + _DEVICE_ATTR(cpld_mac_mask), + _DEVICE_ATTR(cpld_hwm_mask), + _DEVICE_ATTR(cpld_cpld2_mask), + _DEVICE_ATTR(cpld_ptp_mask), + _DEVICE_ATTR(cpld_system_mask), + + _DEVICE_ATTR(cpld_mac_evt), + _DEVICE_ATTR(cpld_hwm_evt), + _DEVICE_ATTR(cpld_cpld2_evt), + + _DEVICE_ATTR(cpld_evt_ctrl), + + _DEVICE_ATTR(cpld_mac_reset), + _DEVICE_ATTR(cpld_system_reset), + _DEVICE_ATTR(cpld_bmc_ntm_reset), + _DEVICE_ATTR(cpld_usb_reset), + _DEVICE_ATTR(cpld_i2c_mux_reset), + _DEVICE_ATTR(cpld_misc_reset), + + _DEVICE_ATTR(cpld_brd_present), + _DEVICE_ATTR(cpld_psu_status), + _DEVICE_ATTR(cpld_system_pwr), + _DEVICE_ATTR(cpld_mac_synce), + _DEVICE_ATTR(cpld_mac_avs), + _DEVICE_ATTR(cpld_system_status), + _DEVICE_ATTR(cpld_watchdog), + _DEVICE_ATTR(cpld_boot_select), + _DEVICE_ATTR(cpld_mux_ctrl), + _DEVICE_ATTR(cpld_misc_ctrl_1), + _DEVICE_ATTR(cpld_misc_ctrl_2), + _DEVICE_ATTR(cpld_mac_temp), + + _DEVICE_ATTR(cpld_system_led_psu), + _DEVICE_ATTR(cpld_system_led_sys), + _DEVICE_ATTR(cpld_system_led_fan), + _DEVICE_ATTR(cpld_system_led_id), + + _DEVICE_ATTR(dbg_cpld_mac_intr), + _DEVICE_ATTR(dbg_cpld_hwm_intr), + _DEVICE_ATTR(dbg_cpld_cpld2_intr), + _DEVICE_ATTR(dbg_cpld_ptp_intr), + + _DEVICE_ATTR(bsp_debug), + + NULL +}; + +/* cpld 2 */ +static struct attribute *cpld2_attributes[] = { + + _DEVICE_ATTR(cpld_major_ver), + _DEVICE_ATTR(cpld_minor_ver), + _DEVICE_ATTR(cpld_id), + _DEVICE_ATTR(cpld_build), + _DEVICE_ATTR(cpld_version_h), + _DEVICE_ATTR(cpld_chip), + + _DEVICE_ATTR(cpld_qsfp_abs_0_7), + _DEVICE_ATTR(cpld_qsfp_abs_8_15), + _DEVICE_ATTR(cpld_qsfp_abs_16_23), + _DEVICE_ATTR(cpld_qsfp_abs_24_31), + + _DEVICE_ATTR(cpld_qsfp_intr_0_7), + _DEVICE_ATTR(cpld_qsfp_intr_8_15), + _DEVICE_ATTR(cpld_qsfp_intr_16_23), + _DEVICE_ATTR(cpld_qsfp_intr_24_31), + + _DEVICE_ATTR(cpld_sfp_abs_0_1), + _DEVICE_ATTR(cpld_sfp_rxlos_0_1), + _DEVICE_ATTR(cpld_sfp_txflt_0_1), + + _DEVICE_ATTR(cpld_qsfp_mask_abs_0_7), + _DEVICE_ATTR(cpld_qsfp_mask_abs_8_15), + _DEVICE_ATTR(cpld_qsfp_mask_abs_16_23), + _DEVICE_ATTR(cpld_qsfp_mask_abs_24_31), + + _DEVICE_ATTR(cpld_qsfp_mask_intr_0_7), + _DEVICE_ATTR(cpld_qsfp_mask_intr_8_15), + _DEVICE_ATTR(cpld_qsfp_mask_intr_16_23), + _DEVICE_ATTR(cpld_qsfp_mask_intr_24_31), + + _DEVICE_ATTR(cpld_sfp_mask_abs_0_1), + _DEVICE_ATTR(cpld_sfp_mask_rxlos_0_1), + _DEVICE_ATTR(cpld_sfp_mask_txflt_0_1), + + _DEVICE_ATTR(cpld_qsfp_evt_abs_0_7), + _DEVICE_ATTR(cpld_qsfp_evt_abs_8_15), + _DEVICE_ATTR(cpld_qsfp_evt_abs_16_23), + _DEVICE_ATTR(cpld_qsfp_evt_abs_24_31), + + _DEVICE_ATTR(cpld_qsfp_evt_intr_0_7), + _DEVICE_ATTR(cpld_qsfp_evt_intr_8_15), + _DEVICE_ATTR(cpld_qsfp_evt_intr_16_23), + _DEVICE_ATTR(cpld_qsfp_evt_intr_24_31), + + _DEVICE_ATTR(cpld_sfp_evt_abs_0_1), + _DEVICE_ATTR(cpld_sfp_evt_rxlos_0_1), + _DEVICE_ATTR(cpld_sfp_evt_txflt_0_1), + + _DEVICE_ATTR(cpld_evt_ctrl), + + _DEVICE_ATTR(cpld_qsfp_reset_0_7), + _DEVICE_ATTR(cpld_qsfp_reset_8_15), + _DEVICE_ATTR(cpld_qsfp_reset_16_23), + _DEVICE_ATTR(cpld_qsfp_reset_24_31), + + _DEVICE_ATTR(cpld_qsfp_lpmode_0_7), + _DEVICE_ATTR(cpld_qsfp_lpmode_8_15), + _DEVICE_ATTR(cpld_qsfp_lpmode_16_23), + _DEVICE_ATTR(cpld_qsfp_lpmode_24_31), + + _DEVICE_ATTR(cpld_sfp_txdis_0_1), + _DEVICE_ATTR(cpld_sfp_ts_0_1), + _DEVICE_ATTR(cpld_sfp_rs_0_1), + + _DEVICE_ATTR(dbg_cpld_qsfp_abs_0_7), + _DEVICE_ATTR(dbg_cpld_qsfp_abs_8_15), + _DEVICE_ATTR(dbg_cpld_qsfp_abs_16_23), + _DEVICE_ATTR(dbg_cpld_qsfp_abs_24_31), + + _DEVICE_ATTR(dbg_cpld_qsfp_intr_0_7), + _DEVICE_ATTR(dbg_cpld_qsfp_intr_8_15), + _DEVICE_ATTR(dbg_cpld_qsfp_intr_16_23), + _DEVICE_ATTR(dbg_cpld_qsfp_intr_24_31), + + _DEVICE_ATTR(dbg_cpld_sfp_abs_0_1), + _DEVICE_ATTR(dbg_cpld_sfp_rxlos_0_1), + _DEVICE_ATTR(dbg_cpld_sfp_txflt_0_1), + + NULL +}; + +/* cpld 1 attributes group */ +static const struct attribute_group cpld1_group = { + .attrs = cpld1_attributes, +}; + +/* cpld 2 attributes group */ +static const struct attribute_group cpld2_group = { + .attrs = cpld2_attributes, +}; + +/* reg shift */ +static u8 _shift(u8 mask) +{ + int i=0, mask_one=1; + + for(i=0; i<8; ++i) { + if ((mask & mask_one) == 1) + return i; + else + mask >>= 1; + } + + return -1; +} + +/* reg mask and shift */ +static u8 _mask_shift(u8 val, u8 mask) +{ + int shift=0; + + shift = _shift(mask); + + return (val & mask) >> shift; +} + +static u8 _parse_data(char *buf, unsigned int data, u8 data_type) +{ + if(buf == NULL) { + return -1; + } + + if(data_type == DATA_HEX) { + return sprintf(buf, "0x%02x", data); + } else if(data_type == DATA_DEC) { + return sprintf(buf, "%u", data); + } else { + return -1; + } + return 0; +} + +static int _bsp_log(u8 log_type, char *fmt, ...) +{ + if ((log_type==LOG_READ && enable_log_read) || + (log_type==LOG_WRITE && enable_log_write)) { + va_list args; + int r; + + va_start(args, fmt); + r = vprintk(fmt, args); + va_end(args); + + return r; + } else { + return 0; + } +} + +static int _config_bsp_log(u8 log_type) +{ + switch(log_type) { + case LOG_NONE: + enable_log_read = LOG_DISABLE; + enable_log_write = LOG_DISABLE; + break; + case LOG_RW: + enable_log_read = LOG_ENABLE; + enable_log_write = LOG_ENABLE; + break; + case LOG_READ: + enable_log_read = LOG_ENABLE; + enable_log_write = LOG_DISABLE; + break; + case LOG_WRITE: + enable_log_read = LOG_DISABLE; + enable_log_write = LOG_ENABLE; + break; + default: + return -EINVAL; + } + return 0; +} + +/* get bsp value */ +static ssize_t bsp_read(char *buf, char *str) +{ + ssize_t len=0; + + len=sprintf(buf, "%s", str); + BSP_LOG_R("reg_val=%s", str); + + return len; +} + +/* set bsp value */ +static ssize_t bsp_write(const char *buf, char *str, size_t str_len, size_t count) +{ + snprintf(str, str_len, "%s", buf); + BSP_LOG_W("reg_val=%s", str); + + return count; +} + +/* get bsp parameter value */ +static ssize_t bsp_callback_show(struct device *dev, + struct device_attribute *da, char *buf) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + int str_len=0; + char *str=NULL; + + switch (attr->index) { + case BSP_DEBUG: + str = bsp_debug; + str_len = sizeof(bsp_debug); + break; + default: + return -EINVAL; + } + return bsp_read(buf, str); +} + +/* set bsp parameter value */ +static ssize_t bsp_callback_store(struct device *dev, + struct device_attribute *da, const char *buf, size_t count) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + int str_len=0; + char *str=NULL; + ssize_t ret = 0; + u8 bsp_debug_u8 = 0; + + switch (attr->index) { + case BSP_DEBUG: + str = bsp_debug; + str_len = sizeof(str); + ret = bsp_write(buf, str, str_len, count); + + if (kstrtou8(buf, 0, &bsp_debug_u8) < 0) { + return -EINVAL; + } else if (_config_bsp_log(bsp_debug_u8) < 0) { + return -EINVAL; + } + return ret; + default: + return -EINVAL; + } + return 0; +} + +/* get cpld register value */ +static ssize_t cpld_show(struct device *dev, + struct device_attribute *da, char *buf) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + u8 reg = 0; + u8 mask = MASK_NONE; + u8 data_type=DATA_UNK; + + switch (attr->index) { + //CPLD 1 & CPLD 2 + case CPLD_MAJOR_VER: + case CPLD_MINOR_VER: + case CPLD_ID: + case CPLD_BUILD: + case CPLD_CHIP: + case CPLD_EVT_CTRL: + + //CPLD 1 + case CPLD_BOARD_ID_0: + case CPLD_BOARD_ID_1: + case CPLD_SKU_EXT: + + case CPLD_MAC_INTR: + case CPLD_HWM_INTR: + case CPLD_CPLD2_INTR: + case CPLD_PTP_INTR: + case CPLD_SYSTEM_INTR: + + case CPLD_MAC_MASK: + case CPLD_HWM_MASK: + case CPLD_CPLD2_MASK: + case CPLD_PTP_MASK: + case CPLD_SYSTEM_MASK: + + case CPLD_MAC_EVT: + case CPLD_HWM_EVT: + case CPLD_CPLD2_EVT: + + case CPLD_MAC_RESET: + case CPLD_SYSTEM_RESET: + case CPLD_BMC_NTM_RESET: + case CPLD_USB_RESET: + case CPLD_I2C_MUX_RESET: + case CPLD_MISC_RESET: + + case CPLD_BRD_PRESENT: + case CPLD_PSU_STATUS: + case CPLD_SYSTEM_PWR: + case CPLD_MAC_SYNCE: + case CPLD_MAC_AVS: + case CPLD_SYSTEM_STATUS: + case CPLD_WATCHDOG: + case CPLD_BOOT_SELECT: + case CPLD_MUX_CTRL: + case CPLD_MISC_CTRL_1: + case CPLD_MISC_CTRL_2: + case CPLD_MAC_TEMP: + + case CPLD_SYSTEM_LED_PSU: + case CPLD_SYSTEM_LED_SYS: + case CPLD_SYSTEM_LED_FAN: + case CPLD_SYSTEM_LED_ID: + + case DBG_CPLD_MAC_INTR: + case DBG_CPLD_HWM_INTR: + case DBG_CPLD_CPLD2_INTR: + case DBG_CPLD_PTP_INTR: + + //CPLD 2 + case CPLD_QSFP_ABS_0_7: + case CPLD_QSFP_ABS_8_15: + case CPLD_QSFP_ABS_16_23: + case CPLD_QSFP_ABS_24_31: + + case CPLD_QSFP_INTR_0_7: + case CPLD_QSFP_INTR_8_15: + case CPLD_QSFP_INTR_16_23: + case CPLD_QSFP_INTR_24_31: + + case CPLD_SFP_ABS_0_1: + case CPLD_SFP_RXLOS_0_1: + case CPLD_SFP_TXFLT_0_1: + + case CPLD_QSFP_MASK_ABS_0_7: + case CPLD_QSFP_MASK_ABS_8_15: + case CPLD_QSFP_MASK_ABS_16_23: + case CPLD_QSFP_MASK_ABS_24_31: + + case CPLD_QSFP_MASK_INTR_0_7: + case CPLD_QSFP_MASK_INTR_8_15: + case CPLD_QSFP_MASK_INTR_16_23: + case CPLD_QSFP_MASK_INTR_24_31: + + case CPLD_SFP_MASK_ABS_0_1: + case CPLD_SFP_MASK_RXLOS_0_1: + case CPLD_SFP_MASK_TXFLT_0_1: + + case CPLD_QSFP_EVT_ABS_0_7: + case CPLD_QSFP_EVT_ABS_8_15: + case CPLD_QSFP_EVT_ABS_16_23: + case CPLD_QSFP_EVT_ABS_24_31: + + case CPLD_QSFP_EVT_INTR_0_7: + case CPLD_QSFP_EVT_INTR_8_15: + case CPLD_QSFP_EVT_INTR_16_23: + case CPLD_QSFP_EVT_INTR_24_31: + + case CPLD_SFP_EVT_ABS_0_1: + case CPLD_SFP_EVT_RXLOS_0_1: + case CPLD_SFP_EVT_TXFLT_0_1: + + case CPLD_QSFP_RESET_0_7: + case CPLD_QSFP_RESET_8_15: + case CPLD_QSFP_RESET_16_23: + case CPLD_QSFP_RESET_24_31: + + case CPLD_QSFP_LPMODE_0_7: + case CPLD_QSFP_LPMODE_8_15: + case CPLD_QSFP_LPMODE_16_23: + case CPLD_QSFP_LPMODE_24_31: + + case CPLD_SFP_TXDIS_0_1: + case CPLD_SFP_TS_0_1: + case CPLD_SFP_RS_0_1: + + case DBG_CPLD_QSFP_ABS_0_7: + case DBG_CPLD_QSFP_ABS_8_15: + case DBG_CPLD_QSFP_ABS_16_23: + case DBG_CPLD_QSFP_ABS_24_31: + + case DBG_CPLD_QSFP_INTR_0_7: + case DBG_CPLD_QSFP_INTR_8_15: + case DBG_CPLD_QSFP_INTR_16_23: + case DBG_CPLD_QSFP_INTR_24_31: + + case DBG_CPLD_SFP_ABS_0_1: + case DBG_CPLD_SFP_RXLOS_0_1: + case DBG_CPLD_SFP_TXFLT_0_1: + reg = attr_reg[attr->index].reg; + mask= attr_reg[attr->index].mask; + data_type = attr_reg[attr->index].data_type; + break; + default: + return -EINVAL; + } + return cpld_reg_read(dev, buf, reg, mask, data_type); +} + +/* set cpld register value */ +static ssize_t cpld_store(struct device *dev, + struct device_attribute *da, const char *buf, size_t count) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + u8 reg = 0; + u8 mask = MASK_NONE; + + switch (attr->index) { + + // CPLD 1 & CPLD2 + case CPLD_EVT_CTRL: + + //CPLD 1 + case CPLD_MAC_MASK: + case CPLD_HWM_MASK: + case CPLD_CPLD2_MASK: + case CPLD_PTP_MASK: + case CPLD_SYSTEM_MASK: + case CPLD_MAC_RESET: + case CPLD_SYSTEM_RESET: + case CPLD_BMC_NTM_RESET: + case CPLD_USB_RESET: + case CPLD_I2C_MUX_RESET: + case CPLD_MISC_RESET: + case CPLD_BOOT_SELECT: + case CPLD_MUX_CTRL: + case CPLD_MISC_CTRL_1: + case CPLD_MISC_CTRL_2: + case CPLD_SYSTEM_LED_PSU: + case CPLD_SYSTEM_LED_SYS: + case CPLD_SYSTEM_LED_FAN: + case CPLD_SYSTEM_LED_ID: + + //CPLD 2 + case CPLD_QSFP_MASK_ABS_0_7: + case CPLD_QSFP_MASK_ABS_8_15: + case CPLD_QSFP_MASK_ABS_16_23: + case CPLD_QSFP_MASK_ABS_24_31: + case CPLD_QSFP_MASK_INTR_0_7: + case CPLD_QSFP_MASK_INTR_8_15: + case CPLD_QSFP_MASK_INTR_16_23: + case CPLD_QSFP_MASK_INTR_24_31: + case CPLD_SFP_MASK_ABS_0_1: + case CPLD_SFP_MASK_RXLOS_0_1: + case CPLD_SFP_MASK_TXFLT_0_1: + case CPLD_QSFP_RESET_0_7: + case CPLD_QSFP_RESET_8_15: + case CPLD_QSFP_RESET_16_23: + case CPLD_QSFP_RESET_24_31: + case CPLD_QSFP_LPMODE_0_7: + case CPLD_QSFP_LPMODE_8_15: + case CPLD_QSFP_LPMODE_16_23: + case CPLD_QSFP_LPMODE_24_31: + case CPLD_SFP_TXDIS_0_1: + case CPLD_SFP_TS_0_1: + case CPLD_SFP_RS_0_1: + reg = attr_reg[attr->index].reg; + mask= attr_reg[attr->index].mask; + break; + default: + return -EINVAL; + } + return cpld_reg_write(dev, buf, count, reg, mask); +} + +/* get cpld register value */ +static u8 _cpld_reg_read(struct device *dev, + u8 reg, + u8 mask) +{ + struct i2c_client *client = to_i2c_client(dev); + struct cpld_data *data = i2c_get_clientdata(client); + int reg_val; + + I2C_READ_BYTE_DATA(reg_val, &data->access_lock, client, reg); + + if (unlikely(reg_val < 0)) { + return reg_val; + } else { + reg_val=_mask_shift(reg_val, mask); + return reg_val; + } +} + +/* get cpld register value */ +static ssize_t cpld_reg_read(struct device *dev, + char *buf, + u8 reg, + u8 mask, + u8 data_type) +{ + int reg_val; + + reg_val = _cpld_reg_read(dev, reg, mask); + if (unlikely(reg_val < 0)) { + dev_err(dev, "cpld_reg_read() error, reg_val=%d\n", reg_val); + return reg_val; + } else { + return _parse_data(buf, reg_val, data_type); + } +} + +/* set cpld register value */ +static ssize_t cpld_reg_write(struct device *dev, + const char *buf, + size_t count, + u8 reg, + u8 mask) +{ + struct i2c_client *client = to_i2c_client(dev); + struct cpld_data *data = i2c_get_clientdata(client); + u8 reg_val, reg_val_now, shift; + int ret = 0; + + if (kstrtou8(buf, 0, ®_val) < 0) + return -EINVAL; + + //apply continuous bits operation if mask is specified, discontinuous bits are not supported + if (mask != MASK_ALL) { + reg_val_now = _cpld_reg_read(dev, reg, MASK_ALL); + if (unlikely(reg_val_now < 0)) { + dev_err(dev, "cpld_reg_write() error, reg_val_now=%d\n", reg_val_now); + return reg_val_now; + } else { + //clear bits in reg_val_now by the mask + reg_val_now &= ~mask; + //get bit shift by the mask + shift = _shift(mask); + //calculate new reg_val + reg_val = reg_val_now | (reg_val << shift); + } + } + + I2C_WRITE_BYTE_DATA(ret, &data->access_lock, + client, reg, reg_val); + + if (unlikely(ret < 0)) { + dev_err(dev, "cpld_reg_write() error, return=%d\n", ret); + return ret; + } + + return count; +} + +/* get qsfp port config register value */ +static ssize_t cpld_version_h_show(struct device *dev, + struct device_attribute *da, + char *buf) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + + if (attr->index == CPLD_VERSION_H) { + return sprintf(buf, "%d.%02d.%03d", + _cpld_reg_read(dev, attr_reg[CPLD_MAJOR_VER].reg, attr_reg[CPLD_MAJOR_VER].mask), + _cpld_reg_read(dev, attr_reg[CPLD_MINOR_VER].reg, attr_reg[CPLD_MINOR_VER].mask), + _cpld_reg_read(dev, attr_reg[CPLD_BUILD].reg, attr_reg[CPLD_BUILD].mask)); + } + return -1; +} + +/* add valid cpld client to list */ +static void cpld_add_client(struct i2c_client *client) +{ + struct cpld_client_node *node = NULL; + + node = kzalloc(sizeof(struct cpld_client_node), GFP_KERNEL); + if (!node) { + dev_info(&client->dev, + "Can't allocate cpld_client_node for index %d\n", + client->addr); + return; + } + + node->client = client; + + mutex_lock(&list_lock); + list_add(&node->list, &cpld_client_list); + mutex_unlock(&list_lock); +} + +/* remove exist cpld client in list */ +static void cpld_remove_client(struct i2c_client *client) +{ + struct list_head *list_node = NULL; + struct cpld_client_node *cpld_node = NULL; + int found = 0; + + mutex_lock(&list_lock); + list_for_each(list_node, &cpld_client_list) { + cpld_node = list_entry(list_node, + struct cpld_client_node, list); + + if (cpld_node->client == client) { + found = 1; + break; + } + } + + if (found) { + list_del(list_node); + kfree(cpld_node); + } + mutex_unlock(&list_lock); +} + +/* cpld drvier probe */ +static int cpld_probe(struct i2c_client *client, + const struct i2c_device_id *dev_id) +{ + int status; + struct cpld_data *data = NULL; + int ret = -EPERM; + + data = kzalloc(sizeof(struct cpld_data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + /* init cpld data for client */ + i2c_set_clientdata(client, data); + mutex_init(&data->access_lock); + + if (!i2c_check_functionality(client->adapter, + I2C_FUNC_SMBUS_BYTE_DATA)) { + dev_info(&client->dev, + "i2c_check_functionality failed (0x%x)\n", + client->addr); + status = -EIO; + goto exit; + } + + /* get cpld id from device */ + ret = i2c_smbus_read_byte_data(client, CPLD_ID_REG); + + if (ret < 0) { + dev_info(&client->dev, + "fail to get cpld id (0x%x) at addr (0x%x)\n", + CPLD_ID_REG, client->addr); + status = -EIO; + goto exit; + } + + if (INVALID(ret, cpld1, cpld2)) { + dev_info(&client->dev, + "cpld id %d(device) not valid\n", ret); + //status = -EPERM; + //goto exit; + } + + data->index = dev_id->driver_data; + + /* register sysfs hooks for different cpld group */ + dev_info(&client->dev, "probe cpld with index %d\n", data->index); + switch (data->index) { + case cpld1: + status = sysfs_create_group(&client->dev.kobj, + &cpld1_group); + break; + case cpld2: + status = sysfs_create_group(&client->dev.kobj, + &cpld2_group); + break; + default: + status = -EINVAL; + } + + if (status) + goto exit; + + dev_info(&client->dev, "chip found\n"); + + /* add probe chip to client list */ + cpld_add_client(client); + + return 0; +exit: + switch (data->index) { + case cpld1: + sysfs_remove_group(&client->dev.kobj, &cpld1_group); + break; + case cpld2: + sysfs_remove_group(&client->dev.kobj, &cpld2_group); + break; + default: + break; + } + return status; +} + +/* cpld drvier remove */ +static int cpld_remove(struct i2c_client *client) +{ + struct cpld_data *data = i2c_get_clientdata(client); + + switch (data->index) { + case cpld1: + sysfs_remove_group(&client->dev.kobj, &cpld1_group); + break; + case cpld2: + sysfs_remove_group(&client->dev.kobj, &cpld2_group); + break; + } + + cpld_remove_client(client); + return 0; +} + +#if 0 /* FIXME */ +#define I2C_RW_RETRY_COUNT 3 +#define I2C_RW_RETRY_INTERVAL 60 + +static int s9110_32x_cpld_read_internal(struct i2c_client *client, u8 reg) +{ + int retry = I2C_RW_RETRY_COUNT; + int reg_val = 0; + struct cpld_data *data = i2c_get_clientdata(client); + + while (retry) { + I2C_READ_BYTE_DATA(reg_val, &data->access_lock, client, reg); + if (unlikely(reg_val < 0)) { + msleep(I2C_RW_RETRY_INTERVAL); + retry--; + + if (retry == 0) { + dev_err(&client->dev, "%s() retry %d times but still failed, reg=%x\n", __func__, I2C_RW_RETRY_COUNT, reg); + } + + continue; + } + + break; + } + + return reg_val; +} + +static int s9110_32x_cpld_write_internal(struct i2c_client *client, u8 reg, u8 value) +{ + int ret = 0, retry = I2C_RW_RETRY_COUNT; + struct cpld_data *data = i2c_get_clientdata(client); + + while (retry) { + I2C_WRITE_BYTE_DATA(ret, &data->access_lock, client, reg, value); + if (unlikely(ret < 0)) { + msleep(I2C_RW_RETRY_INTERVAL); + retry--; + + if (retry == 0) { + dev_err(&client->dev, "%s() retry %d times but still failed, reg=%x\n", __func__, I2C_RW_RETRY_COUNT, reg); + } + + continue; + } + break; + } + + return ret; +} + + +int s9110_32x_cpld_psu_mux_sel(u8 mux_sel) +{ + unsigned short cpld_addr = cpld_i2c_addr[0]; + u8 reg = CPLD_MUX_CTRL_REG; + u8 reg_val = 0; + u8 psu_mux_mask = 0x06; + u8 mux_sel_val = 0; + + struct list_head *list_node = NULL; + struct cpld_client_node *cpld_node = NULL; + int ret = -EIO; + + switch(mux_sel) { + case 0: + //psu 0 + mux_sel_val = 0x04; + break; + case 1: + //psu 1 + mux_sel_val = 0x02; + break; + default: + //bmc + mux_sel_val = psu_mux_mask; + break; + } + + mutex_lock(&list_lock); + + list_for_each(list_node, &cpld_client_list) + { + cpld_node = list_entry(list_node, struct cpld_client_node, list); + + if (cpld_node->client->addr == cpld_addr) { + //read current reg value + reg_val = s9110_32x_cpld_read_internal(cpld_node->client, reg); + //clear psu_mux_sel bits (bit 1 and 2) + reg_val &= ~psu_mux_mask; + //modify psu_mux_sel bits (bit 1 and 2) + reg_val |= mux_sel_val; + //write reg value + s9110_32x_cpld_write_internal(cpld_node->client, reg, reg_val); + + break; + } else { + pr_err("cpld_node->client->addr=%x, cpld_addr=%x\n", cpld_node->client->addr, cpld_addr); + } + } + + mutex_unlock(&list_lock); + + return ret; +} +EXPORT_SYMBOL(s9110_32x_cpld_psu_mux_sel); +#endif + +MODULE_DEVICE_TABLE(i2c, cpld_id); + +static struct i2c_driver cpld_driver = { + .class = I2C_CLASS_HWMON, + .driver = { + .name = "x86_64_ufispace_s9110_32x_cpld", + }, + .probe = cpld_probe, + .remove = cpld_remove, + .id_table = cpld_id, + .address_list = cpld_i2c_addr, +}; + +static int __init cpld_init(void) +{ + mutex_init(&list_lock); + return i2c_add_driver(&cpld_driver); +} + +static void __exit cpld_exit(void) +{ + i2c_del_driver(&cpld_driver); +} + +MODULE_AUTHOR("Nonodark Huang "); +MODULE_DESCRIPTION("x86_64_ufispace_s9110_32x_cpld driver"); +MODULE_LICENSE("GPL"); + +module_init(cpld_init); +module_exit(cpld_exit); diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/modules/x86-64-ufispace-s9110-32x-cpld.h b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/modules/x86-64-ufispace-s9110-32x-cpld.h new file mode 100644 index 000000000000..74db9cab4a69 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/modules/x86-64-ufispace-s9110-32x-cpld.h @@ -0,0 +1,149 @@ +/* header file for i2c cpld driver of ufispace_s9110_32x + * + * Copyright (C) 2022 UfiSpace Technology Corporation. + * Jason Tsai + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef UFISPACE_S9110_32X_CPLD_H +#define UFISPACE_S9110_32X_CPLD_H + +/* CPLD device index value */ +enum cpld_id { + cpld1, + cpld2 +}; + +/* CPLD 1 & CPLD 2 registers */ +#define CPLD_NONE_REG 0x00 +#define CPLD_VERSION_REG 0x02 +#define CPLD_ID_REG 0x03 +#define CPLD_BUILD_REG 0x04 +#define CPLD_CHIP_REG 0x05 +#define CPLD_EVT_CTRL_REG 0x3F + +/* CPLD 1 registers */ +#define CPLD_BOARD_ID_0_REG 0x00 +#define CPLD_BOARD_ID_1_REG 0x01 +#define CPLD_SKU_EXT_REG 0x06 +#define CPLD_MAC_INTR_REG 0x10 +#define CPLD_HWM_INTR_REG 0x13 +#define CPLD_CPLD2_INTR_REG 0x14 +#define CPLD_PTP_INTR_REG 0x1B +#define CPLD_SYSTEM_INTR_REG 0x1C +#define CPLD_MAC_MASK_REG 0x20 +#define CPLD_HWM_MASK_REG 0x23 +#define CPLD_CPLD2_MASK_REG 0x24 +#define CPLD_PTP_MASK_REG 0x2B +#define CPLD_SYSTEM_MASK_REG 0x2C +#define CPLD_MAC_EVT_REG 0x30 +#define CPLD_HWM_EVT_REG 0x33 +#define CPLD_CPLD2_EVT_REG 0x34 +#define CPLD_MAC_RESET_REG 0x40 +#define CPLD_SYSTEM_RESET_REG 0x41 +#define CPLD_BMC_NTM_RESET_REG 0x43 +#define CPLD_USB_RESET_REG 0x44 +#define CPLD_I2C_MUX_RESET_REG 0x46 +#define CPLD_MISC_RESET_REG 0x48 +#define CPLD_BRD_PRESENT_REG 0x50 +#define CPLD_PSU_STATUS_REG 0x51 +#define CPLD_SYSTEM_PWR_REG 0x52 +#define CPLD_MAC_SYNCE_REG 0x53 +#define CPLD_MAC_AVS_REG 0x54 +#define CPLD_SYSTEM_STATUS_REG 0x55 +#define CPLD_WATCHDOG_REG 0x5A +#define CPLD_BOOT_SELECT_REG 0x5B +#define CPLD_MUX_CTRL_REG 0x5C +#define CPLD_MISC_CTRL_1_REG 0x5D +#define CPLD_MISC_CTRL_2_REG 0x5E +#define CPLD_MAC_TEMP_REG 0x61 +#define CPLD_SYSTEM_LED_PSU_REG 0x80 +#define CPLD_SYSTEM_LED_SYS_REG 0x81 +#define CPLD_SYSTEM_LED_FAN_REG 0x83 +#define CPLD_SYSTEM_LED_ID_REG 0x84 +#define DBG_CPLD_MAC_INTR_REG 0xE0 +#define DBG_CPLD_HWM_INTR_REG 0xE3 +#define DBG_CPLD_CPLD2_INTR_REG 0xE4 +#define DBG_CPLD_PTP_INTR_REG 0xEB + +/* CPLD 2*/ +#define CPLD_QSFP_ABS_0_7_REG 0x10 +#define CPLD_QSFP_ABS_8_15_REG 0x11 +#define CPLD_QSFP_ABS_16_23_REG 0x12 +#define CPLD_QSFP_ABS_24_31_REG 0x13 +#define CPLD_QSFP_INTR_0_7_REG 0x14 +#define CPLD_QSFP_INTR_8_15_REG 0x15 +#define CPLD_QSFP_INTR_16_23_REG 0x16 +#define CPLD_QSFP_INTR_24_31_REG 0x17 +#define CPLD_SFP_ABS_0_1_REG 0x18 +#define CPLD_SFP_RXLOS_0_1_REG 0x19 +#define CPLD_SFP_TXFLT_0_1_REG 0x1a +#define CPLD_QSFP_MASK_ABS_0_7_REG 0x20 +#define CPLD_QSFP_MASK_ABS_8_15_REG 0x21 +#define CPLD_QSFP_MASK_ABS_16_23_REG 0x22 +#define CPLD_QSFP_MASK_ABS_24_31_REG 0x23 +#define CPLD_QSFP_MASK_INTR_0_7_REG 0x24 +#define CPLD_QSFP_MASK_INTR_8_15_REG 0x25 +#define CPLD_QSFP_MASK_INTR_16_23_REG 0x26 +#define CPLD_QSFP_MASK_INTR_24_31_REG 0x27 +#define CPLD_SFP_MASK_ABS_0_1_REG 0x28 +#define CPLD_SFP_MASK_RXLOS_0_1_REG 0x29 +#define CPLD_SFP_MASK_TXFLT_0_1_REG 0x2A +#define CPLD_QSFP_EVT_ABS_0_7_REG 0x30 +#define CPLD_QSFP_EVT_ABS_8_15_REG 0x31 +#define CPLD_QSFP_EVT_ABS_16_23_REG 0x32 +#define CPLD_QSFP_EVT_ABS_24_31_REG 0x33 +#define CPLD_QSFP_EVT_INTR_0_7_REG 0x34 +#define CPLD_QSFP_EVT_INTR_8_15_REG 0x35 +#define CPLD_QSFP_EVT_INTR_16_23_REG 0x36 +#define CPLD_QSFP_EVT_INTR_24_31_REG 0x37 +#define CPLD_SFP_EVT_ABS_0_1_REG 0x38 +#define CPLD_SFP_EVT_RXLOS_0_1_REG 0x39 +#define CPLD_SFP_EVT_TXFLT_0_1_REG 0x3A +#define CPLD_QSFP_RESET_0_7_REG 0x40 +#define CPLD_QSFP_RESET_8_15_REG 0x41 +#define CPLD_QSFP_RESET_16_23_REG 0x42 +#define CPLD_QSFP_RESET_24_31_REG 0x43 +#define CPLD_QSFP_LPMODE_0_7_REG 0x44 +#define CPLD_QSFP_LPMODE_8_15_REG 0x45 +#define CPLD_QSFP_LPMODE_16_23_REG 0x46 +#define CPLD_QSFP_LPMODE_24_31_REG 0x47 +#define CPLD_SFP_TXDIS_0_1_REG 0x48 +#define CPLD_SFP_TS_0_1_REG 0x49 +#define CPLD_SFP_RS_0_1_REG 0x4A +#define DBG_CPLD_QSFP_ABS_0_7_REG 0xD0 +#define DBG_CPLD_QSFP_ABS_8_15_REG 0xD1 +#define DBG_CPLD_QSFP_ABS_16_23_REG 0xD2 +#define DBG_CPLD_QSFP_ABS_24_31_REG 0xD3 +#define DBG_CPLD_QSFP_INTR_0_7_REG 0xD4 +#define DBG_CPLD_QSFP_INTR_8_15_REG 0xD5 +#define DBG_CPLD_QSFP_INTR_16_23_REG 0xD6 +#define DBG_CPLD_QSFP_INTR_24_31_REG 0xD7 +#define DBG_CPLD_SFP_ABS_0_1_REG 0xD8 +#define DBG_CPLD_SFP_RXLOS_0_1_REG 0xD9 +#define DBG_CPLD_SFP_TXFLT_0_1_REG 0xDA + +//MASK +#define MASK_ALL (0xFF) +#define MASK_NONE (0x00) +#define MASK_0000_0111 (0x07) +#define MASK_0011_1111 (0x3F) +#define MASK_1100_0000 (0xC0) + +/* common manipulation */ +#define INVALID(i, min, max) ((i < min) || (i > max) ? 1u : 0u) + +#endif diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/modules/x86-64-ufispace-s9110-32x-lpc.c b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/modules/x86-64-ufispace-s9110-32x-lpc.c new file mode 100644 index 000000000000..14d7c7ec6e4a --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/modules/x86-64-ufispace-s9110-32x-lpc.c @@ -0,0 +1,981 @@ +/* + * A lpc driver for the ufispace_s9110_32x + * + * Copyright (C) 2022 UfiSpace Technology Corporation. + * Nonodark Huang + * + * Based on ad7414.c + * Copyright 2006 Stefan Roese , DENX Software Engineering + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include + +#if !defined(SENSOR_DEVICE_ATTR_RO) +#define SENSOR_DEVICE_ATTR_RO(_name, _func, _index) \ + SENSOR_DEVICE_ATTR(_name, 0444, _func##_show, NULL, _index) +#endif + +#if !defined(SENSOR_DEVICE_ATTR_RW) +#define SENSOR_DEVICE_ATTR_RW(_name, _func, _index) \ + SENSOR_DEVICE_ATTR(_name, 0644, _func##_show, _func##_store, _index) + +#endif + +#if !defined(SENSOR_DEVICE_ATTR_WO) +#define SENSOR_DEVICE_ATTR_WO(_name, _func, _index) \ + SENSOR_DEVICE_ATTR(_name, 0200, NULL, _func##_store, _index) +#endif + +#define BSP_LOG_R(fmt, args...) \ + _bsp_log (LOG_READ, KERN_INFO "%s:%s[%d]: " fmt "\r\n", \ + __FILE__, __func__, __LINE__, ##args) +#define BSP_LOG_W(fmt, args...) \ + _bsp_log (LOG_WRITE, KERN_INFO "%s:%s[%d]: " fmt "\r\n", \ + __FILE__, __func__, __LINE__, ##args) + +#define _DEVICE_ATTR(_name) \ + &sensor_dev_attr_##_name.dev_attr.attr + +#define BSP_PR(level, fmt, args...) _bsp_log (LOG_SYS, level "[BSP]" fmt "\r\n", ##args) + +#define DRIVER_NAME "x86_64_ufispace_s9110_32x_lpc" + +/* LPC registers */ + +#define REG_BASE_MB 0x700 +#define REG_BASE_EC 0xE300 + +#define REG_NONE 0x00 +//MB CPLD +#define REG_BRD_ID_0 (REG_BASE_MB + 0x00) +#define REG_BRD_ID_1 (REG_BASE_MB + 0x01) +#define REG_CPLD_VERSION (REG_BASE_MB + 0x02) +#define REG_CPLD_ID (REG_BASE_MB + 0x03) +#define REG_CPLD_BUILD (REG_BASE_MB + 0x04) +#define REG_CPLD_CHIP (REG_BASE_MB + 0x05) +#define REG_BRD_EXT_ID (REG_BASE_MB + 0x06) +#define REG_I2C_MUX_RESET (REG_BASE_MB + 0x46) +#define REG_MUX_CTRL (REG_BASE_MB + 0x5C) +#define REG_CPLD1_MISC_CTRL (REG_BASE_MB + 0x5D) +#define REG_CPLD1_MISC_CTRL_2 (REG_BASE_MB + 0x5E) + +//EC +#define REG_MISC_CTRL (REG_BASE_EC + 0x0C) +#define REG_CPU_REV (REG_BASE_EC + 0x17) + +// BMC mailbox +#define REG_TEMP_MAC_HWM (REG_BASE_MB + 0xC0) + +#define MASK_ALL (0xFF) +#define MASK_NONE (0x00) +#define MASK_0000_0011 (0x03) +#define MASK_0000_0100 (0x04) +#define MASK_0000_0111 (0x07) +#define MASK_0001_1000 (0x18) +#define MASK_0010_0000 (0x20) +#define MASK_0011_0111 (0x37) +#define MASK_0011_1111 (0x3F) +#define MASK_0100_0000 (0x40) +#define MASK_1000_0000 (0x80) +#define MASK_1100_0000 (0xC0) + +#define LPC_MDELAY (5) +#define MDELAY_RESET_INTERVAL (100) +#define MDELAY_RESET_FINISH (500) + +/* LPC sysfs attributes index */ +enum lpc_sysfs_attributes { + //MB CPLD + ATT_BRD_ID_0, + ATT_BRD_SKU_ID, + ATT_BRD_ID_1, + ATT_BRD_HW_ID, + ATT_BRD_DEPH_ID, + ATT_BRD_BUILD_ID, + ATT_BRD_BIT_SEL, + ATT_BRD_CPLD_ID_TYPE, + ATT_CPLD_VERSION_MAJOR, + ATT_CPLD_VERSION_MINOR, + ATT_CPLD_ID, + ATT_CPLD_BUILD, + ATT_CPLD_VERSION_H, + ATT_CPLD_CHIP, + ATT_BRD_EXT_ID, + ATT_MUX_RESET_ALL, + ATT_MUX_CTRL, + ATT_UART_CTRL, + ATT_USB_CTRL, + + //EC + ATT_BIOS_BOOT_SEL, + ATT_CPU_REV_HW_REV, + ATT_CPU_REV_DEV_PHASE, + ATT_CPU_REV_BUILD_ID, + + //BMC mailbox + ATT_TEMP_MAC_HWM, + + //BSP + ATT_BSP_VERSION, + ATT_BSP_DEBUG, + ATT_BSP_PR_INFO, + ATT_BSP_PR_ERR, + ATT_BSP_REG, + ATT_BSP_REG_VALUE, + ATT_BSP_GPIO_MAX, + ATT_MAX +}; + +enum data_type { + DATA_HEX, + DATA_DEC, + DATA_S_DEC, + DATA_UNK, +}; + +typedef struct { + u16 reg; + u8 mask; + u8 data_type; +} attr_reg_map_t; + +attr_reg_map_t attr_reg[]= { + + //MB CPLD + [ATT_BRD_ID_0] = {REG_BRD_ID_0 , MASK_ALL , DATA_HEX}, + [ATT_BRD_SKU_ID] = {REG_BRD_ID_0 , MASK_ALL , DATA_DEC}, + [ATT_BRD_ID_1] = {REG_BRD_ID_1 , MASK_ALL , DATA_HEX}, + [ATT_BRD_HW_ID] = {REG_BRD_ID_1 , MASK_0000_0011, DATA_DEC}, + [ATT_BRD_DEPH_ID] = {REG_BRD_ID_1 , MASK_0000_0100, DATA_DEC}, + [ATT_BRD_BUILD_ID] = {REG_BRD_ID_1 , MASK_0001_1000, DATA_DEC}, + [ATT_BRD_BIT_SEL] = {REG_BRD_ID_1 , MASK_0010_0000, DATA_DEC}, + [ATT_BRD_CPLD_ID_TYPE] = {REG_BRD_ID_1 , MASK_1000_0000, DATA_DEC}, + [ATT_CPLD_VERSION_MAJOR] = {REG_CPLD_VERSION , MASK_1100_0000, DATA_DEC}, + [ATT_CPLD_VERSION_MINOR] = {REG_CPLD_VERSION , MASK_0011_1111, DATA_DEC}, + [ATT_CPLD_ID] = {REG_CPLD_ID , MASK_0000_0111, DATA_DEC}, + [ATT_CPLD_BUILD] = {REG_CPLD_BUILD , MASK_ALL , DATA_DEC}, + [ATT_CPLD_VERSION_H] = {REG_NONE , MASK_NONE , DATA_UNK}, + [ATT_CPLD_CHIP] = {REG_CPLD_CHIP , MASK_0000_0011, DATA_DEC}, + [ATT_BRD_EXT_ID] = {REG_BRD_EXT_ID , MASK_0000_0111, DATA_DEC}, + [ATT_MUX_RESET_ALL] = {REG_I2C_MUX_RESET, MASK_0011_1111, DATA_DEC}, + [ATT_MUX_CTRL] = {REG_MUX_CTRL , MASK_ALL , DATA_HEX}, + [ATT_UART_CTRL] = {REG_MUX_CTRL , MASK_0010_0000, DATA_DEC}, + [ATT_USB_CTRL] = {REG_MUX_CTRL , MASK_1000_0000, DATA_DEC}, + + //EC + [ATT_BIOS_BOOT_SEL] = {REG_MISC_CTRL , MASK_0100_0000, DATA_DEC}, + [ATT_CPU_REV_HW_REV] = {REG_CPU_REV , MASK_0000_0011, DATA_DEC}, + [ATT_CPU_REV_DEV_PHASE] = {REG_CPU_REV , MASK_0000_0100, DATA_DEC}, + [ATT_CPU_REV_BUILD_ID] = {REG_CPU_REV , MASK_0001_1000, DATA_DEC}, + + //BMC mailbox + [ATT_TEMP_MAC_HWM] = {REG_TEMP_MAC_HWM , MASK_ALL , DATA_S_DEC}, + + //BSP + [ATT_BSP_VERSION] = {REG_NONE , MASK_NONE , DATA_UNK}, + [ATT_BSP_DEBUG] = {REG_NONE , MASK_NONE , DATA_UNK}, + [ATT_BSP_PR_INFO] = {REG_NONE , MASK_NONE , DATA_UNK}, + [ATT_BSP_PR_ERR] = {REG_NONE , MASK_NONE , DATA_UNK}, + [ATT_BSP_REG] = {REG_NONE , MASK_NONE , DATA_UNK}, + [ATT_BSP_REG_VALUE] = {REG_NONE , MASK_NONE , DATA_HEX}, + [ATT_BSP_GPIO_MAX] = {REG_NONE , MASK_NONE , DATA_DEC}, +}; + +enum bsp_log_types { + LOG_NONE, + LOG_RW, + LOG_READ, + LOG_WRITE, + LOG_SYS +}; + +enum bsp_log_ctrl { + LOG_DISABLE, + LOG_ENABLE +}; + +struct lpc_data_s { + struct mutex access_lock; +}; + +struct lpc_data_s *lpc_data; +char bsp_version[16]=""; +char bsp_debug[2]="0"; +char bsp_reg[8]="0x0"; +u8 enable_log_read = LOG_DISABLE; +u8 enable_log_write = LOG_DISABLE; +u8 enable_log_sys = LOG_ENABLE; +u8 mailbox_inited=0; + +/* reg shift */ +static u8 _shift(u8 mask) +{ + int i=0, mask_one=1; + + for(i=0; i<8; ++i) { + if ((mask & mask_one) == 1) + return i; + else + mask >>= 1; + } + + return -1; +} + +/* reg mask and shift */ +static u8 _mask_shift(u8 val, u8 mask) +{ + int shift=0; + + shift = _shift(mask); + + return (val & mask) >> shift; +} + +static u8 _bit_operation(u8 reg_val, u8 bit, u8 bit_val) +{ + if (bit_val == 0) + reg_val = reg_val & ~(1 << bit); + else + reg_val = reg_val | (1 << bit); + return reg_val; +} + +static u8 _parse_data(char *buf, unsigned int data, u8 data_type) +{ + if(buf == NULL) { + return -1; + } + + if(data_type == DATA_HEX) { + return sprintf(buf, "0x%02x", data); + } else if(data_type == DATA_DEC) { + return sprintf(buf, "%u", data); + } else { + return -1; + } + return 0; +} + +static int _bsp_log(u8 log_type, char *fmt, ...) +{ + if ((log_type==LOG_READ && enable_log_read) || + (log_type==LOG_WRITE && enable_log_write) || + (log_type==LOG_SYS && enable_log_sys) ) { + va_list args; + int r; + + va_start(args, fmt); + r = vprintk(fmt, args); + va_end(args); + + return r; + } else { + return 0; + } +} + +static int _bsp_log_config(u8 log_type) +{ + switch(log_type) { + case LOG_NONE: + enable_log_read = LOG_DISABLE; + enable_log_write = LOG_DISABLE; + break; + case LOG_RW: + enable_log_read = LOG_ENABLE; + enable_log_write = LOG_ENABLE; + break; + case LOG_READ: + enable_log_read = LOG_ENABLE; + enable_log_write = LOG_DISABLE; + break; + case LOG_WRITE: + enable_log_read = LOG_DISABLE; + enable_log_write = LOG_ENABLE; + break; + default: + return -EINVAL; + } + return 0; +} + +static void _outb(u8 data, u16 port) +{ + outb(data, port); + mdelay(LPC_MDELAY); +} + +/* init bmc mailbox, get from BMC team */ +static int bmc_mailbox_init(void) +{ + if (mailbox_inited) { + return mailbox_inited; + } + + //Enable super io writing + _outb(0xa5, 0x2e); + _outb(0xa5, 0x2e); + + //Logic device number + _outb(0x07, 0x2e); + _outb(0x0e, 0x2f); + + //Disable mailbox + _outb(0x30, 0x2e); + _outb(0x00, 0x2f); + + //Set base address bit + _outb(0x60, 0x2e); + _outb(0x07, 0x2f); + _outb(0x61, 0x2e); + _outb(0xc0, 0x2f); + + //Select bit[3:0] of SIRQ + _outb(0x70, 0x2e); + _outb(0x07, 0x2f); + + //Low level trigger + _outb(0x71, 0x2e); + _outb(0x01, 0x2f); + + //Enable mailbox + _outb(0x30, 0x2e); + _outb(0x01, 0x2f); + + //Disable super io writing + _outb(0xaa, 0x2e); + + //Mailbox initial + _outb(0x00, 0x786); + _outb(0x00, 0x787); + + //set mailbox_inited + mailbox_inited = 1; + + return mailbox_inited; +} + +/* get lpc register value */ +static u8 _lpc_reg_read(u16 reg, u8 mask) +{ + u8 reg_val=0x0, reg_mk_shf_val = 0x0; + + mutex_lock(&lpc_data->access_lock); + reg_val = inb(reg); + mutex_unlock(&lpc_data->access_lock); + + reg_mk_shf_val = _mask_shift(reg_val, mask); + + BSP_LOG_R("reg=0x%03x, reg_val=0x%02x, mask=0x%02x, reg_mk_shf_val=0x%02x", reg, reg_val, mask, reg_mk_shf_val); + + return reg_mk_shf_val; +} + +/* get lpc register value */ +static ssize_t lpc_reg_read(u16 reg, u8 mask, char *buf, u8 data_type) +{ + u8 reg_val; + int len=0; + + reg_val = _lpc_reg_read(reg, mask); + + // may need to change to hex value ? + len=_parse_data(buf, reg_val, data_type); + + return len; +} + +/* set lpc register value */ +static ssize_t lpc_reg_write(u16 reg, u8 mask, const char *buf, size_t count, u8 data_type) +{ + u8 reg_val, reg_val_now, shift; + + if (kstrtou8(buf, 0, ®_val) < 0) { + if(data_type == DATA_S_DEC) { + if (kstrtos8(buf, 0, ®_val) < 0) { + return -EINVAL; + } + } else { + return -EINVAL; + } + } + + //apply continuous bits operation if mask is specified, discontinuous bits are not supported + if (mask != MASK_ALL) { + reg_val_now = _lpc_reg_read(reg, MASK_ALL); + //clear bits in reg_val_now by the mask + reg_val_now &= ~mask; + //get bit shift by the mask + shift = _shift(mask); + //calculate new reg_val + reg_val = _bit_operation(reg_val_now, shift, reg_val); + } + + mutex_lock(&lpc_data->access_lock); + + _outb(reg_val, reg); + + mutex_unlock(&lpc_data->access_lock); + + BSP_LOG_W("reg=0x%03x, reg_val=0x%02x, mask=0x%02x", reg, reg_val, mask); + + return count; +} + +/* get bsp value */ +static ssize_t bsp_read(char *buf, char *str) +{ + ssize_t len=0; + + mutex_lock(&lpc_data->access_lock); + len=sprintf(buf, "%s", str); + mutex_unlock(&lpc_data->access_lock); + + BSP_LOG_R("reg_val=%s", str); + + return len; +} + +/* set bsp value */ +static ssize_t bsp_write(const char *buf, char *str, size_t str_len, size_t count) +{ + mutex_lock(&lpc_data->access_lock); + snprintf(str, str_len, "%s", buf); + mutex_unlock(&lpc_data->access_lock); + + BSP_LOG_W("reg_val=%s", str); + + return count; +} + +/* get gpio max value */ +static ssize_t gpio_max_show(struct device *dev, + struct device_attribute *da, + char *buf) +{ + u8 data_type=DATA_UNK; + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + + if (attr->index == ATT_BSP_GPIO_MAX) { + data_type = attr_reg[attr->index].data_type; + return _parse_data(buf, ARCH_NR_GPIOS-1, data_type); + } + return -1; +} + +/* get mb cpld version in human readable format */ +static ssize_t mb_cpld_version_h_show(struct device *dev, + struct device_attribute *da, char *buf) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + + unsigned int attr_major = 0; + unsigned int attr_minor = 0; + unsigned int attr_build = 0; + + switch (attr->index) { + case ATT_CPLD_VERSION_H: + attr_major = ATT_CPLD_VERSION_MAJOR; + attr_minor = ATT_CPLD_VERSION_MINOR; + attr_build = ATT_CPLD_BUILD; + break; + default: + return -1; + } + + return sprintf(buf, "%d.%02d.%03d", _lpc_reg_read(attr_reg[attr_major].reg, attr_reg[attr_major].mask), + _lpc_reg_read(attr_reg[attr_minor].reg, attr_reg[attr_minor].mask), + _lpc_reg_read(attr_reg[attr_build].reg, attr_reg[attr_build].mask)); + +} + +/* get lpc register value */ +static ssize_t lpc_callback_show(struct device *dev, + struct device_attribute *da, char *buf) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + u16 reg = 0; + u8 mask = MASK_NONE; + u8 data_type=DATA_UNK; + + switch (attr->index) { + // MB CPLD + case ATT_BRD_ID_0: + case ATT_BRD_SKU_ID: + case ATT_BRD_ID_1: + case ATT_BRD_HW_ID: + case ATT_BRD_DEPH_ID: + case ATT_BRD_BUILD_ID: + case ATT_BRD_BIT_SEL: + case ATT_BRD_CPLD_ID_TYPE: + case ATT_CPLD_VERSION_MAJOR: + case ATT_CPLD_VERSION_MINOR: + case ATT_CPLD_ID: + case ATT_CPLD_BUILD: + case ATT_CPLD_VERSION_H: + case ATT_CPLD_CHIP: + case ATT_BRD_EXT_ID: + case ATT_MUX_RESET_ALL: + case ATT_MUX_CTRL: + case ATT_UART_CTRL: + case ATT_USB_CTRL: + + // EC + case ATT_BIOS_BOOT_SEL: + case ATT_CPU_REV_HW_REV: + case ATT_CPU_REV_DEV_PHASE: + case ATT_CPU_REV_BUILD_ID: + + //BSP + case ATT_BSP_GPIO_MAX: + reg = attr_reg[attr->index].reg; + mask= attr_reg[attr->index].mask; + data_type = attr_reg[attr->index].data_type; + break; + case ATT_BSP_REG_VALUE: + if (kstrtou16(bsp_reg, 0, ®) < 0) + return -EINVAL; + + mask = MASK_ALL; + break; + default: + return -EINVAL; + } + return lpc_reg_read(reg, mask, buf, data_type); +} + +/* set lpc register value */ +static ssize_t lpc_callback_store(struct device *dev, + struct device_attribute *da, const char *buf, size_t count) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + u16 reg = 0; + u8 mask = MASK_NONE; + u8 data_type=DATA_UNK; + + switch (attr->index) { + //MB CPLD + case ATT_MUX_CTRL: + case ATT_UART_CTRL: + case ATT_USB_CTRL: + + //BMC mailbox + case ATT_TEMP_MAC_HWM: + reg = attr_reg[attr->index].reg; + mask= attr_reg[attr->index].mask; + data_type = attr_reg[attr->index].data_type; + break; + default: + return -EINVAL; + } + + if(attr->index == ATT_TEMP_MAC_HWM) { + bmc_mailbox_init(); + } + + return lpc_reg_write(reg, mask, buf, count, data_type); + +} + +/* get bsp parameter value */ +static ssize_t bsp_callback_show(struct device *dev, + struct device_attribute *da, char *buf) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + char *str=NULL; + + switch (attr->index) { + case ATT_BSP_VERSION: + str = bsp_version; + break; + case ATT_BSP_DEBUG: + str = bsp_debug; + break; + case ATT_BSP_REG: + str = bsp_reg; + break; + default: + return -EINVAL; + } + return bsp_read(buf, str); +} + +/* set bsp parameter value */ +static ssize_t bsp_callback_store(struct device *dev, + struct device_attribute *da, const char *buf, size_t count) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + int str_len=0; + char *str=NULL; + u16 reg = 0; + u8 bsp_debug_u8 = 0; + + switch (attr->index) { + case ATT_BSP_VERSION: + str = bsp_version; + str_len = sizeof(bsp_version); + break; + case ATT_BSP_DEBUG: + if (kstrtou8(buf, 0, &bsp_debug_u8) < 0) { + return -EINVAL; + } else if (_bsp_log_config(bsp_debug_u8) < 0) { + return -EINVAL; + } + + str = bsp_debug; + str_len = sizeof(bsp_debug); + break; + case ATT_BSP_REG: + if (kstrtou16(buf, 0, ®) < 0) + return -EINVAL; + + str = bsp_reg; + str_len = sizeof(bsp_reg); + break; + default: + return -EINVAL; + } + + return bsp_write(buf, str, str_len, count); +} + +static ssize_t bsp_pr_callback_store(struct device *dev, + struct device_attribute *da, const char *buf, size_t count) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + int str_len = strlen(buf); + + if(str_len <= 0) + return str_len; + + switch (attr->index) { + case ATT_BSP_PR_INFO: + BSP_PR(KERN_INFO, "%s", buf); + break; + case ATT_BSP_PR_ERR: + BSP_PR(KERN_ERR, "%s", buf); + break; + default: + return -EINVAL; + } + + return str_len; +} + +/* set mux_reset register value */ +static ssize_t mux_reset_all_store(struct device *dev, + struct device_attribute *da, const char *buf, size_t count) +{ + struct sensor_device_attribute *attr = to_sensor_dev_attr(da); + u16 reg = 0; + u8 mask = MASK_NONE; + u8 val = 0; + u8 mux_reset_reg_val = 0; + static int mux_reset_flag = 0; + + switch (attr->index) { + case ATT_MUX_RESET_ALL: + reg = attr_reg[attr->index].reg; + mask= attr_reg[attr->index].mask; + break; + default: + return -EINVAL; + } + + if (kstrtou8(buf, 0, &val) < 0) + return -EINVAL; + + if (mux_reset_flag == 0) { + if (val == 0) { + mutex_lock(&lpc_data->access_lock); + mux_reset_flag = 1; + BSP_LOG_W("i2c mux reset is triggered..."); + + //reset mux on ports + mux_reset_reg_val = inb(reg); + outb((mux_reset_reg_val & (u8)(~mask)), reg); + BSP_LOG_W("reg=0x%03x, reg_val=0x%02x", reg, mux_reset_reg_val & (u8)(~mask)); + + mdelay(MDELAY_RESET_INTERVAL); + + //unset mux on ports + outb((mux_reset_reg_val | mask), reg); + BSP_LOG_W("reg=0x%03x, reg_val=0x%02x", reg, mux_reset_reg_val | mask); + mdelay(MDELAY_RESET_FINISH); + mux_reset_flag = 0; + mutex_unlock(&lpc_data->access_lock); + } else { + return -EINVAL; + } + } else { + BSP_LOG_W("i2c mux is resetting... (ignore)"); + mutex_lock(&lpc_data->access_lock); + mutex_unlock(&lpc_data->access_lock); + } + return count; +} + +//SENSOR_DEVICE_ATTR - MB +static SENSOR_DEVICE_ATTR_RO(board_id_0 , lpc_callback , ATT_BRD_ID_0); +static SENSOR_DEVICE_ATTR_RO(board_sku_id , lpc_callback , ATT_BRD_SKU_ID); +static SENSOR_DEVICE_ATTR_RO(board_id_1 , lpc_callback , ATT_BRD_ID_1); +static SENSOR_DEVICE_ATTR_RO(board_hw_id , lpc_callback , ATT_BRD_HW_ID); +static SENSOR_DEVICE_ATTR_RO(board_deph_id , lpc_callback , ATT_BRD_DEPH_ID); +static SENSOR_DEVICE_ATTR_RO(board_build_id , lpc_callback , ATT_BRD_BUILD_ID); +static SENSOR_DEVICE_ATTR_RO(board_bit_sel , lpc_callback , ATT_BRD_BIT_SEL); +static SENSOR_DEVICE_ATTR_RO(board_cpld_id_type , lpc_callback , ATT_BRD_CPLD_ID_TYPE); +static SENSOR_DEVICE_ATTR_RO(cpld_version_major , lpc_callback , ATT_CPLD_VERSION_MAJOR); +static SENSOR_DEVICE_ATTR_RO(cpld_version_minor , lpc_callback , ATT_CPLD_VERSION_MINOR); +static SENSOR_DEVICE_ATTR_RO(cpld_id , lpc_callback , ATT_CPLD_ID); +static SENSOR_DEVICE_ATTR_RO(cpld_build , lpc_callback , ATT_CPLD_BUILD); +static SENSOR_DEVICE_ATTR_RO(cpld_version_h , mb_cpld_version_h, ATT_CPLD_VERSION_H); +static SENSOR_DEVICE_ATTR_RO(cpld_chip , lpc_callback , ATT_CPLD_CHIP); +static SENSOR_DEVICE_ATTR_RO(board_ext_id , lpc_callback , ATT_BRD_EXT_ID); +static SENSOR_DEVICE_ATTR_WO(mux_reset_all , mux_reset_all , ATT_MUX_RESET_ALL); +static SENSOR_DEVICE_ATTR_RW(mux_ctrl , lpc_callback , ATT_MUX_CTRL); +static SENSOR_DEVICE_ATTR_RW(uart_ctrl , lpc_callback , ATT_UART_CTRL); +static SENSOR_DEVICE_ATTR_RW(usb_ctrl , lpc_callback , ATT_USB_CTRL); + +//SENSOR_DEVICE_ATTR - EC +static SENSOR_DEVICE_ATTR_RO(bios_boot_sel , lpc_callback , ATT_BIOS_BOOT_SEL); +static SENSOR_DEVICE_ATTR_RO(cpu_rev_hw_rev , lpc_callback , ATT_CPU_REV_HW_REV); +static SENSOR_DEVICE_ATTR_RO(cpu_rev_dev_phase , lpc_callback , ATT_CPU_REV_DEV_PHASE); +static SENSOR_DEVICE_ATTR_RO(cpu_rev_build_id , lpc_callback , ATT_CPU_REV_BUILD_ID); + +//SENSOR_DEVICE_ATTR - BMC mailbox +static SENSOR_DEVICE_ATTR_WO(temp_mac_hwm , lpc_callback , ATT_TEMP_MAC_HWM); + +//SENSOR_DEVICE_ATTR - BSP +static SENSOR_DEVICE_ATTR_RW(bsp_version , bsp_callback , ATT_BSP_VERSION); +static SENSOR_DEVICE_ATTR_RW(bsp_debug , bsp_callback , ATT_BSP_DEBUG); +static SENSOR_DEVICE_ATTR_WO(bsp_pr_info , bsp_pr_callback , ATT_BSP_PR_INFO); +static SENSOR_DEVICE_ATTR_WO(bsp_pr_err , bsp_pr_callback , ATT_BSP_PR_ERR); +static SENSOR_DEVICE_ATTR_RW(bsp_reg , bsp_callback , ATT_BSP_REG); +static SENSOR_DEVICE_ATTR_RO(bsp_reg_value , lpc_callback , ATT_BSP_REG_VALUE); +static SENSOR_DEVICE_ATTR_RO(bsp_gpio_max , gpio_max , ATT_BSP_GPIO_MAX); + +static struct attribute *mb_cpld_attrs[] = { + _DEVICE_ATTR(board_id_0), + _DEVICE_ATTR(board_sku_id), + _DEVICE_ATTR(board_id_1), + _DEVICE_ATTR(board_hw_id), + _DEVICE_ATTR(board_deph_id), + _DEVICE_ATTR(board_build_id), + _DEVICE_ATTR(board_bit_sel), + _DEVICE_ATTR(board_cpld_id_type), + _DEVICE_ATTR(cpld_version_major), + _DEVICE_ATTR(cpld_version_minor), + _DEVICE_ATTR(cpld_id), + _DEVICE_ATTR(cpld_build), + _DEVICE_ATTR(cpld_version_h), + _DEVICE_ATTR(cpld_chip), + _DEVICE_ATTR(board_ext_id), + _DEVICE_ATTR(mux_reset_all), + _DEVICE_ATTR(mux_ctrl), + _DEVICE_ATTR(uart_ctrl), + _DEVICE_ATTR(usb_ctrl), + NULL, +}; + +static struct attribute *ec_attrs[] = { + _DEVICE_ATTR(bios_boot_sel), + _DEVICE_ATTR(cpu_rev_hw_rev), + _DEVICE_ATTR(cpu_rev_dev_phase), + _DEVICE_ATTR(cpu_rev_build_id), + NULL, +}; + + +static struct attribute *bmc_mailbox_attrs[] = { + _DEVICE_ATTR(temp_mac_hwm), + NULL, +}; + +static struct attribute *bsp_attrs[] = { + _DEVICE_ATTR(bsp_version), + _DEVICE_ATTR(bsp_debug), + _DEVICE_ATTR(bsp_pr_info), + _DEVICE_ATTR(bsp_pr_err), + _DEVICE_ATTR(bsp_reg), + _DEVICE_ATTR(bsp_reg_value), + _DEVICE_ATTR(bsp_gpio_max), + NULL, +}; + +static struct attribute_group mb_cpld_attr_grp = { + .name = "mb_cpld", + .attrs = mb_cpld_attrs, +}; + +static struct attribute_group bsp_attr_grp = { + .name = "bsp", + .attrs = bsp_attrs, +}; + +static struct attribute_group ec_attr_grp = { + .name = "ec", + .attrs = ec_attrs, +}; + +static struct attribute_group bmc_mailbox_attr_grp = { + .name = "bmc_mailbox", + .attrs = bmc_mailbox_attrs, +}; + +static void lpc_dev_release( struct device * dev) +{ + return; +} + +static struct platform_device lpc_dev = { + .name = DRIVER_NAME, + .id = -1, + .dev = { + .release = lpc_dev_release, + } +}; + +static int lpc_drv_probe(struct platform_device *pdev) +{ + int i = 0, grp_num = 4; + int err[4] = {0}; + struct attribute_group *grp; + + lpc_data = devm_kzalloc(&pdev->dev, sizeof(struct lpc_data_s), + GFP_KERNEL); + if (!lpc_data) + return -ENOMEM; + + mutex_init(&lpc_data->access_lock); + + for (i=0; idev.kobj, grp); + if (err[i]) { + printk(KERN_ERR "Cannot create sysfs for group %s\n", grp->name); + goto exit; + } else { + continue; + } + } + + return 0; + +exit: + for (i=0; idev.kobj, grp); + if (!err[i]) { + //remove previous successful cases + continue; + } else { + //remove first failed case, then return + return err[i]; + } + } + return 0; +} + +static int lpc_drv_remove(struct platform_device *pdev) +{ + sysfs_remove_group(&pdev->dev.kobj, &mb_cpld_attr_grp); + sysfs_remove_group(&pdev->dev.kobj, &bsp_attr_grp); + sysfs_remove_group(&pdev->dev.kobj, &ec_attr_grp); + sysfs_remove_group(&pdev->dev.kobj, &bmc_mailbox_attr_grp); + return 0; +} + +static struct platform_driver lpc_drv = { + .probe = lpc_drv_probe, + .remove = __exit_p(lpc_drv_remove), + .driver = { + .name = DRIVER_NAME, + }, +}; + +int lpc_init(void) +{ + int err = 0; + + err = platform_driver_register(&lpc_drv); + if (err) { + printk(KERN_ERR "%s(#%d): platform_driver_register failed(%d)\n", + __func__, __LINE__, err); + + return err; + } + + err = platform_device_register(&lpc_dev); + if (err) { + printk(KERN_ERR "%s(#%d): platform_device_register failed(%d)\n", + __func__, __LINE__, err); + platform_driver_unregister(&lpc_drv); + return err; + } + + return err; +} + +void lpc_exit(void) +{ + platform_driver_unregister(&lpc_drv); + platform_device_unregister(&lpc_dev); +} + +MODULE_AUTHOR("Nonodark Huang "); +MODULE_DESCRIPTION("x86_64_ufispace_s9110_32x_lpc driver"); +MODULE_LICENSE("GPL"); + +module_init(lpc_init); +module_exit(lpc_exit); diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/modules/x86-64-ufispace-s9110-32x-sys-eeprom.c b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/modules/x86-64-ufispace-s9110-32x-sys-eeprom.c new file mode 100644 index 000000000000..976ba05052e7 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/modules/x86-64-ufispace-s9110-32x-sys-eeprom.c @@ -0,0 +1,272 @@ +/* + * Copyright (C) 1998, 1999 Frodo Looijaard and + * Philip Edelbrock + * Copyright (C) 2003 Greg Kroah-Hartman + * Copyright (C) 2003 IBM Corp. + * Copyright (C) 2004 Jean Delvare + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* enable dev_dbg print out */ +//#define DEBUG + +#define __STDC_WANT_LIB_EXT1__ 1 +#include +#include +#include +#include +#include +#include +#include + +/* Addresses to scan */ +static const unsigned short normal_i2c[] = { /*0x50, 0x51, 0x52, 0x53, 0x54, + 0x55, 0x56, 0x57,*/ I2C_CLIENT_END }; + +/* Size of EEPROM in bytes */ +#define EEPROM_SIZE 512 + +#define SLICE_BITS (6) +#define SLICE_SIZE (1 << SLICE_BITS) +#define SLICE_NUM (EEPROM_SIZE/SLICE_SIZE) + +/* Each client has this additional data */ +struct eeprom_data { + struct mutex update_lock; + u8 valid; /* bitfield, bit!=0 if slice is valid */ + unsigned long last_updated[SLICE_NUM]; /* In jiffies, 8 slices */ + u8 data[EEPROM_SIZE]; /* Register values */ +}; + + +static void sys_eeprom_update_client(struct i2c_client *client, u8 slice) +{ + struct eeprom_data *data = i2c_get_clientdata(client); + int i, j; + int ret; + int addr; + + mutex_lock(&data->update_lock); + + if (!(data->valid & (1 << slice)) || + time_after(jiffies, data->last_updated[slice] + 300 * HZ)) { + dev_dbg(&client->dev, "Starting eeprom update, slice %u\n", slice); + + addr = slice << SLICE_BITS; + + ret = i2c_smbus_write_byte_data(client, (u8)((addr >> 8) & 0xFF), (u8)(addr & 0xFF)); + /* select the eeprom address */ + if (ret < 0) { + dev_err(&client->dev, "address set failed\n"); + goto exit; + } + + if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_READ_BYTE)) { + goto exit; + } + + for (i = slice << SLICE_BITS; i < (slice + 1) << SLICE_BITS; i+= SLICE_SIZE) { + for (j = i; j < (i+SLICE_SIZE); j++) { + int res; + + res = i2c_smbus_read_byte(client); + if (res < 0) { + goto exit; + } + + data->data[j] = res & 0xFF; + } + } + + data->last_updated[slice] = jiffies; + data->valid |= (1 << slice); + } +exit: + mutex_unlock(&data->update_lock); +} + +static ssize_t sys_eeprom_read(struct file *filp, struct kobject *kobj, + struct bin_attribute *bin_attr, + char *buf, loff_t off, size_t count) +{ + struct i2c_client *client = to_i2c_client(container_of(kobj, struct device, kobj)); + struct eeprom_data *data = i2c_get_clientdata(client); + u8 slice; + + if (off > EEPROM_SIZE) { + return 0; + } + if (off + count > EEPROM_SIZE) { + count = EEPROM_SIZE - off; + } + if (count == 0) { + return 0; + } + + /* Only refresh slices which contain requested bytes */ + for (slice = off >> SLICE_BITS; slice <= (off + count - 1) >> SLICE_BITS; slice++) { + sys_eeprom_update_client(client, slice); + } + + memcpy(buf, &data->data[off], count); + + return count; +} + +static ssize_t sys_eeprom_write(struct file *filp, struct kobject *kobj, + struct bin_attribute *bin_attr, + char *buf, loff_t off, size_t count) +{ + struct i2c_client *client = to_i2c_client(container_of(kobj, struct device, kobj)); + struct eeprom_data *data = i2c_get_clientdata(client); + int ret; + int i; + u8 cmd; + u16 value16; + + dev_dbg(&client->dev, "sys_eeprom_write off=%d, count=%d\n", (int)off, (int)count); + + if (off > EEPROM_SIZE) { + return 0; + } + if (off + count > EEPROM_SIZE) { + count = EEPROM_SIZE - off; + } + if (count == 0) { + return 0; + } + + mutex_lock(&data->update_lock); + + for(i=0; i < count; i++) { + /* write command */ + cmd = (off >> 8) & 0xff; + value16 = off & 0xff; + value16 |= buf[i] << 8; + ret = i2c_smbus_write_word_data(client, cmd, value16); + + if (ret < 0) { + dev_err(&client->dev, "write address failed at %d \n", (int)off); + goto exit; + } + + off++; + + /* need to wait for write complete */ + udelay(10000); + } +exit: + mutex_unlock(&data->update_lock); + /* force to update client when reading */ + for(i=0; i < SLICE_NUM; i++) { + data->last_updated[i] = 0; + } + + return count; +} + +static struct bin_attribute sys_eeprom_attr = { + .attr = { + .name = "eeprom", + .mode = S_IRUGO | S_IWUSR, + }, + .size = EEPROM_SIZE, + .read = sys_eeprom_read, + .write = sys_eeprom_write, +}; + +/* Return 0 if detection is successful, -ENODEV otherwise */ +static int sys_eeprom_detect(struct i2c_client *client, struct i2c_board_info *info) +{ + struct i2c_adapter *adapter = client->adapter; + + /* EDID EEPROMs are often 24C00 EEPROMs, which answer to all + addresses 0x50-0x57, but we only care about 0x51 and 0x55. So decline + attaching to addresses >= 0x56 on DDC buses */ + if (!(adapter->class & I2C_CLASS_SPD) && client->addr >= 0x56) { + return -ENODEV; + } + + if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_READ_BYTE) + && !i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WRITE_BYTE_DATA)) { + return -ENODEV; + } + + strlcpy(info->type, "eeprom", I2C_NAME_SIZE); + + return 0; +} + +static int sys_eeprom_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct eeprom_data *data; + int err; + + if (!(data = kzalloc(sizeof(struct eeprom_data), GFP_KERNEL))) { + err = -ENOMEM; + goto exit; + } + +#ifdef __STDC_LIB_EXT1__ + memset_s(data->data, EEPROM_SIZE, 0xff, EEPROM_SIZE); +#else + memset(data->data, 0xff, EEPROM_SIZE); +#endif + i2c_set_clientdata(client, data); + mutex_init(&data->update_lock); + + /* create the sysfs eeprom file */ + err = sysfs_create_bin_file(&client->dev.kobj, &sys_eeprom_attr); + if (err) { + goto exit_kfree; + } + + return 0; + +exit_kfree: + kfree(data); +exit: + return err; +} + +static int sys_eeprom_remove(struct i2c_client *client) +{ + sysfs_remove_bin_file(&client->dev.kobj, &sys_eeprom_attr); + kfree(i2c_get_clientdata(client)); + + return 0; +} + +static const struct i2c_device_id sys_eeprom_id[] = { + { "sys_eeprom", 0 }, + { } +}; + +static struct i2c_driver sys_eeprom_driver = { + .driver = { + .name = "sys_eeprom", + }, + .probe = sys_eeprom_probe, + .remove = sys_eeprom_remove, + .id_table = sys_eeprom_id, + + .class = I2C_CLASS_DDC | I2C_CLASS_SPD, + .detect = sys_eeprom_detect, + .address_list = normal_i2c, +}; + +module_i2c_driver(sys_eeprom_driver); + +MODULE_AUTHOR("Nonodark Huang "); +MODULE_DESCRIPTION("UfiSpace System EEPROM driver"); +MODULE_LICENSE("GPL"); diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/service/pddf-platform-init.service b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/service/pddf-platform-init.service new file mode 120000 index 000000000000..0fd9f25b6c5e --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/service/pddf-platform-init.service @@ -0,0 +1 @@ +../../../../pddf/i2c/service/pddf-platform-init.service \ No newline at end of file diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/sonic_platform/__init__.py b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/sonic_platform/__init__.py new file mode 100644 index 000000000000..593867d31c9d --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/sonic_platform/__init__.py @@ -0,0 +1,4 @@ +# All the derived classes for PDDF +__all__ = ["platform", "chassis", "sfp", "psu", "thermal", "fan"] +from . import platform + diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/sonic_platform/chassis.py b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/sonic_platform/chassis.py new file mode 100644 index 000000000000..530332cf1506 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/sonic_platform/chassis.py @@ -0,0 +1,191 @@ +#!/usr/bin/env python + +############################################################################# +# PDDF +# Module contains an implementation of SONiC Chassis API +# +############################################################################# + +try: + import time + from sonic_platform_pddf_base.pddf_chassis import PddfChassis + # from sonic_py_common import device_info +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + +NUM_COMPONENT = 4 + +class Chassis(PddfChassis): + """ + PDDF Platform-specific Chassis class + """ + + port_dict = {} + + def __init__(self, pddf_data=None, pddf_plugin_data=None): + PddfChassis.__init__(self, pddf_data, pddf_plugin_data) + self._initialize_components() + + def _initialize_components(self): + from sonic_platform.component import Component + for index in range(NUM_COMPONENT): + component = Component(index) + self._component_list.append(component) + + # Provide the functions/variables below for which implementation is to be overwritten + def get_name(self): + """ + Retrieves the name of the chassis + Returns: + string: The name of the chassis + """ + # return device_info.get_hwsku() + return self._eeprom.platform_name_str() + + def initizalize_system_led(self): + return True + + def get_status_led(self): + return self.get_system_led("SYS_LED") + + def get_change_event(self, timeout=0): + """ + Returns a nested dictionary containing all devices which have + experienced a change at chassis level + Args: + timeout: Timeout in milliseconds (optional). If timeout == 0, + this method will block until a change is detected. + Returns: + (bool, dict): + - bool: True if call successful, False if not; + - dict: A nested dictionary where key is a device type, + value is a dictionary with key:value pairs in the format of + {'device_id':'device_event'}, where device_id is the device ID + for this device and device_event. + The known devices's device_id and device_event was defined as table below. + ----------------------------------------------------------------- + device | device_id | device_event | annotate + ----------------------------------------------------------------- + 'fan' '' '0' Fan removed + '1' Fan inserted + 'sfp' '' '0' Sfp removed + '1' Sfp inserted + '2' I2C bus stuck + '3' Bad eeprom + '4' Unsupported cable + '5' High Temperature + '6' Bad cable + 'voltage' '' '0' Vout normal + '1' Vout abnormal + -------------------------------------------------------------------- + Ex. {'fan':{'0':'0', '2':'1'}, 'sfp':{'11':'0', '12':'1'}, + 'voltage':{'U20':'0', 'U21':'1'}} + Indicates that: + fan 0 has been removed, fan 2 has been inserted. + sfp 11 has been removed, sfp 12 has been inserted. + monitored voltage U20 became normal, voltage U21 became abnormal. + Note: For sfp, when event 3-6 happened, the module will not be avalaible, + XCVRD shall stop to read eeprom before SFP recovered from error status. + """ + + change_event_dict = {"fan": {}, "sfp": {}, "voltage": {}} + + start_time = time.time() + forever = False + + if timeout == 0: + forever = True + elif timeout > 0: + timeout = timeout / float(1000) # Convert to secs + else: + print("get_change_event:Invalid timeout value", timeout) + return False, change_event_dict + + end_time = start_time + timeout + if start_time > end_time: + print( + "get_change_event:" "time wrap / invalid timeout value", + timeout, + ) + return False, change_event_dict # Time wrap or possibly incorrect timeout + try: + while timeout >= 0: + # check for sfp + sfp_change_dict = self.get_transceiver_change_event() + # check for fan + # fan_change_dict = self.get_fan_change_event() + # check for voltage + # voltage_change_dict = self.get_voltage_change_event() + + if sfp_change_dict: + change_event_dict["sfp"] = sfp_change_dict + # change_event_dict["fan"] = fan_change_dict + # change_event_dict["voltage"] = voltage_change_dict + return True, change_event_dict + if forever: + time.sleep(1) + else: + timeout = end_time - time.time() + if timeout >= 1: + time.sleep(1) # We poll at 1 second granularity + else: + if timeout > 0: + time.sleep(timeout) + return True, change_event_dict + except Exception as e: + print(e) + print("get_change_event: Should not reach here.") + return False, change_event_dict + + def get_transceiver_change_event(self): + current_port_dict = {} + ret_dict = {} + + # Check for OIR events and return ret_dict + for index in range(0, self.platform_inventory['num_ports']): + if self._sfp_list[index].get_presence(): + current_port_dict[index] = self.plugin_data["XCVR"]["status"]["inserted"] + else: + current_port_dict[index] = self.plugin_data["XCVR"]["status"]["removed"] + + if len(self.port_dict) == 0: # first time + self.port_dict = current_port_dict + return {} + + if current_port_dict == self.port_dict: + return {} + + # Update reg value + for index, status in current_port_dict.items(): + if self.port_dict[index] != status: + ret_dict[index] = status + #ret_dict[str(index)] = status + self.port_dict = current_port_dict + for index, status in ret_dict.items(): + if int(status) == 1: + pass + #self._sfp_list[int(index)].check_sfp_optoe_type() + return ret_dict + + def get_reboot_cause(self): + """ + Retrieves the cause of the previous reboot + + Returns: + A tuple (string, string) where the first element is a string + containing the cause of the previous reboot. This string must be + one of the predefined strings in this class. If the first string + is "REBOOT_CAUSE_HARDWARE_OTHER", the second string can be used + to pass a description of the reboot cause. + """ + + reboot_cause_path = self.plugin_data['REBOOT_CAUSE']['reboot_cause_file'] + + try: + with open(reboot_cause_path, 'r', errors='replace') as fd: + data = fd.read() + sw_reboot_cause = data.strip() + except IOError: + sw_reboot_cause = "Unknown" + + return ('REBOOT_CAUSE_NON_HARDWARE', sw_reboot_cause) diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/sonic_platform/component.py b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/sonic_platform/component.py new file mode 100644 index 000000000000..1c583079f8c2 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/sonic_platform/component.py @@ -0,0 +1,125 @@ +############################################################################# +# +# Component contains an implementation of SONiC Platform Base API and +# provides the components firmware management function +# +############################################################################# + +try: + import subprocess + from sonic_platform_base.component_base import ComponentBase + from sonic_platform_pddf_base import pddfapi +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + +CPLD_SYSFS = { + "CPLD1": {"major": "cpld1_major_ver", "minor": "cpld1_minor_ver", "build": "cpld1_build"}, + "CPLD2": {"major": "cpld2_major_ver", "minor": "cpld2_minor_ver", "build": "cpld2_build"}, +} + +BMC_CMDS = { + "VER1": "ipmitool mc info | grep 'Firmware Revision' | cut -d':' -f2 | cut -d'.' -f1", + "VER2": "ipmitool mc info | grep 'Firmware Revision' | cut -d':' -f2 | cut -d'.' -f2", + "VER3": "echo $((`ipmitool mc info | grep 'Aux Firmware Rev Info' -A 2 | sed -n '2p'` + 0))", +} + +BIOS_VERSION_PATH = "/sys/class/dmi/id/bios_version" +COMPONENT_LIST= [ + ("CPLD1", "CPLD 1"), + ("CPLD2", "CPLD 2"), + ("BIOS", "Basic Input/Output System"), + ("BMC", "BMC"), +] + +class Component(ComponentBase): + """Platform-specific Component class""" + + DEVICE_TYPE = "component" + + def __init__(self, component_index=0): + self.pddf_obj = pddfapi.PddfApi() + self.index = component_index + self.name = self.get_name() + + def _get_bios_version(self): + # Retrieves the BIOS firmware version + try: + with open(BIOS_VERSION_PATH, 'r') as fd: + bios_version = fd.read() + return bios_version.strip() + except Exception as e: + return None + + def _get_cpld_version(self): + # Retrieves the CPLD firmware version + cpld_version = dict() + for cpld_name, elem in CPLD_SYSFS.items(): + device = "SYSSTATUS" + major = self.pddf_obj.get_attr_name_output(device, elem["major"]) + minor = self.pddf_obj.get_attr_name_output(device, elem["minor"]) + build = self.pddf_obj.get_attr_name_output(device, elem["build"]) + if major and minor and build: + major = int(major['status'].rstrip(),0) + minor = int(minor['status'].rstrip(),0) + build = int(build['status'].rstrip(),0) + cpld_version[cpld_name] = "{}.{:02d}.{:03d}".format(major, minor, build) + else: + cpld_version[cpld_name] = "N/A" + return cpld_version + + def _get_bmc_version(self): + # Retrieves the BMC firmware version + bmc_ver = dict() + for ver in BMC_CMDS: + status, value = subprocess.getstatusoutput(BMC_CMDS[ver]) + if not status: + bmc_ver[ver] = int(value.rstrip()) + else: + return None + + bmc_version = "{}.{}.{}".format(bmc_ver["VER1"], bmc_ver["VER2"], bmc_ver["VER3"]) + + return bmc_version + + def get_name(self): + """ + Retrieves the name of the component + Returns: + A string containing the name of the component + """ + return COMPONENT_LIST[self.index][0] + + def get_description(self): + """ + Retrieves the description of the component + Returns: + A string containing the description of the component + """ + return COMPONENT_LIST[self.index][1] + + def get_firmware_version(self): + """ + Retrieves the firmware version of module + Returns: + string: The firmware versions of the module + """ + fw_version = None + + if self.name == "BIOS": + fw_version = self._get_bios_version() + elif "CPLD" in self.name: + cpld_version = self._get_cpld_version() + fw_version = cpld_version.get(self.name) + elif self.name == "BMC": + fw_version = self._get_bmc_version() + return fw_version + + def install_firmware(self, image_path): + """ + Install firmware to module + Args: + image_path: A string, path to firmware image + Returns: + A boolean, True if install successfully, False if not + """ + raise NotImplementedError diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/sonic_platform/eeprom.py b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/sonic_platform/eeprom.py new file mode 100644 index 000000000000..90ab1c779a48 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/sonic_platform/eeprom.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python + +try: + from sonic_platform_pddf_base.pddf_eeprom import PddfEeprom +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + + +class Eeprom(PddfEeprom): + + def __init__(self, pddf_data=None, pddf_plugin_data=None): + PddfEeprom.__init__(self, pddf_data, pddf_plugin_data) + + # Provide the functions/variables below for which implementation is to be overwritten + + def platform_name_str(self): + (is_valid, results) = self.get_tlv_field(self.eeprom_data, self._TLV_CODE_PLATFORM_NAME) + if not is_valid: + return "N/A" + + return results[2].decode('ascii') \ No newline at end of file diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/sonic_platform/fan.py b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/sonic_platform/fan.py new file mode 100644 index 000000000000..c38ebdedea5b --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/sonic_platform/fan.py @@ -0,0 +1,147 @@ +#!/usr/bin/env python + + +try: + from sonic_platform_pddf_base.pddf_fan import PddfFan +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + + +class Fan(PddfFan): + """PDDF Platform-Specific Fan class""" + + def __init__(self, tray_idx, fan_idx=0, pddf_data=None, pddf_plugin_data=None, is_psu_fan=False, psu_index=0): + # idx is 0-based + PddfFan.__init__(self, tray_idx, fan_idx, pddf_data, pddf_plugin_data, is_psu_fan, psu_index) + + # Provide the functions/variables below for which implementation is to be overwritten + # Since psu_fan airflow direction cant be read from sysfs, it is fixed as 'F2B' or 'intake' + + def get_mfr_id(self): + """ + Retrieves the manufacturer id of the device + + Returns: + string: Manufacturer Id of device + """ + if self.is_psu_fan: + device = "PSU{}".format(self.fans_psu_index) + output = self.pddf_obj.get_attr_name_output(device, "psu_mfr_id") + else: + raise NotImplementedError + + if not output: + return None + + mfr = output['status'] + + # strip_non_ascii + stripped = (c for c in mfr if 0 < ord(c) < 127) + mfr = ''.join(stripped) + + return mfr.rstrip('\n') + + def get_model(self): + """ + Retrieves the model number (or part number) of the device + + Returns: + string: Model/part number of device + """ + if self.is_psu_fan: + device = "PSU{}".format(self.fans_psu_index) + output = self.pddf_obj.get_attr_name_output(device, "psu_model_name") + else: + raise NotImplementedError + + if not output: + return None + + model = output['status'] + + # strip_non_ascii + stripped = (c for c in model if 0 < ord(c) < 127) + model = ''.join(stripped) + + return model.rstrip('\n') + + def get_max_speed(self): + """ + Retrieves the model name + + Returns: + An string, the model name + """ + if self.is_psu_fan: + mfr = self.get_mfr_id() + model = self.get_model() + + max_speed = int(self.plugin_data['PSU']['valmap']['PSU_AC_FAN_MAX_SPEED']) + if mfr and model : + for dev in self.plugin_data['PSU']['psu_support_list']: + if dev['Manufacturer'] == mfr and dev['Name'] == model: + max_speed = int(self.plugin_data['PSU']['valmap'][dev['MaxSpd']]) + break + else: + if self.fan_index == 1: + max_speed = int(self.plugin_data['FAN']['FAN_F_MAX_SPEED']) + else: + max_speed = int(self.plugin_data['FAN']['FAN_R_MAX_SPEED']) + + return max_speed + + def get_presence(self): + """ + Retrieves the presence of the device + Returns: + bool: True if device is present, False if not + """ + if self.is_psu_fan: + attr_name = "psu_present" + device = "PSU{}".format(self.fans_psu_index) + else: + idx = (self.fantray_index-1)*self.platform['num_fans_pertray'] + self.fan_index + attr_name = "fan" + str(idx) + "_present" + device = "FAN-CTRL" + + output = self.pddf_obj.get_attr_name_output(device, attr_name) + if not output: + return False + + + mode = output['mode'] + presence = output['status'].rstrip() + vmap = self.plugin_data['FAN']['present'][mode]['valmap'] + + if presence in vmap: + status = vmap[presence] + else: + status = False + + return status + + def get_speed(self): + """ + Retrieves the speed of fan as a percentage of full speed + + Returns: + An integer, the percentage of full fan speed, in the range 0 (off) + to 100 (full speed) + """ + speed_percentage = 0 + + max_speed = self.get_max_speed() + rpm_speed = self.get_speed_rpm() + + speed_percentage = round((rpm_speed*100)/max_speed) + + return min(speed_percentage, 100) + + def get_target_speed(self): + """ + Retrieves the target (expected) speed of the fan + Returns: + An integer, the percentage of full fan speed, in the range 0 (off) + to 100 (full speed) + """ + return self.get_speed() \ No newline at end of file diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/sonic_platform/fan_drawer.py b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/sonic_platform/fan_drawer.py new file mode 100644 index 000000000000..3b9bb607f632 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/sonic_platform/fan_drawer.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python + + +try: + from sonic_platform_pddf_base.pddf_fan_drawer import PddfFanDrawer +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + + +class FanDrawer(PddfFanDrawer): + """PDDF Platform-Specific Fan-Drawer class""" + + def __init__(self, tray_idx, pddf_data=None, pddf_plugin_data=None): + # idx is 0-based + PddfFanDrawer.__init__(self, tray_idx, pddf_data, pddf_plugin_data) + + # Provide the functions/variables below for which implementation is to be overwritten diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/sonic_platform/platform.py b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/sonic_platform/platform.py new file mode 100644 index 000000000000..406b1179ae1b --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/sonic_platform/platform.py @@ -0,0 +1,25 @@ +#!/usr/bin/env python + +############################################################################# +# PDDF +# Module contains an implementation of SONiC Platform Base API and +# provides the platform information +# +############################################################################# + + +try: + from sonic_platform_pddf_base.pddf_platform import PddfPlatform +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + + +class Platform(PddfPlatform): + """ + PDDF Platform-Specific Platform Class + """ + + def __init__(self): + PddfPlatform.__init__(self) + + # Provide the functions/variables below for which implementation is to be overwritten diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/sonic_platform/psu.py b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/sonic_platform/psu.py new file mode 100644 index 000000000000..4f7e843361d4 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/sonic_platform/psu.py @@ -0,0 +1,38 @@ +#!/usr/bin/env python + + +try: + from sonic_platform_pddf_base.pddf_psu import PddfPsu +except ImportError as e: + raise ImportError (str(e) + "- required module not found") + + +class Psu(PddfPsu): + """PDDF Platform-Specific PSU class""" + + PLATFORM_PSU_CAPACITY = 750 + + def __init__(self, index, pddf_data=None, pddf_plugin_data=None): + PddfPsu.__init__(self, index, pddf_data, pddf_plugin_data) + + # Provide the functions/variables below for which implementation is to be overwritten + def get_power(self): + """ + Retrieves current energy supplied by PSU + + Returns: + A float number, the power in watts, + e.g. 302.6 + """ + + # power is returned in micro watts + return round(float(self.get_voltage()*self.get_current()), 2) + + def get_maximum_supplied_power(self): + """ + Retrieves the maximum supplied power by PSU (or PSU capacity) + Returns: + A float number, the maximum power output in Watts. + e.g. 1200.1 + """ + return float(self.PLATFORM_PSU_CAPACITY) \ No newline at end of file diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/sonic_platform/sfp.py b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/sonic_platform/sfp.py new file mode 100644 index 000000000000..c7919482f69c --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/sonic_platform/sfp.py @@ -0,0 +1,31 @@ +#!/usr/bin/env python + +try: + from sonic_platform_pddf_base.pddf_sfp import PddfSfp +except ImportError as e: + raise ImportError (str(e) + "- required module not found") + + +class Sfp(PddfSfp): + """ + PDDF Platform-Specific Sfp class + """ + + def __init__(self, index, pddf_data=None, pddf_plugin_data=None): + PddfSfp.__init__(self, index, pddf_data, pddf_plugin_data) + self.index = index + + # Provide the functions/variables below for which implementation is to be overwritten + + def get_error_description(self): + """ + Retrives the error descriptions of the SFP module + Returns: + String that represents the current error descriptions of vendor specific errors + In case there are multiple errors, they should be joined by '|', + like: "Bad EEPROM|Unsupported cable" + """ + if not self.get_presence(): + return self.SFP_STATUS_UNPLUGGED + + return self.SFP_STATUS_OK diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/sonic_platform/thermal.py b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/sonic_platform/thermal.py new file mode 100644 index 000000000000..77d6ec7ae886 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/sonic_platform/thermal.py @@ -0,0 +1,17 @@ +#!/usr/bin/env python + + +try: + from sonic_platform_pddf_base.pddf_thermal import PddfThermal +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + + + +class Thermal(PddfThermal): + """PDDF Platform-Specific Thermal class""" + + def __init__(self, index, pddf_data=None, pddf_plugin_data=None, is_psu_thermal=False, psu_index=0): + PddfThermal.__init__(self, index, pddf_data, pddf_plugin_data, is_psu_thermal, psu_index) + + # Provide the functions/variables below for which implementation is to be overwritten diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/sonic_platform_setup.py b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/sonic_platform_setup.py new file mode 100644 index 000000000000..2152c64d420a --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/sonic_platform_setup.py @@ -0,0 +1,27 @@ +from setuptools import setup + +setup( + name='sonic-platform', + version='1.0', + description='SONiC platform API implementation on ufispace platform', + license='Apache 2.0', + author='SONiC Team', + author_email='linuxnetdev@microsoft.com', + url='https://github.com/Azure/sonic-buildimage', + maintainer='Nonodark Huangn', + maintainer_email='nonodark.huang@ufispace.com', + packages=['sonic_platform'], + classifiers=[ + 'Development Status :: 3 - Alpha', + 'Environment :: Plugins', + 'Intended Audience :: Developers', + 'Intended Audience :: Information Technology', + 'Intended Audience :: System Administrators', + 'License :: OSI Approved :: Apache Software License', + 'Natural Language :: English', + 'Operating System :: POSIX :: Linux', + 'Programming Language :: Python :: 3.7', + 'Topic :: Utilities', + ], + keywords='sonic SONiC platform PLATFORM', +) diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/utils/pddf_post_device_create.sh b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/utils/pddf_post_device_create.sh new file mode 100755 index 000000000000..47076d99c4ca --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/utils/pddf_post_device_create.sh @@ -0,0 +1,14 @@ +#!/bin/bash + +#disable bmc watchdog +echo "Disable BMC watchdog" +timeout 3 ipmitool mc watchdog off + +pddf_ledutil setstatusled SYS_LED off +pddf_ledutil setstatusled ID_LED off + +curr_led=$(pddf_ledutil getstatusled SYS_LED) +pddf_ledutil setstatusled SYS_LED green +echo "Set System $curr_led to green" + +echo "PDDF device post-create completed" diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/utils/pddf_post_driver_install.sh b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/utils/pddf_post_driver_install.sh new file mode 100755 index 000000000000..ed2559977e42 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/utils/pddf_post_driver_install.sh @@ -0,0 +1,2 @@ +#!/bin/bash +echo "PDDF driver post-install completed" diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/utils/pddf_pre_device_create.sh b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/utils/pddf_pre_device_create.sh new file mode 100755 index 000000000000..df19dd9338a0 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/utils/pddf_pre_device_create.sh @@ -0,0 +1,74 @@ +#!/bin/bash + +# import sonic env +[ -f /etc/sonic/sonic-environment ] && . /etc/sonic/sonic-environment + +TRUE=0 +FALSE=1 + +PROTO=0 +ALPHA=1 +BETA=2 +PVT=3 + +PLATFORM=${PLATFORM:-x86_64-ufispace_s9110_32x-r0} +PLAT_CONF_PATH="/usr/share/sonic/device/$PLATFORM" +PLAT_CONF_FILE="/usr/share/sonic/device/$PLATFORM/platform.json" +PDDF_DEV_PATH="/usr/share/sonic/device/$PLATFORM/pddf" +PDDF_DEV_FILE="/usr/share/sonic/device/$PLATFORM/pddf/pddf-device.json" +IO_PORT_FILE="/dev/port" + +function _check_filepath { + filepath=$1 + if [ -z "${filepath}" ]; then + echo "[ERR] the ipnut string is empty!!!" + return ${FALSE} + elif [ ! -f "$filepath" ] && [ ! -c "$filepath" ]; then + echo "[ERR] No such file: ${filepath}" + return ${FALSE} + else + return ${TRUE} + fi +} + +if _check_filepath "$IO_PORT_FILE" ; then + MASK=2#00000011 + REG="0x$(xxd -s 0x701 -p -l 1 -c 1 /dev/port)" + HW_REV_ID=$(( $REG & $MASK )) +else + HW_REV_ID=$PVT +fi + +if [ "$HW_REV_ID" = "$BETA" ]; then + + src="$PDDF_DEV_PATH/pddf-device-beta.json" + if _check_filepath $src; then + ln -rsf "$src" "$PDDF_DEV_FILE" + fi + + src="$PLAT_CONF_PATH/platform-beta.json" + if _check_filepath $src; then + ln -rsf $src "$PLAT_CONF_FILE" + fi + +elif [ "$HW_REV_ID" -ge "$PVT" ]; then + src="$PDDF_DEV_PATH/pddf-device-pvt.json" + if _check_filepath $src; then + ln -rsf "$src" "$PDDF_DEV_FILE" + fi + + src="$PLAT_CONF_PATH/platform-pvt.json" + if _check_filepath $src; then + ln -rsf $src "$PLAT_CONF_FILE" + fi +else + src="$PDDF_DEV_PATH/pddf-device-pvt.json" + if _check_filepath $src; then + ln -rsf "$src" "$PDDF_DEV_FILE" + fi + + src="$PLAT_CONF_PATH/platform-pvt.json" + if _check_filepath $src; then + ln -rsf $src "$PLAT_CONF_FILE" + fi +fi diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/utils/pddf_pre_driver_install.sh b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/utils/pddf_pre_driver_install.sh new file mode 100755 index 000000000000..187943061e6c --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/utils/pddf_pre_driver_install.sh @@ -0,0 +1,11 @@ +#!/bin/bash +#rmmod gpio_ich +if [ ! -f /tmp/._pddf_pre_driver_init_completion ]; then + # make sure igb/i40e init in correct order + rmmod i2c-i801 + rmmod i2c_ismt + modprobe -r i2c-i801 + modprobe -r i2c_ismt + date > /tmp/._pddf_pre_driver_init_completion +fi +echo "PDDF driver pre-install completed" diff --git a/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/utils/pddf_switch_svc.py b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/utils/pddf_switch_svc.py new file mode 100755 index 000000000000..c556d77f1c66 --- /dev/null +++ b/platform/broadcom/sonic-platform-modules-ufispace/s9110-32x/utils/pddf_switch_svc.py @@ -0,0 +1,86 @@ +#!/usr/bin/env python +# Script to stop and start the respective platforms default services. +# This will be used while switching the pddf->non-pddf mode and vice versa +import commands + +def check_pddf_support(): + return True + +def stop_platform_svc(): + + ''' + status, output = commands.getstatusoutput("systemctl stop s9110-32x-platform-monitor-fan.service") + if status: + print "Stop s9110-32x-platform-fan.service failed %d"%status + return False + + status, output = commands.getstatusoutput("systemctl stop s9110-32x-platform-monitor-psu.service") + if status: + print "Stop s9110-32x-platform-psu.service failed %d"%status + return False + + status, output = commands.getstatusoutput("systemctl stop s9110-32x-platform-monitor.service") + if status: + print "Stop s9110-32x-platform-init.service failed %d"%status + return False + status, output = commands.getstatusoutput("systemctl disable s9110-32x-platform-monitor.service") + if status: + print "Disable s9110-32x-platform-monitor.service failed %d"%status + return False + ''' + + status, output = commands.getstatusoutput("/usr/local/bin/platform_utility.py deinit") + if status: + print "platform_utility.py deinit command failed %d"%status + return False + + # HACK , stop the pddf-platform-init service if it is active + status, output = commands.getstatusoutput("systemctl stop pddf-platform-init.service") + if status: + print "Stop pddf-platform-init.service along with other platform serives failed %d"%status + return False + + return True + +def start_platform_svc(): + + status, output = commands.getstatusoutput("/usr/local/bin/platform_utility.py init") + if status: + print "platform_utility.py init command failed %d"%status + return False + + ''' + status, output = commands.getstatusoutput("systemctl enable s9110-32x-platform-monitor.service") + if status: + print "Enable s9110-32x-platform-monitor.service failed %d"%status + return False + status, output = commands.getstatusoutput("systemctl start s9110-32x-platform-monitor-fan.service") + if status: + print "Start s9110-32x-platform-monitor-fan.service failed %d"%status + return False + + status, output = commands.getstatusoutput("systemctl start s9110-32x-platform-monitor-psu.service") + if status: + print "Start s9110-32x-platform-monitor-psu.service failed %d"%status + return False + ''' + return True + +def start_platform_pddf(): + + status, output = commands.getstatusoutput("systemctl start pddf-platform-init.service") + if status: + print "Start pddf-platform-init.service failed %d"%status + return False + + return True + +def stop_platform_pddf(): + + status, output = commands.getstatusoutput("systemctl stop pddf-platform-init.service") + if status: + print "Stop pddf-platform-init.service failed %d"%status + return False + + return True + diff --git a/platform/innovium/one-image.mk b/platform/innovium/one-image.mk index 2cae779d71ac..bd63990f511d 100755 --- a/platform/innovium/one-image.mk +++ b/platform/innovium/one-image.mk @@ -7,6 +7,7 @@ $(SONIC_ONE_IMAGE)_IMAGE_TYPE = onie $(SONIC_ONE_IMAGE)_LAZY_INSTALLS += $(CEL_MIDSTONE_200I_PLATFORM_MODULE) $(SONIC_ONE_IMAGE)_LAZY_INSTALLS += $(DELTA_PLATFORM_MODULE) $(SONIC_ONE_IMAGE)_LAZY_INSTALLS += $(NETBERG_AURORA_715_PLATFORM_MODULE) +$(SONIC_ONE_IMAGE)_LAZY_INSTALLS += $(SMCI_SSE_T7132S_PLATFORM_MODULE) $(SONIC_ONE_IMAGE)_LAZY_INSTALLS += $(WISTRON_PLATFORM_MODULE) $(SONIC_ONE_IMAGE)_INSTALLS += $(INVM_DRV) $(SONIC_ONE_IMAGE)_DOCKERS += $(SONIC_INSTALL_DOCKER_IMAGES) diff --git a/platform/innovium/platform-modules-supermicro.mk b/platform/innovium/platform-modules-supermicro.mk new file mode 100644 index 000000000000..f9efee4aedb9 --- /dev/null +++ b/platform/innovium/platform-modules-supermicro.mk @@ -0,0 +1,9 @@ +SMCI_PLATFORM_MODULE_VERSION = 0.1 + +export SMCI_PLATFORM_MODULE_VERSION + +SMCI_SSE_T7132S_PLATFORM_MODULE = platform-modules-sse-t7132s_$(SMCI_PLATFORM_MODULE_VERSION)_$(CONFIGURED_ARCH).deb +$(SMCI_SSE_T7132S_PLATFORM_MODULE)_SRC_PATH = $(PLATFORM_PATH)/sonic-platform-modules-supermicro +$(SMCI_SSE_T7132S_PLATFORM_MODULE)_DEPENDS += $(LINUX_HEADERS) $(LINUX_HEADERS_COMMON) +$(SMCI_SSE_T7132S_PLATFORM_MODULE)_PLATFORM = x86_64-supermicro_sse_t7132s-r0 +SONIC_DPKG_DEBS += $(SMCI_SSE_T7132S_PLATFORM_MODULE) diff --git a/platform/innovium/rules.mk b/platform/innovium/rules.mk index 350ab8ef3f80..03efa70b0def 100755 --- a/platform/innovium/rules.mk +++ b/platform/innovium/rules.mk @@ -1,5 +1,6 @@ include $(PLATFORM_PATH)/invm-sai.mk include $(PLATFORM_PATH)/platform-modules-cel.mk +include $(PLATFORM_PATH)/platform-modules-supermicro.mk #include $(PLATFORM_PATH)/platform-modules-delta.mk include $(PLATFORM_PATH)/platform-modules-wistron.mk #include $(PLATFORM_PATH)/platform-modules-netberg.mk diff --git a/platform/innovium/sonic-platform-modules-cel/midstone-200i/modules/mc24lc64t.c b/platform/innovium/sonic-platform-modules-cel/midstone-200i/modules/mc24lc64t.c index a391056d09a7..002172f587e8 100755 --- a/platform/innovium/sonic-platform-modules-cel/midstone-200i/modules/mc24lc64t.c +++ b/platform/innovium/sonic-platform-modules-cel/midstone-200i/modules/mc24lc64t.c @@ -94,7 +94,7 @@ static int mc24lc64t_probe(struct i2c_client *client, sizeof(struct mc24lc64t_data), GFP_KERNEL))) return -ENOMEM; - drvdata->fake_client = i2c_new_dummy(client->adapter, client->addr + 1); + drvdata->fake_client = i2c_new_dummy_device(client->adapter, client->addr + 1); if (!drvdata->fake_client) return -ENOMEM; diff --git a/platform/innovium/sonic-platform-modules-supermicro/debian/changelog b/platform/innovium/sonic-platform-modules-supermicro/debian/changelog new file mode 100644 index 000000000000..d7863facbb9d --- /dev/null +++ b/platform/innovium/sonic-platform-modules-supermicro/debian/changelog @@ -0,0 +1,5 @@ +sonic-supermicro-platform-modules (0.1) unstable; urgency=low + + * Inital release of SSE-T7132S platform module package. + + -- SuperMicro Team Fri, 22 Oct 2021 17:14:00 +0800 diff --git a/platform/innovium/sonic-platform-modules-supermicro/debian/compat b/platform/innovium/sonic-platform-modules-supermicro/debian/compat new file mode 100644 index 000000000000..ec635144f600 --- /dev/null +++ b/platform/innovium/sonic-platform-modules-supermicro/debian/compat @@ -0,0 +1 @@ +9 diff --git a/platform/innovium/sonic-platform-modules-supermicro/debian/control b/platform/innovium/sonic-platform-modules-supermicro/debian/control new file mode 100644 index 000000000000..1189c7d86766 --- /dev/null +++ b/platform/innovium/sonic-platform-modules-supermicro/debian/control @@ -0,0 +1,16 @@ +Source: sonic-supermicro-platform-modules +Section: main +Priority: extra +Maintainer: SuperMicro Team +Build-Depends: + dh-python, + debhelper (>= 9.0.0), + python3(>=3.5), + python3-setuptools, + bzip2 + +Standards-Version: 3.9.3 +Package: platform-modules-sse-t7132s +Architecture: amd64 +Description: kernel modules for platform devices such as fan, led, sfp + diff --git a/platform/innovium/sonic-platform-modules-supermicro/debian/platform-modules-sse-t7132s.install b/platform/innovium/sonic-platform-modules-supermicro/debian/platform-modules-sse-t7132s.install new file mode 100644 index 000000000000..bf9378db1f10 --- /dev/null +++ b/platform/innovium/sonic-platform-modules-supermicro/debian/platform-modules-sse-t7132s.install @@ -0,0 +1,8 @@ +sse-t7132s/scripts/platform.sh /usr/local/bin +sse-t7132s/scripts/health_checker_thermal.py /usr/local/bin +sse-t7132s/scripts/sysledctl.py /usr/local/bin +sse-t7132s/cfg/t7132s-modules.conf etc/modules-load.d +sse-t7132s/cfg/iTCO_wdt.conf /etc/modprobe.d +sse-t7132s/systemd/platform-modules-sse-t7132s.service etc/systemd/system +sse-t7132s/systemd/sysled.service etc/systemd/system +sse-t7132s/modules/sonic_platform-1.0-py3-none-any.whl usr/share/sonic/device/x86_64-supermicro_sse_t7132s-r0 diff --git a/platform/innovium/sonic-platform-modules-supermicro/debian/platform-modules-sse-t7132s.postinst b/platform/innovium/sonic-platform-modules-supermicro/debian/platform-modules-sse-t7132s.postinst new file mode 100644 index 000000000000..fc0521a672e4 --- /dev/null +++ b/platform/innovium/sonic-platform-modules-supermicro/debian/platform-modules-sse-t7132s.postinst @@ -0,0 +1,14 @@ +# postinst script for SSE-T7132S + +# Enable SuperMicro SSE-T7132S +depmod -a +modprobe -r iTCO_wdt +modprobe -r t7132s +modprobe t7132s +systemctl enable platform-modules-sse-t7132s.service +systemctl start platform-modules-sse-t7132s.service +systemctl enable sysled.service + + +#DEBHELPER# + diff --git a/platform/innovium/sonic-platform-modules-supermicro/debian/rules b/platform/innovium/sonic-platform-modules-supermicro/debian/rules new file mode 100644 index 000000000000..1d733f22f4d6 --- /dev/null +++ b/platform/innovium/sonic-platform-modules-supermicro/debian/rules @@ -0,0 +1,39 @@ +#!/usr/bin/make -f + +export INSTALL_MOD_DIR:=extra + +KVERSION ?= $(shell uname -r) +KERNEL_SRC := /lib/modules/$(KVERSION) +MOD_SRC_DIR:= $(shell pwd) +MODULE_DIRS:= sse-t7132s + +%: + dh $@ + +override_dh_auto_build: + (for mod in $(MODULE_DIRS); do \ + make -C $(KERNEL_SRC)/build M=$(MOD_SRC_DIR)/$${mod}/modules; \ + cd $(MOD_SRC_DIR)/$${mod}; \ + python3 setup.py bdist_wheel -d $(MOD_SRC_DIR)/$${mod}/modules; \ + cd $(MOD_SRC_DIR); \ + done) + +override_dh_auto_install: + (for mod in $(MODULE_DIRS); do \ + dh_installdirs -pplatform-modules-$${mod} \ + $(KERNEL_SRC)/$(INSTALL_MOD_DIR); \ + cp $(MOD_SRC_DIR)/$${mod}/modules/*.ko \ + debian/platform-modules-$${mod}/$(KERNEL_SRC)/$(INSTALL_MOD_DIR); \ + done) + +override_dh_usrlocal: + +override_dh_clean: + dh_clean + (for mod in $(MODULE_DIRS); do \ + make -C $(KERNEL_SRC)/build M=$(MOD_SRC_DIR)/$${mod}/modules clean; \ + rm -f $(MOD_SRC_DIR)/$${mod}/modules/*.whl; \ + rm -rf $(MOD_SRC_DIR)/$${mod}/build; \ + rm -rf $(MOD_SRC_DIR)/$${mod}/*.egg-info; \ + done) + diff --git a/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/cfg/iTCO_wdt.conf b/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/cfg/iTCO_wdt.conf new file mode 100644 index 000000000000..99ded4c32206 --- /dev/null +++ b/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/cfg/iTCO_wdt.conf @@ -0,0 +1 @@ +blacklist iTCO_wdt diff --git a/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/cfg/t7132s-modules.conf b/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/cfg/t7132s-modules.conf new file mode 100644 index 000000000000..ffb5b98feb4a --- /dev/null +++ b/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/cfg/t7132s-modules.conf @@ -0,0 +1,16 @@ +# /etc/modules: kernel modules to load at boot time. +# +# This file contains the names of kernel modules that should be loaded +# at boot time, one per line. Lines beginning with "#" are ignored. + +i2c-i801 +i2c-isch +i2c-ismt +i2c-dev +i2c-mux +i2c-smbus +i2c-mux-gpio +i2c-mux-pca954x +ipmi-devintf +ast +t7132s \ No newline at end of file diff --git a/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/modules/Makefile b/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/modules/Makefile new file mode 100644 index 000000000000..7288a5e59c2c --- /dev/null +++ b/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/modules/Makefile @@ -0,0 +1 @@ +obj-m := t7132s.o diff --git a/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/modules/t7132s.c b/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/modules/t7132s.c new file mode 100755 index 000000000000..2bc83f5b3a7a --- /dev/null +++ b/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/modules/t7132s.c @@ -0,0 +1,1706 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include /* For the watchdog specific items */ +#define REG_LACKSR 0x00 +#define LACKSR_CLKDIV 0x8 +#define LACKSR_CLKSEL (1 << 8) +#define LACKSR_DIVEN (1 << 10) +#define LACKSR_CLKODR (1 << 12) +#define LACKSR_CLKOEN (1 << 13) +#define LACKSR_ALERA (1 << 14) + +#define REG_LAS0CFGR 0x00C +#define REG_LAS0TIMR 0x010 +#define REG_LAS0ADDR 0x014 +#define REG_LAS1CFGR 0x018 +#define REG_LAS1TIMR 0x01C +#define REG_LAS1ADDR 0x020 +#define LASCFGR_INT_P (1 << 0) +#define LASCFGR_INT_L (1 << 1) +#define LASCFGR_DRQ_P (1 << 2) +#define LASCFGR_DAK_P (1 << 3) +#define LASCFGR_LSER (1 << 4) +#define LASCFGR_ENDIAN (1 << 5) +#define LASCFGR_BW16 (1 << 6) +#define REG_LIEMR 0x024 +#define LIEMR_RDYPOL (1 << 4) +#define LIEMR_ALEPOL (1 << 5) +#define LIEMR_SYNCBUS (1 << 6) +#define LIEMR_MULTBUS (1 << 7) +#define LIEMR_DMA0EN (1 << 8) +#define LIEMR_DMA1EN (1 << 9) +#define LIEMR_LRST (1 << 14) +#define LIEMR_SRST (1 << 15) +#define LIEMR_L0EINTEN (1 << 16) +#define LIEMR_L0RTOIEN (1 << 17) +#define LIEMR_L1EINTEN (1 << 18) +#define LIEMR_L1RTOIEN (1 << 19) +#define LIEMR_D0DIEN (1 << 24) +#define LIEMR_D0AIEN (1 << 25) +#define LIEMR_D1DIEN (1 << 26) +#define LIEMR_D1AIEN (1 << 27) + +#define DRIVER_NAME "switchboard" +#define DEVICE_NAME "fwupgrade" +#define CLASS_NAME "t7132s_cpld" +#define SFF_PORT_TOTAL 34 +#define QSFP_PORT_TOTAL 32 +#define SFP_PORT_TOTAL 2 + +/* Refer to SSE_T7132S_CPLD_spec_0820.docx for more details */ +/* Switch model ID */ +#define CPLD1_REG_SW_ID 0x1 +/* HW/CPLD version */ +#define CPLD1_REG_HWREV 0x2 +/* Power sequence module status */ +#define CPLD1_REG_PWR_GOOD 0x3 +/* Voltage Regulator Module ALERT/Thermal */ +#define CPLD1_REG_VRM 0x4 +/* Enable/ Reset misc. devices */ +#define CPLD1_REG_DEV_STATE_1 0x5 +/* Enable/ Reset misc. devices */ +#define CPLD1_REG_DEV_STATE_2 0x6 +/* System reset records */ +#define CPLD1_REG_SYS_RESET_REC 0x9 +/* PCA9548 I2C bus switch RSTn */ +#define CPLD1_REG_MUX_STATE 0xB +/* Transceiver Power Enable */ +#define CPLD1_REG_X_PWR_EN_1 0xC +/* Transceiver Power Enable */ +#define CPLD1_REG_X_PWR_EN_2 0xD +/* Transceiver Power Good */ +#define CPLD1_REG_X_PWR_GOOD_1 0xE +/* Transceiver Power Good */ +#define CPLD1_REG_X_PWR_GOOD_2 0xF +/* Watch Dog Timer maximum count setting by seconds */ +#define CPLD1_REG_WDT_MAX_COUNT_1 0x22 +#define CPLD1_REG_WDT_MAX_COUNT_2 0x23 +/* Watch Dog Timer current count value 16 bits */ +#define CPLD1_REG_WDT_CUR_COUNT_1 0x24 +#define CPLD1_REG_WDT_CUR_COUNT_2 0x25 +/* Version as BMC I2C Registers */ +#define CPLD1_REG_VER_BMC_I2C_1 0xF0 +#define CPLD1_REG_VER_BMC_I2C_2 0xF1 +#define CPLD1_REG_VER_BMC_I2C_3 0xF2 +#define CPLD1_REG_VER_BMC_I2C_4 0xF3 +/* CPLD JED Released Date */ +#define CPLD1_REG_JED_REL_MONTH 0xFE +#define CPLD1_REG_JED_REL_DAY 0xFF + +/* HW/CPLD version */ +#define CPLD2_REG_HWREV 0x2 +/* System Ready/Reset Status */ +#define CPLD2_REG_SYSRDY_RESET_STATUS 0x3 +/* All xcvr LED control */ +#define CPLD2_REG_ALL_LED_CTRL 0x4 +/* Version as BMC I2C Registers */ +#define CPLD2_REG_VER_BMC_I2C_1 0xF0 +#define CPLD2_REG_VER_BMC_I2C_2 0xF1 +#define CPLD2_REG_VER_BMC_I2C_3 0xF2 +#define CPLD2_REG_VER_BMC_I2C_4 0xF3 +/* CPLD JED Released Date */ +#define CPLD2_REG_JED_REL_MONTH 0xFE +#define CPLD2_REG_JED_REL_DAY 0xFF + +#define QSFP_T_RESET_LOf 0x10 +#define QSFP_T_RESET_HIf 0x11 + +#define QSFP_T_LPMODE_LOf 0x12 +#define QSFP_T_LPMODE_HIf 0x13 + +#define QSFP_T_INT_LOf 0x14 +#define QSFP_T_INT_HIf 0x15 + +#define QSFP_T_MODPRS_LOf 0x16 +#define QSFP_T_MODPRS_HIf 0x17 + +#define QSFP_B_RESET_LOf 0x18 +#define QSFP_B_RESET_HIf 0x19 + +#define QSFP_B_LPMODE_LOf 0x1A +#define QSFP_B_LPMODE_HIf 0x1B + +#define QSFP_B_INT_LOf 0x1C +#define QSFP_B_INT_HIf 0x1D + +#define QSFP_B_MODPRS_LOf 0x1E +#define QSFP_B_MODPRS_HIf 0x1F + +#define QSFP_REG_READ(_pbmp_, _reg_, _base_) \ + do { \ + _pbmp_ = readb(_base_ + _reg_##_HIf) | \ + (readb(_base_ + _reg_##_LOf) << 8); \ + } while (0); + +#define QSFP_REG_WRITE(_pbmp_, _reg_, _base_) \ + do { \ + writeb((_pbmp_ & 0x00ff), \ + _base_ + _reg_##_HIf); \ + writeb(((_pbmp_ >> 8) & 0x00ff), \ + _base_ + _reg_##_LOf); \ + } while (0); + +enum PORT_TYPE { NONE, QSFP, SFP }; + +struct t7132s_cpld { + struct mutex lock; + unsigned char __iomem *cpld_base; + unsigned char __iomem *cpld2_base; + struct device *sff_devices[SFF_PORT_TOTAL]; + struct i2c_client *sff_i2c_clients[SFF_PORT_TOTAL]; +}; + +static struct t7132s_cpld *cpld_data; +static struct class *cpld_class = NULL; + +enum i2c_adapter_type { + I2C_ADAPTER_I801 = 0, + I2C_ADAPTER_ISMT, + I2C_ADAPTER_CP2112, + I2C_ADAPTER_PCA954X +}; + +const char *bms_i2c_adapter_names[] = { + "SMBus I801 adapter", + "SMBus iSMT adapter", + "CP2112 SMBus Bridge", + "PCA954X Mux" }; + +struct i2c_topo_node { + int adapter_type; + int parent_index; + int chan_id; + struct i2c_board_info entry; + struct i2c_client *client; +}; + +static struct i2c_topo_node i2c_topo[] = { + { I2C_ADAPTER_CP2112, -1, -1, { I2C_BOARD_INFO("pca9548", 0x70) }, NULL }, + { I2C_ADAPTER_PCA954X, 0, 0, { I2C_BOARD_INFO("pca9548", 0x71) }, NULL }, + { I2C_ADAPTER_PCA954X, 0, 2, { I2C_BOARD_INFO("pca9548", 0x72) }, NULL }, + { I2C_ADAPTER_PCA954X, 0, 1, { I2C_BOARD_INFO("pca9548", 0x73) }, NULL }, + { I2C_ADAPTER_PCA954X, 0, 3, { I2C_BOARD_INFO("pca9548", 0x74) }, NULL }, + { I2C_ADAPTER_PCA954X, 0, 4, { I2C_BOARD_INFO("pca9548", 0x75) }, NULL }, + { I2C_ADAPTER_PCA954X, 5, 3, { I2C_BOARD_INFO("24c64", 0x53) }, NULL }, +}; + +static struct i2c_board_info sff_eeprom_info[] = { + { I2C_BOARD_INFO("optoe3", 0x50) }, + { I2C_BOARD_INFO("optoe2", 0x50) } +}; + +struct sff_device_data { + int portid; + enum PORT_TYPE port_type; + int parent_index; + int chan_id; +}; + +struct sff_device_data sff_device_tbl[SFF_PORT_TOTAL] = { + { 1, QSFP, 1, 0 }, { 2, QSFP, 3, 3 }, { 3, QSFP, 1, 1 }, + { 4, QSFP, 3, 2 }, { 5, QSFP, 1, 2 }, { 6, QSFP, 3, 1 }, + { 7, QSFP, 1, 3 }, { 8, QSFP, 3, 0 }, { 9, QSFP, 1, 4 }, + { 10, QSFP, 3, 7 }, { 11, QSFP, 1, 5 }, { 12, QSFP, 3, 6 }, + { 13, QSFP, 1, 6 }, { 14, QSFP, 3, 5 }, { 15, QSFP, 1, 7 }, + { 16, QSFP, 3, 4 }, { 17, QSFP, 2, 0 }, { 18, QSFP, 4, 3 }, + { 19, QSFP, 2, 1 }, { 20, QSFP, 4, 2 }, { 21, QSFP, 2, 2 }, + { 22, QSFP, 4, 1 }, { 23, QSFP, 2, 3 }, { 24, QSFP, 4, 0 }, + { 25, QSFP, 2, 4 }, { 26, QSFP, 4, 7 }, { 27, QSFP, 2, 5 }, + { 28, QSFP, 4, 6 }, { 29, QSFP, 2, 6 }, { 30, QSFP, 4, 5 }, + { 31, QSFP, 2, 7 }, { 32, QSFP, 4, 4 }, { 1, SFP, 5, 0 }, + { 2, SFP, 5, 1 }, +}; + +#define WATCHDOG_TIMEOUT 30 /* 30 sec default heartbeat */ + +static struct watchdog_device *pwddev; + +static const struct watchdog_info ident = { + .options = WDIOF_SETTIMEOUT | + WDIOF_KEEPALIVEPING | + WDIOF_MAGICCLOSE, + .firmware_version = 0, + .identity = "t7132s_wdt", +}; + +/* used to access CPLD register not defined in this driver with sys filesystem */ +uint8_t cpld_testee_offset[2] = {0, 0}; + +static ssize_t swid_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + uint8_t data = 0; + int err; + char *ptr = (cpld_data->cpld_base + CPLD1_REG_SW_ID); + + mutex_lock(&cpld_data->lock); + data = readb(cpld_data->cpld_base + CPLD1_REG_SW_ID); + mutex_unlock(&cpld_data->lock); + + return sprintf(buf, "0x%2.2x\n", data); +} +struct device_attribute dev_attr_swid = __ATTR(swid, 0400, swid_show, NULL); + +static ssize_t hwrev_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + uint8_t data = 0; + int err; + char *ptr = (cpld_data->cpld_base + CPLD1_REG_HWREV); + + mutex_lock(&cpld_data->lock); + data = readb(cpld_data->cpld_base + CPLD1_REG_HWREV); + mutex_unlock(&cpld_data->lock); + + return sprintf(buf, "0x%2.2x\n", data); +} +struct device_attribute dev_attr_hwrev = __ATTR(hw_rev, 0400, hwrev_show, NULL); + +static ssize_t pwrgood_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + uint8_t data = 0; + int err; + + mutex_lock(&cpld_data->lock); + data = readb(cpld_data->cpld_base + CPLD1_REG_PWR_GOOD); + mutex_unlock(&cpld_data->lock); + + return sprintf(buf, "0x%2.2x\n", data); +} +struct device_attribute dev_attr_pwrgood = + __ATTR(pwr_good, 0400, pwrgood_show, NULL); + +static ssize_t vrm_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + uint8_t data = 0; + int err; + + mutex_lock(&cpld_data->lock); + data = readb(cpld_data->cpld_base + CPLD1_REG_VRM); + mutex_unlock(&cpld_data->lock); + + return sprintf(buf, "0x%2.2x\n", data); +} +struct device_attribute dev_attr_vrm = __ATTR(vrm, 0400, vrm_show, NULL); + +static ssize_t devstate_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + uint8_t data = 0; + uint8_t data2 = 0; + long value = 0; + int err; + + mutex_lock(&cpld_data->lock); + data = readb(cpld_data->cpld_base + CPLD1_REG_DEV_STATE_1); + data2 = readb(cpld_data->cpld_base + CPLD1_REG_DEV_STATE_2); + value = data; + value |= (data2 << 8); + mutex_unlock(&cpld_data->lock); + + return sprintf(buf, "0x%4.4lx\n", value); +} +static ssize_t devstate_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + ssize_t status = 0; + long value = 0; + uint8_t data = 0; + uint8_t data2 = 0; + + mutex_lock(&cpld_data->lock); + status = kstrtol(buf, 0, &value); + if (status == 0) { + data = value & 0xff; + data2 = (value & 0xff00) >> 8; + writeb(data, cpld_data->cpld_base + CPLD1_REG_DEV_STATE_1); + writeb(data2, cpld_data->cpld_base + CPLD1_REG_DEV_STATE_2); + status = count; + } + mutex_unlock(&cpld_data->lock); + + return status; +} +struct device_attribute dev_attr_devstate = + __ATTR(dev_state, 0600, devstate_show, devstate_store); + +static ssize_t wdtmax_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + uint8_t data1 = 0; + uint8_t data2 = 0; + long value = 0; + + mutex_lock(&cpld_data->lock); + data1 = readb(cpld_data->cpld_base + CPLD1_REG_WDT_MAX_COUNT_1); + data2 = readb(cpld_data->cpld_base + CPLD1_REG_WDT_MAX_COUNT_2); + value = (data2 << 8) | data1; + mutex_unlock(&cpld_data->lock); + + return sprintf(buf, "0x%4.4lx\n", value); +} +static ssize_t wdtmax_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + ssize_t status = 0; + long value = 0; + uint8_t data1; + uint8_t data2; + + mutex_lock(&cpld_data->lock); + status = kstrtol(buf, 0, &value); + if (status == 0) { + data1 = value & 0xff; + data2 = (value & 0xff00) >> 8; + writeb(data1, cpld_data->cpld_base + CPLD1_REG_WDT_MAX_COUNT_1); + writeb(data2, cpld_data->cpld_base + CPLD1_REG_WDT_MAX_COUNT_2); + status = count; + } + mutex_unlock(&cpld_data->lock); + + return status; +} +struct device_attribute dev_attr_wdtmax = + __ATTR(wdt_max, 0600, wdtmax_show, wdtmax_store); + +static ssize_t wdtcount_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + uint8_t data1 = 0; + uint8_t data2 = 0; + long value = 0; + + mutex_lock(&cpld_data->lock); + data1 = readb(cpld_data->cpld_base + CPLD1_REG_WDT_CUR_COUNT_1); + data2 = readb(cpld_data->cpld_base + CPLD1_REG_WDT_CUR_COUNT_2); + value = (data2 << 8) | data1; + mutex_unlock(&cpld_data->lock); + + return sprintf(buf, "0x%4.4lx\n", value); +} +struct device_attribute dev_attr_wdtcount = + __ATTR(wdt_count, 0400, wdtcount_show, NULL); + +static ssize_t sysrst_rec_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + uint8_t data = 0; + int err; + + mutex_lock(&cpld_data->lock); + data = readb(cpld_data->cpld_base + CPLD1_REG_SYS_RESET_REC); + mutex_unlock(&cpld_data->lock); + + return sprintf(buf, "0x%2.2x\n", data); +} +static ssize_t sysrst_rec_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + ssize_t status = 0; + uint8_t data; + + mutex_lock(&cpld_data->lock); + status = kstrtou8(buf, 0, &data); + + if (status == 0) { + writeb(data, cpld_data->cpld_base + CPLD1_REG_SYS_RESET_REC); + status = count; + } + mutex_unlock(&cpld_data->lock); + + return status; +} +struct device_attribute dev_attr_sysrst_rec = + __ATTR(sysrst_rec, 0600, sysrst_rec_show, sysrst_rec_store); + +static ssize_t muxstate_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + uint8_t data = 0; + int err; + + mutex_lock(&cpld_data->lock); + data = readb(cpld_data->cpld_base + CPLD1_REG_MUX_STATE); + mutex_unlock(&cpld_data->lock); + + return sprintf(buf, "0x%2.2x\n", data); +} +static ssize_t muxstate_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + ssize_t status = 0; + uint8_t data; + + mutex_lock(&cpld_data->lock); + status = kstrtou8(buf, 0, &data); + if (status == 0) { + writeb(data, cpld_data->cpld_base + CPLD1_REG_MUX_STATE); + status = count; + } + mutex_unlock(&cpld_data->lock); + + return status; +} +struct device_attribute dev_attr_muxstate = + __ATTR(i2c_mux_state, 0600, muxstate_show, muxstate_store); + +static ssize_t xcvr_pwrstate_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + uint8_t data = 0; + uint8_t data2 = 0; + long value = 0; + int err; + + mutex_lock(&cpld_data->lock); + data = readb(cpld_data->cpld_base + CPLD1_REG_X_PWR_EN_2); + data2 = readb(cpld_data->cpld_base + CPLD1_REG_X_PWR_EN_1); + value = data; + value |= (data2 << 8); + mutex_unlock(&cpld_data->lock); + + return sprintf(buf, "0x%2.2x\n", value); +} +static ssize_t xcvr_pwrstate_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + ssize_t status = 0; + long value = 0; + uint8_t data = 0; + uint8_t data2 = 0; + + mutex_lock(&cpld_data->lock); + status = kstrtol(buf, 0, &value); + if (status == 0) { + data = value & 0xff; + data2 = (value & 0xff00) >> 8; + writeb(data, cpld_data->cpld_base + CPLD1_REG_X_PWR_EN_2); + writeb(data2, cpld_data->cpld_base + CPLD1_REG_X_PWR_EN_1); + status = count; + } + mutex_unlock(&cpld_data->lock); + + return status; +} +struct device_attribute dev_attr_xcvr_pwrstate = + __ATTR(xcvr_pwr_state, 0600, xcvr_pwrstate_show, xcvr_pwrstate_store); + +static ssize_t xcvr_pwrgood_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + uint8_t data = 0; + uint8_t data2 = 0; + long value = 0; + int err; + + mutex_lock(&cpld_data->lock); + data = readb(cpld_data->cpld_base + CPLD1_REG_X_PWR_GOOD_2); + data2 = readb(cpld_data->cpld_base + CPLD1_REG_X_PWR_GOOD_1); + value = data; + value |= (data2 << 8); + mutex_unlock(&cpld_data->lock); + + return sprintf(buf, "0x%2.2x\n", value); +} +struct device_attribute dev_attr_xcvr_pwrgood = + __ATTR(xcvr_pwr_good, 0400, xcvr_pwrgood_show, NULL); + +static ssize_t cpld1_ver_bmc_i2c_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + uint8_t data = 0; + uint8_t data2 = 0; + uint8_t data3 = 0; + uint8_t data4 = 0; + long value = 0; + int err; + + mutex_lock(&cpld_data->lock); + data = readb(cpld_data->cpld_base + CPLD1_REG_VER_BMC_I2C_4); + data2 = readb(cpld_data->cpld_base + CPLD1_REG_VER_BMC_I2C_3); + data3 = readb(cpld_data->cpld_base + CPLD1_REG_VER_BMC_I2C_2); + data4 = readb(cpld_data->cpld_base + CPLD1_REG_VER_BMC_I2C_1); + value = data; + value |= (data2 << 8); + value |= (data3 << 16); + value |= (data4 << 24); + mutex_unlock(&cpld_data->lock); + + return sprintf(buf, "0x%8.8lx\n", value); +} +struct device_attribute dev_attr_cpld1_ver_bmc_i2c = + __ATTR(ver_bmc_i2c, 0444, cpld1_ver_bmc_i2c_show, NULL); + +static ssize_t cpld1_jed_rel_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + uint8_t data = 0; + uint8_t data2 = 0; + long value = 0; + int err; + + mutex_lock(&cpld_data->lock); + data = readb(cpld_data->cpld_base + CPLD1_REG_JED_REL_DAY); + data2 = readb(cpld_data->cpld_base + CPLD1_REG_JED_REL_MONTH); + value = data; + value |= (data2 << 8); + mutex_unlock(&cpld_data->lock); + + return sprintf(buf, "0x%4.4lx\n", value); +} +struct device_attribute dev_attr_cpld1_jed_rel = + __ATTR(jed_rel, 0400, cpld1_jed_rel_show, NULL); + +static ssize_t cpld1_testee_offset_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + return sprintf(buf, "0x%2.2x\n", cpld_testee_offset[0]); +} +static ssize_t cpld1_testee_offset_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + ssize_t status = 0; + uint8_t data; + + status = kstrtou8(buf, 0, &data); + if (status == 0) { + cpld_testee_offset[0] = data; + status = count; + } + + return status; +} +struct device_attribute dev_attr_cpld1_testee_offset = + __ATTR(testee_offset, 0600, cpld1_testee_offset_show, cpld1_testee_offset_store); + +static ssize_t cpld1_testee_value_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + uint8_t data = 0; + int err; + + mutex_lock(&cpld_data->lock); + data = readb(cpld_data->cpld_base + cpld_testee_offset[0]); + mutex_unlock(&cpld_data->lock); + + return sprintf(buf, "0x%2.2x\n", data); +} +static ssize_t cpld1_testee_value_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + ssize_t status = 0; + uint8_t data; + + mutex_lock(&cpld_data->lock); + status = kstrtou8(buf, 0, &data); + if (status == 0) { + writeb(data, cpld_data->cpld_base + cpld_testee_offset[0]); + status = count; + } + mutex_unlock(&cpld_data->lock); + + return status; +} +struct device_attribute dev_attr_cpld1_testee_value = + __ATTR(testee_value, 0600, cpld1_testee_value_show, cpld1_testee_value_store); + +static struct attribute *cpld1_attrs[] = { + &dev_attr_swid.attr, + &dev_attr_hwrev.attr, + &dev_attr_pwrgood.attr, + &dev_attr_vrm.attr, + &dev_attr_devstate.attr, + &dev_attr_sysrst_rec.attr, + &dev_attr_muxstate.attr, + &dev_attr_xcvr_pwrstate.attr, + &dev_attr_xcvr_pwrgood.attr, + &dev_attr_wdtmax.attr, + &dev_attr_wdtcount.attr, + &dev_attr_cpld1_ver_bmc_i2c.attr, + &dev_attr_cpld1_jed_rel.attr, + &dev_attr_cpld1_testee_offset.attr, + &dev_attr_cpld1_testee_value.attr, + NULL, +}; + +static struct attribute_group cpld1_attr_grp = { + .attrs = cpld1_attrs, +}; + +static ssize_t cpld2_ver_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + uint8_t data = 0; + int err; + + mutex_lock(&cpld_data->lock); + data = readb(cpld_data->cpld2_base + CPLD2_REG_HWREV); + mutex_unlock(&cpld_data->lock); + + return sprintf(buf, "0x%2.2x\n", data); +} +struct device_attribute dev_attr_cpld2_ver = __ATTR(cpld2_ver, 0400, cpld2_ver_show, NULL); + +static ssize_t sysrdy_rst_status_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + uint8_t data = 0; + long value = 0; + int err; + + mutex_lock(&cpld_data->lock); + data = readb(cpld_data->cpld2_base + + CPLD2_REG_SYSRDY_RESET_STATUS); + value = data; + mutex_unlock(&cpld_data->lock); + + return sprintf(buf, "0x%2.2x\n", value); +} +static ssize_t sysrdy_rst_status_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + ssize_t status = 0; + long value = 0; + uint8_t data = 0; + + mutex_lock(&cpld_data->lock); + status = kstrtol(buf, 0, &value); + if (status == 0) { + data = value & 0xff; + writeb(data, cpld_data->cpld2_base + + CPLD2_REG_SYSRDY_RESET_STATUS); + status = count; + } + mutex_unlock(&cpld_data->lock); + + return status; +} +struct device_attribute dev_attr_sysrdy_rst_status = + __ATTR(sysrdy_rst_state, 0600, sysrdy_rst_status_show, + sysrdy_rst_status_store); + +static ssize_t all_xcvr_led_ctrl_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + uint8_t data = 0; + long value = 0; + int err; + + mutex_lock(&cpld_data->lock); + data = readb(cpld_data->cpld2_base + + CPLD2_REG_ALL_LED_CTRL); + value = data; + mutex_unlock(&cpld_data->lock); + + return sprintf(buf, "0x%2.2x\n", value); +} +static ssize_t all_xcvr_led_ctrl_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + ssize_t status = 0; + long value = 0; + uint8_t data = 0; + + mutex_lock(&cpld_data->lock); + status = kstrtol(buf, 0, &value); + if (status == 0) { + data = value & 0x1f; + writeb(data, cpld_data->cpld2_base + + CPLD2_REG_ALL_LED_CTRL); + status = count; + } + mutex_unlock(&cpld_data->lock); + + return status; +} +struct device_attribute dev_attr_all_xcvr_led_ctrl = + __ATTR(all_xcvr_led_ctrl, 0600, all_xcvr_led_ctrl_show, + all_xcvr_led_ctrl_store); + +static ssize_t cpld2_ver_bmc_i2c_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + uint8_t data = 0; + uint8_t data2 = 0; + uint8_t data3 = 0; + uint8_t data4 = 0; + long value = 0; + int err; + + mutex_lock(&cpld_data->lock); + data = readb(cpld_data->cpld2_base + CPLD2_REG_VER_BMC_I2C_4); + data2 = readb(cpld_data->cpld2_base + CPLD2_REG_VER_BMC_I2C_3); + data3 = readb(cpld_data->cpld2_base + CPLD2_REG_VER_BMC_I2C_2); + data4 = readb(cpld_data->cpld2_base + CPLD2_REG_VER_BMC_I2C_1); + value = data; + value |= (data2 << 8); + value |= (data3 << 16); + value |= (data4 << 24); + mutex_unlock(&cpld_data->lock); + + return sprintf(buf, "0x%8.8lx\n", value); +} +struct device_attribute dev_attr_cpld2_ver_bmc_i2c = + __ATTR(ver_bmc_i2c, 0400, cpld2_ver_bmc_i2c_show, NULL); + +static ssize_t cpld2_jed_rel_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + uint8_t data = 0; + uint8_t data2 = 0; + long value = 0; + int err; + + mutex_lock(&cpld_data->lock); + data = readb(cpld_data->cpld2_base + CPLD2_REG_JED_REL_DAY); + data2 = readb(cpld_data->cpld2_base + CPLD2_REG_JED_REL_MONTH); + value = data; + value |= (data2 << 8); + mutex_unlock(&cpld_data->lock); + + return sprintf(buf, "0x%4.4lx\n", value); +} +struct device_attribute dev_attr_cpld2_jed_rel = + __ATTR(jed_rel, 0400, cpld2_jed_rel_show, NULL); + +static ssize_t cpld2_testee_offset_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + return sprintf(buf, "0x%2.2x\n", cpld_testee_offset[1]); +} +static ssize_t cpld2_testee_offset_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + ssize_t status = 0; + uint8_t data; + + status = kstrtou8(buf, 0, &data); + if (status == 0) { + cpld_testee_offset[1] = data; + status = count; + } + + return status; +} +struct device_attribute dev_attr_cpld2_testee_offset = + __ATTR(testee_offset, 0600, cpld2_testee_offset_show, cpld2_testee_offset_store); + +static ssize_t cpld2_testee_value_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + uint8_t data = 0; + int err; + + mutex_lock(&cpld_data->lock); + data = readb(cpld_data->cpld2_base + cpld_testee_offset[1]); + mutex_unlock(&cpld_data->lock); + + return sprintf(buf, "0x%2.2x\n", data); +} +static ssize_t cpld2_testee_value_store(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + ssize_t status = 0; + uint8_t data; + + mutex_lock(&cpld_data->lock); + status = kstrtou8(buf, 0, &data); + if (status == 0) { + writeb(data, cpld_data->cpld2_base + cpld_testee_offset[1]); + status = count; + } + mutex_unlock(&cpld_data->lock); + + return status; +} +struct device_attribute dev_attr_cpld2_testee_value = + __ATTR(testee_value, 0600, cpld2_testee_value_show, cpld2_testee_value_store); + +static struct attribute *cpld2_attrs[] = { + &dev_attr_cpld2_ver.attr, + &dev_attr_sysrdy_rst_status.attr, + &dev_attr_all_xcvr_led_ctrl.attr, + &dev_attr_cpld2_ver_bmc_i2c.attr, + &dev_attr_cpld2_jed_rel.attr, + &dev_attr_cpld2_testee_offset.attr, + &dev_attr_cpld2_testee_value.attr, + NULL, +}; + +static struct attribute_group cpld2_attr_grp = { + .attrs = cpld2_attrs, +}; + +struct t7132s { + unsigned char __iomem *cfg_mmio_start; + resource_size_t cfg_mmio_len; + unsigned char __iomem *dev_mmio_start; + resource_size_t dev_mmio_len; + unsigned char __iomem *dev2_mmio_start; + resource_size_t dev2_mmio_len; +}; + +static struct t7132s t7132s_dev; +static struct platform_device *t7132s_platform_dev; +static struct kobject *cpld1 = NULL; +static struct kobject *cpld2 = NULL; +static struct device *sff_dev = NULL; + +static ssize_t qsfp_modirq_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct sff_device_data *dev_data = dev_get_drvdata(dev); + unsigned int portid = dev_data->portid; + u8 index = 0; + u16 reg = 0; + u8 value = 0; + + mutex_lock(&cpld_data->lock); + if ((portid % 2) != 0) { + QSFP_REG_READ (reg, QSFP_T_INT, + cpld_data->cpld_base); + index = (portid + 1) / 2; + } else { + QSFP_REG_READ (reg, QSFP_B_INT, + cpld_data->cpld_base); + index = portid / 2; + } + value = reg >> (index - 1) & 1; + mutex_unlock(&cpld_data->lock); + + return sprintf(buf, "%d\n", value); +} +DEVICE_ATTR_RO(qsfp_modirq); + +static ssize_t qsfp_modprs_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct sff_device_data *dev_data = dev_get_drvdata(dev); + unsigned int portid = dev_data->portid; + u8 index = 0; + u16 reg = 0; + u8 value = 0; + + mutex_lock(&cpld_data->lock); + if ((portid % 2) != 0) { + QSFP_REG_READ (reg, QSFP_T_MODPRS, + cpld_data->cpld_base); + index = (portid + 1) / 2; + } else { + QSFP_REG_READ (reg, QSFP_B_MODPRS, + cpld_data->cpld_base); + index = portid / 2; + } + value = reg >> (index - 1) & 1; + mutex_unlock(&cpld_data->lock); + + return sprintf(buf, "%d\n", value); +} +DEVICE_ATTR_RO(qsfp_modprs); + +static ssize_t qsfp_lpmode_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct sff_device_data *dev_data = dev_get_drvdata(dev); + unsigned int portid = dev_data->portid; + u8 index = 0; + u16 reg = 0; + u8 value = 0; + + mutex_lock(&cpld_data->lock); + if ((portid % 2) != 0) { + QSFP_REG_READ (reg, QSFP_T_LPMODE, + cpld_data->cpld_base); + index = (portid + 1) / 2; + } else { + QSFP_REG_READ (reg, QSFP_B_LPMODE, + cpld_data->cpld_base); + index = portid / 2; + } + value = reg >> (index - 1) & 1; + mutex_unlock(&cpld_data->lock); + + return sprintf(buf, "%d\n", value); +} +static ssize_t qsfp_lpmode_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + ssize_t status; + struct sff_device_data *dev_data = dev_get_drvdata(dev); + unsigned int portid = dev_data->portid; + u8 value = 0; + u8 index = 0; + u16 reg = 0; + + mutex_lock(&cpld_data->lock); + status = kstrtou8(buf, 0, &value); + + if ((status == 0) && (value <= 1)) { + if ((portid % 2) != 0) { + QSFP_REG_READ (reg, QSFP_T_LPMODE, + cpld_data->cpld_base); + index = (portid + 1) / 2; + if (value == 1) { + reg |= (1 << (index - 1)); + } else { + reg &= ~(1 << (index - 1)); + } + QSFP_REG_WRITE (reg, QSFP_T_LPMODE, + cpld_data->cpld_base); + } else { + QSFP_REG_READ (reg, QSFP_B_LPMODE, + cpld_data->cpld_base); + index = portid / 2; + if (value == 1) { + reg |= (1 << (index - 1)); + } else { + reg &= ~(1 << (index - 1)); + } + QSFP_REG_WRITE (reg, QSFP_B_LPMODE, + cpld_data->cpld_base); + } + status = count; + } + + mutex_unlock(&cpld_data->lock); + + return status; +} +DEVICE_ATTR_RW(qsfp_lpmode); + +static ssize_t qsfp_reset_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct sff_device_data *dev_data = dev_get_drvdata(dev); + unsigned int portid = dev_data->portid; + u8 index = 0; + u16 reg = 0; + u8 value = 0; + + mutex_lock(&cpld_data->lock); + if ((portid % 2) != 0) { + QSFP_REG_READ (reg, QSFP_T_RESET, + cpld_data->cpld_base); + index = (portid + 1) / 2; + } else { + QSFP_REG_READ (reg, QSFP_B_RESET, + cpld_data->cpld_base); + index = portid / 2; + } + value = reg >> (index - 1) & 1; + mutex_unlock(&cpld_data->lock); + + return sprintf(buf, "%d\n", value); +} + +static ssize_t qsfp_reset_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + ssize_t status; + struct sff_device_data *dev_data = dev_get_drvdata(dev); + unsigned int portid = dev_data->portid; + u8 value = 0; + u8 index = 0; + u16 reg = 0; + + mutex_lock(&cpld_data->lock); + status = kstrtou8(buf, 0, &value); + + if ((status == 0) && (value <= 1)) { + if ((portid % 2) != 0) { + QSFP_REG_READ (reg, QSFP_T_RESET, + cpld_data->cpld_base); + index = (portid + 1) / 2; + if (value == 1) { + reg |= (1 << (index - 1)); + } else { + reg &= ~(1 << (index - 1)); + } + QSFP_REG_WRITE (reg, QSFP_T_RESET, + cpld_data->cpld_base); + } else { + QSFP_REG_READ (reg, QSFP_B_RESET, + cpld_data->cpld_base); + index = portid / 2; + if (value == 1) { + reg |= (1 << (index - 1)); + } else { + reg &= ~(1 << (index - 1)); + } + QSFP_REG_WRITE (reg, QSFP_B_RESET, + cpld_data->cpld_base); + } + status = count; + } + mutex_unlock(&cpld_data->lock); + + return status; +} +DEVICE_ATTR_RW(qsfp_reset); + +static struct attribute *sff_attrs[] = { + &dev_attr_qsfp_modprs.attr, + &dev_attr_qsfp_modirq.attr, + &dev_attr_qsfp_lpmode.attr, + &dev_attr_qsfp_reset.attr, + NULL, +}; +static struct attribute_group sff_attr_grp = { + .attrs = sff_attrs, +}; +static const struct attribute_group *sff_attr_grps[] = { &sff_attr_grp, NULL }; + +#define SFP_MOD_MASK (1 << 5) +#define SFP_LOS_MASK (1 << 4) +#define SFP_TXFAULT_MASK (1 << 3) +#define SFP_RS0_MASK (1 << 2) +#define SFP_RS1_MASK (1 << 1) +#define SFP_TXDISABLE_MASK (1) +#define CPLD1_SFP_OFFSET 0x20 +#define SFP_REG_READ(_portid_, _data_, _base_) \ + do { \ + _data_ = readb(_base_ + CPLD1_SFP_OFFSET + _portid_ - 1); \ + } while (0); +#define SFP_REG_WRITE(_portid_, _data_, _base_) \ + do { \ + writeb(_data_, _base_ + CPLD1_SFP_OFFSET + _portid_ - 1); \ + } while (0); + +static ssize_t sfp_modabs_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct sff_device_data *dev_data = dev_get_drvdata(dev); + unsigned int portid = dev_data->portid; + u8 value = 0; + + mutex_lock(&cpld_data->lock); + SFP_REG_READ (portid, value, cpld_data->cpld_base); + value = ((value & SFP_MOD_MASK) != 0) ? 1 : 0; + mutex_unlock(&cpld_data->lock); + + return sprintf(buf, "%d\n", value); +} +DEVICE_ATTR_RO(sfp_modabs); + +static ssize_t sfp_txfault_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct sff_device_data *dev_data = dev_get_drvdata(dev); + unsigned int portid = dev_data->portid; + u8 value = 0; + + mutex_lock(&cpld_data->lock); + SFP_REG_READ (portid, value, cpld_data->cpld_base); + value = ((value & SFP_TXFAULT_MASK) != 0) ? 1 : 0; + mutex_unlock(&cpld_data->lock); + + return sprintf(buf, "%d\n", value); +} +DEVICE_ATTR_RO(sfp_txfault); + +static ssize_t sfp_rxlos_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct sff_device_data *dev_data = dev_get_drvdata(dev); + unsigned int portid = dev_data->portid; + u8 index = 0; + u16 reg = 0; + u8 value = 0; + + mutex_lock(&cpld_data->lock); + SFP_REG_READ (portid, value, cpld_data->cpld_base); + value = ((value & SFP_LOS_MASK) != 0) ? 1 : 0; + mutex_unlock(&cpld_data->lock); + + return sprintf(buf, "%d\n", value); +} +DEVICE_ATTR_RO(sfp_rxlos); + +static ssize_t sfp_txdisable_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct sff_device_data *dev_data = dev_get_drvdata(dev); + unsigned int portid = dev_data->portid; + u8 value = 0; + + mutex_lock(&cpld_data->lock); + SFP_REG_READ (portid, value, cpld_data->cpld_base); + value = ((value & SFP_TXDISABLE_MASK) != 0) ? 1 : 0; + mutex_unlock(&cpld_data->lock); + + return sprintf(buf, "%d\n", value); +} + +static ssize_t sfp_txdisable_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t count) +{ + ssize_t status; + struct sff_device_data *dev_data = dev_get_drvdata(dev); + unsigned int portid = dev_data->portid; + u8 value = 0; + u8 index = 0; + u8 reg = 0; + + mutex_lock(&cpld_data->lock); + status = kstrtou8(buf, 0, &value); + + if ((status == 0) && value <= 1) { + SFP_REG_READ (portid, reg, cpld_data->cpld_base); + if (value == 1) { + reg |= 1; + } else { + reg &= ~1; + } + SFP_REG_WRITE (portid, reg, cpld_data->cpld_base); + status = count; + } else { + status = -EINVAL; + } + + mutex_unlock(&cpld_data->lock); + + return status; +} +DEVICE_ATTR_RW(sfp_txdisable); + +static struct attribute *sff_sfp_attrs[] = { + &dev_attr_sfp_txfault.attr, + &dev_attr_sfp_rxlos.attr, + &dev_attr_sfp_modabs.attr, + &dev_attr_sfp_txdisable.attr, + NULL, +}; +static struct attribute_group sff_sfp_attr_grp = { + .attrs = sff_sfp_attrs, +}; +static const struct attribute_group *sff_sfp_attr_grps[] = + { &sff_sfp_attr_grp, NULL }; + +static struct device *t7132s_sff_init(int portid) +{ + struct sff_device_data *new_data; + struct device *new_device; + char tmpStr[20]; + + new_data = kzalloc(sizeof(*new_data), GFP_KERNEL); + + new_data->portid = sff_device_tbl[portid].portid; + new_data->port_type = sff_device_tbl[portid].port_type; + new_data->parent_index = sff_device_tbl[portid].parent_index; + new_data->chan_id = sff_device_tbl[portid].chan_id; + + if (sff_device_tbl[portid].port_type == QSFP) { + sprintf(tmpStr, "QSFP%d", new_data->portid); + new_device = device_create_with_groups(cpld_class, sff_dev, MKDEV(0, 0), + new_data, sff_attr_grps, "%s", + tmpStr); + } else { + sprintf(tmpStr, "SFP%d", new_data->portid); + new_device = device_create_with_groups(cpld_class, sff_dev, MKDEV(0, 0), + new_data, sff_sfp_attr_grps, "%s", + tmpStr); + } + + return new_device; +} + +static void t7132s_sff_deinit(int portid) +{ + struct sff_device_data *dev_data; + + dev_data = dev_get_drvdata(cpld_data->sff_devices[portid]); + device_unregister(cpld_data->sff_devices[portid]); + put_device(cpld_data->sff_devices[portid]); + kfree(dev_data); + + return; +} + +static int t7132s_wdt_start(struct watchdog_device *wd_dev) +{ + uint8_t data = 0; + + mutex_lock(&cpld_data->lock); + data = readb(cpld_data->cpld_base + CPLD1_REG_DEV_STATE_2); + data |= 0x01; + writeb(data, cpld_data->cpld_base + CPLD1_REG_DEV_STATE_2); + mutex_unlock(&cpld_data->lock); + return 0; +} + +static int t7132s_wdt_stop(struct watchdog_device *wd_dev) +{ + uint8_t data = 0; + + mutex_lock(&cpld_data->lock); + data = readb(cpld_data->cpld_base + CPLD1_REG_DEV_STATE_2); + data &= 0xfe; + writeb(data, cpld_data->cpld_base + CPLD1_REG_DEV_STATE_2); + mutex_unlock(&cpld_data->lock); + return 0; +} + +static int t7132s_wdt_ping(struct watchdog_device *wd_dev) +{ + uint8_t data = 0; + + mutex_lock(&cpld_data->lock); + data = readb(cpld_data->cpld_base + CPLD1_REG_DEV_STATE_2); + /* disable */ + data &= 0xfe; + writeb(data, cpld_data->cpld_base + CPLD1_REG_DEV_STATE_2); + /* enable */ + data |= 0x01; + writeb(data, cpld_data->cpld_base + CPLD1_REG_DEV_STATE_2); + mutex_unlock(&cpld_data->lock); + return 0; +} + +static int t7132s_wdt_set_timeout(struct watchdog_device *wd_dev, unsigned int t) +{ + uint8_t data1 = 0; + uint8_t data2 = 0; + uint8_t data = 0; + int is_enabled = 0; + + if (t > 65535) + return -EINVAL; + + data1 = t & 0xff; + data2 = (t & 0xff00) >> 8; + mutex_lock(&cpld_data->lock); + /* save and stop */ + data = readb(cpld_data->cpld_base + CPLD1_REG_DEV_STATE_2); + is_enabled = data & 0x01; + if (is_enabled != 0) { + data &= 0xfe; + writeb(data, cpld_data->cpld_base + CPLD1_REG_DEV_STATE_2); + } + /* update max */ + writeb(data1, cpld_data->cpld_base + CPLD1_REG_WDT_MAX_COUNT_1); + writeb(data2, cpld_data->cpld_base + CPLD1_REG_WDT_MAX_COUNT_2); + /* restore */ + if (is_enabled != 0) { + data = readb(cpld_data->cpld_base + CPLD1_REG_DEV_STATE_2); + data |= is_enabled; + writeb(data, cpld_data->cpld_base + CPLD1_REG_DEV_STATE_2); + } + mutex_unlock(&cpld_data->lock); + + wd_dev->timeout = t; + return 0; +} + +static unsigned int t7132s_wdt_get_timeleft(struct watchdog_device *wd_dev) +{ + unsigned int time_left = 0; + uint8_t data_max1 = 0; + uint8_t data_max2 = 0; + long time_max = 0; + uint8_t data_now1 = 0; + uint8_t data_now2 = 0; + long time_now = 0; + + mutex_lock(&cpld_data->lock); + data_max1 = readb(cpld_data->cpld_base + CPLD1_REG_WDT_MAX_COUNT_1); + data_max2 = readb(cpld_data->cpld_base + CPLD1_REG_WDT_MAX_COUNT_2); + data_now1 = readb(cpld_data->cpld_base + CPLD1_REG_WDT_CUR_COUNT_1); + data_now2 = readb(cpld_data->cpld_base + CPLD1_REG_WDT_CUR_COUNT_2); + mutex_unlock(&cpld_data->lock); + + /* our watchdog is counting up */ + time_max = (data_max2 << 8) | data_max1; + time_now = (data_now2 << 8) | data_now1; + if (time_max >= time_now) { + time_left = time_max - time_now; + } + else + { + /* for debug */ + time_left = 0; + printk("T7132S: t7132s_wdt_get_timeleft time_max=0x%04lx time_now=0x%04lx\n", + time_max, time_now); + } + + return time_left; + +} + +static const struct watchdog_ops t7132s_wdt_ops = { + .owner = THIS_MODULE, + .start = t7132s_wdt_start, + .stop = t7132s_wdt_stop, + .ping = t7132s_wdt_ping, + .set_timeout = t7132s_wdt_set_timeout, + .get_timeleft = t7132s_wdt_get_timeleft, +}; + +static int __init __find_i2c_adap(struct device *dev, const void *data) +{ + const char *name = data; + static const char *prefix = "i2c-"; + struct i2c_adapter *adapter; + + if (strncmp(dev_name(dev), prefix, strlen(prefix)) != 0) { + return 0; + } + adapter = to_i2c_adapter(dev); + + return (strncmp(adapter->name, name, strlen(name)) == 0); +} + +static int t7132s_drv_probe(struct platform_device *pdev) +{ + int ret = 0; + int port_count = 0; + struct sff_device_data *sff_data = NULL; + const char *name = NULL; + struct device *dev = NULL; + struct i2c_adapter *adapter = NULL; + struct i2c_board_info *entry = NULL; + struct i2c_client *client = NULL; + struct i2c_mux_core *muxc = NULL; + int index = 0; + int parent_idx = 0; + int max_index = sizeof(i2c_topo) / sizeof(struct i2c_topo_node); + int adapter_id = 0; + int chan_id = 0; + + cpld_class = class_create(THIS_MODULE, CLASS_NAME); + ret = PTR_ERR(cpld_class); + + cpld_data = devm_kzalloc(&pdev->dev, sizeof(struct t7132s_cpld), + GFP_KERNEL); + mutex_init(&cpld_data->lock); + cpld_data->cpld_base = t7132s_dev.dev_mmio_start; + cpld1 = kobject_create_and_add("CPLD1", &pdev->dev.kobj); + ret = sysfs_create_group(cpld1, &cpld1_attr_grp); + cpld_data->cpld2_base = t7132s_dev.dev2_mmio_start; + cpld2 = kobject_create_and_add("CPLD2", &pdev->dev.kobj); + ret = sysfs_create_group(cpld2, &cpld2_attr_grp); + + sff_dev = device_create(cpld_class, NULL, MKDEV(0, 0), NULL, "%s", + "sff_device"); + ret = sysfs_create_link(&pdev->dev.kobj, &sff_dev->kobj, "SFF"); + + /* Setup i2c MUX devices */ + for (index = 0; index < max_index; index++) { + if (i2c_topo[index].parent_index == -1) { + name = bms_i2c_adapter_names[i2c_topo[index] + .adapter_type]; + dev = bus_find_device(&i2c_bus_type, NULL, (void *)name, + __find_i2c_adap); + adapter = to_i2c_adapter(dev); + if (adapter != NULL) { + i2c_topo[index].client = i2c_new_client_device( + adapter, &i2c_topo[index].entry); + msleep(500); + } + } else if (i2c_topo[index].parent_index != -1) { + parent_idx = i2c_topo[index].parent_index; + if (i2c_topo[parent_idx].client != NULL) { + client = i2c_topo[parent_idx].client; + muxc = i2c_get_clientdata(client); + if (muxc != NULL) { + chan_id = i2c_topo[index].chan_id; + adapter_id = muxc->adapter[chan_id]->nr; + adapter = i2c_get_adapter(adapter_id); + if (adapter != NULL) { + i2c_topo[index] + .client = i2c_new_client_device( + adapter, + &i2c_topo[index].entry); + i2c_put_adapter(adapter); + msleep(100); + } + } + } + } + dev = NULL; + adapter = NULL; + } + + for (port_count = 0; port_count < SFF_PORT_TOTAL; port_count++) { + cpld_data->sff_devices[port_count] = + t7132s_sff_init(port_count); + sff_data = dev_get_drvdata(cpld_data->sff_devices[port_count]); + parent_idx = sff_data->parent_index; + chan_id = sff_data->chan_id; + muxc = i2c_get_clientdata(i2c_topo[parent_idx].client); + if (muxc != NULL) { + adapter_id = muxc->adapter[chan_id]->nr; + adapter = i2c_get_adapter(adapter_id); + } + if (adapter == NULL) + continue; + if (sff_data->port_type == QSFP) { + /* Initiate optoe1 device */ + cpld_data->sff_i2c_clients[port_count] = + i2c_new_client_device(adapter, &sff_eeprom_info[0]); + } else { + /* Initiate optoe2 device */ + cpld_data->sff_i2c_clients[port_count] = + i2c_new_client_device(adapter, &sff_eeprom_info[1]); + } + i2c_put_adapter(adapter); + sff_data = NULL; + adapter = NULL; + /* Create sysfs link */ + sysfs_create_link( + &cpld_data->sff_devices[port_count]->kobj, + &cpld_data->sff_i2c_clients[port_count]->dev.kobj, + "i2c"); + } + + /* watchdog */ + pwddev = devm_kzalloc(&pdev->dev, sizeof(*pwddev), GFP_KERNEL); + if (pwddev) { + pwddev->info = &ident, + pwddev->ops = &t7132s_wdt_ops, + pwddev->bootstatus = 0; + pwddev->timeout = WATCHDOG_TIMEOUT; + pwddev->parent = &pdev->dev; + pwddev->min_timeout = 1; + pwddev->max_timeout = 65535; + //pwddev->max_hw_heartbeat_ms = 65535 * 1000; + + ret = devm_watchdog_register_device(&pdev->dev, pwddev); + if (ret != 0) { + printk("T7132S: cannot register watchdog device (err=%d)\n", ret); + } + else { + t7132s_wdt_stop(pwddev); + t7132s_wdt_set_timeout(pwddev, WATCHDOG_TIMEOUT); + printk("T7132S: watchdog initialized. heartbeat=%d sec (nowayout=%d)\n", + pwddev->timeout, 0); + } + } + else { + printk("T7132S: devm_kzalloc fail for watchdog device\n"); + } + + return 0; +} + +static int t7132s_drv_remove(struct platform_device *pdev) +{ + int ret = 0; + int port_count = 0; + struct sff_device_data *sff_data = NULL; + const char *name = NULL; + struct device *dev = NULL; + struct i2c_adapter *adapter; + struct i2c_board_info *entry; + int index = 0; + int max_index = sizeof(i2c_topo) / sizeof(struct i2c_topo_node); + + for (port_count = 0; port_count < SFF_PORT_TOTAL; port_count++) { + sysfs_remove_link(&cpld_data->sff_devices[port_count]->kobj, + "i2c"); + if (cpld_data->sff_i2c_clients[port_count] != NULL) { + i2c_unregister_device( + cpld_data->sff_i2c_clients[port_count]); + } + } + + for (port_count = 0; port_count < SFF_PORT_TOTAL; port_count++) { + t7132s_sff_deinit(port_count); + } + + for (index = max_index - 1; index >= 0; index--) { + if (i2c_topo[index].client != NULL) { + i2c_unregister_device(i2c_topo[index].client); + } + } + + sysfs_remove_link(&pdev->dev.kobj, "SFF"); + device_destroy(cpld_class, MKDEV(0, 0)); + sysfs_remove_group(cpld1, &cpld1_attr_grp); + class_destroy(cpld_class); // remove the device class + cpld_class = NULL; + devm_kfree(&pdev->dev, cpld_data); + devm_kfree(&pdev->dev, pwddev); + + return 0; +} + +static struct platform_driver t7132s_drv = { + .probe = t7132s_drv_probe, + .remove = __exit_p(t7132s_drv_remove), + .driver = + { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + }, +}; + +static void t7132s_remove(struct pci_dev *dev) +{ + platform_device_unregister(t7132s_platform_dev); + platform_driver_unregister(&t7132s_drv); + iounmap(t7132s_dev.cfg_mmio_start); + iounmap(t7132s_dev.dev_mmio_start); + iounmap(t7132s_dev.dev2_mmio_start); + + pci_disable_device(dev); +} + +static int t7132s_probe(struct pci_dev *dev, const struct pci_device_id *ent) +{ + int retval, ret; + unsigned long base; + resource_size_t len; + unsigned long val; + char *ptr = NULL; + + retval = pci_enable_device(dev); + pci_set_master(dev); + + len = pci_resource_len(dev, 5); + base = pci_resource_start(dev, 5); + t7132s_dev.cfg_mmio_start = ioremap(base, len); + t7132s_dev.cfg_mmio_len = len; + + len = pci_resource_len(dev, 0); + base = pci_resource_start(dev, 0); + t7132s_dev.dev_mmio_start = ioremap(base, len); + t7132s_dev.dev_mmio_len = len; + + len = pci_resource_len(dev, 1); + base = pci_resource_start(dev, 1); + t7132s_dev.dev2_mmio_start = ioremap(base, len); + t7132s_dev.dev2_mmio_len = len; + + /* Localbus bridge reset sequence */ + val = readl(t7132s_dev.cfg_mmio_start + REG_LIEMR); + printk("LIEMR = 0x%x", val); + writeb(val | LIEMR_SRST | LIEMR_LRST, + t7132s_dev.cfg_mmio_start + REG_LIEMR); + val = readl(t7132s_dev.cfg_mmio_start + REG_LIEMR); + printk("LIEMR(after hw reset) = 0x%x", val); + + /* Localbus init sequence */ + val = LIEMR_RDYPOL | LIEMR_ALEPOL | LIEMR_SYNCBUS | LIEMR_MULTBUS | + LIEMR_DMA0EN | LIEMR_DMA1EN | LIEMR_L0EINTEN | LIEMR_L0RTOIEN | + LIEMR_L1EINTEN | LIEMR_L1RTOIEN | LIEMR_D0DIEN | LIEMR_D0AIEN | + LIEMR_D1DIEN | LIEMR_D1AIEN; + printk("LIEMR(new) = 0x%x", val); + writel(val, t7132s_dev.cfg_mmio_start + REG_LIEMR); + val = readl(t7132s_dev.cfg_mmio_start + REG_LIEMR); + printk("LIEMR(modified) = 0x%x", val); + + val = readl(t7132s_dev.cfg_mmio_start + REG_LAS0CFGR); + val &= ~LASCFGR_BW16; + writel(val, t7132s_dev.cfg_mmio_start + REG_LAS0CFGR); + val = readl(t7132s_dev.cfg_mmio_start + REG_LAS0CFGR); /* flush */ + + val = readl(t7132s_dev.cfg_mmio_start + REG_LAS1CFGR); + val &= ~LASCFGR_BW16; + writel(val, t7132s_dev.cfg_mmio_start + REG_LAS1CFGR); + val = readl(t7132s_dev.cfg_mmio_start + REG_LAS1CFGR); /* flush */ + + val = readl(t7132s_dev.cfg_mmio_start + REG_LACKSR); + printk("LACKSR = 0x%x", val); + val &= ~LACKSR_ALERA; + val |= LACKSR_CLKOEN; + val = 0x2405; + writel(val, t7132s_dev.cfg_mmio_start + REG_LACKSR); + val = readl(t7132s_dev.cfg_mmio_start + REG_LACKSR); + printk("LACKSR(modified) = 0x%x", val); + + /* Read Switch ID from offset 0x1 */ + ptr = (t7132s_dev.dev_mmio_start + CPLD1_REG_SW_ID); + val = readb(t7132s_dev.dev_mmio_start + CPLD1_REG_SW_ID); + printk("Switch ID : 0x%x", val); + + platform_driver_register(&t7132s_drv); + t7132s_platform_dev = + platform_device_register_simple(DRIVER_NAME, -1, NULL, 0); + + return 0; +} + +static int t7132s_suspend(struct pci_dev *dev, pm_message_t state) +{ + return 0; +}; + +static int t7132s_resume(struct pci_dev *dev) +{ + return 0; +}; + +static struct pci_device_id t7132s_pci_tbl[] = { + { 0x125B, 0x9110, 0xa000, 0x7000, 0, 0, 0 }, + { 0x125B, 0x9100, 0xa000, 0x7000, 0, 0, 0 }, + { + 0, + }, +}; + +static struct pci_driver t7132s_pci_driver = { + .name = "t7132s", + .probe = t7132s_probe, + .remove = t7132s_remove, + .id_table = t7132s_pci_tbl, + .suspend = t7132s_suspend, + .resume = t7132s_resume, +}; + +static int __init t7132s_init(void) +{ + int ret; + + memset(&t7132s_dev, 0, sizeof(struct t7132s)); + ret = pci_register_driver(&t7132s_pci_driver); + + return ret; +} + +static void __exit t7132s_exit(void) +{ + pci_unregister_driver(&t7132s_pci_driver); +} + +module_init(t7132s_init); +module_exit(t7132s_exit); + +MODULE_DEVICE_TABLE(pci, t7132s_pci_tbl); +MODULE_DESCRIPTION("SuperMicro T7132S CPLD Module"); +MODULE_SUPPORTED_DEVICE("T7132S"); +MODULE_LICENSE("GPL"); diff --git a/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/scripts/health_checker_thermal.py b/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/scripts/health_checker_thermal.py new file mode 100755 index 000000000000..6f1ee137843d --- /dev/null +++ b/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/scripts/health_checker_thermal.py @@ -0,0 +1,50 @@ +#!/usr/bin/python3 + +''' +This script is for healthd user_defined_checkers. +''' + +from swsscommon.swsscommon import SonicV2Connector +from natsort import natsorted + +TEMPER_TABLE_NAME = 'TEMPERATURE_INFO' +TEMPER_FIELD_NAME = 'temperature' +TIMESTAMP_FIELD_NAME = 'timestamp' +HIGH_THRESH_FIELD_NAME = 'high_threshold' +LOW_THRESH_FIELD_NAME = 'low_threshold' +CRIT_HIGH_THRESH_FIELD_NAME = 'critical_high_threshold' +CRIT_LOW_THRESH_FIELD_NAME = 'critical_low_threshold' +WARNING_STATUS_FIELD_NAME = 'warning_status' + +class TemperCheck(object): + def __init__(self): + self.db = SonicV2Connector(host="127.0.0.1") + self.db.connect(self.db.STATE_DB) + + def show(self): + keys = self.db.keys(self.db.STATE_DB, TEMPER_TABLE_NAME + '*') + if not keys: + #print('Thermal Not detected\n') + return + + print("Thermal") + for key in natsorted(keys): + key_list = key.split('|') + if len(key_list) != 2: # error data in DB, log it and ignore + #print('Warn: Invalid key in table {}: {}'.format(TEMPER_TABLE_NAME, key)) + continue + + name = key_list[1] + data_dict = self.db.get_all(self.db.STATE_DB, key) + if data_dict[WARNING_STATUS_FIELD_NAME] == 'False': + print("{}:OK".format(name)) + else: + temperature = data_dict[TEMPER_FIELD_NAME] + high_threshold = data_dict[HIGH_THRESH_FIELD_NAME] + low_threshold = data_dict[LOW_THRESH_FIELD_NAME] + print("{}:{} status is warning about temperature {} (threshold high {} low {})". + format(name, name, temperature, high_threshold, low_threshold)) + +if __name__ == "__main__": + temperCheck = TemperCheck() + temperCheck.show() diff --git a/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/scripts/platform.sh b/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/scripts/platform.sh new file mode 100755 index 000000000000..91c7249b448c --- /dev/null +++ b/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/scripts/platform.sh @@ -0,0 +1,102 @@ +#!/bin/bash + +i2c_config() { + local count=0 + local MAX_BUS_RETRY=20 + local MAX_I2C_OP_RETRY=10 + + i2c_bus_op=`echo "$@" | cut -d'>' -f 2` + i2c_bus=$(dirname $i2c_bus_op) + + # check if bus exists + while [[ "$count" -lt "$MAX_BUS_RETRY" ]]; do + [[ -e $i2c_bus ]] && break || sleep .1 + count=$((count+1)) + done + + if [[ "$count" -eq "$MAX_BUS_RETRY" ]]; then + echo "dell_i2c_utils : ERROR: $@ : i2c bus not created" + return + fi + + # perform the add/delete + count=0 + while [[ "$count" -lt "$MAX_I2C_OP_RETRY" ]]; do + eval "$@" > /dev/null 2>&1 + [[ $? == 0 ]] && break || sleep .2 + count=$((count+1)) + done + + if [[ "$count" -eq "$MAX_I2C_OP_RETRY" ]]; then + echo "dell_i2c_utils : ERROR: $@ : i2c operation failed" + return + fi +} + +# Attach/Detach syseeprom on CPU board +sys_eeprom() { + case $1 in + "new_device") i2c_config "echo 24c02 0x53 > /sys/bus/i2c/devices/i2c-0/$1" + ;; + "delete_device") i2c_config "echo 0x53 > /sys/bus/i2c/devices/i2c-0/$1" + ;; + *) echo "platform: sys_eeprom : invalid command !" + ;; + esac +} + +install_python_api_package() { + device="/usr/share/sonic/device" + platform=$(/usr/local/bin/sonic-cfggen -H -v DEVICE_METADATA.localhost.platform) + + rv=$(pip3 install $device/$platform/sonic_platform-1.0-py3-none-any.whl) +} + +remove_python_api_package() { + rv=$(pip3 show sonic-platform > /dev/null 2>/dev/null) + if [ $? -eq 0 ]; then + rv=$(pip3 uninstall -y sonic-platform > /dev/null 2>/dev/null) + fi +} +update_share_password() { + echo "Update shared password !!!" + SONIC_VERSION=$(cat /etc/sonic/sonic_version.yml | grep "build_version" | sed -e "s/build_version: //g;s/'//g") + image_dir=$(cat /proc/cmdline | sed -e 's/.*loop=\(\S*\)\/.*/\1/') + if [ -f /host/reboot-cause/platform/last_boot_image ]; then + last_image_ver=$(cat /host/reboot-cause/platform/last_boot_image) + else + last_image_ver="" + fi + echo "last_image_ver=${last_image_ver}" + + find /host -name "*image-*" | sed -e 's/\/host\/image-//' | while read var ; do + #echo "var=${var} image_dir=${image_dir}" + if [ "image-${var}" != "$image_dir" ] && [ "$last_image_ver" != "${SONIC_VERSION}" ]; then + cp /host/image-${var}/rw/etc/shadow /host/${image_dir}/rw/etc/shadow + cp /host/image-${var}/rw/etc/passwd /host/${image_dir}/rw/etc/passwd + cp /host/image-${var}/rw/etc/gshadow /host/${image_dir}/rw/etc/gshadow + cp /host/image-${var}/rw/etc/group /host/${image_dir}/rw/etc/group + fi + done + + if [ -d /host/reboot-cause/platform ]; then + echo "${SONIC_VERSION}" | sudo tee /host/reboot-cause/platform/last_boot_image > /dev/null + fi +} + + +if [ "$1" == "init" ]; then + echo "Initializing hardware components ..." + depmod -a + sys_eeprom "new_device" + modprobe t7132s + install_python_api_package + update_share_password +elif [ "$1" == "deinit" ]; then + echo "De-initializing hardware components ..." + modprobe -r t7132s + sys_eeprom "delete_device" + remove_python_api_package +else + echo "Invalid options !" +fi diff --git a/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/scripts/sysledctl.py b/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/scripts/sysledctl.py new file mode 100755 index 000000000000..4493ee55028d --- /dev/null +++ b/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/scripts/sysledctl.py @@ -0,0 +1,53 @@ +#!/usr/bin/python3 +import sys +import subprocess +import re +import sonic_platform.platform + +def systemctl(): + log_path = sys.argv[0] + ".log" + with open(log_path, 'w') as f: + out = subprocess.run(['systemctl', 'list-jobs'], capture_output=True, text=True).stdout + f.write(out) + chassis = sonic_platform.platform.Platform().get_chassis() + + x = re.search("reboot.target[ ]+start", out) + if x: + f.write("starting reboot\n") + chassis.set_status_led('green_blink') + + x = re.search("kexec.target[ ]+start", out) + if x: + f.write("starting kexec\n") + chassis.set_status_led('green_blink') + + x = re.search("halt.target[ ]+start", out) + if x: + f.write("starting halt\n") + chassis.set_status_led('red') + + x = re.search("poweroff.target[ ]+start", out) + if x: + f.write("starting poweroff\n") + chassis.set_status_led('off') + chassis.set_cpld2_s3(1) + + f.write("done\n") + +def reboot(): + log_path = sys.argv[0] + ".log" + with open(log_path, 'w') as f: + f.write("fast/warm reboot\n") + chassis = sonic_platform.platform.Platform().get_chassis() + chassis.set_status_led('green_blink') + f.write("done\n") + +def main(): + if len(sys.argv)>=2 and sys.argv[1]=='start': + systemctl() + if len(sys.argv)>=2 and sys.argv[1]=='reboot': + reboot() + + +if __name__ == '__main__': + main() diff --git a/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/scripts/test_cpld.py b/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/scripts/test_cpld.py new file mode 100755 index 000000000000..69e0f8302aea --- /dev/null +++ b/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/scripts/test_cpld.py @@ -0,0 +1,209 @@ +import pytest + +CPLD_INFO_PATH='/sys/devices/platform/switchboard/CPLD{}' + +@pytest.mark.parametrize( + "cpld, offset, default, valid_mask, writeable_mask, test_mask", + [ + pytest.param( 1, 0x00, 0x00, 0x00, 0x00, 0x00, id="CPLD1 0x00 Reserved"), + pytest.param( 1, 0x01, 0x00, 0x1f, 0x00, 0x00, id="CPLD1 0x01 Switch model ID"), + pytest.param( 1, 0x02, 0x10, 0xff, 0x00, 0x00, id="CPLD1 0x02 HW/CPLD version"), + pytest.param( 1, 0x03, 0xff, 0xff, 0x00, 0x00, id="CPLD1 0x03 Power sequence module status"), + pytest.param( 1, 0x04, 0x00, 0xff, 0x00, 0x00, id="CPLD1 0x04 Voltage Regulator Module ALERT/ Thermal"), + pytest.param( 1, 0x05, 0x7f, 0xff, 0x98, 0x18, id="CPLD1 0x05 Enable/ Reset misc. devices"), + pytest.param( 1, 0x06, 0xfe, 0xff, 0xff, 0x01, id="CPLD1 0x06 Enable/ Reset misc. devices"), + pytest.param( 1, 0x07, 0x0a, 0x0f, 0x0a, 0x0a, id="CPLD1 0x07 FACTORY_BTN event log and clear"), + pytest.param( 1, 0x09, 0xe0, 0xe0, 0xe0, 0xe0, id="CPLD1 0x09 System reset records"), + pytest.param( 1, 0x0B, 0xff, 0xff, 0x3f, 0x00, id="CPLD1 0x0B PCA9548 I2C bus switch RSTn"), + pytest.param( 1, 0x0C, 0x07, 0x07, 0x07, 0x07, id="CPLD1 0x0C Transceiver Power Enable"), + pytest.param( 1, 0x0D, 0xff, 0xff, 0xff, 0xff, id="CPLD1 0x0D Transceiver Power Enable"), + pytest.param( 1, 0x0E, 0x07, 0x07, 0x00, 0x00, id="CPLD1 0x0E Transceiver Power Good"), + pytest.param( 1, 0x0F, 0xff, 0xff, 0x00, 0x00, id="CPLD1 0x0F Transceiver Power Good"), + pytest.param( 1, 0x10, 0xff, 0xff, 0xff, 0xff, id="CPLD1 0x10 QSFP-DD Reset signals for Port QT16 to QT9"), + pytest.param( 1, 0x11, 0xff, 0xff, 0xff, 0xff, id="CPLD1 0x11 QSFP-DD Reset signals for Port QT8 to QT1"), + pytest.param( 1, 0x12, 0x00, 0xff, 0xff, 0xff, id="CPLD1 0x12 QSFP-DD LPMODE signals for Port QT16 to QT9"), + pytest.param( 1, 0x13, 0x00, 0xff, 0xff, 0xff, id="CPLD1 0x13 QSFP-DD LPMODE signals for Port QT8 to QT1"), + pytest.param( 1, 0x14, 0x00, 0x00, 0x00, 0x00, id="CPLD1 0x14 QSFP-DD INT signals from Port QT16 to QT9"), + pytest.param( 1, 0x15, 0x00, 0x00, 0x00, 0x00, id="CPLD1 0x15 QSFP-DD INT signals from Port QT8 to QT1"), + pytest.param( 1, 0x16, 0x00, 0x00, 0x00, 0x00, id="CPLD1 0x16 QSFP-DD MODPRS signals from Port QT16 to QT9"), + pytest.param( 1, 0x17, 0x00, 0x00, 0x00, 0x00, id="CPLD1 0x17 QSFP-DD MODPRS signals from Port QT8 to QT1"), + pytest.param( 1, 0x18, 0xff, 0xff, 0xff, 0xff, id="CPLD1 0x18 QSFP-DD Reset signals for Port QB16 to QB9"), + pytest.param( 1, 0x19, 0xff, 0xff, 0xff, 0xff, id="CPLD1 0x19 QSFP-DD Reset signals for Port QB8 to QB1"), + pytest.param( 1, 0x1A, 0x00, 0x00, 0xff, 0xff, id="CPLD1 0x1A QSFP-DD LPMODE signals for Port QB16 to QB9"), + pytest.param( 1, 0x1B, 0x00, 0x00, 0xff, 0xff, id="CPLD1 0x1B QSFP-DD LPMODE signals for Port QB8 to QB1"), + pytest.param( 1, 0x1C, 0x00, 0x00, 0x00, 0x00, id="CPLD1 0x1C QSFP-DD INT signals from Port QB16 to QB9"), + pytest.param( 1, 0x1D, 0x00, 0x00, 0x00, 0x00, id="CPLD1 0x1D QSFP-DD INT signals from Port QB8 to QB1"), + pytest.param( 1, 0x1E, 0x00, 0x00, 0x00, 0x00, id="CPLD1 0x1E QSFP-DD MODPRS signals from Port QB16 to QB9"), + pytest.param( 1, 0x1F, 0x00, 0x00, 0x00, 0x00, id="CPLD1 0x1F QSFP-DD MODPRS signals from Port QB8 to QB1"), + pytest.param( 1, 0x20, 0x06, 0x00, 0x07, 0x07, id="CPLD1 0x20 Top side SFPP"), + pytest.param( 1, 0x21, 0x06, 0x00, 0x07, 0x07, id="CPLD1 0x21 Bottom side SFPP"), + pytest.param( 1, 0x22, 0x00, 0x00, 0xff, 0xff, id="CPLD1 0x22 Watch Dog Maximum count setting, Least significant 8 bits"), + pytest.param( 1, 0x23, 0x00, 0x00, 0xff, 0xff, id="CPLD1 0x23 Watch Dog Maximum count setting, Most significant 8 bits"), + pytest.param( 1, 0x24, 0x00, 0x00, 0x00, 0x00, id="CPLD1 0x24 Watch Dog Current count value, Least significant 8 bits"), + pytest.param( 1, 0x25, 0x00, 0x00, 0x00, 0x00, id="CPLD1 0x25 Watch Dog Current count value, Most significant 8 bits"), + pytest.param( 1, 0xF0, 0x00, 0xff, 0x00, 0x00, id="CPLD1 0xF0 Version as BMC I2C Registers #0"), + pytest.param( 1, 0xF1, 0x48, 0xff, 0x00, 0x00, id="CPLD1 0xF1 Version as BMC I2C Registers #1"), + pytest.param( 1, 0xF2, 0x00, 0xff, 0x00, 0x00, id="CPLD1 0xF2 Version as BMC I2C Registers #2"), + pytest.param( 1, 0xF3, 0x02, 0xff, 0x00, 0x00, id="CPLD1 0xF3 Version as BMC I2C Registers #3"), + pytest.param( 1, 0xFE, 0x10, 0xff, 0x00, 0x00, id="CPLD1 0xFE CPLD JED Released Date Month"), + pytest.param( 1, 0xFF, 0x26, 0xff, 0x00, 0x00, id="CPLD1 0xFF CPLD JED Released Date Day"), + pytest.param( 2, 0x00, 0x00, 0x00, 0x00, 0x00, id="CPLD2 0x00 Reserved"), + pytest.param( 2, 0x01, 0x00, 0x00, 0x00, 0x00, id="CPLD2 0x01 Reserved"), + pytest.param( 2, 0x02, 0x00, 0x0f, 0x00, 0x00, id="CPLD2 0x02 CPLD2 FW version"), + pytest.param( 2, 0x03, 0x2c, 0x7f, 0x37, 0x33, id="CPLD2 0x03 System Ready/Reset Status and LED control"), + pytest.param( 2, 0x04, 0x00, 0xff, 0x1f, 0x1f, id="CPLD2 0x04 All transceiver LEDs control"), + pytest.param( 2, 0x05, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x05 SFPP LED manual control TSFPP"), + pytest.param( 2, 0x06, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x06 SFPP LED manual control BSFPP"), + pytest.param( 2, 0x07, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x07 QSFP-DD LED manual control QT1_Pn_G"), + pytest.param( 2, 0x08, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x08 QSFP-DD LED manual control QT1_Pn_Y"), + pytest.param( 2, 0x09, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x09 QSFP-DD LED manual control QB1_P1_G"), + pytest.param( 2, 0x0A, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x0A QSFP-DD LED manual control QB1_P1_Y"), + pytest.param( 2, 0x0B, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x0B QT2 Green 4 LEDs"), + pytest.param( 2, 0x0C, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x0C QT2 Yellow 4 LEDs"), + pytest.param( 2, 0x0D, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x0D QB2 Green 4 LEDs"), + pytest.param( 2, 0x0E, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x0E QB2Yellow 4 LEDs"), + pytest.param( 2, 0x0F, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x0F QT3 Green 4 LEDs"), + pytest.param( 2, 0x10, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x10 QT3 Yellow 4 LEDs"), + pytest.param( 2, 0x11, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x11 QB3 Green 4 LEDs"), + pytest.param( 2, 0x12, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x12 QB3Yellow 4 LEDs"), + pytest.param( 2, 0x13, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x13 QT4 Green 4 LEDs"), + pytest.param( 2, 0x14, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x14 QT4 Yellow 4 LEDs"), + pytest.param( 2, 0x15, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x15 QB4 Green 4 LEDs"), + pytest.param( 2, 0x16, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x16 QB4Yellow 4 LEDs"), + pytest.param( 2, 0x17, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x17 QT5 Green 4 LEDs"), + pytest.param( 2, 0x18, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x18 QT5 Yellow 4 LEDs"), + pytest.param( 2, 0x19, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x19 QB5 Green 4 LEDs"), + pytest.param( 2, 0x1A, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x1A QB5Yellow 4 LEDs"), + pytest.param( 2, 0x1B, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x1B QT6 Green 4 LEDs"), + pytest.param( 2, 0x1C, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x1C QT6 Yellow 4 LEDs"), + pytest.param( 2, 0x1D, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x1D QB6 Green 4 LEDs"), + pytest.param( 2, 0x1E, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x1E QB6 Yellow 4 LEDs"), + pytest.param( 2, 0x1F, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x1F QT7 Green 4 LEDs"), + pytest.param( 2, 0x20, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x20 QT7 Yellow 4 LEDs"), + pytest.param( 2, 0x21, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x21 QB7 Green 4 LEDs"), + pytest.param( 2, 0x22, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x22 QB7 Yellow 4 LEDs"), + pytest.param( 2, 0x23, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x23 QT8 Green 4 LEDs"), + pytest.param( 2, 0x24, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x24 QT8 Yellow 4 LEDs"), + pytest.param( 2, 0x25, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x25 QB8 Green 4 LEDs"), + pytest.param( 2, 0x26, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x26 QB8 Yellow 4 LEDs"), + pytest.param( 2, 0x27, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x27 QT9 Green 4 LEDs"), + pytest.param( 2, 0x28, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x28 QT9 Yellow 4 LEDs"), + pytest.param( 2, 0x29, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x29 QB9 Green 4 LEDs"), + pytest.param( 2, 0x2A, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x2A QB9 Yellow 4 LEDs"), + pytest.param( 2, 0x2B, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x2B QT10 Green 4 LEDs"), + pytest.param( 2, 0x2C, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x2C QT10 Yellow 4 LEDs"), + pytest.param( 2, 0x2D, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x2D QB10 Green 4 LEDs"), + pytest.param( 2, 0x2E, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x2E QB10 Yellow 4 LEDs"), + pytest.param( 2, 0x2F, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x2F QT11 Green 4 LEDs"), + pytest.param( 2, 0x30, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x30 QT11 Yellow 4 LEDs"), + pytest.param( 2, 0x31, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x31 QB11 Green 4 LEDs"), + pytest.param( 2, 0x32, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x32 QB11 Yellow 4 LEDs"), + pytest.param( 2, 0x33, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x33 QT12 Green 4 LEDs"), + pytest.param( 2, 0x34, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x34 QT12 Yellow 4 LEDs"), + pytest.param( 2, 0x35, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x35 QB12 Green 4 LEDs"), + pytest.param( 2, 0x36, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x36 QB12 Yellow 4 LEDs"), + pytest.param( 2, 0x37, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x37 QT13 Green 4 LEDs"), + pytest.param( 2, 0x38, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x38 QT13 Yellow 4 LEDs"), + pytest.param( 2, 0x39, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x39 QB13 Green 4 LEDs"), + pytest.param( 2, 0x3A, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x3A QB13 Yellow 4 LEDs"), + pytest.param( 2, 0x3B, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x3B QT14 Green 4 LEDs"), + pytest.param( 2, 0x3C, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x3C QT14 Yellow 4 LEDs"), + pytest.param( 2, 0x3D, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x3D QB14 Green 4 LEDs"), + pytest.param( 2, 0x3E, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x3E QB14 Yellow 4 LEDs"), + pytest.param( 2, 0x3F, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x3F QT15 Green 4 LEDs"), + pytest.param( 2, 0x40, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x40 QT15 Yellow 4 LEDs"), + pytest.param( 2, 0x41, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x41 QB15 Green 4 LEDs"), + pytest.param( 2, 0x42, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x42 QB15 Yellow 4 LEDs"), + pytest.param( 2, 0x43, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x43 QT16 Green 4 LEDs"), + pytest.param( 2, 0x44, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x44 QT16 Yellow 4 LEDs"), + pytest.param( 2, 0x45, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x45 QB16 Green 4 LEDs"), + pytest.param( 2, 0x46, 0x00, 0xff, 0xff, 0xff, id="CPLD2 0x46 QB16 Yellow 4 LEDs"), + pytest.param( 2, 0xF0, 0x00, 0xff, 0x00, 0x00, id="CPLD2 0xF0 Version as BMC I2C Registers #0"), + pytest.param( 2, 0xF1, 0x48, 0xff, 0x00, 0x00, id="CPLD2 0xF1 Version as BMC I2C Registers #1"), + pytest.param( 2, 0xF2, 0x20, 0xff, 0x00, 0x00, id="CPLD2 0xF2 Version as BMC I2C Registers #2"), + pytest.param( 2, 0xF3, 0x02, 0xff, 0x00, 0x00, id="CPLD2 0xF3 Version as BMC I2C Registers #3"), + pytest.param( 2, 0xFE, 0x10, 0xff, 0x00, 0x00, id="CPLD2 0xFE CPLD JED Released Date Month"), + pytest.param( 2, 0xFF, 0x27, 0xff, 0x00, 0x00, id="CPLD2 0xFF CPLD JED Released Date Day"), + ], +) +class TestClass: + def test_cpld_read_default(self, cpld, offset, default, valid_mask, writeable_mask, test_mask): + reg_offset = "/".join([CPLD_INFO_PATH.format(cpld), "testee_offset"]) + reg_value = "/".join([CPLD_INFO_PATH.format(cpld), "testee_value"]) + + # write offset + with open(reg_offset, "r+") as file_offset: + file_offset.write(hex(offset)) + + for i in range(2): + with open(reg_value, "r+") as file_value: + content = file_value.readline().strip() + content_value = int(content, 16) + assert hex(content_value & valid_mask) == hex(default & valid_mask) + + def test_cpld_read_stable(self, cpld, offset, default, valid_mask, writeable_mask, test_mask): + reg_offset = "/".join([CPLD_INFO_PATH.format(cpld), "testee_offset"]) + reg_value = "/".join([CPLD_INFO_PATH.format(cpld), "testee_value"]) + + # write offset + with open(reg_offset, "r+") as file_offset: + file_offset.write(hex(offset)) + + # read current value + with open(reg_value, "r+") as file_value: + content = file_value.readline().strip() + last_value = int(content, 16) + + for i in range(100): + with open(reg_value, "r+") as file_value: + content = file_value.readline().strip() + content_value = int(content, 16) + assert hex(content_value) == hex(last_value) + + def test_cpld_write_stable(self, cpld, offset, default, valid_mask, writeable_mask, test_mask): + reg_offset = "/".join([CPLD_INFO_PATH.format(cpld), "testee_offset"]) + reg_value = "/".join([CPLD_INFO_PATH.format(cpld), "testee_value"]) + + # write offset + with open(reg_offset, "r+") as file_offset: + file_offset.write(hex(offset)) + + # read and save current value + with open(reg_value, "r+") as file_value: + content = file_value.readline().strip() + last_value = int(content, 16) + + for i in range(100): + for j in range(8): + if (1< 0): + return True, change_dict + + if timeout: + now_ms = time.time() * 1000 + if (now_ms - start_ms >= timeout): + return True, change_dict + + ############################################################## + ######################## SFP methods ######################### + ############################################################## + + def get_num_sfps(self): + """ + Retrieves the number of sfps available on this chassis + Returns: + An integer, the number of sfps available on this chassis + """ + if not self.sfp_module_initialized: + self.__initialize_sfp() + + return len(self._sfp_list) + + def get_all_sfps(self): + """ + Retrieves all sfps available on this chassis + Returns: + A list of objects derived from SfpBase representing all sfps + available on this chassis + """ + if not self.sfp_module_initialized: + self.__initialize_sfp() + + return self._sfp_list + + def get_sfp(self, index): + """ + Retrieves sfp represented by (0-based) index + + Args: + index: An integer, the index (0-based) of the sfp to retrieve. + The index should be the sequence of a physical port in a chassis, + starting from 0. + For example, 0 for Ethernet0, 1 for Ethernet4 and so on. + + Returns: + An object dervied from SfpBase representing the specified sfp + """ + sfp = None + if not self.sfp_module_initialized: + self.__initialize_sfp() + + try: + # The index will start from 0 + sfp = self._sfp_list[index-1] + except IndexError: + sys.stderr.write("SFP index {} out of range (1-{})\n".format( + index, len(self._sfp_list))) + return sfp + + ############################################## + # System LED methods + ############################################## + + def set_status_led(self, color): + """ + Sets the state of the system LED + + Args: + color: A string representing the color with which to set the + system LED + + Returns: + bool: True if system LED state is set successfully, False if not + """ + if color not in self.supported_led_color: + return False + + reg_path = "/".join([CPLD2_INFO_PATH, "sysrdy_rst_state"]) + + # Read current status + try: + with open(reg_path, "r+") as reg_file: + content_str = reg_file.readline().rstrip() + reg_value = int(content_str, 16) + color_value = self.color_to_status_led_reg[color] + new_reg_value = reg_value & 0b11111100 | color_value + reg_file.seek(0) + reg_file.write(hex(new_reg_value)) + except IOError as e: + print("Error: unable to open file: %s" % str(e)) + return False + + # clear S3 and S5 if status led set 'green_blink' for booting + if color == 'green_blink': + if self.get_cpld2_s5() == 1: + self.set_cpld2_s5(0) #Clear S5 status + self.set_cpld2_s5(1) #Enable to record S5 status + if self.get_cpld2_s3() == 1: + self.set_cpld2_s3(0) #Clear S3 status + + return True + + def get_status_led(self): + """ + Gets the state of the system LED + + Returns: + A string, one of the valid LED color strings which could be vendor + specified. + """ + reg_path = "/".join([CPLD2_INFO_PATH, "sysrdy_rst_state"]) + + # Read status + try: + with open(reg_path) as reg_file: + content = reg_file.readline().rstrip() + except IOError as e: + print("Error: unable to open file: %s" % str(e)) + return False + + content_value = int(content, 16) + sysled_color_reg = content_value & 0b11 + return self.status_led_reg_to_color.get(sysled_color_reg, "Unknown " + content) + + def get_watchdog(self): + """ + Retreives hardware watchdog device on this chassis + + Returns: + An object derived from WatchdogBase representing the hardware + watchdog device + """ + if self._watchdog is None: + # Initialize watchdog + try: + self._watchdog = Watchdog() + except Exception as e: + self._watchdog = None + + return self._watchdog + + def set_cpld2_s3(self, s3): + """ + Sets the bit S3 in CPLD2 sysrdy_rst_state (offset 0x03) + + Args: + s3: integer 1 or 0 + + Returns: + bool: True if the bit is set successfully, False if not + """ + reg_path = "/".join([CPLD2_INFO_PATH, "sysrdy_rst_state"]) + + # Read current status + try: + with open(reg_path, "r+") as reg_file: + content_str = reg_file.readline().rstrip() + reg_value = int(content_str, 16) + bit_value = 0b10000 if s3!=0 else 0 + new_reg_value = reg_value & 0b11101111 | bit_value + reg_file.seek(0) + reg_file.write(hex(new_reg_value)) + except IOError as e: + print("Error: unable to open file: %s" % str(e)) + return False + + return True + + def get_cpld2_s3(self): + """ + Gets the bit S3 in CPLD2 sysrdy_rst_state (offset 0x03) + + Returns: + integer 1 or 0. + """ + reg_path = "/".join([CPLD2_INFO_PATH, "sysrdy_rst_state"]) + + # Read status + try: + with open(reg_path) as reg_file: + content = reg_file.readline().rstrip() + except IOError as e: + print("Error: unable to open file: %s" % str(e)) + return False + + content_value = int(content, 16) + bit_value = 1 if (content_value & 0b10000) != 0 else 0 + return bit_value + + def initizalize_system_led(self): + """ + called by system_health.py. do nothing here. + """ + return True + + def get_cpld2_s5(self): + """ + Gets the bit S5 in CPLD2 sysrdy_rst_state (offset 0x03) + + Returns: + integer 1 or 0. + """ + reg_path = "/".join([CPLD2_INFO_PATH, "sysrdy_rst_state"]) + + # Read status + try: + with open(reg_path) as reg_file: + content = reg_file.readline().rstrip() + except IOError as e: + print("Error: unable to open file: %s" % str(e)) + return False + + content_value = int(content, 16) + bit_value = 1 if (content_value & 0b1000000) != 0 else 0 + return bit_value + + def set_cpld2_s5(self, s5): + """ + Sets the bit S5 in CPLD2 sysrdy_rst_state (offset 0x03) + + Args: + s5: integer 1 or 0 + + Returns: + bool: True if the bit is set successfully, False if not + """ + reg_path = "/".join([CPLD2_INFO_PATH, "sysrdy_rst_state"]) + + # Read current status + try: + with open(reg_path, "r+") as reg_file: + content_str = reg_file.readline().rstrip() + reg_value = int(content_str, 16) + bit_value = 0b100000 if s5!=0 else 0 + new_reg_value = reg_value & 0b11011111 | bit_value + reg_file.seek(0) + reg_file.write(hex(new_reg_value)) + except IOError as e: + print("Error: unable to open file: %s" % str(e)) + return False + + return True + + def get_bmc_reboot_cause(self): + """ + Gets the reboot cause from BMC + """ + reboot_cause = -1 + status, raw_cause = self._api_helper.ipmi_raw( + IPMI_OEM_NETFN, IPMI_GET_REBOOT_CAUSE) + if status: + hx_cause_list = [] + if raw_cause == '': + return False + else: + hx_cause = int(raw_cause.split()[0], 16) + if hx_cause > 0: + self._api_helper.ipmi_raw(IPMI_OEM_NETFN, IPMI_CLEAR_REBOOT_CAUSE) #Clear BMC reboot cause + for i in range(0, NUM_BMC_REBOOT_CAUSE): + if ((hx_cause >> i) & 1): + hx_cause_list.append(i) + #Invalid case if multiple BMC reboot causes + if len(hx_cause_list) > 1: + sys.stderr.write("{} BMC reboot causes: {}\n".format( + len(hx_cause_list), f'0b{hx_cause:08b}')) + else: + reboot_cause = hx_cause_list[0] + else: + status = False + return status, reboot_cause + + def set_cpld1_wdt_rst(self, enable): + """ + Set bit 7 in CPLD1 sysrst_rec (offset 0x09) to clean bit 4. + + Args: + enable: 1: enable record + 0: clear + + Returns: + bool: True if the bit is set successfully, False if not + """ + reg_path = "/".join([CPLD1_INFO_PATH, "sysrst_rec"]) + + # Read current status + try: + with open(reg_path, "r+") as reg_file: + content_str = reg_file.readline().rstrip() + reg_value = int(content_str, 16) + bit_value = 0x80 if enable else 0 + new_reg_value = reg_value & 0x7f | bit_value + reg_file.seek(0) + reg_file.write(hex(new_reg_value)) + except IOError as e: + print("Error: unable to open file: %s" % str(e)) + return False + + return True + + def get_cpld1_wdt_rst(self): + """ + Get the bit 4 in CPLD1 sysrst_rec (offset 0x09). + + Returns: + integer 1 or 0. + """ + reg_path = "/".join([CPLD1_INFO_PATH, "sysrst_rec"]) + + # Read status + try: + with open(reg_path) as reg_file: + content = reg_file.readline().rstrip() + except IOError as e: + print("Error: unable to open file: %s" % str(e)) + return False + + content_value = int(content, 16) + bit_value = 1 if (content_value & 0x10) != 0 else 0 + return bit_value + + def get_cpld1_board_rev(self): + """ + Get the bit [5:3] from CPLD1 ver_bmc_i2c (offset 0xF0:0xF3). + + Returns: + String of board version. + """ + reg_path = "/".join([CPLD1_INFO_PATH, "ver_bmc_i2c"]) + + # Read status + try: + with open(reg_path) as reg_file: + content = reg_file.readline().rstrip() + except IOError as e: + print("Error: unable to open file: %s" % str(e)) + return 'N/A' + + content_value = int(content, 16) + # bit [5:3] offset 0xF1 + board_ver = (content_value >> 19) & 0x07 + str_dir = {0b000:'1.00', 0b001:'1.01', 0b010:'1.02'} + rev_str = str_dir.get(board_ver, 'Unknown({:#05b})'.format(board_ver)) + return rev_str diff --git a/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/sonic_platform/component.py b/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/sonic_platform/component.py new file mode 100644 index 000000000000..ee22ce843f65 --- /dev/null +++ b/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/sonic_platform/component.py @@ -0,0 +1,106 @@ +############################################################################# +# SuperMicro SSE-T7132S +# +# Component contains an implementation of SONiC Platform Base API and +# provides the components firmware management function +# +############################################################################# + +try: + from sonic_platform_base.component_base import ComponentBase + from .helper import APIHelper +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + +COMPONENT_LIST = [ + ("BIOS", "Basic Input/Output System"), + ("BMC", "Baseboard Management Controller"), + ("SWITCH_CPLD1", "Switch board CPLD1"), + ("SWITCH_CPLD2", "Switch board CPLD2") +] +SW_CPLD1_VER_PATH = "/sys/devices/platform/switchboard/CPLD1/ver_bmc_i2c" +SW_CPLD2_VER_PATH = "/sys/devices/platform/switchboard/CPLD2/ver_bmc_i2c" +CPLD_UPGRADE_OPT = 4 +BIOS_VER_PATH = "/sys/class/dmi/id/bios_version" +BIOS__UPGRADE_OPT = 2 +BMC_VER_CMD = "ipmitool mc info | grep 'Firmware Revision'" +IPMI_BMC_VER_NETFN = "0x6" +IPMI_BMC_VER_CMD = "0x1" +BMC_VER_MAJOR_OFFSET = 2 +BMC_VER_MINOR_OFFSET = 3 +BMC_VER_AUX_OFFSET = 11 +BMC_UPGRADE_OPT = 1 +CFUFLASH_FW_UPGRADE_CMD = "CFUFLASH -cd -d {} -mse 3 {}" +MEM_PCI_RESOURCE = "/sys/bus/pci/devices/0000:09:00.0/resource0" +FPGA_VER_MEM_OFFSET = 0 + + +class Component(ComponentBase): + """Platform-specific Component class""" + + DEVICE_TYPE = "component" + + def __init__(self, component_index): + ComponentBase.__init__(self) + self.index = component_index + self.name = self.get_name() + self._api_helper = APIHelper() + + def __get_bmc_ver(self): + bmc_ver = "Unknown" + status, raw_bmc_data = self._api_helper.ipmi_raw( + IPMI_BMC_VER_NETFN, IPMI_BMC_VER_CMD) + if status: + bmc_ver_data_list = raw_bmc_data.split() + bmc_ver = '{}.{}.{}'.format(bmc_ver_data_list[BMC_VER_MAJOR_OFFSET], + bmc_ver_data_list[BMC_VER_MINOR_OFFSET], + bmc_ver_data_list[BMC_VER_AUX_OFFSET]) + return bmc_ver + + def __get_cpld_ver(self,path): + cpld_data = self._api_helper.read_txt_file(path) + cpld_ver = cpld_data[-2:] + + return cpld_ver + + def get_name(self): + """ + Retrieves the name of the component + Returns: + A string containing the name of the component + """ + return COMPONENT_LIST[self.index][0] + + def get_description(self): + """ + Retrieves the description of the component + Returns: + A string containing the description of the component + """ + return COMPONENT_LIST[self.index][1] + + def get_firmware_version(self): + """ + Retrieves the firmware version of module + Returns: + string: The firmware versions of the module + """ + fw_version = { + "BIOS": self._api_helper.read_txt_file(BIOS_VER_PATH), + "BMC": self.__get_bmc_ver(), + "SWITCH_CPLD1": self.__get_cpld_ver(SW_CPLD1_VER_PATH), + "SWITCH_CPLD2": self.__get_cpld_ver(SW_CPLD2_VER_PATH), + }.get(self.name, "Unknown") + + return fw_version + + def install_firmware(self, image_path): + """ + Install firmware to module + Args: + image_path: A string, path to firmware image + Returns: + A boolean, True if install successfully, False if not + """ + """Not Implement""" + return False diff --git a/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/sonic_platform/eeprom.py b/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/sonic_platform/eeprom.py new file mode 100644 index 000000000000..bd73d93ad3d9 --- /dev/null +++ b/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/sonic_platform/eeprom.py @@ -0,0 +1,122 @@ +############################################################################# +# SuperMicro SSE-T7132S +# +# Platform and model specific eeprom subclass, inherits from the base class, +# and provides the followings: +# - the eeprom format definition +# - specific encoder/decoder if there is special need +############################################################################# + +try: + import os + import sys + import re + + if sys.version_info.major == 3: + from io import StringIO + else: + from cStringIO import StringIO + + from sonic_platform_base.sonic_eeprom import eeprom_dts + from sonic_platform_base.sonic_eeprom import eeprom_tlvinfo +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + +CACHE_ROOT = '/var/cache/sonic/decode-syseeprom' +CACHE_FILE = 'syseeprom_cache' +TLV_EEPROM_I2C_BUS = 0 +TLV_EEPROM_I2C_ADDR = 53 + + +class Tlv(eeprom_tlvinfo.TlvInfoDecoder): + + EEPROM_DECODE_HEADLINES = 6 + + def __init__(self): + self._eeprom_path = "/sys/class/i2c-adapter/i2c-{0}/{0}-00{1}/eeprom".format( + TLV_EEPROM_I2C_BUS, TLV_EEPROM_I2C_ADDR) + super(Tlv, self).__init__(self._eeprom_path, 0, '', True) + self._eeprom = self._load_eeprom() + + def __parse_output(self, decode_output): + decode_output.replace('\0', '') + lines = decode_output.split('\n') + lines = lines[self.EEPROM_DECODE_HEADLINES:] + _eeprom_info_dict = dict() + + for line in lines: + try: + match = re.search( + '(0x[0-9a-fA-F]{2})([\s]+[\S]+[\s]+)([\S]+)', line) + if match is not None: + idx = match.group(1) + value = match.group(3).rstrip('\0') + + _eeprom_info_dict[idx] = value + except Exception: + pass + return _eeprom_info_dict + + def _load_eeprom(self): + original_stdout = sys.stdout + sys.stdout = StringIO() + try: + self.read_eeprom_db() + except Exception as e: + decode_output = sys.stdout.getvalue() + sys.stdout = original_stdout + return self.__parse_output(decode_output) + + status = self.check_status() + if 'ok' not in status: + return False + + if not os.path.exists(CACHE_ROOT): + try: + os.makedirs(CACHE_ROOT) + except Exception: + pass + + # + # only the eeprom classes that inherit from eeprom_base + # support caching. Others will work normally + # + try: + self.set_cache_name(os.path.join(CACHE_ROOT, CACHE_FILE)) + except Exception: + pass + + e = self.read_eeprom() + if e is None: + return 0 + + try: + self.update_cache(e) + except Exception: + pass + + self.decode_eeprom(e) + decode_output = sys.stdout.getvalue() + sys.stdout = original_stdout + + (is_valid, valid_crc) = self.is_checksum_valid(e) + if not is_valid: + return False + + return self.__parse_output(decode_output) + + def get_eeprom(self): + return self._eeprom + + def get_serial(self): + return self._eeprom.get('0x23', "Undefined.") + + def get_mac(self): + return self._eeprom.get('0x24', "Undefined.") + + def get_productname(self): + return self._eeprom.get('0x21', "Undefined.") + + def get_partnumber(self): + return self._eeprom.get('0x22', "Undefined.") + diff --git a/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/sonic_platform/fan.py b/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/sonic_platform/fan.py new file mode 100644 index 000000000000..12e2ab0a75e4 --- /dev/null +++ b/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/sonic_platform/fan.py @@ -0,0 +1,353 @@ +############################################################################# +# SuperMicro SSE-T7132S +# +# Module contains an implementation of SONiC Platform Base API and +# provides the fan status which are available in the platform +# +############################################################################# + +import subprocess + +try: + from sonic_platform_base.fan_base import FanBase + from .helper import APIHelper + from swsscommon.swsscommon import SonicV2Connector +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + + +FAN_NAME_LIST = ["FAN-1", "FAN-2", "FAN-3", "FAN-4", "FAN-5", "FAN-6"] + +IPMI_SENSOR_NETFN = "0x04" +IPMI_SS_READ_CMD = "0x2D {}" +IPMI_OEM_NETFN = "0x30" +IPMI_GET_FAN_SPEED_CMD = "0x70 0x66 0x00 {}" +IPMI_SET_FAN_SPEED_CMD = "0x70 0x66 0x01 {} {}" +IPMI_GET_FAN_LED_CMD = "0x89 0x03 0x00 {}" +IPMI_SET_FAN_LED_CMD = "0x89 0x03 0x01 {} {}" +IPMI_FAN_LED_OFF = 0x00 +IPMI_FAN_LED_GREEN = 0x01 +IPMI_FAN_LED_AMBER = 0x02 +IPMI_FAN_LED_AMBER_BLINK = 0x03 +IPMI_GET_PSU_FAN_SPEED_CMD = "0x89 0x04 0x{:02x} {}" + +MAX_OUTLET = 29500 +MAX_INLET = 25500 +#MAX_PSU_FAN_OUTLET = 11200 # not a fixed value +#MAX_PSU_FAN_INLET = 11200 # not a fixed value +SPEED_TOLERANCE = 20 # based on the speed graph the slowest is about 20% + +FAN_LIST = [ + #name sensor_id led_num + ('FAN1', '0x41', '0x04'), + ('FAN2', '0x42', '0x05'), + ('FAN3', '0x43', '0x06'), + ('FAN4', '0x44', '0x07'), + ('FAN5', '0x45', '0x08'), + ('FAN6', '0x46', '0x09'), +] + +SYSLOG_IDENTIFIER = "fan.py" +NOT_AVAILABLE = 'N/A' + +class Fan(FanBase): + """Platform-specific Fan class""" + + def __init__(self, fan_pwn_number=0, fan_index=0, is_psu_fan=False, psu=None): + FanBase.__init__(self) + #self.logger = logger.Logger(SYSLOG_IDENTIFIER) + #self.logger.set_min_log_priority_debug() + #self.logger.log_debug('init fan_pwn_number={} fan_index={}'.format(fan_pwn_number, fan_index)) + self.fan_pwn_number = fan_pwn_number + self.is_psu_fan = is_psu_fan + if self.is_psu_fan: + self.psu = psu + self.psu_index = self.psu.index + self._api_helper = APIHelper() + self.index = fan_index + self.sensor_reading_addr = FAN_LIST[self.index][1] + self.led_number = FAN_LIST[self.index][2] + self.led_set = self.STATUS_LED_COLOR_OFF + self.speed_set = None + + def get_direction(self): + """ + Retrieves the direction of fan + + Returns: + A string, either FAN_DIRECTION_INTAKE or FAN_DIRECTION_EXHAUST + depending on fan direction + """ + # read part number from eeprom + # psu fan follows the same rule + db = SonicV2Connector() + db.connect(db.STATE_DB) + eeprom_table = db.get_all(db.STATE_DB, 'EEPROM_INFO|0x22') + if "Name" in eeprom_table and eeprom_table["Name"] == "Part Number" and "Value" in eeprom_table: + part_number = eeprom_table["Value"] + else: + part_number_cmd = "sudo decode-syseeprom | grep 'Part Number' | grep -oE '[^ ]+$'" + part_number = subprocess.Popen(part_number_cmd, shell=True, text=True, stdout=subprocess.PIPE).stdout.read() + + if "T7132SR" in part_number: + # "SSE-T7132SR" + direction = self.FAN_DIRECTION_INTAKE + else: + # "SSE-T7132S" + direction = self.FAN_DIRECTION_EXHAUST + + return direction + + def get_speed_rpm(self): + """ + Retrieves the speed of fan as RPM. + + Returns: + An integer of RPM. + """ + if self.is_psu_fan: + status, raw_ss_read = self._api_helper.ipmi_raw( + IPMI_OEM_NETFN, IPMI_GET_PSU_FAN_SPEED_CMD.format(self.psu_index + 1, "0x08")) + rpm_speed = int("".join(raw_ss_read.split()[::-1]), 16) if status else 0 + else: + status, raw_ss_read = self._api_helper.ipmi_raw( + IPMI_SENSOR_NETFN, IPMI_SS_READ_CMD.format(self.sensor_reading_addr)) + # factor 140 should read from SDR + rpm_speed = int(raw_ss_read.split()[0], 16) * 140 if status else 0 + + return rpm_speed + + def get_speed(self): + """ + Retrieves the speed of fan as a percentage of full speed + + Returns: + An integer, the percentage of full fan speed, in the range 0 (off) + to 100 (full speed) + """ + rpm_speed = self.get_speed_rpm() + + if self.is_psu_fan: + # psu fan do not know max speed, so return rpm + speed = rpm_speed + if speed <= 100: + speed = 0 # to prevent be taken as percentage + else: + # when intake, the whole fan module is reversed, so still MAX_OUTLET + max = MAX_OUTLET + speed = int(float(rpm_speed)/max * 100) + + return speed + + def get_target_speed(self): + """ + Retrieves the target (expected) speed of the fan + + Returns: + An integer, the percentage of full fan speed, in the range 0 (off) + to 100 (full speed) + """ + """ + status, raw_ss_read = self._api_helper.ipmi_raw( + IPMI_OEM_NETFN, IPMI_GET_FAN_SPEED_CMD.format(self.fan_pwn_number)) + ss_read = raw_ss_read.split()[0] + pwn = int(ss_read, 16) + target = pwn + """ + if self.is_psu_fan: + # not support so return current speed + target = self.get_speed() + else: + # set and get result are not the same with our ipmi oem command + # This is because of the scaling between 100-based and 255-based + # here just return the cached set value for tesstbed + target = self.speed_set + if target is None: + target = self.get_speed() + return target + + def get_speed_tolerance(self): + """ + Retrieves the speed tolerance of the fan + + Returns: + An integer, the percentage of variance from target speed which is + considered tolerable + """ + return SPEED_TOLERANCE + + def set_speed(self, speed): + """ + Sets the fan speed + + Args: + speed: An integer, the percentage of full fan speed to set fan to, + in the range 0 (off) to 100 (full speed) + + Returns: + A boolean, True if speed is set successfully, False if not + """ + if self.is_psu_fan: + # not support + return False + + speed_hex = hex(speed) + status, raw_ss_read = self._api_helper.ipmi_raw( + IPMI_OEM_NETFN, IPMI_SET_FAN_SPEED_CMD.format(self.fan_pwn_number, speed_hex)) + set_speed = False if not status else True + if set_speed: + self.speed_set = speed + return set_speed + + def set_status_led(self, color): + """ + Sets the state of the fan module status LED + + Args: + color: A string representing the color with which to set the + fan module status LED + + Returns: + bool: True if status LED state is set successfully, False if not + """ + if self.is_psu_fan: + # Not support + return False + + # there are only green and red led on fan + led_color = { + self.STATUS_LED_COLOR_GREEN: IPMI_FAN_LED_GREEN, + self.STATUS_LED_COLOR_AMBER: IPMI_FAN_LED_AMBER, + self.STATUS_LED_COLOR_RED: IPMI_FAN_LED_AMBER, + self.STATUS_LED_COLOR_OFF: IPMI_FAN_LED_OFF + }.get(color) + status, set_led = self._api_helper.ipmi_raw( + IPMI_OEM_NETFN, IPMI_SET_FAN_LED_CMD.format(self.led_number, led_color)) + if status: + set_status_led = True + self.led_set = color + else: + set_status_led = False + + return set_status_led + + def get_status_led(self): + """ + Gets the state of the fan status LED + + Returns: + A string, one of the predefined STATUS_LED_COLOR_* strings above + """ + if self.is_psu_fan: + # Not support + return NOT_AVAILABLE + + status, hx_color = self._api_helper.ipmi_raw( + IPMI_OEM_NETFN, IPMI_GET_FAN_LED_CMD.format(self.led_number)) + # there are only green and red led on fan + status_led = { + "00": self.STATUS_LED_COLOR_OFF, + "01": self.STATUS_LED_COLOR_GREEN, + "02": self.STATUS_LED_COLOR_RED, + }.get(hx_color, self.STATUS_LED_COLOR_OFF) + + # if it was set AMBER then return AMBER + if status_led == self.STATUS_LED_COLOR_RED: + if self.led_set == self.STATUS_LED_COLOR_AMBER: + status_led = self.STATUS_LED_COLOR_AMBER + + return status_led + + def get_name(self): + """ + Retrieves the name of the device + + Returns: + string: The name of the device + """ + if self.is_psu_fan: + fan_name = "PSU {} FAN-{}".format(self.psu_index+1, self.index+1) + else: + fan_name = FAN_NAME_LIST[self.index] + + return fan_name + + def get_presence(self): + """ + Retrieves the presence of the FAN + Returns: + bool: True if FAN is present, False if not + """ + if self.is_psu_fan: + presence = self.psu.get_presence() + return presence + + rpm_speed = self.get_speed_rpm() + if rpm_speed == 0: + presence = False + else: + presence = True + + return presence + + def get_model(self): + """ + Retrieves the model number (or part number) of the device + Returns: + string: Model/part number of device + """ + if self.is_psu_fan: + model = self.psu.get_model() + else: + model = "Unknown" + + return model + + def get_serial(self): + """ + Retrieves the serial number of the device + Returns: + string: Serial number of device + """ + if self.is_psu_fan: + serial = self.psu.get_serial() + else: + serial = "Unknown" + + return serial + + def get_status(self): + """ + Retrieves the operational status of the device + Returns: + A boolean value, True if device is operating properly, False if not + """ + if self.is_psu_fan: + # psu status dose not include psu fan status + # follow PWS-1K62A-1R HW P2 11122014.pdf defined slow fan (<1200rpm) + rpm = self.get_speed_rpm() + status = (rpm >= 1200) + return status + else: + return self.get_presence() and self.get_speed() > 0 + + def get_position_in_parent(self): + """ + Retrieves 1-based relative physical position in parent device. If the agent cannot determine the parent-relative position + for some reason, or if the associated value of entPhysicalContainedIn is '0', then the value '-1' is returned + Returns: + integer: The 1-based relative physical position in parent device or -1 if cannot determine the position + """ + return (self.index + 1) + + def is_replaceable(self): + """ + Indicate whether this device is replaceable. + Returns: + bool: True if it is replaceable. + """ + if self.is_psu_fan: + replaceable = self.psu.is_replaceable() + return replaceable + else: + return True diff --git a/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/sonic_platform/fan_drawer.py b/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/sonic_platform/fan_drawer.py new file mode 100644 index 000000000000..9ead756023a9 --- /dev/null +++ b/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/sonic_platform/fan_drawer.py @@ -0,0 +1,121 @@ +#!/usr/bin/env python + +############################################################################# +# Celestica +# +# Module contains an implementation of SONiC Platform Base API and +# provides the the Fan-Drawers' information available in the platform +# +############################################################################# + +try: + from sonic_platform_base.fan_drawer_base import FanDrawerBase +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + +NUM_FAN = 1 + + +class FanDrawer(FanDrawerBase): + def __init__(self, fantray_index): + FanDrawerBase.__init__(self) + self._index = fantray_index + 1 + self._init_fan(fantray_index) + + def _init_fan(self, fantray_index): + from sonic_platform.fan import Fan + self.PWN_LIST = [0, 1, 0, 1, 2, 2] # TODO: will change in next HW version + for index in range(NUM_FAN): + pwn = self.PWN_LIST[fantray_index] + fan = Fan(pwn, fantray_index) + self._fan_list.append(fan) + + def set_status_led(self, color): + """ + Sets the state of the fan drawer status LED + Args: + color: A string representing the color with which to set the + fan drawer status LED + Returns: + bool: True if status LED state is set successfully, False if not + """ + return self._fan_list[0].set_status_led(color) + + def get_status_led(self, color=None): + """ + Gets the state of the fan drawer LED + Returns: + A string, one of the predefined STATUS_LED_COLOR_* strings above + """ + return self._fan_list[0].get_status_led() + + def get_maximum_consumed_power(self): + """ + Retrives the maximum power drawn by Fan Drawer + + Returns: + A float, with value of the maximum consumable power of the + component. + """ + return 30.24 # by Eddie + + ############################################################## + ###################### Device methods ######################## + ############################################################## + + def get_name(self): + """ + Retrieves the name of the device + Returns: + string: The name of the device + """ + return "Drawer{}".format(self._index) + + def get_presence(self): + """ + Retrieves the presence of the device + Returns: + bool: True if device is present, False if not + """ + return self._fan_list[0].get_presence() + + def get_model(self): + """ + Retrieves the model number (or part number) of the device + Returns: + string: Model/part number of device + """ + return self._fan_list[0].get_model() + + def get_serial(self): + """ + Retrieves the serial number of the device + Returns: + string: Serial number of device + """ + return self._fan_list[0].get_serial() + + def get_status(self): + """ + Retrieves the operational status of the device + Returns: + A boolean value, True if device is operating properly, False if not + """ + return self._fan_list[0].get_status() + + def get_position_in_parent(self): + """ + Retrieves 1-based relative physical position in parent device. If the agent cannot determine the parent-relative position + for some reason, or if the associated value of entPhysicalContainedIn is '0', then the value '-1' is returned + Returns: + integer: The 1-based relative physical position in parent device or -1 if cannot determine the position + """ + return self._index + + def is_replaceable(self): + """ + Indicate whether this device is replaceable. + Returns: + bool: True if it is replaceable. + """ + return True diff --git a/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/sonic_platform/helper.py b/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/sonic_platform/helper.py new file mode 100644 index 000000000000..7acdedb5fabe --- /dev/null +++ b/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/sonic_platform/helper.py @@ -0,0 +1,108 @@ +import os +import struct +import subprocess +from mmap import * + +HOST_CHK_CMD = "docker > /dev/null 2>&1" +EMPTY_STRING = "" + + +class APIHelper(): + + def __init__(self): + pass + + def is_host(self): + return os.system(HOST_CHK_CMD) == 0 + + def pci_get_value(self, resource, offset): + status = True + result = "" + try: + fd = os.open(resource, os.O_RDWR) + mm = mmap(fd, 0) + mm.seek(int(offset)) + read_data_stream = mm.read(4) + result = struct.unpack('I', read_data_stream) + except Exception as e: + status = False + return status, result + + def run_command(self, cmd): + status = True + result = "" + try: + p = subprocess.Popen( + cmd, shell=True, universal_newlines=True, stdout=subprocess.PIPE, stderr=subprocess.PIPE) + raw_data, err = p.communicate() + if err == '': + result = raw_data.strip() + except Exception as e: + status = False + return status, result + + def run_interactive_command(self, cmd): + try: + os.system(cmd) + except Exception as e: + return False + return True + + def read_txt_file(self, file_path): + try: + with open(file_path, 'r') as fd: + data = fd.read() + return data.strip() + except IOError: + pass + return None + + def ipmi_raw(self, netfn, cmd): + status = True + result = "" + try: + cmd = ["ipmitool raw {} {}".format(str(netfn), str(cmd))] + p = subprocess.Popen( + cmd, shell=True, universal_newlines=True, stdout=subprocess.PIPE, stderr=subprocess.PIPE) + raw_data, err = p.communicate() + if err == '': + result = raw_data.strip() + else: + status = False + except Exception as e: + status = False + return status, result + + def ipmi_fru_id(self, id, key=None): + status = True + result = "" + try: + cmd = ["ipmitool fru print {}".format(str( + id))] if not key else ["ipmitool fru print {0} | grep '{1}' ".format(str(id), str(key))] + + p = subprocess.Popen( + cmd, shell=True, universal_newlines=True, stdout=subprocess.PIPE, stderr=subprocess.PIPE) + raw_data, err = p.communicate() + if err == '': + result = raw_data.strip() + else: + status = False + except Exception as e: + status = False + return status, result + + def ipmi_set_ss_thres(self, id, threshold_key, value): + status = True + result = "" + try: + cmd = ["ipmitool sensor thresh '{}' {} {}".format(str(id), str(threshold_key), str(value))] + p = subprocess.Popen( + cmd, shell=True, universal_newlines=True, stdout=subprocess.PIPE, stderr=subprocess.PIPE) + raw_data, err = p.communicate() + if err == '': + result = raw_data.strip() + else: + status = False + except Exception as e: + status = False + return status, result diff --git a/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/sonic_platform/pcie.py b/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/sonic_platform/pcie.py new file mode 100644 index 000000000000..6901f62ea856 --- /dev/null +++ b/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/sonic_platform/pcie.py @@ -0,0 +1,18 @@ +############################################################################# +# SuperMicro SSE-T7132S +# +# Module contains an implementation of SONiC Platform Base API and +# provides the PCIe information which are available in the platform +# +############################################################################# + +try: + from sonic_platform_base.sonic_pcie.pcie_common import PcieUtil +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + + +class Pcie(PcieUtil): + """ T7132S Platform-specific PCIe class """ + """ fallback to pcie_common.PcieUtil to avoid pcieutil warning message """ + diff --git a/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/sonic_platform/platform.py b/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/sonic_platform/platform.py new file mode 100644 index 000000000000..7d5424dc9419 --- /dev/null +++ b/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/sonic_platform/platform.py @@ -0,0 +1,21 @@ +############################################################################# +# SuperMicro SSE-T7132S +# +# Module contains an implementation of SONiC Platform Base API and +# provides the platform information +# +############################################################################# + +try: + from sonic_platform_base.platform_base import PlatformBase + from sonic_platform.chassis import Chassis +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + + +class Platform(PlatformBase): + """Platform-specific Platform class""" + + def __init__(self): + PlatformBase.__init__(self) + self._chassis = Chassis() diff --git a/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/sonic_platform/psu.py b/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/sonic_platform/psu.py new file mode 100644 index 000000000000..1a77b75f7415 --- /dev/null +++ b/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/sonic_platform/psu.py @@ -0,0 +1,545 @@ +############################################################################# +# SuperMicro SSE-T7132S +# +# Module contains an implementation of SONiC Platform Base API and +# provides the PSUs status which are available in the platform +# +############################################################################# + +import re + +try: + from sonic_platform_base.psu_base import PsuBase + from .helper import APIHelper + from sonic_platform.fan import Fan + from sonic_platform_base.thermal_base import ThermalBase +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + +PSU_NAME_LIST = ["PSU_1", "PSU_2"] +PSU_NUM_FAN = [1, 1] +PSU_NUM_TERMAL = [2, 2] + +IPMI_SENSOR_NETFN = "0x04" +IPMI_OEM_NETFN = "0x30" +IPMI_SS_READ_CMD = "0x2D {}" +IPMI_OEM_CMD = "0x89 {}" +IPMI_PSU_TYPE_CMD = "0x1 {}" +IPMI_GET_PSU_LED_MODE_CMD = "0x2 0x1" +IPMI_SET_PSU_LED_MODE_CMD = "0x2 0x2 {}" +IPMI_GET_PSU_LED_PATTERN_CMD = "0x3 0x0 {}" +IPMI_SET_PSU_LED_PATTERN_CMD = "0x3 0x1 {} {}" +IPMI_PSU_INFO_CMD= "0x4 {} {}" + +PSU_LED_OFF_CMD = "0x00" +PSU_LED_GREEN_CMD = "0x01" +PSU_LED_AMBER_CMD = "0x02" + +PSU_SERIAL_CMD = "0x00" +PSU_MODEL_CMD = "0x01" +PSU_VOUT_CMD = "0x02" +PSU_COUT_CMD = "0x03" +PSU_POUT_CMD = "0x04" +PSU_VIN_CMD = "0x05" +PSU_CIN_CMD = "0x06" +PSU_PIN_CMD = "0x07" +PSU_FAN1_CMD = "0x08" +PSU_FAN2_CMD = "0x09" +PSU_TEMP1_CMD = "0x0A" +PSU_TEMP2_CMD = "0x0B" +PSU_MAX_TEMP1_CMD = "0x0C" +PSU_MAX_TEMP2_CMD = "0x0D" +PSU_MAX_POUT_CMD = "0x0E" + +PSU1_STATUS_REG = "0xC4" +PSU2_STATUS_REG = "0xC5" + +PSU1_FRU_ID = 3 + +PSU_OUT_VOLTAGE = 12 + +SS_READ_OFFSET = 0 +OEM_READ_OFFSET = 0 + + +class Psu(PsuBase): + """Platform-specific Psu class""" + + def __init__(self, psu_index): + PsuBase.__init__(self) + self.index = psu_index + for fan_index in range(0, PSU_NUM_FAN[self.index]): + fan = Fan(0, fan_index, is_psu_fan=True, psu=self) + self._fan_list.append(fan) + for thermal_index in range(0, PSU_NUM_TERMAL[self.index]): + self._thermal_list.append(PsuThermal(self, thermal_index)) + self._api_helper = APIHelper() + + def find_value(self, in_string): + result = re.search("^.+ ([0-9a-f]{2}) .+$", in_string) + return result.group(1) if result else result + + def get_voltage(self): + """ + Retrieves current PSU voltage output + Returns: + A float number, the output voltage in volts, + e.g. 12.1 + """ + psu_voltage = 0.0 + psu_vout_key = IPMI_PSU_INFO_CMD.format(self.index+1, PSU_VOUT_CMD) + status, raw_oem_read = self._api_helper.ipmi_raw( + IPMI_OEM_NETFN, IPMI_OEM_CMD.format(psu_vout_key)) + + if raw_oem_read: + # Formula: R/10 + psu_voltage = int("".join(raw_oem_read.split()[::-1]), 16) / 10 + + return psu_voltage + + def get_voltage_high_threshold(self): + """ + Retrieves the high threshold PSU voltage output + Returns: + A float number, the high threshold output voltage in volts, + e.g. 12.1 + """ + # Formula: PSU_OUT_VOLTAGEx11/10 + psu_voltage = PSU_OUT_VOLTAGE * 11 / 10 + + return psu_voltage + + def get_voltage_low_threshold(self): + """ + Retrieves the low threshold PSU voltage output + Returns: + A float number, the low threshold output voltage in volts, + e.g. 12.1 + """ + # Formula: PSU_OUT_VOLTAGEx9/10 + psu_voltage = PSU_OUT_VOLTAGE * 9 / 10 + + return psu_voltage + + def get_current(self): + """ + Retrieves present electric current supplied by PSU + Returns: + A float number, the electric current in amperes, e.g 15.4 + """ + psu_current = 0.0 + psu_cout_key = IPMI_PSU_INFO_CMD.format(self.index+1, PSU_COUT_CMD) + status, raw_oem_read = self._api_helper.ipmi_raw( + IPMI_OEM_NETFN, IPMI_OEM_CMD.format(psu_cout_key)) + + if raw_oem_read: + # Formula: R/1000 + psu_current = int("".join(raw_oem_read.split()[::-1]), 16) / 1000 + + return psu_current + + def get_power(self): + """ + Retrieves current energy supplied by PSU + Returns: + A float number, the power in watts, e.g. 302.6 + """ + psu_power = 0.0 + psu_pout_key = IPMI_PSU_INFO_CMD.format(self.index+1, PSU_POUT_CMD) + status, raw_oem_read = self._api_helper.ipmi_raw( + IPMI_OEM_NETFN, IPMI_OEM_CMD.format(psu_pout_key)) + + if raw_oem_read: + # Formula: R + psu_power = int("".join(raw_oem_read.split()[::-1]), 16) + return psu_power + + def get_maximum_supplied_power(self): + """ + Retrieves the maximum supplied power by PSU + Returns: + A float number, the maximum power output in Watts. + e.g. 1200.1 + """ + psu_power = 0.0 + psu_pout_key = IPMI_PSU_INFO_CMD.format(self.index+1, PSU_MAX_POUT_CMD) + status, raw_oem_read = self._api_helper.ipmi_raw( + IPMI_OEM_NETFN, IPMI_OEM_CMD.format(psu_pout_key)) + + if raw_oem_read: + # Formula: R + psu_power = int("".join(raw_oem_read.split()[::-1]), 16) + return psu_power + + def get_powergood_status(self): + """ + Retrieves the powergood status of PSU + Returns: + A boolean, True if PSU has stablized its output voltages and passed all + its internal self-tests, False if not. + """ + return self.get_status() + + def set_status_led(self, color): + """ + Sets the state of the PSU status LED + Args: + color: A string representing the color with which to set the PSU status LED + Note: Only support green and off + Returns: + bool: True if status LED state is set successfully, False if not + Note + """ + led_cmd = { + self.STATUS_LED_COLOR_GREEN: PSU_LED_GREEN_CMD, + "orange": PSU_LED_AMBER_CMD, + self.STATUS_LED_COLOR_OFF: PSU_LED_OFF_CMD + }.get(color) + + psu_led_key = IPMI_SET_PSU_LED_PATTERN_CMD.format(self.index+2,led_cmd) + status, set_led = self._api_helper.ipmi_raw( + IPMI_OEM_NETFN, IPMI_OEM_CMD.format(psu_led_key)) + set_status_led = False if not status else True + + return set_status_led + + def get_status_led(self): + """ + Gets the state of the PSU status LED + Returns: + A string, one of the predefined STATUS_LED_COLOR_* strings above + """ + psu_led_key = IPMI_GET_PSU_LED_PATTERN_CMD.format(self.index+2) + status, hx_color = self._api_helper.ipmi_raw( + IPMI_OEM_NETFN, IPMI_OEM_CMD.format(psu_led_key)) + + status_led = { + "00": self.STATUS_LED_COLOR_OFF, + "01": self.STATUS_LED_COLOR_GREEN, + "02": "orange", + }.get(hx_color, self.STATUS_LED_COLOR_OFF) + + return status_led + + def get_temperature(self): + """ + Retrieves current temperature reading from PSU + Returns: + A float number of current temperature in Celsius up to nearest thousandth + of one degree Celsius, e.g. 30.125 + there are three temp sensors , we choose one of them + """ + # Need implement after BMC function ready + psu_temperature = None + + return psu_temperature + + def get_temperature_high_threshold(self): + """ + Retrieves the high threshold temperature of PSU + Returns: + A float number, the high threshold temperature of PSU in Celsius + up to nearest thousandth of one degree Celsius, e.g. 30.125 + there are three temp sensors , we choose one of them + """ + # Need implement after BMC function ready + psu_temperature = None + + return psu_temperature + + def get_name(self): + """ + Retrieves the name of the device + Returns: + string: The name of the device + """ + return PSU_NAME_LIST[self.index] + + def get_presence(self): + """ + Retrieves the presence of the PSU + Returns: + bool: True if PSU is present, False if not + """ + psu_presence = False + psu_pstatus_key = globals()['PSU{}_STATUS_REG'.format(self.index+1)] + status, raw_status_read = self._api_helper.ipmi_raw( + IPMI_SENSOR_NETFN, IPMI_SS_READ_CMD.format(psu_pstatus_key)) + status_byte = self.find_value(raw_status_read) + + if status: + presence_int = (int(status_byte, 16) >> 0) & 1 + psu_presence = True if presence_int else False + + return psu_presence + + def get_model(self): + """ + Retrieves the model number (or part number) of the device + Returns: + string: Model/part number of device + """ + model = "Unknown" + psu_model_key = IPMI_PSU_INFO_CMD.format(self.index+1, PSU_MODEL_CMD) + status, raw_model = self._api_helper.ipmi_raw( + IPMI_OEM_NETFN, IPMI_OEM_CMD.format(psu_model_key)) + + model_raw_list = raw_model.split() + if len(model_raw_list) > 0: + model="".join(map(chr,map(lambda x: int(x, 16), model_raw_list))) + return model + + def get_serial(self): + """ + Retrieves the serial number of the device + Returns: + string: Serial number of device + """ + serial = "Unknown" + psu_serial_key = IPMI_PSU_INFO_CMD.format(self.index+1, PSU_SERIAL_CMD) + status, raw_serial = self._api_helper.ipmi_raw( + IPMI_OEM_NETFN, IPMI_OEM_CMD.format(psu_serial_key)) + + serial_raw_list = raw_serial.split() + if len(serial_raw_list) > 0: + serial="".join(map(chr,map(lambda x: int(x, 16), serial_raw_list))) + + return serial + + def get_status(self): + """ + Retrieves the operational status of the device + Returns: + A boolean value, True if device is operating properly, False if not + """ + psu_status = False + psu_pstatus_key = globals()['PSU{}_STATUS_REG'.format(self.index+1)] + status, raw_status_read = self._api_helper.ipmi_raw( + IPMI_SENSOR_NETFN, IPMI_SS_READ_CMD.format(psu_pstatus_key)) + status_byte = self.find_value(raw_status_read) + + if status: + failure_detected = (int(status_byte, 16) >> 1) & 1 + input_lost = (int(status_byte, 16) >> 3) & 1 + psu_status = False if (input_lost or failure_detected) else True + + return psu_status + + def get_type(self): + """ + Retrives the Power Type of PSU + + Returns : + A string, PSU power type + """ + psu_type = [None, 'AC', 'AC', 'DC'] + psu_type_key = IPMI_PSU_TYPE_CMD.format(self.index+1) + status, raw_type_read = self._api_helper.ipmi_raw( + IPMI_OEM_NETFN, IPMI_OEM_CMD.format(psu_type_key)) + if status: + raw_type = raw_type_read.split()[OEM_READ_OFFSET] + type_index = int(raw_type, 16) + if type_index < 4: + return psu_type[type_index] + return None + + def get_position_in_parent(self): + """ + Retrieves 1-based relative physical position in parent device. + Returns: + integer: The 1-based relative physical position in parent + device or -1 if cannot determine the position + """ + return self.index + + def is_replaceable(self): + """ + Indicate whether this PSU is replaceable. + Returns: + bool: True if it is replaceable. + """ + return True + + + def get_num_thermals(self): + """ + Retrieves the number of thermals available on this PSU + + Returns: + An integer, the number of thermals available on this PSU + """ + return len(self._thermal_list) + + def get_all_thermals(self): + """ + Retrieves all thermals available on this PSU + + Returns: + A list of objects derived from ThermalBase representing all thermals + available on this PSU + """ + return self._thermal_list + + def get_thermal(self, index): + """ + Retrieves thermal unit represented by (0-based) index + + Args: + index: An integer, the index (0-based) of the thermal to + retrieve + + Returns: + An object derived from ThermalBase representing the specified thermal + """ + thermal = None + + try: + thermal = self._thermal_list[index] + except IndexError: + sys.stderr.write("THERMAL index {} out of range (0-{})\n".format( + index, len(self._thermal_list)-1)) + + return thermal + +class PsuThermal(ThermalBase): + """Platform-specific Thermal class for PSU """ + + def __init__(self, psu, index): + self._api_helper = APIHelper() + self.psu = psu + self.index = index + self.minimum_thermal = 999 + self.maximum_thermal = 0 + + def get_temperature(self): + """ + Retrieves current temperature reading from thermal + + Returns: + A float number of current temperature in Celsius up to nearest thousandth + of one degree Celsius, e.g. 30.125 + """ + if self.psu.get_presence() != True: + return None + + psu_temperature = 0.0 + psu_temp_cmd_key = globals()['PSU_TEMP{}_CMD'.format(self.index+1)] + psu_temp_key = IPMI_PSU_INFO_CMD.format(self.psu.index+1, psu_temp_cmd_key) + status, raw_oem_read = self._api_helper.ipmi_raw( + IPMI_OEM_NETFN, IPMI_OEM_CMD.format(psu_temp_key)) + + if raw_oem_read: + # Formula: R + psu_temperature = int("".join(raw_oem_read.split()[::-1]), 16) + + if psu_temperature > self.maximum_thermal: + self.maximum_thermal = psu_temperature + if psu_temperature < self.minimum_thermal: + self.minimum_thermal = psu_temperature + + return psu_temperature + + def get_high_threshold(self): + """ + Retrieves the high threshold temperature of thermal + + Returns: + A float number, the high threshold temperature of thermal in Celsius + up to nearest thousandth of one degree Celsius, e.g. 30.125 + """ + # ignore max_temp 1 to aviod false alarm because PSU fan control is not ready + if self.index == 0: + return None + + if self.get_presence() != True: + return None + + psu_temper_high = 0.0 + psu_temp_cmd_key = globals()['PSU_MAX_TEMP{}_CMD'.format(self.index+1)] + psu_temp_key = IPMI_PSU_INFO_CMD.format(self.psu.index+1, psu_temp_cmd_key) + status, raw_oem_read = self._api_helper.ipmi_raw( + IPMI_OEM_NETFN, IPMI_OEM_CMD.format(psu_temp_key)) + + if raw_oem_read: + # Formula: R + psu_temper_high = int("".join(raw_oem_read.split()[::-1]), 16) + + return psu_temper_high + + def get_minimum_recorded(self): + """ + Retrieves the minimum recorded temperature of thermal + + Returns: + A float number, the minimum recorded temperature of thermal in Celsius + up to nearest thousandth of one degree Celsius, e.g. 30.125 + """ + return self.minimum_thermal; + + def get_maximum_recorded(self): + """ + Retrieves the maximum recorded temperature of thermal + + Returns: + A float number, the maximum recorded temperature of thermal in Celsius + up to nearest thousandth of one degree Celsius, e.g. 30.125 + """ + return self.maximum_thermal + + def get_name(self): + """ + Retrieves the name of the thermal device + Returns: + string: The name of the thermal device + """ + return '{}_TEMP_{}'.format(self.psu.get_name(), self.index+1) + + def get_presence(self): + """ + Retrieves the presence of the device + Returns: + bool: True if device is present, False if not + """ + return self.psu.get_presence() + + def get_model(self): + """ + Retrieves the model number (or part number) of the device + Returns: + string: Model/part number of device + """ + return self.psu.get_model() + + def get_serial(self): + """ + Retrieves the serial number of the device + Returns: + string: Serial number of device + """ + return self.psu.get_serial() + + def get_status(self): + """ + Retrieves the operational status of the device + Returns: + A boolean value, True if device is operating properly, False if not + """ + return self.psu.get_status() + + def get_position_in_parent(self): + """ + Retrieves 1-based relative physical position in parent device. + Returns: + integer: The 1-based relative physical position in parent + device or -1 if cannot determine the position + """ + return (self.index + 1) + + def is_replaceable(self): + """ + Indicate whether this Thermal is replaceable. + Returns: + bool: True if it is replaceable. + """ + return False + diff --git a/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/sonic_platform/sfp.py b/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/sonic_platform/sfp.py new file mode 100644 index 000000000000..3bb0d7fdda33 --- /dev/null +++ b/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/sonic_platform/sfp.py @@ -0,0 +1,444 @@ +#!/usr/bin/env python +""" +############################################################################# +# SuperMicro SSE-T7132S +# +# Sfp contains an implementation of SONiC Platform Base API and +# provides the sfp status which are available in the platform +# +############################################################################# +""" + +try: + import os + import time + from sonic_platform_base.sonic_xcvr.sfp_optoe_base import SfpOptoeBase + +except ImportError as err: + raise ImportError(str(err) + "- required module not found") + +QSFP_INFO_OFFSET = 128 +SFP_INFO_OFFSET = 0 +QSFP_DD_PAGE0 = 0 + +SFP_TYPE_LIST = [ + '0x3' # SFP/SFP+/SFP28 and later +] +QSFP_TYPE_LIST = [ + '0x0c', # QSFP + '0x0d', # QSFP+ or later + '0x11' # QSFP28 or later +] +QSFP_DD_TYPE_LIST = [ + '0x18' #QSFP_DD Type +] + +OSFP_TYPE_LIST = [ + '0x19' # OSFP 8X Type +] + +SFP_TYPE = "SFP" +QSFP_TYPE = "QSFP" +OSFP_TYPE = "OSFP" +QSFP_DD_TYPE = "QSFP_DD" +SFP_NAME = "Ethernet{}" + +PORT_START = 0 +PORT_END = 34 +QSFP_PORT_START = 0 +QSFP_PORT_END = 32 + +I2C_EEPROM_PATH = '/sys/bus/i2c/devices/i2c-{0}/{0}-0050/eeprom' +PORT_INFO_PATH= '/sys/class/t7132s_cpld' + +class Sfp(SfpOptoeBase): + """Platform-specific Sfp class""" + PLATFORM = "x86_64-supermicro_sse_t7132s-r0" + HWSKU = "Supermicro_sse_t7132s" + + _port_to_offset = [11, 30, 12, 29, 13, 28, 14, 27, 15, 34, + 16, 33, 17, 32, 18, 31, 19, 38, 20, 37, + 21, 36, 22, 35, 23, 42, 24, 41, 25, 40, + 26, 39, + 43, 44] + + def __init__(self, sfp_index=0): + SfpOptoeBase.__init__(self) + + self.index = sfp_index # for sfputil show error-status --fetch-from-hardware + self._master_port = self.index - 1 + self._port_num = self.index + self.sfp_type = QSFP_DD_TYPE + #port_type is the native port type and sfp_type is the transceiver type + #sfp_type will be detected in get_transceiver_info + if self._master_port < QSFP_PORT_END: + self.port_type = QSFP_DD_TYPE + self.NUM_CHANNELS = 8 + self.port_name = "QSFP" + str(self._port_num) + self._name = [SFP_NAME.format(str(self._master_port*8))] + else: + self.port_type = SFP_TYPE + self.NUM_CHANNELS = 1 + self.port_name = "SFP" + str(self._port_num - QSFP_PORT_END) + self._name = [SFP_NAME.format(str((QSFP_PORT_END*8)+(self._master_port - QSFP_PORT_END)))] + self.sfp_type = self.port_type + self.sfp_eeprom_path = self.get_eeprom_path() + self._initialize_media(delay=False) + + def _detect_sfp_type(self): + eeprom_raw = [] + eeprom_ready = True + + time_begin = time.time() + eeprom_ready = False + while (time.time() - time_begin) < 4: + # read 2 more bytes to check eeprom ready + eeprom_raw = self.read_eeprom(XCVR_TYPE_OFFSET, XCVR_TYPE_WIDTH + 2) + + if eeprom_raw: + if eeprom_raw[0] in SFP_TYPE_CODE_LIST: + self.sfp_type = SFP_TYPE + eeprom_ready = True + elif eeprom_raw[0] in QSFP_TYPE_CODE_LIST: + self.sfp_type = QSFP_TYPE + eeprom_ready = True + elif eeprom_raw[0] in QSFP_DD_TYPE_CODE_LIST: + self.sfp_type = QSFP_DD_TYPE + eeprom_ready = True + else: + self.sfp_type = self.port_type + if all([b == '00' for b in eeprom_raw]): + logger.Logger('SFP').log_warning( + "_detect_sfp_type: {} index {} by {} eeprom all 0". + format(self._name, self.index, + inspect.currentframe().f_back.f_code.co_name)) + else: + eeprom_ready = True + else: + logger.Logger('SFP').log_warning( + "_detect_sfp_type: {} index {} by {} eeprom none". + format(self._name, self.index, + inspect.currentframe().f_back.f_code.co_name)) + self.sfp_type = self.port_type + + if not eeprom_ready: + # retry after sleep + time.sleep(1) + else: + break; + + if self.sfp_type == QSFP_DD_TYPE: + self.NUM_CHANNELS = 8 + elif self.sfp_type == QSFP_TYPE: + self.NUM_CHANNELS = 4 + elif self.sfp_type == SFP_TYPE: + self.NUM_CHANNELS = 1 + + return eeprom_ready + + def get_eeprom_path(self): + """ + Returns SFP eeprom path + """ + port_eeprom_path = I2C_EEPROM_PATH.format(self._port_to_offset[self._master_port]) + return port_eeprom_path + + def get_name(self): + """ + Retrieves the name of the device + Returns: + string: The name of the device + """ + return self._name[0] + + def _initialize_media(self, delay=False): + """ + Initialize the media type and eeprom driver for SFP + """ + if delay: + time.sleep(1) + self._xcvr_api = None + self.get_xcvr_api() + + self.set_media_type() + self.reinit_sfp_driver() + + def get_presence(self): + """ + Retrieves the presence of the SFP + Returns: + bool: True if SFP is present, False if not + """ + sysfs_filename = "sfp_modabs" if self.port_type == SFP_TYPE else "qsfp_modprs" + reg_path = "/".join([PORT_INFO_PATH, self.port_name, sysfs_filename]) + + # Read status + try: + with open(reg_path) as reg_file: + content = reg_file.readline().rstrip() + reg_value = int(content) + # Module present is active low + if reg_value == 0: + return True + except IOError as e: + print("Error: unable to open file: %s" % str(e)) + return False + + # not present + return False + + def get_reset_status(self): + """ + Retrieves the reset status of SFP + Returns: + A Boolean, True if reset enabled, False if disabled + """ + if self.port_type != QSFP_DD_TYPE: + return False + + try: + with open( + "/".join([PORT_INFO_PATH, self.port_name, "qsfp_reset"])) as reg_file: + # Read status + content = reg_file.readline().rstrip() + reg_value = int(content) + # reset is active low + if reg_value == 0: + return True + except IOError as e: + print("Error: unable to open file: %s" % str(e)) + return False + + return False + + def get_lpmode(self): + """ + Retrieves the lpmode (low power mode) status of this SFP + Returns: + A Boolean, True if lpmode is enabled, False if disabled + """ + if self.port_type != QSFP_DD_TYPE: + return False + + try: + with open( + "/".join([PORT_INFO_PATH, self.port_name, "qsfp_lpmode"])) as reg_file: + # Read status + content = reg_file.readline().rstrip() + reg_value = int(content) + # low power mode is active high + if reg_value == 0: + return False + except IOError as e: + print("Error: unable to open file: %s" % str(e)) + return False + + return True + + def reset(self): + """ + Reset SFP and return all user module settings to their default srate. + Returns: + A boolean, True if successful, False if not + """ + if self.port_type != QSFP_DD_TYPE: + return False + + try: + with open( + "/".join([PORT_INFO_PATH, self.port_name, "qsfp_reset"]), "w") as reg_file: + # Convert our register value back to a hex string and write back + reg_file.seek(0) + reg_file.write(hex(0)) + except IOError as e: + print("Error: unable to open file: %s" % str(e)) + return False + + # Sleep 1 second to allow it to settle + time.sleep(1) + + # Flip the bit back high and write back to the register to take port out of reset + try: + with open( + "/".join([PORT_INFO_PATH, self.port_name, "qsfp_reset"]), "w") as reg_file: + reg_file.seek(0) + reg_file.write(hex(1)) + except IOError as e: + print("Error: unable to open file: %s" % str(e)) + return False + + return True + + def no_reset(self): + """ + Set CPLD qsfp_reset to 1 for non-reset status. + Returns: + A boolean, True if successful, False if not + """ + if self.port_type != QSFP_DD_TYPE: + return False + + try: + with open( + "/".join([PORT_INFO_PATH, self.port_name, "qsfp_reset"]), "w") as reg_file: + reg_file.seek(0) + reg_file.write(hex(1)) + except IOError as e: + print("Error: unable to open file: %s" % str(e)) + return False + + return True + + def set_lpmode(self, lpmode): + """ + Sets the lpmode (low power mode) of SFP + Args: + lpmode: A Boolean, True to enable lpmode, False to disable it + Note : lpmode can be overridden by set_power_override + Returns: + A boolean, True if lpmode is set successfully, False if not + """ + if not self._detect_sfp_type(): + return False + + if self.port_type != QSFP_DD_TYPE: + return False + + try: + reg_file = open( + "/".join([PORT_INFO_PATH, self.port_name, "qsfp_lpmode"]), "r+") + except IOError as e: + print("Error: unable to open file: %s" % str(e)) + return False + + content = hex(lpmode) + + reg_file.seek(0) + reg_file.write(content) + reg_file.close() + + return True + + def set_media_type(self): + """ + Reads optic eeprom byte to determine media type inserted + """ + eeprom_raw = [] + eeprom_raw = self._xcvr_api_factory._get_id() + if eeprom_raw is not None: + eeprom_raw = hex(eeprom_raw) + if eeprom_raw in SFP_TYPE_LIST: + self.sfp_type = SFP_TYPE + elif eeprom_raw in QSFP_TYPE_LIST: + self.sfp_type = QSFP_TYPE + elif eeprom_raw in QSFP_DD_TYPE_LIST: + self.sfp_type = QSFP_DD_TYPE + else: + #Set native port type if EEPROM type is not recognized/readable + self.sfp_type = self.port_type + else: + self.sfp_type = self.port_type + + return self.sfp_type + + def reinit_sfp_driver(self): + """ + Changes the driver based on media type detected + """ + + i2c_bus = self.sfp_eeprom_path[25:].split('/')[0] + del_sfp_path = "/sys/bus/i2c/devices/i2c-{0}/delete_device".format(i2c_bus) + new_sfp_path = "/sys/bus/i2c/devices/i2c-{0}/new_device".format(i2c_bus) + driver_path = "/sys/bus/i2c/devices/i2c-{0}/{0}-0050/name".format(i2c_bus) + + if not os.path.isfile(driver_path): + print(driver_path, "does not exist") + return False + + try: + with os.fdopen(os.open(driver_path, os.O_RDONLY)) as filed: + driver_name = filed.read() + driver_name = driver_name.rstrip('\r\n') + driver_name = driver_name.lstrip(" ") + + #Avoid re-initialization of the QSFP/SFP optic on QSFP/SFP port. + if self.sfp_type == SFP_TYPE and driver_name in ['optoe1', 'optoe3']: + with open(del_sfp_path, 'w') as f: + f.write('0x50\n') + time.sleep(0.2) + with open(new_sfp_path, 'w') as f: + f.write('optoe2 0x50\n') + time.sleep(2) + elif self.sfp_type == OSFP_TYPE and driver_name in ['optoe2', 'optoe3']: + with open(del_sfp_path, 'w') as f: + f.write('0x50\n') + time.sleep(0.2) + with open(new_sfp_path, 'w') as f: + f.write('optoe1 0x50\n') + time.sleep(2) + elif self.sfp_type == QSFP_DD_TYPE and driver_name in ['optoe1', 'optoe2']: + with open(del_sfp_path, 'w') as f: + f.write('0x50\n') + time.sleep(0.2) + with open(new_sfp_path, 'w') as f: + f.write('optoe3 0x50\n') + time.sleep(2) + + except IOError as err: + print("Error: Unable to open file: %s" %str(err)) + return False + + return True + + def get_position_in_parent(self): + """ + Retrieves 1-based relative physical position in parent device. + Returns: + integer: The 1-based relative physical position in parent + device or -1 if cannot determine the position + """ + return 0 + + @staticmethod + def is_replaceable(): + """ + Indicate whether this device is replaceable. + Returns: + bool: True if it is replaceable. + """ + return True + + def get_error_description(self): + """ + Retrives the error descriptions of the SFP module + + Returns: + String that represents the current error descriptions of vendor specific errors + In case there are multiple errors, they should be joined by '|', + like: "Bad EEPROM|Unsupported cable" + """ + if not self.get_presence(): + return self.SFP_STATUS_UNPLUGGED + else: + if not os.path.isfile(self.sfp_eeprom_path): + return "EEPROM driver is not attached" + + if self.sfp_type == SFP_TYPE: + offset = SFP_INFO_OFFSET + elif self.sfp_type == OSFP_TYPE: + offset = QSFP_INFO_OFFSET + elif self.sfp_type == QSFP_TYPE: + offset = QSFP_INFO_OFFSET + elif self.sfp_type == QSFP_DD_TYPE: + offset = QSFP_DD_PAGE0 + else: + return "Invalid SFP type {}".format(self.sfp_type) + + try: + with open(self.sfp_eeprom_path, mode="rb", buffering=0) as eeprom: + eeprom.seek(offset) + eeprom.read(1) + except OSError as e: + return "EEPROM read failed ({})".format(e.strerror) + + return self.SFP_STATUS_OK \ No newline at end of file diff --git a/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/sonic_platform/thermal.py b/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/sonic_platform/thermal.py new file mode 100644 index 000000000000..38e3b5b7dc84 --- /dev/null +++ b/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/sonic_platform/thermal.py @@ -0,0 +1,253 @@ +############################################################################# +# SuperMicro SSE-T7132S +# +# Thermal contains an implementation of SONiC Platform Base API and +# provides the thermal device status which are available in the platform +# +############################################################################# + +try: + from sonic_platform_base.thermal_base import ThermalBase + from .helper import APIHelper +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + +IPMI_SENSOR_NETFN = "0x04" +IPMI_SS_READ_CMD = "0x2D {}" +IPMI_SS_THRESHOLD_CMD = "0x27 {}" +HIGH_TRESHOLD_SET_KEY = "ucr" +LOW_TRESHOLD_SET_KEY = "lcr" +HIGH_CRIT_TRESHOLD_SET_KEY = "unr" +LOW_CRIT_TRESHOLD_SET_KEY = "lnr" + + +class Thermal(ThermalBase): + """Platform-specific Thermal class""" + + def __init__(self, thermal_index): + ThermalBase.__init__(self) + self._api_helper = APIHelper() + self.index = thermal_index + self.THERMAL_LIST = [ + ('CPU_Temp', 'CPU Temperature Sensor', '0x01'), + ('PCH_Temp', 'PCH Temperature Sensor', '0x0a'), + ('System_Temp', 'System Temperature Sensor', '0x0b'), + ('Peripheral_Temp', 'Peripheral Temperature Sensor', '0x0c'), + ('Switch_Top-1', 'Switchboard Left Inlet Temperature Sensor', '0xb4'), + ('Switch_Buttom-1', 'Switchboard Left Outlet Temperature Sensor', '0xb5'), + ('Switch_Top-2', 'Switchboard Right Inlet Temperature Sensor', '0xb6'), + ('Switch_Buttom-2', 'Switchboard Right Outlet Temperature Sensor','0xb7'), + ('Switch_Temp', 'Switch Temperature Sensor', '0xb8'), + ] + self.sensor_id = self.THERMAL_LIST[self.index][0] + self.sensor_des = self.THERMAL_LIST[self.index][1] + self.sensor_reading_addr = self.THERMAL_LIST[self.index][2] + self.minimum_thermal = self.get_temperature() + self.maximum_thermal = self.get_temperature() + + def __set_threshold(self, key, value): + print('{} {}'.format(key, value)) + + def get_temperature(self): + """ + Retrieves current temperature reading from thermal + Returns: + A float number of current temperature in Celsius up to nearest thousandth + of one degree Celsius, e.g. 30.125 + """ + temperature = 0.0 + status, raw_ss_read = self._api_helper.ipmi_raw( + IPMI_SENSOR_NETFN, IPMI_SS_READ_CMD.format(self.sensor_reading_addr)) + if status and len(raw_ss_read.split()) > 0: + ss_read = raw_ss_read.split()[0] + temperature = float(int(ss_read, 16)) + return temperature + + def get_high_threshold(self): + """ + Retrieves the high threshold temperature of thermal + Returns: + A float number, the high threshold temperature of thermal in Celsius + up to nearest thousandth of one degree Celsius, e.g. 30.125 + """ + high_threshold = 0.0 + status, raw_up_thres_read = self._api_helper.ipmi_raw( + IPMI_SENSOR_NETFN, IPMI_SS_THRESHOLD_CMD.format(self.sensor_reading_addr)) + if status and len(raw_up_thres_read.split()) > 6: + ss_read = raw_up_thres_read.split()[5] + high_threshold = float(int(ss_read, 16)) + return high_threshold + + def get_low_threshold(self): + """ + Retrieves the low threshold temperature of thermal + Returns: + A float number, the low threshold temperature of thermal in Celsius + up to nearest thousandth of one degree Celsius, e.g. 30.125 + """ + low_threshold = 0.0 + status, raw_up_thres_read = self._api_helper.ipmi_raw( + IPMI_SENSOR_NETFN, IPMI_SS_THRESHOLD_CMD.format(self.sensor_reading_addr)) + if status and len(raw_up_thres_read.split()) > 6: + ss_read = raw_up_thres_read.split()[2] + low_threshold = float(int(ss_read, 16)) + return low_threshold + + def set_high_threshold(self, temperature): + """ + Sets the high threshold temperature of thermal + Args : + temperature: A float number up to nearest thousandth of one degree Celsius, + e.g. 30.125 + Returns: + A boolean, True if threshold is set successfully, False if not + """ + status, ret_txt = self._api_helper.ipmi_set_ss_thres(self.sensor_id, HIGH_TRESHOLD_SET_KEY, temperature) + return status + + def set_low_threshold(self, temperature): + """ + Sets the low threshold temperature of thermal + Args : + temperature: A float number up to nearest thousandth of one degree Celsius, + e.g. 30.125 + Returns: + A boolean, True if threshold is set successfully, False if not + """ + status, ret_txt = self._api_helper.ipmi_set_ss_thres(self.sensor_id, LOW_TRESHOLD_SET_KEY, temperature) + return status + + def get_high_critical_threshold(self): + """ + Retrieves the high critical threshold temperature of thermal + Returns: + A float number, the high critical threshold temperature of thermal in Celsius + up to nearest thousandth of one degree Celsius, e.g. 30.125 + """ + high_critical_threshold = 0.0 + status, raw_up_thres_read = self._api_helper.ipmi_raw( + IPMI_SENSOR_NETFN, IPMI_SS_THRESHOLD_CMD.format(self.sensor_reading_addr)) + if status and len(raw_up_thres_read.split()) > 6: + ss_read = raw_up_thres_read.split()[6] + high_critical_threshold = float(int(ss_read, 16)) + return high_critical_threshold + + def get_low_critical_threshold(self): + """ + Retrieves the low critical threshold temperature of thermal + Returns: + A float number, the low critical threshold temperature of thermal in Celsius + up to nearest thousandth of one degree Celsius, e.g. 30.125 + """ + critical_low_threshold = 0.0 + status, raw_up_thres_read = self._api_helper.ipmi_raw( + IPMI_SENSOR_NETFN, IPMI_SS_THRESHOLD_CMD.format(self.sensor_reading_addr)) + if status and len(raw_up_thres_read.split()) > 6: + ss_read = raw_up_thres_read.split()[3] + critical_low_threshold = float(int(ss_read, 16)) + return critical_low_threshold + + def set_high_critical_threshold(self, temperature): + """ + Sets the critical high threshold temperature of thermal + Args : + temperature: A float number up to nearest thousandth of one degree Celsius, + e.g. 30.125 + Returns: + A boolean, True if threshold is set successfully, False if not + """ + status, ret_txt = self._api_helper.ipmi_set_ss_thres(self.sensor_id, HIGH_CRIT_TRESHOLD_SET_KEY, temperature) + return status + + def set_low_critical_threshold(self, temperature): + """ + Sets the critical low threshold temperature of thermal + Args : + temperature: A float number up to nearest thousandth of one degree Celsius, + e.g. 30.125 + Returns: + A boolean, True if threshold is set successfully, False if not + """ + status, ret_txt = self._api_helper.ipmi_set_ss_thres(self.sensor_id, LOW_CRIT_TRESHOLD_SET_KEY, temperature) + return status + + def get_name(self): + """ + Retrieves the name of the thermal device + Returns: + string: The name of the thermal device + """ + return self.THERMAL_LIST[self.index][0] + + def get_presence(self): + """ + Retrieves the presence of the device + Returns: + bool: True if device is present, False if not + """ + return True if self.get_temperature() > 0 else False + + def get_model(self): + """ + Retrieves the model number (or part number) of the device + Returns: + string: Model/part number of device + """ + return self.sensor_des + + def get_serial(self): + """ + Retrieves the serial number of the device + Returns: + string: Serial number of device + """ + return "Unknown" + + def get_status(self): + """ + Retrieves the operational status of the device + Returns: + A boolean value, True if device is operating properly, False if not + """ + return self.get_presence() + + def get_position_in_parent(self): + """ + Retrieves 1-based relative physical position in parent device. + Returns: + integer: The 1-based relative physical position in parent + device or -1 if cannot determine the position + """ + return (self.index + 1) + + def is_replaceable(self): + """ + Indicate whether this Thermal is replaceable. + Returns: + bool: True if it is replaceable. + """ + return False + + def get_minimum_recorded(self): + """ + Retrieves the minimum recorded temperature of thermal + Returns: + A float number, the minimum recorded temperature of thermal in Celsius + up to nearest thousandth of one degree Celsius, e.g. 30.125 + """ + tmp = self.get_temperature() + if tmp < self.minimum_thermal: + self.minimum_thermal = tmp + return self.minimum_thermal + + def get_maximum_recorded(self): + """ + Retrieves the maximum recorded temperature of thermal + Returns: + A float number, the maximum recorded temperature of thermal in Celsius + up to nearest thousandth of one degree Celsius, e.g. 30.125 + """ + tmp = self.get_temperature() + if tmp > self.maximum_thermal: + self.maximum_thermal = tmp + return self.maximum_thermal diff --git a/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/sonic_platform/watchdog.py b/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/sonic_platform/watchdog.py new file mode 100644 index 000000000000..35c55945deeb --- /dev/null +++ b/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/sonic_platform/watchdog.py @@ -0,0 +1,317 @@ +#!/usr/bin/env python + +############################################################################# +# +# Module contains an implementation of SONiC Platform Base API and +# provides the Watchdog information +# +############################################################################# + +import os + +try: + from sonic_platform_base.watchdog_base import WatchdogBase +except ImportError as e: + raise ImportError(str(e) + "- required module not found") + +""" ioctl constants """ +IO_WRITE = 0x40000000 +IO_READ = 0x80000000 +IO_READ_WRITE = 0xC0000000 +IO_SIZE_INT = 0x00040000 +IO_SIZE_40 = 0x00280000 +IO_TYPE_WATCHDOG = ord('W') << 8 + +WDR_INT = IO_READ | IO_SIZE_INT | IO_TYPE_WATCHDOG +WDR_40 = IO_READ | IO_SIZE_40 | IO_TYPE_WATCHDOG +WDWR_INT = IO_READ_WRITE | IO_SIZE_INT | IO_TYPE_WATCHDOG + +""" Watchdog ioctl commands """ +WDIOC_GETSUPPORT = 0 | WDR_40 +WDIOC_GETSTATUS = 1 | WDR_INT +WDIOC_GETBOOTSTATUS = 2 | WDR_INT +WDIOC_GETTEMP = 3 | WDR_INT +WDIOC_SETOPTIONS = 4 | WDR_INT +WDIOC_KEEPALIVE = 5 | WDR_INT +WDIOC_SETTIMEOUT = 6 | WDWR_INT +WDIOC_GETTIMEOUT = 7 | WDR_INT +WDIOC_SETPRETIMEOUT = 8 | WDWR_INT +WDIOC_GETPRETIMEOUT = 9 | WDR_INT +WDIOC_GETTIMELEFT = 10 | WDR_INT + +""" Watchdog status constants """ +WDIOS_DISABLECARD = 0x0001 +WDIOS_ENABLECARD = 0x0002 + +WDT_COMMON_ERROR = -1 +#WD_MAIN_IDENTITY = "iTCO_wdt" +WD_MAIN_IDENTITY = "t7132s_wdt" +WDT_SYSFS_PATH = "/sys/class/watchdog/" +DEV_STATE_PATH = "/sys/devices/platform/switchboard/CPLD1/dev_state" +WDT_MAX_PATH = "/sys/devices/platform/switchboard/CPLD1/wdt_max" +WDT_COUNT_PATH = "/sys/devices/platform/switchboard/CPLD1/wdt_count" + + +class Watchdog(WatchdogBase): + + def __init__(self): + self.watchdog = None + self.wdt_main_dev_name = None + self.armed = self.is_armed() + self.timeout = self._gettimeout() + + def _is_wd_main(self, dev): + """ + Checks watchdog identity + """ + identity = self._read_file( + "{}/{}/identity".format(WDT_SYSFS_PATH, dev)) + return identity == WD_MAIN_IDENTITY + + def _get_wdt(self): + """ + Retrieves watchdog device + """ + if self.watchdog is not None: + return + + wdt_main_dev_list = [dev for dev in os.listdir( + "/dev/") if dev.startswith("watchdog") and self._is_wd_main(dev)] + if not wdt_main_dev_list: + self.wdt_main_dev_name = None + return + self.wdt_main_dev_name = wdt_main_dev_list[0] + + watchdog_device_path = "/dev/{}".format(self.wdt_main_dev_name) + try: + self.watchdog = os.open(watchdog_device_path, os.O_RDWR) + except (FileNotFoundError, IOError, OSError): + self.watchdog = None + self.wdt_main_dev_name = None + except SystemExit: + pass + + return + + def _put_wdt(self): + """ + Release watchdog device + """ + if self.watchdog is not None: + os.close(self.watchdog) + self.watchdog = None + self.wdt_main_dev_name = None + + def _read_file(self, file_path): + """ + Read text file + """ + try: + with open(file_path, "r") as fd: + txt = fd.read() + except IOError: + return WDT_COMMON_ERROR + return txt.strip() + + def _enable(self): + """ + Turn on the watchdog timer + """ + try: + with open(DEV_STATE_PATH, "r+") as reg_file: + content = reg_file.readline().strip() + reg_value = int(content, 16) + bit_enable = 0x100 + reg_value_new = reg_value | bit_enable + reg_file.write(hex(reg_value_new)) + except IOError as e: + print("Error: unable to open file: %s" % str(e)) + + def _disable(self): + """ + Turn off the watchdog timer + """ + try: + with open(DEV_STATE_PATH, "r+") as reg_file: + content = reg_file.readline().strip() + reg_value = int(content, 16) + bit_enable = 0x100 + reg_value_new = reg_value & ~bit_enable + reg_file.write(hex(reg_value_new)) + except IOError as e: + print("Error: unable to open file: %s" % str(e)) + + def _keepalive(self): + """ + Keep alive watchdog timer + """ + self._disable() + self._enable() + + def _settimeout(self, seconds): + """ + Set watchdog timer timeout + @param seconds - timeout in seconds + @return is the actual set timeout + """ + if seconds > 65535: + seconds = 65535 + + try: + with open(WDT_MAX_PATH, "r+") as reg_file: + reg_value = seconds + reg_file.write(hex(reg_value)) + except IOError as e: + print("Error: unable to open file: %s" % str(e)) + + return seconds + + def _gettimeout(self): + """ + Get watchdog timeout + @return watchdog timeout + """ + seconds = 0 + try: + with open(WDT_MAX_PATH, "r+") as reg_file: + content = reg_file.readline().strip() + reg_value = int(content, 16) + seconds = reg_value + except IOError as e: + print("Error: unable to open file: %s" % str(e)) + + return seconds + + def _gettimeleft(self): + """ + Get time left before watchdog timer expires + @return time left in seconds + """ + try: + with open(WDT_MAX_PATH, "r+") as reg_file: + content = reg_file.readline().strip() + reg_value = int(content, 16) + state_seconds = reg_value + except IOError as e: + print("Error: unable to open file: %s" % str(e)) + + try: + with open(WDT_COUNT_PATH, "r+") as reg_file: + content = reg_file.readline().strip() + reg_value = int(content, 16) + count_seconds = reg_value + except IOError as e: + print("Error: unable to open file: %s" % str(e)) + + timeleft = state_seconds - count_seconds + if timeleft < 0: + timeleft = 0 + print("Error: incorrect counter: state={} count={}". + format(state_seconds, count_seconds)) + elif timeleft > 65535: + timeleft = 65535 + print("Error: incorrect counter: state={} count={}". + format(state_seconds, count_seconds)) + + return timeleft + + ################################################################# + + def arm(self, seconds): + """ + Arm the hardware watchdog with a timeout of seconds. + If the watchdog is currently armed, calling this function will + simply reset the timer to the provided value. If the underlying + hardware does not support the value provided in , this + method should arm the watchdog with the *next greater* available + value. + Returns: + An integer specifying the *actual* number of seconds the watchdog + was armed with. On failure returns -1. + """ + ret = WDT_COMMON_ERROR + if seconds < 0: + return ret + if seconds > 65535: + return ret + + try: + self._disable() + if self._gettimeout() != seconds: + self.timeout = self._settimeout(seconds) + self._enable() + self.armed = True + ret = self.timeout + except IOError as e: + pass + + return ret + + def disarm(self): + """ + Disarm the hardware watchdog + Returns: + A boolean, True if watchdog is disarmed successfully, False if not + """ + disarmed = False + + if self.is_armed(): + try: + self._disable() + self.armed = False + disarmed = True + except IOError: + pass + + return disarmed + + def is_armed(self): + """ + Retrieves the armed state of the hardware watchdog. + Returns: + A boolean, True if watchdog is armed, False if not + """ + """ + We always get the HW status because all new instance have + it's own self.armed. And only the instance had called arm() + has self.armed = True if self.armed is a class variable. + """ + # Read status + try: + with open(DEV_STATE_PATH) as reg_file: + content = reg_file.readline().rstrip() + reg_value = int(content, 16) + except IOError as e: + print("Error: unable to open file: %s" % str(e)) + return False + + bit_enable = 0x100 + if reg_value & bit_enable: + return True + + return False + + def get_remaining_time(self): + """ + If the watchdog is armed, retrieve the number of seconds remaining on + the watchdog timer + Returns: + An integer specifying the number of seconds remaining on thei + watchdog timer. If the watchdog is not armed, returns -1. + """ + timeleft = WDT_COMMON_ERROR + + if self.is_armed(): + try: + timeleft = self._gettimeleft() + except IOError: + pass + + return timeleft + + def __del__(self): + """ + Close watchdog + """ + if self.watchdog is not None: + os.close(self.watchdog) diff --git a/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/systemd/platform-modules-sse-t7132s.service b/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/systemd/platform-modules-sse-t7132s.service new file mode 100644 index 000000000000..71d2b0d98c9f --- /dev/null +++ b/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/systemd/platform-modules-sse-t7132s.service @@ -0,0 +1,14 @@ +[Unit] +Description=SuperMicro SSE-T7132S Platform modules +Before=pmon.service +DefaultDependencies=no + +[Service] +Type=oneshot +ExecStart=/usr/local/bin/platform.sh init +ExecStop=/usr/local/bin/platform.sh deinit +RemainAfterExit=yes + +[Install] +WantedBy=multi-user.target + diff --git a/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/systemd/sysled.service b/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/systemd/sysled.service new file mode 100644 index 000000000000..cde02505d47e --- /dev/null +++ b/platform/innovium/sonic-platform-modules-supermicro/sse-t7132s/systemd/sysled.service @@ -0,0 +1,15 @@ +[Unit] +Description=Set system LED before reboot/poweroff/halt +DefaultDependencies=no +#Conflicts=reboot.target +Before=poweroff.target halt.target reboot.target kexec.target shutdown.target +#Requires=poweroff.target + +[Service] +Type=oneshot +ExecStart=/usr/local/bin/sysledctl.py start +#ExecStop=/usr/local/bin/sysledctl.py stop +RemainAfterExit=yes + +[Install] +WantedBy=poweroff.target halt.target shutdown.target reboot.target kexec.target diff --git a/platform/marvell-arm64/platform.conf b/platform/marvell-arm64/platform.conf index 4de0dadd28e9..2fa347b68b0d 100644 --- a/platform/marvell-arm64/platform.conf +++ b/platform/marvell-arm64/platform.conf @@ -37,11 +37,11 @@ if [ $PLATFORM_AC5X -eq 1 ]; then fit_addr=0x210000000 initrd_addr=0x206000000 - fdt_fname="/boot/ac5x.dtb" + fdt_fname="/usr/lib/linux-image-${kernel_version}/marvell/7215-ixs-a1.dtb" FW_ENV_DEFAULT='/dev/mtd0 0x400000 0x10000 0x10000' demo_part=2 - fit_conf_name="#conf_ac5x" + fit_conf_name="#conf_7215_a1" mmc_bus="mmc0:0001" else fdt_addr=0x1000000 @@ -205,6 +205,7 @@ prepare_boot_menu() { fw_setenv ${FW_ARG} kernel_addr $kernel_addr > /dev/null fw_setenv ${FW_ARG} fdt_addr $fdt_addr > /dev/null fw_setenv ${FW_ARG} fit_addr $fit_addr > /dev/null + fw_setenv ${FW_ARG} fit_conf_name $fit_conf_name > /dev/null fw_setenv ${FW_ARG} initrd_addr $initrd_addr > /dev/null MMC_LOAD='ext4load mmc 0:'$demo_part' $fit_addr $fit_name' fw_setenv ${FW_ARG} sonic_boot_load "$MMC_LOAD" > /dev/null diff --git a/platform/marvell-arm64/sonic-platform-nokia/7215/modules/Makefile b/platform/marvell-arm64/sonic-platform-nokia/7215/modules/Makefile index 47e1492f1572..73d6e5f38876 100644 --- a/platform/marvell-arm64/sonic-platform-nokia/7215/modules/Makefile +++ b/platform/marvell-arm64/sonic-platform-nokia/7215/modules/Makefile @@ -1 +1 @@ -obj-m:= nokia_7215_ixs_a1_cpld.o +obj-m:= nokia_7215_ixs_a1_cpld.o ac5_thermal_sensor.o diff --git a/platform/marvell-arm64/sonic-platform-nokia/7215/modules/ac5_thermal_sensor.c b/platform/marvell-arm64/sonic-platform-nokia/7215/modules/ac5_thermal_sensor.c new file mode 100644 index 000000000000..faf4402ffe61 --- /dev/null +++ b/platform/marvell-arm64/sonic-platform-nokia/7215/modules/ac5_thermal_sensor.c @@ -0,0 +1,218 @@ +/* + * HWMON Driver for AC5x thermal sensor + * + * Author: Natarajan Subbiramani + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define AC5_DEFAULT_TEMP_CRIT 100000 +#define AC5_DEFAULT_TEMP_MAX 110000 + +#define AC5_TEMP_BASE_ADDR 0x944F80D0 +static unsigned long thermal_base_addr=AC5_TEMP_BASE_ADDR; +module_param(thermal_base_addr, ulong, 0444); +MODULE_PARM_DESC(thermal_base_addr, + "Initialize the base address of the thermal sensor"); + +struct ac5_thermal_data { + struct device *dev; + struct device *hwmon_dev; + uint8_t * __iomem temp_base; + int temp_input; + int temp_crit; + int temp_max; +}; + +static long ac5_thermal_read_reg_in_mcelcius(struct device *dev, struct ac5_thermal_data *data) +{ + volatile uint8_t * __iomem temp_base = data->temp_base; + uint32_t regval; + long output=data->temp_max; + + //STOP MEASUREMENT + writel(0xF0F01034, temp_base); + + //delay for 1ms + mdelay(1); + + //Read thermal value + regval = readl(temp_base+0xC); + + //RE-START MEASUREMENT + writel(0xF0F01035, temp_base); + + //Validate data + if(regval & 0x10000) { + //Calibrate it to milli-celcius + output = (regval>> 6) & 0x3FF; + output = ((output*42)-27250)*10; + } + + return output; +} +static int ac5_thermal_read(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long *val) +{ + struct ac5_thermal_data *data = dev_get_drvdata(dev); + + switch (type) { + case hwmon_temp: + switch (attr) { + case hwmon_temp_input: + *val = ac5_thermal_read_reg_in_mcelcius(dev, data); + break; + case hwmon_temp_crit: + *val = data->temp_crit; + break; + case hwmon_temp_max: + *val = data->temp_max; + break; + default: + return -EINVAL; + } + break; + default: + return -EINVAL; + } + return 0; +} + +static int ac5_thermal_write(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long val) +{ + struct ac5_thermal_data *data = dev_get_drvdata(dev); + switch (type) { + case hwmon_temp: + switch (attr) { + case hwmon_temp_crit: + data->temp_crit = val; + break; + case hwmon_temp_max: + data->temp_max = val; + break; + default: + return -EINVAL; + } + break; + default: + return -EINVAL; + } + return 0; +} + + +static umode_t ac5_thermal_is_visible(const void *data, enum hwmon_sensor_types type, + u32 attr, int channel) +{ + switch (type) { + case hwmon_temp: + switch (attr) { + case hwmon_temp_input: + return 0444; + case hwmon_temp_crit: + case hwmon_temp_max: + return 0644; + } + break; + default: + break; + } + return 0; +} + +static const struct hwmon_channel_info *ac5_thermal_info[] = { + HWMON_CHANNEL_INFO(temp, + HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT), + NULL +}; + +static const struct hwmon_ops ac5_thermal_hwmon_ops = { + .is_visible = ac5_thermal_is_visible, + .read = ac5_thermal_read, + .write = ac5_thermal_write, +}; + +static const struct hwmon_chip_info ac5_thermal_chip_info = { + .ops = &ac5_thermal_hwmon_ops, + .info = ac5_thermal_info, +}; + +static const struct file_operations fops = { + .owner = THIS_MODULE, +}; + +struct miscdevice ac5_thermal_misc_device = { + .minor = TEMP_MINOR, + .name = "ac5_thermal", + .fops = &fops, +}; + +static int __init ac5_thermal_init_misc_driver(void) +{ + struct device *dev; + struct ac5_thermal_data *thermal_data; + int err; + void * __iomem reg; + + err = misc_register(&ac5_thermal_misc_device); + if (err) { + pr_err("ac5_thermal misc_register failed!!!\n"); + return err; + } + + dev = ac5_thermal_misc_device.this_device; + thermal_data = devm_kzalloc(dev, sizeof(struct ac5_thermal_data), GFP_KERNEL); + if (!thermal_data) + return -ENOMEM; + + thermal_data->dev = dev; + thermal_data->temp_crit = AC5_DEFAULT_TEMP_CRIT; + thermal_data->temp_max = AC5_DEFAULT_TEMP_MAX; + + thermal_data->hwmon_dev = devm_hwmon_device_register_with_info(dev, ac5_thermal_misc_device.name, + thermal_data, &ac5_thermal_chip_info, + NULL); + if (IS_ERR(thermal_data->hwmon_dev)) { + dev_err(dev, "%s: hwmon registration failed.\n", ac5_thermal_misc_device.name); + return PTR_ERR(thermal_data->hwmon_dev); + } + + reg = devm_ioremap(dev, thermal_base_addr, 16); + if (IS_ERR(reg)) { + dev_err(dev, "%s: base addr remap failed\n", ac5_thermal_misc_device.name); + return PTR_ERR(reg); + } + thermal_data->temp_base = reg; + /*Enable measurement*/ + writel(0xF0F01035, thermal_data->temp_base); + writel(0x0584e680, thermal_data->temp_base+8); + + dev_info(dev, "%s: initialized. base_addr: 0x%lx\n", dev_name(thermal_data->hwmon_dev), thermal_base_addr); + + return 0; +} + +static void __exit ac5_thermal_exit_misc_driver(void) +{ + misc_deregister(&ac5_thermal_misc_device); +} + +module_init(ac5_thermal_init_misc_driver); +module_exit(ac5_thermal_exit_misc_driver); + +MODULE_AUTHOR("Natarajan Subbiramani "); +MODULE_DESCRIPTION("AC5 Thermal sensor Driver"); +MODULE_LICENSE("GPL"); diff --git a/platform/marvell-arm64/sonic-platform-nokia/7215/scripts/nokia-7215-init.sh b/platform/marvell-arm64/sonic-platform-nokia/7215/scripts/nokia-7215-init.sh index 9659bee7c715..b105c0f711c4 100644 --- a/platform/marvell-arm64/sonic-platform-nokia/7215/scripts/nokia-7215-init.sh +++ b/platform/marvell-arm64/sonic-platform-nokia/7215/scripts/nokia-7215-init.sh @@ -4,9 +4,9 @@ # Load required kernel-mode drivers load_kernel_drivers() { -#placeholder for now - echo "Loading Kernel Drivers" + echo "Loading Kernel Drivers" sudo insmod /lib/modules/5.10.0-18-2-arm64/nokia_7215_ixs_a1_cpld.ko + sudo insmod /lib/modules/5.10.0-18-2-arm64/ac5_thermal_sensor.ko } nokia_7215_profile() @@ -16,23 +16,28 @@ nokia_7215_profile() sudo ifconfig eth0 hw ether $MAC_ADDR echo "Nokia-7215-A1: Updating switch mac address ${MAC_ADDR}" } +file_exists() { + # Wait 10 seconds max till file exists + for((i=0; i<10; i++)); + do + if [ -f $1 ]; then + return 1 + fi + sleep 1 + done + return 0 + } # - Main entry # Install kernel drivers required for i2c bus access load_kernel_drivers +# Enumerate RTC +echo m41t11 0x68 > /sys/bus/i2c/devices/i2c-0/new_device -# LOGIC to enumerate SFP eeprom devices - send 0x50 to kernel i2c driver - initialize devices -# the mux may be enumerated at number 4 or 5 so we check for the mux and skip if needed -# Get list of the mux channels # Enumerate the SFP eeprom device on each mux channel -#echo optoe2 0x50 > /sys/bus/i2c/devices/i2c-0/new_device - -# Enumerate system eeprom -echo 24c64 0x53 > /sys/class/i2c-adapter/i2c-0/new_device -sleep 2 -chmod 644 /sys/class/i2c-adapter/i2c-0/0-0053/eeprom +echo pca9546 0x70> /sys/bus/i2c/devices/i2c-1/new_device # Enumerate power monitor echo ina230 0x40 > /sys/bus/i2c/devices/i2c-0/new_device @@ -40,17 +45,52 @@ echo ina230 0x40 > /sys/bus/i2c/devices/i2c-0/new_device # Enumerate fan echo emc2305 0x2e > /sys/bus/i2c/devices/i2c-0/new_device -# Enumerate RTC -echo m41t11 0x68 > /sys/bus/i2c/devices/i2c-0/new_device - # Enumerate Thermals - echo tmp75 0x48 > /sys/bus/i2c/devices/i2c-0/new_device echo tmp75 0x49 > /sys/bus/i2c/devices/i2c-0/new_device +#Enumerate CPLD echo nokia_7215_a1_cpld 0x41 > /sys/bus/i2c/devices/i2c-0/new_device +# Enumerate system eeprom +echo 24c64 0x53 > /sys/class/i2c-adapter/i2c-0/new_device + +file_exists /sys/class/i2c-adapter/i2c-0/0-0053/eeprom +status=$? +if [ "$status" == "1" ]; then + chmod 644 /sys/class/i2c-adapter/i2c-0/0-0053/eeprom +else + echo "SYSEEPROM file not foud" +fi + +# Get list of the mux channels +for((i=0; i<10; i++)); + do + ismux_bus=$(i2cdetect -l|grep mux|cut -f1) + if [[ $ismux_bus ]]; then + break; + fi + sleep 1 + done + +# Enumerate the SFP eeprom device on each mux channel +for mux in ${ismux_bus} +do + echo optoe2 0x50 > /sys/class/i2c-adapter/${mux}/new_device +done + +# Enable optical SFP Tx +for i in {49..52} +do + echo 0 > /sys/bus/i2c/devices/0-0041/sfp${i}_tx_disable +done + +#slow down fan speed to 50 untill thermal algorithm kicks in% +i2c_path="/sys/bus/i2c/devices/0-002e/hwmon/hwmon?" +echo 128 > $i2c_path/pwm1 +echo 128 > $i2c_path/pwm2 + # Ensure switch is programmed with base MAC addr nokia_7215_profile -exit 0 \ No newline at end of file +exit 0 diff --git a/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/chassis.py b/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/chassis.py index c5f3c1db18b4..11eeb15106af 100644 --- a/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/chassis.py +++ b/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/chassis.py @@ -35,7 +35,7 @@ MAX_7215_FAN_DRAWERS = 2 MAX_7215_FANS_PER_DRAWER = 1 MAX_7215_PSU = 2 -MAX_7215_THERMAL = 3 +MAX_7215_THERMAL = 4 CPLD_DIR = "/sys/bus/i2c/devices/0-0041/" SYSLOG_IDENTIFIER = "chassis" @@ -64,11 +64,10 @@ def __init__(self): sfp_node = Sfp(index, 'COPPER', 'N/A', 'N/A') self._sfp_list.append(sfp_node) - """ # Verify optoe2 driver SFP eeprom devices were enumerated and exist # then create the sfp nodes eeprom_path = "/sys/class/i2c-adapter/i2c-{0}/{0}-0050/eeprom" - mux_dev = sorted(glob.glob("/sys/class/i2c-adapter/i2c-0/i2c-[0-9]")) + mux_dev = sorted(glob.glob("/sys/class/i2c-adapter/i2c-1/i2c-[0-9]")) y = 0 for index in range(self.SFP_PORT_START, self.SFP_PORT_END+1): mux_dev_num = mux_dev[y] @@ -80,7 +79,6 @@ def __init__(self): sfp_node = Sfp(index, 'SFP', port_eeprom_path, port_i2c_map) self._sfp_list.append(sfp_node) self.sfp_event_initialized = False - """ # Instantiate system eeprom object self._eeprom = Eeprom() @@ -196,11 +194,11 @@ def get_model(self): def get_serial(self): """ - Retrieves the serial number of the chassis (Service tag) + Retrieves the serial number of the chassis Returns: string: Serial number of chassis """ - return self._eeprom.serial_str() + return self._eeprom.serial_number_str() def get_status(self): """ @@ -221,15 +219,13 @@ def get_base_mac(self): """ return self._eeprom.base_mac_addr() - def get_serial_number(self): + def get_service_tag(self): """ - Retrieves the hardware serial number for the chassis - + Retrieves the Service Tag of the chassis Returns: - A string containing the hardware serial number for this - chassis. + string: Service Tag of chassis """ - return self._eeprom.serial_number_str() + return self._eeprom.service_tag_str() def get_revision(self): """ @@ -275,6 +271,13 @@ def get_watchdog(self): Returns: An object derived from WatchdogBase representing the hardware watchdog device + + Note: + We overload this method to ensure that watchdog is only initialized + when it is referenced. Currently, only one daemon can open the + watchdog. To initialize watchdog in the constructor causes multiple + daemon try opening watchdog when loading and constructing a chassis + object and fail. By doing so we can eliminate that risk. """ try: if self._watchdog is None: @@ -405,31 +408,6 @@ def get_status_led(self): return color - def get_watchdog(self): - """ - Retrieves hardware watchdog device on this chassis - - Returns: - An object derived from WatchdogBase representing the hardware - watchdog device - - Note: - We overload this method to ensure that watchdog is only initialized - when it is referenced. Currently, only one daemon can open the - watchdog. To initialize watchdog in the constructor causes multiple - daemon try opening watchdog when loading and constructing a chassis - object and fail. By doing so we can eliminate that risk. - """ - try: - if self._watchdog is None: - from sonic_platform.watchdog import WatchdogImplBase - watchdog_device_path = "/dev/watchdog0" - self._watchdog = WatchdogImplBase(watchdog_device_path) - except Exception as e: - sonic_logger.log_warning(" Fail to load watchdog {}".format(repr(e))) - - return self._watchdog - def get_position_in_parent(self): """ Retrieves 1-based relative physical position in parent device. If the agent diff --git a/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/component.py b/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/component.py index f510bde8043f..cda5abc3c223 100644 --- a/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/component.py +++ b/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/component.py @@ -34,10 +34,7 @@ class Component(ComponentBase): ["System-CPLD", "Used for managing SFPs, LEDs, PSUs and FANs "], ["U-Boot", "Performs initialization during booting"], ] - CPLD_UPDATE_COMMAND1 = ['cp', '/usr/sbin/vme', '/tmp'] - CPLD_UPDATE_COMMAND2 = ['cp', '', '/tmp'] - CPLD_UPDATE_COMMAND3 = ['cd', '/tmp'] - CPLD_UPDATE_COMMAND4 = ['./vme', ''] + CPLD_UPDATE_COMMAND = ['./cpldupd_A1', ''] def __init__(self, component_index): self.index = component_index @@ -192,23 +189,25 @@ def install_firmware(self, image_path): A boolean, True if install was successful, False if not """ image_name = ntpath.basename(image_path) - print(" ixs7215 - install cpld {}".format(image_name)) + print(" ixs-7215-A1 - install cpld {}".format(image_name)) # check whether the image file exists if not os.path.isfile(image_path): print("ERROR: the cpld image {} doesn't exist ".format(image_path)) return False - self.CPLD_UPDATE_COMMAND2[1] = image_path - self.CPLD_UPDATE_COMMAND4[1] = image_name + # check whether the cpld exe exists + if not os.path.isfile('/tmp/cpldupd_A1'): + print("ERROR: the cpld exe {} doesn't exist ".format('/tmp/cpldupd_A1')) + return False + + self.CPLD_UPDATE_COMMAND[1] = image_name success_flag = False try: - subprocess.check_call(self.CPLD_UPDATE_COMMAND1, stderr=subprocess.STDOUT) - subprocess.check_call(self.CPLD_UPDATE_COMMAND2, stderr=subprocess.STDOUT) - subprocess.check_call(self.CPLD_UPDATE_COMMAND3, stderr=subprocess.STDOUT) - subprocess.check_call(self.CPLD_UPDATE_COMMAND4, stderr=subprocess.STDOUT) + subprocess.check_call(self.CPLD_UPDATE_COMMAND, stderr=subprocess.STDOUT) + success_flag = True except subprocess.CalledProcessError as e: print("ERROR: Failed to upgrade CPLD: rc={}".format(e.returncode)) diff --git a/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/eeprom.py b/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/eeprom.py index ada5e979ee41..4abfad47be9f 100644 --- a/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/eeprom.py +++ b/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/eeprom.py @@ -27,23 +27,28 @@ def __init__(self, is_psu=False, psu_index=0, is_fan=False, fan_index=0): self.is_psu_eeprom = is_psu self.is_fan_eeprom = is_fan self.is_sys_eeprom = not (is_psu | is_fan) + + if self.is_sys_eeprom: + self.start_offset = 0 + self.eeprom_path = self.I2C_DIR + "i2c-0/0-0053/eeprom" + # System EEPROM is in ONIE TlvInfo EEPROM format + super(Eeprom, self).__init__(self.eeprom_path, + self.start_offset, '', True) + self._load_system_eeprom() + + else: + if self.is_psu_eeprom: + self.index = psu_index + self.part_number = '1' + self.model_str = 'PJT-12V100WBBA' + self.serial_number = 'NA' + self.serial_number = 'NA' - self.start_offset = 0 - self.eeprom_path = self.I2C_DIR + "i2c-0/0-0053/eeprom" - # System EEPROM is in ONIE TlvInfo EEPROM format - super(Eeprom, self).__init__(self.eeprom_path, - self.start_offset, '', True) - self._load_system_eeprom() - - if self.is_psu_eeprom: - self.index = psu_index - self.part_number = '1' - self.model_str = 'PJT-12V100WBBA' - - if self.is_fan_eeprom: - self.index = fan_index - self.part_number = '1' - self.model_str = 'FFB0412UHN-BC2EA12' + if self.is_fan_eeprom: + self.index = fan_index + self.part_number = '1' + self.model_str = 'FFB0412UHN-BC2EA12' + self.serial_number = 'NA' def _load_system_eeprom(self): @@ -61,7 +66,7 @@ def _load_system_eeprom(self): self.serial_number = 'NA' self.part_number = 'NA' self.model_str = 'NA' - self.serial = 'NA' + self.service_tag = 'NA' self.eeprom_tlv_dict = dict() else: eeprom = self.eeprom_data @@ -73,7 +78,7 @@ def _load_system_eeprom(self): self.serial_number = 'NA' self.part_number = 'NA' self.model_str = 'NA' - self.serial = 'NA' + self.service_tag = 'NA' return total_length = (eeprom[9] << 8) | eeprom[10] @@ -88,12 +93,7 @@ def _load_system_eeprom(self): + eeprom[tlv_index + 1]] code = "0x%02X" % (tlv[0]) - if tlv[0] == self._TLV_CODE_VENDOR_EXT: - value = str((tlv[2] << 24) | (tlv[3] << 16) | - (tlv[4]<< 8) | tlv[5]) - value += str(tlv[6:6 + tlv[1]]) - else: - name, value = self.decoder(None, tlv) + name, value = self.decoder(None, tlv) self.eeprom_tlv_dict[code] = value if eeprom[tlv_index] == self._TLV_CODE_CRC_32: @@ -109,7 +109,7 @@ def _load_system_eeprom(self): "0x%X" % (self._TLV_CODE_PART_NUMBER), 'NA') self.model_str = self.eeprom_tlv_dict.get( "0x%X" % (self._TLV_CODE_PRODUCT_NAME), 'NA') - self.serial = self.eeprom_tlv_dict.get( + self.service_tag = self.eeprom_tlv_dict.get( "0x%X" % (self._TLV_CODE_SERVICE_TAG), 'NA') def _get_eeprom_field(self, field_name): @@ -160,11 +160,11 @@ def modelstr(self): """ return self.model_str - def serial_str(self): + def service_tag_str(self): """ Returns the servicetag number. """ - return self.serial + return self.service_tag def system_eeprom_info(self): """ diff --git a/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/fan.py b/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/fan.py index f03122686f03..aa4a51a95d31 100644 --- a/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/fan.py +++ b/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/fan.py @@ -16,8 +16,9 @@ except ImportError as e: raise ImportError(str(e) + "- required module not found") -MAX_IXS7215_FAN_SPEED = 23000 -WORKING_IXS7215_FAN_SPEED = 2300 +MAX_IXS7215_FAN_SPEED = 24000 +WORKING_IXS7215_FAN_SPEED = 2400 + sonic_logger = logger.Logger('fan') @@ -27,9 +28,11 @@ class Fan(FanBase): def __init__(self, fan_index, fan_drawer, psu_fan=False, dependency=None): self.is_psu_fan = psu_fan + EMC2302_DIR = " " i2c_path = "/sys/bus/i2c/devices/0-002e/hwmon/" - hwmon_node = os.listdir(i2c_path)[0] - EMC2302_DIR = i2c_path + hwmon_node + '/' + if(os.path.exists(i2c_path)): + hwmon_node = os.listdir(i2c_path)[0] + EMC2302_DIR = i2c_path + hwmon_node + '/' if not self.is_psu_fan: # Fan is 1-based in Nokia platforms @@ -140,7 +143,7 @@ def get_service_tag(self): Returns: string: Service Tag of Fan """ - return self.eeprom.serial_str() + return self.eeprom.service_tag_str() def get_status(self): """ @@ -217,7 +220,7 @@ def get_speed_tolerance(self): """ if self.get_presence(): # The tolerance value is fixed as 25% for this platform - tolerance = 25 + tolerance = 50 else: tolerance = 0 @@ -235,17 +238,16 @@ def set_speed(self, speed): if self.is_psu_fan: return False - # Set current fan duty cycle - # - 0x00 : fan off - # - 0x40 : 25% duty cycle - # - 0x80 : 50% duty cycle (default) - # - 0xff : 100% duty cycle (full speed) if speed in range(0, 6): fandutycycle = 0x00 - elif speed in range(6, 41): + elif speed in range(6, 26): fandutycycle = 64 - elif speed in range(41, 76): + elif speed in range(26, 41): + fandutycycle = 102 + elif speed in range(41, 52): fandutycycle = 128 + elif speed in range(52, 76): + fandutycycle = 192 elif speed in range(76, 101): fandutycycle = 255 else: @@ -300,9 +302,13 @@ def get_target_speed(self): speed = 0 elif dutyspeed == 64: speed = 25 + elif dutyspeed == 102: + speed = 40 elif dutyspeed == 128: speed = 50 + elif dutyspeed == 192: + speed = 75 elif dutyspeed == 255: speed = 100 - return speed \ No newline at end of file + return speed diff --git a/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/psu.py b/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/psu.py index bd45ed054636..eb8aeeaedfb1 100644 --- a/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/psu.py +++ b/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/psu.py @@ -167,11 +167,11 @@ def get_voltage(self): e.g. 12.1 """ if(self.get_status()): - psu_voltage = self._read_sysfs_file(INA230_DIR+"in_voltage1_scale") + psu_voltage = self._read_sysfs_file(INA230_DIR+"in_voltage1_raw") else: psu_voltage = 0.0 - psu_voltage = float(psu_voltage)*10 + psu_voltage = (float(psu_voltage)*1.25)/1000 return psu_voltage @@ -184,8 +184,8 @@ def get_current(self): """ num_psus = self._get_active_psus() if(self.get_status()): - psu_current = self._read_sysfs_file(INA230_DIR+"in_current3_scale") - psu_current = (float(psu_current)*10)/num_psus + psu_current = self._read_sysfs_file(INA230_DIR+"in_current3_raw") + psu_current = ((float(psu_current)*0.5)/1000)/num_psus else: psu_current = 0.0 diff --git a/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/sfp.py b/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/sfp.py index c7b659c00feb..4cb96ed47046 100644 --- a/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/sfp.py +++ b/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/sfp.py @@ -1,13 +1,14 @@ # Name: sfp.py, version: 1.0 # # Description: Module contains the definitions of SFP related APIs -# for Nokia IXR 7250 platform. +# for Nokia IXS 7215 platform. # # Copyright (c) 2023, Nokia # All rights reserved. # try: + import os from sonic_platform_base.sonic_xcvr.sfp_optoe_base import SfpOptoeBase from sonic_py_common.logger import Logger from sonic_py_common import device_info @@ -18,20 +19,13 @@ import subprocess as cmd -smbus_present = 1 - -try: - import smbus -except ImportError as e: - smbus_present = 0 - COPPER_TYPE = "COPPER" SFP_TYPE = "SFP" # SFP PORT numbers SFP_PORT_START = 49 SFP_PORT_END = 52 - +CPLD_DIR = "/sys/bus/i2c/devices/0-0041/" logger = Logger() class Sfp(SfpOptoeBase): @@ -71,7 +65,24 @@ def __init__(self, index, sfp_type, eeprom_path, port_i2c_map): logger.log_debug("Sfp __init__ index {} setting name to {} and eeprom_path to {}".format(index, self.name, self.eeprom_path)) Sfp.instances.append(self) - + + def _read_sysfs_file(self, sysfs_file): + # On successful read, returns the value read from given + # reg_name and on failure returns 'ERR' + rv = 'ERR' + + if (not os.path.isfile(sysfs_file)): + return rv + try: + with open(sysfs_file, 'r') as fd: + rv = fd.read() + except Exception as e: + rv = 'ERR' + + rv = rv.rstrip('\r\n') + rv = rv.lstrip(" ") + return rv + def get_eeprom_path(self): return self.eeprom_path @@ -83,22 +94,8 @@ def get_presence(self): """ if self.sfp_type == COPPER_TYPE: return False - - if smbus_present == 0: # if called from sfputil outside of pmon - # cmdstatus, sfpstatus = cmd.getstatusoutput('sudo i2cget -y 0 0x41 0x3') - cmdstatus, sfpstatus = getstatusoutput_noshell(['sudo', 'i2cget', '-y', '0', '0x41', '0x3']) - sfpstatus = int(sfpstatus, 16) - else: - bus = smbus.SMBus(0) - DEVICE_ADDRESS = 0x41 - DEVICE_REG = 0x3 - sfpstatus = bus.read_byte_data(DEVICE_ADDRESS, DEVICE_REG) - - pos = [1, 2, 4, 8] - bit_pos = pos[self.index-SFP_PORT_START] - sfpstatus = sfpstatus & (bit_pos) - - if sfpstatus == 0: + sfpstatus = self._read_sysfs_file(CPLD_DIR+"sfp{}_present".format(self.index)) + if sfpstatus == '1': return True return False @@ -157,7 +154,6 @@ def get_error_description(self): error_description = self.SFP_STATUS_OK return error_description - # return NotImplementedError def get_reset_status(self): """ diff --git a/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/sfp_event.py b/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/sfp_event.py index 34fc2bc6ae5d..92f759b97895 100644 --- a/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/sfp_event.py +++ b/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/sfp_event.py @@ -1,17 +1,11 @@ ''' listen for the SFP change event and return to chassis. ''' +import os import time from sonic_py_common import logger from sonic_py_common.general import getstatusoutput_noshell -smbus_present = 1 - -try: - import smbus -except ImportError as e: - smbus_present = 0 - # system level event/error EVENT_ON_ALL_SFP = '-1' SYSTEM_NOT_READY = 'system_not_ready' @@ -21,6 +15,7 @@ # SFP PORT numbers SFP_PORT_START = 49 SFP_PORT_END = 52 +CPLD_DIR = "/sys/bus/i2c/devices/0-0041/" SYSLOG_IDENTIFIER = "sfp_event" sonic_logger = logger.Logger(SYSLOG_IDENTIFIER) @@ -32,6 +27,23 @@ class sfp_event: def __init__(self): self.handle = None + def _read_sysfs_file(self, sysfs_file): + # On successful read, returns the value read from given + # reg_name and on failure returns 'ERR' + rv = 'ERR' + + if (not os.path.isfile(sysfs_file)): + return rv + try: + with open(sysfs_file, 'r') as fd: + rv = fd.read() + except Exception as e: + rv = 'ERR' + + rv = rv.rstrip('\r\n') + rv = rv.lstrip(" ") + return rv + def initialize(self): self.modprs_register = 0 # Get Transceiver status @@ -44,18 +56,13 @@ def deinitialize(self): return def _get_transceiver_status(self): - if smbus_present == 0: - sonic_logger.log_info(" PMON - smbus ERROR - DEBUG sfp_event ") - cmdstatus, sfpstatus = getstatusoutput_noshell(['sudo', 'i2cget', '-y', '0', '0x41', '0x3']) - sfpstatus = int(sfpstatus, 16) - else: - bus = smbus.SMBus(0) - DEVICE_ADDRESS = 0x41 - DEVICE_REG = 0x3 - sfpstatus = bus.read_byte_data(DEVICE_ADDRESS, DEVICE_REG) - sfpstatus = ~sfpstatus - sfpstatus = sfpstatus & 0xF + pos = [1, 2, 4, 8] + sfpstatus = 0 + for port in range (SFP_PORT_START,SFP_PORT_END+1): + status = self._read_sysfs_file(CPLD_DIR+"sfp{}_present".format(port)) + bit_pos = pos[port-SFP_PORT_START] + sfpstatus = sfpstatus + (bit_pos * (int(status))) return sfpstatus diff --git a/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/test/test-eeprom.py b/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/test/test-eeprom.py index f63dd0241201..bee72e022e88 100755 --- a/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/test/test-eeprom.py +++ b/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/test/test-eeprom.py @@ -13,7 +13,7 @@ def main(): eeprom = chassis.get_eeprom() print(" Model: {}, Service Tag: {}".format(eeprom.modelstr(), - eeprom.serial_str())) + eeprom. service_tag_str())) print(" Part#: {}, Serial#: {}".format(eeprom.part_number_str(), eeprom.serial_number_str())) print(" Base MAC: {}".format(eeprom.base_mac_addr())) diff --git a/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/thermal.py b/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/thermal.py index 4af8fce144f5..5a8a084cfc7c 100644 --- a/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/thermal.py +++ b/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/thermal.py @@ -24,8 +24,9 @@ class Thermal(ThermalBase): ['i2c-0/0-0049/hwmon/', 1]) HWMON_CLASS_DIR = "/sys/class/hwmon/hwmon0/" + AC5X_THERMAL_DIR = "/sys/class/hwmon/hwmon1/" - THERMAL_NAME = ("PCB BACK", "PCB FRONT", "CPU Core") + THERMAL_NAME = ("PCB BACK", "PCB FRONT", "AC5X CORE", "OOB PHY") def __init__(self, thermal_index): ThermalBase.__init__(self) @@ -39,12 +40,19 @@ def __init__(self, thermal_index): if self.index < 3: i2c_path = self.I2C_CLASS_DIR + self.I2C_DEV_MAPPING[self.index - 1][0] sensor_index = self.I2C_DEV_MAPPING[self.index - 1][1] - sensor_high_suffix = None - sensor_high_crit_suffix = "max" + sensor_high_suffix = "max" + sensor_high_crit_suffix = None hwmon_node = os.listdir(i2c_path)[0] self.SENSOR_DIR = i2c_path + hwmon_node + '/' # SOC temperature sensor + elif self.index == 3: + dev_path = self.AC5X_THERMAL_DIR + sensor_index = 1 + sensor_high_suffix = "max" + sensor_high_crit_suffix = None + self.SENSOR_DIR = dev_path + # else: dev_path = self.HWMON_CLASS_DIR sensor_index = 1 diff --git a/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/thermal_actions.py b/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/thermal_actions.py index a829fd80a5ba..4dc9b6ab5b48 100644 --- a/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/thermal_actions.py +++ b/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/thermal_actions.py @@ -13,13 +13,17 @@ class SetFanSpeedAction(ThermalPolicyActionBase): # JSON field definition JSON_FIELD_SPEED = 'speed' JSON_FIELD_DEFAULT_SPEED = 'default_speed' + JSON_FIELD_THRESHOLD1_SPEED = 'threshold1_speed' + JSON_FIELD_THRESHOLD2_SPEED = 'threshold2_speed' JSON_FIELD_HIGHTEMP_SPEED = 'hightemp_speed' def __init__(self): """ Constructor of SetFanSpeedAction """ - self.default_speed = 50 + self.default_speed = 25 + self.threshold1_speed=40 + self.threshold2_speed=75 self.hightemp_speed = 100 self.speed = self.default_speed @@ -77,7 +81,9 @@ def load_from_json(self, json_obj): Construct ThermalRecoverAction via JSON. JSON example: { "type": "thermal.temp_check_and_set_all_fan_speed" - "default_speed": "50" + "default_speed": "25", + "threshold1_speed": "40", + "threshold2_speed": "75", "hightemp_speed": "100" } :param json_obj: A JSON object representing a ThermalRecoverAction action. @@ -93,6 +99,26 @@ def load_from_json(self, json_obj): raise ValueError('SetFanSpeedAction missing mandatory field {} in JSON policy file'. format(SetFanSpeedAction.JSON_FIELD_DEFAULT_SPEED)) + if SetFanSpeedAction.JSON_FIELD_THRESHOLD1_SPEED in json_obj: + threshold1_speed = float(json_obj[SetFanSpeedAction.JSON_FIELD_THRESHOLD1_SPEED]) + if threshold1_speed < 0 or threshold1_speed > 100: + raise ValueError('SetFanSpeedAction invalid default speed value {} in JSON policy file, valid value should be [0, 100]'. + format(threshold1_speed)) + self.threshold1_speed = float(json_obj[SetFanSpeedAction.JSON_FIELD_THRESHOLD1_SPEED]) + else: + raise ValueError('SetFanSpeedAction missing mandatory field {} in JSON policy file'. + format(SetFanSpeedAction.JSON_FIELD_THRESHOLD1_SPEED)) + + if SetFanSpeedAction.JSON_FIELD_THRESHOLD2_SPEED in json_obj: + threshold2_speed = float(json_obj[SetFanSpeedAction.JSON_FIELD_THRESHOLD2_SPEED]) + if threshold2_speed < 0 or threshold2_speed > 100: + raise ValueError('SetFanSpeedAction invalid default speed value {} in JSON policy file, valid value should be [0, 100]'. + format(threshold2_speed)) + self.threshold2_speed = float(json_obj[SetFanSpeedAction.JSON_FIELD_THRESHOLD2_SPEED]) + else: + raise ValueError('SetFanSpeedAction missing mandatory field {} in JSON policy file'. + format(SetFanSpeedAction.JSON_FIELD_THRESHOLD2_SPEED)) + if SetFanSpeedAction.JSON_FIELD_HIGHTEMP_SPEED in json_obj: hightemp_speed = float(json_obj[SetFanSpeedAction.JSON_FIELD_HIGHTEMP_SPEED]) if hightemp_speed < 0 or hightemp_speed > 100: @@ -103,7 +129,7 @@ def load_from_json(self, json_obj): raise ValueError('SetFanSpeedAction missing mandatory field {} in JSON policy file'. format(SetFanSpeedAction.JSON_FIELD_HIGHTEMP_SPEED)) - sonic_logger.log_warning("ThermalRecoverAction: default: {}, hightemp: {}".format(self.default_speed, self.hightemp_speed)) + sonic_logger.log_warning("ThermalRecoverAction: default: {}, threshold1: {}, threshold2: {}, hightemp: {}".format(self.default_speed, self.threshold1_speed, self.threshold2_speed, self.hightemp_speed)) def execute(self, thermal_info_dict): """ @@ -116,9 +142,13 @@ def execute(self, thermal_info_dict): isinstance(thermal_info_dict[ThermalInfo.INFO_NAME], ThermalInfo): thermal_info_obj = thermal_info_dict[ThermalInfo.INFO_NAME] - if thermal_info_obj.is_warm_up_and_over_high_threshold(): - ThermalRecoverAction.set_all_fan_speed(thermal_info_dict, self.hightemp_speed) - elif thermal_info_obj.is_cool_down_and_below_low_threshold(): + if thermal_info_obj.is_set_fan_high_temp_speed(): + ThermalRecoverAction.set_all_fan_speed(thermal_info_dict, self.hightemp_speed) + elif thermal_info_obj.is_set_fan_threshold_two_speed(): + ThermalRecoverAction.set_all_fan_speed(thermal_info_dict, self.threshold2_speed) + elif thermal_info_obj.is_set_fan_threshold_one_speed(): + ThermalRecoverAction.set_all_fan_speed(thermal_info_dict, self.threshold1_speed) + elif thermal_info_obj.is_set_fan_default_speed(): ThermalRecoverAction.set_all_fan_speed(thermal_info_dict, self.default_speed) diff --git a/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/thermal_infos.py b/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/thermal_infos.py index cd0a0591cd2a..cf9b0cdee6de 100644 --- a/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/thermal_infos.py +++ b/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/thermal_infos.py @@ -1,6 +1,8 @@ from sonic_platform_base.sonic_thermal_control.thermal_info_base import ThermalPolicyInfoBase from sonic_platform_base.sonic_thermal_control.thermal_json_object import thermal_json_object +from sonic_py_common.logger import Logger +logger = Logger() @thermal_json_object('fan_info') class FanInfo(ThermalPolicyInfoBase): @@ -67,12 +69,17 @@ class ThermalInfo(ThermalPolicyInfoBase): INFO_NAME = 'thermal_info' def __init__(self): - self.init = False - self._old_avg_temp = 0 - self._current_avg_temp = 0 + self._old_threshold_level = -1 + self._current_threshold_level = 0 + self._num_fan_levels = 3 self._high_crital_threshold = 75 - self._high_threshold = 45 - self._low_threshold = 40 + self._level_up_threshold = [[31,39,58,46], + [39,46,65,54], + [51,57,77,68]] + + self._level_down_threshold = [[24,31,47,40], + [31,38,53,46], + [48,54,72,63]] def collect(self, chassis): """ @@ -82,46 +89,84 @@ def collect(self, chassis): """ self._temps = [] self._over_high_critical_threshold = False - self._warm_up_and_over_high_threshold = False - self._cool_down_and_below_low_threshold = False + self._set_fan_default_speed = False + self._set_fan_threshold_one_speed = False + self._set_fan_threshold_two_speed = False + self._set_fan_high_temp_speed = False # Calculate average temp within the device - temp = 0 num_of_thermals = chassis.get_num_thermals() for index in range(num_of_thermals): self._temps.insert(index, chassis.get_thermal(index).get_temperature()) - temp += self._temps[index] + - self._current_avg_temp = temp / num_of_thermals - - # Special case if first time - if self.init is False: - self._old_avg_temp = self._current_avg_temp - self.init = True + # Find current required threshold level + max_level =0 + min_level = [self._num_fan_levels for i in range(num_of_thermals)] + for index in range(num_of_thermals): + for level in range(self._num_fan_levels): + + if self._temps[index]>self._level_up_threshold[level][index]: + if max_levellevel: + min_level[index]=level + + max_of_min_level=max(min_level) + + #compare with running threshold level + if max_of_min_level > self._old_threshold_level: + max_of_min_level=self._old_threshold_level + + self._current_threshold_level = max(max_of_min_level,max_level) + + #set fan to max speed if one fan is down + for fan in chassis.get_all_fans(): + if not fan.get_status() : + self._current_threshold_level = 3 + + # Decide fan speed based on threshold level - # Check if new average temp exceeds high threshold value - if self._current_avg_temp >= self._old_avg_temp and self._current_avg_temp >= self._high_threshold: - self._warm_up_and_over_high_threshold = True + if self._current_threshold_level != self._old_threshold_level: + if self._current_threshold_level == 0: + self._set_fan_default_speed = True + elif self._current_threshold_level == 1: + self._set_fan_threshold_one_speed = True + elif self._current_threshold_level == 2: + self._set_fan_threshold_two_speed = True + elif self._current_threshold_level == 3: + self._set_fan_high_temp_speed = True - # Check if new average temp exceeds low threshold value - if self._current_avg_temp <= self._old_avg_temp and self._current_avg_temp <= self._low_threshold: - self._cool_down_and_below_low_threshold = True + self._old_threshold_level=self._current_threshold_level - self._old_avg_temp = self._current_avg_temp + def is_set_fan_default_speed(self): + """ + Retrieves if the temperature is warm up and over high threshold + :return: True if the temperature is warm up and over high threshold else False + """ + return self._set_fan_default_speed - def is_warm_up_and_over_high_threshold(self): + def is_set_fan_threshold_one_speed(self): """ Retrieves if the temperature is warm up and over high threshold :return: True if the temperature is warm up and over high threshold else False """ - return self._warm_up_and_over_high_threshold + return self._set_fan_threshold_one_speed + + def is_set_fan_threshold_two_speed(self): + """ + Retrieves if the temperature is warm up and over high threshold + :return: True if the temperature is warm up and over high threshold else False + """ + return self._set_fan_threshold_two_speed - def is_cool_down_and_below_low_threshold(self): + def is_set_fan_high_temp_speed(self): """ - Retrieves if the temperature is cold down and below low threshold - :return: True if the temperature is cold down and below low threshold else False + Retrieves if the temperature is warm up and over high threshold + :return: True if the temperature is warm up and over high threshold else False """ - return self._cool_down_and_below_low_threshold + return self._set_fan_high_temp_speed def is_over_high_critical_threshold(self): """ diff --git a/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/watchdog.py b/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/watchdog.py index e351c90fe52e..cf655448d6df 100644 --- a/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/watchdog.py +++ b/platform/marvell-arm64/sonic-platform-nokia/7215/sonic_platform/watchdog.py @@ -11,6 +11,7 @@ from sonic_py_common import logger """ ioctl constants """ +IO_WRITE = 0x40000000 IO_READ = 0x80000000 IO_SIZE_INT = 0x00040000 IO_READ_WRITE = 0xC0000000 @@ -24,6 +25,8 @@ WDIOC_KEEPALIVE = 5 | WDR_INT WDIOC_SETTIMEOUT = 6 | WDWR_INT WDIOC_GETTIMEOUT = 7 | WDR_INT +WDIOC_SETPRETIMEOUT = 8 | WDWR_INT +WDIOC_GETPRETIMEOUT = 9 | WDR_INT WDIOC_GETTIMELEFT = 10 | WDR_INT """ Watchdog status constants """ @@ -49,6 +52,7 @@ def __init__(self, wd_device_path): Open a watchdog handle @param wd_device_path Path to watchdog device """ + super(WatchdogImplBase, self).__init__() self.watchdog_path = wd_device_path self.watchdog = os.open(self.watchdog_path, os.O_WRONLY) diff --git a/platform/marvell-arm64/sonic-platform-nokia/7215/utils/sonic_ssd.py b/platform/marvell-arm64/sonic-platform-nokia/7215/utils/sonic_ssd.py index 5065b470867c..563a0b22ce2d 100644 --- a/platform/marvell-arm64/sonic-platform-nokia/7215/utils/sonic_ssd.py +++ b/platform/marvell-arm64/sonic-platform-nokia/7215/utils/sonic_ssd.py @@ -44,6 +44,4 @@ def get_vendor_output(self): return '' def SsdUtil(diskdev): - if os.path.basename(diskdev).startswith('mmcblk'): - return EmmcUtil(diskdev) - return SsdUtilDefault(diskdev) + return EmmcUtil('/dev/mmcblk0') diff --git a/platform/marvell-arm64/sonic_fit.its b/platform/marvell-arm64/sonic_fit.its index b70877b27767..1671dd19ef6c 100644 --- a/platform/marvell-arm64/sonic_fit.its +++ b/platform/marvell-arm64/sonic_fit.its @@ -29,6 +29,17 @@ algo = "sha1"; }; }; + fdt_7215_a1 { + description = "Flattened Device Tree blob for 7215_IXS_A1"; + data = /incbin/("/usr/lib/linux-image-5.10.0-18-2-arm64/marvell/7215-ixs-a1.dtb"); + type = "flat_dt"; + arch = "arm64"; + compression = "none"; + load = <0x2 0x1000000>; + hash@1 { + algo = "sha1"; + }; + }; ramdisk_ac5x { description = "ramdisk for AC5x"; data = /incbin/("/boot/initrd.img-5.10.0-18-2-arm64"); @@ -54,5 +65,14 @@ algo = "sha1"; }; }; + conf_7215_a1 { + description = "Boot Linux kernel with FDT blob + ramdisk for 7125_IXS_A1"; + kernel = "kernel_ac5x"; + fdt = "fdt_7215_a1"; + ramdisk = "ramdisk_ac5x"; + hash@1 { + algo = "sha1"; + }; + }; }; }; diff --git a/platform/mellanox/.gitignore b/platform/mellanox/.gitignore index 1f3d15d640d4..9fc0ece98e1a 100644 --- a/platform/mellanox/.gitignore +++ b/platform/mellanox/.gitignore @@ -1,6 +1,4 @@ # Subdirectories -mlnx-sai/* -!mlnx-sai/Makefile hw-management/* !hw-management/Makefile !hw-management/*.patch diff --git a/platform/mellanox/docker-syncd-mlnx.mk b/platform/mellanox/docker-syncd-mlnx.mk index 144a571c308a..678a45fa8b0e 100644 --- a/platform/mellanox/docker-syncd-mlnx.mk +++ b/platform/mellanox/docker-syncd-mlnx.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2016-2021 NVIDIA CORPORATION & AFFILIATES. +# Copyright (c) 2016-2023 NVIDIA CORPORATION & AFFILIATES. # Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -19,7 +19,7 @@ DOCKER_SYNCD_PLATFORM_CODE = mlnx include $(PLATFORM_PATH)/../template/docker-syncd-bullseye.mk -$(DOCKER_SYNCD_BASE)_DEPENDS += $(SYNCD) $(PYTHON_SDK_API) $(MFT) $(IPROUTE2_MLNX) +$(DOCKER_SYNCD_BASE)_DEPENDS += $(SYNCD) $(PYTHON_SDK_API) $(MFT) $(MFT_FWTRACE_CFG) $(IPROUTE2_MLNX) ifeq ($(ENABLE_ASAN), y) $(DOCKER_SYNCD_BASE)_DEPENDS += $(SYNCD_DBG) diff --git a/platform/mellanox/fw.dep b/platform/mellanox/fw.dep index 228f6dc87e36..f57bad8eb9b0 100644 --- a/platform/mellanox/fw.dep +++ b/platform/mellanox/fw.dep @@ -14,3 +14,7 @@ $(MLNX_SPC2_FW_FILE)_DEP_FILES := $(DEP_FILES) $(MLNX_SPC3_FW_FILE)_CACHE_MODE := GIT_CONTENT_SHA $(MLNX_SPC3_FW_FILE)_DEP_FLAGS := $(SONIC_COMMON_FLAGS_LIST) $(MLNX_SPC3_FW_FILE)_DEP_FILES := $(DEP_FILES) + +$(MLNX_SPC4_FW_FILE)_CACHE_MODE := GIT_CONTENT_SHA +$(MLNX_SPC4_FW_FILE)_DEP_FLAGS := $(SONIC_COMMON_FLAGS_LIST) +$(MLNX_SPC4_FW_FILE)_DEP_FILES := $(DEP_FILES) diff --git a/platform/mellanox/fw.mk b/platform/mellanox/fw.mk index 9cde768bd1b8..e449c56e952a 100644 --- a/platform/mellanox/fw.mk +++ b/platform/mellanox/fw.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. +# Copyright (c) 2016-2023 NVIDIA CORPORATION & AFFILIATES. # Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -21,33 +21,38 @@ MLNX_FW_BASE_PATH = $(MLNX_SDK_BASE_PATH) # Place an URL here to FW if you want to download FW instead MLNX_FW_BASE_URL = -SIMX_VERSION = 23.4-1072 +SIMX_VERSION = 23.7-1086 FW_FROM_URL = y -MLNX_FW_ASSETS_RELEASE_TAG = fw-2010.5144 +MLNX_FW_ASSETS_RELEASE_TAG = fw-2012.1020 MLNX_FW_ASSETS_URL = $(MLNX_ASSETS_GITHUB_URL)/releases/download/$(MLNX_FW_ASSETS_RELEASE_TAG) ifeq ($(MLNX_FW_BASE_URL), ) MLNX_FW_BASE_URL = $(MLNX_FW_ASSETS_URL) endif -MLNX_SPC_FW_VERSION = 13.2010.5144 +MLNX_SPC_FW_VERSION = 13.2012.1020 MLNX_SPC_FW_FILE = fw-SPC-rel-$(subst .,_,$(MLNX_SPC_FW_VERSION))-EVB.mfa $(MLNX_SPC_FW_FILE)_PATH = $(MLNX_FW_BASE_PATH) $(MLNX_SPC_FW_FILE)_URL = $(MLNX_FW_BASE_URL)/$(MLNX_SPC_FW_FILE) -MLNX_SPC2_FW_VERSION = 29.2010.5144 +MLNX_SPC2_FW_VERSION = 29.2012.1020 MLNX_SPC2_FW_FILE = fw-SPC2-rel-$(subst .,_,$(MLNX_SPC2_FW_VERSION))-EVB.mfa $(MLNX_SPC2_FW_FILE)_PATH = $(MLNX_FW_BASE_PATH) $(MLNX_SPC2_FW_FILE)_URL = $(MLNX_FW_BASE_URL)/$(MLNX_SPC2_FW_FILE) -MLNX_SPC3_FW_VERSION = 30.2010.5144 +MLNX_SPC3_FW_VERSION = 30.2012.1020 MLNX_SPC3_FW_FILE = fw-SPC3-rel-$(subst .,_,$(MLNX_SPC3_FW_VERSION))-EVB.mfa $(MLNX_SPC3_FW_FILE)_PATH = $(MLNX_FW_BASE_PATH) $(MLNX_SPC3_FW_FILE)_URL = $(MLNX_FW_BASE_URL)/$(MLNX_SPC3_FW_FILE) -MLNX_FW_FILES = $(MLNX_SPC_FW_FILE) $(MLNX_SPC2_FW_FILE) $(MLNX_SPC3_FW_FILE) +MLNX_SPC4_FW_VERSION = 34.2012.1020 +MLNX_SPC4_FW_FILE = fw-SPC4-rel-$(subst .,_,$(MLNX_SPC4_FW_VERSION))-EVB.mfa +$(MLNX_SPC4_FW_FILE)_PATH = $(MLNX_FW_BASE_PATH) +$(MLNX_SPC4_FW_FILE)_URL = $(MLNX_FW_BASE_URL)/$(MLNX_SPC4_FW_FILE) + +MLNX_FW_FILES = $(MLNX_SPC_FW_FILE) $(MLNX_SPC2_FW_FILE) $(MLNX_SPC3_FW_FILE) $(MLNX_SPC4_FW_FILE) ifeq ($(FW_FROM_URL),n) SONIC_COPY_FILES += $(MLNX_FW_FILES) @@ -60,3 +65,4 @@ MLNX_FILES += $(MLNX_FW_FILES) export MLNX_SPC_FW_FILE export MLNX_SPC2_FW_FILE export MLNX_SPC3_FW_FILE +export MLNX_SPC4_FW_FILE diff --git a/platform/mellanox/mft-fwtrace-cfg.dep b/platform/mellanox/mft-fwtrace-cfg.dep new file mode 100644 index 000000000000..1dd698e3bb02 --- /dev/null +++ b/platform/mellanox/mft-fwtrace-cfg.dep @@ -0,0 +1,10 @@ +# DPKG FRK + +SPATH := $($(MFT_FWTRACE_CFG)_SRC_PATH) +DEP_FILES := $(SONIC_COMMON_FILES_LIST) $(PLATFORM_PATH)/mft-fwtrace-cfg.mk $(PLATFORM_PATH)/mft-fwtrace-cfg.dep +DEP_FILES += $(SONIC_COMMON_BASE_FILES_LIST) +DEP_FILES += $(shell git ls-files -- $(SPATH)) + +$(MFT_FWTRACE_CFG)_CACHE_MODE := GIT_CONTENT_SHA +$(MFT_FWTRACE_CFG)_DEP_FLAGS := $(SONIC_COMMON_FLAGS_LIST) +$(MFT_FWTRACE_CFG)_DEP_FILES := $(DEP_FILES) diff --git a/platform/mellanox/mft-fwtrace-cfg.mk b/platform/mellanox/mft-fwtrace-cfg.mk new file mode 100644 index 000000000000..9857fb063b5e --- /dev/null +++ b/platform/mellanox/mft-fwtrace-cfg.mk @@ -0,0 +1,22 @@ +# +# Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. +# Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +MFT_FWTRACE_CFG = mft-fwtrace-cfg-$(MFT_VERSION)-$(MFT_REVISION).deb +$(MFT_FWTRACE_CFG)_SRC_PATH = $(PLATFORM_PATH)/mft-fwtrace-cfg +SONIC_MAKE_DEBS += $(MFT_FWTRACE_CFG) + +export MFT_FWTRACE_CFG diff --git a/platform/mellanox/mft-fwtrace-cfg/DEBIAN/changelog b/platform/mellanox/mft-fwtrace-cfg/DEBIAN/changelog new file mode 100644 index 000000000000..d4bd60ef10ee --- /dev/null +++ b/platform/mellanox/mft-fwtrace-cfg/DEBIAN/changelog @@ -0,0 +1,5 @@ +mft-fwtrace-cfg (1.0.0) STABLE; urgency=low + + * Initial release. + + -- Vadym Hlushko Mon, 24 Jul 2023 12:03:04 +0300 diff --git a/platform/mellanox/mft-fwtrace-cfg/DEBIAN/control b/platform/mellanox/mft-fwtrace-cfg/DEBIAN/control new file mode 100755 index 000000000000..f71a8c72a5a9 --- /dev/null +++ b/platform/mellanox/mft-fwtrace-cfg/DEBIAN/control @@ -0,0 +1,7 @@ +Package: mft-fwtrace-cfg +Version: 1.0.0 +Section: utils +Priority: optional +Architecture: all +Maintainer: Vadym Hlushko +Description: fwtrace_cfg files for the mlxtrace utility from the MFT debian package diff --git a/platform/mellanox/mft-fwtrace-cfg/Makefile b/platform/mellanox/mft-fwtrace-cfg/Makefile new file mode 100644 index 000000000000..2862042174b5 --- /dev/null +++ b/platform/mellanox/mft-fwtrace-cfg/Makefile @@ -0,0 +1,25 @@ +# +# Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. +# Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +.ONESHELL: +SHELL = /bin/bash +.SHELLFLAGS += -e + +MAIN_TARGET = $(MFT_FWTRACE_CFG) + +$(addprefix $(DEST)/, $(MAIN_TARGET)): $(DEST)/% : + dpkg -b . $(MAIN_TARGET) + mv $(MAIN_TARGET) $(DEST)/ diff --git a/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum2_itrace.cfg.ext b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum2_itrace.cfg.ext new file mode 100644 index 000000000000..99e9445e4925 --- /dev/null +++ b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum2_itrace.cfg.ext @@ -0,0 +1,2570 @@ +OP1 Spectrum2 +OP4 ITRACE0 1 +OP4 ITRACE1 1 +OP4 ITRACE2 1 +OP4 ITRACE3 1 +OP4 ITRACE4 1 +OP4 ITRACE5 1 +OP4 ITRACE6 1 +OP4 ITRACE7 1 +OP4 Main_PhyUC 0 +OP4 E00009 0 +OP4 E0000A 0 +OP4 E0000B 0 +OP4 E0000C 0 +OP4 E0000D 0 +OP4 E0000E 0 +OP4 E0000F 0 +OP4 E00010 0 +OP4 E00011 0 +OP4 E00012 0 +OP4 E00013 0 +OP4 E00014 0 +OP4 E00015 0 +OP4 E00016 0 +OP4 E00017 0 +OP4 E00018 0 +OP4 E00019 0 +OP4 E0001A 0 +OP4 E0001B 0 +OP4 E0001C 0 +OP4 E0001D 0 +OP4 E0001E 0 +OP4 E0001F 0 +OP4 E00020 0 +OP4 E00021 0 +OP4 E00022 0 +OP4 E00023 0 +OP4 E00024 0 +OP4 E00025 0 +OP4 E00026 0 +OP4 E00027 0 +OP4 E00028 0 +OP4 E00029 0 +OP4 E0002A 0 +OP4 E0002B 0 +OP4 E0002C 0 +OP4 E0002D 0 +OP4 E0002E 0 +OP4 E0002F 0 +OP4 E00030 0 +OP4 E00031 0 +OP4 E00032 0 +OP4 E00033 0 +OP4 E00034 0 +OP4 E00035 0 +OP4 E00036 0 +OP4 E00037 0 +OP4 E00038 0 +OP4 E00039 0 +OP4 E0003A 0 +OP4 E0003B 0 +OP4 E0003C 0 +OP4 E0003D 0 +OP4 E0003E 0 +OP4 E0003F 0 +OP4 E00040 0 +OP4 E00041 0 +OP4 E00042 0 +OP4 E00043 0 +OP4 E00044 0 +OP4 E00045 0 +OP4 E00046 0 +OP4 E00047 0 +OP4 E00048 0 +OP4 E00049 0 +OP4 E0004A 0 +OP4 E0004B 0 +OP4 E0004C 0 +OP4 E0004D 0 +OP4 E0004E 0 +OP4 E0004F 0 +OP4 E00050 0 +OP4 E00051 0 +OP4 E00052 0 +OP4 E00053 0 +OP4 E00054 0 +OP4 E00055 0 +OP4 E00056 0 +OP4 E00057 0 +OP4 E00058 0 +OP4 E00059 0 +OP4 E0005A 0 +OP4 E0005B 0 +OP4 E0005C 0 +OP4 E0005D 0 +OP4 E0005E 0 +OP4 E0005F 0 +OP4 E00060 0 +OP4 E00061 0 +OP4 E00062 0 +OP4 E00063 0 +OP4 E00064 0 +OP4 E00065 0 +OP4 E00066 0 +OP4 E00067 0 +OP4 E00068 0 +OP4 E00069 0 +OP4 E0006A 0 +OP4 E0006B 0 +OP4 E0006C 0 +OP4 E0006D 0 +OP4 E0006E 0 +OP4 E0006F 0 +OP4 E00070 0 +OP4 E00071 0 +OP4 E00072 0 +OP4 E00073 0 +OP4 E00074 0 +OP4 E00075 0 +OP4 E00076 0 +OP4 E00077 0 +OP4 E00078 0 +OP4 E00079 0 +OP4 E0007A 0 +OP4 E0007B 0 +OP4 E0007C 0 +OP4 E0007D 0 +OP4 E0007E 0 +OP4 E0007F 0 +OP4 E00080 0 +OP4 E00081 0 +OP4 E00082 0 +OP4 E00083 0 +OP4 E00084 0 +OP4 E00085 0 +OP4 E00086 0 +OP4 E00087 0 +OP4 E00088 0 +OP4 E00089 0 +OP4 E0008A 0 +OP4 E0008B 0 +OP4 E0008C 0 +OP4 E0008D 0 +OP4 E0008E 0 +OP4 E0008F 0 +OP4 E00090 0 +OP4 E00091 0 +OP4 E00092 0 +OP4 E00093 0 +OP4 E00094 0 +OP4 E00095 0 +OP4 E00096 0 +OP4 E00097 0 +OP4 E00098 0 +OP4 E00099 0 +OP4 E0009A 0 +OP4 E0009B 0 +OP4 E0009C 0 +OP4 E0009D 0 +OP4 E0009E 0 +OP4 E0009F 0 +OP4 E000A0 0 +OP4 E000A1 0 +OP4 E000A2 0 +OP4 E000A3 0 +OP4 E000A4 0 +OP4 E000A5 0 +OP4 E000A6 0 +OP4 E000A7 0 +OP4 E000A8 0 +OP4 E000A9 0 +OP4 E000AA 0 +OP4 E000AB 0 +OP4 E000AC 0 +OP4 E000AD 0 +OP4 E000AE 0 +OP4 E000AF 0 +OP4 E000B0 0 +OP4 E000B1 0 +OP4 E000B2 0 +OP4 E000B3 0 +OP4 E000B4 0 +OP4 E000B5 0 +OP4 E000B6 0 +OP4 E000B7 0 +OP4 E000B8 0 +OP4 E000B9 0 +OP4 E000BA 0 +OP4 E000BB 0 +OP4 E000BC 0 +OP4 E000BD 0 +OP4 E000BE 0 +OP4 E000BF 0 +OP4 E000C0 0 +OP4 E000C1 0 +OP4 E000C2 0 +OP4 E000C3 0 +OP4 E000C4 0 +OP4 E000C5 0 +OP4 E000C6 0 +OP4 E000C7 0 +OP4 E000C8 0 +OP4 E000C9 0 +OP4 E000CA 0 +OP4 E000CB 0 +OP4 E000CC 0 +OP4 E000CD 0 +OP4 E000CE 0 +OP4 E000CF 0 +OP4 E000D0 0 +OP4 E000D1 0 +OP4 E000D2 0 +OP4 E000D3 0 +OP4 E000D4 0 +OP4 E000D5 0 +OP4 E000D6 0 +OP4 E000D7 0 +OP4 E000D8 0 +OP4 E000D9 0 +OP4 E000DA 0 +OP4 E000DB 0 +OP4 E000DC 0 +OP4 E000DD 0 +OP4 E000DE 0 +OP4 E000DF 0 +OP4 E000E0 0 +OP4 E000E1 0 +OP4 E000E2 0 +OP4 E000E3 0 +OP4 E000E4 0 +OP4 E000E5 0 +OP4 E000E6 0 +OP4 E000E7 0 +OP4 E000E8 0 +OP4 E000E9 0 +OP4 E000EA 0 +OP4 E000EB 0 +OP4 E000EC 0 +OP4 E000ED 0 +OP4 E000EE 0 +OP4 E000EF 0 +OP4 E000F0 0 +OP4 E000F1 0 +OP4 E000F2 0 +OP4 E000F3 0 +OP4 E000F4 0 +OP4 E000F5 0 +OP4 E000F6 0 +OP4 E000F7 0 +OP4 E000F8 0 +OP4 E000F9 0 +OP4 E000FA 0 +OP4 E000FB 0 +OP4 E000FC 0 +OP4 E000FD 0 +OP4 E000FE 0 +OP4 E000FF 0 +OP4 E00100 0 +OP4 E00101 0 +OP4 E00102 0 +OP4 E00103 0 +OP4 E00104 0 +OP4 E00105 0 +OP4 E00106 0 +OP4 E00107 0 +OP4 E00108 0 +OP4 E00109 0 +OP4 E0010A 0 +OP4 E0010B 0 +OP4 E0010C 0 +OP4 E0010D 0 +OP4 E0010E 0 +OP4 E0010F 0 +OP4 E00110 0 +OP4 E00111 0 +OP4 E00112 0 +OP4 E00113 0 +OP4 E00114 0 +OP4 E00115 0 +OP4 E00116 0 +OP4 E00117 0 +OP4 E00118 0 +OP4 E00119 0 +OP4 E0011A 0 +OP4 E0011B 0 +OP4 E0011C 0 +OP4 E0011D 0 +OP4 E0011E 0 +OP4 E0011F 0 +OP4 E00120 0 +OP4 E00121 0 +OP4 E00122 0 +OP4 E00123 0 +OP4 E00124 0 +OP4 E00125 0 +OP4 E00126 0 +OP4 E00127 0 +OP4 E00128 0 +OP4 E00129 0 +OP4 E0012A 0 +OP4 E0012B 0 +OP4 E0012C 0 +OP4 E0012D 0 +OP4 E0012E 0 +OP4 E0012F 0 +OP4 E00130 0 +OP4 E00131 0 +OP4 E00132 0 +OP4 E00133 0 +OP4 E00134 0 +OP4 E00135 0 +OP4 E00136 0 +OP4 E00137 0 +OP4 E00138 0 +OP4 E00139 0 +OP4 E0013A 0 +OP4 E0013B 0 +OP4 E0013C 0 +OP4 E0013D 0 +OP4 E0013E 0 +OP4 E0013F 0 +OP4 E00140 0 +OP4 E00141 0 +OP4 E00142 0 +OP4 E00143 0 +OP4 E00144 0 +OP4 E00145 0 +OP4 E00146 0 +OP4 E00147 0 +OP4 E00148 0 +OP4 E00149 0 +OP4 E0014A 0 +OP4 E0014B 0 +OP4 E0014C 0 +OP4 E0014D 0 +OP4 E0014E 0 +OP4 E0014F 0 +OP4 E00150 0 +OP4 E00151 0 +OP4 E00152 0 +OP4 E00153 0 +OP4 E00154 0 +OP4 E00155 0 +OP4 E00156 0 +OP4 E00157 0 +OP4 E00158 0 +OP4 E00159 0 +OP4 E0015A 0 +OP4 E0015B 0 +OP4 E0015C 0 +OP4 E0015D 0 +OP4 E0015E 0 +OP4 E0015F 0 +OP4 E00160 0 +OP4 E00161 0 +OP4 E00162 0 +OP4 E00163 0 +OP4 E00164 0 +OP4 E00165 0 +OP4 E00166 0 +OP4 E00167 0 +OP4 E00168 0 +OP4 E00169 0 +OP4 E0016A 0 +OP4 E0016B 0 +OP4 E0016C 0 +OP4 E0016D 0 +OP4 E0016E 0 +OP4 E0016F 0 +OP4 E00170 0 +OP4 E00171 0 +OP4 E00172 0 +OP4 E00173 0 +OP4 E00174 0 +OP4 E00175 0 +OP4 E00176 0 +OP4 E00177 0 +OP4 E00178 0 +OP4 E00179 0 +OP4 E0017A 0 +OP4 E0017B 0 +OP4 E0017C 0 +OP4 E0017D 0 +OP4 E0017E 0 +OP4 E0017F 0 +OP4 E00180 0 +OP4 E00181 0 +OP4 E00182 0 +OP4 E00183 0 +OP4 E00184 0 +OP4 E00185 0 +OP4 E00186 0 +OP4 E00187 0 +OP4 E00188 0 +OP4 E00189 0 +OP4 E0018A 0 +OP4 E0018B 0 +OP4 E0018C 0 +OP4 E0018D 0 +OP4 E0018E 0 +OP4 E0018F 0 +OP4 E00190 0 +OP4 E00191 0 +OP4 E00192 0 +OP4 E00193 0 +OP4 E00194 0 +OP4 E00195 0 +OP4 E00196 0 +OP4 E00197 0 +OP4 E00198 0 +OP4 E00199 0 +OP4 E0019A 0 +OP4 E0019B 0 +OP4 E0019C 0 +OP4 E0019D 0 +OP4 E0019E 0 +OP4 E0019F 0 +OP4 E001A0 0 +OP4 E001A1 0 +OP4 E001A2 0 +OP4 E001A3 0 +OP4 E001A4 0 +OP4 E001A5 0 +OP4 E001A6 0 +OP4 E001A7 0 +OP4 E001A8 0 +OP4 E001A9 0 +OP4 E001AA 0 +OP4 E001AB 0 +OP4 E001AC 0 +OP4 E001AD 0 +OP4 E001AE 0 +OP4 E001AF 0 +OP4 E001B0 0 +OP4 E001B1 0 +OP4 E001B2 0 +OP4 E001B3 0 +OP4 E001B4 0 +OP4 E001B5 0 +OP4 E001B6 0 +OP4 E001B7 0 +OP4 E001B8 0 +OP4 E001B9 0 +OP4 E001BA 0 +OP4 E001BB 0 +OP4 E001BC 0 +OP4 E001BD 0 +OP4 E001BE 0 +OP4 E001BF 0 +OP4 E001C0 0 +OP4 E001C1 0 +OP4 E001C2 0 +OP4 E001C3 0 +OP4 E001C4 0 +OP4 E001C5 0 +OP4 E001C6 0 +OP4 E001C7 0 +OP4 E001C8 0 +OP4 E001C9 0 +OP4 E001CA 0 +OP4 E001CB 0 +OP4 E001CC 0 +OP4 E001CD 0 +OP4 E001CE 0 +OP4 E001CF 0 +OP4 E001D0 0 +OP4 E001D1 0 +OP4 E001D2 0 +OP4 E001D3 0 +OP4 E001D4 0 +OP4 E001D5 0 +OP4 E001D6 0 +OP4 E001D7 0 +OP4 E001D8 0 +OP4 E001D9 0 +OP4 E001DA 0 +OP4 E001DB 0 +OP4 E001DC 0 +OP4 E001DD 0 +OP4 E001DE 0 +OP4 E001DF 0 +OP4 E001E0 0 +OP4 E001E1 0 +OP4 E001E2 0 +OP4 E001E3 0 +OP4 E001E4 0 +OP4 E001E5 0 +OP4 E001E6 0 +OP4 E001E7 0 +OP4 E001E8 0 +OP4 E001E9 0 +OP4 E001EA 0 +OP4 E001EB 0 +OP4 E001EC 0 +OP4 E001ED 0 +OP4 E001EE 0 +OP4 E001EF 0 +OP4 E001F0 0 +OP4 E001F1 0 +OP4 E001F2 0 +OP4 E001F3 0 +OP4 E001F4 0 +OP4 E001F5 0 +OP4 E001F6 0 +OP4 E001F7 0 +OP4 E001F8 0 +OP4 E001F9 0 +OP4 E001FA 0 +OP4 E001FB 0 +OP4 E001FC 0 +OP4 E001FD 0 +OP4 E001FE 0 +OP4 E001FF 0 +OP4 E00200 0 +OP4 E00201 0 +OP4 E00202 0 +OP4 E00203 0 +OP4 E00204 0 +OP4 E00205 0 +OP4 E00206 0 +OP4 E00207 0 +OP4 E00208 0 +OP4 E00209 0 +OP4 E0020A 0 +OP4 E0020B 0 +OP4 E0020C 0 +OP4 E0020D 0 +OP4 E0020E 0 +OP4 E0020F 0 +OP4 E00210 0 +OP4 E00211 0 +OP4 E00212 0 +OP4 E00213 0 +OP4 E00214 0 +OP4 E00215 0 +OP4 E00216 0 +OP4 E00217 0 +OP4 E00218 0 +OP4 E00219 0 +OP4 E0021A 0 +OP4 E0021B 0 +OP4 E0021C 0 +OP4 E0021D 0 +OP4 E0021E 0 +OP4 E0021F 0 +OP4 E00220 0 +OP4 E00221 0 +OP4 E00222 0 +OP4 E00223 0 +OP4 E00224 0 +OP4 E00225 0 +OP4 E00226 0 +OP4 E00227 0 +OP4 E00228 0 +OP4 E00229 0 +OP4 E0022A 0 +OP4 E0022B 0 +OP4 E0022C 0 +OP4 E0022D 0 +OP4 E0022E 0 +OP4 E0022F 0 +OP4 E00230 0 +OP4 E00231 0 +OP4 E00232 0 +OP4 E00233 0 +OP4 E00234 0 +OP4 E00235 0 +OP4 E00236 0 +OP4 E00237 0 +OP4 E00238 0 +OP4 E00239 0 +OP4 E0023A 0 +OP4 E0023B 0 +OP4 E0023C 0 +OP4 E0023D 0 +OP4 E0023E 0 +OP4 E0023F 0 +OP4 E00240 0 +OP4 E00241 0 +OP4 E00242 0 +OP4 E00243 0 +OP4 E00244 0 +OP4 E00245 0 +OP4 E00246 0 +OP4 E00247 0 +OP4 E00248 0 +OP4 E00249 0 +OP4 E0024A 0 +OP4 E0024B 0 +OP4 E0024C 0 +OP4 E0024D 0 +OP4 E0024E 0 +OP4 E0024F 0 +OP4 E00250 0 +OP4 E00251 0 +OP4 E00252 0 +OP4 E00253 0 +OP4 E00254 0 +OP4 E00255 0 +OP4 E00256 0 +OP4 E00257 0 +OP4 E00258 0 +OP4 E00259 0 +OP4 E0025A 0 +OP4 E0025B 0 +OP4 E0025C 0 +OP4 E0025D 0 +OP4 E0025E 0 +OP4 E0025F 0 +OP4 E00260 0 +OP4 E00261 0 +OP4 E00262 0 +OP4 E00263 0 +OP4 E00264 0 +OP4 E00265 0 +OP4 E00266 0 +OP4 E00267 0 +OP4 E00268 0 +OP4 E00269 0 +OP4 E0026A 0 +OP4 E0026B 0 +OP4 E0026C 0 +OP4 E0026D 0 +OP4 E0026E 0 +OP4 E0026F 0 +OP4 E00270 0 +OP4 E00271 0 +OP4 E00272 0 +OP4 E00273 0 +OP4 E00274 0 +OP4 E00275 0 +OP4 E00276 0 +OP4 E00277 0 +OP4 E00278 0 +OP4 E00279 0 +OP4 E0027A 0 +OP4 E0027B 0 +OP4 E0027C 0 +OP4 E0027D 0 +OP4 E0027E 0 +OP4 E0027F 0 +OP4 E00280 0 +OP4 E00281 0 +OP4 E00282 0 +OP4 E00283 0 +OP4 E00284 0 +OP4 E00285 0 +OP4 E00286 0 +OP4 E00287 0 +OP4 E00288 0 +OP4 E00289 0 +OP4 E0028A 0 +OP4 E0028B 0 +OP4 E0028C 0 +OP4 E0028D 0 +OP4 E0028E 0 +OP4 E0028F 0 +OP4 E00290 0 +OP4 E00291 0 +OP4 E00292 0 +OP4 E00293 0 +OP4 E00294 0 +OP4 E00295 0 +OP4 E00296 0 +OP4 E00297 0 +OP4 E00298 0 +OP4 E00299 0 +OP4 E0029A 0 +OP4 E0029B 0 +OP4 E0029C 0 +OP4 E0029D 0 +OP4 E0029E 0 +OP4 E0029F 0 +OP4 E002A0 0 +OP4 E002A1 0 +OP4 E002A2 0 +OP4 E002A3 0 +OP4 E002A4 0 +OP4 E002A5 0 +OP4 E002A6 0 +OP4 E002A7 0 +OP4 E002A8 0 +OP4 E002A9 0 +OP4 E002AA 0 +OP4 E002AB 0 +OP4 E002AC 0 +OP4 E002AD 0 +OP4 E002AE 0 +OP4 E002AF 0 +OP4 E002B0 0 +OP4 E002B1 0 +OP4 E002B2 0 +OP4 E002B3 0 +OP4 E002B4 0 +OP4 E002B5 0 +OP4 E002B6 0 +OP4 E002B7 0 +OP4 E002B8 0 +OP4 E002B9 0 +OP4 E002BA 0 +OP4 E002BB 0 +OP4 E002BC 0 +OP4 E002BD 0 +OP4 E002BE 0 +OP4 E002BF 0 +OP4 E002C0 0 +OP4 E002C1 0 +OP4 E002C2 0 +OP4 E002C3 0 +OP4 E002C4 0 +OP4 E002C5 0 +OP4 E002C6 0 +OP4 E002C7 0 +OP4 E002C8 0 +OP4 E002C9 0 +OP4 E002CA 0 +OP4 E002CB 0 +OP4 E002CC 0 +OP4 E002CD 0 +OP4 E002CE 0 +OP4 E002CF 0 +OP4 E002D0 0 +OP4 E002D1 0 +OP4 E002D2 0 +OP4 E002D3 0 +OP4 E002D4 0 +OP4 E002D5 0 +OP4 E002D6 0 +OP4 E002D7 0 +OP4 E002D8 0 +OP4 E002D9 0 +OP4 E002DA 0 +OP4 E002DB 0 +OP4 E002DC 0 +OP4 E002DD 0 +OP4 E002DE 0 +OP4 E002DF 0 +OP4 E002E0 0 +OP4 E002E1 0 +OP4 E002E2 0 +OP4 E002E3 0 +OP4 E002E4 0 +OP4 E002E5 0 +OP4 E002E6 0 +OP4 E002E7 0 +OP4 E002E8 0 +OP4 E002E9 0 +OP4 E002EA 0 +OP4 E002EB 0 +OP4 E002EC 0 +OP4 E002ED 0 +OP4 E002EE 0 +OP4 E002EF 0 +OP4 E002F0 0 +OP4 E002F1 0 +OP4 E002F2 0 +OP4 E002F3 0 +OP4 E002F4 0 +OP4 E002F5 0 +OP4 E002F6 0 +OP4 E002F7 0 +OP4 E002F8 0 +OP4 E002F9 0 +OP4 E002FA 0 +OP4 E002FB 0 +OP4 E002FC 0 +OP4 E002FD 0 +OP4 E002FE 0 +OP4 E002FF 0 +OP4 E00300 0 +OP4 E00301 0 +OP4 E00302 0 +OP4 E00303 0 +OP4 E00304 0 +OP4 E00305 0 +OP4 E00306 0 +OP4 E00307 0 +OP4 E00308 0 +OP4 E00309 0 +OP4 E0030A 0 +OP4 E0030B 0 +OP4 E0030C 0 +OP4 E0030D 0 +OP4 E0030E 0 +OP4 E0030F 0 +OP4 E00310 0 +OP4 E00311 0 +OP4 E00312 0 +OP4 E00313 0 +OP4 E00314 0 +OP4 E00315 0 +OP4 E00316 0 +OP4 E00317 0 +OP4 E00318 0 +OP4 E00319 0 +OP4 E0031A 0 +OP4 E0031B 0 +OP4 E0031C 0 +OP4 E0031D 0 +OP4 E0031E 0 +OP4 E0031F 0 +OP4 E00320 0 +OP4 E00321 0 +OP4 E00322 0 +OP4 E00323 0 +OP4 E00324 0 +OP4 E00325 0 +OP4 E00326 0 +OP4 E00327 0 +OP4 E00328 0 +OP4 E00329 0 +OP4 E0032A 0 +OP4 E0032B 0 +OP4 E0032C 0 +OP4 E0032D 0 +OP4 E0032E 0 +OP4 E0032F 0 +OP4 E00330 0 +OP4 E00331 0 +OP4 E00332 0 +OP4 E00333 0 +OP4 E00334 0 +OP4 E00335 0 +OP4 E00336 0 +OP4 E00337 0 +OP4 E00338 0 +OP4 E00339 0 +OP4 E0033A 0 +OP4 E0033B 0 +OP4 E0033C 0 +OP4 E0033D 0 +OP4 E0033E 0 +OP4 E0033F 0 +OP4 E00340 0 +OP4 E00341 0 +OP4 E00342 0 +OP4 E00343 0 +OP4 E00344 0 +OP4 E00345 0 +OP4 E00346 0 +OP4 E00347 0 +OP4 E00348 0 +OP4 E00349 0 +OP4 E0034A 0 +OP4 E0034B 0 +OP4 E0034C 0 +OP4 E0034D 0 +OP4 E0034E 0 +OP4 E0034F 0 +OP4 E00350 0 +OP4 E00351 0 +OP4 E00352 0 +OP4 E00353 0 +OP4 E00354 0 +OP4 E00355 0 +OP4 E00356 0 +OP4 E00357 0 +OP4 E00358 0 +OP4 E00359 0 +OP4 E0035A 0 +OP4 E0035B 0 +OP4 E0035C 0 +OP4 E0035D 0 +OP4 E0035E 0 +OP4 E0035F 0 +OP4 E00360 0 +OP4 E00361 0 +OP4 E00362 0 +OP4 E00363 0 +OP4 E00364 0 +OP4 E00365 0 +OP4 E00366 0 +OP4 E00367 0 +OP4 E00368 0 +OP4 E00369 0 +OP4 E0036A 0 +OP4 E0036B 0 +OP4 E0036C 0 +OP4 E0036D 0 +OP4 E0036E 0 +OP4 E0036F 0 +OP4 E00370 0 +OP4 E00371 0 +OP4 E00372 0 +OP4 E00373 0 +OP4 E00374 0 +OP4 E00375 0 +OP4 E00376 0 +OP4 E00377 0 +OP4 E00378 0 +OP4 E00379 0 +OP4 E0037A 0 +OP4 E0037B 0 +OP4 E0037C 0 +OP4 E0037D 0 +OP4 E0037E 0 +OP4 E0037F 0 +OP4 E00380 0 +OP4 E00381 0 +OP4 E00382 0 +OP4 E00383 0 +OP4 E00384 0 +OP4 E00385 0 +OP4 E00386 0 +OP4 E00387 0 +OP4 E00388 0 +OP4 E00389 0 +OP4 E0038A 0 +OP4 E0038B 0 +OP4 E0038C 0 +OP4 E0038D 0 +OP4 E0038E 0 +OP4 E0038F 0 +OP4 E00390 0 +OP4 E00391 0 +OP4 E00392 0 +OP4 E00393 0 +OP4 E00394 0 +OP4 E00395 0 +OP4 E00396 0 +OP4 E00397 0 +OP4 E00398 0 +OP4 E00399 0 +OP4 E0039A 0 +OP4 E0039B 0 +OP4 E0039C 0 +OP4 E0039D 0 +OP4 E0039E 0 +OP4 E0039F 0 +OP4 E003A0 0 +OP4 E003A1 0 +OP4 E003A2 0 +OP4 E003A3 0 +OP4 E003A4 0 +OP4 E003A5 0 +OP4 E003A6 0 +OP4 E003A7 0 +OP4 E003A8 0 +OP4 E003A9 0 +OP4 E003AA 0 +OP4 E003AB 0 +OP4 E003AC 0 +OP4 E003AD 0 +OP4 E003AE 0 +OP4 E003AF 0 +OP4 E003B0 0 +OP4 E003B1 0 +OP4 E003B2 0 +OP4 E003B3 0 +OP4 E003B4 0 +OP4 E003B5 0 +OP4 E003B6 0 +OP4 E003B7 0 +OP4 E003B8 0 +OP4 E003B9 0 +OP4 E003BA 0 +OP4 E003BB 0 +OP4 E003BC 0 +OP4 E003BD 0 +OP4 E003BE 0 +OP4 E003BF 0 +OP4 E003C0 0 +OP4 E003C1 0 +OP4 E003C2 0 +OP4 E003C3 0 +OP4 E003C4 0 +OP4 E003C5 0 +OP4 E003C6 0 +OP4 E003C7 0 +OP4 E003C8 0 +OP4 E003C9 0 +OP4 E003CA 0 +OP4 E003CB 0 +OP4 E003CC 0 +OP4 E003CD 0 +OP4 E003CE 0 +OP4 E003CF 0 +OP4 E003D0 0 +OP4 E003D1 0 +OP4 E003D2 0 +OP4 E003D3 0 +OP4 E003D4 0 +OP4 E003D5 0 +OP4 E003D6 0 +OP4 E003D7 0 +OP4 E003D8 0 +OP4 E003D9 0 +OP4 E003DA 0 +OP4 E003DB 0 +OP4 E003DC 0 +OP4 E003DD 0 +OP4 E003DE 0 +OP4 E003DF 0 +OP4 E003E0 0 +OP4 E003E1 0 +OP4 E003E2 0 +OP4 E003E3 0 +OP4 E003E4 0 +OP4 E003E5 0 +OP4 E003E6 0 +OP4 E003E7 0 +OP4 E003E8 0 +OP4 E003E9 0 +OP4 E003EA 0 +OP4 E003EB 0 +OP4 E003EC 0 +OP4 E003ED 0 +OP4 E003EE 0 +OP4 E003EF 0 +OP4 E003F0 0 +OP4 E003F1 0 +OP4 E003F2 0 +OP4 E003F3 0 +OP4 E003F4 0 +OP4 E003F5 0 +OP4 E003F6 0 +OP4 E003F7 0 +OP4 E003F8 0 +OP4 E003F9 0 +OP4 E003FA 0 +OP4 E003FB 0 +OP4 E003FC 0 +OP4 E003FD 0 +OP4 E003FE 0 +OP4 E003FF 0 +OP4 E00400 0 +OP4 E00401 0 +OP4 E00402 0 +OP4 E00403 0 +OP4 E00404 0 +OP4 E00405 0 +OP4 E00406 0 +OP4 E00407 0 +OP4 E00408 0 +OP4 E00409 0 +OP4 E0040A 0 +OP4 E0040B 0 +OP4 E0040C 0 +OP4 E0040D 0 +OP4 E0040E 0 +OP4 E0040F 0 +OP4 E00410 0 +OP4 E00411 0 +OP4 E00412 0 +OP4 E00413 0 +OP4 E00414 0 +OP4 E00415 0 +OP4 E00416 0 +OP4 E00417 0 +OP4 E00418 0 +OP4 E00419 0 +OP4 E0041A 0 +OP4 E0041B 0 +OP4 E0041C 0 +OP4 E0041D 0 +OP4 E0041E 0 +OP4 E0041F 0 +OP4 E00420 0 +OP4 E00421 0 +OP4 E00422 0 +OP4 E00423 0 +OP4 E00424 0 +OP4 E00425 0 +OP4 E00426 0 +OP4 E00427 0 +OP4 E00428 0 +OP4 E00429 0 +OP4 E0042A 0 +OP4 E0042B 0 +OP4 E0042C 0 +OP4 E0042D 0 +OP4 E0042E 0 +OP4 E0042F 0 +OP4 E00430 0 +OP4 E00431 0 +OP4 E00432 0 +OP4 E00433 0 +OP4 E00434 0 +OP4 E00435 0 +OP4 E00436 0 +OP4 E00437 0 +OP4 E00438 0 +OP4 E00439 0 +OP4 E0043A 0 +OP4 E0043B 0 +OP4 E0043C 0 +OP4 E0043D 0 +OP4 E0043E 0 +OP4 E0043F 0 +OP4 E00440 0 +OP4 E00441 0 +OP4 E00442 0 +OP4 E00443 0 +OP4 E00444 0 +OP4 E00445 0 +OP4 E00446 0 +OP4 E00447 0 +OP4 E00448 0 +OP4 E00449 0 +OP4 E0044A 0 +OP4 E0044B 0 +OP4 E0044C 0 +OP4 E0044D 0 +OP4 E0044E 0 +OP4 E0044F 0 +OP4 E00450 0 +OP4 E00451 0 +OP4 E00452 0 +OP4 E00453 0 +OP4 E00454 0 +OP4 E00455 0 +OP4 E00456 0 +OP4 E00457 0 +OP4 E00458 0 +OP4 E00459 0 +OP4 E0045A 0 +OP4 E0045B 0 +OP4 E0045C 0 +OP4 E0045D 0 +OP4 E0045E 0 +OP4 E0045F 0 +OP4 E00460 0 +OP4 E00461 0 +OP4 E00462 0 +OP4 E00463 0 +OP4 E00464 0 +OP4 E00465 0 +OP4 E00466 0 +OP4 E00467 0 +OP4 E00468 0 +OP4 E00469 0 +OP4 E0046A 0 +OP4 E0046B 0 +OP4 E0046C 0 +OP4 E0046D 0 +OP4 E0046E 0 +OP4 E0046F 0 +OP4 E00470 0 +OP4 E00471 0 +OP4 E00472 0 +OP4 E00473 0 +OP4 E00474 0 +OP4 E00475 0 +OP4 E00476 0 +OP4 E00477 0 +OP4 E00478 0 +OP4 E00479 0 +OP4 E0047A 0 +OP4 E0047B 0 +OP4 E0047C 0 +OP4 E0047D 0 +OP4 E0047E 0 +OP4 E0047F 0 +OP4 E00480 0 +OP4 E00481 0 +OP4 E00482 0 +OP4 E00483 0 +OP4 E00484 0 +OP4 E00485 0 +OP4 E00486 0 +OP4 E00487 0 +OP4 E00488 0 +OP4 E00489 0 +OP4 E0048A 0 +OP4 E0048B 0 +OP4 E0048C 0 +OP4 E0048D 0 +OP4 E0048E 0 +OP4 E0048F 0 +OP4 E00490 0 +OP4 E00491 0 +OP4 E00492 0 +OP4 E00493 0 +OP4 E00494 0 +OP4 E00495 0 +OP4 E00496 0 +OP4 E00497 0 +OP4 E00498 0 +OP4 E00499 0 +OP4 E0049A 0 +OP4 E0049B 0 +OP4 E0049C 0 +OP4 E0049D 0 +OP4 E0049E 0 +OP4 E0049F 0 +OP4 E004A0 0 +OP4 E004A1 0 +OP4 E004A2 0 +OP4 E004A3 0 +OP4 E004A4 0 +OP4 E004A5 0 +OP4 E004A6 0 +OP4 E004A7 0 +OP4 E004A8 0 +OP4 E004A9 0 +OP4 E004AA 0 +OP4 E004AB 0 +OP4 E004AC 0 +OP4 E004AD 0 +OP4 E004AE 0 +OP4 E004AF 0 +OP4 E004B0 0 +OP4 E004B1 0 +OP4 E004B2 0 +OP4 E004B3 0 +OP4 E004B4 0 +OP4 E004B5 0 +OP4 E004B6 0 +OP4 E004B7 0 +OP4 E004B8 0 +OP4 E004B9 0 +OP4 E004BA 0 +OP4 E004BB 0 +OP4 E004BC 0 +OP4 E004BD 0 +OP4 E004BE 0 +OP4 E004BF 0 +OP4 E004C0 0 +OP4 E004C1 0 +OP4 E004C2 0 +OP4 E004C3 0 +OP4 E004C4 0 +OP4 E004C5 0 +OP4 E004C6 0 +OP4 E004C7 0 +OP4 E004C8 0 +OP4 E004C9 0 +OP4 E004CA 0 +OP4 E004CB 0 +OP4 E004CC 0 +OP4 E004CD 0 +OP4 E004CE 0 +OP4 E004CF 0 +OP4 E004D0 0 +OP4 E004D1 0 +OP4 E004D2 0 +OP4 E004D3 0 +OP4 E004D4 0 +OP4 E004D5 0 +OP4 E004D6 0 +OP4 E004D7 0 +OP4 E004D8 0 +OP4 E004D9 0 +OP4 E004DA 0 +OP4 E004DB 0 +OP4 E004DC 0 +OP4 E004DD 0 +OP4 E004DE 0 +OP4 E004DF 0 +OP4 E004E0 0 +OP4 E004E1 0 +OP4 E004E2 0 +OP4 E004E3 0 +OP4 E004E4 0 +OP4 E004E5 0 +OP4 E004E6 0 +OP4 E004E7 0 +OP4 E004E8 0 +OP4 E004E9 0 +OP4 E004EA 0 +OP4 E004EB 0 +OP4 E004EC 0 +OP4 E004ED 0 +OP4 E004EE 0 +OP4 E004EF 0 +OP4 E004F0 0 +OP4 E004F1 0 +OP4 E004F2 0 +OP4 E004F3 0 +OP4 E004F4 0 +OP4 E004F5 0 +OP4 E004F6 0 +OP4 E004F7 0 +OP4 E004F8 0 +OP4 E004F9 0 +OP4 E004FA 0 +OP4 E004FB 0 +OP4 E004FC 0 +OP4 E004FD 0 +OP4 E004FE 0 +OP4 E004FF 0 +OP4 E00500 0 +OP4 E00501 0 +OP4 E00502 0 +OP4 E00503 0 +OP4 E00504 0 +OP4 E00505 0 +OP4 E00506 0 +OP4 E00507 0 +OP4 E00508 0 +OP4 E00509 0 +OP4 E0050A 0 +OP4 E0050B 0 +OP4 E0050C 0 +OP4 E0050D 0 +OP4 E0050E 0 +OP4 E0050F 0 +OP4 E00510 0 +OP4 E00511 0 +OP4 E00512 0 +OP4 E00513 0 +OP4 E00514 0 +OP4 E00515 0 +OP4 E00516 0 +OP4 E00517 0 +OP4 E00518 0 +OP4 E00519 0 +OP4 E0051A 0 +OP4 E0051B 0 +OP4 E0051C 0 +OP4 E0051D 0 +OP4 E0051E 0 +OP4 E0051F 0 +OP4 E00520 0 +OP4 E00521 0 +OP4 E00522 0 +OP4 E00523 0 +OP4 E00524 0 +OP4 E00525 0 +OP4 E00526 0 +OP4 E00527 0 +OP4 E00528 0 +OP4 E00529 0 +OP4 E0052A 0 +OP4 E0052B 0 +OP4 E0052C 0 +OP4 E0052D 0 +OP4 E0052E 0 +OP4 E0052F 0 +OP4 E00530 0 +OP4 E00531 0 +OP4 E00532 0 +OP4 E00533 0 +OP4 E00534 0 +OP4 E00535 0 +OP4 E00536 0 +OP4 E00537 0 +OP4 E00538 0 +OP4 E00539 0 +OP4 E0053A 0 +OP4 E0053B 0 +OP4 E0053C 0 +OP4 E0053D 0 +OP4 E0053E 0 +OP4 E0053F 0 +OP4 E00540 0 +OP4 E00541 0 +OP4 E00542 0 +OP4 E00543 0 +OP4 E00544 0 +OP4 E00545 0 +OP4 E00546 0 +OP4 E00547 0 +OP4 E00548 0 +OP4 E00549 0 +OP4 E0054A 0 +OP4 E0054B 0 +OP4 E0054C 0 +OP4 E0054D 0 +OP4 E0054E 0 +OP4 E0054F 0 +OP4 E00550 0 +OP4 E00551 0 +OP4 E00552 0 +OP4 E00553 0 +OP4 E00554 0 +OP4 E00555 0 +OP4 E00556 0 +OP4 E00557 0 +OP4 E00558 0 +OP4 E00559 0 +OP4 E0055A 0 +OP4 E0055B 0 +OP4 E0055C 0 +OP4 E0055D 0 +OP4 E0055E 0 +OP4 E0055F 0 +OP4 E00560 0 +OP4 E00561 0 +OP4 E00562 0 +OP4 E00563 0 +OP4 E00564 0 +OP4 E00565 0 +OP4 E00566 0 +OP4 E00567 0 +OP4 E00568 0 +OP4 E00569 0 +OP4 E0056A 0 +OP4 E0056B 0 +OP4 E0056C 0 +OP4 E0056D 0 +OP4 E0056E 0 +OP4 E0056F 0 +OP4 E00570 0 +OP4 E00571 0 +OP4 E00572 0 +OP4 E00573 0 +OP4 E00574 0 +OP4 E00575 0 +OP4 E00576 0 +OP4 E00577 0 +OP4 E00578 0 +OP4 E00579 0 +OP4 E0057A 0 +OP4 E0057B 0 +OP4 E0057C 0 +OP4 E0057D 0 +OP4 E0057E 0 +OP4 E0057F 0 +OP4 E00580 0 +OP4 E00581 0 +OP4 E00582 0 +OP4 E00583 0 +OP4 E00584 0 +OP4 E00585 0 +OP4 E00586 0 +OP4 E00587 0 +OP4 E00588 0 +OP4 E00589 0 +OP4 E0058A 0 +OP4 E0058B 0 +OP4 E0058C 0 +OP4 E0058D 0 +OP4 E0058E 0 +OP4 E0058F 0 +OP4 E00590 0 +OP4 E00591 0 +OP4 E00592 0 +OP4 E00593 0 +OP4 E00594 0 +OP4 E00595 0 +OP4 E00596 0 +OP4 E00597 0 +OP4 E00598 0 +OP4 E00599 0 +OP4 E0059A 0 +OP4 E0059B 0 +OP4 E0059C 0 +OP4 E0059D 0 +OP4 E0059E 0 +OP4 E0059F 0 +OP4 E005A0 0 +OP4 E005A1 0 +OP4 E005A2 0 +OP4 E005A3 0 +OP4 E005A4 0 +OP4 E005A5 0 +OP4 E005A6 0 +OP4 E005A7 0 +OP4 E005A8 0 +OP4 E005A9 0 +OP4 E005AA 0 +OP4 E005AB 0 +OP4 E005AC 0 +OP4 E005AD 0 +OP4 E005AE 0 +OP4 E005AF 0 +OP4 E005B0 0 +OP4 E005B1 0 +OP4 E005B2 0 +OP4 E005B3 0 +OP4 E005B4 0 +OP4 E005B5 0 +OP4 E005B6 0 +OP4 E005B7 0 +OP4 E005B8 0 +OP4 E005B9 0 +OP4 E005BA 0 +OP4 E005BB 0 +OP4 E005BC 0 +OP4 E005BD 0 +OP4 E005BE 0 +OP4 E005BF 0 +OP4 E005C0 0 +OP4 E005C1 0 +OP4 E005C2 0 +OP4 E005C3 0 +OP4 E005C4 0 +OP4 E005C5 0 +OP4 E005C6 0 +OP4 E005C7 0 +OP4 E005C8 0 +OP4 E005C9 0 +OP4 E005CA 0 +OP4 E005CB 0 +OP4 E005CC 0 +OP4 E005CD 0 +OP4 E005CE 0 +OP4 E005CF 0 +OP4 E005D0 0 +OP4 E005D1 0 +OP4 E005D2 0 +OP4 E005D3 0 +OP4 E005D4 0 +OP4 E005D5 0 +OP4 E005D6 0 +OP4 E005D7 0 +OP4 E005D8 0 +OP4 E005D9 0 +OP4 E005DA 0 +OP4 E005DB 0 +OP4 E005DC 0 +OP4 E005DD 0 +OP4 E005DE 0 +OP4 E005DF 0 +OP4 E005E0 0 +OP4 E005E1 0 +OP4 E005E2 0 +OP4 E005E3 0 +OP4 E005E4 0 +OP4 E005E5 0 +OP4 E005E6 0 +OP4 E005E7 0 +OP4 E005E8 0 +OP4 E005E9 0 +OP4 E005EA 0 +OP4 E005EB 0 +OP4 E005EC 0 +OP4 E005ED 0 +OP4 E005EE 0 +OP4 E005EF 0 +OP4 E005F0 0 +OP4 E005F1 0 +OP4 E005F2 0 +OP4 E005F3 0 +OP4 E005F4 0 +OP4 E005F5 0 +OP4 E005F6 0 +OP4 E005F7 0 +OP4 E005F8 0 +OP4 E005F9 0 +OP4 E005FA 0 +OP4 E005FB 0 +OP4 E005FC 0 +OP4 E005FD 0 +OP4 E005FE 0 +OP4 E005FF 0 +OP4 E00600 0 +OP4 E00601 0 +OP4 E00602 0 +OP4 E00603 0 +OP4 E00604 0 +OP4 E00605 0 +OP4 E00606 0 +OP4 E00607 0 +OP4 E00608 0 +OP4 E00609 0 +OP4 E0060A 0 +OP4 E0060B 0 +OP4 E0060C 0 +OP4 E0060D 0 +OP4 E0060E 0 +OP4 E0060F 0 +OP4 E00610 0 +OP4 E00611 0 +OP4 E00612 0 +OP4 E00613 0 +OP4 E00614 0 +OP4 E00615 0 +OP4 E00616 0 +OP4 E00617 0 +OP4 E00618 0 +OP4 E00619 0 +OP4 E0061A 0 +OP4 E0061B 0 +OP4 E0061C 0 +OP4 E0061D 0 +OP4 E0061E 0 +OP4 E0061F 0 +OP4 E00620 0 +OP4 E00621 0 +OP4 E00622 0 +OP4 E00623 0 +OP4 E00624 0 +OP4 E00625 0 +OP4 E00626 0 +OP4 E00627 0 +OP4 E00628 0 +OP4 E00629 0 +OP4 E0062A 0 +OP4 E0062B 0 +OP4 E0062C 0 +OP4 E0062D 0 +OP4 E0062E 0 +OP4 E0062F 0 +OP4 E00630 0 +OP4 E00631 0 +OP4 E00632 0 +OP4 E00633 0 +OP4 E00634 0 +OP4 E00635 0 +OP4 E00636 0 +OP4 E00637 0 +OP4 E00638 0 +OP4 E00639 0 +OP4 E0063A 0 +OP4 E0063B 0 +OP4 E0063C 0 +OP4 E0063D 0 +OP4 E0063E 0 +OP4 E0063F 0 +OP4 E00640 0 +OP4 E00641 0 +OP4 E00642 0 +OP4 E00643 0 +OP4 E00644 0 +OP4 E00645 0 +OP4 E00646 0 +OP4 E00647 0 +OP4 E00648 0 +OP4 E00649 0 +OP4 E0064A 0 +OP4 E0064B 0 +OP4 E0064C 0 +OP4 E0064D 0 +OP4 E0064E 0 +OP4 E0064F 0 +OP4 E00650 0 +OP4 E00651 0 +OP4 E00652 0 +OP4 E00653 0 +OP4 E00654 0 +OP4 E00655 0 +OP4 E00656 0 +OP4 E00657 0 +OP4 E00658 0 +OP4 E00659 0 +OP4 E0065A 0 +OP4 E0065B 0 +OP4 E0065C 0 +OP4 E0065D 0 +OP4 E0065E 0 +OP4 E0065F 0 +OP4 E00660 0 +OP4 E00661 0 +OP4 E00662 0 +OP4 E00663 0 +OP4 E00664 0 +OP4 E00665 0 +OP4 E00666 0 +OP4 E00667 0 +OP4 E00668 0 +OP4 E00669 0 +OP4 E0066A 0 +OP4 E0066B 0 +OP4 E0066C 0 +OP4 E0066D 0 +OP4 E0066E 0 +OP4 E0066F 0 +OP4 E00670 0 +OP4 E00671 0 +OP4 E00672 0 +OP4 E00673 0 +OP4 E00674 0 +OP4 E00675 0 +OP4 E00676 0 +OP4 E00677 0 +OP4 E00678 0 +OP4 E00679 0 +OP4 E0067A 0 +OP4 E0067B 0 +OP4 E0067C 0 +OP4 E0067D 0 +OP4 E0067E 0 +OP4 E0067F 0 +OP4 E00680 0 +OP4 E00681 0 +OP4 E00682 0 +OP4 E00683 0 +OP4 E00684 0 +OP4 E00685 0 +OP4 E00686 0 +OP4 E00687 0 +OP4 E00688 0 +OP4 E00689 0 +OP4 E0068A 0 +OP4 E0068B 0 +OP4 E0068C 0 +OP4 E0068D 0 +OP4 E0068E 0 +OP4 E0068F 0 +OP4 E00690 0 +OP4 E00691 0 +OP4 E00692 0 +OP4 E00693 0 +OP4 E00694 0 +OP4 E00695 0 +OP4 E00696 0 +OP4 E00697 0 +OP4 E00698 0 +OP4 E00699 0 +OP4 E0069A 0 +OP4 E0069B 0 +OP4 E0069C 0 +OP4 E0069D 0 +OP4 E0069E 0 +OP4 E0069F 0 +OP4 E006A0 0 +OP4 E006A1 0 +OP4 E006A2 0 +OP4 E006A3 0 +OP4 E006A4 0 +OP4 E006A5 0 +OP4 E006A6 0 +OP4 E006A7 0 +OP4 E006A8 0 +OP4 E006A9 0 +OP4 E006AA 0 +OP4 E006AB 0 +OP4 E006AC 0 +OP4 E006AD 0 +OP4 E006AE 0 +OP4 E006AF 0 +OP4 E006B0 0 +OP4 E006B1 0 +OP4 E006B2 0 +OP4 E006B3 0 +OP4 E006B4 0 +OP4 E006B5 0 +OP4 E006B6 0 +OP4 E006B7 0 +OP4 E006B8 0 +OP4 E006B9 0 +OP4 E006BA 0 +OP4 E006BB 0 +OP4 E006BC 0 +OP4 E006BD 0 +OP4 E006BE 0 +OP4 E006BF 0 +OP4 E006C0 0 +OP4 E006C1 0 +OP4 E006C2 0 +OP4 E006C3 0 +OP4 E006C4 0 +OP4 E006C5 0 +OP4 E006C6 0 +OP4 E006C7 0 +OP4 E006C8 0 +OP4 E006C9 0 +OP4 E006CA 0 +OP4 E006CB 0 +OP4 E006CC 0 +OP4 E006CD 0 +OP4 E006CE 0 +OP4 E006CF 0 +OP4 E006D0 0 +OP4 E006D1 0 +OP4 E006D2 0 +OP4 E006D3 0 +OP4 E006D4 0 +OP4 E006D5 0 +OP4 E006D6 0 +OP4 E006D7 0 +OP4 E006D8 0 +OP4 E006D9 0 +OP4 E006DA 0 +OP4 E006DB 0 +OP4 E006DC 0 +OP4 E006DD 0 +OP4 E006DE 0 +OP4 E006DF 0 +OP4 E006E0 0 +OP4 E006E1 0 +OP4 E006E2 0 +OP4 E006E3 0 +OP4 E006E4 0 +OP4 E006E5 0 +OP4 E006E6 0 +OP4 E006E7 0 +OP4 E006E8 0 +OP4 E006E9 0 +OP4 E006EA 0 +OP4 E006EB 0 +OP4 E006EC 0 +OP4 E006ED 0 +OP4 E006EE 0 +OP4 E006EF 0 +OP4 E006F0 0 +OP4 E006F1 0 +OP4 E006F2 0 +OP4 E006F3 0 +OP4 E006F4 0 +OP4 E006F5 0 +OP4 E006F6 0 +OP4 E006F7 0 +OP4 E006F8 0 +OP4 E006F9 0 +OP4 E006FA 0 +OP4 E006FB 0 +OP4 E006FC 0 +OP4 E006FD 0 +OP4 E006FE 0 +OP4 E006FF 0 +OP4 E00700 0 +OP4 E00701 0 +OP4 E00702 0 +OP4 E00703 0 +OP4 E00704 0 +OP4 E00705 0 +OP4 E00706 0 +OP4 E00707 0 +OP4 E00708 0 +OP4 E00709 0 +OP4 E0070A 0 +OP4 E0070B 0 +OP4 E0070C 0 +OP4 E0070D 0 +OP4 E0070E 0 +OP4 E0070F 0 +OP4 E00710 0 +OP4 E00711 0 +OP4 E00712 0 +OP4 E00713 0 +OP4 E00714 0 +OP4 E00715 0 +OP4 E00716 0 +OP4 E00717 0 +OP4 E00718 0 +OP4 E00719 0 +OP4 E0071A 0 +OP4 E0071B 0 +OP4 E0071C 0 +OP4 E0071D 0 +OP4 E0071E 0 +OP4 E0071F 0 +OP4 E00720 0 +OP4 E00721 0 +OP4 E00722 0 +OP4 E00723 0 +OP4 E00724 0 +OP4 E00725 0 +OP4 E00726 0 +OP4 E00727 0 +OP4 E00728 0 +OP4 E00729 0 +OP4 E0072A 0 +OP4 E0072B 0 +OP4 E0072C 0 +OP4 E0072D 0 +OP4 E0072E 0 +OP4 E0072F 0 +OP4 E00730 0 +OP4 E00731 0 +OP4 E00732 0 +OP4 E00733 0 +OP4 E00734 0 +OP4 E00735 0 +OP4 E00736 0 +OP4 E00737 0 +OP4 E00738 0 +OP4 E00739 0 +OP4 E0073A 0 +OP4 E0073B 0 +OP4 E0073C 0 +OP4 E0073D 0 +OP4 E0073E 0 +OP4 E0073F 0 +OP4 E00740 0 +OP4 E00741 0 +OP4 E00742 0 +OP4 E00743 0 +OP4 E00744 0 +OP4 E00745 0 +OP4 E00746 0 +OP4 E00747 0 +OP4 E00748 0 +OP4 E00749 0 +OP4 E0074A 0 +OP4 E0074B 0 +OP4 E0074C 0 +OP4 E0074D 0 +OP4 E0074E 0 +OP4 E0074F 0 +OP4 E00750 0 +OP4 E00751 0 +OP4 E00752 0 +OP4 E00753 0 +OP4 E00754 0 +OP4 E00755 0 +OP4 E00756 0 +OP4 E00757 0 +OP4 E00758 0 +OP4 E00759 0 +OP4 E0075A 0 +OP4 E0075B 0 +OP4 E0075C 0 +OP4 E0075D 0 +OP4 E0075E 0 +OP4 E0075F 0 +OP4 E00760 0 +OP4 E00761 0 +OP4 E00762 0 +OP4 E00763 0 +OP4 E00764 0 +OP4 E00765 0 +OP4 E00766 0 +OP4 E00767 0 +OP4 E00768 0 +OP4 E00769 0 +OP4 E0076A 0 +OP4 E0076B 0 +OP4 E0076C 0 +OP4 E0076D 0 +OP4 E0076E 0 +OP4 E0076F 0 +OP4 E00770 0 +OP4 E00771 0 +OP4 E00772 0 +OP4 E00773 0 +OP4 E00774 0 +OP4 E00775 0 +OP4 E00776 0 +OP4 E00777 0 +OP4 E00778 0 +OP4 E00779 0 +OP4 E0077A 0 +OP4 E0077B 0 +OP4 E0077C 0 +OP4 E0077D 0 +OP4 E0077E 0 +OP4 E0077F 0 +OP4 E00780 0 +OP4 E00781 0 +OP4 E00782 0 +OP4 E00783 0 +OP4 E00784 0 +OP4 E00785 0 +OP4 E00786 0 +OP4 E00787 0 +OP4 E00788 0 +OP4 E00789 0 +OP4 E0078A 0 +OP4 E0078B 0 +OP4 E0078C 0 +OP4 E0078D 0 +OP4 E0078E 0 +OP4 E0078F 0 +OP4 E00790 0 +OP4 E00791 0 +OP4 E00792 0 +OP4 E00793 0 +OP4 E00794 0 +OP4 E00795 0 +OP4 E00796 0 +OP4 E00797 0 +OP4 E00798 0 +OP4 E00799 0 +OP4 E0079A 0 +OP4 E0079B 0 +OP4 E0079C 0 +OP4 E0079D 0 +OP4 E0079E 0 +OP4 E0079F 0 +OP4 E007A0 0 +OP4 E007A1 0 +OP4 E007A2 0 +OP4 E007A3 0 +OP4 E007A4 0 +OP4 E007A5 0 +OP4 E007A6 0 +OP4 E007A7 0 +OP4 E007A8 0 +OP4 E007A9 0 +OP4 E007AA 0 +OP4 E007AB 0 +OP4 E007AC 0 +OP4 E007AD 0 +OP4 E007AE 0 +OP4 E007AF 0 +OP4 E007B0 0 +OP4 E007B1 0 +OP4 E007B2 0 +OP4 E007B3 0 +OP4 E007B4 0 +OP4 E007B5 0 +OP4 E007B6 0 +OP4 E007B7 0 +OP4 E007B8 0 +OP4 E007B9 0 +OP4 E007BA 0 +OP4 E007BB 0 +OP4 E007BC 0 +OP4 E007BD 0 +OP4 E007BE 0 +OP4 E007BF 0 +OP4 E007C0 0 +OP4 E007C1 0 +OP4 E007C2 0 +OP4 E007C3 0 +OP4 E007C4 0 +OP4 E007C5 0 +OP4 E007C6 0 +OP4 E007C7 0 +OP4 E007C8 0 +OP4 E007C9 0 +OP4 E007CA 0 +OP4 E007CB 0 +OP4 E007CC 0 +OP4 E007CD 0 +OP4 E007CE 0 +OP4 E007CF 0 +OP4 E007D0 0 +OP4 E007D1 0 +OP4 E007D2 0 +OP4 E007D3 0 +OP4 E007D4 0 +OP4 E007D5 0 +OP4 E007D6 0 +OP4 E007D7 0 +OP4 E007D8 0 +OP4 E007D9 0 +OP4 E007DA 0 +OP4 E007DB 0 +OP4 E007DC 0 +OP4 E007DD 0 +OP4 E007DE 0 +OP4 E007DF 0 +OP4 E007E0 0 +OP4 E007E1 0 +OP4 E007E2 0 +OP4 E007E3 0 +OP4 E007E4 0 +OP4 E007E5 0 +OP4 E007E6 0 +OP4 E007E7 0 +OP4 E007E8 0 +OP4 E007E9 0 +OP4 E007EA 0 +OP4 E007EB 0 +OP4 E007EC 0 +OP4 E007ED 0 +OP4 E007EE 0 +OP4 E007EF 0 +OP4 E007F0 0 +OP4 E007F1 0 +OP4 E007F2 0 +OP4 E007F3 0 +OP4 E007F4 0 +OP4 E007F5 0 +OP4 E007F6 0 +OP4 E007F7 0 +OP4 E007F8 0 +OP4 E007F9 0 +OP4 E007FA 0 +OP4 E007FB 0 +OP4 E007FC 0 +OP4 E007FD 0 +OP4 E007FE 0 +OP4 E007FF 0 +OP4 E00800 0 +OP4 E00801 0 +OP4 E00802 0 +OP4 E00803 0 +OP4 E00804 0 +OP4 E00805 0 +OP4 E00806 0 +OP4 E00807 0 +OP4 E00808 0 +OP4 E00809 0 +OP4 E0080A 0 +OP4 E0080B 0 +OP4 E0080C 0 +OP4 E0080D 0 +OP4 E0080E 0 +OP4 E0080F 0 +OP4 E00810 0 +OP4 E00811 0 +OP4 E00812 0 +OP4 E00813 0 +OP4 E00814 0 +OP4 E00815 0 +OP4 E00816 0 +OP4 E00817 0 +OP4 E00818 0 +OP4 E00819 0 +OP4 E0081A 0 +OP4 E0081B 0 +OP4 E0081C 0 +OP4 E0081D 0 +OP4 E0081E 0 +OP4 E0081F 0 +OP4 E00820 0 +OP4 E00821 0 +OP4 E00822 0 +OP4 E00823 0 +OP4 E00824 0 +OP4 E00825 0 +OP4 E00826 0 +OP4 E00827 0 +OP4 E00828 0 +OP4 E00829 0 +OP4 E0082A 0 +OP4 E0082B 0 +OP4 E0082C 0 +OP4 E0082D 0 +OP4 E0082E 0 +OP4 E0082F 0 +OP4 E00830 0 +OP4 E00831 0 +OP4 E00832 0 +OP4 E00833 0 +OP4 E00834 0 +OP4 E00835 0 +OP4 E00836 0 +OP4 E00837 0 +OP4 E00838 0 +OP4 E00839 0 +OP4 E0083A 0 +OP4 E0083B 0 +OP4 E0083C 0 +OP4 E0083D 0 +OP4 E0083E 0 +OP4 E0083F 0 +OP4 E00840 0 +OP4 E00841 0 +OP4 E00842 0 +OP4 E00843 0 +OP4 E00844 0 +OP4 E00845 0 +OP4 E00846 0 +OP4 E00847 0 +OP4 E00848 0 +OP4 E00849 0 +OP4 E0084A 0 +OP4 E0084B 0 +OP4 E0084C 0 +OP4 E0084D 0 +OP4 E0084E 0 +OP4 E0084F 0 +OP4 E00850 0 +OP4 E00851 0 +OP4 E00852 0 +OP4 E00853 0 +OP4 E00854 0 +OP4 E00855 0 +OP4 E00856 0 +OP4 E00857 0 +OP4 E00858 0 +OP4 E00859 0 +OP4 E0085A 0 +OP4 E0085B 0 +OP4 E0085C 0 +OP4 E0085D 0 +OP4 E0085E 0 +OP4 E0085F 0 +OP4 E00860 0 +OP4 E00861 0 +OP4 E00862 0 +OP4 E00863 0 +OP4 E00864 0 +OP4 E00865 0 +OP4 E00866 0 +OP4 E00867 0 +OP4 E00868 0 +OP4 E00869 0 +OP4 E0086A 0 +OP4 E0086B 0 +OP4 E0086C 0 +OP4 E0086D 0 +OP4 E0086E 0 +OP4 E0086F 0 +OP4 E00870 0 +OP4 E00871 0 +OP4 E00872 0 +OP4 E00873 0 +OP4 E00874 0 +OP4 E00875 0 +OP4 E00876 0 +OP4 E00877 0 +OP4 E00878 0 +OP4 E00879 0 +OP4 E0087A 0 +OP4 E0087B 0 +OP4 E0087C 0 +OP4 E0087D 0 +OP4 E0087E 0 +OP4 E0087F 0 +OP4 E00880 0 +OP4 E00881 0 +OP4 E00882 0 +OP4 E00883 0 +OP4 E00884 0 +OP4 E00885 0 +OP4 E00886 0 +OP4 E00887 0 +OP4 E00888 0 +OP4 E00889 0 +OP4 E0088A 0 +OP4 E0088B 0 +OP4 E0088C 0 +OP4 E0088D 0 +OP4 E0088E 0 +OP4 E0088F 0 +OP4 E00890 0 +OP4 E00891 0 +OP4 E00892 0 +OP4 E00893 0 +OP4 E00894 0 +OP4 E00895 0 +OP4 E00896 0 +OP4 E00897 0 +OP4 E00898 0 +OP4 E00899 0 +OP4 E0089A 0 +OP4 E0089B 0 +OP4 E0089C 0 +OP4 E0089D 0 +OP4 E0089E 0 +OP4 E0089F 0 +OP4 E008A0 0 +OP4 E008A1 0 +OP4 E008A2 0 +OP4 E008A3 0 +OP4 E008A4 0 +OP4 E008A5 0 +OP4 E008A6 0 +OP4 E008A7 0 +OP4 E008A8 0 +OP4 E008A9 0 +OP4 E008AA 0 +OP4 E008AB 0 +OP4 E008AC 0 +OP4 E008AD 0 +OP4 E008AE 0 +OP4 E008AF 0 +OP4 E008B0 0 +OP4 E008B1 0 +OP4 E008B2 0 +OP4 E008B3 0 +OP4 E008B4 0 +OP4 E008B5 0 +OP4 E008B6 0 +OP4 E008B7 0 +OP4 E008B8 0 +OP4 E008B9 0 +OP4 E008BA 0 +OP4 E008BB 0 +OP4 E008BC 0 +OP4 E008BD 0 +OP4 E008BE 0 +OP4 E008BF 0 +OP4 E008C0 0 +OP4 E008C1 0 +OP4 E008C2 0 +OP4 E008C3 0 +OP4 E008C4 0 +OP4 E008C5 0 +OP4 E008C6 0 +OP4 E008C7 0 +OP4 E008C8 0 +OP4 E008C9 0 +OP4 E008CA 0 +OP4 E008CB 0 +OP4 E008CC 0 +OP4 E008CD 0 +OP4 E008CE 0 +OP4 E008CF 0 +OP4 E008D0 0 +OP4 E008D1 0 +OP4 E008D2 0 +OP4 E008D3 0 +OP4 E008D4 0 +OP4 E008D5 0 +OP4 E008D6 0 +OP4 E008D7 0 +OP4 E008D8 0 +OP4 E008D9 0 +OP4 E008DA 0 +OP4 E008DB 0 +OP4 E008DC 0 +OP4 E008DD 0 +OP4 E008DE 0 +OP4 E008DF 0 +OP4 E008E0 0 +OP4 E008E1 0 +OP4 E008E2 0 +OP4 E008E3 0 +OP4 E008E4 0 +OP4 E008E5 0 +OP4 E008E6 0 +OP4 E008E7 0 +OP4 E008E8 0 +OP4 E008E9 0 +OP4 E008EA 0 +OP4 E008EB 0 +OP4 E008EC 0 +OP4 E008ED 0 +OP4 E008EE 0 +OP4 E008EF 0 +OP4 E008F0 0 +OP4 E008F1 0 +OP4 E008F2 0 +OP4 E008F3 0 +OP4 E008F4 0 +OP4 E008F5 0 +OP4 E008F6 0 +OP4 E008F7 0 +OP4 E008F8 0 +OP4 E008F9 0 +OP4 E008FA 0 +OP4 E008FB 0 +OP4 E008FC 0 +OP4 E008FD 0 +OP4 E008FE 0 +OP4 E008FF 0 +OP4 E00900 0 +OP4 E00901 0 +OP4 E00902 0 +OP4 E00903 0 +OP4 E00904 0 +OP4 E00905 0 +OP4 E00906 0 +OP4 E00907 0 +OP4 E00908 0 +OP4 E00909 0 +OP4 E0090A 0 +OP4 E0090B 0 +OP4 E0090C 0 +OP4 E0090D 0 +OP4 E0090E 0 +OP4 E0090F 0 +OP4 E00910 0 +OP4 E00911 0 +OP4 E00912 0 +OP4 E00913 0 +OP4 E00914 0 +OP4 E00915 0 +OP4 E00916 0 +OP4 E00917 0 +OP4 E00918 0 +OP4 E00919 0 +OP4 E0091A 0 +OP4 E0091B 0 +OP4 E0091C 0 +OP4 E0091D 0 +OP4 E0091E 0 +OP4 E0091F 0 +OP4 E00920 0 +OP4 E00921 0 +OP4 E00922 0 +OP4 E00923 0 +OP4 E00924 0 +OP4 E00925 0 +OP4 E00926 0 +OP4 E00927 0 +OP4 E00928 0 +OP4 E00929 0 +OP4 E0092A 0 +OP4 E0092B 0 +OP4 E0092C 0 +OP4 E0092D 0 +OP4 E0092E 0 +OP4 E0092F 0 +OP4 E00930 0 +OP4 E00931 0 +OP4 E00932 0 +OP4 E00933 0 +OP4 E00934 0 +OP4 E00935 0 +OP4 E00936 0 +OP4 E00937 0 +OP4 E00938 0 +OP4 E00939 0 +OP4 E0093A 0 +OP4 E0093B 0 +OP4 E0093C 0 +OP4 E0093D 0 +OP4 E0093E 0 +OP4 E0093F 0 +OP4 E00940 0 +OP4 E00941 0 +OP4 E00942 0 +OP4 E00943 0 +OP4 E00944 0 +OP4 E00945 0 +OP4 E00946 0 +OP4 E00947 0 +OP4 E00948 0 +OP4 E00949 0 +OP4 E0094A 0 +OP4 E0094B 0 +OP4 E0094C 0 +OP4 E0094D 0 +OP4 E0094E 0 +OP4 E0094F 0 +OP4 E00950 0 +OP4 E00951 0 +OP4 E00952 0 +OP4 E00953 0 +OP4 E00954 0 +OP4 E00955 0 +OP4 E00956 0 +OP4 E00957 0 +OP4 E00958 0 +OP4 E00959 0 +OP4 E0095A 0 +OP4 E0095B 0 +OP4 E0095C 0 +OP4 E0095D 0 +OP4 E0095E 0 +OP4 E0095F 0 +OP4 E00960 0 +OP4 E00961 0 +OP4 E00962 0 +OP4 E00963 0 +OP4 E00964 0 +OP4 E00965 0 +OP4 E00966 0 +OP4 E00967 0 +OP4 E00968 0 +OP4 E00969 0 +OP4 E0096A 0 +OP4 E0096B 0 +OP4 E0096C 0 +OP4 E0096D 0 +OP4 E0096E 0 +OP4 E0096F 0 +OP4 E00970 0 +OP4 E00971 0 +OP4 E00972 0 +OP4 E00973 0 +OP4 E00974 0 +OP4 E00975 0 +OP4 E00976 0 +OP4 E00977 0 +OP4 E00978 0 +OP4 E00979 0 +OP4 E0097A 0 +OP4 E0097B 0 +OP4 E0097C 0 +OP4 E0097D 0 +OP4 E0097E 0 +OP4 E0097F 0 +OP4 E00980 0 +OP4 E00981 0 +OP4 E00982 0 +OP4 E00983 0 +OP4 E00984 0 +OP4 E00985 0 +OP4 E00986 0 +OP4 E00987 0 +OP4 E00988 0 +OP4 E00989 0 +OP4 E0098A 0 +OP4 E0098B 0 +OP4 E0098C 0 +OP4 E0098D 0 +OP4 E0098E 0 +OP4 E0098F 0 +OP4 E00990 0 +OP4 E00991 0 +OP4 E00992 0 +OP4 E00993 0 +OP4 E00994 0 +OP4 E00995 0 +OP4 E00996 0 +OP4 E00997 0 +OP4 E00998 0 +OP4 E00999 0 +OP4 E0099A 0 +OP4 E0099B 0 +OP4 E0099C 0 +OP4 E0099D 0 +OP4 E0099E 0 +OP4 E0099F 0 +OP4 E009A0 0 +OP4 E009A1 0 +OP4 E009A2 0 +OP4 E009A3 0 +OP4 E009A4 0 +OP4 E009A5 0 +OP4 E009A6 0 +OP4 E009A7 0 +OP4 E009A8 0 +OP4 E009A9 0 +OP4 E009AA 0 +OP4 E009AB 0 +OP4 E009AC 0 +OP4 E009AD 0 +OP4 E009AE 0 +OP4 E009AF 0 +OP4 E009B0 0 +OP4 E009B1 0 +OP4 E009B2 0 +OP4 E009B3 0 +OP4 E009B4 0 +OP4 E009B5 0 +OP4 E009B6 0 +OP4 E009B7 0 +OP4 E009B8 0 +OP4 E009B9 0 +OP4 E009BA 0 +OP4 E009BB 0 +OP4 E009BC 0 +OP4 E009BD 0 +OP4 E009BE 0 +OP4 E009BF 0 +OP4 E009C0 0 +OP4 E009C1 0 +OP4 E009C2 0 +OP4 E009C3 0 +OP4 E009C4 0 +OP4 E009C5 0 +OP4 E009C6 0 +OP4 E009C7 0 +OP4 E009C8 0 +OP4 E009C9 0 +OP4 E009CA 0 +OP4 E009CB 0 +OP4 E009CC 0 +OP4 E009CD 0 +OP4 E009CE 0 +OP4 E009CF 0 +OP4 E009D0 0 +OP4 E009D1 0 +OP4 E009D2 0 +OP4 E009D3 0 +OP4 E009D4 0 +OP4 E009D5 0 +OP4 E009D6 0 +OP4 E009D7 0 +OP4 E009D8 0 +OP4 E009D9 0 +OP4 E009DA 0 +OP4 E009DB 0 +OP4 E009DC 0 +OP4 E009DD 0 +OP4 E009DE 0 +OP4 E009DF 0 +OP4 E009E0 0 +OP4 E009E1 0 +OP4 E009E2 0 +OP4 E009E3 0 +OP4 E009E4 0 +OP4 E009E5 0 +OP4 E009E6 0 +OP4 E009E7 0 +OP4 E009E8 0 +OP4 E009E9 0 +OP4 E009EA 0 +OP4 E009EB 0 +OP4 E009EC 0 +OP4 E009ED 0 +OP4 E009EE 0 +OP4 E009EF 0 +OP4 E009F0 0 +OP4 E009F1 0 +OP4 E009F2 0 +OP4 E009F3 0 +OP4 E009F4 0 +OP4 E009F5 0 +OP4 E009F6 0 +OP4 E009F7 0 +OP4 E009F8 0 +OP4 E009F9 0 +OP4 E009FA 0 +OP4 E009FB 0 +OP4 E009FC 0 +OP4 E009FD 0 +OP4 E009FE 0 +OP4 E009FF 0 +OP4 E00A00 0 +OP4 E00A01 0 +OP4 E00A02 0 +OP4 E00A03 0 +OP4 E00A04 0 +OP4 E00A05 0 +OP4 E00A06 0 +OP4 E00A07 0 +OP4 E00A08 0 diff --git a/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum2_itrace_irisc0.cfg.ext b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum2_itrace_irisc0.cfg.ext new file mode 100644 index 000000000000..24f8a91a7276 --- /dev/null +++ b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum2_itrace_irisc0.cfg.ext @@ -0,0 +1,2570 @@ +OP1 Spectrum2 +OP4 ITRACE0 1 +OP4 ITRACE1 0 +OP4 ITRACE2 0 +OP4 ITRACE3 0 +OP4 ITRACE4 0 +OP4 ITRACE5 0 +OP4 ITRACE6 0 +OP4 ITRACE7 0 +OP4 Main_PhyUC 0 +OP4 E00009 0 +OP4 E0000A 0 +OP4 E0000B 0 +OP4 E0000C 0 +OP4 E0000D 0 +OP4 E0000E 0 +OP4 E0000F 0 +OP4 E00010 0 +OP4 E00011 0 +OP4 E00012 0 +OP4 E00013 0 +OP4 E00014 0 +OP4 E00015 0 +OP4 E00016 0 +OP4 E00017 0 +OP4 E00018 0 +OP4 E00019 0 +OP4 E0001A 0 +OP4 E0001B 0 +OP4 E0001C 0 +OP4 E0001D 0 +OP4 E0001E 0 +OP4 E0001F 0 +OP4 E00020 0 +OP4 E00021 0 +OP4 E00022 0 +OP4 E00023 0 +OP4 E00024 0 +OP4 E00025 0 +OP4 E00026 0 +OP4 E00027 0 +OP4 E00028 0 +OP4 E00029 0 +OP4 E0002A 0 +OP4 E0002B 0 +OP4 E0002C 0 +OP4 E0002D 0 +OP4 E0002E 0 +OP4 E0002F 0 +OP4 E00030 0 +OP4 E00031 0 +OP4 E00032 0 +OP4 E00033 0 +OP4 E00034 0 +OP4 E00035 0 +OP4 E00036 0 +OP4 E00037 0 +OP4 E00038 0 +OP4 E00039 0 +OP4 E0003A 0 +OP4 E0003B 0 +OP4 E0003C 0 +OP4 E0003D 0 +OP4 E0003E 0 +OP4 E0003F 0 +OP4 E00040 0 +OP4 E00041 0 +OP4 E00042 0 +OP4 E00043 0 +OP4 E00044 0 +OP4 E00045 0 +OP4 E00046 0 +OP4 E00047 0 +OP4 E00048 0 +OP4 E00049 0 +OP4 E0004A 0 +OP4 E0004B 0 +OP4 E0004C 0 +OP4 E0004D 0 +OP4 E0004E 0 +OP4 E0004F 0 +OP4 E00050 0 +OP4 E00051 0 +OP4 E00052 0 +OP4 E00053 0 +OP4 E00054 0 +OP4 E00055 0 +OP4 E00056 0 +OP4 E00057 0 +OP4 E00058 0 +OP4 E00059 0 +OP4 E0005A 0 +OP4 E0005B 0 +OP4 E0005C 0 +OP4 E0005D 0 +OP4 E0005E 0 +OP4 E0005F 0 +OP4 E00060 0 +OP4 E00061 0 +OP4 E00062 0 +OP4 E00063 0 +OP4 E00064 0 +OP4 E00065 0 +OP4 E00066 0 +OP4 E00067 0 +OP4 E00068 0 +OP4 E00069 0 +OP4 E0006A 0 +OP4 E0006B 0 +OP4 E0006C 0 +OP4 E0006D 0 +OP4 E0006E 0 +OP4 E0006F 0 +OP4 E00070 0 +OP4 E00071 0 +OP4 E00072 0 +OP4 E00073 0 +OP4 E00074 0 +OP4 E00075 0 +OP4 E00076 0 +OP4 E00077 0 +OP4 E00078 0 +OP4 E00079 0 +OP4 E0007A 0 +OP4 E0007B 0 +OP4 E0007C 0 +OP4 E0007D 0 +OP4 E0007E 0 +OP4 E0007F 0 +OP4 E00080 0 +OP4 E00081 0 +OP4 E00082 0 +OP4 E00083 0 +OP4 E00084 0 +OP4 E00085 0 +OP4 E00086 0 +OP4 E00087 0 +OP4 E00088 0 +OP4 E00089 0 +OP4 E0008A 0 +OP4 E0008B 0 +OP4 E0008C 0 +OP4 E0008D 0 +OP4 E0008E 0 +OP4 E0008F 0 +OP4 E00090 0 +OP4 E00091 0 +OP4 E00092 0 +OP4 E00093 0 +OP4 E00094 0 +OP4 E00095 0 +OP4 E00096 0 +OP4 E00097 0 +OP4 E00098 0 +OP4 E00099 0 +OP4 E0009A 0 +OP4 E0009B 0 +OP4 E0009C 0 +OP4 E0009D 0 +OP4 E0009E 0 +OP4 E0009F 0 +OP4 E000A0 0 +OP4 E000A1 0 +OP4 E000A2 0 +OP4 E000A3 0 +OP4 E000A4 0 +OP4 E000A5 0 +OP4 E000A6 0 +OP4 E000A7 0 +OP4 E000A8 0 +OP4 E000A9 0 +OP4 E000AA 0 +OP4 E000AB 0 +OP4 E000AC 0 +OP4 E000AD 0 +OP4 E000AE 0 +OP4 E000AF 0 +OP4 E000B0 0 +OP4 E000B1 0 +OP4 E000B2 0 +OP4 E000B3 0 +OP4 E000B4 0 +OP4 E000B5 0 +OP4 E000B6 0 +OP4 E000B7 0 +OP4 E000B8 0 +OP4 E000B9 0 +OP4 E000BA 0 +OP4 E000BB 0 +OP4 E000BC 0 +OP4 E000BD 0 +OP4 E000BE 0 +OP4 E000BF 0 +OP4 E000C0 0 +OP4 E000C1 0 +OP4 E000C2 0 +OP4 E000C3 0 +OP4 E000C4 0 +OP4 E000C5 0 +OP4 E000C6 0 +OP4 E000C7 0 +OP4 E000C8 0 +OP4 E000C9 0 +OP4 E000CA 0 +OP4 E000CB 0 +OP4 E000CC 0 +OP4 E000CD 0 +OP4 E000CE 0 +OP4 E000CF 0 +OP4 E000D0 0 +OP4 E000D1 0 +OP4 E000D2 0 +OP4 E000D3 0 +OP4 E000D4 0 +OP4 E000D5 0 +OP4 E000D6 0 +OP4 E000D7 0 +OP4 E000D8 0 +OP4 E000D9 0 +OP4 E000DA 0 +OP4 E000DB 0 +OP4 E000DC 0 +OP4 E000DD 0 +OP4 E000DE 0 +OP4 E000DF 0 +OP4 E000E0 0 +OP4 E000E1 0 +OP4 E000E2 0 +OP4 E000E3 0 +OP4 E000E4 0 +OP4 E000E5 0 +OP4 E000E6 0 +OP4 E000E7 0 +OP4 E000E8 0 +OP4 E000E9 0 +OP4 E000EA 0 +OP4 E000EB 0 +OP4 E000EC 0 +OP4 E000ED 0 +OP4 E000EE 0 +OP4 E000EF 0 +OP4 E000F0 0 +OP4 E000F1 0 +OP4 E000F2 0 +OP4 E000F3 0 +OP4 E000F4 0 +OP4 E000F5 0 +OP4 E000F6 0 +OP4 E000F7 0 +OP4 E000F8 0 +OP4 E000F9 0 +OP4 E000FA 0 +OP4 E000FB 0 +OP4 E000FC 0 +OP4 E000FD 0 +OP4 E000FE 0 +OP4 E000FF 0 +OP4 E00100 0 +OP4 E00101 0 +OP4 E00102 0 +OP4 E00103 0 +OP4 E00104 0 +OP4 E00105 0 +OP4 E00106 0 +OP4 E00107 0 +OP4 E00108 0 +OP4 E00109 0 +OP4 E0010A 0 +OP4 E0010B 0 +OP4 E0010C 0 +OP4 E0010D 0 +OP4 E0010E 0 +OP4 E0010F 0 +OP4 E00110 0 +OP4 E00111 0 +OP4 E00112 0 +OP4 E00113 0 +OP4 E00114 0 +OP4 E00115 0 +OP4 E00116 0 +OP4 E00117 0 +OP4 E00118 0 +OP4 E00119 0 +OP4 E0011A 0 +OP4 E0011B 0 +OP4 E0011C 0 +OP4 E0011D 0 +OP4 E0011E 0 +OP4 E0011F 0 +OP4 E00120 0 +OP4 E00121 0 +OP4 E00122 0 +OP4 E00123 0 +OP4 E00124 0 +OP4 E00125 0 +OP4 E00126 0 +OP4 E00127 0 +OP4 E00128 0 +OP4 E00129 0 +OP4 E0012A 0 +OP4 E0012B 0 +OP4 E0012C 0 +OP4 E0012D 0 +OP4 E0012E 0 +OP4 E0012F 0 +OP4 E00130 0 +OP4 E00131 0 +OP4 E00132 0 +OP4 E00133 0 +OP4 E00134 0 +OP4 E00135 0 +OP4 E00136 0 +OP4 E00137 0 +OP4 E00138 0 +OP4 E00139 0 +OP4 E0013A 0 +OP4 E0013B 0 +OP4 E0013C 0 +OP4 E0013D 0 +OP4 E0013E 0 +OP4 E0013F 0 +OP4 E00140 0 +OP4 E00141 0 +OP4 E00142 0 +OP4 E00143 0 +OP4 E00144 0 +OP4 E00145 0 +OP4 E00146 0 +OP4 E00147 0 +OP4 E00148 0 +OP4 E00149 0 +OP4 E0014A 0 +OP4 E0014B 0 +OP4 E0014C 0 +OP4 E0014D 0 +OP4 E0014E 0 +OP4 E0014F 0 +OP4 E00150 0 +OP4 E00151 0 +OP4 E00152 0 +OP4 E00153 0 +OP4 E00154 0 +OP4 E00155 0 +OP4 E00156 0 +OP4 E00157 0 +OP4 E00158 0 +OP4 E00159 0 +OP4 E0015A 0 +OP4 E0015B 0 +OP4 E0015C 0 +OP4 E0015D 0 +OP4 E0015E 0 +OP4 E0015F 0 +OP4 E00160 0 +OP4 E00161 0 +OP4 E00162 0 +OP4 E00163 0 +OP4 E00164 0 +OP4 E00165 0 +OP4 E00166 0 +OP4 E00167 0 +OP4 E00168 0 +OP4 E00169 0 +OP4 E0016A 0 +OP4 E0016B 0 +OP4 E0016C 0 +OP4 E0016D 0 +OP4 E0016E 0 +OP4 E0016F 0 +OP4 E00170 0 +OP4 E00171 0 +OP4 E00172 0 +OP4 E00173 0 +OP4 E00174 0 +OP4 E00175 0 +OP4 E00176 0 +OP4 E00177 0 +OP4 E00178 0 +OP4 E00179 0 +OP4 E0017A 0 +OP4 E0017B 0 +OP4 E0017C 0 +OP4 E0017D 0 +OP4 E0017E 0 +OP4 E0017F 0 +OP4 E00180 0 +OP4 E00181 0 +OP4 E00182 0 +OP4 E00183 0 +OP4 E00184 0 +OP4 E00185 0 +OP4 E00186 0 +OP4 E00187 0 +OP4 E00188 0 +OP4 E00189 0 +OP4 E0018A 0 +OP4 E0018B 0 +OP4 E0018C 0 +OP4 E0018D 0 +OP4 E0018E 0 +OP4 E0018F 0 +OP4 E00190 0 +OP4 E00191 0 +OP4 E00192 0 +OP4 E00193 0 +OP4 E00194 0 +OP4 E00195 0 +OP4 E00196 0 +OP4 E00197 0 +OP4 E00198 0 +OP4 E00199 0 +OP4 E0019A 0 +OP4 E0019B 0 +OP4 E0019C 0 +OP4 E0019D 0 +OP4 E0019E 0 +OP4 E0019F 0 +OP4 E001A0 0 +OP4 E001A1 0 +OP4 E001A2 0 +OP4 E001A3 0 +OP4 E001A4 0 +OP4 E001A5 0 +OP4 E001A6 0 +OP4 E001A7 0 +OP4 E001A8 0 +OP4 E001A9 0 +OP4 E001AA 0 +OP4 E001AB 0 +OP4 E001AC 0 +OP4 E001AD 0 +OP4 E001AE 0 +OP4 E001AF 0 +OP4 E001B0 0 +OP4 E001B1 0 +OP4 E001B2 0 +OP4 E001B3 0 +OP4 E001B4 0 +OP4 E001B5 0 +OP4 E001B6 0 +OP4 E001B7 0 +OP4 E001B8 0 +OP4 E001B9 0 +OP4 E001BA 0 +OP4 E001BB 0 +OP4 E001BC 0 +OP4 E001BD 0 +OP4 E001BE 0 +OP4 E001BF 0 +OP4 E001C0 0 +OP4 E001C1 0 +OP4 E001C2 0 +OP4 E001C3 0 +OP4 E001C4 0 +OP4 E001C5 0 +OP4 E001C6 0 +OP4 E001C7 0 +OP4 E001C8 0 +OP4 E001C9 0 +OP4 E001CA 0 +OP4 E001CB 0 +OP4 E001CC 0 +OP4 E001CD 0 +OP4 E001CE 0 +OP4 E001CF 0 +OP4 E001D0 0 +OP4 E001D1 0 +OP4 E001D2 0 +OP4 E001D3 0 +OP4 E001D4 0 +OP4 E001D5 0 +OP4 E001D6 0 +OP4 E001D7 0 +OP4 E001D8 0 +OP4 E001D9 0 +OP4 E001DA 0 +OP4 E001DB 0 +OP4 E001DC 0 +OP4 E001DD 0 +OP4 E001DE 0 +OP4 E001DF 0 +OP4 E001E0 0 +OP4 E001E1 0 +OP4 E001E2 0 +OP4 E001E3 0 +OP4 E001E4 0 +OP4 E001E5 0 +OP4 E001E6 0 +OP4 E001E7 0 +OP4 E001E8 0 +OP4 E001E9 0 +OP4 E001EA 0 +OP4 E001EB 0 +OP4 E001EC 0 +OP4 E001ED 0 +OP4 E001EE 0 +OP4 E001EF 0 +OP4 E001F0 0 +OP4 E001F1 0 +OP4 E001F2 0 +OP4 E001F3 0 +OP4 E001F4 0 +OP4 E001F5 0 +OP4 E001F6 0 +OP4 E001F7 0 +OP4 E001F8 0 +OP4 E001F9 0 +OP4 E001FA 0 +OP4 E001FB 0 +OP4 E001FC 0 +OP4 E001FD 0 +OP4 E001FE 0 +OP4 E001FF 0 +OP4 E00200 0 +OP4 E00201 0 +OP4 E00202 0 +OP4 E00203 0 +OP4 E00204 0 +OP4 E00205 0 +OP4 E00206 0 +OP4 E00207 0 +OP4 E00208 0 +OP4 E00209 0 +OP4 E0020A 0 +OP4 E0020B 0 +OP4 E0020C 0 +OP4 E0020D 0 +OP4 E0020E 0 +OP4 E0020F 0 +OP4 E00210 0 +OP4 E00211 0 +OP4 E00212 0 +OP4 E00213 0 +OP4 E00214 0 +OP4 E00215 0 +OP4 E00216 0 +OP4 E00217 0 +OP4 E00218 0 +OP4 E00219 0 +OP4 E0021A 0 +OP4 E0021B 0 +OP4 E0021C 0 +OP4 E0021D 0 +OP4 E0021E 0 +OP4 E0021F 0 +OP4 E00220 0 +OP4 E00221 0 +OP4 E00222 0 +OP4 E00223 0 +OP4 E00224 0 +OP4 E00225 0 +OP4 E00226 0 +OP4 E00227 0 +OP4 E00228 0 +OP4 E00229 0 +OP4 E0022A 0 +OP4 E0022B 0 +OP4 E0022C 0 +OP4 E0022D 0 +OP4 E0022E 0 +OP4 E0022F 0 +OP4 E00230 0 +OP4 E00231 0 +OP4 E00232 0 +OP4 E00233 0 +OP4 E00234 0 +OP4 E00235 0 +OP4 E00236 0 +OP4 E00237 0 +OP4 E00238 0 +OP4 E00239 0 +OP4 E0023A 0 +OP4 E0023B 0 +OP4 E0023C 0 +OP4 E0023D 0 +OP4 E0023E 0 +OP4 E0023F 0 +OP4 E00240 0 +OP4 E00241 0 +OP4 E00242 0 +OP4 E00243 0 +OP4 E00244 0 +OP4 E00245 0 +OP4 E00246 0 +OP4 E00247 0 +OP4 E00248 0 +OP4 E00249 0 +OP4 E0024A 0 +OP4 E0024B 0 +OP4 E0024C 0 +OP4 E0024D 0 +OP4 E0024E 0 +OP4 E0024F 0 +OP4 E00250 0 +OP4 E00251 0 +OP4 E00252 0 +OP4 E00253 0 +OP4 E00254 0 +OP4 E00255 0 +OP4 E00256 0 +OP4 E00257 0 +OP4 E00258 0 +OP4 E00259 0 +OP4 E0025A 0 +OP4 E0025B 0 +OP4 E0025C 0 +OP4 E0025D 0 +OP4 E0025E 0 +OP4 E0025F 0 +OP4 E00260 0 +OP4 E00261 0 +OP4 E00262 0 +OP4 E00263 0 +OP4 E00264 0 +OP4 E00265 0 +OP4 E00266 0 +OP4 E00267 0 +OP4 E00268 0 +OP4 E00269 0 +OP4 E0026A 0 +OP4 E0026B 0 +OP4 E0026C 0 +OP4 E0026D 0 +OP4 E0026E 0 +OP4 E0026F 0 +OP4 E00270 0 +OP4 E00271 0 +OP4 E00272 0 +OP4 E00273 0 +OP4 E00274 0 +OP4 E00275 0 +OP4 E00276 0 +OP4 E00277 0 +OP4 E00278 0 +OP4 E00279 0 +OP4 E0027A 0 +OP4 E0027B 0 +OP4 E0027C 0 +OP4 E0027D 0 +OP4 E0027E 0 +OP4 E0027F 0 +OP4 E00280 0 +OP4 E00281 0 +OP4 E00282 0 +OP4 E00283 0 +OP4 E00284 0 +OP4 E00285 0 +OP4 E00286 0 +OP4 E00287 0 +OP4 E00288 0 +OP4 E00289 0 +OP4 E0028A 0 +OP4 E0028B 0 +OP4 E0028C 0 +OP4 E0028D 0 +OP4 E0028E 0 +OP4 E0028F 0 +OP4 E00290 0 +OP4 E00291 0 +OP4 E00292 0 +OP4 E00293 0 +OP4 E00294 0 +OP4 E00295 0 +OP4 E00296 0 +OP4 E00297 0 +OP4 E00298 0 +OP4 E00299 0 +OP4 E0029A 0 +OP4 E0029B 0 +OP4 E0029C 0 +OP4 E0029D 0 +OP4 E0029E 0 +OP4 E0029F 0 +OP4 E002A0 0 +OP4 E002A1 0 +OP4 E002A2 0 +OP4 E002A3 0 +OP4 E002A4 0 +OP4 E002A5 0 +OP4 E002A6 0 +OP4 E002A7 0 +OP4 E002A8 0 +OP4 E002A9 0 +OP4 E002AA 0 +OP4 E002AB 0 +OP4 E002AC 0 +OP4 E002AD 0 +OP4 E002AE 0 +OP4 E002AF 0 +OP4 E002B0 0 +OP4 E002B1 0 +OP4 E002B2 0 +OP4 E002B3 0 +OP4 E002B4 0 +OP4 E002B5 0 +OP4 E002B6 0 +OP4 E002B7 0 +OP4 E002B8 0 +OP4 E002B9 0 +OP4 E002BA 0 +OP4 E002BB 0 +OP4 E002BC 0 +OP4 E002BD 0 +OP4 E002BE 0 +OP4 E002BF 0 +OP4 E002C0 0 +OP4 E002C1 0 +OP4 E002C2 0 +OP4 E002C3 0 +OP4 E002C4 0 +OP4 E002C5 0 +OP4 E002C6 0 +OP4 E002C7 0 +OP4 E002C8 0 +OP4 E002C9 0 +OP4 E002CA 0 +OP4 E002CB 0 +OP4 E002CC 0 +OP4 E002CD 0 +OP4 E002CE 0 +OP4 E002CF 0 +OP4 E002D0 0 +OP4 E002D1 0 +OP4 E002D2 0 +OP4 E002D3 0 +OP4 E002D4 0 +OP4 E002D5 0 +OP4 E002D6 0 +OP4 E002D7 0 +OP4 E002D8 0 +OP4 E002D9 0 +OP4 E002DA 0 +OP4 E002DB 0 +OP4 E002DC 0 +OP4 E002DD 0 +OP4 E002DE 0 +OP4 E002DF 0 +OP4 E002E0 0 +OP4 E002E1 0 +OP4 E002E2 0 +OP4 E002E3 0 +OP4 E002E4 0 +OP4 E002E5 0 +OP4 E002E6 0 +OP4 E002E7 0 +OP4 E002E8 0 +OP4 E002E9 0 +OP4 E002EA 0 +OP4 E002EB 0 +OP4 E002EC 0 +OP4 E002ED 0 +OP4 E002EE 0 +OP4 E002EF 0 +OP4 E002F0 0 +OP4 E002F1 0 +OP4 E002F2 0 +OP4 E002F3 0 +OP4 E002F4 0 +OP4 E002F5 0 +OP4 E002F6 0 +OP4 E002F7 0 +OP4 E002F8 0 +OP4 E002F9 0 +OP4 E002FA 0 +OP4 E002FB 0 +OP4 E002FC 0 +OP4 E002FD 0 +OP4 E002FE 0 +OP4 E002FF 0 +OP4 E00300 0 +OP4 E00301 0 +OP4 E00302 0 +OP4 E00303 0 +OP4 E00304 0 +OP4 E00305 0 +OP4 E00306 0 +OP4 E00307 0 +OP4 E00308 0 +OP4 E00309 0 +OP4 E0030A 0 +OP4 E0030B 0 +OP4 E0030C 0 +OP4 E0030D 0 +OP4 E0030E 0 +OP4 E0030F 0 +OP4 E00310 0 +OP4 E00311 0 +OP4 E00312 0 +OP4 E00313 0 +OP4 E00314 0 +OP4 E00315 0 +OP4 E00316 0 +OP4 E00317 0 +OP4 E00318 0 +OP4 E00319 0 +OP4 E0031A 0 +OP4 E0031B 0 +OP4 E0031C 0 +OP4 E0031D 0 +OP4 E0031E 0 +OP4 E0031F 0 +OP4 E00320 0 +OP4 E00321 0 +OP4 E00322 0 +OP4 E00323 0 +OP4 E00324 0 +OP4 E00325 0 +OP4 E00326 0 +OP4 E00327 0 +OP4 E00328 0 +OP4 E00329 0 +OP4 E0032A 0 +OP4 E0032B 0 +OP4 E0032C 0 +OP4 E0032D 0 +OP4 E0032E 0 +OP4 E0032F 0 +OP4 E00330 0 +OP4 E00331 0 +OP4 E00332 0 +OP4 E00333 0 +OP4 E00334 0 +OP4 E00335 0 +OP4 E00336 0 +OP4 E00337 0 +OP4 E00338 0 +OP4 E00339 0 +OP4 E0033A 0 +OP4 E0033B 0 +OP4 E0033C 0 +OP4 E0033D 0 +OP4 E0033E 0 +OP4 E0033F 0 +OP4 E00340 0 +OP4 E00341 0 +OP4 E00342 0 +OP4 E00343 0 +OP4 E00344 0 +OP4 E00345 0 +OP4 E00346 0 +OP4 E00347 0 +OP4 E00348 0 +OP4 E00349 0 +OP4 E0034A 0 +OP4 E0034B 0 +OP4 E0034C 0 +OP4 E0034D 0 +OP4 E0034E 0 +OP4 E0034F 0 +OP4 E00350 0 +OP4 E00351 0 +OP4 E00352 0 +OP4 E00353 0 +OP4 E00354 0 +OP4 E00355 0 +OP4 E00356 0 +OP4 E00357 0 +OP4 E00358 0 +OP4 E00359 0 +OP4 E0035A 0 +OP4 E0035B 0 +OP4 E0035C 0 +OP4 E0035D 0 +OP4 E0035E 0 +OP4 E0035F 0 +OP4 E00360 0 +OP4 E00361 0 +OP4 E00362 0 +OP4 E00363 0 +OP4 E00364 0 +OP4 E00365 0 +OP4 E00366 0 +OP4 E00367 0 +OP4 E00368 0 +OP4 E00369 0 +OP4 E0036A 0 +OP4 E0036B 0 +OP4 E0036C 0 +OP4 E0036D 0 +OP4 E0036E 0 +OP4 E0036F 0 +OP4 E00370 0 +OP4 E00371 0 +OP4 E00372 0 +OP4 E00373 0 +OP4 E00374 0 +OP4 E00375 0 +OP4 E00376 0 +OP4 E00377 0 +OP4 E00378 0 +OP4 E00379 0 +OP4 E0037A 0 +OP4 E0037B 0 +OP4 E0037C 0 +OP4 E0037D 0 +OP4 E0037E 0 +OP4 E0037F 0 +OP4 E00380 0 +OP4 E00381 0 +OP4 E00382 0 +OP4 E00383 0 +OP4 E00384 0 +OP4 E00385 0 +OP4 E00386 0 +OP4 E00387 0 +OP4 E00388 0 +OP4 E00389 0 +OP4 E0038A 0 +OP4 E0038B 0 +OP4 E0038C 0 +OP4 E0038D 0 +OP4 E0038E 0 +OP4 E0038F 0 +OP4 E00390 0 +OP4 E00391 0 +OP4 E00392 0 +OP4 E00393 0 +OP4 E00394 0 +OP4 E00395 0 +OP4 E00396 0 +OP4 E00397 0 +OP4 E00398 0 +OP4 E00399 0 +OP4 E0039A 0 +OP4 E0039B 0 +OP4 E0039C 0 +OP4 E0039D 0 +OP4 E0039E 0 +OP4 E0039F 0 +OP4 E003A0 0 +OP4 E003A1 0 +OP4 E003A2 0 +OP4 E003A3 0 +OP4 E003A4 0 +OP4 E003A5 0 +OP4 E003A6 0 +OP4 E003A7 0 +OP4 E003A8 0 +OP4 E003A9 0 +OP4 E003AA 0 +OP4 E003AB 0 +OP4 E003AC 0 +OP4 E003AD 0 +OP4 E003AE 0 +OP4 E003AF 0 +OP4 E003B0 0 +OP4 E003B1 0 +OP4 E003B2 0 +OP4 E003B3 0 +OP4 E003B4 0 +OP4 E003B5 0 +OP4 E003B6 0 +OP4 E003B7 0 +OP4 E003B8 0 +OP4 E003B9 0 +OP4 E003BA 0 +OP4 E003BB 0 +OP4 E003BC 0 +OP4 E003BD 0 +OP4 E003BE 0 +OP4 E003BF 0 +OP4 E003C0 0 +OP4 E003C1 0 +OP4 E003C2 0 +OP4 E003C3 0 +OP4 E003C4 0 +OP4 E003C5 0 +OP4 E003C6 0 +OP4 E003C7 0 +OP4 E003C8 0 +OP4 E003C9 0 +OP4 E003CA 0 +OP4 E003CB 0 +OP4 E003CC 0 +OP4 E003CD 0 +OP4 E003CE 0 +OP4 E003CF 0 +OP4 E003D0 0 +OP4 E003D1 0 +OP4 E003D2 0 +OP4 E003D3 0 +OP4 E003D4 0 +OP4 E003D5 0 +OP4 E003D6 0 +OP4 E003D7 0 +OP4 E003D8 0 +OP4 E003D9 0 +OP4 E003DA 0 +OP4 E003DB 0 +OP4 E003DC 0 +OP4 E003DD 0 +OP4 E003DE 0 +OP4 E003DF 0 +OP4 E003E0 0 +OP4 E003E1 0 +OP4 E003E2 0 +OP4 E003E3 0 +OP4 E003E4 0 +OP4 E003E5 0 +OP4 E003E6 0 +OP4 E003E7 0 +OP4 E003E8 0 +OP4 E003E9 0 +OP4 E003EA 0 +OP4 E003EB 0 +OP4 E003EC 0 +OP4 E003ED 0 +OP4 E003EE 0 +OP4 E003EF 0 +OP4 E003F0 0 +OP4 E003F1 0 +OP4 E003F2 0 +OP4 E003F3 0 +OP4 E003F4 0 +OP4 E003F5 0 +OP4 E003F6 0 +OP4 E003F7 0 +OP4 E003F8 0 +OP4 E003F9 0 +OP4 E003FA 0 +OP4 E003FB 0 +OP4 E003FC 0 +OP4 E003FD 0 +OP4 E003FE 0 +OP4 E003FF 0 +OP4 E00400 0 +OP4 E00401 0 +OP4 E00402 0 +OP4 E00403 0 +OP4 E00404 0 +OP4 E00405 0 +OP4 E00406 0 +OP4 E00407 0 +OP4 E00408 0 +OP4 E00409 0 +OP4 E0040A 0 +OP4 E0040B 0 +OP4 E0040C 0 +OP4 E0040D 0 +OP4 E0040E 0 +OP4 E0040F 0 +OP4 E00410 0 +OP4 E00411 0 +OP4 E00412 0 +OP4 E00413 0 +OP4 E00414 0 +OP4 E00415 0 +OP4 E00416 0 +OP4 E00417 0 +OP4 E00418 0 +OP4 E00419 0 +OP4 E0041A 0 +OP4 E0041B 0 +OP4 E0041C 0 +OP4 E0041D 0 +OP4 E0041E 0 +OP4 E0041F 0 +OP4 E00420 0 +OP4 E00421 0 +OP4 E00422 0 +OP4 E00423 0 +OP4 E00424 0 +OP4 E00425 0 +OP4 E00426 0 +OP4 E00427 0 +OP4 E00428 0 +OP4 E00429 0 +OP4 E0042A 0 +OP4 E0042B 0 +OP4 E0042C 0 +OP4 E0042D 0 +OP4 E0042E 0 +OP4 E0042F 0 +OP4 E00430 0 +OP4 E00431 0 +OP4 E00432 0 +OP4 E00433 0 +OP4 E00434 0 +OP4 E00435 0 +OP4 E00436 0 +OP4 E00437 0 +OP4 E00438 0 +OP4 E00439 0 +OP4 E0043A 0 +OP4 E0043B 0 +OP4 E0043C 0 +OP4 E0043D 0 +OP4 E0043E 0 +OP4 E0043F 0 +OP4 E00440 0 +OP4 E00441 0 +OP4 E00442 0 +OP4 E00443 0 +OP4 E00444 0 +OP4 E00445 0 +OP4 E00446 0 +OP4 E00447 0 +OP4 E00448 0 +OP4 E00449 0 +OP4 E0044A 0 +OP4 E0044B 0 +OP4 E0044C 0 +OP4 E0044D 0 +OP4 E0044E 0 +OP4 E0044F 0 +OP4 E00450 0 +OP4 E00451 0 +OP4 E00452 0 +OP4 E00453 0 +OP4 E00454 0 +OP4 E00455 0 +OP4 E00456 0 +OP4 E00457 0 +OP4 E00458 0 +OP4 E00459 0 +OP4 E0045A 0 +OP4 E0045B 0 +OP4 E0045C 0 +OP4 E0045D 0 +OP4 E0045E 0 +OP4 E0045F 0 +OP4 E00460 0 +OP4 E00461 0 +OP4 E00462 0 +OP4 E00463 0 +OP4 E00464 0 +OP4 E00465 0 +OP4 E00466 0 +OP4 E00467 0 +OP4 E00468 0 +OP4 E00469 0 +OP4 E0046A 0 +OP4 E0046B 0 +OP4 E0046C 0 +OP4 E0046D 0 +OP4 E0046E 0 +OP4 E0046F 0 +OP4 E00470 0 +OP4 E00471 0 +OP4 E00472 0 +OP4 E00473 0 +OP4 E00474 0 +OP4 E00475 0 +OP4 E00476 0 +OP4 E00477 0 +OP4 E00478 0 +OP4 E00479 0 +OP4 E0047A 0 +OP4 E0047B 0 +OP4 E0047C 0 +OP4 E0047D 0 +OP4 E0047E 0 +OP4 E0047F 0 +OP4 E00480 0 +OP4 E00481 0 +OP4 E00482 0 +OP4 E00483 0 +OP4 E00484 0 +OP4 E00485 0 +OP4 E00486 0 +OP4 E00487 0 +OP4 E00488 0 +OP4 E00489 0 +OP4 E0048A 0 +OP4 E0048B 0 +OP4 E0048C 0 +OP4 E0048D 0 +OP4 E0048E 0 +OP4 E0048F 0 +OP4 E00490 0 +OP4 E00491 0 +OP4 E00492 0 +OP4 E00493 0 +OP4 E00494 0 +OP4 E00495 0 +OP4 E00496 0 +OP4 E00497 0 +OP4 E00498 0 +OP4 E00499 0 +OP4 E0049A 0 +OP4 E0049B 0 +OP4 E0049C 0 +OP4 E0049D 0 +OP4 E0049E 0 +OP4 E0049F 0 +OP4 E004A0 0 +OP4 E004A1 0 +OP4 E004A2 0 +OP4 E004A3 0 +OP4 E004A4 0 +OP4 E004A5 0 +OP4 E004A6 0 +OP4 E004A7 0 +OP4 E004A8 0 +OP4 E004A9 0 +OP4 E004AA 0 +OP4 E004AB 0 +OP4 E004AC 0 +OP4 E004AD 0 +OP4 E004AE 0 +OP4 E004AF 0 +OP4 E004B0 0 +OP4 E004B1 0 +OP4 E004B2 0 +OP4 E004B3 0 +OP4 E004B4 0 +OP4 E004B5 0 +OP4 E004B6 0 +OP4 E004B7 0 +OP4 E004B8 0 +OP4 E004B9 0 +OP4 E004BA 0 +OP4 E004BB 0 +OP4 E004BC 0 +OP4 E004BD 0 +OP4 E004BE 0 +OP4 E004BF 0 +OP4 E004C0 0 +OP4 E004C1 0 +OP4 E004C2 0 +OP4 E004C3 0 +OP4 E004C4 0 +OP4 E004C5 0 +OP4 E004C6 0 +OP4 E004C7 0 +OP4 E004C8 0 +OP4 E004C9 0 +OP4 E004CA 0 +OP4 E004CB 0 +OP4 E004CC 0 +OP4 E004CD 0 +OP4 E004CE 0 +OP4 E004CF 0 +OP4 E004D0 0 +OP4 E004D1 0 +OP4 E004D2 0 +OP4 E004D3 0 +OP4 E004D4 0 +OP4 E004D5 0 +OP4 E004D6 0 +OP4 E004D7 0 +OP4 E004D8 0 +OP4 E004D9 0 +OP4 E004DA 0 +OP4 E004DB 0 +OP4 E004DC 0 +OP4 E004DD 0 +OP4 E004DE 0 +OP4 E004DF 0 +OP4 E004E0 0 +OP4 E004E1 0 +OP4 E004E2 0 +OP4 E004E3 0 +OP4 E004E4 0 +OP4 E004E5 0 +OP4 E004E6 0 +OP4 E004E7 0 +OP4 E004E8 0 +OP4 E004E9 0 +OP4 E004EA 0 +OP4 E004EB 0 +OP4 E004EC 0 +OP4 E004ED 0 +OP4 E004EE 0 +OP4 E004EF 0 +OP4 E004F0 0 +OP4 E004F1 0 +OP4 E004F2 0 +OP4 E004F3 0 +OP4 E004F4 0 +OP4 E004F5 0 +OP4 E004F6 0 +OP4 E004F7 0 +OP4 E004F8 0 +OP4 E004F9 0 +OP4 E004FA 0 +OP4 E004FB 0 +OP4 E004FC 0 +OP4 E004FD 0 +OP4 E004FE 0 +OP4 E004FF 0 +OP4 E00500 0 +OP4 E00501 0 +OP4 E00502 0 +OP4 E00503 0 +OP4 E00504 0 +OP4 E00505 0 +OP4 E00506 0 +OP4 E00507 0 +OP4 E00508 0 +OP4 E00509 0 +OP4 E0050A 0 +OP4 E0050B 0 +OP4 E0050C 0 +OP4 E0050D 0 +OP4 E0050E 0 +OP4 E0050F 0 +OP4 E00510 0 +OP4 E00511 0 +OP4 E00512 0 +OP4 E00513 0 +OP4 E00514 0 +OP4 E00515 0 +OP4 E00516 0 +OP4 E00517 0 +OP4 E00518 0 +OP4 E00519 0 +OP4 E0051A 0 +OP4 E0051B 0 +OP4 E0051C 0 +OP4 E0051D 0 +OP4 E0051E 0 +OP4 E0051F 0 +OP4 E00520 0 +OP4 E00521 0 +OP4 E00522 0 +OP4 E00523 0 +OP4 E00524 0 +OP4 E00525 0 +OP4 E00526 0 +OP4 E00527 0 +OP4 E00528 0 +OP4 E00529 0 +OP4 E0052A 0 +OP4 E0052B 0 +OP4 E0052C 0 +OP4 E0052D 0 +OP4 E0052E 0 +OP4 E0052F 0 +OP4 E00530 0 +OP4 E00531 0 +OP4 E00532 0 +OP4 E00533 0 +OP4 E00534 0 +OP4 E00535 0 +OP4 E00536 0 +OP4 E00537 0 +OP4 E00538 0 +OP4 E00539 0 +OP4 E0053A 0 +OP4 E0053B 0 +OP4 E0053C 0 +OP4 E0053D 0 +OP4 E0053E 0 +OP4 E0053F 0 +OP4 E00540 0 +OP4 E00541 0 +OP4 E00542 0 +OP4 E00543 0 +OP4 E00544 0 +OP4 E00545 0 +OP4 E00546 0 +OP4 E00547 0 +OP4 E00548 0 +OP4 E00549 0 +OP4 E0054A 0 +OP4 E0054B 0 +OP4 E0054C 0 +OP4 E0054D 0 +OP4 E0054E 0 +OP4 E0054F 0 +OP4 E00550 0 +OP4 E00551 0 +OP4 E00552 0 +OP4 E00553 0 +OP4 E00554 0 +OP4 E00555 0 +OP4 E00556 0 +OP4 E00557 0 +OP4 E00558 0 +OP4 E00559 0 +OP4 E0055A 0 +OP4 E0055B 0 +OP4 E0055C 0 +OP4 E0055D 0 +OP4 E0055E 0 +OP4 E0055F 0 +OP4 E00560 0 +OP4 E00561 0 +OP4 E00562 0 +OP4 E00563 0 +OP4 E00564 0 +OP4 E00565 0 +OP4 E00566 0 +OP4 E00567 0 +OP4 E00568 0 +OP4 E00569 0 +OP4 E0056A 0 +OP4 E0056B 0 +OP4 E0056C 0 +OP4 E0056D 0 +OP4 E0056E 0 +OP4 E0056F 0 +OP4 E00570 0 +OP4 E00571 0 +OP4 E00572 0 +OP4 E00573 0 +OP4 E00574 0 +OP4 E00575 0 +OP4 E00576 0 +OP4 E00577 0 +OP4 E00578 0 +OP4 E00579 0 +OP4 E0057A 0 +OP4 E0057B 0 +OP4 E0057C 0 +OP4 E0057D 0 +OP4 E0057E 0 +OP4 E0057F 0 +OP4 E00580 0 +OP4 E00581 0 +OP4 E00582 0 +OP4 E00583 0 +OP4 E00584 0 +OP4 E00585 0 +OP4 E00586 0 +OP4 E00587 0 +OP4 E00588 0 +OP4 E00589 0 +OP4 E0058A 0 +OP4 E0058B 0 +OP4 E0058C 0 +OP4 E0058D 0 +OP4 E0058E 0 +OP4 E0058F 0 +OP4 E00590 0 +OP4 E00591 0 +OP4 E00592 0 +OP4 E00593 0 +OP4 E00594 0 +OP4 E00595 0 +OP4 E00596 0 +OP4 E00597 0 +OP4 E00598 0 +OP4 E00599 0 +OP4 E0059A 0 +OP4 E0059B 0 +OP4 E0059C 0 +OP4 E0059D 0 +OP4 E0059E 0 +OP4 E0059F 0 +OP4 E005A0 0 +OP4 E005A1 0 +OP4 E005A2 0 +OP4 E005A3 0 +OP4 E005A4 0 +OP4 E005A5 0 +OP4 E005A6 0 +OP4 E005A7 0 +OP4 E005A8 0 +OP4 E005A9 0 +OP4 E005AA 0 +OP4 E005AB 0 +OP4 E005AC 0 +OP4 E005AD 0 +OP4 E005AE 0 +OP4 E005AF 0 +OP4 E005B0 0 +OP4 E005B1 0 +OP4 E005B2 0 +OP4 E005B3 0 +OP4 E005B4 0 +OP4 E005B5 0 +OP4 E005B6 0 +OP4 E005B7 0 +OP4 E005B8 0 +OP4 E005B9 0 +OP4 E005BA 0 +OP4 E005BB 0 +OP4 E005BC 0 +OP4 E005BD 0 +OP4 E005BE 0 +OP4 E005BF 0 +OP4 E005C0 0 +OP4 E005C1 0 +OP4 E005C2 0 +OP4 E005C3 0 +OP4 E005C4 0 +OP4 E005C5 0 +OP4 E005C6 0 +OP4 E005C7 0 +OP4 E005C8 0 +OP4 E005C9 0 +OP4 E005CA 0 +OP4 E005CB 0 +OP4 E005CC 0 +OP4 E005CD 0 +OP4 E005CE 0 +OP4 E005CF 0 +OP4 E005D0 0 +OP4 E005D1 0 +OP4 E005D2 0 +OP4 E005D3 0 +OP4 E005D4 0 +OP4 E005D5 0 +OP4 E005D6 0 +OP4 E005D7 0 +OP4 E005D8 0 +OP4 E005D9 0 +OP4 E005DA 0 +OP4 E005DB 0 +OP4 E005DC 0 +OP4 E005DD 0 +OP4 E005DE 0 +OP4 E005DF 0 +OP4 E005E0 0 +OP4 E005E1 0 +OP4 E005E2 0 +OP4 E005E3 0 +OP4 E005E4 0 +OP4 E005E5 0 +OP4 E005E6 0 +OP4 E005E7 0 +OP4 E005E8 0 +OP4 E005E9 0 +OP4 E005EA 0 +OP4 E005EB 0 +OP4 E005EC 0 +OP4 E005ED 0 +OP4 E005EE 0 +OP4 E005EF 0 +OP4 E005F0 0 +OP4 E005F1 0 +OP4 E005F2 0 +OP4 E005F3 0 +OP4 E005F4 0 +OP4 E005F5 0 +OP4 E005F6 0 +OP4 E005F7 0 +OP4 E005F8 0 +OP4 E005F9 0 +OP4 E005FA 0 +OP4 E005FB 0 +OP4 E005FC 0 +OP4 E005FD 0 +OP4 E005FE 0 +OP4 E005FF 0 +OP4 E00600 0 +OP4 E00601 0 +OP4 E00602 0 +OP4 E00603 0 +OP4 E00604 0 +OP4 E00605 0 +OP4 E00606 0 +OP4 E00607 0 +OP4 E00608 0 +OP4 E00609 0 +OP4 E0060A 0 +OP4 E0060B 0 +OP4 E0060C 0 +OP4 E0060D 0 +OP4 E0060E 0 +OP4 E0060F 0 +OP4 E00610 0 +OP4 E00611 0 +OP4 E00612 0 +OP4 E00613 0 +OP4 E00614 0 +OP4 E00615 0 +OP4 E00616 0 +OP4 E00617 0 +OP4 E00618 0 +OP4 E00619 0 +OP4 E0061A 0 +OP4 E0061B 0 +OP4 E0061C 0 +OP4 E0061D 0 +OP4 E0061E 0 +OP4 E0061F 0 +OP4 E00620 0 +OP4 E00621 0 +OP4 E00622 0 +OP4 E00623 0 +OP4 E00624 0 +OP4 E00625 0 +OP4 E00626 0 +OP4 E00627 0 +OP4 E00628 0 +OP4 E00629 0 +OP4 E0062A 0 +OP4 E0062B 0 +OP4 E0062C 0 +OP4 E0062D 0 +OP4 E0062E 0 +OP4 E0062F 0 +OP4 E00630 0 +OP4 E00631 0 +OP4 E00632 0 +OP4 E00633 0 +OP4 E00634 0 +OP4 E00635 0 +OP4 E00636 0 +OP4 E00637 0 +OP4 E00638 0 +OP4 E00639 0 +OP4 E0063A 0 +OP4 E0063B 0 +OP4 E0063C 0 +OP4 E0063D 0 +OP4 E0063E 0 +OP4 E0063F 0 +OP4 E00640 0 +OP4 E00641 0 +OP4 E00642 0 +OP4 E00643 0 +OP4 E00644 0 +OP4 E00645 0 +OP4 E00646 0 +OP4 E00647 0 +OP4 E00648 0 +OP4 E00649 0 +OP4 E0064A 0 +OP4 E0064B 0 +OP4 E0064C 0 +OP4 E0064D 0 +OP4 E0064E 0 +OP4 E0064F 0 +OP4 E00650 0 +OP4 E00651 0 +OP4 E00652 0 +OP4 E00653 0 +OP4 E00654 0 +OP4 E00655 0 +OP4 E00656 0 +OP4 E00657 0 +OP4 E00658 0 +OP4 E00659 0 +OP4 E0065A 0 +OP4 E0065B 0 +OP4 E0065C 0 +OP4 E0065D 0 +OP4 E0065E 0 +OP4 E0065F 0 +OP4 E00660 0 +OP4 E00661 0 +OP4 E00662 0 +OP4 E00663 0 +OP4 E00664 0 +OP4 E00665 0 +OP4 E00666 0 +OP4 E00667 0 +OP4 E00668 0 +OP4 E00669 0 +OP4 E0066A 0 +OP4 E0066B 0 +OP4 E0066C 0 +OP4 E0066D 0 +OP4 E0066E 0 +OP4 E0066F 0 +OP4 E00670 0 +OP4 E00671 0 +OP4 E00672 0 +OP4 E00673 0 +OP4 E00674 0 +OP4 E00675 0 +OP4 E00676 0 +OP4 E00677 0 +OP4 E00678 0 +OP4 E00679 0 +OP4 E0067A 0 +OP4 E0067B 0 +OP4 E0067C 0 +OP4 E0067D 0 +OP4 E0067E 0 +OP4 E0067F 0 +OP4 E00680 0 +OP4 E00681 0 +OP4 E00682 0 +OP4 E00683 0 +OP4 E00684 0 +OP4 E00685 0 +OP4 E00686 0 +OP4 E00687 0 +OP4 E00688 0 +OP4 E00689 0 +OP4 E0068A 0 +OP4 E0068B 0 +OP4 E0068C 0 +OP4 E0068D 0 +OP4 E0068E 0 +OP4 E0068F 0 +OP4 E00690 0 +OP4 E00691 0 +OP4 E00692 0 +OP4 E00693 0 +OP4 E00694 0 +OP4 E00695 0 +OP4 E00696 0 +OP4 E00697 0 +OP4 E00698 0 +OP4 E00699 0 +OP4 E0069A 0 +OP4 E0069B 0 +OP4 E0069C 0 +OP4 E0069D 0 +OP4 E0069E 0 +OP4 E0069F 0 +OP4 E006A0 0 +OP4 E006A1 0 +OP4 E006A2 0 +OP4 E006A3 0 +OP4 E006A4 0 +OP4 E006A5 0 +OP4 E006A6 0 +OP4 E006A7 0 +OP4 E006A8 0 +OP4 E006A9 0 +OP4 E006AA 0 +OP4 E006AB 0 +OP4 E006AC 0 +OP4 E006AD 0 +OP4 E006AE 0 +OP4 E006AF 0 +OP4 E006B0 0 +OP4 E006B1 0 +OP4 E006B2 0 +OP4 E006B3 0 +OP4 E006B4 0 +OP4 E006B5 0 +OP4 E006B6 0 +OP4 E006B7 0 +OP4 E006B8 0 +OP4 E006B9 0 +OP4 E006BA 0 +OP4 E006BB 0 +OP4 E006BC 0 +OP4 E006BD 0 +OP4 E006BE 0 +OP4 E006BF 0 +OP4 E006C0 0 +OP4 E006C1 0 +OP4 E006C2 0 +OP4 E006C3 0 +OP4 E006C4 0 +OP4 E006C5 0 +OP4 E006C6 0 +OP4 E006C7 0 +OP4 E006C8 0 +OP4 E006C9 0 +OP4 E006CA 0 +OP4 E006CB 0 +OP4 E006CC 0 +OP4 E006CD 0 +OP4 E006CE 0 +OP4 E006CF 0 +OP4 E006D0 0 +OP4 E006D1 0 +OP4 E006D2 0 +OP4 E006D3 0 +OP4 E006D4 0 +OP4 E006D5 0 +OP4 E006D6 0 +OP4 E006D7 0 +OP4 E006D8 0 +OP4 E006D9 0 +OP4 E006DA 0 +OP4 E006DB 0 +OP4 E006DC 0 +OP4 E006DD 0 +OP4 E006DE 0 +OP4 E006DF 0 +OP4 E006E0 0 +OP4 E006E1 0 +OP4 E006E2 0 +OP4 E006E3 0 +OP4 E006E4 0 +OP4 E006E5 0 +OP4 E006E6 0 +OP4 E006E7 0 +OP4 E006E8 0 +OP4 E006E9 0 +OP4 E006EA 0 +OP4 E006EB 0 +OP4 E006EC 0 +OP4 E006ED 0 +OP4 E006EE 0 +OP4 E006EF 0 +OP4 E006F0 0 +OP4 E006F1 0 +OP4 E006F2 0 +OP4 E006F3 0 +OP4 E006F4 0 +OP4 E006F5 0 +OP4 E006F6 0 +OP4 E006F7 0 +OP4 E006F8 0 +OP4 E006F9 0 +OP4 E006FA 0 +OP4 E006FB 0 +OP4 E006FC 0 +OP4 E006FD 0 +OP4 E006FE 0 +OP4 E006FF 0 +OP4 E00700 0 +OP4 E00701 0 +OP4 E00702 0 +OP4 E00703 0 +OP4 E00704 0 +OP4 E00705 0 +OP4 E00706 0 +OP4 E00707 0 +OP4 E00708 0 +OP4 E00709 0 +OP4 E0070A 0 +OP4 E0070B 0 +OP4 E0070C 0 +OP4 E0070D 0 +OP4 E0070E 0 +OP4 E0070F 0 +OP4 E00710 0 +OP4 E00711 0 +OP4 E00712 0 +OP4 E00713 0 +OP4 E00714 0 +OP4 E00715 0 +OP4 E00716 0 +OP4 E00717 0 +OP4 E00718 0 +OP4 E00719 0 +OP4 E0071A 0 +OP4 E0071B 0 +OP4 E0071C 0 +OP4 E0071D 0 +OP4 E0071E 0 +OP4 E0071F 0 +OP4 E00720 0 +OP4 E00721 0 +OP4 E00722 0 +OP4 E00723 0 +OP4 E00724 0 +OP4 E00725 0 +OP4 E00726 0 +OP4 E00727 0 +OP4 E00728 0 +OP4 E00729 0 +OP4 E0072A 0 +OP4 E0072B 0 +OP4 E0072C 0 +OP4 E0072D 0 +OP4 E0072E 0 +OP4 E0072F 0 +OP4 E00730 0 +OP4 E00731 0 +OP4 E00732 0 +OP4 E00733 0 +OP4 E00734 0 +OP4 E00735 0 +OP4 E00736 0 +OP4 E00737 0 +OP4 E00738 0 +OP4 E00739 0 +OP4 E0073A 0 +OP4 E0073B 0 +OP4 E0073C 0 +OP4 E0073D 0 +OP4 E0073E 0 +OP4 E0073F 0 +OP4 E00740 0 +OP4 E00741 0 +OP4 E00742 0 +OP4 E00743 0 +OP4 E00744 0 +OP4 E00745 0 +OP4 E00746 0 +OP4 E00747 0 +OP4 E00748 0 +OP4 E00749 0 +OP4 E0074A 0 +OP4 E0074B 0 +OP4 E0074C 0 +OP4 E0074D 0 +OP4 E0074E 0 +OP4 E0074F 0 +OP4 E00750 0 +OP4 E00751 0 +OP4 E00752 0 +OP4 E00753 0 +OP4 E00754 0 +OP4 E00755 0 +OP4 E00756 0 +OP4 E00757 0 +OP4 E00758 0 +OP4 E00759 0 +OP4 E0075A 0 +OP4 E0075B 0 +OP4 E0075C 0 +OP4 E0075D 0 +OP4 E0075E 0 +OP4 E0075F 0 +OP4 E00760 0 +OP4 E00761 0 +OP4 E00762 0 +OP4 E00763 0 +OP4 E00764 0 +OP4 E00765 0 +OP4 E00766 0 +OP4 E00767 0 +OP4 E00768 0 +OP4 E00769 0 +OP4 E0076A 0 +OP4 E0076B 0 +OP4 E0076C 0 +OP4 E0076D 0 +OP4 E0076E 0 +OP4 E0076F 0 +OP4 E00770 0 +OP4 E00771 0 +OP4 E00772 0 +OP4 E00773 0 +OP4 E00774 0 +OP4 E00775 0 +OP4 E00776 0 +OP4 E00777 0 +OP4 E00778 0 +OP4 E00779 0 +OP4 E0077A 0 +OP4 E0077B 0 +OP4 E0077C 0 +OP4 E0077D 0 +OP4 E0077E 0 +OP4 E0077F 0 +OP4 E00780 0 +OP4 E00781 0 +OP4 E00782 0 +OP4 E00783 0 +OP4 E00784 0 +OP4 E00785 0 +OP4 E00786 0 +OP4 E00787 0 +OP4 E00788 0 +OP4 E00789 0 +OP4 E0078A 0 +OP4 E0078B 0 +OP4 E0078C 0 +OP4 E0078D 0 +OP4 E0078E 0 +OP4 E0078F 0 +OP4 E00790 0 +OP4 E00791 0 +OP4 E00792 0 +OP4 E00793 0 +OP4 E00794 0 +OP4 E00795 0 +OP4 E00796 0 +OP4 E00797 0 +OP4 E00798 0 +OP4 E00799 0 +OP4 E0079A 0 +OP4 E0079B 0 +OP4 E0079C 0 +OP4 E0079D 0 +OP4 E0079E 0 +OP4 E0079F 0 +OP4 E007A0 0 +OP4 E007A1 0 +OP4 E007A2 0 +OP4 E007A3 0 +OP4 E007A4 0 +OP4 E007A5 0 +OP4 E007A6 0 +OP4 E007A7 0 +OP4 E007A8 0 +OP4 E007A9 0 +OP4 E007AA 0 +OP4 E007AB 0 +OP4 E007AC 0 +OP4 E007AD 0 +OP4 E007AE 0 +OP4 E007AF 0 +OP4 E007B0 0 +OP4 E007B1 0 +OP4 E007B2 0 +OP4 E007B3 0 +OP4 E007B4 0 +OP4 E007B5 0 +OP4 E007B6 0 +OP4 E007B7 0 +OP4 E007B8 0 +OP4 E007B9 0 +OP4 E007BA 0 +OP4 E007BB 0 +OP4 E007BC 0 +OP4 E007BD 0 +OP4 E007BE 0 +OP4 E007BF 0 +OP4 E007C0 0 +OP4 E007C1 0 +OP4 E007C2 0 +OP4 E007C3 0 +OP4 E007C4 0 +OP4 E007C5 0 +OP4 E007C6 0 +OP4 E007C7 0 +OP4 E007C8 0 +OP4 E007C9 0 +OP4 E007CA 0 +OP4 E007CB 0 +OP4 E007CC 0 +OP4 E007CD 0 +OP4 E007CE 0 +OP4 E007CF 0 +OP4 E007D0 0 +OP4 E007D1 0 +OP4 E007D2 0 +OP4 E007D3 0 +OP4 E007D4 0 +OP4 E007D5 0 +OP4 E007D6 0 +OP4 E007D7 0 +OP4 E007D8 0 +OP4 E007D9 0 +OP4 E007DA 0 +OP4 E007DB 0 +OP4 E007DC 0 +OP4 E007DD 0 +OP4 E007DE 0 +OP4 E007DF 0 +OP4 E007E0 0 +OP4 E007E1 0 +OP4 E007E2 0 +OP4 E007E3 0 +OP4 E007E4 0 +OP4 E007E5 0 +OP4 E007E6 0 +OP4 E007E7 0 +OP4 E007E8 0 +OP4 E007E9 0 +OP4 E007EA 0 +OP4 E007EB 0 +OP4 E007EC 0 +OP4 E007ED 0 +OP4 E007EE 0 +OP4 E007EF 0 +OP4 E007F0 0 +OP4 E007F1 0 +OP4 E007F2 0 +OP4 E007F3 0 +OP4 E007F4 0 +OP4 E007F5 0 +OP4 E007F6 0 +OP4 E007F7 0 +OP4 E007F8 0 +OP4 E007F9 0 +OP4 E007FA 0 +OP4 E007FB 0 +OP4 E007FC 0 +OP4 E007FD 0 +OP4 E007FE 0 +OP4 E007FF 0 +OP4 E00800 0 +OP4 E00801 0 +OP4 E00802 0 +OP4 E00803 0 +OP4 E00804 0 +OP4 E00805 0 +OP4 E00806 0 +OP4 E00807 0 +OP4 E00808 0 +OP4 E00809 0 +OP4 E0080A 0 +OP4 E0080B 0 +OP4 E0080C 0 +OP4 E0080D 0 +OP4 E0080E 0 +OP4 E0080F 0 +OP4 E00810 0 +OP4 E00811 0 +OP4 E00812 0 +OP4 E00813 0 +OP4 E00814 0 +OP4 E00815 0 +OP4 E00816 0 +OP4 E00817 0 +OP4 E00818 0 +OP4 E00819 0 +OP4 E0081A 0 +OP4 E0081B 0 +OP4 E0081C 0 +OP4 E0081D 0 +OP4 E0081E 0 +OP4 E0081F 0 +OP4 E00820 0 +OP4 E00821 0 +OP4 E00822 0 +OP4 E00823 0 +OP4 E00824 0 +OP4 E00825 0 +OP4 E00826 0 +OP4 E00827 0 +OP4 E00828 0 +OP4 E00829 0 +OP4 E0082A 0 +OP4 E0082B 0 +OP4 E0082C 0 +OP4 E0082D 0 +OP4 E0082E 0 +OP4 E0082F 0 +OP4 E00830 0 +OP4 E00831 0 +OP4 E00832 0 +OP4 E00833 0 +OP4 E00834 0 +OP4 E00835 0 +OP4 E00836 0 +OP4 E00837 0 +OP4 E00838 0 +OP4 E00839 0 +OP4 E0083A 0 +OP4 E0083B 0 +OP4 E0083C 0 +OP4 E0083D 0 +OP4 E0083E 0 +OP4 E0083F 0 +OP4 E00840 0 +OP4 E00841 0 +OP4 E00842 0 +OP4 E00843 0 +OP4 E00844 0 +OP4 E00845 0 +OP4 E00846 0 +OP4 E00847 0 +OP4 E00848 0 +OP4 E00849 0 +OP4 E0084A 0 +OP4 E0084B 0 +OP4 E0084C 0 +OP4 E0084D 0 +OP4 E0084E 0 +OP4 E0084F 0 +OP4 E00850 0 +OP4 E00851 0 +OP4 E00852 0 +OP4 E00853 0 +OP4 E00854 0 +OP4 E00855 0 +OP4 E00856 0 +OP4 E00857 0 +OP4 E00858 0 +OP4 E00859 0 +OP4 E0085A 0 +OP4 E0085B 0 +OP4 E0085C 0 +OP4 E0085D 0 +OP4 E0085E 0 +OP4 E0085F 0 +OP4 E00860 0 +OP4 E00861 0 +OP4 E00862 0 +OP4 E00863 0 +OP4 E00864 0 +OP4 E00865 0 +OP4 E00866 0 +OP4 E00867 0 +OP4 E00868 0 +OP4 E00869 0 +OP4 E0086A 0 +OP4 E0086B 0 +OP4 E0086C 0 +OP4 E0086D 0 +OP4 E0086E 0 +OP4 E0086F 0 +OP4 E00870 0 +OP4 E00871 0 +OP4 E00872 0 +OP4 E00873 0 +OP4 E00874 0 +OP4 E00875 0 +OP4 E00876 0 +OP4 E00877 0 +OP4 E00878 0 +OP4 E00879 0 +OP4 E0087A 0 +OP4 E0087B 0 +OP4 E0087C 0 +OP4 E0087D 0 +OP4 E0087E 0 +OP4 E0087F 0 +OP4 E00880 0 +OP4 E00881 0 +OP4 E00882 0 +OP4 E00883 0 +OP4 E00884 0 +OP4 E00885 0 +OP4 E00886 0 +OP4 E00887 0 +OP4 E00888 0 +OP4 E00889 0 +OP4 E0088A 0 +OP4 E0088B 0 +OP4 E0088C 0 +OP4 E0088D 0 +OP4 E0088E 0 +OP4 E0088F 0 +OP4 E00890 0 +OP4 E00891 0 +OP4 E00892 0 +OP4 E00893 0 +OP4 E00894 0 +OP4 E00895 0 +OP4 E00896 0 +OP4 E00897 0 +OP4 E00898 0 +OP4 E00899 0 +OP4 E0089A 0 +OP4 E0089B 0 +OP4 E0089C 0 +OP4 E0089D 0 +OP4 E0089E 0 +OP4 E0089F 0 +OP4 E008A0 0 +OP4 E008A1 0 +OP4 E008A2 0 +OP4 E008A3 0 +OP4 E008A4 0 +OP4 E008A5 0 +OP4 E008A6 0 +OP4 E008A7 0 +OP4 E008A8 0 +OP4 E008A9 0 +OP4 E008AA 0 +OP4 E008AB 0 +OP4 E008AC 0 +OP4 E008AD 0 +OP4 E008AE 0 +OP4 E008AF 0 +OP4 E008B0 0 +OP4 E008B1 0 +OP4 E008B2 0 +OP4 E008B3 0 +OP4 E008B4 0 +OP4 E008B5 0 +OP4 E008B6 0 +OP4 E008B7 0 +OP4 E008B8 0 +OP4 E008B9 0 +OP4 E008BA 0 +OP4 E008BB 0 +OP4 E008BC 0 +OP4 E008BD 0 +OP4 E008BE 0 +OP4 E008BF 0 +OP4 E008C0 0 +OP4 E008C1 0 +OP4 E008C2 0 +OP4 E008C3 0 +OP4 E008C4 0 +OP4 E008C5 0 +OP4 E008C6 0 +OP4 E008C7 0 +OP4 E008C8 0 +OP4 E008C9 0 +OP4 E008CA 0 +OP4 E008CB 0 +OP4 E008CC 0 +OP4 E008CD 0 +OP4 E008CE 0 +OP4 E008CF 0 +OP4 E008D0 0 +OP4 E008D1 0 +OP4 E008D2 0 +OP4 E008D3 0 +OP4 E008D4 0 +OP4 E008D5 0 +OP4 E008D6 0 +OP4 E008D7 0 +OP4 E008D8 0 +OP4 E008D9 0 +OP4 E008DA 0 +OP4 E008DB 0 +OP4 E008DC 0 +OP4 E008DD 0 +OP4 E008DE 0 +OP4 E008DF 0 +OP4 E008E0 0 +OP4 E008E1 0 +OP4 E008E2 0 +OP4 E008E3 0 +OP4 E008E4 0 +OP4 E008E5 0 +OP4 E008E6 0 +OP4 E008E7 0 +OP4 E008E8 0 +OP4 E008E9 0 +OP4 E008EA 0 +OP4 E008EB 0 +OP4 E008EC 0 +OP4 E008ED 0 +OP4 E008EE 0 +OP4 E008EF 0 +OP4 E008F0 0 +OP4 E008F1 0 +OP4 E008F2 0 +OP4 E008F3 0 +OP4 E008F4 0 +OP4 E008F5 0 +OP4 E008F6 0 +OP4 E008F7 0 +OP4 E008F8 0 +OP4 E008F9 0 +OP4 E008FA 0 +OP4 E008FB 0 +OP4 E008FC 0 +OP4 E008FD 0 +OP4 E008FE 0 +OP4 E008FF 0 +OP4 E00900 0 +OP4 E00901 0 +OP4 E00902 0 +OP4 E00903 0 +OP4 E00904 0 +OP4 E00905 0 +OP4 E00906 0 +OP4 E00907 0 +OP4 E00908 0 +OP4 E00909 0 +OP4 E0090A 0 +OP4 E0090B 0 +OP4 E0090C 0 +OP4 E0090D 0 +OP4 E0090E 0 +OP4 E0090F 0 +OP4 E00910 0 +OP4 E00911 0 +OP4 E00912 0 +OP4 E00913 0 +OP4 E00914 0 +OP4 E00915 0 +OP4 E00916 0 +OP4 E00917 0 +OP4 E00918 0 +OP4 E00919 0 +OP4 E0091A 0 +OP4 E0091B 0 +OP4 E0091C 0 +OP4 E0091D 0 +OP4 E0091E 0 +OP4 E0091F 0 +OP4 E00920 0 +OP4 E00921 0 +OP4 E00922 0 +OP4 E00923 0 +OP4 E00924 0 +OP4 E00925 0 +OP4 E00926 0 +OP4 E00927 0 +OP4 E00928 0 +OP4 E00929 0 +OP4 E0092A 0 +OP4 E0092B 0 +OP4 E0092C 0 +OP4 E0092D 0 +OP4 E0092E 0 +OP4 E0092F 0 +OP4 E00930 0 +OP4 E00931 0 +OP4 E00932 0 +OP4 E00933 0 +OP4 E00934 0 +OP4 E00935 0 +OP4 E00936 0 +OP4 E00937 0 +OP4 E00938 0 +OP4 E00939 0 +OP4 E0093A 0 +OP4 E0093B 0 +OP4 E0093C 0 +OP4 E0093D 0 +OP4 E0093E 0 +OP4 E0093F 0 +OP4 E00940 0 +OP4 E00941 0 +OP4 E00942 0 +OP4 E00943 0 +OP4 E00944 0 +OP4 E00945 0 +OP4 E00946 0 +OP4 E00947 0 +OP4 E00948 0 +OP4 E00949 0 +OP4 E0094A 0 +OP4 E0094B 0 +OP4 E0094C 0 +OP4 E0094D 0 +OP4 E0094E 0 +OP4 E0094F 0 +OP4 E00950 0 +OP4 E00951 0 +OP4 E00952 0 +OP4 E00953 0 +OP4 E00954 0 +OP4 E00955 0 +OP4 E00956 0 +OP4 E00957 0 +OP4 E00958 0 +OP4 E00959 0 +OP4 E0095A 0 +OP4 E0095B 0 +OP4 E0095C 0 +OP4 E0095D 0 +OP4 E0095E 0 +OP4 E0095F 0 +OP4 E00960 0 +OP4 E00961 0 +OP4 E00962 0 +OP4 E00963 0 +OP4 E00964 0 +OP4 E00965 0 +OP4 E00966 0 +OP4 E00967 0 +OP4 E00968 0 +OP4 E00969 0 +OP4 E0096A 0 +OP4 E0096B 0 +OP4 E0096C 0 +OP4 E0096D 0 +OP4 E0096E 0 +OP4 E0096F 0 +OP4 E00970 0 +OP4 E00971 0 +OP4 E00972 0 +OP4 E00973 0 +OP4 E00974 0 +OP4 E00975 0 +OP4 E00976 0 +OP4 E00977 0 +OP4 E00978 0 +OP4 E00979 0 +OP4 E0097A 0 +OP4 E0097B 0 +OP4 E0097C 0 +OP4 E0097D 0 +OP4 E0097E 0 +OP4 E0097F 0 +OP4 E00980 0 +OP4 E00981 0 +OP4 E00982 0 +OP4 E00983 0 +OP4 E00984 0 +OP4 E00985 0 +OP4 E00986 0 +OP4 E00987 0 +OP4 E00988 0 +OP4 E00989 0 +OP4 E0098A 0 +OP4 E0098B 0 +OP4 E0098C 0 +OP4 E0098D 0 +OP4 E0098E 0 +OP4 E0098F 0 +OP4 E00990 0 +OP4 E00991 0 +OP4 E00992 0 +OP4 E00993 0 +OP4 E00994 0 +OP4 E00995 0 +OP4 E00996 0 +OP4 E00997 0 +OP4 E00998 0 +OP4 E00999 0 +OP4 E0099A 0 +OP4 E0099B 0 +OP4 E0099C 0 +OP4 E0099D 0 +OP4 E0099E 0 +OP4 E0099F 0 +OP4 E009A0 0 +OP4 E009A1 0 +OP4 E009A2 0 +OP4 E009A3 0 +OP4 E009A4 0 +OP4 E009A5 0 +OP4 E009A6 0 +OP4 E009A7 0 +OP4 E009A8 0 +OP4 E009A9 0 +OP4 E009AA 0 +OP4 E009AB 0 +OP4 E009AC 0 +OP4 E009AD 0 +OP4 E009AE 0 +OP4 E009AF 0 +OP4 E009B0 0 +OP4 E009B1 0 +OP4 E009B2 0 +OP4 E009B3 0 +OP4 E009B4 0 +OP4 E009B5 0 +OP4 E009B6 0 +OP4 E009B7 0 +OP4 E009B8 0 +OP4 E009B9 0 +OP4 E009BA 0 +OP4 E009BB 0 +OP4 E009BC 0 +OP4 E009BD 0 +OP4 E009BE 0 +OP4 E009BF 0 +OP4 E009C0 0 +OP4 E009C1 0 +OP4 E009C2 0 +OP4 E009C3 0 +OP4 E009C4 0 +OP4 E009C5 0 +OP4 E009C6 0 +OP4 E009C7 0 +OP4 E009C8 0 +OP4 E009C9 0 +OP4 E009CA 0 +OP4 E009CB 0 +OP4 E009CC 0 +OP4 E009CD 0 +OP4 E009CE 0 +OP4 E009CF 0 +OP4 E009D0 0 +OP4 E009D1 0 +OP4 E009D2 0 +OP4 E009D3 0 +OP4 E009D4 0 +OP4 E009D5 0 +OP4 E009D6 0 +OP4 E009D7 0 +OP4 E009D8 0 +OP4 E009D9 0 +OP4 E009DA 0 +OP4 E009DB 0 +OP4 E009DC 0 +OP4 E009DD 0 +OP4 E009DE 0 +OP4 E009DF 0 +OP4 E009E0 0 +OP4 E009E1 0 +OP4 E009E2 0 +OP4 E009E3 0 +OP4 E009E4 0 +OP4 E009E5 0 +OP4 E009E6 0 +OP4 E009E7 0 +OP4 E009E8 0 +OP4 E009E9 0 +OP4 E009EA 0 +OP4 E009EB 0 +OP4 E009EC 0 +OP4 E009ED 0 +OP4 E009EE 0 +OP4 E009EF 0 +OP4 E009F0 0 +OP4 E009F1 0 +OP4 E009F2 0 +OP4 E009F3 0 +OP4 E009F4 0 +OP4 E009F5 0 +OP4 E009F6 0 +OP4 E009F7 0 +OP4 E009F8 0 +OP4 E009F9 0 +OP4 E009FA 0 +OP4 E009FB 0 +OP4 E009FC 0 +OP4 E009FD 0 +OP4 E009FE 0 +OP4 E009FF 0 +OP4 E00A00 0 +OP4 E00A01 0 +OP4 E00A02 0 +OP4 E00A03 0 +OP4 E00A04 0 +OP4 E00A05 0 +OP4 E00A06 0 +OP4 E00A07 0 +OP4 E00A08 0 diff --git a/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum2_itrace_irisc1.cfg.ext b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum2_itrace_irisc1.cfg.ext new file mode 100644 index 000000000000..f5df804d8285 --- /dev/null +++ b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum2_itrace_irisc1.cfg.ext @@ -0,0 +1,2570 @@ +OP1 Spectrum2 +OP4 ITRACE0 0 +OP4 ITRACE1 1 +OP4 ITRACE2 0 +OP4 ITRACE3 0 +OP4 ITRACE4 0 +OP4 ITRACE5 0 +OP4 ITRACE6 0 +OP4 ITRACE7 0 +OP4 Main_PhyUC 0 +OP4 E00009 0 +OP4 E0000A 0 +OP4 E0000B 0 +OP4 E0000C 0 +OP4 E0000D 0 +OP4 E0000E 0 +OP4 E0000F 0 +OP4 E00010 0 +OP4 E00011 0 +OP4 E00012 0 +OP4 E00013 0 +OP4 E00014 0 +OP4 E00015 0 +OP4 E00016 0 +OP4 E00017 0 +OP4 E00018 0 +OP4 E00019 0 +OP4 E0001A 0 +OP4 E0001B 0 +OP4 E0001C 0 +OP4 E0001D 0 +OP4 E0001E 0 +OP4 E0001F 0 +OP4 E00020 0 +OP4 E00021 0 +OP4 E00022 0 +OP4 E00023 0 +OP4 E00024 0 +OP4 E00025 0 +OP4 E00026 0 +OP4 E00027 0 +OP4 E00028 0 +OP4 E00029 0 +OP4 E0002A 0 +OP4 E0002B 0 +OP4 E0002C 0 +OP4 E0002D 0 +OP4 E0002E 0 +OP4 E0002F 0 +OP4 E00030 0 +OP4 E00031 0 +OP4 E00032 0 +OP4 E00033 0 +OP4 E00034 0 +OP4 E00035 0 +OP4 E00036 0 +OP4 E00037 0 +OP4 E00038 0 +OP4 E00039 0 +OP4 E0003A 0 +OP4 E0003B 0 +OP4 E0003C 0 +OP4 E0003D 0 +OP4 E0003E 0 +OP4 E0003F 0 +OP4 E00040 0 +OP4 E00041 0 +OP4 E00042 0 +OP4 E00043 0 +OP4 E00044 0 +OP4 E00045 0 +OP4 E00046 0 +OP4 E00047 0 +OP4 E00048 0 +OP4 E00049 0 +OP4 E0004A 0 +OP4 E0004B 0 +OP4 E0004C 0 +OP4 E0004D 0 +OP4 E0004E 0 +OP4 E0004F 0 +OP4 E00050 0 +OP4 E00051 0 +OP4 E00052 0 +OP4 E00053 0 +OP4 E00054 0 +OP4 E00055 0 +OP4 E00056 0 +OP4 E00057 0 +OP4 E00058 0 +OP4 E00059 0 +OP4 E0005A 0 +OP4 E0005B 0 +OP4 E0005C 0 +OP4 E0005D 0 +OP4 E0005E 0 +OP4 E0005F 0 +OP4 E00060 0 +OP4 E00061 0 +OP4 E00062 0 +OP4 E00063 0 +OP4 E00064 0 +OP4 E00065 0 +OP4 E00066 0 +OP4 E00067 0 +OP4 E00068 0 +OP4 E00069 0 +OP4 E0006A 0 +OP4 E0006B 0 +OP4 E0006C 0 +OP4 E0006D 0 +OP4 E0006E 0 +OP4 E0006F 0 +OP4 E00070 0 +OP4 E00071 0 +OP4 E00072 0 +OP4 E00073 0 +OP4 E00074 0 +OP4 E00075 0 +OP4 E00076 0 +OP4 E00077 0 +OP4 E00078 0 +OP4 E00079 0 +OP4 E0007A 0 +OP4 E0007B 0 +OP4 E0007C 0 +OP4 E0007D 0 +OP4 E0007E 0 +OP4 E0007F 0 +OP4 E00080 0 +OP4 E00081 0 +OP4 E00082 0 +OP4 E00083 0 +OP4 E00084 0 +OP4 E00085 0 +OP4 E00086 0 +OP4 E00087 0 +OP4 E00088 0 +OP4 E00089 0 +OP4 E0008A 0 +OP4 E0008B 0 +OP4 E0008C 0 +OP4 E0008D 0 +OP4 E0008E 0 +OP4 E0008F 0 +OP4 E00090 0 +OP4 E00091 0 +OP4 E00092 0 +OP4 E00093 0 +OP4 E00094 0 +OP4 E00095 0 +OP4 E00096 0 +OP4 E00097 0 +OP4 E00098 0 +OP4 E00099 0 +OP4 E0009A 0 +OP4 E0009B 0 +OP4 E0009C 0 +OP4 E0009D 0 +OP4 E0009E 0 +OP4 E0009F 0 +OP4 E000A0 0 +OP4 E000A1 0 +OP4 E000A2 0 +OP4 E000A3 0 +OP4 E000A4 0 +OP4 E000A5 0 +OP4 E000A6 0 +OP4 E000A7 0 +OP4 E000A8 0 +OP4 E000A9 0 +OP4 E000AA 0 +OP4 E000AB 0 +OP4 E000AC 0 +OP4 E000AD 0 +OP4 E000AE 0 +OP4 E000AF 0 +OP4 E000B0 0 +OP4 E000B1 0 +OP4 E000B2 0 +OP4 E000B3 0 +OP4 E000B4 0 +OP4 E000B5 0 +OP4 E000B6 0 +OP4 E000B7 0 +OP4 E000B8 0 +OP4 E000B9 0 +OP4 E000BA 0 +OP4 E000BB 0 +OP4 E000BC 0 +OP4 E000BD 0 +OP4 E000BE 0 +OP4 E000BF 0 +OP4 E000C0 0 +OP4 E000C1 0 +OP4 E000C2 0 +OP4 E000C3 0 +OP4 E000C4 0 +OP4 E000C5 0 +OP4 E000C6 0 +OP4 E000C7 0 +OP4 E000C8 0 +OP4 E000C9 0 +OP4 E000CA 0 +OP4 E000CB 0 +OP4 E000CC 0 +OP4 E000CD 0 +OP4 E000CE 0 +OP4 E000CF 0 +OP4 E000D0 0 +OP4 E000D1 0 +OP4 E000D2 0 +OP4 E000D3 0 +OP4 E000D4 0 +OP4 E000D5 0 +OP4 E000D6 0 +OP4 E000D7 0 +OP4 E000D8 0 +OP4 E000D9 0 +OP4 E000DA 0 +OP4 E000DB 0 +OP4 E000DC 0 +OP4 E000DD 0 +OP4 E000DE 0 +OP4 E000DF 0 +OP4 E000E0 0 +OP4 E000E1 0 +OP4 E000E2 0 +OP4 E000E3 0 +OP4 E000E4 0 +OP4 E000E5 0 +OP4 E000E6 0 +OP4 E000E7 0 +OP4 E000E8 0 +OP4 E000E9 0 +OP4 E000EA 0 +OP4 E000EB 0 +OP4 E000EC 0 +OP4 E000ED 0 +OP4 E000EE 0 +OP4 E000EF 0 +OP4 E000F0 0 +OP4 E000F1 0 +OP4 E000F2 0 +OP4 E000F3 0 +OP4 E000F4 0 +OP4 E000F5 0 +OP4 E000F6 0 +OP4 E000F7 0 +OP4 E000F8 0 +OP4 E000F9 0 +OP4 E000FA 0 +OP4 E000FB 0 +OP4 E000FC 0 +OP4 E000FD 0 +OP4 E000FE 0 +OP4 E000FF 0 +OP4 E00100 0 +OP4 E00101 0 +OP4 E00102 0 +OP4 E00103 0 +OP4 E00104 0 +OP4 E00105 0 +OP4 E00106 0 +OP4 E00107 0 +OP4 E00108 0 +OP4 E00109 0 +OP4 E0010A 0 +OP4 E0010B 0 +OP4 E0010C 0 +OP4 E0010D 0 +OP4 E0010E 0 +OP4 E0010F 0 +OP4 E00110 0 +OP4 E00111 0 +OP4 E00112 0 +OP4 E00113 0 +OP4 E00114 0 +OP4 E00115 0 +OP4 E00116 0 +OP4 E00117 0 +OP4 E00118 0 +OP4 E00119 0 +OP4 E0011A 0 +OP4 E0011B 0 +OP4 E0011C 0 +OP4 E0011D 0 +OP4 E0011E 0 +OP4 E0011F 0 +OP4 E00120 0 +OP4 E00121 0 +OP4 E00122 0 +OP4 E00123 0 +OP4 E00124 0 +OP4 E00125 0 +OP4 E00126 0 +OP4 E00127 0 +OP4 E00128 0 +OP4 E00129 0 +OP4 E0012A 0 +OP4 E0012B 0 +OP4 E0012C 0 +OP4 E0012D 0 +OP4 E0012E 0 +OP4 E0012F 0 +OP4 E00130 0 +OP4 E00131 0 +OP4 E00132 0 +OP4 E00133 0 +OP4 E00134 0 +OP4 E00135 0 +OP4 E00136 0 +OP4 E00137 0 +OP4 E00138 0 +OP4 E00139 0 +OP4 E0013A 0 +OP4 E0013B 0 +OP4 E0013C 0 +OP4 E0013D 0 +OP4 E0013E 0 +OP4 E0013F 0 +OP4 E00140 0 +OP4 E00141 0 +OP4 E00142 0 +OP4 E00143 0 +OP4 E00144 0 +OP4 E00145 0 +OP4 E00146 0 +OP4 E00147 0 +OP4 E00148 0 +OP4 E00149 0 +OP4 E0014A 0 +OP4 E0014B 0 +OP4 E0014C 0 +OP4 E0014D 0 +OP4 E0014E 0 +OP4 E0014F 0 +OP4 E00150 0 +OP4 E00151 0 +OP4 E00152 0 +OP4 E00153 0 +OP4 E00154 0 +OP4 E00155 0 +OP4 E00156 0 +OP4 E00157 0 +OP4 E00158 0 +OP4 E00159 0 +OP4 E0015A 0 +OP4 E0015B 0 +OP4 E0015C 0 +OP4 E0015D 0 +OP4 E0015E 0 +OP4 E0015F 0 +OP4 E00160 0 +OP4 E00161 0 +OP4 E00162 0 +OP4 E00163 0 +OP4 E00164 0 +OP4 E00165 0 +OP4 E00166 0 +OP4 E00167 0 +OP4 E00168 0 +OP4 E00169 0 +OP4 E0016A 0 +OP4 E0016B 0 +OP4 E0016C 0 +OP4 E0016D 0 +OP4 E0016E 0 +OP4 E0016F 0 +OP4 E00170 0 +OP4 E00171 0 +OP4 E00172 0 +OP4 E00173 0 +OP4 E00174 0 +OP4 E00175 0 +OP4 E00176 0 +OP4 E00177 0 +OP4 E00178 0 +OP4 E00179 0 +OP4 E0017A 0 +OP4 E0017B 0 +OP4 E0017C 0 +OP4 E0017D 0 +OP4 E0017E 0 +OP4 E0017F 0 +OP4 E00180 0 +OP4 E00181 0 +OP4 E00182 0 +OP4 E00183 0 +OP4 E00184 0 +OP4 E00185 0 +OP4 E00186 0 +OP4 E00187 0 +OP4 E00188 0 +OP4 E00189 0 +OP4 E0018A 0 +OP4 E0018B 0 +OP4 E0018C 0 +OP4 E0018D 0 +OP4 E0018E 0 +OP4 E0018F 0 +OP4 E00190 0 +OP4 E00191 0 +OP4 E00192 0 +OP4 E00193 0 +OP4 E00194 0 +OP4 E00195 0 +OP4 E00196 0 +OP4 E00197 0 +OP4 E00198 0 +OP4 E00199 0 +OP4 E0019A 0 +OP4 E0019B 0 +OP4 E0019C 0 +OP4 E0019D 0 +OP4 E0019E 0 +OP4 E0019F 0 +OP4 E001A0 0 +OP4 E001A1 0 +OP4 E001A2 0 +OP4 E001A3 0 +OP4 E001A4 0 +OP4 E001A5 0 +OP4 E001A6 0 +OP4 E001A7 0 +OP4 E001A8 0 +OP4 E001A9 0 +OP4 E001AA 0 +OP4 E001AB 0 +OP4 E001AC 0 +OP4 E001AD 0 +OP4 E001AE 0 +OP4 E001AF 0 +OP4 E001B0 0 +OP4 E001B1 0 +OP4 E001B2 0 +OP4 E001B3 0 +OP4 E001B4 0 +OP4 E001B5 0 +OP4 E001B6 0 +OP4 E001B7 0 +OP4 E001B8 0 +OP4 E001B9 0 +OP4 E001BA 0 +OP4 E001BB 0 +OP4 E001BC 0 +OP4 E001BD 0 +OP4 E001BE 0 +OP4 E001BF 0 +OP4 E001C0 0 +OP4 E001C1 0 +OP4 E001C2 0 +OP4 E001C3 0 +OP4 E001C4 0 +OP4 E001C5 0 +OP4 E001C6 0 +OP4 E001C7 0 +OP4 E001C8 0 +OP4 E001C9 0 +OP4 E001CA 0 +OP4 E001CB 0 +OP4 E001CC 0 +OP4 E001CD 0 +OP4 E001CE 0 +OP4 E001CF 0 +OP4 E001D0 0 +OP4 E001D1 0 +OP4 E001D2 0 +OP4 E001D3 0 +OP4 E001D4 0 +OP4 E001D5 0 +OP4 E001D6 0 +OP4 E001D7 0 +OP4 E001D8 0 +OP4 E001D9 0 +OP4 E001DA 0 +OP4 E001DB 0 +OP4 E001DC 0 +OP4 E001DD 0 +OP4 E001DE 0 +OP4 E001DF 0 +OP4 E001E0 0 +OP4 E001E1 0 +OP4 E001E2 0 +OP4 E001E3 0 +OP4 E001E4 0 +OP4 E001E5 0 +OP4 E001E6 0 +OP4 E001E7 0 +OP4 E001E8 0 +OP4 E001E9 0 +OP4 E001EA 0 +OP4 E001EB 0 +OP4 E001EC 0 +OP4 E001ED 0 +OP4 E001EE 0 +OP4 E001EF 0 +OP4 E001F0 0 +OP4 E001F1 0 +OP4 E001F2 0 +OP4 E001F3 0 +OP4 E001F4 0 +OP4 E001F5 0 +OP4 E001F6 0 +OP4 E001F7 0 +OP4 E001F8 0 +OP4 E001F9 0 +OP4 E001FA 0 +OP4 E001FB 0 +OP4 E001FC 0 +OP4 E001FD 0 +OP4 E001FE 0 +OP4 E001FF 0 +OP4 E00200 0 +OP4 E00201 0 +OP4 E00202 0 +OP4 E00203 0 +OP4 E00204 0 +OP4 E00205 0 +OP4 E00206 0 +OP4 E00207 0 +OP4 E00208 0 +OP4 E00209 0 +OP4 E0020A 0 +OP4 E0020B 0 +OP4 E0020C 0 +OP4 E0020D 0 +OP4 E0020E 0 +OP4 E0020F 0 +OP4 E00210 0 +OP4 E00211 0 +OP4 E00212 0 +OP4 E00213 0 +OP4 E00214 0 +OP4 E00215 0 +OP4 E00216 0 +OP4 E00217 0 +OP4 E00218 0 +OP4 E00219 0 +OP4 E0021A 0 +OP4 E0021B 0 +OP4 E0021C 0 +OP4 E0021D 0 +OP4 E0021E 0 +OP4 E0021F 0 +OP4 E00220 0 +OP4 E00221 0 +OP4 E00222 0 +OP4 E00223 0 +OP4 E00224 0 +OP4 E00225 0 +OP4 E00226 0 +OP4 E00227 0 +OP4 E00228 0 +OP4 E00229 0 +OP4 E0022A 0 +OP4 E0022B 0 +OP4 E0022C 0 +OP4 E0022D 0 +OP4 E0022E 0 +OP4 E0022F 0 +OP4 E00230 0 +OP4 E00231 0 +OP4 E00232 0 +OP4 E00233 0 +OP4 E00234 0 +OP4 E00235 0 +OP4 E00236 0 +OP4 E00237 0 +OP4 E00238 0 +OP4 E00239 0 +OP4 E0023A 0 +OP4 E0023B 0 +OP4 E0023C 0 +OP4 E0023D 0 +OP4 E0023E 0 +OP4 E0023F 0 +OP4 E00240 0 +OP4 E00241 0 +OP4 E00242 0 +OP4 E00243 0 +OP4 E00244 0 +OP4 E00245 0 +OP4 E00246 0 +OP4 E00247 0 +OP4 E00248 0 +OP4 E00249 0 +OP4 E0024A 0 +OP4 E0024B 0 +OP4 E0024C 0 +OP4 E0024D 0 +OP4 E0024E 0 +OP4 E0024F 0 +OP4 E00250 0 +OP4 E00251 0 +OP4 E00252 0 +OP4 E00253 0 +OP4 E00254 0 +OP4 E00255 0 +OP4 E00256 0 +OP4 E00257 0 +OP4 E00258 0 +OP4 E00259 0 +OP4 E0025A 0 +OP4 E0025B 0 +OP4 E0025C 0 +OP4 E0025D 0 +OP4 E0025E 0 +OP4 E0025F 0 +OP4 E00260 0 +OP4 E00261 0 +OP4 E00262 0 +OP4 E00263 0 +OP4 E00264 0 +OP4 E00265 0 +OP4 E00266 0 +OP4 E00267 0 +OP4 E00268 0 +OP4 E00269 0 +OP4 E0026A 0 +OP4 E0026B 0 +OP4 E0026C 0 +OP4 E0026D 0 +OP4 E0026E 0 +OP4 E0026F 0 +OP4 E00270 0 +OP4 E00271 0 +OP4 E00272 0 +OP4 E00273 0 +OP4 E00274 0 +OP4 E00275 0 +OP4 E00276 0 +OP4 E00277 0 +OP4 E00278 0 +OP4 E00279 0 +OP4 E0027A 0 +OP4 E0027B 0 +OP4 E0027C 0 +OP4 E0027D 0 +OP4 E0027E 0 +OP4 E0027F 0 +OP4 E00280 0 +OP4 E00281 0 +OP4 E00282 0 +OP4 E00283 0 +OP4 E00284 0 +OP4 E00285 0 +OP4 E00286 0 +OP4 E00287 0 +OP4 E00288 0 +OP4 E00289 0 +OP4 E0028A 0 +OP4 E0028B 0 +OP4 E0028C 0 +OP4 E0028D 0 +OP4 E0028E 0 +OP4 E0028F 0 +OP4 E00290 0 +OP4 E00291 0 +OP4 E00292 0 +OP4 E00293 0 +OP4 E00294 0 +OP4 E00295 0 +OP4 E00296 0 +OP4 E00297 0 +OP4 E00298 0 +OP4 E00299 0 +OP4 E0029A 0 +OP4 E0029B 0 +OP4 E0029C 0 +OP4 E0029D 0 +OP4 E0029E 0 +OP4 E0029F 0 +OP4 E002A0 0 +OP4 E002A1 0 +OP4 E002A2 0 +OP4 E002A3 0 +OP4 E002A4 0 +OP4 E002A5 0 +OP4 E002A6 0 +OP4 E002A7 0 +OP4 E002A8 0 +OP4 E002A9 0 +OP4 E002AA 0 +OP4 E002AB 0 +OP4 E002AC 0 +OP4 E002AD 0 +OP4 E002AE 0 +OP4 E002AF 0 +OP4 E002B0 0 +OP4 E002B1 0 +OP4 E002B2 0 +OP4 E002B3 0 +OP4 E002B4 0 +OP4 E002B5 0 +OP4 E002B6 0 +OP4 E002B7 0 +OP4 E002B8 0 +OP4 E002B9 0 +OP4 E002BA 0 +OP4 E002BB 0 +OP4 E002BC 0 +OP4 E002BD 0 +OP4 E002BE 0 +OP4 E002BF 0 +OP4 E002C0 0 +OP4 E002C1 0 +OP4 E002C2 0 +OP4 E002C3 0 +OP4 E002C4 0 +OP4 E002C5 0 +OP4 E002C6 0 +OP4 E002C7 0 +OP4 E002C8 0 +OP4 E002C9 0 +OP4 E002CA 0 +OP4 E002CB 0 +OP4 E002CC 0 +OP4 E002CD 0 +OP4 E002CE 0 +OP4 E002CF 0 +OP4 E002D0 0 +OP4 E002D1 0 +OP4 E002D2 0 +OP4 E002D3 0 +OP4 E002D4 0 +OP4 E002D5 0 +OP4 E002D6 0 +OP4 E002D7 0 +OP4 E002D8 0 +OP4 E002D9 0 +OP4 E002DA 0 +OP4 E002DB 0 +OP4 E002DC 0 +OP4 E002DD 0 +OP4 E002DE 0 +OP4 E002DF 0 +OP4 E002E0 0 +OP4 E002E1 0 +OP4 E002E2 0 +OP4 E002E3 0 +OP4 E002E4 0 +OP4 E002E5 0 +OP4 E002E6 0 +OP4 E002E7 0 +OP4 E002E8 0 +OP4 E002E9 0 +OP4 E002EA 0 +OP4 E002EB 0 +OP4 E002EC 0 +OP4 E002ED 0 +OP4 E002EE 0 +OP4 E002EF 0 +OP4 E002F0 0 +OP4 E002F1 0 +OP4 E002F2 0 +OP4 E002F3 0 +OP4 E002F4 0 +OP4 E002F5 0 +OP4 E002F6 0 +OP4 E002F7 0 +OP4 E002F8 0 +OP4 E002F9 0 +OP4 E002FA 0 +OP4 E002FB 0 +OP4 E002FC 0 +OP4 E002FD 0 +OP4 E002FE 0 +OP4 E002FF 0 +OP4 E00300 0 +OP4 E00301 0 +OP4 E00302 0 +OP4 E00303 0 +OP4 E00304 0 +OP4 E00305 0 +OP4 E00306 0 +OP4 E00307 0 +OP4 E00308 0 +OP4 E00309 0 +OP4 E0030A 0 +OP4 E0030B 0 +OP4 E0030C 0 +OP4 E0030D 0 +OP4 E0030E 0 +OP4 E0030F 0 +OP4 E00310 0 +OP4 E00311 0 +OP4 E00312 0 +OP4 E00313 0 +OP4 E00314 0 +OP4 E00315 0 +OP4 E00316 0 +OP4 E00317 0 +OP4 E00318 0 +OP4 E00319 0 +OP4 E0031A 0 +OP4 E0031B 0 +OP4 E0031C 0 +OP4 E0031D 0 +OP4 E0031E 0 +OP4 E0031F 0 +OP4 E00320 0 +OP4 E00321 0 +OP4 E00322 0 +OP4 E00323 0 +OP4 E00324 0 +OP4 E00325 0 +OP4 E00326 0 +OP4 E00327 0 +OP4 E00328 0 +OP4 E00329 0 +OP4 E0032A 0 +OP4 E0032B 0 +OP4 E0032C 0 +OP4 E0032D 0 +OP4 E0032E 0 +OP4 E0032F 0 +OP4 E00330 0 +OP4 E00331 0 +OP4 E00332 0 +OP4 E00333 0 +OP4 E00334 0 +OP4 E00335 0 +OP4 E00336 0 +OP4 E00337 0 +OP4 E00338 0 +OP4 E00339 0 +OP4 E0033A 0 +OP4 E0033B 0 +OP4 E0033C 0 +OP4 E0033D 0 +OP4 E0033E 0 +OP4 E0033F 0 +OP4 E00340 0 +OP4 E00341 0 +OP4 E00342 0 +OP4 E00343 0 +OP4 E00344 0 +OP4 E00345 0 +OP4 E00346 0 +OP4 E00347 0 +OP4 E00348 0 +OP4 E00349 0 +OP4 E0034A 0 +OP4 E0034B 0 +OP4 E0034C 0 +OP4 E0034D 0 +OP4 E0034E 0 +OP4 E0034F 0 +OP4 E00350 0 +OP4 E00351 0 +OP4 E00352 0 +OP4 E00353 0 +OP4 E00354 0 +OP4 E00355 0 +OP4 E00356 0 +OP4 E00357 0 +OP4 E00358 0 +OP4 E00359 0 +OP4 E0035A 0 +OP4 E0035B 0 +OP4 E0035C 0 +OP4 E0035D 0 +OP4 E0035E 0 +OP4 E0035F 0 +OP4 E00360 0 +OP4 E00361 0 +OP4 E00362 0 +OP4 E00363 0 +OP4 E00364 0 +OP4 E00365 0 +OP4 E00366 0 +OP4 E00367 0 +OP4 E00368 0 +OP4 E00369 0 +OP4 E0036A 0 +OP4 E0036B 0 +OP4 E0036C 0 +OP4 E0036D 0 +OP4 E0036E 0 +OP4 E0036F 0 +OP4 E00370 0 +OP4 E00371 0 +OP4 E00372 0 +OP4 E00373 0 +OP4 E00374 0 +OP4 E00375 0 +OP4 E00376 0 +OP4 E00377 0 +OP4 E00378 0 +OP4 E00379 0 +OP4 E0037A 0 +OP4 E0037B 0 +OP4 E0037C 0 +OP4 E0037D 0 +OP4 E0037E 0 +OP4 E0037F 0 +OP4 E00380 0 +OP4 E00381 0 +OP4 E00382 0 +OP4 E00383 0 +OP4 E00384 0 +OP4 E00385 0 +OP4 E00386 0 +OP4 E00387 0 +OP4 E00388 0 +OP4 E00389 0 +OP4 E0038A 0 +OP4 E0038B 0 +OP4 E0038C 0 +OP4 E0038D 0 +OP4 E0038E 0 +OP4 E0038F 0 +OP4 E00390 0 +OP4 E00391 0 +OP4 E00392 0 +OP4 E00393 0 +OP4 E00394 0 +OP4 E00395 0 +OP4 E00396 0 +OP4 E00397 0 +OP4 E00398 0 +OP4 E00399 0 +OP4 E0039A 0 +OP4 E0039B 0 +OP4 E0039C 0 +OP4 E0039D 0 +OP4 E0039E 0 +OP4 E0039F 0 +OP4 E003A0 0 +OP4 E003A1 0 +OP4 E003A2 0 +OP4 E003A3 0 +OP4 E003A4 0 +OP4 E003A5 0 +OP4 E003A6 0 +OP4 E003A7 0 +OP4 E003A8 0 +OP4 E003A9 0 +OP4 E003AA 0 +OP4 E003AB 0 +OP4 E003AC 0 +OP4 E003AD 0 +OP4 E003AE 0 +OP4 E003AF 0 +OP4 E003B0 0 +OP4 E003B1 0 +OP4 E003B2 0 +OP4 E003B3 0 +OP4 E003B4 0 +OP4 E003B5 0 +OP4 E003B6 0 +OP4 E003B7 0 +OP4 E003B8 0 +OP4 E003B9 0 +OP4 E003BA 0 +OP4 E003BB 0 +OP4 E003BC 0 +OP4 E003BD 0 +OP4 E003BE 0 +OP4 E003BF 0 +OP4 E003C0 0 +OP4 E003C1 0 +OP4 E003C2 0 +OP4 E003C3 0 +OP4 E003C4 0 +OP4 E003C5 0 +OP4 E003C6 0 +OP4 E003C7 0 +OP4 E003C8 0 +OP4 E003C9 0 +OP4 E003CA 0 +OP4 E003CB 0 +OP4 E003CC 0 +OP4 E003CD 0 +OP4 E003CE 0 +OP4 E003CF 0 +OP4 E003D0 0 +OP4 E003D1 0 +OP4 E003D2 0 +OP4 E003D3 0 +OP4 E003D4 0 +OP4 E003D5 0 +OP4 E003D6 0 +OP4 E003D7 0 +OP4 E003D8 0 +OP4 E003D9 0 +OP4 E003DA 0 +OP4 E003DB 0 +OP4 E003DC 0 +OP4 E003DD 0 +OP4 E003DE 0 +OP4 E003DF 0 +OP4 E003E0 0 +OP4 E003E1 0 +OP4 E003E2 0 +OP4 E003E3 0 +OP4 E003E4 0 +OP4 E003E5 0 +OP4 E003E6 0 +OP4 E003E7 0 +OP4 E003E8 0 +OP4 E003E9 0 +OP4 E003EA 0 +OP4 E003EB 0 +OP4 E003EC 0 +OP4 E003ED 0 +OP4 E003EE 0 +OP4 E003EF 0 +OP4 E003F0 0 +OP4 E003F1 0 +OP4 E003F2 0 +OP4 E003F3 0 +OP4 E003F4 0 +OP4 E003F5 0 +OP4 E003F6 0 +OP4 E003F7 0 +OP4 E003F8 0 +OP4 E003F9 0 +OP4 E003FA 0 +OP4 E003FB 0 +OP4 E003FC 0 +OP4 E003FD 0 +OP4 E003FE 0 +OP4 E003FF 0 +OP4 E00400 0 +OP4 E00401 0 +OP4 E00402 0 +OP4 E00403 0 +OP4 E00404 0 +OP4 E00405 0 +OP4 E00406 0 +OP4 E00407 0 +OP4 E00408 0 +OP4 E00409 0 +OP4 E0040A 0 +OP4 E0040B 0 +OP4 E0040C 0 +OP4 E0040D 0 +OP4 E0040E 0 +OP4 E0040F 0 +OP4 E00410 0 +OP4 E00411 0 +OP4 E00412 0 +OP4 E00413 0 +OP4 E00414 0 +OP4 E00415 0 +OP4 E00416 0 +OP4 E00417 0 +OP4 E00418 0 +OP4 E00419 0 +OP4 E0041A 0 +OP4 E0041B 0 +OP4 E0041C 0 +OP4 E0041D 0 +OP4 E0041E 0 +OP4 E0041F 0 +OP4 E00420 0 +OP4 E00421 0 +OP4 E00422 0 +OP4 E00423 0 +OP4 E00424 0 +OP4 E00425 0 +OP4 E00426 0 +OP4 E00427 0 +OP4 E00428 0 +OP4 E00429 0 +OP4 E0042A 0 +OP4 E0042B 0 +OP4 E0042C 0 +OP4 E0042D 0 +OP4 E0042E 0 +OP4 E0042F 0 +OP4 E00430 0 +OP4 E00431 0 +OP4 E00432 0 +OP4 E00433 0 +OP4 E00434 0 +OP4 E00435 0 +OP4 E00436 0 +OP4 E00437 0 +OP4 E00438 0 +OP4 E00439 0 +OP4 E0043A 0 +OP4 E0043B 0 +OP4 E0043C 0 +OP4 E0043D 0 +OP4 E0043E 0 +OP4 E0043F 0 +OP4 E00440 0 +OP4 E00441 0 +OP4 E00442 0 +OP4 E00443 0 +OP4 E00444 0 +OP4 E00445 0 +OP4 E00446 0 +OP4 E00447 0 +OP4 E00448 0 +OP4 E00449 0 +OP4 E0044A 0 +OP4 E0044B 0 +OP4 E0044C 0 +OP4 E0044D 0 +OP4 E0044E 0 +OP4 E0044F 0 +OP4 E00450 0 +OP4 E00451 0 +OP4 E00452 0 +OP4 E00453 0 +OP4 E00454 0 +OP4 E00455 0 +OP4 E00456 0 +OP4 E00457 0 +OP4 E00458 0 +OP4 E00459 0 +OP4 E0045A 0 +OP4 E0045B 0 +OP4 E0045C 0 +OP4 E0045D 0 +OP4 E0045E 0 +OP4 E0045F 0 +OP4 E00460 0 +OP4 E00461 0 +OP4 E00462 0 +OP4 E00463 0 +OP4 E00464 0 +OP4 E00465 0 +OP4 E00466 0 +OP4 E00467 0 +OP4 E00468 0 +OP4 E00469 0 +OP4 E0046A 0 +OP4 E0046B 0 +OP4 E0046C 0 +OP4 E0046D 0 +OP4 E0046E 0 +OP4 E0046F 0 +OP4 E00470 0 +OP4 E00471 0 +OP4 E00472 0 +OP4 E00473 0 +OP4 E00474 0 +OP4 E00475 0 +OP4 E00476 0 +OP4 E00477 0 +OP4 E00478 0 +OP4 E00479 0 +OP4 E0047A 0 +OP4 E0047B 0 +OP4 E0047C 0 +OP4 E0047D 0 +OP4 E0047E 0 +OP4 E0047F 0 +OP4 E00480 0 +OP4 E00481 0 +OP4 E00482 0 +OP4 E00483 0 +OP4 E00484 0 +OP4 E00485 0 +OP4 E00486 0 +OP4 E00487 0 +OP4 E00488 0 +OP4 E00489 0 +OP4 E0048A 0 +OP4 E0048B 0 +OP4 E0048C 0 +OP4 E0048D 0 +OP4 E0048E 0 +OP4 E0048F 0 +OP4 E00490 0 +OP4 E00491 0 +OP4 E00492 0 +OP4 E00493 0 +OP4 E00494 0 +OP4 E00495 0 +OP4 E00496 0 +OP4 E00497 0 +OP4 E00498 0 +OP4 E00499 0 +OP4 E0049A 0 +OP4 E0049B 0 +OP4 E0049C 0 +OP4 E0049D 0 +OP4 E0049E 0 +OP4 E0049F 0 +OP4 E004A0 0 +OP4 E004A1 0 +OP4 E004A2 0 +OP4 E004A3 0 +OP4 E004A4 0 +OP4 E004A5 0 +OP4 E004A6 0 +OP4 E004A7 0 +OP4 E004A8 0 +OP4 E004A9 0 +OP4 E004AA 0 +OP4 E004AB 0 +OP4 E004AC 0 +OP4 E004AD 0 +OP4 E004AE 0 +OP4 E004AF 0 +OP4 E004B0 0 +OP4 E004B1 0 +OP4 E004B2 0 +OP4 E004B3 0 +OP4 E004B4 0 +OP4 E004B5 0 +OP4 E004B6 0 +OP4 E004B7 0 +OP4 E004B8 0 +OP4 E004B9 0 +OP4 E004BA 0 +OP4 E004BB 0 +OP4 E004BC 0 +OP4 E004BD 0 +OP4 E004BE 0 +OP4 E004BF 0 +OP4 E004C0 0 +OP4 E004C1 0 +OP4 E004C2 0 +OP4 E004C3 0 +OP4 E004C4 0 +OP4 E004C5 0 +OP4 E004C6 0 +OP4 E004C7 0 +OP4 E004C8 0 +OP4 E004C9 0 +OP4 E004CA 0 +OP4 E004CB 0 +OP4 E004CC 0 +OP4 E004CD 0 +OP4 E004CE 0 +OP4 E004CF 0 +OP4 E004D0 0 +OP4 E004D1 0 +OP4 E004D2 0 +OP4 E004D3 0 +OP4 E004D4 0 +OP4 E004D5 0 +OP4 E004D6 0 +OP4 E004D7 0 +OP4 E004D8 0 +OP4 E004D9 0 +OP4 E004DA 0 +OP4 E004DB 0 +OP4 E004DC 0 +OP4 E004DD 0 +OP4 E004DE 0 +OP4 E004DF 0 +OP4 E004E0 0 +OP4 E004E1 0 +OP4 E004E2 0 +OP4 E004E3 0 +OP4 E004E4 0 +OP4 E004E5 0 +OP4 E004E6 0 +OP4 E004E7 0 +OP4 E004E8 0 +OP4 E004E9 0 +OP4 E004EA 0 +OP4 E004EB 0 +OP4 E004EC 0 +OP4 E004ED 0 +OP4 E004EE 0 +OP4 E004EF 0 +OP4 E004F0 0 +OP4 E004F1 0 +OP4 E004F2 0 +OP4 E004F3 0 +OP4 E004F4 0 +OP4 E004F5 0 +OP4 E004F6 0 +OP4 E004F7 0 +OP4 E004F8 0 +OP4 E004F9 0 +OP4 E004FA 0 +OP4 E004FB 0 +OP4 E004FC 0 +OP4 E004FD 0 +OP4 E004FE 0 +OP4 E004FF 0 +OP4 E00500 0 +OP4 E00501 0 +OP4 E00502 0 +OP4 E00503 0 +OP4 E00504 0 +OP4 E00505 0 +OP4 E00506 0 +OP4 E00507 0 +OP4 E00508 0 +OP4 E00509 0 +OP4 E0050A 0 +OP4 E0050B 0 +OP4 E0050C 0 +OP4 E0050D 0 +OP4 E0050E 0 +OP4 E0050F 0 +OP4 E00510 0 +OP4 E00511 0 +OP4 E00512 0 +OP4 E00513 0 +OP4 E00514 0 +OP4 E00515 0 +OP4 E00516 0 +OP4 E00517 0 +OP4 E00518 0 +OP4 E00519 0 +OP4 E0051A 0 +OP4 E0051B 0 +OP4 E0051C 0 +OP4 E0051D 0 +OP4 E0051E 0 +OP4 E0051F 0 +OP4 E00520 0 +OP4 E00521 0 +OP4 E00522 0 +OP4 E00523 0 +OP4 E00524 0 +OP4 E00525 0 +OP4 E00526 0 +OP4 E00527 0 +OP4 E00528 0 +OP4 E00529 0 +OP4 E0052A 0 +OP4 E0052B 0 +OP4 E0052C 0 +OP4 E0052D 0 +OP4 E0052E 0 +OP4 E0052F 0 +OP4 E00530 0 +OP4 E00531 0 +OP4 E00532 0 +OP4 E00533 0 +OP4 E00534 0 +OP4 E00535 0 +OP4 E00536 0 +OP4 E00537 0 +OP4 E00538 0 +OP4 E00539 0 +OP4 E0053A 0 +OP4 E0053B 0 +OP4 E0053C 0 +OP4 E0053D 0 +OP4 E0053E 0 +OP4 E0053F 0 +OP4 E00540 0 +OP4 E00541 0 +OP4 E00542 0 +OP4 E00543 0 +OP4 E00544 0 +OP4 E00545 0 +OP4 E00546 0 +OP4 E00547 0 +OP4 E00548 0 +OP4 E00549 0 +OP4 E0054A 0 +OP4 E0054B 0 +OP4 E0054C 0 +OP4 E0054D 0 +OP4 E0054E 0 +OP4 E0054F 0 +OP4 E00550 0 +OP4 E00551 0 +OP4 E00552 0 +OP4 E00553 0 +OP4 E00554 0 +OP4 E00555 0 +OP4 E00556 0 +OP4 E00557 0 +OP4 E00558 0 +OP4 E00559 0 +OP4 E0055A 0 +OP4 E0055B 0 +OP4 E0055C 0 +OP4 E0055D 0 +OP4 E0055E 0 +OP4 E0055F 0 +OP4 E00560 0 +OP4 E00561 0 +OP4 E00562 0 +OP4 E00563 0 +OP4 E00564 0 +OP4 E00565 0 +OP4 E00566 0 +OP4 E00567 0 +OP4 E00568 0 +OP4 E00569 0 +OP4 E0056A 0 +OP4 E0056B 0 +OP4 E0056C 0 +OP4 E0056D 0 +OP4 E0056E 0 +OP4 E0056F 0 +OP4 E00570 0 +OP4 E00571 0 +OP4 E00572 0 +OP4 E00573 0 +OP4 E00574 0 +OP4 E00575 0 +OP4 E00576 0 +OP4 E00577 0 +OP4 E00578 0 +OP4 E00579 0 +OP4 E0057A 0 +OP4 E0057B 0 +OP4 E0057C 0 +OP4 E0057D 0 +OP4 E0057E 0 +OP4 E0057F 0 +OP4 E00580 0 +OP4 E00581 0 +OP4 E00582 0 +OP4 E00583 0 +OP4 E00584 0 +OP4 E00585 0 +OP4 E00586 0 +OP4 E00587 0 +OP4 E00588 0 +OP4 E00589 0 +OP4 E0058A 0 +OP4 E0058B 0 +OP4 E0058C 0 +OP4 E0058D 0 +OP4 E0058E 0 +OP4 E0058F 0 +OP4 E00590 0 +OP4 E00591 0 +OP4 E00592 0 +OP4 E00593 0 +OP4 E00594 0 +OP4 E00595 0 +OP4 E00596 0 +OP4 E00597 0 +OP4 E00598 0 +OP4 E00599 0 +OP4 E0059A 0 +OP4 E0059B 0 +OP4 E0059C 0 +OP4 E0059D 0 +OP4 E0059E 0 +OP4 E0059F 0 +OP4 E005A0 0 +OP4 E005A1 0 +OP4 E005A2 0 +OP4 E005A3 0 +OP4 E005A4 0 +OP4 E005A5 0 +OP4 E005A6 0 +OP4 E005A7 0 +OP4 E005A8 0 +OP4 E005A9 0 +OP4 E005AA 0 +OP4 E005AB 0 +OP4 E005AC 0 +OP4 E005AD 0 +OP4 E005AE 0 +OP4 E005AF 0 +OP4 E005B0 0 +OP4 E005B1 0 +OP4 E005B2 0 +OP4 E005B3 0 +OP4 E005B4 0 +OP4 E005B5 0 +OP4 E005B6 0 +OP4 E005B7 0 +OP4 E005B8 0 +OP4 E005B9 0 +OP4 E005BA 0 +OP4 E005BB 0 +OP4 E005BC 0 +OP4 E005BD 0 +OP4 E005BE 0 +OP4 E005BF 0 +OP4 E005C0 0 +OP4 E005C1 0 +OP4 E005C2 0 +OP4 E005C3 0 +OP4 E005C4 0 +OP4 E005C5 0 +OP4 E005C6 0 +OP4 E005C7 0 +OP4 E005C8 0 +OP4 E005C9 0 +OP4 E005CA 0 +OP4 E005CB 0 +OP4 E005CC 0 +OP4 E005CD 0 +OP4 E005CE 0 +OP4 E005CF 0 +OP4 E005D0 0 +OP4 E005D1 0 +OP4 E005D2 0 +OP4 E005D3 0 +OP4 E005D4 0 +OP4 E005D5 0 +OP4 E005D6 0 +OP4 E005D7 0 +OP4 E005D8 0 +OP4 E005D9 0 +OP4 E005DA 0 +OP4 E005DB 0 +OP4 E005DC 0 +OP4 E005DD 0 +OP4 E005DE 0 +OP4 E005DF 0 +OP4 E005E0 0 +OP4 E005E1 0 +OP4 E005E2 0 +OP4 E005E3 0 +OP4 E005E4 0 +OP4 E005E5 0 +OP4 E005E6 0 +OP4 E005E7 0 +OP4 E005E8 0 +OP4 E005E9 0 +OP4 E005EA 0 +OP4 E005EB 0 +OP4 E005EC 0 +OP4 E005ED 0 +OP4 E005EE 0 +OP4 E005EF 0 +OP4 E005F0 0 +OP4 E005F1 0 +OP4 E005F2 0 +OP4 E005F3 0 +OP4 E005F4 0 +OP4 E005F5 0 +OP4 E005F6 0 +OP4 E005F7 0 +OP4 E005F8 0 +OP4 E005F9 0 +OP4 E005FA 0 +OP4 E005FB 0 +OP4 E005FC 0 +OP4 E005FD 0 +OP4 E005FE 0 +OP4 E005FF 0 +OP4 E00600 0 +OP4 E00601 0 +OP4 E00602 0 +OP4 E00603 0 +OP4 E00604 0 +OP4 E00605 0 +OP4 E00606 0 +OP4 E00607 0 +OP4 E00608 0 +OP4 E00609 0 +OP4 E0060A 0 +OP4 E0060B 0 +OP4 E0060C 0 +OP4 E0060D 0 +OP4 E0060E 0 +OP4 E0060F 0 +OP4 E00610 0 +OP4 E00611 0 +OP4 E00612 0 +OP4 E00613 0 +OP4 E00614 0 +OP4 E00615 0 +OP4 E00616 0 +OP4 E00617 0 +OP4 E00618 0 +OP4 E00619 0 +OP4 E0061A 0 +OP4 E0061B 0 +OP4 E0061C 0 +OP4 E0061D 0 +OP4 E0061E 0 +OP4 E0061F 0 +OP4 E00620 0 +OP4 E00621 0 +OP4 E00622 0 +OP4 E00623 0 +OP4 E00624 0 +OP4 E00625 0 +OP4 E00626 0 +OP4 E00627 0 +OP4 E00628 0 +OP4 E00629 0 +OP4 E0062A 0 +OP4 E0062B 0 +OP4 E0062C 0 +OP4 E0062D 0 +OP4 E0062E 0 +OP4 E0062F 0 +OP4 E00630 0 +OP4 E00631 0 +OP4 E00632 0 +OP4 E00633 0 +OP4 E00634 0 +OP4 E00635 0 +OP4 E00636 0 +OP4 E00637 0 +OP4 E00638 0 +OP4 E00639 0 +OP4 E0063A 0 +OP4 E0063B 0 +OP4 E0063C 0 +OP4 E0063D 0 +OP4 E0063E 0 +OP4 E0063F 0 +OP4 E00640 0 +OP4 E00641 0 +OP4 E00642 0 +OP4 E00643 0 +OP4 E00644 0 +OP4 E00645 0 +OP4 E00646 0 +OP4 E00647 0 +OP4 E00648 0 +OP4 E00649 0 +OP4 E0064A 0 +OP4 E0064B 0 +OP4 E0064C 0 +OP4 E0064D 0 +OP4 E0064E 0 +OP4 E0064F 0 +OP4 E00650 0 +OP4 E00651 0 +OP4 E00652 0 +OP4 E00653 0 +OP4 E00654 0 +OP4 E00655 0 +OP4 E00656 0 +OP4 E00657 0 +OP4 E00658 0 +OP4 E00659 0 +OP4 E0065A 0 +OP4 E0065B 0 +OP4 E0065C 0 +OP4 E0065D 0 +OP4 E0065E 0 +OP4 E0065F 0 +OP4 E00660 0 +OP4 E00661 0 +OP4 E00662 0 +OP4 E00663 0 +OP4 E00664 0 +OP4 E00665 0 +OP4 E00666 0 +OP4 E00667 0 +OP4 E00668 0 +OP4 E00669 0 +OP4 E0066A 0 +OP4 E0066B 0 +OP4 E0066C 0 +OP4 E0066D 0 +OP4 E0066E 0 +OP4 E0066F 0 +OP4 E00670 0 +OP4 E00671 0 +OP4 E00672 0 +OP4 E00673 0 +OP4 E00674 0 +OP4 E00675 0 +OP4 E00676 0 +OP4 E00677 0 +OP4 E00678 0 +OP4 E00679 0 +OP4 E0067A 0 +OP4 E0067B 0 +OP4 E0067C 0 +OP4 E0067D 0 +OP4 E0067E 0 +OP4 E0067F 0 +OP4 E00680 0 +OP4 E00681 0 +OP4 E00682 0 +OP4 E00683 0 +OP4 E00684 0 +OP4 E00685 0 +OP4 E00686 0 +OP4 E00687 0 +OP4 E00688 0 +OP4 E00689 0 +OP4 E0068A 0 +OP4 E0068B 0 +OP4 E0068C 0 +OP4 E0068D 0 +OP4 E0068E 0 +OP4 E0068F 0 +OP4 E00690 0 +OP4 E00691 0 +OP4 E00692 0 +OP4 E00693 0 +OP4 E00694 0 +OP4 E00695 0 +OP4 E00696 0 +OP4 E00697 0 +OP4 E00698 0 +OP4 E00699 0 +OP4 E0069A 0 +OP4 E0069B 0 +OP4 E0069C 0 +OP4 E0069D 0 +OP4 E0069E 0 +OP4 E0069F 0 +OP4 E006A0 0 +OP4 E006A1 0 +OP4 E006A2 0 +OP4 E006A3 0 +OP4 E006A4 0 +OP4 E006A5 0 +OP4 E006A6 0 +OP4 E006A7 0 +OP4 E006A8 0 +OP4 E006A9 0 +OP4 E006AA 0 +OP4 E006AB 0 +OP4 E006AC 0 +OP4 E006AD 0 +OP4 E006AE 0 +OP4 E006AF 0 +OP4 E006B0 0 +OP4 E006B1 0 +OP4 E006B2 0 +OP4 E006B3 0 +OP4 E006B4 0 +OP4 E006B5 0 +OP4 E006B6 0 +OP4 E006B7 0 +OP4 E006B8 0 +OP4 E006B9 0 +OP4 E006BA 0 +OP4 E006BB 0 +OP4 E006BC 0 +OP4 E006BD 0 +OP4 E006BE 0 +OP4 E006BF 0 +OP4 E006C0 0 +OP4 E006C1 0 +OP4 E006C2 0 +OP4 E006C3 0 +OP4 E006C4 0 +OP4 E006C5 0 +OP4 E006C6 0 +OP4 E006C7 0 +OP4 E006C8 0 +OP4 E006C9 0 +OP4 E006CA 0 +OP4 E006CB 0 +OP4 E006CC 0 +OP4 E006CD 0 +OP4 E006CE 0 +OP4 E006CF 0 +OP4 E006D0 0 +OP4 E006D1 0 +OP4 E006D2 0 +OP4 E006D3 0 +OP4 E006D4 0 +OP4 E006D5 0 +OP4 E006D6 0 +OP4 E006D7 0 +OP4 E006D8 0 +OP4 E006D9 0 +OP4 E006DA 0 +OP4 E006DB 0 +OP4 E006DC 0 +OP4 E006DD 0 +OP4 E006DE 0 +OP4 E006DF 0 +OP4 E006E0 0 +OP4 E006E1 0 +OP4 E006E2 0 +OP4 E006E3 0 +OP4 E006E4 0 +OP4 E006E5 0 +OP4 E006E6 0 +OP4 E006E7 0 +OP4 E006E8 0 +OP4 E006E9 0 +OP4 E006EA 0 +OP4 E006EB 0 +OP4 E006EC 0 +OP4 E006ED 0 +OP4 E006EE 0 +OP4 E006EF 0 +OP4 E006F0 0 +OP4 E006F1 0 +OP4 E006F2 0 +OP4 E006F3 0 +OP4 E006F4 0 +OP4 E006F5 0 +OP4 E006F6 0 +OP4 E006F7 0 +OP4 E006F8 0 +OP4 E006F9 0 +OP4 E006FA 0 +OP4 E006FB 0 +OP4 E006FC 0 +OP4 E006FD 0 +OP4 E006FE 0 +OP4 E006FF 0 +OP4 E00700 0 +OP4 E00701 0 +OP4 E00702 0 +OP4 E00703 0 +OP4 E00704 0 +OP4 E00705 0 +OP4 E00706 0 +OP4 E00707 0 +OP4 E00708 0 +OP4 E00709 0 +OP4 E0070A 0 +OP4 E0070B 0 +OP4 E0070C 0 +OP4 E0070D 0 +OP4 E0070E 0 +OP4 E0070F 0 +OP4 E00710 0 +OP4 E00711 0 +OP4 E00712 0 +OP4 E00713 0 +OP4 E00714 0 +OP4 E00715 0 +OP4 E00716 0 +OP4 E00717 0 +OP4 E00718 0 +OP4 E00719 0 +OP4 E0071A 0 +OP4 E0071B 0 +OP4 E0071C 0 +OP4 E0071D 0 +OP4 E0071E 0 +OP4 E0071F 0 +OP4 E00720 0 +OP4 E00721 0 +OP4 E00722 0 +OP4 E00723 0 +OP4 E00724 0 +OP4 E00725 0 +OP4 E00726 0 +OP4 E00727 0 +OP4 E00728 0 +OP4 E00729 0 +OP4 E0072A 0 +OP4 E0072B 0 +OP4 E0072C 0 +OP4 E0072D 0 +OP4 E0072E 0 +OP4 E0072F 0 +OP4 E00730 0 +OP4 E00731 0 +OP4 E00732 0 +OP4 E00733 0 +OP4 E00734 0 +OP4 E00735 0 +OP4 E00736 0 +OP4 E00737 0 +OP4 E00738 0 +OP4 E00739 0 +OP4 E0073A 0 +OP4 E0073B 0 +OP4 E0073C 0 +OP4 E0073D 0 +OP4 E0073E 0 +OP4 E0073F 0 +OP4 E00740 0 +OP4 E00741 0 +OP4 E00742 0 +OP4 E00743 0 +OP4 E00744 0 +OP4 E00745 0 +OP4 E00746 0 +OP4 E00747 0 +OP4 E00748 0 +OP4 E00749 0 +OP4 E0074A 0 +OP4 E0074B 0 +OP4 E0074C 0 +OP4 E0074D 0 +OP4 E0074E 0 +OP4 E0074F 0 +OP4 E00750 0 +OP4 E00751 0 +OP4 E00752 0 +OP4 E00753 0 +OP4 E00754 0 +OP4 E00755 0 +OP4 E00756 0 +OP4 E00757 0 +OP4 E00758 0 +OP4 E00759 0 +OP4 E0075A 0 +OP4 E0075B 0 +OP4 E0075C 0 +OP4 E0075D 0 +OP4 E0075E 0 +OP4 E0075F 0 +OP4 E00760 0 +OP4 E00761 0 +OP4 E00762 0 +OP4 E00763 0 +OP4 E00764 0 +OP4 E00765 0 +OP4 E00766 0 +OP4 E00767 0 +OP4 E00768 0 +OP4 E00769 0 +OP4 E0076A 0 +OP4 E0076B 0 +OP4 E0076C 0 +OP4 E0076D 0 +OP4 E0076E 0 +OP4 E0076F 0 +OP4 E00770 0 +OP4 E00771 0 +OP4 E00772 0 +OP4 E00773 0 +OP4 E00774 0 +OP4 E00775 0 +OP4 E00776 0 +OP4 E00777 0 +OP4 E00778 0 +OP4 E00779 0 +OP4 E0077A 0 +OP4 E0077B 0 +OP4 E0077C 0 +OP4 E0077D 0 +OP4 E0077E 0 +OP4 E0077F 0 +OP4 E00780 0 +OP4 E00781 0 +OP4 E00782 0 +OP4 E00783 0 +OP4 E00784 0 +OP4 E00785 0 +OP4 E00786 0 +OP4 E00787 0 +OP4 E00788 0 +OP4 E00789 0 +OP4 E0078A 0 +OP4 E0078B 0 +OP4 E0078C 0 +OP4 E0078D 0 +OP4 E0078E 0 +OP4 E0078F 0 +OP4 E00790 0 +OP4 E00791 0 +OP4 E00792 0 +OP4 E00793 0 +OP4 E00794 0 +OP4 E00795 0 +OP4 E00796 0 +OP4 E00797 0 +OP4 E00798 0 +OP4 E00799 0 +OP4 E0079A 0 +OP4 E0079B 0 +OP4 E0079C 0 +OP4 E0079D 0 +OP4 E0079E 0 +OP4 E0079F 0 +OP4 E007A0 0 +OP4 E007A1 0 +OP4 E007A2 0 +OP4 E007A3 0 +OP4 E007A4 0 +OP4 E007A5 0 +OP4 E007A6 0 +OP4 E007A7 0 +OP4 E007A8 0 +OP4 E007A9 0 +OP4 E007AA 0 +OP4 E007AB 0 +OP4 E007AC 0 +OP4 E007AD 0 +OP4 E007AE 0 +OP4 E007AF 0 +OP4 E007B0 0 +OP4 E007B1 0 +OP4 E007B2 0 +OP4 E007B3 0 +OP4 E007B4 0 +OP4 E007B5 0 +OP4 E007B6 0 +OP4 E007B7 0 +OP4 E007B8 0 +OP4 E007B9 0 +OP4 E007BA 0 +OP4 E007BB 0 +OP4 E007BC 0 +OP4 E007BD 0 +OP4 E007BE 0 +OP4 E007BF 0 +OP4 E007C0 0 +OP4 E007C1 0 +OP4 E007C2 0 +OP4 E007C3 0 +OP4 E007C4 0 +OP4 E007C5 0 +OP4 E007C6 0 +OP4 E007C7 0 +OP4 E007C8 0 +OP4 E007C9 0 +OP4 E007CA 0 +OP4 E007CB 0 +OP4 E007CC 0 +OP4 E007CD 0 +OP4 E007CE 0 +OP4 E007CF 0 +OP4 E007D0 0 +OP4 E007D1 0 +OP4 E007D2 0 +OP4 E007D3 0 +OP4 E007D4 0 +OP4 E007D5 0 +OP4 E007D6 0 +OP4 E007D7 0 +OP4 E007D8 0 +OP4 E007D9 0 +OP4 E007DA 0 +OP4 E007DB 0 +OP4 E007DC 0 +OP4 E007DD 0 +OP4 E007DE 0 +OP4 E007DF 0 +OP4 E007E0 0 +OP4 E007E1 0 +OP4 E007E2 0 +OP4 E007E3 0 +OP4 E007E4 0 +OP4 E007E5 0 +OP4 E007E6 0 +OP4 E007E7 0 +OP4 E007E8 0 +OP4 E007E9 0 +OP4 E007EA 0 +OP4 E007EB 0 +OP4 E007EC 0 +OP4 E007ED 0 +OP4 E007EE 0 +OP4 E007EF 0 +OP4 E007F0 0 +OP4 E007F1 0 +OP4 E007F2 0 +OP4 E007F3 0 +OP4 E007F4 0 +OP4 E007F5 0 +OP4 E007F6 0 +OP4 E007F7 0 +OP4 E007F8 0 +OP4 E007F9 0 +OP4 E007FA 0 +OP4 E007FB 0 +OP4 E007FC 0 +OP4 E007FD 0 +OP4 E007FE 0 +OP4 E007FF 0 +OP4 E00800 0 +OP4 E00801 0 +OP4 E00802 0 +OP4 E00803 0 +OP4 E00804 0 +OP4 E00805 0 +OP4 E00806 0 +OP4 E00807 0 +OP4 E00808 0 +OP4 E00809 0 +OP4 E0080A 0 +OP4 E0080B 0 +OP4 E0080C 0 +OP4 E0080D 0 +OP4 E0080E 0 +OP4 E0080F 0 +OP4 E00810 0 +OP4 E00811 0 +OP4 E00812 0 +OP4 E00813 0 +OP4 E00814 0 +OP4 E00815 0 +OP4 E00816 0 +OP4 E00817 0 +OP4 E00818 0 +OP4 E00819 0 +OP4 E0081A 0 +OP4 E0081B 0 +OP4 E0081C 0 +OP4 E0081D 0 +OP4 E0081E 0 +OP4 E0081F 0 +OP4 E00820 0 +OP4 E00821 0 +OP4 E00822 0 +OP4 E00823 0 +OP4 E00824 0 +OP4 E00825 0 +OP4 E00826 0 +OP4 E00827 0 +OP4 E00828 0 +OP4 E00829 0 +OP4 E0082A 0 +OP4 E0082B 0 +OP4 E0082C 0 +OP4 E0082D 0 +OP4 E0082E 0 +OP4 E0082F 0 +OP4 E00830 0 +OP4 E00831 0 +OP4 E00832 0 +OP4 E00833 0 +OP4 E00834 0 +OP4 E00835 0 +OP4 E00836 0 +OP4 E00837 0 +OP4 E00838 0 +OP4 E00839 0 +OP4 E0083A 0 +OP4 E0083B 0 +OP4 E0083C 0 +OP4 E0083D 0 +OP4 E0083E 0 +OP4 E0083F 0 +OP4 E00840 0 +OP4 E00841 0 +OP4 E00842 0 +OP4 E00843 0 +OP4 E00844 0 +OP4 E00845 0 +OP4 E00846 0 +OP4 E00847 0 +OP4 E00848 0 +OP4 E00849 0 +OP4 E0084A 0 +OP4 E0084B 0 +OP4 E0084C 0 +OP4 E0084D 0 +OP4 E0084E 0 +OP4 E0084F 0 +OP4 E00850 0 +OP4 E00851 0 +OP4 E00852 0 +OP4 E00853 0 +OP4 E00854 0 +OP4 E00855 0 +OP4 E00856 0 +OP4 E00857 0 +OP4 E00858 0 +OP4 E00859 0 +OP4 E0085A 0 +OP4 E0085B 0 +OP4 E0085C 0 +OP4 E0085D 0 +OP4 E0085E 0 +OP4 E0085F 0 +OP4 E00860 0 +OP4 E00861 0 +OP4 E00862 0 +OP4 E00863 0 +OP4 E00864 0 +OP4 E00865 0 +OP4 E00866 0 +OP4 E00867 0 +OP4 E00868 0 +OP4 E00869 0 +OP4 E0086A 0 +OP4 E0086B 0 +OP4 E0086C 0 +OP4 E0086D 0 +OP4 E0086E 0 +OP4 E0086F 0 +OP4 E00870 0 +OP4 E00871 0 +OP4 E00872 0 +OP4 E00873 0 +OP4 E00874 0 +OP4 E00875 0 +OP4 E00876 0 +OP4 E00877 0 +OP4 E00878 0 +OP4 E00879 0 +OP4 E0087A 0 +OP4 E0087B 0 +OP4 E0087C 0 +OP4 E0087D 0 +OP4 E0087E 0 +OP4 E0087F 0 +OP4 E00880 0 +OP4 E00881 0 +OP4 E00882 0 +OP4 E00883 0 +OP4 E00884 0 +OP4 E00885 0 +OP4 E00886 0 +OP4 E00887 0 +OP4 E00888 0 +OP4 E00889 0 +OP4 E0088A 0 +OP4 E0088B 0 +OP4 E0088C 0 +OP4 E0088D 0 +OP4 E0088E 0 +OP4 E0088F 0 +OP4 E00890 0 +OP4 E00891 0 +OP4 E00892 0 +OP4 E00893 0 +OP4 E00894 0 +OP4 E00895 0 +OP4 E00896 0 +OP4 E00897 0 +OP4 E00898 0 +OP4 E00899 0 +OP4 E0089A 0 +OP4 E0089B 0 +OP4 E0089C 0 +OP4 E0089D 0 +OP4 E0089E 0 +OP4 E0089F 0 +OP4 E008A0 0 +OP4 E008A1 0 +OP4 E008A2 0 +OP4 E008A3 0 +OP4 E008A4 0 +OP4 E008A5 0 +OP4 E008A6 0 +OP4 E008A7 0 +OP4 E008A8 0 +OP4 E008A9 0 +OP4 E008AA 0 +OP4 E008AB 0 +OP4 E008AC 0 +OP4 E008AD 0 +OP4 E008AE 0 +OP4 E008AF 0 +OP4 E008B0 0 +OP4 E008B1 0 +OP4 E008B2 0 +OP4 E008B3 0 +OP4 E008B4 0 +OP4 E008B5 0 +OP4 E008B6 0 +OP4 E008B7 0 +OP4 E008B8 0 +OP4 E008B9 0 +OP4 E008BA 0 +OP4 E008BB 0 +OP4 E008BC 0 +OP4 E008BD 0 +OP4 E008BE 0 +OP4 E008BF 0 +OP4 E008C0 0 +OP4 E008C1 0 +OP4 E008C2 0 +OP4 E008C3 0 +OP4 E008C4 0 +OP4 E008C5 0 +OP4 E008C6 0 +OP4 E008C7 0 +OP4 E008C8 0 +OP4 E008C9 0 +OP4 E008CA 0 +OP4 E008CB 0 +OP4 E008CC 0 +OP4 E008CD 0 +OP4 E008CE 0 +OP4 E008CF 0 +OP4 E008D0 0 +OP4 E008D1 0 +OP4 E008D2 0 +OP4 E008D3 0 +OP4 E008D4 0 +OP4 E008D5 0 +OP4 E008D6 0 +OP4 E008D7 0 +OP4 E008D8 0 +OP4 E008D9 0 +OP4 E008DA 0 +OP4 E008DB 0 +OP4 E008DC 0 +OP4 E008DD 0 +OP4 E008DE 0 +OP4 E008DF 0 +OP4 E008E0 0 +OP4 E008E1 0 +OP4 E008E2 0 +OP4 E008E3 0 +OP4 E008E4 0 +OP4 E008E5 0 +OP4 E008E6 0 +OP4 E008E7 0 +OP4 E008E8 0 +OP4 E008E9 0 +OP4 E008EA 0 +OP4 E008EB 0 +OP4 E008EC 0 +OP4 E008ED 0 +OP4 E008EE 0 +OP4 E008EF 0 +OP4 E008F0 0 +OP4 E008F1 0 +OP4 E008F2 0 +OP4 E008F3 0 +OP4 E008F4 0 +OP4 E008F5 0 +OP4 E008F6 0 +OP4 E008F7 0 +OP4 E008F8 0 +OP4 E008F9 0 +OP4 E008FA 0 +OP4 E008FB 0 +OP4 E008FC 0 +OP4 E008FD 0 +OP4 E008FE 0 +OP4 E008FF 0 +OP4 E00900 0 +OP4 E00901 0 +OP4 E00902 0 +OP4 E00903 0 +OP4 E00904 0 +OP4 E00905 0 +OP4 E00906 0 +OP4 E00907 0 +OP4 E00908 0 +OP4 E00909 0 +OP4 E0090A 0 +OP4 E0090B 0 +OP4 E0090C 0 +OP4 E0090D 0 +OP4 E0090E 0 +OP4 E0090F 0 +OP4 E00910 0 +OP4 E00911 0 +OP4 E00912 0 +OP4 E00913 0 +OP4 E00914 0 +OP4 E00915 0 +OP4 E00916 0 +OP4 E00917 0 +OP4 E00918 0 +OP4 E00919 0 +OP4 E0091A 0 +OP4 E0091B 0 +OP4 E0091C 0 +OP4 E0091D 0 +OP4 E0091E 0 +OP4 E0091F 0 +OP4 E00920 0 +OP4 E00921 0 +OP4 E00922 0 +OP4 E00923 0 +OP4 E00924 0 +OP4 E00925 0 +OP4 E00926 0 +OP4 E00927 0 +OP4 E00928 0 +OP4 E00929 0 +OP4 E0092A 0 +OP4 E0092B 0 +OP4 E0092C 0 +OP4 E0092D 0 +OP4 E0092E 0 +OP4 E0092F 0 +OP4 E00930 0 +OP4 E00931 0 +OP4 E00932 0 +OP4 E00933 0 +OP4 E00934 0 +OP4 E00935 0 +OP4 E00936 0 +OP4 E00937 0 +OP4 E00938 0 +OP4 E00939 0 +OP4 E0093A 0 +OP4 E0093B 0 +OP4 E0093C 0 +OP4 E0093D 0 +OP4 E0093E 0 +OP4 E0093F 0 +OP4 E00940 0 +OP4 E00941 0 +OP4 E00942 0 +OP4 E00943 0 +OP4 E00944 0 +OP4 E00945 0 +OP4 E00946 0 +OP4 E00947 0 +OP4 E00948 0 +OP4 E00949 0 +OP4 E0094A 0 +OP4 E0094B 0 +OP4 E0094C 0 +OP4 E0094D 0 +OP4 E0094E 0 +OP4 E0094F 0 +OP4 E00950 0 +OP4 E00951 0 +OP4 E00952 0 +OP4 E00953 0 +OP4 E00954 0 +OP4 E00955 0 +OP4 E00956 0 +OP4 E00957 0 +OP4 E00958 0 +OP4 E00959 0 +OP4 E0095A 0 +OP4 E0095B 0 +OP4 E0095C 0 +OP4 E0095D 0 +OP4 E0095E 0 +OP4 E0095F 0 +OP4 E00960 0 +OP4 E00961 0 +OP4 E00962 0 +OP4 E00963 0 +OP4 E00964 0 +OP4 E00965 0 +OP4 E00966 0 +OP4 E00967 0 +OP4 E00968 0 +OP4 E00969 0 +OP4 E0096A 0 +OP4 E0096B 0 +OP4 E0096C 0 +OP4 E0096D 0 +OP4 E0096E 0 +OP4 E0096F 0 +OP4 E00970 0 +OP4 E00971 0 +OP4 E00972 0 +OP4 E00973 0 +OP4 E00974 0 +OP4 E00975 0 +OP4 E00976 0 +OP4 E00977 0 +OP4 E00978 0 +OP4 E00979 0 +OP4 E0097A 0 +OP4 E0097B 0 +OP4 E0097C 0 +OP4 E0097D 0 +OP4 E0097E 0 +OP4 E0097F 0 +OP4 E00980 0 +OP4 E00981 0 +OP4 E00982 0 +OP4 E00983 0 +OP4 E00984 0 +OP4 E00985 0 +OP4 E00986 0 +OP4 E00987 0 +OP4 E00988 0 +OP4 E00989 0 +OP4 E0098A 0 +OP4 E0098B 0 +OP4 E0098C 0 +OP4 E0098D 0 +OP4 E0098E 0 +OP4 E0098F 0 +OP4 E00990 0 +OP4 E00991 0 +OP4 E00992 0 +OP4 E00993 0 +OP4 E00994 0 +OP4 E00995 0 +OP4 E00996 0 +OP4 E00997 0 +OP4 E00998 0 +OP4 E00999 0 +OP4 E0099A 0 +OP4 E0099B 0 +OP4 E0099C 0 +OP4 E0099D 0 +OP4 E0099E 0 +OP4 E0099F 0 +OP4 E009A0 0 +OP4 E009A1 0 +OP4 E009A2 0 +OP4 E009A3 0 +OP4 E009A4 0 +OP4 E009A5 0 +OP4 E009A6 0 +OP4 E009A7 0 +OP4 E009A8 0 +OP4 E009A9 0 +OP4 E009AA 0 +OP4 E009AB 0 +OP4 E009AC 0 +OP4 E009AD 0 +OP4 E009AE 0 +OP4 E009AF 0 +OP4 E009B0 0 +OP4 E009B1 0 +OP4 E009B2 0 +OP4 E009B3 0 +OP4 E009B4 0 +OP4 E009B5 0 +OP4 E009B6 0 +OP4 E009B7 0 +OP4 E009B8 0 +OP4 E009B9 0 +OP4 E009BA 0 +OP4 E009BB 0 +OP4 E009BC 0 +OP4 E009BD 0 +OP4 E009BE 0 +OP4 E009BF 0 +OP4 E009C0 0 +OP4 E009C1 0 +OP4 E009C2 0 +OP4 E009C3 0 +OP4 E009C4 0 +OP4 E009C5 0 +OP4 E009C6 0 +OP4 E009C7 0 +OP4 E009C8 0 +OP4 E009C9 0 +OP4 E009CA 0 +OP4 E009CB 0 +OP4 E009CC 0 +OP4 E009CD 0 +OP4 E009CE 0 +OP4 E009CF 0 +OP4 E009D0 0 +OP4 E009D1 0 +OP4 E009D2 0 +OP4 E009D3 0 +OP4 E009D4 0 +OP4 E009D5 0 +OP4 E009D6 0 +OP4 E009D7 0 +OP4 E009D8 0 +OP4 E009D9 0 +OP4 E009DA 0 +OP4 E009DB 0 +OP4 E009DC 0 +OP4 E009DD 0 +OP4 E009DE 0 +OP4 E009DF 0 +OP4 E009E0 0 +OP4 E009E1 0 +OP4 E009E2 0 +OP4 E009E3 0 +OP4 E009E4 0 +OP4 E009E5 0 +OP4 E009E6 0 +OP4 E009E7 0 +OP4 E009E8 0 +OP4 E009E9 0 +OP4 E009EA 0 +OP4 E009EB 0 +OP4 E009EC 0 +OP4 E009ED 0 +OP4 E009EE 0 +OP4 E009EF 0 +OP4 E009F0 0 +OP4 E009F1 0 +OP4 E009F2 0 +OP4 E009F3 0 +OP4 E009F4 0 +OP4 E009F5 0 +OP4 E009F6 0 +OP4 E009F7 0 +OP4 E009F8 0 +OP4 E009F9 0 +OP4 E009FA 0 +OP4 E009FB 0 +OP4 E009FC 0 +OP4 E009FD 0 +OP4 E009FE 0 +OP4 E009FF 0 +OP4 E00A00 0 +OP4 E00A01 0 +OP4 E00A02 0 +OP4 E00A03 0 +OP4 E00A04 0 +OP4 E00A05 0 +OP4 E00A06 0 +OP4 E00A07 0 +OP4 E00A08 0 diff --git a/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum2_itrace_irisc2.cfg.ext b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum2_itrace_irisc2.cfg.ext new file mode 100644 index 000000000000..e7edd0795752 --- /dev/null +++ b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum2_itrace_irisc2.cfg.ext @@ -0,0 +1,2570 @@ +OP1 Spectrum2 +OP4 ITRACE0 0 +OP4 ITRACE1 0 +OP4 ITRACE2 1 +OP4 ITRACE3 0 +OP4 ITRACE4 0 +OP4 ITRACE5 0 +OP4 ITRACE6 0 +OP4 ITRACE7 0 +OP4 Main_PhyUC 0 +OP4 E00009 0 +OP4 E0000A 0 +OP4 E0000B 0 +OP4 E0000C 0 +OP4 E0000D 0 +OP4 E0000E 0 +OP4 E0000F 0 +OP4 E00010 0 +OP4 E00011 0 +OP4 E00012 0 +OP4 E00013 0 +OP4 E00014 0 +OP4 E00015 0 +OP4 E00016 0 +OP4 E00017 0 +OP4 E00018 0 +OP4 E00019 0 +OP4 E0001A 0 +OP4 E0001B 0 +OP4 E0001C 0 +OP4 E0001D 0 +OP4 E0001E 0 +OP4 E0001F 0 +OP4 E00020 0 +OP4 E00021 0 +OP4 E00022 0 +OP4 E00023 0 +OP4 E00024 0 +OP4 E00025 0 +OP4 E00026 0 +OP4 E00027 0 +OP4 E00028 0 +OP4 E00029 0 +OP4 E0002A 0 +OP4 E0002B 0 +OP4 E0002C 0 +OP4 E0002D 0 +OP4 E0002E 0 +OP4 E0002F 0 +OP4 E00030 0 +OP4 E00031 0 +OP4 E00032 0 +OP4 E00033 0 +OP4 E00034 0 +OP4 E00035 0 +OP4 E00036 0 +OP4 E00037 0 +OP4 E00038 0 +OP4 E00039 0 +OP4 E0003A 0 +OP4 E0003B 0 +OP4 E0003C 0 +OP4 E0003D 0 +OP4 E0003E 0 +OP4 E0003F 0 +OP4 E00040 0 +OP4 E00041 0 +OP4 E00042 0 +OP4 E00043 0 +OP4 E00044 0 +OP4 E00045 0 +OP4 E00046 0 +OP4 E00047 0 +OP4 E00048 0 +OP4 E00049 0 +OP4 E0004A 0 +OP4 E0004B 0 +OP4 E0004C 0 +OP4 E0004D 0 +OP4 E0004E 0 +OP4 E0004F 0 +OP4 E00050 0 +OP4 E00051 0 +OP4 E00052 0 +OP4 E00053 0 +OP4 E00054 0 +OP4 E00055 0 +OP4 E00056 0 +OP4 E00057 0 +OP4 E00058 0 +OP4 E00059 0 +OP4 E0005A 0 +OP4 E0005B 0 +OP4 E0005C 0 +OP4 E0005D 0 +OP4 E0005E 0 +OP4 E0005F 0 +OP4 E00060 0 +OP4 E00061 0 +OP4 E00062 0 +OP4 E00063 0 +OP4 E00064 0 +OP4 E00065 0 +OP4 E00066 0 +OP4 E00067 0 +OP4 E00068 0 +OP4 E00069 0 +OP4 E0006A 0 +OP4 E0006B 0 +OP4 E0006C 0 +OP4 E0006D 0 +OP4 E0006E 0 +OP4 E0006F 0 +OP4 E00070 0 +OP4 E00071 0 +OP4 E00072 0 +OP4 E00073 0 +OP4 E00074 0 +OP4 E00075 0 +OP4 E00076 0 +OP4 E00077 0 +OP4 E00078 0 +OP4 E00079 0 +OP4 E0007A 0 +OP4 E0007B 0 +OP4 E0007C 0 +OP4 E0007D 0 +OP4 E0007E 0 +OP4 E0007F 0 +OP4 E00080 0 +OP4 E00081 0 +OP4 E00082 0 +OP4 E00083 0 +OP4 E00084 0 +OP4 E00085 0 +OP4 E00086 0 +OP4 E00087 0 +OP4 E00088 0 +OP4 E00089 0 +OP4 E0008A 0 +OP4 E0008B 0 +OP4 E0008C 0 +OP4 E0008D 0 +OP4 E0008E 0 +OP4 E0008F 0 +OP4 E00090 0 +OP4 E00091 0 +OP4 E00092 0 +OP4 E00093 0 +OP4 E00094 0 +OP4 E00095 0 +OP4 E00096 0 +OP4 E00097 0 +OP4 E00098 0 +OP4 E00099 0 +OP4 E0009A 0 +OP4 E0009B 0 +OP4 E0009C 0 +OP4 E0009D 0 +OP4 E0009E 0 +OP4 E0009F 0 +OP4 E000A0 0 +OP4 E000A1 0 +OP4 E000A2 0 +OP4 E000A3 0 +OP4 E000A4 0 +OP4 E000A5 0 +OP4 E000A6 0 +OP4 E000A7 0 +OP4 E000A8 0 +OP4 E000A9 0 +OP4 E000AA 0 +OP4 E000AB 0 +OP4 E000AC 0 +OP4 E000AD 0 +OP4 E000AE 0 +OP4 E000AF 0 +OP4 E000B0 0 +OP4 E000B1 0 +OP4 E000B2 0 +OP4 E000B3 0 +OP4 E000B4 0 +OP4 E000B5 0 +OP4 E000B6 0 +OP4 E000B7 0 +OP4 E000B8 0 +OP4 E000B9 0 +OP4 E000BA 0 +OP4 E000BB 0 +OP4 E000BC 0 +OP4 E000BD 0 +OP4 E000BE 0 +OP4 E000BF 0 +OP4 E000C0 0 +OP4 E000C1 0 +OP4 E000C2 0 +OP4 E000C3 0 +OP4 E000C4 0 +OP4 E000C5 0 +OP4 E000C6 0 +OP4 E000C7 0 +OP4 E000C8 0 +OP4 E000C9 0 +OP4 E000CA 0 +OP4 E000CB 0 +OP4 E000CC 0 +OP4 E000CD 0 +OP4 E000CE 0 +OP4 E000CF 0 +OP4 E000D0 0 +OP4 E000D1 0 +OP4 E000D2 0 +OP4 E000D3 0 +OP4 E000D4 0 +OP4 E000D5 0 +OP4 E000D6 0 +OP4 E000D7 0 +OP4 E000D8 0 +OP4 E000D9 0 +OP4 E000DA 0 +OP4 E000DB 0 +OP4 E000DC 0 +OP4 E000DD 0 +OP4 E000DE 0 +OP4 E000DF 0 +OP4 E000E0 0 +OP4 E000E1 0 +OP4 E000E2 0 +OP4 E000E3 0 +OP4 E000E4 0 +OP4 E000E5 0 +OP4 E000E6 0 +OP4 E000E7 0 +OP4 E000E8 0 +OP4 E000E9 0 +OP4 E000EA 0 +OP4 E000EB 0 +OP4 E000EC 0 +OP4 E000ED 0 +OP4 E000EE 0 +OP4 E000EF 0 +OP4 E000F0 0 +OP4 E000F1 0 +OP4 E000F2 0 +OP4 E000F3 0 +OP4 E000F4 0 +OP4 E000F5 0 +OP4 E000F6 0 +OP4 E000F7 0 +OP4 E000F8 0 +OP4 E000F9 0 +OP4 E000FA 0 +OP4 E000FB 0 +OP4 E000FC 0 +OP4 E000FD 0 +OP4 E000FE 0 +OP4 E000FF 0 +OP4 E00100 0 +OP4 E00101 0 +OP4 E00102 0 +OP4 E00103 0 +OP4 E00104 0 +OP4 E00105 0 +OP4 E00106 0 +OP4 E00107 0 +OP4 E00108 0 +OP4 E00109 0 +OP4 E0010A 0 +OP4 E0010B 0 +OP4 E0010C 0 +OP4 E0010D 0 +OP4 E0010E 0 +OP4 E0010F 0 +OP4 E00110 0 +OP4 E00111 0 +OP4 E00112 0 +OP4 E00113 0 +OP4 E00114 0 +OP4 E00115 0 +OP4 E00116 0 +OP4 E00117 0 +OP4 E00118 0 +OP4 E00119 0 +OP4 E0011A 0 +OP4 E0011B 0 +OP4 E0011C 0 +OP4 E0011D 0 +OP4 E0011E 0 +OP4 E0011F 0 +OP4 E00120 0 +OP4 E00121 0 +OP4 E00122 0 +OP4 E00123 0 +OP4 E00124 0 +OP4 E00125 0 +OP4 E00126 0 +OP4 E00127 0 +OP4 E00128 0 +OP4 E00129 0 +OP4 E0012A 0 +OP4 E0012B 0 +OP4 E0012C 0 +OP4 E0012D 0 +OP4 E0012E 0 +OP4 E0012F 0 +OP4 E00130 0 +OP4 E00131 0 +OP4 E00132 0 +OP4 E00133 0 +OP4 E00134 0 +OP4 E00135 0 +OP4 E00136 0 +OP4 E00137 0 +OP4 E00138 0 +OP4 E00139 0 +OP4 E0013A 0 +OP4 E0013B 0 +OP4 E0013C 0 +OP4 E0013D 0 +OP4 E0013E 0 +OP4 E0013F 0 +OP4 E00140 0 +OP4 E00141 0 +OP4 E00142 0 +OP4 E00143 0 +OP4 E00144 0 +OP4 E00145 0 +OP4 E00146 0 +OP4 E00147 0 +OP4 E00148 0 +OP4 E00149 0 +OP4 E0014A 0 +OP4 E0014B 0 +OP4 E0014C 0 +OP4 E0014D 0 +OP4 E0014E 0 +OP4 E0014F 0 +OP4 E00150 0 +OP4 E00151 0 +OP4 E00152 0 +OP4 E00153 0 +OP4 E00154 0 +OP4 E00155 0 +OP4 E00156 0 +OP4 E00157 0 +OP4 E00158 0 +OP4 E00159 0 +OP4 E0015A 0 +OP4 E0015B 0 +OP4 E0015C 0 +OP4 E0015D 0 +OP4 E0015E 0 +OP4 E0015F 0 +OP4 E00160 0 +OP4 E00161 0 +OP4 E00162 0 +OP4 E00163 0 +OP4 E00164 0 +OP4 E00165 0 +OP4 E00166 0 +OP4 E00167 0 +OP4 E00168 0 +OP4 E00169 0 +OP4 E0016A 0 +OP4 E0016B 0 +OP4 E0016C 0 +OP4 E0016D 0 +OP4 E0016E 0 +OP4 E0016F 0 +OP4 E00170 0 +OP4 E00171 0 +OP4 E00172 0 +OP4 E00173 0 +OP4 E00174 0 +OP4 E00175 0 +OP4 E00176 0 +OP4 E00177 0 +OP4 E00178 0 +OP4 E00179 0 +OP4 E0017A 0 +OP4 E0017B 0 +OP4 E0017C 0 +OP4 E0017D 0 +OP4 E0017E 0 +OP4 E0017F 0 +OP4 E00180 0 +OP4 E00181 0 +OP4 E00182 0 +OP4 E00183 0 +OP4 E00184 0 +OP4 E00185 0 +OP4 E00186 0 +OP4 E00187 0 +OP4 E00188 0 +OP4 E00189 0 +OP4 E0018A 0 +OP4 E0018B 0 +OP4 E0018C 0 +OP4 E0018D 0 +OP4 E0018E 0 +OP4 E0018F 0 +OP4 E00190 0 +OP4 E00191 0 +OP4 E00192 0 +OP4 E00193 0 +OP4 E00194 0 +OP4 E00195 0 +OP4 E00196 0 +OP4 E00197 0 +OP4 E00198 0 +OP4 E00199 0 +OP4 E0019A 0 +OP4 E0019B 0 +OP4 E0019C 0 +OP4 E0019D 0 +OP4 E0019E 0 +OP4 E0019F 0 +OP4 E001A0 0 +OP4 E001A1 0 +OP4 E001A2 0 +OP4 E001A3 0 +OP4 E001A4 0 +OP4 E001A5 0 +OP4 E001A6 0 +OP4 E001A7 0 +OP4 E001A8 0 +OP4 E001A9 0 +OP4 E001AA 0 +OP4 E001AB 0 +OP4 E001AC 0 +OP4 E001AD 0 +OP4 E001AE 0 +OP4 E001AF 0 +OP4 E001B0 0 +OP4 E001B1 0 +OP4 E001B2 0 +OP4 E001B3 0 +OP4 E001B4 0 +OP4 E001B5 0 +OP4 E001B6 0 +OP4 E001B7 0 +OP4 E001B8 0 +OP4 E001B9 0 +OP4 E001BA 0 +OP4 E001BB 0 +OP4 E001BC 0 +OP4 E001BD 0 +OP4 E001BE 0 +OP4 E001BF 0 +OP4 E001C0 0 +OP4 E001C1 0 +OP4 E001C2 0 +OP4 E001C3 0 +OP4 E001C4 0 +OP4 E001C5 0 +OP4 E001C6 0 +OP4 E001C7 0 +OP4 E001C8 0 +OP4 E001C9 0 +OP4 E001CA 0 +OP4 E001CB 0 +OP4 E001CC 0 +OP4 E001CD 0 +OP4 E001CE 0 +OP4 E001CF 0 +OP4 E001D0 0 +OP4 E001D1 0 +OP4 E001D2 0 +OP4 E001D3 0 +OP4 E001D4 0 +OP4 E001D5 0 +OP4 E001D6 0 +OP4 E001D7 0 +OP4 E001D8 0 +OP4 E001D9 0 +OP4 E001DA 0 +OP4 E001DB 0 +OP4 E001DC 0 +OP4 E001DD 0 +OP4 E001DE 0 +OP4 E001DF 0 +OP4 E001E0 0 +OP4 E001E1 0 +OP4 E001E2 0 +OP4 E001E3 0 +OP4 E001E4 0 +OP4 E001E5 0 +OP4 E001E6 0 +OP4 E001E7 0 +OP4 E001E8 0 +OP4 E001E9 0 +OP4 E001EA 0 +OP4 E001EB 0 +OP4 E001EC 0 +OP4 E001ED 0 +OP4 E001EE 0 +OP4 E001EF 0 +OP4 E001F0 0 +OP4 E001F1 0 +OP4 E001F2 0 +OP4 E001F3 0 +OP4 E001F4 0 +OP4 E001F5 0 +OP4 E001F6 0 +OP4 E001F7 0 +OP4 E001F8 0 +OP4 E001F9 0 +OP4 E001FA 0 +OP4 E001FB 0 +OP4 E001FC 0 +OP4 E001FD 0 +OP4 E001FE 0 +OP4 E001FF 0 +OP4 E00200 0 +OP4 E00201 0 +OP4 E00202 0 +OP4 E00203 0 +OP4 E00204 0 +OP4 E00205 0 +OP4 E00206 0 +OP4 E00207 0 +OP4 E00208 0 +OP4 E00209 0 +OP4 E0020A 0 +OP4 E0020B 0 +OP4 E0020C 0 +OP4 E0020D 0 +OP4 E0020E 0 +OP4 E0020F 0 +OP4 E00210 0 +OP4 E00211 0 +OP4 E00212 0 +OP4 E00213 0 +OP4 E00214 0 +OP4 E00215 0 +OP4 E00216 0 +OP4 E00217 0 +OP4 E00218 0 +OP4 E00219 0 +OP4 E0021A 0 +OP4 E0021B 0 +OP4 E0021C 0 +OP4 E0021D 0 +OP4 E0021E 0 +OP4 E0021F 0 +OP4 E00220 0 +OP4 E00221 0 +OP4 E00222 0 +OP4 E00223 0 +OP4 E00224 0 +OP4 E00225 0 +OP4 E00226 0 +OP4 E00227 0 +OP4 E00228 0 +OP4 E00229 0 +OP4 E0022A 0 +OP4 E0022B 0 +OP4 E0022C 0 +OP4 E0022D 0 +OP4 E0022E 0 +OP4 E0022F 0 +OP4 E00230 0 +OP4 E00231 0 +OP4 E00232 0 +OP4 E00233 0 +OP4 E00234 0 +OP4 E00235 0 +OP4 E00236 0 +OP4 E00237 0 +OP4 E00238 0 +OP4 E00239 0 +OP4 E0023A 0 +OP4 E0023B 0 +OP4 E0023C 0 +OP4 E0023D 0 +OP4 E0023E 0 +OP4 E0023F 0 +OP4 E00240 0 +OP4 E00241 0 +OP4 E00242 0 +OP4 E00243 0 +OP4 E00244 0 +OP4 E00245 0 +OP4 E00246 0 +OP4 E00247 0 +OP4 E00248 0 +OP4 E00249 0 +OP4 E0024A 0 +OP4 E0024B 0 +OP4 E0024C 0 +OP4 E0024D 0 +OP4 E0024E 0 +OP4 E0024F 0 +OP4 E00250 0 +OP4 E00251 0 +OP4 E00252 0 +OP4 E00253 0 +OP4 E00254 0 +OP4 E00255 0 +OP4 E00256 0 +OP4 E00257 0 +OP4 E00258 0 +OP4 E00259 0 +OP4 E0025A 0 +OP4 E0025B 0 +OP4 E0025C 0 +OP4 E0025D 0 +OP4 E0025E 0 +OP4 E0025F 0 +OP4 E00260 0 +OP4 E00261 0 +OP4 E00262 0 +OP4 E00263 0 +OP4 E00264 0 +OP4 E00265 0 +OP4 E00266 0 +OP4 E00267 0 +OP4 E00268 0 +OP4 E00269 0 +OP4 E0026A 0 +OP4 E0026B 0 +OP4 E0026C 0 +OP4 E0026D 0 +OP4 E0026E 0 +OP4 E0026F 0 +OP4 E00270 0 +OP4 E00271 0 +OP4 E00272 0 +OP4 E00273 0 +OP4 E00274 0 +OP4 E00275 0 +OP4 E00276 0 +OP4 E00277 0 +OP4 E00278 0 +OP4 E00279 0 +OP4 E0027A 0 +OP4 E0027B 0 +OP4 E0027C 0 +OP4 E0027D 0 +OP4 E0027E 0 +OP4 E0027F 0 +OP4 E00280 0 +OP4 E00281 0 +OP4 E00282 0 +OP4 E00283 0 +OP4 E00284 0 +OP4 E00285 0 +OP4 E00286 0 +OP4 E00287 0 +OP4 E00288 0 +OP4 E00289 0 +OP4 E0028A 0 +OP4 E0028B 0 +OP4 E0028C 0 +OP4 E0028D 0 +OP4 E0028E 0 +OP4 E0028F 0 +OP4 E00290 0 +OP4 E00291 0 +OP4 E00292 0 +OP4 E00293 0 +OP4 E00294 0 +OP4 E00295 0 +OP4 E00296 0 +OP4 E00297 0 +OP4 E00298 0 +OP4 E00299 0 +OP4 E0029A 0 +OP4 E0029B 0 +OP4 E0029C 0 +OP4 E0029D 0 +OP4 E0029E 0 +OP4 E0029F 0 +OP4 E002A0 0 +OP4 E002A1 0 +OP4 E002A2 0 +OP4 E002A3 0 +OP4 E002A4 0 +OP4 E002A5 0 +OP4 E002A6 0 +OP4 E002A7 0 +OP4 E002A8 0 +OP4 E002A9 0 +OP4 E002AA 0 +OP4 E002AB 0 +OP4 E002AC 0 +OP4 E002AD 0 +OP4 E002AE 0 +OP4 E002AF 0 +OP4 E002B0 0 +OP4 E002B1 0 +OP4 E002B2 0 +OP4 E002B3 0 +OP4 E002B4 0 +OP4 E002B5 0 +OP4 E002B6 0 +OP4 E002B7 0 +OP4 E002B8 0 +OP4 E002B9 0 +OP4 E002BA 0 +OP4 E002BB 0 +OP4 E002BC 0 +OP4 E002BD 0 +OP4 E002BE 0 +OP4 E002BF 0 +OP4 E002C0 0 +OP4 E002C1 0 +OP4 E002C2 0 +OP4 E002C3 0 +OP4 E002C4 0 +OP4 E002C5 0 +OP4 E002C6 0 +OP4 E002C7 0 +OP4 E002C8 0 +OP4 E002C9 0 +OP4 E002CA 0 +OP4 E002CB 0 +OP4 E002CC 0 +OP4 E002CD 0 +OP4 E002CE 0 +OP4 E002CF 0 +OP4 E002D0 0 +OP4 E002D1 0 +OP4 E002D2 0 +OP4 E002D3 0 +OP4 E002D4 0 +OP4 E002D5 0 +OP4 E002D6 0 +OP4 E002D7 0 +OP4 E002D8 0 +OP4 E002D9 0 +OP4 E002DA 0 +OP4 E002DB 0 +OP4 E002DC 0 +OP4 E002DD 0 +OP4 E002DE 0 +OP4 E002DF 0 +OP4 E002E0 0 +OP4 E002E1 0 +OP4 E002E2 0 +OP4 E002E3 0 +OP4 E002E4 0 +OP4 E002E5 0 +OP4 E002E6 0 +OP4 E002E7 0 +OP4 E002E8 0 +OP4 E002E9 0 +OP4 E002EA 0 +OP4 E002EB 0 +OP4 E002EC 0 +OP4 E002ED 0 +OP4 E002EE 0 +OP4 E002EF 0 +OP4 E002F0 0 +OP4 E002F1 0 +OP4 E002F2 0 +OP4 E002F3 0 +OP4 E002F4 0 +OP4 E002F5 0 +OP4 E002F6 0 +OP4 E002F7 0 +OP4 E002F8 0 +OP4 E002F9 0 +OP4 E002FA 0 +OP4 E002FB 0 +OP4 E002FC 0 +OP4 E002FD 0 +OP4 E002FE 0 +OP4 E002FF 0 +OP4 E00300 0 +OP4 E00301 0 +OP4 E00302 0 +OP4 E00303 0 +OP4 E00304 0 +OP4 E00305 0 +OP4 E00306 0 +OP4 E00307 0 +OP4 E00308 0 +OP4 E00309 0 +OP4 E0030A 0 +OP4 E0030B 0 +OP4 E0030C 0 +OP4 E0030D 0 +OP4 E0030E 0 +OP4 E0030F 0 +OP4 E00310 0 +OP4 E00311 0 +OP4 E00312 0 +OP4 E00313 0 +OP4 E00314 0 +OP4 E00315 0 +OP4 E00316 0 +OP4 E00317 0 +OP4 E00318 0 +OP4 E00319 0 +OP4 E0031A 0 +OP4 E0031B 0 +OP4 E0031C 0 +OP4 E0031D 0 +OP4 E0031E 0 +OP4 E0031F 0 +OP4 E00320 0 +OP4 E00321 0 +OP4 E00322 0 +OP4 E00323 0 +OP4 E00324 0 +OP4 E00325 0 +OP4 E00326 0 +OP4 E00327 0 +OP4 E00328 0 +OP4 E00329 0 +OP4 E0032A 0 +OP4 E0032B 0 +OP4 E0032C 0 +OP4 E0032D 0 +OP4 E0032E 0 +OP4 E0032F 0 +OP4 E00330 0 +OP4 E00331 0 +OP4 E00332 0 +OP4 E00333 0 +OP4 E00334 0 +OP4 E00335 0 +OP4 E00336 0 +OP4 E00337 0 +OP4 E00338 0 +OP4 E00339 0 +OP4 E0033A 0 +OP4 E0033B 0 +OP4 E0033C 0 +OP4 E0033D 0 +OP4 E0033E 0 +OP4 E0033F 0 +OP4 E00340 0 +OP4 E00341 0 +OP4 E00342 0 +OP4 E00343 0 +OP4 E00344 0 +OP4 E00345 0 +OP4 E00346 0 +OP4 E00347 0 +OP4 E00348 0 +OP4 E00349 0 +OP4 E0034A 0 +OP4 E0034B 0 +OP4 E0034C 0 +OP4 E0034D 0 +OP4 E0034E 0 +OP4 E0034F 0 +OP4 E00350 0 +OP4 E00351 0 +OP4 E00352 0 +OP4 E00353 0 +OP4 E00354 0 +OP4 E00355 0 +OP4 E00356 0 +OP4 E00357 0 +OP4 E00358 0 +OP4 E00359 0 +OP4 E0035A 0 +OP4 E0035B 0 +OP4 E0035C 0 +OP4 E0035D 0 +OP4 E0035E 0 +OP4 E0035F 0 +OP4 E00360 0 +OP4 E00361 0 +OP4 E00362 0 +OP4 E00363 0 +OP4 E00364 0 +OP4 E00365 0 +OP4 E00366 0 +OP4 E00367 0 +OP4 E00368 0 +OP4 E00369 0 +OP4 E0036A 0 +OP4 E0036B 0 +OP4 E0036C 0 +OP4 E0036D 0 +OP4 E0036E 0 +OP4 E0036F 0 +OP4 E00370 0 +OP4 E00371 0 +OP4 E00372 0 +OP4 E00373 0 +OP4 E00374 0 +OP4 E00375 0 +OP4 E00376 0 +OP4 E00377 0 +OP4 E00378 0 +OP4 E00379 0 +OP4 E0037A 0 +OP4 E0037B 0 +OP4 E0037C 0 +OP4 E0037D 0 +OP4 E0037E 0 +OP4 E0037F 0 +OP4 E00380 0 +OP4 E00381 0 +OP4 E00382 0 +OP4 E00383 0 +OP4 E00384 0 +OP4 E00385 0 +OP4 E00386 0 +OP4 E00387 0 +OP4 E00388 0 +OP4 E00389 0 +OP4 E0038A 0 +OP4 E0038B 0 +OP4 E0038C 0 +OP4 E0038D 0 +OP4 E0038E 0 +OP4 E0038F 0 +OP4 E00390 0 +OP4 E00391 0 +OP4 E00392 0 +OP4 E00393 0 +OP4 E00394 0 +OP4 E00395 0 +OP4 E00396 0 +OP4 E00397 0 +OP4 E00398 0 +OP4 E00399 0 +OP4 E0039A 0 +OP4 E0039B 0 +OP4 E0039C 0 +OP4 E0039D 0 +OP4 E0039E 0 +OP4 E0039F 0 +OP4 E003A0 0 +OP4 E003A1 0 +OP4 E003A2 0 +OP4 E003A3 0 +OP4 E003A4 0 +OP4 E003A5 0 +OP4 E003A6 0 +OP4 E003A7 0 +OP4 E003A8 0 +OP4 E003A9 0 +OP4 E003AA 0 +OP4 E003AB 0 +OP4 E003AC 0 +OP4 E003AD 0 +OP4 E003AE 0 +OP4 E003AF 0 +OP4 E003B0 0 +OP4 E003B1 0 +OP4 E003B2 0 +OP4 E003B3 0 +OP4 E003B4 0 +OP4 E003B5 0 +OP4 E003B6 0 +OP4 E003B7 0 +OP4 E003B8 0 +OP4 E003B9 0 +OP4 E003BA 0 +OP4 E003BB 0 +OP4 E003BC 0 +OP4 E003BD 0 +OP4 E003BE 0 +OP4 E003BF 0 +OP4 E003C0 0 +OP4 E003C1 0 +OP4 E003C2 0 +OP4 E003C3 0 +OP4 E003C4 0 +OP4 E003C5 0 +OP4 E003C6 0 +OP4 E003C7 0 +OP4 E003C8 0 +OP4 E003C9 0 +OP4 E003CA 0 +OP4 E003CB 0 +OP4 E003CC 0 +OP4 E003CD 0 +OP4 E003CE 0 +OP4 E003CF 0 +OP4 E003D0 0 +OP4 E003D1 0 +OP4 E003D2 0 +OP4 E003D3 0 +OP4 E003D4 0 +OP4 E003D5 0 +OP4 E003D6 0 +OP4 E003D7 0 +OP4 E003D8 0 +OP4 E003D9 0 +OP4 E003DA 0 +OP4 E003DB 0 +OP4 E003DC 0 +OP4 E003DD 0 +OP4 E003DE 0 +OP4 E003DF 0 +OP4 E003E0 0 +OP4 E003E1 0 +OP4 E003E2 0 +OP4 E003E3 0 +OP4 E003E4 0 +OP4 E003E5 0 +OP4 E003E6 0 +OP4 E003E7 0 +OP4 E003E8 0 +OP4 E003E9 0 +OP4 E003EA 0 +OP4 E003EB 0 +OP4 E003EC 0 +OP4 E003ED 0 +OP4 E003EE 0 +OP4 E003EF 0 +OP4 E003F0 0 +OP4 E003F1 0 +OP4 E003F2 0 +OP4 E003F3 0 +OP4 E003F4 0 +OP4 E003F5 0 +OP4 E003F6 0 +OP4 E003F7 0 +OP4 E003F8 0 +OP4 E003F9 0 +OP4 E003FA 0 +OP4 E003FB 0 +OP4 E003FC 0 +OP4 E003FD 0 +OP4 E003FE 0 +OP4 E003FF 0 +OP4 E00400 0 +OP4 E00401 0 +OP4 E00402 0 +OP4 E00403 0 +OP4 E00404 0 +OP4 E00405 0 +OP4 E00406 0 +OP4 E00407 0 +OP4 E00408 0 +OP4 E00409 0 +OP4 E0040A 0 +OP4 E0040B 0 +OP4 E0040C 0 +OP4 E0040D 0 +OP4 E0040E 0 +OP4 E0040F 0 +OP4 E00410 0 +OP4 E00411 0 +OP4 E00412 0 +OP4 E00413 0 +OP4 E00414 0 +OP4 E00415 0 +OP4 E00416 0 +OP4 E00417 0 +OP4 E00418 0 +OP4 E00419 0 +OP4 E0041A 0 +OP4 E0041B 0 +OP4 E0041C 0 +OP4 E0041D 0 +OP4 E0041E 0 +OP4 E0041F 0 +OP4 E00420 0 +OP4 E00421 0 +OP4 E00422 0 +OP4 E00423 0 +OP4 E00424 0 +OP4 E00425 0 +OP4 E00426 0 +OP4 E00427 0 +OP4 E00428 0 +OP4 E00429 0 +OP4 E0042A 0 +OP4 E0042B 0 +OP4 E0042C 0 +OP4 E0042D 0 +OP4 E0042E 0 +OP4 E0042F 0 +OP4 E00430 0 +OP4 E00431 0 +OP4 E00432 0 +OP4 E00433 0 +OP4 E00434 0 +OP4 E00435 0 +OP4 E00436 0 +OP4 E00437 0 +OP4 E00438 0 +OP4 E00439 0 +OP4 E0043A 0 +OP4 E0043B 0 +OP4 E0043C 0 +OP4 E0043D 0 +OP4 E0043E 0 +OP4 E0043F 0 +OP4 E00440 0 +OP4 E00441 0 +OP4 E00442 0 +OP4 E00443 0 +OP4 E00444 0 +OP4 E00445 0 +OP4 E00446 0 +OP4 E00447 0 +OP4 E00448 0 +OP4 E00449 0 +OP4 E0044A 0 +OP4 E0044B 0 +OP4 E0044C 0 +OP4 E0044D 0 +OP4 E0044E 0 +OP4 E0044F 0 +OP4 E00450 0 +OP4 E00451 0 +OP4 E00452 0 +OP4 E00453 0 +OP4 E00454 0 +OP4 E00455 0 +OP4 E00456 0 +OP4 E00457 0 +OP4 E00458 0 +OP4 E00459 0 +OP4 E0045A 0 +OP4 E0045B 0 +OP4 E0045C 0 +OP4 E0045D 0 +OP4 E0045E 0 +OP4 E0045F 0 +OP4 E00460 0 +OP4 E00461 0 +OP4 E00462 0 +OP4 E00463 0 +OP4 E00464 0 +OP4 E00465 0 +OP4 E00466 0 +OP4 E00467 0 +OP4 E00468 0 +OP4 E00469 0 +OP4 E0046A 0 +OP4 E0046B 0 +OP4 E0046C 0 +OP4 E0046D 0 +OP4 E0046E 0 +OP4 E0046F 0 +OP4 E00470 0 +OP4 E00471 0 +OP4 E00472 0 +OP4 E00473 0 +OP4 E00474 0 +OP4 E00475 0 +OP4 E00476 0 +OP4 E00477 0 +OP4 E00478 0 +OP4 E00479 0 +OP4 E0047A 0 +OP4 E0047B 0 +OP4 E0047C 0 +OP4 E0047D 0 +OP4 E0047E 0 +OP4 E0047F 0 +OP4 E00480 0 +OP4 E00481 0 +OP4 E00482 0 +OP4 E00483 0 +OP4 E00484 0 +OP4 E00485 0 +OP4 E00486 0 +OP4 E00487 0 +OP4 E00488 0 +OP4 E00489 0 +OP4 E0048A 0 +OP4 E0048B 0 +OP4 E0048C 0 +OP4 E0048D 0 +OP4 E0048E 0 +OP4 E0048F 0 +OP4 E00490 0 +OP4 E00491 0 +OP4 E00492 0 +OP4 E00493 0 +OP4 E00494 0 +OP4 E00495 0 +OP4 E00496 0 +OP4 E00497 0 +OP4 E00498 0 +OP4 E00499 0 +OP4 E0049A 0 +OP4 E0049B 0 +OP4 E0049C 0 +OP4 E0049D 0 +OP4 E0049E 0 +OP4 E0049F 0 +OP4 E004A0 0 +OP4 E004A1 0 +OP4 E004A2 0 +OP4 E004A3 0 +OP4 E004A4 0 +OP4 E004A5 0 +OP4 E004A6 0 +OP4 E004A7 0 +OP4 E004A8 0 +OP4 E004A9 0 +OP4 E004AA 0 +OP4 E004AB 0 +OP4 E004AC 0 +OP4 E004AD 0 +OP4 E004AE 0 +OP4 E004AF 0 +OP4 E004B0 0 +OP4 E004B1 0 +OP4 E004B2 0 +OP4 E004B3 0 +OP4 E004B4 0 +OP4 E004B5 0 +OP4 E004B6 0 +OP4 E004B7 0 +OP4 E004B8 0 +OP4 E004B9 0 +OP4 E004BA 0 +OP4 E004BB 0 +OP4 E004BC 0 +OP4 E004BD 0 +OP4 E004BE 0 +OP4 E004BF 0 +OP4 E004C0 0 +OP4 E004C1 0 +OP4 E004C2 0 +OP4 E004C3 0 +OP4 E004C4 0 +OP4 E004C5 0 +OP4 E004C6 0 +OP4 E004C7 0 +OP4 E004C8 0 +OP4 E004C9 0 +OP4 E004CA 0 +OP4 E004CB 0 +OP4 E004CC 0 +OP4 E004CD 0 +OP4 E004CE 0 +OP4 E004CF 0 +OP4 E004D0 0 +OP4 E004D1 0 +OP4 E004D2 0 +OP4 E004D3 0 +OP4 E004D4 0 +OP4 E004D5 0 +OP4 E004D6 0 +OP4 E004D7 0 +OP4 E004D8 0 +OP4 E004D9 0 +OP4 E004DA 0 +OP4 E004DB 0 +OP4 E004DC 0 +OP4 E004DD 0 +OP4 E004DE 0 +OP4 E004DF 0 +OP4 E004E0 0 +OP4 E004E1 0 +OP4 E004E2 0 +OP4 E004E3 0 +OP4 E004E4 0 +OP4 E004E5 0 +OP4 E004E6 0 +OP4 E004E7 0 +OP4 E004E8 0 +OP4 E004E9 0 +OP4 E004EA 0 +OP4 E004EB 0 +OP4 E004EC 0 +OP4 E004ED 0 +OP4 E004EE 0 +OP4 E004EF 0 +OP4 E004F0 0 +OP4 E004F1 0 +OP4 E004F2 0 +OP4 E004F3 0 +OP4 E004F4 0 +OP4 E004F5 0 +OP4 E004F6 0 +OP4 E004F7 0 +OP4 E004F8 0 +OP4 E004F9 0 +OP4 E004FA 0 +OP4 E004FB 0 +OP4 E004FC 0 +OP4 E004FD 0 +OP4 E004FE 0 +OP4 E004FF 0 +OP4 E00500 0 +OP4 E00501 0 +OP4 E00502 0 +OP4 E00503 0 +OP4 E00504 0 +OP4 E00505 0 +OP4 E00506 0 +OP4 E00507 0 +OP4 E00508 0 +OP4 E00509 0 +OP4 E0050A 0 +OP4 E0050B 0 +OP4 E0050C 0 +OP4 E0050D 0 +OP4 E0050E 0 +OP4 E0050F 0 +OP4 E00510 0 +OP4 E00511 0 +OP4 E00512 0 +OP4 E00513 0 +OP4 E00514 0 +OP4 E00515 0 +OP4 E00516 0 +OP4 E00517 0 +OP4 E00518 0 +OP4 E00519 0 +OP4 E0051A 0 +OP4 E0051B 0 +OP4 E0051C 0 +OP4 E0051D 0 +OP4 E0051E 0 +OP4 E0051F 0 +OP4 E00520 0 +OP4 E00521 0 +OP4 E00522 0 +OP4 E00523 0 +OP4 E00524 0 +OP4 E00525 0 +OP4 E00526 0 +OP4 E00527 0 +OP4 E00528 0 +OP4 E00529 0 +OP4 E0052A 0 +OP4 E0052B 0 +OP4 E0052C 0 +OP4 E0052D 0 +OP4 E0052E 0 +OP4 E0052F 0 +OP4 E00530 0 +OP4 E00531 0 +OP4 E00532 0 +OP4 E00533 0 +OP4 E00534 0 +OP4 E00535 0 +OP4 E00536 0 +OP4 E00537 0 +OP4 E00538 0 +OP4 E00539 0 +OP4 E0053A 0 +OP4 E0053B 0 +OP4 E0053C 0 +OP4 E0053D 0 +OP4 E0053E 0 +OP4 E0053F 0 +OP4 E00540 0 +OP4 E00541 0 +OP4 E00542 0 +OP4 E00543 0 +OP4 E00544 0 +OP4 E00545 0 +OP4 E00546 0 +OP4 E00547 0 +OP4 E00548 0 +OP4 E00549 0 +OP4 E0054A 0 +OP4 E0054B 0 +OP4 E0054C 0 +OP4 E0054D 0 +OP4 E0054E 0 +OP4 E0054F 0 +OP4 E00550 0 +OP4 E00551 0 +OP4 E00552 0 +OP4 E00553 0 +OP4 E00554 0 +OP4 E00555 0 +OP4 E00556 0 +OP4 E00557 0 +OP4 E00558 0 +OP4 E00559 0 +OP4 E0055A 0 +OP4 E0055B 0 +OP4 E0055C 0 +OP4 E0055D 0 +OP4 E0055E 0 +OP4 E0055F 0 +OP4 E00560 0 +OP4 E00561 0 +OP4 E00562 0 +OP4 E00563 0 +OP4 E00564 0 +OP4 E00565 0 +OP4 E00566 0 +OP4 E00567 0 +OP4 E00568 0 +OP4 E00569 0 +OP4 E0056A 0 +OP4 E0056B 0 +OP4 E0056C 0 +OP4 E0056D 0 +OP4 E0056E 0 +OP4 E0056F 0 +OP4 E00570 0 +OP4 E00571 0 +OP4 E00572 0 +OP4 E00573 0 +OP4 E00574 0 +OP4 E00575 0 +OP4 E00576 0 +OP4 E00577 0 +OP4 E00578 0 +OP4 E00579 0 +OP4 E0057A 0 +OP4 E0057B 0 +OP4 E0057C 0 +OP4 E0057D 0 +OP4 E0057E 0 +OP4 E0057F 0 +OP4 E00580 0 +OP4 E00581 0 +OP4 E00582 0 +OP4 E00583 0 +OP4 E00584 0 +OP4 E00585 0 +OP4 E00586 0 +OP4 E00587 0 +OP4 E00588 0 +OP4 E00589 0 +OP4 E0058A 0 +OP4 E0058B 0 +OP4 E0058C 0 +OP4 E0058D 0 +OP4 E0058E 0 +OP4 E0058F 0 +OP4 E00590 0 +OP4 E00591 0 +OP4 E00592 0 +OP4 E00593 0 +OP4 E00594 0 +OP4 E00595 0 +OP4 E00596 0 +OP4 E00597 0 +OP4 E00598 0 +OP4 E00599 0 +OP4 E0059A 0 +OP4 E0059B 0 +OP4 E0059C 0 +OP4 E0059D 0 +OP4 E0059E 0 +OP4 E0059F 0 +OP4 E005A0 0 +OP4 E005A1 0 +OP4 E005A2 0 +OP4 E005A3 0 +OP4 E005A4 0 +OP4 E005A5 0 +OP4 E005A6 0 +OP4 E005A7 0 +OP4 E005A8 0 +OP4 E005A9 0 +OP4 E005AA 0 +OP4 E005AB 0 +OP4 E005AC 0 +OP4 E005AD 0 +OP4 E005AE 0 +OP4 E005AF 0 +OP4 E005B0 0 +OP4 E005B1 0 +OP4 E005B2 0 +OP4 E005B3 0 +OP4 E005B4 0 +OP4 E005B5 0 +OP4 E005B6 0 +OP4 E005B7 0 +OP4 E005B8 0 +OP4 E005B9 0 +OP4 E005BA 0 +OP4 E005BB 0 +OP4 E005BC 0 +OP4 E005BD 0 +OP4 E005BE 0 +OP4 E005BF 0 +OP4 E005C0 0 +OP4 E005C1 0 +OP4 E005C2 0 +OP4 E005C3 0 +OP4 E005C4 0 +OP4 E005C5 0 +OP4 E005C6 0 +OP4 E005C7 0 +OP4 E005C8 0 +OP4 E005C9 0 +OP4 E005CA 0 +OP4 E005CB 0 +OP4 E005CC 0 +OP4 E005CD 0 +OP4 E005CE 0 +OP4 E005CF 0 +OP4 E005D0 0 +OP4 E005D1 0 +OP4 E005D2 0 +OP4 E005D3 0 +OP4 E005D4 0 +OP4 E005D5 0 +OP4 E005D6 0 +OP4 E005D7 0 +OP4 E005D8 0 +OP4 E005D9 0 +OP4 E005DA 0 +OP4 E005DB 0 +OP4 E005DC 0 +OP4 E005DD 0 +OP4 E005DE 0 +OP4 E005DF 0 +OP4 E005E0 0 +OP4 E005E1 0 +OP4 E005E2 0 +OP4 E005E3 0 +OP4 E005E4 0 +OP4 E005E5 0 +OP4 E005E6 0 +OP4 E005E7 0 +OP4 E005E8 0 +OP4 E005E9 0 +OP4 E005EA 0 +OP4 E005EB 0 +OP4 E005EC 0 +OP4 E005ED 0 +OP4 E005EE 0 +OP4 E005EF 0 +OP4 E005F0 0 +OP4 E005F1 0 +OP4 E005F2 0 +OP4 E005F3 0 +OP4 E005F4 0 +OP4 E005F5 0 +OP4 E005F6 0 +OP4 E005F7 0 +OP4 E005F8 0 +OP4 E005F9 0 +OP4 E005FA 0 +OP4 E005FB 0 +OP4 E005FC 0 +OP4 E005FD 0 +OP4 E005FE 0 +OP4 E005FF 0 +OP4 E00600 0 +OP4 E00601 0 +OP4 E00602 0 +OP4 E00603 0 +OP4 E00604 0 +OP4 E00605 0 +OP4 E00606 0 +OP4 E00607 0 +OP4 E00608 0 +OP4 E00609 0 +OP4 E0060A 0 +OP4 E0060B 0 +OP4 E0060C 0 +OP4 E0060D 0 +OP4 E0060E 0 +OP4 E0060F 0 +OP4 E00610 0 +OP4 E00611 0 +OP4 E00612 0 +OP4 E00613 0 +OP4 E00614 0 +OP4 E00615 0 +OP4 E00616 0 +OP4 E00617 0 +OP4 E00618 0 +OP4 E00619 0 +OP4 E0061A 0 +OP4 E0061B 0 +OP4 E0061C 0 +OP4 E0061D 0 +OP4 E0061E 0 +OP4 E0061F 0 +OP4 E00620 0 +OP4 E00621 0 +OP4 E00622 0 +OP4 E00623 0 +OP4 E00624 0 +OP4 E00625 0 +OP4 E00626 0 +OP4 E00627 0 +OP4 E00628 0 +OP4 E00629 0 +OP4 E0062A 0 +OP4 E0062B 0 +OP4 E0062C 0 +OP4 E0062D 0 +OP4 E0062E 0 +OP4 E0062F 0 +OP4 E00630 0 +OP4 E00631 0 +OP4 E00632 0 +OP4 E00633 0 +OP4 E00634 0 +OP4 E00635 0 +OP4 E00636 0 +OP4 E00637 0 +OP4 E00638 0 +OP4 E00639 0 +OP4 E0063A 0 +OP4 E0063B 0 +OP4 E0063C 0 +OP4 E0063D 0 +OP4 E0063E 0 +OP4 E0063F 0 +OP4 E00640 0 +OP4 E00641 0 +OP4 E00642 0 +OP4 E00643 0 +OP4 E00644 0 +OP4 E00645 0 +OP4 E00646 0 +OP4 E00647 0 +OP4 E00648 0 +OP4 E00649 0 +OP4 E0064A 0 +OP4 E0064B 0 +OP4 E0064C 0 +OP4 E0064D 0 +OP4 E0064E 0 +OP4 E0064F 0 +OP4 E00650 0 +OP4 E00651 0 +OP4 E00652 0 +OP4 E00653 0 +OP4 E00654 0 +OP4 E00655 0 +OP4 E00656 0 +OP4 E00657 0 +OP4 E00658 0 +OP4 E00659 0 +OP4 E0065A 0 +OP4 E0065B 0 +OP4 E0065C 0 +OP4 E0065D 0 +OP4 E0065E 0 +OP4 E0065F 0 +OP4 E00660 0 +OP4 E00661 0 +OP4 E00662 0 +OP4 E00663 0 +OP4 E00664 0 +OP4 E00665 0 +OP4 E00666 0 +OP4 E00667 0 +OP4 E00668 0 +OP4 E00669 0 +OP4 E0066A 0 +OP4 E0066B 0 +OP4 E0066C 0 +OP4 E0066D 0 +OP4 E0066E 0 +OP4 E0066F 0 +OP4 E00670 0 +OP4 E00671 0 +OP4 E00672 0 +OP4 E00673 0 +OP4 E00674 0 +OP4 E00675 0 +OP4 E00676 0 +OP4 E00677 0 +OP4 E00678 0 +OP4 E00679 0 +OP4 E0067A 0 +OP4 E0067B 0 +OP4 E0067C 0 +OP4 E0067D 0 +OP4 E0067E 0 +OP4 E0067F 0 +OP4 E00680 0 +OP4 E00681 0 +OP4 E00682 0 +OP4 E00683 0 +OP4 E00684 0 +OP4 E00685 0 +OP4 E00686 0 +OP4 E00687 0 +OP4 E00688 0 +OP4 E00689 0 +OP4 E0068A 0 +OP4 E0068B 0 +OP4 E0068C 0 +OP4 E0068D 0 +OP4 E0068E 0 +OP4 E0068F 0 +OP4 E00690 0 +OP4 E00691 0 +OP4 E00692 0 +OP4 E00693 0 +OP4 E00694 0 +OP4 E00695 0 +OP4 E00696 0 +OP4 E00697 0 +OP4 E00698 0 +OP4 E00699 0 +OP4 E0069A 0 +OP4 E0069B 0 +OP4 E0069C 0 +OP4 E0069D 0 +OP4 E0069E 0 +OP4 E0069F 0 +OP4 E006A0 0 +OP4 E006A1 0 +OP4 E006A2 0 +OP4 E006A3 0 +OP4 E006A4 0 +OP4 E006A5 0 +OP4 E006A6 0 +OP4 E006A7 0 +OP4 E006A8 0 +OP4 E006A9 0 +OP4 E006AA 0 +OP4 E006AB 0 +OP4 E006AC 0 +OP4 E006AD 0 +OP4 E006AE 0 +OP4 E006AF 0 +OP4 E006B0 0 +OP4 E006B1 0 +OP4 E006B2 0 +OP4 E006B3 0 +OP4 E006B4 0 +OP4 E006B5 0 +OP4 E006B6 0 +OP4 E006B7 0 +OP4 E006B8 0 +OP4 E006B9 0 +OP4 E006BA 0 +OP4 E006BB 0 +OP4 E006BC 0 +OP4 E006BD 0 +OP4 E006BE 0 +OP4 E006BF 0 +OP4 E006C0 0 +OP4 E006C1 0 +OP4 E006C2 0 +OP4 E006C3 0 +OP4 E006C4 0 +OP4 E006C5 0 +OP4 E006C6 0 +OP4 E006C7 0 +OP4 E006C8 0 +OP4 E006C9 0 +OP4 E006CA 0 +OP4 E006CB 0 +OP4 E006CC 0 +OP4 E006CD 0 +OP4 E006CE 0 +OP4 E006CF 0 +OP4 E006D0 0 +OP4 E006D1 0 +OP4 E006D2 0 +OP4 E006D3 0 +OP4 E006D4 0 +OP4 E006D5 0 +OP4 E006D6 0 +OP4 E006D7 0 +OP4 E006D8 0 +OP4 E006D9 0 +OP4 E006DA 0 +OP4 E006DB 0 +OP4 E006DC 0 +OP4 E006DD 0 +OP4 E006DE 0 +OP4 E006DF 0 +OP4 E006E0 0 +OP4 E006E1 0 +OP4 E006E2 0 +OP4 E006E3 0 +OP4 E006E4 0 +OP4 E006E5 0 +OP4 E006E6 0 +OP4 E006E7 0 +OP4 E006E8 0 +OP4 E006E9 0 +OP4 E006EA 0 +OP4 E006EB 0 +OP4 E006EC 0 +OP4 E006ED 0 +OP4 E006EE 0 +OP4 E006EF 0 +OP4 E006F0 0 +OP4 E006F1 0 +OP4 E006F2 0 +OP4 E006F3 0 +OP4 E006F4 0 +OP4 E006F5 0 +OP4 E006F6 0 +OP4 E006F7 0 +OP4 E006F8 0 +OP4 E006F9 0 +OP4 E006FA 0 +OP4 E006FB 0 +OP4 E006FC 0 +OP4 E006FD 0 +OP4 E006FE 0 +OP4 E006FF 0 +OP4 E00700 0 +OP4 E00701 0 +OP4 E00702 0 +OP4 E00703 0 +OP4 E00704 0 +OP4 E00705 0 +OP4 E00706 0 +OP4 E00707 0 +OP4 E00708 0 +OP4 E00709 0 +OP4 E0070A 0 +OP4 E0070B 0 +OP4 E0070C 0 +OP4 E0070D 0 +OP4 E0070E 0 +OP4 E0070F 0 +OP4 E00710 0 +OP4 E00711 0 +OP4 E00712 0 +OP4 E00713 0 +OP4 E00714 0 +OP4 E00715 0 +OP4 E00716 0 +OP4 E00717 0 +OP4 E00718 0 +OP4 E00719 0 +OP4 E0071A 0 +OP4 E0071B 0 +OP4 E0071C 0 +OP4 E0071D 0 +OP4 E0071E 0 +OP4 E0071F 0 +OP4 E00720 0 +OP4 E00721 0 +OP4 E00722 0 +OP4 E00723 0 +OP4 E00724 0 +OP4 E00725 0 +OP4 E00726 0 +OP4 E00727 0 +OP4 E00728 0 +OP4 E00729 0 +OP4 E0072A 0 +OP4 E0072B 0 +OP4 E0072C 0 +OP4 E0072D 0 +OP4 E0072E 0 +OP4 E0072F 0 +OP4 E00730 0 +OP4 E00731 0 +OP4 E00732 0 +OP4 E00733 0 +OP4 E00734 0 +OP4 E00735 0 +OP4 E00736 0 +OP4 E00737 0 +OP4 E00738 0 +OP4 E00739 0 +OP4 E0073A 0 +OP4 E0073B 0 +OP4 E0073C 0 +OP4 E0073D 0 +OP4 E0073E 0 +OP4 E0073F 0 +OP4 E00740 0 +OP4 E00741 0 +OP4 E00742 0 +OP4 E00743 0 +OP4 E00744 0 +OP4 E00745 0 +OP4 E00746 0 +OP4 E00747 0 +OP4 E00748 0 +OP4 E00749 0 +OP4 E0074A 0 +OP4 E0074B 0 +OP4 E0074C 0 +OP4 E0074D 0 +OP4 E0074E 0 +OP4 E0074F 0 +OP4 E00750 0 +OP4 E00751 0 +OP4 E00752 0 +OP4 E00753 0 +OP4 E00754 0 +OP4 E00755 0 +OP4 E00756 0 +OP4 E00757 0 +OP4 E00758 0 +OP4 E00759 0 +OP4 E0075A 0 +OP4 E0075B 0 +OP4 E0075C 0 +OP4 E0075D 0 +OP4 E0075E 0 +OP4 E0075F 0 +OP4 E00760 0 +OP4 E00761 0 +OP4 E00762 0 +OP4 E00763 0 +OP4 E00764 0 +OP4 E00765 0 +OP4 E00766 0 +OP4 E00767 0 +OP4 E00768 0 +OP4 E00769 0 +OP4 E0076A 0 +OP4 E0076B 0 +OP4 E0076C 0 +OP4 E0076D 0 +OP4 E0076E 0 +OP4 E0076F 0 +OP4 E00770 0 +OP4 E00771 0 +OP4 E00772 0 +OP4 E00773 0 +OP4 E00774 0 +OP4 E00775 0 +OP4 E00776 0 +OP4 E00777 0 +OP4 E00778 0 +OP4 E00779 0 +OP4 E0077A 0 +OP4 E0077B 0 +OP4 E0077C 0 +OP4 E0077D 0 +OP4 E0077E 0 +OP4 E0077F 0 +OP4 E00780 0 +OP4 E00781 0 +OP4 E00782 0 +OP4 E00783 0 +OP4 E00784 0 +OP4 E00785 0 +OP4 E00786 0 +OP4 E00787 0 +OP4 E00788 0 +OP4 E00789 0 +OP4 E0078A 0 +OP4 E0078B 0 +OP4 E0078C 0 +OP4 E0078D 0 +OP4 E0078E 0 +OP4 E0078F 0 +OP4 E00790 0 +OP4 E00791 0 +OP4 E00792 0 +OP4 E00793 0 +OP4 E00794 0 +OP4 E00795 0 +OP4 E00796 0 +OP4 E00797 0 +OP4 E00798 0 +OP4 E00799 0 +OP4 E0079A 0 +OP4 E0079B 0 +OP4 E0079C 0 +OP4 E0079D 0 +OP4 E0079E 0 +OP4 E0079F 0 +OP4 E007A0 0 +OP4 E007A1 0 +OP4 E007A2 0 +OP4 E007A3 0 +OP4 E007A4 0 +OP4 E007A5 0 +OP4 E007A6 0 +OP4 E007A7 0 +OP4 E007A8 0 +OP4 E007A9 0 +OP4 E007AA 0 +OP4 E007AB 0 +OP4 E007AC 0 +OP4 E007AD 0 +OP4 E007AE 0 +OP4 E007AF 0 +OP4 E007B0 0 +OP4 E007B1 0 +OP4 E007B2 0 +OP4 E007B3 0 +OP4 E007B4 0 +OP4 E007B5 0 +OP4 E007B6 0 +OP4 E007B7 0 +OP4 E007B8 0 +OP4 E007B9 0 +OP4 E007BA 0 +OP4 E007BB 0 +OP4 E007BC 0 +OP4 E007BD 0 +OP4 E007BE 0 +OP4 E007BF 0 +OP4 E007C0 0 +OP4 E007C1 0 +OP4 E007C2 0 +OP4 E007C3 0 +OP4 E007C4 0 +OP4 E007C5 0 +OP4 E007C6 0 +OP4 E007C7 0 +OP4 E007C8 0 +OP4 E007C9 0 +OP4 E007CA 0 +OP4 E007CB 0 +OP4 E007CC 0 +OP4 E007CD 0 +OP4 E007CE 0 +OP4 E007CF 0 +OP4 E007D0 0 +OP4 E007D1 0 +OP4 E007D2 0 +OP4 E007D3 0 +OP4 E007D4 0 +OP4 E007D5 0 +OP4 E007D6 0 +OP4 E007D7 0 +OP4 E007D8 0 +OP4 E007D9 0 +OP4 E007DA 0 +OP4 E007DB 0 +OP4 E007DC 0 +OP4 E007DD 0 +OP4 E007DE 0 +OP4 E007DF 0 +OP4 E007E0 0 +OP4 E007E1 0 +OP4 E007E2 0 +OP4 E007E3 0 +OP4 E007E4 0 +OP4 E007E5 0 +OP4 E007E6 0 +OP4 E007E7 0 +OP4 E007E8 0 +OP4 E007E9 0 +OP4 E007EA 0 +OP4 E007EB 0 +OP4 E007EC 0 +OP4 E007ED 0 +OP4 E007EE 0 +OP4 E007EF 0 +OP4 E007F0 0 +OP4 E007F1 0 +OP4 E007F2 0 +OP4 E007F3 0 +OP4 E007F4 0 +OP4 E007F5 0 +OP4 E007F6 0 +OP4 E007F7 0 +OP4 E007F8 0 +OP4 E007F9 0 +OP4 E007FA 0 +OP4 E007FB 0 +OP4 E007FC 0 +OP4 E007FD 0 +OP4 E007FE 0 +OP4 E007FF 0 +OP4 E00800 0 +OP4 E00801 0 +OP4 E00802 0 +OP4 E00803 0 +OP4 E00804 0 +OP4 E00805 0 +OP4 E00806 0 +OP4 E00807 0 +OP4 E00808 0 +OP4 E00809 0 +OP4 E0080A 0 +OP4 E0080B 0 +OP4 E0080C 0 +OP4 E0080D 0 +OP4 E0080E 0 +OP4 E0080F 0 +OP4 E00810 0 +OP4 E00811 0 +OP4 E00812 0 +OP4 E00813 0 +OP4 E00814 0 +OP4 E00815 0 +OP4 E00816 0 +OP4 E00817 0 +OP4 E00818 0 +OP4 E00819 0 +OP4 E0081A 0 +OP4 E0081B 0 +OP4 E0081C 0 +OP4 E0081D 0 +OP4 E0081E 0 +OP4 E0081F 0 +OP4 E00820 0 +OP4 E00821 0 +OP4 E00822 0 +OP4 E00823 0 +OP4 E00824 0 +OP4 E00825 0 +OP4 E00826 0 +OP4 E00827 0 +OP4 E00828 0 +OP4 E00829 0 +OP4 E0082A 0 +OP4 E0082B 0 +OP4 E0082C 0 +OP4 E0082D 0 +OP4 E0082E 0 +OP4 E0082F 0 +OP4 E00830 0 +OP4 E00831 0 +OP4 E00832 0 +OP4 E00833 0 +OP4 E00834 0 +OP4 E00835 0 +OP4 E00836 0 +OP4 E00837 0 +OP4 E00838 0 +OP4 E00839 0 +OP4 E0083A 0 +OP4 E0083B 0 +OP4 E0083C 0 +OP4 E0083D 0 +OP4 E0083E 0 +OP4 E0083F 0 +OP4 E00840 0 +OP4 E00841 0 +OP4 E00842 0 +OP4 E00843 0 +OP4 E00844 0 +OP4 E00845 0 +OP4 E00846 0 +OP4 E00847 0 +OP4 E00848 0 +OP4 E00849 0 +OP4 E0084A 0 +OP4 E0084B 0 +OP4 E0084C 0 +OP4 E0084D 0 +OP4 E0084E 0 +OP4 E0084F 0 +OP4 E00850 0 +OP4 E00851 0 +OP4 E00852 0 +OP4 E00853 0 +OP4 E00854 0 +OP4 E00855 0 +OP4 E00856 0 +OP4 E00857 0 +OP4 E00858 0 +OP4 E00859 0 +OP4 E0085A 0 +OP4 E0085B 0 +OP4 E0085C 0 +OP4 E0085D 0 +OP4 E0085E 0 +OP4 E0085F 0 +OP4 E00860 0 +OP4 E00861 0 +OP4 E00862 0 +OP4 E00863 0 +OP4 E00864 0 +OP4 E00865 0 +OP4 E00866 0 +OP4 E00867 0 +OP4 E00868 0 +OP4 E00869 0 +OP4 E0086A 0 +OP4 E0086B 0 +OP4 E0086C 0 +OP4 E0086D 0 +OP4 E0086E 0 +OP4 E0086F 0 +OP4 E00870 0 +OP4 E00871 0 +OP4 E00872 0 +OP4 E00873 0 +OP4 E00874 0 +OP4 E00875 0 +OP4 E00876 0 +OP4 E00877 0 +OP4 E00878 0 +OP4 E00879 0 +OP4 E0087A 0 +OP4 E0087B 0 +OP4 E0087C 0 +OP4 E0087D 0 +OP4 E0087E 0 +OP4 E0087F 0 +OP4 E00880 0 +OP4 E00881 0 +OP4 E00882 0 +OP4 E00883 0 +OP4 E00884 0 +OP4 E00885 0 +OP4 E00886 0 +OP4 E00887 0 +OP4 E00888 0 +OP4 E00889 0 +OP4 E0088A 0 +OP4 E0088B 0 +OP4 E0088C 0 +OP4 E0088D 0 +OP4 E0088E 0 +OP4 E0088F 0 +OP4 E00890 0 +OP4 E00891 0 +OP4 E00892 0 +OP4 E00893 0 +OP4 E00894 0 +OP4 E00895 0 +OP4 E00896 0 +OP4 E00897 0 +OP4 E00898 0 +OP4 E00899 0 +OP4 E0089A 0 +OP4 E0089B 0 +OP4 E0089C 0 +OP4 E0089D 0 +OP4 E0089E 0 +OP4 E0089F 0 +OP4 E008A0 0 +OP4 E008A1 0 +OP4 E008A2 0 +OP4 E008A3 0 +OP4 E008A4 0 +OP4 E008A5 0 +OP4 E008A6 0 +OP4 E008A7 0 +OP4 E008A8 0 +OP4 E008A9 0 +OP4 E008AA 0 +OP4 E008AB 0 +OP4 E008AC 0 +OP4 E008AD 0 +OP4 E008AE 0 +OP4 E008AF 0 +OP4 E008B0 0 +OP4 E008B1 0 +OP4 E008B2 0 +OP4 E008B3 0 +OP4 E008B4 0 +OP4 E008B5 0 +OP4 E008B6 0 +OP4 E008B7 0 +OP4 E008B8 0 +OP4 E008B9 0 +OP4 E008BA 0 +OP4 E008BB 0 +OP4 E008BC 0 +OP4 E008BD 0 +OP4 E008BE 0 +OP4 E008BF 0 +OP4 E008C0 0 +OP4 E008C1 0 +OP4 E008C2 0 +OP4 E008C3 0 +OP4 E008C4 0 +OP4 E008C5 0 +OP4 E008C6 0 +OP4 E008C7 0 +OP4 E008C8 0 +OP4 E008C9 0 +OP4 E008CA 0 +OP4 E008CB 0 +OP4 E008CC 0 +OP4 E008CD 0 +OP4 E008CE 0 +OP4 E008CF 0 +OP4 E008D0 0 +OP4 E008D1 0 +OP4 E008D2 0 +OP4 E008D3 0 +OP4 E008D4 0 +OP4 E008D5 0 +OP4 E008D6 0 +OP4 E008D7 0 +OP4 E008D8 0 +OP4 E008D9 0 +OP4 E008DA 0 +OP4 E008DB 0 +OP4 E008DC 0 +OP4 E008DD 0 +OP4 E008DE 0 +OP4 E008DF 0 +OP4 E008E0 0 +OP4 E008E1 0 +OP4 E008E2 0 +OP4 E008E3 0 +OP4 E008E4 0 +OP4 E008E5 0 +OP4 E008E6 0 +OP4 E008E7 0 +OP4 E008E8 0 +OP4 E008E9 0 +OP4 E008EA 0 +OP4 E008EB 0 +OP4 E008EC 0 +OP4 E008ED 0 +OP4 E008EE 0 +OP4 E008EF 0 +OP4 E008F0 0 +OP4 E008F1 0 +OP4 E008F2 0 +OP4 E008F3 0 +OP4 E008F4 0 +OP4 E008F5 0 +OP4 E008F6 0 +OP4 E008F7 0 +OP4 E008F8 0 +OP4 E008F9 0 +OP4 E008FA 0 +OP4 E008FB 0 +OP4 E008FC 0 +OP4 E008FD 0 +OP4 E008FE 0 +OP4 E008FF 0 +OP4 E00900 0 +OP4 E00901 0 +OP4 E00902 0 +OP4 E00903 0 +OP4 E00904 0 +OP4 E00905 0 +OP4 E00906 0 +OP4 E00907 0 +OP4 E00908 0 +OP4 E00909 0 +OP4 E0090A 0 +OP4 E0090B 0 +OP4 E0090C 0 +OP4 E0090D 0 +OP4 E0090E 0 +OP4 E0090F 0 +OP4 E00910 0 +OP4 E00911 0 +OP4 E00912 0 +OP4 E00913 0 +OP4 E00914 0 +OP4 E00915 0 +OP4 E00916 0 +OP4 E00917 0 +OP4 E00918 0 +OP4 E00919 0 +OP4 E0091A 0 +OP4 E0091B 0 +OP4 E0091C 0 +OP4 E0091D 0 +OP4 E0091E 0 +OP4 E0091F 0 +OP4 E00920 0 +OP4 E00921 0 +OP4 E00922 0 +OP4 E00923 0 +OP4 E00924 0 +OP4 E00925 0 +OP4 E00926 0 +OP4 E00927 0 +OP4 E00928 0 +OP4 E00929 0 +OP4 E0092A 0 +OP4 E0092B 0 +OP4 E0092C 0 +OP4 E0092D 0 +OP4 E0092E 0 +OP4 E0092F 0 +OP4 E00930 0 +OP4 E00931 0 +OP4 E00932 0 +OP4 E00933 0 +OP4 E00934 0 +OP4 E00935 0 +OP4 E00936 0 +OP4 E00937 0 +OP4 E00938 0 +OP4 E00939 0 +OP4 E0093A 0 +OP4 E0093B 0 +OP4 E0093C 0 +OP4 E0093D 0 +OP4 E0093E 0 +OP4 E0093F 0 +OP4 E00940 0 +OP4 E00941 0 +OP4 E00942 0 +OP4 E00943 0 +OP4 E00944 0 +OP4 E00945 0 +OP4 E00946 0 +OP4 E00947 0 +OP4 E00948 0 +OP4 E00949 0 +OP4 E0094A 0 +OP4 E0094B 0 +OP4 E0094C 0 +OP4 E0094D 0 +OP4 E0094E 0 +OP4 E0094F 0 +OP4 E00950 0 +OP4 E00951 0 +OP4 E00952 0 +OP4 E00953 0 +OP4 E00954 0 +OP4 E00955 0 +OP4 E00956 0 +OP4 E00957 0 +OP4 E00958 0 +OP4 E00959 0 +OP4 E0095A 0 +OP4 E0095B 0 +OP4 E0095C 0 +OP4 E0095D 0 +OP4 E0095E 0 +OP4 E0095F 0 +OP4 E00960 0 +OP4 E00961 0 +OP4 E00962 0 +OP4 E00963 0 +OP4 E00964 0 +OP4 E00965 0 +OP4 E00966 0 +OP4 E00967 0 +OP4 E00968 0 +OP4 E00969 0 +OP4 E0096A 0 +OP4 E0096B 0 +OP4 E0096C 0 +OP4 E0096D 0 +OP4 E0096E 0 +OP4 E0096F 0 +OP4 E00970 0 +OP4 E00971 0 +OP4 E00972 0 +OP4 E00973 0 +OP4 E00974 0 +OP4 E00975 0 +OP4 E00976 0 +OP4 E00977 0 +OP4 E00978 0 +OP4 E00979 0 +OP4 E0097A 0 +OP4 E0097B 0 +OP4 E0097C 0 +OP4 E0097D 0 +OP4 E0097E 0 +OP4 E0097F 0 +OP4 E00980 0 +OP4 E00981 0 +OP4 E00982 0 +OP4 E00983 0 +OP4 E00984 0 +OP4 E00985 0 +OP4 E00986 0 +OP4 E00987 0 +OP4 E00988 0 +OP4 E00989 0 +OP4 E0098A 0 +OP4 E0098B 0 +OP4 E0098C 0 +OP4 E0098D 0 +OP4 E0098E 0 +OP4 E0098F 0 +OP4 E00990 0 +OP4 E00991 0 +OP4 E00992 0 +OP4 E00993 0 +OP4 E00994 0 +OP4 E00995 0 +OP4 E00996 0 +OP4 E00997 0 +OP4 E00998 0 +OP4 E00999 0 +OP4 E0099A 0 +OP4 E0099B 0 +OP4 E0099C 0 +OP4 E0099D 0 +OP4 E0099E 0 +OP4 E0099F 0 +OP4 E009A0 0 +OP4 E009A1 0 +OP4 E009A2 0 +OP4 E009A3 0 +OP4 E009A4 0 +OP4 E009A5 0 +OP4 E009A6 0 +OP4 E009A7 0 +OP4 E009A8 0 +OP4 E009A9 0 +OP4 E009AA 0 +OP4 E009AB 0 +OP4 E009AC 0 +OP4 E009AD 0 +OP4 E009AE 0 +OP4 E009AF 0 +OP4 E009B0 0 +OP4 E009B1 0 +OP4 E009B2 0 +OP4 E009B3 0 +OP4 E009B4 0 +OP4 E009B5 0 +OP4 E009B6 0 +OP4 E009B7 0 +OP4 E009B8 0 +OP4 E009B9 0 +OP4 E009BA 0 +OP4 E009BB 0 +OP4 E009BC 0 +OP4 E009BD 0 +OP4 E009BE 0 +OP4 E009BF 0 +OP4 E009C0 0 +OP4 E009C1 0 +OP4 E009C2 0 +OP4 E009C3 0 +OP4 E009C4 0 +OP4 E009C5 0 +OP4 E009C6 0 +OP4 E009C7 0 +OP4 E009C8 0 +OP4 E009C9 0 +OP4 E009CA 0 +OP4 E009CB 0 +OP4 E009CC 0 +OP4 E009CD 0 +OP4 E009CE 0 +OP4 E009CF 0 +OP4 E009D0 0 +OP4 E009D1 0 +OP4 E009D2 0 +OP4 E009D3 0 +OP4 E009D4 0 +OP4 E009D5 0 +OP4 E009D6 0 +OP4 E009D7 0 +OP4 E009D8 0 +OP4 E009D9 0 +OP4 E009DA 0 +OP4 E009DB 0 +OP4 E009DC 0 +OP4 E009DD 0 +OP4 E009DE 0 +OP4 E009DF 0 +OP4 E009E0 0 +OP4 E009E1 0 +OP4 E009E2 0 +OP4 E009E3 0 +OP4 E009E4 0 +OP4 E009E5 0 +OP4 E009E6 0 +OP4 E009E7 0 +OP4 E009E8 0 +OP4 E009E9 0 +OP4 E009EA 0 +OP4 E009EB 0 +OP4 E009EC 0 +OP4 E009ED 0 +OP4 E009EE 0 +OP4 E009EF 0 +OP4 E009F0 0 +OP4 E009F1 0 +OP4 E009F2 0 +OP4 E009F3 0 +OP4 E009F4 0 +OP4 E009F5 0 +OP4 E009F6 0 +OP4 E009F7 0 +OP4 E009F8 0 +OP4 E009F9 0 +OP4 E009FA 0 +OP4 E009FB 0 +OP4 E009FC 0 +OP4 E009FD 0 +OP4 E009FE 0 +OP4 E009FF 0 +OP4 E00A00 0 +OP4 E00A01 0 +OP4 E00A02 0 +OP4 E00A03 0 +OP4 E00A04 0 +OP4 E00A05 0 +OP4 E00A06 0 +OP4 E00A07 0 +OP4 E00A08 0 diff --git a/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum2_itrace_irisc3.cfg.ext b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum2_itrace_irisc3.cfg.ext new file mode 100644 index 000000000000..044a59991f94 --- /dev/null +++ b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum2_itrace_irisc3.cfg.ext @@ -0,0 +1,2570 @@ +OP1 Spectrum2 +OP4 ITRACE0 0 +OP4 ITRACE1 0 +OP4 ITRACE2 0 +OP4 ITRACE3 1 +OP4 ITRACE4 0 +OP4 ITRACE5 0 +OP4 ITRACE6 0 +OP4 ITRACE7 0 +OP4 Main_PhyUC 0 +OP4 E00009 0 +OP4 E0000A 0 +OP4 E0000B 0 +OP4 E0000C 0 +OP4 E0000D 0 +OP4 E0000E 0 +OP4 E0000F 0 +OP4 E00010 0 +OP4 E00011 0 +OP4 E00012 0 +OP4 E00013 0 +OP4 E00014 0 +OP4 E00015 0 +OP4 E00016 0 +OP4 E00017 0 +OP4 E00018 0 +OP4 E00019 0 +OP4 E0001A 0 +OP4 E0001B 0 +OP4 E0001C 0 +OP4 E0001D 0 +OP4 E0001E 0 +OP4 E0001F 0 +OP4 E00020 0 +OP4 E00021 0 +OP4 E00022 0 +OP4 E00023 0 +OP4 E00024 0 +OP4 E00025 0 +OP4 E00026 0 +OP4 E00027 0 +OP4 E00028 0 +OP4 E00029 0 +OP4 E0002A 0 +OP4 E0002B 0 +OP4 E0002C 0 +OP4 E0002D 0 +OP4 E0002E 0 +OP4 E0002F 0 +OP4 E00030 0 +OP4 E00031 0 +OP4 E00032 0 +OP4 E00033 0 +OP4 E00034 0 +OP4 E00035 0 +OP4 E00036 0 +OP4 E00037 0 +OP4 E00038 0 +OP4 E00039 0 +OP4 E0003A 0 +OP4 E0003B 0 +OP4 E0003C 0 +OP4 E0003D 0 +OP4 E0003E 0 +OP4 E0003F 0 +OP4 E00040 0 +OP4 E00041 0 +OP4 E00042 0 +OP4 E00043 0 +OP4 E00044 0 +OP4 E00045 0 +OP4 E00046 0 +OP4 E00047 0 +OP4 E00048 0 +OP4 E00049 0 +OP4 E0004A 0 +OP4 E0004B 0 +OP4 E0004C 0 +OP4 E0004D 0 +OP4 E0004E 0 +OP4 E0004F 0 +OP4 E00050 0 +OP4 E00051 0 +OP4 E00052 0 +OP4 E00053 0 +OP4 E00054 0 +OP4 E00055 0 +OP4 E00056 0 +OP4 E00057 0 +OP4 E00058 0 +OP4 E00059 0 +OP4 E0005A 0 +OP4 E0005B 0 +OP4 E0005C 0 +OP4 E0005D 0 +OP4 E0005E 0 +OP4 E0005F 0 +OP4 E00060 0 +OP4 E00061 0 +OP4 E00062 0 +OP4 E00063 0 +OP4 E00064 0 +OP4 E00065 0 +OP4 E00066 0 +OP4 E00067 0 +OP4 E00068 0 +OP4 E00069 0 +OP4 E0006A 0 +OP4 E0006B 0 +OP4 E0006C 0 +OP4 E0006D 0 +OP4 E0006E 0 +OP4 E0006F 0 +OP4 E00070 0 +OP4 E00071 0 +OP4 E00072 0 +OP4 E00073 0 +OP4 E00074 0 +OP4 E00075 0 +OP4 E00076 0 +OP4 E00077 0 +OP4 E00078 0 +OP4 E00079 0 +OP4 E0007A 0 +OP4 E0007B 0 +OP4 E0007C 0 +OP4 E0007D 0 +OP4 E0007E 0 +OP4 E0007F 0 +OP4 E00080 0 +OP4 E00081 0 +OP4 E00082 0 +OP4 E00083 0 +OP4 E00084 0 +OP4 E00085 0 +OP4 E00086 0 +OP4 E00087 0 +OP4 E00088 0 +OP4 E00089 0 +OP4 E0008A 0 +OP4 E0008B 0 +OP4 E0008C 0 +OP4 E0008D 0 +OP4 E0008E 0 +OP4 E0008F 0 +OP4 E00090 0 +OP4 E00091 0 +OP4 E00092 0 +OP4 E00093 0 +OP4 E00094 0 +OP4 E00095 0 +OP4 E00096 0 +OP4 E00097 0 +OP4 E00098 0 +OP4 E00099 0 +OP4 E0009A 0 +OP4 E0009B 0 +OP4 E0009C 0 +OP4 E0009D 0 +OP4 E0009E 0 +OP4 E0009F 0 +OP4 E000A0 0 +OP4 E000A1 0 +OP4 E000A2 0 +OP4 E000A3 0 +OP4 E000A4 0 +OP4 E000A5 0 +OP4 E000A6 0 +OP4 E000A7 0 +OP4 E000A8 0 +OP4 E000A9 0 +OP4 E000AA 0 +OP4 E000AB 0 +OP4 E000AC 0 +OP4 E000AD 0 +OP4 E000AE 0 +OP4 E000AF 0 +OP4 E000B0 0 +OP4 E000B1 0 +OP4 E000B2 0 +OP4 E000B3 0 +OP4 E000B4 0 +OP4 E000B5 0 +OP4 E000B6 0 +OP4 E000B7 0 +OP4 E000B8 0 +OP4 E000B9 0 +OP4 E000BA 0 +OP4 E000BB 0 +OP4 E000BC 0 +OP4 E000BD 0 +OP4 E000BE 0 +OP4 E000BF 0 +OP4 E000C0 0 +OP4 E000C1 0 +OP4 E000C2 0 +OP4 E000C3 0 +OP4 E000C4 0 +OP4 E000C5 0 +OP4 E000C6 0 +OP4 E000C7 0 +OP4 E000C8 0 +OP4 E000C9 0 +OP4 E000CA 0 +OP4 E000CB 0 +OP4 E000CC 0 +OP4 E000CD 0 +OP4 E000CE 0 +OP4 E000CF 0 +OP4 E000D0 0 +OP4 E000D1 0 +OP4 E000D2 0 +OP4 E000D3 0 +OP4 E000D4 0 +OP4 E000D5 0 +OP4 E000D6 0 +OP4 E000D7 0 +OP4 E000D8 0 +OP4 E000D9 0 +OP4 E000DA 0 +OP4 E000DB 0 +OP4 E000DC 0 +OP4 E000DD 0 +OP4 E000DE 0 +OP4 E000DF 0 +OP4 E000E0 0 +OP4 E000E1 0 +OP4 E000E2 0 +OP4 E000E3 0 +OP4 E000E4 0 +OP4 E000E5 0 +OP4 E000E6 0 +OP4 E000E7 0 +OP4 E000E8 0 +OP4 E000E9 0 +OP4 E000EA 0 +OP4 E000EB 0 +OP4 E000EC 0 +OP4 E000ED 0 +OP4 E000EE 0 +OP4 E000EF 0 +OP4 E000F0 0 +OP4 E000F1 0 +OP4 E000F2 0 +OP4 E000F3 0 +OP4 E000F4 0 +OP4 E000F5 0 +OP4 E000F6 0 +OP4 E000F7 0 +OP4 E000F8 0 +OP4 E000F9 0 +OP4 E000FA 0 +OP4 E000FB 0 +OP4 E000FC 0 +OP4 E000FD 0 +OP4 E000FE 0 +OP4 E000FF 0 +OP4 E00100 0 +OP4 E00101 0 +OP4 E00102 0 +OP4 E00103 0 +OP4 E00104 0 +OP4 E00105 0 +OP4 E00106 0 +OP4 E00107 0 +OP4 E00108 0 +OP4 E00109 0 +OP4 E0010A 0 +OP4 E0010B 0 +OP4 E0010C 0 +OP4 E0010D 0 +OP4 E0010E 0 +OP4 E0010F 0 +OP4 E00110 0 +OP4 E00111 0 +OP4 E00112 0 +OP4 E00113 0 +OP4 E00114 0 +OP4 E00115 0 +OP4 E00116 0 +OP4 E00117 0 +OP4 E00118 0 +OP4 E00119 0 +OP4 E0011A 0 +OP4 E0011B 0 +OP4 E0011C 0 +OP4 E0011D 0 +OP4 E0011E 0 +OP4 E0011F 0 +OP4 E00120 0 +OP4 E00121 0 +OP4 E00122 0 +OP4 E00123 0 +OP4 E00124 0 +OP4 E00125 0 +OP4 E00126 0 +OP4 E00127 0 +OP4 E00128 0 +OP4 E00129 0 +OP4 E0012A 0 +OP4 E0012B 0 +OP4 E0012C 0 +OP4 E0012D 0 +OP4 E0012E 0 +OP4 E0012F 0 +OP4 E00130 0 +OP4 E00131 0 +OP4 E00132 0 +OP4 E00133 0 +OP4 E00134 0 +OP4 E00135 0 +OP4 E00136 0 +OP4 E00137 0 +OP4 E00138 0 +OP4 E00139 0 +OP4 E0013A 0 +OP4 E0013B 0 +OP4 E0013C 0 +OP4 E0013D 0 +OP4 E0013E 0 +OP4 E0013F 0 +OP4 E00140 0 +OP4 E00141 0 +OP4 E00142 0 +OP4 E00143 0 +OP4 E00144 0 +OP4 E00145 0 +OP4 E00146 0 +OP4 E00147 0 +OP4 E00148 0 +OP4 E00149 0 +OP4 E0014A 0 +OP4 E0014B 0 +OP4 E0014C 0 +OP4 E0014D 0 +OP4 E0014E 0 +OP4 E0014F 0 +OP4 E00150 0 +OP4 E00151 0 +OP4 E00152 0 +OP4 E00153 0 +OP4 E00154 0 +OP4 E00155 0 +OP4 E00156 0 +OP4 E00157 0 +OP4 E00158 0 +OP4 E00159 0 +OP4 E0015A 0 +OP4 E0015B 0 +OP4 E0015C 0 +OP4 E0015D 0 +OP4 E0015E 0 +OP4 E0015F 0 +OP4 E00160 0 +OP4 E00161 0 +OP4 E00162 0 +OP4 E00163 0 +OP4 E00164 0 +OP4 E00165 0 +OP4 E00166 0 +OP4 E00167 0 +OP4 E00168 0 +OP4 E00169 0 +OP4 E0016A 0 +OP4 E0016B 0 +OP4 E0016C 0 +OP4 E0016D 0 +OP4 E0016E 0 +OP4 E0016F 0 +OP4 E00170 0 +OP4 E00171 0 +OP4 E00172 0 +OP4 E00173 0 +OP4 E00174 0 +OP4 E00175 0 +OP4 E00176 0 +OP4 E00177 0 +OP4 E00178 0 +OP4 E00179 0 +OP4 E0017A 0 +OP4 E0017B 0 +OP4 E0017C 0 +OP4 E0017D 0 +OP4 E0017E 0 +OP4 E0017F 0 +OP4 E00180 0 +OP4 E00181 0 +OP4 E00182 0 +OP4 E00183 0 +OP4 E00184 0 +OP4 E00185 0 +OP4 E00186 0 +OP4 E00187 0 +OP4 E00188 0 +OP4 E00189 0 +OP4 E0018A 0 +OP4 E0018B 0 +OP4 E0018C 0 +OP4 E0018D 0 +OP4 E0018E 0 +OP4 E0018F 0 +OP4 E00190 0 +OP4 E00191 0 +OP4 E00192 0 +OP4 E00193 0 +OP4 E00194 0 +OP4 E00195 0 +OP4 E00196 0 +OP4 E00197 0 +OP4 E00198 0 +OP4 E00199 0 +OP4 E0019A 0 +OP4 E0019B 0 +OP4 E0019C 0 +OP4 E0019D 0 +OP4 E0019E 0 +OP4 E0019F 0 +OP4 E001A0 0 +OP4 E001A1 0 +OP4 E001A2 0 +OP4 E001A3 0 +OP4 E001A4 0 +OP4 E001A5 0 +OP4 E001A6 0 +OP4 E001A7 0 +OP4 E001A8 0 +OP4 E001A9 0 +OP4 E001AA 0 +OP4 E001AB 0 +OP4 E001AC 0 +OP4 E001AD 0 +OP4 E001AE 0 +OP4 E001AF 0 +OP4 E001B0 0 +OP4 E001B1 0 +OP4 E001B2 0 +OP4 E001B3 0 +OP4 E001B4 0 +OP4 E001B5 0 +OP4 E001B6 0 +OP4 E001B7 0 +OP4 E001B8 0 +OP4 E001B9 0 +OP4 E001BA 0 +OP4 E001BB 0 +OP4 E001BC 0 +OP4 E001BD 0 +OP4 E001BE 0 +OP4 E001BF 0 +OP4 E001C0 0 +OP4 E001C1 0 +OP4 E001C2 0 +OP4 E001C3 0 +OP4 E001C4 0 +OP4 E001C5 0 +OP4 E001C6 0 +OP4 E001C7 0 +OP4 E001C8 0 +OP4 E001C9 0 +OP4 E001CA 0 +OP4 E001CB 0 +OP4 E001CC 0 +OP4 E001CD 0 +OP4 E001CE 0 +OP4 E001CF 0 +OP4 E001D0 0 +OP4 E001D1 0 +OP4 E001D2 0 +OP4 E001D3 0 +OP4 E001D4 0 +OP4 E001D5 0 +OP4 E001D6 0 +OP4 E001D7 0 +OP4 E001D8 0 +OP4 E001D9 0 +OP4 E001DA 0 +OP4 E001DB 0 +OP4 E001DC 0 +OP4 E001DD 0 +OP4 E001DE 0 +OP4 E001DF 0 +OP4 E001E0 0 +OP4 E001E1 0 +OP4 E001E2 0 +OP4 E001E3 0 +OP4 E001E4 0 +OP4 E001E5 0 +OP4 E001E6 0 +OP4 E001E7 0 +OP4 E001E8 0 +OP4 E001E9 0 +OP4 E001EA 0 +OP4 E001EB 0 +OP4 E001EC 0 +OP4 E001ED 0 +OP4 E001EE 0 +OP4 E001EF 0 +OP4 E001F0 0 +OP4 E001F1 0 +OP4 E001F2 0 +OP4 E001F3 0 +OP4 E001F4 0 +OP4 E001F5 0 +OP4 E001F6 0 +OP4 E001F7 0 +OP4 E001F8 0 +OP4 E001F9 0 +OP4 E001FA 0 +OP4 E001FB 0 +OP4 E001FC 0 +OP4 E001FD 0 +OP4 E001FE 0 +OP4 E001FF 0 +OP4 E00200 0 +OP4 E00201 0 +OP4 E00202 0 +OP4 E00203 0 +OP4 E00204 0 +OP4 E00205 0 +OP4 E00206 0 +OP4 E00207 0 +OP4 E00208 0 +OP4 E00209 0 +OP4 E0020A 0 +OP4 E0020B 0 +OP4 E0020C 0 +OP4 E0020D 0 +OP4 E0020E 0 +OP4 E0020F 0 +OP4 E00210 0 +OP4 E00211 0 +OP4 E00212 0 +OP4 E00213 0 +OP4 E00214 0 +OP4 E00215 0 +OP4 E00216 0 +OP4 E00217 0 +OP4 E00218 0 +OP4 E00219 0 +OP4 E0021A 0 +OP4 E0021B 0 +OP4 E0021C 0 +OP4 E0021D 0 +OP4 E0021E 0 +OP4 E0021F 0 +OP4 E00220 0 +OP4 E00221 0 +OP4 E00222 0 +OP4 E00223 0 +OP4 E00224 0 +OP4 E00225 0 +OP4 E00226 0 +OP4 E00227 0 +OP4 E00228 0 +OP4 E00229 0 +OP4 E0022A 0 +OP4 E0022B 0 +OP4 E0022C 0 +OP4 E0022D 0 +OP4 E0022E 0 +OP4 E0022F 0 +OP4 E00230 0 +OP4 E00231 0 +OP4 E00232 0 +OP4 E00233 0 +OP4 E00234 0 +OP4 E00235 0 +OP4 E00236 0 +OP4 E00237 0 +OP4 E00238 0 +OP4 E00239 0 +OP4 E0023A 0 +OP4 E0023B 0 +OP4 E0023C 0 +OP4 E0023D 0 +OP4 E0023E 0 +OP4 E0023F 0 +OP4 E00240 0 +OP4 E00241 0 +OP4 E00242 0 +OP4 E00243 0 +OP4 E00244 0 +OP4 E00245 0 +OP4 E00246 0 +OP4 E00247 0 +OP4 E00248 0 +OP4 E00249 0 +OP4 E0024A 0 +OP4 E0024B 0 +OP4 E0024C 0 +OP4 E0024D 0 +OP4 E0024E 0 +OP4 E0024F 0 +OP4 E00250 0 +OP4 E00251 0 +OP4 E00252 0 +OP4 E00253 0 +OP4 E00254 0 +OP4 E00255 0 +OP4 E00256 0 +OP4 E00257 0 +OP4 E00258 0 +OP4 E00259 0 +OP4 E0025A 0 +OP4 E0025B 0 +OP4 E0025C 0 +OP4 E0025D 0 +OP4 E0025E 0 +OP4 E0025F 0 +OP4 E00260 0 +OP4 E00261 0 +OP4 E00262 0 +OP4 E00263 0 +OP4 E00264 0 +OP4 E00265 0 +OP4 E00266 0 +OP4 E00267 0 +OP4 E00268 0 +OP4 E00269 0 +OP4 E0026A 0 +OP4 E0026B 0 +OP4 E0026C 0 +OP4 E0026D 0 +OP4 E0026E 0 +OP4 E0026F 0 +OP4 E00270 0 +OP4 E00271 0 +OP4 E00272 0 +OP4 E00273 0 +OP4 E00274 0 +OP4 E00275 0 +OP4 E00276 0 +OP4 E00277 0 +OP4 E00278 0 +OP4 E00279 0 +OP4 E0027A 0 +OP4 E0027B 0 +OP4 E0027C 0 +OP4 E0027D 0 +OP4 E0027E 0 +OP4 E0027F 0 +OP4 E00280 0 +OP4 E00281 0 +OP4 E00282 0 +OP4 E00283 0 +OP4 E00284 0 +OP4 E00285 0 +OP4 E00286 0 +OP4 E00287 0 +OP4 E00288 0 +OP4 E00289 0 +OP4 E0028A 0 +OP4 E0028B 0 +OP4 E0028C 0 +OP4 E0028D 0 +OP4 E0028E 0 +OP4 E0028F 0 +OP4 E00290 0 +OP4 E00291 0 +OP4 E00292 0 +OP4 E00293 0 +OP4 E00294 0 +OP4 E00295 0 +OP4 E00296 0 +OP4 E00297 0 +OP4 E00298 0 +OP4 E00299 0 +OP4 E0029A 0 +OP4 E0029B 0 +OP4 E0029C 0 +OP4 E0029D 0 +OP4 E0029E 0 +OP4 E0029F 0 +OP4 E002A0 0 +OP4 E002A1 0 +OP4 E002A2 0 +OP4 E002A3 0 +OP4 E002A4 0 +OP4 E002A5 0 +OP4 E002A6 0 +OP4 E002A7 0 +OP4 E002A8 0 +OP4 E002A9 0 +OP4 E002AA 0 +OP4 E002AB 0 +OP4 E002AC 0 +OP4 E002AD 0 +OP4 E002AE 0 +OP4 E002AF 0 +OP4 E002B0 0 +OP4 E002B1 0 +OP4 E002B2 0 +OP4 E002B3 0 +OP4 E002B4 0 +OP4 E002B5 0 +OP4 E002B6 0 +OP4 E002B7 0 +OP4 E002B8 0 +OP4 E002B9 0 +OP4 E002BA 0 +OP4 E002BB 0 +OP4 E002BC 0 +OP4 E002BD 0 +OP4 E002BE 0 +OP4 E002BF 0 +OP4 E002C0 0 +OP4 E002C1 0 +OP4 E002C2 0 +OP4 E002C3 0 +OP4 E002C4 0 +OP4 E002C5 0 +OP4 E002C6 0 +OP4 E002C7 0 +OP4 E002C8 0 +OP4 E002C9 0 +OP4 E002CA 0 +OP4 E002CB 0 +OP4 E002CC 0 +OP4 E002CD 0 +OP4 E002CE 0 +OP4 E002CF 0 +OP4 E002D0 0 +OP4 E002D1 0 +OP4 E002D2 0 +OP4 E002D3 0 +OP4 E002D4 0 +OP4 E002D5 0 +OP4 E002D6 0 +OP4 E002D7 0 +OP4 E002D8 0 +OP4 E002D9 0 +OP4 E002DA 0 +OP4 E002DB 0 +OP4 E002DC 0 +OP4 E002DD 0 +OP4 E002DE 0 +OP4 E002DF 0 +OP4 E002E0 0 +OP4 E002E1 0 +OP4 E002E2 0 +OP4 E002E3 0 +OP4 E002E4 0 +OP4 E002E5 0 +OP4 E002E6 0 +OP4 E002E7 0 +OP4 E002E8 0 +OP4 E002E9 0 +OP4 E002EA 0 +OP4 E002EB 0 +OP4 E002EC 0 +OP4 E002ED 0 +OP4 E002EE 0 +OP4 E002EF 0 +OP4 E002F0 0 +OP4 E002F1 0 +OP4 E002F2 0 +OP4 E002F3 0 +OP4 E002F4 0 +OP4 E002F5 0 +OP4 E002F6 0 +OP4 E002F7 0 +OP4 E002F8 0 +OP4 E002F9 0 +OP4 E002FA 0 +OP4 E002FB 0 +OP4 E002FC 0 +OP4 E002FD 0 +OP4 E002FE 0 +OP4 E002FF 0 +OP4 E00300 0 +OP4 E00301 0 +OP4 E00302 0 +OP4 E00303 0 +OP4 E00304 0 +OP4 E00305 0 +OP4 E00306 0 +OP4 E00307 0 +OP4 E00308 0 +OP4 E00309 0 +OP4 E0030A 0 +OP4 E0030B 0 +OP4 E0030C 0 +OP4 E0030D 0 +OP4 E0030E 0 +OP4 E0030F 0 +OP4 E00310 0 +OP4 E00311 0 +OP4 E00312 0 +OP4 E00313 0 +OP4 E00314 0 +OP4 E00315 0 +OP4 E00316 0 +OP4 E00317 0 +OP4 E00318 0 +OP4 E00319 0 +OP4 E0031A 0 +OP4 E0031B 0 +OP4 E0031C 0 +OP4 E0031D 0 +OP4 E0031E 0 +OP4 E0031F 0 +OP4 E00320 0 +OP4 E00321 0 +OP4 E00322 0 +OP4 E00323 0 +OP4 E00324 0 +OP4 E00325 0 +OP4 E00326 0 +OP4 E00327 0 +OP4 E00328 0 +OP4 E00329 0 +OP4 E0032A 0 +OP4 E0032B 0 +OP4 E0032C 0 +OP4 E0032D 0 +OP4 E0032E 0 +OP4 E0032F 0 +OP4 E00330 0 +OP4 E00331 0 +OP4 E00332 0 +OP4 E00333 0 +OP4 E00334 0 +OP4 E00335 0 +OP4 E00336 0 +OP4 E00337 0 +OP4 E00338 0 +OP4 E00339 0 +OP4 E0033A 0 +OP4 E0033B 0 +OP4 E0033C 0 +OP4 E0033D 0 +OP4 E0033E 0 +OP4 E0033F 0 +OP4 E00340 0 +OP4 E00341 0 +OP4 E00342 0 +OP4 E00343 0 +OP4 E00344 0 +OP4 E00345 0 +OP4 E00346 0 +OP4 E00347 0 +OP4 E00348 0 +OP4 E00349 0 +OP4 E0034A 0 +OP4 E0034B 0 +OP4 E0034C 0 +OP4 E0034D 0 +OP4 E0034E 0 +OP4 E0034F 0 +OP4 E00350 0 +OP4 E00351 0 +OP4 E00352 0 +OP4 E00353 0 +OP4 E00354 0 +OP4 E00355 0 +OP4 E00356 0 +OP4 E00357 0 +OP4 E00358 0 +OP4 E00359 0 +OP4 E0035A 0 +OP4 E0035B 0 +OP4 E0035C 0 +OP4 E0035D 0 +OP4 E0035E 0 +OP4 E0035F 0 +OP4 E00360 0 +OP4 E00361 0 +OP4 E00362 0 +OP4 E00363 0 +OP4 E00364 0 +OP4 E00365 0 +OP4 E00366 0 +OP4 E00367 0 +OP4 E00368 0 +OP4 E00369 0 +OP4 E0036A 0 +OP4 E0036B 0 +OP4 E0036C 0 +OP4 E0036D 0 +OP4 E0036E 0 +OP4 E0036F 0 +OP4 E00370 0 +OP4 E00371 0 +OP4 E00372 0 +OP4 E00373 0 +OP4 E00374 0 +OP4 E00375 0 +OP4 E00376 0 +OP4 E00377 0 +OP4 E00378 0 +OP4 E00379 0 +OP4 E0037A 0 +OP4 E0037B 0 +OP4 E0037C 0 +OP4 E0037D 0 +OP4 E0037E 0 +OP4 E0037F 0 +OP4 E00380 0 +OP4 E00381 0 +OP4 E00382 0 +OP4 E00383 0 +OP4 E00384 0 +OP4 E00385 0 +OP4 E00386 0 +OP4 E00387 0 +OP4 E00388 0 +OP4 E00389 0 +OP4 E0038A 0 +OP4 E0038B 0 +OP4 E0038C 0 +OP4 E0038D 0 +OP4 E0038E 0 +OP4 E0038F 0 +OP4 E00390 0 +OP4 E00391 0 +OP4 E00392 0 +OP4 E00393 0 +OP4 E00394 0 +OP4 E00395 0 +OP4 E00396 0 +OP4 E00397 0 +OP4 E00398 0 +OP4 E00399 0 +OP4 E0039A 0 +OP4 E0039B 0 +OP4 E0039C 0 +OP4 E0039D 0 +OP4 E0039E 0 +OP4 E0039F 0 +OP4 E003A0 0 +OP4 E003A1 0 +OP4 E003A2 0 +OP4 E003A3 0 +OP4 E003A4 0 +OP4 E003A5 0 +OP4 E003A6 0 +OP4 E003A7 0 +OP4 E003A8 0 +OP4 E003A9 0 +OP4 E003AA 0 +OP4 E003AB 0 +OP4 E003AC 0 +OP4 E003AD 0 +OP4 E003AE 0 +OP4 E003AF 0 +OP4 E003B0 0 +OP4 E003B1 0 +OP4 E003B2 0 +OP4 E003B3 0 +OP4 E003B4 0 +OP4 E003B5 0 +OP4 E003B6 0 +OP4 E003B7 0 +OP4 E003B8 0 +OP4 E003B9 0 +OP4 E003BA 0 +OP4 E003BB 0 +OP4 E003BC 0 +OP4 E003BD 0 +OP4 E003BE 0 +OP4 E003BF 0 +OP4 E003C0 0 +OP4 E003C1 0 +OP4 E003C2 0 +OP4 E003C3 0 +OP4 E003C4 0 +OP4 E003C5 0 +OP4 E003C6 0 +OP4 E003C7 0 +OP4 E003C8 0 +OP4 E003C9 0 +OP4 E003CA 0 +OP4 E003CB 0 +OP4 E003CC 0 +OP4 E003CD 0 +OP4 E003CE 0 +OP4 E003CF 0 +OP4 E003D0 0 +OP4 E003D1 0 +OP4 E003D2 0 +OP4 E003D3 0 +OP4 E003D4 0 +OP4 E003D5 0 +OP4 E003D6 0 +OP4 E003D7 0 +OP4 E003D8 0 +OP4 E003D9 0 +OP4 E003DA 0 +OP4 E003DB 0 +OP4 E003DC 0 +OP4 E003DD 0 +OP4 E003DE 0 +OP4 E003DF 0 +OP4 E003E0 0 +OP4 E003E1 0 +OP4 E003E2 0 +OP4 E003E3 0 +OP4 E003E4 0 +OP4 E003E5 0 +OP4 E003E6 0 +OP4 E003E7 0 +OP4 E003E8 0 +OP4 E003E9 0 +OP4 E003EA 0 +OP4 E003EB 0 +OP4 E003EC 0 +OP4 E003ED 0 +OP4 E003EE 0 +OP4 E003EF 0 +OP4 E003F0 0 +OP4 E003F1 0 +OP4 E003F2 0 +OP4 E003F3 0 +OP4 E003F4 0 +OP4 E003F5 0 +OP4 E003F6 0 +OP4 E003F7 0 +OP4 E003F8 0 +OP4 E003F9 0 +OP4 E003FA 0 +OP4 E003FB 0 +OP4 E003FC 0 +OP4 E003FD 0 +OP4 E003FE 0 +OP4 E003FF 0 +OP4 E00400 0 +OP4 E00401 0 +OP4 E00402 0 +OP4 E00403 0 +OP4 E00404 0 +OP4 E00405 0 +OP4 E00406 0 +OP4 E00407 0 +OP4 E00408 0 +OP4 E00409 0 +OP4 E0040A 0 +OP4 E0040B 0 +OP4 E0040C 0 +OP4 E0040D 0 +OP4 E0040E 0 +OP4 E0040F 0 +OP4 E00410 0 +OP4 E00411 0 +OP4 E00412 0 +OP4 E00413 0 +OP4 E00414 0 +OP4 E00415 0 +OP4 E00416 0 +OP4 E00417 0 +OP4 E00418 0 +OP4 E00419 0 +OP4 E0041A 0 +OP4 E0041B 0 +OP4 E0041C 0 +OP4 E0041D 0 +OP4 E0041E 0 +OP4 E0041F 0 +OP4 E00420 0 +OP4 E00421 0 +OP4 E00422 0 +OP4 E00423 0 +OP4 E00424 0 +OP4 E00425 0 +OP4 E00426 0 +OP4 E00427 0 +OP4 E00428 0 +OP4 E00429 0 +OP4 E0042A 0 +OP4 E0042B 0 +OP4 E0042C 0 +OP4 E0042D 0 +OP4 E0042E 0 +OP4 E0042F 0 +OP4 E00430 0 +OP4 E00431 0 +OP4 E00432 0 +OP4 E00433 0 +OP4 E00434 0 +OP4 E00435 0 +OP4 E00436 0 +OP4 E00437 0 +OP4 E00438 0 +OP4 E00439 0 +OP4 E0043A 0 +OP4 E0043B 0 +OP4 E0043C 0 +OP4 E0043D 0 +OP4 E0043E 0 +OP4 E0043F 0 +OP4 E00440 0 +OP4 E00441 0 +OP4 E00442 0 +OP4 E00443 0 +OP4 E00444 0 +OP4 E00445 0 +OP4 E00446 0 +OP4 E00447 0 +OP4 E00448 0 +OP4 E00449 0 +OP4 E0044A 0 +OP4 E0044B 0 +OP4 E0044C 0 +OP4 E0044D 0 +OP4 E0044E 0 +OP4 E0044F 0 +OP4 E00450 0 +OP4 E00451 0 +OP4 E00452 0 +OP4 E00453 0 +OP4 E00454 0 +OP4 E00455 0 +OP4 E00456 0 +OP4 E00457 0 +OP4 E00458 0 +OP4 E00459 0 +OP4 E0045A 0 +OP4 E0045B 0 +OP4 E0045C 0 +OP4 E0045D 0 +OP4 E0045E 0 +OP4 E0045F 0 +OP4 E00460 0 +OP4 E00461 0 +OP4 E00462 0 +OP4 E00463 0 +OP4 E00464 0 +OP4 E00465 0 +OP4 E00466 0 +OP4 E00467 0 +OP4 E00468 0 +OP4 E00469 0 +OP4 E0046A 0 +OP4 E0046B 0 +OP4 E0046C 0 +OP4 E0046D 0 +OP4 E0046E 0 +OP4 E0046F 0 +OP4 E00470 0 +OP4 E00471 0 +OP4 E00472 0 +OP4 E00473 0 +OP4 E00474 0 +OP4 E00475 0 +OP4 E00476 0 +OP4 E00477 0 +OP4 E00478 0 +OP4 E00479 0 +OP4 E0047A 0 +OP4 E0047B 0 +OP4 E0047C 0 +OP4 E0047D 0 +OP4 E0047E 0 +OP4 E0047F 0 +OP4 E00480 0 +OP4 E00481 0 +OP4 E00482 0 +OP4 E00483 0 +OP4 E00484 0 +OP4 E00485 0 +OP4 E00486 0 +OP4 E00487 0 +OP4 E00488 0 +OP4 E00489 0 +OP4 E0048A 0 +OP4 E0048B 0 +OP4 E0048C 0 +OP4 E0048D 0 +OP4 E0048E 0 +OP4 E0048F 0 +OP4 E00490 0 +OP4 E00491 0 +OP4 E00492 0 +OP4 E00493 0 +OP4 E00494 0 +OP4 E00495 0 +OP4 E00496 0 +OP4 E00497 0 +OP4 E00498 0 +OP4 E00499 0 +OP4 E0049A 0 +OP4 E0049B 0 +OP4 E0049C 0 +OP4 E0049D 0 +OP4 E0049E 0 +OP4 E0049F 0 +OP4 E004A0 0 +OP4 E004A1 0 +OP4 E004A2 0 +OP4 E004A3 0 +OP4 E004A4 0 +OP4 E004A5 0 +OP4 E004A6 0 +OP4 E004A7 0 +OP4 E004A8 0 +OP4 E004A9 0 +OP4 E004AA 0 +OP4 E004AB 0 +OP4 E004AC 0 +OP4 E004AD 0 +OP4 E004AE 0 +OP4 E004AF 0 +OP4 E004B0 0 +OP4 E004B1 0 +OP4 E004B2 0 +OP4 E004B3 0 +OP4 E004B4 0 +OP4 E004B5 0 +OP4 E004B6 0 +OP4 E004B7 0 +OP4 E004B8 0 +OP4 E004B9 0 +OP4 E004BA 0 +OP4 E004BB 0 +OP4 E004BC 0 +OP4 E004BD 0 +OP4 E004BE 0 +OP4 E004BF 0 +OP4 E004C0 0 +OP4 E004C1 0 +OP4 E004C2 0 +OP4 E004C3 0 +OP4 E004C4 0 +OP4 E004C5 0 +OP4 E004C6 0 +OP4 E004C7 0 +OP4 E004C8 0 +OP4 E004C9 0 +OP4 E004CA 0 +OP4 E004CB 0 +OP4 E004CC 0 +OP4 E004CD 0 +OP4 E004CE 0 +OP4 E004CF 0 +OP4 E004D0 0 +OP4 E004D1 0 +OP4 E004D2 0 +OP4 E004D3 0 +OP4 E004D4 0 +OP4 E004D5 0 +OP4 E004D6 0 +OP4 E004D7 0 +OP4 E004D8 0 +OP4 E004D9 0 +OP4 E004DA 0 +OP4 E004DB 0 +OP4 E004DC 0 +OP4 E004DD 0 +OP4 E004DE 0 +OP4 E004DF 0 +OP4 E004E0 0 +OP4 E004E1 0 +OP4 E004E2 0 +OP4 E004E3 0 +OP4 E004E4 0 +OP4 E004E5 0 +OP4 E004E6 0 +OP4 E004E7 0 +OP4 E004E8 0 +OP4 E004E9 0 +OP4 E004EA 0 +OP4 E004EB 0 +OP4 E004EC 0 +OP4 E004ED 0 +OP4 E004EE 0 +OP4 E004EF 0 +OP4 E004F0 0 +OP4 E004F1 0 +OP4 E004F2 0 +OP4 E004F3 0 +OP4 E004F4 0 +OP4 E004F5 0 +OP4 E004F6 0 +OP4 E004F7 0 +OP4 E004F8 0 +OP4 E004F9 0 +OP4 E004FA 0 +OP4 E004FB 0 +OP4 E004FC 0 +OP4 E004FD 0 +OP4 E004FE 0 +OP4 E004FF 0 +OP4 E00500 0 +OP4 E00501 0 +OP4 E00502 0 +OP4 E00503 0 +OP4 E00504 0 +OP4 E00505 0 +OP4 E00506 0 +OP4 E00507 0 +OP4 E00508 0 +OP4 E00509 0 +OP4 E0050A 0 +OP4 E0050B 0 +OP4 E0050C 0 +OP4 E0050D 0 +OP4 E0050E 0 +OP4 E0050F 0 +OP4 E00510 0 +OP4 E00511 0 +OP4 E00512 0 +OP4 E00513 0 +OP4 E00514 0 +OP4 E00515 0 +OP4 E00516 0 +OP4 E00517 0 +OP4 E00518 0 +OP4 E00519 0 +OP4 E0051A 0 +OP4 E0051B 0 +OP4 E0051C 0 +OP4 E0051D 0 +OP4 E0051E 0 +OP4 E0051F 0 +OP4 E00520 0 +OP4 E00521 0 +OP4 E00522 0 +OP4 E00523 0 +OP4 E00524 0 +OP4 E00525 0 +OP4 E00526 0 +OP4 E00527 0 +OP4 E00528 0 +OP4 E00529 0 +OP4 E0052A 0 +OP4 E0052B 0 +OP4 E0052C 0 +OP4 E0052D 0 +OP4 E0052E 0 +OP4 E0052F 0 +OP4 E00530 0 +OP4 E00531 0 +OP4 E00532 0 +OP4 E00533 0 +OP4 E00534 0 +OP4 E00535 0 +OP4 E00536 0 +OP4 E00537 0 +OP4 E00538 0 +OP4 E00539 0 +OP4 E0053A 0 +OP4 E0053B 0 +OP4 E0053C 0 +OP4 E0053D 0 +OP4 E0053E 0 +OP4 E0053F 0 +OP4 E00540 0 +OP4 E00541 0 +OP4 E00542 0 +OP4 E00543 0 +OP4 E00544 0 +OP4 E00545 0 +OP4 E00546 0 +OP4 E00547 0 +OP4 E00548 0 +OP4 E00549 0 +OP4 E0054A 0 +OP4 E0054B 0 +OP4 E0054C 0 +OP4 E0054D 0 +OP4 E0054E 0 +OP4 E0054F 0 +OP4 E00550 0 +OP4 E00551 0 +OP4 E00552 0 +OP4 E00553 0 +OP4 E00554 0 +OP4 E00555 0 +OP4 E00556 0 +OP4 E00557 0 +OP4 E00558 0 +OP4 E00559 0 +OP4 E0055A 0 +OP4 E0055B 0 +OP4 E0055C 0 +OP4 E0055D 0 +OP4 E0055E 0 +OP4 E0055F 0 +OP4 E00560 0 +OP4 E00561 0 +OP4 E00562 0 +OP4 E00563 0 +OP4 E00564 0 +OP4 E00565 0 +OP4 E00566 0 +OP4 E00567 0 +OP4 E00568 0 +OP4 E00569 0 +OP4 E0056A 0 +OP4 E0056B 0 +OP4 E0056C 0 +OP4 E0056D 0 +OP4 E0056E 0 +OP4 E0056F 0 +OP4 E00570 0 +OP4 E00571 0 +OP4 E00572 0 +OP4 E00573 0 +OP4 E00574 0 +OP4 E00575 0 +OP4 E00576 0 +OP4 E00577 0 +OP4 E00578 0 +OP4 E00579 0 +OP4 E0057A 0 +OP4 E0057B 0 +OP4 E0057C 0 +OP4 E0057D 0 +OP4 E0057E 0 +OP4 E0057F 0 +OP4 E00580 0 +OP4 E00581 0 +OP4 E00582 0 +OP4 E00583 0 +OP4 E00584 0 +OP4 E00585 0 +OP4 E00586 0 +OP4 E00587 0 +OP4 E00588 0 +OP4 E00589 0 +OP4 E0058A 0 +OP4 E0058B 0 +OP4 E0058C 0 +OP4 E0058D 0 +OP4 E0058E 0 +OP4 E0058F 0 +OP4 E00590 0 +OP4 E00591 0 +OP4 E00592 0 +OP4 E00593 0 +OP4 E00594 0 +OP4 E00595 0 +OP4 E00596 0 +OP4 E00597 0 +OP4 E00598 0 +OP4 E00599 0 +OP4 E0059A 0 +OP4 E0059B 0 +OP4 E0059C 0 +OP4 E0059D 0 +OP4 E0059E 0 +OP4 E0059F 0 +OP4 E005A0 0 +OP4 E005A1 0 +OP4 E005A2 0 +OP4 E005A3 0 +OP4 E005A4 0 +OP4 E005A5 0 +OP4 E005A6 0 +OP4 E005A7 0 +OP4 E005A8 0 +OP4 E005A9 0 +OP4 E005AA 0 +OP4 E005AB 0 +OP4 E005AC 0 +OP4 E005AD 0 +OP4 E005AE 0 +OP4 E005AF 0 +OP4 E005B0 0 +OP4 E005B1 0 +OP4 E005B2 0 +OP4 E005B3 0 +OP4 E005B4 0 +OP4 E005B5 0 +OP4 E005B6 0 +OP4 E005B7 0 +OP4 E005B8 0 +OP4 E005B9 0 +OP4 E005BA 0 +OP4 E005BB 0 +OP4 E005BC 0 +OP4 E005BD 0 +OP4 E005BE 0 +OP4 E005BF 0 +OP4 E005C0 0 +OP4 E005C1 0 +OP4 E005C2 0 +OP4 E005C3 0 +OP4 E005C4 0 +OP4 E005C5 0 +OP4 E005C6 0 +OP4 E005C7 0 +OP4 E005C8 0 +OP4 E005C9 0 +OP4 E005CA 0 +OP4 E005CB 0 +OP4 E005CC 0 +OP4 E005CD 0 +OP4 E005CE 0 +OP4 E005CF 0 +OP4 E005D0 0 +OP4 E005D1 0 +OP4 E005D2 0 +OP4 E005D3 0 +OP4 E005D4 0 +OP4 E005D5 0 +OP4 E005D6 0 +OP4 E005D7 0 +OP4 E005D8 0 +OP4 E005D9 0 +OP4 E005DA 0 +OP4 E005DB 0 +OP4 E005DC 0 +OP4 E005DD 0 +OP4 E005DE 0 +OP4 E005DF 0 +OP4 E005E0 0 +OP4 E005E1 0 +OP4 E005E2 0 +OP4 E005E3 0 +OP4 E005E4 0 +OP4 E005E5 0 +OP4 E005E6 0 +OP4 E005E7 0 +OP4 E005E8 0 +OP4 E005E9 0 +OP4 E005EA 0 +OP4 E005EB 0 +OP4 E005EC 0 +OP4 E005ED 0 +OP4 E005EE 0 +OP4 E005EF 0 +OP4 E005F0 0 +OP4 E005F1 0 +OP4 E005F2 0 +OP4 E005F3 0 +OP4 E005F4 0 +OP4 E005F5 0 +OP4 E005F6 0 +OP4 E005F7 0 +OP4 E005F8 0 +OP4 E005F9 0 +OP4 E005FA 0 +OP4 E005FB 0 +OP4 E005FC 0 +OP4 E005FD 0 +OP4 E005FE 0 +OP4 E005FF 0 +OP4 E00600 0 +OP4 E00601 0 +OP4 E00602 0 +OP4 E00603 0 +OP4 E00604 0 +OP4 E00605 0 +OP4 E00606 0 +OP4 E00607 0 +OP4 E00608 0 +OP4 E00609 0 +OP4 E0060A 0 +OP4 E0060B 0 +OP4 E0060C 0 +OP4 E0060D 0 +OP4 E0060E 0 +OP4 E0060F 0 +OP4 E00610 0 +OP4 E00611 0 +OP4 E00612 0 +OP4 E00613 0 +OP4 E00614 0 +OP4 E00615 0 +OP4 E00616 0 +OP4 E00617 0 +OP4 E00618 0 +OP4 E00619 0 +OP4 E0061A 0 +OP4 E0061B 0 +OP4 E0061C 0 +OP4 E0061D 0 +OP4 E0061E 0 +OP4 E0061F 0 +OP4 E00620 0 +OP4 E00621 0 +OP4 E00622 0 +OP4 E00623 0 +OP4 E00624 0 +OP4 E00625 0 +OP4 E00626 0 +OP4 E00627 0 +OP4 E00628 0 +OP4 E00629 0 +OP4 E0062A 0 +OP4 E0062B 0 +OP4 E0062C 0 +OP4 E0062D 0 +OP4 E0062E 0 +OP4 E0062F 0 +OP4 E00630 0 +OP4 E00631 0 +OP4 E00632 0 +OP4 E00633 0 +OP4 E00634 0 +OP4 E00635 0 +OP4 E00636 0 +OP4 E00637 0 +OP4 E00638 0 +OP4 E00639 0 +OP4 E0063A 0 +OP4 E0063B 0 +OP4 E0063C 0 +OP4 E0063D 0 +OP4 E0063E 0 +OP4 E0063F 0 +OP4 E00640 0 +OP4 E00641 0 +OP4 E00642 0 +OP4 E00643 0 +OP4 E00644 0 +OP4 E00645 0 +OP4 E00646 0 +OP4 E00647 0 +OP4 E00648 0 +OP4 E00649 0 +OP4 E0064A 0 +OP4 E0064B 0 +OP4 E0064C 0 +OP4 E0064D 0 +OP4 E0064E 0 +OP4 E0064F 0 +OP4 E00650 0 +OP4 E00651 0 +OP4 E00652 0 +OP4 E00653 0 +OP4 E00654 0 +OP4 E00655 0 +OP4 E00656 0 +OP4 E00657 0 +OP4 E00658 0 +OP4 E00659 0 +OP4 E0065A 0 +OP4 E0065B 0 +OP4 E0065C 0 +OP4 E0065D 0 +OP4 E0065E 0 +OP4 E0065F 0 +OP4 E00660 0 +OP4 E00661 0 +OP4 E00662 0 +OP4 E00663 0 +OP4 E00664 0 +OP4 E00665 0 +OP4 E00666 0 +OP4 E00667 0 +OP4 E00668 0 +OP4 E00669 0 +OP4 E0066A 0 +OP4 E0066B 0 +OP4 E0066C 0 +OP4 E0066D 0 +OP4 E0066E 0 +OP4 E0066F 0 +OP4 E00670 0 +OP4 E00671 0 +OP4 E00672 0 +OP4 E00673 0 +OP4 E00674 0 +OP4 E00675 0 +OP4 E00676 0 +OP4 E00677 0 +OP4 E00678 0 +OP4 E00679 0 +OP4 E0067A 0 +OP4 E0067B 0 +OP4 E0067C 0 +OP4 E0067D 0 +OP4 E0067E 0 +OP4 E0067F 0 +OP4 E00680 0 +OP4 E00681 0 +OP4 E00682 0 +OP4 E00683 0 +OP4 E00684 0 +OP4 E00685 0 +OP4 E00686 0 +OP4 E00687 0 +OP4 E00688 0 +OP4 E00689 0 +OP4 E0068A 0 +OP4 E0068B 0 +OP4 E0068C 0 +OP4 E0068D 0 +OP4 E0068E 0 +OP4 E0068F 0 +OP4 E00690 0 +OP4 E00691 0 +OP4 E00692 0 +OP4 E00693 0 +OP4 E00694 0 +OP4 E00695 0 +OP4 E00696 0 +OP4 E00697 0 +OP4 E00698 0 +OP4 E00699 0 +OP4 E0069A 0 +OP4 E0069B 0 +OP4 E0069C 0 +OP4 E0069D 0 +OP4 E0069E 0 +OP4 E0069F 0 +OP4 E006A0 0 +OP4 E006A1 0 +OP4 E006A2 0 +OP4 E006A3 0 +OP4 E006A4 0 +OP4 E006A5 0 +OP4 E006A6 0 +OP4 E006A7 0 +OP4 E006A8 0 +OP4 E006A9 0 +OP4 E006AA 0 +OP4 E006AB 0 +OP4 E006AC 0 +OP4 E006AD 0 +OP4 E006AE 0 +OP4 E006AF 0 +OP4 E006B0 0 +OP4 E006B1 0 +OP4 E006B2 0 +OP4 E006B3 0 +OP4 E006B4 0 +OP4 E006B5 0 +OP4 E006B6 0 +OP4 E006B7 0 +OP4 E006B8 0 +OP4 E006B9 0 +OP4 E006BA 0 +OP4 E006BB 0 +OP4 E006BC 0 +OP4 E006BD 0 +OP4 E006BE 0 +OP4 E006BF 0 +OP4 E006C0 0 +OP4 E006C1 0 +OP4 E006C2 0 +OP4 E006C3 0 +OP4 E006C4 0 +OP4 E006C5 0 +OP4 E006C6 0 +OP4 E006C7 0 +OP4 E006C8 0 +OP4 E006C9 0 +OP4 E006CA 0 +OP4 E006CB 0 +OP4 E006CC 0 +OP4 E006CD 0 +OP4 E006CE 0 +OP4 E006CF 0 +OP4 E006D0 0 +OP4 E006D1 0 +OP4 E006D2 0 +OP4 E006D3 0 +OP4 E006D4 0 +OP4 E006D5 0 +OP4 E006D6 0 +OP4 E006D7 0 +OP4 E006D8 0 +OP4 E006D9 0 +OP4 E006DA 0 +OP4 E006DB 0 +OP4 E006DC 0 +OP4 E006DD 0 +OP4 E006DE 0 +OP4 E006DF 0 +OP4 E006E0 0 +OP4 E006E1 0 +OP4 E006E2 0 +OP4 E006E3 0 +OP4 E006E4 0 +OP4 E006E5 0 +OP4 E006E6 0 +OP4 E006E7 0 +OP4 E006E8 0 +OP4 E006E9 0 +OP4 E006EA 0 +OP4 E006EB 0 +OP4 E006EC 0 +OP4 E006ED 0 +OP4 E006EE 0 +OP4 E006EF 0 +OP4 E006F0 0 +OP4 E006F1 0 +OP4 E006F2 0 +OP4 E006F3 0 +OP4 E006F4 0 +OP4 E006F5 0 +OP4 E006F6 0 +OP4 E006F7 0 +OP4 E006F8 0 +OP4 E006F9 0 +OP4 E006FA 0 +OP4 E006FB 0 +OP4 E006FC 0 +OP4 E006FD 0 +OP4 E006FE 0 +OP4 E006FF 0 +OP4 E00700 0 +OP4 E00701 0 +OP4 E00702 0 +OP4 E00703 0 +OP4 E00704 0 +OP4 E00705 0 +OP4 E00706 0 +OP4 E00707 0 +OP4 E00708 0 +OP4 E00709 0 +OP4 E0070A 0 +OP4 E0070B 0 +OP4 E0070C 0 +OP4 E0070D 0 +OP4 E0070E 0 +OP4 E0070F 0 +OP4 E00710 0 +OP4 E00711 0 +OP4 E00712 0 +OP4 E00713 0 +OP4 E00714 0 +OP4 E00715 0 +OP4 E00716 0 +OP4 E00717 0 +OP4 E00718 0 +OP4 E00719 0 +OP4 E0071A 0 +OP4 E0071B 0 +OP4 E0071C 0 +OP4 E0071D 0 +OP4 E0071E 0 +OP4 E0071F 0 +OP4 E00720 0 +OP4 E00721 0 +OP4 E00722 0 +OP4 E00723 0 +OP4 E00724 0 +OP4 E00725 0 +OP4 E00726 0 +OP4 E00727 0 +OP4 E00728 0 +OP4 E00729 0 +OP4 E0072A 0 +OP4 E0072B 0 +OP4 E0072C 0 +OP4 E0072D 0 +OP4 E0072E 0 +OP4 E0072F 0 +OP4 E00730 0 +OP4 E00731 0 +OP4 E00732 0 +OP4 E00733 0 +OP4 E00734 0 +OP4 E00735 0 +OP4 E00736 0 +OP4 E00737 0 +OP4 E00738 0 +OP4 E00739 0 +OP4 E0073A 0 +OP4 E0073B 0 +OP4 E0073C 0 +OP4 E0073D 0 +OP4 E0073E 0 +OP4 E0073F 0 +OP4 E00740 0 +OP4 E00741 0 +OP4 E00742 0 +OP4 E00743 0 +OP4 E00744 0 +OP4 E00745 0 +OP4 E00746 0 +OP4 E00747 0 +OP4 E00748 0 +OP4 E00749 0 +OP4 E0074A 0 +OP4 E0074B 0 +OP4 E0074C 0 +OP4 E0074D 0 +OP4 E0074E 0 +OP4 E0074F 0 +OP4 E00750 0 +OP4 E00751 0 +OP4 E00752 0 +OP4 E00753 0 +OP4 E00754 0 +OP4 E00755 0 +OP4 E00756 0 +OP4 E00757 0 +OP4 E00758 0 +OP4 E00759 0 +OP4 E0075A 0 +OP4 E0075B 0 +OP4 E0075C 0 +OP4 E0075D 0 +OP4 E0075E 0 +OP4 E0075F 0 +OP4 E00760 0 +OP4 E00761 0 +OP4 E00762 0 +OP4 E00763 0 +OP4 E00764 0 +OP4 E00765 0 +OP4 E00766 0 +OP4 E00767 0 +OP4 E00768 0 +OP4 E00769 0 +OP4 E0076A 0 +OP4 E0076B 0 +OP4 E0076C 0 +OP4 E0076D 0 +OP4 E0076E 0 +OP4 E0076F 0 +OP4 E00770 0 +OP4 E00771 0 +OP4 E00772 0 +OP4 E00773 0 +OP4 E00774 0 +OP4 E00775 0 +OP4 E00776 0 +OP4 E00777 0 +OP4 E00778 0 +OP4 E00779 0 +OP4 E0077A 0 +OP4 E0077B 0 +OP4 E0077C 0 +OP4 E0077D 0 +OP4 E0077E 0 +OP4 E0077F 0 +OP4 E00780 0 +OP4 E00781 0 +OP4 E00782 0 +OP4 E00783 0 +OP4 E00784 0 +OP4 E00785 0 +OP4 E00786 0 +OP4 E00787 0 +OP4 E00788 0 +OP4 E00789 0 +OP4 E0078A 0 +OP4 E0078B 0 +OP4 E0078C 0 +OP4 E0078D 0 +OP4 E0078E 0 +OP4 E0078F 0 +OP4 E00790 0 +OP4 E00791 0 +OP4 E00792 0 +OP4 E00793 0 +OP4 E00794 0 +OP4 E00795 0 +OP4 E00796 0 +OP4 E00797 0 +OP4 E00798 0 +OP4 E00799 0 +OP4 E0079A 0 +OP4 E0079B 0 +OP4 E0079C 0 +OP4 E0079D 0 +OP4 E0079E 0 +OP4 E0079F 0 +OP4 E007A0 0 +OP4 E007A1 0 +OP4 E007A2 0 +OP4 E007A3 0 +OP4 E007A4 0 +OP4 E007A5 0 +OP4 E007A6 0 +OP4 E007A7 0 +OP4 E007A8 0 +OP4 E007A9 0 +OP4 E007AA 0 +OP4 E007AB 0 +OP4 E007AC 0 +OP4 E007AD 0 +OP4 E007AE 0 +OP4 E007AF 0 +OP4 E007B0 0 +OP4 E007B1 0 +OP4 E007B2 0 +OP4 E007B3 0 +OP4 E007B4 0 +OP4 E007B5 0 +OP4 E007B6 0 +OP4 E007B7 0 +OP4 E007B8 0 +OP4 E007B9 0 +OP4 E007BA 0 +OP4 E007BB 0 +OP4 E007BC 0 +OP4 E007BD 0 +OP4 E007BE 0 +OP4 E007BF 0 +OP4 E007C0 0 +OP4 E007C1 0 +OP4 E007C2 0 +OP4 E007C3 0 +OP4 E007C4 0 +OP4 E007C5 0 +OP4 E007C6 0 +OP4 E007C7 0 +OP4 E007C8 0 +OP4 E007C9 0 +OP4 E007CA 0 +OP4 E007CB 0 +OP4 E007CC 0 +OP4 E007CD 0 +OP4 E007CE 0 +OP4 E007CF 0 +OP4 E007D0 0 +OP4 E007D1 0 +OP4 E007D2 0 +OP4 E007D3 0 +OP4 E007D4 0 +OP4 E007D5 0 +OP4 E007D6 0 +OP4 E007D7 0 +OP4 E007D8 0 +OP4 E007D9 0 +OP4 E007DA 0 +OP4 E007DB 0 +OP4 E007DC 0 +OP4 E007DD 0 +OP4 E007DE 0 +OP4 E007DF 0 +OP4 E007E0 0 +OP4 E007E1 0 +OP4 E007E2 0 +OP4 E007E3 0 +OP4 E007E4 0 +OP4 E007E5 0 +OP4 E007E6 0 +OP4 E007E7 0 +OP4 E007E8 0 +OP4 E007E9 0 +OP4 E007EA 0 +OP4 E007EB 0 +OP4 E007EC 0 +OP4 E007ED 0 +OP4 E007EE 0 +OP4 E007EF 0 +OP4 E007F0 0 +OP4 E007F1 0 +OP4 E007F2 0 +OP4 E007F3 0 +OP4 E007F4 0 +OP4 E007F5 0 +OP4 E007F6 0 +OP4 E007F7 0 +OP4 E007F8 0 +OP4 E007F9 0 +OP4 E007FA 0 +OP4 E007FB 0 +OP4 E007FC 0 +OP4 E007FD 0 +OP4 E007FE 0 +OP4 E007FF 0 +OP4 E00800 0 +OP4 E00801 0 +OP4 E00802 0 +OP4 E00803 0 +OP4 E00804 0 +OP4 E00805 0 +OP4 E00806 0 +OP4 E00807 0 +OP4 E00808 0 +OP4 E00809 0 +OP4 E0080A 0 +OP4 E0080B 0 +OP4 E0080C 0 +OP4 E0080D 0 +OP4 E0080E 0 +OP4 E0080F 0 +OP4 E00810 0 +OP4 E00811 0 +OP4 E00812 0 +OP4 E00813 0 +OP4 E00814 0 +OP4 E00815 0 +OP4 E00816 0 +OP4 E00817 0 +OP4 E00818 0 +OP4 E00819 0 +OP4 E0081A 0 +OP4 E0081B 0 +OP4 E0081C 0 +OP4 E0081D 0 +OP4 E0081E 0 +OP4 E0081F 0 +OP4 E00820 0 +OP4 E00821 0 +OP4 E00822 0 +OP4 E00823 0 +OP4 E00824 0 +OP4 E00825 0 +OP4 E00826 0 +OP4 E00827 0 +OP4 E00828 0 +OP4 E00829 0 +OP4 E0082A 0 +OP4 E0082B 0 +OP4 E0082C 0 +OP4 E0082D 0 +OP4 E0082E 0 +OP4 E0082F 0 +OP4 E00830 0 +OP4 E00831 0 +OP4 E00832 0 +OP4 E00833 0 +OP4 E00834 0 +OP4 E00835 0 +OP4 E00836 0 +OP4 E00837 0 +OP4 E00838 0 +OP4 E00839 0 +OP4 E0083A 0 +OP4 E0083B 0 +OP4 E0083C 0 +OP4 E0083D 0 +OP4 E0083E 0 +OP4 E0083F 0 +OP4 E00840 0 +OP4 E00841 0 +OP4 E00842 0 +OP4 E00843 0 +OP4 E00844 0 +OP4 E00845 0 +OP4 E00846 0 +OP4 E00847 0 +OP4 E00848 0 +OP4 E00849 0 +OP4 E0084A 0 +OP4 E0084B 0 +OP4 E0084C 0 +OP4 E0084D 0 +OP4 E0084E 0 +OP4 E0084F 0 +OP4 E00850 0 +OP4 E00851 0 +OP4 E00852 0 +OP4 E00853 0 +OP4 E00854 0 +OP4 E00855 0 +OP4 E00856 0 +OP4 E00857 0 +OP4 E00858 0 +OP4 E00859 0 +OP4 E0085A 0 +OP4 E0085B 0 +OP4 E0085C 0 +OP4 E0085D 0 +OP4 E0085E 0 +OP4 E0085F 0 +OP4 E00860 0 +OP4 E00861 0 +OP4 E00862 0 +OP4 E00863 0 +OP4 E00864 0 +OP4 E00865 0 +OP4 E00866 0 +OP4 E00867 0 +OP4 E00868 0 +OP4 E00869 0 +OP4 E0086A 0 +OP4 E0086B 0 +OP4 E0086C 0 +OP4 E0086D 0 +OP4 E0086E 0 +OP4 E0086F 0 +OP4 E00870 0 +OP4 E00871 0 +OP4 E00872 0 +OP4 E00873 0 +OP4 E00874 0 +OP4 E00875 0 +OP4 E00876 0 +OP4 E00877 0 +OP4 E00878 0 +OP4 E00879 0 +OP4 E0087A 0 +OP4 E0087B 0 +OP4 E0087C 0 +OP4 E0087D 0 +OP4 E0087E 0 +OP4 E0087F 0 +OP4 E00880 0 +OP4 E00881 0 +OP4 E00882 0 +OP4 E00883 0 +OP4 E00884 0 +OP4 E00885 0 +OP4 E00886 0 +OP4 E00887 0 +OP4 E00888 0 +OP4 E00889 0 +OP4 E0088A 0 +OP4 E0088B 0 +OP4 E0088C 0 +OP4 E0088D 0 +OP4 E0088E 0 +OP4 E0088F 0 +OP4 E00890 0 +OP4 E00891 0 +OP4 E00892 0 +OP4 E00893 0 +OP4 E00894 0 +OP4 E00895 0 +OP4 E00896 0 +OP4 E00897 0 +OP4 E00898 0 +OP4 E00899 0 +OP4 E0089A 0 +OP4 E0089B 0 +OP4 E0089C 0 +OP4 E0089D 0 +OP4 E0089E 0 +OP4 E0089F 0 +OP4 E008A0 0 +OP4 E008A1 0 +OP4 E008A2 0 +OP4 E008A3 0 +OP4 E008A4 0 +OP4 E008A5 0 +OP4 E008A6 0 +OP4 E008A7 0 +OP4 E008A8 0 +OP4 E008A9 0 +OP4 E008AA 0 +OP4 E008AB 0 +OP4 E008AC 0 +OP4 E008AD 0 +OP4 E008AE 0 +OP4 E008AF 0 +OP4 E008B0 0 +OP4 E008B1 0 +OP4 E008B2 0 +OP4 E008B3 0 +OP4 E008B4 0 +OP4 E008B5 0 +OP4 E008B6 0 +OP4 E008B7 0 +OP4 E008B8 0 +OP4 E008B9 0 +OP4 E008BA 0 +OP4 E008BB 0 +OP4 E008BC 0 +OP4 E008BD 0 +OP4 E008BE 0 +OP4 E008BF 0 +OP4 E008C0 0 +OP4 E008C1 0 +OP4 E008C2 0 +OP4 E008C3 0 +OP4 E008C4 0 +OP4 E008C5 0 +OP4 E008C6 0 +OP4 E008C7 0 +OP4 E008C8 0 +OP4 E008C9 0 +OP4 E008CA 0 +OP4 E008CB 0 +OP4 E008CC 0 +OP4 E008CD 0 +OP4 E008CE 0 +OP4 E008CF 0 +OP4 E008D0 0 +OP4 E008D1 0 +OP4 E008D2 0 +OP4 E008D3 0 +OP4 E008D4 0 +OP4 E008D5 0 +OP4 E008D6 0 +OP4 E008D7 0 +OP4 E008D8 0 +OP4 E008D9 0 +OP4 E008DA 0 +OP4 E008DB 0 +OP4 E008DC 0 +OP4 E008DD 0 +OP4 E008DE 0 +OP4 E008DF 0 +OP4 E008E0 0 +OP4 E008E1 0 +OP4 E008E2 0 +OP4 E008E3 0 +OP4 E008E4 0 +OP4 E008E5 0 +OP4 E008E6 0 +OP4 E008E7 0 +OP4 E008E8 0 +OP4 E008E9 0 +OP4 E008EA 0 +OP4 E008EB 0 +OP4 E008EC 0 +OP4 E008ED 0 +OP4 E008EE 0 +OP4 E008EF 0 +OP4 E008F0 0 +OP4 E008F1 0 +OP4 E008F2 0 +OP4 E008F3 0 +OP4 E008F4 0 +OP4 E008F5 0 +OP4 E008F6 0 +OP4 E008F7 0 +OP4 E008F8 0 +OP4 E008F9 0 +OP4 E008FA 0 +OP4 E008FB 0 +OP4 E008FC 0 +OP4 E008FD 0 +OP4 E008FE 0 +OP4 E008FF 0 +OP4 E00900 0 +OP4 E00901 0 +OP4 E00902 0 +OP4 E00903 0 +OP4 E00904 0 +OP4 E00905 0 +OP4 E00906 0 +OP4 E00907 0 +OP4 E00908 0 +OP4 E00909 0 +OP4 E0090A 0 +OP4 E0090B 0 +OP4 E0090C 0 +OP4 E0090D 0 +OP4 E0090E 0 +OP4 E0090F 0 +OP4 E00910 0 +OP4 E00911 0 +OP4 E00912 0 +OP4 E00913 0 +OP4 E00914 0 +OP4 E00915 0 +OP4 E00916 0 +OP4 E00917 0 +OP4 E00918 0 +OP4 E00919 0 +OP4 E0091A 0 +OP4 E0091B 0 +OP4 E0091C 0 +OP4 E0091D 0 +OP4 E0091E 0 +OP4 E0091F 0 +OP4 E00920 0 +OP4 E00921 0 +OP4 E00922 0 +OP4 E00923 0 +OP4 E00924 0 +OP4 E00925 0 +OP4 E00926 0 +OP4 E00927 0 +OP4 E00928 0 +OP4 E00929 0 +OP4 E0092A 0 +OP4 E0092B 0 +OP4 E0092C 0 +OP4 E0092D 0 +OP4 E0092E 0 +OP4 E0092F 0 +OP4 E00930 0 +OP4 E00931 0 +OP4 E00932 0 +OP4 E00933 0 +OP4 E00934 0 +OP4 E00935 0 +OP4 E00936 0 +OP4 E00937 0 +OP4 E00938 0 +OP4 E00939 0 +OP4 E0093A 0 +OP4 E0093B 0 +OP4 E0093C 0 +OP4 E0093D 0 +OP4 E0093E 0 +OP4 E0093F 0 +OP4 E00940 0 +OP4 E00941 0 +OP4 E00942 0 +OP4 E00943 0 +OP4 E00944 0 +OP4 E00945 0 +OP4 E00946 0 +OP4 E00947 0 +OP4 E00948 0 +OP4 E00949 0 +OP4 E0094A 0 +OP4 E0094B 0 +OP4 E0094C 0 +OP4 E0094D 0 +OP4 E0094E 0 +OP4 E0094F 0 +OP4 E00950 0 +OP4 E00951 0 +OP4 E00952 0 +OP4 E00953 0 +OP4 E00954 0 +OP4 E00955 0 +OP4 E00956 0 +OP4 E00957 0 +OP4 E00958 0 +OP4 E00959 0 +OP4 E0095A 0 +OP4 E0095B 0 +OP4 E0095C 0 +OP4 E0095D 0 +OP4 E0095E 0 +OP4 E0095F 0 +OP4 E00960 0 +OP4 E00961 0 +OP4 E00962 0 +OP4 E00963 0 +OP4 E00964 0 +OP4 E00965 0 +OP4 E00966 0 +OP4 E00967 0 +OP4 E00968 0 +OP4 E00969 0 +OP4 E0096A 0 +OP4 E0096B 0 +OP4 E0096C 0 +OP4 E0096D 0 +OP4 E0096E 0 +OP4 E0096F 0 +OP4 E00970 0 +OP4 E00971 0 +OP4 E00972 0 +OP4 E00973 0 +OP4 E00974 0 +OP4 E00975 0 +OP4 E00976 0 +OP4 E00977 0 +OP4 E00978 0 +OP4 E00979 0 +OP4 E0097A 0 +OP4 E0097B 0 +OP4 E0097C 0 +OP4 E0097D 0 +OP4 E0097E 0 +OP4 E0097F 0 +OP4 E00980 0 +OP4 E00981 0 +OP4 E00982 0 +OP4 E00983 0 +OP4 E00984 0 +OP4 E00985 0 +OP4 E00986 0 +OP4 E00987 0 +OP4 E00988 0 +OP4 E00989 0 +OP4 E0098A 0 +OP4 E0098B 0 +OP4 E0098C 0 +OP4 E0098D 0 +OP4 E0098E 0 +OP4 E0098F 0 +OP4 E00990 0 +OP4 E00991 0 +OP4 E00992 0 +OP4 E00993 0 +OP4 E00994 0 +OP4 E00995 0 +OP4 E00996 0 +OP4 E00997 0 +OP4 E00998 0 +OP4 E00999 0 +OP4 E0099A 0 +OP4 E0099B 0 +OP4 E0099C 0 +OP4 E0099D 0 +OP4 E0099E 0 +OP4 E0099F 0 +OP4 E009A0 0 +OP4 E009A1 0 +OP4 E009A2 0 +OP4 E009A3 0 +OP4 E009A4 0 +OP4 E009A5 0 +OP4 E009A6 0 +OP4 E009A7 0 +OP4 E009A8 0 +OP4 E009A9 0 +OP4 E009AA 0 +OP4 E009AB 0 +OP4 E009AC 0 +OP4 E009AD 0 +OP4 E009AE 0 +OP4 E009AF 0 +OP4 E009B0 0 +OP4 E009B1 0 +OP4 E009B2 0 +OP4 E009B3 0 +OP4 E009B4 0 +OP4 E009B5 0 +OP4 E009B6 0 +OP4 E009B7 0 +OP4 E009B8 0 +OP4 E009B9 0 +OP4 E009BA 0 +OP4 E009BB 0 +OP4 E009BC 0 +OP4 E009BD 0 +OP4 E009BE 0 +OP4 E009BF 0 +OP4 E009C0 0 +OP4 E009C1 0 +OP4 E009C2 0 +OP4 E009C3 0 +OP4 E009C4 0 +OP4 E009C5 0 +OP4 E009C6 0 +OP4 E009C7 0 +OP4 E009C8 0 +OP4 E009C9 0 +OP4 E009CA 0 +OP4 E009CB 0 +OP4 E009CC 0 +OP4 E009CD 0 +OP4 E009CE 0 +OP4 E009CF 0 +OP4 E009D0 0 +OP4 E009D1 0 +OP4 E009D2 0 +OP4 E009D3 0 +OP4 E009D4 0 +OP4 E009D5 0 +OP4 E009D6 0 +OP4 E009D7 0 +OP4 E009D8 0 +OP4 E009D9 0 +OP4 E009DA 0 +OP4 E009DB 0 +OP4 E009DC 0 +OP4 E009DD 0 +OP4 E009DE 0 +OP4 E009DF 0 +OP4 E009E0 0 +OP4 E009E1 0 +OP4 E009E2 0 +OP4 E009E3 0 +OP4 E009E4 0 +OP4 E009E5 0 +OP4 E009E6 0 +OP4 E009E7 0 +OP4 E009E8 0 +OP4 E009E9 0 +OP4 E009EA 0 +OP4 E009EB 0 +OP4 E009EC 0 +OP4 E009ED 0 +OP4 E009EE 0 +OP4 E009EF 0 +OP4 E009F0 0 +OP4 E009F1 0 +OP4 E009F2 0 +OP4 E009F3 0 +OP4 E009F4 0 +OP4 E009F5 0 +OP4 E009F6 0 +OP4 E009F7 0 +OP4 E009F8 0 +OP4 E009F9 0 +OP4 E009FA 0 +OP4 E009FB 0 +OP4 E009FC 0 +OP4 E009FD 0 +OP4 E009FE 0 +OP4 E009FF 0 +OP4 E00A00 0 +OP4 E00A01 0 +OP4 E00A02 0 +OP4 E00A03 0 +OP4 E00A04 0 +OP4 E00A05 0 +OP4 E00A06 0 +OP4 E00A07 0 +OP4 E00A08 0 diff --git a/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum2_itrace_irisc4.cfg.ext b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum2_itrace_irisc4.cfg.ext new file mode 100644 index 000000000000..11e1a14745c0 --- /dev/null +++ b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum2_itrace_irisc4.cfg.ext @@ -0,0 +1,2570 @@ +OP1 Spectrum2 +OP4 ITRACE0 0 +OP4 ITRACE1 0 +OP4 ITRACE2 0 +OP4 ITRACE3 0 +OP4 ITRACE4 1 +OP4 ITRACE5 0 +OP4 ITRACE6 0 +OP4 ITRACE7 0 +OP4 Main_PhyUC 0 +OP4 E00009 0 +OP4 E0000A 0 +OP4 E0000B 0 +OP4 E0000C 0 +OP4 E0000D 0 +OP4 E0000E 0 +OP4 E0000F 0 +OP4 E00010 0 +OP4 E00011 0 +OP4 E00012 0 +OP4 E00013 0 +OP4 E00014 0 +OP4 E00015 0 +OP4 E00016 0 +OP4 E00017 0 +OP4 E00018 0 +OP4 E00019 0 +OP4 E0001A 0 +OP4 E0001B 0 +OP4 E0001C 0 +OP4 E0001D 0 +OP4 E0001E 0 +OP4 E0001F 0 +OP4 E00020 0 +OP4 E00021 0 +OP4 E00022 0 +OP4 E00023 0 +OP4 E00024 0 +OP4 E00025 0 +OP4 E00026 0 +OP4 E00027 0 +OP4 E00028 0 +OP4 E00029 0 +OP4 E0002A 0 +OP4 E0002B 0 +OP4 E0002C 0 +OP4 E0002D 0 +OP4 E0002E 0 +OP4 E0002F 0 +OP4 E00030 0 +OP4 E00031 0 +OP4 E00032 0 +OP4 E00033 0 +OP4 E00034 0 +OP4 E00035 0 +OP4 E00036 0 +OP4 E00037 0 +OP4 E00038 0 +OP4 E00039 0 +OP4 E0003A 0 +OP4 E0003B 0 +OP4 E0003C 0 +OP4 E0003D 0 +OP4 E0003E 0 +OP4 E0003F 0 +OP4 E00040 0 +OP4 E00041 0 +OP4 E00042 0 +OP4 E00043 0 +OP4 E00044 0 +OP4 E00045 0 +OP4 E00046 0 +OP4 E00047 0 +OP4 E00048 0 +OP4 E00049 0 +OP4 E0004A 0 +OP4 E0004B 0 +OP4 E0004C 0 +OP4 E0004D 0 +OP4 E0004E 0 +OP4 E0004F 0 +OP4 E00050 0 +OP4 E00051 0 +OP4 E00052 0 +OP4 E00053 0 +OP4 E00054 0 +OP4 E00055 0 +OP4 E00056 0 +OP4 E00057 0 +OP4 E00058 0 +OP4 E00059 0 +OP4 E0005A 0 +OP4 E0005B 0 +OP4 E0005C 0 +OP4 E0005D 0 +OP4 E0005E 0 +OP4 E0005F 0 +OP4 E00060 0 +OP4 E00061 0 +OP4 E00062 0 +OP4 E00063 0 +OP4 E00064 0 +OP4 E00065 0 +OP4 E00066 0 +OP4 E00067 0 +OP4 E00068 0 +OP4 E00069 0 +OP4 E0006A 0 +OP4 E0006B 0 +OP4 E0006C 0 +OP4 E0006D 0 +OP4 E0006E 0 +OP4 E0006F 0 +OP4 E00070 0 +OP4 E00071 0 +OP4 E00072 0 +OP4 E00073 0 +OP4 E00074 0 +OP4 E00075 0 +OP4 E00076 0 +OP4 E00077 0 +OP4 E00078 0 +OP4 E00079 0 +OP4 E0007A 0 +OP4 E0007B 0 +OP4 E0007C 0 +OP4 E0007D 0 +OP4 E0007E 0 +OP4 E0007F 0 +OP4 E00080 0 +OP4 E00081 0 +OP4 E00082 0 +OP4 E00083 0 +OP4 E00084 0 +OP4 E00085 0 +OP4 E00086 0 +OP4 E00087 0 +OP4 E00088 0 +OP4 E00089 0 +OP4 E0008A 0 +OP4 E0008B 0 +OP4 E0008C 0 +OP4 E0008D 0 +OP4 E0008E 0 +OP4 E0008F 0 +OP4 E00090 0 +OP4 E00091 0 +OP4 E00092 0 +OP4 E00093 0 +OP4 E00094 0 +OP4 E00095 0 +OP4 E00096 0 +OP4 E00097 0 +OP4 E00098 0 +OP4 E00099 0 +OP4 E0009A 0 +OP4 E0009B 0 +OP4 E0009C 0 +OP4 E0009D 0 +OP4 E0009E 0 +OP4 E0009F 0 +OP4 E000A0 0 +OP4 E000A1 0 +OP4 E000A2 0 +OP4 E000A3 0 +OP4 E000A4 0 +OP4 E000A5 0 +OP4 E000A6 0 +OP4 E000A7 0 +OP4 E000A8 0 +OP4 E000A9 0 +OP4 E000AA 0 +OP4 E000AB 0 +OP4 E000AC 0 +OP4 E000AD 0 +OP4 E000AE 0 +OP4 E000AF 0 +OP4 E000B0 0 +OP4 E000B1 0 +OP4 E000B2 0 +OP4 E000B3 0 +OP4 E000B4 0 +OP4 E000B5 0 +OP4 E000B6 0 +OP4 E000B7 0 +OP4 E000B8 0 +OP4 E000B9 0 +OP4 E000BA 0 +OP4 E000BB 0 +OP4 E000BC 0 +OP4 E000BD 0 +OP4 E000BE 0 +OP4 E000BF 0 +OP4 E000C0 0 +OP4 E000C1 0 +OP4 E000C2 0 +OP4 E000C3 0 +OP4 E000C4 0 +OP4 E000C5 0 +OP4 E000C6 0 +OP4 E000C7 0 +OP4 E000C8 0 +OP4 E000C9 0 +OP4 E000CA 0 +OP4 E000CB 0 +OP4 E000CC 0 +OP4 E000CD 0 +OP4 E000CE 0 +OP4 E000CF 0 +OP4 E000D0 0 +OP4 E000D1 0 +OP4 E000D2 0 +OP4 E000D3 0 +OP4 E000D4 0 +OP4 E000D5 0 +OP4 E000D6 0 +OP4 E000D7 0 +OP4 E000D8 0 +OP4 E000D9 0 +OP4 E000DA 0 +OP4 E000DB 0 +OP4 E000DC 0 +OP4 E000DD 0 +OP4 E000DE 0 +OP4 E000DF 0 +OP4 E000E0 0 +OP4 E000E1 0 +OP4 E000E2 0 +OP4 E000E3 0 +OP4 E000E4 0 +OP4 E000E5 0 +OP4 E000E6 0 +OP4 E000E7 0 +OP4 E000E8 0 +OP4 E000E9 0 +OP4 E000EA 0 +OP4 E000EB 0 +OP4 E000EC 0 +OP4 E000ED 0 +OP4 E000EE 0 +OP4 E000EF 0 +OP4 E000F0 0 +OP4 E000F1 0 +OP4 E000F2 0 +OP4 E000F3 0 +OP4 E000F4 0 +OP4 E000F5 0 +OP4 E000F6 0 +OP4 E000F7 0 +OP4 E000F8 0 +OP4 E000F9 0 +OP4 E000FA 0 +OP4 E000FB 0 +OP4 E000FC 0 +OP4 E000FD 0 +OP4 E000FE 0 +OP4 E000FF 0 +OP4 E00100 0 +OP4 E00101 0 +OP4 E00102 0 +OP4 E00103 0 +OP4 E00104 0 +OP4 E00105 0 +OP4 E00106 0 +OP4 E00107 0 +OP4 E00108 0 +OP4 E00109 0 +OP4 E0010A 0 +OP4 E0010B 0 +OP4 E0010C 0 +OP4 E0010D 0 +OP4 E0010E 0 +OP4 E0010F 0 +OP4 E00110 0 +OP4 E00111 0 +OP4 E00112 0 +OP4 E00113 0 +OP4 E00114 0 +OP4 E00115 0 +OP4 E00116 0 +OP4 E00117 0 +OP4 E00118 0 +OP4 E00119 0 +OP4 E0011A 0 +OP4 E0011B 0 +OP4 E0011C 0 +OP4 E0011D 0 +OP4 E0011E 0 +OP4 E0011F 0 +OP4 E00120 0 +OP4 E00121 0 +OP4 E00122 0 +OP4 E00123 0 +OP4 E00124 0 +OP4 E00125 0 +OP4 E00126 0 +OP4 E00127 0 +OP4 E00128 0 +OP4 E00129 0 +OP4 E0012A 0 +OP4 E0012B 0 +OP4 E0012C 0 +OP4 E0012D 0 +OP4 E0012E 0 +OP4 E0012F 0 +OP4 E00130 0 +OP4 E00131 0 +OP4 E00132 0 +OP4 E00133 0 +OP4 E00134 0 +OP4 E00135 0 +OP4 E00136 0 +OP4 E00137 0 +OP4 E00138 0 +OP4 E00139 0 +OP4 E0013A 0 +OP4 E0013B 0 +OP4 E0013C 0 +OP4 E0013D 0 +OP4 E0013E 0 +OP4 E0013F 0 +OP4 E00140 0 +OP4 E00141 0 +OP4 E00142 0 +OP4 E00143 0 +OP4 E00144 0 +OP4 E00145 0 +OP4 E00146 0 +OP4 E00147 0 +OP4 E00148 0 +OP4 E00149 0 +OP4 E0014A 0 +OP4 E0014B 0 +OP4 E0014C 0 +OP4 E0014D 0 +OP4 E0014E 0 +OP4 E0014F 0 +OP4 E00150 0 +OP4 E00151 0 +OP4 E00152 0 +OP4 E00153 0 +OP4 E00154 0 +OP4 E00155 0 +OP4 E00156 0 +OP4 E00157 0 +OP4 E00158 0 +OP4 E00159 0 +OP4 E0015A 0 +OP4 E0015B 0 +OP4 E0015C 0 +OP4 E0015D 0 +OP4 E0015E 0 +OP4 E0015F 0 +OP4 E00160 0 +OP4 E00161 0 +OP4 E00162 0 +OP4 E00163 0 +OP4 E00164 0 +OP4 E00165 0 +OP4 E00166 0 +OP4 E00167 0 +OP4 E00168 0 +OP4 E00169 0 +OP4 E0016A 0 +OP4 E0016B 0 +OP4 E0016C 0 +OP4 E0016D 0 +OP4 E0016E 0 +OP4 E0016F 0 +OP4 E00170 0 +OP4 E00171 0 +OP4 E00172 0 +OP4 E00173 0 +OP4 E00174 0 +OP4 E00175 0 +OP4 E00176 0 +OP4 E00177 0 +OP4 E00178 0 +OP4 E00179 0 +OP4 E0017A 0 +OP4 E0017B 0 +OP4 E0017C 0 +OP4 E0017D 0 +OP4 E0017E 0 +OP4 E0017F 0 +OP4 E00180 0 +OP4 E00181 0 +OP4 E00182 0 +OP4 E00183 0 +OP4 E00184 0 +OP4 E00185 0 +OP4 E00186 0 +OP4 E00187 0 +OP4 E00188 0 +OP4 E00189 0 +OP4 E0018A 0 +OP4 E0018B 0 +OP4 E0018C 0 +OP4 E0018D 0 +OP4 E0018E 0 +OP4 E0018F 0 +OP4 E00190 0 +OP4 E00191 0 +OP4 E00192 0 +OP4 E00193 0 +OP4 E00194 0 +OP4 E00195 0 +OP4 E00196 0 +OP4 E00197 0 +OP4 E00198 0 +OP4 E00199 0 +OP4 E0019A 0 +OP4 E0019B 0 +OP4 E0019C 0 +OP4 E0019D 0 +OP4 E0019E 0 +OP4 E0019F 0 +OP4 E001A0 0 +OP4 E001A1 0 +OP4 E001A2 0 +OP4 E001A3 0 +OP4 E001A4 0 +OP4 E001A5 0 +OP4 E001A6 0 +OP4 E001A7 0 +OP4 E001A8 0 +OP4 E001A9 0 +OP4 E001AA 0 +OP4 E001AB 0 +OP4 E001AC 0 +OP4 E001AD 0 +OP4 E001AE 0 +OP4 E001AF 0 +OP4 E001B0 0 +OP4 E001B1 0 +OP4 E001B2 0 +OP4 E001B3 0 +OP4 E001B4 0 +OP4 E001B5 0 +OP4 E001B6 0 +OP4 E001B7 0 +OP4 E001B8 0 +OP4 E001B9 0 +OP4 E001BA 0 +OP4 E001BB 0 +OP4 E001BC 0 +OP4 E001BD 0 +OP4 E001BE 0 +OP4 E001BF 0 +OP4 E001C0 0 +OP4 E001C1 0 +OP4 E001C2 0 +OP4 E001C3 0 +OP4 E001C4 0 +OP4 E001C5 0 +OP4 E001C6 0 +OP4 E001C7 0 +OP4 E001C8 0 +OP4 E001C9 0 +OP4 E001CA 0 +OP4 E001CB 0 +OP4 E001CC 0 +OP4 E001CD 0 +OP4 E001CE 0 +OP4 E001CF 0 +OP4 E001D0 0 +OP4 E001D1 0 +OP4 E001D2 0 +OP4 E001D3 0 +OP4 E001D4 0 +OP4 E001D5 0 +OP4 E001D6 0 +OP4 E001D7 0 +OP4 E001D8 0 +OP4 E001D9 0 +OP4 E001DA 0 +OP4 E001DB 0 +OP4 E001DC 0 +OP4 E001DD 0 +OP4 E001DE 0 +OP4 E001DF 0 +OP4 E001E0 0 +OP4 E001E1 0 +OP4 E001E2 0 +OP4 E001E3 0 +OP4 E001E4 0 +OP4 E001E5 0 +OP4 E001E6 0 +OP4 E001E7 0 +OP4 E001E8 0 +OP4 E001E9 0 +OP4 E001EA 0 +OP4 E001EB 0 +OP4 E001EC 0 +OP4 E001ED 0 +OP4 E001EE 0 +OP4 E001EF 0 +OP4 E001F0 0 +OP4 E001F1 0 +OP4 E001F2 0 +OP4 E001F3 0 +OP4 E001F4 0 +OP4 E001F5 0 +OP4 E001F6 0 +OP4 E001F7 0 +OP4 E001F8 0 +OP4 E001F9 0 +OP4 E001FA 0 +OP4 E001FB 0 +OP4 E001FC 0 +OP4 E001FD 0 +OP4 E001FE 0 +OP4 E001FF 0 +OP4 E00200 0 +OP4 E00201 0 +OP4 E00202 0 +OP4 E00203 0 +OP4 E00204 0 +OP4 E00205 0 +OP4 E00206 0 +OP4 E00207 0 +OP4 E00208 0 +OP4 E00209 0 +OP4 E0020A 0 +OP4 E0020B 0 +OP4 E0020C 0 +OP4 E0020D 0 +OP4 E0020E 0 +OP4 E0020F 0 +OP4 E00210 0 +OP4 E00211 0 +OP4 E00212 0 +OP4 E00213 0 +OP4 E00214 0 +OP4 E00215 0 +OP4 E00216 0 +OP4 E00217 0 +OP4 E00218 0 +OP4 E00219 0 +OP4 E0021A 0 +OP4 E0021B 0 +OP4 E0021C 0 +OP4 E0021D 0 +OP4 E0021E 0 +OP4 E0021F 0 +OP4 E00220 0 +OP4 E00221 0 +OP4 E00222 0 +OP4 E00223 0 +OP4 E00224 0 +OP4 E00225 0 +OP4 E00226 0 +OP4 E00227 0 +OP4 E00228 0 +OP4 E00229 0 +OP4 E0022A 0 +OP4 E0022B 0 +OP4 E0022C 0 +OP4 E0022D 0 +OP4 E0022E 0 +OP4 E0022F 0 +OP4 E00230 0 +OP4 E00231 0 +OP4 E00232 0 +OP4 E00233 0 +OP4 E00234 0 +OP4 E00235 0 +OP4 E00236 0 +OP4 E00237 0 +OP4 E00238 0 +OP4 E00239 0 +OP4 E0023A 0 +OP4 E0023B 0 +OP4 E0023C 0 +OP4 E0023D 0 +OP4 E0023E 0 +OP4 E0023F 0 +OP4 E00240 0 +OP4 E00241 0 +OP4 E00242 0 +OP4 E00243 0 +OP4 E00244 0 +OP4 E00245 0 +OP4 E00246 0 +OP4 E00247 0 +OP4 E00248 0 +OP4 E00249 0 +OP4 E0024A 0 +OP4 E0024B 0 +OP4 E0024C 0 +OP4 E0024D 0 +OP4 E0024E 0 +OP4 E0024F 0 +OP4 E00250 0 +OP4 E00251 0 +OP4 E00252 0 +OP4 E00253 0 +OP4 E00254 0 +OP4 E00255 0 +OP4 E00256 0 +OP4 E00257 0 +OP4 E00258 0 +OP4 E00259 0 +OP4 E0025A 0 +OP4 E0025B 0 +OP4 E0025C 0 +OP4 E0025D 0 +OP4 E0025E 0 +OP4 E0025F 0 +OP4 E00260 0 +OP4 E00261 0 +OP4 E00262 0 +OP4 E00263 0 +OP4 E00264 0 +OP4 E00265 0 +OP4 E00266 0 +OP4 E00267 0 +OP4 E00268 0 +OP4 E00269 0 +OP4 E0026A 0 +OP4 E0026B 0 +OP4 E0026C 0 +OP4 E0026D 0 +OP4 E0026E 0 +OP4 E0026F 0 +OP4 E00270 0 +OP4 E00271 0 +OP4 E00272 0 +OP4 E00273 0 +OP4 E00274 0 +OP4 E00275 0 +OP4 E00276 0 +OP4 E00277 0 +OP4 E00278 0 +OP4 E00279 0 +OP4 E0027A 0 +OP4 E0027B 0 +OP4 E0027C 0 +OP4 E0027D 0 +OP4 E0027E 0 +OP4 E0027F 0 +OP4 E00280 0 +OP4 E00281 0 +OP4 E00282 0 +OP4 E00283 0 +OP4 E00284 0 +OP4 E00285 0 +OP4 E00286 0 +OP4 E00287 0 +OP4 E00288 0 +OP4 E00289 0 +OP4 E0028A 0 +OP4 E0028B 0 +OP4 E0028C 0 +OP4 E0028D 0 +OP4 E0028E 0 +OP4 E0028F 0 +OP4 E00290 0 +OP4 E00291 0 +OP4 E00292 0 +OP4 E00293 0 +OP4 E00294 0 +OP4 E00295 0 +OP4 E00296 0 +OP4 E00297 0 +OP4 E00298 0 +OP4 E00299 0 +OP4 E0029A 0 +OP4 E0029B 0 +OP4 E0029C 0 +OP4 E0029D 0 +OP4 E0029E 0 +OP4 E0029F 0 +OP4 E002A0 0 +OP4 E002A1 0 +OP4 E002A2 0 +OP4 E002A3 0 +OP4 E002A4 0 +OP4 E002A5 0 +OP4 E002A6 0 +OP4 E002A7 0 +OP4 E002A8 0 +OP4 E002A9 0 +OP4 E002AA 0 +OP4 E002AB 0 +OP4 E002AC 0 +OP4 E002AD 0 +OP4 E002AE 0 +OP4 E002AF 0 +OP4 E002B0 0 +OP4 E002B1 0 +OP4 E002B2 0 +OP4 E002B3 0 +OP4 E002B4 0 +OP4 E002B5 0 +OP4 E002B6 0 +OP4 E002B7 0 +OP4 E002B8 0 +OP4 E002B9 0 +OP4 E002BA 0 +OP4 E002BB 0 +OP4 E002BC 0 +OP4 E002BD 0 +OP4 E002BE 0 +OP4 E002BF 0 +OP4 E002C0 0 +OP4 E002C1 0 +OP4 E002C2 0 +OP4 E002C3 0 +OP4 E002C4 0 +OP4 E002C5 0 +OP4 E002C6 0 +OP4 E002C7 0 +OP4 E002C8 0 +OP4 E002C9 0 +OP4 E002CA 0 +OP4 E002CB 0 +OP4 E002CC 0 +OP4 E002CD 0 +OP4 E002CE 0 +OP4 E002CF 0 +OP4 E002D0 0 +OP4 E002D1 0 +OP4 E002D2 0 +OP4 E002D3 0 +OP4 E002D4 0 +OP4 E002D5 0 +OP4 E002D6 0 +OP4 E002D7 0 +OP4 E002D8 0 +OP4 E002D9 0 +OP4 E002DA 0 +OP4 E002DB 0 +OP4 E002DC 0 +OP4 E002DD 0 +OP4 E002DE 0 +OP4 E002DF 0 +OP4 E002E0 0 +OP4 E002E1 0 +OP4 E002E2 0 +OP4 E002E3 0 +OP4 E002E4 0 +OP4 E002E5 0 +OP4 E002E6 0 +OP4 E002E7 0 +OP4 E002E8 0 +OP4 E002E9 0 +OP4 E002EA 0 +OP4 E002EB 0 +OP4 E002EC 0 +OP4 E002ED 0 +OP4 E002EE 0 +OP4 E002EF 0 +OP4 E002F0 0 +OP4 E002F1 0 +OP4 E002F2 0 +OP4 E002F3 0 +OP4 E002F4 0 +OP4 E002F5 0 +OP4 E002F6 0 +OP4 E002F7 0 +OP4 E002F8 0 +OP4 E002F9 0 +OP4 E002FA 0 +OP4 E002FB 0 +OP4 E002FC 0 +OP4 E002FD 0 +OP4 E002FE 0 +OP4 E002FF 0 +OP4 E00300 0 +OP4 E00301 0 +OP4 E00302 0 +OP4 E00303 0 +OP4 E00304 0 +OP4 E00305 0 +OP4 E00306 0 +OP4 E00307 0 +OP4 E00308 0 +OP4 E00309 0 +OP4 E0030A 0 +OP4 E0030B 0 +OP4 E0030C 0 +OP4 E0030D 0 +OP4 E0030E 0 +OP4 E0030F 0 +OP4 E00310 0 +OP4 E00311 0 +OP4 E00312 0 +OP4 E00313 0 +OP4 E00314 0 +OP4 E00315 0 +OP4 E00316 0 +OP4 E00317 0 +OP4 E00318 0 +OP4 E00319 0 +OP4 E0031A 0 +OP4 E0031B 0 +OP4 E0031C 0 +OP4 E0031D 0 +OP4 E0031E 0 +OP4 E0031F 0 +OP4 E00320 0 +OP4 E00321 0 +OP4 E00322 0 +OP4 E00323 0 +OP4 E00324 0 +OP4 E00325 0 +OP4 E00326 0 +OP4 E00327 0 +OP4 E00328 0 +OP4 E00329 0 +OP4 E0032A 0 +OP4 E0032B 0 +OP4 E0032C 0 +OP4 E0032D 0 +OP4 E0032E 0 +OP4 E0032F 0 +OP4 E00330 0 +OP4 E00331 0 +OP4 E00332 0 +OP4 E00333 0 +OP4 E00334 0 +OP4 E00335 0 +OP4 E00336 0 +OP4 E00337 0 +OP4 E00338 0 +OP4 E00339 0 +OP4 E0033A 0 +OP4 E0033B 0 +OP4 E0033C 0 +OP4 E0033D 0 +OP4 E0033E 0 +OP4 E0033F 0 +OP4 E00340 0 +OP4 E00341 0 +OP4 E00342 0 +OP4 E00343 0 +OP4 E00344 0 +OP4 E00345 0 +OP4 E00346 0 +OP4 E00347 0 +OP4 E00348 0 +OP4 E00349 0 +OP4 E0034A 0 +OP4 E0034B 0 +OP4 E0034C 0 +OP4 E0034D 0 +OP4 E0034E 0 +OP4 E0034F 0 +OP4 E00350 0 +OP4 E00351 0 +OP4 E00352 0 +OP4 E00353 0 +OP4 E00354 0 +OP4 E00355 0 +OP4 E00356 0 +OP4 E00357 0 +OP4 E00358 0 +OP4 E00359 0 +OP4 E0035A 0 +OP4 E0035B 0 +OP4 E0035C 0 +OP4 E0035D 0 +OP4 E0035E 0 +OP4 E0035F 0 +OP4 E00360 0 +OP4 E00361 0 +OP4 E00362 0 +OP4 E00363 0 +OP4 E00364 0 +OP4 E00365 0 +OP4 E00366 0 +OP4 E00367 0 +OP4 E00368 0 +OP4 E00369 0 +OP4 E0036A 0 +OP4 E0036B 0 +OP4 E0036C 0 +OP4 E0036D 0 +OP4 E0036E 0 +OP4 E0036F 0 +OP4 E00370 0 +OP4 E00371 0 +OP4 E00372 0 +OP4 E00373 0 +OP4 E00374 0 +OP4 E00375 0 +OP4 E00376 0 +OP4 E00377 0 +OP4 E00378 0 +OP4 E00379 0 +OP4 E0037A 0 +OP4 E0037B 0 +OP4 E0037C 0 +OP4 E0037D 0 +OP4 E0037E 0 +OP4 E0037F 0 +OP4 E00380 0 +OP4 E00381 0 +OP4 E00382 0 +OP4 E00383 0 +OP4 E00384 0 +OP4 E00385 0 +OP4 E00386 0 +OP4 E00387 0 +OP4 E00388 0 +OP4 E00389 0 +OP4 E0038A 0 +OP4 E0038B 0 +OP4 E0038C 0 +OP4 E0038D 0 +OP4 E0038E 0 +OP4 E0038F 0 +OP4 E00390 0 +OP4 E00391 0 +OP4 E00392 0 +OP4 E00393 0 +OP4 E00394 0 +OP4 E00395 0 +OP4 E00396 0 +OP4 E00397 0 +OP4 E00398 0 +OP4 E00399 0 +OP4 E0039A 0 +OP4 E0039B 0 +OP4 E0039C 0 +OP4 E0039D 0 +OP4 E0039E 0 +OP4 E0039F 0 +OP4 E003A0 0 +OP4 E003A1 0 +OP4 E003A2 0 +OP4 E003A3 0 +OP4 E003A4 0 +OP4 E003A5 0 +OP4 E003A6 0 +OP4 E003A7 0 +OP4 E003A8 0 +OP4 E003A9 0 +OP4 E003AA 0 +OP4 E003AB 0 +OP4 E003AC 0 +OP4 E003AD 0 +OP4 E003AE 0 +OP4 E003AF 0 +OP4 E003B0 0 +OP4 E003B1 0 +OP4 E003B2 0 +OP4 E003B3 0 +OP4 E003B4 0 +OP4 E003B5 0 +OP4 E003B6 0 +OP4 E003B7 0 +OP4 E003B8 0 +OP4 E003B9 0 +OP4 E003BA 0 +OP4 E003BB 0 +OP4 E003BC 0 +OP4 E003BD 0 +OP4 E003BE 0 +OP4 E003BF 0 +OP4 E003C0 0 +OP4 E003C1 0 +OP4 E003C2 0 +OP4 E003C3 0 +OP4 E003C4 0 +OP4 E003C5 0 +OP4 E003C6 0 +OP4 E003C7 0 +OP4 E003C8 0 +OP4 E003C9 0 +OP4 E003CA 0 +OP4 E003CB 0 +OP4 E003CC 0 +OP4 E003CD 0 +OP4 E003CE 0 +OP4 E003CF 0 +OP4 E003D0 0 +OP4 E003D1 0 +OP4 E003D2 0 +OP4 E003D3 0 +OP4 E003D4 0 +OP4 E003D5 0 +OP4 E003D6 0 +OP4 E003D7 0 +OP4 E003D8 0 +OP4 E003D9 0 +OP4 E003DA 0 +OP4 E003DB 0 +OP4 E003DC 0 +OP4 E003DD 0 +OP4 E003DE 0 +OP4 E003DF 0 +OP4 E003E0 0 +OP4 E003E1 0 +OP4 E003E2 0 +OP4 E003E3 0 +OP4 E003E4 0 +OP4 E003E5 0 +OP4 E003E6 0 +OP4 E003E7 0 +OP4 E003E8 0 +OP4 E003E9 0 +OP4 E003EA 0 +OP4 E003EB 0 +OP4 E003EC 0 +OP4 E003ED 0 +OP4 E003EE 0 +OP4 E003EF 0 +OP4 E003F0 0 +OP4 E003F1 0 +OP4 E003F2 0 +OP4 E003F3 0 +OP4 E003F4 0 +OP4 E003F5 0 +OP4 E003F6 0 +OP4 E003F7 0 +OP4 E003F8 0 +OP4 E003F9 0 +OP4 E003FA 0 +OP4 E003FB 0 +OP4 E003FC 0 +OP4 E003FD 0 +OP4 E003FE 0 +OP4 E003FF 0 +OP4 E00400 0 +OP4 E00401 0 +OP4 E00402 0 +OP4 E00403 0 +OP4 E00404 0 +OP4 E00405 0 +OP4 E00406 0 +OP4 E00407 0 +OP4 E00408 0 +OP4 E00409 0 +OP4 E0040A 0 +OP4 E0040B 0 +OP4 E0040C 0 +OP4 E0040D 0 +OP4 E0040E 0 +OP4 E0040F 0 +OP4 E00410 0 +OP4 E00411 0 +OP4 E00412 0 +OP4 E00413 0 +OP4 E00414 0 +OP4 E00415 0 +OP4 E00416 0 +OP4 E00417 0 +OP4 E00418 0 +OP4 E00419 0 +OP4 E0041A 0 +OP4 E0041B 0 +OP4 E0041C 0 +OP4 E0041D 0 +OP4 E0041E 0 +OP4 E0041F 0 +OP4 E00420 0 +OP4 E00421 0 +OP4 E00422 0 +OP4 E00423 0 +OP4 E00424 0 +OP4 E00425 0 +OP4 E00426 0 +OP4 E00427 0 +OP4 E00428 0 +OP4 E00429 0 +OP4 E0042A 0 +OP4 E0042B 0 +OP4 E0042C 0 +OP4 E0042D 0 +OP4 E0042E 0 +OP4 E0042F 0 +OP4 E00430 0 +OP4 E00431 0 +OP4 E00432 0 +OP4 E00433 0 +OP4 E00434 0 +OP4 E00435 0 +OP4 E00436 0 +OP4 E00437 0 +OP4 E00438 0 +OP4 E00439 0 +OP4 E0043A 0 +OP4 E0043B 0 +OP4 E0043C 0 +OP4 E0043D 0 +OP4 E0043E 0 +OP4 E0043F 0 +OP4 E00440 0 +OP4 E00441 0 +OP4 E00442 0 +OP4 E00443 0 +OP4 E00444 0 +OP4 E00445 0 +OP4 E00446 0 +OP4 E00447 0 +OP4 E00448 0 +OP4 E00449 0 +OP4 E0044A 0 +OP4 E0044B 0 +OP4 E0044C 0 +OP4 E0044D 0 +OP4 E0044E 0 +OP4 E0044F 0 +OP4 E00450 0 +OP4 E00451 0 +OP4 E00452 0 +OP4 E00453 0 +OP4 E00454 0 +OP4 E00455 0 +OP4 E00456 0 +OP4 E00457 0 +OP4 E00458 0 +OP4 E00459 0 +OP4 E0045A 0 +OP4 E0045B 0 +OP4 E0045C 0 +OP4 E0045D 0 +OP4 E0045E 0 +OP4 E0045F 0 +OP4 E00460 0 +OP4 E00461 0 +OP4 E00462 0 +OP4 E00463 0 +OP4 E00464 0 +OP4 E00465 0 +OP4 E00466 0 +OP4 E00467 0 +OP4 E00468 0 +OP4 E00469 0 +OP4 E0046A 0 +OP4 E0046B 0 +OP4 E0046C 0 +OP4 E0046D 0 +OP4 E0046E 0 +OP4 E0046F 0 +OP4 E00470 0 +OP4 E00471 0 +OP4 E00472 0 +OP4 E00473 0 +OP4 E00474 0 +OP4 E00475 0 +OP4 E00476 0 +OP4 E00477 0 +OP4 E00478 0 +OP4 E00479 0 +OP4 E0047A 0 +OP4 E0047B 0 +OP4 E0047C 0 +OP4 E0047D 0 +OP4 E0047E 0 +OP4 E0047F 0 +OP4 E00480 0 +OP4 E00481 0 +OP4 E00482 0 +OP4 E00483 0 +OP4 E00484 0 +OP4 E00485 0 +OP4 E00486 0 +OP4 E00487 0 +OP4 E00488 0 +OP4 E00489 0 +OP4 E0048A 0 +OP4 E0048B 0 +OP4 E0048C 0 +OP4 E0048D 0 +OP4 E0048E 0 +OP4 E0048F 0 +OP4 E00490 0 +OP4 E00491 0 +OP4 E00492 0 +OP4 E00493 0 +OP4 E00494 0 +OP4 E00495 0 +OP4 E00496 0 +OP4 E00497 0 +OP4 E00498 0 +OP4 E00499 0 +OP4 E0049A 0 +OP4 E0049B 0 +OP4 E0049C 0 +OP4 E0049D 0 +OP4 E0049E 0 +OP4 E0049F 0 +OP4 E004A0 0 +OP4 E004A1 0 +OP4 E004A2 0 +OP4 E004A3 0 +OP4 E004A4 0 +OP4 E004A5 0 +OP4 E004A6 0 +OP4 E004A7 0 +OP4 E004A8 0 +OP4 E004A9 0 +OP4 E004AA 0 +OP4 E004AB 0 +OP4 E004AC 0 +OP4 E004AD 0 +OP4 E004AE 0 +OP4 E004AF 0 +OP4 E004B0 0 +OP4 E004B1 0 +OP4 E004B2 0 +OP4 E004B3 0 +OP4 E004B4 0 +OP4 E004B5 0 +OP4 E004B6 0 +OP4 E004B7 0 +OP4 E004B8 0 +OP4 E004B9 0 +OP4 E004BA 0 +OP4 E004BB 0 +OP4 E004BC 0 +OP4 E004BD 0 +OP4 E004BE 0 +OP4 E004BF 0 +OP4 E004C0 0 +OP4 E004C1 0 +OP4 E004C2 0 +OP4 E004C3 0 +OP4 E004C4 0 +OP4 E004C5 0 +OP4 E004C6 0 +OP4 E004C7 0 +OP4 E004C8 0 +OP4 E004C9 0 +OP4 E004CA 0 +OP4 E004CB 0 +OP4 E004CC 0 +OP4 E004CD 0 +OP4 E004CE 0 +OP4 E004CF 0 +OP4 E004D0 0 +OP4 E004D1 0 +OP4 E004D2 0 +OP4 E004D3 0 +OP4 E004D4 0 +OP4 E004D5 0 +OP4 E004D6 0 +OP4 E004D7 0 +OP4 E004D8 0 +OP4 E004D9 0 +OP4 E004DA 0 +OP4 E004DB 0 +OP4 E004DC 0 +OP4 E004DD 0 +OP4 E004DE 0 +OP4 E004DF 0 +OP4 E004E0 0 +OP4 E004E1 0 +OP4 E004E2 0 +OP4 E004E3 0 +OP4 E004E4 0 +OP4 E004E5 0 +OP4 E004E6 0 +OP4 E004E7 0 +OP4 E004E8 0 +OP4 E004E9 0 +OP4 E004EA 0 +OP4 E004EB 0 +OP4 E004EC 0 +OP4 E004ED 0 +OP4 E004EE 0 +OP4 E004EF 0 +OP4 E004F0 0 +OP4 E004F1 0 +OP4 E004F2 0 +OP4 E004F3 0 +OP4 E004F4 0 +OP4 E004F5 0 +OP4 E004F6 0 +OP4 E004F7 0 +OP4 E004F8 0 +OP4 E004F9 0 +OP4 E004FA 0 +OP4 E004FB 0 +OP4 E004FC 0 +OP4 E004FD 0 +OP4 E004FE 0 +OP4 E004FF 0 +OP4 E00500 0 +OP4 E00501 0 +OP4 E00502 0 +OP4 E00503 0 +OP4 E00504 0 +OP4 E00505 0 +OP4 E00506 0 +OP4 E00507 0 +OP4 E00508 0 +OP4 E00509 0 +OP4 E0050A 0 +OP4 E0050B 0 +OP4 E0050C 0 +OP4 E0050D 0 +OP4 E0050E 0 +OP4 E0050F 0 +OP4 E00510 0 +OP4 E00511 0 +OP4 E00512 0 +OP4 E00513 0 +OP4 E00514 0 +OP4 E00515 0 +OP4 E00516 0 +OP4 E00517 0 +OP4 E00518 0 +OP4 E00519 0 +OP4 E0051A 0 +OP4 E0051B 0 +OP4 E0051C 0 +OP4 E0051D 0 +OP4 E0051E 0 +OP4 E0051F 0 +OP4 E00520 0 +OP4 E00521 0 +OP4 E00522 0 +OP4 E00523 0 +OP4 E00524 0 +OP4 E00525 0 +OP4 E00526 0 +OP4 E00527 0 +OP4 E00528 0 +OP4 E00529 0 +OP4 E0052A 0 +OP4 E0052B 0 +OP4 E0052C 0 +OP4 E0052D 0 +OP4 E0052E 0 +OP4 E0052F 0 +OP4 E00530 0 +OP4 E00531 0 +OP4 E00532 0 +OP4 E00533 0 +OP4 E00534 0 +OP4 E00535 0 +OP4 E00536 0 +OP4 E00537 0 +OP4 E00538 0 +OP4 E00539 0 +OP4 E0053A 0 +OP4 E0053B 0 +OP4 E0053C 0 +OP4 E0053D 0 +OP4 E0053E 0 +OP4 E0053F 0 +OP4 E00540 0 +OP4 E00541 0 +OP4 E00542 0 +OP4 E00543 0 +OP4 E00544 0 +OP4 E00545 0 +OP4 E00546 0 +OP4 E00547 0 +OP4 E00548 0 +OP4 E00549 0 +OP4 E0054A 0 +OP4 E0054B 0 +OP4 E0054C 0 +OP4 E0054D 0 +OP4 E0054E 0 +OP4 E0054F 0 +OP4 E00550 0 +OP4 E00551 0 +OP4 E00552 0 +OP4 E00553 0 +OP4 E00554 0 +OP4 E00555 0 +OP4 E00556 0 +OP4 E00557 0 +OP4 E00558 0 +OP4 E00559 0 +OP4 E0055A 0 +OP4 E0055B 0 +OP4 E0055C 0 +OP4 E0055D 0 +OP4 E0055E 0 +OP4 E0055F 0 +OP4 E00560 0 +OP4 E00561 0 +OP4 E00562 0 +OP4 E00563 0 +OP4 E00564 0 +OP4 E00565 0 +OP4 E00566 0 +OP4 E00567 0 +OP4 E00568 0 +OP4 E00569 0 +OP4 E0056A 0 +OP4 E0056B 0 +OP4 E0056C 0 +OP4 E0056D 0 +OP4 E0056E 0 +OP4 E0056F 0 +OP4 E00570 0 +OP4 E00571 0 +OP4 E00572 0 +OP4 E00573 0 +OP4 E00574 0 +OP4 E00575 0 +OP4 E00576 0 +OP4 E00577 0 +OP4 E00578 0 +OP4 E00579 0 +OP4 E0057A 0 +OP4 E0057B 0 +OP4 E0057C 0 +OP4 E0057D 0 +OP4 E0057E 0 +OP4 E0057F 0 +OP4 E00580 0 +OP4 E00581 0 +OP4 E00582 0 +OP4 E00583 0 +OP4 E00584 0 +OP4 E00585 0 +OP4 E00586 0 +OP4 E00587 0 +OP4 E00588 0 +OP4 E00589 0 +OP4 E0058A 0 +OP4 E0058B 0 +OP4 E0058C 0 +OP4 E0058D 0 +OP4 E0058E 0 +OP4 E0058F 0 +OP4 E00590 0 +OP4 E00591 0 +OP4 E00592 0 +OP4 E00593 0 +OP4 E00594 0 +OP4 E00595 0 +OP4 E00596 0 +OP4 E00597 0 +OP4 E00598 0 +OP4 E00599 0 +OP4 E0059A 0 +OP4 E0059B 0 +OP4 E0059C 0 +OP4 E0059D 0 +OP4 E0059E 0 +OP4 E0059F 0 +OP4 E005A0 0 +OP4 E005A1 0 +OP4 E005A2 0 +OP4 E005A3 0 +OP4 E005A4 0 +OP4 E005A5 0 +OP4 E005A6 0 +OP4 E005A7 0 +OP4 E005A8 0 +OP4 E005A9 0 +OP4 E005AA 0 +OP4 E005AB 0 +OP4 E005AC 0 +OP4 E005AD 0 +OP4 E005AE 0 +OP4 E005AF 0 +OP4 E005B0 0 +OP4 E005B1 0 +OP4 E005B2 0 +OP4 E005B3 0 +OP4 E005B4 0 +OP4 E005B5 0 +OP4 E005B6 0 +OP4 E005B7 0 +OP4 E005B8 0 +OP4 E005B9 0 +OP4 E005BA 0 +OP4 E005BB 0 +OP4 E005BC 0 +OP4 E005BD 0 +OP4 E005BE 0 +OP4 E005BF 0 +OP4 E005C0 0 +OP4 E005C1 0 +OP4 E005C2 0 +OP4 E005C3 0 +OP4 E005C4 0 +OP4 E005C5 0 +OP4 E005C6 0 +OP4 E005C7 0 +OP4 E005C8 0 +OP4 E005C9 0 +OP4 E005CA 0 +OP4 E005CB 0 +OP4 E005CC 0 +OP4 E005CD 0 +OP4 E005CE 0 +OP4 E005CF 0 +OP4 E005D0 0 +OP4 E005D1 0 +OP4 E005D2 0 +OP4 E005D3 0 +OP4 E005D4 0 +OP4 E005D5 0 +OP4 E005D6 0 +OP4 E005D7 0 +OP4 E005D8 0 +OP4 E005D9 0 +OP4 E005DA 0 +OP4 E005DB 0 +OP4 E005DC 0 +OP4 E005DD 0 +OP4 E005DE 0 +OP4 E005DF 0 +OP4 E005E0 0 +OP4 E005E1 0 +OP4 E005E2 0 +OP4 E005E3 0 +OP4 E005E4 0 +OP4 E005E5 0 +OP4 E005E6 0 +OP4 E005E7 0 +OP4 E005E8 0 +OP4 E005E9 0 +OP4 E005EA 0 +OP4 E005EB 0 +OP4 E005EC 0 +OP4 E005ED 0 +OP4 E005EE 0 +OP4 E005EF 0 +OP4 E005F0 0 +OP4 E005F1 0 +OP4 E005F2 0 +OP4 E005F3 0 +OP4 E005F4 0 +OP4 E005F5 0 +OP4 E005F6 0 +OP4 E005F7 0 +OP4 E005F8 0 +OP4 E005F9 0 +OP4 E005FA 0 +OP4 E005FB 0 +OP4 E005FC 0 +OP4 E005FD 0 +OP4 E005FE 0 +OP4 E005FF 0 +OP4 E00600 0 +OP4 E00601 0 +OP4 E00602 0 +OP4 E00603 0 +OP4 E00604 0 +OP4 E00605 0 +OP4 E00606 0 +OP4 E00607 0 +OP4 E00608 0 +OP4 E00609 0 +OP4 E0060A 0 +OP4 E0060B 0 +OP4 E0060C 0 +OP4 E0060D 0 +OP4 E0060E 0 +OP4 E0060F 0 +OP4 E00610 0 +OP4 E00611 0 +OP4 E00612 0 +OP4 E00613 0 +OP4 E00614 0 +OP4 E00615 0 +OP4 E00616 0 +OP4 E00617 0 +OP4 E00618 0 +OP4 E00619 0 +OP4 E0061A 0 +OP4 E0061B 0 +OP4 E0061C 0 +OP4 E0061D 0 +OP4 E0061E 0 +OP4 E0061F 0 +OP4 E00620 0 +OP4 E00621 0 +OP4 E00622 0 +OP4 E00623 0 +OP4 E00624 0 +OP4 E00625 0 +OP4 E00626 0 +OP4 E00627 0 +OP4 E00628 0 +OP4 E00629 0 +OP4 E0062A 0 +OP4 E0062B 0 +OP4 E0062C 0 +OP4 E0062D 0 +OP4 E0062E 0 +OP4 E0062F 0 +OP4 E00630 0 +OP4 E00631 0 +OP4 E00632 0 +OP4 E00633 0 +OP4 E00634 0 +OP4 E00635 0 +OP4 E00636 0 +OP4 E00637 0 +OP4 E00638 0 +OP4 E00639 0 +OP4 E0063A 0 +OP4 E0063B 0 +OP4 E0063C 0 +OP4 E0063D 0 +OP4 E0063E 0 +OP4 E0063F 0 +OP4 E00640 0 +OP4 E00641 0 +OP4 E00642 0 +OP4 E00643 0 +OP4 E00644 0 +OP4 E00645 0 +OP4 E00646 0 +OP4 E00647 0 +OP4 E00648 0 +OP4 E00649 0 +OP4 E0064A 0 +OP4 E0064B 0 +OP4 E0064C 0 +OP4 E0064D 0 +OP4 E0064E 0 +OP4 E0064F 0 +OP4 E00650 0 +OP4 E00651 0 +OP4 E00652 0 +OP4 E00653 0 +OP4 E00654 0 +OP4 E00655 0 +OP4 E00656 0 +OP4 E00657 0 +OP4 E00658 0 +OP4 E00659 0 +OP4 E0065A 0 +OP4 E0065B 0 +OP4 E0065C 0 +OP4 E0065D 0 +OP4 E0065E 0 +OP4 E0065F 0 +OP4 E00660 0 +OP4 E00661 0 +OP4 E00662 0 +OP4 E00663 0 +OP4 E00664 0 +OP4 E00665 0 +OP4 E00666 0 +OP4 E00667 0 +OP4 E00668 0 +OP4 E00669 0 +OP4 E0066A 0 +OP4 E0066B 0 +OP4 E0066C 0 +OP4 E0066D 0 +OP4 E0066E 0 +OP4 E0066F 0 +OP4 E00670 0 +OP4 E00671 0 +OP4 E00672 0 +OP4 E00673 0 +OP4 E00674 0 +OP4 E00675 0 +OP4 E00676 0 +OP4 E00677 0 +OP4 E00678 0 +OP4 E00679 0 +OP4 E0067A 0 +OP4 E0067B 0 +OP4 E0067C 0 +OP4 E0067D 0 +OP4 E0067E 0 +OP4 E0067F 0 +OP4 E00680 0 +OP4 E00681 0 +OP4 E00682 0 +OP4 E00683 0 +OP4 E00684 0 +OP4 E00685 0 +OP4 E00686 0 +OP4 E00687 0 +OP4 E00688 0 +OP4 E00689 0 +OP4 E0068A 0 +OP4 E0068B 0 +OP4 E0068C 0 +OP4 E0068D 0 +OP4 E0068E 0 +OP4 E0068F 0 +OP4 E00690 0 +OP4 E00691 0 +OP4 E00692 0 +OP4 E00693 0 +OP4 E00694 0 +OP4 E00695 0 +OP4 E00696 0 +OP4 E00697 0 +OP4 E00698 0 +OP4 E00699 0 +OP4 E0069A 0 +OP4 E0069B 0 +OP4 E0069C 0 +OP4 E0069D 0 +OP4 E0069E 0 +OP4 E0069F 0 +OP4 E006A0 0 +OP4 E006A1 0 +OP4 E006A2 0 +OP4 E006A3 0 +OP4 E006A4 0 +OP4 E006A5 0 +OP4 E006A6 0 +OP4 E006A7 0 +OP4 E006A8 0 +OP4 E006A9 0 +OP4 E006AA 0 +OP4 E006AB 0 +OP4 E006AC 0 +OP4 E006AD 0 +OP4 E006AE 0 +OP4 E006AF 0 +OP4 E006B0 0 +OP4 E006B1 0 +OP4 E006B2 0 +OP4 E006B3 0 +OP4 E006B4 0 +OP4 E006B5 0 +OP4 E006B6 0 +OP4 E006B7 0 +OP4 E006B8 0 +OP4 E006B9 0 +OP4 E006BA 0 +OP4 E006BB 0 +OP4 E006BC 0 +OP4 E006BD 0 +OP4 E006BE 0 +OP4 E006BF 0 +OP4 E006C0 0 +OP4 E006C1 0 +OP4 E006C2 0 +OP4 E006C3 0 +OP4 E006C4 0 +OP4 E006C5 0 +OP4 E006C6 0 +OP4 E006C7 0 +OP4 E006C8 0 +OP4 E006C9 0 +OP4 E006CA 0 +OP4 E006CB 0 +OP4 E006CC 0 +OP4 E006CD 0 +OP4 E006CE 0 +OP4 E006CF 0 +OP4 E006D0 0 +OP4 E006D1 0 +OP4 E006D2 0 +OP4 E006D3 0 +OP4 E006D4 0 +OP4 E006D5 0 +OP4 E006D6 0 +OP4 E006D7 0 +OP4 E006D8 0 +OP4 E006D9 0 +OP4 E006DA 0 +OP4 E006DB 0 +OP4 E006DC 0 +OP4 E006DD 0 +OP4 E006DE 0 +OP4 E006DF 0 +OP4 E006E0 0 +OP4 E006E1 0 +OP4 E006E2 0 +OP4 E006E3 0 +OP4 E006E4 0 +OP4 E006E5 0 +OP4 E006E6 0 +OP4 E006E7 0 +OP4 E006E8 0 +OP4 E006E9 0 +OP4 E006EA 0 +OP4 E006EB 0 +OP4 E006EC 0 +OP4 E006ED 0 +OP4 E006EE 0 +OP4 E006EF 0 +OP4 E006F0 0 +OP4 E006F1 0 +OP4 E006F2 0 +OP4 E006F3 0 +OP4 E006F4 0 +OP4 E006F5 0 +OP4 E006F6 0 +OP4 E006F7 0 +OP4 E006F8 0 +OP4 E006F9 0 +OP4 E006FA 0 +OP4 E006FB 0 +OP4 E006FC 0 +OP4 E006FD 0 +OP4 E006FE 0 +OP4 E006FF 0 +OP4 E00700 0 +OP4 E00701 0 +OP4 E00702 0 +OP4 E00703 0 +OP4 E00704 0 +OP4 E00705 0 +OP4 E00706 0 +OP4 E00707 0 +OP4 E00708 0 +OP4 E00709 0 +OP4 E0070A 0 +OP4 E0070B 0 +OP4 E0070C 0 +OP4 E0070D 0 +OP4 E0070E 0 +OP4 E0070F 0 +OP4 E00710 0 +OP4 E00711 0 +OP4 E00712 0 +OP4 E00713 0 +OP4 E00714 0 +OP4 E00715 0 +OP4 E00716 0 +OP4 E00717 0 +OP4 E00718 0 +OP4 E00719 0 +OP4 E0071A 0 +OP4 E0071B 0 +OP4 E0071C 0 +OP4 E0071D 0 +OP4 E0071E 0 +OP4 E0071F 0 +OP4 E00720 0 +OP4 E00721 0 +OP4 E00722 0 +OP4 E00723 0 +OP4 E00724 0 +OP4 E00725 0 +OP4 E00726 0 +OP4 E00727 0 +OP4 E00728 0 +OP4 E00729 0 +OP4 E0072A 0 +OP4 E0072B 0 +OP4 E0072C 0 +OP4 E0072D 0 +OP4 E0072E 0 +OP4 E0072F 0 +OP4 E00730 0 +OP4 E00731 0 +OP4 E00732 0 +OP4 E00733 0 +OP4 E00734 0 +OP4 E00735 0 +OP4 E00736 0 +OP4 E00737 0 +OP4 E00738 0 +OP4 E00739 0 +OP4 E0073A 0 +OP4 E0073B 0 +OP4 E0073C 0 +OP4 E0073D 0 +OP4 E0073E 0 +OP4 E0073F 0 +OP4 E00740 0 +OP4 E00741 0 +OP4 E00742 0 +OP4 E00743 0 +OP4 E00744 0 +OP4 E00745 0 +OP4 E00746 0 +OP4 E00747 0 +OP4 E00748 0 +OP4 E00749 0 +OP4 E0074A 0 +OP4 E0074B 0 +OP4 E0074C 0 +OP4 E0074D 0 +OP4 E0074E 0 +OP4 E0074F 0 +OP4 E00750 0 +OP4 E00751 0 +OP4 E00752 0 +OP4 E00753 0 +OP4 E00754 0 +OP4 E00755 0 +OP4 E00756 0 +OP4 E00757 0 +OP4 E00758 0 +OP4 E00759 0 +OP4 E0075A 0 +OP4 E0075B 0 +OP4 E0075C 0 +OP4 E0075D 0 +OP4 E0075E 0 +OP4 E0075F 0 +OP4 E00760 0 +OP4 E00761 0 +OP4 E00762 0 +OP4 E00763 0 +OP4 E00764 0 +OP4 E00765 0 +OP4 E00766 0 +OP4 E00767 0 +OP4 E00768 0 +OP4 E00769 0 +OP4 E0076A 0 +OP4 E0076B 0 +OP4 E0076C 0 +OP4 E0076D 0 +OP4 E0076E 0 +OP4 E0076F 0 +OP4 E00770 0 +OP4 E00771 0 +OP4 E00772 0 +OP4 E00773 0 +OP4 E00774 0 +OP4 E00775 0 +OP4 E00776 0 +OP4 E00777 0 +OP4 E00778 0 +OP4 E00779 0 +OP4 E0077A 0 +OP4 E0077B 0 +OP4 E0077C 0 +OP4 E0077D 0 +OP4 E0077E 0 +OP4 E0077F 0 +OP4 E00780 0 +OP4 E00781 0 +OP4 E00782 0 +OP4 E00783 0 +OP4 E00784 0 +OP4 E00785 0 +OP4 E00786 0 +OP4 E00787 0 +OP4 E00788 0 +OP4 E00789 0 +OP4 E0078A 0 +OP4 E0078B 0 +OP4 E0078C 0 +OP4 E0078D 0 +OP4 E0078E 0 +OP4 E0078F 0 +OP4 E00790 0 +OP4 E00791 0 +OP4 E00792 0 +OP4 E00793 0 +OP4 E00794 0 +OP4 E00795 0 +OP4 E00796 0 +OP4 E00797 0 +OP4 E00798 0 +OP4 E00799 0 +OP4 E0079A 0 +OP4 E0079B 0 +OP4 E0079C 0 +OP4 E0079D 0 +OP4 E0079E 0 +OP4 E0079F 0 +OP4 E007A0 0 +OP4 E007A1 0 +OP4 E007A2 0 +OP4 E007A3 0 +OP4 E007A4 0 +OP4 E007A5 0 +OP4 E007A6 0 +OP4 E007A7 0 +OP4 E007A8 0 +OP4 E007A9 0 +OP4 E007AA 0 +OP4 E007AB 0 +OP4 E007AC 0 +OP4 E007AD 0 +OP4 E007AE 0 +OP4 E007AF 0 +OP4 E007B0 0 +OP4 E007B1 0 +OP4 E007B2 0 +OP4 E007B3 0 +OP4 E007B4 0 +OP4 E007B5 0 +OP4 E007B6 0 +OP4 E007B7 0 +OP4 E007B8 0 +OP4 E007B9 0 +OP4 E007BA 0 +OP4 E007BB 0 +OP4 E007BC 0 +OP4 E007BD 0 +OP4 E007BE 0 +OP4 E007BF 0 +OP4 E007C0 0 +OP4 E007C1 0 +OP4 E007C2 0 +OP4 E007C3 0 +OP4 E007C4 0 +OP4 E007C5 0 +OP4 E007C6 0 +OP4 E007C7 0 +OP4 E007C8 0 +OP4 E007C9 0 +OP4 E007CA 0 +OP4 E007CB 0 +OP4 E007CC 0 +OP4 E007CD 0 +OP4 E007CE 0 +OP4 E007CF 0 +OP4 E007D0 0 +OP4 E007D1 0 +OP4 E007D2 0 +OP4 E007D3 0 +OP4 E007D4 0 +OP4 E007D5 0 +OP4 E007D6 0 +OP4 E007D7 0 +OP4 E007D8 0 +OP4 E007D9 0 +OP4 E007DA 0 +OP4 E007DB 0 +OP4 E007DC 0 +OP4 E007DD 0 +OP4 E007DE 0 +OP4 E007DF 0 +OP4 E007E0 0 +OP4 E007E1 0 +OP4 E007E2 0 +OP4 E007E3 0 +OP4 E007E4 0 +OP4 E007E5 0 +OP4 E007E6 0 +OP4 E007E7 0 +OP4 E007E8 0 +OP4 E007E9 0 +OP4 E007EA 0 +OP4 E007EB 0 +OP4 E007EC 0 +OP4 E007ED 0 +OP4 E007EE 0 +OP4 E007EF 0 +OP4 E007F0 0 +OP4 E007F1 0 +OP4 E007F2 0 +OP4 E007F3 0 +OP4 E007F4 0 +OP4 E007F5 0 +OP4 E007F6 0 +OP4 E007F7 0 +OP4 E007F8 0 +OP4 E007F9 0 +OP4 E007FA 0 +OP4 E007FB 0 +OP4 E007FC 0 +OP4 E007FD 0 +OP4 E007FE 0 +OP4 E007FF 0 +OP4 E00800 0 +OP4 E00801 0 +OP4 E00802 0 +OP4 E00803 0 +OP4 E00804 0 +OP4 E00805 0 +OP4 E00806 0 +OP4 E00807 0 +OP4 E00808 0 +OP4 E00809 0 +OP4 E0080A 0 +OP4 E0080B 0 +OP4 E0080C 0 +OP4 E0080D 0 +OP4 E0080E 0 +OP4 E0080F 0 +OP4 E00810 0 +OP4 E00811 0 +OP4 E00812 0 +OP4 E00813 0 +OP4 E00814 0 +OP4 E00815 0 +OP4 E00816 0 +OP4 E00817 0 +OP4 E00818 0 +OP4 E00819 0 +OP4 E0081A 0 +OP4 E0081B 0 +OP4 E0081C 0 +OP4 E0081D 0 +OP4 E0081E 0 +OP4 E0081F 0 +OP4 E00820 0 +OP4 E00821 0 +OP4 E00822 0 +OP4 E00823 0 +OP4 E00824 0 +OP4 E00825 0 +OP4 E00826 0 +OP4 E00827 0 +OP4 E00828 0 +OP4 E00829 0 +OP4 E0082A 0 +OP4 E0082B 0 +OP4 E0082C 0 +OP4 E0082D 0 +OP4 E0082E 0 +OP4 E0082F 0 +OP4 E00830 0 +OP4 E00831 0 +OP4 E00832 0 +OP4 E00833 0 +OP4 E00834 0 +OP4 E00835 0 +OP4 E00836 0 +OP4 E00837 0 +OP4 E00838 0 +OP4 E00839 0 +OP4 E0083A 0 +OP4 E0083B 0 +OP4 E0083C 0 +OP4 E0083D 0 +OP4 E0083E 0 +OP4 E0083F 0 +OP4 E00840 0 +OP4 E00841 0 +OP4 E00842 0 +OP4 E00843 0 +OP4 E00844 0 +OP4 E00845 0 +OP4 E00846 0 +OP4 E00847 0 +OP4 E00848 0 +OP4 E00849 0 +OP4 E0084A 0 +OP4 E0084B 0 +OP4 E0084C 0 +OP4 E0084D 0 +OP4 E0084E 0 +OP4 E0084F 0 +OP4 E00850 0 +OP4 E00851 0 +OP4 E00852 0 +OP4 E00853 0 +OP4 E00854 0 +OP4 E00855 0 +OP4 E00856 0 +OP4 E00857 0 +OP4 E00858 0 +OP4 E00859 0 +OP4 E0085A 0 +OP4 E0085B 0 +OP4 E0085C 0 +OP4 E0085D 0 +OP4 E0085E 0 +OP4 E0085F 0 +OP4 E00860 0 +OP4 E00861 0 +OP4 E00862 0 +OP4 E00863 0 +OP4 E00864 0 +OP4 E00865 0 +OP4 E00866 0 +OP4 E00867 0 +OP4 E00868 0 +OP4 E00869 0 +OP4 E0086A 0 +OP4 E0086B 0 +OP4 E0086C 0 +OP4 E0086D 0 +OP4 E0086E 0 +OP4 E0086F 0 +OP4 E00870 0 +OP4 E00871 0 +OP4 E00872 0 +OP4 E00873 0 +OP4 E00874 0 +OP4 E00875 0 +OP4 E00876 0 +OP4 E00877 0 +OP4 E00878 0 +OP4 E00879 0 +OP4 E0087A 0 +OP4 E0087B 0 +OP4 E0087C 0 +OP4 E0087D 0 +OP4 E0087E 0 +OP4 E0087F 0 +OP4 E00880 0 +OP4 E00881 0 +OP4 E00882 0 +OP4 E00883 0 +OP4 E00884 0 +OP4 E00885 0 +OP4 E00886 0 +OP4 E00887 0 +OP4 E00888 0 +OP4 E00889 0 +OP4 E0088A 0 +OP4 E0088B 0 +OP4 E0088C 0 +OP4 E0088D 0 +OP4 E0088E 0 +OP4 E0088F 0 +OP4 E00890 0 +OP4 E00891 0 +OP4 E00892 0 +OP4 E00893 0 +OP4 E00894 0 +OP4 E00895 0 +OP4 E00896 0 +OP4 E00897 0 +OP4 E00898 0 +OP4 E00899 0 +OP4 E0089A 0 +OP4 E0089B 0 +OP4 E0089C 0 +OP4 E0089D 0 +OP4 E0089E 0 +OP4 E0089F 0 +OP4 E008A0 0 +OP4 E008A1 0 +OP4 E008A2 0 +OP4 E008A3 0 +OP4 E008A4 0 +OP4 E008A5 0 +OP4 E008A6 0 +OP4 E008A7 0 +OP4 E008A8 0 +OP4 E008A9 0 +OP4 E008AA 0 +OP4 E008AB 0 +OP4 E008AC 0 +OP4 E008AD 0 +OP4 E008AE 0 +OP4 E008AF 0 +OP4 E008B0 0 +OP4 E008B1 0 +OP4 E008B2 0 +OP4 E008B3 0 +OP4 E008B4 0 +OP4 E008B5 0 +OP4 E008B6 0 +OP4 E008B7 0 +OP4 E008B8 0 +OP4 E008B9 0 +OP4 E008BA 0 +OP4 E008BB 0 +OP4 E008BC 0 +OP4 E008BD 0 +OP4 E008BE 0 +OP4 E008BF 0 +OP4 E008C0 0 +OP4 E008C1 0 +OP4 E008C2 0 +OP4 E008C3 0 +OP4 E008C4 0 +OP4 E008C5 0 +OP4 E008C6 0 +OP4 E008C7 0 +OP4 E008C8 0 +OP4 E008C9 0 +OP4 E008CA 0 +OP4 E008CB 0 +OP4 E008CC 0 +OP4 E008CD 0 +OP4 E008CE 0 +OP4 E008CF 0 +OP4 E008D0 0 +OP4 E008D1 0 +OP4 E008D2 0 +OP4 E008D3 0 +OP4 E008D4 0 +OP4 E008D5 0 +OP4 E008D6 0 +OP4 E008D7 0 +OP4 E008D8 0 +OP4 E008D9 0 +OP4 E008DA 0 +OP4 E008DB 0 +OP4 E008DC 0 +OP4 E008DD 0 +OP4 E008DE 0 +OP4 E008DF 0 +OP4 E008E0 0 +OP4 E008E1 0 +OP4 E008E2 0 +OP4 E008E3 0 +OP4 E008E4 0 +OP4 E008E5 0 +OP4 E008E6 0 +OP4 E008E7 0 +OP4 E008E8 0 +OP4 E008E9 0 +OP4 E008EA 0 +OP4 E008EB 0 +OP4 E008EC 0 +OP4 E008ED 0 +OP4 E008EE 0 +OP4 E008EF 0 +OP4 E008F0 0 +OP4 E008F1 0 +OP4 E008F2 0 +OP4 E008F3 0 +OP4 E008F4 0 +OP4 E008F5 0 +OP4 E008F6 0 +OP4 E008F7 0 +OP4 E008F8 0 +OP4 E008F9 0 +OP4 E008FA 0 +OP4 E008FB 0 +OP4 E008FC 0 +OP4 E008FD 0 +OP4 E008FE 0 +OP4 E008FF 0 +OP4 E00900 0 +OP4 E00901 0 +OP4 E00902 0 +OP4 E00903 0 +OP4 E00904 0 +OP4 E00905 0 +OP4 E00906 0 +OP4 E00907 0 +OP4 E00908 0 +OP4 E00909 0 +OP4 E0090A 0 +OP4 E0090B 0 +OP4 E0090C 0 +OP4 E0090D 0 +OP4 E0090E 0 +OP4 E0090F 0 +OP4 E00910 0 +OP4 E00911 0 +OP4 E00912 0 +OP4 E00913 0 +OP4 E00914 0 +OP4 E00915 0 +OP4 E00916 0 +OP4 E00917 0 +OP4 E00918 0 +OP4 E00919 0 +OP4 E0091A 0 +OP4 E0091B 0 +OP4 E0091C 0 +OP4 E0091D 0 +OP4 E0091E 0 +OP4 E0091F 0 +OP4 E00920 0 +OP4 E00921 0 +OP4 E00922 0 +OP4 E00923 0 +OP4 E00924 0 +OP4 E00925 0 +OP4 E00926 0 +OP4 E00927 0 +OP4 E00928 0 +OP4 E00929 0 +OP4 E0092A 0 +OP4 E0092B 0 +OP4 E0092C 0 +OP4 E0092D 0 +OP4 E0092E 0 +OP4 E0092F 0 +OP4 E00930 0 +OP4 E00931 0 +OP4 E00932 0 +OP4 E00933 0 +OP4 E00934 0 +OP4 E00935 0 +OP4 E00936 0 +OP4 E00937 0 +OP4 E00938 0 +OP4 E00939 0 +OP4 E0093A 0 +OP4 E0093B 0 +OP4 E0093C 0 +OP4 E0093D 0 +OP4 E0093E 0 +OP4 E0093F 0 +OP4 E00940 0 +OP4 E00941 0 +OP4 E00942 0 +OP4 E00943 0 +OP4 E00944 0 +OP4 E00945 0 +OP4 E00946 0 +OP4 E00947 0 +OP4 E00948 0 +OP4 E00949 0 +OP4 E0094A 0 +OP4 E0094B 0 +OP4 E0094C 0 +OP4 E0094D 0 +OP4 E0094E 0 +OP4 E0094F 0 +OP4 E00950 0 +OP4 E00951 0 +OP4 E00952 0 +OP4 E00953 0 +OP4 E00954 0 +OP4 E00955 0 +OP4 E00956 0 +OP4 E00957 0 +OP4 E00958 0 +OP4 E00959 0 +OP4 E0095A 0 +OP4 E0095B 0 +OP4 E0095C 0 +OP4 E0095D 0 +OP4 E0095E 0 +OP4 E0095F 0 +OP4 E00960 0 +OP4 E00961 0 +OP4 E00962 0 +OP4 E00963 0 +OP4 E00964 0 +OP4 E00965 0 +OP4 E00966 0 +OP4 E00967 0 +OP4 E00968 0 +OP4 E00969 0 +OP4 E0096A 0 +OP4 E0096B 0 +OP4 E0096C 0 +OP4 E0096D 0 +OP4 E0096E 0 +OP4 E0096F 0 +OP4 E00970 0 +OP4 E00971 0 +OP4 E00972 0 +OP4 E00973 0 +OP4 E00974 0 +OP4 E00975 0 +OP4 E00976 0 +OP4 E00977 0 +OP4 E00978 0 +OP4 E00979 0 +OP4 E0097A 0 +OP4 E0097B 0 +OP4 E0097C 0 +OP4 E0097D 0 +OP4 E0097E 0 +OP4 E0097F 0 +OP4 E00980 0 +OP4 E00981 0 +OP4 E00982 0 +OP4 E00983 0 +OP4 E00984 0 +OP4 E00985 0 +OP4 E00986 0 +OP4 E00987 0 +OP4 E00988 0 +OP4 E00989 0 +OP4 E0098A 0 +OP4 E0098B 0 +OP4 E0098C 0 +OP4 E0098D 0 +OP4 E0098E 0 +OP4 E0098F 0 +OP4 E00990 0 +OP4 E00991 0 +OP4 E00992 0 +OP4 E00993 0 +OP4 E00994 0 +OP4 E00995 0 +OP4 E00996 0 +OP4 E00997 0 +OP4 E00998 0 +OP4 E00999 0 +OP4 E0099A 0 +OP4 E0099B 0 +OP4 E0099C 0 +OP4 E0099D 0 +OP4 E0099E 0 +OP4 E0099F 0 +OP4 E009A0 0 +OP4 E009A1 0 +OP4 E009A2 0 +OP4 E009A3 0 +OP4 E009A4 0 +OP4 E009A5 0 +OP4 E009A6 0 +OP4 E009A7 0 +OP4 E009A8 0 +OP4 E009A9 0 +OP4 E009AA 0 +OP4 E009AB 0 +OP4 E009AC 0 +OP4 E009AD 0 +OP4 E009AE 0 +OP4 E009AF 0 +OP4 E009B0 0 +OP4 E009B1 0 +OP4 E009B2 0 +OP4 E009B3 0 +OP4 E009B4 0 +OP4 E009B5 0 +OP4 E009B6 0 +OP4 E009B7 0 +OP4 E009B8 0 +OP4 E009B9 0 +OP4 E009BA 0 +OP4 E009BB 0 +OP4 E009BC 0 +OP4 E009BD 0 +OP4 E009BE 0 +OP4 E009BF 0 +OP4 E009C0 0 +OP4 E009C1 0 +OP4 E009C2 0 +OP4 E009C3 0 +OP4 E009C4 0 +OP4 E009C5 0 +OP4 E009C6 0 +OP4 E009C7 0 +OP4 E009C8 0 +OP4 E009C9 0 +OP4 E009CA 0 +OP4 E009CB 0 +OP4 E009CC 0 +OP4 E009CD 0 +OP4 E009CE 0 +OP4 E009CF 0 +OP4 E009D0 0 +OP4 E009D1 0 +OP4 E009D2 0 +OP4 E009D3 0 +OP4 E009D4 0 +OP4 E009D5 0 +OP4 E009D6 0 +OP4 E009D7 0 +OP4 E009D8 0 +OP4 E009D9 0 +OP4 E009DA 0 +OP4 E009DB 0 +OP4 E009DC 0 +OP4 E009DD 0 +OP4 E009DE 0 +OP4 E009DF 0 +OP4 E009E0 0 +OP4 E009E1 0 +OP4 E009E2 0 +OP4 E009E3 0 +OP4 E009E4 0 +OP4 E009E5 0 +OP4 E009E6 0 +OP4 E009E7 0 +OP4 E009E8 0 +OP4 E009E9 0 +OP4 E009EA 0 +OP4 E009EB 0 +OP4 E009EC 0 +OP4 E009ED 0 +OP4 E009EE 0 +OP4 E009EF 0 +OP4 E009F0 0 +OP4 E009F1 0 +OP4 E009F2 0 +OP4 E009F3 0 +OP4 E009F4 0 +OP4 E009F5 0 +OP4 E009F6 0 +OP4 E009F7 0 +OP4 E009F8 0 +OP4 E009F9 0 +OP4 E009FA 0 +OP4 E009FB 0 +OP4 E009FC 0 +OP4 E009FD 0 +OP4 E009FE 0 +OP4 E009FF 0 +OP4 E00A00 0 +OP4 E00A01 0 +OP4 E00A02 0 +OP4 E00A03 0 +OP4 E00A04 0 +OP4 E00A05 0 +OP4 E00A06 0 +OP4 E00A07 0 +OP4 E00A08 0 diff --git a/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum2_itrace_irisc5.cfg.ext b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum2_itrace_irisc5.cfg.ext new file mode 100644 index 000000000000..c70f5e004b18 --- /dev/null +++ b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum2_itrace_irisc5.cfg.ext @@ -0,0 +1,2570 @@ +OP1 Spectrum2 +OP4 ITRACE0 0 +OP4 ITRACE1 0 +OP4 ITRACE2 0 +OP4 ITRACE3 0 +OP4 ITRACE4 0 +OP4 ITRACE5 1 +OP4 ITRACE6 0 +OP4 ITRACE7 0 +OP4 Main_PhyUC 0 +OP4 E00009 0 +OP4 E0000A 0 +OP4 E0000B 0 +OP4 E0000C 0 +OP4 E0000D 0 +OP4 E0000E 0 +OP4 E0000F 0 +OP4 E00010 0 +OP4 E00011 0 +OP4 E00012 0 +OP4 E00013 0 +OP4 E00014 0 +OP4 E00015 0 +OP4 E00016 0 +OP4 E00017 0 +OP4 E00018 0 +OP4 E00019 0 +OP4 E0001A 0 +OP4 E0001B 0 +OP4 E0001C 0 +OP4 E0001D 0 +OP4 E0001E 0 +OP4 E0001F 0 +OP4 E00020 0 +OP4 E00021 0 +OP4 E00022 0 +OP4 E00023 0 +OP4 E00024 0 +OP4 E00025 0 +OP4 E00026 0 +OP4 E00027 0 +OP4 E00028 0 +OP4 E00029 0 +OP4 E0002A 0 +OP4 E0002B 0 +OP4 E0002C 0 +OP4 E0002D 0 +OP4 E0002E 0 +OP4 E0002F 0 +OP4 E00030 0 +OP4 E00031 0 +OP4 E00032 0 +OP4 E00033 0 +OP4 E00034 0 +OP4 E00035 0 +OP4 E00036 0 +OP4 E00037 0 +OP4 E00038 0 +OP4 E00039 0 +OP4 E0003A 0 +OP4 E0003B 0 +OP4 E0003C 0 +OP4 E0003D 0 +OP4 E0003E 0 +OP4 E0003F 0 +OP4 E00040 0 +OP4 E00041 0 +OP4 E00042 0 +OP4 E00043 0 +OP4 E00044 0 +OP4 E00045 0 +OP4 E00046 0 +OP4 E00047 0 +OP4 E00048 0 +OP4 E00049 0 +OP4 E0004A 0 +OP4 E0004B 0 +OP4 E0004C 0 +OP4 E0004D 0 +OP4 E0004E 0 +OP4 E0004F 0 +OP4 E00050 0 +OP4 E00051 0 +OP4 E00052 0 +OP4 E00053 0 +OP4 E00054 0 +OP4 E00055 0 +OP4 E00056 0 +OP4 E00057 0 +OP4 E00058 0 +OP4 E00059 0 +OP4 E0005A 0 +OP4 E0005B 0 +OP4 E0005C 0 +OP4 E0005D 0 +OP4 E0005E 0 +OP4 E0005F 0 +OP4 E00060 0 +OP4 E00061 0 +OP4 E00062 0 +OP4 E00063 0 +OP4 E00064 0 +OP4 E00065 0 +OP4 E00066 0 +OP4 E00067 0 +OP4 E00068 0 +OP4 E00069 0 +OP4 E0006A 0 +OP4 E0006B 0 +OP4 E0006C 0 +OP4 E0006D 0 +OP4 E0006E 0 +OP4 E0006F 0 +OP4 E00070 0 +OP4 E00071 0 +OP4 E00072 0 +OP4 E00073 0 +OP4 E00074 0 +OP4 E00075 0 +OP4 E00076 0 +OP4 E00077 0 +OP4 E00078 0 +OP4 E00079 0 +OP4 E0007A 0 +OP4 E0007B 0 +OP4 E0007C 0 +OP4 E0007D 0 +OP4 E0007E 0 +OP4 E0007F 0 +OP4 E00080 0 +OP4 E00081 0 +OP4 E00082 0 +OP4 E00083 0 +OP4 E00084 0 +OP4 E00085 0 +OP4 E00086 0 +OP4 E00087 0 +OP4 E00088 0 +OP4 E00089 0 +OP4 E0008A 0 +OP4 E0008B 0 +OP4 E0008C 0 +OP4 E0008D 0 +OP4 E0008E 0 +OP4 E0008F 0 +OP4 E00090 0 +OP4 E00091 0 +OP4 E00092 0 +OP4 E00093 0 +OP4 E00094 0 +OP4 E00095 0 +OP4 E00096 0 +OP4 E00097 0 +OP4 E00098 0 +OP4 E00099 0 +OP4 E0009A 0 +OP4 E0009B 0 +OP4 E0009C 0 +OP4 E0009D 0 +OP4 E0009E 0 +OP4 E0009F 0 +OP4 E000A0 0 +OP4 E000A1 0 +OP4 E000A2 0 +OP4 E000A3 0 +OP4 E000A4 0 +OP4 E000A5 0 +OP4 E000A6 0 +OP4 E000A7 0 +OP4 E000A8 0 +OP4 E000A9 0 +OP4 E000AA 0 +OP4 E000AB 0 +OP4 E000AC 0 +OP4 E000AD 0 +OP4 E000AE 0 +OP4 E000AF 0 +OP4 E000B0 0 +OP4 E000B1 0 +OP4 E000B2 0 +OP4 E000B3 0 +OP4 E000B4 0 +OP4 E000B5 0 +OP4 E000B6 0 +OP4 E000B7 0 +OP4 E000B8 0 +OP4 E000B9 0 +OP4 E000BA 0 +OP4 E000BB 0 +OP4 E000BC 0 +OP4 E000BD 0 +OP4 E000BE 0 +OP4 E000BF 0 +OP4 E000C0 0 +OP4 E000C1 0 +OP4 E000C2 0 +OP4 E000C3 0 +OP4 E000C4 0 +OP4 E000C5 0 +OP4 E000C6 0 +OP4 E000C7 0 +OP4 E000C8 0 +OP4 E000C9 0 +OP4 E000CA 0 +OP4 E000CB 0 +OP4 E000CC 0 +OP4 E000CD 0 +OP4 E000CE 0 +OP4 E000CF 0 +OP4 E000D0 0 +OP4 E000D1 0 +OP4 E000D2 0 +OP4 E000D3 0 +OP4 E000D4 0 +OP4 E000D5 0 +OP4 E000D6 0 +OP4 E000D7 0 +OP4 E000D8 0 +OP4 E000D9 0 +OP4 E000DA 0 +OP4 E000DB 0 +OP4 E000DC 0 +OP4 E000DD 0 +OP4 E000DE 0 +OP4 E000DF 0 +OP4 E000E0 0 +OP4 E000E1 0 +OP4 E000E2 0 +OP4 E000E3 0 +OP4 E000E4 0 +OP4 E000E5 0 +OP4 E000E6 0 +OP4 E000E7 0 +OP4 E000E8 0 +OP4 E000E9 0 +OP4 E000EA 0 +OP4 E000EB 0 +OP4 E000EC 0 +OP4 E000ED 0 +OP4 E000EE 0 +OP4 E000EF 0 +OP4 E000F0 0 +OP4 E000F1 0 +OP4 E000F2 0 +OP4 E000F3 0 +OP4 E000F4 0 +OP4 E000F5 0 +OP4 E000F6 0 +OP4 E000F7 0 +OP4 E000F8 0 +OP4 E000F9 0 +OP4 E000FA 0 +OP4 E000FB 0 +OP4 E000FC 0 +OP4 E000FD 0 +OP4 E000FE 0 +OP4 E000FF 0 +OP4 E00100 0 +OP4 E00101 0 +OP4 E00102 0 +OP4 E00103 0 +OP4 E00104 0 +OP4 E00105 0 +OP4 E00106 0 +OP4 E00107 0 +OP4 E00108 0 +OP4 E00109 0 +OP4 E0010A 0 +OP4 E0010B 0 +OP4 E0010C 0 +OP4 E0010D 0 +OP4 E0010E 0 +OP4 E0010F 0 +OP4 E00110 0 +OP4 E00111 0 +OP4 E00112 0 +OP4 E00113 0 +OP4 E00114 0 +OP4 E00115 0 +OP4 E00116 0 +OP4 E00117 0 +OP4 E00118 0 +OP4 E00119 0 +OP4 E0011A 0 +OP4 E0011B 0 +OP4 E0011C 0 +OP4 E0011D 0 +OP4 E0011E 0 +OP4 E0011F 0 +OP4 E00120 0 +OP4 E00121 0 +OP4 E00122 0 +OP4 E00123 0 +OP4 E00124 0 +OP4 E00125 0 +OP4 E00126 0 +OP4 E00127 0 +OP4 E00128 0 +OP4 E00129 0 +OP4 E0012A 0 +OP4 E0012B 0 +OP4 E0012C 0 +OP4 E0012D 0 +OP4 E0012E 0 +OP4 E0012F 0 +OP4 E00130 0 +OP4 E00131 0 +OP4 E00132 0 +OP4 E00133 0 +OP4 E00134 0 +OP4 E00135 0 +OP4 E00136 0 +OP4 E00137 0 +OP4 E00138 0 +OP4 E00139 0 +OP4 E0013A 0 +OP4 E0013B 0 +OP4 E0013C 0 +OP4 E0013D 0 +OP4 E0013E 0 +OP4 E0013F 0 +OP4 E00140 0 +OP4 E00141 0 +OP4 E00142 0 +OP4 E00143 0 +OP4 E00144 0 +OP4 E00145 0 +OP4 E00146 0 +OP4 E00147 0 +OP4 E00148 0 +OP4 E00149 0 +OP4 E0014A 0 +OP4 E0014B 0 +OP4 E0014C 0 +OP4 E0014D 0 +OP4 E0014E 0 +OP4 E0014F 0 +OP4 E00150 0 +OP4 E00151 0 +OP4 E00152 0 +OP4 E00153 0 +OP4 E00154 0 +OP4 E00155 0 +OP4 E00156 0 +OP4 E00157 0 +OP4 E00158 0 +OP4 E00159 0 +OP4 E0015A 0 +OP4 E0015B 0 +OP4 E0015C 0 +OP4 E0015D 0 +OP4 E0015E 0 +OP4 E0015F 0 +OP4 E00160 0 +OP4 E00161 0 +OP4 E00162 0 +OP4 E00163 0 +OP4 E00164 0 +OP4 E00165 0 +OP4 E00166 0 +OP4 E00167 0 +OP4 E00168 0 +OP4 E00169 0 +OP4 E0016A 0 +OP4 E0016B 0 +OP4 E0016C 0 +OP4 E0016D 0 +OP4 E0016E 0 +OP4 E0016F 0 +OP4 E00170 0 +OP4 E00171 0 +OP4 E00172 0 +OP4 E00173 0 +OP4 E00174 0 +OP4 E00175 0 +OP4 E00176 0 +OP4 E00177 0 +OP4 E00178 0 +OP4 E00179 0 +OP4 E0017A 0 +OP4 E0017B 0 +OP4 E0017C 0 +OP4 E0017D 0 +OP4 E0017E 0 +OP4 E0017F 0 +OP4 E00180 0 +OP4 E00181 0 +OP4 E00182 0 +OP4 E00183 0 +OP4 E00184 0 +OP4 E00185 0 +OP4 E00186 0 +OP4 E00187 0 +OP4 E00188 0 +OP4 E00189 0 +OP4 E0018A 0 +OP4 E0018B 0 +OP4 E0018C 0 +OP4 E0018D 0 +OP4 E0018E 0 +OP4 E0018F 0 +OP4 E00190 0 +OP4 E00191 0 +OP4 E00192 0 +OP4 E00193 0 +OP4 E00194 0 +OP4 E00195 0 +OP4 E00196 0 +OP4 E00197 0 +OP4 E00198 0 +OP4 E00199 0 +OP4 E0019A 0 +OP4 E0019B 0 +OP4 E0019C 0 +OP4 E0019D 0 +OP4 E0019E 0 +OP4 E0019F 0 +OP4 E001A0 0 +OP4 E001A1 0 +OP4 E001A2 0 +OP4 E001A3 0 +OP4 E001A4 0 +OP4 E001A5 0 +OP4 E001A6 0 +OP4 E001A7 0 +OP4 E001A8 0 +OP4 E001A9 0 +OP4 E001AA 0 +OP4 E001AB 0 +OP4 E001AC 0 +OP4 E001AD 0 +OP4 E001AE 0 +OP4 E001AF 0 +OP4 E001B0 0 +OP4 E001B1 0 +OP4 E001B2 0 +OP4 E001B3 0 +OP4 E001B4 0 +OP4 E001B5 0 +OP4 E001B6 0 +OP4 E001B7 0 +OP4 E001B8 0 +OP4 E001B9 0 +OP4 E001BA 0 +OP4 E001BB 0 +OP4 E001BC 0 +OP4 E001BD 0 +OP4 E001BE 0 +OP4 E001BF 0 +OP4 E001C0 0 +OP4 E001C1 0 +OP4 E001C2 0 +OP4 E001C3 0 +OP4 E001C4 0 +OP4 E001C5 0 +OP4 E001C6 0 +OP4 E001C7 0 +OP4 E001C8 0 +OP4 E001C9 0 +OP4 E001CA 0 +OP4 E001CB 0 +OP4 E001CC 0 +OP4 E001CD 0 +OP4 E001CE 0 +OP4 E001CF 0 +OP4 E001D0 0 +OP4 E001D1 0 +OP4 E001D2 0 +OP4 E001D3 0 +OP4 E001D4 0 +OP4 E001D5 0 +OP4 E001D6 0 +OP4 E001D7 0 +OP4 E001D8 0 +OP4 E001D9 0 +OP4 E001DA 0 +OP4 E001DB 0 +OP4 E001DC 0 +OP4 E001DD 0 +OP4 E001DE 0 +OP4 E001DF 0 +OP4 E001E0 0 +OP4 E001E1 0 +OP4 E001E2 0 +OP4 E001E3 0 +OP4 E001E4 0 +OP4 E001E5 0 +OP4 E001E6 0 +OP4 E001E7 0 +OP4 E001E8 0 +OP4 E001E9 0 +OP4 E001EA 0 +OP4 E001EB 0 +OP4 E001EC 0 +OP4 E001ED 0 +OP4 E001EE 0 +OP4 E001EF 0 +OP4 E001F0 0 +OP4 E001F1 0 +OP4 E001F2 0 +OP4 E001F3 0 +OP4 E001F4 0 +OP4 E001F5 0 +OP4 E001F6 0 +OP4 E001F7 0 +OP4 E001F8 0 +OP4 E001F9 0 +OP4 E001FA 0 +OP4 E001FB 0 +OP4 E001FC 0 +OP4 E001FD 0 +OP4 E001FE 0 +OP4 E001FF 0 +OP4 E00200 0 +OP4 E00201 0 +OP4 E00202 0 +OP4 E00203 0 +OP4 E00204 0 +OP4 E00205 0 +OP4 E00206 0 +OP4 E00207 0 +OP4 E00208 0 +OP4 E00209 0 +OP4 E0020A 0 +OP4 E0020B 0 +OP4 E0020C 0 +OP4 E0020D 0 +OP4 E0020E 0 +OP4 E0020F 0 +OP4 E00210 0 +OP4 E00211 0 +OP4 E00212 0 +OP4 E00213 0 +OP4 E00214 0 +OP4 E00215 0 +OP4 E00216 0 +OP4 E00217 0 +OP4 E00218 0 +OP4 E00219 0 +OP4 E0021A 0 +OP4 E0021B 0 +OP4 E0021C 0 +OP4 E0021D 0 +OP4 E0021E 0 +OP4 E0021F 0 +OP4 E00220 0 +OP4 E00221 0 +OP4 E00222 0 +OP4 E00223 0 +OP4 E00224 0 +OP4 E00225 0 +OP4 E00226 0 +OP4 E00227 0 +OP4 E00228 0 +OP4 E00229 0 +OP4 E0022A 0 +OP4 E0022B 0 +OP4 E0022C 0 +OP4 E0022D 0 +OP4 E0022E 0 +OP4 E0022F 0 +OP4 E00230 0 +OP4 E00231 0 +OP4 E00232 0 +OP4 E00233 0 +OP4 E00234 0 +OP4 E00235 0 +OP4 E00236 0 +OP4 E00237 0 +OP4 E00238 0 +OP4 E00239 0 +OP4 E0023A 0 +OP4 E0023B 0 +OP4 E0023C 0 +OP4 E0023D 0 +OP4 E0023E 0 +OP4 E0023F 0 +OP4 E00240 0 +OP4 E00241 0 +OP4 E00242 0 +OP4 E00243 0 +OP4 E00244 0 +OP4 E00245 0 +OP4 E00246 0 +OP4 E00247 0 +OP4 E00248 0 +OP4 E00249 0 +OP4 E0024A 0 +OP4 E0024B 0 +OP4 E0024C 0 +OP4 E0024D 0 +OP4 E0024E 0 +OP4 E0024F 0 +OP4 E00250 0 +OP4 E00251 0 +OP4 E00252 0 +OP4 E00253 0 +OP4 E00254 0 +OP4 E00255 0 +OP4 E00256 0 +OP4 E00257 0 +OP4 E00258 0 +OP4 E00259 0 +OP4 E0025A 0 +OP4 E0025B 0 +OP4 E0025C 0 +OP4 E0025D 0 +OP4 E0025E 0 +OP4 E0025F 0 +OP4 E00260 0 +OP4 E00261 0 +OP4 E00262 0 +OP4 E00263 0 +OP4 E00264 0 +OP4 E00265 0 +OP4 E00266 0 +OP4 E00267 0 +OP4 E00268 0 +OP4 E00269 0 +OP4 E0026A 0 +OP4 E0026B 0 +OP4 E0026C 0 +OP4 E0026D 0 +OP4 E0026E 0 +OP4 E0026F 0 +OP4 E00270 0 +OP4 E00271 0 +OP4 E00272 0 +OP4 E00273 0 +OP4 E00274 0 +OP4 E00275 0 +OP4 E00276 0 +OP4 E00277 0 +OP4 E00278 0 +OP4 E00279 0 +OP4 E0027A 0 +OP4 E0027B 0 +OP4 E0027C 0 +OP4 E0027D 0 +OP4 E0027E 0 +OP4 E0027F 0 +OP4 E00280 0 +OP4 E00281 0 +OP4 E00282 0 +OP4 E00283 0 +OP4 E00284 0 +OP4 E00285 0 +OP4 E00286 0 +OP4 E00287 0 +OP4 E00288 0 +OP4 E00289 0 +OP4 E0028A 0 +OP4 E0028B 0 +OP4 E0028C 0 +OP4 E0028D 0 +OP4 E0028E 0 +OP4 E0028F 0 +OP4 E00290 0 +OP4 E00291 0 +OP4 E00292 0 +OP4 E00293 0 +OP4 E00294 0 +OP4 E00295 0 +OP4 E00296 0 +OP4 E00297 0 +OP4 E00298 0 +OP4 E00299 0 +OP4 E0029A 0 +OP4 E0029B 0 +OP4 E0029C 0 +OP4 E0029D 0 +OP4 E0029E 0 +OP4 E0029F 0 +OP4 E002A0 0 +OP4 E002A1 0 +OP4 E002A2 0 +OP4 E002A3 0 +OP4 E002A4 0 +OP4 E002A5 0 +OP4 E002A6 0 +OP4 E002A7 0 +OP4 E002A8 0 +OP4 E002A9 0 +OP4 E002AA 0 +OP4 E002AB 0 +OP4 E002AC 0 +OP4 E002AD 0 +OP4 E002AE 0 +OP4 E002AF 0 +OP4 E002B0 0 +OP4 E002B1 0 +OP4 E002B2 0 +OP4 E002B3 0 +OP4 E002B4 0 +OP4 E002B5 0 +OP4 E002B6 0 +OP4 E002B7 0 +OP4 E002B8 0 +OP4 E002B9 0 +OP4 E002BA 0 +OP4 E002BB 0 +OP4 E002BC 0 +OP4 E002BD 0 +OP4 E002BE 0 +OP4 E002BF 0 +OP4 E002C0 0 +OP4 E002C1 0 +OP4 E002C2 0 +OP4 E002C3 0 +OP4 E002C4 0 +OP4 E002C5 0 +OP4 E002C6 0 +OP4 E002C7 0 +OP4 E002C8 0 +OP4 E002C9 0 +OP4 E002CA 0 +OP4 E002CB 0 +OP4 E002CC 0 +OP4 E002CD 0 +OP4 E002CE 0 +OP4 E002CF 0 +OP4 E002D0 0 +OP4 E002D1 0 +OP4 E002D2 0 +OP4 E002D3 0 +OP4 E002D4 0 +OP4 E002D5 0 +OP4 E002D6 0 +OP4 E002D7 0 +OP4 E002D8 0 +OP4 E002D9 0 +OP4 E002DA 0 +OP4 E002DB 0 +OP4 E002DC 0 +OP4 E002DD 0 +OP4 E002DE 0 +OP4 E002DF 0 +OP4 E002E0 0 +OP4 E002E1 0 +OP4 E002E2 0 +OP4 E002E3 0 +OP4 E002E4 0 +OP4 E002E5 0 +OP4 E002E6 0 +OP4 E002E7 0 +OP4 E002E8 0 +OP4 E002E9 0 +OP4 E002EA 0 +OP4 E002EB 0 +OP4 E002EC 0 +OP4 E002ED 0 +OP4 E002EE 0 +OP4 E002EF 0 +OP4 E002F0 0 +OP4 E002F1 0 +OP4 E002F2 0 +OP4 E002F3 0 +OP4 E002F4 0 +OP4 E002F5 0 +OP4 E002F6 0 +OP4 E002F7 0 +OP4 E002F8 0 +OP4 E002F9 0 +OP4 E002FA 0 +OP4 E002FB 0 +OP4 E002FC 0 +OP4 E002FD 0 +OP4 E002FE 0 +OP4 E002FF 0 +OP4 E00300 0 +OP4 E00301 0 +OP4 E00302 0 +OP4 E00303 0 +OP4 E00304 0 +OP4 E00305 0 +OP4 E00306 0 +OP4 E00307 0 +OP4 E00308 0 +OP4 E00309 0 +OP4 E0030A 0 +OP4 E0030B 0 +OP4 E0030C 0 +OP4 E0030D 0 +OP4 E0030E 0 +OP4 E0030F 0 +OP4 E00310 0 +OP4 E00311 0 +OP4 E00312 0 +OP4 E00313 0 +OP4 E00314 0 +OP4 E00315 0 +OP4 E00316 0 +OP4 E00317 0 +OP4 E00318 0 +OP4 E00319 0 +OP4 E0031A 0 +OP4 E0031B 0 +OP4 E0031C 0 +OP4 E0031D 0 +OP4 E0031E 0 +OP4 E0031F 0 +OP4 E00320 0 +OP4 E00321 0 +OP4 E00322 0 +OP4 E00323 0 +OP4 E00324 0 +OP4 E00325 0 +OP4 E00326 0 +OP4 E00327 0 +OP4 E00328 0 +OP4 E00329 0 +OP4 E0032A 0 +OP4 E0032B 0 +OP4 E0032C 0 +OP4 E0032D 0 +OP4 E0032E 0 +OP4 E0032F 0 +OP4 E00330 0 +OP4 E00331 0 +OP4 E00332 0 +OP4 E00333 0 +OP4 E00334 0 +OP4 E00335 0 +OP4 E00336 0 +OP4 E00337 0 +OP4 E00338 0 +OP4 E00339 0 +OP4 E0033A 0 +OP4 E0033B 0 +OP4 E0033C 0 +OP4 E0033D 0 +OP4 E0033E 0 +OP4 E0033F 0 +OP4 E00340 0 +OP4 E00341 0 +OP4 E00342 0 +OP4 E00343 0 +OP4 E00344 0 +OP4 E00345 0 +OP4 E00346 0 +OP4 E00347 0 +OP4 E00348 0 +OP4 E00349 0 +OP4 E0034A 0 +OP4 E0034B 0 +OP4 E0034C 0 +OP4 E0034D 0 +OP4 E0034E 0 +OP4 E0034F 0 +OP4 E00350 0 +OP4 E00351 0 +OP4 E00352 0 +OP4 E00353 0 +OP4 E00354 0 +OP4 E00355 0 +OP4 E00356 0 +OP4 E00357 0 +OP4 E00358 0 +OP4 E00359 0 +OP4 E0035A 0 +OP4 E0035B 0 +OP4 E0035C 0 +OP4 E0035D 0 +OP4 E0035E 0 +OP4 E0035F 0 +OP4 E00360 0 +OP4 E00361 0 +OP4 E00362 0 +OP4 E00363 0 +OP4 E00364 0 +OP4 E00365 0 +OP4 E00366 0 +OP4 E00367 0 +OP4 E00368 0 +OP4 E00369 0 +OP4 E0036A 0 +OP4 E0036B 0 +OP4 E0036C 0 +OP4 E0036D 0 +OP4 E0036E 0 +OP4 E0036F 0 +OP4 E00370 0 +OP4 E00371 0 +OP4 E00372 0 +OP4 E00373 0 +OP4 E00374 0 +OP4 E00375 0 +OP4 E00376 0 +OP4 E00377 0 +OP4 E00378 0 +OP4 E00379 0 +OP4 E0037A 0 +OP4 E0037B 0 +OP4 E0037C 0 +OP4 E0037D 0 +OP4 E0037E 0 +OP4 E0037F 0 +OP4 E00380 0 +OP4 E00381 0 +OP4 E00382 0 +OP4 E00383 0 +OP4 E00384 0 +OP4 E00385 0 +OP4 E00386 0 +OP4 E00387 0 +OP4 E00388 0 +OP4 E00389 0 +OP4 E0038A 0 +OP4 E0038B 0 +OP4 E0038C 0 +OP4 E0038D 0 +OP4 E0038E 0 +OP4 E0038F 0 +OP4 E00390 0 +OP4 E00391 0 +OP4 E00392 0 +OP4 E00393 0 +OP4 E00394 0 +OP4 E00395 0 +OP4 E00396 0 +OP4 E00397 0 +OP4 E00398 0 +OP4 E00399 0 +OP4 E0039A 0 +OP4 E0039B 0 +OP4 E0039C 0 +OP4 E0039D 0 +OP4 E0039E 0 +OP4 E0039F 0 +OP4 E003A0 0 +OP4 E003A1 0 +OP4 E003A2 0 +OP4 E003A3 0 +OP4 E003A4 0 +OP4 E003A5 0 +OP4 E003A6 0 +OP4 E003A7 0 +OP4 E003A8 0 +OP4 E003A9 0 +OP4 E003AA 0 +OP4 E003AB 0 +OP4 E003AC 0 +OP4 E003AD 0 +OP4 E003AE 0 +OP4 E003AF 0 +OP4 E003B0 0 +OP4 E003B1 0 +OP4 E003B2 0 +OP4 E003B3 0 +OP4 E003B4 0 +OP4 E003B5 0 +OP4 E003B6 0 +OP4 E003B7 0 +OP4 E003B8 0 +OP4 E003B9 0 +OP4 E003BA 0 +OP4 E003BB 0 +OP4 E003BC 0 +OP4 E003BD 0 +OP4 E003BE 0 +OP4 E003BF 0 +OP4 E003C0 0 +OP4 E003C1 0 +OP4 E003C2 0 +OP4 E003C3 0 +OP4 E003C4 0 +OP4 E003C5 0 +OP4 E003C6 0 +OP4 E003C7 0 +OP4 E003C8 0 +OP4 E003C9 0 +OP4 E003CA 0 +OP4 E003CB 0 +OP4 E003CC 0 +OP4 E003CD 0 +OP4 E003CE 0 +OP4 E003CF 0 +OP4 E003D0 0 +OP4 E003D1 0 +OP4 E003D2 0 +OP4 E003D3 0 +OP4 E003D4 0 +OP4 E003D5 0 +OP4 E003D6 0 +OP4 E003D7 0 +OP4 E003D8 0 +OP4 E003D9 0 +OP4 E003DA 0 +OP4 E003DB 0 +OP4 E003DC 0 +OP4 E003DD 0 +OP4 E003DE 0 +OP4 E003DF 0 +OP4 E003E0 0 +OP4 E003E1 0 +OP4 E003E2 0 +OP4 E003E3 0 +OP4 E003E4 0 +OP4 E003E5 0 +OP4 E003E6 0 +OP4 E003E7 0 +OP4 E003E8 0 +OP4 E003E9 0 +OP4 E003EA 0 +OP4 E003EB 0 +OP4 E003EC 0 +OP4 E003ED 0 +OP4 E003EE 0 +OP4 E003EF 0 +OP4 E003F0 0 +OP4 E003F1 0 +OP4 E003F2 0 +OP4 E003F3 0 +OP4 E003F4 0 +OP4 E003F5 0 +OP4 E003F6 0 +OP4 E003F7 0 +OP4 E003F8 0 +OP4 E003F9 0 +OP4 E003FA 0 +OP4 E003FB 0 +OP4 E003FC 0 +OP4 E003FD 0 +OP4 E003FE 0 +OP4 E003FF 0 +OP4 E00400 0 +OP4 E00401 0 +OP4 E00402 0 +OP4 E00403 0 +OP4 E00404 0 +OP4 E00405 0 +OP4 E00406 0 +OP4 E00407 0 +OP4 E00408 0 +OP4 E00409 0 +OP4 E0040A 0 +OP4 E0040B 0 +OP4 E0040C 0 +OP4 E0040D 0 +OP4 E0040E 0 +OP4 E0040F 0 +OP4 E00410 0 +OP4 E00411 0 +OP4 E00412 0 +OP4 E00413 0 +OP4 E00414 0 +OP4 E00415 0 +OP4 E00416 0 +OP4 E00417 0 +OP4 E00418 0 +OP4 E00419 0 +OP4 E0041A 0 +OP4 E0041B 0 +OP4 E0041C 0 +OP4 E0041D 0 +OP4 E0041E 0 +OP4 E0041F 0 +OP4 E00420 0 +OP4 E00421 0 +OP4 E00422 0 +OP4 E00423 0 +OP4 E00424 0 +OP4 E00425 0 +OP4 E00426 0 +OP4 E00427 0 +OP4 E00428 0 +OP4 E00429 0 +OP4 E0042A 0 +OP4 E0042B 0 +OP4 E0042C 0 +OP4 E0042D 0 +OP4 E0042E 0 +OP4 E0042F 0 +OP4 E00430 0 +OP4 E00431 0 +OP4 E00432 0 +OP4 E00433 0 +OP4 E00434 0 +OP4 E00435 0 +OP4 E00436 0 +OP4 E00437 0 +OP4 E00438 0 +OP4 E00439 0 +OP4 E0043A 0 +OP4 E0043B 0 +OP4 E0043C 0 +OP4 E0043D 0 +OP4 E0043E 0 +OP4 E0043F 0 +OP4 E00440 0 +OP4 E00441 0 +OP4 E00442 0 +OP4 E00443 0 +OP4 E00444 0 +OP4 E00445 0 +OP4 E00446 0 +OP4 E00447 0 +OP4 E00448 0 +OP4 E00449 0 +OP4 E0044A 0 +OP4 E0044B 0 +OP4 E0044C 0 +OP4 E0044D 0 +OP4 E0044E 0 +OP4 E0044F 0 +OP4 E00450 0 +OP4 E00451 0 +OP4 E00452 0 +OP4 E00453 0 +OP4 E00454 0 +OP4 E00455 0 +OP4 E00456 0 +OP4 E00457 0 +OP4 E00458 0 +OP4 E00459 0 +OP4 E0045A 0 +OP4 E0045B 0 +OP4 E0045C 0 +OP4 E0045D 0 +OP4 E0045E 0 +OP4 E0045F 0 +OP4 E00460 0 +OP4 E00461 0 +OP4 E00462 0 +OP4 E00463 0 +OP4 E00464 0 +OP4 E00465 0 +OP4 E00466 0 +OP4 E00467 0 +OP4 E00468 0 +OP4 E00469 0 +OP4 E0046A 0 +OP4 E0046B 0 +OP4 E0046C 0 +OP4 E0046D 0 +OP4 E0046E 0 +OP4 E0046F 0 +OP4 E00470 0 +OP4 E00471 0 +OP4 E00472 0 +OP4 E00473 0 +OP4 E00474 0 +OP4 E00475 0 +OP4 E00476 0 +OP4 E00477 0 +OP4 E00478 0 +OP4 E00479 0 +OP4 E0047A 0 +OP4 E0047B 0 +OP4 E0047C 0 +OP4 E0047D 0 +OP4 E0047E 0 +OP4 E0047F 0 +OP4 E00480 0 +OP4 E00481 0 +OP4 E00482 0 +OP4 E00483 0 +OP4 E00484 0 +OP4 E00485 0 +OP4 E00486 0 +OP4 E00487 0 +OP4 E00488 0 +OP4 E00489 0 +OP4 E0048A 0 +OP4 E0048B 0 +OP4 E0048C 0 +OP4 E0048D 0 +OP4 E0048E 0 +OP4 E0048F 0 +OP4 E00490 0 +OP4 E00491 0 +OP4 E00492 0 +OP4 E00493 0 +OP4 E00494 0 +OP4 E00495 0 +OP4 E00496 0 +OP4 E00497 0 +OP4 E00498 0 +OP4 E00499 0 +OP4 E0049A 0 +OP4 E0049B 0 +OP4 E0049C 0 +OP4 E0049D 0 +OP4 E0049E 0 +OP4 E0049F 0 +OP4 E004A0 0 +OP4 E004A1 0 +OP4 E004A2 0 +OP4 E004A3 0 +OP4 E004A4 0 +OP4 E004A5 0 +OP4 E004A6 0 +OP4 E004A7 0 +OP4 E004A8 0 +OP4 E004A9 0 +OP4 E004AA 0 +OP4 E004AB 0 +OP4 E004AC 0 +OP4 E004AD 0 +OP4 E004AE 0 +OP4 E004AF 0 +OP4 E004B0 0 +OP4 E004B1 0 +OP4 E004B2 0 +OP4 E004B3 0 +OP4 E004B4 0 +OP4 E004B5 0 +OP4 E004B6 0 +OP4 E004B7 0 +OP4 E004B8 0 +OP4 E004B9 0 +OP4 E004BA 0 +OP4 E004BB 0 +OP4 E004BC 0 +OP4 E004BD 0 +OP4 E004BE 0 +OP4 E004BF 0 +OP4 E004C0 0 +OP4 E004C1 0 +OP4 E004C2 0 +OP4 E004C3 0 +OP4 E004C4 0 +OP4 E004C5 0 +OP4 E004C6 0 +OP4 E004C7 0 +OP4 E004C8 0 +OP4 E004C9 0 +OP4 E004CA 0 +OP4 E004CB 0 +OP4 E004CC 0 +OP4 E004CD 0 +OP4 E004CE 0 +OP4 E004CF 0 +OP4 E004D0 0 +OP4 E004D1 0 +OP4 E004D2 0 +OP4 E004D3 0 +OP4 E004D4 0 +OP4 E004D5 0 +OP4 E004D6 0 +OP4 E004D7 0 +OP4 E004D8 0 +OP4 E004D9 0 +OP4 E004DA 0 +OP4 E004DB 0 +OP4 E004DC 0 +OP4 E004DD 0 +OP4 E004DE 0 +OP4 E004DF 0 +OP4 E004E0 0 +OP4 E004E1 0 +OP4 E004E2 0 +OP4 E004E3 0 +OP4 E004E4 0 +OP4 E004E5 0 +OP4 E004E6 0 +OP4 E004E7 0 +OP4 E004E8 0 +OP4 E004E9 0 +OP4 E004EA 0 +OP4 E004EB 0 +OP4 E004EC 0 +OP4 E004ED 0 +OP4 E004EE 0 +OP4 E004EF 0 +OP4 E004F0 0 +OP4 E004F1 0 +OP4 E004F2 0 +OP4 E004F3 0 +OP4 E004F4 0 +OP4 E004F5 0 +OP4 E004F6 0 +OP4 E004F7 0 +OP4 E004F8 0 +OP4 E004F9 0 +OP4 E004FA 0 +OP4 E004FB 0 +OP4 E004FC 0 +OP4 E004FD 0 +OP4 E004FE 0 +OP4 E004FF 0 +OP4 E00500 0 +OP4 E00501 0 +OP4 E00502 0 +OP4 E00503 0 +OP4 E00504 0 +OP4 E00505 0 +OP4 E00506 0 +OP4 E00507 0 +OP4 E00508 0 +OP4 E00509 0 +OP4 E0050A 0 +OP4 E0050B 0 +OP4 E0050C 0 +OP4 E0050D 0 +OP4 E0050E 0 +OP4 E0050F 0 +OP4 E00510 0 +OP4 E00511 0 +OP4 E00512 0 +OP4 E00513 0 +OP4 E00514 0 +OP4 E00515 0 +OP4 E00516 0 +OP4 E00517 0 +OP4 E00518 0 +OP4 E00519 0 +OP4 E0051A 0 +OP4 E0051B 0 +OP4 E0051C 0 +OP4 E0051D 0 +OP4 E0051E 0 +OP4 E0051F 0 +OP4 E00520 0 +OP4 E00521 0 +OP4 E00522 0 +OP4 E00523 0 +OP4 E00524 0 +OP4 E00525 0 +OP4 E00526 0 +OP4 E00527 0 +OP4 E00528 0 +OP4 E00529 0 +OP4 E0052A 0 +OP4 E0052B 0 +OP4 E0052C 0 +OP4 E0052D 0 +OP4 E0052E 0 +OP4 E0052F 0 +OP4 E00530 0 +OP4 E00531 0 +OP4 E00532 0 +OP4 E00533 0 +OP4 E00534 0 +OP4 E00535 0 +OP4 E00536 0 +OP4 E00537 0 +OP4 E00538 0 +OP4 E00539 0 +OP4 E0053A 0 +OP4 E0053B 0 +OP4 E0053C 0 +OP4 E0053D 0 +OP4 E0053E 0 +OP4 E0053F 0 +OP4 E00540 0 +OP4 E00541 0 +OP4 E00542 0 +OP4 E00543 0 +OP4 E00544 0 +OP4 E00545 0 +OP4 E00546 0 +OP4 E00547 0 +OP4 E00548 0 +OP4 E00549 0 +OP4 E0054A 0 +OP4 E0054B 0 +OP4 E0054C 0 +OP4 E0054D 0 +OP4 E0054E 0 +OP4 E0054F 0 +OP4 E00550 0 +OP4 E00551 0 +OP4 E00552 0 +OP4 E00553 0 +OP4 E00554 0 +OP4 E00555 0 +OP4 E00556 0 +OP4 E00557 0 +OP4 E00558 0 +OP4 E00559 0 +OP4 E0055A 0 +OP4 E0055B 0 +OP4 E0055C 0 +OP4 E0055D 0 +OP4 E0055E 0 +OP4 E0055F 0 +OP4 E00560 0 +OP4 E00561 0 +OP4 E00562 0 +OP4 E00563 0 +OP4 E00564 0 +OP4 E00565 0 +OP4 E00566 0 +OP4 E00567 0 +OP4 E00568 0 +OP4 E00569 0 +OP4 E0056A 0 +OP4 E0056B 0 +OP4 E0056C 0 +OP4 E0056D 0 +OP4 E0056E 0 +OP4 E0056F 0 +OP4 E00570 0 +OP4 E00571 0 +OP4 E00572 0 +OP4 E00573 0 +OP4 E00574 0 +OP4 E00575 0 +OP4 E00576 0 +OP4 E00577 0 +OP4 E00578 0 +OP4 E00579 0 +OP4 E0057A 0 +OP4 E0057B 0 +OP4 E0057C 0 +OP4 E0057D 0 +OP4 E0057E 0 +OP4 E0057F 0 +OP4 E00580 0 +OP4 E00581 0 +OP4 E00582 0 +OP4 E00583 0 +OP4 E00584 0 +OP4 E00585 0 +OP4 E00586 0 +OP4 E00587 0 +OP4 E00588 0 +OP4 E00589 0 +OP4 E0058A 0 +OP4 E0058B 0 +OP4 E0058C 0 +OP4 E0058D 0 +OP4 E0058E 0 +OP4 E0058F 0 +OP4 E00590 0 +OP4 E00591 0 +OP4 E00592 0 +OP4 E00593 0 +OP4 E00594 0 +OP4 E00595 0 +OP4 E00596 0 +OP4 E00597 0 +OP4 E00598 0 +OP4 E00599 0 +OP4 E0059A 0 +OP4 E0059B 0 +OP4 E0059C 0 +OP4 E0059D 0 +OP4 E0059E 0 +OP4 E0059F 0 +OP4 E005A0 0 +OP4 E005A1 0 +OP4 E005A2 0 +OP4 E005A3 0 +OP4 E005A4 0 +OP4 E005A5 0 +OP4 E005A6 0 +OP4 E005A7 0 +OP4 E005A8 0 +OP4 E005A9 0 +OP4 E005AA 0 +OP4 E005AB 0 +OP4 E005AC 0 +OP4 E005AD 0 +OP4 E005AE 0 +OP4 E005AF 0 +OP4 E005B0 0 +OP4 E005B1 0 +OP4 E005B2 0 +OP4 E005B3 0 +OP4 E005B4 0 +OP4 E005B5 0 +OP4 E005B6 0 +OP4 E005B7 0 +OP4 E005B8 0 +OP4 E005B9 0 +OP4 E005BA 0 +OP4 E005BB 0 +OP4 E005BC 0 +OP4 E005BD 0 +OP4 E005BE 0 +OP4 E005BF 0 +OP4 E005C0 0 +OP4 E005C1 0 +OP4 E005C2 0 +OP4 E005C3 0 +OP4 E005C4 0 +OP4 E005C5 0 +OP4 E005C6 0 +OP4 E005C7 0 +OP4 E005C8 0 +OP4 E005C9 0 +OP4 E005CA 0 +OP4 E005CB 0 +OP4 E005CC 0 +OP4 E005CD 0 +OP4 E005CE 0 +OP4 E005CF 0 +OP4 E005D0 0 +OP4 E005D1 0 +OP4 E005D2 0 +OP4 E005D3 0 +OP4 E005D4 0 +OP4 E005D5 0 +OP4 E005D6 0 +OP4 E005D7 0 +OP4 E005D8 0 +OP4 E005D9 0 +OP4 E005DA 0 +OP4 E005DB 0 +OP4 E005DC 0 +OP4 E005DD 0 +OP4 E005DE 0 +OP4 E005DF 0 +OP4 E005E0 0 +OP4 E005E1 0 +OP4 E005E2 0 +OP4 E005E3 0 +OP4 E005E4 0 +OP4 E005E5 0 +OP4 E005E6 0 +OP4 E005E7 0 +OP4 E005E8 0 +OP4 E005E9 0 +OP4 E005EA 0 +OP4 E005EB 0 +OP4 E005EC 0 +OP4 E005ED 0 +OP4 E005EE 0 +OP4 E005EF 0 +OP4 E005F0 0 +OP4 E005F1 0 +OP4 E005F2 0 +OP4 E005F3 0 +OP4 E005F4 0 +OP4 E005F5 0 +OP4 E005F6 0 +OP4 E005F7 0 +OP4 E005F8 0 +OP4 E005F9 0 +OP4 E005FA 0 +OP4 E005FB 0 +OP4 E005FC 0 +OP4 E005FD 0 +OP4 E005FE 0 +OP4 E005FF 0 +OP4 E00600 0 +OP4 E00601 0 +OP4 E00602 0 +OP4 E00603 0 +OP4 E00604 0 +OP4 E00605 0 +OP4 E00606 0 +OP4 E00607 0 +OP4 E00608 0 +OP4 E00609 0 +OP4 E0060A 0 +OP4 E0060B 0 +OP4 E0060C 0 +OP4 E0060D 0 +OP4 E0060E 0 +OP4 E0060F 0 +OP4 E00610 0 +OP4 E00611 0 +OP4 E00612 0 +OP4 E00613 0 +OP4 E00614 0 +OP4 E00615 0 +OP4 E00616 0 +OP4 E00617 0 +OP4 E00618 0 +OP4 E00619 0 +OP4 E0061A 0 +OP4 E0061B 0 +OP4 E0061C 0 +OP4 E0061D 0 +OP4 E0061E 0 +OP4 E0061F 0 +OP4 E00620 0 +OP4 E00621 0 +OP4 E00622 0 +OP4 E00623 0 +OP4 E00624 0 +OP4 E00625 0 +OP4 E00626 0 +OP4 E00627 0 +OP4 E00628 0 +OP4 E00629 0 +OP4 E0062A 0 +OP4 E0062B 0 +OP4 E0062C 0 +OP4 E0062D 0 +OP4 E0062E 0 +OP4 E0062F 0 +OP4 E00630 0 +OP4 E00631 0 +OP4 E00632 0 +OP4 E00633 0 +OP4 E00634 0 +OP4 E00635 0 +OP4 E00636 0 +OP4 E00637 0 +OP4 E00638 0 +OP4 E00639 0 +OP4 E0063A 0 +OP4 E0063B 0 +OP4 E0063C 0 +OP4 E0063D 0 +OP4 E0063E 0 +OP4 E0063F 0 +OP4 E00640 0 +OP4 E00641 0 +OP4 E00642 0 +OP4 E00643 0 +OP4 E00644 0 +OP4 E00645 0 +OP4 E00646 0 +OP4 E00647 0 +OP4 E00648 0 +OP4 E00649 0 +OP4 E0064A 0 +OP4 E0064B 0 +OP4 E0064C 0 +OP4 E0064D 0 +OP4 E0064E 0 +OP4 E0064F 0 +OP4 E00650 0 +OP4 E00651 0 +OP4 E00652 0 +OP4 E00653 0 +OP4 E00654 0 +OP4 E00655 0 +OP4 E00656 0 +OP4 E00657 0 +OP4 E00658 0 +OP4 E00659 0 +OP4 E0065A 0 +OP4 E0065B 0 +OP4 E0065C 0 +OP4 E0065D 0 +OP4 E0065E 0 +OP4 E0065F 0 +OP4 E00660 0 +OP4 E00661 0 +OP4 E00662 0 +OP4 E00663 0 +OP4 E00664 0 +OP4 E00665 0 +OP4 E00666 0 +OP4 E00667 0 +OP4 E00668 0 +OP4 E00669 0 +OP4 E0066A 0 +OP4 E0066B 0 +OP4 E0066C 0 +OP4 E0066D 0 +OP4 E0066E 0 +OP4 E0066F 0 +OP4 E00670 0 +OP4 E00671 0 +OP4 E00672 0 +OP4 E00673 0 +OP4 E00674 0 +OP4 E00675 0 +OP4 E00676 0 +OP4 E00677 0 +OP4 E00678 0 +OP4 E00679 0 +OP4 E0067A 0 +OP4 E0067B 0 +OP4 E0067C 0 +OP4 E0067D 0 +OP4 E0067E 0 +OP4 E0067F 0 +OP4 E00680 0 +OP4 E00681 0 +OP4 E00682 0 +OP4 E00683 0 +OP4 E00684 0 +OP4 E00685 0 +OP4 E00686 0 +OP4 E00687 0 +OP4 E00688 0 +OP4 E00689 0 +OP4 E0068A 0 +OP4 E0068B 0 +OP4 E0068C 0 +OP4 E0068D 0 +OP4 E0068E 0 +OP4 E0068F 0 +OP4 E00690 0 +OP4 E00691 0 +OP4 E00692 0 +OP4 E00693 0 +OP4 E00694 0 +OP4 E00695 0 +OP4 E00696 0 +OP4 E00697 0 +OP4 E00698 0 +OP4 E00699 0 +OP4 E0069A 0 +OP4 E0069B 0 +OP4 E0069C 0 +OP4 E0069D 0 +OP4 E0069E 0 +OP4 E0069F 0 +OP4 E006A0 0 +OP4 E006A1 0 +OP4 E006A2 0 +OP4 E006A3 0 +OP4 E006A4 0 +OP4 E006A5 0 +OP4 E006A6 0 +OP4 E006A7 0 +OP4 E006A8 0 +OP4 E006A9 0 +OP4 E006AA 0 +OP4 E006AB 0 +OP4 E006AC 0 +OP4 E006AD 0 +OP4 E006AE 0 +OP4 E006AF 0 +OP4 E006B0 0 +OP4 E006B1 0 +OP4 E006B2 0 +OP4 E006B3 0 +OP4 E006B4 0 +OP4 E006B5 0 +OP4 E006B6 0 +OP4 E006B7 0 +OP4 E006B8 0 +OP4 E006B9 0 +OP4 E006BA 0 +OP4 E006BB 0 +OP4 E006BC 0 +OP4 E006BD 0 +OP4 E006BE 0 +OP4 E006BF 0 +OP4 E006C0 0 +OP4 E006C1 0 +OP4 E006C2 0 +OP4 E006C3 0 +OP4 E006C4 0 +OP4 E006C5 0 +OP4 E006C6 0 +OP4 E006C7 0 +OP4 E006C8 0 +OP4 E006C9 0 +OP4 E006CA 0 +OP4 E006CB 0 +OP4 E006CC 0 +OP4 E006CD 0 +OP4 E006CE 0 +OP4 E006CF 0 +OP4 E006D0 0 +OP4 E006D1 0 +OP4 E006D2 0 +OP4 E006D3 0 +OP4 E006D4 0 +OP4 E006D5 0 +OP4 E006D6 0 +OP4 E006D7 0 +OP4 E006D8 0 +OP4 E006D9 0 +OP4 E006DA 0 +OP4 E006DB 0 +OP4 E006DC 0 +OP4 E006DD 0 +OP4 E006DE 0 +OP4 E006DF 0 +OP4 E006E0 0 +OP4 E006E1 0 +OP4 E006E2 0 +OP4 E006E3 0 +OP4 E006E4 0 +OP4 E006E5 0 +OP4 E006E6 0 +OP4 E006E7 0 +OP4 E006E8 0 +OP4 E006E9 0 +OP4 E006EA 0 +OP4 E006EB 0 +OP4 E006EC 0 +OP4 E006ED 0 +OP4 E006EE 0 +OP4 E006EF 0 +OP4 E006F0 0 +OP4 E006F1 0 +OP4 E006F2 0 +OP4 E006F3 0 +OP4 E006F4 0 +OP4 E006F5 0 +OP4 E006F6 0 +OP4 E006F7 0 +OP4 E006F8 0 +OP4 E006F9 0 +OP4 E006FA 0 +OP4 E006FB 0 +OP4 E006FC 0 +OP4 E006FD 0 +OP4 E006FE 0 +OP4 E006FF 0 +OP4 E00700 0 +OP4 E00701 0 +OP4 E00702 0 +OP4 E00703 0 +OP4 E00704 0 +OP4 E00705 0 +OP4 E00706 0 +OP4 E00707 0 +OP4 E00708 0 +OP4 E00709 0 +OP4 E0070A 0 +OP4 E0070B 0 +OP4 E0070C 0 +OP4 E0070D 0 +OP4 E0070E 0 +OP4 E0070F 0 +OP4 E00710 0 +OP4 E00711 0 +OP4 E00712 0 +OP4 E00713 0 +OP4 E00714 0 +OP4 E00715 0 +OP4 E00716 0 +OP4 E00717 0 +OP4 E00718 0 +OP4 E00719 0 +OP4 E0071A 0 +OP4 E0071B 0 +OP4 E0071C 0 +OP4 E0071D 0 +OP4 E0071E 0 +OP4 E0071F 0 +OP4 E00720 0 +OP4 E00721 0 +OP4 E00722 0 +OP4 E00723 0 +OP4 E00724 0 +OP4 E00725 0 +OP4 E00726 0 +OP4 E00727 0 +OP4 E00728 0 +OP4 E00729 0 +OP4 E0072A 0 +OP4 E0072B 0 +OP4 E0072C 0 +OP4 E0072D 0 +OP4 E0072E 0 +OP4 E0072F 0 +OP4 E00730 0 +OP4 E00731 0 +OP4 E00732 0 +OP4 E00733 0 +OP4 E00734 0 +OP4 E00735 0 +OP4 E00736 0 +OP4 E00737 0 +OP4 E00738 0 +OP4 E00739 0 +OP4 E0073A 0 +OP4 E0073B 0 +OP4 E0073C 0 +OP4 E0073D 0 +OP4 E0073E 0 +OP4 E0073F 0 +OP4 E00740 0 +OP4 E00741 0 +OP4 E00742 0 +OP4 E00743 0 +OP4 E00744 0 +OP4 E00745 0 +OP4 E00746 0 +OP4 E00747 0 +OP4 E00748 0 +OP4 E00749 0 +OP4 E0074A 0 +OP4 E0074B 0 +OP4 E0074C 0 +OP4 E0074D 0 +OP4 E0074E 0 +OP4 E0074F 0 +OP4 E00750 0 +OP4 E00751 0 +OP4 E00752 0 +OP4 E00753 0 +OP4 E00754 0 +OP4 E00755 0 +OP4 E00756 0 +OP4 E00757 0 +OP4 E00758 0 +OP4 E00759 0 +OP4 E0075A 0 +OP4 E0075B 0 +OP4 E0075C 0 +OP4 E0075D 0 +OP4 E0075E 0 +OP4 E0075F 0 +OP4 E00760 0 +OP4 E00761 0 +OP4 E00762 0 +OP4 E00763 0 +OP4 E00764 0 +OP4 E00765 0 +OP4 E00766 0 +OP4 E00767 0 +OP4 E00768 0 +OP4 E00769 0 +OP4 E0076A 0 +OP4 E0076B 0 +OP4 E0076C 0 +OP4 E0076D 0 +OP4 E0076E 0 +OP4 E0076F 0 +OP4 E00770 0 +OP4 E00771 0 +OP4 E00772 0 +OP4 E00773 0 +OP4 E00774 0 +OP4 E00775 0 +OP4 E00776 0 +OP4 E00777 0 +OP4 E00778 0 +OP4 E00779 0 +OP4 E0077A 0 +OP4 E0077B 0 +OP4 E0077C 0 +OP4 E0077D 0 +OP4 E0077E 0 +OP4 E0077F 0 +OP4 E00780 0 +OP4 E00781 0 +OP4 E00782 0 +OP4 E00783 0 +OP4 E00784 0 +OP4 E00785 0 +OP4 E00786 0 +OP4 E00787 0 +OP4 E00788 0 +OP4 E00789 0 +OP4 E0078A 0 +OP4 E0078B 0 +OP4 E0078C 0 +OP4 E0078D 0 +OP4 E0078E 0 +OP4 E0078F 0 +OP4 E00790 0 +OP4 E00791 0 +OP4 E00792 0 +OP4 E00793 0 +OP4 E00794 0 +OP4 E00795 0 +OP4 E00796 0 +OP4 E00797 0 +OP4 E00798 0 +OP4 E00799 0 +OP4 E0079A 0 +OP4 E0079B 0 +OP4 E0079C 0 +OP4 E0079D 0 +OP4 E0079E 0 +OP4 E0079F 0 +OP4 E007A0 0 +OP4 E007A1 0 +OP4 E007A2 0 +OP4 E007A3 0 +OP4 E007A4 0 +OP4 E007A5 0 +OP4 E007A6 0 +OP4 E007A7 0 +OP4 E007A8 0 +OP4 E007A9 0 +OP4 E007AA 0 +OP4 E007AB 0 +OP4 E007AC 0 +OP4 E007AD 0 +OP4 E007AE 0 +OP4 E007AF 0 +OP4 E007B0 0 +OP4 E007B1 0 +OP4 E007B2 0 +OP4 E007B3 0 +OP4 E007B4 0 +OP4 E007B5 0 +OP4 E007B6 0 +OP4 E007B7 0 +OP4 E007B8 0 +OP4 E007B9 0 +OP4 E007BA 0 +OP4 E007BB 0 +OP4 E007BC 0 +OP4 E007BD 0 +OP4 E007BE 0 +OP4 E007BF 0 +OP4 E007C0 0 +OP4 E007C1 0 +OP4 E007C2 0 +OP4 E007C3 0 +OP4 E007C4 0 +OP4 E007C5 0 +OP4 E007C6 0 +OP4 E007C7 0 +OP4 E007C8 0 +OP4 E007C9 0 +OP4 E007CA 0 +OP4 E007CB 0 +OP4 E007CC 0 +OP4 E007CD 0 +OP4 E007CE 0 +OP4 E007CF 0 +OP4 E007D0 0 +OP4 E007D1 0 +OP4 E007D2 0 +OP4 E007D3 0 +OP4 E007D4 0 +OP4 E007D5 0 +OP4 E007D6 0 +OP4 E007D7 0 +OP4 E007D8 0 +OP4 E007D9 0 +OP4 E007DA 0 +OP4 E007DB 0 +OP4 E007DC 0 +OP4 E007DD 0 +OP4 E007DE 0 +OP4 E007DF 0 +OP4 E007E0 0 +OP4 E007E1 0 +OP4 E007E2 0 +OP4 E007E3 0 +OP4 E007E4 0 +OP4 E007E5 0 +OP4 E007E6 0 +OP4 E007E7 0 +OP4 E007E8 0 +OP4 E007E9 0 +OP4 E007EA 0 +OP4 E007EB 0 +OP4 E007EC 0 +OP4 E007ED 0 +OP4 E007EE 0 +OP4 E007EF 0 +OP4 E007F0 0 +OP4 E007F1 0 +OP4 E007F2 0 +OP4 E007F3 0 +OP4 E007F4 0 +OP4 E007F5 0 +OP4 E007F6 0 +OP4 E007F7 0 +OP4 E007F8 0 +OP4 E007F9 0 +OP4 E007FA 0 +OP4 E007FB 0 +OP4 E007FC 0 +OP4 E007FD 0 +OP4 E007FE 0 +OP4 E007FF 0 +OP4 E00800 0 +OP4 E00801 0 +OP4 E00802 0 +OP4 E00803 0 +OP4 E00804 0 +OP4 E00805 0 +OP4 E00806 0 +OP4 E00807 0 +OP4 E00808 0 +OP4 E00809 0 +OP4 E0080A 0 +OP4 E0080B 0 +OP4 E0080C 0 +OP4 E0080D 0 +OP4 E0080E 0 +OP4 E0080F 0 +OP4 E00810 0 +OP4 E00811 0 +OP4 E00812 0 +OP4 E00813 0 +OP4 E00814 0 +OP4 E00815 0 +OP4 E00816 0 +OP4 E00817 0 +OP4 E00818 0 +OP4 E00819 0 +OP4 E0081A 0 +OP4 E0081B 0 +OP4 E0081C 0 +OP4 E0081D 0 +OP4 E0081E 0 +OP4 E0081F 0 +OP4 E00820 0 +OP4 E00821 0 +OP4 E00822 0 +OP4 E00823 0 +OP4 E00824 0 +OP4 E00825 0 +OP4 E00826 0 +OP4 E00827 0 +OP4 E00828 0 +OP4 E00829 0 +OP4 E0082A 0 +OP4 E0082B 0 +OP4 E0082C 0 +OP4 E0082D 0 +OP4 E0082E 0 +OP4 E0082F 0 +OP4 E00830 0 +OP4 E00831 0 +OP4 E00832 0 +OP4 E00833 0 +OP4 E00834 0 +OP4 E00835 0 +OP4 E00836 0 +OP4 E00837 0 +OP4 E00838 0 +OP4 E00839 0 +OP4 E0083A 0 +OP4 E0083B 0 +OP4 E0083C 0 +OP4 E0083D 0 +OP4 E0083E 0 +OP4 E0083F 0 +OP4 E00840 0 +OP4 E00841 0 +OP4 E00842 0 +OP4 E00843 0 +OP4 E00844 0 +OP4 E00845 0 +OP4 E00846 0 +OP4 E00847 0 +OP4 E00848 0 +OP4 E00849 0 +OP4 E0084A 0 +OP4 E0084B 0 +OP4 E0084C 0 +OP4 E0084D 0 +OP4 E0084E 0 +OP4 E0084F 0 +OP4 E00850 0 +OP4 E00851 0 +OP4 E00852 0 +OP4 E00853 0 +OP4 E00854 0 +OP4 E00855 0 +OP4 E00856 0 +OP4 E00857 0 +OP4 E00858 0 +OP4 E00859 0 +OP4 E0085A 0 +OP4 E0085B 0 +OP4 E0085C 0 +OP4 E0085D 0 +OP4 E0085E 0 +OP4 E0085F 0 +OP4 E00860 0 +OP4 E00861 0 +OP4 E00862 0 +OP4 E00863 0 +OP4 E00864 0 +OP4 E00865 0 +OP4 E00866 0 +OP4 E00867 0 +OP4 E00868 0 +OP4 E00869 0 +OP4 E0086A 0 +OP4 E0086B 0 +OP4 E0086C 0 +OP4 E0086D 0 +OP4 E0086E 0 +OP4 E0086F 0 +OP4 E00870 0 +OP4 E00871 0 +OP4 E00872 0 +OP4 E00873 0 +OP4 E00874 0 +OP4 E00875 0 +OP4 E00876 0 +OP4 E00877 0 +OP4 E00878 0 +OP4 E00879 0 +OP4 E0087A 0 +OP4 E0087B 0 +OP4 E0087C 0 +OP4 E0087D 0 +OP4 E0087E 0 +OP4 E0087F 0 +OP4 E00880 0 +OP4 E00881 0 +OP4 E00882 0 +OP4 E00883 0 +OP4 E00884 0 +OP4 E00885 0 +OP4 E00886 0 +OP4 E00887 0 +OP4 E00888 0 +OP4 E00889 0 +OP4 E0088A 0 +OP4 E0088B 0 +OP4 E0088C 0 +OP4 E0088D 0 +OP4 E0088E 0 +OP4 E0088F 0 +OP4 E00890 0 +OP4 E00891 0 +OP4 E00892 0 +OP4 E00893 0 +OP4 E00894 0 +OP4 E00895 0 +OP4 E00896 0 +OP4 E00897 0 +OP4 E00898 0 +OP4 E00899 0 +OP4 E0089A 0 +OP4 E0089B 0 +OP4 E0089C 0 +OP4 E0089D 0 +OP4 E0089E 0 +OP4 E0089F 0 +OP4 E008A0 0 +OP4 E008A1 0 +OP4 E008A2 0 +OP4 E008A3 0 +OP4 E008A4 0 +OP4 E008A5 0 +OP4 E008A6 0 +OP4 E008A7 0 +OP4 E008A8 0 +OP4 E008A9 0 +OP4 E008AA 0 +OP4 E008AB 0 +OP4 E008AC 0 +OP4 E008AD 0 +OP4 E008AE 0 +OP4 E008AF 0 +OP4 E008B0 0 +OP4 E008B1 0 +OP4 E008B2 0 +OP4 E008B3 0 +OP4 E008B4 0 +OP4 E008B5 0 +OP4 E008B6 0 +OP4 E008B7 0 +OP4 E008B8 0 +OP4 E008B9 0 +OP4 E008BA 0 +OP4 E008BB 0 +OP4 E008BC 0 +OP4 E008BD 0 +OP4 E008BE 0 +OP4 E008BF 0 +OP4 E008C0 0 +OP4 E008C1 0 +OP4 E008C2 0 +OP4 E008C3 0 +OP4 E008C4 0 +OP4 E008C5 0 +OP4 E008C6 0 +OP4 E008C7 0 +OP4 E008C8 0 +OP4 E008C9 0 +OP4 E008CA 0 +OP4 E008CB 0 +OP4 E008CC 0 +OP4 E008CD 0 +OP4 E008CE 0 +OP4 E008CF 0 +OP4 E008D0 0 +OP4 E008D1 0 +OP4 E008D2 0 +OP4 E008D3 0 +OP4 E008D4 0 +OP4 E008D5 0 +OP4 E008D6 0 +OP4 E008D7 0 +OP4 E008D8 0 +OP4 E008D9 0 +OP4 E008DA 0 +OP4 E008DB 0 +OP4 E008DC 0 +OP4 E008DD 0 +OP4 E008DE 0 +OP4 E008DF 0 +OP4 E008E0 0 +OP4 E008E1 0 +OP4 E008E2 0 +OP4 E008E3 0 +OP4 E008E4 0 +OP4 E008E5 0 +OP4 E008E6 0 +OP4 E008E7 0 +OP4 E008E8 0 +OP4 E008E9 0 +OP4 E008EA 0 +OP4 E008EB 0 +OP4 E008EC 0 +OP4 E008ED 0 +OP4 E008EE 0 +OP4 E008EF 0 +OP4 E008F0 0 +OP4 E008F1 0 +OP4 E008F2 0 +OP4 E008F3 0 +OP4 E008F4 0 +OP4 E008F5 0 +OP4 E008F6 0 +OP4 E008F7 0 +OP4 E008F8 0 +OP4 E008F9 0 +OP4 E008FA 0 +OP4 E008FB 0 +OP4 E008FC 0 +OP4 E008FD 0 +OP4 E008FE 0 +OP4 E008FF 0 +OP4 E00900 0 +OP4 E00901 0 +OP4 E00902 0 +OP4 E00903 0 +OP4 E00904 0 +OP4 E00905 0 +OP4 E00906 0 +OP4 E00907 0 +OP4 E00908 0 +OP4 E00909 0 +OP4 E0090A 0 +OP4 E0090B 0 +OP4 E0090C 0 +OP4 E0090D 0 +OP4 E0090E 0 +OP4 E0090F 0 +OP4 E00910 0 +OP4 E00911 0 +OP4 E00912 0 +OP4 E00913 0 +OP4 E00914 0 +OP4 E00915 0 +OP4 E00916 0 +OP4 E00917 0 +OP4 E00918 0 +OP4 E00919 0 +OP4 E0091A 0 +OP4 E0091B 0 +OP4 E0091C 0 +OP4 E0091D 0 +OP4 E0091E 0 +OP4 E0091F 0 +OP4 E00920 0 +OP4 E00921 0 +OP4 E00922 0 +OP4 E00923 0 +OP4 E00924 0 +OP4 E00925 0 +OP4 E00926 0 +OP4 E00927 0 +OP4 E00928 0 +OP4 E00929 0 +OP4 E0092A 0 +OP4 E0092B 0 +OP4 E0092C 0 +OP4 E0092D 0 +OP4 E0092E 0 +OP4 E0092F 0 +OP4 E00930 0 +OP4 E00931 0 +OP4 E00932 0 +OP4 E00933 0 +OP4 E00934 0 +OP4 E00935 0 +OP4 E00936 0 +OP4 E00937 0 +OP4 E00938 0 +OP4 E00939 0 +OP4 E0093A 0 +OP4 E0093B 0 +OP4 E0093C 0 +OP4 E0093D 0 +OP4 E0093E 0 +OP4 E0093F 0 +OP4 E00940 0 +OP4 E00941 0 +OP4 E00942 0 +OP4 E00943 0 +OP4 E00944 0 +OP4 E00945 0 +OP4 E00946 0 +OP4 E00947 0 +OP4 E00948 0 +OP4 E00949 0 +OP4 E0094A 0 +OP4 E0094B 0 +OP4 E0094C 0 +OP4 E0094D 0 +OP4 E0094E 0 +OP4 E0094F 0 +OP4 E00950 0 +OP4 E00951 0 +OP4 E00952 0 +OP4 E00953 0 +OP4 E00954 0 +OP4 E00955 0 +OP4 E00956 0 +OP4 E00957 0 +OP4 E00958 0 +OP4 E00959 0 +OP4 E0095A 0 +OP4 E0095B 0 +OP4 E0095C 0 +OP4 E0095D 0 +OP4 E0095E 0 +OP4 E0095F 0 +OP4 E00960 0 +OP4 E00961 0 +OP4 E00962 0 +OP4 E00963 0 +OP4 E00964 0 +OP4 E00965 0 +OP4 E00966 0 +OP4 E00967 0 +OP4 E00968 0 +OP4 E00969 0 +OP4 E0096A 0 +OP4 E0096B 0 +OP4 E0096C 0 +OP4 E0096D 0 +OP4 E0096E 0 +OP4 E0096F 0 +OP4 E00970 0 +OP4 E00971 0 +OP4 E00972 0 +OP4 E00973 0 +OP4 E00974 0 +OP4 E00975 0 +OP4 E00976 0 +OP4 E00977 0 +OP4 E00978 0 +OP4 E00979 0 +OP4 E0097A 0 +OP4 E0097B 0 +OP4 E0097C 0 +OP4 E0097D 0 +OP4 E0097E 0 +OP4 E0097F 0 +OP4 E00980 0 +OP4 E00981 0 +OP4 E00982 0 +OP4 E00983 0 +OP4 E00984 0 +OP4 E00985 0 +OP4 E00986 0 +OP4 E00987 0 +OP4 E00988 0 +OP4 E00989 0 +OP4 E0098A 0 +OP4 E0098B 0 +OP4 E0098C 0 +OP4 E0098D 0 +OP4 E0098E 0 +OP4 E0098F 0 +OP4 E00990 0 +OP4 E00991 0 +OP4 E00992 0 +OP4 E00993 0 +OP4 E00994 0 +OP4 E00995 0 +OP4 E00996 0 +OP4 E00997 0 +OP4 E00998 0 +OP4 E00999 0 +OP4 E0099A 0 +OP4 E0099B 0 +OP4 E0099C 0 +OP4 E0099D 0 +OP4 E0099E 0 +OP4 E0099F 0 +OP4 E009A0 0 +OP4 E009A1 0 +OP4 E009A2 0 +OP4 E009A3 0 +OP4 E009A4 0 +OP4 E009A5 0 +OP4 E009A6 0 +OP4 E009A7 0 +OP4 E009A8 0 +OP4 E009A9 0 +OP4 E009AA 0 +OP4 E009AB 0 +OP4 E009AC 0 +OP4 E009AD 0 +OP4 E009AE 0 +OP4 E009AF 0 +OP4 E009B0 0 +OP4 E009B1 0 +OP4 E009B2 0 +OP4 E009B3 0 +OP4 E009B4 0 +OP4 E009B5 0 +OP4 E009B6 0 +OP4 E009B7 0 +OP4 E009B8 0 +OP4 E009B9 0 +OP4 E009BA 0 +OP4 E009BB 0 +OP4 E009BC 0 +OP4 E009BD 0 +OP4 E009BE 0 +OP4 E009BF 0 +OP4 E009C0 0 +OP4 E009C1 0 +OP4 E009C2 0 +OP4 E009C3 0 +OP4 E009C4 0 +OP4 E009C5 0 +OP4 E009C6 0 +OP4 E009C7 0 +OP4 E009C8 0 +OP4 E009C9 0 +OP4 E009CA 0 +OP4 E009CB 0 +OP4 E009CC 0 +OP4 E009CD 0 +OP4 E009CE 0 +OP4 E009CF 0 +OP4 E009D0 0 +OP4 E009D1 0 +OP4 E009D2 0 +OP4 E009D3 0 +OP4 E009D4 0 +OP4 E009D5 0 +OP4 E009D6 0 +OP4 E009D7 0 +OP4 E009D8 0 +OP4 E009D9 0 +OP4 E009DA 0 +OP4 E009DB 0 +OP4 E009DC 0 +OP4 E009DD 0 +OP4 E009DE 0 +OP4 E009DF 0 +OP4 E009E0 0 +OP4 E009E1 0 +OP4 E009E2 0 +OP4 E009E3 0 +OP4 E009E4 0 +OP4 E009E5 0 +OP4 E009E6 0 +OP4 E009E7 0 +OP4 E009E8 0 +OP4 E009E9 0 +OP4 E009EA 0 +OP4 E009EB 0 +OP4 E009EC 0 +OP4 E009ED 0 +OP4 E009EE 0 +OP4 E009EF 0 +OP4 E009F0 0 +OP4 E009F1 0 +OP4 E009F2 0 +OP4 E009F3 0 +OP4 E009F4 0 +OP4 E009F5 0 +OP4 E009F6 0 +OP4 E009F7 0 +OP4 E009F8 0 +OP4 E009F9 0 +OP4 E009FA 0 +OP4 E009FB 0 +OP4 E009FC 0 +OP4 E009FD 0 +OP4 E009FE 0 +OP4 E009FF 0 +OP4 E00A00 0 +OP4 E00A01 0 +OP4 E00A02 0 +OP4 E00A03 0 +OP4 E00A04 0 +OP4 E00A05 0 +OP4 E00A06 0 +OP4 E00A07 0 +OP4 E00A08 0 diff --git a/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum2_itrace_irisc6.cfg.ext b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum2_itrace_irisc6.cfg.ext new file mode 100644 index 000000000000..0cfac0813957 --- /dev/null +++ b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum2_itrace_irisc6.cfg.ext @@ -0,0 +1,2570 @@ +OP1 Spectrum2 +OP4 ITRACE0 0 +OP4 ITRACE1 0 +OP4 ITRACE2 0 +OP4 ITRACE3 0 +OP4 ITRACE4 0 +OP4 ITRACE5 0 +OP4 ITRACE6 1 +OP4 ITRACE7 0 +OP4 Main_PhyUC 0 +OP4 E00009 0 +OP4 E0000A 0 +OP4 E0000B 0 +OP4 E0000C 0 +OP4 E0000D 0 +OP4 E0000E 0 +OP4 E0000F 0 +OP4 E00010 0 +OP4 E00011 0 +OP4 E00012 0 +OP4 E00013 0 +OP4 E00014 0 +OP4 E00015 0 +OP4 E00016 0 +OP4 E00017 0 +OP4 E00018 0 +OP4 E00019 0 +OP4 E0001A 0 +OP4 E0001B 0 +OP4 E0001C 0 +OP4 E0001D 0 +OP4 E0001E 0 +OP4 E0001F 0 +OP4 E00020 0 +OP4 E00021 0 +OP4 E00022 0 +OP4 E00023 0 +OP4 E00024 0 +OP4 E00025 0 +OP4 E00026 0 +OP4 E00027 0 +OP4 E00028 0 +OP4 E00029 0 +OP4 E0002A 0 +OP4 E0002B 0 +OP4 E0002C 0 +OP4 E0002D 0 +OP4 E0002E 0 +OP4 E0002F 0 +OP4 E00030 0 +OP4 E00031 0 +OP4 E00032 0 +OP4 E00033 0 +OP4 E00034 0 +OP4 E00035 0 +OP4 E00036 0 +OP4 E00037 0 +OP4 E00038 0 +OP4 E00039 0 +OP4 E0003A 0 +OP4 E0003B 0 +OP4 E0003C 0 +OP4 E0003D 0 +OP4 E0003E 0 +OP4 E0003F 0 +OP4 E00040 0 +OP4 E00041 0 +OP4 E00042 0 +OP4 E00043 0 +OP4 E00044 0 +OP4 E00045 0 +OP4 E00046 0 +OP4 E00047 0 +OP4 E00048 0 +OP4 E00049 0 +OP4 E0004A 0 +OP4 E0004B 0 +OP4 E0004C 0 +OP4 E0004D 0 +OP4 E0004E 0 +OP4 E0004F 0 +OP4 E00050 0 +OP4 E00051 0 +OP4 E00052 0 +OP4 E00053 0 +OP4 E00054 0 +OP4 E00055 0 +OP4 E00056 0 +OP4 E00057 0 +OP4 E00058 0 +OP4 E00059 0 +OP4 E0005A 0 +OP4 E0005B 0 +OP4 E0005C 0 +OP4 E0005D 0 +OP4 E0005E 0 +OP4 E0005F 0 +OP4 E00060 0 +OP4 E00061 0 +OP4 E00062 0 +OP4 E00063 0 +OP4 E00064 0 +OP4 E00065 0 +OP4 E00066 0 +OP4 E00067 0 +OP4 E00068 0 +OP4 E00069 0 +OP4 E0006A 0 +OP4 E0006B 0 +OP4 E0006C 0 +OP4 E0006D 0 +OP4 E0006E 0 +OP4 E0006F 0 +OP4 E00070 0 +OP4 E00071 0 +OP4 E00072 0 +OP4 E00073 0 +OP4 E00074 0 +OP4 E00075 0 +OP4 E00076 0 +OP4 E00077 0 +OP4 E00078 0 +OP4 E00079 0 +OP4 E0007A 0 +OP4 E0007B 0 +OP4 E0007C 0 +OP4 E0007D 0 +OP4 E0007E 0 +OP4 E0007F 0 +OP4 E00080 0 +OP4 E00081 0 +OP4 E00082 0 +OP4 E00083 0 +OP4 E00084 0 +OP4 E00085 0 +OP4 E00086 0 +OP4 E00087 0 +OP4 E00088 0 +OP4 E00089 0 +OP4 E0008A 0 +OP4 E0008B 0 +OP4 E0008C 0 +OP4 E0008D 0 +OP4 E0008E 0 +OP4 E0008F 0 +OP4 E00090 0 +OP4 E00091 0 +OP4 E00092 0 +OP4 E00093 0 +OP4 E00094 0 +OP4 E00095 0 +OP4 E00096 0 +OP4 E00097 0 +OP4 E00098 0 +OP4 E00099 0 +OP4 E0009A 0 +OP4 E0009B 0 +OP4 E0009C 0 +OP4 E0009D 0 +OP4 E0009E 0 +OP4 E0009F 0 +OP4 E000A0 0 +OP4 E000A1 0 +OP4 E000A2 0 +OP4 E000A3 0 +OP4 E000A4 0 +OP4 E000A5 0 +OP4 E000A6 0 +OP4 E000A7 0 +OP4 E000A8 0 +OP4 E000A9 0 +OP4 E000AA 0 +OP4 E000AB 0 +OP4 E000AC 0 +OP4 E000AD 0 +OP4 E000AE 0 +OP4 E000AF 0 +OP4 E000B0 0 +OP4 E000B1 0 +OP4 E000B2 0 +OP4 E000B3 0 +OP4 E000B4 0 +OP4 E000B5 0 +OP4 E000B6 0 +OP4 E000B7 0 +OP4 E000B8 0 +OP4 E000B9 0 +OP4 E000BA 0 +OP4 E000BB 0 +OP4 E000BC 0 +OP4 E000BD 0 +OP4 E000BE 0 +OP4 E000BF 0 +OP4 E000C0 0 +OP4 E000C1 0 +OP4 E000C2 0 +OP4 E000C3 0 +OP4 E000C4 0 +OP4 E000C5 0 +OP4 E000C6 0 +OP4 E000C7 0 +OP4 E000C8 0 +OP4 E000C9 0 +OP4 E000CA 0 +OP4 E000CB 0 +OP4 E000CC 0 +OP4 E000CD 0 +OP4 E000CE 0 +OP4 E000CF 0 +OP4 E000D0 0 +OP4 E000D1 0 +OP4 E000D2 0 +OP4 E000D3 0 +OP4 E000D4 0 +OP4 E000D5 0 +OP4 E000D6 0 +OP4 E000D7 0 +OP4 E000D8 0 +OP4 E000D9 0 +OP4 E000DA 0 +OP4 E000DB 0 +OP4 E000DC 0 +OP4 E000DD 0 +OP4 E000DE 0 +OP4 E000DF 0 +OP4 E000E0 0 +OP4 E000E1 0 +OP4 E000E2 0 +OP4 E000E3 0 +OP4 E000E4 0 +OP4 E000E5 0 +OP4 E000E6 0 +OP4 E000E7 0 +OP4 E000E8 0 +OP4 E000E9 0 +OP4 E000EA 0 +OP4 E000EB 0 +OP4 E000EC 0 +OP4 E000ED 0 +OP4 E000EE 0 +OP4 E000EF 0 +OP4 E000F0 0 +OP4 E000F1 0 +OP4 E000F2 0 +OP4 E000F3 0 +OP4 E000F4 0 +OP4 E000F5 0 +OP4 E000F6 0 +OP4 E000F7 0 +OP4 E000F8 0 +OP4 E000F9 0 +OP4 E000FA 0 +OP4 E000FB 0 +OP4 E000FC 0 +OP4 E000FD 0 +OP4 E000FE 0 +OP4 E000FF 0 +OP4 E00100 0 +OP4 E00101 0 +OP4 E00102 0 +OP4 E00103 0 +OP4 E00104 0 +OP4 E00105 0 +OP4 E00106 0 +OP4 E00107 0 +OP4 E00108 0 +OP4 E00109 0 +OP4 E0010A 0 +OP4 E0010B 0 +OP4 E0010C 0 +OP4 E0010D 0 +OP4 E0010E 0 +OP4 E0010F 0 +OP4 E00110 0 +OP4 E00111 0 +OP4 E00112 0 +OP4 E00113 0 +OP4 E00114 0 +OP4 E00115 0 +OP4 E00116 0 +OP4 E00117 0 +OP4 E00118 0 +OP4 E00119 0 +OP4 E0011A 0 +OP4 E0011B 0 +OP4 E0011C 0 +OP4 E0011D 0 +OP4 E0011E 0 +OP4 E0011F 0 +OP4 E00120 0 +OP4 E00121 0 +OP4 E00122 0 +OP4 E00123 0 +OP4 E00124 0 +OP4 E00125 0 +OP4 E00126 0 +OP4 E00127 0 +OP4 E00128 0 +OP4 E00129 0 +OP4 E0012A 0 +OP4 E0012B 0 +OP4 E0012C 0 +OP4 E0012D 0 +OP4 E0012E 0 +OP4 E0012F 0 +OP4 E00130 0 +OP4 E00131 0 +OP4 E00132 0 +OP4 E00133 0 +OP4 E00134 0 +OP4 E00135 0 +OP4 E00136 0 +OP4 E00137 0 +OP4 E00138 0 +OP4 E00139 0 +OP4 E0013A 0 +OP4 E0013B 0 +OP4 E0013C 0 +OP4 E0013D 0 +OP4 E0013E 0 +OP4 E0013F 0 +OP4 E00140 0 +OP4 E00141 0 +OP4 E00142 0 +OP4 E00143 0 +OP4 E00144 0 +OP4 E00145 0 +OP4 E00146 0 +OP4 E00147 0 +OP4 E00148 0 +OP4 E00149 0 +OP4 E0014A 0 +OP4 E0014B 0 +OP4 E0014C 0 +OP4 E0014D 0 +OP4 E0014E 0 +OP4 E0014F 0 +OP4 E00150 0 +OP4 E00151 0 +OP4 E00152 0 +OP4 E00153 0 +OP4 E00154 0 +OP4 E00155 0 +OP4 E00156 0 +OP4 E00157 0 +OP4 E00158 0 +OP4 E00159 0 +OP4 E0015A 0 +OP4 E0015B 0 +OP4 E0015C 0 +OP4 E0015D 0 +OP4 E0015E 0 +OP4 E0015F 0 +OP4 E00160 0 +OP4 E00161 0 +OP4 E00162 0 +OP4 E00163 0 +OP4 E00164 0 +OP4 E00165 0 +OP4 E00166 0 +OP4 E00167 0 +OP4 E00168 0 +OP4 E00169 0 +OP4 E0016A 0 +OP4 E0016B 0 +OP4 E0016C 0 +OP4 E0016D 0 +OP4 E0016E 0 +OP4 E0016F 0 +OP4 E00170 0 +OP4 E00171 0 +OP4 E00172 0 +OP4 E00173 0 +OP4 E00174 0 +OP4 E00175 0 +OP4 E00176 0 +OP4 E00177 0 +OP4 E00178 0 +OP4 E00179 0 +OP4 E0017A 0 +OP4 E0017B 0 +OP4 E0017C 0 +OP4 E0017D 0 +OP4 E0017E 0 +OP4 E0017F 0 +OP4 E00180 0 +OP4 E00181 0 +OP4 E00182 0 +OP4 E00183 0 +OP4 E00184 0 +OP4 E00185 0 +OP4 E00186 0 +OP4 E00187 0 +OP4 E00188 0 +OP4 E00189 0 +OP4 E0018A 0 +OP4 E0018B 0 +OP4 E0018C 0 +OP4 E0018D 0 +OP4 E0018E 0 +OP4 E0018F 0 +OP4 E00190 0 +OP4 E00191 0 +OP4 E00192 0 +OP4 E00193 0 +OP4 E00194 0 +OP4 E00195 0 +OP4 E00196 0 +OP4 E00197 0 +OP4 E00198 0 +OP4 E00199 0 +OP4 E0019A 0 +OP4 E0019B 0 +OP4 E0019C 0 +OP4 E0019D 0 +OP4 E0019E 0 +OP4 E0019F 0 +OP4 E001A0 0 +OP4 E001A1 0 +OP4 E001A2 0 +OP4 E001A3 0 +OP4 E001A4 0 +OP4 E001A5 0 +OP4 E001A6 0 +OP4 E001A7 0 +OP4 E001A8 0 +OP4 E001A9 0 +OP4 E001AA 0 +OP4 E001AB 0 +OP4 E001AC 0 +OP4 E001AD 0 +OP4 E001AE 0 +OP4 E001AF 0 +OP4 E001B0 0 +OP4 E001B1 0 +OP4 E001B2 0 +OP4 E001B3 0 +OP4 E001B4 0 +OP4 E001B5 0 +OP4 E001B6 0 +OP4 E001B7 0 +OP4 E001B8 0 +OP4 E001B9 0 +OP4 E001BA 0 +OP4 E001BB 0 +OP4 E001BC 0 +OP4 E001BD 0 +OP4 E001BE 0 +OP4 E001BF 0 +OP4 E001C0 0 +OP4 E001C1 0 +OP4 E001C2 0 +OP4 E001C3 0 +OP4 E001C4 0 +OP4 E001C5 0 +OP4 E001C6 0 +OP4 E001C7 0 +OP4 E001C8 0 +OP4 E001C9 0 +OP4 E001CA 0 +OP4 E001CB 0 +OP4 E001CC 0 +OP4 E001CD 0 +OP4 E001CE 0 +OP4 E001CF 0 +OP4 E001D0 0 +OP4 E001D1 0 +OP4 E001D2 0 +OP4 E001D3 0 +OP4 E001D4 0 +OP4 E001D5 0 +OP4 E001D6 0 +OP4 E001D7 0 +OP4 E001D8 0 +OP4 E001D9 0 +OP4 E001DA 0 +OP4 E001DB 0 +OP4 E001DC 0 +OP4 E001DD 0 +OP4 E001DE 0 +OP4 E001DF 0 +OP4 E001E0 0 +OP4 E001E1 0 +OP4 E001E2 0 +OP4 E001E3 0 +OP4 E001E4 0 +OP4 E001E5 0 +OP4 E001E6 0 +OP4 E001E7 0 +OP4 E001E8 0 +OP4 E001E9 0 +OP4 E001EA 0 +OP4 E001EB 0 +OP4 E001EC 0 +OP4 E001ED 0 +OP4 E001EE 0 +OP4 E001EF 0 +OP4 E001F0 0 +OP4 E001F1 0 +OP4 E001F2 0 +OP4 E001F3 0 +OP4 E001F4 0 +OP4 E001F5 0 +OP4 E001F6 0 +OP4 E001F7 0 +OP4 E001F8 0 +OP4 E001F9 0 +OP4 E001FA 0 +OP4 E001FB 0 +OP4 E001FC 0 +OP4 E001FD 0 +OP4 E001FE 0 +OP4 E001FF 0 +OP4 E00200 0 +OP4 E00201 0 +OP4 E00202 0 +OP4 E00203 0 +OP4 E00204 0 +OP4 E00205 0 +OP4 E00206 0 +OP4 E00207 0 +OP4 E00208 0 +OP4 E00209 0 +OP4 E0020A 0 +OP4 E0020B 0 +OP4 E0020C 0 +OP4 E0020D 0 +OP4 E0020E 0 +OP4 E0020F 0 +OP4 E00210 0 +OP4 E00211 0 +OP4 E00212 0 +OP4 E00213 0 +OP4 E00214 0 +OP4 E00215 0 +OP4 E00216 0 +OP4 E00217 0 +OP4 E00218 0 +OP4 E00219 0 +OP4 E0021A 0 +OP4 E0021B 0 +OP4 E0021C 0 +OP4 E0021D 0 +OP4 E0021E 0 +OP4 E0021F 0 +OP4 E00220 0 +OP4 E00221 0 +OP4 E00222 0 +OP4 E00223 0 +OP4 E00224 0 +OP4 E00225 0 +OP4 E00226 0 +OP4 E00227 0 +OP4 E00228 0 +OP4 E00229 0 +OP4 E0022A 0 +OP4 E0022B 0 +OP4 E0022C 0 +OP4 E0022D 0 +OP4 E0022E 0 +OP4 E0022F 0 +OP4 E00230 0 +OP4 E00231 0 +OP4 E00232 0 +OP4 E00233 0 +OP4 E00234 0 +OP4 E00235 0 +OP4 E00236 0 +OP4 E00237 0 +OP4 E00238 0 +OP4 E00239 0 +OP4 E0023A 0 +OP4 E0023B 0 +OP4 E0023C 0 +OP4 E0023D 0 +OP4 E0023E 0 +OP4 E0023F 0 +OP4 E00240 0 +OP4 E00241 0 +OP4 E00242 0 +OP4 E00243 0 +OP4 E00244 0 +OP4 E00245 0 +OP4 E00246 0 +OP4 E00247 0 +OP4 E00248 0 +OP4 E00249 0 +OP4 E0024A 0 +OP4 E0024B 0 +OP4 E0024C 0 +OP4 E0024D 0 +OP4 E0024E 0 +OP4 E0024F 0 +OP4 E00250 0 +OP4 E00251 0 +OP4 E00252 0 +OP4 E00253 0 +OP4 E00254 0 +OP4 E00255 0 +OP4 E00256 0 +OP4 E00257 0 +OP4 E00258 0 +OP4 E00259 0 +OP4 E0025A 0 +OP4 E0025B 0 +OP4 E0025C 0 +OP4 E0025D 0 +OP4 E0025E 0 +OP4 E0025F 0 +OP4 E00260 0 +OP4 E00261 0 +OP4 E00262 0 +OP4 E00263 0 +OP4 E00264 0 +OP4 E00265 0 +OP4 E00266 0 +OP4 E00267 0 +OP4 E00268 0 +OP4 E00269 0 +OP4 E0026A 0 +OP4 E0026B 0 +OP4 E0026C 0 +OP4 E0026D 0 +OP4 E0026E 0 +OP4 E0026F 0 +OP4 E00270 0 +OP4 E00271 0 +OP4 E00272 0 +OP4 E00273 0 +OP4 E00274 0 +OP4 E00275 0 +OP4 E00276 0 +OP4 E00277 0 +OP4 E00278 0 +OP4 E00279 0 +OP4 E0027A 0 +OP4 E0027B 0 +OP4 E0027C 0 +OP4 E0027D 0 +OP4 E0027E 0 +OP4 E0027F 0 +OP4 E00280 0 +OP4 E00281 0 +OP4 E00282 0 +OP4 E00283 0 +OP4 E00284 0 +OP4 E00285 0 +OP4 E00286 0 +OP4 E00287 0 +OP4 E00288 0 +OP4 E00289 0 +OP4 E0028A 0 +OP4 E0028B 0 +OP4 E0028C 0 +OP4 E0028D 0 +OP4 E0028E 0 +OP4 E0028F 0 +OP4 E00290 0 +OP4 E00291 0 +OP4 E00292 0 +OP4 E00293 0 +OP4 E00294 0 +OP4 E00295 0 +OP4 E00296 0 +OP4 E00297 0 +OP4 E00298 0 +OP4 E00299 0 +OP4 E0029A 0 +OP4 E0029B 0 +OP4 E0029C 0 +OP4 E0029D 0 +OP4 E0029E 0 +OP4 E0029F 0 +OP4 E002A0 0 +OP4 E002A1 0 +OP4 E002A2 0 +OP4 E002A3 0 +OP4 E002A4 0 +OP4 E002A5 0 +OP4 E002A6 0 +OP4 E002A7 0 +OP4 E002A8 0 +OP4 E002A9 0 +OP4 E002AA 0 +OP4 E002AB 0 +OP4 E002AC 0 +OP4 E002AD 0 +OP4 E002AE 0 +OP4 E002AF 0 +OP4 E002B0 0 +OP4 E002B1 0 +OP4 E002B2 0 +OP4 E002B3 0 +OP4 E002B4 0 +OP4 E002B5 0 +OP4 E002B6 0 +OP4 E002B7 0 +OP4 E002B8 0 +OP4 E002B9 0 +OP4 E002BA 0 +OP4 E002BB 0 +OP4 E002BC 0 +OP4 E002BD 0 +OP4 E002BE 0 +OP4 E002BF 0 +OP4 E002C0 0 +OP4 E002C1 0 +OP4 E002C2 0 +OP4 E002C3 0 +OP4 E002C4 0 +OP4 E002C5 0 +OP4 E002C6 0 +OP4 E002C7 0 +OP4 E002C8 0 +OP4 E002C9 0 +OP4 E002CA 0 +OP4 E002CB 0 +OP4 E002CC 0 +OP4 E002CD 0 +OP4 E002CE 0 +OP4 E002CF 0 +OP4 E002D0 0 +OP4 E002D1 0 +OP4 E002D2 0 +OP4 E002D3 0 +OP4 E002D4 0 +OP4 E002D5 0 +OP4 E002D6 0 +OP4 E002D7 0 +OP4 E002D8 0 +OP4 E002D9 0 +OP4 E002DA 0 +OP4 E002DB 0 +OP4 E002DC 0 +OP4 E002DD 0 +OP4 E002DE 0 +OP4 E002DF 0 +OP4 E002E0 0 +OP4 E002E1 0 +OP4 E002E2 0 +OP4 E002E3 0 +OP4 E002E4 0 +OP4 E002E5 0 +OP4 E002E6 0 +OP4 E002E7 0 +OP4 E002E8 0 +OP4 E002E9 0 +OP4 E002EA 0 +OP4 E002EB 0 +OP4 E002EC 0 +OP4 E002ED 0 +OP4 E002EE 0 +OP4 E002EF 0 +OP4 E002F0 0 +OP4 E002F1 0 +OP4 E002F2 0 +OP4 E002F3 0 +OP4 E002F4 0 +OP4 E002F5 0 +OP4 E002F6 0 +OP4 E002F7 0 +OP4 E002F8 0 +OP4 E002F9 0 +OP4 E002FA 0 +OP4 E002FB 0 +OP4 E002FC 0 +OP4 E002FD 0 +OP4 E002FE 0 +OP4 E002FF 0 +OP4 E00300 0 +OP4 E00301 0 +OP4 E00302 0 +OP4 E00303 0 +OP4 E00304 0 +OP4 E00305 0 +OP4 E00306 0 +OP4 E00307 0 +OP4 E00308 0 +OP4 E00309 0 +OP4 E0030A 0 +OP4 E0030B 0 +OP4 E0030C 0 +OP4 E0030D 0 +OP4 E0030E 0 +OP4 E0030F 0 +OP4 E00310 0 +OP4 E00311 0 +OP4 E00312 0 +OP4 E00313 0 +OP4 E00314 0 +OP4 E00315 0 +OP4 E00316 0 +OP4 E00317 0 +OP4 E00318 0 +OP4 E00319 0 +OP4 E0031A 0 +OP4 E0031B 0 +OP4 E0031C 0 +OP4 E0031D 0 +OP4 E0031E 0 +OP4 E0031F 0 +OP4 E00320 0 +OP4 E00321 0 +OP4 E00322 0 +OP4 E00323 0 +OP4 E00324 0 +OP4 E00325 0 +OP4 E00326 0 +OP4 E00327 0 +OP4 E00328 0 +OP4 E00329 0 +OP4 E0032A 0 +OP4 E0032B 0 +OP4 E0032C 0 +OP4 E0032D 0 +OP4 E0032E 0 +OP4 E0032F 0 +OP4 E00330 0 +OP4 E00331 0 +OP4 E00332 0 +OP4 E00333 0 +OP4 E00334 0 +OP4 E00335 0 +OP4 E00336 0 +OP4 E00337 0 +OP4 E00338 0 +OP4 E00339 0 +OP4 E0033A 0 +OP4 E0033B 0 +OP4 E0033C 0 +OP4 E0033D 0 +OP4 E0033E 0 +OP4 E0033F 0 +OP4 E00340 0 +OP4 E00341 0 +OP4 E00342 0 +OP4 E00343 0 +OP4 E00344 0 +OP4 E00345 0 +OP4 E00346 0 +OP4 E00347 0 +OP4 E00348 0 +OP4 E00349 0 +OP4 E0034A 0 +OP4 E0034B 0 +OP4 E0034C 0 +OP4 E0034D 0 +OP4 E0034E 0 +OP4 E0034F 0 +OP4 E00350 0 +OP4 E00351 0 +OP4 E00352 0 +OP4 E00353 0 +OP4 E00354 0 +OP4 E00355 0 +OP4 E00356 0 +OP4 E00357 0 +OP4 E00358 0 +OP4 E00359 0 +OP4 E0035A 0 +OP4 E0035B 0 +OP4 E0035C 0 +OP4 E0035D 0 +OP4 E0035E 0 +OP4 E0035F 0 +OP4 E00360 0 +OP4 E00361 0 +OP4 E00362 0 +OP4 E00363 0 +OP4 E00364 0 +OP4 E00365 0 +OP4 E00366 0 +OP4 E00367 0 +OP4 E00368 0 +OP4 E00369 0 +OP4 E0036A 0 +OP4 E0036B 0 +OP4 E0036C 0 +OP4 E0036D 0 +OP4 E0036E 0 +OP4 E0036F 0 +OP4 E00370 0 +OP4 E00371 0 +OP4 E00372 0 +OP4 E00373 0 +OP4 E00374 0 +OP4 E00375 0 +OP4 E00376 0 +OP4 E00377 0 +OP4 E00378 0 +OP4 E00379 0 +OP4 E0037A 0 +OP4 E0037B 0 +OP4 E0037C 0 +OP4 E0037D 0 +OP4 E0037E 0 +OP4 E0037F 0 +OP4 E00380 0 +OP4 E00381 0 +OP4 E00382 0 +OP4 E00383 0 +OP4 E00384 0 +OP4 E00385 0 +OP4 E00386 0 +OP4 E00387 0 +OP4 E00388 0 +OP4 E00389 0 +OP4 E0038A 0 +OP4 E0038B 0 +OP4 E0038C 0 +OP4 E0038D 0 +OP4 E0038E 0 +OP4 E0038F 0 +OP4 E00390 0 +OP4 E00391 0 +OP4 E00392 0 +OP4 E00393 0 +OP4 E00394 0 +OP4 E00395 0 +OP4 E00396 0 +OP4 E00397 0 +OP4 E00398 0 +OP4 E00399 0 +OP4 E0039A 0 +OP4 E0039B 0 +OP4 E0039C 0 +OP4 E0039D 0 +OP4 E0039E 0 +OP4 E0039F 0 +OP4 E003A0 0 +OP4 E003A1 0 +OP4 E003A2 0 +OP4 E003A3 0 +OP4 E003A4 0 +OP4 E003A5 0 +OP4 E003A6 0 +OP4 E003A7 0 +OP4 E003A8 0 +OP4 E003A9 0 +OP4 E003AA 0 +OP4 E003AB 0 +OP4 E003AC 0 +OP4 E003AD 0 +OP4 E003AE 0 +OP4 E003AF 0 +OP4 E003B0 0 +OP4 E003B1 0 +OP4 E003B2 0 +OP4 E003B3 0 +OP4 E003B4 0 +OP4 E003B5 0 +OP4 E003B6 0 +OP4 E003B7 0 +OP4 E003B8 0 +OP4 E003B9 0 +OP4 E003BA 0 +OP4 E003BB 0 +OP4 E003BC 0 +OP4 E003BD 0 +OP4 E003BE 0 +OP4 E003BF 0 +OP4 E003C0 0 +OP4 E003C1 0 +OP4 E003C2 0 +OP4 E003C3 0 +OP4 E003C4 0 +OP4 E003C5 0 +OP4 E003C6 0 +OP4 E003C7 0 +OP4 E003C8 0 +OP4 E003C9 0 +OP4 E003CA 0 +OP4 E003CB 0 +OP4 E003CC 0 +OP4 E003CD 0 +OP4 E003CE 0 +OP4 E003CF 0 +OP4 E003D0 0 +OP4 E003D1 0 +OP4 E003D2 0 +OP4 E003D3 0 +OP4 E003D4 0 +OP4 E003D5 0 +OP4 E003D6 0 +OP4 E003D7 0 +OP4 E003D8 0 +OP4 E003D9 0 +OP4 E003DA 0 +OP4 E003DB 0 +OP4 E003DC 0 +OP4 E003DD 0 +OP4 E003DE 0 +OP4 E003DF 0 +OP4 E003E0 0 +OP4 E003E1 0 +OP4 E003E2 0 +OP4 E003E3 0 +OP4 E003E4 0 +OP4 E003E5 0 +OP4 E003E6 0 +OP4 E003E7 0 +OP4 E003E8 0 +OP4 E003E9 0 +OP4 E003EA 0 +OP4 E003EB 0 +OP4 E003EC 0 +OP4 E003ED 0 +OP4 E003EE 0 +OP4 E003EF 0 +OP4 E003F0 0 +OP4 E003F1 0 +OP4 E003F2 0 +OP4 E003F3 0 +OP4 E003F4 0 +OP4 E003F5 0 +OP4 E003F6 0 +OP4 E003F7 0 +OP4 E003F8 0 +OP4 E003F9 0 +OP4 E003FA 0 +OP4 E003FB 0 +OP4 E003FC 0 +OP4 E003FD 0 +OP4 E003FE 0 +OP4 E003FF 0 +OP4 E00400 0 +OP4 E00401 0 +OP4 E00402 0 +OP4 E00403 0 +OP4 E00404 0 +OP4 E00405 0 +OP4 E00406 0 +OP4 E00407 0 +OP4 E00408 0 +OP4 E00409 0 +OP4 E0040A 0 +OP4 E0040B 0 +OP4 E0040C 0 +OP4 E0040D 0 +OP4 E0040E 0 +OP4 E0040F 0 +OP4 E00410 0 +OP4 E00411 0 +OP4 E00412 0 +OP4 E00413 0 +OP4 E00414 0 +OP4 E00415 0 +OP4 E00416 0 +OP4 E00417 0 +OP4 E00418 0 +OP4 E00419 0 +OP4 E0041A 0 +OP4 E0041B 0 +OP4 E0041C 0 +OP4 E0041D 0 +OP4 E0041E 0 +OP4 E0041F 0 +OP4 E00420 0 +OP4 E00421 0 +OP4 E00422 0 +OP4 E00423 0 +OP4 E00424 0 +OP4 E00425 0 +OP4 E00426 0 +OP4 E00427 0 +OP4 E00428 0 +OP4 E00429 0 +OP4 E0042A 0 +OP4 E0042B 0 +OP4 E0042C 0 +OP4 E0042D 0 +OP4 E0042E 0 +OP4 E0042F 0 +OP4 E00430 0 +OP4 E00431 0 +OP4 E00432 0 +OP4 E00433 0 +OP4 E00434 0 +OP4 E00435 0 +OP4 E00436 0 +OP4 E00437 0 +OP4 E00438 0 +OP4 E00439 0 +OP4 E0043A 0 +OP4 E0043B 0 +OP4 E0043C 0 +OP4 E0043D 0 +OP4 E0043E 0 +OP4 E0043F 0 +OP4 E00440 0 +OP4 E00441 0 +OP4 E00442 0 +OP4 E00443 0 +OP4 E00444 0 +OP4 E00445 0 +OP4 E00446 0 +OP4 E00447 0 +OP4 E00448 0 +OP4 E00449 0 +OP4 E0044A 0 +OP4 E0044B 0 +OP4 E0044C 0 +OP4 E0044D 0 +OP4 E0044E 0 +OP4 E0044F 0 +OP4 E00450 0 +OP4 E00451 0 +OP4 E00452 0 +OP4 E00453 0 +OP4 E00454 0 +OP4 E00455 0 +OP4 E00456 0 +OP4 E00457 0 +OP4 E00458 0 +OP4 E00459 0 +OP4 E0045A 0 +OP4 E0045B 0 +OP4 E0045C 0 +OP4 E0045D 0 +OP4 E0045E 0 +OP4 E0045F 0 +OP4 E00460 0 +OP4 E00461 0 +OP4 E00462 0 +OP4 E00463 0 +OP4 E00464 0 +OP4 E00465 0 +OP4 E00466 0 +OP4 E00467 0 +OP4 E00468 0 +OP4 E00469 0 +OP4 E0046A 0 +OP4 E0046B 0 +OP4 E0046C 0 +OP4 E0046D 0 +OP4 E0046E 0 +OP4 E0046F 0 +OP4 E00470 0 +OP4 E00471 0 +OP4 E00472 0 +OP4 E00473 0 +OP4 E00474 0 +OP4 E00475 0 +OP4 E00476 0 +OP4 E00477 0 +OP4 E00478 0 +OP4 E00479 0 +OP4 E0047A 0 +OP4 E0047B 0 +OP4 E0047C 0 +OP4 E0047D 0 +OP4 E0047E 0 +OP4 E0047F 0 +OP4 E00480 0 +OP4 E00481 0 +OP4 E00482 0 +OP4 E00483 0 +OP4 E00484 0 +OP4 E00485 0 +OP4 E00486 0 +OP4 E00487 0 +OP4 E00488 0 +OP4 E00489 0 +OP4 E0048A 0 +OP4 E0048B 0 +OP4 E0048C 0 +OP4 E0048D 0 +OP4 E0048E 0 +OP4 E0048F 0 +OP4 E00490 0 +OP4 E00491 0 +OP4 E00492 0 +OP4 E00493 0 +OP4 E00494 0 +OP4 E00495 0 +OP4 E00496 0 +OP4 E00497 0 +OP4 E00498 0 +OP4 E00499 0 +OP4 E0049A 0 +OP4 E0049B 0 +OP4 E0049C 0 +OP4 E0049D 0 +OP4 E0049E 0 +OP4 E0049F 0 +OP4 E004A0 0 +OP4 E004A1 0 +OP4 E004A2 0 +OP4 E004A3 0 +OP4 E004A4 0 +OP4 E004A5 0 +OP4 E004A6 0 +OP4 E004A7 0 +OP4 E004A8 0 +OP4 E004A9 0 +OP4 E004AA 0 +OP4 E004AB 0 +OP4 E004AC 0 +OP4 E004AD 0 +OP4 E004AE 0 +OP4 E004AF 0 +OP4 E004B0 0 +OP4 E004B1 0 +OP4 E004B2 0 +OP4 E004B3 0 +OP4 E004B4 0 +OP4 E004B5 0 +OP4 E004B6 0 +OP4 E004B7 0 +OP4 E004B8 0 +OP4 E004B9 0 +OP4 E004BA 0 +OP4 E004BB 0 +OP4 E004BC 0 +OP4 E004BD 0 +OP4 E004BE 0 +OP4 E004BF 0 +OP4 E004C0 0 +OP4 E004C1 0 +OP4 E004C2 0 +OP4 E004C3 0 +OP4 E004C4 0 +OP4 E004C5 0 +OP4 E004C6 0 +OP4 E004C7 0 +OP4 E004C8 0 +OP4 E004C9 0 +OP4 E004CA 0 +OP4 E004CB 0 +OP4 E004CC 0 +OP4 E004CD 0 +OP4 E004CE 0 +OP4 E004CF 0 +OP4 E004D0 0 +OP4 E004D1 0 +OP4 E004D2 0 +OP4 E004D3 0 +OP4 E004D4 0 +OP4 E004D5 0 +OP4 E004D6 0 +OP4 E004D7 0 +OP4 E004D8 0 +OP4 E004D9 0 +OP4 E004DA 0 +OP4 E004DB 0 +OP4 E004DC 0 +OP4 E004DD 0 +OP4 E004DE 0 +OP4 E004DF 0 +OP4 E004E0 0 +OP4 E004E1 0 +OP4 E004E2 0 +OP4 E004E3 0 +OP4 E004E4 0 +OP4 E004E5 0 +OP4 E004E6 0 +OP4 E004E7 0 +OP4 E004E8 0 +OP4 E004E9 0 +OP4 E004EA 0 +OP4 E004EB 0 +OP4 E004EC 0 +OP4 E004ED 0 +OP4 E004EE 0 +OP4 E004EF 0 +OP4 E004F0 0 +OP4 E004F1 0 +OP4 E004F2 0 +OP4 E004F3 0 +OP4 E004F4 0 +OP4 E004F5 0 +OP4 E004F6 0 +OP4 E004F7 0 +OP4 E004F8 0 +OP4 E004F9 0 +OP4 E004FA 0 +OP4 E004FB 0 +OP4 E004FC 0 +OP4 E004FD 0 +OP4 E004FE 0 +OP4 E004FF 0 +OP4 E00500 0 +OP4 E00501 0 +OP4 E00502 0 +OP4 E00503 0 +OP4 E00504 0 +OP4 E00505 0 +OP4 E00506 0 +OP4 E00507 0 +OP4 E00508 0 +OP4 E00509 0 +OP4 E0050A 0 +OP4 E0050B 0 +OP4 E0050C 0 +OP4 E0050D 0 +OP4 E0050E 0 +OP4 E0050F 0 +OP4 E00510 0 +OP4 E00511 0 +OP4 E00512 0 +OP4 E00513 0 +OP4 E00514 0 +OP4 E00515 0 +OP4 E00516 0 +OP4 E00517 0 +OP4 E00518 0 +OP4 E00519 0 +OP4 E0051A 0 +OP4 E0051B 0 +OP4 E0051C 0 +OP4 E0051D 0 +OP4 E0051E 0 +OP4 E0051F 0 +OP4 E00520 0 +OP4 E00521 0 +OP4 E00522 0 +OP4 E00523 0 +OP4 E00524 0 +OP4 E00525 0 +OP4 E00526 0 +OP4 E00527 0 +OP4 E00528 0 +OP4 E00529 0 +OP4 E0052A 0 +OP4 E0052B 0 +OP4 E0052C 0 +OP4 E0052D 0 +OP4 E0052E 0 +OP4 E0052F 0 +OP4 E00530 0 +OP4 E00531 0 +OP4 E00532 0 +OP4 E00533 0 +OP4 E00534 0 +OP4 E00535 0 +OP4 E00536 0 +OP4 E00537 0 +OP4 E00538 0 +OP4 E00539 0 +OP4 E0053A 0 +OP4 E0053B 0 +OP4 E0053C 0 +OP4 E0053D 0 +OP4 E0053E 0 +OP4 E0053F 0 +OP4 E00540 0 +OP4 E00541 0 +OP4 E00542 0 +OP4 E00543 0 +OP4 E00544 0 +OP4 E00545 0 +OP4 E00546 0 +OP4 E00547 0 +OP4 E00548 0 +OP4 E00549 0 +OP4 E0054A 0 +OP4 E0054B 0 +OP4 E0054C 0 +OP4 E0054D 0 +OP4 E0054E 0 +OP4 E0054F 0 +OP4 E00550 0 +OP4 E00551 0 +OP4 E00552 0 +OP4 E00553 0 +OP4 E00554 0 +OP4 E00555 0 +OP4 E00556 0 +OP4 E00557 0 +OP4 E00558 0 +OP4 E00559 0 +OP4 E0055A 0 +OP4 E0055B 0 +OP4 E0055C 0 +OP4 E0055D 0 +OP4 E0055E 0 +OP4 E0055F 0 +OP4 E00560 0 +OP4 E00561 0 +OP4 E00562 0 +OP4 E00563 0 +OP4 E00564 0 +OP4 E00565 0 +OP4 E00566 0 +OP4 E00567 0 +OP4 E00568 0 +OP4 E00569 0 +OP4 E0056A 0 +OP4 E0056B 0 +OP4 E0056C 0 +OP4 E0056D 0 +OP4 E0056E 0 +OP4 E0056F 0 +OP4 E00570 0 +OP4 E00571 0 +OP4 E00572 0 +OP4 E00573 0 +OP4 E00574 0 +OP4 E00575 0 +OP4 E00576 0 +OP4 E00577 0 +OP4 E00578 0 +OP4 E00579 0 +OP4 E0057A 0 +OP4 E0057B 0 +OP4 E0057C 0 +OP4 E0057D 0 +OP4 E0057E 0 +OP4 E0057F 0 +OP4 E00580 0 +OP4 E00581 0 +OP4 E00582 0 +OP4 E00583 0 +OP4 E00584 0 +OP4 E00585 0 +OP4 E00586 0 +OP4 E00587 0 +OP4 E00588 0 +OP4 E00589 0 +OP4 E0058A 0 +OP4 E0058B 0 +OP4 E0058C 0 +OP4 E0058D 0 +OP4 E0058E 0 +OP4 E0058F 0 +OP4 E00590 0 +OP4 E00591 0 +OP4 E00592 0 +OP4 E00593 0 +OP4 E00594 0 +OP4 E00595 0 +OP4 E00596 0 +OP4 E00597 0 +OP4 E00598 0 +OP4 E00599 0 +OP4 E0059A 0 +OP4 E0059B 0 +OP4 E0059C 0 +OP4 E0059D 0 +OP4 E0059E 0 +OP4 E0059F 0 +OP4 E005A0 0 +OP4 E005A1 0 +OP4 E005A2 0 +OP4 E005A3 0 +OP4 E005A4 0 +OP4 E005A5 0 +OP4 E005A6 0 +OP4 E005A7 0 +OP4 E005A8 0 +OP4 E005A9 0 +OP4 E005AA 0 +OP4 E005AB 0 +OP4 E005AC 0 +OP4 E005AD 0 +OP4 E005AE 0 +OP4 E005AF 0 +OP4 E005B0 0 +OP4 E005B1 0 +OP4 E005B2 0 +OP4 E005B3 0 +OP4 E005B4 0 +OP4 E005B5 0 +OP4 E005B6 0 +OP4 E005B7 0 +OP4 E005B8 0 +OP4 E005B9 0 +OP4 E005BA 0 +OP4 E005BB 0 +OP4 E005BC 0 +OP4 E005BD 0 +OP4 E005BE 0 +OP4 E005BF 0 +OP4 E005C0 0 +OP4 E005C1 0 +OP4 E005C2 0 +OP4 E005C3 0 +OP4 E005C4 0 +OP4 E005C5 0 +OP4 E005C6 0 +OP4 E005C7 0 +OP4 E005C8 0 +OP4 E005C9 0 +OP4 E005CA 0 +OP4 E005CB 0 +OP4 E005CC 0 +OP4 E005CD 0 +OP4 E005CE 0 +OP4 E005CF 0 +OP4 E005D0 0 +OP4 E005D1 0 +OP4 E005D2 0 +OP4 E005D3 0 +OP4 E005D4 0 +OP4 E005D5 0 +OP4 E005D6 0 +OP4 E005D7 0 +OP4 E005D8 0 +OP4 E005D9 0 +OP4 E005DA 0 +OP4 E005DB 0 +OP4 E005DC 0 +OP4 E005DD 0 +OP4 E005DE 0 +OP4 E005DF 0 +OP4 E005E0 0 +OP4 E005E1 0 +OP4 E005E2 0 +OP4 E005E3 0 +OP4 E005E4 0 +OP4 E005E5 0 +OP4 E005E6 0 +OP4 E005E7 0 +OP4 E005E8 0 +OP4 E005E9 0 +OP4 E005EA 0 +OP4 E005EB 0 +OP4 E005EC 0 +OP4 E005ED 0 +OP4 E005EE 0 +OP4 E005EF 0 +OP4 E005F0 0 +OP4 E005F1 0 +OP4 E005F2 0 +OP4 E005F3 0 +OP4 E005F4 0 +OP4 E005F5 0 +OP4 E005F6 0 +OP4 E005F7 0 +OP4 E005F8 0 +OP4 E005F9 0 +OP4 E005FA 0 +OP4 E005FB 0 +OP4 E005FC 0 +OP4 E005FD 0 +OP4 E005FE 0 +OP4 E005FF 0 +OP4 E00600 0 +OP4 E00601 0 +OP4 E00602 0 +OP4 E00603 0 +OP4 E00604 0 +OP4 E00605 0 +OP4 E00606 0 +OP4 E00607 0 +OP4 E00608 0 +OP4 E00609 0 +OP4 E0060A 0 +OP4 E0060B 0 +OP4 E0060C 0 +OP4 E0060D 0 +OP4 E0060E 0 +OP4 E0060F 0 +OP4 E00610 0 +OP4 E00611 0 +OP4 E00612 0 +OP4 E00613 0 +OP4 E00614 0 +OP4 E00615 0 +OP4 E00616 0 +OP4 E00617 0 +OP4 E00618 0 +OP4 E00619 0 +OP4 E0061A 0 +OP4 E0061B 0 +OP4 E0061C 0 +OP4 E0061D 0 +OP4 E0061E 0 +OP4 E0061F 0 +OP4 E00620 0 +OP4 E00621 0 +OP4 E00622 0 +OP4 E00623 0 +OP4 E00624 0 +OP4 E00625 0 +OP4 E00626 0 +OP4 E00627 0 +OP4 E00628 0 +OP4 E00629 0 +OP4 E0062A 0 +OP4 E0062B 0 +OP4 E0062C 0 +OP4 E0062D 0 +OP4 E0062E 0 +OP4 E0062F 0 +OP4 E00630 0 +OP4 E00631 0 +OP4 E00632 0 +OP4 E00633 0 +OP4 E00634 0 +OP4 E00635 0 +OP4 E00636 0 +OP4 E00637 0 +OP4 E00638 0 +OP4 E00639 0 +OP4 E0063A 0 +OP4 E0063B 0 +OP4 E0063C 0 +OP4 E0063D 0 +OP4 E0063E 0 +OP4 E0063F 0 +OP4 E00640 0 +OP4 E00641 0 +OP4 E00642 0 +OP4 E00643 0 +OP4 E00644 0 +OP4 E00645 0 +OP4 E00646 0 +OP4 E00647 0 +OP4 E00648 0 +OP4 E00649 0 +OP4 E0064A 0 +OP4 E0064B 0 +OP4 E0064C 0 +OP4 E0064D 0 +OP4 E0064E 0 +OP4 E0064F 0 +OP4 E00650 0 +OP4 E00651 0 +OP4 E00652 0 +OP4 E00653 0 +OP4 E00654 0 +OP4 E00655 0 +OP4 E00656 0 +OP4 E00657 0 +OP4 E00658 0 +OP4 E00659 0 +OP4 E0065A 0 +OP4 E0065B 0 +OP4 E0065C 0 +OP4 E0065D 0 +OP4 E0065E 0 +OP4 E0065F 0 +OP4 E00660 0 +OP4 E00661 0 +OP4 E00662 0 +OP4 E00663 0 +OP4 E00664 0 +OP4 E00665 0 +OP4 E00666 0 +OP4 E00667 0 +OP4 E00668 0 +OP4 E00669 0 +OP4 E0066A 0 +OP4 E0066B 0 +OP4 E0066C 0 +OP4 E0066D 0 +OP4 E0066E 0 +OP4 E0066F 0 +OP4 E00670 0 +OP4 E00671 0 +OP4 E00672 0 +OP4 E00673 0 +OP4 E00674 0 +OP4 E00675 0 +OP4 E00676 0 +OP4 E00677 0 +OP4 E00678 0 +OP4 E00679 0 +OP4 E0067A 0 +OP4 E0067B 0 +OP4 E0067C 0 +OP4 E0067D 0 +OP4 E0067E 0 +OP4 E0067F 0 +OP4 E00680 0 +OP4 E00681 0 +OP4 E00682 0 +OP4 E00683 0 +OP4 E00684 0 +OP4 E00685 0 +OP4 E00686 0 +OP4 E00687 0 +OP4 E00688 0 +OP4 E00689 0 +OP4 E0068A 0 +OP4 E0068B 0 +OP4 E0068C 0 +OP4 E0068D 0 +OP4 E0068E 0 +OP4 E0068F 0 +OP4 E00690 0 +OP4 E00691 0 +OP4 E00692 0 +OP4 E00693 0 +OP4 E00694 0 +OP4 E00695 0 +OP4 E00696 0 +OP4 E00697 0 +OP4 E00698 0 +OP4 E00699 0 +OP4 E0069A 0 +OP4 E0069B 0 +OP4 E0069C 0 +OP4 E0069D 0 +OP4 E0069E 0 +OP4 E0069F 0 +OP4 E006A0 0 +OP4 E006A1 0 +OP4 E006A2 0 +OP4 E006A3 0 +OP4 E006A4 0 +OP4 E006A5 0 +OP4 E006A6 0 +OP4 E006A7 0 +OP4 E006A8 0 +OP4 E006A9 0 +OP4 E006AA 0 +OP4 E006AB 0 +OP4 E006AC 0 +OP4 E006AD 0 +OP4 E006AE 0 +OP4 E006AF 0 +OP4 E006B0 0 +OP4 E006B1 0 +OP4 E006B2 0 +OP4 E006B3 0 +OP4 E006B4 0 +OP4 E006B5 0 +OP4 E006B6 0 +OP4 E006B7 0 +OP4 E006B8 0 +OP4 E006B9 0 +OP4 E006BA 0 +OP4 E006BB 0 +OP4 E006BC 0 +OP4 E006BD 0 +OP4 E006BE 0 +OP4 E006BF 0 +OP4 E006C0 0 +OP4 E006C1 0 +OP4 E006C2 0 +OP4 E006C3 0 +OP4 E006C4 0 +OP4 E006C5 0 +OP4 E006C6 0 +OP4 E006C7 0 +OP4 E006C8 0 +OP4 E006C9 0 +OP4 E006CA 0 +OP4 E006CB 0 +OP4 E006CC 0 +OP4 E006CD 0 +OP4 E006CE 0 +OP4 E006CF 0 +OP4 E006D0 0 +OP4 E006D1 0 +OP4 E006D2 0 +OP4 E006D3 0 +OP4 E006D4 0 +OP4 E006D5 0 +OP4 E006D6 0 +OP4 E006D7 0 +OP4 E006D8 0 +OP4 E006D9 0 +OP4 E006DA 0 +OP4 E006DB 0 +OP4 E006DC 0 +OP4 E006DD 0 +OP4 E006DE 0 +OP4 E006DF 0 +OP4 E006E0 0 +OP4 E006E1 0 +OP4 E006E2 0 +OP4 E006E3 0 +OP4 E006E4 0 +OP4 E006E5 0 +OP4 E006E6 0 +OP4 E006E7 0 +OP4 E006E8 0 +OP4 E006E9 0 +OP4 E006EA 0 +OP4 E006EB 0 +OP4 E006EC 0 +OP4 E006ED 0 +OP4 E006EE 0 +OP4 E006EF 0 +OP4 E006F0 0 +OP4 E006F1 0 +OP4 E006F2 0 +OP4 E006F3 0 +OP4 E006F4 0 +OP4 E006F5 0 +OP4 E006F6 0 +OP4 E006F7 0 +OP4 E006F8 0 +OP4 E006F9 0 +OP4 E006FA 0 +OP4 E006FB 0 +OP4 E006FC 0 +OP4 E006FD 0 +OP4 E006FE 0 +OP4 E006FF 0 +OP4 E00700 0 +OP4 E00701 0 +OP4 E00702 0 +OP4 E00703 0 +OP4 E00704 0 +OP4 E00705 0 +OP4 E00706 0 +OP4 E00707 0 +OP4 E00708 0 +OP4 E00709 0 +OP4 E0070A 0 +OP4 E0070B 0 +OP4 E0070C 0 +OP4 E0070D 0 +OP4 E0070E 0 +OP4 E0070F 0 +OP4 E00710 0 +OP4 E00711 0 +OP4 E00712 0 +OP4 E00713 0 +OP4 E00714 0 +OP4 E00715 0 +OP4 E00716 0 +OP4 E00717 0 +OP4 E00718 0 +OP4 E00719 0 +OP4 E0071A 0 +OP4 E0071B 0 +OP4 E0071C 0 +OP4 E0071D 0 +OP4 E0071E 0 +OP4 E0071F 0 +OP4 E00720 0 +OP4 E00721 0 +OP4 E00722 0 +OP4 E00723 0 +OP4 E00724 0 +OP4 E00725 0 +OP4 E00726 0 +OP4 E00727 0 +OP4 E00728 0 +OP4 E00729 0 +OP4 E0072A 0 +OP4 E0072B 0 +OP4 E0072C 0 +OP4 E0072D 0 +OP4 E0072E 0 +OP4 E0072F 0 +OP4 E00730 0 +OP4 E00731 0 +OP4 E00732 0 +OP4 E00733 0 +OP4 E00734 0 +OP4 E00735 0 +OP4 E00736 0 +OP4 E00737 0 +OP4 E00738 0 +OP4 E00739 0 +OP4 E0073A 0 +OP4 E0073B 0 +OP4 E0073C 0 +OP4 E0073D 0 +OP4 E0073E 0 +OP4 E0073F 0 +OP4 E00740 0 +OP4 E00741 0 +OP4 E00742 0 +OP4 E00743 0 +OP4 E00744 0 +OP4 E00745 0 +OP4 E00746 0 +OP4 E00747 0 +OP4 E00748 0 +OP4 E00749 0 +OP4 E0074A 0 +OP4 E0074B 0 +OP4 E0074C 0 +OP4 E0074D 0 +OP4 E0074E 0 +OP4 E0074F 0 +OP4 E00750 0 +OP4 E00751 0 +OP4 E00752 0 +OP4 E00753 0 +OP4 E00754 0 +OP4 E00755 0 +OP4 E00756 0 +OP4 E00757 0 +OP4 E00758 0 +OP4 E00759 0 +OP4 E0075A 0 +OP4 E0075B 0 +OP4 E0075C 0 +OP4 E0075D 0 +OP4 E0075E 0 +OP4 E0075F 0 +OP4 E00760 0 +OP4 E00761 0 +OP4 E00762 0 +OP4 E00763 0 +OP4 E00764 0 +OP4 E00765 0 +OP4 E00766 0 +OP4 E00767 0 +OP4 E00768 0 +OP4 E00769 0 +OP4 E0076A 0 +OP4 E0076B 0 +OP4 E0076C 0 +OP4 E0076D 0 +OP4 E0076E 0 +OP4 E0076F 0 +OP4 E00770 0 +OP4 E00771 0 +OP4 E00772 0 +OP4 E00773 0 +OP4 E00774 0 +OP4 E00775 0 +OP4 E00776 0 +OP4 E00777 0 +OP4 E00778 0 +OP4 E00779 0 +OP4 E0077A 0 +OP4 E0077B 0 +OP4 E0077C 0 +OP4 E0077D 0 +OP4 E0077E 0 +OP4 E0077F 0 +OP4 E00780 0 +OP4 E00781 0 +OP4 E00782 0 +OP4 E00783 0 +OP4 E00784 0 +OP4 E00785 0 +OP4 E00786 0 +OP4 E00787 0 +OP4 E00788 0 +OP4 E00789 0 +OP4 E0078A 0 +OP4 E0078B 0 +OP4 E0078C 0 +OP4 E0078D 0 +OP4 E0078E 0 +OP4 E0078F 0 +OP4 E00790 0 +OP4 E00791 0 +OP4 E00792 0 +OP4 E00793 0 +OP4 E00794 0 +OP4 E00795 0 +OP4 E00796 0 +OP4 E00797 0 +OP4 E00798 0 +OP4 E00799 0 +OP4 E0079A 0 +OP4 E0079B 0 +OP4 E0079C 0 +OP4 E0079D 0 +OP4 E0079E 0 +OP4 E0079F 0 +OP4 E007A0 0 +OP4 E007A1 0 +OP4 E007A2 0 +OP4 E007A3 0 +OP4 E007A4 0 +OP4 E007A5 0 +OP4 E007A6 0 +OP4 E007A7 0 +OP4 E007A8 0 +OP4 E007A9 0 +OP4 E007AA 0 +OP4 E007AB 0 +OP4 E007AC 0 +OP4 E007AD 0 +OP4 E007AE 0 +OP4 E007AF 0 +OP4 E007B0 0 +OP4 E007B1 0 +OP4 E007B2 0 +OP4 E007B3 0 +OP4 E007B4 0 +OP4 E007B5 0 +OP4 E007B6 0 +OP4 E007B7 0 +OP4 E007B8 0 +OP4 E007B9 0 +OP4 E007BA 0 +OP4 E007BB 0 +OP4 E007BC 0 +OP4 E007BD 0 +OP4 E007BE 0 +OP4 E007BF 0 +OP4 E007C0 0 +OP4 E007C1 0 +OP4 E007C2 0 +OP4 E007C3 0 +OP4 E007C4 0 +OP4 E007C5 0 +OP4 E007C6 0 +OP4 E007C7 0 +OP4 E007C8 0 +OP4 E007C9 0 +OP4 E007CA 0 +OP4 E007CB 0 +OP4 E007CC 0 +OP4 E007CD 0 +OP4 E007CE 0 +OP4 E007CF 0 +OP4 E007D0 0 +OP4 E007D1 0 +OP4 E007D2 0 +OP4 E007D3 0 +OP4 E007D4 0 +OP4 E007D5 0 +OP4 E007D6 0 +OP4 E007D7 0 +OP4 E007D8 0 +OP4 E007D9 0 +OP4 E007DA 0 +OP4 E007DB 0 +OP4 E007DC 0 +OP4 E007DD 0 +OP4 E007DE 0 +OP4 E007DF 0 +OP4 E007E0 0 +OP4 E007E1 0 +OP4 E007E2 0 +OP4 E007E3 0 +OP4 E007E4 0 +OP4 E007E5 0 +OP4 E007E6 0 +OP4 E007E7 0 +OP4 E007E8 0 +OP4 E007E9 0 +OP4 E007EA 0 +OP4 E007EB 0 +OP4 E007EC 0 +OP4 E007ED 0 +OP4 E007EE 0 +OP4 E007EF 0 +OP4 E007F0 0 +OP4 E007F1 0 +OP4 E007F2 0 +OP4 E007F3 0 +OP4 E007F4 0 +OP4 E007F5 0 +OP4 E007F6 0 +OP4 E007F7 0 +OP4 E007F8 0 +OP4 E007F9 0 +OP4 E007FA 0 +OP4 E007FB 0 +OP4 E007FC 0 +OP4 E007FD 0 +OP4 E007FE 0 +OP4 E007FF 0 +OP4 E00800 0 +OP4 E00801 0 +OP4 E00802 0 +OP4 E00803 0 +OP4 E00804 0 +OP4 E00805 0 +OP4 E00806 0 +OP4 E00807 0 +OP4 E00808 0 +OP4 E00809 0 +OP4 E0080A 0 +OP4 E0080B 0 +OP4 E0080C 0 +OP4 E0080D 0 +OP4 E0080E 0 +OP4 E0080F 0 +OP4 E00810 0 +OP4 E00811 0 +OP4 E00812 0 +OP4 E00813 0 +OP4 E00814 0 +OP4 E00815 0 +OP4 E00816 0 +OP4 E00817 0 +OP4 E00818 0 +OP4 E00819 0 +OP4 E0081A 0 +OP4 E0081B 0 +OP4 E0081C 0 +OP4 E0081D 0 +OP4 E0081E 0 +OP4 E0081F 0 +OP4 E00820 0 +OP4 E00821 0 +OP4 E00822 0 +OP4 E00823 0 +OP4 E00824 0 +OP4 E00825 0 +OP4 E00826 0 +OP4 E00827 0 +OP4 E00828 0 +OP4 E00829 0 +OP4 E0082A 0 +OP4 E0082B 0 +OP4 E0082C 0 +OP4 E0082D 0 +OP4 E0082E 0 +OP4 E0082F 0 +OP4 E00830 0 +OP4 E00831 0 +OP4 E00832 0 +OP4 E00833 0 +OP4 E00834 0 +OP4 E00835 0 +OP4 E00836 0 +OP4 E00837 0 +OP4 E00838 0 +OP4 E00839 0 +OP4 E0083A 0 +OP4 E0083B 0 +OP4 E0083C 0 +OP4 E0083D 0 +OP4 E0083E 0 +OP4 E0083F 0 +OP4 E00840 0 +OP4 E00841 0 +OP4 E00842 0 +OP4 E00843 0 +OP4 E00844 0 +OP4 E00845 0 +OP4 E00846 0 +OP4 E00847 0 +OP4 E00848 0 +OP4 E00849 0 +OP4 E0084A 0 +OP4 E0084B 0 +OP4 E0084C 0 +OP4 E0084D 0 +OP4 E0084E 0 +OP4 E0084F 0 +OP4 E00850 0 +OP4 E00851 0 +OP4 E00852 0 +OP4 E00853 0 +OP4 E00854 0 +OP4 E00855 0 +OP4 E00856 0 +OP4 E00857 0 +OP4 E00858 0 +OP4 E00859 0 +OP4 E0085A 0 +OP4 E0085B 0 +OP4 E0085C 0 +OP4 E0085D 0 +OP4 E0085E 0 +OP4 E0085F 0 +OP4 E00860 0 +OP4 E00861 0 +OP4 E00862 0 +OP4 E00863 0 +OP4 E00864 0 +OP4 E00865 0 +OP4 E00866 0 +OP4 E00867 0 +OP4 E00868 0 +OP4 E00869 0 +OP4 E0086A 0 +OP4 E0086B 0 +OP4 E0086C 0 +OP4 E0086D 0 +OP4 E0086E 0 +OP4 E0086F 0 +OP4 E00870 0 +OP4 E00871 0 +OP4 E00872 0 +OP4 E00873 0 +OP4 E00874 0 +OP4 E00875 0 +OP4 E00876 0 +OP4 E00877 0 +OP4 E00878 0 +OP4 E00879 0 +OP4 E0087A 0 +OP4 E0087B 0 +OP4 E0087C 0 +OP4 E0087D 0 +OP4 E0087E 0 +OP4 E0087F 0 +OP4 E00880 0 +OP4 E00881 0 +OP4 E00882 0 +OP4 E00883 0 +OP4 E00884 0 +OP4 E00885 0 +OP4 E00886 0 +OP4 E00887 0 +OP4 E00888 0 +OP4 E00889 0 +OP4 E0088A 0 +OP4 E0088B 0 +OP4 E0088C 0 +OP4 E0088D 0 +OP4 E0088E 0 +OP4 E0088F 0 +OP4 E00890 0 +OP4 E00891 0 +OP4 E00892 0 +OP4 E00893 0 +OP4 E00894 0 +OP4 E00895 0 +OP4 E00896 0 +OP4 E00897 0 +OP4 E00898 0 +OP4 E00899 0 +OP4 E0089A 0 +OP4 E0089B 0 +OP4 E0089C 0 +OP4 E0089D 0 +OP4 E0089E 0 +OP4 E0089F 0 +OP4 E008A0 0 +OP4 E008A1 0 +OP4 E008A2 0 +OP4 E008A3 0 +OP4 E008A4 0 +OP4 E008A5 0 +OP4 E008A6 0 +OP4 E008A7 0 +OP4 E008A8 0 +OP4 E008A9 0 +OP4 E008AA 0 +OP4 E008AB 0 +OP4 E008AC 0 +OP4 E008AD 0 +OP4 E008AE 0 +OP4 E008AF 0 +OP4 E008B0 0 +OP4 E008B1 0 +OP4 E008B2 0 +OP4 E008B3 0 +OP4 E008B4 0 +OP4 E008B5 0 +OP4 E008B6 0 +OP4 E008B7 0 +OP4 E008B8 0 +OP4 E008B9 0 +OP4 E008BA 0 +OP4 E008BB 0 +OP4 E008BC 0 +OP4 E008BD 0 +OP4 E008BE 0 +OP4 E008BF 0 +OP4 E008C0 0 +OP4 E008C1 0 +OP4 E008C2 0 +OP4 E008C3 0 +OP4 E008C4 0 +OP4 E008C5 0 +OP4 E008C6 0 +OP4 E008C7 0 +OP4 E008C8 0 +OP4 E008C9 0 +OP4 E008CA 0 +OP4 E008CB 0 +OP4 E008CC 0 +OP4 E008CD 0 +OP4 E008CE 0 +OP4 E008CF 0 +OP4 E008D0 0 +OP4 E008D1 0 +OP4 E008D2 0 +OP4 E008D3 0 +OP4 E008D4 0 +OP4 E008D5 0 +OP4 E008D6 0 +OP4 E008D7 0 +OP4 E008D8 0 +OP4 E008D9 0 +OP4 E008DA 0 +OP4 E008DB 0 +OP4 E008DC 0 +OP4 E008DD 0 +OP4 E008DE 0 +OP4 E008DF 0 +OP4 E008E0 0 +OP4 E008E1 0 +OP4 E008E2 0 +OP4 E008E3 0 +OP4 E008E4 0 +OP4 E008E5 0 +OP4 E008E6 0 +OP4 E008E7 0 +OP4 E008E8 0 +OP4 E008E9 0 +OP4 E008EA 0 +OP4 E008EB 0 +OP4 E008EC 0 +OP4 E008ED 0 +OP4 E008EE 0 +OP4 E008EF 0 +OP4 E008F0 0 +OP4 E008F1 0 +OP4 E008F2 0 +OP4 E008F3 0 +OP4 E008F4 0 +OP4 E008F5 0 +OP4 E008F6 0 +OP4 E008F7 0 +OP4 E008F8 0 +OP4 E008F9 0 +OP4 E008FA 0 +OP4 E008FB 0 +OP4 E008FC 0 +OP4 E008FD 0 +OP4 E008FE 0 +OP4 E008FF 0 +OP4 E00900 0 +OP4 E00901 0 +OP4 E00902 0 +OP4 E00903 0 +OP4 E00904 0 +OP4 E00905 0 +OP4 E00906 0 +OP4 E00907 0 +OP4 E00908 0 +OP4 E00909 0 +OP4 E0090A 0 +OP4 E0090B 0 +OP4 E0090C 0 +OP4 E0090D 0 +OP4 E0090E 0 +OP4 E0090F 0 +OP4 E00910 0 +OP4 E00911 0 +OP4 E00912 0 +OP4 E00913 0 +OP4 E00914 0 +OP4 E00915 0 +OP4 E00916 0 +OP4 E00917 0 +OP4 E00918 0 +OP4 E00919 0 +OP4 E0091A 0 +OP4 E0091B 0 +OP4 E0091C 0 +OP4 E0091D 0 +OP4 E0091E 0 +OP4 E0091F 0 +OP4 E00920 0 +OP4 E00921 0 +OP4 E00922 0 +OP4 E00923 0 +OP4 E00924 0 +OP4 E00925 0 +OP4 E00926 0 +OP4 E00927 0 +OP4 E00928 0 +OP4 E00929 0 +OP4 E0092A 0 +OP4 E0092B 0 +OP4 E0092C 0 +OP4 E0092D 0 +OP4 E0092E 0 +OP4 E0092F 0 +OP4 E00930 0 +OP4 E00931 0 +OP4 E00932 0 +OP4 E00933 0 +OP4 E00934 0 +OP4 E00935 0 +OP4 E00936 0 +OP4 E00937 0 +OP4 E00938 0 +OP4 E00939 0 +OP4 E0093A 0 +OP4 E0093B 0 +OP4 E0093C 0 +OP4 E0093D 0 +OP4 E0093E 0 +OP4 E0093F 0 +OP4 E00940 0 +OP4 E00941 0 +OP4 E00942 0 +OP4 E00943 0 +OP4 E00944 0 +OP4 E00945 0 +OP4 E00946 0 +OP4 E00947 0 +OP4 E00948 0 +OP4 E00949 0 +OP4 E0094A 0 +OP4 E0094B 0 +OP4 E0094C 0 +OP4 E0094D 0 +OP4 E0094E 0 +OP4 E0094F 0 +OP4 E00950 0 +OP4 E00951 0 +OP4 E00952 0 +OP4 E00953 0 +OP4 E00954 0 +OP4 E00955 0 +OP4 E00956 0 +OP4 E00957 0 +OP4 E00958 0 +OP4 E00959 0 +OP4 E0095A 0 +OP4 E0095B 0 +OP4 E0095C 0 +OP4 E0095D 0 +OP4 E0095E 0 +OP4 E0095F 0 +OP4 E00960 0 +OP4 E00961 0 +OP4 E00962 0 +OP4 E00963 0 +OP4 E00964 0 +OP4 E00965 0 +OP4 E00966 0 +OP4 E00967 0 +OP4 E00968 0 +OP4 E00969 0 +OP4 E0096A 0 +OP4 E0096B 0 +OP4 E0096C 0 +OP4 E0096D 0 +OP4 E0096E 0 +OP4 E0096F 0 +OP4 E00970 0 +OP4 E00971 0 +OP4 E00972 0 +OP4 E00973 0 +OP4 E00974 0 +OP4 E00975 0 +OP4 E00976 0 +OP4 E00977 0 +OP4 E00978 0 +OP4 E00979 0 +OP4 E0097A 0 +OP4 E0097B 0 +OP4 E0097C 0 +OP4 E0097D 0 +OP4 E0097E 0 +OP4 E0097F 0 +OP4 E00980 0 +OP4 E00981 0 +OP4 E00982 0 +OP4 E00983 0 +OP4 E00984 0 +OP4 E00985 0 +OP4 E00986 0 +OP4 E00987 0 +OP4 E00988 0 +OP4 E00989 0 +OP4 E0098A 0 +OP4 E0098B 0 +OP4 E0098C 0 +OP4 E0098D 0 +OP4 E0098E 0 +OP4 E0098F 0 +OP4 E00990 0 +OP4 E00991 0 +OP4 E00992 0 +OP4 E00993 0 +OP4 E00994 0 +OP4 E00995 0 +OP4 E00996 0 +OP4 E00997 0 +OP4 E00998 0 +OP4 E00999 0 +OP4 E0099A 0 +OP4 E0099B 0 +OP4 E0099C 0 +OP4 E0099D 0 +OP4 E0099E 0 +OP4 E0099F 0 +OP4 E009A0 0 +OP4 E009A1 0 +OP4 E009A2 0 +OP4 E009A3 0 +OP4 E009A4 0 +OP4 E009A5 0 +OP4 E009A6 0 +OP4 E009A7 0 +OP4 E009A8 0 +OP4 E009A9 0 +OP4 E009AA 0 +OP4 E009AB 0 +OP4 E009AC 0 +OP4 E009AD 0 +OP4 E009AE 0 +OP4 E009AF 0 +OP4 E009B0 0 +OP4 E009B1 0 +OP4 E009B2 0 +OP4 E009B3 0 +OP4 E009B4 0 +OP4 E009B5 0 +OP4 E009B6 0 +OP4 E009B7 0 +OP4 E009B8 0 +OP4 E009B9 0 +OP4 E009BA 0 +OP4 E009BB 0 +OP4 E009BC 0 +OP4 E009BD 0 +OP4 E009BE 0 +OP4 E009BF 0 +OP4 E009C0 0 +OP4 E009C1 0 +OP4 E009C2 0 +OP4 E009C3 0 +OP4 E009C4 0 +OP4 E009C5 0 +OP4 E009C6 0 +OP4 E009C7 0 +OP4 E009C8 0 +OP4 E009C9 0 +OP4 E009CA 0 +OP4 E009CB 0 +OP4 E009CC 0 +OP4 E009CD 0 +OP4 E009CE 0 +OP4 E009CF 0 +OP4 E009D0 0 +OP4 E009D1 0 +OP4 E009D2 0 +OP4 E009D3 0 +OP4 E009D4 0 +OP4 E009D5 0 +OP4 E009D6 0 +OP4 E009D7 0 +OP4 E009D8 0 +OP4 E009D9 0 +OP4 E009DA 0 +OP4 E009DB 0 +OP4 E009DC 0 +OP4 E009DD 0 +OP4 E009DE 0 +OP4 E009DF 0 +OP4 E009E0 0 +OP4 E009E1 0 +OP4 E009E2 0 +OP4 E009E3 0 +OP4 E009E4 0 +OP4 E009E5 0 +OP4 E009E6 0 +OP4 E009E7 0 +OP4 E009E8 0 +OP4 E009E9 0 +OP4 E009EA 0 +OP4 E009EB 0 +OP4 E009EC 0 +OP4 E009ED 0 +OP4 E009EE 0 +OP4 E009EF 0 +OP4 E009F0 0 +OP4 E009F1 0 +OP4 E009F2 0 +OP4 E009F3 0 +OP4 E009F4 0 +OP4 E009F5 0 +OP4 E009F6 0 +OP4 E009F7 0 +OP4 E009F8 0 +OP4 E009F9 0 +OP4 E009FA 0 +OP4 E009FB 0 +OP4 E009FC 0 +OP4 E009FD 0 +OP4 E009FE 0 +OP4 E009FF 0 +OP4 E00A00 0 +OP4 E00A01 0 +OP4 E00A02 0 +OP4 E00A03 0 +OP4 E00A04 0 +OP4 E00A05 0 +OP4 E00A06 0 +OP4 E00A07 0 +OP4 E00A08 0 diff --git a/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum2_itrace_irisc7.cfg.ext b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum2_itrace_irisc7.cfg.ext new file mode 100644 index 000000000000..573ca052cbb5 --- /dev/null +++ b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum2_itrace_irisc7.cfg.ext @@ -0,0 +1,2570 @@ +OP1 Spectrum2 +OP4 ITRACE0 0 +OP4 ITRACE1 0 +OP4 ITRACE2 0 +OP4 ITRACE3 0 +OP4 ITRACE4 0 +OP4 ITRACE5 0 +OP4 ITRACE6 0 +OP4 ITRACE7 1 +OP4 Main_PhyUC 0 +OP4 E00009 0 +OP4 E0000A 0 +OP4 E0000B 0 +OP4 E0000C 0 +OP4 E0000D 0 +OP4 E0000E 0 +OP4 E0000F 0 +OP4 E00010 0 +OP4 E00011 0 +OP4 E00012 0 +OP4 E00013 0 +OP4 E00014 0 +OP4 E00015 0 +OP4 E00016 0 +OP4 E00017 0 +OP4 E00018 0 +OP4 E00019 0 +OP4 E0001A 0 +OP4 E0001B 0 +OP4 E0001C 0 +OP4 E0001D 0 +OP4 E0001E 0 +OP4 E0001F 0 +OP4 E00020 0 +OP4 E00021 0 +OP4 E00022 0 +OP4 E00023 0 +OP4 E00024 0 +OP4 E00025 0 +OP4 E00026 0 +OP4 E00027 0 +OP4 E00028 0 +OP4 E00029 0 +OP4 E0002A 0 +OP4 E0002B 0 +OP4 E0002C 0 +OP4 E0002D 0 +OP4 E0002E 0 +OP4 E0002F 0 +OP4 E00030 0 +OP4 E00031 0 +OP4 E00032 0 +OP4 E00033 0 +OP4 E00034 0 +OP4 E00035 0 +OP4 E00036 0 +OP4 E00037 0 +OP4 E00038 0 +OP4 E00039 0 +OP4 E0003A 0 +OP4 E0003B 0 +OP4 E0003C 0 +OP4 E0003D 0 +OP4 E0003E 0 +OP4 E0003F 0 +OP4 E00040 0 +OP4 E00041 0 +OP4 E00042 0 +OP4 E00043 0 +OP4 E00044 0 +OP4 E00045 0 +OP4 E00046 0 +OP4 E00047 0 +OP4 E00048 0 +OP4 E00049 0 +OP4 E0004A 0 +OP4 E0004B 0 +OP4 E0004C 0 +OP4 E0004D 0 +OP4 E0004E 0 +OP4 E0004F 0 +OP4 E00050 0 +OP4 E00051 0 +OP4 E00052 0 +OP4 E00053 0 +OP4 E00054 0 +OP4 E00055 0 +OP4 E00056 0 +OP4 E00057 0 +OP4 E00058 0 +OP4 E00059 0 +OP4 E0005A 0 +OP4 E0005B 0 +OP4 E0005C 0 +OP4 E0005D 0 +OP4 E0005E 0 +OP4 E0005F 0 +OP4 E00060 0 +OP4 E00061 0 +OP4 E00062 0 +OP4 E00063 0 +OP4 E00064 0 +OP4 E00065 0 +OP4 E00066 0 +OP4 E00067 0 +OP4 E00068 0 +OP4 E00069 0 +OP4 E0006A 0 +OP4 E0006B 0 +OP4 E0006C 0 +OP4 E0006D 0 +OP4 E0006E 0 +OP4 E0006F 0 +OP4 E00070 0 +OP4 E00071 0 +OP4 E00072 0 +OP4 E00073 0 +OP4 E00074 0 +OP4 E00075 0 +OP4 E00076 0 +OP4 E00077 0 +OP4 E00078 0 +OP4 E00079 0 +OP4 E0007A 0 +OP4 E0007B 0 +OP4 E0007C 0 +OP4 E0007D 0 +OP4 E0007E 0 +OP4 E0007F 0 +OP4 E00080 0 +OP4 E00081 0 +OP4 E00082 0 +OP4 E00083 0 +OP4 E00084 0 +OP4 E00085 0 +OP4 E00086 0 +OP4 E00087 0 +OP4 E00088 0 +OP4 E00089 0 +OP4 E0008A 0 +OP4 E0008B 0 +OP4 E0008C 0 +OP4 E0008D 0 +OP4 E0008E 0 +OP4 E0008F 0 +OP4 E00090 0 +OP4 E00091 0 +OP4 E00092 0 +OP4 E00093 0 +OP4 E00094 0 +OP4 E00095 0 +OP4 E00096 0 +OP4 E00097 0 +OP4 E00098 0 +OP4 E00099 0 +OP4 E0009A 0 +OP4 E0009B 0 +OP4 E0009C 0 +OP4 E0009D 0 +OP4 E0009E 0 +OP4 E0009F 0 +OP4 E000A0 0 +OP4 E000A1 0 +OP4 E000A2 0 +OP4 E000A3 0 +OP4 E000A4 0 +OP4 E000A5 0 +OP4 E000A6 0 +OP4 E000A7 0 +OP4 E000A8 0 +OP4 E000A9 0 +OP4 E000AA 0 +OP4 E000AB 0 +OP4 E000AC 0 +OP4 E000AD 0 +OP4 E000AE 0 +OP4 E000AF 0 +OP4 E000B0 0 +OP4 E000B1 0 +OP4 E000B2 0 +OP4 E000B3 0 +OP4 E000B4 0 +OP4 E000B5 0 +OP4 E000B6 0 +OP4 E000B7 0 +OP4 E000B8 0 +OP4 E000B9 0 +OP4 E000BA 0 +OP4 E000BB 0 +OP4 E000BC 0 +OP4 E000BD 0 +OP4 E000BE 0 +OP4 E000BF 0 +OP4 E000C0 0 +OP4 E000C1 0 +OP4 E000C2 0 +OP4 E000C3 0 +OP4 E000C4 0 +OP4 E000C5 0 +OP4 E000C6 0 +OP4 E000C7 0 +OP4 E000C8 0 +OP4 E000C9 0 +OP4 E000CA 0 +OP4 E000CB 0 +OP4 E000CC 0 +OP4 E000CD 0 +OP4 E000CE 0 +OP4 E000CF 0 +OP4 E000D0 0 +OP4 E000D1 0 +OP4 E000D2 0 +OP4 E000D3 0 +OP4 E000D4 0 +OP4 E000D5 0 +OP4 E000D6 0 +OP4 E000D7 0 +OP4 E000D8 0 +OP4 E000D9 0 +OP4 E000DA 0 +OP4 E000DB 0 +OP4 E000DC 0 +OP4 E000DD 0 +OP4 E000DE 0 +OP4 E000DF 0 +OP4 E000E0 0 +OP4 E000E1 0 +OP4 E000E2 0 +OP4 E000E3 0 +OP4 E000E4 0 +OP4 E000E5 0 +OP4 E000E6 0 +OP4 E000E7 0 +OP4 E000E8 0 +OP4 E000E9 0 +OP4 E000EA 0 +OP4 E000EB 0 +OP4 E000EC 0 +OP4 E000ED 0 +OP4 E000EE 0 +OP4 E000EF 0 +OP4 E000F0 0 +OP4 E000F1 0 +OP4 E000F2 0 +OP4 E000F3 0 +OP4 E000F4 0 +OP4 E000F5 0 +OP4 E000F6 0 +OP4 E000F7 0 +OP4 E000F8 0 +OP4 E000F9 0 +OP4 E000FA 0 +OP4 E000FB 0 +OP4 E000FC 0 +OP4 E000FD 0 +OP4 E000FE 0 +OP4 E000FF 0 +OP4 E00100 0 +OP4 E00101 0 +OP4 E00102 0 +OP4 E00103 0 +OP4 E00104 0 +OP4 E00105 0 +OP4 E00106 0 +OP4 E00107 0 +OP4 E00108 0 +OP4 E00109 0 +OP4 E0010A 0 +OP4 E0010B 0 +OP4 E0010C 0 +OP4 E0010D 0 +OP4 E0010E 0 +OP4 E0010F 0 +OP4 E00110 0 +OP4 E00111 0 +OP4 E00112 0 +OP4 E00113 0 +OP4 E00114 0 +OP4 E00115 0 +OP4 E00116 0 +OP4 E00117 0 +OP4 E00118 0 +OP4 E00119 0 +OP4 E0011A 0 +OP4 E0011B 0 +OP4 E0011C 0 +OP4 E0011D 0 +OP4 E0011E 0 +OP4 E0011F 0 +OP4 E00120 0 +OP4 E00121 0 +OP4 E00122 0 +OP4 E00123 0 +OP4 E00124 0 +OP4 E00125 0 +OP4 E00126 0 +OP4 E00127 0 +OP4 E00128 0 +OP4 E00129 0 +OP4 E0012A 0 +OP4 E0012B 0 +OP4 E0012C 0 +OP4 E0012D 0 +OP4 E0012E 0 +OP4 E0012F 0 +OP4 E00130 0 +OP4 E00131 0 +OP4 E00132 0 +OP4 E00133 0 +OP4 E00134 0 +OP4 E00135 0 +OP4 E00136 0 +OP4 E00137 0 +OP4 E00138 0 +OP4 E00139 0 +OP4 E0013A 0 +OP4 E0013B 0 +OP4 E0013C 0 +OP4 E0013D 0 +OP4 E0013E 0 +OP4 E0013F 0 +OP4 E00140 0 +OP4 E00141 0 +OP4 E00142 0 +OP4 E00143 0 +OP4 E00144 0 +OP4 E00145 0 +OP4 E00146 0 +OP4 E00147 0 +OP4 E00148 0 +OP4 E00149 0 +OP4 E0014A 0 +OP4 E0014B 0 +OP4 E0014C 0 +OP4 E0014D 0 +OP4 E0014E 0 +OP4 E0014F 0 +OP4 E00150 0 +OP4 E00151 0 +OP4 E00152 0 +OP4 E00153 0 +OP4 E00154 0 +OP4 E00155 0 +OP4 E00156 0 +OP4 E00157 0 +OP4 E00158 0 +OP4 E00159 0 +OP4 E0015A 0 +OP4 E0015B 0 +OP4 E0015C 0 +OP4 E0015D 0 +OP4 E0015E 0 +OP4 E0015F 0 +OP4 E00160 0 +OP4 E00161 0 +OP4 E00162 0 +OP4 E00163 0 +OP4 E00164 0 +OP4 E00165 0 +OP4 E00166 0 +OP4 E00167 0 +OP4 E00168 0 +OP4 E00169 0 +OP4 E0016A 0 +OP4 E0016B 0 +OP4 E0016C 0 +OP4 E0016D 0 +OP4 E0016E 0 +OP4 E0016F 0 +OP4 E00170 0 +OP4 E00171 0 +OP4 E00172 0 +OP4 E00173 0 +OP4 E00174 0 +OP4 E00175 0 +OP4 E00176 0 +OP4 E00177 0 +OP4 E00178 0 +OP4 E00179 0 +OP4 E0017A 0 +OP4 E0017B 0 +OP4 E0017C 0 +OP4 E0017D 0 +OP4 E0017E 0 +OP4 E0017F 0 +OP4 E00180 0 +OP4 E00181 0 +OP4 E00182 0 +OP4 E00183 0 +OP4 E00184 0 +OP4 E00185 0 +OP4 E00186 0 +OP4 E00187 0 +OP4 E00188 0 +OP4 E00189 0 +OP4 E0018A 0 +OP4 E0018B 0 +OP4 E0018C 0 +OP4 E0018D 0 +OP4 E0018E 0 +OP4 E0018F 0 +OP4 E00190 0 +OP4 E00191 0 +OP4 E00192 0 +OP4 E00193 0 +OP4 E00194 0 +OP4 E00195 0 +OP4 E00196 0 +OP4 E00197 0 +OP4 E00198 0 +OP4 E00199 0 +OP4 E0019A 0 +OP4 E0019B 0 +OP4 E0019C 0 +OP4 E0019D 0 +OP4 E0019E 0 +OP4 E0019F 0 +OP4 E001A0 0 +OP4 E001A1 0 +OP4 E001A2 0 +OP4 E001A3 0 +OP4 E001A4 0 +OP4 E001A5 0 +OP4 E001A6 0 +OP4 E001A7 0 +OP4 E001A8 0 +OP4 E001A9 0 +OP4 E001AA 0 +OP4 E001AB 0 +OP4 E001AC 0 +OP4 E001AD 0 +OP4 E001AE 0 +OP4 E001AF 0 +OP4 E001B0 0 +OP4 E001B1 0 +OP4 E001B2 0 +OP4 E001B3 0 +OP4 E001B4 0 +OP4 E001B5 0 +OP4 E001B6 0 +OP4 E001B7 0 +OP4 E001B8 0 +OP4 E001B9 0 +OP4 E001BA 0 +OP4 E001BB 0 +OP4 E001BC 0 +OP4 E001BD 0 +OP4 E001BE 0 +OP4 E001BF 0 +OP4 E001C0 0 +OP4 E001C1 0 +OP4 E001C2 0 +OP4 E001C3 0 +OP4 E001C4 0 +OP4 E001C5 0 +OP4 E001C6 0 +OP4 E001C7 0 +OP4 E001C8 0 +OP4 E001C9 0 +OP4 E001CA 0 +OP4 E001CB 0 +OP4 E001CC 0 +OP4 E001CD 0 +OP4 E001CE 0 +OP4 E001CF 0 +OP4 E001D0 0 +OP4 E001D1 0 +OP4 E001D2 0 +OP4 E001D3 0 +OP4 E001D4 0 +OP4 E001D5 0 +OP4 E001D6 0 +OP4 E001D7 0 +OP4 E001D8 0 +OP4 E001D9 0 +OP4 E001DA 0 +OP4 E001DB 0 +OP4 E001DC 0 +OP4 E001DD 0 +OP4 E001DE 0 +OP4 E001DF 0 +OP4 E001E0 0 +OP4 E001E1 0 +OP4 E001E2 0 +OP4 E001E3 0 +OP4 E001E4 0 +OP4 E001E5 0 +OP4 E001E6 0 +OP4 E001E7 0 +OP4 E001E8 0 +OP4 E001E9 0 +OP4 E001EA 0 +OP4 E001EB 0 +OP4 E001EC 0 +OP4 E001ED 0 +OP4 E001EE 0 +OP4 E001EF 0 +OP4 E001F0 0 +OP4 E001F1 0 +OP4 E001F2 0 +OP4 E001F3 0 +OP4 E001F4 0 +OP4 E001F5 0 +OP4 E001F6 0 +OP4 E001F7 0 +OP4 E001F8 0 +OP4 E001F9 0 +OP4 E001FA 0 +OP4 E001FB 0 +OP4 E001FC 0 +OP4 E001FD 0 +OP4 E001FE 0 +OP4 E001FF 0 +OP4 E00200 0 +OP4 E00201 0 +OP4 E00202 0 +OP4 E00203 0 +OP4 E00204 0 +OP4 E00205 0 +OP4 E00206 0 +OP4 E00207 0 +OP4 E00208 0 +OP4 E00209 0 +OP4 E0020A 0 +OP4 E0020B 0 +OP4 E0020C 0 +OP4 E0020D 0 +OP4 E0020E 0 +OP4 E0020F 0 +OP4 E00210 0 +OP4 E00211 0 +OP4 E00212 0 +OP4 E00213 0 +OP4 E00214 0 +OP4 E00215 0 +OP4 E00216 0 +OP4 E00217 0 +OP4 E00218 0 +OP4 E00219 0 +OP4 E0021A 0 +OP4 E0021B 0 +OP4 E0021C 0 +OP4 E0021D 0 +OP4 E0021E 0 +OP4 E0021F 0 +OP4 E00220 0 +OP4 E00221 0 +OP4 E00222 0 +OP4 E00223 0 +OP4 E00224 0 +OP4 E00225 0 +OP4 E00226 0 +OP4 E00227 0 +OP4 E00228 0 +OP4 E00229 0 +OP4 E0022A 0 +OP4 E0022B 0 +OP4 E0022C 0 +OP4 E0022D 0 +OP4 E0022E 0 +OP4 E0022F 0 +OP4 E00230 0 +OP4 E00231 0 +OP4 E00232 0 +OP4 E00233 0 +OP4 E00234 0 +OP4 E00235 0 +OP4 E00236 0 +OP4 E00237 0 +OP4 E00238 0 +OP4 E00239 0 +OP4 E0023A 0 +OP4 E0023B 0 +OP4 E0023C 0 +OP4 E0023D 0 +OP4 E0023E 0 +OP4 E0023F 0 +OP4 E00240 0 +OP4 E00241 0 +OP4 E00242 0 +OP4 E00243 0 +OP4 E00244 0 +OP4 E00245 0 +OP4 E00246 0 +OP4 E00247 0 +OP4 E00248 0 +OP4 E00249 0 +OP4 E0024A 0 +OP4 E0024B 0 +OP4 E0024C 0 +OP4 E0024D 0 +OP4 E0024E 0 +OP4 E0024F 0 +OP4 E00250 0 +OP4 E00251 0 +OP4 E00252 0 +OP4 E00253 0 +OP4 E00254 0 +OP4 E00255 0 +OP4 E00256 0 +OP4 E00257 0 +OP4 E00258 0 +OP4 E00259 0 +OP4 E0025A 0 +OP4 E0025B 0 +OP4 E0025C 0 +OP4 E0025D 0 +OP4 E0025E 0 +OP4 E0025F 0 +OP4 E00260 0 +OP4 E00261 0 +OP4 E00262 0 +OP4 E00263 0 +OP4 E00264 0 +OP4 E00265 0 +OP4 E00266 0 +OP4 E00267 0 +OP4 E00268 0 +OP4 E00269 0 +OP4 E0026A 0 +OP4 E0026B 0 +OP4 E0026C 0 +OP4 E0026D 0 +OP4 E0026E 0 +OP4 E0026F 0 +OP4 E00270 0 +OP4 E00271 0 +OP4 E00272 0 +OP4 E00273 0 +OP4 E00274 0 +OP4 E00275 0 +OP4 E00276 0 +OP4 E00277 0 +OP4 E00278 0 +OP4 E00279 0 +OP4 E0027A 0 +OP4 E0027B 0 +OP4 E0027C 0 +OP4 E0027D 0 +OP4 E0027E 0 +OP4 E0027F 0 +OP4 E00280 0 +OP4 E00281 0 +OP4 E00282 0 +OP4 E00283 0 +OP4 E00284 0 +OP4 E00285 0 +OP4 E00286 0 +OP4 E00287 0 +OP4 E00288 0 +OP4 E00289 0 +OP4 E0028A 0 +OP4 E0028B 0 +OP4 E0028C 0 +OP4 E0028D 0 +OP4 E0028E 0 +OP4 E0028F 0 +OP4 E00290 0 +OP4 E00291 0 +OP4 E00292 0 +OP4 E00293 0 +OP4 E00294 0 +OP4 E00295 0 +OP4 E00296 0 +OP4 E00297 0 +OP4 E00298 0 +OP4 E00299 0 +OP4 E0029A 0 +OP4 E0029B 0 +OP4 E0029C 0 +OP4 E0029D 0 +OP4 E0029E 0 +OP4 E0029F 0 +OP4 E002A0 0 +OP4 E002A1 0 +OP4 E002A2 0 +OP4 E002A3 0 +OP4 E002A4 0 +OP4 E002A5 0 +OP4 E002A6 0 +OP4 E002A7 0 +OP4 E002A8 0 +OP4 E002A9 0 +OP4 E002AA 0 +OP4 E002AB 0 +OP4 E002AC 0 +OP4 E002AD 0 +OP4 E002AE 0 +OP4 E002AF 0 +OP4 E002B0 0 +OP4 E002B1 0 +OP4 E002B2 0 +OP4 E002B3 0 +OP4 E002B4 0 +OP4 E002B5 0 +OP4 E002B6 0 +OP4 E002B7 0 +OP4 E002B8 0 +OP4 E002B9 0 +OP4 E002BA 0 +OP4 E002BB 0 +OP4 E002BC 0 +OP4 E002BD 0 +OP4 E002BE 0 +OP4 E002BF 0 +OP4 E002C0 0 +OP4 E002C1 0 +OP4 E002C2 0 +OP4 E002C3 0 +OP4 E002C4 0 +OP4 E002C5 0 +OP4 E002C6 0 +OP4 E002C7 0 +OP4 E002C8 0 +OP4 E002C9 0 +OP4 E002CA 0 +OP4 E002CB 0 +OP4 E002CC 0 +OP4 E002CD 0 +OP4 E002CE 0 +OP4 E002CF 0 +OP4 E002D0 0 +OP4 E002D1 0 +OP4 E002D2 0 +OP4 E002D3 0 +OP4 E002D4 0 +OP4 E002D5 0 +OP4 E002D6 0 +OP4 E002D7 0 +OP4 E002D8 0 +OP4 E002D9 0 +OP4 E002DA 0 +OP4 E002DB 0 +OP4 E002DC 0 +OP4 E002DD 0 +OP4 E002DE 0 +OP4 E002DF 0 +OP4 E002E0 0 +OP4 E002E1 0 +OP4 E002E2 0 +OP4 E002E3 0 +OP4 E002E4 0 +OP4 E002E5 0 +OP4 E002E6 0 +OP4 E002E7 0 +OP4 E002E8 0 +OP4 E002E9 0 +OP4 E002EA 0 +OP4 E002EB 0 +OP4 E002EC 0 +OP4 E002ED 0 +OP4 E002EE 0 +OP4 E002EF 0 +OP4 E002F0 0 +OP4 E002F1 0 +OP4 E002F2 0 +OP4 E002F3 0 +OP4 E002F4 0 +OP4 E002F5 0 +OP4 E002F6 0 +OP4 E002F7 0 +OP4 E002F8 0 +OP4 E002F9 0 +OP4 E002FA 0 +OP4 E002FB 0 +OP4 E002FC 0 +OP4 E002FD 0 +OP4 E002FE 0 +OP4 E002FF 0 +OP4 E00300 0 +OP4 E00301 0 +OP4 E00302 0 +OP4 E00303 0 +OP4 E00304 0 +OP4 E00305 0 +OP4 E00306 0 +OP4 E00307 0 +OP4 E00308 0 +OP4 E00309 0 +OP4 E0030A 0 +OP4 E0030B 0 +OP4 E0030C 0 +OP4 E0030D 0 +OP4 E0030E 0 +OP4 E0030F 0 +OP4 E00310 0 +OP4 E00311 0 +OP4 E00312 0 +OP4 E00313 0 +OP4 E00314 0 +OP4 E00315 0 +OP4 E00316 0 +OP4 E00317 0 +OP4 E00318 0 +OP4 E00319 0 +OP4 E0031A 0 +OP4 E0031B 0 +OP4 E0031C 0 +OP4 E0031D 0 +OP4 E0031E 0 +OP4 E0031F 0 +OP4 E00320 0 +OP4 E00321 0 +OP4 E00322 0 +OP4 E00323 0 +OP4 E00324 0 +OP4 E00325 0 +OP4 E00326 0 +OP4 E00327 0 +OP4 E00328 0 +OP4 E00329 0 +OP4 E0032A 0 +OP4 E0032B 0 +OP4 E0032C 0 +OP4 E0032D 0 +OP4 E0032E 0 +OP4 E0032F 0 +OP4 E00330 0 +OP4 E00331 0 +OP4 E00332 0 +OP4 E00333 0 +OP4 E00334 0 +OP4 E00335 0 +OP4 E00336 0 +OP4 E00337 0 +OP4 E00338 0 +OP4 E00339 0 +OP4 E0033A 0 +OP4 E0033B 0 +OP4 E0033C 0 +OP4 E0033D 0 +OP4 E0033E 0 +OP4 E0033F 0 +OP4 E00340 0 +OP4 E00341 0 +OP4 E00342 0 +OP4 E00343 0 +OP4 E00344 0 +OP4 E00345 0 +OP4 E00346 0 +OP4 E00347 0 +OP4 E00348 0 +OP4 E00349 0 +OP4 E0034A 0 +OP4 E0034B 0 +OP4 E0034C 0 +OP4 E0034D 0 +OP4 E0034E 0 +OP4 E0034F 0 +OP4 E00350 0 +OP4 E00351 0 +OP4 E00352 0 +OP4 E00353 0 +OP4 E00354 0 +OP4 E00355 0 +OP4 E00356 0 +OP4 E00357 0 +OP4 E00358 0 +OP4 E00359 0 +OP4 E0035A 0 +OP4 E0035B 0 +OP4 E0035C 0 +OP4 E0035D 0 +OP4 E0035E 0 +OP4 E0035F 0 +OP4 E00360 0 +OP4 E00361 0 +OP4 E00362 0 +OP4 E00363 0 +OP4 E00364 0 +OP4 E00365 0 +OP4 E00366 0 +OP4 E00367 0 +OP4 E00368 0 +OP4 E00369 0 +OP4 E0036A 0 +OP4 E0036B 0 +OP4 E0036C 0 +OP4 E0036D 0 +OP4 E0036E 0 +OP4 E0036F 0 +OP4 E00370 0 +OP4 E00371 0 +OP4 E00372 0 +OP4 E00373 0 +OP4 E00374 0 +OP4 E00375 0 +OP4 E00376 0 +OP4 E00377 0 +OP4 E00378 0 +OP4 E00379 0 +OP4 E0037A 0 +OP4 E0037B 0 +OP4 E0037C 0 +OP4 E0037D 0 +OP4 E0037E 0 +OP4 E0037F 0 +OP4 E00380 0 +OP4 E00381 0 +OP4 E00382 0 +OP4 E00383 0 +OP4 E00384 0 +OP4 E00385 0 +OP4 E00386 0 +OP4 E00387 0 +OP4 E00388 0 +OP4 E00389 0 +OP4 E0038A 0 +OP4 E0038B 0 +OP4 E0038C 0 +OP4 E0038D 0 +OP4 E0038E 0 +OP4 E0038F 0 +OP4 E00390 0 +OP4 E00391 0 +OP4 E00392 0 +OP4 E00393 0 +OP4 E00394 0 +OP4 E00395 0 +OP4 E00396 0 +OP4 E00397 0 +OP4 E00398 0 +OP4 E00399 0 +OP4 E0039A 0 +OP4 E0039B 0 +OP4 E0039C 0 +OP4 E0039D 0 +OP4 E0039E 0 +OP4 E0039F 0 +OP4 E003A0 0 +OP4 E003A1 0 +OP4 E003A2 0 +OP4 E003A3 0 +OP4 E003A4 0 +OP4 E003A5 0 +OP4 E003A6 0 +OP4 E003A7 0 +OP4 E003A8 0 +OP4 E003A9 0 +OP4 E003AA 0 +OP4 E003AB 0 +OP4 E003AC 0 +OP4 E003AD 0 +OP4 E003AE 0 +OP4 E003AF 0 +OP4 E003B0 0 +OP4 E003B1 0 +OP4 E003B2 0 +OP4 E003B3 0 +OP4 E003B4 0 +OP4 E003B5 0 +OP4 E003B6 0 +OP4 E003B7 0 +OP4 E003B8 0 +OP4 E003B9 0 +OP4 E003BA 0 +OP4 E003BB 0 +OP4 E003BC 0 +OP4 E003BD 0 +OP4 E003BE 0 +OP4 E003BF 0 +OP4 E003C0 0 +OP4 E003C1 0 +OP4 E003C2 0 +OP4 E003C3 0 +OP4 E003C4 0 +OP4 E003C5 0 +OP4 E003C6 0 +OP4 E003C7 0 +OP4 E003C8 0 +OP4 E003C9 0 +OP4 E003CA 0 +OP4 E003CB 0 +OP4 E003CC 0 +OP4 E003CD 0 +OP4 E003CE 0 +OP4 E003CF 0 +OP4 E003D0 0 +OP4 E003D1 0 +OP4 E003D2 0 +OP4 E003D3 0 +OP4 E003D4 0 +OP4 E003D5 0 +OP4 E003D6 0 +OP4 E003D7 0 +OP4 E003D8 0 +OP4 E003D9 0 +OP4 E003DA 0 +OP4 E003DB 0 +OP4 E003DC 0 +OP4 E003DD 0 +OP4 E003DE 0 +OP4 E003DF 0 +OP4 E003E0 0 +OP4 E003E1 0 +OP4 E003E2 0 +OP4 E003E3 0 +OP4 E003E4 0 +OP4 E003E5 0 +OP4 E003E6 0 +OP4 E003E7 0 +OP4 E003E8 0 +OP4 E003E9 0 +OP4 E003EA 0 +OP4 E003EB 0 +OP4 E003EC 0 +OP4 E003ED 0 +OP4 E003EE 0 +OP4 E003EF 0 +OP4 E003F0 0 +OP4 E003F1 0 +OP4 E003F2 0 +OP4 E003F3 0 +OP4 E003F4 0 +OP4 E003F5 0 +OP4 E003F6 0 +OP4 E003F7 0 +OP4 E003F8 0 +OP4 E003F9 0 +OP4 E003FA 0 +OP4 E003FB 0 +OP4 E003FC 0 +OP4 E003FD 0 +OP4 E003FE 0 +OP4 E003FF 0 +OP4 E00400 0 +OP4 E00401 0 +OP4 E00402 0 +OP4 E00403 0 +OP4 E00404 0 +OP4 E00405 0 +OP4 E00406 0 +OP4 E00407 0 +OP4 E00408 0 +OP4 E00409 0 +OP4 E0040A 0 +OP4 E0040B 0 +OP4 E0040C 0 +OP4 E0040D 0 +OP4 E0040E 0 +OP4 E0040F 0 +OP4 E00410 0 +OP4 E00411 0 +OP4 E00412 0 +OP4 E00413 0 +OP4 E00414 0 +OP4 E00415 0 +OP4 E00416 0 +OP4 E00417 0 +OP4 E00418 0 +OP4 E00419 0 +OP4 E0041A 0 +OP4 E0041B 0 +OP4 E0041C 0 +OP4 E0041D 0 +OP4 E0041E 0 +OP4 E0041F 0 +OP4 E00420 0 +OP4 E00421 0 +OP4 E00422 0 +OP4 E00423 0 +OP4 E00424 0 +OP4 E00425 0 +OP4 E00426 0 +OP4 E00427 0 +OP4 E00428 0 +OP4 E00429 0 +OP4 E0042A 0 +OP4 E0042B 0 +OP4 E0042C 0 +OP4 E0042D 0 +OP4 E0042E 0 +OP4 E0042F 0 +OP4 E00430 0 +OP4 E00431 0 +OP4 E00432 0 +OP4 E00433 0 +OP4 E00434 0 +OP4 E00435 0 +OP4 E00436 0 +OP4 E00437 0 +OP4 E00438 0 +OP4 E00439 0 +OP4 E0043A 0 +OP4 E0043B 0 +OP4 E0043C 0 +OP4 E0043D 0 +OP4 E0043E 0 +OP4 E0043F 0 +OP4 E00440 0 +OP4 E00441 0 +OP4 E00442 0 +OP4 E00443 0 +OP4 E00444 0 +OP4 E00445 0 +OP4 E00446 0 +OP4 E00447 0 +OP4 E00448 0 +OP4 E00449 0 +OP4 E0044A 0 +OP4 E0044B 0 +OP4 E0044C 0 +OP4 E0044D 0 +OP4 E0044E 0 +OP4 E0044F 0 +OP4 E00450 0 +OP4 E00451 0 +OP4 E00452 0 +OP4 E00453 0 +OP4 E00454 0 +OP4 E00455 0 +OP4 E00456 0 +OP4 E00457 0 +OP4 E00458 0 +OP4 E00459 0 +OP4 E0045A 0 +OP4 E0045B 0 +OP4 E0045C 0 +OP4 E0045D 0 +OP4 E0045E 0 +OP4 E0045F 0 +OP4 E00460 0 +OP4 E00461 0 +OP4 E00462 0 +OP4 E00463 0 +OP4 E00464 0 +OP4 E00465 0 +OP4 E00466 0 +OP4 E00467 0 +OP4 E00468 0 +OP4 E00469 0 +OP4 E0046A 0 +OP4 E0046B 0 +OP4 E0046C 0 +OP4 E0046D 0 +OP4 E0046E 0 +OP4 E0046F 0 +OP4 E00470 0 +OP4 E00471 0 +OP4 E00472 0 +OP4 E00473 0 +OP4 E00474 0 +OP4 E00475 0 +OP4 E00476 0 +OP4 E00477 0 +OP4 E00478 0 +OP4 E00479 0 +OP4 E0047A 0 +OP4 E0047B 0 +OP4 E0047C 0 +OP4 E0047D 0 +OP4 E0047E 0 +OP4 E0047F 0 +OP4 E00480 0 +OP4 E00481 0 +OP4 E00482 0 +OP4 E00483 0 +OP4 E00484 0 +OP4 E00485 0 +OP4 E00486 0 +OP4 E00487 0 +OP4 E00488 0 +OP4 E00489 0 +OP4 E0048A 0 +OP4 E0048B 0 +OP4 E0048C 0 +OP4 E0048D 0 +OP4 E0048E 0 +OP4 E0048F 0 +OP4 E00490 0 +OP4 E00491 0 +OP4 E00492 0 +OP4 E00493 0 +OP4 E00494 0 +OP4 E00495 0 +OP4 E00496 0 +OP4 E00497 0 +OP4 E00498 0 +OP4 E00499 0 +OP4 E0049A 0 +OP4 E0049B 0 +OP4 E0049C 0 +OP4 E0049D 0 +OP4 E0049E 0 +OP4 E0049F 0 +OP4 E004A0 0 +OP4 E004A1 0 +OP4 E004A2 0 +OP4 E004A3 0 +OP4 E004A4 0 +OP4 E004A5 0 +OP4 E004A6 0 +OP4 E004A7 0 +OP4 E004A8 0 +OP4 E004A9 0 +OP4 E004AA 0 +OP4 E004AB 0 +OP4 E004AC 0 +OP4 E004AD 0 +OP4 E004AE 0 +OP4 E004AF 0 +OP4 E004B0 0 +OP4 E004B1 0 +OP4 E004B2 0 +OP4 E004B3 0 +OP4 E004B4 0 +OP4 E004B5 0 +OP4 E004B6 0 +OP4 E004B7 0 +OP4 E004B8 0 +OP4 E004B9 0 +OP4 E004BA 0 +OP4 E004BB 0 +OP4 E004BC 0 +OP4 E004BD 0 +OP4 E004BE 0 +OP4 E004BF 0 +OP4 E004C0 0 +OP4 E004C1 0 +OP4 E004C2 0 +OP4 E004C3 0 +OP4 E004C4 0 +OP4 E004C5 0 +OP4 E004C6 0 +OP4 E004C7 0 +OP4 E004C8 0 +OP4 E004C9 0 +OP4 E004CA 0 +OP4 E004CB 0 +OP4 E004CC 0 +OP4 E004CD 0 +OP4 E004CE 0 +OP4 E004CF 0 +OP4 E004D0 0 +OP4 E004D1 0 +OP4 E004D2 0 +OP4 E004D3 0 +OP4 E004D4 0 +OP4 E004D5 0 +OP4 E004D6 0 +OP4 E004D7 0 +OP4 E004D8 0 +OP4 E004D9 0 +OP4 E004DA 0 +OP4 E004DB 0 +OP4 E004DC 0 +OP4 E004DD 0 +OP4 E004DE 0 +OP4 E004DF 0 +OP4 E004E0 0 +OP4 E004E1 0 +OP4 E004E2 0 +OP4 E004E3 0 +OP4 E004E4 0 +OP4 E004E5 0 +OP4 E004E6 0 +OP4 E004E7 0 +OP4 E004E8 0 +OP4 E004E9 0 +OP4 E004EA 0 +OP4 E004EB 0 +OP4 E004EC 0 +OP4 E004ED 0 +OP4 E004EE 0 +OP4 E004EF 0 +OP4 E004F0 0 +OP4 E004F1 0 +OP4 E004F2 0 +OP4 E004F3 0 +OP4 E004F4 0 +OP4 E004F5 0 +OP4 E004F6 0 +OP4 E004F7 0 +OP4 E004F8 0 +OP4 E004F9 0 +OP4 E004FA 0 +OP4 E004FB 0 +OP4 E004FC 0 +OP4 E004FD 0 +OP4 E004FE 0 +OP4 E004FF 0 +OP4 E00500 0 +OP4 E00501 0 +OP4 E00502 0 +OP4 E00503 0 +OP4 E00504 0 +OP4 E00505 0 +OP4 E00506 0 +OP4 E00507 0 +OP4 E00508 0 +OP4 E00509 0 +OP4 E0050A 0 +OP4 E0050B 0 +OP4 E0050C 0 +OP4 E0050D 0 +OP4 E0050E 0 +OP4 E0050F 0 +OP4 E00510 0 +OP4 E00511 0 +OP4 E00512 0 +OP4 E00513 0 +OP4 E00514 0 +OP4 E00515 0 +OP4 E00516 0 +OP4 E00517 0 +OP4 E00518 0 +OP4 E00519 0 +OP4 E0051A 0 +OP4 E0051B 0 +OP4 E0051C 0 +OP4 E0051D 0 +OP4 E0051E 0 +OP4 E0051F 0 +OP4 E00520 0 +OP4 E00521 0 +OP4 E00522 0 +OP4 E00523 0 +OP4 E00524 0 +OP4 E00525 0 +OP4 E00526 0 +OP4 E00527 0 +OP4 E00528 0 +OP4 E00529 0 +OP4 E0052A 0 +OP4 E0052B 0 +OP4 E0052C 0 +OP4 E0052D 0 +OP4 E0052E 0 +OP4 E0052F 0 +OP4 E00530 0 +OP4 E00531 0 +OP4 E00532 0 +OP4 E00533 0 +OP4 E00534 0 +OP4 E00535 0 +OP4 E00536 0 +OP4 E00537 0 +OP4 E00538 0 +OP4 E00539 0 +OP4 E0053A 0 +OP4 E0053B 0 +OP4 E0053C 0 +OP4 E0053D 0 +OP4 E0053E 0 +OP4 E0053F 0 +OP4 E00540 0 +OP4 E00541 0 +OP4 E00542 0 +OP4 E00543 0 +OP4 E00544 0 +OP4 E00545 0 +OP4 E00546 0 +OP4 E00547 0 +OP4 E00548 0 +OP4 E00549 0 +OP4 E0054A 0 +OP4 E0054B 0 +OP4 E0054C 0 +OP4 E0054D 0 +OP4 E0054E 0 +OP4 E0054F 0 +OP4 E00550 0 +OP4 E00551 0 +OP4 E00552 0 +OP4 E00553 0 +OP4 E00554 0 +OP4 E00555 0 +OP4 E00556 0 +OP4 E00557 0 +OP4 E00558 0 +OP4 E00559 0 +OP4 E0055A 0 +OP4 E0055B 0 +OP4 E0055C 0 +OP4 E0055D 0 +OP4 E0055E 0 +OP4 E0055F 0 +OP4 E00560 0 +OP4 E00561 0 +OP4 E00562 0 +OP4 E00563 0 +OP4 E00564 0 +OP4 E00565 0 +OP4 E00566 0 +OP4 E00567 0 +OP4 E00568 0 +OP4 E00569 0 +OP4 E0056A 0 +OP4 E0056B 0 +OP4 E0056C 0 +OP4 E0056D 0 +OP4 E0056E 0 +OP4 E0056F 0 +OP4 E00570 0 +OP4 E00571 0 +OP4 E00572 0 +OP4 E00573 0 +OP4 E00574 0 +OP4 E00575 0 +OP4 E00576 0 +OP4 E00577 0 +OP4 E00578 0 +OP4 E00579 0 +OP4 E0057A 0 +OP4 E0057B 0 +OP4 E0057C 0 +OP4 E0057D 0 +OP4 E0057E 0 +OP4 E0057F 0 +OP4 E00580 0 +OP4 E00581 0 +OP4 E00582 0 +OP4 E00583 0 +OP4 E00584 0 +OP4 E00585 0 +OP4 E00586 0 +OP4 E00587 0 +OP4 E00588 0 +OP4 E00589 0 +OP4 E0058A 0 +OP4 E0058B 0 +OP4 E0058C 0 +OP4 E0058D 0 +OP4 E0058E 0 +OP4 E0058F 0 +OP4 E00590 0 +OP4 E00591 0 +OP4 E00592 0 +OP4 E00593 0 +OP4 E00594 0 +OP4 E00595 0 +OP4 E00596 0 +OP4 E00597 0 +OP4 E00598 0 +OP4 E00599 0 +OP4 E0059A 0 +OP4 E0059B 0 +OP4 E0059C 0 +OP4 E0059D 0 +OP4 E0059E 0 +OP4 E0059F 0 +OP4 E005A0 0 +OP4 E005A1 0 +OP4 E005A2 0 +OP4 E005A3 0 +OP4 E005A4 0 +OP4 E005A5 0 +OP4 E005A6 0 +OP4 E005A7 0 +OP4 E005A8 0 +OP4 E005A9 0 +OP4 E005AA 0 +OP4 E005AB 0 +OP4 E005AC 0 +OP4 E005AD 0 +OP4 E005AE 0 +OP4 E005AF 0 +OP4 E005B0 0 +OP4 E005B1 0 +OP4 E005B2 0 +OP4 E005B3 0 +OP4 E005B4 0 +OP4 E005B5 0 +OP4 E005B6 0 +OP4 E005B7 0 +OP4 E005B8 0 +OP4 E005B9 0 +OP4 E005BA 0 +OP4 E005BB 0 +OP4 E005BC 0 +OP4 E005BD 0 +OP4 E005BE 0 +OP4 E005BF 0 +OP4 E005C0 0 +OP4 E005C1 0 +OP4 E005C2 0 +OP4 E005C3 0 +OP4 E005C4 0 +OP4 E005C5 0 +OP4 E005C6 0 +OP4 E005C7 0 +OP4 E005C8 0 +OP4 E005C9 0 +OP4 E005CA 0 +OP4 E005CB 0 +OP4 E005CC 0 +OP4 E005CD 0 +OP4 E005CE 0 +OP4 E005CF 0 +OP4 E005D0 0 +OP4 E005D1 0 +OP4 E005D2 0 +OP4 E005D3 0 +OP4 E005D4 0 +OP4 E005D5 0 +OP4 E005D6 0 +OP4 E005D7 0 +OP4 E005D8 0 +OP4 E005D9 0 +OP4 E005DA 0 +OP4 E005DB 0 +OP4 E005DC 0 +OP4 E005DD 0 +OP4 E005DE 0 +OP4 E005DF 0 +OP4 E005E0 0 +OP4 E005E1 0 +OP4 E005E2 0 +OP4 E005E3 0 +OP4 E005E4 0 +OP4 E005E5 0 +OP4 E005E6 0 +OP4 E005E7 0 +OP4 E005E8 0 +OP4 E005E9 0 +OP4 E005EA 0 +OP4 E005EB 0 +OP4 E005EC 0 +OP4 E005ED 0 +OP4 E005EE 0 +OP4 E005EF 0 +OP4 E005F0 0 +OP4 E005F1 0 +OP4 E005F2 0 +OP4 E005F3 0 +OP4 E005F4 0 +OP4 E005F5 0 +OP4 E005F6 0 +OP4 E005F7 0 +OP4 E005F8 0 +OP4 E005F9 0 +OP4 E005FA 0 +OP4 E005FB 0 +OP4 E005FC 0 +OP4 E005FD 0 +OP4 E005FE 0 +OP4 E005FF 0 +OP4 E00600 0 +OP4 E00601 0 +OP4 E00602 0 +OP4 E00603 0 +OP4 E00604 0 +OP4 E00605 0 +OP4 E00606 0 +OP4 E00607 0 +OP4 E00608 0 +OP4 E00609 0 +OP4 E0060A 0 +OP4 E0060B 0 +OP4 E0060C 0 +OP4 E0060D 0 +OP4 E0060E 0 +OP4 E0060F 0 +OP4 E00610 0 +OP4 E00611 0 +OP4 E00612 0 +OP4 E00613 0 +OP4 E00614 0 +OP4 E00615 0 +OP4 E00616 0 +OP4 E00617 0 +OP4 E00618 0 +OP4 E00619 0 +OP4 E0061A 0 +OP4 E0061B 0 +OP4 E0061C 0 +OP4 E0061D 0 +OP4 E0061E 0 +OP4 E0061F 0 +OP4 E00620 0 +OP4 E00621 0 +OP4 E00622 0 +OP4 E00623 0 +OP4 E00624 0 +OP4 E00625 0 +OP4 E00626 0 +OP4 E00627 0 +OP4 E00628 0 +OP4 E00629 0 +OP4 E0062A 0 +OP4 E0062B 0 +OP4 E0062C 0 +OP4 E0062D 0 +OP4 E0062E 0 +OP4 E0062F 0 +OP4 E00630 0 +OP4 E00631 0 +OP4 E00632 0 +OP4 E00633 0 +OP4 E00634 0 +OP4 E00635 0 +OP4 E00636 0 +OP4 E00637 0 +OP4 E00638 0 +OP4 E00639 0 +OP4 E0063A 0 +OP4 E0063B 0 +OP4 E0063C 0 +OP4 E0063D 0 +OP4 E0063E 0 +OP4 E0063F 0 +OP4 E00640 0 +OP4 E00641 0 +OP4 E00642 0 +OP4 E00643 0 +OP4 E00644 0 +OP4 E00645 0 +OP4 E00646 0 +OP4 E00647 0 +OP4 E00648 0 +OP4 E00649 0 +OP4 E0064A 0 +OP4 E0064B 0 +OP4 E0064C 0 +OP4 E0064D 0 +OP4 E0064E 0 +OP4 E0064F 0 +OP4 E00650 0 +OP4 E00651 0 +OP4 E00652 0 +OP4 E00653 0 +OP4 E00654 0 +OP4 E00655 0 +OP4 E00656 0 +OP4 E00657 0 +OP4 E00658 0 +OP4 E00659 0 +OP4 E0065A 0 +OP4 E0065B 0 +OP4 E0065C 0 +OP4 E0065D 0 +OP4 E0065E 0 +OP4 E0065F 0 +OP4 E00660 0 +OP4 E00661 0 +OP4 E00662 0 +OP4 E00663 0 +OP4 E00664 0 +OP4 E00665 0 +OP4 E00666 0 +OP4 E00667 0 +OP4 E00668 0 +OP4 E00669 0 +OP4 E0066A 0 +OP4 E0066B 0 +OP4 E0066C 0 +OP4 E0066D 0 +OP4 E0066E 0 +OP4 E0066F 0 +OP4 E00670 0 +OP4 E00671 0 +OP4 E00672 0 +OP4 E00673 0 +OP4 E00674 0 +OP4 E00675 0 +OP4 E00676 0 +OP4 E00677 0 +OP4 E00678 0 +OP4 E00679 0 +OP4 E0067A 0 +OP4 E0067B 0 +OP4 E0067C 0 +OP4 E0067D 0 +OP4 E0067E 0 +OP4 E0067F 0 +OP4 E00680 0 +OP4 E00681 0 +OP4 E00682 0 +OP4 E00683 0 +OP4 E00684 0 +OP4 E00685 0 +OP4 E00686 0 +OP4 E00687 0 +OP4 E00688 0 +OP4 E00689 0 +OP4 E0068A 0 +OP4 E0068B 0 +OP4 E0068C 0 +OP4 E0068D 0 +OP4 E0068E 0 +OP4 E0068F 0 +OP4 E00690 0 +OP4 E00691 0 +OP4 E00692 0 +OP4 E00693 0 +OP4 E00694 0 +OP4 E00695 0 +OP4 E00696 0 +OP4 E00697 0 +OP4 E00698 0 +OP4 E00699 0 +OP4 E0069A 0 +OP4 E0069B 0 +OP4 E0069C 0 +OP4 E0069D 0 +OP4 E0069E 0 +OP4 E0069F 0 +OP4 E006A0 0 +OP4 E006A1 0 +OP4 E006A2 0 +OP4 E006A3 0 +OP4 E006A4 0 +OP4 E006A5 0 +OP4 E006A6 0 +OP4 E006A7 0 +OP4 E006A8 0 +OP4 E006A9 0 +OP4 E006AA 0 +OP4 E006AB 0 +OP4 E006AC 0 +OP4 E006AD 0 +OP4 E006AE 0 +OP4 E006AF 0 +OP4 E006B0 0 +OP4 E006B1 0 +OP4 E006B2 0 +OP4 E006B3 0 +OP4 E006B4 0 +OP4 E006B5 0 +OP4 E006B6 0 +OP4 E006B7 0 +OP4 E006B8 0 +OP4 E006B9 0 +OP4 E006BA 0 +OP4 E006BB 0 +OP4 E006BC 0 +OP4 E006BD 0 +OP4 E006BE 0 +OP4 E006BF 0 +OP4 E006C0 0 +OP4 E006C1 0 +OP4 E006C2 0 +OP4 E006C3 0 +OP4 E006C4 0 +OP4 E006C5 0 +OP4 E006C6 0 +OP4 E006C7 0 +OP4 E006C8 0 +OP4 E006C9 0 +OP4 E006CA 0 +OP4 E006CB 0 +OP4 E006CC 0 +OP4 E006CD 0 +OP4 E006CE 0 +OP4 E006CF 0 +OP4 E006D0 0 +OP4 E006D1 0 +OP4 E006D2 0 +OP4 E006D3 0 +OP4 E006D4 0 +OP4 E006D5 0 +OP4 E006D6 0 +OP4 E006D7 0 +OP4 E006D8 0 +OP4 E006D9 0 +OP4 E006DA 0 +OP4 E006DB 0 +OP4 E006DC 0 +OP4 E006DD 0 +OP4 E006DE 0 +OP4 E006DF 0 +OP4 E006E0 0 +OP4 E006E1 0 +OP4 E006E2 0 +OP4 E006E3 0 +OP4 E006E4 0 +OP4 E006E5 0 +OP4 E006E6 0 +OP4 E006E7 0 +OP4 E006E8 0 +OP4 E006E9 0 +OP4 E006EA 0 +OP4 E006EB 0 +OP4 E006EC 0 +OP4 E006ED 0 +OP4 E006EE 0 +OP4 E006EF 0 +OP4 E006F0 0 +OP4 E006F1 0 +OP4 E006F2 0 +OP4 E006F3 0 +OP4 E006F4 0 +OP4 E006F5 0 +OP4 E006F6 0 +OP4 E006F7 0 +OP4 E006F8 0 +OP4 E006F9 0 +OP4 E006FA 0 +OP4 E006FB 0 +OP4 E006FC 0 +OP4 E006FD 0 +OP4 E006FE 0 +OP4 E006FF 0 +OP4 E00700 0 +OP4 E00701 0 +OP4 E00702 0 +OP4 E00703 0 +OP4 E00704 0 +OP4 E00705 0 +OP4 E00706 0 +OP4 E00707 0 +OP4 E00708 0 +OP4 E00709 0 +OP4 E0070A 0 +OP4 E0070B 0 +OP4 E0070C 0 +OP4 E0070D 0 +OP4 E0070E 0 +OP4 E0070F 0 +OP4 E00710 0 +OP4 E00711 0 +OP4 E00712 0 +OP4 E00713 0 +OP4 E00714 0 +OP4 E00715 0 +OP4 E00716 0 +OP4 E00717 0 +OP4 E00718 0 +OP4 E00719 0 +OP4 E0071A 0 +OP4 E0071B 0 +OP4 E0071C 0 +OP4 E0071D 0 +OP4 E0071E 0 +OP4 E0071F 0 +OP4 E00720 0 +OP4 E00721 0 +OP4 E00722 0 +OP4 E00723 0 +OP4 E00724 0 +OP4 E00725 0 +OP4 E00726 0 +OP4 E00727 0 +OP4 E00728 0 +OP4 E00729 0 +OP4 E0072A 0 +OP4 E0072B 0 +OP4 E0072C 0 +OP4 E0072D 0 +OP4 E0072E 0 +OP4 E0072F 0 +OP4 E00730 0 +OP4 E00731 0 +OP4 E00732 0 +OP4 E00733 0 +OP4 E00734 0 +OP4 E00735 0 +OP4 E00736 0 +OP4 E00737 0 +OP4 E00738 0 +OP4 E00739 0 +OP4 E0073A 0 +OP4 E0073B 0 +OP4 E0073C 0 +OP4 E0073D 0 +OP4 E0073E 0 +OP4 E0073F 0 +OP4 E00740 0 +OP4 E00741 0 +OP4 E00742 0 +OP4 E00743 0 +OP4 E00744 0 +OP4 E00745 0 +OP4 E00746 0 +OP4 E00747 0 +OP4 E00748 0 +OP4 E00749 0 +OP4 E0074A 0 +OP4 E0074B 0 +OP4 E0074C 0 +OP4 E0074D 0 +OP4 E0074E 0 +OP4 E0074F 0 +OP4 E00750 0 +OP4 E00751 0 +OP4 E00752 0 +OP4 E00753 0 +OP4 E00754 0 +OP4 E00755 0 +OP4 E00756 0 +OP4 E00757 0 +OP4 E00758 0 +OP4 E00759 0 +OP4 E0075A 0 +OP4 E0075B 0 +OP4 E0075C 0 +OP4 E0075D 0 +OP4 E0075E 0 +OP4 E0075F 0 +OP4 E00760 0 +OP4 E00761 0 +OP4 E00762 0 +OP4 E00763 0 +OP4 E00764 0 +OP4 E00765 0 +OP4 E00766 0 +OP4 E00767 0 +OP4 E00768 0 +OP4 E00769 0 +OP4 E0076A 0 +OP4 E0076B 0 +OP4 E0076C 0 +OP4 E0076D 0 +OP4 E0076E 0 +OP4 E0076F 0 +OP4 E00770 0 +OP4 E00771 0 +OP4 E00772 0 +OP4 E00773 0 +OP4 E00774 0 +OP4 E00775 0 +OP4 E00776 0 +OP4 E00777 0 +OP4 E00778 0 +OP4 E00779 0 +OP4 E0077A 0 +OP4 E0077B 0 +OP4 E0077C 0 +OP4 E0077D 0 +OP4 E0077E 0 +OP4 E0077F 0 +OP4 E00780 0 +OP4 E00781 0 +OP4 E00782 0 +OP4 E00783 0 +OP4 E00784 0 +OP4 E00785 0 +OP4 E00786 0 +OP4 E00787 0 +OP4 E00788 0 +OP4 E00789 0 +OP4 E0078A 0 +OP4 E0078B 0 +OP4 E0078C 0 +OP4 E0078D 0 +OP4 E0078E 0 +OP4 E0078F 0 +OP4 E00790 0 +OP4 E00791 0 +OP4 E00792 0 +OP4 E00793 0 +OP4 E00794 0 +OP4 E00795 0 +OP4 E00796 0 +OP4 E00797 0 +OP4 E00798 0 +OP4 E00799 0 +OP4 E0079A 0 +OP4 E0079B 0 +OP4 E0079C 0 +OP4 E0079D 0 +OP4 E0079E 0 +OP4 E0079F 0 +OP4 E007A0 0 +OP4 E007A1 0 +OP4 E007A2 0 +OP4 E007A3 0 +OP4 E007A4 0 +OP4 E007A5 0 +OP4 E007A6 0 +OP4 E007A7 0 +OP4 E007A8 0 +OP4 E007A9 0 +OP4 E007AA 0 +OP4 E007AB 0 +OP4 E007AC 0 +OP4 E007AD 0 +OP4 E007AE 0 +OP4 E007AF 0 +OP4 E007B0 0 +OP4 E007B1 0 +OP4 E007B2 0 +OP4 E007B3 0 +OP4 E007B4 0 +OP4 E007B5 0 +OP4 E007B6 0 +OP4 E007B7 0 +OP4 E007B8 0 +OP4 E007B9 0 +OP4 E007BA 0 +OP4 E007BB 0 +OP4 E007BC 0 +OP4 E007BD 0 +OP4 E007BE 0 +OP4 E007BF 0 +OP4 E007C0 0 +OP4 E007C1 0 +OP4 E007C2 0 +OP4 E007C3 0 +OP4 E007C4 0 +OP4 E007C5 0 +OP4 E007C6 0 +OP4 E007C7 0 +OP4 E007C8 0 +OP4 E007C9 0 +OP4 E007CA 0 +OP4 E007CB 0 +OP4 E007CC 0 +OP4 E007CD 0 +OP4 E007CE 0 +OP4 E007CF 0 +OP4 E007D0 0 +OP4 E007D1 0 +OP4 E007D2 0 +OP4 E007D3 0 +OP4 E007D4 0 +OP4 E007D5 0 +OP4 E007D6 0 +OP4 E007D7 0 +OP4 E007D8 0 +OP4 E007D9 0 +OP4 E007DA 0 +OP4 E007DB 0 +OP4 E007DC 0 +OP4 E007DD 0 +OP4 E007DE 0 +OP4 E007DF 0 +OP4 E007E0 0 +OP4 E007E1 0 +OP4 E007E2 0 +OP4 E007E3 0 +OP4 E007E4 0 +OP4 E007E5 0 +OP4 E007E6 0 +OP4 E007E7 0 +OP4 E007E8 0 +OP4 E007E9 0 +OP4 E007EA 0 +OP4 E007EB 0 +OP4 E007EC 0 +OP4 E007ED 0 +OP4 E007EE 0 +OP4 E007EF 0 +OP4 E007F0 0 +OP4 E007F1 0 +OP4 E007F2 0 +OP4 E007F3 0 +OP4 E007F4 0 +OP4 E007F5 0 +OP4 E007F6 0 +OP4 E007F7 0 +OP4 E007F8 0 +OP4 E007F9 0 +OP4 E007FA 0 +OP4 E007FB 0 +OP4 E007FC 0 +OP4 E007FD 0 +OP4 E007FE 0 +OP4 E007FF 0 +OP4 E00800 0 +OP4 E00801 0 +OP4 E00802 0 +OP4 E00803 0 +OP4 E00804 0 +OP4 E00805 0 +OP4 E00806 0 +OP4 E00807 0 +OP4 E00808 0 +OP4 E00809 0 +OP4 E0080A 0 +OP4 E0080B 0 +OP4 E0080C 0 +OP4 E0080D 0 +OP4 E0080E 0 +OP4 E0080F 0 +OP4 E00810 0 +OP4 E00811 0 +OP4 E00812 0 +OP4 E00813 0 +OP4 E00814 0 +OP4 E00815 0 +OP4 E00816 0 +OP4 E00817 0 +OP4 E00818 0 +OP4 E00819 0 +OP4 E0081A 0 +OP4 E0081B 0 +OP4 E0081C 0 +OP4 E0081D 0 +OP4 E0081E 0 +OP4 E0081F 0 +OP4 E00820 0 +OP4 E00821 0 +OP4 E00822 0 +OP4 E00823 0 +OP4 E00824 0 +OP4 E00825 0 +OP4 E00826 0 +OP4 E00827 0 +OP4 E00828 0 +OP4 E00829 0 +OP4 E0082A 0 +OP4 E0082B 0 +OP4 E0082C 0 +OP4 E0082D 0 +OP4 E0082E 0 +OP4 E0082F 0 +OP4 E00830 0 +OP4 E00831 0 +OP4 E00832 0 +OP4 E00833 0 +OP4 E00834 0 +OP4 E00835 0 +OP4 E00836 0 +OP4 E00837 0 +OP4 E00838 0 +OP4 E00839 0 +OP4 E0083A 0 +OP4 E0083B 0 +OP4 E0083C 0 +OP4 E0083D 0 +OP4 E0083E 0 +OP4 E0083F 0 +OP4 E00840 0 +OP4 E00841 0 +OP4 E00842 0 +OP4 E00843 0 +OP4 E00844 0 +OP4 E00845 0 +OP4 E00846 0 +OP4 E00847 0 +OP4 E00848 0 +OP4 E00849 0 +OP4 E0084A 0 +OP4 E0084B 0 +OP4 E0084C 0 +OP4 E0084D 0 +OP4 E0084E 0 +OP4 E0084F 0 +OP4 E00850 0 +OP4 E00851 0 +OP4 E00852 0 +OP4 E00853 0 +OP4 E00854 0 +OP4 E00855 0 +OP4 E00856 0 +OP4 E00857 0 +OP4 E00858 0 +OP4 E00859 0 +OP4 E0085A 0 +OP4 E0085B 0 +OP4 E0085C 0 +OP4 E0085D 0 +OP4 E0085E 0 +OP4 E0085F 0 +OP4 E00860 0 +OP4 E00861 0 +OP4 E00862 0 +OP4 E00863 0 +OP4 E00864 0 +OP4 E00865 0 +OP4 E00866 0 +OP4 E00867 0 +OP4 E00868 0 +OP4 E00869 0 +OP4 E0086A 0 +OP4 E0086B 0 +OP4 E0086C 0 +OP4 E0086D 0 +OP4 E0086E 0 +OP4 E0086F 0 +OP4 E00870 0 +OP4 E00871 0 +OP4 E00872 0 +OP4 E00873 0 +OP4 E00874 0 +OP4 E00875 0 +OP4 E00876 0 +OP4 E00877 0 +OP4 E00878 0 +OP4 E00879 0 +OP4 E0087A 0 +OP4 E0087B 0 +OP4 E0087C 0 +OP4 E0087D 0 +OP4 E0087E 0 +OP4 E0087F 0 +OP4 E00880 0 +OP4 E00881 0 +OP4 E00882 0 +OP4 E00883 0 +OP4 E00884 0 +OP4 E00885 0 +OP4 E00886 0 +OP4 E00887 0 +OP4 E00888 0 +OP4 E00889 0 +OP4 E0088A 0 +OP4 E0088B 0 +OP4 E0088C 0 +OP4 E0088D 0 +OP4 E0088E 0 +OP4 E0088F 0 +OP4 E00890 0 +OP4 E00891 0 +OP4 E00892 0 +OP4 E00893 0 +OP4 E00894 0 +OP4 E00895 0 +OP4 E00896 0 +OP4 E00897 0 +OP4 E00898 0 +OP4 E00899 0 +OP4 E0089A 0 +OP4 E0089B 0 +OP4 E0089C 0 +OP4 E0089D 0 +OP4 E0089E 0 +OP4 E0089F 0 +OP4 E008A0 0 +OP4 E008A1 0 +OP4 E008A2 0 +OP4 E008A3 0 +OP4 E008A4 0 +OP4 E008A5 0 +OP4 E008A6 0 +OP4 E008A7 0 +OP4 E008A8 0 +OP4 E008A9 0 +OP4 E008AA 0 +OP4 E008AB 0 +OP4 E008AC 0 +OP4 E008AD 0 +OP4 E008AE 0 +OP4 E008AF 0 +OP4 E008B0 0 +OP4 E008B1 0 +OP4 E008B2 0 +OP4 E008B3 0 +OP4 E008B4 0 +OP4 E008B5 0 +OP4 E008B6 0 +OP4 E008B7 0 +OP4 E008B8 0 +OP4 E008B9 0 +OP4 E008BA 0 +OP4 E008BB 0 +OP4 E008BC 0 +OP4 E008BD 0 +OP4 E008BE 0 +OP4 E008BF 0 +OP4 E008C0 0 +OP4 E008C1 0 +OP4 E008C2 0 +OP4 E008C3 0 +OP4 E008C4 0 +OP4 E008C5 0 +OP4 E008C6 0 +OP4 E008C7 0 +OP4 E008C8 0 +OP4 E008C9 0 +OP4 E008CA 0 +OP4 E008CB 0 +OP4 E008CC 0 +OP4 E008CD 0 +OP4 E008CE 0 +OP4 E008CF 0 +OP4 E008D0 0 +OP4 E008D1 0 +OP4 E008D2 0 +OP4 E008D3 0 +OP4 E008D4 0 +OP4 E008D5 0 +OP4 E008D6 0 +OP4 E008D7 0 +OP4 E008D8 0 +OP4 E008D9 0 +OP4 E008DA 0 +OP4 E008DB 0 +OP4 E008DC 0 +OP4 E008DD 0 +OP4 E008DE 0 +OP4 E008DF 0 +OP4 E008E0 0 +OP4 E008E1 0 +OP4 E008E2 0 +OP4 E008E3 0 +OP4 E008E4 0 +OP4 E008E5 0 +OP4 E008E6 0 +OP4 E008E7 0 +OP4 E008E8 0 +OP4 E008E9 0 +OP4 E008EA 0 +OP4 E008EB 0 +OP4 E008EC 0 +OP4 E008ED 0 +OP4 E008EE 0 +OP4 E008EF 0 +OP4 E008F0 0 +OP4 E008F1 0 +OP4 E008F2 0 +OP4 E008F3 0 +OP4 E008F4 0 +OP4 E008F5 0 +OP4 E008F6 0 +OP4 E008F7 0 +OP4 E008F8 0 +OP4 E008F9 0 +OP4 E008FA 0 +OP4 E008FB 0 +OP4 E008FC 0 +OP4 E008FD 0 +OP4 E008FE 0 +OP4 E008FF 0 +OP4 E00900 0 +OP4 E00901 0 +OP4 E00902 0 +OP4 E00903 0 +OP4 E00904 0 +OP4 E00905 0 +OP4 E00906 0 +OP4 E00907 0 +OP4 E00908 0 +OP4 E00909 0 +OP4 E0090A 0 +OP4 E0090B 0 +OP4 E0090C 0 +OP4 E0090D 0 +OP4 E0090E 0 +OP4 E0090F 0 +OP4 E00910 0 +OP4 E00911 0 +OP4 E00912 0 +OP4 E00913 0 +OP4 E00914 0 +OP4 E00915 0 +OP4 E00916 0 +OP4 E00917 0 +OP4 E00918 0 +OP4 E00919 0 +OP4 E0091A 0 +OP4 E0091B 0 +OP4 E0091C 0 +OP4 E0091D 0 +OP4 E0091E 0 +OP4 E0091F 0 +OP4 E00920 0 +OP4 E00921 0 +OP4 E00922 0 +OP4 E00923 0 +OP4 E00924 0 +OP4 E00925 0 +OP4 E00926 0 +OP4 E00927 0 +OP4 E00928 0 +OP4 E00929 0 +OP4 E0092A 0 +OP4 E0092B 0 +OP4 E0092C 0 +OP4 E0092D 0 +OP4 E0092E 0 +OP4 E0092F 0 +OP4 E00930 0 +OP4 E00931 0 +OP4 E00932 0 +OP4 E00933 0 +OP4 E00934 0 +OP4 E00935 0 +OP4 E00936 0 +OP4 E00937 0 +OP4 E00938 0 +OP4 E00939 0 +OP4 E0093A 0 +OP4 E0093B 0 +OP4 E0093C 0 +OP4 E0093D 0 +OP4 E0093E 0 +OP4 E0093F 0 +OP4 E00940 0 +OP4 E00941 0 +OP4 E00942 0 +OP4 E00943 0 +OP4 E00944 0 +OP4 E00945 0 +OP4 E00946 0 +OP4 E00947 0 +OP4 E00948 0 +OP4 E00949 0 +OP4 E0094A 0 +OP4 E0094B 0 +OP4 E0094C 0 +OP4 E0094D 0 +OP4 E0094E 0 +OP4 E0094F 0 +OP4 E00950 0 +OP4 E00951 0 +OP4 E00952 0 +OP4 E00953 0 +OP4 E00954 0 +OP4 E00955 0 +OP4 E00956 0 +OP4 E00957 0 +OP4 E00958 0 +OP4 E00959 0 +OP4 E0095A 0 +OP4 E0095B 0 +OP4 E0095C 0 +OP4 E0095D 0 +OP4 E0095E 0 +OP4 E0095F 0 +OP4 E00960 0 +OP4 E00961 0 +OP4 E00962 0 +OP4 E00963 0 +OP4 E00964 0 +OP4 E00965 0 +OP4 E00966 0 +OP4 E00967 0 +OP4 E00968 0 +OP4 E00969 0 +OP4 E0096A 0 +OP4 E0096B 0 +OP4 E0096C 0 +OP4 E0096D 0 +OP4 E0096E 0 +OP4 E0096F 0 +OP4 E00970 0 +OP4 E00971 0 +OP4 E00972 0 +OP4 E00973 0 +OP4 E00974 0 +OP4 E00975 0 +OP4 E00976 0 +OP4 E00977 0 +OP4 E00978 0 +OP4 E00979 0 +OP4 E0097A 0 +OP4 E0097B 0 +OP4 E0097C 0 +OP4 E0097D 0 +OP4 E0097E 0 +OP4 E0097F 0 +OP4 E00980 0 +OP4 E00981 0 +OP4 E00982 0 +OP4 E00983 0 +OP4 E00984 0 +OP4 E00985 0 +OP4 E00986 0 +OP4 E00987 0 +OP4 E00988 0 +OP4 E00989 0 +OP4 E0098A 0 +OP4 E0098B 0 +OP4 E0098C 0 +OP4 E0098D 0 +OP4 E0098E 0 +OP4 E0098F 0 +OP4 E00990 0 +OP4 E00991 0 +OP4 E00992 0 +OP4 E00993 0 +OP4 E00994 0 +OP4 E00995 0 +OP4 E00996 0 +OP4 E00997 0 +OP4 E00998 0 +OP4 E00999 0 +OP4 E0099A 0 +OP4 E0099B 0 +OP4 E0099C 0 +OP4 E0099D 0 +OP4 E0099E 0 +OP4 E0099F 0 +OP4 E009A0 0 +OP4 E009A1 0 +OP4 E009A2 0 +OP4 E009A3 0 +OP4 E009A4 0 +OP4 E009A5 0 +OP4 E009A6 0 +OP4 E009A7 0 +OP4 E009A8 0 +OP4 E009A9 0 +OP4 E009AA 0 +OP4 E009AB 0 +OP4 E009AC 0 +OP4 E009AD 0 +OP4 E009AE 0 +OP4 E009AF 0 +OP4 E009B0 0 +OP4 E009B1 0 +OP4 E009B2 0 +OP4 E009B3 0 +OP4 E009B4 0 +OP4 E009B5 0 +OP4 E009B6 0 +OP4 E009B7 0 +OP4 E009B8 0 +OP4 E009B9 0 +OP4 E009BA 0 +OP4 E009BB 0 +OP4 E009BC 0 +OP4 E009BD 0 +OP4 E009BE 0 +OP4 E009BF 0 +OP4 E009C0 0 +OP4 E009C1 0 +OP4 E009C2 0 +OP4 E009C3 0 +OP4 E009C4 0 +OP4 E009C5 0 +OP4 E009C6 0 +OP4 E009C7 0 +OP4 E009C8 0 +OP4 E009C9 0 +OP4 E009CA 0 +OP4 E009CB 0 +OP4 E009CC 0 +OP4 E009CD 0 +OP4 E009CE 0 +OP4 E009CF 0 +OP4 E009D0 0 +OP4 E009D1 0 +OP4 E009D2 0 +OP4 E009D3 0 +OP4 E009D4 0 +OP4 E009D5 0 +OP4 E009D6 0 +OP4 E009D7 0 +OP4 E009D8 0 +OP4 E009D9 0 +OP4 E009DA 0 +OP4 E009DB 0 +OP4 E009DC 0 +OP4 E009DD 0 +OP4 E009DE 0 +OP4 E009DF 0 +OP4 E009E0 0 +OP4 E009E1 0 +OP4 E009E2 0 +OP4 E009E3 0 +OP4 E009E4 0 +OP4 E009E5 0 +OP4 E009E6 0 +OP4 E009E7 0 +OP4 E009E8 0 +OP4 E009E9 0 +OP4 E009EA 0 +OP4 E009EB 0 +OP4 E009EC 0 +OP4 E009ED 0 +OP4 E009EE 0 +OP4 E009EF 0 +OP4 E009F0 0 +OP4 E009F1 0 +OP4 E009F2 0 +OP4 E009F3 0 +OP4 E009F4 0 +OP4 E009F5 0 +OP4 E009F6 0 +OP4 E009F7 0 +OP4 E009F8 0 +OP4 E009F9 0 +OP4 E009FA 0 +OP4 E009FB 0 +OP4 E009FC 0 +OP4 E009FD 0 +OP4 E009FE 0 +OP4 E009FF 0 +OP4 E00A00 0 +OP4 E00A01 0 +OP4 E00A02 0 +OP4 E00A03 0 +OP4 E00A04 0 +OP4 E00A05 0 +OP4 E00A06 0 +OP4 E00A07 0 +OP4 E00A08 0 diff --git a/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum3_itrace.cfg.ext b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum3_itrace.cfg.ext new file mode 100644 index 000000000000..14ee84c82970 --- /dev/null +++ b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum3_itrace.cfg.ext @@ -0,0 +1,3890 @@ +OP1 Spectrum3 +OP4 ITRACE0 1 +OP4 ITRACE1 1 +OP4 ITRACE2 1 +OP4 ITRACE3 1 +OP4 ITRACE4 1 +OP4 ITRACE5 1 +OP4 ITRACE6 1 +OP4 ITRACE7 1 +OP4 ITRACE8 1 +OP4 ITRACE9 1 +OP4 Main_PhyUC 0 +OP4 TILE0_ITRACE0 0 +OP4 TILE0_ITRACE1 0 +OP4 TILE0_ITRACE2 0 +OP4 TILE0_ITRACE3 0 +OP4 TILE0_ITRACE4 0 +OP4 TILE0_PhyUC 0 +OP4 TILE1_ITRACE0 0 +OP4 TILE1_ITRACE1 0 +OP4 TILE1_ITRACE2 0 +OP4 TILE1_ITRACE3 0 +OP4 TILE1_ITRACE4 0 +OP4 TILE1_PhyUC 0 +OP4 TILE2_ITRACE0 0 +OP4 TILE2_ITRACE1 0 +OP4 TILE2_ITRACE2 0 +OP4 TILE2_ITRACE3 0 +OP4 TILE2_ITRACE4 0 +OP4 TILE2_PhyUC 0 +OP4 TILE3_ITRACE0 0 +OP4 TILE3_ITRACE1 0 +OP4 TILE3_ITRACE2 0 +OP4 TILE3_ITRACE3 0 +OP4 TILE3_ITRACE4 0 +OP4 TILE3_PhyUC 0 +OP4 TILE4_ITRACE0 0 +OP4 TILE4_ITRACE1 0 +OP4 TILE4_ITRACE2 0 +OP4 TILE4_ITRACE3 0 +OP4 TILE4_ITRACE4 0 +OP4 TILE4_PhyUC 0 +OP4 TILE5_ITRACE0 0 +OP4 TILE5_ITRACE1 0 +OP4 TILE5_ITRACE2 0 +OP4 TILE5_ITRACE3 0 +OP4 TILE5_ITRACE4 0 +OP4 TILE5_PhyUC 0 +OP4 TILE6_ITRACE0 0 +OP4 TILE6_ITRACE1 0 +OP4 TILE6_ITRACE2 0 +OP4 TILE6_ITRACE3 0 +OP4 TILE6_ITRACE4 0 +OP4 TILE6_PhyUC 0 +OP4 TILE7_ITRACE0 0 +OP4 TILE7_ITRACE1 0 +OP4 TILE7_ITRACE2 0 +OP4 TILE7_ITRACE3 0 +OP4 TILE7_ITRACE4 0 +OP4 TILE7_PhyUC 0 +OP4 E0003B 0 +OP4 E0003C 0 +OP4 E0003D 0 +OP4 E0003E 0 +OP4 E0003F 0 +OP4 E00040 0 +OP4 E00041 0 +OP4 E00042 0 +OP4 E00043 0 +OP4 E00044 0 +OP4 E00045 0 +OP4 E00046 0 +OP4 E00047 0 +OP4 E00048 0 +OP4 E00049 0 +OP4 E0004A 0 +OP4 E0004B 0 +OP4 E0004C 0 +OP4 E0004D 0 +OP4 E0004E 0 +OP4 E0004F 0 +OP4 E00050 0 +OP4 E00051 0 +OP4 E00052 0 +OP4 E00053 0 +OP4 E00054 0 +OP4 E00055 0 +OP4 E00056 0 +OP4 E00057 0 +OP4 E00058 0 +OP4 E00059 0 +OP4 E0005A 0 +OP4 E0005B 0 +OP4 E0005C 0 +OP4 E0005D 0 +OP4 E0005E 0 +OP4 E0005F 0 +OP4 E00060 0 +OP4 E00061 0 +OP4 E00062 0 +OP4 E00063 0 +OP4 E00064 0 +OP4 E00065 0 +OP4 E00066 0 +OP4 E00067 0 +OP4 E00068 0 +OP4 E00069 0 +OP4 E0006A 0 +OP4 E0006B 0 +OP4 E0006C 0 +OP4 E0006D 0 +OP4 E0006E 0 +OP4 E0006F 0 +OP4 E00070 0 +OP4 E00071 0 +OP4 E00072 0 +OP4 E00073 0 +OP4 E00074 0 +OP4 E00075 0 +OP4 E00076 0 +OP4 E00077 0 +OP4 E00078 0 +OP4 E00079 0 +OP4 E0007A 0 +OP4 E0007B 0 +OP4 E0007C 0 +OP4 E0007D 0 +OP4 E0007E 0 +OP4 E0007F 0 +OP4 E00080 0 +OP4 E00081 0 +OP4 E00082 0 +OP4 E00083 0 +OP4 E00084 0 +OP4 E00085 0 +OP4 E00086 0 +OP4 E00087 0 +OP4 E00088 0 +OP4 E00089 0 +OP4 E0008A 0 +OP4 E0008B 0 +OP4 E0008C 0 +OP4 E0008D 0 +OP4 E0008E 0 +OP4 E0008F 0 +OP4 E00090 0 +OP4 E00091 0 +OP4 E00092 0 +OP4 E00093 0 +OP4 E00094 0 +OP4 E00095 0 +OP4 E00096 0 +OP4 E00097 0 +OP4 E00098 0 +OP4 E00099 0 +OP4 E0009A 0 +OP4 E0009B 0 +OP4 E0009C 0 +OP4 E0009D 0 +OP4 E0009E 0 +OP4 E0009F 0 +OP4 E000A0 0 +OP4 E000A1 0 +OP4 E000A2 0 +OP4 E000A3 0 +OP4 E000A4 0 +OP4 E000A5 0 +OP4 E000A6 0 +OP4 E000A7 0 +OP4 E000A8 0 +OP4 E000A9 0 +OP4 E000AA 0 +OP4 E000AB 0 +OP4 E000AC 0 +OP4 E000AD 0 +OP4 E000AE 0 +OP4 E000AF 0 +OP4 E000B0 0 +OP4 E000B1 0 +OP4 E000B2 0 +OP4 E000B3 0 +OP4 E000B4 0 +OP4 E000B5 0 +OP4 E000B6 0 +OP4 E000B7 0 +OP4 E000B8 0 +OP4 E000B9 0 +OP4 E000BA 0 +OP4 E000BB 0 +OP4 E000BC 0 +OP4 E000BD 0 +OP4 E000BE 0 +OP4 E000BF 0 +OP4 E000C0 0 +OP4 E000C1 0 +OP4 E000C2 0 +OP4 E000C3 0 +OP4 E000C4 0 +OP4 E000C5 0 +OP4 E000C6 0 +OP4 E000C7 0 +OP4 E000C8 0 +OP4 E000C9 0 +OP4 E000CA 0 +OP4 E000CB 0 +OP4 E000CC 0 +OP4 E000CD 0 +OP4 E000CE 0 +OP4 E000CF 0 +OP4 E000D0 0 +OP4 E000D1 0 +OP4 E000D2 0 +OP4 E000D3 0 +OP4 E000D4 0 +OP4 E000D5 0 +OP4 E000D6 0 +OP4 E000D7 0 +OP4 E000D8 0 +OP4 E000D9 0 +OP4 E000DA 0 +OP4 E000DB 0 +OP4 E000DC 0 +OP4 E000DD 0 +OP4 E000DE 0 +OP4 E000DF 0 +OP4 E000E0 0 +OP4 E000E1 0 +OP4 E000E2 0 +OP4 E000E3 0 +OP4 E000E4 0 +OP4 E000E5 0 +OP4 E000E6 0 +OP4 E000E7 0 +OP4 E000E8 0 +OP4 E000E9 0 +OP4 E000EA 0 +OP4 E000EB 0 +OP4 E000EC 0 +OP4 E000ED 0 +OP4 E000EE 0 +OP4 E000EF 0 +OP4 E000F0 0 +OP4 E000F1 0 +OP4 E000F2 0 +OP4 E000F3 0 +OP4 E000F4 0 +OP4 E000F5 0 +OP4 E000F6 0 +OP4 E000F7 0 +OP4 E000F8 0 +OP4 E000F9 0 +OP4 E000FA 0 +OP4 E000FB 0 +OP4 E000FC 0 +OP4 E000FD 0 +OP4 E000FE 0 +OP4 E000FF 0 +OP4 E00100 0 +OP4 E00101 0 +OP4 E00102 0 +OP4 E00103 0 +OP4 E00104 0 +OP4 E00105 0 +OP4 E00106 0 +OP4 E00107 0 +OP4 E00108 0 +OP4 E00109 0 +OP4 E0010A 0 +OP4 E0010B 0 +OP4 E0010C 0 +OP4 E0010D 0 +OP4 E0010E 0 +OP4 E0010F 0 +OP4 E00110 0 +OP4 E00111 0 +OP4 E00112 0 +OP4 E00113 0 +OP4 E00114 0 +OP4 E00115 0 +OP4 E00116 0 +OP4 E00117 0 +OP4 E00118 0 +OP4 E00119 0 +OP4 E0011A 0 +OP4 E0011B 0 +OP4 E0011C 0 +OP4 E0011D 0 +OP4 E0011E 0 +OP4 E0011F 0 +OP4 E00120 0 +OP4 E00121 0 +OP4 E00122 0 +OP4 E00123 0 +OP4 E00124 0 +OP4 E00125 0 +OP4 E00126 0 +OP4 E00127 0 +OP4 E00128 0 +OP4 E00129 0 +OP4 E0012A 0 +OP4 E0012B 0 +OP4 E0012C 0 +OP4 E0012D 0 +OP4 E0012E 0 +OP4 E0012F 0 +OP4 E00130 0 +OP4 E00131 0 +OP4 E00132 0 +OP4 E00133 0 +OP4 E00134 0 +OP4 E00135 0 +OP4 E00136 0 +OP4 E00137 0 +OP4 E00138 0 +OP4 E00139 0 +OP4 E0013A 0 +OP4 E0013B 0 +OP4 E0013C 0 +OP4 E0013D 0 +OP4 E0013E 0 +OP4 E0013F 0 +OP4 E00140 0 +OP4 E00141 0 +OP4 E00142 0 +OP4 E00143 0 +OP4 E00144 0 +OP4 E00145 0 +OP4 E00146 0 +OP4 E00147 0 +OP4 E00148 0 +OP4 E00149 0 +OP4 E0014A 0 +OP4 E0014B 0 +OP4 E0014C 0 +OP4 E0014D 0 +OP4 E0014E 0 +OP4 E0014F 0 +OP4 E00150 0 +OP4 E00151 0 +OP4 E00152 0 +OP4 E00153 0 +OP4 E00154 0 +OP4 E00155 0 +OP4 E00156 0 +OP4 E00157 0 +OP4 E00158 0 +OP4 E00159 0 +OP4 E0015A 0 +OP4 E0015B 0 +OP4 E0015C 0 +OP4 E0015D 0 +OP4 E0015E 0 +OP4 E0015F 0 +OP4 E00160 0 +OP4 E00161 0 +OP4 E00162 0 +OP4 E00163 0 +OP4 E00164 0 +OP4 E00165 0 +OP4 E00166 0 +OP4 E00167 0 +OP4 E00168 0 +OP4 E00169 0 +OP4 E0016A 0 +OP4 E0016B 0 +OP4 E0016C 0 +OP4 E0016D 0 +OP4 E0016E 0 +OP4 E0016F 0 +OP4 E00170 0 +OP4 E00171 0 +OP4 E00172 0 +OP4 E00173 0 +OP4 E00174 0 +OP4 E00175 0 +OP4 E00176 0 +OP4 E00177 0 +OP4 E00178 0 +OP4 E00179 0 +OP4 E0017A 0 +OP4 E0017B 0 +OP4 E0017C 0 +OP4 E0017D 0 +OP4 E0017E 0 +OP4 E0017F 0 +OP4 E00180 0 +OP4 E00181 0 +OP4 E00182 0 +OP4 E00183 0 +OP4 E00184 0 +OP4 E00185 0 +OP4 E00186 0 +OP4 E00187 0 +OP4 E00188 0 +OP4 E00189 0 +OP4 E0018A 0 +OP4 E0018B 0 +OP4 E0018C 0 +OP4 E0018D 0 +OP4 E0018E 0 +OP4 E0018F 0 +OP4 E00190 0 +OP4 E00191 0 +OP4 E00192 0 +OP4 E00193 0 +OP4 E00194 0 +OP4 E00195 0 +OP4 E00196 0 +OP4 E00197 0 +OP4 E00198 0 +OP4 E00199 0 +OP4 E0019A 0 +OP4 E0019B 0 +OP4 E0019C 0 +OP4 E0019D 0 +OP4 E0019E 0 +OP4 E0019F 0 +OP4 E001A0 0 +OP4 E001A1 0 +OP4 E001A2 0 +OP4 E001A3 0 +OP4 E001A4 0 +OP4 E001A5 0 +OP4 E001A6 0 +OP4 E001A7 0 +OP4 E001A8 0 +OP4 E001A9 0 +OP4 E001AA 0 +OP4 E001AB 0 +OP4 E001AC 0 +OP4 E001AD 0 +OP4 E001AE 0 +OP4 E001AF 0 +OP4 E001B0 0 +OP4 E001B1 0 +OP4 E001B2 0 +OP4 E001B3 0 +OP4 E001B4 0 +OP4 E001B5 0 +OP4 E001B6 0 +OP4 E001B7 0 +OP4 E001B8 0 +OP4 E001B9 0 +OP4 E001BA 0 +OP4 E001BB 0 +OP4 E001BC 0 +OP4 E001BD 0 +OP4 E001BE 0 +OP4 E001BF 0 +OP4 E001C0 0 +OP4 E001C1 0 +OP4 E001C2 0 +OP4 E001C3 0 +OP4 E001C4 0 +OP4 E001C5 0 +OP4 E001C6 0 +OP4 E001C7 0 +OP4 E001C8 0 +OP4 E001C9 0 +OP4 E001CA 0 +OP4 E001CB 0 +OP4 E001CC 0 +OP4 E001CD 0 +OP4 E001CE 0 +OP4 E001CF 0 +OP4 E001D0 0 +OP4 E001D1 0 +OP4 E001D2 0 +OP4 E001D3 0 +OP4 E001D4 0 +OP4 E001D5 0 +OP4 E001D6 0 +OP4 E001D7 0 +OP4 E001D8 0 +OP4 E001D9 0 +OP4 E001DA 0 +OP4 E001DB 0 +OP4 E001DC 0 +OP4 E001DD 0 +OP4 E001DE 0 +OP4 E001DF 0 +OP4 E001E0 0 +OP4 E001E1 0 +OP4 E001E2 0 +OP4 E001E3 0 +OP4 E001E4 0 +OP4 E001E5 0 +OP4 E001E6 0 +OP4 E001E7 0 +OP4 E001E8 0 +OP4 E001E9 0 +OP4 E001EA 0 +OP4 E001EB 0 +OP4 E001EC 0 +OP4 E001ED 0 +OP4 E001EE 0 +OP4 E001EF 0 +OP4 E001F0 0 +OP4 E001F1 0 +OP4 E001F2 0 +OP4 E001F3 0 +OP4 E001F4 0 +OP4 E001F5 0 +OP4 E001F6 0 +OP4 E001F7 0 +OP4 E001F8 0 +OP4 E001F9 0 +OP4 E001FA 0 +OP4 E001FB 0 +OP4 E001FC 0 +OP4 E001FD 0 +OP4 E001FE 0 +OP4 E001FF 0 +OP4 E00200 0 +OP4 E00201 0 +OP4 E00202 0 +OP4 E00203 0 +OP4 E00204 0 +OP4 E00205 0 +OP4 E00206 0 +OP4 E00207 0 +OP4 E00208 0 +OP4 E00209 0 +OP4 E0020A 0 +OP4 E0020B 0 +OP4 E0020C 0 +OP4 E0020D 0 +OP4 E0020E 0 +OP4 E0020F 0 +OP4 E00210 0 +OP4 E00211 0 +OP4 E00212 0 +OP4 E00213 0 +OP4 E00214 0 +OP4 E00215 0 +OP4 E00216 0 +OP4 E00217 0 +OP4 E00218 0 +OP4 E00219 0 +OP4 E0021A 0 +OP4 E0021B 0 +OP4 E0021C 0 +OP4 E0021D 0 +OP4 E0021E 0 +OP4 E0021F 0 +OP4 E00220 0 +OP4 E00221 0 +OP4 E00222 0 +OP4 E00223 0 +OP4 E00224 0 +OP4 E00225 0 +OP4 E00226 0 +OP4 E00227 0 +OP4 E00228 0 +OP4 E00229 0 +OP4 E0022A 0 +OP4 E0022B 0 +OP4 E0022C 0 +OP4 E0022D 0 +OP4 E0022E 0 +OP4 E0022F 0 +OP4 E00230 0 +OP4 E00231 0 +OP4 E00232 0 +OP4 E00233 0 +OP4 E00234 0 +OP4 E00235 0 +OP4 E00236 0 +OP4 E00237 0 +OP4 E00238 0 +OP4 E00239 0 +OP4 E0023A 0 +OP4 E0023B 0 +OP4 E0023C 0 +OP4 E0023D 0 +OP4 E0023E 0 +OP4 E0023F 0 +OP4 E00240 0 +OP4 E00241 0 +OP4 E00242 0 +OP4 E00243 0 +OP4 E00244 0 +OP4 E00245 0 +OP4 E00246 0 +OP4 E00247 0 +OP4 E00248 0 +OP4 E00249 0 +OP4 E0024A 0 +OP4 E0024B 0 +OP4 E0024C 0 +OP4 E0024D 0 +OP4 E0024E 0 +OP4 E0024F 0 +OP4 E00250 0 +OP4 E00251 0 +OP4 E00252 0 +OP4 E00253 0 +OP4 E00254 0 +OP4 E00255 0 +OP4 E00256 0 +OP4 E00257 0 +OP4 E00258 0 +OP4 E00259 0 +OP4 E0025A 0 +OP4 E0025B 0 +OP4 E0025C 0 +OP4 E0025D 0 +OP4 E0025E 0 +OP4 E0025F 0 +OP4 E00260 0 +OP4 E00261 0 +OP4 E00262 0 +OP4 E00263 0 +OP4 E00264 0 +OP4 E00265 0 +OP4 E00266 0 +OP4 E00267 0 +OP4 E00268 0 +OP4 E00269 0 +OP4 E0026A 0 +OP4 E0026B 0 +OP4 E0026C 0 +OP4 E0026D 0 +OP4 E0026E 0 +OP4 E0026F 0 +OP4 E00270 0 +OP4 E00271 0 +OP4 E00272 0 +OP4 E00273 0 +OP4 E00274 0 +OP4 E00275 0 +OP4 E00276 0 +OP4 E00277 0 +OP4 E00278 0 +OP4 E00279 0 +OP4 E0027A 0 +OP4 E0027B 0 +OP4 E0027C 0 +OP4 E0027D 0 +OP4 E0027E 0 +OP4 E0027F 0 +OP4 E00280 0 +OP4 E00281 0 +OP4 E00282 0 +OP4 E00283 0 +OP4 E00284 0 +OP4 E00285 0 +OP4 E00286 0 +OP4 E00287 0 +OP4 E00288 0 +OP4 E00289 0 +OP4 E0028A 0 +OP4 E0028B 0 +OP4 E0028C 0 +OP4 E0028D 0 +OP4 E0028E 0 +OP4 E0028F 0 +OP4 E00290 0 +OP4 E00291 0 +OP4 E00292 0 +OP4 E00293 0 +OP4 E00294 0 +OP4 E00295 0 +OP4 E00296 0 +OP4 E00297 0 +OP4 E00298 0 +OP4 E00299 0 +OP4 E0029A 0 +OP4 E0029B 0 +OP4 E0029C 0 +OP4 E0029D 0 +OP4 E0029E 0 +OP4 E0029F 0 +OP4 E002A0 0 +OP4 E002A1 0 +OP4 E002A2 0 +OP4 E002A3 0 +OP4 E002A4 0 +OP4 E002A5 0 +OP4 E002A6 0 +OP4 E002A7 0 +OP4 E002A8 0 +OP4 E002A9 0 +OP4 E002AA 0 +OP4 E002AB 0 +OP4 E002AC 0 +OP4 E002AD 0 +OP4 E002AE 0 +OP4 E002AF 0 +OP4 E002B0 0 +OP4 E002B1 0 +OP4 E002B2 0 +OP4 E002B3 0 +OP4 E002B4 0 +OP4 E002B5 0 +OP4 E002B6 0 +OP4 E002B7 0 +OP4 E002B8 0 +OP4 E002B9 0 +OP4 E002BA 0 +OP4 E002BB 0 +OP4 E002BC 0 +OP4 E002BD 0 +OP4 E002BE 0 +OP4 E002BF 0 +OP4 E002C0 0 +OP4 E002C1 0 +OP4 E002C2 0 +OP4 E002C3 0 +OP4 E002C4 0 +OP4 E002C5 0 +OP4 E002C6 0 +OP4 E002C7 0 +OP4 E002C8 0 +OP4 E002C9 0 +OP4 E002CA 0 +OP4 E002CB 0 +OP4 E002CC 0 +OP4 E002CD 0 +OP4 E002CE 0 +OP4 E002CF 0 +OP4 E002D0 0 +OP4 E002D1 0 +OP4 E002D2 0 +OP4 E002D3 0 +OP4 E002D4 0 +OP4 E002D5 0 +OP4 E002D6 0 +OP4 E002D7 0 +OP4 E002D8 0 +OP4 E002D9 0 +OP4 E002DA 0 +OP4 E002DB 0 +OP4 E002DC 0 +OP4 E002DD 0 +OP4 E002DE 0 +OP4 E002DF 0 +OP4 E002E0 0 +OP4 E002E1 0 +OP4 E002E2 0 +OP4 E002E3 0 +OP4 E002E4 0 +OP4 E002E5 0 +OP4 E002E6 0 +OP4 E002E7 0 +OP4 E002E8 0 +OP4 E002E9 0 +OP4 E002EA 0 +OP4 E002EB 0 +OP4 E002EC 0 +OP4 E002ED 0 +OP4 E002EE 0 +OP4 E002EF 0 +OP4 E002F0 0 +OP4 E002F1 0 +OP4 E002F2 0 +OP4 E002F3 0 +OP4 E002F4 0 +OP4 E002F5 0 +OP4 E002F6 0 +OP4 E002F7 0 +OP4 E002F8 0 +OP4 E002F9 0 +OP4 E002FA 0 +OP4 E002FB 0 +OP4 E002FC 0 +OP4 E002FD 0 +OP4 E002FE 0 +OP4 E002FF 0 +OP4 E00300 0 +OP4 E00301 0 +OP4 E00302 0 +OP4 E00303 0 +OP4 E00304 0 +OP4 E00305 0 +OP4 E00306 0 +OP4 E00307 0 +OP4 E00308 0 +OP4 E00309 0 +OP4 E0030A 0 +OP4 E0030B 0 +OP4 E0030C 0 +OP4 E0030D 0 +OP4 E0030E 0 +OP4 E0030F 0 +OP4 E00310 0 +OP4 E00311 0 +OP4 E00312 0 +OP4 E00313 0 +OP4 E00314 0 +OP4 E00315 0 +OP4 E00316 0 +OP4 E00317 0 +OP4 E00318 0 +OP4 E00319 0 +OP4 E0031A 0 +OP4 E0031B 0 +OP4 E0031C 0 +OP4 E0031D 0 +OP4 E0031E 0 +OP4 E0031F 0 +OP4 E00320 0 +OP4 E00321 0 +OP4 E00322 0 +OP4 E00323 0 +OP4 E00324 0 +OP4 E00325 0 +OP4 E00326 0 +OP4 E00327 0 +OP4 E00328 0 +OP4 E00329 0 +OP4 E0032A 0 +OP4 E0032B 0 +OP4 E0032C 0 +OP4 E0032D 0 +OP4 E0032E 0 +OP4 E0032F 0 +OP4 E00330 0 +OP4 E00331 0 +OP4 E00332 0 +OP4 E00333 0 +OP4 E00334 0 +OP4 E00335 0 +OP4 E00336 0 +OP4 E00337 0 +OP4 E00338 0 +OP4 E00339 0 +OP4 E0033A 0 +OP4 E0033B 0 +OP4 E0033C 0 +OP4 E0033D 0 +OP4 E0033E 0 +OP4 E0033F 0 +OP4 E00340 0 +OP4 E00341 0 +OP4 E00342 0 +OP4 E00343 0 +OP4 E00344 0 +OP4 E00345 0 +OP4 E00346 0 +OP4 E00347 0 +OP4 E00348 0 +OP4 E00349 0 +OP4 E0034A 0 +OP4 E0034B 0 +OP4 E0034C 0 +OP4 E0034D 0 +OP4 E0034E 0 +OP4 E0034F 0 +OP4 E00350 0 +OP4 E00351 0 +OP4 E00352 0 +OP4 E00353 0 +OP4 E00354 0 +OP4 E00355 0 +OP4 E00356 0 +OP4 E00357 0 +OP4 E00358 0 +OP4 E00359 0 +OP4 E0035A 0 +OP4 E0035B 0 +OP4 E0035C 0 +OP4 E0035D 0 +OP4 E0035E 0 +OP4 E0035F 0 +OP4 E00360 0 +OP4 E00361 0 +OP4 E00362 0 +OP4 E00363 0 +OP4 E00364 0 +OP4 E00365 0 +OP4 E00366 0 +OP4 E00367 0 +OP4 E00368 0 +OP4 E00369 0 +OP4 E0036A 0 +OP4 E0036B 0 +OP4 E0036C 0 +OP4 E0036D 0 +OP4 E0036E 0 +OP4 E0036F 0 +OP4 E00370 0 +OP4 E00371 0 +OP4 E00372 0 +OP4 E00373 0 +OP4 E00374 0 +OP4 E00375 0 +OP4 E00376 0 +OP4 E00377 0 +OP4 E00378 0 +OP4 E00379 0 +OP4 E0037A 0 +OP4 E0037B 0 +OP4 E0037C 0 +OP4 E0037D 0 +OP4 E0037E 0 +OP4 E0037F 0 +OP4 E00380 0 +OP4 E00381 0 +OP4 E00382 0 +OP4 E00383 0 +OP4 E00384 0 +OP4 E00385 0 +OP4 E00386 0 +OP4 E00387 0 +OP4 E00388 0 +OP4 E00389 0 +OP4 E0038A 0 +OP4 E0038B 0 +OP4 E0038C 0 +OP4 E0038D 0 +OP4 E0038E 0 +OP4 E0038F 0 +OP4 E00390 0 +OP4 E00391 0 +OP4 E00392 0 +OP4 E00393 0 +OP4 E00394 0 +OP4 E00395 0 +OP4 E00396 0 +OP4 E00397 0 +OP4 E00398 0 +OP4 E00399 0 +OP4 E0039A 0 +OP4 E0039B 0 +OP4 E0039C 0 +OP4 E0039D 0 +OP4 E0039E 0 +OP4 E0039F 0 +OP4 E003A0 0 +OP4 E003A1 0 +OP4 E003A2 0 +OP4 E003A3 0 +OP4 E003A4 0 +OP4 E003A5 0 +OP4 E003A6 0 +OP4 E003A7 0 +OP4 E003A8 0 +OP4 E003A9 0 +OP4 E003AA 0 +OP4 E003AB 0 +OP4 E003AC 0 +OP4 E003AD 0 +OP4 E003AE 0 +OP4 E003AF 0 +OP4 E003B0 0 +OP4 E003B1 0 +OP4 E003B2 0 +OP4 E003B3 0 +OP4 E003B4 0 +OP4 E003B5 0 +OP4 E003B6 0 +OP4 E003B7 0 +OP4 E003B8 0 +OP4 E003B9 0 +OP4 E003BA 0 +OP4 E003BB 0 +OP4 E003BC 0 +OP4 E003BD 0 +OP4 E003BE 0 +OP4 E003BF 0 +OP4 E003C0 0 +OP4 E003C1 0 +OP4 E003C2 0 +OP4 E003C3 0 +OP4 E003C4 0 +OP4 E003C5 0 +OP4 E003C6 0 +OP4 E003C7 0 +OP4 E003C8 0 +OP4 E003C9 0 +OP4 E003CA 0 +OP4 E003CB 0 +OP4 E003CC 0 +OP4 E003CD 0 +OP4 E003CE 0 +OP4 E003CF 0 +OP4 E003D0 0 +OP4 E003D1 0 +OP4 E003D2 0 +OP4 E003D3 0 +OP4 E003D4 0 +OP4 E003D5 0 +OP4 E003D6 0 +OP4 E003D7 0 +OP4 E003D8 0 +OP4 E003D9 0 +OP4 E003DA 0 +OP4 E003DB 0 +OP4 E003DC 0 +OP4 E003DD 0 +OP4 E003DE 0 +OP4 E003DF 0 +OP4 E003E0 0 +OP4 E003E1 0 +OP4 E003E2 0 +OP4 E003E3 0 +OP4 E003E4 0 +OP4 E003E5 0 +OP4 E003E6 0 +OP4 E003E7 0 +OP4 E003E8 0 +OP4 E003E9 0 +OP4 E003EA 0 +OP4 E003EB 0 +OP4 E003EC 0 +OP4 E003ED 0 +OP4 E003EE 0 +OP4 E003EF 0 +OP4 E003F0 0 +OP4 E003F1 0 +OP4 E003F2 0 +OP4 E003F3 0 +OP4 E003F4 0 +OP4 E003F5 0 +OP4 E003F6 0 +OP4 E003F7 0 +OP4 E003F8 0 +OP4 E003F9 0 +OP4 E003FA 0 +OP4 E003FB 0 +OP4 E003FC 0 +OP4 E003FD 0 +OP4 E003FE 0 +OP4 E003FF 0 +OP4 E00400 0 +OP4 E00401 0 +OP4 E00402 0 +OP4 E00403 0 +OP4 E00404 0 +OP4 E00405 0 +OP4 E00406 0 +OP4 E00407 0 +OP4 E00408 0 +OP4 E00409 0 +OP4 E0040A 0 +OP4 E0040B 0 +OP4 E0040C 0 +OP4 E0040D 0 +OP4 E0040E 0 +OP4 E0040F 0 +OP4 E00410 0 +OP4 E00411 0 +OP4 E00412 0 +OP4 E00413 0 +OP4 E00414 0 +OP4 E00415 0 +OP4 E00416 0 +OP4 E00417 0 +OP4 E00418 0 +OP4 E00419 0 +OP4 E0041A 0 +OP4 E0041B 0 +OP4 E0041C 0 +OP4 E0041D 0 +OP4 E0041E 0 +OP4 E0041F 0 +OP4 E00420 0 +OP4 E00421 0 +OP4 E00422 0 +OP4 E00423 0 +OP4 E00424 0 +OP4 E00425 0 +OP4 E00426 0 +OP4 E00427 0 +OP4 E00428 0 +OP4 E00429 0 +OP4 E0042A 0 +OP4 E0042B 0 +OP4 E0042C 0 +OP4 E0042D 0 +OP4 E0042E 0 +OP4 E0042F 0 +OP4 E00430 0 +OP4 E00431 0 +OP4 E00432 0 +OP4 E00433 0 +OP4 E00434 0 +OP4 E00435 0 +OP4 E00436 0 +OP4 E00437 0 +OP4 E00438 0 +OP4 E00439 0 +OP4 E0043A 0 +OP4 E0043B 0 +OP4 E0043C 0 +OP4 E0043D 0 +OP4 E0043E 0 +OP4 E0043F 0 +OP4 E00440 0 +OP4 E00441 0 +OP4 E00442 0 +OP4 E00443 0 +OP4 E00444 0 +OP4 E00445 0 +OP4 E00446 0 +OP4 E00447 0 +OP4 E00448 0 +OP4 E00449 0 +OP4 E0044A 0 +OP4 E0044B 0 +OP4 E0044C 0 +OP4 E0044D 0 +OP4 E0044E 0 +OP4 E0044F 0 +OP4 E00450 0 +OP4 E00451 0 +OP4 E00452 0 +OP4 E00453 0 +OP4 E00454 0 +OP4 E00455 0 +OP4 E00456 0 +OP4 E00457 0 +OP4 E00458 0 +OP4 E00459 0 +OP4 E0045A 0 +OP4 E0045B 0 +OP4 E0045C 0 +OP4 E0045D 0 +OP4 E0045E 0 +OP4 E0045F 0 +OP4 E00460 0 +OP4 E00461 0 +OP4 E00462 0 +OP4 E00463 0 +OP4 E00464 0 +OP4 E00465 0 +OP4 E00466 0 +OP4 E00467 0 +OP4 E00468 0 +OP4 E00469 0 +OP4 E0046A 0 +OP4 E0046B 0 +OP4 E0046C 0 +OP4 E0046D 0 +OP4 E0046E 0 +OP4 E0046F 0 +OP4 E00470 0 +OP4 E00471 0 +OP4 E00472 0 +OP4 E00473 0 +OP4 E00474 0 +OP4 E00475 0 +OP4 E00476 0 +OP4 E00477 0 +OP4 E00478 0 +OP4 E00479 0 +OP4 E0047A 0 +OP4 E0047B 0 +OP4 E0047C 0 +OP4 E0047D 0 +OP4 E0047E 0 +OP4 E0047F 0 +OP4 E00480 0 +OP4 E00481 0 +OP4 E00482 0 +OP4 E00483 0 +OP4 E00484 0 +OP4 E00485 0 +OP4 E00486 0 +OP4 E00487 0 +OP4 E00488 0 +OP4 E00489 0 +OP4 E0048A 0 +OP4 E0048B 0 +OP4 E0048C 0 +OP4 E0048D 0 +OP4 E0048E 0 +OP4 E0048F 0 +OP4 E00490 0 +OP4 E00491 0 +OP4 E00492 0 +OP4 E00493 0 +OP4 E00494 0 +OP4 E00495 0 +OP4 E00496 0 +OP4 E00497 0 +OP4 E00498 0 +OP4 E00499 0 +OP4 E0049A 0 +OP4 E0049B 0 +OP4 E0049C 0 +OP4 E0049D 0 +OP4 E0049E 0 +OP4 E0049F 0 +OP4 E004A0 0 +OP4 E004A1 0 +OP4 E004A2 0 +OP4 E004A3 0 +OP4 E004A4 0 +OP4 E004A5 0 +OP4 E004A6 0 +OP4 E004A7 0 +OP4 E004A8 0 +OP4 E004A9 0 +OP4 E004AA 0 +OP4 E004AB 0 +OP4 E004AC 0 +OP4 E004AD 0 +OP4 E004AE 0 +OP4 E004AF 0 +OP4 E004B0 0 +OP4 E004B1 0 +OP4 E004B2 0 +OP4 E004B3 0 +OP4 E004B4 0 +OP4 E004B5 0 +OP4 E004B6 0 +OP4 E004B7 0 +OP4 E004B8 0 +OP4 E004B9 0 +OP4 E004BA 0 +OP4 E004BB 0 +OP4 E004BC 0 +OP4 E004BD 0 +OP4 E004BE 0 +OP4 E004BF 0 +OP4 E004C0 0 +OP4 E004C1 0 +OP4 E004C2 0 +OP4 E004C3 0 +OP4 E004C4 0 +OP4 E004C5 0 +OP4 E004C6 0 +OP4 E004C7 0 +OP4 E004C8 0 +OP4 E004C9 0 +OP4 E004CA 0 +OP4 E004CB 0 +OP4 E004CC 0 +OP4 E004CD 0 +OP4 E004CE 0 +OP4 E004CF 0 +OP4 E004D0 0 +OP4 E004D1 0 +OP4 E004D2 0 +OP4 E004D3 0 +OP4 E004D4 0 +OP4 E004D5 0 +OP4 E004D6 0 +OP4 E004D7 0 +OP4 E004D8 0 +OP4 E004D9 0 +OP4 E004DA 0 +OP4 E004DB 0 +OP4 E004DC 0 +OP4 E004DD 0 +OP4 E004DE 0 +OP4 E004DF 0 +OP4 E004E0 0 +OP4 E004E1 0 +OP4 E004E2 0 +OP4 E004E3 0 +OP4 E004E4 0 +OP4 E004E5 0 +OP4 E004E6 0 +OP4 E004E7 0 +OP4 E004E8 0 +OP4 E004E9 0 +OP4 E004EA 0 +OP4 E004EB 0 +OP4 E004EC 0 +OP4 E004ED 0 +OP4 E004EE 0 +OP4 E004EF 0 +OP4 E004F0 0 +OP4 E004F1 0 +OP4 E004F2 0 +OP4 E004F3 0 +OP4 E004F4 0 +OP4 E004F5 0 +OP4 E004F6 0 +OP4 E004F7 0 +OP4 E004F8 0 +OP4 E004F9 0 +OP4 E004FA 0 +OP4 E004FB 0 +OP4 E004FC 0 +OP4 E004FD 0 +OP4 E004FE 0 +OP4 E004FF 0 +OP4 E00500 0 +OP4 E00501 0 +OP4 E00502 0 +OP4 E00503 0 +OP4 E00504 0 +OP4 E00505 0 +OP4 E00506 0 +OP4 E00507 0 +OP4 E00508 0 +OP4 E00509 0 +OP4 E0050A 0 +OP4 E0050B 0 +OP4 E0050C 0 +OP4 E0050D 0 +OP4 E0050E 0 +OP4 E0050F 0 +OP4 E00510 0 +OP4 E00511 0 +OP4 E00512 0 +OP4 E00513 0 +OP4 E00514 0 +OP4 E00515 0 +OP4 E00516 0 +OP4 E00517 0 +OP4 E00518 0 +OP4 E00519 0 +OP4 E0051A 0 +OP4 E0051B 0 +OP4 E0051C 0 +OP4 E0051D 0 +OP4 E0051E 0 +OP4 E0051F 0 +OP4 E00520 0 +OP4 E00521 0 +OP4 E00522 0 +OP4 E00523 0 +OP4 E00524 0 +OP4 E00525 0 +OP4 E00526 0 +OP4 E00527 0 +OP4 E00528 0 +OP4 E00529 0 +OP4 E0052A 0 +OP4 E0052B 0 +OP4 E0052C 0 +OP4 E0052D 0 +OP4 E0052E 0 +OP4 E0052F 0 +OP4 E00530 0 +OP4 E00531 0 +OP4 E00532 0 +OP4 E00533 0 +OP4 E00534 0 +OP4 E00535 0 +OP4 E00536 0 +OP4 E00537 0 +OP4 E00538 0 +OP4 E00539 0 +OP4 E0053A 0 +OP4 E0053B 0 +OP4 E0053C 0 +OP4 E0053D 0 +OP4 E0053E 0 +OP4 E0053F 0 +OP4 E00540 0 +OP4 E00541 0 +OP4 E00542 0 +OP4 E00543 0 +OP4 E00544 0 +OP4 E00545 0 +OP4 E00546 0 +OP4 E00547 0 +OP4 E00548 0 +OP4 E00549 0 +OP4 E0054A 0 +OP4 E0054B 0 +OP4 E0054C 0 +OP4 E0054D 0 +OP4 E0054E 0 +OP4 E0054F 0 +OP4 E00550 0 +OP4 E00551 0 +OP4 E00552 0 +OP4 E00553 0 +OP4 E00554 0 +OP4 E00555 0 +OP4 E00556 0 +OP4 E00557 0 +OP4 E00558 0 +OP4 E00559 0 +OP4 E0055A 0 +OP4 E0055B 0 +OP4 E0055C 0 +OP4 E0055D 0 +OP4 E0055E 0 +OP4 E0055F 0 +OP4 E00560 0 +OP4 E00561 0 +OP4 E00562 0 +OP4 E00563 0 +OP4 E00564 0 +OP4 E00565 0 +OP4 E00566 0 +OP4 E00567 0 +OP4 E00568 0 +OP4 E00569 0 +OP4 E0056A 0 +OP4 E0056B 0 +OP4 E0056C 0 +OP4 E0056D 0 +OP4 E0056E 0 +OP4 E0056F 0 +OP4 E00570 0 +OP4 E00571 0 +OP4 E00572 0 +OP4 E00573 0 +OP4 E00574 0 +OP4 E00575 0 +OP4 E00576 0 +OP4 E00577 0 +OP4 E00578 0 +OP4 E00579 0 +OP4 E0057A 0 +OP4 E0057B 0 +OP4 E0057C 0 +OP4 E0057D 0 +OP4 E0057E 0 +OP4 E0057F 0 +OP4 E00580 0 +OP4 E00581 0 +OP4 E00582 0 +OP4 E00583 0 +OP4 E00584 0 +OP4 E00585 0 +OP4 E00586 0 +OP4 E00587 0 +OP4 E00588 0 +OP4 E00589 0 +OP4 E0058A 0 +OP4 E0058B 0 +OP4 E0058C 0 +OP4 E0058D 0 +OP4 E0058E 0 +OP4 E0058F 0 +OP4 E00590 0 +OP4 E00591 0 +OP4 E00592 0 +OP4 E00593 0 +OP4 E00594 0 +OP4 E00595 0 +OP4 E00596 0 +OP4 E00597 0 +OP4 E00598 0 +OP4 E00599 0 +OP4 E0059A 0 +OP4 E0059B 0 +OP4 E0059C 0 +OP4 E0059D 0 +OP4 E0059E 0 +OP4 E0059F 0 +OP4 E005A0 0 +OP4 E005A1 0 +OP4 E005A2 0 +OP4 E005A3 0 +OP4 E005A4 0 +OP4 E005A5 0 +OP4 E005A6 0 +OP4 E005A7 0 +OP4 E005A8 0 +OP4 E005A9 0 +OP4 E005AA 0 +OP4 E005AB 0 +OP4 E005AC 0 +OP4 E005AD 0 +OP4 E005AE 0 +OP4 E005AF 0 +OP4 E005B0 0 +OP4 E005B1 0 +OP4 E005B2 0 +OP4 E005B3 0 +OP4 E005B4 0 +OP4 E005B5 0 +OP4 E005B6 0 +OP4 E005B7 0 +OP4 E005B8 0 +OP4 E005B9 0 +OP4 E005BA 0 +OP4 E005BB 0 +OP4 E005BC 0 +OP4 E005BD 0 +OP4 E005BE 0 +OP4 E005BF 0 +OP4 E005C0 0 +OP4 E005C1 0 +OP4 E005C2 0 +OP4 E005C3 0 +OP4 E005C4 0 +OP4 E005C5 0 +OP4 E005C6 0 +OP4 E005C7 0 +OP4 E005C8 0 +OP4 E005C9 0 +OP4 E005CA 0 +OP4 E005CB 0 +OP4 E005CC 0 +OP4 E005CD 0 +OP4 E005CE 0 +OP4 E005CF 0 +OP4 E005D0 0 +OP4 E005D1 0 +OP4 E005D2 0 +OP4 E005D3 0 +OP4 E005D4 0 +OP4 E005D5 0 +OP4 E005D6 0 +OP4 E005D7 0 +OP4 E005D8 0 +OP4 E005D9 0 +OP4 E005DA 0 +OP4 E005DB 0 +OP4 E005DC 0 +OP4 E005DD 0 +OP4 E005DE 0 +OP4 E005DF 0 +OP4 E005E0 0 +OP4 E005E1 0 +OP4 E005E2 0 +OP4 E005E3 0 +OP4 E005E4 0 +OP4 E005E5 0 +OP4 E005E6 0 +OP4 E005E7 0 +OP4 E005E8 0 +OP4 E005E9 0 +OP4 E005EA 0 +OP4 E005EB 0 +OP4 E005EC 0 +OP4 E005ED 0 +OP4 E005EE 0 +OP4 E005EF 0 +OP4 E005F0 0 +OP4 E005F1 0 +OP4 E005F2 0 +OP4 E005F3 0 +OP4 E005F4 0 +OP4 E005F5 0 +OP4 E005F6 0 +OP4 E005F7 0 +OP4 E005F8 0 +OP4 E005F9 0 +OP4 E005FA 0 +OP4 E005FB 0 +OP4 E005FC 0 +OP4 E005FD 0 +OP4 E005FE 0 +OP4 E005FF 0 +OP4 E00600 0 +OP4 E00601 0 +OP4 E00602 0 +OP4 E00603 0 +OP4 E00604 0 +OP4 E00605 0 +OP4 E00606 0 +OP4 E00607 0 +OP4 E00608 0 +OP4 E00609 0 +OP4 E0060A 0 +OP4 E0060B 0 +OP4 E0060C 0 +OP4 E0060D 0 +OP4 E0060E 0 +OP4 E0060F 0 +OP4 E00610 0 +OP4 E00611 0 +OP4 E00612 0 +OP4 E00613 0 +OP4 E00614 0 +OP4 E00615 0 +OP4 E00616 0 +OP4 E00617 0 +OP4 E00618 0 +OP4 E00619 0 +OP4 E0061A 0 +OP4 E0061B 0 +OP4 E0061C 0 +OP4 E0061D 0 +OP4 E0061E 0 +OP4 E0061F 0 +OP4 E00620 0 +OP4 E00621 0 +OP4 E00622 0 +OP4 E00623 0 +OP4 E00624 0 +OP4 E00625 0 +OP4 E00626 0 +OP4 E00627 0 +OP4 E00628 0 +OP4 E00629 0 +OP4 E0062A 0 +OP4 E0062B 0 +OP4 E0062C 0 +OP4 E0062D 0 +OP4 E0062E 0 +OP4 E0062F 0 +OP4 E00630 0 +OP4 E00631 0 +OP4 E00632 0 +OP4 E00633 0 +OP4 E00634 0 +OP4 E00635 0 +OP4 E00636 0 +OP4 E00637 0 +OP4 E00638 0 +OP4 E00639 0 +OP4 E0063A 0 +OP4 E0063B 0 +OP4 E0063C 0 +OP4 E0063D 0 +OP4 E0063E 0 +OP4 E0063F 0 +OP4 E00640 0 +OP4 E00641 0 +OP4 E00642 0 +OP4 E00643 0 +OP4 E00644 0 +OP4 E00645 0 +OP4 E00646 0 +OP4 E00647 0 +OP4 E00648 0 +OP4 E00649 0 +OP4 E0064A 0 +OP4 E0064B 0 +OP4 E0064C 0 +OP4 E0064D 0 +OP4 E0064E 0 +OP4 E0064F 0 +OP4 E00650 0 +OP4 E00651 0 +OP4 E00652 0 +OP4 E00653 0 +OP4 E00654 0 +OP4 E00655 0 +OP4 E00656 0 +OP4 E00657 0 +OP4 E00658 0 +OP4 E00659 0 +OP4 E0065A 0 +OP4 E0065B 0 +OP4 E0065C 0 +OP4 E0065D 0 +OP4 E0065E 0 +OP4 E0065F 0 +OP4 E00660 0 +OP4 E00661 0 +OP4 E00662 0 +OP4 E00663 0 +OP4 E00664 0 +OP4 E00665 0 +OP4 E00666 0 +OP4 E00667 0 +OP4 E00668 0 +OP4 E00669 0 +OP4 E0066A 0 +OP4 E0066B 0 +OP4 E0066C 0 +OP4 E0066D 0 +OP4 E0066E 0 +OP4 E0066F 0 +OP4 E00670 0 +OP4 E00671 0 +OP4 E00672 0 +OP4 E00673 0 +OP4 E00674 0 +OP4 E00675 0 +OP4 E00676 0 +OP4 E00677 0 +OP4 E00678 0 +OP4 E00679 0 +OP4 E0067A 0 +OP4 E0067B 0 +OP4 E0067C 0 +OP4 E0067D 0 +OP4 E0067E 0 +OP4 E0067F 0 +OP4 E00680 0 +OP4 E00681 0 +OP4 E00682 0 +OP4 E00683 0 +OP4 E00684 0 +OP4 E00685 0 +OP4 E00686 0 +OP4 E00687 0 +OP4 E00688 0 +OP4 E00689 0 +OP4 E0068A 0 +OP4 E0068B 0 +OP4 E0068C 0 +OP4 E0068D 0 +OP4 E0068E 0 +OP4 E0068F 0 +OP4 E00690 0 +OP4 E00691 0 +OP4 E00692 0 +OP4 E00693 0 +OP4 E00694 0 +OP4 E00695 0 +OP4 E00696 0 +OP4 E00697 0 +OP4 E00698 0 +OP4 E00699 0 +OP4 E0069A 0 +OP4 E0069B 0 +OP4 E0069C 0 +OP4 E0069D 0 +OP4 E0069E 0 +OP4 E0069F 0 +OP4 E006A0 0 +OP4 E006A1 0 +OP4 E006A2 0 +OP4 E006A3 0 +OP4 E006A4 0 +OP4 E006A5 0 +OP4 E006A6 0 +OP4 E006A7 0 +OP4 E006A8 0 +OP4 E006A9 0 +OP4 E006AA 0 +OP4 E006AB 0 +OP4 E006AC 0 +OP4 E006AD 0 +OP4 E006AE 0 +OP4 E006AF 0 +OP4 E006B0 0 +OP4 E006B1 0 +OP4 E006B2 0 +OP4 E006B3 0 +OP4 E006B4 0 +OP4 E006B5 0 +OP4 E006B6 0 +OP4 E006B7 0 +OP4 E006B8 0 +OP4 E006B9 0 +OP4 E006BA 0 +OP4 E006BB 0 +OP4 E006BC 0 +OP4 E006BD 0 +OP4 E006BE 0 +OP4 E006BF 0 +OP4 E006C0 0 +OP4 E006C1 0 +OP4 E006C2 0 +OP4 E006C3 0 +OP4 E006C4 0 +OP4 E006C5 0 +OP4 E006C6 0 +OP4 E006C7 0 +OP4 E006C8 0 +OP4 E006C9 0 +OP4 E006CA 0 +OP4 E006CB 0 +OP4 E006CC 0 +OP4 E006CD 0 +OP4 E006CE 0 +OP4 E006CF 0 +OP4 E006D0 0 +OP4 E006D1 0 +OP4 E006D2 0 +OP4 E006D3 0 +OP4 E006D4 0 +OP4 E006D5 0 +OP4 E006D6 0 +OP4 E006D7 0 +OP4 E006D8 0 +OP4 E006D9 0 +OP4 E006DA 0 +OP4 E006DB 0 +OP4 E006DC 0 +OP4 E006DD 0 +OP4 E006DE 0 +OP4 E006DF 0 +OP4 E006E0 0 +OP4 E006E1 0 +OP4 E006E2 0 +OP4 E006E3 0 +OP4 E006E4 0 +OP4 E006E5 0 +OP4 E006E6 0 +OP4 E006E7 0 +OP4 E006E8 0 +OP4 E006E9 0 +OP4 E006EA 0 +OP4 E006EB 0 +OP4 E006EC 0 +OP4 E006ED 0 +OP4 E006EE 0 +OP4 E006EF 0 +OP4 E006F0 0 +OP4 E006F1 0 +OP4 E006F2 0 +OP4 E006F3 0 +OP4 E006F4 0 +OP4 E006F5 0 +OP4 E006F6 0 +OP4 E006F7 0 +OP4 E006F8 0 +OP4 E006F9 0 +OP4 E006FA 0 +OP4 E006FB 0 +OP4 E006FC 0 +OP4 E006FD 0 +OP4 E006FE 0 +OP4 E006FF 0 +OP4 E00700 0 +OP4 E00701 0 +OP4 E00702 0 +OP4 E00703 0 +OP4 E00704 0 +OP4 E00705 0 +OP4 E00706 0 +OP4 E00707 0 +OP4 E00708 0 +OP4 E00709 0 +OP4 E0070A 0 +OP4 E0070B 0 +OP4 E0070C 0 +OP4 E0070D 0 +OP4 E0070E 0 +OP4 E0070F 0 +OP4 E00710 0 +OP4 E00711 0 +OP4 E00712 0 +OP4 E00713 0 +OP4 E00714 0 +OP4 E00715 0 +OP4 E00716 0 +OP4 E00717 0 +OP4 E00718 0 +OP4 E00719 0 +OP4 E0071A 0 +OP4 E0071B 0 +OP4 E0071C 0 +OP4 E0071D 0 +OP4 E0071E 0 +OP4 E0071F 0 +OP4 E00720 0 +OP4 E00721 0 +OP4 E00722 0 +OP4 E00723 0 +OP4 E00724 0 +OP4 E00725 0 +OP4 E00726 0 +OP4 E00727 0 +OP4 E00728 0 +OP4 E00729 0 +OP4 E0072A 0 +OP4 E0072B 0 +OP4 E0072C 0 +OP4 E0072D 0 +OP4 E0072E 0 +OP4 E0072F 0 +OP4 E00730 0 +OP4 E00731 0 +OP4 E00732 0 +OP4 E00733 0 +OP4 E00734 0 +OP4 E00735 0 +OP4 E00736 0 +OP4 E00737 0 +OP4 E00738 0 +OP4 E00739 0 +OP4 E0073A 0 +OP4 E0073B 0 +OP4 E0073C 0 +OP4 E0073D 0 +OP4 E0073E 0 +OP4 E0073F 0 +OP4 E00740 0 +OP4 E00741 0 +OP4 E00742 0 +OP4 E00743 0 +OP4 E00744 0 +OP4 E00745 0 +OP4 E00746 0 +OP4 E00747 0 +OP4 E00748 0 +OP4 E00749 0 +OP4 E0074A 0 +OP4 E0074B 0 +OP4 E0074C 0 +OP4 E0074D 0 +OP4 E0074E 0 +OP4 E0074F 0 +OP4 E00750 0 +OP4 E00751 0 +OP4 E00752 0 +OP4 E00753 0 +OP4 E00754 0 +OP4 E00755 0 +OP4 E00756 0 +OP4 E00757 0 +OP4 E00758 0 +OP4 E00759 0 +OP4 E0075A 0 +OP4 E0075B 0 +OP4 E0075C 0 +OP4 E0075D 0 +OP4 E0075E 0 +OP4 E0075F 0 +OP4 E00760 0 +OP4 E00761 0 +OP4 E00762 0 +OP4 E00763 0 +OP4 E00764 0 +OP4 E00765 0 +OP4 E00766 0 +OP4 E00767 0 +OP4 E00768 0 +OP4 E00769 0 +OP4 E0076A 0 +OP4 E0076B 0 +OP4 E0076C 0 +OP4 E0076D 0 +OP4 E0076E 0 +OP4 E0076F 0 +OP4 E00770 0 +OP4 E00771 0 +OP4 E00772 0 +OP4 E00773 0 +OP4 E00774 0 +OP4 E00775 0 +OP4 E00776 0 +OP4 E00777 0 +OP4 E00778 0 +OP4 E00779 0 +OP4 E0077A 0 +OP4 E0077B 0 +OP4 E0077C 0 +OP4 E0077D 0 +OP4 E0077E 0 +OP4 E0077F 0 +OP4 E00780 0 +OP4 E00781 0 +OP4 E00782 0 +OP4 E00783 0 +OP4 E00784 0 +OP4 E00785 0 +OP4 E00786 0 +OP4 E00787 0 +OP4 E00788 0 +OP4 E00789 0 +OP4 E0078A 0 +OP4 E0078B 0 +OP4 E0078C 0 +OP4 E0078D 0 +OP4 E0078E 0 +OP4 E0078F 0 +OP4 E00790 0 +OP4 E00791 0 +OP4 E00792 0 +OP4 E00793 0 +OP4 E00794 0 +OP4 E00795 0 +OP4 E00796 0 +OP4 E00797 0 +OP4 E00798 0 +OP4 E00799 0 +OP4 E0079A 0 +OP4 E0079B 0 +OP4 E0079C 0 +OP4 E0079D 0 +OP4 E0079E 0 +OP4 E0079F 0 +OP4 E007A0 0 +OP4 E007A1 0 +OP4 E007A2 0 +OP4 E007A3 0 +OP4 E007A4 0 +OP4 E007A5 0 +OP4 E007A6 0 +OP4 E007A7 0 +OP4 E007A8 0 +OP4 E007A9 0 +OP4 E007AA 0 +OP4 E007AB 0 +OP4 E007AC 0 +OP4 E007AD 0 +OP4 E007AE 0 +OP4 E007AF 0 +OP4 E007B0 0 +OP4 E007B1 0 +OP4 E007B2 0 +OP4 E007B3 0 +OP4 E007B4 0 +OP4 E007B5 0 +OP4 E007B6 0 +OP4 E007B7 0 +OP4 E007B8 0 +OP4 E007B9 0 +OP4 E007BA 0 +OP4 E007BB 0 +OP4 E007BC 0 +OP4 E007BD 0 +OP4 E007BE 0 +OP4 E007BF 0 +OP4 E007C0 0 +OP4 E007C1 0 +OP4 E007C2 0 +OP4 E007C3 0 +OP4 E007C4 0 +OP4 E007C5 0 +OP4 E007C6 0 +OP4 E007C7 0 +OP4 E007C8 0 +OP4 E007C9 0 +OP4 E007CA 0 +OP4 E007CB 0 +OP4 E007CC 0 +OP4 E007CD 0 +OP4 E007CE 0 +OP4 E007CF 0 +OP4 E007D0 0 +OP4 E007D1 0 +OP4 E007D2 0 +OP4 E007D3 0 +OP4 E007D4 0 +OP4 E007D5 0 +OP4 E007D6 0 +OP4 E007D7 0 +OP4 E007D8 0 +OP4 E007D9 0 +OP4 E007DA 0 +OP4 E007DB 0 +OP4 E007DC 0 +OP4 E007DD 0 +OP4 E007DE 0 +OP4 E007DF 0 +OP4 E007E0 0 +OP4 E007E1 0 +OP4 E007E2 0 +OP4 E007E3 0 +OP4 E007E4 0 +OP4 E007E5 0 +OP4 E007E6 0 +OP4 E007E7 0 +OP4 E007E8 0 +OP4 E007E9 0 +OP4 E007EA 0 +OP4 E007EB 0 +OP4 E007EC 0 +OP4 E007ED 0 +OP4 E007EE 0 +OP4 E007EF 0 +OP4 E007F0 0 +OP4 E007F1 0 +OP4 E007F2 0 +OP4 E007F3 0 +OP4 E007F4 0 +OP4 E007F5 0 +OP4 E007F6 0 +OP4 E007F7 0 +OP4 E007F8 0 +OP4 E007F9 0 +OP4 E007FA 0 +OP4 E007FB 0 +OP4 E007FC 0 +OP4 E007FD 0 +OP4 E007FE 0 +OP4 E007FF 0 +OP4 E00800 0 +OP4 E00801 0 +OP4 E00802 0 +OP4 E00803 0 +OP4 E00804 0 +OP4 E00805 0 +OP4 E00806 0 +OP4 E00807 0 +OP4 E00808 0 +OP4 E00809 0 +OP4 E0080A 0 +OP4 E0080B 0 +OP4 E0080C 0 +OP4 E0080D 0 +OP4 E0080E 0 +OP4 E0080F 0 +OP4 E00810 0 +OP4 E00811 0 +OP4 E00812 0 +OP4 E00813 0 +OP4 E00814 0 +OP4 E00815 0 +OP4 E00816 0 +OP4 E00817 0 +OP4 E00818 0 +OP4 E00819 0 +OP4 E0081A 0 +OP4 E0081B 0 +OP4 E0081C 0 +OP4 E0081D 0 +OP4 E0081E 0 +OP4 E0081F 0 +OP4 E00820 0 +OP4 E00821 0 +OP4 E00822 0 +OP4 E00823 0 +OP4 E00824 0 +OP4 E00825 0 +OP4 E00826 0 +OP4 E00827 0 +OP4 E00828 0 +OP4 E00829 0 +OP4 E0082A 0 +OP4 E0082B 0 +OP4 E0082C 0 +OP4 E0082D 0 +OP4 E0082E 0 +OP4 E0082F 0 +OP4 E00830 0 +OP4 E00831 0 +OP4 E00832 0 +OP4 E00833 0 +OP4 E00834 0 +OP4 E00835 0 +OP4 E00836 0 +OP4 E00837 0 +OP4 E00838 0 +OP4 E00839 0 +OP4 E0083A 0 +OP4 E0083B 0 +OP4 E0083C 0 +OP4 E0083D 0 +OP4 E0083E 0 +OP4 E0083F 0 +OP4 E00840 0 +OP4 E00841 0 +OP4 E00842 0 +OP4 E00843 0 +OP4 E00844 0 +OP4 E00845 0 +OP4 E00846 0 +OP4 E00847 0 +OP4 E00848 0 +OP4 E00849 0 +OP4 E0084A 0 +OP4 E0084B 0 +OP4 E0084C 0 +OP4 E0084D 0 +OP4 E0084E 0 +OP4 E0084F 0 +OP4 E00850 0 +OP4 E00851 0 +OP4 E00852 0 +OP4 E00853 0 +OP4 E00854 0 +OP4 E00855 0 +OP4 E00856 0 +OP4 E00857 0 +OP4 E00858 0 +OP4 E00859 0 +OP4 E0085A 0 +OP4 E0085B 0 +OP4 E0085C 0 +OP4 E0085D 0 +OP4 E0085E 0 +OP4 E0085F 0 +OP4 E00860 0 +OP4 E00861 0 +OP4 E00862 0 +OP4 E00863 0 +OP4 E00864 0 +OP4 E00865 0 +OP4 E00866 0 +OP4 E00867 0 +OP4 E00868 0 +OP4 E00869 0 +OP4 E0086A 0 +OP4 E0086B 0 +OP4 E0086C 0 +OP4 E0086D 0 +OP4 E0086E 0 +OP4 E0086F 0 +OP4 E00870 0 +OP4 E00871 0 +OP4 E00872 0 +OP4 E00873 0 +OP4 E00874 0 +OP4 E00875 0 +OP4 E00876 0 +OP4 E00877 0 +OP4 E00878 0 +OP4 E00879 0 +OP4 E0087A 0 +OP4 E0087B 0 +OP4 E0087C 0 +OP4 E0087D 0 +OP4 E0087E 0 +OP4 E0087F 0 +OP4 E00880 0 +OP4 E00881 0 +OP4 E00882 0 +OP4 E00883 0 +OP4 E00884 0 +OP4 E00885 0 +OP4 E00886 0 +OP4 E00887 0 +OP4 E00888 0 +OP4 E00889 0 +OP4 E0088A 0 +OP4 E0088B 0 +OP4 E0088C 0 +OP4 E0088D 0 +OP4 E0088E 0 +OP4 E0088F 0 +OP4 E00890 0 +OP4 E00891 0 +OP4 E00892 0 +OP4 E00893 0 +OP4 E00894 0 +OP4 E00895 0 +OP4 E00896 0 +OP4 E00897 0 +OP4 E00898 0 +OP4 E00899 0 +OP4 E0089A 0 +OP4 E0089B 0 +OP4 E0089C 0 +OP4 E0089D 0 +OP4 E0089E 0 +OP4 E0089F 0 +OP4 E008A0 0 +OP4 E008A1 0 +OP4 E008A2 0 +OP4 E008A3 0 +OP4 E008A4 0 +OP4 E008A5 0 +OP4 E008A6 0 +OP4 E008A7 0 +OP4 E008A8 0 +OP4 E008A9 0 +OP4 E008AA 0 +OP4 E008AB 0 +OP4 E008AC 0 +OP4 E008AD 0 +OP4 E008AE 0 +OP4 E008AF 0 +OP4 E008B0 0 +OP4 E008B1 0 +OP4 E008B2 0 +OP4 E008B3 0 +OP4 E008B4 0 +OP4 E008B5 0 +OP4 E008B6 0 +OP4 E008B7 0 +OP4 E008B8 0 +OP4 E008B9 0 +OP4 E008BA 0 +OP4 E008BB 0 +OP4 E008BC 0 +OP4 E008BD 0 +OP4 E008BE 0 +OP4 E008BF 0 +OP4 E008C0 0 +OP4 E008C1 0 +OP4 E008C2 0 +OP4 E008C3 0 +OP4 E008C4 0 +OP4 E008C5 0 +OP4 E008C6 0 +OP4 E008C7 0 +OP4 E008C8 0 +OP4 E008C9 0 +OP4 E008CA 0 +OP4 E008CB 0 +OP4 E008CC 0 +OP4 E008CD 0 +OP4 E008CE 0 +OP4 E008CF 0 +OP4 E008D0 0 +OP4 E008D1 0 +OP4 E008D2 0 +OP4 E008D3 0 +OP4 E008D4 0 +OP4 E008D5 0 +OP4 E008D6 0 +OP4 E008D7 0 +OP4 E008D8 0 +OP4 E008D9 0 +OP4 E008DA 0 +OP4 E008DB 0 +OP4 E008DC 0 +OP4 E008DD 0 +OP4 E008DE 0 +OP4 E008DF 0 +OP4 E008E0 0 +OP4 E008E1 0 +OP4 E008E2 0 +OP4 E008E3 0 +OP4 E008E4 0 +OP4 E008E5 0 +OP4 E008E6 0 +OP4 E008E7 0 +OP4 E008E8 0 +OP4 E008E9 0 +OP4 E008EA 0 +OP4 E008EB 0 +OP4 E008EC 0 +OP4 E008ED 0 +OP4 E008EE 0 +OP4 E008EF 0 +OP4 E008F0 0 +OP4 E008F1 0 +OP4 E008F2 0 +OP4 E008F3 0 +OP4 E008F4 0 +OP4 E008F5 0 +OP4 E008F6 0 +OP4 E008F7 0 +OP4 E008F8 0 +OP4 E008F9 0 +OP4 E008FA 0 +OP4 E008FB 0 +OP4 E008FC 0 +OP4 E008FD 0 +OP4 E008FE 0 +OP4 E008FF 0 +OP4 E00900 0 +OP4 E00901 0 +OP4 E00902 0 +OP4 E00903 0 +OP4 E00904 0 +OP4 E00905 0 +OP4 E00906 0 +OP4 E00907 0 +OP4 E00908 0 +OP4 E00909 0 +OP4 E0090A 0 +OP4 E0090B 0 +OP4 E0090C 0 +OP4 E0090D 0 +OP4 E0090E 0 +OP4 E0090F 0 +OP4 E00910 0 +OP4 E00911 0 +OP4 E00912 0 +OP4 E00913 0 +OP4 E00914 0 +OP4 E00915 0 +OP4 E00916 0 +OP4 E00917 0 +OP4 E00918 0 +OP4 E00919 0 +OP4 E0091A 0 +OP4 E0091B 0 +OP4 E0091C 0 +OP4 E0091D 0 +OP4 E0091E 0 +OP4 E0091F 0 +OP4 E00920 0 +OP4 E00921 0 +OP4 E00922 0 +OP4 E00923 0 +OP4 E00924 0 +OP4 E00925 0 +OP4 E00926 0 +OP4 E00927 0 +OP4 E00928 0 +OP4 E00929 0 +OP4 E0092A 0 +OP4 E0092B 0 +OP4 E0092C 0 +OP4 E0092D 0 +OP4 E0092E 0 +OP4 E0092F 0 +OP4 E00930 0 +OP4 E00931 0 +OP4 E00932 0 +OP4 E00933 0 +OP4 E00934 0 +OP4 E00935 0 +OP4 E00936 0 +OP4 E00937 0 +OP4 E00938 0 +OP4 E00939 0 +OP4 E0093A 0 +OP4 E0093B 0 +OP4 E0093C 0 +OP4 E0093D 0 +OP4 E0093E 0 +OP4 E0093F 0 +OP4 E00940 0 +OP4 E00941 0 +OP4 E00942 0 +OP4 E00943 0 +OP4 E00944 0 +OP4 E00945 0 +OP4 E00946 0 +OP4 E00947 0 +OP4 E00948 0 +OP4 E00949 0 +OP4 E0094A 0 +OP4 E0094B 0 +OP4 E0094C 0 +OP4 E0094D 0 +OP4 E0094E 0 +OP4 E0094F 0 +OP4 E00950 0 +OP4 E00951 0 +OP4 E00952 0 +OP4 E00953 0 +OP4 E00954 0 +OP4 E00955 0 +OP4 E00956 0 +OP4 E00957 0 +OP4 E00958 0 +OP4 E00959 0 +OP4 E0095A 0 +OP4 E0095B 0 +OP4 E0095C 0 +OP4 E0095D 0 +OP4 E0095E 0 +OP4 E0095F 0 +OP4 E00960 0 +OP4 E00961 0 +OP4 E00962 0 +OP4 E00963 0 +OP4 E00964 0 +OP4 E00965 0 +OP4 E00966 0 +OP4 E00967 0 +OP4 E00968 0 +OP4 E00969 0 +OP4 E0096A 0 +OP4 E0096B 0 +OP4 E0096C 0 +OP4 E0096D 0 +OP4 E0096E 0 +OP4 E0096F 0 +OP4 E00970 0 +OP4 E00971 0 +OP4 E00972 0 +OP4 E00973 0 +OP4 E00974 0 +OP4 E00975 0 +OP4 E00976 0 +OP4 E00977 0 +OP4 E00978 0 +OP4 E00979 0 +OP4 E0097A 0 +OP4 E0097B 0 +OP4 E0097C 0 +OP4 E0097D 0 +OP4 E0097E 0 +OP4 E0097F 0 +OP4 E00980 0 +OP4 E00981 0 +OP4 E00982 0 +OP4 E00983 0 +OP4 E00984 0 +OP4 E00985 0 +OP4 E00986 0 +OP4 E00987 0 +OP4 E00988 0 +OP4 E00989 0 +OP4 E0098A 0 +OP4 E0098B 0 +OP4 E0098C 0 +OP4 E0098D 0 +OP4 E0098E 0 +OP4 E0098F 0 +OP4 E00990 0 +OP4 E00991 0 +OP4 E00992 0 +OP4 E00993 0 +OP4 E00994 0 +OP4 E00995 0 +OP4 E00996 0 +OP4 E00997 0 +OP4 E00998 0 +OP4 E00999 0 +OP4 E0099A 0 +OP4 E0099B 0 +OP4 E0099C 0 +OP4 E0099D 0 +OP4 E0099E 0 +OP4 E0099F 0 +OP4 E009A0 0 +OP4 E009A1 0 +OP4 E009A2 0 +OP4 E009A3 0 +OP4 E009A4 0 +OP4 E009A5 0 +OP4 E009A6 0 +OP4 E009A7 0 +OP4 E009A8 0 +OP4 E009A9 0 +OP4 E009AA 0 +OP4 E009AB 0 +OP4 E009AC 0 +OP4 E009AD 0 +OP4 E009AE 0 +OP4 E009AF 0 +OP4 E009B0 0 +OP4 E009B1 0 +OP4 E009B2 0 +OP4 E009B3 0 +OP4 E009B4 0 +OP4 E009B5 0 +OP4 E009B6 0 +OP4 E009B7 0 +OP4 E009B8 0 +OP4 E009B9 0 +OP4 E009BA 0 +OP4 E009BB 0 +OP4 E009BC 0 +OP4 E009BD 0 +OP4 E009BE 0 +OP4 E009BF 0 +OP4 E009C0 0 +OP4 E009C1 0 +OP4 E009C2 0 +OP4 E009C3 0 +OP4 E009C4 0 +OP4 E009C5 0 +OP4 E009C6 0 +OP4 E009C7 0 +OP4 E009C8 0 +OP4 E009C9 0 +OP4 E009CA 0 +OP4 E009CB 0 +OP4 E009CC 0 +OP4 E009CD 0 +OP4 E009CE 0 +OP4 E009CF 0 +OP4 E009D0 0 +OP4 E009D1 0 +OP4 E009D2 0 +OP4 E009D3 0 +OP4 E009D4 0 +OP4 E009D5 0 +OP4 E009D6 0 +OP4 E009D7 0 +OP4 E009D8 0 +OP4 E009D9 0 +OP4 E009DA 0 +OP4 E009DB 0 +OP4 E009DC 0 +OP4 E009DD 0 +OP4 E009DE 0 +OP4 E009DF 0 +OP4 E009E0 0 +OP4 E009E1 0 +OP4 E009E2 0 +OP4 E009E3 0 +OP4 E009E4 0 +OP4 E009E5 0 +OP4 E009E6 0 +OP4 E009E7 0 +OP4 E009E8 0 +OP4 E009E9 0 +OP4 E009EA 0 +OP4 E009EB 0 +OP4 E009EC 0 +OP4 E009ED 0 +OP4 E009EE 0 +OP4 E009EF 0 +OP4 E009F0 0 +OP4 E009F1 0 +OP4 E009F2 0 +OP4 E009F3 0 +OP4 E009F4 0 +OP4 E009F5 0 +OP4 E009F6 0 +OP4 E009F7 0 +OP4 E009F8 0 +OP4 E009F9 0 +OP4 E009FA 0 +OP4 E009FB 0 +OP4 E009FC 0 +OP4 E009FD 0 +OP4 E009FE 0 +OP4 E009FF 0 +OP4 E00A00 0 +OP4 E00A01 0 +OP4 E00A02 0 +OP4 E00A03 0 +OP4 E00A04 0 +OP4 E00A05 0 +OP4 E00A06 0 +OP4 E00A07 0 +OP4 E00A08 0 +OP4 E00A09 0 +OP4 E00A0A 0 +OP4 E00A0B 0 +OP4 E00A0C 0 +OP4 E00A0D 0 +OP4 E00A0E 0 +OP4 E00A0F 0 +OP4 E00A10 0 +OP4 E00A11 0 +OP4 E00A12 0 +OP4 E00A13 0 +OP4 E00A14 0 +OP4 E00A15 0 +OP4 E00A16 0 +OP4 E00A17 0 +OP4 E00A18 0 +OP4 E00A19 0 +OP4 E00A1A 0 +OP4 E00A1B 0 +OP4 E00A1C 0 +OP4 E00A1D 0 +OP4 E00A1E 0 +OP4 E00A1F 0 +OP4 E00A20 0 +OP4 E00A21 0 +OP4 E00A22 0 +OP4 E00A23 0 +OP4 E00A24 0 +OP4 E00A25 0 +OP4 E00A26 0 +OP4 E00A27 0 +OP4 E00A28 0 +OP4 E00A29 0 +OP4 E00A2A 0 +OP4 E00A2B 0 +OP4 E00A2C 0 +OP4 E00A2D 0 +OP4 E00A2E 0 +OP4 E00A2F 0 +OP4 E00A30 0 +OP4 E00A31 0 +OP4 E00A32 0 +OP4 E00A33 0 +OP4 E00A34 0 +OP4 E00A35 0 +OP4 E00A36 0 +OP4 E00A37 0 +OP4 E00A38 0 +OP4 E00A39 0 +OP4 E00A3A 0 +OP4 E00A3B 0 +OP4 E00A3C 0 +OP4 E00A3D 0 +OP4 E00A3E 0 +OP4 E00A3F 0 +OP4 E00A40 0 +OP4 E00A41 0 +OP4 E00A42 0 +OP4 E00A43 0 +OP4 E00A44 0 +OP4 E00A45 0 +OP4 E00A46 0 +OP4 E00A47 0 +OP4 E00A48 0 +OP4 E00A49 0 +OP4 E00A4A 0 +OP4 E00A4B 0 +OP4 E00A4C 0 +OP4 E00A4D 0 +OP4 E00A4E 0 +OP4 E00A4F 0 +OP4 E00A50 0 +OP4 E00A51 0 +OP4 E00A52 0 +OP4 E00A53 0 +OP4 E00A54 0 +OP4 E00A55 0 +OP4 E00A56 0 +OP4 E00A57 0 +OP4 E00A58 0 +OP4 E00A59 0 +OP4 E00A5A 0 +OP4 E00A5B 0 +OP4 E00A5C 0 +OP4 E00A5D 0 +OP4 E00A5E 0 +OP4 E00A5F 0 +OP4 E00A60 0 +OP4 E00A61 0 +OP4 E00A62 0 +OP4 E00A63 0 +OP4 E00A64 0 +OP4 E00A65 0 +OP4 E00A66 0 +OP4 E00A67 0 +OP4 E00A68 0 +OP4 E00A69 0 +OP4 E00A6A 0 +OP4 E00A6B 0 +OP4 E00A6C 0 +OP4 E00A6D 0 +OP4 E00A6E 0 +OP4 E00A6F 0 +OP4 E00A70 0 +OP4 E00A71 0 +OP4 E00A72 0 +OP4 E00A73 0 +OP4 E00A74 0 +OP4 E00A75 0 +OP4 E00A76 0 +OP4 E00A77 0 +OP4 E00A78 0 +OP4 E00A79 0 +OP4 E00A7A 0 +OP4 E00A7B 0 +OP4 E00A7C 0 +OP4 E00A7D 0 +OP4 E00A7E 0 +OP4 E00A7F 0 +OP4 E00A80 0 +OP4 E00A81 0 +OP4 E00A82 0 +OP4 E00A83 0 +OP4 E00A84 0 +OP4 E00A85 0 +OP4 E00A86 0 +OP4 E00A87 0 +OP4 E00A88 0 +OP4 E00A89 0 +OP4 E00A8A 0 +OP4 E00A8B 0 +OP4 E00A8C 0 +OP4 E00A8D 0 +OP4 E00A8E 0 +OP4 E00A8F 0 +OP4 E00A90 0 +OP4 E00A91 0 +OP4 E00A92 0 +OP4 E00A93 0 +OP4 E00A94 0 +OP4 E00A95 0 +OP4 E00A96 0 +OP4 E00A97 0 +OP4 E00A98 0 +OP4 E00A99 0 +OP4 E00A9A 0 +OP4 E00A9B 0 +OP4 E00A9C 0 +OP4 E00A9D 0 +OP4 E00A9E 0 +OP4 E00A9F 0 +OP4 E00AA0 0 +OP4 E00AA1 0 +OP4 E00AA2 0 +OP4 E00AA3 0 +OP4 E00AA4 0 +OP4 E00AA5 0 +OP4 E00AA6 0 +OP4 E00AA7 0 +OP4 E00AA8 0 +OP4 E00AA9 0 +OP4 E00AAA 0 +OP4 E00AAB 0 +OP4 E00AAC 0 +OP4 E00AAD 0 +OP4 E00AAE 0 +OP4 E00AAF 0 +OP4 E00AB0 0 +OP4 E00AB1 0 +OP4 E00AB2 0 +OP4 E00AB3 0 +OP4 E00AB4 0 +OP4 E00AB5 0 +OP4 E00AB6 0 +OP4 E00AB7 0 +OP4 E00AB8 0 +OP4 E00AB9 0 +OP4 E00ABA 0 +OP4 E00ABB 0 +OP4 E00ABC 0 +OP4 E00ABD 0 +OP4 E00ABE 0 +OP4 E00ABF 0 +OP4 E00AC0 0 +OP4 E00AC1 0 +OP4 E00AC2 0 +OP4 E00AC3 0 +OP4 E00AC4 0 +OP4 E00AC5 0 +OP4 E00AC6 0 +OP4 E00AC7 0 +OP4 E00AC8 0 +OP4 E00AC9 0 +OP4 E00ACA 0 +OP4 E00ACB 0 +OP4 E00ACC 0 +OP4 E00ACD 0 +OP4 E00ACE 0 +OP4 E00ACF 0 +OP4 E00AD0 0 +OP4 E00AD1 0 +OP4 E00AD2 0 +OP4 E00AD3 0 +OP4 E00AD4 0 +OP4 E00AD5 0 +OP4 E00AD6 0 +OP4 E00AD7 0 +OP4 E00AD8 0 +OP4 E00AD9 0 +OP4 E00ADA 0 +OP4 E00ADB 0 +OP4 E00ADC 0 +OP4 E00ADD 0 +OP4 E00ADE 0 +OP4 E00ADF 0 +OP4 E00AE0 0 +OP4 E00AE1 0 +OP4 E00AE2 0 +OP4 E00AE3 0 +OP4 E00AE4 0 +OP4 E00AE5 0 +OP4 E00AE6 0 +OP4 E00AE7 0 +OP4 E00AE8 0 +OP4 E00AE9 0 +OP4 E00AEA 0 +OP4 E00AEB 0 +OP4 E00AEC 0 +OP4 E00AED 0 +OP4 E00AEE 0 +OP4 E00AEF 0 +OP4 E00AF0 0 +OP4 E00AF1 0 +OP4 E00AF2 0 +OP4 E00AF3 0 +OP4 E00AF4 0 +OP4 E00AF5 0 +OP4 E00AF6 0 +OP4 E00AF7 0 +OP4 E00AF8 0 +OP4 E00AF9 0 +OP4 E00AFA 0 +OP4 E00AFB 0 +OP4 E00AFC 0 +OP4 E00AFD 0 +OP4 E00AFE 0 +OP4 E00AFF 0 +OP4 E00B00 0 +OP4 E00B01 0 +OP4 E00B02 0 +OP4 E00B03 0 +OP4 E00B04 0 +OP4 E00B05 0 +OP4 E00B06 0 +OP4 E00B07 0 +OP4 E00B08 0 +OP4 E00B09 0 +OP4 E00B0A 0 +OP4 E00B0B 0 +OP4 E00B0C 0 +OP4 E00B0D 0 +OP4 E00B0E 0 +OP4 E00B0F 0 +OP4 E00B10 0 +OP4 E00B11 0 +OP4 E00B12 0 +OP4 E00B13 0 +OP4 E00B14 0 +OP4 E00B15 0 +OP4 E00B16 0 +OP4 E00B17 0 +OP4 E00B18 0 +OP4 E00B19 0 +OP4 E00B1A 0 +OP4 E00B1B 0 +OP4 E00B1C 0 +OP4 E00B1D 0 +OP4 E00B1E 0 +OP4 E00B1F 0 +OP4 E00B20 0 +OP4 E00B21 0 +OP4 E00B22 0 +OP4 E00B23 0 +OP4 E00B24 0 +OP4 E00B25 0 +OP4 E00B26 0 +OP4 E00B27 0 +OP4 E00B28 0 +OP4 E00B29 0 +OP4 E00B2A 0 +OP4 E00B2B 0 +OP4 E00B2C 0 +OP4 E00B2D 0 +OP4 E00B2E 0 +OP4 E00B2F 0 +OP4 E00B30 0 +OP4 E00B31 0 +OP4 E00B32 0 +OP4 E00B33 0 +OP4 E00B34 0 +OP4 E00B35 0 +OP4 E00B36 0 +OP4 E00B37 0 +OP4 E00B38 0 +OP4 E00B39 0 +OP4 E00B3A 0 +OP4 E00B3B 0 +OP4 E00B3C 0 +OP4 E00B3D 0 +OP4 E00B3E 0 +OP4 E00B3F 0 +OP4 E00B40 0 +OP4 E00B41 0 +OP4 E00B42 0 +OP4 E00B43 0 +OP4 E00B44 0 +OP4 E00B45 0 +OP4 E00B46 0 +OP4 E00B47 0 +OP4 E00B48 0 +OP4 E00B49 0 +OP4 E00B4A 0 +OP4 E00B4B 0 +OP4 E00B4C 0 +OP4 E00B4D 0 +OP4 E00B4E 0 +OP4 E00B4F 0 +OP4 E00B50 0 +OP4 E00B51 0 +OP4 E00B52 0 +OP4 E00B53 0 +OP4 E00B54 0 +OP4 E00B55 0 +OP4 E00B56 0 +OP4 E00B57 0 +OP4 E00B58 0 +OP4 E00B59 0 +OP4 E00B5A 0 +OP4 E00B5B 0 +OP4 E00B5C 0 +OP4 E00B5D 0 +OP4 E00B5E 0 +OP4 E00B5F 0 +OP4 E00B60 0 +OP4 E00B61 0 +OP4 E00B62 0 +OP4 E00B63 0 +OP4 E00B64 0 +OP4 E00B65 0 +OP4 E00B66 0 +OP4 E00B67 0 +OP4 E00B68 0 +OP4 E00B69 0 +OP4 E00B6A 0 +OP4 E00B6B 0 +OP4 E00B6C 0 +OP4 E00B6D 0 +OP4 E00B6E 0 +OP4 E00B6F 0 +OP4 E00B70 0 +OP4 E00B71 0 +OP4 E00B72 0 +OP4 E00B73 0 +OP4 E00B74 0 +OP4 E00B75 0 +OP4 E00B76 0 +OP4 E00B77 0 +OP4 E00B78 0 +OP4 E00B79 0 +OP4 E00B7A 0 +OP4 E00B7B 0 +OP4 E00B7C 0 +OP4 E00B7D 0 +OP4 E00B7E 0 +OP4 E00B7F 0 +OP4 E00B80 0 +OP4 E00B81 0 +OP4 E00B82 0 +OP4 E00B83 0 +OP4 E00B84 0 +OP4 E00B85 0 +OP4 E00B86 0 +OP4 E00B87 0 +OP4 E00B88 0 +OP4 E00B89 0 +OP4 E00B8A 0 +OP4 E00B8B 0 +OP4 E00B8C 0 +OP4 E00B8D 0 +OP4 E00B8E 0 +OP4 E00B8F 0 +OP4 E00B90 0 +OP4 E00B91 0 +OP4 E00B92 0 +OP4 E00B93 0 +OP4 E00B94 0 +OP4 E00B95 0 +OP4 E00B96 0 +OP4 E00B97 0 +OP4 E00B98 0 +OP4 E00B99 0 +OP4 E00B9A 0 +OP4 E00B9B 0 +OP4 E00B9C 0 +OP4 E00B9D 0 +OP4 E00B9E 0 +OP4 E00B9F 0 +OP4 E00BA0 0 +OP4 E00BA1 0 +OP4 E00BA2 0 +OP4 E00BA3 0 +OP4 E00BA4 0 +OP4 E00BA5 0 +OP4 E00BA6 0 +OP4 E00BA7 0 +OP4 E00BA8 0 +OP4 E00BA9 0 +OP4 E00BAA 0 +OP4 E00BAB 0 +OP4 E00BAC 0 +OP4 E00BAD 0 +OP4 E00BAE 0 +OP4 E00BAF 0 +OP4 E00BB0 0 +OP4 E00BB1 0 +OP4 E00BB2 0 +OP4 E00BB3 0 +OP4 E00BB4 0 +OP4 E00BB5 0 +OP4 E00BB6 0 +OP4 E00BB7 0 +OP4 E00BB8 0 +OP4 E00BB9 0 +OP4 E00BBA 0 +OP4 E00BBB 0 +OP4 E00BBC 0 +OP4 E00BBD 0 +OP4 E00BBE 0 +OP4 E00BBF 0 +OP4 E00BC0 0 +OP4 E00BC1 0 +OP4 E00BC2 0 +OP4 E00BC3 0 +OP4 E00BC4 0 +OP4 E00BC5 0 +OP4 E00BC6 0 +OP4 E00BC7 0 +OP4 E00BC8 0 +OP4 E00BC9 0 +OP4 E00BCA 0 +OP4 E00BCB 0 +OP4 E00BCC 0 +OP4 E00BCD 0 +OP4 E00BCE 0 +OP4 E00BCF 0 +OP4 E00BD0 0 +OP4 E00BD1 0 +OP4 E00BD2 0 +OP4 E00BD3 0 +OP4 E00BD4 0 +OP4 E00BD5 0 +OP4 E00BD6 0 +OP4 E00BD7 0 +OP4 E00BD8 0 +OP4 E00BD9 0 +OP4 E00BDA 0 +OP4 E00BDB 0 +OP4 E00BDC 0 +OP4 E00BDD 0 +OP4 E00BDE 0 +OP4 E00BDF 0 +OP4 E00BE0 0 +OP4 E00BE1 0 +OP4 E00BE2 0 +OP4 E00BE3 0 +OP4 E00BE4 0 +OP4 E00BE5 0 +OP4 E00BE6 0 +OP4 E00BE7 0 +OP4 E00BE8 0 +OP4 E00BE9 0 +OP4 E00BEA 0 +OP4 E00BEB 0 +OP4 E00BEC 0 +OP4 E00BED 0 +OP4 E00BEE 0 +OP4 E00BEF 0 +OP4 E00BF0 0 +OP4 E00BF1 0 +OP4 E00BF2 0 +OP4 E00BF3 0 +OP4 E00BF4 0 +OP4 E00BF5 0 +OP4 E00BF6 0 +OP4 E00BF7 0 +OP4 E00BF8 0 +OP4 E00BF9 0 +OP4 E00BFA 0 +OP4 E00BFB 0 +OP4 E00BFC 0 +OP4 E00BFD 0 +OP4 E00BFE 0 +OP4 E00BFF 0 +OP4 E00C00 0 +OP4 E00C01 0 +OP4 E00C02 0 +OP4 E00C03 0 +OP4 E00C04 0 +OP4 E00C05 0 +OP4 E00C06 0 +OP4 E00C07 0 +OP4 E00C08 0 +OP4 E00C09 0 +OP4 E00C0A 0 +OP4 E00C0B 0 +OP4 E00C0C 0 +OP4 E00C0D 0 +OP4 E00C0E 0 +OP4 E00C0F 0 +OP4 E00C10 0 +OP4 E00C11 0 +OP4 E00C12 0 +OP4 E00C13 0 +OP4 E00C14 0 +OP4 E00C15 0 +OP4 E00C16 0 +OP4 E00C17 0 +OP4 E00C18 0 +OP4 E00C19 0 +OP4 E00C1A 0 +OP4 E00C1B 0 +OP4 E00C1C 0 +OP4 E00C1D 0 +OP4 E00C1E 0 +OP4 E00C1F 0 +OP4 E00C20 0 +OP4 E00C21 0 +OP4 E00C22 0 +OP4 E00C23 0 +OP4 E00C24 0 +OP4 E00C25 0 +OP4 E00C26 0 +OP4 E00C27 0 +OP4 E00C28 0 +OP4 E00C29 0 +OP4 E00C2A 0 +OP4 E00C2B 0 +OP4 E00C2C 0 +OP4 E00C2D 0 +OP4 E00C2E 0 +OP4 E00C2F 0 +OP4 E00C30 0 +OP4 E00C31 0 +OP4 E00C32 0 +OP4 E00C33 0 +OP4 E00C34 0 +OP4 E00C35 0 +OP4 E00C36 0 +OP4 E00C37 0 +OP4 E00C38 0 +OP4 E00C39 0 +OP4 E00C3A 0 +OP4 E00C3B 0 +OP4 E00C3C 0 +OP4 E00C3D 0 +OP4 E00C3E 0 +OP4 E00C3F 0 +OP4 E00C40 0 +OP4 E00C41 0 +OP4 E00C42 0 +OP4 E00C43 0 +OP4 E00C44 0 +OP4 E00C45 0 +OP4 E00C46 0 +OP4 E00C47 0 +OP4 E00C48 0 +OP4 E00C49 0 +OP4 E00C4A 0 +OP4 E00C4B 0 +OP4 E00C4C 0 +OP4 E00C4D 0 +OP4 E00C4E 0 +OP4 E00C4F 0 +OP4 E00C50 0 +OP4 E00C51 0 +OP4 E00C52 0 +OP4 E00C53 0 +OP4 E00C54 0 +OP4 E00C55 0 +OP4 E00C56 0 +OP4 E00C57 0 +OP4 E00C58 0 +OP4 E00C59 0 +OP4 E00C5A 0 +OP4 E00C5B 0 +OP4 E00C5C 0 +OP4 E00C5D 0 +OP4 E00C5E 0 +OP4 E00C5F 0 +OP4 E00C60 0 +OP4 E00C61 0 +OP4 E00C62 0 +OP4 E00C63 0 +OP4 E00C64 0 +OP4 E00C65 0 +OP4 E00C66 0 +OP4 E00C67 0 +OP4 E00C68 0 +OP4 E00C69 0 +OP4 E00C6A 0 +OP4 E00C6B 0 +OP4 E00C6C 0 +OP4 E00C6D 0 +OP4 E00C6E 0 +OP4 E00C6F 0 +OP4 E00C70 0 +OP4 E00C71 0 +OP4 E00C72 0 +OP4 E00C73 0 +OP4 E00C74 0 +OP4 E00C75 0 +OP4 E00C76 0 +OP4 E00C77 0 +OP4 E00C78 0 +OP4 E00C79 0 +OP4 E00C7A 0 +OP4 E00C7B 0 +OP4 E00C7C 0 +OP4 E00C7D 0 +OP4 E00C7E 0 +OP4 E00C7F 0 +OP4 E00C80 0 +OP4 E00C81 0 +OP4 E00C82 0 +OP4 E00C83 0 +OP4 E00C84 0 +OP4 E00C85 0 +OP4 E00C86 0 +OP4 E00C87 0 +OP4 E00C88 0 +OP4 E00C89 0 +OP4 E00C8A 0 +OP4 E00C8B 0 +OP4 E00C8C 0 +OP4 E00C8D 0 +OP4 E00C8E 0 +OP4 E00C8F 0 +OP4 E00C90 0 +OP4 E00C91 0 +OP4 E00C92 0 +OP4 E00C93 0 +OP4 E00C94 0 +OP4 E00C95 0 +OP4 E00C96 0 +OP4 E00C97 0 +OP4 E00C98 0 +OP4 E00C99 0 +OP4 E00C9A 0 +OP4 E00C9B 0 +OP4 E00C9C 0 +OP4 E00C9D 0 +OP4 E00C9E 0 +OP4 E00C9F 0 +OP4 E00CA0 0 +OP4 E00CA1 0 +OP4 E00CA2 0 +OP4 E00CA3 0 +OP4 E00CA4 0 +OP4 E00CA5 0 +OP4 E00CA6 0 +OP4 E00CA7 0 +OP4 E00CA8 0 +OP4 E00CA9 0 +OP4 E00CAA 0 +OP4 E00CAB 0 +OP4 E00CAC 0 +OP4 E00CAD 0 +OP4 E00CAE 0 +OP4 E00CAF 0 +OP4 E00CB0 0 +OP4 E00CB1 0 +OP4 E00CB2 0 +OP4 E00CB3 0 +OP4 E00CB4 0 +OP4 E00CB5 0 +OP4 E00CB6 0 +OP4 E00CB7 0 +OP4 E00CB8 0 +OP4 E00CB9 0 +OP4 E00CBA 0 +OP4 E00CBB 0 +OP4 E00CBC 0 +OP4 E00CBD 0 +OP4 E00CBE 0 +OP4 E00CBF 0 +OP4 E00CC0 0 +OP4 E00CC1 0 +OP4 E00CC2 0 +OP4 E00CC3 0 +OP4 E00CC4 0 +OP4 E00CC5 0 +OP4 E00CC6 0 +OP4 E00CC7 0 +OP4 E00CC8 0 +OP4 E00CC9 0 +OP4 E00CCA 0 +OP4 E00CCB 0 +OP4 E00CCC 0 +OP4 E00CCD 0 +OP4 E00CCE 0 +OP4 E00CCF 0 +OP4 E00CD0 0 +OP4 E00CD1 0 +OP4 E00CD2 0 +OP4 E00CD3 0 +OP4 E00CD4 0 +OP4 E00CD5 0 +OP4 E00CD6 0 +OP4 E00CD7 0 +OP4 E00CD8 0 +OP4 E00CD9 0 +OP4 E00CDA 0 +OP4 E00CDB 0 +OP4 E00CDC 0 +OP4 E00CDD 0 +OP4 E00CDE 0 +OP4 E00CDF 0 +OP4 E00CE0 0 +OP4 E00CE1 0 +OP4 E00CE2 0 +OP4 E00CE3 0 +OP4 E00CE4 0 +OP4 E00CE5 0 +OP4 E00CE6 0 +OP4 E00CE7 0 +OP4 E00CE8 0 +OP4 E00CE9 0 +OP4 E00CEA 0 +OP4 E00CEB 0 +OP4 E00CEC 0 +OP4 E00CED 0 +OP4 E00CEE 0 +OP4 E00CEF 0 +OP4 E00CF0 0 +OP4 E00CF1 0 +OP4 E00CF2 0 +OP4 E00CF3 0 +OP4 E00CF4 0 +OP4 E00CF5 0 +OP4 E00CF6 0 +OP4 E00CF7 0 +OP4 E00CF8 0 +OP4 E00CF9 0 +OP4 E00CFA 0 +OP4 E00CFB 0 +OP4 E00CFC 0 +OP4 E00CFD 0 +OP4 E00CFE 0 +OP4 E00CFF 0 +OP4 E00D00 0 +OP4 E00D01 0 +OP4 E00D02 0 +OP4 E00D03 0 +OP4 E00D04 0 +OP4 E00D05 0 +OP4 E00D06 0 +OP4 E00D07 0 +OP4 E00D08 0 +OP4 E00D09 0 +OP4 E00D0A 0 +OP4 E00D0B 0 +OP4 E00D0C 0 +OP4 E00D0D 0 +OP4 E00D0E 0 +OP4 E00D0F 0 +OP4 E00D10 0 +OP4 E00D11 0 +OP4 E00D12 0 +OP4 E00D13 0 +OP4 E00D14 0 +OP4 E00D15 0 +OP4 E00D16 0 +OP4 E00D17 0 +OP4 E00D18 0 +OP4 E00D19 0 +OP4 E00D1A 0 +OP4 E00D1B 0 +OP4 E00D1C 0 +OP4 E00D1D 0 +OP4 E00D1E 0 +OP4 E00D1F 0 +OP4 E00D20 0 +OP4 E00D21 0 +OP4 E00D22 0 +OP4 E00D23 0 +OP4 E00D24 0 +OP4 E00D25 0 +OP4 E00D26 0 +OP4 E00D27 0 +OP4 E00D28 0 +OP4 E00D29 0 +OP4 E00D2A 0 +OP4 E00D2B 0 +OP4 E00D2C 0 +OP4 E00D2D 0 +OP4 E00D2E 0 +OP4 E00D2F 0 +OP4 E00D30 0 +OP4 E00D31 0 +OP4 E00D32 0 +OP4 E00D33 0 +OP4 E00D34 0 +OP4 E00D35 0 +OP4 E00D36 0 +OP4 E00D37 0 +OP4 E00D38 0 +OP4 E00D39 0 +OP4 E00D3A 0 +OP4 E00D3B 0 +OP4 E00D3C 0 +OP4 E00D3D 0 +OP4 E00D3E 0 +OP4 E00D3F 0 +OP4 E00D40 0 +OP4 E00D41 0 +OP4 E00D42 0 +OP4 E00D43 0 +OP4 E00D44 0 +OP4 E00D45 0 +OP4 E00D46 0 +OP4 E00D47 0 +OP4 E00D48 0 +OP4 E00D49 0 +OP4 E00D4A 0 +OP4 E00D4B 0 +OP4 E00D4C 0 +OP4 E00D4D 0 +OP4 E00D4E 0 +OP4 E00D4F 0 +OP4 E00D50 0 +OP4 E00D51 0 +OP4 E00D52 0 +OP4 E00D53 0 +OP4 E00D54 0 +OP4 E00D55 0 +OP4 E00D56 0 +OP4 E00D57 0 +OP4 E00D58 0 +OP4 E00D59 0 +OP4 E00D5A 0 +OP4 E00D5B 0 +OP4 E00D5C 0 +OP4 E00D5D 0 +OP4 E00D5E 0 +OP4 E00D5F 0 +OP4 E00D60 0 +OP4 E00D61 0 +OP4 E00D62 0 +OP4 E00D63 0 +OP4 E00D64 0 +OP4 E00D65 0 +OP4 E00D66 0 +OP4 E00D67 0 +OP4 E00D68 0 +OP4 E00D69 0 +OP4 E00D6A 0 +OP4 E00D6B 0 +OP4 E00D6C 0 +OP4 E00D6D 0 +OP4 E00D6E 0 +OP4 E00D6F 0 +OP4 E00D70 0 +OP4 E00D71 0 +OP4 E00D72 0 +OP4 E00D73 0 +OP4 E00D74 0 +OP4 E00D75 0 +OP4 E00D76 0 +OP4 E00D77 0 +OP4 E00D78 0 +OP4 E00D79 0 +OP4 E00D7A 0 +OP4 E00D7B 0 +OP4 E00D7C 0 +OP4 E00D7D 0 +OP4 E00D7E 0 +OP4 E00D7F 0 +OP4 E00D80 0 +OP4 E00D81 0 +OP4 E00D82 0 +OP4 E00D83 0 +OP4 E00D84 0 +OP4 E00D85 0 +OP4 E00D86 0 +OP4 E00D87 0 +OP4 E00D88 0 +OP4 E00D89 0 +OP4 E00D8A 0 +OP4 E00D8B 0 +OP4 E00D8C 0 +OP4 E00D8D 0 +OP4 E00D8E 0 +OP4 E00D8F 0 +OP4 E00D90 0 +OP4 E00D91 0 +OP4 E00D92 0 +OP4 E00D93 0 +OP4 E00D94 0 +OP4 E00D95 0 +OP4 E00D96 0 +OP4 E00D97 0 +OP4 E00D98 0 +OP4 E00D99 0 +OP4 E00D9A 0 +OP4 E00D9B 0 +OP4 E00D9C 0 +OP4 E00D9D 0 +OP4 E00D9E 0 +OP4 E00D9F 0 +OP4 E00DA0 0 +OP4 E00DA1 0 +OP4 E00DA2 0 +OP4 E00DA3 0 +OP4 E00DA4 0 +OP4 E00DA5 0 +OP4 E00DA6 0 +OP4 E00DA7 0 +OP4 E00DA8 0 +OP4 E00DA9 0 +OP4 E00DAA 0 +OP4 E00DAB 0 +OP4 E00DAC 0 +OP4 E00DAD 0 +OP4 E00DAE 0 +OP4 E00DAF 0 +OP4 E00DB0 0 +OP4 E00DB1 0 +OP4 E00DB2 0 +OP4 E00DB3 0 +OP4 E00DB4 0 +OP4 E00DB5 0 +OP4 E00DB6 0 +OP4 E00DB7 0 +OP4 E00DB8 0 +OP4 E00DB9 0 +OP4 E00DBA 0 +OP4 E00DBB 0 +OP4 E00DBC 0 +OP4 E00DBD 0 +OP4 E00DBE 0 +OP4 E00DBF 0 +OP4 E00DC0 0 +OP4 E00DC1 0 +OP4 E00DC2 0 +OP4 E00DC3 0 +OP4 E00DC4 0 +OP4 E00DC5 0 +OP4 E00DC6 0 +OP4 E00DC7 0 +OP4 E00DC8 0 +OP4 E00DC9 0 +OP4 E00DCA 0 +OP4 E00DCB 0 +OP4 E00DCC 0 +OP4 E00DCD 0 +OP4 E00DCE 0 +OP4 E00DCF 0 +OP4 E00DD0 0 +OP4 E00DD1 0 +OP4 E00DD2 0 +OP4 E00DD3 0 +OP4 E00DD4 0 +OP4 E00DD5 0 +OP4 E00DD6 0 +OP4 E00DD7 0 +OP4 E00DD8 0 +OP4 E00DD9 0 +OP4 E00DDA 0 +OP4 E00DDB 0 +OP4 E00DDC 0 +OP4 E00DDD 0 +OP4 E00DDE 0 +OP4 E00DDF 0 +OP4 E00DE0 0 +OP4 E00DE1 0 +OP4 E00DE2 0 +OP4 E00DE3 0 +OP4 E00DE4 0 +OP4 E00DE5 0 +OP4 E00DE6 0 +OP4 E00DE7 0 +OP4 E00DE8 0 +OP4 E00DE9 0 +OP4 E00DEA 0 +OP4 E00DEB 0 +OP4 E00DEC 0 +OP4 E00DED 0 +OP4 E00DEE 0 +OP4 E00DEF 0 +OP4 E00DF0 0 +OP4 E00DF1 0 +OP4 E00DF2 0 +OP4 E00DF3 0 +OP4 E00DF4 0 +OP4 E00DF5 0 +OP4 E00DF6 0 +OP4 E00DF7 0 +OP4 E00DF8 0 +OP4 E00DF9 0 +OP4 E00DFA 0 +OP4 E00DFB 0 +OP4 E00DFC 0 +OP4 E00DFD 0 +OP4 E00DFE 0 +OP4 E00DFF 0 +OP4 E00E00 0 +OP4 E00E01 0 +OP4 E00E02 0 +OP4 E00E03 0 +OP4 E00E04 0 +OP4 E00E05 0 +OP4 E00E06 0 +OP4 E00E07 0 +OP4 E00E08 0 +OP4 E00E09 0 +OP4 E00E0A 0 +OP4 E00E0B 0 +OP4 E00E0C 0 +OP4 E00E0D 0 +OP4 E00E0E 0 +OP4 E00E0F 0 +OP4 E00E10 0 +OP4 E00E11 0 +OP4 E00E12 0 +OP4 E00E13 0 +OP4 E00E14 0 +OP4 E00E15 0 +OP4 E00E16 0 +OP4 E00E17 0 +OP4 E00E18 0 +OP4 E00E19 0 +OP4 E00E1A 0 +OP4 E00E1B 0 +OP4 E00E1C 0 +OP4 E00E1D 0 +OP4 E00E1E 0 +OP4 E00E1F 0 +OP4 E00E20 0 +OP4 E00E21 0 +OP4 E00E22 0 +OP4 E00E23 0 +OP4 E00E24 0 +OP4 E00E25 0 +OP4 E00E26 0 +OP4 E00E27 0 +OP4 E00E28 0 +OP4 E00E29 0 +OP4 E00E2A 0 +OP4 E00E2B 0 +OP4 E00E2C 0 +OP4 E00E2D 0 +OP4 E00E2E 0 +OP4 E00E2F 0 +OP4 E00E30 0 +OP4 E00E31 0 +OP4 E00E32 0 +OP4 E00E33 0 +OP4 E00E34 0 +OP4 E00E35 0 +OP4 E00E36 0 +OP4 E00E37 0 +OP4 E00E38 0 +OP4 E00E39 0 +OP4 E00E3A 0 +OP4 E00E3B 0 +OP4 E00E3C 0 +OP4 E00E3D 0 +OP4 E00E3E 0 +OP4 E00E3F 0 +OP4 E00E40 0 +OP4 E00E41 0 +OP4 E00E42 0 +OP4 E00E43 0 +OP4 E00E44 0 +OP4 E00E45 0 +OP4 E00E46 0 +OP4 E00E47 0 +OP4 E00E48 0 +OP4 E00E49 0 +OP4 E00E4A 0 +OP4 E00E4B 0 +OP4 E00E4C 0 +OP4 E00E4D 0 +OP4 E00E4E 0 +OP4 E00E4F 0 +OP4 E00E50 0 +OP4 E00E51 0 +OP4 E00E52 0 +OP4 E00E53 0 +OP4 E00E54 0 +OP4 E00E55 0 +OP4 E00E56 0 +OP4 E00E57 0 +OP4 E00E58 0 +OP4 E00E59 0 +OP4 E00E5A 0 +OP4 E00E5B 0 +OP4 E00E5C 0 +OP4 E00E5D 0 +OP4 E00E5E 0 +OP4 E00E5F 0 +OP4 E00E60 0 +OP4 E00E61 0 +OP4 E00E62 0 +OP4 E00E63 0 +OP4 E00E64 0 +OP4 E00E65 0 +OP4 E00E66 0 +OP4 E00E67 0 +OP4 E00E68 0 +OP4 E00E69 0 +OP4 E00E6A 0 +OP4 E00E6B 0 +OP4 E00E6C 0 +OP4 E00E6D 0 +OP4 E00E6E 0 +OP4 E00E6F 0 +OP4 E00E70 0 +OP4 E00E71 0 +OP4 E00E72 0 +OP4 E00E73 0 +OP4 E00E74 0 +OP4 E00E75 0 +OP4 E00E76 0 +OP4 E00E77 0 +OP4 E00E78 0 +OP4 E00E79 0 +OP4 E00E7A 0 +OP4 E00E7B 0 +OP4 E00E7C 0 +OP4 E00E7D 0 +OP4 E00E7E 0 +OP4 E00E7F 0 +OP4 E00E80 0 +OP4 E00E81 0 +OP4 E00E82 0 +OP4 E00E83 0 +OP4 E00E84 0 +OP4 E00E85 0 +OP4 E00E86 0 +OP4 E00E87 0 +OP4 E00E88 0 +OP4 E00E89 0 +OP4 E00E8A 0 +OP4 E00E8B 0 +OP4 E00E8C 0 +OP4 E00E8D 0 +OP4 E00E8E 0 +OP4 E00E8F 0 +OP4 E00E90 0 +OP4 E00E91 0 +OP4 E00E92 0 +OP4 E00E93 0 +OP4 E00E94 0 +OP4 E00E95 0 +OP4 E00E96 0 +OP4 E00E97 0 +OP4 E00E98 0 +OP4 E00E99 0 +OP4 E00E9A 0 +OP4 E00E9B 0 +OP4 E00E9C 0 +OP4 E00E9D 0 +OP4 E00E9E 0 +OP4 E00E9F 0 +OP4 E00EA0 0 +OP4 E00EA1 0 +OP4 E00EA2 0 +OP4 E00EA3 0 +OP4 E00EA4 0 +OP4 E00EA5 0 +OP4 E00EA6 0 +OP4 E00EA7 0 +OP4 E00EA8 0 +OP4 E00EA9 0 +OP4 E00EAA 0 +OP4 E00EAB 0 +OP4 E00EAC 0 +OP4 E00EAD 0 +OP4 E00EAE 0 +OP4 E00EAF 0 +OP4 E00EB0 0 +OP4 E00EB1 0 +OP4 E00EB2 0 +OP4 E00EB3 0 +OP4 E00EB4 0 +OP4 E00EB5 0 +OP4 E00EB6 0 +OP4 E00EB7 0 +OP4 E00EB8 0 +OP4 E00EB9 0 +OP4 E00EBA 0 +OP4 E00EBB 0 +OP4 E00EBC 0 +OP4 E00EBD 0 +OP4 E00EBE 0 +OP4 E00EBF 0 +OP4 E00EC0 0 +OP4 E00EC1 0 +OP4 E00EC2 0 +OP4 E00EC3 0 +OP4 E00EC4 0 +OP4 E00EC5 0 +OP4 E00EC6 0 +OP4 E00EC7 0 +OP4 E00EC8 0 +OP4 E00EC9 0 +OP4 E00ECA 0 +OP4 E00ECB 0 +OP4 E00ECC 0 +OP4 E00ECD 0 +OP4 E00ECE 0 +OP4 E00ECF 0 +OP4 E00ED0 0 +OP4 E00ED1 0 +OP4 E00ED2 0 +OP4 E00ED3 0 +OP4 E00ED4 0 +OP4 E00ED5 0 +OP4 E00ED6 0 +OP4 E00ED7 0 +OP4 E00ED8 0 +OP4 E00ED9 0 +OP4 E00EDA 0 +OP4 E00EDB 0 +OP4 E00EDC 0 +OP4 E00EDD 0 +OP4 E00EDE 0 +OP4 E00EDF 0 +OP4 E00EE0 0 +OP4 E00EE1 0 +OP4 E00EE2 0 +OP4 E00EE3 0 +OP4 E00EE4 0 +OP4 E00EE5 0 +OP4 E00EE6 0 +OP4 E00EE7 0 +OP4 E00EE8 0 +OP4 E00EE9 0 +OP4 E00EEA 0 +OP4 E00EEB 0 +OP4 E00EEC 0 +OP4 E00EED 0 +OP4 E00EEE 0 +OP4 E00EEF 0 +OP4 E00EF0 0 +OP4 E00EF1 0 +OP4 E00EF2 0 +OP4 E00EF3 0 +OP4 E00EF4 0 +OP4 E00EF5 0 +OP4 E00EF6 0 +OP4 E00EF7 0 +OP4 E00EF8 0 +OP4 E00EF9 0 +OP4 E00EFA 0 +OP4 E00EFB 0 +OP4 E00EFC 0 +OP4 E00EFD 0 +OP4 E00EFE 0 +OP4 E00EFF 0 +OP4 E00F00 0 +OP4 E00F01 0 +OP4 E00F02 0 +OP4 E00F03 0 +OP4 E00F04 0 +OP4 E00F05 0 +OP4 E00F06 0 +OP4 E00F07 0 +OP4 E00F08 0 +OP4 E00F09 0 +OP4 E00F0A 0 +OP4 E00F0B 0 +OP4 E00F0C 0 +OP4 E00F0D 0 +OP4 E00F0E 0 +OP4 E00F0F 0 +OP4 E00F10 0 +OP4 E00F11 0 +OP4 E00F12 0 +OP4 E00F13 0 +OP4 E00F14 0 +OP4 E00F15 0 +OP4 E00F16 0 +OP4 E00F17 0 +OP4 E00F18 0 +OP4 E00F19 0 +OP4 E00F1A 0 +OP4 E00F1B 0 +OP4 E00F1C 0 +OP4 E00F1D 0 +OP4 E00F1E 0 +OP4 E00F1F 0 +OP4 E00F20 0 +OP4 E00F21 0 +OP4 E00F22 0 +OP4 E00F23 0 +OP4 E00F24 0 +OP4 E00F25 0 +OP4 E00F26 0 +OP4 E00F27 0 +OP4 E00F28 0 +OP4 E00F29 0 +OP4 E00F2A 0 +OP4 E00F2B 0 +OP4 E00F2C 0 +OP4 E00F2D 0 +OP4 E00F2E 0 +OP4 E00F2F 0 +OP4 E00F30 0 diff --git a/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum3_itrace_irisc0.cfg.ext b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum3_itrace_irisc0.cfg.ext new file mode 100644 index 000000000000..c64287d78034 --- /dev/null +++ b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum3_itrace_irisc0.cfg.ext @@ -0,0 +1,3890 @@ +OP1 Spectrum3 +OP4 ITRACE0 1 +OP4 ITRACE1 0 +OP4 ITRACE2 0 +OP4 ITRACE3 0 +OP4 ITRACE4 0 +OP4 ITRACE5 0 +OP4 ITRACE6 0 +OP4 ITRACE7 0 +OP4 ITRACE8 0 +OP4 ITRACE9 0 +OP4 Main_PhyUC 0 +OP4 TILE0_ITRACE0 0 +OP4 TILE0_ITRACE1 0 +OP4 TILE0_ITRACE2 0 +OP4 TILE0_ITRACE3 0 +OP4 TILE0_ITRACE4 0 +OP4 TILE0_PhyUC 0 +OP4 TILE1_ITRACE0 0 +OP4 TILE1_ITRACE1 0 +OP4 TILE1_ITRACE2 0 +OP4 TILE1_ITRACE3 0 +OP4 TILE1_ITRACE4 0 +OP4 TILE1_PhyUC 0 +OP4 TILE2_ITRACE0 0 +OP4 TILE2_ITRACE1 0 +OP4 TILE2_ITRACE2 0 +OP4 TILE2_ITRACE3 0 +OP4 TILE2_ITRACE4 0 +OP4 TILE2_PhyUC 0 +OP4 TILE3_ITRACE0 0 +OP4 TILE3_ITRACE1 0 +OP4 TILE3_ITRACE2 0 +OP4 TILE3_ITRACE3 0 +OP4 TILE3_ITRACE4 0 +OP4 TILE3_PhyUC 0 +OP4 TILE4_ITRACE0 0 +OP4 TILE4_ITRACE1 0 +OP4 TILE4_ITRACE2 0 +OP4 TILE4_ITRACE3 0 +OP4 TILE4_ITRACE4 0 +OP4 TILE4_PhyUC 0 +OP4 TILE5_ITRACE0 0 +OP4 TILE5_ITRACE1 0 +OP4 TILE5_ITRACE2 0 +OP4 TILE5_ITRACE3 0 +OP4 TILE5_ITRACE4 0 +OP4 TILE5_PhyUC 0 +OP4 TILE6_ITRACE0 0 +OP4 TILE6_ITRACE1 0 +OP4 TILE6_ITRACE2 0 +OP4 TILE6_ITRACE3 0 +OP4 TILE6_ITRACE4 0 +OP4 TILE6_PhyUC 0 +OP4 TILE7_ITRACE0 0 +OP4 TILE7_ITRACE1 0 +OP4 TILE7_ITRACE2 0 +OP4 TILE7_ITRACE3 0 +OP4 TILE7_ITRACE4 0 +OP4 TILE7_PhyUC 0 +OP4 E0003B 0 +OP4 E0003C 0 +OP4 E0003D 0 +OP4 E0003E 0 +OP4 E0003F 0 +OP4 E00040 0 +OP4 E00041 0 +OP4 E00042 0 +OP4 E00043 0 +OP4 E00044 0 +OP4 E00045 0 +OP4 E00046 0 +OP4 E00047 0 +OP4 E00048 0 +OP4 E00049 0 +OP4 E0004A 0 +OP4 E0004B 0 +OP4 E0004C 0 +OP4 E0004D 0 +OP4 E0004E 0 +OP4 E0004F 0 +OP4 E00050 0 +OP4 E00051 0 +OP4 E00052 0 +OP4 E00053 0 +OP4 E00054 0 +OP4 E00055 0 +OP4 E00056 0 +OP4 E00057 0 +OP4 E00058 0 +OP4 E00059 0 +OP4 E0005A 0 +OP4 E0005B 0 +OP4 E0005C 0 +OP4 E0005D 0 +OP4 E0005E 0 +OP4 E0005F 0 +OP4 E00060 0 +OP4 E00061 0 +OP4 E00062 0 +OP4 E00063 0 +OP4 E00064 0 +OP4 E00065 0 +OP4 E00066 0 +OP4 E00067 0 +OP4 E00068 0 +OP4 E00069 0 +OP4 E0006A 0 +OP4 E0006B 0 +OP4 E0006C 0 +OP4 E0006D 0 +OP4 E0006E 0 +OP4 E0006F 0 +OP4 E00070 0 +OP4 E00071 0 +OP4 E00072 0 +OP4 E00073 0 +OP4 E00074 0 +OP4 E00075 0 +OP4 E00076 0 +OP4 E00077 0 +OP4 E00078 0 +OP4 E00079 0 +OP4 E0007A 0 +OP4 E0007B 0 +OP4 E0007C 0 +OP4 E0007D 0 +OP4 E0007E 0 +OP4 E0007F 0 +OP4 E00080 0 +OP4 E00081 0 +OP4 E00082 0 +OP4 E00083 0 +OP4 E00084 0 +OP4 E00085 0 +OP4 E00086 0 +OP4 E00087 0 +OP4 E00088 0 +OP4 E00089 0 +OP4 E0008A 0 +OP4 E0008B 0 +OP4 E0008C 0 +OP4 E0008D 0 +OP4 E0008E 0 +OP4 E0008F 0 +OP4 E00090 0 +OP4 E00091 0 +OP4 E00092 0 +OP4 E00093 0 +OP4 E00094 0 +OP4 E00095 0 +OP4 E00096 0 +OP4 E00097 0 +OP4 E00098 0 +OP4 E00099 0 +OP4 E0009A 0 +OP4 E0009B 0 +OP4 E0009C 0 +OP4 E0009D 0 +OP4 E0009E 0 +OP4 E0009F 0 +OP4 E000A0 0 +OP4 E000A1 0 +OP4 E000A2 0 +OP4 E000A3 0 +OP4 E000A4 0 +OP4 E000A5 0 +OP4 E000A6 0 +OP4 E000A7 0 +OP4 E000A8 0 +OP4 E000A9 0 +OP4 E000AA 0 +OP4 E000AB 0 +OP4 E000AC 0 +OP4 E000AD 0 +OP4 E000AE 0 +OP4 E000AF 0 +OP4 E000B0 0 +OP4 E000B1 0 +OP4 E000B2 0 +OP4 E000B3 0 +OP4 E000B4 0 +OP4 E000B5 0 +OP4 E000B6 0 +OP4 E000B7 0 +OP4 E000B8 0 +OP4 E000B9 0 +OP4 E000BA 0 +OP4 E000BB 0 +OP4 E000BC 0 +OP4 E000BD 0 +OP4 E000BE 0 +OP4 E000BF 0 +OP4 E000C0 0 +OP4 E000C1 0 +OP4 E000C2 0 +OP4 E000C3 0 +OP4 E000C4 0 +OP4 E000C5 0 +OP4 E000C6 0 +OP4 E000C7 0 +OP4 E000C8 0 +OP4 E000C9 0 +OP4 E000CA 0 +OP4 E000CB 0 +OP4 E000CC 0 +OP4 E000CD 0 +OP4 E000CE 0 +OP4 E000CF 0 +OP4 E000D0 0 +OP4 E000D1 0 +OP4 E000D2 0 +OP4 E000D3 0 +OP4 E000D4 0 +OP4 E000D5 0 +OP4 E000D6 0 +OP4 E000D7 0 +OP4 E000D8 0 +OP4 E000D9 0 +OP4 E000DA 0 +OP4 E000DB 0 +OP4 E000DC 0 +OP4 E000DD 0 +OP4 E000DE 0 +OP4 E000DF 0 +OP4 E000E0 0 +OP4 E000E1 0 +OP4 E000E2 0 +OP4 E000E3 0 +OP4 E000E4 0 +OP4 E000E5 0 +OP4 E000E6 0 +OP4 E000E7 0 +OP4 E000E8 0 +OP4 E000E9 0 +OP4 E000EA 0 +OP4 E000EB 0 +OP4 E000EC 0 +OP4 E000ED 0 +OP4 E000EE 0 +OP4 E000EF 0 +OP4 E000F0 0 +OP4 E000F1 0 +OP4 E000F2 0 +OP4 E000F3 0 +OP4 E000F4 0 +OP4 E000F5 0 +OP4 E000F6 0 +OP4 E000F7 0 +OP4 E000F8 0 +OP4 E000F9 0 +OP4 E000FA 0 +OP4 E000FB 0 +OP4 E000FC 0 +OP4 E000FD 0 +OP4 E000FE 0 +OP4 E000FF 0 +OP4 E00100 0 +OP4 E00101 0 +OP4 E00102 0 +OP4 E00103 0 +OP4 E00104 0 +OP4 E00105 0 +OP4 E00106 0 +OP4 E00107 0 +OP4 E00108 0 +OP4 E00109 0 +OP4 E0010A 0 +OP4 E0010B 0 +OP4 E0010C 0 +OP4 E0010D 0 +OP4 E0010E 0 +OP4 E0010F 0 +OP4 E00110 0 +OP4 E00111 0 +OP4 E00112 0 +OP4 E00113 0 +OP4 E00114 0 +OP4 E00115 0 +OP4 E00116 0 +OP4 E00117 0 +OP4 E00118 0 +OP4 E00119 0 +OP4 E0011A 0 +OP4 E0011B 0 +OP4 E0011C 0 +OP4 E0011D 0 +OP4 E0011E 0 +OP4 E0011F 0 +OP4 E00120 0 +OP4 E00121 0 +OP4 E00122 0 +OP4 E00123 0 +OP4 E00124 0 +OP4 E00125 0 +OP4 E00126 0 +OP4 E00127 0 +OP4 E00128 0 +OP4 E00129 0 +OP4 E0012A 0 +OP4 E0012B 0 +OP4 E0012C 0 +OP4 E0012D 0 +OP4 E0012E 0 +OP4 E0012F 0 +OP4 E00130 0 +OP4 E00131 0 +OP4 E00132 0 +OP4 E00133 0 +OP4 E00134 0 +OP4 E00135 0 +OP4 E00136 0 +OP4 E00137 0 +OP4 E00138 0 +OP4 E00139 0 +OP4 E0013A 0 +OP4 E0013B 0 +OP4 E0013C 0 +OP4 E0013D 0 +OP4 E0013E 0 +OP4 E0013F 0 +OP4 E00140 0 +OP4 E00141 0 +OP4 E00142 0 +OP4 E00143 0 +OP4 E00144 0 +OP4 E00145 0 +OP4 E00146 0 +OP4 E00147 0 +OP4 E00148 0 +OP4 E00149 0 +OP4 E0014A 0 +OP4 E0014B 0 +OP4 E0014C 0 +OP4 E0014D 0 +OP4 E0014E 0 +OP4 E0014F 0 +OP4 E00150 0 +OP4 E00151 0 +OP4 E00152 0 +OP4 E00153 0 +OP4 E00154 0 +OP4 E00155 0 +OP4 E00156 0 +OP4 E00157 0 +OP4 E00158 0 +OP4 E00159 0 +OP4 E0015A 0 +OP4 E0015B 0 +OP4 E0015C 0 +OP4 E0015D 0 +OP4 E0015E 0 +OP4 E0015F 0 +OP4 E00160 0 +OP4 E00161 0 +OP4 E00162 0 +OP4 E00163 0 +OP4 E00164 0 +OP4 E00165 0 +OP4 E00166 0 +OP4 E00167 0 +OP4 E00168 0 +OP4 E00169 0 +OP4 E0016A 0 +OP4 E0016B 0 +OP4 E0016C 0 +OP4 E0016D 0 +OP4 E0016E 0 +OP4 E0016F 0 +OP4 E00170 0 +OP4 E00171 0 +OP4 E00172 0 +OP4 E00173 0 +OP4 E00174 0 +OP4 E00175 0 +OP4 E00176 0 +OP4 E00177 0 +OP4 E00178 0 +OP4 E00179 0 +OP4 E0017A 0 +OP4 E0017B 0 +OP4 E0017C 0 +OP4 E0017D 0 +OP4 E0017E 0 +OP4 E0017F 0 +OP4 E00180 0 +OP4 E00181 0 +OP4 E00182 0 +OP4 E00183 0 +OP4 E00184 0 +OP4 E00185 0 +OP4 E00186 0 +OP4 E00187 0 +OP4 E00188 0 +OP4 E00189 0 +OP4 E0018A 0 +OP4 E0018B 0 +OP4 E0018C 0 +OP4 E0018D 0 +OP4 E0018E 0 +OP4 E0018F 0 +OP4 E00190 0 +OP4 E00191 0 +OP4 E00192 0 +OP4 E00193 0 +OP4 E00194 0 +OP4 E00195 0 +OP4 E00196 0 +OP4 E00197 0 +OP4 E00198 0 +OP4 E00199 0 +OP4 E0019A 0 +OP4 E0019B 0 +OP4 E0019C 0 +OP4 E0019D 0 +OP4 E0019E 0 +OP4 E0019F 0 +OP4 E001A0 0 +OP4 E001A1 0 +OP4 E001A2 0 +OP4 E001A3 0 +OP4 E001A4 0 +OP4 E001A5 0 +OP4 E001A6 0 +OP4 E001A7 0 +OP4 E001A8 0 +OP4 E001A9 0 +OP4 E001AA 0 +OP4 E001AB 0 +OP4 E001AC 0 +OP4 E001AD 0 +OP4 E001AE 0 +OP4 E001AF 0 +OP4 E001B0 0 +OP4 E001B1 0 +OP4 E001B2 0 +OP4 E001B3 0 +OP4 E001B4 0 +OP4 E001B5 0 +OP4 E001B6 0 +OP4 E001B7 0 +OP4 E001B8 0 +OP4 E001B9 0 +OP4 E001BA 0 +OP4 E001BB 0 +OP4 E001BC 0 +OP4 E001BD 0 +OP4 E001BE 0 +OP4 E001BF 0 +OP4 E001C0 0 +OP4 E001C1 0 +OP4 E001C2 0 +OP4 E001C3 0 +OP4 E001C4 0 +OP4 E001C5 0 +OP4 E001C6 0 +OP4 E001C7 0 +OP4 E001C8 0 +OP4 E001C9 0 +OP4 E001CA 0 +OP4 E001CB 0 +OP4 E001CC 0 +OP4 E001CD 0 +OP4 E001CE 0 +OP4 E001CF 0 +OP4 E001D0 0 +OP4 E001D1 0 +OP4 E001D2 0 +OP4 E001D3 0 +OP4 E001D4 0 +OP4 E001D5 0 +OP4 E001D6 0 +OP4 E001D7 0 +OP4 E001D8 0 +OP4 E001D9 0 +OP4 E001DA 0 +OP4 E001DB 0 +OP4 E001DC 0 +OP4 E001DD 0 +OP4 E001DE 0 +OP4 E001DF 0 +OP4 E001E0 0 +OP4 E001E1 0 +OP4 E001E2 0 +OP4 E001E3 0 +OP4 E001E4 0 +OP4 E001E5 0 +OP4 E001E6 0 +OP4 E001E7 0 +OP4 E001E8 0 +OP4 E001E9 0 +OP4 E001EA 0 +OP4 E001EB 0 +OP4 E001EC 0 +OP4 E001ED 0 +OP4 E001EE 0 +OP4 E001EF 0 +OP4 E001F0 0 +OP4 E001F1 0 +OP4 E001F2 0 +OP4 E001F3 0 +OP4 E001F4 0 +OP4 E001F5 0 +OP4 E001F6 0 +OP4 E001F7 0 +OP4 E001F8 0 +OP4 E001F9 0 +OP4 E001FA 0 +OP4 E001FB 0 +OP4 E001FC 0 +OP4 E001FD 0 +OP4 E001FE 0 +OP4 E001FF 0 +OP4 E00200 0 +OP4 E00201 0 +OP4 E00202 0 +OP4 E00203 0 +OP4 E00204 0 +OP4 E00205 0 +OP4 E00206 0 +OP4 E00207 0 +OP4 E00208 0 +OP4 E00209 0 +OP4 E0020A 0 +OP4 E0020B 0 +OP4 E0020C 0 +OP4 E0020D 0 +OP4 E0020E 0 +OP4 E0020F 0 +OP4 E00210 0 +OP4 E00211 0 +OP4 E00212 0 +OP4 E00213 0 +OP4 E00214 0 +OP4 E00215 0 +OP4 E00216 0 +OP4 E00217 0 +OP4 E00218 0 +OP4 E00219 0 +OP4 E0021A 0 +OP4 E0021B 0 +OP4 E0021C 0 +OP4 E0021D 0 +OP4 E0021E 0 +OP4 E0021F 0 +OP4 E00220 0 +OP4 E00221 0 +OP4 E00222 0 +OP4 E00223 0 +OP4 E00224 0 +OP4 E00225 0 +OP4 E00226 0 +OP4 E00227 0 +OP4 E00228 0 +OP4 E00229 0 +OP4 E0022A 0 +OP4 E0022B 0 +OP4 E0022C 0 +OP4 E0022D 0 +OP4 E0022E 0 +OP4 E0022F 0 +OP4 E00230 0 +OP4 E00231 0 +OP4 E00232 0 +OP4 E00233 0 +OP4 E00234 0 +OP4 E00235 0 +OP4 E00236 0 +OP4 E00237 0 +OP4 E00238 0 +OP4 E00239 0 +OP4 E0023A 0 +OP4 E0023B 0 +OP4 E0023C 0 +OP4 E0023D 0 +OP4 E0023E 0 +OP4 E0023F 0 +OP4 E00240 0 +OP4 E00241 0 +OP4 E00242 0 +OP4 E00243 0 +OP4 E00244 0 +OP4 E00245 0 +OP4 E00246 0 +OP4 E00247 0 +OP4 E00248 0 +OP4 E00249 0 +OP4 E0024A 0 +OP4 E0024B 0 +OP4 E0024C 0 +OP4 E0024D 0 +OP4 E0024E 0 +OP4 E0024F 0 +OP4 E00250 0 +OP4 E00251 0 +OP4 E00252 0 +OP4 E00253 0 +OP4 E00254 0 +OP4 E00255 0 +OP4 E00256 0 +OP4 E00257 0 +OP4 E00258 0 +OP4 E00259 0 +OP4 E0025A 0 +OP4 E0025B 0 +OP4 E0025C 0 +OP4 E0025D 0 +OP4 E0025E 0 +OP4 E0025F 0 +OP4 E00260 0 +OP4 E00261 0 +OP4 E00262 0 +OP4 E00263 0 +OP4 E00264 0 +OP4 E00265 0 +OP4 E00266 0 +OP4 E00267 0 +OP4 E00268 0 +OP4 E00269 0 +OP4 E0026A 0 +OP4 E0026B 0 +OP4 E0026C 0 +OP4 E0026D 0 +OP4 E0026E 0 +OP4 E0026F 0 +OP4 E00270 0 +OP4 E00271 0 +OP4 E00272 0 +OP4 E00273 0 +OP4 E00274 0 +OP4 E00275 0 +OP4 E00276 0 +OP4 E00277 0 +OP4 E00278 0 +OP4 E00279 0 +OP4 E0027A 0 +OP4 E0027B 0 +OP4 E0027C 0 +OP4 E0027D 0 +OP4 E0027E 0 +OP4 E0027F 0 +OP4 E00280 0 +OP4 E00281 0 +OP4 E00282 0 +OP4 E00283 0 +OP4 E00284 0 +OP4 E00285 0 +OP4 E00286 0 +OP4 E00287 0 +OP4 E00288 0 +OP4 E00289 0 +OP4 E0028A 0 +OP4 E0028B 0 +OP4 E0028C 0 +OP4 E0028D 0 +OP4 E0028E 0 +OP4 E0028F 0 +OP4 E00290 0 +OP4 E00291 0 +OP4 E00292 0 +OP4 E00293 0 +OP4 E00294 0 +OP4 E00295 0 +OP4 E00296 0 +OP4 E00297 0 +OP4 E00298 0 +OP4 E00299 0 +OP4 E0029A 0 +OP4 E0029B 0 +OP4 E0029C 0 +OP4 E0029D 0 +OP4 E0029E 0 +OP4 E0029F 0 +OP4 E002A0 0 +OP4 E002A1 0 +OP4 E002A2 0 +OP4 E002A3 0 +OP4 E002A4 0 +OP4 E002A5 0 +OP4 E002A6 0 +OP4 E002A7 0 +OP4 E002A8 0 +OP4 E002A9 0 +OP4 E002AA 0 +OP4 E002AB 0 +OP4 E002AC 0 +OP4 E002AD 0 +OP4 E002AE 0 +OP4 E002AF 0 +OP4 E002B0 0 +OP4 E002B1 0 +OP4 E002B2 0 +OP4 E002B3 0 +OP4 E002B4 0 +OP4 E002B5 0 +OP4 E002B6 0 +OP4 E002B7 0 +OP4 E002B8 0 +OP4 E002B9 0 +OP4 E002BA 0 +OP4 E002BB 0 +OP4 E002BC 0 +OP4 E002BD 0 +OP4 E002BE 0 +OP4 E002BF 0 +OP4 E002C0 0 +OP4 E002C1 0 +OP4 E002C2 0 +OP4 E002C3 0 +OP4 E002C4 0 +OP4 E002C5 0 +OP4 E002C6 0 +OP4 E002C7 0 +OP4 E002C8 0 +OP4 E002C9 0 +OP4 E002CA 0 +OP4 E002CB 0 +OP4 E002CC 0 +OP4 E002CD 0 +OP4 E002CE 0 +OP4 E002CF 0 +OP4 E002D0 0 +OP4 E002D1 0 +OP4 E002D2 0 +OP4 E002D3 0 +OP4 E002D4 0 +OP4 E002D5 0 +OP4 E002D6 0 +OP4 E002D7 0 +OP4 E002D8 0 +OP4 E002D9 0 +OP4 E002DA 0 +OP4 E002DB 0 +OP4 E002DC 0 +OP4 E002DD 0 +OP4 E002DE 0 +OP4 E002DF 0 +OP4 E002E0 0 +OP4 E002E1 0 +OP4 E002E2 0 +OP4 E002E3 0 +OP4 E002E4 0 +OP4 E002E5 0 +OP4 E002E6 0 +OP4 E002E7 0 +OP4 E002E8 0 +OP4 E002E9 0 +OP4 E002EA 0 +OP4 E002EB 0 +OP4 E002EC 0 +OP4 E002ED 0 +OP4 E002EE 0 +OP4 E002EF 0 +OP4 E002F0 0 +OP4 E002F1 0 +OP4 E002F2 0 +OP4 E002F3 0 +OP4 E002F4 0 +OP4 E002F5 0 +OP4 E002F6 0 +OP4 E002F7 0 +OP4 E002F8 0 +OP4 E002F9 0 +OP4 E002FA 0 +OP4 E002FB 0 +OP4 E002FC 0 +OP4 E002FD 0 +OP4 E002FE 0 +OP4 E002FF 0 +OP4 E00300 0 +OP4 E00301 0 +OP4 E00302 0 +OP4 E00303 0 +OP4 E00304 0 +OP4 E00305 0 +OP4 E00306 0 +OP4 E00307 0 +OP4 E00308 0 +OP4 E00309 0 +OP4 E0030A 0 +OP4 E0030B 0 +OP4 E0030C 0 +OP4 E0030D 0 +OP4 E0030E 0 +OP4 E0030F 0 +OP4 E00310 0 +OP4 E00311 0 +OP4 E00312 0 +OP4 E00313 0 +OP4 E00314 0 +OP4 E00315 0 +OP4 E00316 0 +OP4 E00317 0 +OP4 E00318 0 +OP4 E00319 0 +OP4 E0031A 0 +OP4 E0031B 0 +OP4 E0031C 0 +OP4 E0031D 0 +OP4 E0031E 0 +OP4 E0031F 0 +OP4 E00320 0 +OP4 E00321 0 +OP4 E00322 0 +OP4 E00323 0 +OP4 E00324 0 +OP4 E00325 0 +OP4 E00326 0 +OP4 E00327 0 +OP4 E00328 0 +OP4 E00329 0 +OP4 E0032A 0 +OP4 E0032B 0 +OP4 E0032C 0 +OP4 E0032D 0 +OP4 E0032E 0 +OP4 E0032F 0 +OP4 E00330 0 +OP4 E00331 0 +OP4 E00332 0 +OP4 E00333 0 +OP4 E00334 0 +OP4 E00335 0 +OP4 E00336 0 +OP4 E00337 0 +OP4 E00338 0 +OP4 E00339 0 +OP4 E0033A 0 +OP4 E0033B 0 +OP4 E0033C 0 +OP4 E0033D 0 +OP4 E0033E 0 +OP4 E0033F 0 +OP4 E00340 0 +OP4 E00341 0 +OP4 E00342 0 +OP4 E00343 0 +OP4 E00344 0 +OP4 E00345 0 +OP4 E00346 0 +OP4 E00347 0 +OP4 E00348 0 +OP4 E00349 0 +OP4 E0034A 0 +OP4 E0034B 0 +OP4 E0034C 0 +OP4 E0034D 0 +OP4 E0034E 0 +OP4 E0034F 0 +OP4 E00350 0 +OP4 E00351 0 +OP4 E00352 0 +OP4 E00353 0 +OP4 E00354 0 +OP4 E00355 0 +OP4 E00356 0 +OP4 E00357 0 +OP4 E00358 0 +OP4 E00359 0 +OP4 E0035A 0 +OP4 E0035B 0 +OP4 E0035C 0 +OP4 E0035D 0 +OP4 E0035E 0 +OP4 E0035F 0 +OP4 E00360 0 +OP4 E00361 0 +OP4 E00362 0 +OP4 E00363 0 +OP4 E00364 0 +OP4 E00365 0 +OP4 E00366 0 +OP4 E00367 0 +OP4 E00368 0 +OP4 E00369 0 +OP4 E0036A 0 +OP4 E0036B 0 +OP4 E0036C 0 +OP4 E0036D 0 +OP4 E0036E 0 +OP4 E0036F 0 +OP4 E00370 0 +OP4 E00371 0 +OP4 E00372 0 +OP4 E00373 0 +OP4 E00374 0 +OP4 E00375 0 +OP4 E00376 0 +OP4 E00377 0 +OP4 E00378 0 +OP4 E00379 0 +OP4 E0037A 0 +OP4 E0037B 0 +OP4 E0037C 0 +OP4 E0037D 0 +OP4 E0037E 0 +OP4 E0037F 0 +OP4 E00380 0 +OP4 E00381 0 +OP4 E00382 0 +OP4 E00383 0 +OP4 E00384 0 +OP4 E00385 0 +OP4 E00386 0 +OP4 E00387 0 +OP4 E00388 0 +OP4 E00389 0 +OP4 E0038A 0 +OP4 E0038B 0 +OP4 E0038C 0 +OP4 E0038D 0 +OP4 E0038E 0 +OP4 E0038F 0 +OP4 E00390 0 +OP4 E00391 0 +OP4 E00392 0 +OP4 E00393 0 +OP4 E00394 0 +OP4 E00395 0 +OP4 E00396 0 +OP4 E00397 0 +OP4 E00398 0 +OP4 E00399 0 +OP4 E0039A 0 +OP4 E0039B 0 +OP4 E0039C 0 +OP4 E0039D 0 +OP4 E0039E 0 +OP4 E0039F 0 +OP4 E003A0 0 +OP4 E003A1 0 +OP4 E003A2 0 +OP4 E003A3 0 +OP4 E003A4 0 +OP4 E003A5 0 +OP4 E003A6 0 +OP4 E003A7 0 +OP4 E003A8 0 +OP4 E003A9 0 +OP4 E003AA 0 +OP4 E003AB 0 +OP4 E003AC 0 +OP4 E003AD 0 +OP4 E003AE 0 +OP4 E003AF 0 +OP4 E003B0 0 +OP4 E003B1 0 +OP4 E003B2 0 +OP4 E003B3 0 +OP4 E003B4 0 +OP4 E003B5 0 +OP4 E003B6 0 +OP4 E003B7 0 +OP4 E003B8 0 +OP4 E003B9 0 +OP4 E003BA 0 +OP4 E003BB 0 +OP4 E003BC 0 +OP4 E003BD 0 +OP4 E003BE 0 +OP4 E003BF 0 +OP4 E003C0 0 +OP4 E003C1 0 +OP4 E003C2 0 +OP4 E003C3 0 +OP4 E003C4 0 +OP4 E003C5 0 +OP4 E003C6 0 +OP4 E003C7 0 +OP4 E003C8 0 +OP4 E003C9 0 +OP4 E003CA 0 +OP4 E003CB 0 +OP4 E003CC 0 +OP4 E003CD 0 +OP4 E003CE 0 +OP4 E003CF 0 +OP4 E003D0 0 +OP4 E003D1 0 +OP4 E003D2 0 +OP4 E003D3 0 +OP4 E003D4 0 +OP4 E003D5 0 +OP4 E003D6 0 +OP4 E003D7 0 +OP4 E003D8 0 +OP4 E003D9 0 +OP4 E003DA 0 +OP4 E003DB 0 +OP4 E003DC 0 +OP4 E003DD 0 +OP4 E003DE 0 +OP4 E003DF 0 +OP4 E003E0 0 +OP4 E003E1 0 +OP4 E003E2 0 +OP4 E003E3 0 +OP4 E003E4 0 +OP4 E003E5 0 +OP4 E003E6 0 +OP4 E003E7 0 +OP4 E003E8 0 +OP4 E003E9 0 +OP4 E003EA 0 +OP4 E003EB 0 +OP4 E003EC 0 +OP4 E003ED 0 +OP4 E003EE 0 +OP4 E003EF 0 +OP4 E003F0 0 +OP4 E003F1 0 +OP4 E003F2 0 +OP4 E003F3 0 +OP4 E003F4 0 +OP4 E003F5 0 +OP4 E003F6 0 +OP4 E003F7 0 +OP4 E003F8 0 +OP4 E003F9 0 +OP4 E003FA 0 +OP4 E003FB 0 +OP4 E003FC 0 +OP4 E003FD 0 +OP4 E003FE 0 +OP4 E003FF 0 +OP4 E00400 0 +OP4 E00401 0 +OP4 E00402 0 +OP4 E00403 0 +OP4 E00404 0 +OP4 E00405 0 +OP4 E00406 0 +OP4 E00407 0 +OP4 E00408 0 +OP4 E00409 0 +OP4 E0040A 0 +OP4 E0040B 0 +OP4 E0040C 0 +OP4 E0040D 0 +OP4 E0040E 0 +OP4 E0040F 0 +OP4 E00410 0 +OP4 E00411 0 +OP4 E00412 0 +OP4 E00413 0 +OP4 E00414 0 +OP4 E00415 0 +OP4 E00416 0 +OP4 E00417 0 +OP4 E00418 0 +OP4 E00419 0 +OP4 E0041A 0 +OP4 E0041B 0 +OP4 E0041C 0 +OP4 E0041D 0 +OP4 E0041E 0 +OP4 E0041F 0 +OP4 E00420 0 +OP4 E00421 0 +OP4 E00422 0 +OP4 E00423 0 +OP4 E00424 0 +OP4 E00425 0 +OP4 E00426 0 +OP4 E00427 0 +OP4 E00428 0 +OP4 E00429 0 +OP4 E0042A 0 +OP4 E0042B 0 +OP4 E0042C 0 +OP4 E0042D 0 +OP4 E0042E 0 +OP4 E0042F 0 +OP4 E00430 0 +OP4 E00431 0 +OP4 E00432 0 +OP4 E00433 0 +OP4 E00434 0 +OP4 E00435 0 +OP4 E00436 0 +OP4 E00437 0 +OP4 E00438 0 +OP4 E00439 0 +OP4 E0043A 0 +OP4 E0043B 0 +OP4 E0043C 0 +OP4 E0043D 0 +OP4 E0043E 0 +OP4 E0043F 0 +OP4 E00440 0 +OP4 E00441 0 +OP4 E00442 0 +OP4 E00443 0 +OP4 E00444 0 +OP4 E00445 0 +OP4 E00446 0 +OP4 E00447 0 +OP4 E00448 0 +OP4 E00449 0 +OP4 E0044A 0 +OP4 E0044B 0 +OP4 E0044C 0 +OP4 E0044D 0 +OP4 E0044E 0 +OP4 E0044F 0 +OP4 E00450 0 +OP4 E00451 0 +OP4 E00452 0 +OP4 E00453 0 +OP4 E00454 0 +OP4 E00455 0 +OP4 E00456 0 +OP4 E00457 0 +OP4 E00458 0 +OP4 E00459 0 +OP4 E0045A 0 +OP4 E0045B 0 +OP4 E0045C 0 +OP4 E0045D 0 +OP4 E0045E 0 +OP4 E0045F 0 +OP4 E00460 0 +OP4 E00461 0 +OP4 E00462 0 +OP4 E00463 0 +OP4 E00464 0 +OP4 E00465 0 +OP4 E00466 0 +OP4 E00467 0 +OP4 E00468 0 +OP4 E00469 0 +OP4 E0046A 0 +OP4 E0046B 0 +OP4 E0046C 0 +OP4 E0046D 0 +OP4 E0046E 0 +OP4 E0046F 0 +OP4 E00470 0 +OP4 E00471 0 +OP4 E00472 0 +OP4 E00473 0 +OP4 E00474 0 +OP4 E00475 0 +OP4 E00476 0 +OP4 E00477 0 +OP4 E00478 0 +OP4 E00479 0 +OP4 E0047A 0 +OP4 E0047B 0 +OP4 E0047C 0 +OP4 E0047D 0 +OP4 E0047E 0 +OP4 E0047F 0 +OP4 E00480 0 +OP4 E00481 0 +OP4 E00482 0 +OP4 E00483 0 +OP4 E00484 0 +OP4 E00485 0 +OP4 E00486 0 +OP4 E00487 0 +OP4 E00488 0 +OP4 E00489 0 +OP4 E0048A 0 +OP4 E0048B 0 +OP4 E0048C 0 +OP4 E0048D 0 +OP4 E0048E 0 +OP4 E0048F 0 +OP4 E00490 0 +OP4 E00491 0 +OP4 E00492 0 +OP4 E00493 0 +OP4 E00494 0 +OP4 E00495 0 +OP4 E00496 0 +OP4 E00497 0 +OP4 E00498 0 +OP4 E00499 0 +OP4 E0049A 0 +OP4 E0049B 0 +OP4 E0049C 0 +OP4 E0049D 0 +OP4 E0049E 0 +OP4 E0049F 0 +OP4 E004A0 0 +OP4 E004A1 0 +OP4 E004A2 0 +OP4 E004A3 0 +OP4 E004A4 0 +OP4 E004A5 0 +OP4 E004A6 0 +OP4 E004A7 0 +OP4 E004A8 0 +OP4 E004A9 0 +OP4 E004AA 0 +OP4 E004AB 0 +OP4 E004AC 0 +OP4 E004AD 0 +OP4 E004AE 0 +OP4 E004AF 0 +OP4 E004B0 0 +OP4 E004B1 0 +OP4 E004B2 0 +OP4 E004B3 0 +OP4 E004B4 0 +OP4 E004B5 0 +OP4 E004B6 0 +OP4 E004B7 0 +OP4 E004B8 0 +OP4 E004B9 0 +OP4 E004BA 0 +OP4 E004BB 0 +OP4 E004BC 0 +OP4 E004BD 0 +OP4 E004BE 0 +OP4 E004BF 0 +OP4 E004C0 0 +OP4 E004C1 0 +OP4 E004C2 0 +OP4 E004C3 0 +OP4 E004C4 0 +OP4 E004C5 0 +OP4 E004C6 0 +OP4 E004C7 0 +OP4 E004C8 0 +OP4 E004C9 0 +OP4 E004CA 0 +OP4 E004CB 0 +OP4 E004CC 0 +OP4 E004CD 0 +OP4 E004CE 0 +OP4 E004CF 0 +OP4 E004D0 0 +OP4 E004D1 0 +OP4 E004D2 0 +OP4 E004D3 0 +OP4 E004D4 0 +OP4 E004D5 0 +OP4 E004D6 0 +OP4 E004D7 0 +OP4 E004D8 0 +OP4 E004D9 0 +OP4 E004DA 0 +OP4 E004DB 0 +OP4 E004DC 0 +OP4 E004DD 0 +OP4 E004DE 0 +OP4 E004DF 0 +OP4 E004E0 0 +OP4 E004E1 0 +OP4 E004E2 0 +OP4 E004E3 0 +OP4 E004E4 0 +OP4 E004E5 0 +OP4 E004E6 0 +OP4 E004E7 0 +OP4 E004E8 0 +OP4 E004E9 0 +OP4 E004EA 0 +OP4 E004EB 0 +OP4 E004EC 0 +OP4 E004ED 0 +OP4 E004EE 0 +OP4 E004EF 0 +OP4 E004F0 0 +OP4 E004F1 0 +OP4 E004F2 0 +OP4 E004F3 0 +OP4 E004F4 0 +OP4 E004F5 0 +OP4 E004F6 0 +OP4 E004F7 0 +OP4 E004F8 0 +OP4 E004F9 0 +OP4 E004FA 0 +OP4 E004FB 0 +OP4 E004FC 0 +OP4 E004FD 0 +OP4 E004FE 0 +OP4 E004FF 0 +OP4 E00500 0 +OP4 E00501 0 +OP4 E00502 0 +OP4 E00503 0 +OP4 E00504 0 +OP4 E00505 0 +OP4 E00506 0 +OP4 E00507 0 +OP4 E00508 0 +OP4 E00509 0 +OP4 E0050A 0 +OP4 E0050B 0 +OP4 E0050C 0 +OP4 E0050D 0 +OP4 E0050E 0 +OP4 E0050F 0 +OP4 E00510 0 +OP4 E00511 0 +OP4 E00512 0 +OP4 E00513 0 +OP4 E00514 0 +OP4 E00515 0 +OP4 E00516 0 +OP4 E00517 0 +OP4 E00518 0 +OP4 E00519 0 +OP4 E0051A 0 +OP4 E0051B 0 +OP4 E0051C 0 +OP4 E0051D 0 +OP4 E0051E 0 +OP4 E0051F 0 +OP4 E00520 0 +OP4 E00521 0 +OP4 E00522 0 +OP4 E00523 0 +OP4 E00524 0 +OP4 E00525 0 +OP4 E00526 0 +OP4 E00527 0 +OP4 E00528 0 +OP4 E00529 0 +OP4 E0052A 0 +OP4 E0052B 0 +OP4 E0052C 0 +OP4 E0052D 0 +OP4 E0052E 0 +OP4 E0052F 0 +OP4 E00530 0 +OP4 E00531 0 +OP4 E00532 0 +OP4 E00533 0 +OP4 E00534 0 +OP4 E00535 0 +OP4 E00536 0 +OP4 E00537 0 +OP4 E00538 0 +OP4 E00539 0 +OP4 E0053A 0 +OP4 E0053B 0 +OP4 E0053C 0 +OP4 E0053D 0 +OP4 E0053E 0 +OP4 E0053F 0 +OP4 E00540 0 +OP4 E00541 0 +OP4 E00542 0 +OP4 E00543 0 +OP4 E00544 0 +OP4 E00545 0 +OP4 E00546 0 +OP4 E00547 0 +OP4 E00548 0 +OP4 E00549 0 +OP4 E0054A 0 +OP4 E0054B 0 +OP4 E0054C 0 +OP4 E0054D 0 +OP4 E0054E 0 +OP4 E0054F 0 +OP4 E00550 0 +OP4 E00551 0 +OP4 E00552 0 +OP4 E00553 0 +OP4 E00554 0 +OP4 E00555 0 +OP4 E00556 0 +OP4 E00557 0 +OP4 E00558 0 +OP4 E00559 0 +OP4 E0055A 0 +OP4 E0055B 0 +OP4 E0055C 0 +OP4 E0055D 0 +OP4 E0055E 0 +OP4 E0055F 0 +OP4 E00560 0 +OP4 E00561 0 +OP4 E00562 0 +OP4 E00563 0 +OP4 E00564 0 +OP4 E00565 0 +OP4 E00566 0 +OP4 E00567 0 +OP4 E00568 0 +OP4 E00569 0 +OP4 E0056A 0 +OP4 E0056B 0 +OP4 E0056C 0 +OP4 E0056D 0 +OP4 E0056E 0 +OP4 E0056F 0 +OP4 E00570 0 +OP4 E00571 0 +OP4 E00572 0 +OP4 E00573 0 +OP4 E00574 0 +OP4 E00575 0 +OP4 E00576 0 +OP4 E00577 0 +OP4 E00578 0 +OP4 E00579 0 +OP4 E0057A 0 +OP4 E0057B 0 +OP4 E0057C 0 +OP4 E0057D 0 +OP4 E0057E 0 +OP4 E0057F 0 +OP4 E00580 0 +OP4 E00581 0 +OP4 E00582 0 +OP4 E00583 0 +OP4 E00584 0 +OP4 E00585 0 +OP4 E00586 0 +OP4 E00587 0 +OP4 E00588 0 +OP4 E00589 0 +OP4 E0058A 0 +OP4 E0058B 0 +OP4 E0058C 0 +OP4 E0058D 0 +OP4 E0058E 0 +OP4 E0058F 0 +OP4 E00590 0 +OP4 E00591 0 +OP4 E00592 0 +OP4 E00593 0 +OP4 E00594 0 +OP4 E00595 0 +OP4 E00596 0 +OP4 E00597 0 +OP4 E00598 0 +OP4 E00599 0 +OP4 E0059A 0 +OP4 E0059B 0 +OP4 E0059C 0 +OP4 E0059D 0 +OP4 E0059E 0 +OP4 E0059F 0 +OP4 E005A0 0 +OP4 E005A1 0 +OP4 E005A2 0 +OP4 E005A3 0 +OP4 E005A4 0 +OP4 E005A5 0 +OP4 E005A6 0 +OP4 E005A7 0 +OP4 E005A8 0 +OP4 E005A9 0 +OP4 E005AA 0 +OP4 E005AB 0 +OP4 E005AC 0 +OP4 E005AD 0 +OP4 E005AE 0 +OP4 E005AF 0 +OP4 E005B0 0 +OP4 E005B1 0 +OP4 E005B2 0 +OP4 E005B3 0 +OP4 E005B4 0 +OP4 E005B5 0 +OP4 E005B6 0 +OP4 E005B7 0 +OP4 E005B8 0 +OP4 E005B9 0 +OP4 E005BA 0 +OP4 E005BB 0 +OP4 E005BC 0 +OP4 E005BD 0 +OP4 E005BE 0 +OP4 E005BF 0 +OP4 E005C0 0 +OP4 E005C1 0 +OP4 E005C2 0 +OP4 E005C3 0 +OP4 E005C4 0 +OP4 E005C5 0 +OP4 E005C6 0 +OP4 E005C7 0 +OP4 E005C8 0 +OP4 E005C9 0 +OP4 E005CA 0 +OP4 E005CB 0 +OP4 E005CC 0 +OP4 E005CD 0 +OP4 E005CE 0 +OP4 E005CF 0 +OP4 E005D0 0 +OP4 E005D1 0 +OP4 E005D2 0 +OP4 E005D3 0 +OP4 E005D4 0 +OP4 E005D5 0 +OP4 E005D6 0 +OP4 E005D7 0 +OP4 E005D8 0 +OP4 E005D9 0 +OP4 E005DA 0 +OP4 E005DB 0 +OP4 E005DC 0 +OP4 E005DD 0 +OP4 E005DE 0 +OP4 E005DF 0 +OP4 E005E0 0 +OP4 E005E1 0 +OP4 E005E2 0 +OP4 E005E3 0 +OP4 E005E4 0 +OP4 E005E5 0 +OP4 E005E6 0 +OP4 E005E7 0 +OP4 E005E8 0 +OP4 E005E9 0 +OP4 E005EA 0 +OP4 E005EB 0 +OP4 E005EC 0 +OP4 E005ED 0 +OP4 E005EE 0 +OP4 E005EF 0 +OP4 E005F0 0 +OP4 E005F1 0 +OP4 E005F2 0 +OP4 E005F3 0 +OP4 E005F4 0 +OP4 E005F5 0 +OP4 E005F6 0 +OP4 E005F7 0 +OP4 E005F8 0 +OP4 E005F9 0 +OP4 E005FA 0 +OP4 E005FB 0 +OP4 E005FC 0 +OP4 E005FD 0 +OP4 E005FE 0 +OP4 E005FF 0 +OP4 E00600 0 +OP4 E00601 0 +OP4 E00602 0 +OP4 E00603 0 +OP4 E00604 0 +OP4 E00605 0 +OP4 E00606 0 +OP4 E00607 0 +OP4 E00608 0 +OP4 E00609 0 +OP4 E0060A 0 +OP4 E0060B 0 +OP4 E0060C 0 +OP4 E0060D 0 +OP4 E0060E 0 +OP4 E0060F 0 +OP4 E00610 0 +OP4 E00611 0 +OP4 E00612 0 +OP4 E00613 0 +OP4 E00614 0 +OP4 E00615 0 +OP4 E00616 0 +OP4 E00617 0 +OP4 E00618 0 +OP4 E00619 0 +OP4 E0061A 0 +OP4 E0061B 0 +OP4 E0061C 0 +OP4 E0061D 0 +OP4 E0061E 0 +OP4 E0061F 0 +OP4 E00620 0 +OP4 E00621 0 +OP4 E00622 0 +OP4 E00623 0 +OP4 E00624 0 +OP4 E00625 0 +OP4 E00626 0 +OP4 E00627 0 +OP4 E00628 0 +OP4 E00629 0 +OP4 E0062A 0 +OP4 E0062B 0 +OP4 E0062C 0 +OP4 E0062D 0 +OP4 E0062E 0 +OP4 E0062F 0 +OP4 E00630 0 +OP4 E00631 0 +OP4 E00632 0 +OP4 E00633 0 +OP4 E00634 0 +OP4 E00635 0 +OP4 E00636 0 +OP4 E00637 0 +OP4 E00638 0 +OP4 E00639 0 +OP4 E0063A 0 +OP4 E0063B 0 +OP4 E0063C 0 +OP4 E0063D 0 +OP4 E0063E 0 +OP4 E0063F 0 +OP4 E00640 0 +OP4 E00641 0 +OP4 E00642 0 +OP4 E00643 0 +OP4 E00644 0 +OP4 E00645 0 +OP4 E00646 0 +OP4 E00647 0 +OP4 E00648 0 +OP4 E00649 0 +OP4 E0064A 0 +OP4 E0064B 0 +OP4 E0064C 0 +OP4 E0064D 0 +OP4 E0064E 0 +OP4 E0064F 0 +OP4 E00650 0 +OP4 E00651 0 +OP4 E00652 0 +OP4 E00653 0 +OP4 E00654 0 +OP4 E00655 0 +OP4 E00656 0 +OP4 E00657 0 +OP4 E00658 0 +OP4 E00659 0 +OP4 E0065A 0 +OP4 E0065B 0 +OP4 E0065C 0 +OP4 E0065D 0 +OP4 E0065E 0 +OP4 E0065F 0 +OP4 E00660 0 +OP4 E00661 0 +OP4 E00662 0 +OP4 E00663 0 +OP4 E00664 0 +OP4 E00665 0 +OP4 E00666 0 +OP4 E00667 0 +OP4 E00668 0 +OP4 E00669 0 +OP4 E0066A 0 +OP4 E0066B 0 +OP4 E0066C 0 +OP4 E0066D 0 +OP4 E0066E 0 +OP4 E0066F 0 +OP4 E00670 0 +OP4 E00671 0 +OP4 E00672 0 +OP4 E00673 0 +OP4 E00674 0 +OP4 E00675 0 +OP4 E00676 0 +OP4 E00677 0 +OP4 E00678 0 +OP4 E00679 0 +OP4 E0067A 0 +OP4 E0067B 0 +OP4 E0067C 0 +OP4 E0067D 0 +OP4 E0067E 0 +OP4 E0067F 0 +OP4 E00680 0 +OP4 E00681 0 +OP4 E00682 0 +OP4 E00683 0 +OP4 E00684 0 +OP4 E00685 0 +OP4 E00686 0 +OP4 E00687 0 +OP4 E00688 0 +OP4 E00689 0 +OP4 E0068A 0 +OP4 E0068B 0 +OP4 E0068C 0 +OP4 E0068D 0 +OP4 E0068E 0 +OP4 E0068F 0 +OP4 E00690 0 +OP4 E00691 0 +OP4 E00692 0 +OP4 E00693 0 +OP4 E00694 0 +OP4 E00695 0 +OP4 E00696 0 +OP4 E00697 0 +OP4 E00698 0 +OP4 E00699 0 +OP4 E0069A 0 +OP4 E0069B 0 +OP4 E0069C 0 +OP4 E0069D 0 +OP4 E0069E 0 +OP4 E0069F 0 +OP4 E006A0 0 +OP4 E006A1 0 +OP4 E006A2 0 +OP4 E006A3 0 +OP4 E006A4 0 +OP4 E006A5 0 +OP4 E006A6 0 +OP4 E006A7 0 +OP4 E006A8 0 +OP4 E006A9 0 +OP4 E006AA 0 +OP4 E006AB 0 +OP4 E006AC 0 +OP4 E006AD 0 +OP4 E006AE 0 +OP4 E006AF 0 +OP4 E006B0 0 +OP4 E006B1 0 +OP4 E006B2 0 +OP4 E006B3 0 +OP4 E006B4 0 +OP4 E006B5 0 +OP4 E006B6 0 +OP4 E006B7 0 +OP4 E006B8 0 +OP4 E006B9 0 +OP4 E006BA 0 +OP4 E006BB 0 +OP4 E006BC 0 +OP4 E006BD 0 +OP4 E006BE 0 +OP4 E006BF 0 +OP4 E006C0 0 +OP4 E006C1 0 +OP4 E006C2 0 +OP4 E006C3 0 +OP4 E006C4 0 +OP4 E006C5 0 +OP4 E006C6 0 +OP4 E006C7 0 +OP4 E006C8 0 +OP4 E006C9 0 +OP4 E006CA 0 +OP4 E006CB 0 +OP4 E006CC 0 +OP4 E006CD 0 +OP4 E006CE 0 +OP4 E006CF 0 +OP4 E006D0 0 +OP4 E006D1 0 +OP4 E006D2 0 +OP4 E006D3 0 +OP4 E006D4 0 +OP4 E006D5 0 +OP4 E006D6 0 +OP4 E006D7 0 +OP4 E006D8 0 +OP4 E006D9 0 +OP4 E006DA 0 +OP4 E006DB 0 +OP4 E006DC 0 +OP4 E006DD 0 +OP4 E006DE 0 +OP4 E006DF 0 +OP4 E006E0 0 +OP4 E006E1 0 +OP4 E006E2 0 +OP4 E006E3 0 +OP4 E006E4 0 +OP4 E006E5 0 +OP4 E006E6 0 +OP4 E006E7 0 +OP4 E006E8 0 +OP4 E006E9 0 +OP4 E006EA 0 +OP4 E006EB 0 +OP4 E006EC 0 +OP4 E006ED 0 +OP4 E006EE 0 +OP4 E006EF 0 +OP4 E006F0 0 +OP4 E006F1 0 +OP4 E006F2 0 +OP4 E006F3 0 +OP4 E006F4 0 +OP4 E006F5 0 +OP4 E006F6 0 +OP4 E006F7 0 +OP4 E006F8 0 +OP4 E006F9 0 +OP4 E006FA 0 +OP4 E006FB 0 +OP4 E006FC 0 +OP4 E006FD 0 +OP4 E006FE 0 +OP4 E006FF 0 +OP4 E00700 0 +OP4 E00701 0 +OP4 E00702 0 +OP4 E00703 0 +OP4 E00704 0 +OP4 E00705 0 +OP4 E00706 0 +OP4 E00707 0 +OP4 E00708 0 +OP4 E00709 0 +OP4 E0070A 0 +OP4 E0070B 0 +OP4 E0070C 0 +OP4 E0070D 0 +OP4 E0070E 0 +OP4 E0070F 0 +OP4 E00710 0 +OP4 E00711 0 +OP4 E00712 0 +OP4 E00713 0 +OP4 E00714 0 +OP4 E00715 0 +OP4 E00716 0 +OP4 E00717 0 +OP4 E00718 0 +OP4 E00719 0 +OP4 E0071A 0 +OP4 E0071B 0 +OP4 E0071C 0 +OP4 E0071D 0 +OP4 E0071E 0 +OP4 E0071F 0 +OP4 E00720 0 +OP4 E00721 0 +OP4 E00722 0 +OP4 E00723 0 +OP4 E00724 0 +OP4 E00725 0 +OP4 E00726 0 +OP4 E00727 0 +OP4 E00728 0 +OP4 E00729 0 +OP4 E0072A 0 +OP4 E0072B 0 +OP4 E0072C 0 +OP4 E0072D 0 +OP4 E0072E 0 +OP4 E0072F 0 +OP4 E00730 0 +OP4 E00731 0 +OP4 E00732 0 +OP4 E00733 0 +OP4 E00734 0 +OP4 E00735 0 +OP4 E00736 0 +OP4 E00737 0 +OP4 E00738 0 +OP4 E00739 0 +OP4 E0073A 0 +OP4 E0073B 0 +OP4 E0073C 0 +OP4 E0073D 0 +OP4 E0073E 0 +OP4 E0073F 0 +OP4 E00740 0 +OP4 E00741 0 +OP4 E00742 0 +OP4 E00743 0 +OP4 E00744 0 +OP4 E00745 0 +OP4 E00746 0 +OP4 E00747 0 +OP4 E00748 0 +OP4 E00749 0 +OP4 E0074A 0 +OP4 E0074B 0 +OP4 E0074C 0 +OP4 E0074D 0 +OP4 E0074E 0 +OP4 E0074F 0 +OP4 E00750 0 +OP4 E00751 0 +OP4 E00752 0 +OP4 E00753 0 +OP4 E00754 0 +OP4 E00755 0 +OP4 E00756 0 +OP4 E00757 0 +OP4 E00758 0 +OP4 E00759 0 +OP4 E0075A 0 +OP4 E0075B 0 +OP4 E0075C 0 +OP4 E0075D 0 +OP4 E0075E 0 +OP4 E0075F 0 +OP4 E00760 0 +OP4 E00761 0 +OP4 E00762 0 +OP4 E00763 0 +OP4 E00764 0 +OP4 E00765 0 +OP4 E00766 0 +OP4 E00767 0 +OP4 E00768 0 +OP4 E00769 0 +OP4 E0076A 0 +OP4 E0076B 0 +OP4 E0076C 0 +OP4 E0076D 0 +OP4 E0076E 0 +OP4 E0076F 0 +OP4 E00770 0 +OP4 E00771 0 +OP4 E00772 0 +OP4 E00773 0 +OP4 E00774 0 +OP4 E00775 0 +OP4 E00776 0 +OP4 E00777 0 +OP4 E00778 0 +OP4 E00779 0 +OP4 E0077A 0 +OP4 E0077B 0 +OP4 E0077C 0 +OP4 E0077D 0 +OP4 E0077E 0 +OP4 E0077F 0 +OP4 E00780 0 +OP4 E00781 0 +OP4 E00782 0 +OP4 E00783 0 +OP4 E00784 0 +OP4 E00785 0 +OP4 E00786 0 +OP4 E00787 0 +OP4 E00788 0 +OP4 E00789 0 +OP4 E0078A 0 +OP4 E0078B 0 +OP4 E0078C 0 +OP4 E0078D 0 +OP4 E0078E 0 +OP4 E0078F 0 +OP4 E00790 0 +OP4 E00791 0 +OP4 E00792 0 +OP4 E00793 0 +OP4 E00794 0 +OP4 E00795 0 +OP4 E00796 0 +OP4 E00797 0 +OP4 E00798 0 +OP4 E00799 0 +OP4 E0079A 0 +OP4 E0079B 0 +OP4 E0079C 0 +OP4 E0079D 0 +OP4 E0079E 0 +OP4 E0079F 0 +OP4 E007A0 0 +OP4 E007A1 0 +OP4 E007A2 0 +OP4 E007A3 0 +OP4 E007A4 0 +OP4 E007A5 0 +OP4 E007A6 0 +OP4 E007A7 0 +OP4 E007A8 0 +OP4 E007A9 0 +OP4 E007AA 0 +OP4 E007AB 0 +OP4 E007AC 0 +OP4 E007AD 0 +OP4 E007AE 0 +OP4 E007AF 0 +OP4 E007B0 0 +OP4 E007B1 0 +OP4 E007B2 0 +OP4 E007B3 0 +OP4 E007B4 0 +OP4 E007B5 0 +OP4 E007B6 0 +OP4 E007B7 0 +OP4 E007B8 0 +OP4 E007B9 0 +OP4 E007BA 0 +OP4 E007BB 0 +OP4 E007BC 0 +OP4 E007BD 0 +OP4 E007BE 0 +OP4 E007BF 0 +OP4 E007C0 0 +OP4 E007C1 0 +OP4 E007C2 0 +OP4 E007C3 0 +OP4 E007C4 0 +OP4 E007C5 0 +OP4 E007C6 0 +OP4 E007C7 0 +OP4 E007C8 0 +OP4 E007C9 0 +OP4 E007CA 0 +OP4 E007CB 0 +OP4 E007CC 0 +OP4 E007CD 0 +OP4 E007CE 0 +OP4 E007CF 0 +OP4 E007D0 0 +OP4 E007D1 0 +OP4 E007D2 0 +OP4 E007D3 0 +OP4 E007D4 0 +OP4 E007D5 0 +OP4 E007D6 0 +OP4 E007D7 0 +OP4 E007D8 0 +OP4 E007D9 0 +OP4 E007DA 0 +OP4 E007DB 0 +OP4 E007DC 0 +OP4 E007DD 0 +OP4 E007DE 0 +OP4 E007DF 0 +OP4 E007E0 0 +OP4 E007E1 0 +OP4 E007E2 0 +OP4 E007E3 0 +OP4 E007E4 0 +OP4 E007E5 0 +OP4 E007E6 0 +OP4 E007E7 0 +OP4 E007E8 0 +OP4 E007E9 0 +OP4 E007EA 0 +OP4 E007EB 0 +OP4 E007EC 0 +OP4 E007ED 0 +OP4 E007EE 0 +OP4 E007EF 0 +OP4 E007F0 0 +OP4 E007F1 0 +OP4 E007F2 0 +OP4 E007F3 0 +OP4 E007F4 0 +OP4 E007F5 0 +OP4 E007F6 0 +OP4 E007F7 0 +OP4 E007F8 0 +OP4 E007F9 0 +OP4 E007FA 0 +OP4 E007FB 0 +OP4 E007FC 0 +OP4 E007FD 0 +OP4 E007FE 0 +OP4 E007FF 0 +OP4 E00800 0 +OP4 E00801 0 +OP4 E00802 0 +OP4 E00803 0 +OP4 E00804 0 +OP4 E00805 0 +OP4 E00806 0 +OP4 E00807 0 +OP4 E00808 0 +OP4 E00809 0 +OP4 E0080A 0 +OP4 E0080B 0 +OP4 E0080C 0 +OP4 E0080D 0 +OP4 E0080E 0 +OP4 E0080F 0 +OP4 E00810 0 +OP4 E00811 0 +OP4 E00812 0 +OP4 E00813 0 +OP4 E00814 0 +OP4 E00815 0 +OP4 E00816 0 +OP4 E00817 0 +OP4 E00818 0 +OP4 E00819 0 +OP4 E0081A 0 +OP4 E0081B 0 +OP4 E0081C 0 +OP4 E0081D 0 +OP4 E0081E 0 +OP4 E0081F 0 +OP4 E00820 0 +OP4 E00821 0 +OP4 E00822 0 +OP4 E00823 0 +OP4 E00824 0 +OP4 E00825 0 +OP4 E00826 0 +OP4 E00827 0 +OP4 E00828 0 +OP4 E00829 0 +OP4 E0082A 0 +OP4 E0082B 0 +OP4 E0082C 0 +OP4 E0082D 0 +OP4 E0082E 0 +OP4 E0082F 0 +OP4 E00830 0 +OP4 E00831 0 +OP4 E00832 0 +OP4 E00833 0 +OP4 E00834 0 +OP4 E00835 0 +OP4 E00836 0 +OP4 E00837 0 +OP4 E00838 0 +OP4 E00839 0 +OP4 E0083A 0 +OP4 E0083B 0 +OP4 E0083C 0 +OP4 E0083D 0 +OP4 E0083E 0 +OP4 E0083F 0 +OP4 E00840 0 +OP4 E00841 0 +OP4 E00842 0 +OP4 E00843 0 +OP4 E00844 0 +OP4 E00845 0 +OP4 E00846 0 +OP4 E00847 0 +OP4 E00848 0 +OP4 E00849 0 +OP4 E0084A 0 +OP4 E0084B 0 +OP4 E0084C 0 +OP4 E0084D 0 +OP4 E0084E 0 +OP4 E0084F 0 +OP4 E00850 0 +OP4 E00851 0 +OP4 E00852 0 +OP4 E00853 0 +OP4 E00854 0 +OP4 E00855 0 +OP4 E00856 0 +OP4 E00857 0 +OP4 E00858 0 +OP4 E00859 0 +OP4 E0085A 0 +OP4 E0085B 0 +OP4 E0085C 0 +OP4 E0085D 0 +OP4 E0085E 0 +OP4 E0085F 0 +OP4 E00860 0 +OP4 E00861 0 +OP4 E00862 0 +OP4 E00863 0 +OP4 E00864 0 +OP4 E00865 0 +OP4 E00866 0 +OP4 E00867 0 +OP4 E00868 0 +OP4 E00869 0 +OP4 E0086A 0 +OP4 E0086B 0 +OP4 E0086C 0 +OP4 E0086D 0 +OP4 E0086E 0 +OP4 E0086F 0 +OP4 E00870 0 +OP4 E00871 0 +OP4 E00872 0 +OP4 E00873 0 +OP4 E00874 0 +OP4 E00875 0 +OP4 E00876 0 +OP4 E00877 0 +OP4 E00878 0 +OP4 E00879 0 +OP4 E0087A 0 +OP4 E0087B 0 +OP4 E0087C 0 +OP4 E0087D 0 +OP4 E0087E 0 +OP4 E0087F 0 +OP4 E00880 0 +OP4 E00881 0 +OP4 E00882 0 +OP4 E00883 0 +OP4 E00884 0 +OP4 E00885 0 +OP4 E00886 0 +OP4 E00887 0 +OP4 E00888 0 +OP4 E00889 0 +OP4 E0088A 0 +OP4 E0088B 0 +OP4 E0088C 0 +OP4 E0088D 0 +OP4 E0088E 0 +OP4 E0088F 0 +OP4 E00890 0 +OP4 E00891 0 +OP4 E00892 0 +OP4 E00893 0 +OP4 E00894 0 +OP4 E00895 0 +OP4 E00896 0 +OP4 E00897 0 +OP4 E00898 0 +OP4 E00899 0 +OP4 E0089A 0 +OP4 E0089B 0 +OP4 E0089C 0 +OP4 E0089D 0 +OP4 E0089E 0 +OP4 E0089F 0 +OP4 E008A0 0 +OP4 E008A1 0 +OP4 E008A2 0 +OP4 E008A3 0 +OP4 E008A4 0 +OP4 E008A5 0 +OP4 E008A6 0 +OP4 E008A7 0 +OP4 E008A8 0 +OP4 E008A9 0 +OP4 E008AA 0 +OP4 E008AB 0 +OP4 E008AC 0 +OP4 E008AD 0 +OP4 E008AE 0 +OP4 E008AF 0 +OP4 E008B0 0 +OP4 E008B1 0 +OP4 E008B2 0 +OP4 E008B3 0 +OP4 E008B4 0 +OP4 E008B5 0 +OP4 E008B6 0 +OP4 E008B7 0 +OP4 E008B8 0 +OP4 E008B9 0 +OP4 E008BA 0 +OP4 E008BB 0 +OP4 E008BC 0 +OP4 E008BD 0 +OP4 E008BE 0 +OP4 E008BF 0 +OP4 E008C0 0 +OP4 E008C1 0 +OP4 E008C2 0 +OP4 E008C3 0 +OP4 E008C4 0 +OP4 E008C5 0 +OP4 E008C6 0 +OP4 E008C7 0 +OP4 E008C8 0 +OP4 E008C9 0 +OP4 E008CA 0 +OP4 E008CB 0 +OP4 E008CC 0 +OP4 E008CD 0 +OP4 E008CE 0 +OP4 E008CF 0 +OP4 E008D0 0 +OP4 E008D1 0 +OP4 E008D2 0 +OP4 E008D3 0 +OP4 E008D4 0 +OP4 E008D5 0 +OP4 E008D6 0 +OP4 E008D7 0 +OP4 E008D8 0 +OP4 E008D9 0 +OP4 E008DA 0 +OP4 E008DB 0 +OP4 E008DC 0 +OP4 E008DD 0 +OP4 E008DE 0 +OP4 E008DF 0 +OP4 E008E0 0 +OP4 E008E1 0 +OP4 E008E2 0 +OP4 E008E3 0 +OP4 E008E4 0 +OP4 E008E5 0 +OP4 E008E6 0 +OP4 E008E7 0 +OP4 E008E8 0 +OP4 E008E9 0 +OP4 E008EA 0 +OP4 E008EB 0 +OP4 E008EC 0 +OP4 E008ED 0 +OP4 E008EE 0 +OP4 E008EF 0 +OP4 E008F0 0 +OP4 E008F1 0 +OP4 E008F2 0 +OP4 E008F3 0 +OP4 E008F4 0 +OP4 E008F5 0 +OP4 E008F6 0 +OP4 E008F7 0 +OP4 E008F8 0 +OP4 E008F9 0 +OP4 E008FA 0 +OP4 E008FB 0 +OP4 E008FC 0 +OP4 E008FD 0 +OP4 E008FE 0 +OP4 E008FF 0 +OP4 E00900 0 +OP4 E00901 0 +OP4 E00902 0 +OP4 E00903 0 +OP4 E00904 0 +OP4 E00905 0 +OP4 E00906 0 +OP4 E00907 0 +OP4 E00908 0 +OP4 E00909 0 +OP4 E0090A 0 +OP4 E0090B 0 +OP4 E0090C 0 +OP4 E0090D 0 +OP4 E0090E 0 +OP4 E0090F 0 +OP4 E00910 0 +OP4 E00911 0 +OP4 E00912 0 +OP4 E00913 0 +OP4 E00914 0 +OP4 E00915 0 +OP4 E00916 0 +OP4 E00917 0 +OP4 E00918 0 +OP4 E00919 0 +OP4 E0091A 0 +OP4 E0091B 0 +OP4 E0091C 0 +OP4 E0091D 0 +OP4 E0091E 0 +OP4 E0091F 0 +OP4 E00920 0 +OP4 E00921 0 +OP4 E00922 0 +OP4 E00923 0 +OP4 E00924 0 +OP4 E00925 0 +OP4 E00926 0 +OP4 E00927 0 +OP4 E00928 0 +OP4 E00929 0 +OP4 E0092A 0 +OP4 E0092B 0 +OP4 E0092C 0 +OP4 E0092D 0 +OP4 E0092E 0 +OP4 E0092F 0 +OP4 E00930 0 +OP4 E00931 0 +OP4 E00932 0 +OP4 E00933 0 +OP4 E00934 0 +OP4 E00935 0 +OP4 E00936 0 +OP4 E00937 0 +OP4 E00938 0 +OP4 E00939 0 +OP4 E0093A 0 +OP4 E0093B 0 +OP4 E0093C 0 +OP4 E0093D 0 +OP4 E0093E 0 +OP4 E0093F 0 +OP4 E00940 0 +OP4 E00941 0 +OP4 E00942 0 +OP4 E00943 0 +OP4 E00944 0 +OP4 E00945 0 +OP4 E00946 0 +OP4 E00947 0 +OP4 E00948 0 +OP4 E00949 0 +OP4 E0094A 0 +OP4 E0094B 0 +OP4 E0094C 0 +OP4 E0094D 0 +OP4 E0094E 0 +OP4 E0094F 0 +OP4 E00950 0 +OP4 E00951 0 +OP4 E00952 0 +OP4 E00953 0 +OP4 E00954 0 +OP4 E00955 0 +OP4 E00956 0 +OP4 E00957 0 +OP4 E00958 0 +OP4 E00959 0 +OP4 E0095A 0 +OP4 E0095B 0 +OP4 E0095C 0 +OP4 E0095D 0 +OP4 E0095E 0 +OP4 E0095F 0 +OP4 E00960 0 +OP4 E00961 0 +OP4 E00962 0 +OP4 E00963 0 +OP4 E00964 0 +OP4 E00965 0 +OP4 E00966 0 +OP4 E00967 0 +OP4 E00968 0 +OP4 E00969 0 +OP4 E0096A 0 +OP4 E0096B 0 +OP4 E0096C 0 +OP4 E0096D 0 +OP4 E0096E 0 +OP4 E0096F 0 +OP4 E00970 0 +OP4 E00971 0 +OP4 E00972 0 +OP4 E00973 0 +OP4 E00974 0 +OP4 E00975 0 +OP4 E00976 0 +OP4 E00977 0 +OP4 E00978 0 +OP4 E00979 0 +OP4 E0097A 0 +OP4 E0097B 0 +OP4 E0097C 0 +OP4 E0097D 0 +OP4 E0097E 0 +OP4 E0097F 0 +OP4 E00980 0 +OP4 E00981 0 +OP4 E00982 0 +OP4 E00983 0 +OP4 E00984 0 +OP4 E00985 0 +OP4 E00986 0 +OP4 E00987 0 +OP4 E00988 0 +OP4 E00989 0 +OP4 E0098A 0 +OP4 E0098B 0 +OP4 E0098C 0 +OP4 E0098D 0 +OP4 E0098E 0 +OP4 E0098F 0 +OP4 E00990 0 +OP4 E00991 0 +OP4 E00992 0 +OP4 E00993 0 +OP4 E00994 0 +OP4 E00995 0 +OP4 E00996 0 +OP4 E00997 0 +OP4 E00998 0 +OP4 E00999 0 +OP4 E0099A 0 +OP4 E0099B 0 +OP4 E0099C 0 +OP4 E0099D 0 +OP4 E0099E 0 +OP4 E0099F 0 +OP4 E009A0 0 +OP4 E009A1 0 +OP4 E009A2 0 +OP4 E009A3 0 +OP4 E009A4 0 +OP4 E009A5 0 +OP4 E009A6 0 +OP4 E009A7 0 +OP4 E009A8 0 +OP4 E009A9 0 +OP4 E009AA 0 +OP4 E009AB 0 +OP4 E009AC 0 +OP4 E009AD 0 +OP4 E009AE 0 +OP4 E009AF 0 +OP4 E009B0 0 +OP4 E009B1 0 +OP4 E009B2 0 +OP4 E009B3 0 +OP4 E009B4 0 +OP4 E009B5 0 +OP4 E009B6 0 +OP4 E009B7 0 +OP4 E009B8 0 +OP4 E009B9 0 +OP4 E009BA 0 +OP4 E009BB 0 +OP4 E009BC 0 +OP4 E009BD 0 +OP4 E009BE 0 +OP4 E009BF 0 +OP4 E009C0 0 +OP4 E009C1 0 +OP4 E009C2 0 +OP4 E009C3 0 +OP4 E009C4 0 +OP4 E009C5 0 +OP4 E009C6 0 +OP4 E009C7 0 +OP4 E009C8 0 +OP4 E009C9 0 +OP4 E009CA 0 +OP4 E009CB 0 +OP4 E009CC 0 +OP4 E009CD 0 +OP4 E009CE 0 +OP4 E009CF 0 +OP4 E009D0 0 +OP4 E009D1 0 +OP4 E009D2 0 +OP4 E009D3 0 +OP4 E009D4 0 +OP4 E009D5 0 +OP4 E009D6 0 +OP4 E009D7 0 +OP4 E009D8 0 +OP4 E009D9 0 +OP4 E009DA 0 +OP4 E009DB 0 +OP4 E009DC 0 +OP4 E009DD 0 +OP4 E009DE 0 +OP4 E009DF 0 +OP4 E009E0 0 +OP4 E009E1 0 +OP4 E009E2 0 +OP4 E009E3 0 +OP4 E009E4 0 +OP4 E009E5 0 +OP4 E009E6 0 +OP4 E009E7 0 +OP4 E009E8 0 +OP4 E009E9 0 +OP4 E009EA 0 +OP4 E009EB 0 +OP4 E009EC 0 +OP4 E009ED 0 +OP4 E009EE 0 +OP4 E009EF 0 +OP4 E009F0 0 +OP4 E009F1 0 +OP4 E009F2 0 +OP4 E009F3 0 +OP4 E009F4 0 +OP4 E009F5 0 +OP4 E009F6 0 +OP4 E009F7 0 +OP4 E009F8 0 +OP4 E009F9 0 +OP4 E009FA 0 +OP4 E009FB 0 +OP4 E009FC 0 +OP4 E009FD 0 +OP4 E009FE 0 +OP4 E009FF 0 +OP4 E00A00 0 +OP4 E00A01 0 +OP4 E00A02 0 +OP4 E00A03 0 +OP4 E00A04 0 +OP4 E00A05 0 +OP4 E00A06 0 +OP4 E00A07 0 +OP4 E00A08 0 +OP4 E00A09 0 +OP4 E00A0A 0 +OP4 E00A0B 0 +OP4 E00A0C 0 +OP4 E00A0D 0 +OP4 E00A0E 0 +OP4 E00A0F 0 +OP4 E00A10 0 +OP4 E00A11 0 +OP4 E00A12 0 +OP4 E00A13 0 +OP4 E00A14 0 +OP4 E00A15 0 +OP4 E00A16 0 +OP4 E00A17 0 +OP4 E00A18 0 +OP4 E00A19 0 +OP4 E00A1A 0 +OP4 E00A1B 0 +OP4 E00A1C 0 +OP4 E00A1D 0 +OP4 E00A1E 0 +OP4 E00A1F 0 +OP4 E00A20 0 +OP4 E00A21 0 +OP4 E00A22 0 +OP4 E00A23 0 +OP4 E00A24 0 +OP4 E00A25 0 +OP4 E00A26 0 +OP4 E00A27 0 +OP4 E00A28 0 +OP4 E00A29 0 +OP4 E00A2A 0 +OP4 E00A2B 0 +OP4 E00A2C 0 +OP4 E00A2D 0 +OP4 E00A2E 0 +OP4 E00A2F 0 +OP4 E00A30 0 +OP4 E00A31 0 +OP4 E00A32 0 +OP4 E00A33 0 +OP4 E00A34 0 +OP4 E00A35 0 +OP4 E00A36 0 +OP4 E00A37 0 +OP4 E00A38 0 +OP4 E00A39 0 +OP4 E00A3A 0 +OP4 E00A3B 0 +OP4 E00A3C 0 +OP4 E00A3D 0 +OP4 E00A3E 0 +OP4 E00A3F 0 +OP4 E00A40 0 +OP4 E00A41 0 +OP4 E00A42 0 +OP4 E00A43 0 +OP4 E00A44 0 +OP4 E00A45 0 +OP4 E00A46 0 +OP4 E00A47 0 +OP4 E00A48 0 +OP4 E00A49 0 +OP4 E00A4A 0 +OP4 E00A4B 0 +OP4 E00A4C 0 +OP4 E00A4D 0 +OP4 E00A4E 0 +OP4 E00A4F 0 +OP4 E00A50 0 +OP4 E00A51 0 +OP4 E00A52 0 +OP4 E00A53 0 +OP4 E00A54 0 +OP4 E00A55 0 +OP4 E00A56 0 +OP4 E00A57 0 +OP4 E00A58 0 +OP4 E00A59 0 +OP4 E00A5A 0 +OP4 E00A5B 0 +OP4 E00A5C 0 +OP4 E00A5D 0 +OP4 E00A5E 0 +OP4 E00A5F 0 +OP4 E00A60 0 +OP4 E00A61 0 +OP4 E00A62 0 +OP4 E00A63 0 +OP4 E00A64 0 +OP4 E00A65 0 +OP4 E00A66 0 +OP4 E00A67 0 +OP4 E00A68 0 +OP4 E00A69 0 +OP4 E00A6A 0 +OP4 E00A6B 0 +OP4 E00A6C 0 +OP4 E00A6D 0 +OP4 E00A6E 0 +OP4 E00A6F 0 +OP4 E00A70 0 +OP4 E00A71 0 +OP4 E00A72 0 +OP4 E00A73 0 +OP4 E00A74 0 +OP4 E00A75 0 +OP4 E00A76 0 +OP4 E00A77 0 +OP4 E00A78 0 +OP4 E00A79 0 +OP4 E00A7A 0 +OP4 E00A7B 0 +OP4 E00A7C 0 +OP4 E00A7D 0 +OP4 E00A7E 0 +OP4 E00A7F 0 +OP4 E00A80 0 +OP4 E00A81 0 +OP4 E00A82 0 +OP4 E00A83 0 +OP4 E00A84 0 +OP4 E00A85 0 +OP4 E00A86 0 +OP4 E00A87 0 +OP4 E00A88 0 +OP4 E00A89 0 +OP4 E00A8A 0 +OP4 E00A8B 0 +OP4 E00A8C 0 +OP4 E00A8D 0 +OP4 E00A8E 0 +OP4 E00A8F 0 +OP4 E00A90 0 +OP4 E00A91 0 +OP4 E00A92 0 +OP4 E00A93 0 +OP4 E00A94 0 +OP4 E00A95 0 +OP4 E00A96 0 +OP4 E00A97 0 +OP4 E00A98 0 +OP4 E00A99 0 +OP4 E00A9A 0 +OP4 E00A9B 0 +OP4 E00A9C 0 +OP4 E00A9D 0 +OP4 E00A9E 0 +OP4 E00A9F 0 +OP4 E00AA0 0 +OP4 E00AA1 0 +OP4 E00AA2 0 +OP4 E00AA3 0 +OP4 E00AA4 0 +OP4 E00AA5 0 +OP4 E00AA6 0 +OP4 E00AA7 0 +OP4 E00AA8 0 +OP4 E00AA9 0 +OP4 E00AAA 0 +OP4 E00AAB 0 +OP4 E00AAC 0 +OP4 E00AAD 0 +OP4 E00AAE 0 +OP4 E00AAF 0 +OP4 E00AB0 0 +OP4 E00AB1 0 +OP4 E00AB2 0 +OP4 E00AB3 0 +OP4 E00AB4 0 +OP4 E00AB5 0 +OP4 E00AB6 0 +OP4 E00AB7 0 +OP4 E00AB8 0 +OP4 E00AB9 0 +OP4 E00ABA 0 +OP4 E00ABB 0 +OP4 E00ABC 0 +OP4 E00ABD 0 +OP4 E00ABE 0 +OP4 E00ABF 0 +OP4 E00AC0 0 +OP4 E00AC1 0 +OP4 E00AC2 0 +OP4 E00AC3 0 +OP4 E00AC4 0 +OP4 E00AC5 0 +OP4 E00AC6 0 +OP4 E00AC7 0 +OP4 E00AC8 0 +OP4 E00AC9 0 +OP4 E00ACA 0 +OP4 E00ACB 0 +OP4 E00ACC 0 +OP4 E00ACD 0 +OP4 E00ACE 0 +OP4 E00ACF 0 +OP4 E00AD0 0 +OP4 E00AD1 0 +OP4 E00AD2 0 +OP4 E00AD3 0 +OP4 E00AD4 0 +OP4 E00AD5 0 +OP4 E00AD6 0 +OP4 E00AD7 0 +OP4 E00AD8 0 +OP4 E00AD9 0 +OP4 E00ADA 0 +OP4 E00ADB 0 +OP4 E00ADC 0 +OP4 E00ADD 0 +OP4 E00ADE 0 +OP4 E00ADF 0 +OP4 E00AE0 0 +OP4 E00AE1 0 +OP4 E00AE2 0 +OP4 E00AE3 0 +OP4 E00AE4 0 +OP4 E00AE5 0 +OP4 E00AE6 0 +OP4 E00AE7 0 +OP4 E00AE8 0 +OP4 E00AE9 0 +OP4 E00AEA 0 +OP4 E00AEB 0 +OP4 E00AEC 0 +OP4 E00AED 0 +OP4 E00AEE 0 +OP4 E00AEF 0 +OP4 E00AF0 0 +OP4 E00AF1 0 +OP4 E00AF2 0 +OP4 E00AF3 0 +OP4 E00AF4 0 +OP4 E00AF5 0 +OP4 E00AF6 0 +OP4 E00AF7 0 +OP4 E00AF8 0 +OP4 E00AF9 0 +OP4 E00AFA 0 +OP4 E00AFB 0 +OP4 E00AFC 0 +OP4 E00AFD 0 +OP4 E00AFE 0 +OP4 E00AFF 0 +OP4 E00B00 0 +OP4 E00B01 0 +OP4 E00B02 0 +OP4 E00B03 0 +OP4 E00B04 0 +OP4 E00B05 0 +OP4 E00B06 0 +OP4 E00B07 0 +OP4 E00B08 0 +OP4 E00B09 0 +OP4 E00B0A 0 +OP4 E00B0B 0 +OP4 E00B0C 0 +OP4 E00B0D 0 +OP4 E00B0E 0 +OP4 E00B0F 0 +OP4 E00B10 0 +OP4 E00B11 0 +OP4 E00B12 0 +OP4 E00B13 0 +OP4 E00B14 0 +OP4 E00B15 0 +OP4 E00B16 0 +OP4 E00B17 0 +OP4 E00B18 0 +OP4 E00B19 0 +OP4 E00B1A 0 +OP4 E00B1B 0 +OP4 E00B1C 0 +OP4 E00B1D 0 +OP4 E00B1E 0 +OP4 E00B1F 0 +OP4 E00B20 0 +OP4 E00B21 0 +OP4 E00B22 0 +OP4 E00B23 0 +OP4 E00B24 0 +OP4 E00B25 0 +OP4 E00B26 0 +OP4 E00B27 0 +OP4 E00B28 0 +OP4 E00B29 0 +OP4 E00B2A 0 +OP4 E00B2B 0 +OP4 E00B2C 0 +OP4 E00B2D 0 +OP4 E00B2E 0 +OP4 E00B2F 0 +OP4 E00B30 0 +OP4 E00B31 0 +OP4 E00B32 0 +OP4 E00B33 0 +OP4 E00B34 0 +OP4 E00B35 0 +OP4 E00B36 0 +OP4 E00B37 0 +OP4 E00B38 0 +OP4 E00B39 0 +OP4 E00B3A 0 +OP4 E00B3B 0 +OP4 E00B3C 0 +OP4 E00B3D 0 +OP4 E00B3E 0 +OP4 E00B3F 0 +OP4 E00B40 0 +OP4 E00B41 0 +OP4 E00B42 0 +OP4 E00B43 0 +OP4 E00B44 0 +OP4 E00B45 0 +OP4 E00B46 0 +OP4 E00B47 0 +OP4 E00B48 0 +OP4 E00B49 0 +OP4 E00B4A 0 +OP4 E00B4B 0 +OP4 E00B4C 0 +OP4 E00B4D 0 +OP4 E00B4E 0 +OP4 E00B4F 0 +OP4 E00B50 0 +OP4 E00B51 0 +OP4 E00B52 0 +OP4 E00B53 0 +OP4 E00B54 0 +OP4 E00B55 0 +OP4 E00B56 0 +OP4 E00B57 0 +OP4 E00B58 0 +OP4 E00B59 0 +OP4 E00B5A 0 +OP4 E00B5B 0 +OP4 E00B5C 0 +OP4 E00B5D 0 +OP4 E00B5E 0 +OP4 E00B5F 0 +OP4 E00B60 0 +OP4 E00B61 0 +OP4 E00B62 0 +OP4 E00B63 0 +OP4 E00B64 0 +OP4 E00B65 0 +OP4 E00B66 0 +OP4 E00B67 0 +OP4 E00B68 0 +OP4 E00B69 0 +OP4 E00B6A 0 +OP4 E00B6B 0 +OP4 E00B6C 0 +OP4 E00B6D 0 +OP4 E00B6E 0 +OP4 E00B6F 0 +OP4 E00B70 0 +OP4 E00B71 0 +OP4 E00B72 0 +OP4 E00B73 0 +OP4 E00B74 0 +OP4 E00B75 0 +OP4 E00B76 0 +OP4 E00B77 0 +OP4 E00B78 0 +OP4 E00B79 0 +OP4 E00B7A 0 +OP4 E00B7B 0 +OP4 E00B7C 0 +OP4 E00B7D 0 +OP4 E00B7E 0 +OP4 E00B7F 0 +OP4 E00B80 0 +OP4 E00B81 0 +OP4 E00B82 0 +OP4 E00B83 0 +OP4 E00B84 0 +OP4 E00B85 0 +OP4 E00B86 0 +OP4 E00B87 0 +OP4 E00B88 0 +OP4 E00B89 0 +OP4 E00B8A 0 +OP4 E00B8B 0 +OP4 E00B8C 0 +OP4 E00B8D 0 +OP4 E00B8E 0 +OP4 E00B8F 0 +OP4 E00B90 0 +OP4 E00B91 0 +OP4 E00B92 0 +OP4 E00B93 0 +OP4 E00B94 0 +OP4 E00B95 0 +OP4 E00B96 0 +OP4 E00B97 0 +OP4 E00B98 0 +OP4 E00B99 0 +OP4 E00B9A 0 +OP4 E00B9B 0 +OP4 E00B9C 0 +OP4 E00B9D 0 +OP4 E00B9E 0 +OP4 E00B9F 0 +OP4 E00BA0 0 +OP4 E00BA1 0 +OP4 E00BA2 0 +OP4 E00BA3 0 +OP4 E00BA4 0 +OP4 E00BA5 0 +OP4 E00BA6 0 +OP4 E00BA7 0 +OP4 E00BA8 0 +OP4 E00BA9 0 +OP4 E00BAA 0 +OP4 E00BAB 0 +OP4 E00BAC 0 +OP4 E00BAD 0 +OP4 E00BAE 0 +OP4 E00BAF 0 +OP4 E00BB0 0 +OP4 E00BB1 0 +OP4 E00BB2 0 +OP4 E00BB3 0 +OP4 E00BB4 0 +OP4 E00BB5 0 +OP4 E00BB6 0 +OP4 E00BB7 0 +OP4 E00BB8 0 +OP4 E00BB9 0 +OP4 E00BBA 0 +OP4 E00BBB 0 +OP4 E00BBC 0 +OP4 E00BBD 0 +OP4 E00BBE 0 +OP4 E00BBF 0 +OP4 E00BC0 0 +OP4 E00BC1 0 +OP4 E00BC2 0 +OP4 E00BC3 0 +OP4 E00BC4 0 +OP4 E00BC5 0 +OP4 E00BC6 0 +OP4 E00BC7 0 +OP4 E00BC8 0 +OP4 E00BC9 0 +OP4 E00BCA 0 +OP4 E00BCB 0 +OP4 E00BCC 0 +OP4 E00BCD 0 +OP4 E00BCE 0 +OP4 E00BCF 0 +OP4 E00BD0 0 +OP4 E00BD1 0 +OP4 E00BD2 0 +OP4 E00BD3 0 +OP4 E00BD4 0 +OP4 E00BD5 0 +OP4 E00BD6 0 +OP4 E00BD7 0 +OP4 E00BD8 0 +OP4 E00BD9 0 +OP4 E00BDA 0 +OP4 E00BDB 0 +OP4 E00BDC 0 +OP4 E00BDD 0 +OP4 E00BDE 0 +OP4 E00BDF 0 +OP4 E00BE0 0 +OP4 E00BE1 0 +OP4 E00BE2 0 +OP4 E00BE3 0 +OP4 E00BE4 0 +OP4 E00BE5 0 +OP4 E00BE6 0 +OP4 E00BE7 0 +OP4 E00BE8 0 +OP4 E00BE9 0 +OP4 E00BEA 0 +OP4 E00BEB 0 +OP4 E00BEC 0 +OP4 E00BED 0 +OP4 E00BEE 0 +OP4 E00BEF 0 +OP4 E00BF0 0 +OP4 E00BF1 0 +OP4 E00BF2 0 +OP4 E00BF3 0 +OP4 E00BF4 0 +OP4 E00BF5 0 +OP4 E00BF6 0 +OP4 E00BF7 0 +OP4 E00BF8 0 +OP4 E00BF9 0 +OP4 E00BFA 0 +OP4 E00BFB 0 +OP4 E00BFC 0 +OP4 E00BFD 0 +OP4 E00BFE 0 +OP4 E00BFF 0 +OP4 E00C00 0 +OP4 E00C01 0 +OP4 E00C02 0 +OP4 E00C03 0 +OP4 E00C04 0 +OP4 E00C05 0 +OP4 E00C06 0 +OP4 E00C07 0 +OP4 E00C08 0 +OP4 E00C09 0 +OP4 E00C0A 0 +OP4 E00C0B 0 +OP4 E00C0C 0 +OP4 E00C0D 0 +OP4 E00C0E 0 +OP4 E00C0F 0 +OP4 E00C10 0 +OP4 E00C11 0 +OP4 E00C12 0 +OP4 E00C13 0 +OP4 E00C14 0 +OP4 E00C15 0 +OP4 E00C16 0 +OP4 E00C17 0 +OP4 E00C18 0 +OP4 E00C19 0 +OP4 E00C1A 0 +OP4 E00C1B 0 +OP4 E00C1C 0 +OP4 E00C1D 0 +OP4 E00C1E 0 +OP4 E00C1F 0 +OP4 E00C20 0 +OP4 E00C21 0 +OP4 E00C22 0 +OP4 E00C23 0 +OP4 E00C24 0 +OP4 E00C25 0 +OP4 E00C26 0 +OP4 E00C27 0 +OP4 E00C28 0 +OP4 E00C29 0 +OP4 E00C2A 0 +OP4 E00C2B 0 +OP4 E00C2C 0 +OP4 E00C2D 0 +OP4 E00C2E 0 +OP4 E00C2F 0 +OP4 E00C30 0 +OP4 E00C31 0 +OP4 E00C32 0 +OP4 E00C33 0 +OP4 E00C34 0 +OP4 E00C35 0 +OP4 E00C36 0 +OP4 E00C37 0 +OP4 E00C38 0 +OP4 E00C39 0 +OP4 E00C3A 0 +OP4 E00C3B 0 +OP4 E00C3C 0 +OP4 E00C3D 0 +OP4 E00C3E 0 +OP4 E00C3F 0 +OP4 E00C40 0 +OP4 E00C41 0 +OP4 E00C42 0 +OP4 E00C43 0 +OP4 E00C44 0 +OP4 E00C45 0 +OP4 E00C46 0 +OP4 E00C47 0 +OP4 E00C48 0 +OP4 E00C49 0 +OP4 E00C4A 0 +OP4 E00C4B 0 +OP4 E00C4C 0 +OP4 E00C4D 0 +OP4 E00C4E 0 +OP4 E00C4F 0 +OP4 E00C50 0 +OP4 E00C51 0 +OP4 E00C52 0 +OP4 E00C53 0 +OP4 E00C54 0 +OP4 E00C55 0 +OP4 E00C56 0 +OP4 E00C57 0 +OP4 E00C58 0 +OP4 E00C59 0 +OP4 E00C5A 0 +OP4 E00C5B 0 +OP4 E00C5C 0 +OP4 E00C5D 0 +OP4 E00C5E 0 +OP4 E00C5F 0 +OP4 E00C60 0 +OP4 E00C61 0 +OP4 E00C62 0 +OP4 E00C63 0 +OP4 E00C64 0 +OP4 E00C65 0 +OP4 E00C66 0 +OP4 E00C67 0 +OP4 E00C68 0 +OP4 E00C69 0 +OP4 E00C6A 0 +OP4 E00C6B 0 +OP4 E00C6C 0 +OP4 E00C6D 0 +OP4 E00C6E 0 +OP4 E00C6F 0 +OP4 E00C70 0 +OP4 E00C71 0 +OP4 E00C72 0 +OP4 E00C73 0 +OP4 E00C74 0 +OP4 E00C75 0 +OP4 E00C76 0 +OP4 E00C77 0 +OP4 E00C78 0 +OP4 E00C79 0 +OP4 E00C7A 0 +OP4 E00C7B 0 +OP4 E00C7C 0 +OP4 E00C7D 0 +OP4 E00C7E 0 +OP4 E00C7F 0 +OP4 E00C80 0 +OP4 E00C81 0 +OP4 E00C82 0 +OP4 E00C83 0 +OP4 E00C84 0 +OP4 E00C85 0 +OP4 E00C86 0 +OP4 E00C87 0 +OP4 E00C88 0 +OP4 E00C89 0 +OP4 E00C8A 0 +OP4 E00C8B 0 +OP4 E00C8C 0 +OP4 E00C8D 0 +OP4 E00C8E 0 +OP4 E00C8F 0 +OP4 E00C90 0 +OP4 E00C91 0 +OP4 E00C92 0 +OP4 E00C93 0 +OP4 E00C94 0 +OP4 E00C95 0 +OP4 E00C96 0 +OP4 E00C97 0 +OP4 E00C98 0 +OP4 E00C99 0 +OP4 E00C9A 0 +OP4 E00C9B 0 +OP4 E00C9C 0 +OP4 E00C9D 0 +OP4 E00C9E 0 +OP4 E00C9F 0 +OP4 E00CA0 0 +OP4 E00CA1 0 +OP4 E00CA2 0 +OP4 E00CA3 0 +OP4 E00CA4 0 +OP4 E00CA5 0 +OP4 E00CA6 0 +OP4 E00CA7 0 +OP4 E00CA8 0 +OP4 E00CA9 0 +OP4 E00CAA 0 +OP4 E00CAB 0 +OP4 E00CAC 0 +OP4 E00CAD 0 +OP4 E00CAE 0 +OP4 E00CAF 0 +OP4 E00CB0 0 +OP4 E00CB1 0 +OP4 E00CB2 0 +OP4 E00CB3 0 +OP4 E00CB4 0 +OP4 E00CB5 0 +OP4 E00CB6 0 +OP4 E00CB7 0 +OP4 E00CB8 0 +OP4 E00CB9 0 +OP4 E00CBA 0 +OP4 E00CBB 0 +OP4 E00CBC 0 +OP4 E00CBD 0 +OP4 E00CBE 0 +OP4 E00CBF 0 +OP4 E00CC0 0 +OP4 E00CC1 0 +OP4 E00CC2 0 +OP4 E00CC3 0 +OP4 E00CC4 0 +OP4 E00CC5 0 +OP4 E00CC6 0 +OP4 E00CC7 0 +OP4 E00CC8 0 +OP4 E00CC9 0 +OP4 E00CCA 0 +OP4 E00CCB 0 +OP4 E00CCC 0 +OP4 E00CCD 0 +OP4 E00CCE 0 +OP4 E00CCF 0 +OP4 E00CD0 0 +OP4 E00CD1 0 +OP4 E00CD2 0 +OP4 E00CD3 0 +OP4 E00CD4 0 +OP4 E00CD5 0 +OP4 E00CD6 0 +OP4 E00CD7 0 +OP4 E00CD8 0 +OP4 E00CD9 0 +OP4 E00CDA 0 +OP4 E00CDB 0 +OP4 E00CDC 0 +OP4 E00CDD 0 +OP4 E00CDE 0 +OP4 E00CDF 0 +OP4 E00CE0 0 +OP4 E00CE1 0 +OP4 E00CE2 0 +OP4 E00CE3 0 +OP4 E00CE4 0 +OP4 E00CE5 0 +OP4 E00CE6 0 +OP4 E00CE7 0 +OP4 E00CE8 0 +OP4 E00CE9 0 +OP4 E00CEA 0 +OP4 E00CEB 0 +OP4 E00CEC 0 +OP4 E00CED 0 +OP4 E00CEE 0 +OP4 E00CEF 0 +OP4 E00CF0 0 +OP4 E00CF1 0 +OP4 E00CF2 0 +OP4 E00CF3 0 +OP4 E00CF4 0 +OP4 E00CF5 0 +OP4 E00CF6 0 +OP4 E00CF7 0 +OP4 E00CF8 0 +OP4 E00CF9 0 +OP4 E00CFA 0 +OP4 E00CFB 0 +OP4 E00CFC 0 +OP4 E00CFD 0 +OP4 E00CFE 0 +OP4 E00CFF 0 +OP4 E00D00 0 +OP4 E00D01 0 +OP4 E00D02 0 +OP4 E00D03 0 +OP4 E00D04 0 +OP4 E00D05 0 +OP4 E00D06 0 +OP4 E00D07 0 +OP4 E00D08 0 +OP4 E00D09 0 +OP4 E00D0A 0 +OP4 E00D0B 0 +OP4 E00D0C 0 +OP4 E00D0D 0 +OP4 E00D0E 0 +OP4 E00D0F 0 +OP4 E00D10 0 +OP4 E00D11 0 +OP4 E00D12 0 +OP4 E00D13 0 +OP4 E00D14 0 +OP4 E00D15 0 +OP4 E00D16 0 +OP4 E00D17 0 +OP4 E00D18 0 +OP4 E00D19 0 +OP4 E00D1A 0 +OP4 E00D1B 0 +OP4 E00D1C 0 +OP4 E00D1D 0 +OP4 E00D1E 0 +OP4 E00D1F 0 +OP4 E00D20 0 +OP4 E00D21 0 +OP4 E00D22 0 +OP4 E00D23 0 +OP4 E00D24 0 +OP4 E00D25 0 +OP4 E00D26 0 +OP4 E00D27 0 +OP4 E00D28 0 +OP4 E00D29 0 +OP4 E00D2A 0 +OP4 E00D2B 0 +OP4 E00D2C 0 +OP4 E00D2D 0 +OP4 E00D2E 0 +OP4 E00D2F 0 +OP4 E00D30 0 +OP4 E00D31 0 +OP4 E00D32 0 +OP4 E00D33 0 +OP4 E00D34 0 +OP4 E00D35 0 +OP4 E00D36 0 +OP4 E00D37 0 +OP4 E00D38 0 +OP4 E00D39 0 +OP4 E00D3A 0 +OP4 E00D3B 0 +OP4 E00D3C 0 +OP4 E00D3D 0 +OP4 E00D3E 0 +OP4 E00D3F 0 +OP4 E00D40 0 +OP4 E00D41 0 +OP4 E00D42 0 +OP4 E00D43 0 +OP4 E00D44 0 +OP4 E00D45 0 +OP4 E00D46 0 +OP4 E00D47 0 +OP4 E00D48 0 +OP4 E00D49 0 +OP4 E00D4A 0 +OP4 E00D4B 0 +OP4 E00D4C 0 +OP4 E00D4D 0 +OP4 E00D4E 0 +OP4 E00D4F 0 +OP4 E00D50 0 +OP4 E00D51 0 +OP4 E00D52 0 +OP4 E00D53 0 +OP4 E00D54 0 +OP4 E00D55 0 +OP4 E00D56 0 +OP4 E00D57 0 +OP4 E00D58 0 +OP4 E00D59 0 +OP4 E00D5A 0 +OP4 E00D5B 0 +OP4 E00D5C 0 +OP4 E00D5D 0 +OP4 E00D5E 0 +OP4 E00D5F 0 +OP4 E00D60 0 +OP4 E00D61 0 +OP4 E00D62 0 +OP4 E00D63 0 +OP4 E00D64 0 +OP4 E00D65 0 +OP4 E00D66 0 +OP4 E00D67 0 +OP4 E00D68 0 +OP4 E00D69 0 +OP4 E00D6A 0 +OP4 E00D6B 0 +OP4 E00D6C 0 +OP4 E00D6D 0 +OP4 E00D6E 0 +OP4 E00D6F 0 +OP4 E00D70 0 +OP4 E00D71 0 +OP4 E00D72 0 +OP4 E00D73 0 +OP4 E00D74 0 +OP4 E00D75 0 +OP4 E00D76 0 +OP4 E00D77 0 +OP4 E00D78 0 +OP4 E00D79 0 +OP4 E00D7A 0 +OP4 E00D7B 0 +OP4 E00D7C 0 +OP4 E00D7D 0 +OP4 E00D7E 0 +OP4 E00D7F 0 +OP4 E00D80 0 +OP4 E00D81 0 +OP4 E00D82 0 +OP4 E00D83 0 +OP4 E00D84 0 +OP4 E00D85 0 +OP4 E00D86 0 +OP4 E00D87 0 +OP4 E00D88 0 +OP4 E00D89 0 +OP4 E00D8A 0 +OP4 E00D8B 0 +OP4 E00D8C 0 +OP4 E00D8D 0 +OP4 E00D8E 0 +OP4 E00D8F 0 +OP4 E00D90 0 +OP4 E00D91 0 +OP4 E00D92 0 +OP4 E00D93 0 +OP4 E00D94 0 +OP4 E00D95 0 +OP4 E00D96 0 +OP4 E00D97 0 +OP4 E00D98 0 +OP4 E00D99 0 +OP4 E00D9A 0 +OP4 E00D9B 0 +OP4 E00D9C 0 +OP4 E00D9D 0 +OP4 E00D9E 0 +OP4 E00D9F 0 +OP4 E00DA0 0 +OP4 E00DA1 0 +OP4 E00DA2 0 +OP4 E00DA3 0 +OP4 E00DA4 0 +OP4 E00DA5 0 +OP4 E00DA6 0 +OP4 E00DA7 0 +OP4 E00DA8 0 +OP4 E00DA9 0 +OP4 E00DAA 0 +OP4 E00DAB 0 +OP4 E00DAC 0 +OP4 E00DAD 0 +OP4 E00DAE 0 +OP4 E00DAF 0 +OP4 E00DB0 0 +OP4 E00DB1 0 +OP4 E00DB2 0 +OP4 E00DB3 0 +OP4 E00DB4 0 +OP4 E00DB5 0 +OP4 E00DB6 0 +OP4 E00DB7 0 +OP4 E00DB8 0 +OP4 E00DB9 0 +OP4 E00DBA 0 +OP4 E00DBB 0 +OP4 E00DBC 0 +OP4 E00DBD 0 +OP4 E00DBE 0 +OP4 E00DBF 0 +OP4 E00DC0 0 +OP4 E00DC1 0 +OP4 E00DC2 0 +OP4 E00DC3 0 +OP4 E00DC4 0 +OP4 E00DC5 0 +OP4 E00DC6 0 +OP4 E00DC7 0 +OP4 E00DC8 0 +OP4 E00DC9 0 +OP4 E00DCA 0 +OP4 E00DCB 0 +OP4 E00DCC 0 +OP4 E00DCD 0 +OP4 E00DCE 0 +OP4 E00DCF 0 +OP4 E00DD0 0 +OP4 E00DD1 0 +OP4 E00DD2 0 +OP4 E00DD3 0 +OP4 E00DD4 0 +OP4 E00DD5 0 +OP4 E00DD6 0 +OP4 E00DD7 0 +OP4 E00DD8 0 +OP4 E00DD9 0 +OP4 E00DDA 0 +OP4 E00DDB 0 +OP4 E00DDC 0 +OP4 E00DDD 0 +OP4 E00DDE 0 +OP4 E00DDF 0 +OP4 E00DE0 0 +OP4 E00DE1 0 +OP4 E00DE2 0 +OP4 E00DE3 0 +OP4 E00DE4 0 +OP4 E00DE5 0 +OP4 E00DE6 0 +OP4 E00DE7 0 +OP4 E00DE8 0 +OP4 E00DE9 0 +OP4 E00DEA 0 +OP4 E00DEB 0 +OP4 E00DEC 0 +OP4 E00DED 0 +OP4 E00DEE 0 +OP4 E00DEF 0 +OP4 E00DF0 0 +OP4 E00DF1 0 +OP4 E00DF2 0 +OP4 E00DF3 0 +OP4 E00DF4 0 +OP4 E00DF5 0 +OP4 E00DF6 0 +OP4 E00DF7 0 +OP4 E00DF8 0 +OP4 E00DF9 0 +OP4 E00DFA 0 +OP4 E00DFB 0 +OP4 E00DFC 0 +OP4 E00DFD 0 +OP4 E00DFE 0 +OP4 E00DFF 0 +OP4 E00E00 0 +OP4 E00E01 0 +OP4 E00E02 0 +OP4 E00E03 0 +OP4 E00E04 0 +OP4 E00E05 0 +OP4 E00E06 0 +OP4 E00E07 0 +OP4 E00E08 0 +OP4 E00E09 0 +OP4 E00E0A 0 +OP4 E00E0B 0 +OP4 E00E0C 0 +OP4 E00E0D 0 +OP4 E00E0E 0 +OP4 E00E0F 0 +OP4 E00E10 0 +OP4 E00E11 0 +OP4 E00E12 0 +OP4 E00E13 0 +OP4 E00E14 0 +OP4 E00E15 0 +OP4 E00E16 0 +OP4 E00E17 0 +OP4 E00E18 0 +OP4 E00E19 0 +OP4 E00E1A 0 +OP4 E00E1B 0 +OP4 E00E1C 0 +OP4 E00E1D 0 +OP4 E00E1E 0 +OP4 E00E1F 0 +OP4 E00E20 0 +OP4 E00E21 0 +OP4 E00E22 0 +OP4 E00E23 0 +OP4 E00E24 0 +OP4 E00E25 0 +OP4 E00E26 0 +OP4 E00E27 0 +OP4 E00E28 0 +OP4 E00E29 0 +OP4 E00E2A 0 +OP4 E00E2B 0 +OP4 E00E2C 0 +OP4 E00E2D 0 +OP4 E00E2E 0 +OP4 E00E2F 0 +OP4 E00E30 0 +OP4 E00E31 0 +OP4 E00E32 0 +OP4 E00E33 0 +OP4 E00E34 0 +OP4 E00E35 0 +OP4 E00E36 0 +OP4 E00E37 0 +OP4 E00E38 0 +OP4 E00E39 0 +OP4 E00E3A 0 +OP4 E00E3B 0 +OP4 E00E3C 0 +OP4 E00E3D 0 +OP4 E00E3E 0 +OP4 E00E3F 0 +OP4 E00E40 0 +OP4 E00E41 0 +OP4 E00E42 0 +OP4 E00E43 0 +OP4 E00E44 0 +OP4 E00E45 0 +OP4 E00E46 0 +OP4 E00E47 0 +OP4 E00E48 0 +OP4 E00E49 0 +OP4 E00E4A 0 +OP4 E00E4B 0 +OP4 E00E4C 0 +OP4 E00E4D 0 +OP4 E00E4E 0 +OP4 E00E4F 0 +OP4 E00E50 0 +OP4 E00E51 0 +OP4 E00E52 0 +OP4 E00E53 0 +OP4 E00E54 0 +OP4 E00E55 0 +OP4 E00E56 0 +OP4 E00E57 0 +OP4 E00E58 0 +OP4 E00E59 0 +OP4 E00E5A 0 +OP4 E00E5B 0 +OP4 E00E5C 0 +OP4 E00E5D 0 +OP4 E00E5E 0 +OP4 E00E5F 0 +OP4 E00E60 0 +OP4 E00E61 0 +OP4 E00E62 0 +OP4 E00E63 0 +OP4 E00E64 0 +OP4 E00E65 0 +OP4 E00E66 0 +OP4 E00E67 0 +OP4 E00E68 0 +OP4 E00E69 0 +OP4 E00E6A 0 +OP4 E00E6B 0 +OP4 E00E6C 0 +OP4 E00E6D 0 +OP4 E00E6E 0 +OP4 E00E6F 0 +OP4 E00E70 0 +OP4 E00E71 0 +OP4 E00E72 0 +OP4 E00E73 0 +OP4 E00E74 0 +OP4 E00E75 0 +OP4 E00E76 0 +OP4 E00E77 0 +OP4 E00E78 0 +OP4 E00E79 0 +OP4 E00E7A 0 +OP4 E00E7B 0 +OP4 E00E7C 0 +OP4 E00E7D 0 +OP4 E00E7E 0 +OP4 E00E7F 0 +OP4 E00E80 0 +OP4 E00E81 0 +OP4 E00E82 0 +OP4 E00E83 0 +OP4 E00E84 0 +OP4 E00E85 0 +OP4 E00E86 0 +OP4 E00E87 0 +OP4 E00E88 0 +OP4 E00E89 0 +OP4 E00E8A 0 +OP4 E00E8B 0 +OP4 E00E8C 0 +OP4 E00E8D 0 +OP4 E00E8E 0 +OP4 E00E8F 0 +OP4 E00E90 0 +OP4 E00E91 0 +OP4 E00E92 0 +OP4 E00E93 0 +OP4 E00E94 0 +OP4 E00E95 0 +OP4 E00E96 0 +OP4 E00E97 0 +OP4 E00E98 0 +OP4 E00E99 0 +OP4 E00E9A 0 +OP4 E00E9B 0 +OP4 E00E9C 0 +OP4 E00E9D 0 +OP4 E00E9E 0 +OP4 E00E9F 0 +OP4 E00EA0 0 +OP4 E00EA1 0 +OP4 E00EA2 0 +OP4 E00EA3 0 +OP4 E00EA4 0 +OP4 E00EA5 0 +OP4 E00EA6 0 +OP4 E00EA7 0 +OP4 E00EA8 0 +OP4 E00EA9 0 +OP4 E00EAA 0 +OP4 E00EAB 0 +OP4 E00EAC 0 +OP4 E00EAD 0 +OP4 E00EAE 0 +OP4 E00EAF 0 +OP4 E00EB0 0 +OP4 E00EB1 0 +OP4 E00EB2 0 +OP4 E00EB3 0 +OP4 E00EB4 0 +OP4 E00EB5 0 +OP4 E00EB6 0 +OP4 E00EB7 0 +OP4 E00EB8 0 +OP4 E00EB9 0 +OP4 E00EBA 0 +OP4 E00EBB 0 +OP4 E00EBC 0 +OP4 E00EBD 0 +OP4 E00EBE 0 +OP4 E00EBF 0 +OP4 E00EC0 0 +OP4 E00EC1 0 +OP4 E00EC2 0 +OP4 E00EC3 0 +OP4 E00EC4 0 +OP4 E00EC5 0 +OP4 E00EC6 0 +OP4 E00EC7 0 +OP4 E00EC8 0 +OP4 E00EC9 0 +OP4 E00ECA 0 +OP4 E00ECB 0 +OP4 E00ECC 0 +OP4 E00ECD 0 +OP4 E00ECE 0 +OP4 E00ECF 0 +OP4 E00ED0 0 +OP4 E00ED1 0 +OP4 E00ED2 0 +OP4 E00ED3 0 +OP4 E00ED4 0 +OP4 E00ED5 0 +OP4 E00ED6 0 +OP4 E00ED7 0 +OP4 E00ED8 0 +OP4 E00ED9 0 +OP4 E00EDA 0 +OP4 E00EDB 0 +OP4 E00EDC 0 +OP4 E00EDD 0 +OP4 E00EDE 0 +OP4 E00EDF 0 +OP4 E00EE0 0 +OP4 E00EE1 0 +OP4 E00EE2 0 +OP4 E00EE3 0 +OP4 E00EE4 0 +OP4 E00EE5 0 +OP4 E00EE6 0 +OP4 E00EE7 0 +OP4 E00EE8 0 +OP4 E00EE9 0 +OP4 E00EEA 0 +OP4 E00EEB 0 +OP4 E00EEC 0 +OP4 E00EED 0 +OP4 E00EEE 0 +OP4 E00EEF 0 +OP4 E00EF0 0 +OP4 E00EF1 0 +OP4 E00EF2 0 +OP4 E00EF3 0 +OP4 E00EF4 0 +OP4 E00EF5 0 +OP4 E00EF6 0 +OP4 E00EF7 0 +OP4 E00EF8 0 +OP4 E00EF9 0 +OP4 E00EFA 0 +OP4 E00EFB 0 +OP4 E00EFC 0 +OP4 E00EFD 0 +OP4 E00EFE 0 +OP4 E00EFF 0 +OP4 E00F00 0 +OP4 E00F01 0 +OP4 E00F02 0 +OP4 E00F03 0 +OP4 E00F04 0 +OP4 E00F05 0 +OP4 E00F06 0 +OP4 E00F07 0 +OP4 E00F08 0 +OP4 E00F09 0 +OP4 E00F0A 0 +OP4 E00F0B 0 +OP4 E00F0C 0 +OP4 E00F0D 0 +OP4 E00F0E 0 +OP4 E00F0F 0 +OP4 E00F10 0 +OP4 E00F11 0 +OP4 E00F12 0 +OP4 E00F13 0 +OP4 E00F14 0 +OP4 E00F15 0 +OP4 E00F16 0 +OP4 E00F17 0 +OP4 E00F18 0 +OP4 E00F19 0 +OP4 E00F1A 0 +OP4 E00F1B 0 +OP4 E00F1C 0 +OP4 E00F1D 0 +OP4 E00F1E 0 +OP4 E00F1F 0 +OP4 E00F20 0 +OP4 E00F21 0 +OP4 E00F22 0 +OP4 E00F23 0 +OP4 E00F24 0 +OP4 E00F25 0 +OP4 E00F26 0 +OP4 E00F27 0 +OP4 E00F28 0 +OP4 E00F29 0 +OP4 E00F2A 0 +OP4 E00F2B 0 +OP4 E00F2C 0 +OP4 E00F2D 0 +OP4 E00F2E 0 +OP4 E00F2F 0 +OP4 E00F30 0 diff --git a/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum3_itrace_irisc1.cfg.ext b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum3_itrace_irisc1.cfg.ext new file mode 100644 index 000000000000..130a610a7e93 --- /dev/null +++ b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum3_itrace_irisc1.cfg.ext @@ -0,0 +1,3890 @@ +OP1 Spectrum3 +OP4 ITRACE0 0 +OP4 ITRACE1 1 +OP4 ITRACE2 0 +OP4 ITRACE3 0 +OP4 ITRACE4 0 +OP4 ITRACE5 0 +OP4 ITRACE6 0 +OP4 ITRACE7 0 +OP4 ITRACE8 0 +OP4 ITRACE9 0 +OP4 Main_PhyUC 0 +OP4 TILE0_ITRACE0 0 +OP4 TILE0_ITRACE1 0 +OP4 TILE0_ITRACE2 0 +OP4 TILE0_ITRACE3 0 +OP4 TILE0_ITRACE4 0 +OP4 TILE0_PhyUC 0 +OP4 TILE1_ITRACE0 0 +OP4 TILE1_ITRACE1 0 +OP4 TILE1_ITRACE2 0 +OP4 TILE1_ITRACE3 0 +OP4 TILE1_ITRACE4 0 +OP4 TILE1_PhyUC 0 +OP4 TILE2_ITRACE0 0 +OP4 TILE2_ITRACE1 0 +OP4 TILE2_ITRACE2 0 +OP4 TILE2_ITRACE3 0 +OP4 TILE2_ITRACE4 0 +OP4 TILE2_PhyUC 0 +OP4 TILE3_ITRACE0 0 +OP4 TILE3_ITRACE1 0 +OP4 TILE3_ITRACE2 0 +OP4 TILE3_ITRACE3 0 +OP4 TILE3_ITRACE4 0 +OP4 TILE3_PhyUC 0 +OP4 TILE4_ITRACE0 0 +OP4 TILE4_ITRACE1 0 +OP4 TILE4_ITRACE2 0 +OP4 TILE4_ITRACE3 0 +OP4 TILE4_ITRACE4 0 +OP4 TILE4_PhyUC 0 +OP4 TILE5_ITRACE0 0 +OP4 TILE5_ITRACE1 0 +OP4 TILE5_ITRACE2 0 +OP4 TILE5_ITRACE3 0 +OP4 TILE5_ITRACE4 0 +OP4 TILE5_PhyUC 0 +OP4 TILE6_ITRACE0 0 +OP4 TILE6_ITRACE1 0 +OP4 TILE6_ITRACE2 0 +OP4 TILE6_ITRACE3 0 +OP4 TILE6_ITRACE4 0 +OP4 TILE6_PhyUC 0 +OP4 TILE7_ITRACE0 0 +OP4 TILE7_ITRACE1 0 +OP4 TILE7_ITRACE2 0 +OP4 TILE7_ITRACE3 0 +OP4 TILE7_ITRACE4 0 +OP4 TILE7_PhyUC 0 +OP4 E0003B 0 +OP4 E0003C 0 +OP4 E0003D 0 +OP4 E0003E 0 +OP4 E0003F 0 +OP4 E00040 0 +OP4 E00041 0 +OP4 E00042 0 +OP4 E00043 0 +OP4 E00044 0 +OP4 E00045 0 +OP4 E00046 0 +OP4 E00047 0 +OP4 E00048 0 +OP4 E00049 0 +OP4 E0004A 0 +OP4 E0004B 0 +OP4 E0004C 0 +OP4 E0004D 0 +OP4 E0004E 0 +OP4 E0004F 0 +OP4 E00050 0 +OP4 E00051 0 +OP4 E00052 0 +OP4 E00053 0 +OP4 E00054 0 +OP4 E00055 0 +OP4 E00056 0 +OP4 E00057 0 +OP4 E00058 0 +OP4 E00059 0 +OP4 E0005A 0 +OP4 E0005B 0 +OP4 E0005C 0 +OP4 E0005D 0 +OP4 E0005E 0 +OP4 E0005F 0 +OP4 E00060 0 +OP4 E00061 0 +OP4 E00062 0 +OP4 E00063 0 +OP4 E00064 0 +OP4 E00065 0 +OP4 E00066 0 +OP4 E00067 0 +OP4 E00068 0 +OP4 E00069 0 +OP4 E0006A 0 +OP4 E0006B 0 +OP4 E0006C 0 +OP4 E0006D 0 +OP4 E0006E 0 +OP4 E0006F 0 +OP4 E00070 0 +OP4 E00071 0 +OP4 E00072 0 +OP4 E00073 0 +OP4 E00074 0 +OP4 E00075 0 +OP4 E00076 0 +OP4 E00077 0 +OP4 E00078 0 +OP4 E00079 0 +OP4 E0007A 0 +OP4 E0007B 0 +OP4 E0007C 0 +OP4 E0007D 0 +OP4 E0007E 0 +OP4 E0007F 0 +OP4 E00080 0 +OP4 E00081 0 +OP4 E00082 0 +OP4 E00083 0 +OP4 E00084 0 +OP4 E00085 0 +OP4 E00086 0 +OP4 E00087 0 +OP4 E00088 0 +OP4 E00089 0 +OP4 E0008A 0 +OP4 E0008B 0 +OP4 E0008C 0 +OP4 E0008D 0 +OP4 E0008E 0 +OP4 E0008F 0 +OP4 E00090 0 +OP4 E00091 0 +OP4 E00092 0 +OP4 E00093 0 +OP4 E00094 0 +OP4 E00095 0 +OP4 E00096 0 +OP4 E00097 0 +OP4 E00098 0 +OP4 E00099 0 +OP4 E0009A 0 +OP4 E0009B 0 +OP4 E0009C 0 +OP4 E0009D 0 +OP4 E0009E 0 +OP4 E0009F 0 +OP4 E000A0 0 +OP4 E000A1 0 +OP4 E000A2 0 +OP4 E000A3 0 +OP4 E000A4 0 +OP4 E000A5 0 +OP4 E000A6 0 +OP4 E000A7 0 +OP4 E000A8 0 +OP4 E000A9 0 +OP4 E000AA 0 +OP4 E000AB 0 +OP4 E000AC 0 +OP4 E000AD 0 +OP4 E000AE 0 +OP4 E000AF 0 +OP4 E000B0 0 +OP4 E000B1 0 +OP4 E000B2 0 +OP4 E000B3 0 +OP4 E000B4 0 +OP4 E000B5 0 +OP4 E000B6 0 +OP4 E000B7 0 +OP4 E000B8 0 +OP4 E000B9 0 +OP4 E000BA 0 +OP4 E000BB 0 +OP4 E000BC 0 +OP4 E000BD 0 +OP4 E000BE 0 +OP4 E000BF 0 +OP4 E000C0 0 +OP4 E000C1 0 +OP4 E000C2 0 +OP4 E000C3 0 +OP4 E000C4 0 +OP4 E000C5 0 +OP4 E000C6 0 +OP4 E000C7 0 +OP4 E000C8 0 +OP4 E000C9 0 +OP4 E000CA 0 +OP4 E000CB 0 +OP4 E000CC 0 +OP4 E000CD 0 +OP4 E000CE 0 +OP4 E000CF 0 +OP4 E000D0 0 +OP4 E000D1 0 +OP4 E000D2 0 +OP4 E000D3 0 +OP4 E000D4 0 +OP4 E000D5 0 +OP4 E000D6 0 +OP4 E000D7 0 +OP4 E000D8 0 +OP4 E000D9 0 +OP4 E000DA 0 +OP4 E000DB 0 +OP4 E000DC 0 +OP4 E000DD 0 +OP4 E000DE 0 +OP4 E000DF 0 +OP4 E000E0 0 +OP4 E000E1 0 +OP4 E000E2 0 +OP4 E000E3 0 +OP4 E000E4 0 +OP4 E000E5 0 +OP4 E000E6 0 +OP4 E000E7 0 +OP4 E000E8 0 +OP4 E000E9 0 +OP4 E000EA 0 +OP4 E000EB 0 +OP4 E000EC 0 +OP4 E000ED 0 +OP4 E000EE 0 +OP4 E000EF 0 +OP4 E000F0 0 +OP4 E000F1 0 +OP4 E000F2 0 +OP4 E000F3 0 +OP4 E000F4 0 +OP4 E000F5 0 +OP4 E000F6 0 +OP4 E000F7 0 +OP4 E000F8 0 +OP4 E000F9 0 +OP4 E000FA 0 +OP4 E000FB 0 +OP4 E000FC 0 +OP4 E000FD 0 +OP4 E000FE 0 +OP4 E000FF 0 +OP4 E00100 0 +OP4 E00101 0 +OP4 E00102 0 +OP4 E00103 0 +OP4 E00104 0 +OP4 E00105 0 +OP4 E00106 0 +OP4 E00107 0 +OP4 E00108 0 +OP4 E00109 0 +OP4 E0010A 0 +OP4 E0010B 0 +OP4 E0010C 0 +OP4 E0010D 0 +OP4 E0010E 0 +OP4 E0010F 0 +OP4 E00110 0 +OP4 E00111 0 +OP4 E00112 0 +OP4 E00113 0 +OP4 E00114 0 +OP4 E00115 0 +OP4 E00116 0 +OP4 E00117 0 +OP4 E00118 0 +OP4 E00119 0 +OP4 E0011A 0 +OP4 E0011B 0 +OP4 E0011C 0 +OP4 E0011D 0 +OP4 E0011E 0 +OP4 E0011F 0 +OP4 E00120 0 +OP4 E00121 0 +OP4 E00122 0 +OP4 E00123 0 +OP4 E00124 0 +OP4 E00125 0 +OP4 E00126 0 +OP4 E00127 0 +OP4 E00128 0 +OP4 E00129 0 +OP4 E0012A 0 +OP4 E0012B 0 +OP4 E0012C 0 +OP4 E0012D 0 +OP4 E0012E 0 +OP4 E0012F 0 +OP4 E00130 0 +OP4 E00131 0 +OP4 E00132 0 +OP4 E00133 0 +OP4 E00134 0 +OP4 E00135 0 +OP4 E00136 0 +OP4 E00137 0 +OP4 E00138 0 +OP4 E00139 0 +OP4 E0013A 0 +OP4 E0013B 0 +OP4 E0013C 0 +OP4 E0013D 0 +OP4 E0013E 0 +OP4 E0013F 0 +OP4 E00140 0 +OP4 E00141 0 +OP4 E00142 0 +OP4 E00143 0 +OP4 E00144 0 +OP4 E00145 0 +OP4 E00146 0 +OP4 E00147 0 +OP4 E00148 0 +OP4 E00149 0 +OP4 E0014A 0 +OP4 E0014B 0 +OP4 E0014C 0 +OP4 E0014D 0 +OP4 E0014E 0 +OP4 E0014F 0 +OP4 E00150 0 +OP4 E00151 0 +OP4 E00152 0 +OP4 E00153 0 +OP4 E00154 0 +OP4 E00155 0 +OP4 E00156 0 +OP4 E00157 0 +OP4 E00158 0 +OP4 E00159 0 +OP4 E0015A 0 +OP4 E0015B 0 +OP4 E0015C 0 +OP4 E0015D 0 +OP4 E0015E 0 +OP4 E0015F 0 +OP4 E00160 0 +OP4 E00161 0 +OP4 E00162 0 +OP4 E00163 0 +OP4 E00164 0 +OP4 E00165 0 +OP4 E00166 0 +OP4 E00167 0 +OP4 E00168 0 +OP4 E00169 0 +OP4 E0016A 0 +OP4 E0016B 0 +OP4 E0016C 0 +OP4 E0016D 0 +OP4 E0016E 0 +OP4 E0016F 0 +OP4 E00170 0 +OP4 E00171 0 +OP4 E00172 0 +OP4 E00173 0 +OP4 E00174 0 +OP4 E00175 0 +OP4 E00176 0 +OP4 E00177 0 +OP4 E00178 0 +OP4 E00179 0 +OP4 E0017A 0 +OP4 E0017B 0 +OP4 E0017C 0 +OP4 E0017D 0 +OP4 E0017E 0 +OP4 E0017F 0 +OP4 E00180 0 +OP4 E00181 0 +OP4 E00182 0 +OP4 E00183 0 +OP4 E00184 0 +OP4 E00185 0 +OP4 E00186 0 +OP4 E00187 0 +OP4 E00188 0 +OP4 E00189 0 +OP4 E0018A 0 +OP4 E0018B 0 +OP4 E0018C 0 +OP4 E0018D 0 +OP4 E0018E 0 +OP4 E0018F 0 +OP4 E00190 0 +OP4 E00191 0 +OP4 E00192 0 +OP4 E00193 0 +OP4 E00194 0 +OP4 E00195 0 +OP4 E00196 0 +OP4 E00197 0 +OP4 E00198 0 +OP4 E00199 0 +OP4 E0019A 0 +OP4 E0019B 0 +OP4 E0019C 0 +OP4 E0019D 0 +OP4 E0019E 0 +OP4 E0019F 0 +OP4 E001A0 0 +OP4 E001A1 0 +OP4 E001A2 0 +OP4 E001A3 0 +OP4 E001A4 0 +OP4 E001A5 0 +OP4 E001A6 0 +OP4 E001A7 0 +OP4 E001A8 0 +OP4 E001A9 0 +OP4 E001AA 0 +OP4 E001AB 0 +OP4 E001AC 0 +OP4 E001AD 0 +OP4 E001AE 0 +OP4 E001AF 0 +OP4 E001B0 0 +OP4 E001B1 0 +OP4 E001B2 0 +OP4 E001B3 0 +OP4 E001B4 0 +OP4 E001B5 0 +OP4 E001B6 0 +OP4 E001B7 0 +OP4 E001B8 0 +OP4 E001B9 0 +OP4 E001BA 0 +OP4 E001BB 0 +OP4 E001BC 0 +OP4 E001BD 0 +OP4 E001BE 0 +OP4 E001BF 0 +OP4 E001C0 0 +OP4 E001C1 0 +OP4 E001C2 0 +OP4 E001C3 0 +OP4 E001C4 0 +OP4 E001C5 0 +OP4 E001C6 0 +OP4 E001C7 0 +OP4 E001C8 0 +OP4 E001C9 0 +OP4 E001CA 0 +OP4 E001CB 0 +OP4 E001CC 0 +OP4 E001CD 0 +OP4 E001CE 0 +OP4 E001CF 0 +OP4 E001D0 0 +OP4 E001D1 0 +OP4 E001D2 0 +OP4 E001D3 0 +OP4 E001D4 0 +OP4 E001D5 0 +OP4 E001D6 0 +OP4 E001D7 0 +OP4 E001D8 0 +OP4 E001D9 0 +OP4 E001DA 0 +OP4 E001DB 0 +OP4 E001DC 0 +OP4 E001DD 0 +OP4 E001DE 0 +OP4 E001DF 0 +OP4 E001E0 0 +OP4 E001E1 0 +OP4 E001E2 0 +OP4 E001E3 0 +OP4 E001E4 0 +OP4 E001E5 0 +OP4 E001E6 0 +OP4 E001E7 0 +OP4 E001E8 0 +OP4 E001E9 0 +OP4 E001EA 0 +OP4 E001EB 0 +OP4 E001EC 0 +OP4 E001ED 0 +OP4 E001EE 0 +OP4 E001EF 0 +OP4 E001F0 0 +OP4 E001F1 0 +OP4 E001F2 0 +OP4 E001F3 0 +OP4 E001F4 0 +OP4 E001F5 0 +OP4 E001F6 0 +OP4 E001F7 0 +OP4 E001F8 0 +OP4 E001F9 0 +OP4 E001FA 0 +OP4 E001FB 0 +OP4 E001FC 0 +OP4 E001FD 0 +OP4 E001FE 0 +OP4 E001FF 0 +OP4 E00200 0 +OP4 E00201 0 +OP4 E00202 0 +OP4 E00203 0 +OP4 E00204 0 +OP4 E00205 0 +OP4 E00206 0 +OP4 E00207 0 +OP4 E00208 0 +OP4 E00209 0 +OP4 E0020A 0 +OP4 E0020B 0 +OP4 E0020C 0 +OP4 E0020D 0 +OP4 E0020E 0 +OP4 E0020F 0 +OP4 E00210 0 +OP4 E00211 0 +OP4 E00212 0 +OP4 E00213 0 +OP4 E00214 0 +OP4 E00215 0 +OP4 E00216 0 +OP4 E00217 0 +OP4 E00218 0 +OP4 E00219 0 +OP4 E0021A 0 +OP4 E0021B 0 +OP4 E0021C 0 +OP4 E0021D 0 +OP4 E0021E 0 +OP4 E0021F 0 +OP4 E00220 0 +OP4 E00221 0 +OP4 E00222 0 +OP4 E00223 0 +OP4 E00224 0 +OP4 E00225 0 +OP4 E00226 0 +OP4 E00227 0 +OP4 E00228 0 +OP4 E00229 0 +OP4 E0022A 0 +OP4 E0022B 0 +OP4 E0022C 0 +OP4 E0022D 0 +OP4 E0022E 0 +OP4 E0022F 0 +OP4 E00230 0 +OP4 E00231 0 +OP4 E00232 0 +OP4 E00233 0 +OP4 E00234 0 +OP4 E00235 0 +OP4 E00236 0 +OP4 E00237 0 +OP4 E00238 0 +OP4 E00239 0 +OP4 E0023A 0 +OP4 E0023B 0 +OP4 E0023C 0 +OP4 E0023D 0 +OP4 E0023E 0 +OP4 E0023F 0 +OP4 E00240 0 +OP4 E00241 0 +OP4 E00242 0 +OP4 E00243 0 +OP4 E00244 0 +OP4 E00245 0 +OP4 E00246 0 +OP4 E00247 0 +OP4 E00248 0 +OP4 E00249 0 +OP4 E0024A 0 +OP4 E0024B 0 +OP4 E0024C 0 +OP4 E0024D 0 +OP4 E0024E 0 +OP4 E0024F 0 +OP4 E00250 0 +OP4 E00251 0 +OP4 E00252 0 +OP4 E00253 0 +OP4 E00254 0 +OP4 E00255 0 +OP4 E00256 0 +OP4 E00257 0 +OP4 E00258 0 +OP4 E00259 0 +OP4 E0025A 0 +OP4 E0025B 0 +OP4 E0025C 0 +OP4 E0025D 0 +OP4 E0025E 0 +OP4 E0025F 0 +OP4 E00260 0 +OP4 E00261 0 +OP4 E00262 0 +OP4 E00263 0 +OP4 E00264 0 +OP4 E00265 0 +OP4 E00266 0 +OP4 E00267 0 +OP4 E00268 0 +OP4 E00269 0 +OP4 E0026A 0 +OP4 E0026B 0 +OP4 E0026C 0 +OP4 E0026D 0 +OP4 E0026E 0 +OP4 E0026F 0 +OP4 E00270 0 +OP4 E00271 0 +OP4 E00272 0 +OP4 E00273 0 +OP4 E00274 0 +OP4 E00275 0 +OP4 E00276 0 +OP4 E00277 0 +OP4 E00278 0 +OP4 E00279 0 +OP4 E0027A 0 +OP4 E0027B 0 +OP4 E0027C 0 +OP4 E0027D 0 +OP4 E0027E 0 +OP4 E0027F 0 +OP4 E00280 0 +OP4 E00281 0 +OP4 E00282 0 +OP4 E00283 0 +OP4 E00284 0 +OP4 E00285 0 +OP4 E00286 0 +OP4 E00287 0 +OP4 E00288 0 +OP4 E00289 0 +OP4 E0028A 0 +OP4 E0028B 0 +OP4 E0028C 0 +OP4 E0028D 0 +OP4 E0028E 0 +OP4 E0028F 0 +OP4 E00290 0 +OP4 E00291 0 +OP4 E00292 0 +OP4 E00293 0 +OP4 E00294 0 +OP4 E00295 0 +OP4 E00296 0 +OP4 E00297 0 +OP4 E00298 0 +OP4 E00299 0 +OP4 E0029A 0 +OP4 E0029B 0 +OP4 E0029C 0 +OP4 E0029D 0 +OP4 E0029E 0 +OP4 E0029F 0 +OP4 E002A0 0 +OP4 E002A1 0 +OP4 E002A2 0 +OP4 E002A3 0 +OP4 E002A4 0 +OP4 E002A5 0 +OP4 E002A6 0 +OP4 E002A7 0 +OP4 E002A8 0 +OP4 E002A9 0 +OP4 E002AA 0 +OP4 E002AB 0 +OP4 E002AC 0 +OP4 E002AD 0 +OP4 E002AE 0 +OP4 E002AF 0 +OP4 E002B0 0 +OP4 E002B1 0 +OP4 E002B2 0 +OP4 E002B3 0 +OP4 E002B4 0 +OP4 E002B5 0 +OP4 E002B6 0 +OP4 E002B7 0 +OP4 E002B8 0 +OP4 E002B9 0 +OP4 E002BA 0 +OP4 E002BB 0 +OP4 E002BC 0 +OP4 E002BD 0 +OP4 E002BE 0 +OP4 E002BF 0 +OP4 E002C0 0 +OP4 E002C1 0 +OP4 E002C2 0 +OP4 E002C3 0 +OP4 E002C4 0 +OP4 E002C5 0 +OP4 E002C6 0 +OP4 E002C7 0 +OP4 E002C8 0 +OP4 E002C9 0 +OP4 E002CA 0 +OP4 E002CB 0 +OP4 E002CC 0 +OP4 E002CD 0 +OP4 E002CE 0 +OP4 E002CF 0 +OP4 E002D0 0 +OP4 E002D1 0 +OP4 E002D2 0 +OP4 E002D3 0 +OP4 E002D4 0 +OP4 E002D5 0 +OP4 E002D6 0 +OP4 E002D7 0 +OP4 E002D8 0 +OP4 E002D9 0 +OP4 E002DA 0 +OP4 E002DB 0 +OP4 E002DC 0 +OP4 E002DD 0 +OP4 E002DE 0 +OP4 E002DF 0 +OP4 E002E0 0 +OP4 E002E1 0 +OP4 E002E2 0 +OP4 E002E3 0 +OP4 E002E4 0 +OP4 E002E5 0 +OP4 E002E6 0 +OP4 E002E7 0 +OP4 E002E8 0 +OP4 E002E9 0 +OP4 E002EA 0 +OP4 E002EB 0 +OP4 E002EC 0 +OP4 E002ED 0 +OP4 E002EE 0 +OP4 E002EF 0 +OP4 E002F0 0 +OP4 E002F1 0 +OP4 E002F2 0 +OP4 E002F3 0 +OP4 E002F4 0 +OP4 E002F5 0 +OP4 E002F6 0 +OP4 E002F7 0 +OP4 E002F8 0 +OP4 E002F9 0 +OP4 E002FA 0 +OP4 E002FB 0 +OP4 E002FC 0 +OP4 E002FD 0 +OP4 E002FE 0 +OP4 E002FF 0 +OP4 E00300 0 +OP4 E00301 0 +OP4 E00302 0 +OP4 E00303 0 +OP4 E00304 0 +OP4 E00305 0 +OP4 E00306 0 +OP4 E00307 0 +OP4 E00308 0 +OP4 E00309 0 +OP4 E0030A 0 +OP4 E0030B 0 +OP4 E0030C 0 +OP4 E0030D 0 +OP4 E0030E 0 +OP4 E0030F 0 +OP4 E00310 0 +OP4 E00311 0 +OP4 E00312 0 +OP4 E00313 0 +OP4 E00314 0 +OP4 E00315 0 +OP4 E00316 0 +OP4 E00317 0 +OP4 E00318 0 +OP4 E00319 0 +OP4 E0031A 0 +OP4 E0031B 0 +OP4 E0031C 0 +OP4 E0031D 0 +OP4 E0031E 0 +OP4 E0031F 0 +OP4 E00320 0 +OP4 E00321 0 +OP4 E00322 0 +OP4 E00323 0 +OP4 E00324 0 +OP4 E00325 0 +OP4 E00326 0 +OP4 E00327 0 +OP4 E00328 0 +OP4 E00329 0 +OP4 E0032A 0 +OP4 E0032B 0 +OP4 E0032C 0 +OP4 E0032D 0 +OP4 E0032E 0 +OP4 E0032F 0 +OP4 E00330 0 +OP4 E00331 0 +OP4 E00332 0 +OP4 E00333 0 +OP4 E00334 0 +OP4 E00335 0 +OP4 E00336 0 +OP4 E00337 0 +OP4 E00338 0 +OP4 E00339 0 +OP4 E0033A 0 +OP4 E0033B 0 +OP4 E0033C 0 +OP4 E0033D 0 +OP4 E0033E 0 +OP4 E0033F 0 +OP4 E00340 0 +OP4 E00341 0 +OP4 E00342 0 +OP4 E00343 0 +OP4 E00344 0 +OP4 E00345 0 +OP4 E00346 0 +OP4 E00347 0 +OP4 E00348 0 +OP4 E00349 0 +OP4 E0034A 0 +OP4 E0034B 0 +OP4 E0034C 0 +OP4 E0034D 0 +OP4 E0034E 0 +OP4 E0034F 0 +OP4 E00350 0 +OP4 E00351 0 +OP4 E00352 0 +OP4 E00353 0 +OP4 E00354 0 +OP4 E00355 0 +OP4 E00356 0 +OP4 E00357 0 +OP4 E00358 0 +OP4 E00359 0 +OP4 E0035A 0 +OP4 E0035B 0 +OP4 E0035C 0 +OP4 E0035D 0 +OP4 E0035E 0 +OP4 E0035F 0 +OP4 E00360 0 +OP4 E00361 0 +OP4 E00362 0 +OP4 E00363 0 +OP4 E00364 0 +OP4 E00365 0 +OP4 E00366 0 +OP4 E00367 0 +OP4 E00368 0 +OP4 E00369 0 +OP4 E0036A 0 +OP4 E0036B 0 +OP4 E0036C 0 +OP4 E0036D 0 +OP4 E0036E 0 +OP4 E0036F 0 +OP4 E00370 0 +OP4 E00371 0 +OP4 E00372 0 +OP4 E00373 0 +OP4 E00374 0 +OP4 E00375 0 +OP4 E00376 0 +OP4 E00377 0 +OP4 E00378 0 +OP4 E00379 0 +OP4 E0037A 0 +OP4 E0037B 0 +OP4 E0037C 0 +OP4 E0037D 0 +OP4 E0037E 0 +OP4 E0037F 0 +OP4 E00380 0 +OP4 E00381 0 +OP4 E00382 0 +OP4 E00383 0 +OP4 E00384 0 +OP4 E00385 0 +OP4 E00386 0 +OP4 E00387 0 +OP4 E00388 0 +OP4 E00389 0 +OP4 E0038A 0 +OP4 E0038B 0 +OP4 E0038C 0 +OP4 E0038D 0 +OP4 E0038E 0 +OP4 E0038F 0 +OP4 E00390 0 +OP4 E00391 0 +OP4 E00392 0 +OP4 E00393 0 +OP4 E00394 0 +OP4 E00395 0 +OP4 E00396 0 +OP4 E00397 0 +OP4 E00398 0 +OP4 E00399 0 +OP4 E0039A 0 +OP4 E0039B 0 +OP4 E0039C 0 +OP4 E0039D 0 +OP4 E0039E 0 +OP4 E0039F 0 +OP4 E003A0 0 +OP4 E003A1 0 +OP4 E003A2 0 +OP4 E003A3 0 +OP4 E003A4 0 +OP4 E003A5 0 +OP4 E003A6 0 +OP4 E003A7 0 +OP4 E003A8 0 +OP4 E003A9 0 +OP4 E003AA 0 +OP4 E003AB 0 +OP4 E003AC 0 +OP4 E003AD 0 +OP4 E003AE 0 +OP4 E003AF 0 +OP4 E003B0 0 +OP4 E003B1 0 +OP4 E003B2 0 +OP4 E003B3 0 +OP4 E003B4 0 +OP4 E003B5 0 +OP4 E003B6 0 +OP4 E003B7 0 +OP4 E003B8 0 +OP4 E003B9 0 +OP4 E003BA 0 +OP4 E003BB 0 +OP4 E003BC 0 +OP4 E003BD 0 +OP4 E003BE 0 +OP4 E003BF 0 +OP4 E003C0 0 +OP4 E003C1 0 +OP4 E003C2 0 +OP4 E003C3 0 +OP4 E003C4 0 +OP4 E003C5 0 +OP4 E003C6 0 +OP4 E003C7 0 +OP4 E003C8 0 +OP4 E003C9 0 +OP4 E003CA 0 +OP4 E003CB 0 +OP4 E003CC 0 +OP4 E003CD 0 +OP4 E003CE 0 +OP4 E003CF 0 +OP4 E003D0 0 +OP4 E003D1 0 +OP4 E003D2 0 +OP4 E003D3 0 +OP4 E003D4 0 +OP4 E003D5 0 +OP4 E003D6 0 +OP4 E003D7 0 +OP4 E003D8 0 +OP4 E003D9 0 +OP4 E003DA 0 +OP4 E003DB 0 +OP4 E003DC 0 +OP4 E003DD 0 +OP4 E003DE 0 +OP4 E003DF 0 +OP4 E003E0 0 +OP4 E003E1 0 +OP4 E003E2 0 +OP4 E003E3 0 +OP4 E003E4 0 +OP4 E003E5 0 +OP4 E003E6 0 +OP4 E003E7 0 +OP4 E003E8 0 +OP4 E003E9 0 +OP4 E003EA 0 +OP4 E003EB 0 +OP4 E003EC 0 +OP4 E003ED 0 +OP4 E003EE 0 +OP4 E003EF 0 +OP4 E003F0 0 +OP4 E003F1 0 +OP4 E003F2 0 +OP4 E003F3 0 +OP4 E003F4 0 +OP4 E003F5 0 +OP4 E003F6 0 +OP4 E003F7 0 +OP4 E003F8 0 +OP4 E003F9 0 +OP4 E003FA 0 +OP4 E003FB 0 +OP4 E003FC 0 +OP4 E003FD 0 +OP4 E003FE 0 +OP4 E003FF 0 +OP4 E00400 0 +OP4 E00401 0 +OP4 E00402 0 +OP4 E00403 0 +OP4 E00404 0 +OP4 E00405 0 +OP4 E00406 0 +OP4 E00407 0 +OP4 E00408 0 +OP4 E00409 0 +OP4 E0040A 0 +OP4 E0040B 0 +OP4 E0040C 0 +OP4 E0040D 0 +OP4 E0040E 0 +OP4 E0040F 0 +OP4 E00410 0 +OP4 E00411 0 +OP4 E00412 0 +OP4 E00413 0 +OP4 E00414 0 +OP4 E00415 0 +OP4 E00416 0 +OP4 E00417 0 +OP4 E00418 0 +OP4 E00419 0 +OP4 E0041A 0 +OP4 E0041B 0 +OP4 E0041C 0 +OP4 E0041D 0 +OP4 E0041E 0 +OP4 E0041F 0 +OP4 E00420 0 +OP4 E00421 0 +OP4 E00422 0 +OP4 E00423 0 +OP4 E00424 0 +OP4 E00425 0 +OP4 E00426 0 +OP4 E00427 0 +OP4 E00428 0 +OP4 E00429 0 +OP4 E0042A 0 +OP4 E0042B 0 +OP4 E0042C 0 +OP4 E0042D 0 +OP4 E0042E 0 +OP4 E0042F 0 +OP4 E00430 0 +OP4 E00431 0 +OP4 E00432 0 +OP4 E00433 0 +OP4 E00434 0 +OP4 E00435 0 +OP4 E00436 0 +OP4 E00437 0 +OP4 E00438 0 +OP4 E00439 0 +OP4 E0043A 0 +OP4 E0043B 0 +OP4 E0043C 0 +OP4 E0043D 0 +OP4 E0043E 0 +OP4 E0043F 0 +OP4 E00440 0 +OP4 E00441 0 +OP4 E00442 0 +OP4 E00443 0 +OP4 E00444 0 +OP4 E00445 0 +OP4 E00446 0 +OP4 E00447 0 +OP4 E00448 0 +OP4 E00449 0 +OP4 E0044A 0 +OP4 E0044B 0 +OP4 E0044C 0 +OP4 E0044D 0 +OP4 E0044E 0 +OP4 E0044F 0 +OP4 E00450 0 +OP4 E00451 0 +OP4 E00452 0 +OP4 E00453 0 +OP4 E00454 0 +OP4 E00455 0 +OP4 E00456 0 +OP4 E00457 0 +OP4 E00458 0 +OP4 E00459 0 +OP4 E0045A 0 +OP4 E0045B 0 +OP4 E0045C 0 +OP4 E0045D 0 +OP4 E0045E 0 +OP4 E0045F 0 +OP4 E00460 0 +OP4 E00461 0 +OP4 E00462 0 +OP4 E00463 0 +OP4 E00464 0 +OP4 E00465 0 +OP4 E00466 0 +OP4 E00467 0 +OP4 E00468 0 +OP4 E00469 0 +OP4 E0046A 0 +OP4 E0046B 0 +OP4 E0046C 0 +OP4 E0046D 0 +OP4 E0046E 0 +OP4 E0046F 0 +OP4 E00470 0 +OP4 E00471 0 +OP4 E00472 0 +OP4 E00473 0 +OP4 E00474 0 +OP4 E00475 0 +OP4 E00476 0 +OP4 E00477 0 +OP4 E00478 0 +OP4 E00479 0 +OP4 E0047A 0 +OP4 E0047B 0 +OP4 E0047C 0 +OP4 E0047D 0 +OP4 E0047E 0 +OP4 E0047F 0 +OP4 E00480 0 +OP4 E00481 0 +OP4 E00482 0 +OP4 E00483 0 +OP4 E00484 0 +OP4 E00485 0 +OP4 E00486 0 +OP4 E00487 0 +OP4 E00488 0 +OP4 E00489 0 +OP4 E0048A 0 +OP4 E0048B 0 +OP4 E0048C 0 +OP4 E0048D 0 +OP4 E0048E 0 +OP4 E0048F 0 +OP4 E00490 0 +OP4 E00491 0 +OP4 E00492 0 +OP4 E00493 0 +OP4 E00494 0 +OP4 E00495 0 +OP4 E00496 0 +OP4 E00497 0 +OP4 E00498 0 +OP4 E00499 0 +OP4 E0049A 0 +OP4 E0049B 0 +OP4 E0049C 0 +OP4 E0049D 0 +OP4 E0049E 0 +OP4 E0049F 0 +OP4 E004A0 0 +OP4 E004A1 0 +OP4 E004A2 0 +OP4 E004A3 0 +OP4 E004A4 0 +OP4 E004A5 0 +OP4 E004A6 0 +OP4 E004A7 0 +OP4 E004A8 0 +OP4 E004A9 0 +OP4 E004AA 0 +OP4 E004AB 0 +OP4 E004AC 0 +OP4 E004AD 0 +OP4 E004AE 0 +OP4 E004AF 0 +OP4 E004B0 0 +OP4 E004B1 0 +OP4 E004B2 0 +OP4 E004B3 0 +OP4 E004B4 0 +OP4 E004B5 0 +OP4 E004B6 0 +OP4 E004B7 0 +OP4 E004B8 0 +OP4 E004B9 0 +OP4 E004BA 0 +OP4 E004BB 0 +OP4 E004BC 0 +OP4 E004BD 0 +OP4 E004BE 0 +OP4 E004BF 0 +OP4 E004C0 0 +OP4 E004C1 0 +OP4 E004C2 0 +OP4 E004C3 0 +OP4 E004C4 0 +OP4 E004C5 0 +OP4 E004C6 0 +OP4 E004C7 0 +OP4 E004C8 0 +OP4 E004C9 0 +OP4 E004CA 0 +OP4 E004CB 0 +OP4 E004CC 0 +OP4 E004CD 0 +OP4 E004CE 0 +OP4 E004CF 0 +OP4 E004D0 0 +OP4 E004D1 0 +OP4 E004D2 0 +OP4 E004D3 0 +OP4 E004D4 0 +OP4 E004D5 0 +OP4 E004D6 0 +OP4 E004D7 0 +OP4 E004D8 0 +OP4 E004D9 0 +OP4 E004DA 0 +OP4 E004DB 0 +OP4 E004DC 0 +OP4 E004DD 0 +OP4 E004DE 0 +OP4 E004DF 0 +OP4 E004E0 0 +OP4 E004E1 0 +OP4 E004E2 0 +OP4 E004E3 0 +OP4 E004E4 0 +OP4 E004E5 0 +OP4 E004E6 0 +OP4 E004E7 0 +OP4 E004E8 0 +OP4 E004E9 0 +OP4 E004EA 0 +OP4 E004EB 0 +OP4 E004EC 0 +OP4 E004ED 0 +OP4 E004EE 0 +OP4 E004EF 0 +OP4 E004F0 0 +OP4 E004F1 0 +OP4 E004F2 0 +OP4 E004F3 0 +OP4 E004F4 0 +OP4 E004F5 0 +OP4 E004F6 0 +OP4 E004F7 0 +OP4 E004F8 0 +OP4 E004F9 0 +OP4 E004FA 0 +OP4 E004FB 0 +OP4 E004FC 0 +OP4 E004FD 0 +OP4 E004FE 0 +OP4 E004FF 0 +OP4 E00500 0 +OP4 E00501 0 +OP4 E00502 0 +OP4 E00503 0 +OP4 E00504 0 +OP4 E00505 0 +OP4 E00506 0 +OP4 E00507 0 +OP4 E00508 0 +OP4 E00509 0 +OP4 E0050A 0 +OP4 E0050B 0 +OP4 E0050C 0 +OP4 E0050D 0 +OP4 E0050E 0 +OP4 E0050F 0 +OP4 E00510 0 +OP4 E00511 0 +OP4 E00512 0 +OP4 E00513 0 +OP4 E00514 0 +OP4 E00515 0 +OP4 E00516 0 +OP4 E00517 0 +OP4 E00518 0 +OP4 E00519 0 +OP4 E0051A 0 +OP4 E0051B 0 +OP4 E0051C 0 +OP4 E0051D 0 +OP4 E0051E 0 +OP4 E0051F 0 +OP4 E00520 0 +OP4 E00521 0 +OP4 E00522 0 +OP4 E00523 0 +OP4 E00524 0 +OP4 E00525 0 +OP4 E00526 0 +OP4 E00527 0 +OP4 E00528 0 +OP4 E00529 0 +OP4 E0052A 0 +OP4 E0052B 0 +OP4 E0052C 0 +OP4 E0052D 0 +OP4 E0052E 0 +OP4 E0052F 0 +OP4 E00530 0 +OP4 E00531 0 +OP4 E00532 0 +OP4 E00533 0 +OP4 E00534 0 +OP4 E00535 0 +OP4 E00536 0 +OP4 E00537 0 +OP4 E00538 0 +OP4 E00539 0 +OP4 E0053A 0 +OP4 E0053B 0 +OP4 E0053C 0 +OP4 E0053D 0 +OP4 E0053E 0 +OP4 E0053F 0 +OP4 E00540 0 +OP4 E00541 0 +OP4 E00542 0 +OP4 E00543 0 +OP4 E00544 0 +OP4 E00545 0 +OP4 E00546 0 +OP4 E00547 0 +OP4 E00548 0 +OP4 E00549 0 +OP4 E0054A 0 +OP4 E0054B 0 +OP4 E0054C 0 +OP4 E0054D 0 +OP4 E0054E 0 +OP4 E0054F 0 +OP4 E00550 0 +OP4 E00551 0 +OP4 E00552 0 +OP4 E00553 0 +OP4 E00554 0 +OP4 E00555 0 +OP4 E00556 0 +OP4 E00557 0 +OP4 E00558 0 +OP4 E00559 0 +OP4 E0055A 0 +OP4 E0055B 0 +OP4 E0055C 0 +OP4 E0055D 0 +OP4 E0055E 0 +OP4 E0055F 0 +OP4 E00560 0 +OP4 E00561 0 +OP4 E00562 0 +OP4 E00563 0 +OP4 E00564 0 +OP4 E00565 0 +OP4 E00566 0 +OP4 E00567 0 +OP4 E00568 0 +OP4 E00569 0 +OP4 E0056A 0 +OP4 E0056B 0 +OP4 E0056C 0 +OP4 E0056D 0 +OP4 E0056E 0 +OP4 E0056F 0 +OP4 E00570 0 +OP4 E00571 0 +OP4 E00572 0 +OP4 E00573 0 +OP4 E00574 0 +OP4 E00575 0 +OP4 E00576 0 +OP4 E00577 0 +OP4 E00578 0 +OP4 E00579 0 +OP4 E0057A 0 +OP4 E0057B 0 +OP4 E0057C 0 +OP4 E0057D 0 +OP4 E0057E 0 +OP4 E0057F 0 +OP4 E00580 0 +OP4 E00581 0 +OP4 E00582 0 +OP4 E00583 0 +OP4 E00584 0 +OP4 E00585 0 +OP4 E00586 0 +OP4 E00587 0 +OP4 E00588 0 +OP4 E00589 0 +OP4 E0058A 0 +OP4 E0058B 0 +OP4 E0058C 0 +OP4 E0058D 0 +OP4 E0058E 0 +OP4 E0058F 0 +OP4 E00590 0 +OP4 E00591 0 +OP4 E00592 0 +OP4 E00593 0 +OP4 E00594 0 +OP4 E00595 0 +OP4 E00596 0 +OP4 E00597 0 +OP4 E00598 0 +OP4 E00599 0 +OP4 E0059A 0 +OP4 E0059B 0 +OP4 E0059C 0 +OP4 E0059D 0 +OP4 E0059E 0 +OP4 E0059F 0 +OP4 E005A0 0 +OP4 E005A1 0 +OP4 E005A2 0 +OP4 E005A3 0 +OP4 E005A4 0 +OP4 E005A5 0 +OP4 E005A6 0 +OP4 E005A7 0 +OP4 E005A8 0 +OP4 E005A9 0 +OP4 E005AA 0 +OP4 E005AB 0 +OP4 E005AC 0 +OP4 E005AD 0 +OP4 E005AE 0 +OP4 E005AF 0 +OP4 E005B0 0 +OP4 E005B1 0 +OP4 E005B2 0 +OP4 E005B3 0 +OP4 E005B4 0 +OP4 E005B5 0 +OP4 E005B6 0 +OP4 E005B7 0 +OP4 E005B8 0 +OP4 E005B9 0 +OP4 E005BA 0 +OP4 E005BB 0 +OP4 E005BC 0 +OP4 E005BD 0 +OP4 E005BE 0 +OP4 E005BF 0 +OP4 E005C0 0 +OP4 E005C1 0 +OP4 E005C2 0 +OP4 E005C3 0 +OP4 E005C4 0 +OP4 E005C5 0 +OP4 E005C6 0 +OP4 E005C7 0 +OP4 E005C8 0 +OP4 E005C9 0 +OP4 E005CA 0 +OP4 E005CB 0 +OP4 E005CC 0 +OP4 E005CD 0 +OP4 E005CE 0 +OP4 E005CF 0 +OP4 E005D0 0 +OP4 E005D1 0 +OP4 E005D2 0 +OP4 E005D3 0 +OP4 E005D4 0 +OP4 E005D5 0 +OP4 E005D6 0 +OP4 E005D7 0 +OP4 E005D8 0 +OP4 E005D9 0 +OP4 E005DA 0 +OP4 E005DB 0 +OP4 E005DC 0 +OP4 E005DD 0 +OP4 E005DE 0 +OP4 E005DF 0 +OP4 E005E0 0 +OP4 E005E1 0 +OP4 E005E2 0 +OP4 E005E3 0 +OP4 E005E4 0 +OP4 E005E5 0 +OP4 E005E6 0 +OP4 E005E7 0 +OP4 E005E8 0 +OP4 E005E9 0 +OP4 E005EA 0 +OP4 E005EB 0 +OP4 E005EC 0 +OP4 E005ED 0 +OP4 E005EE 0 +OP4 E005EF 0 +OP4 E005F0 0 +OP4 E005F1 0 +OP4 E005F2 0 +OP4 E005F3 0 +OP4 E005F4 0 +OP4 E005F5 0 +OP4 E005F6 0 +OP4 E005F7 0 +OP4 E005F8 0 +OP4 E005F9 0 +OP4 E005FA 0 +OP4 E005FB 0 +OP4 E005FC 0 +OP4 E005FD 0 +OP4 E005FE 0 +OP4 E005FF 0 +OP4 E00600 0 +OP4 E00601 0 +OP4 E00602 0 +OP4 E00603 0 +OP4 E00604 0 +OP4 E00605 0 +OP4 E00606 0 +OP4 E00607 0 +OP4 E00608 0 +OP4 E00609 0 +OP4 E0060A 0 +OP4 E0060B 0 +OP4 E0060C 0 +OP4 E0060D 0 +OP4 E0060E 0 +OP4 E0060F 0 +OP4 E00610 0 +OP4 E00611 0 +OP4 E00612 0 +OP4 E00613 0 +OP4 E00614 0 +OP4 E00615 0 +OP4 E00616 0 +OP4 E00617 0 +OP4 E00618 0 +OP4 E00619 0 +OP4 E0061A 0 +OP4 E0061B 0 +OP4 E0061C 0 +OP4 E0061D 0 +OP4 E0061E 0 +OP4 E0061F 0 +OP4 E00620 0 +OP4 E00621 0 +OP4 E00622 0 +OP4 E00623 0 +OP4 E00624 0 +OP4 E00625 0 +OP4 E00626 0 +OP4 E00627 0 +OP4 E00628 0 +OP4 E00629 0 +OP4 E0062A 0 +OP4 E0062B 0 +OP4 E0062C 0 +OP4 E0062D 0 +OP4 E0062E 0 +OP4 E0062F 0 +OP4 E00630 0 +OP4 E00631 0 +OP4 E00632 0 +OP4 E00633 0 +OP4 E00634 0 +OP4 E00635 0 +OP4 E00636 0 +OP4 E00637 0 +OP4 E00638 0 +OP4 E00639 0 +OP4 E0063A 0 +OP4 E0063B 0 +OP4 E0063C 0 +OP4 E0063D 0 +OP4 E0063E 0 +OP4 E0063F 0 +OP4 E00640 0 +OP4 E00641 0 +OP4 E00642 0 +OP4 E00643 0 +OP4 E00644 0 +OP4 E00645 0 +OP4 E00646 0 +OP4 E00647 0 +OP4 E00648 0 +OP4 E00649 0 +OP4 E0064A 0 +OP4 E0064B 0 +OP4 E0064C 0 +OP4 E0064D 0 +OP4 E0064E 0 +OP4 E0064F 0 +OP4 E00650 0 +OP4 E00651 0 +OP4 E00652 0 +OP4 E00653 0 +OP4 E00654 0 +OP4 E00655 0 +OP4 E00656 0 +OP4 E00657 0 +OP4 E00658 0 +OP4 E00659 0 +OP4 E0065A 0 +OP4 E0065B 0 +OP4 E0065C 0 +OP4 E0065D 0 +OP4 E0065E 0 +OP4 E0065F 0 +OP4 E00660 0 +OP4 E00661 0 +OP4 E00662 0 +OP4 E00663 0 +OP4 E00664 0 +OP4 E00665 0 +OP4 E00666 0 +OP4 E00667 0 +OP4 E00668 0 +OP4 E00669 0 +OP4 E0066A 0 +OP4 E0066B 0 +OP4 E0066C 0 +OP4 E0066D 0 +OP4 E0066E 0 +OP4 E0066F 0 +OP4 E00670 0 +OP4 E00671 0 +OP4 E00672 0 +OP4 E00673 0 +OP4 E00674 0 +OP4 E00675 0 +OP4 E00676 0 +OP4 E00677 0 +OP4 E00678 0 +OP4 E00679 0 +OP4 E0067A 0 +OP4 E0067B 0 +OP4 E0067C 0 +OP4 E0067D 0 +OP4 E0067E 0 +OP4 E0067F 0 +OP4 E00680 0 +OP4 E00681 0 +OP4 E00682 0 +OP4 E00683 0 +OP4 E00684 0 +OP4 E00685 0 +OP4 E00686 0 +OP4 E00687 0 +OP4 E00688 0 +OP4 E00689 0 +OP4 E0068A 0 +OP4 E0068B 0 +OP4 E0068C 0 +OP4 E0068D 0 +OP4 E0068E 0 +OP4 E0068F 0 +OP4 E00690 0 +OP4 E00691 0 +OP4 E00692 0 +OP4 E00693 0 +OP4 E00694 0 +OP4 E00695 0 +OP4 E00696 0 +OP4 E00697 0 +OP4 E00698 0 +OP4 E00699 0 +OP4 E0069A 0 +OP4 E0069B 0 +OP4 E0069C 0 +OP4 E0069D 0 +OP4 E0069E 0 +OP4 E0069F 0 +OP4 E006A0 0 +OP4 E006A1 0 +OP4 E006A2 0 +OP4 E006A3 0 +OP4 E006A4 0 +OP4 E006A5 0 +OP4 E006A6 0 +OP4 E006A7 0 +OP4 E006A8 0 +OP4 E006A9 0 +OP4 E006AA 0 +OP4 E006AB 0 +OP4 E006AC 0 +OP4 E006AD 0 +OP4 E006AE 0 +OP4 E006AF 0 +OP4 E006B0 0 +OP4 E006B1 0 +OP4 E006B2 0 +OP4 E006B3 0 +OP4 E006B4 0 +OP4 E006B5 0 +OP4 E006B6 0 +OP4 E006B7 0 +OP4 E006B8 0 +OP4 E006B9 0 +OP4 E006BA 0 +OP4 E006BB 0 +OP4 E006BC 0 +OP4 E006BD 0 +OP4 E006BE 0 +OP4 E006BF 0 +OP4 E006C0 0 +OP4 E006C1 0 +OP4 E006C2 0 +OP4 E006C3 0 +OP4 E006C4 0 +OP4 E006C5 0 +OP4 E006C6 0 +OP4 E006C7 0 +OP4 E006C8 0 +OP4 E006C9 0 +OP4 E006CA 0 +OP4 E006CB 0 +OP4 E006CC 0 +OP4 E006CD 0 +OP4 E006CE 0 +OP4 E006CF 0 +OP4 E006D0 0 +OP4 E006D1 0 +OP4 E006D2 0 +OP4 E006D3 0 +OP4 E006D4 0 +OP4 E006D5 0 +OP4 E006D6 0 +OP4 E006D7 0 +OP4 E006D8 0 +OP4 E006D9 0 +OP4 E006DA 0 +OP4 E006DB 0 +OP4 E006DC 0 +OP4 E006DD 0 +OP4 E006DE 0 +OP4 E006DF 0 +OP4 E006E0 0 +OP4 E006E1 0 +OP4 E006E2 0 +OP4 E006E3 0 +OP4 E006E4 0 +OP4 E006E5 0 +OP4 E006E6 0 +OP4 E006E7 0 +OP4 E006E8 0 +OP4 E006E9 0 +OP4 E006EA 0 +OP4 E006EB 0 +OP4 E006EC 0 +OP4 E006ED 0 +OP4 E006EE 0 +OP4 E006EF 0 +OP4 E006F0 0 +OP4 E006F1 0 +OP4 E006F2 0 +OP4 E006F3 0 +OP4 E006F4 0 +OP4 E006F5 0 +OP4 E006F6 0 +OP4 E006F7 0 +OP4 E006F8 0 +OP4 E006F9 0 +OP4 E006FA 0 +OP4 E006FB 0 +OP4 E006FC 0 +OP4 E006FD 0 +OP4 E006FE 0 +OP4 E006FF 0 +OP4 E00700 0 +OP4 E00701 0 +OP4 E00702 0 +OP4 E00703 0 +OP4 E00704 0 +OP4 E00705 0 +OP4 E00706 0 +OP4 E00707 0 +OP4 E00708 0 +OP4 E00709 0 +OP4 E0070A 0 +OP4 E0070B 0 +OP4 E0070C 0 +OP4 E0070D 0 +OP4 E0070E 0 +OP4 E0070F 0 +OP4 E00710 0 +OP4 E00711 0 +OP4 E00712 0 +OP4 E00713 0 +OP4 E00714 0 +OP4 E00715 0 +OP4 E00716 0 +OP4 E00717 0 +OP4 E00718 0 +OP4 E00719 0 +OP4 E0071A 0 +OP4 E0071B 0 +OP4 E0071C 0 +OP4 E0071D 0 +OP4 E0071E 0 +OP4 E0071F 0 +OP4 E00720 0 +OP4 E00721 0 +OP4 E00722 0 +OP4 E00723 0 +OP4 E00724 0 +OP4 E00725 0 +OP4 E00726 0 +OP4 E00727 0 +OP4 E00728 0 +OP4 E00729 0 +OP4 E0072A 0 +OP4 E0072B 0 +OP4 E0072C 0 +OP4 E0072D 0 +OP4 E0072E 0 +OP4 E0072F 0 +OP4 E00730 0 +OP4 E00731 0 +OP4 E00732 0 +OP4 E00733 0 +OP4 E00734 0 +OP4 E00735 0 +OP4 E00736 0 +OP4 E00737 0 +OP4 E00738 0 +OP4 E00739 0 +OP4 E0073A 0 +OP4 E0073B 0 +OP4 E0073C 0 +OP4 E0073D 0 +OP4 E0073E 0 +OP4 E0073F 0 +OP4 E00740 0 +OP4 E00741 0 +OP4 E00742 0 +OP4 E00743 0 +OP4 E00744 0 +OP4 E00745 0 +OP4 E00746 0 +OP4 E00747 0 +OP4 E00748 0 +OP4 E00749 0 +OP4 E0074A 0 +OP4 E0074B 0 +OP4 E0074C 0 +OP4 E0074D 0 +OP4 E0074E 0 +OP4 E0074F 0 +OP4 E00750 0 +OP4 E00751 0 +OP4 E00752 0 +OP4 E00753 0 +OP4 E00754 0 +OP4 E00755 0 +OP4 E00756 0 +OP4 E00757 0 +OP4 E00758 0 +OP4 E00759 0 +OP4 E0075A 0 +OP4 E0075B 0 +OP4 E0075C 0 +OP4 E0075D 0 +OP4 E0075E 0 +OP4 E0075F 0 +OP4 E00760 0 +OP4 E00761 0 +OP4 E00762 0 +OP4 E00763 0 +OP4 E00764 0 +OP4 E00765 0 +OP4 E00766 0 +OP4 E00767 0 +OP4 E00768 0 +OP4 E00769 0 +OP4 E0076A 0 +OP4 E0076B 0 +OP4 E0076C 0 +OP4 E0076D 0 +OP4 E0076E 0 +OP4 E0076F 0 +OP4 E00770 0 +OP4 E00771 0 +OP4 E00772 0 +OP4 E00773 0 +OP4 E00774 0 +OP4 E00775 0 +OP4 E00776 0 +OP4 E00777 0 +OP4 E00778 0 +OP4 E00779 0 +OP4 E0077A 0 +OP4 E0077B 0 +OP4 E0077C 0 +OP4 E0077D 0 +OP4 E0077E 0 +OP4 E0077F 0 +OP4 E00780 0 +OP4 E00781 0 +OP4 E00782 0 +OP4 E00783 0 +OP4 E00784 0 +OP4 E00785 0 +OP4 E00786 0 +OP4 E00787 0 +OP4 E00788 0 +OP4 E00789 0 +OP4 E0078A 0 +OP4 E0078B 0 +OP4 E0078C 0 +OP4 E0078D 0 +OP4 E0078E 0 +OP4 E0078F 0 +OP4 E00790 0 +OP4 E00791 0 +OP4 E00792 0 +OP4 E00793 0 +OP4 E00794 0 +OP4 E00795 0 +OP4 E00796 0 +OP4 E00797 0 +OP4 E00798 0 +OP4 E00799 0 +OP4 E0079A 0 +OP4 E0079B 0 +OP4 E0079C 0 +OP4 E0079D 0 +OP4 E0079E 0 +OP4 E0079F 0 +OP4 E007A0 0 +OP4 E007A1 0 +OP4 E007A2 0 +OP4 E007A3 0 +OP4 E007A4 0 +OP4 E007A5 0 +OP4 E007A6 0 +OP4 E007A7 0 +OP4 E007A8 0 +OP4 E007A9 0 +OP4 E007AA 0 +OP4 E007AB 0 +OP4 E007AC 0 +OP4 E007AD 0 +OP4 E007AE 0 +OP4 E007AF 0 +OP4 E007B0 0 +OP4 E007B1 0 +OP4 E007B2 0 +OP4 E007B3 0 +OP4 E007B4 0 +OP4 E007B5 0 +OP4 E007B6 0 +OP4 E007B7 0 +OP4 E007B8 0 +OP4 E007B9 0 +OP4 E007BA 0 +OP4 E007BB 0 +OP4 E007BC 0 +OP4 E007BD 0 +OP4 E007BE 0 +OP4 E007BF 0 +OP4 E007C0 0 +OP4 E007C1 0 +OP4 E007C2 0 +OP4 E007C3 0 +OP4 E007C4 0 +OP4 E007C5 0 +OP4 E007C6 0 +OP4 E007C7 0 +OP4 E007C8 0 +OP4 E007C9 0 +OP4 E007CA 0 +OP4 E007CB 0 +OP4 E007CC 0 +OP4 E007CD 0 +OP4 E007CE 0 +OP4 E007CF 0 +OP4 E007D0 0 +OP4 E007D1 0 +OP4 E007D2 0 +OP4 E007D3 0 +OP4 E007D4 0 +OP4 E007D5 0 +OP4 E007D6 0 +OP4 E007D7 0 +OP4 E007D8 0 +OP4 E007D9 0 +OP4 E007DA 0 +OP4 E007DB 0 +OP4 E007DC 0 +OP4 E007DD 0 +OP4 E007DE 0 +OP4 E007DF 0 +OP4 E007E0 0 +OP4 E007E1 0 +OP4 E007E2 0 +OP4 E007E3 0 +OP4 E007E4 0 +OP4 E007E5 0 +OP4 E007E6 0 +OP4 E007E7 0 +OP4 E007E8 0 +OP4 E007E9 0 +OP4 E007EA 0 +OP4 E007EB 0 +OP4 E007EC 0 +OP4 E007ED 0 +OP4 E007EE 0 +OP4 E007EF 0 +OP4 E007F0 0 +OP4 E007F1 0 +OP4 E007F2 0 +OP4 E007F3 0 +OP4 E007F4 0 +OP4 E007F5 0 +OP4 E007F6 0 +OP4 E007F7 0 +OP4 E007F8 0 +OP4 E007F9 0 +OP4 E007FA 0 +OP4 E007FB 0 +OP4 E007FC 0 +OP4 E007FD 0 +OP4 E007FE 0 +OP4 E007FF 0 +OP4 E00800 0 +OP4 E00801 0 +OP4 E00802 0 +OP4 E00803 0 +OP4 E00804 0 +OP4 E00805 0 +OP4 E00806 0 +OP4 E00807 0 +OP4 E00808 0 +OP4 E00809 0 +OP4 E0080A 0 +OP4 E0080B 0 +OP4 E0080C 0 +OP4 E0080D 0 +OP4 E0080E 0 +OP4 E0080F 0 +OP4 E00810 0 +OP4 E00811 0 +OP4 E00812 0 +OP4 E00813 0 +OP4 E00814 0 +OP4 E00815 0 +OP4 E00816 0 +OP4 E00817 0 +OP4 E00818 0 +OP4 E00819 0 +OP4 E0081A 0 +OP4 E0081B 0 +OP4 E0081C 0 +OP4 E0081D 0 +OP4 E0081E 0 +OP4 E0081F 0 +OP4 E00820 0 +OP4 E00821 0 +OP4 E00822 0 +OP4 E00823 0 +OP4 E00824 0 +OP4 E00825 0 +OP4 E00826 0 +OP4 E00827 0 +OP4 E00828 0 +OP4 E00829 0 +OP4 E0082A 0 +OP4 E0082B 0 +OP4 E0082C 0 +OP4 E0082D 0 +OP4 E0082E 0 +OP4 E0082F 0 +OP4 E00830 0 +OP4 E00831 0 +OP4 E00832 0 +OP4 E00833 0 +OP4 E00834 0 +OP4 E00835 0 +OP4 E00836 0 +OP4 E00837 0 +OP4 E00838 0 +OP4 E00839 0 +OP4 E0083A 0 +OP4 E0083B 0 +OP4 E0083C 0 +OP4 E0083D 0 +OP4 E0083E 0 +OP4 E0083F 0 +OP4 E00840 0 +OP4 E00841 0 +OP4 E00842 0 +OP4 E00843 0 +OP4 E00844 0 +OP4 E00845 0 +OP4 E00846 0 +OP4 E00847 0 +OP4 E00848 0 +OP4 E00849 0 +OP4 E0084A 0 +OP4 E0084B 0 +OP4 E0084C 0 +OP4 E0084D 0 +OP4 E0084E 0 +OP4 E0084F 0 +OP4 E00850 0 +OP4 E00851 0 +OP4 E00852 0 +OP4 E00853 0 +OP4 E00854 0 +OP4 E00855 0 +OP4 E00856 0 +OP4 E00857 0 +OP4 E00858 0 +OP4 E00859 0 +OP4 E0085A 0 +OP4 E0085B 0 +OP4 E0085C 0 +OP4 E0085D 0 +OP4 E0085E 0 +OP4 E0085F 0 +OP4 E00860 0 +OP4 E00861 0 +OP4 E00862 0 +OP4 E00863 0 +OP4 E00864 0 +OP4 E00865 0 +OP4 E00866 0 +OP4 E00867 0 +OP4 E00868 0 +OP4 E00869 0 +OP4 E0086A 0 +OP4 E0086B 0 +OP4 E0086C 0 +OP4 E0086D 0 +OP4 E0086E 0 +OP4 E0086F 0 +OP4 E00870 0 +OP4 E00871 0 +OP4 E00872 0 +OP4 E00873 0 +OP4 E00874 0 +OP4 E00875 0 +OP4 E00876 0 +OP4 E00877 0 +OP4 E00878 0 +OP4 E00879 0 +OP4 E0087A 0 +OP4 E0087B 0 +OP4 E0087C 0 +OP4 E0087D 0 +OP4 E0087E 0 +OP4 E0087F 0 +OP4 E00880 0 +OP4 E00881 0 +OP4 E00882 0 +OP4 E00883 0 +OP4 E00884 0 +OP4 E00885 0 +OP4 E00886 0 +OP4 E00887 0 +OP4 E00888 0 +OP4 E00889 0 +OP4 E0088A 0 +OP4 E0088B 0 +OP4 E0088C 0 +OP4 E0088D 0 +OP4 E0088E 0 +OP4 E0088F 0 +OP4 E00890 0 +OP4 E00891 0 +OP4 E00892 0 +OP4 E00893 0 +OP4 E00894 0 +OP4 E00895 0 +OP4 E00896 0 +OP4 E00897 0 +OP4 E00898 0 +OP4 E00899 0 +OP4 E0089A 0 +OP4 E0089B 0 +OP4 E0089C 0 +OP4 E0089D 0 +OP4 E0089E 0 +OP4 E0089F 0 +OP4 E008A0 0 +OP4 E008A1 0 +OP4 E008A2 0 +OP4 E008A3 0 +OP4 E008A4 0 +OP4 E008A5 0 +OP4 E008A6 0 +OP4 E008A7 0 +OP4 E008A8 0 +OP4 E008A9 0 +OP4 E008AA 0 +OP4 E008AB 0 +OP4 E008AC 0 +OP4 E008AD 0 +OP4 E008AE 0 +OP4 E008AF 0 +OP4 E008B0 0 +OP4 E008B1 0 +OP4 E008B2 0 +OP4 E008B3 0 +OP4 E008B4 0 +OP4 E008B5 0 +OP4 E008B6 0 +OP4 E008B7 0 +OP4 E008B8 0 +OP4 E008B9 0 +OP4 E008BA 0 +OP4 E008BB 0 +OP4 E008BC 0 +OP4 E008BD 0 +OP4 E008BE 0 +OP4 E008BF 0 +OP4 E008C0 0 +OP4 E008C1 0 +OP4 E008C2 0 +OP4 E008C3 0 +OP4 E008C4 0 +OP4 E008C5 0 +OP4 E008C6 0 +OP4 E008C7 0 +OP4 E008C8 0 +OP4 E008C9 0 +OP4 E008CA 0 +OP4 E008CB 0 +OP4 E008CC 0 +OP4 E008CD 0 +OP4 E008CE 0 +OP4 E008CF 0 +OP4 E008D0 0 +OP4 E008D1 0 +OP4 E008D2 0 +OP4 E008D3 0 +OP4 E008D4 0 +OP4 E008D5 0 +OP4 E008D6 0 +OP4 E008D7 0 +OP4 E008D8 0 +OP4 E008D9 0 +OP4 E008DA 0 +OP4 E008DB 0 +OP4 E008DC 0 +OP4 E008DD 0 +OP4 E008DE 0 +OP4 E008DF 0 +OP4 E008E0 0 +OP4 E008E1 0 +OP4 E008E2 0 +OP4 E008E3 0 +OP4 E008E4 0 +OP4 E008E5 0 +OP4 E008E6 0 +OP4 E008E7 0 +OP4 E008E8 0 +OP4 E008E9 0 +OP4 E008EA 0 +OP4 E008EB 0 +OP4 E008EC 0 +OP4 E008ED 0 +OP4 E008EE 0 +OP4 E008EF 0 +OP4 E008F0 0 +OP4 E008F1 0 +OP4 E008F2 0 +OP4 E008F3 0 +OP4 E008F4 0 +OP4 E008F5 0 +OP4 E008F6 0 +OP4 E008F7 0 +OP4 E008F8 0 +OP4 E008F9 0 +OP4 E008FA 0 +OP4 E008FB 0 +OP4 E008FC 0 +OP4 E008FD 0 +OP4 E008FE 0 +OP4 E008FF 0 +OP4 E00900 0 +OP4 E00901 0 +OP4 E00902 0 +OP4 E00903 0 +OP4 E00904 0 +OP4 E00905 0 +OP4 E00906 0 +OP4 E00907 0 +OP4 E00908 0 +OP4 E00909 0 +OP4 E0090A 0 +OP4 E0090B 0 +OP4 E0090C 0 +OP4 E0090D 0 +OP4 E0090E 0 +OP4 E0090F 0 +OP4 E00910 0 +OP4 E00911 0 +OP4 E00912 0 +OP4 E00913 0 +OP4 E00914 0 +OP4 E00915 0 +OP4 E00916 0 +OP4 E00917 0 +OP4 E00918 0 +OP4 E00919 0 +OP4 E0091A 0 +OP4 E0091B 0 +OP4 E0091C 0 +OP4 E0091D 0 +OP4 E0091E 0 +OP4 E0091F 0 +OP4 E00920 0 +OP4 E00921 0 +OP4 E00922 0 +OP4 E00923 0 +OP4 E00924 0 +OP4 E00925 0 +OP4 E00926 0 +OP4 E00927 0 +OP4 E00928 0 +OP4 E00929 0 +OP4 E0092A 0 +OP4 E0092B 0 +OP4 E0092C 0 +OP4 E0092D 0 +OP4 E0092E 0 +OP4 E0092F 0 +OP4 E00930 0 +OP4 E00931 0 +OP4 E00932 0 +OP4 E00933 0 +OP4 E00934 0 +OP4 E00935 0 +OP4 E00936 0 +OP4 E00937 0 +OP4 E00938 0 +OP4 E00939 0 +OP4 E0093A 0 +OP4 E0093B 0 +OP4 E0093C 0 +OP4 E0093D 0 +OP4 E0093E 0 +OP4 E0093F 0 +OP4 E00940 0 +OP4 E00941 0 +OP4 E00942 0 +OP4 E00943 0 +OP4 E00944 0 +OP4 E00945 0 +OP4 E00946 0 +OP4 E00947 0 +OP4 E00948 0 +OP4 E00949 0 +OP4 E0094A 0 +OP4 E0094B 0 +OP4 E0094C 0 +OP4 E0094D 0 +OP4 E0094E 0 +OP4 E0094F 0 +OP4 E00950 0 +OP4 E00951 0 +OP4 E00952 0 +OP4 E00953 0 +OP4 E00954 0 +OP4 E00955 0 +OP4 E00956 0 +OP4 E00957 0 +OP4 E00958 0 +OP4 E00959 0 +OP4 E0095A 0 +OP4 E0095B 0 +OP4 E0095C 0 +OP4 E0095D 0 +OP4 E0095E 0 +OP4 E0095F 0 +OP4 E00960 0 +OP4 E00961 0 +OP4 E00962 0 +OP4 E00963 0 +OP4 E00964 0 +OP4 E00965 0 +OP4 E00966 0 +OP4 E00967 0 +OP4 E00968 0 +OP4 E00969 0 +OP4 E0096A 0 +OP4 E0096B 0 +OP4 E0096C 0 +OP4 E0096D 0 +OP4 E0096E 0 +OP4 E0096F 0 +OP4 E00970 0 +OP4 E00971 0 +OP4 E00972 0 +OP4 E00973 0 +OP4 E00974 0 +OP4 E00975 0 +OP4 E00976 0 +OP4 E00977 0 +OP4 E00978 0 +OP4 E00979 0 +OP4 E0097A 0 +OP4 E0097B 0 +OP4 E0097C 0 +OP4 E0097D 0 +OP4 E0097E 0 +OP4 E0097F 0 +OP4 E00980 0 +OP4 E00981 0 +OP4 E00982 0 +OP4 E00983 0 +OP4 E00984 0 +OP4 E00985 0 +OP4 E00986 0 +OP4 E00987 0 +OP4 E00988 0 +OP4 E00989 0 +OP4 E0098A 0 +OP4 E0098B 0 +OP4 E0098C 0 +OP4 E0098D 0 +OP4 E0098E 0 +OP4 E0098F 0 +OP4 E00990 0 +OP4 E00991 0 +OP4 E00992 0 +OP4 E00993 0 +OP4 E00994 0 +OP4 E00995 0 +OP4 E00996 0 +OP4 E00997 0 +OP4 E00998 0 +OP4 E00999 0 +OP4 E0099A 0 +OP4 E0099B 0 +OP4 E0099C 0 +OP4 E0099D 0 +OP4 E0099E 0 +OP4 E0099F 0 +OP4 E009A0 0 +OP4 E009A1 0 +OP4 E009A2 0 +OP4 E009A3 0 +OP4 E009A4 0 +OP4 E009A5 0 +OP4 E009A6 0 +OP4 E009A7 0 +OP4 E009A8 0 +OP4 E009A9 0 +OP4 E009AA 0 +OP4 E009AB 0 +OP4 E009AC 0 +OP4 E009AD 0 +OP4 E009AE 0 +OP4 E009AF 0 +OP4 E009B0 0 +OP4 E009B1 0 +OP4 E009B2 0 +OP4 E009B3 0 +OP4 E009B4 0 +OP4 E009B5 0 +OP4 E009B6 0 +OP4 E009B7 0 +OP4 E009B8 0 +OP4 E009B9 0 +OP4 E009BA 0 +OP4 E009BB 0 +OP4 E009BC 0 +OP4 E009BD 0 +OP4 E009BE 0 +OP4 E009BF 0 +OP4 E009C0 0 +OP4 E009C1 0 +OP4 E009C2 0 +OP4 E009C3 0 +OP4 E009C4 0 +OP4 E009C5 0 +OP4 E009C6 0 +OP4 E009C7 0 +OP4 E009C8 0 +OP4 E009C9 0 +OP4 E009CA 0 +OP4 E009CB 0 +OP4 E009CC 0 +OP4 E009CD 0 +OP4 E009CE 0 +OP4 E009CF 0 +OP4 E009D0 0 +OP4 E009D1 0 +OP4 E009D2 0 +OP4 E009D3 0 +OP4 E009D4 0 +OP4 E009D5 0 +OP4 E009D6 0 +OP4 E009D7 0 +OP4 E009D8 0 +OP4 E009D9 0 +OP4 E009DA 0 +OP4 E009DB 0 +OP4 E009DC 0 +OP4 E009DD 0 +OP4 E009DE 0 +OP4 E009DF 0 +OP4 E009E0 0 +OP4 E009E1 0 +OP4 E009E2 0 +OP4 E009E3 0 +OP4 E009E4 0 +OP4 E009E5 0 +OP4 E009E6 0 +OP4 E009E7 0 +OP4 E009E8 0 +OP4 E009E9 0 +OP4 E009EA 0 +OP4 E009EB 0 +OP4 E009EC 0 +OP4 E009ED 0 +OP4 E009EE 0 +OP4 E009EF 0 +OP4 E009F0 0 +OP4 E009F1 0 +OP4 E009F2 0 +OP4 E009F3 0 +OP4 E009F4 0 +OP4 E009F5 0 +OP4 E009F6 0 +OP4 E009F7 0 +OP4 E009F8 0 +OP4 E009F9 0 +OP4 E009FA 0 +OP4 E009FB 0 +OP4 E009FC 0 +OP4 E009FD 0 +OP4 E009FE 0 +OP4 E009FF 0 +OP4 E00A00 0 +OP4 E00A01 0 +OP4 E00A02 0 +OP4 E00A03 0 +OP4 E00A04 0 +OP4 E00A05 0 +OP4 E00A06 0 +OP4 E00A07 0 +OP4 E00A08 0 +OP4 E00A09 0 +OP4 E00A0A 0 +OP4 E00A0B 0 +OP4 E00A0C 0 +OP4 E00A0D 0 +OP4 E00A0E 0 +OP4 E00A0F 0 +OP4 E00A10 0 +OP4 E00A11 0 +OP4 E00A12 0 +OP4 E00A13 0 +OP4 E00A14 0 +OP4 E00A15 0 +OP4 E00A16 0 +OP4 E00A17 0 +OP4 E00A18 0 +OP4 E00A19 0 +OP4 E00A1A 0 +OP4 E00A1B 0 +OP4 E00A1C 0 +OP4 E00A1D 0 +OP4 E00A1E 0 +OP4 E00A1F 0 +OP4 E00A20 0 +OP4 E00A21 0 +OP4 E00A22 0 +OP4 E00A23 0 +OP4 E00A24 0 +OP4 E00A25 0 +OP4 E00A26 0 +OP4 E00A27 0 +OP4 E00A28 0 +OP4 E00A29 0 +OP4 E00A2A 0 +OP4 E00A2B 0 +OP4 E00A2C 0 +OP4 E00A2D 0 +OP4 E00A2E 0 +OP4 E00A2F 0 +OP4 E00A30 0 +OP4 E00A31 0 +OP4 E00A32 0 +OP4 E00A33 0 +OP4 E00A34 0 +OP4 E00A35 0 +OP4 E00A36 0 +OP4 E00A37 0 +OP4 E00A38 0 +OP4 E00A39 0 +OP4 E00A3A 0 +OP4 E00A3B 0 +OP4 E00A3C 0 +OP4 E00A3D 0 +OP4 E00A3E 0 +OP4 E00A3F 0 +OP4 E00A40 0 +OP4 E00A41 0 +OP4 E00A42 0 +OP4 E00A43 0 +OP4 E00A44 0 +OP4 E00A45 0 +OP4 E00A46 0 +OP4 E00A47 0 +OP4 E00A48 0 +OP4 E00A49 0 +OP4 E00A4A 0 +OP4 E00A4B 0 +OP4 E00A4C 0 +OP4 E00A4D 0 +OP4 E00A4E 0 +OP4 E00A4F 0 +OP4 E00A50 0 +OP4 E00A51 0 +OP4 E00A52 0 +OP4 E00A53 0 +OP4 E00A54 0 +OP4 E00A55 0 +OP4 E00A56 0 +OP4 E00A57 0 +OP4 E00A58 0 +OP4 E00A59 0 +OP4 E00A5A 0 +OP4 E00A5B 0 +OP4 E00A5C 0 +OP4 E00A5D 0 +OP4 E00A5E 0 +OP4 E00A5F 0 +OP4 E00A60 0 +OP4 E00A61 0 +OP4 E00A62 0 +OP4 E00A63 0 +OP4 E00A64 0 +OP4 E00A65 0 +OP4 E00A66 0 +OP4 E00A67 0 +OP4 E00A68 0 +OP4 E00A69 0 +OP4 E00A6A 0 +OP4 E00A6B 0 +OP4 E00A6C 0 +OP4 E00A6D 0 +OP4 E00A6E 0 +OP4 E00A6F 0 +OP4 E00A70 0 +OP4 E00A71 0 +OP4 E00A72 0 +OP4 E00A73 0 +OP4 E00A74 0 +OP4 E00A75 0 +OP4 E00A76 0 +OP4 E00A77 0 +OP4 E00A78 0 +OP4 E00A79 0 +OP4 E00A7A 0 +OP4 E00A7B 0 +OP4 E00A7C 0 +OP4 E00A7D 0 +OP4 E00A7E 0 +OP4 E00A7F 0 +OP4 E00A80 0 +OP4 E00A81 0 +OP4 E00A82 0 +OP4 E00A83 0 +OP4 E00A84 0 +OP4 E00A85 0 +OP4 E00A86 0 +OP4 E00A87 0 +OP4 E00A88 0 +OP4 E00A89 0 +OP4 E00A8A 0 +OP4 E00A8B 0 +OP4 E00A8C 0 +OP4 E00A8D 0 +OP4 E00A8E 0 +OP4 E00A8F 0 +OP4 E00A90 0 +OP4 E00A91 0 +OP4 E00A92 0 +OP4 E00A93 0 +OP4 E00A94 0 +OP4 E00A95 0 +OP4 E00A96 0 +OP4 E00A97 0 +OP4 E00A98 0 +OP4 E00A99 0 +OP4 E00A9A 0 +OP4 E00A9B 0 +OP4 E00A9C 0 +OP4 E00A9D 0 +OP4 E00A9E 0 +OP4 E00A9F 0 +OP4 E00AA0 0 +OP4 E00AA1 0 +OP4 E00AA2 0 +OP4 E00AA3 0 +OP4 E00AA4 0 +OP4 E00AA5 0 +OP4 E00AA6 0 +OP4 E00AA7 0 +OP4 E00AA8 0 +OP4 E00AA9 0 +OP4 E00AAA 0 +OP4 E00AAB 0 +OP4 E00AAC 0 +OP4 E00AAD 0 +OP4 E00AAE 0 +OP4 E00AAF 0 +OP4 E00AB0 0 +OP4 E00AB1 0 +OP4 E00AB2 0 +OP4 E00AB3 0 +OP4 E00AB4 0 +OP4 E00AB5 0 +OP4 E00AB6 0 +OP4 E00AB7 0 +OP4 E00AB8 0 +OP4 E00AB9 0 +OP4 E00ABA 0 +OP4 E00ABB 0 +OP4 E00ABC 0 +OP4 E00ABD 0 +OP4 E00ABE 0 +OP4 E00ABF 0 +OP4 E00AC0 0 +OP4 E00AC1 0 +OP4 E00AC2 0 +OP4 E00AC3 0 +OP4 E00AC4 0 +OP4 E00AC5 0 +OP4 E00AC6 0 +OP4 E00AC7 0 +OP4 E00AC8 0 +OP4 E00AC9 0 +OP4 E00ACA 0 +OP4 E00ACB 0 +OP4 E00ACC 0 +OP4 E00ACD 0 +OP4 E00ACE 0 +OP4 E00ACF 0 +OP4 E00AD0 0 +OP4 E00AD1 0 +OP4 E00AD2 0 +OP4 E00AD3 0 +OP4 E00AD4 0 +OP4 E00AD5 0 +OP4 E00AD6 0 +OP4 E00AD7 0 +OP4 E00AD8 0 +OP4 E00AD9 0 +OP4 E00ADA 0 +OP4 E00ADB 0 +OP4 E00ADC 0 +OP4 E00ADD 0 +OP4 E00ADE 0 +OP4 E00ADF 0 +OP4 E00AE0 0 +OP4 E00AE1 0 +OP4 E00AE2 0 +OP4 E00AE3 0 +OP4 E00AE4 0 +OP4 E00AE5 0 +OP4 E00AE6 0 +OP4 E00AE7 0 +OP4 E00AE8 0 +OP4 E00AE9 0 +OP4 E00AEA 0 +OP4 E00AEB 0 +OP4 E00AEC 0 +OP4 E00AED 0 +OP4 E00AEE 0 +OP4 E00AEF 0 +OP4 E00AF0 0 +OP4 E00AF1 0 +OP4 E00AF2 0 +OP4 E00AF3 0 +OP4 E00AF4 0 +OP4 E00AF5 0 +OP4 E00AF6 0 +OP4 E00AF7 0 +OP4 E00AF8 0 +OP4 E00AF9 0 +OP4 E00AFA 0 +OP4 E00AFB 0 +OP4 E00AFC 0 +OP4 E00AFD 0 +OP4 E00AFE 0 +OP4 E00AFF 0 +OP4 E00B00 0 +OP4 E00B01 0 +OP4 E00B02 0 +OP4 E00B03 0 +OP4 E00B04 0 +OP4 E00B05 0 +OP4 E00B06 0 +OP4 E00B07 0 +OP4 E00B08 0 +OP4 E00B09 0 +OP4 E00B0A 0 +OP4 E00B0B 0 +OP4 E00B0C 0 +OP4 E00B0D 0 +OP4 E00B0E 0 +OP4 E00B0F 0 +OP4 E00B10 0 +OP4 E00B11 0 +OP4 E00B12 0 +OP4 E00B13 0 +OP4 E00B14 0 +OP4 E00B15 0 +OP4 E00B16 0 +OP4 E00B17 0 +OP4 E00B18 0 +OP4 E00B19 0 +OP4 E00B1A 0 +OP4 E00B1B 0 +OP4 E00B1C 0 +OP4 E00B1D 0 +OP4 E00B1E 0 +OP4 E00B1F 0 +OP4 E00B20 0 +OP4 E00B21 0 +OP4 E00B22 0 +OP4 E00B23 0 +OP4 E00B24 0 +OP4 E00B25 0 +OP4 E00B26 0 +OP4 E00B27 0 +OP4 E00B28 0 +OP4 E00B29 0 +OP4 E00B2A 0 +OP4 E00B2B 0 +OP4 E00B2C 0 +OP4 E00B2D 0 +OP4 E00B2E 0 +OP4 E00B2F 0 +OP4 E00B30 0 +OP4 E00B31 0 +OP4 E00B32 0 +OP4 E00B33 0 +OP4 E00B34 0 +OP4 E00B35 0 +OP4 E00B36 0 +OP4 E00B37 0 +OP4 E00B38 0 +OP4 E00B39 0 +OP4 E00B3A 0 +OP4 E00B3B 0 +OP4 E00B3C 0 +OP4 E00B3D 0 +OP4 E00B3E 0 +OP4 E00B3F 0 +OP4 E00B40 0 +OP4 E00B41 0 +OP4 E00B42 0 +OP4 E00B43 0 +OP4 E00B44 0 +OP4 E00B45 0 +OP4 E00B46 0 +OP4 E00B47 0 +OP4 E00B48 0 +OP4 E00B49 0 +OP4 E00B4A 0 +OP4 E00B4B 0 +OP4 E00B4C 0 +OP4 E00B4D 0 +OP4 E00B4E 0 +OP4 E00B4F 0 +OP4 E00B50 0 +OP4 E00B51 0 +OP4 E00B52 0 +OP4 E00B53 0 +OP4 E00B54 0 +OP4 E00B55 0 +OP4 E00B56 0 +OP4 E00B57 0 +OP4 E00B58 0 +OP4 E00B59 0 +OP4 E00B5A 0 +OP4 E00B5B 0 +OP4 E00B5C 0 +OP4 E00B5D 0 +OP4 E00B5E 0 +OP4 E00B5F 0 +OP4 E00B60 0 +OP4 E00B61 0 +OP4 E00B62 0 +OP4 E00B63 0 +OP4 E00B64 0 +OP4 E00B65 0 +OP4 E00B66 0 +OP4 E00B67 0 +OP4 E00B68 0 +OP4 E00B69 0 +OP4 E00B6A 0 +OP4 E00B6B 0 +OP4 E00B6C 0 +OP4 E00B6D 0 +OP4 E00B6E 0 +OP4 E00B6F 0 +OP4 E00B70 0 +OP4 E00B71 0 +OP4 E00B72 0 +OP4 E00B73 0 +OP4 E00B74 0 +OP4 E00B75 0 +OP4 E00B76 0 +OP4 E00B77 0 +OP4 E00B78 0 +OP4 E00B79 0 +OP4 E00B7A 0 +OP4 E00B7B 0 +OP4 E00B7C 0 +OP4 E00B7D 0 +OP4 E00B7E 0 +OP4 E00B7F 0 +OP4 E00B80 0 +OP4 E00B81 0 +OP4 E00B82 0 +OP4 E00B83 0 +OP4 E00B84 0 +OP4 E00B85 0 +OP4 E00B86 0 +OP4 E00B87 0 +OP4 E00B88 0 +OP4 E00B89 0 +OP4 E00B8A 0 +OP4 E00B8B 0 +OP4 E00B8C 0 +OP4 E00B8D 0 +OP4 E00B8E 0 +OP4 E00B8F 0 +OP4 E00B90 0 +OP4 E00B91 0 +OP4 E00B92 0 +OP4 E00B93 0 +OP4 E00B94 0 +OP4 E00B95 0 +OP4 E00B96 0 +OP4 E00B97 0 +OP4 E00B98 0 +OP4 E00B99 0 +OP4 E00B9A 0 +OP4 E00B9B 0 +OP4 E00B9C 0 +OP4 E00B9D 0 +OP4 E00B9E 0 +OP4 E00B9F 0 +OP4 E00BA0 0 +OP4 E00BA1 0 +OP4 E00BA2 0 +OP4 E00BA3 0 +OP4 E00BA4 0 +OP4 E00BA5 0 +OP4 E00BA6 0 +OP4 E00BA7 0 +OP4 E00BA8 0 +OP4 E00BA9 0 +OP4 E00BAA 0 +OP4 E00BAB 0 +OP4 E00BAC 0 +OP4 E00BAD 0 +OP4 E00BAE 0 +OP4 E00BAF 0 +OP4 E00BB0 0 +OP4 E00BB1 0 +OP4 E00BB2 0 +OP4 E00BB3 0 +OP4 E00BB4 0 +OP4 E00BB5 0 +OP4 E00BB6 0 +OP4 E00BB7 0 +OP4 E00BB8 0 +OP4 E00BB9 0 +OP4 E00BBA 0 +OP4 E00BBB 0 +OP4 E00BBC 0 +OP4 E00BBD 0 +OP4 E00BBE 0 +OP4 E00BBF 0 +OP4 E00BC0 0 +OP4 E00BC1 0 +OP4 E00BC2 0 +OP4 E00BC3 0 +OP4 E00BC4 0 +OP4 E00BC5 0 +OP4 E00BC6 0 +OP4 E00BC7 0 +OP4 E00BC8 0 +OP4 E00BC9 0 +OP4 E00BCA 0 +OP4 E00BCB 0 +OP4 E00BCC 0 +OP4 E00BCD 0 +OP4 E00BCE 0 +OP4 E00BCF 0 +OP4 E00BD0 0 +OP4 E00BD1 0 +OP4 E00BD2 0 +OP4 E00BD3 0 +OP4 E00BD4 0 +OP4 E00BD5 0 +OP4 E00BD6 0 +OP4 E00BD7 0 +OP4 E00BD8 0 +OP4 E00BD9 0 +OP4 E00BDA 0 +OP4 E00BDB 0 +OP4 E00BDC 0 +OP4 E00BDD 0 +OP4 E00BDE 0 +OP4 E00BDF 0 +OP4 E00BE0 0 +OP4 E00BE1 0 +OP4 E00BE2 0 +OP4 E00BE3 0 +OP4 E00BE4 0 +OP4 E00BE5 0 +OP4 E00BE6 0 +OP4 E00BE7 0 +OP4 E00BE8 0 +OP4 E00BE9 0 +OP4 E00BEA 0 +OP4 E00BEB 0 +OP4 E00BEC 0 +OP4 E00BED 0 +OP4 E00BEE 0 +OP4 E00BEF 0 +OP4 E00BF0 0 +OP4 E00BF1 0 +OP4 E00BF2 0 +OP4 E00BF3 0 +OP4 E00BF4 0 +OP4 E00BF5 0 +OP4 E00BF6 0 +OP4 E00BF7 0 +OP4 E00BF8 0 +OP4 E00BF9 0 +OP4 E00BFA 0 +OP4 E00BFB 0 +OP4 E00BFC 0 +OP4 E00BFD 0 +OP4 E00BFE 0 +OP4 E00BFF 0 +OP4 E00C00 0 +OP4 E00C01 0 +OP4 E00C02 0 +OP4 E00C03 0 +OP4 E00C04 0 +OP4 E00C05 0 +OP4 E00C06 0 +OP4 E00C07 0 +OP4 E00C08 0 +OP4 E00C09 0 +OP4 E00C0A 0 +OP4 E00C0B 0 +OP4 E00C0C 0 +OP4 E00C0D 0 +OP4 E00C0E 0 +OP4 E00C0F 0 +OP4 E00C10 0 +OP4 E00C11 0 +OP4 E00C12 0 +OP4 E00C13 0 +OP4 E00C14 0 +OP4 E00C15 0 +OP4 E00C16 0 +OP4 E00C17 0 +OP4 E00C18 0 +OP4 E00C19 0 +OP4 E00C1A 0 +OP4 E00C1B 0 +OP4 E00C1C 0 +OP4 E00C1D 0 +OP4 E00C1E 0 +OP4 E00C1F 0 +OP4 E00C20 0 +OP4 E00C21 0 +OP4 E00C22 0 +OP4 E00C23 0 +OP4 E00C24 0 +OP4 E00C25 0 +OP4 E00C26 0 +OP4 E00C27 0 +OP4 E00C28 0 +OP4 E00C29 0 +OP4 E00C2A 0 +OP4 E00C2B 0 +OP4 E00C2C 0 +OP4 E00C2D 0 +OP4 E00C2E 0 +OP4 E00C2F 0 +OP4 E00C30 0 +OP4 E00C31 0 +OP4 E00C32 0 +OP4 E00C33 0 +OP4 E00C34 0 +OP4 E00C35 0 +OP4 E00C36 0 +OP4 E00C37 0 +OP4 E00C38 0 +OP4 E00C39 0 +OP4 E00C3A 0 +OP4 E00C3B 0 +OP4 E00C3C 0 +OP4 E00C3D 0 +OP4 E00C3E 0 +OP4 E00C3F 0 +OP4 E00C40 0 +OP4 E00C41 0 +OP4 E00C42 0 +OP4 E00C43 0 +OP4 E00C44 0 +OP4 E00C45 0 +OP4 E00C46 0 +OP4 E00C47 0 +OP4 E00C48 0 +OP4 E00C49 0 +OP4 E00C4A 0 +OP4 E00C4B 0 +OP4 E00C4C 0 +OP4 E00C4D 0 +OP4 E00C4E 0 +OP4 E00C4F 0 +OP4 E00C50 0 +OP4 E00C51 0 +OP4 E00C52 0 +OP4 E00C53 0 +OP4 E00C54 0 +OP4 E00C55 0 +OP4 E00C56 0 +OP4 E00C57 0 +OP4 E00C58 0 +OP4 E00C59 0 +OP4 E00C5A 0 +OP4 E00C5B 0 +OP4 E00C5C 0 +OP4 E00C5D 0 +OP4 E00C5E 0 +OP4 E00C5F 0 +OP4 E00C60 0 +OP4 E00C61 0 +OP4 E00C62 0 +OP4 E00C63 0 +OP4 E00C64 0 +OP4 E00C65 0 +OP4 E00C66 0 +OP4 E00C67 0 +OP4 E00C68 0 +OP4 E00C69 0 +OP4 E00C6A 0 +OP4 E00C6B 0 +OP4 E00C6C 0 +OP4 E00C6D 0 +OP4 E00C6E 0 +OP4 E00C6F 0 +OP4 E00C70 0 +OP4 E00C71 0 +OP4 E00C72 0 +OP4 E00C73 0 +OP4 E00C74 0 +OP4 E00C75 0 +OP4 E00C76 0 +OP4 E00C77 0 +OP4 E00C78 0 +OP4 E00C79 0 +OP4 E00C7A 0 +OP4 E00C7B 0 +OP4 E00C7C 0 +OP4 E00C7D 0 +OP4 E00C7E 0 +OP4 E00C7F 0 +OP4 E00C80 0 +OP4 E00C81 0 +OP4 E00C82 0 +OP4 E00C83 0 +OP4 E00C84 0 +OP4 E00C85 0 +OP4 E00C86 0 +OP4 E00C87 0 +OP4 E00C88 0 +OP4 E00C89 0 +OP4 E00C8A 0 +OP4 E00C8B 0 +OP4 E00C8C 0 +OP4 E00C8D 0 +OP4 E00C8E 0 +OP4 E00C8F 0 +OP4 E00C90 0 +OP4 E00C91 0 +OP4 E00C92 0 +OP4 E00C93 0 +OP4 E00C94 0 +OP4 E00C95 0 +OP4 E00C96 0 +OP4 E00C97 0 +OP4 E00C98 0 +OP4 E00C99 0 +OP4 E00C9A 0 +OP4 E00C9B 0 +OP4 E00C9C 0 +OP4 E00C9D 0 +OP4 E00C9E 0 +OP4 E00C9F 0 +OP4 E00CA0 0 +OP4 E00CA1 0 +OP4 E00CA2 0 +OP4 E00CA3 0 +OP4 E00CA4 0 +OP4 E00CA5 0 +OP4 E00CA6 0 +OP4 E00CA7 0 +OP4 E00CA8 0 +OP4 E00CA9 0 +OP4 E00CAA 0 +OP4 E00CAB 0 +OP4 E00CAC 0 +OP4 E00CAD 0 +OP4 E00CAE 0 +OP4 E00CAF 0 +OP4 E00CB0 0 +OP4 E00CB1 0 +OP4 E00CB2 0 +OP4 E00CB3 0 +OP4 E00CB4 0 +OP4 E00CB5 0 +OP4 E00CB6 0 +OP4 E00CB7 0 +OP4 E00CB8 0 +OP4 E00CB9 0 +OP4 E00CBA 0 +OP4 E00CBB 0 +OP4 E00CBC 0 +OP4 E00CBD 0 +OP4 E00CBE 0 +OP4 E00CBF 0 +OP4 E00CC0 0 +OP4 E00CC1 0 +OP4 E00CC2 0 +OP4 E00CC3 0 +OP4 E00CC4 0 +OP4 E00CC5 0 +OP4 E00CC6 0 +OP4 E00CC7 0 +OP4 E00CC8 0 +OP4 E00CC9 0 +OP4 E00CCA 0 +OP4 E00CCB 0 +OP4 E00CCC 0 +OP4 E00CCD 0 +OP4 E00CCE 0 +OP4 E00CCF 0 +OP4 E00CD0 0 +OP4 E00CD1 0 +OP4 E00CD2 0 +OP4 E00CD3 0 +OP4 E00CD4 0 +OP4 E00CD5 0 +OP4 E00CD6 0 +OP4 E00CD7 0 +OP4 E00CD8 0 +OP4 E00CD9 0 +OP4 E00CDA 0 +OP4 E00CDB 0 +OP4 E00CDC 0 +OP4 E00CDD 0 +OP4 E00CDE 0 +OP4 E00CDF 0 +OP4 E00CE0 0 +OP4 E00CE1 0 +OP4 E00CE2 0 +OP4 E00CE3 0 +OP4 E00CE4 0 +OP4 E00CE5 0 +OP4 E00CE6 0 +OP4 E00CE7 0 +OP4 E00CE8 0 +OP4 E00CE9 0 +OP4 E00CEA 0 +OP4 E00CEB 0 +OP4 E00CEC 0 +OP4 E00CED 0 +OP4 E00CEE 0 +OP4 E00CEF 0 +OP4 E00CF0 0 +OP4 E00CF1 0 +OP4 E00CF2 0 +OP4 E00CF3 0 +OP4 E00CF4 0 +OP4 E00CF5 0 +OP4 E00CF6 0 +OP4 E00CF7 0 +OP4 E00CF8 0 +OP4 E00CF9 0 +OP4 E00CFA 0 +OP4 E00CFB 0 +OP4 E00CFC 0 +OP4 E00CFD 0 +OP4 E00CFE 0 +OP4 E00CFF 0 +OP4 E00D00 0 +OP4 E00D01 0 +OP4 E00D02 0 +OP4 E00D03 0 +OP4 E00D04 0 +OP4 E00D05 0 +OP4 E00D06 0 +OP4 E00D07 0 +OP4 E00D08 0 +OP4 E00D09 0 +OP4 E00D0A 0 +OP4 E00D0B 0 +OP4 E00D0C 0 +OP4 E00D0D 0 +OP4 E00D0E 0 +OP4 E00D0F 0 +OP4 E00D10 0 +OP4 E00D11 0 +OP4 E00D12 0 +OP4 E00D13 0 +OP4 E00D14 0 +OP4 E00D15 0 +OP4 E00D16 0 +OP4 E00D17 0 +OP4 E00D18 0 +OP4 E00D19 0 +OP4 E00D1A 0 +OP4 E00D1B 0 +OP4 E00D1C 0 +OP4 E00D1D 0 +OP4 E00D1E 0 +OP4 E00D1F 0 +OP4 E00D20 0 +OP4 E00D21 0 +OP4 E00D22 0 +OP4 E00D23 0 +OP4 E00D24 0 +OP4 E00D25 0 +OP4 E00D26 0 +OP4 E00D27 0 +OP4 E00D28 0 +OP4 E00D29 0 +OP4 E00D2A 0 +OP4 E00D2B 0 +OP4 E00D2C 0 +OP4 E00D2D 0 +OP4 E00D2E 0 +OP4 E00D2F 0 +OP4 E00D30 0 +OP4 E00D31 0 +OP4 E00D32 0 +OP4 E00D33 0 +OP4 E00D34 0 +OP4 E00D35 0 +OP4 E00D36 0 +OP4 E00D37 0 +OP4 E00D38 0 +OP4 E00D39 0 +OP4 E00D3A 0 +OP4 E00D3B 0 +OP4 E00D3C 0 +OP4 E00D3D 0 +OP4 E00D3E 0 +OP4 E00D3F 0 +OP4 E00D40 0 +OP4 E00D41 0 +OP4 E00D42 0 +OP4 E00D43 0 +OP4 E00D44 0 +OP4 E00D45 0 +OP4 E00D46 0 +OP4 E00D47 0 +OP4 E00D48 0 +OP4 E00D49 0 +OP4 E00D4A 0 +OP4 E00D4B 0 +OP4 E00D4C 0 +OP4 E00D4D 0 +OP4 E00D4E 0 +OP4 E00D4F 0 +OP4 E00D50 0 +OP4 E00D51 0 +OP4 E00D52 0 +OP4 E00D53 0 +OP4 E00D54 0 +OP4 E00D55 0 +OP4 E00D56 0 +OP4 E00D57 0 +OP4 E00D58 0 +OP4 E00D59 0 +OP4 E00D5A 0 +OP4 E00D5B 0 +OP4 E00D5C 0 +OP4 E00D5D 0 +OP4 E00D5E 0 +OP4 E00D5F 0 +OP4 E00D60 0 +OP4 E00D61 0 +OP4 E00D62 0 +OP4 E00D63 0 +OP4 E00D64 0 +OP4 E00D65 0 +OP4 E00D66 0 +OP4 E00D67 0 +OP4 E00D68 0 +OP4 E00D69 0 +OP4 E00D6A 0 +OP4 E00D6B 0 +OP4 E00D6C 0 +OP4 E00D6D 0 +OP4 E00D6E 0 +OP4 E00D6F 0 +OP4 E00D70 0 +OP4 E00D71 0 +OP4 E00D72 0 +OP4 E00D73 0 +OP4 E00D74 0 +OP4 E00D75 0 +OP4 E00D76 0 +OP4 E00D77 0 +OP4 E00D78 0 +OP4 E00D79 0 +OP4 E00D7A 0 +OP4 E00D7B 0 +OP4 E00D7C 0 +OP4 E00D7D 0 +OP4 E00D7E 0 +OP4 E00D7F 0 +OP4 E00D80 0 +OP4 E00D81 0 +OP4 E00D82 0 +OP4 E00D83 0 +OP4 E00D84 0 +OP4 E00D85 0 +OP4 E00D86 0 +OP4 E00D87 0 +OP4 E00D88 0 +OP4 E00D89 0 +OP4 E00D8A 0 +OP4 E00D8B 0 +OP4 E00D8C 0 +OP4 E00D8D 0 +OP4 E00D8E 0 +OP4 E00D8F 0 +OP4 E00D90 0 +OP4 E00D91 0 +OP4 E00D92 0 +OP4 E00D93 0 +OP4 E00D94 0 +OP4 E00D95 0 +OP4 E00D96 0 +OP4 E00D97 0 +OP4 E00D98 0 +OP4 E00D99 0 +OP4 E00D9A 0 +OP4 E00D9B 0 +OP4 E00D9C 0 +OP4 E00D9D 0 +OP4 E00D9E 0 +OP4 E00D9F 0 +OP4 E00DA0 0 +OP4 E00DA1 0 +OP4 E00DA2 0 +OP4 E00DA3 0 +OP4 E00DA4 0 +OP4 E00DA5 0 +OP4 E00DA6 0 +OP4 E00DA7 0 +OP4 E00DA8 0 +OP4 E00DA9 0 +OP4 E00DAA 0 +OP4 E00DAB 0 +OP4 E00DAC 0 +OP4 E00DAD 0 +OP4 E00DAE 0 +OP4 E00DAF 0 +OP4 E00DB0 0 +OP4 E00DB1 0 +OP4 E00DB2 0 +OP4 E00DB3 0 +OP4 E00DB4 0 +OP4 E00DB5 0 +OP4 E00DB6 0 +OP4 E00DB7 0 +OP4 E00DB8 0 +OP4 E00DB9 0 +OP4 E00DBA 0 +OP4 E00DBB 0 +OP4 E00DBC 0 +OP4 E00DBD 0 +OP4 E00DBE 0 +OP4 E00DBF 0 +OP4 E00DC0 0 +OP4 E00DC1 0 +OP4 E00DC2 0 +OP4 E00DC3 0 +OP4 E00DC4 0 +OP4 E00DC5 0 +OP4 E00DC6 0 +OP4 E00DC7 0 +OP4 E00DC8 0 +OP4 E00DC9 0 +OP4 E00DCA 0 +OP4 E00DCB 0 +OP4 E00DCC 0 +OP4 E00DCD 0 +OP4 E00DCE 0 +OP4 E00DCF 0 +OP4 E00DD0 0 +OP4 E00DD1 0 +OP4 E00DD2 0 +OP4 E00DD3 0 +OP4 E00DD4 0 +OP4 E00DD5 0 +OP4 E00DD6 0 +OP4 E00DD7 0 +OP4 E00DD8 0 +OP4 E00DD9 0 +OP4 E00DDA 0 +OP4 E00DDB 0 +OP4 E00DDC 0 +OP4 E00DDD 0 +OP4 E00DDE 0 +OP4 E00DDF 0 +OP4 E00DE0 0 +OP4 E00DE1 0 +OP4 E00DE2 0 +OP4 E00DE3 0 +OP4 E00DE4 0 +OP4 E00DE5 0 +OP4 E00DE6 0 +OP4 E00DE7 0 +OP4 E00DE8 0 +OP4 E00DE9 0 +OP4 E00DEA 0 +OP4 E00DEB 0 +OP4 E00DEC 0 +OP4 E00DED 0 +OP4 E00DEE 0 +OP4 E00DEF 0 +OP4 E00DF0 0 +OP4 E00DF1 0 +OP4 E00DF2 0 +OP4 E00DF3 0 +OP4 E00DF4 0 +OP4 E00DF5 0 +OP4 E00DF6 0 +OP4 E00DF7 0 +OP4 E00DF8 0 +OP4 E00DF9 0 +OP4 E00DFA 0 +OP4 E00DFB 0 +OP4 E00DFC 0 +OP4 E00DFD 0 +OP4 E00DFE 0 +OP4 E00DFF 0 +OP4 E00E00 0 +OP4 E00E01 0 +OP4 E00E02 0 +OP4 E00E03 0 +OP4 E00E04 0 +OP4 E00E05 0 +OP4 E00E06 0 +OP4 E00E07 0 +OP4 E00E08 0 +OP4 E00E09 0 +OP4 E00E0A 0 +OP4 E00E0B 0 +OP4 E00E0C 0 +OP4 E00E0D 0 +OP4 E00E0E 0 +OP4 E00E0F 0 +OP4 E00E10 0 +OP4 E00E11 0 +OP4 E00E12 0 +OP4 E00E13 0 +OP4 E00E14 0 +OP4 E00E15 0 +OP4 E00E16 0 +OP4 E00E17 0 +OP4 E00E18 0 +OP4 E00E19 0 +OP4 E00E1A 0 +OP4 E00E1B 0 +OP4 E00E1C 0 +OP4 E00E1D 0 +OP4 E00E1E 0 +OP4 E00E1F 0 +OP4 E00E20 0 +OP4 E00E21 0 +OP4 E00E22 0 +OP4 E00E23 0 +OP4 E00E24 0 +OP4 E00E25 0 +OP4 E00E26 0 +OP4 E00E27 0 +OP4 E00E28 0 +OP4 E00E29 0 +OP4 E00E2A 0 +OP4 E00E2B 0 +OP4 E00E2C 0 +OP4 E00E2D 0 +OP4 E00E2E 0 +OP4 E00E2F 0 +OP4 E00E30 0 +OP4 E00E31 0 +OP4 E00E32 0 +OP4 E00E33 0 +OP4 E00E34 0 +OP4 E00E35 0 +OP4 E00E36 0 +OP4 E00E37 0 +OP4 E00E38 0 +OP4 E00E39 0 +OP4 E00E3A 0 +OP4 E00E3B 0 +OP4 E00E3C 0 +OP4 E00E3D 0 +OP4 E00E3E 0 +OP4 E00E3F 0 +OP4 E00E40 0 +OP4 E00E41 0 +OP4 E00E42 0 +OP4 E00E43 0 +OP4 E00E44 0 +OP4 E00E45 0 +OP4 E00E46 0 +OP4 E00E47 0 +OP4 E00E48 0 +OP4 E00E49 0 +OP4 E00E4A 0 +OP4 E00E4B 0 +OP4 E00E4C 0 +OP4 E00E4D 0 +OP4 E00E4E 0 +OP4 E00E4F 0 +OP4 E00E50 0 +OP4 E00E51 0 +OP4 E00E52 0 +OP4 E00E53 0 +OP4 E00E54 0 +OP4 E00E55 0 +OP4 E00E56 0 +OP4 E00E57 0 +OP4 E00E58 0 +OP4 E00E59 0 +OP4 E00E5A 0 +OP4 E00E5B 0 +OP4 E00E5C 0 +OP4 E00E5D 0 +OP4 E00E5E 0 +OP4 E00E5F 0 +OP4 E00E60 0 +OP4 E00E61 0 +OP4 E00E62 0 +OP4 E00E63 0 +OP4 E00E64 0 +OP4 E00E65 0 +OP4 E00E66 0 +OP4 E00E67 0 +OP4 E00E68 0 +OP4 E00E69 0 +OP4 E00E6A 0 +OP4 E00E6B 0 +OP4 E00E6C 0 +OP4 E00E6D 0 +OP4 E00E6E 0 +OP4 E00E6F 0 +OP4 E00E70 0 +OP4 E00E71 0 +OP4 E00E72 0 +OP4 E00E73 0 +OP4 E00E74 0 +OP4 E00E75 0 +OP4 E00E76 0 +OP4 E00E77 0 +OP4 E00E78 0 +OP4 E00E79 0 +OP4 E00E7A 0 +OP4 E00E7B 0 +OP4 E00E7C 0 +OP4 E00E7D 0 +OP4 E00E7E 0 +OP4 E00E7F 0 +OP4 E00E80 0 +OP4 E00E81 0 +OP4 E00E82 0 +OP4 E00E83 0 +OP4 E00E84 0 +OP4 E00E85 0 +OP4 E00E86 0 +OP4 E00E87 0 +OP4 E00E88 0 +OP4 E00E89 0 +OP4 E00E8A 0 +OP4 E00E8B 0 +OP4 E00E8C 0 +OP4 E00E8D 0 +OP4 E00E8E 0 +OP4 E00E8F 0 +OP4 E00E90 0 +OP4 E00E91 0 +OP4 E00E92 0 +OP4 E00E93 0 +OP4 E00E94 0 +OP4 E00E95 0 +OP4 E00E96 0 +OP4 E00E97 0 +OP4 E00E98 0 +OP4 E00E99 0 +OP4 E00E9A 0 +OP4 E00E9B 0 +OP4 E00E9C 0 +OP4 E00E9D 0 +OP4 E00E9E 0 +OP4 E00E9F 0 +OP4 E00EA0 0 +OP4 E00EA1 0 +OP4 E00EA2 0 +OP4 E00EA3 0 +OP4 E00EA4 0 +OP4 E00EA5 0 +OP4 E00EA6 0 +OP4 E00EA7 0 +OP4 E00EA8 0 +OP4 E00EA9 0 +OP4 E00EAA 0 +OP4 E00EAB 0 +OP4 E00EAC 0 +OP4 E00EAD 0 +OP4 E00EAE 0 +OP4 E00EAF 0 +OP4 E00EB0 0 +OP4 E00EB1 0 +OP4 E00EB2 0 +OP4 E00EB3 0 +OP4 E00EB4 0 +OP4 E00EB5 0 +OP4 E00EB6 0 +OP4 E00EB7 0 +OP4 E00EB8 0 +OP4 E00EB9 0 +OP4 E00EBA 0 +OP4 E00EBB 0 +OP4 E00EBC 0 +OP4 E00EBD 0 +OP4 E00EBE 0 +OP4 E00EBF 0 +OP4 E00EC0 0 +OP4 E00EC1 0 +OP4 E00EC2 0 +OP4 E00EC3 0 +OP4 E00EC4 0 +OP4 E00EC5 0 +OP4 E00EC6 0 +OP4 E00EC7 0 +OP4 E00EC8 0 +OP4 E00EC9 0 +OP4 E00ECA 0 +OP4 E00ECB 0 +OP4 E00ECC 0 +OP4 E00ECD 0 +OP4 E00ECE 0 +OP4 E00ECF 0 +OP4 E00ED0 0 +OP4 E00ED1 0 +OP4 E00ED2 0 +OP4 E00ED3 0 +OP4 E00ED4 0 +OP4 E00ED5 0 +OP4 E00ED6 0 +OP4 E00ED7 0 +OP4 E00ED8 0 +OP4 E00ED9 0 +OP4 E00EDA 0 +OP4 E00EDB 0 +OP4 E00EDC 0 +OP4 E00EDD 0 +OP4 E00EDE 0 +OP4 E00EDF 0 +OP4 E00EE0 0 +OP4 E00EE1 0 +OP4 E00EE2 0 +OP4 E00EE3 0 +OP4 E00EE4 0 +OP4 E00EE5 0 +OP4 E00EE6 0 +OP4 E00EE7 0 +OP4 E00EE8 0 +OP4 E00EE9 0 +OP4 E00EEA 0 +OP4 E00EEB 0 +OP4 E00EEC 0 +OP4 E00EED 0 +OP4 E00EEE 0 +OP4 E00EEF 0 +OP4 E00EF0 0 +OP4 E00EF1 0 +OP4 E00EF2 0 +OP4 E00EF3 0 +OP4 E00EF4 0 +OP4 E00EF5 0 +OP4 E00EF6 0 +OP4 E00EF7 0 +OP4 E00EF8 0 +OP4 E00EF9 0 +OP4 E00EFA 0 +OP4 E00EFB 0 +OP4 E00EFC 0 +OP4 E00EFD 0 +OP4 E00EFE 0 +OP4 E00EFF 0 +OP4 E00F00 0 +OP4 E00F01 0 +OP4 E00F02 0 +OP4 E00F03 0 +OP4 E00F04 0 +OP4 E00F05 0 +OP4 E00F06 0 +OP4 E00F07 0 +OP4 E00F08 0 +OP4 E00F09 0 +OP4 E00F0A 0 +OP4 E00F0B 0 +OP4 E00F0C 0 +OP4 E00F0D 0 +OP4 E00F0E 0 +OP4 E00F0F 0 +OP4 E00F10 0 +OP4 E00F11 0 +OP4 E00F12 0 +OP4 E00F13 0 +OP4 E00F14 0 +OP4 E00F15 0 +OP4 E00F16 0 +OP4 E00F17 0 +OP4 E00F18 0 +OP4 E00F19 0 +OP4 E00F1A 0 +OP4 E00F1B 0 +OP4 E00F1C 0 +OP4 E00F1D 0 +OP4 E00F1E 0 +OP4 E00F1F 0 +OP4 E00F20 0 +OP4 E00F21 0 +OP4 E00F22 0 +OP4 E00F23 0 +OP4 E00F24 0 +OP4 E00F25 0 +OP4 E00F26 0 +OP4 E00F27 0 +OP4 E00F28 0 +OP4 E00F29 0 +OP4 E00F2A 0 +OP4 E00F2B 0 +OP4 E00F2C 0 +OP4 E00F2D 0 +OP4 E00F2E 0 +OP4 E00F2F 0 +OP4 E00F30 0 diff --git a/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum3_itrace_irisc2.cfg.ext b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum3_itrace_irisc2.cfg.ext new file mode 100644 index 000000000000..6133ffb67640 --- /dev/null +++ b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum3_itrace_irisc2.cfg.ext @@ -0,0 +1,3890 @@ +OP1 Spectrum3 +OP4 ITRACE0 0 +OP4 ITRACE1 0 +OP4 ITRACE2 1 +OP4 ITRACE3 0 +OP4 ITRACE4 0 +OP4 ITRACE5 0 +OP4 ITRACE6 0 +OP4 ITRACE7 0 +OP4 ITRACE8 0 +OP4 ITRACE9 0 +OP4 Main_PhyUC 0 +OP4 TILE0_ITRACE0 0 +OP4 TILE0_ITRACE1 0 +OP4 TILE0_ITRACE2 0 +OP4 TILE0_ITRACE3 0 +OP4 TILE0_ITRACE4 0 +OP4 TILE0_PhyUC 0 +OP4 TILE1_ITRACE0 0 +OP4 TILE1_ITRACE1 0 +OP4 TILE1_ITRACE2 0 +OP4 TILE1_ITRACE3 0 +OP4 TILE1_ITRACE4 0 +OP4 TILE1_PhyUC 0 +OP4 TILE2_ITRACE0 0 +OP4 TILE2_ITRACE1 0 +OP4 TILE2_ITRACE2 0 +OP4 TILE2_ITRACE3 0 +OP4 TILE2_ITRACE4 0 +OP4 TILE2_PhyUC 0 +OP4 TILE3_ITRACE0 0 +OP4 TILE3_ITRACE1 0 +OP4 TILE3_ITRACE2 0 +OP4 TILE3_ITRACE3 0 +OP4 TILE3_ITRACE4 0 +OP4 TILE3_PhyUC 0 +OP4 TILE4_ITRACE0 0 +OP4 TILE4_ITRACE1 0 +OP4 TILE4_ITRACE2 0 +OP4 TILE4_ITRACE3 0 +OP4 TILE4_ITRACE4 0 +OP4 TILE4_PhyUC 0 +OP4 TILE5_ITRACE0 0 +OP4 TILE5_ITRACE1 0 +OP4 TILE5_ITRACE2 0 +OP4 TILE5_ITRACE3 0 +OP4 TILE5_ITRACE4 0 +OP4 TILE5_PhyUC 0 +OP4 TILE6_ITRACE0 0 +OP4 TILE6_ITRACE1 0 +OP4 TILE6_ITRACE2 0 +OP4 TILE6_ITRACE3 0 +OP4 TILE6_ITRACE4 0 +OP4 TILE6_PhyUC 0 +OP4 TILE7_ITRACE0 0 +OP4 TILE7_ITRACE1 0 +OP4 TILE7_ITRACE2 0 +OP4 TILE7_ITRACE3 0 +OP4 TILE7_ITRACE4 0 +OP4 TILE7_PhyUC 0 +OP4 E0003B 0 +OP4 E0003C 0 +OP4 E0003D 0 +OP4 E0003E 0 +OP4 E0003F 0 +OP4 E00040 0 +OP4 E00041 0 +OP4 E00042 0 +OP4 E00043 0 +OP4 E00044 0 +OP4 E00045 0 +OP4 E00046 0 +OP4 E00047 0 +OP4 E00048 0 +OP4 E00049 0 +OP4 E0004A 0 +OP4 E0004B 0 +OP4 E0004C 0 +OP4 E0004D 0 +OP4 E0004E 0 +OP4 E0004F 0 +OP4 E00050 0 +OP4 E00051 0 +OP4 E00052 0 +OP4 E00053 0 +OP4 E00054 0 +OP4 E00055 0 +OP4 E00056 0 +OP4 E00057 0 +OP4 E00058 0 +OP4 E00059 0 +OP4 E0005A 0 +OP4 E0005B 0 +OP4 E0005C 0 +OP4 E0005D 0 +OP4 E0005E 0 +OP4 E0005F 0 +OP4 E00060 0 +OP4 E00061 0 +OP4 E00062 0 +OP4 E00063 0 +OP4 E00064 0 +OP4 E00065 0 +OP4 E00066 0 +OP4 E00067 0 +OP4 E00068 0 +OP4 E00069 0 +OP4 E0006A 0 +OP4 E0006B 0 +OP4 E0006C 0 +OP4 E0006D 0 +OP4 E0006E 0 +OP4 E0006F 0 +OP4 E00070 0 +OP4 E00071 0 +OP4 E00072 0 +OP4 E00073 0 +OP4 E00074 0 +OP4 E00075 0 +OP4 E00076 0 +OP4 E00077 0 +OP4 E00078 0 +OP4 E00079 0 +OP4 E0007A 0 +OP4 E0007B 0 +OP4 E0007C 0 +OP4 E0007D 0 +OP4 E0007E 0 +OP4 E0007F 0 +OP4 E00080 0 +OP4 E00081 0 +OP4 E00082 0 +OP4 E00083 0 +OP4 E00084 0 +OP4 E00085 0 +OP4 E00086 0 +OP4 E00087 0 +OP4 E00088 0 +OP4 E00089 0 +OP4 E0008A 0 +OP4 E0008B 0 +OP4 E0008C 0 +OP4 E0008D 0 +OP4 E0008E 0 +OP4 E0008F 0 +OP4 E00090 0 +OP4 E00091 0 +OP4 E00092 0 +OP4 E00093 0 +OP4 E00094 0 +OP4 E00095 0 +OP4 E00096 0 +OP4 E00097 0 +OP4 E00098 0 +OP4 E00099 0 +OP4 E0009A 0 +OP4 E0009B 0 +OP4 E0009C 0 +OP4 E0009D 0 +OP4 E0009E 0 +OP4 E0009F 0 +OP4 E000A0 0 +OP4 E000A1 0 +OP4 E000A2 0 +OP4 E000A3 0 +OP4 E000A4 0 +OP4 E000A5 0 +OP4 E000A6 0 +OP4 E000A7 0 +OP4 E000A8 0 +OP4 E000A9 0 +OP4 E000AA 0 +OP4 E000AB 0 +OP4 E000AC 0 +OP4 E000AD 0 +OP4 E000AE 0 +OP4 E000AF 0 +OP4 E000B0 0 +OP4 E000B1 0 +OP4 E000B2 0 +OP4 E000B3 0 +OP4 E000B4 0 +OP4 E000B5 0 +OP4 E000B6 0 +OP4 E000B7 0 +OP4 E000B8 0 +OP4 E000B9 0 +OP4 E000BA 0 +OP4 E000BB 0 +OP4 E000BC 0 +OP4 E000BD 0 +OP4 E000BE 0 +OP4 E000BF 0 +OP4 E000C0 0 +OP4 E000C1 0 +OP4 E000C2 0 +OP4 E000C3 0 +OP4 E000C4 0 +OP4 E000C5 0 +OP4 E000C6 0 +OP4 E000C7 0 +OP4 E000C8 0 +OP4 E000C9 0 +OP4 E000CA 0 +OP4 E000CB 0 +OP4 E000CC 0 +OP4 E000CD 0 +OP4 E000CE 0 +OP4 E000CF 0 +OP4 E000D0 0 +OP4 E000D1 0 +OP4 E000D2 0 +OP4 E000D3 0 +OP4 E000D4 0 +OP4 E000D5 0 +OP4 E000D6 0 +OP4 E000D7 0 +OP4 E000D8 0 +OP4 E000D9 0 +OP4 E000DA 0 +OP4 E000DB 0 +OP4 E000DC 0 +OP4 E000DD 0 +OP4 E000DE 0 +OP4 E000DF 0 +OP4 E000E0 0 +OP4 E000E1 0 +OP4 E000E2 0 +OP4 E000E3 0 +OP4 E000E4 0 +OP4 E000E5 0 +OP4 E000E6 0 +OP4 E000E7 0 +OP4 E000E8 0 +OP4 E000E9 0 +OP4 E000EA 0 +OP4 E000EB 0 +OP4 E000EC 0 +OP4 E000ED 0 +OP4 E000EE 0 +OP4 E000EF 0 +OP4 E000F0 0 +OP4 E000F1 0 +OP4 E000F2 0 +OP4 E000F3 0 +OP4 E000F4 0 +OP4 E000F5 0 +OP4 E000F6 0 +OP4 E000F7 0 +OP4 E000F8 0 +OP4 E000F9 0 +OP4 E000FA 0 +OP4 E000FB 0 +OP4 E000FC 0 +OP4 E000FD 0 +OP4 E000FE 0 +OP4 E000FF 0 +OP4 E00100 0 +OP4 E00101 0 +OP4 E00102 0 +OP4 E00103 0 +OP4 E00104 0 +OP4 E00105 0 +OP4 E00106 0 +OP4 E00107 0 +OP4 E00108 0 +OP4 E00109 0 +OP4 E0010A 0 +OP4 E0010B 0 +OP4 E0010C 0 +OP4 E0010D 0 +OP4 E0010E 0 +OP4 E0010F 0 +OP4 E00110 0 +OP4 E00111 0 +OP4 E00112 0 +OP4 E00113 0 +OP4 E00114 0 +OP4 E00115 0 +OP4 E00116 0 +OP4 E00117 0 +OP4 E00118 0 +OP4 E00119 0 +OP4 E0011A 0 +OP4 E0011B 0 +OP4 E0011C 0 +OP4 E0011D 0 +OP4 E0011E 0 +OP4 E0011F 0 +OP4 E00120 0 +OP4 E00121 0 +OP4 E00122 0 +OP4 E00123 0 +OP4 E00124 0 +OP4 E00125 0 +OP4 E00126 0 +OP4 E00127 0 +OP4 E00128 0 +OP4 E00129 0 +OP4 E0012A 0 +OP4 E0012B 0 +OP4 E0012C 0 +OP4 E0012D 0 +OP4 E0012E 0 +OP4 E0012F 0 +OP4 E00130 0 +OP4 E00131 0 +OP4 E00132 0 +OP4 E00133 0 +OP4 E00134 0 +OP4 E00135 0 +OP4 E00136 0 +OP4 E00137 0 +OP4 E00138 0 +OP4 E00139 0 +OP4 E0013A 0 +OP4 E0013B 0 +OP4 E0013C 0 +OP4 E0013D 0 +OP4 E0013E 0 +OP4 E0013F 0 +OP4 E00140 0 +OP4 E00141 0 +OP4 E00142 0 +OP4 E00143 0 +OP4 E00144 0 +OP4 E00145 0 +OP4 E00146 0 +OP4 E00147 0 +OP4 E00148 0 +OP4 E00149 0 +OP4 E0014A 0 +OP4 E0014B 0 +OP4 E0014C 0 +OP4 E0014D 0 +OP4 E0014E 0 +OP4 E0014F 0 +OP4 E00150 0 +OP4 E00151 0 +OP4 E00152 0 +OP4 E00153 0 +OP4 E00154 0 +OP4 E00155 0 +OP4 E00156 0 +OP4 E00157 0 +OP4 E00158 0 +OP4 E00159 0 +OP4 E0015A 0 +OP4 E0015B 0 +OP4 E0015C 0 +OP4 E0015D 0 +OP4 E0015E 0 +OP4 E0015F 0 +OP4 E00160 0 +OP4 E00161 0 +OP4 E00162 0 +OP4 E00163 0 +OP4 E00164 0 +OP4 E00165 0 +OP4 E00166 0 +OP4 E00167 0 +OP4 E00168 0 +OP4 E00169 0 +OP4 E0016A 0 +OP4 E0016B 0 +OP4 E0016C 0 +OP4 E0016D 0 +OP4 E0016E 0 +OP4 E0016F 0 +OP4 E00170 0 +OP4 E00171 0 +OP4 E00172 0 +OP4 E00173 0 +OP4 E00174 0 +OP4 E00175 0 +OP4 E00176 0 +OP4 E00177 0 +OP4 E00178 0 +OP4 E00179 0 +OP4 E0017A 0 +OP4 E0017B 0 +OP4 E0017C 0 +OP4 E0017D 0 +OP4 E0017E 0 +OP4 E0017F 0 +OP4 E00180 0 +OP4 E00181 0 +OP4 E00182 0 +OP4 E00183 0 +OP4 E00184 0 +OP4 E00185 0 +OP4 E00186 0 +OP4 E00187 0 +OP4 E00188 0 +OP4 E00189 0 +OP4 E0018A 0 +OP4 E0018B 0 +OP4 E0018C 0 +OP4 E0018D 0 +OP4 E0018E 0 +OP4 E0018F 0 +OP4 E00190 0 +OP4 E00191 0 +OP4 E00192 0 +OP4 E00193 0 +OP4 E00194 0 +OP4 E00195 0 +OP4 E00196 0 +OP4 E00197 0 +OP4 E00198 0 +OP4 E00199 0 +OP4 E0019A 0 +OP4 E0019B 0 +OP4 E0019C 0 +OP4 E0019D 0 +OP4 E0019E 0 +OP4 E0019F 0 +OP4 E001A0 0 +OP4 E001A1 0 +OP4 E001A2 0 +OP4 E001A3 0 +OP4 E001A4 0 +OP4 E001A5 0 +OP4 E001A6 0 +OP4 E001A7 0 +OP4 E001A8 0 +OP4 E001A9 0 +OP4 E001AA 0 +OP4 E001AB 0 +OP4 E001AC 0 +OP4 E001AD 0 +OP4 E001AE 0 +OP4 E001AF 0 +OP4 E001B0 0 +OP4 E001B1 0 +OP4 E001B2 0 +OP4 E001B3 0 +OP4 E001B4 0 +OP4 E001B5 0 +OP4 E001B6 0 +OP4 E001B7 0 +OP4 E001B8 0 +OP4 E001B9 0 +OP4 E001BA 0 +OP4 E001BB 0 +OP4 E001BC 0 +OP4 E001BD 0 +OP4 E001BE 0 +OP4 E001BF 0 +OP4 E001C0 0 +OP4 E001C1 0 +OP4 E001C2 0 +OP4 E001C3 0 +OP4 E001C4 0 +OP4 E001C5 0 +OP4 E001C6 0 +OP4 E001C7 0 +OP4 E001C8 0 +OP4 E001C9 0 +OP4 E001CA 0 +OP4 E001CB 0 +OP4 E001CC 0 +OP4 E001CD 0 +OP4 E001CE 0 +OP4 E001CF 0 +OP4 E001D0 0 +OP4 E001D1 0 +OP4 E001D2 0 +OP4 E001D3 0 +OP4 E001D4 0 +OP4 E001D5 0 +OP4 E001D6 0 +OP4 E001D7 0 +OP4 E001D8 0 +OP4 E001D9 0 +OP4 E001DA 0 +OP4 E001DB 0 +OP4 E001DC 0 +OP4 E001DD 0 +OP4 E001DE 0 +OP4 E001DF 0 +OP4 E001E0 0 +OP4 E001E1 0 +OP4 E001E2 0 +OP4 E001E3 0 +OP4 E001E4 0 +OP4 E001E5 0 +OP4 E001E6 0 +OP4 E001E7 0 +OP4 E001E8 0 +OP4 E001E9 0 +OP4 E001EA 0 +OP4 E001EB 0 +OP4 E001EC 0 +OP4 E001ED 0 +OP4 E001EE 0 +OP4 E001EF 0 +OP4 E001F0 0 +OP4 E001F1 0 +OP4 E001F2 0 +OP4 E001F3 0 +OP4 E001F4 0 +OP4 E001F5 0 +OP4 E001F6 0 +OP4 E001F7 0 +OP4 E001F8 0 +OP4 E001F9 0 +OP4 E001FA 0 +OP4 E001FB 0 +OP4 E001FC 0 +OP4 E001FD 0 +OP4 E001FE 0 +OP4 E001FF 0 +OP4 E00200 0 +OP4 E00201 0 +OP4 E00202 0 +OP4 E00203 0 +OP4 E00204 0 +OP4 E00205 0 +OP4 E00206 0 +OP4 E00207 0 +OP4 E00208 0 +OP4 E00209 0 +OP4 E0020A 0 +OP4 E0020B 0 +OP4 E0020C 0 +OP4 E0020D 0 +OP4 E0020E 0 +OP4 E0020F 0 +OP4 E00210 0 +OP4 E00211 0 +OP4 E00212 0 +OP4 E00213 0 +OP4 E00214 0 +OP4 E00215 0 +OP4 E00216 0 +OP4 E00217 0 +OP4 E00218 0 +OP4 E00219 0 +OP4 E0021A 0 +OP4 E0021B 0 +OP4 E0021C 0 +OP4 E0021D 0 +OP4 E0021E 0 +OP4 E0021F 0 +OP4 E00220 0 +OP4 E00221 0 +OP4 E00222 0 +OP4 E00223 0 +OP4 E00224 0 +OP4 E00225 0 +OP4 E00226 0 +OP4 E00227 0 +OP4 E00228 0 +OP4 E00229 0 +OP4 E0022A 0 +OP4 E0022B 0 +OP4 E0022C 0 +OP4 E0022D 0 +OP4 E0022E 0 +OP4 E0022F 0 +OP4 E00230 0 +OP4 E00231 0 +OP4 E00232 0 +OP4 E00233 0 +OP4 E00234 0 +OP4 E00235 0 +OP4 E00236 0 +OP4 E00237 0 +OP4 E00238 0 +OP4 E00239 0 +OP4 E0023A 0 +OP4 E0023B 0 +OP4 E0023C 0 +OP4 E0023D 0 +OP4 E0023E 0 +OP4 E0023F 0 +OP4 E00240 0 +OP4 E00241 0 +OP4 E00242 0 +OP4 E00243 0 +OP4 E00244 0 +OP4 E00245 0 +OP4 E00246 0 +OP4 E00247 0 +OP4 E00248 0 +OP4 E00249 0 +OP4 E0024A 0 +OP4 E0024B 0 +OP4 E0024C 0 +OP4 E0024D 0 +OP4 E0024E 0 +OP4 E0024F 0 +OP4 E00250 0 +OP4 E00251 0 +OP4 E00252 0 +OP4 E00253 0 +OP4 E00254 0 +OP4 E00255 0 +OP4 E00256 0 +OP4 E00257 0 +OP4 E00258 0 +OP4 E00259 0 +OP4 E0025A 0 +OP4 E0025B 0 +OP4 E0025C 0 +OP4 E0025D 0 +OP4 E0025E 0 +OP4 E0025F 0 +OP4 E00260 0 +OP4 E00261 0 +OP4 E00262 0 +OP4 E00263 0 +OP4 E00264 0 +OP4 E00265 0 +OP4 E00266 0 +OP4 E00267 0 +OP4 E00268 0 +OP4 E00269 0 +OP4 E0026A 0 +OP4 E0026B 0 +OP4 E0026C 0 +OP4 E0026D 0 +OP4 E0026E 0 +OP4 E0026F 0 +OP4 E00270 0 +OP4 E00271 0 +OP4 E00272 0 +OP4 E00273 0 +OP4 E00274 0 +OP4 E00275 0 +OP4 E00276 0 +OP4 E00277 0 +OP4 E00278 0 +OP4 E00279 0 +OP4 E0027A 0 +OP4 E0027B 0 +OP4 E0027C 0 +OP4 E0027D 0 +OP4 E0027E 0 +OP4 E0027F 0 +OP4 E00280 0 +OP4 E00281 0 +OP4 E00282 0 +OP4 E00283 0 +OP4 E00284 0 +OP4 E00285 0 +OP4 E00286 0 +OP4 E00287 0 +OP4 E00288 0 +OP4 E00289 0 +OP4 E0028A 0 +OP4 E0028B 0 +OP4 E0028C 0 +OP4 E0028D 0 +OP4 E0028E 0 +OP4 E0028F 0 +OP4 E00290 0 +OP4 E00291 0 +OP4 E00292 0 +OP4 E00293 0 +OP4 E00294 0 +OP4 E00295 0 +OP4 E00296 0 +OP4 E00297 0 +OP4 E00298 0 +OP4 E00299 0 +OP4 E0029A 0 +OP4 E0029B 0 +OP4 E0029C 0 +OP4 E0029D 0 +OP4 E0029E 0 +OP4 E0029F 0 +OP4 E002A0 0 +OP4 E002A1 0 +OP4 E002A2 0 +OP4 E002A3 0 +OP4 E002A4 0 +OP4 E002A5 0 +OP4 E002A6 0 +OP4 E002A7 0 +OP4 E002A8 0 +OP4 E002A9 0 +OP4 E002AA 0 +OP4 E002AB 0 +OP4 E002AC 0 +OP4 E002AD 0 +OP4 E002AE 0 +OP4 E002AF 0 +OP4 E002B0 0 +OP4 E002B1 0 +OP4 E002B2 0 +OP4 E002B3 0 +OP4 E002B4 0 +OP4 E002B5 0 +OP4 E002B6 0 +OP4 E002B7 0 +OP4 E002B8 0 +OP4 E002B9 0 +OP4 E002BA 0 +OP4 E002BB 0 +OP4 E002BC 0 +OP4 E002BD 0 +OP4 E002BE 0 +OP4 E002BF 0 +OP4 E002C0 0 +OP4 E002C1 0 +OP4 E002C2 0 +OP4 E002C3 0 +OP4 E002C4 0 +OP4 E002C5 0 +OP4 E002C6 0 +OP4 E002C7 0 +OP4 E002C8 0 +OP4 E002C9 0 +OP4 E002CA 0 +OP4 E002CB 0 +OP4 E002CC 0 +OP4 E002CD 0 +OP4 E002CE 0 +OP4 E002CF 0 +OP4 E002D0 0 +OP4 E002D1 0 +OP4 E002D2 0 +OP4 E002D3 0 +OP4 E002D4 0 +OP4 E002D5 0 +OP4 E002D6 0 +OP4 E002D7 0 +OP4 E002D8 0 +OP4 E002D9 0 +OP4 E002DA 0 +OP4 E002DB 0 +OP4 E002DC 0 +OP4 E002DD 0 +OP4 E002DE 0 +OP4 E002DF 0 +OP4 E002E0 0 +OP4 E002E1 0 +OP4 E002E2 0 +OP4 E002E3 0 +OP4 E002E4 0 +OP4 E002E5 0 +OP4 E002E6 0 +OP4 E002E7 0 +OP4 E002E8 0 +OP4 E002E9 0 +OP4 E002EA 0 +OP4 E002EB 0 +OP4 E002EC 0 +OP4 E002ED 0 +OP4 E002EE 0 +OP4 E002EF 0 +OP4 E002F0 0 +OP4 E002F1 0 +OP4 E002F2 0 +OP4 E002F3 0 +OP4 E002F4 0 +OP4 E002F5 0 +OP4 E002F6 0 +OP4 E002F7 0 +OP4 E002F8 0 +OP4 E002F9 0 +OP4 E002FA 0 +OP4 E002FB 0 +OP4 E002FC 0 +OP4 E002FD 0 +OP4 E002FE 0 +OP4 E002FF 0 +OP4 E00300 0 +OP4 E00301 0 +OP4 E00302 0 +OP4 E00303 0 +OP4 E00304 0 +OP4 E00305 0 +OP4 E00306 0 +OP4 E00307 0 +OP4 E00308 0 +OP4 E00309 0 +OP4 E0030A 0 +OP4 E0030B 0 +OP4 E0030C 0 +OP4 E0030D 0 +OP4 E0030E 0 +OP4 E0030F 0 +OP4 E00310 0 +OP4 E00311 0 +OP4 E00312 0 +OP4 E00313 0 +OP4 E00314 0 +OP4 E00315 0 +OP4 E00316 0 +OP4 E00317 0 +OP4 E00318 0 +OP4 E00319 0 +OP4 E0031A 0 +OP4 E0031B 0 +OP4 E0031C 0 +OP4 E0031D 0 +OP4 E0031E 0 +OP4 E0031F 0 +OP4 E00320 0 +OP4 E00321 0 +OP4 E00322 0 +OP4 E00323 0 +OP4 E00324 0 +OP4 E00325 0 +OP4 E00326 0 +OP4 E00327 0 +OP4 E00328 0 +OP4 E00329 0 +OP4 E0032A 0 +OP4 E0032B 0 +OP4 E0032C 0 +OP4 E0032D 0 +OP4 E0032E 0 +OP4 E0032F 0 +OP4 E00330 0 +OP4 E00331 0 +OP4 E00332 0 +OP4 E00333 0 +OP4 E00334 0 +OP4 E00335 0 +OP4 E00336 0 +OP4 E00337 0 +OP4 E00338 0 +OP4 E00339 0 +OP4 E0033A 0 +OP4 E0033B 0 +OP4 E0033C 0 +OP4 E0033D 0 +OP4 E0033E 0 +OP4 E0033F 0 +OP4 E00340 0 +OP4 E00341 0 +OP4 E00342 0 +OP4 E00343 0 +OP4 E00344 0 +OP4 E00345 0 +OP4 E00346 0 +OP4 E00347 0 +OP4 E00348 0 +OP4 E00349 0 +OP4 E0034A 0 +OP4 E0034B 0 +OP4 E0034C 0 +OP4 E0034D 0 +OP4 E0034E 0 +OP4 E0034F 0 +OP4 E00350 0 +OP4 E00351 0 +OP4 E00352 0 +OP4 E00353 0 +OP4 E00354 0 +OP4 E00355 0 +OP4 E00356 0 +OP4 E00357 0 +OP4 E00358 0 +OP4 E00359 0 +OP4 E0035A 0 +OP4 E0035B 0 +OP4 E0035C 0 +OP4 E0035D 0 +OP4 E0035E 0 +OP4 E0035F 0 +OP4 E00360 0 +OP4 E00361 0 +OP4 E00362 0 +OP4 E00363 0 +OP4 E00364 0 +OP4 E00365 0 +OP4 E00366 0 +OP4 E00367 0 +OP4 E00368 0 +OP4 E00369 0 +OP4 E0036A 0 +OP4 E0036B 0 +OP4 E0036C 0 +OP4 E0036D 0 +OP4 E0036E 0 +OP4 E0036F 0 +OP4 E00370 0 +OP4 E00371 0 +OP4 E00372 0 +OP4 E00373 0 +OP4 E00374 0 +OP4 E00375 0 +OP4 E00376 0 +OP4 E00377 0 +OP4 E00378 0 +OP4 E00379 0 +OP4 E0037A 0 +OP4 E0037B 0 +OP4 E0037C 0 +OP4 E0037D 0 +OP4 E0037E 0 +OP4 E0037F 0 +OP4 E00380 0 +OP4 E00381 0 +OP4 E00382 0 +OP4 E00383 0 +OP4 E00384 0 +OP4 E00385 0 +OP4 E00386 0 +OP4 E00387 0 +OP4 E00388 0 +OP4 E00389 0 +OP4 E0038A 0 +OP4 E0038B 0 +OP4 E0038C 0 +OP4 E0038D 0 +OP4 E0038E 0 +OP4 E0038F 0 +OP4 E00390 0 +OP4 E00391 0 +OP4 E00392 0 +OP4 E00393 0 +OP4 E00394 0 +OP4 E00395 0 +OP4 E00396 0 +OP4 E00397 0 +OP4 E00398 0 +OP4 E00399 0 +OP4 E0039A 0 +OP4 E0039B 0 +OP4 E0039C 0 +OP4 E0039D 0 +OP4 E0039E 0 +OP4 E0039F 0 +OP4 E003A0 0 +OP4 E003A1 0 +OP4 E003A2 0 +OP4 E003A3 0 +OP4 E003A4 0 +OP4 E003A5 0 +OP4 E003A6 0 +OP4 E003A7 0 +OP4 E003A8 0 +OP4 E003A9 0 +OP4 E003AA 0 +OP4 E003AB 0 +OP4 E003AC 0 +OP4 E003AD 0 +OP4 E003AE 0 +OP4 E003AF 0 +OP4 E003B0 0 +OP4 E003B1 0 +OP4 E003B2 0 +OP4 E003B3 0 +OP4 E003B4 0 +OP4 E003B5 0 +OP4 E003B6 0 +OP4 E003B7 0 +OP4 E003B8 0 +OP4 E003B9 0 +OP4 E003BA 0 +OP4 E003BB 0 +OP4 E003BC 0 +OP4 E003BD 0 +OP4 E003BE 0 +OP4 E003BF 0 +OP4 E003C0 0 +OP4 E003C1 0 +OP4 E003C2 0 +OP4 E003C3 0 +OP4 E003C4 0 +OP4 E003C5 0 +OP4 E003C6 0 +OP4 E003C7 0 +OP4 E003C8 0 +OP4 E003C9 0 +OP4 E003CA 0 +OP4 E003CB 0 +OP4 E003CC 0 +OP4 E003CD 0 +OP4 E003CE 0 +OP4 E003CF 0 +OP4 E003D0 0 +OP4 E003D1 0 +OP4 E003D2 0 +OP4 E003D3 0 +OP4 E003D4 0 +OP4 E003D5 0 +OP4 E003D6 0 +OP4 E003D7 0 +OP4 E003D8 0 +OP4 E003D9 0 +OP4 E003DA 0 +OP4 E003DB 0 +OP4 E003DC 0 +OP4 E003DD 0 +OP4 E003DE 0 +OP4 E003DF 0 +OP4 E003E0 0 +OP4 E003E1 0 +OP4 E003E2 0 +OP4 E003E3 0 +OP4 E003E4 0 +OP4 E003E5 0 +OP4 E003E6 0 +OP4 E003E7 0 +OP4 E003E8 0 +OP4 E003E9 0 +OP4 E003EA 0 +OP4 E003EB 0 +OP4 E003EC 0 +OP4 E003ED 0 +OP4 E003EE 0 +OP4 E003EF 0 +OP4 E003F0 0 +OP4 E003F1 0 +OP4 E003F2 0 +OP4 E003F3 0 +OP4 E003F4 0 +OP4 E003F5 0 +OP4 E003F6 0 +OP4 E003F7 0 +OP4 E003F8 0 +OP4 E003F9 0 +OP4 E003FA 0 +OP4 E003FB 0 +OP4 E003FC 0 +OP4 E003FD 0 +OP4 E003FE 0 +OP4 E003FF 0 +OP4 E00400 0 +OP4 E00401 0 +OP4 E00402 0 +OP4 E00403 0 +OP4 E00404 0 +OP4 E00405 0 +OP4 E00406 0 +OP4 E00407 0 +OP4 E00408 0 +OP4 E00409 0 +OP4 E0040A 0 +OP4 E0040B 0 +OP4 E0040C 0 +OP4 E0040D 0 +OP4 E0040E 0 +OP4 E0040F 0 +OP4 E00410 0 +OP4 E00411 0 +OP4 E00412 0 +OP4 E00413 0 +OP4 E00414 0 +OP4 E00415 0 +OP4 E00416 0 +OP4 E00417 0 +OP4 E00418 0 +OP4 E00419 0 +OP4 E0041A 0 +OP4 E0041B 0 +OP4 E0041C 0 +OP4 E0041D 0 +OP4 E0041E 0 +OP4 E0041F 0 +OP4 E00420 0 +OP4 E00421 0 +OP4 E00422 0 +OP4 E00423 0 +OP4 E00424 0 +OP4 E00425 0 +OP4 E00426 0 +OP4 E00427 0 +OP4 E00428 0 +OP4 E00429 0 +OP4 E0042A 0 +OP4 E0042B 0 +OP4 E0042C 0 +OP4 E0042D 0 +OP4 E0042E 0 +OP4 E0042F 0 +OP4 E00430 0 +OP4 E00431 0 +OP4 E00432 0 +OP4 E00433 0 +OP4 E00434 0 +OP4 E00435 0 +OP4 E00436 0 +OP4 E00437 0 +OP4 E00438 0 +OP4 E00439 0 +OP4 E0043A 0 +OP4 E0043B 0 +OP4 E0043C 0 +OP4 E0043D 0 +OP4 E0043E 0 +OP4 E0043F 0 +OP4 E00440 0 +OP4 E00441 0 +OP4 E00442 0 +OP4 E00443 0 +OP4 E00444 0 +OP4 E00445 0 +OP4 E00446 0 +OP4 E00447 0 +OP4 E00448 0 +OP4 E00449 0 +OP4 E0044A 0 +OP4 E0044B 0 +OP4 E0044C 0 +OP4 E0044D 0 +OP4 E0044E 0 +OP4 E0044F 0 +OP4 E00450 0 +OP4 E00451 0 +OP4 E00452 0 +OP4 E00453 0 +OP4 E00454 0 +OP4 E00455 0 +OP4 E00456 0 +OP4 E00457 0 +OP4 E00458 0 +OP4 E00459 0 +OP4 E0045A 0 +OP4 E0045B 0 +OP4 E0045C 0 +OP4 E0045D 0 +OP4 E0045E 0 +OP4 E0045F 0 +OP4 E00460 0 +OP4 E00461 0 +OP4 E00462 0 +OP4 E00463 0 +OP4 E00464 0 +OP4 E00465 0 +OP4 E00466 0 +OP4 E00467 0 +OP4 E00468 0 +OP4 E00469 0 +OP4 E0046A 0 +OP4 E0046B 0 +OP4 E0046C 0 +OP4 E0046D 0 +OP4 E0046E 0 +OP4 E0046F 0 +OP4 E00470 0 +OP4 E00471 0 +OP4 E00472 0 +OP4 E00473 0 +OP4 E00474 0 +OP4 E00475 0 +OP4 E00476 0 +OP4 E00477 0 +OP4 E00478 0 +OP4 E00479 0 +OP4 E0047A 0 +OP4 E0047B 0 +OP4 E0047C 0 +OP4 E0047D 0 +OP4 E0047E 0 +OP4 E0047F 0 +OP4 E00480 0 +OP4 E00481 0 +OP4 E00482 0 +OP4 E00483 0 +OP4 E00484 0 +OP4 E00485 0 +OP4 E00486 0 +OP4 E00487 0 +OP4 E00488 0 +OP4 E00489 0 +OP4 E0048A 0 +OP4 E0048B 0 +OP4 E0048C 0 +OP4 E0048D 0 +OP4 E0048E 0 +OP4 E0048F 0 +OP4 E00490 0 +OP4 E00491 0 +OP4 E00492 0 +OP4 E00493 0 +OP4 E00494 0 +OP4 E00495 0 +OP4 E00496 0 +OP4 E00497 0 +OP4 E00498 0 +OP4 E00499 0 +OP4 E0049A 0 +OP4 E0049B 0 +OP4 E0049C 0 +OP4 E0049D 0 +OP4 E0049E 0 +OP4 E0049F 0 +OP4 E004A0 0 +OP4 E004A1 0 +OP4 E004A2 0 +OP4 E004A3 0 +OP4 E004A4 0 +OP4 E004A5 0 +OP4 E004A6 0 +OP4 E004A7 0 +OP4 E004A8 0 +OP4 E004A9 0 +OP4 E004AA 0 +OP4 E004AB 0 +OP4 E004AC 0 +OP4 E004AD 0 +OP4 E004AE 0 +OP4 E004AF 0 +OP4 E004B0 0 +OP4 E004B1 0 +OP4 E004B2 0 +OP4 E004B3 0 +OP4 E004B4 0 +OP4 E004B5 0 +OP4 E004B6 0 +OP4 E004B7 0 +OP4 E004B8 0 +OP4 E004B9 0 +OP4 E004BA 0 +OP4 E004BB 0 +OP4 E004BC 0 +OP4 E004BD 0 +OP4 E004BE 0 +OP4 E004BF 0 +OP4 E004C0 0 +OP4 E004C1 0 +OP4 E004C2 0 +OP4 E004C3 0 +OP4 E004C4 0 +OP4 E004C5 0 +OP4 E004C6 0 +OP4 E004C7 0 +OP4 E004C8 0 +OP4 E004C9 0 +OP4 E004CA 0 +OP4 E004CB 0 +OP4 E004CC 0 +OP4 E004CD 0 +OP4 E004CE 0 +OP4 E004CF 0 +OP4 E004D0 0 +OP4 E004D1 0 +OP4 E004D2 0 +OP4 E004D3 0 +OP4 E004D4 0 +OP4 E004D5 0 +OP4 E004D6 0 +OP4 E004D7 0 +OP4 E004D8 0 +OP4 E004D9 0 +OP4 E004DA 0 +OP4 E004DB 0 +OP4 E004DC 0 +OP4 E004DD 0 +OP4 E004DE 0 +OP4 E004DF 0 +OP4 E004E0 0 +OP4 E004E1 0 +OP4 E004E2 0 +OP4 E004E3 0 +OP4 E004E4 0 +OP4 E004E5 0 +OP4 E004E6 0 +OP4 E004E7 0 +OP4 E004E8 0 +OP4 E004E9 0 +OP4 E004EA 0 +OP4 E004EB 0 +OP4 E004EC 0 +OP4 E004ED 0 +OP4 E004EE 0 +OP4 E004EF 0 +OP4 E004F0 0 +OP4 E004F1 0 +OP4 E004F2 0 +OP4 E004F3 0 +OP4 E004F4 0 +OP4 E004F5 0 +OP4 E004F6 0 +OP4 E004F7 0 +OP4 E004F8 0 +OP4 E004F9 0 +OP4 E004FA 0 +OP4 E004FB 0 +OP4 E004FC 0 +OP4 E004FD 0 +OP4 E004FE 0 +OP4 E004FF 0 +OP4 E00500 0 +OP4 E00501 0 +OP4 E00502 0 +OP4 E00503 0 +OP4 E00504 0 +OP4 E00505 0 +OP4 E00506 0 +OP4 E00507 0 +OP4 E00508 0 +OP4 E00509 0 +OP4 E0050A 0 +OP4 E0050B 0 +OP4 E0050C 0 +OP4 E0050D 0 +OP4 E0050E 0 +OP4 E0050F 0 +OP4 E00510 0 +OP4 E00511 0 +OP4 E00512 0 +OP4 E00513 0 +OP4 E00514 0 +OP4 E00515 0 +OP4 E00516 0 +OP4 E00517 0 +OP4 E00518 0 +OP4 E00519 0 +OP4 E0051A 0 +OP4 E0051B 0 +OP4 E0051C 0 +OP4 E0051D 0 +OP4 E0051E 0 +OP4 E0051F 0 +OP4 E00520 0 +OP4 E00521 0 +OP4 E00522 0 +OP4 E00523 0 +OP4 E00524 0 +OP4 E00525 0 +OP4 E00526 0 +OP4 E00527 0 +OP4 E00528 0 +OP4 E00529 0 +OP4 E0052A 0 +OP4 E0052B 0 +OP4 E0052C 0 +OP4 E0052D 0 +OP4 E0052E 0 +OP4 E0052F 0 +OP4 E00530 0 +OP4 E00531 0 +OP4 E00532 0 +OP4 E00533 0 +OP4 E00534 0 +OP4 E00535 0 +OP4 E00536 0 +OP4 E00537 0 +OP4 E00538 0 +OP4 E00539 0 +OP4 E0053A 0 +OP4 E0053B 0 +OP4 E0053C 0 +OP4 E0053D 0 +OP4 E0053E 0 +OP4 E0053F 0 +OP4 E00540 0 +OP4 E00541 0 +OP4 E00542 0 +OP4 E00543 0 +OP4 E00544 0 +OP4 E00545 0 +OP4 E00546 0 +OP4 E00547 0 +OP4 E00548 0 +OP4 E00549 0 +OP4 E0054A 0 +OP4 E0054B 0 +OP4 E0054C 0 +OP4 E0054D 0 +OP4 E0054E 0 +OP4 E0054F 0 +OP4 E00550 0 +OP4 E00551 0 +OP4 E00552 0 +OP4 E00553 0 +OP4 E00554 0 +OP4 E00555 0 +OP4 E00556 0 +OP4 E00557 0 +OP4 E00558 0 +OP4 E00559 0 +OP4 E0055A 0 +OP4 E0055B 0 +OP4 E0055C 0 +OP4 E0055D 0 +OP4 E0055E 0 +OP4 E0055F 0 +OP4 E00560 0 +OP4 E00561 0 +OP4 E00562 0 +OP4 E00563 0 +OP4 E00564 0 +OP4 E00565 0 +OP4 E00566 0 +OP4 E00567 0 +OP4 E00568 0 +OP4 E00569 0 +OP4 E0056A 0 +OP4 E0056B 0 +OP4 E0056C 0 +OP4 E0056D 0 +OP4 E0056E 0 +OP4 E0056F 0 +OP4 E00570 0 +OP4 E00571 0 +OP4 E00572 0 +OP4 E00573 0 +OP4 E00574 0 +OP4 E00575 0 +OP4 E00576 0 +OP4 E00577 0 +OP4 E00578 0 +OP4 E00579 0 +OP4 E0057A 0 +OP4 E0057B 0 +OP4 E0057C 0 +OP4 E0057D 0 +OP4 E0057E 0 +OP4 E0057F 0 +OP4 E00580 0 +OP4 E00581 0 +OP4 E00582 0 +OP4 E00583 0 +OP4 E00584 0 +OP4 E00585 0 +OP4 E00586 0 +OP4 E00587 0 +OP4 E00588 0 +OP4 E00589 0 +OP4 E0058A 0 +OP4 E0058B 0 +OP4 E0058C 0 +OP4 E0058D 0 +OP4 E0058E 0 +OP4 E0058F 0 +OP4 E00590 0 +OP4 E00591 0 +OP4 E00592 0 +OP4 E00593 0 +OP4 E00594 0 +OP4 E00595 0 +OP4 E00596 0 +OP4 E00597 0 +OP4 E00598 0 +OP4 E00599 0 +OP4 E0059A 0 +OP4 E0059B 0 +OP4 E0059C 0 +OP4 E0059D 0 +OP4 E0059E 0 +OP4 E0059F 0 +OP4 E005A0 0 +OP4 E005A1 0 +OP4 E005A2 0 +OP4 E005A3 0 +OP4 E005A4 0 +OP4 E005A5 0 +OP4 E005A6 0 +OP4 E005A7 0 +OP4 E005A8 0 +OP4 E005A9 0 +OP4 E005AA 0 +OP4 E005AB 0 +OP4 E005AC 0 +OP4 E005AD 0 +OP4 E005AE 0 +OP4 E005AF 0 +OP4 E005B0 0 +OP4 E005B1 0 +OP4 E005B2 0 +OP4 E005B3 0 +OP4 E005B4 0 +OP4 E005B5 0 +OP4 E005B6 0 +OP4 E005B7 0 +OP4 E005B8 0 +OP4 E005B9 0 +OP4 E005BA 0 +OP4 E005BB 0 +OP4 E005BC 0 +OP4 E005BD 0 +OP4 E005BE 0 +OP4 E005BF 0 +OP4 E005C0 0 +OP4 E005C1 0 +OP4 E005C2 0 +OP4 E005C3 0 +OP4 E005C4 0 +OP4 E005C5 0 +OP4 E005C6 0 +OP4 E005C7 0 +OP4 E005C8 0 +OP4 E005C9 0 +OP4 E005CA 0 +OP4 E005CB 0 +OP4 E005CC 0 +OP4 E005CD 0 +OP4 E005CE 0 +OP4 E005CF 0 +OP4 E005D0 0 +OP4 E005D1 0 +OP4 E005D2 0 +OP4 E005D3 0 +OP4 E005D4 0 +OP4 E005D5 0 +OP4 E005D6 0 +OP4 E005D7 0 +OP4 E005D8 0 +OP4 E005D9 0 +OP4 E005DA 0 +OP4 E005DB 0 +OP4 E005DC 0 +OP4 E005DD 0 +OP4 E005DE 0 +OP4 E005DF 0 +OP4 E005E0 0 +OP4 E005E1 0 +OP4 E005E2 0 +OP4 E005E3 0 +OP4 E005E4 0 +OP4 E005E5 0 +OP4 E005E6 0 +OP4 E005E7 0 +OP4 E005E8 0 +OP4 E005E9 0 +OP4 E005EA 0 +OP4 E005EB 0 +OP4 E005EC 0 +OP4 E005ED 0 +OP4 E005EE 0 +OP4 E005EF 0 +OP4 E005F0 0 +OP4 E005F1 0 +OP4 E005F2 0 +OP4 E005F3 0 +OP4 E005F4 0 +OP4 E005F5 0 +OP4 E005F6 0 +OP4 E005F7 0 +OP4 E005F8 0 +OP4 E005F9 0 +OP4 E005FA 0 +OP4 E005FB 0 +OP4 E005FC 0 +OP4 E005FD 0 +OP4 E005FE 0 +OP4 E005FF 0 +OP4 E00600 0 +OP4 E00601 0 +OP4 E00602 0 +OP4 E00603 0 +OP4 E00604 0 +OP4 E00605 0 +OP4 E00606 0 +OP4 E00607 0 +OP4 E00608 0 +OP4 E00609 0 +OP4 E0060A 0 +OP4 E0060B 0 +OP4 E0060C 0 +OP4 E0060D 0 +OP4 E0060E 0 +OP4 E0060F 0 +OP4 E00610 0 +OP4 E00611 0 +OP4 E00612 0 +OP4 E00613 0 +OP4 E00614 0 +OP4 E00615 0 +OP4 E00616 0 +OP4 E00617 0 +OP4 E00618 0 +OP4 E00619 0 +OP4 E0061A 0 +OP4 E0061B 0 +OP4 E0061C 0 +OP4 E0061D 0 +OP4 E0061E 0 +OP4 E0061F 0 +OP4 E00620 0 +OP4 E00621 0 +OP4 E00622 0 +OP4 E00623 0 +OP4 E00624 0 +OP4 E00625 0 +OP4 E00626 0 +OP4 E00627 0 +OP4 E00628 0 +OP4 E00629 0 +OP4 E0062A 0 +OP4 E0062B 0 +OP4 E0062C 0 +OP4 E0062D 0 +OP4 E0062E 0 +OP4 E0062F 0 +OP4 E00630 0 +OP4 E00631 0 +OP4 E00632 0 +OP4 E00633 0 +OP4 E00634 0 +OP4 E00635 0 +OP4 E00636 0 +OP4 E00637 0 +OP4 E00638 0 +OP4 E00639 0 +OP4 E0063A 0 +OP4 E0063B 0 +OP4 E0063C 0 +OP4 E0063D 0 +OP4 E0063E 0 +OP4 E0063F 0 +OP4 E00640 0 +OP4 E00641 0 +OP4 E00642 0 +OP4 E00643 0 +OP4 E00644 0 +OP4 E00645 0 +OP4 E00646 0 +OP4 E00647 0 +OP4 E00648 0 +OP4 E00649 0 +OP4 E0064A 0 +OP4 E0064B 0 +OP4 E0064C 0 +OP4 E0064D 0 +OP4 E0064E 0 +OP4 E0064F 0 +OP4 E00650 0 +OP4 E00651 0 +OP4 E00652 0 +OP4 E00653 0 +OP4 E00654 0 +OP4 E00655 0 +OP4 E00656 0 +OP4 E00657 0 +OP4 E00658 0 +OP4 E00659 0 +OP4 E0065A 0 +OP4 E0065B 0 +OP4 E0065C 0 +OP4 E0065D 0 +OP4 E0065E 0 +OP4 E0065F 0 +OP4 E00660 0 +OP4 E00661 0 +OP4 E00662 0 +OP4 E00663 0 +OP4 E00664 0 +OP4 E00665 0 +OP4 E00666 0 +OP4 E00667 0 +OP4 E00668 0 +OP4 E00669 0 +OP4 E0066A 0 +OP4 E0066B 0 +OP4 E0066C 0 +OP4 E0066D 0 +OP4 E0066E 0 +OP4 E0066F 0 +OP4 E00670 0 +OP4 E00671 0 +OP4 E00672 0 +OP4 E00673 0 +OP4 E00674 0 +OP4 E00675 0 +OP4 E00676 0 +OP4 E00677 0 +OP4 E00678 0 +OP4 E00679 0 +OP4 E0067A 0 +OP4 E0067B 0 +OP4 E0067C 0 +OP4 E0067D 0 +OP4 E0067E 0 +OP4 E0067F 0 +OP4 E00680 0 +OP4 E00681 0 +OP4 E00682 0 +OP4 E00683 0 +OP4 E00684 0 +OP4 E00685 0 +OP4 E00686 0 +OP4 E00687 0 +OP4 E00688 0 +OP4 E00689 0 +OP4 E0068A 0 +OP4 E0068B 0 +OP4 E0068C 0 +OP4 E0068D 0 +OP4 E0068E 0 +OP4 E0068F 0 +OP4 E00690 0 +OP4 E00691 0 +OP4 E00692 0 +OP4 E00693 0 +OP4 E00694 0 +OP4 E00695 0 +OP4 E00696 0 +OP4 E00697 0 +OP4 E00698 0 +OP4 E00699 0 +OP4 E0069A 0 +OP4 E0069B 0 +OP4 E0069C 0 +OP4 E0069D 0 +OP4 E0069E 0 +OP4 E0069F 0 +OP4 E006A0 0 +OP4 E006A1 0 +OP4 E006A2 0 +OP4 E006A3 0 +OP4 E006A4 0 +OP4 E006A5 0 +OP4 E006A6 0 +OP4 E006A7 0 +OP4 E006A8 0 +OP4 E006A9 0 +OP4 E006AA 0 +OP4 E006AB 0 +OP4 E006AC 0 +OP4 E006AD 0 +OP4 E006AE 0 +OP4 E006AF 0 +OP4 E006B0 0 +OP4 E006B1 0 +OP4 E006B2 0 +OP4 E006B3 0 +OP4 E006B4 0 +OP4 E006B5 0 +OP4 E006B6 0 +OP4 E006B7 0 +OP4 E006B8 0 +OP4 E006B9 0 +OP4 E006BA 0 +OP4 E006BB 0 +OP4 E006BC 0 +OP4 E006BD 0 +OP4 E006BE 0 +OP4 E006BF 0 +OP4 E006C0 0 +OP4 E006C1 0 +OP4 E006C2 0 +OP4 E006C3 0 +OP4 E006C4 0 +OP4 E006C5 0 +OP4 E006C6 0 +OP4 E006C7 0 +OP4 E006C8 0 +OP4 E006C9 0 +OP4 E006CA 0 +OP4 E006CB 0 +OP4 E006CC 0 +OP4 E006CD 0 +OP4 E006CE 0 +OP4 E006CF 0 +OP4 E006D0 0 +OP4 E006D1 0 +OP4 E006D2 0 +OP4 E006D3 0 +OP4 E006D4 0 +OP4 E006D5 0 +OP4 E006D6 0 +OP4 E006D7 0 +OP4 E006D8 0 +OP4 E006D9 0 +OP4 E006DA 0 +OP4 E006DB 0 +OP4 E006DC 0 +OP4 E006DD 0 +OP4 E006DE 0 +OP4 E006DF 0 +OP4 E006E0 0 +OP4 E006E1 0 +OP4 E006E2 0 +OP4 E006E3 0 +OP4 E006E4 0 +OP4 E006E5 0 +OP4 E006E6 0 +OP4 E006E7 0 +OP4 E006E8 0 +OP4 E006E9 0 +OP4 E006EA 0 +OP4 E006EB 0 +OP4 E006EC 0 +OP4 E006ED 0 +OP4 E006EE 0 +OP4 E006EF 0 +OP4 E006F0 0 +OP4 E006F1 0 +OP4 E006F2 0 +OP4 E006F3 0 +OP4 E006F4 0 +OP4 E006F5 0 +OP4 E006F6 0 +OP4 E006F7 0 +OP4 E006F8 0 +OP4 E006F9 0 +OP4 E006FA 0 +OP4 E006FB 0 +OP4 E006FC 0 +OP4 E006FD 0 +OP4 E006FE 0 +OP4 E006FF 0 +OP4 E00700 0 +OP4 E00701 0 +OP4 E00702 0 +OP4 E00703 0 +OP4 E00704 0 +OP4 E00705 0 +OP4 E00706 0 +OP4 E00707 0 +OP4 E00708 0 +OP4 E00709 0 +OP4 E0070A 0 +OP4 E0070B 0 +OP4 E0070C 0 +OP4 E0070D 0 +OP4 E0070E 0 +OP4 E0070F 0 +OP4 E00710 0 +OP4 E00711 0 +OP4 E00712 0 +OP4 E00713 0 +OP4 E00714 0 +OP4 E00715 0 +OP4 E00716 0 +OP4 E00717 0 +OP4 E00718 0 +OP4 E00719 0 +OP4 E0071A 0 +OP4 E0071B 0 +OP4 E0071C 0 +OP4 E0071D 0 +OP4 E0071E 0 +OP4 E0071F 0 +OP4 E00720 0 +OP4 E00721 0 +OP4 E00722 0 +OP4 E00723 0 +OP4 E00724 0 +OP4 E00725 0 +OP4 E00726 0 +OP4 E00727 0 +OP4 E00728 0 +OP4 E00729 0 +OP4 E0072A 0 +OP4 E0072B 0 +OP4 E0072C 0 +OP4 E0072D 0 +OP4 E0072E 0 +OP4 E0072F 0 +OP4 E00730 0 +OP4 E00731 0 +OP4 E00732 0 +OP4 E00733 0 +OP4 E00734 0 +OP4 E00735 0 +OP4 E00736 0 +OP4 E00737 0 +OP4 E00738 0 +OP4 E00739 0 +OP4 E0073A 0 +OP4 E0073B 0 +OP4 E0073C 0 +OP4 E0073D 0 +OP4 E0073E 0 +OP4 E0073F 0 +OP4 E00740 0 +OP4 E00741 0 +OP4 E00742 0 +OP4 E00743 0 +OP4 E00744 0 +OP4 E00745 0 +OP4 E00746 0 +OP4 E00747 0 +OP4 E00748 0 +OP4 E00749 0 +OP4 E0074A 0 +OP4 E0074B 0 +OP4 E0074C 0 +OP4 E0074D 0 +OP4 E0074E 0 +OP4 E0074F 0 +OP4 E00750 0 +OP4 E00751 0 +OP4 E00752 0 +OP4 E00753 0 +OP4 E00754 0 +OP4 E00755 0 +OP4 E00756 0 +OP4 E00757 0 +OP4 E00758 0 +OP4 E00759 0 +OP4 E0075A 0 +OP4 E0075B 0 +OP4 E0075C 0 +OP4 E0075D 0 +OP4 E0075E 0 +OP4 E0075F 0 +OP4 E00760 0 +OP4 E00761 0 +OP4 E00762 0 +OP4 E00763 0 +OP4 E00764 0 +OP4 E00765 0 +OP4 E00766 0 +OP4 E00767 0 +OP4 E00768 0 +OP4 E00769 0 +OP4 E0076A 0 +OP4 E0076B 0 +OP4 E0076C 0 +OP4 E0076D 0 +OP4 E0076E 0 +OP4 E0076F 0 +OP4 E00770 0 +OP4 E00771 0 +OP4 E00772 0 +OP4 E00773 0 +OP4 E00774 0 +OP4 E00775 0 +OP4 E00776 0 +OP4 E00777 0 +OP4 E00778 0 +OP4 E00779 0 +OP4 E0077A 0 +OP4 E0077B 0 +OP4 E0077C 0 +OP4 E0077D 0 +OP4 E0077E 0 +OP4 E0077F 0 +OP4 E00780 0 +OP4 E00781 0 +OP4 E00782 0 +OP4 E00783 0 +OP4 E00784 0 +OP4 E00785 0 +OP4 E00786 0 +OP4 E00787 0 +OP4 E00788 0 +OP4 E00789 0 +OP4 E0078A 0 +OP4 E0078B 0 +OP4 E0078C 0 +OP4 E0078D 0 +OP4 E0078E 0 +OP4 E0078F 0 +OP4 E00790 0 +OP4 E00791 0 +OP4 E00792 0 +OP4 E00793 0 +OP4 E00794 0 +OP4 E00795 0 +OP4 E00796 0 +OP4 E00797 0 +OP4 E00798 0 +OP4 E00799 0 +OP4 E0079A 0 +OP4 E0079B 0 +OP4 E0079C 0 +OP4 E0079D 0 +OP4 E0079E 0 +OP4 E0079F 0 +OP4 E007A0 0 +OP4 E007A1 0 +OP4 E007A2 0 +OP4 E007A3 0 +OP4 E007A4 0 +OP4 E007A5 0 +OP4 E007A6 0 +OP4 E007A7 0 +OP4 E007A8 0 +OP4 E007A9 0 +OP4 E007AA 0 +OP4 E007AB 0 +OP4 E007AC 0 +OP4 E007AD 0 +OP4 E007AE 0 +OP4 E007AF 0 +OP4 E007B0 0 +OP4 E007B1 0 +OP4 E007B2 0 +OP4 E007B3 0 +OP4 E007B4 0 +OP4 E007B5 0 +OP4 E007B6 0 +OP4 E007B7 0 +OP4 E007B8 0 +OP4 E007B9 0 +OP4 E007BA 0 +OP4 E007BB 0 +OP4 E007BC 0 +OP4 E007BD 0 +OP4 E007BE 0 +OP4 E007BF 0 +OP4 E007C0 0 +OP4 E007C1 0 +OP4 E007C2 0 +OP4 E007C3 0 +OP4 E007C4 0 +OP4 E007C5 0 +OP4 E007C6 0 +OP4 E007C7 0 +OP4 E007C8 0 +OP4 E007C9 0 +OP4 E007CA 0 +OP4 E007CB 0 +OP4 E007CC 0 +OP4 E007CD 0 +OP4 E007CE 0 +OP4 E007CF 0 +OP4 E007D0 0 +OP4 E007D1 0 +OP4 E007D2 0 +OP4 E007D3 0 +OP4 E007D4 0 +OP4 E007D5 0 +OP4 E007D6 0 +OP4 E007D7 0 +OP4 E007D8 0 +OP4 E007D9 0 +OP4 E007DA 0 +OP4 E007DB 0 +OP4 E007DC 0 +OP4 E007DD 0 +OP4 E007DE 0 +OP4 E007DF 0 +OP4 E007E0 0 +OP4 E007E1 0 +OP4 E007E2 0 +OP4 E007E3 0 +OP4 E007E4 0 +OP4 E007E5 0 +OP4 E007E6 0 +OP4 E007E7 0 +OP4 E007E8 0 +OP4 E007E9 0 +OP4 E007EA 0 +OP4 E007EB 0 +OP4 E007EC 0 +OP4 E007ED 0 +OP4 E007EE 0 +OP4 E007EF 0 +OP4 E007F0 0 +OP4 E007F1 0 +OP4 E007F2 0 +OP4 E007F3 0 +OP4 E007F4 0 +OP4 E007F5 0 +OP4 E007F6 0 +OP4 E007F7 0 +OP4 E007F8 0 +OP4 E007F9 0 +OP4 E007FA 0 +OP4 E007FB 0 +OP4 E007FC 0 +OP4 E007FD 0 +OP4 E007FE 0 +OP4 E007FF 0 +OP4 E00800 0 +OP4 E00801 0 +OP4 E00802 0 +OP4 E00803 0 +OP4 E00804 0 +OP4 E00805 0 +OP4 E00806 0 +OP4 E00807 0 +OP4 E00808 0 +OP4 E00809 0 +OP4 E0080A 0 +OP4 E0080B 0 +OP4 E0080C 0 +OP4 E0080D 0 +OP4 E0080E 0 +OP4 E0080F 0 +OP4 E00810 0 +OP4 E00811 0 +OP4 E00812 0 +OP4 E00813 0 +OP4 E00814 0 +OP4 E00815 0 +OP4 E00816 0 +OP4 E00817 0 +OP4 E00818 0 +OP4 E00819 0 +OP4 E0081A 0 +OP4 E0081B 0 +OP4 E0081C 0 +OP4 E0081D 0 +OP4 E0081E 0 +OP4 E0081F 0 +OP4 E00820 0 +OP4 E00821 0 +OP4 E00822 0 +OP4 E00823 0 +OP4 E00824 0 +OP4 E00825 0 +OP4 E00826 0 +OP4 E00827 0 +OP4 E00828 0 +OP4 E00829 0 +OP4 E0082A 0 +OP4 E0082B 0 +OP4 E0082C 0 +OP4 E0082D 0 +OP4 E0082E 0 +OP4 E0082F 0 +OP4 E00830 0 +OP4 E00831 0 +OP4 E00832 0 +OP4 E00833 0 +OP4 E00834 0 +OP4 E00835 0 +OP4 E00836 0 +OP4 E00837 0 +OP4 E00838 0 +OP4 E00839 0 +OP4 E0083A 0 +OP4 E0083B 0 +OP4 E0083C 0 +OP4 E0083D 0 +OP4 E0083E 0 +OP4 E0083F 0 +OP4 E00840 0 +OP4 E00841 0 +OP4 E00842 0 +OP4 E00843 0 +OP4 E00844 0 +OP4 E00845 0 +OP4 E00846 0 +OP4 E00847 0 +OP4 E00848 0 +OP4 E00849 0 +OP4 E0084A 0 +OP4 E0084B 0 +OP4 E0084C 0 +OP4 E0084D 0 +OP4 E0084E 0 +OP4 E0084F 0 +OP4 E00850 0 +OP4 E00851 0 +OP4 E00852 0 +OP4 E00853 0 +OP4 E00854 0 +OP4 E00855 0 +OP4 E00856 0 +OP4 E00857 0 +OP4 E00858 0 +OP4 E00859 0 +OP4 E0085A 0 +OP4 E0085B 0 +OP4 E0085C 0 +OP4 E0085D 0 +OP4 E0085E 0 +OP4 E0085F 0 +OP4 E00860 0 +OP4 E00861 0 +OP4 E00862 0 +OP4 E00863 0 +OP4 E00864 0 +OP4 E00865 0 +OP4 E00866 0 +OP4 E00867 0 +OP4 E00868 0 +OP4 E00869 0 +OP4 E0086A 0 +OP4 E0086B 0 +OP4 E0086C 0 +OP4 E0086D 0 +OP4 E0086E 0 +OP4 E0086F 0 +OP4 E00870 0 +OP4 E00871 0 +OP4 E00872 0 +OP4 E00873 0 +OP4 E00874 0 +OP4 E00875 0 +OP4 E00876 0 +OP4 E00877 0 +OP4 E00878 0 +OP4 E00879 0 +OP4 E0087A 0 +OP4 E0087B 0 +OP4 E0087C 0 +OP4 E0087D 0 +OP4 E0087E 0 +OP4 E0087F 0 +OP4 E00880 0 +OP4 E00881 0 +OP4 E00882 0 +OP4 E00883 0 +OP4 E00884 0 +OP4 E00885 0 +OP4 E00886 0 +OP4 E00887 0 +OP4 E00888 0 +OP4 E00889 0 +OP4 E0088A 0 +OP4 E0088B 0 +OP4 E0088C 0 +OP4 E0088D 0 +OP4 E0088E 0 +OP4 E0088F 0 +OP4 E00890 0 +OP4 E00891 0 +OP4 E00892 0 +OP4 E00893 0 +OP4 E00894 0 +OP4 E00895 0 +OP4 E00896 0 +OP4 E00897 0 +OP4 E00898 0 +OP4 E00899 0 +OP4 E0089A 0 +OP4 E0089B 0 +OP4 E0089C 0 +OP4 E0089D 0 +OP4 E0089E 0 +OP4 E0089F 0 +OP4 E008A0 0 +OP4 E008A1 0 +OP4 E008A2 0 +OP4 E008A3 0 +OP4 E008A4 0 +OP4 E008A5 0 +OP4 E008A6 0 +OP4 E008A7 0 +OP4 E008A8 0 +OP4 E008A9 0 +OP4 E008AA 0 +OP4 E008AB 0 +OP4 E008AC 0 +OP4 E008AD 0 +OP4 E008AE 0 +OP4 E008AF 0 +OP4 E008B0 0 +OP4 E008B1 0 +OP4 E008B2 0 +OP4 E008B3 0 +OP4 E008B4 0 +OP4 E008B5 0 +OP4 E008B6 0 +OP4 E008B7 0 +OP4 E008B8 0 +OP4 E008B9 0 +OP4 E008BA 0 +OP4 E008BB 0 +OP4 E008BC 0 +OP4 E008BD 0 +OP4 E008BE 0 +OP4 E008BF 0 +OP4 E008C0 0 +OP4 E008C1 0 +OP4 E008C2 0 +OP4 E008C3 0 +OP4 E008C4 0 +OP4 E008C5 0 +OP4 E008C6 0 +OP4 E008C7 0 +OP4 E008C8 0 +OP4 E008C9 0 +OP4 E008CA 0 +OP4 E008CB 0 +OP4 E008CC 0 +OP4 E008CD 0 +OP4 E008CE 0 +OP4 E008CF 0 +OP4 E008D0 0 +OP4 E008D1 0 +OP4 E008D2 0 +OP4 E008D3 0 +OP4 E008D4 0 +OP4 E008D5 0 +OP4 E008D6 0 +OP4 E008D7 0 +OP4 E008D8 0 +OP4 E008D9 0 +OP4 E008DA 0 +OP4 E008DB 0 +OP4 E008DC 0 +OP4 E008DD 0 +OP4 E008DE 0 +OP4 E008DF 0 +OP4 E008E0 0 +OP4 E008E1 0 +OP4 E008E2 0 +OP4 E008E3 0 +OP4 E008E4 0 +OP4 E008E5 0 +OP4 E008E6 0 +OP4 E008E7 0 +OP4 E008E8 0 +OP4 E008E9 0 +OP4 E008EA 0 +OP4 E008EB 0 +OP4 E008EC 0 +OP4 E008ED 0 +OP4 E008EE 0 +OP4 E008EF 0 +OP4 E008F0 0 +OP4 E008F1 0 +OP4 E008F2 0 +OP4 E008F3 0 +OP4 E008F4 0 +OP4 E008F5 0 +OP4 E008F6 0 +OP4 E008F7 0 +OP4 E008F8 0 +OP4 E008F9 0 +OP4 E008FA 0 +OP4 E008FB 0 +OP4 E008FC 0 +OP4 E008FD 0 +OP4 E008FE 0 +OP4 E008FF 0 +OP4 E00900 0 +OP4 E00901 0 +OP4 E00902 0 +OP4 E00903 0 +OP4 E00904 0 +OP4 E00905 0 +OP4 E00906 0 +OP4 E00907 0 +OP4 E00908 0 +OP4 E00909 0 +OP4 E0090A 0 +OP4 E0090B 0 +OP4 E0090C 0 +OP4 E0090D 0 +OP4 E0090E 0 +OP4 E0090F 0 +OP4 E00910 0 +OP4 E00911 0 +OP4 E00912 0 +OP4 E00913 0 +OP4 E00914 0 +OP4 E00915 0 +OP4 E00916 0 +OP4 E00917 0 +OP4 E00918 0 +OP4 E00919 0 +OP4 E0091A 0 +OP4 E0091B 0 +OP4 E0091C 0 +OP4 E0091D 0 +OP4 E0091E 0 +OP4 E0091F 0 +OP4 E00920 0 +OP4 E00921 0 +OP4 E00922 0 +OP4 E00923 0 +OP4 E00924 0 +OP4 E00925 0 +OP4 E00926 0 +OP4 E00927 0 +OP4 E00928 0 +OP4 E00929 0 +OP4 E0092A 0 +OP4 E0092B 0 +OP4 E0092C 0 +OP4 E0092D 0 +OP4 E0092E 0 +OP4 E0092F 0 +OP4 E00930 0 +OP4 E00931 0 +OP4 E00932 0 +OP4 E00933 0 +OP4 E00934 0 +OP4 E00935 0 +OP4 E00936 0 +OP4 E00937 0 +OP4 E00938 0 +OP4 E00939 0 +OP4 E0093A 0 +OP4 E0093B 0 +OP4 E0093C 0 +OP4 E0093D 0 +OP4 E0093E 0 +OP4 E0093F 0 +OP4 E00940 0 +OP4 E00941 0 +OP4 E00942 0 +OP4 E00943 0 +OP4 E00944 0 +OP4 E00945 0 +OP4 E00946 0 +OP4 E00947 0 +OP4 E00948 0 +OP4 E00949 0 +OP4 E0094A 0 +OP4 E0094B 0 +OP4 E0094C 0 +OP4 E0094D 0 +OP4 E0094E 0 +OP4 E0094F 0 +OP4 E00950 0 +OP4 E00951 0 +OP4 E00952 0 +OP4 E00953 0 +OP4 E00954 0 +OP4 E00955 0 +OP4 E00956 0 +OP4 E00957 0 +OP4 E00958 0 +OP4 E00959 0 +OP4 E0095A 0 +OP4 E0095B 0 +OP4 E0095C 0 +OP4 E0095D 0 +OP4 E0095E 0 +OP4 E0095F 0 +OP4 E00960 0 +OP4 E00961 0 +OP4 E00962 0 +OP4 E00963 0 +OP4 E00964 0 +OP4 E00965 0 +OP4 E00966 0 +OP4 E00967 0 +OP4 E00968 0 +OP4 E00969 0 +OP4 E0096A 0 +OP4 E0096B 0 +OP4 E0096C 0 +OP4 E0096D 0 +OP4 E0096E 0 +OP4 E0096F 0 +OP4 E00970 0 +OP4 E00971 0 +OP4 E00972 0 +OP4 E00973 0 +OP4 E00974 0 +OP4 E00975 0 +OP4 E00976 0 +OP4 E00977 0 +OP4 E00978 0 +OP4 E00979 0 +OP4 E0097A 0 +OP4 E0097B 0 +OP4 E0097C 0 +OP4 E0097D 0 +OP4 E0097E 0 +OP4 E0097F 0 +OP4 E00980 0 +OP4 E00981 0 +OP4 E00982 0 +OP4 E00983 0 +OP4 E00984 0 +OP4 E00985 0 +OP4 E00986 0 +OP4 E00987 0 +OP4 E00988 0 +OP4 E00989 0 +OP4 E0098A 0 +OP4 E0098B 0 +OP4 E0098C 0 +OP4 E0098D 0 +OP4 E0098E 0 +OP4 E0098F 0 +OP4 E00990 0 +OP4 E00991 0 +OP4 E00992 0 +OP4 E00993 0 +OP4 E00994 0 +OP4 E00995 0 +OP4 E00996 0 +OP4 E00997 0 +OP4 E00998 0 +OP4 E00999 0 +OP4 E0099A 0 +OP4 E0099B 0 +OP4 E0099C 0 +OP4 E0099D 0 +OP4 E0099E 0 +OP4 E0099F 0 +OP4 E009A0 0 +OP4 E009A1 0 +OP4 E009A2 0 +OP4 E009A3 0 +OP4 E009A4 0 +OP4 E009A5 0 +OP4 E009A6 0 +OP4 E009A7 0 +OP4 E009A8 0 +OP4 E009A9 0 +OP4 E009AA 0 +OP4 E009AB 0 +OP4 E009AC 0 +OP4 E009AD 0 +OP4 E009AE 0 +OP4 E009AF 0 +OP4 E009B0 0 +OP4 E009B1 0 +OP4 E009B2 0 +OP4 E009B3 0 +OP4 E009B4 0 +OP4 E009B5 0 +OP4 E009B6 0 +OP4 E009B7 0 +OP4 E009B8 0 +OP4 E009B9 0 +OP4 E009BA 0 +OP4 E009BB 0 +OP4 E009BC 0 +OP4 E009BD 0 +OP4 E009BE 0 +OP4 E009BF 0 +OP4 E009C0 0 +OP4 E009C1 0 +OP4 E009C2 0 +OP4 E009C3 0 +OP4 E009C4 0 +OP4 E009C5 0 +OP4 E009C6 0 +OP4 E009C7 0 +OP4 E009C8 0 +OP4 E009C9 0 +OP4 E009CA 0 +OP4 E009CB 0 +OP4 E009CC 0 +OP4 E009CD 0 +OP4 E009CE 0 +OP4 E009CF 0 +OP4 E009D0 0 +OP4 E009D1 0 +OP4 E009D2 0 +OP4 E009D3 0 +OP4 E009D4 0 +OP4 E009D5 0 +OP4 E009D6 0 +OP4 E009D7 0 +OP4 E009D8 0 +OP4 E009D9 0 +OP4 E009DA 0 +OP4 E009DB 0 +OP4 E009DC 0 +OP4 E009DD 0 +OP4 E009DE 0 +OP4 E009DF 0 +OP4 E009E0 0 +OP4 E009E1 0 +OP4 E009E2 0 +OP4 E009E3 0 +OP4 E009E4 0 +OP4 E009E5 0 +OP4 E009E6 0 +OP4 E009E7 0 +OP4 E009E8 0 +OP4 E009E9 0 +OP4 E009EA 0 +OP4 E009EB 0 +OP4 E009EC 0 +OP4 E009ED 0 +OP4 E009EE 0 +OP4 E009EF 0 +OP4 E009F0 0 +OP4 E009F1 0 +OP4 E009F2 0 +OP4 E009F3 0 +OP4 E009F4 0 +OP4 E009F5 0 +OP4 E009F6 0 +OP4 E009F7 0 +OP4 E009F8 0 +OP4 E009F9 0 +OP4 E009FA 0 +OP4 E009FB 0 +OP4 E009FC 0 +OP4 E009FD 0 +OP4 E009FE 0 +OP4 E009FF 0 +OP4 E00A00 0 +OP4 E00A01 0 +OP4 E00A02 0 +OP4 E00A03 0 +OP4 E00A04 0 +OP4 E00A05 0 +OP4 E00A06 0 +OP4 E00A07 0 +OP4 E00A08 0 +OP4 E00A09 0 +OP4 E00A0A 0 +OP4 E00A0B 0 +OP4 E00A0C 0 +OP4 E00A0D 0 +OP4 E00A0E 0 +OP4 E00A0F 0 +OP4 E00A10 0 +OP4 E00A11 0 +OP4 E00A12 0 +OP4 E00A13 0 +OP4 E00A14 0 +OP4 E00A15 0 +OP4 E00A16 0 +OP4 E00A17 0 +OP4 E00A18 0 +OP4 E00A19 0 +OP4 E00A1A 0 +OP4 E00A1B 0 +OP4 E00A1C 0 +OP4 E00A1D 0 +OP4 E00A1E 0 +OP4 E00A1F 0 +OP4 E00A20 0 +OP4 E00A21 0 +OP4 E00A22 0 +OP4 E00A23 0 +OP4 E00A24 0 +OP4 E00A25 0 +OP4 E00A26 0 +OP4 E00A27 0 +OP4 E00A28 0 +OP4 E00A29 0 +OP4 E00A2A 0 +OP4 E00A2B 0 +OP4 E00A2C 0 +OP4 E00A2D 0 +OP4 E00A2E 0 +OP4 E00A2F 0 +OP4 E00A30 0 +OP4 E00A31 0 +OP4 E00A32 0 +OP4 E00A33 0 +OP4 E00A34 0 +OP4 E00A35 0 +OP4 E00A36 0 +OP4 E00A37 0 +OP4 E00A38 0 +OP4 E00A39 0 +OP4 E00A3A 0 +OP4 E00A3B 0 +OP4 E00A3C 0 +OP4 E00A3D 0 +OP4 E00A3E 0 +OP4 E00A3F 0 +OP4 E00A40 0 +OP4 E00A41 0 +OP4 E00A42 0 +OP4 E00A43 0 +OP4 E00A44 0 +OP4 E00A45 0 +OP4 E00A46 0 +OP4 E00A47 0 +OP4 E00A48 0 +OP4 E00A49 0 +OP4 E00A4A 0 +OP4 E00A4B 0 +OP4 E00A4C 0 +OP4 E00A4D 0 +OP4 E00A4E 0 +OP4 E00A4F 0 +OP4 E00A50 0 +OP4 E00A51 0 +OP4 E00A52 0 +OP4 E00A53 0 +OP4 E00A54 0 +OP4 E00A55 0 +OP4 E00A56 0 +OP4 E00A57 0 +OP4 E00A58 0 +OP4 E00A59 0 +OP4 E00A5A 0 +OP4 E00A5B 0 +OP4 E00A5C 0 +OP4 E00A5D 0 +OP4 E00A5E 0 +OP4 E00A5F 0 +OP4 E00A60 0 +OP4 E00A61 0 +OP4 E00A62 0 +OP4 E00A63 0 +OP4 E00A64 0 +OP4 E00A65 0 +OP4 E00A66 0 +OP4 E00A67 0 +OP4 E00A68 0 +OP4 E00A69 0 +OP4 E00A6A 0 +OP4 E00A6B 0 +OP4 E00A6C 0 +OP4 E00A6D 0 +OP4 E00A6E 0 +OP4 E00A6F 0 +OP4 E00A70 0 +OP4 E00A71 0 +OP4 E00A72 0 +OP4 E00A73 0 +OP4 E00A74 0 +OP4 E00A75 0 +OP4 E00A76 0 +OP4 E00A77 0 +OP4 E00A78 0 +OP4 E00A79 0 +OP4 E00A7A 0 +OP4 E00A7B 0 +OP4 E00A7C 0 +OP4 E00A7D 0 +OP4 E00A7E 0 +OP4 E00A7F 0 +OP4 E00A80 0 +OP4 E00A81 0 +OP4 E00A82 0 +OP4 E00A83 0 +OP4 E00A84 0 +OP4 E00A85 0 +OP4 E00A86 0 +OP4 E00A87 0 +OP4 E00A88 0 +OP4 E00A89 0 +OP4 E00A8A 0 +OP4 E00A8B 0 +OP4 E00A8C 0 +OP4 E00A8D 0 +OP4 E00A8E 0 +OP4 E00A8F 0 +OP4 E00A90 0 +OP4 E00A91 0 +OP4 E00A92 0 +OP4 E00A93 0 +OP4 E00A94 0 +OP4 E00A95 0 +OP4 E00A96 0 +OP4 E00A97 0 +OP4 E00A98 0 +OP4 E00A99 0 +OP4 E00A9A 0 +OP4 E00A9B 0 +OP4 E00A9C 0 +OP4 E00A9D 0 +OP4 E00A9E 0 +OP4 E00A9F 0 +OP4 E00AA0 0 +OP4 E00AA1 0 +OP4 E00AA2 0 +OP4 E00AA3 0 +OP4 E00AA4 0 +OP4 E00AA5 0 +OP4 E00AA6 0 +OP4 E00AA7 0 +OP4 E00AA8 0 +OP4 E00AA9 0 +OP4 E00AAA 0 +OP4 E00AAB 0 +OP4 E00AAC 0 +OP4 E00AAD 0 +OP4 E00AAE 0 +OP4 E00AAF 0 +OP4 E00AB0 0 +OP4 E00AB1 0 +OP4 E00AB2 0 +OP4 E00AB3 0 +OP4 E00AB4 0 +OP4 E00AB5 0 +OP4 E00AB6 0 +OP4 E00AB7 0 +OP4 E00AB8 0 +OP4 E00AB9 0 +OP4 E00ABA 0 +OP4 E00ABB 0 +OP4 E00ABC 0 +OP4 E00ABD 0 +OP4 E00ABE 0 +OP4 E00ABF 0 +OP4 E00AC0 0 +OP4 E00AC1 0 +OP4 E00AC2 0 +OP4 E00AC3 0 +OP4 E00AC4 0 +OP4 E00AC5 0 +OP4 E00AC6 0 +OP4 E00AC7 0 +OP4 E00AC8 0 +OP4 E00AC9 0 +OP4 E00ACA 0 +OP4 E00ACB 0 +OP4 E00ACC 0 +OP4 E00ACD 0 +OP4 E00ACE 0 +OP4 E00ACF 0 +OP4 E00AD0 0 +OP4 E00AD1 0 +OP4 E00AD2 0 +OP4 E00AD3 0 +OP4 E00AD4 0 +OP4 E00AD5 0 +OP4 E00AD6 0 +OP4 E00AD7 0 +OP4 E00AD8 0 +OP4 E00AD9 0 +OP4 E00ADA 0 +OP4 E00ADB 0 +OP4 E00ADC 0 +OP4 E00ADD 0 +OP4 E00ADE 0 +OP4 E00ADF 0 +OP4 E00AE0 0 +OP4 E00AE1 0 +OP4 E00AE2 0 +OP4 E00AE3 0 +OP4 E00AE4 0 +OP4 E00AE5 0 +OP4 E00AE6 0 +OP4 E00AE7 0 +OP4 E00AE8 0 +OP4 E00AE9 0 +OP4 E00AEA 0 +OP4 E00AEB 0 +OP4 E00AEC 0 +OP4 E00AED 0 +OP4 E00AEE 0 +OP4 E00AEF 0 +OP4 E00AF0 0 +OP4 E00AF1 0 +OP4 E00AF2 0 +OP4 E00AF3 0 +OP4 E00AF4 0 +OP4 E00AF5 0 +OP4 E00AF6 0 +OP4 E00AF7 0 +OP4 E00AF8 0 +OP4 E00AF9 0 +OP4 E00AFA 0 +OP4 E00AFB 0 +OP4 E00AFC 0 +OP4 E00AFD 0 +OP4 E00AFE 0 +OP4 E00AFF 0 +OP4 E00B00 0 +OP4 E00B01 0 +OP4 E00B02 0 +OP4 E00B03 0 +OP4 E00B04 0 +OP4 E00B05 0 +OP4 E00B06 0 +OP4 E00B07 0 +OP4 E00B08 0 +OP4 E00B09 0 +OP4 E00B0A 0 +OP4 E00B0B 0 +OP4 E00B0C 0 +OP4 E00B0D 0 +OP4 E00B0E 0 +OP4 E00B0F 0 +OP4 E00B10 0 +OP4 E00B11 0 +OP4 E00B12 0 +OP4 E00B13 0 +OP4 E00B14 0 +OP4 E00B15 0 +OP4 E00B16 0 +OP4 E00B17 0 +OP4 E00B18 0 +OP4 E00B19 0 +OP4 E00B1A 0 +OP4 E00B1B 0 +OP4 E00B1C 0 +OP4 E00B1D 0 +OP4 E00B1E 0 +OP4 E00B1F 0 +OP4 E00B20 0 +OP4 E00B21 0 +OP4 E00B22 0 +OP4 E00B23 0 +OP4 E00B24 0 +OP4 E00B25 0 +OP4 E00B26 0 +OP4 E00B27 0 +OP4 E00B28 0 +OP4 E00B29 0 +OP4 E00B2A 0 +OP4 E00B2B 0 +OP4 E00B2C 0 +OP4 E00B2D 0 +OP4 E00B2E 0 +OP4 E00B2F 0 +OP4 E00B30 0 +OP4 E00B31 0 +OP4 E00B32 0 +OP4 E00B33 0 +OP4 E00B34 0 +OP4 E00B35 0 +OP4 E00B36 0 +OP4 E00B37 0 +OP4 E00B38 0 +OP4 E00B39 0 +OP4 E00B3A 0 +OP4 E00B3B 0 +OP4 E00B3C 0 +OP4 E00B3D 0 +OP4 E00B3E 0 +OP4 E00B3F 0 +OP4 E00B40 0 +OP4 E00B41 0 +OP4 E00B42 0 +OP4 E00B43 0 +OP4 E00B44 0 +OP4 E00B45 0 +OP4 E00B46 0 +OP4 E00B47 0 +OP4 E00B48 0 +OP4 E00B49 0 +OP4 E00B4A 0 +OP4 E00B4B 0 +OP4 E00B4C 0 +OP4 E00B4D 0 +OP4 E00B4E 0 +OP4 E00B4F 0 +OP4 E00B50 0 +OP4 E00B51 0 +OP4 E00B52 0 +OP4 E00B53 0 +OP4 E00B54 0 +OP4 E00B55 0 +OP4 E00B56 0 +OP4 E00B57 0 +OP4 E00B58 0 +OP4 E00B59 0 +OP4 E00B5A 0 +OP4 E00B5B 0 +OP4 E00B5C 0 +OP4 E00B5D 0 +OP4 E00B5E 0 +OP4 E00B5F 0 +OP4 E00B60 0 +OP4 E00B61 0 +OP4 E00B62 0 +OP4 E00B63 0 +OP4 E00B64 0 +OP4 E00B65 0 +OP4 E00B66 0 +OP4 E00B67 0 +OP4 E00B68 0 +OP4 E00B69 0 +OP4 E00B6A 0 +OP4 E00B6B 0 +OP4 E00B6C 0 +OP4 E00B6D 0 +OP4 E00B6E 0 +OP4 E00B6F 0 +OP4 E00B70 0 +OP4 E00B71 0 +OP4 E00B72 0 +OP4 E00B73 0 +OP4 E00B74 0 +OP4 E00B75 0 +OP4 E00B76 0 +OP4 E00B77 0 +OP4 E00B78 0 +OP4 E00B79 0 +OP4 E00B7A 0 +OP4 E00B7B 0 +OP4 E00B7C 0 +OP4 E00B7D 0 +OP4 E00B7E 0 +OP4 E00B7F 0 +OP4 E00B80 0 +OP4 E00B81 0 +OP4 E00B82 0 +OP4 E00B83 0 +OP4 E00B84 0 +OP4 E00B85 0 +OP4 E00B86 0 +OP4 E00B87 0 +OP4 E00B88 0 +OP4 E00B89 0 +OP4 E00B8A 0 +OP4 E00B8B 0 +OP4 E00B8C 0 +OP4 E00B8D 0 +OP4 E00B8E 0 +OP4 E00B8F 0 +OP4 E00B90 0 +OP4 E00B91 0 +OP4 E00B92 0 +OP4 E00B93 0 +OP4 E00B94 0 +OP4 E00B95 0 +OP4 E00B96 0 +OP4 E00B97 0 +OP4 E00B98 0 +OP4 E00B99 0 +OP4 E00B9A 0 +OP4 E00B9B 0 +OP4 E00B9C 0 +OP4 E00B9D 0 +OP4 E00B9E 0 +OP4 E00B9F 0 +OP4 E00BA0 0 +OP4 E00BA1 0 +OP4 E00BA2 0 +OP4 E00BA3 0 +OP4 E00BA4 0 +OP4 E00BA5 0 +OP4 E00BA6 0 +OP4 E00BA7 0 +OP4 E00BA8 0 +OP4 E00BA9 0 +OP4 E00BAA 0 +OP4 E00BAB 0 +OP4 E00BAC 0 +OP4 E00BAD 0 +OP4 E00BAE 0 +OP4 E00BAF 0 +OP4 E00BB0 0 +OP4 E00BB1 0 +OP4 E00BB2 0 +OP4 E00BB3 0 +OP4 E00BB4 0 +OP4 E00BB5 0 +OP4 E00BB6 0 +OP4 E00BB7 0 +OP4 E00BB8 0 +OP4 E00BB9 0 +OP4 E00BBA 0 +OP4 E00BBB 0 +OP4 E00BBC 0 +OP4 E00BBD 0 +OP4 E00BBE 0 +OP4 E00BBF 0 +OP4 E00BC0 0 +OP4 E00BC1 0 +OP4 E00BC2 0 +OP4 E00BC3 0 +OP4 E00BC4 0 +OP4 E00BC5 0 +OP4 E00BC6 0 +OP4 E00BC7 0 +OP4 E00BC8 0 +OP4 E00BC9 0 +OP4 E00BCA 0 +OP4 E00BCB 0 +OP4 E00BCC 0 +OP4 E00BCD 0 +OP4 E00BCE 0 +OP4 E00BCF 0 +OP4 E00BD0 0 +OP4 E00BD1 0 +OP4 E00BD2 0 +OP4 E00BD3 0 +OP4 E00BD4 0 +OP4 E00BD5 0 +OP4 E00BD6 0 +OP4 E00BD7 0 +OP4 E00BD8 0 +OP4 E00BD9 0 +OP4 E00BDA 0 +OP4 E00BDB 0 +OP4 E00BDC 0 +OP4 E00BDD 0 +OP4 E00BDE 0 +OP4 E00BDF 0 +OP4 E00BE0 0 +OP4 E00BE1 0 +OP4 E00BE2 0 +OP4 E00BE3 0 +OP4 E00BE4 0 +OP4 E00BE5 0 +OP4 E00BE6 0 +OP4 E00BE7 0 +OP4 E00BE8 0 +OP4 E00BE9 0 +OP4 E00BEA 0 +OP4 E00BEB 0 +OP4 E00BEC 0 +OP4 E00BED 0 +OP4 E00BEE 0 +OP4 E00BEF 0 +OP4 E00BF0 0 +OP4 E00BF1 0 +OP4 E00BF2 0 +OP4 E00BF3 0 +OP4 E00BF4 0 +OP4 E00BF5 0 +OP4 E00BF6 0 +OP4 E00BF7 0 +OP4 E00BF8 0 +OP4 E00BF9 0 +OP4 E00BFA 0 +OP4 E00BFB 0 +OP4 E00BFC 0 +OP4 E00BFD 0 +OP4 E00BFE 0 +OP4 E00BFF 0 +OP4 E00C00 0 +OP4 E00C01 0 +OP4 E00C02 0 +OP4 E00C03 0 +OP4 E00C04 0 +OP4 E00C05 0 +OP4 E00C06 0 +OP4 E00C07 0 +OP4 E00C08 0 +OP4 E00C09 0 +OP4 E00C0A 0 +OP4 E00C0B 0 +OP4 E00C0C 0 +OP4 E00C0D 0 +OP4 E00C0E 0 +OP4 E00C0F 0 +OP4 E00C10 0 +OP4 E00C11 0 +OP4 E00C12 0 +OP4 E00C13 0 +OP4 E00C14 0 +OP4 E00C15 0 +OP4 E00C16 0 +OP4 E00C17 0 +OP4 E00C18 0 +OP4 E00C19 0 +OP4 E00C1A 0 +OP4 E00C1B 0 +OP4 E00C1C 0 +OP4 E00C1D 0 +OP4 E00C1E 0 +OP4 E00C1F 0 +OP4 E00C20 0 +OP4 E00C21 0 +OP4 E00C22 0 +OP4 E00C23 0 +OP4 E00C24 0 +OP4 E00C25 0 +OP4 E00C26 0 +OP4 E00C27 0 +OP4 E00C28 0 +OP4 E00C29 0 +OP4 E00C2A 0 +OP4 E00C2B 0 +OP4 E00C2C 0 +OP4 E00C2D 0 +OP4 E00C2E 0 +OP4 E00C2F 0 +OP4 E00C30 0 +OP4 E00C31 0 +OP4 E00C32 0 +OP4 E00C33 0 +OP4 E00C34 0 +OP4 E00C35 0 +OP4 E00C36 0 +OP4 E00C37 0 +OP4 E00C38 0 +OP4 E00C39 0 +OP4 E00C3A 0 +OP4 E00C3B 0 +OP4 E00C3C 0 +OP4 E00C3D 0 +OP4 E00C3E 0 +OP4 E00C3F 0 +OP4 E00C40 0 +OP4 E00C41 0 +OP4 E00C42 0 +OP4 E00C43 0 +OP4 E00C44 0 +OP4 E00C45 0 +OP4 E00C46 0 +OP4 E00C47 0 +OP4 E00C48 0 +OP4 E00C49 0 +OP4 E00C4A 0 +OP4 E00C4B 0 +OP4 E00C4C 0 +OP4 E00C4D 0 +OP4 E00C4E 0 +OP4 E00C4F 0 +OP4 E00C50 0 +OP4 E00C51 0 +OP4 E00C52 0 +OP4 E00C53 0 +OP4 E00C54 0 +OP4 E00C55 0 +OP4 E00C56 0 +OP4 E00C57 0 +OP4 E00C58 0 +OP4 E00C59 0 +OP4 E00C5A 0 +OP4 E00C5B 0 +OP4 E00C5C 0 +OP4 E00C5D 0 +OP4 E00C5E 0 +OP4 E00C5F 0 +OP4 E00C60 0 +OP4 E00C61 0 +OP4 E00C62 0 +OP4 E00C63 0 +OP4 E00C64 0 +OP4 E00C65 0 +OP4 E00C66 0 +OP4 E00C67 0 +OP4 E00C68 0 +OP4 E00C69 0 +OP4 E00C6A 0 +OP4 E00C6B 0 +OP4 E00C6C 0 +OP4 E00C6D 0 +OP4 E00C6E 0 +OP4 E00C6F 0 +OP4 E00C70 0 +OP4 E00C71 0 +OP4 E00C72 0 +OP4 E00C73 0 +OP4 E00C74 0 +OP4 E00C75 0 +OP4 E00C76 0 +OP4 E00C77 0 +OP4 E00C78 0 +OP4 E00C79 0 +OP4 E00C7A 0 +OP4 E00C7B 0 +OP4 E00C7C 0 +OP4 E00C7D 0 +OP4 E00C7E 0 +OP4 E00C7F 0 +OP4 E00C80 0 +OP4 E00C81 0 +OP4 E00C82 0 +OP4 E00C83 0 +OP4 E00C84 0 +OP4 E00C85 0 +OP4 E00C86 0 +OP4 E00C87 0 +OP4 E00C88 0 +OP4 E00C89 0 +OP4 E00C8A 0 +OP4 E00C8B 0 +OP4 E00C8C 0 +OP4 E00C8D 0 +OP4 E00C8E 0 +OP4 E00C8F 0 +OP4 E00C90 0 +OP4 E00C91 0 +OP4 E00C92 0 +OP4 E00C93 0 +OP4 E00C94 0 +OP4 E00C95 0 +OP4 E00C96 0 +OP4 E00C97 0 +OP4 E00C98 0 +OP4 E00C99 0 +OP4 E00C9A 0 +OP4 E00C9B 0 +OP4 E00C9C 0 +OP4 E00C9D 0 +OP4 E00C9E 0 +OP4 E00C9F 0 +OP4 E00CA0 0 +OP4 E00CA1 0 +OP4 E00CA2 0 +OP4 E00CA3 0 +OP4 E00CA4 0 +OP4 E00CA5 0 +OP4 E00CA6 0 +OP4 E00CA7 0 +OP4 E00CA8 0 +OP4 E00CA9 0 +OP4 E00CAA 0 +OP4 E00CAB 0 +OP4 E00CAC 0 +OP4 E00CAD 0 +OP4 E00CAE 0 +OP4 E00CAF 0 +OP4 E00CB0 0 +OP4 E00CB1 0 +OP4 E00CB2 0 +OP4 E00CB3 0 +OP4 E00CB4 0 +OP4 E00CB5 0 +OP4 E00CB6 0 +OP4 E00CB7 0 +OP4 E00CB8 0 +OP4 E00CB9 0 +OP4 E00CBA 0 +OP4 E00CBB 0 +OP4 E00CBC 0 +OP4 E00CBD 0 +OP4 E00CBE 0 +OP4 E00CBF 0 +OP4 E00CC0 0 +OP4 E00CC1 0 +OP4 E00CC2 0 +OP4 E00CC3 0 +OP4 E00CC4 0 +OP4 E00CC5 0 +OP4 E00CC6 0 +OP4 E00CC7 0 +OP4 E00CC8 0 +OP4 E00CC9 0 +OP4 E00CCA 0 +OP4 E00CCB 0 +OP4 E00CCC 0 +OP4 E00CCD 0 +OP4 E00CCE 0 +OP4 E00CCF 0 +OP4 E00CD0 0 +OP4 E00CD1 0 +OP4 E00CD2 0 +OP4 E00CD3 0 +OP4 E00CD4 0 +OP4 E00CD5 0 +OP4 E00CD6 0 +OP4 E00CD7 0 +OP4 E00CD8 0 +OP4 E00CD9 0 +OP4 E00CDA 0 +OP4 E00CDB 0 +OP4 E00CDC 0 +OP4 E00CDD 0 +OP4 E00CDE 0 +OP4 E00CDF 0 +OP4 E00CE0 0 +OP4 E00CE1 0 +OP4 E00CE2 0 +OP4 E00CE3 0 +OP4 E00CE4 0 +OP4 E00CE5 0 +OP4 E00CE6 0 +OP4 E00CE7 0 +OP4 E00CE8 0 +OP4 E00CE9 0 +OP4 E00CEA 0 +OP4 E00CEB 0 +OP4 E00CEC 0 +OP4 E00CED 0 +OP4 E00CEE 0 +OP4 E00CEF 0 +OP4 E00CF0 0 +OP4 E00CF1 0 +OP4 E00CF2 0 +OP4 E00CF3 0 +OP4 E00CF4 0 +OP4 E00CF5 0 +OP4 E00CF6 0 +OP4 E00CF7 0 +OP4 E00CF8 0 +OP4 E00CF9 0 +OP4 E00CFA 0 +OP4 E00CFB 0 +OP4 E00CFC 0 +OP4 E00CFD 0 +OP4 E00CFE 0 +OP4 E00CFF 0 +OP4 E00D00 0 +OP4 E00D01 0 +OP4 E00D02 0 +OP4 E00D03 0 +OP4 E00D04 0 +OP4 E00D05 0 +OP4 E00D06 0 +OP4 E00D07 0 +OP4 E00D08 0 +OP4 E00D09 0 +OP4 E00D0A 0 +OP4 E00D0B 0 +OP4 E00D0C 0 +OP4 E00D0D 0 +OP4 E00D0E 0 +OP4 E00D0F 0 +OP4 E00D10 0 +OP4 E00D11 0 +OP4 E00D12 0 +OP4 E00D13 0 +OP4 E00D14 0 +OP4 E00D15 0 +OP4 E00D16 0 +OP4 E00D17 0 +OP4 E00D18 0 +OP4 E00D19 0 +OP4 E00D1A 0 +OP4 E00D1B 0 +OP4 E00D1C 0 +OP4 E00D1D 0 +OP4 E00D1E 0 +OP4 E00D1F 0 +OP4 E00D20 0 +OP4 E00D21 0 +OP4 E00D22 0 +OP4 E00D23 0 +OP4 E00D24 0 +OP4 E00D25 0 +OP4 E00D26 0 +OP4 E00D27 0 +OP4 E00D28 0 +OP4 E00D29 0 +OP4 E00D2A 0 +OP4 E00D2B 0 +OP4 E00D2C 0 +OP4 E00D2D 0 +OP4 E00D2E 0 +OP4 E00D2F 0 +OP4 E00D30 0 +OP4 E00D31 0 +OP4 E00D32 0 +OP4 E00D33 0 +OP4 E00D34 0 +OP4 E00D35 0 +OP4 E00D36 0 +OP4 E00D37 0 +OP4 E00D38 0 +OP4 E00D39 0 +OP4 E00D3A 0 +OP4 E00D3B 0 +OP4 E00D3C 0 +OP4 E00D3D 0 +OP4 E00D3E 0 +OP4 E00D3F 0 +OP4 E00D40 0 +OP4 E00D41 0 +OP4 E00D42 0 +OP4 E00D43 0 +OP4 E00D44 0 +OP4 E00D45 0 +OP4 E00D46 0 +OP4 E00D47 0 +OP4 E00D48 0 +OP4 E00D49 0 +OP4 E00D4A 0 +OP4 E00D4B 0 +OP4 E00D4C 0 +OP4 E00D4D 0 +OP4 E00D4E 0 +OP4 E00D4F 0 +OP4 E00D50 0 +OP4 E00D51 0 +OP4 E00D52 0 +OP4 E00D53 0 +OP4 E00D54 0 +OP4 E00D55 0 +OP4 E00D56 0 +OP4 E00D57 0 +OP4 E00D58 0 +OP4 E00D59 0 +OP4 E00D5A 0 +OP4 E00D5B 0 +OP4 E00D5C 0 +OP4 E00D5D 0 +OP4 E00D5E 0 +OP4 E00D5F 0 +OP4 E00D60 0 +OP4 E00D61 0 +OP4 E00D62 0 +OP4 E00D63 0 +OP4 E00D64 0 +OP4 E00D65 0 +OP4 E00D66 0 +OP4 E00D67 0 +OP4 E00D68 0 +OP4 E00D69 0 +OP4 E00D6A 0 +OP4 E00D6B 0 +OP4 E00D6C 0 +OP4 E00D6D 0 +OP4 E00D6E 0 +OP4 E00D6F 0 +OP4 E00D70 0 +OP4 E00D71 0 +OP4 E00D72 0 +OP4 E00D73 0 +OP4 E00D74 0 +OP4 E00D75 0 +OP4 E00D76 0 +OP4 E00D77 0 +OP4 E00D78 0 +OP4 E00D79 0 +OP4 E00D7A 0 +OP4 E00D7B 0 +OP4 E00D7C 0 +OP4 E00D7D 0 +OP4 E00D7E 0 +OP4 E00D7F 0 +OP4 E00D80 0 +OP4 E00D81 0 +OP4 E00D82 0 +OP4 E00D83 0 +OP4 E00D84 0 +OP4 E00D85 0 +OP4 E00D86 0 +OP4 E00D87 0 +OP4 E00D88 0 +OP4 E00D89 0 +OP4 E00D8A 0 +OP4 E00D8B 0 +OP4 E00D8C 0 +OP4 E00D8D 0 +OP4 E00D8E 0 +OP4 E00D8F 0 +OP4 E00D90 0 +OP4 E00D91 0 +OP4 E00D92 0 +OP4 E00D93 0 +OP4 E00D94 0 +OP4 E00D95 0 +OP4 E00D96 0 +OP4 E00D97 0 +OP4 E00D98 0 +OP4 E00D99 0 +OP4 E00D9A 0 +OP4 E00D9B 0 +OP4 E00D9C 0 +OP4 E00D9D 0 +OP4 E00D9E 0 +OP4 E00D9F 0 +OP4 E00DA0 0 +OP4 E00DA1 0 +OP4 E00DA2 0 +OP4 E00DA3 0 +OP4 E00DA4 0 +OP4 E00DA5 0 +OP4 E00DA6 0 +OP4 E00DA7 0 +OP4 E00DA8 0 +OP4 E00DA9 0 +OP4 E00DAA 0 +OP4 E00DAB 0 +OP4 E00DAC 0 +OP4 E00DAD 0 +OP4 E00DAE 0 +OP4 E00DAF 0 +OP4 E00DB0 0 +OP4 E00DB1 0 +OP4 E00DB2 0 +OP4 E00DB3 0 +OP4 E00DB4 0 +OP4 E00DB5 0 +OP4 E00DB6 0 +OP4 E00DB7 0 +OP4 E00DB8 0 +OP4 E00DB9 0 +OP4 E00DBA 0 +OP4 E00DBB 0 +OP4 E00DBC 0 +OP4 E00DBD 0 +OP4 E00DBE 0 +OP4 E00DBF 0 +OP4 E00DC0 0 +OP4 E00DC1 0 +OP4 E00DC2 0 +OP4 E00DC3 0 +OP4 E00DC4 0 +OP4 E00DC5 0 +OP4 E00DC6 0 +OP4 E00DC7 0 +OP4 E00DC8 0 +OP4 E00DC9 0 +OP4 E00DCA 0 +OP4 E00DCB 0 +OP4 E00DCC 0 +OP4 E00DCD 0 +OP4 E00DCE 0 +OP4 E00DCF 0 +OP4 E00DD0 0 +OP4 E00DD1 0 +OP4 E00DD2 0 +OP4 E00DD3 0 +OP4 E00DD4 0 +OP4 E00DD5 0 +OP4 E00DD6 0 +OP4 E00DD7 0 +OP4 E00DD8 0 +OP4 E00DD9 0 +OP4 E00DDA 0 +OP4 E00DDB 0 +OP4 E00DDC 0 +OP4 E00DDD 0 +OP4 E00DDE 0 +OP4 E00DDF 0 +OP4 E00DE0 0 +OP4 E00DE1 0 +OP4 E00DE2 0 +OP4 E00DE3 0 +OP4 E00DE4 0 +OP4 E00DE5 0 +OP4 E00DE6 0 +OP4 E00DE7 0 +OP4 E00DE8 0 +OP4 E00DE9 0 +OP4 E00DEA 0 +OP4 E00DEB 0 +OP4 E00DEC 0 +OP4 E00DED 0 +OP4 E00DEE 0 +OP4 E00DEF 0 +OP4 E00DF0 0 +OP4 E00DF1 0 +OP4 E00DF2 0 +OP4 E00DF3 0 +OP4 E00DF4 0 +OP4 E00DF5 0 +OP4 E00DF6 0 +OP4 E00DF7 0 +OP4 E00DF8 0 +OP4 E00DF9 0 +OP4 E00DFA 0 +OP4 E00DFB 0 +OP4 E00DFC 0 +OP4 E00DFD 0 +OP4 E00DFE 0 +OP4 E00DFF 0 +OP4 E00E00 0 +OP4 E00E01 0 +OP4 E00E02 0 +OP4 E00E03 0 +OP4 E00E04 0 +OP4 E00E05 0 +OP4 E00E06 0 +OP4 E00E07 0 +OP4 E00E08 0 +OP4 E00E09 0 +OP4 E00E0A 0 +OP4 E00E0B 0 +OP4 E00E0C 0 +OP4 E00E0D 0 +OP4 E00E0E 0 +OP4 E00E0F 0 +OP4 E00E10 0 +OP4 E00E11 0 +OP4 E00E12 0 +OP4 E00E13 0 +OP4 E00E14 0 +OP4 E00E15 0 +OP4 E00E16 0 +OP4 E00E17 0 +OP4 E00E18 0 +OP4 E00E19 0 +OP4 E00E1A 0 +OP4 E00E1B 0 +OP4 E00E1C 0 +OP4 E00E1D 0 +OP4 E00E1E 0 +OP4 E00E1F 0 +OP4 E00E20 0 +OP4 E00E21 0 +OP4 E00E22 0 +OP4 E00E23 0 +OP4 E00E24 0 +OP4 E00E25 0 +OP4 E00E26 0 +OP4 E00E27 0 +OP4 E00E28 0 +OP4 E00E29 0 +OP4 E00E2A 0 +OP4 E00E2B 0 +OP4 E00E2C 0 +OP4 E00E2D 0 +OP4 E00E2E 0 +OP4 E00E2F 0 +OP4 E00E30 0 +OP4 E00E31 0 +OP4 E00E32 0 +OP4 E00E33 0 +OP4 E00E34 0 +OP4 E00E35 0 +OP4 E00E36 0 +OP4 E00E37 0 +OP4 E00E38 0 +OP4 E00E39 0 +OP4 E00E3A 0 +OP4 E00E3B 0 +OP4 E00E3C 0 +OP4 E00E3D 0 +OP4 E00E3E 0 +OP4 E00E3F 0 +OP4 E00E40 0 +OP4 E00E41 0 +OP4 E00E42 0 +OP4 E00E43 0 +OP4 E00E44 0 +OP4 E00E45 0 +OP4 E00E46 0 +OP4 E00E47 0 +OP4 E00E48 0 +OP4 E00E49 0 +OP4 E00E4A 0 +OP4 E00E4B 0 +OP4 E00E4C 0 +OP4 E00E4D 0 +OP4 E00E4E 0 +OP4 E00E4F 0 +OP4 E00E50 0 +OP4 E00E51 0 +OP4 E00E52 0 +OP4 E00E53 0 +OP4 E00E54 0 +OP4 E00E55 0 +OP4 E00E56 0 +OP4 E00E57 0 +OP4 E00E58 0 +OP4 E00E59 0 +OP4 E00E5A 0 +OP4 E00E5B 0 +OP4 E00E5C 0 +OP4 E00E5D 0 +OP4 E00E5E 0 +OP4 E00E5F 0 +OP4 E00E60 0 +OP4 E00E61 0 +OP4 E00E62 0 +OP4 E00E63 0 +OP4 E00E64 0 +OP4 E00E65 0 +OP4 E00E66 0 +OP4 E00E67 0 +OP4 E00E68 0 +OP4 E00E69 0 +OP4 E00E6A 0 +OP4 E00E6B 0 +OP4 E00E6C 0 +OP4 E00E6D 0 +OP4 E00E6E 0 +OP4 E00E6F 0 +OP4 E00E70 0 +OP4 E00E71 0 +OP4 E00E72 0 +OP4 E00E73 0 +OP4 E00E74 0 +OP4 E00E75 0 +OP4 E00E76 0 +OP4 E00E77 0 +OP4 E00E78 0 +OP4 E00E79 0 +OP4 E00E7A 0 +OP4 E00E7B 0 +OP4 E00E7C 0 +OP4 E00E7D 0 +OP4 E00E7E 0 +OP4 E00E7F 0 +OP4 E00E80 0 +OP4 E00E81 0 +OP4 E00E82 0 +OP4 E00E83 0 +OP4 E00E84 0 +OP4 E00E85 0 +OP4 E00E86 0 +OP4 E00E87 0 +OP4 E00E88 0 +OP4 E00E89 0 +OP4 E00E8A 0 +OP4 E00E8B 0 +OP4 E00E8C 0 +OP4 E00E8D 0 +OP4 E00E8E 0 +OP4 E00E8F 0 +OP4 E00E90 0 +OP4 E00E91 0 +OP4 E00E92 0 +OP4 E00E93 0 +OP4 E00E94 0 +OP4 E00E95 0 +OP4 E00E96 0 +OP4 E00E97 0 +OP4 E00E98 0 +OP4 E00E99 0 +OP4 E00E9A 0 +OP4 E00E9B 0 +OP4 E00E9C 0 +OP4 E00E9D 0 +OP4 E00E9E 0 +OP4 E00E9F 0 +OP4 E00EA0 0 +OP4 E00EA1 0 +OP4 E00EA2 0 +OP4 E00EA3 0 +OP4 E00EA4 0 +OP4 E00EA5 0 +OP4 E00EA6 0 +OP4 E00EA7 0 +OP4 E00EA8 0 +OP4 E00EA9 0 +OP4 E00EAA 0 +OP4 E00EAB 0 +OP4 E00EAC 0 +OP4 E00EAD 0 +OP4 E00EAE 0 +OP4 E00EAF 0 +OP4 E00EB0 0 +OP4 E00EB1 0 +OP4 E00EB2 0 +OP4 E00EB3 0 +OP4 E00EB4 0 +OP4 E00EB5 0 +OP4 E00EB6 0 +OP4 E00EB7 0 +OP4 E00EB8 0 +OP4 E00EB9 0 +OP4 E00EBA 0 +OP4 E00EBB 0 +OP4 E00EBC 0 +OP4 E00EBD 0 +OP4 E00EBE 0 +OP4 E00EBF 0 +OP4 E00EC0 0 +OP4 E00EC1 0 +OP4 E00EC2 0 +OP4 E00EC3 0 +OP4 E00EC4 0 +OP4 E00EC5 0 +OP4 E00EC6 0 +OP4 E00EC7 0 +OP4 E00EC8 0 +OP4 E00EC9 0 +OP4 E00ECA 0 +OP4 E00ECB 0 +OP4 E00ECC 0 +OP4 E00ECD 0 +OP4 E00ECE 0 +OP4 E00ECF 0 +OP4 E00ED0 0 +OP4 E00ED1 0 +OP4 E00ED2 0 +OP4 E00ED3 0 +OP4 E00ED4 0 +OP4 E00ED5 0 +OP4 E00ED6 0 +OP4 E00ED7 0 +OP4 E00ED8 0 +OP4 E00ED9 0 +OP4 E00EDA 0 +OP4 E00EDB 0 +OP4 E00EDC 0 +OP4 E00EDD 0 +OP4 E00EDE 0 +OP4 E00EDF 0 +OP4 E00EE0 0 +OP4 E00EE1 0 +OP4 E00EE2 0 +OP4 E00EE3 0 +OP4 E00EE4 0 +OP4 E00EE5 0 +OP4 E00EE6 0 +OP4 E00EE7 0 +OP4 E00EE8 0 +OP4 E00EE9 0 +OP4 E00EEA 0 +OP4 E00EEB 0 +OP4 E00EEC 0 +OP4 E00EED 0 +OP4 E00EEE 0 +OP4 E00EEF 0 +OP4 E00EF0 0 +OP4 E00EF1 0 +OP4 E00EF2 0 +OP4 E00EF3 0 +OP4 E00EF4 0 +OP4 E00EF5 0 +OP4 E00EF6 0 +OP4 E00EF7 0 +OP4 E00EF8 0 +OP4 E00EF9 0 +OP4 E00EFA 0 +OP4 E00EFB 0 +OP4 E00EFC 0 +OP4 E00EFD 0 +OP4 E00EFE 0 +OP4 E00EFF 0 +OP4 E00F00 0 +OP4 E00F01 0 +OP4 E00F02 0 +OP4 E00F03 0 +OP4 E00F04 0 +OP4 E00F05 0 +OP4 E00F06 0 +OP4 E00F07 0 +OP4 E00F08 0 +OP4 E00F09 0 +OP4 E00F0A 0 +OP4 E00F0B 0 +OP4 E00F0C 0 +OP4 E00F0D 0 +OP4 E00F0E 0 +OP4 E00F0F 0 +OP4 E00F10 0 +OP4 E00F11 0 +OP4 E00F12 0 +OP4 E00F13 0 +OP4 E00F14 0 +OP4 E00F15 0 +OP4 E00F16 0 +OP4 E00F17 0 +OP4 E00F18 0 +OP4 E00F19 0 +OP4 E00F1A 0 +OP4 E00F1B 0 +OP4 E00F1C 0 +OP4 E00F1D 0 +OP4 E00F1E 0 +OP4 E00F1F 0 +OP4 E00F20 0 +OP4 E00F21 0 +OP4 E00F22 0 +OP4 E00F23 0 +OP4 E00F24 0 +OP4 E00F25 0 +OP4 E00F26 0 +OP4 E00F27 0 +OP4 E00F28 0 +OP4 E00F29 0 +OP4 E00F2A 0 +OP4 E00F2B 0 +OP4 E00F2C 0 +OP4 E00F2D 0 +OP4 E00F2E 0 +OP4 E00F2F 0 +OP4 E00F30 0 diff --git a/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum3_itrace_irisc3.cfg.ext b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum3_itrace_irisc3.cfg.ext new file mode 100644 index 000000000000..0527209426d8 --- /dev/null +++ b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum3_itrace_irisc3.cfg.ext @@ -0,0 +1,3890 @@ +OP1 Spectrum3 +OP4 ITRACE0 0 +OP4 ITRACE1 0 +OP4 ITRACE2 0 +OP4 ITRACE3 1 +OP4 ITRACE4 0 +OP4 ITRACE5 0 +OP4 ITRACE6 0 +OP4 ITRACE7 0 +OP4 ITRACE8 0 +OP4 ITRACE9 0 +OP4 Main_PhyUC 0 +OP4 TILE0_ITRACE0 0 +OP4 TILE0_ITRACE1 0 +OP4 TILE0_ITRACE2 0 +OP4 TILE0_ITRACE3 0 +OP4 TILE0_ITRACE4 0 +OP4 TILE0_PhyUC 0 +OP4 TILE1_ITRACE0 0 +OP4 TILE1_ITRACE1 0 +OP4 TILE1_ITRACE2 0 +OP4 TILE1_ITRACE3 0 +OP4 TILE1_ITRACE4 0 +OP4 TILE1_PhyUC 0 +OP4 TILE2_ITRACE0 0 +OP4 TILE2_ITRACE1 0 +OP4 TILE2_ITRACE2 0 +OP4 TILE2_ITRACE3 0 +OP4 TILE2_ITRACE4 0 +OP4 TILE2_PhyUC 0 +OP4 TILE3_ITRACE0 0 +OP4 TILE3_ITRACE1 0 +OP4 TILE3_ITRACE2 0 +OP4 TILE3_ITRACE3 0 +OP4 TILE3_ITRACE4 0 +OP4 TILE3_PhyUC 0 +OP4 TILE4_ITRACE0 0 +OP4 TILE4_ITRACE1 0 +OP4 TILE4_ITRACE2 0 +OP4 TILE4_ITRACE3 0 +OP4 TILE4_ITRACE4 0 +OP4 TILE4_PhyUC 0 +OP4 TILE5_ITRACE0 0 +OP4 TILE5_ITRACE1 0 +OP4 TILE5_ITRACE2 0 +OP4 TILE5_ITRACE3 0 +OP4 TILE5_ITRACE4 0 +OP4 TILE5_PhyUC 0 +OP4 TILE6_ITRACE0 0 +OP4 TILE6_ITRACE1 0 +OP4 TILE6_ITRACE2 0 +OP4 TILE6_ITRACE3 0 +OP4 TILE6_ITRACE4 0 +OP4 TILE6_PhyUC 0 +OP4 TILE7_ITRACE0 0 +OP4 TILE7_ITRACE1 0 +OP4 TILE7_ITRACE2 0 +OP4 TILE7_ITRACE3 0 +OP4 TILE7_ITRACE4 0 +OP4 TILE7_PhyUC 0 +OP4 E0003B 0 +OP4 E0003C 0 +OP4 E0003D 0 +OP4 E0003E 0 +OP4 E0003F 0 +OP4 E00040 0 +OP4 E00041 0 +OP4 E00042 0 +OP4 E00043 0 +OP4 E00044 0 +OP4 E00045 0 +OP4 E00046 0 +OP4 E00047 0 +OP4 E00048 0 +OP4 E00049 0 +OP4 E0004A 0 +OP4 E0004B 0 +OP4 E0004C 0 +OP4 E0004D 0 +OP4 E0004E 0 +OP4 E0004F 0 +OP4 E00050 0 +OP4 E00051 0 +OP4 E00052 0 +OP4 E00053 0 +OP4 E00054 0 +OP4 E00055 0 +OP4 E00056 0 +OP4 E00057 0 +OP4 E00058 0 +OP4 E00059 0 +OP4 E0005A 0 +OP4 E0005B 0 +OP4 E0005C 0 +OP4 E0005D 0 +OP4 E0005E 0 +OP4 E0005F 0 +OP4 E00060 0 +OP4 E00061 0 +OP4 E00062 0 +OP4 E00063 0 +OP4 E00064 0 +OP4 E00065 0 +OP4 E00066 0 +OP4 E00067 0 +OP4 E00068 0 +OP4 E00069 0 +OP4 E0006A 0 +OP4 E0006B 0 +OP4 E0006C 0 +OP4 E0006D 0 +OP4 E0006E 0 +OP4 E0006F 0 +OP4 E00070 0 +OP4 E00071 0 +OP4 E00072 0 +OP4 E00073 0 +OP4 E00074 0 +OP4 E00075 0 +OP4 E00076 0 +OP4 E00077 0 +OP4 E00078 0 +OP4 E00079 0 +OP4 E0007A 0 +OP4 E0007B 0 +OP4 E0007C 0 +OP4 E0007D 0 +OP4 E0007E 0 +OP4 E0007F 0 +OP4 E00080 0 +OP4 E00081 0 +OP4 E00082 0 +OP4 E00083 0 +OP4 E00084 0 +OP4 E00085 0 +OP4 E00086 0 +OP4 E00087 0 +OP4 E00088 0 +OP4 E00089 0 +OP4 E0008A 0 +OP4 E0008B 0 +OP4 E0008C 0 +OP4 E0008D 0 +OP4 E0008E 0 +OP4 E0008F 0 +OP4 E00090 0 +OP4 E00091 0 +OP4 E00092 0 +OP4 E00093 0 +OP4 E00094 0 +OP4 E00095 0 +OP4 E00096 0 +OP4 E00097 0 +OP4 E00098 0 +OP4 E00099 0 +OP4 E0009A 0 +OP4 E0009B 0 +OP4 E0009C 0 +OP4 E0009D 0 +OP4 E0009E 0 +OP4 E0009F 0 +OP4 E000A0 0 +OP4 E000A1 0 +OP4 E000A2 0 +OP4 E000A3 0 +OP4 E000A4 0 +OP4 E000A5 0 +OP4 E000A6 0 +OP4 E000A7 0 +OP4 E000A8 0 +OP4 E000A9 0 +OP4 E000AA 0 +OP4 E000AB 0 +OP4 E000AC 0 +OP4 E000AD 0 +OP4 E000AE 0 +OP4 E000AF 0 +OP4 E000B0 0 +OP4 E000B1 0 +OP4 E000B2 0 +OP4 E000B3 0 +OP4 E000B4 0 +OP4 E000B5 0 +OP4 E000B6 0 +OP4 E000B7 0 +OP4 E000B8 0 +OP4 E000B9 0 +OP4 E000BA 0 +OP4 E000BB 0 +OP4 E000BC 0 +OP4 E000BD 0 +OP4 E000BE 0 +OP4 E000BF 0 +OP4 E000C0 0 +OP4 E000C1 0 +OP4 E000C2 0 +OP4 E000C3 0 +OP4 E000C4 0 +OP4 E000C5 0 +OP4 E000C6 0 +OP4 E000C7 0 +OP4 E000C8 0 +OP4 E000C9 0 +OP4 E000CA 0 +OP4 E000CB 0 +OP4 E000CC 0 +OP4 E000CD 0 +OP4 E000CE 0 +OP4 E000CF 0 +OP4 E000D0 0 +OP4 E000D1 0 +OP4 E000D2 0 +OP4 E000D3 0 +OP4 E000D4 0 +OP4 E000D5 0 +OP4 E000D6 0 +OP4 E000D7 0 +OP4 E000D8 0 +OP4 E000D9 0 +OP4 E000DA 0 +OP4 E000DB 0 +OP4 E000DC 0 +OP4 E000DD 0 +OP4 E000DE 0 +OP4 E000DF 0 +OP4 E000E0 0 +OP4 E000E1 0 +OP4 E000E2 0 +OP4 E000E3 0 +OP4 E000E4 0 +OP4 E000E5 0 +OP4 E000E6 0 +OP4 E000E7 0 +OP4 E000E8 0 +OP4 E000E9 0 +OP4 E000EA 0 +OP4 E000EB 0 +OP4 E000EC 0 +OP4 E000ED 0 +OP4 E000EE 0 +OP4 E000EF 0 +OP4 E000F0 0 +OP4 E000F1 0 +OP4 E000F2 0 +OP4 E000F3 0 +OP4 E000F4 0 +OP4 E000F5 0 +OP4 E000F6 0 +OP4 E000F7 0 +OP4 E000F8 0 +OP4 E000F9 0 +OP4 E000FA 0 +OP4 E000FB 0 +OP4 E000FC 0 +OP4 E000FD 0 +OP4 E000FE 0 +OP4 E000FF 0 +OP4 E00100 0 +OP4 E00101 0 +OP4 E00102 0 +OP4 E00103 0 +OP4 E00104 0 +OP4 E00105 0 +OP4 E00106 0 +OP4 E00107 0 +OP4 E00108 0 +OP4 E00109 0 +OP4 E0010A 0 +OP4 E0010B 0 +OP4 E0010C 0 +OP4 E0010D 0 +OP4 E0010E 0 +OP4 E0010F 0 +OP4 E00110 0 +OP4 E00111 0 +OP4 E00112 0 +OP4 E00113 0 +OP4 E00114 0 +OP4 E00115 0 +OP4 E00116 0 +OP4 E00117 0 +OP4 E00118 0 +OP4 E00119 0 +OP4 E0011A 0 +OP4 E0011B 0 +OP4 E0011C 0 +OP4 E0011D 0 +OP4 E0011E 0 +OP4 E0011F 0 +OP4 E00120 0 +OP4 E00121 0 +OP4 E00122 0 +OP4 E00123 0 +OP4 E00124 0 +OP4 E00125 0 +OP4 E00126 0 +OP4 E00127 0 +OP4 E00128 0 +OP4 E00129 0 +OP4 E0012A 0 +OP4 E0012B 0 +OP4 E0012C 0 +OP4 E0012D 0 +OP4 E0012E 0 +OP4 E0012F 0 +OP4 E00130 0 +OP4 E00131 0 +OP4 E00132 0 +OP4 E00133 0 +OP4 E00134 0 +OP4 E00135 0 +OP4 E00136 0 +OP4 E00137 0 +OP4 E00138 0 +OP4 E00139 0 +OP4 E0013A 0 +OP4 E0013B 0 +OP4 E0013C 0 +OP4 E0013D 0 +OP4 E0013E 0 +OP4 E0013F 0 +OP4 E00140 0 +OP4 E00141 0 +OP4 E00142 0 +OP4 E00143 0 +OP4 E00144 0 +OP4 E00145 0 +OP4 E00146 0 +OP4 E00147 0 +OP4 E00148 0 +OP4 E00149 0 +OP4 E0014A 0 +OP4 E0014B 0 +OP4 E0014C 0 +OP4 E0014D 0 +OP4 E0014E 0 +OP4 E0014F 0 +OP4 E00150 0 +OP4 E00151 0 +OP4 E00152 0 +OP4 E00153 0 +OP4 E00154 0 +OP4 E00155 0 +OP4 E00156 0 +OP4 E00157 0 +OP4 E00158 0 +OP4 E00159 0 +OP4 E0015A 0 +OP4 E0015B 0 +OP4 E0015C 0 +OP4 E0015D 0 +OP4 E0015E 0 +OP4 E0015F 0 +OP4 E00160 0 +OP4 E00161 0 +OP4 E00162 0 +OP4 E00163 0 +OP4 E00164 0 +OP4 E00165 0 +OP4 E00166 0 +OP4 E00167 0 +OP4 E00168 0 +OP4 E00169 0 +OP4 E0016A 0 +OP4 E0016B 0 +OP4 E0016C 0 +OP4 E0016D 0 +OP4 E0016E 0 +OP4 E0016F 0 +OP4 E00170 0 +OP4 E00171 0 +OP4 E00172 0 +OP4 E00173 0 +OP4 E00174 0 +OP4 E00175 0 +OP4 E00176 0 +OP4 E00177 0 +OP4 E00178 0 +OP4 E00179 0 +OP4 E0017A 0 +OP4 E0017B 0 +OP4 E0017C 0 +OP4 E0017D 0 +OP4 E0017E 0 +OP4 E0017F 0 +OP4 E00180 0 +OP4 E00181 0 +OP4 E00182 0 +OP4 E00183 0 +OP4 E00184 0 +OP4 E00185 0 +OP4 E00186 0 +OP4 E00187 0 +OP4 E00188 0 +OP4 E00189 0 +OP4 E0018A 0 +OP4 E0018B 0 +OP4 E0018C 0 +OP4 E0018D 0 +OP4 E0018E 0 +OP4 E0018F 0 +OP4 E00190 0 +OP4 E00191 0 +OP4 E00192 0 +OP4 E00193 0 +OP4 E00194 0 +OP4 E00195 0 +OP4 E00196 0 +OP4 E00197 0 +OP4 E00198 0 +OP4 E00199 0 +OP4 E0019A 0 +OP4 E0019B 0 +OP4 E0019C 0 +OP4 E0019D 0 +OP4 E0019E 0 +OP4 E0019F 0 +OP4 E001A0 0 +OP4 E001A1 0 +OP4 E001A2 0 +OP4 E001A3 0 +OP4 E001A4 0 +OP4 E001A5 0 +OP4 E001A6 0 +OP4 E001A7 0 +OP4 E001A8 0 +OP4 E001A9 0 +OP4 E001AA 0 +OP4 E001AB 0 +OP4 E001AC 0 +OP4 E001AD 0 +OP4 E001AE 0 +OP4 E001AF 0 +OP4 E001B0 0 +OP4 E001B1 0 +OP4 E001B2 0 +OP4 E001B3 0 +OP4 E001B4 0 +OP4 E001B5 0 +OP4 E001B6 0 +OP4 E001B7 0 +OP4 E001B8 0 +OP4 E001B9 0 +OP4 E001BA 0 +OP4 E001BB 0 +OP4 E001BC 0 +OP4 E001BD 0 +OP4 E001BE 0 +OP4 E001BF 0 +OP4 E001C0 0 +OP4 E001C1 0 +OP4 E001C2 0 +OP4 E001C3 0 +OP4 E001C4 0 +OP4 E001C5 0 +OP4 E001C6 0 +OP4 E001C7 0 +OP4 E001C8 0 +OP4 E001C9 0 +OP4 E001CA 0 +OP4 E001CB 0 +OP4 E001CC 0 +OP4 E001CD 0 +OP4 E001CE 0 +OP4 E001CF 0 +OP4 E001D0 0 +OP4 E001D1 0 +OP4 E001D2 0 +OP4 E001D3 0 +OP4 E001D4 0 +OP4 E001D5 0 +OP4 E001D6 0 +OP4 E001D7 0 +OP4 E001D8 0 +OP4 E001D9 0 +OP4 E001DA 0 +OP4 E001DB 0 +OP4 E001DC 0 +OP4 E001DD 0 +OP4 E001DE 0 +OP4 E001DF 0 +OP4 E001E0 0 +OP4 E001E1 0 +OP4 E001E2 0 +OP4 E001E3 0 +OP4 E001E4 0 +OP4 E001E5 0 +OP4 E001E6 0 +OP4 E001E7 0 +OP4 E001E8 0 +OP4 E001E9 0 +OP4 E001EA 0 +OP4 E001EB 0 +OP4 E001EC 0 +OP4 E001ED 0 +OP4 E001EE 0 +OP4 E001EF 0 +OP4 E001F0 0 +OP4 E001F1 0 +OP4 E001F2 0 +OP4 E001F3 0 +OP4 E001F4 0 +OP4 E001F5 0 +OP4 E001F6 0 +OP4 E001F7 0 +OP4 E001F8 0 +OP4 E001F9 0 +OP4 E001FA 0 +OP4 E001FB 0 +OP4 E001FC 0 +OP4 E001FD 0 +OP4 E001FE 0 +OP4 E001FF 0 +OP4 E00200 0 +OP4 E00201 0 +OP4 E00202 0 +OP4 E00203 0 +OP4 E00204 0 +OP4 E00205 0 +OP4 E00206 0 +OP4 E00207 0 +OP4 E00208 0 +OP4 E00209 0 +OP4 E0020A 0 +OP4 E0020B 0 +OP4 E0020C 0 +OP4 E0020D 0 +OP4 E0020E 0 +OP4 E0020F 0 +OP4 E00210 0 +OP4 E00211 0 +OP4 E00212 0 +OP4 E00213 0 +OP4 E00214 0 +OP4 E00215 0 +OP4 E00216 0 +OP4 E00217 0 +OP4 E00218 0 +OP4 E00219 0 +OP4 E0021A 0 +OP4 E0021B 0 +OP4 E0021C 0 +OP4 E0021D 0 +OP4 E0021E 0 +OP4 E0021F 0 +OP4 E00220 0 +OP4 E00221 0 +OP4 E00222 0 +OP4 E00223 0 +OP4 E00224 0 +OP4 E00225 0 +OP4 E00226 0 +OP4 E00227 0 +OP4 E00228 0 +OP4 E00229 0 +OP4 E0022A 0 +OP4 E0022B 0 +OP4 E0022C 0 +OP4 E0022D 0 +OP4 E0022E 0 +OP4 E0022F 0 +OP4 E00230 0 +OP4 E00231 0 +OP4 E00232 0 +OP4 E00233 0 +OP4 E00234 0 +OP4 E00235 0 +OP4 E00236 0 +OP4 E00237 0 +OP4 E00238 0 +OP4 E00239 0 +OP4 E0023A 0 +OP4 E0023B 0 +OP4 E0023C 0 +OP4 E0023D 0 +OP4 E0023E 0 +OP4 E0023F 0 +OP4 E00240 0 +OP4 E00241 0 +OP4 E00242 0 +OP4 E00243 0 +OP4 E00244 0 +OP4 E00245 0 +OP4 E00246 0 +OP4 E00247 0 +OP4 E00248 0 +OP4 E00249 0 +OP4 E0024A 0 +OP4 E0024B 0 +OP4 E0024C 0 +OP4 E0024D 0 +OP4 E0024E 0 +OP4 E0024F 0 +OP4 E00250 0 +OP4 E00251 0 +OP4 E00252 0 +OP4 E00253 0 +OP4 E00254 0 +OP4 E00255 0 +OP4 E00256 0 +OP4 E00257 0 +OP4 E00258 0 +OP4 E00259 0 +OP4 E0025A 0 +OP4 E0025B 0 +OP4 E0025C 0 +OP4 E0025D 0 +OP4 E0025E 0 +OP4 E0025F 0 +OP4 E00260 0 +OP4 E00261 0 +OP4 E00262 0 +OP4 E00263 0 +OP4 E00264 0 +OP4 E00265 0 +OP4 E00266 0 +OP4 E00267 0 +OP4 E00268 0 +OP4 E00269 0 +OP4 E0026A 0 +OP4 E0026B 0 +OP4 E0026C 0 +OP4 E0026D 0 +OP4 E0026E 0 +OP4 E0026F 0 +OP4 E00270 0 +OP4 E00271 0 +OP4 E00272 0 +OP4 E00273 0 +OP4 E00274 0 +OP4 E00275 0 +OP4 E00276 0 +OP4 E00277 0 +OP4 E00278 0 +OP4 E00279 0 +OP4 E0027A 0 +OP4 E0027B 0 +OP4 E0027C 0 +OP4 E0027D 0 +OP4 E0027E 0 +OP4 E0027F 0 +OP4 E00280 0 +OP4 E00281 0 +OP4 E00282 0 +OP4 E00283 0 +OP4 E00284 0 +OP4 E00285 0 +OP4 E00286 0 +OP4 E00287 0 +OP4 E00288 0 +OP4 E00289 0 +OP4 E0028A 0 +OP4 E0028B 0 +OP4 E0028C 0 +OP4 E0028D 0 +OP4 E0028E 0 +OP4 E0028F 0 +OP4 E00290 0 +OP4 E00291 0 +OP4 E00292 0 +OP4 E00293 0 +OP4 E00294 0 +OP4 E00295 0 +OP4 E00296 0 +OP4 E00297 0 +OP4 E00298 0 +OP4 E00299 0 +OP4 E0029A 0 +OP4 E0029B 0 +OP4 E0029C 0 +OP4 E0029D 0 +OP4 E0029E 0 +OP4 E0029F 0 +OP4 E002A0 0 +OP4 E002A1 0 +OP4 E002A2 0 +OP4 E002A3 0 +OP4 E002A4 0 +OP4 E002A5 0 +OP4 E002A6 0 +OP4 E002A7 0 +OP4 E002A8 0 +OP4 E002A9 0 +OP4 E002AA 0 +OP4 E002AB 0 +OP4 E002AC 0 +OP4 E002AD 0 +OP4 E002AE 0 +OP4 E002AF 0 +OP4 E002B0 0 +OP4 E002B1 0 +OP4 E002B2 0 +OP4 E002B3 0 +OP4 E002B4 0 +OP4 E002B5 0 +OP4 E002B6 0 +OP4 E002B7 0 +OP4 E002B8 0 +OP4 E002B9 0 +OP4 E002BA 0 +OP4 E002BB 0 +OP4 E002BC 0 +OP4 E002BD 0 +OP4 E002BE 0 +OP4 E002BF 0 +OP4 E002C0 0 +OP4 E002C1 0 +OP4 E002C2 0 +OP4 E002C3 0 +OP4 E002C4 0 +OP4 E002C5 0 +OP4 E002C6 0 +OP4 E002C7 0 +OP4 E002C8 0 +OP4 E002C9 0 +OP4 E002CA 0 +OP4 E002CB 0 +OP4 E002CC 0 +OP4 E002CD 0 +OP4 E002CE 0 +OP4 E002CF 0 +OP4 E002D0 0 +OP4 E002D1 0 +OP4 E002D2 0 +OP4 E002D3 0 +OP4 E002D4 0 +OP4 E002D5 0 +OP4 E002D6 0 +OP4 E002D7 0 +OP4 E002D8 0 +OP4 E002D9 0 +OP4 E002DA 0 +OP4 E002DB 0 +OP4 E002DC 0 +OP4 E002DD 0 +OP4 E002DE 0 +OP4 E002DF 0 +OP4 E002E0 0 +OP4 E002E1 0 +OP4 E002E2 0 +OP4 E002E3 0 +OP4 E002E4 0 +OP4 E002E5 0 +OP4 E002E6 0 +OP4 E002E7 0 +OP4 E002E8 0 +OP4 E002E9 0 +OP4 E002EA 0 +OP4 E002EB 0 +OP4 E002EC 0 +OP4 E002ED 0 +OP4 E002EE 0 +OP4 E002EF 0 +OP4 E002F0 0 +OP4 E002F1 0 +OP4 E002F2 0 +OP4 E002F3 0 +OP4 E002F4 0 +OP4 E002F5 0 +OP4 E002F6 0 +OP4 E002F7 0 +OP4 E002F8 0 +OP4 E002F9 0 +OP4 E002FA 0 +OP4 E002FB 0 +OP4 E002FC 0 +OP4 E002FD 0 +OP4 E002FE 0 +OP4 E002FF 0 +OP4 E00300 0 +OP4 E00301 0 +OP4 E00302 0 +OP4 E00303 0 +OP4 E00304 0 +OP4 E00305 0 +OP4 E00306 0 +OP4 E00307 0 +OP4 E00308 0 +OP4 E00309 0 +OP4 E0030A 0 +OP4 E0030B 0 +OP4 E0030C 0 +OP4 E0030D 0 +OP4 E0030E 0 +OP4 E0030F 0 +OP4 E00310 0 +OP4 E00311 0 +OP4 E00312 0 +OP4 E00313 0 +OP4 E00314 0 +OP4 E00315 0 +OP4 E00316 0 +OP4 E00317 0 +OP4 E00318 0 +OP4 E00319 0 +OP4 E0031A 0 +OP4 E0031B 0 +OP4 E0031C 0 +OP4 E0031D 0 +OP4 E0031E 0 +OP4 E0031F 0 +OP4 E00320 0 +OP4 E00321 0 +OP4 E00322 0 +OP4 E00323 0 +OP4 E00324 0 +OP4 E00325 0 +OP4 E00326 0 +OP4 E00327 0 +OP4 E00328 0 +OP4 E00329 0 +OP4 E0032A 0 +OP4 E0032B 0 +OP4 E0032C 0 +OP4 E0032D 0 +OP4 E0032E 0 +OP4 E0032F 0 +OP4 E00330 0 +OP4 E00331 0 +OP4 E00332 0 +OP4 E00333 0 +OP4 E00334 0 +OP4 E00335 0 +OP4 E00336 0 +OP4 E00337 0 +OP4 E00338 0 +OP4 E00339 0 +OP4 E0033A 0 +OP4 E0033B 0 +OP4 E0033C 0 +OP4 E0033D 0 +OP4 E0033E 0 +OP4 E0033F 0 +OP4 E00340 0 +OP4 E00341 0 +OP4 E00342 0 +OP4 E00343 0 +OP4 E00344 0 +OP4 E00345 0 +OP4 E00346 0 +OP4 E00347 0 +OP4 E00348 0 +OP4 E00349 0 +OP4 E0034A 0 +OP4 E0034B 0 +OP4 E0034C 0 +OP4 E0034D 0 +OP4 E0034E 0 +OP4 E0034F 0 +OP4 E00350 0 +OP4 E00351 0 +OP4 E00352 0 +OP4 E00353 0 +OP4 E00354 0 +OP4 E00355 0 +OP4 E00356 0 +OP4 E00357 0 +OP4 E00358 0 +OP4 E00359 0 +OP4 E0035A 0 +OP4 E0035B 0 +OP4 E0035C 0 +OP4 E0035D 0 +OP4 E0035E 0 +OP4 E0035F 0 +OP4 E00360 0 +OP4 E00361 0 +OP4 E00362 0 +OP4 E00363 0 +OP4 E00364 0 +OP4 E00365 0 +OP4 E00366 0 +OP4 E00367 0 +OP4 E00368 0 +OP4 E00369 0 +OP4 E0036A 0 +OP4 E0036B 0 +OP4 E0036C 0 +OP4 E0036D 0 +OP4 E0036E 0 +OP4 E0036F 0 +OP4 E00370 0 +OP4 E00371 0 +OP4 E00372 0 +OP4 E00373 0 +OP4 E00374 0 +OP4 E00375 0 +OP4 E00376 0 +OP4 E00377 0 +OP4 E00378 0 +OP4 E00379 0 +OP4 E0037A 0 +OP4 E0037B 0 +OP4 E0037C 0 +OP4 E0037D 0 +OP4 E0037E 0 +OP4 E0037F 0 +OP4 E00380 0 +OP4 E00381 0 +OP4 E00382 0 +OP4 E00383 0 +OP4 E00384 0 +OP4 E00385 0 +OP4 E00386 0 +OP4 E00387 0 +OP4 E00388 0 +OP4 E00389 0 +OP4 E0038A 0 +OP4 E0038B 0 +OP4 E0038C 0 +OP4 E0038D 0 +OP4 E0038E 0 +OP4 E0038F 0 +OP4 E00390 0 +OP4 E00391 0 +OP4 E00392 0 +OP4 E00393 0 +OP4 E00394 0 +OP4 E00395 0 +OP4 E00396 0 +OP4 E00397 0 +OP4 E00398 0 +OP4 E00399 0 +OP4 E0039A 0 +OP4 E0039B 0 +OP4 E0039C 0 +OP4 E0039D 0 +OP4 E0039E 0 +OP4 E0039F 0 +OP4 E003A0 0 +OP4 E003A1 0 +OP4 E003A2 0 +OP4 E003A3 0 +OP4 E003A4 0 +OP4 E003A5 0 +OP4 E003A6 0 +OP4 E003A7 0 +OP4 E003A8 0 +OP4 E003A9 0 +OP4 E003AA 0 +OP4 E003AB 0 +OP4 E003AC 0 +OP4 E003AD 0 +OP4 E003AE 0 +OP4 E003AF 0 +OP4 E003B0 0 +OP4 E003B1 0 +OP4 E003B2 0 +OP4 E003B3 0 +OP4 E003B4 0 +OP4 E003B5 0 +OP4 E003B6 0 +OP4 E003B7 0 +OP4 E003B8 0 +OP4 E003B9 0 +OP4 E003BA 0 +OP4 E003BB 0 +OP4 E003BC 0 +OP4 E003BD 0 +OP4 E003BE 0 +OP4 E003BF 0 +OP4 E003C0 0 +OP4 E003C1 0 +OP4 E003C2 0 +OP4 E003C3 0 +OP4 E003C4 0 +OP4 E003C5 0 +OP4 E003C6 0 +OP4 E003C7 0 +OP4 E003C8 0 +OP4 E003C9 0 +OP4 E003CA 0 +OP4 E003CB 0 +OP4 E003CC 0 +OP4 E003CD 0 +OP4 E003CE 0 +OP4 E003CF 0 +OP4 E003D0 0 +OP4 E003D1 0 +OP4 E003D2 0 +OP4 E003D3 0 +OP4 E003D4 0 +OP4 E003D5 0 +OP4 E003D6 0 +OP4 E003D7 0 +OP4 E003D8 0 +OP4 E003D9 0 +OP4 E003DA 0 +OP4 E003DB 0 +OP4 E003DC 0 +OP4 E003DD 0 +OP4 E003DE 0 +OP4 E003DF 0 +OP4 E003E0 0 +OP4 E003E1 0 +OP4 E003E2 0 +OP4 E003E3 0 +OP4 E003E4 0 +OP4 E003E5 0 +OP4 E003E6 0 +OP4 E003E7 0 +OP4 E003E8 0 +OP4 E003E9 0 +OP4 E003EA 0 +OP4 E003EB 0 +OP4 E003EC 0 +OP4 E003ED 0 +OP4 E003EE 0 +OP4 E003EF 0 +OP4 E003F0 0 +OP4 E003F1 0 +OP4 E003F2 0 +OP4 E003F3 0 +OP4 E003F4 0 +OP4 E003F5 0 +OP4 E003F6 0 +OP4 E003F7 0 +OP4 E003F8 0 +OP4 E003F9 0 +OP4 E003FA 0 +OP4 E003FB 0 +OP4 E003FC 0 +OP4 E003FD 0 +OP4 E003FE 0 +OP4 E003FF 0 +OP4 E00400 0 +OP4 E00401 0 +OP4 E00402 0 +OP4 E00403 0 +OP4 E00404 0 +OP4 E00405 0 +OP4 E00406 0 +OP4 E00407 0 +OP4 E00408 0 +OP4 E00409 0 +OP4 E0040A 0 +OP4 E0040B 0 +OP4 E0040C 0 +OP4 E0040D 0 +OP4 E0040E 0 +OP4 E0040F 0 +OP4 E00410 0 +OP4 E00411 0 +OP4 E00412 0 +OP4 E00413 0 +OP4 E00414 0 +OP4 E00415 0 +OP4 E00416 0 +OP4 E00417 0 +OP4 E00418 0 +OP4 E00419 0 +OP4 E0041A 0 +OP4 E0041B 0 +OP4 E0041C 0 +OP4 E0041D 0 +OP4 E0041E 0 +OP4 E0041F 0 +OP4 E00420 0 +OP4 E00421 0 +OP4 E00422 0 +OP4 E00423 0 +OP4 E00424 0 +OP4 E00425 0 +OP4 E00426 0 +OP4 E00427 0 +OP4 E00428 0 +OP4 E00429 0 +OP4 E0042A 0 +OP4 E0042B 0 +OP4 E0042C 0 +OP4 E0042D 0 +OP4 E0042E 0 +OP4 E0042F 0 +OP4 E00430 0 +OP4 E00431 0 +OP4 E00432 0 +OP4 E00433 0 +OP4 E00434 0 +OP4 E00435 0 +OP4 E00436 0 +OP4 E00437 0 +OP4 E00438 0 +OP4 E00439 0 +OP4 E0043A 0 +OP4 E0043B 0 +OP4 E0043C 0 +OP4 E0043D 0 +OP4 E0043E 0 +OP4 E0043F 0 +OP4 E00440 0 +OP4 E00441 0 +OP4 E00442 0 +OP4 E00443 0 +OP4 E00444 0 +OP4 E00445 0 +OP4 E00446 0 +OP4 E00447 0 +OP4 E00448 0 +OP4 E00449 0 +OP4 E0044A 0 +OP4 E0044B 0 +OP4 E0044C 0 +OP4 E0044D 0 +OP4 E0044E 0 +OP4 E0044F 0 +OP4 E00450 0 +OP4 E00451 0 +OP4 E00452 0 +OP4 E00453 0 +OP4 E00454 0 +OP4 E00455 0 +OP4 E00456 0 +OP4 E00457 0 +OP4 E00458 0 +OP4 E00459 0 +OP4 E0045A 0 +OP4 E0045B 0 +OP4 E0045C 0 +OP4 E0045D 0 +OP4 E0045E 0 +OP4 E0045F 0 +OP4 E00460 0 +OP4 E00461 0 +OP4 E00462 0 +OP4 E00463 0 +OP4 E00464 0 +OP4 E00465 0 +OP4 E00466 0 +OP4 E00467 0 +OP4 E00468 0 +OP4 E00469 0 +OP4 E0046A 0 +OP4 E0046B 0 +OP4 E0046C 0 +OP4 E0046D 0 +OP4 E0046E 0 +OP4 E0046F 0 +OP4 E00470 0 +OP4 E00471 0 +OP4 E00472 0 +OP4 E00473 0 +OP4 E00474 0 +OP4 E00475 0 +OP4 E00476 0 +OP4 E00477 0 +OP4 E00478 0 +OP4 E00479 0 +OP4 E0047A 0 +OP4 E0047B 0 +OP4 E0047C 0 +OP4 E0047D 0 +OP4 E0047E 0 +OP4 E0047F 0 +OP4 E00480 0 +OP4 E00481 0 +OP4 E00482 0 +OP4 E00483 0 +OP4 E00484 0 +OP4 E00485 0 +OP4 E00486 0 +OP4 E00487 0 +OP4 E00488 0 +OP4 E00489 0 +OP4 E0048A 0 +OP4 E0048B 0 +OP4 E0048C 0 +OP4 E0048D 0 +OP4 E0048E 0 +OP4 E0048F 0 +OP4 E00490 0 +OP4 E00491 0 +OP4 E00492 0 +OP4 E00493 0 +OP4 E00494 0 +OP4 E00495 0 +OP4 E00496 0 +OP4 E00497 0 +OP4 E00498 0 +OP4 E00499 0 +OP4 E0049A 0 +OP4 E0049B 0 +OP4 E0049C 0 +OP4 E0049D 0 +OP4 E0049E 0 +OP4 E0049F 0 +OP4 E004A0 0 +OP4 E004A1 0 +OP4 E004A2 0 +OP4 E004A3 0 +OP4 E004A4 0 +OP4 E004A5 0 +OP4 E004A6 0 +OP4 E004A7 0 +OP4 E004A8 0 +OP4 E004A9 0 +OP4 E004AA 0 +OP4 E004AB 0 +OP4 E004AC 0 +OP4 E004AD 0 +OP4 E004AE 0 +OP4 E004AF 0 +OP4 E004B0 0 +OP4 E004B1 0 +OP4 E004B2 0 +OP4 E004B3 0 +OP4 E004B4 0 +OP4 E004B5 0 +OP4 E004B6 0 +OP4 E004B7 0 +OP4 E004B8 0 +OP4 E004B9 0 +OP4 E004BA 0 +OP4 E004BB 0 +OP4 E004BC 0 +OP4 E004BD 0 +OP4 E004BE 0 +OP4 E004BF 0 +OP4 E004C0 0 +OP4 E004C1 0 +OP4 E004C2 0 +OP4 E004C3 0 +OP4 E004C4 0 +OP4 E004C5 0 +OP4 E004C6 0 +OP4 E004C7 0 +OP4 E004C8 0 +OP4 E004C9 0 +OP4 E004CA 0 +OP4 E004CB 0 +OP4 E004CC 0 +OP4 E004CD 0 +OP4 E004CE 0 +OP4 E004CF 0 +OP4 E004D0 0 +OP4 E004D1 0 +OP4 E004D2 0 +OP4 E004D3 0 +OP4 E004D4 0 +OP4 E004D5 0 +OP4 E004D6 0 +OP4 E004D7 0 +OP4 E004D8 0 +OP4 E004D9 0 +OP4 E004DA 0 +OP4 E004DB 0 +OP4 E004DC 0 +OP4 E004DD 0 +OP4 E004DE 0 +OP4 E004DF 0 +OP4 E004E0 0 +OP4 E004E1 0 +OP4 E004E2 0 +OP4 E004E3 0 +OP4 E004E4 0 +OP4 E004E5 0 +OP4 E004E6 0 +OP4 E004E7 0 +OP4 E004E8 0 +OP4 E004E9 0 +OP4 E004EA 0 +OP4 E004EB 0 +OP4 E004EC 0 +OP4 E004ED 0 +OP4 E004EE 0 +OP4 E004EF 0 +OP4 E004F0 0 +OP4 E004F1 0 +OP4 E004F2 0 +OP4 E004F3 0 +OP4 E004F4 0 +OP4 E004F5 0 +OP4 E004F6 0 +OP4 E004F7 0 +OP4 E004F8 0 +OP4 E004F9 0 +OP4 E004FA 0 +OP4 E004FB 0 +OP4 E004FC 0 +OP4 E004FD 0 +OP4 E004FE 0 +OP4 E004FF 0 +OP4 E00500 0 +OP4 E00501 0 +OP4 E00502 0 +OP4 E00503 0 +OP4 E00504 0 +OP4 E00505 0 +OP4 E00506 0 +OP4 E00507 0 +OP4 E00508 0 +OP4 E00509 0 +OP4 E0050A 0 +OP4 E0050B 0 +OP4 E0050C 0 +OP4 E0050D 0 +OP4 E0050E 0 +OP4 E0050F 0 +OP4 E00510 0 +OP4 E00511 0 +OP4 E00512 0 +OP4 E00513 0 +OP4 E00514 0 +OP4 E00515 0 +OP4 E00516 0 +OP4 E00517 0 +OP4 E00518 0 +OP4 E00519 0 +OP4 E0051A 0 +OP4 E0051B 0 +OP4 E0051C 0 +OP4 E0051D 0 +OP4 E0051E 0 +OP4 E0051F 0 +OP4 E00520 0 +OP4 E00521 0 +OP4 E00522 0 +OP4 E00523 0 +OP4 E00524 0 +OP4 E00525 0 +OP4 E00526 0 +OP4 E00527 0 +OP4 E00528 0 +OP4 E00529 0 +OP4 E0052A 0 +OP4 E0052B 0 +OP4 E0052C 0 +OP4 E0052D 0 +OP4 E0052E 0 +OP4 E0052F 0 +OP4 E00530 0 +OP4 E00531 0 +OP4 E00532 0 +OP4 E00533 0 +OP4 E00534 0 +OP4 E00535 0 +OP4 E00536 0 +OP4 E00537 0 +OP4 E00538 0 +OP4 E00539 0 +OP4 E0053A 0 +OP4 E0053B 0 +OP4 E0053C 0 +OP4 E0053D 0 +OP4 E0053E 0 +OP4 E0053F 0 +OP4 E00540 0 +OP4 E00541 0 +OP4 E00542 0 +OP4 E00543 0 +OP4 E00544 0 +OP4 E00545 0 +OP4 E00546 0 +OP4 E00547 0 +OP4 E00548 0 +OP4 E00549 0 +OP4 E0054A 0 +OP4 E0054B 0 +OP4 E0054C 0 +OP4 E0054D 0 +OP4 E0054E 0 +OP4 E0054F 0 +OP4 E00550 0 +OP4 E00551 0 +OP4 E00552 0 +OP4 E00553 0 +OP4 E00554 0 +OP4 E00555 0 +OP4 E00556 0 +OP4 E00557 0 +OP4 E00558 0 +OP4 E00559 0 +OP4 E0055A 0 +OP4 E0055B 0 +OP4 E0055C 0 +OP4 E0055D 0 +OP4 E0055E 0 +OP4 E0055F 0 +OP4 E00560 0 +OP4 E00561 0 +OP4 E00562 0 +OP4 E00563 0 +OP4 E00564 0 +OP4 E00565 0 +OP4 E00566 0 +OP4 E00567 0 +OP4 E00568 0 +OP4 E00569 0 +OP4 E0056A 0 +OP4 E0056B 0 +OP4 E0056C 0 +OP4 E0056D 0 +OP4 E0056E 0 +OP4 E0056F 0 +OP4 E00570 0 +OP4 E00571 0 +OP4 E00572 0 +OP4 E00573 0 +OP4 E00574 0 +OP4 E00575 0 +OP4 E00576 0 +OP4 E00577 0 +OP4 E00578 0 +OP4 E00579 0 +OP4 E0057A 0 +OP4 E0057B 0 +OP4 E0057C 0 +OP4 E0057D 0 +OP4 E0057E 0 +OP4 E0057F 0 +OP4 E00580 0 +OP4 E00581 0 +OP4 E00582 0 +OP4 E00583 0 +OP4 E00584 0 +OP4 E00585 0 +OP4 E00586 0 +OP4 E00587 0 +OP4 E00588 0 +OP4 E00589 0 +OP4 E0058A 0 +OP4 E0058B 0 +OP4 E0058C 0 +OP4 E0058D 0 +OP4 E0058E 0 +OP4 E0058F 0 +OP4 E00590 0 +OP4 E00591 0 +OP4 E00592 0 +OP4 E00593 0 +OP4 E00594 0 +OP4 E00595 0 +OP4 E00596 0 +OP4 E00597 0 +OP4 E00598 0 +OP4 E00599 0 +OP4 E0059A 0 +OP4 E0059B 0 +OP4 E0059C 0 +OP4 E0059D 0 +OP4 E0059E 0 +OP4 E0059F 0 +OP4 E005A0 0 +OP4 E005A1 0 +OP4 E005A2 0 +OP4 E005A3 0 +OP4 E005A4 0 +OP4 E005A5 0 +OP4 E005A6 0 +OP4 E005A7 0 +OP4 E005A8 0 +OP4 E005A9 0 +OP4 E005AA 0 +OP4 E005AB 0 +OP4 E005AC 0 +OP4 E005AD 0 +OP4 E005AE 0 +OP4 E005AF 0 +OP4 E005B0 0 +OP4 E005B1 0 +OP4 E005B2 0 +OP4 E005B3 0 +OP4 E005B4 0 +OP4 E005B5 0 +OP4 E005B6 0 +OP4 E005B7 0 +OP4 E005B8 0 +OP4 E005B9 0 +OP4 E005BA 0 +OP4 E005BB 0 +OP4 E005BC 0 +OP4 E005BD 0 +OP4 E005BE 0 +OP4 E005BF 0 +OP4 E005C0 0 +OP4 E005C1 0 +OP4 E005C2 0 +OP4 E005C3 0 +OP4 E005C4 0 +OP4 E005C5 0 +OP4 E005C6 0 +OP4 E005C7 0 +OP4 E005C8 0 +OP4 E005C9 0 +OP4 E005CA 0 +OP4 E005CB 0 +OP4 E005CC 0 +OP4 E005CD 0 +OP4 E005CE 0 +OP4 E005CF 0 +OP4 E005D0 0 +OP4 E005D1 0 +OP4 E005D2 0 +OP4 E005D3 0 +OP4 E005D4 0 +OP4 E005D5 0 +OP4 E005D6 0 +OP4 E005D7 0 +OP4 E005D8 0 +OP4 E005D9 0 +OP4 E005DA 0 +OP4 E005DB 0 +OP4 E005DC 0 +OP4 E005DD 0 +OP4 E005DE 0 +OP4 E005DF 0 +OP4 E005E0 0 +OP4 E005E1 0 +OP4 E005E2 0 +OP4 E005E3 0 +OP4 E005E4 0 +OP4 E005E5 0 +OP4 E005E6 0 +OP4 E005E7 0 +OP4 E005E8 0 +OP4 E005E9 0 +OP4 E005EA 0 +OP4 E005EB 0 +OP4 E005EC 0 +OP4 E005ED 0 +OP4 E005EE 0 +OP4 E005EF 0 +OP4 E005F0 0 +OP4 E005F1 0 +OP4 E005F2 0 +OP4 E005F3 0 +OP4 E005F4 0 +OP4 E005F5 0 +OP4 E005F6 0 +OP4 E005F7 0 +OP4 E005F8 0 +OP4 E005F9 0 +OP4 E005FA 0 +OP4 E005FB 0 +OP4 E005FC 0 +OP4 E005FD 0 +OP4 E005FE 0 +OP4 E005FF 0 +OP4 E00600 0 +OP4 E00601 0 +OP4 E00602 0 +OP4 E00603 0 +OP4 E00604 0 +OP4 E00605 0 +OP4 E00606 0 +OP4 E00607 0 +OP4 E00608 0 +OP4 E00609 0 +OP4 E0060A 0 +OP4 E0060B 0 +OP4 E0060C 0 +OP4 E0060D 0 +OP4 E0060E 0 +OP4 E0060F 0 +OP4 E00610 0 +OP4 E00611 0 +OP4 E00612 0 +OP4 E00613 0 +OP4 E00614 0 +OP4 E00615 0 +OP4 E00616 0 +OP4 E00617 0 +OP4 E00618 0 +OP4 E00619 0 +OP4 E0061A 0 +OP4 E0061B 0 +OP4 E0061C 0 +OP4 E0061D 0 +OP4 E0061E 0 +OP4 E0061F 0 +OP4 E00620 0 +OP4 E00621 0 +OP4 E00622 0 +OP4 E00623 0 +OP4 E00624 0 +OP4 E00625 0 +OP4 E00626 0 +OP4 E00627 0 +OP4 E00628 0 +OP4 E00629 0 +OP4 E0062A 0 +OP4 E0062B 0 +OP4 E0062C 0 +OP4 E0062D 0 +OP4 E0062E 0 +OP4 E0062F 0 +OP4 E00630 0 +OP4 E00631 0 +OP4 E00632 0 +OP4 E00633 0 +OP4 E00634 0 +OP4 E00635 0 +OP4 E00636 0 +OP4 E00637 0 +OP4 E00638 0 +OP4 E00639 0 +OP4 E0063A 0 +OP4 E0063B 0 +OP4 E0063C 0 +OP4 E0063D 0 +OP4 E0063E 0 +OP4 E0063F 0 +OP4 E00640 0 +OP4 E00641 0 +OP4 E00642 0 +OP4 E00643 0 +OP4 E00644 0 +OP4 E00645 0 +OP4 E00646 0 +OP4 E00647 0 +OP4 E00648 0 +OP4 E00649 0 +OP4 E0064A 0 +OP4 E0064B 0 +OP4 E0064C 0 +OP4 E0064D 0 +OP4 E0064E 0 +OP4 E0064F 0 +OP4 E00650 0 +OP4 E00651 0 +OP4 E00652 0 +OP4 E00653 0 +OP4 E00654 0 +OP4 E00655 0 +OP4 E00656 0 +OP4 E00657 0 +OP4 E00658 0 +OP4 E00659 0 +OP4 E0065A 0 +OP4 E0065B 0 +OP4 E0065C 0 +OP4 E0065D 0 +OP4 E0065E 0 +OP4 E0065F 0 +OP4 E00660 0 +OP4 E00661 0 +OP4 E00662 0 +OP4 E00663 0 +OP4 E00664 0 +OP4 E00665 0 +OP4 E00666 0 +OP4 E00667 0 +OP4 E00668 0 +OP4 E00669 0 +OP4 E0066A 0 +OP4 E0066B 0 +OP4 E0066C 0 +OP4 E0066D 0 +OP4 E0066E 0 +OP4 E0066F 0 +OP4 E00670 0 +OP4 E00671 0 +OP4 E00672 0 +OP4 E00673 0 +OP4 E00674 0 +OP4 E00675 0 +OP4 E00676 0 +OP4 E00677 0 +OP4 E00678 0 +OP4 E00679 0 +OP4 E0067A 0 +OP4 E0067B 0 +OP4 E0067C 0 +OP4 E0067D 0 +OP4 E0067E 0 +OP4 E0067F 0 +OP4 E00680 0 +OP4 E00681 0 +OP4 E00682 0 +OP4 E00683 0 +OP4 E00684 0 +OP4 E00685 0 +OP4 E00686 0 +OP4 E00687 0 +OP4 E00688 0 +OP4 E00689 0 +OP4 E0068A 0 +OP4 E0068B 0 +OP4 E0068C 0 +OP4 E0068D 0 +OP4 E0068E 0 +OP4 E0068F 0 +OP4 E00690 0 +OP4 E00691 0 +OP4 E00692 0 +OP4 E00693 0 +OP4 E00694 0 +OP4 E00695 0 +OP4 E00696 0 +OP4 E00697 0 +OP4 E00698 0 +OP4 E00699 0 +OP4 E0069A 0 +OP4 E0069B 0 +OP4 E0069C 0 +OP4 E0069D 0 +OP4 E0069E 0 +OP4 E0069F 0 +OP4 E006A0 0 +OP4 E006A1 0 +OP4 E006A2 0 +OP4 E006A3 0 +OP4 E006A4 0 +OP4 E006A5 0 +OP4 E006A6 0 +OP4 E006A7 0 +OP4 E006A8 0 +OP4 E006A9 0 +OP4 E006AA 0 +OP4 E006AB 0 +OP4 E006AC 0 +OP4 E006AD 0 +OP4 E006AE 0 +OP4 E006AF 0 +OP4 E006B0 0 +OP4 E006B1 0 +OP4 E006B2 0 +OP4 E006B3 0 +OP4 E006B4 0 +OP4 E006B5 0 +OP4 E006B6 0 +OP4 E006B7 0 +OP4 E006B8 0 +OP4 E006B9 0 +OP4 E006BA 0 +OP4 E006BB 0 +OP4 E006BC 0 +OP4 E006BD 0 +OP4 E006BE 0 +OP4 E006BF 0 +OP4 E006C0 0 +OP4 E006C1 0 +OP4 E006C2 0 +OP4 E006C3 0 +OP4 E006C4 0 +OP4 E006C5 0 +OP4 E006C6 0 +OP4 E006C7 0 +OP4 E006C8 0 +OP4 E006C9 0 +OP4 E006CA 0 +OP4 E006CB 0 +OP4 E006CC 0 +OP4 E006CD 0 +OP4 E006CE 0 +OP4 E006CF 0 +OP4 E006D0 0 +OP4 E006D1 0 +OP4 E006D2 0 +OP4 E006D3 0 +OP4 E006D4 0 +OP4 E006D5 0 +OP4 E006D6 0 +OP4 E006D7 0 +OP4 E006D8 0 +OP4 E006D9 0 +OP4 E006DA 0 +OP4 E006DB 0 +OP4 E006DC 0 +OP4 E006DD 0 +OP4 E006DE 0 +OP4 E006DF 0 +OP4 E006E0 0 +OP4 E006E1 0 +OP4 E006E2 0 +OP4 E006E3 0 +OP4 E006E4 0 +OP4 E006E5 0 +OP4 E006E6 0 +OP4 E006E7 0 +OP4 E006E8 0 +OP4 E006E9 0 +OP4 E006EA 0 +OP4 E006EB 0 +OP4 E006EC 0 +OP4 E006ED 0 +OP4 E006EE 0 +OP4 E006EF 0 +OP4 E006F0 0 +OP4 E006F1 0 +OP4 E006F2 0 +OP4 E006F3 0 +OP4 E006F4 0 +OP4 E006F5 0 +OP4 E006F6 0 +OP4 E006F7 0 +OP4 E006F8 0 +OP4 E006F9 0 +OP4 E006FA 0 +OP4 E006FB 0 +OP4 E006FC 0 +OP4 E006FD 0 +OP4 E006FE 0 +OP4 E006FF 0 +OP4 E00700 0 +OP4 E00701 0 +OP4 E00702 0 +OP4 E00703 0 +OP4 E00704 0 +OP4 E00705 0 +OP4 E00706 0 +OP4 E00707 0 +OP4 E00708 0 +OP4 E00709 0 +OP4 E0070A 0 +OP4 E0070B 0 +OP4 E0070C 0 +OP4 E0070D 0 +OP4 E0070E 0 +OP4 E0070F 0 +OP4 E00710 0 +OP4 E00711 0 +OP4 E00712 0 +OP4 E00713 0 +OP4 E00714 0 +OP4 E00715 0 +OP4 E00716 0 +OP4 E00717 0 +OP4 E00718 0 +OP4 E00719 0 +OP4 E0071A 0 +OP4 E0071B 0 +OP4 E0071C 0 +OP4 E0071D 0 +OP4 E0071E 0 +OP4 E0071F 0 +OP4 E00720 0 +OP4 E00721 0 +OP4 E00722 0 +OP4 E00723 0 +OP4 E00724 0 +OP4 E00725 0 +OP4 E00726 0 +OP4 E00727 0 +OP4 E00728 0 +OP4 E00729 0 +OP4 E0072A 0 +OP4 E0072B 0 +OP4 E0072C 0 +OP4 E0072D 0 +OP4 E0072E 0 +OP4 E0072F 0 +OP4 E00730 0 +OP4 E00731 0 +OP4 E00732 0 +OP4 E00733 0 +OP4 E00734 0 +OP4 E00735 0 +OP4 E00736 0 +OP4 E00737 0 +OP4 E00738 0 +OP4 E00739 0 +OP4 E0073A 0 +OP4 E0073B 0 +OP4 E0073C 0 +OP4 E0073D 0 +OP4 E0073E 0 +OP4 E0073F 0 +OP4 E00740 0 +OP4 E00741 0 +OP4 E00742 0 +OP4 E00743 0 +OP4 E00744 0 +OP4 E00745 0 +OP4 E00746 0 +OP4 E00747 0 +OP4 E00748 0 +OP4 E00749 0 +OP4 E0074A 0 +OP4 E0074B 0 +OP4 E0074C 0 +OP4 E0074D 0 +OP4 E0074E 0 +OP4 E0074F 0 +OP4 E00750 0 +OP4 E00751 0 +OP4 E00752 0 +OP4 E00753 0 +OP4 E00754 0 +OP4 E00755 0 +OP4 E00756 0 +OP4 E00757 0 +OP4 E00758 0 +OP4 E00759 0 +OP4 E0075A 0 +OP4 E0075B 0 +OP4 E0075C 0 +OP4 E0075D 0 +OP4 E0075E 0 +OP4 E0075F 0 +OP4 E00760 0 +OP4 E00761 0 +OP4 E00762 0 +OP4 E00763 0 +OP4 E00764 0 +OP4 E00765 0 +OP4 E00766 0 +OP4 E00767 0 +OP4 E00768 0 +OP4 E00769 0 +OP4 E0076A 0 +OP4 E0076B 0 +OP4 E0076C 0 +OP4 E0076D 0 +OP4 E0076E 0 +OP4 E0076F 0 +OP4 E00770 0 +OP4 E00771 0 +OP4 E00772 0 +OP4 E00773 0 +OP4 E00774 0 +OP4 E00775 0 +OP4 E00776 0 +OP4 E00777 0 +OP4 E00778 0 +OP4 E00779 0 +OP4 E0077A 0 +OP4 E0077B 0 +OP4 E0077C 0 +OP4 E0077D 0 +OP4 E0077E 0 +OP4 E0077F 0 +OP4 E00780 0 +OP4 E00781 0 +OP4 E00782 0 +OP4 E00783 0 +OP4 E00784 0 +OP4 E00785 0 +OP4 E00786 0 +OP4 E00787 0 +OP4 E00788 0 +OP4 E00789 0 +OP4 E0078A 0 +OP4 E0078B 0 +OP4 E0078C 0 +OP4 E0078D 0 +OP4 E0078E 0 +OP4 E0078F 0 +OP4 E00790 0 +OP4 E00791 0 +OP4 E00792 0 +OP4 E00793 0 +OP4 E00794 0 +OP4 E00795 0 +OP4 E00796 0 +OP4 E00797 0 +OP4 E00798 0 +OP4 E00799 0 +OP4 E0079A 0 +OP4 E0079B 0 +OP4 E0079C 0 +OP4 E0079D 0 +OP4 E0079E 0 +OP4 E0079F 0 +OP4 E007A0 0 +OP4 E007A1 0 +OP4 E007A2 0 +OP4 E007A3 0 +OP4 E007A4 0 +OP4 E007A5 0 +OP4 E007A6 0 +OP4 E007A7 0 +OP4 E007A8 0 +OP4 E007A9 0 +OP4 E007AA 0 +OP4 E007AB 0 +OP4 E007AC 0 +OP4 E007AD 0 +OP4 E007AE 0 +OP4 E007AF 0 +OP4 E007B0 0 +OP4 E007B1 0 +OP4 E007B2 0 +OP4 E007B3 0 +OP4 E007B4 0 +OP4 E007B5 0 +OP4 E007B6 0 +OP4 E007B7 0 +OP4 E007B8 0 +OP4 E007B9 0 +OP4 E007BA 0 +OP4 E007BB 0 +OP4 E007BC 0 +OP4 E007BD 0 +OP4 E007BE 0 +OP4 E007BF 0 +OP4 E007C0 0 +OP4 E007C1 0 +OP4 E007C2 0 +OP4 E007C3 0 +OP4 E007C4 0 +OP4 E007C5 0 +OP4 E007C6 0 +OP4 E007C7 0 +OP4 E007C8 0 +OP4 E007C9 0 +OP4 E007CA 0 +OP4 E007CB 0 +OP4 E007CC 0 +OP4 E007CD 0 +OP4 E007CE 0 +OP4 E007CF 0 +OP4 E007D0 0 +OP4 E007D1 0 +OP4 E007D2 0 +OP4 E007D3 0 +OP4 E007D4 0 +OP4 E007D5 0 +OP4 E007D6 0 +OP4 E007D7 0 +OP4 E007D8 0 +OP4 E007D9 0 +OP4 E007DA 0 +OP4 E007DB 0 +OP4 E007DC 0 +OP4 E007DD 0 +OP4 E007DE 0 +OP4 E007DF 0 +OP4 E007E0 0 +OP4 E007E1 0 +OP4 E007E2 0 +OP4 E007E3 0 +OP4 E007E4 0 +OP4 E007E5 0 +OP4 E007E6 0 +OP4 E007E7 0 +OP4 E007E8 0 +OP4 E007E9 0 +OP4 E007EA 0 +OP4 E007EB 0 +OP4 E007EC 0 +OP4 E007ED 0 +OP4 E007EE 0 +OP4 E007EF 0 +OP4 E007F0 0 +OP4 E007F1 0 +OP4 E007F2 0 +OP4 E007F3 0 +OP4 E007F4 0 +OP4 E007F5 0 +OP4 E007F6 0 +OP4 E007F7 0 +OP4 E007F8 0 +OP4 E007F9 0 +OP4 E007FA 0 +OP4 E007FB 0 +OP4 E007FC 0 +OP4 E007FD 0 +OP4 E007FE 0 +OP4 E007FF 0 +OP4 E00800 0 +OP4 E00801 0 +OP4 E00802 0 +OP4 E00803 0 +OP4 E00804 0 +OP4 E00805 0 +OP4 E00806 0 +OP4 E00807 0 +OP4 E00808 0 +OP4 E00809 0 +OP4 E0080A 0 +OP4 E0080B 0 +OP4 E0080C 0 +OP4 E0080D 0 +OP4 E0080E 0 +OP4 E0080F 0 +OP4 E00810 0 +OP4 E00811 0 +OP4 E00812 0 +OP4 E00813 0 +OP4 E00814 0 +OP4 E00815 0 +OP4 E00816 0 +OP4 E00817 0 +OP4 E00818 0 +OP4 E00819 0 +OP4 E0081A 0 +OP4 E0081B 0 +OP4 E0081C 0 +OP4 E0081D 0 +OP4 E0081E 0 +OP4 E0081F 0 +OP4 E00820 0 +OP4 E00821 0 +OP4 E00822 0 +OP4 E00823 0 +OP4 E00824 0 +OP4 E00825 0 +OP4 E00826 0 +OP4 E00827 0 +OP4 E00828 0 +OP4 E00829 0 +OP4 E0082A 0 +OP4 E0082B 0 +OP4 E0082C 0 +OP4 E0082D 0 +OP4 E0082E 0 +OP4 E0082F 0 +OP4 E00830 0 +OP4 E00831 0 +OP4 E00832 0 +OP4 E00833 0 +OP4 E00834 0 +OP4 E00835 0 +OP4 E00836 0 +OP4 E00837 0 +OP4 E00838 0 +OP4 E00839 0 +OP4 E0083A 0 +OP4 E0083B 0 +OP4 E0083C 0 +OP4 E0083D 0 +OP4 E0083E 0 +OP4 E0083F 0 +OP4 E00840 0 +OP4 E00841 0 +OP4 E00842 0 +OP4 E00843 0 +OP4 E00844 0 +OP4 E00845 0 +OP4 E00846 0 +OP4 E00847 0 +OP4 E00848 0 +OP4 E00849 0 +OP4 E0084A 0 +OP4 E0084B 0 +OP4 E0084C 0 +OP4 E0084D 0 +OP4 E0084E 0 +OP4 E0084F 0 +OP4 E00850 0 +OP4 E00851 0 +OP4 E00852 0 +OP4 E00853 0 +OP4 E00854 0 +OP4 E00855 0 +OP4 E00856 0 +OP4 E00857 0 +OP4 E00858 0 +OP4 E00859 0 +OP4 E0085A 0 +OP4 E0085B 0 +OP4 E0085C 0 +OP4 E0085D 0 +OP4 E0085E 0 +OP4 E0085F 0 +OP4 E00860 0 +OP4 E00861 0 +OP4 E00862 0 +OP4 E00863 0 +OP4 E00864 0 +OP4 E00865 0 +OP4 E00866 0 +OP4 E00867 0 +OP4 E00868 0 +OP4 E00869 0 +OP4 E0086A 0 +OP4 E0086B 0 +OP4 E0086C 0 +OP4 E0086D 0 +OP4 E0086E 0 +OP4 E0086F 0 +OP4 E00870 0 +OP4 E00871 0 +OP4 E00872 0 +OP4 E00873 0 +OP4 E00874 0 +OP4 E00875 0 +OP4 E00876 0 +OP4 E00877 0 +OP4 E00878 0 +OP4 E00879 0 +OP4 E0087A 0 +OP4 E0087B 0 +OP4 E0087C 0 +OP4 E0087D 0 +OP4 E0087E 0 +OP4 E0087F 0 +OP4 E00880 0 +OP4 E00881 0 +OP4 E00882 0 +OP4 E00883 0 +OP4 E00884 0 +OP4 E00885 0 +OP4 E00886 0 +OP4 E00887 0 +OP4 E00888 0 +OP4 E00889 0 +OP4 E0088A 0 +OP4 E0088B 0 +OP4 E0088C 0 +OP4 E0088D 0 +OP4 E0088E 0 +OP4 E0088F 0 +OP4 E00890 0 +OP4 E00891 0 +OP4 E00892 0 +OP4 E00893 0 +OP4 E00894 0 +OP4 E00895 0 +OP4 E00896 0 +OP4 E00897 0 +OP4 E00898 0 +OP4 E00899 0 +OP4 E0089A 0 +OP4 E0089B 0 +OP4 E0089C 0 +OP4 E0089D 0 +OP4 E0089E 0 +OP4 E0089F 0 +OP4 E008A0 0 +OP4 E008A1 0 +OP4 E008A2 0 +OP4 E008A3 0 +OP4 E008A4 0 +OP4 E008A5 0 +OP4 E008A6 0 +OP4 E008A7 0 +OP4 E008A8 0 +OP4 E008A9 0 +OP4 E008AA 0 +OP4 E008AB 0 +OP4 E008AC 0 +OP4 E008AD 0 +OP4 E008AE 0 +OP4 E008AF 0 +OP4 E008B0 0 +OP4 E008B1 0 +OP4 E008B2 0 +OP4 E008B3 0 +OP4 E008B4 0 +OP4 E008B5 0 +OP4 E008B6 0 +OP4 E008B7 0 +OP4 E008B8 0 +OP4 E008B9 0 +OP4 E008BA 0 +OP4 E008BB 0 +OP4 E008BC 0 +OP4 E008BD 0 +OP4 E008BE 0 +OP4 E008BF 0 +OP4 E008C0 0 +OP4 E008C1 0 +OP4 E008C2 0 +OP4 E008C3 0 +OP4 E008C4 0 +OP4 E008C5 0 +OP4 E008C6 0 +OP4 E008C7 0 +OP4 E008C8 0 +OP4 E008C9 0 +OP4 E008CA 0 +OP4 E008CB 0 +OP4 E008CC 0 +OP4 E008CD 0 +OP4 E008CE 0 +OP4 E008CF 0 +OP4 E008D0 0 +OP4 E008D1 0 +OP4 E008D2 0 +OP4 E008D3 0 +OP4 E008D4 0 +OP4 E008D5 0 +OP4 E008D6 0 +OP4 E008D7 0 +OP4 E008D8 0 +OP4 E008D9 0 +OP4 E008DA 0 +OP4 E008DB 0 +OP4 E008DC 0 +OP4 E008DD 0 +OP4 E008DE 0 +OP4 E008DF 0 +OP4 E008E0 0 +OP4 E008E1 0 +OP4 E008E2 0 +OP4 E008E3 0 +OP4 E008E4 0 +OP4 E008E5 0 +OP4 E008E6 0 +OP4 E008E7 0 +OP4 E008E8 0 +OP4 E008E9 0 +OP4 E008EA 0 +OP4 E008EB 0 +OP4 E008EC 0 +OP4 E008ED 0 +OP4 E008EE 0 +OP4 E008EF 0 +OP4 E008F0 0 +OP4 E008F1 0 +OP4 E008F2 0 +OP4 E008F3 0 +OP4 E008F4 0 +OP4 E008F5 0 +OP4 E008F6 0 +OP4 E008F7 0 +OP4 E008F8 0 +OP4 E008F9 0 +OP4 E008FA 0 +OP4 E008FB 0 +OP4 E008FC 0 +OP4 E008FD 0 +OP4 E008FE 0 +OP4 E008FF 0 +OP4 E00900 0 +OP4 E00901 0 +OP4 E00902 0 +OP4 E00903 0 +OP4 E00904 0 +OP4 E00905 0 +OP4 E00906 0 +OP4 E00907 0 +OP4 E00908 0 +OP4 E00909 0 +OP4 E0090A 0 +OP4 E0090B 0 +OP4 E0090C 0 +OP4 E0090D 0 +OP4 E0090E 0 +OP4 E0090F 0 +OP4 E00910 0 +OP4 E00911 0 +OP4 E00912 0 +OP4 E00913 0 +OP4 E00914 0 +OP4 E00915 0 +OP4 E00916 0 +OP4 E00917 0 +OP4 E00918 0 +OP4 E00919 0 +OP4 E0091A 0 +OP4 E0091B 0 +OP4 E0091C 0 +OP4 E0091D 0 +OP4 E0091E 0 +OP4 E0091F 0 +OP4 E00920 0 +OP4 E00921 0 +OP4 E00922 0 +OP4 E00923 0 +OP4 E00924 0 +OP4 E00925 0 +OP4 E00926 0 +OP4 E00927 0 +OP4 E00928 0 +OP4 E00929 0 +OP4 E0092A 0 +OP4 E0092B 0 +OP4 E0092C 0 +OP4 E0092D 0 +OP4 E0092E 0 +OP4 E0092F 0 +OP4 E00930 0 +OP4 E00931 0 +OP4 E00932 0 +OP4 E00933 0 +OP4 E00934 0 +OP4 E00935 0 +OP4 E00936 0 +OP4 E00937 0 +OP4 E00938 0 +OP4 E00939 0 +OP4 E0093A 0 +OP4 E0093B 0 +OP4 E0093C 0 +OP4 E0093D 0 +OP4 E0093E 0 +OP4 E0093F 0 +OP4 E00940 0 +OP4 E00941 0 +OP4 E00942 0 +OP4 E00943 0 +OP4 E00944 0 +OP4 E00945 0 +OP4 E00946 0 +OP4 E00947 0 +OP4 E00948 0 +OP4 E00949 0 +OP4 E0094A 0 +OP4 E0094B 0 +OP4 E0094C 0 +OP4 E0094D 0 +OP4 E0094E 0 +OP4 E0094F 0 +OP4 E00950 0 +OP4 E00951 0 +OP4 E00952 0 +OP4 E00953 0 +OP4 E00954 0 +OP4 E00955 0 +OP4 E00956 0 +OP4 E00957 0 +OP4 E00958 0 +OP4 E00959 0 +OP4 E0095A 0 +OP4 E0095B 0 +OP4 E0095C 0 +OP4 E0095D 0 +OP4 E0095E 0 +OP4 E0095F 0 +OP4 E00960 0 +OP4 E00961 0 +OP4 E00962 0 +OP4 E00963 0 +OP4 E00964 0 +OP4 E00965 0 +OP4 E00966 0 +OP4 E00967 0 +OP4 E00968 0 +OP4 E00969 0 +OP4 E0096A 0 +OP4 E0096B 0 +OP4 E0096C 0 +OP4 E0096D 0 +OP4 E0096E 0 +OP4 E0096F 0 +OP4 E00970 0 +OP4 E00971 0 +OP4 E00972 0 +OP4 E00973 0 +OP4 E00974 0 +OP4 E00975 0 +OP4 E00976 0 +OP4 E00977 0 +OP4 E00978 0 +OP4 E00979 0 +OP4 E0097A 0 +OP4 E0097B 0 +OP4 E0097C 0 +OP4 E0097D 0 +OP4 E0097E 0 +OP4 E0097F 0 +OP4 E00980 0 +OP4 E00981 0 +OP4 E00982 0 +OP4 E00983 0 +OP4 E00984 0 +OP4 E00985 0 +OP4 E00986 0 +OP4 E00987 0 +OP4 E00988 0 +OP4 E00989 0 +OP4 E0098A 0 +OP4 E0098B 0 +OP4 E0098C 0 +OP4 E0098D 0 +OP4 E0098E 0 +OP4 E0098F 0 +OP4 E00990 0 +OP4 E00991 0 +OP4 E00992 0 +OP4 E00993 0 +OP4 E00994 0 +OP4 E00995 0 +OP4 E00996 0 +OP4 E00997 0 +OP4 E00998 0 +OP4 E00999 0 +OP4 E0099A 0 +OP4 E0099B 0 +OP4 E0099C 0 +OP4 E0099D 0 +OP4 E0099E 0 +OP4 E0099F 0 +OP4 E009A0 0 +OP4 E009A1 0 +OP4 E009A2 0 +OP4 E009A3 0 +OP4 E009A4 0 +OP4 E009A5 0 +OP4 E009A6 0 +OP4 E009A7 0 +OP4 E009A8 0 +OP4 E009A9 0 +OP4 E009AA 0 +OP4 E009AB 0 +OP4 E009AC 0 +OP4 E009AD 0 +OP4 E009AE 0 +OP4 E009AF 0 +OP4 E009B0 0 +OP4 E009B1 0 +OP4 E009B2 0 +OP4 E009B3 0 +OP4 E009B4 0 +OP4 E009B5 0 +OP4 E009B6 0 +OP4 E009B7 0 +OP4 E009B8 0 +OP4 E009B9 0 +OP4 E009BA 0 +OP4 E009BB 0 +OP4 E009BC 0 +OP4 E009BD 0 +OP4 E009BE 0 +OP4 E009BF 0 +OP4 E009C0 0 +OP4 E009C1 0 +OP4 E009C2 0 +OP4 E009C3 0 +OP4 E009C4 0 +OP4 E009C5 0 +OP4 E009C6 0 +OP4 E009C7 0 +OP4 E009C8 0 +OP4 E009C9 0 +OP4 E009CA 0 +OP4 E009CB 0 +OP4 E009CC 0 +OP4 E009CD 0 +OP4 E009CE 0 +OP4 E009CF 0 +OP4 E009D0 0 +OP4 E009D1 0 +OP4 E009D2 0 +OP4 E009D3 0 +OP4 E009D4 0 +OP4 E009D5 0 +OP4 E009D6 0 +OP4 E009D7 0 +OP4 E009D8 0 +OP4 E009D9 0 +OP4 E009DA 0 +OP4 E009DB 0 +OP4 E009DC 0 +OP4 E009DD 0 +OP4 E009DE 0 +OP4 E009DF 0 +OP4 E009E0 0 +OP4 E009E1 0 +OP4 E009E2 0 +OP4 E009E3 0 +OP4 E009E4 0 +OP4 E009E5 0 +OP4 E009E6 0 +OP4 E009E7 0 +OP4 E009E8 0 +OP4 E009E9 0 +OP4 E009EA 0 +OP4 E009EB 0 +OP4 E009EC 0 +OP4 E009ED 0 +OP4 E009EE 0 +OP4 E009EF 0 +OP4 E009F0 0 +OP4 E009F1 0 +OP4 E009F2 0 +OP4 E009F3 0 +OP4 E009F4 0 +OP4 E009F5 0 +OP4 E009F6 0 +OP4 E009F7 0 +OP4 E009F8 0 +OP4 E009F9 0 +OP4 E009FA 0 +OP4 E009FB 0 +OP4 E009FC 0 +OP4 E009FD 0 +OP4 E009FE 0 +OP4 E009FF 0 +OP4 E00A00 0 +OP4 E00A01 0 +OP4 E00A02 0 +OP4 E00A03 0 +OP4 E00A04 0 +OP4 E00A05 0 +OP4 E00A06 0 +OP4 E00A07 0 +OP4 E00A08 0 +OP4 E00A09 0 +OP4 E00A0A 0 +OP4 E00A0B 0 +OP4 E00A0C 0 +OP4 E00A0D 0 +OP4 E00A0E 0 +OP4 E00A0F 0 +OP4 E00A10 0 +OP4 E00A11 0 +OP4 E00A12 0 +OP4 E00A13 0 +OP4 E00A14 0 +OP4 E00A15 0 +OP4 E00A16 0 +OP4 E00A17 0 +OP4 E00A18 0 +OP4 E00A19 0 +OP4 E00A1A 0 +OP4 E00A1B 0 +OP4 E00A1C 0 +OP4 E00A1D 0 +OP4 E00A1E 0 +OP4 E00A1F 0 +OP4 E00A20 0 +OP4 E00A21 0 +OP4 E00A22 0 +OP4 E00A23 0 +OP4 E00A24 0 +OP4 E00A25 0 +OP4 E00A26 0 +OP4 E00A27 0 +OP4 E00A28 0 +OP4 E00A29 0 +OP4 E00A2A 0 +OP4 E00A2B 0 +OP4 E00A2C 0 +OP4 E00A2D 0 +OP4 E00A2E 0 +OP4 E00A2F 0 +OP4 E00A30 0 +OP4 E00A31 0 +OP4 E00A32 0 +OP4 E00A33 0 +OP4 E00A34 0 +OP4 E00A35 0 +OP4 E00A36 0 +OP4 E00A37 0 +OP4 E00A38 0 +OP4 E00A39 0 +OP4 E00A3A 0 +OP4 E00A3B 0 +OP4 E00A3C 0 +OP4 E00A3D 0 +OP4 E00A3E 0 +OP4 E00A3F 0 +OP4 E00A40 0 +OP4 E00A41 0 +OP4 E00A42 0 +OP4 E00A43 0 +OP4 E00A44 0 +OP4 E00A45 0 +OP4 E00A46 0 +OP4 E00A47 0 +OP4 E00A48 0 +OP4 E00A49 0 +OP4 E00A4A 0 +OP4 E00A4B 0 +OP4 E00A4C 0 +OP4 E00A4D 0 +OP4 E00A4E 0 +OP4 E00A4F 0 +OP4 E00A50 0 +OP4 E00A51 0 +OP4 E00A52 0 +OP4 E00A53 0 +OP4 E00A54 0 +OP4 E00A55 0 +OP4 E00A56 0 +OP4 E00A57 0 +OP4 E00A58 0 +OP4 E00A59 0 +OP4 E00A5A 0 +OP4 E00A5B 0 +OP4 E00A5C 0 +OP4 E00A5D 0 +OP4 E00A5E 0 +OP4 E00A5F 0 +OP4 E00A60 0 +OP4 E00A61 0 +OP4 E00A62 0 +OP4 E00A63 0 +OP4 E00A64 0 +OP4 E00A65 0 +OP4 E00A66 0 +OP4 E00A67 0 +OP4 E00A68 0 +OP4 E00A69 0 +OP4 E00A6A 0 +OP4 E00A6B 0 +OP4 E00A6C 0 +OP4 E00A6D 0 +OP4 E00A6E 0 +OP4 E00A6F 0 +OP4 E00A70 0 +OP4 E00A71 0 +OP4 E00A72 0 +OP4 E00A73 0 +OP4 E00A74 0 +OP4 E00A75 0 +OP4 E00A76 0 +OP4 E00A77 0 +OP4 E00A78 0 +OP4 E00A79 0 +OP4 E00A7A 0 +OP4 E00A7B 0 +OP4 E00A7C 0 +OP4 E00A7D 0 +OP4 E00A7E 0 +OP4 E00A7F 0 +OP4 E00A80 0 +OP4 E00A81 0 +OP4 E00A82 0 +OP4 E00A83 0 +OP4 E00A84 0 +OP4 E00A85 0 +OP4 E00A86 0 +OP4 E00A87 0 +OP4 E00A88 0 +OP4 E00A89 0 +OP4 E00A8A 0 +OP4 E00A8B 0 +OP4 E00A8C 0 +OP4 E00A8D 0 +OP4 E00A8E 0 +OP4 E00A8F 0 +OP4 E00A90 0 +OP4 E00A91 0 +OP4 E00A92 0 +OP4 E00A93 0 +OP4 E00A94 0 +OP4 E00A95 0 +OP4 E00A96 0 +OP4 E00A97 0 +OP4 E00A98 0 +OP4 E00A99 0 +OP4 E00A9A 0 +OP4 E00A9B 0 +OP4 E00A9C 0 +OP4 E00A9D 0 +OP4 E00A9E 0 +OP4 E00A9F 0 +OP4 E00AA0 0 +OP4 E00AA1 0 +OP4 E00AA2 0 +OP4 E00AA3 0 +OP4 E00AA4 0 +OP4 E00AA5 0 +OP4 E00AA6 0 +OP4 E00AA7 0 +OP4 E00AA8 0 +OP4 E00AA9 0 +OP4 E00AAA 0 +OP4 E00AAB 0 +OP4 E00AAC 0 +OP4 E00AAD 0 +OP4 E00AAE 0 +OP4 E00AAF 0 +OP4 E00AB0 0 +OP4 E00AB1 0 +OP4 E00AB2 0 +OP4 E00AB3 0 +OP4 E00AB4 0 +OP4 E00AB5 0 +OP4 E00AB6 0 +OP4 E00AB7 0 +OP4 E00AB8 0 +OP4 E00AB9 0 +OP4 E00ABA 0 +OP4 E00ABB 0 +OP4 E00ABC 0 +OP4 E00ABD 0 +OP4 E00ABE 0 +OP4 E00ABF 0 +OP4 E00AC0 0 +OP4 E00AC1 0 +OP4 E00AC2 0 +OP4 E00AC3 0 +OP4 E00AC4 0 +OP4 E00AC5 0 +OP4 E00AC6 0 +OP4 E00AC7 0 +OP4 E00AC8 0 +OP4 E00AC9 0 +OP4 E00ACA 0 +OP4 E00ACB 0 +OP4 E00ACC 0 +OP4 E00ACD 0 +OP4 E00ACE 0 +OP4 E00ACF 0 +OP4 E00AD0 0 +OP4 E00AD1 0 +OP4 E00AD2 0 +OP4 E00AD3 0 +OP4 E00AD4 0 +OP4 E00AD5 0 +OP4 E00AD6 0 +OP4 E00AD7 0 +OP4 E00AD8 0 +OP4 E00AD9 0 +OP4 E00ADA 0 +OP4 E00ADB 0 +OP4 E00ADC 0 +OP4 E00ADD 0 +OP4 E00ADE 0 +OP4 E00ADF 0 +OP4 E00AE0 0 +OP4 E00AE1 0 +OP4 E00AE2 0 +OP4 E00AE3 0 +OP4 E00AE4 0 +OP4 E00AE5 0 +OP4 E00AE6 0 +OP4 E00AE7 0 +OP4 E00AE8 0 +OP4 E00AE9 0 +OP4 E00AEA 0 +OP4 E00AEB 0 +OP4 E00AEC 0 +OP4 E00AED 0 +OP4 E00AEE 0 +OP4 E00AEF 0 +OP4 E00AF0 0 +OP4 E00AF1 0 +OP4 E00AF2 0 +OP4 E00AF3 0 +OP4 E00AF4 0 +OP4 E00AF5 0 +OP4 E00AF6 0 +OP4 E00AF7 0 +OP4 E00AF8 0 +OP4 E00AF9 0 +OP4 E00AFA 0 +OP4 E00AFB 0 +OP4 E00AFC 0 +OP4 E00AFD 0 +OP4 E00AFE 0 +OP4 E00AFF 0 +OP4 E00B00 0 +OP4 E00B01 0 +OP4 E00B02 0 +OP4 E00B03 0 +OP4 E00B04 0 +OP4 E00B05 0 +OP4 E00B06 0 +OP4 E00B07 0 +OP4 E00B08 0 +OP4 E00B09 0 +OP4 E00B0A 0 +OP4 E00B0B 0 +OP4 E00B0C 0 +OP4 E00B0D 0 +OP4 E00B0E 0 +OP4 E00B0F 0 +OP4 E00B10 0 +OP4 E00B11 0 +OP4 E00B12 0 +OP4 E00B13 0 +OP4 E00B14 0 +OP4 E00B15 0 +OP4 E00B16 0 +OP4 E00B17 0 +OP4 E00B18 0 +OP4 E00B19 0 +OP4 E00B1A 0 +OP4 E00B1B 0 +OP4 E00B1C 0 +OP4 E00B1D 0 +OP4 E00B1E 0 +OP4 E00B1F 0 +OP4 E00B20 0 +OP4 E00B21 0 +OP4 E00B22 0 +OP4 E00B23 0 +OP4 E00B24 0 +OP4 E00B25 0 +OP4 E00B26 0 +OP4 E00B27 0 +OP4 E00B28 0 +OP4 E00B29 0 +OP4 E00B2A 0 +OP4 E00B2B 0 +OP4 E00B2C 0 +OP4 E00B2D 0 +OP4 E00B2E 0 +OP4 E00B2F 0 +OP4 E00B30 0 +OP4 E00B31 0 +OP4 E00B32 0 +OP4 E00B33 0 +OP4 E00B34 0 +OP4 E00B35 0 +OP4 E00B36 0 +OP4 E00B37 0 +OP4 E00B38 0 +OP4 E00B39 0 +OP4 E00B3A 0 +OP4 E00B3B 0 +OP4 E00B3C 0 +OP4 E00B3D 0 +OP4 E00B3E 0 +OP4 E00B3F 0 +OP4 E00B40 0 +OP4 E00B41 0 +OP4 E00B42 0 +OP4 E00B43 0 +OP4 E00B44 0 +OP4 E00B45 0 +OP4 E00B46 0 +OP4 E00B47 0 +OP4 E00B48 0 +OP4 E00B49 0 +OP4 E00B4A 0 +OP4 E00B4B 0 +OP4 E00B4C 0 +OP4 E00B4D 0 +OP4 E00B4E 0 +OP4 E00B4F 0 +OP4 E00B50 0 +OP4 E00B51 0 +OP4 E00B52 0 +OP4 E00B53 0 +OP4 E00B54 0 +OP4 E00B55 0 +OP4 E00B56 0 +OP4 E00B57 0 +OP4 E00B58 0 +OP4 E00B59 0 +OP4 E00B5A 0 +OP4 E00B5B 0 +OP4 E00B5C 0 +OP4 E00B5D 0 +OP4 E00B5E 0 +OP4 E00B5F 0 +OP4 E00B60 0 +OP4 E00B61 0 +OP4 E00B62 0 +OP4 E00B63 0 +OP4 E00B64 0 +OP4 E00B65 0 +OP4 E00B66 0 +OP4 E00B67 0 +OP4 E00B68 0 +OP4 E00B69 0 +OP4 E00B6A 0 +OP4 E00B6B 0 +OP4 E00B6C 0 +OP4 E00B6D 0 +OP4 E00B6E 0 +OP4 E00B6F 0 +OP4 E00B70 0 +OP4 E00B71 0 +OP4 E00B72 0 +OP4 E00B73 0 +OP4 E00B74 0 +OP4 E00B75 0 +OP4 E00B76 0 +OP4 E00B77 0 +OP4 E00B78 0 +OP4 E00B79 0 +OP4 E00B7A 0 +OP4 E00B7B 0 +OP4 E00B7C 0 +OP4 E00B7D 0 +OP4 E00B7E 0 +OP4 E00B7F 0 +OP4 E00B80 0 +OP4 E00B81 0 +OP4 E00B82 0 +OP4 E00B83 0 +OP4 E00B84 0 +OP4 E00B85 0 +OP4 E00B86 0 +OP4 E00B87 0 +OP4 E00B88 0 +OP4 E00B89 0 +OP4 E00B8A 0 +OP4 E00B8B 0 +OP4 E00B8C 0 +OP4 E00B8D 0 +OP4 E00B8E 0 +OP4 E00B8F 0 +OP4 E00B90 0 +OP4 E00B91 0 +OP4 E00B92 0 +OP4 E00B93 0 +OP4 E00B94 0 +OP4 E00B95 0 +OP4 E00B96 0 +OP4 E00B97 0 +OP4 E00B98 0 +OP4 E00B99 0 +OP4 E00B9A 0 +OP4 E00B9B 0 +OP4 E00B9C 0 +OP4 E00B9D 0 +OP4 E00B9E 0 +OP4 E00B9F 0 +OP4 E00BA0 0 +OP4 E00BA1 0 +OP4 E00BA2 0 +OP4 E00BA3 0 +OP4 E00BA4 0 +OP4 E00BA5 0 +OP4 E00BA6 0 +OP4 E00BA7 0 +OP4 E00BA8 0 +OP4 E00BA9 0 +OP4 E00BAA 0 +OP4 E00BAB 0 +OP4 E00BAC 0 +OP4 E00BAD 0 +OP4 E00BAE 0 +OP4 E00BAF 0 +OP4 E00BB0 0 +OP4 E00BB1 0 +OP4 E00BB2 0 +OP4 E00BB3 0 +OP4 E00BB4 0 +OP4 E00BB5 0 +OP4 E00BB6 0 +OP4 E00BB7 0 +OP4 E00BB8 0 +OP4 E00BB9 0 +OP4 E00BBA 0 +OP4 E00BBB 0 +OP4 E00BBC 0 +OP4 E00BBD 0 +OP4 E00BBE 0 +OP4 E00BBF 0 +OP4 E00BC0 0 +OP4 E00BC1 0 +OP4 E00BC2 0 +OP4 E00BC3 0 +OP4 E00BC4 0 +OP4 E00BC5 0 +OP4 E00BC6 0 +OP4 E00BC7 0 +OP4 E00BC8 0 +OP4 E00BC9 0 +OP4 E00BCA 0 +OP4 E00BCB 0 +OP4 E00BCC 0 +OP4 E00BCD 0 +OP4 E00BCE 0 +OP4 E00BCF 0 +OP4 E00BD0 0 +OP4 E00BD1 0 +OP4 E00BD2 0 +OP4 E00BD3 0 +OP4 E00BD4 0 +OP4 E00BD5 0 +OP4 E00BD6 0 +OP4 E00BD7 0 +OP4 E00BD8 0 +OP4 E00BD9 0 +OP4 E00BDA 0 +OP4 E00BDB 0 +OP4 E00BDC 0 +OP4 E00BDD 0 +OP4 E00BDE 0 +OP4 E00BDF 0 +OP4 E00BE0 0 +OP4 E00BE1 0 +OP4 E00BE2 0 +OP4 E00BE3 0 +OP4 E00BE4 0 +OP4 E00BE5 0 +OP4 E00BE6 0 +OP4 E00BE7 0 +OP4 E00BE8 0 +OP4 E00BE9 0 +OP4 E00BEA 0 +OP4 E00BEB 0 +OP4 E00BEC 0 +OP4 E00BED 0 +OP4 E00BEE 0 +OP4 E00BEF 0 +OP4 E00BF0 0 +OP4 E00BF1 0 +OP4 E00BF2 0 +OP4 E00BF3 0 +OP4 E00BF4 0 +OP4 E00BF5 0 +OP4 E00BF6 0 +OP4 E00BF7 0 +OP4 E00BF8 0 +OP4 E00BF9 0 +OP4 E00BFA 0 +OP4 E00BFB 0 +OP4 E00BFC 0 +OP4 E00BFD 0 +OP4 E00BFE 0 +OP4 E00BFF 0 +OP4 E00C00 0 +OP4 E00C01 0 +OP4 E00C02 0 +OP4 E00C03 0 +OP4 E00C04 0 +OP4 E00C05 0 +OP4 E00C06 0 +OP4 E00C07 0 +OP4 E00C08 0 +OP4 E00C09 0 +OP4 E00C0A 0 +OP4 E00C0B 0 +OP4 E00C0C 0 +OP4 E00C0D 0 +OP4 E00C0E 0 +OP4 E00C0F 0 +OP4 E00C10 0 +OP4 E00C11 0 +OP4 E00C12 0 +OP4 E00C13 0 +OP4 E00C14 0 +OP4 E00C15 0 +OP4 E00C16 0 +OP4 E00C17 0 +OP4 E00C18 0 +OP4 E00C19 0 +OP4 E00C1A 0 +OP4 E00C1B 0 +OP4 E00C1C 0 +OP4 E00C1D 0 +OP4 E00C1E 0 +OP4 E00C1F 0 +OP4 E00C20 0 +OP4 E00C21 0 +OP4 E00C22 0 +OP4 E00C23 0 +OP4 E00C24 0 +OP4 E00C25 0 +OP4 E00C26 0 +OP4 E00C27 0 +OP4 E00C28 0 +OP4 E00C29 0 +OP4 E00C2A 0 +OP4 E00C2B 0 +OP4 E00C2C 0 +OP4 E00C2D 0 +OP4 E00C2E 0 +OP4 E00C2F 0 +OP4 E00C30 0 +OP4 E00C31 0 +OP4 E00C32 0 +OP4 E00C33 0 +OP4 E00C34 0 +OP4 E00C35 0 +OP4 E00C36 0 +OP4 E00C37 0 +OP4 E00C38 0 +OP4 E00C39 0 +OP4 E00C3A 0 +OP4 E00C3B 0 +OP4 E00C3C 0 +OP4 E00C3D 0 +OP4 E00C3E 0 +OP4 E00C3F 0 +OP4 E00C40 0 +OP4 E00C41 0 +OP4 E00C42 0 +OP4 E00C43 0 +OP4 E00C44 0 +OP4 E00C45 0 +OP4 E00C46 0 +OP4 E00C47 0 +OP4 E00C48 0 +OP4 E00C49 0 +OP4 E00C4A 0 +OP4 E00C4B 0 +OP4 E00C4C 0 +OP4 E00C4D 0 +OP4 E00C4E 0 +OP4 E00C4F 0 +OP4 E00C50 0 +OP4 E00C51 0 +OP4 E00C52 0 +OP4 E00C53 0 +OP4 E00C54 0 +OP4 E00C55 0 +OP4 E00C56 0 +OP4 E00C57 0 +OP4 E00C58 0 +OP4 E00C59 0 +OP4 E00C5A 0 +OP4 E00C5B 0 +OP4 E00C5C 0 +OP4 E00C5D 0 +OP4 E00C5E 0 +OP4 E00C5F 0 +OP4 E00C60 0 +OP4 E00C61 0 +OP4 E00C62 0 +OP4 E00C63 0 +OP4 E00C64 0 +OP4 E00C65 0 +OP4 E00C66 0 +OP4 E00C67 0 +OP4 E00C68 0 +OP4 E00C69 0 +OP4 E00C6A 0 +OP4 E00C6B 0 +OP4 E00C6C 0 +OP4 E00C6D 0 +OP4 E00C6E 0 +OP4 E00C6F 0 +OP4 E00C70 0 +OP4 E00C71 0 +OP4 E00C72 0 +OP4 E00C73 0 +OP4 E00C74 0 +OP4 E00C75 0 +OP4 E00C76 0 +OP4 E00C77 0 +OP4 E00C78 0 +OP4 E00C79 0 +OP4 E00C7A 0 +OP4 E00C7B 0 +OP4 E00C7C 0 +OP4 E00C7D 0 +OP4 E00C7E 0 +OP4 E00C7F 0 +OP4 E00C80 0 +OP4 E00C81 0 +OP4 E00C82 0 +OP4 E00C83 0 +OP4 E00C84 0 +OP4 E00C85 0 +OP4 E00C86 0 +OP4 E00C87 0 +OP4 E00C88 0 +OP4 E00C89 0 +OP4 E00C8A 0 +OP4 E00C8B 0 +OP4 E00C8C 0 +OP4 E00C8D 0 +OP4 E00C8E 0 +OP4 E00C8F 0 +OP4 E00C90 0 +OP4 E00C91 0 +OP4 E00C92 0 +OP4 E00C93 0 +OP4 E00C94 0 +OP4 E00C95 0 +OP4 E00C96 0 +OP4 E00C97 0 +OP4 E00C98 0 +OP4 E00C99 0 +OP4 E00C9A 0 +OP4 E00C9B 0 +OP4 E00C9C 0 +OP4 E00C9D 0 +OP4 E00C9E 0 +OP4 E00C9F 0 +OP4 E00CA0 0 +OP4 E00CA1 0 +OP4 E00CA2 0 +OP4 E00CA3 0 +OP4 E00CA4 0 +OP4 E00CA5 0 +OP4 E00CA6 0 +OP4 E00CA7 0 +OP4 E00CA8 0 +OP4 E00CA9 0 +OP4 E00CAA 0 +OP4 E00CAB 0 +OP4 E00CAC 0 +OP4 E00CAD 0 +OP4 E00CAE 0 +OP4 E00CAF 0 +OP4 E00CB0 0 +OP4 E00CB1 0 +OP4 E00CB2 0 +OP4 E00CB3 0 +OP4 E00CB4 0 +OP4 E00CB5 0 +OP4 E00CB6 0 +OP4 E00CB7 0 +OP4 E00CB8 0 +OP4 E00CB9 0 +OP4 E00CBA 0 +OP4 E00CBB 0 +OP4 E00CBC 0 +OP4 E00CBD 0 +OP4 E00CBE 0 +OP4 E00CBF 0 +OP4 E00CC0 0 +OP4 E00CC1 0 +OP4 E00CC2 0 +OP4 E00CC3 0 +OP4 E00CC4 0 +OP4 E00CC5 0 +OP4 E00CC6 0 +OP4 E00CC7 0 +OP4 E00CC8 0 +OP4 E00CC9 0 +OP4 E00CCA 0 +OP4 E00CCB 0 +OP4 E00CCC 0 +OP4 E00CCD 0 +OP4 E00CCE 0 +OP4 E00CCF 0 +OP4 E00CD0 0 +OP4 E00CD1 0 +OP4 E00CD2 0 +OP4 E00CD3 0 +OP4 E00CD4 0 +OP4 E00CD5 0 +OP4 E00CD6 0 +OP4 E00CD7 0 +OP4 E00CD8 0 +OP4 E00CD9 0 +OP4 E00CDA 0 +OP4 E00CDB 0 +OP4 E00CDC 0 +OP4 E00CDD 0 +OP4 E00CDE 0 +OP4 E00CDF 0 +OP4 E00CE0 0 +OP4 E00CE1 0 +OP4 E00CE2 0 +OP4 E00CE3 0 +OP4 E00CE4 0 +OP4 E00CE5 0 +OP4 E00CE6 0 +OP4 E00CE7 0 +OP4 E00CE8 0 +OP4 E00CE9 0 +OP4 E00CEA 0 +OP4 E00CEB 0 +OP4 E00CEC 0 +OP4 E00CED 0 +OP4 E00CEE 0 +OP4 E00CEF 0 +OP4 E00CF0 0 +OP4 E00CF1 0 +OP4 E00CF2 0 +OP4 E00CF3 0 +OP4 E00CF4 0 +OP4 E00CF5 0 +OP4 E00CF6 0 +OP4 E00CF7 0 +OP4 E00CF8 0 +OP4 E00CF9 0 +OP4 E00CFA 0 +OP4 E00CFB 0 +OP4 E00CFC 0 +OP4 E00CFD 0 +OP4 E00CFE 0 +OP4 E00CFF 0 +OP4 E00D00 0 +OP4 E00D01 0 +OP4 E00D02 0 +OP4 E00D03 0 +OP4 E00D04 0 +OP4 E00D05 0 +OP4 E00D06 0 +OP4 E00D07 0 +OP4 E00D08 0 +OP4 E00D09 0 +OP4 E00D0A 0 +OP4 E00D0B 0 +OP4 E00D0C 0 +OP4 E00D0D 0 +OP4 E00D0E 0 +OP4 E00D0F 0 +OP4 E00D10 0 +OP4 E00D11 0 +OP4 E00D12 0 +OP4 E00D13 0 +OP4 E00D14 0 +OP4 E00D15 0 +OP4 E00D16 0 +OP4 E00D17 0 +OP4 E00D18 0 +OP4 E00D19 0 +OP4 E00D1A 0 +OP4 E00D1B 0 +OP4 E00D1C 0 +OP4 E00D1D 0 +OP4 E00D1E 0 +OP4 E00D1F 0 +OP4 E00D20 0 +OP4 E00D21 0 +OP4 E00D22 0 +OP4 E00D23 0 +OP4 E00D24 0 +OP4 E00D25 0 +OP4 E00D26 0 +OP4 E00D27 0 +OP4 E00D28 0 +OP4 E00D29 0 +OP4 E00D2A 0 +OP4 E00D2B 0 +OP4 E00D2C 0 +OP4 E00D2D 0 +OP4 E00D2E 0 +OP4 E00D2F 0 +OP4 E00D30 0 +OP4 E00D31 0 +OP4 E00D32 0 +OP4 E00D33 0 +OP4 E00D34 0 +OP4 E00D35 0 +OP4 E00D36 0 +OP4 E00D37 0 +OP4 E00D38 0 +OP4 E00D39 0 +OP4 E00D3A 0 +OP4 E00D3B 0 +OP4 E00D3C 0 +OP4 E00D3D 0 +OP4 E00D3E 0 +OP4 E00D3F 0 +OP4 E00D40 0 +OP4 E00D41 0 +OP4 E00D42 0 +OP4 E00D43 0 +OP4 E00D44 0 +OP4 E00D45 0 +OP4 E00D46 0 +OP4 E00D47 0 +OP4 E00D48 0 +OP4 E00D49 0 +OP4 E00D4A 0 +OP4 E00D4B 0 +OP4 E00D4C 0 +OP4 E00D4D 0 +OP4 E00D4E 0 +OP4 E00D4F 0 +OP4 E00D50 0 +OP4 E00D51 0 +OP4 E00D52 0 +OP4 E00D53 0 +OP4 E00D54 0 +OP4 E00D55 0 +OP4 E00D56 0 +OP4 E00D57 0 +OP4 E00D58 0 +OP4 E00D59 0 +OP4 E00D5A 0 +OP4 E00D5B 0 +OP4 E00D5C 0 +OP4 E00D5D 0 +OP4 E00D5E 0 +OP4 E00D5F 0 +OP4 E00D60 0 +OP4 E00D61 0 +OP4 E00D62 0 +OP4 E00D63 0 +OP4 E00D64 0 +OP4 E00D65 0 +OP4 E00D66 0 +OP4 E00D67 0 +OP4 E00D68 0 +OP4 E00D69 0 +OP4 E00D6A 0 +OP4 E00D6B 0 +OP4 E00D6C 0 +OP4 E00D6D 0 +OP4 E00D6E 0 +OP4 E00D6F 0 +OP4 E00D70 0 +OP4 E00D71 0 +OP4 E00D72 0 +OP4 E00D73 0 +OP4 E00D74 0 +OP4 E00D75 0 +OP4 E00D76 0 +OP4 E00D77 0 +OP4 E00D78 0 +OP4 E00D79 0 +OP4 E00D7A 0 +OP4 E00D7B 0 +OP4 E00D7C 0 +OP4 E00D7D 0 +OP4 E00D7E 0 +OP4 E00D7F 0 +OP4 E00D80 0 +OP4 E00D81 0 +OP4 E00D82 0 +OP4 E00D83 0 +OP4 E00D84 0 +OP4 E00D85 0 +OP4 E00D86 0 +OP4 E00D87 0 +OP4 E00D88 0 +OP4 E00D89 0 +OP4 E00D8A 0 +OP4 E00D8B 0 +OP4 E00D8C 0 +OP4 E00D8D 0 +OP4 E00D8E 0 +OP4 E00D8F 0 +OP4 E00D90 0 +OP4 E00D91 0 +OP4 E00D92 0 +OP4 E00D93 0 +OP4 E00D94 0 +OP4 E00D95 0 +OP4 E00D96 0 +OP4 E00D97 0 +OP4 E00D98 0 +OP4 E00D99 0 +OP4 E00D9A 0 +OP4 E00D9B 0 +OP4 E00D9C 0 +OP4 E00D9D 0 +OP4 E00D9E 0 +OP4 E00D9F 0 +OP4 E00DA0 0 +OP4 E00DA1 0 +OP4 E00DA2 0 +OP4 E00DA3 0 +OP4 E00DA4 0 +OP4 E00DA5 0 +OP4 E00DA6 0 +OP4 E00DA7 0 +OP4 E00DA8 0 +OP4 E00DA9 0 +OP4 E00DAA 0 +OP4 E00DAB 0 +OP4 E00DAC 0 +OP4 E00DAD 0 +OP4 E00DAE 0 +OP4 E00DAF 0 +OP4 E00DB0 0 +OP4 E00DB1 0 +OP4 E00DB2 0 +OP4 E00DB3 0 +OP4 E00DB4 0 +OP4 E00DB5 0 +OP4 E00DB6 0 +OP4 E00DB7 0 +OP4 E00DB8 0 +OP4 E00DB9 0 +OP4 E00DBA 0 +OP4 E00DBB 0 +OP4 E00DBC 0 +OP4 E00DBD 0 +OP4 E00DBE 0 +OP4 E00DBF 0 +OP4 E00DC0 0 +OP4 E00DC1 0 +OP4 E00DC2 0 +OP4 E00DC3 0 +OP4 E00DC4 0 +OP4 E00DC5 0 +OP4 E00DC6 0 +OP4 E00DC7 0 +OP4 E00DC8 0 +OP4 E00DC9 0 +OP4 E00DCA 0 +OP4 E00DCB 0 +OP4 E00DCC 0 +OP4 E00DCD 0 +OP4 E00DCE 0 +OP4 E00DCF 0 +OP4 E00DD0 0 +OP4 E00DD1 0 +OP4 E00DD2 0 +OP4 E00DD3 0 +OP4 E00DD4 0 +OP4 E00DD5 0 +OP4 E00DD6 0 +OP4 E00DD7 0 +OP4 E00DD8 0 +OP4 E00DD9 0 +OP4 E00DDA 0 +OP4 E00DDB 0 +OP4 E00DDC 0 +OP4 E00DDD 0 +OP4 E00DDE 0 +OP4 E00DDF 0 +OP4 E00DE0 0 +OP4 E00DE1 0 +OP4 E00DE2 0 +OP4 E00DE3 0 +OP4 E00DE4 0 +OP4 E00DE5 0 +OP4 E00DE6 0 +OP4 E00DE7 0 +OP4 E00DE8 0 +OP4 E00DE9 0 +OP4 E00DEA 0 +OP4 E00DEB 0 +OP4 E00DEC 0 +OP4 E00DED 0 +OP4 E00DEE 0 +OP4 E00DEF 0 +OP4 E00DF0 0 +OP4 E00DF1 0 +OP4 E00DF2 0 +OP4 E00DF3 0 +OP4 E00DF4 0 +OP4 E00DF5 0 +OP4 E00DF6 0 +OP4 E00DF7 0 +OP4 E00DF8 0 +OP4 E00DF9 0 +OP4 E00DFA 0 +OP4 E00DFB 0 +OP4 E00DFC 0 +OP4 E00DFD 0 +OP4 E00DFE 0 +OP4 E00DFF 0 +OP4 E00E00 0 +OP4 E00E01 0 +OP4 E00E02 0 +OP4 E00E03 0 +OP4 E00E04 0 +OP4 E00E05 0 +OP4 E00E06 0 +OP4 E00E07 0 +OP4 E00E08 0 +OP4 E00E09 0 +OP4 E00E0A 0 +OP4 E00E0B 0 +OP4 E00E0C 0 +OP4 E00E0D 0 +OP4 E00E0E 0 +OP4 E00E0F 0 +OP4 E00E10 0 +OP4 E00E11 0 +OP4 E00E12 0 +OP4 E00E13 0 +OP4 E00E14 0 +OP4 E00E15 0 +OP4 E00E16 0 +OP4 E00E17 0 +OP4 E00E18 0 +OP4 E00E19 0 +OP4 E00E1A 0 +OP4 E00E1B 0 +OP4 E00E1C 0 +OP4 E00E1D 0 +OP4 E00E1E 0 +OP4 E00E1F 0 +OP4 E00E20 0 +OP4 E00E21 0 +OP4 E00E22 0 +OP4 E00E23 0 +OP4 E00E24 0 +OP4 E00E25 0 +OP4 E00E26 0 +OP4 E00E27 0 +OP4 E00E28 0 +OP4 E00E29 0 +OP4 E00E2A 0 +OP4 E00E2B 0 +OP4 E00E2C 0 +OP4 E00E2D 0 +OP4 E00E2E 0 +OP4 E00E2F 0 +OP4 E00E30 0 +OP4 E00E31 0 +OP4 E00E32 0 +OP4 E00E33 0 +OP4 E00E34 0 +OP4 E00E35 0 +OP4 E00E36 0 +OP4 E00E37 0 +OP4 E00E38 0 +OP4 E00E39 0 +OP4 E00E3A 0 +OP4 E00E3B 0 +OP4 E00E3C 0 +OP4 E00E3D 0 +OP4 E00E3E 0 +OP4 E00E3F 0 +OP4 E00E40 0 +OP4 E00E41 0 +OP4 E00E42 0 +OP4 E00E43 0 +OP4 E00E44 0 +OP4 E00E45 0 +OP4 E00E46 0 +OP4 E00E47 0 +OP4 E00E48 0 +OP4 E00E49 0 +OP4 E00E4A 0 +OP4 E00E4B 0 +OP4 E00E4C 0 +OP4 E00E4D 0 +OP4 E00E4E 0 +OP4 E00E4F 0 +OP4 E00E50 0 +OP4 E00E51 0 +OP4 E00E52 0 +OP4 E00E53 0 +OP4 E00E54 0 +OP4 E00E55 0 +OP4 E00E56 0 +OP4 E00E57 0 +OP4 E00E58 0 +OP4 E00E59 0 +OP4 E00E5A 0 +OP4 E00E5B 0 +OP4 E00E5C 0 +OP4 E00E5D 0 +OP4 E00E5E 0 +OP4 E00E5F 0 +OP4 E00E60 0 +OP4 E00E61 0 +OP4 E00E62 0 +OP4 E00E63 0 +OP4 E00E64 0 +OP4 E00E65 0 +OP4 E00E66 0 +OP4 E00E67 0 +OP4 E00E68 0 +OP4 E00E69 0 +OP4 E00E6A 0 +OP4 E00E6B 0 +OP4 E00E6C 0 +OP4 E00E6D 0 +OP4 E00E6E 0 +OP4 E00E6F 0 +OP4 E00E70 0 +OP4 E00E71 0 +OP4 E00E72 0 +OP4 E00E73 0 +OP4 E00E74 0 +OP4 E00E75 0 +OP4 E00E76 0 +OP4 E00E77 0 +OP4 E00E78 0 +OP4 E00E79 0 +OP4 E00E7A 0 +OP4 E00E7B 0 +OP4 E00E7C 0 +OP4 E00E7D 0 +OP4 E00E7E 0 +OP4 E00E7F 0 +OP4 E00E80 0 +OP4 E00E81 0 +OP4 E00E82 0 +OP4 E00E83 0 +OP4 E00E84 0 +OP4 E00E85 0 +OP4 E00E86 0 +OP4 E00E87 0 +OP4 E00E88 0 +OP4 E00E89 0 +OP4 E00E8A 0 +OP4 E00E8B 0 +OP4 E00E8C 0 +OP4 E00E8D 0 +OP4 E00E8E 0 +OP4 E00E8F 0 +OP4 E00E90 0 +OP4 E00E91 0 +OP4 E00E92 0 +OP4 E00E93 0 +OP4 E00E94 0 +OP4 E00E95 0 +OP4 E00E96 0 +OP4 E00E97 0 +OP4 E00E98 0 +OP4 E00E99 0 +OP4 E00E9A 0 +OP4 E00E9B 0 +OP4 E00E9C 0 +OP4 E00E9D 0 +OP4 E00E9E 0 +OP4 E00E9F 0 +OP4 E00EA0 0 +OP4 E00EA1 0 +OP4 E00EA2 0 +OP4 E00EA3 0 +OP4 E00EA4 0 +OP4 E00EA5 0 +OP4 E00EA6 0 +OP4 E00EA7 0 +OP4 E00EA8 0 +OP4 E00EA9 0 +OP4 E00EAA 0 +OP4 E00EAB 0 +OP4 E00EAC 0 +OP4 E00EAD 0 +OP4 E00EAE 0 +OP4 E00EAF 0 +OP4 E00EB0 0 +OP4 E00EB1 0 +OP4 E00EB2 0 +OP4 E00EB3 0 +OP4 E00EB4 0 +OP4 E00EB5 0 +OP4 E00EB6 0 +OP4 E00EB7 0 +OP4 E00EB8 0 +OP4 E00EB9 0 +OP4 E00EBA 0 +OP4 E00EBB 0 +OP4 E00EBC 0 +OP4 E00EBD 0 +OP4 E00EBE 0 +OP4 E00EBF 0 +OP4 E00EC0 0 +OP4 E00EC1 0 +OP4 E00EC2 0 +OP4 E00EC3 0 +OP4 E00EC4 0 +OP4 E00EC5 0 +OP4 E00EC6 0 +OP4 E00EC7 0 +OP4 E00EC8 0 +OP4 E00EC9 0 +OP4 E00ECA 0 +OP4 E00ECB 0 +OP4 E00ECC 0 +OP4 E00ECD 0 +OP4 E00ECE 0 +OP4 E00ECF 0 +OP4 E00ED0 0 +OP4 E00ED1 0 +OP4 E00ED2 0 +OP4 E00ED3 0 +OP4 E00ED4 0 +OP4 E00ED5 0 +OP4 E00ED6 0 +OP4 E00ED7 0 +OP4 E00ED8 0 +OP4 E00ED9 0 +OP4 E00EDA 0 +OP4 E00EDB 0 +OP4 E00EDC 0 +OP4 E00EDD 0 +OP4 E00EDE 0 +OP4 E00EDF 0 +OP4 E00EE0 0 +OP4 E00EE1 0 +OP4 E00EE2 0 +OP4 E00EE3 0 +OP4 E00EE4 0 +OP4 E00EE5 0 +OP4 E00EE6 0 +OP4 E00EE7 0 +OP4 E00EE8 0 +OP4 E00EE9 0 +OP4 E00EEA 0 +OP4 E00EEB 0 +OP4 E00EEC 0 +OP4 E00EED 0 +OP4 E00EEE 0 +OP4 E00EEF 0 +OP4 E00EF0 0 +OP4 E00EF1 0 +OP4 E00EF2 0 +OP4 E00EF3 0 +OP4 E00EF4 0 +OP4 E00EF5 0 +OP4 E00EF6 0 +OP4 E00EF7 0 +OP4 E00EF8 0 +OP4 E00EF9 0 +OP4 E00EFA 0 +OP4 E00EFB 0 +OP4 E00EFC 0 +OP4 E00EFD 0 +OP4 E00EFE 0 +OP4 E00EFF 0 +OP4 E00F00 0 +OP4 E00F01 0 +OP4 E00F02 0 +OP4 E00F03 0 +OP4 E00F04 0 +OP4 E00F05 0 +OP4 E00F06 0 +OP4 E00F07 0 +OP4 E00F08 0 +OP4 E00F09 0 +OP4 E00F0A 0 +OP4 E00F0B 0 +OP4 E00F0C 0 +OP4 E00F0D 0 +OP4 E00F0E 0 +OP4 E00F0F 0 +OP4 E00F10 0 +OP4 E00F11 0 +OP4 E00F12 0 +OP4 E00F13 0 +OP4 E00F14 0 +OP4 E00F15 0 +OP4 E00F16 0 +OP4 E00F17 0 +OP4 E00F18 0 +OP4 E00F19 0 +OP4 E00F1A 0 +OP4 E00F1B 0 +OP4 E00F1C 0 +OP4 E00F1D 0 +OP4 E00F1E 0 +OP4 E00F1F 0 +OP4 E00F20 0 +OP4 E00F21 0 +OP4 E00F22 0 +OP4 E00F23 0 +OP4 E00F24 0 +OP4 E00F25 0 +OP4 E00F26 0 +OP4 E00F27 0 +OP4 E00F28 0 +OP4 E00F29 0 +OP4 E00F2A 0 +OP4 E00F2B 0 +OP4 E00F2C 0 +OP4 E00F2D 0 +OP4 E00F2E 0 +OP4 E00F2F 0 +OP4 E00F30 0 diff --git a/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum3_itrace_irisc4.cfg.ext b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum3_itrace_irisc4.cfg.ext new file mode 100644 index 000000000000..a8b034cbfef4 --- /dev/null +++ b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum3_itrace_irisc4.cfg.ext @@ -0,0 +1,3890 @@ +OP1 Spectrum3 +OP4 ITRACE0 0 +OP4 ITRACE1 0 +OP4 ITRACE2 0 +OP4 ITRACE3 0 +OP4 ITRACE4 1 +OP4 ITRACE5 0 +OP4 ITRACE6 0 +OP4 ITRACE7 0 +OP4 ITRACE8 0 +OP4 ITRACE9 0 +OP4 Main_PhyUC 0 +OP4 TILE0_ITRACE0 0 +OP4 TILE0_ITRACE1 0 +OP4 TILE0_ITRACE2 0 +OP4 TILE0_ITRACE3 0 +OP4 TILE0_ITRACE4 0 +OP4 TILE0_PhyUC 0 +OP4 TILE1_ITRACE0 0 +OP4 TILE1_ITRACE1 0 +OP4 TILE1_ITRACE2 0 +OP4 TILE1_ITRACE3 0 +OP4 TILE1_ITRACE4 0 +OP4 TILE1_PhyUC 0 +OP4 TILE2_ITRACE0 0 +OP4 TILE2_ITRACE1 0 +OP4 TILE2_ITRACE2 0 +OP4 TILE2_ITRACE3 0 +OP4 TILE2_ITRACE4 0 +OP4 TILE2_PhyUC 0 +OP4 TILE3_ITRACE0 0 +OP4 TILE3_ITRACE1 0 +OP4 TILE3_ITRACE2 0 +OP4 TILE3_ITRACE3 0 +OP4 TILE3_ITRACE4 0 +OP4 TILE3_PhyUC 0 +OP4 TILE4_ITRACE0 0 +OP4 TILE4_ITRACE1 0 +OP4 TILE4_ITRACE2 0 +OP4 TILE4_ITRACE3 0 +OP4 TILE4_ITRACE4 0 +OP4 TILE4_PhyUC 0 +OP4 TILE5_ITRACE0 0 +OP4 TILE5_ITRACE1 0 +OP4 TILE5_ITRACE2 0 +OP4 TILE5_ITRACE3 0 +OP4 TILE5_ITRACE4 0 +OP4 TILE5_PhyUC 0 +OP4 TILE6_ITRACE0 0 +OP4 TILE6_ITRACE1 0 +OP4 TILE6_ITRACE2 0 +OP4 TILE6_ITRACE3 0 +OP4 TILE6_ITRACE4 0 +OP4 TILE6_PhyUC 0 +OP4 TILE7_ITRACE0 0 +OP4 TILE7_ITRACE1 0 +OP4 TILE7_ITRACE2 0 +OP4 TILE7_ITRACE3 0 +OP4 TILE7_ITRACE4 0 +OP4 TILE7_PhyUC 0 +OP4 E0003B 0 +OP4 E0003C 0 +OP4 E0003D 0 +OP4 E0003E 0 +OP4 E0003F 0 +OP4 E00040 0 +OP4 E00041 0 +OP4 E00042 0 +OP4 E00043 0 +OP4 E00044 0 +OP4 E00045 0 +OP4 E00046 0 +OP4 E00047 0 +OP4 E00048 0 +OP4 E00049 0 +OP4 E0004A 0 +OP4 E0004B 0 +OP4 E0004C 0 +OP4 E0004D 0 +OP4 E0004E 0 +OP4 E0004F 0 +OP4 E00050 0 +OP4 E00051 0 +OP4 E00052 0 +OP4 E00053 0 +OP4 E00054 0 +OP4 E00055 0 +OP4 E00056 0 +OP4 E00057 0 +OP4 E00058 0 +OP4 E00059 0 +OP4 E0005A 0 +OP4 E0005B 0 +OP4 E0005C 0 +OP4 E0005D 0 +OP4 E0005E 0 +OP4 E0005F 0 +OP4 E00060 0 +OP4 E00061 0 +OP4 E00062 0 +OP4 E00063 0 +OP4 E00064 0 +OP4 E00065 0 +OP4 E00066 0 +OP4 E00067 0 +OP4 E00068 0 +OP4 E00069 0 +OP4 E0006A 0 +OP4 E0006B 0 +OP4 E0006C 0 +OP4 E0006D 0 +OP4 E0006E 0 +OP4 E0006F 0 +OP4 E00070 0 +OP4 E00071 0 +OP4 E00072 0 +OP4 E00073 0 +OP4 E00074 0 +OP4 E00075 0 +OP4 E00076 0 +OP4 E00077 0 +OP4 E00078 0 +OP4 E00079 0 +OP4 E0007A 0 +OP4 E0007B 0 +OP4 E0007C 0 +OP4 E0007D 0 +OP4 E0007E 0 +OP4 E0007F 0 +OP4 E00080 0 +OP4 E00081 0 +OP4 E00082 0 +OP4 E00083 0 +OP4 E00084 0 +OP4 E00085 0 +OP4 E00086 0 +OP4 E00087 0 +OP4 E00088 0 +OP4 E00089 0 +OP4 E0008A 0 +OP4 E0008B 0 +OP4 E0008C 0 +OP4 E0008D 0 +OP4 E0008E 0 +OP4 E0008F 0 +OP4 E00090 0 +OP4 E00091 0 +OP4 E00092 0 +OP4 E00093 0 +OP4 E00094 0 +OP4 E00095 0 +OP4 E00096 0 +OP4 E00097 0 +OP4 E00098 0 +OP4 E00099 0 +OP4 E0009A 0 +OP4 E0009B 0 +OP4 E0009C 0 +OP4 E0009D 0 +OP4 E0009E 0 +OP4 E0009F 0 +OP4 E000A0 0 +OP4 E000A1 0 +OP4 E000A2 0 +OP4 E000A3 0 +OP4 E000A4 0 +OP4 E000A5 0 +OP4 E000A6 0 +OP4 E000A7 0 +OP4 E000A8 0 +OP4 E000A9 0 +OP4 E000AA 0 +OP4 E000AB 0 +OP4 E000AC 0 +OP4 E000AD 0 +OP4 E000AE 0 +OP4 E000AF 0 +OP4 E000B0 0 +OP4 E000B1 0 +OP4 E000B2 0 +OP4 E000B3 0 +OP4 E000B4 0 +OP4 E000B5 0 +OP4 E000B6 0 +OP4 E000B7 0 +OP4 E000B8 0 +OP4 E000B9 0 +OP4 E000BA 0 +OP4 E000BB 0 +OP4 E000BC 0 +OP4 E000BD 0 +OP4 E000BE 0 +OP4 E000BF 0 +OP4 E000C0 0 +OP4 E000C1 0 +OP4 E000C2 0 +OP4 E000C3 0 +OP4 E000C4 0 +OP4 E000C5 0 +OP4 E000C6 0 +OP4 E000C7 0 +OP4 E000C8 0 +OP4 E000C9 0 +OP4 E000CA 0 +OP4 E000CB 0 +OP4 E000CC 0 +OP4 E000CD 0 +OP4 E000CE 0 +OP4 E000CF 0 +OP4 E000D0 0 +OP4 E000D1 0 +OP4 E000D2 0 +OP4 E000D3 0 +OP4 E000D4 0 +OP4 E000D5 0 +OP4 E000D6 0 +OP4 E000D7 0 +OP4 E000D8 0 +OP4 E000D9 0 +OP4 E000DA 0 +OP4 E000DB 0 +OP4 E000DC 0 +OP4 E000DD 0 +OP4 E000DE 0 +OP4 E000DF 0 +OP4 E000E0 0 +OP4 E000E1 0 +OP4 E000E2 0 +OP4 E000E3 0 +OP4 E000E4 0 +OP4 E000E5 0 +OP4 E000E6 0 +OP4 E000E7 0 +OP4 E000E8 0 +OP4 E000E9 0 +OP4 E000EA 0 +OP4 E000EB 0 +OP4 E000EC 0 +OP4 E000ED 0 +OP4 E000EE 0 +OP4 E000EF 0 +OP4 E000F0 0 +OP4 E000F1 0 +OP4 E000F2 0 +OP4 E000F3 0 +OP4 E000F4 0 +OP4 E000F5 0 +OP4 E000F6 0 +OP4 E000F7 0 +OP4 E000F8 0 +OP4 E000F9 0 +OP4 E000FA 0 +OP4 E000FB 0 +OP4 E000FC 0 +OP4 E000FD 0 +OP4 E000FE 0 +OP4 E000FF 0 +OP4 E00100 0 +OP4 E00101 0 +OP4 E00102 0 +OP4 E00103 0 +OP4 E00104 0 +OP4 E00105 0 +OP4 E00106 0 +OP4 E00107 0 +OP4 E00108 0 +OP4 E00109 0 +OP4 E0010A 0 +OP4 E0010B 0 +OP4 E0010C 0 +OP4 E0010D 0 +OP4 E0010E 0 +OP4 E0010F 0 +OP4 E00110 0 +OP4 E00111 0 +OP4 E00112 0 +OP4 E00113 0 +OP4 E00114 0 +OP4 E00115 0 +OP4 E00116 0 +OP4 E00117 0 +OP4 E00118 0 +OP4 E00119 0 +OP4 E0011A 0 +OP4 E0011B 0 +OP4 E0011C 0 +OP4 E0011D 0 +OP4 E0011E 0 +OP4 E0011F 0 +OP4 E00120 0 +OP4 E00121 0 +OP4 E00122 0 +OP4 E00123 0 +OP4 E00124 0 +OP4 E00125 0 +OP4 E00126 0 +OP4 E00127 0 +OP4 E00128 0 +OP4 E00129 0 +OP4 E0012A 0 +OP4 E0012B 0 +OP4 E0012C 0 +OP4 E0012D 0 +OP4 E0012E 0 +OP4 E0012F 0 +OP4 E00130 0 +OP4 E00131 0 +OP4 E00132 0 +OP4 E00133 0 +OP4 E00134 0 +OP4 E00135 0 +OP4 E00136 0 +OP4 E00137 0 +OP4 E00138 0 +OP4 E00139 0 +OP4 E0013A 0 +OP4 E0013B 0 +OP4 E0013C 0 +OP4 E0013D 0 +OP4 E0013E 0 +OP4 E0013F 0 +OP4 E00140 0 +OP4 E00141 0 +OP4 E00142 0 +OP4 E00143 0 +OP4 E00144 0 +OP4 E00145 0 +OP4 E00146 0 +OP4 E00147 0 +OP4 E00148 0 +OP4 E00149 0 +OP4 E0014A 0 +OP4 E0014B 0 +OP4 E0014C 0 +OP4 E0014D 0 +OP4 E0014E 0 +OP4 E0014F 0 +OP4 E00150 0 +OP4 E00151 0 +OP4 E00152 0 +OP4 E00153 0 +OP4 E00154 0 +OP4 E00155 0 +OP4 E00156 0 +OP4 E00157 0 +OP4 E00158 0 +OP4 E00159 0 +OP4 E0015A 0 +OP4 E0015B 0 +OP4 E0015C 0 +OP4 E0015D 0 +OP4 E0015E 0 +OP4 E0015F 0 +OP4 E00160 0 +OP4 E00161 0 +OP4 E00162 0 +OP4 E00163 0 +OP4 E00164 0 +OP4 E00165 0 +OP4 E00166 0 +OP4 E00167 0 +OP4 E00168 0 +OP4 E00169 0 +OP4 E0016A 0 +OP4 E0016B 0 +OP4 E0016C 0 +OP4 E0016D 0 +OP4 E0016E 0 +OP4 E0016F 0 +OP4 E00170 0 +OP4 E00171 0 +OP4 E00172 0 +OP4 E00173 0 +OP4 E00174 0 +OP4 E00175 0 +OP4 E00176 0 +OP4 E00177 0 +OP4 E00178 0 +OP4 E00179 0 +OP4 E0017A 0 +OP4 E0017B 0 +OP4 E0017C 0 +OP4 E0017D 0 +OP4 E0017E 0 +OP4 E0017F 0 +OP4 E00180 0 +OP4 E00181 0 +OP4 E00182 0 +OP4 E00183 0 +OP4 E00184 0 +OP4 E00185 0 +OP4 E00186 0 +OP4 E00187 0 +OP4 E00188 0 +OP4 E00189 0 +OP4 E0018A 0 +OP4 E0018B 0 +OP4 E0018C 0 +OP4 E0018D 0 +OP4 E0018E 0 +OP4 E0018F 0 +OP4 E00190 0 +OP4 E00191 0 +OP4 E00192 0 +OP4 E00193 0 +OP4 E00194 0 +OP4 E00195 0 +OP4 E00196 0 +OP4 E00197 0 +OP4 E00198 0 +OP4 E00199 0 +OP4 E0019A 0 +OP4 E0019B 0 +OP4 E0019C 0 +OP4 E0019D 0 +OP4 E0019E 0 +OP4 E0019F 0 +OP4 E001A0 0 +OP4 E001A1 0 +OP4 E001A2 0 +OP4 E001A3 0 +OP4 E001A4 0 +OP4 E001A5 0 +OP4 E001A6 0 +OP4 E001A7 0 +OP4 E001A8 0 +OP4 E001A9 0 +OP4 E001AA 0 +OP4 E001AB 0 +OP4 E001AC 0 +OP4 E001AD 0 +OP4 E001AE 0 +OP4 E001AF 0 +OP4 E001B0 0 +OP4 E001B1 0 +OP4 E001B2 0 +OP4 E001B3 0 +OP4 E001B4 0 +OP4 E001B5 0 +OP4 E001B6 0 +OP4 E001B7 0 +OP4 E001B8 0 +OP4 E001B9 0 +OP4 E001BA 0 +OP4 E001BB 0 +OP4 E001BC 0 +OP4 E001BD 0 +OP4 E001BE 0 +OP4 E001BF 0 +OP4 E001C0 0 +OP4 E001C1 0 +OP4 E001C2 0 +OP4 E001C3 0 +OP4 E001C4 0 +OP4 E001C5 0 +OP4 E001C6 0 +OP4 E001C7 0 +OP4 E001C8 0 +OP4 E001C9 0 +OP4 E001CA 0 +OP4 E001CB 0 +OP4 E001CC 0 +OP4 E001CD 0 +OP4 E001CE 0 +OP4 E001CF 0 +OP4 E001D0 0 +OP4 E001D1 0 +OP4 E001D2 0 +OP4 E001D3 0 +OP4 E001D4 0 +OP4 E001D5 0 +OP4 E001D6 0 +OP4 E001D7 0 +OP4 E001D8 0 +OP4 E001D9 0 +OP4 E001DA 0 +OP4 E001DB 0 +OP4 E001DC 0 +OP4 E001DD 0 +OP4 E001DE 0 +OP4 E001DF 0 +OP4 E001E0 0 +OP4 E001E1 0 +OP4 E001E2 0 +OP4 E001E3 0 +OP4 E001E4 0 +OP4 E001E5 0 +OP4 E001E6 0 +OP4 E001E7 0 +OP4 E001E8 0 +OP4 E001E9 0 +OP4 E001EA 0 +OP4 E001EB 0 +OP4 E001EC 0 +OP4 E001ED 0 +OP4 E001EE 0 +OP4 E001EF 0 +OP4 E001F0 0 +OP4 E001F1 0 +OP4 E001F2 0 +OP4 E001F3 0 +OP4 E001F4 0 +OP4 E001F5 0 +OP4 E001F6 0 +OP4 E001F7 0 +OP4 E001F8 0 +OP4 E001F9 0 +OP4 E001FA 0 +OP4 E001FB 0 +OP4 E001FC 0 +OP4 E001FD 0 +OP4 E001FE 0 +OP4 E001FF 0 +OP4 E00200 0 +OP4 E00201 0 +OP4 E00202 0 +OP4 E00203 0 +OP4 E00204 0 +OP4 E00205 0 +OP4 E00206 0 +OP4 E00207 0 +OP4 E00208 0 +OP4 E00209 0 +OP4 E0020A 0 +OP4 E0020B 0 +OP4 E0020C 0 +OP4 E0020D 0 +OP4 E0020E 0 +OP4 E0020F 0 +OP4 E00210 0 +OP4 E00211 0 +OP4 E00212 0 +OP4 E00213 0 +OP4 E00214 0 +OP4 E00215 0 +OP4 E00216 0 +OP4 E00217 0 +OP4 E00218 0 +OP4 E00219 0 +OP4 E0021A 0 +OP4 E0021B 0 +OP4 E0021C 0 +OP4 E0021D 0 +OP4 E0021E 0 +OP4 E0021F 0 +OP4 E00220 0 +OP4 E00221 0 +OP4 E00222 0 +OP4 E00223 0 +OP4 E00224 0 +OP4 E00225 0 +OP4 E00226 0 +OP4 E00227 0 +OP4 E00228 0 +OP4 E00229 0 +OP4 E0022A 0 +OP4 E0022B 0 +OP4 E0022C 0 +OP4 E0022D 0 +OP4 E0022E 0 +OP4 E0022F 0 +OP4 E00230 0 +OP4 E00231 0 +OP4 E00232 0 +OP4 E00233 0 +OP4 E00234 0 +OP4 E00235 0 +OP4 E00236 0 +OP4 E00237 0 +OP4 E00238 0 +OP4 E00239 0 +OP4 E0023A 0 +OP4 E0023B 0 +OP4 E0023C 0 +OP4 E0023D 0 +OP4 E0023E 0 +OP4 E0023F 0 +OP4 E00240 0 +OP4 E00241 0 +OP4 E00242 0 +OP4 E00243 0 +OP4 E00244 0 +OP4 E00245 0 +OP4 E00246 0 +OP4 E00247 0 +OP4 E00248 0 +OP4 E00249 0 +OP4 E0024A 0 +OP4 E0024B 0 +OP4 E0024C 0 +OP4 E0024D 0 +OP4 E0024E 0 +OP4 E0024F 0 +OP4 E00250 0 +OP4 E00251 0 +OP4 E00252 0 +OP4 E00253 0 +OP4 E00254 0 +OP4 E00255 0 +OP4 E00256 0 +OP4 E00257 0 +OP4 E00258 0 +OP4 E00259 0 +OP4 E0025A 0 +OP4 E0025B 0 +OP4 E0025C 0 +OP4 E0025D 0 +OP4 E0025E 0 +OP4 E0025F 0 +OP4 E00260 0 +OP4 E00261 0 +OP4 E00262 0 +OP4 E00263 0 +OP4 E00264 0 +OP4 E00265 0 +OP4 E00266 0 +OP4 E00267 0 +OP4 E00268 0 +OP4 E00269 0 +OP4 E0026A 0 +OP4 E0026B 0 +OP4 E0026C 0 +OP4 E0026D 0 +OP4 E0026E 0 +OP4 E0026F 0 +OP4 E00270 0 +OP4 E00271 0 +OP4 E00272 0 +OP4 E00273 0 +OP4 E00274 0 +OP4 E00275 0 +OP4 E00276 0 +OP4 E00277 0 +OP4 E00278 0 +OP4 E00279 0 +OP4 E0027A 0 +OP4 E0027B 0 +OP4 E0027C 0 +OP4 E0027D 0 +OP4 E0027E 0 +OP4 E0027F 0 +OP4 E00280 0 +OP4 E00281 0 +OP4 E00282 0 +OP4 E00283 0 +OP4 E00284 0 +OP4 E00285 0 +OP4 E00286 0 +OP4 E00287 0 +OP4 E00288 0 +OP4 E00289 0 +OP4 E0028A 0 +OP4 E0028B 0 +OP4 E0028C 0 +OP4 E0028D 0 +OP4 E0028E 0 +OP4 E0028F 0 +OP4 E00290 0 +OP4 E00291 0 +OP4 E00292 0 +OP4 E00293 0 +OP4 E00294 0 +OP4 E00295 0 +OP4 E00296 0 +OP4 E00297 0 +OP4 E00298 0 +OP4 E00299 0 +OP4 E0029A 0 +OP4 E0029B 0 +OP4 E0029C 0 +OP4 E0029D 0 +OP4 E0029E 0 +OP4 E0029F 0 +OP4 E002A0 0 +OP4 E002A1 0 +OP4 E002A2 0 +OP4 E002A3 0 +OP4 E002A4 0 +OP4 E002A5 0 +OP4 E002A6 0 +OP4 E002A7 0 +OP4 E002A8 0 +OP4 E002A9 0 +OP4 E002AA 0 +OP4 E002AB 0 +OP4 E002AC 0 +OP4 E002AD 0 +OP4 E002AE 0 +OP4 E002AF 0 +OP4 E002B0 0 +OP4 E002B1 0 +OP4 E002B2 0 +OP4 E002B3 0 +OP4 E002B4 0 +OP4 E002B5 0 +OP4 E002B6 0 +OP4 E002B7 0 +OP4 E002B8 0 +OP4 E002B9 0 +OP4 E002BA 0 +OP4 E002BB 0 +OP4 E002BC 0 +OP4 E002BD 0 +OP4 E002BE 0 +OP4 E002BF 0 +OP4 E002C0 0 +OP4 E002C1 0 +OP4 E002C2 0 +OP4 E002C3 0 +OP4 E002C4 0 +OP4 E002C5 0 +OP4 E002C6 0 +OP4 E002C7 0 +OP4 E002C8 0 +OP4 E002C9 0 +OP4 E002CA 0 +OP4 E002CB 0 +OP4 E002CC 0 +OP4 E002CD 0 +OP4 E002CE 0 +OP4 E002CF 0 +OP4 E002D0 0 +OP4 E002D1 0 +OP4 E002D2 0 +OP4 E002D3 0 +OP4 E002D4 0 +OP4 E002D5 0 +OP4 E002D6 0 +OP4 E002D7 0 +OP4 E002D8 0 +OP4 E002D9 0 +OP4 E002DA 0 +OP4 E002DB 0 +OP4 E002DC 0 +OP4 E002DD 0 +OP4 E002DE 0 +OP4 E002DF 0 +OP4 E002E0 0 +OP4 E002E1 0 +OP4 E002E2 0 +OP4 E002E3 0 +OP4 E002E4 0 +OP4 E002E5 0 +OP4 E002E6 0 +OP4 E002E7 0 +OP4 E002E8 0 +OP4 E002E9 0 +OP4 E002EA 0 +OP4 E002EB 0 +OP4 E002EC 0 +OP4 E002ED 0 +OP4 E002EE 0 +OP4 E002EF 0 +OP4 E002F0 0 +OP4 E002F1 0 +OP4 E002F2 0 +OP4 E002F3 0 +OP4 E002F4 0 +OP4 E002F5 0 +OP4 E002F6 0 +OP4 E002F7 0 +OP4 E002F8 0 +OP4 E002F9 0 +OP4 E002FA 0 +OP4 E002FB 0 +OP4 E002FC 0 +OP4 E002FD 0 +OP4 E002FE 0 +OP4 E002FF 0 +OP4 E00300 0 +OP4 E00301 0 +OP4 E00302 0 +OP4 E00303 0 +OP4 E00304 0 +OP4 E00305 0 +OP4 E00306 0 +OP4 E00307 0 +OP4 E00308 0 +OP4 E00309 0 +OP4 E0030A 0 +OP4 E0030B 0 +OP4 E0030C 0 +OP4 E0030D 0 +OP4 E0030E 0 +OP4 E0030F 0 +OP4 E00310 0 +OP4 E00311 0 +OP4 E00312 0 +OP4 E00313 0 +OP4 E00314 0 +OP4 E00315 0 +OP4 E00316 0 +OP4 E00317 0 +OP4 E00318 0 +OP4 E00319 0 +OP4 E0031A 0 +OP4 E0031B 0 +OP4 E0031C 0 +OP4 E0031D 0 +OP4 E0031E 0 +OP4 E0031F 0 +OP4 E00320 0 +OP4 E00321 0 +OP4 E00322 0 +OP4 E00323 0 +OP4 E00324 0 +OP4 E00325 0 +OP4 E00326 0 +OP4 E00327 0 +OP4 E00328 0 +OP4 E00329 0 +OP4 E0032A 0 +OP4 E0032B 0 +OP4 E0032C 0 +OP4 E0032D 0 +OP4 E0032E 0 +OP4 E0032F 0 +OP4 E00330 0 +OP4 E00331 0 +OP4 E00332 0 +OP4 E00333 0 +OP4 E00334 0 +OP4 E00335 0 +OP4 E00336 0 +OP4 E00337 0 +OP4 E00338 0 +OP4 E00339 0 +OP4 E0033A 0 +OP4 E0033B 0 +OP4 E0033C 0 +OP4 E0033D 0 +OP4 E0033E 0 +OP4 E0033F 0 +OP4 E00340 0 +OP4 E00341 0 +OP4 E00342 0 +OP4 E00343 0 +OP4 E00344 0 +OP4 E00345 0 +OP4 E00346 0 +OP4 E00347 0 +OP4 E00348 0 +OP4 E00349 0 +OP4 E0034A 0 +OP4 E0034B 0 +OP4 E0034C 0 +OP4 E0034D 0 +OP4 E0034E 0 +OP4 E0034F 0 +OP4 E00350 0 +OP4 E00351 0 +OP4 E00352 0 +OP4 E00353 0 +OP4 E00354 0 +OP4 E00355 0 +OP4 E00356 0 +OP4 E00357 0 +OP4 E00358 0 +OP4 E00359 0 +OP4 E0035A 0 +OP4 E0035B 0 +OP4 E0035C 0 +OP4 E0035D 0 +OP4 E0035E 0 +OP4 E0035F 0 +OP4 E00360 0 +OP4 E00361 0 +OP4 E00362 0 +OP4 E00363 0 +OP4 E00364 0 +OP4 E00365 0 +OP4 E00366 0 +OP4 E00367 0 +OP4 E00368 0 +OP4 E00369 0 +OP4 E0036A 0 +OP4 E0036B 0 +OP4 E0036C 0 +OP4 E0036D 0 +OP4 E0036E 0 +OP4 E0036F 0 +OP4 E00370 0 +OP4 E00371 0 +OP4 E00372 0 +OP4 E00373 0 +OP4 E00374 0 +OP4 E00375 0 +OP4 E00376 0 +OP4 E00377 0 +OP4 E00378 0 +OP4 E00379 0 +OP4 E0037A 0 +OP4 E0037B 0 +OP4 E0037C 0 +OP4 E0037D 0 +OP4 E0037E 0 +OP4 E0037F 0 +OP4 E00380 0 +OP4 E00381 0 +OP4 E00382 0 +OP4 E00383 0 +OP4 E00384 0 +OP4 E00385 0 +OP4 E00386 0 +OP4 E00387 0 +OP4 E00388 0 +OP4 E00389 0 +OP4 E0038A 0 +OP4 E0038B 0 +OP4 E0038C 0 +OP4 E0038D 0 +OP4 E0038E 0 +OP4 E0038F 0 +OP4 E00390 0 +OP4 E00391 0 +OP4 E00392 0 +OP4 E00393 0 +OP4 E00394 0 +OP4 E00395 0 +OP4 E00396 0 +OP4 E00397 0 +OP4 E00398 0 +OP4 E00399 0 +OP4 E0039A 0 +OP4 E0039B 0 +OP4 E0039C 0 +OP4 E0039D 0 +OP4 E0039E 0 +OP4 E0039F 0 +OP4 E003A0 0 +OP4 E003A1 0 +OP4 E003A2 0 +OP4 E003A3 0 +OP4 E003A4 0 +OP4 E003A5 0 +OP4 E003A6 0 +OP4 E003A7 0 +OP4 E003A8 0 +OP4 E003A9 0 +OP4 E003AA 0 +OP4 E003AB 0 +OP4 E003AC 0 +OP4 E003AD 0 +OP4 E003AE 0 +OP4 E003AF 0 +OP4 E003B0 0 +OP4 E003B1 0 +OP4 E003B2 0 +OP4 E003B3 0 +OP4 E003B4 0 +OP4 E003B5 0 +OP4 E003B6 0 +OP4 E003B7 0 +OP4 E003B8 0 +OP4 E003B9 0 +OP4 E003BA 0 +OP4 E003BB 0 +OP4 E003BC 0 +OP4 E003BD 0 +OP4 E003BE 0 +OP4 E003BF 0 +OP4 E003C0 0 +OP4 E003C1 0 +OP4 E003C2 0 +OP4 E003C3 0 +OP4 E003C4 0 +OP4 E003C5 0 +OP4 E003C6 0 +OP4 E003C7 0 +OP4 E003C8 0 +OP4 E003C9 0 +OP4 E003CA 0 +OP4 E003CB 0 +OP4 E003CC 0 +OP4 E003CD 0 +OP4 E003CE 0 +OP4 E003CF 0 +OP4 E003D0 0 +OP4 E003D1 0 +OP4 E003D2 0 +OP4 E003D3 0 +OP4 E003D4 0 +OP4 E003D5 0 +OP4 E003D6 0 +OP4 E003D7 0 +OP4 E003D8 0 +OP4 E003D9 0 +OP4 E003DA 0 +OP4 E003DB 0 +OP4 E003DC 0 +OP4 E003DD 0 +OP4 E003DE 0 +OP4 E003DF 0 +OP4 E003E0 0 +OP4 E003E1 0 +OP4 E003E2 0 +OP4 E003E3 0 +OP4 E003E4 0 +OP4 E003E5 0 +OP4 E003E6 0 +OP4 E003E7 0 +OP4 E003E8 0 +OP4 E003E9 0 +OP4 E003EA 0 +OP4 E003EB 0 +OP4 E003EC 0 +OP4 E003ED 0 +OP4 E003EE 0 +OP4 E003EF 0 +OP4 E003F0 0 +OP4 E003F1 0 +OP4 E003F2 0 +OP4 E003F3 0 +OP4 E003F4 0 +OP4 E003F5 0 +OP4 E003F6 0 +OP4 E003F7 0 +OP4 E003F8 0 +OP4 E003F9 0 +OP4 E003FA 0 +OP4 E003FB 0 +OP4 E003FC 0 +OP4 E003FD 0 +OP4 E003FE 0 +OP4 E003FF 0 +OP4 E00400 0 +OP4 E00401 0 +OP4 E00402 0 +OP4 E00403 0 +OP4 E00404 0 +OP4 E00405 0 +OP4 E00406 0 +OP4 E00407 0 +OP4 E00408 0 +OP4 E00409 0 +OP4 E0040A 0 +OP4 E0040B 0 +OP4 E0040C 0 +OP4 E0040D 0 +OP4 E0040E 0 +OP4 E0040F 0 +OP4 E00410 0 +OP4 E00411 0 +OP4 E00412 0 +OP4 E00413 0 +OP4 E00414 0 +OP4 E00415 0 +OP4 E00416 0 +OP4 E00417 0 +OP4 E00418 0 +OP4 E00419 0 +OP4 E0041A 0 +OP4 E0041B 0 +OP4 E0041C 0 +OP4 E0041D 0 +OP4 E0041E 0 +OP4 E0041F 0 +OP4 E00420 0 +OP4 E00421 0 +OP4 E00422 0 +OP4 E00423 0 +OP4 E00424 0 +OP4 E00425 0 +OP4 E00426 0 +OP4 E00427 0 +OP4 E00428 0 +OP4 E00429 0 +OP4 E0042A 0 +OP4 E0042B 0 +OP4 E0042C 0 +OP4 E0042D 0 +OP4 E0042E 0 +OP4 E0042F 0 +OP4 E00430 0 +OP4 E00431 0 +OP4 E00432 0 +OP4 E00433 0 +OP4 E00434 0 +OP4 E00435 0 +OP4 E00436 0 +OP4 E00437 0 +OP4 E00438 0 +OP4 E00439 0 +OP4 E0043A 0 +OP4 E0043B 0 +OP4 E0043C 0 +OP4 E0043D 0 +OP4 E0043E 0 +OP4 E0043F 0 +OP4 E00440 0 +OP4 E00441 0 +OP4 E00442 0 +OP4 E00443 0 +OP4 E00444 0 +OP4 E00445 0 +OP4 E00446 0 +OP4 E00447 0 +OP4 E00448 0 +OP4 E00449 0 +OP4 E0044A 0 +OP4 E0044B 0 +OP4 E0044C 0 +OP4 E0044D 0 +OP4 E0044E 0 +OP4 E0044F 0 +OP4 E00450 0 +OP4 E00451 0 +OP4 E00452 0 +OP4 E00453 0 +OP4 E00454 0 +OP4 E00455 0 +OP4 E00456 0 +OP4 E00457 0 +OP4 E00458 0 +OP4 E00459 0 +OP4 E0045A 0 +OP4 E0045B 0 +OP4 E0045C 0 +OP4 E0045D 0 +OP4 E0045E 0 +OP4 E0045F 0 +OP4 E00460 0 +OP4 E00461 0 +OP4 E00462 0 +OP4 E00463 0 +OP4 E00464 0 +OP4 E00465 0 +OP4 E00466 0 +OP4 E00467 0 +OP4 E00468 0 +OP4 E00469 0 +OP4 E0046A 0 +OP4 E0046B 0 +OP4 E0046C 0 +OP4 E0046D 0 +OP4 E0046E 0 +OP4 E0046F 0 +OP4 E00470 0 +OP4 E00471 0 +OP4 E00472 0 +OP4 E00473 0 +OP4 E00474 0 +OP4 E00475 0 +OP4 E00476 0 +OP4 E00477 0 +OP4 E00478 0 +OP4 E00479 0 +OP4 E0047A 0 +OP4 E0047B 0 +OP4 E0047C 0 +OP4 E0047D 0 +OP4 E0047E 0 +OP4 E0047F 0 +OP4 E00480 0 +OP4 E00481 0 +OP4 E00482 0 +OP4 E00483 0 +OP4 E00484 0 +OP4 E00485 0 +OP4 E00486 0 +OP4 E00487 0 +OP4 E00488 0 +OP4 E00489 0 +OP4 E0048A 0 +OP4 E0048B 0 +OP4 E0048C 0 +OP4 E0048D 0 +OP4 E0048E 0 +OP4 E0048F 0 +OP4 E00490 0 +OP4 E00491 0 +OP4 E00492 0 +OP4 E00493 0 +OP4 E00494 0 +OP4 E00495 0 +OP4 E00496 0 +OP4 E00497 0 +OP4 E00498 0 +OP4 E00499 0 +OP4 E0049A 0 +OP4 E0049B 0 +OP4 E0049C 0 +OP4 E0049D 0 +OP4 E0049E 0 +OP4 E0049F 0 +OP4 E004A0 0 +OP4 E004A1 0 +OP4 E004A2 0 +OP4 E004A3 0 +OP4 E004A4 0 +OP4 E004A5 0 +OP4 E004A6 0 +OP4 E004A7 0 +OP4 E004A8 0 +OP4 E004A9 0 +OP4 E004AA 0 +OP4 E004AB 0 +OP4 E004AC 0 +OP4 E004AD 0 +OP4 E004AE 0 +OP4 E004AF 0 +OP4 E004B0 0 +OP4 E004B1 0 +OP4 E004B2 0 +OP4 E004B3 0 +OP4 E004B4 0 +OP4 E004B5 0 +OP4 E004B6 0 +OP4 E004B7 0 +OP4 E004B8 0 +OP4 E004B9 0 +OP4 E004BA 0 +OP4 E004BB 0 +OP4 E004BC 0 +OP4 E004BD 0 +OP4 E004BE 0 +OP4 E004BF 0 +OP4 E004C0 0 +OP4 E004C1 0 +OP4 E004C2 0 +OP4 E004C3 0 +OP4 E004C4 0 +OP4 E004C5 0 +OP4 E004C6 0 +OP4 E004C7 0 +OP4 E004C8 0 +OP4 E004C9 0 +OP4 E004CA 0 +OP4 E004CB 0 +OP4 E004CC 0 +OP4 E004CD 0 +OP4 E004CE 0 +OP4 E004CF 0 +OP4 E004D0 0 +OP4 E004D1 0 +OP4 E004D2 0 +OP4 E004D3 0 +OP4 E004D4 0 +OP4 E004D5 0 +OP4 E004D6 0 +OP4 E004D7 0 +OP4 E004D8 0 +OP4 E004D9 0 +OP4 E004DA 0 +OP4 E004DB 0 +OP4 E004DC 0 +OP4 E004DD 0 +OP4 E004DE 0 +OP4 E004DF 0 +OP4 E004E0 0 +OP4 E004E1 0 +OP4 E004E2 0 +OP4 E004E3 0 +OP4 E004E4 0 +OP4 E004E5 0 +OP4 E004E6 0 +OP4 E004E7 0 +OP4 E004E8 0 +OP4 E004E9 0 +OP4 E004EA 0 +OP4 E004EB 0 +OP4 E004EC 0 +OP4 E004ED 0 +OP4 E004EE 0 +OP4 E004EF 0 +OP4 E004F0 0 +OP4 E004F1 0 +OP4 E004F2 0 +OP4 E004F3 0 +OP4 E004F4 0 +OP4 E004F5 0 +OP4 E004F6 0 +OP4 E004F7 0 +OP4 E004F8 0 +OP4 E004F9 0 +OP4 E004FA 0 +OP4 E004FB 0 +OP4 E004FC 0 +OP4 E004FD 0 +OP4 E004FE 0 +OP4 E004FF 0 +OP4 E00500 0 +OP4 E00501 0 +OP4 E00502 0 +OP4 E00503 0 +OP4 E00504 0 +OP4 E00505 0 +OP4 E00506 0 +OP4 E00507 0 +OP4 E00508 0 +OP4 E00509 0 +OP4 E0050A 0 +OP4 E0050B 0 +OP4 E0050C 0 +OP4 E0050D 0 +OP4 E0050E 0 +OP4 E0050F 0 +OP4 E00510 0 +OP4 E00511 0 +OP4 E00512 0 +OP4 E00513 0 +OP4 E00514 0 +OP4 E00515 0 +OP4 E00516 0 +OP4 E00517 0 +OP4 E00518 0 +OP4 E00519 0 +OP4 E0051A 0 +OP4 E0051B 0 +OP4 E0051C 0 +OP4 E0051D 0 +OP4 E0051E 0 +OP4 E0051F 0 +OP4 E00520 0 +OP4 E00521 0 +OP4 E00522 0 +OP4 E00523 0 +OP4 E00524 0 +OP4 E00525 0 +OP4 E00526 0 +OP4 E00527 0 +OP4 E00528 0 +OP4 E00529 0 +OP4 E0052A 0 +OP4 E0052B 0 +OP4 E0052C 0 +OP4 E0052D 0 +OP4 E0052E 0 +OP4 E0052F 0 +OP4 E00530 0 +OP4 E00531 0 +OP4 E00532 0 +OP4 E00533 0 +OP4 E00534 0 +OP4 E00535 0 +OP4 E00536 0 +OP4 E00537 0 +OP4 E00538 0 +OP4 E00539 0 +OP4 E0053A 0 +OP4 E0053B 0 +OP4 E0053C 0 +OP4 E0053D 0 +OP4 E0053E 0 +OP4 E0053F 0 +OP4 E00540 0 +OP4 E00541 0 +OP4 E00542 0 +OP4 E00543 0 +OP4 E00544 0 +OP4 E00545 0 +OP4 E00546 0 +OP4 E00547 0 +OP4 E00548 0 +OP4 E00549 0 +OP4 E0054A 0 +OP4 E0054B 0 +OP4 E0054C 0 +OP4 E0054D 0 +OP4 E0054E 0 +OP4 E0054F 0 +OP4 E00550 0 +OP4 E00551 0 +OP4 E00552 0 +OP4 E00553 0 +OP4 E00554 0 +OP4 E00555 0 +OP4 E00556 0 +OP4 E00557 0 +OP4 E00558 0 +OP4 E00559 0 +OP4 E0055A 0 +OP4 E0055B 0 +OP4 E0055C 0 +OP4 E0055D 0 +OP4 E0055E 0 +OP4 E0055F 0 +OP4 E00560 0 +OP4 E00561 0 +OP4 E00562 0 +OP4 E00563 0 +OP4 E00564 0 +OP4 E00565 0 +OP4 E00566 0 +OP4 E00567 0 +OP4 E00568 0 +OP4 E00569 0 +OP4 E0056A 0 +OP4 E0056B 0 +OP4 E0056C 0 +OP4 E0056D 0 +OP4 E0056E 0 +OP4 E0056F 0 +OP4 E00570 0 +OP4 E00571 0 +OP4 E00572 0 +OP4 E00573 0 +OP4 E00574 0 +OP4 E00575 0 +OP4 E00576 0 +OP4 E00577 0 +OP4 E00578 0 +OP4 E00579 0 +OP4 E0057A 0 +OP4 E0057B 0 +OP4 E0057C 0 +OP4 E0057D 0 +OP4 E0057E 0 +OP4 E0057F 0 +OP4 E00580 0 +OP4 E00581 0 +OP4 E00582 0 +OP4 E00583 0 +OP4 E00584 0 +OP4 E00585 0 +OP4 E00586 0 +OP4 E00587 0 +OP4 E00588 0 +OP4 E00589 0 +OP4 E0058A 0 +OP4 E0058B 0 +OP4 E0058C 0 +OP4 E0058D 0 +OP4 E0058E 0 +OP4 E0058F 0 +OP4 E00590 0 +OP4 E00591 0 +OP4 E00592 0 +OP4 E00593 0 +OP4 E00594 0 +OP4 E00595 0 +OP4 E00596 0 +OP4 E00597 0 +OP4 E00598 0 +OP4 E00599 0 +OP4 E0059A 0 +OP4 E0059B 0 +OP4 E0059C 0 +OP4 E0059D 0 +OP4 E0059E 0 +OP4 E0059F 0 +OP4 E005A0 0 +OP4 E005A1 0 +OP4 E005A2 0 +OP4 E005A3 0 +OP4 E005A4 0 +OP4 E005A5 0 +OP4 E005A6 0 +OP4 E005A7 0 +OP4 E005A8 0 +OP4 E005A9 0 +OP4 E005AA 0 +OP4 E005AB 0 +OP4 E005AC 0 +OP4 E005AD 0 +OP4 E005AE 0 +OP4 E005AF 0 +OP4 E005B0 0 +OP4 E005B1 0 +OP4 E005B2 0 +OP4 E005B3 0 +OP4 E005B4 0 +OP4 E005B5 0 +OP4 E005B6 0 +OP4 E005B7 0 +OP4 E005B8 0 +OP4 E005B9 0 +OP4 E005BA 0 +OP4 E005BB 0 +OP4 E005BC 0 +OP4 E005BD 0 +OP4 E005BE 0 +OP4 E005BF 0 +OP4 E005C0 0 +OP4 E005C1 0 +OP4 E005C2 0 +OP4 E005C3 0 +OP4 E005C4 0 +OP4 E005C5 0 +OP4 E005C6 0 +OP4 E005C7 0 +OP4 E005C8 0 +OP4 E005C9 0 +OP4 E005CA 0 +OP4 E005CB 0 +OP4 E005CC 0 +OP4 E005CD 0 +OP4 E005CE 0 +OP4 E005CF 0 +OP4 E005D0 0 +OP4 E005D1 0 +OP4 E005D2 0 +OP4 E005D3 0 +OP4 E005D4 0 +OP4 E005D5 0 +OP4 E005D6 0 +OP4 E005D7 0 +OP4 E005D8 0 +OP4 E005D9 0 +OP4 E005DA 0 +OP4 E005DB 0 +OP4 E005DC 0 +OP4 E005DD 0 +OP4 E005DE 0 +OP4 E005DF 0 +OP4 E005E0 0 +OP4 E005E1 0 +OP4 E005E2 0 +OP4 E005E3 0 +OP4 E005E4 0 +OP4 E005E5 0 +OP4 E005E6 0 +OP4 E005E7 0 +OP4 E005E8 0 +OP4 E005E9 0 +OP4 E005EA 0 +OP4 E005EB 0 +OP4 E005EC 0 +OP4 E005ED 0 +OP4 E005EE 0 +OP4 E005EF 0 +OP4 E005F0 0 +OP4 E005F1 0 +OP4 E005F2 0 +OP4 E005F3 0 +OP4 E005F4 0 +OP4 E005F5 0 +OP4 E005F6 0 +OP4 E005F7 0 +OP4 E005F8 0 +OP4 E005F9 0 +OP4 E005FA 0 +OP4 E005FB 0 +OP4 E005FC 0 +OP4 E005FD 0 +OP4 E005FE 0 +OP4 E005FF 0 +OP4 E00600 0 +OP4 E00601 0 +OP4 E00602 0 +OP4 E00603 0 +OP4 E00604 0 +OP4 E00605 0 +OP4 E00606 0 +OP4 E00607 0 +OP4 E00608 0 +OP4 E00609 0 +OP4 E0060A 0 +OP4 E0060B 0 +OP4 E0060C 0 +OP4 E0060D 0 +OP4 E0060E 0 +OP4 E0060F 0 +OP4 E00610 0 +OP4 E00611 0 +OP4 E00612 0 +OP4 E00613 0 +OP4 E00614 0 +OP4 E00615 0 +OP4 E00616 0 +OP4 E00617 0 +OP4 E00618 0 +OP4 E00619 0 +OP4 E0061A 0 +OP4 E0061B 0 +OP4 E0061C 0 +OP4 E0061D 0 +OP4 E0061E 0 +OP4 E0061F 0 +OP4 E00620 0 +OP4 E00621 0 +OP4 E00622 0 +OP4 E00623 0 +OP4 E00624 0 +OP4 E00625 0 +OP4 E00626 0 +OP4 E00627 0 +OP4 E00628 0 +OP4 E00629 0 +OP4 E0062A 0 +OP4 E0062B 0 +OP4 E0062C 0 +OP4 E0062D 0 +OP4 E0062E 0 +OP4 E0062F 0 +OP4 E00630 0 +OP4 E00631 0 +OP4 E00632 0 +OP4 E00633 0 +OP4 E00634 0 +OP4 E00635 0 +OP4 E00636 0 +OP4 E00637 0 +OP4 E00638 0 +OP4 E00639 0 +OP4 E0063A 0 +OP4 E0063B 0 +OP4 E0063C 0 +OP4 E0063D 0 +OP4 E0063E 0 +OP4 E0063F 0 +OP4 E00640 0 +OP4 E00641 0 +OP4 E00642 0 +OP4 E00643 0 +OP4 E00644 0 +OP4 E00645 0 +OP4 E00646 0 +OP4 E00647 0 +OP4 E00648 0 +OP4 E00649 0 +OP4 E0064A 0 +OP4 E0064B 0 +OP4 E0064C 0 +OP4 E0064D 0 +OP4 E0064E 0 +OP4 E0064F 0 +OP4 E00650 0 +OP4 E00651 0 +OP4 E00652 0 +OP4 E00653 0 +OP4 E00654 0 +OP4 E00655 0 +OP4 E00656 0 +OP4 E00657 0 +OP4 E00658 0 +OP4 E00659 0 +OP4 E0065A 0 +OP4 E0065B 0 +OP4 E0065C 0 +OP4 E0065D 0 +OP4 E0065E 0 +OP4 E0065F 0 +OP4 E00660 0 +OP4 E00661 0 +OP4 E00662 0 +OP4 E00663 0 +OP4 E00664 0 +OP4 E00665 0 +OP4 E00666 0 +OP4 E00667 0 +OP4 E00668 0 +OP4 E00669 0 +OP4 E0066A 0 +OP4 E0066B 0 +OP4 E0066C 0 +OP4 E0066D 0 +OP4 E0066E 0 +OP4 E0066F 0 +OP4 E00670 0 +OP4 E00671 0 +OP4 E00672 0 +OP4 E00673 0 +OP4 E00674 0 +OP4 E00675 0 +OP4 E00676 0 +OP4 E00677 0 +OP4 E00678 0 +OP4 E00679 0 +OP4 E0067A 0 +OP4 E0067B 0 +OP4 E0067C 0 +OP4 E0067D 0 +OP4 E0067E 0 +OP4 E0067F 0 +OP4 E00680 0 +OP4 E00681 0 +OP4 E00682 0 +OP4 E00683 0 +OP4 E00684 0 +OP4 E00685 0 +OP4 E00686 0 +OP4 E00687 0 +OP4 E00688 0 +OP4 E00689 0 +OP4 E0068A 0 +OP4 E0068B 0 +OP4 E0068C 0 +OP4 E0068D 0 +OP4 E0068E 0 +OP4 E0068F 0 +OP4 E00690 0 +OP4 E00691 0 +OP4 E00692 0 +OP4 E00693 0 +OP4 E00694 0 +OP4 E00695 0 +OP4 E00696 0 +OP4 E00697 0 +OP4 E00698 0 +OP4 E00699 0 +OP4 E0069A 0 +OP4 E0069B 0 +OP4 E0069C 0 +OP4 E0069D 0 +OP4 E0069E 0 +OP4 E0069F 0 +OP4 E006A0 0 +OP4 E006A1 0 +OP4 E006A2 0 +OP4 E006A3 0 +OP4 E006A4 0 +OP4 E006A5 0 +OP4 E006A6 0 +OP4 E006A7 0 +OP4 E006A8 0 +OP4 E006A9 0 +OP4 E006AA 0 +OP4 E006AB 0 +OP4 E006AC 0 +OP4 E006AD 0 +OP4 E006AE 0 +OP4 E006AF 0 +OP4 E006B0 0 +OP4 E006B1 0 +OP4 E006B2 0 +OP4 E006B3 0 +OP4 E006B4 0 +OP4 E006B5 0 +OP4 E006B6 0 +OP4 E006B7 0 +OP4 E006B8 0 +OP4 E006B9 0 +OP4 E006BA 0 +OP4 E006BB 0 +OP4 E006BC 0 +OP4 E006BD 0 +OP4 E006BE 0 +OP4 E006BF 0 +OP4 E006C0 0 +OP4 E006C1 0 +OP4 E006C2 0 +OP4 E006C3 0 +OP4 E006C4 0 +OP4 E006C5 0 +OP4 E006C6 0 +OP4 E006C7 0 +OP4 E006C8 0 +OP4 E006C9 0 +OP4 E006CA 0 +OP4 E006CB 0 +OP4 E006CC 0 +OP4 E006CD 0 +OP4 E006CE 0 +OP4 E006CF 0 +OP4 E006D0 0 +OP4 E006D1 0 +OP4 E006D2 0 +OP4 E006D3 0 +OP4 E006D4 0 +OP4 E006D5 0 +OP4 E006D6 0 +OP4 E006D7 0 +OP4 E006D8 0 +OP4 E006D9 0 +OP4 E006DA 0 +OP4 E006DB 0 +OP4 E006DC 0 +OP4 E006DD 0 +OP4 E006DE 0 +OP4 E006DF 0 +OP4 E006E0 0 +OP4 E006E1 0 +OP4 E006E2 0 +OP4 E006E3 0 +OP4 E006E4 0 +OP4 E006E5 0 +OP4 E006E6 0 +OP4 E006E7 0 +OP4 E006E8 0 +OP4 E006E9 0 +OP4 E006EA 0 +OP4 E006EB 0 +OP4 E006EC 0 +OP4 E006ED 0 +OP4 E006EE 0 +OP4 E006EF 0 +OP4 E006F0 0 +OP4 E006F1 0 +OP4 E006F2 0 +OP4 E006F3 0 +OP4 E006F4 0 +OP4 E006F5 0 +OP4 E006F6 0 +OP4 E006F7 0 +OP4 E006F8 0 +OP4 E006F9 0 +OP4 E006FA 0 +OP4 E006FB 0 +OP4 E006FC 0 +OP4 E006FD 0 +OP4 E006FE 0 +OP4 E006FF 0 +OP4 E00700 0 +OP4 E00701 0 +OP4 E00702 0 +OP4 E00703 0 +OP4 E00704 0 +OP4 E00705 0 +OP4 E00706 0 +OP4 E00707 0 +OP4 E00708 0 +OP4 E00709 0 +OP4 E0070A 0 +OP4 E0070B 0 +OP4 E0070C 0 +OP4 E0070D 0 +OP4 E0070E 0 +OP4 E0070F 0 +OP4 E00710 0 +OP4 E00711 0 +OP4 E00712 0 +OP4 E00713 0 +OP4 E00714 0 +OP4 E00715 0 +OP4 E00716 0 +OP4 E00717 0 +OP4 E00718 0 +OP4 E00719 0 +OP4 E0071A 0 +OP4 E0071B 0 +OP4 E0071C 0 +OP4 E0071D 0 +OP4 E0071E 0 +OP4 E0071F 0 +OP4 E00720 0 +OP4 E00721 0 +OP4 E00722 0 +OP4 E00723 0 +OP4 E00724 0 +OP4 E00725 0 +OP4 E00726 0 +OP4 E00727 0 +OP4 E00728 0 +OP4 E00729 0 +OP4 E0072A 0 +OP4 E0072B 0 +OP4 E0072C 0 +OP4 E0072D 0 +OP4 E0072E 0 +OP4 E0072F 0 +OP4 E00730 0 +OP4 E00731 0 +OP4 E00732 0 +OP4 E00733 0 +OP4 E00734 0 +OP4 E00735 0 +OP4 E00736 0 +OP4 E00737 0 +OP4 E00738 0 +OP4 E00739 0 +OP4 E0073A 0 +OP4 E0073B 0 +OP4 E0073C 0 +OP4 E0073D 0 +OP4 E0073E 0 +OP4 E0073F 0 +OP4 E00740 0 +OP4 E00741 0 +OP4 E00742 0 +OP4 E00743 0 +OP4 E00744 0 +OP4 E00745 0 +OP4 E00746 0 +OP4 E00747 0 +OP4 E00748 0 +OP4 E00749 0 +OP4 E0074A 0 +OP4 E0074B 0 +OP4 E0074C 0 +OP4 E0074D 0 +OP4 E0074E 0 +OP4 E0074F 0 +OP4 E00750 0 +OP4 E00751 0 +OP4 E00752 0 +OP4 E00753 0 +OP4 E00754 0 +OP4 E00755 0 +OP4 E00756 0 +OP4 E00757 0 +OP4 E00758 0 +OP4 E00759 0 +OP4 E0075A 0 +OP4 E0075B 0 +OP4 E0075C 0 +OP4 E0075D 0 +OP4 E0075E 0 +OP4 E0075F 0 +OP4 E00760 0 +OP4 E00761 0 +OP4 E00762 0 +OP4 E00763 0 +OP4 E00764 0 +OP4 E00765 0 +OP4 E00766 0 +OP4 E00767 0 +OP4 E00768 0 +OP4 E00769 0 +OP4 E0076A 0 +OP4 E0076B 0 +OP4 E0076C 0 +OP4 E0076D 0 +OP4 E0076E 0 +OP4 E0076F 0 +OP4 E00770 0 +OP4 E00771 0 +OP4 E00772 0 +OP4 E00773 0 +OP4 E00774 0 +OP4 E00775 0 +OP4 E00776 0 +OP4 E00777 0 +OP4 E00778 0 +OP4 E00779 0 +OP4 E0077A 0 +OP4 E0077B 0 +OP4 E0077C 0 +OP4 E0077D 0 +OP4 E0077E 0 +OP4 E0077F 0 +OP4 E00780 0 +OP4 E00781 0 +OP4 E00782 0 +OP4 E00783 0 +OP4 E00784 0 +OP4 E00785 0 +OP4 E00786 0 +OP4 E00787 0 +OP4 E00788 0 +OP4 E00789 0 +OP4 E0078A 0 +OP4 E0078B 0 +OP4 E0078C 0 +OP4 E0078D 0 +OP4 E0078E 0 +OP4 E0078F 0 +OP4 E00790 0 +OP4 E00791 0 +OP4 E00792 0 +OP4 E00793 0 +OP4 E00794 0 +OP4 E00795 0 +OP4 E00796 0 +OP4 E00797 0 +OP4 E00798 0 +OP4 E00799 0 +OP4 E0079A 0 +OP4 E0079B 0 +OP4 E0079C 0 +OP4 E0079D 0 +OP4 E0079E 0 +OP4 E0079F 0 +OP4 E007A0 0 +OP4 E007A1 0 +OP4 E007A2 0 +OP4 E007A3 0 +OP4 E007A4 0 +OP4 E007A5 0 +OP4 E007A6 0 +OP4 E007A7 0 +OP4 E007A8 0 +OP4 E007A9 0 +OP4 E007AA 0 +OP4 E007AB 0 +OP4 E007AC 0 +OP4 E007AD 0 +OP4 E007AE 0 +OP4 E007AF 0 +OP4 E007B0 0 +OP4 E007B1 0 +OP4 E007B2 0 +OP4 E007B3 0 +OP4 E007B4 0 +OP4 E007B5 0 +OP4 E007B6 0 +OP4 E007B7 0 +OP4 E007B8 0 +OP4 E007B9 0 +OP4 E007BA 0 +OP4 E007BB 0 +OP4 E007BC 0 +OP4 E007BD 0 +OP4 E007BE 0 +OP4 E007BF 0 +OP4 E007C0 0 +OP4 E007C1 0 +OP4 E007C2 0 +OP4 E007C3 0 +OP4 E007C4 0 +OP4 E007C5 0 +OP4 E007C6 0 +OP4 E007C7 0 +OP4 E007C8 0 +OP4 E007C9 0 +OP4 E007CA 0 +OP4 E007CB 0 +OP4 E007CC 0 +OP4 E007CD 0 +OP4 E007CE 0 +OP4 E007CF 0 +OP4 E007D0 0 +OP4 E007D1 0 +OP4 E007D2 0 +OP4 E007D3 0 +OP4 E007D4 0 +OP4 E007D5 0 +OP4 E007D6 0 +OP4 E007D7 0 +OP4 E007D8 0 +OP4 E007D9 0 +OP4 E007DA 0 +OP4 E007DB 0 +OP4 E007DC 0 +OP4 E007DD 0 +OP4 E007DE 0 +OP4 E007DF 0 +OP4 E007E0 0 +OP4 E007E1 0 +OP4 E007E2 0 +OP4 E007E3 0 +OP4 E007E4 0 +OP4 E007E5 0 +OP4 E007E6 0 +OP4 E007E7 0 +OP4 E007E8 0 +OP4 E007E9 0 +OP4 E007EA 0 +OP4 E007EB 0 +OP4 E007EC 0 +OP4 E007ED 0 +OP4 E007EE 0 +OP4 E007EF 0 +OP4 E007F0 0 +OP4 E007F1 0 +OP4 E007F2 0 +OP4 E007F3 0 +OP4 E007F4 0 +OP4 E007F5 0 +OP4 E007F6 0 +OP4 E007F7 0 +OP4 E007F8 0 +OP4 E007F9 0 +OP4 E007FA 0 +OP4 E007FB 0 +OP4 E007FC 0 +OP4 E007FD 0 +OP4 E007FE 0 +OP4 E007FF 0 +OP4 E00800 0 +OP4 E00801 0 +OP4 E00802 0 +OP4 E00803 0 +OP4 E00804 0 +OP4 E00805 0 +OP4 E00806 0 +OP4 E00807 0 +OP4 E00808 0 +OP4 E00809 0 +OP4 E0080A 0 +OP4 E0080B 0 +OP4 E0080C 0 +OP4 E0080D 0 +OP4 E0080E 0 +OP4 E0080F 0 +OP4 E00810 0 +OP4 E00811 0 +OP4 E00812 0 +OP4 E00813 0 +OP4 E00814 0 +OP4 E00815 0 +OP4 E00816 0 +OP4 E00817 0 +OP4 E00818 0 +OP4 E00819 0 +OP4 E0081A 0 +OP4 E0081B 0 +OP4 E0081C 0 +OP4 E0081D 0 +OP4 E0081E 0 +OP4 E0081F 0 +OP4 E00820 0 +OP4 E00821 0 +OP4 E00822 0 +OP4 E00823 0 +OP4 E00824 0 +OP4 E00825 0 +OP4 E00826 0 +OP4 E00827 0 +OP4 E00828 0 +OP4 E00829 0 +OP4 E0082A 0 +OP4 E0082B 0 +OP4 E0082C 0 +OP4 E0082D 0 +OP4 E0082E 0 +OP4 E0082F 0 +OP4 E00830 0 +OP4 E00831 0 +OP4 E00832 0 +OP4 E00833 0 +OP4 E00834 0 +OP4 E00835 0 +OP4 E00836 0 +OP4 E00837 0 +OP4 E00838 0 +OP4 E00839 0 +OP4 E0083A 0 +OP4 E0083B 0 +OP4 E0083C 0 +OP4 E0083D 0 +OP4 E0083E 0 +OP4 E0083F 0 +OP4 E00840 0 +OP4 E00841 0 +OP4 E00842 0 +OP4 E00843 0 +OP4 E00844 0 +OP4 E00845 0 +OP4 E00846 0 +OP4 E00847 0 +OP4 E00848 0 +OP4 E00849 0 +OP4 E0084A 0 +OP4 E0084B 0 +OP4 E0084C 0 +OP4 E0084D 0 +OP4 E0084E 0 +OP4 E0084F 0 +OP4 E00850 0 +OP4 E00851 0 +OP4 E00852 0 +OP4 E00853 0 +OP4 E00854 0 +OP4 E00855 0 +OP4 E00856 0 +OP4 E00857 0 +OP4 E00858 0 +OP4 E00859 0 +OP4 E0085A 0 +OP4 E0085B 0 +OP4 E0085C 0 +OP4 E0085D 0 +OP4 E0085E 0 +OP4 E0085F 0 +OP4 E00860 0 +OP4 E00861 0 +OP4 E00862 0 +OP4 E00863 0 +OP4 E00864 0 +OP4 E00865 0 +OP4 E00866 0 +OP4 E00867 0 +OP4 E00868 0 +OP4 E00869 0 +OP4 E0086A 0 +OP4 E0086B 0 +OP4 E0086C 0 +OP4 E0086D 0 +OP4 E0086E 0 +OP4 E0086F 0 +OP4 E00870 0 +OP4 E00871 0 +OP4 E00872 0 +OP4 E00873 0 +OP4 E00874 0 +OP4 E00875 0 +OP4 E00876 0 +OP4 E00877 0 +OP4 E00878 0 +OP4 E00879 0 +OP4 E0087A 0 +OP4 E0087B 0 +OP4 E0087C 0 +OP4 E0087D 0 +OP4 E0087E 0 +OP4 E0087F 0 +OP4 E00880 0 +OP4 E00881 0 +OP4 E00882 0 +OP4 E00883 0 +OP4 E00884 0 +OP4 E00885 0 +OP4 E00886 0 +OP4 E00887 0 +OP4 E00888 0 +OP4 E00889 0 +OP4 E0088A 0 +OP4 E0088B 0 +OP4 E0088C 0 +OP4 E0088D 0 +OP4 E0088E 0 +OP4 E0088F 0 +OP4 E00890 0 +OP4 E00891 0 +OP4 E00892 0 +OP4 E00893 0 +OP4 E00894 0 +OP4 E00895 0 +OP4 E00896 0 +OP4 E00897 0 +OP4 E00898 0 +OP4 E00899 0 +OP4 E0089A 0 +OP4 E0089B 0 +OP4 E0089C 0 +OP4 E0089D 0 +OP4 E0089E 0 +OP4 E0089F 0 +OP4 E008A0 0 +OP4 E008A1 0 +OP4 E008A2 0 +OP4 E008A3 0 +OP4 E008A4 0 +OP4 E008A5 0 +OP4 E008A6 0 +OP4 E008A7 0 +OP4 E008A8 0 +OP4 E008A9 0 +OP4 E008AA 0 +OP4 E008AB 0 +OP4 E008AC 0 +OP4 E008AD 0 +OP4 E008AE 0 +OP4 E008AF 0 +OP4 E008B0 0 +OP4 E008B1 0 +OP4 E008B2 0 +OP4 E008B3 0 +OP4 E008B4 0 +OP4 E008B5 0 +OP4 E008B6 0 +OP4 E008B7 0 +OP4 E008B8 0 +OP4 E008B9 0 +OP4 E008BA 0 +OP4 E008BB 0 +OP4 E008BC 0 +OP4 E008BD 0 +OP4 E008BE 0 +OP4 E008BF 0 +OP4 E008C0 0 +OP4 E008C1 0 +OP4 E008C2 0 +OP4 E008C3 0 +OP4 E008C4 0 +OP4 E008C5 0 +OP4 E008C6 0 +OP4 E008C7 0 +OP4 E008C8 0 +OP4 E008C9 0 +OP4 E008CA 0 +OP4 E008CB 0 +OP4 E008CC 0 +OP4 E008CD 0 +OP4 E008CE 0 +OP4 E008CF 0 +OP4 E008D0 0 +OP4 E008D1 0 +OP4 E008D2 0 +OP4 E008D3 0 +OP4 E008D4 0 +OP4 E008D5 0 +OP4 E008D6 0 +OP4 E008D7 0 +OP4 E008D8 0 +OP4 E008D9 0 +OP4 E008DA 0 +OP4 E008DB 0 +OP4 E008DC 0 +OP4 E008DD 0 +OP4 E008DE 0 +OP4 E008DF 0 +OP4 E008E0 0 +OP4 E008E1 0 +OP4 E008E2 0 +OP4 E008E3 0 +OP4 E008E4 0 +OP4 E008E5 0 +OP4 E008E6 0 +OP4 E008E7 0 +OP4 E008E8 0 +OP4 E008E9 0 +OP4 E008EA 0 +OP4 E008EB 0 +OP4 E008EC 0 +OP4 E008ED 0 +OP4 E008EE 0 +OP4 E008EF 0 +OP4 E008F0 0 +OP4 E008F1 0 +OP4 E008F2 0 +OP4 E008F3 0 +OP4 E008F4 0 +OP4 E008F5 0 +OP4 E008F6 0 +OP4 E008F7 0 +OP4 E008F8 0 +OP4 E008F9 0 +OP4 E008FA 0 +OP4 E008FB 0 +OP4 E008FC 0 +OP4 E008FD 0 +OP4 E008FE 0 +OP4 E008FF 0 +OP4 E00900 0 +OP4 E00901 0 +OP4 E00902 0 +OP4 E00903 0 +OP4 E00904 0 +OP4 E00905 0 +OP4 E00906 0 +OP4 E00907 0 +OP4 E00908 0 +OP4 E00909 0 +OP4 E0090A 0 +OP4 E0090B 0 +OP4 E0090C 0 +OP4 E0090D 0 +OP4 E0090E 0 +OP4 E0090F 0 +OP4 E00910 0 +OP4 E00911 0 +OP4 E00912 0 +OP4 E00913 0 +OP4 E00914 0 +OP4 E00915 0 +OP4 E00916 0 +OP4 E00917 0 +OP4 E00918 0 +OP4 E00919 0 +OP4 E0091A 0 +OP4 E0091B 0 +OP4 E0091C 0 +OP4 E0091D 0 +OP4 E0091E 0 +OP4 E0091F 0 +OP4 E00920 0 +OP4 E00921 0 +OP4 E00922 0 +OP4 E00923 0 +OP4 E00924 0 +OP4 E00925 0 +OP4 E00926 0 +OP4 E00927 0 +OP4 E00928 0 +OP4 E00929 0 +OP4 E0092A 0 +OP4 E0092B 0 +OP4 E0092C 0 +OP4 E0092D 0 +OP4 E0092E 0 +OP4 E0092F 0 +OP4 E00930 0 +OP4 E00931 0 +OP4 E00932 0 +OP4 E00933 0 +OP4 E00934 0 +OP4 E00935 0 +OP4 E00936 0 +OP4 E00937 0 +OP4 E00938 0 +OP4 E00939 0 +OP4 E0093A 0 +OP4 E0093B 0 +OP4 E0093C 0 +OP4 E0093D 0 +OP4 E0093E 0 +OP4 E0093F 0 +OP4 E00940 0 +OP4 E00941 0 +OP4 E00942 0 +OP4 E00943 0 +OP4 E00944 0 +OP4 E00945 0 +OP4 E00946 0 +OP4 E00947 0 +OP4 E00948 0 +OP4 E00949 0 +OP4 E0094A 0 +OP4 E0094B 0 +OP4 E0094C 0 +OP4 E0094D 0 +OP4 E0094E 0 +OP4 E0094F 0 +OP4 E00950 0 +OP4 E00951 0 +OP4 E00952 0 +OP4 E00953 0 +OP4 E00954 0 +OP4 E00955 0 +OP4 E00956 0 +OP4 E00957 0 +OP4 E00958 0 +OP4 E00959 0 +OP4 E0095A 0 +OP4 E0095B 0 +OP4 E0095C 0 +OP4 E0095D 0 +OP4 E0095E 0 +OP4 E0095F 0 +OP4 E00960 0 +OP4 E00961 0 +OP4 E00962 0 +OP4 E00963 0 +OP4 E00964 0 +OP4 E00965 0 +OP4 E00966 0 +OP4 E00967 0 +OP4 E00968 0 +OP4 E00969 0 +OP4 E0096A 0 +OP4 E0096B 0 +OP4 E0096C 0 +OP4 E0096D 0 +OP4 E0096E 0 +OP4 E0096F 0 +OP4 E00970 0 +OP4 E00971 0 +OP4 E00972 0 +OP4 E00973 0 +OP4 E00974 0 +OP4 E00975 0 +OP4 E00976 0 +OP4 E00977 0 +OP4 E00978 0 +OP4 E00979 0 +OP4 E0097A 0 +OP4 E0097B 0 +OP4 E0097C 0 +OP4 E0097D 0 +OP4 E0097E 0 +OP4 E0097F 0 +OP4 E00980 0 +OP4 E00981 0 +OP4 E00982 0 +OP4 E00983 0 +OP4 E00984 0 +OP4 E00985 0 +OP4 E00986 0 +OP4 E00987 0 +OP4 E00988 0 +OP4 E00989 0 +OP4 E0098A 0 +OP4 E0098B 0 +OP4 E0098C 0 +OP4 E0098D 0 +OP4 E0098E 0 +OP4 E0098F 0 +OP4 E00990 0 +OP4 E00991 0 +OP4 E00992 0 +OP4 E00993 0 +OP4 E00994 0 +OP4 E00995 0 +OP4 E00996 0 +OP4 E00997 0 +OP4 E00998 0 +OP4 E00999 0 +OP4 E0099A 0 +OP4 E0099B 0 +OP4 E0099C 0 +OP4 E0099D 0 +OP4 E0099E 0 +OP4 E0099F 0 +OP4 E009A0 0 +OP4 E009A1 0 +OP4 E009A2 0 +OP4 E009A3 0 +OP4 E009A4 0 +OP4 E009A5 0 +OP4 E009A6 0 +OP4 E009A7 0 +OP4 E009A8 0 +OP4 E009A9 0 +OP4 E009AA 0 +OP4 E009AB 0 +OP4 E009AC 0 +OP4 E009AD 0 +OP4 E009AE 0 +OP4 E009AF 0 +OP4 E009B0 0 +OP4 E009B1 0 +OP4 E009B2 0 +OP4 E009B3 0 +OP4 E009B4 0 +OP4 E009B5 0 +OP4 E009B6 0 +OP4 E009B7 0 +OP4 E009B8 0 +OP4 E009B9 0 +OP4 E009BA 0 +OP4 E009BB 0 +OP4 E009BC 0 +OP4 E009BD 0 +OP4 E009BE 0 +OP4 E009BF 0 +OP4 E009C0 0 +OP4 E009C1 0 +OP4 E009C2 0 +OP4 E009C3 0 +OP4 E009C4 0 +OP4 E009C5 0 +OP4 E009C6 0 +OP4 E009C7 0 +OP4 E009C8 0 +OP4 E009C9 0 +OP4 E009CA 0 +OP4 E009CB 0 +OP4 E009CC 0 +OP4 E009CD 0 +OP4 E009CE 0 +OP4 E009CF 0 +OP4 E009D0 0 +OP4 E009D1 0 +OP4 E009D2 0 +OP4 E009D3 0 +OP4 E009D4 0 +OP4 E009D5 0 +OP4 E009D6 0 +OP4 E009D7 0 +OP4 E009D8 0 +OP4 E009D9 0 +OP4 E009DA 0 +OP4 E009DB 0 +OP4 E009DC 0 +OP4 E009DD 0 +OP4 E009DE 0 +OP4 E009DF 0 +OP4 E009E0 0 +OP4 E009E1 0 +OP4 E009E2 0 +OP4 E009E3 0 +OP4 E009E4 0 +OP4 E009E5 0 +OP4 E009E6 0 +OP4 E009E7 0 +OP4 E009E8 0 +OP4 E009E9 0 +OP4 E009EA 0 +OP4 E009EB 0 +OP4 E009EC 0 +OP4 E009ED 0 +OP4 E009EE 0 +OP4 E009EF 0 +OP4 E009F0 0 +OP4 E009F1 0 +OP4 E009F2 0 +OP4 E009F3 0 +OP4 E009F4 0 +OP4 E009F5 0 +OP4 E009F6 0 +OP4 E009F7 0 +OP4 E009F8 0 +OP4 E009F9 0 +OP4 E009FA 0 +OP4 E009FB 0 +OP4 E009FC 0 +OP4 E009FD 0 +OP4 E009FE 0 +OP4 E009FF 0 +OP4 E00A00 0 +OP4 E00A01 0 +OP4 E00A02 0 +OP4 E00A03 0 +OP4 E00A04 0 +OP4 E00A05 0 +OP4 E00A06 0 +OP4 E00A07 0 +OP4 E00A08 0 +OP4 E00A09 0 +OP4 E00A0A 0 +OP4 E00A0B 0 +OP4 E00A0C 0 +OP4 E00A0D 0 +OP4 E00A0E 0 +OP4 E00A0F 0 +OP4 E00A10 0 +OP4 E00A11 0 +OP4 E00A12 0 +OP4 E00A13 0 +OP4 E00A14 0 +OP4 E00A15 0 +OP4 E00A16 0 +OP4 E00A17 0 +OP4 E00A18 0 +OP4 E00A19 0 +OP4 E00A1A 0 +OP4 E00A1B 0 +OP4 E00A1C 0 +OP4 E00A1D 0 +OP4 E00A1E 0 +OP4 E00A1F 0 +OP4 E00A20 0 +OP4 E00A21 0 +OP4 E00A22 0 +OP4 E00A23 0 +OP4 E00A24 0 +OP4 E00A25 0 +OP4 E00A26 0 +OP4 E00A27 0 +OP4 E00A28 0 +OP4 E00A29 0 +OP4 E00A2A 0 +OP4 E00A2B 0 +OP4 E00A2C 0 +OP4 E00A2D 0 +OP4 E00A2E 0 +OP4 E00A2F 0 +OP4 E00A30 0 +OP4 E00A31 0 +OP4 E00A32 0 +OP4 E00A33 0 +OP4 E00A34 0 +OP4 E00A35 0 +OP4 E00A36 0 +OP4 E00A37 0 +OP4 E00A38 0 +OP4 E00A39 0 +OP4 E00A3A 0 +OP4 E00A3B 0 +OP4 E00A3C 0 +OP4 E00A3D 0 +OP4 E00A3E 0 +OP4 E00A3F 0 +OP4 E00A40 0 +OP4 E00A41 0 +OP4 E00A42 0 +OP4 E00A43 0 +OP4 E00A44 0 +OP4 E00A45 0 +OP4 E00A46 0 +OP4 E00A47 0 +OP4 E00A48 0 +OP4 E00A49 0 +OP4 E00A4A 0 +OP4 E00A4B 0 +OP4 E00A4C 0 +OP4 E00A4D 0 +OP4 E00A4E 0 +OP4 E00A4F 0 +OP4 E00A50 0 +OP4 E00A51 0 +OP4 E00A52 0 +OP4 E00A53 0 +OP4 E00A54 0 +OP4 E00A55 0 +OP4 E00A56 0 +OP4 E00A57 0 +OP4 E00A58 0 +OP4 E00A59 0 +OP4 E00A5A 0 +OP4 E00A5B 0 +OP4 E00A5C 0 +OP4 E00A5D 0 +OP4 E00A5E 0 +OP4 E00A5F 0 +OP4 E00A60 0 +OP4 E00A61 0 +OP4 E00A62 0 +OP4 E00A63 0 +OP4 E00A64 0 +OP4 E00A65 0 +OP4 E00A66 0 +OP4 E00A67 0 +OP4 E00A68 0 +OP4 E00A69 0 +OP4 E00A6A 0 +OP4 E00A6B 0 +OP4 E00A6C 0 +OP4 E00A6D 0 +OP4 E00A6E 0 +OP4 E00A6F 0 +OP4 E00A70 0 +OP4 E00A71 0 +OP4 E00A72 0 +OP4 E00A73 0 +OP4 E00A74 0 +OP4 E00A75 0 +OP4 E00A76 0 +OP4 E00A77 0 +OP4 E00A78 0 +OP4 E00A79 0 +OP4 E00A7A 0 +OP4 E00A7B 0 +OP4 E00A7C 0 +OP4 E00A7D 0 +OP4 E00A7E 0 +OP4 E00A7F 0 +OP4 E00A80 0 +OP4 E00A81 0 +OP4 E00A82 0 +OP4 E00A83 0 +OP4 E00A84 0 +OP4 E00A85 0 +OP4 E00A86 0 +OP4 E00A87 0 +OP4 E00A88 0 +OP4 E00A89 0 +OP4 E00A8A 0 +OP4 E00A8B 0 +OP4 E00A8C 0 +OP4 E00A8D 0 +OP4 E00A8E 0 +OP4 E00A8F 0 +OP4 E00A90 0 +OP4 E00A91 0 +OP4 E00A92 0 +OP4 E00A93 0 +OP4 E00A94 0 +OP4 E00A95 0 +OP4 E00A96 0 +OP4 E00A97 0 +OP4 E00A98 0 +OP4 E00A99 0 +OP4 E00A9A 0 +OP4 E00A9B 0 +OP4 E00A9C 0 +OP4 E00A9D 0 +OP4 E00A9E 0 +OP4 E00A9F 0 +OP4 E00AA0 0 +OP4 E00AA1 0 +OP4 E00AA2 0 +OP4 E00AA3 0 +OP4 E00AA4 0 +OP4 E00AA5 0 +OP4 E00AA6 0 +OP4 E00AA7 0 +OP4 E00AA8 0 +OP4 E00AA9 0 +OP4 E00AAA 0 +OP4 E00AAB 0 +OP4 E00AAC 0 +OP4 E00AAD 0 +OP4 E00AAE 0 +OP4 E00AAF 0 +OP4 E00AB0 0 +OP4 E00AB1 0 +OP4 E00AB2 0 +OP4 E00AB3 0 +OP4 E00AB4 0 +OP4 E00AB5 0 +OP4 E00AB6 0 +OP4 E00AB7 0 +OP4 E00AB8 0 +OP4 E00AB9 0 +OP4 E00ABA 0 +OP4 E00ABB 0 +OP4 E00ABC 0 +OP4 E00ABD 0 +OP4 E00ABE 0 +OP4 E00ABF 0 +OP4 E00AC0 0 +OP4 E00AC1 0 +OP4 E00AC2 0 +OP4 E00AC3 0 +OP4 E00AC4 0 +OP4 E00AC5 0 +OP4 E00AC6 0 +OP4 E00AC7 0 +OP4 E00AC8 0 +OP4 E00AC9 0 +OP4 E00ACA 0 +OP4 E00ACB 0 +OP4 E00ACC 0 +OP4 E00ACD 0 +OP4 E00ACE 0 +OP4 E00ACF 0 +OP4 E00AD0 0 +OP4 E00AD1 0 +OP4 E00AD2 0 +OP4 E00AD3 0 +OP4 E00AD4 0 +OP4 E00AD5 0 +OP4 E00AD6 0 +OP4 E00AD7 0 +OP4 E00AD8 0 +OP4 E00AD9 0 +OP4 E00ADA 0 +OP4 E00ADB 0 +OP4 E00ADC 0 +OP4 E00ADD 0 +OP4 E00ADE 0 +OP4 E00ADF 0 +OP4 E00AE0 0 +OP4 E00AE1 0 +OP4 E00AE2 0 +OP4 E00AE3 0 +OP4 E00AE4 0 +OP4 E00AE5 0 +OP4 E00AE6 0 +OP4 E00AE7 0 +OP4 E00AE8 0 +OP4 E00AE9 0 +OP4 E00AEA 0 +OP4 E00AEB 0 +OP4 E00AEC 0 +OP4 E00AED 0 +OP4 E00AEE 0 +OP4 E00AEF 0 +OP4 E00AF0 0 +OP4 E00AF1 0 +OP4 E00AF2 0 +OP4 E00AF3 0 +OP4 E00AF4 0 +OP4 E00AF5 0 +OP4 E00AF6 0 +OP4 E00AF7 0 +OP4 E00AF8 0 +OP4 E00AF9 0 +OP4 E00AFA 0 +OP4 E00AFB 0 +OP4 E00AFC 0 +OP4 E00AFD 0 +OP4 E00AFE 0 +OP4 E00AFF 0 +OP4 E00B00 0 +OP4 E00B01 0 +OP4 E00B02 0 +OP4 E00B03 0 +OP4 E00B04 0 +OP4 E00B05 0 +OP4 E00B06 0 +OP4 E00B07 0 +OP4 E00B08 0 +OP4 E00B09 0 +OP4 E00B0A 0 +OP4 E00B0B 0 +OP4 E00B0C 0 +OP4 E00B0D 0 +OP4 E00B0E 0 +OP4 E00B0F 0 +OP4 E00B10 0 +OP4 E00B11 0 +OP4 E00B12 0 +OP4 E00B13 0 +OP4 E00B14 0 +OP4 E00B15 0 +OP4 E00B16 0 +OP4 E00B17 0 +OP4 E00B18 0 +OP4 E00B19 0 +OP4 E00B1A 0 +OP4 E00B1B 0 +OP4 E00B1C 0 +OP4 E00B1D 0 +OP4 E00B1E 0 +OP4 E00B1F 0 +OP4 E00B20 0 +OP4 E00B21 0 +OP4 E00B22 0 +OP4 E00B23 0 +OP4 E00B24 0 +OP4 E00B25 0 +OP4 E00B26 0 +OP4 E00B27 0 +OP4 E00B28 0 +OP4 E00B29 0 +OP4 E00B2A 0 +OP4 E00B2B 0 +OP4 E00B2C 0 +OP4 E00B2D 0 +OP4 E00B2E 0 +OP4 E00B2F 0 +OP4 E00B30 0 +OP4 E00B31 0 +OP4 E00B32 0 +OP4 E00B33 0 +OP4 E00B34 0 +OP4 E00B35 0 +OP4 E00B36 0 +OP4 E00B37 0 +OP4 E00B38 0 +OP4 E00B39 0 +OP4 E00B3A 0 +OP4 E00B3B 0 +OP4 E00B3C 0 +OP4 E00B3D 0 +OP4 E00B3E 0 +OP4 E00B3F 0 +OP4 E00B40 0 +OP4 E00B41 0 +OP4 E00B42 0 +OP4 E00B43 0 +OP4 E00B44 0 +OP4 E00B45 0 +OP4 E00B46 0 +OP4 E00B47 0 +OP4 E00B48 0 +OP4 E00B49 0 +OP4 E00B4A 0 +OP4 E00B4B 0 +OP4 E00B4C 0 +OP4 E00B4D 0 +OP4 E00B4E 0 +OP4 E00B4F 0 +OP4 E00B50 0 +OP4 E00B51 0 +OP4 E00B52 0 +OP4 E00B53 0 +OP4 E00B54 0 +OP4 E00B55 0 +OP4 E00B56 0 +OP4 E00B57 0 +OP4 E00B58 0 +OP4 E00B59 0 +OP4 E00B5A 0 +OP4 E00B5B 0 +OP4 E00B5C 0 +OP4 E00B5D 0 +OP4 E00B5E 0 +OP4 E00B5F 0 +OP4 E00B60 0 +OP4 E00B61 0 +OP4 E00B62 0 +OP4 E00B63 0 +OP4 E00B64 0 +OP4 E00B65 0 +OP4 E00B66 0 +OP4 E00B67 0 +OP4 E00B68 0 +OP4 E00B69 0 +OP4 E00B6A 0 +OP4 E00B6B 0 +OP4 E00B6C 0 +OP4 E00B6D 0 +OP4 E00B6E 0 +OP4 E00B6F 0 +OP4 E00B70 0 +OP4 E00B71 0 +OP4 E00B72 0 +OP4 E00B73 0 +OP4 E00B74 0 +OP4 E00B75 0 +OP4 E00B76 0 +OP4 E00B77 0 +OP4 E00B78 0 +OP4 E00B79 0 +OP4 E00B7A 0 +OP4 E00B7B 0 +OP4 E00B7C 0 +OP4 E00B7D 0 +OP4 E00B7E 0 +OP4 E00B7F 0 +OP4 E00B80 0 +OP4 E00B81 0 +OP4 E00B82 0 +OP4 E00B83 0 +OP4 E00B84 0 +OP4 E00B85 0 +OP4 E00B86 0 +OP4 E00B87 0 +OP4 E00B88 0 +OP4 E00B89 0 +OP4 E00B8A 0 +OP4 E00B8B 0 +OP4 E00B8C 0 +OP4 E00B8D 0 +OP4 E00B8E 0 +OP4 E00B8F 0 +OP4 E00B90 0 +OP4 E00B91 0 +OP4 E00B92 0 +OP4 E00B93 0 +OP4 E00B94 0 +OP4 E00B95 0 +OP4 E00B96 0 +OP4 E00B97 0 +OP4 E00B98 0 +OP4 E00B99 0 +OP4 E00B9A 0 +OP4 E00B9B 0 +OP4 E00B9C 0 +OP4 E00B9D 0 +OP4 E00B9E 0 +OP4 E00B9F 0 +OP4 E00BA0 0 +OP4 E00BA1 0 +OP4 E00BA2 0 +OP4 E00BA3 0 +OP4 E00BA4 0 +OP4 E00BA5 0 +OP4 E00BA6 0 +OP4 E00BA7 0 +OP4 E00BA8 0 +OP4 E00BA9 0 +OP4 E00BAA 0 +OP4 E00BAB 0 +OP4 E00BAC 0 +OP4 E00BAD 0 +OP4 E00BAE 0 +OP4 E00BAF 0 +OP4 E00BB0 0 +OP4 E00BB1 0 +OP4 E00BB2 0 +OP4 E00BB3 0 +OP4 E00BB4 0 +OP4 E00BB5 0 +OP4 E00BB6 0 +OP4 E00BB7 0 +OP4 E00BB8 0 +OP4 E00BB9 0 +OP4 E00BBA 0 +OP4 E00BBB 0 +OP4 E00BBC 0 +OP4 E00BBD 0 +OP4 E00BBE 0 +OP4 E00BBF 0 +OP4 E00BC0 0 +OP4 E00BC1 0 +OP4 E00BC2 0 +OP4 E00BC3 0 +OP4 E00BC4 0 +OP4 E00BC5 0 +OP4 E00BC6 0 +OP4 E00BC7 0 +OP4 E00BC8 0 +OP4 E00BC9 0 +OP4 E00BCA 0 +OP4 E00BCB 0 +OP4 E00BCC 0 +OP4 E00BCD 0 +OP4 E00BCE 0 +OP4 E00BCF 0 +OP4 E00BD0 0 +OP4 E00BD1 0 +OP4 E00BD2 0 +OP4 E00BD3 0 +OP4 E00BD4 0 +OP4 E00BD5 0 +OP4 E00BD6 0 +OP4 E00BD7 0 +OP4 E00BD8 0 +OP4 E00BD9 0 +OP4 E00BDA 0 +OP4 E00BDB 0 +OP4 E00BDC 0 +OP4 E00BDD 0 +OP4 E00BDE 0 +OP4 E00BDF 0 +OP4 E00BE0 0 +OP4 E00BE1 0 +OP4 E00BE2 0 +OP4 E00BE3 0 +OP4 E00BE4 0 +OP4 E00BE5 0 +OP4 E00BE6 0 +OP4 E00BE7 0 +OP4 E00BE8 0 +OP4 E00BE9 0 +OP4 E00BEA 0 +OP4 E00BEB 0 +OP4 E00BEC 0 +OP4 E00BED 0 +OP4 E00BEE 0 +OP4 E00BEF 0 +OP4 E00BF0 0 +OP4 E00BF1 0 +OP4 E00BF2 0 +OP4 E00BF3 0 +OP4 E00BF4 0 +OP4 E00BF5 0 +OP4 E00BF6 0 +OP4 E00BF7 0 +OP4 E00BF8 0 +OP4 E00BF9 0 +OP4 E00BFA 0 +OP4 E00BFB 0 +OP4 E00BFC 0 +OP4 E00BFD 0 +OP4 E00BFE 0 +OP4 E00BFF 0 +OP4 E00C00 0 +OP4 E00C01 0 +OP4 E00C02 0 +OP4 E00C03 0 +OP4 E00C04 0 +OP4 E00C05 0 +OP4 E00C06 0 +OP4 E00C07 0 +OP4 E00C08 0 +OP4 E00C09 0 +OP4 E00C0A 0 +OP4 E00C0B 0 +OP4 E00C0C 0 +OP4 E00C0D 0 +OP4 E00C0E 0 +OP4 E00C0F 0 +OP4 E00C10 0 +OP4 E00C11 0 +OP4 E00C12 0 +OP4 E00C13 0 +OP4 E00C14 0 +OP4 E00C15 0 +OP4 E00C16 0 +OP4 E00C17 0 +OP4 E00C18 0 +OP4 E00C19 0 +OP4 E00C1A 0 +OP4 E00C1B 0 +OP4 E00C1C 0 +OP4 E00C1D 0 +OP4 E00C1E 0 +OP4 E00C1F 0 +OP4 E00C20 0 +OP4 E00C21 0 +OP4 E00C22 0 +OP4 E00C23 0 +OP4 E00C24 0 +OP4 E00C25 0 +OP4 E00C26 0 +OP4 E00C27 0 +OP4 E00C28 0 +OP4 E00C29 0 +OP4 E00C2A 0 +OP4 E00C2B 0 +OP4 E00C2C 0 +OP4 E00C2D 0 +OP4 E00C2E 0 +OP4 E00C2F 0 +OP4 E00C30 0 +OP4 E00C31 0 +OP4 E00C32 0 +OP4 E00C33 0 +OP4 E00C34 0 +OP4 E00C35 0 +OP4 E00C36 0 +OP4 E00C37 0 +OP4 E00C38 0 +OP4 E00C39 0 +OP4 E00C3A 0 +OP4 E00C3B 0 +OP4 E00C3C 0 +OP4 E00C3D 0 +OP4 E00C3E 0 +OP4 E00C3F 0 +OP4 E00C40 0 +OP4 E00C41 0 +OP4 E00C42 0 +OP4 E00C43 0 +OP4 E00C44 0 +OP4 E00C45 0 +OP4 E00C46 0 +OP4 E00C47 0 +OP4 E00C48 0 +OP4 E00C49 0 +OP4 E00C4A 0 +OP4 E00C4B 0 +OP4 E00C4C 0 +OP4 E00C4D 0 +OP4 E00C4E 0 +OP4 E00C4F 0 +OP4 E00C50 0 +OP4 E00C51 0 +OP4 E00C52 0 +OP4 E00C53 0 +OP4 E00C54 0 +OP4 E00C55 0 +OP4 E00C56 0 +OP4 E00C57 0 +OP4 E00C58 0 +OP4 E00C59 0 +OP4 E00C5A 0 +OP4 E00C5B 0 +OP4 E00C5C 0 +OP4 E00C5D 0 +OP4 E00C5E 0 +OP4 E00C5F 0 +OP4 E00C60 0 +OP4 E00C61 0 +OP4 E00C62 0 +OP4 E00C63 0 +OP4 E00C64 0 +OP4 E00C65 0 +OP4 E00C66 0 +OP4 E00C67 0 +OP4 E00C68 0 +OP4 E00C69 0 +OP4 E00C6A 0 +OP4 E00C6B 0 +OP4 E00C6C 0 +OP4 E00C6D 0 +OP4 E00C6E 0 +OP4 E00C6F 0 +OP4 E00C70 0 +OP4 E00C71 0 +OP4 E00C72 0 +OP4 E00C73 0 +OP4 E00C74 0 +OP4 E00C75 0 +OP4 E00C76 0 +OP4 E00C77 0 +OP4 E00C78 0 +OP4 E00C79 0 +OP4 E00C7A 0 +OP4 E00C7B 0 +OP4 E00C7C 0 +OP4 E00C7D 0 +OP4 E00C7E 0 +OP4 E00C7F 0 +OP4 E00C80 0 +OP4 E00C81 0 +OP4 E00C82 0 +OP4 E00C83 0 +OP4 E00C84 0 +OP4 E00C85 0 +OP4 E00C86 0 +OP4 E00C87 0 +OP4 E00C88 0 +OP4 E00C89 0 +OP4 E00C8A 0 +OP4 E00C8B 0 +OP4 E00C8C 0 +OP4 E00C8D 0 +OP4 E00C8E 0 +OP4 E00C8F 0 +OP4 E00C90 0 +OP4 E00C91 0 +OP4 E00C92 0 +OP4 E00C93 0 +OP4 E00C94 0 +OP4 E00C95 0 +OP4 E00C96 0 +OP4 E00C97 0 +OP4 E00C98 0 +OP4 E00C99 0 +OP4 E00C9A 0 +OP4 E00C9B 0 +OP4 E00C9C 0 +OP4 E00C9D 0 +OP4 E00C9E 0 +OP4 E00C9F 0 +OP4 E00CA0 0 +OP4 E00CA1 0 +OP4 E00CA2 0 +OP4 E00CA3 0 +OP4 E00CA4 0 +OP4 E00CA5 0 +OP4 E00CA6 0 +OP4 E00CA7 0 +OP4 E00CA8 0 +OP4 E00CA9 0 +OP4 E00CAA 0 +OP4 E00CAB 0 +OP4 E00CAC 0 +OP4 E00CAD 0 +OP4 E00CAE 0 +OP4 E00CAF 0 +OP4 E00CB0 0 +OP4 E00CB1 0 +OP4 E00CB2 0 +OP4 E00CB3 0 +OP4 E00CB4 0 +OP4 E00CB5 0 +OP4 E00CB6 0 +OP4 E00CB7 0 +OP4 E00CB8 0 +OP4 E00CB9 0 +OP4 E00CBA 0 +OP4 E00CBB 0 +OP4 E00CBC 0 +OP4 E00CBD 0 +OP4 E00CBE 0 +OP4 E00CBF 0 +OP4 E00CC0 0 +OP4 E00CC1 0 +OP4 E00CC2 0 +OP4 E00CC3 0 +OP4 E00CC4 0 +OP4 E00CC5 0 +OP4 E00CC6 0 +OP4 E00CC7 0 +OP4 E00CC8 0 +OP4 E00CC9 0 +OP4 E00CCA 0 +OP4 E00CCB 0 +OP4 E00CCC 0 +OP4 E00CCD 0 +OP4 E00CCE 0 +OP4 E00CCF 0 +OP4 E00CD0 0 +OP4 E00CD1 0 +OP4 E00CD2 0 +OP4 E00CD3 0 +OP4 E00CD4 0 +OP4 E00CD5 0 +OP4 E00CD6 0 +OP4 E00CD7 0 +OP4 E00CD8 0 +OP4 E00CD9 0 +OP4 E00CDA 0 +OP4 E00CDB 0 +OP4 E00CDC 0 +OP4 E00CDD 0 +OP4 E00CDE 0 +OP4 E00CDF 0 +OP4 E00CE0 0 +OP4 E00CE1 0 +OP4 E00CE2 0 +OP4 E00CE3 0 +OP4 E00CE4 0 +OP4 E00CE5 0 +OP4 E00CE6 0 +OP4 E00CE7 0 +OP4 E00CE8 0 +OP4 E00CE9 0 +OP4 E00CEA 0 +OP4 E00CEB 0 +OP4 E00CEC 0 +OP4 E00CED 0 +OP4 E00CEE 0 +OP4 E00CEF 0 +OP4 E00CF0 0 +OP4 E00CF1 0 +OP4 E00CF2 0 +OP4 E00CF3 0 +OP4 E00CF4 0 +OP4 E00CF5 0 +OP4 E00CF6 0 +OP4 E00CF7 0 +OP4 E00CF8 0 +OP4 E00CF9 0 +OP4 E00CFA 0 +OP4 E00CFB 0 +OP4 E00CFC 0 +OP4 E00CFD 0 +OP4 E00CFE 0 +OP4 E00CFF 0 +OP4 E00D00 0 +OP4 E00D01 0 +OP4 E00D02 0 +OP4 E00D03 0 +OP4 E00D04 0 +OP4 E00D05 0 +OP4 E00D06 0 +OP4 E00D07 0 +OP4 E00D08 0 +OP4 E00D09 0 +OP4 E00D0A 0 +OP4 E00D0B 0 +OP4 E00D0C 0 +OP4 E00D0D 0 +OP4 E00D0E 0 +OP4 E00D0F 0 +OP4 E00D10 0 +OP4 E00D11 0 +OP4 E00D12 0 +OP4 E00D13 0 +OP4 E00D14 0 +OP4 E00D15 0 +OP4 E00D16 0 +OP4 E00D17 0 +OP4 E00D18 0 +OP4 E00D19 0 +OP4 E00D1A 0 +OP4 E00D1B 0 +OP4 E00D1C 0 +OP4 E00D1D 0 +OP4 E00D1E 0 +OP4 E00D1F 0 +OP4 E00D20 0 +OP4 E00D21 0 +OP4 E00D22 0 +OP4 E00D23 0 +OP4 E00D24 0 +OP4 E00D25 0 +OP4 E00D26 0 +OP4 E00D27 0 +OP4 E00D28 0 +OP4 E00D29 0 +OP4 E00D2A 0 +OP4 E00D2B 0 +OP4 E00D2C 0 +OP4 E00D2D 0 +OP4 E00D2E 0 +OP4 E00D2F 0 +OP4 E00D30 0 +OP4 E00D31 0 +OP4 E00D32 0 +OP4 E00D33 0 +OP4 E00D34 0 +OP4 E00D35 0 +OP4 E00D36 0 +OP4 E00D37 0 +OP4 E00D38 0 +OP4 E00D39 0 +OP4 E00D3A 0 +OP4 E00D3B 0 +OP4 E00D3C 0 +OP4 E00D3D 0 +OP4 E00D3E 0 +OP4 E00D3F 0 +OP4 E00D40 0 +OP4 E00D41 0 +OP4 E00D42 0 +OP4 E00D43 0 +OP4 E00D44 0 +OP4 E00D45 0 +OP4 E00D46 0 +OP4 E00D47 0 +OP4 E00D48 0 +OP4 E00D49 0 +OP4 E00D4A 0 +OP4 E00D4B 0 +OP4 E00D4C 0 +OP4 E00D4D 0 +OP4 E00D4E 0 +OP4 E00D4F 0 +OP4 E00D50 0 +OP4 E00D51 0 +OP4 E00D52 0 +OP4 E00D53 0 +OP4 E00D54 0 +OP4 E00D55 0 +OP4 E00D56 0 +OP4 E00D57 0 +OP4 E00D58 0 +OP4 E00D59 0 +OP4 E00D5A 0 +OP4 E00D5B 0 +OP4 E00D5C 0 +OP4 E00D5D 0 +OP4 E00D5E 0 +OP4 E00D5F 0 +OP4 E00D60 0 +OP4 E00D61 0 +OP4 E00D62 0 +OP4 E00D63 0 +OP4 E00D64 0 +OP4 E00D65 0 +OP4 E00D66 0 +OP4 E00D67 0 +OP4 E00D68 0 +OP4 E00D69 0 +OP4 E00D6A 0 +OP4 E00D6B 0 +OP4 E00D6C 0 +OP4 E00D6D 0 +OP4 E00D6E 0 +OP4 E00D6F 0 +OP4 E00D70 0 +OP4 E00D71 0 +OP4 E00D72 0 +OP4 E00D73 0 +OP4 E00D74 0 +OP4 E00D75 0 +OP4 E00D76 0 +OP4 E00D77 0 +OP4 E00D78 0 +OP4 E00D79 0 +OP4 E00D7A 0 +OP4 E00D7B 0 +OP4 E00D7C 0 +OP4 E00D7D 0 +OP4 E00D7E 0 +OP4 E00D7F 0 +OP4 E00D80 0 +OP4 E00D81 0 +OP4 E00D82 0 +OP4 E00D83 0 +OP4 E00D84 0 +OP4 E00D85 0 +OP4 E00D86 0 +OP4 E00D87 0 +OP4 E00D88 0 +OP4 E00D89 0 +OP4 E00D8A 0 +OP4 E00D8B 0 +OP4 E00D8C 0 +OP4 E00D8D 0 +OP4 E00D8E 0 +OP4 E00D8F 0 +OP4 E00D90 0 +OP4 E00D91 0 +OP4 E00D92 0 +OP4 E00D93 0 +OP4 E00D94 0 +OP4 E00D95 0 +OP4 E00D96 0 +OP4 E00D97 0 +OP4 E00D98 0 +OP4 E00D99 0 +OP4 E00D9A 0 +OP4 E00D9B 0 +OP4 E00D9C 0 +OP4 E00D9D 0 +OP4 E00D9E 0 +OP4 E00D9F 0 +OP4 E00DA0 0 +OP4 E00DA1 0 +OP4 E00DA2 0 +OP4 E00DA3 0 +OP4 E00DA4 0 +OP4 E00DA5 0 +OP4 E00DA6 0 +OP4 E00DA7 0 +OP4 E00DA8 0 +OP4 E00DA9 0 +OP4 E00DAA 0 +OP4 E00DAB 0 +OP4 E00DAC 0 +OP4 E00DAD 0 +OP4 E00DAE 0 +OP4 E00DAF 0 +OP4 E00DB0 0 +OP4 E00DB1 0 +OP4 E00DB2 0 +OP4 E00DB3 0 +OP4 E00DB4 0 +OP4 E00DB5 0 +OP4 E00DB6 0 +OP4 E00DB7 0 +OP4 E00DB8 0 +OP4 E00DB9 0 +OP4 E00DBA 0 +OP4 E00DBB 0 +OP4 E00DBC 0 +OP4 E00DBD 0 +OP4 E00DBE 0 +OP4 E00DBF 0 +OP4 E00DC0 0 +OP4 E00DC1 0 +OP4 E00DC2 0 +OP4 E00DC3 0 +OP4 E00DC4 0 +OP4 E00DC5 0 +OP4 E00DC6 0 +OP4 E00DC7 0 +OP4 E00DC8 0 +OP4 E00DC9 0 +OP4 E00DCA 0 +OP4 E00DCB 0 +OP4 E00DCC 0 +OP4 E00DCD 0 +OP4 E00DCE 0 +OP4 E00DCF 0 +OP4 E00DD0 0 +OP4 E00DD1 0 +OP4 E00DD2 0 +OP4 E00DD3 0 +OP4 E00DD4 0 +OP4 E00DD5 0 +OP4 E00DD6 0 +OP4 E00DD7 0 +OP4 E00DD8 0 +OP4 E00DD9 0 +OP4 E00DDA 0 +OP4 E00DDB 0 +OP4 E00DDC 0 +OP4 E00DDD 0 +OP4 E00DDE 0 +OP4 E00DDF 0 +OP4 E00DE0 0 +OP4 E00DE1 0 +OP4 E00DE2 0 +OP4 E00DE3 0 +OP4 E00DE4 0 +OP4 E00DE5 0 +OP4 E00DE6 0 +OP4 E00DE7 0 +OP4 E00DE8 0 +OP4 E00DE9 0 +OP4 E00DEA 0 +OP4 E00DEB 0 +OP4 E00DEC 0 +OP4 E00DED 0 +OP4 E00DEE 0 +OP4 E00DEF 0 +OP4 E00DF0 0 +OP4 E00DF1 0 +OP4 E00DF2 0 +OP4 E00DF3 0 +OP4 E00DF4 0 +OP4 E00DF5 0 +OP4 E00DF6 0 +OP4 E00DF7 0 +OP4 E00DF8 0 +OP4 E00DF9 0 +OP4 E00DFA 0 +OP4 E00DFB 0 +OP4 E00DFC 0 +OP4 E00DFD 0 +OP4 E00DFE 0 +OP4 E00DFF 0 +OP4 E00E00 0 +OP4 E00E01 0 +OP4 E00E02 0 +OP4 E00E03 0 +OP4 E00E04 0 +OP4 E00E05 0 +OP4 E00E06 0 +OP4 E00E07 0 +OP4 E00E08 0 +OP4 E00E09 0 +OP4 E00E0A 0 +OP4 E00E0B 0 +OP4 E00E0C 0 +OP4 E00E0D 0 +OP4 E00E0E 0 +OP4 E00E0F 0 +OP4 E00E10 0 +OP4 E00E11 0 +OP4 E00E12 0 +OP4 E00E13 0 +OP4 E00E14 0 +OP4 E00E15 0 +OP4 E00E16 0 +OP4 E00E17 0 +OP4 E00E18 0 +OP4 E00E19 0 +OP4 E00E1A 0 +OP4 E00E1B 0 +OP4 E00E1C 0 +OP4 E00E1D 0 +OP4 E00E1E 0 +OP4 E00E1F 0 +OP4 E00E20 0 +OP4 E00E21 0 +OP4 E00E22 0 +OP4 E00E23 0 +OP4 E00E24 0 +OP4 E00E25 0 +OP4 E00E26 0 +OP4 E00E27 0 +OP4 E00E28 0 +OP4 E00E29 0 +OP4 E00E2A 0 +OP4 E00E2B 0 +OP4 E00E2C 0 +OP4 E00E2D 0 +OP4 E00E2E 0 +OP4 E00E2F 0 +OP4 E00E30 0 +OP4 E00E31 0 +OP4 E00E32 0 +OP4 E00E33 0 +OP4 E00E34 0 +OP4 E00E35 0 +OP4 E00E36 0 +OP4 E00E37 0 +OP4 E00E38 0 +OP4 E00E39 0 +OP4 E00E3A 0 +OP4 E00E3B 0 +OP4 E00E3C 0 +OP4 E00E3D 0 +OP4 E00E3E 0 +OP4 E00E3F 0 +OP4 E00E40 0 +OP4 E00E41 0 +OP4 E00E42 0 +OP4 E00E43 0 +OP4 E00E44 0 +OP4 E00E45 0 +OP4 E00E46 0 +OP4 E00E47 0 +OP4 E00E48 0 +OP4 E00E49 0 +OP4 E00E4A 0 +OP4 E00E4B 0 +OP4 E00E4C 0 +OP4 E00E4D 0 +OP4 E00E4E 0 +OP4 E00E4F 0 +OP4 E00E50 0 +OP4 E00E51 0 +OP4 E00E52 0 +OP4 E00E53 0 +OP4 E00E54 0 +OP4 E00E55 0 +OP4 E00E56 0 +OP4 E00E57 0 +OP4 E00E58 0 +OP4 E00E59 0 +OP4 E00E5A 0 +OP4 E00E5B 0 +OP4 E00E5C 0 +OP4 E00E5D 0 +OP4 E00E5E 0 +OP4 E00E5F 0 +OP4 E00E60 0 +OP4 E00E61 0 +OP4 E00E62 0 +OP4 E00E63 0 +OP4 E00E64 0 +OP4 E00E65 0 +OP4 E00E66 0 +OP4 E00E67 0 +OP4 E00E68 0 +OP4 E00E69 0 +OP4 E00E6A 0 +OP4 E00E6B 0 +OP4 E00E6C 0 +OP4 E00E6D 0 +OP4 E00E6E 0 +OP4 E00E6F 0 +OP4 E00E70 0 +OP4 E00E71 0 +OP4 E00E72 0 +OP4 E00E73 0 +OP4 E00E74 0 +OP4 E00E75 0 +OP4 E00E76 0 +OP4 E00E77 0 +OP4 E00E78 0 +OP4 E00E79 0 +OP4 E00E7A 0 +OP4 E00E7B 0 +OP4 E00E7C 0 +OP4 E00E7D 0 +OP4 E00E7E 0 +OP4 E00E7F 0 +OP4 E00E80 0 +OP4 E00E81 0 +OP4 E00E82 0 +OP4 E00E83 0 +OP4 E00E84 0 +OP4 E00E85 0 +OP4 E00E86 0 +OP4 E00E87 0 +OP4 E00E88 0 +OP4 E00E89 0 +OP4 E00E8A 0 +OP4 E00E8B 0 +OP4 E00E8C 0 +OP4 E00E8D 0 +OP4 E00E8E 0 +OP4 E00E8F 0 +OP4 E00E90 0 +OP4 E00E91 0 +OP4 E00E92 0 +OP4 E00E93 0 +OP4 E00E94 0 +OP4 E00E95 0 +OP4 E00E96 0 +OP4 E00E97 0 +OP4 E00E98 0 +OP4 E00E99 0 +OP4 E00E9A 0 +OP4 E00E9B 0 +OP4 E00E9C 0 +OP4 E00E9D 0 +OP4 E00E9E 0 +OP4 E00E9F 0 +OP4 E00EA0 0 +OP4 E00EA1 0 +OP4 E00EA2 0 +OP4 E00EA3 0 +OP4 E00EA4 0 +OP4 E00EA5 0 +OP4 E00EA6 0 +OP4 E00EA7 0 +OP4 E00EA8 0 +OP4 E00EA9 0 +OP4 E00EAA 0 +OP4 E00EAB 0 +OP4 E00EAC 0 +OP4 E00EAD 0 +OP4 E00EAE 0 +OP4 E00EAF 0 +OP4 E00EB0 0 +OP4 E00EB1 0 +OP4 E00EB2 0 +OP4 E00EB3 0 +OP4 E00EB4 0 +OP4 E00EB5 0 +OP4 E00EB6 0 +OP4 E00EB7 0 +OP4 E00EB8 0 +OP4 E00EB9 0 +OP4 E00EBA 0 +OP4 E00EBB 0 +OP4 E00EBC 0 +OP4 E00EBD 0 +OP4 E00EBE 0 +OP4 E00EBF 0 +OP4 E00EC0 0 +OP4 E00EC1 0 +OP4 E00EC2 0 +OP4 E00EC3 0 +OP4 E00EC4 0 +OP4 E00EC5 0 +OP4 E00EC6 0 +OP4 E00EC7 0 +OP4 E00EC8 0 +OP4 E00EC9 0 +OP4 E00ECA 0 +OP4 E00ECB 0 +OP4 E00ECC 0 +OP4 E00ECD 0 +OP4 E00ECE 0 +OP4 E00ECF 0 +OP4 E00ED0 0 +OP4 E00ED1 0 +OP4 E00ED2 0 +OP4 E00ED3 0 +OP4 E00ED4 0 +OP4 E00ED5 0 +OP4 E00ED6 0 +OP4 E00ED7 0 +OP4 E00ED8 0 +OP4 E00ED9 0 +OP4 E00EDA 0 +OP4 E00EDB 0 +OP4 E00EDC 0 +OP4 E00EDD 0 +OP4 E00EDE 0 +OP4 E00EDF 0 +OP4 E00EE0 0 +OP4 E00EE1 0 +OP4 E00EE2 0 +OP4 E00EE3 0 +OP4 E00EE4 0 +OP4 E00EE5 0 +OP4 E00EE6 0 +OP4 E00EE7 0 +OP4 E00EE8 0 +OP4 E00EE9 0 +OP4 E00EEA 0 +OP4 E00EEB 0 +OP4 E00EEC 0 +OP4 E00EED 0 +OP4 E00EEE 0 +OP4 E00EEF 0 +OP4 E00EF0 0 +OP4 E00EF1 0 +OP4 E00EF2 0 +OP4 E00EF3 0 +OP4 E00EF4 0 +OP4 E00EF5 0 +OP4 E00EF6 0 +OP4 E00EF7 0 +OP4 E00EF8 0 +OP4 E00EF9 0 +OP4 E00EFA 0 +OP4 E00EFB 0 +OP4 E00EFC 0 +OP4 E00EFD 0 +OP4 E00EFE 0 +OP4 E00EFF 0 +OP4 E00F00 0 +OP4 E00F01 0 +OP4 E00F02 0 +OP4 E00F03 0 +OP4 E00F04 0 +OP4 E00F05 0 +OP4 E00F06 0 +OP4 E00F07 0 +OP4 E00F08 0 +OP4 E00F09 0 +OP4 E00F0A 0 +OP4 E00F0B 0 +OP4 E00F0C 0 +OP4 E00F0D 0 +OP4 E00F0E 0 +OP4 E00F0F 0 +OP4 E00F10 0 +OP4 E00F11 0 +OP4 E00F12 0 +OP4 E00F13 0 +OP4 E00F14 0 +OP4 E00F15 0 +OP4 E00F16 0 +OP4 E00F17 0 +OP4 E00F18 0 +OP4 E00F19 0 +OP4 E00F1A 0 +OP4 E00F1B 0 +OP4 E00F1C 0 +OP4 E00F1D 0 +OP4 E00F1E 0 +OP4 E00F1F 0 +OP4 E00F20 0 +OP4 E00F21 0 +OP4 E00F22 0 +OP4 E00F23 0 +OP4 E00F24 0 +OP4 E00F25 0 +OP4 E00F26 0 +OP4 E00F27 0 +OP4 E00F28 0 +OP4 E00F29 0 +OP4 E00F2A 0 +OP4 E00F2B 0 +OP4 E00F2C 0 +OP4 E00F2D 0 +OP4 E00F2E 0 +OP4 E00F2F 0 +OP4 E00F30 0 diff --git a/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum3_itrace_irisc5.cfg.ext b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum3_itrace_irisc5.cfg.ext new file mode 100644 index 000000000000..0b5c4434a32f --- /dev/null +++ b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum3_itrace_irisc5.cfg.ext @@ -0,0 +1,3890 @@ +OP1 Spectrum3 +OP4 ITRACE0 0 +OP4 ITRACE1 0 +OP4 ITRACE2 0 +OP4 ITRACE3 0 +OP4 ITRACE4 0 +OP4 ITRACE5 1 +OP4 ITRACE6 0 +OP4 ITRACE7 0 +OP4 ITRACE8 0 +OP4 ITRACE9 0 +OP4 Main_PhyUC 0 +OP4 TILE0_ITRACE0 0 +OP4 TILE0_ITRACE1 0 +OP4 TILE0_ITRACE2 0 +OP4 TILE0_ITRACE3 0 +OP4 TILE0_ITRACE4 0 +OP4 TILE0_PhyUC 0 +OP4 TILE1_ITRACE0 0 +OP4 TILE1_ITRACE1 0 +OP4 TILE1_ITRACE2 0 +OP4 TILE1_ITRACE3 0 +OP4 TILE1_ITRACE4 0 +OP4 TILE1_PhyUC 0 +OP4 TILE2_ITRACE0 0 +OP4 TILE2_ITRACE1 0 +OP4 TILE2_ITRACE2 0 +OP4 TILE2_ITRACE3 0 +OP4 TILE2_ITRACE4 0 +OP4 TILE2_PhyUC 0 +OP4 TILE3_ITRACE0 0 +OP4 TILE3_ITRACE1 0 +OP4 TILE3_ITRACE2 0 +OP4 TILE3_ITRACE3 0 +OP4 TILE3_ITRACE4 0 +OP4 TILE3_PhyUC 0 +OP4 TILE4_ITRACE0 0 +OP4 TILE4_ITRACE1 0 +OP4 TILE4_ITRACE2 0 +OP4 TILE4_ITRACE3 0 +OP4 TILE4_ITRACE4 0 +OP4 TILE4_PhyUC 0 +OP4 TILE5_ITRACE0 0 +OP4 TILE5_ITRACE1 0 +OP4 TILE5_ITRACE2 0 +OP4 TILE5_ITRACE3 0 +OP4 TILE5_ITRACE4 0 +OP4 TILE5_PhyUC 0 +OP4 TILE6_ITRACE0 0 +OP4 TILE6_ITRACE1 0 +OP4 TILE6_ITRACE2 0 +OP4 TILE6_ITRACE3 0 +OP4 TILE6_ITRACE4 0 +OP4 TILE6_PhyUC 0 +OP4 TILE7_ITRACE0 0 +OP4 TILE7_ITRACE1 0 +OP4 TILE7_ITRACE2 0 +OP4 TILE7_ITRACE3 0 +OP4 TILE7_ITRACE4 0 +OP4 TILE7_PhyUC 0 +OP4 E0003B 0 +OP4 E0003C 0 +OP4 E0003D 0 +OP4 E0003E 0 +OP4 E0003F 0 +OP4 E00040 0 +OP4 E00041 0 +OP4 E00042 0 +OP4 E00043 0 +OP4 E00044 0 +OP4 E00045 0 +OP4 E00046 0 +OP4 E00047 0 +OP4 E00048 0 +OP4 E00049 0 +OP4 E0004A 0 +OP4 E0004B 0 +OP4 E0004C 0 +OP4 E0004D 0 +OP4 E0004E 0 +OP4 E0004F 0 +OP4 E00050 0 +OP4 E00051 0 +OP4 E00052 0 +OP4 E00053 0 +OP4 E00054 0 +OP4 E00055 0 +OP4 E00056 0 +OP4 E00057 0 +OP4 E00058 0 +OP4 E00059 0 +OP4 E0005A 0 +OP4 E0005B 0 +OP4 E0005C 0 +OP4 E0005D 0 +OP4 E0005E 0 +OP4 E0005F 0 +OP4 E00060 0 +OP4 E00061 0 +OP4 E00062 0 +OP4 E00063 0 +OP4 E00064 0 +OP4 E00065 0 +OP4 E00066 0 +OP4 E00067 0 +OP4 E00068 0 +OP4 E00069 0 +OP4 E0006A 0 +OP4 E0006B 0 +OP4 E0006C 0 +OP4 E0006D 0 +OP4 E0006E 0 +OP4 E0006F 0 +OP4 E00070 0 +OP4 E00071 0 +OP4 E00072 0 +OP4 E00073 0 +OP4 E00074 0 +OP4 E00075 0 +OP4 E00076 0 +OP4 E00077 0 +OP4 E00078 0 +OP4 E00079 0 +OP4 E0007A 0 +OP4 E0007B 0 +OP4 E0007C 0 +OP4 E0007D 0 +OP4 E0007E 0 +OP4 E0007F 0 +OP4 E00080 0 +OP4 E00081 0 +OP4 E00082 0 +OP4 E00083 0 +OP4 E00084 0 +OP4 E00085 0 +OP4 E00086 0 +OP4 E00087 0 +OP4 E00088 0 +OP4 E00089 0 +OP4 E0008A 0 +OP4 E0008B 0 +OP4 E0008C 0 +OP4 E0008D 0 +OP4 E0008E 0 +OP4 E0008F 0 +OP4 E00090 0 +OP4 E00091 0 +OP4 E00092 0 +OP4 E00093 0 +OP4 E00094 0 +OP4 E00095 0 +OP4 E00096 0 +OP4 E00097 0 +OP4 E00098 0 +OP4 E00099 0 +OP4 E0009A 0 +OP4 E0009B 0 +OP4 E0009C 0 +OP4 E0009D 0 +OP4 E0009E 0 +OP4 E0009F 0 +OP4 E000A0 0 +OP4 E000A1 0 +OP4 E000A2 0 +OP4 E000A3 0 +OP4 E000A4 0 +OP4 E000A5 0 +OP4 E000A6 0 +OP4 E000A7 0 +OP4 E000A8 0 +OP4 E000A9 0 +OP4 E000AA 0 +OP4 E000AB 0 +OP4 E000AC 0 +OP4 E000AD 0 +OP4 E000AE 0 +OP4 E000AF 0 +OP4 E000B0 0 +OP4 E000B1 0 +OP4 E000B2 0 +OP4 E000B3 0 +OP4 E000B4 0 +OP4 E000B5 0 +OP4 E000B6 0 +OP4 E000B7 0 +OP4 E000B8 0 +OP4 E000B9 0 +OP4 E000BA 0 +OP4 E000BB 0 +OP4 E000BC 0 +OP4 E000BD 0 +OP4 E000BE 0 +OP4 E000BF 0 +OP4 E000C0 0 +OP4 E000C1 0 +OP4 E000C2 0 +OP4 E000C3 0 +OP4 E000C4 0 +OP4 E000C5 0 +OP4 E000C6 0 +OP4 E000C7 0 +OP4 E000C8 0 +OP4 E000C9 0 +OP4 E000CA 0 +OP4 E000CB 0 +OP4 E000CC 0 +OP4 E000CD 0 +OP4 E000CE 0 +OP4 E000CF 0 +OP4 E000D0 0 +OP4 E000D1 0 +OP4 E000D2 0 +OP4 E000D3 0 +OP4 E000D4 0 +OP4 E000D5 0 +OP4 E000D6 0 +OP4 E000D7 0 +OP4 E000D8 0 +OP4 E000D9 0 +OP4 E000DA 0 +OP4 E000DB 0 +OP4 E000DC 0 +OP4 E000DD 0 +OP4 E000DE 0 +OP4 E000DF 0 +OP4 E000E0 0 +OP4 E000E1 0 +OP4 E000E2 0 +OP4 E000E3 0 +OP4 E000E4 0 +OP4 E000E5 0 +OP4 E000E6 0 +OP4 E000E7 0 +OP4 E000E8 0 +OP4 E000E9 0 +OP4 E000EA 0 +OP4 E000EB 0 +OP4 E000EC 0 +OP4 E000ED 0 +OP4 E000EE 0 +OP4 E000EF 0 +OP4 E000F0 0 +OP4 E000F1 0 +OP4 E000F2 0 +OP4 E000F3 0 +OP4 E000F4 0 +OP4 E000F5 0 +OP4 E000F6 0 +OP4 E000F7 0 +OP4 E000F8 0 +OP4 E000F9 0 +OP4 E000FA 0 +OP4 E000FB 0 +OP4 E000FC 0 +OP4 E000FD 0 +OP4 E000FE 0 +OP4 E000FF 0 +OP4 E00100 0 +OP4 E00101 0 +OP4 E00102 0 +OP4 E00103 0 +OP4 E00104 0 +OP4 E00105 0 +OP4 E00106 0 +OP4 E00107 0 +OP4 E00108 0 +OP4 E00109 0 +OP4 E0010A 0 +OP4 E0010B 0 +OP4 E0010C 0 +OP4 E0010D 0 +OP4 E0010E 0 +OP4 E0010F 0 +OP4 E00110 0 +OP4 E00111 0 +OP4 E00112 0 +OP4 E00113 0 +OP4 E00114 0 +OP4 E00115 0 +OP4 E00116 0 +OP4 E00117 0 +OP4 E00118 0 +OP4 E00119 0 +OP4 E0011A 0 +OP4 E0011B 0 +OP4 E0011C 0 +OP4 E0011D 0 +OP4 E0011E 0 +OP4 E0011F 0 +OP4 E00120 0 +OP4 E00121 0 +OP4 E00122 0 +OP4 E00123 0 +OP4 E00124 0 +OP4 E00125 0 +OP4 E00126 0 +OP4 E00127 0 +OP4 E00128 0 +OP4 E00129 0 +OP4 E0012A 0 +OP4 E0012B 0 +OP4 E0012C 0 +OP4 E0012D 0 +OP4 E0012E 0 +OP4 E0012F 0 +OP4 E00130 0 +OP4 E00131 0 +OP4 E00132 0 +OP4 E00133 0 +OP4 E00134 0 +OP4 E00135 0 +OP4 E00136 0 +OP4 E00137 0 +OP4 E00138 0 +OP4 E00139 0 +OP4 E0013A 0 +OP4 E0013B 0 +OP4 E0013C 0 +OP4 E0013D 0 +OP4 E0013E 0 +OP4 E0013F 0 +OP4 E00140 0 +OP4 E00141 0 +OP4 E00142 0 +OP4 E00143 0 +OP4 E00144 0 +OP4 E00145 0 +OP4 E00146 0 +OP4 E00147 0 +OP4 E00148 0 +OP4 E00149 0 +OP4 E0014A 0 +OP4 E0014B 0 +OP4 E0014C 0 +OP4 E0014D 0 +OP4 E0014E 0 +OP4 E0014F 0 +OP4 E00150 0 +OP4 E00151 0 +OP4 E00152 0 +OP4 E00153 0 +OP4 E00154 0 +OP4 E00155 0 +OP4 E00156 0 +OP4 E00157 0 +OP4 E00158 0 +OP4 E00159 0 +OP4 E0015A 0 +OP4 E0015B 0 +OP4 E0015C 0 +OP4 E0015D 0 +OP4 E0015E 0 +OP4 E0015F 0 +OP4 E00160 0 +OP4 E00161 0 +OP4 E00162 0 +OP4 E00163 0 +OP4 E00164 0 +OP4 E00165 0 +OP4 E00166 0 +OP4 E00167 0 +OP4 E00168 0 +OP4 E00169 0 +OP4 E0016A 0 +OP4 E0016B 0 +OP4 E0016C 0 +OP4 E0016D 0 +OP4 E0016E 0 +OP4 E0016F 0 +OP4 E00170 0 +OP4 E00171 0 +OP4 E00172 0 +OP4 E00173 0 +OP4 E00174 0 +OP4 E00175 0 +OP4 E00176 0 +OP4 E00177 0 +OP4 E00178 0 +OP4 E00179 0 +OP4 E0017A 0 +OP4 E0017B 0 +OP4 E0017C 0 +OP4 E0017D 0 +OP4 E0017E 0 +OP4 E0017F 0 +OP4 E00180 0 +OP4 E00181 0 +OP4 E00182 0 +OP4 E00183 0 +OP4 E00184 0 +OP4 E00185 0 +OP4 E00186 0 +OP4 E00187 0 +OP4 E00188 0 +OP4 E00189 0 +OP4 E0018A 0 +OP4 E0018B 0 +OP4 E0018C 0 +OP4 E0018D 0 +OP4 E0018E 0 +OP4 E0018F 0 +OP4 E00190 0 +OP4 E00191 0 +OP4 E00192 0 +OP4 E00193 0 +OP4 E00194 0 +OP4 E00195 0 +OP4 E00196 0 +OP4 E00197 0 +OP4 E00198 0 +OP4 E00199 0 +OP4 E0019A 0 +OP4 E0019B 0 +OP4 E0019C 0 +OP4 E0019D 0 +OP4 E0019E 0 +OP4 E0019F 0 +OP4 E001A0 0 +OP4 E001A1 0 +OP4 E001A2 0 +OP4 E001A3 0 +OP4 E001A4 0 +OP4 E001A5 0 +OP4 E001A6 0 +OP4 E001A7 0 +OP4 E001A8 0 +OP4 E001A9 0 +OP4 E001AA 0 +OP4 E001AB 0 +OP4 E001AC 0 +OP4 E001AD 0 +OP4 E001AE 0 +OP4 E001AF 0 +OP4 E001B0 0 +OP4 E001B1 0 +OP4 E001B2 0 +OP4 E001B3 0 +OP4 E001B4 0 +OP4 E001B5 0 +OP4 E001B6 0 +OP4 E001B7 0 +OP4 E001B8 0 +OP4 E001B9 0 +OP4 E001BA 0 +OP4 E001BB 0 +OP4 E001BC 0 +OP4 E001BD 0 +OP4 E001BE 0 +OP4 E001BF 0 +OP4 E001C0 0 +OP4 E001C1 0 +OP4 E001C2 0 +OP4 E001C3 0 +OP4 E001C4 0 +OP4 E001C5 0 +OP4 E001C6 0 +OP4 E001C7 0 +OP4 E001C8 0 +OP4 E001C9 0 +OP4 E001CA 0 +OP4 E001CB 0 +OP4 E001CC 0 +OP4 E001CD 0 +OP4 E001CE 0 +OP4 E001CF 0 +OP4 E001D0 0 +OP4 E001D1 0 +OP4 E001D2 0 +OP4 E001D3 0 +OP4 E001D4 0 +OP4 E001D5 0 +OP4 E001D6 0 +OP4 E001D7 0 +OP4 E001D8 0 +OP4 E001D9 0 +OP4 E001DA 0 +OP4 E001DB 0 +OP4 E001DC 0 +OP4 E001DD 0 +OP4 E001DE 0 +OP4 E001DF 0 +OP4 E001E0 0 +OP4 E001E1 0 +OP4 E001E2 0 +OP4 E001E3 0 +OP4 E001E4 0 +OP4 E001E5 0 +OP4 E001E6 0 +OP4 E001E7 0 +OP4 E001E8 0 +OP4 E001E9 0 +OP4 E001EA 0 +OP4 E001EB 0 +OP4 E001EC 0 +OP4 E001ED 0 +OP4 E001EE 0 +OP4 E001EF 0 +OP4 E001F0 0 +OP4 E001F1 0 +OP4 E001F2 0 +OP4 E001F3 0 +OP4 E001F4 0 +OP4 E001F5 0 +OP4 E001F6 0 +OP4 E001F7 0 +OP4 E001F8 0 +OP4 E001F9 0 +OP4 E001FA 0 +OP4 E001FB 0 +OP4 E001FC 0 +OP4 E001FD 0 +OP4 E001FE 0 +OP4 E001FF 0 +OP4 E00200 0 +OP4 E00201 0 +OP4 E00202 0 +OP4 E00203 0 +OP4 E00204 0 +OP4 E00205 0 +OP4 E00206 0 +OP4 E00207 0 +OP4 E00208 0 +OP4 E00209 0 +OP4 E0020A 0 +OP4 E0020B 0 +OP4 E0020C 0 +OP4 E0020D 0 +OP4 E0020E 0 +OP4 E0020F 0 +OP4 E00210 0 +OP4 E00211 0 +OP4 E00212 0 +OP4 E00213 0 +OP4 E00214 0 +OP4 E00215 0 +OP4 E00216 0 +OP4 E00217 0 +OP4 E00218 0 +OP4 E00219 0 +OP4 E0021A 0 +OP4 E0021B 0 +OP4 E0021C 0 +OP4 E0021D 0 +OP4 E0021E 0 +OP4 E0021F 0 +OP4 E00220 0 +OP4 E00221 0 +OP4 E00222 0 +OP4 E00223 0 +OP4 E00224 0 +OP4 E00225 0 +OP4 E00226 0 +OP4 E00227 0 +OP4 E00228 0 +OP4 E00229 0 +OP4 E0022A 0 +OP4 E0022B 0 +OP4 E0022C 0 +OP4 E0022D 0 +OP4 E0022E 0 +OP4 E0022F 0 +OP4 E00230 0 +OP4 E00231 0 +OP4 E00232 0 +OP4 E00233 0 +OP4 E00234 0 +OP4 E00235 0 +OP4 E00236 0 +OP4 E00237 0 +OP4 E00238 0 +OP4 E00239 0 +OP4 E0023A 0 +OP4 E0023B 0 +OP4 E0023C 0 +OP4 E0023D 0 +OP4 E0023E 0 +OP4 E0023F 0 +OP4 E00240 0 +OP4 E00241 0 +OP4 E00242 0 +OP4 E00243 0 +OP4 E00244 0 +OP4 E00245 0 +OP4 E00246 0 +OP4 E00247 0 +OP4 E00248 0 +OP4 E00249 0 +OP4 E0024A 0 +OP4 E0024B 0 +OP4 E0024C 0 +OP4 E0024D 0 +OP4 E0024E 0 +OP4 E0024F 0 +OP4 E00250 0 +OP4 E00251 0 +OP4 E00252 0 +OP4 E00253 0 +OP4 E00254 0 +OP4 E00255 0 +OP4 E00256 0 +OP4 E00257 0 +OP4 E00258 0 +OP4 E00259 0 +OP4 E0025A 0 +OP4 E0025B 0 +OP4 E0025C 0 +OP4 E0025D 0 +OP4 E0025E 0 +OP4 E0025F 0 +OP4 E00260 0 +OP4 E00261 0 +OP4 E00262 0 +OP4 E00263 0 +OP4 E00264 0 +OP4 E00265 0 +OP4 E00266 0 +OP4 E00267 0 +OP4 E00268 0 +OP4 E00269 0 +OP4 E0026A 0 +OP4 E0026B 0 +OP4 E0026C 0 +OP4 E0026D 0 +OP4 E0026E 0 +OP4 E0026F 0 +OP4 E00270 0 +OP4 E00271 0 +OP4 E00272 0 +OP4 E00273 0 +OP4 E00274 0 +OP4 E00275 0 +OP4 E00276 0 +OP4 E00277 0 +OP4 E00278 0 +OP4 E00279 0 +OP4 E0027A 0 +OP4 E0027B 0 +OP4 E0027C 0 +OP4 E0027D 0 +OP4 E0027E 0 +OP4 E0027F 0 +OP4 E00280 0 +OP4 E00281 0 +OP4 E00282 0 +OP4 E00283 0 +OP4 E00284 0 +OP4 E00285 0 +OP4 E00286 0 +OP4 E00287 0 +OP4 E00288 0 +OP4 E00289 0 +OP4 E0028A 0 +OP4 E0028B 0 +OP4 E0028C 0 +OP4 E0028D 0 +OP4 E0028E 0 +OP4 E0028F 0 +OP4 E00290 0 +OP4 E00291 0 +OP4 E00292 0 +OP4 E00293 0 +OP4 E00294 0 +OP4 E00295 0 +OP4 E00296 0 +OP4 E00297 0 +OP4 E00298 0 +OP4 E00299 0 +OP4 E0029A 0 +OP4 E0029B 0 +OP4 E0029C 0 +OP4 E0029D 0 +OP4 E0029E 0 +OP4 E0029F 0 +OP4 E002A0 0 +OP4 E002A1 0 +OP4 E002A2 0 +OP4 E002A3 0 +OP4 E002A4 0 +OP4 E002A5 0 +OP4 E002A6 0 +OP4 E002A7 0 +OP4 E002A8 0 +OP4 E002A9 0 +OP4 E002AA 0 +OP4 E002AB 0 +OP4 E002AC 0 +OP4 E002AD 0 +OP4 E002AE 0 +OP4 E002AF 0 +OP4 E002B0 0 +OP4 E002B1 0 +OP4 E002B2 0 +OP4 E002B3 0 +OP4 E002B4 0 +OP4 E002B5 0 +OP4 E002B6 0 +OP4 E002B7 0 +OP4 E002B8 0 +OP4 E002B9 0 +OP4 E002BA 0 +OP4 E002BB 0 +OP4 E002BC 0 +OP4 E002BD 0 +OP4 E002BE 0 +OP4 E002BF 0 +OP4 E002C0 0 +OP4 E002C1 0 +OP4 E002C2 0 +OP4 E002C3 0 +OP4 E002C4 0 +OP4 E002C5 0 +OP4 E002C6 0 +OP4 E002C7 0 +OP4 E002C8 0 +OP4 E002C9 0 +OP4 E002CA 0 +OP4 E002CB 0 +OP4 E002CC 0 +OP4 E002CD 0 +OP4 E002CE 0 +OP4 E002CF 0 +OP4 E002D0 0 +OP4 E002D1 0 +OP4 E002D2 0 +OP4 E002D3 0 +OP4 E002D4 0 +OP4 E002D5 0 +OP4 E002D6 0 +OP4 E002D7 0 +OP4 E002D8 0 +OP4 E002D9 0 +OP4 E002DA 0 +OP4 E002DB 0 +OP4 E002DC 0 +OP4 E002DD 0 +OP4 E002DE 0 +OP4 E002DF 0 +OP4 E002E0 0 +OP4 E002E1 0 +OP4 E002E2 0 +OP4 E002E3 0 +OP4 E002E4 0 +OP4 E002E5 0 +OP4 E002E6 0 +OP4 E002E7 0 +OP4 E002E8 0 +OP4 E002E9 0 +OP4 E002EA 0 +OP4 E002EB 0 +OP4 E002EC 0 +OP4 E002ED 0 +OP4 E002EE 0 +OP4 E002EF 0 +OP4 E002F0 0 +OP4 E002F1 0 +OP4 E002F2 0 +OP4 E002F3 0 +OP4 E002F4 0 +OP4 E002F5 0 +OP4 E002F6 0 +OP4 E002F7 0 +OP4 E002F8 0 +OP4 E002F9 0 +OP4 E002FA 0 +OP4 E002FB 0 +OP4 E002FC 0 +OP4 E002FD 0 +OP4 E002FE 0 +OP4 E002FF 0 +OP4 E00300 0 +OP4 E00301 0 +OP4 E00302 0 +OP4 E00303 0 +OP4 E00304 0 +OP4 E00305 0 +OP4 E00306 0 +OP4 E00307 0 +OP4 E00308 0 +OP4 E00309 0 +OP4 E0030A 0 +OP4 E0030B 0 +OP4 E0030C 0 +OP4 E0030D 0 +OP4 E0030E 0 +OP4 E0030F 0 +OP4 E00310 0 +OP4 E00311 0 +OP4 E00312 0 +OP4 E00313 0 +OP4 E00314 0 +OP4 E00315 0 +OP4 E00316 0 +OP4 E00317 0 +OP4 E00318 0 +OP4 E00319 0 +OP4 E0031A 0 +OP4 E0031B 0 +OP4 E0031C 0 +OP4 E0031D 0 +OP4 E0031E 0 +OP4 E0031F 0 +OP4 E00320 0 +OP4 E00321 0 +OP4 E00322 0 +OP4 E00323 0 +OP4 E00324 0 +OP4 E00325 0 +OP4 E00326 0 +OP4 E00327 0 +OP4 E00328 0 +OP4 E00329 0 +OP4 E0032A 0 +OP4 E0032B 0 +OP4 E0032C 0 +OP4 E0032D 0 +OP4 E0032E 0 +OP4 E0032F 0 +OP4 E00330 0 +OP4 E00331 0 +OP4 E00332 0 +OP4 E00333 0 +OP4 E00334 0 +OP4 E00335 0 +OP4 E00336 0 +OP4 E00337 0 +OP4 E00338 0 +OP4 E00339 0 +OP4 E0033A 0 +OP4 E0033B 0 +OP4 E0033C 0 +OP4 E0033D 0 +OP4 E0033E 0 +OP4 E0033F 0 +OP4 E00340 0 +OP4 E00341 0 +OP4 E00342 0 +OP4 E00343 0 +OP4 E00344 0 +OP4 E00345 0 +OP4 E00346 0 +OP4 E00347 0 +OP4 E00348 0 +OP4 E00349 0 +OP4 E0034A 0 +OP4 E0034B 0 +OP4 E0034C 0 +OP4 E0034D 0 +OP4 E0034E 0 +OP4 E0034F 0 +OP4 E00350 0 +OP4 E00351 0 +OP4 E00352 0 +OP4 E00353 0 +OP4 E00354 0 +OP4 E00355 0 +OP4 E00356 0 +OP4 E00357 0 +OP4 E00358 0 +OP4 E00359 0 +OP4 E0035A 0 +OP4 E0035B 0 +OP4 E0035C 0 +OP4 E0035D 0 +OP4 E0035E 0 +OP4 E0035F 0 +OP4 E00360 0 +OP4 E00361 0 +OP4 E00362 0 +OP4 E00363 0 +OP4 E00364 0 +OP4 E00365 0 +OP4 E00366 0 +OP4 E00367 0 +OP4 E00368 0 +OP4 E00369 0 +OP4 E0036A 0 +OP4 E0036B 0 +OP4 E0036C 0 +OP4 E0036D 0 +OP4 E0036E 0 +OP4 E0036F 0 +OP4 E00370 0 +OP4 E00371 0 +OP4 E00372 0 +OP4 E00373 0 +OP4 E00374 0 +OP4 E00375 0 +OP4 E00376 0 +OP4 E00377 0 +OP4 E00378 0 +OP4 E00379 0 +OP4 E0037A 0 +OP4 E0037B 0 +OP4 E0037C 0 +OP4 E0037D 0 +OP4 E0037E 0 +OP4 E0037F 0 +OP4 E00380 0 +OP4 E00381 0 +OP4 E00382 0 +OP4 E00383 0 +OP4 E00384 0 +OP4 E00385 0 +OP4 E00386 0 +OP4 E00387 0 +OP4 E00388 0 +OP4 E00389 0 +OP4 E0038A 0 +OP4 E0038B 0 +OP4 E0038C 0 +OP4 E0038D 0 +OP4 E0038E 0 +OP4 E0038F 0 +OP4 E00390 0 +OP4 E00391 0 +OP4 E00392 0 +OP4 E00393 0 +OP4 E00394 0 +OP4 E00395 0 +OP4 E00396 0 +OP4 E00397 0 +OP4 E00398 0 +OP4 E00399 0 +OP4 E0039A 0 +OP4 E0039B 0 +OP4 E0039C 0 +OP4 E0039D 0 +OP4 E0039E 0 +OP4 E0039F 0 +OP4 E003A0 0 +OP4 E003A1 0 +OP4 E003A2 0 +OP4 E003A3 0 +OP4 E003A4 0 +OP4 E003A5 0 +OP4 E003A6 0 +OP4 E003A7 0 +OP4 E003A8 0 +OP4 E003A9 0 +OP4 E003AA 0 +OP4 E003AB 0 +OP4 E003AC 0 +OP4 E003AD 0 +OP4 E003AE 0 +OP4 E003AF 0 +OP4 E003B0 0 +OP4 E003B1 0 +OP4 E003B2 0 +OP4 E003B3 0 +OP4 E003B4 0 +OP4 E003B5 0 +OP4 E003B6 0 +OP4 E003B7 0 +OP4 E003B8 0 +OP4 E003B9 0 +OP4 E003BA 0 +OP4 E003BB 0 +OP4 E003BC 0 +OP4 E003BD 0 +OP4 E003BE 0 +OP4 E003BF 0 +OP4 E003C0 0 +OP4 E003C1 0 +OP4 E003C2 0 +OP4 E003C3 0 +OP4 E003C4 0 +OP4 E003C5 0 +OP4 E003C6 0 +OP4 E003C7 0 +OP4 E003C8 0 +OP4 E003C9 0 +OP4 E003CA 0 +OP4 E003CB 0 +OP4 E003CC 0 +OP4 E003CD 0 +OP4 E003CE 0 +OP4 E003CF 0 +OP4 E003D0 0 +OP4 E003D1 0 +OP4 E003D2 0 +OP4 E003D3 0 +OP4 E003D4 0 +OP4 E003D5 0 +OP4 E003D6 0 +OP4 E003D7 0 +OP4 E003D8 0 +OP4 E003D9 0 +OP4 E003DA 0 +OP4 E003DB 0 +OP4 E003DC 0 +OP4 E003DD 0 +OP4 E003DE 0 +OP4 E003DF 0 +OP4 E003E0 0 +OP4 E003E1 0 +OP4 E003E2 0 +OP4 E003E3 0 +OP4 E003E4 0 +OP4 E003E5 0 +OP4 E003E6 0 +OP4 E003E7 0 +OP4 E003E8 0 +OP4 E003E9 0 +OP4 E003EA 0 +OP4 E003EB 0 +OP4 E003EC 0 +OP4 E003ED 0 +OP4 E003EE 0 +OP4 E003EF 0 +OP4 E003F0 0 +OP4 E003F1 0 +OP4 E003F2 0 +OP4 E003F3 0 +OP4 E003F4 0 +OP4 E003F5 0 +OP4 E003F6 0 +OP4 E003F7 0 +OP4 E003F8 0 +OP4 E003F9 0 +OP4 E003FA 0 +OP4 E003FB 0 +OP4 E003FC 0 +OP4 E003FD 0 +OP4 E003FE 0 +OP4 E003FF 0 +OP4 E00400 0 +OP4 E00401 0 +OP4 E00402 0 +OP4 E00403 0 +OP4 E00404 0 +OP4 E00405 0 +OP4 E00406 0 +OP4 E00407 0 +OP4 E00408 0 +OP4 E00409 0 +OP4 E0040A 0 +OP4 E0040B 0 +OP4 E0040C 0 +OP4 E0040D 0 +OP4 E0040E 0 +OP4 E0040F 0 +OP4 E00410 0 +OP4 E00411 0 +OP4 E00412 0 +OP4 E00413 0 +OP4 E00414 0 +OP4 E00415 0 +OP4 E00416 0 +OP4 E00417 0 +OP4 E00418 0 +OP4 E00419 0 +OP4 E0041A 0 +OP4 E0041B 0 +OP4 E0041C 0 +OP4 E0041D 0 +OP4 E0041E 0 +OP4 E0041F 0 +OP4 E00420 0 +OP4 E00421 0 +OP4 E00422 0 +OP4 E00423 0 +OP4 E00424 0 +OP4 E00425 0 +OP4 E00426 0 +OP4 E00427 0 +OP4 E00428 0 +OP4 E00429 0 +OP4 E0042A 0 +OP4 E0042B 0 +OP4 E0042C 0 +OP4 E0042D 0 +OP4 E0042E 0 +OP4 E0042F 0 +OP4 E00430 0 +OP4 E00431 0 +OP4 E00432 0 +OP4 E00433 0 +OP4 E00434 0 +OP4 E00435 0 +OP4 E00436 0 +OP4 E00437 0 +OP4 E00438 0 +OP4 E00439 0 +OP4 E0043A 0 +OP4 E0043B 0 +OP4 E0043C 0 +OP4 E0043D 0 +OP4 E0043E 0 +OP4 E0043F 0 +OP4 E00440 0 +OP4 E00441 0 +OP4 E00442 0 +OP4 E00443 0 +OP4 E00444 0 +OP4 E00445 0 +OP4 E00446 0 +OP4 E00447 0 +OP4 E00448 0 +OP4 E00449 0 +OP4 E0044A 0 +OP4 E0044B 0 +OP4 E0044C 0 +OP4 E0044D 0 +OP4 E0044E 0 +OP4 E0044F 0 +OP4 E00450 0 +OP4 E00451 0 +OP4 E00452 0 +OP4 E00453 0 +OP4 E00454 0 +OP4 E00455 0 +OP4 E00456 0 +OP4 E00457 0 +OP4 E00458 0 +OP4 E00459 0 +OP4 E0045A 0 +OP4 E0045B 0 +OP4 E0045C 0 +OP4 E0045D 0 +OP4 E0045E 0 +OP4 E0045F 0 +OP4 E00460 0 +OP4 E00461 0 +OP4 E00462 0 +OP4 E00463 0 +OP4 E00464 0 +OP4 E00465 0 +OP4 E00466 0 +OP4 E00467 0 +OP4 E00468 0 +OP4 E00469 0 +OP4 E0046A 0 +OP4 E0046B 0 +OP4 E0046C 0 +OP4 E0046D 0 +OP4 E0046E 0 +OP4 E0046F 0 +OP4 E00470 0 +OP4 E00471 0 +OP4 E00472 0 +OP4 E00473 0 +OP4 E00474 0 +OP4 E00475 0 +OP4 E00476 0 +OP4 E00477 0 +OP4 E00478 0 +OP4 E00479 0 +OP4 E0047A 0 +OP4 E0047B 0 +OP4 E0047C 0 +OP4 E0047D 0 +OP4 E0047E 0 +OP4 E0047F 0 +OP4 E00480 0 +OP4 E00481 0 +OP4 E00482 0 +OP4 E00483 0 +OP4 E00484 0 +OP4 E00485 0 +OP4 E00486 0 +OP4 E00487 0 +OP4 E00488 0 +OP4 E00489 0 +OP4 E0048A 0 +OP4 E0048B 0 +OP4 E0048C 0 +OP4 E0048D 0 +OP4 E0048E 0 +OP4 E0048F 0 +OP4 E00490 0 +OP4 E00491 0 +OP4 E00492 0 +OP4 E00493 0 +OP4 E00494 0 +OP4 E00495 0 +OP4 E00496 0 +OP4 E00497 0 +OP4 E00498 0 +OP4 E00499 0 +OP4 E0049A 0 +OP4 E0049B 0 +OP4 E0049C 0 +OP4 E0049D 0 +OP4 E0049E 0 +OP4 E0049F 0 +OP4 E004A0 0 +OP4 E004A1 0 +OP4 E004A2 0 +OP4 E004A3 0 +OP4 E004A4 0 +OP4 E004A5 0 +OP4 E004A6 0 +OP4 E004A7 0 +OP4 E004A8 0 +OP4 E004A9 0 +OP4 E004AA 0 +OP4 E004AB 0 +OP4 E004AC 0 +OP4 E004AD 0 +OP4 E004AE 0 +OP4 E004AF 0 +OP4 E004B0 0 +OP4 E004B1 0 +OP4 E004B2 0 +OP4 E004B3 0 +OP4 E004B4 0 +OP4 E004B5 0 +OP4 E004B6 0 +OP4 E004B7 0 +OP4 E004B8 0 +OP4 E004B9 0 +OP4 E004BA 0 +OP4 E004BB 0 +OP4 E004BC 0 +OP4 E004BD 0 +OP4 E004BE 0 +OP4 E004BF 0 +OP4 E004C0 0 +OP4 E004C1 0 +OP4 E004C2 0 +OP4 E004C3 0 +OP4 E004C4 0 +OP4 E004C5 0 +OP4 E004C6 0 +OP4 E004C7 0 +OP4 E004C8 0 +OP4 E004C9 0 +OP4 E004CA 0 +OP4 E004CB 0 +OP4 E004CC 0 +OP4 E004CD 0 +OP4 E004CE 0 +OP4 E004CF 0 +OP4 E004D0 0 +OP4 E004D1 0 +OP4 E004D2 0 +OP4 E004D3 0 +OP4 E004D4 0 +OP4 E004D5 0 +OP4 E004D6 0 +OP4 E004D7 0 +OP4 E004D8 0 +OP4 E004D9 0 +OP4 E004DA 0 +OP4 E004DB 0 +OP4 E004DC 0 +OP4 E004DD 0 +OP4 E004DE 0 +OP4 E004DF 0 +OP4 E004E0 0 +OP4 E004E1 0 +OP4 E004E2 0 +OP4 E004E3 0 +OP4 E004E4 0 +OP4 E004E5 0 +OP4 E004E6 0 +OP4 E004E7 0 +OP4 E004E8 0 +OP4 E004E9 0 +OP4 E004EA 0 +OP4 E004EB 0 +OP4 E004EC 0 +OP4 E004ED 0 +OP4 E004EE 0 +OP4 E004EF 0 +OP4 E004F0 0 +OP4 E004F1 0 +OP4 E004F2 0 +OP4 E004F3 0 +OP4 E004F4 0 +OP4 E004F5 0 +OP4 E004F6 0 +OP4 E004F7 0 +OP4 E004F8 0 +OP4 E004F9 0 +OP4 E004FA 0 +OP4 E004FB 0 +OP4 E004FC 0 +OP4 E004FD 0 +OP4 E004FE 0 +OP4 E004FF 0 +OP4 E00500 0 +OP4 E00501 0 +OP4 E00502 0 +OP4 E00503 0 +OP4 E00504 0 +OP4 E00505 0 +OP4 E00506 0 +OP4 E00507 0 +OP4 E00508 0 +OP4 E00509 0 +OP4 E0050A 0 +OP4 E0050B 0 +OP4 E0050C 0 +OP4 E0050D 0 +OP4 E0050E 0 +OP4 E0050F 0 +OP4 E00510 0 +OP4 E00511 0 +OP4 E00512 0 +OP4 E00513 0 +OP4 E00514 0 +OP4 E00515 0 +OP4 E00516 0 +OP4 E00517 0 +OP4 E00518 0 +OP4 E00519 0 +OP4 E0051A 0 +OP4 E0051B 0 +OP4 E0051C 0 +OP4 E0051D 0 +OP4 E0051E 0 +OP4 E0051F 0 +OP4 E00520 0 +OP4 E00521 0 +OP4 E00522 0 +OP4 E00523 0 +OP4 E00524 0 +OP4 E00525 0 +OP4 E00526 0 +OP4 E00527 0 +OP4 E00528 0 +OP4 E00529 0 +OP4 E0052A 0 +OP4 E0052B 0 +OP4 E0052C 0 +OP4 E0052D 0 +OP4 E0052E 0 +OP4 E0052F 0 +OP4 E00530 0 +OP4 E00531 0 +OP4 E00532 0 +OP4 E00533 0 +OP4 E00534 0 +OP4 E00535 0 +OP4 E00536 0 +OP4 E00537 0 +OP4 E00538 0 +OP4 E00539 0 +OP4 E0053A 0 +OP4 E0053B 0 +OP4 E0053C 0 +OP4 E0053D 0 +OP4 E0053E 0 +OP4 E0053F 0 +OP4 E00540 0 +OP4 E00541 0 +OP4 E00542 0 +OP4 E00543 0 +OP4 E00544 0 +OP4 E00545 0 +OP4 E00546 0 +OP4 E00547 0 +OP4 E00548 0 +OP4 E00549 0 +OP4 E0054A 0 +OP4 E0054B 0 +OP4 E0054C 0 +OP4 E0054D 0 +OP4 E0054E 0 +OP4 E0054F 0 +OP4 E00550 0 +OP4 E00551 0 +OP4 E00552 0 +OP4 E00553 0 +OP4 E00554 0 +OP4 E00555 0 +OP4 E00556 0 +OP4 E00557 0 +OP4 E00558 0 +OP4 E00559 0 +OP4 E0055A 0 +OP4 E0055B 0 +OP4 E0055C 0 +OP4 E0055D 0 +OP4 E0055E 0 +OP4 E0055F 0 +OP4 E00560 0 +OP4 E00561 0 +OP4 E00562 0 +OP4 E00563 0 +OP4 E00564 0 +OP4 E00565 0 +OP4 E00566 0 +OP4 E00567 0 +OP4 E00568 0 +OP4 E00569 0 +OP4 E0056A 0 +OP4 E0056B 0 +OP4 E0056C 0 +OP4 E0056D 0 +OP4 E0056E 0 +OP4 E0056F 0 +OP4 E00570 0 +OP4 E00571 0 +OP4 E00572 0 +OP4 E00573 0 +OP4 E00574 0 +OP4 E00575 0 +OP4 E00576 0 +OP4 E00577 0 +OP4 E00578 0 +OP4 E00579 0 +OP4 E0057A 0 +OP4 E0057B 0 +OP4 E0057C 0 +OP4 E0057D 0 +OP4 E0057E 0 +OP4 E0057F 0 +OP4 E00580 0 +OP4 E00581 0 +OP4 E00582 0 +OP4 E00583 0 +OP4 E00584 0 +OP4 E00585 0 +OP4 E00586 0 +OP4 E00587 0 +OP4 E00588 0 +OP4 E00589 0 +OP4 E0058A 0 +OP4 E0058B 0 +OP4 E0058C 0 +OP4 E0058D 0 +OP4 E0058E 0 +OP4 E0058F 0 +OP4 E00590 0 +OP4 E00591 0 +OP4 E00592 0 +OP4 E00593 0 +OP4 E00594 0 +OP4 E00595 0 +OP4 E00596 0 +OP4 E00597 0 +OP4 E00598 0 +OP4 E00599 0 +OP4 E0059A 0 +OP4 E0059B 0 +OP4 E0059C 0 +OP4 E0059D 0 +OP4 E0059E 0 +OP4 E0059F 0 +OP4 E005A0 0 +OP4 E005A1 0 +OP4 E005A2 0 +OP4 E005A3 0 +OP4 E005A4 0 +OP4 E005A5 0 +OP4 E005A6 0 +OP4 E005A7 0 +OP4 E005A8 0 +OP4 E005A9 0 +OP4 E005AA 0 +OP4 E005AB 0 +OP4 E005AC 0 +OP4 E005AD 0 +OP4 E005AE 0 +OP4 E005AF 0 +OP4 E005B0 0 +OP4 E005B1 0 +OP4 E005B2 0 +OP4 E005B3 0 +OP4 E005B4 0 +OP4 E005B5 0 +OP4 E005B6 0 +OP4 E005B7 0 +OP4 E005B8 0 +OP4 E005B9 0 +OP4 E005BA 0 +OP4 E005BB 0 +OP4 E005BC 0 +OP4 E005BD 0 +OP4 E005BE 0 +OP4 E005BF 0 +OP4 E005C0 0 +OP4 E005C1 0 +OP4 E005C2 0 +OP4 E005C3 0 +OP4 E005C4 0 +OP4 E005C5 0 +OP4 E005C6 0 +OP4 E005C7 0 +OP4 E005C8 0 +OP4 E005C9 0 +OP4 E005CA 0 +OP4 E005CB 0 +OP4 E005CC 0 +OP4 E005CD 0 +OP4 E005CE 0 +OP4 E005CF 0 +OP4 E005D0 0 +OP4 E005D1 0 +OP4 E005D2 0 +OP4 E005D3 0 +OP4 E005D4 0 +OP4 E005D5 0 +OP4 E005D6 0 +OP4 E005D7 0 +OP4 E005D8 0 +OP4 E005D9 0 +OP4 E005DA 0 +OP4 E005DB 0 +OP4 E005DC 0 +OP4 E005DD 0 +OP4 E005DE 0 +OP4 E005DF 0 +OP4 E005E0 0 +OP4 E005E1 0 +OP4 E005E2 0 +OP4 E005E3 0 +OP4 E005E4 0 +OP4 E005E5 0 +OP4 E005E6 0 +OP4 E005E7 0 +OP4 E005E8 0 +OP4 E005E9 0 +OP4 E005EA 0 +OP4 E005EB 0 +OP4 E005EC 0 +OP4 E005ED 0 +OP4 E005EE 0 +OP4 E005EF 0 +OP4 E005F0 0 +OP4 E005F1 0 +OP4 E005F2 0 +OP4 E005F3 0 +OP4 E005F4 0 +OP4 E005F5 0 +OP4 E005F6 0 +OP4 E005F7 0 +OP4 E005F8 0 +OP4 E005F9 0 +OP4 E005FA 0 +OP4 E005FB 0 +OP4 E005FC 0 +OP4 E005FD 0 +OP4 E005FE 0 +OP4 E005FF 0 +OP4 E00600 0 +OP4 E00601 0 +OP4 E00602 0 +OP4 E00603 0 +OP4 E00604 0 +OP4 E00605 0 +OP4 E00606 0 +OP4 E00607 0 +OP4 E00608 0 +OP4 E00609 0 +OP4 E0060A 0 +OP4 E0060B 0 +OP4 E0060C 0 +OP4 E0060D 0 +OP4 E0060E 0 +OP4 E0060F 0 +OP4 E00610 0 +OP4 E00611 0 +OP4 E00612 0 +OP4 E00613 0 +OP4 E00614 0 +OP4 E00615 0 +OP4 E00616 0 +OP4 E00617 0 +OP4 E00618 0 +OP4 E00619 0 +OP4 E0061A 0 +OP4 E0061B 0 +OP4 E0061C 0 +OP4 E0061D 0 +OP4 E0061E 0 +OP4 E0061F 0 +OP4 E00620 0 +OP4 E00621 0 +OP4 E00622 0 +OP4 E00623 0 +OP4 E00624 0 +OP4 E00625 0 +OP4 E00626 0 +OP4 E00627 0 +OP4 E00628 0 +OP4 E00629 0 +OP4 E0062A 0 +OP4 E0062B 0 +OP4 E0062C 0 +OP4 E0062D 0 +OP4 E0062E 0 +OP4 E0062F 0 +OP4 E00630 0 +OP4 E00631 0 +OP4 E00632 0 +OP4 E00633 0 +OP4 E00634 0 +OP4 E00635 0 +OP4 E00636 0 +OP4 E00637 0 +OP4 E00638 0 +OP4 E00639 0 +OP4 E0063A 0 +OP4 E0063B 0 +OP4 E0063C 0 +OP4 E0063D 0 +OP4 E0063E 0 +OP4 E0063F 0 +OP4 E00640 0 +OP4 E00641 0 +OP4 E00642 0 +OP4 E00643 0 +OP4 E00644 0 +OP4 E00645 0 +OP4 E00646 0 +OP4 E00647 0 +OP4 E00648 0 +OP4 E00649 0 +OP4 E0064A 0 +OP4 E0064B 0 +OP4 E0064C 0 +OP4 E0064D 0 +OP4 E0064E 0 +OP4 E0064F 0 +OP4 E00650 0 +OP4 E00651 0 +OP4 E00652 0 +OP4 E00653 0 +OP4 E00654 0 +OP4 E00655 0 +OP4 E00656 0 +OP4 E00657 0 +OP4 E00658 0 +OP4 E00659 0 +OP4 E0065A 0 +OP4 E0065B 0 +OP4 E0065C 0 +OP4 E0065D 0 +OP4 E0065E 0 +OP4 E0065F 0 +OP4 E00660 0 +OP4 E00661 0 +OP4 E00662 0 +OP4 E00663 0 +OP4 E00664 0 +OP4 E00665 0 +OP4 E00666 0 +OP4 E00667 0 +OP4 E00668 0 +OP4 E00669 0 +OP4 E0066A 0 +OP4 E0066B 0 +OP4 E0066C 0 +OP4 E0066D 0 +OP4 E0066E 0 +OP4 E0066F 0 +OP4 E00670 0 +OP4 E00671 0 +OP4 E00672 0 +OP4 E00673 0 +OP4 E00674 0 +OP4 E00675 0 +OP4 E00676 0 +OP4 E00677 0 +OP4 E00678 0 +OP4 E00679 0 +OP4 E0067A 0 +OP4 E0067B 0 +OP4 E0067C 0 +OP4 E0067D 0 +OP4 E0067E 0 +OP4 E0067F 0 +OP4 E00680 0 +OP4 E00681 0 +OP4 E00682 0 +OP4 E00683 0 +OP4 E00684 0 +OP4 E00685 0 +OP4 E00686 0 +OP4 E00687 0 +OP4 E00688 0 +OP4 E00689 0 +OP4 E0068A 0 +OP4 E0068B 0 +OP4 E0068C 0 +OP4 E0068D 0 +OP4 E0068E 0 +OP4 E0068F 0 +OP4 E00690 0 +OP4 E00691 0 +OP4 E00692 0 +OP4 E00693 0 +OP4 E00694 0 +OP4 E00695 0 +OP4 E00696 0 +OP4 E00697 0 +OP4 E00698 0 +OP4 E00699 0 +OP4 E0069A 0 +OP4 E0069B 0 +OP4 E0069C 0 +OP4 E0069D 0 +OP4 E0069E 0 +OP4 E0069F 0 +OP4 E006A0 0 +OP4 E006A1 0 +OP4 E006A2 0 +OP4 E006A3 0 +OP4 E006A4 0 +OP4 E006A5 0 +OP4 E006A6 0 +OP4 E006A7 0 +OP4 E006A8 0 +OP4 E006A9 0 +OP4 E006AA 0 +OP4 E006AB 0 +OP4 E006AC 0 +OP4 E006AD 0 +OP4 E006AE 0 +OP4 E006AF 0 +OP4 E006B0 0 +OP4 E006B1 0 +OP4 E006B2 0 +OP4 E006B3 0 +OP4 E006B4 0 +OP4 E006B5 0 +OP4 E006B6 0 +OP4 E006B7 0 +OP4 E006B8 0 +OP4 E006B9 0 +OP4 E006BA 0 +OP4 E006BB 0 +OP4 E006BC 0 +OP4 E006BD 0 +OP4 E006BE 0 +OP4 E006BF 0 +OP4 E006C0 0 +OP4 E006C1 0 +OP4 E006C2 0 +OP4 E006C3 0 +OP4 E006C4 0 +OP4 E006C5 0 +OP4 E006C6 0 +OP4 E006C7 0 +OP4 E006C8 0 +OP4 E006C9 0 +OP4 E006CA 0 +OP4 E006CB 0 +OP4 E006CC 0 +OP4 E006CD 0 +OP4 E006CE 0 +OP4 E006CF 0 +OP4 E006D0 0 +OP4 E006D1 0 +OP4 E006D2 0 +OP4 E006D3 0 +OP4 E006D4 0 +OP4 E006D5 0 +OP4 E006D6 0 +OP4 E006D7 0 +OP4 E006D8 0 +OP4 E006D9 0 +OP4 E006DA 0 +OP4 E006DB 0 +OP4 E006DC 0 +OP4 E006DD 0 +OP4 E006DE 0 +OP4 E006DF 0 +OP4 E006E0 0 +OP4 E006E1 0 +OP4 E006E2 0 +OP4 E006E3 0 +OP4 E006E4 0 +OP4 E006E5 0 +OP4 E006E6 0 +OP4 E006E7 0 +OP4 E006E8 0 +OP4 E006E9 0 +OP4 E006EA 0 +OP4 E006EB 0 +OP4 E006EC 0 +OP4 E006ED 0 +OP4 E006EE 0 +OP4 E006EF 0 +OP4 E006F0 0 +OP4 E006F1 0 +OP4 E006F2 0 +OP4 E006F3 0 +OP4 E006F4 0 +OP4 E006F5 0 +OP4 E006F6 0 +OP4 E006F7 0 +OP4 E006F8 0 +OP4 E006F9 0 +OP4 E006FA 0 +OP4 E006FB 0 +OP4 E006FC 0 +OP4 E006FD 0 +OP4 E006FE 0 +OP4 E006FF 0 +OP4 E00700 0 +OP4 E00701 0 +OP4 E00702 0 +OP4 E00703 0 +OP4 E00704 0 +OP4 E00705 0 +OP4 E00706 0 +OP4 E00707 0 +OP4 E00708 0 +OP4 E00709 0 +OP4 E0070A 0 +OP4 E0070B 0 +OP4 E0070C 0 +OP4 E0070D 0 +OP4 E0070E 0 +OP4 E0070F 0 +OP4 E00710 0 +OP4 E00711 0 +OP4 E00712 0 +OP4 E00713 0 +OP4 E00714 0 +OP4 E00715 0 +OP4 E00716 0 +OP4 E00717 0 +OP4 E00718 0 +OP4 E00719 0 +OP4 E0071A 0 +OP4 E0071B 0 +OP4 E0071C 0 +OP4 E0071D 0 +OP4 E0071E 0 +OP4 E0071F 0 +OP4 E00720 0 +OP4 E00721 0 +OP4 E00722 0 +OP4 E00723 0 +OP4 E00724 0 +OP4 E00725 0 +OP4 E00726 0 +OP4 E00727 0 +OP4 E00728 0 +OP4 E00729 0 +OP4 E0072A 0 +OP4 E0072B 0 +OP4 E0072C 0 +OP4 E0072D 0 +OP4 E0072E 0 +OP4 E0072F 0 +OP4 E00730 0 +OP4 E00731 0 +OP4 E00732 0 +OP4 E00733 0 +OP4 E00734 0 +OP4 E00735 0 +OP4 E00736 0 +OP4 E00737 0 +OP4 E00738 0 +OP4 E00739 0 +OP4 E0073A 0 +OP4 E0073B 0 +OP4 E0073C 0 +OP4 E0073D 0 +OP4 E0073E 0 +OP4 E0073F 0 +OP4 E00740 0 +OP4 E00741 0 +OP4 E00742 0 +OP4 E00743 0 +OP4 E00744 0 +OP4 E00745 0 +OP4 E00746 0 +OP4 E00747 0 +OP4 E00748 0 +OP4 E00749 0 +OP4 E0074A 0 +OP4 E0074B 0 +OP4 E0074C 0 +OP4 E0074D 0 +OP4 E0074E 0 +OP4 E0074F 0 +OP4 E00750 0 +OP4 E00751 0 +OP4 E00752 0 +OP4 E00753 0 +OP4 E00754 0 +OP4 E00755 0 +OP4 E00756 0 +OP4 E00757 0 +OP4 E00758 0 +OP4 E00759 0 +OP4 E0075A 0 +OP4 E0075B 0 +OP4 E0075C 0 +OP4 E0075D 0 +OP4 E0075E 0 +OP4 E0075F 0 +OP4 E00760 0 +OP4 E00761 0 +OP4 E00762 0 +OP4 E00763 0 +OP4 E00764 0 +OP4 E00765 0 +OP4 E00766 0 +OP4 E00767 0 +OP4 E00768 0 +OP4 E00769 0 +OP4 E0076A 0 +OP4 E0076B 0 +OP4 E0076C 0 +OP4 E0076D 0 +OP4 E0076E 0 +OP4 E0076F 0 +OP4 E00770 0 +OP4 E00771 0 +OP4 E00772 0 +OP4 E00773 0 +OP4 E00774 0 +OP4 E00775 0 +OP4 E00776 0 +OP4 E00777 0 +OP4 E00778 0 +OP4 E00779 0 +OP4 E0077A 0 +OP4 E0077B 0 +OP4 E0077C 0 +OP4 E0077D 0 +OP4 E0077E 0 +OP4 E0077F 0 +OP4 E00780 0 +OP4 E00781 0 +OP4 E00782 0 +OP4 E00783 0 +OP4 E00784 0 +OP4 E00785 0 +OP4 E00786 0 +OP4 E00787 0 +OP4 E00788 0 +OP4 E00789 0 +OP4 E0078A 0 +OP4 E0078B 0 +OP4 E0078C 0 +OP4 E0078D 0 +OP4 E0078E 0 +OP4 E0078F 0 +OP4 E00790 0 +OP4 E00791 0 +OP4 E00792 0 +OP4 E00793 0 +OP4 E00794 0 +OP4 E00795 0 +OP4 E00796 0 +OP4 E00797 0 +OP4 E00798 0 +OP4 E00799 0 +OP4 E0079A 0 +OP4 E0079B 0 +OP4 E0079C 0 +OP4 E0079D 0 +OP4 E0079E 0 +OP4 E0079F 0 +OP4 E007A0 0 +OP4 E007A1 0 +OP4 E007A2 0 +OP4 E007A3 0 +OP4 E007A4 0 +OP4 E007A5 0 +OP4 E007A6 0 +OP4 E007A7 0 +OP4 E007A8 0 +OP4 E007A9 0 +OP4 E007AA 0 +OP4 E007AB 0 +OP4 E007AC 0 +OP4 E007AD 0 +OP4 E007AE 0 +OP4 E007AF 0 +OP4 E007B0 0 +OP4 E007B1 0 +OP4 E007B2 0 +OP4 E007B3 0 +OP4 E007B4 0 +OP4 E007B5 0 +OP4 E007B6 0 +OP4 E007B7 0 +OP4 E007B8 0 +OP4 E007B9 0 +OP4 E007BA 0 +OP4 E007BB 0 +OP4 E007BC 0 +OP4 E007BD 0 +OP4 E007BE 0 +OP4 E007BF 0 +OP4 E007C0 0 +OP4 E007C1 0 +OP4 E007C2 0 +OP4 E007C3 0 +OP4 E007C4 0 +OP4 E007C5 0 +OP4 E007C6 0 +OP4 E007C7 0 +OP4 E007C8 0 +OP4 E007C9 0 +OP4 E007CA 0 +OP4 E007CB 0 +OP4 E007CC 0 +OP4 E007CD 0 +OP4 E007CE 0 +OP4 E007CF 0 +OP4 E007D0 0 +OP4 E007D1 0 +OP4 E007D2 0 +OP4 E007D3 0 +OP4 E007D4 0 +OP4 E007D5 0 +OP4 E007D6 0 +OP4 E007D7 0 +OP4 E007D8 0 +OP4 E007D9 0 +OP4 E007DA 0 +OP4 E007DB 0 +OP4 E007DC 0 +OP4 E007DD 0 +OP4 E007DE 0 +OP4 E007DF 0 +OP4 E007E0 0 +OP4 E007E1 0 +OP4 E007E2 0 +OP4 E007E3 0 +OP4 E007E4 0 +OP4 E007E5 0 +OP4 E007E6 0 +OP4 E007E7 0 +OP4 E007E8 0 +OP4 E007E9 0 +OP4 E007EA 0 +OP4 E007EB 0 +OP4 E007EC 0 +OP4 E007ED 0 +OP4 E007EE 0 +OP4 E007EF 0 +OP4 E007F0 0 +OP4 E007F1 0 +OP4 E007F2 0 +OP4 E007F3 0 +OP4 E007F4 0 +OP4 E007F5 0 +OP4 E007F6 0 +OP4 E007F7 0 +OP4 E007F8 0 +OP4 E007F9 0 +OP4 E007FA 0 +OP4 E007FB 0 +OP4 E007FC 0 +OP4 E007FD 0 +OP4 E007FE 0 +OP4 E007FF 0 +OP4 E00800 0 +OP4 E00801 0 +OP4 E00802 0 +OP4 E00803 0 +OP4 E00804 0 +OP4 E00805 0 +OP4 E00806 0 +OP4 E00807 0 +OP4 E00808 0 +OP4 E00809 0 +OP4 E0080A 0 +OP4 E0080B 0 +OP4 E0080C 0 +OP4 E0080D 0 +OP4 E0080E 0 +OP4 E0080F 0 +OP4 E00810 0 +OP4 E00811 0 +OP4 E00812 0 +OP4 E00813 0 +OP4 E00814 0 +OP4 E00815 0 +OP4 E00816 0 +OP4 E00817 0 +OP4 E00818 0 +OP4 E00819 0 +OP4 E0081A 0 +OP4 E0081B 0 +OP4 E0081C 0 +OP4 E0081D 0 +OP4 E0081E 0 +OP4 E0081F 0 +OP4 E00820 0 +OP4 E00821 0 +OP4 E00822 0 +OP4 E00823 0 +OP4 E00824 0 +OP4 E00825 0 +OP4 E00826 0 +OP4 E00827 0 +OP4 E00828 0 +OP4 E00829 0 +OP4 E0082A 0 +OP4 E0082B 0 +OP4 E0082C 0 +OP4 E0082D 0 +OP4 E0082E 0 +OP4 E0082F 0 +OP4 E00830 0 +OP4 E00831 0 +OP4 E00832 0 +OP4 E00833 0 +OP4 E00834 0 +OP4 E00835 0 +OP4 E00836 0 +OP4 E00837 0 +OP4 E00838 0 +OP4 E00839 0 +OP4 E0083A 0 +OP4 E0083B 0 +OP4 E0083C 0 +OP4 E0083D 0 +OP4 E0083E 0 +OP4 E0083F 0 +OP4 E00840 0 +OP4 E00841 0 +OP4 E00842 0 +OP4 E00843 0 +OP4 E00844 0 +OP4 E00845 0 +OP4 E00846 0 +OP4 E00847 0 +OP4 E00848 0 +OP4 E00849 0 +OP4 E0084A 0 +OP4 E0084B 0 +OP4 E0084C 0 +OP4 E0084D 0 +OP4 E0084E 0 +OP4 E0084F 0 +OP4 E00850 0 +OP4 E00851 0 +OP4 E00852 0 +OP4 E00853 0 +OP4 E00854 0 +OP4 E00855 0 +OP4 E00856 0 +OP4 E00857 0 +OP4 E00858 0 +OP4 E00859 0 +OP4 E0085A 0 +OP4 E0085B 0 +OP4 E0085C 0 +OP4 E0085D 0 +OP4 E0085E 0 +OP4 E0085F 0 +OP4 E00860 0 +OP4 E00861 0 +OP4 E00862 0 +OP4 E00863 0 +OP4 E00864 0 +OP4 E00865 0 +OP4 E00866 0 +OP4 E00867 0 +OP4 E00868 0 +OP4 E00869 0 +OP4 E0086A 0 +OP4 E0086B 0 +OP4 E0086C 0 +OP4 E0086D 0 +OP4 E0086E 0 +OP4 E0086F 0 +OP4 E00870 0 +OP4 E00871 0 +OP4 E00872 0 +OP4 E00873 0 +OP4 E00874 0 +OP4 E00875 0 +OP4 E00876 0 +OP4 E00877 0 +OP4 E00878 0 +OP4 E00879 0 +OP4 E0087A 0 +OP4 E0087B 0 +OP4 E0087C 0 +OP4 E0087D 0 +OP4 E0087E 0 +OP4 E0087F 0 +OP4 E00880 0 +OP4 E00881 0 +OP4 E00882 0 +OP4 E00883 0 +OP4 E00884 0 +OP4 E00885 0 +OP4 E00886 0 +OP4 E00887 0 +OP4 E00888 0 +OP4 E00889 0 +OP4 E0088A 0 +OP4 E0088B 0 +OP4 E0088C 0 +OP4 E0088D 0 +OP4 E0088E 0 +OP4 E0088F 0 +OP4 E00890 0 +OP4 E00891 0 +OP4 E00892 0 +OP4 E00893 0 +OP4 E00894 0 +OP4 E00895 0 +OP4 E00896 0 +OP4 E00897 0 +OP4 E00898 0 +OP4 E00899 0 +OP4 E0089A 0 +OP4 E0089B 0 +OP4 E0089C 0 +OP4 E0089D 0 +OP4 E0089E 0 +OP4 E0089F 0 +OP4 E008A0 0 +OP4 E008A1 0 +OP4 E008A2 0 +OP4 E008A3 0 +OP4 E008A4 0 +OP4 E008A5 0 +OP4 E008A6 0 +OP4 E008A7 0 +OP4 E008A8 0 +OP4 E008A9 0 +OP4 E008AA 0 +OP4 E008AB 0 +OP4 E008AC 0 +OP4 E008AD 0 +OP4 E008AE 0 +OP4 E008AF 0 +OP4 E008B0 0 +OP4 E008B1 0 +OP4 E008B2 0 +OP4 E008B3 0 +OP4 E008B4 0 +OP4 E008B5 0 +OP4 E008B6 0 +OP4 E008B7 0 +OP4 E008B8 0 +OP4 E008B9 0 +OP4 E008BA 0 +OP4 E008BB 0 +OP4 E008BC 0 +OP4 E008BD 0 +OP4 E008BE 0 +OP4 E008BF 0 +OP4 E008C0 0 +OP4 E008C1 0 +OP4 E008C2 0 +OP4 E008C3 0 +OP4 E008C4 0 +OP4 E008C5 0 +OP4 E008C6 0 +OP4 E008C7 0 +OP4 E008C8 0 +OP4 E008C9 0 +OP4 E008CA 0 +OP4 E008CB 0 +OP4 E008CC 0 +OP4 E008CD 0 +OP4 E008CE 0 +OP4 E008CF 0 +OP4 E008D0 0 +OP4 E008D1 0 +OP4 E008D2 0 +OP4 E008D3 0 +OP4 E008D4 0 +OP4 E008D5 0 +OP4 E008D6 0 +OP4 E008D7 0 +OP4 E008D8 0 +OP4 E008D9 0 +OP4 E008DA 0 +OP4 E008DB 0 +OP4 E008DC 0 +OP4 E008DD 0 +OP4 E008DE 0 +OP4 E008DF 0 +OP4 E008E0 0 +OP4 E008E1 0 +OP4 E008E2 0 +OP4 E008E3 0 +OP4 E008E4 0 +OP4 E008E5 0 +OP4 E008E6 0 +OP4 E008E7 0 +OP4 E008E8 0 +OP4 E008E9 0 +OP4 E008EA 0 +OP4 E008EB 0 +OP4 E008EC 0 +OP4 E008ED 0 +OP4 E008EE 0 +OP4 E008EF 0 +OP4 E008F0 0 +OP4 E008F1 0 +OP4 E008F2 0 +OP4 E008F3 0 +OP4 E008F4 0 +OP4 E008F5 0 +OP4 E008F6 0 +OP4 E008F7 0 +OP4 E008F8 0 +OP4 E008F9 0 +OP4 E008FA 0 +OP4 E008FB 0 +OP4 E008FC 0 +OP4 E008FD 0 +OP4 E008FE 0 +OP4 E008FF 0 +OP4 E00900 0 +OP4 E00901 0 +OP4 E00902 0 +OP4 E00903 0 +OP4 E00904 0 +OP4 E00905 0 +OP4 E00906 0 +OP4 E00907 0 +OP4 E00908 0 +OP4 E00909 0 +OP4 E0090A 0 +OP4 E0090B 0 +OP4 E0090C 0 +OP4 E0090D 0 +OP4 E0090E 0 +OP4 E0090F 0 +OP4 E00910 0 +OP4 E00911 0 +OP4 E00912 0 +OP4 E00913 0 +OP4 E00914 0 +OP4 E00915 0 +OP4 E00916 0 +OP4 E00917 0 +OP4 E00918 0 +OP4 E00919 0 +OP4 E0091A 0 +OP4 E0091B 0 +OP4 E0091C 0 +OP4 E0091D 0 +OP4 E0091E 0 +OP4 E0091F 0 +OP4 E00920 0 +OP4 E00921 0 +OP4 E00922 0 +OP4 E00923 0 +OP4 E00924 0 +OP4 E00925 0 +OP4 E00926 0 +OP4 E00927 0 +OP4 E00928 0 +OP4 E00929 0 +OP4 E0092A 0 +OP4 E0092B 0 +OP4 E0092C 0 +OP4 E0092D 0 +OP4 E0092E 0 +OP4 E0092F 0 +OP4 E00930 0 +OP4 E00931 0 +OP4 E00932 0 +OP4 E00933 0 +OP4 E00934 0 +OP4 E00935 0 +OP4 E00936 0 +OP4 E00937 0 +OP4 E00938 0 +OP4 E00939 0 +OP4 E0093A 0 +OP4 E0093B 0 +OP4 E0093C 0 +OP4 E0093D 0 +OP4 E0093E 0 +OP4 E0093F 0 +OP4 E00940 0 +OP4 E00941 0 +OP4 E00942 0 +OP4 E00943 0 +OP4 E00944 0 +OP4 E00945 0 +OP4 E00946 0 +OP4 E00947 0 +OP4 E00948 0 +OP4 E00949 0 +OP4 E0094A 0 +OP4 E0094B 0 +OP4 E0094C 0 +OP4 E0094D 0 +OP4 E0094E 0 +OP4 E0094F 0 +OP4 E00950 0 +OP4 E00951 0 +OP4 E00952 0 +OP4 E00953 0 +OP4 E00954 0 +OP4 E00955 0 +OP4 E00956 0 +OP4 E00957 0 +OP4 E00958 0 +OP4 E00959 0 +OP4 E0095A 0 +OP4 E0095B 0 +OP4 E0095C 0 +OP4 E0095D 0 +OP4 E0095E 0 +OP4 E0095F 0 +OP4 E00960 0 +OP4 E00961 0 +OP4 E00962 0 +OP4 E00963 0 +OP4 E00964 0 +OP4 E00965 0 +OP4 E00966 0 +OP4 E00967 0 +OP4 E00968 0 +OP4 E00969 0 +OP4 E0096A 0 +OP4 E0096B 0 +OP4 E0096C 0 +OP4 E0096D 0 +OP4 E0096E 0 +OP4 E0096F 0 +OP4 E00970 0 +OP4 E00971 0 +OP4 E00972 0 +OP4 E00973 0 +OP4 E00974 0 +OP4 E00975 0 +OP4 E00976 0 +OP4 E00977 0 +OP4 E00978 0 +OP4 E00979 0 +OP4 E0097A 0 +OP4 E0097B 0 +OP4 E0097C 0 +OP4 E0097D 0 +OP4 E0097E 0 +OP4 E0097F 0 +OP4 E00980 0 +OP4 E00981 0 +OP4 E00982 0 +OP4 E00983 0 +OP4 E00984 0 +OP4 E00985 0 +OP4 E00986 0 +OP4 E00987 0 +OP4 E00988 0 +OP4 E00989 0 +OP4 E0098A 0 +OP4 E0098B 0 +OP4 E0098C 0 +OP4 E0098D 0 +OP4 E0098E 0 +OP4 E0098F 0 +OP4 E00990 0 +OP4 E00991 0 +OP4 E00992 0 +OP4 E00993 0 +OP4 E00994 0 +OP4 E00995 0 +OP4 E00996 0 +OP4 E00997 0 +OP4 E00998 0 +OP4 E00999 0 +OP4 E0099A 0 +OP4 E0099B 0 +OP4 E0099C 0 +OP4 E0099D 0 +OP4 E0099E 0 +OP4 E0099F 0 +OP4 E009A0 0 +OP4 E009A1 0 +OP4 E009A2 0 +OP4 E009A3 0 +OP4 E009A4 0 +OP4 E009A5 0 +OP4 E009A6 0 +OP4 E009A7 0 +OP4 E009A8 0 +OP4 E009A9 0 +OP4 E009AA 0 +OP4 E009AB 0 +OP4 E009AC 0 +OP4 E009AD 0 +OP4 E009AE 0 +OP4 E009AF 0 +OP4 E009B0 0 +OP4 E009B1 0 +OP4 E009B2 0 +OP4 E009B3 0 +OP4 E009B4 0 +OP4 E009B5 0 +OP4 E009B6 0 +OP4 E009B7 0 +OP4 E009B8 0 +OP4 E009B9 0 +OP4 E009BA 0 +OP4 E009BB 0 +OP4 E009BC 0 +OP4 E009BD 0 +OP4 E009BE 0 +OP4 E009BF 0 +OP4 E009C0 0 +OP4 E009C1 0 +OP4 E009C2 0 +OP4 E009C3 0 +OP4 E009C4 0 +OP4 E009C5 0 +OP4 E009C6 0 +OP4 E009C7 0 +OP4 E009C8 0 +OP4 E009C9 0 +OP4 E009CA 0 +OP4 E009CB 0 +OP4 E009CC 0 +OP4 E009CD 0 +OP4 E009CE 0 +OP4 E009CF 0 +OP4 E009D0 0 +OP4 E009D1 0 +OP4 E009D2 0 +OP4 E009D3 0 +OP4 E009D4 0 +OP4 E009D5 0 +OP4 E009D6 0 +OP4 E009D7 0 +OP4 E009D8 0 +OP4 E009D9 0 +OP4 E009DA 0 +OP4 E009DB 0 +OP4 E009DC 0 +OP4 E009DD 0 +OP4 E009DE 0 +OP4 E009DF 0 +OP4 E009E0 0 +OP4 E009E1 0 +OP4 E009E2 0 +OP4 E009E3 0 +OP4 E009E4 0 +OP4 E009E5 0 +OP4 E009E6 0 +OP4 E009E7 0 +OP4 E009E8 0 +OP4 E009E9 0 +OP4 E009EA 0 +OP4 E009EB 0 +OP4 E009EC 0 +OP4 E009ED 0 +OP4 E009EE 0 +OP4 E009EF 0 +OP4 E009F0 0 +OP4 E009F1 0 +OP4 E009F2 0 +OP4 E009F3 0 +OP4 E009F4 0 +OP4 E009F5 0 +OP4 E009F6 0 +OP4 E009F7 0 +OP4 E009F8 0 +OP4 E009F9 0 +OP4 E009FA 0 +OP4 E009FB 0 +OP4 E009FC 0 +OP4 E009FD 0 +OP4 E009FE 0 +OP4 E009FF 0 +OP4 E00A00 0 +OP4 E00A01 0 +OP4 E00A02 0 +OP4 E00A03 0 +OP4 E00A04 0 +OP4 E00A05 0 +OP4 E00A06 0 +OP4 E00A07 0 +OP4 E00A08 0 +OP4 E00A09 0 +OP4 E00A0A 0 +OP4 E00A0B 0 +OP4 E00A0C 0 +OP4 E00A0D 0 +OP4 E00A0E 0 +OP4 E00A0F 0 +OP4 E00A10 0 +OP4 E00A11 0 +OP4 E00A12 0 +OP4 E00A13 0 +OP4 E00A14 0 +OP4 E00A15 0 +OP4 E00A16 0 +OP4 E00A17 0 +OP4 E00A18 0 +OP4 E00A19 0 +OP4 E00A1A 0 +OP4 E00A1B 0 +OP4 E00A1C 0 +OP4 E00A1D 0 +OP4 E00A1E 0 +OP4 E00A1F 0 +OP4 E00A20 0 +OP4 E00A21 0 +OP4 E00A22 0 +OP4 E00A23 0 +OP4 E00A24 0 +OP4 E00A25 0 +OP4 E00A26 0 +OP4 E00A27 0 +OP4 E00A28 0 +OP4 E00A29 0 +OP4 E00A2A 0 +OP4 E00A2B 0 +OP4 E00A2C 0 +OP4 E00A2D 0 +OP4 E00A2E 0 +OP4 E00A2F 0 +OP4 E00A30 0 +OP4 E00A31 0 +OP4 E00A32 0 +OP4 E00A33 0 +OP4 E00A34 0 +OP4 E00A35 0 +OP4 E00A36 0 +OP4 E00A37 0 +OP4 E00A38 0 +OP4 E00A39 0 +OP4 E00A3A 0 +OP4 E00A3B 0 +OP4 E00A3C 0 +OP4 E00A3D 0 +OP4 E00A3E 0 +OP4 E00A3F 0 +OP4 E00A40 0 +OP4 E00A41 0 +OP4 E00A42 0 +OP4 E00A43 0 +OP4 E00A44 0 +OP4 E00A45 0 +OP4 E00A46 0 +OP4 E00A47 0 +OP4 E00A48 0 +OP4 E00A49 0 +OP4 E00A4A 0 +OP4 E00A4B 0 +OP4 E00A4C 0 +OP4 E00A4D 0 +OP4 E00A4E 0 +OP4 E00A4F 0 +OP4 E00A50 0 +OP4 E00A51 0 +OP4 E00A52 0 +OP4 E00A53 0 +OP4 E00A54 0 +OP4 E00A55 0 +OP4 E00A56 0 +OP4 E00A57 0 +OP4 E00A58 0 +OP4 E00A59 0 +OP4 E00A5A 0 +OP4 E00A5B 0 +OP4 E00A5C 0 +OP4 E00A5D 0 +OP4 E00A5E 0 +OP4 E00A5F 0 +OP4 E00A60 0 +OP4 E00A61 0 +OP4 E00A62 0 +OP4 E00A63 0 +OP4 E00A64 0 +OP4 E00A65 0 +OP4 E00A66 0 +OP4 E00A67 0 +OP4 E00A68 0 +OP4 E00A69 0 +OP4 E00A6A 0 +OP4 E00A6B 0 +OP4 E00A6C 0 +OP4 E00A6D 0 +OP4 E00A6E 0 +OP4 E00A6F 0 +OP4 E00A70 0 +OP4 E00A71 0 +OP4 E00A72 0 +OP4 E00A73 0 +OP4 E00A74 0 +OP4 E00A75 0 +OP4 E00A76 0 +OP4 E00A77 0 +OP4 E00A78 0 +OP4 E00A79 0 +OP4 E00A7A 0 +OP4 E00A7B 0 +OP4 E00A7C 0 +OP4 E00A7D 0 +OP4 E00A7E 0 +OP4 E00A7F 0 +OP4 E00A80 0 +OP4 E00A81 0 +OP4 E00A82 0 +OP4 E00A83 0 +OP4 E00A84 0 +OP4 E00A85 0 +OP4 E00A86 0 +OP4 E00A87 0 +OP4 E00A88 0 +OP4 E00A89 0 +OP4 E00A8A 0 +OP4 E00A8B 0 +OP4 E00A8C 0 +OP4 E00A8D 0 +OP4 E00A8E 0 +OP4 E00A8F 0 +OP4 E00A90 0 +OP4 E00A91 0 +OP4 E00A92 0 +OP4 E00A93 0 +OP4 E00A94 0 +OP4 E00A95 0 +OP4 E00A96 0 +OP4 E00A97 0 +OP4 E00A98 0 +OP4 E00A99 0 +OP4 E00A9A 0 +OP4 E00A9B 0 +OP4 E00A9C 0 +OP4 E00A9D 0 +OP4 E00A9E 0 +OP4 E00A9F 0 +OP4 E00AA0 0 +OP4 E00AA1 0 +OP4 E00AA2 0 +OP4 E00AA3 0 +OP4 E00AA4 0 +OP4 E00AA5 0 +OP4 E00AA6 0 +OP4 E00AA7 0 +OP4 E00AA8 0 +OP4 E00AA9 0 +OP4 E00AAA 0 +OP4 E00AAB 0 +OP4 E00AAC 0 +OP4 E00AAD 0 +OP4 E00AAE 0 +OP4 E00AAF 0 +OP4 E00AB0 0 +OP4 E00AB1 0 +OP4 E00AB2 0 +OP4 E00AB3 0 +OP4 E00AB4 0 +OP4 E00AB5 0 +OP4 E00AB6 0 +OP4 E00AB7 0 +OP4 E00AB8 0 +OP4 E00AB9 0 +OP4 E00ABA 0 +OP4 E00ABB 0 +OP4 E00ABC 0 +OP4 E00ABD 0 +OP4 E00ABE 0 +OP4 E00ABF 0 +OP4 E00AC0 0 +OP4 E00AC1 0 +OP4 E00AC2 0 +OP4 E00AC3 0 +OP4 E00AC4 0 +OP4 E00AC5 0 +OP4 E00AC6 0 +OP4 E00AC7 0 +OP4 E00AC8 0 +OP4 E00AC9 0 +OP4 E00ACA 0 +OP4 E00ACB 0 +OP4 E00ACC 0 +OP4 E00ACD 0 +OP4 E00ACE 0 +OP4 E00ACF 0 +OP4 E00AD0 0 +OP4 E00AD1 0 +OP4 E00AD2 0 +OP4 E00AD3 0 +OP4 E00AD4 0 +OP4 E00AD5 0 +OP4 E00AD6 0 +OP4 E00AD7 0 +OP4 E00AD8 0 +OP4 E00AD9 0 +OP4 E00ADA 0 +OP4 E00ADB 0 +OP4 E00ADC 0 +OP4 E00ADD 0 +OP4 E00ADE 0 +OP4 E00ADF 0 +OP4 E00AE0 0 +OP4 E00AE1 0 +OP4 E00AE2 0 +OP4 E00AE3 0 +OP4 E00AE4 0 +OP4 E00AE5 0 +OP4 E00AE6 0 +OP4 E00AE7 0 +OP4 E00AE8 0 +OP4 E00AE9 0 +OP4 E00AEA 0 +OP4 E00AEB 0 +OP4 E00AEC 0 +OP4 E00AED 0 +OP4 E00AEE 0 +OP4 E00AEF 0 +OP4 E00AF0 0 +OP4 E00AF1 0 +OP4 E00AF2 0 +OP4 E00AF3 0 +OP4 E00AF4 0 +OP4 E00AF5 0 +OP4 E00AF6 0 +OP4 E00AF7 0 +OP4 E00AF8 0 +OP4 E00AF9 0 +OP4 E00AFA 0 +OP4 E00AFB 0 +OP4 E00AFC 0 +OP4 E00AFD 0 +OP4 E00AFE 0 +OP4 E00AFF 0 +OP4 E00B00 0 +OP4 E00B01 0 +OP4 E00B02 0 +OP4 E00B03 0 +OP4 E00B04 0 +OP4 E00B05 0 +OP4 E00B06 0 +OP4 E00B07 0 +OP4 E00B08 0 +OP4 E00B09 0 +OP4 E00B0A 0 +OP4 E00B0B 0 +OP4 E00B0C 0 +OP4 E00B0D 0 +OP4 E00B0E 0 +OP4 E00B0F 0 +OP4 E00B10 0 +OP4 E00B11 0 +OP4 E00B12 0 +OP4 E00B13 0 +OP4 E00B14 0 +OP4 E00B15 0 +OP4 E00B16 0 +OP4 E00B17 0 +OP4 E00B18 0 +OP4 E00B19 0 +OP4 E00B1A 0 +OP4 E00B1B 0 +OP4 E00B1C 0 +OP4 E00B1D 0 +OP4 E00B1E 0 +OP4 E00B1F 0 +OP4 E00B20 0 +OP4 E00B21 0 +OP4 E00B22 0 +OP4 E00B23 0 +OP4 E00B24 0 +OP4 E00B25 0 +OP4 E00B26 0 +OP4 E00B27 0 +OP4 E00B28 0 +OP4 E00B29 0 +OP4 E00B2A 0 +OP4 E00B2B 0 +OP4 E00B2C 0 +OP4 E00B2D 0 +OP4 E00B2E 0 +OP4 E00B2F 0 +OP4 E00B30 0 +OP4 E00B31 0 +OP4 E00B32 0 +OP4 E00B33 0 +OP4 E00B34 0 +OP4 E00B35 0 +OP4 E00B36 0 +OP4 E00B37 0 +OP4 E00B38 0 +OP4 E00B39 0 +OP4 E00B3A 0 +OP4 E00B3B 0 +OP4 E00B3C 0 +OP4 E00B3D 0 +OP4 E00B3E 0 +OP4 E00B3F 0 +OP4 E00B40 0 +OP4 E00B41 0 +OP4 E00B42 0 +OP4 E00B43 0 +OP4 E00B44 0 +OP4 E00B45 0 +OP4 E00B46 0 +OP4 E00B47 0 +OP4 E00B48 0 +OP4 E00B49 0 +OP4 E00B4A 0 +OP4 E00B4B 0 +OP4 E00B4C 0 +OP4 E00B4D 0 +OP4 E00B4E 0 +OP4 E00B4F 0 +OP4 E00B50 0 +OP4 E00B51 0 +OP4 E00B52 0 +OP4 E00B53 0 +OP4 E00B54 0 +OP4 E00B55 0 +OP4 E00B56 0 +OP4 E00B57 0 +OP4 E00B58 0 +OP4 E00B59 0 +OP4 E00B5A 0 +OP4 E00B5B 0 +OP4 E00B5C 0 +OP4 E00B5D 0 +OP4 E00B5E 0 +OP4 E00B5F 0 +OP4 E00B60 0 +OP4 E00B61 0 +OP4 E00B62 0 +OP4 E00B63 0 +OP4 E00B64 0 +OP4 E00B65 0 +OP4 E00B66 0 +OP4 E00B67 0 +OP4 E00B68 0 +OP4 E00B69 0 +OP4 E00B6A 0 +OP4 E00B6B 0 +OP4 E00B6C 0 +OP4 E00B6D 0 +OP4 E00B6E 0 +OP4 E00B6F 0 +OP4 E00B70 0 +OP4 E00B71 0 +OP4 E00B72 0 +OP4 E00B73 0 +OP4 E00B74 0 +OP4 E00B75 0 +OP4 E00B76 0 +OP4 E00B77 0 +OP4 E00B78 0 +OP4 E00B79 0 +OP4 E00B7A 0 +OP4 E00B7B 0 +OP4 E00B7C 0 +OP4 E00B7D 0 +OP4 E00B7E 0 +OP4 E00B7F 0 +OP4 E00B80 0 +OP4 E00B81 0 +OP4 E00B82 0 +OP4 E00B83 0 +OP4 E00B84 0 +OP4 E00B85 0 +OP4 E00B86 0 +OP4 E00B87 0 +OP4 E00B88 0 +OP4 E00B89 0 +OP4 E00B8A 0 +OP4 E00B8B 0 +OP4 E00B8C 0 +OP4 E00B8D 0 +OP4 E00B8E 0 +OP4 E00B8F 0 +OP4 E00B90 0 +OP4 E00B91 0 +OP4 E00B92 0 +OP4 E00B93 0 +OP4 E00B94 0 +OP4 E00B95 0 +OP4 E00B96 0 +OP4 E00B97 0 +OP4 E00B98 0 +OP4 E00B99 0 +OP4 E00B9A 0 +OP4 E00B9B 0 +OP4 E00B9C 0 +OP4 E00B9D 0 +OP4 E00B9E 0 +OP4 E00B9F 0 +OP4 E00BA0 0 +OP4 E00BA1 0 +OP4 E00BA2 0 +OP4 E00BA3 0 +OP4 E00BA4 0 +OP4 E00BA5 0 +OP4 E00BA6 0 +OP4 E00BA7 0 +OP4 E00BA8 0 +OP4 E00BA9 0 +OP4 E00BAA 0 +OP4 E00BAB 0 +OP4 E00BAC 0 +OP4 E00BAD 0 +OP4 E00BAE 0 +OP4 E00BAF 0 +OP4 E00BB0 0 +OP4 E00BB1 0 +OP4 E00BB2 0 +OP4 E00BB3 0 +OP4 E00BB4 0 +OP4 E00BB5 0 +OP4 E00BB6 0 +OP4 E00BB7 0 +OP4 E00BB8 0 +OP4 E00BB9 0 +OP4 E00BBA 0 +OP4 E00BBB 0 +OP4 E00BBC 0 +OP4 E00BBD 0 +OP4 E00BBE 0 +OP4 E00BBF 0 +OP4 E00BC0 0 +OP4 E00BC1 0 +OP4 E00BC2 0 +OP4 E00BC3 0 +OP4 E00BC4 0 +OP4 E00BC5 0 +OP4 E00BC6 0 +OP4 E00BC7 0 +OP4 E00BC8 0 +OP4 E00BC9 0 +OP4 E00BCA 0 +OP4 E00BCB 0 +OP4 E00BCC 0 +OP4 E00BCD 0 +OP4 E00BCE 0 +OP4 E00BCF 0 +OP4 E00BD0 0 +OP4 E00BD1 0 +OP4 E00BD2 0 +OP4 E00BD3 0 +OP4 E00BD4 0 +OP4 E00BD5 0 +OP4 E00BD6 0 +OP4 E00BD7 0 +OP4 E00BD8 0 +OP4 E00BD9 0 +OP4 E00BDA 0 +OP4 E00BDB 0 +OP4 E00BDC 0 +OP4 E00BDD 0 +OP4 E00BDE 0 +OP4 E00BDF 0 +OP4 E00BE0 0 +OP4 E00BE1 0 +OP4 E00BE2 0 +OP4 E00BE3 0 +OP4 E00BE4 0 +OP4 E00BE5 0 +OP4 E00BE6 0 +OP4 E00BE7 0 +OP4 E00BE8 0 +OP4 E00BE9 0 +OP4 E00BEA 0 +OP4 E00BEB 0 +OP4 E00BEC 0 +OP4 E00BED 0 +OP4 E00BEE 0 +OP4 E00BEF 0 +OP4 E00BF0 0 +OP4 E00BF1 0 +OP4 E00BF2 0 +OP4 E00BF3 0 +OP4 E00BF4 0 +OP4 E00BF5 0 +OP4 E00BF6 0 +OP4 E00BF7 0 +OP4 E00BF8 0 +OP4 E00BF9 0 +OP4 E00BFA 0 +OP4 E00BFB 0 +OP4 E00BFC 0 +OP4 E00BFD 0 +OP4 E00BFE 0 +OP4 E00BFF 0 +OP4 E00C00 0 +OP4 E00C01 0 +OP4 E00C02 0 +OP4 E00C03 0 +OP4 E00C04 0 +OP4 E00C05 0 +OP4 E00C06 0 +OP4 E00C07 0 +OP4 E00C08 0 +OP4 E00C09 0 +OP4 E00C0A 0 +OP4 E00C0B 0 +OP4 E00C0C 0 +OP4 E00C0D 0 +OP4 E00C0E 0 +OP4 E00C0F 0 +OP4 E00C10 0 +OP4 E00C11 0 +OP4 E00C12 0 +OP4 E00C13 0 +OP4 E00C14 0 +OP4 E00C15 0 +OP4 E00C16 0 +OP4 E00C17 0 +OP4 E00C18 0 +OP4 E00C19 0 +OP4 E00C1A 0 +OP4 E00C1B 0 +OP4 E00C1C 0 +OP4 E00C1D 0 +OP4 E00C1E 0 +OP4 E00C1F 0 +OP4 E00C20 0 +OP4 E00C21 0 +OP4 E00C22 0 +OP4 E00C23 0 +OP4 E00C24 0 +OP4 E00C25 0 +OP4 E00C26 0 +OP4 E00C27 0 +OP4 E00C28 0 +OP4 E00C29 0 +OP4 E00C2A 0 +OP4 E00C2B 0 +OP4 E00C2C 0 +OP4 E00C2D 0 +OP4 E00C2E 0 +OP4 E00C2F 0 +OP4 E00C30 0 +OP4 E00C31 0 +OP4 E00C32 0 +OP4 E00C33 0 +OP4 E00C34 0 +OP4 E00C35 0 +OP4 E00C36 0 +OP4 E00C37 0 +OP4 E00C38 0 +OP4 E00C39 0 +OP4 E00C3A 0 +OP4 E00C3B 0 +OP4 E00C3C 0 +OP4 E00C3D 0 +OP4 E00C3E 0 +OP4 E00C3F 0 +OP4 E00C40 0 +OP4 E00C41 0 +OP4 E00C42 0 +OP4 E00C43 0 +OP4 E00C44 0 +OP4 E00C45 0 +OP4 E00C46 0 +OP4 E00C47 0 +OP4 E00C48 0 +OP4 E00C49 0 +OP4 E00C4A 0 +OP4 E00C4B 0 +OP4 E00C4C 0 +OP4 E00C4D 0 +OP4 E00C4E 0 +OP4 E00C4F 0 +OP4 E00C50 0 +OP4 E00C51 0 +OP4 E00C52 0 +OP4 E00C53 0 +OP4 E00C54 0 +OP4 E00C55 0 +OP4 E00C56 0 +OP4 E00C57 0 +OP4 E00C58 0 +OP4 E00C59 0 +OP4 E00C5A 0 +OP4 E00C5B 0 +OP4 E00C5C 0 +OP4 E00C5D 0 +OP4 E00C5E 0 +OP4 E00C5F 0 +OP4 E00C60 0 +OP4 E00C61 0 +OP4 E00C62 0 +OP4 E00C63 0 +OP4 E00C64 0 +OP4 E00C65 0 +OP4 E00C66 0 +OP4 E00C67 0 +OP4 E00C68 0 +OP4 E00C69 0 +OP4 E00C6A 0 +OP4 E00C6B 0 +OP4 E00C6C 0 +OP4 E00C6D 0 +OP4 E00C6E 0 +OP4 E00C6F 0 +OP4 E00C70 0 +OP4 E00C71 0 +OP4 E00C72 0 +OP4 E00C73 0 +OP4 E00C74 0 +OP4 E00C75 0 +OP4 E00C76 0 +OP4 E00C77 0 +OP4 E00C78 0 +OP4 E00C79 0 +OP4 E00C7A 0 +OP4 E00C7B 0 +OP4 E00C7C 0 +OP4 E00C7D 0 +OP4 E00C7E 0 +OP4 E00C7F 0 +OP4 E00C80 0 +OP4 E00C81 0 +OP4 E00C82 0 +OP4 E00C83 0 +OP4 E00C84 0 +OP4 E00C85 0 +OP4 E00C86 0 +OP4 E00C87 0 +OP4 E00C88 0 +OP4 E00C89 0 +OP4 E00C8A 0 +OP4 E00C8B 0 +OP4 E00C8C 0 +OP4 E00C8D 0 +OP4 E00C8E 0 +OP4 E00C8F 0 +OP4 E00C90 0 +OP4 E00C91 0 +OP4 E00C92 0 +OP4 E00C93 0 +OP4 E00C94 0 +OP4 E00C95 0 +OP4 E00C96 0 +OP4 E00C97 0 +OP4 E00C98 0 +OP4 E00C99 0 +OP4 E00C9A 0 +OP4 E00C9B 0 +OP4 E00C9C 0 +OP4 E00C9D 0 +OP4 E00C9E 0 +OP4 E00C9F 0 +OP4 E00CA0 0 +OP4 E00CA1 0 +OP4 E00CA2 0 +OP4 E00CA3 0 +OP4 E00CA4 0 +OP4 E00CA5 0 +OP4 E00CA6 0 +OP4 E00CA7 0 +OP4 E00CA8 0 +OP4 E00CA9 0 +OP4 E00CAA 0 +OP4 E00CAB 0 +OP4 E00CAC 0 +OP4 E00CAD 0 +OP4 E00CAE 0 +OP4 E00CAF 0 +OP4 E00CB0 0 +OP4 E00CB1 0 +OP4 E00CB2 0 +OP4 E00CB3 0 +OP4 E00CB4 0 +OP4 E00CB5 0 +OP4 E00CB6 0 +OP4 E00CB7 0 +OP4 E00CB8 0 +OP4 E00CB9 0 +OP4 E00CBA 0 +OP4 E00CBB 0 +OP4 E00CBC 0 +OP4 E00CBD 0 +OP4 E00CBE 0 +OP4 E00CBF 0 +OP4 E00CC0 0 +OP4 E00CC1 0 +OP4 E00CC2 0 +OP4 E00CC3 0 +OP4 E00CC4 0 +OP4 E00CC5 0 +OP4 E00CC6 0 +OP4 E00CC7 0 +OP4 E00CC8 0 +OP4 E00CC9 0 +OP4 E00CCA 0 +OP4 E00CCB 0 +OP4 E00CCC 0 +OP4 E00CCD 0 +OP4 E00CCE 0 +OP4 E00CCF 0 +OP4 E00CD0 0 +OP4 E00CD1 0 +OP4 E00CD2 0 +OP4 E00CD3 0 +OP4 E00CD4 0 +OP4 E00CD5 0 +OP4 E00CD6 0 +OP4 E00CD7 0 +OP4 E00CD8 0 +OP4 E00CD9 0 +OP4 E00CDA 0 +OP4 E00CDB 0 +OP4 E00CDC 0 +OP4 E00CDD 0 +OP4 E00CDE 0 +OP4 E00CDF 0 +OP4 E00CE0 0 +OP4 E00CE1 0 +OP4 E00CE2 0 +OP4 E00CE3 0 +OP4 E00CE4 0 +OP4 E00CE5 0 +OP4 E00CE6 0 +OP4 E00CE7 0 +OP4 E00CE8 0 +OP4 E00CE9 0 +OP4 E00CEA 0 +OP4 E00CEB 0 +OP4 E00CEC 0 +OP4 E00CED 0 +OP4 E00CEE 0 +OP4 E00CEF 0 +OP4 E00CF0 0 +OP4 E00CF1 0 +OP4 E00CF2 0 +OP4 E00CF3 0 +OP4 E00CF4 0 +OP4 E00CF5 0 +OP4 E00CF6 0 +OP4 E00CF7 0 +OP4 E00CF8 0 +OP4 E00CF9 0 +OP4 E00CFA 0 +OP4 E00CFB 0 +OP4 E00CFC 0 +OP4 E00CFD 0 +OP4 E00CFE 0 +OP4 E00CFF 0 +OP4 E00D00 0 +OP4 E00D01 0 +OP4 E00D02 0 +OP4 E00D03 0 +OP4 E00D04 0 +OP4 E00D05 0 +OP4 E00D06 0 +OP4 E00D07 0 +OP4 E00D08 0 +OP4 E00D09 0 +OP4 E00D0A 0 +OP4 E00D0B 0 +OP4 E00D0C 0 +OP4 E00D0D 0 +OP4 E00D0E 0 +OP4 E00D0F 0 +OP4 E00D10 0 +OP4 E00D11 0 +OP4 E00D12 0 +OP4 E00D13 0 +OP4 E00D14 0 +OP4 E00D15 0 +OP4 E00D16 0 +OP4 E00D17 0 +OP4 E00D18 0 +OP4 E00D19 0 +OP4 E00D1A 0 +OP4 E00D1B 0 +OP4 E00D1C 0 +OP4 E00D1D 0 +OP4 E00D1E 0 +OP4 E00D1F 0 +OP4 E00D20 0 +OP4 E00D21 0 +OP4 E00D22 0 +OP4 E00D23 0 +OP4 E00D24 0 +OP4 E00D25 0 +OP4 E00D26 0 +OP4 E00D27 0 +OP4 E00D28 0 +OP4 E00D29 0 +OP4 E00D2A 0 +OP4 E00D2B 0 +OP4 E00D2C 0 +OP4 E00D2D 0 +OP4 E00D2E 0 +OP4 E00D2F 0 +OP4 E00D30 0 +OP4 E00D31 0 +OP4 E00D32 0 +OP4 E00D33 0 +OP4 E00D34 0 +OP4 E00D35 0 +OP4 E00D36 0 +OP4 E00D37 0 +OP4 E00D38 0 +OP4 E00D39 0 +OP4 E00D3A 0 +OP4 E00D3B 0 +OP4 E00D3C 0 +OP4 E00D3D 0 +OP4 E00D3E 0 +OP4 E00D3F 0 +OP4 E00D40 0 +OP4 E00D41 0 +OP4 E00D42 0 +OP4 E00D43 0 +OP4 E00D44 0 +OP4 E00D45 0 +OP4 E00D46 0 +OP4 E00D47 0 +OP4 E00D48 0 +OP4 E00D49 0 +OP4 E00D4A 0 +OP4 E00D4B 0 +OP4 E00D4C 0 +OP4 E00D4D 0 +OP4 E00D4E 0 +OP4 E00D4F 0 +OP4 E00D50 0 +OP4 E00D51 0 +OP4 E00D52 0 +OP4 E00D53 0 +OP4 E00D54 0 +OP4 E00D55 0 +OP4 E00D56 0 +OP4 E00D57 0 +OP4 E00D58 0 +OP4 E00D59 0 +OP4 E00D5A 0 +OP4 E00D5B 0 +OP4 E00D5C 0 +OP4 E00D5D 0 +OP4 E00D5E 0 +OP4 E00D5F 0 +OP4 E00D60 0 +OP4 E00D61 0 +OP4 E00D62 0 +OP4 E00D63 0 +OP4 E00D64 0 +OP4 E00D65 0 +OP4 E00D66 0 +OP4 E00D67 0 +OP4 E00D68 0 +OP4 E00D69 0 +OP4 E00D6A 0 +OP4 E00D6B 0 +OP4 E00D6C 0 +OP4 E00D6D 0 +OP4 E00D6E 0 +OP4 E00D6F 0 +OP4 E00D70 0 +OP4 E00D71 0 +OP4 E00D72 0 +OP4 E00D73 0 +OP4 E00D74 0 +OP4 E00D75 0 +OP4 E00D76 0 +OP4 E00D77 0 +OP4 E00D78 0 +OP4 E00D79 0 +OP4 E00D7A 0 +OP4 E00D7B 0 +OP4 E00D7C 0 +OP4 E00D7D 0 +OP4 E00D7E 0 +OP4 E00D7F 0 +OP4 E00D80 0 +OP4 E00D81 0 +OP4 E00D82 0 +OP4 E00D83 0 +OP4 E00D84 0 +OP4 E00D85 0 +OP4 E00D86 0 +OP4 E00D87 0 +OP4 E00D88 0 +OP4 E00D89 0 +OP4 E00D8A 0 +OP4 E00D8B 0 +OP4 E00D8C 0 +OP4 E00D8D 0 +OP4 E00D8E 0 +OP4 E00D8F 0 +OP4 E00D90 0 +OP4 E00D91 0 +OP4 E00D92 0 +OP4 E00D93 0 +OP4 E00D94 0 +OP4 E00D95 0 +OP4 E00D96 0 +OP4 E00D97 0 +OP4 E00D98 0 +OP4 E00D99 0 +OP4 E00D9A 0 +OP4 E00D9B 0 +OP4 E00D9C 0 +OP4 E00D9D 0 +OP4 E00D9E 0 +OP4 E00D9F 0 +OP4 E00DA0 0 +OP4 E00DA1 0 +OP4 E00DA2 0 +OP4 E00DA3 0 +OP4 E00DA4 0 +OP4 E00DA5 0 +OP4 E00DA6 0 +OP4 E00DA7 0 +OP4 E00DA8 0 +OP4 E00DA9 0 +OP4 E00DAA 0 +OP4 E00DAB 0 +OP4 E00DAC 0 +OP4 E00DAD 0 +OP4 E00DAE 0 +OP4 E00DAF 0 +OP4 E00DB0 0 +OP4 E00DB1 0 +OP4 E00DB2 0 +OP4 E00DB3 0 +OP4 E00DB4 0 +OP4 E00DB5 0 +OP4 E00DB6 0 +OP4 E00DB7 0 +OP4 E00DB8 0 +OP4 E00DB9 0 +OP4 E00DBA 0 +OP4 E00DBB 0 +OP4 E00DBC 0 +OP4 E00DBD 0 +OP4 E00DBE 0 +OP4 E00DBF 0 +OP4 E00DC0 0 +OP4 E00DC1 0 +OP4 E00DC2 0 +OP4 E00DC3 0 +OP4 E00DC4 0 +OP4 E00DC5 0 +OP4 E00DC6 0 +OP4 E00DC7 0 +OP4 E00DC8 0 +OP4 E00DC9 0 +OP4 E00DCA 0 +OP4 E00DCB 0 +OP4 E00DCC 0 +OP4 E00DCD 0 +OP4 E00DCE 0 +OP4 E00DCF 0 +OP4 E00DD0 0 +OP4 E00DD1 0 +OP4 E00DD2 0 +OP4 E00DD3 0 +OP4 E00DD4 0 +OP4 E00DD5 0 +OP4 E00DD6 0 +OP4 E00DD7 0 +OP4 E00DD8 0 +OP4 E00DD9 0 +OP4 E00DDA 0 +OP4 E00DDB 0 +OP4 E00DDC 0 +OP4 E00DDD 0 +OP4 E00DDE 0 +OP4 E00DDF 0 +OP4 E00DE0 0 +OP4 E00DE1 0 +OP4 E00DE2 0 +OP4 E00DE3 0 +OP4 E00DE4 0 +OP4 E00DE5 0 +OP4 E00DE6 0 +OP4 E00DE7 0 +OP4 E00DE8 0 +OP4 E00DE9 0 +OP4 E00DEA 0 +OP4 E00DEB 0 +OP4 E00DEC 0 +OP4 E00DED 0 +OP4 E00DEE 0 +OP4 E00DEF 0 +OP4 E00DF0 0 +OP4 E00DF1 0 +OP4 E00DF2 0 +OP4 E00DF3 0 +OP4 E00DF4 0 +OP4 E00DF5 0 +OP4 E00DF6 0 +OP4 E00DF7 0 +OP4 E00DF8 0 +OP4 E00DF9 0 +OP4 E00DFA 0 +OP4 E00DFB 0 +OP4 E00DFC 0 +OP4 E00DFD 0 +OP4 E00DFE 0 +OP4 E00DFF 0 +OP4 E00E00 0 +OP4 E00E01 0 +OP4 E00E02 0 +OP4 E00E03 0 +OP4 E00E04 0 +OP4 E00E05 0 +OP4 E00E06 0 +OP4 E00E07 0 +OP4 E00E08 0 +OP4 E00E09 0 +OP4 E00E0A 0 +OP4 E00E0B 0 +OP4 E00E0C 0 +OP4 E00E0D 0 +OP4 E00E0E 0 +OP4 E00E0F 0 +OP4 E00E10 0 +OP4 E00E11 0 +OP4 E00E12 0 +OP4 E00E13 0 +OP4 E00E14 0 +OP4 E00E15 0 +OP4 E00E16 0 +OP4 E00E17 0 +OP4 E00E18 0 +OP4 E00E19 0 +OP4 E00E1A 0 +OP4 E00E1B 0 +OP4 E00E1C 0 +OP4 E00E1D 0 +OP4 E00E1E 0 +OP4 E00E1F 0 +OP4 E00E20 0 +OP4 E00E21 0 +OP4 E00E22 0 +OP4 E00E23 0 +OP4 E00E24 0 +OP4 E00E25 0 +OP4 E00E26 0 +OP4 E00E27 0 +OP4 E00E28 0 +OP4 E00E29 0 +OP4 E00E2A 0 +OP4 E00E2B 0 +OP4 E00E2C 0 +OP4 E00E2D 0 +OP4 E00E2E 0 +OP4 E00E2F 0 +OP4 E00E30 0 +OP4 E00E31 0 +OP4 E00E32 0 +OP4 E00E33 0 +OP4 E00E34 0 +OP4 E00E35 0 +OP4 E00E36 0 +OP4 E00E37 0 +OP4 E00E38 0 +OP4 E00E39 0 +OP4 E00E3A 0 +OP4 E00E3B 0 +OP4 E00E3C 0 +OP4 E00E3D 0 +OP4 E00E3E 0 +OP4 E00E3F 0 +OP4 E00E40 0 +OP4 E00E41 0 +OP4 E00E42 0 +OP4 E00E43 0 +OP4 E00E44 0 +OP4 E00E45 0 +OP4 E00E46 0 +OP4 E00E47 0 +OP4 E00E48 0 +OP4 E00E49 0 +OP4 E00E4A 0 +OP4 E00E4B 0 +OP4 E00E4C 0 +OP4 E00E4D 0 +OP4 E00E4E 0 +OP4 E00E4F 0 +OP4 E00E50 0 +OP4 E00E51 0 +OP4 E00E52 0 +OP4 E00E53 0 +OP4 E00E54 0 +OP4 E00E55 0 +OP4 E00E56 0 +OP4 E00E57 0 +OP4 E00E58 0 +OP4 E00E59 0 +OP4 E00E5A 0 +OP4 E00E5B 0 +OP4 E00E5C 0 +OP4 E00E5D 0 +OP4 E00E5E 0 +OP4 E00E5F 0 +OP4 E00E60 0 +OP4 E00E61 0 +OP4 E00E62 0 +OP4 E00E63 0 +OP4 E00E64 0 +OP4 E00E65 0 +OP4 E00E66 0 +OP4 E00E67 0 +OP4 E00E68 0 +OP4 E00E69 0 +OP4 E00E6A 0 +OP4 E00E6B 0 +OP4 E00E6C 0 +OP4 E00E6D 0 +OP4 E00E6E 0 +OP4 E00E6F 0 +OP4 E00E70 0 +OP4 E00E71 0 +OP4 E00E72 0 +OP4 E00E73 0 +OP4 E00E74 0 +OP4 E00E75 0 +OP4 E00E76 0 +OP4 E00E77 0 +OP4 E00E78 0 +OP4 E00E79 0 +OP4 E00E7A 0 +OP4 E00E7B 0 +OP4 E00E7C 0 +OP4 E00E7D 0 +OP4 E00E7E 0 +OP4 E00E7F 0 +OP4 E00E80 0 +OP4 E00E81 0 +OP4 E00E82 0 +OP4 E00E83 0 +OP4 E00E84 0 +OP4 E00E85 0 +OP4 E00E86 0 +OP4 E00E87 0 +OP4 E00E88 0 +OP4 E00E89 0 +OP4 E00E8A 0 +OP4 E00E8B 0 +OP4 E00E8C 0 +OP4 E00E8D 0 +OP4 E00E8E 0 +OP4 E00E8F 0 +OP4 E00E90 0 +OP4 E00E91 0 +OP4 E00E92 0 +OP4 E00E93 0 +OP4 E00E94 0 +OP4 E00E95 0 +OP4 E00E96 0 +OP4 E00E97 0 +OP4 E00E98 0 +OP4 E00E99 0 +OP4 E00E9A 0 +OP4 E00E9B 0 +OP4 E00E9C 0 +OP4 E00E9D 0 +OP4 E00E9E 0 +OP4 E00E9F 0 +OP4 E00EA0 0 +OP4 E00EA1 0 +OP4 E00EA2 0 +OP4 E00EA3 0 +OP4 E00EA4 0 +OP4 E00EA5 0 +OP4 E00EA6 0 +OP4 E00EA7 0 +OP4 E00EA8 0 +OP4 E00EA9 0 +OP4 E00EAA 0 +OP4 E00EAB 0 +OP4 E00EAC 0 +OP4 E00EAD 0 +OP4 E00EAE 0 +OP4 E00EAF 0 +OP4 E00EB0 0 +OP4 E00EB1 0 +OP4 E00EB2 0 +OP4 E00EB3 0 +OP4 E00EB4 0 +OP4 E00EB5 0 +OP4 E00EB6 0 +OP4 E00EB7 0 +OP4 E00EB8 0 +OP4 E00EB9 0 +OP4 E00EBA 0 +OP4 E00EBB 0 +OP4 E00EBC 0 +OP4 E00EBD 0 +OP4 E00EBE 0 +OP4 E00EBF 0 +OP4 E00EC0 0 +OP4 E00EC1 0 +OP4 E00EC2 0 +OP4 E00EC3 0 +OP4 E00EC4 0 +OP4 E00EC5 0 +OP4 E00EC6 0 +OP4 E00EC7 0 +OP4 E00EC8 0 +OP4 E00EC9 0 +OP4 E00ECA 0 +OP4 E00ECB 0 +OP4 E00ECC 0 +OP4 E00ECD 0 +OP4 E00ECE 0 +OP4 E00ECF 0 +OP4 E00ED0 0 +OP4 E00ED1 0 +OP4 E00ED2 0 +OP4 E00ED3 0 +OP4 E00ED4 0 +OP4 E00ED5 0 +OP4 E00ED6 0 +OP4 E00ED7 0 +OP4 E00ED8 0 +OP4 E00ED9 0 +OP4 E00EDA 0 +OP4 E00EDB 0 +OP4 E00EDC 0 +OP4 E00EDD 0 +OP4 E00EDE 0 +OP4 E00EDF 0 +OP4 E00EE0 0 +OP4 E00EE1 0 +OP4 E00EE2 0 +OP4 E00EE3 0 +OP4 E00EE4 0 +OP4 E00EE5 0 +OP4 E00EE6 0 +OP4 E00EE7 0 +OP4 E00EE8 0 +OP4 E00EE9 0 +OP4 E00EEA 0 +OP4 E00EEB 0 +OP4 E00EEC 0 +OP4 E00EED 0 +OP4 E00EEE 0 +OP4 E00EEF 0 +OP4 E00EF0 0 +OP4 E00EF1 0 +OP4 E00EF2 0 +OP4 E00EF3 0 +OP4 E00EF4 0 +OP4 E00EF5 0 +OP4 E00EF6 0 +OP4 E00EF7 0 +OP4 E00EF8 0 +OP4 E00EF9 0 +OP4 E00EFA 0 +OP4 E00EFB 0 +OP4 E00EFC 0 +OP4 E00EFD 0 +OP4 E00EFE 0 +OP4 E00EFF 0 +OP4 E00F00 0 +OP4 E00F01 0 +OP4 E00F02 0 +OP4 E00F03 0 +OP4 E00F04 0 +OP4 E00F05 0 +OP4 E00F06 0 +OP4 E00F07 0 +OP4 E00F08 0 +OP4 E00F09 0 +OP4 E00F0A 0 +OP4 E00F0B 0 +OP4 E00F0C 0 +OP4 E00F0D 0 +OP4 E00F0E 0 +OP4 E00F0F 0 +OP4 E00F10 0 +OP4 E00F11 0 +OP4 E00F12 0 +OP4 E00F13 0 +OP4 E00F14 0 +OP4 E00F15 0 +OP4 E00F16 0 +OP4 E00F17 0 +OP4 E00F18 0 +OP4 E00F19 0 +OP4 E00F1A 0 +OP4 E00F1B 0 +OP4 E00F1C 0 +OP4 E00F1D 0 +OP4 E00F1E 0 +OP4 E00F1F 0 +OP4 E00F20 0 +OP4 E00F21 0 +OP4 E00F22 0 +OP4 E00F23 0 +OP4 E00F24 0 +OP4 E00F25 0 +OP4 E00F26 0 +OP4 E00F27 0 +OP4 E00F28 0 +OP4 E00F29 0 +OP4 E00F2A 0 +OP4 E00F2B 0 +OP4 E00F2C 0 +OP4 E00F2D 0 +OP4 E00F2E 0 +OP4 E00F2F 0 +OP4 E00F30 0 diff --git a/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum3_itrace_irisc6.cfg.ext b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum3_itrace_irisc6.cfg.ext new file mode 100644 index 000000000000..7b8d3a5a33fc --- /dev/null +++ b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum3_itrace_irisc6.cfg.ext @@ -0,0 +1,3890 @@ +OP1 Spectrum3 +OP4 ITRACE0 0 +OP4 ITRACE1 0 +OP4 ITRACE2 0 +OP4 ITRACE3 0 +OP4 ITRACE4 0 +OP4 ITRACE5 0 +OP4 ITRACE6 1 +OP4 ITRACE7 0 +OP4 ITRACE8 0 +OP4 ITRACE9 0 +OP4 Main_PhyUC 0 +OP4 TILE0_ITRACE0 0 +OP4 TILE0_ITRACE1 0 +OP4 TILE0_ITRACE2 0 +OP4 TILE0_ITRACE3 0 +OP4 TILE0_ITRACE4 0 +OP4 TILE0_PhyUC 0 +OP4 TILE1_ITRACE0 0 +OP4 TILE1_ITRACE1 0 +OP4 TILE1_ITRACE2 0 +OP4 TILE1_ITRACE3 0 +OP4 TILE1_ITRACE4 0 +OP4 TILE1_PhyUC 0 +OP4 TILE2_ITRACE0 0 +OP4 TILE2_ITRACE1 0 +OP4 TILE2_ITRACE2 0 +OP4 TILE2_ITRACE3 0 +OP4 TILE2_ITRACE4 0 +OP4 TILE2_PhyUC 0 +OP4 TILE3_ITRACE0 0 +OP4 TILE3_ITRACE1 0 +OP4 TILE3_ITRACE2 0 +OP4 TILE3_ITRACE3 0 +OP4 TILE3_ITRACE4 0 +OP4 TILE3_PhyUC 0 +OP4 TILE4_ITRACE0 0 +OP4 TILE4_ITRACE1 0 +OP4 TILE4_ITRACE2 0 +OP4 TILE4_ITRACE3 0 +OP4 TILE4_ITRACE4 0 +OP4 TILE4_PhyUC 0 +OP4 TILE5_ITRACE0 0 +OP4 TILE5_ITRACE1 0 +OP4 TILE5_ITRACE2 0 +OP4 TILE5_ITRACE3 0 +OP4 TILE5_ITRACE4 0 +OP4 TILE5_PhyUC 0 +OP4 TILE6_ITRACE0 0 +OP4 TILE6_ITRACE1 0 +OP4 TILE6_ITRACE2 0 +OP4 TILE6_ITRACE3 0 +OP4 TILE6_ITRACE4 0 +OP4 TILE6_PhyUC 0 +OP4 TILE7_ITRACE0 0 +OP4 TILE7_ITRACE1 0 +OP4 TILE7_ITRACE2 0 +OP4 TILE7_ITRACE3 0 +OP4 TILE7_ITRACE4 0 +OP4 TILE7_PhyUC 0 +OP4 E0003B 0 +OP4 E0003C 0 +OP4 E0003D 0 +OP4 E0003E 0 +OP4 E0003F 0 +OP4 E00040 0 +OP4 E00041 0 +OP4 E00042 0 +OP4 E00043 0 +OP4 E00044 0 +OP4 E00045 0 +OP4 E00046 0 +OP4 E00047 0 +OP4 E00048 0 +OP4 E00049 0 +OP4 E0004A 0 +OP4 E0004B 0 +OP4 E0004C 0 +OP4 E0004D 0 +OP4 E0004E 0 +OP4 E0004F 0 +OP4 E00050 0 +OP4 E00051 0 +OP4 E00052 0 +OP4 E00053 0 +OP4 E00054 0 +OP4 E00055 0 +OP4 E00056 0 +OP4 E00057 0 +OP4 E00058 0 +OP4 E00059 0 +OP4 E0005A 0 +OP4 E0005B 0 +OP4 E0005C 0 +OP4 E0005D 0 +OP4 E0005E 0 +OP4 E0005F 0 +OP4 E00060 0 +OP4 E00061 0 +OP4 E00062 0 +OP4 E00063 0 +OP4 E00064 0 +OP4 E00065 0 +OP4 E00066 0 +OP4 E00067 0 +OP4 E00068 0 +OP4 E00069 0 +OP4 E0006A 0 +OP4 E0006B 0 +OP4 E0006C 0 +OP4 E0006D 0 +OP4 E0006E 0 +OP4 E0006F 0 +OP4 E00070 0 +OP4 E00071 0 +OP4 E00072 0 +OP4 E00073 0 +OP4 E00074 0 +OP4 E00075 0 +OP4 E00076 0 +OP4 E00077 0 +OP4 E00078 0 +OP4 E00079 0 +OP4 E0007A 0 +OP4 E0007B 0 +OP4 E0007C 0 +OP4 E0007D 0 +OP4 E0007E 0 +OP4 E0007F 0 +OP4 E00080 0 +OP4 E00081 0 +OP4 E00082 0 +OP4 E00083 0 +OP4 E00084 0 +OP4 E00085 0 +OP4 E00086 0 +OP4 E00087 0 +OP4 E00088 0 +OP4 E00089 0 +OP4 E0008A 0 +OP4 E0008B 0 +OP4 E0008C 0 +OP4 E0008D 0 +OP4 E0008E 0 +OP4 E0008F 0 +OP4 E00090 0 +OP4 E00091 0 +OP4 E00092 0 +OP4 E00093 0 +OP4 E00094 0 +OP4 E00095 0 +OP4 E00096 0 +OP4 E00097 0 +OP4 E00098 0 +OP4 E00099 0 +OP4 E0009A 0 +OP4 E0009B 0 +OP4 E0009C 0 +OP4 E0009D 0 +OP4 E0009E 0 +OP4 E0009F 0 +OP4 E000A0 0 +OP4 E000A1 0 +OP4 E000A2 0 +OP4 E000A3 0 +OP4 E000A4 0 +OP4 E000A5 0 +OP4 E000A6 0 +OP4 E000A7 0 +OP4 E000A8 0 +OP4 E000A9 0 +OP4 E000AA 0 +OP4 E000AB 0 +OP4 E000AC 0 +OP4 E000AD 0 +OP4 E000AE 0 +OP4 E000AF 0 +OP4 E000B0 0 +OP4 E000B1 0 +OP4 E000B2 0 +OP4 E000B3 0 +OP4 E000B4 0 +OP4 E000B5 0 +OP4 E000B6 0 +OP4 E000B7 0 +OP4 E000B8 0 +OP4 E000B9 0 +OP4 E000BA 0 +OP4 E000BB 0 +OP4 E000BC 0 +OP4 E000BD 0 +OP4 E000BE 0 +OP4 E000BF 0 +OP4 E000C0 0 +OP4 E000C1 0 +OP4 E000C2 0 +OP4 E000C3 0 +OP4 E000C4 0 +OP4 E000C5 0 +OP4 E000C6 0 +OP4 E000C7 0 +OP4 E000C8 0 +OP4 E000C9 0 +OP4 E000CA 0 +OP4 E000CB 0 +OP4 E000CC 0 +OP4 E000CD 0 +OP4 E000CE 0 +OP4 E000CF 0 +OP4 E000D0 0 +OP4 E000D1 0 +OP4 E000D2 0 +OP4 E000D3 0 +OP4 E000D4 0 +OP4 E000D5 0 +OP4 E000D6 0 +OP4 E000D7 0 +OP4 E000D8 0 +OP4 E000D9 0 +OP4 E000DA 0 +OP4 E000DB 0 +OP4 E000DC 0 +OP4 E000DD 0 +OP4 E000DE 0 +OP4 E000DF 0 +OP4 E000E0 0 +OP4 E000E1 0 +OP4 E000E2 0 +OP4 E000E3 0 +OP4 E000E4 0 +OP4 E000E5 0 +OP4 E000E6 0 +OP4 E000E7 0 +OP4 E000E8 0 +OP4 E000E9 0 +OP4 E000EA 0 +OP4 E000EB 0 +OP4 E000EC 0 +OP4 E000ED 0 +OP4 E000EE 0 +OP4 E000EF 0 +OP4 E000F0 0 +OP4 E000F1 0 +OP4 E000F2 0 +OP4 E000F3 0 +OP4 E000F4 0 +OP4 E000F5 0 +OP4 E000F6 0 +OP4 E000F7 0 +OP4 E000F8 0 +OP4 E000F9 0 +OP4 E000FA 0 +OP4 E000FB 0 +OP4 E000FC 0 +OP4 E000FD 0 +OP4 E000FE 0 +OP4 E000FF 0 +OP4 E00100 0 +OP4 E00101 0 +OP4 E00102 0 +OP4 E00103 0 +OP4 E00104 0 +OP4 E00105 0 +OP4 E00106 0 +OP4 E00107 0 +OP4 E00108 0 +OP4 E00109 0 +OP4 E0010A 0 +OP4 E0010B 0 +OP4 E0010C 0 +OP4 E0010D 0 +OP4 E0010E 0 +OP4 E0010F 0 +OP4 E00110 0 +OP4 E00111 0 +OP4 E00112 0 +OP4 E00113 0 +OP4 E00114 0 +OP4 E00115 0 +OP4 E00116 0 +OP4 E00117 0 +OP4 E00118 0 +OP4 E00119 0 +OP4 E0011A 0 +OP4 E0011B 0 +OP4 E0011C 0 +OP4 E0011D 0 +OP4 E0011E 0 +OP4 E0011F 0 +OP4 E00120 0 +OP4 E00121 0 +OP4 E00122 0 +OP4 E00123 0 +OP4 E00124 0 +OP4 E00125 0 +OP4 E00126 0 +OP4 E00127 0 +OP4 E00128 0 +OP4 E00129 0 +OP4 E0012A 0 +OP4 E0012B 0 +OP4 E0012C 0 +OP4 E0012D 0 +OP4 E0012E 0 +OP4 E0012F 0 +OP4 E00130 0 +OP4 E00131 0 +OP4 E00132 0 +OP4 E00133 0 +OP4 E00134 0 +OP4 E00135 0 +OP4 E00136 0 +OP4 E00137 0 +OP4 E00138 0 +OP4 E00139 0 +OP4 E0013A 0 +OP4 E0013B 0 +OP4 E0013C 0 +OP4 E0013D 0 +OP4 E0013E 0 +OP4 E0013F 0 +OP4 E00140 0 +OP4 E00141 0 +OP4 E00142 0 +OP4 E00143 0 +OP4 E00144 0 +OP4 E00145 0 +OP4 E00146 0 +OP4 E00147 0 +OP4 E00148 0 +OP4 E00149 0 +OP4 E0014A 0 +OP4 E0014B 0 +OP4 E0014C 0 +OP4 E0014D 0 +OP4 E0014E 0 +OP4 E0014F 0 +OP4 E00150 0 +OP4 E00151 0 +OP4 E00152 0 +OP4 E00153 0 +OP4 E00154 0 +OP4 E00155 0 +OP4 E00156 0 +OP4 E00157 0 +OP4 E00158 0 +OP4 E00159 0 +OP4 E0015A 0 +OP4 E0015B 0 +OP4 E0015C 0 +OP4 E0015D 0 +OP4 E0015E 0 +OP4 E0015F 0 +OP4 E00160 0 +OP4 E00161 0 +OP4 E00162 0 +OP4 E00163 0 +OP4 E00164 0 +OP4 E00165 0 +OP4 E00166 0 +OP4 E00167 0 +OP4 E00168 0 +OP4 E00169 0 +OP4 E0016A 0 +OP4 E0016B 0 +OP4 E0016C 0 +OP4 E0016D 0 +OP4 E0016E 0 +OP4 E0016F 0 +OP4 E00170 0 +OP4 E00171 0 +OP4 E00172 0 +OP4 E00173 0 +OP4 E00174 0 +OP4 E00175 0 +OP4 E00176 0 +OP4 E00177 0 +OP4 E00178 0 +OP4 E00179 0 +OP4 E0017A 0 +OP4 E0017B 0 +OP4 E0017C 0 +OP4 E0017D 0 +OP4 E0017E 0 +OP4 E0017F 0 +OP4 E00180 0 +OP4 E00181 0 +OP4 E00182 0 +OP4 E00183 0 +OP4 E00184 0 +OP4 E00185 0 +OP4 E00186 0 +OP4 E00187 0 +OP4 E00188 0 +OP4 E00189 0 +OP4 E0018A 0 +OP4 E0018B 0 +OP4 E0018C 0 +OP4 E0018D 0 +OP4 E0018E 0 +OP4 E0018F 0 +OP4 E00190 0 +OP4 E00191 0 +OP4 E00192 0 +OP4 E00193 0 +OP4 E00194 0 +OP4 E00195 0 +OP4 E00196 0 +OP4 E00197 0 +OP4 E00198 0 +OP4 E00199 0 +OP4 E0019A 0 +OP4 E0019B 0 +OP4 E0019C 0 +OP4 E0019D 0 +OP4 E0019E 0 +OP4 E0019F 0 +OP4 E001A0 0 +OP4 E001A1 0 +OP4 E001A2 0 +OP4 E001A3 0 +OP4 E001A4 0 +OP4 E001A5 0 +OP4 E001A6 0 +OP4 E001A7 0 +OP4 E001A8 0 +OP4 E001A9 0 +OP4 E001AA 0 +OP4 E001AB 0 +OP4 E001AC 0 +OP4 E001AD 0 +OP4 E001AE 0 +OP4 E001AF 0 +OP4 E001B0 0 +OP4 E001B1 0 +OP4 E001B2 0 +OP4 E001B3 0 +OP4 E001B4 0 +OP4 E001B5 0 +OP4 E001B6 0 +OP4 E001B7 0 +OP4 E001B8 0 +OP4 E001B9 0 +OP4 E001BA 0 +OP4 E001BB 0 +OP4 E001BC 0 +OP4 E001BD 0 +OP4 E001BE 0 +OP4 E001BF 0 +OP4 E001C0 0 +OP4 E001C1 0 +OP4 E001C2 0 +OP4 E001C3 0 +OP4 E001C4 0 +OP4 E001C5 0 +OP4 E001C6 0 +OP4 E001C7 0 +OP4 E001C8 0 +OP4 E001C9 0 +OP4 E001CA 0 +OP4 E001CB 0 +OP4 E001CC 0 +OP4 E001CD 0 +OP4 E001CE 0 +OP4 E001CF 0 +OP4 E001D0 0 +OP4 E001D1 0 +OP4 E001D2 0 +OP4 E001D3 0 +OP4 E001D4 0 +OP4 E001D5 0 +OP4 E001D6 0 +OP4 E001D7 0 +OP4 E001D8 0 +OP4 E001D9 0 +OP4 E001DA 0 +OP4 E001DB 0 +OP4 E001DC 0 +OP4 E001DD 0 +OP4 E001DE 0 +OP4 E001DF 0 +OP4 E001E0 0 +OP4 E001E1 0 +OP4 E001E2 0 +OP4 E001E3 0 +OP4 E001E4 0 +OP4 E001E5 0 +OP4 E001E6 0 +OP4 E001E7 0 +OP4 E001E8 0 +OP4 E001E9 0 +OP4 E001EA 0 +OP4 E001EB 0 +OP4 E001EC 0 +OP4 E001ED 0 +OP4 E001EE 0 +OP4 E001EF 0 +OP4 E001F0 0 +OP4 E001F1 0 +OP4 E001F2 0 +OP4 E001F3 0 +OP4 E001F4 0 +OP4 E001F5 0 +OP4 E001F6 0 +OP4 E001F7 0 +OP4 E001F8 0 +OP4 E001F9 0 +OP4 E001FA 0 +OP4 E001FB 0 +OP4 E001FC 0 +OP4 E001FD 0 +OP4 E001FE 0 +OP4 E001FF 0 +OP4 E00200 0 +OP4 E00201 0 +OP4 E00202 0 +OP4 E00203 0 +OP4 E00204 0 +OP4 E00205 0 +OP4 E00206 0 +OP4 E00207 0 +OP4 E00208 0 +OP4 E00209 0 +OP4 E0020A 0 +OP4 E0020B 0 +OP4 E0020C 0 +OP4 E0020D 0 +OP4 E0020E 0 +OP4 E0020F 0 +OP4 E00210 0 +OP4 E00211 0 +OP4 E00212 0 +OP4 E00213 0 +OP4 E00214 0 +OP4 E00215 0 +OP4 E00216 0 +OP4 E00217 0 +OP4 E00218 0 +OP4 E00219 0 +OP4 E0021A 0 +OP4 E0021B 0 +OP4 E0021C 0 +OP4 E0021D 0 +OP4 E0021E 0 +OP4 E0021F 0 +OP4 E00220 0 +OP4 E00221 0 +OP4 E00222 0 +OP4 E00223 0 +OP4 E00224 0 +OP4 E00225 0 +OP4 E00226 0 +OP4 E00227 0 +OP4 E00228 0 +OP4 E00229 0 +OP4 E0022A 0 +OP4 E0022B 0 +OP4 E0022C 0 +OP4 E0022D 0 +OP4 E0022E 0 +OP4 E0022F 0 +OP4 E00230 0 +OP4 E00231 0 +OP4 E00232 0 +OP4 E00233 0 +OP4 E00234 0 +OP4 E00235 0 +OP4 E00236 0 +OP4 E00237 0 +OP4 E00238 0 +OP4 E00239 0 +OP4 E0023A 0 +OP4 E0023B 0 +OP4 E0023C 0 +OP4 E0023D 0 +OP4 E0023E 0 +OP4 E0023F 0 +OP4 E00240 0 +OP4 E00241 0 +OP4 E00242 0 +OP4 E00243 0 +OP4 E00244 0 +OP4 E00245 0 +OP4 E00246 0 +OP4 E00247 0 +OP4 E00248 0 +OP4 E00249 0 +OP4 E0024A 0 +OP4 E0024B 0 +OP4 E0024C 0 +OP4 E0024D 0 +OP4 E0024E 0 +OP4 E0024F 0 +OP4 E00250 0 +OP4 E00251 0 +OP4 E00252 0 +OP4 E00253 0 +OP4 E00254 0 +OP4 E00255 0 +OP4 E00256 0 +OP4 E00257 0 +OP4 E00258 0 +OP4 E00259 0 +OP4 E0025A 0 +OP4 E0025B 0 +OP4 E0025C 0 +OP4 E0025D 0 +OP4 E0025E 0 +OP4 E0025F 0 +OP4 E00260 0 +OP4 E00261 0 +OP4 E00262 0 +OP4 E00263 0 +OP4 E00264 0 +OP4 E00265 0 +OP4 E00266 0 +OP4 E00267 0 +OP4 E00268 0 +OP4 E00269 0 +OP4 E0026A 0 +OP4 E0026B 0 +OP4 E0026C 0 +OP4 E0026D 0 +OP4 E0026E 0 +OP4 E0026F 0 +OP4 E00270 0 +OP4 E00271 0 +OP4 E00272 0 +OP4 E00273 0 +OP4 E00274 0 +OP4 E00275 0 +OP4 E00276 0 +OP4 E00277 0 +OP4 E00278 0 +OP4 E00279 0 +OP4 E0027A 0 +OP4 E0027B 0 +OP4 E0027C 0 +OP4 E0027D 0 +OP4 E0027E 0 +OP4 E0027F 0 +OP4 E00280 0 +OP4 E00281 0 +OP4 E00282 0 +OP4 E00283 0 +OP4 E00284 0 +OP4 E00285 0 +OP4 E00286 0 +OP4 E00287 0 +OP4 E00288 0 +OP4 E00289 0 +OP4 E0028A 0 +OP4 E0028B 0 +OP4 E0028C 0 +OP4 E0028D 0 +OP4 E0028E 0 +OP4 E0028F 0 +OP4 E00290 0 +OP4 E00291 0 +OP4 E00292 0 +OP4 E00293 0 +OP4 E00294 0 +OP4 E00295 0 +OP4 E00296 0 +OP4 E00297 0 +OP4 E00298 0 +OP4 E00299 0 +OP4 E0029A 0 +OP4 E0029B 0 +OP4 E0029C 0 +OP4 E0029D 0 +OP4 E0029E 0 +OP4 E0029F 0 +OP4 E002A0 0 +OP4 E002A1 0 +OP4 E002A2 0 +OP4 E002A3 0 +OP4 E002A4 0 +OP4 E002A5 0 +OP4 E002A6 0 +OP4 E002A7 0 +OP4 E002A8 0 +OP4 E002A9 0 +OP4 E002AA 0 +OP4 E002AB 0 +OP4 E002AC 0 +OP4 E002AD 0 +OP4 E002AE 0 +OP4 E002AF 0 +OP4 E002B0 0 +OP4 E002B1 0 +OP4 E002B2 0 +OP4 E002B3 0 +OP4 E002B4 0 +OP4 E002B5 0 +OP4 E002B6 0 +OP4 E002B7 0 +OP4 E002B8 0 +OP4 E002B9 0 +OP4 E002BA 0 +OP4 E002BB 0 +OP4 E002BC 0 +OP4 E002BD 0 +OP4 E002BE 0 +OP4 E002BF 0 +OP4 E002C0 0 +OP4 E002C1 0 +OP4 E002C2 0 +OP4 E002C3 0 +OP4 E002C4 0 +OP4 E002C5 0 +OP4 E002C6 0 +OP4 E002C7 0 +OP4 E002C8 0 +OP4 E002C9 0 +OP4 E002CA 0 +OP4 E002CB 0 +OP4 E002CC 0 +OP4 E002CD 0 +OP4 E002CE 0 +OP4 E002CF 0 +OP4 E002D0 0 +OP4 E002D1 0 +OP4 E002D2 0 +OP4 E002D3 0 +OP4 E002D4 0 +OP4 E002D5 0 +OP4 E002D6 0 +OP4 E002D7 0 +OP4 E002D8 0 +OP4 E002D9 0 +OP4 E002DA 0 +OP4 E002DB 0 +OP4 E002DC 0 +OP4 E002DD 0 +OP4 E002DE 0 +OP4 E002DF 0 +OP4 E002E0 0 +OP4 E002E1 0 +OP4 E002E2 0 +OP4 E002E3 0 +OP4 E002E4 0 +OP4 E002E5 0 +OP4 E002E6 0 +OP4 E002E7 0 +OP4 E002E8 0 +OP4 E002E9 0 +OP4 E002EA 0 +OP4 E002EB 0 +OP4 E002EC 0 +OP4 E002ED 0 +OP4 E002EE 0 +OP4 E002EF 0 +OP4 E002F0 0 +OP4 E002F1 0 +OP4 E002F2 0 +OP4 E002F3 0 +OP4 E002F4 0 +OP4 E002F5 0 +OP4 E002F6 0 +OP4 E002F7 0 +OP4 E002F8 0 +OP4 E002F9 0 +OP4 E002FA 0 +OP4 E002FB 0 +OP4 E002FC 0 +OP4 E002FD 0 +OP4 E002FE 0 +OP4 E002FF 0 +OP4 E00300 0 +OP4 E00301 0 +OP4 E00302 0 +OP4 E00303 0 +OP4 E00304 0 +OP4 E00305 0 +OP4 E00306 0 +OP4 E00307 0 +OP4 E00308 0 +OP4 E00309 0 +OP4 E0030A 0 +OP4 E0030B 0 +OP4 E0030C 0 +OP4 E0030D 0 +OP4 E0030E 0 +OP4 E0030F 0 +OP4 E00310 0 +OP4 E00311 0 +OP4 E00312 0 +OP4 E00313 0 +OP4 E00314 0 +OP4 E00315 0 +OP4 E00316 0 +OP4 E00317 0 +OP4 E00318 0 +OP4 E00319 0 +OP4 E0031A 0 +OP4 E0031B 0 +OP4 E0031C 0 +OP4 E0031D 0 +OP4 E0031E 0 +OP4 E0031F 0 +OP4 E00320 0 +OP4 E00321 0 +OP4 E00322 0 +OP4 E00323 0 +OP4 E00324 0 +OP4 E00325 0 +OP4 E00326 0 +OP4 E00327 0 +OP4 E00328 0 +OP4 E00329 0 +OP4 E0032A 0 +OP4 E0032B 0 +OP4 E0032C 0 +OP4 E0032D 0 +OP4 E0032E 0 +OP4 E0032F 0 +OP4 E00330 0 +OP4 E00331 0 +OP4 E00332 0 +OP4 E00333 0 +OP4 E00334 0 +OP4 E00335 0 +OP4 E00336 0 +OP4 E00337 0 +OP4 E00338 0 +OP4 E00339 0 +OP4 E0033A 0 +OP4 E0033B 0 +OP4 E0033C 0 +OP4 E0033D 0 +OP4 E0033E 0 +OP4 E0033F 0 +OP4 E00340 0 +OP4 E00341 0 +OP4 E00342 0 +OP4 E00343 0 +OP4 E00344 0 +OP4 E00345 0 +OP4 E00346 0 +OP4 E00347 0 +OP4 E00348 0 +OP4 E00349 0 +OP4 E0034A 0 +OP4 E0034B 0 +OP4 E0034C 0 +OP4 E0034D 0 +OP4 E0034E 0 +OP4 E0034F 0 +OP4 E00350 0 +OP4 E00351 0 +OP4 E00352 0 +OP4 E00353 0 +OP4 E00354 0 +OP4 E00355 0 +OP4 E00356 0 +OP4 E00357 0 +OP4 E00358 0 +OP4 E00359 0 +OP4 E0035A 0 +OP4 E0035B 0 +OP4 E0035C 0 +OP4 E0035D 0 +OP4 E0035E 0 +OP4 E0035F 0 +OP4 E00360 0 +OP4 E00361 0 +OP4 E00362 0 +OP4 E00363 0 +OP4 E00364 0 +OP4 E00365 0 +OP4 E00366 0 +OP4 E00367 0 +OP4 E00368 0 +OP4 E00369 0 +OP4 E0036A 0 +OP4 E0036B 0 +OP4 E0036C 0 +OP4 E0036D 0 +OP4 E0036E 0 +OP4 E0036F 0 +OP4 E00370 0 +OP4 E00371 0 +OP4 E00372 0 +OP4 E00373 0 +OP4 E00374 0 +OP4 E00375 0 +OP4 E00376 0 +OP4 E00377 0 +OP4 E00378 0 +OP4 E00379 0 +OP4 E0037A 0 +OP4 E0037B 0 +OP4 E0037C 0 +OP4 E0037D 0 +OP4 E0037E 0 +OP4 E0037F 0 +OP4 E00380 0 +OP4 E00381 0 +OP4 E00382 0 +OP4 E00383 0 +OP4 E00384 0 +OP4 E00385 0 +OP4 E00386 0 +OP4 E00387 0 +OP4 E00388 0 +OP4 E00389 0 +OP4 E0038A 0 +OP4 E0038B 0 +OP4 E0038C 0 +OP4 E0038D 0 +OP4 E0038E 0 +OP4 E0038F 0 +OP4 E00390 0 +OP4 E00391 0 +OP4 E00392 0 +OP4 E00393 0 +OP4 E00394 0 +OP4 E00395 0 +OP4 E00396 0 +OP4 E00397 0 +OP4 E00398 0 +OP4 E00399 0 +OP4 E0039A 0 +OP4 E0039B 0 +OP4 E0039C 0 +OP4 E0039D 0 +OP4 E0039E 0 +OP4 E0039F 0 +OP4 E003A0 0 +OP4 E003A1 0 +OP4 E003A2 0 +OP4 E003A3 0 +OP4 E003A4 0 +OP4 E003A5 0 +OP4 E003A6 0 +OP4 E003A7 0 +OP4 E003A8 0 +OP4 E003A9 0 +OP4 E003AA 0 +OP4 E003AB 0 +OP4 E003AC 0 +OP4 E003AD 0 +OP4 E003AE 0 +OP4 E003AF 0 +OP4 E003B0 0 +OP4 E003B1 0 +OP4 E003B2 0 +OP4 E003B3 0 +OP4 E003B4 0 +OP4 E003B5 0 +OP4 E003B6 0 +OP4 E003B7 0 +OP4 E003B8 0 +OP4 E003B9 0 +OP4 E003BA 0 +OP4 E003BB 0 +OP4 E003BC 0 +OP4 E003BD 0 +OP4 E003BE 0 +OP4 E003BF 0 +OP4 E003C0 0 +OP4 E003C1 0 +OP4 E003C2 0 +OP4 E003C3 0 +OP4 E003C4 0 +OP4 E003C5 0 +OP4 E003C6 0 +OP4 E003C7 0 +OP4 E003C8 0 +OP4 E003C9 0 +OP4 E003CA 0 +OP4 E003CB 0 +OP4 E003CC 0 +OP4 E003CD 0 +OP4 E003CE 0 +OP4 E003CF 0 +OP4 E003D0 0 +OP4 E003D1 0 +OP4 E003D2 0 +OP4 E003D3 0 +OP4 E003D4 0 +OP4 E003D5 0 +OP4 E003D6 0 +OP4 E003D7 0 +OP4 E003D8 0 +OP4 E003D9 0 +OP4 E003DA 0 +OP4 E003DB 0 +OP4 E003DC 0 +OP4 E003DD 0 +OP4 E003DE 0 +OP4 E003DF 0 +OP4 E003E0 0 +OP4 E003E1 0 +OP4 E003E2 0 +OP4 E003E3 0 +OP4 E003E4 0 +OP4 E003E5 0 +OP4 E003E6 0 +OP4 E003E7 0 +OP4 E003E8 0 +OP4 E003E9 0 +OP4 E003EA 0 +OP4 E003EB 0 +OP4 E003EC 0 +OP4 E003ED 0 +OP4 E003EE 0 +OP4 E003EF 0 +OP4 E003F0 0 +OP4 E003F1 0 +OP4 E003F2 0 +OP4 E003F3 0 +OP4 E003F4 0 +OP4 E003F5 0 +OP4 E003F6 0 +OP4 E003F7 0 +OP4 E003F8 0 +OP4 E003F9 0 +OP4 E003FA 0 +OP4 E003FB 0 +OP4 E003FC 0 +OP4 E003FD 0 +OP4 E003FE 0 +OP4 E003FF 0 +OP4 E00400 0 +OP4 E00401 0 +OP4 E00402 0 +OP4 E00403 0 +OP4 E00404 0 +OP4 E00405 0 +OP4 E00406 0 +OP4 E00407 0 +OP4 E00408 0 +OP4 E00409 0 +OP4 E0040A 0 +OP4 E0040B 0 +OP4 E0040C 0 +OP4 E0040D 0 +OP4 E0040E 0 +OP4 E0040F 0 +OP4 E00410 0 +OP4 E00411 0 +OP4 E00412 0 +OP4 E00413 0 +OP4 E00414 0 +OP4 E00415 0 +OP4 E00416 0 +OP4 E00417 0 +OP4 E00418 0 +OP4 E00419 0 +OP4 E0041A 0 +OP4 E0041B 0 +OP4 E0041C 0 +OP4 E0041D 0 +OP4 E0041E 0 +OP4 E0041F 0 +OP4 E00420 0 +OP4 E00421 0 +OP4 E00422 0 +OP4 E00423 0 +OP4 E00424 0 +OP4 E00425 0 +OP4 E00426 0 +OP4 E00427 0 +OP4 E00428 0 +OP4 E00429 0 +OP4 E0042A 0 +OP4 E0042B 0 +OP4 E0042C 0 +OP4 E0042D 0 +OP4 E0042E 0 +OP4 E0042F 0 +OP4 E00430 0 +OP4 E00431 0 +OP4 E00432 0 +OP4 E00433 0 +OP4 E00434 0 +OP4 E00435 0 +OP4 E00436 0 +OP4 E00437 0 +OP4 E00438 0 +OP4 E00439 0 +OP4 E0043A 0 +OP4 E0043B 0 +OP4 E0043C 0 +OP4 E0043D 0 +OP4 E0043E 0 +OP4 E0043F 0 +OP4 E00440 0 +OP4 E00441 0 +OP4 E00442 0 +OP4 E00443 0 +OP4 E00444 0 +OP4 E00445 0 +OP4 E00446 0 +OP4 E00447 0 +OP4 E00448 0 +OP4 E00449 0 +OP4 E0044A 0 +OP4 E0044B 0 +OP4 E0044C 0 +OP4 E0044D 0 +OP4 E0044E 0 +OP4 E0044F 0 +OP4 E00450 0 +OP4 E00451 0 +OP4 E00452 0 +OP4 E00453 0 +OP4 E00454 0 +OP4 E00455 0 +OP4 E00456 0 +OP4 E00457 0 +OP4 E00458 0 +OP4 E00459 0 +OP4 E0045A 0 +OP4 E0045B 0 +OP4 E0045C 0 +OP4 E0045D 0 +OP4 E0045E 0 +OP4 E0045F 0 +OP4 E00460 0 +OP4 E00461 0 +OP4 E00462 0 +OP4 E00463 0 +OP4 E00464 0 +OP4 E00465 0 +OP4 E00466 0 +OP4 E00467 0 +OP4 E00468 0 +OP4 E00469 0 +OP4 E0046A 0 +OP4 E0046B 0 +OP4 E0046C 0 +OP4 E0046D 0 +OP4 E0046E 0 +OP4 E0046F 0 +OP4 E00470 0 +OP4 E00471 0 +OP4 E00472 0 +OP4 E00473 0 +OP4 E00474 0 +OP4 E00475 0 +OP4 E00476 0 +OP4 E00477 0 +OP4 E00478 0 +OP4 E00479 0 +OP4 E0047A 0 +OP4 E0047B 0 +OP4 E0047C 0 +OP4 E0047D 0 +OP4 E0047E 0 +OP4 E0047F 0 +OP4 E00480 0 +OP4 E00481 0 +OP4 E00482 0 +OP4 E00483 0 +OP4 E00484 0 +OP4 E00485 0 +OP4 E00486 0 +OP4 E00487 0 +OP4 E00488 0 +OP4 E00489 0 +OP4 E0048A 0 +OP4 E0048B 0 +OP4 E0048C 0 +OP4 E0048D 0 +OP4 E0048E 0 +OP4 E0048F 0 +OP4 E00490 0 +OP4 E00491 0 +OP4 E00492 0 +OP4 E00493 0 +OP4 E00494 0 +OP4 E00495 0 +OP4 E00496 0 +OP4 E00497 0 +OP4 E00498 0 +OP4 E00499 0 +OP4 E0049A 0 +OP4 E0049B 0 +OP4 E0049C 0 +OP4 E0049D 0 +OP4 E0049E 0 +OP4 E0049F 0 +OP4 E004A0 0 +OP4 E004A1 0 +OP4 E004A2 0 +OP4 E004A3 0 +OP4 E004A4 0 +OP4 E004A5 0 +OP4 E004A6 0 +OP4 E004A7 0 +OP4 E004A8 0 +OP4 E004A9 0 +OP4 E004AA 0 +OP4 E004AB 0 +OP4 E004AC 0 +OP4 E004AD 0 +OP4 E004AE 0 +OP4 E004AF 0 +OP4 E004B0 0 +OP4 E004B1 0 +OP4 E004B2 0 +OP4 E004B3 0 +OP4 E004B4 0 +OP4 E004B5 0 +OP4 E004B6 0 +OP4 E004B7 0 +OP4 E004B8 0 +OP4 E004B9 0 +OP4 E004BA 0 +OP4 E004BB 0 +OP4 E004BC 0 +OP4 E004BD 0 +OP4 E004BE 0 +OP4 E004BF 0 +OP4 E004C0 0 +OP4 E004C1 0 +OP4 E004C2 0 +OP4 E004C3 0 +OP4 E004C4 0 +OP4 E004C5 0 +OP4 E004C6 0 +OP4 E004C7 0 +OP4 E004C8 0 +OP4 E004C9 0 +OP4 E004CA 0 +OP4 E004CB 0 +OP4 E004CC 0 +OP4 E004CD 0 +OP4 E004CE 0 +OP4 E004CF 0 +OP4 E004D0 0 +OP4 E004D1 0 +OP4 E004D2 0 +OP4 E004D3 0 +OP4 E004D4 0 +OP4 E004D5 0 +OP4 E004D6 0 +OP4 E004D7 0 +OP4 E004D8 0 +OP4 E004D9 0 +OP4 E004DA 0 +OP4 E004DB 0 +OP4 E004DC 0 +OP4 E004DD 0 +OP4 E004DE 0 +OP4 E004DF 0 +OP4 E004E0 0 +OP4 E004E1 0 +OP4 E004E2 0 +OP4 E004E3 0 +OP4 E004E4 0 +OP4 E004E5 0 +OP4 E004E6 0 +OP4 E004E7 0 +OP4 E004E8 0 +OP4 E004E9 0 +OP4 E004EA 0 +OP4 E004EB 0 +OP4 E004EC 0 +OP4 E004ED 0 +OP4 E004EE 0 +OP4 E004EF 0 +OP4 E004F0 0 +OP4 E004F1 0 +OP4 E004F2 0 +OP4 E004F3 0 +OP4 E004F4 0 +OP4 E004F5 0 +OP4 E004F6 0 +OP4 E004F7 0 +OP4 E004F8 0 +OP4 E004F9 0 +OP4 E004FA 0 +OP4 E004FB 0 +OP4 E004FC 0 +OP4 E004FD 0 +OP4 E004FE 0 +OP4 E004FF 0 +OP4 E00500 0 +OP4 E00501 0 +OP4 E00502 0 +OP4 E00503 0 +OP4 E00504 0 +OP4 E00505 0 +OP4 E00506 0 +OP4 E00507 0 +OP4 E00508 0 +OP4 E00509 0 +OP4 E0050A 0 +OP4 E0050B 0 +OP4 E0050C 0 +OP4 E0050D 0 +OP4 E0050E 0 +OP4 E0050F 0 +OP4 E00510 0 +OP4 E00511 0 +OP4 E00512 0 +OP4 E00513 0 +OP4 E00514 0 +OP4 E00515 0 +OP4 E00516 0 +OP4 E00517 0 +OP4 E00518 0 +OP4 E00519 0 +OP4 E0051A 0 +OP4 E0051B 0 +OP4 E0051C 0 +OP4 E0051D 0 +OP4 E0051E 0 +OP4 E0051F 0 +OP4 E00520 0 +OP4 E00521 0 +OP4 E00522 0 +OP4 E00523 0 +OP4 E00524 0 +OP4 E00525 0 +OP4 E00526 0 +OP4 E00527 0 +OP4 E00528 0 +OP4 E00529 0 +OP4 E0052A 0 +OP4 E0052B 0 +OP4 E0052C 0 +OP4 E0052D 0 +OP4 E0052E 0 +OP4 E0052F 0 +OP4 E00530 0 +OP4 E00531 0 +OP4 E00532 0 +OP4 E00533 0 +OP4 E00534 0 +OP4 E00535 0 +OP4 E00536 0 +OP4 E00537 0 +OP4 E00538 0 +OP4 E00539 0 +OP4 E0053A 0 +OP4 E0053B 0 +OP4 E0053C 0 +OP4 E0053D 0 +OP4 E0053E 0 +OP4 E0053F 0 +OP4 E00540 0 +OP4 E00541 0 +OP4 E00542 0 +OP4 E00543 0 +OP4 E00544 0 +OP4 E00545 0 +OP4 E00546 0 +OP4 E00547 0 +OP4 E00548 0 +OP4 E00549 0 +OP4 E0054A 0 +OP4 E0054B 0 +OP4 E0054C 0 +OP4 E0054D 0 +OP4 E0054E 0 +OP4 E0054F 0 +OP4 E00550 0 +OP4 E00551 0 +OP4 E00552 0 +OP4 E00553 0 +OP4 E00554 0 +OP4 E00555 0 +OP4 E00556 0 +OP4 E00557 0 +OP4 E00558 0 +OP4 E00559 0 +OP4 E0055A 0 +OP4 E0055B 0 +OP4 E0055C 0 +OP4 E0055D 0 +OP4 E0055E 0 +OP4 E0055F 0 +OP4 E00560 0 +OP4 E00561 0 +OP4 E00562 0 +OP4 E00563 0 +OP4 E00564 0 +OP4 E00565 0 +OP4 E00566 0 +OP4 E00567 0 +OP4 E00568 0 +OP4 E00569 0 +OP4 E0056A 0 +OP4 E0056B 0 +OP4 E0056C 0 +OP4 E0056D 0 +OP4 E0056E 0 +OP4 E0056F 0 +OP4 E00570 0 +OP4 E00571 0 +OP4 E00572 0 +OP4 E00573 0 +OP4 E00574 0 +OP4 E00575 0 +OP4 E00576 0 +OP4 E00577 0 +OP4 E00578 0 +OP4 E00579 0 +OP4 E0057A 0 +OP4 E0057B 0 +OP4 E0057C 0 +OP4 E0057D 0 +OP4 E0057E 0 +OP4 E0057F 0 +OP4 E00580 0 +OP4 E00581 0 +OP4 E00582 0 +OP4 E00583 0 +OP4 E00584 0 +OP4 E00585 0 +OP4 E00586 0 +OP4 E00587 0 +OP4 E00588 0 +OP4 E00589 0 +OP4 E0058A 0 +OP4 E0058B 0 +OP4 E0058C 0 +OP4 E0058D 0 +OP4 E0058E 0 +OP4 E0058F 0 +OP4 E00590 0 +OP4 E00591 0 +OP4 E00592 0 +OP4 E00593 0 +OP4 E00594 0 +OP4 E00595 0 +OP4 E00596 0 +OP4 E00597 0 +OP4 E00598 0 +OP4 E00599 0 +OP4 E0059A 0 +OP4 E0059B 0 +OP4 E0059C 0 +OP4 E0059D 0 +OP4 E0059E 0 +OP4 E0059F 0 +OP4 E005A0 0 +OP4 E005A1 0 +OP4 E005A2 0 +OP4 E005A3 0 +OP4 E005A4 0 +OP4 E005A5 0 +OP4 E005A6 0 +OP4 E005A7 0 +OP4 E005A8 0 +OP4 E005A9 0 +OP4 E005AA 0 +OP4 E005AB 0 +OP4 E005AC 0 +OP4 E005AD 0 +OP4 E005AE 0 +OP4 E005AF 0 +OP4 E005B0 0 +OP4 E005B1 0 +OP4 E005B2 0 +OP4 E005B3 0 +OP4 E005B4 0 +OP4 E005B5 0 +OP4 E005B6 0 +OP4 E005B7 0 +OP4 E005B8 0 +OP4 E005B9 0 +OP4 E005BA 0 +OP4 E005BB 0 +OP4 E005BC 0 +OP4 E005BD 0 +OP4 E005BE 0 +OP4 E005BF 0 +OP4 E005C0 0 +OP4 E005C1 0 +OP4 E005C2 0 +OP4 E005C3 0 +OP4 E005C4 0 +OP4 E005C5 0 +OP4 E005C6 0 +OP4 E005C7 0 +OP4 E005C8 0 +OP4 E005C9 0 +OP4 E005CA 0 +OP4 E005CB 0 +OP4 E005CC 0 +OP4 E005CD 0 +OP4 E005CE 0 +OP4 E005CF 0 +OP4 E005D0 0 +OP4 E005D1 0 +OP4 E005D2 0 +OP4 E005D3 0 +OP4 E005D4 0 +OP4 E005D5 0 +OP4 E005D6 0 +OP4 E005D7 0 +OP4 E005D8 0 +OP4 E005D9 0 +OP4 E005DA 0 +OP4 E005DB 0 +OP4 E005DC 0 +OP4 E005DD 0 +OP4 E005DE 0 +OP4 E005DF 0 +OP4 E005E0 0 +OP4 E005E1 0 +OP4 E005E2 0 +OP4 E005E3 0 +OP4 E005E4 0 +OP4 E005E5 0 +OP4 E005E6 0 +OP4 E005E7 0 +OP4 E005E8 0 +OP4 E005E9 0 +OP4 E005EA 0 +OP4 E005EB 0 +OP4 E005EC 0 +OP4 E005ED 0 +OP4 E005EE 0 +OP4 E005EF 0 +OP4 E005F0 0 +OP4 E005F1 0 +OP4 E005F2 0 +OP4 E005F3 0 +OP4 E005F4 0 +OP4 E005F5 0 +OP4 E005F6 0 +OP4 E005F7 0 +OP4 E005F8 0 +OP4 E005F9 0 +OP4 E005FA 0 +OP4 E005FB 0 +OP4 E005FC 0 +OP4 E005FD 0 +OP4 E005FE 0 +OP4 E005FF 0 +OP4 E00600 0 +OP4 E00601 0 +OP4 E00602 0 +OP4 E00603 0 +OP4 E00604 0 +OP4 E00605 0 +OP4 E00606 0 +OP4 E00607 0 +OP4 E00608 0 +OP4 E00609 0 +OP4 E0060A 0 +OP4 E0060B 0 +OP4 E0060C 0 +OP4 E0060D 0 +OP4 E0060E 0 +OP4 E0060F 0 +OP4 E00610 0 +OP4 E00611 0 +OP4 E00612 0 +OP4 E00613 0 +OP4 E00614 0 +OP4 E00615 0 +OP4 E00616 0 +OP4 E00617 0 +OP4 E00618 0 +OP4 E00619 0 +OP4 E0061A 0 +OP4 E0061B 0 +OP4 E0061C 0 +OP4 E0061D 0 +OP4 E0061E 0 +OP4 E0061F 0 +OP4 E00620 0 +OP4 E00621 0 +OP4 E00622 0 +OP4 E00623 0 +OP4 E00624 0 +OP4 E00625 0 +OP4 E00626 0 +OP4 E00627 0 +OP4 E00628 0 +OP4 E00629 0 +OP4 E0062A 0 +OP4 E0062B 0 +OP4 E0062C 0 +OP4 E0062D 0 +OP4 E0062E 0 +OP4 E0062F 0 +OP4 E00630 0 +OP4 E00631 0 +OP4 E00632 0 +OP4 E00633 0 +OP4 E00634 0 +OP4 E00635 0 +OP4 E00636 0 +OP4 E00637 0 +OP4 E00638 0 +OP4 E00639 0 +OP4 E0063A 0 +OP4 E0063B 0 +OP4 E0063C 0 +OP4 E0063D 0 +OP4 E0063E 0 +OP4 E0063F 0 +OP4 E00640 0 +OP4 E00641 0 +OP4 E00642 0 +OP4 E00643 0 +OP4 E00644 0 +OP4 E00645 0 +OP4 E00646 0 +OP4 E00647 0 +OP4 E00648 0 +OP4 E00649 0 +OP4 E0064A 0 +OP4 E0064B 0 +OP4 E0064C 0 +OP4 E0064D 0 +OP4 E0064E 0 +OP4 E0064F 0 +OP4 E00650 0 +OP4 E00651 0 +OP4 E00652 0 +OP4 E00653 0 +OP4 E00654 0 +OP4 E00655 0 +OP4 E00656 0 +OP4 E00657 0 +OP4 E00658 0 +OP4 E00659 0 +OP4 E0065A 0 +OP4 E0065B 0 +OP4 E0065C 0 +OP4 E0065D 0 +OP4 E0065E 0 +OP4 E0065F 0 +OP4 E00660 0 +OP4 E00661 0 +OP4 E00662 0 +OP4 E00663 0 +OP4 E00664 0 +OP4 E00665 0 +OP4 E00666 0 +OP4 E00667 0 +OP4 E00668 0 +OP4 E00669 0 +OP4 E0066A 0 +OP4 E0066B 0 +OP4 E0066C 0 +OP4 E0066D 0 +OP4 E0066E 0 +OP4 E0066F 0 +OP4 E00670 0 +OP4 E00671 0 +OP4 E00672 0 +OP4 E00673 0 +OP4 E00674 0 +OP4 E00675 0 +OP4 E00676 0 +OP4 E00677 0 +OP4 E00678 0 +OP4 E00679 0 +OP4 E0067A 0 +OP4 E0067B 0 +OP4 E0067C 0 +OP4 E0067D 0 +OP4 E0067E 0 +OP4 E0067F 0 +OP4 E00680 0 +OP4 E00681 0 +OP4 E00682 0 +OP4 E00683 0 +OP4 E00684 0 +OP4 E00685 0 +OP4 E00686 0 +OP4 E00687 0 +OP4 E00688 0 +OP4 E00689 0 +OP4 E0068A 0 +OP4 E0068B 0 +OP4 E0068C 0 +OP4 E0068D 0 +OP4 E0068E 0 +OP4 E0068F 0 +OP4 E00690 0 +OP4 E00691 0 +OP4 E00692 0 +OP4 E00693 0 +OP4 E00694 0 +OP4 E00695 0 +OP4 E00696 0 +OP4 E00697 0 +OP4 E00698 0 +OP4 E00699 0 +OP4 E0069A 0 +OP4 E0069B 0 +OP4 E0069C 0 +OP4 E0069D 0 +OP4 E0069E 0 +OP4 E0069F 0 +OP4 E006A0 0 +OP4 E006A1 0 +OP4 E006A2 0 +OP4 E006A3 0 +OP4 E006A4 0 +OP4 E006A5 0 +OP4 E006A6 0 +OP4 E006A7 0 +OP4 E006A8 0 +OP4 E006A9 0 +OP4 E006AA 0 +OP4 E006AB 0 +OP4 E006AC 0 +OP4 E006AD 0 +OP4 E006AE 0 +OP4 E006AF 0 +OP4 E006B0 0 +OP4 E006B1 0 +OP4 E006B2 0 +OP4 E006B3 0 +OP4 E006B4 0 +OP4 E006B5 0 +OP4 E006B6 0 +OP4 E006B7 0 +OP4 E006B8 0 +OP4 E006B9 0 +OP4 E006BA 0 +OP4 E006BB 0 +OP4 E006BC 0 +OP4 E006BD 0 +OP4 E006BE 0 +OP4 E006BF 0 +OP4 E006C0 0 +OP4 E006C1 0 +OP4 E006C2 0 +OP4 E006C3 0 +OP4 E006C4 0 +OP4 E006C5 0 +OP4 E006C6 0 +OP4 E006C7 0 +OP4 E006C8 0 +OP4 E006C9 0 +OP4 E006CA 0 +OP4 E006CB 0 +OP4 E006CC 0 +OP4 E006CD 0 +OP4 E006CE 0 +OP4 E006CF 0 +OP4 E006D0 0 +OP4 E006D1 0 +OP4 E006D2 0 +OP4 E006D3 0 +OP4 E006D4 0 +OP4 E006D5 0 +OP4 E006D6 0 +OP4 E006D7 0 +OP4 E006D8 0 +OP4 E006D9 0 +OP4 E006DA 0 +OP4 E006DB 0 +OP4 E006DC 0 +OP4 E006DD 0 +OP4 E006DE 0 +OP4 E006DF 0 +OP4 E006E0 0 +OP4 E006E1 0 +OP4 E006E2 0 +OP4 E006E3 0 +OP4 E006E4 0 +OP4 E006E5 0 +OP4 E006E6 0 +OP4 E006E7 0 +OP4 E006E8 0 +OP4 E006E9 0 +OP4 E006EA 0 +OP4 E006EB 0 +OP4 E006EC 0 +OP4 E006ED 0 +OP4 E006EE 0 +OP4 E006EF 0 +OP4 E006F0 0 +OP4 E006F1 0 +OP4 E006F2 0 +OP4 E006F3 0 +OP4 E006F4 0 +OP4 E006F5 0 +OP4 E006F6 0 +OP4 E006F7 0 +OP4 E006F8 0 +OP4 E006F9 0 +OP4 E006FA 0 +OP4 E006FB 0 +OP4 E006FC 0 +OP4 E006FD 0 +OP4 E006FE 0 +OP4 E006FF 0 +OP4 E00700 0 +OP4 E00701 0 +OP4 E00702 0 +OP4 E00703 0 +OP4 E00704 0 +OP4 E00705 0 +OP4 E00706 0 +OP4 E00707 0 +OP4 E00708 0 +OP4 E00709 0 +OP4 E0070A 0 +OP4 E0070B 0 +OP4 E0070C 0 +OP4 E0070D 0 +OP4 E0070E 0 +OP4 E0070F 0 +OP4 E00710 0 +OP4 E00711 0 +OP4 E00712 0 +OP4 E00713 0 +OP4 E00714 0 +OP4 E00715 0 +OP4 E00716 0 +OP4 E00717 0 +OP4 E00718 0 +OP4 E00719 0 +OP4 E0071A 0 +OP4 E0071B 0 +OP4 E0071C 0 +OP4 E0071D 0 +OP4 E0071E 0 +OP4 E0071F 0 +OP4 E00720 0 +OP4 E00721 0 +OP4 E00722 0 +OP4 E00723 0 +OP4 E00724 0 +OP4 E00725 0 +OP4 E00726 0 +OP4 E00727 0 +OP4 E00728 0 +OP4 E00729 0 +OP4 E0072A 0 +OP4 E0072B 0 +OP4 E0072C 0 +OP4 E0072D 0 +OP4 E0072E 0 +OP4 E0072F 0 +OP4 E00730 0 +OP4 E00731 0 +OP4 E00732 0 +OP4 E00733 0 +OP4 E00734 0 +OP4 E00735 0 +OP4 E00736 0 +OP4 E00737 0 +OP4 E00738 0 +OP4 E00739 0 +OP4 E0073A 0 +OP4 E0073B 0 +OP4 E0073C 0 +OP4 E0073D 0 +OP4 E0073E 0 +OP4 E0073F 0 +OP4 E00740 0 +OP4 E00741 0 +OP4 E00742 0 +OP4 E00743 0 +OP4 E00744 0 +OP4 E00745 0 +OP4 E00746 0 +OP4 E00747 0 +OP4 E00748 0 +OP4 E00749 0 +OP4 E0074A 0 +OP4 E0074B 0 +OP4 E0074C 0 +OP4 E0074D 0 +OP4 E0074E 0 +OP4 E0074F 0 +OP4 E00750 0 +OP4 E00751 0 +OP4 E00752 0 +OP4 E00753 0 +OP4 E00754 0 +OP4 E00755 0 +OP4 E00756 0 +OP4 E00757 0 +OP4 E00758 0 +OP4 E00759 0 +OP4 E0075A 0 +OP4 E0075B 0 +OP4 E0075C 0 +OP4 E0075D 0 +OP4 E0075E 0 +OP4 E0075F 0 +OP4 E00760 0 +OP4 E00761 0 +OP4 E00762 0 +OP4 E00763 0 +OP4 E00764 0 +OP4 E00765 0 +OP4 E00766 0 +OP4 E00767 0 +OP4 E00768 0 +OP4 E00769 0 +OP4 E0076A 0 +OP4 E0076B 0 +OP4 E0076C 0 +OP4 E0076D 0 +OP4 E0076E 0 +OP4 E0076F 0 +OP4 E00770 0 +OP4 E00771 0 +OP4 E00772 0 +OP4 E00773 0 +OP4 E00774 0 +OP4 E00775 0 +OP4 E00776 0 +OP4 E00777 0 +OP4 E00778 0 +OP4 E00779 0 +OP4 E0077A 0 +OP4 E0077B 0 +OP4 E0077C 0 +OP4 E0077D 0 +OP4 E0077E 0 +OP4 E0077F 0 +OP4 E00780 0 +OP4 E00781 0 +OP4 E00782 0 +OP4 E00783 0 +OP4 E00784 0 +OP4 E00785 0 +OP4 E00786 0 +OP4 E00787 0 +OP4 E00788 0 +OP4 E00789 0 +OP4 E0078A 0 +OP4 E0078B 0 +OP4 E0078C 0 +OP4 E0078D 0 +OP4 E0078E 0 +OP4 E0078F 0 +OP4 E00790 0 +OP4 E00791 0 +OP4 E00792 0 +OP4 E00793 0 +OP4 E00794 0 +OP4 E00795 0 +OP4 E00796 0 +OP4 E00797 0 +OP4 E00798 0 +OP4 E00799 0 +OP4 E0079A 0 +OP4 E0079B 0 +OP4 E0079C 0 +OP4 E0079D 0 +OP4 E0079E 0 +OP4 E0079F 0 +OP4 E007A0 0 +OP4 E007A1 0 +OP4 E007A2 0 +OP4 E007A3 0 +OP4 E007A4 0 +OP4 E007A5 0 +OP4 E007A6 0 +OP4 E007A7 0 +OP4 E007A8 0 +OP4 E007A9 0 +OP4 E007AA 0 +OP4 E007AB 0 +OP4 E007AC 0 +OP4 E007AD 0 +OP4 E007AE 0 +OP4 E007AF 0 +OP4 E007B0 0 +OP4 E007B1 0 +OP4 E007B2 0 +OP4 E007B3 0 +OP4 E007B4 0 +OP4 E007B5 0 +OP4 E007B6 0 +OP4 E007B7 0 +OP4 E007B8 0 +OP4 E007B9 0 +OP4 E007BA 0 +OP4 E007BB 0 +OP4 E007BC 0 +OP4 E007BD 0 +OP4 E007BE 0 +OP4 E007BF 0 +OP4 E007C0 0 +OP4 E007C1 0 +OP4 E007C2 0 +OP4 E007C3 0 +OP4 E007C4 0 +OP4 E007C5 0 +OP4 E007C6 0 +OP4 E007C7 0 +OP4 E007C8 0 +OP4 E007C9 0 +OP4 E007CA 0 +OP4 E007CB 0 +OP4 E007CC 0 +OP4 E007CD 0 +OP4 E007CE 0 +OP4 E007CF 0 +OP4 E007D0 0 +OP4 E007D1 0 +OP4 E007D2 0 +OP4 E007D3 0 +OP4 E007D4 0 +OP4 E007D5 0 +OP4 E007D6 0 +OP4 E007D7 0 +OP4 E007D8 0 +OP4 E007D9 0 +OP4 E007DA 0 +OP4 E007DB 0 +OP4 E007DC 0 +OP4 E007DD 0 +OP4 E007DE 0 +OP4 E007DF 0 +OP4 E007E0 0 +OP4 E007E1 0 +OP4 E007E2 0 +OP4 E007E3 0 +OP4 E007E4 0 +OP4 E007E5 0 +OP4 E007E6 0 +OP4 E007E7 0 +OP4 E007E8 0 +OP4 E007E9 0 +OP4 E007EA 0 +OP4 E007EB 0 +OP4 E007EC 0 +OP4 E007ED 0 +OP4 E007EE 0 +OP4 E007EF 0 +OP4 E007F0 0 +OP4 E007F1 0 +OP4 E007F2 0 +OP4 E007F3 0 +OP4 E007F4 0 +OP4 E007F5 0 +OP4 E007F6 0 +OP4 E007F7 0 +OP4 E007F8 0 +OP4 E007F9 0 +OP4 E007FA 0 +OP4 E007FB 0 +OP4 E007FC 0 +OP4 E007FD 0 +OP4 E007FE 0 +OP4 E007FF 0 +OP4 E00800 0 +OP4 E00801 0 +OP4 E00802 0 +OP4 E00803 0 +OP4 E00804 0 +OP4 E00805 0 +OP4 E00806 0 +OP4 E00807 0 +OP4 E00808 0 +OP4 E00809 0 +OP4 E0080A 0 +OP4 E0080B 0 +OP4 E0080C 0 +OP4 E0080D 0 +OP4 E0080E 0 +OP4 E0080F 0 +OP4 E00810 0 +OP4 E00811 0 +OP4 E00812 0 +OP4 E00813 0 +OP4 E00814 0 +OP4 E00815 0 +OP4 E00816 0 +OP4 E00817 0 +OP4 E00818 0 +OP4 E00819 0 +OP4 E0081A 0 +OP4 E0081B 0 +OP4 E0081C 0 +OP4 E0081D 0 +OP4 E0081E 0 +OP4 E0081F 0 +OP4 E00820 0 +OP4 E00821 0 +OP4 E00822 0 +OP4 E00823 0 +OP4 E00824 0 +OP4 E00825 0 +OP4 E00826 0 +OP4 E00827 0 +OP4 E00828 0 +OP4 E00829 0 +OP4 E0082A 0 +OP4 E0082B 0 +OP4 E0082C 0 +OP4 E0082D 0 +OP4 E0082E 0 +OP4 E0082F 0 +OP4 E00830 0 +OP4 E00831 0 +OP4 E00832 0 +OP4 E00833 0 +OP4 E00834 0 +OP4 E00835 0 +OP4 E00836 0 +OP4 E00837 0 +OP4 E00838 0 +OP4 E00839 0 +OP4 E0083A 0 +OP4 E0083B 0 +OP4 E0083C 0 +OP4 E0083D 0 +OP4 E0083E 0 +OP4 E0083F 0 +OP4 E00840 0 +OP4 E00841 0 +OP4 E00842 0 +OP4 E00843 0 +OP4 E00844 0 +OP4 E00845 0 +OP4 E00846 0 +OP4 E00847 0 +OP4 E00848 0 +OP4 E00849 0 +OP4 E0084A 0 +OP4 E0084B 0 +OP4 E0084C 0 +OP4 E0084D 0 +OP4 E0084E 0 +OP4 E0084F 0 +OP4 E00850 0 +OP4 E00851 0 +OP4 E00852 0 +OP4 E00853 0 +OP4 E00854 0 +OP4 E00855 0 +OP4 E00856 0 +OP4 E00857 0 +OP4 E00858 0 +OP4 E00859 0 +OP4 E0085A 0 +OP4 E0085B 0 +OP4 E0085C 0 +OP4 E0085D 0 +OP4 E0085E 0 +OP4 E0085F 0 +OP4 E00860 0 +OP4 E00861 0 +OP4 E00862 0 +OP4 E00863 0 +OP4 E00864 0 +OP4 E00865 0 +OP4 E00866 0 +OP4 E00867 0 +OP4 E00868 0 +OP4 E00869 0 +OP4 E0086A 0 +OP4 E0086B 0 +OP4 E0086C 0 +OP4 E0086D 0 +OP4 E0086E 0 +OP4 E0086F 0 +OP4 E00870 0 +OP4 E00871 0 +OP4 E00872 0 +OP4 E00873 0 +OP4 E00874 0 +OP4 E00875 0 +OP4 E00876 0 +OP4 E00877 0 +OP4 E00878 0 +OP4 E00879 0 +OP4 E0087A 0 +OP4 E0087B 0 +OP4 E0087C 0 +OP4 E0087D 0 +OP4 E0087E 0 +OP4 E0087F 0 +OP4 E00880 0 +OP4 E00881 0 +OP4 E00882 0 +OP4 E00883 0 +OP4 E00884 0 +OP4 E00885 0 +OP4 E00886 0 +OP4 E00887 0 +OP4 E00888 0 +OP4 E00889 0 +OP4 E0088A 0 +OP4 E0088B 0 +OP4 E0088C 0 +OP4 E0088D 0 +OP4 E0088E 0 +OP4 E0088F 0 +OP4 E00890 0 +OP4 E00891 0 +OP4 E00892 0 +OP4 E00893 0 +OP4 E00894 0 +OP4 E00895 0 +OP4 E00896 0 +OP4 E00897 0 +OP4 E00898 0 +OP4 E00899 0 +OP4 E0089A 0 +OP4 E0089B 0 +OP4 E0089C 0 +OP4 E0089D 0 +OP4 E0089E 0 +OP4 E0089F 0 +OP4 E008A0 0 +OP4 E008A1 0 +OP4 E008A2 0 +OP4 E008A3 0 +OP4 E008A4 0 +OP4 E008A5 0 +OP4 E008A6 0 +OP4 E008A7 0 +OP4 E008A8 0 +OP4 E008A9 0 +OP4 E008AA 0 +OP4 E008AB 0 +OP4 E008AC 0 +OP4 E008AD 0 +OP4 E008AE 0 +OP4 E008AF 0 +OP4 E008B0 0 +OP4 E008B1 0 +OP4 E008B2 0 +OP4 E008B3 0 +OP4 E008B4 0 +OP4 E008B5 0 +OP4 E008B6 0 +OP4 E008B7 0 +OP4 E008B8 0 +OP4 E008B9 0 +OP4 E008BA 0 +OP4 E008BB 0 +OP4 E008BC 0 +OP4 E008BD 0 +OP4 E008BE 0 +OP4 E008BF 0 +OP4 E008C0 0 +OP4 E008C1 0 +OP4 E008C2 0 +OP4 E008C3 0 +OP4 E008C4 0 +OP4 E008C5 0 +OP4 E008C6 0 +OP4 E008C7 0 +OP4 E008C8 0 +OP4 E008C9 0 +OP4 E008CA 0 +OP4 E008CB 0 +OP4 E008CC 0 +OP4 E008CD 0 +OP4 E008CE 0 +OP4 E008CF 0 +OP4 E008D0 0 +OP4 E008D1 0 +OP4 E008D2 0 +OP4 E008D3 0 +OP4 E008D4 0 +OP4 E008D5 0 +OP4 E008D6 0 +OP4 E008D7 0 +OP4 E008D8 0 +OP4 E008D9 0 +OP4 E008DA 0 +OP4 E008DB 0 +OP4 E008DC 0 +OP4 E008DD 0 +OP4 E008DE 0 +OP4 E008DF 0 +OP4 E008E0 0 +OP4 E008E1 0 +OP4 E008E2 0 +OP4 E008E3 0 +OP4 E008E4 0 +OP4 E008E5 0 +OP4 E008E6 0 +OP4 E008E7 0 +OP4 E008E8 0 +OP4 E008E9 0 +OP4 E008EA 0 +OP4 E008EB 0 +OP4 E008EC 0 +OP4 E008ED 0 +OP4 E008EE 0 +OP4 E008EF 0 +OP4 E008F0 0 +OP4 E008F1 0 +OP4 E008F2 0 +OP4 E008F3 0 +OP4 E008F4 0 +OP4 E008F5 0 +OP4 E008F6 0 +OP4 E008F7 0 +OP4 E008F8 0 +OP4 E008F9 0 +OP4 E008FA 0 +OP4 E008FB 0 +OP4 E008FC 0 +OP4 E008FD 0 +OP4 E008FE 0 +OP4 E008FF 0 +OP4 E00900 0 +OP4 E00901 0 +OP4 E00902 0 +OP4 E00903 0 +OP4 E00904 0 +OP4 E00905 0 +OP4 E00906 0 +OP4 E00907 0 +OP4 E00908 0 +OP4 E00909 0 +OP4 E0090A 0 +OP4 E0090B 0 +OP4 E0090C 0 +OP4 E0090D 0 +OP4 E0090E 0 +OP4 E0090F 0 +OP4 E00910 0 +OP4 E00911 0 +OP4 E00912 0 +OP4 E00913 0 +OP4 E00914 0 +OP4 E00915 0 +OP4 E00916 0 +OP4 E00917 0 +OP4 E00918 0 +OP4 E00919 0 +OP4 E0091A 0 +OP4 E0091B 0 +OP4 E0091C 0 +OP4 E0091D 0 +OP4 E0091E 0 +OP4 E0091F 0 +OP4 E00920 0 +OP4 E00921 0 +OP4 E00922 0 +OP4 E00923 0 +OP4 E00924 0 +OP4 E00925 0 +OP4 E00926 0 +OP4 E00927 0 +OP4 E00928 0 +OP4 E00929 0 +OP4 E0092A 0 +OP4 E0092B 0 +OP4 E0092C 0 +OP4 E0092D 0 +OP4 E0092E 0 +OP4 E0092F 0 +OP4 E00930 0 +OP4 E00931 0 +OP4 E00932 0 +OP4 E00933 0 +OP4 E00934 0 +OP4 E00935 0 +OP4 E00936 0 +OP4 E00937 0 +OP4 E00938 0 +OP4 E00939 0 +OP4 E0093A 0 +OP4 E0093B 0 +OP4 E0093C 0 +OP4 E0093D 0 +OP4 E0093E 0 +OP4 E0093F 0 +OP4 E00940 0 +OP4 E00941 0 +OP4 E00942 0 +OP4 E00943 0 +OP4 E00944 0 +OP4 E00945 0 +OP4 E00946 0 +OP4 E00947 0 +OP4 E00948 0 +OP4 E00949 0 +OP4 E0094A 0 +OP4 E0094B 0 +OP4 E0094C 0 +OP4 E0094D 0 +OP4 E0094E 0 +OP4 E0094F 0 +OP4 E00950 0 +OP4 E00951 0 +OP4 E00952 0 +OP4 E00953 0 +OP4 E00954 0 +OP4 E00955 0 +OP4 E00956 0 +OP4 E00957 0 +OP4 E00958 0 +OP4 E00959 0 +OP4 E0095A 0 +OP4 E0095B 0 +OP4 E0095C 0 +OP4 E0095D 0 +OP4 E0095E 0 +OP4 E0095F 0 +OP4 E00960 0 +OP4 E00961 0 +OP4 E00962 0 +OP4 E00963 0 +OP4 E00964 0 +OP4 E00965 0 +OP4 E00966 0 +OP4 E00967 0 +OP4 E00968 0 +OP4 E00969 0 +OP4 E0096A 0 +OP4 E0096B 0 +OP4 E0096C 0 +OP4 E0096D 0 +OP4 E0096E 0 +OP4 E0096F 0 +OP4 E00970 0 +OP4 E00971 0 +OP4 E00972 0 +OP4 E00973 0 +OP4 E00974 0 +OP4 E00975 0 +OP4 E00976 0 +OP4 E00977 0 +OP4 E00978 0 +OP4 E00979 0 +OP4 E0097A 0 +OP4 E0097B 0 +OP4 E0097C 0 +OP4 E0097D 0 +OP4 E0097E 0 +OP4 E0097F 0 +OP4 E00980 0 +OP4 E00981 0 +OP4 E00982 0 +OP4 E00983 0 +OP4 E00984 0 +OP4 E00985 0 +OP4 E00986 0 +OP4 E00987 0 +OP4 E00988 0 +OP4 E00989 0 +OP4 E0098A 0 +OP4 E0098B 0 +OP4 E0098C 0 +OP4 E0098D 0 +OP4 E0098E 0 +OP4 E0098F 0 +OP4 E00990 0 +OP4 E00991 0 +OP4 E00992 0 +OP4 E00993 0 +OP4 E00994 0 +OP4 E00995 0 +OP4 E00996 0 +OP4 E00997 0 +OP4 E00998 0 +OP4 E00999 0 +OP4 E0099A 0 +OP4 E0099B 0 +OP4 E0099C 0 +OP4 E0099D 0 +OP4 E0099E 0 +OP4 E0099F 0 +OP4 E009A0 0 +OP4 E009A1 0 +OP4 E009A2 0 +OP4 E009A3 0 +OP4 E009A4 0 +OP4 E009A5 0 +OP4 E009A6 0 +OP4 E009A7 0 +OP4 E009A8 0 +OP4 E009A9 0 +OP4 E009AA 0 +OP4 E009AB 0 +OP4 E009AC 0 +OP4 E009AD 0 +OP4 E009AE 0 +OP4 E009AF 0 +OP4 E009B0 0 +OP4 E009B1 0 +OP4 E009B2 0 +OP4 E009B3 0 +OP4 E009B4 0 +OP4 E009B5 0 +OP4 E009B6 0 +OP4 E009B7 0 +OP4 E009B8 0 +OP4 E009B9 0 +OP4 E009BA 0 +OP4 E009BB 0 +OP4 E009BC 0 +OP4 E009BD 0 +OP4 E009BE 0 +OP4 E009BF 0 +OP4 E009C0 0 +OP4 E009C1 0 +OP4 E009C2 0 +OP4 E009C3 0 +OP4 E009C4 0 +OP4 E009C5 0 +OP4 E009C6 0 +OP4 E009C7 0 +OP4 E009C8 0 +OP4 E009C9 0 +OP4 E009CA 0 +OP4 E009CB 0 +OP4 E009CC 0 +OP4 E009CD 0 +OP4 E009CE 0 +OP4 E009CF 0 +OP4 E009D0 0 +OP4 E009D1 0 +OP4 E009D2 0 +OP4 E009D3 0 +OP4 E009D4 0 +OP4 E009D5 0 +OP4 E009D6 0 +OP4 E009D7 0 +OP4 E009D8 0 +OP4 E009D9 0 +OP4 E009DA 0 +OP4 E009DB 0 +OP4 E009DC 0 +OP4 E009DD 0 +OP4 E009DE 0 +OP4 E009DF 0 +OP4 E009E0 0 +OP4 E009E1 0 +OP4 E009E2 0 +OP4 E009E3 0 +OP4 E009E4 0 +OP4 E009E5 0 +OP4 E009E6 0 +OP4 E009E7 0 +OP4 E009E8 0 +OP4 E009E9 0 +OP4 E009EA 0 +OP4 E009EB 0 +OP4 E009EC 0 +OP4 E009ED 0 +OP4 E009EE 0 +OP4 E009EF 0 +OP4 E009F0 0 +OP4 E009F1 0 +OP4 E009F2 0 +OP4 E009F3 0 +OP4 E009F4 0 +OP4 E009F5 0 +OP4 E009F6 0 +OP4 E009F7 0 +OP4 E009F8 0 +OP4 E009F9 0 +OP4 E009FA 0 +OP4 E009FB 0 +OP4 E009FC 0 +OP4 E009FD 0 +OP4 E009FE 0 +OP4 E009FF 0 +OP4 E00A00 0 +OP4 E00A01 0 +OP4 E00A02 0 +OP4 E00A03 0 +OP4 E00A04 0 +OP4 E00A05 0 +OP4 E00A06 0 +OP4 E00A07 0 +OP4 E00A08 0 +OP4 E00A09 0 +OP4 E00A0A 0 +OP4 E00A0B 0 +OP4 E00A0C 0 +OP4 E00A0D 0 +OP4 E00A0E 0 +OP4 E00A0F 0 +OP4 E00A10 0 +OP4 E00A11 0 +OP4 E00A12 0 +OP4 E00A13 0 +OP4 E00A14 0 +OP4 E00A15 0 +OP4 E00A16 0 +OP4 E00A17 0 +OP4 E00A18 0 +OP4 E00A19 0 +OP4 E00A1A 0 +OP4 E00A1B 0 +OP4 E00A1C 0 +OP4 E00A1D 0 +OP4 E00A1E 0 +OP4 E00A1F 0 +OP4 E00A20 0 +OP4 E00A21 0 +OP4 E00A22 0 +OP4 E00A23 0 +OP4 E00A24 0 +OP4 E00A25 0 +OP4 E00A26 0 +OP4 E00A27 0 +OP4 E00A28 0 +OP4 E00A29 0 +OP4 E00A2A 0 +OP4 E00A2B 0 +OP4 E00A2C 0 +OP4 E00A2D 0 +OP4 E00A2E 0 +OP4 E00A2F 0 +OP4 E00A30 0 +OP4 E00A31 0 +OP4 E00A32 0 +OP4 E00A33 0 +OP4 E00A34 0 +OP4 E00A35 0 +OP4 E00A36 0 +OP4 E00A37 0 +OP4 E00A38 0 +OP4 E00A39 0 +OP4 E00A3A 0 +OP4 E00A3B 0 +OP4 E00A3C 0 +OP4 E00A3D 0 +OP4 E00A3E 0 +OP4 E00A3F 0 +OP4 E00A40 0 +OP4 E00A41 0 +OP4 E00A42 0 +OP4 E00A43 0 +OP4 E00A44 0 +OP4 E00A45 0 +OP4 E00A46 0 +OP4 E00A47 0 +OP4 E00A48 0 +OP4 E00A49 0 +OP4 E00A4A 0 +OP4 E00A4B 0 +OP4 E00A4C 0 +OP4 E00A4D 0 +OP4 E00A4E 0 +OP4 E00A4F 0 +OP4 E00A50 0 +OP4 E00A51 0 +OP4 E00A52 0 +OP4 E00A53 0 +OP4 E00A54 0 +OP4 E00A55 0 +OP4 E00A56 0 +OP4 E00A57 0 +OP4 E00A58 0 +OP4 E00A59 0 +OP4 E00A5A 0 +OP4 E00A5B 0 +OP4 E00A5C 0 +OP4 E00A5D 0 +OP4 E00A5E 0 +OP4 E00A5F 0 +OP4 E00A60 0 +OP4 E00A61 0 +OP4 E00A62 0 +OP4 E00A63 0 +OP4 E00A64 0 +OP4 E00A65 0 +OP4 E00A66 0 +OP4 E00A67 0 +OP4 E00A68 0 +OP4 E00A69 0 +OP4 E00A6A 0 +OP4 E00A6B 0 +OP4 E00A6C 0 +OP4 E00A6D 0 +OP4 E00A6E 0 +OP4 E00A6F 0 +OP4 E00A70 0 +OP4 E00A71 0 +OP4 E00A72 0 +OP4 E00A73 0 +OP4 E00A74 0 +OP4 E00A75 0 +OP4 E00A76 0 +OP4 E00A77 0 +OP4 E00A78 0 +OP4 E00A79 0 +OP4 E00A7A 0 +OP4 E00A7B 0 +OP4 E00A7C 0 +OP4 E00A7D 0 +OP4 E00A7E 0 +OP4 E00A7F 0 +OP4 E00A80 0 +OP4 E00A81 0 +OP4 E00A82 0 +OP4 E00A83 0 +OP4 E00A84 0 +OP4 E00A85 0 +OP4 E00A86 0 +OP4 E00A87 0 +OP4 E00A88 0 +OP4 E00A89 0 +OP4 E00A8A 0 +OP4 E00A8B 0 +OP4 E00A8C 0 +OP4 E00A8D 0 +OP4 E00A8E 0 +OP4 E00A8F 0 +OP4 E00A90 0 +OP4 E00A91 0 +OP4 E00A92 0 +OP4 E00A93 0 +OP4 E00A94 0 +OP4 E00A95 0 +OP4 E00A96 0 +OP4 E00A97 0 +OP4 E00A98 0 +OP4 E00A99 0 +OP4 E00A9A 0 +OP4 E00A9B 0 +OP4 E00A9C 0 +OP4 E00A9D 0 +OP4 E00A9E 0 +OP4 E00A9F 0 +OP4 E00AA0 0 +OP4 E00AA1 0 +OP4 E00AA2 0 +OP4 E00AA3 0 +OP4 E00AA4 0 +OP4 E00AA5 0 +OP4 E00AA6 0 +OP4 E00AA7 0 +OP4 E00AA8 0 +OP4 E00AA9 0 +OP4 E00AAA 0 +OP4 E00AAB 0 +OP4 E00AAC 0 +OP4 E00AAD 0 +OP4 E00AAE 0 +OP4 E00AAF 0 +OP4 E00AB0 0 +OP4 E00AB1 0 +OP4 E00AB2 0 +OP4 E00AB3 0 +OP4 E00AB4 0 +OP4 E00AB5 0 +OP4 E00AB6 0 +OP4 E00AB7 0 +OP4 E00AB8 0 +OP4 E00AB9 0 +OP4 E00ABA 0 +OP4 E00ABB 0 +OP4 E00ABC 0 +OP4 E00ABD 0 +OP4 E00ABE 0 +OP4 E00ABF 0 +OP4 E00AC0 0 +OP4 E00AC1 0 +OP4 E00AC2 0 +OP4 E00AC3 0 +OP4 E00AC4 0 +OP4 E00AC5 0 +OP4 E00AC6 0 +OP4 E00AC7 0 +OP4 E00AC8 0 +OP4 E00AC9 0 +OP4 E00ACA 0 +OP4 E00ACB 0 +OP4 E00ACC 0 +OP4 E00ACD 0 +OP4 E00ACE 0 +OP4 E00ACF 0 +OP4 E00AD0 0 +OP4 E00AD1 0 +OP4 E00AD2 0 +OP4 E00AD3 0 +OP4 E00AD4 0 +OP4 E00AD5 0 +OP4 E00AD6 0 +OP4 E00AD7 0 +OP4 E00AD8 0 +OP4 E00AD9 0 +OP4 E00ADA 0 +OP4 E00ADB 0 +OP4 E00ADC 0 +OP4 E00ADD 0 +OP4 E00ADE 0 +OP4 E00ADF 0 +OP4 E00AE0 0 +OP4 E00AE1 0 +OP4 E00AE2 0 +OP4 E00AE3 0 +OP4 E00AE4 0 +OP4 E00AE5 0 +OP4 E00AE6 0 +OP4 E00AE7 0 +OP4 E00AE8 0 +OP4 E00AE9 0 +OP4 E00AEA 0 +OP4 E00AEB 0 +OP4 E00AEC 0 +OP4 E00AED 0 +OP4 E00AEE 0 +OP4 E00AEF 0 +OP4 E00AF0 0 +OP4 E00AF1 0 +OP4 E00AF2 0 +OP4 E00AF3 0 +OP4 E00AF4 0 +OP4 E00AF5 0 +OP4 E00AF6 0 +OP4 E00AF7 0 +OP4 E00AF8 0 +OP4 E00AF9 0 +OP4 E00AFA 0 +OP4 E00AFB 0 +OP4 E00AFC 0 +OP4 E00AFD 0 +OP4 E00AFE 0 +OP4 E00AFF 0 +OP4 E00B00 0 +OP4 E00B01 0 +OP4 E00B02 0 +OP4 E00B03 0 +OP4 E00B04 0 +OP4 E00B05 0 +OP4 E00B06 0 +OP4 E00B07 0 +OP4 E00B08 0 +OP4 E00B09 0 +OP4 E00B0A 0 +OP4 E00B0B 0 +OP4 E00B0C 0 +OP4 E00B0D 0 +OP4 E00B0E 0 +OP4 E00B0F 0 +OP4 E00B10 0 +OP4 E00B11 0 +OP4 E00B12 0 +OP4 E00B13 0 +OP4 E00B14 0 +OP4 E00B15 0 +OP4 E00B16 0 +OP4 E00B17 0 +OP4 E00B18 0 +OP4 E00B19 0 +OP4 E00B1A 0 +OP4 E00B1B 0 +OP4 E00B1C 0 +OP4 E00B1D 0 +OP4 E00B1E 0 +OP4 E00B1F 0 +OP4 E00B20 0 +OP4 E00B21 0 +OP4 E00B22 0 +OP4 E00B23 0 +OP4 E00B24 0 +OP4 E00B25 0 +OP4 E00B26 0 +OP4 E00B27 0 +OP4 E00B28 0 +OP4 E00B29 0 +OP4 E00B2A 0 +OP4 E00B2B 0 +OP4 E00B2C 0 +OP4 E00B2D 0 +OP4 E00B2E 0 +OP4 E00B2F 0 +OP4 E00B30 0 +OP4 E00B31 0 +OP4 E00B32 0 +OP4 E00B33 0 +OP4 E00B34 0 +OP4 E00B35 0 +OP4 E00B36 0 +OP4 E00B37 0 +OP4 E00B38 0 +OP4 E00B39 0 +OP4 E00B3A 0 +OP4 E00B3B 0 +OP4 E00B3C 0 +OP4 E00B3D 0 +OP4 E00B3E 0 +OP4 E00B3F 0 +OP4 E00B40 0 +OP4 E00B41 0 +OP4 E00B42 0 +OP4 E00B43 0 +OP4 E00B44 0 +OP4 E00B45 0 +OP4 E00B46 0 +OP4 E00B47 0 +OP4 E00B48 0 +OP4 E00B49 0 +OP4 E00B4A 0 +OP4 E00B4B 0 +OP4 E00B4C 0 +OP4 E00B4D 0 +OP4 E00B4E 0 +OP4 E00B4F 0 +OP4 E00B50 0 +OP4 E00B51 0 +OP4 E00B52 0 +OP4 E00B53 0 +OP4 E00B54 0 +OP4 E00B55 0 +OP4 E00B56 0 +OP4 E00B57 0 +OP4 E00B58 0 +OP4 E00B59 0 +OP4 E00B5A 0 +OP4 E00B5B 0 +OP4 E00B5C 0 +OP4 E00B5D 0 +OP4 E00B5E 0 +OP4 E00B5F 0 +OP4 E00B60 0 +OP4 E00B61 0 +OP4 E00B62 0 +OP4 E00B63 0 +OP4 E00B64 0 +OP4 E00B65 0 +OP4 E00B66 0 +OP4 E00B67 0 +OP4 E00B68 0 +OP4 E00B69 0 +OP4 E00B6A 0 +OP4 E00B6B 0 +OP4 E00B6C 0 +OP4 E00B6D 0 +OP4 E00B6E 0 +OP4 E00B6F 0 +OP4 E00B70 0 +OP4 E00B71 0 +OP4 E00B72 0 +OP4 E00B73 0 +OP4 E00B74 0 +OP4 E00B75 0 +OP4 E00B76 0 +OP4 E00B77 0 +OP4 E00B78 0 +OP4 E00B79 0 +OP4 E00B7A 0 +OP4 E00B7B 0 +OP4 E00B7C 0 +OP4 E00B7D 0 +OP4 E00B7E 0 +OP4 E00B7F 0 +OP4 E00B80 0 +OP4 E00B81 0 +OP4 E00B82 0 +OP4 E00B83 0 +OP4 E00B84 0 +OP4 E00B85 0 +OP4 E00B86 0 +OP4 E00B87 0 +OP4 E00B88 0 +OP4 E00B89 0 +OP4 E00B8A 0 +OP4 E00B8B 0 +OP4 E00B8C 0 +OP4 E00B8D 0 +OP4 E00B8E 0 +OP4 E00B8F 0 +OP4 E00B90 0 +OP4 E00B91 0 +OP4 E00B92 0 +OP4 E00B93 0 +OP4 E00B94 0 +OP4 E00B95 0 +OP4 E00B96 0 +OP4 E00B97 0 +OP4 E00B98 0 +OP4 E00B99 0 +OP4 E00B9A 0 +OP4 E00B9B 0 +OP4 E00B9C 0 +OP4 E00B9D 0 +OP4 E00B9E 0 +OP4 E00B9F 0 +OP4 E00BA0 0 +OP4 E00BA1 0 +OP4 E00BA2 0 +OP4 E00BA3 0 +OP4 E00BA4 0 +OP4 E00BA5 0 +OP4 E00BA6 0 +OP4 E00BA7 0 +OP4 E00BA8 0 +OP4 E00BA9 0 +OP4 E00BAA 0 +OP4 E00BAB 0 +OP4 E00BAC 0 +OP4 E00BAD 0 +OP4 E00BAE 0 +OP4 E00BAF 0 +OP4 E00BB0 0 +OP4 E00BB1 0 +OP4 E00BB2 0 +OP4 E00BB3 0 +OP4 E00BB4 0 +OP4 E00BB5 0 +OP4 E00BB6 0 +OP4 E00BB7 0 +OP4 E00BB8 0 +OP4 E00BB9 0 +OP4 E00BBA 0 +OP4 E00BBB 0 +OP4 E00BBC 0 +OP4 E00BBD 0 +OP4 E00BBE 0 +OP4 E00BBF 0 +OP4 E00BC0 0 +OP4 E00BC1 0 +OP4 E00BC2 0 +OP4 E00BC3 0 +OP4 E00BC4 0 +OP4 E00BC5 0 +OP4 E00BC6 0 +OP4 E00BC7 0 +OP4 E00BC8 0 +OP4 E00BC9 0 +OP4 E00BCA 0 +OP4 E00BCB 0 +OP4 E00BCC 0 +OP4 E00BCD 0 +OP4 E00BCE 0 +OP4 E00BCF 0 +OP4 E00BD0 0 +OP4 E00BD1 0 +OP4 E00BD2 0 +OP4 E00BD3 0 +OP4 E00BD4 0 +OP4 E00BD5 0 +OP4 E00BD6 0 +OP4 E00BD7 0 +OP4 E00BD8 0 +OP4 E00BD9 0 +OP4 E00BDA 0 +OP4 E00BDB 0 +OP4 E00BDC 0 +OP4 E00BDD 0 +OP4 E00BDE 0 +OP4 E00BDF 0 +OP4 E00BE0 0 +OP4 E00BE1 0 +OP4 E00BE2 0 +OP4 E00BE3 0 +OP4 E00BE4 0 +OP4 E00BE5 0 +OP4 E00BE6 0 +OP4 E00BE7 0 +OP4 E00BE8 0 +OP4 E00BE9 0 +OP4 E00BEA 0 +OP4 E00BEB 0 +OP4 E00BEC 0 +OP4 E00BED 0 +OP4 E00BEE 0 +OP4 E00BEF 0 +OP4 E00BF0 0 +OP4 E00BF1 0 +OP4 E00BF2 0 +OP4 E00BF3 0 +OP4 E00BF4 0 +OP4 E00BF5 0 +OP4 E00BF6 0 +OP4 E00BF7 0 +OP4 E00BF8 0 +OP4 E00BF9 0 +OP4 E00BFA 0 +OP4 E00BFB 0 +OP4 E00BFC 0 +OP4 E00BFD 0 +OP4 E00BFE 0 +OP4 E00BFF 0 +OP4 E00C00 0 +OP4 E00C01 0 +OP4 E00C02 0 +OP4 E00C03 0 +OP4 E00C04 0 +OP4 E00C05 0 +OP4 E00C06 0 +OP4 E00C07 0 +OP4 E00C08 0 +OP4 E00C09 0 +OP4 E00C0A 0 +OP4 E00C0B 0 +OP4 E00C0C 0 +OP4 E00C0D 0 +OP4 E00C0E 0 +OP4 E00C0F 0 +OP4 E00C10 0 +OP4 E00C11 0 +OP4 E00C12 0 +OP4 E00C13 0 +OP4 E00C14 0 +OP4 E00C15 0 +OP4 E00C16 0 +OP4 E00C17 0 +OP4 E00C18 0 +OP4 E00C19 0 +OP4 E00C1A 0 +OP4 E00C1B 0 +OP4 E00C1C 0 +OP4 E00C1D 0 +OP4 E00C1E 0 +OP4 E00C1F 0 +OP4 E00C20 0 +OP4 E00C21 0 +OP4 E00C22 0 +OP4 E00C23 0 +OP4 E00C24 0 +OP4 E00C25 0 +OP4 E00C26 0 +OP4 E00C27 0 +OP4 E00C28 0 +OP4 E00C29 0 +OP4 E00C2A 0 +OP4 E00C2B 0 +OP4 E00C2C 0 +OP4 E00C2D 0 +OP4 E00C2E 0 +OP4 E00C2F 0 +OP4 E00C30 0 +OP4 E00C31 0 +OP4 E00C32 0 +OP4 E00C33 0 +OP4 E00C34 0 +OP4 E00C35 0 +OP4 E00C36 0 +OP4 E00C37 0 +OP4 E00C38 0 +OP4 E00C39 0 +OP4 E00C3A 0 +OP4 E00C3B 0 +OP4 E00C3C 0 +OP4 E00C3D 0 +OP4 E00C3E 0 +OP4 E00C3F 0 +OP4 E00C40 0 +OP4 E00C41 0 +OP4 E00C42 0 +OP4 E00C43 0 +OP4 E00C44 0 +OP4 E00C45 0 +OP4 E00C46 0 +OP4 E00C47 0 +OP4 E00C48 0 +OP4 E00C49 0 +OP4 E00C4A 0 +OP4 E00C4B 0 +OP4 E00C4C 0 +OP4 E00C4D 0 +OP4 E00C4E 0 +OP4 E00C4F 0 +OP4 E00C50 0 +OP4 E00C51 0 +OP4 E00C52 0 +OP4 E00C53 0 +OP4 E00C54 0 +OP4 E00C55 0 +OP4 E00C56 0 +OP4 E00C57 0 +OP4 E00C58 0 +OP4 E00C59 0 +OP4 E00C5A 0 +OP4 E00C5B 0 +OP4 E00C5C 0 +OP4 E00C5D 0 +OP4 E00C5E 0 +OP4 E00C5F 0 +OP4 E00C60 0 +OP4 E00C61 0 +OP4 E00C62 0 +OP4 E00C63 0 +OP4 E00C64 0 +OP4 E00C65 0 +OP4 E00C66 0 +OP4 E00C67 0 +OP4 E00C68 0 +OP4 E00C69 0 +OP4 E00C6A 0 +OP4 E00C6B 0 +OP4 E00C6C 0 +OP4 E00C6D 0 +OP4 E00C6E 0 +OP4 E00C6F 0 +OP4 E00C70 0 +OP4 E00C71 0 +OP4 E00C72 0 +OP4 E00C73 0 +OP4 E00C74 0 +OP4 E00C75 0 +OP4 E00C76 0 +OP4 E00C77 0 +OP4 E00C78 0 +OP4 E00C79 0 +OP4 E00C7A 0 +OP4 E00C7B 0 +OP4 E00C7C 0 +OP4 E00C7D 0 +OP4 E00C7E 0 +OP4 E00C7F 0 +OP4 E00C80 0 +OP4 E00C81 0 +OP4 E00C82 0 +OP4 E00C83 0 +OP4 E00C84 0 +OP4 E00C85 0 +OP4 E00C86 0 +OP4 E00C87 0 +OP4 E00C88 0 +OP4 E00C89 0 +OP4 E00C8A 0 +OP4 E00C8B 0 +OP4 E00C8C 0 +OP4 E00C8D 0 +OP4 E00C8E 0 +OP4 E00C8F 0 +OP4 E00C90 0 +OP4 E00C91 0 +OP4 E00C92 0 +OP4 E00C93 0 +OP4 E00C94 0 +OP4 E00C95 0 +OP4 E00C96 0 +OP4 E00C97 0 +OP4 E00C98 0 +OP4 E00C99 0 +OP4 E00C9A 0 +OP4 E00C9B 0 +OP4 E00C9C 0 +OP4 E00C9D 0 +OP4 E00C9E 0 +OP4 E00C9F 0 +OP4 E00CA0 0 +OP4 E00CA1 0 +OP4 E00CA2 0 +OP4 E00CA3 0 +OP4 E00CA4 0 +OP4 E00CA5 0 +OP4 E00CA6 0 +OP4 E00CA7 0 +OP4 E00CA8 0 +OP4 E00CA9 0 +OP4 E00CAA 0 +OP4 E00CAB 0 +OP4 E00CAC 0 +OP4 E00CAD 0 +OP4 E00CAE 0 +OP4 E00CAF 0 +OP4 E00CB0 0 +OP4 E00CB1 0 +OP4 E00CB2 0 +OP4 E00CB3 0 +OP4 E00CB4 0 +OP4 E00CB5 0 +OP4 E00CB6 0 +OP4 E00CB7 0 +OP4 E00CB8 0 +OP4 E00CB9 0 +OP4 E00CBA 0 +OP4 E00CBB 0 +OP4 E00CBC 0 +OP4 E00CBD 0 +OP4 E00CBE 0 +OP4 E00CBF 0 +OP4 E00CC0 0 +OP4 E00CC1 0 +OP4 E00CC2 0 +OP4 E00CC3 0 +OP4 E00CC4 0 +OP4 E00CC5 0 +OP4 E00CC6 0 +OP4 E00CC7 0 +OP4 E00CC8 0 +OP4 E00CC9 0 +OP4 E00CCA 0 +OP4 E00CCB 0 +OP4 E00CCC 0 +OP4 E00CCD 0 +OP4 E00CCE 0 +OP4 E00CCF 0 +OP4 E00CD0 0 +OP4 E00CD1 0 +OP4 E00CD2 0 +OP4 E00CD3 0 +OP4 E00CD4 0 +OP4 E00CD5 0 +OP4 E00CD6 0 +OP4 E00CD7 0 +OP4 E00CD8 0 +OP4 E00CD9 0 +OP4 E00CDA 0 +OP4 E00CDB 0 +OP4 E00CDC 0 +OP4 E00CDD 0 +OP4 E00CDE 0 +OP4 E00CDF 0 +OP4 E00CE0 0 +OP4 E00CE1 0 +OP4 E00CE2 0 +OP4 E00CE3 0 +OP4 E00CE4 0 +OP4 E00CE5 0 +OP4 E00CE6 0 +OP4 E00CE7 0 +OP4 E00CE8 0 +OP4 E00CE9 0 +OP4 E00CEA 0 +OP4 E00CEB 0 +OP4 E00CEC 0 +OP4 E00CED 0 +OP4 E00CEE 0 +OP4 E00CEF 0 +OP4 E00CF0 0 +OP4 E00CF1 0 +OP4 E00CF2 0 +OP4 E00CF3 0 +OP4 E00CF4 0 +OP4 E00CF5 0 +OP4 E00CF6 0 +OP4 E00CF7 0 +OP4 E00CF8 0 +OP4 E00CF9 0 +OP4 E00CFA 0 +OP4 E00CFB 0 +OP4 E00CFC 0 +OP4 E00CFD 0 +OP4 E00CFE 0 +OP4 E00CFF 0 +OP4 E00D00 0 +OP4 E00D01 0 +OP4 E00D02 0 +OP4 E00D03 0 +OP4 E00D04 0 +OP4 E00D05 0 +OP4 E00D06 0 +OP4 E00D07 0 +OP4 E00D08 0 +OP4 E00D09 0 +OP4 E00D0A 0 +OP4 E00D0B 0 +OP4 E00D0C 0 +OP4 E00D0D 0 +OP4 E00D0E 0 +OP4 E00D0F 0 +OP4 E00D10 0 +OP4 E00D11 0 +OP4 E00D12 0 +OP4 E00D13 0 +OP4 E00D14 0 +OP4 E00D15 0 +OP4 E00D16 0 +OP4 E00D17 0 +OP4 E00D18 0 +OP4 E00D19 0 +OP4 E00D1A 0 +OP4 E00D1B 0 +OP4 E00D1C 0 +OP4 E00D1D 0 +OP4 E00D1E 0 +OP4 E00D1F 0 +OP4 E00D20 0 +OP4 E00D21 0 +OP4 E00D22 0 +OP4 E00D23 0 +OP4 E00D24 0 +OP4 E00D25 0 +OP4 E00D26 0 +OP4 E00D27 0 +OP4 E00D28 0 +OP4 E00D29 0 +OP4 E00D2A 0 +OP4 E00D2B 0 +OP4 E00D2C 0 +OP4 E00D2D 0 +OP4 E00D2E 0 +OP4 E00D2F 0 +OP4 E00D30 0 +OP4 E00D31 0 +OP4 E00D32 0 +OP4 E00D33 0 +OP4 E00D34 0 +OP4 E00D35 0 +OP4 E00D36 0 +OP4 E00D37 0 +OP4 E00D38 0 +OP4 E00D39 0 +OP4 E00D3A 0 +OP4 E00D3B 0 +OP4 E00D3C 0 +OP4 E00D3D 0 +OP4 E00D3E 0 +OP4 E00D3F 0 +OP4 E00D40 0 +OP4 E00D41 0 +OP4 E00D42 0 +OP4 E00D43 0 +OP4 E00D44 0 +OP4 E00D45 0 +OP4 E00D46 0 +OP4 E00D47 0 +OP4 E00D48 0 +OP4 E00D49 0 +OP4 E00D4A 0 +OP4 E00D4B 0 +OP4 E00D4C 0 +OP4 E00D4D 0 +OP4 E00D4E 0 +OP4 E00D4F 0 +OP4 E00D50 0 +OP4 E00D51 0 +OP4 E00D52 0 +OP4 E00D53 0 +OP4 E00D54 0 +OP4 E00D55 0 +OP4 E00D56 0 +OP4 E00D57 0 +OP4 E00D58 0 +OP4 E00D59 0 +OP4 E00D5A 0 +OP4 E00D5B 0 +OP4 E00D5C 0 +OP4 E00D5D 0 +OP4 E00D5E 0 +OP4 E00D5F 0 +OP4 E00D60 0 +OP4 E00D61 0 +OP4 E00D62 0 +OP4 E00D63 0 +OP4 E00D64 0 +OP4 E00D65 0 +OP4 E00D66 0 +OP4 E00D67 0 +OP4 E00D68 0 +OP4 E00D69 0 +OP4 E00D6A 0 +OP4 E00D6B 0 +OP4 E00D6C 0 +OP4 E00D6D 0 +OP4 E00D6E 0 +OP4 E00D6F 0 +OP4 E00D70 0 +OP4 E00D71 0 +OP4 E00D72 0 +OP4 E00D73 0 +OP4 E00D74 0 +OP4 E00D75 0 +OP4 E00D76 0 +OP4 E00D77 0 +OP4 E00D78 0 +OP4 E00D79 0 +OP4 E00D7A 0 +OP4 E00D7B 0 +OP4 E00D7C 0 +OP4 E00D7D 0 +OP4 E00D7E 0 +OP4 E00D7F 0 +OP4 E00D80 0 +OP4 E00D81 0 +OP4 E00D82 0 +OP4 E00D83 0 +OP4 E00D84 0 +OP4 E00D85 0 +OP4 E00D86 0 +OP4 E00D87 0 +OP4 E00D88 0 +OP4 E00D89 0 +OP4 E00D8A 0 +OP4 E00D8B 0 +OP4 E00D8C 0 +OP4 E00D8D 0 +OP4 E00D8E 0 +OP4 E00D8F 0 +OP4 E00D90 0 +OP4 E00D91 0 +OP4 E00D92 0 +OP4 E00D93 0 +OP4 E00D94 0 +OP4 E00D95 0 +OP4 E00D96 0 +OP4 E00D97 0 +OP4 E00D98 0 +OP4 E00D99 0 +OP4 E00D9A 0 +OP4 E00D9B 0 +OP4 E00D9C 0 +OP4 E00D9D 0 +OP4 E00D9E 0 +OP4 E00D9F 0 +OP4 E00DA0 0 +OP4 E00DA1 0 +OP4 E00DA2 0 +OP4 E00DA3 0 +OP4 E00DA4 0 +OP4 E00DA5 0 +OP4 E00DA6 0 +OP4 E00DA7 0 +OP4 E00DA8 0 +OP4 E00DA9 0 +OP4 E00DAA 0 +OP4 E00DAB 0 +OP4 E00DAC 0 +OP4 E00DAD 0 +OP4 E00DAE 0 +OP4 E00DAF 0 +OP4 E00DB0 0 +OP4 E00DB1 0 +OP4 E00DB2 0 +OP4 E00DB3 0 +OP4 E00DB4 0 +OP4 E00DB5 0 +OP4 E00DB6 0 +OP4 E00DB7 0 +OP4 E00DB8 0 +OP4 E00DB9 0 +OP4 E00DBA 0 +OP4 E00DBB 0 +OP4 E00DBC 0 +OP4 E00DBD 0 +OP4 E00DBE 0 +OP4 E00DBF 0 +OP4 E00DC0 0 +OP4 E00DC1 0 +OP4 E00DC2 0 +OP4 E00DC3 0 +OP4 E00DC4 0 +OP4 E00DC5 0 +OP4 E00DC6 0 +OP4 E00DC7 0 +OP4 E00DC8 0 +OP4 E00DC9 0 +OP4 E00DCA 0 +OP4 E00DCB 0 +OP4 E00DCC 0 +OP4 E00DCD 0 +OP4 E00DCE 0 +OP4 E00DCF 0 +OP4 E00DD0 0 +OP4 E00DD1 0 +OP4 E00DD2 0 +OP4 E00DD3 0 +OP4 E00DD4 0 +OP4 E00DD5 0 +OP4 E00DD6 0 +OP4 E00DD7 0 +OP4 E00DD8 0 +OP4 E00DD9 0 +OP4 E00DDA 0 +OP4 E00DDB 0 +OP4 E00DDC 0 +OP4 E00DDD 0 +OP4 E00DDE 0 +OP4 E00DDF 0 +OP4 E00DE0 0 +OP4 E00DE1 0 +OP4 E00DE2 0 +OP4 E00DE3 0 +OP4 E00DE4 0 +OP4 E00DE5 0 +OP4 E00DE6 0 +OP4 E00DE7 0 +OP4 E00DE8 0 +OP4 E00DE9 0 +OP4 E00DEA 0 +OP4 E00DEB 0 +OP4 E00DEC 0 +OP4 E00DED 0 +OP4 E00DEE 0 +OP4 E00DEF 0 +OP4 E00DF0 0 +OP4 E00DF1 0 +OP4 E00DF2 0 +OP4 E00DF3 0 +OP4 E00DF4 0 +OP4 E00DF5 0 +OP4 E00DF6 0 +OP4 E00DF7 0 +OP4 E00DF8 0 +OP4 E00DF9 0 +OP4 E00DFA 0 +OP4 E00DFB 0 +OP4 E00DFC 0 +OP4 E00DFD 0 +OP4 E00DFE 0 +OP4 E00DFF 0 +OP4 E00E00 0 +OP4 E00E01 0 +OP4 E00E02 0 +OP4 E00E03 0 +OP4 E00E04 0 +OP4 E00E05 0 +OP4 E00E06 0 +OP4 E00E07 0 +OP4 E00E08 0 +OP4 E00E09 0 +OP4 E00E0A 0 +OP4 E00E0B 0 +OP4 E00E0C 0 +OP4 E00E0D 0 +OP4 E00E0E 0 +OP4 E00E0F 0 +OP4 E00E10 0 +OP4 E00E11 0 +OP4 E00E12 0 +OP4 E00E13 0 +OP4 E00E14 0 +OP4 E00E15 0 +OP4 E00E16 0 +OP4 E00E17 0 +OP4 E00E18 0 +OP4 E00E19 0 +OP4 E00E1A 0 +OP4 E00E1B 0 +OP4 E00E1C 0 +OP4 E00E1D 0 +OP4 E00E1E 0 +OP4 E00E1F 0 +OP4 E00E20 0 +OP4 E00E21 0 +OP4 E00E22 0 +OP4 E00E23 0 +OP4 E00E24 0 +OP4 E00E25 0 +OP4 E00E26 0 +OP4 E00E27 0 +OP4 E00E28 0 +OP4 E00E29 0 +OP4 E00E2A 0 +OP4 E00E2B 0 +OP4 E00E2C 0 +OP4 E00E2D 0 +OP4 E00E2E 0 +OP4 E00E2F 0 +OP4 E00E30 0 +OP4 E00E31 0 +OP4 E00E32 0 +OP4 E00E33 0 +OP4 E00E34 0 +OP4 E00E35 0 +OP4 E00E36 0 +OP4 E00E37 0 +OP4 E00E38 0 +OP4 E00E39 0 +OP4 E00E3A 0 +OP4 E00E3B 0 +OP4 E00E3C 0 +OP4 E00E3D 0 +OP4 E00E3E 0 +OP4 E00E3F 0 +OP4 E00E40 0 +OP4 E00E41 0 +OP4 E00E42 0 +OP4 E00E43 0 +OP4 E00E44 0 +OP4 E00E45 0 +OP4 E00E46 0 +OP4 E00E47 0 +OP4 E00E48 0 +OP4 E00E49 0 +OP4 E00E4A 0 +OP4 E00E4B 0 +OP4 E00E4C 0 +OP4 E00E4D 0 +OP4 E00E4E 0 +OP4 E00E4F 0 +OP4 E00E50 0 +OP4 E00E51 0 +OP4 E00E52 0 +OP4 E00E53 0 +OP4 E00E54 0 +OP4 E00E55 0 +OP4 E00E56 0 +OP4 E00E57 0 +OP4 E00E58 0 +OP4 E00E59 0 +OP4 E00E5A 0 +OP4 E00E5B 0 +OP4 E00E5C 0 +OP4 E00E5D 0 +OP4 E00E5E 0 +OP4 E00E5F 0 +OP4 E00E60 0 +OP4 E00E61 0 +OP4 E00E62 0 +OP4 E00E63 0 +OP4 E00E64 0 +OP4 E00E65 0 +OP4 E00E66 0 +OP4 E00E67 0 +OP4 E00E68 0 +OP4 E00E69 0 +OP4 E00E6A 0 +OP4 E00E6B 0 +OP4 E00E6C 0 +OP4 E00E6D 0 +OP4 E00E6E 0 +OP4 E00E6F 0 +OP4 E00E70 0 +OP4 E00E71 0 +OP4 E00E72 0 +OP4 E00E73 0 +OP4 E00E74 0 +OP4 E00E75 0 +OP4 E00E76 0 +OP4 E00E77 0 +OP4 E00E78 0 +OP4 E00E79 0 +OP4 E00E7A 0 +OP4 E00E7B 0 +OP4 E00E7C 0 +OP4 E00E7D 0 +OP4 E00E7E 0 +OP4 E00E7F 0 +OP4 E00E80 0 +OP4 E00E81 0 +OP4 E00E82 0 +OP4 E00E83 0 +OP4 E00E84 0 +OP4 E00E85 0 +OP4 E00E86 0 +OP4 E00E87 0 +OP4 E00E88 0 +OP4 E00E89 0 +OP4 E00E8A 0 +OP4 E00E8B 0 +OP4 E00E8C 0 +OP4 E00E8D 0 +OP4 E00E8E 0 +OP4 E00E8F 0 +OP4 E00E90 0 +OP4 E00E91 0 +OP4 E00E92 0 +OP4 E00E93 0 +OP4 E00E94 0 +OP4 E00E95 0 +OP4 E00E96 0 +OP4 E00E97 0 +OP4 E00E98 0 +OP4 E00E99 0 +OP4 E00E9A 0 +OP4 E00E9B 0 +OP4 E00E9C 0 +OP4 E00E9D 0 +OP4 E00E9E 0 +OP4 E00E9F 0 +OP4 E00EA0 0 +OP4 E00EA1 0 +OP4 E00EA2 0 +OP4 E00EA3 0 +OP4 E00EA4 0 +OP4 E00EA5 0 +OP4 E00EA6 0 +OP4 E00EA7 0 +OP4 E00EA8 0 +OP4 E00EA9 0 +OP4 E00EAA 0 +OP4 E00EAB 0 +OP4 E00EAC 0 +OP4 E00EAD 0 +OP4 E00EAE 0 +OP4 E00EAF 0 +OP4 E00EB0 0 +OP4 E00EB1 0 +OP4 E00EB2 0 +OP4 E00EB3 0 +OP4 E00EB4 0 +OP4 E00EB5 0 +OP4 E00EB6 0 +OP4 E00EB7 0 +OP4 E00EB8 0 +OP4 E00EB9 0 +OP4 E00EBA 0 +OP4 E00EBB 0 +OP4 E00EBC 0 +OP4 E00EBD 0 +OP4 E00EBE 0 +OP4 E00EBF 0 +OP4 E00EC0 0 +OP4 E00EC1 0 +OP4 E00EC2 0 +OP4 E00EC3 0 +OP4 E00EC4 0 +OP4 E00EC5 0 +OP4 E00EC6 0 +OP4 E00EC7 0 +OP4 E00EC8 0 +OP4 E00EC9 0 +OP4 E00ECA 0 +OP4 E00ECB 0 +OP4 E00ECC 0 +OP4 E00ECD 0 +OP4 E00ECE 0 +OP4 E00ECF 0 +OP4 E00ED0 0 +OP4 E00ED1 0 +OP4 E00ED2 0 +OP4 E00ED3 0 +OP4 E00ED4 0 +OP4 E00ED5 0 +OP4 E00ED6 0 +OP4 E00ED7 0 +OP4 E00ED8 0 +OP4 E00ED9 0 +OP4 E00EDA 0 +OP4 E00EDB 0 +OP4 E00EDC 0 +OP4 E00EDD 0 +OP4 E00EDE 0 +OP4 E00EDF 0 +OP4 E00EE0 0 +OP4 E00EE1 0 +OP4 E00EE2 0 +OP4 E00EE3 0 +OP4 E00EE4 0 +OP4 E00EE5 0 +OP4 E00EE6 0 +OP4 E00EE7 0 +OP4 E00EE8 0 +OP4 E00EE9 0 +OP4 E00EEA 0 +OP4 E00EEB 0 +OP4 E00EEC 0 +OP4 E00EED 0 +OP4 E00EEE 0 +OP4 E00EEF 0 +OP4 E00EF0 0 +OP4 E00EF1 0 +OP4 E00EF2 0 +OP4 E00EF3 0 +OP4 E00EF4 0 +OP4 E00EF5 0 +OP4 E00EF6 0 +OP4 E00EF7 0 +OP4 E00EF8 0 +OP4 E00EF9 0 +OP4 E00EFA 0 +OP4 E00EFB 0 +OP4 E00EFC 0 +OP4 E00EFD 0 +OP4 E00EFE 0 +OP4 E00EFF 0 +OP4 E00F00 0 +OP4 E00F01 0 +OP4 E00F02 0 +OP4 E00F03 0 +OP4 E00F04 0 +OP4 E00F05 0 +OP4 E00F06 0 +OP4 E00F07 0 +OP4 E00F08 0 +OP4 E00F09 0 +OP4 E00F0A 0 +OP4 E00F0B 0 +OP4 E00F0C 0 +OP4 E00F0D 0 +OP4 E00F0E 0 +OP4 E00F0F 0 +OP4 E00F10 0 +OP4 E00F11 0 +OP4 E00F12 0 +OP4 E00F13 0 +OP4 E00F14 0 +OP4 E00F15 0 +OP4 E00F16 0 +OP4 E00F17 0 +OP4 E00F18 0 +OP4 E00F19 0 +OP4 E00F1A 0 +OP4 E00F1B 0 +OP4 E00F1C 0 +OP4 E00F1D 0 +OP4 E00F1E 0 +OP4 E00F1F 0 +OP4 E00F20 0 +OP4 E00F21 0 +OP4 E00F22 0 +OP4 E00F23 0 +OP4 E00F24 0 +OP4 E00F25 0 +OP4 E00F26 0 +OP4 E00F27 0 +OP4 E00F28 0 +OP4 E00F29 0 +OP4 E00F2A 0 +OP4 E00F2B 0 +OP4 E00F2C 0 +OP4 E00F2D 0 +OP4 E00F2E 0 +OP4 E00F2F 0 +OP4 E00F30 0 diff --git a/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum3_itrace_irisc7.cfg.ext b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum3_itrace_irisc7.cfg.ext new file mode 100644 index 000000000000..a6384fecb728 --- /dev/null +++ b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum3_itrace_irisc7.cfg.ext @@ -0,0 +1,3890 @@ +OP1 Spectrum3 +OP4 ITRACE0 0 +OP4 ITRACE1 0 +OP4 ITRACE2 0 +OP4 ITRACE3 0 +OP4 ITRACE4 0 +OP4 ITRACE5 0 +OP4 ITRACE6 0 +OP4 ITRACE7 1 +OP4 ITRACE8 0 +OP4 ITRACE9 0 +OP4 Main_PhyUC 0 +OP4 TILE0_ITRACE0 0 +OP4 TILE0_ITRACE1 0 +OP4 TILE0_ITRACE2 0 +OP4 TILE0_ITRACE3 0 +OP4 TILE0_ITRACE4 0 +OP4 TILE0_PhyUC 0 +OP4 TILE1_ITRACE0 0 +OP4 TILE1_ITRACE1 0 +OP4 TILE1_ITRACE2 0 +OP4 TILE1_ITRACE3 0 +OP4 TILE1_ITRACE4 0 +OP4 TILE1_PhyUC 0 +OP4 TILE2_ITRACE0 0 +OP4 TILE2_ITRACE1 0 +OP4 TILE2_ITRACE2 0 +OP4 TILE2_ITRACE3 0 +OP4 TILE2_ITRACE4 0 +OP4 TILE2_PhyUC 0 +OP4 TILE3_ITRACE0 0 +OP4 TILE3_ITRACE1 0 +OP4 TILE3_ITRACE2 0 +OP4 TILE3_ITRACE3 0 +OP4 TILE3_ITRACE4 0 +OP4 TILE3_PhyUC 0 +OP4 TILE4_ITRACE0 0 +OP4 TILE4_ITRACE1 0 +OP4 TILE4_ITRACE2 0 +OP4 TILE4_ITRACE3 0 +OP4 TILE4_ITRACE4 0 +OP4 TILE4_PhyUC 0 +OP4 TILE5_ITRACE0 0 +OP4 TILE5_ITRACE1 0 +OP4 TILE5_ITRACE2 0 +OP4 TILE5_ITRACE3 0 +OP4 TILE5_ITRACE4 0 +OP4 TILE5_PhyUC 0 +OP4 TILE6_ITRACE0 0 +OP4 TILE6_ITRACE1 0 +OP4 TILE6_ITRACE2 0 +OP4 TILE6_ITRACE3 0 +OP4 TILE6_ITRACE4 0 +OP4 TILE6_PhyUC 0 +OP4 TILE7_ITRACE0 0 +OP4 TILE7_ITRACE1 0 +OP4 TILE7_ITRACE2 0 +OP4 TILE7_ITRACE3 0 +OP4 TILE7_ITRACE4 0 +OP4 TILE7_PhyUC 0 +OP4 E0003B 0 +OP4 E0003C 0 +OP4 E0003D 0 +OP4 E0003E 0 +OP4 E0003F 0 +OP4 E00040 0 +OP4 E00041 0 +OP4 E00042 0 +OP4 E00043 0 +OP4 E00044 0 +OP4 E00045 0 +OP4 E00046 0 +OP4 E00047 0 +OP4 E00048 0 +OP4 E00049 0 +OP4 E0004A 0 +OP4 E0004B 0 +OP4 E0004C 0 +OP4 E0004D 0 +OP4 E0004E 0 +OP4 E0004F 0 +OP4 E00050 0 +OP4 E00051 0 +OP4 E00052 0 +OP4 E00053 0 +OP4 E00054 0 +OP4 E00055 0 +OP4 E00056 0 +OP4 E00057 0 +OP4 E00058 0 +OP4 E00059 0 +OP4 E0005A 0 +OP4 E0005B 0 +OP4 E0005C 0 +OP4 E0005D 0 +OP4 E0005E 0 +OP4 E0005F 0 +OP4 E00060 0 +OP4 E00061 0 +OP4 E00062 0 +OP4 E00063 0 +OP4 E00064 0 +OP4 E00065 0 +OP4 E00066 0 +OP4 E00067 0 +OP4 E00068 0 +OP4 E00069 0 +OP4 E0006A 0 +OP4 E0006B 0 +OP4 E0006C 0 +OP4 E0006D 0 +OP4 E0006E 0 +OP4 E0006F 0 +OP4 E00070 0 +OP4 E00071 0 +OP4 E00072 0 +OP4 E00073 0 +OP4 E00074 0 +OP4 E00075 0 +OP4 E00076 0 +OP4 E00077 0 +OP4 E00078 0 +OP4 E00079 0 +OP4 E0007A 0 +OP4 E0007B 0 +OP4 E0007C 0 +OP4 E0007D 0 +OP4 E0007E 0 +OP4 E0007F 0 +OP4 E00080 0 +OP4 E00081 0 +OP4 E00082 0 +OP4 E00083 0 +OP4 E00084 0 +OP4 E00085 0 +OP4 E00086 0 +OP4 E00087 0 +OP4 E00088 0 +OP4 E00089 0 +OP4 E0008A 0 +OP4 E0008B 0 +OP4 E0008C 0 +OP4 E0008D 0 +OP4 E0008E 0 +OP4 E0008F 0 +OP4 E00090 0 +OP4 E00091 0 +OP4 E00092 0 +OP4 E00093 0 +OP4 E00094 0 +OP4 E00095 0 +OP4 E00096 0 +OP4 E00097 0 +OP4 E00098 0 +OP4 E00099 0 +OP4 E0009A 0 +OP4 E0009B 0 +OP4 E0009C 0 +OP4 E0009D 0 +OP4 E0009E 0 +OP4 E0009F 0 +OP4 E000A0 0 +OP4 E000A1 0 +OP4 E000A2 0 +OP4 E000A3 0 +OP4 E000A4 0 +OP4 E000A5 0 +OP4 E000A6 0 +OP4 E000A7 0 +OP4 E000A8 0 +OP4 E000A9 0 +OP4 E000AA 0 +OP4 E000AB 0 +OP4 E000AC 0 +OP4 E000AD 0 +OP4 E000AE 0 +OP4 E000AF 0 +OP4 E000B0 0 +OP4 E000B1 0 +OP4 E000B2 0 +OP4 E000B3 0 +OP4 E000B4 0 +OP4 E000B5 0 +OP4 E000B6 0 +OP4 E000B7 0 +OP4 E000B8 0 +OP4 E000B9 0 +OP4 E000BA 0 +OP4 E000BB 0 +OP4 E000BC 0 +OP4 E000BD 0 +OP4 E000BE 0 +OP4 E000BF 0 +OP4 E000C0 0 +OP4 E000C1 0 +OP4 E000C2 0 +OP4 E000C3 0 +OP4 E000C4 0 +OP4 E000C5 0 +OP4 E000C6 0 +OP4 E000C7 0 +OP4 E000C8 0 +OP4 E000C9 0 +OP4 E000CA 0 +OP4 E000CB 0 +OP4 E000CC 0 +OP4 E000CD 0 +OP4 E000CE 0 +OP4 E000CF 0 +OP4 E000D0 0 +OP4 E000D1 0 +OP4 E000D2 0 +OP4 E000D3 0 +OP4 E000D4 0 +OP4 E000D5 0 +OP4 E000D6 0 +OP4 E000D7 0 +OP4 E000D8 0 +OP4 E000D9 0 +OP4 E000DA 0 +OP4 E000DB 0 +OP4 E000DC 0 +OP4 E000DD 0 +OP4 E000DE 0 +OP4 E000DF 0 +OP4 E000E0 0 +OP4 E000E1 0 +OP4 E000E2 0 +OP4 E000E3 0 +OP4 E000E4 0 +OP4 E000E5 0 +OP4 E000E6 0 +OP4 E000E7 0 +OP4 E000E8 0 +OP4 E000E9 0 +OP4 E000EA 0 +OP4 E000EB 0 +OP4 E000EC 0 +OP4 E000ED 0 +OP4 E000EE 0 +OP4 E000EF 0 +OP4 E000F0 0 +OP4 E000F1 0 +OP4 E000F2 0 +OP4 E000F3 0 +OP4 E000F4 0 +OP4 E000F5 0 +OP4 E000F6 0 +OP4 E000F7 0 +OP4 E000F8 0 +OP4 E000F9 0 +OP4 E000FA 0 +OP4 E000FB 0 +OP4 E000FC 0 +OP4 E000FD 0 +OP4 E000FE 0 +OP4 E000FF 0 +OP4 E00100 0 +OP4 E00101 0 +OP4 E00102 0 +OP4 E00103 0 +OP4 E00104 0 +OP4 E00105 0 +OP4 E00106 0 +OP4 E00107 0 +OP4 E00108 0 +OP4 E00109 0 +OP4 E0010A 0 +OP4 E0010B 0 +OP4 E0010C 0 +OP4 E0010D 0 +OP4 E0010E 0 +OP4 E0010F 0 +OP4 E00110 0 +OP4 E00111 0 +OP4 E00112 0 +OP4 E00113 0 +OP4 E00114 0 +OP4 E00115 0 +OP4 E00116 0 +OP4 E00117 0 +OP4 E00118 0 +OP4 E00119 0 +OP4 E0011A 0 +OP4 E0011B 0 +OP4 E0011C 0 +OP4 E0011D 0 +OP4 E0011E 0 +OP4 E0011F 0 +OP4 E00120 0 +OP4 E00121 0 +OP4 E00122 0 +OP4 E00123 0 +OP4 E00124 0 +OP4 E00125 0 +OP4 E00126 0 +OP4 E00127 0 +OP4 E00128 0 +OP4 E00129 0 +OP4 E0012A 0 +OP4 E0012B 0 +OP4 E0012C 0 +OP4 E0012D 0 +OP4 E0012E 0 +OP4 E0012F 0 +OP4 E00130 0 +OP4 E00131 0 +OP4 E00132 0 +OP4 E00133 0 +OP4 E00134 0 +OP4 E00135 0 +OP4 E00136 0 +OP4 E00137 0 +OP4 E00138 0 +OP4 E00139 0 +OP4 E0013A 0 +OP4 E0013B 0 +OP4 E0013C 0 +OP4 E0013D 0 +OP4 E0013E 0 +OP4 E0013F 0 +OP4 E00140 0 +OP4 E00141 0 +OP4 E00142 0 +OP4 E00143 0 +OP4 E00144 0 +OP4 E00145 0 +OP4 E00146 0 +OP4 E00147 0 +OP4 E00148 0 +OP4 E00149 0 +OP4 E0014A 0 +OP4 E0014B 0 +OP4 E0014C 0 +OP4 E0014D 0 +OP4 E0014E 0 +OP4 E0014F 0 +OP4 E00150 0 +OP4 E00151 0 +OP4 E00152 0 +OP4 E00153 0 +OP4 E00154 0 +OP4 E00155 0 +OP4 E00156 0 +OP4 E00157 0 +OP4 E00158 0 +OP4 E00159 0 +OP4 E0015A 0 +OP4 E0015B 0 +OP4 E0015C 0 +OP4 E0015D 0 +OP4 E0015E 0 +OP4 E0015F 0 +OP4 E00160 0 +OP4 E00161 0 +OP4 E00162 0 +OP4 E00163 0 +OP4 E00164 0 +OP4 E00165 0 +OP4 E00166 0 +OP4 E00167 0 +OP4 E00168 0 +OP4 E00169 0 +OP4 E0016A 0 +OP4 E0016B 0 +OP4 E0016C 0 +OP4 E0016D 0 +OP4 E0016E 0 +OP4 E0016F 0 +OP4 E00170 0 +OP4 E00171 0 +OP4 E00172 0 +OP4 E00173 0 +OP4 E00174 0 +OP4 E00175 0 +OP4 E00176 0 +OP4 E00177 0 +OP4 E00178 0 +OP4 E00179 0 +OP4 E0017A 0 +OP4 E0017B 0 +OP4 E0017C 0 +OP4 E0017D 0 +OP4 E0017E 0 +OP4 E0017F 0 +OP4 E00180 0 +OP4 E00181 0 +OP4 E00182 0 +OP4 E00183 0 +OP4 E00184 0 +OP4 E00185 0 +OP4 E00186 0 +OP4 E00187 0 +OP4 E00188 0 +OP4 E00189 0 +OP4 E0018A 0 +OP4 E0018B 0 +OP4 E0018C 0 +OP4 E0018D 0 +OP4 E0018E 0 +OP4 E0018F 0 +OP4 E00190 0 +OP4 E00191 0 +OP4 E00192 0 +OP4 E00193 0 +OP4 E00194 0 +OP4 E00195 0 +OP4 E00196 0 +OP4 E00197 0 +OP4 E00198 0 +OP4 E00199 0 +OP4 E0019A 0 +OP4 E0019B 0 +OP4 E0019C 0 +OP4 E0019D 0 +OP4 E0019E 0 +OP4 E0019F 0 +OP4 E001A0 0 +OP4 E001A1 0 +OP4 E001A2 0 +OP4 E001A3 0 +OP4 E001A4 0 +OP4 E001A5 0 +OP4 E001A6 0 +OP4 E001A7 0 +OP4 E001A8 0 +OP4 E001A9 0 +OP4 E001AA 0 +OP4 E001AB 0 +OP4 E001AC 0 +OP4 E001AD 0 +OP4 E001AE 0 +OP4 E001AF 0 +OP4 E001B0 0 +OP4 E001B1 0 +OP4 E001B2 0 +OP4 E001B3 0 +OP4 E001B4 0 +OP4 E001B5 0 +OP4 E001B6 0 +OP4 E001B7 0 +OP4 E001B8 0 +OP4 E001B9 0 +OP4 E001BA 0 +OP4 E001BB 0 +OP4 E001BC 0 +OP4 E001BD 0 +OP4 E001BE 0 +OP4 E001BF 0 +OP4 E001C0 0 +OP4 E001C1 0 +OP4 E001C2 0 +OP4 E001C3 0 +OP4 E001C4 0 +OP4 E001C5 0 +OP4 E001C6 0 +OP4 E001C7 0 +OP4 E001C8 0 +OP4 E001C9 0 +OP4 E001CA 0 +OP4 E001CB 0 +OP4 E001CC 0 +OP4 E001CD 0 +OP4 E001CE 0 +OP4 E001CF 0 +OP4 E001D0 0 +OP4 E001D1 0 +OP4 E001D2 0 +OP4 E001D3 0 +OP4 E001D4 0 +OP4 E001D5 0 +OP4 E001D6 0 +OP4 E001D7 0 +OP4 E001D8 0 +OP4 E001D9 0 +OP4 E001DA 0 +OP4 E001DB 0 +OP4 E001DC 0 +OP4 E001DD 0 +OP4 E001DE 0 +OP4 E001DF 0 +OP4 E001E0 0 +OP4 E001E1 0 +OP4 E001E2 0 +OP4 E001E3 0 +OP4 E001E4 0 +OP4 E001E5 0 +OP4 E001E6 0 +OP4 E001E7 0 +OP4 E001E8 0 +OP4 E001E9 0 +OP4 E001EA 0 +OP4 E001EB 0 +OP4 E001EC 0 +OP4 E001ED 0 +OP4 E001EE 0 +OP4 E001EF 0 +OP4 E001F0 0 +OP4 E001F1 0 +OP4 E001F2 0 +OP4 E001F3 0 +OP4 E001F4 0 +OP4 E001F5 0 +OP4 E001F6 0 +OP4 E001F7 0 +OP4 E001F8 0 +OP4 E001F9 0 +OP4 E001FA 0 +OP4 E001FB 0 +OP4 E001FC 0 +OP4 E001FD 0 +OP4 E001FE 0 +OP4 E001FF 0 +OP4 E00200 0 +OP4 E00201 0 +OP4 E00202 0 +OP4 E00203 0 +OP4 E00204 0 +OP4 E00205 0 +OP4 E00206 0 +OP4 E00207 0 +OP4 E00208 0 +OP4 E00209 0 +OP4 E0020A 0 +OP4 E0020B 0 +OP4 E0020C 0 +OP4 E0020D 0 +OP4 E0020E 0 +OP4 E0020F 0 +OP4 E00210 0 +OP4 E00211 0 +OP4 E00212 0 +OP4 E00213 0 +OP4 E00214 0 +OP4 E00215 0 +OP4 E00216 0 +OP4 E00217 0 +OP4 E00218 0 +OP4 E00219 0 +OP4 E0021A 0 +OP4 E0021B 0 +OP4 E0021C 0 +OP4 E0021D 0 +OP4 E0021E 0 +OP4 E0021F 0 +OP4 E00220 0 +OP4 E00221 0 +OP4 E00222 0 +OP4 E00223 0 +OP4 E00224 0 +OP4 E00225 0 +OP4 E00226 0 +OP4 E00227 0 +OP4 E00228 0 +OP4 E00229 0 +OP4 E0022A 0 +OP4 E0022B 0 +OP4 E0022C 0 +OP4 E0022D 0 +OP4 E0022E 0 +OP4 E0022F 0 +OP4 E00230 0 +OP4 E00231 0 +OP4 E00232 0 +OP4 E00233 0 +OP4 E00234 0 +OP4 E00235 0 +OP4 E00236 0 +OP4 E00237 0 +OP4 E00238 0 +OP4 E00239 0 +OP4 E0023A 0 +OP4 E0023B 0 +OP4 E0023C 0 +OP4 E0023D 0 +OP4 E0023E 0 +OP4 E0023F 0 +OP4 E00240 0 +OP4 E00241 0 +OP4 E00242 0 +OP4 E00243 0 +OP4 E00244 0 +OP4 E00245 0 +OP4 E00246 0 +OP4 E00247 0 +OP4 E00248 0 +OP4 E00249 0 +OP4 E0024A 0 +OP4 E0024B 0 +OP4 E0024C 0 +OP4 E0024D 0 +OP4 E0024E 0 +OP4 E0024F 0 +OP4 E00250 0 +OP4 E00251 0 +OP4 E00252 0 +OP4 E00253 0 +OP4 E00254 0 +OP4 E00255 0 +OP4 E00256 0 +OP4 E00257 0 +OP4 E00258 0 +OP4 E00259 0 +OP4 E0025A 0 +OP4 E0025B 0 +OP4 E0025C 0 +OP4 E0025D 0 +OP4 E0025E 0 +OP4 E0025F 0 +OP4 E00260 0 +OP4 E00261 0 +OP4 E00262 0 +OP4 E00263 0 +OP4 E00264 0 +OP4 E00265 0 +OP4 E00266 0 +OP4 E00267 0 +OP4 E00268 0 +OP4 E00269 0 +OP4 E0026A 0 +OP4 E0026B 0 +OP4 E0026C 0 +OP4 E0026D 0 +OP4 E0026E 0 +OP4 E0026F 0 +OP4 E00270 0 +OP4 E00271 0 +OP4 E00272 0 +OP4 E00273 0 +OP4 E00274 0 +OP4 E00275 0 +OP4 E00276 0 +OP4 E00277 0 +OP4 E00278 0 +OP4 E00279 0 +OP4 E0027A 0 +OP4 E0027B 0 +OP4 E0027C 0 +OP4 E0027D 0 +OP4 E0027E 0 +OP4 E0027F 0 +OP4 E00280 0 +OP4 E00281 0 +OP4 E00282 0 +OP4 E00283 0 +OP4 E00284 0 +OP4 E00285 0 +OP4 E00286 0 +OP4 E00287 0 +OP4 E00288 0 +OP4 E00289 0 +OP4 E0028A 0 +OP4 E0028B 0 +OP4 E0028C 0 +OP4 E0028D 0 +OP4 E0028E 0 +OP4 E0028F 0 +OP4 E00290 0 +OP4 E00291 0 +OP4 E00292 0 +OP4 E00293 0 +OP4 E00294 0 +OP4 E00295 0 +OP4 E00296 0 +OP4 E00297 0 +OP4 E00298 0 +OP4 E00299 0 +OP4 E0029A 0 +OP4 E0029B 0 +OP4 E0029C 0 +OP4 E0029D 0 +OP4 E0029E 0 +OP4 E0029F 0 +OP4 E002A0 0 +OP4 E002A1 0 +OP4 E002A2 0 +OP4 E002A3 0 +OP4 E002A4 0 +OP4 E002A5 0 +OP4 E002A6 0 +OP4 E002A7 0 +OP4 E002A8 0 +OP4 E002A9 0 +OP4 E002AA 0 +OP4 E002AB 0 +OP4 E002AC 0 +OP4 E002AD 0 +OP4 E002AE 0 +OP4 E002AF 0 +OP4 E002B0 0 +OP4 E002B1 0 +OP4 E002B2 0 +OP4 E002B3 0 +OP4 E002B4 0 +OP4 E002B5 0 +OP4 E002B6 0 +OP4 E002B7 0 +OP4 E002B8 0 +OP4 E002B9 0 +OP4 E002BA 0 +OP4 E002BB 0 +OP4 E002BC 0 +OP4 E002BD 0 +OP4 E002BE 0 +OP4 E002BF 0 +OP4 E002C0 0 +OP4 E002C1 0 +OP4 E002C2 0 +OP4 E002C3 0 +OP4 E002C4 0 +OP4 E002C5 0 +OP4 E002C6 0 +OP4 E002C7 0 +OP4 E002C8 0 +OP4 E002C9 0 +OP4 E002CA 0 +OP4 E002CB 0 +OP4 E002CC 0 +OP4 E002CD 0 +OP4 E002CE 0 +OP4 E002CF 0 +OP4 E002D0 0 +OP4 E002D1 0 +OP4 E002D2 0 +OP4 E002D3 0 +OP4 E002D4 0 +OP4 E002D5 0 +OP4 E002D6 0 +OP4 E002D7 0 +OP4 E002D8 0 +OP4 E002D9 0 +OP4 E002DA 0 +OP4 E002DB 0 +OP4 E002DC 0 +OP4 E002DD 0 +OP4 E002DE 0 +OP4 E002DF 0 +OP4 E002E0 0 +OP4 E002E1 0 +OP4 E002E2 0 +OP4 E002E3 0 +OP4 E002E4 0 +OP4 E002E5 0 +OP4 E002E6 0 +OP4 E002E7 0 +OP4 E002E8 0 +OP4 E002E9 0 +OP4 E002EA 0 +OP4 E002EB 0 +OP4 E002EC 0 +OP4 E002ED 0 +OP4 E002EE 0 +OP4 E002EF 0 +OP4 E002F0 0 +OP4 E002F1 0 +OP4 E002F2 0 +OP4 E002F3 0 +OP4 E002F4 0 +OP4 E002F5 0 +OP4 E002F6 0 +OP4 E002F7 0 +OP4 E002F8 0 +OP4 E002F9 0 +OP4 E002FA 0 +OP4 E002FB 0 +OP4 E002FC 0 +OP4 E002FD 0 +OP4 E002FE 0 +OP4 E002FF 0 +OP4 E00300 0 +OP4 E00301 0 +OP4 E00302 0 +OP4 E00303 0 +OP4 E00304 0 +OP4 E00305 0 +OP4 E00306 0 +OP4 E00307 0 +OP4 E00308 0 +OP4 E00309 0 +OP4 E0030A 0 +OP4 E0030B 0 +OP4 E0030C 0 +OP4 E0030D 0 +OP4 E0030E 0 +OP4 E0030F 0 +OP4 E00310 0 +OP4 E00311 0 +OP4 E00312 0 +OP4 E00313 0 +OP4 E00314 0 +OP4 E00315 0 +OP4 E00316 0 +OP4 E00317 0 +OP4 E00318 0 +OP4 E00319 0 +OP4 E0031A 0 +OP4 E0031B 0 +OP4 E0031C 0 +OP4 E0031D 0 +OP4 E0031E 0 +OP4 E0031F 0 +OP4 E00320 0 +OP4 E00321 0 +OP4 E00322 0 +OP4 E00323 0 +OP4 E00324 0 +OP4 E00325 0 +OP4 E00326 0 +OP4 E00327 0 +OP4 E00328 0 +OP4 E00329 0 +OP4 E0032A 0 +OP4 E0032B 0 +OP4 E0032C 0 +OP4 E0032D 0 +OP4 E0032E 0 +OP4 E0032F 0 +OP4 E00330 0 +OP4 E00331 0 +OP4 E00332 0 +OP4 E00333 0 +OP4 E00334 0 +OP4 E00335 0 +OP4 E00336 0 +OP4 E00337 0 +OP4 E00338 0 +OP4 E00339 0 +OP4 E0033A 0 +OP4 E0033B 0 +OP4 E0033C 0 +OP4 E0033D 0 +OP4 E0033E 0 +OP4 E0033F 0 +OP4 E00340 0 +OP4 E00341 0 +OP4 E00342 0 +OP4 E00343 0 +OP4 E00344 0 +OP4 E00345 0 +OP4 E00346 0 +OP4 E00347 0 +OP4 E00348 0 +OP4 E00349 0 +OP4 E0034A 0 +OP4 E0034B 0 +OP4 E0034C 0 +OP4 E0034D 0 +OP4 E0034E 0 +OP4 E0034F 0 +OP4 E00350 0 +OP4 E00351 0 +OP4 E00352 0 +OP4 E00353 0 +OP4 E00354 0 +OP4 E00355 0 +OP4 E00356 0 +OP4 E00357 0 +OP4 E00358 0 +OP4 E00359 0 +OP4 E0035A 0 +OP4 E0035B 0 +OP4 E0035C 0 +OP4 E0035D 0 +OP4 E0035E 0 +OP4 E0035F 0 +OP4 E00360 0 +OP4 E00361 0 +OP4 E00362 0 +OP4 E00363 0 +OP4 E00364 0 +OP4 E00365 0 +OP4 E00366 0 +OP4 E00367 0 +OP4 E00368 0 +OP4 E00369 0 +OP4 E0036A 0 +OP4 E0036B 0 +OP4 E0036C 0 +OP4 E0036D 0 +OP4 E0036E 0 +OP4 E0036F 0 +OP4 E00370 0 +OP4 E00371 0 +OP4 E00372 0 +OP4 E00373 0 +OP4 E00374 0 +OP4 E00375 0 +OP4 E00376 0 +OP4 E00377 0 +OP4 E00378 0 +OP4 E00379 0 +OP4 E0037A 0 +OP4 E0037B 0 +OP4 E0037C 0 +OP4 E0037D 0 +OP4 E0037E 0 +OP4 E0037F 0 +OP4 E00380 0 +OP4 E00381 0 +OP4 E00382 0 +OP4 E00383 0 +OP4 E00384 0 +OP4 E00385 0 +OP4 E00386 0 +OP4 E00387 0 +OP4 E00388 0 +OP4 E00389 0 +OP4 E0038A 0 +OP4 E0038B 0 +OP4 E0038C 0 +OP4 E0038D 0 +OP4 E0038E 0 +OP4 E0038F 0 +OP4 E00390 0 +OP4 E00391 0 +OP4 E00392 0 +OP4 E00393 0 +OP4 E00394 0 +OP4 E00395 0 +OP4 E00396 0 +OP4 E00397 0 +OP4 E00398 0 +OP4 E00399 0 +OP4 E0039A 0 +OP4 E0039B 0 +OP4 E0039C 0 +OP4 E0039D 0 +OP4 E0039E 0 +OP4 E0039F 0 +OP4 E003A0 0 +OP4 E003A1 0 +OP4 E003A2 0 +OP4 E003A3 0 +OP4 E003A4 0 +OP4 E003A5 0 +OP4 E003A6 0 +OP4 E003A7 0 +OP4 E003A8 0 +OP4 E003A9 0 +OP4 E003AA 0 +OP4 E003AB 0 +OP4 E003AC 0 +OP4 E003AD 0 +OP4 E003AE 0 +OP4 E003AF 0 +OP4 E003B0 0 +OP4 E003B1 0 +OP4 E003B2 0 +OP4 E003B3 0 +OP4 E003B4 0 +OP4 E003B5 0 +OP4 E003B6 0 +OP4 E003B7 0 +OP4 E003B8 0 +OP4 E003B9 0 +OP4 E003BA 0 +OP4 E003BB 0 +OP4 E003BC 0 +OP4 E003BD 0 +OP4 E003BE 0 +OP4 E003BF 0 +OP4 E003C0 0 +OP4 E003C1 0 +OP4 E003C2 0 +OP4 E003C3 0 +OP4 E003C4 0 +OP4 E003C5 0 +OP4 E003C6 0 +OP4 E003C7 0 +OP4 E003C8 0 +OP4 E003C9 0 +OP4 E003CA 0 +OP4 E003CB 0 +OP4 E003CC 0 +OP4 E003CD 0 +OP4 E003CE 0 +OP4 E003CF 0 +OP4 E003D0 0 +OP4 E003D1 0 +OP4 E003D2 0 +OP4 E003D3 0 +OP4 E003D4 0 +OP4 E003D5 0 +OP4 E003D6 0 +OP4 E003D7 0 +OP4 E003D8 0 +OP4 E003D9 0 +OP4 E003DA 0 +OP4 E003DB 0 +OP4 E003DC 0 +OP4 E003DD 0 +OP4 E003DE 0 +OP4 E003DF 0 +OP4 E003E0 0 +OP4 E003E1 0 +OP4 E003E2 0 +OP4 E003E3 0 +OP4 E003E4 0 +OP4 E003E5 0 +OP4 E003E6 0 +OP4 E003E7 0 +OP4 E003E8 0 +OP4 E003E9 0 +OP4 E003EA 0 +OP4 E003EB 0 +OP4 E003EC 0 +OP4 E003ED 0 +OP4 E003EE 0 +OP4 E003EF 0 +OP4 E003F0 0 +OP4 E003F1 0 +OP4 E003F2 0 +OP4 E003F3 0 +OP4 E003F4 0 +OP4 E003F5 0 +OP4 E003F6 0 +OP4 E003F7 0 +OP4 E003F8 0 +OP4 E003F9 0 +OP4 E003FA 0 +OP4 E003FB 0 +OP4 E003FC 0 +OP4 E003FD 0 +OP4 E003FE 0 +OP4 E003FF 0 +OP4 E00400 0 +OP4 E00401 0 +OP4 E00402 0 +OP4 E00403 0 +OP4 E00404 0 +OP4 E00405 0 +OP4 E00406 0 +OP4 E00407 0 +OP4 E00408 0 +OP4 E00409 0 +OP4 E0040A 0 +OP4 E0040B 0 +OP4 E0040C 0 +OP4 E0040D 0 +OP4 E0040E 0 +OP4 E0040F 0 +OP4 E00410 0 +OP4 E00411 0 +OP4 E00412 0 +OP4 E00413 0 +OP4 E00414 0 +OP4 E00415 0 +OP4 E00416 0 +OP4 E00417 0 +OP4 E00418 0 +OP4 E00419 0 +OP4 E0041A 0 +OP4 E0041B 0 +OP4 E0041C 0 +OP4 E0041D 0 +OP4 E0041E 0 +OP4 E0041F 0 +OP4 E00420 0 +OP4 E00421 0 +OP4 E00422 0 +OP4 E00423 0 +OP4 E00424 0 +OP4 E00425 0 +OP4 E00426 0 +OP4 E00427 0 +OP4 E00428 0 +OP4 E00429 0 +OP4 E0042A 0 +OP4 E0042B 0 +OP4 E0042C 0 +OP4 E0042D 0 +OP4 E0042E 0 +OP4 E0042F 0 +OP4 E00430 0 +OP4 E00431 0 +OP4 E00432 0 +OP4 E00433 0 +OP4 E00434 0 +OP4 E00435 0 +OP4 E00436 0 +OP4 E00437 0 +OP4 E00438 0 +OP4 E00439 0 +OP4 E0043A 0 +OP4 E0043B 0 +OP4 E0043C 0 +OP4 E0043D 0 +OP4 E0043E 0 +OP4 E0043F 0 +OP4 E00440 0 +OP4 E00441 0 +OP4 E00442 0 +OP4 E00443 0 +OP4 E00444 0 +OP4 E00445 0 +OP4 E00446 0 +OP4 E00447 0 +OP4 E00448 0 +OP4 E00449 0 +OP4 E0044A 0 +OP4 E0044B 0 +OP4 E0044C 0 +OP4 E0044D 0 +OP4 E0044E 0 +OP4 E0044F 0 +OP4 E00450 0 +OP4 E00451 0 +OP4 E00452 0 +OP4 E00453 0 +OP4 E00454 0 +OP4 E00455 0 +OP4 E00456 0 +OP4 E00457 0 +OP4 E00458 0 +OP4 E00459 0 +OP4 E0045A 0 +OP4 E0045B 0 +OP4 E0045C 0 +OP4 E0045D 0 +OP4 E0045E 0 +OP4 E0045F 0 +OP4 E00460 0 +OP4 E00461 0 +OP4 E00462 0 +OP4 E00463 0 +OP4 E00464 0 +OP4 E00465 0 +OP4 E00466 0 +OP4 E00467 0 +OP4 E00468 0 +OP4 E00469 0 +OP4 E0046A 0 +OP4 E0046B 0 +OP4 E0046C 0 +OP4 E0046D 0 +OP4 E0046E 0 +OP4 E0046F 0 +OP4 E00470 0 +OP4 E00471 0 +OP4 E00472 0 +OP4 E00473 0 +OP4 E00474 0 +OP4 E00475 0 +OP4 E00476 0 +OP4 E00477 0 +OP4 E00478 0 +OP4 E00479 0 +OP4 E0047A 0 +OP4 E0047B 0 +OP4 E0047C 0 +OP4 E0047D 0 +OP4 E0047E 0 +OP4 E0047F 0 +OP4 E00480 0 +OP4 E00481 0 +OP4 E00482 0 +OP4 E00483 0 +OP4 E00484 0 +OP4 E00485 0 +OP4 E00486 0 +OP4 E00487 0 +OP4 E00488 0 +OP4 E00489 0 +OP4 E0048A 0 +OP4 E0048B 0 +OP4 E0048C 0 +OP4 E0048D 0 +OP4 E0048E 0 +OP4 E0048F 0 +OP4 E00490 0 +OP4 E00491 0 +OP4 E00492 0 +OP4 E00493 0 +OP4 E00494 0 +OP4 E00495 0 +OP4 E00496 0 +OP4 E00497 0 +OP4 E00498 0 +OP4 E00499 0 +OP4 E0049A 0 +OP4 E0049B 0 +OP4 E0049C 0 +OP4 E0049D 0 +OP4 E0049E 0 +OP4 E0049F 0 +OP4 E004A0 0 +OP4 E004A1 0 +OP4 E004A2 0 +OP4 E004A3 0 +OP4 E004A4 0 +OP4 E004A5 0 +OP4 E004A6 0 +OP4 E004A7 0 +OP4 E004A8 0 +OP4 E004A9 0 +OP4 E004AA 0 +OP4 E004AB 0 +OP4 E004AC 0 +OP4 E004AD 0 +OP4 E004AE 0 +OP4 E004AF 0 +OP4 E004B0 0 +OP4 E004B1 0 +OP4 E004B2 0 +OP4 E004B3 0 +OP4 E004B4 0 +OP4 E004B5 0 +OP4 E004B6 0 +OP4 E004B7 0 +OP4 E004B8 0 +OP4 E004B9 0 +OP4 E004BA 0 +OP4 E004BB 0 +OP4 E004BC 0 +OP4 E004BD 0 +OP4 E004BE 0 +OP4 E004BF 0 +OP4 E004C0 0 +OP4 E004C1 0 +OP4 E004C2 0 +OP4 E004C3 0 +OP4 E004C4 0 +OP4 E004C5 0 +OP4 E004C6 0 +OP4 E004C7 0 +OP4 E004C8 0 +OP4 E004C9 0 +OP4 E004CA 0 +OP4 E004CB 0 +OP4 E004CC 0 +OP4 E004CD 0 +OP4 E004CE 0 +OP4 E004CF 0 +OP4 E004D0 0 +OP4 E004D1 0 +OP4 E004D2 0 +OP4 E004D3 0 +OP4 E004D4 0 +OP4 E004D5 0 +OP4 E004D6 0 +OP4 E004D7 0 +OP4 E004D8 0 +OP4 E004D9 0 +OP4 E004DA 0 +OP4 E004DB 0 +OP4 E004DC 0 +OP4 E004DD 0 +OP4 E004DE 0 +OP4 E004DF 0 +OP4 E004E0 0 +OP4 E004E1 0 +OP4 E004E2 0 +OP4 E004E3 0 +OP4 E004E4 0 +OP4 E004E5 0 +OP4 E004E6 0 +OP4 E004E7 0 +OP4 E004E8 0 +OP4 E004E9 0 +OP4 E004EA 0 +OP4 E004EB 0 +OP4 E004EC 0 +OP4 E004ED 0 +OP4 E004EE 0 +OP4 E004EF 0 +OP4 E004F0 0 +OP4 E004F1 0 +OP4 E004F2 0 +OP4 E004F3 0 +OP4 E004F4 0 +OP4 E004F5 0 +OP4 E004F6 0 +OP4 E004F7 0 +OP4 E004F8 0 +OP4 E004F9 0 +OP4 E004FA 0 +OP4 E004FB 0 +OP4 E004FC 0 +OP4 E004FD 0 +OP4 E004FE 0 +OP4 E004FF 0 +OP4 E00500 0 +OP4 E00501 0 +OP4 E00502 0 +OP4 E00503 0 +OP4 E00504 0 +OP4 E00505 0 +OP4 E00506 0 +OP4 E00507 0 +OP4 E00508 0 +OP4 E00509 0 +OP4 E0050A 0 +OP4 E0050B 0 +OP4 E0050C 0 +OP4 E0050D 0 +OP4 E0050E 0 +OP4 E0050F 0 +OP4 E00510 0 +OP4 E00511 0 +OP4 E00512 0 +OP4 E00513 0 +OP4 E00514 0 +OP4 E00515 0 +OP4 E00516 0 +OP4 E00517 0 +OP4 E00518 0 +OP4 E00519 0 +OP4 E0051A 0 +OP4 E0051B 0 +OP4 E0051C 0 +OP4 E0051D 0 +OP4 E0051E 0 +OP4 E0051F 0 +OP4 E00520 0 +OP4 E00521 0 +OP4 E00522 0 +OP4 E00523 0 +OP4 E00524 0 +OP4 E00525 0 +OP4 E00526 0 +OP4 E00527 0 +OP4 E00528 0 +OP4 E00529 0 +OP4 E0052A 0 +OP4 E0052B 0 +OP4 E0052C 0 +OP4 E0052D 0 +OP4 E0052E 0 +OP4 E0052F 0 +OP4 E00530 0 +OP4 E00531 0 +OP4 E00532 0 +OP4 E00533 0 +OP4 E00534 0 +OP4 E00535 0 +OP4 E00536 0 +OP4 E00537 0 +OP4 E00538 0 +OP4 E00539 0 +OP4 E0053A 0 +OP4 E0053B 0 +OP4 E0053C 0 +OP4 E0053D 0 +OP4 E0053E 0 +OP4 E0053F 0 +OP4 E00540 0 +OP4 E00541 0 +OP4 E00542 0 +OP4 E00543 0 +OP4 E00544 0 +OP4 E00545 0 +OP4 E00546 0 +OP4 E00547 0 +OP4 E00548 0 +OP4 E00549 0 +OP4 E0054A 0 +OP4 E0054B 0 +OP4 E0054C 0 +OP4 E0054D 0 +OP4 E0054E 0 +OP4 E0054F 0 +OP4 E00550 0 +OP4 E00551 0 +OP4 E00552 0 +OP4 E00553 0 +OP4 E00554 0 +OP4 E00555 0 +OP4 E00556 0 +OP4 E00557 0 +OP4 E00558 0 +OP4 E00559 0 +OP4 E0055A 0 +OP4 E0055B 0 +OP4 E0055C 0 +OP4 E0055D 0 +OP4 E0055E 0 +OP4 E0055F 0 +OP4 E00560 0 +OP4 E00561 0 +OP4 E00562 0 +OP4 E00563 0 +OP4 E00564 0 +OP4 E00565 0 +OP4 E00566 0 +OP4 E00567 0 +OP4 E00568 0 +OP4 E00569 0 +OP4 E0056A 0 +OP4 E0056B 0 +OP4 E0056C 0 +OP4 E0056D 0 +OP4 E0056E 0 +OP4 E0056F 0 +OP4 E00570 0 +OP4 E00571 0 +OP4 E00572 0 +OP4 E00573 0 +OP4 E00574 0 +OP4 E00575 0 +OP4 E00576 0 +OP4 E00577 0 +OP4 E00578 0 +OP4 E00579 0 +OP4 E0057A 0 +OP4 E0057B 0 +OP4 E0057C 0 +OP4 E0057D 0 +OP4 E0057E 0 +OP4 E0057F 0 +OP4 E00580 0 +OP4 E00581 0 +OP4 E00582 0 +OP4 E00583 0 +OP4 E00584 0 +OP4 E00585 0 +OP4 E00586 0 +OP4 E00587 0 +OP4 E00588 0 +OP4 E00589 0 +OP4 E0058A 0 +OP4 E0058B 0 +OP4 E0058C 0 +OP4 E0058D 0 +OP4 E0058E 0 +OP4 E0058F 0 +OP4 E00590 0 +OP4 E00591 0 +OP4 E00592 0 +OP4 E00593 0 +OP4 E00594 0 +OP4 E00595 0 +OP4 E00596 0 +OP4 E00597 0 +OP4 E00598 0 +OP4 E00599 0 +OP4 E0059A 0 +OP4 E0059B 0 +OP4 E0059C 0 +OP4 E0059D 0 +OP4 E0059E 0 +OP4 E0059F 0 +OP4 E005A0 0 +OP4 E005A1 0 +OP4 E005A2 0 +OP4 E005A3 0 +OP4 E005A4 0 +OP4 E005A5 0 +OP4 E005A6 0 +OP4 E005A7 0 +OP4 E005A8 0 +OP4 E005A9 0 +OP4 E005AA 0 +OP4 E005AB 0 +OP4 E005AC 0 +OP4 E005AD 0 +OP4 E005AE 0 +OP4 E005AF 0 +OP4 E005B0 0 +OP4 E005B1 0 +OP4 E005B2 0 +OP4 E005B3 0 +OP4 E005B4 0 +OP4 E005B5 0 +OP4 E005B6 0 +OP4 E005B7 0 +OP4 E005B8 0 +OP4 E005B9 0 +OP4 E005BA 0 +OP4 E005BB 0 +OP4 E005BC 0 +OP4 E005BD 0 +OP4 E005BE 0 +OP4 E005BF 0 +OP4 E005C0 0 +OP4 E005C1 0 +OP4 E005C2 0 +OP4 E005C3 0 +OP4 E005C4 0 +OP4 E005C5 0 +OP4 E005C6 0 +OP4 E005C7 0 +OP4 E005C8 0 +OP4 E005C9 0 +OP4 E005CA 0 +OP4 E005CB 0 +OP4 E005CC 0 +OP4 E005CD 0 +OP4 E005CE 0 +OP4 E005CF 0 +OP4 E005D0 0 +OP4 E005D1 0 +OP4 E005D2 0 +OP4 E005D3 0 +OP4 E005D4 0 +OP4 E005D5 0 +OP4 E005D6 0 +OP4 E005D7 0 +OP4 E005D8 0 +OP4 E005D9 0 +OP4 E005DA 0 +OP4 E005DB 0 +OP4 E005DC 0 +OP4 E005DD 0 +OP4 E005DE 0 +OP4 E005DF 0 +OP4 E005E0 0 +OP4 E005E1 0 +OP4 E005E2 0 +OP4 E005E3 0 +OP4 E005E4 0 +OP4 E005E5 0 +OP4 E005E6 0 +OP4 E005E7 0 +OP4 E005E8 0 +OP4 E005E9 0 +OP4 E005EA 0 +OP4 E005EB 0 +OP4 E005EC 0 +OP4 E005ED 0 +OP4 E005EE 0 +OP4 E005EF 0 +OP4 E005F0 0 +OP4 E005F1 0 +OP4 E005F2 0 +OP4 E005F3 0 +OP4 E005F4 0 +OP4 E005F5 0 +OP4 E005F6 0 +OP4 E005F7 0 +OP4 E005F8 0 +OP4 E005F9 0 +OP4 E005FA 0 +OP4 E005FB 0 +OP4 E005FC 0 +OP4 E005FD 0 +OP4 E005FE 0 +OP4 E005FF 0 +OP4 E00600 0 +OP4 E00601 0 +OP4 E00602 0 +OP4 E00603 0 +OP4 E00604 0 +OP4 E00605 0 +OP4 E00606 0 +OP4 E00607 0 +OP4 E00608 0 +OP4 E00609 0 +OP4 E0060A 0 +OP4 E0060B 0 +OP4 E0060C 0 +OP4 E0060D 0 +OP4 E0060E 0 +OP4 E0060F 0 +OP4 E00610 0 +OP4 E00611 0 +OP4 E00612 0 +OP4 E00613 0 +OP4 E00614 0 +OP4 E00615 0 +OP4 E00616 0 +OP4 E00617 0 +OP4 E00618 0 +OP4 E00619 0 +OP4 E0061A 0 +OP4 E0061B 0 +OP4 E0061C 0 +OP4 E0061D 0 +OP4 E0061E 0 +OP4 E0061F 0 +OP4 E00620 0 +OP4 E00621 0 +OP4 E00622 0 +OP4 E00623 0 +OP4 E00624 0 +OP4 E00625 0 +OP4 E00626 0 +OP4 E00627 0 +OP4 E00628 0 +OP4 E00629 0 +OP4 E0062A 0 +OP4 E0062B 0 +OP4 E0062C 0 +OP4 E0062D 0 +OP4 E0062E 0 +OP4 E0062F 0 +OP4 E00630 0 +OP4 E00631 0 +OP4 E00632 0 +OP4 E00633 0 +OP4 E00634 0 +OP4 E00635 0 +OP4 E00636 0 +OP4 E00637 0 +OP4 E00638 0 +OP4 E00639 0 +OP4 E0063A 0 +OP4 E0063B 0 +OP4 E0063C 0 +OP4 E0063D 0 +OP4 E0063E 0 +OP4 E0063F 0 +OP4 E00640 0 +OP4 E00641 0 +OP4 E00642 0 +OP4 E00643 0 +OP4 E00644 0 +OP4 E00645 0 +OP4 E00646 0 +OP4 E00647 0 +OP4 E00648 0 +OP4 E00649 0 +OP4 E0064A 0 +OP4 E0064B 0 +OP4 E0064C 0 +OP4 E0064D 0 +OP4 E0064E 0 +OP4 E0064F 0 +OP4 E00650 0 +OP4 E00651 0 +OP4 E00652 0 +OP4 E00653 0 +OP4 E00654 0 +OP4 E00655 0 +OP4 E00656 0 +OP4 E00657 0 +OP4 E00658 0 +OP4 E00659 0 +OP4 E0065A 0 +OP4 E0065B 0 +OP4 E0065C 0 +OP4 E0065D 0 +OP4 E0065E 0 +OP4 E0065F 0 +OP4 E00660 0 +OP4 E00661 0 +OP4 E00662 0 +OP4 E00663 0 +OP4 E00664 0 +OP4 E00665 0 +OP4 E00666 0 +OP4 E00667 0 +OP4 E00668 0 +OP4 E00669 0 +OP4 E0066A 0 +OP4 E0066B 0 +OP4 E0066C 0 +OP4 E0066D 0 +OP4 E0066E 0 +OP4 E0066F 0 +OP4 E00670 0 +OP4 E00671 0 +OP4 E00672 0 +OP4 E00673 0 +OP4 E00674 0 +OP4 E00675 0 +OP4 E00676 0 +OP4 E00677 0 +OP4 E00678 0 +OP4 E00679 0 +OP4 E0067A 0 +OP4 E0067B 0 +OP4 E0067C 0 +OP4 E0067D 0 +OP4 E0067E 0 +OP4 E0067F 0 +OP4 E00680 0 +OP4 E00681 0 +OP4 E00682 0 +OP4 E00683 0 +OP4 E00684 0 +OP4 E00685 0 +OP4 E00686 0 +OP4 E00687 0 +OP4 E00688 0 +OP4 E00689 0 +OP4 E0068A 0 +OP4 E0068B 0 +OP4 E0068C 0 +OP4 E0068D 0 +OP4 E0068E 0 +OP4 E0068F 0 +OP4 E00690 0 +OP4 E00691 0 +OP4 E00692 0 +OP4 E00693 0 +OP4 E00694 0 +OP4 E00695 0 +OP4 E00696 0 +OP4 E00697 0 +OP4 E00698 0 +OP4 E00699 0 +OP4 E0069A 0 +OP4 E0069B 0 +OP4 E0069C 0 +OP4 E0069D 0 +OP4 E0069E 0 +OP4 E0069F 0 +OP4 E006A0 0 +OP4 E006A1 0 +OP4 E006A2 0 +OP4 E006A3 0 +OP4 E006A4 0 +OP4 E006A5 0 +OP4 E006A6 0 +OP4 E006A7 0 +OP4 E006A8 0 +OP4 E006A9 0 +OP4 E006AA 0 +OP4 E006AB 0 +OP4 E006AC 0 +OP4 E006AD 0 +OP4 E006AE 0 +OP4 E006AF 0 +OP4 E006B0 0 +OP4 E006B1 0 +OP4 E006B2 0 +OP4 E006B3 0 +OP4 E006B4 0 +OP4 E006B5 0 +OP4 E006B6 0 +OP4 E006B7 0 +OP4 E006B8 0 +OP4 E006B9 0 +OP4 E006BA 0 +OP4 E006BB 0 +OP4 E006BC 0 +OP4 E006BD 0 +OP4 E006BE 0 +OP4 E006BF 0 +OP4 E006C0 0 +OP4 E006C1 0 +OP4 E006C2 0 +OP4 E006C3 0 +OP4 E006C4 0 +OP4 E006C5 0 +OP4 E006C6 0 +OP4 E006C7 0 +OP4 E006C8 0 +OP4 E006C9 0 +OP4 E006CA 0 +OP4 E006CB 0 +OP4 E006CC 0 +OP4 E006CD 0 +OP4 E006CE 0 +OP4 E006CF 0 +OP4 E006D0 0 +OP4 E006D1 0 +OP4 E006D2 0 +OP4 E006D3 0 +OP4 E006D4 0 +OP4 E006D5 0 +OP4 E006D6 0 +OP4 E006D7 0 +OP4 E006D8 0 +OP4 E006D9 0 +OP4 E006DA 0 +OP4 E006DB 0 +OP4 E006DC 0 +OP4 E006DD 0 +OP4 E006DE 0 +OP4 E006DF 0 +OP4 E006E0 0 +OP4 E006E1 0 +OP4 E006E2 0 +OP4 E006E3 0 +OP4 E006E4 0 +OP4 E006E5 0 +OP4 E006E6 0 +OP4 E006E7 0 +OP4 E006E8 0 +OP4 E006E9 0 +OP4 E006EA 0 +OP4 E006EB 0 +OP4 E006EC 0 +OP4 E006ED 0 +OP4 E006EE 0 +OP4 E006EF 0 +OP4 E006F0 0 +OP4 E006F1 0 +OP4 E006F2 0 +OP4 E006F3 0 +OP4 E006F4 0 +OP4 E006F5 0 +OP4 E006F6 0 +OP4 E006F7 0 +OP4 E006F8 0 +OP4 E006F9 0 +OP4 E006FA 0 +OP4 E006FB 0 +OP4 E006FC 0 +OP4 E006FD 0 +OP4 E006FE 0 +OP4 E006FF 0 +OP4 E00700 0 +OP4 E00701 0 +OP4 E00702 0 +OP4 E00703 0 +OP4 E00704 0 +OP4 E00705 0 +OP4 E00706 0 +OP4 E00707 0 +OP4 E00708 0 +OP4 E00709 0 +OP4 E0070A 0 +OP4 E0070B 0 +OP4 E0070C 0 +OP4 E0070D 0 +OP4 E0070E 0 +OP4 E0070F 0 +OP4 E00710 0 +OP4 E00711 0 +OP4 E00712 0 +OP4 E00713 0 +OP4 E00714 0 +OP4 E00715 0 +OP4 E00716 0 +OP4 E00717 0 +OP4 E00718 0 +OP4 E00719 0 +OP4 E0071A 0 +OP4 E0071B 0 +OP4 E0071C 0 +OP4 E0071D 0 +OP4 E0071E 0 +OP4 E0071F 0 +OP4 E00720 0 +OP4 E00721 0 +OP4 E00722 0 +OP4 E00723 0 +OP4 E00724 0 +OP4 E00725 0 +OP4 E00726 0 +OP4 E00727 0 +OP4 E00728 0 +OP4 E00729 0 +OP4 E0072A 0 +OP4 E0072B 0 +OP4 E0072C 0 +OP4 E0072D 0 +OP4 E0072E 0 +OP4 E0072F 0 +OP4 E00730 0 +OP4 E00731 0 +OP4 E00732 0 +OP4 E00733 0 +OP4 E00734 0 +OP4 E00735 0 +OP4 E00736 0 +OP4 E00737 0 +OP4 E00738 0 +OP4 E00739 0 +OP4 E0073A 0 +OP4 E0073B 0 +OP4 E0073C 0 +OP4 E0073D 0 +OP4 E0073E 0 +OP4 E0073F 0 +OP4 E00740 0 +OP4 E00741 0 +OP4 E00742 0 +OP4 E00743 0 +OP4 E00744 0 +OP4 E00745 0 +OP4 E00746 0 +OP4 E00747 0 +OP4 E00748 0 +OP4 E00749 0 +OP4 E0074A 0 +OP4 E0074B 0 +OP4 E0074C 0 +OP4 E0074D 0 +OP4 E0074E 0 +OP4 E0074F 0 +OP4 E00750 0 +OP4 E00751 0 +OP4 E00752 0 +OP4 E00753 0 +OP4 E00754 0 +OP4 E00755 0 +OP4 E00756 0 +OP4 E00757 0 +OP4 E00758 0 +OP4 E00759 0 +OP4 E0075A 0 +OP4 E0075B 0 +OP4 E0075C 0 +OP4 E0075D 0 +OP4 E0075E 0 +OP4 E0075F 0 +OP4 E00760 0 +OP4 E00761 0 +OP4 E00762 0 +OP4 E00763 0 +OP4 E00764 0 +OP4 E00765 0 +OP4 E00766 0 +OP4 E00767 0 +OP4 E00768 0 +OP4 E00769 0 +OP4 E0076A 0 +OP4 E0076B 0 +OP4 E0076C 0 +OP4 E0076D 0 +OP4 E0076E 0 +OP4 E0076F 0 +OP4 E00770 0 +OP4 E00771 0 +OP4 E00772 0 +OP4 E00773 0 +OP4 E00774 0 +OP4 E00775 0 +OP4 E00776 0 +OP4 E00777 0 +OP4 E00778 0 +OP4 E00779 0 +OP4 E0077A 0 +OP4 E0077B 0 +OP4 E0077C 0 +OP4 E0077D 0 +OP4 E0077E 0 +OP4 E0077F 0 +OP4 E00780 0 +OP4 E00781 0 +OP4 E00782 0 +OP4 E00783 0 +OP4 E00784 0 +OP4 E00785 0 +OP4 E00786 0 +OP4 E00787 0 +OP4 E00788 0 +OP4 E00789 0 +OP4 E0078A 0 +OP4 E0078B 0 +OP4 E0078C 0 +OP4 E0078D 0 +OP4 E0078E 0 +OP4 E0078F 0 +OP4 E00790 0 +OP4 E00791 0 +OP4 E00792 0 +OP4 E00793 0 +OP4 E00794 0 +OP4 E00795 0 +OP4 E00796 0 +OP4 E00797 0 +OP4 E00798 0 +OP4 E00799 0 +OP4 E0079A 0 +OP4 E0079B 0 +OP4 E0079C 0 +OP4 E0079D 0 +OP4 E0079E 0 +OP4 E0079F 0 +OP4 E007A0 0 +OP4 E007A1 0 +OP4 E007A2 0 +OP4 E007A3 0 +OP4 E007A4 0 +OP4 E007A5 0 +OP4 E007A6 0 +OP4 E007A7 0 +OP4 E007A8 0 +OP4 E007A9 0 +OP4 E007AA 0 +OP4 E007AB 0 +OP4 E007AC 0 +OP4 E007AD 0 +OP4 E007AE 0 +OP4 E007AF 0 +OP4 E007B0 0 +OP4 E007B1 0 +OP4 E007B2 0 +OP4 E007B3 0 +OP4 E007B4 0 +OP4 E007B5 0 +OP4 E007B6 0 +OP4 E007B7 0 +OP4 E007B8 0 +OP4 E007B9 0 +OP4 E007BA 0 +OP4 E007BB 0 +OP4 E007BC 0 +OP4 E007BD 0 +OP4 E007BE 0 +OP4 E007BF 0 +OP4 E007C0 0 +OP4 E007C1 0 +OP4 E007C2 0 +OP4 E007C3 0 +OP4 E007C4 0 +OP4 E007C5 0 +OP4 E007C6 0 +OP4 E007C7 0 +OP4 E007C8 0 +OP4 E007C9 0 +OP4 E007CA 0 +OP4 E007CB 0 +OP4 E007CC 0 +OP4 E007CD 0 +OP4 E007CE 0 +OP4 E007CF 0 +OP4 E007D0 0 +OP4 E007D1 0 +OP4 E007D2 0 +OP4 E007D3 0 +OP4 E007D4 0 +OP4 E007D5 0 +OP4 E007D6 0 +OP4 E007D7 0 +OP4 E007D8 0 +OP4 E007D9 0 +OP4 E007DA 0 +OP4 E007DB 0 +OP4 E007DC 0 +OP4 E007DD 0 +OP4 E007DE 0 +OP4 E007DF 0 +OP4 E007E0 0 +OP4 E007E1 0 +OP4 E007E2 0 +OP4 E007E3 0 +OP4 E007E4 0 +OP4 E007E5 0 +OP4 E007E6 0 +OP4 E007E7 0 +OP4 E007E8 0 +OP4 E007E9 0 +OP4 E007EA 0 +OP4 E007EB 0 +OP4 E007EC 0 +OP4 E007ED 0 +OP4 E007EE 0 +OP4 E007EF 0 +OP4 E007F0 0 +OP4 E007F1 0 +OP4 E007F2 0 +OP4 E007F3 0 +OP4 E007F4 0 +OP4 E007F5 0 +OP4 E007F6 0 +OP4 E007F7 0 +OP4 E007F8 0 +OP4 E007F9 0 +OP4 E007FA 0 +OP4 E007FB 0 +OP4 E007FC 0 +OP4 E007FD 0 +OP4 E007FE 0 +OP4 E007FF 0 +OP4 E00800 0 +OP4 E00801 0 +OP4 E00802 0 +OP4 E00803 0 +OP4 E00804 0 +OP4 E00805 0 +OP4 E00806 0 +OP4 E00807 0 +OP4 E00808 0 +OP4 E00809 0 +OP4 E0080A 0 +OP4 E0080B 0 +OP4 E0080C 0 +OP4 E0080D 0 +OP4 E0080E 0 +OP4 E0080F 0 +OP4 E00810 0 +OP4 E00811 0 +OP4 E00812 0 +OP4 E00813 0 +OP4 E00814 0 +OP4 E00815 0 +OP4 E00816 0 +OP4 E00817 0 +OP4 E00818 0 +OP4 E00819 0 +OP4 E0081A 0 +OP4 E0081B 0 +OP4 E0081C 0 +OP4 E0081D 0 +OP4 E0081E 0 +OP4 E0081F 0 +OP4 E00820 0 +OP4 E00821 0 +OP4 E00822 0 +OP4 E00823 0 +OP4 E00824 0 +OP4 E00825 0 +OP4 E00826 0 +OP4 E00827 0 +OP4 E00828 0 +OP4 E00829 0 +OP4 E0082A 0 +OP4 E0082B 0 +OP4 E0082C 0 +OP4 E0082D 0 +OP4 E0082E 0 +OP4 E0082F 0 +OP4 E00830 0 +OP4 E00831 0 +OP4 E00832 0 +OP4 E00833 0 +OP4 E00834 0 +OP4 E00835 0 +OP4 E00836 0 +OP4 E00837 0 +OP4 E00838 0 +OP4 E00839 0 +OP4 E0083A 0 +OP4 E0083B 0 +OP4 E0083C 0 +OP4 E0083D 0 +OP4 E0083E 0 +OP4 E0083F 0 +OP4 E00840 0 +OP4 E00841 0 +OP4 E00842 0 +OP4 E00843 0 +OP4 E00844 0 +OP4 E00845 0 +OP4 E00846 0 +OP4 E00847 0 +OP4 E00848 0 +OP4 E00849 0 +OP4 E0084A 0 +OP4 E0084B 0 +OP4 E0084C 0 +OP4 E0084D 0 +OP4 E0084E 0 +OP4 E0084F 0 +OP4 E00850 0 +OP4 E00851 0 +OP4 E00852 0 +OP4 E00853 0 +OP4 E00854 0 +OP4 E00855 0 +OP4 E00856 0 +OP4 E00857 0 +OP4 E00858 0 +OP4 E00859 0 +OP4 E0085A 0 +OP4 E0085B 0 +OP4 E0085C 0 +OP4 E0085D 0 +OP4 E0085E 0 +OP4 E0085F 0 +OP4 E00860 0 +OP4 E00861 0 +OP4 E00862 0 +OP4 E00863 0 +OP4 E00864 0 +OP4 E00865 0 +OP4 E00866 0 +OP4 E00867 0 +OP4 E00868 0 +OP4 E00869 0 +OP4 E0086A 0 +OP4 E0086B 0 +OP4 E0086C 0 +OP4 E0086D 0 +OP4 E0086E 0 +OP4 E0086F 0 +OP4 E00870 0 +OP4 E00871 0 +OP4 E00872 0 +OP4 E00873 0 +OP4 E00874 0 +OP4 E00875 0 +OP4 E00876 0 +OP4 E00877 0 +OP4 E00878 0 +OP4 E00879 0 +OP4 E0087A 0 +OP4 E0087B 0 +OP4 E0087C 0 +OP4 E0087D 0 +OP4 E0087E 0 +OP4 E0087F 0 +OP4 E00880 0 +OP4 E00881 0 +OP4 E00882 0 +OP4 E00883 0 +OP4 E00884 0 +OP4 E00885 0 +OP4 E00886 0 +OP4 E00887 0 +OP4 E00888 0 +OP4 E00889 0 +OP4 E0088A 0 +OP4 E0088B 0 +OP4 E0088C 0 +OP4 E0088D 0 +OP4 E0088E 0 +OP4 E0088F 0 +OP4 E00890 0 +OP4 E00891 0 +OP4 E00892 0 +OP4 E00893 0 +OP4 E00894 0 +OP4 E00895 0 +OP4 E00896 0 +OP4 E00897 0 +OP4 E00898 0 +OP4 E00899 0 +OP4 E0089A 0 +OP4 E0089B 0 +OP4 E0089C 0 +OP4 E0089D 0 +OP4 E0089E 0 +OP4 E0089F 0 +OP4 E008A0 0 +OP4 E008A1 0 +OP4 E008A2 0 +OP4 E008A3 0 +OP4 E008A4 0 +OP4 E008A5 0 +OP4 E008A6 0 +OP4 E008A7 0 +OP4 E008A8 0 +OP4 E008A9 0 +OP4 E008AA 0 +OP4 E008AB 0 +OP4 E008AC 0 +OP4 E008AD 0 +OP4 E008AE 0 +OP4 E008AF 0 +OP4 E008B0 0 +OP4 E008B1 0 +OP4 E008B2 0 +OP4 E008B3 0 +OP4 E008B4 0 +OP4 E008B5 0 +OP4 E008B6 0 +OP4 E008B7 0 +OP4 E008B8 0 +OP4 E008B9 0 +OP4 E008BA 0 +OP4 E008BB 0 +OP4 E008BC 0 +OP4 E008BD 0 +OP4 E008BE 0 +OP4 E008BF 0 +OP4 E008C0 0 +OP4 E008C1 0 +OP4 E008C2 0 +OP4 E008C3 0 +OP4 E008C4 0 +OP4 E008C5 0 +OP4 E008C6 0 +OP4 E008C7 0 +OP4 E008C8 0 +OP4 E008C9 0 +OP4 E008CA 0 +OP4 E008CB 0 +OP4 E008CC 0 +OP4 E008CD 0 +OP4 E008CE 0 +OP4 E008CF 0 +OP4 E008D0 0 +OP4 E008D1 0 +OP4 E008D2 0 +OP4 E008D3 0 +OP4 E008D4 0 +OP4 E008D5 0 +OP4 E008D6 0 +OP4 E008D7 0 +OP4 E008D8 0 +OP4 E008D9 0 +OP4 E008DA 0 +OP4 E008DB 0 +OP4 E008DC 0 +OP4 E008DD 0 +OP4 E008DE 0 +OP4 E008DF 0 +OP4 E008E0 0 +OP4 E008E1 0 +OP4 E008E2 0 +OP4 E008E3 0 +OP4 E008E4 0 +OP4 E008E5 0 +OP4 E008E6 0 +OP4 E008E7 0 +OP4 E008E8 0 +OP4 E008E9 0 +OP4 E008EA 0 +OP4 E008EB 0 +OP4 E008EC 0 +OP4 E008ED 0 +OP4 E008EE 0 +OP4 E008EF 0 +OP4 E008F0 0 +OP4 E008F1 0 +OP4 E008F2 0 +OP4 E008F3 0 +OP4 E008F4 0 +OP4 E008F5 0 +OP4 E008F6 0 +OP4 E008F7 0 +OP4 E008F8 0 +OP4 E008F9 0 +OP4 E008FA 0 +OP4 E008FB 0 +OP4 E008FC 0 +OP4 E008FD 0 +OP4 E008FE 0 +OP4 E008FF 0 +OP4 E00900 0 +OP4 E00901 0 +OP4 E00902 0 +OP4 E00903 0 +OP4 E00904 0 +OP4 E00905 0 +OP4 E00906 0 +OP4 E00907 0 +OP4 E00908 0 +OP4 E00909 0 +OP4 E0090A 0 +OP4 E0090B 0 +OP4 E0090C 0 +OP4 E0090D 0 +OP4 E0090E 0 +OP4 E0090F 0 +OP4 E00910 0 +OP4 E00911 0 +OP4 E00912 0 +OP4 E00913 0 +OP4 E00914 0 +OP4 E00915 0 +OP4 E00916 0 +OP4 E00917 0 +OP4 E00918 0 +OP4 E00919 0 +OP4 E0091A 0 +OP4 E0091B 0 +OP4 E0091C 0 +OP4 E0091D 0 +OP4 E0091E 0 +OP4 E0091F 0 +OP4 E00920 0 +OP4 E00921 0 +OP4 E00922 0 +OP4 E00923 0 +OP4 E00924 0 +OP4 E00925 0 +OP4 E00926 0 +OP4 E00927 0 +OP4 E00928 0 +OP4 E00929 0 +OP4 E0092A 0 +OP4 E0092B 0 +OP4 E0092C 0 +OP4 E0092D 0 +OP4 E0092E 0 +OP4 E0092F 0 +OP4 E00930 0 +OP4 E00931 0 +OP4 E00932 0 +OP4 E00933 0 +OP4 E00934 0 +OP4 E00935 0 +OP4 E00936 0 +OP4 E00937 0 +OP4 E00938 0 +OP4 E00939 0 +OP4 E0093A 0 +OP4 E0093B 0 +OP4 E0093C 0 +OP4 E0093D 0 +OP4 E0093E 0 +OP4 E0093F 0 +OP4 E00940 0 +OP4 E00941 0 +OP4 E00942 0 +OP4 E00943 0 +OP4 E00944 0 +OP4 E00945 0 +OP4 E00946 0 +OP4 E00947 0 +OP4 E00948 0 +OP4 E00949 0 +OP4 E0094A 0 +OP4 E0094B 0 +OP4 E0094C 0 +OP4 E0094D 0 +OP4 E0094E 0 +OP4 E0094F 0 +OP4 E00950 0 +OP4 E00951 0 +OP4 E00952 0 +OP4 E00953 0 +OP4 E00954 0 +OP4 E00955 0 +OP4 E00956 0 +OP4 E00957 0 +OP4 E00958 0 +OP4 E00959 0 +OP4 E0095A 0 +OP4 E0095B 0 +OP4 E0095C 0 +OP4 E0095D 0 +OP4 E0095E 0 +OP4 E0095F 0 +OP4 E00960 0 +OP4 E00961 0 +OP4 E00962 0 +OP4 E00963 0 +OP4 E00964 0 +OP4 E00965 0 +OP4 E00966 0 +OP4 E00967 0 +OP4 E00968 0 +OP4 E00969 0 +OP4 E0096A 0 +OP4 E0096B 0 +OP4 E0096C 0 +OP4 E0096D 0 +OP4 E0096E 0 +OP4 E0096F 0 +OP4 E00970 0 +OP4 E00971 0 +OP4 E00972 0 +OP4 E00973 0 +OP4 E00974 0 +OP4 E00975 0 +OP4 E00976 0 +OP4 E00977 0 +OP4 E00978 0 +OP4 E00979 0 +OP4 E0097A 0 +OP4 E0097B 0 +OP4 E0097C 0 +OP4 E0097D 0 +OP4 E0097E 0 +OP4 E0097F 0 +OP4 E00980 0 +OP4 E00981 0 +OP4 E00982 0 +OP4 E00983 0 +OP4 E00984 0 +OP4 E00985 0 +OP4 E00986 0 +OP4 E00987 0 +OP4 E00988 0 +OP4 E00989 0 +OP4 E0098A 0 +OP4 E0098B 0 +OP4 E0098C 0 +OP4 E0098D 0 +OP4 E0098E 0 +OP4 E0098F 0 +OP4 E00990 0 +OP4 E00991 0 +OP4 E00992 0 +OP4 E00993 0 +OP4 E00994 0 +OP4 E00995 0 +OP4 E00996 0 +OP4 E00997 0 +OP4 E00998 0 +OP4 E00999 0 +OP4 E0099A 0 +OP4 E0099B 0 +OP4 E0099C 0 +OP4 E0099D 0 +OP4 E0099E 0 +OP4 E0099F 0 +OP4 E009A0 0 +OP4 E009A1 0 +OP4 E009A2 0 +OP4 E009A3 0 +OP4 E009A4 0 +OP4 E009A5 0 +OP4 E009A6 0 +OP4 E009A7 0 +OP4 E009A8 0 +OP4 E009A9 0 +OP4 E009AA 0 +OP4 E009AB 0 +OP4 E009AC 0 +OP4 E009AD 0 +OP4 E009AE 0 +OP4 E009AF 0 +OP4 E009B0 0 +OP4 E009B1 0 +OP4 E009B2 0 +OP4 E009B3 0 +OP4 E009B4 0 +OP4 E009B5 0 +OP4 E009B6 0 +OP4 E009B7 0 +OP4 E009B8 0 +OP4 E009B9 0 +OP4 E009BA 0 +OP4 E009BB 0 +OP4 E009BC 0 +OP4 E009BD 0 +OP4 E009BE 0 +OP4 E009BF 0 +OP4 E009C0 0 +OP4 E009C1 0 +OP4 E009C2 0 +OP4 E009C3 0 +OP4 E009C4 0 +OP4 E009C5 0 +OP4 E009C6 0 +OP4 E009C7 0 +OP4 E009C8 0 +OP4 E009C9 0 +OP4 E009CA 0 +OP4 E009CB 0 +OP4 E009CC 0 +OP4 E009CD 0 +OP4 E009CE 0 +OP4 E009CF 0 +OP4 E009D0 0 +OP4 E009D1 0 +OP4 E009D2 0 +OP4 E009D3 0 +OP4 E009D4 0 +OP4 E009D5 0 +OP4 E009D6 0 +OP4 E009D7 0 +OP4 E009D8 0 +OP4 E009D9 0 +OP4 E009DA 0 +OP4 E009DB 0 +OP4 E009DC 0 +OP4 E009DD 0 +OP4 E009DE 0 +OP4 E009DF 0 +OP4 E009E0 0 +OP4 E009E1 0 +OP4 E009E2 0 +OP4 E009E3 0 +OP4 E009E4 0 +OP4 E009E5 0 +OP4 E009E6 0 +OP4 E009E7 0 +OP4 E009E8 0 +OP4 E009E9 0 +OP4 E009EA 0 +OP4 E009EB 0 +OP4 E009EC 0 +OP4 E009ED 0 +OP4 E009EE 0 +OP4 E009EF 0 +OP4 E009F0 0 +OP4 E009F1 0 +OP4 E009F2 0 +OP4 E009F3 0 +OP4 E009F4 0 +OP4 E009F5 0 +OP4 E009F6 0 +OP4 E009F7 0 +OP4 E009F8 0 +OP4 E009F9 0 +OP4 E009FA 0 +OP4 E009FB 0 +OP4 E009FC 0 +OP4 E009FD 0 +OP4 E009FE 0 +OP4 E009FF 0 +OP4 E00A00 0 +OP4 E00A01 0 +OP4 E00A02 0 +OP4 E00A03 0 +OP4 E00A04 0 +OP4 E00A05 0 +OP4 E00A06 0 +OP4 E00A07 0 +OP4 E00A08 0 +OP4 E00A09 0 +OP4 E00A0A 0 +OP4 E00A0B 0 +OP4 E00A0C 0 +OP4 E00A0D 0 +OP4 E00A0E 0 +OP4 E00A0F 0 +OP4 E00A10 0 +OP4 E00A11 0 +OP4 E00A12 0 +OP4 E00A13 0 +OP4 E00A14 0 +OP4 E00A15 0 +OP4 E00A16 0 +OP4 E00A17 0 +OP4 E00A18 0 +OP4 E00A19 0 +OP4 E00A1A 0 +OP4 E00A1B 0 +OP4 E00A1C 0 +OP4 E00A1D 0 +OP4 E00A1E 0 +OP4 E00A1F 0 +OP4 E00A20 0 +OP4 E00A21 0 +OP4 E00A22 0 +OP4 E00A23 0 +OP4 E00A24 0 +OP4 E00A25 0 +OP4 E00A26 0 +OP4 E00A27 0 +OP4 E00A28 0 +OP4 E00A29 0 +OP4 E00A2A 0 +OP4 E00A2B 0 +OP4 E00A2C 0 +OP4 E00A2D 0 +OP4 E00A2E 0 +OP4 E00A2F 0 +OP4 E00A30 0 +OP4 E00A31 0 +OP4 E00A32 0 +OP4 E00A33 0 +OP4 E00A34 0 +OP4 E00A35 0 +OP4 E00A36 0 +OP4 E00A37 0 +OP4 E00A38 0 +OP4 E00A39 0 +OP4 E00A3A 0 +OP4 E00A3B 0 +OP4 E00A3C 0 +OP4 E00A3D 0 +OP4 E00A3E 0 +OP4 E00A3F 0 +OP4 E00A40 0 +OP4 E00A41 0 +OP4 E00A42 0 +OP4 E00A43 0 +OP4 E00A44 0 +OP4 E00A45 0 +OP4 E00A46 0 +OP4 E00A47 0 +OP4 E00A48 0 +OP4 E00A49 0 +OP4 E00A4A 0 +OP4 E00A4B 0 +OP4 E00A4C 0 +OP4 E00A4D 0 +OP4 E00A4E 0 +OP4 E00A4F 0 +OP4 E00A50 0 +OP4 E00A51 0 +OP4 E00A52 0 +OP4 E00A53 0 +OP4 E00A54 0 +OP4 E00A55 0 +OP4 E00A56 0 +OP4 E00A57 0 +OP4 E00A58 0 +OP4 E00A59 0 +OP4 E00A5A 0 +OP4 E00A5B 0 +OP4 E00A5C 0 +OP4 E00A5D 0 +OP4 E00A5E 0 +OP4 E00A5F 0 +OP4 E00A60 0 +OP4 E00A61 0 +OP4 E00A62 0 +OP4 E00A63 0 +OP4 E00A64 0 +OP4 E00A65 0 +OP4 E00A66 0 +OP4 E00A67 0 +OP4 E00A68 0 +OP4 E00A69 0 +OP4 E00A6A 0 +OP4 E00A6B 0 +OP4 E00A6C 0 +OP4 E00A6D 0 +OP4 E00A6E 0 +OP4 E00A6F 0 +OP4 E00A70 0 +OP4 E00A71 0 +OP4 E00A72 0 +OP4 E00A73 0 +OP4 E00A74 0 +OP4 E00A75 0 +OP4 E00A76 0 +OP4 E00A77 0 +OP4 E00A78 0 +OP4 E00A79 0 +OP4 E00A7A 0 +OP4 E00A7B 0 +OP4 E00A7C 0 +OP4 E00A7D 0 +OP4 E00A7E 0 +OP4 E00A7F 0 +OP4 E00A80 0 +OP4 E00A81 0 +OP4 E00A82 0 +OP4 E00A83 0 +OP4 E00A84 0 +OP4 E00A85 0 +OP4 E00A86 0 +OP4 E00A87 0 +OP4 E00A88 0 +OP4 E00A89 0 +OP4 E00A8A 0 +OP4 E00A8B 0 +OP4 E00A8C 0 +OP4 E00A8D 0 +OP4 E00A8E 0 +OP4 E00A8F 0 +OP4 E00A90 0 +OP4 E00A91 0 +OP4 E00A92 0 +OP4 E00A93 0 +OP4 E00A94 0 +OP4 E00A95 0 +OP4 E00A96 0 +OP4 E00A97 0 +OP4 E00A98 0 +OP4 E00A99 0 +OP4 E00A9A 0 +OP4 E00A9B 0 +OP4 E00A9C 0 +OP4 E00A9D 0 +OP4 E00A9E 0 +OP4 E00A9F 0 +OP4 E00AA0 0 +OP4 E00AA1 0 +OP4 E00AA2 0 +OP4 E00AA3 0 +OP4 E00AA4 0 +OP4 E00AA5 0 +OP4 E00AA6 0 +OP4 E00AA7 0 +OP4 E00AA8 0 +OP4 E00AA9 0 +OP4 E00AAA 0 +OP4 E00AAB 0 +OP4 E00AAC 0 +OP4 E00AAD 0 +OP4 E00AAE 0 +OP4 E00AAF 0 +OP4 E00AB0 0 +OP4 E00AB1 0 +OP4 E00AB2 0 +OP4 E00AB3 0 +OP4 E00AB4 0 +OP4 E00AB5 0 +OP4 E00AB6 0 +OP4 E00AB7 0 +OP4 E00AB8 0 +OP4 E00AB9 0 +OP4 E00ABA 0 +OP4 E00ABB 0 +OP4 E00ABC 0 +OP4 E00ABD 0 +OP4 E00ABE 0 +OP4 E00ABF 0 +OP4 E00AC0 0 +OP4 E00AC1 0 +OP4 E00AC2 0 +OP4 E00AC3 0 +OP4 E00AC4 0 +OP4 E00AC5 0 +OP4 E00AC6 0 +OP4 E00AC7 0 +OP4 E00AC8 0 +OP4 E00AC9 0 +OP4 E00ACA 0 +OP4 E00ACB 0 +OP4 E00ACC 0 +OP4 E00ACD 0 +OP4 E00ACE 0 +OP4 E00ACF 0 +OP4 E00AD0 0 +OP4 E00AD1 0 +OP4 E00AD2 0 +OP4 E00AD3 0 +OP4 E00AD4 0 +OP4 E00AD5 0 +OP4 E00AD6 0 +OP4 E00AD7 0 +OP4 E00AD8 0 +OP4 E00AD9 0 +OP4 E00ADA 0 +OP4 E00ADB 0 +OP4 E00ADC 0 +OP4 E00ADD 0 +OP4 E00ADE 0 +OP4 E00ADF 0 +OP4 E00AE0 0 +OP4 E00AE1 0 +OP4 E00AE2 0 +OP4 E00AE3 0 +OP4 E00AE4 0 +OP4 E00AE5 0 +OP4 E00AE6 0 +OP4 E00AE7 0 +OP4 E00AE8 0 +OP4 E00AE9 0 +OP4 E00AEA 0 +OP4 E00AEB 0 +OP4 E00AEC 0 +OP4 E00AED 0 +OP4 E00AEE 0 +OP4 E00AEF 0 +OP4 E00AF0 0 +OP4 E00AF1 0 +OP4 E00AF2 0 +OP4 E00AF3 0 +OP4 E00AF4 0 +OP4 E00AF5 0 +OP4 E00AF6 0 +OP4 E00AF7 0 +OP4 E00AF8 0 +OP4 E00AF9 0 +OP4 E00AFA 0 +OP4 E00AFB 0 +OP4 E00AFC 0 +OP4 E00AFD 0 +OP4 E00AFE 0 +OP4 E00AFF 0 +OP4 E00B00 0 +OP4 E00B01 0 +OP4 E00B02 0 +OP4 E00B03 0 +OP4 E00B04 0 +OP4 E00B05 0 +OP4 E00B06 0 +OP4 E00B07 0 +OP4 E00B08 0 +OP4 E00B09 0 +OP4 E00B0A 0 +OP4 E00B0B 0 +OP4 E00B0C 0 +OP4 E00B0D 0 +OP4 E00B0E 0 +OP4 E00B0F 0 +OP4 E00B10 0 +OP4 E00B11 0 +OP4 E00B12 0 +OP4 E00B13 0 +OP4 E00B14 0 +OP4 E00B15 0 +OP4 E00B16 0 +OP4 E00B17 0 +OP4 E00B18 0 +OP4 E00B19 0 +OP4 E00B1A 0 +OP4 E00B1B 0 +OP4 E00B1C 0 +OP4 E00B1D 0 +OP4 E00B1E 0 +OP4 E00B1F 0 +OP4 E00B20 0 +OP4 E00B21 0 +OP4 E00B22 0 +OP4 E00B23 0 +OP4 E00B24 0 +OP4 E00B25 0 +OP4 E00B26 0 +OP4 E00B27 0 +OP4 E00B28 0 +OP4 E00B29 0 +OP4 E00B2A 0 +OP4 E00B2B 0 +OP4 E00B2C 0 +OP4 E00B2D 0 +OP4 E00B2E 0 +OP4 E00B2F 0 +OP4 E00B30 0 +OP4 E00B31 0 +OP4 E00B32 0 +OP4 E00B33 0 +OP4 E00B34 0 +OP4 E00B35 0 +OP4 E00B36 0 +OP4 E00B37 0 +OP4 E00B38 0 +OP4 E00B39 0 +OP4 E00B3A 0 +OP4 E00B3B 0 +OP4 E00B3C 0 +OP4 E00B3D 0 +OP4 E00B3E 0 +OP4 E00B3F 0 +OP4 E00B40 0 +OP4 E00B41 0 +OP4 E00B42 0 +OP4 E00B43 0 +OP4 E00B44 0 +OP4 E00B45 0 +OP4 E00B46 0 +OP4 E00B47 0 +OP4 E00B48 0 +OP4 E00B49 0 +OP4 E00B4A 0 +OP4 E00B4B 0 +OP4 E00B4C 0 +OP4 E00B4D 0 +OP4 E00B4E 0 +OP4 E00B4F 0 +OP4 E00B50 0 +OP4 E00B51 0 +OP4 E00B52 0 +OP4 E00B53 0 +OP4 E00B54 0 +OP4 E00B55 0 +OP4 E00B56 0 +OP4 E00B57 0 +OP4 E00B58 0 +OP4 E00B59 0 +OP4 E00B5A 0 +OP4 E00B5B 0 +OP4 E00B5C 0 +OP4 E00B5D 0 +OP4 E00B5E 0 +OP4 E00B5F 0 +OP4 E00B60 0 +OP4 E00B61 0 +OP4 E00B62 0 +OP4 E00B63 0 +OP4 E00B64 0 +OP4 E00B65 0 +OP4 E00B66 0 +OP4 E00B67 0 +OP4 E00B68 0 +OP4 E00B69 0 +OP4 E00B6A 0 +OP4 E00B6B 0 +OP4 E00B6C 0 +OP4 E00B6D 0 +OP4 E00B6E 0 +OP4 E00B6F 0 +OP4 E00B70 0 +OP4 E00B71 0 +OP4 E00B72 0 +OP4 E00B73 0 +OP4 E00B74 0 +OP4 E00B75 0 +OP4 E00B76 0 +OP4 E00B77 0 +OP4 E00B78 0 +OP4 E00B79 0 +OP4 E00B7A 0 +OP4 E00B7B 0 +OP4 E00B7C 0 +OP4 E00B7D 0 +OP4 E00B7E 0 +OP4 E00B7F 0 +OP4 E00B80 0 +OP4 E00B81 0 +OP4 E00B82 0 +OP4 E00B83 0 +OP4 E00B84 0 +OP4 E00B85 0 +OP4 E00B86 0 +OP4 E00B87 0 +OP4 E00B88 0 +OP4 E00B89 0 +OP4 E00B8A 0 +OP4 E00B8B 0 +OP4 E00B8C 0 +OP4 E00B8D 0 +OP4 E00B8E 0 +OP4 E00B8F 0 +OP4 E00B90 0 +OP4 E00B91 0 +OP4 E00B92 0 +OP4 E00B93 0 +OP4 E00B94 0 +OP4 E00B95 0 +OP4 E00B96 0 +OP4 E00B97 0 +OP4 E00B98 0 +OP4 E00B99 0 +OP4 E00B9A 0 +OP4 E00B9B 0 +OP4 E00B9C 0 +OP4 E00B9D 0 +OP4 E00B9E 0 +OP4 E00B9F 0 +OP4 E00BA0 0 +OP4 E00BA1 0 +OP4 E00BA2 0 +OP4 E00BA3 0 +OP4 E00BA4 0 +OP4 E00BA5 0 +OP4 E00BA6 0 +OP4 E00BA7 0 +OP4 E00BA8 0 +OP4 E00BA9 0 +OP4 E00BAA 0 +OP4 E00BAB 0 +OP4 E00BAC 0 +OP4 E00BAD 0 +OP4 E00BAE 0 +OP4 E00BAF 0 +OP4 E00BB0 0 +OP4 E00BB1 0 +OP4 E00BB2 0 +OP4 E00BB3 0 +OP4 E00BB4 0 +OP4 E00BB5 0 +OP4 E00BB6 0 +OP4 E00BB7 0 +OP4 E00BB8 0 +OP4 E00BB9 0 +OP4 E00BBA 0 +OP4 E00BBB 0 +OP4 E00BBC 0 +OP4 E00BBD 0 +OP4 E00BBE 0 +OP4 E00BBF 0 +OP4 E00BC0 0 +OP4 E00BC1 0 +OP4 E00BC2 0 +OP4 E00BC3 0 +OP4 E00BC4 0 +OP4 E00BC5 0 +OP4 E00BC6 0 +OP4 E00BC7 0 +OP4 E00BC8 0 +OP4 E00BC9 0 +OP4 E00BCA 0 +OP4 E00BCB 0 +OP4 E00BCC 0 +OP4 E00BCD 0 +OP4 E00BCE 0 +OP4 E00BCF 0 +OP4 E00BD0 0 +OP4 E00BD1 0 +OP4 E00BD2 0 +OP4 E00BD3 0 +OP4 E00BD4 0 +OP4 E00BD5 0 +OP4 E00BD6 0 +OP4 E00BD7 0 +OP4 E00BD8 0 +OP4 E00BD9 0 +OP4 E00BDA 0 +OP4 E00BDB 0 +OP4 E00BDC 0 +OP4 E00BDD 0 +OP4 E00BDE 0 +OP4 E00BDF 0 +OP4 E00BE0 0 +OP4 E00BE1 0 +OP4 E00BE2 0 +OP4 E00BE3 0 +OP4 E00BE4 0 +OP4 E00BE5 0 +OP4 E00BE6 0 +OP4 E00BE7 0 +OP4 E00BE8 0 +OP4 E00BE9 0 +OP4 E00BEA 0 +OP4 E00BEB 0 +OP4 E00BEC 0 +OP4 E00BED 0 +OP4 E00BEE 0 +OP4 E00BEF 0 +OP4 E00BF0 0 +OP4 E00BF1 0 +OP4 E00BF2 0 +OP4 E00BF3 0 +OP4 E00BF4 0 +OP4 E00BF5 0 +OP4 E00BF6 0 +OP4 E00BF7 0 +OP4 E00BF8 0 +OP4 E00BF9 0 +OP4 E00BFA 0 +OP4 E00BFB 0 +OP4 E00BFC 0 +OP4 E00BFD 0 +OP4 E00BFE 0 +OP4 E00BFF 0 +OP4 E00C00 0 +OP4 E00C01 0 +OP4 E00C02 0 +OP4 E00C03 0 +OP4 E00C04 0 +OP4 E00C05 0 +OP4 E00C06 0 +OP4 E00C07 0 +OP4 E00C08 0 +OP4 E00C09 0 +OP4 E00C0A 0 +OP4 E00C0B 0 +OP4 E00C0C 0 +OP4 E00C0D 0 +OP4 E00C0E 0 +OP4 E00C0F 0 +OP4 E00C10 0 +OP4 E00C11 0 +OP4 E00C12 0 +OP4 E00C13 0 +OP4 E00C14 0 +OP4 E00C15 0 +OP4 E00C16 0 +OP4 E00C17 0 +OP4 E00C18 0 +OP4 E00C19 0 +OP4 E00C1A 0 +OP4 E00C1B 0 +OP4 E00C1C 0 +OP4 E00C1D 0 +OP4 E00C1E 0 +OP4 E00C1F 0 +OP4 E00C20 0 +OP4 E00C21 0 +OP4 E00C22 0 +OP4 E00C23 0 +OP4 E00C24 0 +OP4 E00C25 0 +OP4 E00C26 0 +OP4 E00C27 0 +OP4 E00C28 0 +OP4 E00C29 0 +OP4 E00C2A 0 +OP4 E00C2B 0 +OP4 E00C2C 0 +OP4 E00C2D 0 +OP4 E00C2E 0 +OP4 E00C2F 0 +OP4 E00C30 0 +OP4 E00C31 0 +OP4 E00C32 0 +OP4 E00C33 0 +OP4 E00C34 0 +OP4 E00C35 0 +OP4 E00C36 0 +OP4 E00C37 0 +OP4 E00C38 0 +OP4 E00C39 0 +OP4 E00C3A 0 +OP4 E00C3B 0 +OP4 E00C3C 0 +OP4 E00C3D 0 +OP4 E00C3E 0 +OP4 E00C3F 0 +OP4 E00C40 0 +OP4 E00C41 0 +OP4 E00C42 0 +OP4 E00C43 0 +OP4 E00C44 0 +OP4 E00C45 0 +OP4 E00C46 0 +OP4 E00C47 0 +OP4 E00C48 0 +OP4 E00C49 0 +OP4 E00C4A 0 +OP4 E00C4B 0 +OP4 E00C4C 0 +OP4 E00C4D 0 +OP4 E00C4E 0 +OP4 E00C4F 0 +OP4 E00C50 0 +OP4 E00C51 0 +OP4 E00C52 0 +OP4 E00C53 0 +OP4 E00C54 0 +OP4 E00C55 0 +OP4 E00C56 0 +OP4 E00C57 0 +OP4 E00C58 0 +OP4 E00C59 0 +OP4 E00C5A 0 +OP4 E00C5B 0 +OP4 E00C5C 0 +OP4 E00C5D 0 +OP4 E00C5E 0 +OP4 E00C5F 0 +OP4 E00C60 0 +OP4 E00C61 0 +OP4 E00C62 0 +OP4 E00C63 0 +OP4 E00C64 0 +OP4 E00C65 0 +OP4 E00C66 0 +OP4 E00C67 0 +OP4 E00C68 0 +OP4 E00C69 0 +OP4 E00C6A 0 +OP4 E00C6B 0 +OP4 E00C6C 0 +OP4 E00C6D 0 +OP4 E00C6E 0 +OP4 E00C6F 0 +OP4 E00C70 0 +OP4 E00C71 0 +OP4 E00C72 0 +OP4 E00C73 0 +OP4 E00C74 0 +OP4 E00C75 0 +OP4 E00C76 0 +OP4 E00C77 0 +OP4 E00C78 0 +OP4 E00C79 0 +OP4 E00C7A 0 +OP4 E00C7B 0 +OP4 E00C7C 0 +OP4 E00C7D 0 +OP4 E00C7E 0 +OP4 E00C7F 0 +OP4 E00C80 0 +OP4 E00C81 0 +OP4 E00C82 0 +OP4 E00C83 0 +OP4 E00C84 0 +OP4 E00C85 0 +OP4 E00C86 0 +OP4 E00C87 0 +OP4 E00C88 0 +OP4 E00C89 0 +OP4 E00C8A 0 +OP4 E00C8B 0 +OP4 E00C8C 0 +OP4 E00C8D 0 +OP4 E00C8E 0 +OP4 E00C8F 0 +OP4 E00C90 0 +OP4 E00C91 0 +OP4 E00C92 0 +OP4 E00C93 0 +OP4 E00C94 0 +OP4 E00C95 0 +OP4 E00C96 0 +OP4 E00C97 0 +OP4 E00C98 0 +OP4 E00C99 0 +OP4 E00C9A 0 +OP4 E00C9B 0 +OP4 E00C9C 0 +OP4 E00C9D 0 +OP4 E00C9E 0 +OP4 E00C9F 0 +OP4 E00CA0 0 +OP4 E00CA1 0 +OP4 E00CA2 0 +OP4 E00CA3 0 +OP4 E00CA4 0 +OP4 E00CA5 0 +OP4 E00CA6 0 +OP4 E00CA7 0 +OP4 E00CA8 0 +OP4 E00CA9 0 +OP4 E00CAA 0 +OP4 E00CAB 0 +OP4 E00CAC 0 +OP4 E00CAD 0 +OP4 E00CAE 0 +OP4 E00CAF 0 +OP4 E00CB0 0 +OP4 E00CB1 0 +OP4 E00CB2 0 +OP4 E00CB3 0 +OP4 E00CB4 0 +OP4 E00CB5 0 +OP4 E00CB6 0 +OP4 E00CB7 0 +OP4 E00CB8 0 +OP4 E00CB9 0 +OP4 E00CBA 0 +OP4 E00CBB 0 +OP4 E00CBC 0 +OP4 E00CBD 0 +OP4 E00CBE 0 +OP4 E00CBF 0 +OP4 E00CC0 0 +OP4 E00CC1 0 +OP4 E00CC2 0 +OP4 E00CC3 0 +OP4 E00CC4 0 +OP4 E00CC5 0 +OP4 E00CC6 0 +OP4 E00CC7 0 +OP4 E00CC8 0 +OP4 E00CC9 0 +OP4 E00CCA 0 +OP4 E00CCB 0 +OP4 E00CCC 0 +OP4 E00CCD 0 +OP4 E00CCE 0 +OP4 E00CCF 0 +OP4 E00CD0 0 +OP4 E00CD1 0 +OP4 E00CD2 0 +OP4 E00CD3 0 +OP4 E00CD4 0 +OP4 E00CD5 0 +OP4 E00CD6 0 +OP4 E00CD7 0 +OP4 E00CD8 0 +OP4 E00CD9 0 +OP4 E00CDA 0 +OP4 E00CDB 0 +OP4 E00CDC 0 +OP4 E00CDD 0 +OP4 E00CDE 0 +OP4 E00CDF 0 +OP4 E00CE0 0 +OP4 E00CE1 0 +OP4 E00CE2 0 +OP4 E00CE3 0 +OP4 E00CE4 0 +OP4 E00CE5 0 +OP4 E00CE6 0 +OP4 E00CE7 0 +OP4 E00CE8 0 +OP4 E00CE9 0 +OP4 E00CEA 0 +OP4 E00CEB 0 +OP4 E00CEC 0 +OP4 E00CED 0 +OP4 E00CEE 0 +OP4 E00CEF 0 +OP4 E00CF0 0 +OP4 E00CF1 0 +OP4 E00CF2 0 +OP4 E00CF3 0 +OP4 E00CF4 0 +OP4 E00CF5 0 +OP4 E00CF6 0 +OP4 E00CF7 0 +OP4 E00CF8 0 +OP4 E00CF9 0 +OP4 E00CFA 0 +OP4 E00CFB 0 +OP4 E00CFC 0 +OP4 E00CFD 0 +OP4 E00CFE 0 +OP4 E00CFF 0 +OP4 E00D00 0 +OP4 E00D01 0 +OP4 E00D02 0 +OP4 E00D03 0 +OP4 E00D04 0 +OP4 E00D05 0 +OP4 E00D06 0 +OP4 E00D07 0 +OP4 E00D08 0 +OP4 E00D09 0 +OP4 E00D0A 0 +OP4 E00D0B 0 +OP4 E00D0C 0 +OP4 E00D0D 0 +OP4 E00D0E 0 +OP4 E00D0F 0 +OP4 E00D10 0 +OP4 E00D11 0 +OP4 E00D12 0 +OP4 E00D13 0 +OP4 E00D14 0 +OP4 E00D15 0 +OP4 E00D16 0 +OP4 E00D17 0 +OP4 E00D18 0 +OP4 E00D19 0 +OP4 E00D1A 0 +OP4 E00D1B 0 +OP4 E00D1C 0 +OP4 E00D1D 0 +OP4 E00D1E 0 +OP4 E00D1F 0 +OP4 E00D20 0 +OP4 E00D21 0 +OP4 E00D22 0 +OP4 E00D23 0 +OP4 E00D24 0 +OP4 E00D25 0 +OP4 E00D26 0 +OP4 E00D27 0 +OP4 E00D28 0 +OP4 E00D29 0 +OP4 E00D2A 0 +OP4 E00D2B 0 +OP4 E00D2C 0 +OP4 E00D2D 0 +OP4 E00D2E 0 +OP4 E00D2F 0 +OP4 E00D30 0 +OP4 E00D31 0 +OP4 E00D32 0 +OP4 E00D33 0 +OP4 E00D34 0 +OP4 E00D35 0 +OP4 E00D36 0 +OP4 E00D37 0 +OP4 E00D38 0 +OP4 E00D39 0 +OP4 E00D3A 0 +OP4 E00D3B 0 +OP4 E00D3C 0 +OP4 E00D3D 0 +OP4 E00D3E 0 +OP4 E00D3F 0 +OP4 E00D40 0 +OP4 E00D41 0 +OP4 E00D42 0 +OP4 E00D43 0 +OP4 E00D44 0 +OP4 E00D45 0 +OP4 E00D46 0 +OP4 E00D47 0 +OP4 E00D48 0 +OP4 E00D49 0 +OP4 E00D4A 0 +OP4 E00D4B 0 +OP4 E00D4C 0 +OP4 E00D4D 0 +OP4 E00D4E 0 +OP4 E00D4F 0 +OP4 E00D50 0 +OP4 E00D51 0 +OP4 E00D52 0 +OP4 E00D53 0 +OP4 E00D54 0 +OP4 E00D55 0 +OP4 E00D56 0 +OP4 E00D57 0 +OP4 E00D58 0 +OP4 E00D59 0 +OP4 E00D5A 0 +OP4 E00D5B 0 +OP4 E00D5C 0 +OP4 E00D5D 0 +OP4 E00D5E 0 +OP4 E00D5F 0 +OP4 E00D60 0 +OP4 E00D61 0 +OP4 E00D62 0 +OP4 E00D63 0 +OP4 E00D64 0 +OP4 E00D65 0 +OP4 E00D66 0 +OP4 E00D67 0 +OP4 E00D68 0 +OP4 E00D69 0 +OP4 E00D6A 0 +OP4 E00D6B 0 +OP4 E00D6C 0 +OP4 E00D6D 0 +OP4 E00D6E 0 +OP4 E00D6F 0 +OP4 E00D70 0 +OP4 E00D71 0 +OP4 E00D72 0 +OP4 E00D73 0 +OP4 E00D74 0 +OP4 E00D75 0 +OP4 E00D76 0 +OP4 E00D77 0 +OP4 E00D78 0 +OP4 E00D79 0 +OP4 E00D7A 0 +OP4 E00D7B 0 +OP4 E00D7C 0 +OP4 E00D7D 0 +OP4 E00D7E 0 +OP4 E00D7F 0 +OP4 E00D80 0 +OP4 E00D81 0 +OP4 E00D82 0 +OP4 E00D83 0 +OP4 E00D84 0 +OP4 E00D85 0 +OP4 E00D86 0 +OP4 E00D87 0 +OP4 E00D88 0 +OP4 E00D89 0 +OP4 E00D8A 0 +OP4 E00D8B 0 +OP4 E00D8C 0 +OP4 E00D8D 0 +OP4 E00D8E 0 +OP4 E00D8F 0 +OP4 E00D90 0 +OP4 E00D91 0 +OP4 E00D92 0 +OP4 E00D93 0 +OP4 E00D94 0 +OP4 E00D95 0 +OP4 E00D96 0 +OP4 E00D97 0 +OP4 E00D98 0 +OP4 E00D99 0 +OP4 E00D9A 0 +OP4 E00D9B 0 +OP4 E00D9C 0 +OP4 E00D9D 0 +OP4 E00D9E 0 +OP4 E00D9F 0 +OP4 E00DA0 0 +OP4 E00DA1 0 +OP4 E00DA2 0 +OP4 E00DA3 0 +OP4 E00DA4 0 +OP4 E00DA5 0 +OP4 E00DA6 0 +OP4 E00DA7 0 +OP4 E00DA8 0 +OP4 E00DA9 0 +OP4 E00DAA 0 +OP4 E00DAB 0 +OP4 E00DAC 0 +OP4 E00DAD 0 +OP4 E00DAE 0 +OP4 E00DAF 0 +OP4 E00DB0 0 +OP4 E00DB1 0 +OP4 E00DB2 0 +OP4 E00DB3 0 +OP4 E00DB4 0 +OP4 E00DB5 0 +OP4 E00DB6 0 +OP4 E00DB7 0 +OP4 E00DB8 0 +OP4 E00DB9 0 +OP4 E00DBA 0 +OP4 E00DBB 0 +OP4 E00DBC 0 +OP4 E00DBD 0 +OP4 E00DBE 0 +OP4 E00DBF 0 +OP4 E00DC0 0 +OP4 E00DC1 0 +OP4 E00DC2 0 +OP4 E00DC3 0 +OP4 E00DC4 0 +OP4 E00DC5 0 +OP4 E00DC6 0 +OP4 E00DC7 0 +OP4 E00DC8 0 +OP4 E00DC9 0 +OP4 E00DCA 0 +OP4 E00DCB 0 +OP4 E00DCC 0 +OP4 E00DCD 0 +OP4 E00DCE 0 +OP4 E00DCF 0 +OP4 E00DD0 0 +OP4 E00DD1 0 +OP4 E00DD2 0 +OP4 E00DD3 0 +OP4 E00DD4 0 +OP4 E00DD5 0 +OP4 E00DD6 0 +OP4 E00DD7 0 +OP4 E00DD8 0 +OP4 E00DD9 0 +OP4 E00DDA 0 +OP4 E00DDB 0 +OP4 E00DDC 0 +OP4 E00DDD 0 +OP4 E00DDE 0 +OP4 E00DDF 0 +OP4 E00DE0 0 +OP4 E00DE1 0 +OP4 E00DE2 0 +OP4 E00DE3 0 +OP4 E00DE4 0 +OP4 E00DE5 0 +OP4 E00DE6 0 +OP4 E00DE7 0 +OP4 E00DE8 0 +OP4 E00DE9 0 +OP4 E00DEA 0 +OP4 E00DEB 0 +OP4 E00DEC 0 +OP4 E00DED 0 +OP4 E00DEE 0 +OP4 E00DEF 0 +OP4 E00DF0 0 +OP4 E00DF1 0 +OP4 E00DF2 0 +OP4 E00DF3 0 +OP4 E00DF4 0 +OP4 E00DF5 0 +OP4 E00DF6 0 +OP4 E00DF7 0 +OP4 E00DF8 0 +OP4 E00DF9 0 +OP4 E00DFA 0 +OP4 E00DFB 0 +OP4 E00DFC 0 +OP4 E00DFD 0 +OP4 E00DFE 0 +OP4 E00DFF 0 +OP4 E00E00 0 +OP4 E00E01 0 +OP4 E00E02 0 +OP4 E00E03 0 +OP4 E00E04 0 +OP4 E00E05 0 +OP4 E00E06 0 +OP4 E00E07 0 +OP4 E00E08 0 +OP4 E00E09 0 +OP4 E00E0A 0 +OP4 E00E0B 0 +OP4 E00E0C 0 +OP4 E00E0D 0 +OP4 E00E0E 0 +OP4 E00E0F 0 +OP4 E00E10 0 +OP4 E00E11 0 +OP4 E00E12 0 +OP4 E00E13 0 +OP4 E00E14 0 +OP4 E00E15 0 +OP4 E00E16 0 +OP4 E00E17 0 +OP4 E00E18 0 +OP4 E00E19 0 +OP4 E00E1A 0 +OP4 E00E1B 0 +OP4 E00E1C 0 +OP4 E00E1D 0 +OP4 E00E1E 0 +OP4 E00E1F 0 +OP4 E00E20 0 +OP4 E00E21 0 +OP4 E00E22 0 +OP4 E00E23 0 +OP4 E00E24 0 +OP4 E00E25 0 +OP4 E00E26 0 +OP4 E00E27 0 +OP4 E00E28 0 +OP4 E00E29 0 +OP4 E00E2A 0 +OP4 E00E2B 0 +OP4 E00E2C 0 +OP4 E00E2D 0 +OP4 E00E2E 0 +OP4 E00E2F 0 +OP4 E00E30 0 +OP4 E00E31 0 +OP4 E00E32 0 +OP4 E00E33 0 +OP4 E00E34 0 +OP4 E00E35 0 +OP4 E00E36 0 +OP4 E00E37 0 +OP4 E00E38 0 +OP4 E00E39 0 +OP4 E00E3A 0 +OP4 E00E3B 0 +OP4 E00E3C 0 +OP4 E00E3D 0 +OP4 E00E3E 0 +OP4 E00E3F 0 +OP4 E00E40 0 +OP4 E00E41 0 +OP4 E00E42 0 +OP4 E00E43 0 +OP4 E00E44 0 +OP4 E00E45 0 +OP4 E00E46 0 +OP4 E00E47 0 +OP4 E00E48 0 +OP4 E00E49 0 +OP4 E00E4A 0 +OP4 E00E4B 0 +OP4 E00E4C 0 +OP4 E00E4D 0 +OP4 E00E4E 0 +OP4 E00E4F 0 +OP4 E00E50 0 +OP4 E00E51 0 +OP4 E00E52 0 +OP4 E00E53 0 +OP4 E00E54 0 +OP4 E00E55 0 +OP4 E00E56 0 +OP4 E00E57 0 +OP4 E00E58 0 +OP4 E00E59 0 +OP4 E00E5A 0 +OP4 E00E5B 0 +OP4 E00E5C 0 +OP4 E00E5D 0 +OP4 E00E5E 0 +OP4 E00E5F 0 +OP4 E00E60 0 +OP4 E00E61 0 +OP4 E00E62 0 +OP4 E00E63 0 +OP4 E00E64 0 +OP4 E00E65 0 +OP4 E00E66 0 +OP4 E00E67 0 +OP4 E00E68 0 +OP4 E00E69 0 +OP4 E00E6A 0 +OP4 E00E6B 0 +OP4 E00E6C 0 +OP4 E00E6D 0 +OP4 E00E6E 0 +OP4 E00E6F 0 +OP4 E00E70 0 +OP4 E00E71 0 +OP4 E00E72 0 +OP4 E00E73 0 +OP4 E00E74 0 +OP4 E00E75 0 +OP4 E00E76 0 +OP4 E00E77 0 +OP4 E00E78 0 +OP4 E00E79 0 +OP4 E00E7A 0 +OP4 E00E7B 0 +OP4 E00E7C 0 +OP4 E00E7D 0 +OP4 E00E7E 0 +OP4 E00E7F 0 +OP4 E00E80 0 +OP4 E00E81 0 +OP4 E00E82 0 +OP4 E00E83 0 +OP4 E00E84 0 +OP4 E00E85 0 +OP4 E00E86 0 +OP4 E00E87 0 +OP4 E00E88 0 +OP4 E00E89 0 +OP4 E00E8A 0 +OP4 E00E8B 0 +OP4 E00E8C 0 +OP4 E00E8D 0 +OP4 E00E8E 0 +OP4 E00E8F 0 +OP4 E00E90 0 +OP4 E00E91 0 +OP4 E00E92 0 +OP4 E00E93 0 +OP4 E00E94 0 +OP4 E00E95 0 +OP4 E00E96 0 +OP4 E00E97 0 +OP4 E00E98 0 +OP4 E00E99 0 +OP4 E00E9A 0 +OP4 E00E9B 0 +OP4 E00E9C 0 +OP4 E00E9D 0 +OP4 E00E9E 0 +OP4 E00E9F 0 +OP4 E00EA0 0 +OP4 E00EA1 0 +OP4 E00EA2 0 +OP4 E00EA3 0 +OP4 E00EA4 0 +OP4 E00EA5 0 +OP4 E00EA6 0 +OP4 E00EA7 0 +OP4 E00EA8 0 +OP4 E00EA9 0 +OP4 E00EAA 0 +OP4 E00EAB 0 +OP4 E00EAC 0 +OP4 E00EAD 0 +OP4 E00EAE 0 +OP4 E00EAF 0 +OP4 E00EB0 0 +OP4 E00EB1 0 +OP4 E00EB2 0 +OP4 E00EB3 0 +OP4 E00EB4 0 +OP4 E00EB5 0 +OP4 E00EB6 0 +OP4 E00EB7 0 +OP4 E00EB8 0 +OP4 E00EB9 0 +OP4 E00EBA 0 +OP4 E00EBB 0 +OP4 E00EBC 0 +OP4 E00EBD 0 +OP4 E00EBE 0 +OP4 E00EBF 0 +OP4 E00EC0 0 +OP4 E00EC1 0 +OP4 E00EC2 0 +OP4 E00EC3 0 +OP4 E00EC4 0 +OP4 E00EC5 0 +OP4 E00EC6 0 +OP4 E00EC7 0 +OP4 E00EC8 0 +OP4 E00EC9 0 +OP4 E00ECA 0 +OP4 E00ECB 0 +OP4 E00ECC 0 +OP4 E00ECD 0 +OP4 E00ECE 0 +OP4 E00ECF 0 +OP4 E00ED0 0 +OP4 E00ED1 0 +OP4 E00ED2 0 +OP4 E00ED3 0 +OP4 E00ED4 0 +OP4 E00ED5 0 +OP4 E00ED6 0 +OP4 E00ED7 0 +OP4 E00ED8 0 +OP4 E00ED9 0 +OP4 E00EDA 0 +OP4 E00EDB 0 +OP4 E00EDC 0 +OP4 E00EDD 0 +OP4 E00EDE 0 +OP4 E00EDF 0 +OP4 E00EE0 0 +OP4 E00EE1 0 +OP4 E00EE2 0 +OP4 E00EE3 0 +OP4 E00EE4 0 +OP4 E00EE5 0 +OP4 E00EE6 0 +OP4 E00EE7 0 +OP4 E00EE8 0 +OP4 E00EE9 0 +OP4 E00EEA 0 +OP4 E00EEB 0 +OP4 E00EEC 0 +OP4 E00EED 0 +OP4 E00EEE 0 +OP4 E00EEF 0 +OP4 E00EF0 0 +OP4 E00EF1 0 +OP4 E00EF2 0 +OP4 E00EF3 0 +OP4 E00EF4 0 +OP4 E00EF5 0 +OP4 E00EF6 0 +OP4 E00EF7 0 +OP4 E00EF8 0 +OP4 E00EF9 0 +OP4 E00EFA 0 +OP4 E00EFB 0 +OP4 E00EFC 0 +OP4 E00EFD 0 +OP4 E00EFE 0 +OP4 E00EFF 0 +OP4 E00F00 0 +OP4 E00F01 0 +OP4 E00F02 0 +OP4 E00F03 0 +OP4 E00F04 0 +OP4 E00F05 0 +OP4 E00F06 0 +OP4 E00F07 0 +OP4 E00F08 0 +OP4 E00F09 0 +OP4 E00F0A 0 +OP4 E00F0B 0 +OP4 E00F0C 0 +OP4 E00F0D 0 +OP4 E00F0E 0 +OP4 E00F0F 0 +OP4 E00F10 0 +OP4 E00F11 0 +OP4 E00F12 0 +OP4 E00F13 0 +OP4 E00F14 0 +OP4 E00F15 0 +OP4 E00F16 0 +OP4 E00F17 0 +OP4 E00F18 0 +OP4 E00F19 0 +OP4 E00F1A 0 +OP4 E00F1B 0 +OP4 E00F1C 0 +OP4 E00F1D 0 +OP4 E00F1E 0 +OP4 E00F1F 0 +OP4 E00F20 0 +OP4 E00F21 0 +OP4 E00F22 0 +OP4 E00F23 0 +OP4 E00F24 0 +OP4 E00F25 0 +OP4 E00F26 0 +OP4 E00F27 0 +OP4 E00F28 0 +OP4 E00F29 0 +OP4 E00F2A 0 +OP4 E00F2B 0 +OP4 E00F2C 0 +OP4 E00F2D 0 +OP4 E00F2E 0 +OP4 E00F2F 0 +OP4 E00F30 0 diff --git a/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum3_itrace_irisc8.cfg.ext b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum3_itrace_irisc8.cfg.ext new file mode 100644 index 000000000000..2b7751023c6a --- /dev/null +++ b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum3_itrace_irisc8.cfg.ext @@ -0,0 +1,3890 @@ +OP1 Spectrum3 +OP4 ITRACE0 0 +OP4 ITRACE1 0 +OP4 ITRACE2 0 +OP4 ITRACE3 0 +OP4 ITRACE4 0 +OP4 ITRACE5 0 +OP4 ITRACE6 0 +OP4 ITRACE7 0 +OP4 ITRACE8 1 +OP4 ITRACE9 0 +OP4 Main_PhyUC 0 +OP4 TILE0_ITRACE0 0 +OP4 TILE0_ITRACE1 0 +OP4 TILE0_ITRACE2 0 +OP4 TILE0_ITRACE3 0 +OP4 TILE0_ITRACE4 0 +OP4 TILE0_PhyUC 0 +OP4 TILE1_ITRACE0 0 +OP4 TILE1_ITRACE1 0 +OP4 TILE1_ITRACE2 0 +OP4 TILE1_ITRACE3 0 +OP4 TILE1_ITRACE4 0 +OP4 TILE1_PhyUC 0 +OP4 TILE2_ITRACE0 0 +OP4 TILE2_ITRACE1 0 +OP4 TILE2_ITRACE2 0 +OP4 TILE2_ITRACE3 0 +OP4 TILE2_ITRACE4 0 +OP4 TILE2_PhyUC 0 +OP4 TILE3_ITRACE0 0 +OP4 TILE3_ITRACE1 0 +OP4 TILE3_ITRACE2 0 +OP4 TILE3_ITRACE3 0 +OP4 TILE3_ITRACE4 0 +OP4 TILE3_PhyUC 0 +OP4 TILE4_ITRACE0 0 +OP4 TILE4_ITRACE1 0 +OP4 TILE4_ITRACE2 0 +OP4 TILE4_ITRACE3 0 +OP4 TILE4_ITRACE4 0 +OP4 TILE4_PhyUC 0 +OP4 TILE5_ITRACE0 0 +OP4 TILE5_ITRACE1 0 +OP4 TILE5_ITRACE2 0 +OP4 TILE5_ITRACE3 0 +OP4 TILE5_ITRACE4 0 +OP4 TILE5_PhyUC 0 +OP4 TILE6_ITRACE0 0 +OP4 TILE6_ITRACE1 0 +OP4 TILE6_ITRACE2 0 +OP4 TILE6_ITRACE3 0 +OP4 TILE6_ITRACE4 0 +OP4 TILE6_PhyUC 0 +OP4 TILE7_ITRACE0 0 +OP4 TILE7_ITRACE1 0 +OP4 TILE7_ITRACE2 0 +OP4 TILE7_ITRACE3 0 +OP4 TILE7_ITRACE4 0 +OP4 TILE7_PhyUC 0 +OP4 E0003B 0 +OP4 E0003C 0 +OP4 E0003D 0 +OP4 E0003E 0 +OP4 E0003F 0 +OP4 E00040 0 +OP4 E00041 0 +OP4 E00042 0 +OP4 E00043 0 +OP4 E00044 0 +OP4 E00045 0 +OP4 E00046 0 +OP4 E00047 0 +OP4 E00048 0 +OP4 E00049 0 +OP4 E0004A 0 +OP4 E0004B 0 +OP4 E0004C 0 +OP4 E0004D 0 +OP4 E0004E 0 +OP4 E0004F 0 +OP4 E00050 0 +OP4 E00051 0 +OP4 E00052 0 +OP4 E00053 0 +OP4 E00054 0 +OP4 E00055 0 +OP4 E00056 0 +OP4 E00057 0 +OP4 E00058 0 +OP4 E00059 0 +OP4 E0005A 0 +OP4 E0005B 0 +OP4 E0005C 0 +OP4 E0005D 0 +OP4 E0005E 0 +OP4 E0005F 0 +OP4 E00060 0 +OP4 E00061 0 +OP4 E00062 0 +OP4 E00063 0 +OP4 E00064 0 +OP4 E00065 0 +OP4 E00066 0 +OP4 E00067 0 +OP4 E00068 0 +OP4 E00069 0 +OP4 E0006A 0 +OP4 E0006B 0 +OP4 E0006C 0 +OP4 E0006D 0 +OP4 E0006E 0 +OP4 E0006F 0 +OP4 E00070 0 +OP4 E00071 0 +OP4 E00072 0 +OP4 E00073 0 +OP4 E00074 0 +OP4 E00075 0 +OP4 E00076 0 +OP4 E00077 0 +OP4 E00078 0 +OP4 E00079 0 +OP4 E0007A 0 +OP4 E0007B 0 +OP4 E0007C 0 +OP4 E0007D 0 +OP4 E0007E 0 +OP4 E0007F 0 +OP4 E00080 0 +OP4 E00081 0 +OP4 E00082 0 +OP4 E00083 0 +OP4 E00084 0 +OP4 E00085 0 +OP4 E00086 0 +OP4 E00087 0 +OP4 E00088 0 +OP4 E00089 0 +OP4 E0008A 0 +OP4 E0008B 0 +OP4 E0008C 0 +OP4 E0008D 0 +OP4 E0008E 0 +OP4 E0008F 0 +OP4 E00090 0 +OP4 E00091 0 +OP4 E00092 0 +OP4 E00093 0 +OP4 E00094 0 +OP4 E00095 0 +OP4 E00096 0 +OP4 E00097 0 +OP4 E00098 0 +OP4 E00099 0 +OP4 E0009A 0 +OP4 E0009B 0 +OP4 E0009C 0 +OP4 E0009D 0 +OP4 E0009E 0 +OP4 E0009F 0 +OP4 E000A0 0 +OP4 E000A1 0 +OP4 E000A2 0 +OP4 E000A3 0 +OP4 E000A4 0 +OP4 E000A5 0 +OP4 E000A6 0 +OP4 E000A7 0 +OP4 E000A8 0 +OP4 E000A9 0 +OP4 E000AA 0 +OP4 E000AB 0 +OP4 E000AC 0 +OP4 E000AD 0 +OP4 E000AE 0 +OP4 E000AF 0 +OP4 E000B0 0 +OP4 E000B1 0 +OP4 E000B2 0 +OP4 E000B3 0 +OP4 E000B4 0 +OP4 E000B5 0 +OP4 E000B6 0 +OP4 E000B7 0 +OP4 E000B8 0 +OP4 E000B9 0 +OP4 E000BA 0 +OP4 E000BB 0 +OP4 E000BC 0 +OP4 E000BD 0 +OP4 E000BE 0 +OP4 E000BF 0 +OP4 E000C0 0 +OP4 E000C1 0 +OP4 E000C2 0 +OP4 E000C3 0 +OP4 E000C4 0 +OP4 E000C5 0 +OP4 E000C6 0 +OP4 E000C7 0 +OP4 E000C8 0 +OP4 E000C9 0 +OP4 E000CA 0 +OP4 E000CB 0 +OP4 E000CC 0 +OP4 E000CD 0 +OP4 E000CE 0 +OP4 E000CF 0 +OP4 E000D0 0 +OP4 E000D1 0 +OP4 E000D2 0 +OP4 E000D3 0 +OP4 E000D4 0 +OP4 E000D5 0 +OP4 E000D6 0 +OP4 E000D7 0 +OP4 E000D8 0 +OP4 E000D9 0 +OP4 E000DA 0 +OP4 E000DB 0 +OP4 E000DC 0 +OP4 E000DD 0 +OP4 E000DE 0 +OP4 E000DF 0 +OP4 E000E0 0 +OP4 E000E1 0 +OP4 E000E2 0 +OP4 E000E3 0 +OP4 E000E4 0 +OP4 E000E5 0 +OP4 E000E6 0 +OP4 E000E7 0 +OP4 E000E8 0 +OP4 E000E9 0 +OP4 E000EA 0 +OP4 E000EB 0 +OP4 E000EC 0 +OP4 E000ED 0 +OP4 E000EE 0 +OP4 E000EF 0 +OP4 E000F0 0 +OP4 E000F1 0 +OP4 E000F2 0 +OP4 E000F3 0 +OP4 E000F4 0 +OP4 E000F5 0 +OP4 E000F6 0 +OP4 E000F7 0 +OP4 E000F8 0 +OP4 E000F9 0 +OP4 E000FA 0 +OP4 E000FB 0 +OP4 E000FC 0 +OP4 E000FD 0 +OP4 E000FE 0 +OP4 E000FF 0 +OP4 E00100 0 +OP4 E00101 0 +OP4 E00102 0 +OP4 E00103 0 +OP4 E00104 0 +OP4 E00105 0 +OP4 E00106 0 +OP4 E00107 0 +OP4 E00108 0 +OP4 E00109 0 +OP4 E0010A 0 +OP4 E0010B 0 +OP4 E0010C 0 +OP4 E0010D 0 +OP4 E0010E 0 +OP4 E0010F 0 +OP4 E00110 0 +OP4 E00111 0 +OP4 E00112 0 +OP4 E00113 0 +OP4 E00114 0 +OP4 E00115 0 +OP4 E00116 0 +OP4 E00117 0 +OP4 E00118 0 +OP4 E00119 0 +OP4 E0011A 0 +OP4 E0011B 0 +OP4 E0011C 0 +OP4 E0011D 0 +OP4 E0011E 0 +OP4 E0011F 0 +OP4 E00120 0 +OP4 E00121 0 +OP4 E00122 0 +OP4 E00123 0 +OP4 E00124 0 +OP4 E00125 0 +OP4 E00126 0 +OP4 E00127 0 +OP4 E00128 0 +OP4 E00129 0 +OP4 E0012A 0 +OP4 E0012B 0 +OP4 E0012C 0 +OP4 E0012D 0 +OP4 E0012E 0 +OP4 E0012F 0 +OP4 E00130 0 +OP4 E00131 0 +OP4 E00132 0 +OP4 E00133 0 +OP4 E00134 0 +OP4 E00135 0 +OP4 E00136 0 +OP4 E00137 0 +OP4 E00138 0 +OP4 E00139 0 +OP4 E0013A 0 +OP4 E0013B 0 +OP4 E0013C 0 +OP4 E0013D 0 +OP4 E0013E 0 +OP4 E0013F 0 +OP4 E00140 0 +OP4 E00141 0 +OP4 E00142 0 +OP4 E00143 0 +OP4 E00144 0 +OP4 E00145 0 +OP4 E00146 0 +OP4 E00147 0 +OP4 E00148 0 +OP4 E00149 0 +OP4 E0014A 0 +OP4 E0014B 0 +OP4 E0014C 0 +OP4 E0014D 0 +OP4 E0014E 0 +OP4 E0014F 0 +OP4 E00150 0 +OP4 E00151 0 +OP4 E00152 0 +OP4 E00153 0 +OP4 E00154 0 +OP4 E00155 0 +OP4 E00156 0 +OP4 E00157 0 +OP4 E00158 0 +OP4 E00159 0 +OP4 E0015A 0 +OP4 E0015B 0 +OP4 E0015C 0 +OP4 E0015D 0 +OP4 E0015E 0 +OP4 E0015F 0 +OP4 E00160 0 +OP4 E00161 0 +OP4 E00162 0 +OP4 E00163 0 +OP4 E00164 0 +OP4 E00165 0 +OP4 E00166 0 +OP4 E00167 0 +OP4 E00168 0 +OP4 E00169 0 +OP4 E0016A 0 +OP4 E0016B 0 +OP4 E0016C 0 +OP4 E0016D 0 +OP4 E0016E 0 +OP4 E0016F 0 +OP4 E00170 0 +OP4 E00171 0 +OP4 E00172 0 +OP4 E00173 0 +OP4 E00174 0 +OP4 E00175 0 +OP4 E00176 0 +OP4 E00177 0 +OP4 E00178 0 +OP4 E00179 0 +OP4 E0017A 0 +OP4 E0017B 0 +OP4 E0017C 0 +OP4 E0017D 0 +OP4 E0017E 0 +OP4 E0017F 0 +OP4 E00180 0 +OP4 E00181 0 +OP4 E00182 0 +OP4 E00183 0 +OP4 E00184 0 +OP4 E00185 0 +OP4 E00186 0 +OP4 E00187 0 +OP4 E00188 0 +OP4 E00189 0 +OP4 E0018A 0 +OP4 E0018B 0 +OP4 E0018C 0 +OP4 E0018D 0 +OP4 E0018E 0 +OP4 E0018F 0 +OP4 E00190 0 +OP4 E00191 0 +OP4 E00192 0 +OP4 E00193 0 +OP4 E00194 0 +OP4 E00195 0 +OP4 E00196 0 +OP4 E00197 0 +OP4 E00198 0 +OP4 E00199 0 +OP4 E0019A 0 +OP4 E0019B 0 +OP4 E0019C 0 +OP4 E0019D 0 +OP4 E0019E 0 +OP4 E0019F 0 +OP4 E001A0 0 +OP4 E001A1 0 +OP4 E001A2 0 +OP4 E001A3 0 +OP4 E001A4 0 +OP4 E001A5 0 +OP4 E001A6 0 +OP4 E001A7 0 +OP4 E001A8 0 +OP4 E001A9 0 +OP4 E001AA 0 +OP4 E001AB 0 +OP4 E001AC 0 +OP4 E001AD 0 +OP4 E001AE 0 +OP4 E001AF 0 +OP4 E001B0 0 +OP4 E001B1 0 +OP4 E001B2 0 +OP4 E001B3 0 +OP4 E001B4 0 +OP4 E001B5 0 +OP4 E001B6 0 +OP4 E001B7 0 +OP4 E001B8 0 +OP4 E001B9 0 +OP4 E001BA 0 +OP4 E001BB 0 +OP4 E001BC 0 +OP4 E001BD 0 +OP4 E001BE 0 +OP4 E001BF 0 +OP4 E001C0 0 +OP4 E001C1 0 +OP4 E001C2 0 +OP4 E001C3 0 +OP4 E001C4 0 +OP4 E001C5 0 +OP4 E001C6 0 +OP4 E001C7 0 +OP4 E001C8 0 +OP4 E001C9 0 +OP4 E001CA 0 +OP4 E001CB 0 +OP4 E001CC 0 +OP4 E001CD 0 +OP4 E001CE 0 +OP4 E001CF 0 +OP4 E001D0 0 +OP4 E001D1 0 +OP4 E001D2 0 +OP4 E001D3 0 +OP4 E001D4 0 +OP4 E001D5 0 +OP4 E001D6 0 +OP4 E001D7 0 +OP4 E001D8 0 +OP4 E001D9 0 +OP4 E001DA 0 +OP4 E001DB 0 +OP4 E001DC 0 +OP4 E001DD 0 +OP4 E001DE 0 +OP4 E001DF 0 +OP4 E001E0 0 +OP4 E001E1 0 +OP4 E001E2 0 +OP4 E001E3 0 +OP4 E001E4 0 +OP4 E001E5 0 +OP4 E001E6 0 +OP4 E001E7 0 +OP4 E001E8 0 +OP4 E001E9 0 +OP4 E001EA 0 +OP4 E001EB 0 +OP4 E001EC 0 +OP4 E001ED 0 +OP4 E001EE 0 +OP4 E001EF 0 +OP4 E001F0 0 +OP4 E001F1 0 +OP4 E001F2 0 +OP4 E001F3 0 +OP4 E001F4 0 +OP4 E001F5 0 +OP4 E001F6 0 +OP4 E001F7 0 +OP4 E001F8 0 +OP4 E001F9 0 +OP4 E001FA 0 +OP4 E001FB 0 +OP4 E001FC 0 +OP4 E001FD 0 +OP4 E001FE 0 +OP4 E001FF 0 +OP4 E00200 0 +OP4 E00201 0 +OP4 E00202 0 +OP4 E00203 0 +OP4 E00204 0 +OP4 E00205 0 +OP4 E00206 0 +OP4 E00207 0 +OP4 E00208 0 +OP4 E00209 0 +OP4 E0020A 0 +OP4 E0020B 0 +OP4 E0020C 0 +OP4 E0020D 0 +OP4 E0020E 0 +OP4 E0020F 0 +OP4 E00210 0 +OP4 E00211 0 +OP4 E00212 0 +OP4 E00213 0 +OP4 E00214 0 +OP4 E00215 0 +OP4 E00216 0 +OP4 E00217 0 +OP4 E00218 0 +OP4 E00219 0 +OP4 E0021A 0 +OP4 E0021B 0 +OP4 E0021C 0 +OP4 E0021D 0 +OP4 E0021E 0 +OP4 E0021F 0 +OP4 E00220 0 +OP4 E00221 0 +OP4 E00222 0 +OP4 E00223 0 +OP4 E00224 0 +OP4 E00225 0 +OP4 E00226 0 +OP4 E00227 0 +OP4 E00228 0 +OP4 E00229 0 +OP4 E0022A 0 +OP4 E0022B 0 +OP4 E0022C 0 +OP4 E0022D 0 +OP4 E0022E 0 +OP4 E0022F 0 +OP4 E00230 0 +OP4 E00231 0 +OP4 E00232 0 +OP4 E00233 0 +OP4 E00234 0 +OP4 E00235 0 +OP4 E00236 0 +OP4 E00237 0 +OP4 E00238 0 +OP4 E00239 0 +OP4 E0023A 0 +OP4 E0023B 0 +OP4 E0023C 0 +OP4 E0023D 0 +OP4 E0023E 0 +OP4 E0023F 0 +OP4 E00240 0 +OP4 E00241 0 +OP4 E00242 0 +OP4 E00243 0 +OP4 E00244 0 +OP4 E00245 0 +OP4 E00246 0 +OP4 E00247 0 +OP4 E00248 0 +OP4 E00249 0 +OP4 E0024A 0 +OP4 E0024B 0 +OP4 E0024C 0 +OP4 E0024D 0 +OP4 E0024E 0 +OP4 E0024F 0 +OP4 E00250 0 +OP4 E00251 0 +OP4 E00252 0 +OP4 E00253 0 +OP4 E00254 0 +OP4 E00255 0 +OP4 E00256 0 +OP4 E00257 0 +OP4 E00258 0 +OP4 E00259 0 +OP4 E0025A 0 +OP4 E0025B 0 +OP4 E0025C 0 +OP4 E0025D 0 +OP4 E0025E 0 +OP4 E0025F 0 +OP4 E00260 0 +OP4 E00261 0 +OP4 E00262 0 +OP4 E00263 0 +OP4 E00264 0 +OP4 E00265 0 +OP4 E00266 0 +OP4 E00267 0 +OP4 E00268 0 +OP4 E00269 0 +OP4 E0026A 0 +OP4 E0026B 0 +OP4 E0026C 0 +OP4 E0026D 0 +OP4 E0026E 0 +OP4 E0026F 0 +OP4 E00270 0 +OP4 E00271 0 +OP4 E00272 0 +OP4 E00273 0 +OP4 E00274 0 +OP4 E00275 0 +OP4 E00276 0 +OP4 E00277 0 +OP4 E00278 0 +OP4 E00279 0 +OP4 E0027A 0 +OP4 E0027B 0 +OP4 E0027C 0 +OP4 E0027D 0 +OP4 E0027E 0 +OP4 E0027F 0 +OP4 E00280 0 +OP4 E00281 0 +OP4 E00282 0 +OP4 E00283 0 +OP4 E00284 0 +OP4 E00285 0 +OP4 E00286 0 +OP4 E00287 0 +OP4 E00288 0 +OP4 E00289 0 +OP4 E0028A 0 +OP4 E0028B 0 +OP4 E0028C 0 +OP4 E0028D 0 +OP4 E0028E 0 +OP4 E0028F 0 +OP4 E00290 0 +OP4 E00291 0 +OP4 E00292 0 +OP4 E00293 0 +OP4 E00294 0 +OP4 E00295 0 +OP4 E00296 0 +OP4 E00297 0 +OP4 E00298 0 +OP4 E00299 0 +OP4 E0029A 0 +OP4 E0029B 0 +OP4 E0029C 0 +OP4 E0029D 0 +OP4 E0029E 0 +OP4 E0029F 0 +OP4 E002A0 0 +OP4 E002A1 0 +OP4 E002A2 0 +OP4 E002A3 0 +OP4 E002A4 0 +OP4 E002A5 0 +OP4 E002A6 0 +OP4 E002A7 0 +OP4 E002A8 0 +OP4 E002A9 0 +OP4 E002AA 0 +OP4 E002AB 0 +OP4 E002AC 0 +OP4 E002AD 0 +OP4 E002AE 0 +OP4 E002AF 0 +OP4 E002B0 0 +OP4 E002B1 0 +OP4 E002B2 0 +OP4 E002B3 0 +OP4 E002B4 0 +OP4 E002B5 0 +OP4 E002B6 0 +OP4 E002B7 0 +OP4 E002B8 0 +OP4 E002B9 0 +OP4 E002BA 0 +OP4 E002BB 0 +OP4 E002BC 0 +OP4 E002BD 0 +OP4 E002BE 0 +OP4 E002BF 0 +OP4 E002C0 0 +OP4 E002C1 0 +OP4 E002C2 0 +OP4 E002C3 0 +OP4 E002C4 0 +OP4 E002C5 0 +OP4 E002C6 0 +OP4 E002C7 0 +OP4 E002C8 0 +OP4 E002C9 0 +OP4 E002CA 0 +OP4 E002CB 0 +OP4 E002CC 0 +OP4 E002CD 0 +OP4 E002CE 0 +OP4 E002CF 0 +OP4 E002D0 0 +OP4 E002D1 0 +OP4 E002D2 0 +OP4 E002D3 0 +OP4 E002D4 0 +OP4 E002D5 0 +OP4 E002D6 0 +OP4 E002D7 0 +OP4 E002D8 0 +OP4 E002D9 0 +OP4 E002DA 0 +OP4 E002DB 0 +OP4 E002DC 0 +OP4 E002DD 0 +OP4 E002DE 0 +OP4 E002DF 0 +OP4 E002E0 0 +OP4 E002E1 0 +OP4 E002E2 0 +OP4 E002E3 0 +OP4 E002E4 0 +OP4 E002E5 0 +OP4 E002E6 0 +OP4 E002E7 0 +OP4 E002E8 0 +OP4 E002E9 0 +OP4 E002EA 0 +OP4 E002EB 0 +OP4 E002EC 0 +OP4 E002ED 0 +OP4 E002EE 0 +OP4 E002EF 0 +OP4 E002F0 0 +OP4 E002F1 0 +OP4 E002F2 0 +OP4 E002F3 0 +OP4 E002F4 0 +OP4 E002F5 0 +OP4 E002F6 0 +OP4 E002F7 0 +OP4 E002F8 0 +OP4 E002F9 0 +OP4 E002FA 0 +OP4 E002FB 0 +OP4 E002FC 0 +OP4 E002FD 0 +OP4 E002FE 0 +OP4 E002FF 0 +OP4 E00300 0 +OP4 E00301 0 +OP4 E00302 0 +OP4 E00303 0 +OP4 E00304 0 +OP4 E00305 0 +OP4 E00306 0 +OP4 E00307 0 +OP4 E00308 0 +OP4 E00309 0 +OP4 E0030A 0 +OP4 E0030B 0 +OP4 E0030C 0 +OP4 E0030D 0 +OP4 E0030E 0 +OP4 E0030F 0 +OP4 E00310 0 +OP4 E00311 0 +OP4 E00312 0 +OP4 E00313 0 +OP4 E00314 0 +OP4 E00315 0 +OP4 E00316 0 +OP4 E00317 0 +OP4 E00318 0 +OP4 E00319 0 +OP4 E0031A 0 +OP4 E0031B 0 +OP4 E0031C 0 +OP4 E0031D 0 +OP4 E0031E 0 +OP4 E0031F 0 +OP4 E00320 0 +OP4 E00321 0 +OP4 E00322 0 +OP4 E00323 0 +OP4 E00324 0 +OP4 E00325 0 +OP4 E00326 0 +OP4 E00327 0 +OP4 E00328 0 +OP4 E00329 0 +OP4 E0032A 0 +OP4 E0032B 0 +OP4 E0032C 0 +OP4 E0032D 0 +OP4 E0032E 0 +OP4 E0032F 0 +OP4 E00330 0 +OP4 E00331 0 +OP4 E00332 0 +OP4 E00333 0 +OP4 E00334 0 +OP4 E00335 0 +OP4 E00336 0 +OP4 E00337 0 +OP4 E00338 0 +OP4 E00339 0 +OP4 E0033A 0 +OP4 E0033B 0 +OP4 E0033C 0 +OP4 E0033D 0 +OP4 E0033E 0 +OP4 E0033F 0 +OP4 E00340 0 +OP4 E00341 0 +OP4 E00342 0 +OP4 E00343 0 +OP4 E00344 0 +OP4 E00345 0 +OP4 E00346 0 +OP4 E00347 0 +OP4 E00348 0 +OP4 E00349 0 +OP4 E0034A 0 +OP4 E0034B 0 +OP4 E0034C 0 +OP4 E0034D 0 +OP4 E0034E 0 +OP4 E0034F 0 +OP4 E00350 0 +OP4 E00351 0 +OP4 E00352 0 +OP4 E00353 0 +OP4 E00354 0 +OP4 E00355 0 +OP4 E00356 0 +OP4 E00357 0 +OP4 E00358 0 +OP4 E00359 0 +OP4 E0035A 0 +OP4 E0035B 0 +OP4 E0035C 0 +OP4 E0035D 0 +OP4 E0035E 0 +OP4 E0035F 0 +OP4 E00360 0 +OP4 E00361 0 +OP4 E00362 0 +OP4 E00363 0 +OP4 E00364 0 +OP4 E00365 0 +OP4 E00366 0 +OP4 E00367 0 +OP4 E00368 0 +OP4 E00369 0 +OP4 E0036A 0 +OP4 E0036B 0 +OP4 E0036C 0 +OP4 E0036D 0 +OP4 E0036E 0 +OP4 E0036F 0 +OP4 E00370 0 +OP4 E00371 0 +OP4 E00372 0 +OP4 E00373 0 +OP4 E00374 0 +OP4 E00375 0 +OP4 E00376 0 +OP4 E00377 0 +OP4 E00378 0 +OP4 E00379 0 +OP4 E0037A 0 +OP4 E0037B 0 +OP4 E0037C 0 +OP4 E0037D 0 +OP4 E0037E 0 +OP4 E0037F 0 +OP4 E00380 0 +OP4 E00381 0 +OP4 E00382 0 +OP4 E00383 0 +OP4 E00384 0 +OP4 E00385 0 +OP4 E00386 0 +OP4 E00387 0 +OP4 E00388 0 +OP4 E00389 0 +OP4 E0038A 0 +OP4 E0038B 0 +OP4 E0038C 0 +OP4 E0038D 0 +OP4 E0038E 0 +OP4 E0038F 0 +OP4 E00390 0 +OP4 E00391 0 +OP4 E00392 0 +OP4 E00393 0 +OP4 E00394 0 +OP4 E00395 0 +OP4 E00396 0 +OP4 E00397 0 +OP4 E00398 0 +OP4 E00399 0 +OP4 E0039A 0 +OP4 E0039B 0 +OP4 E0039C 0 +OP4 E0039D 0 +OP4 E0039E 0 +OP4 E0039F 0 +OP4 E003A0 0 +OP4 E003A1 0 +OP4 E003A2 0 +OP4 E003A3 0 +OP4 E003A4 0 +OP4 E003A5 0 +OP4 E003A6 0 +OP4 E003A7 0 +OP4 E003A8 0 +OP4 E003A9 0 +OP4 E003AA 0 +OP4 E003AB 0 +OP4 E003AC 0 +OP4 E003AD 0 +OP4 E003AE 0 +OP4 E003AF 0 +OP4 E003B0 0 +OP4 E003B1 0 +OP4 E003B2 0 +OP4 E003B3 0 +OP4 E003B4 0 +OP4 E003B5 0 +OP4 E003B6 0 +OP4 E003B7 0 +OP4 E003B8 0 +OP4 E003B9 0 +OP4 E003BA 0 +OP4 E003BB 0 +OP4 E003BC 0 +OP4 E003BD 0 +OP4 E003BE 0 +OP4 E003BF 0 +OP4 E003C0 0 +OP4 E003C1 0 +OP4 E003C2 0 +OP4 E003C3 0 +OP4 E003C4 0 +OP4 E003C5 0 +OP4 E003C6 0 +OP4 E003C7 0 +OP4 E003C8 0 +OP4 E003C9 0 +OP4 E003CA 0 +OP4 E003CB 0 +OP4 E003CC 0 +OP4 E003CD 0 +OP4 E003CE 0 +OP4 E003CF 0 +OP4 E003D0 0 +OP4 E003D1 0 +OP4 E003D2 0 +OP4 E003D3 0 +OP4 E003D4 0 +OP4 E003D5 0 +OP4 E003D6 0 +OP4 E003D7 0 +OP4 E003D8 0 +OP4 E003D9 0 +OP4 E003DA 0 +OP4 E003DB 0 +OP4 E003DC 0 +OP4 E003DD 0 +OP4 E003DE 0 +OP4 E003DF 0 +OP4 E003E0 0 +OP4 E003E1 0 +OP4 E003E2 0 +OP4 E003E3 0 +OP4 E003E4 0 +OP4 E003E5 0 +OP4 E003E6 0 +OP4 E003E7 0 +OP4 E003E8 0 +OP4 E003E9 0 +OP4 E003EA 0 +OP4 E003EB 0 +OP4 E003EC 0 +OP4 E003ED 0 +OP4 E003EE 0 +OP4 E003EF 0 +OP4 E003F0 0 +OP4 E003F1 0 +OP4 E003F2 0 +OP4 E003F3 0 +OP4 E003F4 0 +OP4 E003F5 0 +OP4 E003F6 0 +OP4 E003F7 0 +OP4 E003F8 0 +OP4 E003F9 0 +OP4 E003FA 0 +OP4 E003FB 0 +OP4 E003FC 0 +OP4 E003FD 0 +OP4 E003FE 0 +OP4 E003FF 0 +OP4 E00400 0 +OP4 E00401 0 +OP4 E00402 0 +OP4 E00403 0 +OP4 E00404 0 +OP4 E00405 0 +OP4 E00406 0 +OP4 E00407 0 +OP4 E00408 0 +OP4 E00409 0 +OP4 E0040A 0 +OP4 E0040B 0 +OP4 E0040C 0 +OP4 E0040D 0 +OP4 E0040E 0 +OP4 E0040F 0 +OP4 E00410 0 +OP4 E00411 0 +OP4 E00412 0 +OP4 E00413 0 +OP4 E00414 0 +OP4 E00415 0 +OP4 E00416 0 +OP4 E00417 0 +OP4 E00418 0 +OP4 E00419 0 +OP4 E0041A 0 +OP4 E0041B 0 +OP4 E0041C 0 +OP4 E0041D 0 +OP4 E0041E 0 +OP4 E0041F 0 +OP4 E00420 0 +OP4 E00421 0 +OP4 E00422 0 +OP4 E00423 0 +OP4 E00424 0 +OP4 E00425 0 +OP4 E00426 0 +OP4 E00427 0 +OP4 E00428 0 +OP4 E00429 0 +OP4 E0042A 0 +OP4 E0042B 0 +OP4 E0042C 0 +OP4 E0042D 0 +OP4 E0042E 0 +OP4 E0042F 0 +OP4 E00430 0 +OP4 E00431 0 +OP4 E00432 0 +OP4 E00433 0 +OP4 E00434 0 +OP4 E00435 0 +OP4 E00436 0 +OP4 E00437 0 +OP4 E00438 0 +OP4 E00439 0 +OP4 E0043A 0 +OP4 E0043B 0 +OP4 E0043C 0 +OP4 E0043D 0 +OP4 E0043E 0 +OP4 E0043F 0 +OP4 E00440 0 +OP4 E00441 0 +OP4 E00442 0 +OP4 E00443 0 +OP4 E00444 0 +OP4 E00445 0 +OP4 E00446 0 +OP4 E00447 0 +OP4 E00448 0 +OP4 E00449 0 +OP4 E0044A 0 +OP4 E0044B 0 +OP4 E0044C 0 +OP4 E0044D 0 +OP4 E0044E 0 +OP4 E0044F 0 +OP4 E00450 0 +OP4 E00451 0 +OP4 E00452 0 +OP4 E00453 0 +OP4 E00454 0 +OP4 E00455 0 +OP4 E00456 0 +OP4 E00457 0 +OP4 E00458 0 +OP4 E00459 0 +OP4 E0045A 0 +OP4 E0045B 0 +OP4 E0045C 0 +OP4 E0045D 0 +OP4 E0045E 0 +OP4 E0045F 0 +OP4 E00460 0 +OP4 E00461 0 +OP4 E00462 0 +OP4 E00463 0 +OP4 E00464 0 +OP4 E00465 0 +OP4 E00466 0 +OP4 E00467 0 +OP4 E00468 0 +OP4 E00469 0 +OP4 E0046A 0 +OP4 E0046B 0 +OP4 E0046C 0 +OP4 E0046D 0 +OP4 E0046E 0 +OP4 E0046F 0 +OP4 E00470 0 +OP4 E00471 0 +OP4 E00472 0 +OP4 E00473 0 +OP4 E00474 0 +OP4 E00475 0 +OP4 E00476 0 +OP4 E00477 0 +OP4 E00478 0 +OP4 E00479 0 +OP4 E0047A 0 +OP4 E0047B 0 +OP4 E0047C 0 +OP4 E0047D 0 +OP4 E0047E 0 +OP4 E0047F 0 +OP4 E00480 0 +OP4 E00481 0 +OP4 E00482 0 +OP4 E00483 0 +OP4 E00484 0 +OP4 E00485 0 +OP4 E00486 0 +OP4 E00487 0 +OP4 E00488 0 +OP4 E00489 0 +OP4 E0048A 0 +OP4 E0048B 0 +OP4 E0048C 0 +OP4 E0048D 0 +OP4 E0048E 0 +OP4 E0048F 0 +OP4 E00490 0 +OP4 E00491 0 +OP4 E00492 0 +OP4 E00493 0 +OP4 E00494 0 +OP4 E00495 0 +OP4 E00496 0 +OP4 E00497 0 +OP4 E00498 0 +OP4 E00499 0 +OP4 E0049A 0 +OP4 E0049B 0 +OP4 E0049C 0 +OP4 E0049D 0 +OP4 E0049E 0 +OP4 E0049F 0 +OP4 E004A0 0 +OP4 E004A1 0 +OP4 E004A2 0 +OP4 E004A3 0 +OP4 E004A4 0 +OP4 E004A5 0 +OP4 E004A6 0 +OP4 E004A7 0 +OP4 E004A8 0 +OP4 E004A9 0 +OP4 E004AA 0 +OP4 E004AB 0 +OP4 E004AC 0 +OP4 E004AD 0 +OP4 E004AE 0 +OP4 E004AF 0 +OP4 E004B0 0 +OP4 E004B1 0 +OP4 E004B2 0 +OP4 E004B3 0 +OP4 E004B4 0 +OP4 E004B5 0 +OP4 E004B6 0 +OP4 E004B7 0 +OP4 E004B8 0 +OP4 E004B9 0 +OP4 E004BA 0 +OP4 E004BB 0 +OP4 E004BC 0 +OP4 E004BD 0 +OP4 E004BE 0 +OP4 E004BF 0 +OP4 E004C0 0 +OP4 E004C1 0 +OP4 E004C2 0 +OP4 E004C3 0 +OP4 E004C4 0 +OP4 E004C5 0 +OP4 E004C6 0 +OP4 E004C7 0 +OP4 E004C8 0 +OP4 E004C9 0 +OP4 E004CA 0 +OP4 E004CB 0 +OP4 E004CC 0 +OP4 E004CD 0 +OP4 E004CE 0 +OP4 E004CF 0 +OP4 E004D0 0 +OP4 E004D1 0 +OP4 E004D2 0 +OP4 E004D3 0 +OP4 E004D4 0 +OP4 E004D5 0 +OP4 E004D6 0 +OP4 E004D7 0 +OP4 E004D8 0 +OP4 E004D9 0 +OP4 E004DA 0 +OP4 E004DB 0 +OP4 E004DC 0 +OP4 E004DD 0 +OP4 E004DE 0 +OP4 E004DF 0 +OP4 E004E0 0 +OP4 E004E1 0 +OP4 E004E2 0 +OP4 E004E3 0 +OP4 E004E4 0 +OP4 E004E5 0 +OP4 E004E6 0 +OP4 E004E7 0 +OP4 E004E8 0 +OP4 E004E9 0 +OP4 E004EA 0 +OP4 E004EB 0 +OP4 E004EC 0 +OP4 E004ED 0 +OP4 E004EE 0 +OP4 E004EF 0 +OP4 E004F0 0 +OP4 E004F1 0 +OP4 E004F2 0 +OP4 E004F3 0 +OP4 E004F4 0 +OP4 E004F5 0 +OP4 E004F6 0 +OP4 E004F7 0 +OP4 E004F8 0 +OP4 E004F9 0 +OP4 E004FA 0 +OP4 E004FB 0 +OP4 E004FC 0 +OP4 E004FD 0 +OP4 E004FE 0 +OP4 E004FF 0 +OP4 E00500 0 +OP4 E00501 0 +OP4 E00502 0 +OP4 E00503 0 +OP4 E00504 0 +OP4 E00505 0 +OP4 E00506 0 +OP4 E00507 0 +OP4 E00508 0 +OP4 E00509 0 +OP4 E0050A 0 +OP4 E0050B 0 +OP4 E0050C 0 +OP4 E0050D 0 +OP4 E0050E 0 +OP4 E0050F 0 +OP4 E00510 0 +OP4 E00511 0 +OP4 E00512 0 +OP4 E00513 0 +OP4 E00514 0 +OP4 E00515 0 +OP4 E00516 0 +OP4 E00517 0 +OP4 E00518 0 +OP4 E00519 0 +OP4 E0051A 0 +OP4 E0051B 0 +OP4 E0051C 0 +OP4 E0051D 0 +OP4 E0051E 0 +OP4 E0051F 0 +OP4 E00520 0 +OP4 E00521 0 +OP4 E00522 0 +OP4 E00523 0 +OP4 E00524 0 +OP4 E00525 0 +OP4 E00526 0 +OP4 E00527 0 +OP4 E00528 0 +OP4 E00529 0 +OP4 E0052A 0 +OP4 E0052B 0 +OP4 E0052C 0 +OP4 E0052D 0 +OP4 E0052E 0 +OP4 E0052F 0 +OP4 E00530 0 +OP4 E00531 0 +OP4 E00532 0 +OP4 E00533 0 +OP4 E00534 0 +OP4 E00535 0 +OP4 E00536 0 +OP4 E00537 0 +OP4 E00538 0 +OP4 E00539 0 +OP4 E0053A 0 +OP4 E0053B 0 +OP4 E0053C 0 +OP4 E0053D 0 +OP4 E0053E 0 +OP4 E0053F 0 +OP4 E00540 0 +OP4 E00541 0 +OP4 E00542 0 +OP4 E00543 0 +OP4 E00544 0 +OP4 E00545 0 +OP4 E00546 0 +OP4 E00547 0 +OP4 E00548 0 +OP4 E00549 0 +OP4 E0054A 0 +OP4 E0054B 0 +OP4 E0054C 0 +OP4 E0054D 0 +OP4 E0054E 0 +OP4 E0054F 0 +OP4 E00550 0 +OP4 E00551 0 +OP4 E00552 0 +OP4 E00553 0 +OP4 E00554 0 +OP4 E00555 0 +OP4 E00556 0 +OP4 E00557 0 +OP4 E00558 0 +OP4 E00559 0 +OP4 E0055A 0 +OP4 E0055B 0 +OP4 E0055C 0 +OP4 E0055D 0 +OP4 E0055E 0 +OP4 E0055F 0 +OP4 E00560 0 +OP4 E00561 0 +OP4 E00562 0 +OP4 E00563 0 +OP4 E00564 0 +OP4 E00565 0 +OP4 E00566 0 +OP4 E00567 0 +OP4 E00568 0 +OP4 E00569 0 +OP4 E0056A 0 +OP4 E0056B 0 +OP4 E0056C 0 +OP4 E0056D 0 +OP4 E0056E 0 +OP4 E0056F 0 +OP4 E00570 0 +OP4 E00571 0 +OP4 E00572 0 +OP4 E00573 0 +OP4 E00574 0 +OP4 E00575 0 +OP4 E00576 0 +OP4 E00577 0 +OP4 E00578 0 +OP4 E00579 0 +OP4 E0057A 0 +OP4 E0057B 0 +OP4 E0057C 0 +OP4 E0057D 0 +OP4 E0057E 0 +OP4 E0057F 0 +OP4 E00580 0 +OP4 E00581 0 +OP4 E00582 0 +OP4 E00583 0 +OP4 E00584 0 +OP4 E00585 0 +OP4 E00586 0 +OP4 E00587 0 +OP4 E00588 0 +OP4 E00589 0 +OP4 E0058A 0 +OP4 E0058B 0 +OP4 E0058C 0 +OP4 E0058D 0 +OP4 E0058E 0 +OP4 E0058F 0 +OP4 E00590 0 +OP4 E00591 0 +OP4 E00592 0 +OP4 E00593 0 +OP4 E00594 0 +OP4 E00595 0 +OP4 E00596 0 +OP4 E00597 0 +OP4 E00598 0 +OP4 E00599 0 +OP4 E0059A 0 +OP4 E0059B 0 +OP4 E0059C 0 +OP4 E0059D 0 +OP4 E0059E 0 +OP4 E0059F 0 +OP4 E005A0 0 +OP4 E005A1 0 +OP4 E005A2 0 +OP4 E005A3 0 +OP4 E005A4 0 +OP4 E005A5 0 +OP4 E005A6 0 +OP4 E005A7 0 +OP4 E005A8 0 +OP4 E005A9 0 +OP4 E005AA 0 +OP4 E005AB 0 +OP4 E005AC 0 +OP4 E005AD 0 +OP4 E005AE 0 +OP4 E005AF 0 +OP4 E005B0 0 +OP4 E005B1 0 +OP4 E005B2 0 +OP4 E005B3 0 +OP4 E005B4 0 +OP4 E005B5 0 +OP4 E005B6 0 +OP4 E005B7 0 +OP4 E005B8 0 +OP4 E005B9 0 +OP4 E005BA 0 +OP4 E005BB 0 +OP4 E005BC 0 +OP4 E005BD 0 +OP4 E005BE 0 +OP4 E005BF 0 +OP4 E005C0 0 +OP4 E005C1 0 +OP4 E005C2 0 +OP4 E005C3 0 +OP4 E005C4 0 +OP4 E005C5 0 +OP4 E005C6 0 +OP4 E005C7 0 +OP4 E005C8 0 +OP4 E005C9 0 +OP4 E005CA 0 +OP4 E005CB 0 +OP4 E005CC 0 +OP4 E005CD 0 +OP4 E005CE 0 +OP4 E005CF 0 +OP4 E005D0 0 +OP4 E005D1 0 +OP4 E005D2 0 +OP4 E005D3 0 +OP4 E005D4 0 +OP4 E005D5 0 +OP4 E005D6 0 +OP4 E005D7 0 +OP4 E005D8 0 +OP4 E005D9 0 +OP4 E005DA 0 +OP4 E005DB 0 +OP4 E005DC 0 +OP4 E005DD 0 +OP4 E005DE 0 +OP4 E005DF 0 +OP4 E005E0 0 +OP4 E005E1 0 +OP4 E005E2 0 +OP4 E005E3 0 +OP4 E005E4 0 +OP4 E005E5 0 +OP4 E005E6 0 +OP4 E005E7 0 +OP4 E005E8 0 +OP4 E005E9 0 +OP4 E005EA 0 +OP4 E005EB 0 +OP4 E005EC 0 +OP4 E005ED 0 +OP4 E005EE 0 +OP4 E005EF 0 +OP4 E005F0 0 +OP4 E005F1 0 +OP4 E005F2 0 +OP4 E005F3 0 +OP4 E005F4 0 +OP4 E005F5 0 +OP4 E005F6 0 +OP4 E005F7 0 +OP4 E005F8 0 +OP4 E005F9 0 +OP4 E005FA 0 +OP4 E005FB 0 +OP4 E005FC 0 +OP4 E005FD 0 +OP4 E005FE 0 +OP4 E005FF 0 +OP4 E00600 0 +OP4 E00601 0 +OP4 E00602 0 +OP4 E00603 0 +OP4 E00604 0 +OP4 E00605 0 +OP4 E00606 0 +OP4 E00607 0 +OP4 E00608 0 +OP4 E00609 0 +OP4 E0060A 0 +OP4 E0060B 0 +OP4 E0060C 0 +OP4 E0060D 0 +OP4 E0060E 0 +OP4 E0060F 0 +OP4 E00610 0 +OP4 E00611 0 +OP4 E00612 0 +OP4 E00613 0 +OP4 E00614 0 +OP4 E00615 0 +OP4 E00616 0 +OP4 E00617 0 +OP4 E00618 0 +OP4 E00619 0 +OP4 E0061A 0 +OP4 E0061B 0 +OP4 E0061C 0 +OP4 E0061D 0 +OP4 E0061E 0 +OP4 E0061F 0 +OP4 E00620 0 +OP4 E00621 0 +OP4 E00622 0 +OP4 E00623 0 +OP4 E00624 0 +OP4 E00625 0 +OP4 E00626 0 +OP4 E00627 0 +OP4 E00628 0 +OP4 E00629 0 +OP4 E0062A 0 +OP4 E0062B 0 +OP4 E0062C 0 +OP4 E0062D 0 +OP4 E0062E 0 +OP4 E0062F 0 +OP4 E00630 0 +OP4 E00631 0 +OP4 E00632 0 +OP4 E00633 0 +OP4 E00634 0 +OP4 E00635 0 +OP4 E00636 0 +OP4 E00637 0 +OP4 E00638 0 +OP4 E00639 0 +OP4 E0063A 0 +OP4 E0063B 0 +OP4 E0063C 0 +OP4 E0063D 0 +OP4 E0063E 0 +OP4 E0063F 0 +OP4 E00640 0 +OP4 E00641 0 +OP4 E00642 0 +OP4 E00643 0 +OP4 E00644 0 +OP4 E00645 0 +OP4 E00646 0 +OP4 E00647 0 +OP4 E00648 0 +OP4 E00649 0 +OP4 E0064A 0 +OP4 E0064B 0 +OP4 E0064C 0 +OP4 E0064D 0 +OP4 E0064E 0 +OP4 E0064F 0 +OP4 E00650 0 +OP4 E00651 0 +OP4 E00652 0 +OP4 E00653 0 +OP4 E00654 0 +OP4 E00655 0 +OP4 E00656 0 +OP4 E00657 0 +OP4 E00658 0 +OP4 E00659 0 +OP4 E0065A 0 +OP4 E0065B 0 +OP4 E0065C 0 +OP4 E0065D 0 +OP4 E0065E 0 +OP4 E0065F 0 +OP4 E00660 0 +OP4 E00661 0 +OP4 E00662 0 +OP4 E00663 0 +OP4 E00664 0 +OP4 E00665 0 +OP4 E00666 0 +OP4 E00667 0 +OP4 E00668 0 +OP4 E00669 0 +OP4 E0066A 0 +OP4 E0066B 0 +OP4 E0066C 0 +OP4 E0066D 0 +OP4 E0066E 0 +OP4 E0066F 0 +OP4 E00670 0 +OP4 E00671 0 +OP4 E00672 0 +OP4 E00673 0 +OP4 E00674 0 +OP4 E00675 0 +OP4 E00676 0 +OP4 E00677 0 +OP4 E00678 0 +OP4 E00679 0 +OP4 E0067A 0 +OP4 E0067B 0 +OP4 E0067C 0 +OP4 E0067D 0 +OP4 E0067E 0 +OP4 E0067F 0 +OP4 E00680 0 +OP4 E00681 0 +OP4 E00682 0 +OP4 E00683 0 +OP4 E00684 0 +OP4 E00685 0 +OP4 E00686 0 +OP4 E00687 0 +OP4 E00688 0 +OP4 E00689 0 +OP4 E0068A 0 +OP4 E0068B 0 +OP4 E0068C 0 +OP4 E0068D 0 +OP4 E0068E 0 +OP4 E0068F 0 +OP4 E00690 0 +OP4 E00691 0 +OP4 E00692 0 +OP4 E00693 0 +OP4 E00694 0 +OP4 E00695 0 +OP4 E00696 0 +OP4 E00697 0 +OP4 E00698 0 +OP4 E00699 0 +OP4 E0069A 0 +OP4 E0069B 0 +OP4 E0069C 0 +OP4 E0069D 0 +OP4 E0069E 0 +OP4 E0069F 0 +OP4 E006A0 0 +OP4 E006A1 0 +OP4 E006A2 0 +OP4 E006A3 0 +OP4 E006A4 0 +OP4 E006A5 0 +OP4 E006A6 0 +OP4 E006A7 0 +OP4 E006A8 0 +OP4 E006A9 0 +OP4 E006AA 0 +OP4 E006AB 0 +OP4 E006AC 0 +OP4 E006AD 0 +OP4 E006AE 0 +OP4 E006AF 0 +OP4 E006B0 0 +OP4 E006B1 0 +OP4 E006B2 0 +OP4 E006B3 0 +OP4 E006B4 0 +OP4 E006B5 0 +OP4 E006B6 0 +OP4 E006B7 0 +OP4 E006B8 0 +OP4 E006B9 0 +OP4 E006BA 0 +OP4 E006BB 0 +OP4 E006BC 0 +OP4 E006BD 0 +OP4 E006BE 0 +OP4 E006BF 0 +OP4 E006C0 0 +OP4 E006C1 0 +OP4 E006C2 0 +OP4 E006C3 0 +OP4 E006C4 0 +OP4 E006C5 0 +OP4 E006C6 0 +OP4 E006C7 0 +OP4 E006C8 0 +OP4 E006C9 0 +OP4 E006CA 0 +OP4 E006CB 0 +OP4 E006CC 0 +OP4 E006CD 0 +OP4 E006CE 0 +OP4 E006CF 0 +OP4 E006D0 0 +OP4 E006D1 0 +OP4 E006D2 0 +OP4 E006D3 0 +OP4 E006D4 0 +OP4 E006D5 0 +OP4 E006D6 0 +OP4 E006D7 0 +OP4 E006D8 0 +OP4 E006D9 0 +OP4 E006DA 0 +OP4 E006DB 0 +OP4 E006DC 0 +OP4 E006DD 0 +OP4 E006DE 0 +OP4 E006DF 0 +OP4 E006E0 0 +OP4 E006E1 0 +OP4 E006E2 0 +OP4 E006E3 0 +OP4 E006E4 0 +OP4 E006E5 0 +OP4 E006E6 0 +OP4 E006E7 0 +OP4 E006E8 0 +OP4 E006E9 0 +OP4 E006EA 0 +OP4 E006EB 0 +OP4 E006EC 0 +OP4 E006ED 0 +OP4 E006EE 0 +OP4 E006EF 0 +OP4 E006F0 0 +OP4 E006F1 0 +OP4 E006F2 0 +OP4 E006F3 0 +OP4 E006F4 0 +OP4 E006F5 0 +OP4 E006F6 0 +OP4 E006F7 0 +OP4 E006F8 0 +OP4 E006F9 0 +OP4 E006FA 0 +OP4 E006FB 0 +OP4 E006FC 0 +OP4 E006FD 0 +OP4 E006FE 0 +OP4 E006FF 0 +OP4 E00700 0 +OP4 E00701 0 +OP4 E00702 0 +OP4 E00703 0 +OP4 E00704 0 +OP4 E00705 0 +OP4 E00706 0 +OP4 E00707 0 +OP4 E00708 0 +OP4 E00709 0 +OP4 E0070A 0 +OP4 E0070B 0 +OP4 E0070C 0 +OP4 E0070D 0 +OP4 E0070E 0 +OP4 E0070F 0 +OP4 E00710 0 +OP4 E00711 0 +OP4 E00712 0 +OP4 E00713 0 +OP4 E00714 0 +OP4 E00715 0 +OP4 E00716 0 +OP4 E00717 0 +OP4 E00718 0 +OP4 E00719 0 +OP4 E0071A 0 +OP4 E0071B 0 +OP4 E0071C 0 +OP4 E0071D 0 +OP4 E0071E 0 +OP4 E0071F 0 +OP4 E00720 0 +OP4 E00721 0 +OP4 E00722 0 +OP4 E00723 0 +OP4 E00724 0 +OP4 E00725 0 +OP4 E00726 0 +OP4 E00727 0 +OP4 E00728 0 +OP4 E00729 0 +OP4 E0072A 0 +OP4 E0072B 0 +OP4 E0072C 0 +OP4 E0072D 0 +OP4 E0072E 0 +OP4 E0072F 0 +OP4 E00730 0 +OP4 E00731 0 +OP4 E00732 0 +OP4 E00733 0 +OP4 E00734 0 +OP4 E00735 0 +OP4 E00736 0 +OP4 E00737 0 +OP4 E00738 0 +OP4 E00739 0 +OP4 E0073A 0 +OP4 E0073B 0 +OP4 E0073C 0 +OP4 E0073D 0 +OP4 E0073E 0 +OP4 E0073F 0 +OP4 E00740 0 +OP4 E00741 0 +OP4 E00742 0 +OP4 E00743 0 +OP4 E00744 0 +OP4 E00745 0 +OP4 E00746 0 +OP4 E00747 0 +OP4 E00748 0 +OP4 E00749 0 +OP4 E0074A 0 +OP4 E0074B 0 +OP4 E0074C 0 +OP4 E0074D 0 +OP4 E0074E 0 +OP4 E0074F 0 +OP4 E00750 0 +OP4 E00751 0 +OP4 E00752 0 +OP4 E00753 0 +OP4 E00754 0 +OP4 E00755 0 +OP4 E00756 0 +OP4 E00757 0 +OP4 E00758 0 +OP4 E00759 0 +OP4 E0075A 0 +OP4 E0075B 0 +OP4 E0075C 0 +OP4 E0075D 0 +OP4 E0075E 0 +OP4 E0075F 0 +OP4 E00760 0 +OP4 E00761 0 +OP4 E00762 0 +OP4 E00763 0 +OP4 E00764 0 +OP4 E00765 0 +OP4 E00766 0 +OP4 E00767 0 +OP4 E00768 0 +OP4 E00769 0 +OP4 E0076A 0 +OP4 E0076B 0 +OP4 E0076C 0 +OP4 E0076D 0 +OP4 E0076E 0 +OP4 E0076F 0 +OP4 E00770 0 +OP4 E00771 0 +OP4 E00772 0 +OP4 E00773 0 +OP4 E00774 0 +OP4 E00775 0 +OP4 E00776 0 +OP4 E00777 0 +OP4 E00778 0 +OP4 E00779 0 +OP4 E0077A 0 +OP4 E0077B 0 +OP4 E0077C 0 +OP4 E0077D 0 +OP4 E0077E 0 +OP4 E0077F 0 +OP4 E00780 0 +OP4 E00781 0 +OP4 E00782 0 +OP4 E00783 0 +OP4 E00784 0 +OP4 E00785 0 +OP4 E00786 0 +OP4 E00787 0 +OP4 E00788 0 +OP4 E00789 0 +OP4 E0078A 0 +OP4 E0078B 0 +OP4 E0078C 0 +OP4 E0078D 0 +OP4 E0078E 0 +OP4 E0078F 0 +OP4 E00790 0 +OP4 E00791 0 +OP4 E00792 0 +OP4 E00793 0 +OP4 E00794 0 +OP4 E00795 0 +OP4 E00796 0 +OP4 E00797 0 +OP4 E00798 0 +OP4 E00799 0 +OP4 E0079A 0 +OP4 E0079B 0 +OP4 E0079C 0 +OP4 E0079D 0 +OP4 E0079E 0 +OP4 E0079F 0 +OP4 E007A0 0 +OP4 E007A1 0 +OP4 E007A2 0 +OP4 E007A3 0 +OP4 E007A4 0 +OP4 E007A5 0 +OP4 E007A6 0 +OP4 E007A7 0 +OP4 E007A8 0 +OP4 E007A9 0 +OP4 E007AA 0 +OP4 E007AB 0 +OP4 E007AC 0 +OP4 E007AD 0 +OP4 E007AE 0 +OP4 E007AF 0 +OP4 E007B0 0 +OP4 E007B1 0 +OP4 E007B2 0 +OP4 E007B3 0 +OP4 E007B4 0 +OP4 E007B5 0 +OP4 E007B6 0 +OP4 E007B7 0 +OP4 E007B8 0 +OP4 E007B9 0 +OP4 E007BA 0 +OP4 E007BB 0 +OP4 E007BC 0 +OP4 E007BD 0 +OP4 E007BE 0 +OP4 E007BF 0 +OP4 E007C0 0 +OP4 E007C1 0 +OP4 E007C2 0 +OP4 E007C3 0 +OP4 E007C4 0 +OP4 E007C5 0 +OP4 E007C6 0 +OP4 E007C7 0 +OP4 E007C8 0 +OP4 E007C9 0 +OP4 E007CA 0 +OP4 E007CB 0 +OP4 E007CC 0 +OP4 E007CD 0 +OP4 E007CE 0 +OP4 E007CF 0 +OP4 E007D0 0 +OP4 E007D1 0 +OP4 E007D2 0 +OP4 E007D3 0 +OP4 E007D4 0 +OP4 E007D5 0 +OP4 E007D6 0 +OP4 E007D7 0 +OP4 E007D8 0 +OP4 E007D9 0 +OP4 E007DA 0 +OP4 E007DB 0 +OP4 E007DC 0 +OP4 E007DD 0 +OP4 E007DE 0 +OP4 E007DF 0 +OP4 E007E0 0 +OP4 E007E1 0 +OP4 E007E2 0 +OP4 E007E3 0 +OP4 E007E4 0 +OP4 E007E5 0 +OP4 E007E6 0 +OP4 E007E7 0 +OP4 E007E8 0 +OP4 E007E9 0 +OP4 E007EA 0 +OP4 E007EB 0 +OP4 E007EC 0 +OP4 E007ED 0 +OP4 E007EE 0 +OP4 E007EF 0 +OP4 E007F0 0 +OP4 E007F1 0 +OP4 E007F2 0 +OP4 E007F3 0 +OP4 E007F4 0 +OP4 E007F5 0 +OP4 E007F6 0 +OP4 E007F7 0 +OP4 E007F8 0 +OP4 E007F9 0 +OP4 E007FA 0 +OP4 E007FB 0 +OP4 E007FC 0 +OP4 E007FD 0 +OP4 E007FE 0 +OP4 E007FF 0 +OP4 E00800 0 +OP4 E00801 0 +OP4 E00802 0 +OP4 E00803 0 +OP4 E00804 0 +OP4 E00805 0 +OP4 E00806 0 +OP4 E00807 0 +OP4 E00808 0 +OP4 E00809 0 +OP4 E0080A 0 +OP4 E0080B 0 +OP4 E0080C 0 +OP4 E0080D 0 +OP4 E0080E 0 +OP4 E0080F 0 +OP4 E00810 0 +OP4 E00811 0 +OP4 E00812 0 +OP4 E00813 0 +OP4 E00814 0 +OP4 E00815 0 +OP4 E00816 0 +OP4 E00817 0 +OP4 E00818 0 +OP4 E00819 0 +OP4 E0081A 0 +OP4 E0081B 0 +OP4 E0081C 0 +OP4 E0081D 0 +OP4 E0081E 0 +OP4 E0081F 0 +OP4 E00820 0 +OP4 E00821 0 +OP4 E00822 0 +OP4 E00823 0 +OP4 E00824 0 +OP4 E00825 0 +OP4 E00826 0 +OP4 E00827 0 +OP4 E00828 0 +OP4 E00829 0 +OP4 E0082A 0 +OP4 E0082B 0 +OP4 E0082C 0 +OP4 E0082D 0 +OP4 E0082E 0 +OP4 E0082F 0 +OP4 E00830 0 +OP4 E00831 0 +OP4 E00832 0 +OP4 E00833 0 +OP4 E00834 0 +OP4 E00835 0 +OP4 E00836 0 +OP4 E00837 0 +OP4 E00838 0 +OP4 E00839 0 +OP4 E0083A 0 +OP4 E0083B 0 +OP4 E0083C 0 +OP4 E0083D 0 +OP4 E0083E 0 +OP4 E0083F 0 +OP4 E00840 0 +OP4 E00841 0 +OP4 E00842 0 +OP4 E00843 0 +OP4 E00844 0 +OP4 E00845 0 +OP4 E00846 0 +OP4 E00847 0 +OP4 E00848 0 +OP4 E00849 0 +OP4 E0084A 0 +OP4 E0084B 0 +OP4 E0084C 0 +OP4 E0084D 0 +OP4 E0084E 0 +OP4 E0084F 0 +OP4 E00850 0 +OP4 E00851 0 +OP4 E00852 0 +OP4 E00853 0 +OP4 E00854 0 +OP4 E00855 0 +OP4 E00856 0 +OP4 E00857 0 +OP4 E00858 0 +OP4 E00859 0 +OP4 E0085A 0 +OP4 E0085B 0 +OP4 E0085C 0 +OP4 E0085D 0 +OP4 E0085E 0 +OP4 E0085F 0 +OP4 E00860 0 +OP4 E00861 0 +OP4 E00862 0 +OP4 E00863 0 +OP4 E00864 0 +OP4 E00865 0 +OP4 E00866 0 +OP4 E00867 0 +OP4 E00868 0 +OP4 E00869 0 +OP4 E0086A 0 +OP4 E0086B 0 +OP4 E0086C 0 +OP4 E0086D 0 +OP4 E0086E 0 +OP4 E0086F 0 +OP4 E00870 0 +OP4 E00871 0 +OP4 E00872 0 +OP4 E00873 0 +OP4 E00874 0 +OP4 E00875 0 +OP4 E00876 0 +OP4 E00877 0 +OP4 E00878 0 +OP4 E00879 0 +OP4 E0087A 0 +OP4 E0087B 0 +OP4 E0087C 0 +OP4 E0087D 0 +OP4 E0087E 0 +OP4 E0087F 0 +OP4 E00880 0 +OP4 E00881 0 +OP4 E00882 0 +OP4 E00883 0 +OP4 E00884 0 +OP4 E00885 0 +OP4 E00886 0 +OP4 E00887 0 +OP4 E00888 0 +OP4 E00889 0 +OP4 E0088A 0 +OP4 E0088B 0 +OP4 E0088C 0 +OP4 E0088D 0 +OP4 E0088E 0 +OP4 E0088F 0 +OP4 E00890 0 +OP4 E00891 0 +OP4 E00892 0 +OP4 E00893 0 +OP4 E00894 0 +OP4 E00895 0 +OP4 E00896 0 +OP4 E00897 0 +OP4 E00898 0 +OP4 E00899 0 +OP4 E0089A 0 +OP4 E0089B 0 +OP4 E0089C 0 +OP4 E0089D 0 +OP4 E0089E 0 +OP4 E0089F 0 +OP4 E008A0 0 +OP4 E008A1 0 +OP4 E008A2 0 +OP4 E008A3 0 +OP4 E008A4 0 +OP4 E008A5 0 +OP4 E008A6 0 +OP4 E008A7 0 +OP4 E008A8 0 +OP4 E008A9 0 +OP4 E008AA 0 +OP4 E008AB 0 +OP4 E008AC 0 +OP4 E008AD 0 +OP4 E008AE 0 +OP4 E008AF 0 +OP4 E008B0 0 +OP4 E008B1 0 +OP4 E008B2 0 +OP4 E008B3 0 +OP4 E008B4 0 +OP4 E008B5 0 +OP4 E008B6 0 +OP4 E008B7 0 +OP4 E008B8 0 +OP4 E008B9 0 +OP4 E008BA 0 +OP4 E008BB 0 +OP4 E008BC 0 +OP4 E008BD 0 +OP4 E008BE 0 +OP4 E008BF 0 +OP4 E008C0 0 +OP4 E008C1 0 +OP4 E008C2 0 +OP4 E008C3 0 +OP4 E008C4 0 +OP4 E008C5 0 +OP4 E008C6 0 +OP4 E008C7 0 +OP4 E008C8 0 +OP4 E008C9 0 +OP4 E008CA 0 +OP4 E008CB 0 +OP4 E008CC 0 +OP4 E008CD 0 +OP4 E008CE 0 +OP4 E008CF 0 +OP4 E008D0 0 +OP4 E008D1 0 +OP4 E008D2 0 +OP4 E008D3 0 +OP4 E008D4 0 +OP4 E008D5 0 +OP4 E008D6 0 +OP4 E008D7 0 +OP4 E008D8 0 +OP4 E008D9 0 +OP4 E008DA 0 +OP4 E008DB 0 +OP4 E008DC 0 +OP4 E008DD 0 +OP4 E008DE 0 +OP4 E008DF 0 +OP4 E008E0 0 +OP4 E008E1 0 +OP4 E008E2 0 +OP4 E008E3 0 +OP4 E008E4 0 +OP4 E008E5 0 +OP4 E008E6 0 +OP4 E008E7 0 +OP4 E008E8 0 +OP4 E008E9 0 +OP4 E008EA 0 +OP4 E008EB 0 +OP4 E008EC 0 +OP4 E008ED 0 +OP4 E008EE 0 +OP4 E008EF 0 +OP4 E008F0 0 +OP4 E008F1 0 +OP4 E008F2 0 +OP4 E008F3 0 +OP4 E008F4 0 +OP4 E008F5 0 +OP4 E008F6 0 +OP4 E008F7 0 +OP4 E008F8 0 +OP4 E008F9 0 +OP4 E008FA 0 +OP4 E008FB 0 +OP4 E008FC 0 +OP4 E008FD 0 +OP4 E008FE 0 +OP4 E008FF 0 +OP4 E00900 0 +OP4 E00901 0 +OP4 E00902 0 +OP4 E00903 0 +OP4 E00904 0 +OP4 E00905 0 +OP4 E00906 0 +OP4 E00907 0 +OP4 E00908 0 +OP4 E00909 0 +OP4 E0090A 0 +OP4 E0090B 0 +OP4 E0090C 0 +OP4 E0090D 0 +OP4 E0090E 0 +OP4 E0090F 0 +OP4 E00910 0 +OP4 E00911 0 +OP4 E00912 0 +OP4 E00913 0 +OP4 E00914 0 +OP4 E00915 0 +OP4 E00916 0 +OP4 E00917 0 +OP4 E00918 0 +OP4 E00919 0 +OP4 E0091A 0 +OP4 E0091B 0 +OP4 E0091C 0 +OP4 E0091D 0 +OP4 E0091E 0 +OP4 E0091F 0 +OP4 E00920 0 +OP4 E00921 0 +OP4 E00922 0 +OP4 E00923 0 +OP4 E00924 0 +OP4 E00925 0 +OP4 E00926 0 +OP4 E00927 0 +OP4 E00928 0 +OP4 E00929 0 +OP4 E0092A 0 +OP4 E0092B 0 +OP4 E0092C 0 +OP4 E0092D 0 +OP4 E0092E 0 +OP4 E0092F 0 +OP4 E00930 0 +OP4 E00931 0 +OP4 E00932 0 +OP4 E00933 0 +OP4 E00934 0 +OP4 E00935 0 +OP4 E00936 0 +OP4 E00937 0 +OP4 E00938 0 +OP4 E00939 0 +OP4 E0093A 0 +OP4 E0093B 0 +OP4 E0093C 0 +OP4 E0093D 0 +OP4 E0093E 0 +OP4 E0093F 0 +OP4 E00940 0 +OP4 E00941 0 +OP4 E00942 0 +OP4 E00943 0 +OP4 E00944 0 +OP4 E00945 0 +OP4 E00946 0 +OP4 E00947 0 +OP4 E00948 0 +OP4 E00949 0 +OP4 E0094A 0 +OP4 E0094B 0 +OP4 E0094C 0 +OP4 E0094D 0 +OP4 E0094E 0 +OP4 E0094F 0 +OP4 E00950 0 +OP4 E00951 0 +OP4 E00952 0 +OP4 E00953 0 +OP4 E00954 0 +OP4 E00955 0 +OP4 E00956 0 +OP4 E00957 0 +OP4 E00958 0 +OP4 E00959 0 +OP4 E0095A 0 +OP4 E0095B 0 +OP4 E0095C 0 +OP4 E0095D 0 +OP4 E0095E 0 +OP4 E0095F 0 +OP4 E00960 0 +OP4 E00961 0 +OP4 E00962 0 +OP4 E00963 0 +OP4 E00964 0 +OP4 E00965 0 +OP4 E00966 0 +OP4 E00967 0 +OP4 E00968 0 +OP4 E00969 0 +OP4 E0096A 0 +OP4 E0096B 0 +OP4 E0096C 0 +OP4 E0096D 0 +OP4 E0096E 0 +OP4 E0096F 0 +OP4 E00970 0 +OP4 E00971 0 +OP4 E00972 0 +OP4 E00973 0 +OP4 E00974 0 +OP4 E00975 0 +OP4 E00976 0 +OP4 E00977 0 +OP4 E00978 0 +OP4 E00979 0 +OP4 E0097A 0 +OP4 E0097B 0 +OP4 E0097C 0 +OP4 E0097D 0 +OP4 E0097E 0 +OP4 E0097F 0 +OP4 E00980 0 +OP4 E00981 0 +OP4 E00982 0 +OP4 E00983 0 +OP4 E00984 0 +OP4 E00985 0 +OP4 E00986 0 +OP4 E00987 0 +OP4 E00988 0 +OP4 E00989 0 +OP4 E0098A 0 +OP4 E0098B 0 +OP4 E0098C 0 +OP4 E0098D 0 +OP4 E0098E 0 +OP4 E0098F 0 +OP4 E00990 0 +OP4 E00991 0 +OP4 E00992 0 +OP4 E00993 0 +OP4 E00994 0 +OP4 E00995 0 +OP4 E00996 0 +OP4 E00997 0 +OP4 E00998 0 +OP4 E00999 0 +OP4 E0099A 0 +OP4 E0099B 0 +OP4 E0099C 0 +OP4 E0099D 0 +OP4 E0099E 0 +OP4 E0099F 0 +OP4 E009A0 0 +OP4 E009A1 0 +OP4 E009A2 0 +OP4 E009A3 0 +OP4 E009A4 0 +OP4 E009A5 0 +OP4 E009A6 0 +OP4 E009A7 0 +OP4 E009A8 0 +OP4 E009A9 0 +OP4 E009AA 0 +OP4 E009AB 0 +OP4 E009AC 0 +OP4 E009AD 0 +OP4 E009AE 0 +OP4 E009AF 0 +OP4 E009B0 0 +OP4 E009B1 0 +OP4 E009B2 0 +OP4 E009B3 0 +OP4 E009B4 0 +OP4 E009B5 0 +OP4 E009B6 0 +OP4 E009B7 0 +OP4 E009B8 0 +OP4 E009B9 0 +OP4 E009BA 0 +OP4 E009BB 0 +OP4 E009BC 0 +OP4 E009BD 0 +OP4 E009BE 0 +OP4 E009BF 0 +OP4 E009C0 0 +OP4 E009C1 0 +OP4 E009C2 0 +OP4 E009C3 0 +OP4 E009C4 0 +OP4 E009C5 0 +OP4 E009C6 0 +OP4 E009C7 0 +OP4 E009C8 0 +OP4 E009C9 0 +OP4 E009CA 0 +OP4 E009CB 0 +OP4 E009CC 0 +OP4 E009CD 0 +OP4 E009CE 0 +OP4 E009CF 0 +OP4 E009D0 0 +OP4 E009D1 0 +OP4 E009D2 0 +OP4 E009D3 0 +OP4 E009D4 0 +OP4 E009D5 0 +OP4 E009D6 0 +OP4 E009D7 0 +OP4 E009D8 0 +OP4 E009D9 0 +OP4 E009DA 0 +OP4 E009DB 0 +OP4 E009DC 0 +OP4 E009DD 0 +OP4 E009DE 0 +OP4 E009DF 0 +OP4 E009E0 0 +OP4 E009E1 0 +OP4 E009E2 0 +OP4 E009E3 0 +OP4 E009E4 0 +OP4 E009E5 0 +OP4 E009E6 0 +OP4 E009E7 0 +OP4 E009E8 0 +OP4 E009E9 0 +OP4 E009EA 0 +OP4 E009EB 0 +OP4 E009EC 0 +OP4 E009ED 0 +OP4 E009EE 0 +OP4 E009EF 0 +OP4 E009F0 0 +OP4 E009F1 0 +OP4 E009F2 0 +OP4 E009F3 0 +OP4 E009F4 0 +OP4 E009F5 0 +OP4 E009F6 0 +OP4 E009F7 0 +OP4 E009F8 0 +OP4 E009F9 0 +OP4 E009FA 0 +OP4 E009FB 0 +OP4 E009FC 0 +OP4 E009FD 0 +OP4 E009FE 0 +OP4 E009FF 0 +OP4 E00A00 0 +OP4 E00A01 0 +OP4 E00A02 0 +OP4 E00A03 0 +OP4 E00A04 0 +OP4 E00A05 0 +OP4 E00A06 0 +OP4 E00A07 0 +OP4 E00A08 0 +OP4 E00A09 0 +OP4 E00A0A 0 +OP4 E00A0B 0 +OP4 E00A0C 0 +OP4 E00A0D 0 +OP4 E00A0E 0 +OP4 E00A0F 0 +OP4 E00A10 0 +OP4 E00A11 0 +OP4 E00A12 0 +OP4 E00A13 0 +OP4 E00A14 0 +OP4 E00A15 0 +OP4 E00A16 0 +OP4 E00A17 0 +OP4 E00A18 0 +OP4 E00A19 0 +OP4 E00A1A 0 +OP4 E00A1B 0 +OP4 E00A1C 0 +OP4 E00A1D 0 +OP4 E00A1E 0 +OP4 E00A1F 0 +OP4 E00A20 0 +OP4 E00A21 0 +OP4 E00A22 0 +OP4 E00A23 0 +OP4 E00A24 0 +OP4 E00A25 0 +OP4 E00A26 0 +OP4 E00A27 0 +OP4 E00A28 0 +OP4 E00A29 0 +OP4 E00A2A 0 +OP4 E00A2B 0 +OP4 E00A2C 0 +OP4 E00A2D 0 +OP4 E00A2E 0 +OP4 E00A2F 0 +OP4 E00A30 0 +OP4 E00A31 0 +OP4 E00A32 0 +OP4 E00A33 0 +OP4 E00A34 0 +OP4 E00A35 0 +OP4 E00A36 0 +OP4 E00A37 0 +OP4 E00A38 0 +OP4 E00A39 0 +OP4 E00A3A 0 +OP4 E00A3B 0 +OP4 E00A3C 0 +OP4 E00A3D 0 +OP4 E00A3E 0 +OP4 E00A3F 0 +OP4 E00A40 0 +OP4 E00A41 0 +OP4 E00A42 0 +OP4 E00A43 0 +OP4 E00A44 0 +OP4 E00A45 0 +OP4 E00A46 0 +OP4 E00A47 0 +OP4 E00A48 0 +OP4 E00A49 0 +OP4 E00A4A 0 +OP4 E00A4B 0 +OP4 E00A4C 0 +OP4 E00A4D 0 +OP4 E00A4E 0 +OP4 E00A4F 0 +OP4 E00A50 0 +OP4 E00A51 0 +OP4 E00A52 0 +OP4 E00A53 0 +OP4 E00A54 0 +OP4 E00A55 0 +OP4 E00A56 0 +OP4 E00A57 0 +OP4 E00A58 0 +OP4 E00A59 0 +OP4 E00A5A 0 +OP4 E00A5B 0 +OP4 E00A5C 0 +OP4 E00A5D 0 +OP4 E00A5E 0 +OP4 E00A5F 0 +OP4 E00A60 0 +OP4 E00A61 0 +OP4 E00A62 0 +OP4 E00A63 0 +OP4 E00A64 0 +OP4 E00A65 0 +OP4 E00A66 0 +OP4 E00A67 0 +OP4 E00A68 0 +OP4 E00A69 0 +OP4 E00A6A 0 +OP4 E00A6B 0 +OP4 E00A6C 0 +OP4 E00A6D 0 +OP4 E00A6E 0 +OP4 E00A6F 0 +OP4 E00A70 0 +OP4 E00A71 0 +OP4 E00A72 0 +OP4 E00A73 0 +OP4 E00A74 0 +OP4 E00A75 0 +OP4 E00A76 0 +OP4 E00A77 0 +OP4 E00A78 0 +OP4 E00A79 0 +OP4 E00A7A 0 +OP4 E00A7B 0 +OP4 E00A7C 0 +OP4 E00A7D 0 +OP4 E00A7E 0 +OP4 E00A7F 0 +OP4 E00A80 0 +OP4 E00A81 0 +OP4 E00A82 0 +OP4 E00A83 0 +OP4 E00A84 0 +OP4 E00A85 0 +OP4 E00A86 0 +OP4 E00A87 0 +OP4 E00A88 0 +OP4 E00A89 0 +OP4 E00A8A 0 +OP4 E00A8B 0 +OP4 E00A8C 0 +OP4 E00A8D 0 +OP4 E00A8E 0 +OP4 E00A8F 0 +OP4 E00A90 0 +OP4 E00A91 0 +OP4 E00A92 0 +OP4 E00A93 0 +OP4 E00A94 0 +OP4 E00A95 0 +OP4 E00A96 0 +OP4 E00A97 0 +OP4 E00A98 0 +OP4 E00A99 0 +OP4 E00A9A 0 +OP4 E00A9B 0 +OP4 E00A9C 0 +OP4 E00A9D 0 +OP4 E00A9E 0 +OP4 E00A9F 0 +OP4 E00AA0 0 +OP4 E00AA1 0 +OP4 E00AA2 0 +OP4 E00AA3 0 +OP4 E00AA4 0 +OP4 E00AA5 0 +OP4 E00AA6 0 +OP4 E00AA7 0 +OP4 E00AA8 0 +OP4 E00AA9 0 +OP4 E00AAA 0 +OP4 E00AAB 0 +OP4 E00AAC 0 +OP4 E00AAD 0 +OP4 E00AAE 0 +OP4 E00AAF 0 +OP4 E00AB0 0 +OP4 E00AB1 0 +OP4 E00AB2 0 +OP4 E00AB3 0 +OP4 E00AB4 0 +OP4 E00AB5 0 +OP4 E00AB6 0 +OP4 E00AB7 0 +OP4 E00AB8 0 +OP4 E00AB9 0 +OP4 E00ABA 0 +OP4 E00ABB 0 +OP4 E00ABC 0 +OP4 E00ABD 0 +OP4 E00ABE 0 +OP4 E00ABF 0 +OP4 E00AC0 0 +OP4 E00AC1 0 +OP4 E00AC2 0 +OP4 E00AC3 0 +OP4 E00AC4 0 +OP4 E00AC5 0 +OP4 E00AC6 0 +OP4 E00AC7 0 +OP4 E00AC8 0 +OP4 E00AC9 0 +OP4 E00ACA 0 +OP4 E00ACB 0 +OP4 E00ACC 0 +OP4 E00ACD 0 +OP4 E00ACE 0 +OP4 E00ACF 0 +OP4 E00AD0 0 +OP4 E00AD1 0 +OP4 E00AD2 0 +OP4 E00AD3 0 +OP4 E00AD4 0 +OP4 E00AD5 0 +OP4 E00AD6 0 +OP4 E00AD7 0 +OP4 E00AD8 0 +OP4 E00AD9 0 +OP4 E00ADA 0 +OP4 E00ADB 0 +OP4 E00ADC 0 +OP4 E00ADD 0 +OP4 E00ADE 0 +OP4 E00ADF 0 +OP4 E00AE0 0 +OP4 E00AE1 0 +OP4 E00AE2 0 +OP4 E00AE3 0 +OP4 E00AE4 0 +OP4 E00AE5 0 +OP4 E00AE6 0 +OP4 E00AE7 0 +OP4 E00AE8 0 +OP4 E00AE9 0 +OP4 E00AEA 0 +OP4 E00AEB 0 +OP4 E00AEC 0 +OP4 E00AED 0 +OP4 E00AEE 0 +OP4 E00AEF 0 +OP4 E00AF0 0 +OP4 E00AF1 0 +OP4 E00AF2 0 +OP4 E00AF3 0 +OP4 E00AF4 0 +OP4 E00AF5 0 +OP4 E00AF6 0 +OP4 E00AF7 0 +OP4 E00AF8 0 +OP4 E00AF9 0 +OP4 E00AFA 0 +OP4 E00AFB 0 +OP4 E00AFC 0 +OP4 E00AFD 0 +OP4 E00AFE 0 +OP4 E00AFF 0 +OP4 E00B00 0 +OP4 E00B01 0 +OP4 E00B02 0 +OP4 E00B03 0 +OP4 E00B04 0 +OP4 E00B05 0 +OP4 E00B06 0 +OP4 E00B07 0 +OP4 E00B08 0 +OP4 E00B09 0 +OP4 E00B0A 0 +OP4 E00B0B 0 +OP4 E00B0C 0 +OP4 E00B0D 0 +OP4 E00B0E 0 +OP4 E00B0F 0 +OP4 E00B10 0 +OP4 E00B11 0 +OP4 E00B12 0 +OP4 E00B13 0 +OP4 E00B14 0 +OP4 E00B15 0 +OP4 E00B16 0 +OP4 E00B17 0 +OP4 E00B18 0 +OP4 E00B19 0 +OP4 E00B1A 0 +OP4 E00B1B 0 +OP4 E00B1C 0 +OP4 E00B1D 0 +OP4 E00B1E 0 +OP4 E00B1F 0 +OP4 E00B20 0 +OP4 E00B21 0 +OP4 E00B22 0 +OP4 E00B23 0 +OP4 E00B24 0 +OP4 E00B25 0 +OP4 E00B26 0 +OP4 E00B27 0 +OP4 E00B28 0 +OP4 E00B29 0 +OP4 E00B2A 0 +OP4 E00B2B 0 +OP4 E00B2C 0 +OP4 E00B2D 0 +OP4 E00B2E 0 +OP4 E00B2F 0 +OP4 E00B30 0 +OP4 E00B31 0 +OP4 E00B32 0 +OP4 E00B33 0 +OP4 E00B34 0 +OP4 E00B35 0 +OP4 E00B36 0 +OP4 E00B37 0 +OP4 E00B38 0 +OP4 E00B39 0 +OP4 E00B3A 0 +OP4 E00B3B 0 +OP4 E00B3C 0 +OP4 E00B3D 0 +OP4 E00B3E 0 +OP4 E00B3F 0 +OP4 E00B40 0 +OP4 E00B41 0 +OP4 E00B42 0 +OP4 E00B43 0 +OP4 E00B44 0 +OP4 E00B45 0 +OP4 E00B46 0 +OP4 E00B47 0 +OP4 E00B48 0 +OP4 E00B49 0 +OP4 E00B4A 0 +OP4 E00B4B 0 +OP4 E00B4C 0 +OP4 E00B4D 0 +OP4 E00B4E 0 +OP4 E00B4F 0 +OP4 E00B50 0 +OP4 E00B51 0 +OP4 E00B52 0 +OP4 E00B53 0 +OP4 E00B54 0 +OP4 E00B55 0 +OP4 E00B56 0 +OP4 E00B57 0 +OP4 E00B58 0 +OP4 E00B59 0 +OP4 E00B5A 0 +OP4 E00B5B 0 +OP4 E00B5C 0 +OP4 E00B5D 0 +OP4 E00B5E 0 +OP4 E00B5F 0 +OP4 E00B60 0 +OP4 E00B61 0 +OP4 E00B62 0 +OP4 E00B63 0 +OP4 E00B64 0 +OP4 E00B65 0 +OP4 E00B66 0 +OP4 E00B67 0 +OP4 E00B68 0 +OP4 E00B69 0 +OP4 E00B6A 0 +OP4 E00B6B 0 +OP4 E00B6C 0 +OP4 E00B6D 0 +OP4 E00B6E 0 +OP4 E00B6F 0 +OP4 E00B70 0 +OP4 E00B71 0 +OP4 E00B72 0 +OP4 E00B73 0 +OP4 E00B74 0 +OP4 E00B75 0 +OP4 E00B76 0 +OP4 E00B77 0 +OP4 E00B78 0 +OP4 E00B79 0 +OP4 E00B7A 0 +OP4 E00B7B 0 +OP4 E00B7C 0 +OP4 E00B7D 0 +OP4 E00B7E 0 +OP4 E00B7F 0 +OP4 E00B80 0 +OP4 E00B81 0 +OP4 E00B82 0 +OP4 E00B83 0 +OP4 E00B84 0 +OP4 E00B85 0 +OP4 E00B86 0 +OP4 E00B87 0 +OP4 E00B88 0 +OP4 E00B89 0 +OP4 E00B8A 0 +OP4 E00B8B 0 +OP4 E00B8C 0 +OP4 E00B8D 0 +OP4 E00B8E 0 +OP4 E00B8F 0 +OP4 E00B90 0 +OP4 E00B91 0 +OP4 E00B92 0 +OP4 E00B93 0 +OP4 E00B94 0 +OP4 E00B95 0 +OP4 E00B96 0 +OP4 E00B97 0 +OP4 E00B98 0 +OP4 E00B99 0 +OP4 E00B9A 0 +OP4 E00B9B 0 +OP4 E00B9C 0 +OP4 E00B9D 0 +OP4 E00B9E 0 +OP4 E00B9F 0 +OP4 E00BA0 0 +OP4 E00BA1 0 +OP4 E00BA2 0 +OP4 E00BA3 0 +OP4 E00BA4 0 +OP4 E00BA5 0 +OP4 E00BA6 0 +OP4 E00BA7 0 +OP4 E00BA8 0 +OP4 E00BA9 0 +OP4 E00BAA 0 +OP4 E00BAB 0 +OP4 E00BAC 0 +OP4 E00BAD 0 +OP4 E00BAE 0 +OP4 E00BAF 0 +OP4 E00BB0 0 +OP4 E00BB1 0 +OP4 E00BB2 0 +OP4 E00BB3 0 +OP4 E00BB4 0 +OP4 E00BB5 0 +OP4 E00BB6 0 +OP4 E00BB7 0 +OP4 E00BB8 0 +OP4 E00BB9 0 +OP4 E00BBA 0 +OP4 E00BBB 0 +OP4 E00BBC 0 +OP4 E00BBD 0 +OP4 E00BBE 0 +OP4 E00BBF 0 +OP4 E00BC0 0 +OP4 E00BC1 0 +OP4 E00BC2 0 +OP4 E00BC3 0 +OP4 E00BC4 0 +OP4 E00BC5 0 +OP4 E00BC6 0 +OP4 E00BC7 0 +OP4 E00BC8 0 +OP4 E00BC9 0 +OP4 E00BCA 0 +OP4 E00BCB 0 +OP4 E00BCC 0 +OP4 E00BCD 0 +OP4 E00BCE 0 +OP4 E00BCF 0 +OP4 E00BD0 0 +OP4 E00BD1 0 +OP4 E00BD2 0 +OP4 E00BD3 0 +OP4 E00BD4 0 +OP4 E00BD5 0 +OP4 E00BD6 0 +OP4 E00BD7 0 +OP4 E00BD8 0 +OP4 E00BD9 0 +OP4 E00BDA 0 +OP4 E00BDB 0 +OP4 E00BDC 0 +OP4 E00BDD 0 +OP4 E00BDE 0 +OP4 E00BDF 0 +OP4 E00BE0 0 +OP4 E00BE1 0 +OP4 E00BE2 0 +OP4 E00BE3 0 +OP4 E00BE4 0 +OP4 E00BE5 0 +OP4 E00BE6 0 +OP4 E00BE7 0 +OP4 E00BE8 0 +OP4 E00BE9 0 +OP4 E00BEA 0 +OP4 E00BEB 0 +OP4 E00BEC 0 +OP4 E00BED 0 +OP4 E00BEE 0 +OP4 E00BEF 0 +OP4 E00BF0 0 +OP4 E00BF1 0 +OP4 E00BF2 0 +OP4 E00BF3 0 +OP4 E00BF4 0 +OP4 E00BF5 0 +OP4 E00BF6 0 +OP4 E00BF7 0 +OP4 E00BF8 0 +OP4 E00BF9 0 +OP4 E00BFA 0 +OP4 E00BFB 0 +OP4 E00BFC 0 +OP4 E00BFD 0 +OP4 E00BFE 0 +OP4 E00BFF 0 +OP4 E00C00 0 +OP4 E00C01 0 +OP4 E00C02 0 +OP4 E00C03 0 +OP4 E00C04 0 +OP4 E00C05 0 +OP4 E00C06 0 +OP4 E00C07 0 +OP4 E00C08 0 +OP4 E00C09 0 +OP4 E00C0A 0 +OP4 E00C0B 0 +OP4 E00C0C 0 +OP4 E00C0D 0 +OP4 E00C0E 0 +OP4 E00C0F 0 +OP4 E00C10 0 +OP4 E00C11 0 +OP4 E00C12 0 +OP4 E00C13 0 +OP4 E00C14 0 +OP4 E00C15 0 +OP4 E00C16 0 +OP4 E00C17 0 +OP4 E00C18 0 +OP4 E00C19 0 +OP4 E00C1A 0 +OP4 E00C1B 0 +OP4 E00C1C 0 +OP4 E00C1D 0 +OP4 E00C1E 0 +OP4 E00C1F 0 +OP4 E00C20 0 +OP4 E00C21 0 +OP4 E00C22 0 +OP4 E00C23 0 +OP4 E00C24 0 +OP4 E00C25 0 +OP4 E00C26 0 +OP4 E00C27 0 +OP4 E00C28 0 +OP4 E00C29 0 +OP4 E00C2A 0 +OP4 E00C2B 0 +OP4 E00C2C 0 +OP4 E00C2D 0 +OP4 E00C2E 0 +OP4 E00C2F 0 +OP4 E00C30 0 +OP4 E00C31 0 +OP4 E00C32 0 +OP4 E00C33 0 +OP4 E00C34 0 +OP4 E00C35 0 +OP4 E00C36 0 +OP4 E00C37 0 +OP4 E00C38 0 +OP4 E00C39 0 +OP4 E00C3A 0 +OP4 E00C3B 0 +OP4 E00C3C 0 +OP4 E00C3D 0 +OP4 E00C3E 0 +OP4 E00C3F 0 +OP4 E00C40 0 +OP4 E00C41 0 +OP4 E00C42 0 +OP4 E00C43 0 +OP4 E00C44 0 +OP4 E00C45 0 +OP4 E00C46 0 +OP4 E00C47 0 +OP4 E00C48 0 +OP4 E00C49 0 +OP4 E00C4A 0 +OP4 E00C4B 0 +OP4 E00C4C 0 +OP4 E00C4D 0 +OP4 E00C4E 0 +OP4 E00C4F 0 +OP4 E00C50 0 +OP4 E00C51 0 +OP4 E00C52 0 +OP4 E00C53 0 +OP4 E00C54 0 +OP4 E00C55 0 +OP4 E00C56 0 +OP4 E00C57 0 +OP4 E00C58 0 +OP4 E00C59 0 +OP4 E00C5A 0 +OP4 E00C5B 0 +OP4 E00C5C 0 +OP4 E00C5D 0 +OP4 E00C5E 0 +OP4 E00C5F 0 +OP4 E00C60 0 +OP4 E00C61 0 +OP4 E00C62 0 +OP4 E00C63 0 +OP4 E00C64 0 +OP4 E00C65 0 +OP4 E00C66 0 +OP4 E00C67 0 +OP4 E00C68 0 +OP4 E00C69 0 +OP4 E00C6A 0 +OP4 E00C6B 0 +OP4 E00C6C 0 +OP4 E00C6D 0 +OP4 E00C6E 0 +OP4 E00C6F 0 +OP4 E00C70 0 +OP4 E00C71 0 +OP4 E00C72 0 +OP4 E00C73 0 +OP4 E00C74 0 +OP4 E00C75 0 +OP4 E00C76 0 +OP4 E00C77 0 +OP4 E00C78 0 +OP4 E00C79 0 +OP4 E00C7A 0 +OP4 E00C7B 0 +OP4 E00C7C 0 +OP4 E00C7D 0 +OP4 E00C7E 0 +OP4 E00C7F 0 +OP4 E00C80 0 +OP4 E00C81 0 +OP4 E00C82 0 +OP4 E00C83 0 +OP4 E00C84 0 +OP4 E00C85 0 +OP4 E00C86 0 +OP4 E00C87 0 +OP4 E00C88 0 +OP4 E00C89 0 +OP4 E00C8A 0 +OP4 E00C8B 0 +OP4 E00C8C 0 +OP4 E00C8D 0 +OP4 E00C8E 0 +OP4 E00C8F 0 +OP4 E00C90 0 +OP4 E00C91 0 +OP4 E00C92 0 +OP4 E00C93 0 +OP4 E00C94 0 +OP4 E00C95 0 +OP4 E00C96 0 +OP4 E00C97 0 +OP4 E00C98 0 +OP4 E00C99 0 +OP4 E00C9A 0 +OP4 E00C9B 0 +OP4 E00C9C 0 +OP4 E00C9D 0 +OP4 E00C9E 0 +OP4 E00C9F 0 +OP4 E00CA0 0 +OP4 E00CA1 0 +OP4 E00CA2 0 +OP4 E00CA3 0 +OP4 E00CA4 0 +OP4 E00CA5 0 +OP4 E00CA6 0 +OP4 E00CA7 0 +OP4 E00CA8 0 +OP4 E00CA9 0 +OP4 E00CAA 0 +OP4 E00CAB 0 +OP4 E00CAC 0 +OP4 E00CAD 0 +OP4 E00CAE 0 +OP4 E00CAF 0 +OP4 E00CB0 0 +OP4 E00CB1 0 +OP4 E00CB2 0 +OP4 E00CB3 0 +OP4 E00CB4 0 +OP4 E00CB5 0 +OP4 E00CB6 0 +OP4 E00CB7 0 +OP4 E00CB8 0 +OP4 E00CB9 0 +OP4 E00CBA 0 +OP4 E00CBB 0 +OP4 E00CBC 0 +OP4 E00CBD 0 +OP4 E00CBE 0 +OP4 E00CBF 0 +OP4 E00CC0 0 +OP4 E00CC1 0 +OP4 E00CC2 0 +OP4 E00CC3 0 +OP4 E00CC4 0 +OP4 E00CC5 0 +OP4 E00CC6 0 +OP4 E00CC7 0 +OP4 E00CC8 0 +OP4 E00CC9 0 +OP4 E00CCA 0 +OP4 E00CCB 0 +OP4 E00CCC 0 +OP4 E00CCD 0 +OP4 E00CCE 0 +OP4 E00CCF 0 +OP4 E00CD0 0 +OP4 E00CD1 0 +OP4 E00CD2 0 +OP4 E00CD3 0 +OP4 E00CD4 0 +OP4 E00CD5 0 +OP4 E00CD6 0 +OP4 E00CD7 0 +OP4 E00CD8 0 +OP4 E00CD9 0 +OP4 E00CDA 0 +OP4 E00CDB 0 +OP4 E00CDC 0 +OP4 E00CDD 0 +OP4 E00CDE 0 +OP4 E00CDF 0 +OP4 E00CE0 0 +OP4 E00CE1 0 +OP4 E00CE2 0 +OP4 E00CE3 0 +OP4 E00CE4 0 +OP4 E00CE5 0 +OP4 E00CE6 0 +OP4 E00CE7 0 +OP4 E00CE8 0 +OP4 E00CE9 0 +OP4 E00CEA 0 +OP4 E00CEB 0 +OP4 E00CEC 0 +OP4 E00CED 0 +OP4 E00CEE 0 +OP4 E00CEF 0 +OP4 E00CF0 0 +OP4 E00CF1 0 +OP4 E00CF2 0 +OP4 E00CF3 0 +OP4 E00CF4 0 +OP4 E00CF5 0 +OP4 E00CF6 0 +OP4 E00CF7 0 +OP4 E00CF8 0 +OP4 E00CF9 0 +OP4 E00CFA 0 +OP4 E00CFB 0 +OP4 E00CFC 0 +OP4 E00CFD 0 +OP4 E00CFE 0 +OP4 E00CFF 0 +OP4 E00D00 0 +OP4 E00D01 0 +OP4 E00D02 0 +OP4 E00D03 0 +OP4 E00D04 0 +OP4 E00D05 0 +OP4 E00D06 0 +OP4 E00D07 0 +OP4 E00D08 0 +OP4 E00D09 0 +OP4 E00D0A 0 +OP4 E00D0B 0 +OP4 E00D0C 0 +OP4 E00D0D 0 +OP4 E00D0E 0 +OP4 E00D0F 0 +OP4 E00D10 0 +OP4 E00D11 0 +OP4 E00D12 0 +OP4 E00D13 0 +OP4 E00D14 0 +OP4 E00D15 0 +OP4 E00D16 0 +OP4 E00D17 0 +OP4 E00D18 0 +OP4 E00D19 0 +OP4 E00D1A 0 +OP4 E00D1B 0 +OP4 E00D1C 0 +OP4 E00D1D 0 +OP4 E00D1E 0 +OP4 E00D1F 0 +OP4 E00D20 0 +OP4 E00D21 0 +OP4 E00D22 0 +OP4 E00D23 0 +OP4 E00D24 0 +OP4 E00D25 0 +OP4 E00D26 0 +OP4 E00D27 0 +OP4 E00D28 0 +OP4 E00D29 0 +OP4 E00D2A 0 +OP4 E00D2B 0 +OP4 E00D2C 0 +OP4 E00D2D 0 +OP4 E00D2E 0 +OP4 E00D2F 0 +OP4 E00D30 0 +OP4 E00D31 0 +OP4 E00D32 0 +OP4 E00D33 0 +OP4 E00D34 0 +OP4 E00D35 0 +OP4 E00D36 0 +OP4 E00D37 0 +OP4 E00D38 0 +OP4 E00D39 0 +OP4 E00D3A 0 +OP4 E00D3B 0 +OP4 E00D3C 0 +OP4 E00D3D 0 +OP4 E00D3E 0 +OP4 E00D3F 0 +OP4 E00D40 0 +OP4 E00D41 0 +OP4 E00D42 0 +OP4 E00D43 0 +OP4 E00D44 0 +OP4 E00D45 0 +OP4 E00D46 0 +OP4 E00D47 0 +OP4 E00D48 0 +OP4 E00D49 0 +OP4 E00D4A 0 +OP4 E00D4B 0 +OP4 E00D4C 0 +OP4 E00D4D 0 +OP4 E00D4E 0 +OP4 E00D4F 0 +OP4 E00D50 0 +OP4 E00D51 0 +OP4 E00D52 0 +OP4 E00D53 0 +OP4 E00D54 0 +OP4 E00D55 0 +OP4 E00D56 0 +OP4 E00D57 0 +OP4 E00D58 0 +OP4 E00D59 0 +OP4 E00D5A 0 +OP4 E00D5B 0 +OP4 E00D5C 0 +OP4 E00D5D 0 +OP4 E00D5E 0 +OP4 E00D5F 0 +OP4 E00D60 0 +OP4 E00D61 0 +OP4 E00D62 0 +OP4 E00D63 0 +OP4 E00D64 0 +OP4 E00D65 0 +OP4 E00D66 0 +OP4 E00D67 0 +OP4 E00D68 0 +OP4 E00D69 0 +OP4 E00D6A 0 +OP4 E00D6B 0 +OP4 E00D6C 0 +OP4 E00D6D 0 +OP4 E00D6E 0 +OP4 E00D6F 0 +OP4 E00D70 0 +OP4 E00D71 0 +OP4 E00D72 0 +OP4 E00D73 0 +OP4 E00D74 0 +OP4 E00D75 0 +OP4 E00D76 0 +OP4 E00D77 0 +OP4 E00D78 0 +OP4 E00D79 0 +OP4 E00D7A 0 +OP4 E00D7B 0 +OP4 E00D7C 0 +OP4 E00D7D 0 +OP4 E00D7E 0 +OP4 E00D7F 0 +OP4 E00D80 0 +OP4 E00D81 0 +OP4 E00D82 0 +OP4 E00D83 0 +OP4 E00D84 0 +OP4 E00D85 0 +OP4 E00D86 0 +OP4 E00D87 0 +OP4 E00D88 0 +OP4 E00D89 0 +OP4 E00D8A 0 +OP4 E00D8B 0 +OP4 E00D8C 0 +OP4 E00D8D 0 +OP4 E00D8E 0 +OP4 E00D8F 0 +OP4 E00D90 0 +OP4 E00D91 0 +OP4 E00D92 0 +OP4 E00D93 0 +OP4 E00D94 0 +OP4 E00D95 0 +OP4 E00D96 0 +OP4 E00D97 0 +OP4 E00D98 0 +OP4 E00D99 0 +OP4 E00D9A 0 +OP4 E00D9B 0 +OP4 E00D9C 0 +OP4 E00D9D 0 +OP4 E00D9E 0 +OP4 E00D9F 0 +OP4 E00DA0 0 +OP4 E00DA1 0 +OP4 E00DA2 0 +OP4 E00DA3 0 +OP4 E00DA4 0 +OP4 E00DA5 0 +OP4 E00DA6 0 +OP4 E00DA7 0 +OP4 E00DA8 0 +OP4 E00DA9 0 +OP4 E00DAA 0 +OP4 E00DAB 0 +OP4 E00DAC 0 +OP4 E00DAD 0 +OP4 E00DAE 0 +OP4 E00DAF 0 +OP4 E00DB0 0 +OP4 E00DB1 0 +OP4 E00DB2 0 +OP4 E00DB3 0 +OP4 E00DB4 0 +OP4 E00DB5 0 +OP4 E00DB6 0 +OP4 E00DB7 0 +OP4 E00DB8 0 +OP4 E00DB9 0 +OP4 E00DBA 0 +OP4 E00DBB 0 +OP4 E00DBC 0 +OP4 E00DBD 0 +OP4 E00DBE 0 +OP4 E00DBF 0 +OP4 E00DC0 0 +OP4 E00DC1 0 +OP4 E00DC2 0 +OP4 E00DC3 0 +OP4 E00DC4 0 +OP4 E00DC5 0 +OP4 E00DC6 0 +OP4 E00DC7 0 +OP4 E00DC8 0 +OP4 E00DC9 0 +OP4 E00DCA 0 +OP4 E00DCB 0 +OP4 E00DCC 0 +OP4 E00DCD 0 +OP4 E00DCE 0 +OP4 E00DCF 0 +OP4 E00DD0 0 +OP4 E00DD1 0 +OP4 E00DD2 0 +OP4 E00DD3 0 +OP4 E00DD4 0 +OP4 E00DD5 0 +OP4 E00DD6 0 +OP4 E00DD7 0 +OP4 E00DD8 0 +OP4 E00DD9 0 +OP4 E00DDA 0 +OP4 E00DDB 0 +OP4 E00DDC 0 +OP4 E00DDD 0 +OP4 E00DDE 0 +OP4 E00DDF 0 +OP4 E00DE0 0 +OP4 E00DE1 0 +OP4 E00DE2 0 +OP4 E00DE3 0 +OP4 E00DE4 0 +OP4 E00DE5 0 +OP4 E00DE6 0 +OP4 E00DE7 0 +OP4 E00DE8 0 +OP4 E00DE9 0 +OP4 E00DEA 0 +OP4 E00DEB 0 +OP4 E00DEC 0 +OP4 E00DED 0 +OP4 E00DEE 0 +OP4 E00DEF 0 +OP4 E00DF0 0 +OP4 E00DF1 0 +OP4 E00DF2 0 +OP4 E00DF3 0 +OP4 E00DF4 0 +OP4 E00DF5 0 +OP4 E00DF6 0 +OP4 E00DF7 0 +OP4 E00DF8 0 +OP4 E00DF9 0 +OP4 E00DFA 0 +OP4 E00DFB 0 +OP4 E00DFC 0 +OP4 E00DFD 0 +OP4 E00DFE 0 +OP4 E00DFF 0 +OP4 E00E00 0 +OP4 E00E01 0 +OP4 E00E02 0 +OP4 E00E03 0 +OP4 E00E04 0 +OP4 E00E05 0 +OP4 E00E06 0 +OP4 E00E07 0 +OP4 E00E08 0 +OP4 E00E09 0 +OP4 E00E0A 0 +OP4 E00E0B 0 +OP4 E00E0C 0 +OP4 E00E0D 0 +OP4 E00E0E 0 +OP4 E00E0F 0 +OP4 E00E10 0 +OP4 E00E11 0 +OP4 E00E12 0 +OP4 E00E13 0 +OP4 E00E14 0 +OP4 E00E15 0 +OP4 E00E16 0 +OP4 E00E17 0 +OP4 E00E18 0 +OP4 E00E19 0 +OP4 E00E1A 0 +OP4 E00E1B 0 +OP4 E00E1C 0 +OP4 E00E1D 0 +OP4 E00E1E 0 +OP4 E00E1F 0 +OP4 E00E20 0 +OP4 E00E21 0 +OP4 E00E22 0 +OP4 E00E23 0 +OP4 E00E24 0 +OP4 E00E25 0 +OP4 E00E26 0 +OP4 E00E27 0 +OP4 E00E28 0 +OP4 E00E29 0 +OP4 E00E2A 0 +OP4 E00E2B 0 +OP4 E00E2C 0 +OP4 E00E2D 0 +OP4 E00E2E 0 +OP4 E00E2F 0 +OP4 E00E30 0 +OP4 E00E31 0 +OP4 E00E32 0 +OP4 E00E33 0 +OP4 E00E34 0 +OP4 E00E35 0 +OP4 E00E36 0 +OP4 E00E37 0 +OP4 E00E38 0 +OP4 E00E39 0 +OP4 E00E3A 0 +OP4 E00E3B 0 +OP4 E00E3C 0 +OP4 E00E3D 0 +OP4 E00E3E 0 +OP4 E00E3F 0 +OP4 E00E40 0 +OP4 E00E41 0 +OP4 E00E42 0 +OP4 E00E43 0 +OP4 E00E44 0 +OP4 E00E45 0 +OP4 E00E46 0 +OP4 E00E47 0 +OP4 E00E48 0 +OP4 E00E49 0 +OP4 E00E4A 0 +OP4 E00E4B 0 +OP4 E00E4C 0 +OP4 E00E4D 0 +OP4 E00E4E 0 +OP4 E00E4F 0 +OP4 E00E50 0 +OP4 E00E51 0 +OP4 E00E52 0 +OP4 E00E53 0 +OP4 E00E54 0 +OP4 E00E55 0 +OP4 E00E56 0 +OP4 E00E57 0 +OP4 E00E58 0 +OP4 E00E59 0 +OP4 E00E5A 0 +OP4 E00E5B 0 +OP4 E00E5C 0 +OP4 E00E5D 0 +OP4 E00E5E 0 +OP4 E00E5F 0 +OP4 E00E60 0 +OP4 E00E61 0 +OP4 E00E62 0 +OP4 E00E63 0 +OP4 E00E64 0 +OP4 E00E65 0 +OP4 E00E66 0 +OP4 E00E67 0 +OP4 E00E68 0 +OP4 E00E69 0 +OP4 E00E6A 0 +OP4 E00E6B 0 +OP4 E00E6C 0 +OP4 E00E6D 0 +OP4 E00E6E 0 +OP4 E00E6F 0 +OP4 E00E70 0 +OP4 E00E71 0 +OP4 E00E72 0 +OP4 E00E73 0 +OP4 E00E74 0 +OP4 E00E75 0 +OP4 E00E76 0 +OP4 E00E77 0 +OP4 E00E78 0 +OP4 E00E79 0 +OP4 E00E7A 0 +OP4 E00E7B 0 +OP4 E00E7C 0 +OP4 E00E7D 0 +OP4 E00E7E 0 +OP4 E00E7F 0 +OP4 E00E80 0 +OP4 E00E81 0 +OP4 E00E82 0 +OP4 E00E83 0 +OP4 E00E84 0 +OP4 E00E85 0 +OP4 E00E86 0 +OP4 E00E87 0 +OP4 E00E88 0 +OP4 E00E89 0 +OP4 E00E8A 0 +OP4 E00E8B 0 +OP4 E00E8C 0 +OP4 E00E8D 0 +OP4 E00E8E 0 +OP4 E00E8F 0 +OP4 E00E90 0 +OP4 E00E91 0 +OP4 E00E92 0 +OP4 E00E93 0 +OP4 E00E94 0 +OP4 E00E95 0 +OP4 E00E96 0 +OP4 E00E97 0 +OP4 E00E98 0 +OP4 E00E99 0 +OP4 E00E9A 0 +OP4 E00E9B 0 +OP4 E00E9C 0 +OP4 E00E9D 0 +OP4 E00E9E 0 +OP4 E00E9F 0 +OP4 E00EA0 0 +OP4 E00EA1 0 +OP4 E00EA2 0 +OP4 E00EA3 0 +OP4 E00EA4 0 +OP4 E00EA5 0 +OP4 E00EA6 0 +OP4 E00EA7 0 +OP4 E00EA8 0 +OP4 E00EA9 0 +OP4 E00EAA 0 +OP4 E00EAB 0 +OP4 E00EAC 0 +OP4 E00EAD 0 +OP4 E00EAE 0 +OP4 E00EAF 0 +OP4 E00EB0 0 +OP4 E00EB1 0 +OP4 E00EB2 0 +OP4 E00EB3 0 +OP4 E00EB4 0 +OP4 E00EB5 0 +OP4 E00EB6 0 +OP4 E00EB7 0 +OP4 E00EB8 0 +OP4 E00EB9 0 +OP4 E00EBA 0 +OP4 E00EBB 0 +OP4 E00EBC 0 +OP4 E00EBD 0 +OP4 E00EBE 0 +OP4 E00EBF 0 +OP4 E00EC0 0 +OP4 E00EC1 0 +OP4 E00EC2 0 +OP4 E00EC3 0 +OP4 E00EC4 0 +OP4 E00EC5 0 +OP4 E00EC6 0 +OP4 E00EC7 0 +OP4 E00EC8 0 +OP4 E00EC9 0 +OP4 E00ECA 0 +OP4 E00ECB 0 +OP4 E00ECC 0 +OP4 E00ECD 0 +OP4 E00ECE 0 +OP4 E00ECF 0 +OP4 E00ED0 0 +OP4 E00ED1 0 +OP4 E00ED2 0 +OP4 E00ED3 0 +OP4 E00ED4 0 +OP4 E00ED5 0 +OP4 E00ED6 0 +OP4 E00ED7 0 +OP4 E00ED8 0 +OP4 E00ED9 0 +OP4 E00EDA 0 +OP4 E00EDB 0 +OP4 E00EDC 0 +OP4 E00EDD 0 +OP4 E00EDE 0 +OP4 E00EDF 0 +OP4 E00EE0 0 +OP4 E00EE1 0 +OP4 E00EE2 0 +OP4 E00EE3 0 +OP4 E00EE4 0 +OP4 E00EE5 0 +OP4 E00EE6 0 +OP4 E00EE7 0 +OP4 E00EE8 0 +OP4 E00EE9 0 +OP4 E00EEA 0 +OP4 E00EEB 0 +OP4 E00EEC 0 +OP4 E00EED 0 +OP4 E00EEE 0 +OP4 E00EEF 0 +OP4 E00EF0 0 +OP4 E00EF1 0 +OP4 E00EF2 0 +OP4 E00EF3 0 +OP4 E00EF4 0 +OP4 E00EF5 0 +OP4 E00EF6 0 +OP4 E00EF7 0 +OP4 E00EF8 0 +OP4 E00EF9 0 +OP4 E00EFA 0 +OP4 E00EFB 0 +OP4 E00EFC 0 +OP4 E00EFD 0 +OP4 E00EFE 0 +OP4 E00EFF 0 +OP4 E00F00 0 +OP4 E00F01 0 +OP4 E00F02 0 +OP4 E00F03 0 +OP4 E00F04 0 +OP4 E00F05 0 +OP4 E00F06 0 +OP4 E00F07 0 +OP4 E00F08 0 +OP4 E00F09 0 +OP4 E00F0A 0 +OP4 E00F0B 0 +OP4 E00F0C 0 +OP4 E00F0D 0 +OP4 E00F0E 0 +OP4 E00F0F 0 +OP4 E00F10 0 +OP4 E00F11 0 +OP4 E00F12 0 +OP4 E00F13 0 +OP4 E00F14 0 +OP4 E00F15 0 +OP4 E00F16 0 +OP4 E00F17 0 +OP4 E00F18 0 +OP4 E00F19 0 +OP4 E00F1A 0 +OP4 E00F1B 0 +OP4 E00F1C 0 +OP4 E00F1D 0 +OP4 E00F1E 0 +OP4 E00F1F 0 +OP4 E00F20 0 +OP4 E00F21 0 +OP4 E00F22 0 +OP4 E00F23 0 +OP4 E00F24 0 +OP4 E00F25 0 +OP4 E00F26 0 +OP4 E00F27 0 +OP4 E00F28 0 +OP4 E00F29 0 +OP4 E00F2A 0 +OP4 E00F2B 0 +OP4 E00F2C 0 +OP4 E00F2D 0 +OP4 E00F2E 0 +OP4 E00F2F 0 +OP4 E00F30 0 diff --git a/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum3_itrace_irisc9.cfg.ext b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum3_itrace_irisc9.cfg.ext new file mode 100644 index 000000000000..8ff37d42e8e8 --- /dev/null +++ b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum3_itrace_irisc9.cfg.ext @@ -0,0 +1,3890 @@ +OP1 Spectrum3 +OP4 ITRACE0 0 +OP4 ITRACE1 0 +OP4 ITRACE2 0 +OP4 ITRACE3 0 +OP4 ITRACE4 0 +OP4 ITRACE5 0 +OP4 ITRACE6 0 +OP4 ITRACE7 0 +OP4 ITRACE8 0 +OP4 ITRACE9 1 +OP4 Main_PhyUC 0 +OP4 TILE0_ITRACE0 0 +OP4 TILE0_ITRACE1 0 +OP4 TILE0_ITRACE2 0 +OP4 TILE0_ITRACE3 0 +OP4 TILE0_ITRACE4 0 +OP4 TILE0_PhyUC 0 +OP4 TILE1_ITRACE0 0 +OP4 TILE1_ITRACE1 0 +OP4 TILE1_ITRACE2 0 +OP4 TILE1_ITRACE3 0 +OP4 TILE1_ITRACE4 0 +OP4 TILE1_PhyUC 0 +OP4 TILE2_ITRACE0 0 +OP4 TILE2_ITRACE1 0 +OP4 TILE2_ITRACE2 0 +OP4 TILE2_ITRACE3 0 +OP4 TILE2_ITRACE4 0 +OP4 TILE2_PhyUC 0 +OP4 TILE3_ITRACE0 0 +OP4 TILE3_ITRACE1 0 +OP4 TILE3_ITRACE2 0 +OP4 TILE3_ITRACE3 0 +OP4 TILE3_ITRACE4 0 +OP4 TILE3_PhyUC 0 +OP4 TILE4_ITRACE0 0 +OP4 TILE4_ITRACE1 0 +OP4 TILE4_ITRACE2 0 +OP4 TILE4_ITRACE3 0 +OP4 TILE4_ITRACE4 0 +OP4 TILE4_PhyUC 0 +OP4 TILE5_ITRACE0 0 +OP4 TILE5_ITRACE1 0 +OP4 TILE5_ITRACE2 0 +OP4 TILE5_ITRACE3 0 +OP4 TILE5_ITRACE4 0 +OP4 TILE5_PhyUC 0 +OP4 TILE6_ITRACE0 0 +OP4 TILE6_ITRACE1 0 +OP4 TILE6_ITRACE2 0 +OP4 TILE6_ITRACE3 0 +OP4 TILE6_ITRACE4 0 +OP4 TILE6_PhyUC 0 +OP4 TILE7_ITRACE0 0 +OP4 TILE7_ITRACE1 0 +OP4 TILE7_ITRACE2 0 +OP4 TILE7_ITRACE3 0 +OP4 TILE7_ITRACE4 0 +OP4 TILE7_PhyUC 0 +OP4 E0003B 0 +OP4 E0003C 0 +OP4 E0003D 0 +OP4 E0003E 0 +OP4 E0003F 0 +OP4 E00040 0 +OP4 E00041 0 +OP4 E00042 0 +OP4 E00043 0 +OP4 E00044 0 +OP4 E00045 0 +OP4 E00046 0 +OP4 E00047 0 +OP4 E00048 0 +OP4 E00049 0 +OP4 E0004A 0 +OP4 E0004B 0 +OP4 E0004C 0 +OP4 E0004D 0 +OP4 E0004E 0 +OP4 E0004F 0 +OP4 E00050 0 +OP4 E00051 0 +OP4 E00052 0 +OP4 E00053 0 +OP4 E00054 0 +OP4 E00055 0 +OP4 E00056 0 +OP4 E00057 0 +OP4 E00058 0 +OP4 E00059 0 +OP4 E0005A 0 +OP4 E0005B 0 +OP4 E0005C 0 +OP4 E0005D 0 +OP4 E0005E 0 +OP4 E0005F 0 +OP4 E00060 0 +OP4 E00061 0 +OP4 E00062 0 +OP4 E00063 0 +OP4 E00064 0 +OP4 E00065 0 +OP4 E00066 0 +OP4 E00067 0 +OP4 E00068 0 +OP4 E00069 0 +OP4 E0006A 0 +OP4 E0006B 0 +OP4 E0006C 0 +OP4 E0006D 0 +OP4 E0006E 0 +OP4 E0006F 0 +OP4 E00070 0 +OP4 E00071 0 +OP4 E00072 0 +OP4 E00073 0 +OP4 E00074 0 +OP4 E00075 0 +OP4 E00076 0 +OP4 E00077 0 +OP4 E00078 0 +OP4 E00079 0 +OP4 E0007A 0 +OP4 E0007B 0 +OP4 E0007C 0 +OP4 E0007D 0 +OP4 E0007E 0 +OP4 E0007F 0 +OP4 E00080 0 +OP4 E00081 0 +OP4 E00082 0 +OP4 E00083 0 +OP4 E00084 0 +OP4 E00085 0 +OP4 E00086 0 +OP4 E00087 0 +OP4 E00088 0 +OP4 E00089 0 +OP4 E0008A 0 +OP4 E0008B 0 +OP4 E0008C 0 +OP4 E0008D 0 +OP4 E0008E 0 +OP4 E0008F 0 +OP4 E00090 0 +OP4 E00091 0 +OP4 E00092 0 +OP4 E00093 0 +OP4 E00094 0 +OP4 E00095 0 +OP4 E00096 0 +OP4 E00097 0 +OP4 E00098 0 +OP4 E00099 0 +OP4 E0009A 0 +OP4 E0009B 0 +OP4 E0009C 0 +OP4 E0009D 0 +OP4 E0009E 0 +OP4 E0009F 0 +OP4 E000A0 0 +OP4 E000A1 0 +OP4 E000A2 0 +OP4 E000A3 0 +OP4 E000A4 0 +OP4 E000A5 0 +OP4 E000A6 0 +OP4 E000A7 0 +OP4 E000A8 0 +OP4 E000A9 0 +OP4 E000AA 0 +OP4 E000AB 0 +OP4 E000AC 0 +OP4 E000AD 0 +OP4 E000AE 0 +OP4 E000AF 0 +OP4 E000B0 0 +OP4 E000B1 0 +OP4 E000B2 0 +OP4 E000B3 0 +OP4 E000B4 0 +OP4 E000B5 0 +OP4 E000B6 0 +OP4 E000B7 0 +OP4 E000B8 0 +OP4 E000B9 0 +OP4 E000BA 0 +OP4 E000BB 0 +OP4 E000BC 0 +OP4 E000BD 0 +OP4 E000BE 0 +OP4 E000BF 0 +OP4 E000C0 0 +OP4 E000C1 0 +OP4 E000C2 0 +OP4 E000C3 0 +OP4 E000C4 0 +OP4 E000C5 0 +OP4 E000C6 0 +OP4 E000C7 0 +OP4 E000C8 0 +OP4 E000C9 0 +OP4 E000CA 0 +OP4 E000CB 0 +OP4 E000CC 0 +OP4 E000CD 0 +OP4 E000CE 0 +OP4 E000CF 0 +OP4 E000D0 0 +OP4 E000D1 0 +OP4 E000D2 0 +OP4 E000D3 0 +OP4 E000D4 0 +OP4 E000D5 0 +OP4 E000D6 0 +OP4 E000D7 0 +OP4 E000D8 0 +OP4 E000D9 0 +OP4 E000DA 0 +OP4 E000DB 0 +OP4 E000DC 0 +OP4 E000DD 0 +OP4 E000DE 0 +OP4 E000DF 0 +OP4 E000E0 0 +OP4 E000E1 0 +OP4 E000E2 0 +OP4 E000E3 0 +OP4 E000E4 0 +OP4 E000E5 0 +OP4 E000E6 0 +OP4 E000E7 0 +OP4 E000E8 0 +OP4 E000E9 0 +OP4 E000EA 0 +OP4 E000EB 0 +OP4 E000EC 0 +OP4 E000ED 0 +OP4 E000EE 0 +OP4 E000EF 0 +OP4 E000F0 0 +OP4 E000F1 0 +OP4 E000F2 0 +OP4 E000F3 0 +OP4 E000F4 0 +OP4 E000F5 0 +OP4 E000F6 0 +OP4 E000F7 0 +OP4 E000F8 0 +OP4 E000F9 0 +OP4 E000FA 0 +OP4 E000FB 0 +OP4 E000FC 0 +OP4 E000FD 0 +OP4 E000FE 0 +OP4 E000FF 0 +OP4 E00100 0 +OP4 E00101 0 +OP4 E00102 0 +OP4 E00103 0 +OP4 E00104 0 +OP4 E00105 0 +OP4 E00106 0 +OP4 E00107 0 +OP4 E00108 0 +OP4 E00109 0 +OP4 E0010A 0 +OP4 E0010B 0 +OP4 E0010C 0 +OP4 E0010D 0 +OP4 E0010E 0 +OP4 E0010F 0 +OP4 E00110 0 +OP4 E00111 0 +OP4 E00112 0 +OP4 E00113 0 +OP4 E00114 0 +OP4 E00115 0 +OP4 E00116 0 +OP4 E00117 0 +OP4 E00118 0 +OP4 E00119 0 +OP4 E0011A 0 +OP4 E0011B 0 +OP4 E0011C 0 +OP4 E0011D 0 +OP4 E0011E 0 +OP4 E0011F 0 +OP4 E00120 0 +OP4 E00121 0 +OP4 E00122 0 +OP4 E00123 0 +OP4 E00124 0 +OP4 E00125 0 +OP4 E00126 0 +OP4 E00127 0 +OP4 E00128 0 +OP4 E00129 0 +OP4 E0012A 0 +OP4 E0012B 0 +OP4 E0012C 0 +OP4 E0012D 0 +OP4 E0012E 0 +OP4 E0012F 0 +OP4 E00130 0 +OP4 E00131 0 +OP4 E00132 0 +OP4 E00133 0 +OP4 E00134 0 +OP4 E00135 0 +OP4 E00136 0 +OP4 E00137 0 +OP4 E00138 0 +OP4 E00139 0 +OP4 E0013A 0 +OP4 E0013B 0 +OP4 E0013C 0 +OP4 E0013D 0 +OP4 E0013E 0 +OP4 E0013F 0 +OP4 E00140 0 +OP4 E00141 0 +OP4 E00142 0 +OP4 E00143 0 +OP4 E00144 0 +OP4 E00145 0 +OP4 E00146 0 +OP4 E00147 0 +OP4 E00148 0 +OP4 E00149 0 +OP4 E0014A 0 +OP4 E0014B 0 +OP4 E0014C 0 +OP4 E0014D 0 +OP4 E0014E 0 +OP4 E0014F 0 +OP4 E00150 0 +OP4 E00151 0 +OP4 E00152 0 +OP4 E00153 0 +OP4 E00154 0 +OP4 E00155 0 +OP4 E00156 0 +OP4 E00157 0 +OP4 E00158 0 +OP4 E00159 0 +OP4 E0015A 0 +OP4 E0015B 0 +OP4 E0015C 0 +OP4 E0015D 0 +OP4 E0015E 0 +OP4 E0015F 0 +OP4 E00160 0 +OP4 E00161 0 +OP4 E00162 0 +OP4 E00163 0 +OP4 E00164 0 +OP4 E00165 0 +OP4 E00166 0 +OP4 E00167 0 +OP4 E00168 0 +OP4 E00169 0 +OP4 E0016A 0 +OP4 E0016B 0 +OP4 E0016C 0 +OP4 E0016D 0 +OP4 E0016E 0 +OP4 E0016F 0 +OP4 E00170 0 +OP4 E00171 0 +OP4 E00172 0 +OP4 E00173 0 +OP4 E00174 0 +OP4 E00175 0 +OP4 E00176 0 +OP4 E00177 0 +OP4 E00178 0 +OP4 E00179 0 +OP4 E0017A 0 +OP4 E0017B 0 +OP4 E0017C 0 +OP4 E0017D 0 +OP4 E0017E 0 +OP4 E0017F 0 +OP4 E00180 0 +OP4 E00181 0 +OP4 E00182 0 +OP4 E00183 0 +OP4 E00184 0 +OP4 E00185 0 +OP4 E00186 0 +OP4 E00187 0 +OP4 E00188 0 +OP4 E00189 0 +OP4 E0018A 0 +OP4 E0018B 0 +OP4 E0018C 0 +OP4 E0018D 0 +OP4 E0018E 0 +OP4 E0018F 0 +OP4 E00190 0 +OP4 E00191 0 +OP4 E00192 0 +OP4 E00193 0 +OP4 E00194 0 +OP4 E00195 0 +OP4 E00196 0 +OP4 E00197 0 +OP4 E00198 0 +OP4 E00199 0 +OP4 E0019A 0 +OP4 E0019B 0 +OP4 E0019C 0 +OP4 E0019D 0 +OP4 E0019E 0 +OP4 E0019F 0 +OP4 E001A0 0 +OP4 E001A1 0 +OP4 E001A2 0 +OP4 E001A3 0 +OP4 E001A4 0 +OP4 E001A5 0 +OP4 E001A6 0 +OP4 E001A7 0 +OP4 E001A8 0 +OP4 E001A9 0 +OP4 E001AA 0 +OP4 E001AB 0 +OP4 E001AC 0 +OP4 E001AD 0 +OP4 E001AE 0 +OP4 E001AF 0 +OP4 E001B0 0 +OP4 E001B1 0 +OP4 E001B2 0 +OP4 E001B3 0 +OP4 E001B4 0 +OP4 E001B5 0 +OP4 E001B6 0 +OP4 E001B7 0 +OP4 E001B8 0 +OP4 E001B9 0 +OP4 E001BA 0 +OP4 E001BB 0 +OP4 E001BC 0 +OP4 E001BD 0 +OP4 E001BE 0 +OP4 E001BF 0 +OP4 E001C0 0 +OP4 E001C1 0 +OP4 E001C2 0 +OP4 E001C3 0 +OP4 E001C4 0 +OP4 E001C5 0 +OP4 E001C6 0 +OP4 E001C7 0 +OP4 E001C8 0 +OP4 E001C9 0 +OP4 E001CA 0 +OP4 E001CB 0 +OP4 E001CC 0 +OP4 E001CD 0 +OP4 E001CE 0 +OP4 E001CF 0 +OP4 E001D0 0 +OP4 E001D1 0 +OP4 E001D2 0 +OP4 E001D3 0 +OP4 E001D4 0 +OP4 E001D5 0 +OP4 E001D6 0 +OP4 E001D7 0 +OP4 E001D8 0 +OP4 E001D9 0 +OP4 E001DA 0 +OP4 E001DB 0 +OP4 E001DC 0 +OP4 E001DD 0 +OP4 E001DE 0 +OP4 E001DF 0 +OP4 E001E0 0 +OP4 E001E1 0 +OP4 E001E2 0 +OP4 E001E3 0 +OP4 E001E4 0 +OP4 E001E5 0 +OP4 E001E6 0 +OP4 E001E7 0 +OP4 E001E8 0 +OP4 E001E9 0 +OP4 E001EA 0 +OP4 E001EB 0 +OP4 E001EC 0 +OP4 E001ED 0 +OP4 E001EE 0 +OP4 E001EF 0 +OP4 E001F0 0 +OP4 E001F1 0 +OP4 E001F2 0 +OP4 E001F3 0 +OP4 E001F4 0 +OP4 E001F5 0 +OP4 E001F6 0 +OP4 E001F7 0 +OP4 E001F8 0 +OP4 E001F9 0 +OP4 E001FA 0 +OP4 E001FB 0 +OP4 E001FC 0 +OP4 E001FD 0 +OP4 E001FE 0 +OP4 E001FF 0 +OP4 E00200 0 +OP4 E00201 0 +OP4 E00202 0 +OP4 E00203 0 +OP4 E00204 0 +OP4 E00205 0 +OP4 E00206 0 +OP4 E00207 0 +OP4 E00208 0 +OP4 E00209 0 +OP4 E0020A 0 +OP4 E0020B 0 +OP4 E0020C 0 +OP4 E0020D 0 +OP4 E0020E 0 +OP4 E0020F 0 +OP4 E00210 0 +OP4 E00211 0 +OP4 E00212 0 +OP4 E00213 0 +OP4 E00214 0 +OP4 E00215 0 +OP4 E00216 0 +OP4 E00217 0 +OP4 E00218 0 +OP4 E00219 0 +OP4 E0021A 0 +OP4 E0021B 0 +OP4 E0021C 0 +OP4 E0021D 0 +OP4 E0021E 0 +OP4 E0021F 0 +OP4 E00220 0 +OP4 E00221 0 +OP4 E00222 0 +OP4 E00223 0 +OP4 E00224 0 +OP4 E00225 0 +OP4 E00226 0 +OP4 E00227 0 +OP4 E00228 0 +OP4 E00229 0 +OP4 E0022A 0 +OP4 E0022B 0 +OP4 E0022C 0 +OP4 E0022D 0 +OP4 E0022E 0 +OP4 E0022F 0 +OP4 E00230 0 +OP4 E00231 0 +OP4 E00232 0 +OP4 E00233 0 +OP4 E00234 0 +OP4 E00235 0 +OP4 E00236 0 +OP4 E00237 0 +OP4 E00238 0 +OP4 E00239 0 +OP4 E0023A 0 +OP4 E0023B 0 +OP4 E0023C 0 +OP4 E0023D 0 +OP4 E0023E 0 +OP4 E0023F 0 +OP4 E00240 0 +OP4 E00241 0 +OP4 E00242 0 +OP4 E00243 0 +OP4 E00244 0 +OP4 E00245 0 +OP4 E00246 0 +OP4 E00247 0 +OP4 E00248 0 +OP4 E00249 0 +OP4 E0024A 0 +OP4 E0024B 0 +OP4 E0024C 0 +OP4 E0024D 0 +OP4 E0024E 0 +OP4 E0024F 0 +OP4 E00250 0 +OP4 E00251 0 +OP4 E00252 0 +OP4 E00253 0 +OP4 E00254 0 +OP4 E00255 0 +OP4 E00256 0 +OP4 E00257 0 +OP4 E00258 0 +OP4 E00259 0 +OP4 E0025A 0 +OP4 E0025B 0 +OP4 E0025C 0 +OP4 E0025D 0 +OP4 E0025E 0 +OP4 E0025F 0 +OP4 E00260 0 +OP4 E00261 0 +OP4 E00262 0 +OP4 E00263 0 +OP4 E00264 0 +OP4 E00265 0 +OP4 E00266 0 +OP4 E00267 0 +OP4 E00268 0 +OP4 E00269 0 +OP4 E0026A 0 +OP4 E0026B 0 +OP4 E0026C 0 +OP4 E0026D 0 +OP4 E0026E 0 +OP4 E0026F 0 +OP4 E00270 0 +OP4 E00271 0 +OP4 E00272 0 +OP4 E00273 0 +OP4 E00274 0 +OP4 E00275 0 +OP4 E00276 0 +OP4 E00277 0 +OP4 E00278 0 +OP4 E00279 0 +OP4 E0027A 0 +OP4 E0027B 0 +OP4 E0027C 0 +OP4 E0027D 0 +OP4 E0027E 0 +OP4 E0027F 0 +OP4 E00280 0 +OP4 E00281 0 +OP4 E00282 0 +OP4 E00283 0 +OP4 E00284 0 +OP4 E00285 0 +OP4 E00286 0 +OP4 E00287 0 +OP4 E00288 0 +OP4 E00289 0 +OP4 E0028A 0 +OP4 E0028B 0 +OP4 E0028C 0 +OP4 E0028D 0 +OP4 E0028E 0 +OP4 E0028F 0 +OP4 E00290 0 +OP4 E00291 0 +OP4 E00292 0 +OP4 E00293 0 +OP4 E00294 0 +OP4 E00295 0 +OP4 E00296 0 +OP4 E00297 0 +OP4 E00298 0 +OP4 E00299 0 +OP4 E0029A 0 +OP4 E0029B 0 +OP4 E0029C 0 +OP4 E0029D 0 +OP4 E0029E 0 +OP4 E0029F 0 +OP4 E002A0 0 +OP4 E002A1 0 +OP4 E002A2 0 +OP4 E002A3 0 +OP4 E002A4 0 +OP4 E002A5 0 +OP4 E002A6 0 +OP4 E002A7 0 +OP4 E002A8 0 +OP4 E002A9 0 +OP4 E002AA 0 +OP4 E002AB 0 +OP4 E002AC 0 +OP4 E002AD 0 +OP4 E002AE 0 +OP4 E002AF 0 +OP4 E002B0 0 +OP4 E002B1 0 +OP4 E002B2 0 +OP4 E002B3 0 +OP4 E002B4 0 +OP4 E002B5 0 +OP4 E002B6 0 +OP4 E002B7 0 +OP4 E002B8 0 +OP4 E002B9 0 +OP4 E002BA 0 +OP4 E002BB 0 +OP4 E002BC 0 +OP4 E002BD 0 +OP4 E002BE 0 +OP4 E002BF 0 +OP4 E002C0 0 +OP4 E002C1 0 +OP4 E002C2 0 +OP4 E002C3 0 +OP4 E002C4 0 +OP4 E002C5 0 +OP4 E002C6 0 +OP4 E002C7 0 +OP4 E002C8 0 +OP4 E002C9 0 +OP4 E002CA 0 +OP4 E002CB 0 +OP4 E002CC 0 +OP4 E002CD 0 +OP4 E002CE 0 +OP4 E002CF 0 +OP4 E002D0 0 +OP4 E002D1 0 +OP4 E002D2 0 +OP4 E002D3 0 +OP4 E002D4 0 +OP4 E002D5 0 +OP4 E002D6 0 +OP4 E002D7 0 +OP4 E002D8 0 +OP4 E002D9 0 +OP4 E002DA 0 +OP4 E002DB 0 +OP4 E002DC 0 +OP4 E002DD 0 +OP4 E002DE 0 +OP4 E002DF 0 +OP4 E002E0 0 +OP4 E002E1 0 +OP4 E002E2 0 +OP4 E002E3 0 +OP4 E002E4 0 +OP4 E002E5 0 +OP4 E002E6 0 +OP4 E002E7 0 +OP4 E002E8 0 +OP4 E002E9 0 +OP4 E002EA 0 +OP4 E002EB 0 +OP4 E002EC 0 +OP4 E002ED 0 +OP4 E002EE 0 +OP4 E002EF 0 +OP4 E002F0 0 +OP4 E002F1 0 +OP4 E002F2 0 +OP4 E002F3 0 +OP4 E002F4 0 +OP4 E002F5 0 +OP4 E002F6 0 +OP4 E002F7 0 +OP4 E002F8 0 +OP4 E002F9 0 +OP4 E002FA 0 +OP4 E002FB 0 +OP4 E002FC 0 +OP4 E002FD 0 +OP4 E002FE 0 +OP4 E002FF 0 +OP4 E00300 0 +OP4 E00301 0 +OP4 E00302 0 +OP4 E00303 0 +OP4 E00304 0 +OP4 E00305 0 +OP4 E00306 0 +OP4 E00307 0 +OP4 E00308 0 +OP4 E00309 0 +OP4 E0030A 0 +OP4 E0030B 0 +OP4 E0030C 0 +OP4 E0030D 0 +OP4 E0030E 0 +OP4 E0030F 0 +OP4 E00310 0 +OP4 E00311 0 +OP4 E00312 0 +OP4 E00313 0 +OP4 E00314 0 +OP4 E00315 0 +OP4 E00316 0 +OP4 E00317 0 +OP4 E00318 0 +OP4 E00319 0 +OP4 E0031A 0 +OP4 E0031B 0 +OP4 E0031C 0 +OP4 E0031D 0 +OP4 E0031E 0 +OP4 E0031F 0 +OP4 E00320 0 +OP4 E00321 0 +OP4 E00322 0 +OP4 E00323 0 +OP4 E00324 0 +OP4 E00325 0 +OP4 E00326 0 +OP4 E00327 0 +OP4 E00328 0 +OP4 E00329 0 +OP4 E0032A 0 +OP4 E0032B 0 +OP4 E0032C 0 +OP4 E0032D 0 +OP4 E0032E 0 +OP4 E0032F 0 +OP4 E00330 0 +OP4 E00331 0 +OP4 E00332 0 +OP4 E00333 0 +OP4 E00334 0 +OP4 E00335 0 +OP4 E00336 0 +OP4 E00337 0 +OP4 E00338 0 +OP4 E00339 0 +OP4 E0033A 0 +OP4 E0033B 0 +OP4 E0033C 0 +OP4 E0033D 0 +OP4 E0033E 0 +OP4 E0033F 0 +OP4 E00340 0 +OP4 E00341 0 +OP4 E00342 0 +OP4 E00343 0 +OP4 E00344 0 +OP4 E00345 0 +OP4 E00346 0 +OP4 E00347 0 +OP4 E00348 0 +OP4 E00349 0 +OP4 E0034A 0 +OP4 E0034B 0 +OP4 E0034C 0 +OP4 E0034D 0 +OP4 E0034E 0 +OP4 E0034F 0 +OP4 E00350 0 +OP4 E00351 0 +OP4 E00352 0 +OP4 E00353 0 +OP4 E00354 0 +OP4 E00355 0 +OP4 E00356 0 +OP4 E00357 0 +OP4 E00358 0 +OP4 E00359 0 +OP4 E0035A 0 +OP4 E0035B 0 +OP4 E0035C 0 +OP4 E0035D 0 +OP4 E0035E 0 +OP4 E0035F 0 +OP4 E00360 0 +OP4 E00361 0 +OP4 E00362 0 +OP4 E00363 0 +OP4 E00364 0 +OP4 E00365 0 +OP4 E00366 0 +OP4 E00367 0 +OP4 E00368 0 +OP4 E00369 0 +OP4 E0036A 0 +OP4 E0036B 0 +OP4 E0036C 0 +OP4 E0036D 0 +OP4 E0036E 0 +OP4 E0036F 0 +OP4 E00370 0 +OP4 E00371 0 +OP4 E00372 0 +OP4 E00373 0 +OP4 E00374 0 +OP4 E00375 0 +OP4 E00376 0 +OP4 E00377 0 +OP4 E00378 0 +OP4 E00379 0 +OP4 E0037A 0 +OP4 E0037B 0 +OP4 E0037C 0 +OP4 E0037D 0 +OP4 E0037E 0 +OP4 E0037F 0 +OP4 E00380 0 +OP4 E00381 0 +OP4 E00382 0 +OP4 E00383 0 +OP4 E00384 0 +OP4 E00385 0 +OP4 E00386 0 +OP4 E00387 0 +OP4 E00388 0 +OP4 E00389 0 +OP4 E0038A 0 +OP4 E0038B 0 +OP4 E0038C 0 +OP4 E0038D 0 +OP4 E0038E 0 +OP4 E0038F 0 +OP4 E00390 0 +OP4 E00391 0 +OP4 E00392 0 +OP4 E00393 0 +OP4 E00394 0 +OP4 E00395 0 +OP4 E00396 0 +OP4 E00397 0 +OP4 E00398 0 +OP4 E00399 0 +OP4 E0039A 0 +OP4 E0039B 0 +OP4 E0039C 0 +OP4 E0039D 0 +OP4 E0039E 0 +OP4 E0039F 0 +OP4 E003A0 0 +OP4 E003A1 0 +OP4 E003A2 0 +OP4 E003A3 0 +OP4 E003A4 0 +OP4 E003A5 0 +OP4 E003A6 0 +OP4 E003A7 0 +OP4 E003A8 0 +OP4 E003A9 0 +OP4 E003AA 0 +OP4 E003AB 0 +OP4 E003AC 0 +OP4 E003AD 0 +OP4 E003AE 0 +OP4 E003AF 0 +OP4 E003B0 0 +OP4 E003B1 0 +OP4 E003B2 0 +OP4 E003B3 0 +OP4 E003B4 0 +OP4 E003B5 0 +OP4 E003B6 0 +OP4 E003B7 0 +OP4 E003B8 0 +OP4 E003B9 0 +OP4 E003BA 0 +OP4 E003BB 0 +OP4 E003BC 0 +OP4 E003BD 0 +OP4 E003BE 0 +OP4 E003BF 0 +OP4 E003C0 0 +OP4 E003C1 0 +OP4 E003C2 0 +OP4 E003C3 0 +OP4 E003C4 0 +OP4 E003C5 0 +OP4 E003C6 0 +OP4 E003C7 0 +OP4 E003C8 0 +OP4 E003C9 0 +OP4 E003CA 0 +OP4 E003CB 0 +OP4 E003CC 0 +OP4 E003CD 0 +OP4 E003CE 0 +OP4 E003CF 0 +OP4 E003D0 0 +OP4 E003D1 0 +OP4 E003D2 0 +OP4 E003D3 0 +OP4 E003D4 0 +OP4 E003D5 0 +OP4 E003D6 0 +OP4 E003D7 0 +OP4 E003D8 0 +OP4 E003D9 0 +OP4 E003DA 0 +OP4 E003DB 0 +OP4 E003DC 0 +OP4 E003DD 0 +OP4 E003DE 0 +OP4 E003DF 0 +OP4 E003E0 0 +OP4 E003E1 0 +OP4 E003E2 0 +OP4 E003E3 0 +OP4 E003E4 0 +OP4 E003E5 0 +OP4 E003E6 0 +OP4 E003E7 0 +OP4 E003E8 0 +OP4 E003E9 0 +OP4 E003EA 0 +OP4 E003EB 0 +OP4 E003EC 0 +OP4 E003ED 0 +OP4 E003EE 0 +OP4 E003EF 0 +OP4 E003F0 0 +OP4 E003F1 0 +OP4 E003F2 0 +OP4 E003F3 0 +OP4 E003F4 0 +OP4 E003F5 0 +OP4 E003F6 0 +OP4 E003F7 0 +OP4 E003F8 0 +OP4 E003F9 0 +OP4 E003FA 0 +OP4 E003FB 0 +OP4 E003FC 0 +OP4 E003FD 0 +OP4 E003FE 0 +OP4 E003FF 0 +OP4 E00400 0 +OP4 E00401 0 +OP4 E00402 0 +OP4 E00403 0 +OP4 E00404 0 +OP4 E00405 0 +OP4 E00406 0 +OP4 E00407 0 +OP4 E00408 0 +OP4 E00409 0 +OP4 E0040A 0 +OP4 E0040B 0 +OP4 E0040C 0 +OP4 E0040D 0 +OP4 E0040E 0 +OP4 E0040F 0 +OP4 E00410 0 +OP4 E00411 0 +OP4 E00412 0 +OP4 E00413 0 +OP4 E00414 0 +OP4 E00415 0 +OP4 E00416 0 +OP4 E00417 0 +OP4 E00418 0 +OP4 E00419 0 +OP4 E0041A 0 +OP4 E0041B 0 +OP4 E0041C 0 +OP4 E0041D 0 +OP4 E0041E 0 +OP4 E0041F 0 +OP4 E00420 0 +OP4 E00421 0 +OP4 E00422 0 +OP4 E00423 0 +OP4 E00424 0 +OP4 E00425 0 +OP4 E00426 0 +OP4 E00427 0 +OP4 E00428 0 +OP4 E00429 0 +OP4 E0042A 0 +OP4 E0042B 0 +OP4 E0042C 0 +OP4 E0042D 0 +OP4 E0042E 0 +OP4 E0042F 0 +OP4 E00430 0 +OP4 E00431 0 +OP4 E00432 0 +OP4 E00433 0 +OP4 E00434 0 +OP4 E00435 0 +OP4 E00436 0 +OP4 E00437 0 +OP4 E00438 0 +OP4 E00439 0 +OP4 E0043A 0 +OP4 E0043B 0 +OP4 E0043C 0 +OP4 E0043D 0 +OP4 E0043E 0 +OP4 E0043F 0 +OP4 E00440 0 +OP4 E00441 0 +OP4 E00442 0 +OP4 E00443 0 +OP4 E00444 0 +OP4 E00445 0 +OP4 E00446 0 +OP4 E00447 0 +OP4 E00448 0 +OP4 E00449 0 +OP4 E0044A 0 +OP4 E0044B 0 +OP4 E0044C 0 +OP4 E0044D 0 +OP4 E0044E 0 +OP4 E0044F 0 +OP4 E00450 0 +OP4 E00451 0 +OP4 E00452 0 +OP4 E00453 0 +OP4 E00454 0 +OP4 E00455 0 +OP4 E00456 0 +OP4 E00457 0 +OP4 E00458 0 +OP4 E00459 0 +OP4 E0045A 0 +OP4 E0045B 0 +OP4 E0045C 0 +OP4 E0045D 0 +OP4 E0045E 0 +OP4 E0045F 0 +OP4 E00460 0 +OP4 E00461 0 +OP4 E00462 0 +OP4 E00463 0 +OP4 E00464 0 +OP4 E00465 0 +OP4 E00466 0 +OP4 E00467 0 +OP4 E00468 0 +OP4 E00469 0 +OP4 E0046A 0 +OP4 E0046B 0 +OP4 E0046C 0 +OP4 E0046D 0 +OP4 E0046E 0 +OP4 E0046F 0 +OP4 E00470 0 +OP4 E00471 0 +OP4 E00472 0 +OP4 E00473 0 +OP4 E00474 0 +OP4 E00475 0 +OP4 E00476 0 +OP4 E00477 0 +OP4 E00478 0 +OP4 E00479 0 +OP4 E0047A 0 +OP4 E0047B 0 +OP4 E0047C 0 +OP4 E0047D 0 +OP4 E0047E 0 +OP4 E0047F 0 +OP4 E00480 0 +OP4 E00481 0 +OP4 E00482 0 +OP4 E00483 0 +OP4 E00484 0 +OP4 E00485 0 +OP4 E00486 0 +OP4 E00487 0 +OP4 E00488 0 +OP4 E00489 0 +OP4 E0048A 0 +OP4 E0048B 0 +OP4 E0048C 0 +OP4 E0048D 0 +OP4 E0048E 0 +OP4 E0048F 0 +OP4 E00490 0 +OP4 E00491 0 +OP4 E00492 0 +OP4 E00493 0 +OP4 E00494 0 +OP4 E00495 0 +OP4 E00496 0 +OP4 E00497 0 +OP4 E00498 0 +OP4 E00499 0 +OP4 E0049A 0 +OP4 E0049B 0 +OP4 E0049C 0 +OP4 E0049D 0 +OP4 E0049E 0 +OP4 E0049F 0 +OP4 E004A0 0 +OP4 E004A1 0 +OP4 E004A2 0 +OP4 E004A3 0 +OP4 E004A4 0 +OP4 E004A5 0 +OP4 E004A6 0 +OP4 E004A7 0 +OP4 E004A8 0 +OP4 E004A9 0 +OP4 E004AA 0 +OP4 E004AB 0 +OP4 E004AC 0 +OP4 E004AD 0 +OP4 E004AE 0 +OP4 E004AF 0 +OP4 E004B0 0 +OP4 E004B1 0 +OP4 E004B2 0 +OP4 E004B3 0 +OP4 E004B4 0 +OP4 E004B5 0 +OP4 E004B6 0 +OP4 E004B7 0 +OP4 E004B8 0 +OP4 E004B9 0 +OP4 E004BA 0 +OP4 E004BB 0 +OP4 E004BC 0 +OP4 E004BD 0 +OP4 E004BE 0 +OP4 E004BF 0 +OP4 E004C0 0 +OP4 E004C1 0 +OP4 E004C2 0 +OP4 E004C3 0 +OP4 E004C4 0 +OP4 E004C5 0 +OP4 E004C6 0 +OP4 E004C7 0 +OP4 E004C8 0 +OP4 E004C9 0 +OP4 E004CA 0 +OP4 E004CB 0 +OP4 E004CC 0 +OP4 E004CD 0 +OP4 E004CE 0 +OP4 E004CF 0 +OP4 E004D0 0 +OP4 E004D1 0 +OP4 E004D2 0 +OP4 E004D3 0 +OP4 E004D4 0 +OP4 E004D5 0 +OP4 E004D6 0 +OP4 E004D7 0 +OP4 E004D8 0 +OP4 E004D9 0 +OP4 E004DA 0 +OP4 E004DB 0 +OP4 E004DC 0 +OP4 E004DD 0 +OP4 E004DE 0 +OP4 E004DF 0 +OP4 E004E0 0 +OP4 E004E1 0 +OP4 E004E2 0 +OP4 E004E3 0 +OP4 E004E4 0 +OP4 E004E5 0 +OP4 E004E6 0 +OP4 E004E7 0 +OP4 E004E8 0 +OP4 E004E9 0 +OP4 E004EA 0 +OP4 E004EB 0 +OP4 E004EC 0 +OP4 E004ED 0 +OP4 E004EE 0 +OP4 E004EF 0 +OP4 E004F0 0 +OP4 E004F1 0 +OP4 E004F2 0 +OP4 E004F3 0 +OP4 E004F4 0 +OP4 E004F5 0 +OP4 E004F6 0 +OP4 E004F7 0 +OP4 E004F8 0 +OP4 E004F9 0 +OP4 E004FA 0 +OP4 E004FB 0 +OP4 E004FC 0 +OP4 E004FD 0 +OP4 E004FE 0 +OP4 E004FF 0 +OP4 E00500 0 +OP4 E00501 0 +OP4 E00502 0 +OP4 E00503 0 +OP4 E00504 0 +OP4 E00505 0 +OP4 E00506 0 +OP4 E00507 0 +OP4 E00508 0 +OP4 E00509 0 +OP4 E0050A 0 +OP4 E0050B 0 +OP4 E0050C 0 +OP4 E0050D 0 +OP4 E0050E 0 +OP4 E0050F 0 +OP4 E00510 0 +OP4 E00511 0 +OP4 E00512 0 +OP4 E00513 0 +OP4 E00514 0 +OP4 E00515 0 +OP4 E00516 0 +OP4 E00517 0 +OP4 E00518 0 +OP4 E00519 0 +OP4 E0051A 0 +OP4 E0051B 0 +OP4 E0051C 0 +OP4 E0051D 0 +OP4 E0051E 0 +OP4 E0051F 0 +OP4 E00520 0 +OP4 E00521 0 +OP4 E00522 0 +OP4 E00523 0 +OP4 E00524 0 +OP4 E00525 0 +OP4 E00526 0 +OP4 E00527 0 +OP4 E00528 0 +OP4 E00529 0 +OP4 E0052A 0 +OP4 E0052B 0 +OP4 E0052C 0 +OP4 E0052D 0 +OP4 E0052E 0 +OP4 E0052F 0 +OP4 E00530 0 +OP4 E00531 0 +OP4 E00532 0 +OP4 E00533 0 +OP4 E00534 0 +OP4 E00535 0 +OP4 E00536 0 +OP4 E00537 0 +OP4 E00538 0 +OP4 E00539 0 +OP4 E0053A 0 +OP4 E0053B 0 +OP4 E0053C 0 +OP4 E0053D 0 +OP4 E0053E 0 +OP4 E0053F 0 +OP4 E00540 0 +OP4 E00541 0 +OP4 E00542 0 +OP4 E00543 0 +OP4 E00544 0 +OP4 E00545 0 +OP4 E00546 0 +OP4 E00547 0 +OP4 E00548 0 +OP4 E00549 0 +OP4 E0054A 0 +OP4 E0054B 0 +OP4 E0054C 0 +OP4 E0054D 0 +OP4 E0054E 0 +OP4 E0054F 0 +OP4 E00550 0 +OP4 E00551 0 +OP4 E00552 0 +OP4 E00553 0 +OP4 E00554 0 +OP4 E00555 0 +OP4 E00556 0 +OP4 E00557 0 +OP4 E00558 0 +OP4 E00559 0 +OP4 E0055A 0 +OP4 E0055B 0 +OP4 E0055C 0 +OP4 E0055D 0 +OP4 E0055E 0 +OP4 E0055F 0 +OP4 E00560 0 +OP4 E00561 0 +OP4 E00562 0 +OP4 E00563 0 +OP4 E00564 0 +OP4 E00565 0 +OP4 E00566 0 +OP4 E00567 0 +OP4 E00568 0 +OP4 E00569 0 +OP4 E0056A 0 +OP4 E0056B 0 +OP4 E0056C 0 +OP4 E0056D 0 +OP4 E0056E 0 +OP4 E0056F 0 +OP4 E00570 0 +OP4 E00571 0 +OP4 E00572 0 +OP4 E00573 0 +OP4 E00574 0 +OP4 E00575 0 +OP4 E00576 0 +OP4 E00577 0 +OP4 E00578 0 +OP4 E00579 0 +OP4 E0057A 0 +OP4 E0057B 0 +OP4 E0057C 0 +OP4 E0057D 0 +OP4 E0057E 0 +OP4 E0057F 0 +OP4 E00580 0 +OP4 E00581 0 +OP4 E00582 0 +OP4 E00583 0 +OP4 E00584 0 +OP4 E00585 0 +OP4 E00586 0 +OP4 E00587 0 +OP4 E00588 0 +OP4 E00589 0 +OP4 E0058A 0 +OP4 E0058B 0 +OP4 E0058C 0 +OP4 E0058D 0 +OP4 E0058E 0 +OP4 E0058F 0 +OP4 E00590 0 +OP4 E00591 0 +OP4 E00592 0 +OP4 E00593 0 +OP4 E00594 0 +OP4 E00595 0 +OP4 E00596 0 +OP4 E00597 0 +OP4 E00598 0 +OP4 E00599 0 +OP4 E0059A 0 +OP4 E0059B 0 +OP4 E0059C 0 +OP4 E0059D 0 +OP4 E0059E 0 +OP4 E0059F 0 +OP4 E005A0 0 +OP4 E005A1 0 +OP4 E005A2 0 +OP4 E005A3 0 +OP4 E005A4 0 +OP4 E005A5 0 +OP4 E005A6 0 +OP4 E005A7 0 +OP4 E005A8 0 +OP4 E005A9 0 +OP4 E005AA 0 +OP4 E005AB 0 +OP4 E005AC 0 +OP4 E005AD 0 +OP4 E005AE 0 +OP4 E005AF 0 +OP4 E005B0 0 +OP4 E005B1 0 +OP4 E005B2 0 +OP4 E005B3 0 +OP4 E005B4 0 +OP4 E005B5 0 +OP4 E005B6 0 +OP4 E005B7 0 +OP4 E005B8 0 +OP4 E005B9 0 +OP4 E005BA 0 +OP4 E005BB 0 +OP4 E005BC 0 +OP4 E005BD 0 +OP4 E005BE 0 +OP4 E005BF 0 +OP4 E005C0 0 +OP4 E005C1 0 +OP4 E005C2 0 +OP4 E005C3 0 +OP4 E005C4 0 +OP4 E005C5 0 +OP4 E005C6 0 +OP4 E005C7 0 +OP4 E005C8 0 +OP4 E005C9 0 +OP4 E005CA 0 +OP4 E005CB 0 +OP4 E005CC 0 +OP4 E005CD 0 +OP4 E005CE 0 +OP4 E005CF 0 +OP4 E005D0 0 +OP4 E005D1 0 +OP4 E005D2 0 +OP4 E005D3 0 +OP4 E005D4 0 +OP4 E005D5 0 +OP4 E005D6 0 +OP4 E005D7 0 +OP4 E005D8 0 +OP4 E005D9 0 +OP4 E005DA 0 +OP4 E005DB 0 +OP4 E005DC 0 +OP4 E005DD 0 +OP4 E005DE 0 +OP4 E005DF 0 +OP4 E005E0 0 +OP4 E005E1 0 +OP4 E005E2 0 +OP4 E005E3 0 +OP4 E005E4 0 +OP4 E005E5 0 +OP4 E005E6 0 +OP4 E005E7 0 +OP4 E005E8 0 +OP4 E005E9 0 +OP4 E005EA 0 +OP4 E005EB 0 +OP4 E005EC 0 +OP4 E005ED 0 +OP4 E005EE 0 +OP4 E005EF 0 +OP4 E005F0 0 +OP4 E005F1 0 +OP4 E005F2 0 +OP4 E005F3 0 +OP4 E005F4 0 +OP4 E005F5 0 +OP4 E005F6 0 +OP4 E005F7 0 +OP4 E005F8 0 +OP4 E005F9 0 +OP4 E005FA 0 +OP4 E005FB 0 +OP4 E005FC 0 +OP4 E005FD 0 +OP4 E005FE 0 +OP4 E005FF 0 +OP4 E00600 0 +OP4 E00601 0 +OP4 E00602 0 +OP4 E00603 0 +OP4 E00604 0 +OP4 E00605 0 +OP4 E00606 0 +OP4 E00607 0 +OP4 E00608 0 +OP4 E00609 0 +OP4 E0060A 0 +OP4 E0060B 0 +OP4 E0060C 0 +OP4 E0060D 0 +OP4 E0060E 0 +OP4 E0060F 0 +OP4 E00610 0 +OP4 E00611 0 +OP4 E00612 0 +OP4 E00613 0 +OP4 E00614 0 +OP4 E00615 0 +OP4 E00616 0 +OP4 E00617 0 +OP4 E00618 0 +OP4 E00619 0 +OP4 E0061A 0 +OP4 E0061B 0 +OP4 E0061C 0 +OP4 E0061D 0 +OP4 E0061E 0 +OP4 E0061F 0 +OP4 E00620 0 +OP4 E00621 0 +OP4 E00622 0 +OP4 E00623 0 +OP4 E00624 0 +OP4 E00625 0 +OP4 E00626 0 +OP4 E00627 0 +OP4 E00628 0 +OP4 E00629 0 +OP4 E0062A 0 +OP4 E0062B 0 +OP4 E0062C 0 +OP4 E0062D 0 +OP4 E0062E 0 +OP4 E0062F 0 +OP4 E00630 0 +OP4 E00631 0 +OP4 E00632 0 +OP4 E00633 0 +OP4 E00634 0 +OP4 E00635 0 +OP4 E00636 0 +OP4 E00637 0 +OP4 E00638 0 +OP4 E00639 0 +OP4 E0063A 0 +OP4 E0063B 0 +OP4 E0063C 0 +OP4 E0063D 0 +OP4 E0063E 0 +OP4 E0063F 0 +OP4 E00640 0 +OP4 E00641 0 +OP4 E00642 0 +OP4 E00643 0 +OP4 E00644 0 +OP4 E00645 0 +OP4 E00646 0 +OP4 E00647 0 +OP4 E00648 0 +OP4 E00649 0 +OP4 E0064A 0 +OP4 E0064B 0 +OP4 E0064C 0 +OP4 E0064D 0 +OP4 E0064E 0 +OP4 E0064F 0 +OP4 E00650 0 +OP4 E00651 0 +OP4 E00652 0 +OP4 E00653 0 +OP4 E00654 0 +OP4 E00655 0 +OP4 E00656 0 +OP4 E00657 0 +OP4 E00658 0 +OP4 E00659 0 +OP4 E0065A 0 +OP4 E0065B 0 +OP4 E0065C 0 +OP4 E0065D 0 +OP4 E0065E 0 +OP4 E0065F 0 +OP4 E00660 0 +OP4 E00661 0 +OP4 E00662 0 +OP4 E00663 0 +OP4 E00664 0 +OP4 E00665 0 +OP4 E00666 0 +OP4 E00667 0 +OP4 E00668 0 +OP4 E00669 0 +OP4 E0066A 0 +OP4 E0066B 0 +OP4 E0066C 0 +OP4 E0066D 0 +OP4 E0066E 0 +OP4 E0066F 0 +OP4 E00670 0 +OP4 E00671 0 +OP4 E00672 0 +OP4 E00673 0 +OP4 E00674 0 +OP4 E00675 0 +OP4 E00676 0 +OP4 E00677 0 +OP4 E00678 0 +OP4 E00679 0 +OP4 E0067A 0 +OP4 E0067B 0 +OP4 E0067C 0 +OP4 E0067D 0 +OP4 E0067E 0 +OP4 E0067F 0 +OP4 E00680 0 +OP4 E00681 0 +OP4 E00682 0 +OP4 E00683 0 +OP4 E00684 0 +OP4 E00685 0 +OP4 E00686 0 +OP4 E00687 0 +OP4 E00688 0 +OP4 E00689 0 +OP4 E0068A 0 +OP4 E0068B 0 +OP4 E0068C 0 +OP4 E0068D 0 +OP4 E0068E 0 +OP4 E0068F 0 +OP4 E00690 0 +OP4 E00691 0 +OP4 E00692 0 +OP4 E00693 0 +OP4 E00694 0 +OP4 E00695 0 +OP4 E00696 0 +OP4 E00697 0 +OP4 E00698 0 +OP4 E00699 0 +OP4 E0069A 0 +OP4 E0069B 0 +OP4 E0069C 0 +OP4 E0069D 0 +OP4 E0069E 0 +OP4 E0069F 0 +OP4 E006A0 0 +OP4 E006A1 0 +OP4 E006A2 0 +OP4 E006A3 0 +OP4 E006A4 0 +OP4 E006A5 0 +OP4 E006A6 0 +OP4 E006A7 0 +OP4 E006A8 0 +OP4 E006A9 0 +OP4 E006AA 0 +OP4 E006AB 0 +OP4 E006AC 0 +OP4 E006AD 0 +OP4 E006AE 0 +OP4 E006AF 0 +OP4 E006B0 0 +OP4 E006B1 0 +OP4 E006B2 0 +OP4 E006B3 0 +OP4 E006B4 0 +OP4 E006B5 0 +OP4 E006B6 0 +OP4 E006B7 0 +OP4 E006B8 0 +OP4 E006B9 0 +OP4 E006BA 0 +OP4 E006BB 0 +OP4 E006BC 0 +OP4 E006BD 0 +OP4 E006BE 0 +OP4 E006BF 0 +OP4 E006C0 0 +OP4 E006C1 0 +OP4 E006C2 0 +OP4 E006C3 0 +OP4 E006C4 0 +OP4 E006C5 0 +OP4 E006C6 0 +OP4 E006C7 0 +OP4 E006C8 0 +OP4 E006C9 0 +OP4 E006CA 0 +OP4 E006CB 0 +OP4 E006CC 0 +OP4 E006CD 0 +OP4 E006CE 0 +OP4 E006CF 0 +OP4 E006D0 0 +OP4 E006D1 0 +OP4 E006D2 0 +OP4 E006D3 0 +OP4 E006D4 0 +OP4 E006D5 0 +OP4 E006D6 0 +OP4 E006D7 0 +OP4 E006D8 0 +OP4 E006D9 0 +OP4 E006DA 0 +OP4 E006DB 0 +OP4 E006DC 0 +OP4 E006DD 0 +OP4 E006DE 0 +OP4 E006DF 0 +OP4 E006E0 0 +OP4 E006E1 0 +OP4 E006E2 0 +OP4 E006E3 0 +OP4 E006E4 0 +OP4 E006E5 0 +OP4 E006E6 0 +OP4 E006E7 0 +OP4 E006E8 0 +OP4 E006E9 0 +OP4 E006EA 0 +OP4 E006EB 0 +OP4 E006EC 0 +OP4 E006ED 0 +OP4 E006EE 0 +OP4 E006EF 0 +OP4 E006F0 0 +OP4 E006F1 0 +OP4 E006F2 0 +OP4 E006F3 0 +OP4 E006F4 0 +OP4 E006F5 0 +OP4 E006F6 0 +OP4 E006F7 0 +OP4 E006F8 0 +OP4 E006F9 0 +OP4 E006FA 0 +OP4 E006FB 0 +OP4 E006FC 0 +OP4 E006FD 0 +OP4 E006FE 0 +OP4 E006FF 0 +OP4 E00700 0 +OP4 E00701 0 +OP4 E00702 0 +OP4 E00703 0 +OP4 E00704 0 +OP4 E00705 0 +OP4 E00706 0 +OP4 E00707 0 +OP4 E00708 0 +OP4 E00709 0 +OP4 E0070A 0 +OP4 E0070B 0 +OP4 E0070C 0 +OP4 E0070D 0 +OP4 E0070E 0 +OP4 E0070F 0 +OP4 E00710 0 +OP4 E00711 0 +OP4 E00712 0 +OP4 E00713 0 +OP4 E00714 0 +OP4 E00715 0 +OP4 E00716 0 +OP4 E00717 0 +OP4 E00718 0 +OP4 E00719 0 +OP4 E0071A 0 +OP4 E0071B 0 +OP4 E0071C 0 +OP4 E0071D 0 +OP4 E0071E 0 +OP4 E0071F 0 +OP4 E00720 0 +OP4 E00721 0 +OP4 E00722 0 +OP4 E00723 0 +OP4 E00724 0 +OP4 E00725 0 +OP4 E00726 0 +OP4 E00727 0 +OP4 E00728 0 +OP4 E00729 0 +OP4 E0072A 0 +OP4 E0072B 0 +OP4 E0072C 0 +OP4 E0072D 0 +OP4 E0072E 0 +OP4 E0072F 0 +OP4 E00730 0 +OP4 E00731 0 +OP4 E00732 0 +OP4 E00733 0 +OP4 E00734 0 +OP4 E00735 0 +OP4 E00736 0 +OP4 E00737 0 +OP4 E00738 0 +OP4 E00739 0 +OP4 E0073A 0 +OP4 E0073B 0 +OP4 E0073C 0 +OP4 E0073D 0 +OP4 E0073E 0 +OP4 E0073F 0 +OP4 E00740 0 +OP4 E00741 0 +OP4 E00742 0 +OP4 E00743 0 +OP4 E00744 0 +OP4 E00745 0 +OP4 E00746 0 +OP4 E00747 0 +OP4 E00748 0 +OP4 E00749 0 +OP4 E0074A 0 +OP4 E0074B 0 +OP4 E0074C 0 +OP4 E0074D 0 +OP4 E0074E 0 +OP4 E0074F 0 +OP4 E00750 0 +OP4 E00751 0 +OP4 E00752 0 +OP4 E00753 0 +OP4 E00754 0 +OP4 E00755 0 +OP4 E00756 0 +OP4 E00757 0 +OP4 E00758 0 +OP4 E00759 0 +OP4 E0075A 0 +OP4 E0075B 0 +OP4 E0075C 0 +OP4 E0075D 0 +OP4 E0075E 0 +OP4 E0075F 0 +OP4 E00760 0 +OP4 E00761 0 +OP4 E00762 0 +OP4 E00763 0 +OP4 E00764 0 +OP4 E00765 0 +OP4 E00766 0 +OP4 E00767 0 +OP4 E00768 0 +OP4 E00769 0 +OP4 E0076A 0 +OP4 E0076B 0 +OP4 E0076C 0 +OP4 E0076D 0 +OP4 E0076E 0 +OP4 E0076F 0 +OP4 E00770 0 +OP4 E00771 0 +OP4 E00772 0 +OP4 E00773 0 +OP4 E00774 0 +OP4 E00775 0 +OP4 E00776 0 +OP4 E00777 0 +OP4 E00778 0 +OP4 E00779 0 +OP4 E0077A 0 +OP4 E0077B 0 +OP4 E0077C 0 +OP4 E0077D 0 +OP4 E0077E 0 +OP4 E0077F 0 +OP4 E00780 0 +OP4 E00781 0 +OP4 E00782 0 +OP4 E00783 0 +OP4 E00784 0 +OP4 E00785 0 +OP4 E00786 0 +OP4 E00787 0 +OP4 E00788 0 +OP4 E00789 0 +OP4 E0078A 0 +OP4 E0078B 0 +OP4 E0078C 0 +OP4 E0078D 0 +OP4 E0078E 0 +OP4 E0078F 0 +OP4 E00790 0 +OP4 E00791 0 +OP4 E00792 0 +OP4 E00793 0 +OP4 E00794 0 +OP4 E00795 0 +OP4 E00796 0 +OP4 E00797 0 +OP4 E00798 0 +OP4 E00799 0 +OP4 E0079A 0 +OP4 E0079B 0 +OP4 E0079C 0 +OP4 E0079D 0 +OP4 E0079E 0 +OP4 E0079F 0 +OP4 E007A0 0 +OP4 E007A1 0 +OP4 E007A2 0 +OP4 E007A3 0 +OP4 E007A4 0 +OP4 E007A5 0 +OP4 E007A6 0 +OP4 E007A7 0 +OP4 E007A8 0 +OP4 E007A9 0 +OP4 E007AA 0 +OP4 E007AB 0 +OP4 E007AC 0 +OP4 E007AD 0 +OP4 E007AE 0 +OP4 E007AF 0 +OP4 E007B0 0 +OP4 E007B1 0 +OP4 E007B2 0 +OP4 E007B3 0 +OP4 E007B4 0 +OP4 E007B5 0 +OP4 E007B6 0 +OP4 E007B7 0 +OP4 E007B8 0 +OP4 E007B9 0 +OP4 E007BA 0 +OP4 E007BB 0 +OP4 E007BC 0 +OP4 E007BD 0 +OP4 E007BE 0 +OP4 E007BF 0 +OP4 E007C0 0 +OP4 E007C1 0 +OP4 E007C2 0 +OP4 E007C3 0 +OP4 E007C4 0 +OP4 E007C5 0 +OP4 E007C6 0 +OP4 E007C7 0 +OP4 E007C8 0 +OP4 E007C9 0 +OP4 E007CA 0 +OP4 E007CB 0 +OP4 E007CC 0 +OP4 E007CD 0 +OP4 E007CE 0 +OP4 E007CF 0 +OP4 E007D0 0 +OP4 E007D1 0 +OP4 E007D2 0 +OP4 E007D3 0 +OP4 E007D4 0 +OP4 E007D5 0 +OP4 E007D6 0 +OP4 E007D7 0 +OP4 E007D8 0 +OP4 E007D9 0 +OP4 E007DA 0 +OP4 E007DB 0 +OP4 E007DC 0 +OP4 E007DD 0 +OP4 E007DE 0 +OP4 E007DF 0 +OP4 E007E0 0 +OP4 E007E1 0 +OP4 E007E2 0 +OP4 E007E3 0 +OP4 E007E4 0 +OP4 E007E5 0 +OP4 E007E6 0 +OP4 E007E7 0 +OP4 E007E8 0 +OP4 E007E9 0 +OP4 E007EA 0 +OP4 E007EB 0 +OP4 E007EC 0 +OP4 E007ED 0 +OP4 E007EE 0 +OP4 E007EF 0 +OP4 E007F0 0 +OP4 E007F1 0 +OP4 E007F2 0 +OP4 E007F3 0 +OP4 E007F4 0 +OP4 E007F5 0 +OP4 E007F6 0 +OP4 E007F7 0 +OP4 E007F8 0 +OP4 E007F9 0 +OP4 E007FA 0 +OP4 E007FB 0 +OP4 E007FC 0 +OP4 E007FD 0 +OP4 E007FE 0 +OP4 E007FF 0 +OP4 E00800 0 +OP4 E00801 0 +OP4 E00802 0 +OP4 E00803 0 +OP4 E00804 0 +OP4 E00805 0 +OP4 E00806 0 +OP4 E00807 0 +OP4 E00808 0 +OP4 E00809 0 +OP4 E0080A 0 +OP4 E0080B 0 +OP4 E0080C 0 +OP4 E0080D 0 +OP4 E0080E 0 +OP4 E0080F 0 +OP4 E00810 0 +OP4 E00811 0 +OP4 E00812 0 +OP4 E00813 0 +OP4 E00814 0 +OP4 E00815 0 +OP4 E00816 0 +OP4 E00817 0 +OP4 E00818 0 +OP4 E00819 0 +OP4 E0081A 0 +OP4 E0081B 0 +OP4 E0081C 0 +OP4 E0081D 0 +OP4 E0081E 0 +OP4 E0081F 0 +OP4 E00820 0 +OP4 E00821 0 +OP4 E00822 0 +OP4 E00823 0 +OP4 E00824 0 +OP4 E00825 0 +OP4 E00826 0 +OP4 E00827 0 +OP4 E00828 0 +OP4 E00829 0 +OP4 E0082A 0 +OP4 E0082B 0 +OP4 E0082C 0 +OP4 E0082D 0 +OP4 E0082E 0 +OP4 E0082F 0 +OP4 E00830 0 +OP4 E00831 0 +OP4 E00832 0 +OP4 E00833 0 +OP4 E00834 0 +OP4 E00835 0 +OP4 E00836 0 +OP4 E00837 0 +OP4 E00838 0 +OP4 E00839 0 +OP4 E0083A 0 +OP4 E0083B 0 +OP4 E0083C 0 +OP4 E0083D 0 +OP4 E0083E 0 +OP4 E0083F 0 +OP4 E00840 0 +OP4 E00841 0 +OP4 E00842 0 +OP4 E00843 0 +OP4 E00844 0 +OP4 E00845 0 +OP4 E00846 0 +OP4 E00847 0 +OP4 E00848 0 +OP4 E00849 0 +OP4 E0084A 0 +OP4 E0084B 0 +OP4 E0084C 0 +OP4 E0084D 0 +OP4 E0084E 0 +OP4 E0084F 0 +OP4 E00850 0 +OP4 E00851 0 +OP4 E00852 0 +OP4 E00853 0 +OP4 E00854 0 +OP4 E00855 0 +OP4 E00856 0 +OP4 E00857 0 +OP4 E00858 0 +OP4 E00859 0 +OP4 E0085A 0 +OP4 E0085B 0 +OP4 E0085C 0 +OP4 E0085D 0 +OP4 E0085E 0 +OP4 E0085F 0 +OP4 E00860 0 +OP4 E00861 0 +OP4 E00862 0 +OP4 E00863 0 +OP4 E00864 0 +OP4 E00865 0 +OP4 E00866 0 +OP4 E00867 0 +OP4 E00868 0 +OP4 E00869 0 +OP4 E0086A 0 +OP4 E0086B 0 +OP4 E0086C 0 +OP4 E0086D 0 +OP4 E0086E 0 +OP4 E0086F 0 +OP4 E00870 0 +OP4 E00871 0 +OP4 E00872 0 +OP4 E00873 0 +OP4 E00874 0 +OP4 E00875 0 +OP4 E00876 0 +OP4 E00877 0 +OP4 E00878 0 +OP4 E00879 0 +OP4 E0087A 0 +OP4 E0087B 0 +OP4 E0087C 0 +OP4 E0087D 0 +OP4 E0087E 0 +OP4 E0087F 0 +OP4 E00880 0 +OP4 E00881 0 +OP4 E00882 0 +OP4 E00883 0 +OP4 E00884 0 +OP4 E00885 0 +OP4 E00886 0 +OP4 E00887 0 +OP4 E00888 0 +OP4 E00889 0 +OP4 E0088A 0 +OP4 E0088B 0 +OP4 E0088C 0 +OP4 E0088D 0 +OP4 E0088E 0 +OP4 E0088F 0 +OP4 E00890 0 +OP4 E00891 0 +OP4 E00892 0 +OP4 E00893 0 +OP4 E00894 0 +OP4 E00895 0 +OP4 E00896 0 +OP4 E00897 0 +OP4 E00898 0 +OP4 E00899 0 +OP4 E0089A 0 +OP4 E0089B 0 +OP4 E0089C 0 +OP4 E0089D 0 +OP4 E0089E 0 +OP4 E0089F 0 +OP4 E008A0 0 +OP4 E008A1 0 +OP4 E008A2 0 +OP4 E008A3 0 +OP4 E008A4 0 +OP4 E008A5 0 +OP4 E008A6 0 +OP4 E008A7 0 +OP4 E008A8 0 +OP4 E008A9 0 +OP4 E008AA 0 +OP4 E008AB 0 +OP4 E008AC 0 +OP4 E008AD 0 +OP4 E008AE 0 +OP4 E008AF 0 +OP4 E008B0 0 +OP4 E008B1 0 +OP4 E008B2 0 +OP4 E008B3 0 +OP4 E008B4 0 +OP4 E008B5 0 +OP4 E008B6 0 +OP4 E008B7 0 +OP4 E008B8 0 +OP4 E008B9 0 +OP4 E008BA 0 +OP4 E008BB 0 +OP4 E008BC 0 +OP4 E008BD 0 +OP4 E008BE 0 +OP4 E008BF 0 +OP4 E008C0 0 +OP4 E008C1 0 +OP4 E008C2 0 +OP4 E008C3 0 +OP4 E008C4 0 +OP4 E008C5 0 +OP4 E008C6 0 +OP4 E008C7 0 +OP4 E008C8 0 +OP4 E008C9 0 +OP4 E008CA 0 +OP4 E008CB 0 +OP4 E008CC 0 +OP4 E008CD 0 +OP4 E008CE 0 +OP4 E008CF 0 +OP4 E008D0 0 +OP4 E008D1 0 +OP4 E008D2 0 +OP4 E008D3 0 +OP4 E008D4 0 +OP4 E008D5 0 +OP4 E008D6 0 +OP4 E008D7 0 +OP4 E008D8 0 +OP4 E008D9 0 +OP4 E008DA 0 +OP4 E008DB 0 +OP4 E008DC 0 +OP4 E008DD 0 +OP4 E008DE 0 +OP4 E008DF 0 +OP4 E008E0 0 +OP4 E008E1 0 +OP4 E008E2 0 +OP4 E008E3 0 +OP4 E008E4 0 +OP4 E008E5 0 +OP4 E008E6 0 +OP4 E008E7 0 +OP4 E008E8 0 +OP4 E008E9 0 +OP4 E008EA 0 +OP4 E008EB 0 +OP4 E008EC 0 +OP4 E008ED 0 +OP4 E008EE 0 +OP4 E008EF 0 +OP4 E008F0 0 +OP4 E008F1 0 +OP4 E008F2 0 +OP4 E008F3 0 +OP4 E008F4 0 +OP4 E008F5 0 +OP4 E008F6 0 +OP4 E008F7 0 +OP4 E008F8 0 +OP4 E008F9 0 +OP4 E008FA 0 +OP4 E008FB 0 +OP4 E008FC 0 +OP4 E008FD 0 +OP4 E008FE 0 +OP4 E008FF 0 +OP4 E00900 0 +OP4 E00901 0 +OP4 E00902 0 +OP4 E00903 0 +OP4 E00904 0 +OP4 E00905 0 +OP4 E00906 0 +OP4 E00907 0 +OP4 E00908 0 +OP4 E00909 0 +OP4 E0090A 0 +OP4 E0090B 0 +OP4 E0090C 0 +OP4 E0090D 0 +OP4 E0090E 0 +OP4 E0090F 0 +OP4 E00910 0 +OP4 E00911 0 +OP4 E00912 0 +OP4 E00913 0 +OP4 E00914 0 +OP4 E00915 0 +OP4 E00916 0 +OP4 E00917 0 +OP4 E00918 0 +OP4 E00919 0 +OP4 E0091A 0 +OP4 E0091B 0 +OP4 E0091C 0 +OP4 E0091D 0 +OP4 E0091E 0 +OP4 E0091F 0 +OP4 E00920 0 +OP4 E00921 0 +OP4 E00922 0 +OP4 E00923 0 +OP4 E00924 0 +OP4 E00925 0 +OP4 E00926 0 +OP4 E00927 0 +OP4 E00928 0 +OP4 E00929 0 +OP4 E0092A 0 +OP4 E0092B 0 +OP4 E0092C 0 +OP4 E0092D 0 +OP4 E0092E 0 +OP4 E0092F 0 +OP4 E00930 0 +OP4 E00931 0 +OP4 E00932 0 +OP4 E00933 0 +OP4 E00934 0 +OP4 E00935 0 +OP4 E00936 0 +OP4 E00937 0 +OP4 E00938 0 +OP4 E00939 0 +OP4 E0093A 0 +OP4 E0093B 0 +OP4 E0093C 0 +OP4 E0093D 0 +OP4 E0093E 0 +OP4 E0093F 0 +OP4 E00940 0 +OP4 E00941 0 +OP4 E00942 0 +OP4 E00943 0 +OP4 E00944 0 +OP4 E00945 0 +OP4 E00946 0 +OP4 E00947 0 +OP4 E00948 0 +OP4 E00949 0 +OP4 E0094A 0 +OP4 E0094B 0 +OP4 E0094C 0 +OP4 E0094D 0 +OP4 E0094E 0 +OP4 E0094F 0 +OP4 E00950 0 +OP4 E00951 0 +OP4 E00952 0 +OP4 E00953 0 +OP4 E00954 0 +OP4 E00955 0 +OP4 E00956 0 +OP4 E00957 0 +OP4 E00958 0 +OP4 E00959 0 +OP4 E0095A 0 +OP4 E0095B 0 +OP4 E0095C 0 +OP4 E0095D 0 +OP4 E0095E 0 +OP4 E0095F 0 +OP4 E00960 0 +OP4 E00961 0 +OP4 E00962 0 +OP4 E00963 0 +OP4 E00964 0 +OP4 E00965 0 +OP4 E00966 0 +OP4 E00967 0 +OP4 E00968 0 +OP4 E00969 0 +OP4 E0096A 0 +OP4 E0096B 0 +OP4 E0096C 0 +OP4 E0096D 0 +OP4 E0096E 0 +OP4 E0096F 0 +OP4 E00970 0 +OP4 E00971 0 +OP4 E00972 0 +OP4 E00973 0 +OP4 E00974 0 +OP4 E00975 0 +OP4 E00976 0 +OP4 E00977 0 +OP4 E00978 0 +OP4 E00979 0 +OP4 E0097A 0 +OP4 E0097B 0 +OP4 E0097C 0 +OP4 E0097D 0 +OP4 E0097E 0 +OP4 E0097F 0 +OP4 E00980 0 +OP4 E00981 0 +OP4 E00982 0 +OP4 E00983 0 +OP4 E00984 0 +OP4 E00985 0 +OP4 E00986 0 +OP4 E00987 0 +OP4 E00988 0 +OP4 E00989 0 +OP4 E0098A 0 +OP4 E0098B 0 +OP4 E0098C 0 +OP4 E0098D 0 +OP4 E0098E 0 +OP4 E0098F 0 +OP4 E00990 0 +OP4 E00991 0 +OP4 E00992 0 +OP4 E00993 0 +OP4 E00994 0 +OP4 E00995 0 +OP4 E00996 0 +OP4 E00997 0 +OP4 E00998 0 +OP4 E00999 0 +OP4 E0099A 0 +OP4 E0099B 0 +OP4 E0099C 0 +OP4 E0099D 0 +OP4 E0099E 0 +OP4 E0099F 0 +OP4 E009A0 0 +OP4 E009A1 0 +OP4 E009A2 0 +OP4 E009A3 0 +OP4 E009A4 0 +OP4 E009A5 0 +OP4 E009A6 0 +OP4 E009A7 0 +OP4 E009A8 0 +OP4 E009A9 0 +OP4 E009AA 0 +OP4 E009AB 0 +OP4 E009AC 0 +OP4 E009AD 0 +OP4 E009AE 0 +OP4 E009AF 0 +OP4 E009B0 0 +OP4 E009B1 0 +OP4 E009B2 0 +OP4 E009B3 0 +OP4 E009B4 0 +OP4 E009B5 0 +OP4 E009B6 0 +OP4 E009B7 0 +OP4 E009B8 0 +OP4 E009B9 0 +OP4 E009BA 0 +OP4 E009BB 0 +OP4 E009BC 0 +OP4 E009BD 0 +OP4 E009BE 0 +OP4 E009BF 0 +OP4 E009C0 0 +OP4 E009C1 0 +OP4 E009C2 0 +OP4 E009C3 0 +OP4 E009C4 0 +OP4 E009C5 0 +OP4 E009C6 0 +OP4 E009C7 0 +OP4 E009C8 0 +OP4 E009C9 0 +OP4 E009CA 0 +OP4 E009CB 0 +OP4 E009CC 0 +OP4 E009CD 0 +OP4 E009CE 0 +OP4 E009CF 0 +OP4 E009D0 0 +OP4 E009D1 0 +OP4 E009D2 0 +OP4 E009D3 0 +OP4 E009D4 0 +OP4 E009D5 0 +OP4 E009D6 0 +OP4 E009D7 0 +OP4 E009D8 0 +OP4 E009D9 0 +OP4 E009DA 0 +OP4 E009DB 0 +OP4 E009DC 0 +OP4 E009DD 0 +OP4 E009DE 0 +OP4 E009DF 0 +OP4 E009E0 0 +OP4 E009E1 0 +OP4 E009E2 0 +OP4 E009E3 0 +OP4 E009E4 0 +OP4 E009E5 0 +OP4 E009E6 0 +OP4 E009E7 0 +OP4 E009E8 0 +OP4 E009E9 0 +OP4 E009EA 0 +OP4 E009EB 0 +OP4 E009EC 0 +OP4 E009ED 0 +OP4 E009EE 0 +OP4 E009EF 0 +OP4 E009F0 0 +OP4 E009F1 0 +OP4 E009F2 0 +OP4 E009F3 0 +OP4 E009F4 0 +OP4 E009F5 0 +OP4 E009F6 0 +OP4 E009F7 0 +OP4 E009F8 0 +OP4 E009F9 0 +OP4 E009FA 0 +OP4 E009FB 0 +OP4 E009FC 0 +OP4 E009FD 0 +OP4 E009FE 0 +OP4 E009FF 0 +OP4 E00A00 0 +OP4 E00A01 0 +OP4 E00A02 0 +OP4 E00A03 0 +OP4 E00A04 0 +OP4 E00A05 0 +OP4 E00A06 0 +OP4 E00A07 0 +OP4 E00A08 0 +OP4 E00A09 0 +OP4 E00A0A 0 +OP4 E00A0B 0 +OP4 E00A0C 0 +OP4 E00A0D 0 +OP4 E00A0E 0 +OP4 E00A0F 0 +OP4 E00A10 0 +OP4 E00A11 0 +OP4 E00A12 0 +OP4 E00A13 0 +OP4 E00A14 0 +OP4 E00A15 0 +OP4 E00A16 0 +OP4 E00A17 0 +OP4 E00A18 0 +OP4 E00A19 0 +OP4 E00A1A 0 +OP4 E00A1B 0 +OP4 E00A1C 0 +OP4 E00A1D 0 +OP4 E00A1E 0 +OP4 E00A1F 0 +OP4 E00A20 0 +OP4 E00A21 0 +OP4 E00A22 0 +OP4 E00A23 0 +OP4 E00A24 0 +OP4 E00A25 0 +OP4 E00A26 0 +OP4 E00A27 0 +OP4 E00A28 0 +OP4 E00A29 0 +OP4 E00A2A 0 +OP4 E00A2B 0 +OP4 E00A2C 0 +OP4 E00A2D 0 +OP4 E00A2E 0 +OP4 E00A2F 0 +OP4 E00A30 0 +OP4 E00A31 0 +OP4 E00A32 0 +OP4 E00A33 0 +OP4 E00A34 0 +OP4 E00A35 0 +OP4 E00A36 0 +OP4 E00A37 0 +OP4 E00A38 0 +OP4 E00A39 0 +OP4 E00A3A 0 +OP4 E00A3B 0 +OP4 E00A3C 0 +OP4 E00A3D 0 +OP4 E00A3E 0 +OP4 E00A3F 0 +OP4 E00A40 0 +OP4 E00A41 0 +OP4 E00A42 0 +OP4 E00A43 0 +OP4 E00A44 0 +OP4 E00A45 0 +OP4 E00A46 0 +OP4 E00A47 0 +OP4 E00A48 0 +OP4 E00A49 0 +OP4 E00A4A 0 +OP4 E00A4B 0 +OP4 E00A4C 0 +OP4 E00A4D 0 +OP4 E00A4E 0 +OP4 E00A4F 0 +OP4 E00A50 0 +OP4 E00A51 0 +OP4 E00A52 0 +OP4 E00A53 0 +OP4 E00A54 0 +OP4 E00A55 0 +OP4 E00A56 0 +OP4 E00A57 0 +OP4 E00A58 0 +OP4 E00A59 0 +OP4 E00A5A 0 +OP4 E00A5B 0 +OP4 E00A5C 0 +OP4 E00A5D 0 +OP4 E00A5E 0 +OP4 E00A5F 0 +OP4 E00A60 0 +OP4 E00A61 0 +OP4 E00A62 0 +OP4 E00A63 0 +OP4 E00A64 0 +OP4 E00A65 0 +OP4 E00A66 0 +OP4 E00A67 0 +OP4 E00A68 0 +OP4 E00A69 0 +OP4 E00A6A 0 +OP4 E00A6B 0 +OP4 E00A6C 0 +OP4 E00A6D 0 +OP4 E00A6E 0 +OP4 E00A6F 0 +OP4 E00A70 0 +OP4 E00A71 0 +OP4 E00A72 0 +OP4 E00A73 0 +OP4 E00A74 0 +OP4 E00A75 0 +OP4 E00A76 0 +OP4 E00A77 0 +OP4 E00A78 0 +OP4 E00A79 0 +OP4 E00A7A 0 +OP4 E00A7B 0 +OP4 E00A7C 0 +OP4 E00A7D 0 +OP4 E00A7E 0 +OP4 E00A7F 0 +OP4 E00A80 0 +OP4 E00A81 0 +OP4 E00A82 0 +OP4 E00A83 0 +OP4 E00A84 0 +OP4 E00A85 0 +OP4 E00A86 0 +OP4 E00A87 0 +OP4 E00A88 0 +OP4 E00A89 0 +OP4 E00A8A 0 +OP4 E00A8B 0 +OP4 E00A8C 0 +OP4 E00A8D 0 +OP4 E00A8E 0 +OP4 E00A8F 0 +OP4 E00A90 0 +OP4 E00A91 0 +OP4 E00A92 0 +OP4 E00A93 0 +OP4 E00A94 0 +OP4 E00A95 0 +OP4 E00A96 0 +OP4 E00A97 0 +OP4 E00A98 0 +OP4 E00A99 0 +OP4 E00A9A 0 +OP4 E00A9B 0 +OP4 E00A9C 0 +OP4 E00A9D 0 +OP4 E00A9E 0 +OP4 E00A9F 0 +OP4 E00AA0 0 +OP4 E00AA1 0 +OP4 E00AA2 0 +OP4 E00AA3 0 +OP4 E00AA4 0 +OP4 E00AA5 0 +OP4 E00AA6 0 +OP4 E00AA7 0 +OP4 E00AA8 0 +OP4 E00AA9 0 +OP4 E00AAA 0 +OP4 E00AAB 0 +OP4 E00AAC 0 +OP4 E00AAD 0 +OP4 E00AAE 0 +OP4 E00AAF 0 +OP4 E00AB0 0 +OP4 E00AB1 0 +OP4 E00AB2 0 +OP4 E00AB3 0 +OP4 E00AB4 0 +OP4 E00AB5 0 +OP4 E00AB6 0 +OP4 E00AB7 0 +OP4 E00AB8 0 +OP4 E00AB9 0 +OP4 E00ABA 0 +OP4 E00ABB 0 +OP4 E00ABC 0 +OP4 E00ABD 0 +OP4 E00ABE 0 +OP4 E00ABF 0 +OP4 E00AC0 0 +OP4 E00AC1 0 +OP4 E00AC2 0 +OP4 E00AC3 0 +OP4 E00AC4 0 +OP4 E00AC5 0 +OP4 E00AC6 0 +OP4 E00AC7 0 +OP4 E00AC8 0 +OP4 E00AC9 0 +OP4 E00ACA 0 +OP4 E00ACB 0 +OP4 E00ACC 0 +OP4 E00ACD 0 +OP4 E00ACE 0 +OP4 E00ACF 0 +OP4 E00AD0 0 +OP4 E00AD1 0 +OP4 E00AD2 0 +OP4 E00AD3 0 +OP4 E00AD4 0 +OP4 E00AD5 0 +OP4 E00AD6 0 +OP4 E00AD7 0 +OP4 E00AD8 0 +OP4 E00AD9 0 +OP4 E00ADA 0 +OP4 E00ADB 0 +OP4 E00ADC 0 +OP4 E00ADD 0 +OP4 E00ADE 0 +OP4 E00ADF 0 +OP4 E00AE0 0 +OP4 E00AE1 0 +OP4 E00AE2 0 +OP4 E00AE3 0 +OP4 E00AE4 0 +OP4 E00AE5 0 +OP4 E00AE6 0 +OP4 E00AE7 0 +OP4 E00AE8 0 +OP4 E00AE9 0 +OP4 E00AEA 0 +OP4 E00AEB 0 +OP4 E00AEC 0 +OP4 E00AED 0 +OP4 E00AEE 0 +OP4 E00AEF 0 +OP4 E00AF0 0 +OP4 E00AF1 0 +OP4 E00AF2 0 +OP4 E00AF3 0 +OP4 E00AF4 0 +OP4 E00AF5 0 +OP4 E00AF6 0 +OP4 E00AF7 0 +OP4 E00AF8 0 +OP4 E00AF9 0 +OP4 E00AFA 0 +OP4 E00AFB 0 +OP4 E00AFC 0 +OP4 E00AFD 0 +OP4 E00AFE 0 +OP4 E00AFF 0 +OP4 E00B00 0 +OP4 E00B01 0 +OP4 E00B02 0 +OP4 E00B03 0 +OP4 E00B04 0 +OP4 E00B05 0 +OP4 E00B06 0 +OP4 E00B07 0 +OP4 E00B08 0 +OP4 E00B09 0 +OP4 E00B0A 0 +OP4 E00B0B 0 +OP4 E00B0C 0 +OP4 E00B0D 0 +OP4 E00B0E 0 +OP4 E00B0F 0 +OP4 E00B10 0 +OP4 E00B11 0 +OP4 E00B12 0 +OP4 E00B13 0 +OP4 E00B14 0 +OP4 E00B15 0 +OP4 E00B16 0 +OP4 E00B17 0 +OP4 E00B18 0 +OP4 E00B19 0 +OP4 E00B1A 0 +OP4 E00B1B 0 +OP4 E00B1C 0 +OP4 E00B1D 0 +OP4 E00B1E 0 +OP4 E00B1F 0 +OP4 E00B20 0 +OP4 E00B21 0 +OP4 E00B22 0 +OP4 E00B23 0 +OP4 E00B24 0 +OP4 E00B25 0 +OP4 E00B26 0 +OP4 E00B27 0 +OP4 E00B28 0 +OP4 E00B29 0 +OP4 E00B2A 0 +OP4 E00B2B 0 +OP4 E00B2C 0 +OP4 E00B2D 0 +OP4 E00B2E 0 +OP4 E00B2F 0 +OP4 E00B30 0 +OP4 E00B31 0 +OP4 E00B32 0 +OP4 E00B33 0 +OP4 E00B34 0 +OP4 E00B35 0 +OP4 E00B36 0 +OP4 E00B37 0 +OP4 E00B38 0 +OP4 E00B39 0 +OP4 E00B3A 0 +OP4 E00B3B 0 +OP4 E00B3C 0 +OP4 E00B3D 0 +OP4 E00B3E 0 +OP4 E00B3F 0 +OP4 E00B40 0 +OP4 E00B41 0 +OP4 E00B42 0 +OP4 E00B43 0 +OP4 E00B44 0 +OP4 E00B45 0 +OP4 E00B46 0 +OP4 E00B47 0 +OP4 E00B48 0 +OP4 E00B49 0 +OP4 E00B4A 0 +OP4 E00B4B 0 +OP4 E00B4C 0 +OP4 E00B4D 0 +OP4 E00B4E 0 +OP4 E00B4F 0 +OP4 E00B50 0 +OP4 E00B51 0 +OP4 E00B52 0 +OP4 E00B53 0 +OP4 E00B54 0 +OP4 E00B55 0 +OP4 E00B56 0 +OP4 E00B57 0 +OP4 E00B58 0 +OP4 E00B59 0 +OP4 E00B5A 0 +OP4 E00B5B 0 +OP4 E00B5C 0 +OP4 E00B5D 0 +OP4 E00B5E 0 +OP4 E00B5F 0 +OP4 E00B60 0 +OP4 E00B61 0 +OP4 E00B62 0 +OP4 E00B63 0 +OP4 E00B64 0 +OP4 E00B65 0 +OP4 E00B66 0 +OP4 E00B67 0 +OP4 E00B68 0 +OP4 E00B69 0 +OP4 E00B6A 0 +OP4 E00B6B 0 +OP4 E00B6C 0 +OP4 E00B6D 0 +OP4 E00B6E 0 +OP4 E00B6F 0 +OP4 E00B70 0 +OP4 E00B71 0 +OP4 E00B72 0 +OP4 E00B73 0 +OP4 E00B74 0 +OP4 E00B75 0 +OP4 E00B76 0 +OP4 E00B77 0 +OP4 E00B78 0 +OP4 E00B79 0 +OP4 E00B7A 0 +OP4 E00B7B 0 +OP4 E00B7C 0 +OP4 E00B7D 0 +OP4 E00B7E 0 +OP4 E00B7F 0 +OP4 E00B80 0 +OP4 E00B81 0 +OP4 E00B82 0 +OP4 E00B83 0 +OP4 E00B84 0 +OP4 E00B85 0 +OP4 E00B86 0 +OP4 E00B87 0 +OP4 E00B88 0 +OP4 E00B89 0 +OP4 E00B8A 0 +OP4 E00B8B 0 +OP4 E00B8C 0 +OP4 E00B8D 0 +OP4 E00B8E 0 +OP4 E00B8F 0 +OP4 E00B90 0 +OP4 E00B91 0 +OP4 E00B92 0 +OP4 E00B93 0 +OP4 E00B94 0 +OP4 E00B95 0 +OP4 E00B96 0 +OP4 E00B97 0 +OP4 E00B98 0 +OP4 E00B99 0 +OP4 E00B9A 0 +OP4 E00B9B 0 +OP4 E00B9C 0 +OP4 E00B9D 0 +OP4 E00B9E 0 +OP4 E00B9F 0 +OP4 E00BA0 0 +OP4 E00BA1 0 +OP4 E00BA2 0 +OP4 E00BA3 0 +OP4 E00BA4 0 +OP4 E00BA5 0 +OP4 E00BA6 0 +OP4 E00BA7 0 +OP4 E00BA8 0 +OP4 E00BA9 0 +OP4 E00BAA 0 +OP4 E00BAB 0 +OP4 E00BAC 0 +OP4 E00BAD 0 +OP4 E00BAE 0 +OP4 E00BAF 0 +OP4 E00BB0 0 +OP4 E00BB1 0 +OP4 E00BB2 0 +OP4 E00BB3 0 +OP4 E00BB4 0 +OP4 E00BB5 0 +OP4 E00BB6 0 +OP4 E00BB7 0 +OP4 E00BB8 0 +OP4 E00BB9 0 +OP4 E00BBA 0 +OP4 E00BBB 0 +OP4 E00BBC 0 +OP4 E00BBD 0 +OP4 E00BBE 0 +OP4 E00BBF 0 +OP4 E00BC0 0 +OP4 E00BC1 0 +OP4 E00BC2 0 +OP4 E00BC3 0 +OP4 E00BC4 0 +OP4 E00BC5 0 +OP4 E00BC6 0 +OP4 E00BC7 0 +OP4 E00BC8 0 +OP4 E00BC9 0 +OP4 E00BCA 0 +OP4 E00BCB 0 +OP4 E00BCC 0 +OP4 E00BCD 0 +OP4 E00BCE 0 +OP4 E00BCF 0 +OP4 E00BD0 0 +OP4 E00BD1 0 +OP4 E00BD2 0 +OP4 E00BD3 0 +OP4 E00BD4 0 +OP4 E00BD5 0 +OP4 E00BD6 0 +OP4 E00BD7 0 +OP4 E00BD8 0 +OP4 E00BD9 0 +OP4 E00BDA 0 +OP4 E00BDB 0 +OP4 E00BDC 0 +OP4 E00BDD 0 +OP4 E00BDE 0 +OP4 E00BDF 0 +OP4 E00BE0 0 +OP4 E00BE1 0 +OP4 E00BE2 0 +OP4 E00BE3 0 +OP4 E00BE4 0 +OP4 E00BE5 0 +OP4 E00BE6 0 +OP4 E00BE7 0 +OP4 E00BE8 0 +OP4 E00BE9 0 +OP4 E00BEA 0 +OP4 E00BEB 0 +OP4 E00BEC 0 +OP4 E00BED 0 +OP4 E00BEE 0 +OP4 E00BEF 0 +OP4 E00BF0 0 +OP4 E00BF1 0 +OP4 E00BF2 0 +OP4 E00BF3 0 +OP4 E00BF4 0 +OP4 E00BF5 0 +OP4 E00BF6 0 +OP4 E00BF7 0 +OP4 E00BF8 0 +OP4 E00BF9 0 +OP4 E00BFA 0 +OP4 E00BFB 0 +OP4 E00BFC 0 +OP4 E00BFD 0 +OP4 E00BFE 0 +OP4 E00BFF 0 +OP4 E00C00 0 +OP4 E00C01 0 +OP4 E00C02 0 +OP4 E00C03 0 +OP4 E00C04 0 +OP4 E00C05 0 +OP4 E00C06 0 +OP4 E00C07 0 +OP4 E00C08 0 +OP4 E00C09 0 +OP4 E00C0A 0 +OP4 E00C0B 0 +OP4 E00C0C 0 +OP4 E00C0D 0 +OP4 E00C0E 0 +OP4 E00C0F 0 +OP4 E00C10 0 +OP4 E00C11 0 +OP4 E00C12 0 +OP4 E00C13 0 +OP4 E00C14 0 +OP4 E00C15 0 +OP4 E00C16 0 +OP4 E00C17 0 +OP4 E00C18 0 +OP4 E00C19 0 +OP4 E00C1A 0 +OP4 E00C1B 0 +OP4 E00C1C 0 +OP4 E00C1D 0 +OP4 E00C1E 0 +OP4 E00C1F 0 +OP4 E00C20 0 +OP4 E00C21 0 +OP4 E00C22 0 +OP4 E00C23 0 +OP4 E00C24 0 +OP4 E00C25 0 +OP4 E00C26 0 +OP4 E00C27 0 +OP4 E00C28 0 +OP4 E00C29 0 +OP4 E00C2A 0 +OP4 E00C2B 0 +OP4 E00C2C 0 +OP4 E00C2D 0 +OP4 E00C2E 0 +OP4 E00C2F 0 +OP4 E00C30 0 +OP4 E00C31 0 +OP4 E00C32 0 +OP4 E00C33 0 +OP4 E00C34 0 +OP4 E00C35 0 +OP4 E00C36 0 +OP4 E00C37 0 +OP4 E00C38 0 +OP4 E00C39 0 +OP4 E00C3A 0 +OP4 E00C3B 0 +OP4 E00C3C 0 +OP4 E00C3D 0 +OP4 E00C3E 0 +OP4 E00C3F 0 +OP4 E00C40 0 +OP4 E00C41 0 +OP4 E00C42 0 +OP4 E00C43 0 +OP4 E00C44 0 +OP4 E00C45 0 +OP4 E00C46 0 +OP4 E00C47 0 +OP4 E00C48 0 +OP4 E00C49 0 +OP4 E00C4A 0 +OP4 E00C4B 0 +OP4 E00C4C 0 +OP4 E00C4D 0 +OP4 E00C4E 0 +OP4 E00C4F 0 +OP4 E00C50 0 +OP4 E00C51 0 +OP4 E00C52 0 +OP4 E00C53 0 +OP4 E00C54 0 +OP4 E00C55 0 +OP4 E00C56 0 +OP4 E00C57 0 +OP4 E00C58 0 +OP4 E00C59 0 +OP4 E00C5A 0 +OP4 E00C5B 0 +OP4 E00C5C 0 +OP4 E00C5D 0 +OP4 E00C5E 0 +OP4 E00C5F 0 +OP4 E00C60 0 +OP4 E00C61 0 +OP4 E00C62 0 +OP4 E00C63 0 +OP4 E00C64 0 +OP4 E00C65 0 +OP4 E00C66 0 +OP4 E00C67 0 +OP4 E00C68 0 +OP4 E00C69 0 +OP4 E00C6A 0 +OP4 E00C6B 0 +OP4 E00C6C 0 +OP4 E00C6D 0 +OP4 E00C6E 0 +OP4 E00C6F 0 +OP4 E00C70 0 +OP4 E00C71 0 +OP4 E00C72 0 +OP4 E00C73 0 +OP4 E00C74 0 +OP4 E00C75 0 +OP4 E00C76 0 +OP4 E00C77 0 +OP4 E00C78 0 +OP4 E00C79 0 +OP4 E00C7A 0 +OP4 E00C7B 0 +OP4 E00C7C 0 +OP4 E00C7D 0 +OP4 E00C7E 0 +OP4 E00C7F 0 +OP4 E00C80 0 +OP4 E00C81 0 +OP4 E00C82 0 +OP4 E00C83 0 +OP4 E00C84 0 +OP4 E00C85 0 +OP4 E00C86 0 +OP4 E00C87 0 +OP4 E00C88 0 +OP4 E00C89 0 +OP4 E00C8A 0 +OP4 E00C8B 0 +OP4 E00C8C 0 +OP4 E00C8D 0 +OP4 E00C8E 0 +OP4 E00C8F 0 +OP4 E00C90 0 +OP4 E00C91 0 +OP4 E00C92 0 +OP4 E00C93 0 +OP4 E00C94 0 +OP4 E00C95 0 +OP4 E00C96 0 +OP4 E00C97 0 +OP4 E00C98 0 +OP4 E00C99 0 +OP4 E00C9A 0 +OP4 E00C9B 0 +OP4 E00C9C 0 +OP4 E00C9D 0 +OP4 E00C9E 0 +OP4 E00C9F 0 +OP4 E00CA0 0 +OP4 E00CA1 0 +OP4 E00CA2 0 +OP4 E00CA3 0 +OP4 E00CA4 0 +OP4 E00CA5 0 +OP4 E00CA6 0 +OP4 E00CA7 0 +OP4 E00CA8 0 +OP4 E00CA9 0 +OP4 E00CAA 0 +OP4 E00CAB 0 +OP4 E00CAC 0 +OP4 E00CAD 0 +OP4 E00CAE 0 +OP4 E00CAF 0 +OP4 E00CB0 0 +OP4 E00CB1 0 +OP4 E00CB2 0 +OP4 E00CB3 0 +OP4 E00CB4 0 +OP4 E00CB5 0 +OP4 E00CB6 0 +OP4 E00CB7 0 +OP4 E00CB8 0 +OP4 E00CB9 0 +OP4 E00CBA 0 +OP4 E00CBB 0 +OP4 E00CBC 0 +OP4 E00CBD 0 +OP4 E00CBE 0 +OP4 E00CBF 0 +OP4 E00CC0 0 +OP4 E00CC1 0 +OP4 E00CC2 0 +OP4 E00CC3 0 +OP4 E00CC4 0 +OP4 E00CC5 0 +OP4 E00CC6 0 +OP4 E00CC7 0 +OP4 E00CC8 0 +OP4 E00CC9 0 +OP4 E00CCA 0 +OP4 E00CCB 0 +OP4 E00CCC 0 +OP4 E00CCD 0 +OP4 E00CCE 0 +OP4 E00CCF 0 +OP4 E00CD0 0 +OP4 E00CD1 0 +OP4 E00CD2 0 +OP4 E00CD3 0 +OP4 E00CD4 0 +OP4 E00CD5 0 +OP4 E00CD6 0 +OP4 E00CD7 0 +OP4 E00CD8 0 +OP4 E00CD9 0 +OP4 E00CDA 0 +OP4 E00CDB 0 +OP4 E00CDC 0 +OP4 E00CDD 0 +OP4 E00CDE 0 +OP4 E00CDF 0 +OP4 E00CE0 0 +OP4 E00CE1 0 +OP4 E00CE2 0 +OP4 E00CE3 0 +OP4 E00CE4 0 +OP4 E00CE5 0 +OP4 E00CE6 0 +OP4 E00CE7 0 +OP4 E00CE8 0 +OP4 E00CE9 0 +OP4 E00CEA 0 +OP4 E00CEB 0 +OP4 E00CEC 0 +OP4 E00CED 0 +OP4 E00CEE 0 +OP4 E00CEF 0 +OP4 E00CF0 0 +OP4 E00CF1 0 +OP4 E00CF2 0 +OP4 E00CF3 0 +OP4 E00CF4 0 +OP4 E00CF5 0 +OP4 E00CF6 0 +OP4 E00CF7 0 +OP4 E00CF8 0 +OP4 E00CF9 0 +OP4 E00CFA 0 +OP4 E00CFB 0 +OP4 E00CFC 0 +OP4 E00CFD 0 +OP4 E00CFE 0 +OP4 E00CFF 0 +OP4 E00D00 0 +OP4 E00D01 0 +OP4 E00D02 0 +OP4 E00D03 0 +OP4 E00D04 0 +OP4 E00D05 0 +OP4 E00D06 0 +OP4 E00D07 0 +OP4 E00D08 0 +OP4 E00D09 0 +OP4 E00D0A 0 +OP4 E00D0B 0 +OP4 E00D0C 0 +OP4 E00D0D 0 +OP4 E00D0E 0 +OP4 E00D0F 0 +OP4 E00D10 0 +OP4 E00D11 0 +OP4 E00D12 0 +OP4 E00D13 0 +OP4 E00D14 0 +OP4 E00D15 0 +OP4 E00D16 0 +OP4 E00D17 0 +OP4 E00D18 0 +OP4 E00D19 0 +OP4 E00D1A 0 +OP4 E00D1B 0 +OP4 E00D1C 0 +OP4 E00D1D 0 +OP4 E00D1E 0 +OP4 E00D1F 0 +OP4 E00D20 0 +OP4 E00D21 0 +OP4 E00D22 0 +OP4 E00D23 0 +OP4 E00D24 0 +OP4 E00D25 0 +OP4 E00D26 0 +OP4 E00D27 0 +OP4 E00D28 0 +OP4 E00D29 0 +OP4 E00D2A 0 +OP4 E00D2B 0 +OP4 E00D2C 0 +OP4 E00D2D 0 +OP4 E00D2E 0 +OP4 E00D2F 0 +OP4 E00D30 0 +OP4 E00D31 0 +OP4 E00D32 0 +OP4 E00D33 0 +OP4 E00D34 0 +OP4 E00D35 0 +OP4 E00D36 0 +OP4 E00D37 0 +OP4 E00D38 0 +OP4 E00D39 0 +OP4 E00D3A 0 +OP4 E00D3B 0 +OP4 E00D3C 0 +OP4 E00D3D 0 +OP4 E00D3E 0 +OP4 E00D3F 0 +OP4 E00D40 0 +OP4 E00D41 0 +OP4 E00D42 0 +OP4 E00D43 0 +OP4 E00D44 0 +OP4 E00D45 0 +OP4 E00D46 0 +OP4 E00D47 0 +OP4 E00D48 0 +OP4 E00D49 0 +OP4 E00D4A 0 +OP4 E00D4B 0 +OP4 E00D4C 0 +OP4 E00D4D 0 +OP4 E00D4E 0 +OP4 E00D4F 0 +OP4 E00D50 0 +OP4 E00D51 0 +OP4 E00D52 0 +OP4 E00D53 0 +OP4 E00D54 0 +OP4 E00D55 0 +OP4 E00D56 0 +OP4 E00D57 0 +OP4 E00D58 0 +OP4 E00D59 0 +OP4 E00D5A 0 +OP4 E00D5B 0 +OP4 E00D5C 0 +OP4 E00D5D 0 +OP4 E00D5E 0 +OP4 E00D5F 0 +OP4 E00D60 0 +OP4 E00D61 0 +OP4 E00D62 0 +OP4 E00D63 0 +OP4 E00D64 0 +OP4 E00D65 0 +OP4 E00D66 0 +OP4 E00D67 0 +OP4 E00D68 0 +OP4 E00D69 0 +OP4 E00D6A 0 +OP4 E00D6B 0 +OP4 E00D6C 0 +OP4 E00D6D 0 +OP4 E00D6E 0 +OP4 E00D6F 0 +OP4 E00D70 0 +OP4 E00D71 0 +OP4 E00D72 0 +OP4 E00D73 0 +OP4 E00D74 0 +OP4 E00D75 0 +OP4 E00D76 0 +OP4 E00D77 0 +OP4 E00D78 0 +OP4 E00D79 0 +OP4 E00D7A 0 +OP4 E00D7B 0 +OP4 E00D7C 0 +OP4 E00D7D 0 +OP4 E00D7E 0 +OP4 E00D7F 0 +OP4 E00D80 0 +OP4 E00D81 0 +OP4 E00D82 0 +OP4 E00D83 0 +OP4 E00D84 0 +OP4 E00D85 0 +OP4 E00D86 0 +OP4 E00D87 0 +OP4 E00D88 0 +OP4 E00D89 0 +OP4 E00D8A 0 +OP4 E00D8B 0 +OP4 E00D8C 0 +OP4 E00D8D 0 +OP4 E00D8E 0 +OP4 E00D8F 0 +OP4 E00D90 0 +OP4 E00D91 0 +OP4 E00D92 0 +OP4 E00D93 0 +OP4 E00D94 0 +OP4 E00D95 0 +OP4 E00D96 0 +OP4 E00D97 0 +OP4 E00D98 0 +OP4 E00D99 0 +OP4 E00D9A 0 +OP4 E00D9B 0 +OP4 E00D9C 0 +OP4 E00D9D 0 +OP4 E00D9E 0 +OP4 E00D9F 0 +OP4 E00DA0 0 +OP4 E00DA1 0 +OP4 E00DA2 0 +OP4 E00DA3 0 +OP4 E00DA4 0 +OP4 E00DA5 0 +OP4 E00DA6 0 +OP4 E00DA7 0 +OP4 E00DA8 0 +OP4 E00DA9 0 +OP4 E00DAA 0 +OP4 E00DAB 0 +OP4 E00DAC 0 +OP4 E00DAD 0 +OP4 E00DAE 0 +OP4 E00DAF 0 +OP4 E00DB0 0 +OP4 E00DB1 0 +OP4 E00DB2 0 +OP4 E00DB3 0 +OP4 E00DB4 0 +OP4 E00DB5 0 +OP4 E00DB6 0 +OP4 E00DB7 0 +OP4 E00DB8 0 +OP4 E00DB9 0 +OP4 E00DBA 0 +OP4 E00DBB 0 +OP4 E00DBC 0 +OP4 E00DBD 0 +OP4 E00DBE 0 +OP4 E00DBF 0 +OP4 E00DC0 0 +OP4 E00DC1 0 +OP4 E00DC2 0 +OP4 E00DC3 0 +OP4 E00DC4 0 +OP4 E00DC5 0 +OP4 E00DC6 0 +OP4 E00DC7 0 +OP4 E00DC8 0 +OP4 E00DC9 0 +OP4 E00DCA 0 +OP4 E00DCB 0 +OP4 E00DCC 0 +OP4 E00DCD 0 +OP4 E00DCE 0 +OP4 E00DCF 0 +OP4 E00DD0 0 +OP4 E00DD1 0 +OP4 E00DD2 0 +OP4 E00DD3 0 +OP4 E00DD4 0 +OP4 E00DD5 0 +OP4 E00DD6 0 +OP4 E00DD7 0 +OP4 E00DD8 0 +OP4 E00DD9 0 +OP4 E00DDA 0 +OP4 E00DDB 0 +OP4 E00DDC 0 +OP4 E00DDD 0 +OP4 E00DDE 0 +OP4 E00DDF 0 +OP4 E00DE0 0 +OP4 E00DE1 0 +OP4 E00DE2 0 +OP4 E00DE3 0 +OP4 E00DE4 0 +OP4 E00DE5 0 +OP4 E00DE6 0 +OP4 E00DE7 0 +OP4 E00DE8 0 +OP4 E00DE9 0 +OP4 E00DEA 0 +OP4 E00DEB 0 +OP4 E00DEC 0 +OP4 E00DED 0 +OP4 E00DEE 0 +OP4 E00DEF 0 +OP4 E00DF0 0 +OP4 E00DF1 0 +OP4 E00DF2 0 +OP4 E00DF3 0 +OP4 E00DF4 0 +OP4 E00DF5 0 +OP4 E00DF6 0 +OP4 E00DF7 0 +OP4 E00DF8 0 +OP4 E00DF9 0 +OP4 E00DFA 0 +OP4 E00DFB 0 +OP4 E00DFC 0 +OP4 E00DFD 0 +OP4 E00DFE 0 +OP4 E00DFF 0 +OP4 E00E00 0 +OP4 E00E01 0 +OP4 E00E02 0 +OP4 E00E03 0 +OP4 E00E04 0 +OP4 E00E05 0 +OP4 E00E06 0 +OP4 E00E07 0 +OP4 E00E08 0 +OP4 E00E09 0 +OP4 E00E0A 0 +OP4 E00E0B 0 +OP4 E00E0C 0 +OP4 E00E0D 0 +OP4 E00E0E 0 +OP4 E00E0F 0 +OP4 E00E10 0 +OP4 E00E11 0 +OP4 E00E12 0 +OP4 E00E13 0 +OP4 E00E14 0 +OP4 E00E15 0 +OP4 E00E16 0 +OP4 E00E17 0 +OP4 E00E18 0 +OP4 E00E19 0 +OP4 E00E1A 0 +OP4 E00E1B 0 +OP4 E00E1C 0 +OP4 E00E1D 0 +OP4 E00E1E 0 +OP4 E00E1F 0 +OP4 E00E20 0 +OP4 E00E21 0 +OP4 E00E22 0 +OP4 E00E23 0 +OP4 E00E24 0 +OP4 E00E25 0 +OP4 E00E26 0 +OP4 E00E27 0 +OP4 E00E28 0 +OP4 E00E29 0 +OP4 E00E2A 0 +OP4 E00E2B 0 +OP4 E00E2C 0 +OP4 E00E2D 0 +OP4 E00E2E 0 +OP4 E00E2F 0 +OP4 E00E30 0 +OP4 E00E31 0 +OP4 E00E32 0 +OP4 E00E33 0 +OP4 E00E34 0 +OP4 E00E35 0 +OP4 E00E36 0 +OP4 E00E37 0 +OP4 E00E38 0 +OP4 E00E39 0 +OP4 E00E3A 0 +OP4 E00E3B 0 +OP4 E00E3C 0 +OP4 E00E3D 0 +OP4 E00E3E 0 +OP4 E00E3F 0 +OP4 E00E40 0 +OP4 E00E41 0 +OP4 E00E42 0 +OP4 E00E43 0 +OP4 E00E44 0 +OP4 E00E45 0 +OP4 E00E46 0 +OP4 E00E47 0 +OP4 E00E48 0 +OP4 E00E49 0 +OP4 E00E4A 0 +OP4 E00E4B 0 +OP4 E00E4C 0 +OP4 E00E4D 0 +OP4 E00E4E 0 +OP4 E00E4F 0 +OP4 E00E50 0 +OP4 E00E51 0 +OP4 E00E52 0 +OP4 E00E53 0 +OP4 E00E54 0 +OP4 E00E55 0 +OP4 E00E56 0 +OP4 E00E57 0 +OP4 E00E58 0 +OP4 E00E59 0 +OP4 E00E5A 0 +OP4 E00E5B 0 +OP4 E00E5C 0 +OP4 E00E5D 0 +OP4 E00E5E 0 +OP4 E00E5F 0 +OP4 E00E60 0 +OP4 E00E61 0 +OP4 E00E62 0 +OP4 E00E63 0 +OP4 E00E64 0 +OP4 E00E65 0 +OP4 E00E66 0 +OP4 E00E67 0 +OP4 E00E68 0 +OP4 E00E69 0 +OP4 E00E6A 0 +OP4 E00E6B 0 +OP4 E00E6C 0 +OP4 E00E6D 0 +OP4 E00E6E 0 +OP4 E00E6F 0 +OP4 E00E70 0 +OP4 E00E71 0 +OP4 E00E72 0 +OP4 E00E73 0 +OP4 E00E74 0 +OP4 E00E75 0 +OP4 E00E76 0 +OP4 E00E77 0 +OP4 E00E78 0 +OP4 E00E79 0 +OP4 E00E7A 0 +OP4 E00E7B 0 +OP4 E00E7C 0 +OP4 E00E7D 0 +OP4 E00E7E 0 +OP4 E00E7F 0 +OP4 E00E80 0 +OP4 E00E81 0 +OP4 E00E82 0 +OP4 E00E83 0 +OP4 E00E84 0 +OP4 E00E85 0 +OP4 E00E86 0 +OP4 E00E87 0 +OP4 E00E88 0 +OP4 E00E89 0 +OP4 E00E8A 0 +OP4 E00E8B 0 +OP4 E00E8C 0 +OP4 E00E8D 0 +OP4 E00E8E 0 +OP4 E00E8F 0 +OP4 E00E90 0 +OP4 E00E91 0 +OP4 E00E92 0 +OP4 E00E93 0 +OP4 E00E94 0 +OP4 E00E95 0 +OP4 E00E96 0 +OP4 E00E97 0 +OP4 E00E98 0 +OP4 E00E99 0 +OP4 E00E9A 0 +OP4 E00E9B 0 +OP4 E00E9C 0 +OP4 E00E9D 0 +OP4 E00E9E 0 +OP4 E00E9F 0 +OP4 E00EA0 0 +OP4 E00EA1 0 +OP4 E00EA2 0 +OP4 E00EA3 0 +OP4 E00EA4 0 +OP4 E00EA5 0 +OP4 E00EA6 0 +OP4 E00EA7 0 +OP4 E00EA8 0 +OP4 E00EA9 0 +OP4 E00EAA 0 +OP4 E00EAB 0 +OP4 E00EAC 0 +OP4 E00EAD 0 +OP4 E00EAE 0 +OP4 E00EAF 0 +OP4 E00EB0 0 +OP4 E00EB1 0 +OP4 E00EB2 0 +OP4 E00EB3 0 +OP4 E00EB4 0 +OP4 E00EB5 0 +OP4 E00EB6 0 +OP4 E00EB7 0 +OP4 E00EB8 0 +OP4 E00EB9 0 +OP4 E00EBA 0 +OP4 E00EBB 0 +OP4 E00EBC 0 +OP4 E00EBD 0 +OP4 E00EBE 0 +OP4 E00EBF 0 +OP4 E00EC0 0 +OP4 E00EC1 0 +OP4 E00EC2 0 +OP4 E00EC3 0 +OP4 E00EC4 0 +OP4 E00EC5 0 +OP4 E00EC6 0 +OP4 E00EC7 0 +OP4 E00EC8 0 +OP4 E00EC9 0 +OP4 E00ECA 0 +OP4 E00ECB 0 +OP4 E00ECC 0 +OP4 E00ECD 0 +OP4 E00ECE 0 +OP4 E00ECF 0 +OP4 E00ED0 0 +OP4 E00ED1 0 +OP4 E00ED2 0 +OP4 E00ED3 0 +OP4 E00ED4 0 +OP4 E00ED5 0 +OP4 E00ED6 0 +OP4 E00ED7 0 +OP4 E00ED8 0 +OP4 E00ED9 0 +OP4 E00EDA 0 +OP4 E00EDB 0 +OP4 E00EDC 0 +OP4 E00EDD 0 +OP4 E00EDE 0 +OP4 E00EDF 0 +OP4 E00EE0 0 +OP4 E00EE1 0 +OP4 E00EE2 0 +OP4 E00EE3 0 +OP4 E00EE4 0 +OP4 E00EE5 0 +OP4 E00EE6 0 +OP4 E00EE7 0 +OP4 E00EE8 0 +OP4 E00EE9 0 +OP4 E00EEA 0 +OP4 E00EEB 0 +OP4 E00EEC 0 +OP4 E00EED 0 +OP4 E00EEE 0 +OP4 E00EEF 0 +OP4 E00EF0 0 +OP4 E00EF1 0 +OP4 E00EF2 0 +OP4 E00EF3 0 +OP4 E00EF4 0 +OP4 E00EF5 0 +OP4 E00EF6 0 +OP4 E00EF7 0 +OP4 E00EF8 0 +OP4 E00EF9 0 +OP4 E00EFA 0 +OP4 E00EFB 0 +OP4 E00EFC 0 +OP4 E00EFD 0 +OP4 E00EFE 0 +OP4 E00EFF 0 +OP4 E00F00 0 +OP4 E00F01 0 +OP4 E00F02 0 +OP4 E00F03 0 +OP4 E00F04 0 +OP4 E00F05 0 +OP4 E00F06 0 +OP4 E00F07 0 +OP4 E00F08 0 +OP4 E00F09 0 +OP4 E00F0A 0 +OP4 E00F0B 0 +OP4 E00F0C 0 +OP4 E00F0D 0 +OP4 E00F0E 0 +OP4 E00F0F 0 +OP4 E00F10 0 +OP4 E00F11 0 +OP4 E00F12 0 +OP4 E00F13 0 +OP4 E00F14 0 +OP4 E00F15 0 +OP4 E00F16 0 +OP4 E00F17 0 +OP4 E00F18 0 +OP4 E00F19 0 +OP4 E00F1A 0 +OP4 E00F1B 0 +OP4 E00F1C 0 +OP4 E00F1D 0 +OP4 E00F1E 0 +OP4 E00F1F 0 +OP4 E00F20 0 +OP4 E00F21 0 +OP4 E00F22 0 +OP4 E00F23 0 +OP4 E00F24 0 +OP4 E00F25 0 +OP4 E00F26 0 +OP4 E00F27 0 +OP4 E00F28 0 +OP4 E00F29 0 +OP4 E00F2A 0 +OP4 E00F2B 0 +OP4 E00F2C 0 +OP4 E00F2D 0 +OP4 E00F2E 0 +OP4 E00F2F 0 +OP4 E00F30 0 diff --git a/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum4_itrace.cfg.ext b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum4_itrace.cfg.ext new file mode 100644 index 000000000000..ab21020d6f4e --- /dev/null +++ b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum4_itrace.cfg.ext @@ -0,0 +1,15814 @@ +OP1 Spectrum4 +OP4 ITRACE0 1 +OP4 ITRACE1 1 +OP4 ITRACE2 1 +OP4 ITRACE3 1 +OP4 ITRACE4 1 +OP4 ITRACE5 1 +OP4 ITRACE6 1 +OP4 ITRACE7 1 +OP4 ITRACE8 1 +OP4 ITRACE9 1 +OP4 Main_PhyUC 0 +OP4 TILE0_ITRACE0 0 +OP4 TILE0_ITRACE1 0 +OP4 TILE0_ITRACE2 0 +OP4 TILE0_ITRACE3 0 +OP4 TILE0_ITRACE4 0 +OP4 TILE0_PhyUC 0 +OP4 TILE1_ITRACE0 0 +OP4 TILE1_ITRACE1 0 +OP4 TILE1_ITRACE2 0 +OP4 TILE1_ITRACE3 0 +OP4 TILE1_ITRACE4 0 +OP4 TILE1_PhyUC 0 +OP4 TILE2_ITRACE0 0 +OP4 TILE2_ITRACE1 0 +OP4 TILE2_ITRACE2 0 +OP4 TILE2_ITRACE3 0 +OP4 TILE2_ITRACE4 0 +OP4 TILE2_PhyUC 0 +OP4 TILE3_ITRACE0 0 +OP4 TILE3_ITRACE1 0 +OP4 TILE3_ITRACE2 0 +OP4 TILE3_ITRACE3 0 +OP4 TILE3_ITRACE4 0 +OP4 TILE3_PhyUC 0 +OP4 TILE4_ITRACE0 0 +OP4 TILE4_ITRACE1 0 +OP4 TILE4_ITRACE2 0 +OP4 TILE4_ITRACE3 0 +OP4 TILE4_ITRACE4 0 +OP4 TILE4_PhyUC 0 +OP4 TILE5_ITRACE0 0 +OP4 TILE5_ITRACE1 0 +OP4 TILE5_ITRACE2 0 +OP4 TILE5_ITRACE3 0 +OP4 TILE5_ITRACE4 0 +OP4 TILE5_PhyUC 0 +OP4 TILE6_ITRACE0 0 +OP4 TILE6_ITRACE1 0 +OP4 TILE6_ITRACE2 0 +OP4 TILE6_ITRACE3 0 +OP4 TILE6_ITRACE4 0 +OP4 TILE6_PhyUC 0 +OP4 TILE7_ITRACE0 0 +OP4 TILE7_ITRACE1 0 +OP4 TILE7_ITRACE2 0 +OP4 TILE7_ITRACE3 0 +OP4 TILE7_ITRACE4 0 +OP4 TILE7_PhyUC 0 +OP4 E0003B 0 +OP4 E0003C 0 +OP4 E0003D 0 +OP4 E0003E 0 +OP4 E0003F 0 +OP4 E00040 0 +OP4 E00041 0 +OP4 E00042 0 +OP4 E00043 0 +OP4 E00044 0 +OP4 E00045 0 +OP4 E00046 0 +OP4 E00047 0 +OP4 E00048 0 +OP4 E00049 0 +OP4 E0004A 0 +OP4 E0004B 0 +OP4 E0004C 0 +OP4 E0004D 0 +OP4 E0004E 0 +OP4 E0004F 0 +OP4 E00050 0 +OP4 E00051 0 +OP4 E00052 0 +OP4 E00053 0 +OP4 E00054 0 +OP4 E00055 0 +OP4 E00056 0 +OP4 E00057 0 +OP4 E00058 0 +OP4 E00059 0 +OP4 E0005A 0 +OP4 E0005B 0 +OP4 E0005C 0 +OP4 E0005D 0 +OP4 E0005E 0 +OP4 E0005F 0 +OP4 E00060 0 +OP4 E00061 0 +OP4 E00062 0 +OP4 E00063 0 +OP4 E00064 0 +OP4 E00065 0 +OP4 E00066 0 +OP4 E00067 0 +OP4 E00068 0 +OP4 E00069 0 +OP4 E0006A 0 +OP4 E0006B 0 +OP4 E0006C 0 +OP4 E0006D 0 +OP4 E0006E 0 +OP4 E0006F 0 +OP4 E00070 0 +OP4 E00071 0 +OP4 E00072 0 +OP4 E00073 0 +OP4 E00074 0 +OP4 E00075 0 +OP4 E00076 0 +OP4 E00077 0 +OP4 E00078 0 +OP4 E00079 0 +OP4 E0007A 0 +OP4 E0007B 0 +OP4 E0007C 0 +OP4 E0007D 0 +OP4 E0007E 0 +OP4 E0007F 0 +OP4 E00080 0 +OP4 E00081 0 +OP4 E00082 0 +OP4 E00083 0 +OP4 E00084 0 +OP4 E00085 0 +OP4 E00086 0 +OP4 E00087 0 +OP4 E00088 0 +OP4 E00089 0 +OP4 E0008A 0 +OP4 E0008B 0 +OP4 E0008C 0 +OP4 E0008D 0 +OP4 E0008E 0 +OP4 E0008F 0 +OP4 E00090 0 +OP4 E00091 0 +OP4 E00092 0 +OP4 E00093 0 +OP4 E00094 0 +OP4 E00095 0 +OP4 E00096 0 +OP4 E00097 0 +OP4 E00098 0 +OP4 E00099 0 +OP4 E0009A 0 +OP4 E0009B 0 +OP4 E0009C 0 +OP4 E0009D 0 +OP4 E0009E 0 +OP4 E0009F 0 +OP4 E000A0 0 +OP4 E000A1 0 +OP4 E000A2 0 +OP4 E000A3 0 +OP4 E000A4 0 +OP4 E000A5 0 +OP4 E000A6 0 +OP4 E000A7 0 +OP4 E000A8 0 +OP4 E000A9 0 +OP4 E000AA 0 +OP4 E000AB 0 +OP4 E000AC 0 +OP4 E000AD 0 +OP4 E000AE 0 +OP4 E000AF 0 +OP4 E000B0 0 +OP4 E000B1 0 +OP4 E000B2 0 +OP4 E000B3 0 +OP4 E000B4 0 +OP4 E000B5 0 +OP4 E000B6 0 +OP4 E000B7 0 +OP4 E000B8 0 +OP4 E000B9 0 +OP4 E000BA 0 +OP4 E000BB 0 +OP4 E000BC 0 +OP4 E000BD 0 +OP4 E000BE 0 +OP4 E000BF 0 +OP4 E000C0 0 +OP4 E000C1 0 +OP4 E000C2 0 +OP4 E000C3 0 +OP4 E000C4 0 +OP4 E000C5 0 +OP4 E000C6 0 +OP4 E000C7 0 +OP4 E000C8 0 +OP4 E000C9 0 +OP4 E000CA 0 +OP4 E000CB 0 +OP4 E000CC 0 +OP4 E000CD 0 +OP4 E000CE 0 +OP4 E000CF 0 +OP4 E000D0 0 +OP4 E000D1 0 +OP4 E000D2 0 +OP4 E000D3 0 +OP4 E000D4 0 +OP4 E000D5 0 +OP4 E000D6 0 +OP4 E000D7 0 +OP4 E000D8 0 +OP4 E000D9 0 +OP4 E000DA 0 +OP4 E000DB 0 +OP4 E000DC 0 +OP4 E000DD 0 +OP4 E000DE 0 +OP4 E000DF 0 +OP4 E000E0 0 +OP4 E000E1 0 +OP4 E000E2 0 +OP4 E000E3 0 +OP4 E000E4 0 +OP4 E000E5 0 +OP4 E000E6 0 +OP4 E000E7 0 +OP4 E000E8 0 +OP4 E000E9 0 +OP4 E000EA 0 +OP4 E000EB 0 +OP4 E000EC 0 +OP4 E000ED 0 +OP4 E000EE 0 +OP4 E000EF 0 +OP4 E000F0 0 +OP4 E000F1 0 +OP4 E000F2 0 +OP4 E000F3 0 +OP4 E000F4 0 +OP4 E000F5 0 +OP4 E000F6 0 +OP4 E000F7 0 +OP4 E000F8 0 +OP4 E000F9 0 +OP4 E000FA 0 +OP4 E000FB 0 +OP4 E000FC 0 +OP4 E000FD 0 +OP4 E000FE 0 +OP4 E000FF 0 +OP4 E00100 0 +OP4 E00101 0 +OP4 E00102 0 +OP4 E00103 0 +OP4 E00104 0 +OP4 E00105 0 +OP4 E00106 0 +OP4 E00107 0 +OP4 E00108 0 +OP4 E00109 0 +OP4 E0010A 0 +OP4 E0010B 0 +OP4 E0010C 0 +OP4 E0010D 0 +OP4 E0010E 0 +OP4 E0010F 0 +OP4 E00110 0 +OP4 E00111 0 +OP4 E00112 0 +OP4 E00113 0 +OP4 E00114 0 +OP4 E00115 0 +OP4 E00116 0 +OP4 E00117 0 +OP4 E00118 0 +OP4 E00119 0 +OP4 E0011A 0 +OP4 E0011B 0 +OP4 E0011C 0 +OP4 E0011D 0 +OP4 E0011E 0 +OP4 E0011F 0 +OP4 E00120 0 +OP4 E00121 0 +OP4 E00122 0 +OP4 E00123 0 +OP4 E00124 0 +OP4 E00125 0 +OP4 E00126 0 +OP4 E00127 0 +OP4 E00128 0 +OP4 E00129 0 +OP4 E0012A 0 +OP4 E0012B 0 +OP4 E0012C 0 +OP4 E0012D 0 +OP4 E0012E 0 +OP4 E0012F 0 +OP4 E00130 0 +OP4 E00131 0 +OP4 E00132 0 +OP4 E00133 0 +OP4 E00134 0 +OP4 E00135 0 +OP4 E00136 0 +OP4 E00137 0 +OP4 E00138 0 +OP4 E00139 0 +OP4 E0013A 0 +OP4 E0013B 0 +OP4 E0013C 0 +OP4 E0013D 0 +OP4 E0013E 0 +OP4 E0013F 0 +OP4 E00140 0 +OP4 E00141 0 +OP4 E00142 0 +OP4 E00143 0 +OP4 E00144 0 +OP4 E00145 0 +OP4 E00146 0 +OP4 E00147 0 +OP4 E00148 0 +OP4 E00149 0 +OP4 E0014A 0 +OP4 E0014B 0 +OP4 E0014C 0 +OP4 E0014D 0 +OP4 E0014E 0 +OP4 E0014F 0 +OP4 E00150 0 +OP4 E00151 0 +OP4 E00152 0 +OP4 E00153 0 +OP4 E00154 0 +OP4 E00155 0 +OP4 E00156 0 +OP4 E00157 0 +OP4 E00158 0 +OP4 E00159 0 +OP4 E0015A 0 +OP4 E0015B 0 +OP4 E0015C 0 +OP4 E0015D 0 +OP4 E0015E 0 +OP4 E0015F 0 +OP4 E00160 0 +OP4 E00161 0 +OP4 E00162 0 +OP4 E00163 0 +OP4 E00164 0 +OP4 E00165 0 +OP4 E00166 0 +OP4 E00167 0 +OP4 E00168 0 +OP4 E00169 0 +OP4 E0016A 0 +OP4 E0016B 0 +OP4 E0016C 0 +OP4 E0016D 0 +OP4 E0016E 0 +OP4 E0016F 0 +OP4 E00170 0 +OP4 E00171 0 +OP4 E00172 0 +OP4 E00173 0 +OP4 E00174 0 +OP4 E00175 0 +OP4 E00176 0 +OP4 E00177 0 +OP4 E00178 0 +OP4 E00179 0 +OP4 E0017A 0 +OP4 E0017B 0 +OP4 E0017C 0 +OP4 E0017D 0 +OP4 E0017E 0 +OP4 E0017F 0 +OP4 E00180 0 +OP4 E00181 0 +OP4 E00182 0 +OP4 E00183 0 +OP4 E00184 0 +OP4 E00185 0 +OP4 E00186 0 +OP4 E00187 0 +OP4 E00188 0 +OP4 E00189 0 +OP4 E0018A 0 +OP4 E0018B 0 +OP4 E0018C 0 +OP4 E0018D 0 +OP4 E0018E 0 +OP4 E0018F 0 +OP4 E00190 0 +OP4 E00191 0 +OP4 E00192 0 +OP4 E00193 0 +OP4 E00194 0 +OP4 E00195 0 +OP4 E00196 0 +OP4 E00197 0 +OP4 E00198 0 +OP4 E00199 0 +OP4 E0019A 0 +OP4 E0019B 0 +OP4 E0019C 0 +OP4 E0019D 0 +OP4 E0019E 0 +OP4 E0019F 0 +OP4 E001A0 0 +OP4 E001A1 0 +OP4 E001A2 0 +OP4 E001A3 0 +OP4 E001A4 0 +OP4 E001A5 0 +OP4 E001A6 0 +OP4 E001A7 0 +OP4 E001A8 0 +OP4 E001A9 0 +OP4 E001AA 0 +OP4 E001AB 0 +OP4 E001AC 0 +OP4 E001AD 0 +OP4 E001AE 0 +OP4 E001AF 0 +OP4 E001B0 0 +OP4 E001B1 0 +OP4 E001B2 0 +OP4 E001B3 0 +OP4 E001B4 0 +OP4 E001B5 0 +OP4 E001B6 0 +OP4 E001B7 0 +OP4 E001B8 0 +OP4 E001B9 0 +OP4 E001BA 0 +OP4 E001BB 0 +OP4 E001BC 0 +OP4 E001BD 0 +OP4 E001BE 0 +OP4 E001BF 0 +OP4 E001C0 0 +OP4 E001C1 0 +OP4 E001C2 0 +OP4 E001C3 0 +OP4 E001C4 0 +OP4 E001C5 0 +OP4 E001C6 0 +OP4 E001C7 0 +OP4 E001C8 0 +OP4 E001C9 0 +OP4 E001CA 0 +OP4 E001CB 0 +OP4 E001CC 0 +OP4 E001CD 0 +OP4 E001CE 0 +OP4 E001CF 0 +OP4 E001D0 0 +OP4 E001D1 0 +OP4 E001D2 0 +OP4 E001D3 0 +OP4 E001D4 0 +OP4 E001D5 0 +OP4 E001D6 0 +OP4 E001D7 0 +OP4 E001D8 0 +OP4 E001D9 0 +OP4 E001DA 0 +OP4 E001DB 0 +OP4 E001DC 0 +OP4 E001DD 0 +OP4 E001DE 0 +OP4 E001DF 0 +OP4 E001E0 0 +OP4 E001E1 0 +OP4 E001E2 0 +OP4 E001E3 0 +OP4 E001E4 0 +OP4 E001E5 0 +OP4 E001E6 0 +OP4 E001E7 0 +OP4 E001E8 0 +OP4 E001E9 0 +OP4 E001EA 0 +OP4 E001EB 0 +OP4 E001EC 0 +OP4 E001ED 0 +OP4 E001EE 0 +OP4 E001EF 0 +OP4 E001F0 0 +OP4 E001F1 0 +OP4 E001F2 0 +OP4 E001F3 0 +OP4 E001F4 0 +OP4 E001F5 0 +OP4 E001F6 0 +OP4 E001F7 0 +OP4 E001F8 0 +OP4 E001F9 0 +OP4 E001FA 0 +OP4 E001FB 0 +OP4 E001FC 0 +OP4 E001FD 0 +OP4 E001FE 0 +OP4 E001FF 0 +OP4 E00200 0 +OP4 E00201 0 +OP4 E00202 0 +OP4 E00203 0 +OP4 E00204 0 +OP4 E00205 0 +OP4 E00206 0 +OP4 E00207 0 +OP4 E00208 0 +OP4 E00209 0 +OP4 E0020A 0 +OP4 E0020B 0 +OP4 E0020C 0 +OP4 E0020D 0 +OP4 E0020E 0 +OP4 E0020F 0 +OP4 E00210 0 +OP4 E00211 0 +OP4 E00212 0 +OP4 E00213 0 +OP4 E00214 0 +OP4 E00215 0 +OP4 E00216 0 +OP4 E00217 0 +OP4 E00218 0 +OP4 E00219 0 +OP4 E0021A 0 +OP4 E0021B 0 +OP4 E0021C 0 +OP4 E0021D 0 +OP4 E0021E 0 +OP4 E0021F 0 +OP4 E00220 0 +OP4 E00221 0 +OP4 E00222 0 +OP4 E00223 0 +OP4 E00224 0 +OP4 E00225 0 +OP4 E00226 0 +OP4 E00227 0 +OP4 E00228 0 +OP4 E00229 0 +OP4 E0022A 0 +OP4 E0022B 0 +OP4 E0022C 0 +OP4 E0022D 0 +OP4 E0022E 0 +OP4 E0022F 0 +OP4 E00230 0 +OP4 E00231 0 +OP4 E00232 0 +OP4 E00233 0 +OP4 E00234 0 +OP4 E00235 0 +OP4 E00236 0 +OP4 E00237 0 +OP4 E00238 0 +OP4 E00239 0 +OP4 E0023A 0 +OP4 E0023B 0 +OP4 E0023C 0 +OP4 E0023D 0 +OP4 E0023E 0 +OP4 E0023F 0 +OP4 E00240 0 +OP4 E00241 0 +OP4 E00242 0 +OP4 E00243 0 +OP4 E00244 0 +OP4 E00245 0 +OP4 E00246 0 +OP4 E00247 0 +OP4 E00248 0 +OP4 E00249 0 +OP4 E0024A 0 +OP4 E0024B 0 +OP4 E0024C 0 +OP4 E0024D 0 +OP4 E0024E 0 +OP4 E0024F 0 +OP4 E00250 0 +OP4 E00251 0 +OP4 E00252 0 +OP4 E00253 0 +OP4 E00254 0 +OP4 E00255 0 +OP4 E00256 0 +OP4 E00257 0 +OP4 E00258 0 +OP4 E00259 0 +OP4 E0025A 0 +OP4 E0025B 0 +OP4 E0025C 0 +OP4 E0025D 0 +OP4 E0025E 0 +OP4 E0025F 0 +OP4 E00260 0 +OP4 E00261 0 +OP4 E00262 0 +OP4 E00263 0 +OP4 E00264 0 +OP4 E00265 0 +OP4 E00266 0 +OP4 E00267 0 +OP4 E00268 0 +OP4 E00269 0 +OP4 E0026A 0 +OP4 E0026B 0 +OP4 E0026C 0 +OP4 E0026D 0 +OP4 E0026E 0 +OP4 E0026F 0 +OP4 E00270 0 +OP4 E00271 0 +OP4 E00272 0 +OP4 E00273 0 +OP4 E00274 0 +OP4 E00275 0 +OP4 E00276 0 +OP4 E00277 0 +OP4 E00278 0 +OP4 E00279 0 +OP4 E0027A 0 +OP4 E0027B 0 +OP4 E0027C 0 +OP4 E0027D 0 +OP4 E0027E 0 +OP4 E0027F 0 +OP4 E00280 0 +OP4 E00281 0 +OP4 E00282 0 +OP4 E00283 0 +OP4 E00284 0 +OP4 E00285 0 +OP4 E00286 0 +OP4 E00287 0 +OP4 E00288 0 +OP4 E00289 0 +OP4 E0028A 0 +OP4 E0028B 0 +OP4 E0028C 0 +OP4 E0028D 0 +OP4 E0028E 0 +OP4 E0028F 0 +OP4 E00290 0 +OP4 E00291 0 +OP4 E00292 0 +OP4 E00293 0 +OP4 E00294 0 +OP4 E00295 0 +OP4 E00296 0 +OP4 E00297 0 +OP4 E00298 0 +OP4 E00299 0 +OP4 E0029A 0 +OP4 E0029B 0 +OP4 E0029C 0 +OP4 E0029D 0 +OP4 E0029E 0 +OP4 E0029F 0 +OP4 E002A0 0 +OP4 E002A1 0 +OP4 E002A2 0 +OP4 E002A3 0 +OP4 E002A4 0 +OP4 E002A5 0 +OP4 E002A6 0 +OP4 E002A7 0 +OP4 E002A8 0 +OP4 E002A9 0 +OP4 E002AA 0 +OP4 E002AB 0 +OP4 E002AC 0 +OP4 E002AD 0 +OP4 E002AE 0 +OP4 E002AF 0 +OP4 E002B0 0 +OP4 E002B1 0 +OP4 E002B2 0 +OP4 E002B3 0 +OP4 E002B4 0 +OP4 E002B5 0 +OP4 E002B6 0 +OP4 E002B7 0 +OP4 E002B8 0 +OP4 E002B9 0 +OP4 E002BA 0 +OP4 E002BB 0 +OP4 E002BC 0 +OP4 E002BD 0 +OP4 E002BE 0 +OP4 E002BF 0 +OP4 E002C0 0 +OP4 E002C1 0 +OP4 E002C2 0 +OP4 E002C3 0 +OP4 E002C4 0 +OP4 E002C5 0 +OP4 E002C6 0 +OP4 E002C7 0 +OP4 E002C8 0 +OP4 E002C9 0 +OP4 E002CA 0 +OP4 E002CB 0 +OP4 E002CC 0 +OP4 E002CD 0 +OP4 E002CE 0 +OP4 E002CF 0 +OP4 E002D0 0 +OP4 E002D1 0 +OP4 E002D2 0 +OP4 E002D3 0 +OP4 E002D4 0 +OP4 E002D5 0 +OP4 E002D6 0 +OP4 E002D7 0 +OP4 E002D8 0 +OP4 E002D9 0 +OP4 E002DA 0 +OP4 E002DB 0 +OP4 E002DC 0 +OP4 E002DD 0 +OP4 E002DE 0 +OP4 E002DF 0 +OP4 E002E0 0 +OP4 E002E1 0 +OP4 E002E2 0 +OP4 E002E3 0 +OP4 E002E4 0 +OP4 E002E5 0 +OP4 E002E6 0 +OP4 E002E7 0 +OP4 E002E8 0 +OP4 E002E9 0 +OP4 E002EA 0 +OP4 E002EB 0 +OP4 E002EC 0 +OP4 E002ED 0 +OP4 E002EE 0 +OP4 E002EF 0 +OP4 E002F0 0 +OP4 E002F1 0 +OP4 E002F2 0 +OP4 E002F3 0 +OP4 E002F4 0 +OP4 E002F5 0 +OP4 E002F6 0 +OP4 E002F7 0 +OP4 E002F8 0 +OP4 E002F9 0 +OP4 E002FA 0 +OP4 E002FB 0 +OP4 E002FC 0 +OP4 E002FD 0 +OP4 E002FE 0 +OP4 E002FF 0 +OP4 E00300 0 +OP4 E00301 0 +OP4 E00302 0 +OP4 E00303 0 +OP4 E00304 0 +OP4 E00305 0 +OP4 E00306 0 +OP4 E00307 0 +OP4 E00308 0 +OP4 E00309 0 +OP4 E0030A 0 +OP4 E0030B 0 +OP4 E0030C 0 +OP4 E0030D 0 +OP4 E0030E 0 +OP4 E0030F 0 +OP4 E00310 0 +OP4 E00311 0 +OP4 E00312 0 +OP4 E00313 0 +OP4 E00314 0 +OP4 E00315 0 +OP4 E00316 0 +OP4 E00317 0 +OP4 E00318 0 +OP4 E00319 0 +OP4 E0031A 0 +OP4 E0031B 0 +OP4 E0031C 0 +OP4 E0031D 0 +OP4 E0031E 0 +OP4 E0031F 0 +OP4 E00320 0 +OP4 E00321 0 +OP4 E00322 0 +OP4 E00323 0 +OP4 E00324 0 +OP4 E00325 0 +OP4 E00326 0 +OP4 E00327 0 +OP4 E00328 0 +OP4 E00329 0 +OP4 E0032A 0 +OP4 E0032B 0 +OP4 E0032C 0 +OP4 E0032D 0 +OP4 E0032E 0 +OP4 E0032F 0 +OP4 E00330 0 +OP4 E00331 0 +OP4 E00332 0 +OP4 E00333 0 +OP4 E00334 0 +OP4 E00335 0 +OP4 E00336 0 +OP4 E00337 0 +OP4 E00338 0 +OP4 E00339 0 +OP4 E0033A 0 +OP4 E0033B 0 +OP4 E0033C 0 +OP4 E0033D 0 +OP4 E0033E 0 +OP4 E0033F 0 +OP4 E00340 0 +OP4 E00341 0 +OP4 E00342 0 +OP4 E00343 0 +OP4 E00344 0 +OP4 E00345 0 +OP4 E00346 0 +OP4 E00347 0 +OP4 E00348 0 +OP4 E00349 0 +OP4 E0034A 0 +OP4 E0034B 0 +OP4 E0034C 0 +OP4 E0034D 0 +OP4 E0034E 0 +OP4 E0034F 0 +OP4 E00350 0 +OP4 E00351 0 +OP4 E00352 0 +OP4 E00353 0 +OP4 E00354 0 +OP4 E00355 0 +OP4 E00356 0 +OP4 E00357 0 +OP4 E00358 0 +OP4 E00359 0 +OP4 E0035A 0 +OP4 E0035B 0 +OP4 E0035C 0 +OP4 E0035D 0 +OP4 E0035E 0 +OP4 E0035F 0 +OP4 E00360 0 +OP4 E00361 0 +OP4 E00362 0 +OP4 E00363 0 +OP4 E00364 0 +OP4 E00365 0 +OP4 E00366 0 +OP4 E00367 0 +OP4 E00368 0 +OP4 E00369 0 +OP4 E0036A 0 +OP4 E0036B 0 +OP4 E0036C 0 +OP4 E0036D 0 +OP4 E0036E 0 +OP4 E0036F 0 +OP4 E00370 0 +OP4 E00371 0 +OP4 E00372 0 +OP4 E00373 0 +OP4 E00374 0 +OP4 E00375 0 +OP4 E00376 0 +OP4 E00377 0 +OP4 E00378 0 +OP4 E00379 0 +OP4 E0037A 0 +OP4 E0037B 0 +OP4 E0037C 0 +OP4 E0037D 0 +OP4 E0037E 0 +OP4 E0037F 0 +OP4 E00380 0 +OP4 E00381 0 +OP4 E00382 0 +OP4 E00383 0 +OP4 E00384 0 +OP4 E00385 0 +OP4 E00386 0 +OP4 E00387 0 +OP4 E00388 0 +OP4 E00389 0 +OP4 E0038A 0 +OP4 E0038B 0 +OP4 E0038C 0 +OP4 E0038D 0 +OP4 E0038E 0 +OP4 E0038F 0 +OP4 E00390 0 +OP4 E00391 0 +OP4 E00392 0 +OP4 E00393 0 +OP4 E00394 0 +OP4 E00395 0 +OP4 E00396 0 +OP4 E00397 0 +OP4 E00398 0 +OP4 E00399 0 +OP4 E0039A 0 +OP4 E0039B 0 +OP4 E0039C 0 +OP4 E0039D 0 +OP4 E0039E 0 +OP4 E0039F 0 +OP4 E003A0 0 +OP4 E003A1 0 +OP4 E003A2 0 +OP4 E003A3 0 +OP4 E003A4 0 +OP4 E003A5 0 +OP4 E003A6 0 +OP4 E003A7 0 +OP4 E003A8 0 +OP4 E003A9 0 +OP4 E003AA 0 +OP4 E003AB 0 +OP4 E003AC 0 +OP4 E003AD 0 +OP4 E003AE 0 +OP4 E003AF 0 +OP4 E003B0 0 +OP4 E003B1 0 +OP4 E003B2 0 +OP4 E003B3 0 +OP4 E003B4 0 +OP4 E003B5 0 +OP4 E003B6 0 +OP4 E003B7 0 +OP4 E003B8 0 +OP4 E003B9 0 +OP4 E003BA 0 +OP4 E003BB 0 +OP4 E003BC 0 +OP4 E003BD 0 +OP4 E003BE 0 +OP4 E003BF 0 +OP4 E003C0 0 +OP4 E003C1 0 +OP4 E003C2 0 +OP4 E003C3 0 +OP4 E003C4 0 +OP4 E003C5 0 +OP4 E003C6 0 +OP4 E003C7 0 +OP4 E003C8 0 +OP4 E003C9 0 +OP4 E003CA 0 +OP4 E003CB 0 +OP4 E003CC 0 +OP4 E003CD 0 +OP4 E003CE 0 +OP4 E003CF 0 +OP4 E003D0 0 +OP4 E003D1 0 +OP4 E003D2 0 +OP4 E003D3 0 +OP4 E003D4 0 +OP4 E003D5 0 +OP4 E003D6 0 +OP4 E003D7 0 +OP4 E003D8 0 +OP4 E003D9 0 +OP4 E003DA 0 +OP4 E003DB 0 +OP4 E003DC 0 +OP4 E003DD 0 +OP4 E003DE 0 +OP4 E003DF 0 +OP4 E003E0 0 +OP4 E003E1 0 +OP4 E003E2 0 +OP4 E003E3 0 +OP4 E003E4 0 +OP4 E003E5 0 +OP4 E003E6 0 +OP4 E003E7 0 +OP4 E003E8 0 +OP4 E003E9 0 +OP4 E003EA 0 +OP4 E003EB 0 +OP4 E003EC 0 +OP4 E003ED 0 +OP4 E003EE 0 +OP4 E003EF 0 +OP4 E003F0 0 +OP4 E003F1 0 +OP4 E003F2 0 +OP4 E003F3 0 +OP4 E003F4 0 +OP4 E003F5 0 +OP4 E003F6 0 +OP4 E003F7 0 +OP4 E003F8 0 +OP4 E003F9 0 +OP4 E003FA 0 +OP4 E003FB 0 +OP4 E003FC 0 +OP4 E003FD 0 +OP4 E003FE 0 +OP4 E003FF 0 +OP4 E00400 0 +OP4 E00401 0 +OP4 E00402 0 +OP4 E00403 0 +OP4 E00404 0 +OP4 E00405 0 +OP4 E00406 0 +OP4 E00407 0 +OP4 E00408 0 +OP4 E00409 0 +OP4 E0040A 0 +OP4 E0040B 0 +OP4 E0040C 0 +OP4 E0040D 0 +OP4 E0040E 0 +OP4 E0040F 0 +OP4 E00410 0 +OP4 E00411 0 +OP4 E00412 0 +OP4 E00413 0 +OP4 E00414 0 +OP4 E00415 0 +OP4 E00416 0 +OP4 E00417 0 +OP4 E00418 0 +OP4 E00419 0 +OP4 E0041A 0 +OP4 E0041B 0 +OP4 E0041C 0 +OP4 E0041D 0 +OP4 E0041E 0 +OP4 E0041F 0 +OP4 E00420 0 +OP4 E00421 0 +OP4 E00422 0 +OP4 E00423 0 +OP4 E00424 0 +OP4 E00425 0 +OP4 E00426 0 +OP4 E00427 0 +OP4 E00428 0 +OP4 E00429 0 +OP4 E0042A 0 +OP4 E0042B 0 +OP4 E0042C 0 +OP4 E0042D 0 +OP4 E0042E 0 +OP4 E0042F 0 +OP4 E00430 0 +OP4 E00431 0 +OP4 E00432 0 +OP4 E00433 0 +OP4 E00434 0 +OP4 E00435 0 +OP4 E00436 0 +OP4 E00437 0 +OP4 E00438 0 +OP4 E00439 0 +OP4 E0043A 0 +OP4 E0043B 0 +OP4 E0043C 0 +OP4 E0043D 0 +OP4 E0043E 0 +OP4 E0043F 0 +OP4 E00440 0 +OP4 E00441 0 +OP4 E00442 0 +OP4 E00443 0 +OP4 E00444 0 +OP4 E00445 0 +OP4 E00446 0 +OP4 E00447 0 +OP4 E00448 0 +OP4 E00449 0 +OP4 E0044A 0 +OP4 E0044B 0 +OP4 E0044C 0 +OP4 E0044D 0 +OP4 E0044E 0 +OP4 E0044F 0 +OP4 E00450 0 +OP4 E00451 0 +OP4 E00452 0 +OP4 E00453 0 +OP4 E00454 0 +OP4 E00455 0 +OP4 E00456 0 +OP4 E00457 0 +OP4 E00458 0 +OP4 E00459 0 +OP4 E0045A 0 +OP4 E0045B 0 +OP4 E0045C 0 +OP4 E0045D 0 +OP4 E0045E 0 +OP4 E0045F 0 +OP4 E00460 0 +OP4 E00461 0 +OP4 E00462 0 +OP4 E00463 0 +OP4 E00464 0 +OP4 E00465 0 +OP4 E00466 0 +OP4 E00467 0 +OP4 E00468 0 +OP4 E00469 0 +OP4 E0046A 0 +OP4 E0046B 0 +OP4 E0046C 0 +OP4 E0046D 0 +OP4 E0046E 0 +OP4 E0046F 0 +OP4 E00470 0 +OP4 E00471 0 +OP4 E00472 0 +OP4 E00473 0 +OP4 E00474 0 +OP4 E00475 0 +OP4 E00476 0 +OP4 E00477 0 +OP4 E00478 0 +OP4 E00479 0 +OP4 E0047A 0 +OP4 E0047B 0 +OP4 E0047C 0 +OP4 E0047D 0 +OP4 E0047E 0 +OP4 E0047F 0 +OP4 E00480 0 +OP4 E00481 0 +OP4 E00482 0 +OP4 E00483 0 +OP4 E00484 0 +OP4 E00485 0 +OP4 E00486 0 +OP4 E00487 0 +OP4 E00488 0 +OP4 E00489 0 +OP4 E0048A 0 +OP4 E0048B 0 +OP4 E0048C 0 +OP4 E0048D 0 +OP4 E0048E 0 +OP4 E0048F 0 +OP4 E00490 0 +OP4 E00491 0 +OP4 E00492 0 +OP4 E00493 0 +OP4 E00494 0 +OP4 E00495 0 +OP4 E00496 0 +OP4 E00497 0 +OP4 E00498 0 +OP4 E00499 0 +OP4 E0049A 0 +OP4 E0049B 0 +OP4 E0049C 0 +OP4 E0049D 0 +OP4 E0049E 0 +OP4 E0049F 0 +OP4 E004A0 0 +OP4 E004A1 0 +OP4 E004A2 0 +OP4 E004A3 0 +OP4 E004A4 0 +OP4 E004A5 0 +OP4 E004A6 0 +OP4 E004A7 0 +OP4 E004A8 0 +OP4 E004A9 0 +OP4 E004AA 0 +OP4 E004AB 0 +OP4 E004AC 0 +OP4 E004AD 0 +OP4 E004AE 0 +OP4 E004AF 0 +OP4 E004B0 0 +OP4 E004B1 0 +OP4 E004B2 0 +OP4 E004B3 0 +OP4 E004B4 0 +OP4 E004B5 0 +OP4 E004B6 0 +OP4 E004B7 0 +OP4 E004B8 0 +OP4 E004B9 0 +OP4 E004BA 0 +OP4 E004BB 0 +OP4 E004BC 0 +OP4 E004BD 0 +OP4 E004BE 0 +OP4 E004BF 0 +OP4 E004C0 0 +OP4 E004C1 0 +OP4 E004C2 0 +OP4 E004C3 0 +OP4 E004C4 0 +OP4 E004C5 0 +OP4 E004C6 0 +OP4 E004C7 0 +OP4 E004C8 0 +OP4 E004C9 0 +OP4 E004CA 0 +OP4 E004CB 0 +OP4 E004CC 0 +OP4 E004CD 0 +OP4 E004CE 0 +OP4 E004CF 0 +OP4 E004D0 0 +OP4 E004D1 0 +OP4 E004D2 0 +OP4 E004D3 0 +OP4 E004D4 0 +OP4 E004D5 0 +OP4 E004D6 0 +OP4 E004D7 0 +OP4 E004D8 0 +OP4 E004D9 0 +OP4 E004DA 0 +OP4 E004DB 0 +OP4 E004DC 0 +OP4 E004DD 0 +OP4 E004DE 0 +OP4 E004DF 0 +OP4 E004E0 0 +OP4 E004E1 0 +OP4 E004E2 0 +OP4 E004E3 0 +OP4 E004E4 0 +OP4 E004E5 0 +OP4 E004E6 0 +OP4 E004E7 0 +OP4 E004E8 0 +OP4 E004E9 0 +OP4 E004EA 0 +OP4 E004EB 0 +OP4 E004EC 0 +OP4 E004ED 0 +OP4 E004EE 0 +OP4 E004EF 0 +OP4 E004F0 0 +OP4 E004F1 0 +OP4 E004F2 0 +OP4 E004F3 0 +OP4 E004F4 0 +OP4 E004F5 0 +OP4 E004F6 0 +OP4 E004F7 0 +OP4 E004F8 0 +OP4 E004F9 0 +OP4 E004FA 0 +OP4 E004FB 0 +OP4 E004FC 0 +OP4 E004FD 0 +OP4 E004FE 0 +OP4 E004FF 0 +OP4 E00500 0 +OP4 E00501 0 +OP4 E00502 0 +OP4 E00503 0 +OP4 E00504 0 +OP4 E00505 0 +OP4 E00506 0 +OP4 E00507 0 +OP4 E00508 0 +OP4 E00509 0 +OP4 E0050A 0 +OP4 E0050B 0 +OP4 E0050C 0 +OP4 E0050D 0 +OP4 E0050E 0 +OP4 E0050F 0 +OP4 E00510 0 +OP4 E00511 0 +OP4 E00512 0 +OP4 E00513 0 +OP4 E00514 0 +OP4 E00515 0 +OP4 E00516 0 +OP4 E00517 0 +OP4 E00518 0 +OP4 E00519 0 +OP4 E0051A 0 +OP4 E0051B 0 +OP4 E0051C 0 +OP4 E0051D 0 +OP4 E0051E 0 +OP4 E0051F 0 +OP4 E00520 0 +OP4 E00521 0 +OP4 E00522 0 +OP4 E00523 0 +OP4 E00524 0 +OP4 E00525 0 +OP4 E00526 0 +OP4 E00527 0 +OP4 E00528 0 +OP4 E00529 0 +OP4 E0052A 0 +OP4 E0052B 0 +OP4 E0052C 0 +OP4 E0052D 0 +OP4 E0052E 0 +OP4 E0052F 0 +OP4 E00530 0 +OP4 E00531 0 +OP4 E00532 0 +OP4 E00533 0 +OP4 E00534 0 +OP4 E00535 0 +OP4 E00536 0 +OP4 E00537 0 +OP4 E00538 0 +OP4 E00539 0 +OP4 E0053A 0 +OP4 E0053B 0 +OP4 E0053C 0 +OP4 E0053D 0 +OP4 E0053E 0 +OP4 E0053F 0 +OP4 E00540 0 +OP4 E00541 0 +OP4 E00542 0 +OP4 E00543 0 +OP4 E00544 0 +OP4 E00545 0 +OP4 E00546 0 +OP4 E00547 0 +OP4 E00548 0 +OP4 E00549 0 +OP4 E0054A 0 +OP4 E0054B 0 +OP4 E0054C 0 +OP4 E0054D 0 +OP4 E0054E 0 +OP4 E0054F 0 +OP4 E00550 0 +OP4 E00551 0 +OP4 E00552 0 +OP4 E00553 0 +OP4 E00554 0 +OP4 E00555 0 +OP4 E00556 0 +OP4 E00557 0 +OP4 E00558 0 +OP4 E00559 0 +OP4 E0055A 0 +OP4 E0055B 0 +OP4 E0055C 0 +OP4 E0055D 0 +OP4 E0055E 0 +OP4 E0055F 0 +OP4 E00560 0 +OP4 E00561 0 +OP4 E00562 0 +OP4 E00563 0 +OP4 E00564 0 +OP4 E00565 0 +OP4 E00566 0 +OP4 E00567 0 +OP4 E00568 0 +OP4 E00569 0 +OP4 E0056A 0 +OP4 E0056B 0 +OP4 E0056C 0 +OP4 E0056D 0 +OP4 E0056E 0 +OP4 E0056F 0 +OP4 E00570 0 +OP4 E00571 0 +OP4 E00572 0 +OP4 E00573 0 +OP4 E00574 0 +OP4 E00575 0 +OP4 E00576 0 +OP4 E00577 0 +OP4 E00578 0 +OP4 E00579 0 +OP4 E0057A 0 +OP4 E0057B 0 +OP4 E0057C 0 +OP4 E0057D 0 +OP4 E0057E 0 +OP4 E0057F 0 +OP4 E00580 0 +OP4 E00581 0 +OP4 E00582 0 +OP4 E00583 0 +OP4 E00584 0 +OP4 E00585 0 +OP4 E00586 0 +OP4 E00587 0 +OP4 E00588 0 +OP4 E00589 0 +OP4 E0058A 0 +OP4 E0058B 0 +OP4 E0058C 0 +OP4 E0058D 0 +OP4 E0058E 0 +OP4 E0058F 0 +OP4 E00590 0 +OP4 E00591 0 +OP4 E00592 0 +OP4 E00593 0 +OP4 E00594 0 +OP4 E00595 0 +OP4 E00596 0 +OP4 E00597 0 +OP4 E00598 0 +OP4 E00599 0 +OP4 E0059A 0 +OP4 E0059B 0 +OP4 E0059C 0 +OP4 E0059D 0 +OP4 E0059E 0 +OP4 E0059F 0 +OP4 E005A0 0 +OP4 E005A1 0 +OP4 E005A2 0 +OP4 E005A3 0 +OP4 E005A4 0 +OP4 E005A5 0 +OP4 E005A6 0 +OP4 E005A7 0 +OP4 E005A8 0 +OP4 E005A9 0 +OP4 E005AA 0 +OP4 E005AB 0 +OP4 E005AC 0 +OP4 E005AD 0 +OP4 E005AE 0 +OP4 E005AF 0 +OP4 E005B0 0 +OP4 E005B1 0 +OP4 E005B2 0 +OP4 E005B3 0 +OP4 E005B4 0 +OP4 E005B5 0 +OP4 E005B6 0 +OP4 E005B7 0 +OP4 E005B8 0 +OP4 E005B9 0 +OP4 E005BA 0 +OP4 E005BB 0 +OP4 E005BC 0 +OP4 E005BD 0 +OP4 E005BE 0 +OP4 E005BF 0 +OP4 E005C0 0 +OP4 E005C1 0 +OP4 E005C2 0 +OP4 E005C3 0 +OP4 E005C4 0 +OP4 E005C5 0 +OP4 E005C6 0 +OP4 E005C7 0 +OP4 E005C8 0 +OP4 E005C9 0 +OP4 E005CA 0 +OP4 E005CB 0 +OP4 E005CC 0 +OP4 E005CD 0 +OP4 E005CE 0 +OP4 E005CF 0 +OP4 E005D0 0 +OP4 E005D1 0 +OP4 E005D2 0 +OP4 E005D3 0 +OP4 E005D4 0 +OP4 E005D5 0 +OP4 E005D6 0 +OP4 E005D7 0 +OP4 E005D8 0 +OP4 E005D9 0 +OP4 E005DA 0 +OP4 E005DB 0 +OP4 E005DC 0 +OP4 E005DD 0 +OP4 E005DE 0 +OP4 E005DF 0 +OP4 E005E0 0 +OP4 E005E1 0 +OP4 E005E2 0 +OP4 E005E3 0 +OP4 E005E4 0 +OP4 E005E5 0 +OP4 E005E6 0 +OP4 E005E7 0 +OP4 E005E8 0 +OP4 E005E9 0 +OP4 E005EA 0 +OP4 E005EB 0 +OP4 E005EC 0 +OP4 E005ED 0 +OP4 E005EE 0 +OP4 E005EF 0 +OP4 E005F0 0 +OP4 E005F1 0 +OP4 E005F2 0 +OP4 E005F3 0 +OP4 E005F4 0 +OP4 E005F5 0 +OP4 E005F6 0 +OP4 E005F7 0 +OP4 E005F8 0 +OP4 E005F9 0 +OP4 E005FA 0 +OP4 E005FB 0 +OP4 E005FC 0 +OP4 E005FD 0 +OP4 E005FE 0 +OP4 E005FF 0 +OP4 E00600 0 +OP4 E00601 0 +OP4 E00602 0 +OP4 E00603 0 +OP4 E00604 0 +OP4 E00605 0 +OP4 E00606 0 +OP4 E00607 0 +OP4 E00608 0 +OP4 E00609 0 +OP4 E0060A 0 +OP4 E0060B 0 +OP4 E0060C 0 +OP4 E0060D 0 +OP4 E0060E 0 +OP4 E0060F 0 +OP4 E00610 0 +OP4 E00611 0 +OP4 E00612 0 +OP4 E00613 0 +OP4 E00614 0 +OP4 E00615 0 +OP4 E00616 0 +OP4 E00617 0 +OP4 E00618 0 +OP4 E00619 0 +OP4 E0061A 0 +OP4 E0061B 0 +OP4 E0061C 0 +OP4 E0061D 0 +OP4 E0061E 0 +OP4 E0061F 0 +OP4 E00620 0 +OP4 E00621 0 +OP4 E00622 0 +OP4 E00623 0 +OP4 E00624 0 +OP4 E00625 0 +OP4 E00626 0 +OP4 E00627 0 +OP4 E00628 0 +OP4 E00629 0 +OP4 E0062A 0 +OP4 E0062B 0 +OP4 E0062C 0 +OP4 E0062D 0 +OP4 E0062E 0 +OP4 E0062F 0 +OP4 E00630 0 +OP4 E00631 0 +OP4 E00632 0 +OP4 E00633 0 +OP4 E00634 0 +OP4 E00635 0 +OP4 E00636 0 +OP4 E00637 0 +OP4 E00638 0 +OP4 E00639 0 +OP4 E0063A 0 +OP4 E0063B 0 +OP4 E0063C 0 +OP4 E0063D 0 +OP4 E0063E 0 +OP4 E0063F 0 +OP4 E00640 0 +OP4 E00641 0 +OP4 E00642 0 +OP4 E00643 0 +OP4 E00644 0 +OP4 E00645 0 +OP4 E00646 0 +OP4 E00647 0 +OP4 E00648 0 +OP4 E00649 0 +OP4 E0064A 0 +OP4 E0064B 0 +OP4 E0064C 0 +OP4 E0064D 0 +OP4 E0064E 0 +OP4 E0064F 0 +OP4 E00650 0 +OP4 E00651 0 +OP4 E00652 0 +OP4 E00653 0 +OP4 E00654 0 +OP4 E00655 0 +OP4 E00656 0 +OP4 E00657 0 +OP4 E00658 0 +OP4 E00659 0 +OP4 E0065A 0 +OP4 E0065B 0 +OP4 E0065C 0 +OP4 E0065D 0 +OP4 E0065E 0 +OP4 E0065F 0 +OP4 E00660 0 +OP4 E00661 0 +OP4 E00662 0 +OP4 E00663 0 +OP4 E00664 0 +OP4 E00665 0 +OP4 E00666 0 +OP4 E00667 0 +OP4 E00668 0 +OP4 E00669 0 +OP4 E0066A 0 +OP4 E0066B 0 +OP4 E0066C 0 +OP4 E0066D 0 +OP4 E0066E 0 +OP4 E0066F 0 +OP4 E00670 0 +OP4 E00671 0 +OP4 E00672 0 +OP4 E00673 0 +OP4 E00674 0 +OP4 E00675 0 +OP4 E00676 0 +OP4 E00677 0 +OP4 E00678 0 +OP4 E00679 0 +OP4 E0067A 0 +OP4 E0067B 0 +OP4 E0067C 0 +OP4 E0067D 0 +OP4 E0067E 0 +OP4 E0067F 0 +OP4 E00680 0 +OP4 E00681 0 +OP4 E00682 0 +OP4 E00683 0 +OP4 E00684 0 +OP4 E00685 0 +OP4 E00686 0 +OP4 E00687 0 +OP4 E00688 0 +OP4 E00689 0 +OP4 E0068A 0 +OP4 E0068B 0 +OP4 E0068C 0 +OP4 E0068D 0 +OP4 E0068E 0 +OP4 E0068F 0 +OP4 E00690 0 +OP4 E00691 0 +OP4 E00692 0 +OP4 E00693 0 +OP4 E00694 0 +OP4 E00695 0 +OP4 E00696 0 +OP4 E00697 0 +OP4 E00698 0 +OP4 E00699 0 +OP4 E0069A 0 +OP4 E0069B 0 +OP4 E0069C 0 +OP4 E0069D 0 +OP4 E0069E 0 +OP4 E0069F 0 +OP4 E006A0 0 +OP4 E006A1 0 +OP4 E006A2 0 +OP4 E006A3 0 +OP4 E006A4 0 +OP4 E006A5 0 +OP4 E006A6 0 +OP4 E006A7 0 +OP4 E006A8 0 +OP4 E006A9 0 +OP4 E006AA 0 +OP4 E006AB 0 +OP4 E006AC 0 +OP4 E006AD 0 +OP4 E006AE 0 +OP4 E006AF 0 +OP4 E006B0 0 +OP4 E006B1 0 +OP4 E006B2 0 +OP4 E006B3 0 +OP4 E006B4 0 +OP4 E006B5 0 +OP4 E006B6 0 +OP4 E006B7 0 +OP4 E006B8 0 +OP4 E006B9 0 +OP4 E006BA 0 +OP4 E006BB 0 +OP4 E006BC 0 +OP4 E006BD 0 +OP4 E006BE 0 +OP4 E006BF 0 +OP4 E006C0 0 +OP4 E006C1 0 +OP4 E006C2 0 +OP4 E006C3 0 +OP4 E006C4 0 +OP4 E006C5 0 +OP4 E006C6 0 +OP4 E006C7 0 +OP4 E006C8 0 +OP4 E006C9 0 +OP4 E006CA 0 +OP4 E006CB 0 +OP4 E006CC 0 +OP4 E006CD 0 +OP4 E006CE 0 +OP4 E006CF 0 +OP4 E006D0 0 +OP4 E006D1 0 +OP4 E006D2 0 +OP4 E006D3 0 +OP4 E006D4 0 +OP4 E006D5 0 +OP4 E006D6 0 +OP4 E006D7 0 +OP4 E006D8 0 +OP4 E006D9 0 +OP4 E006DA 0 +OP4 E006DB 0 +OP4 E006DC 0 +OP4 E006DD 0 +OP4 E006DE 0 +OP4 E006DF 0 +OP4 E006E0 0 +OP4 E006E1 0 +OP4 E006E2 0 +OP4 E006E3 0 +OP4 E006E4 0 +OP4 E006E5 0 +OP4 E006E6 0 +OP4 E006E7 0 +OP4 E006E8 0 +OP4 E006E9 0 +OP4 E006EA 0 +OP4 E006EB 0 +OP4 E006EC 0 +OP4 E006ED 0 +OP4 E006EE 0 +OP4 E006EF 0 +OP4 E006F0 0 +OP4 E006F1 0 +OP4 E006F2 0 +OP4 E006F3 0 +OP4 E006F4 0 +OP4 E006F5 0 +OP4 E006F6 0 +OP4 E006F7 0 +OP4 E006F8 0 +OP4 E006F9 0 +OP4 E006FA 0 +OP4 E006FB 0 +OP4 E006FC 0 +OP4 E006FD 0 +OP4 E006FE 0 +OP4 E006FF 0 +OP4 E00700 0 +OP4 E00701 0 +OP4 E00702 0 +OP4 E00703 0 +OP4 E00704 0 +OP4 E00705 0 +OP4 E00706 0 +OP4 E00707 0 +OP4 E00708 0 +OP4 E00709 0 +OP4 E0070A 0 +OP4 E0070B 0 +OP4 E0070C 0 +OP4 E0070D 0 +OP4 E0070E 0 +OP4 E0070F 0 +OP4 E00710 0 +OP4 E00711 0 +OP4 E00712 0 +OP4 E00713 0 +OP4 E00714 0 +OP4 E00715 0 +OP4 E00716 0 +OP4 E00717 0 +OP4 E00718 0 +OP4 E00719 0 +OP4 E0071A 0 +OP4 E0071B 0 +OP4 E0071C 0 +OP4 E0071D 0 +OP4 E0071E 0 +OP4 E0071F 0 +OP4 E00720 0 +OP4 E00721 0 +OP4 E00722 0 +OP4 E00723 0 +OP4 E00724 0 +OP4 E00725 0 +OP4 E00726 0 +OP4 E00727 0 +OP4 E00728 0 +OP4 E00729 0 +OP4 E0072A 0 +OP4 E0072B 0 +OP4 E0072C 0 +OP4 E0072D 0 +OP4 E0072E 0 +OP4 E0072F 0 +OP4 E00730 0 +OP4 E00731 0 +OP4 E00732 0 +OP4 E00733 0 +OP4 E00734 0 +OP4 E00735 0 +OP4 E00736 0 +OP4 E00737 0 +OP4 E00738 0 +OP4 E00739 0 +OP4 E0073A 0 +OP4 E0073B 0 +OP4 E0073C 0 +OP4 E0073D 0 +OP4 E0073E 0 +OP4 E0073F 0 +OP4 E00740 0 +OP4 E00741 0 +OP4 E00742 0 +OP4 E00743 0 +OP4 E00744 0 +OP4 E00745 0 +OP4 E00746 0 +OP4 E00747 0 +OP4 E00748 0 +OP4 E00749 0 +OP4 E0074A 0 +OP4 E0074B 0 +OP4 E0074C 0 +OP4 E0074D 0 +OP4 E0074E 0 +OP4 E0074F 0 +OP4 E00750 0 +OP4 E00751 0 +OP4 E00752 0 +OP4 E00753 0 +OP4 E00754 0 +OP4 E00755 0 +OP4 E00756 0 +OP4 E00757 0 +OP4 E00758 0 +OP4 E00759 0 +OP4 E0075A 0 +OP4 E0075B 0 +OP4 E0075C 0 +OP4 E0075D 0 +OP4 E0075E 0 +OP4 E0075F 0 +OP4 E00760 0 +OP4 E00761 0 +OP4 E00762 0 +OP4 E00763 0 +OP4 E00764 0 +OP4 E00765 0 +OP4 E00766 0 +OP4 E00767 0 +OP4 E00768 0 +OP4 E00769 0 +OP4 E0076A 0 +OP4 E0076B 0 +OP4 E0076C 0 +OP4 E0076D 0 +OP4 E0076E 0 +OP4 E0076F 0 +OP4 E00770 0 +OP4 E00771 0 +OP4 E00772 0 +OP4 E00773 0 +OP4 E00774 0 +OP4 E00775 0 +OP4 E00776 0 +OP4 E00777 0 +OP4 E00778 0 +OP4 E00779 0 +OP4 E0077A 0 +OP4 E0077B 0 +OP4 E0077C 0 +OP4 E0077D 0 +OP4 E0077E 0 +OP4 E0077F 0 +OP4 E00780 0 +OP4 E00781 0 +OP4 E00782 0 +OP4 E00783 0 +OP4 E00784 0 +OP4 E00785 0 +OP4 E00786 0 +OP4 E00787 0 +OP4 E00788 0 +OP4 E00789 0 +OP4 E0078A 0 +OP4 E0078B 0 +OP4 E0078C 0 +OP4 E0078D 0 +OP4 E0078E 0 +OP4 E0078F 0 +OP4 E00790 0 +OP4 E00791 0 +OP4 E00792 0 +OP4 E00793 0 +OP4 E00794 0 +OP4 E00795 0 +OP4 E00796 0 +OP4 E00797 0 +OP4 E00798 0 +OP4 E00799 0 +OP4 E0079A 0 +OP4 E0079B 0 +OP4 E0079C 0 +OP4 E0079D 0 +OP4 E0079E 0 +OP4 E0079F 0 +OP4 E007A0 0 +OP4 E007A1 0 +OP4 E007A2 0 +OP4 E007A3 0 +OP4 E007A4 0 +OP4 E007A5 0 +OP4 E007A6 0 +OP4 E007A7 0 +OP4 E007A8 0 +OP4 E007A9 0 +OP4 E007AA 0 +OP4 E007AB 0 +OP4 E007AC 0 +OP4 E007AD 0 +OP4 E007AE 0 +OP4 E007AF 0 +OP4 E007B0 0 +OP4 E007B1 0 +OP4 E007B2 0 +OP4 E007B3 0 +OP4 E007B4 0 +OP4 E007B5 0 +OP4 E007B6 0 +OP4 E007B7 0 +OP4 E007B8 0 +OP4 E007B9 0 +OP4 E007BA 0 +OP4 E007BB 0 +OP4 E007BC 0 +OP4 E007BD 0 +OP4 E007BE 0 +OP4 E007BF 0 +OP4 E007C0 0 +OP4 E007C1 0 +OP4 E007C2 0 +OP4 E007C3 0 +OP4 E007C4 0 +OP4 E007C5 0 +OP4 E007C6 0 +OP4 E007C7 0 +OP4 E007C8 0 +OP4 E007C9 0 +OP4 E007CA 0 +OP4 E007CB 0 +OP4 E007CC 0 +OP4 E007CD 0 +OP4 E007CE 0 +OP4 E007CF 0 +OP4 E007D0 0 +OP4 E007D1 0 +OP4 E007D2 0 +OP4 E007D3 0 +OP4 E007D4 0 +OP4 E007D5 0 +OP4 E007D6 0 +OP4 E007D7 0 +OP4 E007D8 0 +OP4 E007D9 0 +OP4 E007DA 0 +OP4 E007DB 0 +OP4 E007DC 0 +OP4 E007DD 0 +OP4 E007DE 0 +OP4 E007DF 0 +OP4 E007E0 0 +OP4 E007E1 0 +OP4 E007E2 0 +OP4 E007E3 0 +OP4 E007E4 0 +OP4 E007E5 0 +OP4 E007E6 0 +OP4 E007E7 0 +OP4 E007E8 0 +OP4 E007E9 0 +OP4 E007EA 0 +OP4 E007EB 0 +OP4 E007EC 0 +OP4 E007ED 0 +OP4 E007EE 0 +OP4 E007EF 0 +OP4 E007F0 0 +OP4 E007F1 0 +OP4 E007F2 0 +OP4 E007F3 0 +OP4 E007F4 0 +OP4 E007F5 0 +OP4 E007F6 0 +OP4 E007F7 0 +OP4 E007F8 0 +OP4 E007F9 0 +OP4 E007FA 0 +OP4 E007FB 0 +OP4 E007FC 0 +OP4 E007FD 0 +OP4 E007FE 0 +OP4 E007FF 0 +OP4 E00800 0 +OP4 E00801 0 +OP4 E00802 0 +OP4 E00803 0 +OP4 E00804 0 +OP4 E00805 0 +OP4 E00806 0 +OP4 E00807 0 +OP4 E00808 0 +OP4 E00809 0 +OP4 E0080A 0 +OP4 E0080B 0 +OP4 E0080C 0 +OP4 E0080D 0 +OP4 E0080E 0 +OP4 E0080F 0 +OP4 E00810 0 +OP4 E00811 0 +OP4 E00812 0 +OP4 E00813 0 +OP4 E00814 0 +OP4 E00815 0 +OP4 E00816 0 +OP4 E00817 0 +OP4 E00818 0 +OP4 E00819 0 +OP4 E0081A 0 +OP4 E0081B 0 +OP4 E0081C 0 +OP4 E0081D 0 +OP4 E0081E 0 +OP4 E0081F 0 +OP4 E00820 0 +OP4 E00821 0 +OP4 E00822 0 +OP4 E00823 0 +OP4 E00824 0 +OP4 E00825 0 +OP4 E00826 0 +OP4 E00827 0 +OP4 E00828 0 +OP4 E00829 0 +OP4 E0082A 0 +OP4 E0082B 0 +OP4 E0082C 0 +OP4 E0082D 0 +OP4 E0082E 0 +OP4 E0082F 0 +OP4 E00830 0 +OP4 E00831 0 +OP4 E00832 0 +OP4 E00833 0 +OP4 E00834 0 +OP4 E00835 0 +OP4 E00836 0 +OP4 E00837 0 +OP4 E00838 0 +OP4 E00839 0 +OP4 E0083A 0 +OP4 E0083B 0 +OP4 E0083C 0 +OP4 E0083D 0 +OP4 E0083E 0 +OP4 E0083F 0 +OP4 E00840 0 +OP4 E00841 0 +OP4 E00842 0 +OP4 E00843 0 +OP4 E00844 0 +OP4 E00845 0 +OP4 E00846 0 +OP4 E00847 0 +OP4 E00848 0 +OP4 E00849 0 +OP4 E0084A 0 +OP4 E0084B 0 +OP4 E0084C 0 +OP4 E0084D 0 +OP4 E0084E 0 +OP4 E0084F 0 +OP4 E00850 0 +OP4 E00851 0 +OP4 E00852 0 +OP4 E00853 0 +OP4 E00854 0 +OP4 E00855 0 +OP4 E00856 0 +OP4 E00857 0 +OP4 E00858 0 +OP4 E00859 0 +OP4 E0085A 0 +OP4 E0085B 0 +OP4 E0085C 0 +OP4 E0085D 0 +OP4 E0085E 0 +OP4 E0085F 0 +OP4 E00860 0 +OP4 E00861 0 +OP4 E00862 0 +OP4 E00863 0 +OP4 E00864 0 +OP4 E00865 0 +OP4 E00866 0 +OP4 E00867 0 +OP4 E00868 0 +OP4 E00869 0 +OP4 E0086A 0 +OP4 E0086B 0 +OP4 E0086C 0 +OP4 E0086D 0 +OP4 E0086E 0 +OP4 E0086F 0 +OP4 E00870 0 +OP4 E00871 0 +OP4 E00872 0 +OP4 E00873 0 +OP4 E00874 0 +OP4 E00875 0 +OP4 E00876 0 +OP4 E00877 0 +OP4 E00878 0 +OP4 E00879 0 +OP4 E0087A 0 +OP4 E0087B 0 +OP4 E0087C 0 +OP4 E0087D 0 +OP4 E0087E 0 +OP4 E0087F 0 +OP4 E00880 0 +OP4 E00881 0 +OP4 E00882 0 +OP4 E00883 0 +OP4 E00884 0 +OP4 E00885 0 +OP4 E00886 0 +OP4 E00887 0 +OP4 E00888 0 +OP4 E00889 0 +OP4 E0088A 0 +OP4 E0088B 0 +OP4 E0088C 0 +OP4 E0088D 0 +OP4 E0088E 0 +OP4 E0088F 0 +OP4 E00890 0 +OP4 E00891 0 +OP4 E00892 0 +OP4 E00893 0 +OP4 E00894 0 +OP4 E00895 0 +OP4 E00896 0 +OP4 E00897 0 +OP4 E00898 0 +OP4 E00899 0 +OP4 E0089A 0 +OP4 E0089B 0 +OP4 E0089C 0 +OP4 E0089D 0 +OP4 E0089E 0 +OP4 E0089F 0 +OP4 E008A0 0 +OP4 E008A1 0 +OP4 E008A2 0 +OP4 E008A3 0 +OP4 E008A4 0 +OP4 E008A5 0 +OP4 E008A6 0 +OP4 E008A7 0 +OP4 E008A8 0 +OP4 E008A9 0 +OP4 E008AA 0 +OP4 E008AB 0 +OP4 E008AC 0 +OP4 E008AD 0 +OP4 E008AE 0 +OP4 E008AF 0 +OP4 E008B0 0 +OP4 E008B1 0 +OP4 E008B2 0 +OP4 E008B3 0 +OP4 E008B4 0 +OP4 E008B5 0 +OP4 E008B6 0 +OP4 E008B7 0 +OP4 E008B8 0 +OP4 E008B9 0 +OP4 E008BA 0 +OP4 E008BB 0 +OP4 E008BC 0 +OP4 E008BD 0 +OP4 E008BE 0 +OP4 E008BF 0 +OP4 E008C0 0 +OP4 E008C1 0 +OP4 E008C2 0 +OP4 E008C3 0 +OP4 E008C4 0 +OP4 E008C5 0 +OP4 E008C6 0 +OP4 E008C7 0 +OP4 E008C8 0 +OP4 E008C9 0 +OP4 E008CA 0 +OP4 E008CB 0 +OP4 E008CC 0 +OP4 E008CD 0 +OP4 E008CE 0 +OP4 E008CF 0 +OP4 E008D0 0 +OP4 E008D1 0 +OP4 E008D2 0 +OP4 E008D3 0 +OP4 E008D4 0 +OP4 E008D5 0 +OP4 E008D6 0 +OP4 E008D7 0 +OP4 E008D8 0 +OP4 E008D9 0 +OP4 E008DA 0 +OP4 E008DB 0 +OP4 E008DC 0 +OP4 E008DD 0 +OP4 E008DE 0 +OP4 E008DF 0 +OP4 E008E0 0 +OP4 E008E1 0 +OP4 E008E2 0 +OP4 E008E3 0 +OP4 E008E4 0 +OP4 E008E5 0 +OP4 E008E6 0 +OP4 E008E7 0 +OP4 E008E8 0 +OP4 E008E9 0 +OP4 E008EA 0 +OP4 E008EB 0 +OP4 E008EC 0 +OP4 E008ED 0 +OP4 E008EE 0 +OP4 E008EF 0 +OP4 E008F0 0 +OP4 E008F1 0 +OP4 E008F2 0 +OP4 E008F3 0 +OP4 E008F4 0 +OP4 E008F5 0 +OP4 E008F6 0 +OP4 E008F7 0 +OP4 E008F8 0 +OP4 E008F9 0 +OP4 E008FA 0 +OP4 E008FB 0 +OP4 E008FC 0 +OP4 E008FD 0 +OP4 E008FE 0 +OP4 E008FF 0 +OP4 E00900 0 +OP4 E00901 0 +OP4 E00902 0 +OP4 E00903 0 +OP4 E00904 0 +OP4 E00905 0 +OP4 E00906 0 +OP4 E00907 0 +OP4 E00908 0 +OP4 E00909 0 +OP4 E0090A 0 +OP4 E0090B 0 +OP4 E0090C 0 +OP4 E0090D 0 +OP4 E0090E 0 +OP4 E0090F 0 +OP4 E00910 0 +OP4 E00911 0 +OP4 E00912 0 +OP4 E00913 0 +OP4 E00914 0 +OP4 E00915 0 +OP4 E00916 0 +OP4 E00917 0 +OP4 E00918 0 +OP4 E00919 0 +OP4 E0091A 0 +OP4 E0091B 0 +OP4 E0091C 0 +OP4 E0091D 0 +OP4 E0091E 0 +OP4 E0091F 0 +OP4 E00920 0 +OP4 E00921 0 +OP4 E00922 0 +OP4 E00923 0 +OP4 E00924 0 +OP4 E00925 0 +OP4 E00926 0 +OP4 E00927 0 +OP4 E00928 0 +OP4 E00929 0 +OP4 E0092A 0 +OP4 E0092B 0 +OP4 E0092C 0 +OP4 E0092D 0 +OP4 E0092E 0 +OP4 E0092F 0 +OP4 E00930 0 +OP4 E00931 0 +OP4 E00932 0 +OP4 E00933 0 +OP4 E00934 0 +OP4 E00935 0 +OP4 E00936 0 +OP4 E00937 0 +OP4 E00938 0 +OP4 E00939 0 +OP4 E0093A 0 +OP4 E0093B 0 +OP4 E0093C 0 +OP4 E0093D 0 +OP4 E0093E 0 +OP4 E0093F 0 +OP4 E00940 0 +OP4 E00941 0 +OP4 E00942 0 +OP4 E00943 0 +OP4 E00944 0 +OP4 E00945 0 +OP4 E00946 0 +OP4 E00947 0 +OP4 E00948 0 +OP4 E00949 0 +OP4 E0094A 0 +OP4 E0094B 0 +OP4 E0094C 0 +OP4 E0094D 0 +OP4 E0094E 0 +OP4 E0094F 0 +OP4 E00950 0 +OP4 E00951 0 +OP4 E00952 0 +OP4 E00953 0 +OP4 E00954 0 +OP4 E00955 0 +OP4 E00956 0 +OP4 E00957 0 +OP4 E00958 0 +OP4 E00959 0 +OP4 E0095A 0 +OP4 E0095B 0 +OP4 E0095C 0 +OP4 E0095D 0 +OP4 E0095E 0 +OP4 E0095F 0 +OP4 E00960 0 +OP4 E00961 0 +OP4 E00962 0 +OP4 E00963 0 +OP4 E00964 0 +OP4 E00965 0 +OP4 E00966 0 +OP4 E00967 0 +OP4 E00968 0 +OP4 E00969 0 +OP4 E0096A 0 +OP4 E0096B 0 +OP4 E0096C 0 +OP4 E0096D 0 +OP4 E0096E 0 +OP4 E0096F 0 +OP4 E00970 0 +OP4 E00971 0 +OP4 E00972 0 +OP4 E00973 0 +OP4 E00974 0 +OP4 E00975 0 +OP4 E00976 0 +OP4 E00977 0 +OP4 E00978 0 +OP4 E00979 0 +OP4 E0097A 0 +OP4 E0097B 0 +OP4 E0097C 0 +OP4 E0097D 0 +OP4 E0097E 0 +OP4 E0097F 0 +OP4 E00980 0 +OP4 E00981 0 +OP4 E00982 0 +OP4 E00983 0 +OP4 E00984 0 +OP4 E00985 0 +OP4 E00986 0 +OP4 E00987 0 +OP4 E00988 0 +OP4 E00989 0 +OP4 E0098A 0 +OP4 E0098B 0 +OP4 E0098C 0 +OP4 E0098D 0 +OP4 E0098E 0 +OP4 E0098F 0 +OP4 E00990 0 +OP4 E00991 0 +OP4 E00992 0 +OP4 E00993 0 +OP4 E00994 0 +OP4 E00995 0 +OP4 E00996 0 +OP4 E00997 0 +OP4 E00998 0 +OP4 E00999 0 +OP4 E0099A 0 +OP4 E0099B 0 +OP4 E0099C 0 +OP4 E0099D 0 +OP4 E0099E 0 +OP4 E0099F 0 +OP4 E009A0 0 +OP4 E009A1 0 +OP4 E009A2 0 +OP4 E009A3 0 +OP4 E009A4 0 +OP4 E009A5 0 +OP4 E009A6 0 +OP4 E009A7 0 +OP4 E009A8 0 +OP4 E009A9 0 +OP4 E009AA 0 +OP4 E009AB 0 +OP4 E009AC 0 +OP4 E009AD 0 +OP4 E009AE 0 +OP4 E009AF 0 +OP4 E009B0 0 +OP4 E009B1 0 +OP4 E009B2 0 +OP4 E009B3 0 +OP4 E009B4 0 +OP4 E009B5 0 +OP4 E009B6 0 +OP4 E009B7 0 +OP4 E009B8 0 +OP4 E009B9 0 +OP4 E009BA 0 +OP4 E009BB 0 +OP4 E009BC 0 +OP4 E009BD 0 +OP4 E009BE 0 +OP4 E009BF 0 +OP4 E009C0 0 +OP4 E009C1 0 +OP4 E009C2 0 +OP4 E009C3 0 +OP4 E009C4 0 +OP4 E009C5 0 +OP4 E009C6 0 +OP4 E009C7 0 +OP4 E009C8 0 +OP4 E009C9 0 +OP4 E009CA 0 +OP4 E009CB 0 +OP4 E009CC 0 +OP4 E009CD 0 +OP4 E009CE 0 +OP4 E009CF 0 +OP4 E009D0 0 +OP4 E009D1 0 +OP4 E009D2 0 +OP4 E009D3 0 +OP4 E009D4 0 +OP4 E009D5 0 +OP4 E009D6 0 +OP4 E009D7 0 +OP4 E009D8 0 +OP4 E009D9 0 +OP4 E009DA 0 +OP4 E009DB 0 +OP4 E009DC 0 +OP4 E009DD 0 +OP4 E009DE 0 +OP4 E009DF 0 +OP4 E009E0 0 +OP4 E009E1 0 +OP4 E009E2 0 +OP4 E009E3 0 +OP4 E009E4 0 +OP4 E009E5 0 +OP4 E009E6 0 +OP4 E009E7 0 +OP4 E009E8 0 +OP4 E009E9 0 +OP4 E009EA 0 +OP4 E009EB 0 +OP4 E009EC 0 +OP4 E009ED 0 +OP4 E009EE 0 +OP4 E009EF 0 +OP4 E009F0 0 +OP4 E009F1 0 +OP4 E009F2 0 +OP4 E009F3 0 +OP4 E009F4 0 +OP4 E009F5 0 +OP4 E009F6 0 +OP4 E009F7 0 +OP4 E009F8 0 +OP4 E009F9 0 +OP4 E009FA 0 +OP4 E009FB 0 +OP4 E009FC 0 +OP4 E009FD 0 +OP4 E009FE 0 +OP4 E009FF 0 +OP4 E00A00 0 +OP4 E00A01 0 +OP4 E00A02 0 +OP4 E00A03 0 +OP4 E00A04 0 +OP4 E00A05 0 +OP4 E00A06 0 +OP4 E00A07 0 +OP4 E00A08 0 +OP4 E00A09 0 +OP4 E00A0A 0 +OP4 E00A0B 0 +OP4 E00A0C 0 +OP4 E00A0D 0 +OP4 E00A0E 0 +OP4 E00A0F 0 +OP4 E00A10 0 +OP4 E00A11 0 +OP4 E00A12 0 +OP4 E00A13 0 +OP4 E00A14 0 +OP4 E00A15 0 +OP4 E00A16 0 +OP4 E00A17 0 +OP4 E00A18 0 +OP4 E00A19 0 +OP4 E00A1A 0 +OP4 E00A1B 0 +OP4 E00A1C 0 +OP4 E00A1D 0 +OP4 E00A1E 0 +OP4 E00A1F 0 +OP4 E00A20 0 +OP4 E00A21 0 +OP4 E00A22 0 +OP4 E00A23 0 +OP4 E00A24 0 +OP4 E00A25 0 +OP4 E00A26 0 +OP4 E00A27 0 +OP4 E00A28 0 +OP4 E00A29 0 +OP4 E00A2A 0 +OP4 E00A2B 0 +OP4 E00A2C 0 +OP4 E00A2D 0 +OP4 E00A2E 0 +OP4 E00A2F 0 +OP4 E00A30 0 +OP4 E00A31 0 +OP4 E00A32 0 +OP4 E00A33 0 +OP4 E00A34 0 +OP4 E00A35 0 +OP4 E00A36 0 +OP4 E00A37 0 +OP4 E00A38 0 +OP4 E00A39 0 +OP4 E00A3A 0 +OP4 E00A3B 0 +OP4 E00A3C 0 +OP4 E00A3D 0 +OP4 E00A3E 0 +OP4 E00A3F 0 +OP4 E00A40 0 +OP4 E00A41 0 +OP4 E00A42 0 +OP4 E00A43 0 +OP4 E00A44 0 +OP4 E00A45 0 +OP4 E00A46 0 +OP4 E00A47 0 +OP4 E00A48 0 +OP4 E00A49 0 +OP4 E00A4A 0 +OP4 E00A4B 0 +OP4 E00A4C 0 +OP4 E00A4D 0 +OP4 E00A4E 0 +OP4 E00A4F 0 +OP4 E00A50 0 +OP4 E00A51 0 +OP4 E00A52 0 +OP4 E00A53 0 +OP4 E00A54 0 +OP4 E00A55 0 +OP4 E00A56 0 +OP4 E00A57 0 +OP4 E00A58 0 +OP4 E00A59 0 +OP4 E00A5A 0 +OP4 E00A5B 0 +OP4 E00A5C 0 +OP4 E00A5D 0 +OP4 E00A5E 0 +OP4 E00A5F 0 +OP4 E00A60 0 +OP4 E00A61 0 +OP4 E00A62 0 +OP4 E00A63 0 +OP4 E00A64 0 +OP4 E00A65 0 +OP4 E00A66 0 +OP4 E00A67 0 +OP4 E00A68 0 +OP4 E00A69 0 +OP4 E00A6A 0 +OP4 E00A6B 0 +OP4 E00A6C 0 +OP4 E00A6D 0 +OP4 E00A6E 0 +OP4 E00A6F 0 +OP4 E00A70 0 +OP4 E00A71 0 +OP4 E00A72 0 +OP4 E00A73 0 +OP4 E00A74 0 +OP4 E00A75 0 +OP4 E00A76 0 +OP4 E00A77 0 +OP4 E00A78 0 +OP4 E00A79 0 +OP4 E00A7A 0 +OP4 E00A7B 0 +OP4 E00A7C 0 +OP4 E00A7D 0 +OP4 E00A7E 0 +OP4 E00A7F 0 +OP4 E00A80 0 +OP4 E00A81 0 +OP4 E00A82 0 +OP4 E00A83 0 +OP4 E00A84 0 +OP4 E00A85 0 +OP4 E00A86 0 +OP4 E00A87 0 +OP4 E00A88 0 +OP4 E00A89 0 +OP4 E00A8A 0 +OP4 E00A8B 0 +OP4 E00A8C 0 +OP4 E00A8D 0 +OP4 E00A8E 0 +OP4 E00A8F 0 +OP4 E00A90 0 +OP4 E00A91 0 +OP4 E00A92 0 +OP4 E00A93 0 +OP4 E00A94 0 +OP4 E00A95 0 +OP4 E00A96 0 +OP4 E00A97 0 +OP4 E00A98 0 +OP4 E00A99 0 +OP4 E00A9A 0 +OP4 E00A9B 0 +OP4 E00A9C 0 +OP4 E00A9D 0 +OP4 E00A9E 0 +OP4 E00A9F 0 +OP4 E00AA0 0 +OP4 E00AA1 0 +OP4 E00AA2 0 +OP4 E00AA3 0 +OP4 E00AA4 0 +OP4 E00AA5 0 +OP4 E00AA6 0 +OP4 E00AA7 0 +OP4 E00AA8 0 +OP4 E00AA9 0 +OP4 E00AAA 0 +OP4 E00AAB 0 +OP4 E00AAC 0 +OP4 E00AAD 0 +OP4 E00AAE 0 +OP4 E00AAF 0 +OP4 E00AB0 0 +OP4 E00AB1 0 +OP4 E00AB2 0 +OP4 E00AB3 0 +OP4 E00AB4 0 +OP4 E00AB5 0 +OP4 E00AB6 0 +OP4 E00AB7 0 +OP4 E00AB8 0 +OP4 E00AB9 0 +OP4 E00ABA 0 +OP4 E00ABB 0 +OP4 E00ABC 0 +OP4 E00ABD 0 +OP4 E00ABE 0 +OP4 E00ABF 0 +OP4 E00AC0 0 +OP4 E00AC1 0 +OP4 E00AC2 0 +OP4 E00AC3 0 +OP4 E00AC4 0 +OP4 E00AC5 0 +OP4 E00AC6 0 +OP4 E00AC7 0 +OP4 E00AC8 0 +OP4 E00AC9 0 +OP4 E00ACA 0 +OP4 E00ACB 0 +OP4 E00ACC 0 +OP4 E00ACD 0 +OP4 E00ACE 0 +OP4 E00ACF 0 +OP4 E00AD0 0 +OP4 E00AD1 0 +OP4 E00AD2 0 +OP4 E00AD3 0 +OP4 E00AD4 0 +OP4 E00AD5 0 +OP4 E00AD6 0 +OP4 E00AD7 0 +OP4 E00AD8 0 +OP4 E00AD9 0 +OP4 E00ADA 0 +OP4 E00ADB 0 +OP4 E00ADC 0 +OP4 E00ADD 0 +OP4 E00ADE 0 +OP4 E00ADF 0 +OP4 E00AE0 0 +OP4 E00AE1 0 +OP4 E00AE2 0 +OP4 E00AE3 0 +OP4 E00AE4 0 +OP4 E00AE5 0 +OP4 E00AE6 0 +OP4 E00AE7 0 +OP4 E00AE8 0 +OP4 E00AE9 0 +OP4 E00AEA 0 +OP4 E00AEB 0 +OP4 E00AEC 0 +OP4 E00AED 0 +OP4 E00AEE 0 +OP4 E00AEF 0 +OP4 E00AF0 0 +OP4 E00AF1 0 +OP4 E00AF2 0 +OP4 E00AF3 0 +OP4 E00AF4 0 +OP4 E00AF5 0 +OP4 E00AF6 0 +OP4 E00AF7 0 +OP4 E00AF8 0 +OP4 E00AF9 0 +OP4 E00AFA 0 +OP4 E00AFB 0 +OP4 E00AFC 0 +OP4 E00AFD 0 +OP4 E00AFE 0 +OP4 E00AFF 0 +OP4 E00B00 0 +OP4 E00B01 0 +OP4 E00B02 0 +OP4 E00B03 0 +OP4 E00B04 0 +OP4 E00B05 0 +OP4 E00B06 0 +OP4 E00B07 0 +OP4 E00B08 0 +OP4 E00B09 0 +OP4 E00B0A 0 +OP4 E00B0B 0 +OP4 E00B0C 0 +OP4 E00B0D 0 +OP4 E00B0E 0 +OP4 E00B0F 0 +OP4 E00B10 0 +OP4 E00B11 0 +OP4 E00B12 0 +OP4 E00B13 0 +OP4 E00B14 0 +OP4 E00B15 0 +OP4 E00B16 0 +OP4 E00B17 0 +OP4 E00B18 0 +OP4 E00B19 0 +OP4 E00B1A 0 +OP4 E00B1B 0 +OP4 E00B1C 0 +OP4 E00B1D 0 +OP4 E00B1E 0 +OP4 E00B1F 0 +OP4 E00B20 0 +OP4 E00B21 0 +OP4 E00B22 0 +OP4 E00B23 0 +OP4 E00B24 0 +OP4 E00B25 0 +OP4 E00B26 0 +OP4 E00B27 0 +OP4 E00B28 0 +OP4 E00B29 0 +OP4 E00B2A 0 +OP4 E00B2B 0 +OP4 E00B2C 0 +OP4 E00B2D 0 +OP4 E00B2E 0 +OP4 E00B2F 0 +OP4 E00B30 0 +OP4 E00B31 0 +OP4 E00B32 0 +OP4 E00B33 0 +OP4 E00B34 0 +OP4 E00B35 0 +OP4 E00B36 0 +OP4 E00B37 0 +OP4 E00B38 0 +OP4 E00B39 0 +OP4 E00B3A 0 +OP4 E00B3B 0 +OP4 E00B3C 0 +OP4 E00B3D 0 +OP4 E00B3E 0 +OP4 E00B3F 0 +OP4 E00B40 0 +OP4 E00B41 0 +OP4 E00B42 0 +OP4 E00B43 0 +OP4 E00B44 0 +OP4 E00B45 0 +OP4 E00B46 0 +OP4 E00B47 0 +OP4 E00B48 0 +OP4 E00B49 0 +OP4 E00B4A 0 +OP4 E00B4B 0 +OP4 E00B4C 0 +OP4 E00B4D 0 +OP4 E00B4E 0 +OP4 E00B4F 0 +OP4 E00B50 0 +OP4 E00B51 0 +OP4 E00B52 0 +OP4 E00B53 0 +OP4 E00B54 0 +OP4 E00B55 0 +OP4 E00B56 0 +OP4 E00B57 0 +OP4 E00B58 0 +OP4 E00B59 0 +OP4 E00B5A 0 +OP4 E00B5B 0 +OP4 E00B5C 0 +OP4 E00B5D 0 +OP4 E00B5E 0 +OP4 E00B5F 0 +OP4 E00B60 0 +OP4 E00B61 0 +OP4 E00B62 0 +OP4 E00B63 0 +OP4 E00B64 0 +OP4 E00B65 0 +OP4 E00B66 0 +OP4 E00B67 0 +OP4 E00B68 0 +OP4 E00B69 0 +OP4 E00B6A 0 +OP4 E00B6B 0 +OP4 E00B6C 0 +OP4 E00B6D 0 +OP4 E00B6E 0 +OP4 E00B6F 0 +OP4 E00B70 0 +OP4 E00B71 0 +OP4 E00B72 0 +OP4 E00B73 0 +OP4 E00B74 0 +OP4 E00B75 0 +OP4 E00B76 0 +OP4 E00B77 0 +OP4 E00B78 0 +OP4 E00B79 0 +OP4 E00B7A 0 +OP4 E00B7B 0 +OP4 E00B7C 0 +OP4 E00B7D 0 +OP4 E00B7E 0 +OP4 E00B7F 0 +OP4 E00B80 0 +OP4 E00B81 0 +OP4 E00B82 0 +OP4 E00B83 0 +OP4 E00B84 0 +OP4 E00B85 0 +OP4 E00B86 0 +OP4 E00B87 0 +OP4 E00B88 0 +OP4 E00B89 0 +OP4 E00B8A 0 +OP4 E00B8B 0 +OP4 E00B8C 0 +OP4 E00B8D 0 +OP4 E00B8E 0 +OP4 E00B8F 0 +OP4 E00B90 0 +OP4 E00B91 0 +OP4 E00B92 0 +OP4 E00B93 0 +OP4 E00B94 0 +OP4 E00B95 0 +OP4 E00B96 0 +OP4 E00B97 0 +OP4 E00B98 0 +OP4 E00B99 0 +OP4 E00B9A 0 +OP4 E00B9B 0 +OP4 E00B9C 0 +OP4 E00B9D 0 +OP4 E00B9E 0 +OP4 E00B9F 0 +OP4 E00BA0 0 +OP4 E00BA1 0 +OP4 E00BA2 0 +OP4 E00BA3 0 +OP4 E00BA4 0 +OP4 E00BA5 0 +OP4 E00BA6 0 +OP4 E00BA7 0 +OP4 E00BA8 0 +OP4 E00BA9 0 +OP4 E00BAA 0 +OP4 E00BAB 0 +OP4 E00BAC 0 +OP4 E00BAD 0 +OP4 E00BAE 0 +OP4 E00BAF 0 +OP4 E00BB0 0 +OP4 E00BB1 0 +OP4 E00BB2 0 +OP4 E00BB3 0 +OP4 E00BB4 0 +OP4 E00BB5 0 +OP4 E00BB6 0 +OP4 E00BB7 0 +OP4 E00BB8 0 +OP4 E00BB9 0 +OP4 E00BBA 0 +OP4 E00BBB 0 +OP4 E00BBC 0 +OP4 E00BBD 0 +OP4 E00BBE 0 +OP4 E00BBF 0 +OP4 E00BC0 0 +OP4 E00BC1 0 +OP4 E00BC2 0 +OP4 E00BC3 0 +OP4 E00BC4 0 +OP4 E00BC5 0 +OP4 E00BC6 0 +OP4 E00BC7 0 +OP4 E00BC8 0 +OP4 E00BC9 0 +OP4 E00BCA 0 +OP4 E00BCB 0 +OP4 E00BCC 0 +OP4 E00BCD 0 +OP4 E00BCE 0 +OP4 E00BCF 0 +OP4 E00BD0 0 +OP4 E00BD1 0 +OP4 E00BD2 0 +OP4 E00BD3 0 +OP4 E00BD4 0 +OP4 E00BD5 0 +OP4 E00BD6 0 +OP4 E00BD7 0 +OP4 E00BD8 0 +OP4 E00BD9 0 +OP4 E00BDA 0 +OP4 E00BDB 0 +OP4 E00BDC 0 +OP4 E00BDD 0 +OP4 E00BDE 0 +OP4 E00BDF 0 +OP4 E00BE0 0 +OP4 E00BE1 0 +OP4 E00BE2 0 +OP4 E00BE3 0 +OP4 E00BE4 0 +OP4 E00BE5 0 +OP4 E00BE6 0 +OP4 E00BE7 0 +OP4 E00BE8 0 +OP4 E00BE9 0 +OP4 E00BEA 0 +OP4 E00BEB 0 +OP4 E00BEC 0 +OP4 E00BED 0 +OP4 E00BEE 0 +OP4 E00BEF 0 +OP4 E00BF0 0 +OP4 E00BF1 0 +OP4 E00BF2 0 +OP4 E00BF3 0 +OP4 E00BF4 0 +OP4 E00BF5 0 +OP4 E00BF6 0 +OP4 E00BF7 0 +OP4 E00BF8 0 +OP4 E00BF9 0 +OP4 E00BFA 0 +OP4 E00BFB 0 +OP4 E00BFC 0 +OP4 E00BFD 0 +OP4 E00BFE 0 +OP4 E00BFF 0 +OP4 E00C00 0 +OP4 E00C01 0 +OP4 E00C02 0 +OP4 E00C03 0 +OP4 E00C04 0 +OP4 E00C05 0 +OP4 E00C06 0 +OP4 E00C07 0 +OP4 E00C08 0 +OP4 E00C09 0 +OP4 E00C0A 0 +OP4 E00C0B 0 +OP4 E00C0C 0 +OP4 E00C0D 0 +OP4 E00C0E 0 +OP4 E00C0F 0 +OP4 E00C10 0 +OP4 E00C11 0 +OP4 E00C12 0 +OP4 E00C13 0 +OP4 E00C14 0 +OP4 E00C15 0 +OP4 E00C16 0 +OP4 E00C17 0 +OP4 E00C18 0 +OP4 E00C19 0 +OP4 E00C1A 0 +OP4 E00C1B 0 +OP4 E00C1C 0 +OP4 E00C1D 0 +OP4 E00C1E 0 +OP4 E00C1F 0 +OP4 E00C20 0 +OP4 E00C21 0 +OP4 E00C22 0 +OP4 E00C23 0 +OP4 E00C24 0 +OP4 E00C25 0 +OP4 E00C26 0 +OP4 E00C27 0 +OP4 E00C28 0 +OP4 E00C29 0 +OP4 E00C2A 0 +OP4 E00C2B 0 +OP4 E00C2C 0 +OP4 E00C2D 0 +OP4 E00C2E 0 +OP4 E00C2F 0 +OP4 E00C30 0 +OP4 E00C31 0 +OP4 E00C32 0 +OP4 E00C33 0 +OP4 E00C34 0 +OP4 E00C35 0 +OP4 E00C36 0 +OP4 E00C37 0 +OP4 E00C38 0 +OP4 E00C39 0 +OP4 E00C3A 0 +OP4 E00C3B 0 +OP4 E00C3C 0 +OP4 E00C3D 0 +OP4 E00C3E 0 +OP4 E00C3F 0 +OP4 E00C40 0 +OP4 E00C41 0 +OP4 E00C42 0 +OP4 E00C43 0 +OP4 E00C44 0 +OP4 E00C45 0 +OP4 E00C46 0 +OP4 E00C47 0 +OP4 E00C48 0 +OP4 E00C49 0 +OP4 E00C4A 0 +OP4 E00C4B 0 +OP4 E00C4C 0 +OP4 E00C4D 0 +OP4 E00C4E 0 +OP4 E00C4F 0 +OP4 E00C50 0 +OP4 E00C51 0 +OP4 E00C52 0 +OP4 E00C53 0 +OP4 E00C54 0 +OP4 E00C55 0 +OP4 E00C56 0 +OP4 E00C57 0 +OP4 E00C58 0 +OP4 E00C59 0 +OP4 E00C5A 0 +OP4 E00C5B 0 +OP4 E00C5C 0 +OP4 E00C5D 0 +OP4 E00C5E 0 +OP4 E00C5F 0 +OP4 E00C60 0 +OP4 E00C61 0 +OP4 E00C62 0 +OP4 E00C63 0 +OP4 E00C64 0 +OP4 E00C65 0 +OP4 E00C66 0 +OP4 E00C67 0 +OP4 E00C68 0 +OP4 E00C69 0 +OP4 E00C6A 0 +OP4 E00C6B 0 +OP4 E00C6C 0 +OP4 E00C6D 0 +OP4 E00C6E 0 +OP4 E00C6F 0 +OP4 E00C70 0 +OP4 E00C71 0 +OP4 E00C72 0 +OP4 E00C73 0 +OP4 E00C74 0 +OP4 E00C75 0 +OP4 E00C76 0 +OP4 E00C77 0 +OP4 E00C78 0 +OP4 E00C79 0 +OP4 E00C7A 0 +OP4 E00C7B 0 +OP4 E00C7C 0 +OP4 E00C7D 0 +OP4 E00C7E 0 +OP4 E00C7F 0 +OP4 E00C80 0 +OP4 E00C81 0 +OP4 E00C82 0 +OP4 E00C83 0 +OP4 E00C84 0 +OP4 E00C85 0 +OP4 E00C86 0 +OP4 E00C87 0 +OP4 E00C88 0 +OP4 E00C89 0 +OP4 E00C8A 0 +OP4 E00C8B 0 +OP4 E00C8C 0 +OP4 E00C8D 0 +OP4 E00C8E 0 +OP4 E00C8F 0 +OP4 E00C90 0 +OP4 E00C91 0 +OP4 E00C92 0 +OP4 E00C93 0 +OP4 E00C94 0 +OP4 E00C95 0 +OP4 E00C96 0 +OP4 E00C97 0 +OP4 E00C98 0 +OP4 E00C99 0 +OP4 E00C9A 0 +OP4 E00C9B 0 +OP4 E00C9C 0 +OP4 E00C9D 0 +OP4 E00C9E 0 +OP4 E00C9F 0 +OP4 E00CA0 0 +OP4 E00CA1 0 +OP4 E00CA2 0 +OP4 E00CA3 0 +OP4 E00CA4 0 +OP4 E00CA5 0 +OP4 E00CA6 0 +OP4 E00CA7 0 +OP4 E00CA8 0 +OP4 E00CA9 0 +OP4 E00CAA 0 +OP4 E00CAB 0 +OP4 E00CAC 0 +OP4 E00CAD 0 +OP4 E00CAE 0 +OP4 E00CAF 0 +OP4 E00CB0 0 +OP4 E00CB1 0 +OP4 E00CB2 0 +OP4 E00CB3 0 +OP4 E00CB4 0 +OP4 E00CB5 0 +OP4 E00CB6 0 +OP4 E00CB7 0 +OP4 E00CB8 0 +OP4 E00CB9 0 +OP4 E00CBA 0 +OP4 E00CBB 0 +OP4 E00CBC 0 +OP4 E00CBD 0 +OP4 E00CBE 0 +OP4 E00CBF 0 +OP4 E00CC0 0 +OP4 E00CC1 0 +OP4 E00CC2 0 +OP4 E00CC3 0 +OP4 E00CC4 0 +OP4 E00CC5 0 +OP4 E00CC6 0 +OP4 E00CC7 0 +OP4 E00CC8 0 +OP4 E00CC9 0 +OP4 E00CCA 0 +OP4 E00CCB 0 +OP4 E00CCC 0 +OP4 E00CCD 0 +OP4 E00CCE 0 +OP4 E00CCF 0 +OP4 E00CD0 0 +OP4 E00CD1 0 +OP4 E00CD2 0 +OP4 E00CD3 0 +OP4 E00CD4 0 +OP4 E00CD5 0 +OP4 E00CD6 0 +OP4 E00CD7 0 +OP4 E00CD8 0 +OP4 E00CD9 0 +OP4 E00CDA 0 +OP4 E00CDB 0 +OP4 E00CDC 0 +OP4 E00CDD 0 +OP4 E00CDE 0 +OP4 E00CDF 0 +OP4 E00CE0 0 +OP4 E00CE1 0 +OP4 E00CE2 0 +OP4 E00CE3 0 +OP4 E00CE4 0 +OP4 E00CE5 0 +OP4 E00CE6 0 +OP4 E00CE7 0 +OP4 E00CE8 0 +OP4 E00CE9 0 +OP4 E00CEA 0 +OP4 E00CEB 0 +OP4 E00CEC 0 +OP4 E00CED 0 +OP4 E00CEE 0 +OP4 E00CEF 0 +OP4 E00CF0 0 +OP4 E00CF1 0 +OP4 E00CF2 0 +OP4 E00CF3 0 +OP4 E00CF4 0 +OP4 E00CF5 0 +OP4 E00CF6 0 +OP4 E00CF7 0 +OP4 E00CF8 0 +OP4 E00CF9 0 +OP4 E00CFA 0 +OP4 E00CFB 0 +OP4 E00CFC 0 +OP4 E00CFD 0 +OP4 E00CFE 0 +OP4 E00CFF 0 +OP4 E00D00 0 +OP4 E00D01 0 +OP4 E00D02 0 +OP4 E00D03 0 +OP4 E00D04 0 +OP4 E00D05 0 +OP4 E00D06 0 +OP4 E00D07 0 +OP4 E00D08 0 +OP4 E00D09 0 +OP4 E00D0A 0 +OP4 E00D0B 0 +OP4 E00D0C 0 +OP4 E00D0D 0 +OP4 E00D0E 0 +OP4 E00D0F 0 +OP4 E00D10 0 +OP4 E00D11 0 +OP4 E00D12 0 +OP4 E00D13 0 +OP4 E00D14 0 +OP4 E00D15 0 +OP4 E00D16 0 +OP4 E00D17 0 +OP4 E00D18 0 +OP4 E00D19 0 +OP4 E00D1A 0 +OP4 E00D1B 0 +OP4 E00D1C 0 +OP4 E00D1D 0 +OP4 E00D1E 0 +OP4 E00D1F 0 +OP4 E00D20 0 +OP4 E00D21 0 +OP4 E00D22 0 +OP4 E00D23 0 +OP4 E00D24 0 +OP4 E00D25 0 +OP4 E00D26 0 +OP4 E00D27 0 +OP4 E00D28 0 +OP4 E00D29 0 +OP4 E00D2A 0 +OP4 E00D2B 0 +OP4 E00D2C 0 +OP4 E00D2D 0 +OP4 E00D2E 0 +OP4 E00D2F 0 +OP4 E00D30 0 +OP4 E00D31 0 +OP4 E00D32 0 +OP4 E00D33 0 +OP4 E00D34 0 +OP4 E00D35 0 +OP4 E00D36 0 +OP4 E00D37 0 +OP4 E00D38 0 +OP4 E00D39 0 +OP4 E00D3A 0 +OP4 E00D3B 0 +OP4 E00D3C 0 +OP4 E00D3D 0 +OP4 E00D3E 0 +OP4 E00D3F 0 +OP4 E00D40 0 +OP4 E00D41 0 +OP4 E00D42 0 +OP4 E00D43 0 +OP4 E00D44 0 +OP4 E00D45 0 +OP4 E00D46 0 +OP4 E00D47 0 +OP4 E00D48 0 +OP4 E00D49 0 +OP4 E00D4A 0 +OP4 E00D4B 0 +OP4 E00D4C 0 +OP4 E00D4D 0 +OP4 E00D4E 0 +OP4 E00D4F 0 +OP4 E00D50 0 +OP4 E00D51 0 +OP4 E00D52 0 +OP4 E00D53 0 +OP4 E00D54 0 +OP4 E00D55 0 +OP4 E00D56 0 +OP4 E00D57 0 +OP4 E00D58 0 +OP4 E00D59 0 +OP4 E00D5A 0 +OP4 E00D5B 0 +OP4 E00D5C 0 +OP4 E00D5D 0 +OP4 E00D5E 0 +OP4 E00D5F 0 +OP4 E00D60 0 +OP4 E00D61 0 +OP4 E00D62 0 +OP4 E00D63 0 +OP4 E00D64 0 +OP4 E00D65 0 +OP4 E00D66 0 +OP4 E00D67 0 +OP4 E00D68 0 +OP4 E00D69 0 +OP4 E00D6A 0 +OP4 E00D6B 0 +OP4 E00D6C 0 +OP4 E00D6D 0 +OP4 E00D6E 0 +OP4 E00D6F 0 +OP4 E00D70 0 +OP4 E00D71 0 +OP4 E00D72 0 +OP4 E00D73 0 +OP4 E00D74 0 +OP4 E00D75 0 +OP4 E00D76 0 +OP4 E00D77 0 +OP4 E00D78 0 +OP4 E00D79 0 +OP4 E00D7A 0 +OP4 E00D7B 0 +OP4 E00D7C 0 +OP4 E00D7D 0 +OP4 E00D7E 0 +OP4 E00D7F 0 +OP4 E00D80 0 +OP4 E00D81 0 +OP4 E00D82 0 +OP4 E00D83 0 +OP4 E00D84 0 +OP4 E00D85 0 +OP4 E00D86 0 +OP4 E00D87 0 +OP4 E00D88 0 +OP4 E00D89 0 +OP4 E00D8A 0 +OP4 E00D8B 0 +OP4 E00D8C 0 +OP4 E00D8D 0 +OP4 E00D8E 0 +OP4 E00D8F 0 +OP4 E00D90 0 +OP4 E00D91 0 +OP4 E00D92 0 +OP4 E00D93 0 +OP4 E00D94 0 +OP4 E00D95 0 +OP4 E00D96 0 +OP4 E00D97 0 +OP4 E00D98 0 +OP4 E00D99 0 +OP4 E00D9A 0 +OP4 E00D9B 0 +OP4 E00D9C 0 +OP4 E00D9D 0 +OP4 E00D9E 0 +OP4 E00D9F 0 +OP4 E00DA0 0 +OP4 E00DA1 0 +OP4 E00DA2 0 +OP4 E00DA3 0 +OP4 E00DA4 0 +OP4 E00DA5 0 +OP4 E00DA6 0 +OP4 E00DA7 0 +OP4 E00DA8 0 +OP4 E00DA9 0 +OP4 E00DAA 0 +OP4 E00DAB 0 +OP4 E00DAC 0 +OP4 E00DAD 0 +OP4 E00DAE 0 +OP4 E00DAF 0 +OP4 E00DB0 0 +OP4 E00DB1 0 +OP4 E00DB2 0 +OP4 E00DB3 0 +OP4 E00DB4 0 +OP4 E00DB5 0 +OP4 E00DB6 0 +OP4 E00DB7 0 +OP4 E00DB8 0 +OP4 E00DB9 0 +OP4 E00DBA 0 +OP4 E00DBB 0 +OP4 E00DBC 0 +OP4 E00DBD 0 +OP4 E00DBE 0 +OP4 E00DBF 0 +OP4 E00DC0 0 +OP4 E00DC1 0 +OP4 E00DC2 0 +OP4 E00DC3 0 +OP4 E00DC4 0 +OP4 E00DC5 0 +OP4 E00DC6 0 +OP4 E00DC7 0 +OP4 E00DC8 0 +OP4 E00DC9 0 +OP4 E00DCA 0 +OP4 E00DCB 0 +OP4 E00DCC 0 +OP4 E00DCD 0 +OP4 E00DCE 0 +OP4 E00DCF 0 +OP4 E00DD0 0 +OP4 E00DD1 0 +OP4 E00DD2 0 +OP4 E00DD3 0 +OP4 E00DD4 0 +OP4 E00DD5 0 +OP4 E00DD6 0 +OP4 E00DD7 0 +OP4 E00DD8 0 +OP4 E00DD9 0 +OP4 E00DDA 0 +OP4 E00DDB 0 +OP4 E00DDC 0 +OP4 E00DDD 0 +OP4 E00DDE 0 +OP4 E00DDF 0 +OP4 E00DE0 0 +OP4 E00DE1 0 +OP4 E00DE2 0 +OP4 E00DE3 0 +OP4 E00DE4 0 +OP4 E00DE5 0 +OP4 E00DE6 0 +OP4 E00DE7 0 +OP4 E00DE8 0 +OP4 E00DE9 0 +OP4 E00DEA 0 +OP4 E00DEB 0 +OP4 E00DEC 0 +OP4 E00DED 0 +OP4 E00DEE 0 +OP4 E00DEF 0 +OP4 E00DF0 0 +OP4 E00DF1 0 +OP4 E00DF2 0 +OP4 E00DF3 0 +OP4 E00DF4 0 +OP4 E00DF5 0 +OP4 E00DF6 0 +OP4 E00DF7 0 +OP4 E00DF8 0 +OP4 E00DF9 0 +OP4 E00DFA 0 +OP4 E00DFB 0 +OP4 E00DFC 0 +OP4 E00DFD 0 +OP4 E00DFE 0 +OP4 E00DFF 0 +OP4 E00E00 0 +OP4 E00E01 0 +OP4 E00E02 0 +OP4 E00E03 0 +OP4 E00E04 0 +OP4 E00E05 0 +OP4 E00E06 0 +OP4 E00E07 0 +OP4 E00E08 0 +OP4 E00E09 0 +OP4 E00E0A 0 +OP4 E00E0B 0 +OP4 E00E0C 0 +OP4 E00E0D 0 +OP4 E00E0E 0 +OP4 E00E0F 0 +OP4 E00E10 0 +OP4 E00E11 0 +OP4 E00E12 0 +OP4 E00E13 0 +OP4 E00E14 0 +OP4 E00E15 0 +OP4 E00E16 0 +OP4 E00E17 0 +OP4 E00E18 0 +OP4 E00E19 0 +OP4 E00E1A 0 +OP4 E00E1B 0 +OP4 E00E1C 0 +OP4 E00E1D 0 +OP4 E00E1E 0 +OP4 E00E1F 0 +OP4 E00E20 0 +OP4 E00E21 0 +OP4 E00E22 0 +OP4 E00E23 0 +OP4 E00E24 0 +OP4 E00E25 0 +OP4 E00E26 0 +OP4 E00E27 0 +OP4 E00E28 0 +OP4 E00E29 0 +OP4 E00E2A 0 +OP4 E00E2B 0 +OP4 E00E2C 0 +OP4 E00E2D 0 +OP4 E00E2E 0 +OP4 E00E2F 0 +OP4 E00E30 0 +OP4 E00E31 0 +OP4 E00E32 0 +OP4 E00E33 0 +OP4 E00E34 0 +OP4 E00E35 0 +OP4 E00E36 0 +OP4 E00E37 0 +OP4 E00E38 0 +OP4 E00E39 0 +OP4 E00E3A 0 +OP4 E00E3B 0 +OP4 E00E3C 0 +OP4 E00E3D 0 +OP4 E00E3E 0 +OP4 E00E3F 0 +OP4 E00E40 0 +OP4 E00E41 0 +OP4 E00E42 0 +OP4 E00E43 0 +OP4 E00E44 0 +OP4 E00E45 0 +OP4 E00E46 0 +OP4 E00E47 0 +OP4 E00E48 0 +OP4 E00E49 0 +OP4 E00E4A 0 +OP4 E00E4B 0 +OP4 E00E4C 0 +OP4 E00E4D 0 +OP4 E00E4E 0 +OP4 E00E4F 0 +OP4 E00E50 0 +OP4 E00E51 0 +OP4 E00E52 0 +OP4 E00E53 0 +OP4 E00E54 0 +OP4 E00E55 0 +OP4 E00E56 0 +OP4 E00E57 0 +OP4 E00E58 0 +OP4 E00E59 0 +OP4 E00E5A 0 +OP4 E00E5B 0 +OP4 E00E5C 0 +OP4 E00E5D 0 +OP4 E00E5E 0 +OP4 E00E5F 0 +OP4 E00E60 0 +OP4 E00E61 0 +OP4 E00E62 0 +OP4 E00E63 0 +OP4 E00E64 0 +OP4 E00E65 0 +OP4 E00E66 0 +OP4 E00E67 0 +OP4 E00E68 0 +OP4 E00E69 0 +OP4 E00E6A 0 +OP4 E00E6B 0 +OP4 E00E6C 0 +OP4 E00E6D 0 +OP4 E00E6E 0 +OP4 E00E6F 0 +OP4 E00E70 0 +OP4 E00E71 0 +OP4 E00E72 0 +OP4 E00E73 0 +OP4 E00E74 0 +OP4 E00E75 0 +OP4 E00E76 0 +OP4 E00E77 0 +OP4 E00E78 0 +OP4 E00E79 0 +OP4 E00E7A 0 +OP4 E00E7B 0 +OP4 E00E7C 0 +OP4 E00E7D 0 +OP4 E00E7E 0 +OP4 E00E7F 0 +OP4 E00E80 0 +OP4 E00E81 0 +OP4 E00E82 0 +OP4 E00E83 0 +OP4 E00E84 0 +OP4 E00E85 0 +OP4 E00E86 0 +OP4 E00E87 0 +OP4 E00E88 0 +OP4 E00E89 0 +OP4 E00E8A 0 +OP4 E00E8B 0 +OP4 E00E8C 0 +OP4 E00E8D 0 +OP4 E00E8E 0 +OP4 E00E8F 0 +OP4 E00E90 0 +OP4 E00E91 0 +OP4 E00E92 0 +OP4 E00E93 0 +OP4 E00E94 0 +OP4 E00E95 0 +OP4 E00E96 0 +OP4 E00E97 0 +OP4 E00E98 0 +OP4 E00E99 0 +OP4 E00E9A 0 +OP4 E00E9B 0 +OP4 E00E9C 0 +OP4 E00E9D 0 +OP4 E00E9E 0 +OP4 E00E9F 0 +OP4 E00EA0 0 +OP4 E00EA1 0 +OP4 E00EA2 0 +OP4 E00EA3 0 +OP4 E00EA4 0 +OP4 E00EA5 0 +OP4 E00EA6 0 +OP4 E00EA7 0 +OP4 E00EA8 0 +OP4 E00EA9 0 +OP4 E00EAA 0 +OP4 E00EAB 0 +OP4 E00EAC 0 +OP4 E00EAD 0 +OP4 E00EAE 0 +OP4 E00EAF 0 +OP4 E00EB0 0 +OP4 E00EB1 0 +OP4 E00EB2 0 +OP4 E00EB3 0 +OP4 E00EB4 0 +OP4 E00EB5 0 +OP4 E00EB6 0 +OP4 E00EB7 0 +OP4 E00EB8 0 +OP4 E00EB9 0 +OP4 E00EBA 0 +OP4 E00EBB 0 +OP4 E00EBC 0 +OP4 E00EBD 0 +OP4 E00EBE 0 +OP4 E00EBF 0 +OP4 E00EC0 0 +OP4 E00EC1 0 +OP4 E00EC2 0 +OP4 E00EC3 0 +OP4 E00EC4 0 +OP4 E00EC5 0 +OP4 E00EC6 0 +OP4 E00EC7 0 +OP4 E00EC8 0 +OP4 E00EC9 0 +OP4 E00ECA 0 +OP4 E00ECB 0 +OP4 E00ECC 0 +OP4 E00ECD 0 +OP4 E00ECE 0 +OP4 E00ECF 0 +OP4 E00ED0 0 +OP4 E00ED1 0 +OP4 E00ED2 0 +OP4 E00ED3 0 +OP4 E00ED4 0 +OP4 E00ED5 0 +OP4 E00ED6 0 +OP4 E00ED7 0 +OP4 E00ED8 0 +OP4 E00ED9 0 +OP4 E00EDA 0 +OP4 E00EDB 0 +OP4 E00EDC 0 +OP4 E00EDD 0 +OP4 E00EDE 0 +OP4 E00EDF 0 +OP4 E00EE0 0 +OP4 E00EE1 0 +OP4 E00EE2 0 +OP4 E00EE3 0 +OP4 E00EE4 0 +OP4 E00EE5 0 +OP4 E00EE6 0 +OP4 E00EE7 0 +OP4 E00EE8 0 +OP4 E00EE9 0 +OP4 E00EEA 0 +OP4 E00EEB 0 +OP4 E00EEC 0 +OP4 E00EED 0 +OP4 E00EEE 0 +OP4 E00EEF 0 +OP4 E00EF0 0 +OP4 E00EF1 0 +OP4 E00EF2 0 +OP4 E00EF3 0 +OP4 E00EF4 0 +OP4 E00EF5 0 +OP4 E00EF6 0 +OP4 E00EF7 0 +OP4 E00EF8 0 +OP4 E00EF9 0 +OP4 E00EFA 0 +OP4 E00EFB 0 +OP4 E00EFC 0 +OP4 E00EFD 0 +OP4 E00EFE 0 +OP4 E00EFF 0 +OP4 E00F00 0 +OP4 E00F01 0 +OP4 E00F02 0 +OP4 E00F03 0 +OP4 E00F04 0 +OP4 E00F05 0 +OP4 E00F06 0 +OP4 E00F07 0 +OP4 E00F08 0 +OP4 E00F09 0 +OP4 E00F0A 0 +OP4 E00F0B 0 +OP4 E00F0C 0 +OP4 E00F0D 0 +OP4 E00F0E 0 +OP4 E00F0F 0 +OP4 E00F10 0 +OP4 E00F11 0 +OP4 E00F12 0 +OP4 E00F13 0 +OP4 E00F14 0 +OP4 E00F15 0 +OP4 E00F16 0 +OP4 E00F17 0 +OP4 E00F18 0 +OP4 E00F19 0 +OP4 E00F1A 0 +OP4 E00F1B 0 +OP4 E00F1C 0 +OP4 E00F1D 0 +OP4 E00F1E 0 +OP4 E00F1F 0 +OP4 E00F20 0 +OP4 E00F21 0 +OP4 E00F22 0 +OP4 E00F23 0 +OP4 E00F24 0 +OP4 E00F25 0 +OP4 E00F26 0 +OP4 E00F27 0 +OP4 E00F28 0 +OP4 E00F29 0 +OP4 E00F2A 0 +OP4 E00F2B 0 +OP4 E00F2C 0 +OP4 E00F2D 0 +OP4 E00F2E 0 +OP4 E00F2F 0 +OP4 E00F30 0 +OP4 E00F31 0 +OP4 E00F32 0 +OP4 E00F33 0 +OP4 E00F34 0 +OP4 E00F35 0 +OP4 E00F36 0 +OP4 E00F37 0 +OP4 E00F38 0 +OP4 E00F39 0 +OP4 E00F3A 0 +OP4 E00F3B 0 +OP4 E00F3C 0 +OP4 E00F3D 0 +OP4 E00F3E 0 +OP4 E00F3F 0 +OP4 E00F40 0 +OP4 E00F41 0 +OP4 E00F42 0 +OP4 E00F43 0 +OP4 E00F44 0 +OP4 E00F45 0 +OP4 E00F46 0 +OP4 E00F47 0 +OP4 E00F48 0 +OP4 E00F49 0 +OP4 E00F4A 0 +OP4 E00F4B 0 +OP4 E00F4C 0 +OP4 E00F4D 0 +OP4 E00F4E 0 +OP4 E00F4F 0 +OP4 E00F50 0 +OP4 E00F51 0 +OP4 E00F52 0 +OP4 E00F53 0 +OP4 E00F54 0 +OP4 E00F55 0 +OP4 E00F56 0 +OP4 E00F57 0 +OP4 E00F58 0 +OP4 E00F59 0 +OP4 E00F5A 0 +OP4 E00F5B 0 +OP4 E00F5C 0 +OP4 E00F5D 0 +OP4 E00F5E 0 +OP4 E00F5F 0 +OP4 E00F60 0 +OP4 E00F61 0 +OP4 E00F62 0 +OP4 E00F63 0 +OP4 E00F64 0 +OP4 E00F65 0 +OP4 E00F66 0 +OP4 E00F67 0 +OP4 E00F68 0 +OP4 E00F69 0 +OP4 E00F6A 0 +OP4 E00F6B 0 +OP4 E00F6C 0 +OP4 E00F6D 0 +OP4 E00F6E 0 +OP4 E00F6F 0 +OP4 E00F70 0 +OP4 E00F71 0 +OP4 E00F72 0 +OP4 E00F73 0 +OP4 E00F74 0 +OP4 E00F75 0 +OP4 E00F76 0 +OP4 E00F77 0 +OP4 E00F78 0 +OP4 E00F79 0 +OP4 E00F7A 0 +OP4 E00F7B 0 +OP4 E00F7C 0 +OP4 E00F7D 0 +OP4 E00F7E 0 +OP4 E00F7F 0 +OP4 E00F80 0 +OP4 E00F81 0 +OP4 E00F82 0 +OP4 E00F83 0 +OP4 E00F84 0 +OP4 E00F85 0 +OP4 E00F86 0 +OP4 E00F87 0 +OP4 E00F88 0 +OP4 E00F89 0 +OP4 E00F8A 0 +OP4 E00F8B 0 +OP4 E00F8C 0 +OP4 E00F8D 0 +OP4 E00F8E 0 +OP4 E00F8F 0 +OP4 E00F90 0 +OP4 E00F91 0 +OP4 E00F92 0 +OP4 E00F93 0 +OP4 E00F94 0 +OP4 E00F95 0 +OP4 E00F96 0 +OP4 E00F97 0 +OP4 E00F98 0 +OP4 E00F99 0 +OP4 E00F9A 0 +OP4 E00F9B 0 +OP4 E00F9C 0 +OP4 E00F9D 0 +OP4 E00F9E 0 +OP4 E00F9F 0 +OP4 E00FA0 0 +OP4 E00FA1 0 +OP4 E00FA2 0 +OP4 E00FA3 0 +OP4 E00FA4 0 +OP4 E00FA5 0 +OP4 E00FA6 0 +OP4 E00FA7 0 +OP4 E00FA8 0 +OP4 E00FA9 0 +OP4 E00FAA 0 +OP4 E00FAB 0 +OP4 E00FAC 0 +OP4 E00FAD 0 +OP4 E00FAE 0 +OP4 E00FAF 0 +OP4 E00FB0 0 +OP4 E00FB1 0 +OP4 E00FB2 0 +OP4 E00FB3 0 +OP4 E00FB4 0 +OP4 E00FB5 0 +OP4 E00FB6 0 +OP4 E00FB7 0 +OP4 E00FB8 0 +OP4 E00FB9 0 +OP4 E00FBA 0 +OP4 E00FBB 0 +OP4 E00FBC 0 +OP4 E00FBD 0 +OP4 E00FBE 0 +OP4 E00FBF 0 +OP4 E00FC0 0 +OP4 E00FC1 0 +OP4 E00FC2 0 +OP4 E00FC3 0 +OP4 E00FC4 0 +OP4 E00FC5 0 +OP4 E00FC6 0 +OP4 E00FC7 0 +OP4 E00FC8 0 +OP4 E00FC9 0 +OP4 E00FCA 0 +OP4 E00FCB 0 +OP4 E00FCC 0 +OP4 E00FCD 0 +OP4 E00FCE 0 +OP4 E00FCF 0 +OP4 E00FD0 0 +OP4 E00FD1 0 +OP4 E00FD2 0 +OP4 E00FD3 0 +OP4 E00FD4 0 +OP4 E00FD5 0 +OP4 E00FD6 0 +OP4 E00FD7 0 +OP4 E00FD8 0 +OP4 E00FD9 0 +OP4 E00FDA 0 +OP4 E00FDB 0 +OP4 E00FDC 0 +OP4 E00FDD 0 +OP4 E00FDE 0 +OP4 E00FDF 0 +OP4 E00FE0 0 +OP4 E00FE1 0 +OP4 E00FE2 0 +OP4 E00FE3 0 +OP4 E00FE4 0 +OP4 E00FE5 0 +OP4 E00FE6 0 +OP4 E00FE7 0 +OP4 E00FE8 0 +OP4 E00FE9 0 +OP4 E00FEA 0 +OP4 E00FEB 0 +OP4 E00FEC 0 +OP4 E00FED 0 +OP4 E00FEE 0 +OP4 E00FEF 0 +OP4 E00FF0 0 +OP4 E00FF1 0 +OP4 E00FF2 0 +OP4 E00FF3 0 +OP4 E00FF4 0 +OP4 E00FF5 0 +OP4 E00FF6 0 +OP4 E00FF7 0 +OP4 E00FF8 0 +OP4 E00FF9 0 +OP4 E00FFA 0 +OP4 E00FFB 0 +OP4 E00FFC 0 +OP4 E00FFD 0 +OP4 E00FFE 0 +OP4 E00FFF 0 +OP4 E01000 0 +OP4 E01001 0 +OP4 E01002 0 +OP4 E01003 0 +OP4 E01004 0 +OP4 E01005 0 +OP4 E01006 0 +OP4 E01007 0 +OP4 E01008 0 +OP4 E01009 0 +OP4 E0100A 0 +OP4 E0100B 0 +OP4 E0100C 0 +OP4 E0100D 0 +OP4 E0100E 0 +OP4 E0100F 0 +OP4 E01010 0 +OP4 E01011 0 +OP4 E01012 0 +OP4 E01013 0 +OP4 E01014 0 +OP4 E01015 0 +OP4 E01016 0 +OP4 E01017 0 +OP4 E01018 0 +OP4 E01019 0 +OP4 E0101A 0 +OP4 E0101B 0 +OP4 E0101C 0 +OP4 E0101D 0 +OP4 E0101E 0 +OP4 E0101F 0 +OP4 E01020 0 +OP4 E01021 0 +OP4 E01022 0 +OP4 E01023 0 +OP4 E01024 0 +OP4 E01025 0 +OP4 E01026 0 +OP4 E01027 0 +OP4 E01028 0 +OP4 E01029 0 +OP4 E0102A 0 +OP4 E0102B 0 +OP4 E0102C 0 +OP4 E0102D 0 +OP4 E0102E 0 +OP4 E0102F 0 +OP4 E01030 0 +OP4 E01031 0 +OP4 E01032 0 +OP4 E01033 0 +OP4 E01034 0 +OP4 E01035 0 +OP4 E01036 0 +OP4 E01037 0 +OP4 E01038 0 +OP4 E01039 0 +OP4 E0103A 0 +OP4 E0103B 0 +OP4 E0103C 0 +OP4 E0103D 0 +OP4 E0103E 0 +OP4 E0103F 0 +OP4 E01040 0 +OP4 E01041 0 +OP4 E01042 0 +OP4 E01043 0 +OP4 E01044 0 +OP4 E01045 0 +OP4 E01046 0 +OP4 E01047 0 +OP4 E01048 0 +OP4 E01049 0 +OP4 E0104A 0 +OP4 E0104B 0 +OP4 E0104C 0 +OP4 E0104D 0 +OP4 E0104E 0 +OP4 E0104F 0 +OP4 E01050 0 +OP4 E01051 0 +OP4 E01052 0 +OP4 E01053 0 +OP4 E01054 0 +OP4 E01055 0 +OP4 E01056 0 +OP4 E01057 0 +OP4 E01058 0 +OP4 E01059 0 +OP4 E0105A 0 +OP4 E0105B 0 +OP4 E0105C 0 +OP4 E0105D 0 +OP4 E0105E 0 +OP4 E0105F 0 +OP4 E01060 0 +OP4 E01061 0 +OP4 E01062 0 +OP4 E01063 0 +OP4 E01064 0 +OP4 E01065 0 +OP4 E01066 0 +OP4 E01067 0 +OP4 E01068 0 +OP4 E01069 0 +OP4 E0106A 0 +OP4 E0106B 0 +OP4 E0106C 0 +OP4 E0106D 0 +OP4 E0106E 0 +OP4 E0106F 0 +OP4 E01070 0 +OP4 E01071 0 +OP4 E01072 0 +OP4 E01073 0 +OP4 E01074 0 +OP4 E01075 0 +OP4 E01076 0 +OP4 E01077 0 +OP4 E01078 0 +OP4 E01079 0 +OP4 E0107A 0 +OP4 E0107B 0 +OP4 E0107C 0 +OP4 E0107D 0 +OP4 E0107E 0 +OP4 E0107F 0 +OP4 E01080 0 +OP4 E01081 0 +OP4 E01082 0 +OP4 E01083 0 +OP4 E01084 0 +OP4 E01085 0 +OP4 E01086 0 +OP4 E01087 0 +OP4 E01088 0 +OP4 E01089 0 +OP4 E0108A 0 +OP4 E0108B 0 +OP4 E0108C 0 +OP4 E0108D 0 +OP4 E0108E 0 +OP4 E0108F 0 +OP4 E01090 0 +OP4 E01091 0 +OP4 E01092 0 +OP4 E01093 0 +OP4 E01094 0 +OP4 E01095 0 +OP4 E01096 0 +OP4 E01097 0 +OP4 E01098 0 +OP4 E01099 0 +OP4 E0109A 0 +OP4 E0109B 0 +OP4 E0109C 0 +OP4 E0109D 0 +OP4 E0109E 0 +OP4 E0109F 0 +OP4 E010A0 0 +OP4 E010A1 0 +OP4 E010A2 0 +OP4 E010A3 0 +OP4 E010A4 0 +OP4 E010A5 0 +OP4 E010A6 0 +OP4 E010A7 0 +OP4 E010A8 0 +OP4 E010A9 0 +OP4 E010AA 0 +OP4 E010AB 0 +OP4 E010AC 0 +OP4 E010AD 0 +OP4 E010AE 0 +OP4 E010AF 0 +OP4 E010B0 0 +OP4 E010B1 0 +OP4 E010B2 0 +OP4 E010B3 0 +OP4 E010B4 0 +OP4 E010B5 0 +OP4 E010B6 0 +OP4 E010B7 0 +OP4 E010B8 0 +OP4 E010B9 0 +OP4 E010BA 0 +OP4 E010BB 0 +OP4 E010BC 0 +OP4 E010BD 0 +OP4 E010BE 0 +OP4 E010BF 0 +OP4 E010C0 0 +OP4 E010C1 0 +OP4 E010C2 0 +OP4 E010C3 0 +OP4 E010C4 0 +OP4 E010C5 0 +OP4 E010C6 0 +OP4 E010C7 0 +OP4 E010C8 0 +OP4 E010C9 0 +OP4 E010CA 0 +OP4 E010CB 0 +OP4 E010CC 0 +OP4 E010CD 0 +OP4 E010CE 0 +OP4 E010CF 0 +OP4 E010D0 0 +OP4 E010D1 0 +OP4 E010D2 0 +OP4 E010D3 0 +OP4 E010D4 0 +OP4 E010D5 0 +OP4 E010D6 0 +OP4 E010D7 0 +OP4 E010D8 0 +OP4 E010D9 0 +OP4 E010DA 0 +OP4 E010DB 0 +OP4 E010DC 0 +OP4 E010DD 0 +OP4 E010DE 0 +OP4 E010DF 0 +OP4 E010E0 0 +OP4 E010E1 0 +OP4 E010E2 0 +OP4 E010E3 0 +OP4 E010E4 0 +OP4 E010E5 0 +OP4 E010E6 0 +OP4 E010E7 0 +OP4 E010E8 0 +OP4 E010E9 0 +OP4 E010EA 0 +OP4 E010EB 0 +OP4 E010EC 0 +OP4 E010ED 0 +OP4 E010EE 0 +OP4 E010EF 0 +OP4 E010F0 0 +OP4 E010F1 0 +OP4 E010F2 0 +OP4 E010F3 0 +OP4 E010F4 0 +OP4 E010F5 0 +OP4 E010F6 0 +OP4 E010F7 0 +OP4 E010F8 0 +OP4 E010F9 0 +OP4 E010FA 0 +OP4 E010FB 0 +OP4 E010FC 0 +OP4 E010FD 0 +OP4 E010FE 0 +OP4 E010FF 0 +OP4 E01100 0 +OP4 E01101 0 +OP4 E01102 0 +OP4 E01103 0 +OP4 E01104 0 +OP4 E01105 0 +OP4 E01106 0 +OP4 E01107 0 +OP4 E01108 0 +OP4 E01109 0 +OP4 E0110A 0 +OP4 E0110B 0 +OP4 E0110C 0 +OP4 E0110D 0 +OP4 E0110E 0 +OP4 E0110F 0 +OP4 E01110 0 +OP4 E01111 0 +OP4 E01112 0 +OP4 E01113 0 +OP4 E01114 0 +OP4 E01115 0 +OP4 E01116 0 +OP4 E01117 0 +OP4 E01118 0 +OP4 E01119 0 +OP4 E0111A 0 +OP4 E0111B 0 +OP4 E0111C 0 +OP4 E0111D 0 +OP4 E0111E 0 +OP4 E0111F 0 +OP4 E01120 0 +OP4 E01121 0 +OP4 E01122 0 +OP4 E01123 0 +OP4 E01124 0 +OP4 E01125 0 +OP4 E01126 0 +OP4 E01127 0 +OP4 E01128 0 +OP4 E01129 0 +OP4 E0112A 0 +OP4 E0112B 0 +OP4 E0112C 0 +OP4 E0112D 0 +OP4 E0112E 0 +OP4 E0112F 0 +OP4 E01130 0 +OP4 E01131 0 +OP4 E01132 0 +OP4 E01133 0 +OP4 E01134 0 +OP4 E01135 0 +OP4 E01136 0 +OP4 E01137 0 +OP4 E01138 0 +OP4 E01139 0 +OP4 E0113A 0 +OP4 E0113B 0 +OP4 E0113C 0 +OP4 E0113D 0 +OP4 E0113E 0 +OP4 E0113F 0 +OP4 E01140 0 +OP4 E01141 0 +OP4 E01142 0 +OP4 E01143 0 +OP4 E01144 0 +OP4 E01145 0 +OP4 E01146 0 +OP4 E01147 0 +OP4 E01148 0 +OP4 E01149 0 +OP4 E0114A 0 +OP4 E0114B 0 +OP4 E0114C 0 +OP4 E0114D 0 +OP4 E0114E 0 +OP4 E0114F 0 +OP4 E01150 0 +OP4 E01151 0 +OP4 E01152 0 +OP4 E01153 0 +OP4 E01154 0 +OP4 E01155 0 +OP4 E01156 0 +OP4 E01157 0 +OP4 E01158 0 +OP4 E01159 0 +OP4 E0115A 0 +OP4 E0115B 0 +OP4 E0115C 0 +OP4 E0115D 0 +OP4 E0115E 0 +OP4 E0115F 0 +OP4 E01160 0 +OP4 E01161 0 +OP4 E01162 0 +OP4 E01163 0 +OP4 E01164 0 +OP4 E01165 0 +OP4 E01166 0 +OP4 E01167 0 +OP4 E01168 0 +OP4 E01169 0 +OP4 E0116A 0 +OP4 E0116B 0 +OP4 E0116C 0 +OP4 E0116D 0 +OP4 E0116E 0 +OP4 E0116F 0 +OP4 E01170 0 +OP4 E01171 0 +OP4 E01172 0 +OP4 E01173 0 +OP4 E01174 0 +OP4 E01175 0 +OP4 E01176 0 +OP4 E01177 0 +OP4 E01178 0 +OP4 E01179 0 +OP4 E0117A 0 +OP4 E0117B 0 +OP4 E0117C 0 +OP4 E0117D 0 +OP4 E0117E 0 +OP4 E0117F 0 +OP4 E01180 0 +OP4 E01181 0 +OP4 E01182 0 +OP4 E01183 0 +OP4 E01184 0 +OP4 E01185 0 +OP4 E01186 0 +OP4 E01187 0 +OP4 E01188 0 +OP4 E01189 0 +OP4 E0118A 0 +OP4 E0118B 0 +OP4 E0118C 0 +OP4 E0118D 0 +OP4 E0118E 0 +OP4 E0118F 0 +OP4 E01190 0 +OP4 E01191 0 +OP4 E01192 0 +OP4 E01193 0 +OP4 E01194 0 +OP4 E01195 0 +OP4 E01196 0 +OP4 E01197 0 +OP4 E01198 0 +OP4 E01199 0 +OP4 E0119A 0 +OP4 E0119B 0 +OP4 E0119C 0 +OP4 E0119D 0 +OP4 E0119E 0 +OP4 E0119F 0 +OP4 E011A0 0 +OP4 E011A1 0 +OP4 E011A2 0 +OP4 E011A3 0 +OP4 E011A4 0 +OP4 E011A5 0 +OP4 E011A6 0 +OP4 E011A7 0 +OP4 E011A8 0 +OP4 E011A9 0 +OP4 E011AA 0 +OP4 E011AB 0 +OP4 E011AC 0 +OP4 E011AD 0 +OP4 E011AE 0 +OP4 E011AF 0 +OP4 E011B0 0 +OP4 E011B1 0 +OP4 E011B2 0 +OP4 E011B3 0 +OP4 E011B4 0 +OP4 E011B5 0 +OP4 E011B6 0 +OP4 E011B7 0 +OP4 E011B8 0 +OP4 E011B9 0 +OP4 E011BA 0 +OP4 E011BB 0 +OP4 E011BC 0 +OP4 E011BD 0 +OP4 E011BE 0 +OP4 E011BF 0 +OP4 E011C0 0 +OP4 E011C1 0 +OP4 E011C2 0 +OP4 E011C3 0 +OP4 E011C4 0 +OP4 E011C5 0 +OP4 E011C6 0 +OP4 E011C7 0 +OP4 E011C8 0 +OP4 E011C9 0 +OP4 E011CA 0 +OP4 E011CB 0 +OP4 E011CC 0 +OP4 E011CD 0 +OP4 E011CE 0 +OP4 E011CF 0 +OP4 E011D0 0 +OP4 E011D1 0 +OP4 E011D2 0 +OP4 E011D3 0 +OP4 E011D4 0 +OP4 E011D5 0 +OP4 E011D6 0 +OP4 E011D7 0 +OP4 E011D8 0 +OP4 E011D9 0 +OP4 E011DA 0 +OP4 E011DB 0 +OP4 E011DC 0 +OP4 E011DD 0 +OP4 E011DE 0 +OP4 E011DF 0 +OP4 E011E0 0 +OP4 E011E1 0 +OP4 E011E2 0 +OP4 E011E3 0 +OP4 E011E4 0 +OP4 E011E5 0 +OP4 E011E6 0 +OP4 E011E7 0 +OP4 E011E8 0 +OP4 E011E9 0 +OP4 E011EA 0 +OP4 E011EB 0 +OP4 E011EC 0 +OP4 E011ED 0 +OP4 E011EE 0 +OP4 E011EF 0 +OP4 E011F0 0 +OP4 E011F1 0 +OP4 E011F2 0 +OP4 E011F3 0 +OP4 E011F4 0 +OP4 E011F5 0 +OP4 E011F6 0 +OP4 E011F7 0 +OP4 E011F8 0 +OP4 E011F9 0 +OP4 E011FA 0 +OP4 E011FB 0 +OP4 E011FC 0 +OP4 E011FD 0 +OP4 E011FE 0 +OP4 E011FF 0 +OP4 E01200 0 +OP4 E01201 0 +OP4 E01202 0 +OP4 E01203 0 +OP4 E01204 0 +OP4 E01205 0 +OP4 E01206 0 +OP4 E01207 0 +OP4 E01208 0 +OP4 E01209 0 +OP4 E0120A 0 +OP4 E0120B 0 +OP4 E0120C 0 +OP4 E0120D 0 +OP4 E0120E 0 +OP4 E0120F 0 +OP4 E01210 0 +OP4 E01211 0 +OP4 E01212 0 +OP4 E01213 0 +OP4 E01214 0 +OP4 E01215 0 +OP4 E01216 0 +OP4 E01217 0 +OP4 E01218 0 +OP4 E01219 0 +OP4 E0121A 0 +OP4 E0121B 0 +OP4 E0121C 0 +OP4 E0121D 0 +OP4 E0121E 0 +OP4 E0121F 0 +OP4 E01220 0 +OP4 E01221 0 +OP4 E01222 0 +OP4 E01223 0 +OP4 E01224 0 +OP4 E01225 0 +OP4 E01226 0 +OP4 E01227 0 +OP4 E01228 0 +OP4 E01229 0 +OP4 E0122A 0 +OP4 E0122B 0 +OP4 E0122C 0 +OP4 E0122D 0 +OP4 E0122E 0 +OP4 E0122F 0 +OP4 E01230 0 +OP4 E01231 0 +OP4 E01232 0 +OP4 E01233 0 +OP4 E01234 0 +OP4 E01235 0 +OP4 E01236 0 +OP4 E01237 0 +OP4 E01238 0 +OP4 E01239 0 +OP4 E0123A 0 +OP4 E0123B 0 +OP4 E0123C 0 +OP4 E0123D 0 +OP4 E0123E 0 +OP4 E0123F 0 +OP4 E01240 0 +OP4 E01241 0 +OP4 E01242 0 +OP4 E01243 0 +OP4 E01244 0 +OP4 E01245 0 +OP4 E01246 0 +OP4 E01247 0 +OP4 E01248 0 +OP4 E01249 0 +OP4 E0124A 0 +OP4 E0124B 0 +OP4 E0124C 0 +OP4 E0124D 0 +OP4 E0124E 0 +OP4 E0124F 0 +OP4 E01250 0 +OP4 E01251 0 +OP4 E01252 0 +OP4 E01253 0 +OP4 E01254 0 +OP4 E01255 0 +OP4 E01256 0 +OP4 E01257 0 +OP4 E01258 0 +OP4 E01259 0 +OP4 E0125A 0 +OP4 E0125B 0 +OP4 E0125C 0 +OP4 E0125D 0 +OP4 E0125E 0 +OP4 E0125F 0 +OP4 E01260 0 +OP4 E01261 0 +OP4 E01262 0 +OP4 E01263 0 +OP4 E01264 0 +OP4 E01265 0 +OP4 E01266 0 +OP4 E01267 0 +OP4 E01268 0 +OP4 E01269 0 +OP4 E0126A 0 +OP4 E0126B 0 +OP4 E0126C 0 +OP4 E0126D 0 +OP4 E0126E 0 +OP4 E0126F 0 +OP4 E01270 0 +OP4 E01271 0 +OP4 E01272 0 +OP4 E01273 0 +OP4 E01274 0 +OP4 E01275 0 +OP4 E01276 0 +OP4 E01277 0 +OP4 E01278 0 +OP4 E01279 0 +OP4 E0127A 0 +OP4 E0127B 0 +OP4 E0127C 0 +OP4 E0127D 0 +OP4 E0127E 0 +OP4 E0127F 0 +OP4 E01280 0 +OP4 E01281 0 +OP4 E01282 0 +OP4 E01283 0 +OP4 E01284 0 +OP4 E01285 0 +OP4 E01286 0 +OP4 E01287 0 +OP4 E01288 0 +OP4 E01289 0 +OP4 E0128A 0 +OP4 E0128B 0 +OP4 E0128C 0 +OP4 E0128D 0 +OP4 E0128E 0 +OP4 E0128F 0 +OP4 E01290 0 +OP4 E01291 0 +OP4 E01292 0 +OP4 E01293 0 +OP4 E01294 0 +OP4 E01295 0 +OP4 E01296 0 +OP4 E01297 0 +OP4 E01298 0 +OP4 E01299 0 +OP4 E0129A 0 +OP4 E0129B 0 +OP4 E0129C 0 +OP4 E0129D 0 +OP4 E0129E 0 +OP4 E0129F 0 +OP4 E012A0 0 +OP4 E012A1 0 +OP4 E012A2 0 +OP4 E012A3 0 +OP4 E012A4 0 +OP4 E012A5 0 +OP4 E012A6 0 +OP4 E012A7 0 +OP4 E012A8 0 +OP4 E012A9 0 +OP4 E012AA 0 +OP4 E012AB 0 +OP4 E012AC 0 +OP4 E012AD 0 +OP4 E012AE 0 +OP4 E012AF 0 +OP4 E012B0 0 +OP4 E012B1 0 +OP4 E012B2 0 +OP4 E012B3 0 +OP4 E012B4 0 +OP4 E012B5 0 +OP4 E012B6 0 +OP4 E012B7 0 +OP4 E012B8 0 +OP4 E012B9 0 +OP4 E012BA 0 +OP4 E012BB 0 +OP4 E012BC 0 +OP4 E012BD 0 +OP4 E012BE 0 +OP4 E012BF 0 +OP4 E012C0 0 +OP4 E012C1 0 +OP4 E012C2 0 +OP4 E012C3 0 +OP4 E012C4 0 +OP4 E012C5 0 +OP4 E012C6 0 +OP4 E012C7 0 +OP4 E012C8 0 +OP4 E012C9 0 +OP4 E012CA 0 +OP4 E012CB 0 +OP4 E012CC 0 +OP4 E012CD 0 +OP4 E012CE 0 +OP4 E012CF 0 +OP4 E012D0 0 +OP4 E012D1 0 +OP4 E012D2 0 +OP4 E012D3 0 +OP4 E012D4 0 +OP4 E012D5 0 +OP4 E012D6 0 +OP4 E012D7 0 +OP4 E012D8 0 +OP4 E012D9 0 +OP4 E012DA 0 +OP4 E012DB 0 +OP4 E012DC 0 +OP4 E012DD 0 +OP4 E012DE 0 +OP4 E012DF 0 +OP4 E012E0 0 +OP4 E012E1 0 +OP4 E012E2 0 +OP4 E012E3 0 +OP4 E012E4 0 +OP4 E012E5 0 +OP4 E012E6 0 +OP4 E012E7 0 +OP4 E012E8 0 +OP4 E012E9 0 +OP4 E012EA 0 +OP4 E012EB 0 +OP4 E012EC 0 +OP4 E012ED 0 +OP4 E012EE 0 +OP4 E012EF 0 +OP4 E012F0 0 +OP4 E012F1 0 +OP4 E012F2 0 +OP4 E012F3 0 +OP4 E012F4 0 +OP4 E012F5 0 +OP4 E012F6 0 +OP4 E012F7 0 +OP4 E012F8 0 +OP4 E012F9 0 +OP4 E012FA 0 +OP4 E012FB 0 +OP4 E012FC 0 +OP4 E012FD 0 +OP4 E012FE 0 +OP4 E012FF 0 +OP4 E01300 0 +OP4 E01301 0 +OP4 E01302 0 +OP4 E01303 0 +OP4 E01304 0 +OP4 E01305 0 +OP4 E01306 0 +OP4 E01307 0 +OP4 E01308 0 +OP4 E01309 0 +OP4 E0130A 0 +OP4 E0130B 0 +OP4 E0130C 0 +OP4 E0130D 0 +OP4 E0130E 0 +OP4 E0130F 0 +OP4 E01310 0 +OP4 E01311 0 +OP4 E01312 0 +OP4 E01313 0 +OP4 E01314 0 +OP4 E01315 0 +OP4 E01316 0 +OP4 E01317 0 +OP4 E01318 0 +OP4 E01319 0 +OP4 E0131A 0 +OP4 E0131B 0 +OP4 E0131C 0 +OP4 E0131D 0 +OP4 E0131E 0 +OP4 E0131F 0 +OP4 E01320 0 +OP4 E01321 0 +OP4 E01322 0 +OP4 E01323 0 +OP4 E01324 0 +OP4 E01325 0 +OP4 E01326 0 +OP4 E01327 0 +OP4 E01328 0 +OP4 E01329 0 +OP4 E0132A 0 +OP4 E0132B 0 +OP4 E0132C 0 +OP4 E0132D 0 +OP4 E0132E 0 +OP4 E0132F 0 +OP4 E01330 0 +OP4 E01331 0 +OP4 E01332 0 +OP4 E01333 0 +OP4 E01334 0 +OP4 E01335 0 +OP4 E01336 0 +OP4 E01337 0 +OP4 E01338 0 +OP4 E01339 0 +OP4 E0133A 0 +OP4 E0133B 0 +OP4 E0133C 0 +OP4 E0133D 0 +OP4 E0133E 0 +OP4 E0133F 0 +OP4 E01340 0 +OP4 E01341 0 +OP4 E01342 0 +OP4 E01343 0 +OP4 E01344 0 +OP4 E01345 0 +OP4 E01346 0 +OP4 E01347 0 +OP4 E01348 0 +OP4 E01349 0 +OP4 E0134A 0 +OP4 E0134B 0 +OP4 E0134C 0 +OP4 E0134D 0 +OP4 E0134E 0 +OP4 E0134F 0 +OP4 E01350 0 +OP4 E01351 0 +OP4 E01352 0 +OP4 E01353 0 +OP4 E01354 0 +OP4 E01355 0 +OP4 E01356 0 +OP4 E01357 0 +OP4 E01358 0 +OP4 E01359 0 +OP4 E0135A 0 +OP4 E0135B 0 +OP4 E0135C 0 +OP4 E0135D 0 +OP4 E0135E 0 +OP4 E0135F 0 +OP4 E01360 0 +OP4 E01361 0 +OP4 E01362 0 +OP4 E01363 0 +OP4 E01364 0 +OP4 E01365 0 +OP4 E01366 0 +OP4 E01367 0 +OP4 E01368 0 +OP4 E01369 0 +OP4 E0136A 0 +OP4 E0136B 0 +OP4 E0136C 0 +OP4 E0136D 0 +OP4 E0136E 0 +OP4 E0136F 0 +OP4 E01370 0 +OP4 E01371 0 +OP4 E01372 0 +OP4 E01373 0 +OP4 E01374 0 +OP4 E01375 0 +OP4 E01376 0 +OP4 E01377 0 +OP4 E01378 0 +OP4 E01379 0 +OP4 E0137A 0 +OP4 E0137B 0 +OP4 E0137C 0 +OP4 E0137D 0 +OP4 E0137E 0 +OP4 E0137F 0 +OP4 E01380 0 +OP4 E01381 0 +OP4 E01382 0 +OP4 E01383 0 +OP4 E01384 0 +OP4 E01385 0 +OP4 E01386 0 +OP4 E01387 0 +OP4 E01388 0 +OP4 E01389 0 +OP4 E0138A 0 +OP4 E0138B 0 +OP4 E0138C 0 +OP4 E0138D 0 +OP4 E0138E 0 +OP4 E0138F 0 +OP4 E01390 0 +OP4 E01391 0 +OP4 E01392 0 +OP4 E01393 0 +OP4 E01394 0 +OP4 E01395 0 +OP4 E01396 0 +OP4 E01397 0 +OP4 E01398 0 +OP4 E01399 0 +OP4 E0139A 0 +OP4 E0139B 0 +OP4 E0139C 0 +OP4 E0139D 0 +OP4 E0139E 0 +OP4 E0139F 0 +OP4 E013A0 0 +OP4 E013A1 0 +OP4 E013A2 0 +OP4 E013A3 0 +OP4 E013A4 0 +OP4 E013A5 0 +OP4 E013A6 0 +OP4 E013A7 0 +OP4 E013A8 0 +OP4 E013A9 0 +OP4 E013AA 0 +OP4 E013AB 0 +OP4 E013AC 0 +OP4 E013AD 0 +OP4 E013AE 0 +OP4 E013AF 0 +OP4 E013B0 0 +OP4 E013B1 0 +OP4 E013B2 0 +OP4 E013B3 0 +OP4 E013B4 0 +OP4 E013B5 0 +OP4 E013B6 0 +OP4 E013B7 0 +OP4 E013B8 0 +OP4 E013B9 0 +OP4 E013BA 0 +OP4 E013BB 0 +OP4 E013BC 0 +OP4 E013BD 0 +OP4 E013BE 0 +OP4 E013BF 0 +OP4 E013C0 0 +OP4 E013C1 0 +OP4 E013C2 0 +OP4 E013C3 0 +OP4 E013C4 0 +OP4 E013C5 0 +OP4 E013C6 0 +OP4 E013C7 0 +OP4 E013C8 0 +OP4 E013C9 0 +OP4 E013CA 0 +OP4 E013CB 0 +OP4 E013CC 0 +OP4 E013CD 0 +OP4 E013CE 0 +OP4 E013CF 0 +OP4 E013D0 0 +OP4 E013D1 0 +OP4 E013D2 0 +OP4 E013D3 0 +OP4 E013D4 0 +OP4 E013D5 0 +OP4 E013D6 0 +OP4 E013D7 0 +OP4 E013D8 0 +OP4 E013D9 0 +OP4 E013DA 0 +OP4 E013DB 0 +OP4 E013DC 0 +OP4 E013DD 0 +OP4 E013DE 0 +OP4 E013DF 0 +OP4 E013E0 0 +OP4 E013E1 0 +OP4 E013E2 0 +OP4 E013E3 0 +OP4 E013E4 0 +OP4 E013E5 0 +OP4 E013E6 0 +OP4 E013E7 0 +OP4 E013E8 0 +OP4 E013E9 0 +OP4 E013EA 0 +OP4 E013EB 0 +OP4 E013EC 0 +OP4 E013ED 0 +OP4 E013EE 0 +OP4 E013EF 0 +OP4 E013F0 0 +OP4 E013F1 0 +OP4 E013F2 0 +OP4 E013F3 0 +OP4 E013F4 0 +OP4 E013F5 0 +OP4 E013F6 0 +OP4 E013F7 0 +OP4 E013F8 0 +OP4 E013F9 0 +OP4 E013FA 0 +OP4 E013FB 0 +OP4 E013FC 0 +OP4 E013FD 0 +OP4 E013FE 0 +OP4 E013FF 0 +OP4 E01400 0 +OP4 E01401 0 +OP4 E01402 0 +OP4 E01403 0 +OP4 E01404 0 +OP4 E01405 0 +OP4 E01406 0 +OP4 E01407 0 +OP4 E01408 0 +OP4 E01409 0 +OP4 E0140A 0 +OP4 E0140B 0 +OP4 E0140C 0 +OP4 E0140D 0 +OP4 E0140E 0 +OP4 E0140F 0 +OP4 E01410 0 +OP4 E01411 0 +OP4 E01412 0 +OP4 E01413 0 +OP4 E01414 0 +OP4 E01415 0 +OP4 E01416 0 +OP4 E01417 0 +OP4 E01418 0 +OP4 E01419 0 +OP4 E0141A 0 +OP4 E0141B 0 +OP4 E0141C 0 +OP4 E0141D 0 +OP4 E0141E 0 +OP4 E0141F 0 +OP4 E01420 0 +OP4 E01421 0 +OP4 E01422 0 +OP4 E01423 0 +OP4 E01424 0 +OP4 E01425 0 +OP4 E01426 0 +OP4 E01427 0 +OP4 E01428 0 +OP4 E01429 0 +OP4 E0142A 0 +OP4 E0142B 0 +OP4 E0142C 0 +OP4 E0142D 0 +OP4 E0142E 0 +OP4 E0142F 0 +OP4 E01430 0 +OP4 E01431 0 +OP4 E01432 0 +OP4 E01433 0 +OP4 E01434 0 +OP4 E01435 0 +OP4 E01436 0 +OP4 E01437 0 +OP4 E01438 0 +OP4 E01439 0 +OP4 E0143A 0 +OP4 E0143B 0 +OP4 E0143C 0 +OP4 E0143D 0 +OP4 E0143E 0 +OP4 E0143F 0 +OP4 E01440 0 +OP4 E01441 0 +OP4 E01442 0 +OP4 E01443 0 +OP4 E01444 0 +OP4 E01445 0 +OP4 E01446 0 +OP4 E01447 0 +OP4 E01448 0 +OP4 E01449 0 +OP4 E0144A 0 +OP4 E0144B 0 +OP4 E0144C 0 +OP4 E0144D 0 +OP4 E0144E 0 +OP4 E0144F 0 +OP4 E01450 0 +OP4 E01451 0 +OP4 E01452 0 +OP4 E01453 0 +OP4 E01454 0 +OP4 E01455 0 +OP4 E01456 0 +OP4 E01457 0 +OP4 E01458 0 +OP4 E01459 0 +OP4 E0145A 0 +OP4 E0145B 0 +OP4 E0145C 0 +OP4 E0145D 0 +OP4 E0145E 0 +OP4 E0145F 0 +OP4 E01460 0 +OP4 E01461 0 +OP4 E01462 0 +OP4 E01463 0 +OP4 E01464 0 +OP4 E01465 0 +OP4 E01466 0 +OP4 E01467 0 +OP4 E01468 0 +OP4 E01469 0 +OP4 E0146A 0 +OP4 E0146B 0 +OP4 E0146C 0 +OP4 E0146D 0 +OP4 E0146E 0 +OP4 E0146F 0 +OP4 E01470 0 +OP4 E01471 0 +OP4 E01472 0 +OP4 E01473 0 +OP4 E01474 0 +OP4 E01475 0 +OP4 E01476 0 +OP4 E01477 0 +OP4 E01478 0 +OP4 E01479 0 +OP4 E0147A 0 +OP4 E0147B 0 +OP4 E0147C 0 +OP4 E0147D 0 +OP4 E0147E 0 +OP4 E0147F 0 +OP4 E01480 0 +OP4 E01481 0 +OP4 E01482 0 +OP4 E01483 0 +OP4 E01484 0 +OP4 E01485 0 +OP4 E01486 0 +OP4 E01487 0 +OP4 E01488 0 +OP4 E01489 0 +OP4 E0148A 0 +OP4 E0148B 0 +OP4 E0148C 0 +OP4 E0148D 0 +OP4 E0148E 0 +OP4 E0148F 0 +OP4 E01490 0 +OP4 E01491 0 +OP4 E01492 0 +OP4 E01493 0 +OP4 E01494 0 +OP4 E01495 0 +OP4 E01496 0 +OP4 E01497 0 +OP4 E01498 0 +OP4 E01499 0 +OP4 E0149A 0 +OP4 E0149B 0 +OP4 E0149C 0 +OP4 E0149D 0 +OP4 E0149E 0 +OP4 E0149F 0 +OP4 E014A0 0 +OP4 E014A1 0 +OP4 E014A2 0 +OP4 E014A3 0 +OP4 E014A4 0 +OP4 E014A5 0 +OP4 E014A6 0 +OP4 E014A7 0 +OP4 E014A8 0 +OP4 E014A9 0 +OP4 E014AA 0 +OP4 E014AB 0 +OP4 E014AC 0 +OP4 E014AD 0 +OP4 E014AE 0 +OP4 E014AF 0 +OP4 E014B0 0 +OP4 E014B1 0 +OP4 E014B2 0 +OP4 E014B3 0 +OP4 E014B4 0 +OP4 E014B5 0 +OP4 E014B6 0 +OP4 E014B7 0 +OP4 E014B8 0 +OP4 E014B9 0 +OP4 E014BA 0 +OP4 E014BB 0 +OP4 E014BC 0 +OP4 E014BD 0 +OP4 E014BE 0 +OP4 E014BF 0 +OP4 E014C0 0 +OP4 E014C1 0 +OP4 E014C2 0 +OP4 E014C3 0 +OP4 E014C4 0 +OP4 E014C5 0 +OP4 E014C6 0 +OP4 E014C7 0 +OP4 E014C8 0 +OP4 E014C9 0 +OP4 E014CA 0 +OP4 E014CB 0 +OP4 E014CC 0 +OP4 E014CD 0 +OP4 E014CE 0 +OP4 E014CF 0 +OP4 E014D0 0 +OP4 E014D1 0 +OP4 E014D2 0 +OP4 E014D3 0 +OP4 E014D4 0 +OP4 E014D5 0 +OP4 E014D6 0 +OP4 E014D7 0 +OP4 E014D8 0 +OP4 E014D9 0 +OP4 E014DA 0 +OP4 E014DB 0 +OP4 E014DC 0 +OP4 E014DD 0 +OP4 E014DE 0 +OP4 E014DF 0 +OP4 E014E0 0 +OP4 E014E1 0 +OP4 E014E2 0 +OP4 E014E3 0 +OP4 E014E4 0 +OP4 E014E5 0 +OP4 E014E6 0 +OP4 E014E7 0 +OP4 E014E8 0 +OP4 E014E9 0 +OP4 E014EA 0 +OP4 E014EB 0 +OP4 E014EC 0 +OP4 E014ED 0 +OP4 E014EE 0 +OP4 E014EF 0 +OP4 E014F0 0 +OP4 E014F1 0 +OP4 E014F2 0 +OP4 E014F3 0 +OP4 E014F4 0 +OP4 E014F5 0 +OP4 E014F6 0 +OP4 E014F7 0 +OP4 E014F8 0 +OP4 E014F9 0 +OP4 E014FA 0 +OP4 E014FB 0 +OP4 E014FC 0 +OP4 E014FD 0 +OP4 E014FE 0 +OP4 E014FF 0 +OP4 E01500 0 +OP4 E01501 0 +OP4 E01502 0 +OP4 E01503 0 +OP4 E01504 0 +OP4 E01505 0 +OP4 E01506 0 +OP4 E01507 0 +OP4 E01508 0 +OP4 E01509 0 +OP4 E0150A 0 +OP4 E0150B 0 +OP4 E0150C 0 +OP4 E0150D 0 +OP4 E0150E 0 +OP4 E0150F 0 +OP4 E01510 0 +OP4 E01511 0 +OP4 E01512 0 +OP4 E01513 0 +OP4 E01514 0 +OP4 E01515 0 +OP4 E01516 0 +OP4 E01517 0 +OP4 E01518 0 +OP4 E01519 0 +OP4 E0151A 0 +OP4 E0151B 0 +OP4 E0151C 0 +OP4 E0151D 0 +OP4 E0151E 0 +OP4 E0151F 0 +OP4 E01520 0 +OP4 E01521 0 +OP4 E01522 0 +OP4 E01523 0 +OP4 E01524 0 +OP4 E01525 0 +OP4 E01526 0 +OP4 E01527 0 +OP4 E01528 0 +OP4 E01529 0 +OP4 E0152A 0 +OP4 E0152B 0 +OP4 E0152C 0 +OP4 E0152D 0 +OP4 E0152E 0 +OP4 E0152F 0 +OP4 E01530 0 +OP4 E01531 0 +OP4 E01532 0 +OP4 E01533 0 +OP4 E01534 0 +OP4 E01535 0 +OP4 E01536 0 +OP4 E01537 0 +OP4 E01538 0 +OP4 E01539 0 +OP4 E0153A 0 +OP4 E0153B 0 +OP4 E0153C 0 +OP4 E0153D 0 +OP4 E0153E 0 +OP4 E0153F 0 +OP4 E01540 0 +OP4 E01541 0 +OP4 E01542 0 +OP4 E01543 0 +OP4 E01544 0 +OP4 E01545 0 +OP4 E01546 0 +OP4 E01547 0 +OP4 E01548 0 +OP4 E01549 0 +OP4 E0154A 0 +OP4 E0154B 0 +OP4 E0154C 0 +OP4 E0154D 0 +OP4 E0154E 0 +OP4 E0154F 0 +OP4 E01550 0 +OP4 E01551 0 +OP4 E01552 0 +OP4 E01553 0 +OP4 E01554 0 +OP4 E01555 0 +OP4 E01556 0 +OP4 E01557 0 +OP4 E01558 0 +OP4 E01559 0 +OP4 E0155A 0 +OP4 E0155B 0 +OP4 E0155C 0 +OP4 E0155D 0 +OP4 E0155E 0 +OP4 E0155F 0 +OP4 E01560 0 +OP4 E01561 0 +OP4 E01562 0 +OP4 E01563 0 +OP4 E01564 0 +OP4 E01565 0 +OP4 E01566 0 +OP4 E01567 0 +OP4 E01568 0 +OP4 E01569 0 +OP4 E0156A 0 +OP4 E0156B 0 +OP4 E0156C 0 +OP4 E0156D 0 +OP4 E0156E 0 +OP4 E0156F 0 +OP4 E01570 0 +OP4 E01571 0 +OP4 E01572 0 +OP4 E01573 0 +OP4 E01574 0 +OP4 E01575 0 +OP4 E01576 0 +OP4 E01577 0 +OP4 E01578 0 +OP4 E01579 0 +OP4 E0157A 0 +OP4 E0157B 0 +OP4 E0157C 0 +OP4 E0157D 0 +OP4 E0157E 0 +OP4 E0157F 0 +OP4 E01580 0 +OP4 E01581 0 +OP4 E01582 0 +OP4 E01583 0 +OP4 E01584 0 +OP4 E01585 0 +OP4 E01586 0 +OP4 E01587 0 +OP4 E01588 0 +OP4 E01589 0 +OP4 E0158A 0 +OP4 E0158B 0 +OP4 E0158C 0 +OP4 E0158D 0 +OP4 E0158E 0 +OP4 E0158F 0 +OP4 E01590 0 +OP4 E01591 0 +OP4 E01592 0 +OP4 E01593 0 +OP4 E01594 0 +OP4 E01595 0 +OP4 E01596 0 +OP4 E01597 0 +OP4 E01598 0 +OP4 E01599 0 +OP4 E0159A 0 +OP4 E0159B 0 +OP4 E0159C 0 +OP4 E0159D 0 +OP4 E0159E 0 +OP4 E0159F 0 +OP4 E015A0 0 +OP4 E015A1 0 +OP4 E015A2 0 +OP4 E015A3 0 +OP4 E015A4 0 +OP4 E015A5 0 +OP4 E015A6 0 +OP4 E015A7 0 +OP4 E015A8 0 +OP4 E015A9 0 +OP4 E015AA 0 +OP4 E015AB 0 +OP4 E015AC 0 +OP4 E015AD 0 +OP4 E015AE 0 +OP4 E015AF 0 +OP4 E015B0 0 +OP4 E015B1 0 +OP4 E015B2 0 +OP4 E015B3 0 +OP4 E015B4 0 +OP4 E015B5 0 +OP4 E015B6 0 +OP4 E015B7 0 +OP4 E015B8 0 +OP4 E015B9 0 +OP4 E015BA 0 +OP4 E015BB 0 +OP4 E015BC 0 +OP4 E015BD 0 +OP4 E015BE 0 +OP4 E015BF 0 +OP4 E015C0 0 +OP4 E015C1 0 +OP4 E015C2 0 +OP4 E015C3 0 +OP4 E015C4 0 +OP4 E015C5 0 +OP4 E015C6 0 +OP4 E015C7 0 +OP4 E015C8 0 +OP4 E015C9 0 +OP4 E015CA 0 +OP4 E015CB 0 +OP4 E015CC 0 +OP4 E015CD 0 +OP4 E015CE 0 +OP4 E015CF 0 +OP4 E015D0 0 +OP4 E015D1 0 +OP4 E015D2 0 +OP4 E015D3 0 +OP4 E015D4 0 +OP4 E015D5 0 +OP4 E015D6 0 +OP4 E015D7 0 +OP4 E015D8 0 +OP4 E015D9 0 +OP4 E015DA 0 +OP4 E015DB 0 +OP4 E015DC 0 +OP4 E015DD 0 +OP4 E015DE 0 +OP4 E015DF 0 +OP4 E015E0 0 +OP4 E015E1 0 +OP4 E015E2 0 +OP4 E015E3 0 +OP4 E015E4 0 +OP4 E015E5 0 +OP4 E015E6 0 +OP4 E015E7 0 +OP4 E015E8 0 +OP4 E015E9 0 +OP4 E015EA 0 +OP4 E015EB 0 +OP4 E015EC 0 +OP4 E015ED 0 +OP4 E015EE 0 +OP4 E015EF 0 +OP4 E015F0 0 +OP4 E015F1 0 +OP4 E015F2 0 +OP4 E015F3 0 +OP4 E015F4 0 +OP4 E015F5 0 +OP4 E015F6 0 +OP4 E015F7 0 +OP4 E015F8 0 +OP4 E015F9 0 +OP4 E015FA 0 +OP4 E015FB 0 +OP4 E015FC 0 +OP4 E015FD 0 +OP4 E015FE 0 +OP4 E015FF 0 +OP4 E01600 0 +OP4 E01601 0 +OP4 E01602 0 +OP4 E01603 0 +OP4 E01604 0 +OP4 E01605 0 +OP4 E01606 0 +OP4 E01607 0 +OP4 E01608 0 +OP4 E01609 0 +OP4 E0160A 0 +OP4 E0160B 0 +OP4 E0160C 0 +OP4 E0160D 0 +OP4 E0160E 0 +OP4 E0160F 0 +OP4 E01610 0 +OP4 E01611 0 +OP4 E01612 0 +OP4 E01613 0 +OP4 E01614 0 +OP4 E01615 0 +OP4 E01616 0 +OP4 E01617 0 +OP4 E01618 0 +OP4 E01619 0 +OP4 E0161A 0 +OP4 E0161B 0 +OP4 E0161C 0 +OP4 E0161D 0 +OP4 E0161E 0 +OP4 E0161F 0 +OP4 E01620 0 +OP4 E01621 0 +OP4 E01622 0 +OP4 E01623 0 +OP4 E01624 0 +OP4 E01625 0 +OP4 E01626 0 +OP4 E01627 0 +OP4 E01628 0 +OP4 E01629 0 +OP4 E0162A 0 +OP4 E0162B 0 +OP4 E0162C 0 +OP4 E0162D 0 +OP4 E0162E 0 +OP4 E0162F 0 +OP4 E01630 0 +OP4 E01631 0 +OP4 E01632 0 +OP4 E01633 0 +OP4 E01634 0 +OP4 E01635 0 +OP4 E01636 0 +OP4 E01637 0 +OP4 E01638 0 +OP4 E01639 0 +OP4 E0163A 0 +OP4 E0163B 0 +OP4 E0163C 0 +OP4 E0163D 0 +OP4 E0163E 0 +OP4 E0163F 0 +OP4 E01640 0 +OP4 E01641 0 +OP4 E01642 0 +OP4 E01643 0 +OP4 E01644 0 +OP4 E01645 0 +OP4 E01646 0 +OP4 E01647 0 +OP4 E01648 0 +OP4 E01649 0 +OP4 E0164A 0 +OP4 E0164B 0 +OP4 E0164C 0 +OP4 E0164D 0 +OP4 E0164E 0 +OP4 E0164F 0 +OP4 E01650 0 +OP4 E01651 0 +OP4 E01652 0 +OP4 E01653 0 +OP4 E01654 0 +OP4 E01655 0 +OP4 E01656 0 +OP4 E01657 0 +OP4 E01658 0 +OP4 E01659 0 +OP4 E0165A 0 +OP4 E0165B 0 +OP4 E0165C 0 +OP4 E0165D 0 +OP4 E0165E 0 +OP4 E0165F 0 +OP4 E01660 0 +OP4 E01661 0 +OP4 E01662 0 +OP4 E01663 0 +OP4 E01664 0 +OP4 E01665 0 +OP4 E01666 0 +OP4 E01667 0 +OP4 E01668 0 +OP4 E01669 0 +OP4 E0166A 0 +OP4 E0166B 0 +OP4 E0166C 0 +OP4 E0166D 0 +OP4 E0166E 0 +OP4 E0166F 0 +OP4 E01670 0 +OP4 E01671 0 +OP4 E01672 0 +OP4 E01673 0 +OP4 E01674 0 +OP4 E01675 0 +OP4 E01676 0 +OP4 E01677 0 +OP4 E01678 0 +OP4 E01679 0 +OP4 E0167A 0 +OP4 E0167B 0 +OP4 E0167C 0 +OP4 E0167D 0 +OP4 E0167E 0 +OP4 E0167F 0 +OP4 E01680 0 +OP4 E01681 0 +OP4 E01682 0 +OP4 E01683 0 +OP4 E01684 0 +OP4 E01685 0 +OP4 E01686 0 +OP4 E01687 0 +OP4 E01688 0 +OP4 E01689 0 +OP4 E0168A 0 +OP4 E0168B 0 +OP4 E0168C 0 +OP4 E0168D 0 +OP4 E0168E 0 +OP4 E0168F 0 +OP4 E01690 0 +OP4 E01691 0 +OP4 E01692 0 +OP4 E01693 0 +OP4 E01694 0 +OP4 E01695 0 +OP4 E01696 0 +OP4 E01697 0 +OP4 E01698 0 +OP4 E01699 0 +OP4 E0169A 0 +OP4 E0169B 0 +OP4 E0169C 0 +OP4 E0169D 0 +OP4 E0169E 0 +OP4 E0169F 0 +OP4 E016A0 0 +OP4 E016A1 0 +OP4 E016A2 0 +OP4 E016A3 0 +OP4 E016A4 0 +OP4 E016A5 0 +OP4 E016A6 0 +OP4 E016A7 0 +OP4 E016A8 0 +OP4 E016A9 0 +OP4 E016AA 0 +OP4 E016AB 0 +OP4 E016AC 0 +OP4 E016AD 0 +OP4 E016AE 0 +OP4 E016AF 0 +OP4 E016B0 0 +OP4 E016B1 0 +OP4 E016B2 0 +OP4 E016B3 0 +OP4 E016B4 0 +OP4 E016B5 0 +OP4 E016B6 0 +OP4 E016B7 0 +OP4 E016B8 0 +OP4 E016B9 0 +OP4 E016BA 0 +OP4 E016BB 0 +OP4 E016BC 0 +OP4 E016BD 0 +OP4 E016BE 0 +OP4 E016BF 0 +OP4 E016C0 0 +OP4 E016C1 0 +OP4 E016C2 0 +OP4 E016C3 0 +OP4 E016C4 0 +OP4 E016C5 0 +OP4 E016C6 0 +OP4 E016C7 0 +OP4 E016C8 0 +OP4 E016C9 0 +OP4 E016CA 0 +OP4 E016CB 0 +OP4 E016CC 0 +OP4 E016CD 0 +OP4 E016CE 0 +OP4 E016CF 0 +OP4 E016D0 0 +OP4 E016D1 0 +OP4 E016D2 0 +OP4 E016D3 0 +OP4 E016D4 0 +OP4 E016D5 0 +OP4 E016D6 0 +OP4 E016D7 0 +OP4 E016D8 0 +OP4 E016D9 0 +OP4 E016DA 0 +OP4 E016DB 0 +OP4 E016DC 0 +OP4 E016DD 0 +OP4 E016DE 0 +OP4 E016DF 0 +OP4 E016E0 0 +OP4 E016E1 0 +OP4 E016E2 0 +OP4 E016E3 0 +OP4 E016E4 0 +OP4 E016E5 0 +OP4 E016E6 0 +OP4 E016E7 0 +OP4 E016E8 0 +OP4 E016E9 0 +OP4 E016EA 0 +OP4 E016EB 0 +OP4 E016EC 0 +OP4 E016ED 0 +OP4 E016EE 0 +OP4 E016EF 0 +OP4 E016F0 0 +OP4 E016F1 0 +OP4 E016F2 0 +OP4 E016F3 0 +OP4 E016F4 0 +OP4 E016F5 0 +OP4 E016F6 0 +OP4 E016F7 0 +OP4 E016F8 0 +OP4 E016F9 0 +OP4 E016FA 0 +OP4 E016FB 0 +OP4 E016FC 0 +OP4 E016FD 0 +OP4 E016FE 0 +OP4 E016FF 0 +OP4 E01700 0 +OP4 E01701 0 +OP4 E01702 0 +OP4 E01703 0 +OP4 E01704 0 +OP4 E01705 0 +OP4 E01706 0 +OP4 E01707 0 +OP4 E01708 0 +OP4 E01709 0 +OP4 E0170A 0 +OP4 E0170B 0 +OP4 E0170C 0 +OP4 E0170D 0 +OP4 E0170E 0 +OP4 E0170F 0 +OP4 E01710 0 +OP4 E01711 0 +OP4 E01712 0 +OP4 E01713 0 +OP4 E01714 0 +OP4 E01715 0 +OP4 E01716 0 +OP4 E01717 0 +OP4 E01718 0 +OP4 E01719 0 +OP4 E0171A 0 +OP4 E0171B 0 +OP4 E0171C 0 +OP4 E0171D 0 +OP4 E0171E 0 +OP4 E0171F 0 +OP4 E01720 0 +OP4 E01721 0 +OP4 E01722 0 +OP4 E01723 0 +OP4 E01724 0 +OP4 E01725 0 +OP4 E01726 0 +OP4 E01727 0 +OP4 E01728 0 +OP4 E01729 0 +OP4 E0172A 0 +OP4 E0172B 0 +OP4 E0172C 0 +OP4 E0172D 0 +OP4 E0172E 0 +OP4 E0172F 0 +OP4 E01730 0 +OP4 E01731 0 +OP4 E01732 0 +OP4 E01733 0 +OP4 E01734 0 +OP4 E01735 0 +OP4 E01736 0 +OP4 E01737 0 +OP4 E01738 0 +OP4 E01739 0 +OP4 E0173A 0 +OP4 E0173B 0 +OP4 E0173C 0 +OP4 E0173D 0 +OP4 E0173E 0 +OP4 E0173F 0 +OP4 E01740 0 +OP4 E01741 0 +OP4 E01742 0 +OP4 E01743 0 +OP4 E01744 0 +OP4 E01745 0 +OP4 E01746 0 +OP4 E01747 0 +OP4 E01748 0 +OP4 E01749 0 +OP4 E0174A 0 +OP4 E0174B 0 +OP4 E0174C 0 +OP4 E0174D 0 +OP4 E0174E 0 +OP4 E0174F 0 +OP4 E01750 0 +OP4 E01751 0 +OP4 E01752 0 +OP4 E01753 0 +OP4 E01754 0 +OP4 E01755 0 +OP4 E01756 0 +OP4 E01757 0 +OP4 E01758 0 +OP4 E01759 0 +OP4 E0175A 0 +OP4 E0175B 0 +OP4 E0175C 0 +OP4 E0175D 0 +OP4 E0175E 0 +OP4 E0175F 0 +OP4 E01760 0 +OP4 E01761 0 +OP4 E01762 0 +OP4 E01763 0 +OP4 E01764 0 +OP4 E01765 0 +OP4 E01766 0 +OP4 E01767 0 +OP4 E01768 0 +OP4 E01769 0 +OP4 E0176A 0 +OP4 E0176B 0 +OP4 E0176C 0 +OP4 E0176D 0 +OP4 E0176E 0 +OP4 E0176F 0 +OP4 E01770 0 +OP4 E01771 0 +OP4 E01772 0 +OP4 E01773 0 +OP4 E01774 0 +OP4 E01775 0 +OP4 E01776 0 +OP4 E01777 0 +OP4 E01778 0 +OP4 E01779 0 +OP4 E0177A 0 +OP4 E0177B 0 +OP4 E0177C 0 +OP4 E0177D 0 +OP4 E0177E 0 +OP4 E0177F 0 +OP4 E01780 0 +OP4 E01781 0 +OP4 E01782 0 +OP4 E01783 0 +OP4 E01784 0 +OP4 E01785 0 +OP4 E01786 0 +OP4 E01787 0 +OP4 E01788 0 +OP4 E01789 0 +OP4 E0178A 0 +OP4 E0178B 0 +OP4 E0178C 0 +OP4 E0178D 0 +OP4 E0178E 0 +OP4 E0178F 0 +OP4 E01790 0 +OP4 E01791 0 +OP4 E01792 0 +OP4 E01793 0 +OP4 E01794 0 +OP4 E01795 0 +OP4 E01796 0 +OP4 E01797 0 +OP4 E01798 0 +OP4 E01799 0 +OP4 E0179A 0 +OP4 E0179B 0 +OP4 E0179C 0 +OP4 E0179D 0 +OP4 E0179E 0 +OP4 E0179F 0 +OP4 E017A0 0 +OP4 E017A1 0 +OP4 E017A2 0 +OP4 E017A3 0 +OP4 E017A4 0 +OP4 E017A5 0 +OP4 E017A6 0 +OP4 E017A7 0 +OP4 E017A8 0 +OP4 E017A9 0 +OP4 E017AA 0 +OP4 E017AB 0 +OP4 E017AC 0 +OP4 E017AD 0 +OP4 E017AE 0 +OP4 E017AF 0 +OP4 E017B0 0 +OP4 E017B1 0 +OP4 E017B2 0 +OP4 E017B3 0 +OP4 E017B4 0 +OP4 E017B5 0 +OP4 E017B6 0 +OP4 E017B7 0 +OP4 E017B8 0 +OP4 E017B9 0 +OP4 E017BA 0 +OP4 E017BB 0 +OP4 E017BC 0 +OP4 E017BD 0 +OP4 E017BE 0 +OP4 E017BF 0 +OP4 E017C0 0 +OP4 E017C1 0 +OP4 E017C2 0 +OP4 E017C3 0 +OP4 E017C4 0 +OP4 E017C5 0 +OP4 E017C6 0 +OP4 E017C7 0 +OP4 E017C8 0 +OP4 E017C9 0 +OP4 E017CA 0 +OP4 E017CB 0 +OP4 E017CC 0 +OP4 E017CD 0 +OP4 E017CE 0 +OP4 E017CF 0 +OP4 E017D0 0 +OP4 E017D1 0 +OP4 E017D2 0 +OP4 E017D3 0 +OP4 E017D4 0 +OP4 E017D5 0 +OP4 E017D6 0 +OP4 E017D7 0 +OP4 E017D8 0 +OP4 E017D9 0 +OP4 E017DA 0 +OP4 E017DB 0 +OP4 E017DC 0 +OP4 E017DD 0 +OP4 E017DE 0 +OP4 E017DF 0 +OP4 E017E0 0 +OP4 E017E1 0 +OP4 E017E2 0 +OP4 E017E3 0 +OP4 E017E4 0 +OP4 E017E5 0 +OP4 E017E6 0 +OP4 E017E7 0 +OP4 E017E8 0 +OP4 E017E9 0 +OP4 E017EA 0 +OP4 E017EB 0 +OP4 E017EC 0 +OP4 E017ED 0 +OP4 E017EE 0 +OP4 E017EF 0 +OP4 E017F0 0 +OP4 E017F1 0 +OP4 E017F2 0 +OP4 E017F3 0 +OP4 E017F4 0 +OP4 E017F5 0 +OP4 E017F6 0 +OP4 E017F7 0 +OP4 E017F8 0 +OP4 E017F9 0 +OP4 E017FA 0 +OP4 E017FB 0 +OP4 E017FC 0 +OP4 E017FD 0 +OP4 E017FE 0 +OP4 E017FF 0 +OP4 E01800 0 +OP4 E01801 0 +OP4 E01802 0 +OP4 E01803 0 +OP4 E01804 0 +OP4 E01805 0 +OP4 E01806 0 +OP4 E01807 0 +OP4 E01808 0 +OP4 E01809 0 +OP4 E0180A 0 +OP4 E0180B 0 +OP4 E0180C 0 +OP4 E0180D 0 +OP4 E0180E 0 +OP4 E0180F 0 +OP4 E01810 0 +OP4 E01811 0 +OP4 E01812 0 +OP4 E01813 0 +OP4 E01814 0 +OP4 E01815 0 +OP4 E01816 0 +OP4 E01817 0 +OP4 E01818 0 +OP4 E01819 0 +OP4 E0181A 0 +OP4 E0181B 0 +OP4 E0181C 0 +OP4 E0181D 0 +OP4 E0181E 0 +OP4 E0181F 0 +OP4 E01820 0 +OP4 E01821 0 +OP4 E01822 0 +OP4 E01823 0 +OP4 E01824 0 +OP4 E01825 0 +OP4 E01826 0 +OP4 E01827 0 +OP4 E01828 0 +OP4 E01829 0 +OP4 E0182A 0 +OP4 E0182B 0 +OP4 E0182C 0 +OP4 E0182D 0 +OP4 E0182E 0 +OP4 E0182F 0 +OP4 E01830 0 +OP4 E01831 0 +OP4 E01832 0 +OP4 E01833 0 +OP4 E01834 0 +OP4 E01835 0 +OP4 E01836 0 +OP4 E01837 0 +OP4 E01838 0 +OP4 E01839 0 +OP4 E0183A 0 +OP4 E0183B 0 +OP4 E0183C 0 +OP4 E0183D 0 +OP4 E0183E 0 +OP4 E0183F 0 +OP4 E01840 0 +OP4 E01841 0 +OP4 E01842 0 +OP4 E01843 0 +OP4 E01844 0 +OP4 E01845 0 +OP4 E01846 0 +OP4 E01847 0 +OP4 E01848 0 +OP4 E01849 0 +OP4 E0184A 0 +OP4 E0184B 0 +OP4 E0184C 0 +OP4 E0184D 0 +OP4 E0184E 0 +OP4 E0184F 0 +OP4 E01850 0 +OP4 E01851 0 +OP4 E01852 0 +OP4 E01853 0 +OP4 E01854 0 +OP4 E01855 0 +OP4 E01856 0 +OP4 E01857 0 +OP4 E01858 0 +OP4 E01859 0 +OP4 E0185A 0 +OP4 E0185B 0 +OP4 E0185C 0 +OP4 E0185D 0 +OP4 E0185E 0 +OP4 E0185F 0 +OP4 E01860 0 +OP4 E01861 0 +OP4 E01862 0 +OP4 E01863 0 +OP4 E01864 0 +OP4 E01865 0 +OP4 E01866 0 +OP4 E01867 0 +OP4 E01868 0 +OP4 E01869 0 +OP4 E0186A 0 +OP4 E0186B 0 +OP4 E0186C 0 +OP4 E0186D 0 +OP4 E0186E 0 +OP4 E0186F 0 +OP4 E01870 0 +OP4 E01871 0 +OP4 E01872 0 +OP4 E01873 0 +OP4 E01874 0 +OP4 E01875 0 +OP4 E01876 0 +OP4 E01877 0 +OP4 E01878 0 +OP4 E01879 0 +OP4 E0187A 0 +OP4 E0187B 0 +OP4 E0187C 0 +OP4 E0187D 0 +OP4 E0187E 0 +OP4 E0187F 0 +OP4 E01880 0 +OP4 E01881 0 +OP4 E01882 0 +OP4 E01883 0 +OP4 E01884 0 +OP4 E01885 0 +OP4 E01886 0 +OP4 E01887 0 +OP4 E01888 0 +OP4 E01889 0 +OP4 E0188A 0 +OP4 E0188B 0 +OP4 E0188C 0 +OP4 E0188D 0 +OP4 E0188E 0 +OP4 E0188F 0 +OP4 E01890 0 +OP4 E01891 0 +OP4 E01892 0 +OP4 E01893 0 +OP4 E01894 0 +OP4 E01895 0 +OP4 E01896 0 +OP4 E01897 0 +OP4 E01898 0 +OP4 E01899 0 +OP4 E0189A 0 +OP4 E0189B 0 +OP4 E0189C 0 +OP4 E0189D 0 +OP4 E0189E 0 +OP4 E0189F 0 +OP4 E018A0 0 +OP4 E018A1 0 +OP4 E018A2 0 +OP4 E018A3 0 +OP4 E018A4 0 +OP4 E018A5 0 +OP4 E018A6 0 +OP4 E018A7 0 +OP4 E018A8 0 +OP4 E018A9 0 +OP4 E018AA 0 +OP4 E018AB 0 +OP4 E018AC 0 +OP4 E018AD 0 +OP4 E018AE 0 +OP4 E018AF 0 +OP4 E018B0 0 +OP4 E018B1 0 +OP4 E018B2 0 +OP4 E018B3 0 +OP4 E018B4 0 +OP4 E018B5 0 +OP4 E018B6 0 +OP4 E018B7 0 +OP4 E018B8 0 +OP4 E018B9 0 +OP4 E018BA 0 +OP4 E018BB 0 +OP4 E018BC 0 +OP4 E018BD 0 +OP4 E018BE 0 +OP4 E018BF 0 +OP4 E018C0 0 +OP4 E018C1 0 +OP4 E018C2 0 +OP4 E018C3 0 +OP4 E018C4 0 +OP4 E018C5 0 +OP4 E018C6 0 +OP4 E018C7 0 +OP4 E018C8 0 +OP4 E018C9 0 +OP4 E018CA 0 +OP4 E018CB 0 +OP4 E018CC 0 +OP4 E018CD 0 +OP4 E018CE 0 +OP4 E018CF 0 +OP4 E018D0 0 +OP4 E018D1 0 +OP4 E018D2 0 +OP4 E018D3 0 +OP4 E018D4 0 +OP4 E018D5 0 +OP4 E018D6 0 +OP4 E018D7 0 +OP4 E018D8 0 +OP4 E018D9 0 +OP4 E018DA 0 +OP4 E018DB 0 +OP4 E018DC 0 +OP4 E018DD 0 +OP4 E018DE 0 +OP4 E018DF 0 +OP4 E018E0 0 +OP4 E018E1 0 +OP4 E018E2 0 +OP4 E018E3 0 +OP4 E018E4 0 +OP4 E018E5 0 +OP4 E018E6 0 +OP4 E018E7 0 +OP4 E018E8 0 +OP4 E018E9 0 +OP4 E018EA 0 +OP4 E018EB 0 +OP4 E018EC 0 +OP4 E018ED 0 +OP4 E018EE 0 +OP4 E018EF 0 +OP4 E018F0 0 +OP4 E018F1 0 +OP4 E018F2 0 +OP4 E018F3 0 +OP4 E018F4 0 +OP4 E018F5 0 +OP4 E018F6 0 +OP4 E018F7 0 +OP4 E018F8 0 +OP4 E018F9 0 +OP4 E018FA 0 +OP4 E018FB 0 +OP4 E018FC 0 +OP4 E018FD 0 +OP4 E018FE 0 +OP4 E018FF 0 +OP4 E01900 0 +OP4 E01901 0 +OP4 E01902 0 +OP4 E01903 0 +OP4 E01904 0 +OP4 E01905 0 +OP4 E01906 0 +OP4 E01907 0 +OP4 E01908 0 +OP4 E01909 0 +OP4 E0190A 0 +OP4 E0190B 0 +OP4 E0190C 0 +OP4 E0190D 0 +OP4 E0190E 0 +OP4 E0190F 0 +OP4 E01910 0 +OP4 E01911 0 +OP4 E01912 0 +OP4 E01913 0 +OP4 E01914 0 +OP4 E01915 0 +OP4 E01916 0 +OP4 E01917 0 +OP4 E01918 0 +OP4 E01919 0 +OP4 E0191A 0 +OP4 E0191B 0 +OP4 E0191C 0 +OP4 E0191D 0 +OP4 E0191E 0 +OP4 E0191F 0 +OP4 E01920 0 +OP4 E01921 0 +OP4 E01922 0 +OP4 E01923 0 +OP4 E01924 0 +OP4 E01925 0 +OP4 E01926 0 +OP4 E01927 0 +OP4 E01928 0 +OP4 E01929 0 +OP4 E0192A 0 +OP4 E0192B 0 +OP4 E0192C 0 +OP4 E0192D 0 +OP4 E0192E 0 +OP4 E0192F 0 +OP4 E01930 0 +OP4 E01931 0 +OP4 E01932 0 +OP4 E01933 0 +OP4 E01934 0 +OP4 E01935 0 +OP4 E01936 0 +OP4 E01937 0 +OP4 E01938 0 +OP4 E01939 0 +OP4 E0193A 0 +OP4 E0193B 0 +OP4 E0193C 0 +OP4 E0193D 0 +OP4 E0193E 0 +OP4 E0193F 0 +OP4 E01940 0 +OP4 E01941 0 +OP4 E01942 0 +OP4 E01943 0 +OP4 E01944 0 +OP4 E01945 0 +OP4 E01946 0 +OP4 E01947 0 +OP4 E01948 0 +OP4 E01949 0 +OP4 E0194A 0 +OP4 E0194B 0 +OP4 E0194C 0 +OP4 E0194D 0 +OP4 E0194E 0 +OP4 E0194F 0 +OP4 E01950 0 +OP4 E01951 0 +OP4 E01952 0 +OP4 E01953 0 +OP4 E01954 0 +OP4 E01955 0 +OP4 E01956 0 +OP4 E01957 0 +OP4 E01958 0 +OP4 E01959 0 +OP4 E0195A 0 +OP4 E0195B 0 +OP4 E0195C 0 +OP4 E0195D 0 +OP4 E0195E 0 +OP4 E0195F 0 +OP4 E01960 0 +OP4 E01961 0 +OP4 E01962 0 +OP4 E01963 0 +OP4 E01964 0 +OP4 E01965 0 +OP4 E01966 0 +OP4 E01967 0 +OP4 E01968 0 +OP4 E01969 0 +OP4 E0196A 0 +OP4 E0196B 0 +OP4 E0196C 0 +OP4 E0196D 0 +OP4 E0196E 0 +OP4 E0196F 0 +OP4 E01970 0 +OP4 E01971 0 +OP4 E01972 0 +OP4 E01973 0 +OP4 E01974 0 +OP4 E01975 0 +OP4 E01976 0 +OP4 E01977 0 +OP4 E01978 0 +OP4 E01979 0 +OP4 E0197A 0 +OP4 E0197B 0 +OP4 E0197C 0 +OP4 E0197D 0 +OP4 E0197E 0 +OP4 E0197F 0 +OP4 E01980 0 +OP4 E01981 0 +OP4 E01982 0 +OP4 E01983 0 +OP4 E01984 0 +OP4 E01985 0 +OP4 E01986 0 +OP4 E01987 0 +OP4 E01988 0 +OP4 E01989 0 +OP4 E0198A 0 +OP4 E0198B 0 +OP4 E0198C 0 +OP4 E0198D 0 +OP4 E0198E 0 +OP4 E0198F 0 +OP4 E01990 0 +OP4 E01991 0 +OP4 E01992 0 +OP4 E01993 0 +OP4 E01994 0 +OP4 E01995 0 +OP4 E01996 0 +OP4 E01997 0 +OP4 E01998 0 +OP4 E01999 0 +OP4 E0199A 0 +OP4 E0199B 0 +OP4 E0199C 0 +OP4 E0199D 0 +OP4 E0199E 0 +OP4 E0199F 0 +OP4 E019A0 0 +OP4 E019A1 0 +OP4 E019A2 0 +OP4 E019A3 0 +OP4 E019A4 0 +OP4 E019A5 0 +OP4 E019A6 0 +OP4 E019A7 0 +OP4 E019A8 0 +OP4 E019A9 0 +OP4 E019AA 0 +OP4 E019AB 0 +OP4 E019AC 0 +OP4 E019AD 0 +OP4 E019AE 0 +OP4 E019AF 0 +OP4 E019B0 0 +OP4 E019B1 0 +OP4 E019B2 0 +OP4 E019B3 0 +OP4 E019B4 0 +OP4 E019B5 0 +OP4 E019B6 0 +OP4 E019B7 0 +OP4 E019B8 0 +OP4 E019B9 0 +OP4 E019BA 0 +OP4 E019BB 0 +OP4 E019BC 0 +OP4 E019BD 0 +OP4 E019BE 0 +OP4 E019BF 0 +OP4 E019C0 0 +OP4 E019C1 0 +OP4 E019C2 0 +OP4 E019C3 0 +OP4 E019C4 0 +OP4 E019C5 0 +OP4 E019C6 0 +OP4 E019C7 0 +OP4 E019C8 0 +OP4 E019C9 0 +OP4 E019CA 0 +OP4 E019CB 0 +OP4 E019CC 0 +OP4 E019CD 0 +OP4 E019CE 0 +OP4 E019CF 0 +OP4 E019D0 0 +OP4 E019D1 0 +OP4 E019D2 0 +OP4 E019D3 0 +OP4 E019D4 0 +OP4 E019D5 0 +OP4 E019D6 0 +OP4 E019D7 0 +OP4 E019D8 0 +OP4 E019D9 0 +OP4 E019DA 0 +OP4 E019DB 0 +OP4 E019DC 0 +OP4 E019DD 0 +OP4 E019DE 0 +OP4 E019DF 0 +OP4 E019E0 0 +OP4 E019E1 0 +OP4 E019E2 0 +OP4 E019E3 0 +OP4 E019E4 0 +OP4 E019E5 0 +OP4 E019E6 0 +OP4 E019E7 0 +OP4 E019E8 0 +OP4 E019E9 0 +OP4 E019EA 0 +OP4 E019EB 0 +OP4 E019EC 0 +OP4 E019ED 0 +OP4 E019EE 0 +OP4 E019EF 0 +OP4 E019F0 0 +OP4 E019F1 0 +OP4 E019F2 0 +OP4 E019F3 0 +OP4 E019F4 0 +OP4 E019F5 0 +OP4 E019F6 0 +OP4 E019F7 0 +OP4 E019F8 0 +OP4 E019F9 0 +OP4 E019FA 0 +OP4 E019FB 0 +OP4 E019FC 0 +OP4 E019FD 0 +OP4 E019FE 0 +OP4 E019FF 0 +OP4 E01A00 0 +OP4 E01A01 0 +OP4 E01A02 0 +OP4 E01A03 0 +OP4 E01A04 0 +OP4 E01A05 0 +OP4 E01A06 0 +OP4 E01A07 0 +OP4 E01A08 0 +OP4 E01A09 0 +OP4 E01A0A 0 +OP4 E01A0B 0 +OP4 E01A0C 0 +OP4 E01A0D 0 +OP4 E01A0E 0 +OP4 E01A0F 0 +OP4 E01A10 0 +OP4 E01A11 0 +OP4 E01A12 0 +OP4 E01A13 0 +OP4 E01A14 0 +OP4 E01A15 0 +OP4 E01A16 0 +OP4 E01A17 0 +OP4 E01A18 0 +OP4 E01A19 0 +OP4 E01A1A 0 +OP4 E01A1B 0 +OP4 E01A1C 0 +OP4 E01A1D 0 +OP4 E01A1E 0 +OP4 E01A1F 0 +OP4 E01A20 0 +OP4 E01A21 0 +OP4 E01A22 0 +OP4 E01A23 0 +OP4 E01A24 0 +OP4 E01A25 0 +OP4 E01A26 0 +OP4 E01A27 0 +OP4 E01A28 0 +OP4 E01A29 0 +OP4 E01A2A 0 +OP4 E01A2B 0 +OP4 E01A2C 0 +OP4 E01A2D 0 +OP4 E01A2E 0 +OP4 E01A2F 0 +OP4 E01A30 0 +OP4 E01A31 0 +OP4 E01A32 0 +OP4 E01A33 0 +OP4 E01A34 0 +OP4 E01A35 0 +OP4 E01A36 0 +OP4 E01A37 0 +OP4 E01A38 0 +OP4 E01A39 0 +OP4 E01A3A 0 +OP4 E01A3B 0 +OP4 E01A3C 0 +OP4 E01A3D 0 +OP4 E01A3E 0 +OP4 E01A3F 0 +OP4 E01A40 0 +OP4 E01A41 0 +OP4 E01A42 0 +OP4 E01A43 0 +OP4 E01A44 0 +OP4 E01A45 0 +OP4 E01A46 0 +OP4 E01A47 0 +OP4 E01A48 0 +OP4 E01A49 0 +OP4 E01A4A 0 +OP4 E01A4B 0 +OP4 E01A4C 0 +OP4 E01A4D 0 +OP4 E01A4E 0 +OP4 E01A4F 0 +OP4 E01A50 0 +OP4 E01A51 0 +OP4 E01A52 0 +OP4 E01A53 0 +OP4 E01A54 0 +OP4 E01A55 0 +OP4 E01A56 0 +OP4 E01A57 0 +OP4 E01A58 0 +OP4 E01A59 0 +OP4 E01A5A 0 +OP4 E01A5B 0 +OP4 E01A5C 0 +OP4 E01A5D 0 +OP4 E01A5E 0 +OP4 E01A5F 0 +OP4 E01A60 0 +OP4 E01A61 0 +OP4 E01A62 0 +OP4 E01A63 0 +OP4 E01A64 0 +OP4 E01A65 0 +OP4 E01A66 0 +OP4 E01A67 0 +OP4 E01A68 0 +OP4 E01A69 0 +OP4 E01A6A 0 +OP4 E01A6B 0 +OP4 E01A6C 0 +OP4 E01A6D 0 +OP4 E01A6E 0 +OP4 E01A6F 0 +OP4 E01A70 0 +OP4 E01A71 0 +OP4 E01A72 0 +OP4 E01A73 0 +OP4 E01A74 0 +OP4 E01A75 0 +OP4 E01A76 0 +OP4 E01A77 0 +OP4 E01A78 0 +OP4 E01A79 0 +OP4 E01A7A 0 +OP4 E01A7B 0 +OP4 E01A7C 0 +OP4 E01A7D 0 +OP4 E01A7E 0 +OP4 E01A7F 0 +OP4 E01A80 0 +OP4 E01A81 0 +OP4 E01A82 0 +OP4 E01A83 0 +OP4 E01A84 0 +OP4 E01A85 0 +OP4 E01A86 0 +OP4 E01A87 0 +OP4 E01A88 0 +OP4 E01A89 0 +OP4 E01A8A 0 +OP4 E01A8B 0 +OP4 E01A8C 0 +OP4 E01A8D 0 +OP4 E01A8E 0 +OP4 E01A8F 0 +OP4 E01A90 0 +OP4 E01A91 0 +OP4 E01A92 0 +OP4 E01A93 0 +OP4 E01A94 0 +OP4 E01A95 0 +OP4 E01A96 0 +OP4 E01A97 0 +OP4 E01A98 0 +OP4 E01A99 0 +OP4 E01A9A 0 +OP4 E01A9B 0 +OP4 E01A9C 0 +OP4 E01A9D 0 +OP4 E01A9E 0 +OP4 E01A9F 0 +OP4 E01AA0 0 +OP4 E01AA1 0 +OP4 E01AA2 0 +OP4 E01AA3 0 +OP4 E01AA4 0 +OP4 E01AA5 0 +OP4 E01AA6 0 +OP4 E01AA7 0 +OP4 E01AA8 0 +OP4 E01AA9 0 +OP4 E01AAA 0 +OP4 E01AAB 0 +OP4 E01AAC 0 +OP4 E01AAD 0 +OP4 E01AAE 0 +OP4 E01AAF 0 +OP4 E01AB0 0 +OP4 E01AB1 0 +OP4 E01AB2 0 +OP4 E01AB3 0 +OP4 E01AB4 0 +OP4 E01AB5 0 +OP4 E01AB6 0 +OP4 E01AB7 0 +OP4 E01AB8 0 +OP4 E01AB9 0 +OP4 E01ABA 0 +OP4 E01ABB 0 +OP4 E01ABC 0 +OP4 E01ABD 0 +OP4 E01ABE 0 +OP4 E01ABF 0 +OP4 E01AC0 0 +OP4 E01AC1 0 +OP4 E01AC2 0 +OP4 E01AC3 0 +OP4 E01AC4 0 +OP4 E01AC5 0 +OP4 E01AC6 0 +OP4 E01AC7 0 +OP4 E01AC8 0 +OP4 E01AC9 0 +OP4 E01ACA 0 +OP4 E01ACB 0 +OP4 E01ACC 0 +OP4 E01ACD 0 +OP4 E01ACE 0 +OP4 E01ACF 0 +OP4 E01AD0 0 +OP4 E01AD1 0 +OP4 E01AD2 0 +OP4 E01AD3 0 +OP4 E01AD4 0 +OP4 E01AD5 0 +OP4 E01AD6 0 +OP4 E01AD7 0 +OP4 E01AD8 0 +OP4 E01AD9 0 +OP4 E01ADA 0 +OP4 E01ADB 0 +OP4 E01ADC 0 +OP4 E01ADD 0 +OP4 E01ADE 0 +OP4 E01ADF 0 +OP4 E01AE0 0 +OP4 E01AE1 0 +OP4 E01AE2 0 +OP4 E01AE3 0 +OP4 E01AE4 0 +OP4 E01AE5 0 +OP4 E01AE6 0 +OP4 E01AE7 0 +OP4 E01AE8 0 +OP4 E01AE9 0 +OP4 E01AEA 0 +OP4 E01AEB 0 +OP4 E01AEC 0 +OP4 E01AED 0 +OP4 E01AEE 0 +OP4 E01AEF 0 +OP4 E01AF0 0 +OP4 E01AF1 0 +OP4 E01AF2 0 +OP4 E01AF3 0 +OP4 E01AF4 0 +OP4 E01AF5 0 +OP4 E01AF6 0 +OP4 E01AF7 0 +OP4 E01AF8 0 +OP4 E01AF9 0 +OP4 E01AFA 0 +OP4 E01AFB 0 +OP4 E01AFC 0 +OP4 E01AFD 0 +OP4 E01AFE 0 +OP4 E01AFF 0 +OP4 E01B00 0 +OP4 E01B01 0 +OP4 E01B02 0 +OP4 E01B03 0 +OP4 E01B04 0 +OP4 E01B05 0 +OP4 E01B06 0 +OP4 E01B07 0 +OP4 E01B08 0 +OP4 E01B09 0 +OP4 E01B0A 0 +OP4 E01B0B 0 +OP4 E01B0C 0 +OP4 E01B0D 0 +OP4 E01B0E 0 +OP4 E01B0F 0 +OP4 E01B10 0 +OP4 E01B11 0 +OP4 E01B12 0 +OP4 E01B13 0 +OP4 E01B14 0 +OP4 E01B15 0 +OP4 E01B16 0 +OP4 E01B17 0 +OP4 E01B18 0 +OP4 E01B19 0 +OP4 E01B1A 0 +OP4 E01B1B 0 +OP4 E01B1C 0 +OP4 E01B1D 0 +OP4 E01B1E 0 +OP4 E01B1F 0 +OP4 E01B20 0 +OP4 E01B21 0 +OP4 E01B22 0 +OP4 E01B23 0 +OP4 E01B24 0 +OP4 E01B25 0 +OP4 E01B26 0 +OP4 E01B27 0 +OP4 E01B28 0 +OP4 E01B29 0 +OP4 E01B2A 0 +OP4 E01B2B 0 +OP4 E01B2C 0 +OP4 E01B2D 0 +OP4 E01B2E 0 +OP4 E01B2F 0 +OP4 E01B30 0 +OP4 E01B31 0 +OP4 E01B32 0 +OP4 E01B33 0 +OP4 E01B34 0 +OP4 E01B35 0 +OP4 E01B36 0 +OP4 E01B37 0 +OP4 E01B38 0 +OP4 E01B39 0 +OP4 E01B3A 0 +OP4 E01B3B 0 +OP4 E01B3C 0 +OP4 E01B3D 0 +OP4 E01B3E 0 +OP4 E01B3F 0 +OP4 E01B40 0 +OP4 E01B41 0 +OP4 E01B42 0 +OP4 E01B43 0 +OP4 E01B44 0 +OP4 E01B45 0 +OP4 E01B46 0 +OP4 E01B47 0 +OP4 E01B48 0 +OP4 E01B49 0 +OP4 E01B4A 0 +OP4 E01B4B 0 +OP4 E01B4C 0 +OP4 E01B4D 0 +OP4 E01B4E 0 +OP4 E01B4F 0 +OP4 E01B50 0 +OP4 E01B51 0 +OP4 E01B52 0 +OP4 E01B53 0 +OP4 E01B54 0 +OP4 E01B55 0 +OP4 E01B56 0 +OP4 E01B57 0 +OP4 E01B58 0 +OP4 E01B59 0 +OP4 E01B5A 0 +OP4 E01B5B 0 +OP4 E01B5C 0 +OP4 E01B5D 0 +OP4 E01B5E 0 +OP4 E01B5F 0 +OP4 E01B60 0 +OP4 E01B61 0 +OP4 E01B62 0 +OP4 E01B63 0 +OP4 E01B64 0 +OP4 E01B65 0 +OP4 E01B66 0 +OP4 E01B67 0 +OP4 E01B68 0 +OP4 E01B69 0 +OP4 E01B6A 0 +OP4 E01B6B 0 +OP4 E01B6C 0 +OP4 E01B6D 0 +OP4 E01B6E 0 +OP4 E01B6F 0 +OP4 E01B70 0 +OP4 E01B71 0 +OP4 E01B72 0 +OP4 E01B73 0 +OP4 E01B74 0 +OP4 E01B75 0 +OP4 E01B76 0 +OP4 E01B77 0 +OP4 E01B78 0 +OP4 E01B79 0 +OP4 E01B7A 0 +OP4 E01B7B 0 +OP4 E01B7C 0 +OP4 E01B7D 0 +OP4 E01B7E 0 +OP4 E01B7F 0 +OP4 E01B80 0 +OP4 E01B81 0 +OP4 E01B82 0 +OP4 E01B83 0 +OP4 E01B84 0 +OP4 E01B85 0 +OP4 E01B86 0 +OP4 E01B87 0 +OP4 E01B88 0 +OP4 E01B89 0 +OP4 E01B8A 0 +OP4 E01B8B 0 +OP4 E01B8C 0 +OP4 E01B8D 0 +OP4 E01B8E 0 +OP4 E01B8F 0 +OP4 E01B90 0 +OP4 E01B91 0 +OP4 E01B92 0 +OP4 E01B93 0 +OP4 E01B94 0 +OP4 E01B95 0 +OP4 E01B96 0 +OP4 E01B97 0 +OP4 E01B98 0 +OP4 E01B99 0 +OP4 E01B9A 0 +OP4 E01B9B 0 +OP4 E01B9C 0 +OP4 E01B9D 0 +OP4 E01B9E 0 +OP4 E01B9F 0 +OP4 E01BA0 0 +OP4 E01BA1 0 +OP4 E01BA2 0 +OP4 E01BA3 0 +OP4 E01BA4 0 +OP4 E01BA5 0 +OP4 E01BA6 0 +OP4 E01BA7 0 +OP4 E01BA8 0 +OP4 E01BA9 0 +OP4 E01BAA 0 +OP4 E01BAB 0 +OP4 E01BAC 0 +OP4 E01BAD 0 +OP4 E01BAE 0 +OP4 E01BAF 0 +OP4 E01BB0 0 +OP4 E01BB1 0 +OP4 E01BB2 0 +OP4 E01BB3 0 +OP4 E01BB4 0 +OP4 E01BB5 0 +OP4 E01BB6 0 +OP4 E01BB7 0 +OP4 E01BB8 0 +OP4 E01BB9 0 +OP4 E01BBA 0 +OP4 E01BBB 0 +OP4 E01BBC 0 +OP4 E01BBD 0 +OP4 E01BBE 0 +OP4 E01BBF 0 +OP4 E01BC0 0 +OP4 E01BC1 0 +OP4 E01BC2 0 +OP4 E01BC3 0 +OP4 E01BC4 0 +OP4 E01BC5 0 +OP4 E01BC6 0 +OP4 E01BC7 0 +OP4 E01BC8 0 +OP4 E01BC9 0 +OP4 E01BCA 0 +OP4 E01BCB 0 +OP4 E01BCC 0 +OP4 E01BCD 0 +OP4 E01BCE 0 +OP4 E01BCF 0 +OP4 E01BD0 0 +OP4 E01BD1 0 +OP4 E01BD2 0 +OP4 E01BD3 0 +OP4 E01BD4 0 +OP4 E01BD5 0 +OP4 E01BD6 0 +OP4 E01BD7 0 +OP4 E01BD8 0 +OP4 E01BD9 0 +OP4 E01BDA 0 +OP4 E01BDB 0 +OP4 E01BDC 0 +OP4 E01BDD 0 +OP4 E01BDE 0 +OP4 E01BDF 0 +OP4 E01BE0 0 +OP4 E01BE1 0 +OP4 E01BE2 0 +OP4 E01BE3 0 +OP4 E01BE4 0 +OP4 E01BE5 0 +OP4 E01BE6 0 +OP4 E01BE7 0 +OP4 E01BE8 0 +OP4 E01BE9 0 +OP4 E01BEA 0 +OP4 E01BEB 0 +OP4 E01BEC 0 +OP4 E01BED 0 +OP4 E01BEE 0 +OP4 E01BEF 0 +OP4 E01BF0 0 +OP4 E01BF1 0 +OP4 E01BF2 0 +OP4 E01BF3 0 +OP4 E01BF4 0 +OP4 E01BF5 0 +OP4 E01BF6 0 +OP4 E01BF7 0 +OP4 E01BF8 0 +OP4 E01BF9 0 +OP4 E01BFA 0 +OP4 E01BFB 0 +OP4 E01BFC 0 +OP4 E01BFD 0 +OP4 E01BFE 0 +OP4 E01BFF 0 +OP4 E01C00 0 +OP4 E01C01 0 +OP4 E01C02 0 +OP4 E01C03 0 +OP4 E01C04 0 +OP4 E01C05 0 +OP4 E01C06 0 +OP4 E01C07 0 +OP4 E01C08 0 +OP4 E01C09 0 +OP4 E01C0A 0 +OP4 E01C0B 0 +OP4 E01C0C 0 +OP4 E01C0D 0 +OP4 E01C0E 0 +OP4 E01C0F 0 +OP4 E01C10 0 +OP4 E01C11 0 +OP4 E01C12 0 +OP4 E01C13 0 +OP4 E01C14 0 +OP4 E01C15 0 +OP4 E01C16 0 +OP4 E01C17 0 +OP4 E01C18 0 +OP4 E01C19 0 +OP4 E01C1A 0 +OP4 E01C1B 0 +OP4 E01C1C 0 +OP4 E01C1D 0 +OP4 E01C1E 0 +OP4 E01C1F 0 +OP4 E01C20 0 +OP4 E01C21 0 +OP4 E01C22 0 +OP4 E01C23 0 +OP4 E01C24 0 +OP4 E01C25 0 +OP4 E01C26 0 +OP4 E01C27 0 +OP4 E01C28 0 +OP4 E01C29 0 +OP4 E01C2A 0 +OP4 E01C2B 0 +OP4 E01C2C 0 +OP4 E01C2D 0 +OP4 E01C2E 0 +OP4 E01C2F 0 +OP4 E01C30 0 +OP4 E01C31 0 +OP4 E01C32 0 +OP4 E01C33 0 +OP4 E01C34 0 +OP4 E01C35 0 +OP4 E01C36 0 +OP4 E01C37 0 +OP4 E01C38 0 +OP4 E01C39 0 +OP4 E01C3A 0 +OP4 E01C3B 0 +OP4 E01C3C 0 +OP4 E01C3D 0 +OP4 E01C3E 0 +OP4 E01C3F 0 +OP4 E01C40 0 +OP4 E01C41 0 +OP4 E01C42 0 +OP4 E01C43 0 +OP4 E01C44 0 +OP4 E01C45 0 +OP4 E01C46 0 +OP4 E01C47 0 +OP4 E01C48 0 +OP4 E01C49 0 +OP4 E01C4A 0 +OP4 E01C4B 0 +OP4 E01C4C 0 +OP4 E01C4D 0 +OP4 E01C4E 0 +OP4 E01C4F 0 +OP4 E01C50 0 +OP4 E01C51 0 +OP4 E01C52 0 +OP4 E01C53 0 +OP4 E01C54 0 +OP4 E01C55 0 +OP4 E01C56 0 +OP4 E01C57 0 +OP4 E01C58 0 +OP4 E01C59 0 +OP4 E01C5A 0 +OP4 E01C5B 0 +OP4 E01C5C 0 +OP4 E01C5D 0 +OP4 E01C5E 0 +OP4 E01C5F 0 +OP4 E01C60 0 +OP4 E01C61 0 +OP4 E01C62 0 +OP4 E01C63 0 +OP4 E01C64 0 +OP4 E01C65 0 +OP4 E01C66 0 +OP4 E01C67 0 +OP4 E01C68 0 +OP4 E01C69 0 +OP4 E01C6A 0 +OP4 E01C6B 0 +OP4 E01C6C 0 +OP4 E01C6D 0 +OP4 E01C6E 0 +OP4 E01C6F 0 +OP4 E01C70 0 +OP4 E01C71 0 +OP4 E01C72 0 +OP4 E01C73 0 +OP4 E01C74 0 +OP4 E01C75 0 +OP4 E01C76 0 +OP4 E01C77 0 +OP4 E01C78 0 +OP4 E01C79 0 +OP4 E01C7A 0 +OP4 E01C7B 0 +OP4 E01C7C 0 +OP4 E01C7D 0 +OP4 E01C7E 0 +OP4 E01C7F 0 +OP4 E01C80 0 +OP4 E01C81 0 +OP4 E01C82 0 +OP4 E01C83 0 +OP4 E01C84 0 +OP4 E01C85 0 +OP4 E01C86 0 +OP4 E01C87 0 +OP4 E01C88 0 +OP4 E01C89 0 +OP4 E01C8A 0 +OP4 E01C8B 0 +OP4 E01C8C 0 +OP4 E01C8D 0 +OP4 E01C8E 0 +OP4 E01C8F 0 +OP4 E01C90 0 +OP4 E01C91 0 +OP4 E01C92 0 +OP4 E01C93 0 +OP4 E01C94 0 +OP4 E01C95 0 +OP4 E01C96 0 +OP4 E01C97 0 +OP4 E01C98 0 +OP4 E01C99 0 +OP4 E01C9A 0 +OP4 E01C9B 0 +OP4 E01C9C 0 +OP4 E01C9D 0 +OP4 E01C9E 0 +OP4 E01C9F 0 +OP4 E01CA0 0 +OP4 E01CA1 0 +OP4 E01CA2 0 +OP4 E01CA3 0 +OP4 E01CA4 0 +OP4 E01CA5 0 +OP4 E01CA6 0 +OP4 E01CA7 0 +OP4 E01CA8 0 +OP4 E01CA9 0 +OP4 E01CAA 0 +OP4 E01CAB 0 +OP4 E01CAC 0 +OP4 E01CAD 0 +OP4 E01CAE 0 +OP4 E01CAF 0 +OP4 E01CB0 0 +OP4 E01CB1 0 +OP4 E01CB2 0 +OP4 E01CB3 0 +OP4 E01CB4 0 +OP4 E01CB5 0 +OP4 E01CB6 0 +OP4 E01CB7 0 +OP4 E01CB8 0 +OP4 E01CB9 0 +OP4 E01CBA 0 +OP4 E01CBB 0 +OP4 E01CBC 0 +OP4 E01CBD 0 +OP4 E01CBE 0 +OP4 E01CBF 0 +OP4 E01CC0 0 +OP4 E01CC1 0 +OP4 E01CC2 0 +OP4 E01CC3 0 +OP4 E01CC4 0 +OP4 E01CC5 0 +OP4 E01CC6 0 +OP4 E01CC7 0 +OP4 E01CC8 0 +OP4 E01CC9 0 +OP4 E01CCA 0 +OP4 E01CCB 0 +OP4 E01CCC 0 +OP4 E01CCD 0 +OP4 E01CCE 0 +OP4 E01CCF 0 +OP4 E01CD0 0 +OP4 E01CD1 0 +OP4 E01CD2 0 +OP4 E01CD3 0 +OP4 E01CD4 0 +OP4 E01CD5 0 +OP4 E01CD6 0 +OP4 E01CD7 0 +OP4 E01CD8 0 +OP4 E01CD9 0 +OP4 E01CDA 0 +OP4 E01CDB 0 +OP4 E01CDC 0 +OP4 E01CDD 0 +OP4 E01CDE 0 +OP4 E01CDF 0 +OP4 E01CE0 0 +OP4 E01CE1 0 +OP4 E01CE2 0 +OP4 E01CE3 0 +OP4 E01CE4 0 +OP4 E01CE5 0 +OP4 E01CE6 0 +OP4 E01CE7 0 +OP4 E01CE8 0 +OP4 E01CE9 0 +OP4 E01CEA 0 +OP4 E01CEB 0 +OP4 E01CEC 0 +OP4 E01CED 0 +OP4 E01CEE 0 +OP4 E01CEF 0 +OP4 E01CF0 0 +OP4 E01CF1 0 +OP4 E01CF2 0 +OP4 E01CF3 0 +OP4 E01CF4 0 +OP4 E01CF5 0 +OP4 E01CF6 0 +OP4 E01CF7 0 +OP4 E01CF8 0 +OP4 E01CF9 0 +OP4 E01CFA 0 +OP4 E01CFB 0 +OP4 E01CFC 0 +OP4 E01CFD 0 +OP4 E01CFE 0 +OP4 E01CFF 0 +OP4 E01D00 0 +OP4 E01D01 0 +OP4 E01D02 0 +OP4 E01D03 0 +OP4 E01D04 0 +OP4 E01D05 0 +OP4 E01D06 0 +OP4 E01D07 0 +OP4 E01D08 0 +OP4 E01D09 0 +OP4 E01D0A 0 +OP4 E01D0B 0 +OP4 E01D0C 0 +OP4 E01D0D 0 +OP4 E01D0E 0 +OP4 E01D0F 0 +OP4 E01D10 0 +OP4 E01D11 0 +OP4 E01D12 0 +OP4 E01D13 0 +OP4 E01D14 0 +OP4 E01D15 0 +OP4 E01D16 0 +OP4 E01D17 0 +OP4 E01D18 0 +OP4 E01D19 0 +OP4 E01D1A 0 +OP4 E01D1B 0 +OP4 E01D1C 0 +OP4 E01D1D 0 +OP4 E01D1E 0 +OP4 E01D1F 0 +OP4 E01D20 0 +OP4 E01D21 0 +OP4 E01D22 0 +OP4 E01D23 0 +OP4 E01D24 0 +OP4 E01D25 0 +OP4 E01D26 0 +OP4 E01D27 0 +OP4 E01D28 0 +OP4 E01D29 0 +OP4 E01D2A 0 +OP4 E01D2B 0 +OP4 E01D2C 0 +OP4 E01D2D 0 +OP4 E01D2E 0 +OP4 E01D2F 0 +OP4 E01D30 0 +OP4 E01D31 0 +OP4 E01D32 0 +OP4 E01D33 0 +OP4 E01D34 0 +OP4 E01D35 0 +OP4 E01D36 0 +OP4 E01D37 0 +OP4 E01D38 0 +OP4 E01D39 0 +OP4 E01D3A 0 +OP4 E01D3B 0 +OP4 E01D3C 0 +OP4 E01D3D 0 +OP4 E01D3E 0 +OP4 E01D3F 0 +OP4 E01D40 0 +OP4 E01D41 0 +OP4 E01D42 0 +OP4 E01D43 0 +OP4 E01D44 0 +OP4 E01D45 0 +OP4 E01D46 0 +OP4 E01D47 0 +OP4 E01D48 0 +OP4 E01D49 0 +OP4 E01D4A 0 +OP4 E01D4B 0 +OP4 E01D4C 0 +OP4 E01D4D 0 +OP4 E01D4E 0 +OP4 E01D4F 0 +OP4 E01D50 0 +OP4 E01D51 0 +OP4 E01D52 0 +OP4 E01D53 0 +OP4 E01D54 0 +OP4 E01D55 0 +OP4 E01D56 0 +OP4 E01D57 0 +OP4 E01D58 0 +OP4 E01D59 0 +OP4 E01D5A 0 +OP4 E01D5B 0 +OP4 E01D5C 0 +OP4 E01D5D 0 +OP4 E01D5E 0 +OP4 E01D5F 0 +OP4 E01D60 0 +OP4 E01D61 0 +OP4 E01D62 0 +OP4 E01D63 0 +OP4 E01D64 0 +OP4 E01D65 0 +OP4 E01D66 0 +OP4 E01D67 0 +OP4 E01D68 0 +OP4 E01D69 0 +OP4 E01D6A 0 +OP4 E01D6B 0 +OP4 E01D6C 0 +OP4 E01D6D 0 +OP4 E01D6E 0 +OP4 E01D6F 0 +OP4 E01D70 0 +OP4 E01D71 0 +OP4 E01D72 0 +OP4 E01D73 0 +OP4 E01D74 0 +OP4 E01D75 0 +OP4 E01D76 0 +OP4 E01D77 0 +OP4 E01D78 0 +OP4 E01D79 0 +OP4 E01D7A 0 +OP4 E01D7B 0 +OP4 E01D7C 0 +OP4 E01D7D 0 +OP4 E01D7E 0 +OP4 E01D7F 0 +OP4 E01D80 0 +OP4 E01D81 0 +OP4 E01D82 0 +OP4 E01D83 0 +OP4 E01D84 0 +OP4 E01D85 0 +OP4 E01D86 0 +OP4 E01D87 0 +OP4 E01D88 0 +OP4 E01D89 0 +OP4 E01D8A 0 +OP4 E01D8B 0 +OP4 E01D8C 0 +OP4 E01D8D 0 +OP4 E01D8E 0 +OP4 E01D8F 0 +OP4 E01D90 0 +OP4 E01D91 0 +OP4 E01D92 0 +OP4 E01D93 0 +OP4 E01D94 0 +OP4 E01D95 0 +OP4 E01D96 0 +OP4 E01D97 0 +OP4 E01D98 0 +OP4 E01D99 0 +OP4 E01D9A 0 +OP4 E01D9B 0 +OP4 E01D9C 0 +OP4 E01D9D 0 +OP4 E01D9E 0 +OP4 E01D9F 0 +OP4 E01DA0 0 +OP4 E01DA1 0 +OP4 E01DA2 0 +OP4 E01DA3 0 +OP4 E01DA4 0 +OP4 E01DA5 0 +OP4 E01DA6 0 +OP4 E01DA7 0 +OP4 E01DA8 0 +OP4 E01DA9 0 +OP4 E01DAA 0 +OP4 E01DAB 0 +OP4 E01DAC 0 +OP4 E01DAD 0 +OP4 E01DAE 0 +OP4 E01DAF 0 +OP4 E01DB0 0 +OP4 E01DB1 0 +OP4 E01DB2 0 +OP4 E01DB3 0 +OP4 E01DB4 0 +OP4 E01DB5 0 +OP4 E01DB6 0 +OP4 E01DB7 0 +OP4 E01DB8 0 +OP4 E01DB9 0 +OP4 E01DBA 0 +OP4 E01DBB 0 +OP4 E01DBC 0 +OP4 E01DBD 0 +OP4 E01DBE 0 +OP4 E01DBF 0 +OP4 E01DC0 0 +OP4 E01DC1 0 +OP4 E01DC2 0 +OP4 E01DC3 0 +OP4 E01DC4 0 +OP4 E01DC5 0 +OP4 E01DC6 0 +OP4 E01DC7 0 +OP4 E01DC8 0 +OP4 E01DC9 0 +OP4 E01DCA 0 +OP4 E01DCB 0 +OP4 E01DCC 0 +OP4 E01DCD 0 +OP4 E01DCE 0 +OP4 E01DCF 0 +OP4 E01DD0 0 +OP4 E01DD1 0 +OP4 E01DD2 0 +OP4 E01DD3 0 +OP4 E01DD4 0 +OP4 E01DD5 0 +OP4 E01DD6 0 +OP4 E01DD7 0 +OP4 E01DD8 0 +OP4 E01DD9 0 +OP4 E01DDA 0 +OP4 E01DDB 0 +OP4 E01DDC 0 +OP4 E01DDD 0 +OP4 E01DDE 0 +OP4 E01DDF 0 +OP4 E01DE0 0 +OP4 E01DE1 0 +OP4 E01DE2 0 +OP4 E01DE3 0 +OP4 E01DE4 0 +OP4 E01DE5 0 +OP4 E01DE6 0 +OP4 E01DE7 0 +OP4 E01DE8 0 +OP4 E01DE9 0 +OP4 E01DEA 0 +OP4 E01DEB 0 +OP4 E01DEC 0 +OP4 E01DED 0 +OP4 E01DEE 0 +OP4 E01DEF 0 +OP4 E01DF0 0 +OP4 E01DF1 0 +OP4 E01DF2 0 +OP4 E01DF3 0 +OP4 E01DF4 0 +OP4 E01DF5 0 +OP4 E01DF6 0 +OP4 E01DF7 0 +OP4 E01DF8 0 +OP4 E01DF9 0 +OP4 E01DFA 0 +OP4 E01DFB 0 +OP4 E01DFC 0 +OP4 E01DFD 0 +OP4 E01DFE 0 +OP4 E01DFF 0 +OP4 E01E00 0 +OP4 E01E01 0 +OP4 E01E02 0 +OP4 E01E03 0 +OP4 E01E04 0 +OP4 E01E05 0 +OP4 E01E06 0 +OP4 E01E07 0 +OP4 E01E08 0 +OP4 E01E09 0 +OP4 E01E0A 0 +OP4 E01E0B 0 +OP4 E01E0C 0 +OP4 E01E0D 0 +OP4 E01E0E 0 +OP4 E01E0F 0 +OP4 E01E10 0 +OP4 E01E11 0 +OP4 E01E12 0 +OP4 E01E13 0 +OP4 E01E14 0 +OP4 E01E15 0 +OP4 E01E16 0 +OP4 E01E17 0 +OP4 E01E18 0 +OP4 E01E19 0 +OP4 E01E1A 0 +OP4 E01E1B 0 +OP4 E01E1C 0 +OP4 E01E1D 0 +OP4 E01E1E 0 +OP4 E01E1F 0 +OP4 E01E20 0 +OP4 E01E21 0 +OP4 E01E22 0 +OP4 E01E23 0 +OP4 E01E24 0 +OP4 E01E25 0 +OP4 E01E26 0 +OP4 E01E27 0 +OP4 E01E28 0 +OP4 E01E29 0 +OP4 E01E2A 0 +OP4 E01E2B 0 +OP4 E01E2C 0 +OP4 E01E2D 0 +OP4 E01E2E 0 +OP4 E01E2F 0 +OP4 E01E30 0 +OP4 E01E31 0 +OP4 E01E32 0 +OP4 E01E33 0 +OP4 E01E34 0 +OP4 E01E35 0 +OP4 E01E36 0 +OP4 E01E37 0 +OP4 E01E38 0 +OP4 E01E39 0 +OP4 E01E3A 0 +OP4 E01E3B 0 +OP4 E01E3C 0 +OP4 E01E3D 0 +OP4 E01E3E 0 +OP4 E01E3F 0 +OP4 E01E40 0 +OP4 E01E41 0 +OP4 E01E42 0 +OP4 E01E43 0 +OP4 E01E44 0 +OP4 E01E45 0 +OP4 E01E46 0 +OP4 E01E47 0 +OP4 E01E48 0 +OP4 E01E49 0 +OP4 E01E4A 0 +OP4 E01E4B 0 +OP4 E01E4C 0 +OP4 E01E4D 0 +OP4 E01E4E 0 +OP4 E01E4F 0 +OP4 E01E50 0 +OP4 E01E51 0 +OP4 E01E52 0 +OP4 E01E53 0 +OP4 E01E54 0 +OP4 E01E55 0 +OP4 E01E56 0 +OP4 E01E57 0 +OP4 E01E58 0 +OP4 E01E59 0 +OP4 E01E5A 0 +OP4 E01E5B 0 +OP4 E01E5C 0 +OP4 E01E5D 0 +OP4 E01E5E 0 +OP4 E01E5F 0 +OP4 E01E60 0 +OP4 E01E61 0 +OP4 E01E62 0 +OP4 E01E63 0 +OP4 E01E64 0 +OP4 E01E65 0 +OP4 E01E66 0 +OP4 E01E67 0 +OP4 E01E68 0 +OP4 E01E69 0 +OP4 E01E6A 0 +OP4 E01E6B 0 +OP4 E01E6C 0 +OP4 E01E6D 0 +OP4 E01E6E 0 +OP4 E01E6F 0 +OP4 E01E70 0 +OP4 E01E71 0 +OP4 E01E72 0 +OP4 E01E73 0 +OP4 E01E74 0 +OP4 E01E75 0 +OP4 E01E76 0 +OP4 E01E77 0 +OP4 E01E78 0 +OP4 E01E79 0 +OP4 E01E7A 0 +OP4 E01E7B 0 +OP4 E01E7C 0 +OP4 E01E7D 0 +OP4 E01E7E 0 +OP4 E01E7F 0 +OP4 E01E80 0 +OP4 E01E81 0 +OP4 E01E82 0 +OP4 E01E83 0 +OP4 E01E84 0 +OP4 E01E85 0 +OP4 E01E86 0 +OP4 E01E87 0 +OP4 E01E88 0 +OP4 E01E89 0 +OP4 E01E8A 0 +OP4 E01E8B 0 +OP4 E01E8C 0 +OP4 E01E8D 0 +OP4 E01E8E 0 +OP4 E01E8F 0 +OP4 E01E90 0 +OP4 E01E91 0 +OP4 E01E92 0 +OP4 E01E93 0 +OP4 E01E94 0 +OP4 E01E95 0 +OP4 E01E96 0 +OP4 E01E97 0 +OP4 E01E98 0 +OP4 E01E99 0 +OP4 E01E9A 0 +OP4 E01E9B 0 +OP4 E01E9C 0 +OP4 E01E9D 0 +OP4 E01E9E 0 +OP4 E01E9F 0 +OP4 E01EA0 0 +OP4 E01EA1 0 +OP4 E01EA2 0 +OP4 E01EA3 0 +OP4 E01EA4 0 +OP4 E01EA5 0 +OP4 E01EA6 0 +OP4 E01EA7 0 +OP4 E01EA8 0 +OP4 E01EA9 0 +OP4 E01EAA 0 +OP4 E01EAB 0 +OP4 E01EAC 0 +OP4 E01EAD 0 +OP4 E01EAE 0 +OP4 E01EAF 0 +OP4 E01EB0 0 +OP4 E01EB1 0 +OP4 E01EB2 0 +OP4 E01EB3 0 +OP4 E01EB4 0 +OP4 E01EB5 0 +OP4 E01EB6 0 +OP4 E01EB7 0 +OP4 E01EB8 0 +OP4 E01EB9 0 +OP4 E01EBA 0 +OP4 E01EBB 0 +OP4 E01EBC 0 +OP4 E01EBD 0 +OP4 E01EBE 0 +OP4 E01EBF 0 +OP4 E01EC0 0 +OP4 E01EC1 0 +OP4 E01EC2 0 +OP4 E01EC3 0 +OP4 E01EC4 0 +OP4 E01EC5 0 +OP4 E01EC6 0 +OP4 E01EC7 0 +OP4 E01EC8 0 +OP4 E01EC9 0 +OP4 E01ECA 0 +OP4 E01ECB 0 +OP4 E01ECC 0 +OP4 E01ECD 0 +OP4 E01ECE 0 +OP4 E01ECF 0 +OP4 E01ED0 0 +OP4 E01ED1 0 +OP4 E01ED2 0 +OP4 E01ED3 0 +OP4 E01ED4 0 +OP4 E01ED5 0 +OP4 E01ED6 0 +OP4 E01ED7 0 +OP4 E01ED8 0 +OP4 E01ED9 0 +OP4 E01EDA 0 +OP4 E01EDB 0 +OP4 E01EDC 0 +OP4 E01EDD 0 +OP4 E01EDE 0 +OP4 E01EDF 0 +OP4 E01EE0 0 +OP4 E01EE1 0 +OP4 E01EE2 0 +OP4 E01EE3 0 +OP4 E01EE4 0 +OP4 E01EE5 0 +OP4 E01EE6 0 +OP4 E01EE7 0 +OP4 E01EE8 0 +OP4 E01EE9 0 +OP4 E01EEA 0 +OP4 E01EEB 0 +OP4 E01EEC 0 +OP4 E01EED 0 +OP4 E01EEE 0 +OP4 E01EEF 0 +OP4 E01EF0 0 +OP4 E01EF1 0 +OP4 E01EF2 0 +OP4 E01EF3 0 +OP4 E01EF4 0 +OP4 E01EF5 0 +OP4 E01EF6 0 +OP4 E01EF7 0 +OP4 E01EF8 0 +OP4 E01EF9 0 +OP4 E01EFA 0 +OP4 E01EFB 0 +OP4 E01EFC 0 +OP4 E01EFD 0 +OP4 E01EFE 0 +OP4 E01EFF 0 +OP4 E01F00 0 +OP4 E01F01 0 +OP4 E01F02 0 +OP4 E01F03 0 +OP4 E01F04 0 +OP4 E01F05 0 +OP4 E01F06 0 +OP4 E01F07 0 +OP4 E01F08 0 +OP4 E01F09 0 +OP4 E01F0A 0 +OP4 E01F0B 0 +OP4 E01F0C 0 +OP4 E01F0D 0 +OP4 E01F0E 0 +OP4 E01F0F 0 +OP4 E01F10 0 +OP4 E01F11 0 +OP4 E01F12 0 +OP4 E01F13 0 +OP4 E01F14 0 +OP4 E01F15 0 +OP4 E01F16 0 +OP4 E01F17 0 +OP4 E01F18 0 +OP4 E01F19 0 +OP4 E01F1A 0 +OP4 E01F1B 0 +OP4 E01F1C 0 +OP4 E01F1D 0 +OP4 E01F1E 0 +OP4 E01F1F 0 +OP4 E01F20 0 +OP4 E01F21 0 +OP4 E01F22 0 +OP4 E01F23 0 +OP4 E01F24 0 +OP4 E01F25 0 +OP4 E01F26 0 +OP4 E01F27 0 +OP4 E01F28 0 +OP4 E01F29 0 +OP4 E01F2A 0 +OP4 E01F2B 0 +OP4 E01F2C 0 +OP4 E01F2D 0 +OP4 E01F2E 0 +OP4 E01F2F 0 +OP4 E01F30 0 +OP4 E01F31 0 +OP4 E01F32 0 +OP4 E01F33 0 +OP4 E01F34 0 +OP4 E01F35 0 +OP4 E01F36 0 +OP4 E01F37 0 +OP4 E01F38 0 +OP4 E01F39 0 +OP4 E01F3A 0 +OP4 E01F3B 0 +OP4 E01F3C 0 +OP4 E01F3D 0 +OP4 E01F3E 0 +OP4 E01F3F 0 +OP4 E01F40 0 +OP4 E01F41 0 +OP4 E01F42 0 +OP4 E01F43 0 +OP4 E01F44 0 +OP4 E01F45 0 +OP4 E01F46 0 +OP4 E01F47 0 +OP4 E01F48 0 +OP4 E01F49 0 +OP4 E01F4A 0 +OP4 E01F4B 0 +OP4 E01F4C 0 +OP4 E01F4D 0 +OP4 E01F4E 0 +OP4 E01F4F 0 +OP4 E01F50 0 +OP4 E01F51 0 +OP4 E01F52 0 +OP4 E01F53 0 +OP4 E01F54 0 +OP4 E01F55 0 +OP4 E01F56 0 +OP4 E01F57 0 +OP4 E01F58 0 +OP4 E01F59 0 +OP4 E01F5A 0 +OP4 E01F5B 0 +OP4 E01F5C 0 +OP4 E01F5D 0 +OP4 E01F5E 0 +OP4 E01F5F 0 +OP4 E01F60 0 +OP4 E01F61 0 +OP4 E01F62 0 +OP4 E01F63 0 +OP4 E01F64 0 +OP4 E01F65 0 +OP4 E01F66 0 +OP4 E01F67 0 +OP4 E01F68 0 +OP4 E01F69 0 +OP4 E01F6A 0 +OP4 E01F6B 0 +OP4 E01F6C 0 +OP4 E01F6D 0 +OP4 E01F6E 0 +OP4 E01F6F 0 +OP4 E01F70 0 +OP4 E01F71 0 +OP4 E01F72 0 +OP4 E01F73 0 +OP4 E01F74 0 +OP4 E01F75 0 +OP4 E01F76 0 +OP4 E01F77 0 +OP4 E01F78 0 +OP4 E01F79 0 +OP4 E01F7A 0 +OP4 E01F7B 0 +OP4 E01F7C 0 +OP4 E01F7D 0 +OP4 E01F7E 0 +OP4 E01F7F 0 +OP4 E01F80 0 +OP4 E01F81 0 +OP4 E01F82 0 +OP4 E01F83 0 +OP4 E01F84 0 +OP4 E01F85 0 +OP4 E01F86 0 +OP4 E01F87 0 +OP4 E01F88 0 +OP4 E01F89 0 +OP4 E01F8A 0 +OP4 E01F8B 0 +OP4 E01F8C 0 +OP4 E01F8D 0 +OP4 E01F8E 0 +OP4 E01F8F 0 +OP4 E01F90 0 +OP4 E01F91 0 +OP4 E01F92 0 +OP4 E01F93 0 +OP4 E01F94 0 +OP4 E01F95 0 +OP4 E01F96 0 +OP4 E01F97 0 +OP4 E01F98 0 +OP4 E01F99 0 +OP4 E01F9A 0 +OP4 E01F9B 0 +OP4 E01F9C 0 +OP4 E01F9D 0 +OP4 E01F9E 0 +OP4 E01F9F 0 +OP4 E01FA0 0 +OP4 E01FA1 0 +OP4 E01FA2 0 +OP4 E01FA3 0 +OP4 E01FA4 0 +OP4 E01FA5 0 +OP4 E01FA6 0 +OP4 E01FA7 0 +OP4 E01FA8 0 +OP4 E01FA9 0 +OP4 E01FAA 0 +OP4 E01FAB 0 +OP4 E01FAC 0 +OP4 E01FAD 0 +OP4 E01FAE 0 +OP4 E01FAF 0 +OP4 E01FB0 0 +OP4 E01FB1 0 +OP4 E01FB2 0 +OP4 E01FB3 0 +OP4 E01FB4 0 +OP4 E01FB5 0 +OP4 E01FB6 0 +OP4 E01FB7 0 +OP4 E01FB8 0 +OP4 E01FB9 0 +OP4 E01FBA 0 +OP4 E01FBB 0 +OP4 E01FBC 0 +OP4 E01FBD 0 +OP4 E01FBE 0 +OP4 E01FBF 0 +OP4 E01FC0 0 +OP4 E01FC1 0 +OP4 E01FC2 0 +OP4 E01FC3 0 +OP4 E01FC4 0 +OP4 E01FC5 0 +OP4 E01FC6 0 +OP4 E01FC7 0 +OP4 E01FC8 0 +OP4 E01FC9 0 +OP4 E01FCA 0 +OP4 E01FCB 0 +OP4 E01FCC 0 +OP4 E01FCD 0 +OP4 E01FCE 0 +OP4 E01FCF 0 +OP4 E01FD0 0 +OP4 E01FD1 0 +OP4 E01FD2 0 +OP4 E01FD3 0 +OP4 E01FD4 0 +OP4 E01FD5 0 +OP4 E01FD6 0 +OP4 E01FD7 0 +OP4 E01FD8 0 +OP4 E01FD9 0 +OP4 E01FDA 0 +OP4 E01FDB 0 +OP4 E01FDC 0 +OP4 E01FDD 0 +OP4 E01FDE 0 +OP4 E01FDF 0 +OP4 E01FE0 0 +OP4 E01FE1 0 +OP4 E01FE2 0 +OP4 E01FE3 0 +OP4 E01FE4 0 +OP4 E01FE5 0 +OP4 E01FE6 0 +OP4 E01FE7 0 +OP4 E01FE8 0 +OP4 E01FE9 0 +OP4 E01FEA 0 +OP4 E01FEB 0 +OP4 E01FEC 0 +OP4 E01FED 0 +OP4 E01FEE 0 +OP4 E01FEF 0 +OP4 E01FF0 0 +OP4 E01FF1 0 +OP4 E01FF2 0 +OP4 E01FF3 0 +OP4 E01FF4 0 +OP4 E01FF5 0 +OP4 E01FF6 0 +OP4 E01FF7 0 +OP4 E01FF8 0 +OP4 E01FF9 0 +OP4 E01FFA 0 +OP4 E01FFB 0 +OP4 E01FFC 0 +OP4 E01FFD 0 +OP4 E01FFE 0 +OP4 E01FFF 0 +OP4 E02000 0 +OP4 E02001 0 +OP4 E02002 0 +OP4 E02003 0 +OP4 E02004 0 +OP4 E02005 0 +OP4 E02006 0 +OP4 E02007 0 +OP4 E02008 0 +OP4 E02009 0 +OP4 E0200A 0 +OP4 E0200B 0 +OP4 E0200C 0 +OP4 E0200D 0 +OP4 E0200E 0 +OP4 E0200F 0 +OP4 E02010 0 +OP4 E02011 0 +OP4 E02012 0 +OP4 E02013 0 +OP4 E02014 0 +OP4 E02015 0 +OP4 E02016 0 +OP4 E02017 0 +OP4 E02018 0 +OP4 E02019 0 +OP4 E0201A 0 +OP4 E0201B 0 +OP4 E0201C 0 +OP4 E0201D 0 +OP4 E0201E 0 +OP4 E0201F 0 +OP4 E02020 0 +OP4 E02021 0 +OP4 E02022 0 +OP4 E02023 0 +OP4 E02024 0 +OP4 E02025 0 +OP4 E02026 0 +OP4 E02027 0 +OP4 E02028 0 +OP4 E02029 0 +OP4 E0202A 0 +OP4 E0202B 0 +OP4 E0202C 0 +OP4 E0202D 0 +OP4 E0202E 0 +OP4 E0202F 0 +OP4 E02030 0 +OP4 E02031 0 +OP4 E02032 0 +OP4 E02033 0 +OP4 E02034 0 +OP4 E02035 0 +OP4 E02036 0 +OP4 E02037 0 +OP4 E02038 0 +OP4 E02039 0 +OP4 E0203A 0 +OP4 E0203B 0 +OP4 E0203C 0 +OP4 E0203D 0 +OP4 E0203E 0 +OP4 E0203F 0 +OP4 E02040 0 +OP4 E02041 0 +OP4 E02042 0 +OP4 E02043 0 +OP4 E02044 0 +OP4 E02045 0 +OP4 E02046 0 +OP4 E02047 0 +OP4 E02048 0 +OP4 E02049 0 +OP4 E0204A 0 +OP4 E0204B 0 +OP4 E0204C 0 +OP4 E0204D 0 +OP4 E0204E 0 +OP4 E0204F 0 +OP4 E02050 0 +OP4 E02051 0 +OP4 E02052 0 +OP4 E02053 0 +OP4 E02054 0 +OP4 E02055 0 +OP4 E02056 0 +OP4 E02057 0 +OP4 E02058 0 +OP4 E02059 0 +OP4 E0205A 0 +OP4 E0205B 0 +OP4 E0205C 0 +OP4 E0205D 0 +OP4 E0205E 0 +OP4 E0205F 0 +OP4 E02060 0 +OP4 E02061 0 +OP4 E02062 0 +OP4 E02063 0 +OP4 E02064 0 +OP4 E02065 0 +OP4 E02066 0 +OP4 E02067 0 +OP4 E02068 0 +OP4 E02069 0 +OP4 E0206A 0 +OP4 E0206B 0 +OP4 E0206C 0 +OP4 E0206D 0 +OP4 E0206E 0 +OP4 E0206F 0 +OP4 E02070 0 +OP4 E02071 0 +OP4 E02072 0 +OP4 E02073 0 +OP4 E02074 0 +OP4 E02075 0 +OP4 E02076 0 +OP4 E02077 0 +OP4 E02078 0 +OP4 E02079 0 +OP4 E0207A 0 +OP4 E0207B 0 +OP4 E0207C 0 +OP4 E0207D 0 +OP4 E0207E 0 +OP4 E0207F 0 +OP4 E02080 0 +OP4 E02081 0 +OP4 E02082 0 +OP4 E02083 0 +OP4 E02084 0 +OP4 E02085 0 +OP4 E02086 0 +OP4 E02087 0 +OP4 E02088 0 +OP4 E02089 0 +OP4 E0208A 0 +OP4 E0208B 0 +OP4 E0208C 0 +OP4 E0208D 0 +OP4 E0208E 0 +OP4 E0208F 0 +OP4 E02090 0 +OP4 E02091 0 +OP4 E02092 0 +OP4 E02093 0 +OP4 E02094 0 +OP4 E02095 0 +OP4 E02096 0 +OP4 E02097 0 +OP4 E02098 0 +OP4 E02099 0 +OP4 E0209A 0 +OP4 E0209B 0 +OP4 E0209C 0 +OP4 E0209D 0 +OP4 E0209E 0 +OP4 E0209F 0 +OP4 E020A0 0 +OP4 E020A1 0 +OP4 E020A2 0 +OP4 E020A3 0 +OP4 E020A4 0 +OP4 E020A5 0 +OP4 E020A6 0 +OP4 E020A7 0 +OP4 E020A8 0 +OP4 E020A9 0 +OP4 E020AA 0 +OP4 E020AB 0 +OP4 E020AC 0 +OP4 E020AD 0 +OP4 E020AE 0 +OP4 E020AF 0 +OP4 E020B0 0 +OP4 E020B1 0 +OP4 E020B2 0 +OP4 E020B3 0 +OP4 E020B4 0 +OP4 E020B5 0 +OP4 E020B6 0 +OP4 E020B7 0 +OP4 E020B8 0 +OP4 E020B9 0 +OP4 E020BA 0 +OP4 E020BB 0 +OP4 E020BC 0 +OP4 E020BD 0 +OP4 E020BE 0 +OP4 E020BF 0 +OP4 E020C0 0 +OP4 E020C1 0 +OP4 E020C2 0 +OP4 E020C3 0 +OP4 E020C4 0 +OP4 E020C5 0 +OP4 E020C6 0 +OP4 E020C7 0 +OP4 E020C8 0 +OP4 E020C9 0 +OP4 E020CA 0 +OP4 E020CB 0 +OP4 E020CC 0 +OP4 E020CD 0 +OP4 E020CE 0 +OP4 E020CF 0 +OP4 E020D0 0 +OP4 E020D1 0 +OP4 E020D2 0 +OP4 E020D3 0 +OP4 E020D4 0 +OP4 E020D5 0 +OP4 E020D6 0 +OP4 E020D7 0 +OP4 E020D8 0 +OP4 E020D9 0 +OP4 E020DA 0 +OP4 E020DB 0 +OP4 E020DC 0 +OP4 E020DD 0 +OP4 E020DE 0 +OP4 E020DF 0 +OP4 E020E0 0 +OP4 E020E1 0 +OP4 E020E2 0 +OP4 E020E3 0 +OP4 E020E4 0 +OP4 E020E5 0 +OP4 E020E6 0 +OP4 E020E7 0 +OP4 E020E8 0 +OP4 E020E9 0 +OP4 E020EA 0 +OP4 E020EB 0 +OP4 E020EC 0 +OP4 E020ED 0 +OP4 E020EE 0 +OP4 E020EF 0 +OP4 E020F0 0 +OP4 E020F1 0 +OP4 E020F2 0 +OP4 E020F3 0 +OP4 E020F4 0 +OP4 E020F5 0 +OP4 E020F6 0 +OP4 E020F7 0 +OP4 E020F8 0 +OP4 E020F9 0 +OP4 E020FA 0 +OP4 E020FB 0 +OP4 E020FC 0 +OP4 E020FD 0 +OP4 E020FE 0 +OP4 E020FF 0 +OP4 E02100 0 +OP4 E02101 0 +OP4 E02102 0 +OP4 E02103 0 +OP4 E02104 0 +OP4 E02105 0 +OP4 E02106 0 +OP4 E02107 0 +OP4 E02108 0 +OP4 E02109 0 +OP4 E0210A 0 +OP4 E0210B 0 +OP4 E0210C 0 +OP4 E0210D 0 +OP4 E0210E 0 +OP4 E0210F 0 +OP4 E02110 0 +OP4 E02111 0 +OP4 E02112 0 +OP4 E02113 0 +OP4 E02114 0 +OP4 E02115 0 +OP4 E02116 0 +OP4 E02117 0 +OP4 E02118 0 +OP4 E02119 0 +OP4 E0211A 0 +OP4 E0211B 0 +OP4 E0211C 0 +OP4 E0211D 0 +OP4 E0211E 0 +OP4 E0211F 0 +OP4 E02120 0 +OP4 E02121 0 +OP4 E02122 0 +OP4 E02123 0 +OP4 E02124 0 +OP4 E02125 0 +OP4 E02126 0 +OP4 E02127 0 +OP4 E02128 0 +OP4 E02129 0 +OP4 E0212A 0 +OP4 E0212B 0 +OP4 E0212C 0 +OP4 E0212D 0 +OP4 E0212E 0 +OP4 E0212F 0 +OP4 E02130 0 +OP4 E02131 0 +OP4 E02132 0 +OP4 E02133 0 +OP4 E02134 0 +OP4 E02135 0 +OP4 E02136 0 +OP4 E02137 0 +OP4 E02138 0 +OP4 E02139 0 +OP4 E0213A 0 +OP4 E0213B 0 +OP4 E0213C 0 +OP4 E0213D 0 +OP4 E0213E 0 +OP4 E0213F 0 +OP4 E02140 0 +OP4 E02141 0 +OP4 E02142 0 +OP4 E02143 0 +OP4 E02144 0 +OP4 E02145 0 +OP4 E02146 0 +OP4 E02147 0 +OP4 E02148 0 +OP4 E02149 0 +OP4 E0214A 0 +OP4 E0214B 0 +OP4 E0214C 0 +OP4 E0214D 0 +OP4 E0214E 0 +OP4 E0214F 0 +OP4 E02150 0 +OP4 E02151 0 +OP4 E02152 0 +OP4 E02153 0 +OP4 E02154 0 +OP4 E02155 0 +OP4 E02156 0 +OP4 E02157 0 +OP4 E02158 0 +OP4 E02159 0 +OP4 E0215A 0 +OP4 E0215B 0 +OP4 E0215C 0 +OP4 E0215D 0 +OP4 E0215E 0 +OP4 E0215F 0 +OP4 E02160 0 +OP4 E02161 0 +OP4 E02162 0 +OP4 E02163 0 +OP4 E02164 0 +OP4 E02165 0 +OP4 E02166 0 +OP4 E02167 0 +OP4 E02168 0 +OP4 E02169 0 +OP4 E0216A 0 +OP4 E0216B 0 +OP4 E0216C 0 +OP4 E0216D 0 +OP4 E0216E 0 +OP4 E0216F 0 +OP4 E02170 0 +OP4 E02171 0 +OP4 E02172 0 +OP4 E02173 0 +OP4 E02174 0 +OP4 E02175 0 +OP4 E02176 0 +OP4 E02177 0 +OP4 E02178 0 +OP4 E02179 0 +OP4 E0217A 0 +OP4 E0217B 0 +OP4 E0217C 0 +OP4 E0217D 0 +OP4 E0217E 0 +OP4 E0217F 0 +OP4 E02180 0 +OP4 E02181 0 +OP4 E02182 0 +OP4 E02183 0 +OP4 E02184 0 +OP4 E02185 0 +OP4 E02186 0 +OP4 E02187 0 +OP4 E02188 0 +OP4 E02189 0 +OP4 E0218A 0 +OP4 E0218B 0 +OP4 E0218C 0 +OP4 E0218D 0 +OP4 E0218E 0 +OP4 E0218F 0 +OP4 E02190 0 +OP4 E02191 0 +OP4 E02192 0 +OP4 E02193 0 +OP4 E02194 0 +OP4 E02195 0 +OP4 E02196 0 +OP4 E02197 0 +OP4 E02198 0 +OP4 E02199 0 +OP4 E0219A 0 +OP4 E0219B 0 +OP4 E0219C 0 +OP4 E0219D 0 +OP4 E0219E 0 +OP4 E0219F 0 +OP4 E021A0 0 +OP4 E021A1 0 +OP4 E021A2 0 +OP4 E021A3 0 +OP4 E021A4 0 +OP4 E021A5 0 +OP4 E021A6 0 +OP4 E021A7 0 +OP4 E021A8 0 +OP4 E021A9 0 +OP4 E021AA 0 +OP4 E021AB 0 +OP4 E021AC 0 +OP4 E021AD 0 +OP4 E021AE 0 +OP4 E021AF 0 +OP4 E021B0 0 +OP4 E021B1 0 +OP4 E021B2 0 +OP4 E021B3 0 +OP4 E021B4 0 +OP4 E021B5 0 +OP4 E021B6 0 +OP4 E021B7 0 +OP4 E021B8 0 +OP4 E021B9 0 +OP4 E021BA 0 +OP4 E021BB 0 +OP4 E021BC 0 +OP4 E021BD 0 +OP4 E021BE 0 +OP4 E021BF 0 +OP4 E021C0 0 +OP4 E021C1 0 +OP4 E021C2 0 +OP4 E021C3 0 +OP4 E021C4 0 +OP4 E021C5 0 +OP4 E021C6 0 +OP4 E021C7 0 +OP4 E021C8 0 +OP4 E021C9 0 +OP4 E021CA 0 +OP4 E021CB 0 +OP4 E021CC 0 +OP4 E021CD 0 +OP4 E021CE 0 +OP4 E021CF 0 +OP4 E021D0 0 +OP4 E021D1 0 +OP4 E021D2 0 +OP4 E021D3 0 +OP4 E021D4 0 +OP4 E021D5 0 +OP4 E021D6 0 +OP4 E021D7 0 +OP4 E021D8 0 +OP4 E021D9 0 +OP4 E021DA 0 +OP4 E021DB 0 +OP4 E021DC 0 +OP4 E021DD 0 +OP4 E021DE 0 +OP4 E021DF 0 +OP4 E021E0 0 +OP4 E021E1 0 +OP4 E021E2 0 +OP4 E021E3 0 +OP4 E021E4 0 +OP4 E021E5 0 +OP4 E021E6 0 +OP4 E021E7 0 +OP4 E021E8 0 +OP4 E021E9 0 +OP4 E021EA 0 +OP4 E021EB 0 +OP4 E021EC 0 +OP4 E021ED 0 +OP4 E021EE 0 +OP4 E021EF 0 +OP4 E021F0 0 +OP4 E021F1 0 +OP4 E021F2 0 +OP4 E021F3 0 +OP4 E021F4 0 +OP4 E021F5 0 +OP4 E021F6 0 +OP4 E021F7 0 +OP4 E021F8 0 +OP4 E021F9 0 +OP4 E021FA 0 +OP4 E021FB 0 +OP4 E021FC 0 +OP4 E021FD 0 +OP4 E021FE 0 +OP4 E021FF 0 +OP4 E02200 0 +OP4 E02201 0 +OP4 E02202 0 +OP4 E02203 0 +OP4 E02204 0 +OP4 E02205 0 +OP4 E02206 0 +OP4 E02207 0 +OP4 E02208 0 +OP4 E02209 0 +OP4 E0220A 0 +OP4 E0220B 0 +OP4 E0220C 0 +OP4 E0220D 0 +OP4 E0220E 0 +OP4 E0220F 0 +OP4 E02210 0 +OP4 E02211 0 +OP4 E02212 0 +OP4 E02213 0 +OP4 E02214 0 +OP4 E02215 0 +OP4 E02216 0 +OP4 E02217 0 +OP4 E02218 0 +OP4 E02219 0 +OP4 E0221A 0 +OP4 E0221B 0 +OP4 E0221C 0 +OP4 E0221D 0 +OP4 E0221E 0 +OP4 E0221F 0 +OP4 E02220 0 +OP4 E02221 0 +OP4 E02222 0 +OP4 E02223 0 +OP4 E02224 0 +OP4 E02225 0 +OP4 E02226 0 +OP4 E02227 0 +OP4 E02228 0 +OP4 E02229 0 +OP4 E0222A 0 +OP4 E0222B 0 +OP4 E0222C 0 +OP4 E0222D 0 +OP4 E0222E 0 +OP4 E0222F 0 +OP4 E02230 0 +OP4 E02231 0 +OP4 E02232 0 +OP4 E02233 0 +OP4 E02234 0 +OP4 E02235 0 +OP4 E02236 0 +OP4 E02237 0 +OP4 E02238 0 +OP4 E02239 0 +OP4 E0223A 0 +OP4 E0223B 0 +OP4 E0223C 0 +OP4 E0223D 0 +OP4 E0223E 0 +OP4 E0223F 0 +OP4 E02240 0 +OP4 E02241 0 +OP4 E02242 0 +OP4 E02243 0 +OP4 E02244 0 +OP4 E02245 0 +OP4 E02246 0 +OP4 E02247 0 +OP4 E02248 0 +OP4 E02249 0 +OP4 E0224A 0 +OP4 E0224B 0 +OP4 E0224C 0 +OP4 E0224D 0 +OP4 E0224E 0 +OP4 E0224F 0 +OP4 E02250 0 +OP4 E02251 0 +OP4 E02252 0 +OP4 E02253 0 +OP4 E02254 0 +OP4 E02255 0 +OP4 E02256 0 +OP4 E02257 0 +OP4 E02258 0 +OP4 E02259 0 +OP4 E0225A 0 +OP4 E0225B 0 +OP4 E0225C 0 +OP4 E0225D 0 +OP4 E0225E 0 +OP4 E0225F 0 +OP4 E02260 0 +OP4 E02261 0 +OP4 E02262 0 +OP4 E02263 0 +OP4 E02264 0 +OP4 E02265 0 +OP4 E02266 0 +OP4 E02267 0 +OP4 E02268 0 +OP4 E02269 0 +OP4 E0226A 0 +OP4 E0226B 0 +OP4 E0226C 0 +OP4 E0226D 0 +OP4 E0226E 0 +OP4 E0226F 0 +OP4 E02270 0 +OP4 E02271 0 +OP4 E02272 0 +OP4 E02273 0 +OP4 E02274 0 +OP4 E02275 0 +OP4 E02276 0 +OP4 E02277 0 +OP4 E02278 0 +OP4 E02279 0 +OP4 E0227A 0 +OP4 E0227B 0 +OP4 E0227C 0 +OP4 E0227D 0 +OP4 E0227E 0 +OP4 E0227F 0 +OP4 E02280 0 +OP4 E02281 0 +OP4 E02282 0 +OP4 E02283 0 +OP4 E02284 0 +OP4 E02285 0 +OP4 E02286 0 +OP4 E02287 0 +OP4 E02288 0 +OP4 E02289 0 +OP4 E0228A 0 +OP4 E0228B 0 +OP4 E0228C 0 +OP4 E0228D 0 +OP4 E0228E 0 +OP4 E0228F 0 +OP4 E02290 0 +OP4 E02291 0 +OP4 E02292 0 +OP4 E02293 0 +OP4 E02294 0 +OP4 E02295 0 +OP4 E02296 0 +OP4 E02297 0 +OP4 E02298 0 +OP4 E02299 0 +OP4 E0229A 0 +OP4 E0229B 0 +OP4 E0229C 0 +OP4 E0229D 0 +OP4 E0229E 0 +OP4 E0229F 0 +OP4 E022A0 0 +OP4 E022A1 0 +OP4 E022A2 0 +OP4 E022A3 0 +OP4 E022A4 0 +OP4 E022A5 0 +OP4 E022A6 0 +OP4 E022A7 0 +OP4 E022A8 0 +OP4 E022A9 0 +OP4 E022AA 0 +OP4 E022AB 0 +OP4 E022AC 0 +OP4 E022AD 0 +OP4 E022AE 0 +OP4 E022AF 0 +OP4 E022B0 0 +OP4 E022B1 0 +OP4 E022B2 0 +OP4 E022B3 0 +OP4 E022B4 0 +OP4 E022B5 0 +OP4 E022B6 0 +OP4 E022B7 0 +OP4 E022B8 0 +OP4 E022B9 0 +OP4 E022BA 0 +OP4 E022BB 0 +OP4 E022BC 0 +OP4 E022BD 0 +OP4 E022BE 0 +OP4 E022BF 0 +OP4 E022C0 0 +OP4 E022C1 0 +OP4 E022C2 0 +OP4 E022C3 0 +OP4 E022C4 0 +OP4 E022C5 0 +OP4 E022C6 0 +OP4 E022C7 0 +OP4 E022C8 0 +OP4 E022C9 0 +OP4 E022CA 0 +OP4 E022CB 0 +OP4 E022CC 0 +OP4 E022CD 0 +OP4 E022CE 0 +OP4 E022CF 0 +OP4 E022D0 0 +OP4 E022D1 0 +OP4 E022D2 0 +OP4 E022D3 0 +OP4 E022D4 0 +OP4 E022D5 0 +OP4 E022D6 0 +OP4 E022D7 0 +OP4 E022D8 0 +OP4 E022D9 0 +OP4 E022DA 0 +OP4 E022DB 0 +OP4 E022DC 0 +OP4 E022DD 0 +OP4 E022DE 0 +OP4 E022DF 0 +OP4 E022E0 0 +OP4 E022E1 0 +OP4 E022E2 0 +OP4 E022E3 0 +OP4 E022E4 0 +OP4 E022E5 0 +OP4 E022E6 0 +OP4 E022E7 0 +OP4 E022E8 0 +OP4 E022E9 0 +OP4 E022EA 0 +OP4 E022EB 0 +OP4 E022EC 0 +OP4 E022ED 0 +OP4 E022EE 0 +OP4 E022EF 0 +OP4 E022F0 0 +OP4 E022F1 0 +OP4 E022F2 0 +OP4 E022F3 0 +OP4 E022F4 0 +OP4 E022F5 0 +OP4 E022F6 0 +OP4 E022F7 0 +OP4 E022F8 0 +OP4 E022F9 0 +OP4 E022FA 0 +OP4 E022FB 0 +OP4 E022FC 0 +OP4 E022FD 0 +OP4 E022FE 0 +OP4 E022FF 0 +OP4 E02300 0 +OP4 E02301 0 +OP4 E02302 0 +OP4 E02303 0 +OP4 E02304 0 +OP4 E02305 0 +OP4 E02306 0 +OP4 E02307 0 +OP4 E02308 0 +OP4 E02309 0 +OP4 E0230A 0 +OP4 E0230B 0 +OP4 E0230C 0 +OP4 E0230D 0 +OP4 E0230E 0 +OP4 E0230F 0 +OP4 E02310 0 +OP4 E02311 0 +OP4 E02312 0 +OP4 E02313 0 +OP4 E02314 0 +OP4 E02315 0 +OP4 E02316 0 +OP4 E02317 0 +OP4 E02318 0 +OP4 E02319 0 +OP4 E0231A 0 +OP4 E0231B 0 +OP4 E0231C 0 +OP4 E0231D 0 +OP4 E0231E 0 +OP4 E0231F 0 +OP4 E02320 0 +OP4 E02321 0 +OP4 E02322 0 +OP4 E02323 0 +OP4 E02324 0 +OP4 E02325 0 +OP4 E02326 0 +OP4 E02327 0 +OP4 E02328 0 +OP4 E02329 0 +OP4 E0232A 0 +OP4 E0232B 0 +OP4 E0232C 0 +OP4 E0232D 0 +OP4 E0232E 0 +OP4 E0232F 0 +OP4 E02330 0 +OP4 E02331 0 +OP4 E02332 0 +OP4 E02333 0 +OP4 E02334 0 +OP4 E02335 0 +OP4 E02336 0 +OP4 E02337 0 +OP4 E02338 0 +OP4 E02339 0 +OP4 E0233A 0 +OP4 E0233B 0 +OP4 E0233C 0 +OP4 E0233D 0 +OP4 E0233E 0 +OP4 E0233F 0 +OP4 E02340 0 +OP4 E02341 0 +OP4 E02342 0 +OP4 E02343 0 +OP4 E02344 0 +OP4 E02345 0 +OP4 E02346 0 +OP4 E02347 0 +OP4 E02348 0 +OP4 E02349 0 +OP4 E0234A 0 +OP4 E0234B 0 +OP4 E0234C 0 +OP4 E0234D 0 +OP4 E0234E 0 +OP4 E0234F 0 +OP4 E02350 0 +OP4 E02351 0 +OP4 E02352 0 +OP4 E02353 0 +OP4 E02354 0 +OP4 E02355 0 +OP4 E02356 0 +OP4 E02357 0 +OP4 E02358 0 +OP4 E02359 0 +OP4 E0235A 0 +OP4 E0235B 0 +OP4 E0235C 0 +OP4 E0235D 0 +OP4 E0235E 0 +OP4 E0235F 0 +OP4 E02360 0 +OP4 E02361 0 +OP4 E02362 0 +OP4 E02363 0 +OP4 E02364 0 +OP4 E02365 0 +OP4 E02366 0 +OP4 E02367 0 +OP4 E02368 0 +OP4 E02369 0 +OP4 E0236A 0 +OP4 E0236B 0 +OP4 E0236C 0 +OP4 E0236D 0 +OP4 E0236E 0 +OP4 E0236F 0 +OP4 E02370 0 +OP4 E02371 0 +OP4 E02372 0 +OP4 E02373 0 +OP4 E02374 0 +OP4 E02375 0 +OP4 E02376 0 +OP4 E02377 0 +OP4 E02378 0 +OP4 E02379 0 +OP4 E0237A 0 +OP4 E0237B 0 +OP4 E0237C 0 +OP4 E0237D 0 +OP4 E0237E 0 +OP4 E0237F 0 +OP4 E02380 0 +OP4 E02381 0 +OP4 E02382 0 +OP4 E02383 0 +OP4 E02384 0 +OP4 E02385 0 +OP4 E02386 0 +OP4 E02387 0 +OP4 E02388 0 +OP4 E02389 0 +OP4 E0238A 0 +OP4 E0238B 0 +OP4 E0238C 0 +OP4 E0238D 0 +OP4 E0238E 0 +OP4 E0238F 0 +OP4 E02390 0 +OP4 E02391 0 +OP4 E02392 0 +OP4 E02393 0 +OP4 E02394 0 +OP4 E02395 0 +OP4 E02396 0 +OP4 E02397 0 +OP4 E02398 0 +OP4 E02399 0 +OP4 E0239A 0 +OP4 E0239B 0 +OP4 E0239C 0 +OP4 E0239D 0 +OP4 E0239E 0 +OP4 E0239F 0 +OP4 E023A0 0 +OP4 E023A1 0 +OP4 E023A2 0 +OP4 E023A3 0 +OP4 E023A4 0 +OP4 E023A5 0 +OP4 E023A6 0 +OP4 E023A7 0 +OP4 E023A8 0 +OP4 E023A9 0 +OP4 E023AA 0 +OP4 E023AB 0 +OP4 E023AC 0 +OP4 E023AD 0 +OP4 E023AE 0 +OP4 E023AF 0 +OP4 E023B0 0 +OP4 E023B1 0 +OP4 E023B2 0 +OP4 E023B3 0 +OP4 E023B4 0 +OP4 E023B5 0 +OP4 E023B6 0 +OP4 E023B7 0 +OP4 E023B8 0 +OP4 E023B9 0 +OP4 E023BA 0 +OP4 E023BB 0 +OP4 E023BC 0 +OP4 E023BD 0 +OP4 E023BE 0 +OP4 E023BF 0 +OP4 E023C0 0 +OP4 E023C1 0 +OP4 E023C2 0 +OP4 E023C3 0 +OP4 E023C4 0 +OP4 E023C5 0 +OP4 E023C6 0 +OP4 E023C7 0 +OP4 E023C8 0 +OP4 E023C9 0 +OP4 E023CA 0 +OP4 E023CB 0 +OP4 E023CC 0 +OP4 E023CD 0 +OP4 E023CE 0 +OP4 E023CF 0 +OP4 E023D0 0 +OP4 E023D1 0 +OP4 E023D2 0 +OP4 E023D3 0 +OP4 E023D4 0 +OP4 E023D5 0 +OP4 E023D6 0 +OP4 E023D7 0 +OP4 E023D8 0 +OP4 E023D9 0 +OP4 E023DA 0 +OP4 E023DB 0 +OP4 E023DC 0 +OP4 E023DD 0 +OP4 E023DE 0 +OP4 E023DF 0 +OP4 E023E0 0 +OP4 E023E1 0 +OP4 E023E2 0 +OP4 E023E3 0 +OP4 E023E4 0 +OP4 E023E5 0 +OP4 E023E6 0 +OP4 E023E7 0 +OP4 E023E8 0 +OP4 E023E9 0 +OP4 E023EA 0 +OP4 E023EB 0 +OP4 E023EC 0 +OP4 E023ED 0 +OP4 E023EE 0 +OP4 E023EF 0 +OP4 E023F0 0 +OP4 E023F1 0 +OP4 E023F2 0 +OP4 E023F3 0 +OP4 E023F4 0 +OP4 E023F5 0 +OP4 E023F6 0 +OP4 E023F7 0 +OP4 E023F8 0 +OP4 E023F9 0 +OP4 E023FA 0 +OP4 E023FB 0 +OP4 E023FC 0 +OP4 E023FD 0 +OP4 E023FE 0 +OP4 E023FF 0 +OP4 E02400 0 +OP4 E02401 0 +OP4 E02402 0 +OP4 E02403 0 +OP4 E02404 0 +OP4 E02405 0 +OP4 E02406 0 +OP4 E02407 0 +OP4 E02408 0 +OP4 E02409 0 +OP4 E0240A 0 +OP4 E0240B 0 +OP4 E0240C 0 +OP4 E0240D 0 +OP4 E0240E 0 +OP4 E0240F 0 +OP4 E02410 0 +OP4 E02411 0 +OP4 E02412 0 +OP4 E02413 0 +OP4 E02414 0 +OP4 E02415 0 +OP4 E02416 0 +OP4 E02417 0 +OP4 E02418 0 +OP4 E02419 0 +OP4 E0241A 0 +OP4 E0241B 0 +OP4 E0241C 0 +OP4 E0241D 0 +OP4 E0241E 0 +OP4 E0241F 0 +OP4 E02420 0 +OP4 E02421 0 +OP4 E02422 0 +OP4 E02423 0 +OP4 E02424 0 +OP4 E02425 0 +OP4 E02426 0 +OP4 E02427 0 +OP4 E02428 0 +OP4 E02429 0 +OP4 E0242A 0 +OP4 E0242B 0 +OP4 E0242C 0 +OP4 E0242D 0 +OP4 E0242E 0 +OP4 E0242F 0 +OP4 E02430 0 +OP4 E02431 0 +OP4 E02432 0 +OP4 E02433 0 +OP4 E02434 0 +OP4 E02435 0 +OP4 E02436 0 +OP4 E02437 0 +OP4 E02438 0 +OP4 E02439 0 +OP4 E0243A 0 +OP4 E0243B 0 +OP4 E0243C 0 +OP4 E0243D 0 +OP4 E0243E 0 +OP4 E0243F 0 +OP4 E02440 0 +OP4 E02441 0 +OP4 E02442 0 +OP4 E02443 0 +OP4 E02444 0 +OP4 E02445 0 +OP4 E02446 0 +OP4 E02447 0 +OP4 E02448 0 +OP4 E02449 0 +OP4 E0244A 0 +OP4 E0244B 0 +OP4 E0244C 0 +OP4 E0244D 0 +OP4 E0244E 0 +OP4 E0244F 0 +OP4 E02450 0 +OP4 E02451 0 +OP4 E02452 0 +OP4 E02453 0 +OP4 E02454 0 +OP4 E02455 0 +OP4 E02456 0 +OP4 E02457 0 +OP4 E02458 0 +OP4 E02459 0 +OP4 E0245A 0 +OP4 E0245B 0 +OP4 E0245C 0 +OP4 E0245D 0 +OP4 E0245E 0 +OP4 E0245F 0 +OP4 E02460 0 +OP4 E02461 0 +OP4 E02462 0 +OP4 E02463 0 +OP4 E02464 0 +OP4 E02465 0 +OP4 E02466 0 +OP4 E02467 0 +OP4 E02468 0 +OP4 E02469 0 +OP4 E0246A 0 +OP4 E0246B 0 +OP4 E0246C 0 +OP4 E0246D 0 +OP4 E0246E 0 +OP4 E0246F 0 +OP4 E02470 0 +OP4 E02471 0 +OP4 E02472 0 +OP4 E02473 0 +OP4 E02474 0 +OP4 E02475 0 +OP4 E02476 0 +OP4 E02477 0 +OP4 E02478 0 +OP4 E02479 0 +OP4 E0247A 0 +OP4 E0247B 0 +OP4 E0247C 0 +OP4 E0247D 0 +OP4 E0247E 0 +OP4 E0247F 0 +OP4 E02480 0 +OP4 E02481 0 +OP4 E02482 0 +OP4 E02483 0 +OP4 E02484 0 +OP4 E02485 0 +OP4 E02486 0 +OP4 E02487 0 +OP4 E02488 0 +OP4 E02489 0 +OP4 E0248A 0 +OP4 E0248B 0 +OP4 E0248C 0 +OP4 E0248D 0 +OP4 E0248E 0 +OP4 E0248F 0 +OP4 E02490 0 +OP4 E02491 0 +OP4 E02492 0 +OP4 E02493 0 +OP4 E02494 0 +OP4 E02495 0 +OP4 E02496 0 +OP4 E02497 0 +OP4 E02498 0 +OP4 E02499 0 +OP4 E0249A 0 +OP4 E0249B 0 +OP4 E0249C 0 +OP4 E0249D 0 +OP4 E0249E 0 +OP4 E0249F 0 +OP4 E024A0 0 +OP4 E024A1 0 +OP4 E024A2 0 +OP4 E024A3 0 +OP4 E024A4 0 +OP4 E024A5 0 +OP4 E024A6 0 +OP4 E024A7 0 +OP4 E024A8 0 +OP4 E024A9 0 +OP4 E024AA 0 +OP4 E024AB 0 +OP4 E024AC 0 +OP4 E024AD 0 +OP4 E024AE 0 +OP4 E024AF 0 +OP4 E024B0 0 +OP4 E024B1 0 +OP4 E024B2 0 +OP4 E024B3 0 +OP4 E024B4 0 +OP4 E024B5 0 +OP4 E024B6 0 +OP4 E024B7 0 +OP4 E024B8 0 +OP4 E024B9 0 +OP4 E024BA 0 +OP4 E024BB 0 +OP4 E024BC 0 +OP4 E024BD 0 +OP4 E024BE 0 +OP4 E024BF 0 +OP4 E024C0 0 +OP4 E024C1 0 +OP4 E024C2 0 +OP4 E024C3 0 +OP4 E024C4 0 +OP4 E024C5 0 +OP4 E024C6 0 +OP4 E024C7 0 +OP4 E024C8 0 +OP4 E024C9 0 +OP4 E024CA 0 +OP4 E024CB 0 +OP4 E024CC 0 +OP4 E024CD 0 +OP4 E024CE 0 +OP4 E024CF 0 +OP4 E024D0 0 +OP4 E024D1 0 +OP4 E024D2 0 +OP4 E024D3 0 +OP4 E024D4 0 +OP4 E024D5 0 +OP4 E024D6 0 +OP4 E024D7 0 +OP4 E024D8 0 +OP4 E024D9 0 +OP4 E024DA 0 +OP4 E024DB 0 +OP4 E024DC 0 +OP4 E024DD 0 +OP4 E024DE 0 +OP4 E024DF 0 +OP4 E024E0 0 +OP4 E024E1 0 +OP4 E024E2 0 +OP4 E024E3 0 +OP4 E024E4 0 +OP4 E024E5 0 +OP4 E024E6 0 +OP4 E024E7 0 +OP4 E024E8 0 +OP4 E024E9 0 +OP4 E024EA 0 +OP4 E024EB 0 +OP4 E024EC 0 +OP4 E024ED 0 +OP4 E024EE 0 +OP4 E024EF 0 +OP4 E024F0 0 +OP4 E024F1 0 +OP4 E024F2 0 +OP4 E024F3 0 +OP4 E024F4 0 +OP4 E024F5 0 +OP4 E024F6 0 +OP4 E024F7 0 +OP4 E024F8 0 +OP4 E024F9 0 +OP4 E024FA 0 +OP4 E024FB 0 +OP4 E024FC 0 +OP4 E024FD 0 +OP4 E024FE 0 +OP4 E024FF 0 +OP4 E02500 0 +OP4 E02501 0 +OP4 E02502 0 +OP4 E02503 0 +OP4 E02504 0 +OP4 E02505 0 +OP4 E02506 0 +OP4 E02507 0 +OP4 E02508 0 +OP4 E02509 0 +OP4 E0250A 0 +OP4 E0250B 0 +OP4 E0250C 0 +OP4 E0250D 0 +OP4 E0250E 0 +OP4 E0250F 0 +OP4 E02510 0 +OP4 E02511 0 +OP4 E02512 0 +OP4 E02513 0 +OP4 E02514 0 +OP4 E02515 0 +OP4 E02516 0 +OP4 E02517 0 +OP4 E02518 0 +OP4 E02519 0 +OP4 E0251A 0 +OP4 E0251B 0 +OP4 E0251C 0 +OP4 E0251D 0 +OP4 E0251E 0 +OP4 E0251F 0 +OP4 E02520 0 +OP4 E02521 0 +OP4 E02522 0 +OP4 E02523 0 +OP4 E02524 0 +OP4 E02525 0 +OP4 E02526 0 +OP4 E02527 0 +OP4 E02528 0 +OP4 E02529 0 +OP4 E0252A 0 +OP4 E0252B 0 +OP4 E0252C 0 +OP4 E0252D 0 +OP4 E0252E 0 +OP4 E0252F 0 +OP4 E02530 0 +OP4 E02531 0 +OP4 E02532 0 +OP4 E02533 0 +OP4 E02534 0 +OP4 E02535 0 +OP4 E02536 0 +OP4 E02537 0 +OP4 E02538 0 +OP4 E02539 0 +OP4 E0253A 0 +OP4 E0253B 0 +OP4 E0253C 0 +OP4 E0253D 0 +OP4 E0253E 0 +OP4 E0253F 0 +OP4 E02540 0 +OP4 E02541 0 +OP4 E02542 0 +OP4 E02543 0 +OP4 E02544 0 +OP4 E02545 0 +OP4 E02546 0 +OP4 E02547 0 +OP4 E02548 0 +OP4 E02549 0 +OP4 E0254A 0 +OP4 E0254B 0 +OP4 E0254C 0 +OP4 E0254D 0 +OP4 E0254E 0 +OP4 E0254F 0 +OP4 E02550 0 +OP4 E02551 0 +OP4 E02552 0 +OP4 E02553 0 +OP4 E02554 0 +OP4 E02555 0 +OP4 E02556 0 +OP4 E02557 0 +OP4 E02558 0 +OP4 E02559 0 +OP4 E0255A 0 +OP4 E0255B 0 +OP4 E0255C 0 +OP4 E0255D 0 +OP4 E0255E 0 +OP4 E0255F 0 +OP4 E02560 0 +OP4 E02561 0 +OP4 E02562 0 +OP4 E02563 0 +OP4 E02564 0 +OP4 E02565 0 +OP4 E02566 0 +OP4 E02567 0 +OP4 E02568 0 +OP4 E02569 0 +OP4 E0256A 0 +OP4 E0256B 0 +OP4 E0256C 0 +OP4 E0256D 0 +OP4 E0256E 0 +OP4 E0256F 0 +OP4 E02570 0 +OP4 E02571 0 +OP4 E02572 0 +OP4 E02573 0 +OP4 E02574 0 +OP4 E02575 0 +OP4 E02576 0 +OP4 E02577 0 +OP4 E02578 0 +OP4 E02579 0 +OP4 E0257A 0 +OP4 E0257B 0 +OP4 E0257C 0 +OP4 E0257D 0 +OP4 E0257E 0 +OP4 E0257F 0 +OP4 E02580 0 +OP4 E02581 0 +OP4 E02582 0 +OP4 E02583 0 +OP4 E02584 0 +OP4 E02585 0 +OP4 E02586 0 +OP4 E02587 0 +OP4 E02588 0 +OP4 E02589 0 +OP4 E0258A 0 +OP4 E0258B 0 +OP4 E0258C 0 +OP4 E0258D 0 +OP4 E0258E 0 +OP4 E0258F 0 +OP4 E02590 0 +OP4 E02591 0 +OP4 E02592 0 +OP4 E02593 0 +OP4 E02594 0 +OP4 E02595 0 +OP4 E02596 0 +OP4 E02597 0 +OP4 E02598 0 +OP4 E02599 0 +OP4 E0259A 0 +OP4 E0259B 0 +OP4 E0259C 0 +OP4 E0259D 0 +OP4 E0259E 0 +OP4 E0259F 0 +OP4 E025A0 0 +OP4 E025A1 0 +OP4 E025A2 0 +OP4 E025A3 0 +OP4 E025A4 0 +OP4 E025A5 0 +OP4 E025A6 0 +OP4 E025A7 0 +OP4 E025A8 0 +OP4 E025A9 0 +OP4 E025AA 0 +OP4 E025AB 0 +OP4 E025AC 0 +OP4 E025AD 0 +OP4 E025AE 0 +OP4 E025AF 0 +OP4 E025B0 0 +OP4 E025B1 0 +OP4 E025B2 0 +OP4 E025B3 0 +OP4 E025B4 0 +OP4 E025B5 0 +OP4 E025B6 0 +OP4 E025B7 0 +OP4 E025B8 0 +OP4 E025B9 0 +OP4 E025BA 0 +OP4 E025BB 0 +OP4 E025BC 0 +OP4 E025BD 0 +OP4 E025BE 0 +OP4 E025BF 0 +OP4 E025C0 0 +OP4 E025C1 0 +OP4 E025C2 0 +OP4 E025C3 0 +OP4 E025C4 0 +OP4 E025C5 0 +OP4 E025C6 0 +OP4 E025C7 0 +OP4 E025C8 0 +OP4 E025C9 0 +OP4 E025CA 0 +OP4 E025CB 0 +OP4 E025CC 0 +OP4 E025CD 0 +OP4 E025CE 0 +OP4 E025CF 0 +OP4 E025D0 0 +OP4 E025D1 0 +OP4 E025D2 0 +OP4 E025D3 0 +OP4 E025D4 0 +OP4 E025D5 0 +OP4 E025D6 0 +OP4 E025D7 0 +OP4 E025D8 0 +OP4 E025D9 0 +OP4 E025DA 0 +OP4 E025DB 0 +OP4 E025DC 0 +OP4 E025DD 0 +OP4 E025DE 0 +OP4 E025DF 0 +OP4 E025E0 0 +OP4 E025E1 0 +OP4 E025E2 0 +OP4 E025E3 0 +OP4 E025E4 0 +OP4 E025E5 0 +OP4 E025E6 0 +OP4 E025E7 0 +OP4 E025E8 0 +OP4 E025E9 0 +OP4 E025EA 0 +OP4 E025EB 0 +OP4 E025EC 0 +OP4 E025ED 0 +OP4 E025EE 0 +OP4 E025EF 0 +OP4 E025F0 0 +OP4 E025F1 0 +OP4 E025F2 0 +OP4 E025F3 0 +OP4 E025F4 0 +OP4 E025F5 0 +OP4 E025F6 0 +OP4 E025F7 0 +OP4 E025F8 0 +OP4 E025F9 0 +OP4 E025FA 0 +OP4 E025FB 0 +OP4 E025FC 0 +OP4 E025FD 0 +OP4 E025FE 0 +OP4 E025FF 0 +OP4 E02600 0 +OP4 E02601 0 +OP4 E02602 0 +OP4 E02603 0 +OP4 E02604 0 +OP4 E02605 0 +OP4 E02606 0 +OP4 E02607 0 +OP4 E02608 0 +OP4 E02609 0 +OP4 E0260A 0 +OP4 E0260B 0 +OP4 E0260C 0 +OP4 E0260D 0 +OP4 E0260E 0 +OP4 E0260F 0 +OP4 E02610 0 +OP4 E02611 0 +OP4 E02612 0 +OP4 E02613 0 +OP4 E02614 0 +OP4 E02615 0 +OP4 E02616 0 +OP4 E02617 0 +OP4 E02618 0 +OP4 E02619 0 +OP4 E0261A 0 +OP4 E0261B 0 +OP4 E0261C 0 +OP4 E0261D 0 +OP4 E0261E 0 +OP4 E0261F 0 +OP4 E02620 0 +OP4 E02621 0 +OP4 E02622 0 +OP4 E02623 0 +OP4 E02624 0 +OP4 E02625 0 +OP4 E02626 0 +OP4 E02627 0 +OP4 E02628 0 +OP4 E02629 0 +OP4 E0262A 0 +OP4 E0262B 0 +OP4 E0262C 0 +OP4 E0262D 0 +OP4 E0262E 0 +OP4 E0262F 0 +OP4 E02630 0 +OP4 E02631 0 +OP4 E02632 0 +OP4 E02633 0 +OP4 E02634 0 +OP4 E02635 0 +OP4 E02636 0 +OP4 E02637 0 +OP4 E02638 0 +OP4 E02639 0 +OP4 E0263A 0 +OP4 E0263B 0 +OP4 E0263C 0 +OP4 E0263D 0 +OP4 E0263E 0 +OP4 E0263F 0 +OP4 E02640 0 +OP4 E02641 0 +OP4 E02642 0 +OP4 E02643 0 +OP4 E02644 0 +OP4 E02645 0 +OP4 E02646 0 +OP4 E02647 0 +OP4 E02648 0 +OP4 E02649 0 +OP4 E0264A 0 +OP4 E0264B 0 +OP4 E0264C 0 +OP4 E0264D 0 +OP4 E0264E 0 +OP4 E0264F 0 +OP4 E02650 0 +OP4 E02651 0 +OP4 E02652 0 +OP4 E02653 0 +OP4 E02654 0 +OP4 E02655 0 +OP4 E02656 0 +OP4 E02657 0 +OP4 E02658 0 +OP4 E02659 0 +OP4 E0265A 0 +OP4 E0265B 0 +OP4 E0265C 0 +OP4 E0265D 0 +OP4 E0265E 0 +OP4 E0265F 0 +OP4 E02660 0 +OP4 E02661 0 +OP4 E02662 0 +OP4 E02663 0 +OP4 E02664 0 +OP4 E02665 0 +OP4 E02666 0 +OP4 E02667 0 +OP4 E02668 0 +OP4 E02669 0 +OP4 E0266A 0 +OP4 E0266B 0 +OP4 E0266C 0 +OP4 E0266D 0 +OP4 E0266E 0 +OP4 E0266F 0 +OP4 E02670 0 +OP4 E02671 0 +OP4 E02672 0 +OP4 E02673 0 +OP4 E02674 0 +OP4 E02675 0 +OP4 E02676 0 +OP4 E02677 0 +OP4 E02678 0 +OP4 E02679 0 +OP4 E0267A 0 +OP4 E0267B 0 +OP4 E0267C 0 +OP4 E0267D 0 +OP4 E0267E 0 +OP4 E0267F 0 +OP4 E02680 0 +OP4 E02681 0 +OP4 E02682 0 +OP4 E02683 0 +OP4 E02684 0 +OP4 E02685 0 +OP4 E02686 0 +OP4 E02687 0 +OP4 E02688 0 +OP4 E02689 0 +OP4 E0268A 0 +OP4 E0268B 0 +OP4 E0268C 0 +OP4 E0268D 0 +OP4 E0268E 0 +OP4 E0268F 0 +OP4 E02690 0 +OP4 E02691 0 +OP4 E02692 0 +OP4 E02693 0 +OP4 E02694 0 +OP4 E02695 0 +OP4 E02696 0 +OP4 E02697 0 +OP4 E02698 0 +OP4 E02699 0 +OP4 E0269A 0 +OP4 E0269B 0 +OP4 E0269C 0 +OP4 E0269D 0 +OP4 E0269E 0 +OP4 E0269F 0 +OP4 E026A0 0 +OP4 E026A1 0 +OP4 E026A2 0 +OP4 E026A3 0 +OP4 E026A4 0 +OP4 E026A5 0 +OP4 E026A6 0 +OP4 E026A7 0 +OP4 E026A8 0 +OP4 E026A9 0 +OP4 E026AA 0 +OP4 E026AB 0 +OP4 E026AC 0 +OP4 E026AD 0 +OP4 E026AE 0 +OP4 E026AF 0 +OP4 E026B0 0 +OP4 E026B1 0 +OP4 E026B2 0 +OP4 E026B3 0 +OP4 E026B4 0 +OP4 E026B5 0 +OP4 E026B6 0 +OP4 E026B7 0 +OP4 E026B8 0 +OP4 E026B9 0 +OP4 E026BA 0 +OP4 E026BB 0 +OP4 E026BC 0 +OP4 E026BD 0 +OP4 E026BE 0 +OP4 E026BF 0 +OP4 E026C0 0 +OP4 E026C1 0 +OP4 E026C2 0 +OP4 E026C3 0 +OP4 E026C4 0 +OP4 E026C5 0 +OP4 E026C6 0 +OP4 E026C7 0 +OP4 E026C8 0 +OP4 E026C9 0 +OP4 E026CA 0 +OP4 E026CB 0 +OP4 E026CC 0 +OP4 E026CD 0 +OP4 E026CE 0 +OP4 E026CF 0 +OP4 E026D0 0 +OP4 E026D1 0 +OP4 E026D2 0 +OP4 E026D3 0 +OP4 E026D4 0 +OP4 E026D5 0 +OP4 E026D6 0 +OP4 E026D7 0 +OP4 E026D8 0 +OP4 E026D9 0 +OP4 E026DA 0 +OP4 E026DB 0 +OP4 E026DC 0 +OP4 E026DD 0 +OP4 E026DE 0 +OP4 E026DF 0 +OP4 E026E0 0 +OP4 E026E1 0 +OP4 E026E2 0 +OP4 E026E3 0 +OP4 E026E4 0 +OP4 E026E5 0 +OP4 E026E6 0 +OP4 E026E7 0 +OP4 E026E8 0 +OP4 E026E9 0 +OP4 E026EA 0 +OP4 E026EB 0 +OP4 E026EC 0 +OP4 E026ED 0 +OP4 E026EE 0 +OP4 E026EF 0 +OP4 E026F0 0 +OP4 E026F1 0 +OP4 E026F2 0 +OP4 E026F3 0 +OP4 E026F4 0 +OP4 E026F5 0 +OP4 E026F6 0 +OP4 E026F7 0 +OP4 E026F8 0 +OP4 E026F9 0 +OP4 E026FA 0 +OP4 E026FB 0 +OP4 E026FC 0 +OP4 E026FD 0 +OP4 E026FE 0 +OP4 E026FF 0 +OP4 E02700 0 +OP4 E02701 0 +OP4 E02702 0 +OP4 E02703 0 +OP4 E02704 0 +OP4 E02705 0 +OP4 E02706 0 +OP4 E02707 0 +OP4 E02708 0 +OP4 E02709 0 +OP4 E0270A 0 +OP4 E0270B 0 +OP4 E0270C 0 +OP4 E0270D 0 +OP4 E0270E 0 +OP4 E0270F 0 +OP4 E02710 0 +OP4 E02711 0 +OP4 E02712 0 +OP4 E02713 0 +OP4 E02714 0 +OP4 E02715 0 +OP4 E02716 0 +OP4 E02717 0 +OP4 E02718 0 +OP4 E02719 0 +OP4 E0271A 0 +OP4 E0271B 0 +OP4 E0271C 0 +OP4 E0271D 0 +OP4 E0271E 0 +OP4 E0271F 0 +OP4 E02720 0 +OP4 E02721 0 +OP4 E02722 0 +OP4 E02723 0 +OP4 E02724 0 +OP4 E02725 0 +OP4 E02726 0 +OP4 E02727 0 +OP4 E02728 0 +OP4 E02729 0 +OP4 E0272A 0 +OP4 E0272B 0 +OP4 E0272C 0 +OP4 E0272D 0 +OP4 E0272E 0 +OP4 E0272F 0 +OP4 E02730 0 +OP4 E02731 0 +OP4 E02732 0 +OP4 E02733 0 +OP4 E02734 0 +OP4 E02735 0 +OP4 E02736 0 +OP4 E02737 0 +OP4 E02738 0 +OP4 E02739 0 +OP4 E0273A 0 +OP4 E0273B 0 +OP4 E0273C 0 +OP4 E0273D 0 +OP4 E0273E 0 +OP4 E0273F 0 +OP4 E02740 0 +OP4 E02741 0 +OP4 E02742 0 +OP4 E02743 0 +OP4 E02744 0 +OP4 E02745 0 +OP4 E02746 0 +OP4 E02747 0 +OP4 E02748 0 +OP4 E02749 0 +OP4 E0274A 0 +OP4 E0274B 0 +OP4 E0274C 0 +OP4 E0274D 0 +OP4 E0274E 0 +OP4 E0274F 0 +OP4 E02750 0 +OP4 E02751 0 +OP4 E02752 0 +OP4 E02753 0 +OP4 E02754 0 +OP4 E02755 0 +OP4 E02756 0 +OP4 E02757 0 +OP4 E02758 0 +OP4 E02759 0 +OP4 E0275A 0 +OP4 E0275B 0 +OP4 E0275C 0 +OP4 E0275D 0 +OP4 E0275E 0 +OP4 E0275F 0 +OP4 E02760 0 +OP4 E02761 0 +OP4 E02762 0 +OP4 E02763 0 +OP4 E02764 0 +OP4 E02765 0 +OP4 E02766 0 +OP4 E02767 0 +OP4 E02768 0 +OP4 E02769 0 +OP4 E0276A 0 +OP4 E0276B 0 +OP4 E0276C 0 +OP4 E0276D 0 +OP4 E0276E 0 +OP4 E0276F 0 +OP4 E02770 0 +OP4 E02771 0 +OP4 E02772 0 +OP4 E02773 0 +OP4 E02774 0 +OP4 E02775 0 +OP4 E02776 0 +OP4 E02777 0 +OP4 E02778 0 +OP4 E02779 0 +OP4 E0277A 0 +OP4 E0277B 0 +OP4 E0277C 0 +OP4 E0277D 0 +OP4 E0277E 0 +OP4 E0277F 0 +OP4 E02780 0 +OP4 E02781 0 +OP4 E02782 0 +OP4 E02783 0 +OP4 E02784 0 +OP4 E02785 0 +OP4 E02786 0 +OP4 E02787 0 +OP4 E02788 0 +OP4 E02789 0 +OP4 E0278A 0 +OP4 E0278B 0 +OP4 E0278C 0 +OP4 E0278D 0 +OP4 E0278E 0 +OP4 E0278F 0 +OP4 E02790 0 +OP4 E02791 0 +OP4 E02792 0 +OP4 E02793 0 +OP4 E02794 0 +OP4 E02795 0 +OP4 E02796 0 +OP4 E02797 0 +OP4 E02798 0 +OP4 E02799 0 +OP4 E0279A 0 +OP4 E0279B 0 +OP4 E0279C 0 +OP4 E0279D 0 +OP4 E0279E 0 +OP4 E0279F 0 +OP4 E027A0 0 +OP4 E027A1 0 +OP4 E027A2 0 +OP4 E027A3 0 +OP4 E027A4 0 +OP4 E027A5 0 +OP4 E027A6 0 +OP4 E027A7 0 +OP4 E027A8 0 +OP4 E027A9 0 +OP4 E027AA 0 +OP4 E027AB 0 +OP4 E027AC 0 +OP4 E027AD 0 +OP4 E027AE 0 +OP4 E027AF 0 +OP4 E027B0 0 +OP4 E027B1 0 +OP4 E027B2 0 +OP4 E027B3 0 +OP4 E027B4 0 +OP4 E027B5 0 +OP4 E027B6 0 +OP4 E027B7 0 +OP4 E027B8 0 +OP4 E027B9 0 +OP4 E027BA 0 +OP4 E027BB 0 +OP4 E027BC 0 +OP4 E027BD 0 +OP4 E027BE 0 +OP4 E027BF 0 +OP4 E027C0 0 +OP4 E027C1 0 +OP4 E027C2 0 +OP4 E027C3 0 +OP4 E027C4 0 +OP4 E027C5 0 +OP4 E027C6 0 +OP4 E027C7 0 +OP4 E027C8 0 +OP4 E027C9 0 +OP4 E027CA 0 +OP4 E027CB 0 +OP4 E027CC 0 +OP4 E027CD 0 +OP4 E027CE 0 +OP4 E027CF 0 +OP4 E027D0 0 +OP4 E027D1 0 +OP4 E027D2 0 +OP4 E027D3 0 +OP4 E027D4 0 +OP4 E027D5 0 +OP4 E027D6 0 +OP4 E027D7 0 +OP4 E027D8 0 +OP4 E027D9 0 +OP4 E027DA 0 +OP4 E027DB 0 +OP4 E027DC 0 +OP4 E027DD 0 +OP4 E027DE 0 +OP4 E027DF 0 +OP4 E027E0 0 +OP4 E027E1 0 +OP4 E027E2 0 +OP4 E027E3 0 +OP4 E027E4 0 +OP4 E027E5 0 +OP4 E027E6 0 +OP4 E027E7 0 +OP4 E027E8 0 +OP4 E027E9 0 +OP4 E027EA 0 +OP4 E027EB 0 +OP4 E027EC 0 +OP4 E027ED 0 +OP4 E027EE 0 +OP4 E027EF 0 +OP4 E027F0 0 +OP4 E027F1 0 +OP4 E027F2 0 +OP4 E027F3 0 +OP4 E027F4 0 +OP4 E027F5 0 +OP4 E027F6 0 +OP4 E027F7 0 +OP4 E027F8 0 +OP4 E027F9 0 +OP4 E027FA 0 +OP4 E027FB 0 +OP4 E027FC 0 +OP4 E027FD 0 +OP4 E027FE 0 +OP4 E027FF 0 +OP4 E02800 0 +OP4 E02801 0 +OP4 E02802 0 +OP4 E02803 0 +OP4 E02804 0 +OP4 E02805 0 +OP4 E02806 0 +OP4 E02807 0 +OP4 E02808 0 +OP4 E02809 0 +OP4 E0280A 0 +OP4 E0280B 0 +OP4 E0280C 0 +OP4 E0280D 0 +OP4 E0280E 0 +OP4 E0280F 0 +OP4 E02810 0 +OP4 E02811 0 +OP4 E02812 0 +OP4 E02813 0 +OP4 E02814 0 +OP4 E02815 0 +OP4 E02816 0 +OP4 E02817 0 +OP4 E02818 0 +OP4 E02819 0 +OP4 E0281A 0 +OP4 E0281B 0 +OP4 E0281C 0 +OP4 E0281D 0 +OP4 E0281E 0 +OP4 E0281F 0 +OP4 E02820 0 +OP4 E02821 0 +OP4 E02822 0 +OP4 E02823 0 +OP4 E02824 0 +OP4 E02825 0 +OP4 E02826 0 +OP4 E02827 0 +OP4 E02828 0 +OP4 E02829 0 +OP4 E0282A 0 +OP4 E0282B 0 +OP4 E0282C 0 +OP4 E0282D 0 +OP4 E0282E 0 +OP4 E0282F 0 +OP4 E02830 0 +OP4 E02831 0 +OP4 E02832 0 +OP4 E02833 0 +OP4 E02834 0 +OP4 E02835 0 +OP4 E02836 0 +OP4 E02837 0 +OP4 E02838 0 +OP4 E02839 0 +OP4 E0283A 0 +OP4 E0283B 0 +OP4 E0283C 0 +OP4 E0283D 0 +OP4 E0283E 0 +OP4 E0283F 0 +OP4 E02840 0 +OP4 E02841 0 +OP4 E02842 0 +OP4 E02843 0 +OP4 E02844 0 +OP4 E02845 0 +OP4 E02846 0 +OP4 E02847 0 +OP4 E02848 0 +OP4 E02849 0 +OP4 E0284A 0 +OP4 E0284B 0 +OP4 E0284C 0 +OP4 E0284D 0 +OP4 E0284E 0 +OP4 E0284F 0 +OP4 E02850 0 +OP4 E02851 0 +OP4 E02852 0 +OP4 E02853 0 +OP4 E02854 0 +OP4 E02855 0 +OP4 E02856 0 +OP4 E02857 0 +OP4 E02858 0 +OP4 E02859 0 +OP4 E0285A 0 +OP4 E0285B 0 +OP4 E0285C 0 +OP4 E0285D 0 +OP4 E0285E 0 +OP4 E0285F 0 +OP4 E02860 0 +OP4 E02861 0 +OP4 E02862 0 +OP4 E02863 0 +OP4 E02864 0 +OP4 E02865 0 +OP4 E02866 0 +OP4 E02867 0 +OP4 E02868 0 +OP4 E02869 0 +OP4 E0286A 0 +OP4 E0286B 0 +OP4 E0286C 0 +OP4 E0286D 0 +OP4 E0286E 0 +OP4 E0286F 0 +OP4 E02870 0 +OP4 E02871 0 +OP4 E02872 0 +OP4 E02873 0 +OP4 E02874 0 +OP4 E02875 0 +OP4 E02876 0 +OP4 E02877 0 +OP4 E02878 0 +OP4 E02879 0 +OP4 E0287A 0 +OP4 E0287B 0 +OP4 E0287C 0 +OP4 E0287D 0 +OP4 E0287E 0 +OP4 E0287F 0 +OP4 E02880 0 +OP4 E02881 0 +OP4 E02882 0 +OP4 E02883 0 +OP4 E02884 0 +OP4 E02885 0 +OP4 E02886 0 +OP4 E02887 0 +OP4 E02888 0 +OP4 E02889 0 +OP4 E0288A 0 +OP4 E0288B 0 +OP4 E0288C 0 +OP4 E0288D 0 +OP4 E0288E 0 +OP4 E0288F 0 +OP4 E02890 0 +OP4 E02891 0 +OP4 E02892 0 +OP4 E02893 0 +OP4 E02894 0 +OP4 E02895 0 +OP4 E02896 0 +OP4 E02897 0 +OP4 E02898 0 +OP4 E02899 0 +OP4 E0289A 0 +OP4 E0289B 0 +OP4 E0289C 0 +OP4 E0289D 0 +OP4 E0289E 0 +OP4 E0289F 0 +OP4 E028A0 0 +OP4 E028A1 0 +OP4 E028A2 0 +OP4 E028A3 0 +OP4 E028A4 0 +OP4 E028A5 0 +OP4 E028A6 0 +OP4 E028A7 0 +OP4 E028A8 0 +OP4 E028A9 0 +OP4 E028AA 0 +OP4 E028AB 0 +OP4 E028AC 0 +OP4 E028AD 0 +OP4 E028AE 0 +OP4 E028AF 0 +OP4 E028B0 0 +OP4 E028B1 0 +OP4 E028B2 0 +OP4 E028B3 0 +OP4 E028B4 0 +OP4 E028B5 0 +OP4 E028B6 0 +OP4 E028B7 0 +OP4 E028B8 0 +OP4 E028B9 0 +OP4 E028BA 0 +OP4 E028BB 0 +OP4 E028BC 0 +OP4 E028BD 0 +OP4 E028BE 0 +OP4 E028BF 0 +OP4 E028C0 0 +OP4 E028C1 0 +OP4 E028C2 0 +OP4 E028C3 0 +OP4 E028C4 0 +OP4 E028C5 0 +OP4 E028C6 0 +OP4 E028C7 0 +OP4 E028C8 0 +OP4 E028C9 0 +OP4 E028CA 0 +OP4 E028CB 0 +OP4 E028CC 0 +OP4 E028CD 0 +OP4 E028CE 0 +OP4 E028CF 0 +OP4 E028D0 0 +OP4 E028D1 0 +OP4 E028D2 0 +OP4 E028D3 0 +OP4 E028D4 0 +OP4 E028D5 0 +OP4 E028D6 0 +OP4 E028D7 0 +OP4 E028D8 0 +OP4 E028D9 0 +OP4 E028DA 0 +OP4 E028DB 0 +OP4 E028DC 0 +OP4 E028DD 0 +OP4 E028DE 0 +OP4 E028DF 0 +OP4 E028E0 0 +OP4 E028E1 0 +OP4 E028E2 0 +OP4 E028E3 0 +OP4 E028E4 0 +OP4 E028E5 0 +OP4 E028E6 0 +OP4 E028E7 0 +OP4 E028E8 0 +OP4 E028E9 0 +OP4 E028EA 0 +OP4 E028EB 0 +OP4 E028EC 0 +OP4 E028ED 0 +OP4 E028EE 0 +OP4 E028EF 0 +OP4 E028F0 0 +OP4 E028F1 0 +OP4 E028F2 0 +OP4 E028F3 0 +OP4 E028F4 0 +OP4 E028F5 0 +OP4 E028F6 0 +OP4 E028F7 0 +OP4 E028F8 0 +OP4 E028F9 0 +OP4 E028FA 0 +OP4 E028FB 0 +OP4 E028FC 0 +OP4 E028FD 0 +OP4 E028FE 0 +OP4 E028FF 0 +OP4 E02900 0 +OP4 E02901 0 +OP4 E02902 0 +OP4 E02903 0 +OP4 E02904 0 +OP4 E02905 0 +OP4 E02906 0 +OP4 E02907 0 +OP4 E02908 0 +OP4 E02909 0 +OP4 E0290A 0 +OP4 E0290B 0 +OP4 E0290C 0 +OP4 E0290D 0 +OP4 E0290E 0 +OP4 E0290F 0 +OP4 E02910 0 +OP4 E02911 0 +OP4 E02912 0 +OP4 E02913 0 +OP4 E02914 0 +OP4 E02915 0 +OP4 E02916 0 +OP4 E02917 0 +OP4 E02918 0 +OP4 E02919 0 +OP4 E0291A 0 +OP4 E0291B 0 +OP4 E0291C 0 +OP4 E0291D 0 +OP4 E0291E 0 +OP4 E0291F 0 +OP4 E02920 0 +OP4 E02921 0 +OP4 E02922 0 +OP4 E02923 0 +OP4 E02924 0 +OP4 E02925 0 +OP4 E02926 0 +OP4 E02927 0 +OP4 E02928 0 +OP4 E02929 0 +OP4 E0292A 0 +OP4 E0292B 0 +OP4 E0292C 0 +OP4 E0292D 0 +OP4 E0292E 0 +OP4 E0292F 0 +OP4 E02930 0 +OP4 E02931 0 +OP4 E02932 0 +OP4 E02933 0 +OP4 E02934 0 +OP4 E02935 0 +OP4 E02936 0 +OP4 E02937 0 +OP4 E02938 0 +OP4 E02939 0 +OP4 E0293A 0 +OP4 E0293B 0 +OP4 E0293C 0 +OP4 E0293D 0 +OP4 E0293E 0 +OP4 E0293F 0 +OP4 E02940 0 +OP4 E02941 0 +OP4 E02942 0 +OP4 E02943 0 +OP4 E02944 0 +OP4 E02945 0 +OP4 E02946 0 +OP4 E02947 0 +OP4 E02948 0 +OP4 E02949 0 +OP4 E0294A 0 +OP4 E0294B 0 +OP4 E0294C 0 +OP4 E0294D 0 +OP4 E0294E 0 +OP4 E0294F 0 +OP4 E02950 0 +OP4 E02951 0 +OP4 E02952 0 +OP4 E02953 0 +OP4 E02954 0 +OP4 E02955 0 +OP4 E02956 0 +OP4 E02957 0 +OP4 E02958 0 +OP4 E02959 0 +OP4 E0295A 0 +OP4 E0295B 0 +OP4 E0295C 0 +OP4 E0295D 0 +OP4 E0295E 0 +OP4 E0295F 0 +OP4 E02960 0 +OP4 E02961 0 +OP4 E02962 0 +OP4 E02963 0 +OP4 E02964 0 +OP4 E02965 0 +OP4 E02966 0 +OP4 E02967 0 +OP4 E02968 0 +OP4 E02969 0 +OP4 E0296A 0 +OP4 E0296B 0 +OP4 E0296C 0 +OP4 E0296D 0 +OP4 E0296E 0 +OP4 E0296F 0 +OP4 E02970 0 +OP4 E02971 0 +OP4 E02972 0 +OP4 E02973 0 +OP4 E02974 0 +OP4 E02975 0 +OP4 E02976 0 +OP4 E02977 0 +OP4 E02978 0 +OP4 E02979 0 +OP4 E0297A 0 +OP4 E0297B 0 +OP4 E0297C 0 +OP4 E0297D 0 +OP4 E0297E 0 +OP4 E0297F 0 +OP4 E02980 0 +OP4 E02981 0 +OP4 E02982 0 +OP4 E02983 0 +OP4 E02984 0 +OP4 E02985 0 +OP4 E02986 0 +OP4 E02987 0 +OP4 E02988 0 +OP4 E02989 0 +OP4 E0298A 0 +OP4 E0298B 0 +OP4 E0298C 0 +OP4 E0298D 0 +OP4 E0298E 0 +OP4 E0298F 0 +OP4 E02990 0 +OP4 E02991 0 +OP4 E02992 0 +OP4 E02993 0 +OP4 E02994 0 +OP4 E02995 0 +OP4 E02996 0 +OP4 E02997 0 +OP4 E02998 0 +OP4 E02999 0 +OP4 E0299A 0 +OP4 E0299B 0 +OP4 E0299C 0 +OP4 E0299D 0 +OP4 E0299E 0 +OP4 E0299F 0 +OP4 E029A0 0 +OP4 E029A1 0 +OP4 E029A2 0 +OP4 E029A3 0 +OP4 E029A4 0 +OP4 E029A5 0 +OP4 E029A6 0 +OP4 E029A7 0 +OP4 E029A8 0 +OP4 E029A9 0 +OP4 E029AA 0 +OP4 E029AB 0 +OP4 E029AC 0 +OP4 E029AD 0 +OP4 E029AE 0 +OP4 E029AF 0 +OP4 E029B0 0 +OP4 E029B1 0 +OP4 E029B2 0 +OP4 E029B3 0 +OP4 E029B4 0 +OP4 E029B5 0 +OP4 E029B6 0 +OP4 E029B7 0 +OP4 E029B8 0 +OP4 E029B9 0 +OP4 E029BA 0 +OP4 E029BB 0 +OP4 E029BC 0 +OP4 E029BD 0 +OP4 E029BE 0 +OP4 E029BF 0 +OP4 E029C0 0 +OP4 E029C1 0 +OP4 E029C2 0 +OP4 E029C3 0 +OP4 E029C4 0 +OP4 E029C5 0 +OP4 E029C6 0 +OP4 E029C7 0 +OP4 E029C8 0 +OP4 E029C9 0 +OP4 E029CA 0 +OP4 E029CB 0 +OP4 E029CC 0 +OP4 E029CD 0 +OP4 E029CE 0 +OP4 E029CF 0 +OP4 E029D0 0 +OP4 E029D1 0 +OP4 E029D2 0 +OP4 E029D3 0 +OP4 E029D4 0 +OP4 E029D5 0 +OP4 E029D6 0 +OP4 E029D7 0 +OP4 E029D8 0 +OP4 E029D9 0 +OP4 E029DA 0 +OP4 E029DB 0 +OP4 E029DC 0 +OP4 E029DD 0 +OP4 E029DE 0 +OP4 E029DF 0 +OP4 E029E0 0 +OP4 E029E1 0 +OP4 E029E2 0 +OP4 E029E3 0 +OP4 E029E4 0 +OP4 E029E5 0 +OP4 E029E6 0 +OP4 E029E7 0 +OP4 E029E8 0 +OP4 E029E9 0 +OP4 E029EA 0 +OP4 E029EB 0 +OP4 E029EC 0 +OP4 E029ED 0 +OP4 E029EE 0 +OP4 E029EF 0 +OP4 E029F0 0 +OP4 E029F1 0 +OP4 E029F2 0 +OP4 E029F3 0 +OP4 E029F4 0 +OP4 E029F5 0 +OP4 E029F6 0 +OP4 E029F7 0 +OP4 E029F8 0 +OP4 E029F9 0 +OP4 E029FA 0 +OP4 E029FB 0 +OP4 E029FC 0 +OP4 E029FD 0 +OP4 E029FE 0 +OP4 E029FF 0 +OP4 E02A00 0 +OP4 E02A01 0 +OP4 E02A02 0 +OP4 E02A03 0 +OP4 E02A04 0 +OP4 E02A05 0 +OP4 E02A06 0 +OP4 E02A07 0 +OP4 E02A08 0 +OP4 E02A09 0 +OP4 E02A0A 0 +OP4 E02A0B 0 +OP4 E02A0C 0 +OP4 E02A0D 0 +OP4 E02A0E 0 +OP4 E02A0F 0 +OP4 E02A10 0 +OP4 E02A11 0 +OP4 E02A12 0 +OP4 E02A13 0 +OP4 E02A14 0 +OP4 E02A15 0 +OP4 E02A16 0 +OP4 E02A17 0 +OP4 E02A18 0 +OP4 E02A19 0 +OP4 E02A1A 0 +OP4 E02A1B 0 +OP4 E02A1C 0 +OP4 E02A1D 0 +OP4 E02A1E 0 +OP4 E02A1F 0 +OP4 E02A20 0 +OP4 E02A21 0 +OP4 E02A22 0 +OP4 E02A23 0 +OP4 E02A24 0 +OP4 E02A25 0 +OP4 E02A26 0 +OP4 E02A27 0 +OP4 E02A28 0 +OP4 E02A29 0 +OP4 E02A2A 0 +OP4 E02A2B 0 +OP4 E02A2C 0 +OP4 E02A2D 0 +OP4 E02A2E 0 +OP4 E02A2F 0 +OP4 E02A30 0 +OP4 E02A31 0 +OP4 E02A32 0 +OP4 E02A33 0 +OP4 E02A34 0 +OP4 E02A35 0 +OP4 E02A36 0 +OP4 E02A37 0 +OP4 E02A38 0 +OP4 E02A39 0 +OP4 E02A3A 0 +OP4 E02A3B 0 +OP4 E02A3C 0 +OP4 E02A3D 0 +OP4 E02A3E 0 +OP4 E02A3F 0 +OP4 E02A40 0 +OP4 E02A41 0 +OP4 E02A42 0 +OP4 E02A43 0 +OP4 E02A44 0 +OP4 E02A45 0 +OP4 E02A46 0 +OP4 E02A47 0 +OP4 E02A48 0 +OP4 E02A49 0 +OP4 E02A4A 0 +OP4 E02A4B 0 +OP4 E02A4C 0 +OP4 E02A4D 0 +OP4 E02A4E 0 +OP4 E02A4F 0 +OP4 E02A50 0 +OP4 E02A51 0 +OP4 E02A52 0 +OP4 E02A53 0 +OP4 E02A54 0 +OP4 E02A55 0 +OP4 E02A56 0 +OP4 E02A57 0 +OP4 E02A58 0 +OP4 E02A59 0 +OP4 E02A5A 0 +OP4 E02A5B 0 +OP4 E02A5C 0 +OP4 E02A5D 0 +OP4 E02A5E 0 +OP4 E02A5F 0 +OP4 E02A60 0 +OP4 E02A61 0 +OP4 E02A62 0 +OP4 E02A63 0 +OP4 E02A64 0 +OP4 E02A65 0 +OP4 E02A66 0 +OP4 E02A67 0 +OP4 E02A68 0 +OP4 E02A69 0 +OP4 E02A6A 0 +OP4 E02A6B 0 +OP4 E02A6C 0 +OP4 E02A6D 0 +OP4 E02A6E 0 +OP4 E02A6F 0 +OP4 E02A70 0 +OP4 E02A71 0 +OP4 E02A72 0 +OP4 E02A73 0 +OP4 E02A74 0 +OP4 E02A75 0 +OP4 E02A76 0 +OP4 E02A77 0 +OP4 E02A78 0 +OP4 E02A79 0 +OP4 E02A7A 0 +OP4 E02A7B 0 +OP4 E02A7C 0 +OP4 E02A7D 0 +OP4 E02A7E 0 +OP4 E02A7F 0 +OP4 E02A80 0 +OP4 E02A81 0 +OP4 E02A82 0 +OP4 E02A83 0 +OP4 E02A84 0 +OP4 E02A85 0 +OP4 E02A86 0 +OP4 E02A87 0 +OP4 E02A88 0 +OP4 E02A89 0 +OP4 E02A8A 0 +OP4 E02A8B 0 +OP4 E02A8C 0 +OP4 E02A8D 0 +OP4 E02A8E 0 +OP4 E02A8F 0 +OP4 E02A90 0 +OP4 E02A91 0 +OP4 E02A92 0 +OP4 E02A93 0 +OP4 E02A94 0 +OP4 E02A95 0 +OP4 E02A96 0 +OP4 E02A97 0 +OP4 E02A98 0 +OP4 E02A99 0 +OP4 E02A9A 0 +OP4 E02A9B 0 +OP4 E02A9C 0 +OP4 E02A9D 0 +OP4 E02A9E 0 +OP4 E02A9F 0 +OP4 E02AA0 0 +OP4 E02AA1 0 +OP4 E02AA2 0 +OP4 E02AA3 0 +OP4 E02AA4 0 +OP4 E02AA5 0 +OP4 E02AA6 0 +OP4 E02AA7 0 +OP4 E02AA8 0 +OP4 E02AA9 0 +OP4 E02AAA 0 +OP4 E02AAB 0 +OP4 E02AAC 0 +OP4 E02AAD 0 +OP4 E02AAE 0 +OP4 E02AAF 0 +OP4 E02AB0 0 +OP4 E02AB1 0 +OP4 E02AB2 0 +OP4 E02AB3 0 +OP4 E02AB4 0 +OP4 E02AB5 0 +OP4 E02AB6 0 +OP4 E02AB7 0 +OP4 E02AB8 0 +OP4 E02AB9 0 +OP4 E02ABA 0 +OP4 E02ABB 0 +OP4 E02ABC 0 +OP4 E02ABD 0 +OP4 E02ABE 0 +OP4 E02ABF 0 +OP4 E02AC0 0 +OP4 E02AC1 0 +OP4 E02AC2 0 +OP4 E02AC3 0 +OP4 E02AC4 0 +OP4 E02AC5 0 +OP4 E02AC6 0 +OP4 E02AC7 0 +OP4 E02AC8 0 +OP4 E02AC9 0 +OP4 E02ACA 0 +OP4 E02ACB 0 +OP4 E02ACC 0 +OP4 E02ACD 0 +OP4 E02ACE 0 +OP4 E02ACF 0 +OP4 E02AD0 0 +OP4 E02AD1 0 +OP4 E02AD2 0 +OP4 E02AD3 0 +OP4 E02AD4 0 +OP4 E02AD5 0 +OP4 E02AD6 0 +OP4 E02AD7 0 +OP4 E02AD8 0 +OP4 E02AD9 0 +OP4 E02ADA 0 +OP4 E02ADB 0 +OP4 E02ADC 0 +OP4 E02ADD 0 +OP4 E02ADE 0 +OP4 E02ADF 0 +OP4 E02AE0 0 +OP4 E02AE1 0 +OP4 E02AE2 0 +OP4 E02AE3 0 +OP4 E02AE4 0 +OP4 E02AE5 0 +OP4 E02AE6 0 +OP4 E02AE7 0 +OP4 E02AE8 0 +OP4 E02AE9 0 +OP4 E02AEA 0 +OP4 E02AEB 0 +OP4 E02AEC 0 +OP4 E02AED 0 +OP4 E02AEE 0 +OP4 E02AEF 0 +OP4 E02AF0 0 +OP4 E02AF1 0 +OP4 E02AF2 0 +OP4 E02AF3 0 +OP4 E02AF4 0 +OP4 E02AF5 0 +OP4 E02AF6 0 +OP4 E02AF7 0 +OP4 E02AF8 0 +OP4 E02AF9 0 +OP4 E02AFA 0 +OP4 E02AFB 0 +OP4 E02AFC 0 +OP4 E02AFD 0 +OP4 E02AFE 0 +OP4 E02AFF 0 +OP4 E02B00 0 +OP4 E02B01 0 +OP4 E02B02 0 +OP4 E02B03 0 +OP4 E02B04 0 +OP4 E02B05 0 +OP4 E02B06 0 +OP4 E02B07 0 +OP4 E02B08 0 +OP4 E02B09 0 +OP4 E02B0A 0 +OP4 E02B0B 0 +OP4 E02B0C 0 +OP4 E02B0D 0 +OP4 E02B0E 0 +OP4 E02B0F 0 +OP4 E02B10 0 +OP4 E02B11 0 +OP4 E02B12 0 +OP4 E02B13 0 +OP4 E02B14 0 +OP4 E02B15 0 +OP4 E02B16 0 +OP4 E02B17 0 +OP4 E02B18 0 +OP4 E02B19 0 +OP4 E02B1A 0 +OP4 E02B1B 0 +OP4 E02B1C 0 +OP4 E02B1D 0 +OP4 E02B1E 0 +OP4 E02B1F 0 +OP4 E02B20 0 +OP4 E02B21 0 +OP4 E02B22 0 +OP4 E02B23 0 +OP4 E02B24 0 +OP4 E02B25 0 +OP4 E02B26 0 +OP4 E02B27 0 +OP4 E02B28 0 +OP4 E02B29 0 +OP4 E02B2A 0 +OP4 E02B2B 0 +OP4 E02B2C 0 +OP4 E02B2D 0 +OP4 E02B2E 0 +OP4 E02B2F 0 +OP4 E02B30 0 +OP4 E02B31 0 +OP4 E02B32 0 +OP4 E02B33 0 +OP4 E02B34 0 +OP4 E02B35 0 +OP4 E02B36 0 +OP4 E02B37 0 +OP4 E02B38 0 +OP4 E02B39 0 +OP4 E02B3A 0 +OP4 E02B3B 0 +OP4 E02B3C 0 +OP4 E02B3D 0 +OP4 E02B3E 0 +OP4 E02B3F 0 +OP4 E02B40 0 +OP4 E02B41 0 +OP4 E02B42 0 +OP4 E02B43 0 +OP4 E02B44 0 +OP4 E02B45 0 +OP4 E02B46 0 +OP4 E02B47 0 +OP4 E02B48 0 +OP4 E02B49 0 +OP4 E02B4A 0 +OP4 E02B4B 0 +OP4 E02B4C 0 +OP4 E02B4D 0 +OP4 E02B4E 0 +OP4 E02B4F 0 +OP4 E02B50 0 +OP4 E02B51 0 +OP4 E02B52 0 +OP4 E02B53 0 +OP4 E02B54 0 +OP4 E02B55 0 +OP4 E02B56 0 +OP4 E02B57 0 +OP4 E02B58 0 +OP4 E02B59 0 +OP4 E02B5A 0 +OP4 E02B5B 0 +OP4 E02B5C 0 +OP4 E02B5D 0 +OP4 E02B5E 0 +OP4 E02B5F 0 +OP4 E02B60 0 +OP4 E02B61 0 +OP4 E02B62 0 +OP4 E02B63 0 +OP4 E02B64 0 +OP4 E02B65 0 +OP4 E02B66 0 +OP4 E02B67 0 +OP4 E02B68 0 +OP4 E02B69 0 +OP4 E02B6A 0 +OP4 E02B6B 0 +OP4 E02B6C 0 +OP4 E02B6D 0 +OP4 E02B6E 0 +OP4 E02B6F 0 +OP4 E02B70 0 +OP4 E02B71 0 +OP4 E02B72 0 +OP4 E02B73 0 +OP4 E02B74 0 +OP4 E02B75 0 +OP4 E02B76 0 +OP4 E02B77 0 +OP4 E02B78 0 +OP4 E02B79 0 +OP4 E02B7A 0 +OP4 E02B7B 0 +OP4 E02B7C 0 +OP4 E02B7D 0 +OP4 E02B7E 0 +OP4 E02B7F 0 +OP4 E02B80 0 +OP4 E02B81 0 +OP4 E02B82 0 +OP4 E02B83 0 +OP4 E02B84 0 +OP4 E02B85 0 +OP4 E02B86 0 +OP4 E02B87 0 +OP4 E02B88 0 +OP4 E02B89 0 +OP4 E02B8A 0 +OP4 E02B8B 0 +OP4 E02B8C 0 +OP4 E02B8D 0 +OP4 E02B8E 0 +OP4 E02B8F 0 +OP4 E02B90 0 +OP4 E02B91 0 +OP4 E02B92 0 +OP4 E02B93 0 +OP4 E02B94 0 +OP4 E02B95 0 +OP4 E02B96 0 +OP4 E02B97 0 +OP4 E02B98 0 +OP4 E02B99 0 +OP4 E02B9A 0 +OP4 E02B9B 0 +OP4 E02B9C 0 +OP4 E02B9D 0 +OP4 E02B9E 0 +OP4 E02B9F 0 +OP4 E02BA0 0 +OP4 E02BA1 0 +OP4 E02BA2 0 +OP4 E02BA3 0 +OP4 E02BA4 0 +OP4 E02BA5 0 +OP4 E02BA6 0 +OP4 E02BA7 0 +OP4 E02BA8 0 +OP4 E02BA9 0 +OP4 E02BAA 0 +OP4 E02BAB 0 +OP4 E02BAC 0 +OP4 E02BAD 0 +OP4 E02BAE 0 +OP4 E02BAF 0 +OP4 E02BB0 0 +OP4 E02BB1 0 +OP4 E02BB2 0 +OP4 E02BB3 0 +OP4 E02BB4 0 +OP4 E02BB5 0 +OP4 E02BB6 0 +OP4 E02BB7 0 +OP4 E02BB8 0 +OP4 E02BB9 0 +OP4 E02BBA 0 +OP4 E02BBB 0 +OP4 E02BBC 0 +OP4 E02BBD 0 +OP4 E02BBE 0 +OP4 E02BBF 0 +OP4 E02BC0 0 +OP4 E02BC1 0 +OP4 E02BC2 0 +OP4 E02BC3 0 +OP4 E02BC4 0 +OP4 E02BC5 0 +OP4 E02BC6 0 +OP4 E02BC7 0 +OP4 E02BC8 0 +OP4 E02BC9 0 +OP4 E02BCA 0 +OP4 E02BCB 0 +OP4 E02BCC 0 +OP4 E02BCD 0 +OP4 E02BCE 0 +OP4 E02BCF 0 +OP4 E02BD0 0 +OP4 E02BD1 0 +OP4 E02BD2 0 +OP4 E02BD3 0 +OP4 E02BD4 0 +OP4 E02BD5 0 +OP4 E02BD6 0 +OP4 E02BD7 0 +OP4 E02BD8 0 +OP4 E02BD9 0 +OP4 E02BDA 0 +OP4 E02BDB 0 +OP4 E02BDC 0 +OP4 E02BDD 0 +OP4 E02BDE 0 +OP4 E02BDF 0 +OP4 E02BE0 0 +OP4 E02BE1 0 +OP4 E02BE2 0 +OP4 E02BE3 0 +OP4 E02BE4 0 +OP4 E02BE5 0 +OP4 E02BE6 0 +OP4 E02BE7 0 +OP4 E02BE8 0 +OP4 E02BE9 0 +OP4 E02BEA 0 +OP4 E02BEB 0 +OP4 E02BEC 0 +OP4 E02BED 0 +OP4 E02BEE 0 +OP4 E02BEF 0 +OP4 E02BF0 0 +OP4 E02BF1 0 +OP4 E02BF2 0 +OP4 E02BF3 0 +OP4 E02BF4 0 +OP4 E02BF5 0 +OP4 E02BF6 0 +OP4 E02BF7 0 +OP4 E02BF8 0 +OP4 E02BF9 0 +OP4 E02BFA 0 +OP4 E02BFB 0 +OP4 E02BFC 0 +OP4 E02BFD 0 +OP4 E02BFE 0 +OP4 E02BFF 0 +OP4 E02C00 0 +OP4 E02C01 0 +OP4 E02C02 0 +OP4 E02C03 0 +OP4 E02C04 0 +OP4 E02C05 0 +OP4 E02C06 0 +OP4 E02C07 0 +OP4 E02C08 0 +OP4 E02C09 0 +OP4 E02C0A 0 +OP4 E02C0B 0 +OP4 E02C0C 0 +OP4 E02C0D 0 +OP4 E02C0E 0 +OP4 E02C0F 0 +OP4 E02C10 0 +OP4 E02C11 0 +OP4 E02C12 0 +OP4 E02C13 0 +OP4 E02C14 0 +OP4 E02C15 0 +OP4 E02C16 0 +OP4 E02C17 0 +OP4 E02C18 0 +OP4 E02C19 0 +OP4 E02C1A 0 +OP4 E02C1B 0 +OP4 E02C1C 0 +OP4 E02C1D 0 +OP4 E02C1E 0 +OP4 E02C1F 0 +OP4 E02C20 0 +OP4 E02C21 0 +OP4 E02C22 0 +OP4 E02C23 0 +OP4 E02C24 0 +OP4 E02C25 0 +OP4 E02C26 0 +OP4 E02C27 0 +OP4 E02C28 0 +OP4 E02C29 0 +OP4 E02C2A 0 +OP4 E02C2B 0 +OP4 E02C2C 0 +OP4 E02C2D 0 +OP4 E02C2E 0 +OP4 E02C2F 0 +OP4 E02C30 0 +OP4 E02C31 0 +OP4 E02C32 0 +OP4 E02C33 0 +OP4 E02C34 0 +OP4 E02C35 0 +OP4 E02C36 0 +OP4 E02C37 0 +OP4 E02C38 0 +OP4 E02C39 0 +OP4 E02C3A 0 +OP4 E02C3B 0 +OP4 E02C3C 0 +OP4 E02C3D 0 +OP4 E02C3E 0 +OP4 E02C3F 0 +OP4 E02C40 0 +OP4 E02C41 0 +OP4 E02C42 0 +OP4 E02C43 0 +OP4 E02C44 0 +OP4 E02C45 0 +OP4 E02C46 0 +OP4 E02C47 0 +OP4 E02C48 0 +OP4 E02C49 0 +OP4 E02C4A 0 +OP4 E02C4B 0 +OP4 E02C4C 0 +OP4 E02C4D 0 +OP4 E02C4E 0 +OP4 E02C4F 0 +OP4 E02C50 0 +OP4 E02C51 0 +OP4 E02C52 0 +OP4 E02C53 0 +OP4 E02C54 0 +OP4 E02C55 0 +OP4 E02C56 0 +OP4 E02C57 0 +OP4 E02C58 0 +OP4 E02C59 0 +OP4 E02C5A 0 +OP4 E02C5B 0 +OP4 E02C5C 0 +OP4 E02C5D 0 +OP4 E02C5E 0 +OP4 E02C5F 0 +OP4 E02C60 0 +OP4 E02C61 0 +OP4 E02C62 0 +OP4 E02C63 0 +OP4 E02C64 0 +OP4 E02C65 0 +OP4 E02C66 0 +OP4 E02C67 0 +OP4 E02C68 0 +OP4 E02C69 0 +OP4 E02C6A 0 +OP4 E02C6B 0 +OP4 E02C6C 0 +OP4 E02C6D 0 +OP4 E02C6E 0 +OP4 E02C6F 0 +OP4 E02C70 0 +OP4 E02C71 0 +OP4 E02C72 0 +OP4 E02C73 0 +OP4 E02C74 0 +OP4 E02C75 0 +OP4 E02C76 0 +OP4 E02C77 0 +OP4 E02C78 0 +OP4 E02C79 0 +OP4 E02C7A 0 +OP4 E02C7B 0 +OP4 E02C7C 0 +OP4 E02C7D 0 +OP4 E02C7E 0 +OP4 E02C7F 0 +OP4 E02C80 0 +OP4 E02C81 0 +OP4 E02C82 0 +OP4 E02C83 0 +OP4 E02C84 0 +OP4 E02C85 0 +OP4 E02C86 0 +OP4 E02C87 0 +OP4 E02C88 0 +OP4 E02C89 0 +OP4 E02C8A 0 +OP4 E02C8B 0 +OP4 E02C8C 0 +OP4 E02C8D 0 +OP4 E02C8E 0 +OP4 E02C8F 0 +OP4 E02C90 0 +OP4 E02C91 0 +OP4 E02C92 0 +OP4 E02C93 0 +OP4 E02C94 0 +OP4 E02C95 0 +OP4 E02C96 0 +OP4 E02C97 0 +OP4 E02C98 0 +OP4 E02C99 0 +OP4 E02C9A 0 +OP4 E02C9B 0 +OP4 E02C9C 0 +OP4 E02C9D 0 +OP4 E02C9E 0 +OP4 E02C9F 0 +OP4 E02CA0 0 +OP4 E02CA1 0 +OP4 E02CA2 0 +OP4 E02CA3 0 +OP4 E02CA4 0 +OP4 E02CA5 0 +OP4 E02CA6 0 +OP4 E02CA7 0 +OP4 E02CA8 0 +OP4 E02CA9 0 +OP4 E02CAA 0 +OP4 E02CAB 0 +OP4 E02CAC 0 +OP4 E02CAD 0 +OP4 E02CAE 0 +OP4 E02CAF 0 +OP4 E02CB0 0 +OP4 E02CB1 0 +OP4 E02CB2 0 +OP4 E02CB3 0 +OP4 E02CB4 0 +OP4 E02CB5 0 +OP4 E02CB6 0 +OP4 E02CB7 0 +OP4 E02CB8 0 +OP4 E02CB9 0 +OP4 E02CBA 0 +OP4 E02CBB 0 +OP4 E02CBC 0 +OP4 E02CBD 0 +OP4 E02CBE 0 +OP4 E02CBF 0 +OP4 E02CC0 0 +OP4 E02CC1 0 +OP4 E02CC2 0 +OP4 E02CC3 0 +OP4 E02CC4 0 +OP4 E02CC5 0 +OP4 E02CC6 0 +OP4 E02CC7 0 +OP4 E02CC8 0 +OP4 E02CC9 0 +OP4 E02CCA 0 +OP4 E02CCB 0 +OP4 E02CCC 0 +OP4 E02CCD 0 +OP4 E02CCE 0 +OP4 E02CCF 0 +OP4 E02CD0 0 +OP4 E02CD1 0 +OP4 E02CD2 0 +OP4 E02CD3 0 +OP4 E02CD4 0 +OP4 E02CD5 0 +OP4 E02CD6 0 +OP4 E02CD7 0 +OP4 E02CD8 0 +OP4 E02CD9 0 +OP4 E02CDA 0 +OP4 E02CDB 0 +OP4 E02CDC 0 +OP4 E02CDD 0 +OP4 E02CDE 0 +OP4 E02CDF 0 +OP4 E02CE0 0 +OP4 E02CE1 0 +OP4 E02CE2 0 +OP4 E02CE3 0 +OP4 E02CE4 0 +OP4 E02CE5 0 +OP4 E02CE6 0 +OP4 E02CE7 0 +OP4 E02CE8 0 +OP4 E02CE9 0 +OP4 E02CEA 0 +OP4 E02CEB 0 +OP4 E02CEC 0 +OP4 E02CED 0 +OP4 E02CEE 0 +OP4 E02CEF 0 +OP4 E02CF0 0 +OP4 E02CF1 0 +OP4 E02CF2 0 +OP4 E02CF3 0 +OP4 E02CF4 0 +OP4 E02CF5 0 +OP4 E02CF6 0 +OP4 E02CF7 0 +OP4 E02CF8 0 +OP4 E02CF9 0 +OP4 E02CFA 0 +OP4 E02CFB 0 +OP4 E02CFC 0 +OP4 E02CFD 0 +OP4 E02CFE 0 +OP4 E02CFF 0 +OP4 E02D00 0 +OP4 E02D01 0 +OP4 E02D02 0 +OP4 E02D03 0 +OP4 E02D04 0 +OP4 E02D05 0 +OP4 E02D06 0 +OP4 E02D07 0 +OP4 E02D08 0 +OP4 E02D09 0 +OP4 E02D0A 0 +OP4 E02D0B 0 +OP4 E02D0C 0 +OP4 E02D0D 0 +OP4 E02D0E 0 +OP4 E02D0F 0 +OP4 E02D10 0 +OP4 E02D11 0 +OP4 E02D12 0 +OP4 E02D13 0 +OP4 E02D14 0 +OP4 E02D15 0 +OP4 E02D16 0 +OP4 E02D17 0 +OP4 E02D18 0 +OP4 E02D19 0 +OP4 E02D1A 0 +OP4 E02D1B 0 +OP4 E02D1C 0 +OP4 E02D1D 0 +OP4 E02D1E 0 +OP4 E02D1F 0 +OP4 E02D20 0 +OP4 E02D21 0 +OP4 E02D22 0 +OP4 E02D23 0 +OP4 E02D24 0 +OP4 E02D25 0 +OP4 E02D26 0 +OP4 E02D27 0 +OP4 E02D28 0 +OP4 E02D29 0 +OP4 E02D2A 0 +OP4 E02D2B 0 +OP4 E02D2C 0 +OP4 E02D2D 0 +OP4 E02D2E 0 +OP4 E02D2F 0 +OP4 E02D30 0 +OP4 E02D31 0 +OP4 E02D32 0 +OP4 E02D33 0 +OP4 E02D34 0 +OP4 E02D35 0 +OP4 E02D36 0 +OP4 E02D37 0 +OP4 E02D38 0 +OP4 E02D39 0 +OP4 E02D3A 0 +OP4 E02D3B 0 +OP4 E02D3C 0 +OP4 E02D3D 0 +OP4 E02D3E 0 +OP4 E02D3F 0 +OP4 E02D40 0 +OP4 E02D41 0 +OP4 E02D42 0 +OP4 E02D43 0 +OP4 E02D44 0 +OP4 E02D45 0 +OP4 E02D46 0 +OP4 E02D47 0 +OP4 E02D48 0 +OP4 E02D49 0 +OP4 E02D4A 0 +OP4 E02D4B 0 +OP4 E02D4C 0 +OP4 E02D4D 0 +OP4 E02D4E 0 +OP4 E02D4F 0 +OP4 E02D50 0 +OP4 E02D51 0 +OP4 E02D52 0 +OP4 E02D53 0 +OP4 E02D54 0 +OP4 E02D55 0 +OP4 E02D56 0 +OP4 E02D57 0 +OP4 E02D58 0 +OP4 E02D59 0 +OP4 E02D5A 0 +OP4 E02D5B 0 +OP4 E02D5C 0 +OP4 E02D5D 0 +OP4 E02D5E 0 +OP4 E02D5F 0 +OP4 E02D60 0 +OP4 E02D61 0 +OP4 E02D62 0 +OP4 E02D63 0 +OP4 E02D64 0 +OP4 E02D65 0 +OP4 E02D66 0 +OP4 E02D67 0 +OP4 E02D68 0 +OP4 E02D69 0 +OP4 E02D6A 0 +OP4 E02D6B 0 +OP4 E02D6C 0 +OP4 E02D6D 0 +OP4 E02D6E 0 +OP4 E02D6F 0 +OP4 E02D70 0 +OP4 E02D71 0 +OP4 E02D72 0 +OP4 E02D73 0 +OP4 E02D74 0 +OP4 E02D75 0 +OP4 E02D76 0 +OP4 E02D77 0 +OP4 E02D78 0 +OP4 E02D79 0 +OP4 E02D7A 0 +OP4 E02D7B 0 +OP4 E02D7C 0 +OP4 E02D7D 0 +OP4 E02D7E 0 +OP4 E02D7F 0 +OP4 E02D80 0 +OP4 E02D81 0 +OP4 E02D82 0 +OP4 E02D83 0 +OP4 E02D84 0 +OP4 E02D85 0 +OP4 E02D86 0 +OP4 E02D87 0 +OP4 E02D88 0 +OP4 E02D89 0 +OP4 E02D8A 0 +OP4 E02D8B 0 +OP4 E02D8C 0 +OP4 E02D8D 0 +OP4 E02D8E 0 +OP4 E02D8F 0 +OP4 E02D90 0 +OP4 E02D91 0 +OP4 E02D92 0 +OP4 E02D93 0 +OP4 E02D94 0 +OP4 E02D95 0 +OP4 E02D96 0 +OP4 E02D97 0 +OP4 E02D98 0 +OP4 E02D99 0 +OP4 E02D9A 0 +OP4 E02D9B 0 +OP4 E02D9C 0 +OP4 E02D9D 0 +OP4 E02D9E 0 +OP4 E02D9F 0 +OP4 E02DA0 0 +OP4 E02DA1 0 +OP4 E02DA2 0 +OP4 E02DA3 0 +OP4 E02DA4 0 +OP4 E02DA5 0 +OP4 E02DA6 0 +OP4 E02DA7 0 +OP4 E02DA8 0 +OP4 E02DA9 0 +OP4 E02DAA 0 +OP4 E02DAB 0 +OP4 E02DAC 0 +OP4 E02DAD 0 +OP4 E02DAE 0 +OP4 E02DAF 0 +OP4 E02DB0 0 +OP4 E02DB1 0 +OP4 E02DB2 0 +OP4 E02DB3 0 +OP4 E02DB4 0 +OP4 E02DB5 0 +OP4 E02DB6 0 +OP4 E02DB7 0 +OP4 E02DB8 0 +OP4 E02DB9 0 +OP4 E02DBA 0 +OP4 E02DBB 0 +OP4 E02DBC 0 +OP4 E02DBD 0 +OP4 E02DBE 0 +OP4 E02DBF 0 +OP4 E02DC0 0 +OP4 E02DC1 0 +OP4 E02DC2 0 +OP4 E02DC3 0 +OP4 E02DC4 0 +OP4 E02DC5 0 +OP4 E02DC6 0 +OP4 E02DC7 0 +OP4 E02DC8 0 +OP4 E02DC9 0 +OP4 E02DCA 0 +OP4 E02DCB 0 +OP4 E02DCC 0 +OP4 E02DCD 0 +OP4 E02DCE 0 +OP4 E02DCF 0 +OP4 E02DD0 0 +OP4 E02DD1 0 +OP4 E02DD2 0 +OP4 E02DD3 0 +OP4 E02DD4 0 +OP4 E02DD5 0 +OP4 E02DD6 0 +OP4 E02DD7 0 +OP4 E02DD8 0 +OP4 E02DD9 0 +OP4 E02DDA 0 +OP4 E02DDB 0 +OP4 E02DDC 0 +OP4 E02DDD 0 +OP4 E02DDE 0 +OP4 E02DDF 0 +OP4 E02DE0 0 +OP4 E02DE1 0 +OP4 E02DE2 0 +OP4 E02DE3 0 +OP4 E02DE4 0 +OP4 E02DE5 0 +OP4 E02DE6 0 +OP4 E02DE7 0 +OP4 E02DE8 0 +OP4 E02DE9 0 +OP4 E02DEA 0 +OP4 E02DEB 0 +OP4 E02DEC 0 +OP4 E02DED 0 +OP4 E02DEE 0 +OP4 E02DEF 0 +OP4 E02DF0 0 +OP4 E02DF1 0 +OP4 E02DF2 0 +OP4 E02DF3 0 +OP4 E02DF4 0 +OP4 E02DF5 0 +OP4 E02DF6 0 +OP4 E02DF7 0 +OP4 E02DF8 0 +OP4 E02DF9 0 +OP4 E02DFA 0 +OP4 E02DFB 0 +OP4 E02DFC 0 +OP4 E02DFD 0 +OP4 E02DFE 0 +OP4 E02DFF 0 +OP4 E02E00 0 +OP4 E02E01 0 +OP4 E02E02 0 +OP4 E02E03 0 +OP4 E02E04 0 +OP4 E02E05 0 +OP4 E02E06 0 +OP4 E02E07 0 +OP4 E02E08 0 +OP4 E02E09 0 +OP4 E02E0A 0 +OP4 E02E0B 0 +OP4 E02E0C 0 +OP4 E02E0D 0 +OP4 E02E0E 0 +OP4 E02E0F 0 +OP4 E02E10 0 +OP4 E02E11 0 +OP4 E02E12 0 +OP4 E02E13 0 +OP4 E02E14 0 +OP4 E02E15 0 +OP4 E02E16 0 +OP4 E02E17 0 +OP4 E02E18 0 +OP4 E02E19 0 +OP4 E02E1A 0 +OP4 E02E1B 0 +OP4 E02E1C 0 +OP4 E02E1D 0 +OP4 E02E1E 0 +OP4 E02E1F 0 +OP4 E02E20 0 +OP4 E02E21 0 +OP4 E02E22 0 +OP4 E02E23 0 +OP4 E02E24 0 +OP4 E02E25 0 +OP4 E02E26 0 +OP4 E02E27 0 +OP4 E02E28 0 +OP4 E02E29 0 +OP4 E02E2A 0 +OP4 E02E2B 0 +OP4 E02E2C 0 +OP4 E02E2D 0 +OP4 E02E2E 0 +OP4 E02E2F 0 +OP4 E02E30 0 +OP4 E02E31 0 +OP4 E02E32 0 +OP4 E02E33 0 +OP4 E02E34 0 +OP4 E02E35 0 +OP4 E02E36 0 +OP4 E02E37 0 +OP4 E02E38 0 +OP4 E02E39 0 +OP4 E02E3A 0 +OP4 E02E3B 0 +OP4 E02E3C 0 +OP4 E02E3D 0 +OP4 E02E3E 0 +OP4 E02E3F 0 +OP4 E02E40 0 +OP4 E02E41 0 +OP4 E02E42 0 +OP4 E02E43 0 +OP4 E02E44 0 +OP4 E02E45 0 +OP4 E02E46 0 +OP4 E02E47 0 +OP4 E02E48 0 +OP4 E02E49 0 +OP4 E02E4A 0 +OP4 E02E4B 0 +OP4 E02E4C 0 +OP4 E02E4D 0 +OP4 E02E4E 0 +OP4 E02E4F 0 +OP4 E02E50 0 +OP4 E02E51 0 +OP4 E02E52 0 +OP4 E02E53 0 +OP4 E02E54 0 +OP4 E02E55 0 +OP4 E02E56 0 +OP4 E02E57 0 +OP4 E02E58 0 +OP4 E02E59 0 +OP4 E02E5A 0 +OP4 E02E5B 0 +OP4 E02E5C 0 +OP4 E02E5D 0 +OP4 E02E5E 0 +OP4 E02E5F 0 +OP4 E02E60 0 +OP4 E02E61 0 +OP4 E02E62 0 +OP4 E02E63 0 +OP4 E02E64 0 +OP4 E02E65 0 +OP4 E02E66 0 +OP4 E02E67 0 +OP4 E02E68 0 +OP4 E02E69 0 +OP4 E02E6A 0 +OP4 E02E6B 0 +OP4 E02E6C 0 +OP4 E02E6D 0 +OP4 E02E6E 0 +OP4 E02E6F 0 +OP4 E02E70 0 +OP4 E02E71 0 +OP4 E02E72 0 +OP4 E02E73 0 +OP4 E02E74 0 +OP4 E02E75 0 +OP4 E02E76 0 +OP4 E02E77 0 +OP4 E02E78 0 +OP4 E02E79 0 +OP4 E02E7A 0 +OP4 E02E7B 0 +OP4 E02E7C 0 +OP4 E02E7D 0 +OP4 E02E7E 0 +OP4 E02E7F 0 +OP4 E02E80 0 +OP4 E02E81 0 +OP4 E02E82 0 +OP4 E02E83 0 +OP4 E02E84 0 +OP4 E02E85 0 +OP4 E02E86 0 +OP4 E02E87 0 +OP4 E02E88 0 +OP4 E02E89 0 +OP4 E02E8A 0 +OP4 E02E8B 0 +OP4 E02E8C 0 +OP4 E02E8D 0 +OP4 E02E8E 0 +OP4 E02E8F 0 +OP4 E02E90 0 +OP4 E02E91 0 +OP4 E02E92 0 +OP4 E02E93 0 +OP4 E02E94 0 +OP4 E02E95 0 +OP4 E02E96 0 +OP4 E02E97 0 +OP4 E02E98 0 +OP4 E02E99 0 +OP4 E02E9A 0 +OP4 E02E9B 0 +OP4 E02E9C 0 +OP4 E02E9D 0 +OP4 E02E9E 0 +OP4 E02E9F 0 +OP4 E02EA0 0 +OP4 E02EA1 0 +OP4 E02EA2 0 +OP4 E02EA3 0 +OP4 E02EA4 0 +OP4 E02EA5 0 +OP4 E02EA6 0 +OP4 E02EA7 0 +OP4 E02EA8 0 +OP4 E02EA9 0 +OP4 E02EAA 0 +OP4 E02EAB 0 +OP4 E02EAC 0 +OP4 E02EAD 0 +OP4 E02EAE 0 +OP4 E02EAF 0 +OP4 E02EB0 0 +OP4 E02EB1 0 +OP4 E02EB2 0 +OP4 E02EB3 0 +OP4 E02EB4 0 +OP4 E02EB5 0 +OP4 E02EB6 0 +OP4 E02EB7 0 +OP4 E02EB8 0 +OP4 E02EB9 0 +OP4 E02EBA 0 +OP4 E02EBB 0 +OP4 E02EBC 0 +OP4 E02EBD 0 +OP4 E02EBE 0 +OP4 E02EBF 0 +OP4 E02EC0 0 +OP4 E02EC1 0 +OP4 E02EC2 0 +OP4 E02EC3 0 +OP4 E02EC4 0 +OP4 E02EC5 0 +OP4 E02EC6 0 +OP4 E02EC7 0 +OP4 E02EC8 0 +OP4 E02EC9 0 +OP4 E02ECA 0 +OP4 E02ECB 0 +OP4 E02ECC 0 +OP4 E02ECD 0 +OP4 E02ECE 0 +OP4 E02ECF 0 +OP4 E02ED0 0 +OP4 E02ED1 0 +OP4 E02ED2 0 +OP4 E02ED3 0 +OP4 E02ED4 0 +OP4 E02ED5 0 +OP4 E02ED6 0 +OP4 E02ED7 0 +OP4 E02ED8 0 +OP4 E02ED9 0 +OP4 E02EDA 0 +OP4 E02EDB 0 +OP4 E02EDC 0 +OP4 E02EDD 0 +OP4 E02EDE 0 +OP4 E02EDF 0 +OP4 E02EE0 0 +OP4 E02EE1 0 +OP4 E02EE2 0 +OP4 E02EE3 0 +OP4 E02EE4 0 +OP4 E02EE5 0 +OP4 E02EE6 0 +OP4 E02EE7 0 +OP4 E02EE8 0 +OP4 E02EE9 0 +OP4 E02EEA 0 +OP4 E02EEB 0 +OP4 E02EEC 0 +OP4 E02EED 0 +OP4 E02EEE 0 +OP4 E02EEF 0 +OP4 E02EF0 0 +OP4 E02EF1 0 +OP4 E02EF2 0 +OP4 E02EF3 0 +OP4 E02EF4 0 +OP4 E02EF5 0 +OP4 E02EF6 0 +OP4 E02EF7 0 +OP4 E02EF8 0 +OP4 E02EF9 0 +OP4 E02EFA 0 +OP4 E02EFB 0 +OP4 E02EFC 0 +OP4 E02EFD 0 +OP4 E02EFE 0 +OP4 E02EFF 0 +OP4 E02F00 0 +OP4 E02F01 0 +OP4 E02F02 0 +OP4 E02F03 0 +OP4 E02F04 0 +OP4 E02F05 0 +OP4 E02F06 0 +OP4 E02F07 0 +OP4 E02F08 0 +OP4 E02F09 0 +OP4 E02F0A 0 +OP4 E02F0B 0 +OP4 E02F0C 0 +OP4 E02F0D 0 +OP4 E02F0E 0 +OP4 E02F0F 0 +OP4 E02F10 0 +OP4 E02F11 0 +OP4 E02F12 0 +OP4 E02F13 0 +OP4 E02F14 0 +OP4 E02F15 0 +OP4 E02F16 0 +OP4 E02F17 0 +OP4 E02F18 0 +OP4 E02F19 0 +OP4 E02F1A 0 +OP4 E02F1B 0 +OP4 E02F1C 0 +OP4 E02F1D 0 +OP4 E02F1E 0 +OP4 E02F1F 0 +OP4 E02F20 0 +OP4 E02F21 0 +OP4 E02F22 0 +OP4 E02F23 0 +OP4 E02F24 0 +OP4 E02F25 0 +OP4 E02F26 0 +OP4 E02F27 0 +OP4 E02F28 0 +OP4 E02F29 0 +OP4 E02F2A 0 +OP4 E02F2B 0 +OP4 E02F2C 0 +OP4 E02F2D 0 +OP4 E02F2E 0 +OP4 E02F2F 0 +OP4 E02F30 0 +OP4 E02F31 0 +OP4 E02F32 0 +OP4 E02F33 0 +OP4 E02F34 0 +OP4 E02F35 0 +OP4 E02F36 0 +OP4 E02F37 0 +OP4 E02F38 0 +OP4 E02F39 0 +OP4 E02F3A 0 +OP4 E02F3B 0 +OP4 E02F3C 0 +OP4 E02F3D 0 +OP4 E02F3E 0 +OP4 E02F3F 0 +OP4 E02F40 0 +OP4 E02F41 0 +OP4 E02F42 0 +OP4 E02F43 0 +OP4 E02F44 0 +OP4 E02F45 0 +OP4 E02F46 0 +OP4 E02F47 0 +OP4 E02F48 0 +OP4 E02F49 0 +OP4 E02F4A 0 +OP4 E02F4B 0 +OP4 E02F4C 0 +OP4 E02F4D 0 +OP4 E02F4E 0 +OP4 E02F4F 0 +OP4 E02F50 0 +OP4 E02F51 0 +OP4 E02F52 0 +OP4 E02F53 0 +OP4 E02F54 0 +OP4 E02F55 0 +OP4 E02F56 0 +OP4 E02F57 0 +OP4 E02F58 0 +OP4 E02F59 0 +OP4 E02F5A 0 +OP4 E02F5B 0 +OP4 E02F5C 0 +OP4 E02F5D 0 +OP4 E02F5E 0 +OP4 E02F5F 0 +OP4 E02F60 0 +OP4 E02F61 0 +OP4 E02F62 0 +OP4 E02F63 0 +OP4 E02F64 0 +OP4 E02F65 0 +OP4 E02F66 0 +OP4 E02F67 0 +OP4 E02F68 0 +OP4 E02F69 0 +OP4 E02F6A 0 +OP4 E02F6B 0 +OP4 E02F6C 0 +OP4 E02F6D 0 +OP4 E02F6E 0 +OP4 E02F6F 0 +OP4 E02F70 0 +OP4 E02F71 0 +OP4 E02F72 0 +OP4 E02F73 0 +OP4 E02F74 0 +OP4 E02F75 0 +OP4 E02F76 0 +OP4 E02F77 0 +OP4 E02F78 0 +OP4 E02F79 0 +OP4 E02F7A 0 +OP4 E02F7B 0 +OP4 E02F7C 0 +OP4 E02F7D 0 +OP4 E02F7E 0 +OP4 E02F7F 0 +OP4 E02F80 0 +OP4 E02F81 0 +OP4 E02F82 0 +OP4 E02F83 0 +OP4 E02F84 0 +OP4 E02F85 0 +OP4 E02F86 0 +OP4 E02F87 0 +OP4 E02F88 0 +OP4 E02F89 0 +OP4 E02F8A 0 +OP4 E02F8B 0 +OP4 E02F8C 0 +OP4 E02F8D 0 +OP4 E02F8E 0 +OP4 E02F8F 0 +OP4 E02F90 0 +OP4 E02F91 0 +OP4 E02F92 0 +OP4 E02F93 0 +OP4 E02F94 0 +OP4 E02F95 0 +OP4 E02F96 0 +OP4 E02F97 0 +OP4 E02F98 0 +OP4 E02F99 0 +OP4 E02F9A 0 +OP4 E02F9B 0 +OP4 E02F9C 0 +OP4 E02F9D 0 +OP4 E02F9E 0 +OP4 E02F9F 0 +OP4 E02FA0 0 +OP4 E02FA1 0 +OP4 E02FA2 0 +OP4 E02FA3 0 +OP4 E02FA4 0 +OP4 E02FA5 0 +OP4 E02FA6 0 +OP4 E02FA7 0 +OP4 E02FA8 0 +OP4 E02FA9 0 +OP4 E02FAA 0 +OP4 E02FAB 0 +OP4 E02FAC 0 +OP4 E02FAD 0 +OP4 E02FAE 0 +OP4 E02FAF 0 +OP4 E02FB0 0 +OP4 E02FB1 0 +OP4 E02FB2 0 +OP4 E02FB3 0 +OP4 E02FB4 0 +OP4 E02FB5 0 +OP4 E02FB6 0 +OP4 E02FB7 0 +OP4 E02FB8 0 +OP4 E02FB9 0 +OP4 E02FBA 0 +OP4 E02FBB 0 +OP4 E02FBC 0 +OP4 E02FBD 0 +OP4 E02FBE 0 +OP4 E02FBF 0 +OP4 E02FC0 0 +OP4 E02FC1 0 +OP4 E02FC2 0 +OP4 E02FC3 0 +OP4 E02FC4 0 +OP4 E02FC5 0 +OP4 E02FC6 0 +OP4 E02FC7 0 +OP4 E02FC8 0 +OP4 E02FC9 0 +OP4 E02FCA 0 +OP4 E02FCB 0 +OP4 E02FCC 0 +OP4 E02FCD 0 +OP4 E02FCE 0 +OP4 E02FCF 0 +OP4 E02FD0 0 +OP4 E02FD1 0 +OP4 E02FD2 0 +OP4 E02FD3 0 +OP4 E02FD4 0 +OP4 E02FD5 0 +OP4 E02FD6 0 +OP4 E02FD7 0 +OP4 E02FD8 0 +OP4 E02FD9 0 +OP4 E02FDA 0 +OP4 E02FDB 0 +OP4 E02FDC 0 +OP4 E02FDD 0 +OP4 E02FDE 0 +OP4 E02FDF 0 +OP4 E02FE0 0 +OP4 E02FE1 0 +OP4 E02FE2 0 +OP4 E02FE3 0 +OP4 E02FE4 0 +OP4 E02FE5 0 +OP4 E02FE6 0 +OP4 E02FE7 0 +OP4 E02FE8 0 +OP4 E02FE9 0 +OP4 E02FEA 0 +OP4 E02FEB 0 +OP4 E02FEC 0 +OP4 E02FED 0 +OP4 E02FEE 0 +OP4 E02FEF 0 +OP4 E02FF0 0 +OP4 E02FF1 0 +OP4 E02FF2 0 +OP4 E02FF3 0 +OP4 E02FF4 0 +OP4 E02FF5 0 +OP4 E02FF6 0 +OP4 E02FF7 0 +OP4 E02FF8 0 +OP4 E02FF9 0 +OP4 E02FFA 0 +OP4 E02FFB 0 +OP4 E02FFC 0 +OP4 E02FFD 0 +OP4 E02FFE 0 +OP4 E02FFF 0 +OP4 E03000 0 +OP4 E03001 0 +OP4 E03002 0 +OP4 E03003 0 +OP4 E03004 0 +OP4 E03005 0 +OP4 E03006 0 +OP4 E03007 0 +OP4 E03008 0 +OP4 E03009 0 +OP4 E0300A 0 +OP4 E0300B 0 +OP4 E0300C 0 +OP4 E0300D 0 +OP4 E0300E 0 +OP4 E0300F 0 +OP4 E03010 0 +OP4 E03011 0 +OP4 E03012 0 +OP4 E03013 0 +OP4 E03014 0 +OP4 E03015 0 +OP4 E03016 0 +OP4 E03017 0 +OP4 E03018 0 +OP4 E03019 0 +OP4 E0301A 0 +OP4 E0301B 0 +OP4 E0301C 0 +OP4 E0301D 0 +OP4 E0301E 0 +OP4 E0301F 0 +OP4 E03020 0 +OP4 E03021 0 +OP4 E03022 0 +OP4 E03023 0 +OP4 E03024 0 +OP4 E03025 0 +OP4 E03026 0 +OP4 E03027 0 +OP4 E03028 0 +OP4 E03029 0 +OP4 E0302A 0 +OP4 E0302B 0 +OP4 E0302C 0 +OP4 E0302D 0 +OP4 E0302E 0 +OP4 E0302F 0 +OP4 E03030 0 +OP4 E03031 0 +OP4 E03032 0 +OP4 E03033 0 +OP4 E03034 0 +OP4 E03035 0 +OP4 E03036 0 +OP4 E03037 0 +OP4 E03038 0 +OP4 E03039 0 +OP4 E0303A 0 +OP4 E0303B 0 +OP4 E0303C 0 +OP4 E0303D 0 +OP4 E0303E 0 +OP4 E0303F 0 +OP4 E03040 0 +OP4 E03041 0 +OP4 E03042 0 +OP4 E03043 0 +OP4 E03044 0 +OP4 E03045 0 +OP4 E03046 0 +OP4 E03047 0 +OP4 E03048 0 +OP4 E03049 0 +OP4 E0304A 0 +OP4 E0304B 0 +OP4 E0304C 0 +OP4 E0304D 0 +OP4 E0304E 0 +OP4 E0304F 0 +OP4 E03050 0 +OP4 E03051 0 +OP4 E03052 0 +OP4 E03053 0 +OP4 E03054 0 +OP4 E03055 0 +OP4 E03056 0 +OP4 E03057 0 +OP4 E03058 0 +OP4 E03059 0 +OP4 E0305A 0 +OP4 E0305B 0 +OP4 E0305C 0 +OP4 E0305D 0 +OP4 E0305E 0 +OP4 E0305F 0 +OP4 E03060 0 +OP4 E03061 0 +OP4 E03062 0 +OP4 E03063 0 +OP4 E03064 0 +OP4 E03065 0 +OP4 E03066 0 +OP4 E03067 0 +OP4 E03068 0 +OP4 E03069 0 +OP4 E0306A 0 +OP4 E0306B 0 +OP4 E0306C 0 +OP4 E0306D 0 +OP4 E0306E 0 +OP4 E0306F 0 +OP4 E03070 0 +OP4 E03071 0 +OP4 E03072 0 +OP4 E03073 0 +OP4 E03074 0 +OP4 E03075 0 +OP4 E03076 0 +OP4 E03077 0 +OP4 E03078 0 +OP4 E03079 0 +OP4 E0307A 0 +OP4 E0307B 0 +OP4 E0307C 0 +OP4 E0307D 0 +OP4 E0307E 0 +OP4 E0307F 0 +OP4 E03080 0 +OP4 E03081 0 +OP4 E03082 0 +OP4 E03083 0 +OP4 E03084 0 +OP4 E03085 0 +OP4 E03086 0 +OP4 E03087 0 +OP4 E03088 0 +OP4 E03089 0 +OP4 E0308A 0 +OP4 E0308B 0 +OP4 E0308C 0 +OP4 E0308D 0 +OP4 E0308E 0 +OP4 E0308F 0 +OP4 E03090 0 +OP4 E03091 0 +OP4 E03092 0 +OP4 E03093 0 +OP4 E03094 0 +OP4 E03095 0 +OP4 E03096 0 +OP4 E03097 0 +OP4 E03098 0 +OP4 E03099 0 +OP4 E0309A 0 +OP4 E0309B 0 +OP4 E0309C 0 +OP4 E0309D 0 +OP4 E0309E 0 +OP4 E0309F 0 +OP4 E030A0 0 +OP4 E030A1 0 +OP4 E030A2 0 +OP4 E030A3 0 +OP4 E030A4 0 +OP4 E030A5 0 +OP4 E030A6 0 +OP4 E030A7 0 +OP4 E030A8 0 +OP4 E030A9 0 +OP4 E030AA 0 +OP4 E030AB 0 +OP4 E030AC 0 +OP4 E030AD 0 +OP4 E030AE 0 +OP4 E030AF 0 +OP4 E030B0 0 +OP4 E030B1 0 +OP4 E030B2 0 +OP4 E030B3 0 +OP4 E030B4 0 +OP4 E030B5 0 +OP4 E030B6 0 +OP4 E030B7 0 +OP4 E030B8 0 +OP4 E030B9 0 +OP4 E030BA 0 +OP4 E030BB 0 +OP4 E030BC 0 +OP4 E030BD 0 +OP4 E030BE 0 +OP4 E030BF 0 +OP4 E030C0 0 +OP4 E030C1 0 +OP4 E030C2 0 +OP4 E030C3 0 +OP4 E030C4 0 +OP4 E030C5 0 +OP4 E030C6 0 +OP4 E030C7 0 +OP4 E030C8 0 +OP4 E030C9 0 +OP4 E030CA 0 +OP4 E030CB 0 +OP4 E030CC 0 +OP4 E030CD 0 +OP4 E030CE 0 +OP4 E030CF 0 +OP4 E030D0 0 +OP4 E030D1 0 +OP4 E030D2 0 +OP4 E030D3 0 +OP4 E030D4 0 +OP4 E030D5 0 +OP4 E030D6 0 +OP4 E030D7 0 +OP4 E030D8 0 +OP4 E030D9 0 +OP4 E030DA 0 +OP4 E030DB 0 +OP4 E030DC 0 +OP4 E030DD 0 +OP4 E030DE 0 +OP4 E030DF 0 +OP4 E030E0 0 +OP4 E030E1 0 +OP4 E030E2 0 +OP4 E030E3 0 +OP4 E030E4 0 +OP4 E030E5 0 +OP4 E030E6 0 +OP4 E030E7 0 +OP4 E030E8 0 +OP4 E030E9 0 +OP4 E030EA 0 +OP4 E030EB 0 +OP4 E030EC 0 +OP4 E030ED 0 +OP4 E030EE 0 +OP4 E030EF 0 +OP4 E030F0 0 +OP4 E030F1 0 +OP4 E030F2 0 +OP4 E030F3 0 +OP4 E030F4 0 +OP4 E030F5 0 +OP4 E030F6 0 +OP4 E030F7 0 +OP4 E030F8 0 +OP4 E030F9 0 +OP4 E030FA 0 +OP4 E030FB 0 +OP4 E030FC 0 +OP4 E030FD 0 +OP4 E030FE 0 +OP4 E030FF 0 +OP4 E03100 0 +OP4 E03101 0 +OP4 E03102 0 +OP4 E03103 0 +OP4 E03104 0 +OP4 E03105 0 +OP4 E03106 0 +OP4 E03107 0 +OP4 E03108 0 +OP4 E03109 0 +OP4 E0310A 0 +OP4 E0310B 0 +OP4 E0310C 0 +OP4 E0310D 0 +OP4 E0310E 0 +OP4 E0310F 0 +OP4 E03110 0 +OP4 E03111 0 +OP4 E03112 0 +OP4 E03113 0 +OP4 E03114 0 +OP4 E03115 0 +OP4 E03116 0 +OP4 E03117 0 +OP4 E03118 0 +OP4 E03119 0 +OP4 E0311A 0 +OP4 E0311B 0 +OP4 E0311C 0 +OP4 E0311D 0 +OP4 E0311E 0 +OP4 E0311F 0 +OP4 E03120 0 +OP4 E03121 0 +OP4 E03122 0 +OP4 E03123 0 +OP4 E03124 0 +OP4 E03125 0 +OP4 E03126 0 +OP4 E03127 0 +OP4 E03128 0 +OP4 E03129 0 +OP4 E0312A 0 +OP4 E0312B 0 +OP4 E0312C 0 +OP4 E0312D 0 +OP4 E0312E 0 +OP4 E0312F 0 +OP4 E03130 0 +OP4 E03131 0 +OP4 E03132 0 +OP4 E03133 0 +OP4 E03134 0 +OP4 E03135 0 +OP4 E03136 0 +OP4 E03137 0 +OP4 E03138 0 +OP4 E03139 0 +OP4 E0313A 0 +OP4 E0313B 0 +OP4 E0313C 0 +OP4 E0313D 0 +OP4 E0313E 0 +OP4 E0313F 0 +OP4 E03140 0 +OP4 E03141 0 +OP4 E03142 0 +OP4 E03143 0 +OP4 E03144 0 +OP4 E03145 0 +OP4 E03146 0 +OP4 E03147 0 +OP4 E03148 0 +OP4 E03149 0 +OP4 E0314A 0 +OP4 E0314B 0 +OP4 E0314C 0 +OP4 E0314D 0 +OP4 E0314E 0 +OP4 E0314F 0 +OP4 E03150 0 +OP4 E03151 0 +OP4 E03152 0 +OP4 E03153 0 +OP4 E03154 0 +OP4 E03155 0 +OP4 E03156 0 +OP4 E03157 0 +OP4 E03158 0 +OP4 E03159 0 +OP4 E0315A 0 +OP4 E0315B 0 +OP4 E0315C 0 +OP4 E0315D 0 +OP4 E0315E 0 +OP4 E0315F 0 +OP4 E03160 0 +OP4 E03161 0 +OP4 E03162 0 +OP4 E03163 0 +OP4 E03164 0 +OP4 E03165 0 +OP4 E03166 0 +OP4 E03167 0 +OP4 E03168 0 +OP4 E03169 0 +OP4 E0316A 0 +OP4 E0316B 0 +OP4 E0316C 0 +OP4 E0316D 0 +OP4 E0316E 0 +OP4 E0316F 0 +OP4 E03170 0 +OP4 E03171 0 +OP4 E03172 0 +OP4 E03173 0 +OP4 E03174 0 +OP4 E03175 0 +OP4 E03176 0 +OP4 E03177 0 +OP4 E03178 0 +OP4 E03179 0 +OP4 E0317A 0 +OP4 E0317B 0 +OP4 E0317C 0 +OP4 E0317D 0 +OP4 E0317E 0 +OP4 E0317F 0 +OP4 E03180 0 +OP4 E03181 0 +OP4 E03182 0 +OP4 E03183 0 +OP4 E03184 0 +OP4 E03185 0 +OP4 E03186 0 +OP4 E03187 0 +OP4 E03188 0 +OP4 E03189 0 +OP4 E0318A 0 +OP4 E0318B 0 +OP4 E0318C 0 +OP4 E0318D 0 +OP4 E0318E 0 +OP4 E0318F 0 +OP4 E03190 0 +OP4 E03191 0 +OP4 E03192 0 +OP4 E03193 0 +OP4 E03194 0 +OP4 E03195 0 +OP4 E03196 0 +OP4 E03197 0 +OP4 E03198 0 +OP4 E03199 0 +OP4 E0319A 0 +OP4 E0319B 0 +OP4 E0319C 0 +OP4 E0319D 0 +OP4 E0319E 0 +OP4 E0319F 0 +OP4 E031A0 0 +OP4 E031A1 0 +OP4 E031A2 0 +OP4 E031A3 0 +OP4 E031A4 0 +OP4 E031A5 0 +OP4 E031A6 0 +OP4 E031A7 0 +OP4 E031A8 0 +OP4 E031A9 0 +OP4 E031AA 0 +OP4 E031AB 0 +OP4 E031AC 0 +OP4 E031AD 0 +OP4 E031AE 0 +OP4 E031AF 0 +OP4 E031B0 0 +OP4 E031B1 0 +OP4 E031B2 0 +OP4 E031B3 0 +OP4 E031B4 0 +OP4 E031B5 0 +OP4 E031B6 0 +OP4 E031B7 0 +OP4 E031B8 0 +OP4 E031B9 0 +OP4 E031BA 0 +OP4 E031BB 0 +OP4 E031BC 0 +OP4 E031BD 0 +OP4 E031BE 0 +OP4 E031BF 0 +OP4 E031C0 0 +OP4 E031C1 0 +OP4 E031C2 0 +OP4 E031C3 0 +OP4 E031C4 0 +OP4 E031C5 0 +OP4 E031C6 0 +OP4 E031C7 0 +OP4 E031C8 0 +OP4 E031C9 0 +OP4 E031CA 0 +OP4 E031CB 0 +OP4 E031CC 0 +OP4 E031CD 0 +OP4 E031CE 0 +OP4 E031CF 0 +OP4 E031D0 0 +OP4 E031D1 0 +OP4 E031D2 0 +OP4 E031D3 0 +OP4 E031D4 0 +OP4 E031D5 0 +OP4 E031D6 0 +OP4 E031D7 0 +OP4 E031D8 0 +OP4 E031D9 0 +OP4 E031DA 0 +OP4 E031DB 0 +OP4 E031DC 0 +OP4 E031DD 0 +OP4 E031DE 0 +OP4 E031DF 0 +OP4 E031E0 0 +OP4 E031E1 0 +OP4 E031E2 0 +OP4 E031E3 0 +OP4 E031E4 0 +OP4 E031E5 0 +OP4 E031E6 0 +OP4 E031E7 0 +OP4 E031E8 0 +OP4 E031E9 0 +OP4 E031EA 0 +OP4 E031EB 0 +OP4 E031EC 0 +OP4 E031ED 0 +OP4 E031EE 0 +OP4 E031EF 0 +OP4 E031F0 0 +OP4 E031F1 0 +OP4 E031F2 0 +OP4 E031F3 0 +OP4 E031F4 0 +OP4 E031F5 0 +OP4 E031F6 0 +OP4 E031F7 0 +OP4 E031F8 0 +OP4 E031F9 0 +OP4 E031FA 0 +OP4 E031FB 0 +OP4 E031FC 0 +OP4 E031FD 0 +OP4 E031FE 0 +OP4 E031FF 0 +OP4 E03200 0 +OP4 E03201 0 +OP4 E03202 0 +OP4 E03203 0 +OP4 E03204 0 +OP4 E03205 0 +OP4 E03206 0 +OP4 E03207 0 +OP4 E03208 0 +OP4 E03209 0 +OP4 E0320A 0 +OP4 E0320B 0 +OP4 E0320C 0 +OP4 E0320D 0 +OP4 E0320E 0 +OP4 E0320F 0 +OP4 E03210 0 +OP4 E03211 0 +OP4 E03212 0 +OP4 E03213 0 +OP4 E03214 0 +OP4 E03215 0 +OP4 E03216 0 +OP4 E03217 0 +OP4 E03218 0 +OP4 E03219 0 +OP4 E0321A 0 +OP4 E0321B 0 +OP4 E0321C 0 +OP4 E0321D 0 +OP4 E0321E 0 +OP4 E0321F 0 +OP4 E03220 0 +OP4 E03221 0 +OP4 E03222 0 +OP4 E03223 0 +OP4 E03224 0 +OP4 E03225 0 +OP4 E03226 0 +OP4 E03227 0 +OP4 E03228 0 +OP4 E03229 0 +OP4 E0322A 0 +OP4 E0322B 0 +OP4 E0322C 0 +OP4 E0322D 0 +OP4 E0322E 0 +OP4 E0322F 0 +OP4 E03230 0 +OP4 E03231 0 +OP4 E03232 0 +OP4 E03233 0 +OP4 E03234 0 +OP4 E03235 0 +OP4 E03236 0 +OP4 E03237 0 +OP4 E03238 0 +OP4 E03239 0 +OP4 E0323A 0 +OP4 E0323B 0 +OP4 E0323C 0 +OP4 E0323D 0 +OP4 E0323E 0 +OP4 E0323F 0 +OP4 E03240 0 +OP4 E03241 0 +OP4 E03242 0 +OP4 E03243 0 +OP4 E03244 0 +OP4 E03245 0 +OP4 E03246 0 +OP4 E03247 0 +OP4 E03248 0 +OP4 E03249 0 +OP4 E0324A 0 +OP4 E0324B 0 +OP4 E0324C 0 +OP4 E0324D 0 +OP4 E0324E 0 +OP4 E0324F 0 +OP4 E03250 0 +OP4 E03251 0 +OP4 E03252 0 +OP4 E03253 0 +OP4 E03254 0 +OP4 E03255 0 +OP4 E03256 0 +OP4 E03257 0 +OP4 E03258 0 +OP4 E03259 0 +OP4 E0325A 0 +OP4 E0325B 0 +OP4 E0325C 0 +OP4 E0325D 0 +OP4 E0325E 0 +OP4 E0325F 0 +OP4 E03260 0 +OP4 E03261 0 +OP4 E03262 0 +OP4 E03263 0 +OP4 E03264 0 +OP4 E03265 0 +OP4 E03266 0 +OP4 E03267 0 +OP4 E03268 0 +OP4 E03269 0 +OP4 E0326A 0 +OP4 E0326B 0 +OP4 E0326C 0 +OP4 E0326D 0 +OP4 E0326E 0 +OP4 E0326F 0 +OP4 E03270 0 +OP4 E03271 0 +OP4 E03272 0 +OP4 E03273 0 +OP4 E03274 0 +OP4 E03275 0 +OP4 E03276 0 +OP4 E03277 0 +OP4 E03278 0 +OP4 E03279 0 +OP4 E0327A 0 +OP4 E0327B 0 +OP4 E0327C 0 +OP4 E0327D 0 +OP4 E0327E 0 +OP4 E0327F 0 +OP4 E03280 0 +OP4 E03281 0 +OP4 E03282 0 +OP4 E03283 0 +OP4 E03284 0 +OP4 E03285 0 +OP4 E03286 0 +OP4 E03287 0 +OP4 E03288 0 +OP4 E03289 0 +OP4 E0328A 0 +OP4 E0328B 0 +OP4 E0328C 0 +OP4 E0328D 0 +OP4 E0328E 0 +OP4 E0328F 0 +OP4 E03290 0 +OP4 E03291 0 +OP4 E03292 0 +OP4 E03293 0 +OP4 E03294 0 +OP4 E03295 0 +OP4 E03296 0 +OP4 E03297 0 +OP4 E03298 0 +OP4 E03299 0 +OP4 E0329A 0 +OP4 E0329B 0 +OP4 E0329C 0 +OP4 E0329D 0 +OP4 E0329E 0 +OP4 E0329F 0 +OP4 E032A0 0 +OP4 E032A1 0 +OP4 E032A2 0 +OP4 E032A3 0 +OP4 E032A4 0 +OP4 E032A5 0 +OP4 E032A6 0 +OP4 E032A7 0 +OP4 E032A8 0 +OP4 E032A9 0 +OP4 E032AA 0 +OP4 E032AB 0 +OP4 E032AC 0 +OP4 E032AD 0 +OP4 E032AE 0 +OP4 E032AF 0 +OP4 E032B0 0 +OP4 E032B1 0 +OP4 E032B2 0 +OP4 E032B3 0 +OP4 E032B4 0 +OP4 E032B5 0 +OP4 E032B6 0 +OP4 E032B7 0 +OP4 E032B8 0 +OP4 E032B9 0 +OP4 E032BA 0 +OP4 E032BB 0 +OP4 E032BC 0 +OP4 E032BD 0 +OP4 E032BE 0 +OP4 E032BF 0 +OP4 E032C0 0 +OP4 E032C1 0 +OP4 E032C2 0 +OP4 E032C3 0 +OP4 E032C4 0 +OP4 E032C5 0 +OP4 E032C6 0 +OP4 E032C7 0 +OP4 E032C8 0 +OP4 E032C9 0 +OP4 E032CA 0 +OP4 E032CB 0 +OP4 E032CC 0 +OP4 E032CD 0 +OP4 E032CE 0 +OP4 E032CF 0 +OP4 E032D0 0 +OP4 E032D1 0 +OP4 E032D2 0 +OP4 E032D3 0 +OP4 E032D4 0 +OP4 E032D5 0 +OP4 E032D6 0 +OP4 E032D7 0 +OP4 E032D8 0 +OP4 E032D9 0 +OP4 E032DA 0 +OP4 E032DB 0 +OP4 E032DC 0 +OP4 E032DD 0 +OP4 E032DE 0 +OP4 E032DF 0 +OP4 E032E0 0 +OP4 E032E1 0 +OP4 E032E2 0 +OP4 E032E3 0 +OP4 E032E4 0 +OP4 E032E5 0 +OP4 E032E6 0 +OP4 E032E7 0 +OP4 E032E8 0 +OP4 E032E9 0 +OP4 E032EA 0 +OP4 E032EB 0 +OP4 E032EC 0 +OP4 E032ED 0 +OP4 E032EE 0 +OP4 E032EF 0 +OP4 E032F0 0 +OP4 E032F1 0 +OP4 E032F2 0 +OP4 E032F3 0 +OP4 E032F4 0 +OP4 E032F5 0 +OP4 E032F6 0 +OP4 E032F7 0 +OP4 E032F8 0 +OP4 E032F9 0 +OP4 E032FA 0 +OP4 E032FB 0 +OP4 E032FC 0 +OP4 E032FD 0 +OP4 E032FE 0 +OP4 E032FF 0 +OP4 E03300 0 +OP4 E03301 0 +OP4 E03302 0 +OP4 E03303 0 +OP4 E03304 0 +OP4 E03305 0 +OP4 E03306 0 +OP4 E03307 0 +OP4 E03308 0 +OP4 E03309 0 +OP4 E0330A 0 +OP4 E0330B 0 +OP4 E0330C 0 +OP4 E0330D 0 +OP4 E0330E 0 +OP4 E0330F 0 +OP4 E03310 0 +OP4 E03311 0 +OP4 E03312 0 +OP4 E03313 0 +OP4 E03314 0 +OP4 E03315 0 +OP4 E03316 0 +OP4 E03317 0 +OP4 E03318 0 +OP4 E03319 0 +OP4 E0331A 0 +OP4 E0331B 0 +OP4 E0331C 0 +OP4 E0331D 0 +OP4 E0331E 0 +OP4 E0331F 0 +OP4 E03320 0 +OP4 E03321 0 +OP4 E03322 0 +OP4 E03323 0 +OP4 E03324 0 +OP4 E03325 0 +OP4 E03326 0 +OP4 E03327 0 +OP4 E03328 0 +OP4 E03329 0 +OP4 E0332A 0 +OP4 E0332B 0 +OP4 E0332C 0 +OP4 E0332D 0 +OP4 E0332E 0 +OP4 E0332F 0 +OP4 E03330 0 +OP4 E03331 0 +OP4 E03332 0 +OP4 E03333 0 +OP4 E03334 0 +OP4 E03335 0 +OP4 E03336 0 +OP4 E03337 0 +OP4 E03338 0 +OP4 E03339 0 +OP4 E0333A 0 +OP4 E0333B 0 +OP4 E0333C 0 +OP4 E0333D 0 +OP4 E0333E 0 +OP4 E0333F 0 +OP4 E03340 0 +OP4 E03341 0 +OP4 E03342 0 +OP4 E03343 0 +OP4 E03344 0 +OP4 E03345 0 +OP4 E03346 0 +OP4 E03347 0 +OP4 E03348 0 +OP4 E03349 0 +OP4 E0334A 0 +OP4 E0334B 0 +OP4 E0334C 0 +OP4 E0334D 0 +OP4 E0334E 0 +OP4 E0334F 0 +OP4 E03350 0 +OP4 E03351 0 +OP4 E03352 0 +OP4 E03353 0 +OP4 E03354 0 +OP4 E03355 0 +OP4 E03356 0 +OP4 E03357 0 +OP4 E03358 0 +OP4 E03359 0 +OP4 E0335A 0 +OP4 E0335B 0 +OP4 E0335C 0 +OP4 E0335D 0 +OP4 E0335E 0 +OP4 E0335F 0 +OP4 E03360 0 +OP4 E03361 0 +OP4 E03362 0 +OP4 E03363 0 +OP4 E03364 0 +OP4 E03365 0 +OP4 E03366 0 +OP4 E03367 0 +OP4 E03368 0 +OP4 E03369 0 +OP4 E0336A 0 +OP4 E0336B 0 +OP4 E0336C 0 +OP4 E0336D 0 +OP4 E0336E 0 +OP4 E0336F 0 +OP4 E03370 0 +OP4 E03371 0 +OP4 E03372 0 +OP4 E03373 0 +OP4 E03374 0 +OP4 E03375 0 +OP4 E03376 0 +OP4 E03377 0 +OP4 E03378 0 +OP4 E03379 0 +OP4 E0337A 0 +OP4 E0337B 0 +OP4 E0337C 0 +OP4 E0337D 0 +OP4 E0337E 0 +OP4 E0337F 0 +OP4 E03380 0 +OP4 E03381 0 +OP4 E03382 0 +OP4 E03383 0 +OP4 E03384 0 +OP4 E03385 0 +OP4 E03386 0 +OP4 E03387 0 +OP4 E03388 0 +OP4 E03389 0 +OP4 E0338A 0 +OP4 E0338B 0 +OP4 E0338C 0 +OP4 E0338D 0 +OP4 E0338E 0 +OP4 E0338F 0 +OP4 E03390 0 +OP4 E03391 0 +OP4 E03392 0 +OP4 E03393 0 +OP4 E03394 0 +OP4 E03395 0 +OP4 E03396 0 +OP4 E03397 0 +OP4 E03398 0 +OP4 E03399 0 +OP4 E0339A 0 +OP4 E0339B 0 +OP4 E0339C 0 +OP4 E0339D 0 +OP4 E0339E 0 +OP4 E0339F 0 +OP4 E033A0 0 +OP4 E033A1 0 +OP4 E033A2 0 +OP4 E033A3 0 +OP4 E033A4 0 +OP4 E033A5 0 +OP4 E033A6 0 +OP4 E033A7 0 +OP4 E033A8 0 +OP4 E033A9 0 +OP4 E033AA 0 +OP4 E033AB 0 +OP4 E033AC 0 +OP4 E033AD 0 +OP4 E033AE 0 +OP4 E033AF 0 +OP4 E033B0 0 +OP4 E033B1 0 +OP4 E033B2 0 +OP4 E033B3 0 +OP4 E033B4 0 +OP4 E033B5 0 +OP4 E033B6 0 +OP4 E033B7 0 +OP4 E033B8 0 +OP4 E033B9 0 +OP4 E033BA 0 +OP4 E033BB 0 +OP4 E033BC 0 +OP4 E033BD 0 +OP4 E033BE 0 +OP4 E033BF 0 +OP4 E033C0 0 +OP4 E033C1 0 +OP4 E033C2 0 +OP4 E033C3 0 +OP4 E033C4 0 +OP4 E033C5 0 +OP4 E033C6 0 +OP4 E033C7 0 +OP4 E033C8 0 +OP4 E033C9 0 +OP4 E033CA 0 +OP4 E033CB 0 +OP4 E033CC 0 +OP4 E033CD 0 +OP4 E033CE 0 +OP4 E033CF 0 +OP4 E033D0 0 +OP4 E033D1 0 +OP4 E033D2 0 +OP4 E033D3 0 +OP4 E033D4 0 +OP4 E033D5 0 +OP4 E033D6 0 +OP4 E033D7 0 +OP4 E033D8 0 +OP4 E033D9 0 +OP4 E033DA 0 +OP4 E033DB 0 +OP4 E033DC 0 +OP4 E033DD 0 +OP4 E033DE 0 +OP4 E033DF 0 +OP4 E033E0 0 +OP4 E033E1 0 +OP4 E033E2 0 +OP4 E033E3 0 +OP4 E033E4 0 +OP4 E033E5 0 +OP4 E033E6 0 +OP4 E033E7 0 +OP4 E033E8 0 +OP4 E033E9 0 +OP4 E033EA 0 +OP4 E033EB 0 +OP4 E033EC 0 +OP4 E033ED 0 +OP4 E033EE 0 +OP4 E033EF 0 +OP4 E033F0 0 +OP4 E033F1 0 +OP4 E033F2 0 +OP4 E033F3 0 +OP4 E033F4 0 +OP4 E033F5 0 +OP4 E033F6 0 +OP4 E033F7 0 +OP4 E033F8 0 +OP4 E033F9 0 +OP4 E033FA 0 +OP4 E033FB 0 +OP4 E033FC 0 +OP4 E033FD 0 +OP4 E033FE 0 +OP4 E033FF 0 +OP4 E03400 0 +OP4 E03401 0 +OP4 E03402 0 +OP4 E03403 0 +OP4 E03404 0 +OP4 E03405 0 +OP4 E03406 0 +OP4 E03407 0 +OP4 E03408 0 +OP4 E03409 0 +OP4 E0340A 0 +OP4 E0340B 0 +OP4 E0340C 0 +OP4 E0340D 0 +OP4 E0340E 0 +OP4 E0340F 0 +OP4 E03410 0 +OP4 E03411 0 +OP4 E03412 0 +OP4 E03413 0 +OP4 E03414 0 +OP4 E03415 0 +OP4 E03416 0 +OP4 E03417 0 +OP4 E03418 0 +OP4 E03419 0 +OP4 E0341A 0 +OP4 E0341B 0 +OP4 E0341C 0 +OP4 E0341D 0 +OP4 E0341E 0 +OP4 E0341F 0 +OP4 E03420 0 +OP4 E03421 0 +OP4 E03422 0 +OP4 E03423 0 +OP4 E03424 0 +OP4 E03425 0 +OP4 E03426 0 +OP4 E03427 0 +OP4 E03428 0 +OP4 E03429 0 +OP4 E0342A 0 +OP4 E0342B 0 +OP4 E0342C 0 +OP4 E0342D 0 +OP4 E0342E 0 +OP4 E0342F 0 +OP4 E03430 0 +OP4 E03431 0 +OP4 E03432 0 +OP4 E03433 0 +OP4 E03434 0 +OP4 E03435 0 +OP4 E03436 0 +OP4 E03437 0 +OP4 E03438 0 +OP4 E03439 0 +OP4 E0343A 0 +OP4 E0343B 0 +OP4 E0343C 0 +OP4 E0343D 0 +OP4 E0343E 0 +OP4 E0343F 0 +OP4 E03440 0 +OP4 E03441 0 +OP4 E03442 0 +OP4 E03443 0 +OP4 E03444 0 +OP4 E03445 0 +OP4 E03446 0 +OP4 E03447 0 +OP4 E03448 0 +OP4 E03449 0 +OP4 E0344A 0 +OP4 E0344B 0 +OP4 E0344C 0 +OP4 E0344D 0 +OP4 E0344E 0 +OP4 E0344F 0 +OP4 E03450 0 +OP4 E03451 0 +OP4 E03452 0 +OP4 E03453 0 +OP4 E03454 0 +OP4 E03455 0 +OP4 E03456 0 +OP4 E03457 0 +OP4 E03458 0 +OP4 E03459 0 +OP4 E0345A 0 +OP4 E0345B 0 +OP4 E0345C 0 +OP4 E0345D 0 +OP4 E0345E 0 +OP4 E0345F 0 +OP4 E03460 0 +OP4 E03461 0 +OP4 E03462 0 +OP4 E03463 0 +OP4 E03464 0 +OP4 E03465 0 +OP4 E03466 0 +OP4 E03467 0 +OP4 E03468 0 +OP4 E03469 0 +OP4 E0346A 0 +OP4 E0346B 0 +OP4 E0346C 0 +OP4 E0346D 0 +OP4 E0346E 0 +OP4 E0346F 0 +OP4 E03470 0 +OP4 E03471 0 +OP4 E03472 0 +OP4 E03473 0 +OP4 E03474 0 +OP4 E03475 0 +OP4 E03476 0 +OP4 E03477 0 +OP4 E03478 0 +OP4 E03479 0 +OP4 E0347A 0 +OP4 E0347B 0 +OP4 E0347C 0 +OP4 E0347D 0 +OP4 E0347E 0 +OP4 E0347F 0 +OP4 E03480 0 +OP4 E03481 0 +OP4 E03482 0 +OP4 E03483 0 +OP4 E03484 0 +OP4 E03485 0 +OP4 E03486 0 +OP4 E03487 0 +OP4 E03488 0 +OP4 E03489 0 +OP4 E0348A 0 +OP4 E0348B 0 +OP4 E0348C 0 +OP4 E0348D 0 +OP4 E0348E 0 +OP4 E0348F 0 +OP4 E03490 0 +OP4 E03491 0 +OP4 E03492 0 +OP4 E03493 0 +OP4 E03494 0 +OP4 E03495 0 +OP4 E03496 0 +OP4 E03497 0 +OP4 E03498 0 +OP4 E03499 0 +OP4 E0349A 0 +OP4 E0349B 0 +OP4 E0349C 0 +OP4 E0349D 0 +OP4 E0349E 0 +OP4 E0349F 0 +OP4 E034A0 0 +OP4 E034A1 0 +OP4 E034A2 0 +OP4 E034A3 0 +OP4 E034A4 0 +OP4 E034A5 0 +OP4 E034A6 0 +OP4 E034A7 0 +OP4 E034A8 0 +OP4 E034A9 0 +OP4 E034AA 0 +OP4 E034AB 0 +OP4 E034AC 0 +OP4 E034AD 0 +OP4 E034AE 0 +OP4 E034AF 0 +OP4 E034B0 0 +OP4 E034B1 0 +OP4 E034B2 0 +OP4 E034B3 0 +OP4 E034B4 0 +OP4 E034B5 0 +OP4 E034B6 0 +OP4 E034B7 0 +OP4 E034B8 0 +OP4 E034B9 0 +OP4 E034BA 0 +OP4 E034BB 0 +OP4 E034BC 0 +OP4 E034BD 0 +OP4 E034BE 0 +OP4 E034BF 0 +OP4 E034C0 0 +OP4 E034C1 0 +OP4 E034C2 0 +OP4 E034C3 0 +OP4 E034C4 0 +OP4 E034C5 0 +OP4 E034C6 0 +OP4 E034C7 0 +OP4 E034C8 0 +OP4 E034C9 0 +OP4 E034CA 0 +OP4 E034CB 0 +OP4 E034CC 0 +OP4 E034CD 0 +OP4 E034CE 0 +OP4 E034CF 0 +OP4 E034D0 0 +OP4 E034D1 0 +OP4 E034D2 0 +OP4 E034D3 0 +OP4 E034D4 0 +OP4 E034D5 0 +OP4 E034D6 0 +OP4 E034D7 0 +OP4 E034D8 0 +OP4 E034D9 0 +OP4 E034DA 0 +OP4 E034DB 0 +OP4 E034DC 0 +OP4 E034DD 0 +OP4 E034DE 0 +OP4 E034DF 0 +OP4 E034E0 0 +OP4 E034E1 0 +OP4 E034E2 0 +OP4 E034E3 0 +OP4 E034E4 0 +OP4 E034E5 0 +OP4 E034E6 0 +OP4 E034E7 0 +OP4 E034E8 0 +OP4 E034E9 0 +OP4 E034EA 0 +OP4 E034EB 0 +OP4 E034EC 0 +OP4 E034ED 0 +OP4 E034EE 0 +OP4 E034EF 0 +OP4 E034F0 0 +OP4 E034F1 0 +OP4 E034F2 0 +OP4 E034F3 0 +OP4 E034F4 0 +OP4 E034F5 0 +OP4 E034F6 0 +OP4 E034F7 0 +OP4 E034F8 0 +OP4 E034F9 0 +OP4 E034FA 0 +OP4 E034FB 0 +OP4 E034FC 0 +OP4 E034FD 0 +OP4 E034FE 0 +OP4 E034FF 0 +OP4 E03500 0 +OP4 E03501 0 +OP4 E03502 0 +OP4 E03503 0 +OP4 E03504 0 +OP4 E03505 0 +OP4 E03506 0 +OP4 E03507 0 +OP4 E03508 0 +OP4 E03509 0 +OP4 E0350A 0 +OP4 E0350B 0 +OP4 E0350C 0 +OP4 E0350D 0 +OP4 E0350E 0 +OP4 E0350F 0 +OP4 E03510 0 +OP4 E03511 0 +OP4 E03512 0 +OP4 E03513 0 +OP4 E03514 0 +OP4 E03515 0 +OP4 E03516 0 +OP4 E03517 0 +OP4 E03518 0 +OP4 E03519 0 +OP4 E0351A 0 +OP4 E0351B 0 +OP4 E0351C 0 +OP4 E0351D 0 +OP4 E0351E 0 +OP4 E0351F 0 +OP4 E03520 0 +OP4 E03521 0 +OP4 E03522 0 +OP4 E03523 0 +OP4 E03524 0 +OP4 E03525 0 +OP4 E03526 0 +OP4 E03527 0 +OP4 E03528 0 +OP4 E03529 0 +OP4 E0352A 0 +OP4 E0352B 0 +OP4 E0352C 0 +OP4 E0352D 0 +OP4 E0352E 0 +OP4 E0352F 0 +OP4 E03530 0 +OP4 E03531 0 +OP4 E03532 0 +OP4 E03533 0 +OP4 E03534 0 +OP4 E03535 0 +OP4 E03536 0 +OP4 E03537 0 +OP4 E03538 0 +OP4 E03539 0 +OP4 E0353A 0 +OP4 E0353B 0 +OP4 E0353C 0 +OP4 E0353D 0 +OP4 E0353E 0 +OP4 E0353F 0 +OP4 E03540 0 +OP4 E03541 0 +OP4 E03542 0 +OP4 E03543 0 +OP4 E03544 0 +OP4 E03545 0 +OP4 E03546 0 +OP4 E03547 0 +OP4 E03548 0 +OP4 E03549 0 +OP4 E0354A 0 +OP4 E0354B 0 +OP4 E0354C 0 +OP4 E0354D 0 +OP4 E0354E 0 +OP4 E0354F 0 +OP4 E03550 0 +OP4 E03551 0 +OP4 E03552 0 +OP4 E03553 0 +OP4 E03554 0 +OP4 E03555 0 +OP4 E03556 0 +OP4 E03557 0 +OP4 E03558 0 +OP4 E03559 0 +OP4 E0355A 0 +OP4 E0355B 0 +OP4 E0355C 0 +OP4 E0355D 0 +OP4 E0355E 0 +OP4 E0355F 0 +OP4 E03560 0 +OP4 E03561 0 +OP4 E03562 0 +OP4 E03563 0 +OP4 E03564 0 +OP4 E03565 0 +OP4 E03566 0 +OP4 E03567 0 +OP4 E03568 0 +OP4 E03569 0 +OP4 E0356A 0 +OP4 E0356B 0 +OP4 E0356C 0 +OP4 E0356D 0 +OP4 E0356E 0 +OP4 E0356F 0 +OP4 E03570 0 +OP4 E03571 0 +OP4 E03572 0 +OP4 E03573 0 +OP4 E03574 0 +OP4 E03575 0 +OP4 E03576 0 +OP4 E03577 0 +OP4 E03578 0 +OP4 E03579 0 +OP4 E0357A 0 +OP4 E0357B 0 +OP4 E0357C 0 +OP4 E0357D 0 +OP4 E0357E 0 +OP4 E0357F 0 +OP4 E03580 0 +OP4 E03581 0 +OP4 E03582 0 +OP4 E03583 0 +OP4 E03584 0 +OP4 E03585 0 +OP4 E03586 0 +OP4 E03587 0 +OP4 E03588 0 +OP4 E03589 0 +OP4 E0358A 0 +OP4 E0358B 0 +OP4 E0358C 0 +OP4 E0358D 0 +OP4 E0358E 0 +OP4 E0358F 0 +OP4 E03590 0 +OP4 E03591 0 +OP4 E03592 0 +OP4 E03593 0 +OP4 E03594 0 +OP4 E03595 0 +OP4 E03596 0 +OP4 E03597 0 +OP4 E03598 0 +OP4 E03599 0 +OP4 E0359A 0 +OP4 E0359B 0 +OP4 E0359C 0 +OP4 E0359D 0 +OP4 E0359E 0 +OP4 E0359F 0 +OP4 E035A0 0 +OP4 E035A1 0 +OP4 E035A2 0 +OP4 E035A3 0 +OP4 E035A4 0 +OP4 E035A5 0 +OP4 E035A6 0 +OP4 E035A7 0 +OP4 E035A8 0 +OP4 E035A9 0 +OP4 E035AA 0 +OP4 E035AB 0 +OP4 E035AC 0 +OP4 E035AD 0 +OP4 E035AE 0 +OP4 E035AF 0 +OP4 E035B0 0 +OP4 E035B1 0 +OP4 E035B2 0 +OP4 E035B3 0 +OP4 E035B4 0 +OP4 E035B5 0 +OP4 E035B6 0 +OP4 E035B7 0 +OP4 E035B8 0 +OP4 E035B9 0 +OP4 E035BA 0 +OP4 E035BB 0 +OP4 E035BC 0 +OP4 E035BD 0 +OP4 E035BE 0 +OP4 E035BF 0 +OP4 E035C0 0 +OP4 E035C1 0 +OP4 E035C2 0 +OP4 E035C3 0 +OP4 E035C4 0 +OP4 E035C5 0 +OP4 E035C6 0 +OP4 E035C7 0 +OP4 E035C8 0 +OP4 E035C9 0 +OP4 E035CA 0 +OP4 E035CB 0 +OP4 E035CC 0 +OP4 E035CD 0 +OP4 E035CE 0 +OP4 E035CF 0 +OP4 E035D0 0 +OP4 E035D1 0 +OP4 E035D2 0 +OP4 E035D3 0 +OP4 E035D4 0 +OP4 E035D5 0 +OP4 E035D6 0 +OP4 E035D7 0 +OP4 E035D8 0 +OP4 E035D9 0 +OP4 E035DA 0 +OP4 E035DB 0 +OP4 E035DC 0 +OP4 E035DD 0 +OP4 E035DE 0 +OP4 E035DF 0 +OP4 E035E0 0 +OP4 E035E1 0 +OP4 E035E2 0 +OP4 E035E3 0 +OP4 E035E4 0 +OP4 E035E5 0 +OP4 E035E6 0 +OP4 E035E7 0 +OP4 E035E8 0 +OP4 E035E9 0 +OP4 E035EA 0 +OP4 E035EB 0 +OP4 E035EC 0 +OP4 E035ED 0 +OP4 E035EE 0 +OP4 E035EF 0 +OP4 E035F0 0 +OP4 E035F1 0 +OP4 E035F2 0 +OP4 E035F3 0 +OP4 E035F4 0 +OP4 E035F5 0 +OP4 E035F6 0 +OP4 E035F7 0 +OP4 E035F8 0 +OP4 E035F9 0 +OP4 E035FA 0 +OP4 E035FB 0 +OP4 E035FC 0 +OP4 E035FD 0 +OP4 E035FE 0 +OP4 E035FF 0 +OP4 E03600 0 +OP4 E03601 0 +OP4 E03602 0 +OP4 E03603 0 +OP4 E03604 0 +OP4 E03605 0 +OP4 E03606 0 +OP4 E03607 0 +OP4 E03608 0 +OP4 E03609 0 +OP4 E0360A 0 +OP4 E0360B 0 +OP4 E0360C 0 +OP4 E0360D 0 +OP4 E0360E 0 +OP4 E0360F 0 +OP4 E03610 0 +OP4 E03611 0 +OP4 E03612 0 +OP4 E03613 0 +OP4 E03614 0 +OP4 E03615 0 +OP4 E03616 0 +OP4 E03617 0 +OP4 E03618 0 +OP4 E03619 0 +OP4 E0361A 0 +OP4 E0361B 0 +OP4 E0361C 0 +OP4 E0361D 0 +OP4 E0361E 0 +OP4 E0361F 0 +OP4 E03620 0 +OP4 E03621 0 +OP4 E03622 0 +OP4 E03623 0 +OP4 E03624 0 +OP4 E03625 0 +OP4 E03626 0 +OP4 E03627 0 +OP4 E03628 0 +OP4 E03629 0 +OP4 E0362A 0 +OP4 E0362B 0 +OP4 E0362C 0 +OP4 E0362D 0 +OP4 E0362E 0 +OP4 E0362F 0 +OP4 E03630 0 +OP4 E03631 0 +OP4 E03632 0 +OP4 E03633 0 +OP4 E03634 0 +OP4 E03635 0 +OP4 E03636 0 +OP4 E03637 0 +OP4 E03638 0 +OP4 E03639 0 +OP4 E0363A 0 +OP4 E0363B 0 +OP4 E0363C 0 +OP4 E0363D 0 +OP4 E0363E 0 +OP4 E0363F 0 +OP4 E03640 0 +OP4 E03641 0 +OP4 E03642 0 +OP4 E03643 0 +OP4 E03644 0 +OP4 E03645 0 +OP4 E03646 0 +OP4 E03647 0 +OP4 E03648 0 +OP4 E03649 0 +OP4 E0364A 0 +OP4 E0364B 0 +OP4 E0364C 0 +OP4 E0364D 0 +OP4 E0364E 0 +OP4 E0364F 0 +OP4 E03650 0 +OP4 E03651 0 +OP4 E03652 0 +OP4 E03653 0 +OP4 E03654 0 +OP4 E03655 0 +OP4 E03656 0 +OP4 E03657 0 +OP4 E03658 0 +OP4 E03659 0 +OP4 E0365A 0 +OP4 E0365B 0 +OP4 E0365C 0 +OP4 E0365D 0 +OP4 E0365E 0 +OP4 E0365F 0 +OP4 E03660 0 +OP4 E03661 0 +OP4 E03662 0 +OP4 E03663 0 +OP4 E03664 0 +OP4 E03665 0 +OP4 E03666 0 +OP4 E03667 0 +OP4 E03668 0 +OP4 E03669 0 +OP4 E0366A 0 +OP4 E0366B 0 +OP4 E0366C 0 +OP4 E0366D 0 +OP4 E0366E 0 +OP4 E0366F 0 +OP4 E03670 0 +OP4 E03671 0 +OP4 E03672 0 +OP4 E03673 0 +OP4 E03674 0 +OP4 E03675 0 +OP4 E03676 0 +OP4 E03677 0 +OP4 E03678 0 +OP4 E03679 0 +OP4 E0367A 0 +OP4 E0367B 0 +OP4 E0367C 0 +OP4 E0367D 0 +OP4 E0367E 0 +OP4 E0367F 0 +OP4 E03680 0 +OP4 E03681 0 +OP4 E03682 0 +OP4 E03683 0 +OP4 E03684 0 +OP4 E03685 0 +OP4 E03686 0 +OP4 E03687 0 +OP4 E03688 0 +OP4 E03689 0 +OP4 E0368A 0 +OP4 E0368B 0 +OP4 E0368C 0 +OP4 E0368D 0 +OP4 E0368E 0 +OP4 E0368F 0 +OP4 E03690 0 +OP4 E03691 0 +OP4 E03692 0 +OP4 E03693 0 +OP4 E03694 0 +OP4 E03695 0 +OP4 E03696 0 +OP4 E03697 0 +OP4 E03698 0 +OP4 E03699 0 +OP4 E0369A 0 +OP4 E0369B 0 +OP4 E0369C 0 +OP4 E0369D 0 +OP4 E0369E 0 +OP4 E0369F 0 +OP4 E036A0 0 +OP4 E036A1 0 +OP4 E036A2 0 +OP4 E036A3 0 +OP4 E036A4 0 +OP4 E036A5 0 +OP4 E036A6 0 +OP4 E036A7 0 +OP4 E036A8 0 +OP4 E036A9 0 +OP4 E036AA 0 +OP4 E036AB 0 +OP4 E036AC 0 +OP4 E036AD 0 +OP4 E036AE 0 +OP4 E036AF 0 +OP4 E036B0 0 +OP4 E036B1 0 +OP4 E036B2 0 +OP4 E036B3 0 +OP4 E036B4 0 +OP4 E036B5 0 +OP4 E036B6 0 +OP4 E036B7 0 +OP4 E036B8 0 +OP4 E036B9 0 +OP4 E036BA 0 +OP4 E036BB 0 +OP4 E036BC 0 +OP4 E036BD 0 +OP4 E036BE 0 +OP4 E036BF 0 +OP4 E036C0 0 +OP4 E036C1 0 +OP4 E036C2 0 +OP4 E036C3 0 +OP4 E036C4 0 +OP4 E036C5 0 +OP4 E036C6 0 +OP4 E036C7 0 +OP4 E036C8 0 +OP4 E036C9 0 +OP4 E036CA 0 +OP4 E036CB 0 +OP4 E036CC 0 +OP4 E036CD 0 +OP4 E036CE 0 +OP4 E036CF 0 +OP4 E036D0 0 +OP4 E036D1 0 +OP4 E036D2 0 +OP4 E036D3 0 +OP4 E036D4 0 +OP4 E036D5 0 +OP4 E036D6 0 +OP4 E036D7 0 +OP4 E036D8 0 +OP4 E036D9 0 +OP4 E036DA 0 +OP4 E036DB 0 +OP4 E036DC 0 +OP4 E036DD 0 +OP4 E036DE 0 +OP4 E036DF 0 +OP4 E036E0 0 +OP4 E036E1 0 +OP4 E036E2 0 +OP4 E036E3 0 +OP4 E036E4 0 +OP4 E036E5 0 +OP4 E036E6 0 +OP4 E036E7 0 +OP4 E036E8 0 +OP4 E036E9 0 +OP4 E036EA 0 +OP4 E036EB 0 +OP4 E036EC 0 +OP4 E036ED 0 +OP4 E036EE 0 +OP4 E036EF 0 +OP4 E036F0 0 +OP4 E036F1 0 +OP4 E036F2 0 +OP4 E036F3 0 +OP4 E036F4 0 +OP4 E036F5 0 +OP4 E036F6 0 +OP4 E036F7 0 +OP4 E036F8 0 +OP4 E036F9 0 +OP4 E036FA 0 +OP4 E036FB 0 +OP4 E036FC 0 +OP4 E036FD 0 +OP4 E036FE 0 +OP4 E036FF 0 +OP4 E03700 0 +OP4 E03701 0 +OP4 E03702 0 +OP4 E03703 0 +OP4 E03704 0 +OP4 E03705 0 +OP4 E03706 0 +OP4 E03707 0 +OP4 E03708 0 +OP4 E03709 0 +OP4 E0370A 0 +OP4 E0370B 0 +OP4 E0370C 0 +OP4 E0370D 0 +OP4 E0370E 0 +OP4 E0370F 0 +OP4 E03710 0 +OP4 E03711 0 +OP4 E03712 0 +OP4 E03713 0 +OP4 E03714 0 +OP4 E03715 0 +OP4 E03716 0 +OP4 E03717 0 +OP4 E03718 0 +OP4 E03719 0 +OP4 E0371A 0 +OP4 E0371B 0 +OP4 E0371C 0 +OP4 E0371D 0 +OP4 E0371E 0 +OP4 E0371F 0 +OP4 E03720 0 +OP4 E03721 0 +OP4 E03722 0 +OP4 E03723 0 +OP4 E03724 0 +OP4 E03725 0 +OP4 E03726 0 +OP4 E03727 0 +OP4 E03728 0 +OP4 E03729 0 +OP4 E0372A 0 +OP4 E0372B 0 +OP4 E0372C 0 +OP4 E0372D 0 +OP4 E0372E 0 +OP4 E0372F 0 +OP4 E03730 0 +OP4 E03731 0 +OP4 E03732 0 +OP4 E03733 0 +OP4 E03734 0 +OP4 E03735 0 +OP4 E03736 0 +OP4 E03737 0 +OP4 E03738 0 +OP4 E03739 0 +OP4 E0373A 0 +OP4 E0373B 0 +OP4 E0373C 0 +OP4 E0373D 0 +OP4 E0373E 0 +OP4 E0373F 0 +OP4 E03740 0 +OP4 E03741 0 +OP4 E03742 0 +OP4 E03743 0 +OP4 E03744 0 +OP4 E03745 0 +OP4 E03746 0 +OP4 E03747 0 +OP4 E03748 0 +OP4 E03749 0 +OP4 E0374A 0 +OP4 E0374B 0 +OP4 E0374C 0 +OP4 E0374D 0 +OP4 E0374E 0 +OP4 E0374F 0 +OP4 E03750 0 +OP4 E03751 0 +OP4 E03752 0 +OP4 E03753 0 +OP4 E03754 0 +OP4 E03755 0 +OP4 E03756 0 +OP4 E03757 0 +OP4 E03758 0 +OP4 E03759 0 +OP4 E0375A 0 +OP4 E0375B 0 +OP4 E0375C 0 +OP4 E0375D 0 +OP4 E0375E 0 +OP4 E0375F 0 +OP4 E03760 0 +OP4 E03761 0 +OP4 E03762 0 +OP4 E03763 0 +OP4 E03764 0 +OP4 E03765 0 +OP4 E03766 0 +OP4 E03767 0 +OP4 E03768 0 +OP4 E03769 0 +OP4 E0376A 0 +OP4 E0376B 0 +OP4 E0376C 0 +OP4 E0376D 0 +OP4 E0376E 0 +OP4 E0376F 0 +OP4 E03770 0 +OP4 E03771 0 +OP4 E03772 0 +OP4 E03773 0 +OP4 E03774 0 +OP4 E03775 0 +OP4 E03776 0 +OP4 E03777 0 +OP4 E03778 0 +OP4 E03779 0 +OP4 E0377A 0 +OP4 E0377B 0 +OP4 E0377C 0 +OP4 E0377D 0 +OP4 E0377E 0 +OP4 E0377F 0 +OP4 E03780 0 +OP4 E03781 0 +OP4 E03782 0 +OP4 E03783 0 +OP4 E03784 0 +OP4 E03785 0 +OP4 E03786 0 +OP4 E03787 0 +OP4 E03788 0 +OP4 E03789 0 +OP4 E0378A 0 +OP4 E0378B 0 +OP4 E0378C 0 +OP4 E0378D 0 +OP4 E0378E 0 +OP4 E0378F 0 +OP4 E03790 0 +OP4 E03791 0 +OP4 E03792 0 +OP4 E03793 0 +OP4 E03794 0 +OP4 E03795 0 +OP4 E03796 0 +OP4 E03797 0 +OP4 E03798 0 +OP4 E03799 0 +OP4 E0379A 0 +OP4 E0379B 0 +OP4 E0379C 0 +OP4 E0379D 0 +OP4 E0379E 0 +OP4 E0379F 0 +OP4 E037A0 0 +OP4 E037A1 0 +OP4 E037A2 0 +OP4 E037A3 0 +OP4 E037A4 0 +OP4 E037A5 0 +OP4 E037A6 0 +OP4 E037A7 0 +OP4 E037A8 0 +OP4 E037A9 0 +OP4 E037AA 0 +OP4 E037AB 0 +OP4 E037AC 0 +OP4 E037AD 0 +OP4 E037AE 0 +OP4 E037AF 0 +OP4 E037B0 0 +OP4 E037B1 0 +OP4 E037B2 0 +OP4 E037B3 0 +OP4 E037B4 0 +OP4 E037B5 0 +OP4 E037B6 0 +OP4 E037B7 0 +OP4 E037B8 0 +OP4 E037B9 0 +OP4 E037BA 0 +OP4 E037BB 0 +OP4 E037BC 0 +OP4 E037BD 0 +OP4 E037BE 0 +OP4 E037BF 0 +OP4 E037C0 0 +OP4 E037C1 0 +OP4 E037C2 0 +OP4 E037C3 0 +OP4 E037C4 0 +OP4 E037C5 0 +OP4 E037C6 0 +OP4 E037C7 0 +OP4 E037C8 0 +OP4 E037C9 0 +OP4 E037CA 0 +OP4 E037CB 0 +OP4 E037CC 0 +OP4 E037CD 0 +OP4 E037CE 0 +OP4 E037CF 0 +OP4 E037D0 0 +OP4 E037D1 0 +OP4 E037D2 0 +OP4 E037D3 0 +OP4 E037D4 0 +OP4 E037D5 0 +OP4 E037D6 0 +OP4 E037D7 0 +OP4 E037D8 0 +OP4 E037D9 0 +OP4 E037DA 0 +OP4 E037DB 0 +OP4 E037DC 0 +OP4 E037DD 0 +OP4 E037DE 0 +OP4 E037DF 0 +OP4 E037E0 0 +OP4 E037E1 0 +OP4 E037E2 0 +OP4 E037E3 0 +OP4 E037E4 0 +OP4 E037E5 0 +OP4 E037E6 0 +OP4 E037E7 0 +OP4 E037E8 0 +OP4 E037E9 0 +OP4 E037EA 0 +OP4 E037EB 0 +OP4 E037EC 0 +OP4 E037ED 0 +OP4 E037EE 0 +OP4 E037EF 0 +OP4 E037F0 0 +OP4 E037F1 0 +OP4 E037F2 0 +OP4 E037F3 0 +OP4 E037F4 0 +OP4 E037F5 0 +OP4 E037F6 0 +OP4 E037F7 0 +OP4 E037F8 0 +OP4 E037F9 0 +OP4 E037FA 0 +OP4 E037FB 0 +OP4 E037FC 0 +OP4 E037FD 0 +OP4 E037FE 0 +OP4 E037FF 0 +OP4 E03800 0 +OP4 E03801 0 +OP4 E03802 0 +OP4 E03803 0 +OP4 E03804 0 +OP4 E03805 0 +OP4 E03806 0 +OP4 E03807 0 +OP4 E03808 0 +OP4 E03809 0 +OP4 E0380A 0 +OP4 E0380B 0 +OP4 E0380C 0 +OP4 E0380D 0 +OP4 E0380E 0 +OP4 E0380F 0 +OP4 E03810 0 +OP4 E03811 0 +OP4 E03812 0 +OP4 E03813 0 +OP4 E03814 0 +OP4 E03815 0 +OP4 E03816 0 +OP4 E03817 0 +OP4 E03818 0 +OP4 E03819 0 +OP4 E0381A 0 +OP4 E0381B 0 +OP4 E0381C 0 +OP4 E0381D 0 +OP4 E0381E 0 +OP4 E0381F 0 +OP4 E03820 0 +OP4 E03821 0 +OP4 E03822 0 +OP4 E03823 0 +OP4 E03824 0 +OP4 E03825 0 +OP4 E03826 0 +OP4 E03827 0 +OP4 E03828 0 +OP4 E03829 0 +OP4 E0382A 0 +OP4 E0382B 0 +OP4 E0382C 0 +OP4 E0382D 0 +OP4 E0382E 0 +OP4 E0382F 0 +OP4 E03830 0 +OP4 E03831 0 +OP4 E03832 0 +OP4 E03833 0 +OP4 E03834 0 +OP4 E03835 0 +OP4 E03836 0 +OP4 E03837 0 +OP4 E03838 0 +OP4 E03839 0 +OP4 E0383A 0 +OP4 E0383B 0 +OP4 E0383C 0 +OP4 E0383D 0 +OP4 E0383E 0 +OP4 E0383F 0 +OP4 E03840 0 +OP4 E03841 0 +OP4 E03842 0 +OP4 E03843 0 +OP4 E03844 0 +OP4 E03845 0 +OP4 E03846 0 +OP4 E03847 0 +OP4 E03848 0 +OP4 E03849 0 +OP4 E0384A 0 +OP4 E0384B 0 +OP4 E0384C 0 +OP4 E0384D 0 +OP4 E0384E 0 +OP4 E0384F 0 +OP4 E03850 0 +OP4 E03851 0 +OP4 E03852 0 +OP4 E03853 0 +OP4 E03854 0 +OP4 E03855 0 +OP4 E03856 0 +OP4 E03857 0 +OP4 E03858 0 +OP4 E03859 0 +OP4 E0385A 0 +OP4 E0385B 0 +OP4 E0385C 0 +OP4 E0385D 0 +OP4 E0385E 0 +OP4 E0385F 0 +OP4 E03860 0 +OP4 E03861 0 +OP4 E03862 0 +OP4 E03863 0 +OP4 E03864 0 +OP4 E03865 0 +OP4 E03866 0 +OP4 E03867 0 +OP4 E03868 0 +OP4 E03869 0 +OP4 E0386A 0 +OP4 E0386B 0 +OP4 E0386C 0 +OP4 E0386D 0 +OP4 E0386E 0 +OP4 E0386F 0 +OP4 E03870 0 +OP4 E03871 0 +OP4 E03872 0 +OP4 E03873 0 +OP4 E03874 0 +OP4 E03875 0 +OP4 E03876 0 +OP4 E03877 0 +OP4 E03878 0 +OP4 E03879 0 +OP4 E0387A 0 +OP4 E0387B 0 +OP4 E0387C 0 +OP4 E0387D 0 +OP4 E0387E 0 +OP4 E0387F 0 +OP4 E03880 0 +OP4 E03881 0 +OP4 E03882 0 +OP4 E03883 0 +OP4 E03884 0 +OP4 E03885 0 +OP4 E03886 0 +OP4 E03887 0 +OP4 E03888 0 +OP4 E03889 0 +OP4 E0388A 0 +OP4 E0388B 0 +OP4 E0388C 0 +OP4 E0388D 0 +OP4 E0388E 0 +OP4 E0388F 0 +OP4 E03890 0 +OP4 E03891 0 +OP4 E03892 0 +OP4 E03893 0 +OP4 E03894 0 +OP4 E03895 0 +OP4 E03896 0 +OP4 E03897 0 +OP4 E03898 0 +OP4 E03899 0 +OP4 E0389A 0 +OP4 E0389B 0 +OP4 E0389C 0 +OP4 E0389D 0 +OP4 E0389E 0 +OP4 E0389F 0 +OP4 E038A0 0 +OP4 E038A1 0 +OP4 E038A2 0 +OP4 E038A3 0 +OP4 E038A4 0 +OP4 E038A5 0 +OP4 E038A6 0 +OP4 E038A7 0 +OP4 E038A8 0 +OP4 E038A9 0 +OP4 E038AA 0 +OP4 E038AB 0 +OP4 E038AC 0 +OP4 E038AD 0 +OP4 E038AE 0 +OP4 E038AF 0 +OP4 E038B0 0 +OP4 E038B1 0 +OP4 E038B2 0 +OP4 E038B3 0 +OP4 E038B4 0 +OP4 E038B5 0 +OP4 E038B6 0 +OP4 E038B7 0 +OP4 E038B8 0 +OP4 E038B9 0 +OP4 E038BA 0 +OP4 E038BB 0 +OP4 E038BC 0 +OP4 E038BD 0 +OP4 E038BE 0 +OP4 E038BF 0 +OP4 E038C0 0 +OP4 E038C1 0 +OP4 E038C2 0 +OP4 E038C3 0 +OP4 E038C4 0 +OP4 E038C5 0 +OP4 E038C6 0 +OP4 E038C7 0 +OP4 E038C8 0 +OP4 E038C9 0 +OP4 E038CA 0 +OP4 E038CB 0 +OP4 E038CC 0 +OP4 E038CD 0 +OP4 E038CE 0 +OP4 E038CF 0 +OP4 E038D0 0 +OP4 E038D1 0 +OP4 E038D2 0 +OP4 E038D3 0 +OP4 E038D4 0 +OP4 E038D5 0 +OP4 E038D6 0 +OP4 E038D7 0 +OP4 E038D8 0 +OP4 E038D9 0 +OP4 E038DA 0 +OP4 E038DB 0 +OP4 E038DC 0 +OP4 E038DD 0 +OP4 E038DE 0 +OP4 E038DF 0 +OP4 E038E0 0 +OP4 E038E1 0 +OP4 E038E2 0 +OP4 E038E3 0 +OP4 E038E4 0 +OP4 E038E5 0 +OP4 E038E6 0 +OP4 E038E7 0 +OP4 E038E8 0 +OP4 E038E9 0 +OP4 E038EA 0 +OP4 E038EB 0 +OP4 E038EC 0 +OP4 E038ED 0 +OP4 E038EE 0 +OP4 E038EF 0 +OP4 E038F0 0 +OP4 E038F1 0 +OP4 E038F2 0 +OP4 E038F3 0 +OP4 E038F4 0 +OP4 E038F5 0 +OP4 E038F6 0 +OP4 E038F7 0 +OP4 E038F8 0 +OP4 E038F9 0 +OP4 E038FA 0 +OP4 E038FB 0 +OP4 E038FC 0 +OP4 E038FD 0 +OP4 E038FE 0 +OP4 E038FF 0 +OP4 E03900 0 +OP4 E03901 0 +OP4 E03902 0 +OP4 E03903 0 +OP4 E03904 0 +OP4 E03905 0 +OP4 E03906 0 +OP4 E03907 0 +OP4 E03908 0 +OP4 E03909 0 +OP4 E0390A 0 +OP4 E0390B 0 +OP4 E0390C 0 +OP4 E0390D 0 +OP4 E0390E 0 +OP4 E0390F 0 +OP4 E03910 0 +OP4 E03911 0 +OP4 E03912 0 +OP4 E03913 0 +OP4 E03914 0 +OP4 E03915 0 +OP4 E03916 0 +OP4 E03917 0 +OP4 E03918 0 +OP4 E03919 0 +OP4 E0391A 0 +OP4 E0391B 0 +OP4 E0391C 0 +OP4 E0391D 0 +OP4 E0391E 0 +OP4 E0391F 0 +OP4 E03920 0 +OP4 E03921 0 +OP4 E03922 0 +OP4 E03923 0 +OP4 E03924 0 +OP4 E03925 0 +OP4 E03926 0 +OP4 E03927 0 +OP4 E03928 0 +OP4 E03929 0 +OP4 E0392A 0 +OP4 E0392B 0 +OP4 E0392C 0 +OP4 E0392D 0 +OP4 E0392E 0 +OP4 E0392F 0 +OP4 E03930 0 +OP4 E03931 0 +OP4 E03932 0 +OP4 E03933 0 +OP4 E03934 0 +OP4 E03935 0 +OP4 E03936 0 +OP4 E03937 0 +OP4 E03938 0 +OP4 E03939 0 +OP4 E0393A 0 +OP4 E0393B 0 +OP4 E0393C 0 +OP4 E0393D 0 +OP4 E0393E 0 +OP4 E0393F 0 +OP4 E03940 0 +OP4 E03941 0 +OP4 E03942 0 +OP4 E03943 0 +OP4 E03944 0 +OP4 E03945 0 +OP4 E03946 0 +OP4 E03947 0 +OP4 E03948 0 +OP4 E03949 0 +OP4 E0394A 0 +OP4 E0394B 0 +OP4 E0394C 0 +OP4 E0394D 0 +OP4 E0394E 0 +OP4 E0394F 0 +OP4 E03950 0 +OP4 E03951 0 +OP4 E03952 0 +OP4 E03953 0 +OP4 E03954 0 +OP4 E03955 0 +OP4 E03956 0 +OP4 E03957 0 +OP4 E03958 0 +OP4 E03959 0 +OP4 E0395A 0 +OP4 E0395B 0 +OP4 E0395C 0 +OP4 E0395D 0 +OP4 E0395E 0 +OP4 E0395F 0 +OP4 E03960 0 +OP4 E03961 0 +OP4 E03962 0 +OP4 E03963 0 +OP4 E03964 0 +OP4 E03965 0 +OP4 E03966 0 +OP4 E03967 0 +OP4 E03968 0 +OP4 E03969 0 +OP4 E0396A 0 +OP4 E0396B 0 +OP4 E0396C 0 +OP4 E0396D 0 +OP4 E0396E 0 +OP4 E0396F 0 +OP4 E03970 0 +OP4 E03971 0 +OP4 E03972 0 +OP4 E03973 0 +OP4 E03974 0 +OP4 E03975 0 +OP4 E03976 0 +OP4 E03977 0 +OP4 E03978 0 +OP4 E03979 0 +OP4 E0397A 0 +OP4 E0397B 0 +OP4 E0397C 0 +OP4 E0397D 0 +OP4 E0397E 0 +OP4 E0397F 0 +OP4 E03980 0 +OP4 E03981 0 +OP4 E03982 0 +OP4 E03983 0 +OP4 E03984 0 +OP4 E03985 0 +OP4 E03986 0 +OP4 E03987 0 +OP4 E03988 0 +OP4 E03989 0 +OP4 E0398A 0 +OP4 E0398B 0 +OP4 E0398C 0 +OP4 E0398D 0 +OP4 E0398E 0 +OP4 E0398F 0 +OP4 E03990 0 +OP4 E03991 0 +OP4 E03992 0 +OP4 E03993 0 +OP4 E03994 0 +OP4 E03995 0 +OP4 E03996 0 +OP4 E03997 0 +OP4 E03998 0 +OP4 E03999 0 +OP4 E0399A 0 +OP4 E0399B 0 +OP4 E0399C 0 +OP4 E0399D 0 +OP4 E0399E 0 +OP4 E0399F 0 +OP4 E039A0 0 +OP4 E039A1 0 +OP4 E039A2 0 +OP4 E039A3 0 +OP4 E039A4 0 +OP4 E039A5 0 +OP4 E039A6 0 +OP4 E039A7 0 +OP4 E039A8 0 +OP4 E039A9 0 +OP4 E039AA 0 +OP4 E039AB 0 +OP4 E039AC 0 +OP4 E039AD 0 +OP4 E039AE 0 +OP4 E039AF 0 +OP4 E039B0 0 +OP4 E039B1 0 +OP4 E039B2 0 +OP4 E039B3 0 +OP4 E039B4 0 +OP4 E039B5 0 +OP4 E039B6 0 +OP4 E039B7 0 +OP4 E039B8 0 +OP4 E039B9 0 +OP4 E039BA 0 +OP4 E039BB 0 +OP4 E039BC 0 +OP4 E039BD 0 +OP4 E039BE 0 +OP4 E039BF 0 +OP4 E039C0 0 +OP4 E039C1 0 +OP4 E039C2 0 +OP4 E039C3 0 +OP4 E039C4 0 +OP4 E039C5 0 +OP4 E039C6 0 +OP4 E039C7 0 +OP4 E039C8 0 +OP4 E039C9 0 +OP4 E039CA 0 +OP4 E039CB 0 +OP4 E039CC 0 +OP4 E039CD 0 +OP4 E039CE 0 +OP4 E039CF 0 +OP4 E039D0 0 +OP4 E039D1 0 +OP4 E039D2 0 +OP4 E039D3 0 +OP4 E039D4 0 +OP4 E039D5 0 +OP4 E039D6 0 +OP4 E039D7 0 +OP4 E039D8 0 +OP4 E039D9 0 +OP4 E039DA 0 +OP4 E039DB 0 +OP4 E039DC 0 +OP4 E039DD 0 +OP4 E039DE 0 +OP4 E039DF 0 +OP4 E039E0 0 +OP4 E039E1 0 +OP4 E039E2 0 +OP4 E039E3 0 +OP4 E039E4 0 +OP4 E039E5 0 +OP4 E039E6 0 +OP4 E039E7 0 +OP4 E039E8 0 +OP4 E039E9 0 +OP4 E039EA 0 +OP4 E039EB 0 +OP4 E039EC 0 +OP4 E039ED 0 +OP4 E039EE 0 +OP4 E039EF 0 +OP4 E039F0 0 +OP4 E039F1 0 +OP4 E039F2 0 +OP4 E039F3 0 +OP4 E039F4 0 +OP4 E039F5 0 +OP4 E039F6 0 +OP4 E039F7 0 +OP4 E039F8 0 +OP4 E039F9 0 +OP4 E039FA 0 +OP4 E039FB 0 +OP4 E039FC 0 +OP4 E039FD 0 +OP4 E039FE 0 +OP4 E039FF 0 +OP4 E03A00 0 +OP4 E03A01 0 +OP4 E03A02 0 +OP4 E03A03 0 +OP4 E03A04 0 +OP4 E03A05 0 +OP4 E03A06 0 +OP4 E03A07 0 +OP4 E03A08 0 +OP4 E03A09 0 +OP4 E03A0A 0 +OP4 E03A0B 0 +OP4 E03A0C 0 +OP4 E03A0D 0 +OP4 E03A0E 0 +OP4 E03A0F 0 +OP4 E03A10 0 +OP4 E03A11 0 +OP4 E03A12 0 +OP4 E03A13 0 +OP4 E03A14 0 +OP4 E03A15 0 +OP4 E03A16 0 +OP4 E03A17 0 +OP4 E03A18 0 +OP4 E03A19 0 +OP4 E03A1A 0 +OP4 E03A1B 0 +OP4 E03A1C 0 +OP4 E03A1D 0 +OP4 E03A1E 0 +OP4 E03A1F 0 +OP4 E03A20 0 +OP4 E03A21 0 +OP4 E03A22 0 +OP4 E03A23 0 +OP4 E03A24 0 +OP4 E03A25 0 +OP4 E03A26 0 +OP4 E03A27 0 +OP4 E03A28 0 +OP4 E03A29 0 +OP4 E03A2A 0 +OP4 E03A2B 0 +OP4 E03A2C 0 +OP4 E03A2D 0 +OP4 E03A2E 0 +OP4 E03A2F 0 +OP4 E03A30 0 +OP4 E03A31 0 +OP4 E03A32 0 +OP4 E03A33 0 +OP4 E03A34 0 +OP4 E03A35 0 +OP4 E03A36 0 +OP4 E03A37 0 +OP4 E03A38 0 +OP4 E03A39 0 +OP4 E03A3A 0 +OP4 E03A3B 0 +OP4 E03A3C 0 +OP4 E03A3D 0 +OP4 E03A3E 0 +OP4 E03A3F 0 +OP4 E03A40 0 +OP4 E03A41 0 +OP4 E03A42 0 +OP4 E03A43 0 +OP4 E03A44 0 +OP4 E03A45 0 +OP4 E03A46 0 +OP4 E03A47 0 +OP4 E03A48 0 +OP4 E03A49 0 +OP4 E03A4A 0 +OP4 E03A4B 0 +OP4 E03A4C 0 +OP4 E03A4D 0 +OP4 E03A4E 0 +OP4 E03A4F 0 +OP4 E03A50 0 +OP4 E03A51 0 +OP4 E03A52 0 +OP4 E03A53 0 +OP4 E03A54 0 +OP4 E03A55 0 +OP4 E03A56 0 +OP4 E03A57 0 +OP4 E03A58 0 +OP4 E03A59 0 +OP4 E03A5A 0 +OP4 E03A5B 0 +OP4 E03A5C 0 +OP4 E03A5D 0 +OP4 E03A5E 0 +OP4 E03A5F 0 +OP4 E03A60 0 +OP4 E03A61 0 +OP4 E03A62 0 +OP4 E03A63 0 +OP4 E03A64 0 +OP4 E03A65 0 +OP4 E03A66 0 +OP4 E03A67 0 +OP4 E03A68 0 +OP4 E03A69 0 +OP4 E03A6A 0 +OP4 E03A6B 0 +OP4 E03A6C 0 +OP4 E03A6D 0 +OP4 E03A6E 0 +OP4 E03A6F 0 +OP4 E03A70 0 +OP4 E03A71 0 +OP4 E03A72 0 +OP4 E03A73 0 +OP4 E03A74 0 +OP4 E03A75 0 +OP4 E03A76 0 +OP4 E03A77 0 +OP4 E03A78 0 +OP4 E03A79 0 +OP4 E03A7A 0 +OP4 E03A7B 0 +OP4 E03A7C 0 +OP4 E03A7D 0 +OP4 E03A7E 0 +OP4 E03A7F 0 +OP4 E03A80 0 +OP4 E03A81 0 +OP4 E03A82 0 +OP4 E03A83 0 +OP4 E03A84 0 +OP4 E03A85 0 +OP4 E03A86 0 +OP4 E03A87 0 +OP4 E03A88 0 +OP4 E03A89 0 +OP4 E03A8A 0 +OP4 E03A8B 0 +OP4 E03A8C 0 +OP4 E03A8D 0 +OP4 E03A8E 0 +OP4 E03A8F 0 +OP4 E03A90 0 +OP4 E03A91 0 +OP4 E03A92 0 +OP4 E03A93 0 +OP4 E03A94 0 +OP4 E03A95 0 +OP4 E03A96 0 +OP4 E03A97 0 +OP4 E03A98 0 +OP4 E03A99 0 +OP4 E03A9A 0 +OP4 E03A9B 0 +OP4 E03A9C 0 +OP4 E03A9D 0 +OP4 E03A9E 0 +OP4 E03A9F 0 +OP4 E03AA0 0 +OP4 E03AA1 0 +OP4 E03AA2 0 +OP4 E03AA3 0 +OP4 E03AA4 0 +OP4 E03AA5 0 +OP4 E03AA6 0 +OP4 E03AA7 0 +OP4 E03AA8 0 +OP4 E03AA9 0 +OP4 E03AAA 0 +OP4 E03AAB 0 +OP4 E03AAC 0 +OP4 E03AAD 0 +OP4 E03AAE 0 +OP4 E03AAF 0 +OP4 E03AB0 0 +OP4 E03AB1 0 +OP4 E03AB2 0 +OP4 E03AB3 0 +OP4 E03AB4 0 +OP4 E03AB5 0 +OP4 E03AB6 0 +OP4 E03AB7 0 +OP4 E03AB8 0 +OP4 E03AB9 0 +OP4 E03ABA 0 +OP4 E03ABB 0 +OP4 E03ABC 0 +OP4 E03ABD 0 +OP4 E03ABE 0 +OP4 E03ABF 0 +OP4 E03AC0 0 +OP4 E03AC1 0 +OP4 E03AC2 0 +OP4 E03AC3 0 +OP4 E03AC4 0 +OP4 E03AC5 0 +OP4 E03AC6 0 +OP4 E03AC7 0 +OP4 E03AC8 0 +OP4 E03AC9 0 +OP4 E03ACA 0 +OP4 E03ACB 0 +OP4 E03ACC 0 +OP4 E03ACD 0 +OP4 E03ACE 0 +OP4 E03ACF 0 +OP4 E03AD0 0 +OP4 E03AD1 0 +OP4 E03AD2 0 +OP4 E03AD3 0 +OP4 E03AD4 0 +OP4 E03AD5 0 +OP4 E03AD6 0 +OP4 E03AD7 0 +OP4 E03AD8 0 +OP4 E03AD9 0 +OP4 E03ADA 0 +OP4 E03ADB 0 +OP4 E03ADC 0 +OP4 E03ADD 0 +OP4 E03ADE 0 +OP4 E03ADF 0 +OP4 E03AE0 0 +OP4 E03AE1 0 +OP4 E03AE2 0 +OP4 E03AE3 0 +OP4 E03AE4 0 +OP4 E03AE5 0 +OP4 E03AE6 0 +OP4 E03AE7 0 +OP4 E03AE8 0 +OP4 E03AE9 0 +OP4 E03AEA 0 +OP4 E03AEB 0 +OP4 E03AEC 0 +OP4 E03AED 0 +OP4 E03AEE 0 +OP4 E03AEF 0 +OP4 E03AF0 0 +OP4 E03AF1 0 +OP4 E03AF2 0 +OP4 E03AF3 0 +OP4 E03AF4 0 +OP4 E03AF5 0 +OP4 E03AF6 0 +OP4 E03AF7 0 +OP4 E03AF8 0 +OP4 E03AF9 0 +OP4 E03AFA 0 +OP4 E03AFB 0 +OP4 E03AFC 0 +OP4 E03AFD 0 +OP4 E03AFE 0 +OP4 E03AFF 0 +OP4 E03B00 0 +OP4 E03B01 0 +OP4 E03B02 0 +OP4 E03B03 0 +OP4 E03B04 0 +OP4 E03B05 0 +OP4 E03B06 0 +OP4 E03B07 0 +OP4 E03B08 0 +OP4 E03B09 0 +OP4 E03B0A 0 +OP4 E03B0B 0 +OP4 E03B0C 0 +OP4 E03B0D 0 +OP4 E03B0E 0 +OP4 E03B0F 0 +OP4 E03B10 0 +OP4 E03B11 0 +OP4 E03B12 0 +OP4 E03B13 0 +OP4 E03B14 0 +OP4 E03B15 0 +OP4 E03B16 0 +OP4 E03B17 0 +OP4 E03B18 0 +OP4 E03B19 0 +OP4 E03B1A 0 +OP4 E03B1B 0 +OP4 E03B1C 0 +OP4 E03B1D 0 +OP4 E03B1E 0 +OP4 E03B1F 0 +OP4 E03B20 0 +OP4 E03B21 0 +OP4 E03B22 0 +OP4 E03B23 0 +OP4 E03B24 0 +OP4 E03B25 0 +OP4 E03B26 0 +OP4 E03B27 0 +OP4 E03B28 0 +OP4 E03B29 0 +OP4 E03B2A 0 +OP4 E03B2B 0 +OP4 E03B2C 0 +OP4 E03B2D 0 +OP4 E03B2E 0 +OP4 E03B2F 0 +OP4 E03B30 0 +OP4 E03B31 0 +OP4 E03B32 0 +OP4 E03B33 0 +OP4 E03B34 0 +OP4 E03B35 0 +OP4 E03B36 0 +OP4 E03B37 0 +OP4 E03B38 0 +OP4 E03B39 0 +OP4 E03B3A 0 +OP4 E03B3B 0 +OP4 E03B3C 0 +OP4 E03B3D 0 +OP4 E03B3E 0 +OP4 E03B3F 0 +OP4 E03B40 0 +OP4 E03B41 0 +OP4 E03B42 0 +OP4 E03B43 0 +OP4 E03B44 0 +OP4 E03B45 0 +OP4 E03B46 0 +OP4 E03B47 0 +OP4 E03B48 0 +OP4 E03B49 0 +OP4 E03B4A 0 +OP4 E03B4B 0 +OP4 E03B4C 0 +OP4 E03B4D 0 +OP4 E03B4E 0 +OP4 E03B4F 0 +OP4 E03B50 0 +OP4 E03B51 0 +OP4 E03B52 0 +OP4 E03B53 0 +OP4 E03B54 0 +OP4 E03B55 0 +OP4 E03B56 0 +OP4 E03B57 0 +OP4 E03B58 0 +OP4 E03B59 0 +OP4 E03B5A 0 +OP4 E03B5B 0 +OP4 E03B5C 0 +OP4 E03B5D 0 +OP4 E03B5E 0 +OP4 E03B5F 0 +OP4 E03B60 0 +OP4 E03B61 0 +OP4 E03B62 0 +OP4 E03B63 0 +OP4 E03B64 0 +OP4 E03B65 0 +OP4 E03B66 0 +OP4 E03B67 0 +OP4 E03B68 0 +OP4 E03B69 0 +OP4 E03B6A 0 +OP4 E03B6B 0 +OP4 E03B6C 0 +OP4 E03B6D 0 +OP4 E03B6E 0 +OP4 E03B6F 0 +OP4 E03B70 0 +OP4 E03B71 0 +OP4 E03B72 0 +OP4 E03B73 0 +OP4 E03B74 0 +OP4 E03B75 0 +OP4 E03B76 0 +OP4 E03B77 0 +OP4 E03B78 0 +OP4 E03B79 0 +OP4 E03B7A 0 +OP4 E03B7B 0 +OP4 E03B7C 0 +OP4 E03B7D 0 +OP4 E03B7E 0 +OP4 E03B7F 0 +OP4 E03B80 0 +OP4 E03B81 0 +OP4 E03B82 0 +OP4 E03B83 0 +OP4 E03B84 0 +OP4 E03B85 0 +OP4 E03B86 0 +OP4 E03B87 0 +OP4 E03B88 0 +OP4 E03B89 0 +OP4 E03B8A 0 +OP4 E03B8B 0 +OP4 E03B8C 0 +OP4 E03B8D 0 +OP4 E03B8E 0 +OP4 E03B8F 0 +OP4 E03B90 0 +OP4 E03B91 0 +OP4 E03B92 0 +OP4 E03B93 0 +OP4 E03B94 0 +OP4 E03B95 0 +OP4 E03B96 0 +OP4 E03B97 0 +OP4 E03B98 0 +OP4 E03B99 0 +OP4 E03B9A 0 +OP4 E03B9B 0 +OP4 E03B9C 0 +OP4 E03B9D 0 +OP4 E03B9E 0 +OP4 E03B9F 0 +OP4 E03BA0 0 +OP4 E03BA1 0 +OP4 E03BA2 0 +OP4 E03BA3 0 +OP4 E03BA4 0 +OP4 E03BA5 0 +OP4 E03BA6 0 +OP4 E03BA7 0 +OP4 E03BA8 0 +OP4 E03BA9 0 +OP4 E03BAA 0 +OP4 E03BAB 0 +OP4 E03BAC 0 +OP4 E03BAD 0 +OP4 E03BAE 0 +OP4 E03BAF 0 +OP4 E03BB0 0 +OP4 E03BB1 0 +OP4 E03BB2 0 +OP4 E03BB3 0 +OP4 E03BB4 0 +OP4 E03BB5 0 +OP4 E03BB6 0 +OP4 E03BB7 0 +OP4 E03BB8 0 +OP4 E03BB9 0 +OP4 E03BBA 0 +OP4 E03BBB 0 +OP4 E03BBC 0 +OP4 E03BBD 0 +OP4 E03BBE 0 +OP4 E03BBF 0 +OP4 E03BC0 0 +OP4 E03BC1 0 +OP4 E03BC2 0 +OP4 E03BC3 0 +OP4 E03BC4 0 +OP4 E03BC5 0 +OP4 E03BC6 0 +OP4 E03BC7 0 +OP4 E03BC8 0 +OP4 E03BC9 0 +OP4 E03BCA 0 +OP4 E03BCB 0 +OP4 E03BCC 0 +OP4 E03BCD 0 +OP4 E03BCE 0 +OP4 E03BCF 0 +OP4 E03BD0 0 +OP4 E03BD1 0 +OP4 E03BD2 0 +OP4 E03BD3 0 +OP4 E03BD4 0 +OP4 E03BD5 0 +OP4 E03BD6 0 +OP4 E03BD7 0 +OP4 E03BD8 0 +OP4 E03BD9 0 +OP4 E03BDA 0 +OP4 E03BDB 0 +OP4 E03BDC 0 +OP4 E03BDD 0 +OP4 E03BDE 0 +OP4 E03BDF 0 +OP4 E03BE0 0 +OP4 E03BE1 0 +OP4 E03BE2 0 +OP4 E03BE3 0 +OP4 E03BE4 0 +OP4 E03BE5 0 +OP4 E03BE6 0 +OP4 E03BE7 0 +OP4 E03BE8 0 +OP4 E03BE9 0 +OP4 E03BEA 0 +OP4 E03BEB 0 +OP4 E03BEC 0 +OP4 E03BED 0 +OP4 E03BEE 0 +OP4 E03BEF 0 +OP4 E03BF0 0 +OP4 E03BF1 0 +OP4 E03BF2 0 +OP4 E03BF3 0 +OP4 E03BF4 0 +OP4 E03BF5 0 +OP4 E03BF6 0 +OP4 E03BF7 0 +OP4 E03BF8 0 +OP4 E03BF9 0 +OP4 E03BFA 0 +OP4 E03BFB 0 +OP4 E03BFC 0 +OP4 E03BFD 0 +OP4 E03BFE 0 +OP4 E03BFF 0 +OP4 E03C00 0 +OP4 E03C01 0 +OP4 E03C02 0 +OP4 E03C03 0 +OP4 E03C04 0 +OP4 E03C05 0 +OP4 E03C06 0 +OP4 E03C07 0 +OP4 E03C08 0 +OP4 E03C09 0 +OP4 E03C0A 0 +OP4 E03C0B 0 +OP4 E03C0C 0 +OP4 E03C0D 0 +OP4 E03C0E 0 +OP4 E03C0F 0 +OP4 E03C10 0 +OP4 E03C11 0 +OP4 E03C12 0 +OP4 E03C13 0 +OP4 E03C14 0 +OP4 E03C15 0 +OP4 E03C16 0 +OP4 E03C17 0 +OP4 E03C18 0 +OP4 E03C19 0 +OP4 E03C1A 0 +OP4 E03C1B 0 +OP4 E03C1C 0 +OP4 E03C1D 0 +OP4 E03C1E 0 +OP4 E03C1F 0 +OP4 E03C20 0 +OP4 E03C21 0 +OP4 E03C22 0 +OP4 E03C23 0 +OP4 E03C24 0 +OP4 E03C25 0 +OP4 E03C26 0 +OP4 E03C27 0 +OP4 E03C28 0 +OP4 E03C29 0 +OP4 E03C2A 0 +OP4 E03C2B 0 +OP4 E03C2C 0 +OP4 E03C2D 0 +OP4 E03C2E 0 +OP4 E03C2F 0 +OP4 E03C30 0 +OP4 E03C31 0 +OP4 E03C32 0 +OP4 E03C33 0 +OP4 E03C34 0 +OP4 E03C35 0 +OP4 E03C36 0 +OP4 E03C37 0 +OP4 E03C38 0 +OP4 E03C39 0 +OP4 E03C3A 0 +OP4 E03C3B 0 +OP4 E03C3C 0 +OP4 E03C3D 0 +OP4 E03C3E 0 +OP4 E03C3F 0 +OP4 E03C40 0 +OP4 E03C41 0 +OP4 E03C42 0 +OP4 E03C43 0 +OP4 E03C44 0 +OP4 E03C45 0 +OP4 E03C46 0 +OP4 E03C47 0 +OP4 E03C48 0 +OP4 E03C49 0 +OP4 E03C4A 0 +OP4 E03C4B 0 +OP4 E03C4C 0 +OP4 E03C4D 0 +OP4 E03C4E 0 +OP4 E03C4F 0 +OP4 E03C50 0 +OP4 E03C51 0 +OP4 E03C52 0 +OP4 E03C53 0 +OP4 E03C54 0 +OP4 E03C55 0 +OP4 E03C56 0 +OP4 E03C57 0 +OP4 E03C58 0 +OP4 E03C59 0 +OP4 E03C5A 0 +OP4 E03C5B 0 +OP4 E03C5C 0 +OP4 E03C5D 0 +OP4 E03C5E 0 +OP4 E03C5F 0 +OP4 E03C60 0 +OP4 E03C61 0 +OP4 E03C62 0 +OP4 E03C63 0 +OP4 E03C64 0 +OP4 E03C65 0 +OP4 E03C66 0 +OP4 E03C67 0 +OP4 E03C68 0 +OP4 E03C69 0 +OP4 E03C6A 0 +OP4 E03C6B 0 +OP4 E03C6C 0 +OP4 E03C6D 0 +OP4 E03C6E 0 +OP4 E03C6F 0 +OP4 E03C70 0 +OP4 E03C71 0 +OP4 E03C72 0 +OP4 E03C73 0 +OP4 E03C74 0 +OP4 E03C75 0 +OP4 E03C76 0 +OP4 E03C77 0 +OP4 E03C78 0 +OP4 E03C79 0 +OP4 E03C7A 0 +OP4 E03C7B 0 +OP4 E03C7C 0 +OP4 E03C7D 0 +OP4 E03C7E 0 +OP4 E03C7F 0 +OP4 E03C80 0 +OP4 E03C81 0 +OP4 E03C82 0 +OP4 E03C83 0 +OP4 E03C84 0 +OP4 E03C85 0 +OP4 E03C86 0 +OP4 E03C87 0 +OP4 E03C88 0 +OP4 E03C89 0 +OP4 E03C8A 0 +OP4 E03C8B 0 +OP4 E03C8C 0 +OP4 E03C8D 0 +OP4 E03C8E 0 +OP4 E03C8F 0 +OP4 E03C90 0 +OP4 E03C91 0 +OP4 E03C92 0 +OP4 E03C93 0 +OP4 E03C94 0 +OP4 E03C95 0 +OP4 E03C96 0 +OP4 E03C97 0 +OP4 E03C98 0 +OP4 E03C99 0 +OP4 E03C9A 0 +OP4 E03C9B 0 +OP4 E03C9C 0 +OP4 E03C9D 0 +OP4 E03C9E 0 +OP4 E03C9F 0 +OP4 E03CA0 0 +OP4 E03CA1 0 +OP4 E03CA2 0 +OP4 E03CA3 0 +OP4 E03CA4 0 +OP4 E03CA5 0 +OP4 E03CA6 0 +OP4 E03CA7 0 +OP4 E03CA8 0 +OP4 E03CA9 0 +OP4 E03CAA 0 +OP4 E03CAB 0 +OP4 E03CAC 0 +OP4 E03CAD 0 +OP4 E03CAE 0 +OP4 E03CAF 0 +OP4 E03CB0 0 +OP4 E03CB1 0 +OP4 E03CB2 0 +OP4 E03CB3 0 +OP4 E03CB4 0 +OP4 E03CB5 0 +OP4 E03CB6 0 +OP4 E03CB7 0 +OP4 E03CB8 0 +OP4 E03CB9 0 +OP4 E03CBA 0 +OP4 E03CBB 0 +OP4 E03CBC 0 +OP4 E03CBD 0 +OP4 E03CBE 0 +OP4 E03CBF 0 +OP4 E03CC0 0 +OP4 E03CC1 0 +OP4 E03CC2 0 +OP4 E03CC3 0 +OP4 E03CC4 0 +OP4 E03CC5 0 +OP4 E03CC6 0 +OP4 E03CC7 0 +OP4 E03CC8 0 +OP4 E03CC9 0 +OP4 E03CCA 0 +OP4 E03CCB 0 +OP4 E03CCC 0 +OP4 E03CCD 0 +OP4 E03CCE 0 +OP4 E03CCF 0 +OP4 E03CD0 0 +OP4 E03CD1 0 +OP4 E03CD2 0 +OP4 E03CD3 0 +OP4 E03CD4 0 +OP4 E03CD5 0 +OP4 E03CD6 0 +OP4 E03CD7 0 +OP4 E03CD8 0 +OP4 E03CD9 0 +OP4 E03CDA 0 +OP4 E03CDB 0 +OP4 E03CDC 0 +OP4 E03CDD 0 +OP4 E03CDE 0 +OP4 E03CDF 0 +OP4 E03CE0 0 +OP4 E03CE1 0 +OP4 E03CE2 0 +OP4 E03CE3 0 +OP4 E03CE4 0 +OP4 E03CE5 0 +OP4 E03CE6 0 +OP4 E03CE7 0 +OP4 E03CE8 0 +OP4 E03CE9 0 +OP4 E03CEA 0 +OP4 E03CEB 0 +OP4 E03CEC 0 +OP4 E03CED 0 +OP4 E03CEE 0 +OP4 E03CEF 0 +OP4 E03CF0 0 +OP4 E03CF1 0 +OP4 E03CF2 0 +OP4 E03CF3 0 +OP4 E03CF4 0 +OP4 E03CF5 0 +OP4 E03CF6 0 +OP4 E03CF7 0 +OP4 E03CF8 0 +OP4 E03CF9 0 +OP4 E03CFA 0 +OP4 E03CFB 0 +OP4 E03CFC 0 +OP4 E03CFD 0 +OP4 E03CFE 0 +OP4 E03CFF 0 +OP4 E03D00 0 +OP4 E03D01 0 +OP4 E03D02 0 +OP4 E03D03 0 +OP4 E03D04 0 +OP4 E03D05 0 +OP4 E03D06 0 +OP4 E03D07 0 +OP4 E03D08 0 +OP4 E03D09 0 +OP4 E03D0A 0 +OP4 E03D0B 0 +OP4 E03D0C 0 +OP4 E03D0D 0 +OP4 E03D0E 0 +OP4 E03D0F 0 +OP4 E03D10 0 +OP4 E03D11 0 +OP4 E03D12 0 +OP4 E03D13 0 +OP4 E03D14 0 +OP4 E03D15 0 +OP4 E03D16 0 +OP4 E03D17 0 +OP4 E03D18 0 +OP4 E03D19 0 +OP4 E03D1A 0 +OP4 E03D1B 0 +OP4 E03D1C 0 +OP4 E03D1D 0 +OP4 E03D1E 0 +OP4 E03D1F 0 +OP4 E03D20 0 +OP4 E03D21 0 +OP4 E03D22 0 +OP4 E03D23 0 +OP4 E03D24 0 +OP4 E03D25 0 +OP4 E03D26 0 +OP4 E03D27 0 +OP4 E03D28 0 +OP4 E03D29 0 +OP4 E03D2A 0 +OP4 E03D2B 0 +OP4 E03D2C 0 +OP4 E03D2D 0 +OP4 E03D2E 0 +OP4 E03D2F 0 +OP4 E03D30 0 +OP4 E03D31 0 +OP4 E03D32 0 +OP4 E03D33 0 +OP4 E03D34 0 +OP4 E03D35 0 +OP4 E03D36 0 +OP4 E03D37 0 +OP4 E03D38 0 +OP4 E03D39 0 +OP4 E03D3A 0 +OP4 E03D3B 0 +OP4 E03D3C 0 +OP4 E03D3D 0 +OP4 E03D3E 0 +OP4 E03D3F 0 +OP4 E03D40 0 +OP4 E03D41 0 +OP4 E03D42 0 +OP4 E03D43 0 +OP4 E03D44 0 +OP4 E03D45 0 +OP4 E03D46 0 +OP4 E03D47 0 +OP4 E03D48 0 +OP4 E03D49 0 +OP4 E03D4A 0 +OP4 E03D4B 0 +OP4 E03D4C 0 +OP4 E03D4D 0 +OP4 E03D4E 0 +OP4 E03D4F 0 +OP4 E03D50 0 +OP4 E03D51 0 +OP4 E03D52 0 +OP4 E03D53 0 +OP4 E03D54 0 +OP4 E03D55 0 +OP4 E03D56 0 +OP4 E03D57 0 +OP4 E03D58 0 +OP4 E03D59 0 +OP4 E03D5A 0 +OP4 E03D5B 0 +OP4 E03D5C 0 +OP4 E03D5D 0 +OP4 E03D5E 0 +OP4 E03D5F 0 +OP4 E03D60 0 +OP4 E03D61 0 +OP4 E03D62 0 +OP4 E03D63 0 +OP4 E03D64 0 +OP4 E03D65 0 +OP4 E03D66 0 +OP4 E03D67 0 +OP4 E03D68 0 +OP4 E03D69 0 +OP4 E03D6A 0 +OP4 E03D6B 0 +OP4 E03D6C 0 +OP4 E03D6D 0 +OP4 E03D6E 0 +OP4 E03D6F 0 +OP4 E03D70 0 +OP4 E03D71 0 +OP4 E03D72 0 +OP4 E03D73 0 +OP4 E03D74 0 +OP4 E03D75 0 +OP4 E03D76 0 +OP4 E03D77 0 +OP4 E03D78 0 +OP4 E03D79 0 +OP4 E03D7A 0 +OP4 E03D7B 0 +OP4 E03D7C 0 +OP4 E03D7D 0 +OP4 E03D7E 0 +OP4 E03D7F 0 +OP4 E03D80 0 +OP4 E03D81 0 +OP4 E03D82 0 +OP4 E03D83 0 +OP4 E03D84 0 +OP4 E03D85 0 +OP4 E03D86 0 +OP4 E03D87 0 +OP4 E03D88 0 +OP4 E03D89 0 +OP4 E03D8A 0 +OP4 E03D8B 0 +OP4 E03D8C 0 +OP4 E03D8D 0 +OP4 E03D8E 0 +OP4 E03D8F 0 +OP4 E03D90 0 +OP4 E03D91 0 +OP4 E03D92 0 +OP4 E03D93 0 +OP4 E03D94 0 +OP4 E03D95 0 +OP4 E03D96 0 +OP4 E03D97 0 +OP4 E03D98 0 +OP4 E03D99 0 +OP4 E03D9A 0 +OP4 E03D9B 0 +OP4 E03D9C 0 +OP4 E03D9D 0 +OP4 E03D9E 0 +OP4 E03D9F 0 +OP4 E03DA0 0 +OP4 E03DA1 0 +OP4 E03DA2 0 +OP4 E03DA3 0 +OP4 E03DA4 0 +OP4 E03DA5 0 +OP4 E03DA6 0 +OP4 E03DA7 0 +OP4 E03DA8 0 +OP4 E03DA9 0 +OP4 E03DAA 0 +OP4 E03DAB 0 +OP4 E03DAC 0 +OP4 E03DAD 0 +OP4 E03DAE 0 +OP4 E03DAF 0 +OP4 E03DB0 0 +OP4 E03DB1 0 +OP4 E03DB2 0 +OP4 E03DB3 0 +OP4 E03DB4 0 +OP4 E03DB5 0 +OP4 E03DB6 0 +OP4 E03DB7 0 +OP4 E03DB8 0 +OP4 E03DB9 0 +OP4 E03DBA 0 +OP4 E03DBB 0 +OP4 E03DBC 0 +OP4 E03DBD 0 +OP4 E03DBE 0 +OP4 E03DBF 0 +OP4 E03DC0 0 +OP4 E03DC1 0 +OP4 E03DC2 0 +OP4 E03DC3 0 +OP4 E03DC4 0 diff --git a/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum4_itrace_irisc0.cfg.ext b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum4_itrace_irisc0.cfg.ext new file mode 100644 index 000000000000..9c46e5549906 --- /dev/null +++ b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum4_itrace_irisc0.cfg.ext @@ -0,0 +1,15814 @@ +OP1 Spectrum4 +OP4 ITRACE0 1 +OP4 ITRACE1 0 +OP4 ITRACE2 0 +OP4 ITRACE3 0 +OP4 ITRACE4 0 +OP4 ITRACE5 0 +OP4 ITRACE6 0 +OP4 ITRACE7 0 +OP4 ITRACE8 0 +OP4 ITRACE9 0 +OP4 Main_PhyUC 0 +OP4 TILE0_ITRACE0 0 +OP4 TILE0_ITRACE1 0 +OP4 TILE0_ITRACE2 0 +OP4 TILE0_ITRACE3 0 +OP4 TILE0_ITRACE4 0 +OP4 TILE0_PhyUC 0 +OP4 TILE1_ITRACE0 0 +OP4 TILE1_ITRACE1 0 +OP4 TILE1_ITRACE2 0 +OP4 TILE1_ITRACE3 0 +OP4 TILE1_ITRACE4 0 +OP4 TILE1_PhyUC 0 +OP4 TILE2_ITRACE0 0 +OP4 TILE2_ITRACE1 0 +OP4 TILE2_ITRACE2 0 +OP4 TILE2_ITRACE3 0 +OP4 TILE2_ITRACE4 0 +OP4 TILE2_PhyUC 0 +OP4 TILE3_ITRACE0 0 +OP4 TILE3_ITRACE1 0 +OP4 TILE3_ITRACE2 0 +OP4 TILE3_ITRACE3 0 +OP4 TILE3_ITRACE4 0 +OP4 TILE3_PhyUC 0 +OP4 TILE4_ITRACE0 0 +OP4 TILE4_ITRACE1 0 +OP4 TILE4_ITRACE2 0 +OP4 TILE4_ITRACE3 0 +OP4 TILE4_ITRACE4 0 +OP4 TILE4_PhyUC 0 +OP4 TILE5_ITRACE0 0 +OP4 TILE5_ITRACE1 0 +OP4 TILE5_ITRACE2 0 +OP4 TILE5_ITRACE3 0 +OP4 TILE5_ITRACE4 0 +OP4 TILE5_PhyUC 0 +OP4 TILE6_ITRACE0 0 +OP4 TILE6_ITRACE1 0 +OP4 TILE6_ITRACE2 0 +OP4 TILE6_ITRACE3 0 +OP4 TILE6_ITRACE4 0 +OP4 TILE6_PhyUC 0 +OP4 TILE7_ITRACE0 0 +OP4 TILE7_ITRACE1 0 +OP4 TILE7_ITRACE2 0 +OP4 TILE7_ITRACE3 0 +OP4 TILE7_ITRACE4 0 +OP4 TILE7_PhyUC 0 +OP4 E0003B 0 +OP4 E0003C 0 +OP4 E0003D 0 +OP4 E0003E 0 +OP4 E0003F 0 +OP4 E00040 0 +OP4 E00041 0 +OP4 E00042 0 +OP4 E00043 0 +OP4 E00044 0 +OP4 E00045 0 +OP4 E00046 0 +OP4 E00047 0 +OP4 E00048 0 +OP4 E00049 0 +OP4 E0004A 0 +OP4 E0004B 0 +OP4 E0004C 0 +OP4 E0004D 0 +OP4 E0004E 0 +OP4 E0004F 0 +OP4 E00050 0 +OP4 E00051 0 +OP4 E00052 0 +OP4 E00053 0 +OP4 E00054 0 +OP4 E00055 0 +OP4 E00056 0 +OP4 E00057 0 +OP4 E00058 0 +OP4 E00059 0 +OP4 E0005A 0 +OP4 E0005B 0 +OP4 E0005C 0 +OP4 E0005D 0 +OP4 E0005E 0 +OP4 E0005F 0 +OP4 E00060 0 +OP4 E00061 0 +OP4 E00062 0 +OP4 E00063 0 +OP4 E00064 0 +OP4 E00065 0 +OP4 E00066 0 +OP4 E00067 0 +OP4 E00068 0 +OP4 E00069 0 +OP4 E0006A 0 +OP4 E0006B 0 +OP4 E0006C 0 +OP4 E0006D 0 +OP4 E0006E 0 +OP4 E0006F 0 +OP4 E00070 0 +OP4 E00071 0 +OP4 E00072 0 +OP4 E00073 0 +OP4 E00074 0 +OP4 E00075 0 +OP4 E00076 0 +OP4 E00077 0 +OP4 E00078 0 +OP4 E00079 0 +OP4 E0007A 0 +OP4 E0007B 0 +OP4 E0007C 0 +OP4 E0007D 0 +OP4 E0007E 0 +OP4 E0007F 0 +OP4 E00080 0 +OP4 E00081 0 +OP4 E00082 0 +OP4 E00083 0 +OP4 E00084 0 +OP4 E00085 0 +OP4 E00086 0 +OP4 E00087 0 +OP4 E00088 0 +OP4 E00089 0 +OP4 E0008A 0 +OP4 E0008B 0 +OP4 E0008C 0 +OP4 E0008D 0 +OP4 E0008E 0 +OP4 E0008F 0 +OP4 E00090 0 +OP4 E00091 0 +OP4 E00092 0 +OP4 E00093 0 +OP4 E00094 0 +OP4 E00095 0 +OP4 E00096 0 +OP4 E00097 0 +OP4 E00098 0 +OP4 E00099 0 +OP4 E0009A 0 +OP4 E0009B 0 +OP4 E0009C 0 +OP4 E0009D 0 +OP4 E0009E 0 +OP4 E0009F 0 +OP4 E000A0 0 +OP4 E000A1 0 +OP4 E000A2 0 +OP4 E000A3 0 +OP4 E000A4 0 +OP4 E000A5 0 +OP4 E000A6 0 +OP4 E000A7 0 +OP4 E000A8 0 +OP4 E000A9 0 +OP4 E000AA 0 +OP4 E000AB 0 +OP4 E000AC 0 +OP4 E000AD 0 +OP4 E000AE 0 +OP4 E000AF 0 +OP4 E000B0 0 +OP4 E000B1 0 +OP4 E000B2 0 +OP4 E000B3 0 +OP4 E000B4 0 +OP4 E000B5 0 +OP4 E000B6 0 +OP4 E000B7 0 +OP4 E000B8 0 +OP4 E000B9 0 +OP4 E000BA 0 +OP4 E000BB 0 +OP4 E000BC 0 +OP4 E000BD 0 +OP4 E000BE 0 +OP4 E000BF 0 +OP4 E000C0 0 +OP4 E000C1 0 +OP4 E000C2 0 +OP4 E000C3 0 +OP4 E000C4 0 +OP4 E000C5 0 +OP4 E000C6 0 +OP4 E000C7 0 +OP4 E000C8 0 +OP4 E000C9 0 +OP4 E000CA 0 +OP4 E000CB 0 +OP4 E000CC 0 +OP4 E000CD 0 +OP4 E000CE 0 +OP4 E000CF 0 +OP4 E000D0 0 +OP4 E000D1 0 +OP4 E000D2 0 +OP4 E000D3 0 +OP4 E000D4 0 +OP4 E000D5 0 +OP4 E000D6 0 +OP4 E000D7 0 +OP4 E000D8 0 +OP4 E000D9 0 +OP4 E000DA 0 +OP4 E000DB 0 +OP4 E000DC 0 +OP4 E000DD 0 +OP4 E000DE 0 +OP4 E000DF 0 +OP4 E000E0 0 +OP4 E000E1 0 +OP4 E000E2 0 +OP4 E000E3 0 +OP4 E000E4 0 +OP4 E000E5 0 +OP4 E000E6 0 +OP4 E000E7 0 +OP4 E000E8 0 +OP4 E000E9 0 +OP4 E000EA 0 +OP4 E000EB 0 +OP4 E000EC 0 +OP4 E000ED 0 +OP4 E000EE 0 +OP4 E000EF 0 +OP4 E000F0 0 +OP4 E000F1 0 +OP4 E000F2 0 +OP4 E000F3 0 +OP4 E000F4 0 +OP4 E000F5 0 +OP4 E000F6 0 +OP4 E000F7 0 +OP4 E000F8 0 +OP4 E000F9 0 +OP4 E000FA 0 +OP4 E000FB 0 +OP4 E000FC 0 +OP4 E000FD 0 +OP4 E000FE 0 +OP4 E000FF 0 +OP4 E00100 0 +OP4 E00101 0 +OP4 E00102 0 +OP4 E00103 0 +OP4 E00104 0 +OP4 E00105 0 +OP4 E00106 0 +OP4 E00107 0 +OP4 E00108 0 +OP4 E00109 0 +OP4 E0010A 0 +OP4 E0010B 0 +OP4 E0010C 0 +OP4 E0010D 0 +OP4 E0010E 0 +OP4 E0010F 0 +OP4 E00110 0 +OP4 E00111 0 +OP4 E00112 0 +OP4 E00113 0 +OP4 E00114 0 +OP4 E00115 0 +OP4 E00116 0 +OP4 E00117 0 +OP4 E00118 0 +OP4 E00119 0 +OP4 E0011A 0 +OP4 E0011B 0 +OP4 E0011C 0 +OP4 E0011D 0 +OP4 E0011E 0 +OP4 E0011F 0 +OP4 E00120 0 +OP4 E00121 0 +OP4 E00122 0 +OP4 E00123 0 +OP4 E00124 0 +OP4 E00125 0 +OP4 E00126 0 +OP4 E00127 0 +OP4 E00128 0 +OP4 E00129 0 +OP4 E0012A 0 +OP4 E0012B 0 +OP4 E0012C 0 +OP4 E0012D 0 +OP4 E0012E 0 +OP4 E0012F 0 +OP4 E00130 0 +OP4 E00131 0 +OP4 E00132 0 +OP4 E00133 0 +OP4 E00134 0 +OP4 E00135 0 +OP4 E00136 0 +OP4 E00137 0 +OP4 E00138 0 +OP4 E00139 0 +OP4 E0013A 0 +OP4 E0013B 0 +OP4 E0013C 0 +OP4 E0013D 0 +OP4 E0013E 0 +OP4 E0013F 0 +OP4 E00140 0 +OP4 E00141 0 +OP4 E00142 0 +OP4 E00143 0 +OP4 E00144 0 +OP4 E00145 0 +OP4 E00146 0 +OP4 E00147 0 +OP4 E00148 0 +OP4 E00149 0 +OP4 E0014A 0 +OP4 E0014B 0 +OP4 E0014C 0 +OP4 E0014D 0 +OP4 E0014E 0 +OP4 E0014F 0 +OP4 E00150 0 +OP4 E00151 0 +OP4 E00152 0 +OP4 E00153 0 +OP4 E00154 0 +OP4 E00155 0 +OP4 E00156 0 +OP4 E00157 0 +OP4 E00158 0 +OP4 E00159 0 +OP4 E0015A 0 +OP4 E0015B 0 +OP4 E0015C 0 +OP4 E0015D 0 +OP4 E0015E 0 +OP4 E0015F 0 +OP4 E00160 0 +OP4 E00161 0 +OP4 E00162 0 +OP4 E00163 0 +OP4 E00164 0 +OP4 E00165 0 +OP4 E00166 0 +OP4 E00167 0 +OP4 E00168 0 +OP4 E00169 0 +OP4 E0016A 0 +OP4 E0016B 0 +OP4 E0016C 0 +OP4 E0016D 0 +OP4 E0016E 0 +OP4 E0016F 0 +OP4 E00170 0 +OP4 E00171 0 +OP4 E00172 0 +OP4 E00173 0 +OP4 E00174 0 +OP4 E00175 0 +OP4 E00176 0 +OP4 E00177 0 +OP4 E00178 0 +OP4 E00179 0 +OP4 E0017A 0 +OP4 E0017B 0 +OP4 E0017C 0 +OP4 E0017D 0 +OP4 E0017E 0 +OP4 E0017F 0 +OP4 E00180 0 +OP4 E00181 0 +OP4 E00182 0 +OP4 E00183 0 +OP4 E00184 0 +OP4 E00185 0 +OP4 E00186 0 +OP4 E00187 0 +OP4 E00188 0 +OP4 E00189 0 +OP4 E0018A 0 +OP4 E0018B 0 +OP4 E0018C 0 +OP4 E0018D 0 +OP4 E0018E 0 +OP4 E0018F 0 +OP4 E00190 0 +OP4 E00191 0 +OP4 E00192 0 +OP4 E00193 0 +OP4 E00194 0 +OP4 E00195 0 +OP4 E00196 0 +OP4 E00197 0 +OP4 E00198 0 +OP4 E00199 0 +OP4 E0019A 0 +OP4 E0019B 0 +OP4 E0019C 0 +OP4 E0019D 0 +OP4 E0019E 0 +OP4 E0019F 0 +OP4 E001A0 0 +OP4 E001A1 0 +OP4 E001A2 0 +OP4 E001A3 0 +OP4 E001A4 0 +OP4 E001A5 0 +OP4 E001A6 0 +OP4 E001A7 0 +OP4 E001A8 0 +OP4 E001A9 0 +OP4 E001AA 0 +OP4 E001AB 0 +OP4 E001AC 0 +OP4 E001AD 0 +OP4 E001AE 0 +OP4 E001AF 0 +OP4 E001B0 0 +OP4 E001B1 0 +OP4 E001B2 0 +OP4 E001B3 0 +OP4 E001B4 0 +OP4 E001B5 0 +OP4 E001B6 0 +OP4 E001B7 0 +OP4 E001B8 0 +OP4 E001B9 0 +OP4 E001BA 0 +OP4 E001BB 0 +OP4 E001BC 0 +OP4 E001BD 0 +OP4 E001BE 0 +OP4 E001BF 0 +OP4 E001C0 0 +OP4 E001C1 0 +OP4 E001C2 0 +OP4 E001C3 0 +OP4 E001C4 0 +OP4 E001C5 0 +OP4 E001C6 0 +OP4 E001C7 0 +OP4 E001C8 0 +OP4 E001C9 0 +OP4 E001CA 0 +OP4 E001CB 0 +OP4 E001CC 0 +OP4 E001CD 0 +OP4 E001CE 0 +OP4 E001CF 0 +OP4 E001D0 0 +OP4 E001D1 0 +OP4 E001D2 0 +OP4 E001D3 0 +OP4 E001D4 0 +OP4 E001D5 0 +OP4 E001D6 0 +OP4 E001D7 0 +OP4 E001D8 0 +OP4 E001D9 0 +OP4 E001DA 0 +OP4 E001DB 0 +OP4 E001DC 0 +OP4 E001DD 0 +OP4 E001DE 0 +OP4 E001DF 0 +OP4 E001E0 0 +OP4 E001E1 0 +OP4 E001E2 0 +OP4 E001E3 0 +OP4 E001E4 0 +OP4 E001E5 0 +OP4 E001E6 0 +OP4 E001E7 0 +OP4 E001E8 0 +OP4 E001E9 0 +OP4 E001EA 0 +OP4 E001EB 0 +OP4 E001EC 0 +OP4 E001ED 0 +OP4 E001EE 0 +OP4 E001EF 0 +OP4 E001F0 0 +OP4 E001F1 0 +OP4 E001F2 0 +OP4 E001F3 0 +OP4 E001F4 0 +OP4 E001F5 0 +OP4 E001F6 0 +OP4 E001F7 0 +OP4 E001F8 0 +OP4 E001F9 0 +OP4 E001FA 0 +OP4 E001FB 0 +OP4 E001FC 0 +OP4 E001FD 0 +OP4 E001FE 0 +OP4 E001FF 0 +OP4 E00200 0 +OP4 E00201 0 +OP4 E00202 0 +OP4 E00203 0 +OP4 E00204 0 +OP4 E00205 0 +OP4 E00206 0 +OP4 E00207 0 +OP4 E00208 0 +OP4 E00209 0 +OP4 E0020A 0 +OP4 E0020B 0 +OP4 E0020C 0 +OP4 E0020D 0 +OP4 E0020E 0 +OP4 E0020F 0 +OP4 E00210 0 +OP4 E00211 0 +OP4 E00212 0 +OP4 E00213 0 +OP4 E00214 0 +OP4 E00215 0 +OP4 E00216 0 +OP4 E00217 0 +OP4 E00218 0 +OP4 E00219 0 +OP4 E0021A 0 +OP4 E0021B 0 +OP4 E0021C 0 +OP4 E0021D 0 +OP4 E0021E 0 +OP4 E0021F 0 +OP4 E00220 0 +OP4 E00221 0 +OP4 E00222 0 +OP4 E00223 0 +OP4 E00224 0 +OP4 E00225 0 +OP4 E00226 0 +OP4 E00227 0 +OP4 E00228 0 +OP4 E00229 0 +OP4 E0022A 0 +OP4 E0022B 0 +OP4 E0022C 0 +OP4 E0022D 0 +OP4 E0022E 0 +OP4 E0022F 0 +OP4 E00230 0 +OP4 E00231 0 +OP4 E00232 0 +OP4 E00233 0 +OP4 E00234 0 +OP4 E00235 0 +OP4 E00236 0 +OP4 E00237 0 +OP4 E00238 0 +OP4 E00239 0 +OP4 E0023A 0 +OP4 E0023B 0 +OP4 E0023C 0 +OP4 E0023D 0 +OP4 E0023E 0 +OP4 E0023F 0 +OP4 E00240 0 +OP4 E00241 0 +OP4 E00242 0 +OP4 E00243 0 +OP4 E00244 0 +OP4 E00245 0 +OP4 E00246 0 +OP4 E00247 0 +OP4 E00248 0 +OP4 E00249 0 +OP4 E0024A 0 +OP4 E0024B 0 +OP4 E0024C 0 +OP4 E0024D 0 +OP4 E0024E 0 +OP4 E0024F 0 +OP4 E00250 0 +OP4 E00251 0 +OP4 E00252 0 +OP4 E00253 0 +OP4 E00254 0 +OP4 E00255 0 +OP4 E00256 0 +OP4 E00257 0 +OP4 E00258 0 +OP4 E00259 0 +OP4 E0025A 0 +OP4 E0025B 0 +OP4 E0025C 0 +OP4 E0025D 0 +OP4 E0025E 0 +OP4 E0025F 0 +OP4 E00260 0 +OP4 E00261 0 +OP4 E00262 0 +OP4 E00263 0 +OP4 E00264 0 +OP4 E00265 0 +OP4 E00266 0 +OP4 E00267 0 +OP4 E00268 0 +OP4 E00269 0 +OP4 E0026A 0 +OP4 E0026B 0 +OP4 E0026C 0 +OP4 E0026D 0 +OP4 E0026E 0 +OP4 E0026F 0 +OP4 E00270 0 +OP4 E00271 0 +OP4 E00272 0 +OP4 E00273 0 +OP4 E00274 0 +OP4 E00275 0 +OP4 E00276 0 +OP4 E00277 0 +OP4 E00278 0 +OP4 E00279 0 +OP4 E0027A 0 +OP4 E0027B 0 +OP4 E0027C 0 +OP4 E0027D 0 +OP4 E0027E 0 +OP4 E0027F 0 +OP4 E00280 0 +OP4 E00281 0 +OP4 E00282 0 +OP4 E00283 0 +OP4 E00284 0 +OP4 E00285 0 +OP4 E00286 0 +OP4 E00287 0 +OP4 E00288 0 +OP4 E00289 0 +OP4 E0028A 0 +OP4 E0028B 0 +OP4 E0028C 0 +OP4 E0028D 0 +OP4 E0028E 0 +OP4 E0028F 0 +OP4 E00290 0 +OP4 E00291 0 +OP4 E00292 0 +OP4 E00293 0 +OP4 E00294 0 +OP4 E00295 0 +OP4 E00296 0 +OP4 E00297 0 +OP4 E00298 0 +OP4 E00299 0 +OP4 E0029A 0 +OP4 E0029B 0 +OP4 E0029C 0 +OP4 E0029D 0 +OP4 E0029E 0 +OP4 E0029F 0 +OP4 E002A0 0 +OP4 E002A1 0 +OP4 E002A2 0 +OP4 E002A3 0 +OP4 E002A4 0 +OP4 E002A5 0 +OP4 E002A6 0 +OP4 E002A7 0 +OP4 E002A8 0 +OP4 E002A9 0 +OP4 E002AA 0 +OP4 E002AB 0 +OP4 E002AC 0 +OP4 E002AD 0 +OP4 E002AE 0 +OP4 E002AF 0 +OP4 E002B0 0 +OP4 E002B1 0 +OP4 E002B2 0 +OP4 E002B3 0 +OP4 E002B4 0 +OP4 E002B5 0 +OP4 E002B6 0 +OP4 E002B7 0 +OP4 E002B8 0 +OP4 E002B9 0 +OP4 E002BA 0 +OP4 E002BB 0 +OP4 E002BC 0 +OP4 E002BD 0 +OP4 E002BE 0 +OP4 E002BF 0 +OP4 E002C0 0 +OP4 E002C1 0 +OP4 E002C2 0 +OP4 E002C3 0 +OP4 E002C4 0 +OP4 E002C5 0 +OP4 E002C6 0 +OP4 E002C7 0 +OP4 E002C8 0 +OP4 E002C9 0 +OP4 E002CA 0 +OP4 E002CB 0 +OP4 E002CC 0 +OP4 E002CD 0 +OP4 E002CE 0 +OP4 E002CF 0 +OP4 E002D0 0 +OP4 E002D1 0 +OP4 E002D2 0 +OP4 E002D3 0 +OP4 E002D4 0 +OP4 E002D5 0 +OP4 E002D6 0 +OP4 E002D7 0 +OP4 E002D8 0 +OP4 E002D9 0 +OP4 E002DA 0 +OP4 E002DB 0 +OP4 E002DC 0 +OP4 E002DD 0 +OP4 E002DE 0 +OP4 E002DF 0 +OP4 E002E0 0 +OP4 E002E1 0 +OP4 E002E2 0 +OP4 E002E3 0 +OP4 E002E4 0 +OP4 E002E5 0 +OP4 E002E6 0 +OP4 E002E7 0 +OP4 E002E8 0 +OP4 E002E9 0 +OP4 E002EA 0 +OP4 E002EB 0 +OP4 E002EC 0 +OP4 E002ED 0 +OP4 E002EE 0 +OP4 E002EF 0 +OP4 E002F0 0 +OP4 E002F1 0 +OP4 E002F2 0 +OP4 E002F3 0 +OP4 E002F4 0 +OP4 E002F5 0 +OP4 E002F6 0 +OP4 E002F7 0 +OP4 E002F8 0 +OP4 E002F9 0 +OP4 E002FA 0 +OP4 E002FB 0 +OP4 E002FC 0 +OP4 E002FD 0 +OP4 E002FE 0 +OP4 E002FF 0 +OP4 E00300 0 +OP4 E00301 0 +OP4 E00302 0 +OP4 E00303 0 +OP4 E00304 0 +OP4 E00305 0 +OP4 E00306 0 +OP4 E00307 0 +OP4 E00308 0 +OP4 E00309 0 +OP4 E0030A 0 +OP4 E0030B 0 +OP4 E0030C 0 +OP4 E0030D 0 +OP4 E0030E 0 +OP4 E0030F 0 +OP4 E00310 0 +OP4 E00311 0 +OP4 E00312 0 +OP4 E00313 0 +OP4 E00314 0 +OP4 E00315 0 +OP4 E00316 0 +OP4 E00317 0 +OP4 E00318 0 +OP4 E00319 0 +OP4 E0031A 0 +OP4 E0031B 0 +OP4 E0031C 0 +OP4 E0031D 0 +OP4 E0031E 0 +OP4 E0031F 0 +OP4 E00320 0 +OP4 E00321 0 +OP4 E00322 0 +OP4 E00323 0 +OP4 E00324 0 +OP4 E00325 0 +OP4 E00326 0 +OP4 E00327 0 +OP4 E00328 0 +OP4 E00329 0 +OP4 E0032A 0 +OP4 E0032B 0 +OP4 E0032C 0 +OP4 E0032D 0 +OP4 E0032E 0 +OP4 E0032F 0 +OP4 E00330 0 +OP4 E00331 0 +OP4 E00332 0 +OP4 E00333 0 +OP4 E00334 0 +OP4 E00335 0 +OP4 E00336 0 +OP4 E00337 0 +OP4 E00338 0 +OP4 E00339 0 +OP4 E0033A 0 +OP4 E0033B 0 +OP4 E0033C 0 +OP4 E0033D 0 +OP4 E0033E 0 +OP4 E0033F 0 +OP4 E00340 0 +OP4 E00341 0 +OP4 E00342 0 +OP4 E00343 0 +OP4 E00344 0 +OP4 E00345 0 +OP4 E00346 0 +OP4 E00347 0 +OP4 E00348 0 +OP4 E00349 0 +OP4 E0034A 0 +OP4 E0034B 0 +OP4 E0034C 0 +OP4 E0034D 0 +OP4 E0034E 0 +OP4 E0034F 0 +OP4 E00350 0 +OP4 E00351 0 +OP4 E00352 0 +OP4 E00353 0 +OP4 E00354 0 +OP4 E00355 0 +OP4 E00356 0 +OP4 E00357 0 +OP4 E00358 0 +OP4 E00359 0 +OP4 E0035A 0 +OP4 E0035B 0 +OP4 E0035C 0 +OP4 E0035D 0 +OP4 E0035E 0 +OP4 E0035F 0 +OP4 E00360 0 +OP4 E00361 0 +OP4 E00362 0 +OP4 E00363 0 +OP4 E00364 0 +OP4 E00365 0 +OP4 E00366 0 +OP4 E00367 0 +OP4 E00368 0 +OP4 E00369 0 +OP4 E0036A 0 +OP4 E0036B 0 +OP4 E0036C 0 +OP4 E0036D 0 +OP4 E0036E 0 +OP4 E0036F 0 +OP4 E00370 0 +OP4 E00371 0 +OP4 E00372 0 +OP4 E00373 0 +OP4 E00374 0 +OP4 E00375 0 +OP4 E00376 0 +OP4 E00377 0 +OP4 E00378 0 +OP4 E00379 0 +OP4 E0037A 0 +OP4 E0037B 0 +OP4 E0037C 0 +OP4 E0037D 0 +OP4 E0037E 0 +OP4 E0037F 0 +OP4 E00380 0 +OP4 E00381 0 +OP4 E00382 0 +OP4 E00383 0 +OP4 E00384 0 +OP4 E00385 0 +OP4 E00386 0 +OP4 E00387 0 +OP4 E00388 0 +OP4 E00389 0 +OP4 E0038A 0 +OP4 E0038B 0 +OP4 E0038C 0 +OP4 E0038D 0 +OP4 E0038E 0 +OP4 E0038F 0 +OP4 E00390 0 +OP4 E00391 0 +OP4 E00392 0 +OP4 E00393 0 +OP4 E00394 0 +OP4 E00395 0 +OP4 E00396 0 +OP4 E00397 0 +OP4 E00398 0 +OP4 E00399 0 +OP4 E0039A 0 +OP4 E0039B 0 +OP4 E0039C 0 +OP4 E0039D 0 +OP4 E0039E 0 +OP4 E0039F 0 +OP4 E003A0 0 +OP4 E003A1 0 +OP4 E003A2 0 +OP4 E003A3 0 +OP4 E003A4 0 +OP4 E003A5 0 +OP4 E003A6 0 +OP4 E003A7 0 +OP4 E003A8 0 +OP4 E003A9 0 +OP4 E003AA 0 +OP4 E003AB 0 +OP4 E003AC 0 +OP4 E003AD 0 +OP4 E003AE 0 +OP4 E003AF 0 +OP4 E003B0 0 +OP4 E003B1 0 +OP4 E003B2 0 +OP4 E003B3 0 +OP4 E003B4 0 +OP4 E003B5 0 +OP4 E003B6 0 +OP4 E003B7 0 +OP4 E003B8 0 +OP4 E003B9 0 +OP4 E003BA 0 +OP4 E003BB 0 +OP4 E003BC 0 +OP4 E003BD 0 +OP4 E003BE 0 +OP4 E003BF 0 +OP4 E003C0 0 +OP4 E003C1 0 +OP4 E003C2 0 +OP4 E003C3 0 +OP4 E003C4 0 +OP4 E003C5 0 +OP4 E003C6 0 +OP4 E003C7 0 +OP4 E003C8 0 +OP4 E003C9 0 +OP4 E003CA 0 +OP4 E003CB 0 +OP4 E003CC 0 +OP4 E003CD 0 +OP4 E003CE 0 +OP4 E003CF 0 +OP4 E003D0 0 +OP4 E003D1 0 +OP4 E003D2 0 +OP4 E003D3 0 +OP4 E003D4 0 +OP4 E003D5 0 +OP4 E003D6 0 +OP4 E003D7 0 +OP4 E003D8 0 +OP4 E003D9 0 +OP4 E003DA 0 +OP4 E003DB 0 +OP4 E003DC 0 +OP4 E003DD 0 +OP4 E003DE 0 +OP4 E003DF 0 +OP4 E003E0 0 +OP4 E003E1 0 +OP4 E003E2 0 +OP4 E003E3 0 +OP4 E003E4 0 +OP4 E003E5 0 +OP4 E003E6 0 +OP4 E003E7 0 +OP4 E003E8 0 +OP4 E003E9 0 +OP4 E003EA 0 +OP4 E003EB 0 +OP4 E003EC 0 +OP4 E003ED 0 +OP4 E003EE 0 +OP4 E003EF 0 +OP4 E003F0 0 +OP4 E003F1 0 +OP4 E003F2 0 +OP4 E003F3 0 +OP4 E003F4 0 +OP4 E003F5 0 +OP4 E003F6 0 +OP4 E003F7 0 +OP4 E003F8 0 +OP4 E003F9 0 +OP4 E003FA 0 +OP4 E003FB 0 +OP4 E003FC 0 +OP4 E003FD 0 +OP4 E003FE 0 +OP4 E003FF 0 +OP4 E00400 0 +OP4 E00401 0 +OP4 E00402 0 +OP4 E00403 0 +OP4 E00404 0 +OP4 E00405 0 +OP4 E00406 0 +OP4 E00407 0 +OP4 E00408 0 +OP4 E00409 0 +OP4 E0040A 0 +OP4 E0040B 0 +OP4 E0040C 0 +OP4 E0040D 0 +OP4 E0040E 0 +OP4 E0040F 0 +OP4 E00410 0 +OP4 E00411 0 +OP4 E00412 0 +OP4 E00413 0 +OP4 E00414 0 +OP4 E00415 0 +OP4 E00416 0 +OP4 E00417 0 +OP4 E00418 0 +OP4 E00419 0 +OP4 E0041A 0 +OP4 E0041B 0 +OP4 E0041C 0 +OP4 E0041D 0 +OP4 E0041E 0 +OP4 E0041F 0 +OP4 E00420 0 +OP4 E00421 0 +OP4 E00422 0 +OP4 E00423 0 +OP4 E00424 0 +OP4 E00425 0 +OP4 E00426 0 +OP4 E00427 0 +OP4 E00428 0 +OP4 E00429 0 +OP4 E0042A 0 +OP4 E0042B 0 +OP4 E0042C 0 +OP4 E0042D 0 +OP4 E0042E 0 +OP4 E0042F 0 +OP4 E00430 0 +OP4 E00431 0 +OP4 E00432 0 +OP4 E00433 0 +OP4 E00434 0 +OP4 E00435 0 +OP4 E00436 0 +OP4 E00437 0 +OP4 E00438 0 +OP4 E00439 0 +OP4 E0043A 0 +OP4 E0043B 0 +OP4 E0043C 0 +OP4 E0043D 0 +OP4 E0043E 0 +OP4 E0043F 0 +OP4 E00440 0 +OP4 E00441 0 +OP4 E00442 0 +OP4 E00443 0 +OP4 E00444 0 +OP4 E00445 0 +OP4 E00446 0 +OP4 E00447 0 +OP4 E00448 0 +OP4 E00449 0 +OP4 E0044A 0 +OP4 E0044B 0 +OP4 E0044C 0 +OP4 E0044D 0 +OP4 E0044E 0 +OP4 E0044F 0 +OP4 E00450 0 +OP4 E00451 0 +OP4 E00452 0 +OP4 E00453 0 +OP4 E00454 0 +OP4 E00455 0 +OP4 E00456 0 +OP4 E00457 0 +OP4 E00458 0 +OP4 E00459 0 +OP4 E0045A 0 +OP4 E0045B 0 +OP4 E0045C 0 +OP4 E0045D 0 +OP4 E0045E 0 +OP4 E0045F 0 +OP4 E00460 0 +OP4 E00461 0 +OP4 E00462 0 +OP4 E00463 0 +OP4 E00464 0 +OP4 E00465 0 +OP4 E00466 0 +OP4 E00467 0 +OP4 E00468 0 +OP4 E00469 0 +OP4 E0046A 0 +OP4 E0046B 0 +OP4 E0046C 0 +OP4 E0046D 0 +OP4 E0046E 0 +OP4 E0046F 0 +OP4 E00470 0 +OP4 E00471 0 +OP4 E00472 0 +OP4 E00473 0 +OP4 E00474 0 +OP4 E00475 0 +OP4 E00476 0 +OP4 E00477 0 +OP4 E00478 0 +OP4 E00479 0 +OP4 E0047A 0 +OP4 E0047B 0 +OP4 E0047C 0 +OP4 E0047D 0 +OP4 E0047E 0 +OP4 E0047F 0 +OP4 E00480 0 +OP4 E00481 0 +OP4 E00482 0 +OP4 E00483 0 +OP4 E00484 0 +OP4 E00485 0 +OP4 E00486 0 +OP4 E00487 0 +OP4 E00488 0 +OP4 E00489 0 +OP4 E0048A 0 +OP4 E0048B 0 +OP4 E0048C 0 +OP4 E0048D 0 +OP4 E0048E 0 +OP4 E0048F 0 +OP4 E00490 0 +OP4 E00491 0 +OP4 E00492 0 +OP4 E00493 0 +OP4 E00494 0 +OP4 E00495 0 +OP4 E00496 0 +OP4 E00497 0 +OP4 E00498 0 +OP4 E00499 0 +OP4 E0049A 0 +OP4 E0049B 0 +OP4 E0049C 0 +OP4 E0049D 0 +OP4 E0049E 0 +OP4 E0049F 0 +OP4 E004A0 0 +OP4 E004A1 0 +OP4 E004A2 0 +OP4 E004A3 0 +OP4 E004A4 0 +OP4 E004A5 0 +OP4 E004A6 0 +OP4 E004A7 0 +OP4 E004A8 0 +OP4 E004A9 0 +OP4 E004AA 0 +OP4 E004AB 0 +OP4 E004AC 0 +OP4 E004AD 0 +OP4 E004AE 0 +OP4 E004AF 0 +OP4 E004B0 0 +OP4 E004B1 0 +OP4 E004B2 0 +OP4 E004B3 0 +OP4 E004B4 0 +OP4 E004B5 0 +OP4 E004B6 0 +OP4 E004B7 0 +OP4 E004B8 0 +OP4 E004B9 0 +OP4 E004BA 0 +OP4 E004BB 0 +OP4 E004BC 0 +OP4 E004BD 0 +OP4 E004BE 0 +OP4 E004BF 0 +OP4 E004C0 0 +OP4 E004C1 0 +OP4 E004C2 0 +OP4 E004C3 0 +OP4 E004C4 0 +OP4 E004C5 0 +OP4 E004C6 0 +OP4 E004C7 0 +OP4 E004C8 0 +OP4 E004C9 0 +OP4 E004CA 0 +OP4 E004CB 0 +OP4 E004CC 0 +OP4 E004CD 0 +OP4 E004CE 0 +OP4 E004CF 0 +OP4 E004D0 0 +OP4 E004D1 0 +OP4 E004D2 0 +OP4 E004D3 0 +OP4 E004D4 0 +OP4 E004D5 0 +OP4 E004D6 0 +OP4 E004D7 0 +OP4 E004D8 0 +OP4 E004D9 0 +OP4 E004DA 0 +OP4 E004DB 0 +OP4 E004DC 0 +OP4 E004DD 0 +OP4 E004DE 0 +OP4 E004DF 0 +OP4 E004E0 0 +OP4 E004E1 0 +OP4 E004E2 0 +OP4 E004E3 0 +OP4 E004E4 0 +OP4 E004E5 0 +OP4 E004E6 0 +OP4 E004E7 0 +OP4 E004E8 0 +OP4 E004E9 0 +OP4 E004EA 0 +OP4 E004EB 0 +OP4 E004EC 0 +OP4 E004ED 0 +OP4 E004EE 0 +OP4 E004EF 0 +OP4 E004F0 0 +OP4 E004F1 0 +OP4 E004F2 0 +OP4 E004F3 0 +OP4 E004F4 0 +OP4 E004F5 0 +OP4 E004F6 0 +OP4 E004F7 0 +OP4 E004F8 0 +OP4 E004F9 0 +OP4 E004FA 0 +OP4 E004FB 0 +OP4 E004FC 0 +OP4 E004FD 0 +OP4 E004FE 0 +OP4 E004FF 0 +OP4 E00500 0 +OP4 E00501 0 +OP4 E00502 0 +OP4 E00503 0 +OP4 E00504 0 +OP4 E00505 0 +OP4 E00506 0 +OP4 E00507 0 +OP4 E00508 0 +OP4 E00509 0 +OP4 E0050A 0 +OP4 E0050B 0 +OP4 E0050C 0 +OP4 E0050D 0 +OP4 E0050E 0 +OP4 E0050F 0 +OP4 E00510 0 +OP4 E00511 0 +OP4 E00512 0 +OP4 E00513 0 +OP4 E00514 0 +OP4 E00515 0 +OP4 E00516 0 +OP4 E00517 0 +OP4 E00518 0 +OP4 E00519 0 +OP4 E0051A 0 +OP4 E0051B 0 +OP4 E0051C 0 +OP4 E0051D 0 +OP4 E0051E 0 +OP4 E0051F 0 +OP4 E00520 0 +OP4 E00521 0 +OP4 E00522 0 +OP4 E00523 0 +OP4 E00524 0 +OP4 E00525 0 +OP4 E00526 0 +OP4 E00527 0 +OP4 E00528 0 +OP4 E00529 0 +OP4 E0052A 0 +OP4 E0052B 0 +OP4 E0052C 0 +OP4 E0052D 0 +OP4 E0052E 0 +OP4 E0052F 0 +OP4 E00530 0 +OP4 E00531 0 +OP4 E00532 0 +OP4 E00533 0 +OP4 E00534 0 +OP4 E00535 0 +OP4 E00536 0 +OP4 E00537 0 +OP4 E00538 0 +OP4 E00539 0 +OP4 E0053A 0 +OP4 E0053B 0 +OP4 E0053C 0 +OP4 E0053D 0 +OP4 E0053E 0 +OP4 E0053F 0 +OP4 E00540 0 +OP4 E00541 0 +OP4 E00542 0 +OP4 E00543 0 +OP4 E00544 0 +OP4 E00545 0 +OP4 E00546 0 +OP4 E00547 0 +OP4 E00548 0 +OP4 E00549 0 +OP4 E0054A 0 +OP4 E0054B 0 +OP4 E0054C 0 +OP4 E0054D 0 +OP4 E0054E 0 +OP4 E0054F 0 +OP4 E00550 0 +OP4 E00551 0 +OP4 E00552 0 +OP4 E00553 0 +OP4 E00554 0 +OP4 E00555 0 +OP4 E00556 0 +OP4 E00557 0 +OP4 E00558 0 +OP4 E00559 0 +OP4 E0055A 0 +OP4 E0055B 0 +OP4 E0055C 0 +OP4 E0055D 0 +OP4 E0055E 0 +OP4 E0055F 0 +OP4 E00560 0 +OP4 E00561 0 +OP4 E00562 0 +OP4 E00563 0 +OP4 E00564 0 +OP4 E00565 0 +OP4 E00566 0 +OP4 E00567 0 +OP4 E00568 0 +OP4 E00569 0 +OP4 E0056A 0 +OP4 E0056B 0 +OP4 E0056C 0 +OP4 E0056D 0 +OP4 E0056E 0 +OP4 E0056F 0 +OP4 E00570 0 +OP4 E00571 0 +OP4 E00572 0 +OP4 E00573 0 +OP4 E00574 0 +OP4 E00575 0 +OP4 E00576 0 +OP4 E00577 0 +OP4 E00578 0 +OP4 E00579 0 +OP4 E0057A 0 +OP4 E0057B 0 +OP4 E0057C 0 +OP4 E0057D 0 +OP4 E0057E 0 +OP4 E0057F 0 +OP4 E00580 0 +OP4 E00581 0 +OP4 E00582 0 +OP4 E00583 0 +OP4 E00584 0 +OP4 E00585 0 +OP4 E00586 0 +OP4 E00587 0 +OP4 E00588 0 +OP4 E00589 0 +OP4 E0058A 0 +OP4 E0058B 0 +OP4 E0058C 0 +OP4 E0058D 0 +OP4 E0058E 0 +OP4 E0058F 0 +OP4 E00590 0 +OP4 E00591 0 +OP4 E00592 0 +OP4 E00593 0 +OP4 E00594 0 +OP4 E00595 0 +OP4 E00596 0 +OP4 E00597 0 +OP4 E00598 0 +OP4 E00599 0 +OP4 E0059A 0 +OP4 E0059B 0 +OP4 E0059C 0 +OP4 E0059D 0 +OP4 E0059E 0 +OP4 E0059F 0 +OP4 E005A0 0 +OP4 E005A1 0 +OP4 E005A2 0 +OP4 E005A3 0 +OP4 E005A4 0 +OP4 E005A5 0 +OP4 E005A6 0 +OP4 E005A7 0 +OP4 E005A8 0 +OP4 E005A9 0 +OP4 E005AA 0 +OP4 E005AB 0 +OP4 E005AC 0 +OP4 E005AD 0 +OP4 E005AE 0 +OP4 E005AF 0 +OP4 E005B0 0 +OP4 E005B1 0 +OP4 E005B2 0 +OP4 E005B3 0 +OP4 E005B4 0 +OP4 E005B5 0 +OP4 E005B6 0 +OP4 E005B7 0 +OP4 E005B8 0 +OP4 E005B9 0 +OP4 E005BA 0 +OP4 E005BB 0 +OP4 E005BC 0 +OP4 E005BD 0 +OP4 E005BE 0 +OP4 E005BF 0 +OP4 E005C0 0 +OP4 E005C1 0 +OP4 E005C2 0 +OP4 E005C3 0 +OP4 E005C4 0 +OP4 E005C5 0 +OP4 E005C6 0 +OP4 E005C7 0 +OP4 E005C8 0 +OP4 E005C9 0 +OP4 E005CA 0 +OP4 E005CB 0 +OP4 E005CC 0 +OP4 E005CD 0 +OP4 E005CE 0 +OP4 E005CF 0 +OP4 E005D0 0 +OP4 E005D1 0 +OP4 E005D2 0 +OP4 E005D3 0 +OP4 E005D4 0 +OP4 E005D5 0 +OP4 E005D6 0 +OP4 E005D7 0 +OP4 E005D8 0 +OP4 E005D9 0 +OP4 E005DA 0 +OP4 E005DB 0 +OP4 E005DC 0 +OP4 E005DD 0 +OP4 E005DE 0 +OP4 E005DF 0 +OP4 E005E0 0 +OP4 E005E1 0 +OP4 E005E2 0 +OP4 E005E3 0 +OP4 E005E4 0 +OP4 E005E5 0 +OP4 E005E6 0 +OP4 E005E7 0 +OP4 E005E8 0 +OP4 E005E9 0 +OP4 E005EA 0 +OP4 E005EB 0 +OP4 E005EC 0 +OP4 E005ED 0 +OP4 E005EE 0 +OP4 E005EF 0 +OP4 E005F0 0 +OP4 E005F1 0 +OP4 E005F2 0 +OP4 E005F3 0 +OP4 E005F4 0 +OP4 E005F5 0 +OP4 E005F6 0 +OP4 E005F7 0 +OP4 E005F8 0 +OP4 E005F9 0 +OP4 E005FA 0 +OP4 E005FB 0 +OP4 E005FC 0 +OP4 E005FD 0 +OP4 E005FE 0 +OP4 E005FF 0 +OP4 E00600 0 +OP4 E00601 0 +OP4 E00602 0 +OP4 E00603 0 +OP4 E00604 0 +OP4 E00605 0 +OP4 E00606 0 +OP4 E00607 0 +OP4 E00608 0 +OP4 E00609 0 +OP4 E0060A 0 +OP4 E0060B 0 +OP4 E0060C 0 +OP4 E0060D 0 +OP4 E0060E 0 +OP4 E0060F 0 +OP4 E00610 0 +OP4 E00611 0 +OP4 E00612 0 +OP4 E00613 0 +OP4 E00614 0 +OP4 E00615 0 +OP4 E00616 0 +OP4 E00617 0 +OP4 E00618 0 +OP4 E00619 0 +OP4 E0061A 0 +OP4 E0061B 0 +OP4 E0061C 0 +OP4 E0061D 0 +OP4 E0061E 0 +OP4 E0061F 0 +OP4 E00620 0 +OP4 E00621 0 +OP4 E00622 0 +OP4 E00623 0 +OP4 E00624 0 +OP4 E00625 0 +OP4 E00626 0 +OP4 E00627 0 +OP4 E00628 0 +OP4 E00629 0 +OP4 E0062A 0 +OP4 E0062B 0 +OP4 E0062C 0 +OP4 E0062D 0 +OP4 E0062E 0 +OP4 E0062F 0 +OP4 E00630 0 +OP4 E00631 0 +OP4 E00632 0 +OP4 E00633 0 +OP4 E00634 0 +OP4 E00635 0 +OP4 E00636 0 +OP4 E00637 0 +OP4 E00638 0 +OP4 E00639 0 +OP4 E0063A 0 +OP4 E0063B 0 +OP4 E0063C 0 +OP4 E0063D 0 +OP4 E0063E 0 +OP4 E0063F 0 +OP4 E00640 0 +OP4 E00641 0 +OP4 E00642 0 +OP4 E00643 0 +OP4 E00644 0 +OP4 E00645 0 +OP4 E00646 0 +OP4 E00647 0 +OP4 E00648 0 +OP4 E00649 0 +OP4 E0064A 0 +OP4 E0064B 0 +OP4 E0064C 0 +OP4 E0064D 0 +OP4 E0064E 0 +OP4 E0064F 0 +OP4 E00650 0 +OP4 E00651 0 +OP4 E00652 0 +OP4 E00653 0 +OP4 E00654 0 +OP4 E00655 0 +OP4 E00656 0 +OP4 E00657 0 +OP4 E00658 0 +OP4 E00659 0 +OP4 E0065A 0 +OP4 E0065B 0 +OP4 E0065C 0 +OP4 E0065D 0 +OP4 E0065E 0 +OP4 E0065F 0 +OP4 E00660 0 +OP4 E00661 0 +OP4 E00662 0 +OP4 E00663 0 +OP4 E00664 0 +OP4 E00665 0 +OP4 E00666 0 +OP4 E00667 0 +OP4 E00668 0 +OP4 E00669 0 +OP4 E0066A 0 +OP4 E0066B 0 +OP4 E0066C 0 +OP4 E0066D 0 +OP4 E0066E 0 +OP4 E0066F 0 +OP4 E00670 0 +OP4 E00671 0 +OP4 E00672 0 +OP4 E00673 0 +OP4 E00674 0 +OP4 E00675 0 +OP4 E00676 0 +OP4 E00677 0 +OP4 E00678 0 +OP4 E00679 0 +OP4 E0067A 0 +OP4 E0067B 0 +OP4 E0067C 0 +OP4 E0067D 0 +OP4 E0067E 0 +OP4 E0067F 0 +OP4 E00680 0 +OP4 E00681 0 +OP4 E00682 0 +OP4 E00683 0 +OP4 E00684 0 +OP4 E00685 0 +OP4 E00686 0 +OP4 E00687 0 +OP4 E00688 0 +OP4 E00689 0 +OP4 E0068A 0 +OP4 E0068B 0 +OP4 E0068C 0 +OP4 E0068D 0 +OP4 E0068E 0 +OP4 E0068F 0 +OP4 E00690 0 +OP4 E00691 0 +OP4 E00692 0 +OP4 E00693 0 +OP4 E00694 0 +OP4 E00695 0 +OP4 E00696 0 +OP4 E00697 0 +OP4 E00698 0 +OP4 E00699 0 +OP4 E0069A 0 +OP4 E0069B 0 +OP4 E0069C 0 +OP4 E0069D 0 +OP4 E0069E 0 +OP4 E0069F 0 +OP4 E006A0 0 +OP4 E006A1 0 +OP4 E006A2 0 +OP4 E006A3 0 +OP4 E006A4 0 +OP4 E006A5 0 +OP4 E006A6 0 +OP4 E006A7 0 +OP4 E006A8 0 +OP4 E006A9 0 +OP4 E006AA 0 +OP4 E006AB 0 +OP4 E006AC 0 +OP4 E006AD 0 +OP4 E006AE 0 +OP4 E006AF 0 +OP4 E006B0 0 +OP4 E006B1 0 +OP4 E006B2 0 +OP4 E006B3 0 +OP4 E006B4 0 +OP4 E006B5 0 +OP4 E006B6 0 +OP4 E006B7 0 +OP4 E006B8 0 +OP4 E006B9 0 +OP4 E006BA 0 +OP4 E006BB 0 +OP4 E006BC 0 +OP4 E006BD 0 +OP4 E006BE 0 +OP4 E006BF 0 +OP4 E006C0 0 +OP4 E006C1 0 +OP4 E006C2 0 +OP4 E006C3 0 +OP4 E006C4 0 +OP4 E006C5 0 +OP4 E006C6 0 +OP4 E006C7 0 +OP4 E006C8 0 +OP4 E006C9 0 +OP4 E006CA 0 +OP4 E006CB 0 +OP4 E006CC 0 +OP4 E006CD 0 +OP4 E006CE 0 +OP4 E006CF 0 +OP4 E006D0 0 +OP4 E006D1 0 +OP4 E006D2 0 +OP4 E006D3 0 +OP4 E006D4 0 +OP4 E006D5 0 +OP4 E006D6 0 +OP4 E006D7 0 +OP4 E006D8 0 +OP4 E006D9 0 +OP4 E006DA 0 +OP4 E006DB 0 +OP4 E006DC 0 +OP4 E006DD 0 +OP4 E006DE 0 +OP4 E006DF 0 +OP4 E006E0 0 +OP4 E006E1 0 +OP4 E006E2 0 +OP4 E006E3 0 +OP4 E006E4 0 +OP4 E006E5 0 +OP4 E006E6 0 +OP4 E006E7 0 +OP4 E006E8 0 +OP4 E006E9 0 +OP4 E006EA 0 +OP4 E006EB 0 +OP4 E006EC 0 +OP4 E006ED 0 +OP4 E006EE 0 +OP4 E006EF 0 +OP4 E006F0 0 +OP4 E006F1 0 +OP4 E006F2 0 +OP4 E006F3 0 +OP4 E006F4 0 +OP4 E006F5 0 +OP4 E006F6 0 +OP4 E006F7 0 +OP4 E006F8 0 +OP4 E006F9 0 +OP4 E006FA 0 +OP4 E006FB 0 +OP4 E006FC 0 +OP4 E006FD 0 +OP4 E006FE 0 +OP4 E006FF 0 +OP4 E00700 0 +OP4 E00701 0 +OP4 E00702 0 +OP4 E00703 0 +OP4 E00704 0 +OP4 E00705 0 +OP4 E00706 0 +OP4 E00707 0 +OP4 E00708 0 +OP4 E00709 0 +OP4 E0070A 0 +OP4 E0070B 0 +OP4 E0070C 0 +OP4 E0070D 0 +OP4 E0070E 0 +OP4 E0070F 0 +OP4 E00710 0 +OP4 E00711 0 +OP4 E00712 0 +OP4 E00713 0 +OP4 E00714 0 +OP4 E00715 0 +OP4 E00716 0 +OP4 E00717 0 +OP4 E00718 0 +OP4 E00719 0 +OP4 E0071A 0 +OP4 E0071B 0 +OP4 E0071C 0 +OP4 E0071D 0 +OP4 E0071E 0 +OP4 E0071F 0 +OP4 E00720 0 +OP4 E00721 0 +OP4 E00722 0 +OP4 E00723 0 +OP4 E00724 0 +OP4 E00725 0 +OP4 E00726 0 +OP4 E00727 0 +OP4 E00728 0 +OP4 E00729 0 +OP4 E0072A 0 +OP4 E0072B 0 +OP4 E0072C 0 +OP4 E0072D 0 +OP4 E0072E 0 +OP4 E0072F 0 +OP4 E00730 0 +OP4 E00731 0 +OP4 E00732 0 +OP4 E00733 0 +OP4 E00734 0 +OP4 E00735 0 +OP4 E00736 0 +OP4 E00737 0 +OP4 E00738 0 +OP4 E00739 0 +OP4 E0073A 0 +OP4 E0073B 0 +OP4 E0073C 0 +OP4 E0073D 0 +OP4 E0073E 0 +OP4 E0073F 0 +OP4 E00740 0 +OP4 E00741 0 +OP4 E00742 0 +OP4 E00743 0 +OP4 E00744 0 +OP4 E00745 0 +OP4 E00746 0 +OP4 E00747 0 +OP4 E00748 0 +OP4 E00749 0 +OP4 E0074A 0 +OP4 E0074B 0 +OP4 E0074C 0 +OP4 E0074D 0 +OP4 E0074E 0 +OP4 E0074F 0 +OP4 E00750 0 +OP4 E00751 0 +OP4 E00752 0 +OP4 E00753 0 +OP4 E00754 0 +OP4 E00755 0 +OP4 E00756 0 +OP4 E00757 0 +OP4 E00758 0 +OP4 E00759 0 +OP4 E0075A 0 +OP4 E0075B 0 +OP4 E0075C 0 +OP4 E0075D 0 +OP4 E0075E 0 +OP4 E0075F 0 +OP4 E00760 0 +OP4 E00761 0 +OP4 E00762 0 +OP4 E00763 0 +OP4 E00764 0 +OP4 E00765 0 +OP4 E00766 0 +OP4 E00767 0 +OP4 E00768 0 +OP4 E00769 0 +OP4 E0076A 0 +OP4 E0076B 0 +OP4 E0076C 0 +OP4 E0076D 0 +OP4 E0076E 0 +OP4 E0076F 0 +OP4 E00770 0 +OP4 E00771 0 +OP4 E00772 0 +OP4 E00773 0 +OP4 E00774 0 +OP4 E00775 0 +OP4 E00776 0 +OP4 E00777 0 +OP4 E00778 0 +OP4 E00779 0 +OP4 E0077A 0 +OP4 E0077B 0 +OP4 E0077C 0 +OP4 E0077D 0 +OP4 E0077E 0 +OP4 E0077F 0 +OP4 E00780 0 +OP4 E00781 0 +OP4 E00782 0 +OP4 E00783 0 +OP4 E00784 0 +OP4 E00785 0 +OP4 E00786 0 +OP4 E00787 0 +OP4 E00788 0 +OP4 E00789 0 +OP4 E0078A 0 +OP4 E0078B 0 +OP4 E0078C 0 +OP4 E0078D 0 +OP4 E0078E 0 +OP4 E0078F 0 +OP4 E00790 0 +OP4 E00791 0 +OP4 E00792 0 +OP4 E00793 0 +OP4 E00794 0 +OP4 E00795 0 +OP4 E00796 0 +OP4 E00797 0 +OP4 E00798 0 +OP4 E00799 0 +OP4 E0079A 0 +OP4 E0079B 0 +OP4 E0079C 0 +OP4 E0079D 0 +OP4 E0079E 0 +OP4 E0079F 0 +OP4 E007A0 0 +OP4 E007A1 0 +OP4 E007A2 0 +OP4 E007A3 0 +OP4 E007A4 0 +OP4 E007A5 0 +OP4 E007A6 0 +OP4 E007A7 0 +OP4 E007A8 0 +OP4 E007A9 0 +OP4 E007AA 0 +OP4 E007AB 0 +OP4 E007AC 0 +OP4 E007AD 0 +OP4 E007AE 0 +OP4 E007AF 0 +OP4 E007B0 0 +OP4 E007B1 0 +OP4 E007B2 0 +OP4 E007B3 0 +OP4 E007B4 0 +OP4 E007B5 0 +OP4 E007B6 0 +OP4 E007B7 0 +OP4 E007B8 0 +OP4 E007B9 0 +OP4 E007BA 0 +OP4 E007BB 0 +OP4 E007BC 0 +OP4 E007BD 0 +OP4 E007BE 0 +OP4 E007BF 0 +OP4 E007C0 0 +OP4 E007C1 0 +OP4 E007C2 0 +OP4 E007C3 0 +OP4 E007C4 0 +OP4 E007C5 0 +OP4 E007C6 0 +OP4 E007C7 0 +OP4 E007C8 0 +OP4 E007C9 0 +OP4 E007CA 0 +OP4 E007CB 0 +OP4 E007CC 0 +OP4 E007CD 0 +OP4 E007CE 0 +OP4 E007CF 0 +OP4 E007D0 0 +OP4 E007D1 0 +OP4 E007D2 0 +OP4 E007D3 0 +OP4 E007D4 0 +OP4 E007D5 0 +OP4 E007D6 0 +OP4 E007D7 0 +OP4 E007D8 0 +OP4 E007D9 0 +OP4 E007DA 0 +OP4 E007DB 0 +OP4 E007DC 0 +OP4 E007DD 0 +OP4 E007DE 0 +OP4 E007DF 0 +OP4 E007E0 0 +OP4 E007E1 0 +OP4 E007E2 0 +OP4 E007E3 0 +OP4 E007E4 0 +OP4 E007E5 0 +OP4 E007E6 0 +OP4 E007E7 0 +OP4 E007E8 0 +OP4 E007E9 0 +OP4 E007EA 0 +OP4 E007EB 0 +OP4 E007EC 0 +OP4 E007ED 0 +OP4 E007EE 0 +OP4 E007EF 0 +OP4 E007F0 0 +OP4 E007F1 0 +OP4 E007F2 0 +OP4 E007F3 0 +OP4 E007F4 0 +OP4 E007F5 0 +OP4 E007F6 0 +OP4 E007F7 0 +OP4 E007F8 0 +OP4 E007F9 0 +OP4 E007FA 0 +OP4 E007FB 0 +OP4 E007FC 0 +OP4 E007FD 0 +OP4 E007FE 0 +OP4 E007FF 0 +OP4 E00800 0 +OP4 E00801 0 +OP4 E00802 0 +OP4 E00803 0 +OP4 E00804 0 +OP4 E00805 0 +OP4 E00806 0 +OP4 E00807 0 +OP4 E00808 0 +OP4 E00809 0 +OP4 E0080A 0 +OP4 E0080B 0 +OP4 E0080C 0 +OP4 E0080D 0 +OP4 E0080E 0 +OP4 E0080F 0 +OP4 E00810 0 +OP4 E00811 0 +OP4 E00812 0 +OP4 E00813 0 +OP4 E00814 0 +OP4 E00815 0 +OP4 E00816 0 +OP4 E00817 0 +OP4 E00818 0 +OP4 E00819 0 +OP4 E0081A 0 +OP4 E0081B 0 +OP4 E0081C 0 +OP4 E0081D 0 +OP4 E0081E 0 +OP4 E0081F 0 +OP4 E00820 0 +OP4 E00821 0 +OP4 E00822 0 +OP4 E00823 0 +OP4 E00824 0 +OP4 E00825 0 +OP4 E00826 0 +OP4 E00827 0 +OP4 E00828 0 +OP4 E00829 0 +OP4 E0082A 0 +OP4 E0082B 0 +OP4 E0082C 0 +OP4 E0082D 0 +OP4 E0082E 0 +OP4 E0082F 0 +OP4 E00830 0 +OP4 E00831 0 +OP4 E00832 0 +OP4 E00833 0 +OP4 E00834 0 +OP4 E00835 0 +OP4 E00836 0 +OP4 E00837 0 +OP4 E00838 0 +OP4 E00839 0 +OP4 E0083A 0 +OP4 E0083B 0 +OP4 E0083C 0 +OP4 E0083D 0 +OP4 E0083E 0 +OP4 E0083F 0 +OP4 E00840 0 +OP4 E00841 0 +OP4 E00842 0 +OP4 E00843 0 +OP4 E00844 0 +OP4 E00845 0 +OP4 E00846 0 +OP4 E00847 0 +OP4 E00848 0 +OP4 E00849 0 +OP4 E0084A 0 +OP4 E0084B 0 +OP4 E0084C 0 +OP4 E0084D 0 +OP4 E0084E 0 +OP4 E0084F 0 +OP4 E00850 0 +OP4 E00851 0 +OP4 E00852 0 +OP4 E00853 0 +OP4 E00854 0 +OP4 E00855 0 +OP4 E00856 0 +OP4 E00857 0 +OP4 E00858 0 +OP4 E00859 0 +OP4 E0085A 0 +OP4 E0085B 0 +OP4 E0085C 0 +OP4 E0085D 0 +OP4 E0085E 0 +OP4 E0085F 0 +OP4 E00860 0 +OP4 E00861 0 +OP4 E00862 0 +OP4 E00863 0 +OP4 E00864 0 +OP4 E00865 0 +OP4 E00866 0 +OP4 E00867 0 +OP4 E00868 0 +OP4 E00869 0 +OP4 E0086A 0 +OP4 E0086B 0 +OP4 E0086C 0 +OP4 E0086D 0 +OP4 E0086E 0 +OP4 E0086F 0 +OP4 E00870 0 +OP4 E00871 0 +OP4 E00872 0 +OP4 E00873 0 +OP4 E00874 0 +OP4 E00875 0 +OP4 E00876 0 +OP4 E00877 0 +OP4 E00878 0 +OP4 E00879 0 +OP4 E0087A 0 +OP4 E0087B 0 +OP4 E0087C 0 +OP4 E0087D 0 +OP4 E0087E 0 +OP4 E0087F 0 +OP4 E00880 0 +OP4 E00881 0 +OP4 E00882 0 +OP4 E00883 0 +OP4 E00884 0 +OP4 E00885 0 +OP4 E00886 0 +OP4 E00887 0 +OP4 E00888 0 +OP4 E00889 0 +OP4 E0088A 0 +OP4 E0088B 0 +OP4 E0088C 0 +OP4 E0088D 0 +OP4 E0088E 0 +OP4 E0088F 0 +OP4 E00890 0 +OP4 E00891 0 +OP4 E00892 0 +OP4 E00893 0 +OP4 E00894 0 +OP4 E00895 0 +OP4 E00896 0 +OP4 E00897 0 +OP4 E00898 0 +OP4 E00899 0 +OP4 E0089A 0 +OP4 E0089B 0 +OP4 E0089C 0 +OP4 E0089D 0 +OP4 E0089E 0 +OP4 E0089F 0 +OP4 E008A0 0 +OP4 E008A1 0 +OP4 E008A2 0 +OP4 E008A3 0 +OP4 E008A4 0 +OP4 E008A5 0 +OP4 E008A6 0 +OP4 E008A7 0 +OP4 E008A8 0 +OP4 E008A9 0 +OP4 E008AA 0 +OP4 E008AB 0 +OP4 E008AC 0 +OP4 E008AD 0 +OP4 E008AE 0 +OP4 E008AF 0 +OP4 E008B0 0 +OP4 E008B1 0 +OP4 E008B2 0 +OP4 E008B3 0 +OP4 E008B4 0 +OP4 E008B5 0 +OP4 E008B6 0 +OP4 E008B7 0 +OP4 E008B8 0 +OP4 E008B9 0 +OP4 E008BA 0 +OP4 E008BB 0 +OP4 E008BC 0 +OP4 E008BD 0 +OP4 E008BE 0 +OP4 E008BF 0 +OP4 E008C0 0 +OP4 E008C1 0 +OP4 E008C2 0 +OP4 E008C3 0 +OP4 E008C4 0 +OP4 E008C5 0 +OP4 E008C6 0 +OP4 E008C7 0 +OP4 E008C8 0 +OP4 E008C9 0 +OP4 E008CA 0 +OP4 E008CB 0 +OP4 E008CC 0 +OP4 E008CD 0 +OP4 E008CE 0 +OP4 E008CF 0 +OP4 E008D0 0 +OP4 E008D1 0 +OP4 E008D2 0 +OP4 E008D3 0 +OP4 E008D4 0 +OP4 E008D5 0 +OP4 E008D6 0 +OP4 E008D7 0 +OP4 E008D8 0 +OP4 E008D9 0 +OP4 E008DA 0 +OP4 E008DB 0 +OP4 E008DC 0 +OP4 E008DD 0 +OP4 E008DE 0 +OP4 E008DF 0 +OP4 E008E0 0 +OP4 E008E1 0 +OP4 E008E2 0 +OP4 E008E3 0 +OP4 E008E4 0 +OP4 E008E5 0 +OP4 E008E6 0 +OP4 E008E7 0 +OP4 E008E8 0 +OP4 E008E9 0 +OP4 E008EA 0 +OP4 E008EB 0 +OP4 E008EC 0 +OP4 E008ED 0 +OP4 E008EE 0 +OP4 E008EF 0 +OP4 E008F0 0 +OP4 E008F1 0 +OP4 E008F2 0 +OP4 E008F3 0 +OP4 E008F4 0 +OP4 E008F5 0 +OP4 E008F6 0 +OP4 E008F7 0 +OP4 E008F8 0 +OP4 E008F9 0 +OP4 E008FA 0 +OP4 E008FB 0 +OP4 E008FC 0 +OP4 E008FD 0 +OP4 E008FE 0 +OP4 E008FF 0 +OP4 E00900 0 +OP4 E00901 0 +OP4 E00902 0 +OP4 E00903 0 +OP4 E00904 0 +OP4 E00905 0 +OP4 E00906 0 +OP4 E00907 0 +OP4 E00908 0 +OP4 E00909 0 +OP4 E0090A 0 +OP4 E0090B 0 +OP4 E0090C 0 +OP4 E0090D 0 +OP4 E0090E 0 +OP4 E0090F 0 +OP4 E00910 0 +OP4 E00911 0 +OP4 E00912 0 +OP4 E00913 0 +OP4 E00914 0 +OP4 E00915 0 +OP4 E00916 0 +OP4 E00917 0 +OP4 E00918 0 +OP4 E00919 0 +OP4 E0091A 0 +OP4 E0091B 0 +OP4 E0091C 0 +OP4 E0091D 0 +OP4 E0091E 0 +OP4 E0091F 0 +OP4 E00920 0 +OP4 E00921 0 +OP4 E00922 0 +OP4 E00923 0 +OP4 E00924 0 +OP4 E00925 0 +OP4 E00926 0 +OP4 E00927 0 +OP4 E00928 0 +OP4 E00929 0 +OP4 E0092A 0 +OP4 E0092B 0 +OP4 E0092C 0 +OP4 E0092D 0 +OP4 E0092E 0 +OP4 E0092F 0 +OP4 E00930 0 +OP4 E00931 0 +OP4 E00932 0 +OP4 E00933 0 +OP4 E00934 0 +OP4 E00935 0 +OP4 E00936 0 +OP4 E00937 0 +OP4 E00938 0 +OP4 E00939 0 +OP4 E0093A 0 +OP4 E0093B 0 +OP4 E0093C 0 +OP4 E0093D 0 +OP4 E0093E 0 +OP4 E0093F 0 +OP4 E00940 0 +OP4 E00941 0 +OP4 E00942 0 +OP4 E00943 0 +OP4 E00944 0 +OP4 E00945 0 +OP4 E00946 0 +OP4 E00947 0 +OP4 E00948 0 +OP4 E00949 0 +OP4 E0094A 0 +OP4 E0094B 0 +OP4 E0094C 0 +OP4 E0094D 0 +OP4 E0094E 0 +OP4 E0094F 0 +OP4 E00950 0 +OP4 E00951 0 +OP4 E00952 0 +OP4 E00953 0 +OP4 E00954 0 +OP4 E00955 0 +OP4 E00956 0 +OP4 E00957 0 +OP4 E00958 0 +OP4 E00959 0 +OP4 E0095A 0 +OP4 E0095B 0 +OP4 E0095C 0 +OP4 E0095D 0 +OP4 E0095E 0 +OP4 E0095F 0 +OP4 E00960 0 +OP4 E00961 0 +OP4 E00962 0 +OP4 E00963 0 +OP4 E00964 0 +OP4 E00965 0 +OP4 E00966 0 +OP4 E00967 0 +OP4 E00968 0 +OP4 E00969 0 +OP4 E0096A 0 +OP4 E0096B 0 +OP4 E0096C 0 +OP4 E0096D 0 +OP4 E0096E 0 +OP4 E0096F 0 +OP4 E00970 0 +OP4 E00971 0 +OP4 E00972 0 +OP4 E00973 0 +OP4 E00974 0 +OP4 E00975 0 +OP4 E00976 0 +OP4 E00977 0 +OP4 E00978 0 +OP4 E00979 0 +OP4 E0097A 0 +OP4 E0097B 0 +OP4 E0097C 0 +OP4 E0097D 0 +OP4 E0097E 0 +OP4 E0097F 0 +OP4 E00980 0 +OP4 E00981 0 +OP4 E00982 0 +OP4 E00983 0 +OP4 E00984 0 +OP4 E00985 0 +OP4 E00986 0 +OP4 E00987 0 +OP4 E00988 0 +OP4 E00989 0 +OP4 E0098A 0 +OP4 E0098B 0 +OP4 E0098C 0 +OP4 E0098D 0 +OP4 E0098E 0 +OP4 E0098F 0 +OP4 E00990 0 +OP4 E00991 0 +OP4 E00992 0 +OP4 E00993 0 +OP4 E00994 0 +OP4 E00995 0 +OP4 E00996 0 +OP4 E00997 0 +OP4 E00998 0 +OP4 E00999 0 +OP4 E0099A 0 +OP4 E0099B 0 +OP4 E0099C 0 +OP4 E0099D 0 +OP4 E0099E 0 +OP4 E0099F 0 +OP4 E009A0 0 +OP4 E009A1 0 +OP4 E009A2 0 +OP4 E009A3 0 +OP4 E009A4 0 +OP4 E009A5 0 +OP4 E009A6 0 +OP4 E009A7 0 +OP4 E009A8 0 +OP4 E009A9 0 +OP4 E009AA 0 +OP4 E009AB 0 +OP4 E009AC 0 +OP4 E009AD 0 +OP4 E009AE 0 +OP4 E009AF 0 +OP4 E009B0 0 +OP4 E009B1 0 +OP4 E009B2 0 +OP4 E009B3 0 +OP4 E009B4 0 +OP4 E009B5 0 +OP4 E009B6 0 +OP4 E009B7 0 +OP4 E009B8 0 +OP4 E009B9 0 +OP4 E009BA 0 +OP4 E009BB 0 +OP4 E009BC 0 +OP4 E009BD 0 +OP4 E009BE 0 +OP4 E009BF 0 +OP4 E009C0 0 +OP4 E009C1 0 +OP4 E009C2 0 +OP4 E009C3 0 +OP4 E009C4 0 +OP4 E009C5 0 +OP4 E009C6 0 +OP4 E009C7 0 +OP4 E009C8 0 +OP4 E009C9 0 +OP4 E009CA 0 +OP4 E009CB 0 +OP4 E009CC 0 +OP4 E009CD 0 +OP4 E009CE 0 +OP4 E009CF 0 +OP4 E009D0 0 +OP4 E009D1 0 +OP4 E009D2 0 +OP4 E009D3 0 +OP4 E009D4 0 +OP4 E009D5 0 +OP4 E009D6 0 +OP4 E009D7 0 +OP4 E009D8 0 +OP4 E009D9 0 +OP4 E009DA 0 +OP4 E009DB 0 +OP4 E009DC 0 +OP4 E009DD 0 +OP4 E009DE 0 +OP4 E009DF 0 +OP4 E009E0 0 +OP4 E009E1 0 +OP4 E009E2 0 +OP4 E009E3 0 +OP4 E009E4 0 +OP4 E009E5 0 +OP4 E009E6 0 +OP4 E009E7 0 +OP4 E009E8 0 +OP4 E009E9 0 +OP4 E009EA 0 +OP4 E009EB 0 +OP4 E009EC 0 +OP4 E009ED 0 +OP4 E009EE 0 +OP4 E009EF 0 +OP4 E009F0 0 +OP4 E009F1 0 +OP4 E009F2 0 +OP4 E009F3 0 +OP4 E009F4 0 +OP4 E009F5 0 +OP4 E009F6 0 +OP4 E009F7 0 +OP4 E009F8 0 +OP4 E009F9 0 +OP4 E009FA 0 +OP4 E009FB 0 +OP4 E009FC 0 +OP4 E009FD 0 +OP4 E009FE 0 +OP4 E009FF 0 +OP4 E00A00 0 +OP4 E00A01 0 +OP4 E00A02 0 +OP4 E00A03 0 +OP4 E00A04 0 +OP4 E00A05 0 +OP4 E00A06 0 +OP4 E00A07 0 +OP4 E00A08 0 +OP4 E00A09 0 +OP4 E00A0A 0 +OP4 E00A0B 0 +OP4 E00A0C 0 +OP4 E00A0D 0 +OP4 E00A0E 0 +OP4 E00A0F 0 +OP4 E00A10 0 +OP4 E00A11 0 +OP4 E00A12 0 +OP4 E00A13 0 +OP4 E00A14 0 +OP4 E00A15 0 +OP4 E00A16 0 +OP4 E00A17 0 +OP4 E00A18 0 +OP4 E00A19 0 +OP4 E00A1A 0 +OP4 E00A1B 0 +OP4 E00A1C 0 +OP4 E00A1D 0 +OP4 E00A1E 0 +OP4 E00A1F 0 +OP4 E00A20 0 +OP4 E00A21 0 +OP4 E00A22 0 +OP4 E00A23 0 +OP4 E00A24 0 +OP4 E00A25 0 +OP4 E00A26 0 +OP4 E00A27 0 +OP4 E00A28 0 +OP4 E00A29 0 +OP4 E00A2A 0 +OP4 E00A2B 0 +OP4 E00A2C 0 +OP4 E00A2D 0 +OP4 E00A2E 0 +OP4 E00A2F 0 +OP4 E00A30 0 +OP4 E00A31 0 +OP4 E00A32 0 +OP4 E00A33 0 +OP4 E00A34 0 +OP4 E00A35 0 +OP4 E00A36 0 +OP4 E00A37 0 +OP4 E00A38 0 +OP4 E00A39 0 +OP4 E00A3A 0 +OP4 E00A3B 0 +OP4 E00A3C 0 +OP4 E00A3D 0 +OP4 E00A3E 0 +OP4 E00A3F 0 +OP4 E00A40 0 +OP4 E00A41 0 +OP4 E00A42 0 +OP4 E00A43 0 +OP4 E00A44 0 +OP4 E00A45 0 +OP4 E00A46 0 +OP4 E00A47 0 +OP4 E00A48 0 +OP4 E00A49 0 +OP4 E00A4A 0 +OP4 E00A4B 0 +OP4 E00A4C 0 +OP4 E00A4D 0 +OP4 E00A4E 0 +OP4 E00A4F 0 +OP4 E00A50 0 +OP4 E00A51 0 +OP4 E00A52 0 +OP4 E00A53 0 +OP4 E00A54 0 +OP4 E00A55 0 +OP4 E00A56 0 +OP4 E00A57 0 +OP4 E00A58 0 +OP4 E00A59 0 +OP4 E00A5A 0 +OP4 E00A5B 0 +OP4 E00A5C 0 +OP4 E00A5D 0 +OP4 E00A5E 0 +OP4 E00A5F 0 +OP4 E00A60 0 +OP4 E00A61 0 +OP4 E00A62 0 +OP4 E00A63 0 +OP4 E00A64 0 +OP4 E00A65 0 +OP4 E00A66 0 +OP4 E00A67 0 +OP4 E00A68 0 +OP4 E00A69 0 +OP4 E00A6A 0 +OP4 E00A6B 0 +OP4 E00A6C 0 +OP4 E00A6D 0 +OP4 E00A6E 0 +OP4 E00A6F 0 +OP4 E00A70 0 +OP4 E00A71 0 +OP4 E00A72 0 +OP4 E00A73 0 +OP4 E00A74 0 +OP4 E00A75 0 +OP4 E00A76 0 +OP4 E00A77 0 +OP4 E00A78 0 +OP4 E00A79 0 +OP4 E00A7A 0 +OP4 E00A7B 0 +OP4 E00A7C 0 +OP4 E00A7D 0 +OP4 E00A7E 0 +OP4 E00A7F 0 +OP4 E00A80 0 +OP4 E00A81 0 +OP4 E00A82 0 +OP4 E00A83 0 +OP4 E00A84 0 +OP4 E00A85 0 +OP4 E00A86 0 +OP4 E00A87 0 +OP4 E00A88 0 +OP4 E00A89 0 +OP4 E00A8A 0 +OP4 E00A8B 0 +OP4 E00A8C 0 +OP4 E00A8D 0 +OP4 E00A8E 0 +OP4 E00A8F 0 +OP4 E00A90 0 +OP4 E00A91 0 +OP4 E00A92 0 +OP4 E00A93 0 +OP4 E00A94 0 +OP4 E00A95 0 +OP4 E00A96 0 +OP4 E00A97 0 +OP4 E00A98 0 +OP4 E00A99 0 +OP4 E00A9A 0 +OP4 E00A9B 0 +OP4 E00A9C 0 +OP4 E00A9D 0 +OP4 E00A9E 0 +OP4 E00A9F 0 +OP4 E00AA0 0 +OP4 E00AA1 0 +OP4 E00AA2 0 +OP4 E00AA3 0 +OP4 E00AA4 0 +OP4 E00AA5 0 +OP4 E00AA6 0 +OP4 E00AA7 0 +OP4 E00AA8 0 +OP4 E00AA9 0 +OP4 E00AAA 0 +OP4 E00AAB 0 +OP4 E00AAC 0 +OP4 E00AAD 0 +OP4 E00AAE 0 +OP4 E00AAF 0 +OP4 E00AB0 0 +OP4 E00AB1 0 +OP4 E00AB2 0 +OP4 E00AB3 0 +OP4 E00AB4 0 +OP4 E00AB5 0 +OP4 E00AB6 0 +OP4 E00AB7 0 +OP4 E00AB8 0 +OP4 E00AB9 0 +OP4 E00ABA 0 +OP4 E00ABB 0 +OP4 E00ABC 0 +OP4 E00ABD 0 +OP4 E00ABE 0 +OP4 E00ABF 0 +OP4 E00AC0 0 +OP4 E00AC1 0 +OP4 E00AC2 0 +OP4 E00AC3 0 +OP4 E00AC4 0 +OP4 E00AC5 0 +OP4 E00AC6 0 +OP4 E00AC7 0 +OP4 E00AC8 0 +OP4 E00AC9 0 +OP4 E00ACA 0 +OP4 E00ACB 0 +OP4 E00ACC 0 +OP4 E00ACD 0 +OP4 E00ACE 0 +OP4 E00ACF 0 +OP4 E00AD0 0 +OP4 E00AD1 0 +OP4 E00AD2 0 +OP4 E00AD3 0 +OP4 E00AD4 0 +OP4 E00AD5 0 +OP4 E00AD6 0 +OP4 E00AD7 0 +OP4 E00AD8 0 +OP4 E00AD9 0 +OP4 E00ADA 0 +OP4 E00ADB 0 +OP4 E00ADC 0 +OP4 E00ADD 0 +OP4 E00ADE 0 +OP4 E00ADF 0 +OP4 E00AE0 0 +OP4 E00AE1 0 +OP4 E00AE2 0 +OP4 E00AE3 0 +OP4 E00AE4 0 +OP4 E00AE5 0 +OP4 E00AE6 0 +OP4 E00AE7 0 +OP4 E00AE8 0 +OP4 E00AE9 0 +OP4 E00AEA 0 +OP4 E00AEB 0 +OP4 E00AEC 0 +OP4 E00AED 0 +OP4 E00AEE 0 +OP4 E00AEF 0 +OP4 E00AF0 0 +OP4 E00AF1 0 +OP4 E00AF2 0 +OP4 E00AF3 0 +OP4 E00AF4 0 +OP4 E00AF5 0 +OP4 E00AF6 0 +OP4 E00AF7 0 +OP4 E00AF8 0 +OP4 E00AF9 0 +OP4 E00AFA 0 +OP4 E00AFB 0 +OP4 E00AFC 0 +OP4 E00AFD 0 +OP4 E00AFE 0 +OP4 E00AFF 0 +OP4 E00B00 0 +OP4 E00B01 0 +OP4 E00B02 0 +OP4 E00B03 0 +OP4 E00B04 0 +OP4 E00B05 0 +OP4 E00B06 0 +OP4 E00B07 0 +OP4 E00B08 0 +OP4 E00B09 0 +OP4 E00B0A 0 +OP4 E00B0B 0 +OP4 E00B0C 0 +OP4 E00B0D 0 +OP4 E00B0E 0 +OP4 E00B0F 0 +OP4 E00B10 0 +OP4 E00B11 0 +OP4 E00B12 0 +OP4 E00B13 0 +OP4 E00B14 0 +OP4 E00B15 0 +OP4 E00B16 0 +OP4 E00B17 0 +OP4 E00B18 0 +OP4 E00B19 0 +OP4 E00B1A 0 +OP4 E00B1B 0 +OP4 E00B1C 0 +OP4 E00B1D 0 +OP4 E00B1E 0 +OP4 E00B1F 0 +OP4 E00B20 0 +OP4 E00B21 0 +OP4 E00B22 0 +OP4 E00B23 0 +OP4 E00B24 0 +OP4 E00B25 0 +OP4 E00B26 0 +OP4 E00B27 0 +OP4 E00B28 0 +OP4 E00B29 0 +OP4 E00B2A 0 +OP4 E00B2B 0 +OP4 E00B2C 0 +OP4 E00B2D 0 +OP4 E00B2E 0 +OP4 E00B2F 0 +OP4 E00B30 0 +OP4 E00B31 0 +OP4 E00B32 0 +OP4 E00B33 0 +OP4 E00B34 0 +OP4 E00B35 0 +OP4 E00B36 0 +OP4 E00B37 0 +OP4 E00B38 0 +OP4 E00B39 0 +OP4 E00B3A 0 +OP4 E00B3B 0 +OP4 E00B3C 0 +OP4 E00B3D 0 +OP4 E00B3E 0 +OP4 E00B3F 0 +OP4 E00B40 0 +OP4 E00B41 0 +OP4 E00B42 0 +OP4 E00B43 0 +OP4 E00B44 0 +OP4 E00B45 0 +OP4 E00B46 0 +OP4 E00B47 0 +OP4 E00B48 0 +OP4 E00B49 0 +OP4 E00B4A 0 +OP4 E00B4B 0 +OP4 E00B4C 0 +OP4 E00B4D 0 +OP4 E00B4E 0 +OP4 E00B4F 0 +OP4 E00B50 0 +OP4 E00B51 0 +OP4 E00B52 0 +OP4 E00B53 0 +OP4 E00B54 0 +OP4 E00B55 0 +OP4 E00B56 0 +OP4 E00B57 0 +OP4 E00B58 0 +OP4 E00B59 0 +OP4 E00B5A 0 +OP4 E00B5B 0 +OP4 E00B5C 0 +OP4 E00B5D 0 +OP4 E00B5E 0 +OP4 E00B5F 0 +OP4 E00B60 0 +OP4 E00B61 0 +OP4 E00B62 0 +OP4 E00B63 0 +OP4 E00B64 0 +OP4 E00B65 0 +OP4 E00B66 0 +OP4 E00B67 0 +OP4 E00B68 0 +OP4 E00B69 0 +OP4 E00B6A 0 +OP4 E00B6B 0 +OP4 E00B6C 0 +OP4 E00B6D 0 +OP4 E00B6E 0 +OP4 E00B6F 0 +OP4 E00B70 0 +OP4 E00B71 0 +OP4 E00B72 0 +OP4 E00B73 0 +OP4 E00B74 0 +OP4 E00B75 0 +OP4 E00B76 0 +OP4 E00B77 0 +OP4 E00B78 0 +OP4 E00B79 0 +OP4 E00B7A 0 +OP4 E00B7B 0 +OP4 E00B7C 0 +OP4 E00B7D 0 +OP4 E00B7E 0 +OP4 E00B7F 0 +OP4 E00B80 0 +OP4 E00B81 0 +OP4 E00B82 0 +OP4 E00B83 0 +OP4 E00B84 0 +OP4 E00B85 0 +OP4 E00B86 0 +OP4 E00B87 0 +OP4 E00B88 0 +OP4 E00B89 0 +OP4 E00B8A 0 +OP4 E00B8B 0 +OP4 E00B8C 0 +OP4 E00B8D 0 +OP4 E00B8E 0 +OP4 E00B8F 0 +OP4 E00B90 0 +OP4 E00B91 0 +OP4 E00B92 0 +OP4 E00B93 0 +OP4 E00B94 0 +OP4 E00B95 0 +OP4 E00B96 0 +OP4 E00B97 0 +OP4 E00B98 0 +OP4 E00B99 0 +OP4 E00B9A 0 +OP4 E00B9B 0 +OP4 E00B9C 0 +OP4 E00B9D 0 +OP4 E00B9E 0 +OP4 E00B9F 0 +OP4 E00BA0 0 +OP4 E00BA1 0 +OP4 E00BA2 0 +OP4 E00BA3 0 +OP4 E00BA4 0 +OP4 E00BA5 0 +OP4 E00BA6 0 +OP4 E00BA7 0 +OP4 E00BA8 0 +OP4 E00BA9 0 +OP4 E00BAA 0 +OP4 E00BAB 0 +OP4 E00BAC 0 +OP4 E00BAD 0 +OP4 E00BAE 0 +OP4 E00BAF 0 +OP4 E00BB0 0 +OP4 E00BB1 0 +OP4 E00BB2 0 +OP4 E00BB3 0 +OP4 E00BB4 0 +OP4 E00BB5 0 +OP4 E00BB6 0 +OP4 E00BB7 0 +OP4 E00BB8 0 +OP4 E00BB9 0 +OP4 E00BBA 0 +OP4 E00BBB 0 +OP4 E00BBC 0 +OP4 E00BBD 0 +OP4 E00BBE 0 +OP4 E00BBF 0 +OP4 E00BC0 0 +OP4 E00BC1 0 +OP4 E00BC2 0 +OP4 E00BC3 0 +OP4 E00BC4 0 +OP4 E00BC5 0 +OP4 E00BC6 0 +OP4 E00BC7 0 +OP4 E00BC8 0 +OP4 E00BC9 0 +OP4 E00BCA 0 +OP4 E00BCB 0 +OP4 E00BCC 0 +OP4 E00BCD 0 +OP4 E00BCE 0 +OP4 E00BCF 0 +OP4 E00BD0 0 +OP4 E00BD1 0 +OP4 E00BD2 0 +OP4 E00BD3 0 +OP4 E00BD4 0 +OP4 E00BD5 0 +OP4 E00BD6 0 +OP4 E00BD7 0 +OP4 E00BD8 0 +OP4 E00BD9 0 +OP4 E00BDA 0 +OP4 E00BDB 0 +OP4 E00BDC 0 +OP4 E00BDD 0 +OP4 E00BDE 0 +OP4 E00BDF 0 +OP4 E00BE0 0 +OP4 E00BE1 0 +OP4 E00BE2 0 +OP4 E00BE3 0 +OP4 E00BE4 0 +OP4 E00BE5 0 +OP4 E00BE6 0 +OP4 E00BE7 0 +OP4 E00BE8 0 +OP4 E00BE9 0 +OP4 E00BEA 0 +OP4 E00BEB 0 +OP4 E00BEC 0 +OP4 E00BED 0 +OP4 E00BEE 0 +OP4 E00BEF 0 +OP4 E00BF0 0 +OP4 E00BF1 0 +OP4 E00BF2 0 +OP4 E00BF3 0 +OP4 E00BF4 0 +OP4 E00BF5 0 +OP4 E00BF6 0 +OP4 E00BF7 0 +OP4 E00BF8 0 +OP4 E00BF9 0 +OP4 E00BFA 0 +OP4 E00BFB 0 +OP4 E00BFC 0 +OP4 E00BFD 0 +OP4 E00BFE 0 +OP4 E00BFF 0 +OP4 E00C00 0 +OP4 E00C01 0 +OP4 E00C02 0 +OP4 E00C03 0 +OP4 E00C04 0 +OP4 E00C05 0 +OP4 E00C06 0 +OP4 E00C07 0 +OP4 E00C08 0 +OP4 E00C09 0 +OP4 E00C0A 0 +OP4 E00C0B 0 +OP4 E00C0C 0 +OP4 E00C0D 0 +OP4 E00C0E 0 +OP4 E00C0F 0 +OP4 E00C10 0 +OP4 E00C11 0 +OP4 E00C12 0 +OP4 E00C13 0 +OP4 E00C14 0 +OP4 E00C15 0 +OP4 E00C16 0 +OP4 E00C17 0 +OP4 E00C18 0 +OP4 E00C19 0 +OP4 E00C1A 0 +OP4 E00C1B 0 +OP4 E00C1C 0 +OP4 E00C1D 0 +OP4 E00C1E 0 +OP4 E00C1F 0 +OP4 E00C20 0 +OP4 E00C21 0 +OP4 E00C22 0 +OP4 E00C23 0 +OP4 E00C24 0 +OP4 E00C25 0 +OP4 E00C26 0 +OP4 E00C27 0 +OP4 E00C28 0 +OP4 E00C29 0 +OP4 E00C2A 0 +OP4 E00C2B 0 +OP4 E00C2C 0 +OP4 E00C2D 0 +OP4 E00C2E 0 +OP4 E00C2F 0 +OP4 E00C30 0 +OP4 E00C31 0 +OP4 E00C32 0 +OP4 E00C33 0 +OP4 E00C34 0 +OP4 E00C35 0 +OP4 E00C36 0 +OP4 E00C37 0 +OP4 E00C38 0 +OP4 E00C39 0 +OP4 E00C3A 0 +OP4 E00C3B 0 +OP4 E00C3C 0 +OP4 E00C3D 0 +OP4 E00C3E 0 +OP4 E00C3F 0 +OP4 E00C40 0 +OP4 E00C41 0 +OP4 E00C42 0 +OP4 E00C43 0 +OP4 E00C44 0 +OP4 E00C45 0 +OP4 E00C46 0 +OP4 E00C47 0 +OP4 E00C48 0 +OP4 E00C49 0 +OP4 E00C4A 0 +OP4 E00C4B 0 +OP4 E00C4C 0 +OP4 E00C4D 0 +OP4 E00C4E 0 +OP4 E00C4F 0 +OP4 E00C50 0 +OP4 E00C51 0 +OP4 E00C52 0 +OP4 E00C53 0 +OP4 E00C54 0 +OP4 E00C55 0 +OP4 E00C56 0 +OP4 E00C57 0 +OP4 E00C58 0 +OP4 E00C59 0 +OP4 E00C5A 0 +OP4 E00C5B 0 +OP4 E00C5C 0 +OP4 E00C5D 0 +OP4 E00C5E 0 +OP4 E00C5F 0 +OP4 E00C60 0 +OP4 E00C61 0 +OP4 E00C62 0 +OP4 E00C63 0 +OP4 E00C64 0 +OP4 E00C65 0 +OP4 E00C66 0 +OP4 E00C67 0 +OP4 E00C68 0 +OP4 E00C69 0 +OP4 E00C6A 0 +OP4 E00C6B 0 +OP4 E00C6C 0 +OP4 E00C6D 0 +OP4 E00C6E 0 +OP4 E00C6F 0 +OP4 E00C70 0 +OP4 E00C71 0 +OP4 E00C72 0 +OP4 E00C73 0 +OP4 E00C74 0 +OP4 E00C75 0 +OP4 E00C76 0 +OP4 E00C77 0 +OP4 E00C78 0 +OP4 E00C79 0 +OP4 E00C7A 0 +OP4 E00C7B 0 +OP4 E00C7C 0 +OP4 E00C7D 0 +OP4 E00C7E 0 +OP4 E00C7F 0 +OP4 E00C80 0 +OP4 E00C81 0 +OP4 E00C82 0 +OP4 E00C83 0 +OP4 E00C84 0 +OP4 E00C85 0 +OP4 E00C86 0 +OP4 E00C87 0 +OP4 E00C88 0 +OP4 E00C89 0 +OP4 E00C8A 0 +OP4 E00C8B 0 +OP4 E00C8C 0 +OP4 E00C8D 0 +OP4 E00C8E 0 +OP4 E00C8F 0 +OP4 E00C90 0 +OP4 E00C91 0 +OP4 E00C92 0 +OP4 E00C93 0 +OP4 E00C94 0 +OP4 E00C95 0 +OP4 E00C96 0 +OP4 E00C97 0 +OP4 E00C98 0 +OP4 E00C99 0 +OP4 E00C9A 0 +OP4 E00C9B 0 +OP4 E00C9C 0 +OP4 E00C9D 0 +OP4 E00C9E 0 +OP4 E00C9F 0 +OP4 E00CA0 0 +OP4 E00CA1 0 +OP4 E00CA2 0 +OP4 E00CA3 0 +OP4 E00CA4 0 +OP4 E00CA5 0 +OP4 E00CA6 0 +OP4 E00CA7 0 +OP4 E00CA8 0 +OP4 E00CA9 0 +OP4 E00CAA 0 +OP4 E00CAB 0 +OP4 E00CAC 0 +OP4 E00CAD 0 +OP4 E00CAE 0 +OP4 E00CAF 0 +OP4 E00CB0 0 +OP4 E00CB1 0 +OP4 E00CB2 0 +OP4 E00CB3 0 +OP4 E00CB4 0 +OP4 E00CB5 0 +OP4 E00CB6 0 +OP4 E00CB7 0 +OP4 E00CB8 0 +OP4 E00CB9 0 +OP4 E00CBA 0 +OP4 E00CBB 0 +OP4 E00CBC 0 +OP4 E00CBD 0 +OP4 E00CBE 0 +OP4 E00CBF 0 +OP4 E00CC0 0 +OP4 E00CC1 0 +OP4 E00CC2 0 +OP4 E00CC3 0 +OP4 E00CC4 0 +OP4 E00CC5 0 +OP4 E00CC6 0 +OP4 E00CC7 0 +OP4 E00CC8 0 +OP4 E00CC9 0 +OP4 E00CCA 0 +OP4 E00CCB 0 +OP4 E00CCC 0 +OP4 E00CCD 0 +OP4 E00CCE 0 +OP4 E00CCF 0 +OP4 E00CD0 0 +OP4 E00CD1 0 +OP4 E00CD2 0 +OP4 E00CD3 0 +OP4 E00CD4 0 +OP4 E00CD5 0 +OP4 E00CD6 0 +OP4 E00CD7 0 +OP4 E00CD8 0 +OP4 E00CD9 0 +OP4 E00CDA 0 +OP4 E00CDB 0 +OP4 E00CDC 0 +OP4 E00CDD 0 +OP4 E00CDE 0 +OP4 E00CDF 0 +OP4 E00CE0 0 +OP4 E00CE1 0 +OP4 E00CE2 0 +OP4 E00CE3 0 +OP4 E00CE4 0 +OP4 E00CE5 0 +OP4 E00CE6 0 +OP4 E00CE7 0 +OP4 E00CE8 0 +OP4 E00CE9 0 +OP4 E00CEA 0 +OP4 E00CEB 0 +OP4 E00CEC 0 +OP4 E00CED 0 +OP4 E00CEE 0 +OP4 E00CEF 0 +OP4 E00CF0 0 +OP4 E00CF1 0 +OP4 E00CF2 0 +OP4 E00CF3 0 +OP4 E00CF4 0 +OP4 E00CF5 0 +OP4 E00CF6 0 +OP4 E00CF7 0 +OP4 E00CF8 0 +OP4 E00CF9 0 +OP4 E00CFA 0 +OP4 E00CFB 0 +OP4 E00CFC 0 +OP4 E00CFD 0 +OP4 E00CFE 0 +OP4 E00CFF 0 +OP4 E00D00 0 +OP4 E00D01 0 +OP4 E00D02 0 +OP4 E00D03 0 +OP4 E00D04 0 +OP4 E00D05 0 +OP4 E00D06 0 +OP4 E00D07 0 +OP4 E00D08 0 +OP4 E00D09 0 +OP4 E00D0A 0 +OP4 E00D0B 0 +OP4 E00D0C 0 +OP4 E00D0D 0 +OP4 E00D0E 0 +OP4 E00D0F 0 +OP4 E00D10 0 +OP4 E00D11 0 +OP4 E00D12 0 +OP4 E00D13 0 +OP4 E00D14 0 +OP4 E00D15 0 +OP4 E00D16 0 +OP4 E00D17 0 +OP4 E00D18 0 +OP4 E00D19 0 +OP4 E00D1A 0 +OP4 E00D1B 0 +OP4 E00D1C 0 +OP4 E00D1D 0 +OP4 E00D1E 0 +OP4 E00D1F 0 +OP4 E00D20 0 +OP4 E00D21 0 +OP4 E00D22 0 +OP4 E00D23 0 +OP4 E00D24 0 +OP4 E00D25 0 +OP4 E00D26 0 +OP4 E00D27 0 +OP4 E00D28 0 +OP4 E00D29 0 +OP4 E00D2A 0 +OP4 E00D2B 0 +OP4 E00D2C 0 +OP4 E00D2D 0 +OP4 E00D2E 0 +OP4 E00D2F 0 +OP4 E00D30 0 +OP4 E00D31 0 +OP4 E00D32 0 +OP4 E00D33 0 +OP4 E00D34 0 +OP4 E00D35 0 +OP4 E00D36 0 +OP4 E00D37 0 +OP4 E00D38 0 +OP4 E00D39 0 +OP4 E00D3A 0 +OP4 E00D3B 0 +OP4 E00D3C 0 +OP4 E00D3D 0 +OP4 E00D3E 0 +OP4 E00D3F 0 +OP4 E00D40 0 +OP4 E00D41 0 +OP4 E00D42 0 +OP4 E00D43 0 +OP4 E00D44 0 +OP4 E00D45 0 +OP4 E00D46 0 +OP4 E00D47 0 +OP4 E00D48 0 +OP4 E00D49 0 +OP4 E00D4A 0 +OP4 E00D4B 0 +OP4 E00D4C 0 +OP4 E00D4D 0 +OP4 E00D4E 0 +OP4 E00D4F 0 +OP4 E00D50 0 +OP4 E00D51 0 +OP4 E00D52 0 +OP4 E00D53 0 +OP4 E00D54 0 +OP4 E00D55 0 +OP4 E00D56 0 +OP4 E00D57 0 +OP4 E00D58 0 +OP4 E00D59 0 +OP4 E00D5A 0 +OP4 E00D5B 0 +OP4 E00D5C 0 +OP4 E00D5D 0 +OP4 E00D5E 0 +OP4 E00D5F 0 +OP4 E00D60 0 +OP4 E00D61 0 +OP4 E00D62 0 +OP4 E00D63 0 +OP4 E00D64 0 +OP4 E00D65 0 +OP4 E00D66 0 +OP4 E00D67 0 +OP4 E00D68 0 +OP4 E00D69 0 +OP4 E00D6A 0 +OP4 E00D6B 0 +OP4 E00D6C 0 +OP4 E00D6D 0 +OP4 E00D6E 0 +OP4 E00D6F 0 +OP4 E00D70 0 +OP4 E00D71 0 +OP4 E00D72 0 +OP4 E00D73 0 +OP4 E00D74 0 +OP4 E00D75 0 +OP4 E00D76 0 +OP4 E00D77 0 +OP4 E00D78 0 +OP4 E00D79 0 +OP4 E00D7A 0 +OP4 E00D7B 0 +OP4 E00D7C 0 +OP4 E00D7D 0 +OP4 E00D7E 0 +OP4 E00D7F 0 +OP4 E00D80 0 +OP4 E00D81 0 +OP4 E00D82 0 +OP4 E00D83 0 +OP4 E00D84 0 +OP4 E00D85 0 +OP4 E00D86 0 +OP4 E00D87 0 +OP4 E00D88 0 +OP4 E00D89 0 +OP4 E00D8A 0 +OP4 E00D8B 0 +OP4 E00D8C 0 +OP4 E00D8D 0 +OP4 E00D8E 0 +OP4 E00D8F 0 +OP4 E00D90 0 +OP4 E00D91 0 +OP4 E00D92 0 +OP4 E00D93 0 +OP4 E00D94 0 +OP4 E00D95 0 +OP4 E00D96 0 +OP4 E00D97 0 +OP4 E00D98 0 +OP4 E00D99 0 +OP4 E00D9A 0 +OP4 E00D9B 0 +OP4 E00D9C 0 +OP4 E00D9D 0 +OP4 E00D9E 0 +OP4 E00D9F 0 +OP4 E00DA0 0 +OP4 E00DA1 0 +OP4 E00DA2 0 +OP4 E00DA3 0 +OP4 E00DA4 0 +OP4 E00DA5 0 +OP4 E00DA6 0 +OP4 E00DA7 0 +OP4 E00DA8 0 +OP4 E00DA9 0 +OP4 E00DAA 0 +OP4 E00DAB 0 +OP4 E00DAC 0 +OP4 E00DAD 0 +OP4 E00DAE 0 +OP4 E00DAF 0 +OP4 E00DB0 0 +OP4 E00DB1 0 +OP4 E00DB2 0 +OP4 E00DB3 0 +OP4 E00DB4 0 +OP4 E00DB5 0 +OP4 E00DB6 0 +OP4 E00DB7 0 +OP4 E00DB8 0 +OP4 E00DB9 0 +OP4 E00DBA 0 +OP4 E00DBB 0 +OP4 E00DBC 0 +OP4 E00DBD 0 +OP4 E00DBE 0 +OP4 E00DBF 0 +OP4 E00DC0 0 +OP4 E00DC1 0 +OP4 E00DC2 0 +OP4 E00DC3 0 +OP4 E00DC4 0 +OP4 E00DC5 0 +OP4 E00DC6 0 +OP4 E00DC7 0 +OP4 E00DC8 0 +OP4 E00DC9 0 +OP4 E00DCA 0 +OP4 E00DCB 0 +OP4 E00DCC 0 +OP4 E00DCD 0 +OP4 E00DCE 0 +OP4 E00DCF 0 +OP4 E00DD0 0 +OP4 E00DD1 0 +OP4 E00DD2 0 +OP4 E00DD3 0 +OP4 E00DD4 0 +OP4 E00DD5 0 +OP4 E00DD6 0 +OP4 E00DD7 0 +OP4 E00DD8 0 +OP4 E00DD9 0 +OP4 E00DDA 0 +OP4 E00DDB 0 +OP4 E00DDC 0 +OP4 E00DDD 0 +OP4 E00DDE 0 +OP4 E00DDF 0 +OP4 E00DE0 0 +OP4 E00DE1 0 +OP4 E00DE2 0 +OP4 E00DE3 0 +OP4 E00DE4 0 +OP4 E00DE5 0 +OP4 E00DE6 0 +OP4 E00DE7 0 +OP4 E00DE8 0 +OP4 E00DE9 0 +OP4 E00DEA 0 +OP4 E00DEB 0 +OP4 E00DEC 0 +OP4 E00DED 0 +OP4 E00DEE 0 +OP4 E00DEF 0 +OP4 E00DF0 0 +OP4 E00DF1 0 +OP4 E00DF2 0 +OP4 E00DF3 0 +OP4 E00DF4 0 +OP4 E00DF5 0 +OP4 E00DF6 0 +OP4 E00DF7 0 +OP4 E00DF8 0 +OP4 E00DF9 0 +OP4 E00DFA 0 +OP4 E00DFB 0 +OP4 E00DFC 0 +OP4 E00DFD 0 +OP4 E00DFE 0 +OP4 E00DFF 0 +OP4 E00E00 0 +OP4 E00E01 0 +OP4 E00E02 0 +OP4 E00E03 0 +OP4 E00E04 0 +OP4 E00E05 0 +OP4 E00E06 0 +OP4 E00E07 0 +OP4 E00E08 0 +OP4 E00E09 0 +OP4 E00E0A 0 +OP4 E00E0B 0 +OP4 E00E0C 0 +OP4 E00E0D 0 +OP4 E00E0E 0 +OP4 E00E0F 0 +OP4 E00E10 0 +OP4 E00E11 0 +OP4 E00E12 0 +OP4 E00E13 0 +OP4 E00E14 0 +OP4 E00E15 0 +OP4 E00E16 0 +OP4 E00E17 0 +OP4 E00E18 0 +OP4 E00E19 0 +OP4 E00E1A 0 +OP4 E00E1B 0 +OP4 E00E1C 0 +OP4 E00E1D 0 +OP4 E00E1E 0 +OP4 E00E1F 0 +OP4 E00E20 0 +OP4 E00E21 0 +OP4 E00E22 0 +OP4 E00E23 0 +OP4 E00E24 0 +OP4 E00E25 0 +OP4 E00E26 0 +OP4 E00E27 0 +OP4 E00E28 0 +OP4 E00E29 0 +OP4 E00E2A 0 +OP4 E00E2B 0 +OP4 E00E2C 0 +OP4 E00E2D 0 +OP4 E00E2E 0 +OP4 E00E2F 0 +OP4 E00E30 0 +OP4 E00E31 0 +OP4 E00E32 0 +OP4 E00E33 0 +OP4 E00E34 0 +OP4 E00E35 0 +OP4 E00E36 0 +OP4 E00E37 0 +OP4 E00E38 0 +OP4 E00E39 0 +OP4 E00E3A 0 +OP4 E00E3B 0 +OP4 E00E3C 0 +OP4 E00E3D 0 +OP4 E00E3E 0 +OP4 E00E3F 0 +OP4 E00E40 0 +OP4 E00E41 0 +OP4 E00E42 0 +OP4 E00E43 0 +OP4 E00E44 0 +OP4 E00E45 0 +OP4 E00E46 0 +OP4 E00E47 0 +OP4 E00E48 0 +OP4 E00E49 0 +OP4 E00E4A 0 +OP4 E00E4B 0 +OP4 E00E4C 0 +OP4 E00E4D 0 +OP4 E00E4E 0 +OP4 E00E4F 0 +OP4 E00E50 0 +OP4 E00E51 0 +OP4 E00E52 0 +OP4 E00E53 0 +OP4 E00E54 0 +OP4 E00E55 0 +OP4 E00E56 0 +OP4 E00E57 0 +OP4 E00E58 0 +OP4 E00E59 0 +OP4 E00E5A 0 +OP4 E00E5B 0 +OP4 E00E5C 0 +OP4 E00E5D 0 +OP4 E00E5E 0 +OP4 E00E5F 0 +OP4 E00E60 0 +OP4 E00E61 0 +OP4 E00E62 0 +OP4 E00E63 0 +OP4 E00E64 0 +OP4 E00E65 0 +OP4 E00E66 0 +OP4 E00E67 0 +OP4 E00E68 0 +OP4 E00E69 0 +OP4 E00E6A 0 +OP4 E00E6B 0 +OP4 E00E6C 0 +OP4 E00E6D 0 +OP4 E00E6E 0 +OP4 E00E6F 0 +OP4 E00E70 0 +OP4 E00E71 0 +OP4 E00E72 0 +OP4 E00E73 0 +OP4 E00E74 0 +OP4 E00E75 0 +OP4 E00E76 0 +OP4 E00E77 0 +OP4 E00E78 0 +OP4 E00E79 0 +OP4 E00E7A 0 +OP4 E00E7B 0 +OP4 E00E7C 0 +OP4 E00E7D 0 +OP4 E00E7E 0 +OP4 E00E7F 0 +OP4 E00E80 0 +OP4 E00E81 0 +OP4 E00E82 0 +OP4 E00E83 0 +OP4 E00E84 0 +OP4 E00E85 0 +OP4 E00E86 0 +OP4 E00E87 0 +OP4 E00E88 0 +OP4 E00E89 0 +OP4 E00E8A 0 +OP4 E00E8B 0 +OP4 E00E8C 0 +OP4 E00E8D 0 +OP4 E00E8E 0 +OP4 E00E8F 0 +OP4 E00E90 0 +OP4 E00E91 0 +OP4 E00E92 0 +OP4 E00E93 0 +OP4 E00E94 0 +OP4 E00E95 0 +OP4 E00E96 0 +OP4 E00E97 0 +OP4 E00E98 0 +OP4 E00E99 0 +OP4 E00E9A 0 +OP4 E00E9B 0 +OP4 E00E9C 0 +OP4 E00E9D 0 +OP4 E00E9E 0 +OP4 E00E9F 0 +OP4 E00EA0 0 +OP4 E00EA1 0 +OP4 E00EA2 0 +OP4 E00EA3 0 +OP4 E00EA4 0 +OP4 E00EA5 0 +OP4 E00EA6 0 +OP4 E00EA7 0 +OP4 E00EA8 0 +OP4 E00EA9 0 +OP4 E00EAA 0 +OP4 E00EAB 0 +OP4 E00EAC 0 +OP4 E00EAD 0 +OP4 E00EAE 0 +OP4 E00EAF 0 +OP4 E00EB0 0 +OP4 E00EB1 0 +OP4 E00EB2 0 +OP4 E00EB3 0 +OP4 E00EB4 0 +OP4 E00EB5 0 +OP4 E00EB6 0 +OP4 E00EB7 0 +OP4 E00EB8 0 +OP4 E00EB9 0 +OP4 E00EBA 0 +OP4 E00EBB 0 +OP4 E00EBC 0 +OP4 E00EBD 0 +OP4 E00EBE 0 +OP4 E00EBF 0 +OP4 E00EC0 0 +OP4 E00EC1 0 +OP4 E00EC2 0 +OP4 E00EC3 0 +OP4 E00EC4 0 +OP4 E00EC5 0 +OP4 E00EC6 0 +OP4 E00EC7 0 +OP4 E00EC8 0 +OP4 E00EC9 0 +OP4 E00ECA 0 +OP4 E00ECB 0 +OP4 E00ECC 0 +OP4 E00ECD 0 +OP4 E00ECE 0 +OP4 E00ECF 0 +OP4 E00ED0 0 +OP4 E00ED1 0 +OP4 E00ED2 0 +OP4 E00ED3 0 +OP4 E00ED4 0 +OP4 E00ED5 0 +OP4 E00ED6 0 +OP4 E00ED7 0 +OP4 E00ED8 0 +OP4 E00ED9 0 +OP4 E00EDA 0 +OP4 E00EDB 0 +OP4 E00EDC 0 +OP4 E00EDD 0 +OP4 E00EDE 0 +OP4 E00EDF 0 +OP4 E00EE0 0 +OP4 E00EE1 0 +OP4 E00EE2 0 +OP4 E00EE3 0 +OP4 E00EE4 0 +OP4 E00EE5 0 +OP4 E00EE6 0 +OP4 E00EE7 0 +OP4 E00EE8 0 +OP4 E00EE9 0 +OP4 E00EEA 0 +OP4 E00EEB 0 +OP4 E00EEC 0 +OP4 E00EED 0 +OP4 E00EEE 0 +OP4 E00EEF 0 +OP4 E00EF0 0 +OP4 E00EF1 0 +OP4 E00EF2 0 +OP4 E00EF3 0 +OP4 E00EF4 0 +OP4 E00EF5 0 +OP4 E00EF6 0 +OP4 E00EF7 0 +OP4 E00EF8 0 +OP4 E00EF9 0 +OP4 E00EFA 0 +OP4 E00EFB 0 +OP4 E00EFC 0 +OP4 E00EFD 0 +OP4 E00EFE 0 +OP4 E00EFF 0 +OP4 E00F00 0 +OP4 E00F01 0 +OP4 E00F02 0 +OP4 E00F03 0 +OP4 E00F04 0 +OP4 E00F05 0 +OP4 E00F06 0 +OP4 E00F07 0 +OP4 E00F08 0 +OP4 E00F09 0 +OP4 E00F0A 0 +OP4 E00F0B 0 +OP4 E00F0C 0 +OP4 E00F0D 0 +OP4 E00F0E 0 +OP4 E00F0F 0 +OP4 E00F10 0 +OP4 E00F11 0 +OP4 E00F12 0 +OP4 E00F13 0 +OP4 E00F14 0 +OP4 E00F15 0 +OP4 E00F16 0 +OP4 E00F17 0 +OP4 E00F18 0 +OP4 E00F19 0 +OP4 E00F1A 0 +OP4 E00F1B 0 +OP4 E00F1C 0 +OP4 E00F1D 0 +OP4 E00F1E 0 +OP4 E00F1F 0 +OP4 E00F20 0 +OP4 E00F21 0 +OP4 E00F22 0 +OP4 E00F23 0 +OP4 E00F24 0 +OP4 E00F25 0 +OP4 E00F26 0 +OP4 E00F27 0 +OP4 E00F28 0 +OP4 E00F29 0 +OP4 E00F2A 0 +OP4 E00F2B 0 +OP4 E00F2C 0 +OP4 E00F2D 0 +OP4 E00F2E 0 +OP4 E00F2F 0 +OP4 E00F30 0 +OP4 E00F31 0 +OP4 E00F32 0 +OP4 E00F33 0 +OP4 E00F34 0 +OP4 E00F35 0 +OP4 E00F36 0 +OP4 E00F37 0 +OP4 E00F38 0 +OP4 E00F39 0 +OP4 E00F3A 0 +OP4 E00F3B 0 +OP4 E00F3C 0 +OP4 E00F3D 0 +OP4 E00F3E 0 +OP4 E00F3F 0 +OP4 E00F40 0 +OP4 E00F41 0 +OP4 E00F42 0 +OP4 E00F43 0 +OP4 E00F44 0 +OP4 E00F45 0 +OP4 E00F46 0 +OP4 E00F47 0 +OP4 E00F48 0 +OP4 E00F49 0 +OP4 E00F4A 0 +OP4 E00F4B 0 +OP4 E00F4C 0 +OP4 E00F4D 0 +OP4 E00F4E 0 +OP4 E00F4F 0 +OP4 E00F50 0 +OP4 E00F51 0 +OP4 E00F52 0 +OP4 E00F53 0 +OP4 E00F54 0 +OP4 E00F55 0 +OP4 E00F56 0 +OP4 E00F57 0 +OP4 E00F58 0 +OP4 E00F59 0 +OP4 E00F5A 0 +OP4 E00F5B 0 +OP4 E00F5C 0 +OP4 E00F5D 0 +OP4 E00F5E 0 +OP4 E00F5F 0 +OP4 E00F60 0 +OP4 E00F61 0 +OP4 E00F62 0 +OP4 E00F63 0 +OP4 E00F64 0 +OP4 E00F65 0 +OP4 E00F66 0 +OP4 E00F67 0 +OP4 E00F68 0 +OP4 E00F69 0 +OP4 E00F6A 0 +OP4 E00F6B 0 +OP4 E00F6C 0 +OP4 E00F6D 0 +OP4 E00F6E 0 +OP4 E00F6F 0 +OP4 E00F70 0 +OP4 E00F71 0 +OP4 E00F72 0 +OP4 E00F73 0 +OP4 E00F74 0 +OP4 E00F75 0 +OP4 E00F76 0 +OP4 E00F77 0 +OP4 E00F78 0 +OP4 E00F79 0 +OP4 E00F7A 0 +OP4 E00F7B 0 +OP4 E00F7C 0 +OP4 E00F7D 0 +OP4 E00F7E 0 +OP4 E00F7F 0 +OP4 E00F80 0 +OP4 E00F81 0 +OP4 E00F82 0 +OP4 E00F83 0 +OP4 E00F84 0 +OP4 E00F85 0 +OP4 E00F86 0 +OP4 E00F87 0 +OP4 E00F88 0 +OP4 E00F89 0 +OP4 E00F8A 0 +OP4 E00F8B 0 +OP4 E00F8C 0 +OP4 E00F8D 0 +OP4 E00F8E 0 +OP4 E00F8F 0 +OP4 E00F90 0 +OP4 E00F91 0 +OP4 E00F92 0 +OP4 E00F93 0 +OP4 E00F94 0 +OP4 E00F95 0 +OP4 E00F96 0 +OP4 E00F97 0 +OP4 E00F98 0 +OP4 E00F99 0 +OP4 E00F9A 0 +OP4 E00F9B 0 +OP4 E00F9C 0 +OP4 E00F9D 0 +OP4 E00F9E 0 +OP4 E00F9F 0 +OP4 E00FA0 0 +OP4 E00FA1 0 +OP4 E00FA2 0 +OP4 E00FA3 0 +OP4 E00FA4 0 +OP4 E00FA5 0 +OP4 E00FA6 0 +OP4 E00FA7 0 +OP4 E00FA8 0 +OP4 E00FA9 0 +OP4 E00FAA 0 +OP4 E00FAB 0 +OP4 E00FAC 0 +OP4 E00FAD 0 +OP4 E00FAE 0 +OP4 E00FAF 0 +OP4 E00FB0 0 +OP4 E00FB1 0 +OP4 E00FB2 0 +OP4 E00FB3 0 +OP4 E00FB4 0 +OP4 E00FB5 0 +OP4 E00FB6 0 +OP4 E00FB7 0 +OP4 E00FB8 0 +OP4 E00FB9 0 +OP4 E00FBA 0 +OP4 E00FBB 0 +OP4 E00FBC 0 +OP4 E00FBD 0 +OP4 E00FBE 0 +OP4 E00FBF 0 +OP4 E00FC0 0 +OP4 E00FC1 0 +OP4 E00FC2 0 +OP4 E00FC3 0 +OP4 E00FC4 0 +OP4 E00FC5 0 +OP4 E00FC6 0 +OP4 E00FC7 0 +OP4 E00FC8 0 +OP4 E00FC9 0 +OP4 E00FCA 0 +OP4 E00FCB 0 +OP4 E00FCC 0 +OP4 E00FCD 0 +OP4 E00FCE 0 +OP4 E00FCF 0 +OP4 E00FD0 0 +OP4 E00FD1 0 +OP4 E00FD2 0 +OP4 E00FD3 0 +OP4 E00FD4 0 +OP4 E00FD5 0 +OP4 E00FD6 0 +OP4 E00FD7 0 +OP4 E00FD8 0 +OP4 E00FD9 0 +OP4 E00FDA 0 +OP4 E00FDB 0 +OP4 E00FDC 0 +OP4 E00FDD 0 +OP4 E00FDE 0 +OP4 E00FDF 0 +OP4 E00FE0 0 +OP4 E00FE1 0 +OP4 E00FE2 0 +OP4 E00FE3 0 +OP4 E00FE4 0 +OP4 E00FE5 0 +OP4 E00FE6 0 +OP4 E00FE7 0 +OP4 E00FE8 0 +OP4 E00FE9 0 +OP4 E00FEA 0 +OP4 E00FEB 0 +OP4 E00FEC 0 +OP4 E00FED 0 +OP4 E00FEE 0 +OP4 E00FEF 0 +OP4 E00FF0 0 +OP4 E00FF1 0 +OP4 E00FF2 0 +OP4 E00FF3 0 +OP4 E00FF4 0 +OP4 E00FF5 0 +OP4 E00FF6 0 +OP4 E00FF7 0 +OP4 E00FF8 0 +OP4 E00FF9 0 +OP4 E00FFA 0 +OP4 E00FFB 0 +OP4 E00FFC 0 +OP4 E00FFD 0 +OP4 E00FFE 0 +OP4 E00FFF 0 +OP4 E01000 0 +OP4 E01001 0 +OP4 E01002 0 +OP4 E01003 0 +OP4 E01004 0 +OP4 E01005 0 +OP4 E01006 0 +OP4 E01007 0 +OP4 E01008 0 +OP4 E01009 0 +OP4 E0100A 0 +OP4 E0100B 0 +OP4 E0100C 0 +OP4 E0100D 0 +OP4 E0100E 0 +OP4 E0100F 0 +OP4 E01010 0 +OP4 E01011 0 +OP4 E01012 0 +OP4 E01013 0 +OP4 E01014 0 +OP4 E01015 0 +OP4 E01016 0 +OP4 E01017 0 +OP4 E01018 0 +OP4 E01019 0 +OP4 E0101A 0 +OP4 E0101B 0 +OP4 E0101C 0 +OP4 E0101D 0 +OP4 E0101E 0 +OP4 E0101F 0 +OP4 E01020 0 +OP4 E01021 0 +OP4 E01022 0 +OP4 E01023 0 +OP4 E01024 0 +OP4 E01025 0 +OP4 E01026 0 +OP4 E01027 0 +OP4 E01028 0 +OP4 E01029 0 +OP4 E0102A 0 +OP4 E0102B 0 +OP4 E0102C 0 +OP4 E0102D 0 +OP4 E0102E 0 +OP4 E0102F 0 +OP4 E01030 0 +OP4 E01031 0 +OP4 E01032 0 +OP4 E01033 0 +OP4 E01034 0 +OP4 E01035 0 +OP4 E01036 0 +OP4 E01037 0 +OP4 E01038 0 +OP4 E01039 0 +OP4 E0103A 0 +OP4 E0103B 0 +OP4 E0103C 0 +OP4 E0103D 0 +OP4 E0103E 0 +OP4 E0103F 0 +OP4 E01040 0 +OP4 E01041 0 +OP4 E01042 0 +OP4 E01043 0 +OP4 E01044 0 +OP4 E01045 0 +OP4 E01046 0 +OP4 E01047 0 +OP4 E01048 0 +OP4 E01049 0 +OP4 E0104A 0 +OP4 E0104B 0 +OP4 E0104C 0 +OP4 E0104D 0 +OP4 E0104E 0 +OP4 E0104F 0 +OP4 E01050 0 +OP4 E01051 0 +OP4 E01052 0 +OP4 E01053 0 +OP4 E01054 0 +OP4 E01055 0 +OP4 E01056 0 +OP4 E01057 0 +OP4 E01058 0 +OP4 E01059 0 +OP4 E0105A 0 +OP4 E0105B 0 +OP4 E0105C 0 +OP4 E0105D 0 +OP4 E0105E 0 +OP4 E0105F 0 +OP4 E01060 0 +OP4 E01061 0 +OP4 E01062 0 +OP4 E01063 0 +OP4 E01064 0 +OP4 E01065 0 +OP4 E01066 0 +OP4 E01067 0 +OP4 E01068 0 +OP4 E01069 0 +OP4 E0106A 0 +OP4 E0106B 0 +OP4 E0106C 0 +OP4 E0106D 0 +OP4 E0106E 0 +OP4 E0106F 0 +OP4 E01070 0 +OP4 E01071 0 +OP4 E01072 0 +OP4 E01073 0 +OP4 E01074 0 +OP4 E01075 0 +OP4 E01076 0 +OP4 E01077 0 +OP4 E01078 0 +OP4 E01079 0 +OP4 E0107A 0 +OP4 E0107B 0 +OP4 E0107C 0 +OP4 E0107D 0 +OP4 E0107E 0 +OP4 E0107F 0 +OP4 E01080 0 +OP4 E01081 0 +OP4 E01082 0 +OP4 E01083 0 +OP4 E01084 0 +OP4 E01085 0 +OP4 E01086 0 +OP4 E01087 0 +OP4 E01088 0 +OP4 E01089 0 +OP4 E0108A 0 +OP4 E0108B 0 +OP4 E0108C 0 +OP4 E0108D 0 +OP4 E0108E 0 +OP4 E0108F 0 +OP4 E01090 0 +OP4 E01091 0 +OP4 E01092 0 +OP4 E01093 0 +OP4 E01094 0 +OP4 E01095 0 +OP4 E01096 0 +OP4 E01097 0 +OP4 E01098 0 +OP4 E01099 0 +OP4 E0109A 0 +OP4 E0109B 0 +OP4 E0109C 0 +OP4 E0109D 0 +OP4 E0109E 0 +OP4 E0109F 0 +OP4 E010A0 0 +OP4 E010A1 0 +OP4 E010A2 0 +OP4 E010A3 0 +OP4 E010A4 0 +OP4 E010A5 0 +OP4 E010A6 0 +OP4 E010A7 0 +OP4 E010A8 0 +OP4 E010A9 0 +OP4 E010AA 0 +OP4 E010AB 0 +OP4 E010AC 0 +OP4 E010AD 0 +OP4 E010AE 0 +OP4 E010AF 0 +OP4 E010B0 0 +OP4 E010B1 0 +OP4 E010B2 0 +OP4 E010B3 0 +OP4 E010B4 0 +OP4 E010B5 0 +OP4 E010B6 0 +OP4 E010B7 0 +OP4 E010B8 0 +OP4 E010B9 0 +OP4 E010BA 0 +OP4 E010BB 0 +OP4 E010BC 0 +OP4 E010BD 0 +OP4 E010BE 0 +OP4 E010BF 0 +OP4 E010C0 0 +OP4 E010C1 0 +OP4 E010C2 0 +OP4 E010C3 0 +OP4 E010C4 0 +OP4 E010C5 0 +OP4 E010C6 0 +OP4 E010C7 0 +OP4 E010C8 0 +OP4 E010C9 0 +OP4 E010CA 0 +OP4 E010CB 0 +OP4 E010CC 0 +OP4 E010CD 0 +OP4 E010CE 0 +OP4 E010CF 0 +OP4 E010D0 0 +OP4 E010D1 0 +OP4 E010D2 0 +OP4 E010D3 0 +OP4 E010D4 0 +OP4 E010D5 0 +OP4 E010D6 0 +OP4 E010D7 0 +OP4 E010D8 0 +OP4 E010D9 0 +OP4 E010DA 0 +OP4 E010DB 0 +OP4 E010DC 0 +OP4 E010DD 0 +OP4 E010DE 0 +OP4 E010DF 0 +OP4 E010E0 0 +OP4 E010E1 0 +OP4 E010E2 0 +OP4 E010E3 0 +OP4 E010E4 0 +OP4 E010E5 0 +OP4 E010E6 0 +OP4 E010E7 0 +OP4 E010E8 0 +OP4 E010E9 0 +OP4 E010EA 0 +OP4 E010EB 0 +OP4 E010EC 0 +OP4 E010ED 0 +OP4 E010EE 0 +OP4 E010EF 0 +OP4 E010F0 0 +OP4 E010F1 0 +OP4 E010F2 0 +OP4 E010F3 0 +OP4 E010F4 0 +OP4 E010F5 0 +OP4 E010F6 0 +OP4 E010F7 0 +OP4 E010F8 0 +OP4 E010F9 0 +OP4 E010FA 0 +OP4 E010FB 0 +OP4 E010FC 0 +OP4 E010FD 0 +OP4 E010FE 0 +OP4 E010FF 0 +OP4 E01100 0 +OP4 E01101 0 +OP4 E01102 0 +OP4 E01103 0 +OP4 E01104 0 +OP4 E01105 0 +OP4 E01106 0 +OP4 E01107 0 +OP4 E01108 0 +OP4 E01109 0 +OP4 E0110A 0 +OP4 E0110B 0 +OP4 E0110C 0 +OP4 E0110D 0 +OP4 E0110E 0 +OP4 E0110F 0 +OP4 E01110 0 +OP4 E01111 0 +OP4 E01112 0 +OP4 E01113 0 +OP4 E01114 0 +OP4 E01115 0 +OP4 E01116 0 +OP4 E01117 0 +OP4 E01118 0 +OP4 E01119 0 +OP4 E0111A 0 +OP4 E0111B 0 +OP4 E0111C 0 +OP4 E0111D 0 +OP4 E0111E 0 +OP4 E0111F 0 +OP4 E01120 0 +OP4 E01121 0 +OP4 E01122 0 +OP4 E01123 0 +OP4 E01124 0 +OP4 E01125 0 +OP4 E01126 0 +OP4 E01127 0 +OP4 E01128 0 +OP4 E01129 0 +OP4 E0112A 0 +OP4 E0112B 0 +OP4 E0112C 0 +OP4 E0112D 0 +OP4 E0112E 0 +OP4 E0112F 0 +OP4 E01130 0 +OP4 E01131 0 +OP4 E01132 0 +OP4 E01133 0 +OP4 E01134 0 +OP4 E01135 0 +OP4 E01136 0 +OP4 E01137 0 +OP4 E01138 0 +OP4 E01139 0 +OP4 E0113A 0 +OP4 E0113B 0 +OP4 E0113C 0 +OP4 E0113D 0 +OP4 E0113E 0 +OP4 E0113F 0 +OP4 E01140 0 +OP4 E01141 0 +OP4 E01142 0 +OP4 E01143 0 +OP4 E01144 0 +OP4 E01145 0 +OP4 E01146 0 +OP4 E01147 0 +OP4 E01148 0 +OP4 E01149 0 +OP4 E0114A 0 +OP4 E0114B 0 +OP4 E0114C 0 +OP4 E0114D 0 +OP4 E0114E 0 +OP4 E0114F 0 +OP4 E01150 0 +OP4 E01151 0 +OP4 E01152 0 +OP4 E01153 0 +OP4 E01154 0 +OP4 E01155 0 +OP4 E01156 0 +OP4 E01157 0 +OP4 E01158 0 +OP4 E01159 0 +OP4 E0115A 0 +OP4 E0115B 0 +OP4 E0115C 0 +OP4 E0115D 0 +OP4 E0115E 0 +OP4 E0115F 0 +OP4 E01160 0 +OP4 E01161 0 +OP4 E01162 0 +OP4 E01163 0 +OP4 E01164 0 +OP4 E01165 0 +OP4 E01166 0 +OP4 E01167 0 +OP4 E01168 0 +OP4 E01169 0 +OP4 E0116A 0 +OP4 E0116B 0 +OP4 E0116C 0 +OP4 E0116D 0 +OP4 E0116E 0 +OP4 E0116F 0 +OP4 E01170 0 +OP4 E01171 0 +OP4 E01172 0 +OP4 E01173 0 +OP4 E01174 0 +OP4 E01175 0 +OP4 E01176 0 +OP4 E01177 0 +OP4 E01178 0 +OP4 E01179 0 +OP4 E0117A 0 +OP4 E0117B 0 +OP4 E0117C 0 +OP4 E0117D 0 +OP4 E0117E 0 +OP4 E0117F 0 +OP4 E01180 0 +OP4 E01181 0 +OP4 E01182 0 +OP4 E01183 0 +OP4 E01184 0 +OP4 E01185 0 +OP4 E01186 0 +OP4 E01187 0 +OP4 E01188 0 +OP4 E01189 0 +OP4 E0118A 0 +OP4 E0118B 0 +OP4 E0118C 0 +OP4 E0118D 0 +OP4 E0118E 0 +OP4 E0118F 0 +OP4 E01190 0 +OP4 E01191 0 +OP4 E01192 0 +OP4 E01193 0 +OP4 E01194 0 +OP4 E01195 0 +OP4 E01196 0 +OP4 E01197 0 +OP4 E01198 0 +OP4 E01199 0 +OP4 E0119A 0 +OP4 E0119B 0 +OP4 E0119C 0 +OP4 E0119D 0 +OP4 E0119E 0 +OP4 E0119F 0 +OP4 E011A0 0 +OP4 E011A1 0 +OP4 E011A2 0 +OP4 E011A3 0 +OP4 E011A4 0 +OP4 E011A5 0 +OP4 E011A6 0 +OP4 E011A7 0 +OP4 E011A8 0 +OP4 E011A9 0 +OP4 E011AA 0 +OP4 E011AB 0 +OP4 E011AC 0 +OP4 E011AD 0 +OP4 E011AE 0 +OP4 E011AF 0 +OP4 E011B0 0 +OP4 E011B1 0 +OP4 E011B2 0 +OP4 E011B3 0 +OP4 E011B4 0 +OP4 E011B5 0 +OP4 E011B6 0 +OP4 E011B7 0 +OP4 E011B8 0 +OP4 E011B9 0 +OP4 E011BA 0 +OP4 E011BB 0 +OP4 E011BC 0 +OP4 E011BD 0 +OP4 E011BE 0 +OP4 E011BF 0 +OP4 E011C0 0 +OP4 E011C1 0 +OP4 E011C2 0 +OP4 E011C3 0 +OP4 E011C4 0 +OP4 E011C5 0 +OP4 E011C6 0 +OP4 E011C7 0 +OP4 E011C8 0 +OP4 E011C9 0 +OP4 E011CA 0 +OP4 E011CB 0 +OP4 E011CC 0 +OP4 E011CD 0 +OP4 E011CE 0 +OP4 E011CF 0 +OP4 E011D0 0 +OP4 E011D1 0 +OP4 E011D2 0 +OP4 E011D3 0 +OP4 E011D4 0 +OP4 E011D5 0 +OP4 E011D6 0 +OP4 E011D7 0 +OP4 E011D8 0 +OP4 E011D9 0 +OP4 E011DA 0 +OP4 E011DB 0 +OP4 E011DC 0 +OP4 E011DD 0 +OP4 E011DE 0 +OP4 E011DF 0 +OP4 E011E0 0 +OP4 E011E1 0 +OP4 E011E2 0 +OP4 E011E3 0 +OP4 E011E4 0 +OP4 E011E5 0 +OP4 E011E6 0 +OP4 E011E7 0 +OP4 E011E8 0 +OP4 E011E9 0 +OP4 E011EA 0 +OP4 E011EB 0 +OP4 E011EC 0 +OP4 E011ED 0 +OP4 E011EE 0 +OP4 E011EF 0 +OP4 E011F0 0 +OP4 E011F1 0 +OP4 E011F2 0 +OP4 E011F3 0 +OP4 E011F4 0 +OP4 E011F5 0 +OP4 E011F6 0 +OP4 E011F7 0 +OP4 E011F8 0 +OP4 E011F9 0 +OP4 E011FA 0 +OP4 E011FB 0 +OP4 E011FC 0 +OP4 E011FD 0 +OP4 E011FE 0 +OP4 E011FF 0 +OP4 E01200 0 +OP4 E01201 0 +OP4 E01202 0 +OP4 E01203 0 +OP4 E01204 0 +OP4 E01205 0 +OP4 E01206 0 +OP4 E01207 0 +OP4 E01208 0 +OP4 E01209 0 +OP4 E0120A 0 +OP4 E0120B 0 +OP4 E0120C 0 +OP4 E0120D 0 +OP4 E0120E 0 +OP4 E0120F 0 +OP4 E01210 0 +OP4 E01211 0 +OP4 E01212 0 +OP4 E01213 0 +OP4 E01214 0 +OP4 E01215 0 +OP4 E01216 0 +OP4 E01217 0 +OP4 E01218 0 +OP4 E01219 0 +OP4 E0121A 0 +OP4 E0121B 0 +OP4 E0121C 0 +OP4 E0121D 0 +OP4 E0121E 0 +OP4 E0121F 0 +OP4 E01220 0 +OP4 E01221 0 +OP4 E01222 0 +OP4 E01223 0 +OP4 E01224 0 +OP4 E01225 0 +OP4 E01226 0 +OP4 E01227 0 +OP4 E01228 0 +OP4 E01229 0 +OP4 E0122A 0 +OP4 E0122B 0 +OP4 E0122C 0 +OP4 E0122D 0 +OP4 E0122E 0 +OP4 E0122F 0 +OP4 E01230 0 +OP4 E01231 0 +OP4 E01232 0 +OP4 E01233 0 +OP4 E01234 0 +OP4 E01235 0 +OP4 E01236 0 +OP4 E01237 0 +OP4 E01238 0 +OP4 E01239 0 +OP4 E0123A 0 +OP4 E0123B 0 +OP4 E0123C 0 +OP4 E0123D 0 +OP4 E0123E 0 +OP4 E0123F 0 +OP4 E01240 0 +OP4 E01241 0 +OP4 E01242 0 +OP4 E01243 0 +OP4 E01244 0 +OP4 E01245 0 +OP4 E01246 0 +OP4 E01247 0 +OP4 E01248 0 +OP4 E01249 0 +OP4 E0124A 0 +OP4 E0124B 0 +OP4 E0124C 0 +OP4 E0124D 0 +OP4 E0124E 0 +OP4 E0124F 0 +OP4 E01250 0 +OP4 E01251 0 +OP4 E01252 0 +OP4 E01253 0 +OP4 E01254 0 +OP4 E01255 0 +OP4 E01256 0 +OP4 E01257 0 +OP4 E01258 0 +OP4 E01259 0 +OP4 E0125A 0 +OP4 E0125B 0 +OP4 E0125C 0 +OP4 E0125D 0 +OP4 E0125E 0 +OP4 E0125F 0 +OP4 E01260 0 +OP4 E01261 0 +OP4 E01262 0 +OP4 E01263 0 +OP4 E01264 0 +OP4 E01265 0 +OP4 E01266 0 +OP4 E01267 0 +OP4 E01268 0 +OP4 E01269 0 +OP4 E0126A 0 +OP4 E0126B 0 +OP4 E0126C 0 +OP4 E0126D 0 +OP4 E0126E 0 +OP4 E0126F 0 +OP4 E01270 0 +OP4 E01271 0 +OP4 E01272 0 +OP4 E01273 0 +OP4 E01274 0 +OP4 E01275 0 +OP4 E01276 0 +OP4 E01277 0 +OP4 E01278 0 +OP4 E01279 0 +OP4 E0127A 0 +OP4 E0127B 0 +OP4 E0127C 0 +OP4 E0127D 0 +OP4 E0127E 0 +OP4 E0127F 0 +OP4 E01280 0 +OP4 E01281 0 +OP4 E01282 0 +OP4 E01283 0 +OP4 E01284 0 +OP4 E01285 0 +OP4 E01286 0 +OP4 E01287 0 +OP4 E01288 0 +OP4 E01289 0 +OP4 E0128A 0 +OP4 E0128B 0 +OP4 E0128C 0 +OP4 E0128D 0 +OP4 E0128E 0 +OP4 E0128F 0 +OP4 E01290 0 +OP4 E01291 0 +OP4 E01292 0 +OP4 E01293 0 +OP4 E01294 0 +OP4 E01295 0 +OP4 E01296 0 +OP4 E01297 0 +OP4 E01298 0 +OP4 E01299 0 +OP4 E0129A 0 +OP4 E0129B 0 +OP4 E0129C 0 +OP4 E0129D 0 +OP4 E0129E 0 +OP4 E0129F 0 +OP4 E012A0 0 +OP4 E012A1 0 +OP4 E012A2 0 +OP4 E012A3 0 +OP4 E012A4 0 +OP4 E012A5 0 +OP4 E012A6 0 +OP4 E012A7 0 +OP4 E012A8 0 +OP4 E012A9 0 +OP4 E012AA 0 +OP4 E012AB 0 +OP4 E012AC 0 +OP4 E012AD 0 +OP4 E012AE 0 +OP4 E012AF 0 +OP4 E012B0 0 +OP4 E012B1 0 +OP4 E012B2 0 +OP4 E012B3 0 +OP4 E012B4 0 +OP4 E012B5 0 +OP4 E012B6 0 +OP4 E012B7 0 +OP4 E012B8 0 +OP4 E012B9 0 +OP4 E012BA 0 +OP4 E012BB 0 +OP4 E012BC 0 +OP4 E012BD 0 +OP4 E012BE 0 +OP4 E012BF 0 +OP4 E012C0 0 +OP4 E012C1 0 +OP4 E012C2 0 +OP4 E012C3 0 +OP4 E012C4 0 +OP4 E012C5 0 +OP4 E012C6 0 +OP4 E012C7 0 +OP4 E012C8 0 +OP4 E012C9 0 +OP4 E012CA 0 +OP4 E012CB 0 +OP4 E012CC 0 +OP4 E012CD 0 +OP4 E012CE 0 +OP4 E012CF 0 +OP4 E012D0 0 +OP4 E012D1 0 +OP4 E012D2 0 +OP4 E012D3 0 +OP4 E012D4 0 +OP4 E012D5 0 +OP4 E012D6 0 +OP4 E012D7 0 +OP4 E012D8 0 +OP4 E012D9 0 +OP4 E012DA 0 +OP4 E012DB 0 +OP4 E012DC 0 +OP4 E012DD 0 +OP4 E012DE 0 +OP4 E012DF 0 +OP4 E012E0 0 +OP4 E012E1 0 +OP4 E012E2 0 +OP4 E012E3 0 +OP4 E012E4 0 +OP4 E012E5 0 +OP4 E012E6 0 +OP4 E012E7 0 +OP4 E012E8 0 +OP4 E012E9 0 +OP4 E012EA 0 +OP4 E012EB 0 +OP4 E012EC 0 +OP4 E012ED 0 +OP4 E012EE 0 +OP4 E012EF 0 +OP4 E012F0 0 +OP4 E012F1 0 +OP4 E012F2 0 +OP4 E012F3 0 +OP4 E012F4 0 +OP4 E012F5 0 +OP4 E012F6 0 +OP4 E012F7 0 +OP4 E012F8 0 +OP4 E012F9 0 +OP4 E012FA 0 +OP4 E012FB 0 +OP4 E012FC 0 +OP4 E012FD 0 +OP4 E012FE 0 +OP4 E012FF 0 +OP4 E01300 0 +OP4 E01301 0 +OP4 E01302 0 +OP4 E01303 0 +OP4 E01304 0 +OP4 E01305 0 +OP4 E01306 0 +OP4 E01307 0 +OP4 E01308 0 +OP4 E01309 0 +OP4 E0130A 0 +OP4 E0130B 0 +OP4 E0130C 0 +OP4 E0130D 0 +OP4 E0130E 0 +OP4 E0130F 0 +OP4 E01310 0 +OP4 E01311 0 +OP4 E01312 0 +OP4 E01313 0 +OP4 E01314 0 +OP4 E01315 0 +OP4 E01316 0 +OP4 E01317 0 +OP4 E01318 0 +OP4 E01319 0 +OP4 E0131A 0 +OP4 E0131B 0 +OP4 E0131C 0 +OP4 E0131D 0 +OP4 E0131E 0 +OP4 E0131F 0 +OP4 E01320 0 +OP4 E01321 0 +OP4 E01322 0 +OP4 E01323 0 +OP4 E01324 0 +OP4 E01325 0 +OP4 E01326 0 +OP4 E01327 0 +OP4 E01328 0 +OP4 E01329 0 +OP4 E0132A 0 +OP4 E0132B 0 +OP4 E0132C 0 +OP4 E0132D 0 +OP4 E0132E 0 +OP4 E0132F 0 +OP4 E01330 0 +OP4 E01331 0 +OP4 E01332 0 +OP4 E01333 0 +OP4 E01334 0 +OP4 E01335 0 +OP4 E01336 0 +OP4 E01337 0 +OP4 E01338 0 +OP4 E01339 0 +OP4 E0133A 0 +OP4 E0133B 0 +OP4 E0133C 0 +OP4 E0133D 0 +OP4 E0133E 0 +OP4 E0133F 0 +OP4 E01340 0 +OP4 E01341 0 +OP4 E01342 0 +OP4 E01343 0 +OP4 E01344 0 +OP4 E01345 0 +OP4 E01346 0 +OP4 E01347 0 +OP4 E01348 0 +OP4 E01349 0 +OP4 E0134A 0 +OP4 E0134B 0 +OP4 E0134C 0 +OP4 E0134D 0 +OP4 E0134E 0 +OP4 E0134F 0 +OP4 E01350 0 +OP4 E01351 0 +OP4 E01352 0 +OP4 E01353 0 +OP4 E01354 0 +OP4 E01355 0 +OP4 E01356 0 +OP4 E01357 0 +OP4 E01358 0 +OP4 E01359 0 +OP4 E0135A 0 +OP4 E0135B 0 +OP4 E0135C 0 +OP4 E0135D 0 +OP4 E0135E 0 +OP4 E0135F 0 +OP4 E01360 0 +OP4 E01361 0 +OP4 E01362 0 +OP4 E01363 0 +OP4 E01364 0 +OP4 E01365 0 +OP4 E01366 0 +OP4 E01367 0 +OP4 E01368 0 +OP4 E01369 0 +OP4 E0136A 0 +OP4 E0136B 0 +OP4 E0136C 0 +OP4 E0136D 0 +OP4 E0136E 0 +OP4 E0136F 0 +OP4 E01370 0 +OP4 E01371 0 +OP4 E01372 0 +OP4 E01373 0 +OP4 E01374 0 +OP4 E01375 0 +OP4 E01376 0 +OP4 E01377 0 +OP4 E01378 0 +OP4 E01379 0 +OP4 E0137A 0 +OP4 E0137B 0 +OP4 E0137C 0 +OP4 E0137D 0 +OP4 E0137E 0 +OP4 E0137F 0 +OP4 E01380 0 +OP4 E01381 0 +OP4 E01382 0 +OP4 E01383 0 +OP4 E01384 0 +OP4 E01385 0 +OP4 E01386 0 +OP4 E01387 0 +OP4 E01388 0 +OP4 E01389 0 +OP4 E0138A 0 +OP4 E0138B 0 +OP4 E0138C 0 +OP4 E0138D 0 +OP4 E0138E 0 +OP4 E0138F 0 +OP4 E01390 0 +OP4 E01391 0 +OP4 E01392 0 +OP4 E01393 0 +OP4 E01394 0 +OP4 E01395 0 +OP4 E01396 0 +OP4 E01397 0 +OP4 E01398 0 +OP4 E01399 0 +OP4 E0139A 0 +OP4 E0139B 0 +OP4 E0139C 0 +OP4 E0139D 0 +OP4 E0139E 0 +OP4 E0139F 0 +OP4 E013A0 0 +OP4 E013A1 0 +OP4 E013A2 0 +OP4 E013A3 0 +OP4 E013A4 0 +OP4 E013A5 0 +OP4 E013A6 0 +OP4 E013A7 0 +OP4 E013A8 0 +OP4 E013A9 0 +OP4 E013AA 0 +OP4 E013AB 0 +OP4 E013AC 0 +OP4 E013AD 0 +OP4 E013AE 0 +OP4 E013AF 0 +OP4 E013B0 0 +OP4 E013B1 0 +OP4 E013B2 0 +OP4 E013B3 0 +OP4 E013B4 0 +OP4 E013B5 0 +OP4 E013B6 0 +OP4 E013B7 0 +OP4 E013B8 0 +OP4 E013B9 0 +OP4 E013BA 0 +OP4 E013BB 0 +OP4 E013BC 0 +OP4 E013BD 0 +OP4 E013BE 0 +OP4 E013BF 0 +OP4 E013C0 0 +OP4 E013C1 0 +OP4 E013C2 0 +OP4 E013C3 0 +OP4 E013C4 0 +OP4 E013C5 0 +OP4 E013C6 0 +OP4 E013C7 0 +OP4 E013C8 0 +OP4 E013C9 0 +OP4 E013CA 0 +OP4 E013CB 0 +OP4 E013CC 0 +OP4 E013CD 0 +OP4 E013CE 0 +OP4 E013CF 0 +OP4 E013D0 0 +OP4 E013D1 0 +OP4 E013D2 0 +OP4 E013D3 0 +OP4 E013D4 0 +OP4 E013D5 0 +OP4 E013D6 0 +OP4 E013D7 0 +OP4 E013D8 0 +OP4 E013D9 0 +OP4 E013DA 0 +OP4 E013DB 0 +OP4 E013DC 0 +OP4 E013DD 0 +OP4 E013DE 0 +OP4 E013DF 0 +OP4 E013E0 0 +OP4 E013E1 0 +OP4 E013E2 0 +OP4 E013E3 0 +OP4 E013E4 0 +OP4 E013E5 0 +OP4 E013E6 0 +OP4 E013E7 0 +OP4 E013E8 0 +OP4 E013E9 0 +OP4 E013EA 0 +OP4 E013EB 0 +OP4 E013EC 0 +OP4 E013ED 0 +OP4 E013EE 0 +OP4 E013EF 0 +OP4 E013F0 0 +OP4 E013F1 0 +OP4 E013F2 0 +OP4 E013F3 0 +OP4 E013F4 0 +OP4 E013F5 0 +OP4 E013F6 0 +OP4 E013F7 0 +OP4 E013F8 0 +OP4 E013F9 0 +OP4 E013FA 0 +OP4 E013FB 0 +OP4 E013FC 0 +OP4 E013FD 0 +OP4 E013FE 0 +OP4 E013FF 0 +OP4 E01400 0 +OP4 E01401 0 +OP4 E01402 0 +OP4 E01403 0 +OP4 E01404 0 +OP4 E01405 0 +OP4 E01406 0 +OP4 E01407 0 +OP4 E01408 0 +OP4 E01409 0 +OP4 E0140A 0 +OP4 E0140B 0 +OP4 E0140C 0 +OP4 E0140D 0 +OP4 E0140E 0 +OP4 E0140F 0 +OP4 E01410 0 +OP4 E01411 0 +OP4 E01412 0 +OP4 E01413 0 +OP4 E01414 0 +OP4 E01415 0 +OP4 E01416 0 +OP4 E01417 0 +OP4 E01418 0 +OP4 E01419 0 +OP4 E0141A 0 +OP4 E0141B 0 +OP4 E0141C 0 +OP4 E0141D 0 +OP4 E0141E 0 +OP4 E0141F 0 +OP4 E01420 0 +OP4 E01421 0 +OP4 E01422 0 +OP4 E01423 0 +OP4 E01424 0 +OP4 E01425 0 +OP4 E01426 0 +OP4 E01427 0 +OP4 E01428 0 +OP4 E01429 0 +OP4 E0142A 0 +OP4 E0142B 0 +OP4 E0142C 0 +OP4 E0142D 0 +OP4 E0142E 0 +OP4 E0142F 0 +OP4 E01430 0 +OP4 E01431 0 +OP4 E01432 0 +OP4 E01433 0 +OP4 E01434 0 +OP4 E01435 0 +OP4 E01436 0 +OP4 E01437 0 +OP4 E01438 0 +OP4 E01439 0 +OP4 E0143A 0 +OP4 E0143B 0 +OP4 E0143C 0 +OP4 E0143D 0 +OP4 E0143E 0 +OP4 E0143F 0 +OP4 E01440 0 +OP4 E01441 0 +OP4 E01442 0 +OP4 E01443 0 +OP4 E01444 0 +OP4 E01445 0 +OP4 E01446 0 +OP4 E01447 0 +OP4 E01448 0 +OP4 E01449 0 +OP4 E0144A 0 +OP4 E0144B 0 +OP4 E0144C 0 +OP4 E0144D 0 +OP4 E0144E 0 +OP4 E0144F 0 +OP4 E01450 0 +OP4 E01451 0 +OP4 E01452 0 +OP4 E01453 0 +OP4 E01454 0 +OP4 E01455 0 +OP4 E01456 0 +OP4 E01457 0 +OP4 E01458 0 +OP4 E01459 0 +OP4 E0145A 0 +OP4 E0145B 0 +OP4 E0145C 0 +OP4 E0145D 0 +OP4 E0145E 0 +OP4 E0145F 0 +OP4 E01460 0 +OP4 E01461 0 +OP4 E01462 0 +OP4 E01463 0 +OP4 E01464 0 +OP4 E01465 0 +OP4 E01466 0 +OP4 E01467 0 +OP4 E01468 0 +OP4 E01469 0 +OP4 E0146A 0 +OP4 E0146B 0 +OP4 E0146C 0 +OP4 E0146D 0 +OP4 E0146E 0 +OP4 E0146F 0 +OP4 E01470 0 +OP4 E01471 0 +OP4 E01472 0 +OP4 E01473 0 +OP4 E01474 0 +OP4 E01475 0 +OP4 E01476 0 +OP4 E01477 0 +OP4 E01478 0 +OP4 E01479 0 +OP4 E0147A 0 +OP4 E0147B 0 +OP4 E0147C 0 +OP4 E0147D 0 +OP4 E0147E 0 +OP4 E0147F 0 +OP4 E01480 0 +OP4 E01481 0 +OP4 E01482 0 +OP4 E01483 0 +OP4 E01484 0 +OP4 E01485 0 +OP4 E01486 0 +OP4 E01487 0 +OP4 E01488 0 +OP4 E01489 0 +OP4 E0148A 0 +OP4 E0148B 0 +OP4 E0148C 0 +OP4 E0148D 0 +OP4 E0148E 0 +OP4 E0148F 0 +OP4 E01490 0 +OP4 E01491 0 +OP4 E01492 0 +OP4 E01493 0 +OP4 E01494 0 +OP4 E01495 0 +OP4 E01496 0 +OP4 E01497 0 +OP4 E01498 0 +OP4 E01499 0 +OP4 E0149A 0 +OP4 E0149B 0 +OP4 E0149C 0 +OP4 E0149D 0 +OP4 E0149E 0 +OP4 E0149F 0 +OP4 E014A0 0 +OP4 E014A1 0 +OP4 E014A2 0 +OP4 E014A3 0 +OP4 E014A4 0 +OP4 E014A5 0 +OP4 E014A6 0 +OP4 E014A7 0 +OP4 E014A8 0 +OP4 E014A9 0 +OP4 E014AA 0 +OP4 E014AB 0 +OP4 E014AC 0 +OP4 E014AD 0 +OP4 E014AE 0 +OP4 E014AF 0 +OP4 E014B0 0 +OP4 E014B1 0 +OP4 E014B2 0 +OP4 E014B3 0 +OP4 E014B4 0 +OP4 E014B5 0 +OP4 E014B6 0 +OP4 E014B7 0 +OP4 E014B8 0 +OP4 E014B9 0 +OP4 E014BA 0 +OP4 E014BB 0 +OP4 E014BC 0 +OP4 E014BD 0 +OP4 E014BE 0 +OP4 E014BF 0 +OP4 E014C0 0 +OP4 E014C1 0 +OP4 E014C2 0 +OP4 E014C3 0 +OP4 E014C4 0 +OP4 E014C5 0 +OP4 E014C6 0 +OP4 E014C7 0 +OP4 E014C8 0 +OP4 E014C9 0 +OP4 E014CA 0 +OP4 E014CB 0 +OP4 E014CC 0 +OP4 E014CD 0 +OP4 E014CE 0 +OP4 E014CF 0 +OP4 E014D0 0 +OP4 E014D1 0 +OP4 E014D2 0 +OP4 E014D3 0 +OP4 E014D4 0 +OP4 E014D5 0 +OP4 E014D6 0 +OP4 E014D7 0 +OP4 E014D8 0 +OP4 E014D9 0 +OP4 E014DA 0 +OP4 E014DB 0 +OP4 E014DC 0 +OP4 E014DD 0 +OP4 E014DE 0 +OP4 E014DF 0 +OP4 E014E0 0 +OP4 E014E1 0 +OP4 E014E2 0 +OP4 E014E3 0 +OP4 E014E4 0 +OP4 E014E5 0 +OP4 E014E6 0 +OP4 E014E7 0 +OP4 E014E8 0 +OP4 E014E9 0 +OP4 E014EA 0 +OP4 E014EB 0 +OP4 E014EC 0 +OP4 E014ED 0 +OP4 E014EE 0 +OP4 E014EF 0 +OP4 E014F0 0 +OP4 E014F1 0 +OP4 E014F2 0 +OP4 E014F3 0 +OP4 E014F4 0 +OP4 E014F5 0 +OP4 E014F6 0 +OP4 E014F7 0 +OP4 E014F8 0 +OP4 E014F9 0 +OP4 E014FA 0 +OP4 E014FB 0 +OP4 E014FC 0 +OP4 E014FD 0 +OP4 E014FE 0 +OP4 E014FF 0 +OP4 E01500 0 +OP4 E01501 0 +OP4 E01502 0 +OP4 E01503 0 +OP4 E01504 0 +OP4 E01505 0 +OP4 E01506 0 +OP4 E01507 0 +OP4 E01508 0 +OP4 E01509 0 +OP4 E0150A 0 +OP4 E0150B 0 +OP4 E0150C 0 +OP4 E0150D 0 +OP4 E0150E 0 +OP4 E0150F 0 +OP4 E01510 0 +OP4 E01511 0 +OP4 E01512 0 +OP4 E01513 0 +OP4 E01514 0 +OP4 E01515 0 +OP4 E01516 0 +OP4 E01517 0 +OP4 E01518 0 +OP4 E01519 0 +OP4 E0151A 0 +OP4 E0151B 0 +OP4 E0151C 0 +OP4 E0151D 0 +OP4 E0151E 0 +OP4 E0151F 0 +OP4 E01520 0 +OP4 E01521 0 +OP4 E01522 0 +OP4 E01523 0 +OP4 E01524 0 +OP4 E01525 0 +OP4 E01526 0 +OP4 E01527 0 +OP4 E01528 0 +OP4 E01529 0 +OP4 E0152A 0 +OP4 E0152B 0 +OP4 E0152C 0 +OP4 E0152D 0 +OP4 E0152E 0 +OP4 E0152F 0 +OP4 E01530 0 +OP4 E01531 0 +OP4 E01532 0 +OP4 E01533 0 +OP4 E01534 0 +OP4 E01535 0 +OP4 E01536 0 +OP4 E01537 0 +OP4 E01538 0 +OP4 E01539 0 +OP4 E0153A 0 +OP4 E0153B 0 +OP4 E0153C 0 +OP4 E0153D 0 +OP4 E0153E 0 +OP4 E0153F 0 +OP4 E01540 0 +OP4 E01541 0 +OP4 E01542 0 +OP4 E01543 0 +OP4 E01544 0 +OP4 E01545 0 +OP4 E01546 0 +OP4 E01547 0 +OP4 E01548 0 +OP4 E01549 0 +OP4 E0154A 0 +OP4 E0154B 0 +OP4 E0154C 0 +OP4 E0154D 0 +OP4 E0154E 0 +OP4 E0154F 0 +OP4 E01550 0 +OP4 E01551 0 +OP4 E01552 0 +OP4 E01553 0 +OP4 E01554 0 +OP4 E01555 0 +OP4 E01556 0 +OP4 E01557 0 +OP4 E01558 0 +OP4 E01559 0 +OP4 E0155A 0 +OP4 E0155B 0 +OP4 E0155C 0 +OP4 E0155D 0 +OP4 E0155E 0 +OP4 E0155F 0 +OP4 E01560 0 +OP4 E01561 0 +OP4 E01562 0 +OP4 E01563 0 +OP4 E01564 0 +OP4 E01565 0 +OP4 E01566 0 +OP4 E01567 0 +OP4 E01568 0 +OP4 E01569 0 +OP4 E0156A 0 +OP4 E0156B 0 +OP4 E0156C 0 +OP4 E0156D 0 +OP4 E0156E 0 +OP4 E0156F 0 +OP4 E01570 0 +OP4 E01571 0 +OP4 E01572 0 +OP4 E01573 0 +OP4 E01574 0 +OP4 E01575 0 +OP4 E01576 0 +OP4 E01577 0 +OP4 E01578 0 +OP4 E01579 0 +OP4 E0157A 0 +OP4 E0157B 0 +OP4 E0157C 0 +OP4 E0157D 0 +OP4 E0157E 0 +OP4 E0157F 0 +OP4 E01580 0 +OP4 E01581 0 +OP4 E01582 0 +OP4 E01583 0 +OP4 E01584 0 +OP4 E01585 0 +OP4 E01586 0 +OP4 E01587 0 +OP4 E01588 0 +OP4 E01589 0 +OP4 E0158A 0 +OP4 E0158B 0 +OP4 E0158C 0 +OP4 E0158D 0 +OP4 E0158E 0 +OP4 E0158F 0 +OP4 E01590 0 +OP4 E01591 0 +OP4 E01592 0 +OP4 E01593 0 +OP4 E01594 0 +OP4 E01595 0 +OP4 E01596 0 +OP4 E01597 0 +OP4 E01598 0 +OP4 E01599 0 +OP4 E0159A 0 +OP4 E0159B 0 +OP4 E0159C 0 +OP4 E0159D 0 +OP4 E0159E 0 +OP4 E0159F 0 +OP4 E015A0 0 +OP4 E015A1 0 +OP4 E015A2 0 +OP4 E015A3 0 +OP4 E015A4 0 +OP4 E015A5 0 +OP4 E015A6 0 +OP4 E015A7 0 +OP4 E015A8 0 +OP4 E015A9 0 +OP4 E015AA 0 +OP4 E015AB 0 +OP4 E015AC 0 +OP4 E015AD 0 +OP4 E015AE 0 +OP4 E015AF 0 +OP4 E015B0 0 +OP4 E015B1 0 +OP4 E015B2 0 +OP4 E015B3 0 +OP4 E015B4 0 +OP4 E015B5 0 +OP4 E015B6 0 +OP4 E015B7 0 +OP4 E015B8 0 +OP4 E015B9 0 +OP4 E015BA 0 +OP4 E015BB 0 +OP4 E015BC 0 +OP4 E015BD 0 +OP4 E015BE 0 +OP4 E015BF 0 +OP4 E015C0 0 +OP4 E015C1 0 +OP4 E015C2 0 +OP4 E015C3 0 +OP4 E015C4 0 +OP4 E015C5 0 +OP4 E015C6 0 +OP4 E015C7 0 +OP4 E015C8 0 +OP4 E015C9 0 +OP4 E015CA 0 +OP4 E015CB 0 +OP4 E015CC 0 +OP4 E015CD 0 +OP4 E015CE 0 +OP4 E015CF 0 +OP4 E015D0 0 +OP4 E015D1 0 +OP4 E015D2 0 +OP4 E015D3 0 +OP4 E015D4 0 +OP4 E015D5 0 +OP4 E015D6 0 +OP4 E015D7 0 +OP4 E015D8 0 +OP4 E015D9 0 +OP4 E015DA 0 +OP4 E015DB 0 +OP4 E015DC 0 +OP4 E015DD 0 +OP4 E015DE 0 +OP4 E015DF 0 +OP4 E015E0 0 +OP4 E015E1 0 +OP4 E015E2 0 +OP4 E015E3 0 +OP4 E015E4 0 +OP4 E015E5 0 +OP4 E015E6 0 +OP4 E015E7 0 +OP4 E015E8 0 +OP4 E015E9 0 +OP4 E015EA 0 +OP4 E015EB 0 +OP4 E015EC 0 +OP4 E015ED 0 +OP4 E015EE 0 +OP4 E015EF 0 +OP4 E015F0 0 +OP4 E015F1 0 +OP4 E015F2 0 +OP4 E015F3 0 +OP4 E015F4 0 +OP4 E015F5 0 +OP4 E015F6 0 +OP4 E015F7 0 +OP4 E015F8 0 +OP4 E015F9 0 +OP4 E015FA 0 +OP4 E015FB 0 +OP4 E015FC 0 +OP4 E015FD 0 +OP4 E015FE 0 +OP4 E015FF 0 +OP4 E01600 0 +OP4 E01601 0 +OP4 E01602 0 +OP4 E01603 0 +OP4 E01604 0 +OP4 E01605 0 +OP4 E01606 0 +OP4 E01607 0 +OP4 E01608 0 +OP4 E01609 0 +OP4 E0160A 0 +OP4 E0160B 0 +OP4 E0160C 0 +OP4 E0160D 0 +OP4 E0160E 0 +OP4 E0160F 0 +OP4 E01610 0 +OP4 E01611 0 +OP4 E01612 0 +OP4 E01613 0 +OP4 E01614 0 +OP4 E01615 0 +OP4 E01616 0 +OP4 E01617 0 +OP4 E01618 0 +OP4 E01619 0 +OP4 E0161A 0 +OP4 E0161B 0 +OP4 E0161C 0 +OP4 E0161D 0 +OP4 E0161E 0 +OP4 E0161F 0 +OP4 E01620 0 +OP4 E01621 0 +OP4 E01622 0 +OP4 E01623 0 +OP4 E01624 0 +OP4 E01625 0 +OP4 E01626 0 +OP4 E01627 0 +OP4 E01628 0 +OP4 E01629 0 +OP4 E0162A 0 +OP4 E0162B 0 +OP4 E0162C 0 +OP4 E0162D 0 +OP4 E0162E 0 +OP4 E0162F 0 +OP4 E01630 0 +OP4 E01631 0 +OP4 E01632 0 +OP4 E01633 0 +OP4 E01634 0 +OP4 E01635 0 +OP4 E01636 0 +OP4 E01637 0 +OP4 E01638 0 +OP4 E01639 0 +OP4 E0163A 0 +OP4 E0163B 0 +OP4 E0163C 0 +OP4 E0163D 0 +OP4 E0163E 0 +OP4 E0163F 0 +OP4 E01640 0 +OP4 E01641 0 +OP4 E01642 0 +OP4 E01643 0 +OP4 E01644 0 +OP4 E01645 0 +OP4 E01646 0 +OP4 E01647 0 +OP4 E01648 0 +OP4 E01649 0 +OP4 E0164A 0 +OP4 E0164B 0 +OP4 E0164C 0 +OP4 E0164D 0 +OP4 E0164E 0 +OP4 E0164F 0 +OP4 E01650 0 +OP4 E01651 0 +OP4 E01652 0 +OP4 E01653 0 +OP4 E01654 0 +OP4 E01655 0 +OP4 E01656 0 +OP4 E01657 0 +OP4 E01658 0 +OP4 E01659 0 +OP4 E0165A 0 +OP4 E0165B 0 +OP4 E0165C 0 +OP4 E0165D 0 +OP4 E0165E 0 +OP4 E0165F 0 +OP4 E01660 0 +OP4 E01661 0 +OP4 E01662 0 +OP4 E01663 0 +OP4 E01664 0 +OP4 E01665 0 +OP4 E01666 0 +OP4 E01667 0 +OP4 E01668 0 +OP4 E01669 0 +OP4 E0166A 0 +OP4 E0166B 0 +OP4 E0166C 0 +OP4 E0166D 0 +OP4 E0166E 0 +OP4 E0166F 0 +OP4 E01670 0 +OP4 E01671 0 +OP4 E01672 0 +OP4 E01673 0 +OP4 E01674 0 +OP4 E01675 0 +OP4 E01676 0 +OP4 E01677 0 +OP4 E01678 0 +OP4 E01679 0 +OP4 E0167A 0 +OP4 E0167B 0 +OP4 E0167C 0 +OP4 E0167D 0 +OP4 E0167E 0 +OP4 E0167F 0 +OP4 E01680 0 +OP4 E01681 0 +OP4 E01682 0 +OP4 E01683 0 +OP4 E01684 0 +OP4 E01685 0 +OP4 E01686 0 +OP4 E01687 0 +OP4 E01688 0 +OP4 E01689 0 +OP4 E0168A 0 +OP4 E0168B 0 +OP4 E0168C 0 +OP4 E0168D 0 +OP4 E0168E 0 +OP4 E0168F 0 +OP4 E01690 0 +OP4 E01691 0 +OP4 E01692 0 +OP4 E01693 0 +OP4 E01694 0 +OP4 E01695 0 +OP4 E01696 0 +OP4 E01697 0 +OP4 E01698 0 +OP4 E01699 0 +OP4 E0169A 0 +OP4 E0169B 0 +OP4 E0169C 0 +OP4 E0169D 0 +OP4 E0169E 0 +OP4 E0169F 0 +OP4 E016A0 0 +OP4 E016A1 0 +OP4 E016A2 0 +OP4 E016A3 0 +OP4 E016A4 0 +OP4 E016A5 0 +OP4 E016A6 0 +OP4 E016A7 0 +OP4 E016A8 0 +OP4 E016A9 0 +OP4 E016AA 0 +OP4 E016AB 0 +OP4 E016AC 0 +OP4 E016AD 0 +OP4 E016AE 0 +OP4 E016AF 0 +OP4 E016B0 0 +OP4 E016B1 0 +OP4 E016B2 0 +OP4 E016B3 0 +OP4 E016B4 0 +OP4 E016B5 0 +OP4 E016B6 0 +OP4 E016B7 0 +OP4 E016B8 0 +OP4 E016B9 0 +OP4 E016BA 0 +OP4 E016BB 0 +OP4 E016BC 0 +OP4 E016BD 0 +OP4 E016BE 0 +OP4 E016BF 0 +OP4 E016C0 0 +OP4 E016C1 0 +OP4 E016C2 0 +OP4 E016C3 0 +OP4 E016C4 0 +OP4 E016C5 0 +OP4 E016C6 0 +OP4 E016C7 0 +OP4 E016C8 0 +OP4 E016C9 0 +OP4 E016CA 0 +OP4 E016CB 0 +OP4 E016CC 0 +OP4 E016CD 0 +OP4 E016CE 0 +OP4 E016CF 0 +OP4 E016D0 0 +OP4 E016D1 0 +OP4 E016D2 0 +OP4 E016D3 0 +OP4 E016D4 0 +OP4 E016D5 0 +OP4 E016D6 0 +OP4 E016D7 0 +OP4 E016D8 0 +OP4 E016D9 0 +OP4 E016DA 0 +OP4 E016DB 0 +OP4 E016DC 0 +OP4 E016DD 0 +OP4 E016DE 0 +OP4 E016DF 0 +OP4 E016E0 0 +OP4 E016E1 0 +OP4 E016E2 0 +OP4 E016E3 0 +OP4 E016E4 0 +OP4 E016E5 0 +OP4 E016E6 0 +OP4 E016E7 0 +OP4 E016E8 0 +OP4 E016E9 0 +OP4 E016EA 0 +OP4 E016EB 0 +OP4 E016EC 0 +OP4 E016ED 0 +OP4 E016EE 0 +OP4 E016EF 0 +OP4 E016F0 0 +OP4 E016F1 0 +OP4 E016F2 0 +OP4 E016F3 0 +OP4 E016F4 0 +OP4 E016F5 0 +OP4 E016F6 0 +OP4 E016F7 0 +OP4 E016F8 0 +OP4 E016F9 0 +OP4 E016FA 0 +OP4 E016FB 0 +OP4 E016FC 0 +OP4 E016FD 0 +OP4 E016FE 0 +OP4 E016FF 0 +OP4 E01700 0 +OP4 E01701 0 +OP4 E01702 0 +OP4 E01703 0 +OP4 E01704 0 +OP4 E01705 0 +OP4 E01706 0 +OP4 E01707 0 +OP4 E01708 0 +OP4 E01709 0 +OP4 E0170A 0 +OP4 E0170B 0 +OP4 E0170C 0 +OP4 E0170D 0 +OP4 E0170E 0 +OP4 E0170F 0 +OP4 E01710 0 +OP4 E01711 0 +OP4 E01712 0 +OP4 E01713 0 +OP4 E01714 0 +OP4 E01715 0 +OP4 E01716 0 +OP4 E01717 0 +OP4 E01718 0 +OP4 E01719 0 +OP4 E0171A 0 +OP4 E0171B 0 +OP4 E0171C 0 +OP4 E0171D 0 +OP4 E0171E 0 +OP4 E0171F 0 +OP4 E01720 0 +OP4 E01721 0 +OP4 E01722 0 +OP4 E01723 0 +OP4 E01724 0 +OP4 E01725 0 +OP4 E01726 0 +OP4 E01727 0 +OP4 E01728 0 +OP4 E01729 0 +OP4 E0172A 0 +OP4 E0172B 0 +OP4 E0172C 0 +OP4 E0172D 0 +OP4 E0172E 0 +OP4 E0172F 0 +OP4 E01730 0 +OP4 E01731 0 +OP4 E01732 0 +OP4 E01733 0 +OP4 E01734 0 +OP4 E01735 0 +OP4 E01736 0 +OP4 E01737 0 +OP4 E01738 0 +OP4 E01739 0 +OP4 E0173A 0 +OP4 E0173B 0 +OP4 E0173C 0 +OP4 E0173D 0 +OP4 E0173E 0 +OP4 E0173F 0 +OP4 E01740 0 +OP4 E01741 0 +OP4 E01742 0 +OP4 E01743 0 +OP4 E01744 0 +OP4 E01745 0 +OP4 E01746 0 +OP4 E01747 0 +OP4 E01748 0 +OP4 E01749 0 +OP4 E0174A 0 +OP4 E0174B 0 +OP4 E0174C 0 +OP4 E0174D 0 +OP4 E0174E 0 +OP4 E0174F 0 +OP4 E01750 0 +OP4 E01751 0 +OP4 E01752 0 +OP4 E01753 0 +OP4 E01754 0 +OP4 E01755 0 +OP4 E01756 0 +OP4 E01757 0 +OP4 E01758 0 +OP4 E01759 0 +OP4 E0175A 0 +OP4 E0175B 0 +OP4 E0175C 0 +OP4 E0175D 0 +OP4 E0175E 0 +OP4 E0175F 0 +OP4 E01760 0 +OP4 E01761 0 +OP4 E01762 0 +OP4 E01763 0 +OP4 E01764 0 +OP4 E01765 0 +OP4 E01766 0 +OP4 E01767 0 +OP4 E01768 0 +OP4 E01769 0 +OP4 E0176A 0 +OP4 E0176B 0 +OP4 E0176C 0 +OP4 E0176D 0 +OP4 E0176E 0 +OP4 E0176F 0 +OP4 E01770 0 +OP4 E01771 0 +OP4 E01772 0 +OP4 E01773 0 +OP4 E01774 0 +OP4 E01775 0 +OP4 E01776 0 +OP4 E01777 0 +OP4 E01778 0 +OP4 E01779 0 +OP4 E0177A 0 +OP4 E0177B 0 +OP4 E0177C 0 +OP4 E0177D 0 +OP4 E0177E 0 +OP4 E0177F 0 +OP4 E01780 0 +OP4 E01781 0 +OP4 E01782 0 +OP4 E01783 0 +OP4 E01784 0 +OP4 E01785 0 +OP4 E01786 0 +OP4 E01787 0 +OP4 E01788 0 +OP4 E01789 0 +OP4 E0178A 0 +OP4 E0178B 0 +OP4 E0178C 0 +OP4 E0178D 0 +OP4 E0178E 0 +OP4 E0178F 0 +OP4 E01790 0 +OP4 E01791 0 +OP4 E01792 0 +OP4 E01793 0 +OP4 E01794 0 +OP4 E01795 0 +OP4 E01796 0 +OP4 E01797 0 +OP4 E01798 0 +OP4 E01799 0 +OP4 E0179A 0 +OP4 E0179B 0 +OP4 E0179C 0 +OP4 E0179D 0 +OP4 E0179E 0 +OP4 E0179F 0 +OP4 E017A0 0 +OP4 E017A1 0 +OP4 E017A2 0 +OP4 E017A3 0 +OP4 E017A4 0 +OP4 E017A5 0 +OP4 E017A6 0 +OP4 E017A7 0 +OP4 E017A8 0 +OP4 E017A9 0 +OP4 E017AA 0 +OP4 E017AB 0 +OP4 E017AC 0 +OP4 E017AD 0 +OP4 E017AE 0 +OP4 E017AF 0 +OP4 E017B0 0 +OP4 E017B1 0 +OP4 E017B2 0 +OP4 E017B3 0 +OP4 E017B4 0 +OP4 E017B5 0 +OP4 E017B6 0 +OP4 E017B7 0 +OP4 E017B8 0 +OP4 E017B9 0 +OP4 E017BA 0 +OP4 E017BB 0 +OP4 E017BC 0 +OP4 E017BD 0 +OP4 E017BE 0 +OP4 E017BF 0 +OP4 E017C0 0 +OP4 E017C1 0 +OP4 E017C2 0 +OP4 E017C3 0 +OP4 E017C4 0 +OP4 E017C5 0 +OP4 E017C6 0 +OP4 E017C7 0 +OP4 E017C8 0 +OP4 E017C9 0 +OP4 E017CA 0 +OP4 E017CB 0 +OP4 E017CC 0 +OP4 E017CD 0 +OP4 E017CE 0 +OP4 E017CF 0 +OP4 E017D0 0 +OP4 E017D1 0 +OP4 E017D2 0 +OP4 E017D3 0 +OP4 E017D4 0 +OP4 E017D5 0 +OP4 E017D6 0 +OP4 E017D7 0 +OP4 E017D8 0 +OP4 E017D9 0 +OP4 E017DA 0 +OP4 E017DB 0 +OP4 E017DC 0 +OP4 E017DD 0 +OP4 E017DE 0 +OP4 E017DF 0 +OP4 E017E0 0 +OP4 E017E1 0 +OP4 E017E2 0 +OP4 E017E3 0 +OP4 E017E4 0 +OP4 E017E5 0 +OP4 E017E6 0 +OP4 E017E7 0 +OP4 E017E8 0 +OP4 E017E9 0 +OP4 E017EA 0 +OP4 E017EB 0 +OP4 E017EC 0 +OP4 E017ED 0 +OP4 E017EE 0 +OP4 E017EF 0 +OP4 E017F0 0 +OP4 E017F1 0 +OP4 E017F2 0 +OP4 E017F3 0 +OP4 E017F4 0 +OP4 E017F5 0 +OP4 E017F6 0 +OP4 E017F7 0 +OP4 E017F8 0 +OP4 E017F9 0 +OP4 E017FA 0 +OP4 E017FB 0 +OP4 E017FC 0 +OP4 E017FD 0 +OP4 E017FE 0 +OP4 E017FF 0 +OP4 E01800 0 +OP4 E01801 0 +OP4 E01802 0 +OP4 E01803 0 +OP4 E01804 0 +OP4 E01805 0 +OP4 E01806 0 +OP4 E01807 0 +OP4 E01808 0 +OP4 E01809 0 +OP4 E0180A 0 +OP4 E0180B 0 +OP4 E0180C 0 +OP4 E0180D 0 +OP4 E0180E 0 +OP4 E0180F 0 +OP4 E01810 0 +OP4 E01811 0 +OP4 E01812 0 +OP4 E01813 0 +OP4 E01814 0 +OP4 E01815 0 +OP4 E01816 0 +OP4 E01817 0 +OP4 E01818 0 +OP4 E01819 0 +OP4 E0181A 0 +OP4 E0181B 0 +OP4 E0181C 0 +OP4 E0181D 0 +OP4 E0181E 0 +OP4 E0181F 0 +OP4 E01820 0 +OP4 E01821 0 +OP4 E01822 0 +OP4 E01823 0 +OP4 E01824 0 +OP4 E01825 0 +OP4 E01826 0 +OP4 E01827 0 +OP4 E01828 0 +OP4 E01829 0 +OP4 E0182A 0 +OP4 E0182B 0 +OP4 E0182C 0 +OP4 E0182D 0 +OP4 E0182E 0 +OP4 E0182F 0 +OP4 E01830 0 +OP4 E01831 0 +OP4 E01832 0 +OP4 E01833 0 +OP4 E01834 0 +OP4 E01835 0 +OP4 E01836 0 +OP4 E01837 0 +OP4 E01838 0 +OP4 E01839 0 +OP4 E0183A 0 +OP4 E0183B 0 +OP4 E0183C 0 +OP4 E0183D 0 +OP4 E0183E 0 +OP4 E0183F 0 +OP4 E01840 0 +OP4 E01841 0 +OP4 E01842 0 +OP4 E01843 0 +OP4 E01844 0 +OP4 E01845 0 +OP4 E01846 0 +OP4 E01847 0 +OP4 E01848 0 +OP4 E01849 0 +OP4 E0184A 0 +OP4 E0184B 0 +OP4 E0184C 0 +OP4 E0184D 0 +OP4 E0184E 0 +OP4 E0184F 0 +OP4 E01850 0 +OP4 E01851 0 +OP4 E01852 0 +OP4 E01853 0 +OP4 E01854 0 +OP4 E01855 0 +OP4 E01856 0 +OP4 E01857 0 +OP4 E01858 0 +OP4 E01859 0 +OP4 E0185A 0 +OP4 E0185B 0 +OP4 E0185C 0 +OP4 E0185D 0 +OP4 E0185E 0 +OP4 E0185F 0 +OP4 E01860 0 +OP4 E01861 0 +OP4 E01862 0 +OP4 E01863 0 +OP4 E01864 0 +OP4 E01865 0 +OP4 E01866 0 +OP4 E01867 0 +OP4 E01868 0 +OP4 E01869 0 +OP4 E0186A 0 +OP4 E0186B 0 +OP4 E0186C 0 +OP4 E0186D 0 +OP4 E0186E 0 +OP4 E0186F 0 +OP4 E01870 0 +OP4 E01871 0 +OP4 E01872 0 +OP4 E01873 0 +OP4 E01874 0 +OP4 E01875 0 +OP4 E01876 0 +OP4 E01877 0 +OP4 E01878 0 +OP4 E01879 0 +OP4 E0187A 0 +OP4 E0187B 0 +OP4 E0187C 0 +OP4 E0187D 0 +OP4 E0187E 0 +OP4 E0187F 0 +OP4 E01880 0 +OP4 E01881 0 +OP4 E01882 0 +OP4 E01883 0 +OP4 E01884 0 +OP4 E01885 0 +OP4 E01886 0 +OP4 E01887 0 +OP4 E01888 0 +OP4 E01889 0 +OP4 E0188A 0 +OP4 E0188B 0 +OP4 E0188C 0 +OP4 E0188D 0 +OP4 E0188E 0 +OP4 E0188F 0 +OP4 E01890 0 +OP4 E01891 0 +OP4 E01892 0 +OP4 E01893 0 +OP4 E01894 0 +OP4 E01895 0 +OP4 E01896 0 +OP4 E01897 0 +OP4 E01898 0 +OP4 E01899 0 +OP4 E0189A 0 +OP4 E0189B 0 +OP4 E0189C 0 +OP4 E0189D 0 +OP4 E0189E 0 +OP4 E0189F 0 +OP4 E018A0 0 +OP4 E018A1 0 +OP4 E018A2 0 +OP4 E018A3 0 +OP4 E018A4 0 +OP4 E018A5 0 +OP4 E018A6 0 +OP4 E018A7 0 +OP4 E018A8 0 +OP4 E018A9 0 +OP4 E018AA 0 +OP4 E018AB 0 +OP4 E018AC 0 +OP4 E018AD 0 +OP4 E018AE 0 +OP4 E018AF 0 +OP4 E018B0 0 +OP4 E018B1 0 +OP4 E018B2 0 +OP4 E018B3 0 +OP4 E018B4 0 +OP4 E018B5 0 +OP4 E018B6 0 +OP4 E018B7 0 +OP4 E018B8 0 +OP4 E018B9 0 +OP4 E018BA 0 +OP4 E018BB 0 +OP4 E018BC 0 +OP4 E018BD 0 +OP4 E018BE 0 +OP4 E018BF 0 +OP4 E018C0 0 +OP4 E018C1 0 +OP4 E018C2 0 +OP4 E018C3 0 +OP4 E018C4 0 +OP4 E018C5 0 +OP4 E018C6 0 +OP4 E018C7 0 +OP4 E018C8 0 +OP4 E018C9 0 +OP4 E018CA 0 +OP4 E018CB 0 +OP4 E018CC 0 +OP4 E018CD 0 +OP4 E018CE 0 +OP4 E018CF 0 +OP4 E018D0 0 +OP4 E018D1 0 +OP4 E018D2 0 +OP4 E018D3 0 +OP4 E018D4 0 +OP4 E018D5 0 +OP4 E018D6 0 +OP4 E018D7 0 +OP4 E018D8 0 +OP4 E018D9 0 +OP4 E018DA 0 +OP4 E018DB 0 +OP4 E018DC 0 +OP4 E018DD 0 +OP4 E018DE 0 +OP4 E018DF 0 +OP4 E018E0 0 +OP4 E018E1 0 +OP4 E018E2 0 +OP4 E018E3 0 +OP4 E018E4 0 +OP4 E018E5 0 +OP4 E018E6 0 +OP4 E018E7 0 +OP4 E018E8 0 +OP4 E018E9 0 +OP4 E018EA 0 +OP4 E018EB 0 +OP4 E018EC 0 +OP4 E018ED 0 +OP4 E018EE 0 +OP4 E018EF 0 +OP4 E018F0 0 +OP4 E018F1 0 +OP4 E018F2 0 +OP4 E018F3 0 +OP4 E018F4 0 +OP4 E018F5 0 +OP4 E018F6 0 +OP4 E018F7 0 +OP4 E018F8 0 +OP4 E018F9 0 +OP4 E018FA 0 +OP4 E018FB 0 +OP4 E018FC 0 +OP4 E018FD 0 +OP4 E018FE 0 +OP4 E018FF 0 +OP4 E01900 0 +OP4 E01901 0 +OP4 E01902 0 +OP4 E01903 0 +OP4 E01904 0 +OP4 E01905 0 +OP4 E01906 0 +OP4 E01907 0 +OP4 E01908 0 +OP4 E01909 0 +OP4 E0190A 0 +OP4 E0190B 0 +OP4 E0190C 0 +OP4 E0190D 0 +OP4 E0190E 0 +OP4 E0190F 0 +OP4 E01910 0 +OP4 E01911 0 +OP4 E01912 0 +OP4 E01913 0 +OP4 E01914 0 +OP4 E01915 0 +OP4 E01916 0 +OP4 E01917 0 +OP4 E01918 0 +OP4 E01919 0 +OP4 E0191A 0 +OP4 E0191B 0 +OP4 E0191C 0 +OP4 E0191D 0 +OP4 E0191E 0 +OP4 E0191F 0 +OP4 E01920 0 +OP4 E01921 0 +OP4 E01922 0 +OP4 E01923 0 +OP4 E01924 0 +OP4 E01925 0 +OP4 E01926 0 +OP4 E01927 0 +OP4 E01928 0 +OP4 E01929 0 +OP4 E0192A 0 +OP4 E0192B 0 +OP4 E0192C 0 +OP4 E0192D 0 +OP4 E0192E 0 +OP4 E0192F 0 +OP4 E01930 0 +OP4 E01931 0 +OP4 E01932 0 +OP4 E01933 0 +OP4 E01934 0 +OP4 E01935 0 +OP4 E01936 0 +OP4 E01937 0 +OP4 E01938 0 +OP4 E01939 0 +OP4 E0193A 0 +OP4 E0193B 0 +OP4 E0193C 0 +OP4 E0193D 0 +OP4 E0193E 0 +OP4 E0193F 0 +OP4 E01940 0 +OP4 E01941 0 +OP4 E01942 0 +OP4 E01943 0 +OP4 E01944 0 +OP4 E01945 0 +OP4 E01946 0 +OP4 E01947 0 +OP4 E01948 0 +OP4 E01949 0 +OP4 E0194A 0 +OP4 E0194B 0 +OP4 E0194C 0 +OP4 E0194D 0 +OP4 E0194E 0 +OP4 E0194F 0 +OP4 E01950 0 +OP4 E01951 0 +OP4 E01952 0 +OP4 E01953 0 +OP4 E01954 0 +OP4 E01955 0 +OP4 E01956 0 +OP4 E01957 0 +OP4 E01958 0 +OP4 E01959 0 +OP4 E0195A 0 +OP4 E0195B 0 +OP4 E0195C 0 +OP4 E0195D 0 +OP4 E0195E 0 +OP4 E0195F 0 +OP4 E01960 0 +OP4 E01961 0 +OP4 E01962 0 +OP4 E01963 0 +OP4 E01964 0 +OP4 E01965 0 +OP4 E01966 0 +OP4 E01967 0 +OP4 E01968 0 +OP4 E01969 0 +OP4 E0196A 0 +OP4 E0196B 0 +OP4 E0196C 0 +OP4 E0196D 0 +OP4 E0196E 0 +OP4 E0196F 0 +OP4 E01970 0 +OP4 E01971 0 +OP4 E01972 0 +OP4 E01973 0 +OP4 E01974 0 +OP4 E01975 0 +OP4 E01976 0 +OP4 E01977 0 +OP4 E01978 0 +OP4 E01979 0 +OP4 E0197A 0 +OP4 E0197B 0 +OP4 E0197C 0 +OP4 E0197D 0 +OP4 E0197E 0 +OP4 E0197F 0 +OP4 E01980 0 +OP4 E01981 0 +OP4 E01982 0 +OP4 E01983 0 +OP4 E01984 0 +OP4 E01985 0 +OP4 E01986 0 +OP4 E01987 0 +OP4 E01988 0 +OP4 E01989 0 +OP4 E0198A 0 +OP4 E0198B 0 +OP4 E0198C 0 +OP4 E0198D 0 +OP4 E0198E 0 +OP4 E0198F 0 +OP4 E01990 0 +OP4 E01991 0 +OP4 E01992 0 +OP4 E01993 0 +OP4 E01994 0 +OP4 E01995 0 +OP4 E01996 0 +OP4 E01997 0 +OP4 E01998 0 +OP4 E01999 0 +OP4 E0199A 0 +OP4 E0199B 0 +OP4 E0199C 0 +OP4 E0199D 0 +OP4 E0199E 0 +OP4 E0199F 0 +OP4 E019A0 0 +OP4 E019A1 0 +OP4 E019A2 0 +OP4 E019A3 0 +OP4 E019A4 0 +OP4 E019A5 0 +OP4 E019A6 0 +OP4 E019A7 0 +OP4 E019A8 0 +OP4 E019A9 0 +OP4 E019AA 0 +OP4 E019AB 0 +OP4 E019AC 0 +OP4 E019AD 0 +OP4 E019AE 0 +OP4 E019AF 0 +OP4 E019B0 0 +OP4 E019B1 0 +OP4 E019B2 0 +OP4 E019B3 0 +OP4 E019B4 0 +OP4 E019B5 0 +OP4 E019B6 0 +OP4 E019B7 0 +OP4 E019B8 0 +OP4 E019B9 0 +OP4 E019BA 0 +OP4 E019BB 0 +OP4 E019BC 0 +OP4 E019BD 0 +OP4 E019BE 0 +OP4 E019BF 0 +OP4 E019C0 0 +OP4 E019C1 0 +OP4 E019C2 0 +OP4 E019C3 0 +OP4 E019C4 0 +OP4 E019C5 0 +OP4 E019C6 0 +OP4 E019C7 0 +OP4 E019C8 0 +OP4 E019C9 0 +OP4 E019CA 0 +OP4 E019CB 0 +OP4 E019CC 0 +OP4 E019CD 0 +OP4 E019CE 0 +OP4 E019CF 0 +OP4 E019D0 0 +OP4 E019D1 0 +OP4 E019D2 0 +OP4 E019D3 0 +OP4 E019D4 0 +OP4 E019D5 0 +OP4 E019D6 0 +OP4 E019D7 0 +OP4 E019D8 0 +OP4 E019D9 0 +OP4 E019DA 0 +OP4 E019DB 0 +OP4 E019DC 0 +OP4 E019DD 0 +OP4 E019DE 0 +OP4 E019DF 0 +OP4 E019E0 0 +OP4 E019E1 0 +OP4 E019E2 0 +OP4 E019E3 0 +OP4 E019E4 0 +OP4 E019E5 0 +OP4 E019E6 0 +OP4 E019E7 0 +OP4 E019E8 0 +OP4 E019E9 0 +OP4 E019EA 0 +OP4 E019EB 0 +OP4 E019EC 0 +OP4 E019ED 0 +OP4 E019EE 0 +OP4 E019EF 0 +OP4 E019F0 0 +OP4 E019F1 0 +OP4 E019F2 0 +OP4 E019F3 0 +OP4 E019F4 0 +OP4 E019F5 0 +OP4 E019F6 0 +OP4 E019F7 0 +OP4 E019F8 0 +OP4 E019F9 0 +OP4 E019FA 0 +OP4 E019FB 0 +OP4 E019FC 0 +OP4 E019FD 0 +OP4 E019FE 0 +OP4 E019FF 0 +OP4 E01A00 0 +OP4 E01A01 0 +OP4 E01A02 0 +OP4 E01A03 0 +OP4 E01A04 0 +OP4 E01A05 0 +OP4 E01A06 0 +OP4 E01A07 0 +OP4 E01A08 0 +OP4 E01A09 0 +OP4 E01A0A 0 +OP4 E01A0B 0 +OP4 E01A0C 0 +OP4 E01A0D 0 +OP4 E01A0E 0 +OP4 E01A0F 0 +OP4 E01A10 0 +OP4 E01A11 0 +OP4 E01A12 0 +OP4 E01A13 0 +OP4 E01A14 0 +OP4 E01A15 0 +OP4 E01A16 0 +OP4 E01A17 0 +OP4 E01A18 0 +OP4 E01A19 0 +OP4 E01A1A 0 +OP4 E01A1B 0 +OP4 E01A1C 0 +OP4 E01A1D 0 +OP4 E01A1E 0 +OP4 E01A1F 0 +OP4 E01A20 0 +OP4 E01A21 0 +OP4 E01A22 0 +OP4 E01A23 0 +OP4 E01A24 0 +OP4 E01A25 0 +OP4 E01A26 0 +OP4 E01A27 0 +OP4 E01A28 0 +OP4 E01A29 0 +OP4 E01A2A 0 +OP4 E01A2B 0 +OP4 E01A2C 0 +OP4 E01A2D 0 +OP4 E01A2E 0 +OP4 E01A2F 0 +OP4 E01A30 0 +OP4 E01A31 0 +OP4 E01A32 0 +OP4 E01A33 0 +OP4 E01A34 0 +OP4 E01A35 0 +OP4 E01A36 0 +OP4 E01A37 0 +OP4 E01A38 0 +OP4 E01A39 0 +OP4 E01A3A 0 +OP4 E01A3B 0 +OP4 E01A3C 0 +OP4 E01A3D 0 +OP4 E01A3E 0 +OP4 E01A3F 0 +OP4 E01A40 0 +OP4 E01A41 0 +OP4 E01A42 0 +OP4 E01A43 0 +OP4 E01A44 0 +OP4 E01A45 0 +OP4 E01A46 0 +OP4 E01A47 0 +OP4 E01A48 0 +OP4 E01A49 0 +OP4 E01A4A 0 +OP4 E01A4B 0 +OP4 E01A4C 0 +OP4 E01A4D 0 +OP4 E01A4E 0 +OP4 E01A4F 0 +OP4 E01A50 0 +OP4 E01A51 0 +OP4 E01A52 0 +OP4 E01A53 0 +OP4 E01A54 0 +OP4 E01A55 0 +OP4 E01A56 0 +OP4 E01A57 0 +OP4 E01A58 0 +OP4 E01A59 0 +OP4 E01A5A 0 +OP4 E01A5B 0 +OP4 E01A5C 0 +OP4 E01A5D 0 +OP4 E01A5E 0 +OP4 E01A5F 0 +OP4 E01A60 0 +OP4 E01A61 0 +OP4 E01A62 0 +OP4 E01A63 0 +OP4 E01A64 0 +OP4 E01A65 0 +OP4 E01A66 0 +OP4 E01A67 0 +OP4 E01A68 0 +OP4 E01A69 0 +OP4 E01A6A 0 +OP4 E01A6B 0 +OP4 E01A6C 0 +OP4 E01A6D 0 +OP4 E01A6E 0 +OP4 E01A6F 0 +OP4 E01A70 0 +OP4 E01A71 0 +OP4 E01A72 0 +OP4 E01A73 0 +OP4 E01A74 0 +OP4 E01A75 0 +OP4 E01A76 0 +OP4 E01A77 0 +OP4 E01A78 0 +OP4 E01A79 0 +OP4 E01A7A 0 +OP4 E01A7B 0 +OP4 E01A7C 0 +OP4 E01A7D 0 +OP4 E01A7E 0 +OP4 E01A7F 0 +OP4 E01A80 0 +OP4 E01A81 0 +OP4 E01A82 0 +OP4 E01A83 0 +OP4 E01A84 0 +OP4 E01A85 0 +OP4 E01A86 0 +OP4 E01A87 0 +OP4 E01A88 0 +OP4 E01A89 0 +OP4 E01A8A 0 +OP4 E01A8B 0 +OP4 E01A8C 0 +OP4 E01A8D 0 +OP4 E01A8E 0 +OP4 E01A8F 0 +OP4 E01A90 0 +OP4 E01A91 0 +OP4 E01A92 0 +OP4 E01A93 0 +OP4 E01A94 0 +OP4 E01A95 0 +OP4 E01A96 0 +OP4 E01A97 0 +OP4 E01A98 0 +OP4 E01A99 0 +OP4 E01A9A 0 +OP4 E01A9B 0 +OP4 E01A9C 0 +OP4 E01A9D 0 +OP4 E01A9E 0 +OP4 E01A9F 0 +OP4 E01AA0 0 +OP4 E01AA1 0 +OP4 E01AA2 0 +OP4 E01AA3 0 +OP4 E01AA4 0 +OP4 E01AA5 0 +OP4 E01AA6 0 +OP4 E01AA7 0 +OP4 E01AA8 0 +OP4 E01AA9 0 +OP4 E01AAA 0 +OP4 E01AAB 0 +OP4 E01AAC 0 +OP4 E01AAD 0 +OP4 E01AAE 0 +OP4 E01AAF 0 +OP4 E01AB0 0 +OP4 E01AB1 0 +OP4 E01AB2 0 +OP4 E01AB3 0 +OP4 E01AB4 0 +OP4 E01AB5 0 +OP4 E01AB6 0 +OP4 E01AB7 0 +OP4 E01AB8 0 +OP4 E01AB9 0 +OP4 E01ABA 0 +OP4 E01ABB 0 +OP4 E01ABC 0 +OP4 E01ABD 0 +OP4 E01ABE 0 +OP4 E01ABF 0 +OP4 E01AC0 0 +OP4 E01AC1 0 +OP4 E01AC2 0 +OP4 E01AC3 0 +OP4 E01AC4 0 +OP4 E01AC5 0 +OP4 E01AC6 0 +OP4 E01AC7 0 +OP4 E01AC8 0 +OP4 E01AC9 0 +OP4 E01ACA 0 +OP4 E01ACB 0 +OP4 E01ACC 0 +OP4 E01ACD 0 +OP4 E01ACE 0 +OP4 E01ACF 0 +OP4 E01AD0 0 +OP4 E01AD1 0 +OP4 E01AD2 0 +OP4 E01AD3 0 +OP4 E01AD4 0 +OP4 E01AD5 0 +OP4 E01AD6 0 +OP4 E01AD7 0 +OP4 E01AD8 0 +OP4 E01AD9 0 +OP4 E01ADA 0 +OP4 E01ADB 0 +OP4 E01ADC 0 +OP4 E01ADD 0 +OP4 E01ADE 0 +OP4 E01ADF 0 +OP4 E01AE0 0 +OP4 E01AE1 0 +OP4 E01AE2 0 +OP4 E01AE3 0 +OP4 E01AE4 0 +OP4 E01AE5 0 +OP4 E01AE6 0 +OP4 E01AE7 0 +OP4 E01AE8 0 +OP4 E01AE9 0 +OP4 E01AEA 0 +OP4 E01AEB 0 +OP4 E01AEC 0 +OP4 E01AED 0 +OP4 E01AEE 0 +OP4 E01AEF 0 +OP4 E01AF0 0 +OP4 E01AF1 0 +OP4 E01AF2 0 +OP4 E01AF3 0 +OP4 E01AF4 0 +OP4 E01AF5 0 +OP4 E01AF6 0 +OP4 E01AF7 0 +OP4 E01AF8 0 +OP4 E01AF9 0 +OP4 E01AFA 0 +OP4 E01AFB 0 +OP4 E01AFC 0 +OP4 E01AFD 0 +OP4 E01AFE 0 +OP4 E01AFF 0 +OP4 E01B00 0 +OP4 E01B01 0 +OP4 E01B02 0 +OP4 E01B03 0 +OP4 E01B04 0 +OP4 E01B05 0 +OP4 E01B06 0 +OP4 E01B07 0 +OP4 E01B08 0 +OP4 E01B09 0 +OP4 E01B0A 0 +OP4 E01B0B 0 +OP4 E01B0C 0 +OP4 E01B0D 0 +OP4 E01B0E 0 +OP4 E01B0F 0 +OP4 E01B10 0 +OP4 E01B11 0 +OP4 E01B12 0 +OP4 E01B13 0 +OP4 E01B14 0 +OP4 E01B15 0 +OP4 E01B16 0 +OP4 E01B17 0 +OP4 E01B18 0 +OP4 E01B19 0 +OP4 E01B1A 0 +OP4 E01B1B 0 +OP4 E01B1C 0 +OP4 E01B1D 0 +OP4 E01B1E 0 +OP4 E01B1F 0 +OP4 E01B20 0 +OP4 E01B21 0 +OP4 E01B22 0 +OP4 E01B23 0 +OP4 E01B24 0 +OP4 E01B25 0 +OP4 E01B26 0 +OP4 E01B27 0 +OP4 E01B28 0 +OP4 E01B29 0 +OP4 E01B2A 0 +OP4 E01B2B 0 +OP4 E01B2C 0 +OP4 E01B2D 0 +OP4 E01B2E 0 +OP4 E01B2F 0 +OP4 E01B30 0 +OP4 E01B31 0 +OP4 E01B32 0 +OP4 E01B33 0 +OP4 E01B34 0 +OP4 E01B35 0 +OP4 E01B36 0 +OP4 E01B37 0 +OP4 E01B38 0 +OP4 E01B39 0 +OP4 E01B3A 0 +OP4 E01B3B 0 +OP4 E01B3C 0 +OP4 E01B3D 0 +OP4 E01B3E 0 +OP4 E01B3F 0 +OP4 E01B40 0 +OP4 E01B41 0 +OP4 E01B42 0 +OP4 E01B43 0 +OP4 E01B44 0 +OP4 E01B45 0 +OP4 E01B46 0 +OP4 E01B47 0 +OP4 E01B48 0 +OP4 E01B49 0 +OP4 E01B4A 0 +OP4 E01B4B 0 +OP4 E01B4C 0 +OP4 E01B4D 0 +OP4 E01B4E 0 +OP4 E01B4F 0 +OP4 E01B50 0 +OP4 E01B51 0 +OP4 E01B52 0 +OP4 E01B53 0 +OP4 E01B54 0 +OP4 E01B55 0 +OP4 E01B56 0 +OP4 E01B57 0 +OP4 E01B58 0 +OP4 E01B59 0 +OP4 E01B5A 0 +OP4 E01B5B 0 +OP4 E01B5C 0 +OP4 E01B5D 0 +OP4 E01B5E 0 +OP4 E01B5F 0 +OP4 E01B60 0 +OP4 E01B61 0 +OP4 E01B62 0 +OP4 E01B63 0 +OP4 E01B64 0 +OP4 E01B65 0 +OP4 E01B66 0 +OP4 E01B67 0 +OP4 E01B68 0 +OP4 E01B69 0 +OP4 E01B6A 0 +OP4 E01B6B 0 +OP4 E01B6C 0 +OP4 E01B6D 0 +OP4 E01B6E 0 +OP4 E01B6F 0 +OP4 E01B70 0 +OP4 E01B71 0 +OP4 E01B72 0 +OP4 E01B73 0 +OP4 E01B74 0 +OP4 E01B75 0 +OP4 E01B76 0 +OP4 E01B77 0 +OP4 E01B78 0 +OP4 E01B79 0 +OP4 E01B7A 0 +OP4 E01B7B 0 +OP4 E01B7C 0 +OP4 E01B7D 0 +OP4 E01B7E 0 +OP4 E01B7F 0 +OP4 E01B80 0 +OP4 E01B81 0 +OP4 E01B82 0 +OP4 E01B83 0 +OP4 E01B84 0 +OP4 E01B85 0 +OP4 E01B86 0 +OP4 E01B87 0 +OP4 E01B88 0 +OP4 E01B89 0 +OP4 E01B8A 0 +OP4 E01B8B 0 +OP4 E01B8C 0 +OP4 E01B8D 0 +OP4 E01B8E 0 +OP4 E01B8F 0 +OP4 E01B90 0 +OP4 E01B91 0 +OP4 E01B92 0 +OP4 E01B93 0 +OP4 E01B94 0 +OP4 E01B95 0 +OP4 E01B96 0 +OP4 E01B97 0 +OP4 E01B98 0 +OP4 E01B99 0 +OP4 E01B9A 0 +OP4 E01B9B 0 +OP4 E01B9C 0 +OP4 E01B9D 0 +OP4 E01B9E 0 +OP4 E01B9F 0 +OP4 E01BA0 0 +OP4 E01BA1 0 +OP4 E01BA2 0 +OP4 E01BA3 0 +OP4 E01BA4 0 +OP4 E01BA5 0 +OP4 E01BA6 0 +OP4 E01BA7 0 +OP4 E01BA8 0 +OP4 E01BA9 0 +OP4 E01BAA 0 +OP4 E01BAB 0 +OP4 E01BAC 0 +OP4 E01BAD 0 +OP4 E01BAE 0 +OP4 E01BAF 0 +OP4 E01BB0 0 +OP4 E01BB1 0 +OP4 E01BB2 0 +OP4 E01BB3 0 +OP4 E01BB4 0 +OP4 E01BB5 0 +OP4 E01BB6 0 +OP4 E01BB7 0 +OP4 E01BB8 0 +OP4 E01BB9 0 +OP4 E01BBA 0 +OP4 E01BBB 0 +OP4 E01BBC 0 +OP4 E01BBD 0 +OP4 E01BBE 0 +OP4 E01BBF 0 +OP4 E01BC0 0 +OP4 E01BC1 0 +OP4 E01BC2 0 +OP4 E01BC3 0 +OP4 E01BC4 0 +OP4 E01BC5 0 +OP4 E01BC6 0 +OP4 E01BC7 0 +OP4 E01BC8 0 +OP4 E01BC9 0 +OP4 E01BCA 0 +OP4 E01BCB 0 +OP4 E01BCC 0 +OP4 E01BCD 0 +OP4 E01BCE 0 +OP4 E01BCF 0 +OP4 E01BD0 0 +OP4 E01BD1 0 +OP4 E01BD2 0 +OP4 E01BD3 0 +OP4 E01BD4 0 +OP4 E01BD5 0 +OP4 E01BD6 0 +OP4 E01BD7 0 +OP4 E01BD8 0 +OP4 E01BD9 0 +OP4 E01BDA 0 +OP4 E01BDB 0 +OP4 E01BDC 0 +OP4 E01BDD 0 +OP4 E01BDE 0 +OP4 E01BDF 0 +OP4 E01BE0 0 +OP4 E01BE1 0 +OP4 E01BE2 0 +OP4 E01BE3 0 +OP4 E01BE4 0 +OP4 E01BE5 0 +OP4 E01BE6 0 +OP4 E01BE7 0 +OP4 E01BE8 0 +OP4 E01BE9 0 +OP4 E01BEA 0 +OP4 E01BEB 0 +OP4 E01BEC 0 +OP4 E01BED 0 +OP4 E01BEE 0 +OP4 E01BEF 0 +OP4 E01BF0 0 +OP4 E01BF1 0 +OP4 E01BF2 0 +OP4 E01BF3 0 +OP4 E01BF4 0 +OP4 E01BF5 0 +OP4 E01BF6 0 +OP4 E01BF7 0 +OP4 E01BF8 0 +OP4 E01BF9 0 +OP4 E01BFA 0 +OP4 E01BFB 0 +OP4 E01BFC 0 +OP4 E01BFD 0 +OP4 E01BFE 0 +OP4 E01BFF 0 +OP4 E01C00 0 +OP4 E01C01 0 +OP4 E01C02 0 +OP4 E01C03 0 +OP4 E01C04 0 +OP4 E01C05 0 +OP4 E01C06 0 +OP4 E01C07 0 +OP4 E01C08 0 +OP4 E01C09 0 +OP4 E01C0A 0 +OP4 E01C0B 0 +OP4 E01C0C 0 +OP4 E01C0D 0 +OP4 E01C0E 0 +OP4 E01C0F 0 +OP4 E01C10 0 +OP4 E01C11 0 +OP4 E01C12 0 +OP4 E01C13 0 +OP4 E01C14 0 +OP4 E01C15 0 +OP4 E01C16 0 +OP4 E01C17 0 +OP4 E01C18 0 +OP4 E01C19 0 +OP4 E01C1A 0 +OP4 E01C1B 0 +OP4 E01C1C 0 +OP4 E01C1D 0 +OP4 E01C1E 0 +OP4 E01C1F 0 +OP4 E01C20 0 +OP4 E01C21 0 +OP4 E01C22 0 +OP4 E01C23 0 +OP4 E01C24 0 +OP4 E01C25 0 +OP4 E01C26 0 +OP4 E01C27 0 +OP4 E01C28 0 +OP4 E01C29 0 +OP4 E01C2A 0 +OP4 E01C2B 0 +OP4 E01C2C 0 +OP4 E01C2D 0 +OP4 E01C2E 0 +OP4 E01C2F 0 +OP4 E01C30 0 +OP4 E01C31 0 +OP4 E01C32 0 +OP4 E01C33 0 +OP4 E01C34 0 +OP4 E01C35 0 +OP4 E01C36 0 +OP4 E01C37 0 +OP4 E01C38 0 +OP4 E01C39 0 +OP4 E01C3A 0 +OP4 E01C3B 0 +OP4 E01C3C 0 +OP4 E01C3D 0 +OP4 E01C3E 0 +OP4 E01C3F 0 +OP4 E01C40 0 +OP4 E01C41 0 +OP4 E01C42 0 +OP4 E01C43 0 +OP4 E01C44 0 +OP4 E01C45 0 +OP4 E01C46 0 +OP4 E01C47 0 +OP4 E01C48 0 +OP4 E01C49 0 +OP4 E01C4A 0 +OP4 E01C4B 0 +OP4 E01C4C 0 +OP4 E01C4D 0 +OP4 E01C4E 0 +OP4 E01C4F 0 +OP4 E01C50 0 +OP4 E01C51 0 +OP4 E01C52 0 +OP4 E01C53 0 +OP4 E01C54 0 +OP4 E01C55 0 +OP4 E01C56 0 +OP4 E01C57 0 +OP4 E01C58 0 +OP4 E01C59 0 +OP4 E01C5A 0 +OP4 E01C5B 0 +OP4 E01C5C 0 +OP4 E01C5D 0 +OP4 E01C5E 0 +OP4 E01C5F 0 +OP4 E01C60 0 +OP4 E01C61 0 +OP4 E01C62 0 +OP4 E01C63 0 +OP4 E01C64 0 +OP4 E01C65 0 +OP4 E01C66 0 +OP4 E01C67 0 +OP4 E01C68 0 +OP4 E01C69 0 +OP4 E01C6A 0 +OP4 E01C6B 0 +OP4 E01C6C 0 +OP4 E01C6D 0 +OP4 E01C6E 0 +OP4 E01C6F 0 +OP4 E01C70 0 +OP4 E01C71 0 +OP4 E01C72 0 +OP4 E01C73 0 +OP4 E01C74 0 +OP4 E01C75 0 +OP4 E01C76 0 +OP4 E01C77 0 +OP4 E01C78 0 +OP4 E01C79 0 +OP4 E01C7A 0 +OP4 E01C7B 0 +OP4 E01C7C 0 +OP4 E01C7D 0 +OP4 E01C7E 0 +OP4 E01C7F 0 +OP4 E01C80 0 +OP4 E01C81 0 +OP4 E01C82 0 +OP4 E01C83 0 +OP4 E01C84 0 +OP4 E01C85 0 +OP4 E01C86 0 +OP4 E01C87 0 +OP4 E01C88 0 +OP4 E01C89 0 +OP4 E01C8A 0 +OP4 E01C8B 0 +OP4 E01C8C 0 +OP4 E01C8D 0 +OP4 E01C8E 0 +OP4 E01C8F 0 +OP4 E01C90 0 +OP4 E01C91 0 +OP4 E01C92 0 +OP4 E01C93 0 +OP4 E01C94 0 +OP4 E01C95 0 +OP4 E01C96 0 +OP4 E01C97 0 +OP4 E01C98 0 +OP4 E01C99 0 +OP4 E01C9A 0 +OP4 E01C9B 0 +OP4 E01C9C 0 +OP4 E01C9D 0 +OP4 E01C9E 0 +OP4 E01C9F 0 +OP4 E01CA0 0 +OP4 E01CA1 0 +OP4 E01CA2 0 +OP4 E01CA3 0 +OP4 E01CA4 0 +OP4 E01CA5 0 +OP4 E01CA6 0 +OP4 E01CA7 0 +OP4 E01CA8 0 +OP4 E01CA9 0 +OP4 E01CAA 0 +OP4 E01CAB 0 +OP4 E01CAC 0 +OP4 E01CAD 0 +OP4 E01CAE 0 +OP4 E01CAF 0 +OP4 E01CB0 0 +OP4 E01CB1 0 +OP4 E01CB2 0 +OP4 E01CB3 0 +OP4 E01CB4 0 +OP4 E01CB5 0 +OP4 E01CB6 0 +OP4 E01CB7 0 +OP4 E01CB8 0 +OP4 E01CB9 0 +OP4 E01CBA 0 +OP4 E01CBB 0 +OP4 E01CBC 0 +OP4 E01CBD 0 +OP4 E01CBE 0 +OP4 E01CBF 0 +OP4 E01CC0 0 +OP4 E01CC1 0 +OP4 E01CC2 0 +OP4 E01CC3 0 +OP4 E01CC4 0 +OP4 E01CC5 0 +OP4 E01CC6 0 +OP4 E01CC7 0 +OP4 E01CC8 0 +OP4 E01CC9 0 +OP4 E01CCA 0 +OP4 E01CCB 0 +OP4 E01CCC 0 +OP4 E01CCD 0 +OP4 E01CCE 0 +OP4 E01CCF 0 +OP4 E01CD0 0 +OP4 E01CD1 0 +OP4 E01CD2 0 +OP4 E01CD3 0 +OP4 E01CD4 0 +OP4 E01CD5 0 +OP4 E01CD6 0 +OP4 E01CD7 0 +OP4 E01CD8 0 +OP4 E01CD9 0 +OP4 E01CDA 0 +OP4 E01CDB 0 +OP4 E01CDC 0 +OP4 E01CDD 0 +OP4 E01CDE 0 +OP4 E01CDF 0 +OP4 E01CE0 0 +OP4 E01CE1 0 +OP4 E01CE2 0 +OP4 E01CE3 0 +OP4 E01CE4 0 +OP4 E01CE5 0 +OP4 E01CE6 0 +OP4 E01CE7 0 +OP4 E01CE8 0 +OP4 E01CE9 0 +OP4 E01CEA 0 +OP4 E01CEB 0 +OP4 E01CEC 0 +OP4 E01CED 0 +OP4 E01CEE 0 +OP4 E01CEF 0 +OP4 E01CF0 0 +OP4 E01CF1 0 +OP4 E01CF2 0 +OP4 E01CF3 0 +OP4 E01CF4 0 +OP4 E01CF5 0 +OP4 E01CF6 0 +OP4 E01CF7 0 +OP4 E01CF8 0 +OP4 E01CF9 0 +OP4 E01CFA 0 +OP4 E01CFB 0 +OP4 E01CFC 0 +OP4 E01CFD 0 +OP4 E01CFE 0 +OP4 E01CFF 0 +OP4 E01D00 0 +OP4 E01D01 0 +OP4 E01D02 0 +OP4 E01D03 0 +OP4 E01D04 0 +OP4 E01D05 0 +OP4 E01D06 0 +OP4 E01D07 0 +OP4 E01D08 0 +OP4 E01D09 0 +OP4 E01D0A 0 +OP4 E01D0B 0 +OP4 E01D0C 0 +OP4 E01D0D 0 +OP4 E01D0E 0 +OP4 E01D0F 0 +OP4 E01D10 0 +OP4 E01D11 0 +OP4 E01D12 0 +OP4 E01D13 0 +OP4 E01D14 0 +OP4 E01D15 0 +OP4 E01D16 0 +OP4 E01D17 0 +OP4 E01D18 0 +OP4 E01D19 0 +OP4 E01D1A 0 +OP4 E01D1B 0 +OP4 E01D1C 0 +OP4 E01D1D 0 +OP4 E01D1E 0 +OP4 E01D1F 0 +OP4 E01D20 0 +OP4 E01D21 0 +OP4 E01D22 0 +OP4 E01D23 0 +OP4 E01D24 0 +OP4 E01D25 0 +OP4 E01D26 0 +OP4 E01D27 0 +OP4 E01D28 0 +OP4 E01D29 0 +OP4 E01D2A 0 +OP4 E01D2B 0 +OP4 E01D2C 0 +OP4 E01D2D 0 +OP4 E01D2E 0 +OP4 E01D2F 0 +OP4 E01D30 0 +OP4 E01D31 0 +OP4 E01D32 0 +OP4 E01D33 0 +OP4 E01D34 0 +OP4 E01D35 0 +OP4 E01D36 0 +OP4 E01D37 0 +OP4 E01D38 0 +OP4 E01D39 0 +OP4 E01D3A 0 +OP4 E01D3B 0 +OP4 E01D3C 0 +OP4 E01D3D 0 +OP4 E01D3E 0 +OP4 E01D3F 0 +OP4 E01D40 0 +OP4 E01D41 0 +OP4 E01D42 0 +OP4 E01D43 0 +OP4 E01D44 0 +OP4 E01D45 0 +OP4 E01D46 0 +OP4 E01D47 0 +OP4 E01D48 0 +OP4 E01D49 0 +OP4 E01D4A 0 +OP4 E01D4B 0 +OP4 E01D4C 0 +OP4 E01D4D 0 +OP4 E01D4E 0 +OP4 E01D4F 0 +OP4 E01D50 0 +OP4 E01D51 0 +OP4 E01D52 0 +OP4 E01D53 0 +OP4 E01D54 0 +OP4 E01D55 0 +OP4 E01D56 0 +OP4 E01D57 0 +OP4 E01D58 0 +OP4 E01D59 0 +OP4 E01D5A 0 +OP4 E01D5B 0 +OP4 E01D5C 0 +OP4 E01D5D 0 +OP4 E01D5E 0 +OP4 E01D5F 0 +OP4 E01D60 0 +OP4 E01D61 0 +OP4 E01D62 0 +OP4 E01D63 0 +OP4 E01D64 0 +OP4 E01D65 0 +OP4 E01D66 0 +OP4 E01D67 0 +OP4 E01D68 0 +OP4 E01D69 0 +OP4 E01D6A 0 +OP4 E01D6B 0 +OP4 E01D6C 0 +OP4 E01D6D 0 +OP4 E01D6E 0 +OP4 E01D6F 0 +OP4 E01D70 0 +OP4 E01D71 0 +OP4 E01D72 0 +OP4 E01D73 0 +OP4 E01D74 0 +OP4 E01D75 0 +OP4 E01D76 0 +OP4 E01D77 0 +OP4 E01D78 0 +OP4 E01D79 0 +OP4 E01D7A 0 +OP4 E01D7B 0 +OP4 E01D7C 0 +OP4 E01D7D 0 +OP4 E01D7E 0 +OP4 E01D7F 0 +OP4 E01D80 0 +OP4 E01D81 0 +OP4 E01D82 0 +OP4 E01D83 0 +OP4 E01D84 0 +OP4 E01D85 0 +OP4 E01D86 0 +OP4 E01D87 0 +OP4 E01D88 0 +OP4 E01D89 0 +OP4 E01D8A 0 +OP4 E01D8B 0 +OP4 E01D8C 0 +OP4 E01D8D 0 +OP4 E01D8E 0 +OP4 E01D8F 0 +OP4 E01D90 0 +OP4 E01D91 0 +OP4 E01D92 0 +OP4 E01D93 0 +OP4 E01D94 0 +OP4 E01D95 0 +OP4 E01D96 0 +OP4 E01D97 0 +OP4 E01D98 0 +OP4 E01D99 0 +OP4 E01D9A 0 +OP4 E01D9B 0 +OP4 E01D9C 0 +OP4 E01D9D 0 +OP4 E01D9E 0 +OP4 E01D9F 0 +OP4 E01DA0 0 +OP4 E01DA1 0 +OP4 E01DA2 0 +OP4 E01DA3 0 +OP4 E01DA4 0 +OP4 E01DA5 0 +OP4 E01DA6 0 +OP4 E01DA7 0 +OP4 E01DA8 0 +OP4 E01DA9 0 +OP4 E01DAA 0 +OP4 E01DAB 0 +OP4 E01DAC 0 +OP4 E01DAD 0 +OP4 E01DAE 0 +OP4 E01DAF 0 +OP4 E01DB0 0 +OP4 E01DB1 0 +OP4 E01DB2 0 +OP4 E01DB3 0 +OP4 E01DB4 0 +OP4 E01DB5 0 +OP4 E01DB6 0 +OP4 E01DB7 0 +OP4 E01DB8 0 +OP4 E01DB9 0 +OP4 E01DBA 0 +OP4 E01DBB 0 +OP4 E01DBC 0 +OP4 E01DBD 0 +OP4 E01DBE 0 +OP4 E01DBF 0 +OP4 E01DC0 0 +OP4 E01DC1 0 +OP4 E01DC2 0 +OP4 E01DC3 0 +OP4 E01DC4 0 +OP4 E01DC5 0 +OP4 E01DC6 0 +OP4 E01DC7 0 +OP4 E01DC8 0 +OP4 E01DC9 0 +OP4 E01DCA 0 +OP4 E01DCB 0 +OP4 E01DCC 0 +OP4 E01DCD 0 +OP4 E01DCE 0 +OP4 E01DCF 0 +OP4 E01DD0 0 +OP4 E01DD1 0 +OP4 E01DD2 0 +OP4 E01DD3 0 +OP4 E01DD4 0 +OP4 E01DD5 0 +OP4 E01DD6 0 +OP4 E01DD7 0 +OP4 E01DD8 0 +OP4 E01DD9 0 +OP4 E01DDA 0 +OP4 E01DDB 0 +OP4 E01DDC 0 +OP4 E01DDD 0 +OP4 E01DDE 0 +OP4 E01DDF 0 +OP4 E01DE0 0 +OP4 E01DE1 0 +OP4 E01DE2 0 +OP4 E01DE3 0 +OP4 E01DE4 0 +OP4 E01DE5 0 +OP4 E01DE6 0 +OP4 E01DE7 0 +OP4 E01DE8 0 +OP4 E01DE9 0 +OP4 E01DEA 0 +OP4 E01DEB 0 +OP4 E01DEC 0 +OP4 E01DED 0 +OP4 E01DEE 0 +OP4 E01DEF 0 +OP4 E01DF0 0 +OP4 E01DF1 0 +OP4 E01DF2 0 +OP4 E01DF3 0 +OP4 E01DF4 0 +OP4 E01DF5 0 +OP4 E01DF6 0 +OP4 E01DF7 0 +OP4 E01DF8 0 +OP4 E01DF9 0 +OP4 E01DFA 0 +OP4 E01DFB 0 +OP4 E01DFC 0 +OP4 E01DFD 0 +OP4 E01DFE 0 +OP4 E01DFF 0 +OP4 E01E00 0 +OP4 E01E01 0 +OP4 E01E02 0 +OP4 E01E03 0 +OP4 E01E04 0 +OP4 E01E05 0 +OP4 E01E06 0 +OP4 E01E07 0 +OP4 E01E08 0 +OP4 E01E09 0 +OP4 E01E0A 0 +OP4 E01E0B 0 +OP4 E01E0C 0 +OP4 E01E0D 0 +OP4 E01E0E 0 +OP4 E01E0F 0 +OP4 E01E10 0 +OP4 E01E11 0 +OP4 E01E12 0 +OP4 E01E13 0 +OP4 E01E14 0 +OP4 E01E15 0 +OP4 E01E16 0 +OP4 E01E17 0 +OP4 E01E18 0 +OP4 E01E19 0 +OP4 E01E1A 0 +OP4 E01E1B 0 +OP4 E01E1C 0 +OP4 E01E1D 0 +OP4 E01E1E 0 +OP4 E01E1F 0 +OP4 E01E20 0 +OP4 E01E21 0 +OP4 E01E22 0 +OP4 E01E23 0 +OP4 E01E24 0 +OP4 E01E25 0 +OP4 E01E26 0 +OP4 E01E27 0 +OP4 E01E28 0 +OP4 E01E29 0 +OP4 E01E2A 0 +OP4 E01E2B 0 +OP4 E01E2C 0 +OP4 E01E2D 0 +OP4 E01E2E 0 +OP4 E01E2F 0 +OP4 E01E30 0 +OP4 E01E31 0 +OP4 E01E32 0 +OP4 E01E33 0 +OP4 E01E34 0 +OP4 E01E35 0 +OP4 E01E36 0 +OP4 E01E37 0 +OP4 E01E38 0 +OP4 E01E39 0 +OP4 E01E3A 0 +OP4 E01E3B 0 +OP4 E01E3C 0 +OP4 E01E3D 0 +OP4 E01E3E 0 +OP4 E01E3F 0 +OP4 E01E40 0 +OP4 E01E41 0 +OP4 E01E42 0 +OP4 E01E43 0 +OP4 E01E44 0 +OP4 E01E45 0 +OP4 E01E46 0 +OP4 E01E47 0 +OP4 E01E48 0 +OP4 E01E49 0 +OP4 E01E4A 0 +OP4 E01E4B 0 +OP4 E01E4C 0 +OP4 E01E4D 0 +OP4 E01E4E 0 +OP4 E01E4F 0 +OP4 E01E50 0 +OP4 E01E51 0 +OP4 E01E52 0 +OP4 E01E53 0 +OP4 E01E54 0 +OP4 E01E55 0 +OP4 E01E56 0 +OP4 E01E57 0 +OP4 E01E58 0 +OP4 E01E59 0 +OP4 E01E5A 0 +OP4 E01E5B 0 +OP4 E01E5C 0 +OP4 E01E5D 0 +OP4 E01E5E 0 +OP4 E01E5F 0 +OP4 E01E60 0 +OP4 E01E61 0 +OP4 E01E62 0 +OP4 E01E63 0 +OP4 E01E64 0 +OP4 E01E65 0 +OP4 E01E66 0 +OP4 E01E67 0 +OP4 E01E68 0 +OP4 E01E69 0 +OP4 E01E6A 0 +OP4 E01E6B 0 +OP4 E01E6C 0 +OP4 E01E6D 0 +OP4 E01E6E 0 +OP4 E01E6F 0 +OP4 E01E70 0 +OP4 E01E71 0 +OP4 E01E72 0 +OP4 E01E73 0 +OP4 E01E74 0 +OP4 E01E75 0 +OP4 E01E76 0 +OP4 E01E77 0 +OP4 E01E78 0 +OP4 E01E79 0 +OP4 E01E7A 0 +OP4 E01E7B 0 +OP4 E01E7C 0 +OP4 E01E7D 0 +OP4 E01E7E 0 +OP4 E01E7F 0 +OP4 E01E80 0 +OP4 E01E81 0 +OP4 E01E82 0 +OP4 E01E83 0 +OP4 E01E84 0 +OP4 E01E85 0 +OP4 E01E86 0 +OP4 E01E87 0 +OP4 E01E88 0 +OP4 E01E89 0 +OP4 E01E8A 0 +OP4 E01E8B 0 +OP4 E01E8C 0 +OP4 E01E8D 0 +OP4 E01E8E 0 +OP4 E01E8F 0 +OP4 E01E90 0 +OP4 E01E91 0 +OP4 E01E92 0 +OP4 E01E93 0 +OP4 E01E94 0 +OP4 E01E95 0 +OP4 E01E96 0 +OP4 E01E97 0 +OP4 E01E98 0 +OP4 E01E99 0 +OP4 E01E9A 0 +OP4 E01E9B 0 +OP4 E01E9C 0 +OP4 E01E9D 0 +OP4 E01E9E 0 +OP4 E01E9F 0 +OP4 E01EA0 0 +OP4 E01EA1 0 +OP4 E01EA2 0 +OP4 E01EA3 0 +OP4 E01EA4 0 +OP4 E01EA5 0 +OP4 E01EA6 0 +OP4 E01EA7 0 +OP4 E01EA8 0 +OP4 E01EA9 0 +OP4 E01EAA 0 +OP4 E01EAB 0 +OP4 E01EAC 0 +OP4 E01EAD 0 +OP4 E01EAE 0 +OP4 E01EAF 0 +OP4 E01EB0 0 +OP4 E01EB1 0 +OP4 E01EB2 0 +OP4 E01EB3 0 +OP4 E01EB4 0 +OP4 E01EB5 0 +OP4 E01EB6 0 +OP4 E01EB7 0 +OP4 E01EB8 0 +OP4 E01EB9 0 +OP4 E01EBA 0 +OP4 E01EBB 0 +OP4 E01EBC 0 +OP4 E01EBD 0 +OP4 E01EBE 0 +OP4 E01EBF 0 +OP4 E01EC0 0 +OP4 E01EC1 0 +OP4 E01EC2 0 +OP4 E01EC3 0 +OP4 E01EC4 0 +OP4 E01EC5 0 +OP4 E01EC6 0 +OP4 E01EC7 0 +OP4 E01EC8 0 +OP4 E01EC9 0 +OP4 E01ECA 0 +OP4 E01ECB 0 +OP4 E01ECC 0 +OP4 E01ECD 0 +OP4 E01ECE 0 +OP4 E01ECF 0 +OP4 E01ED0 0 +OP4 E01ED1 0 +OP4 E01ED2 0 +OP4 E01ED3 0 +OP4 E01ED4 0 +OP4 E01ED5 0 +OP4 E01ED6 0 +OP4 E01ED7 0 +OP4 E01ED8 0 +OP4 E01ED9 0 +OP4 E01EDA 0 +OP4 E01EDB 0 +OP4 E01EDC 0 +OP4 E01EDD 0 +OP4 E01EDE 0 +OP4 E01EDF 0 +OP4 E01EE0 0 +OP4 E01EE1 0 +OP4 E01EE2 0 +OP4 E01EE3 0 +OP4 E01EE4 0 +OP4 E01EE5 0 +OP4 E01EE6 0 +OP4 E01EE7 0 +OP4 E01EE8 0 +OP4 E01EE9 0 +OP4 E01EEA 0 +OP4 E01EEB 0 +OP4 E01EEC 0 +OP4 E01EED 0 +OP4 E01EEE 0 +OP4 E01EEF 0 +OP4 E01EF0 0 +OP4 E01EF1 0 +OP4 E01EF2 0 +OP4 E01EF3 0 +OP4 E01EF4 0 +OP4 E01EF5 0 +OP4 E01EF6 0 +OP4 E01EF7 0 +OP4 E01EF8 0 +OP4 E01EF9 0 +OP4 E01EFA 0 +OP4 E01EFB 0 +OP4 E01EFC 0 +OP4 E01EFD 0 +OP4 E01EFE 0 +OP4 E01EFF 0 +OP4 E01F00 0 +OP4 E01F01 0 +OP4 E01F02 0 +OP4 E01F03 0 +OP4 E01F04 0 +OP4 E01F05 0 +OP4 E01F06 0 +OP4 E01F07 0 +OP4 E01F08 0 +OP4 E01F09 0 +OP4 E01F0A 0 +OP4 E01F0B 0 +OP4 E01F0C 0 +OP4 E01F0D 0 +OP4 E01F0E 0 +OP4 E01F0F 0 +OP4 E01F10 0 +OP4 E01F11 0 +OP4 E01F12 0 +OP4 E01F13 0 +OP4 E01F14 0 +OP4 E01F15 0 +OP4 E01F16 0 +OP4 E01F17 0 +OP4 E01F18 0 +OP4 E01F19 0 +OP4 E01F1A 0 +OP4 E01F1B 0 +OP4 E01F1C 0 +OP4 E01F1D 0 +OP4 E01F1E 0 +OP4 E01F1F 0 +OP4 E01F20 0 +OP4 E01F21 0 +OP4 E01F22 0 +OP4 E01F23 0 +OP4 E01F24 0 +OP4 E01F25 0 +OP4 E01F26 0 +OP4 E01F27 0 +OP4 E01F28 0 +OP4 E01F29 0 +OP4 E01F2A 0 +OP4 E01F2B 0 +OP4 E01F2C 0 +OP4 E01F2D 0 +OP4 E01F2E 0 +OP4 E01F2F 0 +OP4 E01F30 0 +OP4 E01F31 0 +OP4 E01F32 0 +OP4 E01F33 0 +OP4 E01F34 0 +OP4 E01F35 0 +OP4 E01F36 0 +OP4 E01F37 0 +OP4 E01F38 0 +OP4 E01F39 0 +OP4 E01F3A 0 +OP4 E01F3B 0 +OP4 E01F3C 0 +OP4 E01F3D 0 +OP4 E01F3E 0 +OP4 E01F3F 0 +OP4 E01F40 0 +OP4 E01F41 0 +OP4 E01F42 0 +OP4 E01F43 0 +OP4 E01F44 0 +OP4 E01F45 0 +OP4 E01F46 0 +OP4 E01F47 0 +OP4 E01F48 0 +OP4 E01F49 0 +OP4 E01F4A 0 +OP4 E01F4B 0 +OP4 E01F4C 0 +OP4 E01F4D 0 +OP4 E01F4E 0 +OP4 E01F4F 0 +OP4 E01F50 0 +OP4 E01F51 0 +OP4 E01F52 0 +OP4 E01F53 0 +OP4 E01F54 0 +OP4 E01F55 0 +OP4 E01F56 0 +OP4 E01F57 0 +OP4 E01F58 0 +OP4 E01F59 0 +OP4 E01F5A 0 +OP4 E01F5B 0 +OP4 E01F5C 0 +OP4 E01F5D 0 +OP4 E01F5E 0 +OP4 E01F5F 0 +OP4 E01F60 0 +OP4 E01F61 0 +OP4 E01F62 0 +OP4 E01F63 0 +OP4 E01F64 0 +OP4 E01F65 0 +OP4 E01F66 0 +OP4 E01F67 0 +OP4 E01F68 0 +OP4 E01F69 0 +OP4 E01F6A 0 +OP4 E01F6B 0 +OP4 E01F6C 0 +OP4 E01F6D 0 +OP4 E01F6E 0 +OP4 E01F6F 0 +OP4 E01F70 0 +OP4 E01F71 0 +OP4 E01F72 0 +OP4 E01F73 0 +OP4 E01F74 0 +OP4 E01F75 0 +OP4 E01F76 0 +OP4 E01F77 0 +OP4 E01F78 0 +OP4 E01F79 0 +OP4 E01F7A 0 +OP4 E01F7B 0 +OP4 E01F7C 0 +OP4 E01F7D 0 +OP4 E01F7E 0 +OP4 E01F7F 0 +OP4 E01F80 0 +OP4 E01F81 0 +OP4 E01F82 0 +OP4 E01F83 0 +OP4 E01F84 0 +OP4 E01F85 0 +OP4 E01F86 0 +OP4 E01F87 0 +OP4 E01F88 0 +OP4 E01F89 0 +OP4 E01F8A 0 +OP4 E01F8B 0 +OP4 E01F8C 0 +OP4 E01F8D 0 +OP4 E01F8E 0 +OP4 E01F8F 0 +OP4 E01F90 0 +OP4 E01F91 0 +OP4 E01F92 0 +OP4 E01F93 0 +OP4 E01F94 0 +OP4 E01F95 0 +OP4 E01F96 0 +OP4 E01F97 0 +OP4 E01F98 0 +OP4 E01F99 0 +OP4 E01F9A 0 +OP4 E01F9B 0 +OP4 E01F9C 0 +OP4 E01F9D 0 +OP4 E01F9E 0 +OP4 E01F9F 0 +OP4 E01FA0 0 +OP4 E01FA1 0 +OP4 E01FA2 0 +OP4 E01FA3 0 +OP4 E01FA4 0 +OP4 E01FA5 0 +OP4 E01FA6 0 +OP4 E01FA7 0 +OP4 E01FA8 0 +OP4 E01FA9 0 +OP4 E01FAA 0 +OP4 E01FAB 0 +OP4 E01FAC 0 +OP4 E01FAD 0 +OP4 E01FAE 0 +OP4 E01FAF 0 +OP4 E01FB0 0 +OP4 E01FB1 0 +OP4 E01FB2 0 +OP4 E01FB3 0 +OP4 E01FB4 0 +OP4 E01FB5 0 +OP4 E01FB6 0 +OP4 E01FB7 0 +OP4 E01FB8 0 +OP4 E01FB9 0 +OP4 E01FBA 0 +OP4 E01FBB 0 +OP4 E01FBC 0 +OP4 E01FBD 0 +OP4 E01FBE 0 +OP4 E01FBF 0 +OP4 E01FC0 0 +OP4 E01FC1 0 +OP4 E01FC2 0 +OP4 E01FC3 0 +OP4 E01FC4 0 +OP4 E01FC5 0 +OP4 E01FC6 0 +OP4 E01FC7 0 +OP4 E01FC8 0 +OP4 E01FC9 0 +OP4 E01FCA 0 +OP4 E01FCB 0 +OP4 E01FCC 0 +OP4 E01FCD 0 +OP4 E01FCE 0 +OP4 E01FCF 0 +OP4 E01FD0 0 +OP4 E01FD1 0 +OP4 E01FD2 0 +OP4 E01FD3 0 +OP4 E01FD4 0 +OP4 E01FD5 0 +OP4 E01FD6 0 +OP4 E01FD7 0 +OP4 E01FD8 0 +OP4 E01FD9 0 +OP4 E01FDA 0 +OP4 E01FDB 0 +OP4 E01FDC 0 +OP4 E01FDD 0 +OP4 E01FDE 0 +OP4 E01FDF 0 +OP4 E01FE0 0 +OP4 E01FE1 0 +OP4 E01FE2 0 +OP4 E01FE3 0 +OP4 E01FE4 0 +OP4 E01FE5 0 +OP4 E01FE6 0 +OP4 E01FE7 0 +OP4 E01FE8 0 +OP4 E01FE9 0 +OP4 E01FEA 0 +OP4 E01FEB 0 +OP4 E01FEC 0 +OP4 E01FED 0 +OP4 E01FEE 0 +OP4 E01FEF 0 +OP4 E01FF0 0 +OP4 E01FF1 0 +OP4 E01FF2 0 +OP4 E01FF3 0 +OP4 E01FF4 0 +OP4 E01FF5 0 +OP4 E01FF6 0 +OP4 E01FF7 0 +OP4 E01FF8 0 +OP4 E01FF9 0 +OP4 E01FFA 0 +OP4 E01FFB 0 +OP4 E01FFC 0 +OP4 E01FFD 0 +OP4 E01FFE 0 +OP4 E01FFF 0 +OP4 E02000 0 +OP4 E02001 0 +OP4 E02002 0 +OP4 E02003 0 +OP4 E02004 0 +OP4 E02005 0 +OP4 E02006 0 +OP4 E02007 0 +OP4 E02008 0 +OP4 E02009 0 +OP4 E0200A 0 +OP4 E0200B 0 +OP4 E0200C 0 +OP4 E0200D 0 +OP4 E0200E 0 +OP4 E0200F 0 +OP4 E02010 0 +OP4 E02011 0 +OP4 E02012 0 +OP4 E02013 0 +OP4 E02014 0 +OP4 E02015 0 +OP4 E02016 0 +OP4 E02017 0 +OP4 E02018 0 +OP4 E02019 0 +OP4 E0201A 0 +OP4 E0201B 0 +OP4 E0201C 0 +OP4 E0201D 0 +OP4 E0201E 0 +OP4 E0201F 0 +OP4 E02020 0 +OP4 E02021 0 +OP4 E02022 0 +OP4 E02023 0 +OP4 E02024 0 +OP4 E02025 0 +OP4 E02026 0 +OP4 E02027 0 +OP4 E02028 0 +OP4 E02029 0 +OP4 E0202A 0 +OP4 E0202B 0 +OP4 E0202C 0 +OP4 E0202D 0 +OP4 E0202E 0 +OP4 E0202F 0 +OP4 E02030 0 +OP4 E02031 0 +OP4 E02032 0 +OP4 E02033 0 +OP4 E02034 0 +OP4 E02035 0 +OP4 E02036 0 +OP4 E02037 0 +OP4 E02038 0 +OP4 E02039 0 +OP4 E0203A 0 +OP4 E0203B 0 +OP4 E0203C 0 +OP4 E0203D 0 +OP4 E0203E 0 +OP4 E0203F 0 +OP4 E02040 0 +OP4 E02041 0 +OP4 E02042 0 +OP4 E02043 0 +OP4 E02044 0 +OP4 E02045 0 +OP4 E02046 0 +OP4 E02047 0 +OP4 E02048 0 +OP4 E02049 0 +OP4 E0204A 0 +OP4 E0204B 0 +OP4 E0204C 0 +OP4 E0204D 0 +OP4 E0204E 0 +OP4 E0204F 0 +OP4 E02050 0 +OP4 E02051 0 +OP4 E02052 0 +OP4 E02053 0 +OP4 E02054 0 +OP4 E02055 0 +OP4 E02056 0 +OP4 E02057 0 +OP4 E02058 0 +OP4 E02059 0 +OP4 E0205A 0 +OP4 E0205B 0 +OP4 E0205C 0 +OP4 E0205D 0 +OP4 E0205E 0 +OP4 E0205F 0 +OP4 E02060 0 +OP4 E02061 0 +OP4 E02062 0 +OP4 E02063 0 +OP4 E02064 0 +OP4 E02065 0 +OP4 E02066 0 +OP4 E02067 0 +OP4 E02068 0 +OP4 E02069 0 +OP4 E0206A 0 +OP4 E0206B 0 +OP4 E0206C 0 +OP4 E0206D 0 +OP4 E0206E 0 +OP4 E0206F 0 +OP4 E02070 0 +OP4 E02071 0 +OP4 E02072 0 +OP4 E02073 0 +OP4 E02074 0 +OP4 E02075 0 +OP4 E02076 0 +OP4 E02077 0 +OP4 E02078 0 +OP4 E02079 0 +OP4 E0207A 0 +OP4 E0207B 0 +OP4 E0207C 0 +OP4 E0207D 0 +OP4 E0207E 0 +OP4 E0207F 0 +OP4 E02080 0 +OP4 E02081 0 +OP4 E02082 0 +OP4 E02083 0 +OP4 E02084 0 +OP4 E02085 0 +OP4 E02086 0 +OP4 E02087 0 +OP4 E02088 0 +OP4 E02089 0 +OP4 E0208A 0 +OP4 E0208B 0 +OP4 E0208C 0 +OP4 E0208D 0 +OP4 E0208E 0 +OP4 E0208F 0 +OP4 E02090 0 +OP4 E02091 0 +OP4 E02092 0 +OP4 E02093 0 +OP4 E02094 0 +OP4 E02095 0 +OP4 E02096 0 +OP4 E02097 0 +OP4 E02098 0 +OP4 E02099 0 +OP4 E0209A 0 +OP4 E0209B 0 +OP4 E0209C 0 +OP4 E0209D 0 +OP4 E0209E 0 +OP4 E0209F 0 +OP4 E020A0 0 +OP4 E020A1 0 +OP4 E020A2 0 +OP4 E020A3 0 +OP4 E020A4 0 +OP4 E020A5 0 +OP4 E020A6 0 +OP4 E020A7 0 +OP4 E020A8 0 +OP4 E020A9 0 +OP4 E020AA 0 +OP4 E020AB 0 +OP4 E020AC 0 +OP4 E020AD 0 +OP4 E020AE 0 +OP4 E020AF 0 +OP4 E020B0 0 +OP4 E020B1 0 +OP4 E020B2 0 +OP4 E020B3 0 +OP4 E020B4 0 +OP4 E020B5 0 +OP4 E020B6 0 +OP4 E020B7 0 +OP4 E020B8 0 +OP4 E020B9 0 +OP4 E020BA 0 +OP4 E020BB 0 +OP4 E020BC 0 +OP4 E020BD 0 +OP4 E020BE 0 +OP4 E020BF 0 +OP4 E020C0 0 +OP4 E020C1 0 +OP4 E020C2 0 +OP4 E020C3 0 +OP4 E020C4 0 +OP4 E020C5 0 +OP4 E020C6 0 +OP4 E020C7 0 +OP4 E020C8 0 +OP4 E020C9 0 +OP4 E020CA 0 +OP4 E020CB 0 +OP4 E020CC 0 +OP4 E020CD 0 +OP4 E020CE 0 +OP4 E020CF 0 +OP4 E020D0 0 +OP4 E020D1 0 +OP4 E020D2 0 +OP4 E020D3 0 +OP4 E020D4 0 +OP4 E020D5 0 +OP4 E020D6 0 +OP4 E020D7 0 +OP4 E020D8 0 +OP4 E020D9 0 +OP4 E020DA 0 +OP4 E020DB 0 +OP4 E020DC 0 +OP4 E020DD 0 +OP4 E020DE 0 +OP4 E020DF 0 +OP4 E020E0 0 +OP4 E020E1 0 +OP4 E020E2 0 +OP4 E020E3 0 +OP4 E020E4 0 +OP4 E020E5 0 +OP4 E020E6 0 +OP4 E020E7 0 +OP4 E020E8 0 +OP4 E020E9 0 +OP4 E020EA 0 +OP4 E020EB 0 +OP4 E020EC 0 +OP4 E020ED 0 +OP4 E020EE 0 +OP4 E020EF 0 +OP4 E020F0 0 +OP4 E020F1 0 +OP4 E020F2 0 +OP4 E020F3 0 +OP4 E020F4 0 +OP4 E020F5 0 +OP4 E020F6 0 +OP4 E020F7 0 +OP4 E020F8 0 +OP4 E020F9 0 +OP4 E020FA 0 +OP4 E020FB 0 +OP4 E020FC 0 +OP4 E020FD 0 +OP4 E020FE 0 +OP4 E020FF 0 +OP4 E02100 0 +OP4 E02101 0 +OP4 E02102 0 +OP4 E02103 0 +OP4 E02104 0 +OP4 E02105 0 +OP4 E02106 0 +OP4 E02107 0 +OP4 E02108 0 +OP4 E02109 0 +OP4 E0210A 0 +OP4 E0210B 0 +OP4 E0210C 0 +OP4 E0210D 0 +OP4 E0210E 0 +OP4 E0210F 0 +OP4 E02110 0 +OP4 E02111 0 +OP4 E02112 0 +OP4 E02113 0 +OP4 E02114 0 +OP4 E02115 0 +OP4 E02116 0 +OP4 E02117 0 +OP4 E02118 0 +OP4 E02119 0 +OP4 E0211A 0 +OP4 E0211B 0 +OP4 E0211C 0 +OP4 E0211D 0 +OP4 E0211E 0 +OP4 E0211F 0 +OP4 E02120 0 +OP4 E02121 0 +OP4 E02122 0 +OP4 E02123 0 +OP4 E02124 0 +OP4 E02125 0 +OP4 E02126 0 +OP4 E02127 0 +OP4 E02128 0 +OP4 E02129 0 +OP4 E0212A 0 +OP4 E0212B 0 +OP4 E0212C 0 +OP4 E0212D 0 +OP4 E0212E 0 +OP4 E0212F 0 +OP4 E02130 0 +OP4 E02131 0 +OP4 E02132 0 +OP4 E02133 0 +OP4 E02134 0 +OP4 E02135 0 +OP4 E02136 0 +OP4 E02137 0 +OP4 E02138 0 +OP4 E02139 0 +OP4 E0213A 0 +OP4 E0213B 0 +OP4 E0213C 0 +OP4 E0213D 0 +OP4 E0213E 0 +OP4 E0213F 0 +OP4 E02140 0 +OP4 E02141 0 +OP4 E02142 0 +OP4 E02143 0 +OP4 E02144 0 +OP4 E02145 0 +OP4 E02146 0 +OP4 E02147 0 +OP4 E02148 0 +OP4 E02149 0 +OP4 E0214A 0 +OP4 E0214B 0 +OP4 E0214C 0 +OP4 E0214D 0 +OP4 E0214E 0 +OP4 E0214F 0 +OP4 E02150 0 +OP4 E02151 0 +OP4 E02152 0 +OP4 E02153 0 +OP4 E02154 0 +OP4 E02155 0 +OP4 E02156 0 +OP4 E02157 0 +OP4 E02158 0 +OP4 E02159 0 +OP4 E0215A 0 +OP4 E0215B 0 +OP4 E0215C 0 +OP4 E0215D 0 +OP4 E0215E 0 +OP4 E0215F 0 +OP4 E02160 0 +OP4 E02161 0 +OP4 E02162 0 +OP4 E02163 0 +OP4 E02164 0 +OP4 E02165 0 +OP4 E02166 0 +OP4 E02167 0 +OP4 E02168 0 +OP4 E02169 0 +OP4 E0216A 0 +OP4 E0216B 0 +OP4 E0216C 0 +OP4 E0216D 0 +OP4 E0216E 0 +OP4 E0216F 0 +OP4 E02170 0 +OP4 E02171 0 +OP4 E02172 0 +OP4 E02173 0 +OP4 E02174 0 +OP4 E02175 0 +OP4 E02176 0 +OP4 E02177 0 +OP4 E02178 0 +OP4 E02179 0 +OP4 E0217A 0 +OP4 E0217B 0 +OP4 E0217C 0 +OP4 E0217D 0 +OP4 E0217E 0 +OP4 E0217F 0 +OP4 E02180 0 +OP4 E02181 0 +OP4 E02182 0 +OP4 E02183 0 +OP4 E02184 0 +OP4 E02185 0 +OP4 E02186 0 +OP4 E02187 0 +OP4 E02188 0 +OP4 E02189 0 +OP4 E0218A 0 +OP4 E0218B 0 +OP4 E0218C 0 +OP4 E0218D 0 +OP4 E0218E 0 +OP4 E0218F 0 +OP4 E02190 0 +OP4 E02191 0 +OP4 E02192 0 +OP4 E02193 0 +OP4 E02194 0 +OP4 E02195 0 +OP4 E02196 0 +OP4 E02197 0 +OP4 E02198 0 +OP4 E02199 0 +OP4 E0219A 0 +OP4 E0219B 0 +OP4 E0219C 0 +OP4 E0219D 0 +OP4 E0219E 0 +OP4 E0219F 0 +OP4 E021A0 0 +OP4 E021A1 0 +OP4 E021A2 0 +OP4 E021A3 0 +OP4 E021A4 0 +OP4 E021A5 0 +OP4 E021A6 0 +OP4 E021A7 0 +OP4 E021A8 0 +OP4 E021A9 0 +OP4 E021AA 0 +OP4 E021AB 0 +OP4 E021AC 0 +OP4 E021AD 0 +OP4 E021AE 0 +OP4 E021AF 0 +OP4 E021B0 0 +OP4 E021B1 0 +OP4 E021B2 0 +OP4 E021B3 0 +OP4 E021B4 0 +OP4 E021B5 0 +OP4 E021B6 0 +OP4 E021B7 0 +OP4 E021B8 0 +OP4 E021B9 0 +OP4 E021BA 0 +OP4 E021BB 0 +OP4 E021BC 0 +OP4 E021BD 0 +OP4 E021BE 0 +OP4 E021BF 0 +OP4 E021C0 0 +OP4 E021C1 0 +OP4 E021C2 0 +OP4 E021C3 0 +OP4 E021C4 0 +OP4 E021C5 0 +OP4 E021C6 0 +OP4 E021C7 0 +OP4 E021C8 0 +OP4 E021C9 0 +OP4 E021CA 0 +OP4 E021CB 0 +OP4 E021CC 0 +OP4 E021CD 0 +OP4 E021CE 0 +OP4 E021CF 0 +OP4 E021D0 0 +OP4 E021D1 0 +OP4 E021D2 0 +OP4 E021D3 0 +OP4 E021D4 0 +OP4 E021D5 0 +OP4 E021D6 0 +OP4 E021D7 0 +OP4 E021D8 0 +OP4 E021D9 0 +OP4 E021DA 0 +OP4 E021DB 0 +OP4 E021DC 0 +OP4 E021DD 0 +OP4 E021DE 0 +OP4 E021DF 0 +OP4 E021E0 0 +OP4 E021E1 0 +OP4 E021E2 0 +OP4 E021E3 0 +OP4 E021E4 0 +OP4 E021E5 0 +OP4 E021E6 0 +OP4 E021E7 0 +OP4 E021E8 0 +OP4 E021E9 0 +OP4 E021EA 0 +OP4 E021EB 0 +OP4 E021EC 0 +OP4 E021ED 0 +OP4 E021EE 0 +OP4 E021EF 0 +OP4 E021F0 0 +OP4 E021F1 0 +OP4 E021F2 0 +OP4 E021F3 0 +OP4 E021F4 0 +OP4 E021F5 0 +OP4 E021F6 0 +OP4 E021F7 0 +OP4 E021F8 0 +OP4 E021F9 0 +OP4 E021FA 0 +OP4 E021FB 0 +OP4 E021FC 0 +OP4 E021FD 0 +OP4 E021FE 0 +OP4 E021FF 0 +OP4 E02200 0 +OP4 E02201 0 +OP4 E02202 0 +OP4 E02203 0 +OP4 E02204 0 +OP4 E02205 0 +OP4 E02206 0 +OP4 E02207 0 +OP4 E02208 0 +OP4 E02209 0 +OP4 E0220A 0 +OP4 E0220B 0 +OP4 E0220C 0 +OP4 E0220D 0 +OP4 E0220E 0 +OP4 E0220F 0 +OP4 E02210 0 +OP4 E02211 0 +OP4 E02212 0 +OP4 E02213 0 +OP4 E02214 0 +OP4 E02215 0 +OP4 E02216 0 +OP4 E02217 0 +OP4 E02218 0 +OP4 E02219 0 +OP4 E0221A 0 +OP4 E0221B 0 +OP4 E0221C 0 +OP4 E0221D 0 +OP4 E0221E 0 +OP4 E0221F 0 +OP4 E02220 0 +OP4 E02221 0 +OP4 E02222 0 +OP4 E02223 0 +OP4 E02224 0 +OP4 E02225 0 +OP4 E02226 0 +OP4 E02227 0 +OP4 E02228 0 +OP4 E02229 0 +OP4 E0222A 0 +OP4 E0222B 0 +OP4 E0222C 0 +OP4 E0222D 0 +OP4 E0222E 0 +OP4 E0222F 0 +OP4 E02230 0 +OP4 E02231 0 +OP4 E02232 0 +OP4 E02233 0 +OP4 E02234 0 +OP4 E02235 0 +OP4 E02236 0 +OP4 E02237 0 +OP4 E02238 0 +OP4 E02239 0 +OP4 E0223A 0 +OP4 E0223B 0 +OP4 E0223C 0 +OP4 E0223D 0 +OP4 E0223E 0 +OP4 E0223F 0 +OP4 E02240 0 +OP4 E02241 0 +OP4 E02242 0 +OP4 E02243 0 +OP4 E02244 0 +OP4 E02245 0 +OP4 E02246 0 +OP4 E02247 0 +OP4 E02248 0 +OP4 E02249 0 +OP4 E0224A 0 +OP4 E0224B 0 +OP4 E0224C 0 +OP4 E0224D 0 +OP4 E0224E 0 +OP4 E0224F 0 +OP4 E02250 0 +OP4 E02251 0 +OP4 E02252 0 +OP4 E02253 0 +OP4 E02254 0 +OP4 E02255 0 +OP4 E02256 0 +OP4 E02257 0 +OP4 E02258 0 +OP4 E02259 0 +OP4 E0225A 0 +OP4 E0225B 0 +OP4 E0225C 0 +OP4 E0225D 0 +OP4 E0225E 0 +OP4 E0225F 0 +OP4 E02260 0 +OP4 E02261 0 +OP4 E02262 0 +OP4 E02263 0 +OP4 E02264 0 +OP4 E02265 0 +OP4 E02266 0 +OP4 E02267 0 +OP4 E02268 0 +OP4 E02269 0 +OP4 E0226A 0 +OP4 E0226B 0 +OP4 E0226C 0 +OP4 E0226D 0 +OP4 E0226E 0 +OP4 E0226F 0 +OP4 E02270 0 +OP4 E02271 0 +OP4 E02272 0 +OP4 E02273 0 +OP4 E02274 0 +OP4 E02275 0 +OP4 E02276 0 +OP4 E02277 0 +OP4 E02278 0 +OP4 E02279 0 +OP4 E0227A 0 +OP4 E0227B 0 +OP4 E0227C 0 +OP4 E0227D 0 +OP4 E0227E 0 +OP4 E0227F 0 +OP4 E02280 0 +OP4 E02281 0 +OP4 E02282 0 +OP4 E02283 0 +OP4 E02284 0 +OP4 E02285 0 +OP4 E02286 0 +OP4 E02287 0 +OP4 E02288 0 +OP4 E02289 0 +OP4 E0228A 0 +OP4 E0228B 0 +OP4 E0228C 0 +OP4 E0228D 0 +OP4 E0228E 0 +OP4 E0228F 0 +OP4 E02290 0 +OP4 E02291 0 +OP4 E02292 0 +OP4 E02293 0 +OP4 E02294 0 +OP4 E02295 0 +OP4 E02296 0 +OP4 E02297 0 +OP4 E02298 0 +OP4 E02299 0 +OP4 E0229A 0 +OP4 E0229B 0 +OP4 E0229C 0 +OP4 E0229D 0 +OP4 E0229E 0 +OP4 E0229F 0 +OP4 E022A0 0 +OP4 E022A1 0 +OP4 E022A2 0 +OP4 E022A3 0 +OP4 E022A4 0 +OP4 E022A5 0 +OP4 E022A6 0 +OP4 E022A7 0 +OP4 E022A8 0 +OP4 E022A9 0 +OP4 E022AA 0 +OP4 E022AB 0 +OP4 E022AC 0 +OP4 E022AD 0 +OP4 E022AE 0 +OP4 E022AF 0 +OP4 E022B0 0 +OP4 E022B1 0 +OP4 E022B2 0 +OP4 E022B3 0 +OP4 E022B4 0 +OP4 E022B5 0 +OP4 E022B6 0 +OP4 E022B7 0 +OP4 E022B8 0 +OP4 E022B9 0 +OP4 E022BA 0 +OP4 E022BB 0 +OP4 E022BC 0 +OP4 E022BD 0 +OP4 E022BE 0 +OP4 E022BF 0 +OP4 E022C0 0 +OP4 E022C1 0 +OP4 E022C2 0 +OP4 E022C3 0 +OP4 E022C4 0 +OP4 E022C5 0 +OP4 E022C6 0 +OP4 E022C7 0 +OP4 E022C8 0 +OP4 E022C9 0 +OP4 E022CA 0 +OP4 E022CB 0 +OP4 E022CC 0 +OP4 E022CD 0 +OP4 E022CE 0 +OP4 E022CF 0 +OP4 E022D0 0 +OP4 E022D1 0 +OP4 E022D2 0 +OP4 E022D3 0 +OP4 E022D4 0 +OP4 E022D5 0 +OP4 E022D6 0 +OP4 E022D7 0 +OP4 E022D8 0 +OP4 E022D9 0 +OP4 E022DA 0 +OP4 E022DB 0 +OP4 E022DC 0 +OP4 E022DD 0 +OP4 E022DE 0 +OP4 E022DF 0 +OP4 E022E0 0 +OP4 E022E1 0 +OP4 E022E2 0 +OP4 E022E3 0 +OP4 E022E4 0 +OP4 E022E5 0 +OP4 E022E6 0 +OP4 E022E7 0 +OP4 E022E8 0 +OP4 E022E9 0 +OP4 E022EA 0 +OP4 E022EB 0 +OP4 E022EC 0 +OP4 E022ED 0 +OP4 E022EE 0 +OP4 E022EF 0 +OP4 E022F0 0 +OP4 E022F1 0 +OP4 E022F2 0 +OP4 E022F3 0 +OP4 E022F4 0 +OP4 E022F5 0 +OP4 E022F6 0 +OP4 E022F7 0 +OP4 E022F8 0 +OP4 E022F9 0 +OP4 E022FA 0 +OP4 E022FB 0 +OP4 E022FC 0 +OP4 E022FD 0 +OP4 E022FE 0 +OP4 E022FF 0 +OP4 E02300 0 +OP4 E02301 0 +OP4 E02302 0 +OP4 E02303 0 +OP4 E02304 0 +OP4 E02305 0 +OP4 E02306 0 +OP4 E02307 0 +OP4 E02308 0 +OP4 E02309 0 +OP4 E0230A 0 +OP4 E0230B 0 +OP4 E0230C 0 +OP4 E0230D 0 +OP4 E0230E 0 +OP4 E0230F 0 +OP4 E02310 0 +OP4 E02311 0 +OP4 E02312 0 +OP4 E02313 0 +OP4 E02314 0 +OP4 E02315 0 +OP4 E02316 0 +OP4 E02317 0 +OP4 E02318 0 +OP4 E02319 0 +OP4 E0231A 0 +OP4 E0231B 0 +OP4 E0231C 0 +OP4 E0231D 0 +OP4 E0231E 0 +OP4 E0231F 0 +OP4 E02320 0 +OP4 E02321 0 +OP4 E02322 0 +OP4 E02323 0 +OP4 E02324 0 +OP4 E02325 0 +OP4 E02326 0 +OP4 E02327 0 +OP4 E02328 0 +OP4 E02329 0 +OP4 E0232A 0 +OP4 E0232B 0 +OP4 E0232C 0 +OP4 E0232D 0 +OP4 E0232E 0 +OP4 E0232F 0 +OP4 E02330 0 +OP4 E02331 0 +OP4 E02332 0 +OP4 E02333 0 +OP4 E02334 0 +OP4 E02335 0 +OP4 E02336 0 +OP4 E02337 0 +OP4 E02338 0 +OP4 E02339 0 +OP4 E0233A 0 +OP4 E0233B 0 +OP4 E0233C 0 +OP4 E0233D 0 +OP4 E0233E 0 +OP4 E0233F 0 +OP4 E02340 0 +OP4 E02341 0 +OP4 E02342 0 +OP4 E02343 0 +OP4 E02344 0 +OP4 E02345 0 +OP4 E02346 0 +OP4 E02347 0 +OP4 E02348 0 +OP4 E02349 0 +OP4 E0234A 0 +OP4 E0234B 0 +OP4 E0234C 0 +OP4 E0234D 0 +OP4 E0234E 0 +OP4 E0234F 0 +OP4 E02350 0 +OP4 E02351 0 +OP4 E02352 0 +OP4 E02353 0 +OP4 E02354 0 +OP4 E02355 0 +OP4 E02356 0 +OP4 E02357 0 +OP4 E02358 0 +OP4 E02359 0 +OP4 E0235A 0 +OP4 E0235B 0 +OP4 E0235C 0 +OP4 E0235D 0 +OP4 E0235E 0 +OP4 E0235F 0 +OP4 E02360 0 +OP4 E02361 0 +OP4 E02362 0 +OP4 E02363 0 +OP4 E02364 0 +OP4 E02365 0 +OP4 E02366 0 +OP4 E02367 0 +OP4 E02368 0 +OP4 E02369 0 +OP4 E0236A 0 +OP4 E0236B 0 +OP4 E0236C 0 +OP4 E0236D 0 +OP4 E0236E 0 +OP4 E0236F 0 +OP4 E02370 0 +OP4 E02371 0 +OP4 E02372 0 +OP4 E02373 0 +OP4 E02374 0 +OP4 E02375 0 +OP4 E02376 0 +OP4 E02377 0 +OP4 E02378 0 +OP4 E02379 0 +OP4 E0237A 0 +OP4 E0237B 0 +OP4 E0237C 0 +OP4 E0237D 0 +OP4 E0237E 0 +OP4 E0237F 0 +OP4 E02380 0 +OP4 E02381 0 +OP4 E02382 0 +OP4 E02383 0 +OP4 E02384 0 +OP4 E02385 0 +OP4 E02386 0 +OP4 E02387 0 +OP4 E02388 0 +OP4 E02389 0 +OP4 E0238A 0 +OP4 E0238B 0 +OP4 E0238C 0 +OP4 E0238D 0 +OP4 E0238E 0 +OP4 E0238F 0 +OP4 E02390 0 +OP4 E02391 0 +OP4 E02392 0 +OP4 E02393 0 +OP4 E02394 0 +OP4 E02395 0 +OP4 E02396 0 +OP4 E02397 0 +OP4 E02398 0 +OP4 E02399 0 +OP4 E0239A 0 +OP4 E0239B 0 +OP4 E0239C 0 +OP4 E0239D 0 +OP4 E0239E 0 +OP4 E0239F 0 +OP4 E023A0 0 +OP4 E023A1 0 +OP4 E023A2 0 +OP4 E023A3 0 +OP4 E023A4 0 +OP4 E023A5 0 +OP4 E023A6 0 +OP4 E023A7 0 +OP4 E023A8 0 +OP4 E023A9 0 +OP4 E023AA 0 +OP4 E023AB 0 +OP4 E023AC 0 +OP4 E023AD 0 +OP4 E023AE 0 +OP4 E023AF 0 +OP4 E023B0 0 +OP4 E023B1 0 +OP4 E023B2 0 +OP4 E023B3 0 +OP4 E023B4 0 +OP4 E023B5 0 +OP4 E023B6 0 +OP4 E023B7 0 +OP4 E023B8 0 +OP4 E023B9 0 +OP4 E023BA 0 +OP4 E023BB 0 +OP4 E023BC 0 +OP4 E023BD 0 +OP4 E023BE 0 +OP4 E023BF 0 +OP4 E023C0 0 +OP4 E023C1 0 +OP4 E023C2 0 +OP4 E023C3 0 +OP4 E023C4 0 +OP4 E023C5 0 +OP4 E023C6 0 +OP4 E023C7 0 +OP4 E023C8 0 +OP4 E023C9 0 +OP4 E023CA 0 +OP4 E023CB 0 +OP4 E023CC 0 +OP4 E023CD 0 +OP4 E023CE 0 +OP4 E023CF 0 +OP4 E023D0 0 +OP4 E023D1 0 +OP4 E023D2 0 +OP4 E023D3 0 +OP4 E023D4 0 +OP4 E023D5 0 +OP4 E023D6 0 +OP4 E023D7 0 +OP4 E023D8 0 +OP4 E023D9 0 +OP4 E023DA 0 +OP4 E023DB 0 +OP4 E023DC 0 +OP4 E023DD 0 +OP4 E023DE 0 +OP4 E023DF 0 +OP4 E023E0 0 +OP4 E023E1 0 +OP4 E023E2 0 +OP4 E023E3 0 +OP4 E023E4 0 +OP4 E023E5 0 +OP4 E023E6 0 +OP4 E023E7 0 +OP4 E023E8 0 +OP4 E023E9 0 +OP4 E023EA 0 +OP4 E023EB 0 +OP4 E023EC 0 +OP4 E023ED 0 +OP4 E023EE 0 +OP4 E023EF 0 +OP4 E023F0 0 +OP4 E023F1 0 +OP4 E023F2 0 +OP4 E023F3 0 +OP4 E023F4 0 +OP4 E023F5 0 +OP4 E023F6 0 +OP4 E023F7 0 +OP4 E023F8 0 +OP4 E023F9 0 +OP4 E023FA 0 +OP4 E023FB 0 +OP4 E023FC 0 +OP4 E023FD 0 +OP4 E023FE 0 +OP4 E023FF 0 +OP4 E02400 0 +OP4 E02401 0 +OP4 E02402 0 +OP4 E02403 0 +OP4 E02404 0 +OP4 E02405 0 +OP4 E02406 0 +OP4 E02407 0 +OP4 E02408 0 +OP4 E02409 0 +OP4 E0240A 0 +OP4 E0240B 0 +OP4 E0240C 0 +OP4 E0240D 0 +OP4 E0240E 0 +OP4 E0240F 0 +OP4 E02410 0 +OP4 E02411 0 +OP4 E02412 0 +OP4 E02413 0 +OP4 E02414 0 +OP4 E02415 0 +OP4 E02416 0 +OP4 E02417 0 +OP4 E02418 0 +OP4 E02419 0 +OP4 E0241A 0 +OP4 E0241B 0 +OP4 E0241C 0 +OP4 E0241D 0 +OP4 E0241E 0 +OP4 E0241F 0 +OP4 E02420 0 +OP4 E02421 0 +OP4 E02422 0 +OP4 E02423 0 +OP4 E02424 0 +OP4 E02425 0 +OP4 E02426 0 +OP4 E02427 0 +OP4 E02428 0 +OP4 E02429 0 +OP4 E0242A 0 +OP4 E0242B 0 +OP4 E0242C 0 +OP4 E0242D 0 +OP4 E0242E 0 +OP4 E0242F 0 +OP4 E02430 0 +OP4 E02431 0 +OP4 E02432 0 +OP4 E02433 0 +OP4 E02434 0 +OP4 E02435 0 +OP4 E02436 0 +OP4 E02437 0 +OP4 E02438 0 +OP4 E02439 0 +OP4 E0243A 0 +OP4 E0243B 0 +OP4 E0243C 0 +OP4 E0243D 0 +OP4 E0243E 0 +OP4 E0243F 0 +OP4 E02440 0 +OP4 E02441 0 +OP4 E02442 0 +OP4 E02443 0 +OP4 E02444 0 +OP4 E02445 0 +OP4 E02446 0 +OP4 E02447 0 +OP4 E02448 0 +OP4 E02449 0 +OP4 E0244A 0 +OP4 E0244B 0 +OP4 E0244C 0 +OP4 E0244D 0 +OP4 E0244E 0 +OP4 E0244F 0 +OP4 E02450 0 +OP4 E02451 0 +OP4 E02452 0 +OP4 E02453 0 +OP4 E02454 0 +OP4 E02455 0 +OP4 E02456 0 +OP4 E02457 0 +OP4 E02458 0 +OP4 E02459 0 +OP4 E0245A 0 +OP4 E0245B 0 +OP4 E0245C 0 +OP4 E0245D 0 +OP4 E0245E 0 +OP4 E0245F 0 +OP4 E02460 0 +OP4 E02461 0 +OP4 E02462 0 +OP4 E02463 0 +OP4 E02464 0 +OP4 E02465 0 +OP4 E02466 0 +OP4 E02467 0 +OP4 E02468 0 +OP4 E02469 0 +OP4 E0246A 0 +OP4 E0246B 0 +OP4 E0246C 0 +OP4 E0246D 0 +OP4 E0246E 0 +OP4 E0246F 0 +OP4 E02470 0 +OP4 E02471 0 +OP4 E02472 0 +OP4 E02473 0 +OP4 E02474 0 +OP4 E02475 0 +OP4 E02476 0 +OP4 E02477 0 +OP4 E02478 0 +OP4 E02479 0 +OP4 E0247A 0 +OP4 E0247B 0 +OP4 E0247C 0 +OP4 E0247D 0 +OP4 E0247E 0 +OP4 E0247F 0 +OP4 E02480 0 +OP4 E02481 0 +OP4 E02482 0 +OP4 E02483 0 +OP4 E02484 0 +OP4 E02485 0 +OP4 E02486 0 +OP4 E02487 0 +OP4 E02488 0 +OP4 E02489 0 +OP4 E0248A 0 +OP4 E0248B 0 +OP4 E0248C 0 +OP4 E0248D 0 +OP4 E0248E 0 +OP4 E0248F 0 +OP4 E02490 0 +OP4 E02491 0 +OP4 E02492 0 +OP4 E02493 0 +OP4 E02494 0 +OP4 E02495 0 +OP4 E02496 0 +OP4 E02497 0 +OP4 E02498 0 +OP4 E02499 0 +OP4 E0249A 0 +OP4 E0249B 0 +OP4 E0249C 0 +OP4 E0249D 0 +OP4 E0249E 0 +OP4 E0249F 0 +OP4 E024A0 0 +OP4 E024A1 0 +OP4 E024A2 0 +OP4 E024A3 0 +OP4 E024A4 0 +OP4 E024A5 0 +OP4 E024A6 0 +OP4 E024A7 0 +OP4 E024A8 0 +OP4 E024A9 0 +OP4 E024AA 0 +OP4 E024AB 0 +OP4 E024AC 0 +OP4 E024AD 0 +OP4 E024AE 0 +OP4 E024AF 0 +OP4 E024B0 0 +OP4 E024B1 0 +OP4 E024B2 0 +OP4 E024B3 0 +OP4 E024B4 0 +OP4 E024B5 0 +OP4 E024B6 0 +OP4 E024B7 0 +OP4 E024B8 0 +OP4 E024B9 0 +OP4 E024BA 0 +OP4 E024BB 0 +OP4 E024BC 0 +OP4 E024BD 0 +OP4 E024BE 0 +OP4 E024BF 0 +OP4 E024C0 0 +OP4 E024C1 0 +OP4 E024C2 0 +OP4 E024C3 0 +OP4 E024C4 0 +OP4 E024C5 0 +OP4 E024C6 0 +OP4 E024C7 0 +OP4 E024C8 0 +OP4 E024C9 0 +OP4 E024CA 0 +OP4 E024CB 0 +OP4 E024CC 0 +OP4 E024CD 0 +OP4 E024CE 0 +OP4 E024CF 0 +OP4 E024D0 0 +OP4 E024D1 0 +OP4 E024D2 0 +OP4 E024D3 0 +OP4 E024D4 0 +OP4 E024D5 0 +OP4 E024D6 0 +OP4 E024D7 0 +OP4 E024D8 0 +OP4 E024D9 0 +OP4 E024DA 0 +OP4 E024DB 0 +OP4 E024DC 0 +OP4 E024DD 0 +OP4 E024DE 0 +OP4 E024DF 0 +OP4 E024E0 0 +OP4 E024E1 0 +OP4 E024E2 0 +OP4 E024E3 0 +OP4 E024E4 0 +OP4 E024E5 0 +OP4 E024E6 0 +OP4 E024E7 0 +OP4 E024E8 0 +OP4 E024E9 0 +OP4 E024EA 0 +OP4 E024EB 0 +OP4 E024EC 0 +OP4 E024ED 0 +OP4 E024EE 0 +OP4 E024EF 0 +OP4 E024F0 0 +OP4 E024F1 0 +OP4 E024F2 0 +OP4 E024F3 0 +OP4 E024F4 0 +OP4 E024F5 0 +OP4 E024F6 0 +OP4 E024F7 0 +OP4 E024F8 0 +OP4 E024F9 0 +OP4 E024FA 0 +OP4 E024FB 0 +OP4 E024FC 0 +OP4 E024FD 0 +OP4 E024FE 0 +OP4 E024FF 0 +OP4 E02500 0 +OP4 E02501 0 +OP4 E02502 0 +OP4 E02503 0 +OP4 E02504 0 +OP4 E02505 0 +OP4 E02506 0 +OP4 E02507 0 +OP4 E02508 0 +OP4 E02509 0 +OP4 E0250A 0 +OP4 E0250B 0 +OP4 E0250C 0 +OP4 E0250D 0 +OP4 E0250E 0 +OP4 E0250F 0 +OP4 E02510 0 +OP4 E02511 0 +OP4 E02512 0 +OP4 E02513 0 +OP4 E02514 0 +OP4 E02515 0 +OP4 E02516 0 +OP4 E02517 0 +OP4 E02518 0 +OP4 E02519 0 +OP4 E0251A 0 +OP4 E0251B 0 +OP4 E0251C 0 +OP4 E0251D 0 +OP4 E0251E 0 +OP4 E0251F 0 +OP4 E02520 0 +OP4 E02521 0 +OP4 E02522 0 +OP4 E02523 0 +OP4 E02524 0 +OP4 E02525 0 +OP4 E02526 0 +OP4 E02527 0 +OP4 E02528 0 +OP4 E02529 0 +OP4 E0252A 0 +OP4 E0252B 0 +OP4 E0252C 0 +OP4 E0252D 0 +OP4 E0252E 0 +OP4 E0252F 0 +OP4 E02530 0 +OP4 E02531 0 +OP4 E02532 0 +OP4 E02533 0 +OP4 E02534 0 +OP4 E02535 0 +OP4 E02536 0 +OP4 E02537 0 +OP4 E02538 0 +OP4 E02539 0 +OP4 E0253A 0 +OP4 E0253B 0 +OP4 E0253C 0 +OP4 E0253D 0 +OP4 E0253E 0 +OP4 E0253F 0 +OP4 E02540 0 +OP4 E02541 0 +OP4 E02542 0 +OP4 E02543 0 +OP4 E02544 0 +OP4 E02545 0 +OP4 E02546 0 +OP4 E02547 0 +OP4 E02548 0 +OP4 E02549 0 +OP4 E0254A 0 +OP4 E0254B 0 +OP4 E0254C 0 +OP4 E0254D 0 +OP4 E0254E 0 +OP4 E0254F 0 +OP4 E02550 0 +OP4 E02551 0 +OP4 E02552 0 +OP4 E02553 0 +OP4 E02554 0 +OP4 E02555 0 +OP4 E02556 0 +OP4 E02557 0 +OP4 E02558 0 +OP4 E02559 0 +OP4 E0255A 0 +OP4 E0255B 0 +OP4 E0255C 0 +OP4 E0255D 0 +OP4 E0255E 0 +OP4 E0255F 0 +OP4 E02560 0 +OP4 E02561 0 +OP4 E02562 0 +OP4 E02563 0 +OP4 E02564 0 +OP4 E02565 0 +OP4 E02566 0 +OP4 E02567 0 +OP4 E02568 0 +OP4 E02569 0 +OP4 E0256A 0 +OP4 E0256B 0 +OP4 E0256C 0 +OP4 E0256D 0 +OP4 E0256E 0 +OP4 E0256F 0 +OP4 E02570 0 +OP4 E02571 0 +OP4 E02572 0 +OP4 E02573 0 +OP4 E02574 0 +OP4 E02575 0 +OP4 E02576 0 +OP4 E02577 0 +OP4 E02578 0 +OP4 E02579 0 +OP4 E0257A 0 +OP4 E0257B 0 +OP4 E0257C 0 +OP4 E0257D 0 +OP4 E0257E 0 +OP4 E0257F 0 +OP4 E02580 0 +OP4 E02581 0 +OP4 E02582 0 +OP4 E02583 0 +OP4 E02584 0 +OP4 E02585 0 +OP4 E02586 0 +OP4 E02587 0 +OP4 E02588 0 +OP4 E02589 0 +OP4 E0258A 0 +OP4 E0258B 0 +OP4 E0258C 0 +OP4 E0258D 0 +OP4 E0258E 0 +OP4 E0258F 0 +OP4 E02590 0 +OP4 E02591 0 +OP4 E02592 0 +OP4 E02593 0 +OP4 E02594 0 +OP4 E02595 0 +OP4 E02596 0 +OP4 E02597 0 +OP4 E02598 0 +OP4 E02599 0 +OP4 E0259A 0 +OP4 E0259B 0 +OP4 E0259C 0 +OP4 E0259D 0 +OP4 E0259E 0 +OP4 E0259F 0 +OP4 E025A0 0 +OP4 E025A1 0 +OP4 E025A2 0 +OP4 E025A3 0 +OP4 E025A4 0 +OP4 E025A5 0 +OP4 E025A6 0 +OP4 E025A7 0 +OP4 E025A8 0 +OP4 E025A9 0 +OP4 E025AA 0 +OP4 E025AB 0 +OP4 E025AC 0 +OP4 E025AD 0 +OP4 E025AE 0 +OP4 E025AF 0 +OP4 E025B0 0 +OP4 E025B1 0 +OP4 E025B2 0 +OP4 E025B3 0 +OP4 E025B4 0 +OP4 E025B5 0 +OP4 E025B6 0 +OP4 E025B7 0 +OP4 E025B8 0 +OP4 E025B9 0 +OP4 E025BA 0 +OP4 E025BB 0 +OP4 E025BC 0 +OP4 E025BD 0 +OP4 E025BE 0 +OP4 E025BF 0 +OP4 E025C0 0 +OP4 E025C1 0 +OP4 E025C2 0 +OP4 E025C3 0 +OP4 E025C4 0 +OP4 E025C5 0 +OP4 E025C6 0 +OP4 E025C7 0 +OP4 E025C8 0 +OP4 E025C9 0 +OP4 E025CA 0 +OP4 E025CB 0 +OP4 E025CC 0 +OP4 E025CD 0 +OP4 E025CE 0 +OP4 E025CF 0 +OP4 E025D0 0 +OP4 E025D1 0 +OP4 E025D2 0 +OP4 E025D3 0 +OP4 E025D4 0 +OP4 E025D5 0 +OP4 E025D6 0 +OP4 E025D7 0 +OP4 E025D8 0 +OP4 E025D9 0 +OP4 E025DA 0 +OP4 E025DB 0 +OP4 E025DC 0 +OP4 E025DD 0 +OP4 E025DE 0 +OP4 E025DF 0 +OP4 E025E0 0 +OP4 E025E1 0 +OP4 E025E2 0 +OP4 E025E3 0 +OP4 E025E4 0 +OP4 E025E5 0 +OP4 E025E6 0 +OP4 E025E7 0 +OP4 E025E8 0 +OP4 E025E9 0 +OP4 E025EA 0 +OP4 E025EB 0 +OP4 E025EC 0 +OP4 E025ED 0 +OP4 E025EE 0 +OP4 E025EF 0 +OP4 E025F0 0 +OP4 E025F1 0 +OP4 E025F2 0 +OP4 E025F3 0 +OP4 E025F4 0 +OP4 E025F5 0 +OP4 E025F6 0 +OP4 E025F7 0 +OP4 E025F8 0 +OP4 E025F9 0 +OP4 E025FA 0 +OP4 E025FB 0 +OP4 E025FC 0 +OP4 E025FD 0 +OP4 E025FE 0 +OP4 E025FF 0 +OP4 E02600 0 +OP4 E02601 0 +OP4 E02602 0 +OP4 E02603 0 +OP4 E02604 0 +OP4 E02605 0 +OP4 E02606 0 +OP4 E02607 0 +OP4 E02608 0 +OP4 E02609 0 +OP4 E0260A 0 +OP4 E0260B 0 +OP4 E0260C 0 +OP4 E0260D 0 +OP4 E0260E 0 +OP4 E0260F 0 +OP4 E02610 0 +OP4 E02611 0 +OP4 E02612 0 +OP4 E02613 0 +OP4 E02614 0 +OP4 E02615 0 +OP4 E02616 0 +OP4 E02617 0 +OP4 E02618 0 +OP4 E02619 0 +OP4 E0261A 0 +OP4 E0261B 0 +OP4 E0261C 0 +OP4 E0261D 0 +OP4 E0261E 0 +OP4 E0261F 0 +OP4 E02620 0 +OP4 E02621 0 +OP4 E02622 0 +OP4 E02623 0 +OP4 E02624 0 +OP4 E02625 0 +OP4 E02626 0 +OP4 E02627 0 +OP4 E02628 0 +OP4 E02629 0 +OP4 E0262A 0 +OP4 E0262B 0 +OP4 E0262C 0 +OP4 E0262D 0 +OP4 E0262E 0 +OP4 E0262F 0 +OP4 E02630 0 +OP4 E02631 0 +OP4 E02632 0 +OP4 E02633 0 +OP4 E02634 0 +OP4 E02635 0 +OP4 E02636 0 +OP4 E02637 0 +OP4 E02638 0 +OP4 E02639 0 +OP4 E0263A 0 +OP4 E0263B 0 +OP4 E0263C 0 +OP4 E0263D 0 +OP4 E0263E 0 +OP4 E0263F 0 +OP4 E02640 0 +OP4 E02641 0 +OP4 E02642 0 +OP4 E02643 0 +OP4 E02644 0 +OP4 E02645 0 +OP4 E02646 0 +OP4 E02647 0 +OP4 E02648 0 +OP4 E02649 0 +OP4 E0264A 0 +OP4 E0264B 0 +OP4 E0264C 0 +OP4 E0264D 0 +OP4 E0264E 0 +OP4 E0264F 0 +OP4 E02650 0 +OP4 E02651 0 +OP4 E02652 0 +OP4 E02653 0 +OP4 E02654 0 +OP4 E02655 0 +OP4 E02656 0 +OP4 E02657 0 +OP4 E02658 0 +OP4 E02659 0 +OP4 E0265A 0 +OP4 E0265B 0 +OP4 E0265C 0 +OP4 E0265D 0 +OP4 E0265E 0 +OP4 E0265F 0 +OP4 E02660 0 +OP4 E02661 0 +OP4 E02662 0 +OP4 E02663 0 +OP4 E02664 0 +OP4 E02665 0 +OP4 E02666 0 +OP4 E02667 0 +OP4 E02668 0 +OP4 E02669 0 +OP4 E0266A 0 +OP4 E0266B 0 +OP4 E0266C 0 +OP4 E0266D 0 +OP4 E0266E 0 +OP4 E0266F 0 +OP4 E02670 0 +OP4 E02671 0 +OP4 E02672 0 +OP4 E02673 0 +OP4 E02674 0 +OP4 E02675 0 +OP4 E02676 0 +OP4 E02677 0 +OP4 E02678 0 +OP4 E02679 0 +OP4 E0267A 0 +OP4 E0267B 0 +OP4 E0267C 0 +OP4 E0267D 0 +OP4 E0267E 0 +OP4 E0267F 0 +OP4 E02680 0 +OP4 E02681 0 +OP4 E02682 0 +OP4 E02683 0 +OP4 E02684 0 +OP4 E02685 0 +OP4 E02686 0 +OP4 E02687 0 +OP4 E02688 0 +OP4 E02689 0 +OP4 E0268A 0 +OP4 E0268B 0 +OP4 E0268C 0 +OP4 E0268D 0 +OP4 E0268E 0 +OP4 E0268F 0 +OP4 E02690 0 +OP4 E02691 0 +OP4 E02692 0 +OP4 E02693 0 +OP4 E02694 0 +OP4 E02695 0 +OP4 E02696 0 +OP4 E02697 0 +OP4 E02698 0 +OP4 E02699 0 +OP4 E0269A 0 +OP4 E0269B 0 +OP4 E0269C 0 +OP4 E0269D 0 +OP4 E0269E 0 +OP4 E0269F 0 +OP4 E026A0 0 +OP4 E026A1 0 +OP4 E026A2 0 +OP4 E026A3 0 +OP4 E026A4 0 +OP4 E026A5 0 +OP4 E026A6 0 +OP4 E026A7 0 +OP4 E026A8 0 +OP4 E026A9 0 +OP4 E026AA 0 +OP4 E026AB 0 +OP4 E026AC 0 +OP4 E026AD 0 +OP4 E026AE 0 +OP4 E026AF 0 +OP4 E026B0 0 +OP4 E026B1 0 +OP4 E026B2 0 +OP4 E026B3 0 +OP4 E026B4 0 +OP4 E026B5 0 +OP4 E026B6 0 +OP4 E026B7 0 +OP4 E026B8 0 +OP4 E026B9 0 +OP4 E026BA 0 +OP4 E026BB 0 +OP4 E026BC 0 +OP4 E026BD 0 +OP4 E026BE 0 +OP4 E026BF 0 +OP4 E026C0 0 +OP4 E026C1 0 +OP4 E026C2 0 +OP4 E026C3 0 +OP4 E026C4 0 +OP4 E026C5 0 +OP4 E026C6 0 +OP4 E026C7 0 +OP4 E026C8 0 +OP4 E026C9 0 +OP4 E026CA 0 +OP4 E026CB 0 +OP4 E026CC 0 +OP4 E026CD 0 +OP4 E026CE 0 +OP4 E026CF 0 +OP4 E026D0 0 +OP4 E026D1 0 +OP4 E026D2 0 +OP4 E026D3 0 +OP4 E026D4 0 +OP4 E026D5 0 +OP4 E026D6 0 +OP4 E026D7 0 +OP4 E026D8 0 +OP4 E026D9 0 +OP4 E026DA 0 +OP4 E026DB 0 +OP4 E026DC 0 +OP4 E026DD 0 +OP4 E026DE 0 +OP4 E026DF 0 +OP4 E026E0 0 +OP4 E026E1 0 +OP4 E026E2 0 +OP4 E026E3 0 +OP4 E026E4 0 +OP4 E026E5 0 +OP4 E026E6 0 +OP4 E026E7 0 +OP4 E026E8 0 +OP4 E026E9 0 +OP4 E026EA 0 +OP4 E026EB 0 +OP4 E026EC 0 +OP4 E026ED 0 +OP4 E026EE 0 +OP4 E026EF 0 +OP4 E026F0 0 +OP4 E026F1 0 +OP4 E026F2 0 +OP4 E026F3 0 +OP4 E026F4 0 +OP4 E026F5 0 +OP4 E026F6 0 +OP4 E026F7 0 +OP4 E026F8 0 +OP4 E026F9 0 +OP4 E026FA 0 +OP4 E026FB 0 +OP4 E026FC 0 +OP4 E026FD 0 +OP4 E026FE 0 +OP4 E026FF 0 +OP4 E02700 0 +OP4 E02701 0 +OP4 E02702 0 +OP4 E02703 0 +OP4 E02704 0 +OP4 E02705 0 +OP4 E02706 0 +OP4 E02707 0 +OP4 E02708 0 +OP4 E02709 0 +OP4 E0270A 0 +OP4 E0270B 0 +OP4 E0270C 0 +OP4 E0270D 0 +OP4 E0270E 0 +OP4 E0270F 0 +OP4 E02710 0 +OP4 E02711 0 +OP4 E02712 0 +OP4 E02713 0 +OP4 E02714 0 +OP4 E02715 0 +OP4 E02716 0 +OP4 E02717 0 +OP4 E02718 0 +OP4 E02719 0 +OP4 E0271A 0 +OP4 E0271B 0 +OP4 E0271C 0 +OP4 E0271D 0 +OP4 E0271E 0 +OP4 E0271F 0 +OP4 E02720 0 +OP4 E02721 0 +OP4 E02722 0 +OP4 E02723 0 +OP4 E02724 0 +OP4 E02725 0 +OP4 E02726 0 +OP4 E02727 0 +OP4 E02728 0 +OP4 E02729 0 +OP4 E0272A 0 +OP4 E0272B 0 +OP4 E0272C 0 +OP4 E0272D 0 +OP4 E0272E 0 +OP4 E0272F 0 +OP4 E02730 0 +OP4 E02731 0 +OP4 E02732 0 +OP4 E02733 0 +OP4 E02734 0 +OP4 E02735 0 +OP4 E02736 0 +OP4 E02737 0 +OP4 E02738 0 +OP4 E02739 0 +OP4 E0273A 0 +OP4 E0273B 0 +OP4 E0273C 0 +OP4 E0273D 0 +OP4 E0273E 0 +OP4 E0273F 0 +OP4 E02740 0 +OP4 E02741 0 +OP4 E02742 0 +OP4 E02743 0 +OP4 E02744 0 +OP4 E02745 0 +OP4 E02746 0 +OP4 E02747 0 +OP4 E02748 0 +OP4 E02749 0 +OP4 E0274A 0 +OP4 E0274B 0 +OP4 E0274C 0 +OP4 E0274D 0 +OP4 E0274E 0 +OP4 E0274F 0 +OP4 E02750 0 +OP4 E02751 0 +OP4 E02752 0 +OP4 E02753 0 +OP4 E02754 0 +OP4 E02755 0 +OP4 E02756 0 +OP4 E02757 0 +OP4 E02758 0 +OP4 E02759 0 +OP4 E0275A 0 +OP4 E0275B 0 +OP4 E0275C 0 +OP4 E0275D 0 +OP4 E0275E 0 +OP4 E0275F 0 +OP4 E02760 0 +OP4 E02761 0 +OP4 E02762 0 +OP4 E02763 0 +OP4 E02764 0 +OP4 E02765 0 +OP4 E02766 0 +OP4 E02767 0 +OP4 E02768 0 +OP4 E02769 0 +OP4 E0276A 0 +OP4 E0276B 0 +OP4 E0276C 0 +OP4 E0276D 0 +OP4 E0276E 0 +OP4 E0276F 0 +OP4 E02770 0 +OP4 E02771 0 +OP4 E02772 0 +OP4 E02773 0 +OP4 E02774 0 +OP4 E02775 0 +OP4 E02776 0 +OP4 E02777 0 +OP4 E02778 0 +OP4 E02779 0 +OP4 E0277A 0 +OP4 E0277B 0 +OP4 E0277C 0 +OP4 E0277D 0 +OP4 E0277E 0 +OP4 E0277F 0 +OP4 E02780 0 +OP4 E02781 0 +OP4 E02782 0 +OP4 E02783 0 +OP4 E02784 0 +OP4 E02785 0 +OP4 E02786 0 +OP4 E02787 0 +OP4 E02788 0 +OP4 E02789 0 +OP4 E0278A 0 +OP4 E0278B 0 +OP4 E0278C 0 +OP4 E0278D 0 +OP4 E0278E 0 +OP4 E0278F 0 +OP4 E02790 0 +OP4 E02791 0 +OP4 E02792 0 +OP4 E02793 0 +OP4 E02794 0 +OP4 E02795 0 +OP4 E02796 0 +OP4 E02797 0 +OP4 E02798 0 +OP4 E02799 0 +OP4 E0279A 0 +OP4 E0279B 0 +OP4 E0279C 0 +OP4 E0279D 0 +OP4 E0279E 0 +OP4 E0279F 0 +OP4 E027A0 0 +OP4 E027A1 0 +OP4 E027A2 0 +OP4 E027A3 0 +OP4 E027A4 0 +OP4 E027A5 0 +OP4 E027A6 0 +OP4 E027A7 0 +OP4 E027A8 0 +OP4 E027A9 0 +OP4 E027AA 0 +OP4 E027AB 0 +OP4 E027AC 0 +OP4 E027AD 0 +OP4 E027AE 0 +OP4 E027AF 0 +OP4 E027B0 0 +OP4 E027B1 0 +OP4 E027B2 0 +OP4 E027B3 0 +OP4 E027B4 0 +OP4 E027B5 0 +OP4 E027B6 0 +OP4 E027B7 0 +OP4 E027B8 0 +OP4 E027B9 0 +OP4 E027BA 0 +OP4 E027BB 0 +OP4 E027BC 0 +OP4 E027BD 0 +OP4 E027BE 0 +OP4 E027BF 0 +OP4 E027C0 0 +OP4 E027C1 0 +OP4 E027C2 0 +OP4 E027C3 0 +OP4 E027C4 0 +OP4 E027C5 0 +OP4 E027C6 0 +OP4 E027C7 0 +OP4 E027C8 0 +OP4 E027C9 0 +OP4 E027CA 0 +OP4 E027CB 0 +OP4 E027CC 0 +OP4 E027CD 0 +OP4 E027CE 0 +OP4 E027CF 0 +OP4 E027D0 0 +OP4 E027D1 0 +OP4 E027D2 0 +OP4 E027D3 0 +OP4 E027D4 0 +OP4 E027D5 0 +OP4 E027D6 0 +OP4 E027D7 0 +OP4 E027D8 0 +OP4 E027D9 0 +OP4 E027DA 0 +OP4 E027DB 0 +OP4 E027DC 0 +OP4 E027DD 0 +OP4 E027DE 0 +OP4 E027DF 0 +OP4 E027E0 0 +OP4 E027E1 0 +OP4 E027E2 0 +OP4 E027E3 0 +OP4 E027E4 0 +OP4 E027E5 0 +OP4 E027E6 0 +OP4 E027E7 0 +OP4 E027E8 0 +OP4 E027E9 0 +OP4 E027EA 0 +OP4 E027EB 0 +OP4 E027EC 0 +OP4 E027ED 0 +OP4 E027EE 0 +OP4 E027EF 0 +OP4 E027F0 0 +OP4 E027F1 0 +OP4 E027F2 0 +OP4 E027F3 0 +OP4 E027F4 0 +OP4 E027F5 0 +OP4 E027F6 0 +OP4 E027F7 0 +OP4 E027F8 0 +OP4 E027F9 0 +OP4 E027FA 0 +OP4 E027FB 0 +OP4 E027FC 0 +OP4 E027FD 0 +OP4 E027FE 0 +OP4 E027FF 0 +OP4 E02800 0 +OP4 E02801 0 +OP4 E02802 0 +OP4 E02803 0 +OP4 E02804 0 +OP4 E02805 0 +OP4 E02806 0 +OP4 E02807 0 +OP4 E02808 0 +OP4 E02809 0 +OP4 E0280A 0 +OP4 E0280B 0 +OP4 E0280C 0 +OP4 E0280D 0 +OP4 E0280E 0 +OP4 E0280F 0 +OP4 E02810 0 +OP4 E02811 0 +OP4 E02812 0 +OP4 E02813 0 +OP4 E02814 0 +OP4 E02815 0 +OP4 E02816 0 +OP4 E02817 0 +OP4 E02818 0 +OP4 E02819 0 +OP4 E0281A 0 +OP4 E0281B 0 +OP4 E0281C 0 +OP4 E0281D 0 +OP4 E0281E 0 +OP4 E0281F 0 +OP4 E02820 0 +OP4 E02821 0 +OP4 E02822 0 +OP4 E02823 0 +OP4 E02824 0 +OP4 E02825 0 +OP4 E02826 0 +OP4 E02827 0 +OP4 E02828 0 +OP4 E02829 0 +OP4 E0282A 0 +OP4 E0282B 0 +OP4 E0282C 0 +OP4 E0282D 0 +OP4 E0282E 0 +OP4 E0282F 0 +OP4 E02830 0 +OP4 E02831 0 +OP4 E02832 0 +OP4 E02833 0 +OP4 E02834 0 +OP4 E02835 0 +OP4 E02836 0 +OP4 E02837 0 +OP4 E02838 0 +OP4 E02839 0 +OP4 E0283A 0 +OP4 E0283B 0 +OP4 E0283C 0 +OP4 E0283D 0 +OP4 E0283E 0 +OP4 E0283F 0 +OP4 E02840 0 +OP4 E02841 0 +OP4 E02842 0 +OP4 E02843 0 +OP4 E02844 0 +OP4 E02845 0 +OP4 E02846 0 +OP4 E02847 0 +OP4 E02848 0 +OP4 E02849 0 +OP4 E0284A 0 +OP4 E0284B 0 +OP4 E0284C 0 +OP4 E0284D 0 +OP4 E0284E 0 +OP4 E0284F 0 +OP4 E02850 0 +OP4 E02851 0 +OP4 E02852 0 +OP4 E02853 0 +OP4 E02854 0 +OP4 E02855 0 +OP4 E02856 0 +OP4 E02857 0 +OP4 E02858 0 +OP4 E02859 0 +OP4 E0285A 0 +OP4 E0285B 0 +OP4 E0285C 0 +OP4 E0285D 0 +OP4 E0285E 0 +OP4 E0285F 0 +OP4 E02860 0 +OP4 E02861 0 +OP4 E02862 0 +OP4 E02863 0 +OP4 E02864 0 +OP4 E02865 0 +OP4 E02866 0 +OP4 E02867 0 +OP4 E02868 0 +OP4 E02869 0 +OP4 E0286A 0 +OP4 E0286B 0 +OP4 E0286C 0 +OP4 E0286D 0 +OP4 E0286E 0 +OP4 E0286F 0 +OP4 E02870 0 +OP4 E02871 0 +OP4 E02872 0 +OP4 E02873 0 +OP4 E02874 0 +OP4 E02875 0 +OP4 E02876 0 +OP4 E02877 0 +OP4 E02878 0 +OP4 E02879 0 +OP4 E0287A 0 +OP4 E0287B 0 +OP4 E0287C 0 +OP4 E0287D 0 +OP4 E0287E 0 +OP4 E0287F 0 +OP4 E02880 0 +OP4 E02881 0 +OP4 E02882 0 +OP4 E02883 0 +OP4 E02884 0 +OP4 E02885 0 +OP4 E02886 0 +OP4 E02887 0 +OP4 E02888 0 +OP4 E02889 0 +OP4 E0288A 0 +OP4 E0288B 0 +OP4 E0288C 0 +OP4 E0288D 0 +OP4 E0288E 0 +OP4 E0288F 0 +OP4 E02890 0 +OP4 E02891 0 +OP4 E02892 0 +OP4 E02893 0 +OP4 E02894 0 +OP4 E02895 0 +OP4 E02896 0 +OP4 E02897 0 +OP4 E02898 0 +OP4 E02899 0 +OP4 E0289A 0 +OP4 E0289B 0 +OP4 E0289C 0 +OP4 E0289D 0 +OP4 E0289E 0 +OP4 E0289F 0 +OP4 E028A0 0 +OP4 E028A1 0 +OP4 E028A2 0 +OP4 E028A3 0 +OP4 E028A4 0 +OP4 E028A5 0 +OP4 E028A6 0 +OP4 E028A7 0 +OP4 E028A8 0 +OP4 E028A9 0 +OP4 E028AA 0 +OP4 E028AB 0 +OP4 E028AC 0 +OP4 E028AD 0 +OP4 E028AE 0 +OP4 E028AF 0 +OP4 E028B0 0 +OP4 E028B1 0 +OP4 E028B2 0 +OP4 E028B3 0 +OP4 E028B4 0 +OP4 E028B5 0 +OP4 E028B6 0 +OP4 E028B7 0 +OP4 E028B8 0 +OP4 E028B9 0 +OP4 E028BA 0 +OP4 E028BB 0 +OP4 E028BC 0 +OP4 E028BD 0 +OP4 E028BE 0 +OP4 E028BF 0 +OP4 E028C0 0 +OP4 E028C1 0 +OP4 E028C2 0 +OP4 E028C3 0 +OP4 E028C4 0 +OP4 E028C5 0 +OP4 E028C6 0 +OP4 E028C7 0 +OP4 E028C8 0 +OP4 E028C9 0 +OP4 E028CA 0 +OP4 E028CB 0 +OP4 E028CC 0 +OP4 E028CD 0 +OP4 E028CE 0 +OP4 E028CF 0 +OP4 E028D0 0 +OP4 E028D1 0 +OP4 E028D2 0 +OP4 E028D3 0 +OP4 E028D4 0 +OP4 E028D5 0 +OP4 E028D6 0 +OP4 E028D7 0 +OP4 E028D8 0 +OP4 E028D9 0 +OP4 E028DA 0 +OP4 E028DB 0 +OP4 E028DC 0 +OP4 E028DD 0 +OP4 E028DE 0 +OP4 E028DF 0 +OP4 E028E0 0 +OP4 E028E1 0 +OP4 E028E2 0 +OP4 E028E3 0 +OP4 E028E4 0 +OP4 E028E5 0 +OP4 E028E6 0 +OP4 E028E7 0 +OP4 E028E8 0 +OP4 E028E9 0 +OP4 E028EA 0 +OP4 E028EB 0 +OP4 E028EC 0 +OP4 E028ED 0 +OP4 E028EE 0 +OP4 E028EF 0 +OP4 E028F0 0 +OP4 E028F1 0 +OP4 E028F2 0 +OP4 E028F3 0 +OP4 E028F4 0 +OP4 E028F5 0 +OP4 E028F6 0 +OP4 E028F7 0 +OP4 E028F8 0 +OP4 E028F9 0 +OP4 E028FA 0 +OP4 E028FB 0 +OP4 E028FC 0 +OP4 E028FD 0 +OP4 E028FE 0 +OP4 E028FF 0 +OP4 E02900 0 +OP4 E02901 0 +OP4 E02902 0 +OP4 E02903 0 +OP4 E02904 0 +OP4 E02905 0 +OP4 E02906 0 +OP4 E02907 0 +OP4 E02908 0 +OP4 E02909 0 +OP4 E0290A 0 +OP4 E0290B 0 +OP4 E0290C 0 +OP4 E0290D 0 +OP4 E0290E 0 +OP4 E0290F 0 +OP4 E02910 0 +OP4 E02911 0 +OP4 E02912 0 +OP4 E02913 0 +OP4 E02914 0 +OP4 E02915 0 +OP4 E02916 0 +OP4 E02917 0 +OP4 E02918 0 +OP4 E02919 0 +OP4 E0291A 0 +OP4 E0291B 0 +OP4 E0291C 0 +OP4 E0291D 0 +OP4 E0291E 0 +OP4 E0291F 0 +OP4 E02920 0 +OP4 E02921 0 +OP4 E02922 0 +OP4 E02923 0 +OP4 E02924 0 +OP4 E02925 0 +OP4 E02926 0 +OP4 E02927 0 +OP4 E02928 0 +OP4 E02929 0 +OP4 E0292A 0 +OP4 E0292B 0 +OP4 E0292C 0 +OP4 E0292D 0 +OP4 E0292E 0 +OP4 E0292F 0 +OP4 E02930 0 +OP4 E02931 0 +OP4 E02932 0 +OP4 E02933 0 +OP4 E02934 0 +OP4 E02935 0 +OP4 E02936 0 +OP4 E02937 0 +OP4 E02938 0 +OP4 E02939 0 +OP4 E0293A 0 +OP4 E0293B 0 +OP4 E0293C 0 +OP4 E0293D 0 +OP4 E0293E 0 +OP4 E0293F 0 +OP4 E02940 0 +OP4 E02941 0 +OP4 E02942 0 +OP4 E02943 0 +OP4 E02944 0 +OP4 E02945 0 +OP4 E02946 0 +OP4 E02947 0 +OP4 E02948 0 +OP4 E02949 0 +OP4 E0294A 0 +OP4 E0294B 0 +OP4 E0294C 0 +OP4 E0294D 0 +OP4 E0294E 0 +OP4 E0294F 0 +OP4 E02950 0 +OP4 E02951 0 +OP4 E02952 0 +OP4 E02953 0 +OP4 E02954 0 +OP4 E02955 0 +OP4 E02956 0 +OP4 E02957 0 +OP4 E02958 0 +OP4 E02959 0 +OP4 E0295A 0 +OP4 E0295B 0 +OP4 E0295C 0 +OP4 E0295D 0 +OP4 E0295E 0 +OP4 E0295F 0 +OP4 E02960 0 +OP4 E02961 0 +OP4 E02962 0 +OP4 E02963 0 +OP4 E02964 0 +OP4 E02965 0 +OP4 E02966 0 +OP4 E02967 0 +OP4 E02968 0 +OP4 E02969 0 +OP4 E0296A 0 +OP4 E0296B 0 +OP4 E0296C 0 +OP4 E0296D 0 +OP4 E0296E 0 +OP4 E0296F 0 +OP4 E02970 0 +OP4 E02971 0 +OP4 E02972 0 +OP4 E02973 0 +OP4 E02974 0 +OP4 E02975 0 +OP4 E02976 0 +OP4 E02977 0 +OP4 E02978 0 +OP4 E02979 0 +OP4 E0297A 0 +OP4 E0297B 0 +OP4 E0297C 0 +OP4 E0297D 0 +OP4 E0297E 0 +OP4 E0297F 0 +OP4 E02980 0 +OP4 E02981 0 +OP4 E02982 0 +OP4 E02983 0 +OP4 E02984 0 +OP4 E02985 0 +OP4 E02986 0 +OP4 E02987 0 +OP4 E02988 0 +OP4 E02989 0 +OP4 E0298A 0 +OP4 E0298B 0 +OP4 E0298C 0 +OP4 E0298D 0 +OP4 E0298E 0 +OP4 E0298F 0 +OP4 E02990 0 +OP4 E02991 0 +OP4 E02992 0 +OP4 E02993 0 +OP4 E02994 0 +OP4 E02995 0 +OP4 E02996 0 +OP4 E02997 0 +OP4 E02998 0 +OP4 E02999 0 +OP4 E0299A 0 +OP4 E0299B 0 +OP4 E0299C 0 +OP4 E0299D 0 +OP4 E0299E 0 +OP4 E0299F 0 +OP4 E029A0 0 +OP4 E029A1 0 +OP4 E029A2 0 +OP4 E029A3 0 +OP4 E029A4 0 +OP4 E029A5 0 +OP4 E029A6 0 +OP4 E029A7 0 +OP4 E029A8 0 +OP4 E029A9 0 +OP4 E029AA 0 +OP4 E029AB 0 +OP4 E029AC 0 +OP4 E029AD 0 +OP4 E029AE 0 +OP4 E029AF 0 +OP4 E029B0 0 +OP4 E029B1 0 +OP4 E029B2 0 +OP4 E029B3 0 +OP4 E029B4 0 +OP4 E029B5 0 +OP4 E029B6 0 +OP4 E029B7 0 +OP4 E029B8 0 +OP4 E029B9 0 +OP4 E029BA 0 +OP4 E029BB 0 +OP4 E029BC 0 +OP4 E029BD 0 +OP4 E029BE 0 +OP4 E029BF 0 +OP4 E029C0 0 +OP4 E029C1 0 +OP4 E029C2 0 +OP4 E029C3 0 +OP4 E029C4 0 +OP4 E029C5 0 +OP4 E029C6 0 +OP4 E029C7 0 +OP4 E029C8 0 +OP4 E029C9 0 +OP4 E029CA 0 +OP4 E029CB 0 +OP4 E029CC 0 +OP4 E029CD 0 +OP4 E029CE 0 +OP4 E029CF 0 +OP4 E029D0 0 +OP4 E029D1 0 +OP4 E029D2 0 +OP4 E029D3 0 +OP4 E029D4 0 +OP4 E029D5 0 +OP4 E029D6 0 +OP4 E029D7 0 +OP4 E029D8 0 +OP4 E029D9 0 +OP4 E029DA 0 +OP4 E029DB 0 +OP4 E029DC 0 +OP4 E029DD 0 +OP4 E029DE 0 +OP4 E029DF 0 +OP4 E029E0 0 +OP4 E029E1 0 +OP4 E029E2 0 +OP4 E029E3 0 +OP4 E029E4 0 +OP4 E029E5 0 +OP4 E029E6 0 +OP4 E029E7 0 +OP4 E029E8 0 +OP4 E029E9 0 +OP4 E029EA 0 +OP4 E029EB 0 +OP4 E029EC 0 +OP4 E029ED 0 +OP4 E029EE 0 +OP4 E029EF 0 +OP4 E029F0 0 +OP4 E029F1 0 +OP4 E029F2 0 +OP4 E029F3 0 +OP4 E029F4 0 +OP4 E029F5 0 +OP4 E029F6 0 +OP4 E029F7 0 +OP4 E029F8 0 +OP4 E029F9 0 +OP4 E029FA 0 +OP4 E029FB 0 +OP4 E029FC 0 +OP4 E029FD 0 +OP4 E029FE 0 +OP4 E029FF 0 +OP4 E02A00 0 +OP4 E02A01 0 +OP4 E02A02 0 +OP4 E02A03 0 +OP4 E02A04 0 +OP4 E02A05 0 +OP4 E02A06 0 +OP4 E02A07 0 +OP4 E02A08 0 +OP4 E02A09 0 +OP4 E02A0A 0 +OP4 E02A0B 0 +OP4 E02A0C 0 +OP4 E02A0D 0 +OP4 E02A0E 0 +OP4 E02A0F 0 +OP4 E02A10 0 +OP4 E02A11 0 +OP4 E02A12 0 +OP4 E02A13 0 +OP4 E02A14 0 +OP4 E02A15 0 +OP4 E02A16 0 +OP4 E02A17 0 +OP4 E02A18 0 +OP4 E02A19 0 +OP4 E02A1A 0 +OP4 E02A1B 0 +OP4 E02A1C 0 +OP4 E02A1D 0 +OP4 E02A1E 0 +OP4 E02A1F 0 +OP4 E02A20 0 +OP4 E02A21 0 +OP4 E02A22 0 +OP4 E02A23 0 +OP4 E02A24 0 +OP4 E02A25 0 +OP4 E02A26 0 +OP4 E02A27 0 +OP4 E02A28 0 +OP4 E02A29 0 +OP4 E02A2A 0 +OP4 E02A2B 0 +OP4 E02A2C 0 +OP4 E02A2D 0 +OP4 E02A2E 0 +OP4 E02A2F 0 +OP4 E02A30 0 +OP4 E02A31 0 +OP4 E02A32 0 +OP4 E02A33 0 +OP4 E02A34 0 +OP4 E02A35 0 +OP4 E02A36 0 +OP4 E02A37 0 +OP4 E02A38 0 +OP4 E02A39 0 +OP4 E02A3A 0 +OP4 E02A3B 0 +OP4 E02A3C 0 +OP4 E02A3D 0 +OP4 E02A3E 0 +OP4 E02A3F 0 +OP4 E02A40 0 +OP4 E02A41 0 +OP4 E02A42 0 +OP4 E02A43 0 +OP4 E02A44 0 +OP4 E02A45 0 +OP4 E02A46 0 +OP4 E02A47 0 +OP4 E02A48 0 +OP4 E02A49 0 +OP4 E02A4A 0 +OP4 E02A4B 0 +OP4 E02A4C 0 +OP4 E02A4D 0 +OP4 E02A4E 0 +OP4 E02A4F 0 +OP4 E02A50 0 +OP4 E02A51 0 +OP4 E02A52 0 +OP4 E02A53 0 +OP4 E02A54 0 +OP4 E02A55 0 +OP4 E02A56 0 +OP4 E02A57 0 +OP4 E02A58 0 +OP4 E02A59 0 +OP4 E02A5A 0 +OP4 E02A5B 0 +OP4 E02A5C 0 +OP4 E02A5D 0 +OP4 E02A5E 0 +OP4 E02A5F 0 +OP4 E02A60 0 +OP4 E02A61 0 +OP4 E02A62 0 +OP4 E02A63 0 +OP4 E02A64 0 +OP4 E02A65 0 +OP4 E02A66 0 +OP4 E02A67 0 +OP4 E02A68 0 +OP4 E02A69 0 +OP4 E02A6A 0 +OP4 E02A6B 0 +OP4 E02A6C 0 +OP4 E02A6D 0 +OP4 E02A6E 0 +OP4 E02A6F 0 +OP4 E02A70 0 +OP4 E02A71 0 +OP4 E02A72 0 +OP4 E02A73 0 +OP4 E02A74 0 +OP4 E02A75 0 +OP4 E02A76 0 +OP4 E02A77 0 +OP4 E02A78 0 +OP4 E02A79 0 +OP4 E02A7A 0 +OP4 E02A7B 0 +OP4 E02A7C 0 +OP4 E02A7D 0 +OP4 E02A7E 0 +OP4 E02A7F 0 +OP4 E02A80 0 +OP4 E02A81 0 +OP4 E02A82 0 +OP4 E02A83 0 +OP4 E02A84 0 +OP4 E02A85 0 +OP4 E02A86 0 +OP4 E02A87 0 +OP4 E02A88 0 +OP4 E02A89 0 +OP4 E02A8A 0 +OP4 E02A8B 0 +OP4 E02A8C 0 +OP4 E02A8D 0 +OP4 E02A8E 0 +OP4 E02A8F 0 +OP4 E02A90 0 +OP4 E02A91 0 +OP4 E02A92 0 +OP4 E02A93 0 +OP4 E02A94 0 +OP4 E02A95 0 +OP4 E02A96 0 +OP4 E02A97 0 +OP4 E02A98 0 +OP4 E02A99 0 +OP4 E02A9A 0 +OP4 E02A9B 0 +OP4 E02A9C 0 +OP4 E02A9D 0 +OP4 E02A9E 0 +OP4 E02A9F 0 +OP4 E02AA0 0 +OP4 E02AA1 0 +OP4 E02AA2 0 +OP4 E02AA3 0 +OP4 E02AA4 0 +OP4 E02AA5 0 +OP4 E02AA6 0 +OP4 E02AA7 0 +OP4 E02AA8 0 +OP4 E02AA9 0 +OP4 E02AAA 0 +OP4 E02AAB 0 +OP4 E02AAC 0 +OP4 E02AAD 0 +OP4 E02AAE 0 +OP4 E02AAF 0 +OP4 E02AB0 0 +OP4 E02AB1 0 +OP4 E02AB2 0 +OP4 E02AB3 0 +OP4 E02AB4 0 +OP4 E02AB5 0 +OP4 E02AB6 0 +OP4 E02AB7 0 +OP4 E02AB8 0 +OP4 E02AB9 0 +OP4 E02ABA 0 +OP4 E02ABB 0 +OP4 E02ABC 0 +OP4 E02ABD 0 +OP4 E02ABE 0 +OP4 E02ABF 0 +OP4 E02AC0 0 +OP4 E02AC1 0 +OP4 E02AC2 0 +OP4 E02AC3 0 +OP4 E02AC4 0 +OP4 E02AC5 0 +OP4 E02AC6 0 +OP4 E02AC7 0 +OP4 E02AC8 0 +OP4 E02AC9 0 +OP4 E02ACA 0 +OP4 E02ACB 0 +OP4 E02ACC 0 +OP4 E02ACD 0 +OP4 E02ACE 0 +OP4 E02ACF 0 +OP4 E02AD0 0 +OP4 E02AD1 0 +OP4 E02AD2 0 +OP4 E02AD3 0 +OP4 E02AD4 0 +OP4 E02AD5 0 +OP4 E02AD6 0 +OP4 E02AD7 0 +OP4 E02AD8 0 +OP4 E02AD9 0 +OP4 E02ADA 0 +OP4 E02ADB 0 +OP4 E02ADC 0 +OP4 E02ADD 0 +OP4 E02ADE 0 +OP4 E02ADF 0 +OP4 E02AE0 0 +OP4 E02AE1 0 +OP4 E02AE2 0 +OP4 E02AE3 0 +OP4 E02AE4 0 +OP4 E02AE5 0 +OP4 E02AE6 0 +OP4 E02AE7 0 +OP4 E02AE8 0 +OP4 E02AE9 0 +OP4 E02AEA 0 +OP4 E02AEB 0 +OP4 E02AEC 0 +OP4 E02AED 0 +OP4 E02AEE 0 +OP4 E02AEF 0 +OP4 E02AF0 0 +OP4 E02AF1 0 +OP4 E02AF2 0 +OP4 E02AF3 0 +OP4 E02AF4 0 +OP4 E02AF5 0 +OP4 E02AF6 0 +OP4 E02AF7 0 +OP4 E02AF8 0 +OP4 E02AF9 0 +OP4 E02AFA 0 +OP4 E02AFB 0 +OP4 E02AFC 0 +OP4 E02AFD 0 +OP4 E02AFE 0 +OP4 E02AFF 0 +OP4 E02B00 0 +OP4 E02B01 0 +OP4 E02B02 0 +OP4 E02B03 0 +OP4 E02B04 0 +OP4 E02B05 0 +OP4 E02B06 0 +OP4 E02B07 0 +OP4 E02B08 0 +OP4 E02B09 0 +OP4 E02B0A 0 +OP4 E02B0B 0 +OP4 E02B0C 0 +OP4 E02B0D 0 +OP4 E02B0E 0 +OP4 E02B0F 0 +OP4 E02B10 0 +OP4 E02B11 0 +OP4 E02B12 0 +OP4 E02B13 0 +OP4 E02B14 0 +OP4 E02B15 0 +OP4 E02B16 0 +OP4 E02B17 0 +OP4 E02B18 0 +OP4 E02B19 0 +OP4 E02B1A 0 +OP4 E02B1B 0 +OP4 E02B1C 0 +OP4 E02B1D 0 +OP4 E02B1E 0 +OP4 E02B1F 0 +OP4 E02B20 0 +OP4 E02B21 0 +OP4 E02B22 0 +OP4 E02B23 0 +OP4 E02B24 0 +OP4 E02B25 0 +OP4 E02B26 0 +OP4 E02B27 0 +OP4 E02B28 0 +OP4 E02B29 0 +OP4 E02B2A 0 +OP4 E02B2B 0 +OP4 E02B2C 0 +OP4 E02B2D 0 +OP4 E02B2E 0 +OP4 E02B2F 0 +OP4 E02B30 0 +OP4 E02B31 0 +OP4 E02B32 0 +OP4 E02B33 0 +OP4 E02B34 0 +OP4 E02B35 0 +OP4 E02B36 0 +OP4 E02B37 0 +OP4 E02B38 0 +OP4 E02B39 0 +OP4 E02B3A 0 +OP4 E02B3B 0 +OP4 E02B3C 0 +OP4 E02B3D 0 +OP4 E02B3E 0 +OP4 E02B3F 0 +OP4 E02B40 0 +OP4 E02B41 0 +OP4 E02B42 0 +OP4 E02B43 0 +OP4 E02B44 0 +OP4 E02B45 0 +OP4 E02B46 0 +OP4 E02B47 0 +OP4 E02B48 0 +OP4 E02B49 0 +OP4 E02B4A 0 +OP4 E02B4B 0 +OP4 E02B4C 0 +OP4 E02B4D 0 +OP4 E02B4E 0 +OP4 E02B4F 0 +OP4 E02B50 0 +OP4 E02B51 0 +OP4 E02B52 0 +OP4 E02B53 0 +OP4 E02B54 0 +OP4 E02B55 0 +OP4 E02B56 0 +OP4 E02B57 0 +OP4 E02B58 0 +OP4 E02B59 0 +OP4 E02B5A 0 +OP4 E02B5B 0 +OP4 E02B5C 0 +OP4 E02B5D 0 +OP4 E02B5E 0 +OP4 E02B5F 0 +OP4 E02B60 0 +OP4 E02B61 0 +OP4 E02B62 0 +OP4 E02B63 0 +OP4 E02B64 0 +OP4 E02B65 0 +OP4 E02B66 0 +OP4 E02B67 0 +OP4 E02B68 0 +OP4 E02B69 0 +OP4 E02B6A 0 +OP4 E02B6B 0 +OP4 E02B6C 0 +OP4 E02B6D 0 +OP4 E02B6E 0 +OP4 E02B6F 0 +OP4 E02B70 0 +OP4 E02B71 0 +OP4 E02B72 0 +OP4 E02B73 0 +OP4 E02B74 0 +OP4 E02B75 0 +OP4 E02B76 0 +OP4 E02B77 0 +OP4 E02B78 0 +OP4 E02B79 0 +OP4 E02B7A 0 +OP4 E02B7B 0 +OP4 E02B7C 0 +OP4 E02B7D 0 +OP4 E02B7E 0 +OP4 E02B7F 0 +OP4 E02B80 0 +OP4 E02B81 0 +OP4 E02B82 0 +OP4 E02B83 0 +OP4 E02B84 0 +OP4 E02B85 0 +OP4 E02B86 0 +OP4 E02B87 0 +OP4 E02B88 0 +OP4 E02B89 0 +OP4 E02B8A 0 +OP4 E02B8B 0 +OP4 E02B8C 0 +OP4 E02B8D 0 +OP4 E02B8E 0 +OP4 E02B8F 0 +OP4 E02B90 0 +OP4 E02B91 0 +OP4 E02B92 0 +OP4 E02B93 0 +OP4 E02B94 0 +OP4 E02B95 0 +OP4 E02B96 0 +OP4 E02B97 0 +OP4 E02B98 0 +OP4 E02B99 0 +OP4 E02B9A 0 +OP4 E02B9B 0 +OP4 E02B9C 0 +OP4 E02B9D 0 +OP4 E02B9E 0 +OP4 E02B9F 0 +OP4 E02BA0 0 +OP4 E02BA1 0 +OP4 E02BA2 0 +OP4 E02BA3 0 +OP4 E02BA4 0 +OP4 E02BA5 0 +OP4 E02BA6 0 +OP4 E02BA7 0 +OP4 E02BA8 0 +OP4 E02BA9 0 +OP4 E02BAA 0 +OP4 E02BAB 0 +OP4 E02BAC 0 +OP4 E02BAD 0 +OP4 E02BAE 0 +OP4 E02BAF 0 +OP4 E02BB0 0 +OP4 E02BB1 0 +OP4 E02BB2 0 +OP4 E02BB3 0 +OP4 E02BB4 0 +OP4 E02BB5 0 +OP4 E02BB6 0 +OP4 E02BB7 0 +OP4 E02BB8 0 +OP4 E02BB9 0 +OP4 E02BBA 0 +OP4 E02BBB 0 +OP4 E02BBC 0 +OP4 E02BBD 0 +OP4 E02BBE 0 +OP4 E02BBF 0 +OP4 E02BC0 0 +OP4 E02BC1 0 +OP4 E02BC2 0 +OP4 E02BC3 0 +OP4 E02BC4 0 +OP4 E02BC5 0 +OP4 E02BC6 0 +OP4 E02BC7 0 +OP4 E02BC8 0 +OP4 E02BC9 0 +OP4 E02BCA 0 +OP4 E02BCB 0 +OP4 E02BCC 0 +OP4 E02BCD 0 +OP4 E02BCE 0 +OP4 E02BCF 0 +OP4 E02BD0 0 +OP4 E02BD1 0 +OP4 E02BD2 0 +OP4 E02BD3 0 +OP4 E02BD4 0 +OP4 E02BD5 0 +OP4 E02BD6 0 +OP4 E02BD7 0 +OP4 E02BD8 0 +OP4 E02BD9 0 +OP4 E02BDA 0 +OP4 E02BDB 0 +OP4 E02BDC 0 +OP4 E02BDD 0 +OP4 E02BDE 0 +OP4 E02BDF 0 +OP4 E02BE0 0 +OP4 E02BE1 0 +OP4 E02BE2 0 +OP4 E02BE3 0 +OP4 E02BE4 0 +OP4 E02BE5 0 +OP4 E02BE6 0 +OP4 E02BE7 0 +OP4 E02BE8 0 +OP4 E02BE9 0 +OP4 E02BEA 0 +OP4 E02BEB 0 +OP4 E02BEC 0 +OP4 E02BED 0 +OP4 E02BEE 0 +OP4 E02BEF 0 +OP4 E02BF0 0 +OP4 E02BF1 0 +OP4 E02BF2 0 +OP4 E02BF3 0 +OP4 E02BF4 0 +OP4 E02BF5 0 +OP4 E02BF6 0 +OP4 E02BF7 0 +OP4 E02BF8 0 +OP4 E02BF9 0 +OP4 E02BFA 0 +OP4 E02BFB 0 +OP4 E02BFC 0 +OP4 E02BFD 0 +OP4 E02BFE 0 +OP4 E02BFF 0 +OP4 E02C00 0 +OP4 E02C01 0 +OP4 E02C02 0 +OP4 E02C03 0 +OP4 E02C04 0 +OP4 E02C05 0 +OP4 E02C06 0 +OP4 E02C07 0 +OP4 E02C08 0 +OP4 E02C09 0 +OP4 E02C0A 0 +OP4 E02C0B 0 +OP4 E02C0C 0 +OP4 E02C0D 0 +OP4 E02C0E 0 +OP4 E02C0F 0 +OP4 E02C10 0 +OP4 E02C11 0 +OP4 E02C12 0 +OP4 E02C13 0 +OP4 E02C14 0 +OP4 E02C15 0 +OP4 E02C16 0 +OP4 E02C17 0 +OP4 E02C18 0 +OP4 E02C19 0 +OP4 E02C1A 0 +OP4 E02C1B 0 +OP4 E02C1C 0 +OP4 E02C1D 0 +OP4 E02C1E 0 +OP4 E02C1F 0 +OP4 E02C20 0 +OP4 E02C21 0 +OP4 E02C22 0 +OP4 E02C23 0 +OP4 E02C24 0 +OP4 E02C25 0 +OP4 E02C26 0 +OP4 E02C27 0 +OP4 E02C28 0 +OP4 E02C29 0 +OP4 E02C2A 0 +OP4 E02C2B 0 +OP4 E02C2C 0 +OP4 E02C2D 0 +OP4 E02C2E 0 +OP4 E02C2F 0 +OP4 E02C30 0 +OP4 E02C31 0 +OP4 E02C32 0 +OP4 E02C33 0 +OP4 E02C34 0 +OP4 E02C35 0 +OP4 E02C36 0 +OP4 E02C37 0 +OP4 E02C38 0 +OP4 E02C39 0 +OP4 E02C3A 0 +OP4 E02C3B 0 +OP4 E02C3C 0 +OP4 E02C3D 0 +OP4 E02C3E 0 +OP4 E02C3F 0 +OP4 E02C40 0 +OP4 E02C41 0 +OP4 E02C42 0 +OP4 E02C43 0 +OP4 E02C44 0 +OP4 E02C45 0 +OP4 E02C46 0 +OP4 E02C47 0 +OP4 E02C48 0 +OP4 E02C49 0 +OP4 E02C4A 0 +OP4 E02C4B 0 +OP4 E02C4C 0 +OP4 E02C4D 0 +OP4 E02C4E 0 +OP4 E02C4F 0 +OP4 E02C50 0 +OP4 E02C51 0 +OP4 E02C52 0 +OP4 E02C53 0 +OP4 E02C54 0 +OP4 E02C55 0 +OP4 E02C56 0 +OP4 E02C57 0 +OP4 E02C58 0 +OP4 E02C59 0 +OP4 E02C5A 0 +OP4 E02C5B 0 +OP4 E02C5C 0 +OP4 E02C5D 0 +OP4 E02C5E 0 +OP4 E02C5F 0 +OP4 E02C60 0 +OP4 E02C61 0 +OP4 E02C62 0 +OP4 E02C63 0 +OP4 E02C64 0 +OP4 E02C65 0 +OP4 E02C66 0 +OP4 E02C67 0 +OP4 E02C68 0 +OP4 E02C69 0 +OP4 E02C6A 0 +OP4 E02C6B 0 +OP4 E02C6C 0 +OP4 E02C6D 0 +OP4 E02C6E 0 +OP4 E02C6F 0 +OP4 E02C70 0 +OP4 E02C71 0 +OP4 E02C72 0 +OP4 E02C73 0 +OP4 E02C74 0 +OP4 E02C75 0 +OP4 E02C76 0 +OP4 E02C77 0 +OP4 E02C78 0 +OP4 E02C79 0 +OP4 E02C7A 0 +OP4 E02C7B 0 +OP4 E02C7C 0 +OP4 E02C7D 0 +OP4 E02C7E 0 +OP4 E02C7F 0 +OP4 E02C80 0 +OP4 E02C81 0 +OP4 E02C82 0 +OP4 E02C83 0 +OP4 E02C84 0 +OP4 E02C85 0 +OP4 E02C86 0 +OP4 E02C87 0 +OP4 E02C88 0 +OP4 E02C89 0 +OP4 E02C8A 0 +OP4 E02C8B 0 +OP4 E02C8C 0 +OP4 E02C8D 0 +OP4 E02C8E 0 +OP4 E02C8F 0 +OP4 E02C90 0 +OP4 E02C91 0 +OP4 E02C92 0 +OP4 E02C93 0 +OP4 E02C94 0 +OP4 E02C95 0 +OP4 E02C96 0 +OP4 E02C97 0 +OP4 E02C98 0 +OP4 E02C99 0 +OP4 E02C9A 0 +OP4 E02C9B 0 +OP4 E02C9C 0 +OP4 E02C9D 0 +OP4 E02C9E 0 +OP4 E02C9F 0 +OP4 E02CA0 0 +OP4 E02CA1 0 +OP4 E02CA2 0 +OP4 E02CA3 0 +OP4 E02CA4 0 +OP4 E02CA5 0 +OP4 E02CA6 0 +OP4 E02CA7 0 +OP4 E02CA8 0 +OP4 E02CA9 0 +OP4 E02CAA 0 +OP4 E02CAB 0 +OP4 E02CAC 0 +OP4 E02CAD 0 +OP4 E02CAE 0 +OP4 E02CAF 0 +OP4 E02CB0 0 +OP4 E02CB1 0 +OP4 E02CB2 0 +OP4 E02CB3 0 +OP4 E02CB4 0 +OP4 E02CB5 0 +OP4 E02CB6 0 +OP4 E02CB7 0 +OP4 E02CB8 0 +OP4 E02CB9 0 +OP4 E02CBA 0 +OP4 E02CBB 0 +OP4 E02CBC 0 +OP4 E02CBD 0 +OP4 E02CBE 0 +OP4 E02CBF 0 +OP4 E02CC0 0 +OP4 E02CC1 0 +OP4 E02CC2 0 +OP4 E02CC3 0 +OP4 E02CC4 0 +OP4 E02CC5 0 +OP4 E02CC6 0 +OP4 E02CC7 0 +OP4 E02CC8 0 +OP4 E02CC9 0 +OP4 E02CCA 0 +OP4 E02CCB 0 +OP4 E02CCC 0 +OP4 E02CCD 0 +OP4 E02CCE 0 +OP4 E02CCF 0 +OP4 E02CD0 0 +OP4 E02CD1 0 +OP4 E02CD2 0 +OP4 E02CD3 0 +OP4 E02CD4 0 +OP4 E02CD5 0 +OP4 E02CD6 0 +OP4 E02CD7 0 +OP4 E02CD8 0 +OP4 E02CD9 0 +OP4 E02CDA 0 +OP4 E02CDB 0 +OP4 E02CDC 0 +OP4 E02CDD 0 +OP4 E02CDE 0 +OP4 E02CDF 0 +OP4 E02CE0 0 +OP4 E02CE1 0 +OP4 E02CE2 0 +OP4 E02CE3 0 +OP4 E02CE4 0 +OP4 E02CE5 0 +OP4 E02CE6 0 +OP4 E02CE7 0 +OP4 E02CE8 0 +OP4 E02CE9 0 +OP4 E02CEA 0 +OP4 E02CEB 0 +OP4 E02CEC 0 +OP4 E02CED 0 +OP4 E02CEE 0 +OP4 E02CEF 0 +OP4 E02CF0 0 +OP4 E02CF1 0 +OP4 E02CF2 0 +OP4 E02CF3 0 +OP4 E02CF4 0 +OP4 E02CF5 0 +OP4 E02CF6 0 +OP4 E02CF7 0 +OP4 E02CF8 0 +OP4 E02CF9 0 +OP4 E02CFA 0 +OP4 E02CFB 0 +OP4 E02CFC 0 +OP4 E02CFD 0 +OP4 E02CFE 0 +OP4 E02CFF 0 +OP4 E02D00 0 +OP4 E02D01 0 +OP4 E02D02 0 +OP4 E02D03 0 +OP4 E02D04 0 +OP4 E02D05 0 +OP4 E02D06 0 +OP4 E02D07 0 +OP4 E02D08 0 +OP4 E02D09 0 +OP4 E02D0A 0 +OP4 E02D0B 0 +OP4 E02D0C 0 +OP4 E02D0D 0 +OP4 E02D0E 0 +OP4 E02D0F 0 +OP4 E02D10 0 +OP4 E02D11 0 +OP4 E02D12 0 +OP4 E02D13 0 +OP4 E02D14 0 +OP4 E02D15 0 +OP4 E02D16 0 +OP4 E02D17 0 +OP4 E02D18 0 +OP4 E02D19 0 +OP4 E02D1A 0 +OP4 E02D1B 0 +OP4 E02D1C 0 +OP4 E02D1D 0 +OP4 E02D1E 0 +OP4 E02D1F 0 +OP4 E02D20 0 +OP4 E02D21 0 +OP4 E02D22 0 +OP4 E02D23 0 +OP4 E02D24 0 +OP4 E02D25 0 +OP4 E02D26 0 +OP4 E02D27 0 +OP4 E02D28 0 +OP4 E02D29 0 +OP4 E02D2A 0 +OP4 E02D2B 0 +OP4 E02D2C 0 +OP4 E02D2D 0 +OP4 E02D2E 0 +OP4 E02D2F 0 +OP4 E02D30 0 +OP4 E02D31 0 +OP4 E02D32 0 +OP4 E02D33 0 +OP4 E02D34 0 +OP4 E02D35 0 +OP4 E02D36 0 +OP4 E02D37 0 +OP4 E02D38 0 +OP4 E02D39 0 +OP4 E02D3A 0 +OP4 E02D3B 0 +OP4 E02D3C 0 +OP4 E02D3D 0 +OP4 E02D3E 0 +OP4 E02D3F 0 +OP4 E02D40 0 +OP4 E02D41 0 +OP4 E02D42 0 +OP4 E02D43 0 +OP4 E02D44 0 +OP4 E02D45 0 +OP4 E02D46 0 +OP4 E02D47 0 +OP4 E02D48 0 +OP4 E02D49 0 +OP4 E02D4A 0 +OP4 E02D4B 0 +OP4 E02D4C 0 +OP4 E02D4D 0 +OP4 E02D4E 0 +OP4 E02D4F 0 +OP4 E02D50 0 +OP4 E02D51 0 +OP4 E02D52 0 +OP4 E02D53 0 +OP4 E02D54 0 +OP4 E02D55 0 +OP4 E02D56 0 +OP4 E02D57 0 +OP4 E02D58 0 +OP4 E02D59 0 +OP4 E02D5A 0 +OP4 E02D5B 0 +OP4 E02D5C 0 +OP4 E02D5D 0 +OP4 E02D5E 0 +OP4 E02D5F 0 +OP4 E02D60 0 +OP4 E02D61 0 +OP4 E02D62 0 +OP4 E02D63 0 +OP4 E02D64 0 +OP4 E02D65 0 +OP4 E02D66 0 +OP4 E02D67 0 +OP4 E02D68 0 +OP4 E02D69 0 +OP4 E02D6A 0 +OP4 E02D6B 0 +OP4 E02D6C 0 +OP4 E02D6D 0 +OP4 E02D6E 0 +OP4 E02D6F 0 +OP4 E02D70 0 +OP4 E02D71 0 +OP4 E02D72 0 +OP4 E02D73 0 +OP4 E02D74 0 +OP4 E02D75 0 +OP4 E02D76 0 +OP4 E02D77 0 +OP4 E02D78 0 +OP4 E02D79 0 +OP4 E02D7A 0 +OP4 E02D7B 0 +OP4 E02D7C 0 +OP4 E02D7D 0 +OP4 E02D7E 0 +OP4 E02D7F 0 +OP4 E02D80 0 +OP4 E02D81 0 +OP4 E02D82 0 +OP4 E02D83 0 +OP4 E02D84 0 +OP4 E02D85 0 +OP4 E02D86 0 +OP4 E02D87 0 +OP4 E02D88 0 +OP4 E02D89 0 +OP4 E02D8A 0 +OP4 E02D8B 0 +OP4 E02D8C 0 +OP4 E02D8D 0 +OP4 E02D8E 0 +OP4 E02D8F 0 +OP4 E02D90 0 +OP4 E02D91 0 +OP4 E02D92 0 +OP4 E02D93 0 +OP4 E02D94 0 +OP4 E02D95 0 +OP4 E02D96 0 +OP4 E02D97 0 +OP4 E02D98 0 +OP4 E02D99 0 +OP4 E02D9A 0 +OP4 E02D9B 0 +OP4 E02D9C 0 +OP4 E02D9D 0 +OP4 E02D9E 0 +OP4 E02D9F 0 +OP4 E02DA0 0 +OP4 E02DA1 0 +OP4 E02DA2 0 +OP4 E02DA3 0 +OP4 E02DA4 0 +OP4 E02DA5 0 +OP4 E02DA6 0 +OP4 E02DA7 0 +OP4 E02DA8 0 +OP4 E02DA9 0 +OP4 E02DAA 0 +OP4 E02DAB 0 +OP4 E02DAC 0 +OP4 E02DAD 0 +OP4 E02DAE 0 +OP4 E02DAF 0 +OP4 E02DB0 0 +OP4 E02DB1 0 +OP4 E02DB2 0 +OP4 E02DB3 0 +OP4 E02DB4 0 +OP4 E02DB5 0 +OP4 E02DB6 0 +OP4 E02DB7 0 +OP4 E02DB8 0 +OP4 E02DB9 0 +OP4 E02DBA 0 +OP4 E02DBB 0 +OP4 E02DBC 0 +OP4 E02DBD 0 +OP4 E02DBE 0 +OP4 E02DBF 0 +OP4 E02DC0 0 +OP4 E02DC1 0 +OP4 E02DC2 0 +OP4 E02DC3 0 +OP4 E02DC4 0 +OP4 E02DC5 0 +OP4 E02DC6 0 +OP4 E02DC7 0 +OP4 E02DC8 0 +OP4 E02DC9 0 +OP4 E02DCA 0 +OP4 E02DCB 0 +OP4 E02DCC 0 +OP4 E02DCD 0 +OP4 E02DCE 0 +OP4 E02DCF 0 +OP4 E02DD0 0 +OP4 E02DD1 0 +OP4 E02DD2 0 +OP4 E02DD3 0 +OP4 E02DD4 0 +OP4 E02DD5 0 +OP4 E02DD6 0 +OP4 E02DD7 0 +OP4 E02DD8 0 +OP4 E02DD9 0 +OP4 E02DDA 0 +OP4 E02DDB 0 +OP4 E02DDC 0 +OP4 E02DDD 0 +OP4 E02DDE 0 +OP4 E02DDF 0 +OP4 E02DE0 0 +OP4 E02DE1 0 +OP4 E02DE2 0 +OP4 E02DE3 0 +OP4 E02DE4 0 +OP4 E02DE5 0 +OP4 E02DE6 0 +OP4 E02DE7 0 +OP4 E02DE8 0 +OP4 E02DE9 0 +OP4 E02DEA 0 +OP4 E02DEB 0 +OP4 E02DEC 0 +OP4 E02DED 0 +OP4 E02DEE 0 +OP4 E02DEF 0 +OP4 E02DF0 0 +OP4 E02DF1 0 +OP4 E02DF2 0 +OP4 E02DF3 0 +OP4 E02DF4 0 +OP4 E02DF5 0 +OP4 E02DF6 0 +OP4 E02DF7 0 +OP4 E02DF8 0 +OP4 E02DF9 0 +OP4 E02DFA 0 +OP4 E02DFB 0 +OP4 E02DFC 0 +OP4 E02DFD 0 +OP4 E02DFE 0 +OP4 E02DFF 0 +OP4 E02E00 0 +OP4 E02E01 0 +OP4 E02E02 0 +OP4 E02E03 0 +OP4 E02E04 0 +OP4 E02E05 0 +OP4 E02E06 0 +OP4 E02E07 0 +OP4 E02E08 0 +OP4 E02E09 0 +OP4 E02E0A 0 +OP4 E02E0B 0 +OP4 E02E0C 0 +OP4 E02E0D 0 +OP4 E02E0E 0 +OP4 E02E0F 0 +OP4 E02E10 0 +OP4 E02E11 0 +OP4 E02E12 0 +OP4 E02E13 0 +OP4 E02E14 0 +OP4 E02E15 0 +OP4 E02E16 0 +OP4 E02E17 0 +OP4 E02E18 0 +OP4 E02E19 0 +OP4 E02E1A 0 +OP4 E02E1B 0 +OP4 E02E1C 0 +OP4 E02E1D 0 +OP4 E02E1E 0 +OP4 E02E1F 0 +OP4 E02E20 0 +OP4 E02E21 0 +OP4 E02E22 0 +OP4 E02E23 0 +OP4 E02E24 0 +OP4 E02E25 0 +OP4 E02E26 0 +OP4 E02E27 0 +OP4 E02E28 0 +OP4 E02E29 0 +OP4 E02E2A 0 +OP4 E02E2B 0 +OP4 E02E2C 0 +OP4 E02E2D 0 +OP4 E02E2E 0 +OP4 E02E2F 0 +OP4 E02E30 0 +OP4 E02E31 0 +OP4 E02E32 0 +OP4 E02E33 0 +OP4 E02E34 0 +OP4 E02E35 0 +OP4 E02E36 0 +OP4 E02E37 0 +OP4 E02E38 0 +OP4 E02E39 0 +OP4 E02E3A 0 +OP4 E02E3B 0 +OP4 E02E3C 0 +OP4 E02E3D 0 +OP4 E02E3E 0 +OP4 E02E3F 0 +OP4 E02E40 0 +OP4 E02E41 0 +OP4 E02E42 0 +OP4 E02E43 0 +OP4 E02E44 0 +OP4 E02E45 0 +OP4 E02E46 0 +OP4 E02E47 0 +OP4 E02E48 0 +OP4 E02E49 0 +OP4 E02E4A 0 +OP4 E02E4B 0 +OP4 E02E4C 0 +OP4 E02E4D 0 +OP4 E02E4E 0 +OP4 E02E4F 0 +OP4 E02E50 0 +OP4 E02E51 0 +OP4 E02E52 0 +OP4 E02E53 0 +OP4 E02E54 0 +OP4 E02E55 0 +OP4 E02E56 0 +OP4 E02E57 0 +OP4 E02E58 0 +OP4 E02E59 0 +OP4 E02E5A 0 +OP4 E02E5B 0 +OP4 E02E5C 0 +OP4 E02E5D 0 +OP4 E02E5E 0 +OP4 E02E5F 0 +OP4 E02E60 0 +OP4 E02E61 0 +OP4 E02E62 0 +OP4 E02E63 0 +OP4 E02E64 0 +OP4 E02E65 0 +OP4 E02E66 0 +OP4 E02E67 0 +OP4 E02E68 0 +OP4 E02E69 0 +OP4 E02E6A 0 +OP4 E02E6B 0 +OP4 E02E6C 0 +OP4 E02E6D 0 +OP4 E02E6E 0 +OP4 E02E6F 0 +OP4 E02E70 0 +OP4 E02E71 0 +OP4 E02E72 0 +OP4 E02E73 0 +OP4 E02E74 0 +OP4 E02E75 0 +OP4 E02E76 0 +OP4 E02E77 0 +OP4 E02E78 0 +OP4 E02E79 0 +OP4 E02E7A 0 +OP4 E02E7B 0 +OP4 E02E7C 0 +OP4 E02E7D 0 +OP4 E02E7E 0 +OP4 E02E7F 0 +OP4 E02E80 0 +OP4 E02E81 0 +OP4 E02E82 0 +OP4 E02E83 0 +OP4 E02E84 0 +OP4 E02E85 0 +OP4 E02E86 0 +OP4 E02E87 0 +OP4 E02E88 0 +OP4 E02E89 0 +OP4 E02E8A 0 +OP4 E02E8B 0 +OP4 E02E8C 0 +OP4 E02E8D 0 +OP4 E02E8E 0 +OP4 E02E8F 0 +OP4 E02E90 0 +OP4 E02E91 0 +OP4 E02E92 0 +OP4 E02E93 0 +OP4 E02E94 0 +OP4 E02E95 0 +OP4 E02E96 0 +OP4 E02E97 0 +OP4 E02E98 0 +OP4 E02E99 0 +OP4 E02E9A 0 +OP4 E02E9B 0 +OP4 E02E9C 0 +OP4 E02E9D 0 +OP4 E02E9E 0 +OP4 E02E9F 0 +OP4 E02EA0 0 +OP4 E02EA1 0 +OP4 E02EA2 0 +OP4 E02EA3 0 +OP4 E02EA4 0 +OP4 E02EA5 0 +OP4 E02EA6 0 +OP4 E02EA7 0 +OP4 E02EA8 0 +OP4 E02EA9 0 +OP4 E02EAA 0 +OP4 E02EAB 0 +OP4 E02EAC 0 +OP4 E02EAD 0 +OP4 E02EAE 0 +OP4 E02EAF 0 +OP4 E02EB0 0 +OP4 E02EB1 0 +OP4 E02EB2 0 +OP4 E02EB3 0 +OP4 E02EB4 0 +OP4 E02EB5 0 +OP4 E02EB6 0 +OP4 E02EB7 0 +OP4 E02EB8 0 +OP4 E02EB9 0 +OP4 E02EBA 0 +OP4 E02EBB 0 +OP4 E02EBC 0 +OP4 E02EBD 0 +OP4 E02EBE 0 +OP4 E02EBF 0 +OP4 E02EC0 0 +OP4 E02EC1 0 +OP4 E02EC2 0 +OP4 E02EC3 0 +OP4 E02EC4 0 +OP4 E02EC5 0 +OP4 E02EC6 0 +OP4 E02EC7 0 +OP4 E02EC8 0 +OP4 E02EC9 0 +OP4 E02ECA 0 +OP4 E02ECB 0 +OP4 E02ECC 0 +OP4 E02ECD 0 +OP4 E02ECE 0 +OP4 E02ECF 0 +OP4 E02ED0 0 +OP4 E02ED1 0 +OP4 E02ED2 0 +OP4 E02ED3 0 +OP4 E02ED4 0 +OP4 E02ED5 0 +OP4 E02ED6 0 +OP4 E02ED7 0 +OP4 E02ED8 0 +OP4 E02ED9 0 +OP4 E02EDA 0 +OP4 E02EDB 0 +OP4 E02EDC 0 +OP4 E02EDD 0 +OP4 E02EDE 0 +OP4 E02EDF 0 +OP4 E02EE0 0 +OP4 E02EE1 0 +OP4 E02EE2 0 +OP4 E02EE3 0 +OP4 E02EE4 0 +OP4 E02EE5 0 +OP4 E02EE6 0 +OP4 E02EE7 0 +OP4 E02EE8 0 +OP4 E02EE9 0 +OP4 E02EEA 0 +OP4 E02EEB 0 +OP4 E02EEC 0 +OP4 E02EED 0 +OP4 E02EEE 0 +OP4 E02EEF 0 +OP4 E02EF0 0 +OP4 E02EF1 0 +OP4 E02EF2 0 +OP4 E02EF3 0 +OP4 E02EF4 0 +OP4 E02EF5 0 +OP4 E02EF6 0 +OP4 E02EF7 0 +OP4 E02EF8 0 +OP4 E02EF9 0 +OP4 E02EFA 0 +OP4 E02EFB 0 +OP4 E02EFC 0 +OP4 E02EFD 0 +OP4 E02EFE 0 +OP4 E02EFF 0 +OP4 E02F00 0 +OP4 E02F01 0 +OP4 E02F02 0 +OP4 E02F03 0 +OP4 E02F04 0 +OP4 E02F05 0 +OP4 E02F06 0 +OP4 E02F07 0 +OP4 E02F08 0 +OP4 E02F09 0 +OP4 E02F0A 0 +OP4 E02F0B 0 +OP4 E02F0C 0 +OP4 E02F0D 0 +OP4 E02F0E 0 +OP4 E02F0F 0 +OP4 E02F10 0 +OP4 E02F11 0 +OP4 E02F12 0 +OP4 E02F13 0 +OP4 E02F14 0 +OP4 E02F15 0 +OP4 E02F16 0 +OP4 E02F17 0 +OP4 E02F18 0 +OP4 E02F19 0 +OP4 E02F1A 0 +OP4 E02F1B 0 +OP4 E02F1C 0 +OP4 E02F1D 0 +OP4 E02F1E 0 +OP4 E02F1F 0 +OP4 E02F20 0 +OP4 E02F21 0 +OP4 E02F22 0 +OP4 E02F23 0 +OP4 E02F24 0 +OP4 E02F25 0 +OP4 E02F26 0 +OP4 E02F27 0 +OP4 E02F28 0 +OP4 E02F29 0 +OP4 E02F2A 0 +OP4 E02F2B 0 +OP4 E02F2C 0 +OP4 E02F2D 0 +OP4 E02F2E 0 +OP4 E02F2F 0 +OP4 E02F30 0 +OP4 E02F31 0 +OP4 E02F32 0 +OP4 E02F33 0 +OP4 E02F34 0 +OP4 E02F35 0 +OP4 E02F36 0 +OP4 E02F37 0 +OP4 E02F38 0 +OP4 E02F39 0 +OP4 E02F3A 0 +OP4 E02F3B 0 +OP4 E02F3C 0 +OP4 E02F3D 0 +OP4 E02F3E 0 +OP4 E02F3F 0 +OP4 E02F40 0 +OP4 E02F41 0 +OP4 E02F42 0 +OP4 E02F43 0 +OP4 E02F44 0 +OP4 E02F45 0 +OP4 E02F46 0 +OP4 E02F47 0 +OP4 E02F48 0 +OP4 E02F49 0 +OP4 E02F4A 0 +OP4 E02F4B 0 +OP4 E02F4C 0 +OP4 E02F4D 0 +OP4 E02F4E 0 +OP4 E02F4F 0 +OP4 E02F50 0 +OP4 E02F51 0 +OP4 E02F52 0 +OP4 E02F53 0 +OP4 E02F54 0 +OP4 E02F55 0 +OP4 E02F56 0 +OP4 E02F57 0 +OP4 E02F58 0 +OP4 E02F59 0 +OP4 E02F5A 0 +OP4 E02F5B 0 +OP4 E02F5C 0 +OP4 E02F5D 0 +OP4 E02F5E 0 +OP4 E02F5F 0 +OP4 E02F60 0 +OP4 E02F61 0 +OP4 E02F62 0 +OP4 E02F63 0 +OP4 E02F64 0 +OP4 E02F65 0 +OP4 E02F66 0 +OP4 E02F67 0 +OP4 E02F68 0 +OP4 E02F69 0 +OP4 E02F6A 0 +OP4 E02F6B 0 +OP4 E02F6C 0 +OP4 E02F6D 0 +OP4 E02F6E 0 +OP4 E02F6F 0 +OP4 E02F70 0 +OP4 E02F71 0 +OP4 E02F72 0 +OP4 E02F73 0 +OP4 E02F74 0 +OP4 E02F75 0 +OP4 E02F76 0 +OP4 E02F77 0 +OP4 E02F78 0 +OP4 E02F79 0 +OP4 E02F7A 0 +OP4 E02F7B 0 +OP4 E02F7C 0 +OP4 E02F7D 0 +OP4 E02F7E 0 +OP4 E02F7F 0 +OP4 E02F80 0 +OP4 E02F81 0 +OP4 E02F82 0 +OP4 E02F83 0 +OP4 E02F84 0 +OP4 E02F85 0 +OP4 E02F86 0 +OP4 E02F87 0 +OP4 E02F88 0 +OP4 E02F89 0 +OP4 E02F8A 0 +OP4 E02F8B 0 +OP4 E02F8C 0 +OP4 E02F8D 0 +OP4 E02F8E 0 +OP4 E02F8F 0 +OP4 E02F90 0 +OP4 E02F91 0 +OP4 E02F92 0 +OP4 E02F93 0 +OP4 E02F94 0 +OP4 E02F95 0 +OP4 E02F96 0 +OP4 E02F97 0 +OP4 E02F98 0 +OP4 E02F99 0 +OP4 E02F9A 0 +OP4 E02F9B 0 +OP4 E02F9C 0 +OP4 E02F9D 0 +OP4 E02F9E 0 +OP4 E02F9F 0 +OP4 E02FA0 0 +OP4 E02FA1 0 +OP4 E02FA2 0 +OP4 E02FA3 0 +OP4 E02FA4 0 +OP4 E02FA5 0 +OP4 E02FA6 0 +OP4 E02FA7 0 +OP4 E02FA8 0 +OP4 E02FA9 0 +OP4 E02FAA 0 +OP4 E02FAB 0 +OP4 E02FAC 0 +OP4 E02FAD 0 +OP4 E02FAE 0 +OP4 E02FAF 0 +OP4 E02FB0 0 +OP4 E02FB1 0 +OP4 E02FB2 0 +OP4 E02FB3 0 +OP4 E02FB4 0 +OP4 E02FB5 0 +OP4 E02FB6 0 +OP4 E02FB7 0 +OP4 E02FB8 0 +OP4 E02FB9 0 +OP4 E02FBA 0 +OP4 E02FBB 0 +OP4 E02FBC 0 +OP4 E02FBD 0 +OP4 E02FBE 0 +OP4 E02FBF 0 +OP4 E02FC0 0 +OP4 E02FC1 0 +OP4 E02FC2 0 +OP4 E02FC3 0 +OP4 E02FC4 0 +OP4 E02FC5 0 +OP4 E02FC6 0 +OP4 E02FC7 0 +OP4 E02FC8 0 +OP4 E02FC9 0 +OP4 E02FCA 0 +OP4 E02FCB 0 +OP4 E02FCC 0 +OP4 E02FCD 0 +OP4 E02FCE 0 +OP4 E02FCF 0 +OP4 E02FD0 0 +OP4 E02FD1 0 +OP4 E02FD2 0 +OP4 E02FD3 0 +OP4 E02FD4 0 +OP4 E02FD5 0 +OP4 E02FD6 0 +OP4 E02FD7 0 +OP4 E02FD8 0 +OP4 E02FD9 0 +OP4 E02FDA 0 +OP4 E02FDB 0 +OP4 E02FDC 0 +OP4 E02FDD 0 +OP4 E02FDE 0 +OP4 E02FDF 0 +OP4 E02FE0 0 +OP4 E02FE1 0 +OP4 E02FE2 0 +OP4 E02FE3 0 +OP4 E02FE4 0 +OP4 E02FE5 0 +OP4 E02FE6 0 +OP4 E02FE7 0 +OP4 E02FE8 0 +OP4 E02FE9 0 +OP4 E02FEA 0 +OP4 E02FEB 0 +OP4 E02FEC 0 +OP4 E02FED 0 +OP4 E02FEE 0 +OP4 E02FEF 0 +OP4 E02FF0 0 +OP4 E02FF1 0 +OP4 E02FF2 0 +OP4 E02FF3 0 +OP4 E02FF4 0 +OP4 E02FF5 0 +OP4 E02FF6 0 +OP4 E02FF7 0 +OP4 E02FF8 0 +OP4 E02FF9 0 +OP4 E02FFA 0 +OP4 E02FFB 0 +OP4 E02FFC 0 +OP4 E02FFD 0 +OP4 E02FFE 0 +OP4 E02FFF 0 +OP4 E03000 0 +OP4 E03001 0 +OP4 E03002 0 +OP4 E03003 0 +OP4 E03004 0 +OP4 E03005 0 +OP4 E03006 0 +OP4 E03007 0 +OP4 E03008 0 +OP4 E03009 0 +OP4 E0300A 0 +OP4 E0300B 0 +OP4 E0300C 0 +OP4 E0300D 0 +OP4 E0300E 0 +OP4 E0300F 0 +OP4 E03010 0 +OP4 E03011 0 +OP4 E03012 0 +OP4 E03013 0 +OP4 E03014 0 +OP4 E03015 0 +OP4 E03016 0 +OP4 E03017 0 +OP4 E03018 0 +OP4 E03019 0 +OP4 E0301A 0 +OP4 E0301B 0 +OP4 E0301C 0 +OP4 E0301D 0 +OP4 E0301E 0 +OP4 E0301F 0 +OP4 E03020 0 +OP4 E03021 0 +OP4 E03022 0 +OP4 E03023 0 +OP4 E03024 0 +OP4 E03025 0 +OP4 E03026 0 +OP4 E03027 0 +OP4 E03028 0 +OP4 E03029 0 +OP4 E0302A 0 +OP4 E0302B 0 +OP4 E0302C 0 +OP4 E0302D 0 +OP4 E0302E 0 +OP4 E0302F 0 +OP4 E03030 0 +OP4 E03031 0 +OP4 E03032 0 +OP4 E03033 0 +OP4 E03034 0 +OP4 E03035 0 +OP4 E03036 0 +OP4 E03037 0 +OP4 E03038 0 +OP4 E03039 0 +OP4 E0303A 0 +OP4 E0303B 0 +OP4 E0303C 0 +OP4 E0303D 0 +OP4 E0303E 0 +OP4 E0303F 0 +OP4 E03040 0 +OP4 E03041 0 +OP4 E03042 0 +OP4 E03043 0 +OP4 E03044 0 +OP4 E03045 0 +OP4 E03046 0 +OP4 E03047 0 +OP4 E03048 0 +OP4 E03049 0 +OP4 E0304A 0 +OP4 E0304B 0 +OP4 E0304C 0 +OP4 E0304D 0 +OP4 E0304E 0 +OP4 E0304F 0 +OP4 E03050 0 +OP4 E03051 0 +OP4 E03052 0 +OP4 E03053 0 +OP4 E03054 0 +OP4 E03055 0 +OP4 E03056 0 +OP4 E03057 0 +OP4 E03058 0 +OP4 E03059 0 +OP4 E0305A 0 +OP4 E0305B 0 +OP4 E0305C 0 +OP4 E0305D 0 +OP4 E0305E 0 +OP4 E0305F 0 +OP4 E03060 0 +OP4 E03061 0 +OP4 E03062 0 +OP4 E03063 0 +OP4 E03064 0 +OP4 E03065 0 +OP4 E03066 0 +OP4 E03067 0 +OP4 E03068 0 +OP4 E03069 0 +OP4 E0306A 0 +OP4 E0306B 0 +OP4 E0306C 0 +OP4 E0306D 0 +OP4 E0306E 0 +OP4 E0306F 0 +OP4 E03070 0 +OP4 E03071 0 +OP4 E03072 0 +OP4 E03073 0 +OP4 E03074 0 +OP4 E03075 0 +OP4 E03076 0 +OP4 E03077 0 +OP4 E03078 0 +OP4 E03079 0 +OP4 E0307A 0 +OP4 E0307B 0 +OP4 E0307C 0 +OP4 E0307D 0 +OP4 E0307E 0 +OP4 E0307F 0 +OP4 E03080 0 +OP4 E03081 0 +OP4 E03082 0 +OP4 E03083 0 +OP4 E03084 0 +OP4 E03085 0 +OP4 E03086 0 +OP4 E03087 0 +OP4 E03088 0 +OP4 E03089 0 +OP4 E0308A 0 +OP4 E0308B 0 +OP4 E0308C 0 +OP4 E0308D 0 +OP4 E0308E 0 +OP4 E0308F 0 +OP4 E03090 0 +OP4 E03091 0 +OP4 E03092 0 +OP4 E03093 0 +OP4 E03094 0 +OP4 E03095 0 +OP4 E03096 0 +OP4 E03097 0 +OP4 E03098 0 +OP4 E03099 0 +OP4 E0309A 0 +OP4 E0309B 0 +OP4 E0309C 0 +OP4 E0309D 0 +OP4 E0309E 0 +OP4 E0309F 0 +OP4 E030A0 0 +OP4 E030A1 0 +OP4 E030A2 0 +OP4 E030A3 0 +OP4 E030A4 0 +OP4 E030A5 0 +OP4 E030A6 0 +OP4 E030A7 0 +OP4 E030A8 0 +OP4 E030A9 0 +OP4 E030AA 0 +OP4 E030AB 0 +OP4 E030AC 0 +OP4 E030AD 0 +OP4 E030AE 0 +OP4 E030AF 0 +OP4 E030B0 0 +OP4 E030B1 0 +OP4 E030B2 0 +OP4 E030B3 0 +OP4 E030B4 0 +OP4 E030B5 0 +OP4 E030B6 0 +OP4 E030B7 0 +OP4 E030B8 0 +OP4 E030B9 0 +OP4 E030BA 0 +OP4 E030BB 0 +OP4 E030BC 0 +OP4 E030BD 0 +OP4 E030BE 0 +OP4 E030BF 0 +OP4 E030C0 0 +OP4 E030C1 0 +OP4 E030C2 0 +OP4 E030C3 0 +OP4 E030C4 0 +OP4 E030C5 0 +OP4 E030C6 0 +OP4 E030C7 0 +OP4 E030C8 0 +OP4 E030C9 0 +OP4 E030CA 0 +OP4 E030CB 0 +OP4 E030CC 0 +OP4 E030CD 0 +OP4 E030CE 0 +OP4 E030CF 0 +OP4 E030D0 0 +OP4 E030D1 0 +OP4 E030D2 0 +OP4 E030D3 0 +OP4 E030D4 0 +OP4 E030D5 0 +OP4 E030D6 0 +OP4 E030D7 0 +OP4 E030D8 0 +OP4 E030D9 0 +OP4 E030DA 0 +OP4 E030DB 0 +OP4 E030DC 0 +OP4 E030DD 0 +OP4 E030DE 0 +OP4 E030DF 0 +OP4 E030E0 0 +OP4 E030E1 0 +OP4 E030E2 0 +OP4 E030E3 0 +OP4 E030E4 0 +OP4 E030E5 0 +OP4 E030E6 0 +OP4 E030E7 0 +OP4 E030E8 0 +OP4 E030E9 0 +OP4 E030EA 0 +OP4 E030EB 0 +OP4 E030EC 0 +OP4 E030ED 0 +OP4 E030EE 0 +OP4 E030EF 0 +OP4 E030F0 0 +OP4 E030F1 0 +OP4 E030F2 0 +OP4 E030F3 0 +OP4 E030F4 0 +OP4 E030F5 0 +OP4 E030F6 0 +OP4 E030F7 0 +OP4 E030F8 0 +OP4 E030F9 0 +OP4 E030FA 0 +OP4 E030FB 0 +OP4 E030FC 0 +OP4 E030FD 0 +OP4 E030FE 0 +OP4 E030FF 0 +OP4 E03100 0 +OP4 E03101 0 +OP4 E03102 0 +OP4 E03103 0 +OP4 E03104 0 +OP4 E03105 0 +OP4 E03106 0 +OP4 E03107 0 +OP4 E03108 0 +OP4 E03109 0 +OP4 E0310A 0 +OP4 E0310B 0 +OP4 E0310C 0 +OP4 E0310D 0 +OP4 E0310E 0 +OP4 E0310F 0 +OP4 E03110 0 +OP4 E03111 0 +OP4 E03112 0 +OP4 E03113 0 +OP4 E03114 0 +OP4 E03115 0 +OP4 E03116 0 +OP4 E03117 0 +OP4 E03118 0 +OP4 E03119 0 +OP4 E0311A 0 +OP4 E0311B 0 +OP4 E0311C 0 +OP4 E0311D 0 +OP4 E0311E 0 +OP4 E0311F 0 +OP4 E03120 0 +OP4 E03121 0 +OP4 E03122 0 +OP4 E03123 0 +OP4 E03124 0 +OP4 E03125 0 +OP4 E03126 0 +OP4 E03127 0 +OP4 E03128 0 +OP4 E03129 0 +OP4 E0312A 0 +OP4 E0312B 0 +OP4 E0312C 0 +OP4 E0312D 0 +OP4 E0312E 0 +OP4 E0312F 0 +OP4 E03130 0 +OP4 E03131 0 +OP4 E03132 0 +OP4 E03133 0 +OP4 E03134 0 +OP4 E03135 0 +OP4 E03136 0 +OP4 E03137 0 +OP4 E03138 0 +OP4 E03139 0 +OP4 E0313A 0 +OP4 E0313B 0 +OP4 E0313C 0 +OP4 E0313D 0 +OP4 E0313E 0 +OP4 E0313F 0 +OP4 E03140 0 +OP4 E03141 0 +OP4 E03142 0 +OP4 E03143 0 +OP4 E03144 0 +OP4 E03145 0 +OP4 E03146 0 +OP4 E03147 0 +OP4 E03148 0 +OP4 E03149 0 +OP4 E0314A 0 +OP4 E0314B 0 +OP4 E0314C 0 +OP4 E0314D 0 +OP4 E0314E 0 +OP4 E0314F 0 +OP4 E03150 0 +OP4 E03151 0 +OP4 E03152 0 +OP4 E03153 0 +OP4 E03154 0 +OP4 E03155 0 +OP4 E03156 0 +OP4 E03157 0 +OP4 E03158 0 +OP4 E03159 0 +OP4 E0315A 0 +OP4 E0315B 0 +OP4 E0315C 0 +OP4 E0315D 0 +OP4 E0315E 0 +OP4 E0315F 0 +OP4 E03160 0 +OP4 E03161 0 +OP4 E03162 0 +OP4 E03163 0 +OP4 E03164 0 +OP4 E03165 0 +OP4 E03166 0 +OP4 E03167 0 +OP4 E03168 0 +OP4 E03169 0 +OP4 E0316A 0 +OP4 E0316B 0 +OP4 E0316C 0 +OP4 E0316D 0 +OP4 E0316E 0 +OP4 E0316F 0 +OP4 E03170 0 +OP4 E03171 0 +OP4 E03172 0 +OP4 E03173 0 +OP4 E03174 0 +OP4 E03175 0 +OP4 E03176 0 +OP4 E03177 0 +OP4 E03178 0 +OP4 E03179 0 +OP4 E0317A 0 +OP4 E0317B 0 +OP4 E0317C 0 +OP4 E0317D 0 +OP4 E0317E 0 +OP4 E0317F 0 +OP4 E03180 0 +OP4 E03181 0 +OP4 E03182 0 +OP4 E03183 0 +OP4 E03184 0 +OP4 E03185 0 +OP4 E03186 0 +OP4 E03187 0 +OP4 E03188 0 +OP4 E03189 0 +OP4 E0318A 0 +OP4 E0318B 0 +OP4 E0318C 0 +OP4 E0318D 0 +OP4 E0318E 0 +OP4 E0318F 0 +OP4 E03190 0 +OP4 E03191 0 +OP4 E03192 0 +OP4 E03193 0 +OP4 E03194 0 +OP4 E03195 0 +OP4 E03196 0 +OP4 E03197 0 +OP4 E03198 0 +OP4 E03199 0 +OP4 E0319A 0 +OP4 E0319B 0 +OP4 E0319C 0 +OP4 E0319D 0 +OP4 E0319E 0 +OP4 E0319F 0 +OP4 E031A0 0 +OP4 E031A1 0 +OP4 E031A2 0 +OP4 E031A3 0 +OP4 E031A4 0 +OP4 E031A5 0 +OP4 E031A6 0 +OP4 E031A7 0 +OP4 E031A8 0 +OP4 E031A9 0 +OP4 E031AA 0 +OP4 E031AB 0 +OP4 E031AC 0 +OP4 E031AD 0 +OP4 E031AE 0 +OP4 E031AF 0 +OP4 E031B0 0 +OP4 E031B1 0 +OP4 E031B2 0 +OP4 E031B3 0 +OP4 E031B4 0 +OP4 E031B5 0 +OP4 E031B6 0 +OP4 E031B7 0 +OP4 E031B8 0 +OP4 E031B9 0 +OP4 E031BA 0 +OP4 E031BB 0 +OP4 E031BC 0 +OP4 E031BD 0 +OP4 E031BE 0 +OP4 E031BF 0 +OP4 E031C0 0 +OP4 E031C1 0 +OP4 E031C2 0 +OP4 E031C3 0 +OP4 E031C4 0 +OP4 E031C5 0 +OP4 E031C6 0 +OP4 E031C7 0 +OP4 E031C8 0 +OP4 E031C9 0 +OP4 E031CA 0 +OP4 E031CB 0 +OP4 E031CC 0 +OP4 E031CD 0 +OP4 E031CE 0 +OP4 E031CF 0 +OP4 E031D0 0 +OP4 E031D1 0 +OP4 E031D2 0 +OP4 E031D3 0 +OP4 E031D4 0 +OP4 E031D5 0 +OP4 E031D6 0 +OP4 E031D7 0 +OP4 E031D8 0 +OP4 E031D9 0 +OP4 E031DA 0 +OP4 E031DB 0 +OP4 E031DC 0 +OP4 E031DD 0 +OP4 E031DE 0 +OP4 E031DF 0 +OP4 E031E0 0 +OP4 E031E1 0 +OP4 E031E2 0 +OP4 E031E3 0 +OP4 E031E4 0 +OP4 E031E5 0 +OP4 E031E6 0 +OP4 E031E7 0 +OP4 E031E8 0 +OP4 E031E9 0 +OP4 E031EA 0 +OP4 E031EB 0 +OP4 E031EC 0 +OP4 E031ED 0 +OP4 E031EE 0 +OP4 E031EF 0 +OP4 E031F0 0 +OP4 E031F1 0 +OP4 E031F2 0 +OP4 E031F3 0 +OP4 E031F4 0 +OP4 E031F5 0 +OP4 E031F6 0 +OP4 E031F7 0 +OP4 E031F8 0 +OP4 E031F9 0 +OP4 E031FA 0 +OP4 E031FB 0 +OP4 E031FC 0 +OP4 E031FD 0 +OP4 E031FE 0 +OP4 E031FF 0 +OP4 E03200 0 +OP4 E03201 0 +OP4 E03202 0 +OP4 E03203 0 +OP4 E03204 0 +OP4 E03205 0 +OP4 E03206 0 +OP4 E03207 0 +OP4 E03208 0 +OP4 E03209 0 +OP4 E0320A 0 +OP4 E0320B 0 +OP4 E0320C 0 +OP4 E0320D 0 +OP4 E0320E 0 +OP4 E0320F 0 +OP4 E03210 0 +OP4 E03211 0 +OP4 E03212 0 +OP4 E03213 0 +OP4 E03214 0 +OP4 E03215 0 +OP4 E03216 0 +OP4 E03217 0 +OP4 E03218 0 +OP4 E03219 0 +OP4 E0321A 0 +OP4 E0321B 0 +OP4 E0321C 0 +OP4 E0321D 0 +OP4 E0321E 0 +OP4 E0321F 0 +OP4 E03220 0 +OP4 E03221 0 +OP4 E03222 0 +OP4 E03223 0 +OP4 E03224 0 +OP4 E03225 0 +OP4 E03226 0 +OP4 E03227 0 +OP4 E03228 0 +OP4 E03229 0 +OP4 E0322A 0 +OP4 E0322B 0 +OP4 E0322C 0 +OP4 E0322D 0 +OP4 E0322E 0 +OP4 E0322F 0 +OP4 E03230 0 +OP4 E03231 0 +OP4 E03232 0 +OP4 E03233 0 +OP4 E03234 0 +OP4 E03235 0 +OP4 E03236 0 +OP4 E03237 0 +OP4 E03238 0 +OP4 E03239 0 +OP4 E0323A 0 +OP4 E0323B 0 +OP4 E0323C 0 +OP4 E0323D 0 +OP4 E0323E 0 +OP4 E0323F 0 +OP4 E03240 0 +OP4 E03241 0 +OP4 E03242 0 +OP4 E03243 0 +OP4 E03244 0 +OP4 E03245 0 +OP4 E03246 0 +OP4 E03247 0 +OP4 E03248 0 +OP4 E03249 0 +OP4 E0324A 0 +OP4 E0324B 0 +OP4 E0324C 0 +OP4 E0324D 0 +OP4 E0324E 0 +OP4 E0324F 0 +OP4 E03250 0 +OP4 E03251 0 +OP4 E03252 0 +OP4 E03253 0 +OP4 E03254 0 +OP4 E03255 0 +OP4 E03256 0 +OP4 E03257 0 +OP4 E03258 0 +OP4 E03259 0 +OP4 E0325A 0 +OP4 E0325B 0 +OP4 E0325C 0 +OP4 E0325D 0 +OP4 E0325E 0 +OP4 E0325F 0 +OP4 E03260 0 +OP4 E03261 0 +OP4 E03262 0 +OP4 E03263 0 +OP4 E03264 0 +OP4 E03265 0 +OP4 E03266 0 +OP4 E03267 0 +OP4 E03268 0 +OP4 E03269 0 +OP4 E0326A 0 +OP4 E0326B 0 +OP4 E0326C 0 +OP4 E0326D 0 +OP4 E0326E 0 +OP4 E0326F 0 +OP4 E03270 0 +OP4 E03271 0 +OP4 E03272 0 +OP4 E03273 0 +OP4 E03274 0 +OP4 E03275 0 +OP4 E03276 0 +OP4 E03277 0 +OP4 E03278 0 +OP4 E03279 0 +OP4 E0327A 0 +OP4 E0327B 0 +OP4 E0327C 0 +OP4 E0327D 0 +OP4 E0327E 0 +OP4 E0327F 0 +OP4 E03280 0 +OP4 E03281 0 +OP4 E03282 0 +OP4 E03283 0 +OP4 E03284 0 +OP4 E03285 0 +OP4 E03286 0 +OP4 E03287 0 +OP4 E03288 0 +OP4 E03289 0 +OP4 E0328A 0 +OP4 E0328B 0 +OP4 E0328C 0 +OP4 E0328D 0 +OP4 E0328E 0 +OP4 E0328F 0 +OP4 E03290 0 +OP4 E03291 0 +OP4 E03292 0 +OP4 E03293 0 +OP4 E03294 0 +OP4 E03295 0 +OP4 E03296 0 +OP4 E03297 0 +OP4 E03298 0 +OP4 E03299 0 +OP4 E0329A 0 +OP4 E0329B 0 +OP4 E0329C 0 +OP4 E0329D 0 +OP4 E0329E 0 +OP4 E0329F 0 +OP4 E032A0 0 +OP4 E032A1 0 +OP4 E032A2 0 +OP4 E032A3 0 +OP4 E032A4 0 +OP4 E032A5 0 +OP4 E032A6 0 +OP4 E032A7 0 +OP4 E032A8 0 +OP4 E032A9 0 +OP4 E032AA 0 +OP4 E032AB 0 +OP4 E032AC 0 +OP4 E032AD 0 +OP4 E032AE 0 +OP4 E032AF 0 +OP4 E032B0 0 +OP4 E032B1 0 +OP4 E032B2 0 +OP4 E032B3 0 +OP4 E032B4 0 +OP4 E032B5 0 +OP4 E032B6 0 +OP4 E032B7 0 +OP4 E032B8 0 +OP4 E032B9 0 +OP4 E032BA 0 +OP4 E032BB 0 +OP4 E032BC 0 +OP4 E032BD 0 +OP4 E032BE 0 +OP4 E032BF 0 +OP4 E032C0 0 +OP4 E032C1 0 +OP4 E032C2 0 +OP4 E032C3 0 +OP4 E032C4 0 +OP4 E032C5 0 +OP4 E032C6 0 +OP4 E032C7 0 +OP4 E032C8 0 +OP4 E032C9 0 +OP4 E032CA 0 +OP4 E032CB 0 +OP4 E032CC 0 +OP4 E032CD 0 +OP4 E032CE 0 +OP4 E032CF 0 +OP4 E032D0 0 +OP4 E032D1 0 +OP4 E032D2 0 +OP4 E032D3 0 +OP4 E032D4 0 +OP4 E032D5 0 +OP4 E032D6 0 +OP4 E032D7 0 +OP4 E032D8 0 +OP4 E032D9 0 +OP4 E032DA 0 +OP4 E032DB 0 +OP4 E032DC 0 +OP4 E032DD 0 +OP4 E032DE 0 +OP4 E032DF 0 +OP4 E032E0 0 +OP4 E032E1 0 +OP4 E032E2 0 +OP4 E032E3 0 +OP4 E032E4 0 +OP4 E032E5 0 +OP4 E032E6 0 +OP4 E032E7 0 +OP4 E032E8 0 +OP4 E032E9 0 +OP4 E032EA 0 +OP4 E032EB 0 +OP4 E032EC 0 +OP4 E032ED 0 +OP4 E032EE 0 +OP4 E032EF 0 +OP4 E032F0 0 +OP4 E032F1 0 +OP4 E032F2 0 +OP4 E032F3 0 +OP4 E032F4 0 +OP4 E032F5 0 +OP4 E032F6 0 +OP4 E032F7 0 +OP4 E032F8 0 +OP4 E032F9 0 +OP4 E032FA 0 +OP4 E032FB 0 +OP4 E032FC 0 +OP4 E032FD 0 +OP4 E032FE 0 +OP4 E032FF 0 +OP4 E03300 0 +OP4 E03301 0 +OP4 E03302 0 +OP4 E03303 0 +OP4 E03304 0 +OP4 E03305 0 +OP4 E03306 0 +OP4 E03307 0 +OP4 E03308 0 +OP4 E03309 0 +OP4 E0330A 0 +OP4 E0330B 0 +OP4 E0330C 0 +OP4 E0330D 0 +OP4 E0330E 0 +OP4 E0330F 0 +OP4 E03310 0 +OP4 E03311 0 +OP4 E03312 0 +OP4 E03313 0 +OP4 E03314 0 +OP4 E03315 0 +OP4 E03316 0 +OP4 E03317 0 +OP4 E03318 0 +OP4 E03319 0 +OP4 E0331A 0 +OP4 E0331B 0 +OP4 E0331C 0 +OP4 E0331D 0 +OP4 E0331E 0 +OP4 E0331F 0 +OP4 E03320 0 +OP4 E03321 0 +OP4 E03322 0 +OP4 E03323 0 +OP4 E03324 0 +OP4 E03325 0 +OP4 E03326 0 +OP4 E03327 0 +OP4 E03328 0 +OP4 E03329 0 +OP4 E0332A 0 +OP4 E0332B 0 +OP4 E0332C 0 +OP4 E0332D 0 +OP4 E0332E 0 +OP4 E0332F 0 +OP4 E03330 0 +OP4 E03331 0 +OP4 E03332 0 +OP4 E03333 0 +OP4 E03334 0 +OP4 E03335 0 +OP4 E03336 0 +OP4 E03337 0 +OP4 E03338 0 +OP4 E03339 0 +OP4 E0333A 0 +OP4 E0333B 0 +OP4 E0333C 0 +OP4 E0333D 0 +OP4 E0333E 0 +OP4 E0333F 0 +OP4 E03340 0 +OP4 E03341 0 +OP4 E03342 0 +OP4 E03343 0 +OP4 E03344 0 +OP4 E03345 0 +OP4 E03346 0 +OP4 E03347 0 +OP4 E03348 0 +OP4 E03349 0 +OP4 E0334A 0 +OP4 E0334B 0 +OP4 E0334C 0 +OP4 E0334D 0 +OP4 E0334E 0 +OP4 E0334F 0 +OP4 E03350 0 +OP4 E03351 0 +OP4 E03352 0 +OP4 E03353 0 +OP4 E03354 0 +OP4 E03355 0 +OP4 E03356 0 +OP4 E03357 0 +OP4 E03358 0 +OP4 E03359 0 +OP4 E0335A 0 +OP4 E0335B 0 +OP4 E0335C 0 +OP4 E0335D 0 +OP4 E0335E 0 +OP4 E0335F 0 +OP4 E03360 0 +OP4 E03361 0 +OP4 E03362 0 +OP4 E03363 0 +OP4 E03364 0 +OP4 E03365 0 +OP4 E03366 0 +OP4 E03367 0 +OP4 E03368 0 +OP4 E03369 0 +OP4 E0336A 0 +OP4 E0336B 0 +OP4 E0336C 0 +OP4 E0336D 0 +OP4 E0336E 0 +OP4 E0336F 0 +OP4 E03370 0 +OP4 E03371 0 +OP4 E03372 0 +OP4 E03373 0 +OP4 E03374 0 +OP4 E03375 0 +OP4 E03376 0 +OP4 E03377 0 +OP4 E03378 0 +OP4 E03379 0 +OP4 E0337A 0 +OP4 E0337B 0 +OP4 E0337C 0 +OP4 E0337D 0 +OP4 E0337E 0 +OP4 E0337F 0 +OP4 E03380 0 +OP4 E03381 0 +OP4 E03382 0 +OP4 E03383 0 +OP4 E03384 0 +OP4 E03385 0 +OP4 E03386 0 +OP4 E03387 0 +OP4 E03388 0 +OP4 E03389 0 +OP4 E0338A 0 +OP4 E0338B 0 +OP4 E0338C 0 +OP4 E0338D 0 +OP4 E0338E 0 +OP4 E0338F 0 +OP4 E03390 0 +OP4 E03391 0 +OP4 E03392 0 +OP4 E03393 0 +OP4 E03394 0 +OP4 E03395 0 +OP4 E03396 0 +OP4 E03397 0 +OP4 E03398 0 +OP4 E03399 0 +OP4 E0339A 0 +OP4 E0339B 0 +OP4 E0339C 0 +OP4 E0339D 0 +OP4 E0339E 0 +OP4 E0339F 0 +OP4 E033A0 0 +OP4 E033A1 0 +OP4 E033A2 0 +OP4 E033A3 0 +OP4 E033A4 0 +OP4 E033A5 0 +OP4 E033A6 0 +OP4 E033A7 0 +OP4 E033A8 0 +OP4 E033A9 0 +OP4 E033AA 0 +OP4 E033AB 0 +OP4 E033AC 0 +OP4 E033AD 0 +OP4 E033AE 0 +OP4 E033AF 0 +OP4 E033B0 0 +OP4 E033B1 0 +OP4 E033B2 0 +OP4 E033B3 0 +OP4 E033B4 0 +OP4 E033B5 0 +OP4 E033B6 0 +OP4 E033B7 0 +OP4 E033B8 0 +OP4 E033B9 0 +OP4 E033BA 0 +OP4 E033BB 0 +OP4 E033BC 0 +OP4 E033BD 0 +OP4 E033BE 0 +OP4 E033BF 0 +OP4 E033C0 0 +OP4 E033C1 0 +OP4 E033C2 0 +OP4 E033C3 0 +OP4 E033C4 0 +OP4 E033C5 0 +OP4 E033C6 0 +OP4 E033C7 0 +OP4 E033C8 0 +OP4 E033C9 0 +OP4 E033CA 0 +OP4 E033CB 0 +OP4 E033CC 0 +OP4 E033CD 0 +OP4 E033CE 0 +OP4 E033CF 0 +OP4 E033D0 0 +OP4 E033D1 0 +OP4 E033D2 0 +OP4 E033D3 0 +OP4 E033D4 0 +OP4 E033D5 0 +OP4 E033D6 0 +OP4 E033D7 0 +OP4 E033D8 0 +OP4 E033D9 0 +OP4 E033DA 0 +OP4 E033DB 0 +OP4 E033DC 0 +OP4 E033DD 0 +OP4 E033DE 0 +OP4 E033DF 0 +OP4 E033E0 0 +OP4 E033E1 0 +OP4 E033E2 0 +OP4 E033E3 0 +OP4 E033E4 0 +OP4 E033E5 0 +OP4 E033E6 0 +OP4 E033E7 0 +OP4 E033E8 0 +OP4 E033E9 0 +OP4 E033EA 0 +OP4 E033EB 0 +OP4 E033EC 0 +OP4 E033ED 0 +OP4 E033EE 0 +OP4 E033EF 0 +OP4 E033F0 0 +OP4 E033F1 0 +OP4 E033F2 0 +OP4 E033F3 0 +OP4 E033F4 0 +OP4 E033F5 0 +OP4 E033F6 0 +OP4 E033F7 0 +OP4 E033F8 0 +OP4 E033F9 0 +OP4 E033FA 0 +OP4 E033FB 0 +OP4 E033FC 0 +OP4 E033FD 0 +OP4 E033FE 0 +OP4 E033FF 0 +OP4 E03400 0 +OP4 E03401 0 +OP4 E03402 0 +OP4 E03403 0 +OP4 E03404 0 +OP4 E03405 0 +OP4 E03406 0 +OP4 E03407 0 +OP4 E03408 0 +OP4 E03409 0 +OP4 E0340A 0 +OP4 E0340B 0 +OP4 E0340C 0 +OP4 E0340D 0 +OP4 E0340E 0 +OP4 E0340F 0 +OP4 E03410 0 +OP4 E03411 0 +OP4 E03412 0 +OP4 E03413 0 +OP4 E03414 0 +OP4 E03415 0 +OP4 E03416 0 +OP4 E03417 0 +OP4 E03418 0 +OP4 E03419 0 +OP4 E0341A 0 +OP4 E0341B 0 +OP4 E0341C 0 +OP4 E0341D 0 +OP4 E0341E 0 +OP4 E0341F 0 +OP4 E03420 0 +OP4 E03421 0 +OP4 E03422 0 +OP4 E03423 0 +OP4 E03424 0 +OP4 E03425 0 +OP4 E03426 0 +OP4 E03427 0 +OP4 E03428 0 +OP4 E03429 0 +OP4 E0342A 0 +OP4 E0342B 0 +OP4 E0342C 0 +OP4 E0342D 0 +OP4 E0342E 0 +OP4 E0342F 0 +OP4 E03430 0 +OP4 E03431 0 +OP4 E03432 0 +OP4 E03433 0 +OP4 E03434 0 +OP4 E03435 0 +OP4 E03436 0 +OP4 E03437 0 +OP4 E03438 0 +OP4 E03439 0 +OP4 E0343A 0 +OP4 E0343B 0 +OP4 E0343C 0 +OP4 E0343D 0 +OP4 E0343E 0 +OP4 E0343F 0 +OP4 E03440 0 +OP4 E03441 0 +OP4 E03442 0 +OP4 E03443 0 +OP4 E03444 0 +OP4 E03445 0 +OP4 E03446 0 +OP4 E03447 0 +OP4 E03448 0 +OP4 E03449 0 +OP4 E0344A 0 +OP4 E0344B 0 +OP4 E0344C 0 +OP4 E0344D 0 +OP4 E0344E 0 +OP4 E0344F 0 +OP4 E03450 0 +OP4 E03451 0 +OP4 E03452 0 +OP4 E03453 0 +OP4 E03454 0 +OP4 E03455 0 +OP4 E03456 0 +OP4 E03457 0 +OP4 E03458 0 +OP4 E03459 0 +OP4 E0345A 0 +OP4 E0345B 0 +OP4 E0345C 0 +OP4 E0345D 0 +OP4 E0345E 0 +OP4 E0345F 0 +OP4 E03460 0 +OP4 E03461 0 +OP4 E03462 0 +OP4 E03463 0 +OP4 E03464 0 +OP4 E03465 0 +OP4 E03466 0 +OP4 E03467 0 +OP4 E03468 0 +OP4 E03469 0 +OP4 E0346A 0 +OP4 E0346B 0 +OP4 E0346C 0 +OP4 E0346D 0 +OP4 E0346E 0 +OP4 E0346F 0 +OP4 E03470 0 +OP4 E03471 0 +OP4 E03472 0 +OP4 E03473 0 +OP4 E03474 0 +OP4 E03475 0 +OP4 E03476 0 +OP4 E03477 0 +OP4 E03478 0 +OP4 E03479 0 +OP4 E0347A 0 +OP4 E0347B 0 +OP4 E0347C 0 +OP4 E0347D 0 +OP4 E0347E 0 +OP4 E0347F 0 +OP4 E03480 0 +OP4 E03481 0 +OP4 E03482 0 +OP4 E03483 0 +OP4 E03484 0 +OP4 E03485 0 +OP4 E03486 0 +OP4 E03487 0 +OP4 E03488 0 +OP4 E03489 0 +OP4 E0348A 0 +OP4 E0348B 0 +OP4 E0348C 0 +OP4 E0348D 0 +OP4 E0348E 0 +OP4 E0348F 0 +OP4 E03490 0 +OP4 E03491 0 +OP4 E03492 0 +OP4 E03493 0 +OP4 E03494 0 +OP4 E03495 0 +OP4 E03496 0 +OP4 E03497 0 +OP4 E03498 0 +OP4 E03499 0 +OP4 E0349A 0 +OP4 E0349B 0 +OP4 E0349C 0 +OP4 E0349D 0 +OP4 E0349E 0 +OP4 E0349F 0 +OP4 E034A0 0 +OP4 E034A1 0 +OP4 E034A2 0 +OP4 E034A3 0 +OP4 E034A4 0 +OP4 E034A5 0 +OP4 E034A6 0 +OP4 E034A7 0 +OP4 E034A8 0 +OP4 E034A9 0 +OP4 E034AA 0 +OP4 E034AB 0 +OP4 E034AC 0 +OP4 E034AD 0 +OP4 E034AE 0 +OP4 E034AF 0 +OP4 E034B0 0 +OP4 E034B1 0 +OP4 E034B2 0 +OP4 E034B3 0 +OP4 E034B4 0 +OP4 E034B5 0 +OP4 E034B6 0 +OP4 E034B7 0 +OP4 E034B8 0 +OP4 E034B9 0 +OP4 E034BA 0 +OP4 E034BB 0 +OP4 E034BC 0 +OP4 E034BD 0 +OP4 E034BE 0 +OP4 E034BF 0 +OP4 E034C0 0 +OP4 E034C1 0 +OP4 E034C2 0 +OP4 E034C3 0 +OP4 E034C4 0 +OP4 E034C5 0 +OP4 E034C6 0 +OP4 E034C7 0 +OP4 E034C8 0 +OP4 E034C9 0 +OP4 E034CA 0 +OP4 E034CB 0 +OP4 E034CC 0 +OP4 E034CD 0 +OP4 E034CE 0 +OP4 E034CF 0 +OP4 E034D0 0 +OP4 E034D1 0 +OP4 E034D2 0 +OP4 E034D3 0 +OP4 E034D4 0 +OP4 E034D5 0 +OP4 E034D6 0 +OP4 E034D7 0 +OP4 E034D8 0 +OP4 E034D9 0 +OP4 E034DA 0 +OP4 E034DB 0 +OP4 E034DC 0 +OP4 E034DD 0 +OP4 E034DE 0 +OP4 E034DF 0 +OP4 E034E0 0 +OP4 E034E1 0 +OP4 E034E2 0 +OP4 E034E3 0 +OP4 E034E4 0 +OP4 E034E5 0 +OP4 E034E6 0 +OP4 E034E7 0 +OP4 E034E8 0 +OP4 E034E9 0 +OP4 E034EA 0 +OP4 E034EB 0 +OP4 E034EC 0 +OP4 E034ED 0 +OP4 E034EE 0 +OP4 E034EF 0 +OP4 E034F0 0 +OP4 E034F1 0 +OP4 E034F2 0 +OP4 E034F3 0 +OP4 E034F4 0 +OP4 E034F5 0 +OP4 E034F6 0 +OP4 E034F7 0 +OP4 E034F8 0 +OP4 E034F9 0 +OP4 E034FA 0 +OP4 E034FB 0 +OP4 E034FC 0 +OP4 E034FD 0 +OP4 E034FE 0 +OP4 E034FF 0 +OP4 E03500 0 +OP4 E03501 0 +OP4 E03502 0 +OP4 E03503 0 +OP4 E03504 0 +OP4 E03505 0 +OP4 E03506 0 +OP4 E03507 0 +OP4 E03508 0 +OP4 E03509 0 +OP4 E0350A 0 +OP4 E0350B 0 +OP4 E0350C 0 +OP4 E0350D 0 +OP4 E0350E 0 +OP4 E0350F 0 +OP4 E03510 0 +OP4 E03511 0 +OP4 E03512 0 +OP4 E03513 0 +OP4 E03514 0 +OP4 E03515 0 +OP4 E03516 0 +OP4 E03517 0 +OP4 E03518 0 +OP4 E03519 0 +OP4 E0351A 0 +OP4 E0351B 0 +OP4 E0351C 0 +OP4 E0351D 0 +OP4 E0351E 0 +OP4 E0351F 0 +OP4 E03520 0 +OP4 E03521 0 +OP4 E03522 0 +OP4 E03523 0 +OP4 E03524 0 +OP4 E03525 0 +OP4 E03526 0 +OP4 E03527 0 +OP4 E03528 0 +OP4 E03529 0 +OP4 E0352A 0 +OP4 E0352B 0 +OP4 E0352C 0 +OP4 E0352D 0 +OP4 E0352E 0 +OP4 E0352F 0 +OP4 E03530 0 +OP4 E03531 0 +OP4 E03532 0 +OP4 E03533 0 +OP4 E03534 0 +OP4 E03535 0 +OP4 E03536 0 +OP4 E03537 0 +OP4 E03538 0 +OP4 E03539 0 +OP4 E0353A 0 +OP4 E0353B 0 +OP4 E0353C 0 +OP4 E0353D 0 +OP4 E0353E 0 +OP4 E0353F 0 +OP4 E03540 0 +OP4 E03541 0 +OP4 E03542 0 +OP4 E03543 0 +OP4 E03544 0 +OP4 E03545 0 +OP4 E03546 0 +OP4 E03547 0 +OP4 E03548 0 +OP4 E03549 0 +OP4 E0354A 0 +OP4 E0354B 0 +OP4 E0354C 0 +OP4 E0354D 0 +OP4 E0354E 0 +OP4 E0354F 0 +OP4 E03550 0 +OP4 E03551 0 +OP4 E03552 0 +OP4 E03553 0 +OP4 E03554 0 +OP4 E03555 0 +OP4 E03556 0 +OP4 E03557 0 +OP4 E03558 0 +OP4 E03559 0 +OP4 E0355A 0 +OP4 E0355B 0 +OP4 E0355C 0 +OP4 E0355D 0 +OP4 E0355E 0 +OP4 E0355F 0 +OP4 E03560 0 +OP4 E03561 0 +OP4 E03562 0 +OP4 E03563 0 +OP4 E03564 0 +OP4 E03565 0 +OP4 E03566 0 +OP4 E03567 0 +OP4 E03568 0 +OP4 E03569 0 +OP4 E0356A 0 +OP4 E0356B 0 +OP4 E0356C 0 +OP4 E0356D 0 +OP4 E0356E 0 +OP4 E0356F 0 +OP4 E03570 0 +OP4 E03571 0 +OP4 E03572 0 +OP4 E03573 0 +OP4 E03574 0 +OP4 E03575 0 +OP4 E03576 0 +OP4 E03577 0 +OP4 E03578 0 +OP4 E03579 0 +OP4 E0357A 0 +OP4 E0357B 0 +OP4 E0357C 0 +OP4 E0357D 0 +OP4 E0357E 0 +OP4 E0357F 0 +OP4 E03580 0 +OP4 E03581 0 +OP4 E03582 0 +OP4 E03583 0 +OP4 E03584 0 +OP4 E03585 0 +OP4 E03586 0 +OP4 E03587 0 +OP4 E03588 0 +OP4 E03589 0 +OP4 E0358A 0 +OP4 E0358B 0 +OP4 E0358C 0 +OP4 E0358D 0 +OP4 E0358E 0 +OP4 E0358F 0 +OP4 E03590 0 +OP4 E03591 0 +OP4 E03592 0 +OP4 E03593 0 +OP4 E03594 0 +OP4 E03595 0 +OP4 E03596 0 +OP4 E03597 0 +OP4 E03598 0 +OP4 E03599 0 +OP4 E0359A 0 +OP4 E0359B 0 +OP4 E0359C 0 +OP4 E0359D 0 +OP4 E0359E 0 +OP4 E0359F 0 +OP4 E035A0 0 +OP4 E035A1 0 +OP4 E035A2 0 +OP4 E035A3 0 +OP4 E035A4 0 +OP4 E035A5 0 +OP4 E035A6 0 +OP4 E035A7 0 +OP4 E035A8 0 +OP4 E035A9 0 +OP4 E035AA 0 +OP4 E035AB 0 +OP4 E035AC 0 +OP4 E035AD 0 +OP4 E035AE 0 +OP4 E035AF 0 +OP4 E035B0 0 +OP4 E035B1 0 +OP4 E035B2 0 +OP4 E035B3 0 +OP4 E035B4 0 +OP4 E035B5 0 +OP4 E035B6 0 +OP4 E035B7 0 +OP4 E035B8 0 +OP4 E035B9 0 +OP4 E035BA 0 +OP4 E035BB 0 +OP4 E035BC 0 +OP4 E035BD 0 +OP4 E035BE 0 +OP4 E035BF 0 +OP4 E035C0 0 +OP4 E035C1 0 +OP4 E035C2 0 +OP4 E035C3 0 +OP4 E035C4 0 +OP4 E035C5 0 +OP4 E035C6 0 +OP4 E035C7 0 +OP4 E035C8 0 +OP4 E035C9 0 +OP4 E035CA 0 +OP4 E035CB 0 +OP4 E035CC 0 +OP4 E035CD 0 +OP4 E035CE 0 +OP4 E035CF 0 +OP4 E035D0 0 +OP4 E035D1 0 +OP4 E035D2 0 +OP4 E035D3 0 +OP4 E035D4 0 +OP4 E035D5 0 +OP4 E035D6 0 +OP4 E035D7 0 +OP4 E035D8 0 +OP4 E035D9 0 +OP4 E035DA 0 +OP4 E035DB 0 +OP4 E035DC 0 +OP4 E035DD 0 +OP4 E035DE 0 +OP4 E035DF 0 +OP4 E035E0 0 +OP4 E035E1 0 +OP4 E035E2 0 +OP4 E035E3 0 +OP4 E035E4 0 +OP4 E035E5 0 +OP4 E035E6 0 +OP4 E035E7 0 +OP4 E035E8 0 +OP4 E035E9 0 +OP4 E035EA 0 +OP4 E035EB 0 +OP4 E035EC 0 +OP4 E035ED 0 +OP4 E035EE 0 +OP4 E035EF 0 +OP4 E035F0 0 +OP4 E035F1 0 +OP4 E035F2 0 +OP4 E035F3 0 +OP4 E035F4 0 +OP4 E035F5 0 +OP4 E035F6 0 +OP4 E035F7 0 +OP4 E035F8 0 +OP4 E035F9 0 +OP4 E035FA 0 +OP4 E035FB 0 +OP4 E035FC 0 +OP4 E035FD 0 +OP4 E035FE 0 +OP4 E035FF 0 +OP4 E03600 0 +OP4 E03601 0 +OP4 E03602 0 +OP4 E03603 0 +OP4 E03604 0 +OP4 E03605 0 +OP4 E03606 0 +OP4 E03607 0 +OP4 E03608 0 +OP4 E03609 0 +OP4 E0360A 0 +OP4 E0360B 0 +OP4 E0360C 0 +OP4 E0360D 0 +OP4 E0360E 0 +OP4 E0360F 0 +OP4 E03610 0 +OP4 E03611 0 +OP4 E03612 0 +OP4 E03613 0 +OP4 E03614 0 +OP4 E03615 0 +OP4 E03616 0 +OP4 E03617 0 +OP4 E03618 0 +OP4 E03619 0 +OP4 E0361A 0 +OP4 E0361B 0 +OP4 E0361C 0 +OP4 E0361D 0 +OP4 E0361E 0 +OP4 E0361F 0 +OP4 E03620 0 +OP4 E03621 0 +OP4 E03622 0 +OP4 E03623 0 +OP4 E03624 0 +OP4 E03625 0 +OP4 E03626 0 +OP4 E03627 0 +OP4 E03628 0 +OP4 E03629 0 +OP4 E0362A 0 +OP4 E0362B 0 +OP4 E0362C 0 +OP4 E0362D 0 +OP4 E0362E 0 +OP4 E0362F 0 +OP4 E03630 0 +OP4 E03631 0 +OP4 E03632 0 +OP4 E03633 0 +OP4 E03634 0 +OP4 E03635 0 +OP4 E03636 0 +OP4 E03637 0 +OP4 E03638 0 +OP4 E03639 0 +OP4 E0363A 0 +OP4 E0363B 0 +OP4 E0363C 0 +OP4 E0363D 0 +OP4 E0363E 0 +OP4 E0363F 0 +OP4 E03640 0 +OP4 E03641 0 +OP4 E03642 0 +OP4 E03643 0 +OP4 E03644 0 +OP4 E03645 0 +OP4 E03646 0 +OP4 E03647 0 +OP4 E03648 0 +OP4 E03649 0 +OP4 E0364A 0 +OP4 E0364B 0 +OP4 E0364C 0 +OP4 E0364D 0 +OP4 E0364E 0 +OP4 E0364F 0 +OP4 E03650 0 +OP4 E03651 0 +OP4 E03652 0 +OP4 E03653 0 +OP4 E03654 0 +OP4 E03655 0 +OP4 E03656 0 +OP4 E03657 0 +OP4 E03658 0 +OP4 E03659 0 +OP4 E0365A 0 +OP4 E0365B 0 +OP4 E0365C 0 +OP4 E0365D 0 +OP4 E0365E 0 +OP4 E0365F 0 +OP4 E03660 0 +OP4 E03661 0 +OP4 E03662 0 +OP4 E03663 0 +OP4 E03664 0 +OP4 E03665 0 +OP4 E03666 0 +OP4 E03667 0 +OP4 E03668 0 +OP4 E03669 0 +OP4 E0366A 0 +OP4 E0366B 0 +OP4 E0366C 0 +OP4 E0366D 0 +OP4 E0366E 0 +OP4 E0366F 0 +OP4 E03670 0 +OP4 E03671 0 +OP4 E03672 0 +OP4 E03673 0 +OP4 E03674 0 +OP4 E03675 0 +OP4 E03676 0 +OP4 E03677 0 +OP4 E03678 0 +OP4 E03679 0 +OP4 E0367A 0 +OP4 E0367B 0 +OP4 E0367C 0 +OP4 E0367D 0 +OP4 E0367E 0 +OP4 E0367F 0 +OP4 E03680 0 +OP4 E03681 0 +OP4 E03682 0 +OP4 E03683 0 +OP4 E03684 0 +OP4 E03685 0 +OP4 E03686 0 +OP4 E03687 0 +OP4 E03688 0 +OP4 E03689 0 +OP4 E0368A 0 +OP4 E0368B 0 +OP4 E0368C 0 +OP4 E0368D 0 +OP4 E0368E 0 +OP4 E0368F 0 +OP4 E03690 0 +OP4 E03691 0 +OP4 E03692 0 +OP4 E03693 0 +OP4 E03694 0 +OP4 E03695 0 +OP4 E03696 0 +OP4 E03697 0 +OP4 E03698 0 +OP4 E03699 0 +OP4 E0369A 0 +OP4 E0369B 0 +OP4 E0369C 0 +OP4 E0369D 0 +OP4 E0369E 0 +OP4 E0369F 0 +OP4 E036A0 0 +OP4 E036A1 0 +OP4 E036A2 0 +OP4 E036A3 0 +OP4 E036A4 0 +OP4 E036A5 0 +OP4 E036A6 0 +OP4 E036A7 0 +OP4 E036A8 0 +OP4 E036A9 0 +OP4 E036AA 0 +OP4 E036AB 0 +OP4 E036AC 0 +OP4 E036AD 0 +OP4 E036AE 0 +OP4 E036AF 0 +OP4 E036B0 0 +OP4 E036B1 0 +OP4 E036B2 0 +OP4 E036B3 0 +OP4 E036B4 0 +OP4 E036B5 0 +OP4 E036B6 0 +OP4 E036B7 0 +OP4 E036B8 0 +OP4 E036B9 0 +OP4 E036BA 0 +OP4 E036BB 0 +OP4 E036BC 0 +OP4 E036BD 0 +OP4 E036BE 0 +OP4 E036BF 0 +OP4 E036C0 0 +OP4 E036C1 0 +OP4 E036C2 0 +OP4 E036C3 0 +OP4 E036C4 0 +OP4 E036C5 0 +OP4 E036C6 0 +OP4 E036C7 0 +OP4 E036C8 0 +OP4 E036C9 0 +OP4 E036CA 0 +OP4 E036CB 0 +OP4 E036CC 0 +OP4 E036CD 0 +OP4 E036CE 0 +OP4 E036CF 0 +OP4 E036D0 0 +OP4 E036D1 0 +OP4 E036D2 0 +OP4 E036D3 0 +OP4 E036D4 0 +OP4 E036D5 0 +OP4 E036D6 0 +OP4 E036D7 0 +OP4 E036D8 0 +OP4 E036D9 0 +OP4 E036DA 0 +OP4 E036DB 0 +OP4 E036DC 0 +OP4 E036DD 0 +OP4 E036DE 0 +OP4 E036DF 0 +OP4 E036E0 0 +OP4 E036E1 0 +OP4 E036E2 0 +OP4 E036E3 0 +OP4 E036E4 0 +OP4 E036E5 0 +OP4 E036E6 0 +OP4 E036E7 0 +OP4 E036E8 0 +OP4 E036E9 0 +OP4 E036EA 0 +OP4 E036EB 0 +OP4 E036EC 0 +OP4 E036ED 0 +OP4 E036EE 0 +OP4 E036EF 0 +OP4 E036F0 0 +OP4 E036F1 0 +OP4 E036F2 0 +OP4 E036F3 0 +OP4 E036F4 0 +OP4 E036F5 0 +OP4 E036F6 0 +OP4 E036F7 0 +OP4 E036F8 0 +OP4 E036F9 0 +OP4 E036FA 0 +OP4 E036FB 0 +OP4 E036FC 0 +OP4 E036FD 0 +OP4 E036FE 0 +OP4 E036FF 0 +OP4 E03700 0 +OP4 E03701 0 +OP4 E03702 0 +OP4 E03703 0 +OP4 E03704 0 +OP4 E03705 0 +OP4 E03706 0 +OP4 E03707 0 +OP4 E03708 0 +OP4 E03709 0 +OP4 E0370A 0 +OP4 E0370B 0 +OP4 E0370C 0 +OP4 E0370D 0 +OP4 E0370E 0 +OP4 E0370F 0 +OP4 E03710 0 +OP4 E03711 0 +OP4 E03712 0 +OP4 E03713 0 +OP4 E03714 0 +OP4 E03715 0 +OP4 E03716 0 +OP4 E03717 0 +OP4 E03718 0 +OP4 E03719 0 +OP4 E0371A 0 +OP4 E0371B 0 +OP4 E0371C 0 +OP4 E0371D 0 +OP4 E0371E 0 +OP4 E0371F 0 +OP4 E03720 0 +OP4 E03721 0 +OP4 E03722 0 +OP4 E03723 0 +OP4 E03724 0 +OP4 E03725 0 +OP4 E03726 0 +OP4 E03727 0 +OP4 E03728 0 +OP4 E03729 0 +OP4 E0372A 0 +OP4 E0372B 0 +OP4 E0372C 0 +OP4 E0372D 0 +OP4 E0372E 0 +OP4 E0372F 0 +OP4 E03730 0 +OP4 E03731 0 +OP4 E03732 0 +OP4 E03733 0 +OP4 E03734 0 +OP4 E03735 0 +OP4 E03736 0 +OP4 E03737 0 +OP4 E03738 0 +OP4 E03739 0 +OP4 E0373A 0 +OP4 E0373B 0 +OP4 E0373C 0 +OP4 E0373D 0 +OP4 E0373E 0 +OP4 E0373F 0 +OP4 E03740 0 +OP4 E03741 0 +OP4 E03742 0 +OP4 E03743 0 +OP4 E03744 0 +OP4 E03745 0 +OP4 E03746 0 +OP4 E03747 0 +OP4 E03748 0 +OP4 E03749 0 +OP4 E0374A 0 +OP4 E0374B 0 +OP4 E0374C 0 +OP4 E0374D 0 +OP4 E0374E 0 +OP4 E0374F 0 +OP4 E03750 0 +OP4 E03751 0 +OP4 E03752 0 +OP4 E03753 0 +OP4 E03754 0 +OP4 E03755 0 +OP4 E03756 0 +OP4 E03757 0 +OP4 E03758 0 +OP4 E03759 0 +OP4 E0375A 0 +OP4 E0375B 0 +OP4 E0375C 0 +OP4 E0375D 0 +OP4 E0375E 0 +OP4 E0375F 0 +OP4 E03760 0 +OP4 E03761 0 +OP4 E03762 0 +OP4 E03763 0 +OP4 E03764 0 +OP4 E03765 0 +OP4 E03766 0 +OP4 E03767 0 +OP4 E03768 0 +OP4 E03769 0 +OP4 E0376A 0 +OP4 E0376B 0 +OP4 E0376C 0 +OP4 E0376D 0 +OP4 E0376E 0 +OP4 E0376F 0 +OP4 E03770 0 +OP4 E03771 0 +OP4 E03772 0 +OP4 E03773 0 +OP4 E03774 0 +OP4 E03775 0 +OP4 E03776 0 +OP4 E03777 0 +OP4 E03778 0 +OP4 E03779 0 +OP4 E0377A 0 +OP4 E0377B 0 +OP4 E0377C 0 +OP4 E0377D 0 +OP4 E0377E 0 +OP4 E0377F 0 +OP4 E03780 0 +OP4 E03781 0 +OP4 E03782 0 +OP4 E03783 0 +OP4 E03784 0 +OP4 E03785 0 +OP4 E03786 0 +OP4 E03787 0 +OP4 E03788 0 +OP4 E03789 0 +OP4 E0378A 0 +OP4 E0378B 0 +OP4 E0378C 0 +OP4 E0378D 0 +OP4 E0378E 0 +OP4 E0378F 0 +OP4 E03790 0 +OP4 E03791 0 +OP4 E03792 0 +OP4 E03793 0 +OP4 E03794 0 +OP4 E03795 0 +OP4 E03796 0 +OP4 E03797 0 +OP4 E03798 0 +OP4 E03799 0 +OP4 E0379A 0 +OP4 E0379B 0 +OP4 E0379C 0 +OP4 E0379D 0 +OP4 E0379E 0 +OP4 E0379F 0 +OP4 E037A0 0 +OP4 E037A1 0 +OP4 E037A2 0 +OP4 E037A3 0 +OP4 E037A4 0 +OP4 E037A5 0 +OP4 E037A6 0 +OP4 E037A7 0 +OP4 E037A8 0 +OP4 E037A9 0 +OP4 E037AA 0 +OP4 E037AB 0 +OP4 E037AC 0 +OP4 E037AD 0 +OP4 E037AE 0 +OP4 E037AF 0 +OP4 E037B0 0 +OP4 E037B1 0 +OP4 E037B2 0 +OP4 E037B3 0 +OP4 E037B4 0 +OP4 E037B5 0 +OP4 E037B6 0 +OP4 E037B7 0 +OP4 E037B8 0 +OP4 E037B9 0 +OP4 E037BA 0 +OP4 E037BB 0 +OP4 E037BC 0 +OP4 E037BD 0 +OP4 E037BE 0 +OP4 E037BF 0 +OP4 E037C0 0 +OP4 E037C1 0 +OP4 E037C2 0 +OP4 E037C3 0 +OP4 E037C4 0 +OP4 E037C5 0 +OP4 E037C6 0 +OP4 E037C7 0 +OP4 E037C8 0 +OP4 E037C9 0 +OP4 E037CA 0 +OP4 E037CB 0 +OP4 E037CC 0 +OP4 E037CD 0 +OP4 E037CE 0 +OP4 E037CF 0 +OP4 E037D0 0 +OP4 E037D1 0 +OP4 E037D2 0 +OP4 E037D3 0 +OP4 E037D4 0 +OP4 E037D5 0 +OP4 E037D6 0 +OP4 E037D7 0 +OP4 E037D8 0 +OP4 E037D9 0 +OP4 E037DA 0 +OP4 E037DB 0 +OP4 E037DC 0 +OP4 E037DD 0 +OP4 E037DE 0 +OP4 E037DF 0 +OP4 E037E0 0 +OP4 E037E1 0 +OP4 E037E2 0 +OP4 E037E3 0 +OP4 E037E4 0 +OP4 E037E5 0 +OP4 E037E6 0 +OP4 E037E7 0 +OP4 E037E8 0 +OP4 E037E9 0 +OP4 E037EA 0 +OP4 E037EB 0 +OP4 E037EC 0 +OP4 E037ED 0 +OP4 E037EE 0 +OP4 E037EF 0 +OP4 E037F0 0 +OP4 E037F1 0 +OP4 E037F2 0 +OP4 E037F3 0 +OP4 E037F4 0 +OP4 E037F5 0 +OP4 E037F6 0 +OP4 E037F7 0 +OP4 E037F8 0 +OP4 E037F9 0 +OP4 E037FA 0 +OP4 E037FB 0 +OP4 E037FC 0 +OP4 E037FD 0 +OP4 E037FE 0 +OP4 E037FF 0 +OP4 E03800 0 +OP4 E03801 0 +OP4 E03802 0 +OP4 E03803 0 +OP4 E03804 0 +OP4 E03805 0 +OP4 E03806 0 +OP4 E03807 0 +OP4 E03808 0 +OP4 E03809 0 +OP4 E0380A 0 +OP4 E0380B 0 +OP4 E0380C 0 +OP4 E0380D 0 +OP4 E0380E 0 +OP4 E0380F 0 +OP4 E03810 0 +OP4 E03811 0 +OP4 E03812 0 +OP4 E03813 0 +OP4 E03814 0 +OP4 E03815 0 +OP4 E03816 0 +OP4 E03817 0 +OP4 E03818 0 +OP4 E03819 0 +OP4 E0381A 0 +OP4 E0381B 0 +OP4 E0381C 0 +OP4 E0381D 0 +OP4 E0381E 0 +OP4 E0381F 0 +OP4 E03820 0 +OP4 E03821 0 +OP4 E03822 0 +OP4 E03823 0 +OP4 E03824 0 +OP4 E03825 0 +OP4 E03826 0 +OP4 E03827 0 +OP4 E03828 0 +OP4 E03829 0 +OP4 E0382A 0 +OP4 E0382B 0 +OP4 E0382C 0 +OP4 E0382D 0 +OP4 E0382E 0 +OP4 E0382F 0 +OP4 E03830 0 +OP4 E03831 0 +OP4 E03832 0 +OP4 E03833 0 +OP4 E03834 0 +OP4 E03835 0 +OP4 E03836 0 +OP4 E03837 0 +OP4 E03838 0 +OP4 E03839 0 +OP4 E0383A 0 +OP4 E0383B 0 +OP4 E0383C 0 +OP4 E0383D 0 +OP4 E0383E 0 +OP4 E0383F 0 +OP4 E03840 0 +OP4 E03841 0 +OP4 E03842 0 +OP4 E03843 0 +OP4 E03844 0 +OP4 E03845 0 +OP4 E03846 0 +OP4 E03847 0 +OP4 E03848 0 +OP4 E03849 0 +OP4 E0384A 0 +OP4 E0384B 0 +OP4 E0384C 0 +OP4 E0384D 0 +OP4 E0384E 0 +OP4 E0384F 0 +OP4 E03850 0 +OP4 E03851 0 +OP4 E03852 0 +OP4 E03853 0 +OP4 E03854 0 +OP4 E03855 0 +OP4 E03856 0 +OP4 E03857 0 +OP4 E03858 0 +OP4 E03859 0 +OP4 E0385A 0 +OP4 E0385B 0 +OP4 E0385C 0 +OP4 E0385D 0 +OP4 E0385E 0 +OP4 E0385F 0 +OP4 E03860 0 +OP4 E03861 0 +OP4 E03862 0 +OP4 E03863 0 +OP4 E03864 0 +OP4 E03865 0 +OP4 E03866 0 +OP4 E03867 0 +OP4 E03868 0 +OP4 E03869 0 +OP4 E0386A 0 +OP4 E0386B 0 +OP4 E0386C 0 +OP4 E0386D 0 +OP4 E0386E 0 +OP4 E0386F 0 +OP4 E03870 0 +OP4 E03871 0 +OP4 E03872 0 +OP4 E03873 0 +OP4 E03874 0 +OP4 E03875 0 +OP4 E03876 0 +OP4 E03877 0 +OP4 E03878 0 +OP4 E03879 0 +OP4 E0387A 0 +OP4 E0387B 0 +OP4 E0387C 0 +OP4 E0387D 0 +OP4 E0387E 0 +OP4 E0387F 0 +OP4 E03880 0 +OP4 E03881 0 +OP4 E03882 0 +OP4 E03883 0 +OP4 E03884 0 +OP4 E03885 0 +OP4 E03886 0 +OP4 E03887 0 +OP4 E03888 0 +OP4 E03889 0 +OP4 E0388A 0 +OP4 E0388B 0 +OP4 E0388C 0 +OP4 E0388D 0 +OP4 E0388E 0 +OP4 E0388F 0 +OP4 E03890 0 +OP4 E03891 0 +OP4 E03892 0 +OP4 E03893 0 +OP4 E03894 0 +OP4 E03895 0 +OP4 E03896 0 +OP4 E03897 0 +OP4 E03898 0 +OP4 E03899 0 +OP4 E0389A 0 +OP4 E0389B 0 +OP4 E0389C 0 +OP4 E0389D 0 +OP4 E0389E 0 +OP4 E0389F 0 +OP4 E038A0 0 +OP4 E038A1 0 +OP4 E038A2 0 +OP4 E038A3 0 +OP4 E038A4 0 +OP4 E038A5 0 +OP4 E038A6 0 +OP4 E038A7 0 +OP4 E038A8 0 +OP4 E038A9 0 +OP4 E038AA 0 +OP4 E038AB 0 +OP4 E038AC 0 +OP4 E038AD 0 +OP4 E038AE 0 +OP4 E038AF 0 +OP4 E038B0 0 +OP4 E038B1 0 +OP4 E038B2 0 +OP4 E038B3 0 +OP4 E038B4 0 +OP4 E038B5 0 +OP4 E038B6 0 +OP4 E038B7 0 +OP4 E038B8 0 +OP4 E038B9 0 +OP4 E038BA 0 +OP4 E038BB 0 +OP4 E038BC 0 +OP4 E038BD 0 +OP4 E038BE 0 +OP4 E038BF 0 +OP4 E038C0 0 +OP4 E038C1 0 +OP4 E038C2 0 +OP4 E038C3 0 +OP4 E038C4 0 +OP4 E038C5 0 +OP4 E038C6 0 +OP4 E038C7 0 +OP4 E038C8 0 +OP4 E038C9 0 +OP4 E038CA 0 +OP4 E038CB 0 +OP4 E038CC 0 +OP4 E038CD 0 +OP4 E038CE 0 +OP4 E038CF 0 +OP4 E038D0 0 +OP4 E038D1 0 +OP4 E038D2 0 +OP4 E038D3 0 +OP4 E038D4 0 +OP4 E038D5 0 +OP4 E038D6 0 +OP4 E038D7 0 +OP4 E038D8 0 +OP4 E038D9 0 +OP4 E038DA 0 +OP4 E038DB 0 +OP4 E038DC 0 +OP4 E038DD 0 +OP4 E038DE 0 +OP4 E038DF 0 +OP4 E038E0 0 +OP4 E038E1 0 +OP4 E038E2 0 +OP4 E038E3 0 +OP4 E038E4 0 +OP4 E038E5 0 +OP4 E038E6 0 +OP4 E038E7 0 +OP4 E038E8 0 +OP4 E038E9 0 +OP4 E038EA 0 +OP4 E038EB 0 +OP4 E038EC 0 +OP4 E038ED 0 +OP4 E038EE 0 +OP4 E038EF 0 +OP4 E038F0 0 +OP4 E038F1 0 +OP4 E038F2 0 +OP4 E038F3 0 +OP4 E038F4 0 +OP4 E038F5 0 +OP4 E038F6 0 +OP4 E038F7 0 +OP4 E038F8 0 +OP4 E038F9 0 +OP4 E038FA 0 +OP4 E038FB 0 +OP4 E038FC 0 +OP4 E038FD 0 +OP4 E038FE 0 +OP4 E038FF 0 +OP4 E03900 0 +OP4 E03901 0 +OP4 E03902 0 +OP4 E03903 0 +OP4 E03904 0 +OP4 E03905 0 +OP4 E03906 0 +OP4 E03907 0 +OP4 E03908 0 +OP4 E03909 0 +OP4 E0390A 0 +OP4 E0390B 0 +OP4 E0390C 0 +OP4 E0390D 0 +OP4 E0390E 0 +OP4 E0390F 0 +OP4 E03910 0 +OP4 E03911 0 +OP4 E03912 0 +OP4 E03913 0 +OP4 E03914 0 +OP4 E03915 0 +OP4 E03916 0 +OP4 E03917 0 +OP4 E03918 0 +OP4 E03919 0 +OP4 E0391A 0 +OP4 E0391B 0 +OP4 E0391C 0 +OP4 E0391D 0 +OP4 E0391E 0 +OP4 E0391F 0 +OP4 E03920 0 +OP4 E03921 0 +OP4 E03922 0 +OP4 E03923 0 +OP4 E03924 0 +OP4 E03925 0 +OP4 E03926 0 +OP4 E03927 0 +OP4 E03928 0 +OP4 E03929 0 +OP4 E0392A 0 +OP4 E0392B 0 +OP4 E0392C 0 +OP4 E0392D 0 +OP4 E0392E 0 +OP4 E0392F 0 +OP4 E03930 0 +OP4 E03931 0 +OP4 E03932 0 +OP4 E03933 0 +OP4 E03934 0 +OP4 E03935 0 +OP4 E03936 0 +OP4 E03937 0 +OP4 E03938 0 +OP4 E03939 0 +OP4 E0393A 0 +OP4 E0393B 0 +OP4 E0393C 0 +OP4 E0393D 0 +OP4 E0393E 0 +OP4 E0393F 0 +OP4 E03940 0 +OP4 E03941 0 +OP4 E03942 0 +OP4 E03943 0 +OP4 E03944 0 +OP4 E03945 0 +OP4 E03946 0 +OP4 E03947 0 +OP4 E03948 0 +OP4 E03949 0 +OP4 E0394A 0 +OP4 E0394B 0 +OP4 E0394C 0 +OP4 E0394D 0 +OP4 E0394E 0 +OP4 E0394F 0 +OP4 E03950 0 +OP4 E03951 0 +OP4 E03952 0 +OP4 E03953 0 +OP4 E03954 0 +OP4 E03955 0 +OP4 E03956 0 +OP4 E03957 0 +OP4 E03958 0 +OP4 E03959 0 +OP4 E0395A 0 +OP4 E0395B 0 +OP4 E0395C 0 +OP4 E0395D 0 +OP4 E0395E 0 +OP4 E0395F 0 +OP4 E03960 0 +OP4 E03961 0 +OP4 E03962 0 +OP4 E03963 0 +OP4 E03964 0 +OP4 E03965 0 +OP4 E03966 0 +OP4 E03967 0 +OP4 E03968 0 +OP4 E03969 0 +OP4 E0396A 0 +OP4 E0396B 0 +OP4 E0396C 0 +OP4 E0396D 0 +OP4 E0396E 0 +OP4 E0396F 0 +OP4 E03970 0 +OP4 E03971 0 +OP4 E03972 0 +OP4 E03973 0 +OP4 E03974 0 +OP4 E03975 0 +OP4 E03976 0 +OP4 E03977 0 +OP4 E03978 0 +OP4 E03979 0 +OP4 E0397A 0 +OP4 E0397B 0 +OP4 E0397C 0 +OP4 E0397D 0 +OP4 E0397E 0 +OP4 E0397F 0 +OP4 E03980 0 +OP4 E03981 0 +OP4 E03982 0 +OP4 E03983 0 +OP4 E03984 0 +OP4 E03985 0 +OP4 E03986 0 +OP4 E03987 0 +OP4 E03988 0 +OP4 E03989 0 +OP4 E0398A 0 +OP4 E0398B 0 +OP4 E0398C 0 +OP4 E0398D 0 +OP4 E0398E 0 +OP4 E0398F 0 +OP4 E03990 0 +OP4 E03991 0 +OP4 E03992 0 +OP4 E03993 0 +OP4 E03994 0 +OP4 E03995 0 +OP4 E03996 0 +OP4 E03997 0 +OP4 E03998 0 +OP4 E03999 0 +OP4 E0399A 0 +OP4 E0399B 0 +OP4 E0399C 0 +OP4 E0399D 0 +OP4 E0399E 0 +OP4 E0399F 0 +OP4 E039A0 0 +OP4 E039A1 0 +OP4 E039A2 0 +OP4 E039A3 0 +OP4 E039A4 0 +OP4 E039A5 0 +OP4 E039A6 0 +OP4 E039A7 0 +OP4 E039A8 0 +OP4 E039A9 0 +OP4 E039AA 0 +OP4 E039AB 0 +OP4 E039AC 0 +OP4 E039AD 0 +OP4 E039AE 0 +OP4 E039AF 0 +OP4 E039B0 0 +OP4 E039B1 0 +OP4 E039B2 0 +OP4 E039B3 0 +OP4 E039B4 0 +OP4 E039B5 0 +OP4 E039B6 0 +OP4 E039B7 0 +OP4 E039B8 0 +OP4 E039B9 0 +OP4 E039BA 0 +OP4 E039BB 0 +OP4 E039BC 0 +OP4 E039BD 0 +OP4 E039BE 0 +OP4 E039BF 0 +OP4 E039C0 0 +OP4 E039C1 0 +OP4 E039C2 0 +OP4 E039C3 0 +OP4 E039C4 0 +OP4 E039C5 0 +OP4 E039C6 0 +OP4 E039C7 0 +OP4 E039C8 0 +OP4 E039C9 0 +OP4 E039CA 0 +OP4 E039CB 0 +OP4 E039CC 0 +OP4 E039CD 0 +OP4 E039CE 0 +OP4 E039CF 0 +OP4 E039D0 0 +OP4 E039D1 0 +OP4 E039D2 0 +OP4 E039D3 0 +OP4 E039D4 0 +OP4 E039D5 0 +OP4 E039D6 0 +OP4 E039D7 0 +OP4 E039D8 0 +OP4 E039D9 0 +OP4 E039DA 0 +OP4 E039DB 0 +OP4 E039DC 0 +OP4 E039DD 0 +OP4 E039DE 0 +OP4 E039DF 0 +OP4 E039E0 0 +OP4 E039E1 0 +OP4 E039E2 0 +OP4 E039E3 0 +OP4 E039E4 0 +OP4 E039E5 0 +OP4 E039E6 0 +OP4 E039E7 0 +OP4 E039E8 0 +OP4 E039E9 0 +OP4 E039EA 0 +OP4 E039EB 0 +OP4 E039EC 0 +OP4 E039ED 0 +OP4 E039EE 0 +OP4 E039EF 0 +OP4 E039F0 0 +OP4 E039F1 0 +OP4 E039F2 0 +OP4 E039F3 0 +OP4 E039F4 0 +OP4 E039F5 0 +OP4 E039F6 0 +OP4 E039F7 0 +OP4 E039F8 0 +OP4 E039F9 0 +OP4 E039FA 0 +OP4 E039FB 0 +OP4 E039FC 0 +OP4 E039FD 0 +OP4 E039FE 0 +OP4 E039FF 0 +OP4 E03A00 0 +OP4 E03A01 0 +OP4 E03A02 0 +OP4 E03A03 0 +OP4 E03A04 0 +OP4 E03A05 0 +OP4 E03A06 0 +OP4 E03A07 0 +OP4 E03A08 0 +OP4 E03A09 0 +OP4 E03A0A 0 +OP4 E03A0B 0 +OP4 E03A0C 0 +OP4 E03A0D 0 +OP4 E03A0E 0 +OP4 E03A0F 0 +OP4 E03A10 0 +OP4 E03A11 0 +OP4 E03A12 0 +OP4 E03A13 0 +OP4 E03A14 0 +OP4 E03A15 0 +OP4 E03A16 0 +OP4 E03A17 0 +OP4 E03A18 0 +OP4 E03A19 0 +OP4 E03A1A 0 +OP4 E03A1B 0 +OP4 E03A1C 0 +OP4 E03A1D 0 +OP4 E03A1E 0 +OP4 E03A1F 0 +OP4 E03A20 0 +OP4 E03A21 0 +OP4 E03A22 0 +OP4 E03A23 0 +OP4 E03A24 0 +OP4 E03A25 0 +OP4 E03A26 0 +OP4 E03A27 0 +OP4 E03A28 0 +OP4 E03A29 0 +OP4 E03A2A 0 +OP4 E03A2B 0 +OP4 E03A2C 0 +OP4 E03A2D 0 +OP4 E03A2E 0 +OP4 E03A2F 0 +OP4 E03A30 0 +OP4 E03A31 0 +OP4 E03A32 0 +OP4 E03A33 0 +OP4 E03A34 0 +OP4 E03A35 0 +OP4 E03A36 0 +OP4 E03A37 0 +OP4 E03A38 0 +OP4 E03A39 0 +OP4 E03A3A 0 +OP4 E03A3B 0 +OP4 E03A3C 0 +OP4 E03A3D 0 +OP4 E03A3E 0 +OP4 E03A3F 0 +OP4 E03A40 0 +OP4 E03A41 0 +OP4 E03A42 0 +OP4 E03A43 0 +OP4 E03A44 0 +OP4 E03A45 0 +OP4 E03A46 0 +OP4 E03A47 0 +OP4 E03A48 0 +OP4 E03A49 0 +OP4 E03A4A 0 +OP4 E03A4B 0 +OP4 E03A4C 0 +OP4 E03A4D 0 +OP4 E03A4E 0 +OP4 E03A4F 0 +OP4 E03A50 0 +OP4 E03A51 0 +OP4 E03A52 0 +OP4 E03A53 0 +OP4 E03A54 0 +OP4 E03A55 0 +OP4 E03A56 0 +OP4 E03A57 0 +OP4 E03A58 0 +OP4 E03A59 0 +OP4 E03A5A 0 +OP4 E03A5B 0 +OP4 E03A5C 0 +OP4 E03A5D 0 +OP4 E03A5E 0 +OP4 E03A5F 0 +OP4 E03A60 0 +OP4 E03A61 0 +OP4 E03A62 0 +OP4 E03A63 0 +OP4 E03A64 0 +OP4 E03A65 0 +OP4 E03A66 0 +OP4 E03A67 0 +OP4 E03A68 0 +OP4 E03A69 0 +OP4 E03A6A 0 +OP4 E03A6B 0 +OP4 E03A6C 0 +OP4 E03A6D 0 +OP4 E03A6E 0 +OP4 E03A6F 0 +OP4 E03A70 0 +OP4 E03A71 0 +OP4 E03A72 0 +OP4 E03A73 0 +OP4 E03A74 0 +OP4 E03A75 0 +OP4 E03A76 0 +OP4 E03A77 0 +OP4 E03A78 0 +OP4 E03A79 0 +OP4 E03A7A 0 +OP4 E03A7B 0 +OP4 E03A7C 0 +OP4 E03A7D 0 +OP4 E03A7E 0 +OP4 E03A7F 0 +OP4 E03A80 0 +OP4 E03A81 0 +OP4 E03A82 0 +OP4 E03A83 0 +OP4 E03A84 0 +OP4 E03A85 0 +OP4 E03A86 0 +OP4 E03A87 0 +OP4 E03A88 0 +OP4 E03A89 0 +OP4 E03A8A 0 +OP4 E03A8B 0 +OP4 E03A8C 0 +OP4 E03A8D 0 +OP4 E03A8E 0 +OP4 E03A8F 0 +OP4 E03A90 0 +OP4 E03A91 0 +OP4 E03A92 0 +OP4 E03A93 0 +OP4 E03A94 0 +OP4 E03A95 0 +OP4 E03A96 0 +OP4 E03A97 0 +OP4 E03A98 0 +OP4 E03A99 0 +OP4 E03A9A 0 +OP4 E03A9B 0 +OP4 E03A9C 0 +OP4 E03A9D 0 +OP4 E03A9E 0 +OP4 E03A9F 0 +OP4 E03AA0 0 +OP4 E03AA1 0 +OP4 E03AA2 0 +OP4 E03AA3 0 +OP4 E03AA4 0 +OP4 E03AA5 0 +OP4 E03AA6 0 +OP4 E03AA7 0 +OP4 E03AA8 0 +OP4 E03AA9 0 +OP4 E03AAA 0 +OP4 E03AAB 0 +OP4 E03AAC 0 +OP4 E03AAD 0 +OP4 E03AAE 0 +OP4 E03AAF 0 +OP4 E03AB0 0 +OP4 E03AB1 0 +OP4 E03AB2 0 +OP4 E03AB3 0 +OP4 E03AB4 0 +OP4 E03AB5 0 +OP4 E03AB6 0 +OP4 E03AB7 0 +OP4 E03AB8 0 +OP4 E03AB9 0 +OP4 E03ABA 0 +OP4 E03ABB 0 +OP4 E03ABC 0 +OP4 E03ABD 0 +OP4 E03ABE 0 +OP4 E03ABF 0 +OP4 E03AC0 0 +OP4 E03AC1 0 +OP4 E03AC2 0 +OP4 E03AC3 0 +OP4 E03AC4 0 +OP4 E03AC5 0 +OP4 E03AC6 0 +OP4 E03AC7 0 +OP4 E03AC8 0 +OP4 E03AC9 0 +OP4 E03ACA 0 +OP4 E03ACB 0 +OP4 E03ACC 0 +OP4 E03ACD 0 +OP4 E03ACE 0 +OP4 E03ACF 0 +OP4 E03AD0 0 +OP4 E03AD1 0 +OP4 E03AD2 0 +OP4 E03AD3 0 +OP4 E03AD4 0 +OP4 E03AD5 0 +OP4 E03AD6 0 +OP4 E03AD7 0 +OP4 E03AD8 0 +OP4 E03AD9 0 +OP4 E03ADA 0 +OP4 E03ADB 0 +OP4 E03ADC 0 +OP4 E03ADD 0 +OP4 E03ADE 0 +OP4 E03ADF 0 +OP4 E03AE0 0 +OP4 E03AE1 0 +OP4 E03AE2 0 +OP4 E03AE3 0 +OP4 E03AE4 0 +OP4 E03AE5 0 +OP4 E03AE6 0 +OP4 E03AE7 0 +OP4 E03AE8 0 +OP4 E03AE9 0 +OP4 E03AEA 0 +OP4 E03AEB 0 +OP4 E03AEC 0 +OP4 E03AED 0 +OP4 E03AEE 0 +OP4 E03AEF 0 +OP4 E03AF0 0 +OP4 E03AF1 0 +OP4 E03AF2 0 +OP4 E03AF3 0 +OP4 E03AF4 0 +OP4 E03AF5 0 +OP4 E03AF6 0 +OP4 E03AF7 0 +OP4 E03AF8 0 +OP4 E03AF9 0 +OP4 E03AFA 0 +OP4 E03AFB 0 +OP4 E03AFC 0 +OP4 E03AFD 0 +OP4 E03AFE 0 +OP4 E03AFF 0 +OP4 E03B00 0 +OP4 E03B01 0 +OP4 E03B02 0 +OP4 E03B03 0 +OP4 E03B04 0 +OP4 E03B05 0 +OP4 E03B06 0 +OP4 E03B07 0 +OP4 E03B08 0 +OP4 E03B09 0 +OP4 E03B0A 0 +OP4 E03B0B 0 +OP4 E03B0C 0 +OP4 E03B0D 0 +OP4 E03B0E 0 +OP4 E03B0F 0 +OP4 E03B10 0 +OP4 E03B11 0 +OP4 E03B12 0 +OP4 E03B13 0 +OP4 E03B14 0 +OP4 E03B15 0 +OP4 E03B16 0 +OP4 E03B17 0 +OP4 E03B18 0 +OP4 E03B19 0 +OP4 E03B1A 0 +OP4 E03B1B 0 +OP4 E03B1C 0 +OP4 E03B1D 0 +OP4 E03B1E 0 +OP4 E03B1F 0 +OP4 E03B20 0 +OP4 E03B21 0 +OP4 E03B22 0 +OP4 E03B23 0 +OP4 E03B24 0 +OP4 E03B25 0 +OP4 E03B26 0 +OP4 E03B27 0 +OP4 E03B28 0 +OP4 E03B29 0 +OP4 E03B2A 0 +OP4 E03B2B 0 +OP4 E03B2C 0 +OP4 E03B2D 0 +OP4 E03B2E 0 +OP4 E03B2F 0 +OP4 E03B30 0 +OP4 E03B31 0 +OP4 E03B32 0 +OP4 E03B33 0 +OP4 E03B34 0 +OP4 E03B35 0 +OP4 E03B36 0 +OP4 E03B37 0 +OP4 E03B38 0 +OP4 E03B39 0 +OP4 E03B3A 0 +OP4 E03B3B 0 +OP4 E03B3C 0 +OP4 E03B3D 0 +OP4 E03B3E 0 +OP4 E03B3F 0 +OP4 E03B40 0 +OP4 E03B41 0 +OP4 E03B42 0 +OP4 E03B43 0 +OP4 E03B44 0 +OP4 E03B45 0 +OP4 E03B46 0 +OP4 E03B47 0 +OP4 E03B48 0 +OP4 E03B49 0 +OP4 E03B4A 0 +OP4 E03B4B 0 +OP4 E03B4C 0 +OP4 E03B4D 0 +OP4 E03B4E 0 +OP4 E03B4F 0 +OP4 E03B50 0 +OP4 E03B51 0 +OP4 E03B52 0 +OP4 E03B53 0 +OP4 E03B54 0 +OP4 E03B55 0 +OP4 E03B56 0 +OP4 E03B57 0 +OP4 E03B58 0 +OP4 E03B59 0 +OP4 E03B5A 0 +OP4 E03B5B 0 +OP4 E03B5C 0 +OP4 E03B5D 0 +OP4 E03B5E 0 +OP4 E03B5F 0 +OP4 E03B60 0 +OP4 E03B61 0 +OP4 E03B62 0 +OP4 E03B63 0 +OP4 E03B64 0 +OP4 E03B65 0 +OP4 E03B66 0 +OP4 E03B67 0 +OP4 E03B68 0 +OP4 E03B69 0 +OP4 E03B6A 0 +OP4 E03B6B 0 +OP4 E03B6C 0 +OP4 E03B6D 0 +OP4 E03B6E 0 +OP4 E03B6F 0 +OP4 E03B70 0 +OP4 E03B71 0 +OP4 E03B72 0 +OP4 E03B73 0 +OP4 E03B74 0 +OP4 E03B75 0 +OP4 E03B76 0 +OP4 E03B77 0 +OP4 E03B78 0 +OP4 E03B79 0 +OP4 E03B7A 0 +OP4 E03B7B 0 +OP4 E03B7C 0 +OP4 E03B7D 0 +OP4 E03B7E 0 +OP4 E03B7F 0 +OP4 E03B80 0 +OP4 E03B81 0 +OP4 E03B82 0 +OP4 E03B83 0 +OP4 E03B84 0 +OP4 E03B85 0 +OP4 E03B86 0 +OP4 E03B87 0 +OP4 E03B88 0 +OP4 E03B89 0 +OP4 E03B8A 0 +OP4 E03B8B 0 +OP4 E03B8C 0 +OP4 E03B8D 0 +OP4 E03B8E 0 +OP4 E03B8F 0 +OP4 E03B90 0 +OP4 E03B91 0 +OP4 E03B92 0 +OP4 E03B93 0 +OP4 E03B94 0 +OP4 E03B95 0 +OP4 E03B96 0 +OP4 E03B97 0 +OP4 E03B98 0 +OP4 E03B99 0 +OP4 E03B9A 0 +OP4 E03B9B 0 +OP4 E03B9C 0 +OP4 E03B9D 0 +OP4 E03B9E 0 +OP4 E03B9F 0 +OP4 E03BA0 0 +OP4 E03BA1 0 +OP4 E03BA2 0 +OP4 E03BA3 0 +OP4 E03BA4 0 +OP4 E03BA5 0 +OP4 E03BA6 0 +OP4 E03BA7 0 +OP4 E03BA8 0 +OP4 E03BA9 0 +OP4 E03BAA 0 +OP4 E03BAB 0 +OP4 E03BAC 0 +OP4 E03BAD 0 +OP4 E03BAE 0 +OP4 E03BAF 0 +OP4 E03BB0 0 +OP4 E03BB1 0 +OP4 E03BB2 0 +OP4 E03BB3 0 +OP4 E03BB4 0 +OP4 E03BB5 0 +OP4 E03BB6 0 +OP4 E03BB7 0 +OP4 E03BB8 0 +OP4 E03BB9 0 +OP4 E03BBA 0 +OP4 E03BBB 0 +OP4 E03BBC 0 +OP4 E03BBD 0 +OP4 E03BBE 0 +OP4 E03BBF 0 +OP4 E03BC0 0 +OP4 E03BC1 0 +OP4 E03BC2 0 +OP4 E03BC3 0 +OP4 E03BC4 0 +OP4 E03BC5 0 +OP4 E03BC6 0 +OP4 E03BC7 0 +OP4 E03BC8 0 +OP4 E03BC9 0 +OP4 E03BCA 0 +OP4 E03BCB 0 +OP4 E03BCC 0 +OP4 E03BCD 0 +OP4 E03BCE 0 +OP4 E03BCF 0 +OP4 E03BD0 0 +OP4 E03BD1 0 +OP4 E03BD2 0 +OP4 E03BD3 0 +OP4 E03BD4 0 +OP4 E03BD5 0 +OP4 E03BD6 0 +OP4 E03BD7 0 +OP4 E03BD8 0 +OP4 E03BD9 0 +OP4 E03BDA 0 +OP4 E03BDB 0 +OP4 E03BDC 0 +OP4 E03BDD 0 +OP4 E03BDE 0 +OP4 E03BDF 0 +OP4 E03BE0 0 +OP4 E03BE1 0 +OP4 E03BE2 0 +OP4 E03BE3 0 +OP4 E03BE4 0 +OP4 E03BE5 0 +OP4 E03BE6 0 +OP4 E03BE7 0 +OP4 E03BE8 0 +OP4 E03BE9 0 +OP4 E03BEA 0 +OP4 E03BEB 0 +OP4 E03BEC 0 +OP4 E03BED 0 +OP4 E03BEE 0 +OP4 E03BEF 0 +OP4 E03BF0 0 +OP4 E03BF1 0 +OP4 E03BF2 0 +OP4 E03BF3 0 +OP4 E03BF4 0 +OP4 E03BF5 0 +OP4 E03BF6 0 +OP4 E03BF7 0 +OP4 E03BF8 0 +OP4 E03BF9 0 +OP4 E03BFA 0 +OP4 E03BFB 0 +OP4 E03BFC 0 +OP4 E03BFD 0 +OP4 E03BFE 0 +OP4 E03BFF 0 +OP4 E03C00 0 +OP4 E03C01 0 +OP4 E03C02 0 +OP4 E03C03 0 +OP4 E03C04 0 +OP4 E03C05 0 +OP4 E03C06 0 +OP4 E03C07 0 +OP4 E03C08 0 +OP4 E03C09 0 +OP4 E03C0A 0 +OP4 E03C0B 0 +OP4 E03C0C 0 +OP4 E03C0D 0 +OP4 E03C0E 0 +OP4 E03C0F 0 +OP4 E03C10 0 +OP4 E03C11 0 +OP4 E03C12 0 +OP4 E03C13 0 +OP4 E03C14 0 +OP4 E03C15 0 +OP4 E03C16 0 +OP4 E03C17 0 +OP4 E03C18 0 +OP4 E03C19 0 +OP4 E03C1A 0 +OP4 E03C1B 0 +OP4 E03C1C 0 +OP4 E03C1D 0 +OP4 E03C1E 0 +OP4 E03C1F 0 +OP4 E03C20 0 +OP4 E03C21 0 +OP4 E03C22 0 +OP4 E03C23 0 +OP4 E03C24 0 +OP4 E03C25 0 +OP4 E03C26 0 +OP4 E03C27 0 +OP4 E03C28 0 +OP4 E03C29 0 +OP4 E03C2A 0 +OP4 E03C2B 0 +OP4 E03C2C 0 +OP4 E03C2D 0 +OP4 E03C2E 0 +OP4 E03C2F 0 +OP4 E03C30 0 +OP4 E03C31 0 +OP4 E03C32 0 +OP4 E03C33 0 +OP4 E03C34 0 +OP4 E03C35 0 +OP4 E03C36 0 +OP4 E03C37 0 +OP4 E03C38 0 +OP4 E03C39 0 +OP4 E03C3A 0 +OP4 E03C3B 0 +OP4 E03C3C 0 +OP4 E03C3D 0 +OP4 E03C3E 0 +OP4 E03C3F 0 +OP4 E03C40 0 +OP4 E03C41 0 +OP4 E03C42 0 +OP4 E03C43 0 +OP4 E03C44 0 +OP4 E03C45 0 +OP4 E03C46 0 +OP4 E03C47 0 +OP4 E03C48 0 +OP4 E03C49 0 +OP4 E03C4A 0 +OP4 E03C4B 0 +OP4 E03C4C 0 +OP4 E03C4D 0 +OP4 E03C4E 0 +OP4 E03C4F 0 +OP4 E03C50 0 +OP4 E03C51 0 +OP4 E03C52 0 +OP4 E03C53 0 +OP4 E03C54 0 +OP4 E03C55 0 +OP4 E03C56 0 +OP4 E03C57 0 +OP4 E03C58 0 +OP4 E03C59 0 +OP4 E03C5A 0 +OP4 E03C5B 0 +OP4 E03C5C 0 +OP4 E03C5D 0 +OP4 E03C5E 0 +OP4 E03C5F 0 +OP4 E03C60 0 +OP4 E03C61 0 +OP4 E03C62 0 +OP4 E03C63 0 +OP4 E03C64 0 +OP4 E03C65 0 +OP4 E03C66 0 +OP4 E03C67 0 +OP4 E03C68 0 +OP4 E03C69 0 +OP4 E03C6A 0 +OP4 E03C6B 0 +OP4 E03C6C 0 +OP4 E03C6D 0 +OP4 E03C6E 0 +OP4 E03C6F 0 +OP4 E03C70 0 +OP4 E03C71 0 +OP4 E03C72 0 +OP4 E03C73 0 +OP4 E03C74 0 +OP4 E03C75 0 +OP4 E03C76 0 +OP4 E03C77 0 +OP4 E03C78 0 +OP4 E03C79 0 +OP4 E03C7A 0 +OP4 E03C7B 0 +OP4 E03C7C 0 +OP4 E03C7D 0 +OP4 E03C7E 0 +OP4 E03C7F 0 +OP4 E03C80 0 +OP4 E03C81 0 +OP4 E03C82 0 +OP4 E03C83 0 +OP4 E03C84 0 +OP4 E03C85 0 +OP4 E03C86 0 +OP4 E03C87 0 +OP4 E03C88 0 +OP4 E03C89 0 +OP4 E03C8A 0 +OP4 E03C8B 0 +OP4 E03C8C 0 +OP4 E03C8D 0 +OP4 E03C8E 0 +OP4 E03C8F 0 +OP4 E03C90 0 +OP4 E03C91 0 +OP4 E03C92 0 +OP4 E03C93 0 +OP4 E03C94 0 +OP4 E03C95 0 +OP4 E03C96 0 +OP4 E03C97 0 +OP4 E03C98 0 +OP4 E03C99 0 +OP4 E03C9A 0 +OP4 E03C9B 0 +OP4 E03C9C 0 +OP4 E03C9D 0 +OP4 E03C9E 0 +OP4 E03C9F 0 +OP4 E03CA0 0 +OP4 E03CA1 0 +OP4 E03CA2 0 +OP4 E03CA3 0 +OP4 E03CA4 0 +OP4 E03CA5 0 +OP4 E03CA6 0 +OP4 E03CA7 0 +OP4 E03CA8 0 +OP4 E03CA9 0 +OP4 E03CAA 0 +OP4 E03CAB 0 +OP4 E03CAC 0 +OP4 E03CAD 0 +OP4 E03CAE 0 +OP4 E03CAF 0 +OP4 E03CB0 0 +OP4 E03CB1 0 +OP4 E03CB2 0 +OP4 E03CB3 0 +OP4 E03CB4 0 +OP4 E03CB5 0 +OP4 E03CB6 0 +OP4 E03CB7 0 +OP4 E03CB8 0 +OP4 E03CB9 0 +OP4 E03CBA 0 +OP4 E03CBB 0 +OP4 E03CBC 0 +OP4 E03CBD 0 +OP4 E03CBE 0 +OP4 E03CBF 0 +OP4 E03CC0 0 +OP4 E03CC1 0 +OP4 E03CC2 0 +OP4 E03CC3 0 +OP4 E03CC4 0 +OP4 E03CC5 0 +OP4 E03CC6 0 +OP4 E03CC7 0 +OP4 E03CC8 0 +OP4 E03CC9 0 +OP4 E03CCA 0 +OP4 E03CCB 0 +OP4 E03CCC 0 +OP4 E03CCD 0 +OP4 E03CCE 0 +OP4 E03CCF 0 +OP4 E03CD0 0 +OP4 E03CD1 0 +OP4 E03CD2 0 +OP4 E03CD3 0 +OP4 E03CD4 0 +OP4 E03CD5 0 +OP4 E03CD6 0 +OP4 E03CD7 0 +OP4 E03CD8 0 +OP4 E03CD9 0 +OP4 E03CDA 0 +OP4 E03CDB 0 +OP4 E03CDC 0 +OP4 E03CDD 0 +OP4 E03CDE 0 +OP4 E03CDF 0 +OP4 E03CE0 0 +OP4 E03CE1 0 +OP4 E03CE2 0 +OP4 E03CE3 0 +OP4 E03CE4 0 +OP4 E03CE5 0 +OP4 E03CE6 0 +OP4 E03CE7 0 +OP4 E03CE8 0 +OP4 E03CE9 0 +OP4 E03CEA 0 +OP4 E03CEB 0 +OP4 E03CEC 0 +OP4 E03CED 0 +OP4 E03CEE 0 +OP4 E03CEF 0 +OP4 E03CF0 0 +OP4 E03CF1 0 +OP4 E03CF2 0 +OP4 E03CF3 0 +OP4 E03CF4 0 +OP4 E03CF5 0 +OP4 E03CF6 0 +OP4 E03CF7 0 +OP4 E03CF8 0 +OP4 E03CF9 0 +OP4 E03CFA 0 +OP4 E03CFB 0 +OP4 E03CFC 0 +OP4 E03CFD 0 +OP4 E03CFE 0 +OP4 E03CFF 0 +OP4 E03D00 0 +OP4 E03D01 0 +OP4 E03D02 0 +OP4 E03D03 0 +OP4 E03D04 0 +OP4 E03D05 0 +OP4 E03D06 0 +OP4 E03D07 0 +OP4 E03D08 0 +OP4 E03D09 0 +OP4 E03D0A 0 +OP4 E03D0B 0 +OP4 E03D0C 0 +OP4 E03D0D 0 +OP4 E03D0E 0 +OP4 E03D0F 0 +OP4 E03D10 0 +OP4 E03D11 0 +OP4 E03D12 0 +OP4 E03D13 0 +OP4 E03D14 0 +OP4 E03D15 0 +OP4 E03D16 0 +OP4 E03D17 0 +OP4 E03D18 0 +OP4 E03D19 0 +OP4 E03D1A 0 +OP4 E03D1B 0 +OP4 E03D1C 0 +OP4 E03D1D 0 +OP4 E03D1E 0 +OP4 E03D1F 0 +OP4 E03D20 0 +OP4 E03D21 0 +OP4 E03D22 0 +OP4 E03D23 0 +OP4 E03D24 0 +OP4 E03D25 0 +OP4 E03D26 0 +OP4 E03D27 0 +OP4 E03D28 0 +OP4 E03D29 0 +OP4 E03D2A 0 +OP4 E03D2B 0 +OP4 E03D2C 0 +OP4 E03D2D 0 +OP4 E03D2E 0 +OP4 E03D2F 0 +OP4 E03D30 0 +OP4 E03D31 0 +OP4 E03D32 0 +OP4 E03D33 0 +OP4 E03D34 0 +OP4 E03D35 0 +OP4 E03D36 0 +OP4 E03D37 0 +OP4 E03D38 0 +OP4 E03D39 0 +OP4 E03D3A 0 +OP4 E03D3B 0 +OP4 E03D3C 0 +OP4 E03D3D 0 +OP4 E03D3E 0 +OP4 E03D3F 0 +OP4 E03D40 0 +OP4 E03D41 0 +OP4 E03D42 0 +OP4 E03D43 0 +OP4 E03D44 0 +OP4 E03D45 0 +OP4 E03D46 0 +OP4 E03D47 0 +OP4 E03D48 0 +OP4 E03D49 0 +OP4 E03D4A 0 +OP4 E03D4B 0 +OP4 E03D4C 0 +OP4 E03D4D 0 +OP4 E03D4E 0 +OP4 E03D4F 0 +OP4 E03D50 0 +OP4 E03D51 0 +OP4 E03D52 0 +OP4 E03D53 0 +OP4 E03D54 0 +OP4 E03D55 0 +OP4 E03D56 0 +OP4 E03D57 0 +OP4 E03D58 0 +OP4 E03D59 0 +OP4 E03D5A 0 +OP4 E03D5B 0 +OP4 E03D5C 0 +OP4 E03D5D 0 +OP4 E03D5E 0 +OP4 E03D5F 0 +OP4 E03D60 0 +OP4 E03D61 0 +OP4 E03D62 0 +OP4 E03D63 0 +OP4 E03D64 0 +OP4 E03D65 0 +OP4 E03D66 0 +OP4 E03D67 0 +OP4 E03D68 0 +OP4 E03D69 0 +OP4 E03D6A 0 +OP4 E03D6B 0 +OP4 E03D6C 0 +OP4 E03D6D 0 +OP4 E03D6E 0 +OP4 E03D6F 0 +OP4 E03D70 0 +OP4 E03D71 0 +OP4 E03D72 0 +OP4 E03D73 0 +OP4 E03D74 0 +OP4 E03D75 0 +OP4 E03D76 0 +OP4 E03D77 0 +OP4 E03D78 0 +OP4 E03D79 0 +OP4 E03D7A 0 +OP4 E03D7B 0 +OP4 E03D7C 0 +OP4 E03D7D 0 +OP4 E03D7E 0 +OP4 E03D7F 0 +OP4 E03D80 0 +OP4 E03D81 0 +OP4 E03D82 0 +OP4 E03D83 0 +OP4 E03D84 0 +OP4 E03D85 0 +OP4 E03D86 0 +OP4 E03D87 0 +OP4 E03D88 0 +OP4 E03D89 0 +OP4 E03D8A 0 +OP4 E03D8B 0 +OP4 E03D8C 0 +OP4 E03D8D 0 +OP4 E03D8E 0 +OP4 E03D8F 0 +OP4 E03D90 0 +OP4 E03D91 0 +OP4 E03D92 0 +OP4 E03D93 0 +OP4 E03D94 0 +OP4 E03D95 0 +OP4 E03D96 0 +OP4 E03D97 0 +OP4 E03D98 0 +OP4 E03D99 0 +OP4 E03D9A 0 +OP4 E03D9B 0 +OP4 E03D9C 0 +OP4 E03D9D 0 +OP4 E03D9E 0 +OP4 E03D9F 0 +OP4 E03DA0 0 +OP4 E03DA1 0 +OP4 E03DA2 0 +OP4 E03DA3 0 +OP4 E03DA4 0 +OP4 E03DA5 0 +OP4 E03DA6 0 +OP4 E03DA7 0 +OP4 E03DA8 0 +OP4 E03DA9 0 +OP4 E03DAA 0 +OP4 E03DAB 0 +OP4 E03DAC 0 +OP4 E03DAD 0 +OP4 E03DAE 0 +OP4 E03DAF 0 +OP4 E03DB0 0 +OP4 E03DB1 0 +OP4 E03DB2 0 +OP4 E03DB3 0 +OP4 E03DB4 0 +OP4 E03DB5 0 +OP4 E03DB6 0 +OP4 E03DB7 0 +OP4 E03DB8 0 +OP4 E03DB9 0 +OP4 E03DBA 0 +OP4 E03DBB 0 +OP4 E03DBC 0 +OP4 E03DBD 0 +OP4 E03DBE 0 +OP4 E03DBF 0 +OP4 E03DC0 0 +OP4 E03DC1 0 +OP4 E03DC2 0 +OP4 E03DC3 0 +OP4 E03DC4 0 diff --git a/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum4_itrace_irisc1.cfg.ext b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum4_itrace_irisc1.cfg.ext new file mode 100644 index 000000000000..161041664e5c --- /dev/null +++ b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum4_itrace_irisc1.cfg.ext @@ -0,0 +1,15814 @@ +OP1 Spectrum4 +OP4 ITRACE0 0 +OP4 ITRACE1 1 +OP4 ITRACE2 0 +OP4 ITRACE3 0 +OP4 ITRACE4 0 +OP4 ITRACE5 0 +OP4 ITRACE6 0 +OP4 ITRACE7 0 +OP4 ITRACE8 0 +OP4 ITRACE9 0 +OP4 Main_PhyUC 0 +OP4 TILE0_ITRACE0 0 +OP4 TILE0_ITRACE1 0 +OP4 TILE0_ITRACE2 0 +OP4 TILE0_ITRACE3 0 +OP4 TILE0_ITRACE4 0 +OP4 TILE0_PhyUC 0 +OP4 TILE1_ITRACE0 0 +OP4 TILE1_ITRACE1 0 +OP4 TILE1_ITRACE2 0 +OP4 TILE1_ITRACE3 0 +OP4 TILE1_ITRACE4 0 +OP4 TILE1_PhyUC 0 +OP4 TILE2_ITRACE0 0 +OP4 TILE2_ITRACE1 0 +OP4 TILE2_ITRACE2 0 +OP4 TILE2_ITRACE3 0 +OP4 TILE2_ITRACE4 0 +OP4 TILE2_PhyUC 0 +OP4 TILE3_ITRACE0 0 +OP4 TILE3_ITRACE1 0 +OP4 TILE3_ITRACE2 0 +OP4 TILE3_ITRACE3 0 +OP4 TILE3_ITRACE4 0 +OP4 TILE3_PhyUC 0 +OP4 TILE4_ITRACE0 0 +OP4 TILE4_ITRACE1 0 +OP4 TILE4_ITRACE2 0 +OP4 TILE4_ITRACE3 0 +OP4 TILE4_ITRACE4 0 +OP4 TILE4_PhyUC 0 +OP4 TILE5_ITRACE0 0 +OP4 TILE5_ITRACE1 0 +OP4 TILE5_ITRACE2 0 +OP4 TILE5_ITRACE3 0 +OP4 TILE5_ITRACE4 0 +OP4 TILE5_PhyUC 0 +OP4 TILE6_ITRACE0 0 +OP4 TILE6_ITRACE1 0 +OP4 TILE6_ITRACE2 0 +OP4 TILE6_ITRACE3 0 +OP4 TILE6_ITRACE4 0 +OP4 TILE6_PhyUC 0 +OP4 TILE7_ITRACE0 0 +OP4 TILE7_ITRACE1 0 +OP4 TILE7_ITRACE2 0 +OP4 TILE7_ITRACE3 0 +OP4 TILE7_ITRACE4 0 +OP4 TILE7_PhyUC 0 +OP4 E0003B 0 +OP4 E0003C 0 +OP4 E0003D 0 +OP4 E0003E 0 +OP4 E0003F 0 +OP4 E00040 0 +OP4 E00041 0 +OP4 E00042 0 +OP4 E00043 0 +OP4 E00044 0 +OP4 E00045 0 +OP4 E00046 0 +OP4 E00047 0 +OP4 E00048 0 +OP4 E00049 0 +OP4 E0004A 0 +OP4 E0004B 0 +OP4 E0004C 0 +OP4 E0004D 0 +OP4 E0004E 0 +OP4 E0004F 0 +OP4 E00050 0 +OP4 E00051 0 +OP4 E00052 0 +OP4 E00053 0 +OP4 E00054 0 +OP4 E00055 0 +OP4 E00056 0 +OP4 E00057 0 +OP4 E00058 0 +OP4 E00059 0 +OP4 E0005A 0 +OP4 E0005B 0 +OP4 E0005C 0 +OP4 E0005D 0 +OP4 E0005E 0 +OP4 E0005F 0 +OP4 E00060 0 +OP4 E00061 0 +OP4 E00062 0 +OP4 E00063 0 +OP4 E00064 0 +OP4 E00065 0 +OP4 E00066 0 +OP4 E00067 0 +OP4 E00068 0 +OP4 E00069 0 +OP4 E0006A 0 +OP4 E0006B 0 +OP4 E0006C 0 +OP4 E0006D 0 +OP4 E0006E 0 +OP4 E0006F 0 +OP4 E00070 0 +OP4 E00071 0 +OP4 E00072 0 +OP4 E00073 0 +OP4 E00074 0 +OP4 E00075 0 +OP4 E00076 0 +OP4 E00077 0 +OP4 E00078 0 +OP4 E00079 0 +OP4 E0007A 0 +OP4 E0007B 0 +OP4 E0007C 0 +OP4 E0007D 0 +OP4 E0007E 0 +OP4 E0007F 0 +OP4 E00080 0 +OP4 E00081 0 +OP4 E00082 0 +OP4 E00083 0 +OP4 E00084 0 +OP4 E00085 0 +OP4 E00086 0 +OP4 E00087 0 +OP4 E00088 0 +OP4 E00089 0 +OP4 E0008A 0 +OP4 E0008B 0 +OP4 E0008C 0 +OP4 E0008D 0 +OP4 E0008E 0 +OP4 E0008F 0 +OP4 E00090 0 +OP4 E00091 0 +OP4 E00092 0 +OP4 E00093 0 +OP4 E00094 0 +OP4 E00095 0 +OP4 E00096 0 +OP4 E00097 0 +OP4 E00098 0 +OP4 E00099 0 +OP4 E0009A 0 +OP4 E0009B 0 +OP4 E0009C 0 +OP4 E0009D 0 +OP4 E0009E 0 +OP4 E0009F 0 +OP4 E000A0 0 +OP4 E000A1 0 +OP4 E000A2 0 +OP4 E000A3 0 +OP4 E000A4 0 +OP4 E000A5 0 +OP4 E000A6 0 +OP4 E000A7 0 +OP4 E000A8 0 +OP4 E000A9 0 +OP4 E000AA 0 +OP4 E000AB 0 +OP4 E000AC 0 +OP4 E000AD 0 +OP4 E000AE 0 +OP4 E000AF 0 +OP4 E000B0 0 +OP4 E000B1 0 +OP4 E000B2 0 +OP4 E000B3 0 +OP4 E000B4 0 +OP4 E000B5 0 +OP4 E000B6 0 +OP4 E000B7 0 +OP4 E000B8 0 +OP4 E000B9 0 +OP4 E000BA 0 +OP4 E000BB 0 +OP4 E000BC 0 +OP4 E000BD 0 +OP4 E000BE 0 +OP4 E000BF 0 +OP4 E000C0 0 +OP4 E000C1 0 +OP4 E000C2 0 +OP4 E000C3 0 +OP4 E000C4 0 +OP4 E000C5 0 +OP4 E000C6 0 +OP4 E000C7 0 +OP4 E000C8 0 +OP4 E000C9 0 +OP4 E000CA 0 +OP4 E000CB 0 +OP4 E000CC 0 +OP4 E000CD 0 +OP4 E000CE 0 +OP4 E000CF 0 +OP4 E000D0 0 +OP4 E000D1 0 +OP4 E000D2 0 +OP4 E000D3 0 +OP4 E000D4 0 +OP4 E000D5 0 +OP4 E000D6 0 +OP4 E000D7 0 +OP4 E000D8 0 +OP4 E000D9 0 +OP4 E000DA 0 +OP4 E000DB 0 +OP4 E000DC 0 +OP4 E000DD 0 +OP4 E000DE 0 +OP4 E000DF 0 +OP4 E000E0 0 +OP4 E000E1 0 +OP4 E000E2 0 +OP4 E000E3 0 +OP4 E000E4 0 +OP4 E000E5 0 +OP4 E000E6 0 +OP4 E000E7 0 +OP4 E000E8 0 +OP4 E000E9 0 +OP4 E000EA 0 +OP4 E000EB 0 +OP4 E000EC 0 +OP4 E000ED 0 +OP4 E000EE 0 +OP4 E000EF 0 +OP4 E000F0 0 +OP4 E000F1 0 +OP4 E000F2 0 +OP4 E000F3 0 +OP4 E000F4 0 +OP4 E000F5 0 +OP4 E000F6 0 +OP4 E000F7 0 +OP4 E000F8 0 +OP4 E000F9 0 +OP4 E000FA 0 +OP4 E000FB 0 +OP4 E000FC 0 +OP4 E000FD 0 +OP4 E000FE 0 +OP4 E000FF 0 +OP4 E00100 0 +OP4 E00101 0 +OP4 E00102 0 +OP4 E00103 0 +OP4 E00104 0 +OP4 E00105 0 +OP4 E00106 0 +OP4 E00107 0 +OP4 E00108 0 +OP4 E00109 0 +OP4 E0010A 0 +OP4 E0010B 0 +OP4 E0010C 0 +OP4 E0010D 0 +OP4 E0010E 0 +OP4 E0010F 0 +OP4 E00110 0 +OP4 E00111 0 +OP4 E00112 0 +OP4 E00113 0 +OP4 E00114 0 +OP4 E00115 0 +OP4 E00116 0 +OP4 E00117 0 +OP4 E00118 0 +OP4 E00119 0 +OP4 E0011A 0 +OP4 E0011B 0 +OP4 E0011C 0 +OP4 E0011D 0 +OP4 E0011E 0 +OP4 E0011F 0 +OP4 E00120 0 +OP4 E00121 0 +OP4 E00122 0 +OP4 E00123 0 +OP4 E00124 0 +OP4 E00125 0 +OP4 E00126 0 +OP4 E00127 0 +OP4 E00128 0 +OP4 E00129 0 +OP4 E0012A 0 +OP4 E0012B 0 +OP4 E0012C 0 +OP4 E0012D 0 +OP4 E0012E 0 +OP4 E0012F 0 +OP4 E00130 0 +OP4 E00131 0 +OP4 E00132 0 +OP4 E00133 0 +OP4 E00134 0 +OP4 E00135 0 +OP4 E00136 0 +OP4 E00137 0 +OP4 E00138 0 +OP4 E00139 0 +OP4 E0013A 0 +OP4 E0013B 0 +OP4 E0013C 0 +OP4 E0013D 0 +OP4 E0013E 0 +OP4 E0013F 0 +OP4 E00140 0 +OP4 E00141 0 +OP4 E00142 0 +OP4 E00143 0 +OP4 E00144 0 +OP4 E00145 0 +OP4 E00146 0 +OP4 E00147 0 +OP4 E00148 0 +OP4 E00149 0 +OP4 E0014A 0 +OP4 E0014B 0 +OP4 E0014C 0 +OP4 E0014D 0 +OP4 E0014E 0 +OP4 E0014F 0 +OP4 E00150 0 +OP4 E00151 0 +OP4 E00152 0 +OP4 E00153 0 +OP4 E00154 0 +OP4 E00155 0 +OP4 E00156 0 +OP4 E00157 0 +OP4 E00158 0 +OP4 E00159 0 +OP4 E0015A 0 +OP4 E0015B 0 +OP4 E0015C 0 +OP4 E0015D 0 +OP4 E0015E 0 +OP4 E0015F 0 +OP4 E00160 0 +OP4 E00161 0 +OP4 E00162 0 +OP4 E00163 0 +OP4 E00164 0 +OP4 E00165 0 +OP4 E00166 0 +OP4 E00167 0 +OP4 E00168 0 +OP4 E00169 0 +OP4 E0016A 0 +OP4 E0016B 0 +OP4 E0016C 0 +OP4 E0016D 0 +OP4 E0016E 0 +OP4 E0016F 0 +OP4 E00170 0 +OP4 E00171 0 +OP4 E00172 0 +OP4 E00173 0 +OP4 E00174 0 +OP4 E00175 0 +OP4 E00176 0 +OP4 E00177 0 +OP4 E00178 0 +OP4 E00179 0 +OP4 E0017A 0 +OP4 E0017B 0 +OP4 E0017C 0 +OP4 E0017D 0 +OP4 E0017E 0 +OP4 E0017F 0 +OP4 E00180 0 +OP4 E00181 0 +OP4 E00182 0 +OP4 E00183 0 +OP4 E00184 0 +OP4 E00185 0 +OP4 E00186 0 +OP4 E00187 0 +OP4 E00188 0 +OP4 E00189 0 +OP4 E0018A 0 +OP4 E0018B 0 +OP4 E0018C 0 +OP4 E0018D 0 +OP4 E0018E 0 +OP4 E0018F 0 +OP4 E00190 0 +OP4 E00191 0 +OP4 E00192 0 +OP4 E00193 0 +OP4 E00194 0 +OP4 E00195 0 +OP4 E00196 0 +OP4 E00197 0 +OP4 E00198 0 +OP4 E00199 0 +OP4 E0019A 0 +OP4 E0019B 0 +OP4 E0019C 0 +OP4 E0019D 0 +OP4 E0019E 0 +OP4 E0019F 0 +OP4 E001A0 0 +OP4 E001A1 0 +OP4 E001A2 0 +OP4 E001A3 0 +OP4 E001A4 0 +OP4 E001A5 0 +OP4 E001A6 0 +OP4 E001A7 0 +OP4 E001A8 0 +OP4 E001A9 0 +OP4 E001AA 0 +OP4 E001AB 0 +OP4 E001AC 0 +OP4 E001AD 0 +OP4 E001AE 0 +OP4 E001AF 0 +OP4 E001B0 0 +OP4 E001B1 0 +OP4 E001B2 0 +OP4 E001B3 0 +OP4 E001B4 0 +OP4 E001B5 0 +OP4 E001B6 0 +OP4 E001B7 0 +OP4 E001B8 0 +OP4 E001B9 0 +OP4 E001BA 0 +OP4 E001BB 0 +OP4 E001BC 0 +OP4 E001BD 0 +OP4 E001BE 0 +OP4 E001BF 0 +OP4 E001C0 0 +OP4 E001C1 0 +OP4 E001C2 0 +OP4 E001C3 0 +OP4 E001C4 0 +OP4 E001C5 0 +OP4 E001C6 0 +OP4 E001C7 0 +OP4 E001C8 0 +OP4 E001C9 0 +OP4 E001CA 0 +OP4 E001CB 0 +OP4 E001CC 0 +OP4 E001CD 0 +OP4 E001CE 0 +OP4 E001CF 0 +OP4 E001D0 0 +OP4 E001D1 0 +OP4 E001D2 0 +OP4 E001D3 0 +OP4 E001D4 0 +OP4 E001D5 0 +OP4 E001D6 0 +OP4 E001D7 0 +OP4 E001D8 0 +OP4 E001D9 0 +OP4 E001DA 0 +OP4 E001DB 0 +OP4 E001DC 0 +OP4 E001DD 0 +OP4 E001DE 0 +OP4 E001DF 0 +OP4 E001E0 0 +OP4 E001E1 0 +OP4 E001E2 0 +OP4 E001E3 0 +OP4 E001E4 0 +OP4 E001E5 0 +OP4 E001E6 0 +OP4 E001E7 0 +OP4 E001E8 0 +OP4 E001E9 0 +OP4 E001EA 0 +OP4 E001EB 0 +OP4 E001EC 0 +OP4 E001ED 0 +OP4 E001EE 0 +OP4 E001EF 0 +OP4 E001F0 0 +OP4 E001F1 0 +OP4 E001F2 0 +OP4 E001F3 0 +OP4 E001F4 0 +OP4 E001F5 0 +OP4 E001F6 0 +OP4 E001F7 0 +OP4 E001F8 0 +OP4 E001F9 0 +OP4 E001FA 0 +OP4 E001FB 0 +OP4 E001FC 0 +OP4 E001FD 0 +OP4 E001FE 0 +OP4 E001FF 0 +OP4 E00200 0 +OP4 E00201 0 +OP4 E00202 0 +OP4 E00203 0 +OP4 E00204 0 +OP4 E00205 0 +OP4 E00206 0 +OP4 E00207 0 +OP4 E00208 0 +OP4 E00209 0 +OP4 E0020A 0 +OP4 E0020B 0 +OP4 E0020C 0 +OP4 E0020D 0 +OP4 E0020E 0 +OP4 E0020F 0 +OP4 E00210 0 +OP4 E00211 0 +OP4 E00212 0 +OP4 E00213 0 +OP4 E00214 0 +OP4 E00215 0 +OP4 E00216 0 +OP4 E00217 0 +OP4 E00218 0 +OP4 E00219 0 +OP4 E0021A 0 +OP4 E0021B 0 +OP4 E0021C 0 +OP4 E0021D 0 +OP4 E0021E 0 +OP4 E0021F 0 +OP4 E00220 0 +OP4 E00221 0 +OP4 E00222 0 +OP4 E00223 0 +OP4 E00224 0 +OP4 E00225 0 +OP4 E00226 0 +OP4 E00227 0 +OP4 E00228 0 +OP4 E00229 0 +OP4 E0022A 0 +OP4 E0022B 0 +OP4 E0022C 0 +OP4 E0022D 0 +OP4 E0022E 0 +OP4 E0022F 0 +OP4 E00230 0 +OP4 E00231 0 +OP4 E00232 0 +OP4 E00233 0 +OP4 E00234 0 +OP4 E00235 0 +OP4 E00236 0 +OP4 E00237 0 +OP4 E00238 0 +OP4 E00239 0 +OP4 E0023A 0 +OP4 E0023B 0 +OP4 E0023C 0 +OP4 E0023D 0 +OP4 E0023E 0 +OP4 E0023F 0 +OP4 E00240 0 +OP4 E00241 0 +OP4 E00242 0 +OP4 E00243 0 +OP4 E00244 0 +OP4 E00245 0 +OP4 E00246 0 +OP4 E00247 0 +OP4 E00248 0 +OP4 E00249 0 +OP4 E0024A 0 +OP4 E0024B 0 +OP4 E0024C 0 +OP4 E0024D 0 +OP4 E0024E 0 +OP4 E0024F 0 +OP4 E00250 0 +OP4 E00251 0 +OP4 E00252 0 +OP4 E00253 0 +OP4 E00254 0 +OP4 E00255 0 +OP4 E00256 0 +OP4 E00257 0 +OP4 E00258 0 +OP4 E00259 0 +OP4 E0025A 0 +OP4 E0025B 0 +OP4 E0025C 0 +OP4 E0025D 0 +OP4 E0025E 0 +OP4 E0025F 0 +OP4 E00260 0 +OP4 E00261 0 +OP4 E00262 0 +OP4 E00263 0 +OP4 E00264 0 +OP4 E00265 0 +OP4 E00266 0 +OP4 E00267 0 +OP4 E00268 0 +OP4 E00269 0 +OP4 E0026A 0 +OP4 E0026B 0 +OP4 E0026C 0 +OP4 E0026D 0 +OP4 E0026E 0 +OP4 E0026F 0 +OP4 E00270 0 +OP4 E00271 0 +OP4 E00272 0 +OP4 E00273 0 +OP4 E00274 0 +OP4 E00275 0 +OP4 E00276 0 +OP4 E00277 0 +OP4 E00278 0 +OP4 E00279 0 +OP4 E0027A 0 +OP4 E0027B 0 +OP4 E0027C 0 +OP4 E0027D 0 +OP4 E0027E 0 +OP4 E0027F 0 +OP4 E00280 0 +OP4 E00281 0 +OP4 E00282 0 +OP4 E00283 0 +OP4 E00284 0 +OP4 E00285 0 +OP4 E00286 0 +OP4 E00287 0 +OP4 E00288 0 +OP4 E00289 0 +OP4 E0028A 0 +OP4 E0028B 0 +OP4 E0028C 0 +OP4 E0028D 0 +OP4 E0028E 0 +OP4 E0028F 0 +OP4 E00290 0 +OP4 E00291 0 +OP4 E00292 0 +OP4 E00293 0 +OP4 E00294 0 +OP4 E00295 0 +OP4 E00296 0 +OP4 E00297 0 +OP4 E00298 0 +OP4 E00299 0 +OP4 E0029A 0 +OP4 E0029B 0 +OP4 E0029C 0 +OP4 E0029D 0 +OP4 E0029E 0 +OP4 E0029F 0 +OP4 E002A0 0 +OP4 E002A1 0 +OP4 E002A2 0 +OP4 E002A3 0 +OP4 E002A4 0 +OP4 E002A5 0 +OP4 E002A6 0 +OP4 E002A7 0 +OP4 E002A8 0 +OP4 E002A9 0 +OP4 E002AA 0 +OP4 E002AB 0 +OP4 E002AC 0 +OP4 E002AD 0 +OP4 E002AE 0 +OP4 E002AF 0 +OP4 E002B0 0 +OP4 E002B1 0 +OP4 E002B2 0 +OP4 E002B3 0 +OP4 E002B4 0 +OP4 E002B5 0 +OP4 E002B6 0 +OP4 E002B7 0 +OP4 E002B8 0 +OP4 E002B9 0 +OP4 E002BA 0 +OP4 E002BB 0 +OP4 E002BC 0 +OP4 E002BD 0 +OP4 E002BE 0 +OP4 E002BF 0 +OP4 E002C0 0 +OP4 E002C1 0 +OP4 E002C2 0 +OP4 E002C3 0 +OP4 E002C4 0 +OP4 E002C5 0 +OP4 E002C6 0 +OP4 E002C7 0 +OP4 E002C8 0 +OP4 E002C9 0 +OP4 E002CA 0 +OP4 E002CB 0 +OP4 E002CC 0 +OP4 E002CD 0 +OP4 E002CE 0 +OP4 E002CF 0 +OP4 E002D0 0 +OP4 E002D1 0 +OP4 E002D2 0 +OP4 E002D3 0 +OP4 E002D4 0 +OP4 E002D5 0 +OP4 E002D6 0 +OP4 E002D7 0 +OP4 E002D8 0 +OP4 E002D9 0 +OP4 E002DA 0 +OP4 E002DB 0 +OP4 E002DC 0 +OP4 E002DD 0 +OP4 E002DE 0 +OP4 E002DF 0 +OP4 E002E0 0 +OP4 E002E1 0 +OP4 E002E2 0 +OP4 E002E3 0 +OP4 E002E4 0 +OP4 E002E5 0 +OP4 E002E6 0 +OP4 E002E7 0 +OP4 E002E8 0 +OP4 E002E9 0 +OP4 E002EA 0 +OP4 E002EB 0 +OP4 E002EC 0 +OP4 E002ED 0 +OP4 E002EE 0 +OP4 E002EF 0 +OP4 E002F0 0 +OP4 E002F1 0 +OP4 E002F2 0 +OP4 E002F3 0 +OP4 E002F4 0 +OP4 E002F5 0 +OP4 E002F6 0 +OP4 E002F7 0 +OP4 E002F8 0 +OP4 E002F9 0 +OP4 E002FA 0 +OP4 E002FB 0 +OP4 E002FC 0 +OP4 E002FD 0 +OP4 E002FE 0 +OP4 E002FF 0 +OP4 E00300 0 +OP4 E00301 0 +OP4 E00302 0 +OP4 E00303 0 +OP4 E00304 0 +OP4 E00305 0 +OP4 E00306 0 +OP4 E00307 0 +OP4 E00308 0 +OP4 E00309 0 +OP4 E0030A 0 +OP4 E0030B 0 +OP4 E0030C 0 +OP4 E0030D 0 +OP4 E0030E 0 +OP4 E0030F 0 +OP4 E00310 0 +OP4 E00311 0 +OP4 E00312 0 +OP4 E00313 0 +OP4 E00314 0 +OP4 E00315 0 +OP4 E00316 0 +OP4 E00317 0 +OP4 E00318 0 +OP4 E00319 0 +OP4 E0031A 0 +OP4 E0031B 0 +OP4 E0031C 0 +OP4 E0031D 0 +OP4 E0031E 0 +OP4 E0031F 0 +OP4 E00320 0 +OP4 E00321 0 +OP4 E00322 0 +OP4 E00323 0 +OP4 E00324 0 +OP4 E00325 0 +OP4 E00326 0 +OP4 E00327 0 +OP4 E00328 0 +OP4 E00329 0 +OP4 E0032A 0 +OP4 E0032B 0 +OP4 E0032C 0 +OP4 E0032D 0 +OP4 E0032E 0 +OP4 E0032F 0 +OP4 E00330 0 +OP4 E00331 0 +OP4 E00332 0 +OP4 E00333 0 +OP4 E00334 0 +OP4 E00335 0 +OP4 E00336 0 +OP4 E00337 0 +OP4 E00338 0 +OP4 E00339 0 +OP4 E0033A 0 +OP4 E0033B 0 +OP4 E0033C 0 +OP4 E0033D 0 +OP4 E0033E 0 +OP4 E0033F 0 +OP4 E00340 0 +OP4 E00341 0 +OP4 E00342 0 +OP4 E00343 0 +OP4 E00344 0 +OP4 E00345 0 +OP4 E00346 0 +OP4 E00347 0 +OP4 E00348 0 +OP4 E00349 0 +OP4 E0034A 0 +OP4 E0034B 0 +OP4 E0034C 0 +OP4 E0034D 0 +OP4 E0034E 0 +OP4 E0034F 0 +OP4 E00350 0 +OP4 E00351 0 +OP4 E00352 0 +OP4 E00353 0 +OP4 E00354 0 +OP4 E00355 0 +OP4 E00356 0 +OP4 E00357 0 +OP4 E00358 0 +OP4 E00359 0 +OP4 E0035A 0 +OP4 E0035B 0 +OP4 E0035C 0 +OP4 E0035D 0 +OP4 E0035E 0 +OP4 E0035F 0 +OP4 E00360 0 +OP4 E00361 0 +OP4 E00362 0 +OP4 E00363 0 +OP4 E00364 0 +OP4 E00365 0 +OP4 E00366 0 +OP4 E00367 0 +OP4 E00368 0 +OP4 E00369 0 +OP4 E0036A 0 +OP4 E0036B 0 +OP4 E0036C 0 +OP4 E0036D 0 +OP4 E0036E 0 +OP4 E0036F 0 +OP4 E00370 0 +OP4 E00371 0 +OP4 E00372 0 +OP4 E00373 0 +OP4 E00374 0 +OP4 E00375 0 +OP4 E00376 0 +OP4 E00377 0 +OP4 E00378 0 +OP4 E00379 0 +OP4 E0037A 0 +OP4 E0037B 0 +OP4 E0037C 0 +OP4 E0037D 0 +OP4 E0037E 0 +OP4 E0037F 0 +OP4 E00380 0 +OP4 E00381 0 +OP4 E00382 0 +OP4 E00383 0 +OP4 E00384 0 +OP4 E00385 0 +OP4 E00386 0 +OP4 E00387 0 +OP4 E00388 0 +OP4 E00389 0 +OP4 E0038A 0 +OP4 E0038B 0 +OP4 E0038C 0 +OP4 E0038D 0 +OP4 E0038E 0 +OP4 E0038F 0 +OP4 E00390 0 +OP4 E00391 0 +OP4 E00392 0 +OP4 E00393 0 +OP4 E00394 0 +OP4 E00395 0 +OP4 E00396 0 +OP4 E00397 0 +OP4 E00398 0 +OP4 E00399 0 +OP4 E0039A 0 +OP4 E0039B 0 +OP4 E0039C 0 +OP4 E0039D 0 +OP4 E0039E 0 +OP4 E0039F 0 +OP4 E003A0 0 +OP4 E003A1 0 +OP4 E003A2 0 +OP4 E003A3 0 +OP4 E003A4 0 +OP4 E003A5 0 +OP4 E003A6 0 +OP4 E003A7 0 +OP4 E003A8 0 +OP4 E003A9 0 +OP4 E003AA 0 +OP4 E003AB 0 +OP4 E003AC 0 +OP4 E003AD 0 +OP4 E003AE 0 +OP4 E003AF 0 +OP4 E003B0 0 +OP4 E003B1 0 +OP4 E003B2 0 +OP4 E003B3 0 +OP4 E003B4 0 +OP4 E003B5 0 +OP4 E003B6 0 +OP4 E003B7 0 +OP4 E003B8 0 +OP4 E003B9 0 +OP4 E003BA 0 +OP4 E003BB 0 +OP4 E003BC 0 +OP4 E003BD 0 +OP4 E003BE 0 +OP4 E003BF 0 +OP4 E003C0 0 +OP4 E003C1 0 +OP4 E003C2 0 +OP4 E003C3 0 +OP4 E003C4 0 +OP4 E003C5 0 +OP4 E003C6 0 +OP4 E003C7 0 +OP4 E003C8 0 +OP4 E003C9 0 +OP4 E003CA 0 +OP4 E003CB 0 +OP4 E003CC 0 +OP4 E003CD 0 +OP4 E003CE 0 +OP4 E003CF 0 +OP4 E003D0 0 +OP4 E003D1 0 +OP4 E003D2 0 +OP4 E003D3 0 +OP4 E003D4 0 +OP4 E003D5 0 +OP4 E003D6 0 +OP4 E003D7 0 +OP4 E003D8 0 +OP4 E003D9 0 +OP4 E003DA 0 +OP4 E003DB 0 +OP4 E003DC 0 +OP4 E003DD 0 +OP4 E003DE 0 +OP4 E003DF 0 +OP4 E003E0 0 +OP4 E003E1 0 +OP4 E003E2 0 +OP4 E003E3 0 +OP4 E003E4 0 +OP4 E003E5 0 +OP4 E003E6 0 +OP4 E003E7 0 +OP4 E003E8 0 +OP4 E003E9 0 +OP4 E003EA 0 +OP4 E003EB 0 +OP4 E003EC 0 +OP4 E003ED 0 +OP4 E003EE 0 +OP4 E003EF 0 +OP4 E003F0 0 +OP4 E003F1 0 +OP4 E003F2 0 +OP4 E003F3 0 +OP4 E003F4 0 +OP4 E003F5 0 +OP4 E003F6 0 +OP4 E003F7 0 +OP4 E003F8 0 +OP4 E003F9 0 +OP4 E003FA 0 +OP4 E003FB 0 +OP4 E003FC 0 +OP4 E003FD 0 +OP4 E003FE 0 +OP4 E003FF 0 +OP4 E00400 0 +OP4 E00401 0 +OP4 E00402 0 +OP4 E00403 0 +OP4 E00404 0 +OP4 E00405 0 +OP4 E00406 0 +OP4 E00407 0 +OP4 E00408 0 +OP4 E00409 0 +OP4 E0040A 0 +OP4 E0040B 0 +OP4 E0040C 0 +OP4 E0040D 0 +OP4 E0040E 0 +OP4 E0040F 0 +OP4 E00410 0 +OP4 E00411 0 +OP4 E00412 0 +OP4 E00413 0 +OP4 E00414 0 +OP4 E00415 0 +OP4 E00416 0 +OP4 E00417 0 +OP4 E00418 0 +OP4 E00419 0 +OP4 E0041A 0 +OP4 E0041B 0 +OP4 E0041C 0 +OP4 E0041D 0 +OP4 E0041E 0 +OP4 E0041F 0 +OP4 E00420 0 +OP4 E00421 0 +OP4 E00422 0 +OP4 E00423 0 +OP4 E00424 0 +OP4 E00425 0 +OP4 E00426 0 +OP4 E00427 0 +OP4 E00428 0 +OP4 E00429 0 +OP4 E0042A 0 +OP4 E0042B 0 +OP4 E0042C 0 +OP4 E0042D 0 +OP4 E0042E 0 +OP4 E0042F 0 +OP4 E00430 0 +OP4 E00431 0 +OP4 E00432 0 +OP4 E00433 0 +OP4 E00434 0 +OP4 E00435 0 +OP4 E00436 0 +OP4 E00437 0 +OP4 E00438 0 +OP4 E00439 0 +OP4 E0043A 0 +OP4 E0043B 0 +OP4 E0043C 0 +OP4 E0043D 0 +OP4 E0043E 0 +OP4 E0043F 0 +OP4 E00440 0 +OP4 E00441 0 +OP4 E00442 0 +OP4 E00443 0 +OP4 E00444 0 +OP4 E00445 0 +OP4 E00446 0 +OP4 E00447 0 +OP4 E00448 0 +OP4 E00449 0 +OP4 E0044A 0 +OP4 E0044B 0 +OP4 E0044C 0 +OP4 E0044D 0 +OP4 E0044E 0 +OP4 E0044F 0 +OP4 E00450 0 +OP4 E00451 0 +OP4 E00452 0 +OP4 E00453 0 +OP4 E00454 0 +OP4 E00455 0 +OP4 E00456 0 +OP4 E00457 0 +OP4 E00458 0 +OP4 E00459 0 +OP4 E0045A 0 +OP4 E0045B 0 +OP4 E0045C 0 +OP4 E0045D 0 +OP4 E0045E 0 +OP4 E0045F 0 +OP4 E00460 0 +OP4 E00461 0 +OP4 E00462 0 +OP4 E00463 0 +OP4 E00464 0 +OP4 E00465 0 +OP4 E00466 0 +OP4 E00467 0 +OP4 E00468 0 +OP4 E00469 0 +OP4 E0046A 0 +OP4 E0046B 0 +OP4 E0046C 0 +OP4 E0046D 0 +OP4 E0046E 0 +OP4 E0046F 0 +OP4 E00470 0 +OP4 E00471 0 +OP4 E00472 0 +OP4 E00473 0 +OP4 E00474 0 +OP4 E00475 0 +OP4 E00476 0 +OP4 E00477 0 +OP4 E00478 0 +OP4 E00479 0 +OP4 E0047A 0 +OP4 E0047B 0 +OP4 E0047C 0 +OP4 E0047D 0 +OP4 E0047E 0 +OP4 E0047F 0 +OP4 E00480 0 +OP4 E00481 0 +OP4 E00482 0 +OP4 E00483 0 +OP4 E00484 0 +OP4 E00485 0 +OP4 E00486 0 +OP4 E00487 0 +OP4 E00488 0 +OP4 E00489 0 +OP4 E0048A 0 +OP4 E0048B 0 +OP4 E0048C 0 +OP4 E0048D 0 +OP4 E0048E 0 +OP4 E0048F 0 +OP4 E00490 0 +OP4 E00491 0 +OP4 E00492 0 +OP4 E00493 0 +OP4 E00494 0 +OP4 E00495 0 +OP4 E00496 0 +OP4 E00497 0 +OP4 E00498 0 +OP4 E00499 0 +OP4 E0049A 0 +OP4 E0049B 0 +OP4 E0049C 0 +OP4 E0049D 0 +OP4 E0049E 0 +OP4 E0049F 0 +OP4 E004A0 0 +OP4 E004A1 0 +OP4 E004A2 0 +OP4 E004A3 0 +OP4 E004A4 0 +OP4 E004A5 0 +OP4 E004A6 0 +OP4 E004A7 0 +OP4 E004A8 0 +OP4 E004A9 0 +OP4 E004AA 0 +OP4 E004AB 0 +OP4 E004AC 0 +OP4 E004AD 0 +OP4 E004AE 0 +OP4 E004AF 0 +OP4 E004B0 0 +OP4 E004B1 0 +OP4 E004B2 0 +OP4 E004B3 0 +OP4 E004B4 0 +OP4 E004B5 0 +OP4 E004B6 0 +OP4 E004B7 0 +OP4 E004B8 0 +OP4 E004B9 0 +OP4 E004BA 0 +OP4 E004BB 0 +OP4 E004BC 0 +OP4 E004BD 0 +OP4 E004BE 0 +OP4 E004BF 0 +OP4 E004C0 0 +OP4 E004C1 0 +OP4 E004C2 0 +OP4 E004C3 0 +OP4 E004C4 0 +OP4 E004C5 0 +OP4 E004C6 0 +OP4 E004C7 0 +OP4 E004C8 0 +OP4 E004C9 0 +OP4 E004CA 0 +OP4 E004CB 0 +OP4 E004CC 0 +OP4 E004CD 0 +OP4 E004CE 0 +OP4 E004CF 0 +OP4 E004D0 0 +OP4 E004D1 0 +OP4 E004D2 0 +OP4 E004D3 0 +OP4 E004D4 0 +OP4 E004D5 0 +OP4 E004D6 0 +OP4 E004D7 0 +OP4 E004D8 0 +OP4 E004D9 0 +OP4 E004DA 0 +OP4 E004DB 0 +OP4 E004DC 0 +OP4 E004DD 0 +OP4 E004DE 0 +OP4 E004DF 0 +OP4 E004E0 0 +OP4 E004E1 0 +OP4 E004E2 0 +OP4 E004E3 0 +OP4 E004E4 0 +OP4 E004E5 0 +OP4 E004E6 0 +OP4 E004E7 0 +OP4 E004E8 0 +OP4 E004E9 0 +OP4 E004EA 0 +OP4 E004EB 0 +OP4 E004EC 0 +OP4 E004ED 0 +OP4 E004EE 0 +OP4 E004EF 0 +OP4 E004F0 0 +OP4 E004F1 0 +OP4 E004F2 0 +OP4 E004F3 0 +OP4 E004F4 0 +OP4 E004F5 0 +OP4 E004F6 0 +OP4 E004F7 0 +OP4 E004F8 0 +OP4 E004F9 0 +OP4 E004FA 0 +OP4 E004FB 0 +OP4 E004FC 0 +OP4 E004FD 0 +OP4 E004FE 0 +OP4 E004FF 0 +OP4 E00500 0 +OP4 E00501 0 +OP4 E00502 0 +OP4 E00503 0 +OP4 E00504 0 +OP4 E00505 0 +OP4 E00506 0 +OP4 E00507 0 +OP4 E00508 0 +OP4 E00509 0 +OP4 E0050A 0 +OP4 E0050B 0 +OP4 E0050C 0 +OP4 E0050D 0 +OP4 E0050E 0 +OP4 E0050F 0 +OP4 E00510 0 +OP4 E00511 0 +OP4 E00512 0 +OP4 E00513 0 +OP4 E00514 0 +OP4 E00515 0 +OP4 E00516 0 +OP4 E00517 0 +OP4 E00518 0 +OP4 E00519 0 +OP4 E0051A 0 +OP4 E0051B 0 +OP4 E0051C 0 +OP4 E0051D 0 +OP4 E0051E 0 +OP4 E0051F 0 +OP4 E00520 0 +OP4 E00521 0 +OP4 E00522 0 +OP4 E00523 0 +OP4 E00524 0 +OP4 E00525 0 +OP4 E00526 0 +OP4 E00527 0 +OP4 E00528 0 +OP4 E00529 0 +OP4 E0052A 0 +OP4 E0052B 0 +OP4 E0052C 0 +OP4 E0052D 0 +OP4 E0052E 0 +OP4 E0052F 0 +OP4 E00530 0 +OP4 E00531 0 +OP4 E00532 0 +OP4 E00533 0 +OP4 E00534 0 +OP4 E00535 0 +OP4 E00536 0 +OP4 E00537 0 +OP4 E00538 0 +OP4 E00539 0 +OP4 E0053A 0 +OP4 E0053B 0 +OP4 E0053C 0 +OP4 E0053D 0 +OP4 E0053E 0 +OP4 E0053F 0 +OP4 E00540 0 +OP4 E00541 0 +OP4 E00542 0 +OP4 E00543 0 +OP4 E00544 0 +OP4 E00545 0 +OP4 E00546 0 +OP4 E00547 0 +OP4 E00548 0 +OP4 E00549 0 +OP4 E0054A 0 +OP4 E0054B 0 +OP4 E0054C 0 +OP4 E0054D 0 +OP4 E0054E 0 +OP4 E0054F 0 +OP4 E00550 0 +OP4 E00551 0 +OP4 E00552 0 +OP4 E00553 0 +OP4 E00554 0 +OP4 E00555 0 +OP4 E00556 0 +OP4 E00557 0 +OP4 E00558 0 +OP4 E00559 0 +OP4 E0055A 0 +OP4 E0055B 0 +OP4 E0055C 0 +OP4 E0055D 0 +OP4 E0055E 0 +OP4 E0055F 0 +OP4 E00560 0 +OP4 E00561 0 +OP4 E00562 0 +OP4 E00563 0 +OP4 E00564 0 +OP4 E00565 0 +OP4 E00566 0 +OP4 E00567 0 +OP4 E00568 0 +OP4 E00569 0 +OP4 E0056A 0 +OP4 E0056B 0 +OP4 E0056C 0 +OP4 E0056D 0 +OP4 E0056E 0 +OP4 E0056F 0 +OP4 E00570 0 +OP4 E00571 0 +OP4 E00572 0 +OP4 E00573 0 +OP4 E00574 0 +OP4 E00575 0 +OP4 E00576 0 +OP4 E00577 0 +OP4 E00578 0 +OP4 E00579 0 +OP4 E0057A 0 +OP4 E0057B 0 +OP4 E0057C 0 +OP4 E0057D 0 +OP4 E0057E 0 +OP4 E0057F 0 +OP4 E00580 0 +OP4 E00581 0 +OP4 E00582 0 +OP4 E00583 0 +OP4 E00584 0 +OP4 E00585 0 +OP4 E00586 0 +OP4 E00587 0 +OP4 E00588 0 +OP4 E00589 0 +OP4 E0058A 0 +OP4 E0058B 0 +OP4 E0058C 0 +OP4 E0058D 0 +OP4 E0058E 0 +OP4 E0058F 0 +OP4 E00590 0 +OP4 E00591 0 +OP4 E00592 0 +OP4 E00593 0 +OP4 E00594 0 +OP4 E00595 0 +OP4 E00596 0 +OP4 E00597 0 +OP4 E00598 0 +OP4 E00599 0 +OP4 E0059A 0 +OP4 E0059B 0 +OP4 E0059C 0 +OP4 E0059D 0 +OP4 E0059E 0 +OP4 E0059F 0 +OP4 E005A0 0 +OP4 E005A1 0 +OP4 E005A2 0 +OP4 E005A3 0 +OP4 E005A4 0 +OP4 E005A5 0 +OP4 E005A6 0 +OP4 E005A7 0 +OP4 E005A8 0 +OP4 E005A9 0 +OP4 E005AA 0 +OP4 E005AB 0 +OP4 E005AC 0 +OP4 E005AD 0 +OP4 E005AE 0 +OP4 E005AF 0 +OP4 E005B0 0 +OP4 E005B1 0 +OP4 E005B2 0 +OP4 E005B3 0 +OP4 E005B4 0 +OP4 E005B5 0 +OP4 E005B6 0 +OP4 E005B7 0 +OP4 E005B8 0 +OP4 E005B9 0 +OP4 E005BA 0 +OP4 E005BB 0 +OP4 E005BC 0 +OP4 E005BD 0 +OP4 E005BE 0 +OP4 E005BF 0 +OP4 E005C0 0 +OP4 E005C1 0 +OP4 E005C2 0 +OP4 E005C3 0 +OP4 E005C4 0 +OP4 E005C5 0 +OP4 E005C6 0 +OP4 E005C7 0 +OP4 E005C8 0 +OP4 E005C9 0 +OP4 E005CA 0 +OP4 E005CB 0 +OP4 E005CC 0 +OP4 E005CD 0 +OP4 E005CE 0 +OP4 E005CF 0 +OP4 E005D0 0 +OP4 E005D1 0 +OP4 E005D2 0 +OP4 E005D3 0 +OP4 E005D4 0 +OP4 E005D5 0 +OP4 E005D6 0 +OP4 E005D7 0 +OP4 E005D8 0 +OP4 E005D9 0 +OP4 E005DA 0 +OP4 E005DB 0 +OP4 E005DC 0 +OP4 E005DD 0 +OP4 E005DE 0 +OP4 E005DF 0 +OP4 E005E0 0 +OP4 E005E1 0 +OP4 E005E2 0 +OP4 E005E3 0 +OP4 E005E4 0 +OP4 E005E5 0 +OP4 E005E6 0 +OP4 E005E7 0 +OP4 E005E8 0 +OP4 E005E9 0 +OP4 E005EA 0 +OP4 E005EB 0 +OP4 E005EC 0 +OP4 E005ED 0 +OP4 E005EE 0 +OP4 E005EF 0 +OP4 E005F0 0 +OP4 E005F1 0 +OP4 E005F2 0 +OP4 E005F3 0 +OP4 E005F4 0 +OP4 E005F5 0 +OP4 E005F6 0 +OP4 E005F7 0 +OP4 E005F8 0 +OP4 E005F9 0 +OP4 E005FA 0 +OP4 E005FB 0 +OP4 E005FC 0 +OP4 E005FD 0 +OP4 E005FE 0 +OP4 E005FF 0 +OP4 E00600 0 +OP4 E00601 0 +OP4 E00602 0 +OP4 E00603 0 +OP4 E00604 0 +OP4 E00605 0 +OP4 E00606 0 +OP4 E00607 0 +OP4 E00608 0 +OP4 E00609 0 +OP4 E0060A 0 +OP4 E0060B 0 +OP4 E0060C 0 +OP4 E0060D 0 +OP4 E0060E 0 +OP4 E0060F 0 +OP4 E00610 0 +OP4 E00611 0 +OP4 E00612 0 +OP4 E00613 0 +OP4 E00614 0 +OP4 E00615 0 +OP4 E00616 0 +OP4 E00617 0 +OP4 E00618 0 +OP4 E00619 0 +OP4 E0061A 0 +OP4 E0061B 0 +OP4 E0061C 0 +OP4 E0061D 0 +OP4 E0061E 0 +OP4 E0061F 0 +OP4 E00620 0 +OP4 E00621 0 +OP4 E00622 0 +OP4 E00623 0 +OP4 E00624 0 +OP4 E00625 0 +OP4 E00626 0 +OP4 E00627 0 +OP4 E00628 0 +OP4 E00629 0 +OP4 E0062A 0 +OP4 E0062B 0 +OP4 E0062C 0 +OP4 E0062D 0 +OP4 E0062E 0 +OP4 E0062F 0 +OP4 E00630 0 +OP4 E00631 0 +OP4 E00632 0 +OP4 E00633 0 +OP4 E00634 0 +OP4 E00635 0 +OP4 E00636 0 +OP4 E00637 0 +OP4 E00638 0 +OP4 E00639 0 +OP4 E0063A 0 +OP4 E0063B 0 +OP4 E0063C 0 +OP4 E0063D 0 +OP4 E0063E 0 +OP4 E0063F 0 +OP4 E00640 0 +OP4 E00641 0 +OP4 E00642 0 +OP4 E00643 0 +OP4 E00644 0 +OP4 E00645 0 +OP4 E00646 0 +OP4 E00647 0 +OP4 E00648 0 +OP4 E00649 0 +OP4 E0064A 0 +OP4 E0064B 0 +OP4 E0064C 0 +OP4 E0064D 0 +OP4 E0064E 0 +OP4 E0064F 0 +OP4 E00650 0 +OP4 E00651 0 +OP4 E00652 0 +OP4 E00653 0 +OP4 E00654 0 +OP4 E00655 0 +OP4 E00656 0 +OP4 E00657 0 +OP4 E00658 0 +OP4 E00659 0 +OP4 E0065A 0 +OP4 E0065B 0 +OP4 E0065C 0 +OP4 E0065D 0 +OP4 E0065E 0 +OP4 E0065F 0 +OP4 E00660 0 +OP4 E00661 0 +OP4 E00662 0 +OP4 E00663 0 +OP4 E00664 0 +OP4 E00665 0 +OP4 E00666 0 +OP4 E00667 0 +OP4 E00668 0 +OP4 E00669 0 +OP4 E0066A 0 +OP4 E0066B 0 +OP4 E0066C 0 +OP4 E0066D 0 +OP4 E0066E 0 +OP4 E0066F 0 +OP4 E00670 0 +OP4 E00671 0 +OP4 E00672 0 +OP4 E00673 0 +OP4 E00674 0 +OP4 E00675 0 +OP4 E00676 0 +OP4 E00677 0 +OP4 E00678 0 +OP4 E00679 0 +OP4 E0067A 0 +OP4 E0067B 0 +OP4 E0067C 0 +OP4 E0067D 0 +OP4 E0067E 0 +OP4 E0067F 0 +OP4 E00680 0 +OP4 E00681 0 +OP4 E00682 0 +OP4 E00683 0 +OP4 E00684 0 +OP4 E00685 0 +OP4 E00686 0 +OP4 E00687 0 +OP4 E00688 0 +OP4 E00689 0 +OP4 E0068A 0 +OP4 E0068B 0 +OP4 E0068C 0 +OP4 E0068D 0 +OP4 E0068E 0 +OP4 E0068F 0 +OP4 E00690 0 +OP4 E00691 0 +OP4 E00692 0 +OP4 E00693 0 +OP4 E00694 0 +OP4 E00695 0 +OP4 E00696 0 +OP4 E00697 0 +OP4 E00698 0 +OP4 E00699 0 +OP4 E0069A 0 +OP4 E0069B 0 +OP4 E0069C 0 +OP4 E0069D 0 +OP4 E0069E 0 +OP4 E0069F 0 +OP4 E006A0 0 +OP4 E006A1 0 +OP4 E006A2 0 +OP4 E006A3 0 +OP4 E006A4 0 +OP4 E006A5 0 +OP4 E006A6 0 +OP4 E006A7 0 +OP4 E006A8 0 +OP4 E006A9 0 +OP4 E006AA 0 +OP4 E006AB 0 +OP4 E006AC 0 +OP4 E006AD 0 +OP4 E006AE 0 +OP4 E006AF 0 +OP4 E006B0 0 +OP4 E006B1 0 +OP4 E006B2 0 +OP4 E006B3 0 +OP4 E006B4 0 +OP4 E006B5 0 +OP4 E006B6 0 +OP4 E006B7 0 +OP4 E006B8 0 +OP4 E006B9 0 +OP4 E006BA 0 +OP4 E006BB 0 +OP4 E006BC 0 +OP4 E006BD 0 +OP4 E006BE 0 +OP4 E006BF 0 +OP4 E006C0 0 +OP4 E006C1 0 +OP4 E006C2 0 +OP4 E006C3 0 +OP4 E006C4 0 +OP4 E006C5 0 +OP4 E006C6 0 +OP4 E006C7 0 +OP4 E006C8 0 +OP4 E006C9 0 +OP4 E006CA 0 +OP4 E006CB 0 +OP4 E006CC 0 +OP4 E006CD 0 +OP4 E006CE 0 +OP4 E006CF 0 +OP4 E006D0 0 +OP4 E006D1 0 +OP4 E006D2 0 +OP4 E006D3 0 +OP4 E006D4 0 +OP4 E006D5 0 +OP4 E006D6 0 +OP4 E006D7 0 +OP4 E006D8 0 +OP4 E006D9 0 +OP4 E006DA 0 +OP4 E006DB 0 +OP4 E006DC 0 +OP4 E006DD 0 +OP4 E006DE 0 +OP4 E006DF 0 +OP4 E006E0 0 +OP4 E006E1 0 +OP4 E006E2 0 +OP4 E006E3 0 +OP4 E006E4 0 +OP4 E006E5 0 +OP4 E006E6 0 +OP4 E006E7 0 +OP4 E006E8 0 +OP4 E006E9 0 +OP4 E006EA 0 +OP4 E006EB 0 +OP4 E006EC 0 +OP4 E006ED 0 +OP4 E006EE 0 +OP4 E006EF 0 +OP4 E006F0 0 +OP4 E006F1 0 +OP4 E006F2 0 +OP4 E006F3 0 +OP4 E006F4 0 +OP4 E006F5 0 +OP4 E006F6 0 +OP4 E006F7 0 +OP4 E006F8 0 +OP4 E006F9 0 +OP4 E006FA 0 +OP4 E006FB 0 +OP4 E006FC 0 +OP4 E006FD 0 +OP4 E006FE 0 +OP4 E006FF 0 +OP4 E00700 0 +OP4 E00701 0 +OP4 E00702 0 +OP4 E00703 0 +OP4 E00704 0 +OP4 E00705 0 +OP4 E00706 0 +OP4 E00707 0 +OP4 E00708 0 +OP4 E00709 0 +OP4 E0070A 0 +OP4 E0070B 0 +OP4 E0070C 0 +OP4 E0070D 0 +OP4 E0070E 0 +OP4 E0070F 0 +OP4 E00710 0 +OP4 E00711 0 +OP4 E00712 0 +OP4 E00713 0 +OP4 E00714 0 +OP4 E00715 0 +OP4 E00716 0 +OP4 E00717 0 +OP4 E00718 0 +OP4 E00719 0 +OP4 E0071A 0 +OP4 E0071B 0 +OP4 E0071C 0 +OP4 E0071D 0 +OP4 E0071E 0 +OP4 E0071F 0 +OP4 E00720 0 +OP4 E00721 0 +OP4 E00722 0 +OP4 E00723 0 +OP4 E00724 0 +OP4 E00725 0 +OP4 E00726 0 +OP4 E00727 0 +OP4 E00728 0 +OP4 E00729 0 +OP4 E0072A 0 +OP4 E0072B 0 +OP4 E0072C 0 +OP4 E0072D 0 +OP4 E0072E 0 +OP4 E0072F 0 +OP4 E00730 0 +OP4 E00731 0 +OP4 E00732 0 +OP4 E00733 0 +OP4 E00734 0 +OP4 E00735 0 +OP4 E00736 0 +OP4 E00737 0 +OP4 E00738 0 +OP4 E00739 0 +OP4 E0073A 0 +OP4 E0073B 0 +OP4 E0073C 0 +OP4 E0073D 0 +OP4 E0073E 0 +OP4 E0073F 0 +OP4 E00740 0 +OP4 E00741 0 +OP4 E00742 0 +OP4 E00743 0 +OP4 E00744 0 +OP4 E00745 0 +OP4 E00746 0 +OP4 E00747 0 +OP4 E00748 0 +OP4 E00749 0 +OP4 E0074A 0 +OP4 E0074B 0 +OP4 E0074C 0 +OP4 E0074D 0 +OP4 E0074E 0 +OP4 E0074F 0 +OP4 E00750 0 +OP4 E00751 0 +OP4 E00752 0 +OP4 E00753 0 +OP4 E00754 0 +OP4 E00755 0 +OP4 E00756 0 +OP4 E00757 0 +OP4 E00758 0 +OP4 E00759 0 +OP4 E0075A 0 +OP4 E0075B 0 +OP4 E0075C 0 +OP4 E0075D 0 +OP4 E0075E 0 +OP4 E0075F 0 +OP4 E00760 0 +OP4 E00761 0 +OP4 E00762 0 +OP4 E00763 0 +OP4 E00764 0 +OP4 E00765 0 +OP4 E00766 0 +OP4 E00767 0 +OP4 E00768 0 +OP4 E00769 0 +OP4 E0076A 0 +OP4 E0076B 0 +OP4 E0076C 0 +OP4 E0076D 0 +OP4 E0076E 0 +OP4 E0076F 0 +OP4 E00770 0 +OP4 E00771 0 +OP4 E00772 0 +OP4 E00773 0 +OP4 E00774 0 +OP4 E00775 0 +OP4 E00776 0 +OP4 E00777 0 +OP4 E00778 0 +OP4 E00779 0 +OP4 E0077A 0 +OP4 E0077B 0 +OP4 E0077C 0 +OP4 E0077D 0 +OP4 E0077E 0 +OP4 E0077F 0 +OP4 E00780 0 +OP4 E00781 0 +OP4 E00782 0 +OP4 E00783 0 +OP4 E00784 0 +OP4 E00785 0 +OP4 E00786 0 +OP4 E00787 0 +OP4 E00788 0 +OP4 E00789 0 +OP4 E0078A 0 +OP4 E0078B 0 +OP4 E0078C 0 +OP4 E0078D 0 +OP4 E0078E 0 +OP4 E0078F 0 +OP4 E00790 0 +OP4 E00791 0 +OP4 E00792 0 +OP4 E00793 0 +OP4 E00794 0 +OP4 E00795 0 +OP4 E00796 0 +OP4 E00797 0 +OP4 E00798 0 +OP4 E00799 0 +OP4 E0079A 0 +OP4 E0079B 0 +OP4 E0079C 0 +OP4 E0079D 0 +OP4 E0079E 0 +OP4 E0079F 0 +OP4 E007A0 0 +OP4 E007A1 0 +OP4 E007A2 0 +OP4 E007A3 0 +OP4 E007A4 0 +OP4 E007A5 0 +OP4 E007A6 0 +OP4 E007A7 0 +OP4 E007A8 0 +OP4 E007A9 0 +OP4 E007AA 0 +OP4 E007AB 0 +OP4 E007AC 0 +OP4 E007AD 0 +OP4 E007AE 0 +OP4 E007AF 0 +OP4 E007B0 0 +OP4 E007B1 0 +OP4 E007B2 0 +OP4 E007B3 0 +OP4 E007B4 0 +OP4 E007B5 0 +OP4 E007B6 0 +OP4 E007B7 0 +OP4 E007B8 0 +OP4 E007B9 0 +OP4 E007BA 0 +OP4 E007BB 0 +OP4 E007BC 0 +OP4 E007BD 0 +OP4 E007BE 0 +OP4 E007BF 0 +OP4 E007C0 0 +OP4 E007C1 0 +OP4 E007C2 0 +OP4 E007C3 0 +OP4 E007C4 0 +OP4 E007C5 0 +OP4 E007C6 0 +OP4 E007C7 0 +OP4 E007C8 0 +OP4 E007C9 0 +OP4 E007CA 0 +OP4 E007CB 0 +OP4 E007CC 0 +OP4 E007CD 0 +OP4 E007CE 0 +OP4 E007CF 0 +OP4 E007D0 0 +OP4 E007D1 0 +OP4 E007D2 0 +OP4 E007D3 0 +OP4 E007D4 0 +OP4 E007D5 0 +OP4 E007D6 0 +OP4 E007D7 0 +OP4 E007D8 0 +OP4 E007D9 0 +OP4 E007DA 0 +OP4 E007DB 0 +OP4 E007DC 0 +OP4 E007DD 0 +OP4 E007DE 0 +OP4 E007DF 0 +OP4 E007E0 0 +OP4 E007E1 0 +OP4 E007E2 0 +OP4 E007E3 0 +OP4 E007E4 0 +OP4 E007E5 0 +OP4 E007E6 0 +OP4 E007E7 0 +OP4 E007E8 0 +OP4 E007E9 0 +OP4 E007EA 0 +OP4 E007EB 0 +OP4 E007EC 0 +OP4 E007ED 0 +OP4 E007EE 0 +OP4 E007EF 0 +OP4 E007F0 0 +OP4 E007F1 0 +OP4 E007F2 0 +OP4 E007F3 0 +OP4 E007F4 0 +OP4 E007F5 0 +OP4 E007F6 0 +OP4 E007F7 0 +OP4 E007F8 0 +OP4 E007F9 0 +OP4 E007FA 0 +OP4 E007FB 0 +OP4 E007FC 0 +OP4 E007FD 0 +OP4 E007FE 0 +OP4 E007FF 0 +OP4 E00800 0 +OP4 E00801 0 +OP4 E00802 0 +OP4 E00803 0 +OP4 E00804 0 +OP4 E00805 0 +OP4 E00806 0 +OP4 E00807 0 +OP4 E00808 0 +OP4 E00809 0 +OP4 E0080A 0 +OP4 E0080B 0 +OP4 E0080C 0 +OP4 E0080D 0 +OP4 E0080E 0 +OP4 E0080F 0 +OP4 E00810 0 +OP4 E00811 0 +OP4 E00812 0 +OP4 E00813 0 +OP4 E00814 0 +OP4 E00815 0 +OP4 E00816 0 +OP4 E00817 0 +OP4 E00818 0 +OP4 E00819 0 +OP4 E0081A 0 +OP4 E0081B 0 +OP4 E0081C 0 +OP4 E0081D 0 +OP4 E0081E 0 +OP4 E0081F 0 +OP4 E00820 0 +OP4 E00821 0 +OP4 E00822 0 +OP4 E00823 0 +OP4 E00824 0 +OP4 E00825 0 +OP4 E00826 0 +OP4 E00827 0 +OP4 E00828 0 +OP4 E00829 0 +OP4 E0082A 0 +OP4 E0082B 0 +OP4 E0082C 0 +OP4 E0082D 0 +OP4 E0082E 0 +OP4 E0082F 0 +OP4 E00830 0 +OP4 E00831 0 +OP4 E00832 0 +OP4 E00833 0 +OP4 E00834 0 +OP4 E00835 0 +OP4 E00836 0 +OP4 E00837 0 +OP4 E00838 0 +OP4 E00839 0 +OP4 E0083A 0 +OP4 E0083B 0 +OP4 E0083C 0 +OP4 E0083D 0 +OP4 E0083E 0 +OP4 E0083F 0 +OP4 E00840 0 +OP4 E00841 0 +OP4 E00842 0 +OP4 E00843 0 +OP4 E00844 0 +OP4 E00845 0 +OP4 E00846 0 +OP4 E00847 0 +OP4 E00848 0 +OP4 E00849 0 +OP4 E0084A 0 +OP4 E0084B 0 +OP4 E0084C 0 +OP4 E0084D 0 +OP4 E0084E 0 +OP4 E0084F 0 +OP4 E00850 0 +OP4 E00851 0 +OP4 E00852 0 +OP4 E00853 0 +OP4 E00854 0 +OP4 E00855 0 +OP4 E00856 0 +OP4 E00857 0 +OP4 E00858 0 +OP4 E00859 0 +OP4 E0085A 0 +OP4 E0085B 0 +OP4 E0085C 0 +OP4 E0085D 0 +OP4 E0085E 0 +OP4 E0085F 0 +OP4 E00860 0 +OP4 E00861 0 +OP4 E00862 0 +OP4 E00863 0 +OP4 E00864 0 +OP4 E00865 0 +OP4 E00866 0 +OP4 E00867 0 +OP4 E00868 0 +OP4 E00869 0 +OP4 E0086A 0 +OP4 E0086B 0 +OP4 E0086C 0 +OP4 E0086D 0 +OP4 E0086E 0 +OP4 E0086F 0 +OP4 E00870 0 +OP4 E00871 0 +OP4 E00872 0 +OP4 E00873 0 +OP4 E00874 0 +OP4 E00875 0 +OP4 E00876 0 +OP4 E00877 0 +OP4 E00878 0 +OP4 E00879 0 +OP4 E0087A 0 +OP4 E0087B 0 +OP4 E0087C 0 +OP4 E0087D 0 +OP4 E0087E 0 +OP4 E0087F 0 +OP4 E00880 0 +OP4 E00881 0 +OP4 E00882 0 +OP4 E00883 0 +OP4 E00884 0 +OP4 E00885 0 +OP4 E00886 0 +OP4 E00887 0 +OP4 E00888 0 +OP4 E00889 0 +OP4 E0088A 0 +OP4 E0088B 0 +OP4 E0088C 0 +OP4 E0088D 0 +OP4 E0088E 0 +OP4 E0088F 0 +OP4 E00890 0 +OP4 E00891 0 +OP4 E00892 0 +OP4 E00893 0 +OP4 E00894 0 +OP4 E00895 0 +OP4 E00896 0 +OP4 E00897 0 +OP4 E00898 0 +OP4 E00899 0 +OP4 E0089A 0 +OP4 E0089B 0 +OP4 E0089C 0 +OP4 E0089D 0 +OP4 E0089E 0 +OP4 E0089F 0 +OP4 E008A0 0 +OP4 E008A1 0 +OP4 E008A2 0 +OP4 E008A3 0 +OP4 E008A4 0 +OP4 E008A5 0 +OP4 E008A6 0 +OP4 E008A7 0 +OP4 E008A8 0 +OP4 E008A9 0 +OP4 E008AA 0 +OP4 E008AB 0 +OP4 E008AC 0 +OP4 E008AD 0 +OP4 E008AE 0 +OP4 E008AF 0 +OP4 E008B0 0 +OP4 E008B1 0 +OP4 E008B2 0 +OP4 E008B3 0 +OP4 E008B4 0 +OP4 E008B5 0 +OP4 E008B6 0 +OP4 E008B7 0 +OP4 E008B8 0 +OP4 E008B9 0 +OP4 E008BA 0 +OP4 E008BB 0 +OP4 E008BC 0 +OP4 E008BD 0 +OP4 E008BE 0 +OP4 E008BF 0 +OP4 E008C0 0 +OP4 E008C1 0 +OP4 E008C2 0 +OP4 E008C3 0 +OP4 E008C4 0 +OP4 E008C5 0 +OP4 E008C6 0 +OP4 E008C7 0 +OP4 E008C8 0 +OP4 E008C9 0 +OP4 E008CA 0 +OP4 E008CB 0 +OP4 E008CC 0 +OP4 E008CD 0 +OP4 E008CE 0 +OP4 E008CF 0 +OP4 E008D0 0 +OP4 E008D1 0 +OP4 E008D2 0 +OP4 E008D3 0 +OP4 E008D4 0 +OP4 E008D5 0 +OP4 E008D6 0 +OP4 E008D7 0 +OP4 E008D8 0 +OP4 E008D9 0 +OP4 E008DA 0 +OP4 E008DB 0 +OP4 E008DC 0 +OP4 E008DD 0 +OP4 E008DE 0 +OP4 E008DF 0 +OP4 E008E0 0 +OP4 E008E1 0 +OP4 E008E2 0 +OP4 E008E3 0 +OP4 E008E4 0 +OP4 E008E5 0 +OP4 E008E6 0 +OP4 E008E7 0 +OP4 E008E8 0 +OP4 E008E9 0 +OP4 E008EA 0 +OP4 E008EB 0 +OP4 E008EC 0 +OP4 E008ED 0 +OP4 E008EE 0 +OP4 E008EF 0 +OP4 E008F0 0 +OP4 E008F1 0 +OP4 E008F2 0 +OP4 E008F3 0 +OP4 E008F4 0 +OP4 E008F5 0 +OP4 E008F6 0 +OP4 E008F7 0 +OP4 E008F8 0 +OP4 E008F9 0 +OP4 E008FA 0 +OP4 E008FB 0 +OP4 E008FC 0 +OP4 E008FD 0 +OP4 E008FE 0 +OP4 E008FF 0 +OP4 E00900 0 +OP4 E00901 0 +OP4 E00902 0 +OP4 E00903 0 +OP4 E00904 0 +OP4 E00905 0 +OP4 E00906 0 +OP4 E00907 0 +OP4 E00908 0 +OP4 E00909 0 +OP4 E0090A 0 +OP4 E0090B 0 +OP4 E0090C 0 +OP4 E0090D 0 +OP4 E0090E 0 +OP4 E0090F 0 +OP4 E00910 0 +OP4 E00911 0 +OP4 E00912 0 +OP4 E00913 0 +OP4 E00914 0 +OP4 E00915 0 +OP4 E00916 0 +OP4 E00917 0 +OP4 E00918 0 +OP4 E00919 0 +OP4 E0091A 0 +OP4 E0091B 0 +OP4 E0091C 0 +OP4 E0091D 0 +OP4 E0091E 0 +OP4 E0091F 0 +OP4 E00920 0 +OP4 E00921 0 +OP4 E00922 0 +OP4 E00923 0 +OP4 E00924 0 +OP4 E00925 0 +OP4 E00926 0 +OP4 E00927 0 +OP4 E00928 0 +OP4 E00929 0 +OP4 E0092A 0 +OP4 E0092B 0 +OP4 E0092C 0 +OP4 E0092D 0 +OP4 E0092E 0 +OP4 E0092F 0 +OP4 E00930 0 +OP4 E00931 0 +OP4 E00932 0 +OP4 E00933 0 +OP4 E00934 0 +OP4 E00935 0 +OP4 E00936 0 +OP4 E00937 0 +OP4 E00938 0 +OP4 E00939 0 +OP4 E0093A 0 +OP4 E0093B 0 +OP4 E0093C 0 +OP4 E0093D 0 +OP4 E0093E 0 +OP4 E0093F 0 +OP4 E00940 0 +OP4 E00941 0 +OP4 E00942 0 +OP4 E00943 0 +OP4 E00944 0 +OP4 E00945 0 +OP4 E00946 0 +OP4 E00947 0 +OP4 E00948 0 +OP4 E00949 0 +OP4 E0094A 0 +OP4 E0094B 0 +OP4 E0094C 0 +OP4 E0094D 0 +OP4 E0094E 0 +OP4 E0094F 0 +OP4 E00950 0 +OP4 E00951 0 +OP4 E00952 0 +OP4 E00953 0 +OP4 E00954 0 +OP4 E00955 0 +OP4 E00956 0 +OP4 E00957 0 +OP4 E00958 0 +OP4 E00959 0 +OP4 E0095A 0 +OP4 E0095B 0 +OP4 E0095C 0 +OP4 E0095D 0 +OP4 E0095E 0 +OP4 E0095F 0 +OP4 E00960 0 +OP4 E00961 0 +OP4 E00962 0 +OP4 E00963 0 +OP4 E00964 0 +OP4 E00965 0 +OP4 E00966 0 +OP4 E00967 0 +OP4 E00968 0 +OP4 E00969 0 +OP4 E0096A 0 +OP4 E0096B 0 +OP4 E0096C 0 +OP4 E0096D 0 +OP4 E0096E 0 +OP4 E0096F 0 +OP4 E00970 0 +OP4 E00971 0 +OP4 E00972 0 +OP4 E00973 0 +OP4 E00974 0 +OP4 E00975 0 +OP4 E00976 0 +OP4 E00977 0 +OP4 E00978 0 +OP4 E00979 0 +OP4 E0097A 0 +OP4 E0097B 0 +OP4 E0097C 0 +OP4 E0097D 0 +OP4 E0097E 0 +OP4 E0097F 0 +OP4 E00980 0 +OP4 E00981 0 +OP4 E00982 0 +OP4 E00983 0 +OP4 E00984 0 +OP4 E00985 0 +OP4 E00986 0 +OP4 E00987 0 +OP4 E00988 0 +OP4 E00989 0 +OP4 E0098A 0 +OP4 E0098B 0 +OP4 E0098C 0 +OP4 E0098D 0 +OP4 E0098E 0 +OP4 E0098F 0 +OP4 E00990 0 +OP4 E00991 0 +OP4 E00992 0 +OP4 E00993 0 +OP4 E00994 0 +OP4 E00995 0 +OP4 E00996 0 +OP4 E00997 0 +OP4 E00998 0 +OP4 E00999 0 +OP4 E0099A 0 +OP4 E0099B 0 +OP4 E0099C 0 +OP4 E0099D 0 +OP4 E0099E 0 +OP4 E0099F 0 +OP4 E009A0 0 +OP4 E009A1 0 +OP4 E009A2 0 +OP4 E009A3 0 +OP4 E009A4 0 +OP4 E009A5 0 +OP4 E009A6 0 +OP4 E009A7 0 +OP4 E009A8 0 +OP4 E009A9 0 +OP4 E009AA 0 +OP4 E009AB 0 +OP4 E009AC 0 +OP4 E009AD 0 +OP4 E009AE 0 +OP4 E009AF 0 +OP4 E009B0 0 +OP4 E009B1 0 +OP4 E009B2 0 +OP4 E009B3 0 +OP4 E009B4 0 +OP4 E009B5 0 +OP4 E009B6 0 +OP4 E009B7 0 +OP4 E009B8 0 +OP4 E009B9 0 +OP4 E009BA 0 +OP4 E009BB 0 +OP4 E009BC 0 +OP4 E009BD 0 +OP4 E009BE 0 +OP4 E009BF 0 +OP4 E009C0 0 +OP4 E009C1 0 +OP4 E009C2 0 +OP4 E009C3 0 +OP4 E009C4 0 +OP4 E009C5 0 +OP4 E009C6 0 +OP4 E009C7 0 +OP4 E009C8 0 +OP4 E009C9 0 +OP4 E009CA 0 +OP4 E009CB 0 +OP4 E009CC 0 +OP4 E009CD 0 +OP4 E009CE 0 +OP4 E009CF 0 +OP4 E009D0 0 +OP4 E009D1 0 +OP4 E009D2 0 +OP4 E009D3 0 +OP4 E009D4 0 +OP4 E009D5 0 +OP4 E009D6 0 +OP4 E009D7 0 +OP4 E009D8 0 +OP4 E009D9 0 +OP4 E009DA 0 +OP4 E009DB 0 +OP4 E009DC 0 +OP4 E009DD 0 +OP4 E009DE 0 +OP4 E009DF 0 +OP4 E009E0 0 +OP4 E009E1 0 +OP4 E009E2 0 +OP4 E009E3 0 +OP4 E009E4 0 +OP4 E009E5 0 +OP4 E009E6 0 +OP4 E009E7 0 +OP4 E009E8 0 +OP4 E009E9 0 +OP4 E009EA 0 +OP4 E009EB 0 +OP4 E009EC 0 +OP4 E009ED 0 +OP4 E009EE 0 +OP4 E009EF 0 +OP4 E009F0 0 +OP4 E009F1 0 +OP4 E009F2 0 +OP4 E009F3 0 +OP4 E009F4 0 +OP4 E009F5 0 +OP4 E009F6 0 +OP4 E009F7 0 +OP4 E009F8 0 +OP4 E009F9 0 +OP4 E009FA 0 +OP4 E009FB 0 +OP4 E009FC 0 +OP4 E009FD 0 +OP4 E009FE 0 +OP4 E009FF 0 +OP4 E00A00 0 +OP4 E00A01 0 +OP4 E00A02 0 +OP4 E00A03 0 +OP4 E00A04 0 +OP4 E00A05 0 +OP4 E00A06 0 +OP4 E00A07 0 +OP4 E00A08 0 +OP4 E00A09 0 +OP4 E00A0A 0 +OP4 E00A0B 0 +OP4 E00A0C 0 +OP4 E00A0D 0 +OP4 E00A0E 0 +OP4 E00A0F 0 +OP4 E00A10 0 +OP4 E00A11 0 +OP4 E00A12 0 +OP4 E00A13 0 +OP4 E00A14 0 +OP4 E00A15 0 +OP4 E00A16 0 +OP4 E00A17 0 +OP4 E00A18 0 +OP4 E00A19 0 +OP4 E00A1A 0 +OP4 E00A1B 0 +OP4 E00A1C 0 +OP4 E00A1D 0 +OP4 E00A1E 0 +OP4 E00A1F 0 +OP4 E00A20 0 +OP4 E00A21 0 +OP4 E00A22 0 +OP4 E00A23 0 +OP4 E00A24 0 +OP4 E00A25 0 +OP4 E00A26 0 +OP4 E00A27 0 +OP4 E00A28 0 +OP4 E00A29 0 +OP4 E00A2A 0 +OP4 E00A2B 0 +OP4 E00A2C 0 +OP4 E00A2D 0 +OP4 E00A2E 0 +OP4 E00A2F 0 +OP4 E00A30 0 +OP4 E00A31 0 +OP4 E00A32 0 +OP4 E00A33 0 +OP4 E00A34 0 +OP4 E00A35 0 +OP4 E00A36 0 +OP4 E00A37 0 +OP4 E00A38 0 +OP4 E00A39 0 +OP4 E00A3A 0 +OP4 E00A3B 0 +OP4 E00A3C 0 +OP4 E00A3D 0 +OP4 E00A3E 0 +OP4 E00A3F 0 +OP4 E00A40 0 +OP4 E00A41 0 +OP4 E00A42 0 +OP4 E00A43 0 +OP4 E00A44 0 +OP4 E00A45 0 +OP4 E00A46 0 +OP4 E00A47 0 +OP4 E00A48 0 +OP4 E00A49 0 +OP4 E00A4A 0 +OP4 E00A4B 0 +OP4 E00A4C 0 +OP4 E00A4D 0 +OP4 E00A4E 0 +OP4 E00A4F 0 +OP4 E00A50 0 +OP4 E00A51 0 +OP4 E00A52 0 +OP4 E00A53 0 +OP4 E00A54 0 +OP4 E00A55 0 +OP4 E00A56 0 +OP4 E00A57 0 +OP4 E00A58 0 +OP4 E00A59 0 +OP4 E00A5A 0 +OP4 E00A5B 0 +OP4 E00A5C 0 +OP4 E00A5D 0 +OP4 E00A5E 0 +OP4 E00A5F 0 +OP4 E00A60 0 +OP4 E00A61 0 +OP4 E00A62 0 +OP4 E00A63 0 +OP4 E00A64 0 +OP4 E00A65 0 +OP4 E00A66 0 +OP4 E00A67 0 +OP4 E00A68 0 +OP4 E00A69 0 +OP4 E00A6A 0 +OP4 E00A6B 0 +OP4 E00A6C 0 +OP4 E00A6D 0 +OP4 E00A6E 0 +OP4 E00A6F 0 +OP4 E00A70 0 +OP4 E00A71 0 +OP4 E00A72 0 +OP4 E00A73 0 +OP4 E00A74 0 +OP4 E00A75 0 +OP4 E00A76 0 +OP4 E00A77 0 +OP4 E00A78 0 +OP4 E00A79 0 +OP4 E00A7A 0 +OP4 E00A7B 0 +OP4 E00A7C 0 +OP4 E00A7D 0 +OP4 E00A7E 0 +OP4 E00A7F 0 +OP4 E00A80 0 +OP4 E00A81 0 +OP4 E00A82 0 +OP4 E00A83 0 +OP4 E00A84 0 +OP4 E00A85 0 +OP4 E00A86 0 +OP4 E00A87 0 +OP4 E00A88 0 +OP4 E00A89 0 +OP4 E00A8A 0 +OP4 E00A8B 0 +OP4 E00A8C 0 +OP4 E00A8D 0 +OP4 E00A8E 0 +OP4 E00A8F 0 +OP4 E00A90 0 +OP4 E00A91 0 +OP4 E00A92 0 +OP4 E00A93 0 +OP4 E00A94 0 +OP4 E00A95 0 +OP4 E00A96 0 +OP4 E00A97 0 +OP4 E00A98 0 +OP4 E00A99 0 +OP4 E00A9A 0 +OP4 E00A9B 0 +OP4 E00A9C 0 +OP4 E00A9D 0 +OP4 E00A9E 0 +OP4 E00A9F 0 +OP4 E00AA0 0 +OP4 E00AA1 0 +OP4 E00AA2 0 +OP4 E00AA3 0 +OP4 E00AA4 0 +OP4 E00AA5 0 +OP4 E00AA6 0 +OP4 E00AA7 0 +OP4 E00AA8 0 +OP4 E00AA9 0 +OP4 E00AAA 0 +OP4 E00AAB 0 +OP4 E00AAC 0 +OP4 E00AAD 0 +OP4 E00AAE 0 +OP4 E00AAF 0 +OP4 E00AB0 0 +OP4 E00AB1 0 +OP4 E00AB2 0 +OP4 E00AB3 0 +OP4 E00AB4 0 +OP4 E00AB5 0 +OP4 E00AB6 0 +OP4 E00AB7 0 +OP4 E00AB8 0 +OP4 E00AB9 0 +OP4 E00ABA 0 +OP4 E00ABB 0 +OP4 E00ABC 0 +OP4 E00ABD 0 +OP4 E00ABE 0 +OP4 E00ABF 0 +OP4 E00AC0 0 +OP4 E00AC1 0 +OP4 E00AC2 0 +OP4 E00AC3 0 +OP4 E00AC4 0 +OP4 E00AC5 0 +OP4 E00AC6 0 +OP4 E00AC7 0 +OP4 E00AC8 0 +OP4 E00AC9 0 +OP4 E00ACA 0 +OP4 E00ACB 0 +OP4 E00ACC 0 +OP4 E00ACD 0 +OP4 E00ACE 0 +OP4 E00ACF 0 +OP4 E00AD0 0 +OP4 E00AD1 0 +OP4 E00AD2 0 +OP4 E00AD3 0 +OP4 E00AD4 0 +OP4 E00AD5 0 +OP4 E00AD6 0 +OP4 E00AD7 0 +OP4 E00AD8 0 +OP4 E00AD9 0 +OP4 E00ADA 0 +OP4 E00ADB 0 +OP4 E00ADC 0 +OP4 E00ADD 0 +OP4 E00ADE 0 +OP4 E00ADF 0 +OP4 E00AE0 0 +OP4 E00AE1 0 +OP4 E00AE2 0 +OP4 E00AE3 0 +OP4 E00AE4 0 +OP4 E00AE5 0 +OP4 E00AE6 0 +OP4 E00AE7 0 +OP4 E00AE8 0 +OP4 E00AE9 0 +OP4 E00AEA 0 +OP4 E00AEB 0 +OP4 E00AEC 0 +OP4 E00AED 0 +OP4 E00AEE 0 +OP4 E00AEF 0 +OP4 E00AF0 0 +OP4 E00AF1 0 +OP4 E00AF2 0 +OP4 E00AF3 0 +OP4 E00AF4 0 +OP4 E00AF5 0 +OP4 E00AF6 0 +OP4 E00AF7 0 +OP4 E00AF8 0 +OP4 E00AF9 0 +OP4 E00AFA 0 +OP4 E00AFB 0 +OP4 E00AFC 0 +OP4 E00AFD 0 +OP4 E00AFE 0 +OP4 E00AFF 0 +OP4 E00B00 0 +OP4 E00B01 0 +OP4 E00B02 0 +OP4 E00B03 0 +OP4 E00B04 0 +OP4 E00B05 0 +OP4 E00B06 0 +OP4 E00B07 0 +OP4 E00B08 0 +OP4 E00B09 0 +OP4 E00B0A 0 +OP4 E00B0B 0 +OP4 E00B0C 0 +OP4 E00B0D 0 +OP4 E00B0E 0 +OP4 E00B0F 0 +OP4 E00B10 0 +OP4 E00B11 0 +OP4 E00B12 0 +OP4 E00B13 0 +OP4 E00B14 0 +OP4 E00B15 0 +OP4 E00B16 0 +OP4 E00B17 0 +OP4 E00B18 0 +OP4 E00B19 0 +OP4 E00B1A 0 +OP4 E00B1B 0 +OP4 E00B1C 0 +OP4 E00B1D 0 +OP4 E00B1E 0 +OP4 E00B1F 0 +OP4 E00B20 0 +OP4 E00B21 0 +OP4 E00B22 0 +OP4 E00B23 0 +OP4 E00B24 0 +OP4 E00B25 0 +OP4 E00B26 0 +OP4 E00B27 0 +OP4 E00B28 0 +OP4 E00B29 0 +OP4 E00B2A 0 +OP4 E00B2B 0 +OP4 E00B2C 0 +OP4 E00B2D 0 +OP4 E00B2E 0 +OP4 E00B2F 0 +OP4 E00B30 0 +OP4 E00B31 0 +OP4 E00B32 0 +OP4 E00B33 0 +OP4 E00B34 0 +OP4 E00B35 0 +OP4 E00B36 0 +OP4 E00B37 0 +OP4 E00B38 0 +OP4 E00B39 0 +OP4 E00B3A 0 +OP4 E00B3B 0 +OP4 E00B3C 0 +OP4 E00B3D 0 +OP4 E00B3E 0 +OP4 E00B3F 0 +OP4 E00B40 0 +OP4 E00B41 0 +OP4 E00B42 0 +OP4 E00B43 0 +OP4 E00B44 0 +OP4 E00B45 0 +OP4 E00B46 0 +OP4 E00B47 0 +OP4 E00B48 0 +OP4 E00B49 0 +OP4 E00B4A 0 +OP4 E00B4B 0 +OP4 E00B4C 0 +OP4 E00B4D 0 +OP4 E00B4E 0 +OP4 E00B4F 0 +OP4 E00B50 0 +OP4 E00B51 0 +OP4 E00B52 0 +OP4 E00B53 0 +OP4 E00B54 0 +OP4 E00B55 0 +OP4 E00B56 0 +OP4 E00B57 0 +OP4 E00B58 0 +OP4 E00B59 0 +OP4 E00B5A 0 +OP4 E00B5B 0 +OP4 E00B5C 0 +OP4 E00B5D 0 +OP4 E00B5E 0 +OP4 E00B5F 0 +OP4 E00B60 0 +OP4 E00B61 0 +OP4 E00B62 0 +OP4 E00B63 0 +OP4 E00B64 0 +OP4 E00B65 0 +OP4 E00B66 0 +OP4 E00B67 0 +OP4 E00B68 0 +OP4 E00B69 0 +OP4 E00B6A 0 +OP4 E00B6B 0 +OP4 E00B6C 0 +OP4 E00B6D 0 +OP4 E00B6E 0 +OP4 E00B6F 0 +OP4 E00B70 0 +OP4 E00B71 0 +OP4 E00B72 0 +OP4 E00B73 0 +OP4 E00B74 0 +OP4 E00B75 0 +OP4 E00B76 0 +OP4 E00B77 0 +OP4 E00B78 0 +OP4 E00B79 0 +OP4 E00B7A 0 +OP4 E00B7B 0 +OP4 E00B7C 0 +OP4 E00B7D 0 +OP4 E00B7E 0 +OP4 E00B7F 0 +OP4 E00B80 0 +OP4 E00B81 0 +OP4 E00B82 0 +OP4 E00B83 0 +OP4 E00B84 0 +OP4 E00B85 0 +OP4 E00B86 0 +OP4 E00B87 0 +OP4 E00B88 0 +OP4 E00B89 0 +OP4 E00B8A 0 +OP4 E00B8B 0 +OP4 E00B8C 0 +OP4 E00B8D 0 +OP4 E00B8E 0 +OP4 E00B8F 0 +OP4 E00B90 0 +OP4 E00B91 0 +OP4 E00B92 0 +OP4 E00B93 0 +OP4 E00B94 0 +OP4 E00B95 0 +OP4 E00B96 0 +OP4 E00B97 0 +OP4 E00B98 0 +OP4 E00B99 0 +OP4 E00B9A 0 +OP4 E00B9B 0 +OP4 E00B9C 0 +OP4 E00B9D 0 +OP4 E00B9E 0 +OP4 E00B9F 0 +OP4 E00BA0 0 +OP4 E00BA1 0 +OP4 E00BA2 0 +OP4 E00BA3 0 +OP4 E00BA4 0 +OP4 E00BA5 0 +OP4 E00BA6 0 +OP4 E00BA7 0 +OP4 E00BA8 0 +OP4 E00BA9 0 +OP4 E00BAA 0 +OP4 E00BAB 0 +OP4 E00BAC 0 +OP4 E00BAD 0 +OP4 E00BAE 0 +OP4 E00BAF 0 +OP4 E00BB0 0 +OP4 E00BB1 0 +OP4 E00BB2 0 +OP4 E00BB3 0 +OP4 E00BB4 0 +OP4 E00BB5 0 +OP4 E00BB6 0 +OP4 E00BB7 0 +OP4 E00BB8 0 +OP4 E00BB9 0 +OP4 E00BBA 0 +OP4 E00BBB 0 +OP4 E00BBC 0 +OP4 E00BBD 0 +OP4 E00BBE 0 +OP4 E00BBF 0 +OP4 E00BC0 0 +OP4 E00BC1 0 +OP4 E00BC2 0 +OP4 E00BC3 0 +OP4 E00BC4 0 +OP4 E00BC5 0 +OP4 E00BC6 0 +OP4 E00BC7 0 +OP4 E00BC8 0 +OP4 E00BC9 0 +OP4 E00BCA 0 +OP4 E00BCB 0 +OP4 E00BCC 0 +OP4 E00BCD 0 +OP4 E00BCE 0 +OP4 E00BCF 0 +OP4 E00BD0 0 +OP4 E00BD1 0 +OP4 E00BD2 0 +OP4 E00BD3 0 +OP4 E00BD4 0 +OP4 E00BD5 0 +OP4 E00BD6 0 +OP4 E00BD7 0 +OP4 E00BD8 0 +OP4 E00BD9 0 +OP4 E00BDA 0 +OP4 E00BDB 0 +OP4 E00BDC 0 +OP4 E00BDD 0 +OP4 E00BDE 0 +OP4 E00BDF 0 +OP4 E00BE0 0 +OP4 E00BE1 0 +OP4 E00BE2 0 +OP4 E00BE3 0 +OP4 E00BE4 0 +OP4 E00BE5 0 +OP4 E00BE6 0 +OP4 E00BE7 0 +OP4 E00BE8 0 +OP4 E00BE9 0 +OP4 E00BEA 0 +OP4 E00BEB 0 +OP4 E00BEC 0 +OP4 E00BED 0 +OP4 E00BEE 0 +OP4 E00BEF 0 +OP4 E00BF0 0 +OP4 E00BF1 0 +OP4 E00BF2 0 +OP4 E00BF3 0 +OP4 E00BF4 0 +OP4 E00BF5 0 +OP4 E00BF6 0 +OP4 E00BF7 0 +OP4 E00BF8 0 +OP4 E00BF9 0 +OP4 E00BFA 0 +OP4 E00BFB 0 +OP4 E00BFC 0 +OP4 E00BFD 0 +OP4 E00BFE 0 +OP4 E00BFF 0 +OP4 E00C00 0 +OP4 E00C01 0 +OP4 E00C02 0 +OP4 E00C03 0 +OP4 E00C04 0 +OP4 E00C05 0 +OP4 E00C06 0 +OP4 E00C07 0 +OP4 E00C08 0 +OP4 E00C09 0 +OP4 E00C0A 0 +OP4 E00C0B 0 +OP4 E00C0C 0 +OP4 E00C0D 0 +OP4 E00C0E 0 +OP4 E00C0F 0 +OP4 E00C10 0 +OP4 E00C11 0 +OP4 E00C12 0 +OP4 E00C13 0 +OP4 E00C14 0 +OP4 E00C15 0 +OP4 E00C16 0 +OP4 E00C17 0 +OP4 E00C18 0 +OP4 E00C19 0 +OP4 E00C1A 0 +OP4 E00C1B 0 +OP4 E00C1C 0 +OP4 E00C1D 0 +OP4 E00C1E 0 +OP4 E00C1F 0 +OP4 E00C20 0 +OP4 E00C21 0 +OP4 E00C22 0 +OP4 E00C23 0 +OP4 E00C24 0 +OP4 E00C25 0 +OP4 E00C26 0 +OP4 E00C27 0 +OP4 E00C28 0 +OP4 E00C29 0 +OP4 E00C2A 0 +OP4 E00C2B 0 +OP4 E00C2C 0 +OP4 E00C2D 0 +OP4 E00C2E 0 +OP4 E00C2F 0 +OP4 E00C30 0 +OP4 E00C31 0 +OP4 E00C32 0 +OP4 E00C33 0 +OP4 E00C34 0 +OP4 E00C35 0 +OP4 E00C36 0 +OP4 E00C37 0 +OP4 E00C38 0 +OP4 E00C39 0 +OP4 E00C3A 0 +OP4 E00C3B 0 +OP4 E00C3C 0 +OP4 E00C3D 0 +OP4 E00C3E 0 +OP4 E00C3F 0 +OP4 E00C40 0 +OP4 E00C41 0 +OP4 E00C42 0 +OP4 E00C43 0 +OP4 E00C44 0 +OP4 E00C45 0 +OP4 E00C46 0 +OP4 E00C47 0 +OP4 E00C48 0 +OP4 E00C49 0 +OP4 E00C4A 0 +OP4 E00C4B 0 +OP4 E00C4C 0 +OP4 E00C4D 0 +OP4 E00C4E 0 +OP4 E00C4F 0 +OP4 E00C50 0 +OP4 E00C51 0 +OP4 E00C52 0 +OP4 E00C53 0 +OP4 E00C54 0 +OP4 E00C55 0 +OP4 E00C56 0 +OP4 E00C57 0 +OP4 E00C58 0 +OP4 E00C59 0 +OP4 E00C5A 0 +OP4 E00C5B 0 +OP4 E00C5C 0 +OP4 E00C5D 0 +OP4 E00C5E 0 +OP4 E00C5F 0 +OP4 E00C60 0 +OP4 E00C61 0 +OP4 E00C62 0 +OP4 E00C63 0 +OP4 E00C64 0 +OP4 E00C65 0 +OP4 E00C66 0 +OP4 E00C67 0 +OP4 E00C68 0 +OP4 E00C69 0 +OP4 E00C6A 0 +OP4 E00C6B 0 +OP4 E00C6C 0 +OP4 E00C6D 0 +OP4 E00C6E 0 +OP4 E00C6F 0 +OP4 E00C70 0 +OP4 E00C71 0 +OP4 E00C72 0 +OP4 E00C73 0 +OP4 E00C74 0 +OP4 E00C75 0 +OP4 E00C76 0 +OP4 E00C77 0 +OP4 E00C78 0 +OP4 E00C79 0 +OP4 E00C7A 0 +OP4 E00C7B 0 +OP4 E00C7C 0 +OP4 E00C7D 0 +OP4 E00C7E 0 +OP4 E00C7F 0 +OP4 E00C80 0 +OP4 E00C81 0 +OP4 E00C82 0 +OP4 E00C83 0 +OP4 E00C84 0 +OP4 E00C85 0 +OP4 E00C86 0 +OP4 E00C87 0 +OP4 E00C88 0 +OP4 E00C89 0 +OP4 E00C8A 0 +OP4 E00C8B 0 +OP4 E00C8C 0 +OP4 E00C8D 0 +OP4 E00C8E 0 +OP4 E00C8F 0 +OP4 E00C90 0 +OP4 E00C91 0 +OP4 E00C92 0 +OP4 E00C93 0 +OP4 E00C94 0 +OP4 E00C95 0 +OP4 E00C96 0 +OP4 E00C97 0 +OP4 E00C98 0 +OP4 E00C99 0 +OP4 E00C9A 0 +OP4 E00C9B 0 +OP4 E00C9C 0 +OP4 E00C9D 0 +OP4 E00C9E 0 +OP4 E00C9F 0 +OP4 E00CA0 0 +OP4 E00CA1 0 +OP4 E00CA2 0 +OP4 E00CA3 0 +OP4 E00CA4 0 +OP4 E00CA5 0 +OP4 E00CA6 0 +OP4 E00CA7 0 +OP4 E00CA8 0 +OP4 E00CA9 0 +OP4 E00CAA 0 +OP4 E00CAB 0 +OP4 E00CAC 0 +OP4 E00CAD 0 +OP4 E00CAE 0 +OP4 E00CAF 0 +OP4 E00CB0 0 +OP4 E00CB1 0 +OP4 E00CB2 0 +OP4 E00CB3 0 +OP4 E00CB4 0 +OP4 E00CB5 0 +OP4 E00CB6 0 +OP4 E00CB7 0 +OP4 E00CB8 0 +OP4 E00CB9 0 +OP4 E00CBA 0 +OP4 E00CBB 0 +OP4 E00CBC 0 +OP4 E00CBD 0 +OP4 E00CBE 0 +OP4 E00CBF 0 +OP4 E00CC0 0 +OP4 E00CC1 0 +OP4 E00CC2 0 +OP4 E00CC3 0 +OP4 E00CC4 0 +OP4 E00CC5 0 +OP4 E00CC6 0 +OP4 E00CC7 0 +OP4 E00CC8 0 +OP4 E00CC9 0 +OP4 E00CCA 0 +OP4 E00CCB 0 +OP4 E00CCC 0 +OP4 E00CCD 0 +OP4 E00CCE 0 +OP4 E00CCF 0 +OP4 E00CD0 0 +OP4 E00CD1 0 +OP4 E00CD2 0 +OP4 E00CD3 0 +OP4 E00CD4 0 +OP4 E00CD5 0 +OP4 E00CD6 0 +OP4 E00CD7 0 +OP4 E00CD8 0 +OP4 E00CD9 0 +OP4 E00CDA 0 +OP4 E00CDB 0 +OP4 E00CDC 0 +OP4 E00CDD 0 +OP4 E00CDE 0 +OP4 E00CDF 0 +OP4 E00CE0 0 +OP4 E00CE1 0 +OP4 E00CE2 0 +OP4 E00CE3 0 +OP4 E00CE4 0 +OP4 E00CE5 0 +OP4 E00CE6 0 +OP4 E00CE7 0 +OP4 E00CE8 0 +OP4 E00CE9 0 +OP4 E00CEA 0 +OP4 E00CEB 0 +OP4 E00CEC 0 +OP4 E00CED 0 +OP4 E00CEE 0 +OP4 E00CEF 0 +OP4 E00CF0 0 +OP4 E00CF1 0 +OP4 E00CF2 0 +OP4 E00CF3 0 +OP4 E00CF4 0 +OP4 E00CF5 0 +OP4 E00CF6 0 +OP4 E00CF7 0 +OP4 E00CF8 0 +OP4 E00CF9 0 +OP4 E00CFA 0 +OP4 E00CFB 0 +OP4 E00CFC 0 +OP4 E00CFD 0 +OP4 E00CFE 0 +OP4 E00CFF 0 +OP4 E00D00 0 +OP4 E00D01 0 +OP4 E00D02 0 +OP4 E00D03 0 +OP4 E00D04 0 +OP4 E00D05 0 +OP4 E00D06 0 +OP4 E00D07 0 +OP4 E00D08 0 +OP4 E00D09 0 +OP4 E00D0A 0 +OP4 E00D0B 0 +OP4 E00D0C 0 +OP4 E00D0D 0 +OP4 E00D0E 0 +OP4 E00D0F 0 +OP4 E00D10 0 +OP4 E00D11 0 +OP4 E00D12 0 +OP4 E00D13 0 +OP4 E00D14 0 +OP4 E00D15 0 +OP4 E00D16 0 +OP4 E00D17 0 +OP4 E00D18 0 +OP4 E00D19 0 +OP4 E00D1A 0 +OP4 E00D1B 0 +OP4 E00D1C 0 +OP4 E00D1D 0 +OP4 E00D1E 0 +OP4 E00D1F 0 +OP4 E00D20 0 +OP4 E00D21 0 +OP4 E00D22 0 +OP4 E00D23 0 +OP4 E00D24 0 +OP4 E00D25 0 +OP4 E00D26 0 +OP4 E00D27 0 +OP4 E00D28 0 +OP4 E00D29 0 +OP4 E00D2A 0 +OP4 E00D2B 0 +OP4 E00D2C 0 +OP4 E00D2D 0 +OP4 E00D2E 0 +OP4 E00D2F 0 +OP4 E00D30 0 +OP4 E00D31 0 +OP4 E00D32 0 +OP4 E00D33 0 +OP4 E00D34 0 +OP4 E00D35 0 +OP4 E00D36 0 +OP4 E00D37 0 +OP4 E00D38 0 +OP4 E00D39 0 +OP4 E00D3A 0 +OP4 E00D3B 0 +OP4 E00D3C 0 +OP4 E00D3D 0 +OP4 E00D3E 0 +OP4 E00D3F 0 +OP4 E00D40 0 +OP4 E00D41 0 +OP4 E00D42 0 +OP4 E00D43 0 +OP4 E00D44 0 +OP4 E00D45 0 +OP4 E00D46 0 +OP4 E00D47 0 +OP4 E00D48 0 +OP4 E00D49 0 +OP4 E00D4A 0 +OP4 E00D4B 0 +OP4 E00D4C 0 +OP4 E00D4D 0 +OP4 E00D4E 0 +OP4 E00D4F 0 +OP4 E00D50 0 +OP4 E00D51 0 +OP4 E00D52 0 +OP4 E00D53 0 +OP4 E00D54 0 +OP4 E00D55 0 +OP4 E00D56 0 +OP4 E00D57 0 +OP4 E00D58 0 +OP4 E00D59 0 +OP4 E00D5A 0 +OP4 E00D5B 0 +OP4 E00D5C 0 +OP4 E00D5D 0 +OP4 E00D5E 0 +OP4 E00D5F 0 +OP4 E00D60 0 +OP4 E00D61 0 +OP4 E00D62 0 +OP4 E00D63 0 +OP4 E00D64 0 +OP4 E00D65 0 +OP4 E00D66 0 +OP4 E00D67 0 +OP4 E00D68 0 +OP4 E00D69 0 +OP4 E00D6A 0 +OP4 E00D6B 0 +OP4 E00D6C 0 +OP4 E00D6D 0 +OP4 E00D6E 0 +OP4 E00D6F 0 +OP4 E00D70 0 +OP4 E00D71 0 +OP4 E00D72 0 +OP4 E00D73 0 +OP4 E00D74 0 +OP4 E00D75 0 +OP4 E00D76 0 +OP4 E00D77 0 +OP4 E00D78 0 +OP4 E00D79 0 +OP4 E00D7A 0 +OP4 E00D7B 0 +OP4 E00D7C 0 +OP4 E00D7D 0 +OP4 E00D7E 0 +OP4 E00D7F 0 +OP4 E00D80 0 +OP4 E00D81 0 +OP4 E00D82 0 +OP4 E00D83 0 +OP4 E00D84 0 +OP4 E00D85 0 +OP4 E00D86 0 +OP4 E00D87 0 +OP4 E00D88 0 +OP4 E00D89 0 +OP4 E00D8A 0 +OP4 E00D8B 0 +OP4 E00D8C 0 +OP4 E00D8D 0 +OP4 E00D8E 0 +OP4 E00D8F 0 +OP4 E00D90 0 +OP4 E00D91 0 +OP4 E00D92 0 +OP4 E00D93 0 +OP4 E00D94 0 +OP4 E00D95 0 +OP4 E00D96 0 +OP4 E00D97 0 +OP4 E00D98 0 +OP4 E00D99 0 +OP4 E00D9A 0 +OP4 E00D9B 0 +OP4 E00D9C 0 +OP4 E00D9D 0 +OP4 E00D9E 0 +OP4 E00D9F 0 +OP4 E00DA0 0 +OP4 E00DA1 0 +OP4 E00DA2 0 +OP4 E00DA3 0 +OP4 E00DA4 0 +OP4 E00DA5 0 +OP4 E00DA6 0 +OP4 E00DA7 0 +OP4 E00DA8 0 +OP4 E00DA9 0 +OP4 E00DAA 0 +OP4 E00DAB 0 +OP4 E00DAC 0 +OP4 E00DAD 0 +OP4 E00DAE 0 +OP4 E00DAF 0 +OP4 E00DB0 0 +OP4 E00DB1 0 +OP4 E00DB2 0 +OP4 E00DB3 0 +OP4 E00DB4 0 +OP4 E00DB5 0 +OP4 E00DB6 0 +OP4 E00DB7 0 +OP4 E00DB8 0 +OP4 E00DB9 0 +OP4 E00DBA 0 +OP4 E00DBB 0 +OP4 E00DBC 0 +OP4 E00DBD 0 +OP4 E00DBE 0 +OP4 E00DBF 0 +OP4 E00DC0 0 +OP4 E00DC1 0 +OP4 E00DC2 0 +OP4 E00DC3 0 +OP4 E00DC4 0 +OP4 E00DC5 0 +OP4 E00DC6 0 +OP4 E00DC7 0 +OP4 E00DC8 0 +OP4 E00DC9 0 +OP4 E00DCA 0 +OP4 E00DCB 0 +OP4 E00DCC 0 +OP4 E00DCD 0 +OP4 E00DCE 0 +OP4 E00DCF 0 +OP4 E00DD0 0 +OP4 E00DD1 0 +OP4 E00DD2 0 +OP4 E00DD3 0 +OP4 E00DD4 0 +OP4 E00DD5 0 +OP4 E00DD6 0 +OP4 E00DD7 0 +OP4 E00DD8 0 +OP4 E00DD9 0 +OP4 E00DDA 0 +OP4 E00DDB 0 +OP4 E00DDC 0 +OP4 E00DDD 0 +OP4 E00DDE 0 +OP4 E00DDF 0 +OP4 E00DE0 0 +OP4 E00DE1 0 +OP4 E00DE2 0 +OP4 E00DE3 0 +OP4 E00DE4 0 +OP4 E00DE5 0 +OP4 E00DE6 0 +OP4 E00DE7 0 +OP4 E00DE8 0 +OP4 E00DE9 0 +OP4 E00DEA 0 +OP4 E00DEB 0 +OP4 E00DEC 0 +OP4 E00DED 0 +OP4 E00DEE 0 +OP4 E00DEF 0 +OP4 E00DF0 0 +OP4 E00DF1 0 +OP4 E00DF2 0 +OP4 E00DF3 0 +OP4 E00DF4 0 +OP4 E00DF5 0 +OP4 E00DF6 0 +OP4 E00DF7 0 +OP4 E00DF8 0 +OP4 E00DF9 0 +OP4 E00DFA 0 +OP4 E00DFB 0 +OP4 E00DFC 0 +OP4 E00DFD 0 +OP4 E00DFE 0 +OP4 E00DFF 0 +OP4 E00E00 0 +OP4 E00E01 0 +OP4 E00E02 0 +OP4 E00E03 0 +OP4 E00E04 0 +OP4 E00E05 0 +OP4 E00E06 0 +OP4 E00E07 0 +OP4 E00E08 0 +OP4 E00E09 0 +OP4 E00E0A 0 +OP4 E00E0B 0 +OP4 E00E0C 0 +OP4 E00E0D 0 +OP4 E00E0E 0 +OP4 E00E0F 0 +OP4 E00E10 0 +OP4 E00E11 0 +OP4 E00E12 0 +OP4 E00E13 0 +OP4 E00E14 0 +OP4 E00E15 0 +OP4 E00E16 0 +OP4 E00E17 0 +OP4 E00E18 0 +OP4 E00E19 0 +OP4 E00E1A 0 +OP4 E00E1B 0 +OP4 E00E1C 0 +OP4 E00E1D 0 +OP4 E00E1E 0 +OP4 E00E1F 0 +OP4 E00E20 0 +OP4 E00E21 0 +OP4 E00E22 0 +OP4 E00E23 0 +OP4 E00E24 0 +OP4 E00E25 0 +OP4 E00E26 0 +OP4 E00E27 0 +OP4 E00E28 0 +OP4 E00E29 0 +OP4 E00E2A 0 +OP4 E00E2B 0 +OP4 E00E2C 0 +OP4 E00E2D 0 +OP4 E00E2E 0 +OP4 E00E2F 0 +OP4 E00E30 0 +OP4 E00E31 0 +OP4 E00E32 0 +OP4 E00E33 0 +OP4 E00E34 0 +OP4 E00E35 0 +OP4 E00E36 0 +OP4 E00E37 0 +OP4 E00E38 0 +OP4 E00E39 0 +OP4 E00E3A 0 +OP4 E00E3B 0 +OP4 E00E3C 0 +OP4 E00E3D 0 +OP4 E00E3E 0 +OP4 E00E3F 0 +OP4 E00E40 0 +OP4 E00E41 0 +OP4 E00E42 0 +OP4 E00E43 0 +OP4 E00E44 0 +OP4 E00E45 0 +OP4 E00E46 0 +OP4 E00E47 0 +OP4 E00E48 0 +OP4 E00E49 0 +OP4 E00E4A 0 +OP4 E00E4B 0 +OP4 E00E4C 0 +OP4 E00E4D 0 +OP4 E00E4E 0 +OP4 E00E4F 0 +OP4 E00E50 0 +OP4 E00E51 0 +OP4 E00E52 0 +OP4 E00E53 0 +OP4 E00E54 0 +OP4 E00E55 0 +OP4 E00E56 0 +OP4 E00E57 0 +OP4 E00E58 0 +OP4 E00E59 0 +OP4 E00E5A 0 +OP4 E00E5B 0 +OP4 E00E5C 0 +OP4 E00E5D 0 +OP4 E00E5E 0 +OP4 E00E5F 0 +OP4 E00E60 0 +OP4 E00E61 0 +OP4 E00E62 0 +OP4 E00E63 0 +OP4 E00E64 0 +OP4 E00E65 0 +OP4 E00E66 0 +OP4 E00E67 0 +OP4 E00E68 0 +OP4 E00E69 0 +OP4 E00E6A 0 +OP4 E00E6B 0 +OP4 E00E6C 0 +OP4 E00E6D 0 +OP4 E00E6E 0 +OP4 E00E6F 0 +OP4 E00E70 0 +OP4 E00E71 0 +OP4 E00E72 0 +OP4 E00E73 0 +OP4 E00E74 0 +OP4 E00E75 0 +OP4 E00E76 0 +OP4 E00E77 0 +OP4 E00E78 0 +OP4 E00E79 0 +OP4 E00E7A 0 +OP4 E00E7B 0 +OP4 E00E7C 0 +OP4 E00E7D 0 +OP4 E00E7E 0 +OP4 E00E7F 0 +OP4 E00E80 0 +OP4 E00E81 0 +OP4 E00E82 0 +OP4 E00E83 0 +OP4 E00E84 0 +OP4 E00E85 0 +OP4 E00E86 0 +OP4 E00E87 0 +OP4 E00E88 0 +OP4 E00E89 0 +OP4 E00E8A 0 +OP4 E00E8B 0 +OP4 E00E8C 0 +OP4 E00E8D 0 +OP4 E00E8E 0 +OP4 E00E8F 0 +OP4 E00E90 0 +OP4 E00E91 0 +OP4 E00E92 0 +OP4 E00E93 0 +OP4 E00E94 0 +OP4 E00E95 0 +OP4 E00E96 0 +OP4 E00E97 0 +OP4 E00E98 0 +OP4 E00E99 0 +OP4 E00E9A 0 +OP4 E00E9B 0 +OP4 E00E9C 0 +OP4 E00E9D 0 +OP4 E00E9E 0 +OP4 E00E9F 0 +OP4 E00EA0 0 +OP4 E00EA1 0 +OP4 E00EA2 0 +OP4 E00EA3 0 +OP4 E00EA4 0 +OP4 E00EA5 0 +OP4 E00EA6 0 +OP4 E00EA7 0 +OP4 E00EA8 0 +OP4 E00EA9 0 +OP4 E00EAA 0 +OP4 E00EAB 0 +OP4 E00EAC 0 +OP4 E00EAD 0 +OP4 E00EAE 0 +OP4 E00EAF 0 +OP4 E00EB0 0 +OP4 E00EB1 0 +OP4 E00EB2 0 +OP4 E00EB3 0 +OP4 E00EB4 0 +OP4 E00EB5 0 +OP4 E00EB6 0 +OP4 E00EB7 0 +OP4 E00EB8 0 +OP4 E00EB9 0 +OP4 E00EBA 0 +OP4 E00EBB 0 +OP4 E00EBC 0 +OP4 E00EBD 0 +OP4 E00EBE 0 +OP4 E00EBF 0 +OP4 E00EC0 0 +OP4 E00EC1 0 +OP4 E00EC2 0 +OP4 E00EC3 0 +OP4 E00EC4 0 +OP4 E00EC5 0 +OP4 E00EC6 0 +OP4 E00EC7 0 +OP4 E00EC8 0 +OP4 E00EC9 0 +OP4 E00ECA 0 +OP4 E00ECB 0 +OP4 E00ECC 0 +OP4 E00ECD 0 +OP4 E00ECE 0 +OP4 E00ECF 0 +OP4 E00ED0 0 +OP4 E00ED1 0 +OP4 E00ED2 0 +OP4 E00ED3 0 +OP4 E00ED4 0 +OP4 E00ED5 0 +OP4 E00ED6 0 +OP4 E00ED7 0 +OP4 E00ED8 0 +OP4 E00ED9 0 +OP4 E00EDA 0 +OP4 E00EDB 0 +OP4 E00EDC 0 +OP4 E00EDD 0 +OP4 E00EDE 0 +OP4 E00EDF 0 +OP4 E00EE0 0 +OP4 E00EE1 0 +OP4 E00EE2 0 +OP4 E00EE3 0 +OP4 E00EE4 0 +OP4 E00EE5 0 +OP4 E00EE6 0 +OP4 E00EE7 0 +OP4 E00EE8 0 +OP4 E00EE9 0 +OP4 E00EEA 0 +OP4 E00EEB 0 +OP4 E00EEC 0 +OP4 E00EED 0 +OP4 E00EEE 0 +OP4 E00EEF 0 +OP4 E00EF0 0 +OP4 E00EF1 0 +OP4 E00EF2 0 +OP4 E00EF3 0 +OP4 E00EF4 0 +OP4 E00EF5 0 +OP4 E00EF6 0 +OP4 E00EF7 0 +OP4 E00EF8 0 +OP4 E00EF9 0 +OP4 E00EFA 0 +OP4 E00EFB 0 +OP4 E00EFC 0 +OP4 E00EFD 0 +OP4 E00EFE 0 +OP4 E00EFF 0 +OP4 E00F00 0 +OP4 E00F01 0 +OP4 E00F02 0 +OP4 E00F03 0 +OP4 E00F04 0 +OP4 E00F05 0 +OP4 E00F06 0 +OP4 E00F07 0 +OP4 E00F08 0 +OP4 E00F09 0 +OP4 E00F0A 0 +OP4 E00F0B 0 +OP4 E00F0C 0 +OP4 E00F0D 0 +OP4 E00F0E 0 +OP4 E00F0F 0 +OP4 E00F10 0 +OP4 E00F11 0 +OP4 E00F12 0 +OP4 E00F13 0 +OP4 E00F14 0 +OP4 E00F15 0 +OP4 E00F16 0 +OP4 E00F17 0 +OP4 E00F18 0 +OP4 E00F19 0 +OP4 E00F1A 0 +OP4 E00F1B 0 +OP4 E00F1C 0 +OP4 E00F1D 0 +OP4 E00F1E 0 +OP4 E00F1F 0 +OP4 E00F20 0 +OP4 E00F21 0 +OP4 E00F22 0 +OP4 E00F23 0 +OP4 E00F24 0 +OP4 E00F25 0 +OP4 E00F26 0 +OP4 E00F27 0 +OP4 E00F28 0 +OP4 E00F29 0 +OP4 E00F2A 0 +OP4 E00F2B 0 +OP4 E00F2C 0 +OP4 E00F2D 0 +OP4 E00F2E 0 +OP4 E00F2F 0 +OP4 E00F30 0 +OP4 E00F31 0 +OP4 E00F32 0 +OP4 E00F33 0 +OP4 E00F34 0 +OP4 E00F35 0 +OP4 E00F36 0 +OP4 E00F37 0 +OP4 E00F38 0 +OP4 E00F39 0 +OP4 E00F3A 0 +OP4 E00F3B 0 +OP4 E00F3C 0 +OP4 E00F3D 0 +OP4 E00F3E 0 +OP4 E00F3F 0 +OP4 E00F40 0 +OP4 E00F41 0 +OP4 E00F42 0 +OP4 E00F43 0 +OP4 E00F44 0 +OP4 E00F45 0 +OP4 E00F46 0 +OP4 E00F47 0 +OP4 E00F48 0 +OP4 E00F49 0 +OP4 E00F4A 0 +OP4 E00F4B 0 +OP4 E00F4C 0 +OP4 E00F4D 0 +OP4 E00F4E 0 +OP4 E00F4F 0 +OP4 E00F50 0 +OP4 E00F51 0 +OP4 E00F52 0 +OP4 E00F53 0 +OP4 E00F54 0 +OP4 E00F55 0 +OP4 E00F56 0 +OP4 E00F57 0 +OP4 E00F58 0 +OP4 E00F59 0 +OP4 E00F5A 0 +OP4 E00F5B 0 +OP4 E00F5C 0 +OP4 E00F5D 0 +OP4 E00F5E 0 +OP4 E00F5F 0 +OP4 E00F60 0 +OP4 E00F61 0 +OP4 E00F62 0 +OP4 E00F63 0 +OP4 E00F64 0 +OP4 E00F65 0 +OP4 E00F66 0 +OP4 E00F67 0 +OP4 E00F68 0 +OP4 E00F69 0 +OP4 E00F6A 0 +OP4 E00F6B 0 +OP4 E00F6C 0 +OP4 E00F6D 0 +OP4 E00F6E 0 +OP4 E00F6F 0 +OP4 E00F70 0 +OP4 E00F71 0 +OP4 E00F72 0 +OP4 E00F73 0 +OP4 E00F74 0 +OP4 E00F75 0 +OP4 E00F76 0 +OP4 E00F77 0 +OP4 E00F78 0 +OP4 E00F79 0 +OP4 E00F7A 0 +OP4 E00F7B 0 +OP4 E00F7C 0 +OP4 E00F7D 0 +OP4 E00F7E 0 +OP4 E00F7F 0 +OP4 E00F80 0 +OP4 E00F81 0 +OP4 E00F82 0 +OP4 E00F83 0 +OP4 E00F84 0 +OP4 E00F85 0 +OP4 E00F86 0 +OP4 E00F87 0 +OP4 E00F88 0 +OP4 E00F89 0 +OP4 E00F8A 0 +OP4 E00F8B 0 +OP4 E00F8C 0 +OP4 E00F8D 0 +OP4 E00F8E 0 +OP4 E00F8F 0 +OP4 E00F90 0 +OP4 E00F91 0 +OP4 E00F92 0 +OP4 E00F93 0 +OP4 E00F94 0 +OP4 E00F95 0 +OP4 E00F96 0 +OP4 E00F97 0 +OP4 E00F98 0 +OP4 E00F99 0 +OP4 E00F9A 0 +OP4 E00F9B 0 +OP4 E00F9C 0 +OP4 E00F9D 0 +OP4 E00F9E 0 +OP4 E00F9F 0 +OP4 E00FA0 0 +OP4 E00FA1 0 +OP4 E00FA2 0 +OP4 E00FA3 0 +OP4 E00FA4 0 +OP4 E00FA5 0 +OP4 E00FA6 0 +OP4 E00FA7 0 +OP4 E00FA8 0 +OP4 E00FA9 0 +OP4 E00FAA 0 +OP4 E00FAB 0 +OP4 E00FAC 0 +OP4 E00FAD 0 +OP4 E00FAE 0 +OP4 E00FAF 0 +OP4 E00FB0 0 +OP4 E00FB1 0 +OP4 E00FB2 0 +OP4 E00FB3 0 +OP4 E00FB4 0 +OP4 E00FB5 0 +OP4 E00FB6 0 +OP4 E00FB7 0 +OP4 E00FB8 0 +OP4 E00FB9 0 +OP4 E00FBA 0 +OP4 E00FBB 0 +OP4 E00FBC 0 +OP4 E00FBD 0 +OP4 E00FBE 0 +OP4 E00FBF 0 +OP4 E00FC0 0 +OP4 E00FC1 0 +OP4 E00FC2 0 +OP4 E00FC3 0 +OP4 E00FC4 0 +OP4 E00FC5 0 +OP4 E00FC6 0 +OP4 E00FC7 0 +OP4 E00FC8 0 +OP4 E00FC9 0 +OP4 E00FCA 0 +OP4 E00FCB 0 +OP4 E00FCC 0 +OP4 E00FCD 0 +OP4 E00FCE 0 +OP4 E00FCF 0 +OP4 E00FD0 0 +OP4 E00FD1 0 +OP4 E00FD2 0 +OP4 E00FD3 0 +OP4 E00FD4 0 +OP4 E00FD5 0 +OP4 E00FD6 0 +OP4 E00FD7 0 +OP4 E00FD8 0 +OP4 E00FD9 0 +OP4 E00FDA 0 +OP4 E00FDB 0 +OP4 E00FDC 0 +OP4 E00FDD 0 +OP4 E00FDE 0 +OP4 E00FDF 0 +OP4 E00FE0 0 +OP4 E00FE1 0 +OP4 E00FE2 0 +OP4 E00FE3 0 +OP4 E00FE4 0 +OP4 E00FE5 0 +OP4 E00FE6 0 +OP4 E00FE7 0 +OP4 E00FE8 0 +OP4 E00FE9 0 +OP4 E00FEA 0 +OP4 E00FEB 0 +OP4 E00FEC 0 +OP4 E00FED 0 +OP4 E00FEE 0 +OP4 E00FEF 0 +OP4 E00FF0 0 +OP4 E00FF1 0 +OP4 E00FF2 0 +OP4 E00FF3 0 +OP4 E00FF4 0 +OP4 E00FF5 0 +OP4 E00FF6 0 +OP4 E00FF7 0 +OP4 E00FF8 0 +OP4 E00FF9 0 +OP4 E00FFA 0 +OP4 E00FFB 0 +OP4 E00FFC 0 +OP4 E00FFD 0 +OP4 E00FFE 0 +OP4 E00FFF 0 +OP4 E01000 0 +OP4 E01001 0 +OP4 E01002 0 +OP4 E01003 0 +OP4 E01004 0 +OP4 E01005 0 +OP4 E01006 0 +OP4 E01007 0 +OP4 E01008 0 +OP4 E01009 0 +OP4 E0100A 0 +OP4 E0100B 0 +OP4 E0100C 0 +OP4 E0100D 0 +OP4 E0100E 0 +OP4 E0100F 0 +OP4 E01010 0 +OP4 E01011 0 +OP4 E01012 0 +OP4 E01013 0 +OP4 E01014 0 +OP4 E01015 0 +OP4 E01016 0 +OP4 E01017 0 +OP4 E01018 0 +OP4 E01019 0 +OP4 E0101A 0 +OP4 E0101B 0 +OP4 E0101C 0 +OP4 E0101D 0 +OP4 E0101E 0 +OP4 E0101F 0 +OP4 E01020 0 +OP4 E01021 0 +OP4 E01022 0 +OP4 E01023 0 +OP4 E01024 0 +OP4 E01025 0 +OP4 E01026 0 +OP4 E01027 0 +OP4 E01028 0 +OP4 E01029 0 +OP4 E0102A 0 +OP4 E0102B 0 +OP4 E0102C 0 +OP4 E0102D 0 +OP4 E0102E 0 +OP4 E0102F 0 +OP4 E01030 0 +OP4 E01031 0 +OP4 E01032 0 +OP4 E01033 0 +OP4 E01034 0 +OP4 E01035 0 +OP4 E01036 0 +OP4 E01037 0 +OP4 E01038 0 +OP4 E01039 0 +OP4 E0103A 0 +OP4 E0103B 0 +OP4 E0103C 0 +OP4 E0103D 0 +OP4 E0103E 0 +OP4 E0103F 0 +OP4 E01040 0 +OP4 E01041 0 +OP4 E01042 0 +OP4 E01043 0 +OP4 E01044 0 +OP4 E01045 0 +OP4 E01046 0 +OP4 E01047 0 +OP4 E01048 0 +OP4 E01049 0 +OP4 E0104A 0 +OP4 E0104B 0 +OP4 E0104C 0 +OP4 E0104D 0 +OP4 E0104E 0 +OP4 E0104F 0 +OP4 E01050 0 +OP4 E01051 0 +OP4 E01052 0 +OP4 E01053 0 +OP4 E01054 0 +OP4 E01055 0 +OP4 E01056 0 +OP4 E01057 0 +OP4 E01058 0 +OP4 E01059 0 +OP4 E0105A 0 +OP4 E0105B 0 +OP4 E0105C 0 +OP4 E0105D 0 +OP4 E0105E 0 +OP4 E0105F 0 +OP4 E01060 0 +OP4 E01061 0 +OP4 E01062 0 +OP4 E01063 0 +OP4 E01064 0 +OP4 E01065 0 +OP4 E01066 0 +OP4 E01067 0 +OP4 E01068 0 +OP4 E01069 0 +OP4 E0106A 0 +OP4 E0106B 0 +OP4 E0106C 0 +OP4 E0106D 0 +OP4 E0106E 0 +OP4 E0106F 0 +OP4 E01070 0 +OP4 E01071 0 +OP4 E01072 0 +OP4 E01073 0 +OP4 E01074 0 +OP4 E01075 0 +OP4 E01076 0 +OP4 E01077 0 +OP4 E01078 0 +OP4 E01079 0 +OP4 E0107A 0 +OP4 E0107B 0 +OP4 E0107C 0 +OP4 E0107D 0 +OP4 E0107E 0 +OP4 E0107F 0 +OP4 E01080 0 +OP4 E01081 0 +OP4 E01082 0 +OP4 E01083 0 +OP4 E01084 0 +OP4 E01085 0 +OP4 E01086 0 +OP4 E01087 0 +OP4 E01088 0 +OP4 E01089 0 +OP4 E0108A 0 +OP4 E0108B 0 +OP4 E0108C 0 +OP4 E0108D 0 +OP4 E0108E 0 +OP4 E0108F 0 +OP4 E01090 0 +OP4 E01091 0 +OP4 E01092 0 +OP4 E01093 0 +OP4 E01094 0 +OP4 E01095 0 +OP4 E01096 0 +OP4 E01097 0 +OP4 E01098 0 +OP4 E01099 0 +OP4 E0109A 0 +OP4 E0109B 0 +OP4 E0109C 0 +OP4 E0109D 0 +OP4 E0109E 0 +OP4 E0109F 0 +OP4 E010A0 0 +OP4 E010A1 0 +OP4 E010A2 0 +OP4 E010A3 0 +OP4 E010A4 0 +OP4 E010A5 0 +OP4 E010A6 0 +OP4 E010A7 0 +OP4 E010A8 0 +OP4 E010A9 0 +OP4 E010AA 0 +OP4 E010AB 0 +OP4 E010AC 0 +OP4 E010AD 0 +OP4 E010AE 0 +OP4 E010AF 0 +OP4 E010B0 0 +OP4 E010B1 0 +OP4 E010B2 0 +OP4 E010B3 0 +OP4 E010B4 0 +OP4 E010B5 0 +OP4 E010B6 0 +OP4 E010B7 0 +OP4 E010B8 0 +OP4 E010B9 0 +OP4 E010BA 0 +OP4 E010BB 0 +OP4 E010BC 0 +OP4 E010BD 0 +OP4 E010BE 0 +OP4 E010BF 0 +OP4 E010C0 0 +OP4 E010C1 0 +OP4 E010C2 0 +OP4 E010C3 0 +OP4 E010C4 0 +OP4 E010C5 0 +OP4 E010C6 0 +OP4 E010C7 0 +OP4 E010C8 0 +OP4 E010C9 0 +OP4 E010CA 0 +OP4 E010CB 0 +OP4 E010CC 0 +OP4 E010CD 0 +OP4 E010CE 0 +OP4 E010CF 0 +OP4 E010D0 0 +OP4 E010D1 0 +OP4 E010D2 0 +OP4 E010D3 0 +OP4 E010D4 0 +OP4 E010D5 0 +OP4 E010D6 0 +OP4 E010D7 0 +OP4 E010D8 0 +OP4 E010D9 0 +OP4 E010DA 0 +OP4 E010DB 0 +OP4 E010DC 0 +OP4 E010DD 0 +OP4 E010DE 0 +OP4 E010DF 0 +OP4 E010E0 0 +OP4 E010E1 0 +OP4 E010E2 0 +OP4 E010E3 0 +OP4 E010E4 0 +OP4 E010E5 0 +OP4 E010E6 0 +OP4 E010E7 0 +OP4 E010E8 0 +OP4 E010E9 0 +OP4 E010EA 0 +OP4 E010EB 0 +OP4 E010EC 0 +OP4 E010ED 0 +OP4 E010EE 0 +OP4 E010EF 0 +OP4 E010F0 0 +OP4 E010F1 0 +OP4 E010F2 0 +OP4 E010F3 0 +OP4 E010F4 0 +OP4 E010F5 0 +OP4 E010F6 0 +OP4 E010F7 0 +OP4 E010F8 0 +OP4 E010F9 0 +OP4 E010FA 0 +OP4 E010FB 0 +OP4 E010FC 0 +OP4 E010FD 0 +OP4 E010FE 0 +OP4 E010FF 0 +OP4 E01100 0 +OP4 E01101 0 +OP4 E01102 0 +OP4 E01103 0 +OP4 E01104 0 +OP4 E01105 0 +OP4 E01106 0 +OP4 E01107 0 +OP4 E01108 0 +OP4 E01109 0 +OP4 E0110A 0 +OP4 E0110B 0 +OP4 E0110C 0 +OP4 E0110D 0 +OP4 E0110E 0 +OP4 E0110F 0 +OP4 E01110 0 +OP4 E01111 0 +OP4 E01112 0 +OP4 E01113 0 +OP4 E01114 0 +OP4 E01115 0 +OP4 E01116 0 +OP4 E01117 0 +OP4 E01118 0 +OP4 E01119 0 +OP4 E0111A 0 +OP4 E0111B 0 +OP4 E0111C 0 +OP4 E0111D 0 +OP4 E0111E 0 +OP4 E0111F 0 +OP4 E01120 0 +OP4 E01121 0 +OP4 E01122 0 +OP4 E01123 0 +OP4 E01124 0 +OP4 E01125 0 +OP4 E01126 0 +OP4 E01127 0 +OP4 E01128 0 +OP4 E01129 0 +OP4 E0112A 0 +OP4 E0112B 0 +OP4 E0112C 0 +OP4 E0112D 0 +OP4 E0112E 0 +OP4 E0112F 0 +OP4 E01130 0 +OP4 E01131 0 +OP4 E01132 0 +OP4 E01133 0 +OP4 E01134 0 +OP4 E01135 0 +OP4 E01136 0 +OP4 E01137 0 +OP4 E01138 0 +OP4 E01139 0 +OP4 E0113A 0 +OP4 E0113B 0 +OP4 E0113C 0 +OP4 E0113D 0 +OP4 E0113E 0 +OP4 E0113F 0 +OP4 E01140 0 +OP4 E01141 0 +OP4 E01142 0 +OP4 E01143 0 +OP4 E01144 0 +OP4 E01145 0 +OP4 E01146 0 +OP4 E01147 0 +OP4 E01148 0 +OP4 E01149 0 +OP4 E0114A 0 +OP4 E0114B 0 +OP4 E0114C 0 +OP4 E0114D 0 +OP4 E0114E 0 +OP4 E0114F 0 +OP4 E01150 0 +OP4 E01151 0 +OP4 E01152 0 +OP4 E01153 0 +OP4 E01154 0 +OP4 E01155 0 +OP4 E01156 0 +OP4 E01157 0 +OP4 E01158 0 +OP4 E01159 0 +OP4 E0115A 0 +OP4 E0115B 0 +OP4 E0115C 0 +OP4 E0115D 0 +OP4 E0115E 0 +OP4 E0115F 0 +OP4 E01160 0 +OP4 E01161 0 +OP4 E01162 0 +OP4 E01163 0 +OP4 E01164 0 +OP4 E01165 0 +OP4 E01166 0 +OP4 E01167 0 +OP4 E01168 0 +OP4 E01169 0 +OP4 E0116A 0 +OP4 E0116B 0 +OP4 E0116C 0 +OP4 E0116D 0 +OP4 E0116E 0 +OP4 E0116F 0 +OP4 E01170 0 +OP4 E01171 0 +OP4 E01172 0 +OP4 E01173 0 +OP4 E01174 0 +OP4 E01175 0 +OP4 E01176 0 +OP4 E01177 0 +OP4 E01178 0 +OP4 E01179 0 +OP4 E0117A 0 +OP4 E0117B 0 +OP4 E0117C 0 +OP4 E0117D 0 +OP4 E0117E 0 +OP4 E0117F 0 +OP4 E01180 0 +OP4 E01181 0 +OP4 E01182 0 +OP4 E01183 0 +OP4 E01184 0 +OP4 E01185 0 +OP4 E01186 0 +OP4 E01187 0 +OP4 E01188 0 +OP4 E01189 0 +OP4 E0118A 0 +OP4 E0118B 0 +OP4 E0118C 0 +OP4 E0118D 0 +OP4 E0118E 0 +OP4 E0118F 0 +OP4 E01190 0 +OP4 E01191 0 +OP4 E01192 0 +OP4 E01193 0 +OP4 E01194 0 +OP4 E01195 0 +OP4 E01196 0 +OP4 E01197 0 +OP4 E01198 0 +OP4 E01199 0 +OP4 E0119A 0 +OP4 E0119B 0 +OP4 E0119C 0 +OP4 E0119D 0 +OP4 E0119E 0 +OP4 E0119F 0 +OP4 E011A0 0 +OP4 E011A1 0 +OP4 E011A2 0 +OP4 E011A3 0 +OP4 E011A4 0 +OP4 E011A5 0 +OP4 E011A6 0 +OP4 E011A7 0 +OP4 E011A8 0 +OP4 E011A9 0 +OP4 E011AA 0 +OP4 E011AB 0 +OP4 E011AC 0 +OP4 E011AD 0 +OP4 E011AE 0 +OP4 E011AF 0 +OP4 E011B0 0 +OP4 E011B1 0 +OP4 E011B2 0 +OP4 E011B3 0 +OP4 E011B4 0 +OP4 E011B5 0 +OP4 E011B6 0 +OP4 E011B7 0 +OP4 E011B8 0 +OP4 E011B9 0 +OP4 E011BA 0 +OP4 E011BB 0 +OP4 E011BC 0 +OP4 E011BD 0 +OP4 E011BE 0 +OP4 E011BF 0 +OP4 E011C0 0 +OP4 E011C1 0 +OP4 E011C2 0 +OP4 E011C3 0 +OP4 E011C4 0 +OP4 E011C5 0 +OP4 E011C6 0 +OP4 E011C7 0 +OP4 E011C8 0 +OP4 E011C9 0 +OP4 E011CA 0 +OP4 E011CB 0 +OP4 E011CC 0 +OP4 E011CD 0 +OP4 E011CE 0 +OP4 E011CF 0 +OP4 E011D0 0 +OP4 E011D1 0 +OP4 E011D2 0 +OP4 E011D3 0 +OP4 E011D4 0 +OP4 E011D5 0 +OP4 E011D6 0 +OP4 E011D7 0 +OP4 E011D8 0 +OP4 E011D9 0 +OP4 E011DA 0 +OP4 E011DB 0 +OP4 E011DC 0 +OP4 E011DD 0 +OP4 E011DE 0 +OP4 E011DF 0 +OP4 E011E0 0 +OP4 E011E1 0 +OP4 E011E2 0 +OP4 E011E3 0 +OP4 E011E4 0 +OP4 E011E5 0 +OP4 E011E6 0 +OP4 E011E7 0 +OP4 E011E8 0 +OP4 E011E9 0 +OP4 E011EA 0 +OP4 E011EB 0 +OP4 E011EC 0 +OP4 E011ED 0 +OP4 E011EE 0 +OP4 E011EF 0 +OP4 E011F0 0 +OP4 E011F1 0 +OP4 E011F2 0 +OP4 E011F3 0 +OP4 E011F4 0 +OP4 E011F5 0 +OP4 E011F6 0 +OP4 E011F7 0 +OP4 E011F8 0 +OP4 E011F9 0 +OP4 E011FA 0 +OP4 E011FB 0 +OP4 E011FC 0 +OP4 E011FD 0 +OP4 E011FE 0 +OP4 E011FF 0 +OP4 E01200 0 +OP4 E01201 0 +OP4 E01202 0 +OP4 E01203 0 +OP4 E01204 0 +OP4 E01205 0 +OP4 E01206 0 +OP4 E01207 0 +OP4 E01208 0 +OP4 E01209 0 +OP4 E0120A 0 +OP4 E0120B 0 +OP4 E0120C 0 +OP4 E0120D 0 +OP4 E0120E 0 +OP4 E0120F 0 +OP4 E01210 0 +OP4 E01211 0 +OP4 E01212 0 +OP4 E01213 0 +OP4 E01214 0 +OP4 E01215 0 +OP4 E01216 0 +OP4 E01217 0 +OP4 E01218 0 +OP4 E01219 0 +OP4 E0121A 0 +OP4 E0121B 0 +OP4 E0121C 0 +OP4 E0121D 0 +OP4 E0121E 0 +OP4 E0121F 0 +OP4 E01220 0 +OP4 E01221 0 +OP4 E01222 0 +OP4 E01223 0 +OP4 E01224 0 +OP4 E01225 0 +OP4 E01226 0 +OP4 E01227 0 +OP4 E01228 0 +OP4 E01229 0 +OP4 E0122A 0 +OP4 E0122B 0 +OP4 E0122C 0 +OP4 E0122D 0 +OP4 E0122E 0 +OP4 E0122F 0 +OP4 E01230 0 +OP4 E01231 0 +OP4 E01232 0 +OP4 E01233 0 +OP4 E01234 0 +OP4 E01235 0 +OP4 E01236 0 +OP4 E01237 0 +OP4 E01238 0 +OP4 E01239 0 +OP4 E0123A 0 +OP4 E0123B 0 +OP4 E0123C 0 +OP4 E0123D 0 +OP4 E0123E 0 +OP4 E0123F 0 +OP4 E01240 0 +OP4 E01241 0 +OP4 E01242 0 +OP4 E01243 0 +OP4 E01244 0 +OP4 E01245 0 +OP4 E01246 0 +OP4 E01247 0 +OP4 E01248 0 +OP4 E01249 0 +OP4 E0124A 0 +OP4 E0124B 0 +OP4 E0124C 0 +OP4 E0124D 0 +OP4 E0124E 0 +OP4 E0124F 0 +OP4 E01250 0 +OP4 E01251 0 +OP4 E01252 0 +OP4 E01253 0 +OP4 E01254 0 +OP4 E01255 0 +OP4 E01256 0 +OP4 E01257 0 +OP4 E01258 0 +OP4 E01259 0 +OP4 E0125A 0 +OP4 E0125B 0 +OP4 E0125C 0 +OP4 E0125D 0 +OP4 E0125E 0 +OP4 E0125F 0 +OP4 E01260 0 +OP4 E01261 0 +OP4 E01262 0 +OP4 E01263 0 +OP4 E01264 0 +OP4 E01265 0 +OP4 E01266 0 +OP4 E01267 0 +OP4 E01268 0 +OP4 E01269 0 +OP4 E0126A 0 +OP4 E0126B 0 +OP4 E0126C 0 +OP4 E0126D 0 +OP4 E0126E 0 +OP4 E0126F 0 +OP4 E01270 0 +OP4 E01271 0 +OP4 E01272 0 +OP4 E01273 0 +OP4 E01274 0 +OP4 E01275 0 +OP4 E01276 0 +OP4 E01277 0 +OP4 E01278 0 +OP4 E01279 0 +OP4 E0127A 0 +OP4 E0127B 0 +OP4 E0127C 0 +OP4 E0127D 0 +OP4 E0127E 0 +OP4 E0127F 0 +OP4 E01280 0 +OP4 E01281 0 +OP4 E01282 0 +OP4 E01283 0 +OP4 E01284 0 +OP4 E01285 0 +OP4 E01286 0 +OP4 E01287 0 +OP4 E01288 0 +OP4 E01289 0 +OP4 E0128A 0 +OP4 E0128B 0 +OP4 E0128C 0 +OP4 E0128D 0 +OP4 E0128E 0 +OP4 E0128F 0 +OP4 E01290 0 +OP4 E01291 0 +OP4 E01292 0 +OP4 E01293 0 +OP4 E01294 0 +OP4 E01295 0 +OP4 E01296 0 +OP4 E01297 0 +OP4 E01298 0 +OP4 E01299 0 +OP4 E0129A 0 +OP4 E0129B 0 +OP4 E0129C 0 +OP4 E0129D 0 +OP4 E0129E 0 +OP4 E0129F 0 +OP4 E012A0 0 +OP4 E012A1 0 +OP4 E012A2 0 +OP4 E012A3 0 +OP4 E012A4 0 +OP4 E012A5 0 +OP4 E012A6 0 +OP4 E012A7 0 +OP4 E012A8 0 +OP4 E012A9 0 +OP4 E012AA 0 +OP4 E012AB 0 +OP4 E012AC 0 +OP4 E012AD 0 +OP4 E012AE 0 +OP4 E012AF 0 +OP4 E012B0 0 +OP4 E012B1 0 +OP4 E012B2 0 +OP4 E012B3 0 +OP4 E012B4 0 +OP4 E012B5 0 +OP4 E012B6 0 +OP4 E012B7 0 +OP4 E012B8 0 +OP4 E012B9 0 +OP4 E012BA 0 +OP4 E012BB 0 +OP4 E012BC 0 +OP4 E012BD 0 +OP4 E012BE 0 +OP4 E012BF 0 +OP4 E012C0 0 +OP4 E012C1 0 +OP4 E012C2 0 +OP4 E012C3 0 +OP4 E012C4 0 +OP4 E012C5 0 +OP4 E012C6 0 +OP4 E012C7 0 +OP4 E012C8 0 +OP4 E012C9 0 +OP4 E012CA 0 +OP4 E012CB 0 +OP4 E012CC 0 +OP4 E012CD 0 +OP4 E012CE 0 +OP4 E012CF 0 +OP4 E012D0 0 +OP4 E012D1 0 +OP4 E012D2 0 +OP4 E012D3 0 +OP4 E012D4 0 +OP4 E012D5 0 +OP4 E012D6 0 +OP4 E012D7 0 +OP4 E012D8 0 +OP4 E012D9 0 +OP4 E012DA 0 +OP4 E012DB 0 +OP4 E012DC 0 +OP4 E012DD 0 +OP4 E012DE 0 +OP4 E012DF 0 +OP4 E012E0 0 +OP4 E012E1 0 +OP4 E012E2 0 +OP4 E012E3 0 +OP4 E012E4 0 +OP4 E012E5 0 +OP4 E012E6 0 +OP4 E012E7 0 +OP4 E012E8 0 +OP4 E012E9 0 +OP4 E012EA 0 +OP4 E012EB 0 +OP4 E012EC 0 +OP4 E012ED 0 +OP4 E012EE 0 +OP4 E012EF 0 +OP4 E012F0 0 +OP4 E012F1 0 +OP4 E012F2 0 +OP4 E012F3 0 +OP4 E012F4 0 +OP4 E012F5 0 +OP4 E012F6 0 +OP4 E012F7 0 +OP4 E012F8 0 +OP4 E012F9 0 +OP4 E012FA 0 +OP4 E012FB 0 +OP4 E012FC 0 +OP4 E012FD 0 +OP4 E012FE 0 +OP4 E012FF 0 +OP4 E01300 0 +OP4 E01301 0 +OP4 E01302 0 +OP4 E01303 0 +OP4 E01304 0 +OP4 E01305 0 +OP4 E01306 0 +OP4 E01307 0 +OP4 E01308 0 +OP4 E01309 0 +OP4 E0130A 0 +OP4 E0130B 0 +OP4 E0130C 0 +OP4 E0130D 0 +OP4 E0130E 0 +OP4 E0130F 0 +OP4 E01310 0 +OP4 E01311 0 +OP4 E01312 0 +OP4 E01313 0 +OP4 E01314 0 +OP4 E01315 0 +OP4 E01316 0 +OP4 E01317 0 +OP4 E01318 0 +OP4 E01319 0 +OP4 E0131A 0 +OP4 E0131B 0 +OP4 E0131C 0 +OP4 E0131D 0 +OP4 E0131E 0 +OP4 E0131F 0 +OP4 E01320 0 +OP4 E01321 0 +OP4 E01322 0 +OP4 E01323 0 +OP4 E01324 0 +OP4 E01325 0 +OP4 E01326 0 +OP4 E01327 0 +OP4 E01328 0 +OP4 E01329 0 +OP4 E0132A 0 +OP4 E0132B 0 +OP4 E0132C 0 +OP4 E0132D 0 +OP4 E0132E 0 +OP4 E0132F 0 +OP4 E01330 0 +OP4 E01331 0 +OP4 E01332 0 +OP4 E01333 0 +OP4 E01334 0 +OP4 E01335 0 +OP4 E01336 0 +OP4 E01337 0 +OP4 E01338 0 +OP4 E01339 0 +OP4 E0133A 0 +OP4 E0133B 0 +OP4 E0133C 0 +OP4 E0133D 0 +OP4 E0133E 0 +OP4 E0133F 0 +OP4 E01340 0 +OP4 E01341 0 +OP4 E01342 0 +OP4 E01343 0 +OP4 E01344 0 +OP4 E01345 0 +OP4 E01346 0 +OP4 E01347 0 +OP4 E01348 0 +OP4 E01349 0 +OP4 E0134A 0 +OP4 E0134B 0 +OP4 E0134C 0 +OP4 E0134D 0 +OP4 E0134E 0 +OP4 E0134F 0 +OP4 E01350 0 +OP4 E01351 0 +OP4 E01352 0 +OP4 E01353 0 +OP4 E01354 0 +OP4 E01355 0 +OP4 E01356 0 +OP4 E01357 0 +OP4 E01358 0 +OP4 E01359 0 +OP4 E0135A 0 +OP4 E0135B 0 +OP4 E0135C 0 +OP4 E0135D 0 +OP4 E0135E 0 +OP4 E0135F 0 +OP4 E01360 0 +OP4 E01361 0 +OP4 E01362 0 +OP4 E01363 0 +OP4 E01364 0 +OP4 E01365 0 +OP4 E01366 0 +OP4 E01367 0 +OP4 E01368 0 +OP4 E01369 0 +OP4 E0136A 0 +OP4 E0136B 0 +OP4 E0136C 0 +OP4 E0136D 0 +OP4 E0136E 0 +OP4 E0136F 0 +OP4 E01370 0 +OP4 E01371 0 +OP4 E01372 0 +OP4 E01373 0 +OP4 E01374 0 +OP4 E01375 0 +OP4 E01376 0 +OP4 E01377 0 +OP4 E01378 0 +OP4 E01379 0 +OP4 E0137A 0 +OP4 E0137B 0 +OP4 E0137C 0 +OP4 E0137D 0 +OP4 E0137E 0 +OP4 E0137F 0 +OP4 E01380 0 +OP4 E01381 0 +OP4 E01382 0 +OP4 E01383 0 +OP4 E01384 0 +OP4 E01385 0 +OP4 E01386 0 +OP4 E01387 0 +OP4 E01388 0 +OP4 E01389 0 +OP4 E0138A 0 +OP4 E0138B 0 +OP4 E0138C 0 +OP4 E0138D 0 +OP4 E0138E 0 +OP4 E0138F 0 +OP4 E01390 0 +OP4 E01391 0 +OP4 E01392 0 +OP4 E01393 0 +OP4 E01394 0 +OP4 E01395 0 +OP4 E01396 0 +OP4 E01397 0 +OP4 E01398 0 +OP4 E01399 0 +OP4 E0139A 0 +OP4 E0139B 0 +OP4 E0139C 0 +OP4 E0139D 0 +OP4 E0139E 0 +OP4 E0139F 0 +OP4 E013A0 0 +OP4 E013A1 0 +OP4 E013A2 0 +OP4 E013A3 0 +OP4 E013A4 0 +OP4 E013A5 0 +OP4 E013A6 0 +OP4 E013A7 0 +OP4 E013A8 0 +OP4 E013A9 0 +OP4 E013AA 0 +OP4 E013AB 0 +OP4 E013AC 0 +OP4 E013AD 0 +OP4 E013AE 0 +OP4 E013AF 0 +OP4 E013B0 0 +OP4 E013B1 0 +OP4 E013B2 0 +OP4 E013B3 0 +OP4 E013B4 0 +OP4 E013B5 0 +OP4 E013B6 0 +OP4 E013B7 0 +OP4 E013B8 0 +OP4 E013B9 0 +OP4 E013BA 0 +OP4 E013BB 0 +OP4 E013BC 0 +OP4 E013BD 0 +OP4 E013BE 0 +OP4 E013BF 0 +OP4 E013C0 0 +OP4 E013C1 0 +OP4 E013C2 0 +OP4 E013C3 0 +OP4 E013C4 0 +OP4 E013C5 0 +OP4 E013C6 0 +OP4 E013C7 0 +OP4 E013C8 0 +OP4 E013C9 0 +OP4 E013CA 0 +OP4 E013CB 0 +OP4 E013CC 0 +OP4 E013CD 0 +OP4 E013CE 0 +OP4 E013CF 0 +OP4 E013D0 0 +OP4 E013D1 0 +OP4 E013D2 0 +OP4 E013D3 0 +OP4 E013D4 0 +OP4 E013D5 0 +OP4 E013D6 0 +OP4 E013D7 0 +OP4 E013D8 0 +OP4 E013D9 0 +OP4 E013DA 0 +OP4 E013DB 0 +OP4 E013DC 0 +OP4 E013DD 0 +OP4 E013DE 0 +OP4 E013DF 0 +OP4 E013E0 0 +OP4 E013E1 0 +OP4 E013E2 0 +OP4 E013E3 0 +OP4 E013E4 0 +OP4 E013E5 0 +OP4 E013E6 0 +OP4 E013E7 0 +OP4 E013E8 0 +OP4 E013E9 0 +OP4 E013EA 0 +OP4 E013EB 0 +OP4 E013EC 0 +OP4 E013ED 0 +OP4 E013EE 0 +OP4 E013EF 0 +OP4 E013F0 0 +OP4 E013F1 0 +OP4 E013F2 0 +OP4 E013F3 0 +OP4 E013F4 0 +OP4 E013F5 0 +OP4 E013F6 0 +OP4 E013F7 0 +OP4 E013F8 0 +OP4 E013F9 0 +OP4 E013FA 0 +OP4 E013FB 0 +OP4 E013FC 0 +OP4 E013FD 0 +OP4 E013FE 0 +OP4 E013FF 0 +OP4 E01400 0 +OP4 E01401 0 +OP4 E01402 0 +OP4 E01403 0 +OP4 E01404 0 +OP4 E01405 0 +OP4 E01406 0 +OP4 E01407 0 +OP4 E01408 0 +OP4 E01409 0 +OP4 E0140A 0 +OP4 E0140B 0 +OP4 E0140C 0 +OP4 E0140D 0 +OP4 E0140E 0 +OP4 E0140F 0 +OP4 E01410 0 +OP4 E01411 0 +OP4 E01412 0 +OP4 E01413 0 +OP4 E01414 0 +OP4 E01415 0 +OP4 E01416 0 +OP4 E01417 0 +OP4 E01418 0 +OP4 E01419 0 +OP4 E0141A 0 +OP4 E0141B 0 +OP4 E0141C 0 +OP4 E0141D 0 +OP4 E0141E 0 +OP4 E0141F 0 +OP4 E01420 0 +OP4 E01421 0 +OP4 E01422 0 +OP4 E01423 0 +OP4 E01424 0 +OP4 E01425 0 +OP4 E01426 0 +OP4 E01427 0 +OP4 E01428 0 +OP4 E01429 0 +OP4 E0142A 0 +OP4 E0142B 0 +OP4 E0142C 0 +OP4 E0142D 0 +OP4 E0142E 0 +OP4 E0142F 0 +OP4 E01430 0 +OP4 E01431 0 +OP4 E01432 0 +OP4 E01433 0 +OP4 E01434 0 +OP4 E01435 0 +OP4 E01436 0 +OP4 E01437 0 +OP4 E01438 0 +OP4 E01439 0 +OP4 E0143A 0 +OP4 E0143B 0 +OP4 E0143C 0 +OP4 E0143D 0 +OP4 E0143E 0 +OP4 E0143F 0 +OP4 E01440 0 +OP4 E01441 0 +OP4 E01442 0 +OP4 E01443 0 +OP4 E01444 0 +OP4 E01445 0 +OP4 E01446 0 +OP4 E01447 0 +OP4 E01448 0 +OP4 E01449 0 +OP4 E0144A 0 +OP4 E0144B 0 +OP4 E0144C 0 +OP4 E0144D 0 +OP4 E0144E 0 +OP4 E0144F 0 +OP4 E01450 0 +OP4 E01451 0 +OP4 E01452 0 +OP4 E01453 0 +OP4 E01454 0 +OP4 E01455 0 +OP4 E01456 0 +OP4 E01457 0 +OP4 E01458 0 +OP4 E01459 0 +OP4 E0145A 0 +OP4 E0145B 0 +OP4 E0145C 0 +OP4 E0145D 0 +OP4 E0145E 0 +OP4 E0145F 0 +OP4 E01460 0 +OP4 E01461 0 +OP4 E01462 0 +OP4 E01463 0 +OP4 E01464 0 +OP4 E01465 0 +OP4 E01466 0 +OP4 E01467 0 +OP4 E01468 0 +OP4 E01469 0 +OP4 E0146A 0 +OP4 E0146B 0 +OP4 E0146C 0 +OP4 E0146D 0 +OP4 E0146E 0 +OP4 E0146F 0 +OP4 E01470 0 +OP4 E01471 0 +OP4 E01472 0 +OP4 E01473 0 +OP4 E01474 0 +OP4 E01475 0 +OP4 E01476 0 +OP4 E01477 0 +OP4 E01478 0 +OP4 E01479 0 +OP4 E0147A 0 +OP4 E0147B 0 +OP4 E0147C 0 +OP4 E0147D 0 +OP4 E0147E 0 +OP4 E0147F 0 +OP4 E01480 0 +OP4 E01481 0 +OP4 E01482 0 +OP4 E01483 0 +OP4 E01484 0 +OP4 E01485 0 +OP4 E01486 0 +OP4 E01487 0 +OP4 E01488 0 +OP4 E01489 0 +OP4 E0148A 0 +OP4 E0148B 0 +OP4 E0148C 0 +OP4 E0148D 0 +OP4 E0148E 0 +OP4 E0148F 0 +OP4 E01490 0 +OP4 E01491 0 +OP4 E01492 0 +OP4 E01493 0 +OP4 E01494 0 +OP4 E01495 0 +OP4 E01496 0 +OP4 E01497 0 +OP4 E01498 0 +OP4 E01499 0 +OP4 E0149A 0 +OP4 E0149B 0 +OP4 E0149C 0 +OP4 E0149D 0 +OP4 E0149E 0 +OP4 E0149F 0 +OP4 E014A0 0 +OP4 E014A1 0 +OP4 E014A2 0 +OP4 E014A3 0 +OP4 E014A4 0 +OP4 E014A5 0 +OP4 E014A6 0 +OP4 E014A7 0 +OP4 E014A8 0 +OP4 E014A9 0 +OP4 E014AA 0 +OP4 E014AB 0 +OP4 E014AC 0 +OP4 E014AD 0 +OP4 E014AE 0 +OP4 E014AF 0 +OP4 E014B0 0 +OP4 E014B1 0 +OP4 E014B2 0 +OP4 E014B3 0 +OP4 E014B4 0 +OP4 E014B5 0 +OP4 E014B6 0 +OP4 E014B7 0 +OP4 E014B8 0 +OP4 E014B9 0 +OP4 E014BA 0 +OP4 E014BB 0 +OP4 E014BC 0 +OP4 E014BD 0 +OP4 E014BE 0 +OP4 E014BF 0 +OP4 E014C0 0 +OP4 E014C1 0 +OP4 E014C2 0 +OP4 E014C3 0 +OP4 E014C4 0 +OP4 E014C5 0 +OP4 E014C6 0 +OP4 E014C7 0 +OP4 E014C8 0 +OP4 E014C9 0 +OP4 E014CA 0 +OP4 E014CB 0 +OP4 E014CC 0 +OP4 E014CD 0 +OP4 E014CE 0 +OP4 E014CF 0 +OP4 E014D0 0 +OP4 E014D1 0 +OP4 E014D2 0 +OP4 E014D3 0 +OP4 E014D4 0 +OP4 E014D5 0 +OP4 E014D6 0 +OP4 E014D7 0 +OP4 E014D8 0 +OP4 E014D9 0 +OP4 E014DA 0 +OP4 E014DB 0 +OP4 E014DC 0 +OP4 E014DD 0 +OP4 E014DE 0 +OP4 E014DF 0 +OP4 E014E0 0 +OP4 E014E1 0 +OP4 E014E2 0 +OP4 E014E3 0 +OP4 E014E4 0 +OP4 E014E5 0 +OP4 E014E6 0 +OP4 E014E7 0 +OP4 E014E8 0 +OP4 E014E9 0 +OP4 E014EA 0 +OP4 E014EB 0 +OP4 E014EC 0 +OP4 E014ED 0 +OP4 E014EE 0 +OP4 E014EF 0 +OP4 E014F0 0 +OP4 E014F1 0 +OP4 E014F2 0 +OP4 E014F3 0 +OP4 E014F4 0 +OP4 E014F5 0 +OP4 E014F6 0 +OP4 E014F7 0 +OP4 E014F8 0 +OP4 E014F9 0 +OP4 E014FA 0 +OP4 E014FB 0 +OP4 E014FC 0 +OP4 E014FD 0 +OP4 E014FE 0 +OP4 E014FF 0 +OP4 E01500 0 +OP4 E01501 0 +OP4 E01502 0 +OP4 E01503 0 +OP4 E01504 0 +OP4 E01505 0 +OP4 E01506 0 +OP4 E01507 0 +OP4 E01508 0 +OP4 E01509 0 +OP4 E0150A 0 +OP4 E0150B 0 +OP4 E0150C 0 +OP4 E0150D 0 +OP4 E0150E 0 +OP4 E0150F 0 +OP4 E01510 0 +OP4 E01511 0 +OP4 E01512 0 +OP4 E01513 0 +OP4 E01514 0 +OP4 E01515 0 +OP4 E01516 0 +OP4 E01517 0 +OP4 E01518 0 +OP4 E01519 0 +OP4 E0151A 0 +OP4 E0151B 0 +OP4 E0151C 0 +OP4 E0151D 0 +OP4 E0151E 0 +OP4 E0151F 0 +OP4 E01520 0 +OP4 E01521 0 +OP4 E01522 0 +OP4 E01523 0 +OP4 E01524 0 +OP4 E01525 0 +OP4 E01526 0 +OP4 E01527 0 +OP4 E01528 0 +OP4 E01529 0 +OP4 E0152A 0 +OP4 E0152B 0 +OP4 E0152C 0 +OP4 E0152D 0 +OP4 E0152E 0 +OP4 E0152F 0 +OP4 E01530 0 +OP4 E01531 0 +OP4 E01532 0 +OP4 E01533 0 +OP4 E01534 0 +OP4 E01535 0 +OP4 E01536 0 +OP4 E01537 0 +OP4 E01538 0 +OP4 E01539 0 +OP4 E0153A 0 +OP4 E0153B 0 +OP4 E0153C 0 +OP4 E0153D 0 +OP4 E0153E 0 +OP4 E0153F 0 +OP4 E01540 0 +OP4 E01541 0 +OP4 E01542 0 +OP4 E01543 0 +OP4 E01544 0 +OP4 E01545 0 +OP4 E01546 0 +OP4 E01547 0 +OP4 E01548 0 +OP4 E01549 0 +OP4 E0154A 0 +OP4 E0154B 0 +OP4 E0154C 0 +OP4 E0154D 0 +OP4 E0154E 0 +OP4 E0154F 0 +OP4 E01550 0 +OP4 E01551 0 +OP4 E01552 0 +OP4 E01553 0 +OP4 E01554 0 +OP4 E01555 0 +OP4 E01556 0 +OP4 E01557 0 +OP4 E01558 0 +OP4 E01559 0 +OP4 E0155A 0 +OP4 E0155B 0 +OP4 E0155C 0 +OP4 E0155D 0 +OP4 E0155E 0 +OP4 E0155F 0 +OP4 E01560 0 +OP4 E01561 0 +OP4 E01562 0 +OP4 E01563 0 +OP4 E01564 0 +OP4 E01565 0 +OP4 E01566 0 +OP4 E01567 0 +OP4 E01568 0 +OP4 E01569 0 +OP4 E0156A 0 +OP4 E0156B 0 +OP4 E0156C 0 +OP4 E0156D 0 +OP4 E0156E 0 +OP4 E0156F 0 +OP4 E01570 0 +OP4 E01571 0 +OP4 E01572 0 +OP4 E01573 0 +OP4 E01574 0 +OP4 E01575 0 +OP4 E01576 0 +OP4 E01577 0 +OP4 E01578 0 +OP4 E01579 0 +OP4 E0157A 0 +OP4 E0157B 0 +OP4 E0157C 0 +OP4 E0157D 0 +OP4 E0157E 0 +OP4 E0157F 0 +OP4 E01580 0 +OP4 E01581 0 +OP4 E01582 0 +OP4 E01583 0 +OP4 E01584 0 +OP4 E01585 0 +OP4 E01586 0 +OP4 E01587 0 +OP4 E01588 0 +OP4 E01589 0 +OP4 E0158A 0 +OP4 E0158B 0 +OP4 E0158C 0 +OP4 E0158D 0 +OP4 E0158E 0 +OP4 E0158F 0 +OP4 E01590 0 +OP4 E01591 0 +OP4 E01592 0 +OP4 E01593 0 +OP4 E01594 0 +OP4 E01595 0 +OP4 E01596 0 +OP4 E01597 0 +OP4 E01598 0 +OP4 E01599 0 +OP4 E0159A 0 +OP4 E0159B 0 +OP4 E0159C 0 +OP4 E0159D 0 +OP4 E0159E 0 +OP4 E0159F 0 +OP4 E015A0 0 +OP4 E015A1 0 +OP4 E015A2 0 +OP4 E015A3 0 +OP4 E015A4 0 +OP4 E015A5 0 +OP4 E015A6 0 +OP4 E015A7 0 +OP4 E015A8 0 +OP4 E015A9 0 +OP4 E015AA 0 +OP4 E015AB 0 +OP4 E015AC 0 +OP4 E015AD 0 +OP4 E015AE 0 +OP4 E015AF 0 +OP4 E015B0 0 +OP4 E015B1 0 +OP4 E015B2 0 +OP4 E015B3 0 +OP4 E015B4 0 +OP4 E015B5 0 +OP4 E015B6 0 +OP4 E015B7 0 +OP4 E015B8 0 +OP4 E015B9 0 +OP4 E015BA 0 +OP4 E015BB 0 +OP4 E015BC 0 +OP4 E015BD 0 +OP4 E015BE 0 +OP4 E015BF 0 +OP4 E015C0 0 +OP4 E015C1 0 +OP4 E015C2 0 +OP4 E015C3 0 +OP4 E015C4 0 +OP4 E015C5 0 +OP4 E015C6 0 +OP4 E015C7 0 +OP4 E015C8 0 +OP4 E015C9 0 +OP4 E015CA 0 +OP4 E015CB 0 +OP4 E015CC 0 +OP4 E015CD 0 +OP4 E015CE 0 +OP4 E015CF 0 +OP4 E015D0 0 +OP4 E015D1 0 +OP4 E015D2 0 +OP4 E015D3 0 +OP4 E015D4 0 +OP4 E015D5 0 +OP4 E015D6 0 +OP4 E015D7 0 +OP4 E015D8 0 +OP4 E015D9 0 +OP4 E015DA 0 +OP4 E015DB 0 +OP4 E015DC 0 +OP4 E015DD 0 +OP4 E015DE 0 +OP4 E015DF 0 +OP4 E015E0 0 +OP4 E015E1 0 +OP4 E015E2 0 +OP4 E015E3 0 +OP4 E015E4 0 +OP4 E015E5 0 +OP4 E015E6 0 +OP4 E015E7 0 +OP4 E015E8 0 +OP4 E015E9 0 +OP4 E015EA 0 +OP4 E015EB 0 +OP4 E015EC 0 +OP4 E015ED 0 +OP4 E015EE 0 +OP4 E015EF 0 +OP4 E015F0 0 +OP4 E015F1 0 +OP4 E015F2 0 +OP4 E015F3 0 +OP4 E015F4 0 +OP4 E015F5 0 +OP4 E015F6 0 +OP4 E015F7 0 +OP4 E015F8 0 +OP4 E015F9 0 +OP4 E015FA 0 +OP4 E015FB 0 +OP4 E015FC 0 +OP4 E015FD 0 +OP4 E015FE 0 +OP4 E015FF 0 +OP4 E01600 0 +OP4 E01601 0 +OP4 E01602 0 +OP4 E01603 0 +OP4 E01604 0 +OP4 E01605 0 +OP4 E01606 0 +OP4 E01607 0 +OP4 E01608 0 +OP4 E01609 0 +OP4 E0160A 0 +OP4 E0160B 0 +OP4 E0160C 0 +OP4 E0160D 0 +OP4 E0160E 0 +OP4 E0160F 0 +OP4 E01610 0 +OP4 E01611 0 +OP4 E01612 0 +OP4 E01613 0 +OP4 E01614 0 +OP4 E01615 0 +OP4 E01616 0 +OP4 E01617 0 +OP4 E01618 0 +OP4 E01619 0 +OP4 E0161A 0 +OP4 E0161B 0 +OP4 E0161C 0 +OP4 E0161D 0 +OP4 E0161E 0 +OP4 E0161F 0 +OP4 E01620 0 +OP4 E01621 0 +OP4 E01622 0 +OP4 E01623 0 +OP4 E01624 0 +OP4 E01625 0 +OP4 E01626 0 +OP4 E01627 0 +OP4 E01628 0 +OP4 E01629 0 +OP4 E0162A 0 +OP4 E0162B 0 +OP4 E0162C 0 +OP4 E0162D 0 +OP4 E0162E 0 +OP4 E0162F 0 +OP4 E01630 0 +OP4 E01631 0 +OP4 E01632 0 +OP4 E01633 0 +OP4 E01634 0 +OP4 E01635 0 +OP4 E01636 0 +OP4 E01637 0 +OP4 E01638 0 +OP4 E01639 0 +OP4 E0163A 0 +OP4 E0163B 0 +OP4 E0163C 0 +OP4 E0163D 0 +OP4 E0163E 0 +OP4 E0163F 0 +OP4 E01640 0 +OP4 E01641 0 +OP4 E01642 0 +OP4 E01643 0 +OP4 E01644 0 +OP4 E01645 0 +OP4 E01646 0 +OP4 E01647 0 +OP4 E01648 0 +OP4 E01649 0 +OP4 E0164A 0 +OP4 E0164B 0 +OP4 E0164C 0 +OP4 E0164D 0 +OP4 E0164E 0 +OP4 E0164F 0 +OP4 E01650 0 +OP4 E01651 0 +OP4 E01652 0 +OP4 E01653 0 +OP4 E01654 0 +OP4 E01655 0 +OP4 E01656 0 +OP4 E01657 0 +OP4 E01658 0 +OP4 E01659 0 +OP4 E0165A 0 +OP4 E0165B 0 +OP4 E0165C 0 +OP4 E0165D 0 +OP4 E0165E 0 +OP4 E0165F 0 +OP4 E01660 0 +OP4 E01661 0 +OP4 E01662 0 +OP4 E01663 0 +OP4 E01664 0 +OP4 E01665 0 +OP4 E01666 0 +OP4 E01667 0 +OP4 E01668 0 +OP4 E01669 0 +OP4 E0166A 0 +OP4 E0166B 0 +OP4 E0166C 0 +OP4 E0166D 0 +OP4 E0166E 0 +OP4 E0166F 0 +OP4 E01670 0 +OP4 E01671 0 +OP4 E01672 0 +OP4 E01673 0 +OP4 E01674 0 +OP4 E01675 0 +OP4 E01676 0 +OP4 E01677 0 +OP4 E01678 0 +OP4 E01679 0 +OP4 E0167A 0 +OP4 E0167B 0 +OP4 E0167C 0 +OP4 E0167D 0 +OP4 E0167E 0 +OP4 E0167F 0 +OP4 E01680 0 +OP4 E01681 0 +OP4 E01682 0 +OP4 E01683 0 +OP4 E01684 0 +OP4 E01685 0 +OP4 E01686 0 +OP4 E01687 0 +OP4 E01688 0 +OP4 E01689 0 +OP4 E0168A 0 +OP4 E0168B 0 +OP4 E0168C 0 +OP4 E0168D 0 +OP4 E0168E 0 +OP4 E0168F 0 +OP4 E01690 0 +OP4 E01691 0 +OP4 E01692 0 +OP4 E01693 0 +OP4 E01694 0 +OP4 E01695 0 +OP4 E01696 0 +OP4 E01697 0 +OP4 E01698 0 +OP4 E01699 0 +OP4 E0169A 0 +OP4 E0169B 0 +OP4 E0169C 0 +OP4 E0169D 0 +OP4 E0169E 0 +OP4 E0169F 0 +OP4 E016A0 0 +OP4 E016A1 0 +OP4 E016A2 0 +OP4 E016A3 0 +OP4 E016A4 0 +OP4 E016A5 0 +OP4 E016A6 0 +OP4 E016A7 0 +OP4 E016A8 0 +OP4 E016A9 0 +OP4 E016AA 0 +OP4 E016AB 0 +OP4 E016AC 0 +OP4 E016AD 0 +OP4 E016AE 0 +OP4 E016AF 0 +OP4 E016B0 0 +OP4 E016B1 0 +OP4 E016B2 0 +OP4 E016B3 0 +OP4 E016B4 0 +OP4 E016B5 0 +OP4 E016B6 0 +OP4 E016B7 0 +OP4 E016B8 0 +OP4 E016B9 0 +OP4 E016BA 0 +OP4 E016BB 0 +OP4 E016BC 0 +OP4 E016BD 0 +OP4 E016BE 0 +OP4 E016BF 0 +OP4 E016C0 0 +OP4 E016C1 0 +OP4 E016C2 0 +OP4 E016C3 0 +OP4 E016C4 0 +OP4 E016C5 0 +OP4 E016C6 0 +OP4 E016C7 0 +OP4 E016C8 0 +OP4 E016C9 0 +OP4 E016CA 0 +OP4 E016CB 0 +OP4 E016CC 0 +OP4 E016CD 0 +OP4 E016CE 0 +OP4 E016CF 0 +OP4 E016D0 0 +OP4 E016D1 0 +OP4 E016D2 0 +OP4 E016D3 0 +OP4 E016D4 0 +OP4 E016D5 0 +OP4 E016D6 0 +OP4 E016D7 0 +OP4 E016D8 0 +OP4 E016D9 0 +OP4 E016DA 0 +OP4 E016DB 0 +OP4 E016DC 0 +OP4 E016DD 0 +OP4 E016DE 0 +OP4 E016DF 0 +OP4 E016E0 0 +OP4 E016E1 0 +OP4 E016E2 0 +OP4 E016E3 0 +OP4 E016E4 0 +OP4 E016E5 0 +OP4 E016E6 0 +OP4 E016E7 0 +OP4 E016E8 0 +OP4 E016E9 0 +OP4 E016EA 0 +OP4 E016EB 0 +OP4 E016EC 0 +OP4 E016ED 0 +OP4 E016EE 0 +OP4 E016EF 0 +OP4 E016F0 0 +OP4 E016F1 0 +OP4 E016F2 0 +OP4 E016F3 0 +OP4 E016F4 0 +OP4 E016F5 0 +OP4 E016F6 0 +OP4 E016F7 0 +OP4 E016F8 0 +OP4 E016F9 0 +OP4 E016FA 0 +OP4 E016FB 0 +OP4 E016FC 0 +OP4 E016FD 0 +OP4 E016FE 0 +OP4 E016FF 0 +OP4 E01700 0 +OP4 E01701 0 +OP4 E01702 0 +OP4 E01703 0 +OP4 E01704 0 +OP4 E01705 0 +OP4 E01706 0 +OP4 E01707 0 +OP4 E01708 0 +OP4 E01709 0 +OP4 E0170A 0 +OP4 E0170B 0 +OP4 E0170C 0 +OP4 E0170D 0 +OP4 E0170E 0 +OP4 E0170F 0 +OP4 E01710 0 +OP4 E01711 0 +OP4 E01712 0 +OP4 E01713 0 +OP4 E01714 0 +OP4 E01715 0 +OP4 E01716 0 +OP4 E01717 0 +OP4 E01718 0 +OP4 E01719 0 +OP4 E0171A 0 +OP4 E0171B 0 +OP4 E0171C 0 +OP4 E0171D 0 +OP4 E0171E 0 +OP4 E0171F 0 +OP4 E01720 0 +OP4 E01721 0 +OP4 E01722 0 +OP4 E01723 0 +OP4 E01724 0 +OP4 E01725 0 +OP4 E01726 0 +OP4 E01727 0 +OP4 E01728 0 +OP4 E01729 0 +OP4 E0172A 0 +OP4 E0172B 0 +OP4 E0172C 0 +OP4 E0172D 0 +OP4 E0172E 0 +OP4 E0172F 0 +OP4 E01730 0 +OP4 E01731 0 +OP4 E01732 0 +OP4 E01733 0 +OP4 E01734 0 +OP4 E01735 0 +OP4 E01736 0 +OP4 E01737 0 +OP4 E01738 0 +OP4 E01739 0 +OP4 E0173A 0 +OP4 E0173B 0 +OP4 E0173C 0 +OP4 E0173D 0 +OP4 E0173E 0 +OP4 E0173F 0 +OP4 E01740 0 +OP4 E01741 0 +OP4 E01742 0 +OP4 E01743 0 +OP4 E01744 0 +OP4 E01745 0 +OP4 E01746 0 +OP4 E01747 0 +OP4 E01748 0 +OP4 E01749 0 +OP4 E0174A 0 +OP4 E0174B 0 +OP4 E0174C 0 +OP4 E0174D 0 +OP4 E0174E 0 +OP4 E0174F 0 +OP4 E01750 0 +OP4 E01751 0 +OP4 E01752 0 +OP4 E01753 0 +OP4 E01754 0 +OP4 E01755 0 +OP4 E01756 0 +OP4 E01757 0 +OP4 E01758 0 +OP4 E01759 0 +OP4 E0175A 0 +OP4 E0175B 0 +OP4 E0175C 0 +OP4 E0175D 0 +OP4 E0175E 0 +OP4 E0175F 0 +OP4 E01760 0 +OP4 E01761 0 +OP4 E01762 0 +OP4 E01763 0 +OP4 E01764 0 +OP4 E01765 0 +OP4 E01766 0 +OP4 E01767 0 +OP4 E01768 0 +OP4 E01769 0 +OP4 E0176A 0 +OP4 E0176B 0 +OP4 E0176C 0 +OP4 E0176D 0 +OP4 E0176E 0 +OP4 E0176F 0 +OP4 E01770 0 +OP4 E01771 0 +OP4 E01772 0 +OP4 E01773 0 +OP4 E01774 0 +OP4 E01775 0 +OP4 E01776 0 +OP4 E01777 0 +OP4 E01778 0 +OP4 E01779 0 +OP4 E0177A 0 +OP4 E0177B 0 +OP4 E0177C 0 +OP4 E0177D 0 +OP4 E0177E 0 +OP4 E0177F 0 +OP4 E01780 0 +OP4 E01781 0 +OP4 E01782 0 +OP4 E01783 0 +OP4 E01784 0 +OP4 E01785 0 +OP4 E01786 0 +OP4 E01787 0 +OP4 E01788 0 +OP4 E01789 0 +OP4 E0178A 0 +OP4 E0178B 0 +OP4 E0178C 0 +OP4 E0178D 0 +OP4 E0178E 0 +OP4 E0178F 0 +OP4 E01790 0 +OP4 E01791 0 +OP4 E01792 0 +OP4 E01793 0 +OP4 E01794 0 +OP4 E01795 0 +OP4 E01796 0 +OP4 E01797 0 +OP4 E01798 0 +OP4 E01799 0 +OP4 E0179A 0 +OP4 E0179B 0 +OP4 E0179C 0 +OP4 E0179D 0 +OP4 E0179E 0 +OP4 E0179F 0 +OP4 E017A0 0 +OP4 E017A1 0 +OP4 E017A2 0 +OP4 E017A3 0 +OP4 E017A4 0 +OP4 E017A5 0 +OP4 E017A6 0 +OP4 E017A7 0 +OP4 E017A8 0 +OP4 E017A9 0 +OP4 E017AA 0 +OP4 E017AB 0 +OP4 E017AC 0 +OP4 E017AD 0 +OP4 E017AE 0 +OP4 E017AF 0 +OP4 E017B0 0 +OP4 E017B1 0 +OP4 E017B2 0 +OP4 E017B3 0 +OP4 E017B4 0 +OP4 E017B5 0 +OP4 E017B6 0 +OP4 E017B7 0 +OP4 E017B8 0 +OP4 E017B9 0 +OP4 E017BA 0 +OP4 E017BB 0 +OP4 E017BC 0 +OP4 E017BD 0 +OP4 E017BE 0 +OP4 E017BF 0 +OP4 E017C0 0 +OP4 E017C1 0 +OP4 E017C2 0 +OP4 E017C3 0 +OP4 E017C4 0 +OP4 E017C5 0 +OP4 E017C6 0 +OP4 E017C7 0 +OP4 E017C8 0 +OP4 E017C9 0 +OP4 E017CA 0 +OP4 E017CB 0 +OP4 E017CC 0 +OP4 E017CD 0 +OP4 E017CE 0 +OP4 E017CF 0 +OP4 E017D0 0 +OP4 E017D1 0 +OP4 E017D2 0 +OP4 E017D3 0 +OP4 E017D4 0 +OP4 E017D5 0 +OP4 E017D6 0 +OP4 E017D7 0 +OP4 E017D8 0 +OP4 E017D9 0 +OP4 E017DA 0 +OP4 E017DB 0 +OP4 E017DC 0 +OP4 E017DD 0 +OP4 E017DE 0 +OP4 E017DF 0 +OP4 E017E0 0 +OP4 E017E1 0 +OP4 E017E2 0 +OP4 E017E3 0 +OP4 E017E4 0 +OP4 E017E5 0 +OP4 E017E6 0 +OP4 E017E7 0 +OP4 E017E8 0 +OP4 E017E9 0 +OP4 E017EA 0 +OP4 E017EB 0 +OP4 E017EC 0 +OP4 E017ED 0 +OP4 E017EE 0 +OP4 E017EF 0 +OP4 E017F0 0 +OP4 E017F1 0 +OP4 E017F2 0 +OP4 E017F3 0 +OP4 E017F4 0 +OP4 E017F5 0 +OP4 E017F6 0 +OP4 E017F7 0 +OP4 E017F8 0 +OP4 E017F9 0 +OP4 E017FA 0 +OP4 E017FB 0 +OP4 E017FC 0 +OP4 E017FD 0 +OP4 E017FE 0 +OP4 E017FF 0 +OP4 E01800 0 +OP4 E01801 0 +OP4 E01802 0 +OP4 E01803 0 +OP4 E01804 0 +OP4 E01805 0 +OP4 E01806 0 +OP4 E01807 0 +OP4 E01808 0 +OP4 E01809 0 +OP4 E0180A 0 +OP4 E0180B 0 +OP4 E0180C 0 +OP4 E0180D 0 +OP4 E0180E 0 +OP4 E0180F 0 +OP4 E01810 0 +OP4 E01811 0 +OP4 E01812 0 +OP4 E01813 0 +OP4 E01814 0 +OP4 E01815 0 +OP4 E01816 0 +OP4 E01817 0 +OP4 E01818 0 +OP4 E01819 0 +OP4 E0181A 0 +OP4 E0181B 0 +OP4 E0181C 0 +OP4 E0181D 0 +OP4 E0181E 0 +OP4 E0181F 0 +OP4 E01820 0 +OP4 E01821 0 +OP4 E01822 0 +OP4 E01823 0 +OP4 E01824 0 +OP4 E01825 0 +OP4 E01826 0 +OP4 E01827 0 +OP4 E01828 0 +OP4 E01829 0 +OP4 E0182A 0 +OP4 E0182B 0 +OP4 E0182C 0 +OP4 E0182D 0 +OP4 E0182E 0 +OP4 E0182F 0 +OP4 E01830 0 +OP4 E01831 0 +OP4 E01832 0 +OP4 E01833 0 +OP4 E01834 0 +OP4 E01835 0 +OP4 E01836 0 +OP4 E01837 0 +OP4 E01838 0 +OP4 E01839 0 +OP4 E0183A 0 +OP4 E0183B 0 +OP4 E0183C 0 +OP4 E0183D 0 +OP4 E0183E 0 +OP4 E0183F 0 +OP4 E01840 0 +OP4 E01841 0 +OP4 E01842 0 +OP4 E01843 0 +OP4 E01844 0 +OP4 E01845 0 +OP4 E01846 0 +OP4 E01847 0 +OP4 E01848 0 +OP4 E01849 0 +OP4 E0184A 0 +OP4 E0184B 0 +OP4 E0184C 0 +OP4 E0184D 0 +OP4 E0184E 0 +OP4 E0184F 0 +OP4 E01850 0 +OP4 E01851 0 +OP4 E01852 0 +OP4 E01853 0 +OP4 E01854 0 +OP4 E01855 0 +OP4 E01856 0 +OP4 E01857 0 +OP4 E01858 0 +OP4 E01859 0 +OP4 E0185A 0 +OP4 E0185B 0 +OP4 E0185C 0 +OP4 E0185D 0 +OP4 E0185E 0 +OP4 E0185F 0 +OP4 E01860 0 +OP4 E01861 0 +OP4 E01862 0 +OP4 E01863 0 +OP4 E01864 0 +OP4 E01865 0 +OP4 E01866 0 +OP4 E01867 0 +OP4 E01868 0 +OP4 E01869 0 +OP4 E0186A 0 +OP4 E0186B 0 +OP4 E0186C 0 +OP4 E0186D 0 +OP4 E0186E 0 +OP4 E0186F 0 +OP4 E01870 0 +OP4 E01871 0 +OP4 E01872 0 +OP4 E01873 0 +OP4 E01874 0 +OP4 E01875 0 +OP4 E01876 0 +OP4 E01877 0 +OP4 E01878 0 +OP4 E01879 0 +OP4 E0187A 0 +OP4 E0187B 0 +OP4 E0187C 0 +OP4 E0187D 0 +OP4 E0187E 0 +OP4 E0187F 0 +OP4 E01880 0 +OP4 E01881 0 +OP4 E01882 0 +OP4 E01883 0 +OP4 E01884 0 +OP4 E01885 0 +OP4 E01886 0 +OP4 E01887 0 +OP4 E01888 0 +OP4 E01889 0 +OP4 E0188A 0 +OP4 E0188B 0 +OP4 E0188C 0 +OP4 E0188D 0 +OP4 E0188E 0 +OP4 E0188F 0 +OP4 E01890 0 +OP4 E01891 0 +OP4 E01892 0 +OP4 E01893 0 +OP4 E01894 0 +OP4 E01895 0 +OP4 E01896 0 +OP4 E01897 0 +OP4 E01898 0 +OP4 E01899 0 +OP4 E0189A 0 +OP4 E0189B 0 +OP4 E0189C 0 +OP4 E0189D 0 +OP4 E0189E 0 +OP4 E0189F 0 +OP4 E018A0 0 +OP4 E018A1 0 +OP4 E018A2 0 +OP4 E018A3 0 +OP4 E018A4 0 +OP4 E018A5 0 +OP4 E018A6 0 +OP4 E018A7 0 +OP4 E018A8 0 +OP4 E018A9 0 +OP4 E018AA 0 +OP4 E018AB 0 +OP4 E018AC 0 +OP4 E018AD 0 +OP4 E018AE 0 +OP4 E018AF 0 +OP4 E018B0 0 +OP4 E018B1 0 +OP4 E018B2 0 +OP4 E018B3 0 +OP4 E018B4 0 +OP4 E018B5 0 +OP4 E018B6 0 +OP4 E018B7 0 +OP4 E018B8 0 +OP4 E018B9 0 +OP4 E018BA 0 +OP4 E018BB 0 +OP4 E018BC 0 +OP4 E018BD 0 +OP4 E018BE 0 +OP4 E018BF 0 +OP4 E018C0 0 +OP4 E018C1 0 +OP4 E018C2 0 +OP4 E018C3 0 +OP4 E018C4 0 +OP4 E018C5 0 +OP4 E018C6 0 +OP4 E018C7 0 +OP4 E018C8 0 +OP4 E018C9 0 +OP4 E018CA 0 +OP4 E018CB 0 +OP4 E018CC 0 +OP4 E018CD 0 +OP4 E018CE 0 +OP4 E018CF 0 +OP4 E018D0 0 +OP4 E018D1 0 +OP4 E018D2 0 +OP4 E018D3 0 +OP4 E018D4 0 +OP4 E018D5 0 +OP4 E018D6 0 +OP4 E018D7 0 +OP4 E018D8 0 +OP4 E018D9 0 +OP4 E018DA 0 +OP4 E018DB 0 +OP4 E018DC 0 +OP4 E018DD 0 +OP4 E018DE 0 +OP4 E018DF 0 +OP4 E018E0 0 +OP4 E018E1 0 +OP4 E018E2 0 +OP4 E018E3 0 +OP4 E018E4 0 +OP4 E018E5 0 +OP4 E018E6 0 +OP4 E018E7 0 +OP4 E018E8 0 +OP4 E018E9 0 +OP4 E018EA 0 +OP4 E018EB 0 +OP4 E018EC 0 +OP4 E018ED 0 +OP4 E018EE 0 +OP4 E018EF 0 +OP4 E018F0 0 +OP4 E018F1 0 +OP4 E018F2 0 +OP4 E018F3 0 +OP4 E018F4 0 +OP4 E018F5 0 +OP4 E018F6 0 +OP4 E018F7 0 +OP4 E018F8 0 +OP4 E018F9 0 +OP4 E018FA 0 +OP4 E018FB 0 +OP4 E018FC 0 +OP4 E018FD 0 +OP4 E018FE 0 +OP4 E018FF 0 +OP4 E01900 0 +OP4 E01901 0 +OP4 E01902 0 +OP4 E01903 0 +OP4 E01904 0 +OP4 E01905 0 +OP4 E01906 0 +OP4 E01907 0 +OP4 E01908 0 +OP4 E01909 0 +OP4 E0190A 0 +OP4 E0190B 0 +OP4 E0190C 0 +OP4 E0190D 0 +OP4 E0190E 0 +OP4 E0190F 0 +OP4 E01910 0 +OP4 E01911 0 +OP4 E01912 0 +OP4 E01913 0 +OP4 E01914 0 +OP4 E01915 0 +OP4 E01916 0 +OP4 E01917 0 +OP4 E01918 0 +OP4 E01919 0 +OP4 E0191A 0 +OP4 E0191B 0 +OP4 E0191C 0 +OP4 E0191D 0 +OP4 E0191E 0 +OP4 E0191F 0 +OP4 E01920 0 +OP4 E01921 0 +OP4 E01922 0 +OP4 E01923 0 +OP4 E01924 0 +OP4 E01925 0 +OP4 E01926 0 +OP4 E01927 0 +OP4 E01928 0 +OP4 E01929 0 +OP4 E0192A 0 +OP4 E0192B 0 +OP4 E0192C 0 +OP4 E0192D 0 +OP4 E0192E 0 +OP4 E0192F 0 +OP4 E01930 0 +OP4 E01931 0 +OP4 E01932 0 +OP4 E01933 0 +OP4 E01934 0 +OP4 E01935 0 +OP4 E01936 0 +OP4 E01937 0 +OP4 E01938 0 +OP4 E01939 0 +OP4 E0193A 0 +OP4 E0193B 0 +OP4 E0193C 0 +OP4 E0193D 0 +OP4 E0193E 0 +OP4 E0193F 0 +OP4 E01940 0 +OP4 E01941 0 +OP4 E01942 0 +OP4 E01943 0 +OP4 E01944 0 +OP4 E01945 0 +OP4 E01946 0 +OP4 E01947 0 +OP4 E01948 0 +OP4 E01949 0 +OP4 E0194A 0 +OP4 E0194B 0 +OP4 E0194C 0 +OP4 E0194D 0 +OP4 E0194E 0 +OP4 E0194F 0 +OP4 E01950 0 +OP4 E01951 0 +OP4 E01952 0 +OP4 E01953 0 +OP4 E01954 0 +OP4 E01955 0 +OP4 E01956 0 +OP4 E01957 0 +OP4 E01958 0 +OP4 E01959 0 +OP4 E0195A 0 +OP4 E0195B 0 +OP4 E0195C 0 +OP4 E0195D 0 +OP4 E0195E 0 +OP4 E0195F 0 +OP4 E01960 0 +OP4 E01961 0 +OP4 E01962 0 +OP4 E01963 0 +OP4 E01964 0 +OP4 E01965 0 +OP4 E01966 0 +OP4 E01967 0 +OP4 E01968 0 +OP4 E01969 0 +OP4 E0196A 0 +OP4 E0196B 0 +OP4 E0196C 0 +OP4 E0196D 0 +OP4 E0196E 0 +OP4 E0196F 0 +OP4 E01970 0 +OP4 E01971 0 +OP4 E01972 0 +OP4 E01973 0 +OP4 E01974 0 +OP4 E01975 0 +OP4 E01976 0 +OP4 E01977 0 +OP4 E01978 0 +OP4 E01979 0 +OP4 E0197A 0 +OP4 E0197B 0 +OP4 E0197C 0 +OP4 E0197D 0 +OP4 E0197E 0 +OP4 E0197F 0 +OP4 E01980 0 +OP4 E01981 0 +OP4 E01982 0 +OP4 E01983 0 +OP4 E01984 0 +OP4 E01985 0 +OP4 E01986 0 +OP4 E01987 0 +OP4 E01988 0 +OP4 E01989 0 +OP4 E0198A 0 +OP4 E0198B 0 +OP4 E0198C 0 +OP4 E0198D 0 +OP4 E0198E 0 +OP4 E0198F 0 +OP4 E01990 0 +OP4 E01991 0 +OP4 E01992 0 +OP4 E01993 0 +OP4 E01994 0 +OP4 E01995 0 +OP4 E01996 0 +OP4 E01997 0 +OP4 E01998 0 +OP4 E01999 0 +OP4 E0199A 0 +OP4 E0199B 0 +OP4 E0199C 0 +OP4 E0199D 0 +OP4 E0199E 0 +OP4 E0199F 0 +OP4 E019A0 0 +OP4 E019A1 0 +OP4 E019A2 0 +OP4 E019A3 0 +OP4 E019A4 0 +OP4 E019A5 0 +OP4 E019A6 0 +OP4 E019A7 0 +OP4 E019A8 0 +OP4 E019A9 0 +OP4 E019AA 0 +OP4 E019AB 0 +OP4 E019AC 0 +OP4 E019AD 0 +OP4 E019AE 0 +OP4 E019AF 0 +OP4 E019B0 0 +OP4 E019B1 0 +OP4 E019B2 0 +OP4 E019B3 0 +OP4 E019B4 0 +OP4 E019B5 0 +OP4 E019B6 0 +OP4 E019B7 0 +OP4 E019B8 0 +OP4 E019B9 0 +OP4 E019BA 0 +OP4 E019BB 0 +OP4 E019BC 0 +OP4 E019BD 0 +OP4 E019BE 0 +OP4 E019BF 0 +OP4 E019C0 0 +OP4 E019C1 0 +OP4 E019C2 0 +OP4 E019C3 0 +OP4 E019C4 0 +OP4 E019C5 0 +OP4 E019C6 0 +OP4 E019C7 0 +OP4 E019C8 0 +OP4 E019C9 0 +OP4 E019CA 0 +OP4 E019CB 0 +OP4 E019CC 0 +OP4 E019CD 0 +OP4 E019CE 0 +OP4 E019CF 0 +OP4 E019D0 0 +OP4 E019D1 0 +OP4 E019D2 0 +OP4 E019D3 0 +OP4 E019D4 0 +OP4 E019D5 0 +OP4 E019D6 0 +OP4 E019D7 0 +OP4 E019D8 0 +OP4 E019D9 0 +OP4 E019DA 0 +OP4 E019DB 0 +OP4 E019DC 0 +OP4 E019DD 0 +OP4 E019DE 0 +OP4 E019DF 0 +OP4 E019E0 0 +OP4 E019E1 0 +OP4 E019E2 0 +OP4 E019E3 0 +OP4 E019E4 0 +OP4 E019E5 0 +OP4 E019E6 0 +OP4 E019E7 0 +OP4 E019E8 0 +OP4 E019E9 0 +OP4 E019EA 0 +OP4 E019EB 0 +OP4 E019EC 0 +OP4 E019ED 0 +OP4 E019EE 0 +OP4 E019EF 0 +OP4 E019F0 0 +OP4 E019F1 0 +OP4 E019F2 0 +OP4 E019F3 0 +OP4 E019F4 0 +OP4 E019F5 0 +OP4 E019F6 0 +OP4 E019F7 0 +OP4 E019F8 0 +OP4 E019F9 0 +OP4 E019FA 0 +OP4 E019FB 0 +OP4 E019FC 0 +OP4 E019FD 0 +OP4 E019FE 0 +OP4 E019FF 0 +OP4 E01A00 0 +OP4 E01A01 0 +OP4 E01A02 0 +OP4 E01A03 0 +OP4 E01A04 0 +OP4 E01A05 0 +OP4 E01A06 0 +OP4 E01A07 0 +OP4 E01A08 0 +OP4 E01A09 0 +OP4 E01A0A 0 +OP4 E01A0B 0 +OP4 E01A0C 0 +OP4 E01A0D 0 +OP4 E01A0E 0 +OP4 E01A0F 0 +OP4 E01A10 0 +OP4 E01A11 0 +OP4 E01A12 0 +OP4 E01A13 0 +OP4 E01A14 0 +OP4 E01A15 0 +OP4 E01A16 0 +OP4 E01A17 0 +OP4 E01A18 0 +OP4 E01A19 0 +OP4 E01A1A 0 +OP4 E01A1B 0 +OP4 E01A1C 0 +OP4 E01A1D 0 +OP4 E01A1E 0 +OP4 E01A1F 0 +OP4 E01A20 0 +OP4 E01A21 0 +OP4 E01A22 0 +OP4 E01A23 0 +OP4 E01A24 0 +OP4 E01A25 0 +OP4 E01A26 0 +OP4 E01A27 0 +OP4 E01A28 0 +OP4 E01A29 0 +OP4 E01A2A 0 +OP4 E01A2B 0 +OP4 E01A2C 0 +OP4 E01A2D 0 +OP4 E01A2E 0 +OP4 E01A2F 0 +OP4 E01A30 0 +OP4 E01A31 0 +OP4 E01A32 0 +OP4 E01A33 0 +OP4 E01A34 0 +OP4 E01A35 0 +OP4 E01A36 0 +OP4 E01A37 0 +OP4 E01A38 0 +OP4 E01A39 0 +OP4 E01A3A 0 +OP4 E01A3B 0 +OP4 E01A3C 0 +OP4 E01A3D 0 +OP4 E01A3E 0 +OP4 E01A3F 0 +OP4 E01A40 0 +OP4 E01A41 0 +OP4 E01A42 0 +OP4 E01A43 0 +OP4 E01A44 0 +OP4 E01A45 0 +OP4 E01A46 0 +OP4 E01A47 0 +OP4 E01A48 0 +OP4 E01A49 0 +OP4 E01A4A 0 +OP4 E01A4B 0 +OP4 E01A4C 0 +OP4 E01A4D 0 +OP4 E01A4E 0 +OP4 E01A4F 0 +OP4 E01A50 0 +OP4 E01A51 0 +OP4 E01A52 0 +OP4 E01A53 0 +OP4 E01A54 0 +OP4 E01A55 0 +OP4 E01A56 0 +OP4 E01A57 0 +OP4 E01A58 0 +OP4 E01A59 0 +OP4 E01A5A 0 +OP4 E01A5B 0 +OP4 E01A5C 0 +OP4 E01A5D 0 +OP4 E01A5E 0 +OP4 E01A5F 0 +OP4 E01A60 0 +OP4 E01A61 0 +OP4 E01A62 0 +OP4 E01A63 0 +OP4 E01A64 0 +OP4 E01A65 0 +OP4 E01A66 0 +OP4 E01A67 0 +OP4 E01A68 0 +OP4 E01A69 0 +OP4 E01A6A 0 +OP4 E01A6B 0 +OP4 E01A6C 0 +OP4 E01A6D 0 +OP4 E01A6E 0 +OP4 E01A6F 0 +OP4 E01A70 0 +OP4 E01A71 0 +OP4 E01A72 0 +OP4 E01A73 0 +OP4 E01A74 0 +OP4 E01A75 0 +OP4 E01A76 0 +OP4 E01A77 0 +OP4 E01A78 0 +OP4 E01A79 0 +OP4 E01A7A 0 +OP4 E01A7B 0 +OP4 E01A7C 0 +OP4 E01A7D 0 +OP4 E01A7E 0 +OP4 E01A7F 0 +OP4 E01A80 0 +OP4 E01A81 0 +OP4 E01A82 0 +OP4 E01A83 0 +OP4 E01A84 0 +OP4 E01A85 0 +OP4 E01A86 0 +OP4 E01A87 0 +OP4 E01A88 0 +OP4 E01A89 0 +OP4 E01A8A 0 +OP4 E01A8B 0 +OP4 E01A8C 0 +OP4 E01A8D 0 +OP4 E01A8E 0 +OP4 E01A8F 0 +OP4 E01A90 0 +OP4 E01A91 0 +OP4 E01A92 0 +OP4 E01A93 0 +OP4 E01A94 0 +OP4 E01A95 0 +OP4 E01A96 0 +OP4 E01A97 0 +OP4 E01A98 0 +OP4 E01A99 0 +OP4 E01A9A 0 +OP4 E01A9B 0 +OP4 E01A9C 0 +OP4 E01A9D 0 +OP4 E01A9E 0 +OP4 E01A9F 0 +OP4 E01AA0 0 +OP4 E01AA1 0 +OP4 E01AA2 0 +OP4 E01AA3 0 +OP4 E01AA4 0 +OP4 E01AA5 0 +OP4 E01AA6 0 +OP4 E01AA7 0 +OP4 E01AA8 0 +OP4 E01AA9 0 +OP4 E01AAA 0 +OP4 E01AAB 0 +OP4 E01AAC 0 +OP4 E01AAD 0 +OP4 E01AAE 0 +OP4 E01AAF 0 +OP4 E01AB0 0 +OP4 E01AB1 0 +OP4 E01AB2 0 +OP4 E01AB3 0 +OP4 E01AB4 0 +OP4 E01AB5 0 +OP4 E01AB6 0 +OP4 E01AB7 0 +OP4 E01AB8 0 +OP4 E01AB9 0 +OP4 E01ABA 0 +OP4 E01ABB 0 +OP4 E01ABC 0 +OP4 E01ABD 0 +OP4 E01ABE 0 +OP4 E01ABF 0 +OP4 E01AC0 0 +OP4 E01AC1 0 +OP4 E01AC2 0 +OP4 E01AC3 0 +OP4 E01AC4 0 +OP4 E01AC5 0 +OP4 E01AC6 0 +OP4 E01AC7 0 +OP4 E01AC8 0 +OP4 E01AC9 0 +OP4 E01ACA 0 +OP4 E01ACB 0 +OP4 E01ACC 0 +OP4 E01ACD 0 +OP4 E01ACE 0 +OP4 E01ACF 0 +OP4 E01AD0 0 +OP4 E01AD1 0 +OP4 E01AD2 0 +OP4 E01AD3 0 +OP4 E01AD4 0 +OP4 E01AD5 0 +OP4 E01AD6 0 +OP4 E01AD7 0 +OP4 E01AD8 0 +OP4 E01AD9 0 +OP4 E01ADA 0 +OP4 E01ADB 0 +OP4 E01ADC 0 +OP4 E01ADD 0 +OP4 E01ADE 0 +OP4 E01ADF 0 +OP4 E01AE0 0 +OP4 E01AE1 0 +OP4 E01AE2 0 +OP4 E01AE3 0 +OP4 E01AE4 0 +OP4 E01AE5 0 +OP4 E01AE6 0 +OP4 E01AE7 0 +OP4 E01AE8 0 +OP4 E01AE9 0 +OP4 E01AEA 0 +OP4 E01AEB 0 +OP4 E01AEC 0 +OP4 E01AED 0 +OP4 E01AEE 0 +OP4 E01AEF 0 +OP4 E01AF0 0 +OP4 E01AF1 0 +OP4 E01AF2 0 +OP4 E01AF3 0 +OP4 E01AF4 0 +OP4 E01AF5 0 +OP4 E01AF6 0 +OP4 E01AF7 0 +OP4 E01AF8 0 +OP4 E01AF9 0 +OP4 E01AFA 0 +OP4 E01AFB 0 +OP4 E01AFC 0 +OP4 E01AFD 0 +OP4 E01AFE 0 +OP4 E01AFF 0 +OP4 E01B00 0 +OP4 E01B01 0 +OP4 E01B02 0 +OP4 E01B03 0 +OP4 E01B04 0 +OP4 E01B05 0 +OP4 E01B06 0 +OP4 E01B07 0 +OP4 E01B08 0 +OP4 E01B09 0 +OP4 E01B0A 0 +OP4 E01B0B 0 +OP4 E01B0C 0 +OP4 E01B0D 0 +OP4 E01B0E 0 +OP4 E01B0F 0 +OP4 E01B10 0 +OP4 E01B11 0 +OP4 E01B12 0 +OP4 E01B13 0 +OP4 E01B14 0 +OP4 E01B15 0 +OP4 E01B16 0 +OP4 E01B17 0 +OP4 E01B18 0 +OP4 E01B19 0 +OP4 E01B1A 0 +OP4 E01B1B 0 +OP4 E01B1C 0 +OP4 E01B1D 0 +OP4 E01B1E 0 +OP4 E01B1F 0 +OP4 E01B20 0 +OP4 E01B21 0 +OP4 E01B22 0 +OP4 E01B23 0 +OP4 E01B24 0 +OP4 E01B25 0 +OP4 E01B26 0 +OP4 E01B27 0 +OP4 E01B28 0 +OP4 E01B29 0 +OP4 E01B2A 0 +OP4 E01B2B 0 +OP4 E01B2C 0 +OP4 E01B2D 0 +OP4 E01B2E 0 +OP4 E01B2F 0 +OP4 E01B30 0 +OP4 E01B31 0 +OP4 E01B32 0 +OP4 E01B33 0 +OP4 E01B34 0 +OP4 E01B35 0 +OP4 E01B36 0 +OP4 E01B37 0 +OP4 E01B38 0 +OP4 E01B39 0 +OP4 E01B3A 0 +OP4 E01B3B 0 +OP4 E01B3C 0 +OP4 E01B3D 0 +OP4 E01B3E 0 +OP4 E01B3F 0 +OP4 E01B40 0 +OP4 E01B41 0 +OP4 E01B42 0 +OP4 E01B43 0 +OP4 E01B44 0 +OP4 E01B45 0 +OP4 E01B46 0 +OP4 E01B47 0 +OP4 E01B48 0 +OP4 E01B49 0 +OP4 E01B4A 0 +OP4 E01B4B 0 +OP4 E01B4C 0 +OP4 E01B4D 0 +OP4 E01B4E 0 +OP4 E01B4F 0 +OP4 E01B50 0 +OP4 E01B51 0 +OP4 E01B52 0 +OP4 E01B53 0 +OP4 E01B54 0 +OP4 E01B55 0 +OP4 E01B56 0 +OP4 E01B57 0 +OP4 E01B58 0 +OP4 E01B59 0 +OP4 E01B5A 0 +OP4 E01B5B 0 +OP4 E01B5C 0 +OP4 E01B5D 0 +OP4 E01B5E 0 +OP4 E01B5F 0 +OP4 E01B60 0 +OP4 E01B61 0 +OP4 E01B62 0 +OP4 E01B63 0 +OP4 E01B64 0 +OP4 E01B65 0 +OP4 E01B66 0 +OP4 E01B67 0 +OP4 E01B68 0 +OP4 E01B69 0 +OP4 E01B6A 0 +OP4 E01B6B 0 +OP4 E01B6C 0 +OP4 E01B6D 0 +OP4 E01B6E 0 +OP4 E01B6F 0 +OP4 E01B70 0 +OP4 E01B71 0 +OP4 E01B72 0 +OP4 E01B73 0 +OP4 E01B74 0 +OP4 E01B75 0 +OP4 E01B76 0 +OP4 E01B77 0 +OP4 E01B78 0 +OP4 E01B79 0 +OP4 E01B7A 0 +OP4 E01B7B 0 +OP4 E01B7C 0 +OP4 E01B7D 0 +OP4 E01B7E 0 +OP4 E01B7F 0 +OP4 E01B80 0 +OP4 E01B81 0 +OP4 E01B82 0 +OP4 E01B83 0 +OP4 E01B84 0 +OP4 E01B85 0 +OP4 E01B86 0 +OP4 E01B87 0 +OP4 E01B88 0 +OP4 E01B89 0 +OP4 E01B8A 0 +OP4 E01B8B 0 +OP4 E01B8C 0 +OP4 E01B8D 0 +OP4 E01B8E 0 +OP4 E01B8F 0 +OP4 E01B90 0 +OP4 E01B91 0 +OP4 E01B92 0 +OP4 E01B93 0 +OP4 E01B94 0 +OP4 E01B95 0 +OP4 E01B96 0 +OP4 E01B97 0 +OP4 E01B98 0 +OP4 E01B99 0 +OP4 E01B9A 0 +OP4 E01B9B 0 +OP4 E01B9C 0 +OP4 E01B9D 0 +OP4 E01B9E 0 +OP4 E01B9F 0 +OP4 E01BA0 0 +OP4 E01BA1 0 +OP4 E01BA2 0 +OP4 E01BA3 0 +OP4 E01BA4 0 +OP4 E01BA5 0 +OP4 E01BA6 0 +OP4 E01BA7 0 +OP4 E01BA8 0 +OP4 E01BA9 0 +OP4 E01BAA 0 +OP4 E01BAB 0 +OP4 E01BAC 0 +OP4 E01BAD 0 +OP4 E01BAE 0 +OP4 E01BAF 0 +OP4 E01BB0 0 +OP4 E01BB1 0 +OP4 E01BB2 0 +OP4 E01BB3 0 +OP4 E01BB4 0 +OP4 E01BB5 0 +OP4 E01BB6 0 +OP4 E01BB7 0 +OP4 E01BB8 0 +OP4 E01BB9 0 +OP4 E01BBA 0 +OP4 E01BBB 0 +OP4 E01BBC 0 +OP4 E01BBD 0 +OP4 E01BBE 0 +OP4 E01BBF 0 +OP4 E01BC0 0 +OP4 E01BC1 0 +OP4 E01BC2 0 +OP4 E01BC3 0 +OP4 E01BC4 0 +OP4 E01BC5 0 +OP4 E01BC6 0 +OP4 E01BC7 0 +OP4 E01BC8 0 +OP4 E01BC9 0 +OP4 E01BCA 0 +OP4 E01BCB 0 +OP4 E01BCC 0 +OP4 E01BCD 0 +OP4 E01BCE 0 +OP4 E01BCF 0 +OP4 E01BD0 0 +OP4 E01BD1 0 +OP4 E01BD2 0 +OP4 E01BD3 0 +OP4 E01BD4 0 +OP4 E01BD5 0 +OP4 E01BD6 0 +OP4 E01BD7 0 +OP4 E01BD8 0 +OP4 E01BD9 0 +OP4 E01BDA 0 +OP4 E01BDB 0 +OP4 E01BDC 0 +OP4 E01BDD 0 +OP4 E01BDE 0 +OP4 E01BDF 0 +OP4 E01BE0 0 +OP4 E01BE1 0 +OP4 E01BE2 0 +OP4 E01BE3 0 +OP4 E01BE4 0 +OP4 E01BE5 0 +OP4 E01BE6 0 +OP4 E01BE7 0 +OP4 E01BE8 0 +OP4 E01BE9 0 +OP4 E01BEA 0 +OP4 E01BEB 0 +OP4 E01BEC 0 +OP4 E01BED 0 +OP4 E01BEE 0 +OP4 E01BEF 0 +OP4 E01BF0 0 +OP4 E01BF1 0 +OP4 E01BF2 0 +OP4 E01BF3 0 +OP4 E01BF4 0 +OP4 E01BF5 0 +OP4 E01BF6 0 +OP4 E01BF7 0 +OP4 E01BF8 0 +OP4 E01BF9 0 +OP4 E01BFA 0 +OP4 E01BFB 0 +OP4 E01BFC 0 +OP4 E01BFD 0 +OP4 E01BFE 0 +OP4 E01BFF 0 +OP4 E01C00 0 +OP4 E01C01 0 +OP4 E01C02 0 +OP4 E01C03 0 +OP4 E01C04 0 +OP4 E01C05 0 +OP4 E01C06 0 +OP4 E01C07 0 +OP4 E01C08 0 +OP4 E01C09 0 +OP4 E01C0A 0 +OP4 E01C0B 0 +OP4 E01C0C 0 +OP4 E01C0D 0 +OP4 E01C0E 0 +OP4 E01C0F 0 +OP4 E01C10 0 +OP4 E01C11 0 +OP4 E01C12 0 +OP4 E01C13 0 +OP4 E01C14 0 +OP4 E01C15 0 +OP4 E01C16 0 +OP4 E01C17 0 +OP4 E01C18 0 +OP4 E01C19 0 +OP4 E01C1A 0 +OP4 E01C1B 0 +OP4 E01C1C 0 +OP4 E01C1D 0 +OP4 E01C1E 0 +OP4 E01C1F 0 +OP4 E01C20 0 +OP4 E01C21 0 +OP4 E01C22 0 +OP4 E01C23 0 +OP4 E01C24 0 +OP4 E01C25 0 +OP4 E01C26 0 +OP4 E01C27 0 +OP4 E01C28 0 +OP4 E01C29 0 +OP4 E01C2A 0 +OP4 E01C2B 0 +OP4 E01C2C 0 +OP4 E01C2D 0 +OP4 E01C2E 0 +OP4 E01C2F 0 +OP4 E01C30 0 +OP4 E01C31 0 +OP4 E01C32 0 +OP4 E01C33 0 +OP4 E01C34 0 +OP4 E01C35 0 +OP4 E01C36 0 +OP4 E01C37 0 +OP4 E01C38 0 +OP4 E01C39 0 +OP4 E01C3A 0 +OP4 E01C3B 0 +OP4 E01C3C 0 +OP4 E01C3D 0 +OP4 E01C3E 0 +OP4 E01C3F 0 +OP4 E01C40 0 +OP4 E01C41 0 +OP4 E01C42 0 +OP4 E01C43 0 +OP4 E01C44 0 +OP4 E01C45 0 +OP4 E01C46 0 +OP4 E01C47 0 +OP4 E01C48 0 +OP4 E01C49 0 +OP4 E01C4A 0 +OP4 E01C4B 0 +OP4 E01C4C 0 +OP4 E01C4D 0 +OP4 E01C4E 0 +OP4 E01C4F 0 +OP4 E01C50 0 +OP4 E01C51 0 +OP4 E01C52 0 +OP4 E01C53 0 +OP4 E01C54 0 +OP4 E01C55 0 +OP4 E01C56 0 +OP4 E01C57 0 +OP4 E01C58 0 +OP4 E01C59 0 +OP4 E01C5A 0 +OP4 E01C5B 0 +OP4 E01C5C 0 +OP4 E01C5D 0 +OP4 E01C5E 0 +OP4 E01C5F 0 +OP4 E01C60 0 +OP4 E01C61 0 +OP4 E01C62 0 +OP4 E01C63 0 +OP4 E01C64 0 +OP4 E01C65 0 +OP4 E01C66 0 +OP4 E01C67 0 +OP4 E01C68 0 +OP4 E01C69 0 +OP4 E01C6A 0 +OP4 E01C6B 0 +OP4 E01C6C 0 +OP4 E01C6D 0 +OP4 E01C6E 0 +OP4 E01C6F 0 +OP4 E01C70 0 +OP4 E01C71 0 +OP4 E01C72 0 +OP4 E01C73 0 +OP4 E01C74 0 +OP4 E01C75 0 +OP4 E01C76 0 +OP4 E01C77 0 +OP4 E01C78 0 +OP4 E01C79 0 +OP4 E01C7A 0 +OP4 E01C7B 0 +OP4 E01C7C 0 +OP4 E01C7D 0 +OP4 E01C7E 0 +OP4 E01C7F 0 +OP4 E01C80 0 +OP4 E01C81 0 +OP4 E01C82 0 +OP4 E01C83 0 +OP4 E01C84 0 +OP4 E01C85 0 +OP4 E01C86 0 +OP4 E01C87 0 +OP4 E01C88 0 +OP4 E01C89 0 +OP4 E01C8A 0 +OP4 E01C8B 0 +OP4 E01C8C 0 +OP4 E01C8D 0 +OP4 E01C8E 0 +OP4 E01C8F 0 +OP4 E01C90 0 +OP4 E01C91 0 +OP4 E01C92 0 +OP4 E01C93 0 +OP4 E01C94 0 +OP4 E01C95 0 +OP4 E01C96 0 +OP4 E01C97 0 +OP4 E01C98 0 +OP4 E01C99 0 +OP4 E01C9A 0 +OP4 E01C9B 0 +OP4 E01C9C 0 +OP4 E01C9D 0 +OP4 E01C9E 0 +OP4 E01C9F 0 +OP4 E01CA0 0 +OP4 E01CA1 0 +OP4 E01CA2 0 +OP4 E01CA3 0 +OP4 E01CA4 0 +OP4 E01CA5 0 +OP4 E01CA6 0 +OP4 E01CA7 0 +OP4 E01CA8 0 +OP4 E01CA9 0 +OP4 E01CAA 0 +OP4 E01CAB 0 +OP4 E01CAC 0 +OP4 E01CAD 0 +OP4 E01CAE 0 +OP4 E01CAF 0 +OP4 E01CB0 0 +OP4 E01CB1 0 +OP4 E01CB2 0 +OP4 E01CB3 0 +OP4 E01CB4 0 +OP4 E01CB5 0 +OP4 E01CB6 0 +OP4 E01CB7 0 +OP4 E01CB8 0 +OP4 E01CB9 0 +OP4 E01CBA 0 +OP4 E01CBB 0 +OP4 E01CBC 0 +OP4 E01CBD 0 +OP4 E01CBE 0 +OP4 E01CBF 0 +OP4 E01CC0 0 +OP4 E01CC1 0 +OP4 E01CC2 0 +OP4 E01CC3 0 +OP4 E01CC4 0 +OP4 E01CC5 0 +OP4 E01CC6 0 +OP4 E01CC7 0 +OP4 E01CC8 0 +OP4 E01CC9 0 +OP4 E01CCA 0 +OP4 E01CCB 0 +OP4 E01CCC 0 +OP4 E01CCD 0 +OP4 E01CCE 0 +OP4 E01CCF 0 +OP4 E01CD0 0 +OP4 E01CD1 0 +OP4 E01CD2 0 +OP4 E01CD3 0 +OP4 E01CD4 0 +OP4 E01CD5 0 +OP4 E01CD6 0 +OP4 E01CD7 0 +OP4 E01CD8 0 +OP4 E01CD9 0 +OP4 E01CDA 0 +OP4 E01CDB 0 +OP4 E01CDC 0 +OP4 E01CDD 0 +OP4 E01CDE 0 +OP4 E01CDF 0 +OP4 E01CE0 0 +OP4 E01CE1 0 +OP4 E01CE2 0 +OP4 E01CE3 0 +OP4 E01CE4 0 +OP4 E01CE5 0 +OP4 E01CE6 0 +OP4 E01CE7 0 +OP4 E01CE8 0 +OP4 E01CE9 0 +OP4 E01CEA 0 +OP4 E01CEB 0 +OP4 E01CEC 0 +OP4 E01CED 0 +OP4 E01CEE 0 +OP4 E01CEF 0 +OP4 E01CF0 0 +OP4 E01CF1 0 +OP4 E01CF2 0 +OP4 E01CF3 0 +OP4 E01CF4 0 +OP4 E01CF5 0 +OP4 E01CF6 0 +OP4 E01CF7 0 +OP4 E01CF8 0 +OP4 E01CF9 0 +OP4 E01CFA 0 +OP4 E01CFB 0 +OP4 E01CFC 0 +OP4 E01CFD 0 +OP4 E01CFE 0 +OP4 E01CFF 0 +OP4 E01D00 0 +OP4 E01D01 0 +OP4 E01D02 0 +OP4 E01D03 0 +OP4 E01D04 0 +OP4 E01D05 0 +OP4 E01D06 0 +OP4 E01D07 0 +OP4 E01D08 0 +OP4 E01D09 0 +OP4 E01D0A 0 +OP4 E01D0B 0 +OP4 E01D0C 0 +OP4 E01D0D 0 +OP4 E01D0E 0 +OP4 E01D0F 0 +OP4 E01D10 0 +OP4 E01D11 0 +OP4 E01D12 0 +OP4 E01D13 0 +OP4 E01D14 0 +OP4 E01D15 0 +OP4 E01D16 0 +OP4 E01D17 0 +OP4 E01D18 0 +OP4 E01D19 0 +OP4 E01D1A 0 +OP4 E01D1B 0 +OP4 E01D1C 0 +OP4 E01D1D 0 +OP4 E01D1E 0 +OP4 E01D1F 0 +OP4 E01D20 0 +OP4 E01D21 0 +OP4 E01D22 0 +OP4 E01D23 0 +OP4 E01D24 0 +OP4 E01D25 0 +OP4 E01D26 0 +OP4 E01D27 0 +OP4 E01D28 0 +OP4 E01D29 0 +OP4 E01D2A 0 +OP4 E01D2B 0 +OP4 E01D2C 0 +OP4 E01D2D 0 +OP4 E01D2E 0 +OP4 E01D2F 0 +OP4 E01D30 0 +OP4 E01D31 0 +OP4 E01D32 0 +OP4 E01D33 0 +OP4 E01D34 0 +OP4 E01D35 0 +OP4 E01D36 0 +OP4 E01D37 0 +OP4 E01D38 0 +OP4 E01D39 0 +OP4 E01D3A 0 +OP4 E01D3B 0 +OP4 E01D3C 0 +OP4 E01D3D 0 +OP4 E01D3E 0 +OP4 E01D3F 0 +OP4 E01D40 0 +OP4 E01D41 0 +OP4 E01D42 0 +OP4 E01D43 0 +OP4 E01D44 0 +OP4 E01D45 0 +OP4 E01D46 0 +OP4 E01D47 0 +OP4 E01D48 0 +OP4 E01D49 0 +OP4 E01D4A 0 +OP4 E01D4B 0 +OP4 E01D4C 0 +OP4 E01D4D 0 +OP4 E01D4E 0 +OP4 E01D4F 0 +OP4 E01D50 0 +OP4 E01D51 0 +OP4 E01D52 0 +OP4 E01D53 0 +OP4 E01D54 0 +OP4 E01D55 0 +OP4 E01D56 0 +OP4 E01D57 0 +OP4 E01D58 0 +OP4 E01D59 0 +OP4 E01D5A 0 +OP4 E01D5B 0 +OP4 E01D5C 0 +OP4 E01D5D 0 +OP4 E01D5E 0 +OP4 E01D5F 0 +OP4 E01D60 0 +OP4 E01D61 0 +OP4 E01D62 0 +OP4 E01D63 0 +OP4 E01D64 0 +OP4 E01D65 0 +OP4 E01D66 0 +OP4 E01D67 0 +OP4 E01D68 0 +OP4 E01D69 0 +OP4 E01D6A 0 +OP4 E01D6B 0 +OP4 E01D6C 0 +OP4 E01D6D 0 +OP4 E01D6E 0 +OP4 E01D6F 0 +OP4 E01D70 0 +OP4 E01D71 0 +OP4 E01D72 0 +OP4 E01D73 0 +OP4 E01D74 0 +OP4 E01D75 0 +OP4 E01D76 0 +OP4 E01D77 0 +OP4 E01D78 0 +OP4 E01D79 0 +OP4 E01D7A 0 +OP4 E01D7B 0 +OP4 E01D7C 0 +OP4 E01D7D 0 +OP4 E01D7E 0 +OP4 E01D7F 0 +OP4 E01D80 0 +OP4 E01D81 0 +OP4 E01D82 0 +OP4 E01D83 0 +OP4 E01D84 0 +OP4 E01D85 0 +OP4 E01D86 0 +OP4 E01D87 0 +OP4 E01D88 0 +OP4 E01D89 0 +OP4 E01D8A 0 +OP4 E01D8B 0 +OP4 E01D8C 0 +OP4 E01D8D 0 +OP4 E01D8E 0 +OP4 E01D8F 0 +OP4 E01D90 0 +OP4 E01D91 0 +OP4 E01D92 0 +OP4 E01D93 0 +OP4 E01D94 0 +OP4 E01D95 0 +OP4 E01D96 0 +OP4 E01D97 0 +OP4 E01D98 0 +OP4 E01D99 0 +OP4 E01D9A 0 +OP4 E01D9B 0 +OP4 E01D9C 0 +OP4 E01D9D 0 +OP4 E01D9E 0 +OP4 E01D9F 0 +OP4 E01DA0 0 +OP4 E01DA1 0 +OP4 E01DA2 0 +OP4 E01DA3 0 +OP4 E01DA4 0 +OP4 E01DA5 0 +OP4 E01DA6 0 +OP4 E01DA7 0 +OP4 E01DA8 0 +OP4 E01DA9 0 +OP4 E01DAA 0 +OP4 E01DAB 0 +OP4 E01DAC 0 +OP4 E01DAD 0 +OP4 E01DAE 0 +OP4 E01DAF 0 +OP4 E01DB0 0 +OP4 E01DB1 0 +OP4 E01DB2 0 +OP4 E01DB3 0 +OP4 E01DB4 0 +OP4 E01DB5 0 +OP4 E01DB6 0 +OP4 E01DB7 0 +OP4 E01DB8 0 +OP4 E01DB9 0 +OP4 E01DBA 0 +OP4 E01DBB 0 +OP4 E01DBC 0 +OP4 E01DBD 0 +OP4 E01DBE 0 +OP4 E01DBF 0 +OP4 E01DC0 0 +OP4 E01DC1 0 +OP4 E01DC2 0 +OP4 E01DC3 0 +OP4 E01DC4 0 +OP4 E01DC5 0 +OP4 E01DC6 0 +OP4 E01DC7 0 +OP4 E01DC8 0 +OP4 E01DC9 0 +OP4 E01DCA 0 +OP4 E01DCB 0 +OP4 E01DCC 0 +OP4 E01DCD 0 +OP4 E01DCE 0 +OP4 E01DCF 0 +OP4 E01DD0 0 +OP4 E01DD1 0 +OP4 E01DD2 0 +OP4 E01DD3 0 +OP4 E01DD4 0 +OP4 E01DD5 0 +OP4 E01DD6 0 +OP4 E01DD7 0 +OP4 E01DD8 0 +OP4 E01DD9 0 +OP4 E01DDA 0 +OP4 E01DDB 0 +OP4 E01DDC 0 +OP4 E01DDD 0 +OP4 E01DDE 0 +OP4 E01DDF 0 +OP4 E01DE0 0 +OP4 E01DE1 0 +OP4 E01DE2 0 +OP4 E01DE3 0 +OP4 E01DE4 0 +OP4 E01DE5 0 +OP4 E01DE6 0 +OP4 E01DE7 0 +OP4 E01DE8 0 +OP4 E01DE9 0 +OP4 E01DEA 0 +OP4 E01DEB 0 +OP4 E01DEC 0 +OP4 E01DED 0 +OP4 E01DEE 0 +OP4 E01DEF 0 +OP4 E01DF0 0 +OP4 E01DF1 0 +OP4 E01DF2 0 +OP4 E01DF3 0 +OP4 E01DF4 0 +OP4 E01DF5 0 +OP4 E01DF6 0 +OP4 E01DF7 0 +OP4 E01DF8 0 +OP4 E01DF9 0 +OP4 E01DFA 0 +OP4 E01DFB 0 +OP4 E01DFC 0 +OP4 E01DFD 0 +OP4 E01DFE 0 +OP4 E01DFF 0 +OP4 E01E00 0 +OP4 E01E01 0 +OP4 E01E02 0 +OP4 E01E03 0 +OP4 E01E04 0 +OP4 E01E05 0 +OP4 E01E06 0 +OP4 E01E07 0 +OP4 E01E08 0 +OP4 E01E09 0 +OP4 E01E0A 0 +OP4 E01E0B 0 +OP4 E01E0C 0 +OP4 E01E0D 0 +OP4 E01E0E 0 +OP4 E01E0F 0 +OP4 E01E10 0 +OP4 E01E11 0 +OP4 E01E12 0 +OP4 E01E13 0 +OP4 E01E14 0 +OP4 E01E15 0 +OP4 E01E16 0 +OP4 E01E17 0 +OP4 E01E18 0 +OP4 E01E19 0 +OP4 E01E1A 0 +OP4 E01E1B 0 +OP4 E01E1C 0 +OP4 E01E1D 0 +OP4 E01E1E 0 +OP4 E01E1F 0 +OP4 E01E20 0 +OP4 E01E21 0 +OP4 E01E22 0 +OP4 E01E23 0 +OP4 E01E24 0 +OP4 E01E25 0 +OP4 E01E26 0 +OP4 E01E27 0 +OP4 E01E28 0 +OP4 E01E29 0 +OP4 E01E2A 0 +OP4 E01E2B 0 +OP4 E01E2C 0 +OP4 E01E2D 0 +OP4 E01E2E 0 +OP4 E01E2F 0 +OP4 E01E30 0 +OP4 E01E31 0 +OP4 E01E32 0 +OP4 E01E33 0 +OP4 E01E34 0 +OP4 E01E35 0 +OP4 E01E36 0 +OP4 E01E37 0 +OP4 E01E38 0 +OP4 E01E39 0 +OP4 E01E3A 0 +OP4 E01E3B 0 +OP4 E01E3C 0 +OP4 E01E3D 0 +OP4 E01E3E 0 +OP4 E01E3F 0 +OP4 E01E40 0 +OP4 E01E41 0 +OP4 E01E42 0 +OP4 E01E43 0 +OP4 E01E44 0 +OP4 E01E45 0 +OP4 E01E46 0 +OP4 E01E47 0 +OP4 E01E48 0 +OP4 E01E49 0 +OP4 E01E4A 0 +OP4 E01E4B 0 +OP4 E01E4C 0 +OP4 E01E4D 0 +OP4 E01E4E 0 +OP4 E01E4F 0 +OP4 E01E50 0 +OP4 E01E51 0 +OP4 E01E52 0 +OP4 E01E53 0 +OP4 E01E54 0 +OP4 E01E55 0 +OP4 E01E56 0 +OP4 E01E57 0 +OP4 E01E58 0 +OP4 E01E59 0 +OP4 E01E5A 0 +OP4 E01E5B 0 +OP4 E01E5C 0 +OP4 E01E5D 0 +OP4 E01E5E 0 +OP4 E01E5F 0 +OP4 E01E60 0 +OP4 E01E61 0 +OP4 E01E62 0 +OP4 E01E63 0 +OP4 E01E64 0 +OP4 E01E65 0 +OP4 E01E66 0 +OP4 E01E67 0 +OP4 E01E68 0 +OP4 E01E69 0 +OP4 E01E6A 0 +OP4 E01E6B 0 +OP4 E01E6C 0 +OP4 E01E6D 0 +OP4 E01E6E 0 +OP4 E01E6F 0 +OP4 E01E70 0 +OP4 E01E71 0 +OP4 E01E72 0 +OP4 E01E73 0 +OP4 E01E74 0 +OP4 E01E75 0 +OP4 E01E76 0 +OP4 E01E77 0 +OP4 E01E78 0 +OP4 E01E79 0 +OP4 E01E7A 0 +OP4 E01E7B 0 +OP4 E01E7C 0 +OP4 E01E7D 0 +OP4 E01E7E 0 +OP4 E01E7F 0 +OP4 E01E80 0 +OP4 E01E81 0 +OP4 E01E82 0 +OP4 E01E83 0 +OP4 E01E84 0 +OP4 E01E85 0 +OP4 E01E86 0 +OP4 E01E87 0 +OP4 E01E88 0 +OP4 E01E89 0 +OP4 E01E8A 0 +OP4 E01E8B 0 +OP4 E01E8C 0 +OP4 E01E8D 0 +OP4 E01E8E 0 +OP4 E01E8F 0 +OP4 E01E90 0 +OP4 E01E91 0 +OP4 E01E92 0 +OP4 E01E93 0 +OP4 E01E94 0 +OP4 E01E95 0 +OP4 E01E96 0 +OP4 E01E97 0 +OP4 E01E98 0 +OP4 E01E99 0 +OP4 E01E9A 0 +OP4 E01E9B 0 +OP4 E01E9C 0 +OP4 E01E9D 0 +OP4 E01E9E 0 +OP4 E01E9F 0 +OP4 E01EA0 0 +OP4 E01EA1 0 +OP4 E01EA2 0 +OP4 E01EA3 0 +OP4 E01EA4 0 +OP4 E01EA5 0 +OP4 E01EA6 0 +OP4 E01EA7 0 +OP4 E01EA8 0 +OP4 E01EA9 0 +OP4 E01EAA 0 +OP4 E01EAB 0 +OP4 E01EAC 0 +OP4 E01EAD 0 +OP4 E01EAE 0 +OP4 E01EAF 0 +OP4 E01EB0 0 +OP4 E01EB1 0 +OP4 E01EB2 0 +OP4 E01EB3 0 +OP4 E01EB4 0 +OP4 E01EB5 0 +OP4 E01EB6 0 +OP4 E01EB7 0 +OP4 E01EB8 0 +OP4 E01EB9 0 +OP4 E01EBA 0 +OP4 E01EBB 0 +OP4 E01EBC 0 +OP4 E01EBD 0 +OP4 E01EBE 0 +OP4 E01EBF 0 +OP4 E01EC0 0 +OP4 E01EC1 0 +OP4 E01EC2 0 +OP4 E01EC3 0 +OP4 E01EC4 0 +OP4 E01EC5 0 +OP4 E01EC6 0 +OP4 E01EC7 0 +OP4 E01EC8 0 +OP4 E01EC9 0 +OP4 E01ECA 0 +OP4 E01ECB 0 +OP4 E01ECC 0 +OP4 E01ECD 0 +OP4 E01ECE 0 +OP4 E01ECF 0 +OP4 E01ED0 0 +OP4 E01ED1 0 +OP4 E01ED2 0 +OP4 E01ED3 0 +OP4 E01ED4 0 +OP4 E01ED5 0 +OP4 E01ED6 0 +OP4 E01ED7 0 +OP4 E01ED8 0 +OP4 E01ED9 0 +OP4 E01EDA 0 +OP4 E01EDB 0 +OP4 E01EDC 0 +OP4 E01EDD 0 +OP4 E01EDE 0 +OP4 E01EDF 0 +OP4 E01EE0 0 +OP4 E01EE1 0 +OP4 E01EE2 0 +OP4 E01EE3 0 +OP4 E01EE4 0 +OP4 E01EE5 0 +OP4 E01EE6 0 +OP4 E01EE7 0 +OP4 E01EE8 0 +OP4 E01EE9 0 +OP4 E01EEA 0 +OP4 E01EEB 0 +OP4 E01EEC 0 +OP4 E01EED 0 +OP4 E01EEE 0 +OP4 E01EEF 0 +OP4 E01EF0 0 +OP4 E01EF1 0 +OP4 E01EF2 0 +OP4 E01EF3 0 +OP4 E01EF4 0 +OP4 E01EF5 0 +OP4 E01EF6 0 +OP4 E01EF7 0 +OP4 E01EF8 0 +OP4 E01EF9 0 +OP4 E01EFA 0 +OP4 E01EFB 0 +OP4 E01EFC 0 +OP4 E01EFD 0 +OP4 E01EFE 0 +OP4 E01EFF 0 +OP4 E01F00 0 +OP4 E01F01 0 +OP4 E01F02 0 +OP4 E01F03 0 +OP4 E01F04 0 +OP4 E01F05 0 +OP4 E01F06 0 +OP4 E01F07 0 +OP4 E01F08 0 +OP4 E01F09 0 +OP4 E01F0A 0 +OP4 E01F0B 0 +OP4 E01F0C 0 +OP4 E01F0D 0 +OP4 E01F0E 0 +OP4 E01F0F 0 +OP4 E01F10 0 +OP4 E01F11 0 +OP4 E01F12 0 +OP4 E01F13 0 +OP4 E01F14 0 +OP4 E01F15 0 +OP4 E01F16 0 +OP4 E01F17 0 +OP4 E01F18 0 +OP4 E01F19 0 +OP4 E01F1A 0 +OP4 E01F1B 0 +OP4 E01F1C 0 +OP4 E01F1D 0 +OP4 E01F1E 0 +OP4 E01F1F 0 +OP4 E01F20 0 +OP4 E01F21 0 +OP4 E01F22 0 +OP4 E01F23 0 +OP4 E01F24 0 +OP4 E01F25 0 +OP4 E01F26 0 +OP4 E01F27 0 +OP4 E01F28 0 +OP4 E01F29 0 +OP4 E01F2A 0 +OP4 E01F2B 0 +OP4 E01F2C 0 +OP4 E01F2D 0 +OP4 E01F2E 0 +OP4 E01F2F 0 +OP4 E01F30 0 +OP4 E01F31 0 +OP4 E01F32 0 +OP4 E01F33 0 +OP4 E01F34 0 +OP4 E01F35 0 +OP4 E01F36 0 +OP4 E01F37 0 +OP4 E01F38 0 +OP4 E01F39 0 +OP4 E01F3A 0 +OP4 E01F3B 0 +OP4 E01F3C 0 +OP4 E01F3D 0 +OP4 E01F3E 0 +OP4 E01F3F 0 +OP4 E01F40 0 +OP4 E01F41 0 +OP4 E01F42 0 +OP4 E01F43 0 +OP4 E01F44 0 +OP4 E01F45 0 +OP4 E01F46 0 +OP4 E01F47 0 +OP4 E01F48 0 +OP4 E01F49 0 +OP4 E01F4A 0 +OP4 E01F4B 0 +OP4 E01F4C 0 +OP4 E01F4D 0 +OP4 E01F4E 0 +OP4 E01F4F 0 +OP4 E01F50 0 +OP4 E01F51 0 +OP4 E01F52 0 +OP4 E01F53 0 +OP4 E01F54 0 +OP4 E01F55 0 +OP4 E01F56 0 +OP4 E01F57 0 +OP4 E01F58 0 +OP4 E01F59 0 +OP4 E01F5A 0 +OP4 E01F5B 0 +OP4 E01F5C 0 +OP4 E01F5D 0 +OP4 E01F5E 0 +OP4 E01F5F 0 +OP4 E01F60 0 +OP4 E01F61 0 +OP4 E01F62 0 +OP4 E01F63 0 +OP4 E01F64 0 +OP4 E01F65 0 +OP4 E01F66 0 +OP4 E01F67 0 +OP4 E01F68 0 +OP4 E01F69 0 +OP4 E01F6A 0 +OP4 E01F6B 0 +OP4 E01F6C 0 +OP4 E01F6D 0 +OP4 E01F6E 0 +OP4 E01F6F 0 +OP4 E01F70 0 +OP4 E01F71 0 +OP4 E01F72 0 +OP4 E01F73 0 +OP4 E01F74 0 +OP4 E01F75 0 +OP4 E01F76 0 +OP4 E01F77 0 +OP4 E01F78 0 +OP4 E01F79 0 +OP4 E01F7A 0 +OP4 E01F7B 0 +OP4 E01F7C 0 +OP4 E01F7D 0 +OP4 E01F7E 0 +OP4 E01F7F 0 +OP4 E01F80 0 +OP4 E01F81 0 +OP4 E01F82 0 +OP4 E01F83 0 +OP4 E01F84 0 +OP4 E01F85 0 +OP4 E01F86 0 +OP4 E01F87 0 +OP4 E01F88 0 +OP4 E01F89 0 +OP4 E01F8A 0 +OP4 E01F8B 0 +OP4 E01F8C 0 +OP4 E01F8D 0 +OP4 E01F8E 0 +OP4 E01F8F 0 +OP4 E01F90 0 +OP4 E01F91 0 +OP4 E01F92 0 +OP4 E01F93 0 +OP4 E01F94 0 +OP4 E01F95 0 +OP4 E01F96 0 +OP4 E01F97 0 +OP4 E01F98 0 +OP4 E01F99 0 +OP4 E01F9A 0 +OP4 E01F9B 0 +OP4 E01F9C 0 +OP4 E01F9D 0 +OP4 E01F9E 0 +OP4 E01F9F 0 +OP4 E01FA0 0 +OP4 E01FA1 0 +OP4 E01FA2 0 +OP4 E01FA3 0 +OP4 E01FA4 0 +OP4 E01FA5 0 +OP4 E01FA6 0 +OP4 E01FA7 0 +OP4 E01FA8 0 +OP4 E01FA9 0 +OP4 E01FAA 0 +OP4 E01FAB 0 +OP4 E01FAC 0 +OP4 E01FAD 0 +OP4 E01FAE 0 +OP4 E01FAF 0 +OP4 E01FB0 0 +OP4 E01FB1 0 +OP4 E01FB2 0 +OP4 E01FB3 0 +OP4 E01FB4 0 +OP4 E01FB5 0 +OP4 E01FB6 0 +OP4 E01FB7 0 +OP4 E01FB8 0 +OP4 E01FB9 0 +OP4 E01FBA 0 +OP4 E01FBB 0 +OP4 E01FBC 0 +OP4 E01FBD 0 +OP4 E01FBE 0 +OP4 E01FBF 0 +OP4 E01FC0 0 +OP4 E01FC1 0 +OP4 E01FC2 0 +OP4 E01FC3 0 +OP4 E01FC4 0 +OP4 E01FC5 0 +OP4 E01FC6 0 +OP4 E01FC7 0 +OP4 E01FC8 0 +OP4 E01FC9 0 +OP4 E01FCA 0 +OP4 E01FCB 0 +OP4 E01FCC 0 +OP4 E01FCD 0 +OP4 E01FCE 0 +OP4 E01FCF 0 +OP4 E01FD0 0 +OP4 E01FD1 0 +OP4 E01FD2 0 +OP4 E01FD3 0 +OP4 E01FD4 0 +OP4 E01FD5 0 +OP4 E01FD6 0 +OP4 E01FD7 0 +OP4 E01FD8 0 +OP4 E01FD9 0 +OP4 E01FDA 0 +OP4 E01FDB 0 +OP4 E01FDC 0 +OP4 E01FDD 0 +OP4 E01FDE 0 +OP4 E01FDF 0 +OP4 E01FE0 0 +OP4 E01FE1 0 +OP4 E01FE2 0 +OP4 E01FE3 0 +OP4 E01FE4 0 +OP4 E01FE5 0 +OP4 E01FE6 0 +OP4 E01FE7 0 +OP4 E01FE8 0 +OP4 E01FE9 0 +OP4 E01FEA 0 +OP4 E01FEB 0 +OP4 E01FEC 0 +OP4 E01FED 0 +OP4 E01FEE 0 +OP4 E01FEF 0 +OP4 E01FF0 0 +OP4 E01FF1 0 +OP4 E01FF2 0 +OP4 E01FF3 0 +OP4 E01FF4 0 +OP4 E01FF5 0 +OP4 E01FF6 0 +OP4 E01FF7 0 +OP4 E01FF8 0 +OP4 E01FF9 0 +OP4 E01FFA 0 +OP4 E01FFB 0 +OP4 E01FFC 0 +OP4 E01FFD 0 +OP4 E01FFE 0 +OP4 E01FFF 0 +OP4 E02000 0 +OP4 E02001 0 +OP4 E02002 0 +OP4 E02003 0 +OP4 E02004 0 +OP4 E02005 0 +OP4 E02006 0 +OP4 E02007 0 +OP4 E02008 0 +OP4 E02009 0 +OP4 E0200A 0 +OP4 E0200B 0 +OP4 E0200C 0 +OP4 E0200D 0 +OP4 E0200E 0 +OP4 E0200F 0 +OP4 E02010 0 +OP4 E02011 0 +OP4 E02012 0 +OP4 E02013 0 +OP4 E02014 0 +OP4 E02015 0 +OP4 E02016 0 +OP4 E02017 0 +OP4 E02018 0 +OP4 E02019 0 +OP4 E0201A 0 +OP4 E0201B 0 +OP4 E0201C 0 +OP4 E0201D 0 +OP4 E0201E 0 +OP4 E0201F 0 +OP4 E02020 0 +OP4 E02021 0 +OP4 E02022 0 +OP4 E02023 0 +OP4 E02024 0 +OP4 E02025 0 +OP4 E02026 0 +OP4 E02027 0 +OP4 E02028 0 +OP4 E02029 0 +OP4 E0202A 0 +OP4 E0202B 0 +OP4 E0202C 0 +OP4 E0202D 0 +OP4 E0202E 0 +OP4 E0202F 0 +OP4 E02030 0 +OP4 E02031 0 +OP4 E02032 0 +OP4 E02033 0 +OP4 E02034 0 +OP4 E02035 0 +OP4 E02036 0 +OP4 E02037 0 +OP4 E02038 0 +OP4 E02039 0 +OP4 E0203A 0 +OP4 E0203B 0 +OP4 E0203C 0 +OP4 E0203D 0 +OP4 E0203E 0 +OP4 E0203F 0 +OP4 E02040 0 +OP4 E02041 0 +OP4 E02042 0 +OP4 E02043 0 +OP4 E02044 0 +OP4 E02045 0 +OP4 E02046 0 +OP4 E02047 0 +OP4 E02048 0 +OP4 E02049 0 +OP4 E0204A 0 +OP4 E0204B 0 +OP4 E0204C 0 +OP4 E0204D 0 +OP4 E0204E 0 +OP4 E0204F 0 +OP4 E02050 0 +OP4 E02051 0 +OP4 E02052 0 +OP4 E02053 0 +OP4 E02054 0 +OP4 E02055 0 +OP4 E02056 0 +OP4 E02057 0 +OP4 E02058 0 +OP4 E02059 0 +OP4 E0205A 0 +OP4 E0205B 0 +OP4 E0205C 0 +OP4 E0205D 0 +OP4 E0205E 0 +OP4 E0205F 0 +OP4 E02060 0 +OP4 E02061 0 +OP4 E02062 0 +OP4 E02063 0 +OP4 E02064 0 +OP4 E02065 0 +OP4 E02066 0 +OP4 E02067 0 +OP4 E02068 0 +OP4 E02069 0 +OP4 E0206A 0 +OP4 E0206B 0 +OP4 E0206C 0 +OP4 E0206D 0 +OP4 E0206E 0 +OP4 E0206F 0 +OP4 E02070 0 +OP4 E02071 0 +OP4 E02072 0 +OP4 E02073 0 +OP4 E02074 0 +OP4 E02075 0 +OP4 E02076 0 +OP4 E02077 0 +OP4 E02078 0 +OP4 E02079 0 +OP4 E0207A 0 +OP4 E0207B 0 +OP4 E0207C 0 +OP4 E0207D 0 +OP4 E0207E 0 +OP4 E0207F 0 +OP4 E02080 0 +OP4 E02081 0 +OP4 E02082 0 +OP4 E02083 0 +OP4 E02084 0 +OP4 E02085 0 +OP4 E02086 0 +OP4 E02087 0 +OP4 E02088 0 +OP4 E02089 0 +OP4 E0208A 0 +OP4 E0208B 0 +OP4 E0208C 0 +OP4 E0208D 0 +OP4 E0208E 0 +OP4 E0208F 0 +OP4 E02090 0 +OP4 E02091 0 +OP4 E02092 0 +OP4 E02093 0 +OP4 E02094 0 +OP4 E02095 0 +OP4 E02096 0 +OP4 E02097 0 +OP4 E02098 0 +OP4 E02099 0 +OP4 E0209A 0 +OP4 E0209B 0 +OP4 E0209C 0 +OP4 E0209D 0 +OP4 E0209E 0 +OP4 E0209F 0 +OP4 E020A0 0 +OP4 E020A1 0 +OP4 E020A2 0 +OP4 E020A3 0 +OP4 E020A4 0 +OP4 E020A5 0 +OP4 E020A6 0 +OP4 E020A7 0 +OP4 E020A8 0 +OP4 E020A9 0 +OP4 E020AA 0 +OP4 E020AB 0 +OP4 E020AC 0 +OP4 E020AD 0 +OP4 E020AE 0 +OP4 E020AF 0 +OP4 E020B0 0 +OP4 E020B1 0 +OP4 E020B2 0 +OP4 E020B3 0 +OP4 E020B4 0 +OP4 E020B5 0 +OP4 E020B6 0 +OP4 E020B7 0 +OP4 E020B8 0 +OP4 E020B9 0 +OP4 E020BA 0 +OP4 E020BB 0 +OP4 E020BC 0 +OP4 E020BD 0 +OP4 E020BE 0 +OP4 E020BF 0 +OP4 E020C0 0 +OP4 E020C1 0 +OP4 E020C2 0 +OP4 E020C3 0 +OP4 E020C4 0 +OP4 E020C5 0 +OP4 E020C6 0 +OP4 E020C7 0 +OP4 E020C8 0 +OP4 E020C9 0 +OP4 E020CA 0 +OP4 E020CB 0 +OP4 E020CC 0 +OP4 E020CD 0 +OP4 E020CE 0 +OP4 E020CF 0 +OP4 E020D0 0 +OP4 E020D1 0 +OP4 E020D2 0 +OP4 E020D3 0 +OP4 E020D4 0 +OP4 E020D5 0 +OP4 E020D6 0 +OP4 E020D7 0 +OP4 E020D8 0 +OP4 E020D9 0 +OP4 E020DA 0 +OP4 E020DB 0 +OP4 E020DC 0 +OP4 E020DD 0 +OP4 E020DE 0 +OP4 E020DF 0 +OP4 E020E0 0 +OP4 E020E1 0 +OP4 E020E2 0 +OP4 E020E3 0 +OP4 E020E4 0 +OP4 E020E5 0 +OP4 E020E6 0 +OP4 E020E7 0 +OP4 E020E8 0 +OP4 E020E9 0 +OP4 E020EA 0 +OP4 E020EB 0 +OP4 E020EC 0 +OP4 E020ED 0 +OP4 E020EE 0 +OP4 E020EF 0 +OP4 E020F0 0 +OP4 E020F1 0 +OP4 E020F2 0 +OP4 E020F3 0 +OP4 E020F4 0 +OP4 E020F5 0 +OP4 E020F6 0 +OP4 E020F7 0 +OP4 E020F8 0 +OP4 E020F9 0 +OP4 E020FA 0 +OP4 E020FB 0 +OP4 E020FC 0 +OP4 E020FD 0 +OP4 E020FE 0 +OP4 E020FF 0 +OP4 E02100 0 +OP4 E02101 0 +OP4 E02102 0 +OP4 E02103 0 +OP4 E02104 0 +OP4 E02105 0 +OP4 E02106 0 +OP4 E02107 0 +OP4 E02108 0 +OP4 E02109 0 +OP4 E0210A 0 +OP4 E0210B 0 +OP4 E0210C 0 +OP4 E0210D 0 +OP4 E0210E 0 +OP4 E0210F 0 +OP4 E02110 0 +OP4 E02111 0 +OP4 E02112 0 +OP4 E02113 0 +OP4 E02114 0 +OP4 E02115 0 +OP4 E02116 0 +OP4 E02117 0 +OP4 E02118 0 +OP4 E02119 0 +OP4 E0211A 0 +OP4 E0211B 0 +OP4 E0211C 0 +OP4 E0211D 0 +OP4 E0211E 0 +OP4 E0211F 0 +OP4 E02120 0 +OP4 E02121 0 +OP4 E02122 0 +OP4 E02123 0 +OP4 E02124 0 +OP4 E02125 0 +OP4 E02126 0 +OP4 E02127 0 +OP4 E02128 0 +OP4 E02129 0 +OP4 E0212A 0 +OP4 E0212B 0 +OP4 E0212C 0 +OP4 E0212D 0 +OP4 E0212E 0 +OP4 E0212F 0 +OP4 E02130 0 +OP4 E02131 0 +OP4 E02132 0 +OP4 E02133 0 +OP4 E02134 0 +OP4 E02135 0 +OP4 E02136 0 +OP4 E02137 0 +OP4 E02138 0 +OP4 E02139 0 +OP4 E0213A 0 +OP4 E0213B 0 +OP4 E0213C 0 +OP4 E0213D 0 +OP4 E0213E 0 +OP4 E0213F 0 +OP4 E02140 0 +OP4 E02141 0 +OP4 E02142 0 +OP4 E02143 0 +OP4 E02144 0 +OP4 E02145 0 +OP4 E02146 0 +OP4 E02147 0 +OP4 E02148 0 +OP4 E02149 0 +OP4 E0214A 0 +OP4 E0214B 0 +OP4 E0214C 0 +OP4 E0214D 0 +OP4 E0214E 0 +OP4 E0214F 0 +OP4 E02150 0 +OP4 E02151 0 +OP4 E02152 0 +OP4 E02153 0 +OP4 E02154 0 +OP4 E02155 0 +OP4 E02156 0 +OP4 E02157 0 +OP4 E02158 0 +OP4 E02159 0 +OP4 E0215A 0 +OP4 E0215B 0 +OP4 E0215C 0 +OP4 E0215D 0 +OP4 E0215E 0 +OP4 E0215F 0 +OP4 E02160 0 +OP4 E02161 0 +OP4 E02162 0 +OP4 E02163 0 +OP4 E02164 0 +OP4 E02165 0 +OP4 E02166 0 +OP4 E02167 0 +OP4 E02168 0 +OP4 E02169 0 +OP4 E0216A 0 +OP4 E0216B 0 +OP4 E0216C 0 +OP4 E0216D 0 +OP4 E0216E 0 +OP4 E0216F 0 +OP4 E02170 0 +OP4 E02171 0 +OP4 E02172 0 +OP4 E02173 0 +OP4 E02174 0 +OP4 E02175 0 +OP4 E02176 0 +OP4 E02177 0 +OP4 E02178 0 +OP4 E02179 0 +OP4 E0217A 0 +OP4 E0217B 0 +OP4 E0217C 0 +OP4 E0217D 0 +OP4 E0217E 0 +OP4 E0217F 0 +OP4 E02180 0 +OP4 E02181 0 +OP4 E02182 0 +OP4 E02183 0 +OP4 E02184 0 +OP4 E02185 0 +OP4 E02186 0 +OP4 E02187 0 +OP4 E02188 0 +OP4 E02189 0 +OP4 E0218A 0 +OP4 E0218B 0 +OP4 E0218C 0 +OP4 E0218D 0 +OP4 E0218E 0 +OP4 E0218F 0 +OP4 E02190 0 +OP4 E02191 0 +OP4 E02192 0 +OP4 E02193 0 +OP4 E02194 0 +OP4 E02195 0 +OP4 E02196 0 +OP4 E02197 0 +OP4 E02198 0 +OP4 E02199 0 +OP4 E0219A 0 +OP4 E0219B 0 +OP4 E0219C 0 +OP4 E0219D 0 +OP4 E0219E 0 +OP4 E0219F 0 +OP4 E021A0 0 +OP4 E021A1 0 +OP4 E021A2 0 +OP4 E021A3 0 +OP4 E021A4 0 +OP4 E021A5 0 +OP4 E021A6 0 +OP4 E021A7 0 +OP4 E021A8 0 +OP4 E021A9 0 +OP4 E021AA 0 +OP4 E021AB 0 +OP4 E021AC 0 +OP4 E021AD 0 +OP4 E021AE 0 +OP4 E021AF 0 +OP4 E021B0 0 +OP4 E021B1 0 +OP4 E021B2 0 +OP4 E021B3 0 +OP4 E021B4 0 +OP4 E021B5 0 +OP4 E021B6 0 +OP4 E021B7 0 +OP4 E021B8 0 +OP4 E021B9 0 +OP4 E021BA 0 +OP4 E021BB 0 +OP4 E021BC 0 +OP4 E021BD 0 +OP4 E021BE 0 +OP4 E021BF 0 +OP4 E021C0 0 +OP4 E021C1 0 +OP4 E021C2 0 +OP4 E021C3 0 +OP4 E021C4 0 +OP4 E021C5 0 +OP4 E021C6 0 +OP4 E021C7 0 +OP4 E021C8 0 +OP4 E021C9 0 +OP4 E021CA 0 +OP4 E021CB 0 +OP4 E021CC 0 +OP4 E021CD 0 +OP4 E021CE 0 +OP4 E021CF 0 +OP4 E021D0 0 +OP4 E021D1 0 +OP4 E021D2 0 +OP4 E021D3 0 +OP4 E021D4 0 +OP4 E021D5 0 +OP4 E021D6 0 +OP4 E021D7 0 +OP4 E021D8 0 +OP4 E021D9 0 +OP4 E021DA 0 +OP4 E021DB 0 +OP4 E021DC 0 +OP4 E021DD 0 +OP4 E021DE 0 +OP4 E021DF 0 +OP4 E021E0 0 +OP4 E021E1 0 +OP4 E021E2 0 +OP4 E021E3 0 +OP4 E021E4 0 +OP4 E021E5 0 +OP4 E021E6 0 +OP4 E021E7 0 +OP4 E021E8 0 +OP4 E021E9 0 +OP4 E021EA 0 +OP4 E021EB 0 +OP4 E021EC 0 +OP4 E021ED 0 +OP4 E021EE 0 +OP4 E021EF 0 +OP4 E021F0 0 +OP4 E021F1 0 +OP4 E021F2 0 +OP4 E021F3 0 +OP4 E021F4 0 +OP4 E021F5 0 +OP4 E021F6 0 +OP4 E021F7 0 +OP4 E021F8 0 +OP4 E021F9 0 +OP4 E021FA 0 +OP4 E021FB 0 +OP4 E021FC 0 +OP4 E021FD 0 +OP4 E021FE 0 +OP4 E021FF 0 +OP4 E02200 0 +OP4 E02201 0 +OP4 E02202 0 +OP4 E02203 0 +OP4 E02204 0 +OP4 E02205 0 +OP4 E02206 0 +OP4 E02207 0 +OP4 E02208 0 +OP4 E02209 0 +OP4 E0220A 0 +OP4 E0220B 0 +OP4 E0220C 0 +OP4 E0220D 0 +OP4 E0220E 0 +OP4 E0220F 0 +OP4 E02210 0 +OP4 E02211 0 +OP4 E02212 0 +OP4 E02213 0 +OP4 E02214 0 +OP4 E02215 0 +OP4 E02216 0 +OP4 E02217 0 +OP4 E02218 0 +OP4 E02219 0 +OP4 E0221A 0 +OP4 E0221B 0 +OP4 E0221C 0 +OP4 E0221D 0 +OP4 E0221E 0 +OP4 E0221F 0 +OP4 E02220 0 +OP4 E02221 0 +OP4 E02222 0 +OP4 E02223 0 +OP4 E02224 0 +OP4 E02225 0 +OP4 E02226 0 +OP4 E02227 0 +OP4 E02228 0 +OP4 E02229 0 +OP4 E0222A 0 +OP4 E0222B 0 +OP4 E0222C 0 +OP4 E0222D 0 +OP4 E0222E 0 +OP4 E0222F 0 +OP4 E02230 0 +OP4 E02231 0 +OP4 E02232 0 +OP4 E02233 0 +OP4 E02234 0 +OP4 E02235 0 +OP4 E02236 0 +OP4 E02237 0 +OP4 E02238 0 +OP4 E02239 0 +OP4 E0223A 0 +OP4 E0223B 0 +OP4 E0223C 0 +OP4 E0223D 0 +OP4 E0223E 0 +OP4 E0223F 0 +OP4 E02240 0 +OP4 E02241 0 +OP4 E02242 0 +OP4 E02243 0 +OP4 E02244 0 +OP4 E02245 0 +OP4 E02246 0 +OP4 E02247 0 +OP4 E02248 0 +OP4 E02249 0 +OP4 E0224A 0 +OP4 E0224B 0 +OP4 E0224C 0 +OP4 E0224D 0 +OP4 E0224E 0 +OP4 E0224F 0 +OP4 E02250 0 +OP4 E02251 0 +OP4 E02252 0 +OP4 E02253 0 +OP4 E02254 0 +OP4 E02255 0 +OP4 E02256 0 +OP4 E02257 0 +OP4 E02258 0 +OP4 E02259 0 +OP4 E0225A 0 +OP4 E0225B 0 +OP4 E0225C 0 +OP4 E0225D 0 +OP4 E0225E 0 +OP4 E0225F 0 +OP4 E02260 0 +OP4 E02261 0 +OP4 E02262 0 +OP4 E02263 0 +OP4 E02264 0 +OP4 E02265 0 +OP4 E02266 0 +OP4 E02267 0 +OP4 E02268 0 +OP4 E02269 0 +OP4 E0226A 0 +OP4 E0226B 0 +OP4 E0226C 0 +OP4 E0226D 0 +OP4 E0226E 0 +OP4 E0226F 0 +OP4 E02270 0 +OP4 E02271 0 +OP4 E02272 0 +OP4 E02273 0 +OP4 E02274 0 +OP4 E02275 0 +OP4 E02276 0 +OP4 E02277 0 +OP4 E02278 0 +OP4 E02279 0 +OP4 E0227A 0 +OP4 E0227B 0 +OP4 E0227C 0 +OP4 E0227D 0 +OP4 E0227E 0 +OP4 E0227F 0 +OP4 E02280 0 +OP4 E02281 0 +OP4 E02282 0 +OP4 E02283 0 +OP4 E02284 0 +OP4 E02285 0 +OP4 E02286 0 +OP4 E02287 0 +OP4 E02288 0 +OP4 E02289 0 +OP4 E0228A 0 +OP4 E0228B 0 +OP4 E0228C 0 +OP4 E0228D 0 +OP4 E0228E 0 +OP4 E0228F 0 +OP4 E02290 0 +OP4 E02291 0 +OP4 E02292 0 +OP4 E02293 0 +OP4 E02294 0 +OP4 E02295 0 +OP4 E02296 0 +OP4 E02297 0 +OP4 E02298 0 +OP4 E02299 0 +OP4 E0229A 0 +OP4 E0229B 0 +OP4 E0229C 0 +OP4 E0229D 0 +OP4 E0229E 0 +OP4 E0229F 0 +OP4 E022A0 0 +OP4 E022A1 0 +OP4 E022A2 0 +OP4 E022A3 0 +OP4 E022A4 0 +OP4 E022A5 0 +OP4 E022A6 0 +OP4 E022A7 0 +OP4 E022A8 0 +OP4 E022A9 0 +OP4 E022AA 0 +OP4 E022AB 0 +OP4 E022AC 0 +OP4 E022AD 0 +OP4 E022AE 0 +OP4 E022AF 0 +OP4 E022B0 0 +OP4 E022B1 0 +OP4 E022B2 0 +OP4 E022B3 0 +OP4 E022B4 0 +OP4 E022B5 0 +OP4 E022B6 0 +OP4 E022B7 0 +OP4 E022B8 0 +OP4 E022B9 0 +OP4 E022BA 0 +OP4 E022BB 0 +OP4 E022BC 0 +OP4 E022BD 0 +OP4 E022BE 0 +OP4 E022BF 0 +OP4 E022C0 0 +OP4 E022C1 0 +OP4 E022C2 0 +OP4 E022C3 0 +OP4 E022C4 0 +OP4 E022C5 0 +OP4 E022C6 0 +OP4 E022C7 0 +OP4 E022C8 0 +OP4 E022C9 0 +OP4 E022CA 0 +OP4 E022CB 0 +OP4 E022CC 0 +OP4 E022CD 0 +OP4 E022CE 0 +OP4 E022CF 0 +OP4 E022D0 0 +OP4 E022D1 0 +OP4 E022D2 0 +OP4 E022D3 0 +OP4 E022D4 0 +OP4 E022D5 0 +OP4 E022D6 0 +OP4 E022D7 0 +OP4 E022D8 0 +OP4 E022D9 0 +OP4 E022DA 0 +OP4 E022DB 0 +OP4 E022DC 0 +OP4 E022DD 0 +OP4 E022DE 0 +OP4 E022DF 0 +OP4 E022E0 0 +OP4 E022E1 0 +OP4 E022E2 0 +OP4 E022E3 0 +OP4 E022E4 0 +OP4 E022E5 0 +OP4 E022E6 0 +OP4 E022E7 0 +OP4 E022E8 0 +OP4 E022E9 0 +OP4 E022EA 0 +OP4 E022EB 0 +OP4 E022EC 0 +OP4 E022ED 0 +OP4 E022EE 0 +OP4 E022EF 0 +OP4 E022F0 0 +OP4 E022F1 0 +OP4 E022F2 0 +OP4 E022F3 0 +OP4 E022F4 0 +OP4 E022F5 0 +OP4 E022F6 0 +OP4 E022F7 0 +OP4 E022F8 0 +OP4 E022F9 0 +OP4 E022FA 0 +OP4 E022FB 0 +OP4 E022FC 0 +OP4 E022FD 0 +OP4 E022FE 0 +OP4 E022FF 0 +OP4 E02300 0 +OP4 E02301 0 +OP4 E02302 0 +OP4 E02303 0 +OP4 E02304 0 +OP4 E02305 0 +OP4 E02306 0 +OP4 E02307 0 +OP4 E02308 0 +OP4 E02309 0 +OP4 E0230A 0 +OP4 E0230B 0 +OP4 E0230C 0 +OP4 E0230D 0 +OP4 E0230E 0 +OP4 E0230F 0 +OP4 E02310 0 +OP4 E02311 0 +OP4 E02312 0 +OP4 E02313 0 +OP4 E02314 0 +OP4 E02315 0 +OP4 E02316 0 +OP4 E02317 0 +OP4 E02318 0 +OP4 E02319 0 +OP4 E0231A 0 +OP4 E0231B 0 +OP4 E0231C 0 +OP4 E0231D 0 +OP4 E0231E 0 +OP4 E0231F 0 +OP4 E02320 0 +OP4 E02321 0 +OP4 E02322 0 +OP4 E02323 0 +OP4 E02324 0 +OP4 E02325 0 +OP4 E02326 0 +OP4 E02327 0 +OP4 E02328 0 +OP4 E02329 0 +OP4 E0232A 0 +OP4 E0232B 0 +OP4 E0232C 0 +OP4 E0232D 0 +OP4 E0232E 0 +OP4 E0232F 0 +OP4 E02330 0 +OP4 E02331 0 +OP4 E02332 0 +OP4 E02333 0 +OP4 E02334 0 +OP4 E02335 0 +OP4 E02336 0 +OP4 E02337 0 +OP4 E02338 0 +OP4 E02339 0 +OP4 E0233A 0 +OP4 E0233B 0 +OP4 E0233C 0 +OP4 E0233D 0 +OP4 E0233E 0 +OP4 E0233F 0 +OP4 E02340 0 +OP4 E02341 0 +OP4 E02342 0 +OP4 E02343 0 +OP4 E02344 0 +OP4 E02345 0 +OP4 E02346 0 +OP4 E02347 0 +OP4 E02348 0 +OP4 E02349 0 +OP4 E0234A 0 +OP4 E0234B 0 +OP4 E0234C 0 +OP4 E0234D 0 +OP4 E0234E 0 +OP4 E0234F 0 +OP4 E02350 0 +OP4 E02351 0 +OP4 E02352 0 +OP4 E02353 0 +OP4 E02354 0 +OP4 E02355 0 +OP4 E02356 0 +OP4 E02357 0 +OP4 E02358 0 +OP4 E02359 0 +OP4 E0235A 0 +OP4 E0235B 0 +OP4 E0235C 0 +OP4 E0235D 0 +OP4 E0235E 0 +OP4 E0235F 0 +OP4 E02360 0 +OP4 E02361 0 +OP4 E02362 0 +OP4 E02363 0 +OP4 E02364 0 +OP4 E02365 0 +OP4 E02366 0 +OP4 E02367 0 +OP4 E02368 0 +OP4 E02369 0 +OP4 E0236A 0 +OP4 E0236B 0 +OP4 E0236C 0 +OP4 E0236D 0 +OP4 E0236E 0 +OP4 E0236F 0 +OP4 E02370 0 +OP4 E02371 0 +OP4 E02372 0 +OP4 E02373 0 +OP4 E02374 0 +OP4 E02375 0 +OP4 E02376 0 +OP4 E02377 0 +OP4 E02378 0 +OP4 E02379 0 +OP4 E0237A 0 +OP4 E0237B 0 +OP4 E0237C 0 +OP4 E0237D 0 +OP4 E0237E 0 +OP4 E0237F 0 +OP4 E02380 0 +OP4 E02381 0 +OP4 E02382 0 +OP4 E02383 0 +OP4 E02384 0 +OP4 E02385 0 +OP4 E02386 0 +OP4 E02387 0 +OP4 E02388 0 +OP4 E02389 0 +OP4 E0238A 0 +OP4 E0238B 0 +OP4 E0238C 0 +OP4 E0238D 0 +OP4 E0238E 0 +OP4 E0238F 0 +OP4 E02390 0 +OP4 E02391 0 +OP4 E02392 0 +OP4 E02393 0 +OP4 E02394 0 +OP4 E02395 0 +OP4 E02396 0 +OP4 E02397 0 +OP4 E02398 0 +OP4 E02399 0 +OP4 E0239A 0 +OP4 E0239B 0 +OP4 E0239C 0 +OP4 E0239D 0 +OP4 E0239E 0 +OP4 E0239F 0 +OP4 E023A0 0 +OP4 E023A1 0 +OP4 E023A2 0 +OP4 E023A3 0 +OP4 E023A4 0 +OP4 E023A5 0 +OP4 E023A6 0 +OP4 E023A7 0 +OP4 E023A8 0 +OP4 E023A9 0 +OP4 E023AA 0 +OP4 E023AB 0 +OP4 E023AC 0 +OP4 E023AD 0 +OP4 E023AE 0 +OP4 E023AF 0 +OP4 E023B0 0 +OP4 E023B1 0 +OP4 E023B2 0 +OP4 E023B3 0 +OP4 E023B4 0 +OP4 E023B5 0 +OP4 E023B6 0 +OP4 E023B7 0 +OP4 E023B8 0 +OP4 E023B9 0 +OP4 E023BA 0 +OP4 E023BB 0 +OP4 E023BC 0 +OP4 E023BD 0 +OP4 E023BE 0 +OP4 E023BF 0 +OP4 E023C0 0 +OP4 E023C1 0 +OP4 E023C2 0 +OP4 E023C3 0 +OP4 E023C4 0 +OP4 E023C5 0 +OP4 E023C6 0 +OP4 E023C7 0 +OP4 E023C8 0 +OP4 E023C9 0 +OP4 E023CA 0 +OP4 E023CB 0 +OP4 E023CC 0 +OP4 E023CD 0 +OP4 E023CE 0 +OP4 E023CF 0 +OP4 E023D0 0 +OP4 E023D1 0 +OP4 E023D2 0 +OP4 E023D3 0 +OP4 E023D4 0 +OP4 E023D5 0 +OP4 E023D6 0 +OP4 E023D7 0 +OP4 E023D8 0 +OP4 E023D9 0 +OP4 E023DA 0 +OP4 E023DB 0 +OP4 E023DC 0 +OP4 E023DD 0 +OP4 E023DE 0 +OP4 E023DF 0 +OP4 E023E0 0 +OP4 E023E1 0 +OP4 E023E2 0 +OP4 E023E3 0 +OP4 E023E4 0 +OP4 E023E5 0 +OP4 E023E6 0 +OP4 E023E7 0 +OP4 E023E8 0 +OP4 E023E9 0 +OP4 E023EA 0 +OP4 E023EB 0 +OP4 E023EC 0 +OP4 E023ED 0 +OP4 E023EE 0 +OP4 E023EF 0 +OP4 E023F0 0 +OP4 E023F1 0 +OP4 E023F2 0 +OP4 E023F3 0 +OP4 E023F4 0 +OP4 E023F5 0 +OP4 E023F6 0 +OP4 E023F7 0 +OP4 E023F8 0 +OP4 E023F9 0 +OP4 E023FA 0 +OP4 E023FB 0 +OP4 E023FC 0 +OP4 E023FD 0 +OP4 E023FE 0 +OP4 E023FF 0 +OP4 E02400 0 +OP4 E02401 0 +OP4 E02402 0 +OP4 E02403 0 +OP4 E02404 0 +OP4 E02405 0 +OP4 E02406 0 +OP4 E02407 0 +OP4 E02408 0 +OP4 E02409 0 +OP4 E0240A 0 +OP4 E0240B 0 +OP4 E0240C 0 +OP4 E0240D 0 +OP4 E0240E 0 +OP4 E0240F 0 +OP4 E02410 0 +OP4 E02411 0 +OP4 E02412 0 +OP4 E02413 0 +OP4 E02414 0 +OP4 E02415 0 +OP4 E02416 0 +OP4 E02417 0 +OP4 E02418 0 +OP4 E02419 0 +OP4 E0241A 0 +OP4 E0241B 0 +OP4 E0241C 0 +OP4 E0241D 0 +OP4 E0241E 0 +OP4 E0241F 0 +OP4 E02420 0 +OP4 E02421 0 +OP4 E02422 0 +OP4 E02423 0 +OP4 E02424 0 +OP4 E02425 0 +OP4 E02426 0 +OP4 E02427 0 +OP4 E02428 0 +OP4 E02429 0 +OP4 E0242A 0 +OP4 E0242B 0 +OP4 E0242C 0 +OP4 E0242D 0 +OP4 E0242E 0 +OP4 E0242F 0 +OP4 E02430 0 +OP4 E02431 0 +OP4 E02432 0 +OP4 E02433 0 +OP4 E02434 0 +OP4 E02435 0 +OP4 E02436 0 +OP4 E02437 0 +OP4 E02438 0 +OP4 E02439 0 +OP4 E0243A 0 +OP4 E0243B 0 +OP4 E0243C 0 +OP4 E0243D 0 +OP4 E0243E 0 +OP4 E0243F 0 +OP4 E02440 0 +OP4 E02441 0 +OP4 E02442 0 +OP4 E02443 0 +OP4 E02444 0 +OP4 E02445 0 +OP4 E02446 0 +OP4 E02447 0 +OP4 E02448 0 +OP4 E02449 0 +OP4 E0244A 0 +OP4 E0244B 0 +OP4 E0244C 0 +OP4 E0244D 0 +OP4 E0244E 0 +OP4 E0244F 0 +OP4 E02450 0 +OP4 E02451 0 +OP4 E02452 0 +OP4 E02453 0 +OP4 E02454 0 +OP4 E02455 0 +OP4 E02456 0 +OP4 E02457 0 +OP4 E02458 0 +OP4 E02459 0 +OP4 E0245A 0 +OP4 E0245B 0 +OP4 E0245C 0 +OP4 E0245D 0 +OP4 E0245E 0 +OP4 E0245F 0 +OP4 E02460 0 +OP4 E02461 0 +OP4 E02462 0 +OP4 E02463 0 +OP4 E02464 0 +OP4 E02465 0 +OP4 E02466 0 +OP4 E02467 0 +OP4 E02468 0 +OP4 E02469 0 +OP4 E0246A 0 +OP4 E0246B 0 +OP4 E0246C 0 +OP4 E0246D 0 +OP4 E0246E 0 +OP4 E0246F 0 +OP4 E02470 0 +OP4 E02471 0 +OP4 E02472 0 +OP4 E02473 0 +OP4 E02474 0 +OP4 E02475 0 +OP4 E02476 0 +OP4 E02477 0 +OP4 E02478 0 +OP4 E02479 0 +OP4 E0247A 0 +OP4 E0247B 0 +OP4 E0247C 0 +OP4 E0247D 0 +OP4 E0247E 0 +OP4 E0247F 0 +OP4 E02480 0 +OP4 E02481 0 +OP4 E02482 0 +OP4 E02483 0 +OP4 E02484 0 +OP4 E02485 0 +OP4 E02486 0 +OP4 E02487 0 +OP4 E02488 0 +OP4 E02489 0 +OP4 E0248A 0 +OP4 E0248B 0 +OP4 E0248C 0 +OP4 E0248D 0 +OP4 E0248E 0 +OP4 E0248F 0 +OP4 E02490 0 +OP4 E02491 0 +OP4 E02492 0 +OP4 E02493 0 +OP4 E02494 0 +OP4 E02495 0 +OP4 E02496 0 +OP4 E02497 0 +OP4 E02498 0 +OP4 E02499 0 +OP4 E0249A 0 +OP4 E0249B 0 +OP4 E0249C 0 +OP4 E0249D 0 +OP4 E0249E 0 +OP4 E0249F 0 +OP4 E024A0 0 +OP4 E024A1 0 +OP4 E024A2 0 +OP4 E024A3 0 +OP4 E024A4 0 +OP4 E024A5 0 +OP4 E024A6 0 +OP4 E024A7 0 +OP4 E024A8 0 +OP4 E024A9 0 +OP4 E024AA 0 +OP4 E024AB 0 +OP4 E024AC 0 +OP4 E024AD 0 +OP4 E024AE 0 +OP4 E024AF 0 +OP4 E024B0 0 +OP4 E024B1 0 +OP4 E024B2 0 +OP4 E024B3 0 +OP4 E024B4 0 +OP4 E024B5 0 +OP4 E024B6 0 +OP4 E024B7 0 +OP4 E024B8 0 +OP4 E024B9 0 +OP4 E024BA 0 +OP4 E024BB 0 +OP4 E024BC 0 +OP4 E024BD 0 +OP4 E024BE 0 +OP4 E024BF 0 +OP4 E024C0 0 +OP4 E024C1 0 +OP4 E024C2 0 +OP4 E024C3 0 +OP4 E024C4 0 +OP4 E024C5 0 +OP4 E024C6 0 +OP4 E024C7 0 +OP4 E024C8 0 +OP4 E024C9 0 +OP4 E024CA 0 +OP4 E024CB 0 +OP4 E024CC 0 +OP4 E024CD 0 +OP4 E024CE 0 +OP4 E024CF 0 +OP4 E024D0 0 +OP4 E024D1 0 +OP4 E024D2 0 +OP4 E024D3 0 +OP4 E024D4 0 +OP4 E024D5 0 +OP4 E024D6 0 +OP4 E024D7 0 +OP4 E024D8 0 +OP4 E024D9 0 +OP4 E024DA 0 +OP4 E024DB 0 +OP4 E024DC 0 +OP4 E024DD 0 +OP4 E024DE 0 +OP4 E024DF 0 +OP4 E024E0 0 +OP4 E024E1 0 +OP4 E024E2 0 +OP4 E024E3 0 +OP4 E024E4 0 +OP4 E024E5 0 +OP4 E024E6 0 +OP4 E024E7 0 +OP4 E024E8 0 +OP4 E024E9 0 +OP4 E024EA 0 +OP4 E024EB 0 +OP4 E024EC 0 +OP4 E024ED 0 +OP4 E024EE 0 +OP4 E024EF 0 +OP4 E024F0 0 +OP4 E024F1 0 +OP4 E024F2 0 +OP4 E024F3 0 +OP4 E024F4 0 +OP4 E024F5 0 +OP4 E024F6 0 +OP4 E024F7 0 +OP4 E024F8 0 +OP4 E024F9 0 +OP4 E024FA 0 +OP4 E024FB 0 +OP4 E024FC 0 +OP4 E024FD 0 +OP4 E024FE 0 +OP4 E024FF 0 +OP4 E02500 0 +OP4 E02501 0 +OP4 E02502 0 +OP4 E02503 0 +OP4 E02504 0 +OP4 E02505 0 +OP4 E02506 0 +OP4 E02507 0 +OP4 E02508 0 +OP4 E02509 0 +OP4 E0250A 0 +OP4 E0250B 0 +OP4 E0250C 0 +OP4 E0250D 0 +OP4 E0250E 0 +OP4 E0250F 0 +OP4 E02510 0 +OP4 E02511 0 +OP4 E02512 0 +OP4 E02513 0 +OP4 E02514 0 +OP4 E02515 0 +OP4 E02516 0 +OP4 E02517 0 +OP4 E02518 0 +OP4 E02519 0 +OP4 E0251A 0 +OP4 E0251B 0 +OP4 E0251C 0 +OP4 E0251D 0 +OP4 E0251E 0 +OP4 E0251F 0 +OP4 E02520 0 +OP4 E02521 0 +OP4 E02522 0 +OP4 E02523 0 +OP4 E02524 0 +OP4 E02525 0 +OP4 E02526 0 +OP4 E02527 0 +OP4 E02528 0 +OP4 E02529 0 +OP4 E0252A 0 +OP4 E0252B 0 +OP4 E0252C 0 +OP4 E0252D 0 +OP4 E0252E 0 +OP4 E0252F 0 +OP4 E02530 0 +OP4 E02531 0 +OP4 E02532 0 +OP4 E02533 0 +OP4 E02534 0 +OP4 E02535 0 +OP4 E02536 0 +OP4 E02537 0 +OP4 E02538 0 +OP4 E02539 0 +OP4 E0253A 0 +OP4 E0253B 0 +OP4 E0253C 0 +OP4 E0253D 0 +OP4 E0253E 0 +OP4 E0253F 0 +OP4 E02540 0 +OP4 E02541 0 +OP4 E02542 0 +OP4 E02543 0 +OP4 E02544 0 +OP4 E02545 0 +OP4 E02546 0 +OP4 E02547 0 +OP4 E02548 0 +OP4 E02549 0 +OP4 E0254A 0 +OP4 E0254B 0 +OP4 E0254C 0 +OP4 E0254D 0 +OP4 E0254E 0 +OP4 E0254F 0 +OP4 E02550 0 +OP4 E02551 0 +OP4 E02552 0 +OP4 E02553 0 +OP4 E02554 0 +OP4 E02555 0 +OP4 E02556 0 +OP4 E02557 0 +OP4 E02558 0 +OP4 E02559 0 +OP4 E0255A 0 +OP4 E0255B 0 +OP4 E0255C 0 +OP4 E0255D 0 +OP4 E0255E 0 +OP4 E0255F 0 +OP4 E02560 0 +OP4 E02561 0 +OP4 E02562 0 +OP4 E02563 0 +OP4 E02564 0 +OP4 E02565 0 +OP4 E02566 0 +OP4 E02567 0 +OP4 E02568 0 +OP4 E02569 0 +OP4 E0256A 0 +OP4 E0256B 0 +OP4 E0256C 0 +OP4 E0256D 0 +OP4 E0256E 0 +OP4 E0256F 0 +OP4 E02570 0 +OP4 E02571 0 +OP4 E02572 0 +OP4 E02573 0 +OP4 E02574 0 +OP4 E02575 0 +OP4 E02576 0 +OP4 E02577 0 +OP4 E02578 0 +OP4 E02579 0 +OP4 E0257A 0 +OP4 E0257B 0 +OP4 E0257C 0 +OP4 E0257D 0 +OP4 E0257E 0 +OP4 E0257F 0 +OP4 E02580 0 +OP4 E02581 0 +OP4 E02582 0 +OP4 E02583 0 +OP4 E02584 0 +OP4 E02585 0 +OP4 E02586 0 +OP4 E02587 0 +OP4 E02588 0 +OP4 E02589 0 +OP4 E0258A 0 +OP4 E0258B 0 +OP4 E0258C 0 +OP4 E0258D 0 +OP4 E0258E 0 +OP4 E0258F 0 +OP4 E02590 0 +OP4 E02591 0 +OP4 E02592 0 +OP4 E02593 0 +OP4 E02594 0 +OP4 E02595 0 +OP4 E02596 0 +OP4 E02597 0 +OP4 E02598 0 +OP4 E02599 0 +OP4 E0259A 0 +OP4 E0259B 0 +OP4 E0259C 0 +OP4 E0259D 0 +OP4 E0259E 0 +OP4 E0259F 0 +OP4 E025A0 0 +OP4 E025A1 0 +OP4 E025A2 0 +OP4 E025A3 0 +OP4 E025A4 0 +OP4 E025A5 0 +OP4 E025A6 0 +OP4 E025A7 0 +OP4 E025A8 0 +OP4 E025A9 0 +OP4 E025AA 0 +OP4 E025AB 0 +OP4 E025AC 0 +OP4 E025AD 0 +OP4 E025AE 0 +OP4 E025AF 0 +OP4 E025B0 0 +OP4 E025B1 0 +OP4 E025B2 0 +OP4 E025B3 0 +OP4 E025B4 0 +OP4 E025B5 0 +OP4 E025B6 0 +OP4 E025B7 0 +OP4 E025B8 0 +OP4 E025B9 0 +OP4 E025BA 0 +OP4 E025BB 0 +OP4 E025BC 0 +OP4 E025BD 0 +OP4 E025BE 0 +OP4 E025BF 0 +OP4 E025C0 0 +OP4 E025C1 0 +OP4 E025C2 0 +OP4 E025C3 0 +OP4 E025C4 0 +OP4 E025C5 0 +OP4 E025C6 0 +OP4 E025C7 0 +OP4 E025C8 0 +OP4 E025C9 0 +OP4 E025CA 0 +OP4 E025CB 0 +OP4 E025CC 0 +OP4 E025CD 0 +OP4 E025CE 0 +OP4 E025CF 0 +OP4 E025D0 0 +OP4 E025D1 0 +OP4 E025D2 0 +OP4 E025D3 0 +OP4 E025D4 0 +OP4 E025D5 0 +OP4 E025D6 0 +OP4 E025D7 0 +OP4 E025D8 0 +OP4 E025D9 0 +OP4 E025DA 0 +OP4 E025DB 0 +OP4 E025DC 0 +OP4 E025DD 0 +OP4 E025DE 0 +OP4 E025DF 0 +OP4 E025E0 0 +OP4 E025E1 0 +OP4 E025E2 0 +OP4 E025E3 0 +OP4 E025E4 0 +OP4 E025E5 0 +OP4 E025E6 0 +OP4 E025E7 0 +OP4 E025E8 0 +OP4 E025E9 0 +OP4 E025EA 0 +OP4 E025EB 0 +OP4 E025EC 0 +OP4 E025ED 0 +OP4 E025EE 0 +OP4 E025EF 0 +OP4 E025F0 0 +OP4 E025F1 0 +OP4 E025F2 0 +OP4 E025F3 0 +OP4 E025F4 0 +OP4 E025F5 0 +OP4 E025F6 0 +OP4 E025F7 0 +OP4 E025F8 0 +OP4 E025F9 0 +OP4 E025FA 0 +OP4 E025FB 0 +OP4 E025FC 0 +OP4 E025FD 0 +OP4 E025FE 0 +OP4 E025FF 0 +OP4 E02600 0 +OP4 E02601 0 +OP4 E02602 0 +OP4 E02603 0 +OP4 E02604 0 +OP4 E02605 0 +OP4 E02606 0 +OP4 E02607 0 +OP4 E02608 0 +OP4 E02609 0 +OP4 E0260A 0 +OP4 E0260B 0 +OP4 E0260C 0 +OP4 E0260D 0 +OP4 E0260E 0 +OP4 E0260F 0 +OP4 E02610 0 +OP4 E02611 0 +OP4 E02612 0 +OP4 E02613 0 +OP4 E02614 0 +OP4 E02615 0 +OP4 E02616 0 +OP4 E02617 0 +OP4 E02618 0 +OP4 E02619 0 +OP4 E0261A 0 +OP4 E0261B 0 +OP4 E0261C 0 +OP4 E0261D 0 +OP4 E0261E 0 +OP4 E0261F 0 +OP4 E02620 0 +OP4 E02621 0 +OP4 E02622 0 +OP4 E02623 0 +OP4 E02624 0 +OP4 E02625 0 +OP4 E02626 0 +OP4 E02627 0 +OP4 E02628 0 +OP4 E02629 0 +OP4 E0262A 0 +OP4 E0262B 0 +OP4 E0262C 0 +OP4 E0262D 0 +OP4 E0262E 0 +OP4 E0262F 0 +OP4 E02630 0 +OP4 E02631 0 +OP4 E02632 0 +OP4 E02633 0 +OP4 E02634 0 +OP4 E02635 0 +OP4 E02636 0 +OP4 E02637 0 +OP4 E02638 0 +OP4 E02639 0 +OP4 E0263A 0 +OP4 E0263B 0 +OP4 E0263C 0 +OP4 E0263D 0 +OP4 E0263E 0 +OP4 E0263F 0 +OP4 E02640 0 +OP4 E02641 0 +OP4 E02642 0 +OP4 E02643 0 +OP4 E02644 0 +OP4 E02645 0 +OP4 E02646 0 +OP4 E02647 0 +OP4 E02648 0 +OP4 E02649 0 +OP4 E0264A 0 +OP4 E0264B 0 +OP4 E0264C 0 +OP4 E0264D 0 +OP4 E0264E 0 +OP4 E0264F 0 +OP4 E02650 0 +OP4 E02651 0 +OP4 E02652 0 +OP4 E02653 0 +OP4 E02654 0 +OP4 E02655 0 +OP4 E02656 0 +OP4 E02657 0 +OP4 E02658 0 +OP4 E02659 0 +OP4 E0265A 0 +OP4 E0265B 0 +OP4 E0265C 0 +OP4 E0265D 0 +OP4 E0265E 0 +OP4 E0265F 0 +OP4 E02660 0 +OP4 E02661 0 +OP4 E02662 0 +OP4 E02663 0 +OP4 E02664 0 +OP4 E02665 0 +OP4 E02666 0 +OP4 E02667 0 +OP4 E02668 0 +OP4 E02669 0 +OP4 E0266A 0 +OP4 E0266B 0 +OP4 E0266C 0 +OP4 E0266D 0 +OP4 E0266E 0 +OP4 E0266F 0 +OP4 E02670 0 +OP4 E02671 0 +OP4 E02672 0 +OP4 E02673 0 +OP4 E02674 0 +OP4 E02675 0 +OP4 E02676 0 +OP4 E02677 0 +OP4 E02678 0 +OP4 E02679 0 +OP4 E0267A 0 +OP4 E0267B 0 +OP4 E0267C 0 +OP4 E0267D 0 +OP4 E0267E 0 +OP4 E0267F 0 +OP4 E02680 0 +OP4 E02681 0 +OP4 E02682 0 +OP4 E02683 0 +OP4 E02684 0 +OP4 E02685 0 +OP4 E02686 0 +OP4 E02687 0 +OP4 E02688 0 +OP4 E02689 0 +OP4 E0268A 0 +OP4 E0268B 0 +OP4 E0268C 0 +OP4 E0268D 0 +OP4 E0268E 0 +OP4 E0268F 0 +OP4 E02690 0 +OP4 E02691 0 +OP4 E02692 0 +OP4 E02693 0 +OP4 E02694 0 +OP4 E02695 0 +OP4 E02696 0 +OP4 E02697 0 +OP4 E02698 0 +OP4 E02699 0 +OP4 E0269A 0 +OP4 E0269B 0 +OP4 E0269C 0 +OP4 E0269D 0 +OP4 E0269E 0 +OP4 E0269F 0 +OP4 E026A0 0 +OP4 E026A1 0 +OP4 E026A2 0 +OP4 E026A3 0 +OP4 E026A4 0 +OP4 E026A5 0 +OP4 E026A6 0 +OP4 E026A7 0 +OP4 E026A8 0 +OP4 E026A9 0 +OP4 E026AA 0 +OP4 E026AB 0 +OP4 E026AC 0 +OP4 E026AD 0 +OP4 E026AE 0 +OP4 E026AF 0 +OP4 E026B0 0 +OP4 E026B1 0 +OP4 E026B2 0 +OP4 E026B3 0 +OP4 E026B4 0 +OP4 E026B5 0 +OP4 E026B6 0 +OP4 E026B7 0 +OP4 E026B8 0 +OP4 E026B9 0 +OP4 E026BA 0 +OP4 E026BB 0 +OP4 E026BC 0 +OP4 E026BD 0 +OP4 E026BE 0 +OP4 E026BF 0 +OP4 E026C0 0 +OP4 E026C1 0 +OP4 E026C2 0 +OP4 E026C3 0 +OP4 E026C4 0 +OP4 E026C5 0 +OP4 E026C6 0 +OP4 E026C7 0 +OP4 E026C8 0 +OP4 E026C9 0 +OP4 E026CA 0 +OP4 E026CB 0 +OP4 E026CC 0 +OP4 E026CD 0 +OP4 E026CE 0 +OP4 E026CF 0 +OP4 E026D0 0 +OP4 E026D1 0 +OP4 E026D2 0 +OP4 E026D3 0 +OP4 E026D4 0 +OP4 E026D5 0 +OP4 E026D6 0 +OP4 E026D7 0 +OP4 E026D8 0 +OP4 E026D9 0 +OP4 E026DA 0 +OP4 E026DB 0 +OP4 E026DC 0 +OP4 E026DD 0 +OP4 E026DE 0 +OP4 E026DF 0 +OP4 E026E0 0 +OP4 E026E1 0 +OP4 E026E2 0 +OP4 E026E3 0 +OP4 E026E4 0 +OP4 E026E5 0 +OP4 E026E6 0 +OP4 E026E7 0 +OP4 E026E8 0 +OP4 E026E9 0 +OP4 E026EA 0 +OP4 E026EB 0 +OP4 E026EC 0 +OP4 E026ED 0 +OP4 E026EE 0 +OP4 E026EF 0 +OP4 E026F0 0 +OP4 E026F1 0 +OP4 E026F2 0 +OP4 E026F3 0 +OP4 E026F4 0 +OP4 E026F5 0 +OP4 E026F6 0 +OP4 E026F7 0 +OP4 E026F8 0 +OP4 E026F9 0 +OP4 E026FA 0 +OP4 E026FB 0 +OP4 E026FC 0 +OP4 E026FD 0 +OP4 E026FE 0 +OP4 E026FF 0 +OP4 E02700 0 +OP4 E02701 0 +OP4 E02702 0 +OP4 E02703 0 +OP4 E02704 0 +OP4 E02705 0 +OP4 E02706 0 +OP4 E02707 0 +OP4 E02708 0 +OP4 E02709 0 +OP4 E0270A 0 +OP4 E0270B 0 +OP4 E0270C 0 +OP4 E0270D 0 +OP4 E0270E 0 +OP4 E0270F 0 +OP4 E02710 0 +OP4 E02711 0 +OP4 E02712 0 +OP4 E02713 0 +OP4 E02714 0 +OP4 E02715 0 +OP4 E02716 0 +OP4 E02717 0 +OP4 E02718 0 +OP4 E02719 0 +OP4 E0271A 0 +OP4 E0271B 0 +OP4 E0271C 0 +OP4 E0271D 0 +OP4 E0271E 0 +OP4 E0271F 0 +OP4 E02720 0 +OP4 E02721 0 +OP4 E02722 0 +OP4 E02723 0 +OP4 E02724 0 +OP4 E02725 0 +OP4 E02726 0 +OP4 E02727 0 +OP4 E02728 0 +OP4 E02729 0 +OP4 E0272A 0 +OP4 E0272B 0 +OP4 E0272C 0 +OP4 E0272D 0 +OP4 E0272E 0 +OP4 E0272F 0 +OP4 E02730 0 +OP4 E02731 0 +OP4 E02732 0 +OP4 E02733 0 +OP4 E02734 0 +OP4 E02735 0 +OP4 E02736 0 +OP4 E02737 0 +OP4 E02738 0 +OP4 E02739 0 +OP4 E0273A 0 +OP4 E0273B 0 +OP4 E0273C 0 +OP4 E0273D 0 +OP4 E0273E 0 +OP4 E0273F 0 +OP4 E02740 0 +OP4 E02741 0 +OP4 E02742 0 +OP4 E02743 0 +OP4 E02744 0 +OP4 E02745 0 +OP4 E02746 0 +OP4 E02747 0 +OP4 E02748 0 +OP4 E02749 0 +OP4 E0274A 0 +OP4 E0274B 0 +OP4 E0274C 0 +OP4 E0274D 0 +OP4 E0274E 0 +OP4 E0274F 0 +OP4 E02750 0 +OP4 E02751 0 +OP4 E02752 0 +OP4 E02753 0 +OP4 E02754 0 +OP4 E02755 0 +OP4 E02756 0 +OP4 E02757 0 +OP4 E02758 0 +OP4 E02759 0 +OP4 E0275A 0 +OP4 E0275B 0 +OP4 E0275C 0 +OP4 E0275D 0 +OP4 E0275E 0 +OP4 E0275F 0 +OP4 E02760 0 +OP4 E02761 0 +OP4 E02762 0 +OP4 E02763 0 +OP4 E02764 0 +OP4 E02765 0 +OP4 E02766 0 +OP4 E02767 0 +OP4 E02768 0 +OP4 E02769 0 +OP4 E0276A 0 +OP4 E0276B 0 +OP4 E0276C 0 +OP4 E0276D 0 +OP4 E0276E 0 +OP4 E0276F 0 +OP4 E02770 0 +OP4 E02771 0 +OP4 E02772 0 +OP4 E02773 0 +OP4 E02774 0 +OP4 E02775 0 +OP4 E02776 0 +OP4 E02777 0 +OP4 E02778 0 +OP4 E02779 0 +OP4 E0277A 0 +OP4 E0277B 0 +OP4 E0277C 0 +OP4 E0277D 0 +OP4 E0277E 0 +OP4 E0277F 0 +OP4 E02780 0 +OP4 E02781 0 +OP4 E02782 0 +OP4 E02783 0 +OP4 E02784 0 +OP4 E02785 0 +OP4 E02786 0 +OP4 E02787 0 +OP4 E02788 0 +OP4 E02789 0 +OP4 E0278A 0 +OP4 E0278B 0 +OP4 E0278C 0 +OP4 E0278D 0 +OP4 E0278E 0 +OP4 E0278F 0 +OP4 E02790 0 +OP4 E02791 0 +OP4 E02792 0 +OP4 E02793 0 +OP4 E02794 0 +OP4 E02795 0 +OP4 E02796 0 +OP4 E02797 0 +OP4 E02798 0 +OP4 E02799 0 +OP4 E0279A 0 +OP4 E0279B 0 +OP4 E0279C 0 +OP4 E0279D 0 +OP4 E0279E 0 +OP4 E0279F 0 +OP4 E027A0 0 +OP4 E027A1 0 +OP4 E027A2 0 +OP4 E027A3 0 +OP4 E027A4 0 +OP4 E027A5 0 +OP4 E027A6 0 +OP4 E027A7 0 +OP4 E027A8 0 +OP4 E027A9 0 +OP4 E027AA 0 +OP4 E027AB 0 +OP4 E027AC 0 +OP4 E027AD 0 +OP4 E027AE 0 +OP4 E027AF 0 +OP4 E027B0 0 +OP4 E027B1 0 +OP4 E027B2 0 +OP4 E027B3 0 +OP4 E027B4 0 +OP4 E027B5 0 +OP4 E027B6 0 +OP4 E027B7 0 +OP4 E027B8 0 +OP4 E027B9 0 +OP4 E027BA 0 +OP4 E027BB 0 +OP4 E027BC 0 +OP4 E027BD 0 +OP4 E027BE 0 +OP4 E027BF 0 +OP4 E027C0 0 +OP4 E027C1 0 +OP4 E027C2 0 +OP4 E027C3 0 +OP4 E027C4 0 +OP4 E027C5 0 +OP4 E027C6 0 +OP4 E027C7 0 +OP4 E027C8 0 +OP4 E027C9 0 +OP4 E027CA 0 +OP4 E027CB 0 +OP4 E027CC 0 +OP4 E027CD 0 +OP4 E027CE 0 +OP4 E027CF 0 +OP4 E027D0 0 +OP4 E027D1 0 +OP4 E027D2 0 +OP4 E027D3 0 +OP4 E027D4 0 +OP4 E027D5 0 +OP4 E027D6 0 +OP4 E027D7 0 +OP4 E027D8 0 +OP4 E027D9 0 +OP4 E027DA 0 +OP4 E027DB 0 +OP4 E027DC 0 +OP4 E027DD 0 +OP4 E027DE 0 +OP4 E027DF 0 +OP4 E027E0 0 +OP4 E027E1 0 +OP4 E027E2 0 +OP4 E027E3 0 +OP4 E027E4 0 +OP4 E027E5 0 +OP4 E027E6 0 +OP4 E027E7 0 +OP4 E027E8 0 +OP4 E027E9 0 +OP4 E027EA 0 +OP4 E027EB 0 +OP4 E027EC 0 +OP4 E027ED 0 +OP4 E027EE 0 +OP4 E027EF 0 +OP4 E027F0 0 +OP4 E027F1 0 +OP4 E027F2 0 +OP4 E027F3 0 +OP4 E027F4 0 +OP4 E027F5 0 +OP4 E027F6 0 +OP4 E027F7 0 +OP4 E027F8 0 +OP4 E027F9 0 +OP4 E027FA 0 +OP4 E027FB 0 +OP4 E027FC 0 +OP4 E027FD 0 +OP4 E027FE 0 +OP4 E027FF 0 +OP4 E02800 0 +OP4 E02801 0 +OP4 E02802 0 +OP4 E02803 0 +OP4 E02804 0 +OP4 E02805 0 +OP4 E02806 0 +OP4 E02807 0 +OP4 E02808 0 +OP4 E02809 0 +OP4 E0280A 0 +OP4 E0280B 0 +OP4 E0280C 0 +OP4 E0280D 0 +OP4 E0280E 0 +OP4 E0280F 0 +OP4 E02810 0 +OP4 E02811 0 +OP4 E02812 0 +OP4 E02813 0 +OP4 E02814 0 +OP4 E02815 0 +OP4 E02816 0 +OP4 E02817 0 +OP4 E02818 0 +OP4 E02819 0 +OP4 E0281A 0 +OP4 E0281B 0 +OP4 E0281C 0 +OP4 E0281D 0 +OP4 E0281E 0 +OP4 E0281F 0 +OP4 E02820 0 +OP4 E02821 0 +OP4 E02822 0 +OP4 E02823 0 +OP4 E02824 0 +OP4 E02825 0 +OP4 E02826 0 +OP4 E02827 0 +OP4 E02828 0 +OP4 E02829 0 +OP4 E0282A 0 +OP4 E0282B 0 +OP4 E0282C 0 +OP4 E0282D 0 +OP4 E0282E 0 +OP4 E0282F 0 +OP4 E02830 0 +OP4 E02831 0 +OP4 E02832 0 +OP4 E02833 0 +OP4 E02834 0 +OP4 E02835 0 +OP4 E02836 0 +OP4 E02837 0 +OP4 E02838 0 +OP4 E02839 0 +OP4 E0283A 0 +OP4 E0283B 0 +OP4 E0283C 0 +OP4 E0283D 0 +OP4 E0283E 0 +OP4 E0283F 0 +OP4 E02840 0 +OP4 E02841 0 +OP4 E02842 0 +OP4 E02843 0 +OP4 E02844 0 +OP4 E02845 0 +OP4 E02846 0 +OP4 E02847 0 +OP4 E02848 0 +OP4 E02849 0 +OP4 E0284A 0 +OP4 E0284B 0 +OP4 E0284C 0 +OP4 E0284D 0 +OP4 E0284E 0 +OP4 E0284F 0 +OP4 E02850 0 +OP4 E02851 0 +OP4 E02852 0 +OP4 E02853 0 +OP4 E02854 0 +OP4 E02855 0 +OP4 E02856 0 +OP4 E02857 0 +OP4 E02858 0 +OP4 E02859 0 +OP4 E0285A 0 +OP4 E0285B 0 +OP4 E0285C 0 +OP4 E0285D 0 +OP4 E0285E 0 +OP4 E0285F 0 +OP4 E02860 0 +OP4 E02861 0 +OP4 E02862 0 +OP4 E02863 0 +OP4 E02864 0 +OP4 E02865 0 +OP4 E02866 0 +OP4 E02867 0 +OP4 E02868 0 +OP4 E02869 0 +OP4 E0286A 0 +OP4 E0286B 0 +OP4 E0286C 0 +OP4 E0286D 0 +OP4 E0286E 0 +OP4 E0286F 0 +OP4 E02870 0 +OP4 E02871 0 +OP4 E02872 0 +OP4 E02873 0 +OP4 E02874 0 +OP4 E02875 0 +OP4 E02876 0 +OP4 E02877 0 +OP4 E02878 0 +OP4 E02879 0 +OP4 E0287A 0 +OP4 E0287B 0 +OP4 E0287C 0 +OP4 E0287D 0 +OP4 E0287E 0 +OP4 E0287F 0 +OP4 E02880 0 +OP4 E02881 0 +OP4 E02882 0 +OP4 E02883 0 +OP4 E02884 0 +OP4 E02885 0 +OP4 E02886 0 +OP4 E02887 0 +OP4 E02888 0 +OP4 E02889 0 +OP4 E0288A 0 +OP4 E0288B 0 +OP4 E0288C 0 +OP4 E0288D 0 +OP4 E0288E 0 +OP4 E0288F 0 +OP4 E02890 0 +OP4 E02891 0 +OP4 E02892 0 +OP4 E02893 0 +OP4 E02894 0 +OP4 E02895 0 +OP4 E02896 0 +OP4 E02897 0 +OP4 E02898 0 +OP4 E02899 0 +OP4 E0289A 0 +OP4 E0289B 0 +OP4 E0289C 0 +OP4 E0289D 0 +OP4 E0289E 0 +OP4 E0289F 0 +OP4 E028A0 0 +OP4 E028A1 0 +OP4 E028A2 0 +OP4 E028A3 0 +OP4 E028A4 0 +OP4 E028A5 0 +OP4 E028A6 0 +OP4 E028A7 0 +OP4 E028A8 0 +OP4 E028A9 0 +OP4 E028AA 0 +OP4 E028AB 0 +OP4 E028AC 0 +OP4 E028AD 0 +OP4 E028AE 0 +OP4 E028AF 0 +OP4 E028B0 0 +OP4 E028B1 0 +OP4 E028B2 0 +OP4 E028B3 0 +OP4 E028B4 0 +OP4 E028B5 0 +OP4 E028B6 0 +OP4 E028B7 0 +OP4 E028B8 0 +OP4 E028B9 0 +OP4 E028BA 0 +OP4 E028BB 0 +OP4 E028BC 0 +OP4 E028BD 0 +OP4 E028BE 0 +OP4 E028BF 0 +OP4 E028C0 0 +OP4 E028C1 0 +OP4 E028C2 0 +OP4 E028C3 0 +OP4 E028C4 0 +OP4 E028C5 0 +OP4 E028C6 0 +OP4 E028C7 0 +OP4 E028C8 0 +OP4 E028C9 0 +OP4 E028CA 0 +OP4 E028CB 0 +OP4 E028CC 0 +OP4 E028CD 0 +OP4 E028CE 0 +OP4 E028CF 0 +OP4 E028D0 0 +OP4 E028D1 0 +OP4 E028D2 0 +OP4 E028D3 0 +OP4 E028D4 0 +OP4 E028D5 0 +OP4 E028D6 0 +OP4 E028D7 0 +OP4 E028D8 0 +OP4 E028D9 0 +OP4 E028DA 0 +OP4 E028DB 0 +OP4 E028DC 0 +OP4 E028DD 0 +OP4 E028DE 0 +OP4 E028DF 0 +OP4 E028E0 0 +OP4 E028E1 0 +OP4 E028E2 0 +OP4 E028E3 0 +OP4 E028E4 0 +OP4 E028E5 0 +OP4 E028E6 0 +OP4 E028E7 0 +OP4 E028E8 0 +OP4 E028E9 0 +OP4 E028EA 0 +OP4 E028EB 0 +OP4 E028EC 0 +OP4 E028ED 0 +OP4 E028EE 0 +OP4 E028EF 0 +OP4 E028F0 0 +OP4 E028F1 0 +OP4 E028F2 0 +OP4 E028F3 0 +OP4 E028F4 0 +OP4 E028F5 0 +OP4 E028F6 0 +OP4 E028F7 0 +OP4 E028F8 0 +OP4 E028F9 0 +OP4 E028FA 0 +OP4 E028FB 0 +OP4 E028FC 0 +OP4 E028FD 0 +OP4 E028FE 0 +OP4 E028FF 0 +OP4 E02900 0 +OP4 E02901 0 +OP4 E02902 0 +OP4 E02903 0 +OP4 E02904 0 +OP4 E02905 0 +OP4 E02906 0 +OP4 E02907 0 +OP4 E02908 0 +OP4 E02909 0 +OP4 E0290A 0 +OP4 E0290B 0 +OP4 E0290C 0 +OP4 E0290D 0 +OP4 E0290E 0 +OP4 E0290F 0 +OP4 E02910 0 +OP4 E02911 0 +OP4 E02912 0 +OP4 E02913 0 +OP4 E02914 0 +OP4 E02915 0 +OP4 E02916 0 +OP4 E02917 0 +OP4 E02918 0 +OP4 E02919 0 +OP4 E0291A 0 +OP4 E0291B 0 +OP4 E0291C 0 +OP4 E0291D 0 +OP4 E0291E 0 +OP4 E0291F 0 +OP4 E02920 0 +OP4 E02921 0 +OP4 E02922 0 +OP4 E02923 0 +OP4 E02924 0 +OP4 E02925 0 +OP4 E02926 0 +OP4 E02927 0 +OP4 E02928 0 +OP4 E02929 0 +OP4 E0292A 0 +OP4 E0292B 0 +OP4 E0292C 0 +OP4 E0292D 0 +OP4 E0292E 0 +OP4 E0292F 0 +OP4 E02930 0 +OP4 E02931 0 +OP4 E02932 0 +OP4 E02933 0 +OP4 E02934 0 +OP4 E02935 0 +OP4 E02936 0 +OP4 E02937 0 +OP4 E02938 0 +OP4 E02939 0 +OP4 E0293A 0 +OP4 E0293B 0 +OP4 E0293C 0 +OP4 E0293D 0 +OP4 E0293E 0 +OP4 E0293F 0 +OP4 E02940 0 +OP4 E02941 0 +OP4 E02942 0 +OP4 E02943 0 +OP4 E02944 0 +OP4 E02945 0 +OP4 E02946 0 +OP4 E02947 0 +OP4 E02948 0 +OP4 E02949 0 +OP4 E0294A 0 +OP4 E0294B 0 +OP4 E0294C 0 +OP4 E0294D 0 +OP4 E0294E 0 +OP4 E0294F 0 +OP4 E02950 0 +OP4 E02951 0 +OP4 E02952 0 +OP4 E02953 0 +OP4 E02954 0 +OP4 E02955 0 +OP4 E02956 0 +OP4 E02957 0 +OP4 E02958 0 +OP4 E02959 0 +OP4 E0295A 0 +OP4 E0295B 0 +OP4 E0295C 0 +OP4 E0295D 0 +OP4 E0295E 0 +OP4 E0295F 0 +OP4 E02960 0 +OP4 E02961 0 +OP4 E02962 0 +OP4 E02963 0 +OP4 E02964 0 +OP4 E02965 0 +OP4 E02966 0 +OP4 E02967 0 +OP4 E02968 0 +OP4 E02969 0 +OP4 E0296A 0 +OP4 E0296B 0 +OP4 E0296C 0 +OP4 E0296D 0 +OP4 E0296E 0 +OP4 E0296F 0 +OP4 E02970 0 +OP4 E02971 0 +OP4 E02972 0 +OP4 E02973 0 +OP4 E02974 0 +OP4 E02975 0 +OP4 E02976 0 +OP4 E02977 0 +OP4 E02978 0 +OP4 E02979 0 +OP4 E0297A 0 +OP4 E0297B 0 +OP4 E0297C 0 +OP4 E0297D 0 +OP4 E0297E 0 +OP4 E0297F 0 +OP4 E02980 0 +OP4 E02981 0 +OP4 E02982 0 +OP4 E02983 0 +OP4 E02984 0 +OP4 E02985 0 +OP4 E02986 0 +OP4 E02987 0 +OP4 E02988 0 +OP4 E02989 0 +OP4 E0298A 0 +OP4 E0298B 0 +OP4 E0298C 0 +OP4 E0298D 0 +OP4 E0298E 0 +OP4 E0298F 0 +OP4 E02990 0 +OP4 E02991 0 +OP4 E02992 0 +OP4 E02993 0 +OP4 E02994 0 +OP4 E02995 0 +OP4 E02996 0 +OP4 E02997 0 +OP4 E02998 0 +OP4 E02999 0 +OP4 E0299A 0 +OP4 E0299B 0 +OP4 E0299C 0 +OP4 E0299D 0 +OP4 E0299E 0 +OP4 E0299F 0 +OP4 E029A0 0 +OP4 E029A1 0 +OP4 E029A2 0 +OP4 E029A3 0 +OP4 E029A4 0 +OP4 E029A5 0 +OP4 E029A6 0 +OP4 E029A7 0 +OP4 E029A8 0 +OP4 E029A9 0 +OP4 E029AA 0 +OP4 E029AB 0 +OP4 E029AC 0 +OP4 E029AD 0 +OP4 E029AE 0 +OP4 E029AF 0 +OP4 E029B0 0 +OP4 E029B1 0 +OP4 E029B2 0 +OP4 E029B3 0 +OP4 E029B4 0 +OP4 E029B5 0 +OP4 E029B6 0 +OP4 E029B7 0 +OP4 E029B8 0 +OP4 E029B9 0 +OP4 E029BA 0 +OP4 E029BB 0 +OP4 E029BC 0 +OP4 E029BD 0 +OP4 E029BE 0 +OP4 E029BF 0 +OP4 E029C0 0 +OP4 E029C1 0 +OP4 E029C2 0 +OP4 E029C3 0 +OP4 E029C4 0 +OP4 E029C5 0 +OP4 E029C6 0 +OP4 E029C7 0 +OP4 E029C8 0 +OP4 E029C9 0 +OP4 E029CA 0 +OP4 E029CB 0 +OP4 E029CC 0 +OP4 E029CD 0 +OP4 E029CE 0 +OP4 E029CF 0 +OP4 E029D0 0 +OP4 E029D1 0 +OP4 E029D2 0 +OP4 E029D3 0 +OP4 E029D4 0 +OP4 E029D5 0 +OP4 E029D6 0 +OP4 E029D7 0 +OP4 E029D8 0 +OP4 E029D9 0 +OP4 E029DA 0 +OP4 E029DB 0 +OP4 E029DC 0 +OP4 E029DD 0 +OP4 E029DE 0 +OP4 E029DF 0 +OP4 E029E0 0 +OP4 E029E1 0 +OP4 E029E2 0 +OP4 E029E3 0 +OP4 E029E4 0 +OP4 E029E5 0 +OP4 E029E6 0 +OP4 E029E7 0 +OP4 E029E8 0 +OP4 E029E9 0 +OP4 E029EA 0 +OP4 E029EB 0 +OP4 E029EC 0 +OP4 E029ED 0 +OP4 E029EE 0 +OP4 E029EF 0 +OP4 E029F0 0 +OP4 E029F1 0 +OP4 E029F2 0 +OP4 E029F3 0 +OP4 E029F4 0 +OP4 E029F5 0 +OP4 E029F6 0 +OP4 E029F7 0 +OP4 E029F8 0 +OP4 E029F9 0 +OP4 E029FA 0 +OP4 E029FB 0 +OP4 E029FC 0 +OP4 E029FD 0 +OP4 E029FE 0 +OP4 E029FF 0 +OP4 E02A00 0 +OP4 E02A01 0 +OP4 E02A02 0 +OP4 E02A03 0 +OP4 E02A04 0 +OP4 E02A05 0 +OP4 E02A06 0 +OP4 E02A07 0 +OP4 E02A08 0 +OP4 E02A09 0 +OP4 E02A0A 0 +OP4 E02A0B 0 +OP4 E02A0C 0 +OP4 E02A0D 0 +OP4 E02A0E 0 +OP4 E02A0F 0 +OP4 E02A10 0 +OP4 E02A11 0 +OP4 E02A12 0 +OP4 E02A13 0 +OP4 E02A14 0 +OP4 E02A15 0 +OP4 E02A16 0 +OP4 E02A17 0 +OP4 E02A18 0 +OP4 E02A19 0 +OP4 E02A1A 0 +OP4 E02A1B 0 +OP4 E02A1C 0 +OP4 E02A1D 0 +OP4 E02A1E 0 +OP4 E02A1F 0 +OP4 E02A20 0 +OP4 E02A21 0 +OP4 E02A22 0 +OP4 E02A23 0 +OP4 E02A24 0 +OP4 E02A25 0 +OP4 E02A26 0 +OP4 E02A27 0 +OP4 E02A28 0 +OP4 E02A29 0 +OP4 E02A2A 0 +OP4 E02A2B 0 +OP4 E02A2C 0 +OP4 E02A2D 0 +OP4 E02A2E 0 +OP4 E02A2F 0 +OP4 E02A30 0 +OP4 E02A31 0 +OP4 E02A32 0 +OP4 E02A33 0 +OP4 E02A34 0 +OP4 E02A35 0 +OP4 E02A36 0 +OP4 E02A37 0 +OP4 E02A38 0 +OP4 E02A39 0 +OP4 E02A3A 0 +OP4 E02A3B 0 +OP4 E02A3C 0 +OP4 E02A3D 0 +OP4 E02A3E 0 +OP4 E02A3F 0 +OP4 E02A40 0 +OP4 E02A41 0 +OP4 E02A42 0 +OP4 E02A43 0 +OP4 E02A44 0 +OP4 E02A45 0 +OP4 E02A46 0 +OP4 E02A47 0 +OP4 E02A48 0 +OP4 E02A49 0 +OP4 E02A4A 0 +OP4 E02A4B 0 +OP4 E02A4C 0 +OP4 E02A4D 0 +OP4 E02A4E 0 +OP4 E02A4F 0 +OP4 E02A50 0 +OP4 E02A51 0 +OP4 E02A52 0 +OP4 E02A53 0 +OP4 E02A54 0 +OP4 E02A55 0 +OP4 E02A56 0 +OP4 E02A57 0 +OP4 E02A58 0 +OP4 E02A59 0 +OP4 E02A5A 0 +OP4 E02A5B 0 +OP4 E02A5C 0 +OP4 E02A5D 0 +OP4 E02A5E 0 +OP4 E02A5F 0 +OP4 E02A60 0 +OP4 E02A61 0 +OP4 E02A62 0 +OP4 E02A63 0 +OP4 E02A64 0 +OP4 E02A65 0 +OP4 E02A66 0 +OP4 E02A67 0 +OP4 E02A68 0 +OP4 E02A69 0 +OP4 E02A6A 0 +OP4 E02A6B 0 +OP4 E02A6C 0 +OP4 E02A6D 0 +OP4 E02A6E 0 +OP4 E02A6F 0 +OP4 E02A70 0 +OP4 E02A71 0 +OP4 E02A72 0 +OP4 E02A73 0 +OP4 E02A74 0 +OP4 E02A75 0 +OP4 E02A76 0 +OP4 E02A77 0 +OP4 E02A78 0 +OP4 E02A79 0 +OP4 E02A7A 0 +OP4 E02A7B 0 +OP4 E02A7C 0 +OP4 E02A7D 0 +OP4 E02A7E 0 +OP4 E02A7F 0 +OP4 E02A80 0 +OP4 E02A81 0 +OP4 E02A82 0 +OP4 E02A83 0 +OP4 E02A84 0 +OP4 E02A85 0 +OP4 E02A86 0 +OP4 E02A87 0 +OP4 E02A88 0 +OP4 E02A89 0 +OP4 E02A8A 0 +OP4 E02A8B 0 +OP4 E02A8C 0 +OP4 E02A8D 0 +OP4 E02A8E 0 +OP4 E02A8F 0 +OP4 E02A90 0 +OP4 E02A91 0 +OP4 E02A92 0 +OP4 E02A93 0 +OP4 E02A94 0 +OP4 E02A95 0 +OP4 E02A96 0 +OP4 E02A97 0 +OP4 E02A98 0 +OP4 E02A99 0 +OP4 E02A9A 0 +OP4 E02A9B 0 +OP4 E02A9C 0 +OP4 E02A9D 0 +OP4 E02A9E 0 +OP4 E02A9F 0 +OP4 E02AA0 0 +OP4 E02AA1 0 +OP4 E02AA2 0 +OP4 E02AA3 0 +OP4 E02AA4 0 +OP4 E02AA5 0 +OP4 E02AA6 0 +OP4 E02AA7 0 +OP4 E02AA8 0 +OP4 E02AA9 0 +OP4 E02AAA 0 +OP4 E02AAB 0 +OP4 E02AAC 0 +OP4 E02AAD 0 +OP4 E02AAE 0 +OP4 E02AAF 0 +OP4 E02AB0 0 +OP4 E02AB1 0 +OP4 E02AB2 0 +OP4 E02AB3 0 +OP4 E02AB4 0 +OP4 E02AB5 0 +OP4 E02AB6 0 +OP4 E02AB7 0 +OP4 E02AB8 0 +OP4 E02AB9 0 +OP4 E02ABA 0 +OP4 E02ABB 0 +OP4 E02ABC 0 +OP4 E02ABD 0 +OP4 E02ABE 0 +OP4 E02ABF 0 +OP4 E02AC0 0 +OP4 E02AC1 0 +OP4 E02AC2 0 +OP4 E02AC3 0 +OP4 E02AC4 0 +OP4 E02AC5 0 +OP4 E02AC6 0 +OP4 E02AC7 0 +OP4 E02AC8 0 +OP4 E02AC9 0 +OP4 E02ACA 0 +OP4 E02ACB 0 +OP4 E02ACC 0 +OP4 E02ACD 0 +OP4 E02ACE 0 +OP4 E02ACF 0 +OP4 E02AD0 0 +OP4 E02AD1 0 +OP4 E02AD2 0 +OP4 E02AD3 0 +OP4 E02AD4 0 +OP4 E02AD5 0 +OP4 E02AD6 0 +OP4 E02AD7 0 +OP4 E02AD8 0 +OP4 E02AD9 0 +OP4 E02ADA 0 +OP4 E02ADB 0 +OP4 E02ADC 0 +OP4 E02ADD 0 +OP4 E02ADE 0 +OP4 E02ADF 0 +OP4 E02AE0 0 +OP4 E02AE1 0 +OP4 E02AE2 0 +OP4 E02AE3 0 +OP4 E02AE4 0 +OP4 E02AE5 0 +OP4 E02AE6 0 +OP4 E02AE7 0 +OP4 E02AE8 0 +OP4 E02AE9 0 +OP4 E02AEA 0 +OP4 E02AEB 0 +OP4 E02AEC 0 +OP4 E02AED 0 +OP4 E02AEE 0 +OP4 E02AEF 0 +OP4 E02AF0 0 +OP4 E02AF1 0 +OP4 E02AF2 0 +OP4 E02AF3 0 +OP4 E02AF4 0 +OP4 E02AF5 0 +OP4 E02AF6 0 +OP4 E02AF7 0 +OP4 E02AF8 0 +OP4 E02AF9 0 +OP4 E02AFA 0 +OP4 E02AFB 0 +OP4 E02AFC 0 +OP4 E02AFD 0 +OP4 E02AFE 0 +OP4 E02AFF 0 +OP4 E02B00 0 +OP4 E02B01 0 +OP4 E02B02 0 +OP4 E02B03 0 +OP4 E02B04 0 +OP4 E02B05 0 +OP4 E02B06 0 +OP4 E02B07 0 +OP4 E02B08 0 +OP4 E02B09 0 +OP4 E02B0A 0 +OP4 E02B0B 0 +OP4 E02B0C 0 +OP4 E02B0D 0 +OP4 E02B0E 0 +OP4 E02B0F 0 +OP4 E02B10 0 +OP4 E02B11 0 +OP4 E02B12 0 +OP4 E02B13 0 +OP4 E02B14 0 +OP4 E02B15 0 +OP4 E02B16 0 +OP4 E02B17 0 +OP4 E02B18 0 +OP4 E02B19 0 +OP4 E02B1A 0 +OP4 E02B1B 0 +OP4 E02B1C 0 +OP4 E02B1D 0 +OP4 E02B1E 0 +OP4 E02B1F 0 +OP4 E02B20 0 +OP4 E02B21 0 +OP4 E02B22 0 +OP4 E02B23 0 +OP4 E02B24 0 +OP4 E02B25 0 +OP4 E02B26 0 +OP4 E02B27 0 +OP4 E02B28 0 +OP4 E02B29 0 +OP4 E02B2A 0 +OP4 E02B2B 0 +OP4 E02B2C 0 +OP4 E02B2D 0 +OP4 E02B2E 0 +OP4 E02B2F 0 +OP4 E02B30 0 +OP4 E02B31 0 +OP4 E02B32 0 +OP4 E02B33 0 +OP4 E02B34 0 +OP4 E02B35 0 +OP4 E02B36 0 +OP4 E02B37 0 +OP4 E02B38 0 +OP4 E02B39 0 +OP4 E02B3A 0 +OP4 E02B3B 0 +OP4 E02B3C 0 +OP4 E02B3D 0 +OP4 E02B3E 0 +OP4 E02B3F 0 +OP4 E02B40 0 +OP4 E02B41 0 +OP4 E02B42 0 +OP4 E02B43 0 +OP4 E02B44 0 +OP4 E02B45 0 +OP4 E02B46 0 +OP4 E02B47 0 +OP4 E02B48 0 +OP4 E02B49 0 +OP4 E02B4A 0 +OP4 E02B4B 0 +OP4 E02B4C 0 +OP4 E02B4D 0 +OP4 E02B4E 0 +OP4 E02B4F 0 +OP4 E02B50 0 +OP4 E02B51 0 +OP4 E02B52 0 +OP4 E02B53 0 +OP4 E02B54 0 +OP4 E02B55 0 +OP4 E02B56 0 +OP4 E02B57 0 +OP4 E02B58 0 +OP4 E02B59 0 +OP4 E02B5A 0 +OP4 E02B5B 0 +OP4 E02B5C 0 +OP4 E02B5D 0 +OP4 E02B5E 0 +OP4 E02B5F 0 +OP4 E02B60 0 +OP4 E02B61 0 +OP4 E02B62 0 +OP4 E02B63 0 +OP4 E02B64 0 +OP4 E02B65 0 +OP4 E02B66 0 +OP4 E02B67 0 +OP4 E02B68 0 +OP4 E02B69 0 +OP4 E02B6A 0 +OP4 E02B6B 0 +OP4 E02B6C 0 +OP4 E02B6D 0 +OP4 E02B6E 0 +OP4 E02B6F 0 +OP4 E02B70 0 +OP4 E02B71 0 +OP4 E02B72 0 +OP4 E02B73 0 +OP4 E02B74 0 +OP4 E02B75 0 +OP4 E02B76 0 +OP4 E02B77 0 +OP4 E02B78 0 +OP4 E02B79 0 +OP4 E02B7A 0 +OP4 E02B7B 0 +OP4 E02B7C 0 +OP4 E02B7D 0 +OP4 E02B7E 0 +OP4 E02B7F 0 +OP4 E02B80 0 +OP4 E02B81 0 +OP4 E02B82 0 +OP4 E02B83 0 +OP4 E02B84 0 +OP4 E02B85 0 +OP4 E02B86 0 +OP4 E02B87 0 +OP4 E02B88 0 +OP4 E02B89 0 +OP4 E02B8A 0 +OP4 E02B8B 0 +OP4 E02B8C 0 +OP4 E02B8D 0 +OP4 E02B8E 0 +OP4 E02B8F 0 +OP4 E02B90 0 +OP4 E02B91 0 +OP4 E02B92 0 +OP4 E02B93 0 +OP4 E02B94 0 +OP4 E02B95 0 +OP4 E02B96 0 +OP4 E02B97 0 +OP4 E02B98 0 +OP4 E02B99 0 +OP4 E02B9A 0 +OP4 E02B9B 0 +OP4 E02B9C 0 +OP4 E02B9D 0 +OP4 E02B9E 0 +OP4 E02B9F 0 +OP4 E02BA0 0 +OP4 E02BA1 0 +OP4 E02BA2 0 +OP4 E02BA3 0 +OP4 E02BA4 0 +OP4 E02BA5 0 +OP4 E02BA6 0 +OP4 E02BA7 0 +OP4 E02BA8 0 +OP4 E02BA9 0 +OP4 E02BAA 0 +OP4 E02BAB 0 +OP4 E02BAC 0 +OP4 E02BAD 0 +OP4 E02BAE 0 +OP4 E02BAF 0 +OP4 E02BB0 0 +OP4 E02BB1 0 +OP4 E02BB2 0 +OP4 E02BB3 0 +OP4 E02BB4 0 +OP4 E02BB5 0 +OP4 E02BB6 0 +OP4 E02BB7 0 +OP4 E02BB8 0 +OP4 E02BB9 0 +OP4 E02BBA 0 +OP4 E02BBB 0 +OP4 E02BBC 0 +OP4 E02BBD 0 +OP4 E02BBE 0 +OP4 E02BBF 0 +OP4 E02BC0 0 +OP4 E02BC1 0 +OP4 E02BC2 0 +OP4 E02BC3 0 +OP4 E02BC4 0 +OP4 E02BC5 0 +OP4 E02BC6 0 +OP4 E02BC7 0 +OP4 E02BC8 0 +OP4 E02BC9 0 +OP4 E02BCA 0 +OP4 E02BCB 0 +OP4 E02BCC 0 +OP4 E02BCD 0 +OP4 E02BCE 0 +OP4 E02BCF 0 +OP4 E02BD0 0 +OP4 E02BD1 0 +OP4 E02BD2 0 +OP4 E02BD3 0 +OP4 E02BD4 0 +OP4 E02BD5 0 +OP4 E02BD6 0 +OP4 E02BD7 0 +OP4 E02BD8 0 +OP4 E02BD9 0 +OP4 E02BDA 0 +OP4 E02BDB 0 +OP4 E02BDC 0 +OP4 E02BDD 0 +OP4 E02BDE 0 +OP4 E02BDF 0 +OP4 E02BE0 0 +OP4 E02BE1 0 +OP4 E02BE2 0 +OP4 E02BE3 0 +OP4 E02BE4 0 +OP4 E02BE5 0 +OP4 E02BE6 0 +OP4 E02BE7 0 +OP4 E02BE8 0 +OP4 E02BE9 0 +OP4 E02BEA 0 +OP4 E02BEB 0 +OP4 E02BEC 0 +OP4 E02BED 0 +OP4 E02BEE 0 +OP4 E02BEF 0 +OP4 E02BF0 0 +OP4 E02BF1 0 +OP4 E02BF2 0 +OP4 E02BF3 0 +OP4 E02BF4 0 +OP4 E02BF5 0 +OP4 E02BF6 0 +OP4 E02BF7 0 +OP4 E02BF8 0 +OP4 E02BF9 0 +OP4 E02BFA 0 +OP4 E02BFB 0 +OP4 E02BFC 0 +OP4 E02BFD 0 +OP4 E02BFE 0 +OP4 E02BFF 0 +OP4 E02C00 0 +OP4 E02C01 0 +OP4 E02C02 0 +OP4 E02C03 0 +OP4 E02C04 0 +OP4 E02C05 0 +OP4 E02C06 0 +OP4 E02C07 0 +OP4 E02C08 0 +OP4 E02C09 0 +OP4 E02C0A 0 +OP4 E02C0B 0 +OP4 E02C0C 0 +OP4 E02C0D 0 +OP4 E02C0E 0 +OP4 E02C0F 0 +OP4 E02C10 0 +OP4 E02C11 0 +OP4 E02C12 0 +OP4 E02C13 0 +OP4 E02C14 0 +OP4 E02C15 0 +OP4 E02C16 0 +OP4 E02C17 0 +OP4 E02C18 0 +OP4 E02C19 0 +OP4 E02C1A 0 +OP4 E02C1B 0 +OP4 E02C1C 0 +OP4 E02C1D 0 +OP4 E02C1E 0 +OP4 E02C1F 0 +OP4 E02C20 0 +OP4 E02C21 0 +OP4 E02C22 0 +OP4 E02C23 0 +OP4 E02C24 0 +OP4 E02C25 0 +OP4 E02C26 0 +OP4 E02C27 0 +OP4 E02C28 0 +OP4 E02C29 0 +OP4 E02C2A 0 +OP4 E02C2B 0 +OP4 E02C2C 0 +OP4 E02C2D 0 +OP4 E02C2E 0 +OP4 E02C2F 0 +OP4 E02C30 0 +OP4 E02C31 0 +OP4 E02C32 0 +OP4 E02C33 0 +OP4 E02C34 0 +OP4 E02C35 0 +OP4 E02C36 0 +OP4 E02C37 0 +OP4 E02C38 0 +OP4 E02C39 0 +OP4 E02C3A 0 +OP4 E02C3B 0 +OP4 E02C3C 0 +OP4 E02C3D 0 +OP4 E02C3E 0 +OP4 E02C3F 0 +OP4 E02C40 0 +OP4 E02C41 0 +OP4 E02C42 0 +OP4 E02C43 0 +OP4 E02C44 0 +OP4 E02C45 0 +OP4 E02C46 0 +OP4 E02C47 0 +OP4 E02C48 0 +OP4 E02C49 0 +OP4 E02C4A 0 +OP4 E02C4B 0 +OP4 E02C4C 0 +OP4 E02C4D 0 +OP4 E02C4E 0 +OP4 E02C4F 0 +OP4 E02C50 0 +OP4 E02C51 0 +OP4 E02C52 0 +OP4 E02C53 0 +OP4 E02C54 0 +OP4 E02C55 0 +OP4 E02C56 0 +OP4 E02C57 0 +OP4 E02C58 0 +OP4 E02C59 0 +OP4 E02C5A 0 +OP4 E02C5B 0 +OP4 E02C5C 0 +OP4 E02C5D 0 +OP4 E02C5E 0 +OP4 E02C5F 0 +OP4 E02C60 0 +OP4 E02C61 0 +OP4 E02C62 0 +OP4 E02C63 0 +OP4 E02C64 0 +OP4 E02C65 0 +OP4 E02C66 0 +OP4 E02C67 0 +OP4 E02C68 0 +OP4 E02C69 0 +OP4 E02C6A 0 +OP4 E02C6B 0 +OP4 E02C6C 0 +OP4 E02C6D 0 +OP4 E02C6E 0 +OP4 E02C6F 0 +OP4 E02C70 0 +OP4 E02C71 0 +OP4 E02C72 0 +OP4 E02C73 0 +OP4 E02C74 0 +OP4 E02C75 0 +OP4 E02C76 0 +OP4 E02C77 0 +OP4 E02C78 0 +OP4 E02C79 0 +OP4 E02C7A 0 +OP4 E02C7B 0 +OP4 E02C7C 0 +OP4 E02C7D 0 +OP4 E02C7E 0 +OP4 E02C7F 0 +OP4 E02C80 0 +OP4 E02C81 0 +OP4 E02C82 0 +OP4 E02C83 0 +OP4 E02C84 0 +OP4 E02C85 0 +OP4 E02C86 0 +OP4 E02C87 0 +OP4 E02C88 0 +OP4 E02C89 0 +OP4 E02C8A 0 +OP4 E02C8B 0 +OP4 E02C8C 0 +OP4 E02C8D 0 +OP4 E02C8E 0 +OP4 E02C8F 0 +OP4 E02C90 0 +OP4 E02C91 0 +OP4 E02C92 0 +OP4 E02C93 0 +OP4 E02C94 0 +OP4 E02C95 0 +OP4 E02C96 0 +OP4 E02C97 0 +OP4 E02C98 0 +OP4 E02C99 0 +OP4 E02C9A 0 +OP4 E02C9B 0 +OP4 E02C9C 0 +OP4 E02C9D 0 +OP4 E02C9E 0 +OP4 E02C9F 0 +OP4 E02CA0 0 +OP4 E02CA1 0 +OP4 E02CA2 0 +OP4 E02CA3 0 +OP4 E02CA4 0 +OP4 E02CA5 0 +OP4 E02CA6 0 +OP4 E02CA7 0 +OP4 E02CA8 0 +OP4 E02CA9 0 +OP4 E02CAA 0 +OP4 E02CAB 0 +OP4 E02CAC 0 +OP4 E02CAD 0 +OP4 E02CAE 0 +OP4 E02CAF 0 +OP4 E02CB0 0 +OP4 E02CB1 0 +OP4 E02CB2 0 +OP4 E02CB3 0 +OP4 E02CB4 0 +OP4 E02CB5 0 +OP4 E02CB6 0 +OP4 E02CB7 0 +OP4 E02CB8 0 +OP4 E02CB9 0 +OP4 E02CBA 0 +OP4 E02CBB 0 +OP4 E02CBC 0 +OP4 E02CBD 0 +OP4 E02CBE 0 +OP4 E02CBF 0 +OP4 E02CC0 0 +OP4 E02CC1 0 +OP4 E02CC2 0 +OP4 E02CC3 0 +OP4 E02CC4 0 +OP4 E02CC5 0 +OP4 E02CC6 0 +OP4 E02CC7 0 +OP4 E02CC8 0 +OP4 E02CC9 0 +OP4 E02CCA 0 +OP4 E02CCB 0 +OP4 E02CCC 0 +OP4 E02CCD 0 +OP4 E02CCE 0 +OP4 E02CCF 0 +OP4 E02CD0 0 +OP4 E02CD1 0 +OP4 E02CD2 0 +OP4 E02CD3 0 +OP4 E02CD4 0 +OP4 E02CD5 0 +OP4 E02CD6 0 +OP4 E02CD7 0 +OP4 E02CD8 0 +OP4 E02CD9 0 +OP4 E02CDA 0 +OP4 E02CDB 0 +OP4 E02CDC 0 +OP4 E02CDD 0 +OP4 E02CDE 0 +OP4 E02CDF 0 +OP4 E02CE0 0 +OP4 E02CE1 0 +OP4 E02CE2 0 +OP4 E02CE3 0 +OP4 E02CE4 0 +OP4 E02CE5 0 +OP4 E02CE6 0 +OP4 E02CE7 0 +OP4 E02CE8 0 +OP4 E02CE9 0 +OP4 E02CEA 0 +OP4 E02CEB 0 +OP4 E02CEC 0 +OP4 E02CED 0 +OP4 E02CEE 0 +OP4 E02CEF 0 +OP4 E02CF0 0 +OP4 E02CF1 0 +OP4 E02CF2 0 +OP4 E02CF3 0 +OP4 E02CF4 0 +OP4 E02CF5 0 +OP4 E02CF6 0 +OP4 E02CF7 0 +OP4 E02CF8 0 +OP4 E02CF9 0 +OP4 E02CFA 0 +OP4 E02CFB 0 +OP4 E02CFC 0 +OP4 E02CFD 0 +OP4 E02CFE 0 +OP4 E02CFF 0 +OP4 E02D00 0 +OP4 E02D01 0 +OP4 E02D02 0 +OP4 E02D03 0 +OP4 E02D04 0 +OP4 E02D05 0 +OP4 E02D06 0 +OP4 E02D07 0 +OP4 E02D08 0 +OP4 E02D09 0 +OP4 E02D0A 0 +OP4 E02D0B 0 +OP4 E02D0C 0 +OP4 E02D0D 0 +OP4 E02D0E 0 +OP4 E02D0F 0 +OP4 E02D10 0 +OP4 E02D11 0 +OP4 E02D12 0 +OP4 E02D13 0 +OP4 E02D14 0 +OP4 E02D15 0 +OP4 E02D16 0 +OP4 E02D17 0 +OP4 E02D18 0 +OP4 E02D19 0 +OP4 E02D1A 0 +OP4 E02D1B 0 +OP4 E02D1C 0 +OP4 E02D1D 0 +OP4 E02D1E 0 +OP4 E02D1F 0 +OP4 E02D20 0 +OP4 E02D21 0 +OP4 E02D22 0 +OP4 E02D23 0 +OP4 E02D24 0 +OP4 E02D25 0 +OP4 E02D26 0 +OP4 E02D27 0 +OP4 E02D28 0 +OP4 E02D29 0 +OP4 E02D2A 0 +OP4 E02D2B 0 +OP4 E02D2C 0 +OP4 E02D2D 0 +OP4 E02D2E 0 +OP4 E02D2F 0 +OP4 E02D30 0 +OP4 E02D31 0 +OP4 E02D32 0 +OP4 E02D33 0 +OP4 E02D34 0 +OP4 E02D35 0 +OP4 E02D36 0 +OP4 E02D37 0 +OP4 E02D38 0 +OP4 E02D39 0 +OP4 E02D3A 0 +OP4 E02D3B 0 +OP4 E02D3C 0 +OP4 E02D3D 0 +OP4 E02D3E 0 +OP4 E02D3F 0 +OP4 E02D40 0 +OP4 E02D41 0 +OP4 E02D42 0 +OP4 E02D43 0 +OP4 E02D44 0 +OP4 E02D45 0 +OP4 E02D46 0 +OP4 E02D47 0 +OP4 E02D48 0 +OP4 E02D49 0 +OP4 E02D4A 0 +OP4 E02D4B 0 +OP4 E02D4C 0 +OP4 E02D4D 0 +OP4 E02D4E 0 +OP4 E02D4F 0 +OP4 E02D50 0 +OP4 E02D51 0 +OP4 E02D52 0 +OP4 E02D53 0 +OP4 E02D54 0 +OP4 E02D55 0 +OP4 E02D56 0 +OP4 E02D57 0 +OP4 E02D58 0 +OP4 E02D59 0 +OP4 E02D5A 0 +OP4 E02D5B 0 +OP4 E02D5C 0 +OP4 E02D5D 0 +OP4 E02D5E 0 +OP4 E02D5F 0 +OP4 E02D60 0 +OP4 E02D61 0 +OP4 E02D62 0 +OP4 E02D63 0 +OP4 E02D64 0 +OP4 E02D65 0 +OP4 E02D66 0 +OP4 E02D67 0 +OP4 E02D68 0 +OP4 E02D69 0 +OP4 E02D6A 0 +OP4 E02D6B 0 +OP4 E02D6C 0 +OP4 E02D6D 0 +OP4 E02D6E 0 +OP4 E02D6F 0 +OP4 E02D70 0 +OP4 E02D71 0 +OP4 E02D72 0 +OP4 E02D73 0 +OP4 E02D74 0 +OP4 E02D75 0 +OP4 E02D76 0 +OP4 E02D77 0 +OP4 E02D78 0 +OP4 E02D79 0 +OP4 E02D7A 0 +OP4 E02D7B 0 +OP4 E02D7C 0 +OP4 E02D7D 0 +OP4 E02D7E 0 +OP4 E02D7F 0 +OP4 E02D80 0 +OP4 E02D81 0 +OP4 E02D82 0 +OP4 E02D83 0 +OP4 E02D84 0 +OP4 E02D85 0 +OP4 E02D86 0 +OP4 E02D87 0 +OP4 E02D88 0 +OP4 E02D89 0 +OP4 E02D8A 0 +OP4 E02D8B 0 +OP4 E02D8C 0 +OP4 E02D8D 0 +OP4 E02D8E 0 +OP4 E02D8F 0 +OP4 E02D90 0 +OP4 E02D91 0 +OP4 E02D92 0 +OP4 E02D93 0 +OP4 E02D94 0 +OP4 E02D95 0 +OP4 E02D96 0 +OP4 E02D97 0 +OP4 E02D98 0 +OP4 E02D99 0 +OP4 E02D9A 0 +OP4 E02D9B 0 +OP4 E02D9C 0 +OP4 E02D9D 0 +OP4 E02D9E 0 +OP4 E02D9F 0 +OP4 E02DA0 0 +OP4 E02DA1 0 +OP4 E02DA2 0 +OP4 E02DA3 0 +OP4 E02DA4 0 +OP4 E02DA5 0 +OP4 E02DA6 0 +OP4 E02DA7 0 +OP4 E02DA8 0 +OP4 E02DA9 0 +OP4 E02DAA 0 +OP4 E02DAB 0 +OP4 E02DAC 0 +OP4 E02DAD 0 +OP4 E02DAE 0 +OP4 E02DAF 0 +OP4 E02DB0 0 +OP4 E02DB1 0 +OP4 E02DB2 0 +OP4 E02DB3 0 +OP4 E02DB4 0 +OP4 E02DB5 0 +OP4 E02DB6 0 +OP4 E02DB7 0 +OP4 E02DB8 0 +OP4 E02DB9 0 +OP4 E02DBA 0 +OP4 E02DBB 0 +OP4 E02DBC 0 +OP4 E02DBD 0 +OP4 E02DBE 0 +OP4 E02DBF 0 +OP4 E02DC0 0 +OP4 E02DC1 0 +OP4 E02DC2 0 +OP4 E02DC3 0 +OP4 E02DC4 0 +OP4 E02DC5 0 +OP4 E02DC6 0 +OP4 E02DC7 0 +OP4 E02DC8 0 +OP4 E02DC9 0 +OP4 E02DCA 0 +OP4 E02DCB 0 +OP4 E02DCC 0 +OP4 E02DCD 0 +OP4 E02DCE 0 +OP4 E02DCF 0 +OP4 E02DD0 0 +OP4 E02DD1 0 +OP4 E02DD2 0 +OP4 E02DD3 0 +OP4 E02DD4 0 +OP4 E02DD5 0 +OP4 E02DD6 0 +OP4 E02DD7 0 +OP4 E02DD8 0 +OP4 E02DD9 0 +OP4 E02DDA 0 +OP4 E02DDB 0 +OP4 E02DDC 0 +OP4 E02DDD 0 +OP4 E02DDE 0 +OP4 E02DDF 0 +OP4 E02DE0 0 +OP4 E02DE1 0 +OP4 E02DE2 0 +OP4 E02DE3 0 +OP4 E02DE4 0 +OP4 E02DE5 0 +OP4 E02DE6 0 +OP4 E02DE7 0 +OP4 E02DE8 0 +OP4 E02DE9 0 +OP4 E02DEA 0 +OP4 E02DEB 0 +OP4 E02DEC 0 +OP4 E02DED 0 +OP4 E02DEE 0 +OP4 E02DEF 0 +OP4 E02DF0 0 +OP4 E02DF1 0 +OP4 E02DF2 0 +OP4 E02DF3 0 +OP4 E02DF4 0 +OP4 E02DF5 0 +OP4 E02DF6 0 +OP4 E02DF7 0 +OP4 E02DF8 0 +OP4 E02DF9 0 +OP4 E02DFA 0 +OP4 E02DFB 0 +OP4 E02DFC 0 +OP4 E02DFD 0 +OP4 E02DFE 0 +OP4 E02DFF 0 +OP4 E02E00 0 +OP4 E02E01 0 +OP4 E02E02 0 +OP4 E02E03 0 +OP4 E02E04 0 +OP4 E02E05 0 +OP4 E02E06 0 +OP4 E02E07 0 +OP4 E02E08 0 +OP4 E02E09 0 +OP4 E02E0A 0 +OP4 E02E0B 0 +OP4 E02E0C 0 +OP4 E02E0D 0 +OP4 E02E0E 0 +OP4 E02E0F 0 +OP4 E02E10 0 +OP4 E02E11 0 +OP4 E02E12 0 +OP4 E02E13 0 +OP4 E02E14 0 +OP4 E02E15 0 +OP4 E02E16 0 +OP4 E02E17 0 +OP4 E02E18 0 +OP4 E02E19 0 +OP4 E02E1A 0 +OP4 E02E1B 0 +OP4 E02E1C 0 +OP4 E02E1D 0 +OP4 E02E1E 0 +OP4 E02E1F 0 +OP4 E02E20 0 +OP4 E02E21 0 +OP4 E02E22 0 +OP4 E02E23 0 +OP4 E02E24 0 +OP4 E02E25 0 +OP4 E02E26 0 +OP4 E02E27 0 +OP4 E02E28 0 +OP4 E02E29 0 +OP4 E02E2A 0 +OP4 E02E2B 0 +OP4 E02E2C 0 +OP4 E02E2D 0 +OP4 E02E2E 0 +OP4 E02E2F 0 +OP4 E02E30 0 +OP4 E02E31 0 +OP4 E02E32 0 +OP4 E02E33 0 +OP4 E02E34 0 +OP4 E02E35 0 +OP4 E02E36 0 +OP4 E02E37 0 +OP4 E02E38 0 +OP4 E02E39 0 +OP4 E02E3A 0 +OP4 E02E3B 0 +OP4 E02E3C 0 +OP4 E02E3D 0 +OP4 E02E3E 0 +OP4 E02E3F 0 +OP4 E02E40 0 +OP4 E02E41 0 +OP4 E02E42 0 +OP4 E02E43 0 +OP4 E02E44 0 +OP4 E02E45 0 +OP4 E02E46 0 +OP4 E02E47 0 +OP4 E02E48 0 +OP4 E02E49 0 +OP4 E02E4A 0 +OP4 E02E4B 0 +OP4 E02E4C 0 +OP4 E02E4D 0 +OP4 E02E4E 0 +OP4 E02E4F 0 +OP4 E02E50 0 +OP4 E02E51 0 +OP4 E02E52 0 +OP4 E02E53 0 +OP4 E02E54 0 +OP4 E02E55 0 +OP4 E02E56 0 +OP4 E02E57 0 +OP4 E02E58 0 +OP4 E02E59 0 +OP4 E02E5A 0 +OP4 E02E5B 0 +OP4 E02E5C 0 +OP4 E02E5D 0 +OP4 E02E5E 0 +OP4 E02E5F 0 +OP4 E02E60 0 +OP4 E02E61 0 +OP4 E02E62 0 +OP4 E02E63 0 +OP4 E02E64 0 +OP4 E02E65 0 +OP4 E02E66 0 +OP4 E02E67 0 +OP4 E02E68 0 +OP4 E02E69 0 +OP4 E02E6A 0 +OP4 E02E6B 0 +OP4 E02E6C 0 +OP4 E02E6D 0 +OP4 E02E6E 0 +OP4 E02E6F 0 +OP4 E02E70 0 +OP4 E02E71 0 +OP4 E02E72 0 +OP4 E02E73 0 +OP4 E02E74 0 +OP4 E02E75 0 +OP4 E02E76 0 +OP4 E02E77 0 +OP4 E02E78 0 +OP4 E02E79 0 +OP4 E02E7A 0 +OP4 E02E7B 0 +OP4 E02E7C 0 +OP4 E02E7D 0 +OP4 E02E7E 0 +OP4 E02E7F 0 +OP4 E02E80 0 +OP4 E02E81 0 +OP4 E02E82 0 +OP4 E02E83 0 +OP4 E02E84 0 +OP4 E02E85 0 +OP4 E02E86 0 +OP4 E02E87 0 +OP4 E02E88 0 +OP4 E02E89 0 +OP4 E02E8A 0 +OP4 E02E8B 0 +OP4 E02E8C 0 +OP4 E02E8D 0 +OP4 E02E8E 0 +OP4 E02E8F 0 +OP4 E02E90 0 +OP4 E02E91 0 +OP4 E02E92 0 +OP4 E02E93 0 +OP4 E02E94 0 +OP4 E02E95 0 +OP4 E02E96 0 +OP4 E02E97 0 +OP4 E02E98 0 +OP4 E02E99 0 +OP4 E02E9A 0 +OP4 E02E9B 0 +OP4 E02E9C 0 +OP4 E02E9D 0 +OP4 E02E9E 0 +OP4 E02E9F 0 +OP4 E02EA0 0 +OP4 E02EA1 0 +OP4 E02EA2 0 +OP4 E02EA3 0 +OP4 E02EA4 0 +OP4 E02EA5 0 +OP4 E02EA6 0 +OP4 E02EA7 0 +OP4 E02EA8 0 +OP4 E02EA9 0 +OP4 E02EAA 0 +OP4 E02EAB 0 +OP4 E02EAC 0 +OP4 E02EAD 0 +OP4 E02EAE 0 +OP4 E02EAF 0 +OP4 E02EB0 0 +OP4 E02EB1 0 +OP4 E02EB2 0 +OP4 E02EB3 0 +OP4 E02EB4 0 +OP4 E02EB5 0 +OP4 E02EB6 0 +OP4 E02EB7 0 +OP4 E02EB8 0 +OP4 E02EB9 0 +OP4 E02EBA 0 +OP4 E02EBB 0 +OP4 E02EBC 0 +OP4 E02EBD 0 +OP4 E02EBE 0 +OP4 E02EBF 0 +OP4 E02EC0 0 +OP4 E02EC1 0 +OP4 E02EC2 0 +OP4 E02EC3 0 +OP4 E02EC4 0 +OP4 E02EC5 0 +OP4 E02EC6 0 +OP4 E02EC7 0 +OP4 E02EC8 0 +OP4 E02EC9 0 +OP4 E02ECA 0 +OP4 E02ECB 0 +OP4 E02ECC 0 +OP4 E02ECD 0 +OP4 E02ECE 0 +OP4 E02ECF 0 +OP4 E02ED0 0 +OP4 E02ED1 0 +OP4 E02ED2 0 +OP4 E02ED3 0 +OP4 E02ED4 0 +OP4 E02ED5 0 +OP4 E02ED6 0 +OP4 E02ED7 0 +OP4 E02ED8 0 +OP4 E02ED9 0 +OP4 E02EDA 0 +OP4 E02EDB 0 +OP4 E02EDC 0 +OP4 E02EDD 0 +OP4 E02EDE 0 +OP4 E02EDF 0 +OP4 E02EE0 0 +OP4 E02EE1 0 +OP4 E02EE2 0 +OP4 E02EE3 0 +OP4 E02EE4 0 +OP4 E02EE5 0 +OP4 E02EE6 0 +OP4 E02EE7 0 +OP4 E02EE8 0 +OP4 E02EE9 0 +OP4 E02EEA 0 +OP4 E02EEB 0 +OP4 E02EEC 0 +OP4 E02EED 0 +OP4 E02EEE 0 +OP4 E02EEF 0 +OP4 E02EF0 0 +OP4 E02EF1 0 +OP4 E02EF2 0 +OP4 E02EF3 0 +OP4 E02EF4 0 +OP4 E02EF5 0 +OP4 E02EF6 0 +OP4 E02EF7 0 +OP4 E02EF8 0 +OP4 E02EF9 0 +OP4 E02EFA 0 +OP4 E02EFB 0 +OP4 E02EFC 0 +OP4 E02EFD 0 +OP4 E02EFE 0 +OP4 E02EFF 0 +OP4 E02F00 0 +OP4 E02F01 0 +OP4 E02F02 0 +OP4 E02F03 0 +OP4 E02F04 0 +OP4 E02F05 0 +OP4 E02F06 0 +OP4 E02F07 0 +OP4 E02F08 0 +OP4 E02F09 0 +OP4 E02F0A 0 +OP4 E02F0B 0 +OP4 E02F0C 0 +OP4 E02F0D 0 +OP4 E02F0E 0 +OP4 E02F0F 0 +OP4 E02F10 0 +OP4 E02F11 0 +OP4 E02F12 0 +OP4 E02F13 0 +OP4 E02F14 0 +OP4 E02F15 0 +OP4 E02F16 0 +OP4 E02F17 0 +OP4 E02F18 0 +OP4 E02F19 0 +OP4 E02F1A 0 +OP4 E02F1B 0 +OP4 E02F1C 0 +OP4 E02F1D 0 +OP4 E02F1E 0 +OP4 E02F1F 0 +OP4 E02F20 0 +OP4 E02F21 0 +OP4 E02F22 0 +OP4 E02F23 0 +OP4 E02F24 0 +OP4 E02F25 0 +OP4 E02F26 0 +OP4 E02F27 0 +OP4 E02F28 0 +OP4 E02F29 0 +OP4 E02F2A 0 +OP4 E02F2B 0 +OP4 E02F2C 0 +OP4 E02F2D 0 +OP4 E02F2E 0 +OP4 E02F2F 0 +OP4 E02F30 0 +OP4 E02F31 0 +OP4 E02F32 0 +OP4 E02F33 0 +OP4 E02F34 0 +OP4 E02F35 0 +OP4 E02F36 0 +OP4 E02F37 0 +OP4 E02F38 0 +OP4 E02F39 0 +OP4 E02F3A 0 +OP4 E02F3B 0 +OP4 E02F3C 0 +OP4 E02F3D 0 +OP4 E02F3E 0 +OP4 E02F3F 0 +OP4 E02F40 0 +OP4 E02F41 0 +OP4 E02F42 0 +OP4 E02F43 0 +OP4 E02F44 0 +OP4 E02F45 0 +OP4 E02F46 0 +OP4 E02F47 0 +OP4 E02F48 0 +OP4 E02F49 0 +OP4 E02F4A 0 +OP4 E02F4B 0 +OP4 E02F4C 0 +OP4 E02F4D 0 +OP4 E02F4E 0 +OP4 E02F4F 0 +OP4 E02F50 0 +OP4 E02F51 0 +OP4 E02F52 0 +OP4 E02F53 0 +OP4 E02F54 0 +OP4 E02F55 0 +OP4 E02F56 0 +OP4 E02F57 0 +OP4 E02F58 0 +OP4 E02F59 0 +OP4 E02F5A 0 +OP4 E02F5B 0 +OP4 E02F5C 0 +OP4 E02F5D 0 +OP4 E02F5E 0 +OP4 E02F5F 0 +OP4 E02F60 0 +OP4 E02F61 0 +OP4 E02F62 0 +OP4 E02F63 0 +OP4 E02F64 0 +OP4 E02F65 0 +OP4 E02F66 0 +OP4 E02F67 0 +OP4 E02F68 0 +OP4 E02F69 0 +OP4 E02F6A 0 +OP4 E02F6B 0 +OP4 E02F6C 0 +OP4 E02F6D 0 +OP4 E02F6E 0 +OP4 E02F6F 0 +OP4 E02F70 0 +OP4 E02F71 0 +OP4 E02F72 0 +OP4 E02F73 0 +OP4 E02F74 0 +OP4 E02F75 0 +OP4 E02F76 0 +OP4 E02F77 0 +OP4 E02F78 0 +OP4 E02F79 0 +OP4 E02F7A 0 +OP4 E02F7B 0 +OP4 E02F7C 0 +OP4 E02F7D 0 +OP4 E02F7E 0 +OP4 E02F7F 0 +OP4 E02F80 0 +OP4 E02F81 0 +OP4 E02F82 0 +OP4 E02F83 0 +OP4 E02F84 0 +OP4 E02F85 0 +OP4 E02F86 0 +OP4 E02F87 0 +OP4 E02F88 0 +OP4 E02F89 0 +OP4 E02F8A 0 +OP4 E02F8B 0 +OP4 E02F8C 0 +OP4 E02F8D 0 +OP4 E02F8E 0 +OP4 E02F8F 0 +OP4 E02F90 0 +OP4 E02F91 0 +OP4 E02F92 0 +OP4 E02F93 0 +OP4 E02F94 0 +OP4 E02F95 0 +OP4 E02F96 0 +OP4 E02F97 0 +OP4 E02F98 0 +OP4 E02F99 0 +OP4 E02F9A 0 +OP4 E02F9B 0 +OP4 E02F9C 0 +OP4 E02F9D 0 +OP4 E02F9E 0 +OP4 E02F9F 0 +OP4 E02FA0 0 +OP4 E02FA1 0 +OP4 E02FA2 0 +OP4 E02FA3 0 +OP4 E02FA4 0 +OP4 E02FA5 0 +OP4 E02FA6 0 +OP4 E02FA7 0 +OP4 E02FA8 0 +OP4 E02FA9 0 +OP4 E02FAA 0 +OP4 E02FAB 0 +OP4 E02FAC 0 +OP4 E02FAD 0 +OP4 E02FAE 0 +OP4 E02FAF 0 +OP4 E02FB0 0 +OP4 E02FB1 0 +OP4 E02FB2 0 +OP4 E02FB3 0 +OP4 E02FB4 0 +OP4 E02FB5 0 +OP4 E02FB6 0 +OP4 E02FB7 0 +OP4 E02FB8 0 +OP4 E02FB9 0 +OP4 E02FBA 0 +OP4 E02FBB 0 +OP4 E02FBC 0 +OP4 E02FBD 0 +OP4 E02FBE 0 +OP4 E02FBF 0 +OP4 E02FC0 0 +OP4 E02FC1 0 +OP4 E02FC2 0 +OP4 E02FC3 0 +OP4 E02FC4 0 +OP4 E02FC5 0 +OP4 E02FC6 0 +OP4 E02FC7 0 +OP4 E02FC8 0 +OP4 E02FC9 0 +OP4 E02FCA 0 +OP4 E02FCB 0 +OP4 E02FCC 0 +OP4 E02FCD 0 +OP4 E02FCE 0 +OP4 E02FCF 0 +OP4 E02FD0 0 +OP4 E02FD1 0 +OP4 E02FD2 0 +OP4 E02FD3 0 +OP4 E02FD4 0 +OP4 E02FD5 0 +OP4 E02FD6 0 +OP4 E02FD7 0 +OP4 E02FD8 0 +OP4 E02FD9 0 +OP4 E02FDA 0 +OP4 E02FDB 0 +OP4 E02FDC 0 +OP4 E02FDD 0 +OP4 E02FDE 0 +OP4 E02FDF 0 +OP4 E02FE0 0 +OP4 E02FE1 0 +OP4 E02FE2 0 +OP4 E02FE3 0 +OP4 E02FE4 0 +OP4 E02FE5 0 +OP4 E02FE6 0 +OP4 E02FE7 0 +OP4 E02FE8 0 +OP4 E02FE9 0 +OP4 E02FEA 0 +OP4 E02FEB 0 +OP4 E02FEC 0 +OP4 E02FED 0 +OP4 E02FEE 0 +OP4 E02FEF 0 +OP4 E02FF0 0 +OP4 E02FF1 0 +OP4 E02FF2 0 +OP4 E02FF3 0 +OP4 E02FF4 0 +OP4 E02FF5 0 +OP4 E02FF6 0 +OP4 E02FF7 0 +OP4 E02FF8 0 +OP4 E02FF9 0 +OP4 E02FFA 0 +OP4 E02FFB 0 +OP4 E02FFC 0 +OP4 E02FFD 0 +OP4 E02FFE 0 +OP4 E02FFF 0 +OP4 E03000 0 +OP4 E03001 0 +OP4 E03002 0 +OP4 E03003 0 +OP4 E03004 0 +OP4 E03005 0 +OP4 E03006 0 +OP4 E03007 0 +OP4 E03008 0 +OP4 E03009 0 +OP4 E0300A 0 +OP4 E0300B 0 +OP4 E0300C 0 +OP4 E0300D 0 +OP4 E0300E 0 +OP4 E0300F 0 +OP4 E03010 0 +OP4 E03011 0 +OP4 E03012 0 +OP4 E03013 0 +OP4 E03014 0 +OP4 E03015 0 +OP4 E03016 0 +OP4 E03017 0 +OP4 E03018 0 +OP4 E03019 0 +OP4 E0301A 0 +OP4 E0301B 0 +OP4 E0301C 0 +OP4 E0301D 0 +OP4 E0301E 0 +OP4 E0301F 0 +OP4 E03020 0 +OP4 E03021 0 +OP4 E03022 0 +OP4 E03023 0 +OP4 E03024 0 +OP4 E03025 0 +OP4 E03026 0 +OP4 E03027 0 +OP4 E03028 0 +OP4 E03029 0 +OP4 E0302A 0 +OP4 E0302B 0 +OP4 E0302C 0 +OP4 E0302D 0 +OP4 E0302E 0 +OP4 E0302F 0 +OP4 E03030 0 +OP4 E03031 0 +OP4 E03032 0 +OP4 E03033 0 +OP4 E03034 0 +OP4 E03035 0 +OP4 E03036 0 +OP4 E03037 0 +OP4 E03038 0 +OP4 E03039 0 +OP4 E0303A 0 +OP4 E0303B 0 +OP4 E0303C 0 +OP4 E0303D 0 +OP4 E0303E 0 +OP4 E0303F 0 +OP4 E03040 0 +OP4 E03041 0 +OP4 E03042 0 +OP4 E03043 0 +OP4 E03044 0 +OP4 E03045 0 +OP4 E03046 0 +OP4 E03047 0 +OP4 E03048 0 +OP4 E03049 0 +OP4 E0304A 0 +OP4 E0304B 0 +OP4 E0304C 0 +OP4 E0304D 0 +OP4 E0304E 0 +OP4 E0304F 0 +OP4 E03050 0 +OP4 E03051 0 +OP4 E03052 0 +OP4 E03053 0 +OP4 E03054 0 +OP4 E03055 0 +OP4 E03056 0 +OP4 E03057 0 +OP4 E03058 0 +OP4 E03059 0 +OP4 E0305A 0 +OP4 E0305B 0 +OP4 E0305C 0 +OP4 E0305D 0 +OP4 E0305E 0 +OP4 E0305F 0 +OP4 E03060 0 +OP4 E03061 0 +OP4 E03062 0 +OP4 E03063 0 +OP4 E03064 0 +OP4 E03065 0 +OP4 E03066 0 +OP4 E03067 0 +OP4 E03068 0 +OP4 E03069 0 +OP4 E0306A 0 +OP4 E0306B 0 +OP4 E0306C 0 +OP4 E0306D 0 +OP4 E0306E 0 +OP4 E0306F 0 +OP4 E03070 0 +OP4 E03071 0 +OP4 E03072 0 +OP4 E03073 0 +OP4 E03074 0 +OP4 E03075 0 +OP4 E03076 0 +OP4 E03077 0 +OP4 E03078 0 +OP4 E03079 0 +OP4 E0307A 0 +OP4 E0307B 0 +OP4 E0307C 0 +OP4 E0307D 0 +OP4 E0307E 0 +OP4 E0307F 0 +OP4 E03080 0 +OP4 E03081 0 +OP4 E03082 0 +OP4 E03083 0 +OP4 E03084 0 +OP4 E03085 0 +OP4 E03086 0 +OP4 E03087 0 +OP4 E03088 0 +OP4 E03089 0 +OP4 E0308A 0 +OP4 E0308B 0 +OP4 E0308C 0 +OP4 E0308D 0 +OP4 E0308E 0 +OP4 E0308F 0 +OP4 E03090 0 +OP4 E03091 0 +OP4 E03092 0 +OP4 E03093 0 +OP4 E03094 0 +OP4 E03095 0 +OP4 E03096 0 +OP4 E03097 0 +OP4 E03098 0 +OP4 E03099 0 +OP4 E0309A 0 +OP4 E0309B 0 +OP4 E0309C 0 +OP4 E0309D 0 +OP4 E0309E 0 +OP4 E0309F 0 +OP4 E030A0 0 +OP4 E030A1 0 +OP4 E030A2 0 +OP4 E030A3 0 +OP4 E030A4 0 +OP4 E030A5 0 +OP4 E030A6 0 +OP4 E030A7 0 +OP4 E030A8 0 +OP4 E030A9 0 +OP4 E030AA 0 +OP4 E030AB 0 +OP4 E030AC 0 +OP4 E030AD 0 +OP4 E030AE 0 +OP4 E030AF 0 +OP4 E030B0 0 +OP4 E030B1 0 +OP4 E030B2 0 +OP4 E030B3 0 +OP4 E030B4 0 +OP4 E030B5 0 +OP4 E030B6 0 +OP4 E030B7 0 +OP4 E030B8 0 +OP4 E030B9 0 +OP4 E030BA 0 +OP4 E030BB 0 +OP4 E030BC 0 +OP4 E030BD 0 +OP4 E030BE 0 +OP4 E030BF 0 +OP4 E030C0 0 +OP4 E030C1 0 +OP4 E030C2 0 +OP4 E030C3 0 +OP4 E030C4 0 +OP4 E030C5 0 +OP4 E030C6 0 +OP4 E030C7 0 +OP4 E030C8 0 +OP4 E030C9 0 +OP4 E030CA 0 +OP4 E030CB 0 +OP4 E030CC 0 +OP4 E030CD 0 +OP4 E030CE 0 +OP4 E030CF 0 +OP4 E030D0 0 +OP4 E030D1 0 +OP4 E030D2 0 +OP4 E030D3 0 +OP4 E030D4 0 +OP4 E030D5 0 +OP4 E030D6 0 +OP4 E030D7 0 +OP4 E030D8 0 +OP4 E030D9 0 +OP4 E030DA 0 +OP4 E030DB 0 +OP4 E030DC 0 +OP4 E030DD 0 +OP4 E030DE 0 +OP4 E030DF 0 +OP4 E030E0 0 +OP4 E030E1 0 +OP4 E030E2 0 +OP4 E030E3 0 +OP4 E030E4 0 +OP4 E030E5 0 +OP4 E030E6 0 +OP4 E030E7 0 +OP4 E030E8 0 +OP4 E030E9 0 +OP4 E030EA 0 +OP4 E030EB 0 +OP4 E030EC 0 +OP4 E030ED 0 +OP4 E030EE 0 +OP4 E030EF 0 +OP4 E030F0 0 +OP4 E030F1 0 +OP4 E030F2 0 +OP4 E030F3 0 +OP4 E030F4 0 +OP4 E030F5 0 +OP4 E030F6 0 +OP4 E030F7 0 +OP4 E030F8 0 +OP4 E030F9 0 +OP4 E030FA 0 +OP4 E030FB 0 +OP4 E030FC 0 +OP4 E030FD 0 +OP4 E030FE 0 +OP4 E030FF 0 +OP4 E03100 0 +OP4 E03101 0 +OP4 E03102 0 +OP4 E03103 0 +OP4 E03104 0 +OP4 E03105 0 +OP4 E03106 0 +OP4 E03107 0 +OP4 E03108 0 +OP4 E03109 0 +OP4 E0310A 0 +OP4 E0310B 0 +OP4 E0310C 0 +OP4 E0310D 0 +OP4 E0310E 0 +OP4 E0310F 0 +OP4 E03110 0 +OP4 E03111 0 +OP4 E03112 0 +OP4 E03113 0 +OP4 E03114 0 +OP4 E03115 0 +OP4 E03116 0 +OP4 E03117 0 +OP4 E03118 0 +OP4 E03119 0 +OP4 E0311A 0 +OP4 E0311B 0 +OP4 E0311C 0 +OP4 E0311D 0 +OP4 E0311E 0 +OP4 E0311F 0 +OP4 E03120 0 +OP4 E03121 0 +OP4 E03122 0 +OP4 E03123 0 +OP4 E03124 0 +OP4 E03125 0 +OP4 E03126 0 +OP4 E03127 0 +OP4 E03128 0 +OP4 E03129 0 +OP4 E0312A 0 +OP4 E0312B 0 +OP4 E0312C 0 +OP4 E0312D 0 +OP4 E0312E 0 +OP4 E0312F 0 +OP4 E03130 0 +OP4 E03131 0 +OP4 E03132 0 +OP4 E03133 0 +OP4 E03134 0 +OP4 E03135 0 +OP4 E03136 0 +OP4 E03137 0 +OP4 E03138 0 +OP4 E03139 0 +OP4 E0313A 0 +OP4 E0313B 0 +OP4 E0313C 0 +OP4 E0313D 0 +OP4 E0313E 0 +OP4 E0313F 0 +OP4 E03140 0 +OP4 E03141 0 +OP4 E03142 0 +OP4 E03143 0 +OP4 E03144 0 +OP4 E03145 0 +OP4 E03146 0 +OP4 E03147 0 +OP4 E03148 0 +OP4 E03149 0 +OP4 E0314A 0 +OP4 E0314B 0 +OP4 E0314C 0 +OP4 E0314D 0 +OP4 E0314E 0 +OP4 E0314F 0 +OP4 E03150 0 +OP4 E03151 0 +OP4 E03152 0 +OP4 E03153 0 +OP4 E03154 0 +OP4 E03155 0 +OP4 E03156 0 +OP4 E03157 0 +OP4 E03158 0 +OP4 E03159 0 +OP4 E0315A 0 +OP4 E0315B 0 +OP4 E0315C 0 +OP4 E0315D 0 +OP4 E0315E 0 +OP4 E0315F 0 +OP4 E03160 0 +OP4 E03161 0 +OP4 E03162 0 +OP4 E03163 0 +OP4 E03164 0 +OP4 E03165 0 +OP4 E03166 0 +OP4 E03167 0 +OP4 E03168 0 +OP4 E03169 0 +OP4 E0316A 0 +OP4 E0316B 0 +OP4 E0316C 0 +OP4 E0316D 0 +OP4 E0316E 0 +OP4 E0316F 0 +OP4 E03170 0 +OP4 E03171 0 +OP4 E03172 0 +OP4 E03173 0 +OP4 E03174 0 +OP4 E03175 0 +OP4 E03176 0 +OP4 E03177 0 +OP4 E03178 0 +OP4 E03179 0 +OP4 E0317A 0 +OP4 E0317B 0 +OP4 E0317C 0 +OP4 E0317D 0 +OP4 E0317E 0 +OP4 E0317F 0 +OP4 E03180 0 +OP4 E03181 0 +OP4 E03182 0 +OP4 E03183 0 +OP4 E03184 0 +OP4 E03185 0 +OP4 E03186 0 +OP4 E03187 0 +OP4 E03188 0 +OP4 E03189 0 +OP4 E0318A 0 +OP4 E0318B 0 +OP4 E0318C 0 +OP4 E0318D 0 +OP4 E0318E 0 +OP4 E0318F 0 +OP4 E03190 0 +OP4 E03191 0 +OP4 E03192 0 +OP4 E03193 0 +OP4 E03194 0 +OP4 E03195 0 +OP4 E03196 0 +OP4 E03197 0 +OP4 E03198 0 +OP4 E03199 0 +OP4 E0319A 0 +OP4 E0319B 0 +OP4 E0319C 0 +OP4 E0319D 0 +OP4 E0319E 0 +OP4 E0319F 0 +OP4 E031A0 0 +OP4 E031A1 0 +OP4 E031A2 0 +OP4 E031A3 0 +OP4 E031A4 0 +OP4 E031A5 0 +OP4 E031A6 0 +OP4 E031A7 0 +OP4 E031A8 0 +OP4 E031A9 0 +OP4 E031AA 0 +OP4 E031AB 0 +OP4 E031AC 0 +OP4 E031AD 0 +OP4 E031AE 0 +OP4 E031AF 0 +OP4 E031B0 0 +OP4 E031B1 0 +OP4 E031B2 0 +OP4 E031B3 0 +OP4 E031B4 0 +OP4 E031B5 0 +OP4 E031B6 0 +OP4 E031B7 0 +OP4 E031B8 0 +OP4 E031B9 0 +OP4 E031BA 0 +OP4 E031BB 0 +OP4 E031BC 0 +OP4 E031BD 0 +OP4 E031BE 0 +OP4 E031BF 0 +OP4 E031C0 0 +OP4 E031C1 0 +OP4 E031C2 0 +OP4 E031C3 0 +OP4 E031C4 0 +OP4 E031C5 0 +OP4 E031C6 0 +OP4 E031C7 0 +OP4 E031C8 0 +OP4 E031C9 0 +OP4 E031CA 0 +OP4 E031CB 0 +OP4 E031CC 0 +OP4 E031CD 0 +OP4 E031CE 0 +OP4 E031CF 0 +OP4 E031D0 0 +OP4 E031D1 0 +OP4 E031D2 0 +OP4 E031D3 0 +OP4 E031D4 0 +OP4 E031D5 0 +OP4 E031D6 0 +OP4 E031D7 0 +OP4 E031D8 0 +OP4 E031D9 0 +OP4 E031DA 0 +OP4 E031DB 0 +OP4 E031DC 0 +OP4 E031DD 0 +OP4 E031DE 0 +OP4 E031DF 0 +OP4 E031E0 0 +OP4 E031E1 0 +OP4 E031E2 0 +OP4 E031E3 0 +OP4 E031E4 0 +OP4 E031E5 0 +OP4 E031E6 0 +OP4 E031E7 0 +OP4 E031E8 0 +OP4 E031E9 0 +OP4 E031EA 0 +OP4 E031EB 0 +OP4 E031EC 0 +OP4 E031ED 0 +OP4 E031EE 0 +OP4 E031EF 0 +OP4 E031F0 0 +OP4 E031F1 0 +OP4 E031F2 0 +OP4 E031F3 0 +OP4 E031F4 0 +OP4 E031F5 0 +OP4 E031F6 0 +OP4 E031F7 0 +OP4 E031F8 0 +OP4 E031F9 0 +OP4 E031FA 0 +OP4 E031FB 0 +OP4 E031FC 0 +OP4 E031FD 0 +OP4 E031FE 0 +OP4 E031FF 0 +OP4 E03200 0 +OP4 E03201 0 +OP4 E03202 0 +OP4 E03203 0 +OP4 E03204 0 +OP4 E03205 0 +OP4 E03206 0 +OP4 E03207 0 +OP4 E03208 0 +OP4 E03209 0 +OP4 E0320A 0 +OP4 E0320B 0 +OP4 E0320C 0 +OP4 E0320D 0 +OP4 E0320E 0 +OP4 E0320F 0 +OP4 E03210 0 +OP4 E03211 0 +OP4 E03212 0 +OP4 E03213 0 +OP4 E03214 0 +OP4 E03215 0 +OP4 E03216 0 +OP4 E03217 0 +OP4 E03218 0 +OP4 E03219 0 +OP4 E0321A 0 +OP4 E0321B 0 +OP4 E0321C 0 +OP4 E0321D 0 +OP4 E0321E 0 +OP4 E0321F 0 +OP4 E03220 0 +OP4 E03221 0 +OP4 E03222 0 +OP4 E03223 0 +OP4 E03224 0 +OP4 E03225 0 +OP4 E03226 0 +OP4 E03227 0 +OP4 E03228 0 +OP4 E03229 0 +OP4 E0322A 0 +OP4 E0322B 0 +OP4 E0322C 0 +OP4 E0322D 0 +OP4 E0322E 0 +OP4 E0322F 0 +OP4 E03230 0 +OP4 E03231 0 +OP4 E03232 0 +OP4 E03233 0 +OP4 E03234 0 +OP4 E03235 0 +OP4 E03236 0 +OP4 E03237 0 +OP4 E03238 0 +OP4 E03239 0 +OP4 E0323A 0 +OP4 E0323B 0 +OP4 E0323C 0 +OP4 E0323D 0 +OP4 E0323E 0 +OP4 E0323F 0 +OP4 E03240 0 +OP4 E03241 0 +OP4 E03242 0 +OP4 E03243 0 +OP4 E03244 0 +OP4 E03245 0 +OP4 E03246 0 +OP4 E03247 0 +OP4 E03248 0 +OP4 E03249 0 +OP4 E0324A 0 +OP4 E0324B 0 +OP4 E0324C 0 +OP4 E0324D 0 +OP4 E0324E 0 +OP4 E0324F 0 +OP4 E03250 0 +OP4 E03251 0 +OP4 E03252 0 +OP4 E03253 0 +OP4 E03254 0 +OP4 E03255 0 +OP4 E03256 0 +OP4 E03257 0 +OP4 E03258 0 +OP4 E03259 0 +OP4 E0325A 0 +OP4 E0325B 0 +OP4 E0325C 0 +OP4 E0325D 0 +OP4 E0325E 0 +OP4 E0325F 0 +OP4 E03260 0 +OP4 E03261 0 +OP4 E03262 0 +OP4 E03263 0 +OP4 E03264 0 +OP4 E03265 0 +OP4 E03266 0 +OP4 E03267 0 +OP4 E03268 0 +OP4 E03269 0 +OP4 E0326A 0 +OP4 E0326B 0 +OP4 E0326C 0 +OP4 E0326D 0 +OP4 E0326E 0 +OP4 E0326F 0 +OP4 E03270 0 +OP4 E03271 0 +OP4 E03272 0 +OP4 E03273 0 +OP4 E03274 0 +OP4 E03275 0 +OP4 E03276 0 +OP4 E03277 0 +OP4 E03278 0 +OP4 E03279 0 +OP4 E0327A 0 +OP4 E0327B 0 +OP4 E0327C 0 +OP4 E0327D 0 +OP4 E0327E 0 +OP4 E0327F 0 +OP4 E03280 0 +OP4 E03281 0 +OP4 E03282 0 +OP4 E03283 0 +OP4 E03284 0 +OP4 E03285 0 +OP4 E03286 0 +OP4 E03287 0 +OP4 E03288 0 +OP4 E03289 0 +OP4 E0328A 0 +OP4 E0328B 0 +OP4 E0328C 0 +OP4 E0328D 0 +OP4 E0328E 0 +OP4 E0328F 0 +OP4 E03290 0 +OP4 E03291 0 +OP4 E03292 0 +OP4 E03293 0 +OP4 E03294 0 +OP4 E03295 0 +OP4 E03296 0 +OP4 E03297 0 +OP4 E03298 0 +OP4 E03299 0 +OP4 E0329A 0 +OP4 E0329B 0 +OP4 E0329C 0 +OP4 E0329D 0 +OP4 E0329E 0 +OP4 E0329F 0 +OP4 E032A0 0 +OP4 E032A1 0 +OP4 E032A2 0 +OP4 E032A3 0 +OP4 E032A4 0 +OP4 E032A5 0 +OP4 E032A6 0 +OP4 E032A7 0 +OP4 E032A8 0 +OP4 E032A9 0 +OP4 E032AA 0 +OP4 E032AB 0 +OP4 E032AC 0 +OP4 E032AD 0 +OP4 E032AE 0 +OP4 E032AF 0 +OP4 E032B0 0 +OP4 E032B1 0 +OP4 E032B2 0 +OP4 E032B3 0 +OP4 E032B4 0 +OP4 E032B5 0 +OP4 E032B6 0 +OP4 E032B7 0 +OP4 E032B8 0 +OP4 E032B9 0 +OP4 E032BA 0 +OP4 E032BB 0 +OP4 E032BC 0 +OP4 E032BD 0 +OP4 E032BE 0 +OP4 E032BF 0 +OP4 E032C0 0 +OP4 E032C1 0 +OP4 E032C2 0 +OP4 E032C3 0 +OP4 E032C4 0 +OP4 E032C5 0 +OP4 E032C6 0 +OP4 E032C7 0 +OP4 E032C8 0 +OP4 E032C9 0 +OP4 E032CA 0 +OP4 E032CB 0 +OP4 E032CC 0 +OP4 E032CD 0 +OP4 E032CE 0 +OP4 E032CF 0 +OP4 E032D0 0 +OP4 E032D1 0 +OP4 E032D2 0 +OP4 E032D3 0 +OP4 E032D4 0 +OP4 E032D5 0 +OP4 E032D6 0 +OP4 E032D7 0 +OP4 E032D8 0 +OP4 E032D9 0 +OP4 E032DA 0 +OP4 E032DB 0 +OP4 E032DC 0 +OP4 E032DD 0 +OP4 E032DE 0 +OP4 E032DF 0 +OP4 E032E0 0 +OP4 E032E1 0 +OP4 E032E2 0 +OP4 E032E3 0 +OP4 E032E4 0 +OP4 E032E5 0 +OP4 E032E6 0 +OP4 E032E7 0 +OP4 E032E8 0 +OP4 E032E9 0 +OP4 E032EA 0 +OP4 E032EB 0 +OP4 E032EC 0 +OP4 E032ED 0 +OP4 E032EE 0 +OP4 E032EF 0 +OP4 E032F0 0 +OP4 E032F1 0 +OP4 E032F2 0 +OP4 E032F3 0 +OP4 E032F4 0 +OP4 E032F5 0 +OP4 E032F6 0 +OP4 E032F7 0 +OP4 E032F8 0 +OP4 E032F9 0 +OP4 E032FA 0 +OP4 E032FB 0 +OP4 E032FC 0 +OP4 E032FD 0 +OP4 E032FE 0 +OP4 E032FF 0 +OP4 E03300 0 +OP4 E03301 0 +OP4 E03302 0 +OP4 E03303 0 +OP4 E03304 0 +OP4 E03305 0 +OP4 E03306 0 +OP4 E03307 0 +OP4 E03308 0 +OP4 E03309 0 +OP4 E0330A 0 +OP4 E0330B 0 +OP4 E0330C 0 +OP4 E0330D 0 +OP4 E0330E 0 +OP4 E0330F 0 +OP4 E03310 0 +OP4 E03311 0 +OP4 E03312 0 +OP4 E03313 0 +OP4 E03314 0 +OP4 E03315 0 +OP4 E03316 0 +OP4 E03317 0 +OP4 E03318 0 +OP4 E03319 0 +OP4 E0331A 0 +OP4 E0331B 0 +OP4 E0331C 0 +OP4 E0331D 0 +OP4 E0331E 0 +OP4 E0331F 0 +OP4 E03320 0 +OP4 E03321 0 +OP4 E03322 0 +OP4 E03323 0 +OP4 E03324 0 +OP4 E03325 0 +OP4 E03326 0 +OP4 E03327 0 +OP4 E03328 0 +OP4 E03329 0 +OP4 E0332A 0 +OP4 E0332B 0 +OP4 E0332C 0 +OP4 E0332D 0 +OP4 E0332E 0 +OP4 E0332F 0 +OP4 E03330 0 +OP4 E03331 0 +OP4 E03332 0 +OP4 E03333 0 +OP4 E03334 0 +OP4 E03335 0 +OP4 E03336 0 +OP4 E03337 0 +OP4 E03338 0 +OP4 E03339 0 +OP4 E0333A 0 +OP4 E0333B 0 +OP4 E0333C 0 +OP4 E0333D 0 +OP4 E0333E 0 +OP4 E0333F 0 +OP4 E03340 0 +OP4 E03341 0 +OP4 E03342 0 +OP4 E03343 0 +OP4 E03344 0 +OP4 E03345 0 +OP4 E03346 0 +OP4 E03347 0 +OP4 E03348 0 +OP4 E03349 0 +OP4 E0334A 0 +OP4 E0334B 0 +OP4 E0334C 0 +OP4 E0334D 0 +OP4 E0334E 0 +OP4 E0334F 0 +OP4 E03350 0 +OP4 E03351 0 +OP4 E03352 0 +OP4 E03353 0 +OP4 E03354 0 +OP4 E03355 0 +OP4 E03356 0 +OP4 E03357 0 +OP4 E03358 0 +OP4 E03359 0 +OP4 E0335A 0 +OP4 E0335B 0 +OP4 E0335C 0 +OP4 E0335D 0 +OP4 E0335E 0 +OP4 E0335F 0 +OP4 E03360 0 +OP4 E03361 0 +OP4 E03362 0 +OP4 E03363 0 +OP4 E03364 0 +OP4 E03365 0 +OP4 E03366 0 +OP4 E03367 0 +OP4 E03368 0 +OP4 E03369 0 +OP4 E0336A 0 +OP4 E0336B 0 +OP4 E0336C 0 +OP4 E0336D 0 +OP4 E0336E 0 +OP4 E0336F 0 +OP4 E03370 0 +OP4 E03371 0 +OP4 E03372 0 +OP4 E03373 0 +OP4 E03374 0 +OP4 E03375 0 +OP4 E03376 0 +OP4 E03377 0 +OP4 E03378 0 +OP4 E03379 0 +OP4 E0337A 0 +OP4 E0337B 0 +OP4 E0337C 0 +OP4 E0337D 0 +OP4 E0337E 0 +OP4 E0337F 0 +OP4 E03380 0 +OP4 E03381 0 +OP4 E03382 0 +OP4 E03383 0 +OP4 E03384 0 +OP4 E03385 0 +OP4 E03386 0 +OP4 E03387 0 +OP4 E03388 0 +OP4 E03389 0 +OP4 E0338A 0 +OP4 E0338B 0 +OP4 E0338C 0 +OP4 E0338D 0 +OP4 E0338E 0 +OP4 E0338F 0 +OP4 E03390 0 +OP4 E03391 0 +OP4 E03392 0 +OP4 E03393 0 +OP4 E03394 0 +OP4 E03395 0 +OP4 E03396 0 +OP4 E03397 0 +OP4 E03398 0 +OP4 E03399 0 +OP4 E0339A 0 +OP4 E0339B 0 +OP4 E0339C 0 +OP4 E0339D 0 +OP4 E0339E 0 +OP4 E0339F 0 +OP4 E033A0 0 +OP4 E033A1 0 +OP4 E033A2 0 +OP4 E033A3 0 +OP4 E033A4 0 +OP4 E033A5 0 +OP4 E033A6 0 +OP4 E033A7 0 +OP4 E033A8 0 +OP4 E033A9 0 +OP4 E033AA 0 +OP4 E033AB 0 +OP4 E033AC 0 +OP4 E033AD 0 +OP4 E033AE 0 +OP4 E033AF 0 +OP4 E033B0 0 +OP4 E033B1 0 +OP4 E033B2 0 +OP4 E033B3 0 +OP4 E033B4 0 +OP4 E033B5 0 +OP4 E033B6 0 +OP4 E033B7 0 +OP4 E033B8 0 +OP4 E033B9 0 +OP4 E033BA 0 +OP4 E033BB 0 +OP4 E033BC 0 +OP4 E033BD 0 +OP4 E033BE 0 +OP4 E033BF 0 +OP4 E033C0 0 +OP4 E033C1 0 +OP4 E033C2 0 +OP4 E033C3 0 +OP4 E033C4 0 +OP4 E033C5 0 +OP4 E033C6 0 +OP4 E033C7 0 +OP4 E033C8 0 +OP4 E033C9 0 +OP4 E033CA 0 +OP4 E033CB 0 +OP4 E033CC 0 +OP4 E033CD 0 +OP4 E033CE 0 +OP4 E033CF 0 +OP4 E033D0 0 +OP4 E033D1 0 +OP4 E033D2 0 +OP4 E033D3 0 +OP4 E033D4 0 +OP4 E033D5 0 +OP4 E033D6 0 +OP4 E033D7 0 +OP4 E033D8 0 +OP4 E033D9 0 +OP4 E033DA 0 +OP4 E033DB 0 +OP4 E033DC 0 +OP4 E033DD 0 +OP4 E033DE 0 +OP4 E033DF 0 +OP4 E033E0 0 +OP4 E033E1 0 +OP4 E033E2 0 +OP4 E033E3 0 +OP4 E033E4 0 +OP4 E033E5 0 +OP4 E033E6 0 +OP4 E033E7 0 +OP4 E033E8 0 +OP4 E033E9 0 +OP4 E033EA 0 +OP4 E033EB 0 +OP4 E033EC 0 +OP4 E033ED 0 +OP4 E033EE 0 +OP4 E033EF 0 +OP4 E033F0 0 +OP4 E033F1 0 +OP4 E033F2 0 +OP4 E033F3 0 +OP4 E033F4 0 +OP4 E033F5 0 +OP4 E033F6 0 +OP4 E033F7 0 +OP4 E033F8 0 +OP4 E033F9 0 +OP4 E033FA 0 +OP4 E033FB 0 +OP4 E033FC 0 +OP4 E033FD 0 +OP4 E033FE 0 +OP4 E033FF 0 +OP4 E03400 0 +OP4 E03401 0 +OP4 E03402 0 +OP4 E03403 0 +OP4 E03404 0 +OP4 E03405 0 +OP4 E03406 0 +OP4 E03407 0 +OP4 E03408 0 +OP4 E03409 0 +OP4 E0340A 0 +OP4 E0340B 0 +OP4 E0340C 0 +OP4 E0340D 0 +OP4 E0340E 0 +OP4 E0340F 0 +OP4 E03410 0 +OP4 E03411 0 +OP4 E03412 0 +OP4 E03413 0 +OP4 E03414 0 +OP4 E03415 0 +OP4 E03416 0 +OP4 E03417 0 +OP4 E03418 0 +OP4 E03419 0 +OP4 E0341A 0 +OP4 E0341B 0 +OP4 E0341C 0 +OP4 E0341D 0 +OP4 E0341E 0 +OP4 E0341F 0 +OP4 E03420 0 +OP4 E03421 0 +OP4 E03422 0 +OP4 E03423 0 +OP4 E03424 0 +OP4 E03425 0 +OP4 E03426 0 +OP4 E03427 0 +OP4 E03428 0 +OP4 E03429 0 +OP4 E0342A 0 +OP4 E0342B 0 +OP4 E0342C 0 +OP4 E0342D 0 +OP4 E0342E 0 +OP4 E0342F 0 +OP4 E03430 0 +OP4 E03431 0 +OP4 E03432 0 +OP4 E03433 0 +OP4 E03434 0 +OP4 E03435 0 +OP4 E03436 0 +OP4 E03437 0 +OP4 E03438 0 +OP4 E03439 0 +OP4 E0343A 0 +OP4 E0343B 0 +OP4 E0343C 0 +OP4 E0343D 0 +OP4 E0343E 0 +OP4 E0343F 0 +OP4 E03440 0 +OP4 E03441 0 +OP4 E03442 0 +OP4 E03443 0 +OP4 E03444 0 +OP4 E03445 0 +OP4 E03446 0 +OP4 E03447 0 +OP4 E03448 0 +OP4 E03449 0 +OP4 E0344A 0 +OP4 E0344B 0 +OP4 E0344C 0 +OP4 E0344D 0 +OP4 E0344E 0 +OP4 E0344F 0 +OP4 E03450 0 +OP4 E03451 0 +OP4 E03452 0 +OP4 E03453 0 +OP4 E03454 0 +OP4 E03455 0 +OP4 E03456 0 +OP4 E03457 0 +OP4 E03458 0 +OP4 E03459 0 +OP4 E0345A 0 +OP4 E0345B 0 +OP4 E0345C 0 +OP4 E0345D 0 +OP4 E0345E 0 +OP4 E0345F 0 +OP4 E03460 0 +OP4 E03461 0 +OP4 E03462 0 +OP4 E03463 0 +OP4 E03464 0 +OP4 E03465 0 +OP4 E03466 0 +OP4 E03467 0 +OP4 E03468 0 +OP4 E03469 0 +OP4 E0346A 0 +OP4 E0346B 0 +OP4 E0346C 0 +OP4 E0346D 0 +OP4 E0346E 0 +OP4 E0346F 0 +OP4 E03470 0 +OP4 E03471 0 +OP4 E03472 0 +OP4 E03473 0 +OP4 E03474 0 +OP4 E03475 0 +OP4 E03476 0 +OP4 E03477 0 +OP4 E03478 0 +OP4 E03479 0 +OP4 E0347A 0 +OP4 E0347B 0 +OP4 E0347C 0 +OP4 E0347D 0 +OP4 E0347E 0 +OP4 E0347F 0 +OP4 E03480 0 +OP4 E03481 0 +OP4 E03482 0 +OP4 E03483 0 +OP4 E03484 0 +OP4 E03485 0 +OP4 E03486 0 +OP4 E03487 0 +OP4 E03488 0 +OP4 E03489 0 +OP4 E0348A 0 +OP4 E0348B 0 +OP4 E0348C 0 +OP4 E0348D 0 +OP4 E0348E 0 +OP4 E0348F 0 +OP4 E03490 0 +OP4 E03491 0 +OP4 E03492 0 +OP4 E03493 0 +OP4 E03494 0 +OP4 E03495 0 +OP4 E03496 0 +OP4 E03497 0 +OP4 E03498 0 +OP4 E03499 0 +OP4 E0349A 0 +OP4 E0349B 0 +OP4 E0349C 0 +OP4 E0349D 0 +OP4 E0349E 0 +OP4 E0349F 0 +OP4 E034A0 0 +OP4 E034A1 0 +OP4 E034A2 0 +OP4 E034A3 0 +OP4 E034A4 0 +OP4 E034A5 0 +OP4 E034A6 0 +OP4 E034A7 0 +OP4 E034A8 0 +OP4 E034A9 0 +OP4 E034AA 0 +OP4 E034AB 0 +OP4 E034AC 0 +OP4 E034AD 0 +OP4 E034AE 0 +OP4 E034AF 0 +OP4 E034B0 0 +OP4 E034B1 0 +OP4 E034B2 0 +OP4 E034B3 0 +OP4 E034B4 0 +OP4 E034B5 0 +OP4 E034B6 0 +OP4 E034B7 0 +OP4 E034B8 0 +OP4 E034B9 0 +OP4 E034BA 0 +OP4 E034BB 0 +OP4 E034BC 0 +OP4 E034BD 0 +OP4 E034BE 0 +OP4 E034BF 0 +OP4 E034C0 0 +OP4 E034C1 0 +OP4 E034C2 0 +OP4 E034C3 0 +OP4 E034C4 0 +OP4 E034C5 0 +OP4 E034C6 0 +OP4 E034C7 0 +OP4 E034C8 0 +OP4 E034C9 0 +OP4 E034CA 0 +OP4 E034CB 0 +OP4 E034CC 0 +OP4 E034CD 0 +OP4 E034CE 0 +OP4 E034CF 0 +OP4 E034D0 0 +OP4 E034D1 0 +OP4 E034D2 0 +OP4 E034D3 0 +OP4 E034D4 0 +OP4 E034D5 0 +OP4 E034D6 0 +OP4 E034D7 0 +OP4 E034D8 0 +OP4 E034D9 0 +OP4 E034DA 0 +OP4 E034DB 0 +OP4 E034DC 0 +OP4 E034DD 0 +OP4 E034DE 0 +OP4 E034DF 0 +OP4 E034E0 0 +OP4 E034E1 0 +OP4 E034E2 0 +OP4 E034E3 0 +OP4 E034E4 0 +OP4 E034E5 0 +OP4 E034E6 0 +OP4 E034E7 0 +OP4 E034E8 0 +OP4 E034E9 0 +OP4 E034EA 0 +OP4 E034EB 0 +OP4 E034EC 0 +OP4 E034ED 0 +OP4 E034EE 0 +OP4 E034EF 0 +OP4 E034F0 0 +OP4 E034F1 0 +OP4 E034F2 0 +OP4 E034F3 0 +OP4 E034F4 0 +OP4 E034F5 0 +OP4 E034F6 0 +OP4 E034F7 0 +OP4 E034F8 0 +OP4 E034F9 0 +OP4 E034FA 0 +OP4 E034FB 0 +OP4 E034FC 0 +OP4 E034FD 0 +OP4 E034FE 0 +OP4 E034FF 0 +OP4 E03500 0 +OP4 E03501 0 +OP4 E03502 0 +OP4 E03503 0 +OP4 E03504 0 +OP4 E03505 0 +OP4 E03506 0 +OP4 E03507 0 +OP4 E03508 0 +OP4 E03509 0 +OP4 E0350A 0 +OP4 E0350B 0 +OP4 E0350C 0 +OP4 E0350D 0 +OP4 E0350E 0 +OP4 E0350F 0 +OP4 E03510 0 +OP4 E03511 0 +OP4 E03512 0 +OP4 E03513 0 +OP4 E03514 0 +OP4 E03515 0 +OP4 E03516 0 +OP4 E03517 0 +OP4 E03518 0 +OP4 E03519 0 +OP4 E0351A 0 +OP4 E0351B 0 +OP4 E0351C 0 +OP4 E0351D 0 +OP4 E0351E 0 +OP4 E0351F 0 +OP4 E03520 0 +OP4 E03521 0 +OP4 E03522 0 +OP4 E03523 0 +OP4 E03524 0 +OP4 E03525 0 +OP4 E03526 0 +OP4 E03527 0 +OP4 E03528 0 +OP4 E03529 0 +OP4 E0352A 0 +OP4 E0352B 0 +OP4 E0352C 0 +OP4 E0352D 0 +OP4 E0352E 0 +OP4 E0352F 0 +OP4 E03530 0 +OP4 E03531 0 +OP4 E03532 0 +OP4 E03533 0 +OP4 E03534 0 +OP4 E03535 0 +OP4 E03536 0 +OP4 E03537 0 +OP4 E03538 0 +OP4 E03539 0 +OP4 E0353A 0 +OP4 E0353B 0 +OP4 E0353C 0 +OP4 E0353D 0 +OP4 E0353E 0 +OP4 E0353F 0 +OP4 E03540 0 +OP4 E03541 0 +OP4 E03542 0 +OP4 E03543 0 +OP4 E03544 0 +OP4 E03545 0 +OP4 E03546 0 +OP4 E03547 0 +OP4 E03548 0 +OP4 E03549 0 +OP4 E0354A 0 +OP4 E0354B 0 +OP4 E0354C 0 +OP4 E0354D 0 +OP4 E0354E 0 +OP4 E0354F 0 +OP4 E03550 0 +OP4 E03551 0 +OP4 E03552 0 +OP4 E03553 0 +OP4 E03554 0 +OP4 E03555 0 +OP4 E03556 0 +OP4 E03557 0 +OP4 E03558 0 +OP4 E03559 0 +OP4 E0355A 0 +OP4 E0355B 0 +OP4 E0355C 0 +OP4 E0355D 0 +OP4 E0355E 0 +OP4 E0355F 0 +OP4 E03560 0 +OP4 E03561 0 +OP4 E03562 0 +OP4 E03563 0 +OP4 E03564 0 +OP4 E03565 0 +OP4 E03566 0 +OP4 E03567 0 +OP4 E03568 0 +OP4 E03569 0 +OP4 E0356A 0 +OP4 E0356B 0 +OP4 E0356C 0 +OP4 E0356D 0 +OP4 E0356E 0 +OP4 E0356F 0 +OP4 E03570 0 +OP4 E03571 0 +OP4 E03572 0 +OP4 E03573 0 +OP4 E03574 0 +OP4 E03575 0 +OP4 E03576 0 +OP4 E03577 0 +OP4 E03578 0 +OP4 E03579 0 +OP4 E0357A 0 +OP4 E0357B 0 +OP4 E0357C 0 +OP4 E0357D 0 +OP4 E0357E 0 +OP4 E0357F 0 +OP4 E03580 0 +OP4 E03581 0 +OP4 E03582 0 +OP4 E03583 0 +OP4 E03584 0 +OP4 E03585 0 +OP4 E03586 0 +OP4 E03587 0 +OP4 E03588 0 +OP4 E03589 0 +OP4 E0358A 0 +OP4 E0358B 0 +OP4 E0358C 0 +OP4 E0358D 0 +OP4 E0358E 0 +OP4 E0358F 0 +OP4 E03590 0 +OP4 E03591 0 +OP4 E03592 0 +OP4 E03593 0 +OP4 E03594 0 +OP4 E03595 0 +OP4 E03596 0 +OP4 E03597 0 +OP4 E03598 0 +OP4 E03599 0 +OP4 E0359A 0 +OP4 E0359B 0 +OP4 E0359C 0 +OP4 E0359D 0 +OP4 E0359E 0 +OP4 E0359F 0 +OP4 E035A0 0 +OP4 E035A1 0 +OP4 E035A2 0 +OP4 E035A3 0 +OP4 E035A4 0 +OP4 E035A5 0 +OP4 E035A6 0 +OP4 E035A7 0 +OP4 E035A8 0 +OP4 E035A9 0 +OP4 E035AA 0 +OP4 E035AB 0 +OP4 E035AC 0 +OP4 E035AD 0 +OP4 E035AE 0 +OP4 E035AF 0 +OP4 E035B0 0 +OP4 E035B1 0 +OP4 E035B2 0 +OP4 E035B3 0 +OP4 E035B4 0 +OP4 E035B5 0 +OP4 E035B6 0 +OP4 E035B7 0 +OP4 E035B8 0 +OP4 E035B9 0 +OP4 E035BA 0 +OP4 E035BB 0 +OP4 E035BC 0 +OP4 E035BD 0 +OP4 E035BE 0 +OP4 E035BF 0 +OP4 E035C0 0 +OP4 E035C1 0 +OP4 E035C2 0 +OP4 E035C3 0 +OP4 E035C4 0 +OP4 E035C5 0 +OP4 E035C6 0 +OP4 E035C7 0 +OP4 E035C8 0 +OP4 E035C9 0 +OP4 E035CA 0 +OP4 E035CB 0 +OP4 E035CC 0 +OP4 E035CD 0 +OP4 E035CE 0 +OP4 E035CF 0 +OP4 E035D0 0 +OP4 E035D1 0 +OP4 E035D2 0 +OP4 E035D3 0 +OP4 E035D4 0 +OP4 E035D5 0 +OP4 E035D6 0 +OP4 E035D7 0 +OP4 E035D8 0 +OP4 E035D9 0 +OP4 E035DA 0 +OP4 E035DB 0 +OP4 E035DC 0 +OP4 E035DD 0 +OP4 E035DE 0 +OP4 E035DF 0 +OP4 E035E0 0 +OP4 E035E1 0 +OP4 E035E2 0 +OP4 E035E3 0 +OP4 E035E4 0 +OP4 E035E5 0 +OP4 E035E6 0 +OP4 E035E7 0 +OP4 E035E8 0 +OP4 E035E9 0 +OP4 E035EA 0 +OP4 E035EB 0 +OP4 E035EC 0 +OP4 E035ED 0 +OP4 E035EE 0 +OP4 E035EF 0 +OP4 E035F0 0 +OP4 E035F1 0 +OP4 E035F2 0 +OP4 E035F3 0 +OP4 E035F4 0 +OP4 E035F5 0 +OP4 E035F6 0 +OP4 E035F7 0 +OP4 E035F8 0 +OP4 E035F9 0 +OP4 E035FA 0 +OP4 E035FB 0 +OP4 E035FC 0 +OP4 E035FD 0 +OP4 E035FE 0 +OP4 E035FF 0 +OP4 E03600 0 +OP4 E03601 0 +OP4 E03602 0 +OP4 E03603 0 +OP4 E03604 0 +OP4 E03605 0 +OP4 E03606 0 +OP4 E03607 0 +OP4 E03608 0 +OP4 E03609 0 +OP4 E0360A 0 +OP4 E0360B 0 +OP4 E0360C 0 +OP4 E0360D 0 +OP4 E0360E 0 +OP4 E0360F 0 +OP4 E03610 0 +OP4 E03611 0 +OP4 E03612 0 +OP4 E03613 0 +OP4 E03614 0 +OP4 E03615 0 +OP4 E03616 0 +OP4 E03617 0 +OP4 E03618 0 +OP4 E03619 0 +OP4 E0361A 0 +OP4 E0361B 0 +OP4 E0361C 0 +OP4 E0361D 0 +OP4 E0361E 0 +OP4 E0361F 0 +OP4 E03620 0 +OP4 E03621 0 +OP4 E03622 0 +OP4 E03623 0 +OP4 E03624 0 +OP4 E03625 0 +OP4 E03626 0 +OP4 E03627 0 +OP4 E03628 0 +OP4 E03629 0 +OP4 E0362A 0 +OP4 E0362B 0 +OP4 E0362C 0 +OP4 E0362D 0 +OP4 E0362E 0 +OP4 E0362F 0 +OP4 E03630 0 +OP4 E03631 0 +OP4 E03632 0 +OP4 E03633 0 +OP4 E03634 0 +OP4 E03635 0 +OP4 E03636 0 +OP4 E03637 0 +OP4 E03638 0 +OP4 E03639 0 +OP4 E0363A 0 +OP4 E0363B 0 +OP4 E0363C 0 +OP4 E0363D 0 +OP4 E0363E 0 +OP4 E0363F 0 +OP4 E03640 0 +OP4 E03641 0 +OP4 E03642 0 +OP4 E03643 0 +OP4 E03644 0 +OP4 E03645 0 +OP4 E03646 0 +OP4 E03647 0 +OP4 E03648 0 +OP4 E03649 0 +OP4 E0364A 0 +OP4 E0364B 0 +OP4 E0364C 0 +OP4 E0364D 0 +OP4 E0364E 0 +OP4 E0364F 0 +OP4 E03650 0 +OP4 E03651 0 +OP4 E03652 0 +OP4 E03653 0 +OP4 E03654 0 +OP4 E03655 0 +OP4 E03656 0 +OP4 E03657 0 +OP4 E03658 0 +OP4 E03659 0 +OP4 E0365A 0 +OP4 E0365B 0 +OP4 E0365C 0 +OP4 E0365D 0 +OP4 E0365E 0 +OP4 E0365F 0 +OP4 E03660 0 +OP4 E03661 0 +OP4 E03662 0 +OP4 E03663 0 +OP4 E03664 0 +OP4 E03665 0 +OP4 E03666 0 +OP4 E03667 0 +OP4 E03668 0 +OP4 E03669 0 +OP4 E0366A 0 +OP4 E0366B 0 +OP4 E0366C 0 +OP4 E0366D 0 +OP4 E0366E 0 +OP4 E0366F 0 +OP4 E03670 0 +OP4 E03671 0 +OP4 E03672 0 +OP4 E03673 0 +OP4 E03674 0 +OP4 E03675 0 +OP4 E03676 0 +OP4 E03677 0 +OP4 E03678 0 +OP4 E03679 0 +OP4 E0367A 0 +OP4 E0367B 0 +OP4 E0367C 0 +OP4 E0367D 0 +OP4 E0367E 0 +OP4 E0367F 0 +OP4 E03680 0 +OP4 E03681 0 +OP4 E03682 0 +OP4 E03683 0 +OP4 E03684 0 +OP4 E03685 0 +OP4 E03686 0 +OP4 E03687 0 +OP4 E03688 0 +OP4 E03689 0 +OP4 E0368A 0 +OP4 E0368B 0 +OP4 E0368C 0 +OP4 E0368D 0 +OP4 E0368E 0 +OP4 E0368F 0 +OP4 E03690 0 +OP4 E03691 0 +OP4 E03692 0 +OP4 E03693 0 +OP4 E03694 0 +OP4 E03695 0 +OP4 E03696 0 +OP4 E03697 0 +OP4 E03698 0 +OP4 E03699 0 +OP4 E0369A 0 +OP4 E0369B 0 +OP4 E0369C 0 +OP4 E0369D 0 +OP4 E0369E 0 +OP4 E0369F 0 +OP4 E036A0 0 +OP4 E036A1 0 +OP4 E036A2 0 +OP4 E036A3 0 +OP4 E036A4 0 +OP4 E036A5 0 +OP4 E036A6 0 +OP4 E036A7 0 +OP4 E036A8 0 +OP4 E036A9 0 +OP4 E036AA 0 +OP4 E036AB 0 +OP4 E036AC 0 +OP4 E036AD 0 +OP4 E036AE 0 +OP4 E036AF 0 +OP4 E036B0 0 +OP4 E036B1 0 +OP4 E036B2 0 +OP4 E036B3 0 +OP4 E036B4 0 +OP4 E036B5 0 +OP4 E036B6 0 +OP4 E036B7 0 +OP4 E036B8 0 +OP4 E036B9 0 +OP4 E036BA 0 +OP4 E036BB 0 +OP4 E036BC 0 +OP4 E036BD 0 +OP4 E036BE 0 +OP4 E036BF 0 +OP4 E036C0 0 +OP4 E036C1 0 +OP4 E036C2 0 +OP4 E036C3 0 +OP4 E036C4 0 +OP4 E036C5 0 +OP4 E036C6 0 +OP4 E036C7 0 +OP4 E036C8 0 +OP4 E036C9 0 +OP4 E036CA 0 +OP4 E036CB 0 +OP4 E036CC 0 +OP4 E036CD 0 +OP4 E036CE 0 +OP4 E036CF 0 +OP4 E036D0 0 +OP4 E036D1 0 +OP4 E036D2 0 +OP4 E036D3 0 +OP4 E036D4 0 +OP4 E036D5 0 +OP4 E036D6 0 +OP4 E036D7 0 +OP4 E036D8 0 +OP4 E036D9 0 +OP4 E036DA 0 +OP4 E036DB 0 +OP4 E036DC 0 +OP4 E036DD 0 +OP4 E036DE 0 +OP4 E036DF 0 +OP4 E036E0 0 +OP4 E036E1 0 +OP4 E036E2 0 +OP4 E036E3 0 +OP4 E036E4 0 +OP4 E036E5 0 +OP4 E036E6 0 +OP4 E036E7 0 +OP4 E036E8 0 +OP4 E036E9 0 +OP4 E036EA 0 +OP4 E036EB 0 +OP4 E036EC 0 +OP4 E036ED 0 +OP4 E036EE 0 +OP4 E036EF 0 +OP4 E036F0 0 +OP4 E036F1 0 +OP4 E036F2 0 +OP4 E036F3 0 +OP4 E036F4 0 +OP4 E036F5 0 +OP4 E036F6 0 +OP4 E036F7 0 +OP4 E036F8 0 +OP4 E036F9 0 +OP4 E036FA 0 +OP4 E036FB 0 +OP4 E036FC 0 +OP4 E036FD 0 +OP4 E036FE 0 +OP4 E036FF 0 +OP4 E03700 0 +OP4 E03701 0 +OP4 E03702 0 +OP4 E03703 0 +OP4 E03704 0 +OP4 E03705 0 +OP4 E03706 0 +OP4 E03707 0 +OP4 E03708 0 +OP4 E03709 0 +OP4 E0370A 0 +OP4 E0370B 0 +OP4 E0370C 0 +OP4 E0370D 0 +OP4 E0370E 0 +OP4 E0370F 0 +OP4 E03710 0 +OP4 E03711 0 +OP4 E03712 0 +OP4 E03713 0 +OP4 E03714 0 +OP4 E03715 0 +OP4 E03716 0 +OP4 E03717 0 +OP4 E03718 0 +OP4 E03719 0 +OP4 E0371A 0 +OP4 E0371B 0 +OP4 E0371C 0 +OP4 E0371D 0 +OP4 E0371E 0 +OP4 E0371F 0 +OP4 E03720 0 +OP4 E03721 0 +OP4 E03722 0 +OP4 E03723 0 +OP4 E03724 0 +OP4 E03725 0 +OP4 E03726 0 +OP4 E03727 0 +OP4 E03728 0 +OP4 E03729 0 +OP4 E0372A 0 +OP4 E0372B 0 +OP4 E0372C 0 +OP4 E0372D 0 +OP4 E0372E 0 +OP4 E0372F 0 +OP4 E03730 0 +OP4 E03731 0 +OP4 E03732 0 +OP4 E03733 0 +OP4 E03734 0 +OP4 E03735 0 +OP4 E03736 0 +OP4 E03737 0 +OP4 E03738 0 +OP4 E03739 0 +OP4 E0373A 0 +OP4 E0373B 0 +OP4 E0373C 0 +OP4 E0373D 0 +OP4 E0373E 0 +OP4 E0373F 0 +OP4 E03740 0 +OP4 E03741 0 +OP4 E03742 0 +OP4 E03743 0 +OP4 E03744 0 +OP4 E03745 0 +OP4 E03746 0 +OP4 E03747 0 +OP4 E03748 0 +OP4 E03749 0 +OP4 E0374A 0 +OP4 E0374B 0 +OP4 E0374C 0 +OP4 E0374D 0 +OP4 E0374E 0 +OP4 E0374F 0 +OP4 E03750 0 +OP4 E03751 0 +OP4 E03752 0 +OP4 E03753 0 +OP4 E03754 0 +OP4 E03755 0 +OP4 E03756 0 +OP4 E03757 0 +OP4 E03758 0 +OP4 E03759 0 +OP4 E0375A 0 +OP4 E0375B 0 +OP4 E0375C 0 +OP4 E0375D 0 +OP4 E0375E 0 +OP4 E0375F 0 +OP4 E03760 0 +OP4 E03761 0 +OP4 E03762 0 +OP4 E03763 0 +OP4 E03764 0 +OP4 E03765 0 +OP4 E03766 0 +OP4 E03767 0 +OP4 E03768 0 +OP4 E03769 0 +OP4 E0376A 0 +OP4 E0376B 0 +OP4 E0376C 0 +OP4 E0376D 0 +OP4 E0376E 0 +OP4 E0376F 0 +OP4 E03770 0 +OP4 E03771 0 +OP4 E03772 0 +OP4 E03773 0 +OP4 E03774 0 +OP4 E03775 0 +OP4 E03776 0 +OP4 E03777 0 +OP4 E03778 0 +OP4 E03779 0 +OP4 E0377A 0 +OP4 E0377B 0 +OP4 E0377C 0 +OP4 E0377D 0 +OP4 E0377E 0 +OP4 E0377F 0 +OP4 E03780 0 +OP4 E03781 0 +OP4 E03782 0 +OP4 E03783 0 +OP4 E03784 0 +OP4 E03785 0 +OP4 E03786 0 +OP4 E03787 0 +OP4 E03788 0 +OP4 E03789 0 +OP4 E0378A 0 +OP4 E0378B 0 +OP4 E0378C 0 +OP4 E0378D 0 +OP4 E0378E 0 +OP4 E0378F 0 +OP4 E03790 0 +OP4 E03791 0 +OP4 E03792 0 +OP4 E03793 0 +OP4 E03794 0 +OP4 E03795 0 +OP4 E03796 0 +OP4 E03797 0 +OP4 E03798 0 +OP4 E03799 0 +OP4 E0379A 0 +OP4 E0379B 0 +OP4 E0379C 0 +OP4 E0379D 0 +OP4 E0379E 0 +OP4 E0379F 0 +OP4 E037A0 0 +OP4 E037A1 0 +OP4 E037A2 0 +OP4 E037A3 0 +OP4 E037A4 0 +OP4 E037A5 0 +OP4 E037A6 0 +OP4 E037A7 0 +OP4 E037A8 0 +OP4 E037A9 0 +OP4 E037AA 0 +OP4 E037AB 0 +OP4 E037AC 0 +OP4 E037AD 0 +OP4 E037AE 0 +OP4 E037AF 0 +OP4 E037B0 0 +OP4 E037B1 0 +OP4 E037B2 0 +OP4 E037B3 0 +OP4 E037B4 0 +OP4 E037B5 0 +OP4 E037B6 0 +OP4 E037B7 0 +OP4 E037B8 0 +OP4 E037B9 0 +OP4 E037BA 0 +OP4 E037BB 0 +OP4 E037BC 0 +OP4 E037BD 0 +OP4 E037BE 0 +OP4 E037BF 0 +OP4 E037C0 0 +OP4 E037C1 0 +OP4 E037C2 0 +OP4 E037C3 0 +OP4 E037C4 0 +OP4 E037C5 0 +OP4 E037C6 0 +OP4 E037C7 0 +OP4 E037C8 0 +OP4 E037C9 0 +OP4 E037CA 0 +OP4 E037CB 0 +OP4 E037CC 0 +OP4 E037CD 0 +OP4 E037CE 0 +OP4 E037CF 0 +OP4 E037D0 0 +OP4 E037D1 0 +OP4 E037D2 0 +OP4 E037D3 0 +OP4 E037D4 0 +OP4 E037D5 0 +OP4 E037D6 0 +OP4 E037D7 0 +OP4 E037D8 0 +OP4 E037D9 0 +OP4 E037DA 0 +OP4 E037DB 0 +OP4 E037DC 0 +OP4 E037DD 0 +OP4 E037DE 0 +OP4 E037DF 0 +OP4 E037E0 0 +OP4 E037E1 0 +OP4 E037E2 0 +OP4 E037E3 0 +OP4 E037E4 0 +OP4 E037E5 0 +OP4 E037E6 0 +OP4 E037E7 0 +OP4 E037E8 0 +OP4 E037E9 0 +OP4 E037EA 0 +OP4 E037EB 0 +OP4 E037EC 0 +OP4 E037ED 0 +OP4 E037EE 0 +OP4 E037EF 0 +OP4 E037F0 0 +OP4 E037F1 0 +OP4 E037F2 0 +OP4 E037F3 0 +OP4 E037F4 0 +OP4 E037F5 0 +OP4 E037F6 0 +OP4 E037F7 0 +OP4 E037F8 0 +OP4 E037F9 0 +OP4 E037FA 0 +OP4 E037FB 0 +OP4 E037FC 0 +OP4 E037FD 0 +OP4 E037FE 0 +OP4 E037FF 0 +OP4 E03800 0 +OP4 E03801 0 +OP4 E03802 0 +OP4 E03803 0 +OP4 E03804 0 +OP4 E03805 0 +OP4 E03806 0 +OP4 E03807 0 +OP4 E03808 0 +OP4 E03809 0 +OP4 E0380A 0 +OP4 E0380B 0 +OP4 E0380C 0 +OP4 E0380D 0 +OP4 E0380E 0 +OP4 E0380F 0 +OP4 E03810 0 +OP4 E03811 0 +OP4 E03812 0 +OP4 E03813 0 +OP4 E03814 0 +OP4 E03815 0 +OP4 E03816 0 +OP4 E03817 0 +OP4 E03818 0 +OP4 E03819 0 +OP4 E0381A 0 +OP4 E0381B 0 +OP4 E0381C 0 +OP4 E0381D 0 +OP4 E0381E 0 +OP4 E0381F 0 +OP4 E03820 0 +OP4 E03821 0 +OP4 E03822 0 +OP4 E03823 0 +OP4 E03824 0 +OP4 E03825 0 +OP4 E03826 0 +OP4 E03827 0 +OP4 E03828 0 +OP4 E03829 0 +OP4 E0382A 0 +OP4 E0382B 0 +OP4 E0382C 0 +OP4 E0382D 0 +OP4 E0382E 0 +OP4 E0382F 0 +OP4 E03830 0 +OP4 E03831 0 +OP4 E03832 0 +OP4 E03833 0 +OP4 E03834 0 +OP4 E03835 0 +OP4 E03836 0 +OP4 E03837 0 +OP4 E03838 0 +OP4 E03839 0 +OP4 E0383A 0 +OP4 E0383B 0 +OP4 E0383C 0 +OP4 E0383D 0 +OP4 E0383E 0 +OP4 E0383F 0 +OP4 E03840 0 +OP4 E03841 0 +OP4 E03842 0 +OP4 E03843 0 +OP4 E03844 0 +OP4 E03845 0 +OP4 E03846 0 +OP4 E03847 0 +OP4 E03848 0 +OP4 E03849 0 +OP4 E0384A 0 +OP4 E0384B 0 +OP4 E0384C 0 +OP4 E0384D 0 +OP4 E0384E 0 +OP4 E0384F 0 +OP4 E03850 0 +OP4 E03851 0 +OP4 E03852 0 +OP4 E03853 0 +OP4 E03854 0 +OP4 E03855 0 +OP4 E03856 0 +OP4 E03857 0 +OP4 E03858 0 +OP4 E03859 0 +OP4 E0385A 0 +OP4 E0385B 0 +OP4 E0385C 0 +OP4 E0385D 0 +OP4 E0385E 0 +OP4 E0385F 0 +OP4 E03860 0 +OP4 E03861 0 +OP4 E03862 0 +OP4 E03863 0 +OP4 E03864 0 +OP4 E03865 0 +OP4 E03866 0 +OP4 E03867 0 +OP4 E03868 0 +OP4 E03869 0 +OP4 E0386A 0 +OP4 E0386B 0 +OP4 E0386C 0 +OP4 E0386D 0 +OP4 E0386E 0 +OP4 E0386F 0 +OP4 E03870 0 +OP4 E03871 0 +OP4 E03872 0 +OP4 E03873 0 +OP4 E03874 0 +OP4 E03875 0 +OP4 E03876 0 +OP4 E03877 0 +OP4 E03878 0 +OP4 E03879 0 +OP4 E0387A 0 +OP4 E0387B 0 +OP4 E0387C 0 +OP4 E0387D 0 +OP4 E0387E 0 +OP4 E0387F 0 +OP4 E03880 0 +OP4 E03881 0 +OP4 E03882 0 +OP4 E03883 0 +OP4 E03884 0 +OP4 E03885 0 +OP4 E03886 0 +OP4 E03887 0 +OP4 E03888 0 +OP4 E03889 0 +OP4 E0388A 0 +OP4 E0388B 0 +OP4 E0388C 0 +OP4 E0388D 0 +OP4 E0388E 0 +OP4 E0388F 0 +OP4 E03890 0 +OP4 E03891 0 +OP4 E03892 0 +OP4 E03893 0 +OP4 E03894 0 +OP4 E03895 0 +OP4 E03896 0 +OP4 E03897 0 +OP4 E03898 0 +OP4 E03899 0 +OP4 E0389A 0 +OP4 E0389B 0 +OP4 E0389C 0 +OP4 E0389D 0 +OP4 E0389E 0 +OP4 E0389F 0 +OP4 E038A0 0 +OP4 E038A1 0 +OP4 E038A2 0 +OP4 E038A3 0 +OP4 E038A4 0 +OP4 E038A5 0 +OP4 E038A6 0 +OP4 E038A7 0 +OP4 E038A8 0 +OP4 E038A9 0 +OP4 E038AA 0 +OP4 E038AB 0 +OP4 E038AC 0 +OP4 E038AD 0 +OP4 E038AE 0 +OP4 E038AF 0 +OP4 E038B0 0 +OP4 E038B1 0 +OP4 E038B2 0 +OP4 E038B3 0 +OP4 E038B4 0 +OP4 E038B5 0 +OP4 E038B6 0 +OP4 E038B7 0 +OP4 E038B8 0 +OP4 E038B9 0 +OP4 E038BA 0 +OP4 E038BB 0 +OP4 E038BC 0 +OP4 E038BD 0 +OP4 E038BE 0 +OP4 E038BF 0 +OP4 E038C0 0 +OP4 E038C1 0 +OP4 E038C2 0 +OP4 E038C3 0 +OP4 E038C4 0 +OP4 E038C5 0 +OP4 E038C6 0 +OP4 E038C7 0 +OP4 E038C8 0 +OP4 E038C9 0 +OP4 E038CA 0 +OP4 E038CB 0 +OP4 E038CC 0 +OP4 E038CD 0 +OP4 E038CE 0 +OP4 E038CF 0 +OP4 E038D0 0 +OP4 E038D1 0 +OP4 E038D2 0 +OP4 E038D3 0 +OP4 E038D4 0 +OP4 E038D5 0 +OP4 E038D6 0 +OP4 E038D7 0 +OP4 E038D8 0 +OP4 E038D9 0 +OP4 E038DA 0 +OP4 E038DB 0 +OP4 E038DC 0 +OP4 E038DD 0 +OP4 E038DE 0 +OP4 E038DF 0 +OP4 E038E0 0 +OP4 E038E1 0 +OP4 E038E2 0 +OP4 E038E3 0 +OP4 E038E4 0 +OP4 E038E5 0 +OP4 E038E6 0 +OP4 E038E7 0 +OP4 E038E8 0 +OP4 E038E9 0 +OP4 E038EA 0 +OP4 E038EB 0 +OP4 E038EC 0 +OP4 E038ED 0 +OP4 E038EE 0 +OP4 E038EF 0 +OP4 E038F0 0 +OP4 E038F1 0 +OP4 E038F2 0 +OP4 E038F3 0 +OP4 E038F4 0 +OP4 E038F5 0 +OP4 E038F6 0 +OP4 E038F7 0 +OP4 E038F8 0 +OP4 E038F9 0 +OP4 E038FA 0 +OP4 E038FB 0 +OP4 E038FC 0 +OP4 E038FD 0 +OP4 E038FE 0 +OP4 E038FF 0 +OP4 E03900 0 +OP4 E03901 0 +OP4 E03902 0 +OP4 E03903 0 +OP4 E03904 0 +OP4 E03905 0 +OP4 E03906 0 +OP4 E03907 0 +OP4 E03908 0 +OP4 E03909 0 +OP4 E0390A 0 +OP4 E0390B 0 +OP4 E0390C 0 +OP4 E0390D 0 +OP4 E0390E 0 +OP4 E0390F 0 +OP4 E03910 0 +OP4 E03911 0 +OP4 E03912 0 +OP4 E03913 0 +OP4 E03914 0 +OP4 E03915 0 +OP4 E03916 0 +OP4 E03917 0 +OP4 E03918 0 +OP4 E03919 0 +OP4 E0391A 0 +OP4 E0391B 0 +OP4 E0391C 0 +OP4 E0391D 0 +OP4 E0391E 0 +OP4 E0391F 0 +OP4 E03920 0 +OP4 E03921 0 +OP4 E03922 0 +OP4 E03923 0 +OP4 E03924 0 +OP4 E03925 0 +OP4 E03926 0 +OP4 E03927 0 +OP4 E03928 0 +OP4 E03929 0 +OP4 E0392A 0 +OP4 E0392B 0 +OP4 E0392C 0 +OP4 E0392D 0 +OP4 E0392E 0 +OP4 E0392F 0 +OP4 E03930 0 +OP4 E03931 0 +OP4 E03932 0 +OP4 E03933 0 +OP4 E03934 0 +OP4 E03935 0 +OP4 E03936 0 +OP4 E03937 0 +OP4 E03938 0 +OP4 E03939 0 +OP4 E0393A 0 +OP4 E0393B 0 +OP4 E0393C 0 +OP4 E0393D 0 +OP4 E0393E 0 +OP4 E0393F 0 +OP4 E03940 0 +OP4 E03941 0 +OP4 E03942 0 +OP4 E03943 0 +OP4 E03944 0 +OP4 E03945 0 +OP4 E03946 0 +OP4 E03947 0 +OP4 E03948 0 +OP4 E03949 0 +OP4 E0394A 0 +OP4 E0394B 0 +OP4 E0394C 0 +OP4 E0394D 0 +OP4 E0394E 0 +OP4 E0394F 0 +OP4 E03950 0 +OP4 E03951 0 +OP4 E03952 0 +OP4 E03953 0 +OP4 E03954 0 +OP4 E03955 0 +OP4 E03956 0 +OP4 E03957 0 +OP4 E03958 0 +OP4 E03959 0 +OP4 E0395A 0 +OP4 E0395B 0 +OP4 E0395C 0 +OP4 E0395D 0 +OP4 E0395E 0 +OP4 E0395F 0 +OP4 E03960 0 +OP4 E03961 0 +OP4 E03962 0 +OP4 E03963 0 +OP4 E03964 0 +OP4 E03965 0 +OP4 E03966 0 +OP4 E03967 0 +OP4 E03968 0 +OP4 E03969 0 +OP4 E0396A 0 +OP4 E0396B 0 +OP4 E0396C 0 +OP4 E0396D 0 +OP4 E0396E 0 +OP4 E0396F 0 +OP4 E03970 0 +OP4 E03971 0 +OP4 E03972 0 +OP4 E03973 0 +OP4 E03974 0 +OP4 E03975 0 +OP4 E03976 0 +OP4 E03977 0 +OP4 E03978 0 +OP4 E03979 0 +OP4 E0397A 0 +OP4 E0397B 0 +OP4 E0397C 0 +OP4 E0397D 0 +OP4 E0397E 0 +OP4 E0397F 0 +OP4 E03980 0 +OP4 E03981 0 +OP4 E03982 0 +OP4 E03983 0 +OP4 E03984 0 +OP4 E03985 0 +OP4 E03986 0 +OP4 E03987 0 +OP4 E03988 0 +OP4 E03989 0 +OP4 E0398A 0 +OP4 E0398B 0 +OP4 E0398C 0 +OP4 E0398D 0 +OP4 E0398E 0 +OP4 E0398F 0 +OP4 E03990 0 +OP4 E03991 0 +OP4 E03992 0 +OP4 E03993 0 +OP4 E03994 0 +OP4 E03995 0 +OP4 E03996 0 +OP4 E03997 0 +OP4 E03998 0 +OP4 E03999 0 +OP4 E0399A 0 +OP4 E0399B 0 +OP4 E0399C 0 +OP4 E0399D 0 +OP4 E0399E 0 +OP4 E0399F 0 +OP4 E039A0 0 +OP4 E039A1 0 +OP4 E039A2 0 +OP4 E039A3 0 +OP4 E039A4 0 +OP4 E039A5 0 +OP4 E039A6 0 +OP4 E039A7 0 +OP4 E039A8 0 +OP4 E039A9 0 +OP4 E039AA 0 +OP4 E039AB 0 +OP4 E039AC 0 +OP4 E039AD 0 +OP4 E039AE 0 +OP4 E039AF 0 +OP4 E039B0 0 +OP4 E039B1 0 +OP4 E039B2 0 +OP4 E039B3 0 +OP4 E039B4 0 +OP4 E039B5 0 +OP4 E039B6 0 +OP4 E039B7 0 +OP4 E039B8 0 +OP4 E039B9 0 +OP4 E039BA 0 +OP4 E039BB 0 +OP4 E039BC 0 +OP4 E039BD 0 +OP4 E039BE 0 +OP4 E039BF 0 +OP4 E039C0 0 +OP4 E039C1 0 +OP4 E039C2 0 +OP4 E039C3 0 +OP4 E039C4 0 +OP4 E039C5 0 +OP4 E039C6 0 +OP4 E039C7 0 +OP4 E039C8 0 +OP4 E039C9 0 +OP4 E039CA 0 +OP4 E039CB 0 +OP4 E039CC 0 +OP4 E039CD 0 +OP4 E039CE 0 +OP4 E039CF 0 +OP4 E039D0 0 +OP4 E039D1 0 +OP4 E039D2 0 +OP4 E039D3 0 +OP4 E039D4 0 +OP4 E039D5 0 +OP4 E039D6 0 +OP4 E039D7 0 +OP4 E039D8 0 +OP4 E039D9 0 +OP4 E039DA 0 +OP4 E039DB 0 +OP4 E039DC 0 +OP4 E039DD 0 +OP4 E039DE 0 +OP4 E039DF 0 +OP4 E039E0 0 +OP4 E039E1 0 +OP4 E039E2 0 +OP4 E039E3 0 +OP4 E039E4 0 +OP4 E039E5 0 +OP4 E039E6 0 +OP4 E039E7 0 +OP4 E039E8 0 +OP4 E039E9 0 +OP4 E039EA 0 +OP4 E039EB 0 +OP4 E039EC 0 +OP4 E039ED 0 +OP4 E039EE 0 +OP4 E039EF 0 +OP4 E039F0 0 +OP4 E039F1 0 +OP4 E039F2 0 +OP4 E039F3 0 +OP4 E039F4 0 +OP4 E039F5 0 +OP4 E039F6 0 +OP4 E039F7 0 +OP4 E039F8 0 +OP4 E039F9 0 +OP4 E039FA 0 +OP4 E039FB 0 +OP4 E039FC 0 +OP4 E039FD 0 +OP4 E039FE 0 +OP4 E039FF 0 +OP4 E03A00 0 +OP4 E03A01 0 +OP4 E03A02 0 +OP4 E03A03 0 +OP4 E03A04 0 +OP4 E03A05 0 +OP4 E03A06 0 +OP4 E03A07 0 +OP4 E03A08 0 +OP4 E03A09 0 +OP4 E03A0A 0 +OP4 E03A0B 0 +OP4 E03A0C 0 +OP4 E03A0D 0 +OP4 E03A0E 0 +OP4 E03A0F 0 +OP4 E03A10 0 +OP4 E03A11 0 +OP4 E03A12 0 +OP4 E03A13 0 +OP4 E03A14 0 +OP4 E03A15 0 +OP4 E03A16 0 +OP4 E03A17 0 +OP4 E03A18 0 +OP4 E03A19 0 +OP4 E03A1A 0 +OP4 E03A1B 0 +OP4 E03A1C 0 +OP4 E03A1D 0 +OP4 E03A1E 0 +OP4 E03A1F 0 +OP4 E03A20 0 +OP4 E03A21 0 +OP4 E03A22 0 +OP4 E03A23 0 +OP4 E03A24 0 +OP4 E03A25 0 +OP4 E03A26 0 +OP4 E03A27 0 +OP4 E03A28 0 +OP4 E03A29 0 +OP4 E03A2A 0 +OP4 E03A2B 0 +OP4 E03A2C 0 +OP4 E03A2D 0 +OP4 E03A2E 0 +OP4 E03A2F 0 +OP4 E03A30 0 +OP4 E03A31 0 +OP4 E03A32 0 +OP4 E03A33 0 +OP4 E03A34 0 +OP4 E03A35 0 +OP4 E03A36 0 +OP4 E03A37 0 +OP4 E03A38 0 +OP4 E03A39 0 +OP4 E03A3A 0 +OP4 E03A3B 0 +OP4 E03A3C 0 +OP4 E03A3D 0 +OP4 E03A3E 0 +OP4 E03A3F 0 +OP4 E03A40 0 +OP4 E03A41 0 +OP4 E03A42 0 +OP4 E03A43 0 +OP4 E03A44 0 +OP4 E03A45 0 +OP4 E03A46 0 +OP4 E03A47 0 +OP4 E03A48 0 +OP4 E03A49 0 +OP4 E03A4A 0 +OP4 E03A4B 0 +OP4 E03A4C 0 +OP4 E03A4D 0 +OP4 E03A4E 0 +OP4 E03A4F 0 +OP4 E03A50 0 +OP4 E03A51 0 +OP4 E03A52 0 +OP4 E03A53 0 +OP4 E03A54 0 +OP4 E03A55 0 +OP4 E03A56 0 +OP4 E03A57 0 +OP4 E03A58 0 +OP4 E03A59 0 +OP4 E03A5A 0 +OP4 E03A5B 0 +OP4 E03A5C 0 +OP4 E03A5D 0 +OP4 E03A5E 0 +OP4 E03A5F 0 +OP4 E03A60 0 +OP4 E03A61 0 +OP4 E03A62 0 +OP4 E03A63 0 +OP4 E03A64 0 +OP4 E03A65 0 +OP4 E03A66 0 +OP4 E03A67 0 +OP4 E03A68 0 +OP4 E03A69 0 +OP4 E03A6A 0 +OP4 E03A6B 0 +OP4 E03A6C 0 +OP4 E03A6D 0 +OP4 E03A6E 0 +OP4 E03A6F 0 +OP4 E03A70 0 +OP4 E03A71 0 +OP4 E03A72 0 +OP4 E03A73 0 +OP4 E03A74 0 +OP4 E03A75 0 +OP4 E03A76 0 +OP4 E03A77 0 +OP4 E03A78 0 +OP4 E03A79 0 +OP4 E03A7A 0 +OP4 E03A7B 0 +OP4 E03A7C 0 +OP4 E03A7D 0 +OP4 E03A7E 0 +OP4 E03A7F 0 +OP4 E03A80 0 +OP4 E03A81 0 +OP4 E03A82 0 +OP4 E03A83 0 +OP4 E03A84 0 +OP4 E03A85 0 +OP4 E03A86 0 +OP4 E03A87 0 +OP4 E03A88 0 +OP4 E03A89 0 +OP4 E03A8A 0 +OP4 E03A8B 0 +OP4 E03A8C 0 +OP4 E03A8D 0 +OP4 E03A8E 0 +OP4 E03A8F 0 +OP4 E03A90 0 +OP4 E03A91 0 +OP4 E03A92 0 +OP4 E03A93 0 +OP4 E03A94 0 +OP4 E03A95 0 +OP4 E03A96 0 +OP4 E03A97 0 +OP4 E03A98 0 +OP4 E03A99 0 +OP4 E03A9A 0 +OP4 E03A9B 0 +OP4 E03A9C 0 +OP4 E03A9D 0 +OP4 E03A9E 0 +OP4 E03A9F 0 +OP4 E03AA0 0 +OP4 E03AA1 0 +OP4 E03AA2 0 +OP4 E03AA3 0 +OP4 E03AA4 0 +OP4 E03AA5 0 +OP4 E03AA6 0 +OP4 E03AA7 0 +OP4 E03AA8 0 +OP4 E03AA9 0 +OP4 E03AAA 0 +OP4 E03AAB 0 +OP4 E03AAC 0 +OP4 E03AAD 0 +OP4 E03AAE 0 +OP4 E03AAF 0 +OP4 E03AB0 0 +OP4 E03AB1 0 +OP4 E03AB2 0 +OP4 E03AB3 0 +OP4 E03AB4 0 +OP4 E03AB5 0 +OP4 E03AB6 0 +OP4 E03AB7 0 +OP4 E03AB8 0 +OP4 E03AB9 0 +OP4 E03ABA 0 +OP4 E03ABB 0 +OP4 E03ABC 0 +OP4 E03ABD 0 +OP4 E03ABE 0 +OP4 E03ABF 0 +OP4 E03AC0 0 +OP4 E03AC1 0 +OP4 E03AC2 0 +OP4 E03AC3 0 +OP4 E03AC4 0 +OP4 E03AC5 0 +OP4 E03AC6 0 +OP4 E03AC7 0 +OP4 E03AC8 0 +OP4 E03AC9 0 +OP4 E03ACA 0 +OP4 E03ACB 0 +OP4 E03ACC 0 +OP4 E03ACD 0 +OP4 E03ACE 0 +OP4 E03ACF 0 +OP4 E03AD0 0 +OP4 E03AD1 0 +OP4 E03AD2 0 +OP4 E03AD3 0 +OP4 E03AD4 0 +OP4 E03AD5 0 +OP4 E03AD6 0 +OP4 E03AD7 0 +OP4 E03AD8 0 +OP4 E03AD9 0 +OP4 E03ADA 0 +OP4 E03ADB 0 +OP4 E03ADC 0 +OP4 E03ADD 0 +OP4 E03ADE 0 +OP4 E03ADF 0 +OP4 E03AE0 0 +OP4 E03AE1 0 +OP4 E03AE2 0 +OP4 E03AE3 0 +OP4 E03AE4 0 +OP4 E03AE5 0 +OP4 E03AE6 0 +OP4 E03AE7 0 +OP4 E03AE8 0 +OP4 E03AE9 0 +OP4 E03AEA 0 +OP4 E03AEB 0 +OP4 E03AEC 0 +OP4 E03AED 0 +OP4 E03AEE 0 +OP4 E03AEF 0 +OP4 E03AF0 0 +OP4 E03AF1 0 +OP4 E03AF2 0 +OP4 E03AF3 0 +OP4 E03AF4 0 +OP4 E03AF5 0 +OP4 E03AF6 0 +OP4 E03AF7 0 +OP4 E03AF8 0 +OP4 E03AF9 0 +OP4 E03AFA 0 +OP4 E03AFB 0 +OP4 E03AFC 0 +OP4 E03AFD 0 +OP4 E03AFE 0 +OP4 E03AFF 0 +OP4 E03B00 0 +OP4 E03B01 0 +OP4 E03B02 0 +OP4 E03B03 0 +OP4 E03B04 0 +OP4 E03B05 0 +OP4 E03B06 0 +OP4 E03B07 0 +OP4 E03B08 0 +OP4 E03B09 0 +OP4 E03B0A 0 +OP4 E03B0B 0 +OP4 E03B0C 0 +OP4 E03B0D 0 +OP4 E03B0E 0 +OP4 E03B0F 0 +OP4 E03B10 0 +OP4 E03B11 0 +OP4 E03B12 0 +OP4 E03B13 0 +OP4 E03B14 0 +OP4 E03B15 0 +OP4 E03B16 0 +OP4 E03B17 0 +OP4 E03B18 0 +OP4 E03B19 0 +OP4 E03B1A 0 +OP4 E03B1B 0 +OP4 E03B1C 0 +OP4 E03B1D 0 +OP4 E03B1E 0 +OP4 E03B1F 0 +OP4 E03B20 0 +OP4 E03B21 0 +OP4 E03B22 0 +OP4 E03B23 0 +OP4 E03B24 0 +OP4 E03B25 0 +OP4 E03B26 0 +OP4 E03B27 0 +OP4 E03B28 0 +OP4 E03B29 0 +OP4 E03B2A 0 +OP4 E03B2B 0 +OP4 E03B2C 0 +OP4 E03B2D 0 +OP4 E03B2E 0 +OP4 E03B2F 0 +OP4 E03B30 0 +OP4 E03B31 0 +OP4 E03B32 0 +OP4 E03B33 0 +OP4 E03B34 0 +OP4 E03B35 0 +OP4 E03B36 0 +OP4 E03B37 0 +OP4 E03B38 0 +OP4 E03B39 0 +OP4 E03B3A 0 +OP4 E03B3B 0 +OP4 E03B3C 0 +OP4 E03B3D 0 +OP4 E03B3E 0 +OP4 E03B3F 0 +OP4 E03B40 0 +OP4 E03B41 0 +OP4 E03B42 0 +OP4 E03B43 0 +OP4 E03B44 0 +OP4 E03B45 0 +OP4 E03B46 0 +OP4 E03B47 0 +OP4 E03B48 0 +OP4 E03B49 0 +OP4 E03B4A 0 +OP4 E03B4B 0 +OP4 E03B4C 0 +OP4 E03B4D 0 +OP4 E03B4E 0 +OP4 E03B4F 0 +OP4 E03B50 0 +OP4 E03B51 0 +OP4 E03B52 0 +OP4 E03B53 0 +OP4 E03B54 0 +OP4 E03B55 0 +OP4 E03B56 0 +OP4 E03B57 0 +OP4 E03B58 0 +OP4 E03B59 0 +OP4 E03B5A 0 +OP4 E03B5B 0 +OP4 E03B5C 0 +OP4 E03B5D 0 +OP4 E03B5E 0 +OP4 E03B5F 0 +OP4 E03B60 0 +OP4 E03B61 0 +OP4 E03B62 0 +OP4 E03B63 0 +OP4 E03B64 0 +OP4 E03B65 0 +OP4 E03B66 0 +OP4 E03B67 0 +OP4 E03B68 0 +OP4 E03B69 0 +OP4 E03B6A 0 +OP4 E03B6B 0 +OP4 E03B6C 0 +OP4 E03B6D 0 +OP4 E03B6E 0 +OP4 E03B6F 0 +OP4 E03B70 0 +OP4 E03B71 0 +OP4 E03B72 0 +OP4 E03B73 0 +OP4 E03B74 0 +OP4 E03B75 0 +OP4 E03B76 0 +OP4 E03B77 0 +OP4 E03B78 0 +OP4 E03B79 0 +OP4 E03B7A 0 +OP4 E03B7B 0 +OP4 E03B7C 0 +OP4 E03B7D 0 +OP4 E03B7E 0 +OP4 E03B7F 0 +OP4 E03B80 0 +OP4 E03B81 0 +OP4 E03B82 0 +OP4 E03B83 0 +OP4 E03B84 0 +OP4 E03B85 0 +OP4 E03B86 0 +OP4 E03B87 0 +OP4 E03B88 0 +OP4 E03B89 0 +OP4 E03B8A 0 +OP4 E03B8B 0 +OP4 E03B8C 0 +OP4 E03B8D 0 +OP4 E03B8E 0 +OP4 E03B8F 0 +OP4 E03B90 0 +OP4 E03B91 0 +OP4 E03B92 0 +OP4 E03B93 0 +OP4 E03B94 0 +OP4 E03B95 0 +OP4 E03B96 0 +OP4 E03B97 0 +OP4 E03B98 0 +OP4 E03B99 0 +OP4 E03B9A 0 +OP4 E03B9B 0 +OP4 E03B9C 0 +OP4 E03B9D 0 +OP4 E03B9E 0 +OP4 E03B9F 0 +OP4 E03BA0 0 +OP4 E03BA1 0 +OP4 E03BA2 0 +OP4 E03BA3 0 +OP4 E03BA4 0 +OP4 E03BA5 0 +OP4 E03BA6 0 +OP4 E03BA7 0 +OP4 E03BA8 0 +OP4 E03BA9 0 +OP4 E03BAA 0 +OP4 E03BAB 0 +OP4 E03BAC 0 +OP4 E03BAD 0 +OP4 E03BAE 0 +OP4 E03BAF 0 +OP4 E03BB0 0 +OP4 E03BB1 0 +OP4 E03BB2 0 +OP4 E03BB3 0 +OP4 E03BB4 0 +OP4 E03BB5 0 +OP4 E03BB6 0 +OP4 E03BB7 0 +OP4 E03BB8 0 +OP4 E03BB9 0 +OP4 E03BBA 0 +OP4 E03BBB 0 +OP4 E03BBC 0 +OP4 E03BBD 0 +OP4 E03BBE 0 +OP4 E03BBF 0 +OP4 E03BC0 0 +OP4 E03BC1 0 +OP4 E03BC2 0 +OP4 E03BC3 0 +OP4 E03BC4 0 +OP4 E03BC5 0 +OP4 E03BC6 0 +OP4 E03BC7 0 +OP4 E03BC8 0 +OP4 E03BC9 0 +OP4 E03BCA 0 +OP4 E03BCB 0 +OP4 E03BCC 0 +OP4 E03BCD 0 +OP4 E03BCE 0 +OP4 E03BCF 0 +OP4 E03BD0 0 +OP4 E03BD1 0 +OP4 E03BD2 0 +OP4 E03BD3 0 +OP4 E03BD4 0 +OP4 E03BD5 0 +OP4 E03BD6 0 +OP4 E03BD7 0 +OP4 E03BD8 0 +OP4 E03BD9 0 +OP4 E03BDA 0 +OP4 E03BDB 0 +OP4 E03BDC 0 +OP4 E03BDD 0 +OP4 E03BDE 0 +OP4 E03BDF 0 +OP4 E03BE0 0 +OP4 E03BE1 0 +OP4 E03BE2 0 +OP4 E03BE3 0 +OP4 E03BE4 0 +OP4 E03BE5 0 +OP4 E03BE6 0 +OP4 E03BE7 0 +OP4 E03BE8 0 +OP4 E03BE9 0 +OP4 E03BEA 0 +OP4 E03BEB 0 +OP4 E03BEC 0 +OP4 E03BED 0 +OP4 E03BEE 0 +OP4 E03BEF 0 +OP4 E03BF0 0 +OP4 E03BF1 0 +OP4 E03BF2 0 +OP4 E03BF3 0 +OP4 E03BF4 0 +OP4 E03BF5 0 +OP4 E03BF6 0 +OP4 E03BF7 0 +OP4 E03BF8 0 +OP4 E03BF9 0 +OP4 E03BFA 0 +OP4 E03BFB 0 +OP4 E03BFC 0 +OP4 E03BFD 0 +OP4 E03BFE 0 +OP4 E03BFF 0 +OP4 E03C00 0 +OP4 E03C01 0 +OP4 E03C02 0 +OP4 E03C03 0 +OP4 E03C04 0 +OP4 E03C05 0 +OP4 E03C06 0 +OP4 E03C07 0 +OP4 E03C08 0 +OP4 E03C09 0 +OP4 E03C0A 0 +OP4 E03C0B 0 +OP4 E03C0C 0 +OP4 E03C0D 0 +OP4 E03C0E 0 +OP4 E03C0F 0 +OP4 E03C10 0 +OP4 E03C11 0 +OP4 E03C12 0 +OP4 E03C13 0 +OP4 E03C14 0 +OP4 E03C15 0 +OP4 E03C16 0 +OP4 E03C17 0 +OP4 E03C18 0 +OP4 E03C19 0 +OP4 E03C1A 0 +OP4 E03C1B 0 +OP4 E03C1C 0 +OP4 E03C1D 0 +OP4 E03C1E 0 +OP4 E03C1F 0 +OP4 E03C20 0 +OP4 E03C21 0 +OP4 E03C22 0 +OP4 E03C23 0 +OP4 E03C24 0 +OP4 E03C25 0 +OP4 E03C26 0 +OP4 E03C27 0 +OP4 E03C28 0 +OP4 E03C29 0 +OP4 E03C2A 0 +OP4 E03C2B 0 +OP4 E03C2C 0 +OP4 E03C2D 0 +OP4 E03C2E 0 +OP4 E03C2F 0 +OP4 E03C30 0 +OP4 E03C31 0 +OP4 E03C32 0 +OP4 E03C33 0 +OP4 E03C34 0 +OP4 E03C35 0 +OP4 E03C36 0 +OP4 E03C37 0 +OP4 E03C38 0 +OP4 E03C39 0 +OP4 E03C3A 0 +OP4 E03C3B 0 +OP4 E03C3C 0 +OP4 E03C3D 0 +OP4 E03C3E 0 +OP4 E03C3F 0 +OP4 E03C40 0 +OP4 E03C41 0 +OP4 E03C42 0 +OP4 E03C43 0 +OP4 E03C44 0 +OP4 E03C45 0 +OP4 E03C46 0 +OP4 E03C47 0 +OP4 E03C48 0 +OP4 E03C49 0 +OP4 E03C4A 0 +OP4 E03C4B 0 +OP4 E03C4C 0 +OP4 E03C4D 0 +OP4 E03C4E 0 +OP4 E03C4F 0 +OP4 E03C50 0 +OP4 E03C51 0 +OP4 E03C52 0 +OP4 E03C53 0 +OP4 E03C54 0 +OP4 E03C55 0 +OP4 E03C56 0 +OP4 E03C57 0 +OP4 E03C58 0 +OP4 E03C59 0 +OP4 E03C5A 0 +OP4 E03C5B 0 +OP4 E03C5C 0 +OP4 E03C5D 0 +OP4 E03C5E 0 +OP4 E03C5F 0 +OP4 E03C60 0 +OP4 E03C61 0 +OP4 E03C62 0 +OP4 E03C63 0 +OP4 E03C64 0 +OP4 E03C65 0 +OP4 E03C66 0 +OP4 E03C67 0 +OP4 E03C68 0 +OP4 E03C69 0 +OP4 E03C6A 0 +OP4 E03C6B 0 +OP4 E03C6C 0 +OP4 E03C6D 0 +OP4 E03C6E 0 +OP4 E03C6F 0 +OP4 E03C70 0 +OP4 E03C71 0 +OP4 E03C72 0 +OP4 E03C73 0 +OP4 E03C74 0 +OP4 E03C75 0 +OP4 E03C76 0 +OP4 E03C77 0 +OP4 E03C78 0 +OP4 E03C79 0 +OP4 E03C7A 0 +OP4 E03C7B 0 +OP4 E03C7C 0 +OP4 E03C7D 0 +OP4 E03C7E 0 +OP4 E03C7F 0 +OP4 E03C80 0 +OP4 E03C81 0 +OP4 E03C82 0 +OP4 E03C83 0 +OP4 E03C84 0 +OP4 E03C85 0 +OP4 E03C86 0 +OP4 E03C87 0 +OP4 E03C88 0 +OP4 E03C89 0 +OP4 E03C8A 0 +OP4 E03C8B 0 +OP4 E03C8C 0 +OP4 E03C8D 0 +OP4 E03C8E 0 +OP4 E03C8F 0 +OP4 E03C90 0 +OP4 E03C91 0 +OP4 E03C92 0 +OP4 E03C93 0 +OP4 E03C94 0 +OP4 E03C95 0 +OP4 E03C96 0 +OP4 E03C97 0 +OP4 E03C98 0 +OP4 E03C99 0 +OP4 E03C9A 0 +OP4 E03C9B 0 +OP4 E03C9C 0 +OP4 E03C9D 0 +OP4 E03C9E 0 +OP4 E03C9F 0 +OP4 E03CA0 0 +OP4 E03CA1 0 +OP4 E03CA2 0 +OP4 E03CA3 0 +OP4 E03CA4 0 +OP4 E03CA5 0 +OP4 E03CA6 0 +OP4 E03CA7 0 +OP4 E03CA8 0 +OP4 E03CA9 0 +OP4 E03CAA 0 +OP4 E03CAB 0 +OP4 E03CAC 0 +OP4 E03CAD 0 +OP4 E03CAE 0 +OP4 E03CAF 0 +OP4 E03CB0 0 +OP4 E03CB1 0 +OP4 E03CB2 0 +OP4 E03CB3 0 +OP4 E03CB4 0 +OP4 E03CB5 0 +OP4 E03CB6 0 +OP4 E03CB7 0 +OP4 E03CB8 0 +OP4 E03CB9 0 +OP4 E03CBA 0 +OP4 E03CBB 0 +OP4 E03CBC 0 +OP4 E03CBD 0 +OP4 E03CBE 0 +OP4 E03CBF 0 +OP4 E03CC0 0 +OP4 E03CC1 0 +OP4 E03CC2 0 +OP4 E03CC3 0 +OP4 E03CC4 0 +OP4 E03CC5 0 +OP4 E03CC6 0 +OP4 E03CC7 0 +OP4 E03CC8 0 +OP4 E03CC9 0 +OP4 E03CCA 0 +OP4 E03CCB 0 +OP4 E03CCC 0 +OP4 E03CCD 0 +OP4 E03CCE 0 +OP4 E03CCF 0 +OP4 E03CD0 0 +OP4 E03CD1 0 +OP4 E03CD2 0 +OP4 E03CD3 0 +OP4 E03CD4 0 +OP4 E03CD5 0 +OP4 E03CD6 0 +OP4 E03CD7 0 +OP4 E03CD8 0 +OP4 E03CD9 0 +OP4 E03CDA 0 +OP4 E03CDB 0 +OP4 E03CDC 0 +OP4 E03CDD 0 +OP4 E03CDE 0 +OP4 E03CDF 0 +OP4 E03CE0 0 +OP4 E03CE1 0 +OP4 E03CE2 0 +OP4 E03CE3 0 +OP4 E03CE4 0 +OP4 E03CE5 0 +OP4 E03CE6 0 +OP4 E03CE7 0 +OP4 E03CE8 0 +OP4 E03CE9 0 +OP4 E03CEA 0 +OP4 E03CEB 0 +OP4 E03CEC 0 +OP4 E03CED 0 +OP4 E03CEE 0 +OP4 E03CEF 0 +OP4 E03CF0 0 +OP4 E03CF1 0 +OP4 E03CF2 0 +OP4 E03CF3 0 +OP4 E03CF4 0 +OP4 E03CF5 0 +OP4 E03CF6 0 +OP4 E03CF7 0 +OP4 E03CF8 0 +OP4 E03CF9 0 +OP4 E03CFA 0 +OP4 E03CFB 0 +OP4 E03CFC 0 +OP4 E03CFD 0 +OP4 E03CFE 0 +OP4 E03CFF 0 +OP4 E03D00 0 +OP4 E03D01 0 +OP4 E03D02 0 +OP4 E03D03 0 +OP4 E03D04 0 +OP4 E03D05 0 +OP4 E03D06 0 +OP4 E03D07 0 +OP4 E03D08 0 +OP4 E03D09 0 +OP4 E03D0A 0 +OP4 E03D0B 0 +OP4 E03D0C 0 +OP4 E03D0D 0 +OP4 E03D0E 0 +OP4 E03D0F 0 +OP4 E03D10 0 +OP4 E03D11 0 +OP4 E03D12 0 +OP4 E03D13 0 +OP4 E03D14 0 +OP4 E03D15 0 +OP4 E03D16 0 +OP4 E03D17 0 +OP4 E03D18 0 +OP4 E03D19 0 +OP4 E03D1A 0 +OP4 E03D1B 0 +OP4 E03D1C 0 +OP4 E03D1D 0 +OP4 E03D1E 0 +OP4 E03D1F 0 +OP4 E03D20 0 +OP4 E03D21 0 +OP4 E03D22 0 +OP4 E03D23 0 +OP4 E03D24 0 +OP4 E03D25 0 +OP4 E03D26 0 +OP4 E03D27 0 +OP4 E03D28 0 +OP4 E03D29 0 +OP4 E03D2A 0 +OP4 E03D2B 0 +OP4 E03D2C 0 +OP4 E03D2D 0 +OP4 E03D2E 0 +OP4 E03D2F 0 +OP4 E03D30 0 +OP4 E03D31 0 +OP4 E03D32 0 +OP4 E03D33 0 +OP4 E03D34 0 +OP4 E03D35 0 +OP4 E03D36 0 +OP4 E03D37 0 +OP4 E03D38 0 +OP4 E03D39 0 +OP4 E03D3A 0 +OP4 E03D3B 0 +OP4 E03D3C 0 +OP4 E03D3D 0 +OP4 E03D3E 0 +OP4 E03D3F 0 +OP4 E03D40 0 +OP4 E03D41 0 +OP4 E03D42 0 +OP4 E03D43 0 +OP4 E03D44 0 +OP4 E03D45 0 +OP4 E03D46 0 +OP4 E03D47 0 +OP4 E03D48 0 +OP4 E03D49 0 +OP4 E03D4A 0 +OP4 E03D4B 0 +OP4 E03D4C 0 +OP4 E03D4D 0 +OP4 E03D4E 0 +OP4 E03D4F 0 +OP4 E03D50 0 +OP4 E03D51 0 +OP4 E03D52 0 +OP4 E03D53 0 +OP4 E03D54 0 +OP4 E03D55 0 +OP4 E03D56 0 +OP4 E03D57 0 +OP4 E03D58 0 +OP4 E03D59 0 +OP4 E03D5A 0 +OP4 E03D5B 0 +OP4 E03D5C 0 +OP4 E03D5D 0 +OP4 E03D5E 0 +OP4 E03D5F 0 +OP4 E03D60 0 +OP4 E03D61 0 +OP4 E03D62 0 +OP4 E03D63 0 +OP4 E03D64 0 +OP4 E03D65 0 +OP4 E03D66 0 +OP4 E03D67 0 +OP4 E03D68 0 +OP4 E03D69 0 +OP4 E03D6A 0 +OP4 E03D6B 0 +OP4 E03D6C 0 +OP4 E03D6D 0 +OP4 E03D6E 0 +OP4 E03D6F 0 +OP4 E03D70 0 +OP4 E03D71 0 +OP4 E03D72 0 +OP4 E03D73 0 +OP4 E03D74 0 +OP4 E03D75 0 +OP4 E03D76 0 +OP4 E03D77 0 +OP4 E03D78 0 +OP4 E03D79 0 +OP4 E03D7A 0 +OP4 E03D7B 0 +OP4 E03D7C 0 +OP4 E03D7D 0 +OP4 E03D7E 0 +OP4 E03D7F 0 +OP4 E03D80 0 +OP4 E03D81 0 +OP4 E03D82 0 +OP4 E03D83 0 +OP4 E03D84 0 +OP4 E03D85 0 +OP4 E03D86 0 +OP4 E03D87 0 +OP4 E03D88 0 +OP4 E03D89 0 +OP4 E03D8A 0 +OP4 E03D8B 0 +OP4 E03D8C 0 +OP4 E03D8D 0 +OP4 E03D8E 0 +OP4 E03D8F 0 +OP4 E03D90 0 +OP4 E03D91 0 +OP4 E03D92 0 +OP4 E03D93 0 +OP4 E03D94 0 +OP4 E03D95 0 +OP4 E03D96 0 +OP4 E03D97 0 +OP4 E03D98 0 +OP4 E03D99 0 +OP4 E03D9A 0 +OP4 E03D9B 0 +OP4 E03D9C 0 +OP4 E03D9D 0 +OP4 E03D9E 0 +OP4 E03D9F 0 +OP4 E03DA0 0 +OP4 E03DA1 0 +OP4 E03DA2 0 +OP4 E03DA3 0 +OP4 E03DA4 0 +OP4 E03DA5 0 +OP4 E03DA6 0 +OP4 E03DA7 0 +OP4 E03DA8 0 +OP4 E03DA9 0 +OP4 E03DAA 0 +OP4 E03DAB 0 +OP4 E03DAC 0 +OP4 E03DAD 0 +OP4 E03DAE 0 +OP4 E03DAF 0 +OP4 E03DB0 0 +OP4 E03DB1 0 +OP4 E03DB2 0 +OP4 E03DB3 0 +OP4 E03DB4 0 +OP4 E03DB5 0 +OP4 E03DB6 0 +OP4 E03DB7 0 +OP4 E03DB8 0 +OP4 E03DB9 0 +OP4 E03DBA 0 +OP4 E03DBB 0 +OP4 E03DBC 0 +OP4 E03DBD 0 +OP4 E03DBE 0 +OP4 E03DBF 0 +OP4 E03DC0 0 +OP4 E03DC1 0 +OP4 E03DC2 0 +OP4 E03DC3 0 +OP4 E03DC4 0 diff --git a/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum4_itrace_irisc2.cfg.ext b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum4_itrace_irisc2.cfg.ext new file mode 100644 index 000000000000..c5b04f09a951 --- /dev/null +++ b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum4_itrace_irisc2.cfg.ext @@ -0,0 +1,15814 @@ +OP1 Spectrum4 +OP4 ITRACE0 0 +OP4 ITRACE1 0 +OP4 ITRACE2 1 +OP4 ITRACE3 0 +OP4 ITRACE4 0 +OP4 ITRACE5 0 +OP4 ITRACE6 0 +OP4 ITRACE7 0 +OP4 ITRACE8 0 +OP4 ITRACE9 0 +OP4 Main_PhyUC 0 +OP4 TILE0_ITRACE0 0 +OP4 TILE0_ITRACE1 0 +OP4 TILE0_ITRACE2 0 +OP4 TILE0_ITRACE3 0 +OP4 TILE0_ITRACE4 0 +OP4 TILE0_PhyUC 0 +OP4 TILE1_ITRACE0 0 +OP4 TILE1_ITRACE1 0 +OP4 TILE1_ITRACE2 0 +OP4 TILE1_ITRACE3 0 +OP4 TILE1_ITRACE4 0 +OP4 TILE1_PhyUC 0 +OP4 TILE2_ITRACE0 0 +OP4 TILE2_ITRACE1 0 +OP4 TILE2_ITRACE2 0 +OP4 TILE2_ITRACE3 0 +OP4 TILE2_ITRACE4 0 +OP4 TILE2_PhyUC 0 +OP4 TILE3_ITRACE0 0 +OP4 TILE3_ITRACE1 0 +OP4 TILE3_ITRACE2 0 +OP4 TILE3_ITRACE3 0 +OP4 TILE3_ITRACE4 0 +OP4 TILE3_PhyUC 0 +OP4 TILE4_ITRACE0 0 +OP4 TILE4_ITRACE1 0 +OP4 TILE4_ITRACE2 0 +OP4 TILE4_ITRACE3 0 +OP4 TILE4_ITRACE4 0 +OP4 TILE4_PhyUC 0 +OP4 TILE5_ITRACE0 0 +OP4 TILE5_ITRACE1 0 +OP4 TILE5_ITRACE2 0 +OP4 TILE5_ITRACE3 0 +OP4 TILE5_ITRACE4 0 +OP4 TILE5_PhyUC 0 +OP4 TILE6_ITRACE0 0 +OP4 TILE6_ITRACE1 0 +OP4 TILE6_ITRACE2 0 +OP4 TILE6_ITRACE3 0 +OP4 TILE6_ITRACE4 0 +OP4 TILE6_PhyUC 0 +OP4 TILE7_ITRACE0 0 +OP4 TILE7_ITRACE1 0 +OP4 TILE7_ITRACE2 0 +OP4 TILE7_ITRACE3 0 +OP4 TILE7_ITRACE4 0 +OP4 TILE7_PhyUC 0 +OP4 E0003B 0 +OP4 E0003C 0 +OP4 E0003D 0 +OP4 E0003E 0 +OP4 E0003F 0 +OP4 E00040 0 +OP4 E00041 0 +OP4 E00042 0 +OP4 E00043 0 +OP4 E00044 0 +OP4 E00045 0 +OP4 E00046 0 +OP4 E00047 0 +OP4 E00048 0 +OP4 E00049 0 +OP4 E0004A 0 +OP4 E0004B 0 +OP4 E0004C 0 +OP4 E0004D 0 +OP4 E0004E 0 +OP4 E0004F 0 +OP4 E00050 0 +OP4 E00051 0 +OP4 E00052 0 +OP4 E00053 0 +OP4 E00054 0 +OP4 E00055 0 +OP4 E00056 0 +OP4 E00057 0 +OP4 E00058 0 +OP4 E00059 0 +OP4 E0005A 0 +OP4 E0005B 0 +OP4 E0005C 0 +OP4 E0005D 0 +OP4 E0005E 0 +OP4 E0005F 0 +OP4 E00060 0 +OP4 E00061 0 +OP4 E00062 0 +OP4 E00063 0 +OP4 E00064 0 +OP4 E00065 0 +OP4 E00066 0 +OP4 E00067 0 +OP4 E00068 0 +OP4 E00069 0 +OP4 E0006A 0 +OP4 E0006B 0 +OP4 E0006C 0 +OP4 E0006D 0 +OP4 E0006E 0 +OP4 E0006F 0 +OP4 E00070 0 +OP4 E00071 0 +OP4 E00072 0 +OP4 E00073 0 +OP4 E00074 0 +OP4 E00075 0 +OP4 E00076 0 +OP4 E00077 0 +OP4 E00078 0 +OP4 E00079 0 +OP4 E0007A 0 +OP4 E0007B 0 +OP4 E0007C 0 +OP4 E0007D 0 +OP4 E0007E 0 +OP4 E0007F 0 +OP4 E00080 0 +OP4 E00081 0 +OP4 E00082 0 +OP4 E00083 0 +OP4 E00084 0 +OP4 E00085 0 +OP4 E00086 0 +OP4 E00087 0 +OP4 E00088 0 +OP4 E00089 0 +OP4 E0008A 0 +OP4 E0008B 0 +OP4 E0008C 0 +OP4 E0008D 0 +OP4 E0008E 0 +OP4 E0008F 0 +OP4 E00090 0 +OP4 E00091 0 +OP4 E00092 0 +OP4 E00093 0 +OP4 E00094 0 +OP4 E00095 0 +OP4 E00096 0 +OP4 E00097 0 +OP4 E00098 0 +OP4 E00099 0 +OP4 E0009A 0 +OP4 E0009B 0 +OP4 E0009C 0 +OP4 E0009D 0 +OP4 E0009E 0 +OP4 E0009F 0 +OP4 E000A0 0 +OP4 E000A1 0 +OP4 E000A2 0 +OP4 E000A3 0 +OP4 E000A4 0 +OP4 E000A5 0 +OP4 E000A6 0 +OP4 E000A7 0 +OP4 E000A8 0 +OP4 E000A9 0 +OP4 E000AA 0 +OP4 E000AB 0 +OP4 E000AC 0 +OP4 E000AD 0 +OP4 E000AE 0 +OP4 E000AF 0 +OP4 E000B0 0 +OP4 E000B1 0 +OP4 E000B2 0 +OP4 E000B3 0 +OP4 E000B4 0 +OP4 E000B5 0 +OP4 E000B6 0 +OP4 E000B7 0 +OP4 E000B8 0 +OP4 E000B9 0 +OP4 E000BA 0 +OP4 E000BB 0 +OP4 E000BC 0 +OP4 E000BD 0 +OP4 E000BE 0 +OP4 E000BF 0 +OP4 E000C0 0 +OP4 E000C1 0 +OP4 E000C2 0 +OP4 E000C3 0 +OP4 E000C4 0 +OP4 E000C5 0 +OP4 E000C6 0 +OP4 E000C7 0 +OP4 E000C8 0 +OP4 E000C9 0 +OP4 E000CA 0 +OP4 E000CB 0 +OP4 E000CC 0 +OP4 E000CD 0 +OP4 E000CE 0 +OP4 E000CF 0 +OP4 E000D0 0 +OP4 E000D1 0 +OP4 E000D2 0 +OP4 E000D3 0 +OP4 E000D4 0 +OP4 E000D5 0 +OP4 E000D6 0 +OP4 E000D7 0 +OP4 E000D8 0 +OP4 E000D9 0 +OP4 E000DA 0 +OP4 E000DB 0 +OP4 E000DC 0 +OP4 E000DD 0 +OP4 E000DE 0 +OP4 E000DF 0 +OP4 E000E0 0 +OP4 E000E1 0 +OP4 E000E2 0 +OP4 E000E3 0 +OP4 E000E4 0 +OP4 E000E5 0 +OP4 E000E6 0 +OP4 E000E7 0 +OP4 E000E8 0 +OP4 E000E9 0 +OP4 E000EA 0 +OP4 E000EB 0 +OP4 E000EC 0 +OP4 E000ED 0 +OP4 E000EE 0 +OP4 E000EF 0 +OP4 E000F0 0 +OP4 E000F1 0 +OP4 E000F2 0 +OP4 E000F3 0 +OP4 E000F4 0 +OP4 E000F5 0 +OP4 E000F6 0 +OP4 E000F7 0 +OP4 E000F8 0 +OP4 E000F9 0 +OP4 E000FA 0 +OP4 E000FB 0 +OP4 E000FC 0 +OP4 E000FD 0 +OP4 E000FE 0 +OP4 E000FF 0 +OP4 E00100 0 +OP4 E00101 0 +OP4 E00102 0 +OP4 E00103 0 +OP4 E00104 0 +OP4 E00105 0 +OP4 E00106 0 +OP4 E00107 0 +OP4 E00108 0 +OP4 E00109 0 +OP4 E0010A 0 +OP4 E0010B 0 +OP4 E0010C 0 +OP4 E0010D 0 +OP4 E0010E 0 +OP4 E0010F 0 +OP4 E00110 0 +OP4 E00111 0 +OP4 E00112 0 +OP4 E00113 0 +OP4 E00114 0 +OP4 E00115 0 +OP4 E00116 0 +OP4 E00117 0 +OP4 E00118 0 +OP4 E00119 0 +OP4 E0011A 0 +OP4 E0011B 0 +OP4 E0011C 0 +OP4 E0011D 0 +OP4 E0011E 0 +OP4 E0011F 0 +OP4 E00120 0 +OP4 E00121 0 +OP4 E00122 0 +OP4 E00123 0 +OP4 E00124 0 +OP4 E00125 0 +OP4 E00126 0 +OP4 E00127 0 +OP4 E00128 0 +OP4 E00129 0 +OP4 E0012A 0 +OP4 E0012B 0 +OP4 E0012C 0 +OP4 E0012D 0 +OP4 E0012E 0 +OP4 E0012F 0 +OP4 E00130 0 +OP4 E00131 0 +OP4 E00132 0 +OP4 E00133 0 +OP4 E00134 0 +OP4 E00135 0 +OP4 E00136 0 +OP4 E00137 0 +OP4 E00138 0 +OP4 E00139 0 +OP4 E0013A 0 +OP4 E0013B 0 +OP4 E0013C 0 +OP4 E0013D 0 +OP4 E0013E 0 +OP4 E0013F 0 +OP4 E00140 0 +OP4 E00141 0 +OP4 E00142 0 +OP4 E00143 0 +OP4 E00144 0 +OP4 E00145 0 +OP4 E00146 0 +OP4 E00147 0 +OP4 E00148 0 +OP4 E00149 0 +OP4 E0014A 0 +OP4 E0014B 0 +OP4 E0014C 0 +OP4 E0014D 0 +OP4 E0014E 0 +OP4 E0014F 0 +OP4 E00150 0 +OP4 E00151 0 +OP4 E00152 0 +OP4 E00153 0 +OP4 E00154 0 +OP4 E00155 0 +OP4 E00156 0 +OP4 E00157 0 +OP4 E00158 0 +OP4 E00159 0 +OP4 E0015A 0 +OP4 E0015B 0 +OP4 E0015C 0 +OP4 E0015D 0 +OP4 E0015E 0 +OP4 E0015F 0 +OP4 E00160 0 +OP4 E00161 0 +OP4 E00162 0 +OP4 E00163 0 +OP4 E00164 0 +OP4 E00165 0 +OP4 E00166 0 +OP4 E00167 0 +OP4 E00168 0 +OP4 E00169 0 +OP4 E0016A 0 +OP4 E0016B 0 +OP4 E0016C 0 +OP4 E0016D 0 +OP4 E0016E 0 +OP4 E0016F 0 +OP4 E00170 0 +OP4 E00171 0 +OP4 E00172 0 +OP4 E00173 0 +OP4 E00174 0 +OP4 E00175 0 +OP4 E00176 0 +OP4 E00177 0 +OP4 E00178 0 +OP4 E00179 0 +OP4 E0017A 0 +OP4 E0017B 0 +OP4 E0017C 0 +OP4 E0017D 0 +OP4 E0017E 0 +OP4 E0017F 0 +OP4 E00180 0 +OP4 E00181 0 +OP4 E00182 0 +OP4 E00183 0 +OP4 E00184 0 +OP4 E00185 0 +OP4 E00186 0 +OP4 E00187 0 +OP4 E00188 0 +OP4 E00189 0 +OP4 E0018A 0 +OP4 E0018B 0 +OP4 E0018C 0 +OP4 E0018D 0 +OP4 E0018E 0 +OP4 E0018F 0 +OP4 E00190 0 +OP4 E00191 0 +OP4 E00192 0 +OP4 E00193 0 +OP4 E00194 0 +OP4 E00195 0 +OP4 E00196 0 +OP4 E00197 0 +OP4 E00198 0 +OP4 E00199 0 +OP4 E0019A 0 +OP4 E0019B 0 +OP4 E0019C 0 +OP4 E0019D 0 +OP4 E0019E 0 +OP4 E0019F 0 +OP4 E001A0 0 +OP4 E001A1 0 +OP4 E001A2 0 +OP4 E001A3 0 +OP4 E001A4 0 +OP4 E001A5 0 +OP4 E001A6 0 +OP4 E001A7 0 +OP4 E001A8 0 +OP4 E001A9 0 +OP4 E001AA 0 +OP4 E001AB 0 +OP4 E001AC 0 +OP4 E001AD 0 +OP4 E001AE 0 +OP4 E001AF 0 +OP4 E001B0 0 +OP4 E001B1 0 +OP4 E001B2 0 +OP4 E001B3 0 +OP4 E001B4 0 +OP4 E001B5 0 +OP4 E001B6 0 +OP4 E001B7 0 +OP4 E001B8 0 +OP4 E001B9 0 +OP4 E001BA 0 +OP4 E001BB 0 +OP4 E001BC 0 +OP4 E001BD 0 +OP4 E001BE 0 +OP4 E001BF 0 +OP4 E001C0 0 +OP4 E001C1 0 +OP4 E001C2 0 +OP4 E001C3 0 +OP4 E001C4 0 +OP4 E001C5 0 +OP4 E001C6 0 +OP4 E001C7 0 +OP4 E001C8 0 +OP4 E001C9 0 +OP4 E001CA 0 +OP4 E001CB 0 +OP4 E001CC 0 +OP4 E001CD 0 +OP4 E001CE 0 +OP4 E001CF 0 +OP4 E001D0 0 +OP4 E001D1 0 +OP4 E001D2 0 +OP4 E001D3 0 +OP4 E001D4 0 +OP4 E001D5 0 +OP4 E001D6 0 +OP4 E001D7 0 +OP4 E001D8 0 +OP4 E001D9 0 +OP4 E001DA 0 +OP4 E001DB 0 +OP4 E001DC 0 +OP4 E001DD 0 +OP4 E001DE 0 +OP4 E001DF 0 +OP4 E001E0 0 +OP4 E001E1 0 +OP4 E001E2 0 +OP4 E001E3 0 +OP4 E001E4 0 +OP4 E001E5 0 +OP4 E001E6 0 +OP4 E001E7 0 +OP4 E001E8 0 +OP4 E001E9 0 +OP4 E001EA 0 +OP4 E001EB 0 +OP4 E001EC 0 +OP4 E001ED 0 +OP4 E001EE 0 +OP4 E001EF 0 +OP4 E001F0 0 +OP4 E001F1 0 +OP4 E001F2 0 +OP4 E001F3 0 +OP4 E001F4 0 +OP4 E001F5 0 +OP4 E001F6 0 +OP4 E001F7 0 +OP4 E001F8 0 +OP4 E001F9 0 +OP4 E001FA 0 +OP4 E001FB 0 +OP4 E001FC 0 +OP4 E001FD 0 +OP4 E001FE 0 +OP4 E001FF 0 +OP4 E00200 0 +OP4 E00201 0 +OP4 E00202 0 +OP4 E00203 0 +OP4 E00204 0 +OP4 E00205 0 +OP4 E00206 0 +OP4 E00207 0 +OP4 E00208 0 +OP4 E00209 0 +OP4 E0020A 0 +OP4 E0020B 0 +OP4 E0020C 0 +OP4 E0020D 0 +OP4 E0020E 0 +OP4 E0020F 0 +OP4 E00210 0 +OP4 E00211 0 +OP4 E00212 0 +OP4 E00213 0 +OP4 E00214 0 +OP4 E00215 0 +OP4 E00216 0 +OP4 E00217 0 +OP4 E00218 0 +OP4 E00219 0 +OP4 E0021A 0 +OP4 E0021B 0 +OP4 E0021C 0 +OP4 E0021D 0 +OP4 E0021E 0 +OP4 E0021F 0 +OP4 E00220 0 +OP4 E00221 0 +OP4 E00222 0 +OP4 E00223 0 +OP4 E00224 0 +OP4 E00225 0 +OP4 E00226 0 +OP4 E00227 0 +OP4 E00228 0 +OP4 E00229 0 +OP4 E0022A 0 +OP4 E0022B 0 +OP4 E0022C 0 +OP4 E0022D 0 +OP4 E0022E 0 +OP4 E0022F 0 +OP4 E00230 0 +OP4 E00231 0 +OP4 E00232 0 +OP4 E00233 0 +OP4 E00234 0 +OP4 E00235 0 +OP4 E00236 0 +OP4 E00237 0 +OP4 E00238 0 +OP4 E00239 0 +OP4 E0023A 0 +OP4 E0023B 0 +OP4 E0023C 0 +OP4 E0023D 0 +OP4 E0023E 0 +OP4 E0023F 0 +OP4 E00240 0 +OP4 E00241 0 +OP4 E00242 0 +OP4 E00243 0 +OP4 E00244 0 +OP4 E00245 0 +OP4 E00246 0 +OP4 E00247 0 +OP4 E00248 0 +OP4 E00249 0 +OP4 E0024A 0 +OP4 E0024B 0 +OP4 E0024C 0 +OP4 E0024D 0 +OP4 E0024E 0 +OP4 E0024F 0 +OP4 E00250 0 +OP4 E00251 0 +OP4 E00252 0 +OP4 E00253 0 +OP4 E00254 0 +OP4 E00255 0 +OP4 E00256 0 +OP4 E00257 0 +OP4 E00258 0 +OP4 E00259 0 +OP4 E0025A 0 +OP4 E0025B 0 +OP4 E0025C 0 +OP4 E0025D 0 +OP4 E0025E 0 +OP4 E0025F 0 +OP4 E00260 0 +OP4 E00261 0 +OP4 E00262 0 +OP4 E00263 0 +OP4 E00264 0 +OP4 E00265 0 +OP4 E00266 0 +OP4 E00267 0 +OP4 E00268 0 +OP4 E00269 0 +OP4 E0026A 0 +OP4 E0026B 0 +OP4 E0026C 0 +OP4 E0026D 0 +OP4 E0026E 0 +OP4 E0026F 0 +OP4 E00270 0 +OP4 E00271 0 +OP4 E00272 0 +OP4 E00273 0 +OP4 E00274 0 +OP4 E00275 0 +OP4 E00276 0 +OP4 E00277 0 +OP4 E00278 0 +OP4 E00279 0 +OP4 E0027A 0 +OP4 E0027B 0 +OP4 E0027C 0 +OP4 E0027D 0 +OP4 E0027E 0 +OP4 E0027F 0 +OP4 E00280 0 +OP4 E00281 0 +OP4 E00282 0 +OP4 E00283 0 +OP4 E00284 0 +OP4 E00285 0 +OP4 E00286 0 +OP4 E00287 0 +OP4 E00288 0 +OP4 E00289 0 +OP4 E0028A 0 +OP4 E0028B 0 +OP4 E0028C 0 +OP4 E0028D 0 +OP4 E0028E 0 +OP4 E0028F 0 +OP4 E00290 0 +OP4 E00291 0 +OP4 E00292 0 +OP4 E00293 0 +OP4 E00294 0 +OP4 E00295 0 +OP4 E00296 0 +OP4 E00297 0 +OP4 E00298 0 +OP4 E00299 0 +OP4 E0029A 0 +OP4 E0029B 0 +OP4 E0029C 0 +OP4 E0029D 0 +OP4 E0029E 0 +OP4 E0029F 0 +OP4 E002A0 0 +OP4 E002A1 0 +OP4 E002A2 0 +OP4 E002A3 0 +OP4 E002A4 0 +OP4 E002A5 0 +OP4 E002A6 0 +OP4 E002A7 0 +OP4 E002A8 0 +OP4 E002A9 0 +OP4 E002AA 0 +OP4 E002AB 0 +OP4 E002AC 0 +OP4 E002AD 0 +OP4 E002AE 0 +OP4 E002AF 0 +OP4 E002B0 0 +OP4 E002B1 0 +OP4 E002B2 0 +OP4 E002B3 0 +OP4 E002B4 0 +OP4 E002B5 0 +OP4 E002B6 0 +OP4 E002B7 0 +OP4 E002B8 0 +OP4 E002B9 0 +OP4 E002BA 0 +OP4 E002BB 0 +OP4 E002BC 0 +OP4 E002BD 0 +OP4 E002BE 0 +OP4 E002BF 0 +OP4 E002C0 0 +OP4 E002C1 0 +OP4 E002C2 0 +OP4 E002C3 0 +OP4 E002C4 0 +OP4 E002C5 0 +OP4 E002C6 0 +OP4 E002C7 0 +OP4 E002C8 0 +OP4 E002C9 0 +OP4 E002CA 0 +OP4 E002CB 0 +OP4 E002CC 0 +OP4 E002CD 0 +OP4 E002CE 0 +OP4 E002CF 0 +OP4 E002D0 0 +OP4 E002D1 0 +OP4 E002D2 0 +OP4 E002D3 0 +OP4 E002D4 0 +OP4 E002D5 0 +OP4 E002D6 0 +OP4 E002D7 0 +OP4 E002D8 0 +OP4 E002D9 0 +OP4 E002DA 0 +OP4 E002DB 0 +OP4 E002DC 0 +OP4 E002DD 0 +OP4 E002DE 0 +OP4 E002DF 0 +OP4 E002E0 0 +OP4 E002E1 0 +OP4 E002E2 0 +OP4 E002E3 0 +OP4 E002E4 0 +OP4 E002E5 0 +OP4 E002E6 0 +OP4 E002E7 0 +OP4 E002E8 0 +OP4 E002E9 0 +OP4 E002EA 0 +OP4 E002EB 0 +OP4 E002EC 0 +OP4 E002ED 0 +OP4 E002EE 0 +OP4 E002EF 0 +OP4 E002F0 0 +OP4 E002F1 0 +OP4 E002F2 0 +OP4 E002F3 0 +OP4 E002F4 0 +OP4 E002F5 0 +OP4 E002F6 0 +OP4 E002F7 0 +OP4 E002F8 0 +OP4 E002F9 0 +OP4 E002FA 0 +OP4 E002FB 0 +OP4 E002FC 0 +OP4 E002FD 0 +OP4 E002FE 0 +OP4 E002FF 0 +OP4 E00300 0 +OP4 E00301 0 +OP4 E00302 0 +OP4 E00303 0 +OP4 E00304 0 +OP4 E00305 0 +OP4 E00306 0 +OP4 E00307 0 +OP4 E00308 0 +OP4 E00309 0 +OP4 E0030A 0 +OP4 E0030B 0 +OP4 E0030C 0 +OP4 E0030D 0 +OP4 E0030E 0 +OP4 E0030F 0 +OP4 E00310 0 +OP4 E00311 0 +OP4 E00312 0 +OP4 E00313 0 +OP4 E00314 0 +OP4 E00315 0 +OP4 E00316 0 +OP4 E00317 0 +OP4 E00318 0 +OP4 E00319 0 +OP4 E0031A 0 +OP4 E0031B 0 +OP4 E0031C 0 +OP4 E0031D 0 +OP4 E0031E 0 +OP4 E0031F 0 +OP4 E00320 0 +OP4 E00321 0 +OP4 E00322 0 +OP4 E00323 0 +OP4 E00324 0 +OP4 E00325 0 +OP4 E00326 0 +OP4 E00327 0 +OP4 E00328 0 +OP4 E00329 0 +OP4 E0032A 0 +OP4 E0032B 0 +OP4 E0032C 0 +OP4 E0032D 0 +OP4 E0032E 0 +OP4 E0032F 0 +OP4 E00330 0 +OP4 E00331 0 +OP4 E00332 0 +OP4 E00333 0 +OP4 E00334 0 +OP4 E00335 0 +OP4 E00336 0 +OP4 E00337 0 +OP4 E00338 0 +OP4 E00339 0 +OP4 E0033A 0 +OP4 E0033B 0 +OP4 E0033C 0 +OP4 E0033D 0 +OP4 E0033E 0 +OP4 E0033F 0 +OP4 E00340 0 +OP4 E00341 0 +OP4 E00342 0 +OP4 E00343 0 +OP4 E00344 0 +OP4 E00345 0 +OP4 E00346 0 +OP4 E00347 0 +OP4 E00348 0 +OP4 E00349 0 +OP4 E0034A 0 +OP4 E0034B 0 +OP4 E0034C 0 +OP4 E0034D 0 +OP4 E0034E 0 +OP4 E0034F 0 +OP4 E00350 0 +OP4 E00351 0 +OP4 E00352 0 +OP4 E00353 0 +OP4 E00354 0 +OP4 E00355 0 +OP4 E00356 0 +OP4 E00357 0 +OP4 E00358 0 +OP4 E00359 0 +OP4 E0035A 0 +OP4 E0035B 0 +OP4 E0035C 0 +OP4 E0035D 0 +OP4 E0035E 0 +OP4 E0035F 0 +OP4 E00360 0 +OP4 E00361 0 +OP4 E00362 0 +OP4 E00363 0 +OP4 E00364 0 +OP4 E00365 0 +OP4 E00366 0 +OP4 E00367 0 +OP4 E00368 0 +OP4 E00369 0 +OP4 E0036A 0 +OP4 E0036B 0 +OP4 E0036C 0 +OP4 E0036D 0 +OP4 E0036E 0 +OP4 E0036F 0 +OP4 E00370 0 +OP4 E00371 0 +OP4 E00372 0 +OP4 E00373 0 +OP4 E00374 0 +OP4 E00375 0 +OP4 E00376 0 +OP4 E00377 0 +OP4 E00378 0 +OP4 E00379 0 +OP4 E0037A 0 +OP4 E0037B 0 +OP4 E0037C 0 +OP4 E0037D 0 +OP4 E0037E 0 +OP4 E0037F 0 +OP4 E00380 0 +OP4 E00381 0 +OP4 E00382 0 +OP4 E00383 0 +OP4 E00384 0 +OP4 E00385 0 +OP4 E00386 0 +OP4 E00387 0 +OP4 E00388 0 +OP4 E00389 0 +OP4 E0038A 0 +OP4 E0038B 0 +OP4 E0038C 0 +OP4 E0038D 0 +OP4 E0038E 0 +OP4 E0038F 0 +OP4 E00390 0 +OP4 E00391 0 +OP4 E00392 0 +OP4 E00393 0 +OP4 E00394 0 +OP4 E00395 0 +OP4 E00396 0 +OP4 E00397 0 +OP4 E00398 0 +OP4 E00399 0 +OP4 E0039A 0 +OP4 E0039B 0 +OP4 E0039C 0 +OP4 E0039D 0 +OP4 E0039E 0 +OP4 E0039F 0 +OP4 E003A0 0 +OP4 E003A1 0 +OP4 E003A2 0 +OP4 E003A3 0 +OP4 E003A4 0 +OP4 E003A5 0 +OP4 E003A6 0 +OP4 E003A7 0 +OP4 E003A8 0 +OP4 E003A9 0 +OP4 E003AA 0 +OP4 E003AB 0 +OP4 E003AC 0 +OP4 E003AD 0 +OP4 E003AE 0 +OP4 E003AF 0 +OP4 E003B0 0 +OP4 E003B1 0 +OP4 E003B2 0 +OP4 E003B3 0 +OP4 E003B4 0 +OP4 E003B5 0 +OP4 E003B6 0 +OP4 E003B7 0 +OP4 E003B8 0 +OP4 E003B9 0 +OP4 E003BA 0 +OP4 E003BB 0 +OP4 E003BC 0 +OP4 E003BD 0 +OP4 E003BE 0 +OP4 E003BF 0 +OP4 E003C0 0 +OP4 E003C1 0 +OP4 E003C2 0 +OP4 E003C3 0 +OP4 E003C4 0 +OP4 E003C5 0 +OP4 E003C6 0 +OP4 E003C7 0 +OP4 E003C8 0 +OP4 E003C9 0 +OP4 E003CA 0 +OP4 E003CB 0 +OP4 E003CC 0 +OP4 E003CD 0 +OP4 E003CE 0 +OP4 E003CF 0 +OP4 E003D0 0 +OP4 E003D1 0 +OP4 E003D2 0 +OP4 E003D3 0 +OP4 E003D4 0 +OP4 E003D5 0 +OP4 E003D6 0 +OP4 E003D7 0 +OP4 E003D8 0 +OP4 E003D9 0 +OP4 E003DA 0 +OP4 E003DB 0 +OP4 E003DC 0 +OP4 E003DD 0 +OP4 E003DE 0 +OP4 E003DF 0 +OP4 E003E0 0 +OP4 E003E1 0 +OP4 E003E2 0 +OP4 E003E3 0 +OP4 E003E4 0 +OP4 E003E5 0 +OP4 E003E6 0 +OP4 E003E7 0 +OP4 E003E8 0 +OP4 E003E9 0 +OP4 E003EA 0 +OP4 E003EB 0 +OP4 E003EC 0 +OP4 E003ED 0 +OP4 E003EE 0 +OP4 E003EF 0 +OP4 E003F0 0 +OP4 E003F1 0 +OP4 E003F2 0 +OP4 E003F3 0 +OP4 E003F4 0 +OP4 E003F5 0 +OP4 E003F6 0 +OP4 E003F7 0 +OP4 E003F8 0 +OP4 E003F9 0 +OP4 E003FA 0 +OP4 E003FB 0 +OP4 E003FC 0 +OP4 E003FD 0 +OP4 E003FE 0 +OP4 E003FF 0 +OP4 E00400 0 +OP4 E00401 0 +OP4 E00402 0 +OP4 E00403 0 +OP4 E00404 0 +OP4 E00405 0 +OP4 E00406 0 +OP4 E00407 0 +OP4 E00408 0 +OP4 E00409 0 +OP4 E0040A 0 +OP4 E0040B 0 +OP4 E0040C 0 +OP4 E0040D 0 +OP4 E0040E 0 +OP4 E0040F 0 +OP4 E00410 0 +OP4 E00411 0 +OP4 E00412 0 +OP4 E00413 0 +OP4 E00414 0 +OP4 E00415 0 +OP4 E00416 0 +OP4 E00417 0 +OP4 E00418 0 +OP4 E00419 0 +OP4 E0041A 0 +OP4 E0041B 0 +OP4 E0041C 0 +OP4 E0041D 0 +OP4 E0041E 0 +OP4 E0041F 0 +OP4 E00420 0 +OP4 E00421 0 +OP4 E00422 0 +OP4 E00423 0 +OP4 E00424 0 +OP4 E00425 0 +OP4 E00426 0 +OP4 E00427 0 +OP4 E00428 0 +OP4 E00429 0 +OP4 E0042A 0 +OP4 E0042B 0 +OP4 E0042C 0 +OP4 E0042D 0 +OP4 E0042E 0 +OP4 E0042F 0 +OP4 E00430 0 +OP4 E00431 0 +OP4 E00432 0 +OP4 E00433 0 +OP4 E00434 0 +OP4 E00435 0 +OP4 E00436 0 +OP4 E00437 0 +OP4 E00438 0 +OP4 E00439 0 +OP4 E0043A 0 +OP4 E0043B 0 +OP4 E0043C 0 +OP4 E0043D 0 +OP4 E0043E 0 +OP4 E0043F 0 +OP4 E00440 0 +OP4 E00441 0 +OP4 E00442 0 +OP4 E00443 0 +OP4 E00444 0 +OP4 E00445 0 +OP4 E00446 0 +OP4 E00447 0 +OP4 E00448 0 +OP4 E00449 0 +OP4 E0044A 0 +OP4 E0044B 0 +OP4 E0044C 0 +OP4 E0044D 0 +OP4 E0044E 0 +OP4 E0044F 0 +OP4 E00450 0 +OP4 E00451 0 +OP4 E00452 0 +OP4 E00453 0 +OP4 E00454 0 +OP4 E00455 0 +OP4 E00456 0 +OP4 E00457 0 +OP4 E00458 0 +OP4 E00459 0 +OP4 E0045A 0 +OP4 E0045B 0 +OP4 E0045C 0 +OP4 E0045D 0 +OP4 E0045E 0 +OP4 E0045F 0 +OP4 E00460 0 +OP4 E00461 0 +OP4 E00462 0 +OP4 E00463 0 +OP4 E00464 0 +OP4 E00465 0 +OP4 E00466 0 +OP4 E00467 0 +OP4 E00468 0 +OP4 E00469 0 +OP4 E0046A 0 +OP4 E0046B 0 +OP4 E0046C 0 +OP4 E0046D 0 +OP4 E0046E 0 +OP4 E0046F 0 +OP4 E00470 0 +OP4 E00471 0 +OP4 E00472 0 +OP4 E00473 0 +OP4 E00474 0 +OP4 E00475 0 +OP4 E00476 0 +OP4 E00477 0 +OP4 E00478 0 +OP4 E00479 0 +OP4 E0047A 0 +OP4 E0047B 0 +OP4 E0047C 0 +OP4 E0047D 0 +OP4 E0047E 0 +OP4 E0047F 0 +OP4 E00480 0 +OP4 E00481 0 +OP4 E00482 0 +OP4 E00483 0 +OP4 E00484 0 +OP4 E00485 0 +OP4 E00486 0 +OP4 E00487 0 +OP4 E00488 0 +OP4 E00489 0 +OP4 E0048A 0 +OP4 E0048B 0 +OP4 E0048C 0 +OP4 E0048D 0 +OP4 E0048E 0 +OP4 E0048F 0 +OP4 E00490 0 +OP4 E00491 0 +OP4 E00492 0 +OP4 E00493 0 +OP4 E00494 0 +OP4 E00495 0 +OP4 E00496 0 +OP4 E00497 0 +OP4 E00498 0 +OP4 E00499 0 +OP4 E0049A 0 +OP4 E0049B 0 +OP4 E0049C 0 +OP4 E0049D 0 +OP4 E0049E 0 +OP4 E0049F 0 +OP4 E004A0 0 +OP4 E004A1 0 +OP4 E004A2 0 +OP4 E004A3 0 +OP4 E004A4 0 +OP4 E004A5 0 +OP4 E004A6 0 +OP4 E004A7 0 +OP4 E004A8 0 +OP4 E004A9 0 +OP4 E004AA 0 +OP4 E004AB 0 +OP4 E004AC 0 +OP4 E004AD 0 +OP4 E004AE 0 +OP4 E004AF 0 +OP4 E004B0 0 +OP4 E004B1 0 +OP4 E004B2 0 +OP4 E004B3 0 +OP4 E004B4 0 +OP4 E004B5 0 +OP4 E004B6 0 +OP4 E004B7 0 +OP4 E004B8 0 +OP4 E004B9 0 +OP4 E004BA 0 +OP4 E004BB 0 +OP4 E004BC 0 +OP4 E004BD 0 +OP4 E004BE 0 +OP4 E004BF 0 +OP4 E004C0 0 +OP4 E004C1 0 +OP4 E004C2 0 +OP4 E004C3 0 +OP4 E004C4 0 +OP4 E004C5 0 +OP4 E004C6 0 +OP4 E004C7 0 +OP4 E004C8 0 +OP4 E004C9 0 +OP4 E004CA 0 +OP4 E004CB 0 +OP4 E004CC 0 +OP4 E004CD 0 +OP4 E004CE 0 +OP4 E004CF 0 +OP4 E004D0 0 +OP4 E004D1 0 +OP4 E004D2 0 +OP4 E004D3 0 +OP4 E004D4 0 +OP4 E004D5 0 +OP4 E004D6 0 +OP4 E004D7 0 +OP4 E004D8 0 +OP4 E004D9 0 +OP4 E004DA 0 +OP4 E004DB 0 +OP4 E004DC 0 +OP4 E004DD 0 +OP4 E004DE 0 +OP4 E004DF 0 +OP4 E004E0 0 +OP4 E004E1 0 +OP4 E004E2 0 +OP4 E004E3 0 +OP4 E004E4 0 +OP4 E004E5 0 +OP4 E004E6 0 +OP4 E004E7 0 +OP4 E004E8 0 +OP4 E004E9 0 +OP4 E004EA 0 +OP4 E004EB 0 +OP4 E004EC 0 +OP4 E004ED 0 +OP4 E004EE 0 +OP4 E004EF 0 +OP4 E004F0 0 +OP4 E004F1 0 +OP4 E004F2 0 +OP4 E004F3 0 +OP4 E004F4 0 +OP4 E004F5 0 +OP4 E004F6 0 +OP4 E004F7 0 +OP4 E004F8 0 +OP4 E004F9 0 +OP4 E004FA 0 +OP4 E004FB 0 +OP4 E004FC 0 +OP4 E004FD 0 +OP4 E004FE 0 +OP4 E004FF 0 +OP4 E00500 0 +OP4 E00501 0 +OP4 E00502 0 +OP4 E00503 0 +OP4 E00504 0 +OP4 E00505 0 +OP4 E00506 0 +OP4 E00507 0 +OP4 E00508 0 +OP4 E00509 0 +OP4 E0050A 0 +OP4 E0050B 0 +OP4 E0050C 0 +OP4 E0050D 0 +OP4 E0050E 0 +OP4 E0050F 0 +OP4 E00510 0 +OP4 E00511 0 +OP4 E00512 0 +OP4 E00513 0 +OP4 E00514 0 +OP4 E00515 0 +OP4 E00516 0 +OP4 E00517 0 +OP4 E00518 0 +OP4 E00519 0 +OP4 E0051A 0 +OP4 E0051B 0 +OP4 E0051C 0 +OP4 E0051D 0 +OP4 E0051E 0 +OP4 E0051F 0 +OP4 E00520 0 +OP4 E00521 0 +OP4 E00522 0 +OP4 E00523 0 +OP4 E00524 0 +OP4 E00525 0 +OP4 E00526 0 +OP4 E00527 0 +OP4 E00528 0 +OP4 E00529 0 +OP4 E0052A 0 +OP4 E0052B 0 +OP4 E0052C 0 +OP4 E0052D 0 +OP4 E0052E 0 +OP4 E0052F 0 +OP4 E00530 0 +OP4 E00531 0 +OP4 E00532 0 +OP4 E00533 0 +OP4 E00534 0 +OP4 E00535 0 +OP4 E00536 0 +OP4 E00537 0 +OP4 E00538 0 +OP4 E00539 0 +OP4 E0053A 0 +OP4 E0053B 0 +OP4 E0053C 0 +OP4 E0053D 0 +OP4 E0053E 0 +OP4 E0053F 0 +OP4 E00540 0 +OP4 E00541 0 +OP4 E00542 0 +OP4 E00543 0 +OP4 E00544 0 +OP4 E00545 0 +OP4 E00546 0 +OP4 E00547 0 +OP4 E00548 0 +OP4 E00549 0 +OP4 E0054A 0 +OP4 E0054B 0 +OP4 E0054C 0 +OP4 E0054D 0 +OP4 E0054E 0 +OP4 E0054F 0 +OP4 E00550 0 +OP4 E00551 0 +OP4 E00552 0 +OP4 E00553 0 +OP4 E00554 0 +OP4 E00555 0 +OP4 E00556 0 +OP4 E00557 0 +OP4 E00558 0 +OP4 E00559 0 +OP4 E0055A 0 +OP4 E0055B 0 +OP4 E0055C 0 +OP4 E0055D 0 +OP4 E0055E 0 +OP4 E0055F 0 +OP4 E00560 0 +OP4 E00561 0 +OP4 E00562 0 +OP4 E00563 0 +OP4 E00564 0 +OP4 E00565 0 +OP4 E00566 0 +OP4 E00567 0 +OP4 E00568 0 +OP4 E00569 0 +OP4 E0056A 0 +OP4 E0056B 0 +OP4 E0056C 0 +OP4 E0056D 0 +OP4 E0056E 0 +OP4 E0056F 0 +OP4 E00570 0 +OP4 E00571 0 +OP4 E00572 0 +OP4 E00573 0 +OP4 E00574 0 +OP4 E00575 0 +OP4 E00576 0 +OP4 E00577 0 +OP4 E00578 0 +OP4 E00579 0 +OP4 E0057A 0 +OP4 E0057B 0 +OP4 E0057C 0 +OP4 E0057D 0 +OP4 E0057E 0 +OP4 E0057F 0 +OP4 E00580 0 +OP4 E00581 0 +OP4 E00582 0 +OP4 E00583 0 +OP4 E00584 0 +OP4 E00585 0 +OP4 E00586 0 +OP4 E00587 0 +OP4 E00588 0 +OP4 E00589 0 +OP4 E0058A 0 +OP4 E0058B 0 +OP4 E0058C 0 +OP4 E0058D 0 +OP4 E0058E 0 +OP4 E0058F 0 +OP4 E00590 0 +OP4 E00591 0 +OP4 E00592 0 +OP4 E00593 0 +OP4 E00594 0 +OP4 E00595 0 +OP4 E00596 0 +OP4 E00597 0 +OP4 E00598 0 +OP4 E00599 0 +OP4 E0059A 0 +OP4 E0059B 0 +OP4 E0059C 0 +OP4 E0059D 0 +OP4 E0059E 0 +OP4 E0059F 0 +OP4 E005A0 0 +OP4 E005A1 0 +OP4 E005A2 0 +OP4 E005A3 0 +OP4 E005A4 0 +OP4 E005A5 0 +OP4 E005A6 0 +OP4 E005A7 0 +OP4 E005A8 0 +OP4 E005A9 0 +OP4 E005AA 0 +OP4 E005AB 0 +OP4 E005AC 0 +OP4 E005AD 0 +OP4 E005AE 0 +OP4 E005AF 0 +OP4 E005B0 0 +OP4 E005B1 0 +OP4 E005B2 0 +OP4 E005B3 0 +OP4 E005B4 0 +OP4 E005B5 0 +OP4 E005B6 0 +OP4 E005B7 0 +OP4 E005B8 0 +OP4 E005B9 0 +OP4 E005BA 0 +OP4 E005BB 0 +OP4 E005BC 0 +OP4 E005BD 0 +OP4 E005BE 0 +OP4 E005BF 0 +OP4 E005C0 0 +OP4 E005C1 0 +OP4 E005C2 0 +OP4 E005C3 0 +OP4 E005C4 0 +OP4 E005C5 0 +OP4 E005C6 0 +OP4 E005C7 0 +OP4 E005C8 0 +OP4 E005C9 0 +OP4 E005CA 0 +OP4 E005CB 0 +OP4 E005CC 0 +OP4 E005CD 0 +OP4 E005CE 0 +OP4 E005CF 0 +OP4 E005D0 0 +OP4 E005D1 0 +OP4 E005D2 0 +OP4 E005D3 0 +OP4 E005D4 0 +OP4 E005D5 0 +OP4 E005D6 0 +OP4 E005D7 0 +OP4 E005D8 0 +OP4 E005D9 0 +OP4 E005DA 0 +OP4 E005DB 0 +OP4 E005DC 0 +OP4 E005DD 0 +OP4 E005DE 0 +OP4 E005DF 0 +OP4 E005E0 0 +OP4 E005E1 0 +OP4 E005E2 0 +OP4 E005E3 0 +OP4 E005E4 0 +OP4 E005E5 0 +OP4 E005E6 0 +OP4 E005E7 0 +OP4 E005E8 0 +OP4 E005E9 0 +OP4 E005EA 0 +OP4 E005EB 0 +OP4 E005EC 0 +OP4 E005ED 0 +OP4 E005EE 0 +OP4 E005EF 0 +OP4 E005F0 0 +OP4 E005F1 0 +OP4 E005F2 0 +OP4 E005F3 0 +OP4 E005F4 0 +OP4 E005F5 0 +OP4 E005F6 0 +OP4 E005F7 0 +OP4 E005F8 0 +OP4 E005F9 0 +OP4 E005FA 0 +OP4 E005FB 0 +OP4 E005FC 0 +OP4 E005FD 0 +OP4 E005FE 0 +OP4 E005FF 0 +OP4 E00600 0 +OP4 E00601 0 +OP4 E00602 0 +OP4 E00603 0 +OP4 E00604 0 +OP4 E00605 0 +OP4 E00606 0 +OP4 E00607 0 +OP4 E00608 0 +OP4 E00609 0 +OP4 E0060A 0 +OP4 E0060B 0 +OP4 E0060C 0 +OP4 E0060D 0 +OP4 E0060E 0 +OP4 E0060F 0 +OP4 E00610 0 +OP4 E00611 0 +OP4 E00612 0 +OP4 E00613 0 +OP4 E00614 0 +OP4 E00615 0 +OP4 E00616 0 +OP4 E00617 0 +OP4 E00618 0 +OP4 E00619 0 +OP4 E0061A 0 +OP4 E0061B 0 +OP4 E0061C 0 +OP4 E0061D 0 +OP4 E0061E 0 +OP4 E0061F 0 +OP4 E00620 0 +OP4 E00621 0 +OP4 E00622 0 +OP4 E00623 0 +OP4 E00624 0 +OP4 E00625 0 +OP4 E00626 0 +OP4 E00627 0 +OP4 E00628 0 +OP4 E00629 0 +OP4 E0062A 0 +OP4 E0062B 0 +OP4 E0062C 0 +OP4 E0062D 0 +OP4 E0062E 0 +OP4 E0062F 0 +OP4 E00630 0 +OP4 E00631 0 +OP4 E00632 0 +OP4 E00633 0 +OP4 E00634 0 +OP4 E00635 0 +OP4 E00636 0 +OP4 E00637 0 +OP4 E00638 0 +OP4 E00639 0 +OP4 E0063A 0 +OP4 E0063B 0 +OP4 E0063C 0 +OP4 E0063D 0 +OP4 E0063E 0 +OP4 E0063F 0 +OP4 E00640 0 +OP4 E00641 0 +OP4 E00642 0 +OP4 E00643 0 +OP4 E00644 0 +OP4 E00645 0 +OP4 E00646 0 +OP4 E00647 0 +OP4 E00648 0 +OP4 E00649 0 +OP4 E0064A 0 +OP4 E0064B 0 +OP4 E0064C 0 +OP4 E0064D 0 +OP4 E0064E 0 +OP4 E0064F 0 +OP4 E00650 0 +OP4 E00651 0 +OP4 E00652 0 +OP4 E00653 0 +OP4 E00654 0 +OP4 E00655 0 +OP4 E00656 0 +OP4 E00657 0 +OP4 E00658 0 +OP4 E00659 0 +OP4 E0065A 0 +OP4 E0065B 0 +OP4 E0065C 0 +OP4 E0065D 0 +OP4 E0065E 0 +OP4 E0065F 0 +OP4 E00660 0 +OP4 E00661 0 +OP4 E00662 0 +OP4 E00663 0 +OP4 E00664 0 +OP4 E00665 0 +OP4 E00666 0 +OP4 E00667 0 +OP4 E00668 0 +OP4 E00669 0 +OP4 E0066A 0 +OP4 E0066B 0 +OP4 E0066C 0 +OP4 E0066D 0 +OP4 E0066E 0 +OP4 E0066F 0 +OP4 E00670 0 +OP4 E00671 0 +OP4 E00672 0 +OP4 E00673 0 +OP4 E00674 0 +OP4 E00675 0 +OP4 E00676 0 +OP4 E00677 0 +OP4 E00678 0 +OP4 E00679 0 +OP4 E0067A 0 +OP4 E0067B 0 +OP4 E0067C 0 +OP4 E0067D 0 +OP4 E0067E 0 +OP4 E0067F 0 +OP4 E00680 0 +OP4 E00681 0 +OP4 E00682 0 +OP4 E00683 0 +OP4 E00684 0 +OP4 E00685 0 +OP4 E00686 0 +OP4 E00687 0 +OP4 E00688 0 +OP4 E00689 0 +OP4 E0068A 0 +OP4 E0068B 0 +OP4 E0068C 0 +OP4 E0068D 0 +OP4 E0068E 0 +OP4 E0068F 0 +OP4 E00690 0 +OP4 E00691 0 +OP4 E00692 0 +OP4 E00693 0 +OP4 E00694 0 +OP4 E00695 0 +OP4 E00696 0 +OP4 E00697 0 +OP4 E00698 0 +OP4 E00699 0 +OP4 E0069A 0 +OP4 E0069B 0 +OP4 E0069C 0 +OP4 E0069D 0 +OP4 E0069E 0 +OP4 E0069F 0 +OP4 E006A0 0 +OP4 E006A1 0 +OP4 E006A2 0 +OP4 E006A3 0 +OP4 E006A4 0 +OP4 E006A5 0 +OP4 E006A6 0 +OP4 E006A7 0 +OP4 E006A8 0 +OP4 E006A9 0 +OP4 E006AA 0 +OP4 E006AB 0 +OP4 E006AC 0 +OP4 E006AD 0 +OP4 E006AE 0 +OP4 E006AF 0 +OP4 E006B0 0 +OP4 E006B1 0 +OP4 E006B2 0 +OP4 E006B3 0 +OP4 E006B4 0 +OP4 E006B5 0 +OP4 E006B6 0 +OP4 E006B7 0 +OP4 E006B8 0 +OP4 E006B9 0 +OP4 E006BA 0 +OP4 E006BB 0 +OP4 E006BC 0 +OP4 E006BD 0 +OP4 E006BE 0 +OP4 E006BF 0 +OP4 E006C0 0 +OP4 E006C1 0 +OP4 E006C2 0 +OP4 E006C3 0 +OP4 E006C4 0 +OP4 E006C5 0 +OP4 E006C6 0 +OP4 E006C7 0 +OP4 E006C8 0 +OP4 E006C9 0 +OP4 E006CA 0 +OP4 E006CB 0 +OP4 E006CC 0 +OP4 E006CD 0 +OP4 E006CE 0 +OP4 E006CF 0 +OP4 E006D0 0 +OP4 E006D1 0 +OP4 E006D2 0 +OP4 E006D3 0 +OP4 E006D4 0 +OP4 E006D5 0 +OP4 E006D6 0 +OP4 E006D7 0 +OP4 E006D8 0 +OP4 E006D9 0 +OP4 E006DA 0 +OP4 E006DB 0 +OP4 E006DC 0 +OP4 E006DD 0 +OP4 E006DE 0 +OP4 E006DF 0 +OP4 E006E0 0 +OP4 E006E1 0 +OP4 E006E2 0 +OP4 E006E3 0 +OP4 E006E4 0 +OP4 E006E5 0 +OP4 E006E6 0 +OP4 E006E7 0 +OP4 E006E8 0 +OP4 E006E9 0 +OP4 E006EA 0 +OP4 E006EB 0 +OP4 E006EC 0 +OP4 E006ED 0 +OP4 E006EE 0 +OP4 E006EF 0 +OP4 E006F0 0 +OP4 E006F1 0 +OP4 E006F2 0 +OP4 E006F3 0 +OP4 E006F4 0 +OP4 E006F5 0 +OP4 E006F6 0 +OP4 E006F7 0 +OP4 E006F8 0 +OP4 E006F9 0 +OP4 E006FA 0 +OP4 E006FB 0 +OP4 E006FC 0 +OP4 E006FD 0 +OP4 E006FE 0 +OP4 E006FF 0 +OP4 E00700 0 +OP4 E00701 0 +OP4 E00702 0 +OP4 E00703 0 +OP4 E00704 0 +OP4 E00705 0 +OP4 E00706 0 +OP4 E00707 0 +OP4 E00708 0 +OP4 E00709 0 +OP4 E0070A 0 +OP4 E0070B 0 +OP4 E0070C 0 +OP4 E0070D 0 +OP4 E0070E 0 +OP4 E0070F 0 +OP4 E00710 0 +OP4 E00711 0 +OP4 E00712 0 +OP4 E00713 0 +OP4 E00714 0 +OP4 E00715 0 +OP4 E00716 0 +OP4 E00717 0 +OP4 E00718 0 +OP4 E00719 0 +OP4 E0071A 0 +OP4 E0071B 0 +OP4 E0071C 0 +OP4 E0071D 0 +OP4 E0071E 0 +OP4 E0071F 0 +OP4 E00720 0 +OP4 E00721 0 +OP4 E00722 0 +OP4 E00723 0 +OP4 E00724 0 +OP4 E00725 0 +OP4 E00726 0 +OP4 E00727 0 +OP4 E00728 0 +OP4 E00729 0 +OP4 E0072A 0 +OP4 E0072B 0 +OP4 E0072C 0 +OP4 E0072D 0 +OP4 E0072E 0 +OP4 E0072F 0 +OP4 E00730 0 +OP4 E00731 0 +OP4 E00732 0 +OP4 E00733 0 +OP4 E00734 0 +OP4 E00735 0 +OP4 E00736 0 +OP4 E00737 0 +OP4 E00738 0 +OP4 E00739 0 +OP4 E0073A 0 +OP4 E0073B 0 +OP4 E0073C 0 +OP4 E0073D 0 +OP4 E0073E 0 +OP4 E0073F 0 +OP4 E00740 0 +OP4 E00741 0 +OP4 E00742 0 +OP4 E00743 0 +OP4 E00744 0 +OP4 E00745 0 +OP4 E00746 0 +OP4 E00747 0 +OP4 E00748 0 +OP4 E00749 0 +OP4 E0074A 0 +OP4 E0074B 0 +OP4 E0074C 0 +OP4 E0074D 0 +OP4 E0074E 0 +OP4 E0074F 0 +OP4 E00750 0 +OP4 E00751 0 +OP4 E00752 0 +OP4 E00753 0 +OP4 E00754 0 +OP4 E00755 0 +OP4 E00756 0 +OP4 E00757 0 +OP4 E00758 0 +OP4 E00759 0 +OP4 E0075A 0 +OP4 E0075B 0 +OP4 E0075C 0 +OP4 E0075D 0 +OP4 E0075E 0 +OP4 E0075F 0 +OP4 E00760 0 +OP4 E00761 0 +OP4 E00762 0 +OP4 E00763 0 +OP4 E00764 0 +OP4 E00765 0 +OP4 E00766 0 +OP4 E00767 0 +OP4 E00768 0 +OP4 E00769 0 +OP4 E0076A 0 +OP4 E0076B 0 +OP4 E0076C 0 +OP4 E0076D 0 +OP4 E0076E 0 +OP4 E0076F 0 +OP4 E00770 0 +OP4 E00771 0 +OP4 E00772 0 +OP4 E00773 0 +OP4 E00774 0 +OP4 E00775 0 +OP4 E00776 0 +OP4 E00777 0 +OP4 E00778 0 +OP4 E00779 0 +OP4 E0077A 0 +OP4 E0077B 0 +OP4 E0077C 0 +OP4 E0077D 0 +OP4 E0077E 0 +OP4 E0077F 0 +OP4 E00780 0 +OP4 E00781 0 +OP4 E00782 0 +OP4 E00783 0 +OP4 E00784 0 +OP4 E00785 0 +OP4 E00786 0 +OP4 E00787 0 +OP4 E00788 0 +OP4 E00789 0 +OP4 E0078A 0 +OP4 E0078B 0 +OP4 E0078C 0 +OP4 E0078D 0 +OP4 E0078E 0 +OP4 E0078F 0 +OP4 E00790 0 +OP4 E00791 0 +OP4 E00792 0 +OP4 E00793 0 +OP4 E00794 0 +OP4 E00795 0 +OP4 E00796 0 +OP4 E00797 0 +OP4 E00798 0 +OP4 E00799 0 +OP4 E0079A 0 +OP4 E0079B 0 +OP4 E0079C 0 +OP4 E0079D 0 +OP4 E0079E 0 +OP4 E0079F 0 +OP4 E007A0 0 +OP4 E007A1 0 +OP4 E007A2 0 +OP4 E007A3 0 +OP4 E007A4 0 +OP4 E007A5 0 +OP4 E007A6 0 +OP4 E007A7 0 +OP4 E007A8 0 +OP4 E007A9 0 +OP4 E007AA 0 +OP4 E007AB 0 +OP4 E007AC 0 +OP4 E007AD 0 +OP4 E007AE 0 +OP4 E007AF 0 +OP4 E007B0 0 +OP4 E007B1 0 +OP4 E007B2 0 +OP4 E007B3 0 +OP4 E007B4 0 +OP4 E007B5 0 +OP4 E007B6 0 +OP4 E007B7 0 +OP4 E007B8 0 +OP4 E007B9 0 +OP4 E007BA 0 +OP4 E007BB 0 +OP4 E007BC 0 +OP4 E007BD 0 +OP4 E007BE 0 +OP4 E007BF 0 +OP4 E007C0 0 +OP4 E007C1 0 +OP4 E007C2 0 +OP4 E007C3 0 +OP4 E007C4 0 +OP4 E007C5 0 +OP4 E007C6 0 +OP4 E007C7 0 +OP4 E007C8 0 +OP4 E007C9 0 +OP4 E007CA 0 +OP4 E007CB 0 +OP4 E007CC 0 +OP4 E007CD 0 +OP4 E007CE 0 +OP4 E007CF 0 +OP4 E007D0 0 +OP4 E007D1 0 +OP4 E007D2 0 +OP4 E007D3 0 +OP4 E007D4 0 +OP4 E007D5 0 +OP4 E007D6 0 +OP4 E007D7 0 +OP4 E007D8 0 +OP4 E007D9 0 +OP4 E007DA 0 +OP4 E007DB 0 +OP4 E007DC 0 +OP4 E007DD 0 +OP4 E007DE 0 +OP4 E007DF 0 +OP4 E007E0 0 +OP4 E007E1 0 +OP4 E007E2 0 +OP4 E007E3 0 +OP4 E007E4 0 +OP4 E007E5 0 +OP4 E007E6 0 +OP4 E007E7 0 +OP4 E007E8 0 +OP4 E007E9 0 +OP4 E007EA 0 +OP4 E007EB 0 +OP4 E007EC 0 +OP4 E007ED 0 +OP4 E007EE 0 +OP4 E007EF 0 +OP4 E007F0 0 +OP4 E007F1 0 +OP4 E007F2 0 +OP4 E007F3 0 +OP4 E007F4 0 +OP4 E007F5 0 +OP4 E007F6 0 +OP4 E007F7 0 +OP4 E007F8 0 +OP4 E007F9 0 +OP4 E007FA 0 +OP4 E007FB 0 +OP4 E007FC 0 +OP4 E007FD 0 +OP4 E007FE 0 +OP4 E007FF 0 +OP4 E00800 0 +OP4 E00801 0 +OP4 E00802 0 +OP4 E00803 0 +OP4 E00804 0 +OP4 E00805 0 +OP4 E00806 0 +OP4 E00807 0 +OP4 E00808 0 +OP4 E00809 0 +OP4 E0080A 0 +OP4 E0080B 0 +OP4 E0080C 0 +OP4 E0080D 0 +OP4 E0080E 0 +OP4 E0080F 0 +OP4 E00810 0 +OP4 E00811 0 +OP4 E00812 0 +OP4 E00813 0 +OP4 E00814 0 +OP4 E00815 0 +OP4 E00816 0 +OP4 E00817 0 +OP4 E00818 0 +OP4 E00819 0 +OP4 E0081A 0 +OP4 E0081B 0 +OP4 E0081C 0 +OP4 E0081D 0 +OP4 E0081E 0 +OP4 E0081F 0 +OP4 E00820 0 +OP4 E00821 0 +OP4 E00822 0 +OP4 E00823 0 +OP4 E00824 0 +OP4 E00825 0 +OP4 E00826 0 +OP4 E00827 0 +OP4 E00828 0 +OP4 E00829 0 +OP4 E0082A 0 +OP4 E0082B 0 +OP4 E0082C 0 +OP4 E0082D 0 +OP4 E0082E 0 +OP4 E0082F 0 +OP4 E00830 0 +OP4 E00831 0 +OP4 E00832 0 +OP4 E00833 0 +OP4 E00834 0 +OP4 E00835 0 +OP4 E00836 0 +OP4 E00837 0 +OP4 E00838 0 +OP4 E00839 0 +OP4 E0083A 0 +OP4 E0083B 0 +OP4 E0083C 0 +OP4 E0083D 0 +OP4 E0083E 0 +OP4 E0083F 0 +OP4 E00840 0 +OP4 E00841 0 +OP4 E00842 0 +OP4 E00843 0 +OP4 E00844 0 +OP4 E00845 0 +OP4 E00846 0 +OP4 E00847 0 +OP4 E00848 0 +OP4 E00849 0 +OP4 E0084A 0 +OP4 E0084B 0 +OP4 E0084C 0 +OP4 E0084D 0 +OP4 E0084E 0 +OP4 E0084F 0 +OP4 E00850 0 +OP4 E00851 0 +OP4 E00852 0 +OP4 E00853 0 +OP4 E00854 0 +OP4 E00855 0 +OP4 E00856 0 +OP4 E00857 0 +OP4 E00858 0 +OP4 E00859 0 +OP4 E0085A 0 +OP4 E0085B 0 +OP4 E0085C 0 +OP4 E0085D 0 +OP4 E0085E 0 +OP4 E0085F 0 +OP4 E00860 0 +OP4 E00861 0 +OP4 E00862 0 +OP4 E00863 0 +OP4 E00864 0 +OP4 E00865 0 +OP4 E00866 0 +OP4 E00867 0 +OP4 E00868 0 +OP4 E00869 0 +OP4 E0086A 0 +OP4 E0086B 0 +OP4 E0086C 0 +OP4 E0086D 0 +OP4 E0086E 0 +OP4 E0086F 0 +OP4 E00870 0 +OP4 E00871 0 +OP4 E00872 0 +OP4 E00873 0 +OP4 E00874 0 +OP4 E00875 0 +OP4 E00876 0 +OP4 E00877 0 +OP4 E00878 0 +OP4 E00879 0 +OP4 E0087A 0 +OP4 E0087B 0 +OP4 E0087C 0 +OP4 E0087D 0 +OP4 E0087E 0 +OP4 E0087F 0 +OP4 E00880 0 +OP4 E00881 0 +OP4 E00882 0 +OP4 E00883 0 +OP4 E00884 0 +OP4 E00885 0 +OP4 E00886 0 +OP4 E00887 0 +OP4 E00888 0 +OP4 E00889 0 +OP4 E0088A 0 +OP4 E0088B 0 +OP4 E0088C 0 +OP4 E0088D 0 +OP4 E0088E 0 +OP4 E0088F 0 +OP4 E00890 0 +OP4 E00891 0 +OP4 E00892 0 +OP4 E00893 0 +OP4 E00894 0 +OP4 E00895 0 +OP4 E00896 0 +OP4 E00897 0 +OP4 E00898 0 +OP4 E00899 0 +OP4 E0089A 0 +OP4 E0089B 0 +OP4 E0089C 0 +OP4 E0089D 0 +OP4 E0089E 0 +OP4 E0089F 0 +OP4 E008A0 0 +OP4 E008A1 0 +OP4 E008A2 0 +OP4 E008A3 0 +OP4 E008A4 0 +OP4 E008A5 0 +OP4 E008A6 0 +OP4 E008A7 0 +OP4 E008A8 0 +OP4 E008A9 0 +OP4 E008AA 0 +OP4 E008AB 0 +OP4 E008AC 0 +OP4 E008AD 0 +OP4 E008AE 0 +OP4 E008AF 0 +OP4 E008B0 0 +OP4 E008B1 0 +OP4 E008B2 0 +OP4 E008B3 0 +OP4 E008B4 0 +OP4 E008B5 0 +OP4 E008B6 0 +OP4 E008B7 0 +OP4 E008B8 0 +OP4 E008B9 0 +OP4 E008BA 0 +OP4 E008BB 0 +OP4 E008BC 0 +OP4 E008BD 0 +OP4 E008BE 0 +OP4 E008BF 0 +OP4 E008C0 0 +OP4 E008C1 0 +OP4 E008C2 0 +OP4 E008C3 0 +OP4 E008C4 0 +OP4 E008C5 0 +OP4 E008C6 0 +OP4 E008C7 0 +OP4 E008C8 0 +OP4 E008C9 0 +OP4 E008CA 0 +OP4 E008CB 0 +OP4 E008CC 0 +OP4 E008CD 0 +OP4 E008CE 0 +OP4 E008CF 0 +OP4 E008D0 0 +OP4 E008D1 0 +OP4 E008D2 0 +OP4 E008D3 0 +OP4 E008D4 0 +OP4 E008D5 0 +OP4 E008D6 0 +OP4 E008D7 0 +OP4 E008D8 0 +OP4 E008D9 0 +OP4 E008DA 0 +OP4 E008DB 0 +OP4 E008DC 0 +OP4 E008DD 0 +OP4 E008DE 0 +OP4 E008DF 0 +OP4 E008E0 0 +OP4 E008E1 0 +OP4 E008E2 0 +OP4 E008E3 0 +OP4 E008E4 0 +OP4 E008E5 0 +OP4 E008E6 0 +OP4 E008E7 0 +OP4 E008E8 0 +OP4 E008E9 0 +OP4 E008EA 0 +OP4 E008EB 0 +OP4 E008EC 0 +OP4 E008ED 0 +OP4 E008EE 0 +OP4 E008EF 0 +OP4 E008F0 0 +OP4 E008F1 0 +OP4 E008F2 0 +OP4 E008F3 0 +OP4 E008F4 0 +OP4 E008F5 0 +OP4 E008F6 0 +OP4 E008F7 0 +OP4 E008F8 0 +OP4 E008F9 0 +OP4 E008FA 0 +OP4 E008FB 0 +OP4 E008FC 0 +OP4 E008FD 0 +OP4 E008FE 0 +OP4 E008FF 0 +OP4 E00900 0 +OP4 E00901 0 +OP4 E00902 0 +OP4 E00903 0 +OP4 E00904 0 +OP4 E00905 0 +OP4 E00906 0 +OP4 E00907 0 +OP4 E00908 0 +OP4 E00909 0 +OP4 E0090A 0 +OP4 E0090B 0 +OP4 E0090C 0 +OP4 E0090D 0 +OP4 E0090E 0 +OP4 E0090F 0 +OP4 E00910 0 +OP4 E00911 0 +OP4 E00912 0 +OP4 E00913 0 +OP4 E00914 0 +OP4 E00915 0 +OP4 E00916 0 +OP4 E00917 0 +OP4 E00918 0 +OP4 E00919 0 +OP4 E0091A 0 +OP4 E0091B 0 +OP4 E0091C 0 +OP4 E0091D 0 +OP4 E0091E 0 +OP4 E0091F 0 +OP4 E00920 0 +OP4 E00921 0 +OP4 E00922 0 +OP4 E00923 0 +OP4 E00924 0 +OP4 E00925 0 +OP4 E00926 0 +OP4 E00927 0 +OP4 E00928 0 +OP4 E00929 0 +OP4 E0092A 0 +OP4 E0092B 0 +OP4 E0092C 0 +OP4 E0092D 0 +OP4 E0092E 0 +OP4 E0092F 0 +OP4 E00930 0 +OP4 E00931 0 +OP4 E00932 0 +OP4 E00933 0 +OP4 E00934 0 +OP4 E00935 0 +OP4 E00936 0 +OP4 E00937 0 +OP4 E00938 0 +OP4 E00939 0 +OP4 E0093A 0 +OP4 E0093B 0 +OP4 E0093C 0 +OP4 E0093D 0 +OP4 E0093E 0 +OP4 E0093F 0 +OP4 E00940 0 +OP4 E00941 0 +OP4 E00942 0 +OP4 E00943 0 +OP4 E00944 0 +OP4 E00945 0 +OP4 E00946 0 +OP4 E00947 0 +OP4 E00948 0 +OP4 E00949 0 +OP4 E0094A 0 +OP4 E0094B 0 +OP4 E0094C 0 +OP4 E0094D 0 +OP4 E0094E 0 +OP4 E0094F 0 +OP4 E00950 0 +OP4 E00951 0 +OP4 E00952 0 +OP4 E00953 0 +OP4 E00954 0 +OP4 E00955 0 +OP4 E00956 0 +OP4 E00957 0 +OP4 E00958 0 +OP4 E00959 0 +OP4 E0095A 0 +OP4 E0095B 0 +OP4 E0095C 0 +OP4 E0095D 0 +OP4 E0095E 0 +OP4 E0095F 0 +OP4 E00960 0 +OP4 E00961 0 +OP4 E00962 0 +OP4 E00963 0 +OP4 E00964 0 +OP4 E00965 0 +OP4 E00966 0 +OP4 E00967 0 +OP4 E00968 0 +OP4 E00969 0 +OP4 E0096A 0 +OP4 E0096B 0 +OP4 E0096C 0 +OP4 E0096D 0 +OP4 E0096E 0 +OP4 E0096F 0 +OP4 E00970 0 +OP4 E00971 0 +OP4 E00972 0 +OP4 E00973 0 +OP4 E00974 0 +OP4 E00975 0 +OP4 E00976 0 +OP4 E00977 0 +OP4 E00978 0 +OP4 E00979 0 +OP4 E0097A 0 +OP4 E0097B 0 +OP4 E0097C 0 +OP4 E0097D 0 +OP4 E0097E 0 +OP4 E0097F 0 +OP4 E00980 0 +OP4 E00981 0 +OP4 E00982 0 +OP4 E00983 0 +OP4 E00984 0 +OP4 E00985 0 +OP4 E00986 0 +OP4 E00987 0 +OP4 E00988 0 +OP4 E00989 0 +OP4 E0098A 0 +OP4 E0098B 0 +OP4 E0098C 0 +OP4 E0098D 0 +OP4 E0098E 0 +OP4 E0098F 0 +OP4 E00990 0 +OP4 E00991 0 +OP4 E00992 0 +OP4 E00993 0 +OP4 E00994 0 +OP4 E00995 0 +OP4 E00996 0 +OP4 E00997 0 +OP4 E00998 0 +OP4 E00999 0 +OP4 E0099A 0 +OP4 E0099B 0 +OP4 E0099C 0 +OP4 E0099D 0 +OP4 E0099E 0 +OP4 E0099F 0 +OP4 E009A0 0 +OP4 E009A1 0 +OP4 E009A2 0 +OP4 E009A3 0 +OP4 E009A4 0 +OP4 E009A5 0 +OP4 E009A6 0 +OP4 E009A7 0 +OP4 E009A8 0 +OP4 E009A9 0 +OP4 E009AA 0 +OP4 E009AB 0 +OP4 E009AC 0 +OP4 E009AD 0 +OP4 E009AE 0 +OP4 E009AF 0 +OP4 E009B0 0 +OP4 E009B1 0 +OP4 E009B2 0 +OP4 E009B3 0 +OP4 E009B4 0 +OP4 E009B5 0 +OP4 E009B6 0 +OP4 E009B7 0 +OP4 E009B8 0 +OP4 E009B9 0 +OP4 E009BA 0 +OP4 E009BB 0 +OP4 E009BC 0 +OP4 E009BD 0 +OP4 E009BE 0 +OP4 E009BF 0 +OP4 E009C0 0 +OP4 E009C1 0 +OP4 E009C2 0 +OP4 E009C3 0 +OP4 E009C4 0 +OP4 E009C5 0 +OP4 E009C6 0 +OP4 E009C7 0 +OP4 E009C8 0 +OP4 E009C9 0 +OP4 E009CA 0 +OP4 E009CB 0 +OP4 E009CC 0 +OP4 E009CD 0 +OP4 E009CE 0 +OP4 E009CF 0 +OP4 E009D0 0 +OP4 E009D1 0 +OP4 E009D2 0 +OP4 E009D3 0 +OP4 E009D4 0 +OP4 E009D5 0 +OP4 E009D6 0 +OP4 E009D7 0 +OP4 E009D8 0 +OP4 E009D9 0 +OP4 E009DA 0 +OP4 E009DB 0 +OP4 E009DC 0 +OP4 E009DD 0 +OP4 E009DE 0 +OP4 E009DF 0 +OP4 E009E0 0 +OP4 E009E1 0 +OP4 E009E2 0 +OP4 E009E3 0 +OP4 E009E4 0 +OP4 E009E5 0 +OP4 E009E6 0 +OP4 E009E7 0 +OP4 E009E8 0 +OP4 E009E9 0 +OP4 E009EA 0 +OP4 E009EB 0 +OP4 E009EC 0 +OP4 E009ED 0 +OP4 E009EE 0 +OP4 E009EF 0 +OP4 E009F0 0 +OP4 E009F1 0 +OP4 E009F2 0 +OP4 E009F3 0 +OP4 E009F4 0 +OP4 E009F5 0 +OP4 E009F6 0 +OP4 E009F7 0 +OP4 E009F8 0 +OP4 E009F9 0 +OP4 E009FA 0 +OP4 E009FB 0 +OP4 E009FC 0 +OP4 E009FD 0 +OP4 E009FE 0 +OP4 E009FF 0 +OP4 E00A00 0 +OP4 E00A01 0 +OP4 E00A02 0 +OP4 E00A03 0 +OP4 E00A04 0 +OP4 E00A05 0 +OP4 E00A06 0 +OP4 E00A07 0 +OP4 E00A08 0 +OP4 E00A09 0 +OP4 E00A0A 0 +OP4 E00A0B 0 +OP4 E00A0C 0 +OP4 E00A0D 0 +OP4 E00A0E 0 +OP4 E00A0F 0 +OP4 E00A10 0 +OP4 E00A11 0 +OP4 E00A12 0 +OP4 E00A13 0 +OP4 E00A14 0 +OP4 E00A15 0 +OP4 E00A16 0 +OP4 E00A17 0 +OP4 E00A18 0 +OP4 E00A19 0 +OP4 E00A1A 0 +OP4 E00A1B 0 +OP4 E00A1C 0 +OP4 E00A1D 0 +OP4 E00A1E 0 +OP4 E00A1F 0 +OP4 E00A20 0 +OP4 E00A21 0 +OP4 E00A22 0 +OP4 E00A23 0 +OP4 E00A24 0 +OP4 E00A25 0 +OP4 E00A26 0 +OP4 E00A27 0 +OP4 E00A28 0 +OP4 E00A29 0 +OP4 E00A2A 0 +OP4 E00A2B 0 +OP4 E00A2C 0 +OP4 E00A2D 0 +OP4 E00A2E 0 +OP4 E00A2F 0 +OP4 E00A30 0 +OP4 E00A31 0 +OP4 E00A32 0 +OP4 E00A33 0 +OP4 E00A34 0 +OP4 E00A35 0 +OP4 E00A36 0 +OP4 E00A37 0 +OP4 E00A38 0 +OP4 E00A39 0 +OP4 E00A3A 0 +OP4 E00A3B 0 +OP4 E00A3C 0 +OP4 E00A3D 0 +OP4 E00A3E 0 +OP4 E00A3F 0 +OP4 E00A40 0 +OP4 E00A41 0 +OP4 E00A42 0 +OP4 E00A43 0 +OP4 E00A44 0 +OP4 E00A45 0 +OP4 E00A46 0 +OP4 E00A47 0 +OP4 E00A48 0 +OP4 E00A49 0 +OP4 E00A4A 0 +OP4 E00A4B 0 +OP4 E00A4C 0 +OP4 E00A4D 0 +OP4 E00A4E 0 +OP4 E00A4F 0 +OP4 E00A50 0 +OP4 E00A51 0 +OP4 E00A52 0 +OP4 E00A53 0 +OP4 E00A54 0 +OP4 E00A55 0 +OP4 E00A56 0 +OP4 E00A57 0 +OP4 E00A58 0 +OP4 E00A59 0 +OP4 E00A5A 0 +OP4 E00A5B 0 +OP4 E00A5C 0 +OP4 E00A5D 0 +OP4 E00A5E 0 +OP4 E00A5F 0 +OP4 E00A60 0 +OP4 E00A61 0 +OP4 E00A62 0 +OP4 E00A63 0 +OP4 E00A64 0 +OP4 E00A65 0 +OP4 E00A66 0 +OP4 E00A67 0 +OP4 E00A68 0 +OP4 E00A69 0 +OP4 E00A6A 0 +OP4 E00A6B 0 +OP4 E00A6C 0 +OP4 E00A6D 0 +OP4 E00A6E 0 +OP4 E00A6F 0 +OP4 E00A70 0 +OP4 E00A71 0 +OP4 E00A72 0 +OP4 E00A73 0 +OP4 E00A74 0 +OP4 E00A75 0 +OP4 E00A76 0 +OP4 E00A77 0 +OP4 E00A78 0 +OP4 E00A79 0 +OP4 E00A7A 0 +OP4 E00A7B 0 +OP4 E00A7C 0 +OP4 E00A7D 0 +OP4 E00A7E 0 +OP4 E00A7F 0 +OP4 E00A80 0 +OP4 E00A81 0 +OP4 E00A82 0 +OP4 E00A83 0 +OP4 E00A84 0 +OP4 E00A85 0 +OP4 E00A86 0 +OP4 E00A87 0 +OP4 E00A88 0 +OP4 E00A89 0 +OP4 E00A8A 0 +OP4 E00A8B 0 +OP4 E00A8C 0 +OP4 E00A8D 0 +OP4 E00A8E 0 +OP4 E00A8F 0 +OP4 E00A90 0 +OP4 E00A91 0 +OP4 E00A92 0 +OP4 E00A93 0 +OP4 E00A94 0 +OP4 E00A95 0 +OP4 E00A96 0 +OP4 E00A97 0 +OP4 E00A98 0 +OP4 E00A99 0 +OP4 E00A9A 0 +OP4 E00A9B 0 +OP4 E00A9C 0 +OP4 E00A9D 0 +OP4 E00A9E 0 +OP4 E00A9F 0 +OP4 E00AA0 0 +OP4 E00AA1 0 +OP4 E00AA2 0 +OP4 E00AA3 0 +OP4 E00AA4 0 +OP4 E00AA5 0 +OP4 E00AA6 0 +OP4 E00AA7 0 +OP4 E00AA8 0 +OP4 E00AA9 0 +OP4 E00AAA 0 +OP4 E00AAB 0 +OP4 E00AAC 0 +OP4 E00AAD 0 +OP4 E00AAE 0 +OP4 E00AAF 0 +OP4 E00AB0 0 +OP4 E00AB1 0 +OP4 E00AB2 0 +OP4 E00AB3 0 +OP4 E00AB4 0 +OP4 E00AB5 0 +OP4 E00AB6 0 +OP4 E00AB7 0 +OP4 E00AB8 0 +OP4 E00AB9 0 +OP4 E00ABA 0 +OP4 E00ABB 0 +OP4 E00ABC 0 +OP4 E00ABD 0 +OP4 E00ABE 0 +OP4 E00ABF 0 +OP4 E00AC0 0 +OP4 E00AC1 0 +OP4 E00AC2 0 +OP4 E00AC3 0 +OP4 E00AC4 0 +OP4 E00AC5 0 +OP4 E00AC6 0 +OP4 E00AC7 0 +OP4 E00AC8 0 +OP4 E00AC9 0 +OP4 E00ACA 0 +OP4 E00ACB 0 +OP4 E00ACC 0 +OP4 E00ACD 0 +OP4 E00ACE 0 +OP4 E00ACF 0 +OP4 E00AD0 0 +OP4 E00AD1 0 +OP4 E00AD2 0 +OP4 E00AD3 0 +OP4 E00AD4 0 +OP4 E00AD5 0 +OP4 E00AD6 0 +OP4 E00AD7 0 +OP4 E00AD8 0 +OP4 E00AD9 0 +OP4 E00ADA 0 +OP4 E00ADB 0 +OP4 E00ADC 0 +OP4 E00ADD 0 +OP4 E00ADE 0 +OP4 E00ADF 0 +OP4 E00AE0 0 +OP4 E00AE1 0 +OP4 E00AE2 0 +OP4 E00AE3 0 +OP4 E00AE4 0 +OP4 E00AE5 0 +OP4 E00AE6 0 +OP4 E00AE7 0 +OP4 E00AE8 0 +OP4 E00AE9 0 +OP4 E00AEA 0 +OP4 E00AEB 0 +OP4 E00AEC 0 +OP4 E00AED 0 +OP4 E00AEE 0 +OP4 E00AEF 0 +OP4 E00AF0 0 +OP4 E00AF1 0 +OP4 E00AF2 0 +OP4 E00AF3 0 +OP4 E00AF4 0 +OP4 E00AF5 0 +OP4 E00AF6 0 +OP4 E00AF7 0 +OP4 E00AF8 0 +OP4 E00AF9 0 +OP4 E00AFA 0 +OP4 E00AFB 0 +OP4 E00AFC 0 +OP4 E00AFD 0 +OP4 E00AFE 0 +OP4 E00AFF 0 +OP4 E00B00 0 +OP4 E00B01 0 +OP4 E00B02 0 +OP4 E00B03 0 +OP4 E00B04 0 +OP4 E00B05 0 +OP4 E00B06 0 +OP4 E00B07 0 +OP4 E00B08 0 +OP4 E00B09 0 +OP4 E00B0A 0 +OP4 E00B0B 0 +OP4 E00B0C 0 +OP4 E00B0D 0 +OP4 E00B0E 0 +OP4 E00B0F 0 +OP4 E00B10 0 +OP4 E00B11 0 +OP4 E00B12 0 +OP4 E00B13 0 +OP4 E00B14 0 +OP4 E00B15 0 +OP4 E00B16 0 +OP4 E00B17 0 +OP4 E00B18 0 +OP4 E00B19 0 +OP4 E00B1A 0 +OP4 E00B1B 0 +OP4 E00B1C 0 +OP4 E00B1D 0 +OP4 E00B1E 0 +OP4 E00B1F 0 +OP4 E00B20 0 +OP4 E00B21 0 +OP4 E00B22 0 +OP4 E00B23 0 +OP4 E00B24 0 +OP4 E00B25 0 +OP4 E00B26 0 +OP4 E00B27 0 +OP4 E00B28 0 +OP4 E00B29 0 +OP4 E00B2A 0 +OP4 E00B2B 0 +OP4 E00B2C 0 +OP4 E00B2D 0 +OP4 E00B2E 0 +OP4 E00B2F 0 +OP4 E00B30 0 +OP4 E00B31 0 +OP4 E00B32 0 +OP4 E00B33 0 +OP4 E00B34 0 +OP4 E00B35 0 +OP4 E00B36 0 +OP4 E00B37 0 +OP4 E00B38 0 +OP4 E00B39 0 +OP4 E00B3A 0 +OP4 E00B3B 0 +OP4 E00B3C 0 +OP4 E00B3D 0 +OP4 E00B3E 0 +OP4 E00B3F 0 +OP4 E00B40 0 +OP4 E00B41 0 +OP4 E00B42 0 +OP4 E00B43 0 +OP4 E00B44 0 +OP4 E00B45 0 +OP4 E00B46 0 +OP4 E00B47 0 +OP4 E00B48 0 +OP4 E00B49 0 +OP4 E00B4A 0 +OP4 E00B4B 0 +OP4 E00B4C 0 +OP4 E00B4D 0 +OP4 E00B4E 0 +OP4 E00B4F 0 +OP4 E00B50 0 +OP4 E00B51 0 +OP4 E00B52 0 +OP4 E00B53 0 +OP4 E00B54 0 +OP4 E00B55 0 +OP4 E00B56 0 +OP4 E00B57 0 +OP4 E00B58 0 +OP4 E00B59 0 +OP4 E00B5A 0 +OP4 E00B5B 0 +OP4 E00B5C 0 +OP4 E00B5D 0 +OP4 E00B5E 0 +OP4 E00B5F 0 +OP4 E00B60 0 +OP4 E00B61 0 +OP4 E00B62 0 +OP4 E00B63 0 +OP4 E00B64 0 +OP4 E00B65 0 +OP4 E00B66 0 +OP4 E00B67 0 +OP4 E00B68 0 +OP4 E00B69 0 +OP4 E00B6A 0 +OP4 E00B6B 0 +OP4 E00B6C 0 +OP4 E00B6D 0 +OP4 E00B6E 0 +OP4 E00B6F 0 +OP4 E00B70 0 +OP4 E00B71 0 +OP4 E00B72 0 +OP4 E00B73 0 +OP4 E00B74 0 +OP4 E00B75 0 +OP4 E00B76 0 +OP4 E00B77 0 +OP4 E00B78 0 +OP4 E00B79 0 +OP4 E00B7A 0 +OP4 E00B7B 0 +OP4 E00B7C 0 +OP4 E00B7D 0 +OP4 E00B7E 0 +OP4 E00B7F 0 +OP4 E00B80 0 +OP4 E00B81 0 +OP4 E00B82 0 +OP4 E00B83 0 +OP4 E00B84 0 +OP4 E00B85 0 +OP4 E00B86 0 +OP4 E00B87 0 +OP4 E00B88 0 +OP4 E00B89 0 +OP4 E00B8A 0 +OP4 E00B8B 0 +OP4 E00B8C 0 +OP4 E00B8D 0 +OP4 E00B8E 0 +OP4 E00B8F 0 +OP4 E00B90 0 +OP4 E00B91 0 +OP4 E00B92 0 +OP4 E00B93 0 +OP4 E00B94 0 +OP4 E00B95 0 +OP4 E00B96 0 +OP4 E00B97 0 +OP4 E00B98 0 +OP4 E00B99 0 +OP4 E00B9A 0 +OP4 E00B9B 0 +OP4 E00B9C 0 +OP4 E00B9D 0 +OP4 E00B9E 0 +OP4 E00B9F 0 +OP4 E00BA0 0 +OP4 E00BA1 0 +OP4 E00BA2 0 +OP4 E00BA3 0 +OP4 E00BA4 0 +OP4 E00BA5 0 +OP4 E00BA6 0 +OP4 E00BA7 0 +OP4 E00BA8 0 +OP4 E00BA9 0 +OP4 E00BAA 0 +OP4 E00BAB 0 +OP4 E00BAC 0 +OP4 E00BAD 0 +OP4 E00BAE 0 +OP4 E00BAF 0 +OP4 E00BB0 0 +OP4 E00BB1 0 +OP4 E00BB2 0 +OP4 E00BB3 0 +OP4 E00BB4 0 +OP4 E00BB5 0 +OP4 E00BB6 0 +OP4 E00BB7 0 +OP4 E00BB8 0 +OP4 E00BB9 0 +OP4 E00BBA 0 +OP4 E00BBB 0 +OP4 E00BBC 0 +OP4 E00BBD 0 +OP4 E00BBE 0 +OP4 E00BBF 0 +OP4 E00BC0 0 +OP4 E00BC1 0 +OP4 E00BC2 0 +OP4 E00BC3 0 +OP4 E00BC4 0 +OP4 E00BC5 0 +OP4 E00BC6 0 +OP4 E00BC7 0 +OP4 E00BC8 0 +OP4 E00BC9 0 +OP4 E00BCA 0 +OP4 E00BCB 0 +OP4 E00BCC 0 +OP4 E00BCD 0 +OP4 E00BCE 0 +OP4 E00BCF 0 +OP4 E00BD0 0 +OP4 E00BD1 0 +OP4 E00BD2 0 +OP4 E00BD3 0 +OP4 E00BD4 0 +OP4 E00BD5 0 +OP4 E00BD6 0 +OP4 E00BD7 0 +OP4 E00BD8 0 +OP4 E00BD9 0 +OP4 E00BDA 0 +OP4 E00BDB 0 +OP4 E00BDC 0 +OP4 E00BDD 0 +OP4 E00BDE 0 +OP4 E00BDF 0 +OP4 E00BE0 0 +OP4 E00BE1 0 +OP4 E00BE2 0 +OP4 E00BE3 0 +OP4 E00BE4 0 +OP4 E00BE5 0 +OP4 E00BE6 0 +OP4 E00BE7 0 +OP4 E00BE8 0 +OP4 E00BE9 0 +OP4 E00BEA 0 +OP4 E00BEB 0 +OP4 E00BEC 0 +OP4 E00BED 0 +OP4 E00BEE 0 +OP4 E00BEF 0 +OP4 E00BF0 0 +OP4 E00BF1 0 +OP4 E00BF2 0 +OP4 E00BF3 0 +OP4 E00BF4 0 +OP4 E00BF5 0 +OP4 E00BF6 0 +OP4 E00BF7 0 +OP4 E00BF8 0 +OP4 E00BF9 0 +OP4 E00BFA 0 +OP4 E00BFB 0 +OP4 E00BFC 0 +OP4 E00BFD 0 +OP4 E00BFE 0 +OP4 E00BFF 0 +OP4 E00C00 0 +OP4 E00C01 0 +OP4 E00C02 0 +OP4 E00C03 0 +OP4 E00C04 0 +OP4 E00C05 0 +OP4 E00C06 0 +OP4 E00C07 0 +OP4 E00C08 0 +OP4 E00C09 0 +OP4 E00C0A 0 +OP4 E00C0B 0 +OP4 E00C0C 0 +OP4 E00C0D 0 +OP4 E00C0E 0 +OP4 E00C0F 0 +OP4 E00C10 0 +OP4 E00C11 0 +OP4 E00C12 0 +OP4 E00C13 0 +OP4 E00C14 0 +OP4 E00C15 0 +OP4 E00C16 0 +OP4 E00C17 0 +OP4 E00C18 0 +OP4 E00C19 0 +OP4 E00C1A 0 +OP4 E00C1B 0 +OP4 E00C1C 0 +OP4 E00C1D 0 +OP4 E00C1E 0 +OP4 E00C1F 0 +OP4 E00C20 0 +OP4 E00C21 0 +OP4 E00C22 0 +OP4 E00C23 0 +OP4 E00C24 0 +OP4 E00C25 0 +OP4 E00C26 0 +OP4 E00C27 0 +OP4 E00C28 0 +OP4 E00C29 0 +OP4 E00C2A 0 +OP4 E00C2B 0 +OP4 E00C2C 0 +OP4 E00C2D 0 +OP4 E00C2E 0 +OP4 E00C2F 0 +OP4 E00C30 0 +OP4 E00C31 0 +OP4 E00C32 0 +OP4 E00C33 0 +OP4 E00C34 0 +OP4 E00C35 0 +OP4 E00C36 0 +OP4 E00C37 0 +OP4 E00C38 0 +OP4 E00C39 0 +OP4 E00C3A 0 +OP4 E00C3B 0 +OP4 E00C3C 0 +OP4 E00C3D 0 +OP4 E00C3E 0 +OP4 E00C3F 0 +OP4 E00C40 0 +OP4 E00C41 0 +OP4 E00C42 0 +OP4 E00C43 0 +OP4 E00C44 0 +OP4 E00C45 0 +OP4 E00C46 0 +OP4 E00C47 0 +OP4 E00C48 0 +OP4 E00C49 0 +OP4 E00C4A 0 +OP4 E00C4B 0 +OP4 E00C4C 0 +OP4 E00C4D 0 +OP4 E00C4E 0 +OP4 E00C4F 0 +OP4 E00C50 0 +OP4 E00C51 0 +OP4 E00C52 0 +OP4 E00C53 0 +OP4 E00C54 0 +OP4 E00C55 0 +OP4 E00C56 0 +OP4 E00C57 0 +OP4 E00C58 0 +OP4 E00C59 0 +OP4 E00C5A 0 +OP4 E00C5B 0 +OP4 E00C5C 0 +OP4 E00C5D 0 +OP4 E00C5E 0 +OP4 E00C5F 0 +OP4 E00C60 0 +OP4 E00C61 0 +OP4 E00C62 0 +OP4 E00C63 0 +OP4 E00C64 0 +OP4 E00C65 0 +OP4 E00C66 0 +OP4 E00C67 0 +OP4 E00C68 0 +OP4 E00C69 0 +OP4 E00C6A 0 +OP4 E00C6B 0 +OP4 E00C6C 0 +OP4 E00C6D 0 +OP4 E00C6E 0 +OP4 E00C6F 0 +OP4 E00C70 0 +OP4 E00C71 0 +OP4 E00C72 0 +OP4 E00C73 0 +OP4 E00C74 0 +OP4 E00C75 0 +OP4 E00C76 0 +OP4 E00C77 0 +OP4 E00C78 0 +OP4 E00C79 0 +OP4 E00C7A 0 +OP4 E00C7B 0 +OP4 E00C7C 0 +OP4 E00C7D 0 +OP4 E00C7E 0 +OP4 E00C7F 0 +OP4 E00C80 0 +OP4 E00C81 0 +OP4 E00C82 0 +OP4 E00C83 0 +OP4 E00C84 0 +OP4 E00C85 0 +OP4 E00C86 0 +OP4 E00C87 0 +OP4 E00C88 0 +OP4 E00C89 0 +OP4 E00C8A 0 +OP4 E00C8B 0 +OP4 E00C8C 0 +OP4 E00C8D 0 +OP4 E00C8E 0 +OP4 E00C8F 0 +OP4 E00C90 0 +OP4 E00C91 0 +OP4 E00C92 0 +OP4 E00C93 0 +OP4 E00C94 0 +OP4 E00C95 0 +OP4 E00C96 0 +OP4 E00C97 0 +OP4 E00C98 0 +OP4 E00C99 0 +OP4 E00C9A 0 +OP4 E00C9B 0 +OP4 E00C9C 0 +OP4 E00C9D 0 +OP4 E00C9E 0 +OP4 E00C9F 0 +OP4 E00CA0 0 +OP4 E00CA1 0 +OP4 E00CA2 0 +OP4 E00CA3 0 +OP4 E00CA4 0 +OP4 E00CA5 0 +OP4 E00CA6 0 +OP4 E00CA7 0 +OP4 E00CA8 0 +OP4 E00CA9 0 +OP4 E00CAA 0 +OP4 E00CAB 0 +OP4 E00CAC 0 +OP4 E00CAD 0 +OP4 E00CAE 0 +OP4 E00CAF 0 +OP4 E00CB0 0 +OP4 E00CB1 0 +OP4 E00CB2 0 +OP4 E00CB3 0 +OP4 E00CB4 0 +OP4 E00CB5 0 +OP4 E00CB6 0 +OP4 E00CB7 0 +OP4 E00CB8 0 +OP4 E00CB9 0 +OP4 E00CBA 0 +OP4 E00CBB 0 +OP4 E00CBC 0 +OP4 E00CBD 0 +OP4 E00CBE 0 +OP4 E00CBF 0 +OP4 E00CC0 0 +OP4 E00CC1 0 +OP4 E00CC2 0 +OP4 E00CC3 0 +OP4 E00CC4 0 +OP4 E00CC5 0 +OP4 E00CC6 0 +OP4 E00CC7 0 +OP4 E00CC8 0 +OP4 E00CC9 0 +OP4 E00CCA 0 +OP4 E00CCB 0 +OP4 E00CCC 0 +OP4 E00CCD 0 +OP4 E00CCE 0 +OP4 E00CCF 0 +OP4 E00CD0 0 +OP4 E00CD1 0 +OP4 E00CD2 0 +OP4 E00CD3 0 +OP4 E00CD4 0 +OP4 E00CD5 0 +OP4 E00CD6 0 +OP4 E00CD7 0 +OP4 E00CD8 0 +OP4 E00CD9 0 +OP4 E00CDA 0 +OP4 E00CDB 0 +OP4 E00CDC 0 +OP4 E00CDD 0 +OP4 E00CDE 0 +OP4 E00CDF 0 +OP4 E00CE0 0 +OP4 E00CE1 0 +OP4 E00CE2 0 +OP4 E00CE3 0 +OP4 E00CE4 0 +OP4 E00CE5 0 +OP4 E00CE6 0 +OP4 E00CE7 0 +OP4 E00CE8 0 +OP4 E00CE9 0 +OP4 E00CEA 0 +OP4 E00CEB 0 +OP4 E00CEC 0 +OP4 E00CED 0 +OP4 E00CEE 0 +OP4 E00CEF 0 +OP4 E00CF0 0 +OP4 E00CF1 0 +OP4 E00CF2 0 +OP4 E00CF3 0 +OP4 E00CF4 0 +OP4 E00CF5 0 +OP4 E00CF6 0 +OP4 E00CF7 0 +OP4 E00CF8 0 +OP4 E00CF9 0 +OP4 E00CFA 0 +OP4 E00CFB 0 +OP4 E00CFC 0 +OP4 E00CFD 0 +OP4 E00CFE 0 +OP4 E00CFF 0 +OP4 E00D00 0 +OP4 E00D01 0 +OP4 E00D02 0 +OP4 E00D03 0 +OP4 E00D04 0 +OP4 E00D05 0 +OP4 E00D06 0 +OP4 E00D07 0 +OP4 E00D08 0 +OP4 E00D09 0 +OP4 E00D0A 0 +OP4 E00D0B 0 +OP4 E00D0C 0 +OP4 E00D0D 0 +OP4 E00D0E 0 +OP4 E00D0F 0 +OP4 E00D10 0 +OP4 E00D11 0 +OP4 E00D12 0 +OP4 E00D13 0 +OP4 E00D14 0 +OP4 E00D15 0 +OP4 E00D16 0 +OP4 E00D17 0 +OP4 E00D18 0 +OP4 E00D19 0 +OP4 E00D1A 0 +OP4 E00D1B 0 +OP4 E00D1C 0 +OP4 E00D1D 0 +OP4 E00D1E 0 +OP4 E00D1F 0 +OP4 E00D20 0 +OP4 E00D21 0 +OP4 E00D22 0 +OP4 E00D23 0 +OP4 E00D24 0 +OP4 E00D25 0 +OP4 E00D26 0 +OP4 E00D27 0 +OP4 E00D28 0 +OP4 E00D29 0 +OP4 E00D2A 0 +OP4 E00D2B 0 +OP4 E00D2C 0 +OP4 E00D2D 0 +OP4 E00D2E 0 +OP4 E00D2F 0 +OP4 E00D30 0 +OP4 E00D31 0 +OP4 E00D32 0 +OP4 E00D33 0 +OP4 E00D34 0 +OP4 E00D35 0 +OP4 E00D36 0 +OP4 E00D37 0 +OP4 E00D38 0 +OP4 E00D39 0 +OP4 E00D3A 0 +OP4 E00D3B 0 +OP4 E00D3C 0 +OP4 E00D3D 0 +OP4 E00D3E 0 +OP4 E00D3F 0 +OP4 E00D40 0 +OP4 E00D41 0 +OP4 E00D42 0 +OP4 E00D43 0 +OP4 E00D44 0 +OP4 E00D45 0 +OP4 E00D46 0 +OP4 E00D47 0 +OP4 E00D48 0 +OP4 E00D49 0 +OP4 E00D4A 0 +OP4 E00D4B 0 +OP4 E00D4C 0 +OP4 E00D4D 0 +OP4 E00D4E 0 +OP4 E00D4F 0 +OP4 E00D50 0 +OP4 E00D51 0 +OP4 E00D52 0 +OP4 E00D53 0 +OP4 E00D54 0 +OP4 E00D55 0 +OP4 E00D56 0 +OP4 E00D57 0 +OP4 E00D58 0 +OP4 E00D59 0 +OP4 E00D5A 0 +OP4 E00D5B 0 +OP4 E00D5C 0 +OP4 E00D5D 0 +OP4 E00D5E 0 +OP4 E00D5F 0 +OP4 E00D60 0 +OP4 E00D61 0 +OP4 E00D62 0 +OP4 E00D63 0 +OP4 E00D64 0 +OP4 E00D65 0 +OP4 E00D66 0 +OP4 E00D67 0 +OP4 E00D68 0 +OP4 E00D69 0 +OP4 E00D6A 0 +OP4 E00D6B 0 +OP4 E00D6C 0 +OP4 E00D6D 0 +OP4 E00D6E 0 +OP4 E00D6F 0 +OP4 E00D70 0 +OP4 E00D71 0 +OP4 E00D72 0 +OP4 E00D73 0 +OP4 E00D74 0 +OP4 E00D75 0 +OP4 E00D76 0 +OP4 E00D77 0 +OP4 E00D78 0 +OP4 E00D79 0 +OP4 E00D7A 0 +OP4 E00D7B 0 +OP4 E00D7C 0 +OP4 E00D7D 0 +OP4 E00D7E 0 +OP4 E00D7F 0 +OP4 E00D80 0 +OP4 E00D81 0 +OP4 E00D82 0 +OP4 E00D83 0 +OP4 E00D84 0 +OP4 E00D85 0 +OP4 E00D86 0 +OP4 E00D87 0 +OP4 E00D88 0 +OP4 E00D89 0 +OP4 E00D8A 0 +OP4 E00D8B 0 +OP4 E00D8C 0 +OP4 E00D8D 0 +OP4 E00D8E 0 +OP4 E00D8F 0 +OP4 E00D90 0 +OP4 E00D91 0 +OP4 E00D92 0 +OP4 E00D93 0 +OP4 E00D94 0 +OP4 E00D95 0 +OP4 E00D96 0 +OP4 E00D97 0 +OP4 E00D98 0 +OP4 E00D99 0 +OP4 E00D9A 0 +OP4 E00D9B 0 +OP4 E00D9C 0 +OP4 E00D9D 0 +OP4 E00D9E 0 +OP4 E00D9F 0 +OP4 E00DA0 0 +OP4 E00DA1 0 +OP4 E00DA2 0 +OP4 E00DA3 0 +OP4 E00DA4 0 +OP4 E00DA5 0 +OP4 E00DA6 0 +OP4 E00DA7 0 +OP4 E00DA8 0 +OP4 E00DA9 0 +OP4 E00DAA 0 +OP4 E00DAB 0 +OP4 E00DAC 0 +OP4 E00DAD 0 +OP4 E00DAE 0 +OP4 E00DAF 0 +OP4 E00DB0 0 +OP4 E00DB1 0 +OP4 E00DB2 0 +OP4 E00DB3 0 +OP4 E00DB4 0 +OP4 E00DB5 0 +OP4 E00DB6 0 +OP4 E00DB7 0 +OP4 E00DB8 0 +OP4 E00DB9 0 +OP4 E00DBA 0 +OP4 E00DBB 0 +OP4 E00DBC 0 +OP4 E00DBD 0 +OP4 E00DBE 0 +OP4 E00DBF 0 +OP4 E00DC0 0 +OP4 E00DC1 0 +OP4 E00DC2 0 +OP4 E00DC3 0 +OP4 E00DC4 0 +OP4 E00DC5 0 +OP4 E00DC6 0 +OP4 E00DC7 0 +OP4 E00DC8 0 +OP4 E00DC9 0 +OP4 E00DCA 0 +OP4 E00DCB 0 +OP4 E00DCC 0 +OP4 E00DCD 0 +OP4 E00DCE 0 +OP4 E00DCF 0 +OP4 E00DD0 0 +OP4 E00DD1 0 +OP4 E00DD2 0 +OP4 E00DD3 0 +OP4 E00DD4 0 +OP4 E00DD5 0 +OP4 E00DD6 0 +OP4 E00DD7 0 +OP4 E00DD8 0 +OP4 E00DD9 0 +OP4 E00DDA 0 +OP4 E00DDB 0 +OP4 E00DDC 0 +OP4 E00DDD 0 +OP4 E00DDE 0 +OP4 E00DDF 0 +OP4 E00DE0 0 +OP4 E00DE1 0 +OP4 E00DE2 0 +OP4 E00DE3 0 +OP4 E00DE4 0 +OP4 E00DE5 0 +OP4 E00DE6 0 +OP4 E00DE7 0 +OP4 E00DE8 0 +OP4 E00DE9 0 +OP4 E00DEA 0 +OP4 E00DEB 0 +OP4 E00DEC 0 +OP4 E00DED 0 +OP4 E00DEE 0 +OP4 E00DEF 0 +OP4 E00DF0 0 +OP4 E00DF1 0 +OP4 E00DF2 0 +OP4 E00DF3 0 +OP4 E00DF4 0 +OP4 E00DF5 0 +OP4 E00DF6 0 +OP4 E00DF7 0 +OP4 E00DF8 0 +OP4 E00DF9 0 +OP4 E00DFA 0 +OP4 E00DFB 0 +OP4 E00DFC 0 +OP4 E00DFD 0 +OP4 E00DFE 0 +OP4 E00DFF 0 +OP4 E00E00 0 +OP4 E00E01 0 +OP4 E00E02 0 +OP4 E00E03 0 +OP4 E00E04 0 +OP4 E00E05 0 +OP4 E00E06 0 +OP4 E00E07 0 +OP4 E00E08 0 +OP4 E00E09 0 +OP4 E00E0A 0 +OP4 E00E0B 0 +OP4 E00E0C 0 +OP4 E00E0D 0 +OP4 E00E0E 0 +OP4 E00E0F 0 +OP4 E00E10 0 +OP4 E00E11 0 +OP4 E00E12 0 +OP4 E00E13 0 +OP4 E00E14 0 +OP4 E00E15 0 +OP4 E00E16 0 +OP4 E00E17 0 +OP4 E00E18 0 +OP4 E00E19 0 +OP4 E00E1A 0 +OP4 E00E1B 0 +OP4 E00E1C 0 +OP4 E00E1D 0 +OP4 E00E1E 0 +OP4 E00E1F 0 +OP4 E00E20 0 +OP4 E00E21 0 +OP4 E00E22 0 +OP4 E00E23 0 +OP4 E00E24 0 +OP4 E00E25 0 +OP4 E00E26 0 +OP4 E00E27 0 +OP4 E00E28 0 +OP4 E00E29 0 +OP4 E00E2A 0 +OP4 E00E2B 0 +OP4 E00E2C 0 +OP4 E00E2D 0 +OP4 E00E2E 0 +OP4 E00E2F 0 +OP4 E00E30 0 +OP4 E00E31 0 +OP4 E00E32 0 +OP4 E00E33 0 +OP4 E00E34 0 +OP4 E00E35 0 +OP4 E00E36 0 +OP4 E00E37 0 +OP4 E00E38 0 +OP4 E00E39 0 +OP4 E00E3A 0 +OP4 E00E3B 0 +OP4 E00E3C 0 +OP4 E00E3D 0 +OP4 E00E3E 0 +OP4 E00E3F 0 +OP4 E00E40 0 +OP4 E00E41 0 +OP4 E00E42 0 +OP4 E00E43 0 +OP4 E00E44 0 +OP4 E00E45 0 +OP4 E00E46 0 +OP4 E00E47 0 +OP4 E00E48 0 +OP4 E00E49 0 +OP4 E00E4A 0 +OP4 E00E4B 0 +OP4 E00E4C 0 +OP4 E00E4D 0 +OP4 E00E4E 0 +OP4 E00E4F 0 +OP4 E00E50 0 +OP4 E00E51 0 +OP4 E00E52 0 +OP4 E00E53 0 +OP4 E00E54 0 +OP4 E00E55 0 +OP4 E00E56 0 +OP4 E00E57 0 +OP4 E00E58 0 +OP4 E00E59 0 +OP4 E00E5A 0 +OP4 E00E5B 0 +OP4 E00E5C 0 +OP4 E00E5D 0 +OP4 E00E5E 0 +OP4 E00E5F 0 +OP4 E00E60 0 +OP4 E00E61 0 +OP4 E00E62 0 +OP4 E00E63 0 +OP4 E00E64 0 +OP4 E00E65 0 +OP4 E00E66 0 +OP4 E00E67 0 +OP4 E00E68 0 +OP4 E00E69 0 +OP4 E00E6A 0 +OP4 E00E6B 0 +OP4 E00E6C 0 +OP4 E00E6D 0 +OP4 E00E6E 0 +OP4 E00E6F 0 +OP4 E00E70 0 +OP4 E00E71 0 +OP4 E00E72 0 +OP4 E00E73 0 +OP4 E00E74 0 +OP4 E00E75 0 +OP4 E00E76 0 +OP4 E00E77 0 +OP4 E00E78 0 +OP4 E00E79 0 +OP4 E00E7A 0 +OP4 E00E7B 0 +OP4 E00E7C 0 +OP4 E00E7D 0 +OP4 E00E7E 0 +OP4 E00E7F 0 +OP4 E00E80 0 +OP4 E00E81 0 +OP4 E00E82 0 +OP4 E00E83 0 +OP4 E00E84 0 +OP4 E00E85 0 +OP4 E00E86 0 +OP4 E00E87 0 +OP4 E00E88 0 +OP4 E00E89 0 +OP4 E00E8A 0 +OP4 E00E8B 0 +OP4 E00E8C 0 +OP4 E00E8D 0 +OP4 E00E8E 0 +OP4 E00E8F 0 +OP4 E00E90 0 +OP4 E00E91 0 +OP4 E00E92 0 +OP4 E00E93 0 +OP4 E00E94 0 +OP4 E00E95 0 +OP4 E00E96 0 +OP4 E00E97 0 +OP4 E00E98 0 +OP4 E00E99 0 +OP4 E00E9A 0 +OP4 E00E9B 0 +OP4 E00E9C 0 +OP4 E00E9D 0 +OP4 E00E9E 0 +OP4 E00E9F 0 +OP4 E00EA0 0 +OP4 E00EA1 0 +OP4 E00EA2 0 +OP4 E00EA3 0 +OP4 E00EA4 0 +OP4 E00EA5 0 +OP4 E00EA6 0 +OP4 E00EA7 0 +OP4 E00EA8 0 +OP4 E00EA9 0 +OP4 E00EAA 0 +OP4 E00EAB 0 +OP4 E00EAC 0 +OP4 E00EAD 0 +OP4 E00EAE 0 +OP4 E00EAF 0 +OP4 E00EB0 0 +OP4 E00EB1 0 +OP4 E00EB2 0 +OP4 E00EB3 0 +OP4 E00EB4 0 +OP4 E00EB5 0 +OP4 E00EB6 0 +OP4 E00EB7 0 +OP4 E00EB8 0 +OP4 E00EB9 0 +OP4 E00EBA 0 +OP4 E00EBB 0 +OP4 E00EBC 0 +OP4 E00EBD 0 +OP4 E00EBE 0 +OP4 E00EBF 0 +OP4 E00EC0 0 +OP4 E00EC1 0 +OP4 E00EC2 0 +OP4 E00EC3 0 +OP4 E00EC4 0 +OP4 E00EC5 0 +OP4 E00EC6 0 +OP4 E00EC7 0 +OP4 E00EC8 0 +OP4 E00EC9 0 +OP4 E00ECA 0 +OP4 E00ECB 0 +OP4 E00ECC 0 +OP4 E00ECD 0 +OP4 E00ECE 0 +OP4 E00ECF 0 +OP4 E00ED0 0 +OP4 E00ED1 0 +OP4 E00ED2 0 +OP4 E00ED3 0 +OP4 E00ED4 0 +OP4 E00ED5 0 +OP4 E00ED6 0 +OP4 E00ED7 0 +OP4 E00ED8 0 +OP4 E00ED9 0 +OP4 E00EDA 0 +OP4 E00EDB 0 +OP4 E00EDC 0 +OP4 E00EDD 0 +OP4 E00EDE 0 +OP4 E00EDF 0 +OP4 E00EE0 0 +OP4 E00EE1 0 +OP4 E00EE2 0 +OP4 E00EE3 0 +OP4 E00EE4 0 +OP4 E00EE5 0 +OP4 E00EE6 0 +OP4 E00EE7 0 +OP4 E00EE8 0 +OP4 E00EE9 0 +OP4 E00EEA 0 +OP4 E00EEB 0 +OP4 E00EEC 0 +OP4 E00EED 0 +OP4 E00EEE 0 +OP4 E00EEF 0 +OP4 E00EF0 0 +OP4 E00EF1 0 +OP4 E00EF2 0 +OP4 E00EF3 0 +OP4 E00EF4 0 +OP4 E00EF5 0 +OP4 E00EF6 0 +OP4 E00EF7 0 +OP4 E00EF8 0 +OP4 E00EF9 0 +OP4 E00EFA 0 +OP4 E00EFB 0 +OP4 E00EFC 0 +OP4 E00EFD 0 +OP4 E00EFE 0 +OP4 E00EFF 0 +OP4 E00F00 0 +OP4 E00F01 0 +OP4 E00F02 0 +OP4 E00F03 0 +OP4 E00F04 0 +OP4 E00F05 0 +OP4 E00F06 0 +OP4 E00F07 0 +OP4 E00F08 0 +OP4 E00F09 0 +OP4 E00F0A 0 +OP4 E00F0B 0 +OP4 E00F0C 0 +OP4 E00F0D 0 +OP4 E00F0E 0 +OP4 E00F0F 0 +OP4 E00F10 0 +OP4 E00F11 0 +OP4 E00F12 0 +OP4 E00F13 0 +OP4 E00F14 0 +OP4 E00F15 0 +OP4 E00F16 0 +OP4 E00F17 0 +OP4 E00F18 0 +OP4 E00F19 0 +OP4 E00F1A 0 +OP4 E00F1B 0 +OP4 E00F1C 0 +OP4 E00F1D 0 +OP4 E00F1E 0 +OP4 E00F1F 0 +OP4 E00F20 0 +OP4 E00F21 0 +OP4 E00F22 0 +OP4 E00F23 0 +OP4 E00F24 0 +OP4 E00F25 0 +OP4 E00F26 0 +OP4 E00F27 0 +OP4 E00F28 0 +OP4 E00F29 0 +OP4 E00F2A 0 +OP4 E00F2B 0 +OP4 E00F2C 0 +OP4 E00F2D 0 +OP4 E00F2E 0 +OP4 E00F2F 0 +OP4 E00F30 0 +OP4 E00F31 0 +OP4 E00F32 0 +OP4 E00F33 0 +OP4 E00F34 0 +OP4 E00F35 0 +OP4 E00F36 0 +OP4 E00F37 0 +OP4 E00F38 0 +OP4 E00F39 0 +OP4 E00F3A 0 +OP4 E00F3B 0 +OP4 E00F3C 0 +OP4 E00F3D 0 +OP4 E00F3E 0 +OP4 E00F3F 0 +OP4 E00F40 0 +OP4 E00F41 0 +OP4 E00F42 0 +OP4 E00F43 0 +OP4 E00F44 0 +OP4 E00F45 0 +OP4 E00F46 0 +OP4 E00F47 0 +OP4 E00F48 0 +OP4 E00F49 0 +OP4 E00F4A 0 +OP4 E00F4B 0 +OP4 E00F4C 0 +OP4 E00F4D 0 +OP4 E00F4E 0 +OP4 E00F4F 0 +OP4 E00F50 0 +OP4 E00F51 0 +OP4 E00F52 0 +OP4 E00F53 0 +OP4 E00F54 0 +OP4 E00F55 0 +OP4 E00F56 0 +OP4 E00F57 0 +OP4 E00F58 0 +OP4 E00F59 0 +OP4 E00F5A 0 +OP4 E00F5B 0 +OP4 E00F5C 0 +OP4 E00F5D 0 +OP4 E00F5E 0 +OP4 E00F5F 0 +OP4 E00F60 0 +OP4 E00F61 0 +OP4 E00F62 0 +OP4 E00F63 0 +OP4 E00F64 0 +OP4 E00F65 0 +OP4 E00F66 0 +OP4 E00F67 0 +OP4 E00F68 0 +OP4 E00F69 0 +OP4 E00F6A 0 +OP4 E00F6B 0 +OP4 E00F6C 0 +OP4 E00F6D 0 +OP4 E00F6E 0 +OP4 E00F6F 0 +OP4 E00F70 0 +OP4 E00F71 0 +OP4 E00F72 0 +OP4 E00F73 0 +OP4 E00F74 0 +OP4 E00F75 0 +OP4 E00F76 0 +OP4 E00F77 0 +OP4 E00F78 0 +OP4 E00F79 0 +OP4 E00F7A 0 +OP4 E00F7B 0 +OP4 E00F7C 0 +OP4 E00F7D 0 +OP4 E00F7E 0 +OP4 E00F7F 0 +OP4 E00F80 0 +OP4 E00F81 0 +OP4 E00F82 0 +OP4 E00F83 0 +OP4 E00F84 0 +OP4 E00F85 0 +OP4 E00F86 0 +OP4 E00F87 0 +OP4 E00F88 0 +OP4 E00F89 0 +OP4 E00F8A 0 +OP4 E00F8B 0 +OP4 E00F8C 0 +OP4 E00F8D 0 +OP4 E00F8E 0 +OP4 E00F8F 0 +OP4 E00F90 0 +OP4 E00F91 0 +OP4 E00F92 0 +OP4 E00F93 0 +OP4 E00F94 0 +OP4 E00F95 0 +OP4 E00F96 0 +OP4 E00F97 0 +OP4 E00F98 0 +OP4 E00F99 0 +OP4 E00F9A 0 +OP4 E00F9B 0 +OP4 E00F9C 0 +OP4 E00F9D 0 +OP4 E00F9E 0 +OP4 E00F9F 0 +OP4 E00FA0 0 +OP4 E00FA1 0 +OP4 E00FA2 0 +OP4 E00FA3 0 +OP4 E00FA4 0 +OP4 E00FA5 0 +OP4 E00FA6 0 +OP4 E00FA7 0 +OP4 E00FA8 0 +OP4 E00FA9 0 +OP4 E00FAA 0 +OP4 E00FAB 0 +OP4 E00FAC 0 +OP4 E00FAD 0 +OP4 E00FAE 0 +OP4 E00FAF 0 +OP4 E00FB0 0 +OP4 E00FB1 0 +OP4 E00FB2 0 +OP4 E00FB3 0 +OP4 E00FB4 0 +OP4 E00FB5 0 +OP4 E00FB6 0 +OP4 E00FB7 0 +OP4 E00FB8 0 +OP4 E00FB9 0 +OP4 E00FBA 0 +OP4 E00FBB 0 +OP4 E00FBC 0 +OP4 E00FBD 0 +OP4 E00FBE 0 +OP4 E00FBF 0 +OP4 E00FC0 0 +OP4 E00FC1 0 +OP4 E00FC2 0 +OP4 E00FC3 0 +OP4 E00FC4 0 +OP4 E00FC5 0 +OP4 E00FC6 0 +OP4 E00FC7 0 +OP4 E00FC8 0 +OP4 E00FC9 0 +OP4 E00FCA 0 +OP4 E00FCB 0 +OP4 E00FCC 0 +OP4 E00FCD 0 +OP4 E00FCE 0 +OP4 E00FCF 0 +OP4 E00FD0 0 +OP4 E00FD1 0 +OP4 E00FD2 0 +OP4 E00FD3 0 +OP4 E00FD4 0 +OP4 E00FD5 0 +OP4 E00FD6 0 +OP4 E00FD7 0 +OP4 E00FD8 0 +OP4 E00FD9 0 +OP4 E00FDA 0 +OP4 E00FDB 0 +OP4 E00FDC 0 +OP4 E00FDD 0 +OP4 E00FDE 0 +OP4 E00FDF 0 +OP4 E00FE0 0 +OP4 E00FE1 0 +OP4 E00FE2 0 +OP4 E00FE3 0 +OP4 E00FE4 0 +OP4 E00FE5 0 +OP4 E00FE6 0 +OP4 E00FE7 0 +OP4 E00FE8 0 +OP4 E00FE9 0 +OP4 E00FEA 0 +OP4 E00FEB 0 +OP4 E00FEC 0 +OP4 E00FED 0 +OP4 E00FEE 0 +OP4 E00FEF 0 +OP4 E00FF0 0 +OP4 E00FF1 0 +OP4 E00FF2 0 +OP4 E00FF3 0 +OP4 E00FF4 0 +OP4 E00FF5 0 +OP4 E00FF6 0 +OP4 E00FF7 0 +OP4 E00FF8 0 +OP4 E00FF9 0 +OP4 E00FFA 0 +OP4 E00FFB 0 +OP4 E00FFC 0 +OP4 E00FFD 0 +OP4 E00FFE 0 +OP4 E00FFF 0 +OP4 E01000 0 +OP4 E01001 0 +OP4 E01002 0 +OP4 E01003 0 +OP4 E01004 0 +OP4 E01005 0 +OP4 E01006 0 +OP4 E01007 0 +OP4 E01008 0 +OP4 E01009 0 +OP4 E0100A 0 +OP4 E0100B 0 +OP4 E0100C 0 +OP4 E0100D 0 +OP4 E0100E 0 +OP4 E0100F 0 +OP4 E01010 0 +OP4 E01011 0 +OP4 E01012 0 +OP4 E01013 0 +OP4 E01014 0 +OP4 E01015 0 +OP4 E01016 0 +OP4 E01017 0 +OP4 E01018 0 +OP4 E01019 0 +OP4 E0101A 0 +OP4 E0101B 0 +OP4 E0101C 0 +OP4 E0101D 0 +OP4 E0101E 0 +OP4 E0101F 0 +OP4 E01020 0 +OP4 E01021 0 +OP4 E01022 0 +OP4 E01023 0 +OP4 E01024 0 +OP4 E01025 0 +OP4 E01026 0 +OP4 E01027 0 +OP4 E01028 0 +OP4 E01029 0 +OP4 E0102A 0 +OP4 E0102B 0 +OP4 E0102C 0 +OP4 E0102D 0 +OP4 E0102E 0 +OP4 E0102F 0 +OP4 E01030 0 +OP4 E01031 0 +OP4 E01032 0 +OP4 E01033 0 +OP4 E01034 0 +OP4 E01035 0 +OP4 E01036 0 +OP4 E01037 0 +OP4 E01038 0 +OP4 E01039 0 +OP4 E0103A 0 +OP4 E0103B 0 +OP4 E0103C 0 +OP4 E0103D 0 +OP4 E0103E 0 +OP4 E0103F 0 +OP4 E01040 0 +OP4 E01041 0 +OP4 E01042 0 +OP4 E01043 0 +OP4 E01044 0 +OP4 E01045 0 +OP4 E01046 0 +OP4 E01047 0 +OP4 E01048 0 +OP4 E01049 0 +OP4 E0104A 0 +OP4 E0104B 0 +OP4 E0104C 0 +OP4 E0104D 0 +OP4 E0104E 0 +OP4 E0104F 0 +OP4 E01050 0 +OP4 E01051 0 +OP4 E01052 0 +OP4 E01053 0 +OP4 E01054 0 +OP4 E01055 0 +OP4 E01056 0 +OP4 E01057 0 +OP4 E01058 0 +OP4 E01059 0 +OP4 E0105A 0 +OP4 E0105B 0 +OP4 E0105C 0 +OP4 E0105D 0 +OP4 E0105E 0 +OP4 E0105F 0 +OP4 E01060 0 +OP4 E01061 0 +OP4 E01062 0 +OP4 E01063 0 +OP4 E01064 0 +OP4 E01065 0 +OP4 E01066 0 +OP4 E01067 0 +OP4 E01068 0 +OP4 E01069 0 +OP4 E0106A 0 +OP4 E0106B 0 +OP4 E0106C 0 +OP4 E0106D 0 +OP4 E0106E 0 +OP4 E0106F 0 +OP4 E01070 0 +OP4 E01071 0 +OP4 E01072 0 +OP4 E01073 0 +OP4 E01074 0 +OP4 E01075 0 +OP4 E01076 0 +OP4 E01077 0 +OP4 E01078 0 +OP4 E01079 0 +OP4 E0107A 0 +OP4 E0107B 0 +OP4 E0107C 0 +OP4 E0107D 0 +OP4 E0107E 0 +OP4 E0107F 0 +OP4 E01080 0 +OP4 E01081 0 +OP4 E01082 0 +OP4 E01083 0 +OP4 E01084 0 +OP4 E01085 0 +OP4 E01086 0 +OP4 E01087 0 +OP4 E01088 0 +OP4 E01089 0 +OP4 E0108A 0 +OP4 E0108B 0 +OP4 E0108C 0 +OP4 E0108D 0 +OP4 E0108E 0 +OP4 E0108F 0 +OP4 E01090 0 +OP4 E01091 0 +OP4 E01092 0 +OP4 E01093 0 +OP4 E01094 0 +OP4 E01095 0 +OP4 E01096 0 +OP4 E01097 0 +OP4 E01098 0 +OP4 E01099 0 +OP4 E0109A 0 +OP4 E0109B 0 +OP4 E0109C 0 +OP4 E0109D 0 +OP4 E0109E 0 +OP4 E0109F 0 +OP4 E010A0 0 +OP4 E010A1 0 +OP4 E010A2 0 +OP4 E010A3 0 +OP4 E010A4 0 +OP4 E010A5 0 +OP4 E010A6 0 +OP4 E010A7 0 +OP4 E010A8 0 +OP4 E010A9 0 +OP4 E010AA 0 +OP4 E010AB 0 +OP4 E010AC 0 +OP4 E010AD 0 +OP4 E010AE 0 +OP4 E010AF 0 +OP4 E010B0 0 +OP4 E010B1 0 +OP4 E010B2 0 +OP4 E010B3 0 +OP4 E010B4 0 +OP4 E010B5 0 +OP4 E010B6 0 +OP4 E010B7 0 +OP4 E010B8 0 +OP4 E010B9 0 +OP4 E010BA 0 +OP4 E010BB 0 +OP4 E010BC 0 +OP4 E010BD 0 +OP4 E010BE 0 +OP4 E010BF 0 +OP4 E010C0 0 +OP4 E010C1 0 +OP4 E010C2 0 +OP4 E010C3 0 +OP4 E010C4 0 +OP4 E010C5 0 +OP4 E010C6 0 +OP4 E010C7 0 +OP4 E010C8 0 +OP4 E010C9 0 +OP4 E010CA 0 +OP4 E010CB 0 +OP4 E010CC 0 +OP4 E010CD 0 +OP4 E010CE 0 +OP4 E010CF 0 +OP4 E010D0 0 +OP4 E010D1 0 +OP4 E010D2 0 +OP4 E010D3 0 +OP4 E010D4 0 +OP4 E010D5 0 +OP4 E010D6 0 +OP4 E010D7 0 +OP4 E010D8 0 +OP4 E010D9 0 +OP4 E010DA 0 +OP4 E010DB 0 +OP4 E010DC 0 +OP4 E010DD 0 +OP4 E010DE 0 +OP4 E010DF 0 +OP4 E010E0 0 +OP4 E010E1 0 +OP4 E010E2 0 +OP4 E010E3 0 +OP4 E010E4 0 +OP4 E010E5 0 +OP4 E010E6 0 +OP4 E010E7 0 +OP4 E010E8 0 +OP4 E010E9 0 +OP4 E010EA 0 +OP4 E010EB 0 +OP4 E010EC 0 +OP4 E010ED 0 +OP4 E010EE 0 +OP4 E010EF 0 +OP4 E010F0 0 +OP4 E010F1 0 +OP4 E010F2 0 +OP4 E010F3 0 +OP4 E010F4 0 +OP4 E010F5 0 +OP4 E010F6 0 +OP4 E010F7 0 +OP4 E010F8 0 +OP4 E010F9 0 +OP4 E010FA 0 +OP4 E010FB 0 +OP4 E010FC 0 +OP4 E010FD 0 +OP4 E010FE 0 +OP4 E010FF 0 +OP4 E01100 0 +OP4 E01101 0 +OP4 E01102 0 +OP4 E01103 0 +OP4 E01104 0 +OP4 E01105 0 +OP4 E01106 0 +OP4 E01107 0 +OP4 E01108 0 +OP4 E01109 0 +OP4 E0110A 0 +OP4 E0110B 0 +OP4 E0110C 0 +OP4 E0110D 0 +OP4 E0110E 0 +OP4 E0110F 0 +OP4 E01110 0 +OP4 E01111 0 +OP4 E01112 0 +OP4 E01113 0 +OP4 E01114 0 +OP4 E01115 0 +OP4 E01116 0 +OP4 E01117 0 +OP4 E01118 0 +OP4 E01119 0 +OP4 E0111A 0 +OP4 E0111B 0 +OP4 E0111C 0 +OP4 E0111D 0 +OP4 E0111E 0 +OP4 E0111F 0 +OP4 E01120 0 +OP4 E01121 0 +OP4 E01122 0 +OP4 E01123 0 +OP4 E01124 0 +OP4 E01125 0 +OP4 E01126 0 +OP4 E01127 0 +OP4 E01128 0 +OP4 E01129 0 +OP4 E0112A 0 +OP4 E0112B 0 +OP4 E0112C 0 +OP4 E0112D 0 +OP4 E0112E 0 +OP4 E0112F 0 +OP4 E01130 0 +OP4 E01131 0 +OP4 E01132 0 +OP4 E01133 0 +OP4 E01134 0 +OP4 E01135 0 +OP4 E01136 0 +OP4 E01137 0 +OP4 E01138 0 +OP4 E01139 0 +OP4 E0113A 0 +OP4 E0113B 0 +OP4 E0113C 0 +OP4 E0113D 0 +OP4 E0113E 0 +OP4 E0113F 0 +OP4 E01140 0 +OP4 E01141 0 +OP4 E01142 0 +OP4 E01143 0 +OP4 E01144 0 +OP4 E01145 0 +OP4 E01146 0 +OP4 E01147 0 +OP4 E01148 0 +OP4 E01149 0 +OP4 E0114A 0 +OP4 E0114B 0 +OP4 E0114C 0 +OP4 E0114D 0 +OP4 E0114E 0 +OP4 E0114F 0 +OP4 E01150 0 +OP4 E01151 0 +OP4 E01152 0 +OP4 E01153 0 +OP4 E01154 0 +OP4 E01155 0 +OP4 E01156 0 +OP4 E01157 0 +OP4 E01158 0 +OP4 E01159 0 +OP4 E0115A 0 +OP4 E0115B 0 +OP4 E0115C 0 +OP4 E0115D 0 +OP4 E0115E 0 +OP4 E0115F 0 +OP4 E01160 0 +OP4 E01161 0 +OP4 E01162 0 +OP4 E01163 0 +OP4 E01164 0 +OP4 E01165 0 +OP4 E01166 0 +OP4 E01167 0 +OP4 E01168 0 +OP4 E01169 0 +OP4 E0116A 0 +OP4 E0116B 0 +OP4 E0116C 0 +OP4 E0116D 0 +OP4 E0116E 0 +OP4 E0116F 0 +OP4 E01170 0 +OP4 E01171 0 +OP4 E01172 0 +OP4 E01173 0 +OP4 E01174 0 +OP4 E01175 0 +OP4 E01176 0 +OP4 E01177 0 +OP4 E01178 0 +OP4 E01179 0 +OP4 E0117A 0 +OP4 E0117B 0 +OP4 E0117C 0 +OP4 E0117D 0 +OP4 E0117E 0 +OP4 E0117F 0 +OP4 E01180 0 +OP4 E01181 0 +OP4 E01182 0 +OP4 E01183 0 +OP4 E01184 0 +OP4 E01185 0 +OP4 E01186 0 +OP4 E01187 0 +OP4 E01188 0 +OP4 E01189 0 +OP4 E0118A 0 +OP4 E0118B 0 +OP4 E0118C 0 +OP4 E0118D 0 +OP4 E0118E 0 +OP4 E0118F 0 +OP4 E01190 0 +OP4 E01191 0 +OP4 E01192 0 +OP4 E01193 0 +OP4 E01194 0 +OP4 E01195 0 +OP4 E01196 0 +OP4 E01197 0 +OP4 E01198 0 +OP4 E01199 0 +OP4 E0119A 0 +OP4 E0119B 0 +OP4 E0119C 0 +OP4 E0119D 0 +OP4 E0119E 0 +OP4 E0119F 0 +OP4 E011A0 0 +OP4 E011A1 0 +OP4 E011A2 0 +OP4 E011A3 0 +OP4 E011A4 0 +OP4 E011A5 0 +OP4 E011A6 0 +OP4 E011A7 0 +OP4 E011A8 0 +OP4 E011A9 0 +OP4 E011AA 0 +OP4 E011AB 0 +OP4 E011AC 0 +OP4 E011AD 0 +OP4 E011AE 0 +OP4 E011AF 0 +OP4 E011B0 0 +OP4 E011B1 0 +OP4 E011B2 0 +OP4 E011B3 0 +OP4 E011B4 0 +OP4 E011B5 0 +OP4 E011B6 0 +OP4 E011B7 0 +OP4 E011B8 0 +OP4 E011B9 0 +OP4 E011BA 0 +OP4 E011BB 0 +OP4 E011BC 0 +OP4 E011BD 0 +OP4 E011BE 0 +OP4 E011BF 0 +OP4 E011C0 0 +OP4 E011C1 0 +OP4 E011C2 0 +OP4 E011C3 0 +OP4 E011C4 0 +OP4 E011C5 0 +OP4 E011C6 0 +OP4 E011C7 0 +OP4 E011C8 0 +OP4 E011C9 0 +OP4 E011CA 0 +OP4 E011CB 0 +OP4 E011CC 0 +OP4 E011CD 0 +OP4 E011CE 0 +OP4 E011CF 0 +OP4 E011D0 0 +OP4 E011D1 0 +OP4 E011D2 0 +OP4 E011D3 0 +OP4 E011D4 0 +OP4 E011D5 0 +OP4 E011D6 0 +OP4 E011D7 0 +OP4 E011D8 0 +OP4 E011D9 0 +OP4 E011DA 0 +OP4 E011DB 0 +OP4 E011DC 0 +OP4 E011DD 0 +OP4 E011DE 0 +OP4 E011DF 0 +OP4 E011E0 0 +OP4 E011E1 0 +OP4 E011E2 0 +OP4 E011E3 0 +OP4 E011E4 0 +OP4 E011E5 0 +OP4 E011E6 0 +OP4 E011E7 0 +OP4 E011E8 0 +OP4 E011E9 0 +OP4 E011EA 0 +OP4 E011EB 0 +OP4 E011EC 0 +OP4 E011ED 0 +OP4 E011EE 0 +OP4 E011EF 0 +OP4 E011F0 0 +OP4 E011F1 0 +OP4 E011F2 0 +OP4 E011F3 0 +OP4 E011F4 0 +OP4 E011F5 0 +OP4 E011F6 0 +OP4 E011F7 0 +OP4 E011F8 0 +OP4 E011F9 0 +OP4 E011FA 0 +OP4 E011FB 0 +OP4 E011FC 0 +OP4 E011FD 0 +OP4 E011FE 0 +OP4 E011FF 0 +OP4 E01200 0 +OP4 E01201 0 +OP4 E01202 0 +OP4 E01203 0 +OP4 E01204 0 +OP4 E01205 0 +OP4 E01206 0 +OP4 E01207 0 +OP4 E01208 0 +OP4 E01209 0 +OP4 E0120A 0 +OP4 E0120B 0 +OP4 E0120C 0 +OP4 E0120D 0 +OP4 E0120E 0 +OP4 E0120F 0 +OP4 E01210 0 +OP4 E01211 0 +OP4 E01212 0 +OP4 E01213 0 +OP4 E01214 0 +OP4 E01215 0 +OP4 E01216 0 +OP4 E01217 0 +OP4 E01218 0 +OP4 E01219 0 +OP4 E0121A 0 +OP4 E0121B 0 +OP4 E0121C 0 +OP4 E0121D 0 +OP4 E0121E 0 +OP4 E0121F 0 +OP4 E01220 0 +OP4 E01221 0 +OP4 E01222 0 +OP4 E01223 0 +OP4 E01224 0 +OP4 E01225 0 +OP4 E01226 0 +OP4 E01227 0 +OP4 E01228 0 +OP4 E01229 0 +OP4 E0122A 0 +OP4 E0122B 0 +OP4 E0122C 0 +OP4 E0122D 0 +OP4 E0122E 0 +OP4 E0122F 0 +OP4 E01230 0 +OP4 E01231 0 +OP4 E01232 0 +OP4 E01233 0 +OP4 E01234 0 +OP4 E01235 0 +OP4 E01236 0 +OP4 E01237 0 +OP4 E01238 0 +OP4 E01239 0 +OP4 E0123A 0 +OP4 E0123B 0 +OP4 E0123C 0 +OP4 E0123D 0 +OP4 E0123E 0 +OP4 E0123F 0 +OP4 E01240 0 +OP4 E01241 0 +OP4 E01242 0 +OP4 E01243 0 +OP4 E01244 0 +OP4 E01245 0 +OP4 E01246 0 +OP4 E01247 0 +OP4 E01248 0 +OP4 E01249 0 +OP4 E0124A 0 +OP4 E0124B 0 +OP4 E0124C 0 +OP4 E0124D 0 +OP4 E0124E 0 +OP4 E0124F 0 +OP4 E01250 0 +OP4 E01251 0 +OP4 E01252 0 +OP4 E01253 0 +OP4 E01254 0 +OP4 E01255 0 +OP4 E01256 0 +OP4 E01257 0 +OP4 E01258 0 +OP4 E01259 0 +OP4 E0125A 0 +OP4 E0125B 0 +OP4 E0125C 0 +OP4 E0125D 0 +OP4 E0125E 0 +OP4 E0125F 0 +OP4 E01260 0 +OP4 E01261 0 +OP4 E01262 0 +OP4 E01263 0 +OP4 E01264 0 +OP4 E01265 0 +OP4 E01266 0 +OP4 E01267 0 +OP4 E01268 0 +OP4 E01269 0 +OP4 E0126A 0 +OP4 E0126B 0 +OP4 E0126C 0 +OP4 E0126D 0 +OP4 E0126E 0 +OP4 E0126F 0 +OP4 E01270 0 +OP4 E01271 0 +OP4 E01272 0 +OP4 E01273 0 +OP4 E01274 0 +OP4 E01275 0 +OP4 E01276 0 +OP4 E01277 0 +OP4 E01278 0 +OP4 E01279 0 +OP4 E0127A 0 +OP4 E0127B 0 +OP4 E0127C 0 +OP4 E0127D 0 +OP4 E0127E 0 +OP4 E0127F 0 +OP4 E01280 0 +OP4 E01281 0 +OP4 E01282 0 +OP4 E01283 0 +OP4 E01284 0 +OP4 E01285 0 +OP4 E01286 0 +OP4 E01287 0 +OP4 E01288 0 +OP4 E01289 0 +OP4 E0128A 0 +OP4 E0128B 0 +OP4 E0128C 0 +OP4 E0128D 0 +OP4 E0128E 0 +OP4 E0128F 0 +OP4 E01290 0 +OP4 E01291 0 +OP4 E01292 0 +OP4 E01293 0 +OP4 E01294 0 +OP4 E01295 0 +OP4 E01296 0 +OP4 E01297 0 +OP4 E01298 0 +OP4 E01299 0 +OP4 E0129A 0 +OP4 E0129B 0 +OP4 E0129C 0 +OP4 E0129D 0 +OP4 E0129E 0 +OP4 E0129F 0 +OP4 E012A0 0 +OP4 E012A1 0 +OP4 E012A2 0 +OP4 E012A3 0 +OP4 E012A4 0 +OP4 E012A5 0 +OP4 E012A6 0 +OP4 E012A7 0 +OP4 E012A8 0 +OP4 E012A9 0 +OP4 E012AA 0 +OP4 E012AB 0 +OP4 E012AC 0 +OP4 E012AD 0 +OP4 E012AE 0 +OP4 E012AF 0 +OP4 E012B0 0 +OP4 E012B1 0 +OP4 E012B2 0 +OP4 E012B3 0 +OP4 E012B4 0 +OP4 E012B5 0 +OP4 E012B6 0 +OP4 E012B7 0 +OP4 E012B8 0 +OP4 E012B9 0 +OP4 E012BA 0 +OP4 E012BB 0 +OP4 E012BC 0 +OP4 E012BD 0 +OP4 E012BE 0 +OP4 E012BF 0 +OP4 E012C0 0 +OP4 E012C1 0 +OP4 E012C2 0 +OP4 E012C3 0 +OP4 E012C4 0 +OP4 E012C5 0 +OP4 E012C6 0 +OP4 E012C7 0 +OP4 E012C8 0 +OP4 E012C9 0 +OP4 E012CA 0 +OP4 E012CB 0 +OP4 E012CC 0 +OP4 E012CD 0 +OP4 E012CE 0 +OP4 E012CF 0 +OP4 E012D0 0 +OP4 E012D1 0 +OP4 E012D2 0 +OP4 E012D3 0 +OP4 E012D4 0 +OP4 E012D5 0 +OP4 E012D6 0 +OP4 E012D7 0 +OP4 E012D8 0 +OP4 E012D9 0 +OP4 E012DA 0 +OP4 E012DB 0 +OP4 E012DC 0 +OP4 E012DD 0 +OP4 E012DE 0 +OP4 E012DF 0 +OP4 E012E0 0 +OP4 E012E1 0 +OP4 E012E2 0 +OP4 E012E3 0 +OP4 E012E4 0 +OP4 E012E5 0 +OP4 E012E6 0 +OP4 E012E7 0 +OP4 E012E8 0 +OP4 E012E9 0 +OP4 E012EA 0 +OP4 E012EB 0 +OP4 E012EC 0 +OP4 E012ED 0 +OP4 E012EE 0 +OP4 E012EF 0 +OP4 E012F0 0 +OP4 E012F1 0 +OP4 E012F2 0 +OP4 E012F3 0 +OP4 E012F4 0 +OP4 E012F5 0 +OP4 E012F6 0 +OP4 E012F7 0 +OP4 E012F8 0 +OP4 E012F9 0 +OP4 E012FA 0 +OP4 E012FB 0 +OP4 E012FC 0 +OP4 E012FD 0 +OP4 E012FE 0 +OP4 E012FF 0 +OP4 E01300 0 +OP4 E01301 0 +OP4 E01302 0 +OP4 E01303 0 +OP4 E01304 0 +OP4 E01305 0 +OP4 E01306 0 +OP4 E01307 0 +OP4 E01308 0 +OP4 E01309 0 +OP4 E0130A 0 +OP4 E0130B 0 +OP4 E0130C 0 +OP4 E0130D 0 +OP4 E0130E 0 +OP4 E0130F 0 +OP4 E01310 0 +OP4 E01311 0 +OP4 E01312 0 +OP4 E01313 0 +OP4 E01314 0 +OP4 E01315 0 +OP4 E01316 0 +OP4 E01317 0 +OP4 E01318 0 +OP4 E01319 0 +OP4 E0131A 0 +OP4 E0131B 0 +OP4 E0131C 0 +OP4 E0131D 0 +OP4 E0131E 0 +OP4 E0131F 0 +OP4 E01320 0 +OP4 E01321 0 +OP4 E01322 0 +OP4 E01323 0 +OP4 E01324 0 +OP4 E01325 0 +OP4 E01326 0 +OP4 E01327 0 +OP4 E01328 0 +OP4 E01329 0 +OP4 E0132A 0 +OP4 E0132B 0 +OP4 E0132C 0 +OP4 E0132D 0 +OP4 E0132E 0 +OP4 E0132F 0 +OP4 E01330 0 +OP4 E01331 0 +OP4 E01332 0 +OP4 E01333 0 +OP4 E01334 0 +OP4 E01335 0 +OP4 E01336 0 +OP4 E01337 0 +OP4 E01338 0 +OP4 E01339 0 +OP4 E0133A 0 +OP4 E0133B 0 +OP4 E0133C 0 +OP4 E0133D 0 +OP4 E0133E 0 +OP4 E0133F 0 +OP4 E01340 0 +OP4 E01341 0 +OP4 E01342 0 +OP4 E01343 0 +OP4 E01344 0 +OP4 E01345 0 +OP4 E01346 0 +OP4 E01347 0 +OP4 E01348 0 +OP4 E01349 0 +OP4 E0134A 0 +OP4 E0134B 0 +OP4 E0134C 0 +OP4 E0134D 0 +OP4 E0134E 0 +OP4 E0134F 0 +OP4 E01350 0 +OP4 E01351 0 +OP4 E01352 0 +OP4 E01353 0 +OP4 E01354 0 +OP4 E01355 0 +OP4 E01356 0 +OP4 E01357 0 +OP4 E01358 0 +OP4 E01359 0 +OP4 E0135A 0 +OP4 E0135B 0 +OP4 E0135C 0 +OP4 E0135D 0 +OP4 E0135E 0 +OP4 E0135F 0 +OP4 E01360 0 +OP4 E01361 0 +OP4 E01362 0 +OP4 E01363 0 +OP4 E01364 0 +OP4 E01365 0 +OP4 E01366 0 +OP4 E01367 0 +OP4 E01368 0 +OP4 E01369 0 +OP4 E0136A 0 +OP4 E0136B 0 +OP4 E0136C 0 +OP4 E0136D 0 +OP4 E0136E 0 +OP4 E0136F 0 +OP4 E01370 0 +OP4 E01371 0 +OP4 E01372 0 +OP4 E01373 0 +OP4 E01374 0 +OP4 E01375 0 +OP4 E01376 0 +OP4 E01377 0 +OP4 E01378 0 +OP4 E01379 0 +OP4 E0137A 0 +OP4 E0137B 0 +OP4 E0137C 0 +OP4 E0137D 0 +OP4 E0137E 0 +OP4 E0137F 0 +OP4 E01380 0 +OP4 E01381 0 +OP4 E01382 0 +OP4 E01383 0 +OP4 E01384 0 +OP4 E01385 0 +OP4 E01386 0 +OP4 E01387 0 +OP4 E01388 0 +OP4 E01389 0 +OP4 E0138A 0 +OP4 E0138B 0 +OP4 E0138C 0 +OP4 E0138D 0 +OP4 E0138E 0 +OP4 E0138F 0 +OP4 E01390 0 +OP4 E01391 0 +OP4 E01392 0 +OP4 E01393 0 +OP4 E01394 0 +OP4 E01395 0 +OP4 E01396 0 +OP4 E01397 0 +OP4 E01398 0 +OP4 E01399 0 +OP4 E0139A 0 +OP4 E0139B 0 +OP4 E0139C 0 +OP4 E0139D 0 +OP4 E0139E 0 +OP4 E0139F 0 +OP4 E013A0 0 +OP4 E013A1 0 +OP4 E013A2 0 +OP4 E013A3 0 +OP4 E013A4 0 +OP4 E013A5 0 +OP4 E013A6 0 +OP4 E013A7 0 +OP4 E013A8 0 +OP4 E013A9 0 +OP4 E013AA 0 +OP4 E013AB 0 +OP4 E013AC 0 +OP4 E013AD 0 +OP4 E013AE 0 +OP4 E013AF 0 +OP4 E013B0 0 +OP4 E013B1 0 +OP4 E013B2 0 +OP4 E013B3 0 +OP4 E013B4 0 +OP4 E013B5 0 +OP4 E013B6 0 +OP4 E013B7 0 +OP4 E013B8 0 +OP4 E013B9 0 +OP4 E013BA 0 +OP4 E013BB 0 +OP4 E013BC 0 +OP4 E013BD 0 +OP4 E013BE 0 +OP4 E013BF 0 +OP4 E013C0 0 +OP4 E013C1 0 +OP4 E013C2 0 +OP4 E013C3 0 +OP4 E013C4 0 +OP4 E013C5 0 +OP4 E013C6 0 +OP4 E013C7 0 +OP4 E013C8 0 +OP4 E013C9 0 +OP4 E013CA 0 +OP4 E013CB 0 +OP4 E013CC 0 +OP4 E013CD 0 +OP4 E013CE 0 +OP4 E013CF 0 +OP4 E013D0 0 +OP4 E013D1 0 +OP4 E013D2 0 +OP4 E013D3 0 +OP4 E013D4 0 +OP4 E013D5 0 +OP4 E013D6 0 +OP4 E013D7 0 +OP4 E013D8 0 +OP4 E013D9 0 +OP4 E013DA 0 +OP4 E013DB 0 +OP4 E013DC 0 +OP4 E013DD 0 +OP4 E013DE 0 +OP4 E013DF 0 +OP4 E013E0 0 +OP4 E013E1 0 +OP4 E013E2 0 +OP4 E013E3 0 +OP4 E013E4 0 +OP4 E013E5 0 +OP4 E013E6 0 +OP4 E013E7 0 +OP4 E013E8 0 +OP4 E013E9 0 +OP4 E013EA 0 +OP4 E013EB 0 +OP4 E013EC 0 +OP4 E013ED 0 +OP4 E013EE 0 +OP4 E013EF 0 +OP4 E013F0 0 +OP4 E013F1 0 +OP4 E013F2 0 +OP4 E013F3 0 +OP4 E013F4 0 +OP4 E013F5 0 +OP4 E013F6 0 +OP4 E013F7 0 +OP4 E013F8 0 +OP4 E013F9 0 +OP4 E013FA 0 +OP4 E013FB 0 +OP4 E013FC 0 +OP4 E013FD 0 +OP4 E013FE 0 +OP4 E013FF 0 +OP4 E01400 0 +OP4 E01401 0 +OP4 E01402 0 +OP4 E01403 0 +OP4 E01404 0 +OP4 E01405 0 +OP4 E01406 0 +OP4 E01407 0 +OP4 E01408 0 +OP4 E01409 0 +OP4 E0140A 0 +OP4 E0140B 0 +OP4 E0140C 0 +OP4 E0140D 0 +OP4 E0140E 0 +OP4 E0140F 0 +OP4 E01410 0 +OP4 E01411 0 +OP4 E01412 0 +OP4 E01413 0 +OP4 E01414 0 +OP4 E01415 0 +OP4 E01416 0 +OP4 E01417 0 +OP4 E01418 0 +OP4 E01419 0 +OP4 E0141A 0 +OP4 E0141B 0 +OP4 E0141C 0 +OP4 E0141D 0 +OP4 E0141E 0 +OP4 E0141F 0 +OP4 E01420 0 +OP4 E01421 0 +OP4 E01422 0 +OP4 E01423 0 +OP4 E01424 0 +OP4 E01425 0 +OP4 E01426 0 +OP4 E01427 0 +OP4 E01428 0 +OP4 E01429 0 +OP4 E0142A 0 +OP4 E0142B 0 +OP4 E0142C 0 +OP4 E0142D 0 +OP4 E0142E 0 +OP4 E0142F 0 +OP4 E01430 0 +OP4 E01431 0 +OP4 E01432 0 +OP4 E01433 0 +OP4 E01434 0 +OP4 E01435 0 +OP4 E01436 0 +OP4 E01437 0 +OP4 E01438 0 +OP4 E01439 0 +OP4 E0143A 0 +OP4 E0143B 0 +OP4 E0143C 0 +OP4 E0143D 0 +OP4 E0143E 0 +OP4 E0143F 0 +OP4 E01440 0 +OP4 E01441 0 +OP4 E01442 0 +OP4 E01443 0 +OP4 E01444 0 +OP4 E01445 0 +OP4 E01446 0 +OP4 E01447 0 +OP4 E01448 0 +OP4 E01449 0 +OP4 E0144A 0 +OP4 E0144B 0 +OP4 E0144C 0 +OP4 E0144D 0 +OP4 E0144E 0 +OP4 E0144F 0 +OP4 E01450 0 +OP4 E01451 0 +OP4 E01452 0 +OP4 E01453 0 +OP4 E01454 0 +OP4 E01455 0 +OP4 E01456 0 +OP4 E01457 0 +OP4 E01458 0 +OP4 E01459 0 +OP4 E0145A 0 +OP4 E0145B 0 +OP4 E0145C 0 +OP4 E0145D 0 +OP4 E0145E 0 +OP4 E0145F 0 +OP4 E01460 0 +OP4 E01461 0 +OP4 E01462 0 +OP4 E01463 0 +OP4 E01464 0 +OP4 E01465 0 +OP4 E01466 0 +OP4 E01467 0 +OP4 E01468 0 +OP4 E01469 0 +OP4 E0146A 0 +OP4 E0146B 0 +OP4 E0146C 0 +OP4 E0146D 0 +OP4 E0146E 0 +OP4 E0146F 0 +OP4 E01470 0 +OP4 E01471 0 +OP4 E01472 0 +OP4 E01473 0 +OP4 E01474 0 +OP4 E01475 0 +OP4 E01476 0 +OP4 E01477 0 +OP4 E01478 0 +OP4 E01479 0 +OP4 E0147A 0 +OP4 E0147B 0 +OP4 E0147C 0 +OP4 E0147D 0 +OP4 E0147E 0 +OP4 E0147F 0 +OP4 E01480 0 +OP4 E01481 0 +OP4 E01482 0 +OP4 E01483 0 +OP4 E01484 0 +OP4 E01485 0 +OP4 E01486 0 +OP4 E01487 0 +OP4 E01488 0 +OP4 E01489 0 +OP4 E0148A 0 +OP4 E0148B 0 +OP4 E0148C 0 +OP4 E0148D 0 +OP4 E0148E 0 +OP4 E0148F 0 +OP4 E01490 0 +OP4 E01491 0 +OP4 E01492 0 +OP4 E01493 0 +OP4 E01494 0 +OP4 E01495 0 +OP4 E01496 0 +OP4 E01497 0 +OP4 E01498 0 +OP4 E01499 0 +OP4 E0149A 0 +OP4 E0149B 0 +OP4 E0149C 0 +OP4 E0149D 0 +OP4 E0149E 0 +OP4 E0149F 0 +OP4 E014A0 0 +OP4 E014A1 0 +OP4 E014A2 0 +OP4 E014A3 0 +OP4 E014A4 0 +OP4 E014A5 0 +OP4 E014A6 0 +OP4 E014A7 0 +OP4 E014A8 0 +OP4 E014A9 0 +OP4 E014AA 0 +OP4 E014AB 0 +OP4 E014AC 0 +OP4 E014AD 0 +OP4 E014AE 0 +OP4 E014AF 0 +OP4 E014B0 0 +OP4 E014B1 0 +OP4 E014B2 0 +OP4 E014B3 0 +OP4 E014B4 0 +OP4 E014B5 0 +OP4 E014B6 0 +OP4 E014B7 0 +OP4 E014B8 0 +OP4 E014B9 0 +OP4 E014BA 0 +OP4 E014BB 0 +OP4 E014BC 0 +OP4 E014BD 0 +OP4 E014BE 0 +OP4 E014BF 0 +OP4 E014C0 0 +OP4 E014C1 0 +OP4 E014C2 0 +OP4 E014C3 0 +OP4 E014C4 0 +OP4 E014C5 0 +OP4 E014C6 0 +OP4 E014C7 0 +OP4 E014C8 0 +OP4 E014C9 0 +OP4 E014CA 0 +OP4 E014CB 0 +OP4 E014CC 0 +OP4 E014CD 0 +OP4 E014CE 0 +OP4 E014CF 0 +OP4 E014D0 0 +OP4 E014D1 0 +OP4 E014D2 0 +OP4 E014D3 0 +OP4 E014D4 0 +OP4 E014D5 0 +OP4 E014D6 0 +OP4 E014D7 0 +OP4 E014D8 0 +OP4 E014D9 0 +OP4 E014DA 0 +OP4 E014DB 0 +OP4 E014DC 0 +OP4 E014DD 0 +OP4 E014DE 0 +OP4 E014DF 0 +OP4 E014E0 0 +OP4 E014E1 0 +OP4 E014E2 0 +OP4 E014E3 0 +OP4 E014E4 0 +OP4 E014E5 0 +OP4 E014E6 0 +OP4 E014E7 0 +OP4 E014E8 0 +OP4 E014E9 0 +OP4 E014EA 0 +OP4 E014EB 0 +OP4 E014EC 0 +OP4 E014ED 0 +OP4 E014EE 0 +OP4 E014EF 0 +OP4 E014F0 0 +OP4 E014F1 0 +OP4 E014F2 0 +OP4 E014F3 0 +OP4 E014F4 0 +OP4 E014F5 0 +OP4 E014F6 0 +OP4 E014F7 0 +OP4 E014F8 0 +OP4 E014F9 0 +OP4 E014FA 0 +OP4 E014FB 0 +OP4 E014FC 0 +OP4 E014FD 0 +OP4 E014FE 0 +OP4 E014FF 0 +OP4 E01500 0 +OP4 E01501 0 +OP4 E01502 0 +OP4 E01503 0 +OP4 E01504 0 +OP4 E01505 0 +OP4 E01506 0 +OP4 E01507 0 +OP4 E01508 0 +OP4 E01509 0 +OP4 E0150A 0 +OP4 E0150B 0 +OP4 E0150C 0 +OP4 E0150D 0 +OP4 E0150E 0 +OP4 E0150F 0 +OP4 E01510 0 +OP4 E01511 0 +OP4 E01512 0 +OP4 E01513 0 +OP4 E01514 0 +OP4 E01515 0 +OP4 E01516 0 +OP4 E01517 0 +OP4 E01518 0 +OP4 E01519 0 +OP4 E0151A 0 +OP4 E0151B 0 +OP4 E0151C 0 +OP4 E0151D 0 +OP4 E0151E 0 +OP4 E0151F 0 +OP4 E01520 0 +OP4 E01521 0 +OP4 E01522 0 +OP4 E01523 0 +OP4 E01524 0 +OP4 E01525 0 +OP4 E01526 0 +OP4 E01527 0 +OP4 E01528 0 +OP4 E01529 0 +OP4 E0152A 0 +OP4 E0152B 0 +OP4 E0152C 0 +OP4 E0152D 0 +OP4 E0152E 0 +OP4 E0152F 0 +OP4 E01530 0 +OP4 E01531 0 +OP4 E01532 0 +OP4 E01533 0 +OP4 E01534 0 +OP4 E01535 0 +OP4 E01536 0 +OP4 E01537 0 +OP4 E01538 0 +OP4 E01539 0 +OP4 E0153A 0 +OP4 E0153B 0 +OP4 E0153C 0 +OP4 E0153D 0 +OP4 E0153E 0 +OP4 E0153F 0 +OP4 E01540 0 +OP4 E01541 0 +OP4 E01542 0 +OP4 E01543 0 +OP4 E01544 0 +OP4 E01545 0 +OP4 E01546 0 +OP4 E01547 0 +OP4 E01548 0 +OP4 E01549 0 +OP4 E0154A 0 +OP4 E0154B 0 +OP4 E0154C 0 +OP4 E0154D 0 +OP4 E0154E 0 +OP4 E0154F 0 +OP4 E01550 0 +OP4 E01551 0 +OP4 E01552 0 +OP4 E01553 0 +OP4 E01554 0 +OP4 E01555 0 +OP4 E01556 0 +OP4 E01557 0 +OP4 E01558 0 +OP4 E01559 0 +OP4 E0155A 0 +OP4 E0155B 0 +OP4 E0155C 0 +OP4 E0155D 0 +OP4 E0155E 0 +OP4 E0155F 0 +OP4 E01560 0 +OP4 E01561 0 +OP4 E01562 0 +OP4 E01563 0 +OP4 E01564 0 +OP4 E01565 0 +OP4 E01566 0 +OP4 E01567 0 +OP4 E01568 0 +OP4 E01569 0 +OP4 E0156A 0 +OP4 E0156B 0 +OP4 E0156C 0 +OP4 E0156D 0 +OP4 E0156E 0 +OP4 E0156F 0 +OP4 E01570 0 +OP4 E01571 0 +OP4 E01572 0 +OP4 E01573 0 +OP4 E01574 0 +OP4 E01575 0 +OP4 E01576 0 +OP4 E01577 0 +OP4 E01578 0 +OP4 E01579 0 +OP4 E0157A 0 +OP4 E0157B 0 +OP4 E0157C 0 +OP4 E0157D 0 +OP4 E0157E 0 +OP4 E0157F 0 +OP4 E01580 0 +OP4 E01581 0 +OP4 E01582 0 +OP4 E01583 0 +OP4 E01584 0 +OP4 E01585 0 +OP4 E01586 0 +OP4 E01587 0 +OP4 E01588 0 +OP4 E01589 0 +OP4 E0158A 0 +OP4 E0158B 0 +OP4 E0158C 0 +OP4 E0158D 0 +OP4 E0158E 0 +OP4 E0158F 0 +OP4 E01590 0 +OP4 E01591 0 +OP4 E01592 0 +OP4 E01593 0 +OP4 E01594 0 +OP4 E01595 0 +OP4 E01596 0 +OP4 E01597 0 +OP4 E01598 0 +OP4 E01599 0 +OP4 E0159A 0 +OP4 E0159B 0 +OP4 E0159C 0 +OP4 E0159D 0 +OP4 E0159E 0 +OP4 E0159F 0 +OP4 E015A0 0 +OP4 E015A1 0 +OP4 E015A2 0 +OP4 E015A3 0 +OP4 E015A4 0 +OP4 E015A5 0 +OP4 E015A6 0 +OP4 E015A7 0 +OP4 E015A8 0 +OP4 E015A9 0 +OP4 E015AA 0 +OP4 E015AB 0 +OP4 E015AC 0 +OP4 E015AD 0 +OP4 E015AE 0 +OP4 E015AF 0 +OP4 E015B0 0 +OP4 E015B1 0 +OP4 E015B2 0 +OP4 E015B3 0 +OP4 E015B4 0 +OP4 E015B5 0 +OP4 E015B6 0 +OP4 E015B7 0 +OP4 E015B8 0 +OP4 E015B9 0 +OP4 E015BA 0 +OP4 E015BB 0 +OP4 E015BC 0 +OP4 E015BD 0 +OP4 E015BE 0 +OP4 E015BF 0 +OP4 E015C0 0 +OP4 E015C1 0 +OP4 E015C2 0 +OP4 E015C3 0 +OP4 E015C4 0 +OP4 E015C5 0 +OP4 E015C6 0 +OP4 E015C7 0 +OP4 E015C8 0 +OP4 E015C9 0 +OP4 E015CA 0 +OP4 E015CB 0 +OP4 E015CC 0 +OP4 E015CD 0 +OP4 E015CE 0 +OP4 E015CF 0 +OP4 E015D0 0 +OP4 E015D1 0 +OP4 E015D2 0 +OP4 E015D3 0 +OP4 E015D4 0 +OP4 E015D5 0 +OP4 E015D6 0 +OP4 E015D7 0 +OP4 E015D8 0 +OP4 E015D9 0 +OP4 E015DA 0 +OP4 E015DB 0 +OP4 E015DC 0 +OP4 E015DD 0 +OP4 E015DE 0 +OP4 E015DF 0 +OP4 E015E0 0 +OP4 E015E1 0 +OP4 E015E2 0 +OP4 E015E3 0 +OP4 E015E4 0 +OP4 E015E5 0 +OP4 E015E6 0 +OP4 E015E7 0 +OP4 E015E8 0 +OP4 E015E9 0 +OP4 E015EA 0 +OP4 E015EB 0 +OP4 E015EC 0 +OP4 E015ED 0 +OP4 E015EE 0 +OP4 E015EF 0 +OP4 E015F0 0 +OP4 E015F1 0 +OP4 E015F2 0 +OP4 E015F3 0 +OP4 E015F4 0 +OP4 E015F5 0 +OP4 E015F6 0 +OP4 E015F7 0 +OP4 E015F8 0 +OP4 E015F9 0 +OP4 E015FA 0 +OP4 E015FB 0 +OP4 E015FC 0 +OP4 E015FD 0 +OP4 E015FE 0 +OP4 E015FF 0 +OP4 E01600 0 +OP4 E01601 0 +OP4 E01602 0 +OP4 E01603 0 +OP4 E01604 0 +OP4 E01605 0 +OP4 E01606 0 +OP4 E01607 0 +OP4 E01608 0 +OP4 E01609 0 +OP4 E0160A 0 +OP4 E0160B 0 +OP4 E0160C 0 +OP4 E0160D 0 +OP4 E0160E 0 +OP4 E0160F 0 +OP4 E01610 0 +OP4 E01611 0 +OP4 E01612 0 +OP4 E01613 0 +OP4 E01614 0 +OP4 E01615 0 +OP4 E01616 0 +OP4 E01617 0 +OP4 E01618 0 +OP4 E01619 0 +OP4 E0161A 0 +OP4 E0161B 0 +OP4 E0161C 0 +OP4 E0161D 0 +OP4 E0161E 0 +OP4 E0161F 0 +OP4 E01620 0 +OP4 E01621 0 +OP4 E01622 0 +OP4 E01623 0 +OP4 E01624 0 +OP4 E01625 0 +OP4 E01626 0 +OP4 E01627 0 +OP4 E01628 0 +OP4 E01629 0 +OP4 E0162A 0 +OP4 E0162B 0 +OP4 E0162C 0 +OP4 E0162D 0 +OP4 E0162E 0 +OP4 E0162F 0 +OP4 E01630 0 +OP4 E01631 0 +OP4 E01632 0 +OP4 E01633 0 +OP4 E01634 0 +OP4 E01635 0 +OP4 E01636 0 +OP4 E01637 0 +OP4 E01638 0 +OP4 E01639 0 +OP4 E0163A 0 +OP4 E0163B 0 +OP4 E0163C 0 +OP4 E0163D 0 +OP4 E0163E 0 +OP4 E0163F 0 +OP4 E01640 0 +OP4 E01641 0 +OP4 E01642 0 +OP4 E01643 0 +OP4 E01644 0 +OP4 E01645 0 +OP4 E01646 0 +OP4 E01647 0 +OP4 E01648 0 +OP4 E01649 0 +OP4 E0164A 0 +OP4 E0164B 0 +OP4 E0164C 0 +OP4 E0164D 0 +OP4 E0164E 0 +OP4 E0164F 0 +OP4 E01650 0 +OP4 E01651 0 +OP4 E01652 0 +OP4 E01653 0 +OP4 E01654 0 +OP4 E01655 0 +OP4 E01656 0 +OP4 E01657 0 +OP4 E01658 0 +OP4 E01659 0 +OP4 E0165A 0 +OP4 E0165B 0 +OP4 E0165C 0 +OP4 E0165D 0 +OP4 E0165E 0 +OP4 E0165F 0 +OP4 E01660 0 +OP4 E01661 0 +OP4 E01662 0 +OP4 E01663 0 +OP4 E01664 0 +OP4 E01665 0 +OP4 E01666 0 +OP4 E01667 0 +OP4 E01668 0 +OP4 E01669 0 +OP4 E0166A 0 +OP4 E0166B 0 +OP4 E0166C 0 +OP4 E0166D 0 +OP4 E0166E 0 +OP4 E0166F 0 +OP4 E01670 0 +OP4 E01671 0 +OP4 E01672 0 +OP4 E01673 0 +OP4 E01674 0 +OP4 E01675 0 +OP4 E01676 0 +OP4 E01677 0 +OP4 E01678 0 +OP4 E01679 0 +OP4 E0167A 0 +OP4 E0167B 0 +OP4 E0167C 0 +OP4 E0167D 0 +OP4 E0167E 0 +OP4 E0167F 0 +OP4 E01680 0 +OP4 E01681 0 +OP4 E01682 0 +OP4 E01683 0 +OP4 E01684 0 +OP4 E01685 0 +OP4 E01686 0 +OP4 E01687 0 +OP4 E01688 0 +OP4 E01689 0 +OP4 E0168A 0 +OP4 E0168B 0 +OP4 E0168C 0 +OP4 E0168D 0 +OP4 E0168E 0 +OP4 E0168F 0 +OP4 E01690 0 +OP4 E01691 0 +OP4 E01692 0 +OP4 E01693 0 +OP4 E01694 0 +OP4 E01695 0 +OP4 E01696 0 +OP4 E01697 0 +OP4 E01698 0 +OP4 E01699 0 +OP4 E0169A 0 +OP4 E0169B 0 +OP4 E0169C 0 +OP4 E0169D 0 +OP4 E0169E 0 +OP4 E0169F 0 +OP4 E016A0 0 +OP4 E016A1 0 +OP4 E016A2 0 +OP4 E016A3 0 +OP4 E016A4 0 +OP4 E016A5 0 +OP4 E016A6 0 +OP4 E016A7 0 +OP4 E016A8 0 +OP4 E016A9 0 +OP4 E016AA 0 +OP4 E016AB 0 +OP4 E016AC 0 +OP4 E016AD 0 +OP4 E016AE 0 +OP4 E016AF 0 +OP4 E016B0 0 +OP4 E016B1 0 +OP4 E016B2 0 +OP4 E016B3 0 +OP4 E016B4 0 +OP4 E016B5 0 +OP4 E016B6 0 +OP4 E016B7 0 +OP4 E016B8 0 +OP4 E016B9 0 +OP4 E016BA 0 +OP4 E016BB 0 +OP4 E016BC 0 +OP4 E016BD 0 +OP4 E016BE 0 +OP4 E016BF 0 +OP4 E016C0 0 +OP4 E016C1 0 +OP4 E016C2 0 +OP4 E016C3 0 +OP4 E016C4 0 +OP4 E016C5 0 +OP4 E016C6 0 +OP4 E016C7 0 +OP4 E016C8 0 +OP4 E016C9 0 +OP4 E016CA 0 +OP4 E016CB 0 +OP4 E016CC 0 +OP4 E016CD 0 +OP4 E016CE 0 +OP4 E016CF 0 +OP4 E016D0 0 +OP4 E016D1 0 +OP4 E016D2 0 +OP4 E016D3 0 +OP4 E016D4 0 +OP4 E016D5 0 +OP4 E016D6 0 +OP4 E016D7 0 +OP4 E016D8 0 +OP4 E016D9 0 +OP4 E016DA 0 +OP4 E016DB 0 +OP4 E016DC 0 +OP4 E016DD 0 +OP4 E016DE 0 +OP4 E016DF 0 +OP4 E016E0 0 +OP4 E016E1 0 +OP4 E016E2 0 +OP4 E016E3 0 +OP4 E016E4 0 +OP4 E016E5 0 +OP4 E016E6 0 +OP4 E016E7 0 +OP4 E016E8 0 +OP4 E016E9 0 +OP4 E016EA 0 +OP4 E016EB 0 +OP4 E016EC 0 +OP4 E016ED 0 +OP4 E016EE 0 +OP4 E016EF 0 +OP4 E016F0 0 +OP4 E016F1 0 +OP4 E016F2 0 +OP4 E016F3 0 +OP4 E016F4 0 +OP4 E016F5 0 +OP4 E016F6 0 +OP4 E016F7 0 +OP4 E016F8 0 +OP4 E016F9 0 +OP4 E016FA 0 +OP4 E016FB 0 +OP4 E016FC 0 +OP4 E016FD 0 +OP4 E016FE 0 +OP4 E016FF 0 +OP4 E01700 0 +OP4 E01701 0 +OP4 E01702 0 +OP4 E01703 0 +OP4 E01704 0 +OP4 E01705 0 +OP4 E01706 0 +OP4 E01707 0 +OP4 E01708 0 +OP4 E01709 0 +OP4 E0170A 0 +OP4 E0170B 0 +OP4 E0170C 0 +OP4 E0170D 0 +OP4 E0170E 0 +OP4 E0170F 0 +OP4 E01710 0 +OP4 E01711 0 +OP4 E01712 0 +OP4 E01713 0 +OP4 E01714 0 +OP4 E01715 0 +OP4 E01716 0 +OP4 E01717 0 +OP4 E01718 0 +OP4 E01719 0 +OP4 E0171A 0 +OP4 E0171B 0 +OP4 E0171C 0 +OP4 E0171D 0 +OP4 E0171E 0 +OP4 E0171F 0 +OP4 E01720 0 +OP4 E01721 0 +OP4 E01722 0 +OP4 E01723 0 +OP4 E01724 0 +OP4 E01725 0 +OP4 E01726 0 +OP4 E01727 0 +OP4 E01728 0 +OP4 E01729 0 +OP4 E0172A 0 +OP4 E0172B 0 +OP4 E0172C 0 +OP4 E0172D 0 +OP4 E0172E 0 +OP4 E0172F 0 +OP4 E01730 0 +OP4 E01731 0 +OP4 E01732 0 +OP4 E01733 0 +OP4 E01734 0 +OP4 E01735 0 +OP4 E01736 0 +OP4 E01737 0 +OP4 E01738 0 +OP4 E01739 0 +OP4 E0173A 0 +OP4 E0173B 0 +OP4 E0173C 0 +OP4 E0173D 0 +OP4 E0173E 0 +OP4 E0173F 0 +OP4 E01740 0 +OP4 E01741 0 +OP4 E01742 0 +OP4 E01743 0 +OP4 E01744 0 +OP4 E01745 0 +OP4 E01746 0 +OP4 E01747 0 +OP4 E01748 0 +OP4 E01749 0 +OP4 E0174A 0 +OP4 E0174B 0 +OP4 E0174C 0 +OP4 E0174D 0 +OP4 E0174E 0 +OP4 E0174F 0 +OP4 E01750 0 +OP4 E01751 0 +OP4 E01752 0 +OP4 E01753 0 +OP4 E01754 0 +OP4 E01755 0 +OP4 E01756 0 +OP4 E01757 0 +OP4 E01758 0 +OP4 E01759 0 +OP4 E0175A 0 +OP4 E0175B 0 +OP4 E0175C 0 +OP4 E0175D 0 +OP4 E0175E 0 +OP4 E0175F 0 +OP4 E01760 0 +OP4 E01761 0 +OP4 E01762 0 +OP4 E01763 0 +OP4 E01764 0 +OP4 E01765 0 +OP4 E01766 0 +OP4 E01767 0 +OP4 E01768 0 +OP4 E01769 0 +OP4 E0176A 0 +OP4 E0176B 0 +OP4 E0176C 0 +OP4 E0176D 0 +OP4 E0176E 0 +OP4 E0176F 0 +OP4 E01770 0 +OP4 E01771 0 +OP4 E01772 0 +OP4 E01773 0 +OP4 E01774 0 +OP4 E01775 0 +OP4 E01776 0 +OP4 E01777 0 +OP4 E01778 0 +OP4 E01779 0 +OP4 E0177A 0 +OP4 E0177B 0 +OP4 E0177C 0 +OP4 E0177D 0 +OP4 E0177E 0 +OP4 E0177F 0 +OP4 E01780 0 +OP4 E01781 0 +OP4 E01782 0 +OP4 E01783 0 +OP4 E01784 0 +OP4 E01785 0 +OP4 E01786 0 +OP4 E01787 0 +OP4 E01788 0 +OP4 E01789 0 +OP4 E0178A 0 +OP4 E0178B 0 +OP4 E0178C 0 +OP4 E0178D 0 +OP4 E0178E 0 +OP4 E0178F 0 +OP4 E01790 0 +OP4 E01791 0 +OP4 E01792 0 +OP4 E01793 0 +OP4 E01794 0 +OP4 E01795 0 +OP4 E01796 0 +OP4 E01797 0 +OP4 E01798 0 +OP4 E01799 0 +OP4 E0179A 0 +OP4 E0179B 0 +OP4 E0179C 0 +OP4 E0179D 0 +OP4 E0179E 0 +OP4 E0179F 0 +OP4 E017A0 0 +OP4 E017A1 0 +OP4 E017A2 0 +OP4 E017A3 0 +OP4 E017A4 0 +OP4 E017A5 0 +OP4 E017A6 0 +OP4 E017A7 0 +OP4 E017A8 0 +OP4 E017A9 0 +OP4 E017AA 0 +OP4 E017AB 0 +OP4 E017AC 0 +OP4 E017AD 0 +OP4 E017AE 0 +OP4 E017AF 0 +OP4 E017B0 0 +OP4 E017B1 0 +OP4 E017B2 0 +OP4 E017B3 0 +OP4 E017B4 0 +OP4 E017B5 0 +OP4 E017B6 0 +OP4 E017B7 0 +OP4 E017B8 0 +OP4 E017B9 0 +OP4 E017BA 0 +OP4 E017BB 0 +OP4 E017BC 0 +OP4 E017BD 0 +OP4 E017BE 0 +OP4 E017BF 0 +OP4 E017C0 0 +OP4 E017C1 0 +OP4 E017C2 0 +OP4 E017C3 0 +OP4 E017C4 0 +OP4 E017C5 0 +OP4 E017C6 0 +OP4 E017C7 0 +OP4 E017C8 0 +OP4 E017C9 0 +OP4 E017CA 0 +OP4 E017CB 0 +OP4 E017CC 0 +OP4 E017CD 0 +OP4 E017CE 0 +OP4 E017CF 0 +OP4 E017D0 0 +OP4 E017D1 0 +OP4 E017D2 0 +OP4 E017D3 0 +OP4 E017D4 0 +OP4 E017D5 0 +OP4 E017D6 0 +OP4 E017D7 0 +OP4 E017D8 0 +OP4 E017D9 0 +OP4 E017DA 0 +OP4 E017DB 0 +OP4 E017DC 0 +OP4 E017DD 0 +OP4 E017DE 0 +OP4 E017DF 0 +OP4 E017E0 0 +OP4 E017E1 0 +OP4 E017E2 0 +OP4 E017E3 0 +OP4 E017E4 0 +OP4 E017E5 0 +OP4 E017E6 0 +OP4 E017E7 0 +OP4 E017E8 0 +OP4 E017E9 0 +OP4 E017EA 0 +OP4 E017EB 0 +OP4 E017EC 0 +OP4 E017ED 0 +OP4 E017EE 0 +OP4 E017EF 0 +OP4 E017F0 0 +OP4 E017F1 0 +OP4 E017F2 0 +OP4 E017F3 0 +OP4 E017F4 0 +OP4 E017F5 0 +OP4 E017F6 0 +OP4 E017F7 0 +OP4 E017F8 0 +OP4 E017F9 0 +OP4 E017FA 0 +OP4 E017FB 0 +OP4 E017FC 0 +OP4 E017FD 0 +OP4 E017FE 0 +OP4 E017FF 0 +OP4 E01800 0 +OP4 E01801 0 +OP4 E01802 0 +OP4 E01803 0 +OP4 E01804 0 +OP4 E01805 0 +OP4 E01806 0 +OP4 E01807 0 +OP4 E01808 0 +OP4 E01809 0 +OP4 E0180A 0 +OP4 E0180B 0 +OP4 E0180C 0 +OP4 E0180D 0 +OP4 E0180E 0 +OP4 E0180F 0 +OP4 E01810 0 +OP4 E01811 0 +OP4 E01812 0 +OP4 E01813 0 +OP4 E01814 0 +OP4 E01815 0 +OP4 E01816 0 +OP4 E01817 0 +OP4 E01818 0 +OP4 E01819 0 +OP4 E0181A 0 +OP4 E0181B 0 +OP4 E0181C 0 +OP4 E0181D 0 +OP4 E0181E 0 +OP4 E0181F 0 +OP4 E01820 0 +OP4 E01821 0 +OP4 E01822 0 +OP4 E01823 0 +OP4 E01824 0 +OP4 E01825 0 +OP4 E01826 0 +OP4 E01827 0 +OP4 E01828 0 +OP4 E01829 0 +OP4 E0182A 0 +OP4 E0182B 0 +OP4 E0182C 0 +OP4 E0182D 0 +OP4 E0182E 0 +OP4 E0182F 0 +OP4 E01830 0 +OP4 E01831 0 +OP4 E01832 0 +OP4 E01833 0 +OP4 E01834 0 +OP4 E01835 0 +OP4 E01836 0 +OP4 E01837 0 +OP4 E01838 0 +OP4 E01839 0 +OP4 E0183A 0 +OP4 E0183B 0 +OP4 E0183C 0 +OP4 E0183D 0 +OP4 E0183E 0 +OP4 E0183F 0 +OP4 E01840 0 +OP4 E01841 0 +OP4 E01842 0 +OP4 E01843 0 +OP4 E01844 0 +OP4 E01845 0 +OP4 E01846 0 +OP4 E01847 0 +OP4 E01848 0 +OP4 E01849 0 +OP4 E0184A 0 +OP4 E0184B 0 +OP4 E0184C 0 +OP4 E0184D 0 +OP4 E0184E 0 +OP4 E0184F 0 +OP4 E01850 0 +OP4 E01851 0 +OP4 E01852 0 +OP4 E01853 0 +OP4 E01854 0 +OP4 E01855 0 +OP4 E01856 0 +OP4 E01857 0 +OP4 E01858 0 +OP4 E01859 0 +OP4 E0185A 0 +OP4 E0185B 0 +OP4 E0185C 0 +OP4 E0185D 0 +OP4 E0185E 0 +OP4 E0185F 0 +OP4 E01860 0 +OP4 E01861 0 +OP4 E01862 0 +OP4 E01863 0 +OP4 E01864 0 +OP4 E01865 0 +OP4 E01866 0 +OP4 E01867 0 +OP4 E01868 0 +OP4 E01869 0 +OP4 E0186A 0 +OP4 E0186B 0 +OP4 E0186C 0 +OP4 E0186D 0 +OP4 E0186E 0 +OP4 E0186F 0 +OP4 E01870 0 +OP4 E01871 0 +OP4 E01872 0 +OP4 E01873 0 +OP4 E01874 0 +OP4 E01875 0 +OP4 E01876 0 +OP4 E01877 0 +OP4 E01878 0 +OP4 E01879 0 +OP4 E0187A 0 +OP4 E0187B 0 +OP4 E0187C 0 +OP4 E0187D 0 +OP4 E0187E 0 +OP4 E0187F 0 +OP4 E01880 0 +OP4 E01881 0 +OP4 E01882 0 +OP4 E01883 0 +OP4 E01884 0 +OP4 E01885 0 +OP4 E01886 0 +OP4 E01887 0 +OP4 E01888 0 +OP4 E01889 0 +OP4 E0188A 0 +OP4 E0188B 0 +OP4 E0188C 0 +OP4 E0188D 0 +OP4 E0188E 0 +OP4 E0188F 0 +OP4 E01890 0 +OP4 E01891 0 +OP4 E01892 0 +OP4 E01893 0 +OP4 E01894 0 +OP4 E01895 0 +OP4 E01896 0 +OP4 E01897 0 +OP4 E01898 0 +OP4 E01899 0 +OP4 E0189A 0 +OP4 E0189B 0 +OP4 E0189C 0 +OP4 E0189D 0 +OP4 E0189E 0 +OP4 E0189F 0 +OP4 E018A0 0 +OP4 E018A1 0 +OP4 E018A2 0 +OP4 E018A3 0 +OP4 E018A4 0 +OP4 E018A5 0 +OP4 E018A6 0 +OP4 E018A7 0 +OP4 E018A8 0 +OP4 E018A9 0 +OP4 E018AA 0 +OP4 E018AB 0 +OP4 E018AC 0 +OP4 E018AD 0 +OP4 E018AE 0 +OP4 E018AF 0 +OP4 E018B0 0 +OP4 E018B1 0 +OP4 E018B2 0 +OP4 E018B3 0 +OP4 E018B4 0 +OP4 E018B5 0 +OP4 E018B6 0 +OP4 E018B7 0 +OP4 E018B8 0 +OP4 E018B9 0 +OP4 E018BA 0 +OP4 E018BB 0 +OP4 E018BC 0 +OP4 E018BD 0 +OP4 E018BE 0 +OP4 E018BF 0 +OP4 E018C0 0 +OP4 E018C1 0 +OP4 E018C2 0 +OP4 E018C3 0 +OP4 E018C4 0 +OP4 E018C5 0 +OP4 E018C6 0 +OP4 E018C7 0 +OP4 E018C8 0 +OP4 E018C9 0 +OP4 E018CA 0 +OP4 E018CB 0 +OP4 E018CC 0 +OP4 E018CD 0 +OP4 E018CE 0 +OP4 E018CF 0 +OP4 E018D0 0 +OP4 E018D1 0 +OP4 E018D2 0 +OP4 E018D3 0 +OP4 E018D4 0 +OP4 E018D5 0 +OP4 E018D6 0 +OP4 E018D7 0 +OP4 E018D8 0 +OP4 E018D9 0 +OP4 E018DA 0 +OP4 E018DB 0 +OP4 E018DC 0 +OP4 E018DD 0 +OP4 E018DE 0 +OP4 E018DF 0 +OP4 E018E0 0 +OP4 E018E1 0 +OP4 E018E2 0 +OP4 E018E3 0 +OP4 E018E4 0 +OP4 E018E5 0 +OP4 E018E6 0 +OP4 E018E7 0 +OP4 E018E8 0 +OP4 E018E9 0 +OP4 E018EA 0 +OP4 E018EB 0 +OP4 E018EC 0 +OP4 E018ED 0 +OP4 E018EE 0 +OP4 E018EF 0 +OP4 E018F0 0 +OP4 E018F1 0 +OP4 E018F2 0 +OP4 E018F3 0 +OP4 E018F4 0 +OP4 E018F5 0 +OP4 E018F6 0 +OP4 E018F7 0 +OP4 E018F8 0 +OP4 E018F9 0 +OP4 E018FA 0 +OP4 E018FB 0 +OP4 E018FC 0 +OP4 E018FD 0 +OP4 E018FE 0 +OP4 E018FF 0 +OP4 E01900 0 +OP4 E01901 0 +OP4 E01902 0 +OP4 E01903 0 +OP4 E01904 0 +OP4 E01905 0 +OP4 E01906 0 +OP4 E01907 0 +OP4 E01908 0 +OP4 E01909 0 +OP4 E0190A 0 +OP4 E0190B 0 +OP4 E0190C 0 +OP4 E0190D 0 +OP4 E0190E 0 +OP4 E0190F 0 +OP4 E01910 0 +OP4 E01911 0 +OP4 E01912 0 +OP4 E01913 0 +OP4 E01914 0 +OP4 E01915 0 +OP4 E01916 0 +OP4 E01917 0 +OP4 E01918 0 +OP4 E01919 0 +OP4 E0191A 0 +OP4 E0191B 0 +OP4 E0191C 0 +OP4 E0191D 0 +OP4 E0191E 0 +OP4 E0191F 0 +OP4 E01920 0 +OP4 E01921 0 +OP4 E01922 0 +OP4 E01923 0 +OP4 E01924 0 +OP4 E01925 0 +OP4 E01926 0 +OP4 E01927 0 +OP4 E01928 0 +OP4 E01929 0 +OP4 E0192A 0 +OP4 E0192B 0 +OP4 E0192C 0 +OP4 E0192D 0 +OP4 E0192E 0 +OP4 E0192F 0 +OP4 E01930 0 +OP4 E01931 0 +OP4 E01932 0 +OP4 E01933 0 +OP4 E01934 0 +OP4 E01935 0 +OP4 E01936 0 +OP4 E01937 0 +OP4 E01938 0 +OP4 E01939 0 +OP4 E0193A 0 +OP4 E0193B 0 +OP4 E0193C 0 +OP4 E0193D 0 +OP4 E0193E 0 +OP4 E0193F 0 +OP4 E01940 0 +OP4 E01941 0 +OP4 E01942 0 +OP4 E01943 0 +OP4 E01944 0 +OP4 E01945 0 +OP4 E01946 0 +OP4 E01947 0 +OP4 E01948 0 +OP4 E01949 0 +OP4 E0194A 0 +OP4 E0194B 0 +OP4 E0194C 0 +OP4 E0194D 0 +OP4 E0194E 0 +OP4 E0194F 0 +OP4 E01950 0 +OP4 E01951 0 +OP4 E01952 0 +OP4 E01953 0 +OP4 E01954 0 +OP4 E01955 0 +OP4 E01956 0 +OP4 E01957 0 +OP4 E01958 0 +OP4 E01959 0 +OP4 E0195A 0 +OP4 E0195B 0 +OP4 E0195C 0 +OP4 E0195D 0 +OP4 E0195E 0 +OP4 E0195F 0 +OP4 E01960 0 +OP4 E01961 0 +OP4 E01962 0 +OP4 E01963 0 +OP4 E01964 0 +OP4 E01965 0 +OP4 E01966 0 +OP4 E01967 0 +OP4 E01968 0 +OP4 E01969 0 +OP4 E0196A 0 +OP4 E0196B 0 +OP4 E0196C 0 +OP4 E0196D 0 +OP4 E0196E 0 +OP4 E0196F 0 +OP4 E01970 0 +OP4 E01971 0 +OP4 E01972 0 +OP4 E01973 0 +OP4 E01974 0 +OP4 E01975 0 +OP4 E01976 0 +OP4 E01977 0 +OP4 E01978 0 +OP4 E01979 0 +OP4 E0197A 0 +OP4 E0197B 0 +OP4 E0197C 0 +OP4 E0197D 0 +OP4 E0197E 0 +OP4 E0197F 0 +OP4 E01980 0 +OP4 E01981 0 +OP4 E01982 0 +OP4 E01983 0 +OP4 E01984 0 +OP4 E01985 0 +OP4 E01986 0 +OP4 E01987 0 +OP4 E01988 0 +OP4 E01989 0 +OP4 E0198A 0 +OP4 E0198B 0 +OP4 E0198C 0 +OP4 E0198D 0 +OP4 E0198E 0 +OP4 E0198F 0 +OP4 E01990 0 +OP4 E01991 0 +OP4 E01992 0 +OP4 E01993 0 +OP4 E01994 0 +OP4 E01995 0 +OP4 E01996 0 +OP4 E01997 0 +OP4 E01998 0 +OP4 E01999 0 +OP4 E0199A 0 +OP4 E0199B 0 +OP4 E0199C 0 +OP4 E0199D 0 +OP4 E0199E 0 +OP4 E0199F 0 +OP4 E019A0 0 +OP4 E019A1 0 +OP4 E019A2 0 +OP4 E019A3 0 +OP4 E019A4 0 +OP4 E019A5 0 +OP4 E019A6 0 +OP4 E019A7 0 +OP4 E019A8 0 +OP4 E019A9 0 +OP4 E019AA 0 +OP4 E019AB 0 +OP4 E019AC 0 +OP4 E019AD 0 +OP4 E019AE 0 +OP4 E019AF 0 +OP4 E019B0 0 +OP4 E019B1 0 +OP4 E019B2 0 +OP4 E019B3 0 +OP4 E019B4 0 +OP4 E019B5 0 +OP4 E019B6 0 +OP4 E019B7 0 +OP4 E019B8 0 +OP4 E019B9 0 +OP4 E019BA 0 +OP4 E019BB 0 +OP4 E019BC 0 +OP4 E019BD 0 +OP4 E019BE 0 +OP4 E019BF 0 +OP4 E019C0 0 +OP4 E019C1 0 +OP4 E019C2 0 +OP4 E019C3 0 +OP4 E019C4 0 +OP4 E019C5 0 +OP4 E019C6 0 +OP4 E019C7 0 +OP4 E019C8 0 +OP4 E019C9 0 +OP4 E019CA 0 +OP4 E019CB 0 +OP4 E019CC 0 +OP4 E019CD 0 +OP4 E019CE 0 +OP4 E019CF 0 +OP4 E019D0 0 +OP4 E019D1 0 +OP4 E019D2 0 +OP4 E019D3 0 +OP4 E019D4 0 +OP4 E019D5 0 +OP4 E019D6 0 +OP4 E019D7 0 +OP4 E019D8 0 +OP4 E019D9 0 +OP4 E019DA 0 +OP4 E019DB 0 +OP4 E019DC 0 +OP4 E019DD 0 +OP4 E019DE 0 +OP4 E019DF 0 +OP4 E019E0 0 +OP4 E019E1 0 +OP4 E019E2 0 +OP4 E019E3 0 +OP4 E019E4 0 +OP4 E019E5 0 +OP4 E019E6 0 +OP4 E019E7 0 +OP4 E019E8 0 +OP4 E019E9 0 +OP4 E019EA 0 +OP4 E019EB 0 +OP4 E019EC 0 +OP4 E019ED 0 +OP4 E019EE 0 +OP4 E019EF 0 +OP4 E019F0 0 +OP4 E019F1 0 +OP4 E019F2 0 +OP4 E019F3 0 +OP4 E019F4 0 +OP4 E019F5 0 +OP4 E019F6 0 +OP4 E019F7 0 +OP4 E019F8 0 +OP4 E019F9 0 +OP4 E019FA 0 +OP4 E019FB 0 +OP4 E019FC 0 +OP4 E019FD 0 +OP4 E019FE 0 +OP4 E019FF 0 +OP4 E01A00 0 +OP4 E01A01 0 +OP4 E01A02 0 +OP4 E01A03 0 +OP4 E01A04 0 +OP4 E01A05 0 +OP4 E01A06 0 +OP4 E01A07 0 +OP4 E01A08 0 +OP4 E01A09 0 +OP4 E01A0A 0 +OP4 E01A0B 0 +OP4 E01A0C 0 +OP4 E01A0D 0 +OP4 E01A0E 0 +OP4 E01A0F 0 +OP4 E01A10 0 +OP4 E01A11 0 +OP4 E01A12 0 +OP4 E01A13 0 +OP4 E01A14 0 +OP4 E01A15 0 +OP4 E01A16 0 +OP4 E01A17 0 +OP4 E01A18 0 +OP4 E01A19 0 +OP4 E01A1A 0 +OP4 E01A1B 0 +OP4 E01A1C 0 +OP4 E01A1D 0 +OP4 E01A1E 0 +OP4 E01A1F 0 +OP4 E01A20 0 +OP4 E01A21 0 +OP4 E01A22 0 +OP4 E01A23 0 +OP4 E01A24 0 +OP4 E01A25 0 +OP4 E01A26 0 +OP4 E01A27 0 +OP4 E01A28 0 +OP4 E01A29 0 +OP4 E01A2A 0 +OP4 E01A2B 0 +OP4 E01A2C 0 +OP4 E01A2D 0 +OP4 E01A2E 0 +OP4 E01A2F 0 +OP4 E01A30 0 +OP4 E01A31 0 +OP4 E01A32 0 +OP4 E01A33 0 +OP4 E01A34 0 +OP4 E01A35 0 +OP4 E01A36 0 +OP4 E01A37 0 +OP4 E01A38 0 +OP4 E01A39 0 +OP4 E01A3A 0 +OP4 E01A3B 0 +OP4 E01A3C 0 +OP4 E01A3D 0 +OP4 E01A3E 0 +OP4 E01A3F 0 +OP4 E01A40 0 +OP4 E01A41 0 +OP4 E01A42 0 +OP4 E01A43 0 +OP4 E01A44 0 +OP4 E01A45 0 +OP4 E01A46 0 +OP4 E01A47 0 +OP4 E01A48 0 +OP4 E01A49 0 +OP4 E01A4A 0 +OP4 E01A4B 0 +OP4 E01A4C 0 +OP4 E01A4D 0 +OP4 E01A4E 0 +OP4 E01A4F 0 +OP4 E01A50 0 +OP4 E01A51 0 +OP4 E01A52 0 +OP4 E01A53 0 +OP4 E01A54 0 +OP4 E01A55 0 +OP4 E01A56 0 +OP4 E01A57 0 +OP4 E01A58 0 +OP4 E01A59 0 +OP4 E01A5A 0 +OP4 E01A5B 0 +OP4 E01A5C 0 +OP4 E01A5D 0 +OP4 E01A5E 0 +OP4 E01A5F 0 +OP4 E01A60 0 +OP4 E01A61 0 +OP4 E01A62 0 +OP4 E01A63 0 +OP4 E01A64 0 +OP4 E01A65 0 +OP4 E01A66 0 +OP4 E01A67 0 +OP4 E01A68 0 +OP4 E01A69 0 +OP4 E01A6A 0 +OP4 E01A6B 0 +OP4 E01A6C 0 +OP4 E01A6D 0 +OP4 E01A6E 0 +OP4 E01A6F 0 +OP4 E01A70 0 +OP4 E01A71 0 +OP4 E01A72 0 +OP4 E01A73 0 +OP4 E01A74 0 +OP4 E01A75 0 +OP4 E01A76 0 +OP4 E01A77 0 +OP4 E01A78 0 +OP4 E01A79 0 +OP4 E01A7A 0 +OP4 E01A7B 0 +OP4 E01A7C 0 +OP4 E01A7D 0 +OP4 E01A7E 0 +OP4 E01A7F 0 +OP4 E01A80 0 +OP4 E01A81 0 +OP4 E01A82 0 +OP4 E01A83 0 +OP4 E01A84 0 +OP4 E01A85 0 +OP4 E01A86 0 +OP4 E01A87 0 +OP4 E01A88 0 +OP4 E01A89 0 +OP4 E01A8A 0 +OP4 E01A8B 0 +OP4 E01A8C 0 +OP4 E01A8D 0 +OP4 E01A8E 0 +OP4 E01A8F 0 +OP4 E01A90 0 +OP4 E01A91 0 +OP4 E01A92 0 +OP4 E01A93 0 +OP4 E01A94 0 +OP4 E01A95 0 +OP4 E01A96 0 +OP4 E01A97 0 +OP4 E01A98 0 +OP4 E01A99 0 +OP4 E01A9A 0 +OP4 E01A9B 0 +OP4 E01A9C 0 +OP4 E01A9D 0 +OP4 E01A9E 0 +OP4 E01A9F 0 +OP4 E01AA0 0 +OP4 E01AA1 0 +OP4 E01AA2 0 +OP4 E01AA3 0 +OP4 E01AA4 0 +OP4 E01AA5 0 +OP4 E01AA6 0 +OP4 E01AA7 0 +OP4 E01AA8 0 +OP4 E01AA9 0 +OP4 E01AAA 0 +OP4 E01AAB 0 +OP4 E01AAC 0 +OP4 E01AAD 0 +OP4 E01AAE 0 +OP4 E01AAF 0 +OP4 E01AB0 0 +OP4 E01AB1 0 +OP4 E01AB2 0 +OP4 E01AB3 0 +OP4 E01AB4 0 +OP4 E01AB5 0 +OP4 E01AB6 0 +OP4 E01AB7 0 +OP4 E01AB8 0 +OP4 E01AB9 0 +OP4 E01ABA 0 +OP4 E01ABB 0 +OP4 E01ABC 0 +OP4 E01ABD 0 +OP4 E01ABE 0 +OP4 E01ABF 0 +OP4 E01AC0 0 +OP4 E01AC1 0 +OP4 E01AC2 0 +OP4 E01AC3 0 +OP4 E01AC4 0 +OP4 E01AC5 0 +OP4 E01AC6 0 +OP4 E01AC7 0 +OP4 E01AC8 0 +OP4 E01AC9 0 +OP4 E01ACA 0 +OP4 E01ACB 0 +OP4 E01ACC 0 +OP4 E01ACD 0 +OP4 E01ACE 0 +OP4 E01ACF 0 +OP4 E01AD0 0 +OP4 E01AD1 0 +OP4 E01AD2 0 +OP4 E01AD3 0 +OP4 E01AD4 0 +OP4 E01AD5 0 +OP4 E01AD6 0 +OP4 E01AD7 0 +OP4 E01AD8 0 +OP4 E01AD9 0 +OP4 E01ADA 0 +OP4 E01ADB 0 +OP4 E01ADC 0 +OP4 E01ADD 0 +OP4 E01ADE 0 +OP4 E01ADF 0 +OP4 E01AE0 0 +OP4 E01AE1 0 +OP4 E01AE2 0 +OP4 E01AE3 0 +OP4 E01AE4 0 +OP4 E01AE5 0 +OP4 E01AE6 0 +OP4 E01AE7 0 +OP4 E01AE8 0 +OP4 E01AE9 0 +OP4 E01AEA 0 +OP4 E01AEB 0 +OP4 E01AEC 0 +OP4 E01AED 0 +OP4 E01AEE 0 +OP4 E01AEF 0 +OP4 E01AF0 0 +OP4 E01AF1 0 +OP4 E01AF2 0 +OP4 E01AF3 0 +OP4 E01AF4 0 +OP4 E01AF5 0 +OP4 E01AF6 0 +OP4 E01AF7 0 +OP4 E01AF8 0 +OP4 E01AF9 0 +OP4 E01AFA 0 +OP4 E01AFB 0 +OP4 E01AFC 0 +OP4 E01AFD 0 +OP4 E01AFE 0 +OP4 E01AFF 0 +OP4 E01B00 0 +OP4 E01B01 0 +OP4 E01B02 0 +OP4 E01B03 0 +OP4 E01B04 0 +OP4 E01B05 0 +OP4 E01B06 0 +OP4 E01B07 0 +OP4 E01B08 0 +OP4 E01B09 0 +OP4 E01B0A 0 +OP4 E01B0B 0 +OP4 E01B0C 0 +OP4 E01B0D 0 +OP4 E01B0E 0 +OP4 E01B0F 0 +OP4 E01B10 0 +OP4 E01B11 0 +OP4 E01B12 0 +OP4 E01B13 0 +OP4 E01B14 0 +OP4 E01B15 0 +OP4 E01B16 0 +OP4 E01B17 0 +OP4 E01B18 0 +OP4 E01B19 0 +OP4 E01B1A 0 +OP4 E01B1B 0 +OP4 E01B1C 0 +OP4 E01B1D 0 +OP4 E01B1E 0 +OP4 E01B1F 0 +OP4 E01B20 0 +OP4 E01B21 0 +OP4 E01B22 0 +OP4 E01B23 0 +OP4 E01B24 0 +OP4 E01B25 0 +OP4 E01B26 0 +OP4 E01B27 0 +OP4 E01B28 0 +OP4 E01B29 0 +OP4 E01B2A 0 +OP4 E01B2B 0 +OP4 E01B2C 0 +OP4 E01B2D 0 +OP4 E01B2E 0 +OP4 E01B2F 0 +OP4 E01B30 0 +OP4 E01B31 0 +OP4 E01B32 0 +OP4 E01B33 0 +OP4 E01B34 0 +OP4 E01B35 0 +OP4 E01B36 0 +OP4 E01B37 0 +OP4 E01B38 0 +OP4 E01B39 0 +OP4 E01B3A 0 +OP4 E01B3B 0 +OP4 E01B3C 0 +OP4 E01B3D 0 +OP4 E01B3E 0 +OP4 E01B3F 0 +OP4 E01B40 0 +OP4 E01B41 0 +OP4 E01B42 0 +OP4 E01B43 0 +OP4 E01B44 0 +OP4 E01B45 0 +OP4 E01B46 0 +OP4 E01B47 0 +OP4 E01B48 0 +OP4 E01B49 0 +OP4 E01B4A 0 +OP4 E01B4B 0 +OP4 E01B4C 0 +OP4 E01B4D 0 +OP4 E01B4E 0 +OP4 E01B4F 0 +OP4 E01B50 0 +OP4 E01B51 0 +OP4 E01B52 0 +OP4 E01B53 0 +OP4 E01B54 0 +OP4 E01B55 0 +OP4 E01B56 0 +OP4 E01B57 0 +OP4 E01B58 0 +OP4 E01B59 0 +OP4 E01B5A 0 +OP4 E01B5B 0 +OP4 E01B5C 0 +OP4 E01B5D 0 +OP4 E01B5E 0 +OP4 E01B5F 0 +OP4 E01B60 0 +OP4 E01B61 0 +OP4 E01B62 0 +OP4 E01B63 0 +OP4 E01B64 0 +OP4 E01B65 0 +OP4 E01B66 0 +OP4 E01B67 0 +OP4 E01B68 0 +OP4 E01B69 0 +OP4 E01B6A 0 +OP4 E01B6B 0 +OP4 E01B6C 0 +OP4 E01B6D 0 +OP4 E01B6E 0 +OP4 E01B6F 0 +OP4 E01B70 0 +OP4 E01B71 0 +OP4 E01B72 0 +OP4 E01B73 0 +OP4 E01B74 0 +OP4 E01B75 0 +OP4 E01B76 0 +OP4 E01B77 0 +OP4 E01B78 0 +OP4 E01B79 0 +OP4 E01B7A 0 +OP4 E01B7B 0 +OP4 E01B7C 0 +OP4 E01B7D 0 +OP4 E01B7E 0 +OP4 E01B7F 0 +OP4 E01B80 0 +OP4 E01B81 0 +OP4 E01B82 0 +OP4 E01B83 0 +OP4 E01B84 0 +OP4 E01B85 0 +OP4 E01B86 0 +OP4 E01B87 0 +OP4 E01B88 0 +OP4 E01B89 0 +OP4 E01B8A 0 +OP4 E01B8B 0 +OP4 E01B8C 0 +OP4 E01B8D 0 +OP4 E01B8E 0 +OP4 E01B8F 0 +OP4 E01B90 0 +OP4 E01B91 0 +OP4 E01B92 0 +OP4 E01B93 0 +OP4 E01B94 0 +OP4 E01B95 0 +OP4 E01B96 0 +OP4 E01B97 0 +OP4 E01B98 0 +OP4 E01B99 0 +OP4 E01B9A 0 +OP4 E01B9B 0 +OP4 E01B9C 0 +OP4 E01B9D 0 +OP4 E01B9E 0 +OP4 E01B9F 0 +OP4 E01BA0 0 +OP4 E01BA1 0 +OP4 E01BA2 0 +OP4 E01BA3 0 +OP4 E01BA4 0 +OP4 E01BA5 0 +OP4 E01BA6 0 +OP4 E01BA7 0 +OP4 E01BA8 0 +OP4 E01BA9 0 +OP4 E01BAA 0 +OP4 E01BAB 0 +OP4 E01BAC 0 +OP4 E01BAD 0 +OP4 E01BAE 0 +OP4 E01BAF 0 +OP4 E01BB0 0 +OP4 E01BB1 0 +OP4 E01BB2 0 +OP4 E01BB3 0 +OP4 E01BB4 0 +OP4 E01BB5 0 +OP4 E01BB6 0 +OP4 E01BB7 0 +OP4 E01BB8 0 +OP4 E01BB9 0 +OP4 E01BBA 0 +OP4 E01BBB 0 +OP4 E01BBC 0 +OP4 E01BBD 0 +OP4 E01BBE 0 +OP4 E01BBF 0 +OP4 E01BC0 0 +OP4 E01BC1 0 +OP4 E01BC2 0 +OP4 E01BC3 0 +OP4 E01BC4 0 +OP4 E01BC5 0 +OP4 E01BC6 0 +OP4 E01BC7 0 +OP4 E01BC8 0 +OP4 E01BC9 0 +OP4 E01BCA 0 +OP4 E01BCB 0 +OP4 E01BCC 0 +OP4 E01BCD 0 +OP4 E01BCE 0 +OP4 E01BCF 0 +OP4 E01BD0 0 +OP4 E01BD1 0 +OP4 E01BD2 0 +OP4 E01BD3 0 +OP4 E01BD4 0 +OP4 E01BD5 0 +OP4 E01BD6 0 +OP4 E01BD7 0 +OP4 E01BD8 0 +OP4 E01BD9 0 +OP4 E01BDA 0 +OP4 E01BDB 0 +OP4 E01BDC 0 +OP4 E01BDD 0 +OP4 E01BDE 0 +OP4 E01BDF 0 +OP4 E01BE0 0 +OP4 E01BE1 0 +OP4 E01BE2 0 +OP4 E01BE3 0 +OP4 E01BE4 0 +OP4 E01BE5 0 +OP4 E01BE6 0 +OP4 E01BE7 0 +OP4 E01BE8 0 +OP4 E01BE9 0 +OP4 E01BEA 0 +OP4 E01BEB 0 +OP4 E01BEC 0 +OP4 E01BED 0 +OP4 E01BEE 0 +OP4 E01BEF 0 +OP4 E01BF0 0 +OP4 E01BF1 0 +OP4 E01BF2 0 +OP4 E01BF3 0 +OP4 E01BF4 0 +OP4 E01BF5 0 +OP4 E01BF6 0 +OP4 E01BF7 0 +OP4 E01BF8 0 +OP4 E01BF9 0 +OP4 E01BFA 0 +OP4 E01BFB 0 +OP4 E01BFC 0 +OP4 E01BFD 0 +OP4 E01BFE 0 +OP4 E01BFF 0 +OP4 E01C00 0 +OP4 E01C01 0 +OP4 E01C02 0 +OP4 E01C03 0 +OP4 E01C04 0 +OP4 E01C05 0 +OP4 E01C06 0 +OP4 E01C07 0 +OP4 E01C08 0 +OP4 E01C09 0 +OP4 E01C0A 0 +OP4 E01C0B 0 +OP4 E01C0C 0 +OP4 E01C0D 0 +OP4 E01C0E 0 +OP4 E01C0F 0 +OP4 E01C10 0 +OP4 E01C11 0 +OP4 E01C12 0 +OP4 E01C13 0 +OP4 E01C14 0 +OP4 E01C15 0 +OP4 E01C16 0 +OP4 E01C17 0 +OP4 E01C18 0 +OP4 E01C19 0 +OP4 E01C1A 0 +OP4 E01C1B 0 +OP4 E01C1C 0 +OP4 E01C1D 0 +OP4 E01C1E 0 +OP4 E01C1F 0 +OP4 E01C20 0 +OP4 E01C21 0 +OP4 E01C22 0 +OP4 E01C23 0 +OP4 E01C24 0 +OP4 E01C25 0 +OP4 E01C26 0 +OP4 E01C27 0 +OP4 E01C28 0 +OP4 E01C29 0 +OP4 E01C2A 0 +OP4 E01C2B 0 +OP4 E01C2C 0 +OP4 E01C2D 0 +OP4 E01C2E 0 +OP4 E01C2F 0 +OP4 E01C30 0 +OP4 E01C31 0 +OP4 E01C32 0 +OP4 E01C33 0 +OP4 E01C34 0 +OP4 E01C35 0 +OP4 E01C36 0 +OP4 E01C37 0 +OP4 E01C38 0 +OP4 E01C39 0 +OP4 E01C3A 0 +OP4 E01C3B 0 +OP4 E01C3C 0 +OP4 E01C3D 0 +OP4 E01C3E 0 +OP4 E01C3F 0 +OP4 E01C40 0 +OP4 E01C41 0 +OP4 E01C42 0 +OP4 E01C43 0 +OP4 E01C44 0 +OP4 E01C45 0 +OP4 E01C46 0 +OP4 E01C47 0 +OP4 E01C48 0 +OP4 E01C49 0 +OP4 E01C4A 0 +OP4 E01C4B 0 +OP4 E01C4C 0 +OP4 E01C4D 0 +OP4 E01C4E 0 +OP4 E01C4F 0 +OP4 E01C50 0 +OP4 E01C51 0 +OP4 E01C52 0 +OP4 E01C53 0 +OP4 E01C54 0 +OP4 E01C55 0 +OP4 E01C56 0 +OP4 E01C57 0 +OP4 E01C58 0 +OP4 E01C59 0 +OP4 E01C5A 0 +OP4 E01C5B 0 +OP4 E01C5C 0 +OP4 E01C5D 0 +OP4 E01C5E 0 +OP4 E01C5F 0 +OP4 E01C60 0 +OP4 E01C61 0 +OP4 E01C62 0 +OP4 E01C63 0 +OP4 E01C64 0 +OP4 E01C65 0 +OP4 E01C66 0 +OP4 E01C67 0 +OP4 E01C68 0 +OP4 E01C69 0 +OP4 E01C6A 0 +OP4 E01C6B 0 +OP4 E01C6C 0 +OP4 E01C6D 0 +OP4 E01C6E 0 +OP4 E01C6F 0 +OP4 E01C70 0 +OP4 E01C71 0 +OP4 E01C72 0 +OP4 E01C73 0 +OP4 E01C74 0 +OP4 E01C75 0 +OP4 E01C76 0 +OP4 E01C77 0 +OP4 E01C78 0 +OP4 E01C79 0 +OP4 E01C7A 0 +OP4 E01C7B 0 +OP4 E01C7C 0 +OP4 E01C7D 0 +OP4 E01C7E 0 +OP4 E01C7F 0 +OP4 E01C80 0 +OP4 E01C81 0 +OP4 E01C82 0 +OP4 E01C83 0 +OP4 E01C84 0 +OP4 E01C85 0 +OP4 E01C86 0 +OP4 E01C87 0 +OP4 E01C88 0 +OP4 E01C89 0 +OP4 E01C8A 0 +OP4 E01C8B 0 +OP4 E01C8C 0 +OP4 E01C8D 0 +OP4 E01C8E 0 +OP4 E01C8F 0 +OP4 E01C90 0 +OP4 E01C91 0 +OP4 E01C92 0 +OP4 E01C93 0 +OP4 E01C94 0 +OP4 E01C95 0 +OP4 E01C96 0 +OP4 E01C97 0 +OP4 E01C98 0 +OP4 E01C99 0 +OP4 E01C9A 0 +OP4 E01C9B 0 +OP4 E01C9C 0 +OP4 E01C9D 0 +OP4 E01C9E 0 +OP4 E01C9F 0 +OP4 E01CA0 0 +OP4 E01CA1 0 +OP4 E01CA2 0 +OP4 E01CA3 0 +OP4 E01CA4 0 +OP4 E01CA5 0 +OP4 E01CA6 0 +OP4 E01CA7 0 +OP4 E01CA8 0 +OP4 E01CA9 0 +OP4 E01CAA 0 +OP4 E01CAB 0 +OP4 E01CAC 0 +OP4 E01CAD 0 +OP4 E01CAE 0 +OP4 E01CAF 0 +OP4 E01CB0 0 +OP4 E01CB1 0 +OP4 E01CB2 0 +OP4 E01CB3 0 +OP4 E01CB4 0 +OP4 E01CB5 0 +OP4 E01CB6 0 +OP4 E01CB7 0 +OP4 E01CB8 0 +OP4 E01CB9 0 +OP4 E01CBA 0 +OP4 E01CBB 0 +OP4 E01CBC 0 +OP4 E01CBD 0 +OP4 E01CBE 0 +OP4 E01CBF 0 +OP4 E01CC0 0 +OP4 E01CC1 0 +OP4 E01CC2 0 +OP4 E01CC3 0 +OP4 E01CC4 0 +OP4 E01CC5 0 +OP4 E01CC6 0 +OP4 E01CC7 0 +OP4 E01CC8 0 +OP4 E01CC9 0 +OP4 E01CCA 0 +OP4 E01CCB 0 +OP4 E01CCC 0 +OP4 E01CCD 0 +OP4 E01CCE 0 +OP4 E01CCF 0 +OP4 E01CD0 0 +OP4 E01CD1 0 +OP4 E01CD2 0 +OP4 E01CD3 0 +OP4 E01CD4 0 +OP4 E01CD5 0 +OP4 E01CD6 0 +OP4 E01CD7 0 +OP4 E01CD8 0 +OP4 E01CD9 0 +OP4 E01CDA 0 +OP4 E01CDB 0 +OP4 E01CDC 0 +OP4 E01CDD 0 +OP4 E01CDE 0 +OP4 E01CDF 0 +OP4 E01CE0 0 +OP4 E01CE1 0 +OP4 E01CE2 0 +OP4 E01CE3 0 +OP4 E01CE4 0 +OP4 E01CE5 0 +OP4 E01CE6 0 +OP4 E01CE7 0 +OP4 E01CE8 0 +OP4 E01CE9 0 +OP4 E01CEA 0 +OP4 E01CEB 0 +OP4 E01CEC 0 +OP4 E01CED 0 +OP4 E01CEE 0 +OP4 E01CEF 0 +OP4 E01CF0 0 +OP4 E01CF1 0 +OP4 E01CF2 0 +OP4 E01CF3 0 +OP4 E01CF4 0 +OP4 E01CF5 0 +OP4 E01CF6 0 +OP4 E01CF7 0 +OP4 E01CF8 0 +OP4 E01CF9 0 +OP4 E01CFA 0 +OP4 E01CFB 0 +OP4 E01CFC 0 +OP4 E01CFD 0 +OP4 E01CFE 0 +OP4 E01CFF 0 +OP4 E01D00 0 +OP4 E01D01 0 +OP4 E01D02 0 +OP4 E01D03 0 +OP4 E01D04 0 +OP4 E01D05 0 +OP4 E01D06 0 +OP4 E01D07 0 +OP4 E01D08 0 +OP4 E01D09 0 +OP4 E01D0A 0 +OP4 E01D0B 0 +OP4 E01D0C 0 +OP4 E01D0D 0 +OP4 E01D0E 0 +OP4 E01D0F 0 +OP4 E01D10 0 +OP4 E01D11 0 +OP4 E01D12 0 +OP4 E01D13 0 +OP4 E01D14 0 +OP4 E01D15 0 +OP4 E01D16 0 +OP4 E01D17 0 +OP4 E01D18 0 +OP4 E01D19 0 +OP4 E01D1A 0 +OP4 E01D1B 0 +OP4 E01D1C 0 +OP4 E01D1D 0 +OP4 E01D1E 0 +OP4 E01D1F 0 +OP4 E01D20 0 +OP4 E01D21 0 +OP4 E01D22 0 +OP4 E01D23 0 +OP4 E01D24 0 +OP4 E01D25 0 +OP4 E01D26 0 +OP4 E01D27 0 +OP4 E01D28 0 +OP4 E01D29 0 +OP4 E01D2A 0 +OP4 E01D2B 0 +OP4 E01D2C 0 +OP4 E01D2D 0 +OP4 E01D2E 0 +OP4 E01D2F 0 +OP4 E01D30 0 +OP4 E01D31 0 +OP4 E01D32 0 +OP4 E01D33 0 +OP4 E01D34 0 +OP4 E01D35 0 +OP4 E01D36 0 +OP4 E01D37 0 +OP4 E01D38 0 +OP4 E01D39 0 +OP4 E01D3A 0 +OP4 E01D3B 0 +OP4 E01D3C 0 +OP4 E01D3D 0 +OP4 E01D3E 0 +OP4 E01D3F 0 +OP4 E01D40 0 +OP4 E01D41 0 +OP4 E01D42 0 +OP4 E01D43 0 +OP4 E01D44 0 +OP4 E01D45 0 +OP4 E01D46 0 +OP4 E01D47 0 +OP4 E01D48 0 +OP4 E01D49 0 +OP4 E01D4A 0 +OP4 E01D4B 0 +OP4 E01D4C 0 +OP4 E01D4D 0 +OP4 E01D4E 0 +OP4 E01D4F 0 +OP4 E01D50 0 +OP4 E01D51 0 +OP4 E01D52 0 +OP4 E01D53 0 +OP4 E01D54 0 +OP4 E01D55 0 +OP4 E01D56 0 +OP4 E01D57 0 +OP4 E01D58 0 +OP4 E01D59 0 +OP4 E01D5A 0 +OP4 E01D5B 0 +OP4 E01D5C 0 +OP4 E01D5D 0 +OP4 E01D5E 0 +OP4 E01D5F 0 +OP4 E01D60 0 +OP4 E01D61 0 +OP4 E01D62 0 +OP4 E01D63 0 +OP4 E01D64 0 +OP4 E01D65 0 +OP4 E01D66 0 +OP4 E01D67 0 +OP4 E01D68 0 +OP4 E01D69 0 +OP4 E01D6A 0 +OP4 E01D6B 0 +OP4 E01D6C 0 +OP4 E01D6D 0 +OP4 E01D6E 0 +OP4 E01D6F 0 +OP4 E01D70 0 +OP4 E01D71 0 +OP4 E01D72 0 +OP4 E01D73 0 +OP4 E01D74 0 +OP4 E01D75 0 +OP4 E01D76 0 +OP4 E01D77 0 +OP4 E01D78 0 +OP4 E01D79 0 +OP4 E01D7A 0 +OP4 E01D7B 0 +OP4 E01D7C 0 +OP4 E01D7D 0 +OP4 E01D7E 0 +OP4 E01D7F 0 +OP4 E01D80 0 +OP4 E01D81 0 +OP4 E01D82 0 +OP4 E01D83 0 +OP4 E01D84 0 +OP4 E01D85 0 +OP4 E01D86 0 +OP4 E01D87 0 +OP4 E01D88 0 +OP4 E01D89 0 +OP4 E01D8A 0 +OP4 E01D8B 0 +OP4 E01D8C 0 +OP4 E01D8D 0 +OP4 E01D8E 0 +OP4 E01D8F 0 +OP4 E01D90 0 +OP4 E01D91 0 +OP4 E01D92 0 +OP4 E01D93 0 +OP4 E01D94 0 +OP4 E01D95 0 +OP4 E01D96 0 +OP4 E01D97 0 +OP4 E01D98 0 +OP4 E01D99 0 +OP4 E01D9A 0 +OP4 E01D9B 0 +OP4 E01D9C 0 +OP4 E01D9D 0 +OP4 E01D9E 0 +OP4 E01D9F 0 +OP4 E01DA0 0 +OP4 E01DA1 0 +OP4 E01DA2 0 +OP4 E01DA3 0 +OP4 E01DA4 0 +OP4 E01DA5 0 +OP4 E01DA6 0 +OP4 E01DA7 0 +OP4 E01DA8 0 +OP4 E01DA9 0 +OP4 E01DAA 0 +OP4 E01DAB 0 +OP4 E01DAC 0 +OP4 E01DAD 0 +OP4 E01DAE 0 +OP4 E01DAF 0 +OP4 E01DB0 0 +OP4 E01DB1 0 +OP4 E01DB2 0 +OP4 E01DB3 0 +OP4 E01DB4 0 +OP4 E01DB5 0 +OP4 E01DB6 0 +OP4 E01DB7 0 +OP4 E01DB8 0 +OP4 E01DB9 0 +OP4 E01DBA 0 +OP4 E01DBB 0 +OP4 E01DBC 0 +OP4 E01DBD 0 +OP4 E01DBE 0 +OP4 E01DBF 0 +OP4 E01DC0 0 +OP4 E01DC1 0 +OP4 E01DC2 0 +OP4 E01DC3 0 +OP4 E01DC4 0 +OP4 E01DC5 0 +OP4 E01DC6 0 +OP4 E01DC7 0 +OP4 E01DC8 0 +OP4 E01DC9 0 +OP4 E01DCA 0 +OP4 E01DCB 0 +OP4 E01DCC 0 +OP4 E01DCD 0 +OP4 E01DCE 0 +OP4 E01DCF 0 +OP4 E01DD0 0 +OP4 E01DD1 0 +OP4 E01DD2 0 +OP4 E01DD3 0 +OP4 E01DD4 0 +OP4 E01DD5 0 +OP4 E01DD6 0 +OP4 E01DD7 0 +OP4 E01DD8 0 +OP4 E01DD9 0 +OP4 E01DDA 0 +OP4 E01DDB 0 +OP4 E01DDC 0 +OP4 E01DDD 0 +OP4 E01DDE 0 +OP4 E01DDF 0 +OP4 E01DE0 0 +OP4 E01DE1 0 +OP4 E01DE2 0 +OP4 E01DE3 0 +OP4 E01DE4 0 +OP4 E01DE5 0 +OP4 E01DE6 0 +OP4 E01DE7 0 +OP4 E01DE8 0 +OP4 E01DE9 0 +OP4 E01DEA 0 +OP4 E01DEB 0 +OP4 E01DEC 0 +OP4 E01DED 0 +OP4 E01DEE 0 +OP4 E01DEF 0 +OP4 E01DF0 0 +OP4 E01DF1 0 +OP4 E01DF2 0 +OP4 E01DF3 0 +OP4 E01DF4 0 +OP4 E01DF5 0 +OP4 E01DF6 0 +OP4 E01DF7 0 +OP4 E01DF8 0 +OP4 E01DF9 0 +OP4 E01DFA 0 +OP4 E01DFB 0 +OP4 E01DFC 0 +OP4 E01DFD 0 +OP4 E01DFE 0 +OP4 E01DFF 0 +OP4 E01E00 0 +OP4 E01E01 0 +OP4 E01E02 0 +OP4 E01E03 0 +OP4 E01E04 0 +OP4 E01E05 0 +OP4 E01E06 0 +OP4 E01E07 0 +OP4 E01E08 0 +OP4 E01E09 0 +OP4 E01E0A 0 +OP4 E01E0B 0 +OP4 E01E0C 0 +OP4 E01E0D 0 +OP4 E01E0E 0 +OP4 E01E0F 0 +OP4 E01E10 0 +OP4 E01E11 0 +OP4 E01E12 0 +OP4 E01E13 0 +OP4 E01E14 0 +OP4 E01E15 0 +OP4 E01E16 0 +OP4 E01E17 0 +OP4 E01E18 0 +OP4 E01E19 0 +OP4 E01E1A 0 +OP4 E01E1B 0 +OP4 E01E1C 0 +OP4 E01E1D 0 +OP4 E01E1E 0 +OP4 E01E1F 0 +OP4 E01E20 0 +OP4 E01E21 0 +OP4 E01E22 0 +OP4 E01E23 0 +OP4 E01E24 0 +OP4 E01E25 0 +OP4 E01E26 0 +OP4 E01E27 0 +OP4 E01E28 0 +OP4 E01E29 0 +OP4 E01E2A 0 +OP4 E01E2B 0 +OP4 E01E2C 0 +OP4 E01E2D 0 +OP4 E01E2E 0 +OP4 E01E2F 0 +OP4 E01E30 0 +OP4 E01E31 0 +OP4 E01E32 0 +OP4 E01E33 0 +OP4 E01E34 0 +OP4 E01E35 0 +OP4 E01E36 0 +OP4 E01E37 0 +OP4 E01E38 0 +OP4 E01E39 0 +OP4 E01E3A 0 +OP4 E01E3B 0 +OP4 E01E3C 0 +OP4 E01E3D 0 +OP4 E01E3E 0 +OP4 E01E3F 0 +OP4 E01E40 0 +OP4 E01E41 0 +OP4 E01E42 0 +OP4 E01E43 0 +OP4 E01E44 0 +OP4 E01E45 0 +OP4 E01E46 0 +OP4 E01E47 0 +OP4 E01E48 0 +OP4 E01E49 0 +OP4 E01E4A 0 +OP4 E01E4B 0 +OP4 E01E4C 0 +OP4 E01E4D 0 +OP4 E01E4E 0 +OP4 E01E4F 0 +OP4 E01E50 0 +OP4 E01E51 0 +OP4 E01E52 0 +OP4 E01E53 0 +OP4 E01E54 0 +OP4 E01E55 0 +OP4 E01E56 0 +OP4 E01E57 0 +OP4 E01E58 0 +OP4 E01E59 0 +OP4 E01E5A 0 +OP4 E01E5B 0 +OP4 E01E5C 0 +OP4 E01E5D 0 +OP4 E01E5E 0 +OP4 E01E5F 0 +OP4 E01E60 0 +OP4 E01E61 0 +OP4 E01E62 0 +OP4 E01E63 0 +OP4 E01E64 0 +OP4 E01E65 0 +OP4 E01E66 0 +OP4 E01E67 0 +OP4 E01E68 0 +OP4 E01E69 0 +OP4 E01E6A 0 +OP4 E01E6B 0 +OP4 E01E6C 0 +OP4 E01E6D 0 +OP4 E01E6E 0 +OP4 E01E6F 0 +OP4 E01E70 0 +OP4 E01E71 0 +OP4 E01E72 0 +OP4 E01E73 0 +OP4 E01E74 0 +OP4 E01E75 0 +OP4 E01E76 0 +OP4 E01E77 0 +OP4 E01E78 0 +OP4 E01E79 0 +OP4 E01E7A 0 +OP4 E01E7B 0 +OP4 E01E7C 0 +OP4 E01E7D 0 +OP4 E01E7E 0 +OP4 E01E7F 0 +OP4 E01E80 0 +OP4 E01E81 0 +OP4 E01E82 0 +OP4 E01E83 0 +OP4 E01E84 0 +OP4 E01E85 0 +OP4 E01E86 0 +OP4 E01E87 0 +OP4 E01E88 0 +OP4 E01E89 0 +OP4 E01E8A 0 +OP4 E01E8B 0 +OP4 E01E8C 0 +OP4 E01E8D 0 +OP4 E01E8E 0 +OP4 E01E8F 0 +OP4 E01E90 0 +OP4 E01E91 0 +OP4 E01E92 0 +OP4 E01E93 0 +OP4 E01E94 0 +OP4 E01E95 0 +OP4 E01E96 0 +OP4 E01E97 0 +OP4 E01E98 0 +OP4 E01E99 0 +OP4 E01E9A 0 +OP4 E01E9B 0 +OP4 E01E9C 0 +OP4 E01E9D 0 +OP4 E01E9E 0 +OP4 E01E9F 0 +OP4 E01EA0 0 +OP4 E01EA1 0 +OP4 E01EA2 0 +OP4 E01EA3 0 +OP4 E01EA4 0 +OP4 E01EA5 0 +OP4 E01EA6 0 +OP4 E01EA7 0 +OP4 E01EA8 0 +OP4 E01EA9 0 +OP4 E01EAA 0 +OP4 E01EAB 0 +OP4 E01EAC 0 +OP4 E01EAD 0 +OP4 E01EAE 0 +OP4 E01EAF 0 +OP4 E01EB0 0 +OP4 E01EB1 0 +OP4 E01EB2 0 +OP4 E01EB3 0 +OP4 E01EB4 0 +OP4 E01EB5 0 +OP4 E01EB6 0 +OP4 E01EB7 0 +OP4 E01EB8 0 +OP4 E01EB9 0 +OP4 E01EBA 0 +OP4 E01EBB 0 +OP4 E01EBC 0 +OP4 E01EBD 0 +OP4 E01EBE 0 +OP4 E01EBF 0 +OP4 E01EC0 0 +OP4 E01EC1 0 +OP4 E01EC2 0 +OP4 E01EC3 0 +OP4 E01EC4 0 +OP4 E01EC5 0 +OP4 E01EC6 0 +OP4 E01EC7 0 +OP4 E01EC8 0 +OP4 E01EC9 0 +OP4 E01ECA 0 +OP4 E01ECB 0 +OP4 E01ECC 0 +OP4 E01ECD 0 +OP4 E01ECE 0 +OP4 E01ECF 0 +OP4 E01ED0 0 +OP4 E01ED1 0 +OP4 E01ED2 0 +OP4 E01ED3 0 +OP4 E01ED4 0 +OP4 E01ED5 0 +OP4 E01ED6 0 +OP4 E01ED7 0 +OP4 E01ED8 0 +OP4 E01ED9 0 +OP4 E01EDA 0 +OP4 E01EDB 0 +OP4 E01EDC 0 +OP4 E01EDD 0 +OP4 E01EDE 0 +OP4 E01EDF 0 +OP4 E01EE0 0 +OP4 E01EE1 0 +OP4 E01EE2 0 +OP4 E01EE3 0 +OP4 E01EE4 0 +OP4 E01EE5 0 +OP4 E01EE6 0 +OP4 E01EE7 0 +OP4 E01EE8 0 +OP4 E01EE9 0 +OP4 E01EEA 0 +OP4 E01EEB 0 +OP4 E01EEC 0 +OP4 E01EED 0 +OP4 E01EEE 0 +OP4 E01EEF 0 +OP4 E01EF0 0 +OP4 E01EF1 0 +OP4 E01EF2 0 +OP4 E01EF3 0 +OP4 E01EF4 0 +OP4 E01EF5 0 +OP4 E01EF6 0 +OP4 E01EF7 0 +OP4 E01EF8 0 +OP4 E01EF9 0 +OP4 E01EFA 0 +OP4 E01EFB 0 +OP4 E01EFC 0 +OP4 E01EFD 0 +OP4 E01EFE 0 +OP4 E01EFF 0 +OP4 E01F00 0 +OP4 E01F01 0 +OP4 E01F02 0 +OP4 E01F03 0 +OP4 E01F04 0 +OP4 E01F05 0 +OP4 E01F06 0 +OP4 E01F07 0 +OP4 E01F08 0 +OP4 E01F09 0 +OP4 E01F0A 0 +OP4 E01F0B 0 +OP4 E01F0C 0 +OP4 E01F0D 0 +OP4 E01F0E 0 +OP4 E01F0F 0 +OP4 E01F10 0 +OP4 E01F11 0 +OP4 E01F12 0 +OP4 E01F13 0 +OP4 E01F14 0 +OP4 E01F15 0 +OP4 E01F16 0 +OP4 E01F17 0 +OP4 E01F18 0 +OP4 E01F19 0 +OP4 E01F1A 0 +OP4 E01F1B 0 +OP4 E01F1C 0 +OP4 E01F1D 0 +OP4 E01F1E 0 +OP4 E01F1F 0 +OP4 E01F20 0 +OP4 E01F21 0 +OP4 E01F22 0 +OP4 E01F23 0 +OP4 E01F24 0 +OP4 E01F25 0 +OP4 E01F26 0 +OP4 E01F27 0 +OP4 E01F28 0 +OP4 E01F29 0 +OP4 E01F2A 0 +OP4 E01F2B 0 +OP4 E01F2C 0 +OP4 E01F2D 0 +OP4 E01F2E 0 +OP4 E01F2F 0 +OP4 E01F30 0 +OP4 E01F31 0 +OP4 E01F32 0 +OP4 E01F33 0 +OP4 E01F34 0 +OP4 E01F35 0 +OP4 E01F36 0 +OP4 E01F37 0 +OP4 E01F38 0 +OP4 E01F39 0 +OP4 E01F3A 0 +OP4 E01F3B 0 +OP4 E01F3C 0 +OP4 E01F3D 0 +OP4 E01F3E 0 +OP4 E01F3F 0 +OP4 E01F40 0 +OP4 E01F41 0 +OP4 E01F42 0 +OP4 E01F43 0 +OP4 E01F44 0 +OP4 E01F45 0 +OP4 E01F46 0 +OP4 E01F47 0 +OP4 E01F48 0 +OP4 E01F49 0 +OP4 E01F4A 0 +OP4 E01F4B 0 +OP4 E01F4C 0 +OP4 E01F4D 0 +OP4 E01F4E 0 +OP4 E01F4F 0 +OP4 E01F50 0 +OP4 E01F51 0 +OP4 E01F52 0 +OP4 E01F53 0 +OP4 E01F54 0 +OP4 E01F55 0 +OP4 E01F56 0 +OP4 E01F57 0 +OP4 E01F58 0 +OP4 E01F59 0 +OP4 E01F5A 0 +OP4 E01F5B 0 +OP4 E01F5C 0 +OP4 E01F5D 0 +OP4 E01F5E 0 +OP4 E01F5F 0 +OP4 E01F60 0 +OP4 E01F61 0 +OP4 E01F62 0 +OP4 E01F63 0 +OP4 E01F64 0 +OP4 E01F65 0 +OP4 E01F66 0 +OP4 E01F67 0 +OP4 E01F68 0 +OP4 E01F69 0 +OP4 E01F6A 0 +OP4 E01F6B 0 +OP4 E01F6C 0 +OP4 E01F6D 0 +OP4 E01F6E 0 +OP4 E01F6F 0 +OP4 E01F70 0 +OP4 E01F71 0 +OP4 E01F72 0 +OP4 E01F73 0 +OP4 E01F74 0 +OP4 E01F75 0 +OP4 E01F76 0 +OP4 E01F77 0 +OP4 E01F78 0 +OP4 E01F79 0 +OP4 E01F7A 0 +OP4 E01F7B 0 +OP4 E01F7C 0 +OP4 E01F7D 0 +OP4 E01F7E 0 +OP4 E01F7F 0 +OP4 E01F80 0 +OP4 E01F81 0 +OP4 E01F82 0 +OP4 E01F83 0 +OP4 E01F84 0 +OP4 E01F85 0 +OP4 E01F86 0 +OP4 E01F87 0 +OP4 E01F88 0 +OP4 E01F89 0 +OP4 E01F8A 0 +OP4 E01F8B 0 +OP4 E01F8C 0 +OP4 E01F8D 0 +OP4 E01F8E 0 +OP4 E01F8F 0 +OP4 E01F90 0 +OP4 E01F91 0 +OP4 E01F92 0 +OP4 E01F93 0 +OP4 E01F94 0 +OP4 E01F95 0 +OP4 E01F96 0 +OP4 E01F97 0 +OP4 E01F98 0 +OP4 E01F99 0 +OP4 E01F9A 0 +OP4 E01F9B 0 +OP4 E01F9C 0 +OP4 E01F9D 0 +OP4 E01F9E 0 +OP4 E01F9F 0 +OP4 E01FA0 0 +OP4 E01FA1 0 +OP4 E01FA2 0 +OP4 E01FA3 0 +OP4 E01FA4 0 +OP4 E01FA5 0 +OP4 E01FA6 0 +OP4 E01FA7 0 +OP4 E01FA8 0 +OP4 E01FA9 0 +OP4 E01FAA 0 +OP4 E01FAB 0 +OP4 E01FAC 0 +OP4 E01FAD 0 +OP4 E01FAE 0 +OP4 E01FAF 0 +OP4 E01FB0 0 +OP4 E01FB1 0 +OP4 E01FB2 0 +OP4 E01FB3 0 +OP4 E01FB4 0 +OP4 E01FB5 0 +OP4 E01FB6 0 +OP4 E01FB7 0 +OP4 E01FB8 0 +OP4 E01FB9 0 +OP4 E01FBA 0 +OP4 E01FBB 0 +OP4 E01FBC 0 +OP4 E01FBD 0 +OP4 E01FBE 0 +OP4 E01FBF 0 +OP4 E01FC0 0 +OP4 E01FC1 0 +OP4 E01FC2 0 +OP4 E01FC3 0 +OP4 E01FC4 0 +OP4 E01FC5 0 +OP4 E01FC6 0 +OP4 E01FC7 0 +OP4 E01FC8 0 +OP4 E01FC9 0 +OP4 E01FCA 0 +OP4 E01FCB 0 +OP4 E01FCC 0 +OP4 E01FCD 0 +OP4 E01FCE 0 +OP4 E01FCF 0 +OP4 E01FD0 0 +OP4 E01FD1 0 +OP4 E01FD2 0 +OP4 E01FD3 0 +OP4 E01FD4 0 +OP4 E01FD5 0 +OP4 E01FD6 0 +OP4 E01FD7 0 +OP4 E01FD8 0 +OP4 E01FD9 0 +OP4 E01FDA 0 +OP4 E01FDB 0 +OP4 E01FDC 0 +OP4 E01FDD 0 +OP4 E01FDE 0 +OP4 E01FDF 0 +OP4 E01FE0 0 +OP4 E01FE1 0 +OP4 E01FE2 0 +OP4 E01FE3 0 +OP4 E01FE4 0 +OP4 E01FE5 0 +OP4 E01FE6 0 +OP4 E01FE7 0 +OP4 E01FE8 0 +OP4 E01FE9 0 +OP4 E01FEA 0 +OP4 E01FEB 0 +OP4 E01FEC 0 +OP4 E01FED 0 +OP4 E01FEE 0 +OP4 E01FEF 0 +OP4 E01FF0 0 +OP4 E01FF1 0 +OP4 E01FF2 0 +OP4 E01FF3 0 +OP4 E01FF4 0 +OP4 E01FF5 0 +OP4 E01FF6 0 +OP4 E01FF7 0 +OP4 E01FF8 0 +OP4 E01FF9 0 +OP4 E01FFA 0 +OP4 E01FFB 0 +OP4 E01FFC 0 +OP4 E01FFD 0 +OP4 E01FFE 0 +OP4 E01FFF 0 +OP4 E02000 0 +OP4 E02001 0 +OP4 E02002 0 +OP4 E02003 0 +OP4 E02004 0 +OP4 E02005 0 +OP4 E02006 0 +OP4 E02007 0 +OP4 E02008 0 +OP4 E02009 0 +OP4 E0200A 0 +OP4 E0200B 0 +OP4 E0200C 0 +OP4 E0200D 0 +OP4 E0200E 0 +OP4 E0200F 0 +OP4 E02010 0 +OP4 E02011 0 +OP4 E02012 0 +OP4 E02013 0 +OP4 E02014 0 +OP4 E02015 0 +OP4 E02016 0 +OP4 E02017 0 +OP4 E02018 0 +OP4 E02019 0 +OP4 E0201A 0 +OP4 E0201B 0 +OP4 E0201C 0 +OP4 E0201D 0 +OP4 E0201E 0 +OP4 E0201F 0 +OP4 E02020 0 +OP4 E02021 0 +OP4 E02022 0 +OP4 E02023 0 +OP4 E02024 0 +OP4 E02025 0 +OP4 E02026 0 +OP4 E02027 0 +OP4 E02028 0 +OP4 E02029 0 +OP4 E0202A 0 +OP4 E0202B 0 +OP4 E0202C 0 +OP4 E0202D 0 +OP4 E0202E 0 +OP4 E0202F 0 +OP4 E02030 0 +OP4 E02031 0 +OP4 E02032 0 +OP4 E02033 0 +OP4 E02034 0 +OP4 E02035 0 +OP4 E02036 0 +OP4 E02037 0 +OP4 E02038 0 +OP4 E02039 0 +OP4 E0203A 0 +OP4 E0203B 0 +OP4 E0203C 0 +OP4 E0203D 0 +OP4 E0203E 0 +OP4 E0203F 0 +OP4 E02040 0 +OP4 E02041 0 +OP4 E02042 0 +OP4 E02043 0 +OP4 E02044 0 +OP4 E02045 0 +OP4 E02046 0 +OP4 E02047 0 +OP4 E02048 0 +OP4 E02049 0 +OP4 E0204A 0 +OP4 E0204B 0 +OP4 E0204C 0 +OP4 E0204D 0 +OP4 E0204E 0 +OP4 E0204F 0 +OP4 E02050 0 +OP4 E02051 0 +OP4 E02052 0 +OP4 E02053 0 +OP4 E02054 0 +OP4 E02055 0 +OP4 E02056 0 +OP4 E02057 0 +OP4 E02058 0 +OP4 E02059 0 +OP4 E0205A 0 +OP4 E0205B 0 +OP4 E0205C 0 +OP4 E0205D 0 +OP4 E0205E 0 +OP4 E0205F 0 +OP4 E02060 0 +OP4 E02061 0 +OP4 E02062 0 +OP4 E02063 0 +OP4 E02064 0 +OP4 E02065 0 +OP4 E02066 0 +OP4 E02067 0 +OP4 E02068 0 +OP4 E02069 0 +OP4 E0206A 0 +OP4 E0206B 0 +OP4 E0206C 0 +OP4 E0206D 0 +OP4 E0206E 0 +OP4 E0206F 0 +OP4 E02070 0 +OP4 E02071 0 +OP4 E02072 0 +OP4 E02073 0 +OP4 E02074 0 +OP4 E02075 0 +OP4 E02076 0 +OP4 E02077 0 +OP4 E02078 0 +OP4 E02079 0 +OP4 E0207A 0 +OP4 E0207B 0 +OP4 E0207C 0 +OP4 E0207D 0 +OP4 E0207E 0 +OP4 E0207F 0 +OP4 E02080 0 +OP4 E02081 0 +OP4 E02082 0 +OP4 E02083 0 +OP4 E02084 0 +OP4 E02085 0 +OP4 E02086 0 +OP4 E02087 0 +OP4 E02088 0 +OP4 E02089 0 +OP4 E0208A 0 +OP4 E0208B 0 +OP4 E0208C 0 +OP4 E0208D 0 +OP4 E0208E 0 +OP4 E0208F 0 +OP4 E02090 0 +OP4 E02091 0 +OP4 E02092 0 +OP4 E02093 0 +OP4 E02094 0 +OP4 E02095 0 +OP4 E02096 0 +OP4 E02097 0 +OP4 E02098 0 +OP4 E02099 0 +OP4 E0209A 0 +OP4 E0209B 0 +OP4 E0209C 0 +OP4 E0209D 0 +OP4 E0209E 0 +OP4 E0209F 0 +OP4 E020A0 0 +OP4 E020A1 0 +OP4 E020A2 0 +OP4 E020A3 0 +OP4 E020A4 0 +OP4 E020A5 0 +OP4 E020A6 0 +OP4 E020A7 0 +OP4 E020A8 0 +OP4 E020A9 0 +OP4 E020AA 0 +OP4 E020AB 0 +OP4 E020AC 0 +OP4 E020AD 0 +OP4 E020AE 0 +OP4 E020AF 0 +OP4 E020B0 0 +OP4 E020B1 0 +OP4 E020B2 0 +OP4 E020B3 0 +OP4 E020B4 0 +OP4 E020B5 0 +OP4 E020B6 0 +OP4 E020B7 0 +OP4 E020B8 0 +OP4 E020B9 0 +OP4 E020BA 0 +OP4 E020BB 0 +OP4 E020BC 0 +OP4 E020BD 0 +OP4 E020BE 0 +OP4 E020BF 0 +OP4 E020C0 0 +OP4 E020C1 0 +OP4 E020C2 0 +OP4 E020C3 0 +OP4 E020C4 0 +OP4 E020C5 0 +OP4 E020C6 0 +OP4 E020C7 0 +OP4 E020C8 0 +OP4 E020C9 0 +OP4 E020CA 0 +OP4 E020CB 0 +OP4 E020CC 0 +OP4 E020CD 0 +OP4 E020CE 0 +OP4 E020CF 0 +OP4 E020D0 0 +OP4 E020D1 0 +OP4 E020D2 0 +OP4 E020D3 0 +OP4 E020D4 0 +OP4 E020D5 0 +OP4 E020D6 0 +OP4 E020D7 0 +OP4 E020D8 0 +OP4 E020D9 0 +OP4 E020DA 0 +OP4 E020DB 0 +OP4 E020DC 0 +OP4 E020DD 0 +OP4 E020DE 0 +OP4 E020DF 0 +OP4 E020E0 0 +OP4 E020E1 0 +OP4 E020E2 0 +OP4 E020E3 0 +OP4 E020E4 0 +OP4 E020E5 0 +OP4 E020E6 0 +OP4 E020E7 0 +OP4 E020E8 0 +OP4 E020E9 0 +OP4 E020EA 0 +OP4 E020EB 0 +OP4 E020EC 0 +OP4 E020ED 0 +OP4 E020EE 0 +OP4 E020EF 0 +OP4 E020F0 0 +OP4 E020F1 0 +OP4 E020F2 0 +OP4 E020F3 0 +OP4 E020F4 0 +OP4 E020F5 0 +OP4 E020F6 0 +OP4 E020F7 0 +OP4 E020F8 0 +OP4 E020F9 0 +OP4 E020FA 0 +OP4 E020FB 0 +OP4 E020FC 0 +OP4 E020FD 0 +OP4 E020FE 0 +OP4 E020FF 0 +OP4 E02100 0 +OP4 E02101 0 +OP4 E02102 0 +OP4 E02103 0 +OP4 E02104 0 +OP4 E02105 0 +OP4 E02106 0 +OP4 E02107 0 +OP4 E02108 0 +OP4 E02109 0 +OP4 E0210A 0 +OP4 E0210B 0 +OP4 E0210C 0 +OP4 E0210D 0 +OP4 E0210E 0 +OP4 E0210F 0 +OP4 E02110 0 +OP4 E02111 0 +OP4 E02112 0 +OP4 E02113 0 +OP4 E02114 0 +OP4 E02115 0 +OP4 E02116 0 +OP4 E02117 0 +OP4 E02118 0 +OP4 E02119 0 +OP4 E0211A 0 +OP4 E0211B 0 +OP4 E0211C 0 +OP4 E0211D 0 +OP4 E0211E 0 +OP4 E0211F 0 +OP4 E02120 0 +OP4 E02121 0 +OP4 E02122 0 +OP4 E02123 0 +OP4 E02124 0 +OP4 E02125 0 +OP4 E02126 0 +OP4 E02127 0 +OP4 E02128 0 +OP4 E02129 0 +OP4 E0212A 0 +OP4 E0212B 0 +OP4 E0212C 0 +OP4 E0212D 0 +OP4 E0212E 0 +OP4 E0212F 0 +OP4 E02130 0 +OP4 E02131 0 +OP4 E02132 0 +OP4 E02133 0 +OP4 E02134 0 +OP4 E02135 0 +OP4 E02136 0 +OP4 E02137 0 +OP4 E02138 0 +OP4 E02139 0 +OP4 E0213A 0 +OP4 E0213B 0 +OP4 E0213C 0 +OP4 E0213D 0 +OP4 E0213E 0 +OP4 E0213F 0 +OP4 E02140 0 +OP4 E02141 0 +OP4 E02142 0 +OP4 E02143 0 +OP4 E02144 0 +OP4 E02145 0 +OP4 E02146 0 +OP4 E02147 0 +OP4 E02148 0 +OP4 E02149 0 +OP4 E0214A 0 +OP4 E0214B 0 +OP4 E0214C 0 +OP4 E0214D 0 +OP4 E0214E 0 +OP4 E0214F 0 +OP4 E02150 0 +OP4 E02151 0 +OP4 E02152 0 +OP4 E02153 0 +OP4 E02154 0 +OP4 E02155 0 +OP4 E02156 0 +OP4 E02157 0 +OP4 E02158 0 +OP4 E02159 0 +OP4 E0215A 0 +OP4 E0215B 0 +OP4 E0215C 0 +OP4 E0215D 0 +OP4 E0215E 0 +OP4 E0215F 0 +OP4 E02160 0 +OP4 E02161 0 +OP4 E02162 0 +OP4 E02163 0 +OP4 E02164 0 +OP4 E02165 0 +OP4 E02166 0 +OP4 E02167 0 +OP4 E02168 0 +OP4 E02169 0 +OP4 E0216A 0 +OP4 E0216B 0 +OP4 E0216C 0 +OP4 E0216D 0 +OP4 E0216E 0 +OP4 E0216F 0 +OP4 E02170 0 +OP4 E02171 0 +OP4 E02172 0 +OP4 E02173 0 +OP4 E02174 0 +OP4 E02175 0 +OP4 E02176 0 +OP4 E02177 0 +OP4 E02178 0 +OP4 E02179 0 +OP4 E0217A 0 +OP4 E0217B 0 +OP4 E0217C 0 +OP4 E0217D 0 +OP4 E0217E 0 +OP4 E0217F 0 +OP4 E02180 0 +OP4 E02181 0 +OP4 E02182 0 +OP4 E02183 0 +OP4 E02184 0 +OP4 E02185 0 +OP4 E02186 0 +OP4 E02187 0 +OP4 E02188 0 +OP4 E02189 0 +OP4 E0218A 0 +OP4 E0218B 0 +OP4 E0218C 0 +OP4 E0218D 0 +OP4 E0218E 0 +OP4 E0218F 0 +OP4 E02190 0 +OP4 E02191 0 +OP4 E02192 0 +OP4 E02193 0 +OP4 E02194 0 +OP4 E02195 0 +OP4 E02196 0 +OP4 E02197 0 +OP4 E02198 0 +OP4 E02199 0 +OP4 E0219A 0 +OP4 E0219B 0 +OP4 E0219C 0 +OP4 E0219D 0 +OP4 E0219E 0 +OP4 E0219F 0 +OP4 E021A0 0 +OP4 E021A1 0 +OP4 E021A2 0 +OP4 E021A3 0 +OP4 E021A4 0 +OP4 E021A5 0 +OP4 E021A6 0 +OP4 E021A7 0 +OP4 E021A8 0 +OP4 E021A9 0 +OP4 E021AA 0 +OP4 E021AB 0 +OP4 E021AC 0 +OP4 E021AD 0 +OP4 E021AE 0 +OP4 E021AF 0 +OP4 E021B0 0 +OP4 E021B1 0 +OP4 E021B2 0 +OP4 E021B3 0 +OP4 E021B4 0 +OP4 E021B5 0 +OP4 E021B6 0 +OP4 E021B7 0 +OP4 E021B8 0 +OP4 E021B9 0 +OP4 E021BA 0 +OP4 E021BB 0 +OP4 E021BC 0 +OP4 E021BD 0 +OP4 E021BE 0 +OP4 E021BF 0 +OP4 E021C0 0 +OP4 E021C1 0 +OP4 E021C2 0 +OP4 E021C3 0 +OP4 E021C4 0 +OP4 E021C5 0 +OP4 E021C6 0 +OP4 E021C7 0 +OP4 E021C8 0 +OP4 E021C9 0 +OP4 E021CA 0 +OP4 E021CB 0 +OP4 E021CC 0 +OP4 E021CD 0 +OP4 E021CE 0 +OP4 E021CF 0 +OP4 E021D0 0 +OP4 E021D1 0 +OP4 E021D2 0 +OP4 E021D3 0 +OP4 E021D4 0 +OP4 E021D5 0 +OP4 E021D6 0 +OP4 E021D7 0 +OP4 E021D8 0 +OP4 E021D9 0 +OP4 E021DA 0 +OP4 E021DB 0 +OP4 E021DC 0 +OP4 E021DD 0 +OP4 E021DE 0 +OP4 E021DF 0 +OP4 E021E0 0 +OP4 E021E1 0 +OP4 E021E2 0 +OP4 E021E3 0 +OP4 E021E4 0 +OP4 E021E5 0 +OP4 E021E6 0 +OP4 E021E7 0 +OP4 E021E8 0 +OP4 E021E9 0 +OP4 E021EA 0 +OP4 E021EB 0 +OP4 E021EC 0 +OP4 E021ED 0 +OP4 E021EE 0 +OP4 E021EF 0 +OP4 E021F0 0 +OP4 E021F1 0 +OP4 E021F2 0 +OP4 E021F3 0 +OP4 E021F4 0 +OP4 E021F5 0 +OP4 E021F6 0 +OP4 E021F7 0 +OP4 E021F8 0 +OP4 E021F9 0 +OP4 E021FA 0 +OP4 E021FB 0 +OP4 E021FC 0 +OP4 E021FD 0 +OP4 E021FE 0 +OP4 E021FF 0 +OP4 E02200 0 +OP4 E02201 0 +OP4 E02202 0 +OP4 E02203 0 +OP4 E02204 0 +OP4 E02205 0 +OP4 E02206 0 +OP4 E02207 0 +OP4 E02208 0 +OP4 E02209 0 +OP4 E0220A 0 +OP4 E0220B 0 +OP4 E0220C 0 +OP4 E0220D 0 +OP4 E0220E 0 +OP4 E0220F 0 +OP4 E02210 0 +OP4 E02211 0 +OP4 E02212 0 +OP4 E02213 0 +OP4 E02214 0 +OP4 E02215 0 +OP4 E02216 0 +OP4 E02217 0 +OP4 E02218 0 +OP4 E02219 0 +OP4 E0221A 0 +OP4 E0221B 0 +OP4 E0221C 0 +OP4 E0221D 0 +OP4 E0221E 0 +OP4 E0221F 0 +OP4 E02220 0 +OP4 E02221 0 +OP4 E02222 0 +OP4 E02223 0 +OP4 E02224 0 +OP4 E02225 0 +OP4 E02226 0 +OP4 E02227 0 +OP4 E02228 0 +OP4 E02229 0 +OP4 E0222A 0 +OP4 E0222B 0 +OP4 E0222C 0 +OP4 E0222D 0 +OP4 E0222E 0 +OP4 E0222F 0 +OP4 E02230 0 +OP4 E02231 0 +OP4 E02232 0 +OP4 E02233 0 +OP4 E02234 0 +OP4 E02235 0 +OP4 E02236 0 +OP4 E02237 0 +OP4 E02238 0 +OP4 E02239 0 +OP4 E0223A 0 +OP4 E0223B 0 +OP4 E0223C 0 +OP4 E0223D 0 +OP4 E0223E 0 +OP4 E0223F 0 +OP4 E02240 0 +OP4 E02241 0 +OP4 E02242 0 +OP4 E02243 0 +OP4 E02244 0 +OP4 E02245 0 +OP4 E02246 0 +OP4 E02247 0 +OP4 E02248 0 +OP4 E02249 0 +OP4 E0224A 0 +OP4 E0224B 0 +OP4 E0224C 0 +OP4 E0224D 0 +OP4 E0224E 0 +OP4 E0224F 0 +OP4 E02250 0 +OP4 E02251 0 +OP4 E02252 0 +OP4 E02253 0 +OP4 E02254 0 +OP4 E02255 0 +OP4 E02256 0 +OP4 E02257 0 +OP4 E02258 0 +OP4 E02259 0 +OP4 E0225A 0 +OP4 E0225B 0 +OP4 E0225C 0 +OP4 E0225D 0 +OP4 E0225E 0 +OP4 E0225F 0 +OP4 E02260 0 +OP4 E02261 0 +OP4 E02262 0 +OP4 E02263 0 +OP4 E02264 0 +OP4 E02265 0 +OP4 E02266 0 +OP4 E02267 0 +OP4 E02268 0 +OP4 E02269 0 +OP4 E0226A 0 +OP4 E0226B 0 +OP4 E0226C 0 +OP4 E0226D 0 +OP4 E0226E 0 +OP4 E0226F 0 +OP4 E02270 0 +OP4 E02271 0 +OP4 E02272 0 +OP4 E02273 0 +OP4 E02274 0 +OP4 E02275 0 +OP4 E02276 0 +OP4 E02277 0 +OP4 E02278 0 +OP4 E02279 0 +OP4 E0227A 0 +OP4 E0227B 0 +OP4 E0227C 0 +OP4 E0227D 0 +OP4 E0227E 0 +OP4 E0227F 0 +OP4 E02280 0 +OP4 E02281 0 +OP4 E02282 0 +OP4 E02283 0 +OP4 E02284 0 +OP4 E02285 0 +OP4 E02286 0 +OP4 E02287 0 +OP4 E02288 0 +OP4 E02289 0 +OP4 E0228A 0 +OP4 E0228B 0 +OP4 E0228C 0 +OP4 E0228D 0 +OP4 E0228E 0 +OP4 E0228F 0 +OP4 E02290 0 +OP4 E02291 0 +OP4 E02292 0 +OP4 E02293 0 +OP4 E02294 0 +OP4 E02295 0 +OP4 E02296 0 +OP4 E02297 0 +OP4 E02298 0 +OP4 E02299 0 +OP4 E0229A 0 +OP4 E0229B 0 +OP4 E0229C 0 +OP4 E0229D 0 +OP4 E0229E 0 +OP4 E0229F 0 +OP4 E022A0 0 +OP4 E022A1 0 +OP4 E022A2 0 +OP4 E022A3 0 +OP4 E022A4 0 +OP4 E022A5 0 +OP4 E022A6 0 +OP4 E022A7 0 +OP4 E022A8 0 +OP4 E022A9 0 +OP4 E022AA 0 +OP4 E022AB 0 +OP4 E022AC 0 +OP4 E022AD 0 +OP4 E022AE 0 +OP4 E022AF 0 +OP4 E022B0 0 +OP4 E022B1 0 +OP4 E022B2 0 +OP4 E022B3 0 +OP4 E022B4 0 +OP4 E022B5 0 +OP4 E022B6 0 +OP4 E022B7 0 +OP4 E022B8 0 +OP4 E022B9 0 +OP4 E022BA 0 +OP4 E022BB 0 +OP4 E022BC 0 +OP4 E022BD 0 +OP4 E022BE 0 +OP4 E022BF 0 +OP4 E022C0 0 +OP4 E022C1 0 +OP4 E022C2 0 +OP4 E022C3 0 +OP4 E022C4 0 +OP4 E022C5 0 +OP4 E022C6 0 +OP4 E022C7 0 +OP4 E022C8 0 +OP4 E022C9 0 +OP4 E022CA 0 +OP4 E022CB 0 +OP4 E022CC 0 +OP4 E022CD 0 +OP4 E022CE 0 +OP4 E022CF 0 +OP4 E022D0 0 +OP4 E022D1 0 +OP4 E022D2 0 +OP4 E022D3 0 +OP4 E022D4 0 +OP4 E022D5 0 +OP4 E022D6 0 +OP4 E022D7 0 +OP4 E022D8 0 +OP4 E022D9 0 +OP4 E022DA 0 +OP4 E022DB 0 +OP4 E022DC 0 +OP4 E022DD 0 +OP4 E022DE 0 +OP4 E022DF 0 +OP4 E022E0 0 +OP4 E022E1 0 +OP4 E022E2 0 +OP4 E022E3 0 +OP4 E022E4 0 +OP4 E022E5 0 +OP4 E022E6 0 +OP4 E022E7 0 +OP4 E022E8 0 +OP4 E022E9 0 +OP4 E022EA 0 +OP4 E022EB 0 +OP4 E022EC 0 +OP4 E022ED 0 +OP4 E022EE 0 +OP4 E022EF 0 +OP4 E022F0 0 +OP4 E022F1 0 +OP4 E022F2 0 +OP4 E022F3 0 +OP4 E022F4 0 +OP4 E022F5 0 +OP4 E022F6 0 +OP4 E022F7 0 +OP4 E022F8 0 +OP4 E022F9 0 +OP4 E022FA 0 +OP4 E022FB 0 +OP4 E022FC 0 +OP4 E022FD 0 +OP4 E022FE 0 +OP4 E022FF 0 +OP4 E02300 0 +OP4 E02301 0 +OP4 E02302 0 +OP4 E02303 0 +OP4 E02304 0 +OP4 E02305 0 +OP4 E02306 0 +OP4 E02307 0 +OP4 E02308 0 +OP4 E02309 0 +OP4 E0230A 0 +OP4 E0230B 0 +OP4 E0230C 0 +OP4 E0230D 0 +OP4 E0230E 0 +OP4 E0230F 0 +OP4 E02310 0 +OP4 E02311 0 +OP4 E02312 0 +OP4 E02313 0 +OP4 E02314 0 +OP4 E02315 0 +OP4 E02316 0 +OP4 E02317 0 +OP4 E02318 0 +OP4 E02319 0 +OP4 E0231A 0 +OP4 E0231B 0 +OP4 E0231C 0 +OP4 E0231D 0 +OP4 E0231E 0 +OP4 E0231F 0 +OP4 E02320 0 +OP4 E02321 0 +OP4 E02322 0 +OP4 E02323 0 +OP4 E02324 0 +OP4 E02325 0 +OP4 E02326 0 +OP4 E02327 0 +OP4 E02328 0 +OP4 E02329 0 +OP4 E0232A 0 +OP4 E0232B 0 +OP4 E0232C 0 +OP4 E0232D 0 +OP4 E0232E 0 +OP4 E0232F 0 +OP4 E02330 0 +OP4 E02331 0 +OP4 E02332 0 +OP4 E02333 0 +OP4 E02334 0 +OP4 E02335 0 +OP4 E02336 0 +OP4 E02337 0 +OP4 E02338 0 +OP4 E02339 0 +OP4 E0233A 0 +OP4 E0233B 0 +OP4 E0233C 0 +OP4 E0233D 0 +OP4 E0233E 0 +OP4 E0233F 0 +OP4 E02340 0 +OP4 E02341 0 +OP4 E02342 0 +OP4 E02343 0 +OP4 E02344 0 +OP4 E02345 0 +OP4 E02346 0 +OP4 E02347 0 +OP4 E02348 0 +OP4 E02349 0 +OP4 E0234A 0 +OP4 E0234B 0 +OP4 E0234C 0 +OP4 E0234D 0 +OP4 E0234E 0 +OP4 E0234F 0 +OP4 E02350 0 +OP4 E02351 0 +OP4 E02352 0 +OP4 E02353 0 +OP4 E02354 0 +OP4 E02355 0 +OP4 E02356 0 +OP4 E02357 0 +OP4 E02358 0 +OP4 E02359 0 +OP4 E0235A 0 +OP4 E0235B 0 +OP4 E0235C 0 +OP4 E0235D 0 +OP4 E0235E 0 +OP4 E0235F 0 +OP4 E02360 0 +OP4 E02361 0 +OP4 E02362 0 +OP4 E02363 0 +OP4 E02364 0 +OP4 E02365 0 +OP4 E02366 0 +OP4 E02367 0 +OP4 E02368 0 +OP4 E02369 0 +OP4 E0236A 0 +OP4 E0236B 0 +OP4 E0236C 0 +OP4 E0236D 0 +OP4 E0236E 0 +OP4 E0236F 0 +OP4 E02370 0 +OP4 E02371 0 +OP4 E02372 0 +OP4 E02373 0 +OP4 E02374 0 +OP4 E02375 0 +OP4 E02376 0 +OP4 E02377 0 +OP4 E02378 0 +OP4 E02379 0 +OP4 E0237A 0 +OP4 E0237B 0 +OP4 E0237C 0 +OP4 E0237D 0 +OP4 E0237E 0 +OP4 E0237F 0 +OP4 E02380 0 +OP4 E02381 0 +OP4 E02382 0 +OP4 E02383 0 +OP4 E02384 0 +OP4 E02385 0 +OP4 E02386 0 +OP4 E02387 0 +OP4 E02388 0 +OP4 E02389 0 +OP4 E0238A 0 +OP4 E0238B 0 +OP4 E0238C 0 +OP4 E0238D 0 +OP4 E0238E 0 +OP4 E0238F 0 +OP4 E02390 0 +OP4 E02391 0 +OP4 E02392 0 +OP4 E02393 0 +OP4 E02394 0 +OP4 E02395 0 +OP4 E02396 0 +OP4 E02397 0 +OP4 E02398 0 +OP4 E02399 0 +OP4 E0239A 0 +OP4 E0239B 0 +OP4 E0239C 0 +OP4 E0239D 0 +OP4 E0239E 0 +OP4 E0239F 0 +OP4 E023A0 0 +OP4 E023A1 0 +OP4 E023A2 0 +OP4 E023A3 0 +OP4 E023A4 0 +OP4 E023A5 0 +OP4 E023A6 0 +OP4 E023A7 0 +OP4 E023A8 0 +OP4 E023A9 0 +OP4 E023AA 0 +OP4 E023AB 0 +OP4 E023AC 0 +OP4 E023AD 0 +OP4 E023AE 0 +OP4 E023AF 0 +OP4 E023B0 0 +OP4 E023B1 0 +OP4 E023B2 0 +OP4 E023B3 0 +OP4 E023B4 0 +OP4 E023B5 0 +OP4 E023B6 0 +OP4 E023B7 0 +OP4 E023B8 0 +OP4 E023B9 0 +OP4 E023BA 0 +OP4 E023BB 0 +OP4 E023BC 0 +OP4 E023BD 0 +OP4 E023BE 0 +OP4 E023BF 0 +OP4 E023C0 0 +OP4 E023C1 0 +OP4 E023C2 0 +OP4 E023C3 0 +OP4 E023C4 0 +OP4 E023C5 0 +OP4 E023C6 0 +OP4 E023C7 0 +OP4 E023C8 0 +OP4 E023C9 0 +OP4 E023CA 0 +OP4 E023CB 0 +OP4 E023CC 0 +OP4 E023CD 0 +OP4 E023CE 0 +OP4 E023CF 0 +OP4 E023D0 0 +OP4 E023D1 0 +OP4 E023D2 0 +OP4 E023D3 0 +OP4 E023D4 0 +OP4 E023D5 0 +OP4 E023D6 0 +OP4 E023D7 0 +OP4 E023D8 0 +OP4 E023D9 0 +OP4 E023DA 0 +OP4 E023DB 0 +OP4 E023DC 0 +OP4 E023DD 0 +OP4 E023DE 0 +OP4 E023DF 0 +OP4 E023E0 0 +OP4 E023E1 0 +OP4 E023E2 0 +OP4 E023E3 0 +OP4 E023E4 0 +OP4 E023E5 0 +OP4 E023E6 0 +OP4 E023E7 0 +OP4 E023E8 0 +OP4 E023E9 0 +OP4 E023EA 0 +OP4 E023EB 0 +OP4 E023EC 0 +OP4 E023ED 0 +OP4 E023EE 0 +OP4 E023EF 0 +OP4 E023F0 0 +OP4 E023F1 0 +OP4 E023F2 0 +OP4 E023F3 0 +OP4 E023F4 0 +OP4 E023F5 0 +OP4 E023F6 0 +OP4 E023F7 0 +OP4 E023F8 0 +OP4 E023F9 0 +OP4 E023FA 0 +OP4 E023FB 0 +OP4 E023FC 0 +OP4 E023FD 0 +OP4 E023FE 0 +OP4 E023FF 0 +OP4 E02400 0 +OP4 E02401 0 +OP4 E02402 0 +OP4 E02403 0 +OP4 E02404 0 +OP4 E02405 0 +OP4 E02406 0 +OP4 E02407 0 +OP4 E02408 0 +OP4 E02409 0 +OP4 E0240A 0 +OP4 E0240B 0 +OP4 E0240C 0 +OP4 E0240D 0 +OP4 E0240E 0 +OP4 E0240F 0 +OP4 E02410 0 +OP4 E02411 0 +OP4 E02412 0 +OP4 E02413 0 +OP4 E02414 0 +OP4 E02415 0 +OP4 E02416 0 +OP4 E02417 0 +OP4 E02418 0 +OP4 E02419 0 +OP4 E0241A 0 +OP4 E0241B 0 +OP4 E0241C 0 +OP4 E0241D 0 +OP4 E0241E 0 +OP4 E0241F 0 +OP4 E02420 0 +OP4 E02421 0 +OP4 E02422 0 +OP4 E02423 0 +OP4 E02424 0 +OP4 E02425 0 +OP4 E02426 0 +OP4 E02427 0 +OP4 E02428 0 +OP4 E02429 0 +OP4 E0242A 0 +OP4 E0242B 0 +OP4 E0242C 0 +OP4 E0242D 0 +OP4 E0242E 0 +OP4 E0242F 0 +OP4 E02430 0 +OP4 E02431 0 +OP4 E02432 0 +OP4 E02433 0 +OP4 E02434 0 +OP4 E02435 0 +OP4 E02436 0 +OP4 E02437 0 +OP4 E02438 0 +OP4 E02439 0 +OP4 E0243A 0 +OP4 E0243B 0 +OP4 E0243C 0 +OP4 E0243D 0 +OP4 E0243E 0 +OP4 E0243F 0 +OP4 E02440 0 +OP4 E02441 0 +OP4 E02442 0 +OP4 E02443 0 +OP4 E02444 0 +OP4 E02445 0 +OP4 E02446 0 +OP4 E02447 0 +OP4 E02448 0 +OP4 E02449 0 +OP4 E0244A 0 +OP4 E0244B 0 +OP4 E0244C 0 +OP4 E0244D 0 +OP4 E0244E 0 +OP4 E0244F 0 +OP4 E02450 0 +OP4 E02451 0 +OP4 E02452 0 +OP4 E02453 0 +OP4 E02454 0 +OP4 E02455 0 +OP4 E02456 0 +OP4 E02457 0 +OP4 E02458 0 +OP4 E02459 0 +OP4 E0245A 0 +OP4 E0245B 0 +OP4 E0245C 0 +OP4 E0245D 0 +OP4 E0245E 0 +OP4 E0245F 0 +OP4 E02460 0 +OP4 E02461 0 +OP4 E02462 0 +OP4 E02463 0 +OP4 E02464 0 +OP4 E02465 0 +OP4 E02466 0 +OP4 E02467 0 +OP4 E02468 0 +OP4 E02469 0 +OP4 E0246A 0 +OP4 E0246B 0 +OP4 E0246C 0 +OP4 E0246D 0 +OP4 E0246E 0 +OP4 E0246F 0 +OP4 E02470 0 +OP4 E02471 0 +OP4 E02472 0 +OP4 E02473 0 +OP4 E02474 0 +OP4 E02475 0 +OP4 E02476 0 +OP4 E02477 0 +OP4 E02478 0 +OP4 E02479 0 +OP4 E0247A 0 +OP4 E0247B 0 +OP4 E0247C 0 +OP4 E0247D 0 +OP4 E0247E 0 +OP4 E0247F 0 +OP4 E02480 0 +OP4 E02481 0 +OP4 E02482 0 +OP4 E02483 0 +OP4 E02484 0 +OP4 E02485 0 +OP4 E02486 0 +OP4 E02487 0 +OP4 E02488 0 +OP4 E02489 0 +OP4 E0248A 0 +OP4 E0248B 0 +OP4 E0248C 0 +OP4 E0248D 0 +OP4 E0248E 0 +OP4 E0248F 0 +OP4 E02490 0 +OP4 E02491 0 +OP4 E02492 0 +OP4 E02493 0 +OP4 E02494 0 +OP4 E02495 0 +OP4 E02496 0 +OP4 E02497 0 +OP4 E02498 0 +OP4 E02499 0 +OP4 E0249A 0 +OP4 E0249B 0 +OP4 E0249C 0 +OP4 E0249D 0 +OP4 E0249E 0 +OP4 E0249F 0 +OP4 E024A0 0 +OP4 E024A1 0 +OP4 E024A2 0 +OP4 E024A3 0 +OP4 E024A4 0 +OP4 E024A5 0 +OP4 E024A6 0 +OP4 E024A7 0 +OP4 E024A8 0 +OP4 E024A9 0 +OP4 E024AA 0 +OP4 E024AB 0 +OP4 E024AC 0 +OP4 E024AD 0 +OP4 E024AE 0 +OP4 E024AF 0 +OP4 E024B0 0 +OP4 E024B1 0 +OP4 E024B2 0 +OP4 E024B3 0 +OP4 E024B4 0 +OP4 E024B5 0 +OP4 E024B6 0 +OP4 E024B7 0 +OP4 E024B8 0 +OP4 E024B9 0 +OP4 E024BA 0 +OP4 E024BB 0 +OP4 E024BC 0 +OP4 E024BD 0 +OP4 E024BE 0 +OP4 E024BF 0 +OP4 E024C0 0 +OP4 E024C1 0 +OP4 E024C2 0 +OP4 E024C3 0 +OP4 E024C4 0 +OP4 E024C5 0 +OP4 E024C6 0 +OP4 E024C7 0 +OP4 E024C8 0 +OP4 E024C9 0 +OP4 E024CA 0 +OP4 E024CB 0 +OP4 E024CC 0 +OP4 E024CD 0 +OP4 E024CE 0 +OP4 E024CF 0 +OP4 E024D0 0 +OP4 E024D1 0 +OP4 E024D2 0 +OP4 E024D3 0 +OP4 E024D4 0 +OP4 E024D5 0 +OP4 E024D6 0 +OP4 E024D7 0 +OP4 E024D8 0 +OP4 E024D9 0 +OP4 E024DA 0 +OP4 E024DB 0 +OP4 E024DC 0 +OP4 E024DD 0 +OP4 E024DE 0 +OP4 E024DF 0 +OP4 E024E0 0 +OP4 E024E1 0 +OP4 E024E2 0 +OP4 E024E3 0 +OP4 E024E4 0 +OP4 E024E5 0 +OP4 E024E6 0 +OP4 E024E7 0 +OP4 E024E8 0 +OP4 E024E9 0 +OP4 E024EA 0 +OP4 E024EB 0 +OP4 E024EC 0 +OP4 E024ED 0 +OP4 E024EE 0 +OP4 E024EF 0 +OP4 E024F0 0 +OP4 E024F1 0 +OP4 E024F2 0 +OP4 E024F3 0 +OP4 E024F4 0 +OP4 E024F5 0 +OP4 E024F6 0 +OP4 E024F7 0 +OP4 E024F8 0 +OP4 E024F9 0 +OP4 E024FA 0 +OP4 E024FB 0 +OP4 E024FC 0 +OP4 E024FD 0 +OP4 E024FE 0 +OP4 E024FF 0 +OP4 E02500 0 +OP4 E02501 0 +OP4 E02502 0 +OP4 E02503 0 +OP4 E02504 0 +OP4 E02505 0 +OP4 E02506 0 +OP4 E02507 0 +OP4 E02508 0 +OP4 E02509 0 +OP4 E0250A 0 +OP4 E0250B 0 +OP4 E0250C 0 +OP4 E0250D 0 +OP4 E0250E 0 +OP4 E0250F 0 +OP4 E02510 0 +OP4 E02511 0 +OP4 E02512 0 +OP4 E02513 0 +OP4 E02514 0 +OP4 E02515 0 +OP4 E02516 0 +OP4 E02517 0 +OP4 E02518 0 +OP4 E02519 0 +OP4 E0251A 0 +OP4 E0251B 0 +OP4 E0251C 0 +OP4 E0251D 0 +OP4 E0251E 0 +OP4 E0251F 0 +OP4 E02520 0 +OP4 E02521 0 +OP4 E02522 0 +OP4 E02523 0 +OP4 E02524 0 +OP4 E02525 0 +OP4 E02526 0 +OP4 E02527 0 +OP4 E02528 0 +OP4 E02529 0 +OP4 E0252A 0 +OP4 E0252B 0 +OP4 E0252C 0 +OP4 E0252D 0 +OP4 E0252E 0 +OP4 E0252F 0 +OP4 E02530 0 +OP4 E02531 0 +OP4 E02532 0 +OP4 E02533 0 +OP4 E02534 0 +OP4 E02535 0 +OP4 E02536 0 +OP4 E02537 0 +OP4 E02538 0 +OP4 E02539 0 +OP4 E0253A 0 +OP4 E0253B 0 +OP4 E0253C 0 +OP4 E0253D 0 +OP4 E0253E 0 +OP4 E0253F 0 +OP4 E02540 0 +OP4 E02541 0 +OP4 E02542 0 +OP4 E02543 0 +OP4 E02544 0 +OP4 E02545 0 +OP4 E02546 0 +OP4 E02547 0 +OP4 E02548 0 +OP4 E02549 0 +OP4 E0254A 0 +OP4 E0254B 0 +OP4 E0254C 0 +OP4 E0254D 0 +OP4 E0254E 0 +OP4 E0254F 0 +OP4 E02550 0 +OP4 E02551 0 +OP4 E02552 0 +OP4 E02553 0 +OP4 E02554 0 +OP4 E02555 0 +OP4 E02556 0 +OP4 E02557 0 +OP4 E02558 0 +OP4 E02559 0 +OP4 E0255A 0 +OP4 E0255B 0 +OP4 E0255C 0 +OP4 E0255D 0 +OP4 E0255E 0 +OP4 E0255F 0 +OP4 E02560 0 +OP4 E02561 0 +OP4 E02562 0 +OP4 E02563 0 +OP4 E02564 0 +OP4 E02565 0 +OP4 E02566 0 +OP4 E02567 0 +OP4 E02568 0 +OP4 E02569 0 +OP4 E0256A 0 +OP4 E0256B 0 +OP4 E0256C 0 +OP4 E0256D 0 +OP4 E0256E 0 +OP4 E0256F 0 +OP4 E02570 0 +OP4 E02571 0 +OP4 E02572 0 +OP4 E02573 0 +OP4 E02574 0 +OP4 E02575 0 +OP4 E02576 0 +OP4 E02577 0 +OP4 E02578 0 +OP4 E02579 0 +OP4 E0257A 0 +OP4 E0257B 0 +OP4 E0257C 0 +OP4 E0257D 0 +OP4 E0257E 0 +OP4 E0257F 0 +OP4 E02580 0 +OP4 E02581 0 +OP4 E02582 0 +OP4 E02583 0 +OP4 E02584 0 +OP4 E02585 0 +OP4 E02586 0 +OP4 E02587 0 +OP4 E02588 0 +OP4 E02589 0 +OP4 E0258A 0 +OP4 E0258B 0 +OP4 E0258C 0 +OP4 E0258D 0 +OP4 E0258E 0 +OP4 E0258F 0 +OP4 E02590 0 +OP4 E02591 0 +OP4 E02592 0 +OP4 E02593 0 +OP4 E02594 0 +OP4 E02595 0 +OP4 E02596 0 +OP4 E02597 0 +OP4 E02598 0 +OP4 E02599 0 +OP4 E0259A 0 +OP4 E0259B 0 +OP4 E0259C 0 +OP4 E0259D 0 +OP4 E0259E 0 +OP4 E0259F 0 +OP4 E025A0 0 +OP4 E025A1 0 +OP4 E025A2 0 +OP4 E025A3 0 +OP4 E025A4 0 +OP4 E025A5 0 +OP4 E025A6 0 +OP4 E025A7 0 +OP4 E025A8 0 +OP4 E025A9 0 +OP4 E025AA 0 +OP4 E025AB 0 +OP4 E025AC 0 +OP4 E025AD 0 +OP4 E025AE 0 +OP4 E025AF 0 +OP4 E025B0 0 +OP4 E025B1 0 +OP4 E025B2 0 +OP4 E025B3 0 +OP4 E025B4 0 +OP4 E025B5 0 +OP4 E025B6 0 +OP4 E025B7 0 +OP4 E025B8 0 +OP4 E025B9 0 +OP4 E025BA 0 +OP4 E025BB 0 +OP4 E025BC 0 +OP4 E025BD 0 +OP4 E025BE 0 +OP4 E025BF 0 +OP4 E025C0 0 +OP4 E025C1 0 +OP4 E025C2 0 +OP4 E025C3 0 +OP4 E025C4 0 +OP4 E025C5 0 +OP4 E025C6 0 +OP4 E025C7 0 +OP4 E025C8 0 +OP4 E025C9 0 +OP4 E025CA 0 +OP4 E025CB 0 +OP4 E025CC 0 +OP4 E025CD 0 +OP4 E025CE 0 +OP4 E025CF 0 +OP4 E025D0 0 +OP4 E025D1 0 +OP4 E025D2 0 +OP4 E025D3 0 +OP4 E025D4 0 +OP4 E025D5 0 +OP4 E025D6 0 +OP4 E025D7 0 +OP4 E025D8 0 +OP4 E025D9 0 +OP4 E025DA 0 +OP4 E025DB 0 +OP4 E025DC 0 +OP4 E025DD 0 +OP4 E025DE 0 +OP4 E025DF 0 +OP4 E025E0 0 +OP4 E025E1 0 +OP4 E025E2 0 +OP4 E025E3 0 +OP4 E025E4 0 +OP4 E025E5 0 +OP4 E025E6 0 +OP4 E025E7 0 +OP4 E025E8 0 +OP4 E025E9 0 +OP4 E025EA 0 +OP4 E025EB 0 +OP4 E025EC 0 +OP4 E025ED 0 +OP4 E025EE 0 +OP4 E025EF 0 +OP4 E025F0 0 +OP4 E025F1 0 +OP4 E025F2 0 +OP4 E025F3 0 +OP4 E025F4 0 +OP4 E025F5 0 +OP4 E025F6 0 +OP4 E025F7 0 +OP4 E025F8 0 +OP4 E025F9 0 +OP4 E025FA 0 +OP4 E025FB 0 +OP4 E025FC 0 +OP4 E025FD 0 +OP4 E025FE 0 +OP4 E025FF 0 +OP4 E02600 0 +OP4 E02601 0 +OP4 E02602 0 +OP4 E02603 0 +OP4 E02604 0 +OP4 E02605 0 +OP4 E02606 0 +OP4 E02607 0 +OP4 E02608 0 +OP4 E02609 0 +OP4 E0260A 0 +OP4 E0260B 0 +OP4 E0260C 0 +OP4 E0260D 0 +OP4 E0260E 0 +OP4 E0260F 0 +OP4 E02610 0 +OP4 E02611 0 +OP4 E02612 0 +OP4 E02613 0 +OP4 E02614 0 +OP4 E02615 0 +OP4 E02616 0 +OP4 E02617 0 +OP4 E02618 0 +OP4 E02619 0 +OP4 E0261A 0 +OP4 E0261B 0 +OP4 E0261C 0 +OP4 E0261D 0 +OP4 E0261E 0 +OP4 E0261F 0 +OP4 E02620 0 +OP4 E02621 0 +OP4 E02622 0 +OP4 E02623 0 +OP4 E02624 0 +OP4 E02625 0 +OP4 E02626 0 +OP4 E02627 0 +OP4 E02628 0 +OP4 E02629 0 +OP4 E0262A 0 +OP4 E0262B 0 +OP4 E0262C 0 +OP4 E0262D 0 +OP4 E0262E 0 +OP4 E0262F 0 +OP4 E02630 0 +OP4 E02631 0 +OP4 E02632 0 +OP4 E02633 0 +OP4 E02634 0 +OP4 E02635 0 +OP4 E02636 0 +OP4 E02637 0 +OP4 E02638 0 +OP4 E02639 0 +OP4 E0263A 0 +OP4 E0263B 0 +OP4 E0263C 0 +OP4 E0263D 0 +OP4 E0263E 0 +OP4 E0263F 0 +OP4 E02640 0 +OP4 E02641 0 +OP4 E02642 0 +OP4 E02643 0 +OP4 E02644 0 +OP4 E02645 0 +OP4 E02646 0 +OP4 E02647 0 +OP4 E02648 0 +OP4 E02649 0 +OP4 E0264A 0 +OP4 E0264B 0 +OP4 E0264C 0 +OP4 E0264D 0 +OP4 E0264E 0 +OP4 E0264F 0 +OP4 E02650 0 +OP4 E02651 0 +OP4 E02652 0 +OP4 E02653 0 +OP4 E02654 0 +OP4 E02655 0 +OP4 E02656 0 +OP4 E02657 0 +OP4 E02658 0 +OP4 E02659 0 +OP4 E0265A 0 +OP4 E0265B 0 +OP4 E0265C 0 +OP4 E0265D 0 +OP4 E0265E 0 +OP4 E0265F 0 +OP4 E02660 0 +OP4 E02661 0 +OP4 E02662 0 +OP4 E02663 0 +OP4 E02664 0 +OP4 E02665 0 +OP4 E02666 0 +OP4 E02667 0 +OP4 E02668 0 +OP4 E02669 0 +OP4 E0266A 0 +OP4 E0266B 0 +OP4 E0266C 0 +OP4 E0266D 0 +OP4 E0266E 0 +OP4 E0266F 0 +OP4 E02670 0 +OP4 E02671 0 +OP4 E02672 0 +OP4 E02673 0 +OP4 E02674 0 +OP4 E02675 0 +OP4 E02676 0 +OP4 E02677 0 +OP4 E02678 0 +OP4 E02679 0 +OP4 E0267A 0 +OP4 E0267B 0 +OP4 E0267C 0 +OP4 E0267D 0 +OP4 E0267E 0 +OP4 E0267F 0 +OP4 E02680 0 +OP4 E02681 0 +OP4 E02682 0 +OP4 E02683 0 +OP4 E02684 0 +OP4 E02685 0 +OP4 E02686 0 +OP4 E02687 0 +OP4 E02688 0 +OP4 E02689 0 +OP4 E0268A 0 +OP4 E0268B 0 +OP4 E0268C 0 +OP4 E0268D 0 +OP4 E0268E 0 +OP4 E0268F 0 +OP4 E02690 0 +OP4 E02691 0 +OP4 E02692 0 +OP4 E02693 0 +OP4 E02694 0 +OP4 E02695 0 +OP4 E02696 0 +OP4 E02697 0 +OP4 E02698 0 +OP4 E02699 0 +OP4 E0269A 0 +OP4 E0269B 0 +OP4 E0269C 0 +OP4 E0269D 0 +OP4 E0269E 0 +OP4 E0269F 0 +OP4 E026A0 0 +OP4 E026A1 0 +OP4 E026A2 0 +OP4 E026A3 0 +OP4 E026A4 0 +OP4 E026A5 0 +OP4 E026A6 0 +OP4 E026A7 0 +OP4 E026A8 0 +OP4 E026A9 0 +OP4 E026AA 0 +OP4 E026AB 0 +OP4 E026AC 0 +OP4 E026AD 0 +OP4 E026AE 0 +OP4 E026AF 0 +OP4 E026B0 0 +OP4 E026B1 0 +OP4 E026B2 0 +OP4 E026B3 0 +OP4 E026B4 0 +OP4 E026B5 0 +OP4 E026B6 0 +OP4 E026B7 0 +OP4 E026B8 0 +OP4 E026B9 0 +OP4 E026BA 0 +OP4 E026BB 0 +OP4 E026BC 0 +OP4 E026BD 0 +OP4 E026BE 0 +OP4 E026BF 0 +OP4 E026C0 0 +OP4 E026C1 0 +OP4 E026C2 0 +OP4 E026C3 0 +OP4 E026C4 0 +OP4 E026C5 0 +OP4 E026C6 0 +OP4 E026C7 0 +OP4 E026C8 0 +OP4 E026C9 0 +OP4 E026CA 0 +OP4 E026CB 0 +OP4 E026CC 0 +OP4 E026CD 0 +OP4 E026CE 0 +OP4 E026CF 0 +OP4 E026D0 0 +OP4 E026D1 0 +OP4 E026D2 0 +OP4 E026D3 0 +OP4 E026D4 0 +OP4 E026D5 0 +OP4 E026D6 0 +OP4 E026D7 0 +OP4 E026D8 0 +OP4 E026D9 0 +OP4 E026DA 0 +OP4 E026DB 0 +OP4 E026DC 0 +OP4 E026DD 0 +OP4 E026DE 0 +OP4 E026DF 0 +OP4 E026E0 0 +OP4 E026E1 0 +OP4 E026E2 0 +OP4 E026E3 0 +OP4 E026E4 0 +OP4 E026E5 0 +OP4 E026E6 0 +OP4 E026E7 0 +OP4 E026E8 0 +OP4 E026E9 0 +OP4 E026EA 0 +OP4 E026EB 0 +OP4 E026EC 0 +OP4 E026ED 0 +OP4 E026EE 0 +OP4 E026EF 0 +OP4 E026F0 0 +OP4 E026F1 0 +OP4 E026F2 0 +OP4 E026F3 0 +OP4 E026F4 0 +OP4 E026F5 0 +OP4 E026F6 0 +OP4 E026F7 0 +OP4 E026F8 0 +OP4 E026F9 0 +OP4 E026FA 0 +OP4 E026FB 0 +OP4 E026FC 0 +OP4 E026FD 0 +OP4 E026FE 0 +OP4 E026FF 0 +OP4 E02700 0 +OP4 E02701 0 +OP4 E02702 0 +OP4 E02703 0 +OP4 E02704 0 +OP4 E02705 0 +OP4 E02706 0 +OP4 E02707 0 +OP4 E02708 0 +OP4 E02709 0 +OP4 E0270A 0 +OP4 E0270B 0 +OP4 E0270C 0 +OP4 E0270D 0 +OP4 E0270E 0 +OP4 E0270F 0 +OP4 E02710 0 +OP4 E02711 0 +OP4 E02712 0 +OP4 E02713 0 +OP4 E02714 0 +OP4 E02715 0 +OP4 E02716 0 +OP4 E02717 0 +OP4 E02718 0 +OP4 E02719 0 +OP4 E0271A 0 +OP4 E0271B 0 +OP4 E0271C 0 +OP4 E0271D 0 +OP4 E0271E 0 +OP4 E0271F 0 +OP4 E02720 0 +OP4 E02721 0 +OP4 E02722 0 +OP4 E02723 0 +OP4 E02724 0 +OP4 E02725 0 +OP4 E02726 0 +OP4 E02727 0 +OP4 E02728 0 +OP4 E02729 0 +OP4 E0272A 0 +OP4 E0272B 0 +OP4 E0272C 0 +OP4 E0272D 0 +OP4 E0272E 0 +OP4 E0272F 0 +OP4 E02730 0 +OP4 E02731 0 +OP4 E02732 0 +OP4 E02733 0 +OP4 E02734 0 +OP4 E02735 0 +OP4 E02736 0 +OP4 E02737 0 +OP4 E02738 0 +OP4 E02739 0 +OP4 E0273A 0 +OP4 E0273B 0 +OP4 E0273C 0 +OP4 E0273D 0 +OP4 E0273E 0 +OP4 E0273F 0 +OP4 E02740 0 +OP4 E02741 0 +OP4 E02742 0 +OP4 E02743 0 +OP4 E02744 0 +OP4 E02745 0 +OP4 E02746 0 +OP4 E02747 0 +OP4 E02748 0 +OP4 E02749 0 +OP4 E0274A 0 +OP4 E0274B 0 +OP4 E0274C 0 +OP4 E0274D 0 +OP4 E0274E 0 +OP4 E0274F 0 +OP4 E02750 0 +OP4 E02751 0 +OP4 E02752 0 +OP4 E02753 0 +OP4 E02754 0 +OP4 E02755 0 +OP4 E02756 0 +OP4 E02757 0 +OP4 E02758 0 +OP4 E02759 0 +OP4 E0275A 0 +OP4 E0275B 0 +OP4 E0275C 0 +OP4 E0275D 0 +OP4 E0275E 0 +OP4 E0275F 0 +OP4 E02760 0 +OP4 E02761 0 +OP4 E02762 0 +OP4 E02763 0 +OP4 E02764 0 +OP4 E02765 0 +OP4 E02766 0 +OP4 E02767 0 +OP4 E02768 0 +OP4 E02769 0 +OP4 E0276A 0 +OP4 E0276B 0 +OP4 E0276C 0 +OP4 E0276D 0 +OP4 E0276E 0 +OP4 E0276F 0 +OP4 E02770 0 +OP4 E02771 0 +OP4 E02772 0 +OP4 E02773 0 +OP4 E02774 0 +OP4 E02775 0 +OP4 E02776 0 +OP4 E02777 0 +OP4 E02778 0 +OP4 E02779 0 +OP4 E0277A 0 +OP4 E0277B 0 +OP4 E0277C 0 +OP4 E0277D 0 +OP4 E0277E 0 +OP4 E0277F 0 +OP4 E02780 0 +OP4 E02781 0 +OP4 E02782 0 +OP4 E02783 0 +OP4 E02784 0 +OP4 E02785 0 +OP4 E02786 0 +OP4 E02787 0 +OP4 E02788 0 +OP4 E02789 0 +OP4 E0278A 0 +OP4 E0278B 0 +OP4 E0278C 0 +OP4 E0278D 0 +OP4 E0278E 0 +OP4 E0278F 0 +OP4 E02790 0 +OP4 E02791 0 +OP4 E02792 0 +OP4 E02793 0 +OP4 E02794 0 +OP4 E02795 0 +OP4 E02796 0 +OP4 E02797 0 +OP4 E02798 0 +OP4 E02799 0 +OP4 E0279A 0 +OP4 E0279B 0 +OP4 E0279C 0 +OP4 E0279D 0 +OP4 E0279E 0 +OP4 E0279F 0 +OP4 E027A0 0 +OP4 E027A1 0 +OP4 E027A2 0 +OP4 E027A3 0 +OP4 E027A4 0 +OP4 E027A5 0 +OP4 E027A6 0 +OP4 E027A7 0 +OP4 E027A8 0 +OP4 E027A9 0 +OP4 E027AA 0 +OP4 E027AB 0 +OP4 E027AC 0 +OP4 E027AD 0 +OP4 E027AE 0 +OP4 E027AF 0 +OP4 E027B0 0 +OP4 E027B1 0 +OP4 E027B2 0 +OP4 E027B3 0 +OP4 E027B4 0 +OP4 E027B5 0 +OP4 E027B6 0 +OP4 E027B7 0 +OP4 E027B8 0 +OP4 E027B9 0 +OP4 E027BA 0 +OP4 E027BB 0 +OP4 E027BC 0 +OP4 E027BD 0 +OP4 E027BE 0 +OP4 E027BF 0 +OP4 E027C0 0 +OP4 E027C1 0 +OP4 E027C2 0 +OP4 E027C3 0 +OP4 E027C4 0 +OP4 E027C5 0 +OP4 E027C6 0 +OP4 E027C7 0 +OP4 E027C8 0 +OP4 E027C9 0 +OP4 E027CA 0 +OP4 E027CB 0 +OP4 E027CC 0 +OP4 E027CD 0 +OP4 E027CE 0 +OP4 E027CF 0 +OP4 E027D0 0 +OP4 E027D1 0 +OP4 E027D2 0 +OP4 E027D3 0 +OP4 E027D4 0 +OP4 E027D5 0 +OP4 E027D6 0 +OP4 E027D7 0 +OP4 E027D8 0 +OP4 E027D9 0 +OP4 E027DA 0 +OP4 E027DB 0 +OP4 E027DC 0 +OP4 E027DD 0 +OP4 E027DE 0 +OP4 E027DF 0 +OP4 E027E0 0 +OP4 E027E1 0 +OP4 E027E2 0 +OP4 E027E3 0 +OP4 E027E4 0 +OP4 E027E5 0 +OP4 E027E6 0 +OP4 E027E7 0 +OP4 E027E8 0 +OP4 E027E9 0 +OP4 E027EA 0 +OP4 E027EB 0 +OP4 E027EC 0 +OP4 E027ED 0 +OP4 E027EE 0 +OP4 E027EF 0 +OP4 E027F0 0 +OP4 E027F1 0 +OP4 E027F2 0 +OP4 E027F3 0 +OP4 E027F4 0 +OP4 E027F5 0 +OP4 E027F6 0 +OP4 E027F7 0 +OP4 E027F8 0 +OP4 E027F9 0 +OP4 E027FA 0 +OP4 E027FB 0 +OP4 E027FC 0 +OP4 E027FD 0 +OP4 E027FE 0 +OP4 E027FF 0 +OP4 E02800 0 +OP4 E02801 0 +OP4 E02802 0 +OP4 E02803 0 +OP4 E02804 0 +OP4 E02805 0 +OP4 E02806 0 +OP4 E02807 0 +OP4 E02808 0 +OP4 E02809 0 +OP4 E0280A 0 +OP4 E0280B 0 +OP4 E0280C 0 +OP4 E0280D 0 +OP4 E0280E 0 +OP4 E0280F 0 +OP4 E02810 0 +OP4 E02811 0 +OP4 E02812 0 +OP4 E02813 0 +OP4 E02814 0 +OP4 E02815 0 +OP4 E02816 0 +OP4 E02817 0 +OP4 E02818 0 +OP4 E02819 0 +OP4 E0281A 0 +OP4 E0281B 0 +OP4 E0281C 0 +OP4 E0281D 0 +OP4 E0281E 0 +OP4 E0281F 0 +OP4 E02820 0 +OP4 E02821 0 +OP4 E02822 0 +OP4 E02823 0 +OP4 E02824 0 +OP4 E02825 0 +OP4 E02826 0 +OP4 E02827 0 +OP4 E02828 0 +OP4 E02829 0 +OP4 E0282A 0 +OP4 E0282B 0 +OP4 E0282C 0 +OP4 E0282D 0 +OP4 E0282E 0 +OP4 E0282F 0 +OP4 E02830 0 +OP4 E02831 0 +OP4 E02832 0 +OP4 E02833 0 +OP4 E02834 0 +OP4 E02835 0 +OP4 E02836 0 +OP4 E02837 0 +OP4 E02838 0 +OP4 E02839 0 +OP4 E0283A 0 +OP4 E0283B 0 +OP4 E0283C 0 +OP4 E0283D 0 +OP4 E0283E 0 +OP4 E0283F 0 +OP4 E02840 0 +OP4 E02841 0 +OP4 E02842 0 +OP4 E02843 0 +OP4 E02844 0 +OP4 E02845 0 +OP4 E02846 0 +OP4 E02847 0 +OP4 E02848 0 +OP4 E02849 0 +OP4 E0284A 0 +OP4 E0284B 0 +OP4 E0284C 0 +OP4 E0284D 0 +OP4 E0284E 0 +OP4 E0284F 0 +OP4 E02850 0 +OP4 E02851 0 +OP4 E02852 0 +OP4 E02853 0 +OP4 E02854 0 +OP4 E02855 0 +OP4 E02856 0 +OP4 E02857 0 +OP4 E02858 0 +OP4 E02859 0 +OP4 E0285A 0 +OP4 E0285B 0 +OP4 E0285C 0 +OP4 E0285D 0 +OP4 E0285E 0 +OP4 E0285F 0 +OP4 E02860 0 +OP4 E02861 0 +OP4 E02862 0 +OP4 E02863 0 +OP4 E02864 0 +OP4 E02865 0 +OP4 E02866 0 +OP4 E02867 0 +OP4 E02868 0 +OP4 E02869 0 +OP4 E0286A 0 +OP4 E0286B 0 +OP4 E0286C 0 +OP4 E0286D 0 +OP4 E0286E 0 +OP4 E0286F 0 +OP4 E02870 0 +OP4 E02871 0 +OP4 E02872 0 +OP4 E02873 0 +OP4 E02874 0 +OP4 E02875 0 +OP4 E02876 0 +OP4 E02877 0 +OP4 E02878 0 +OP4 E02879 0 +OP4 E0287A 0 +OP4 E0287B 0 +OP4 E0287C 0 +OP4 E0287D 0 +OP4 E0287E 0 +OP4 E0287F 0 +OP4 E02880 0 +OP4 E02881 0 +OP4 E02882 0 +OP4 E02883 0 +OP4 E02884 0 +OP4 E02885 0 +OP4 E02886 0 +OP4 E02887 0 +OP4 E02888 0 +OP4 E02889 0 +OP4 E0288A 0 +OP4 E0288B 0 +OP4 E0288C 0 +OP4 E0288D 0 +OP4 E0288E 0 +OP4 E0288F 0 +OP4 E02890 0 +OP4 E02891 0 +OP4 E02892 0 +OP4 E02893 0 +OP4 E02894 0 +OP4 E02895 0 +OP4 E02896 0 +OP4 E02897 0 +OP4 E02898 0 +OP4 E02899 0 +OP4 E0289A 0 +OP4 E0289B 0 +OP4 E0289C 0 +OP4 E0289D 0 +OP4 E0289E 0 +OP4 E0289F 0 +OP4 E028A0 0 +OP4 E028A1 0 +OP4 E028A2 0 +OP4 E028A3 0 +OP4 E028A4 0 +OP4 E028A5 0 +OP4 E028A6 0 +OP4 E028A7 0 +OP4 E028A8 0 +OP4 E028A9 0 +OP4 E028AA 0 +OP4 E028AB 0 +OP4 E028AC 0 +OP4 E028AD 0 +OP4 E028AE 0 +OP4 E028AF 0 +OP4 E028B0 0 +OP4 E028B1 0 +OP4 E028B2 0 +OP4 E028B3 0 +OP4 E028B4 0 +OP4 E028B5 0 +OP4 E028B6 0 +OP4 E028B7 0 +OP4 E028B8 0 +OP4 E028B9 0 +OP4 E028BA 0 +OP4 E028BB 0 +OP4 E028BC 0 +OP4 E028BD 0 +OP4 E028BE 0 +OP4 E028BF 0 +OP4 E028C0 0 +OP4 E028C1 0 +OP4 E028C2 0 +OP4 E028C3 0 +OP4 E028C4 0 +OP4 E028C5 0 +OP4 E028C6 0 +OP4 E028C7 0 +OP4 E028C8 0 +OP4 E028C9 0 +OP4 E028CA 0 +OP4 E028CB 0 +OP4 E028CC 0 +OP4 E028CD 0 +OP4 E028CE 0 +OP4 E028CF 0 +OP4 E028D0 0 +OP4 E028D1 0 +OP4 E028D2 0 +OP4 E028D3 0 +OP4 E028D4 0 +OP4 E028D5 0 +OP4 E028D6 0 +OP4 E028D7 0 +OP4 E028D8 0 +OP4 E028D9 0 +OP4 E028DA 0 +OP4 E028DB 0 +OP4 E028DC 0 +OP4 E028DD 0 +OP4 E028DE 0 +OP4 E028DF 0 +OP4 E028E0 0 +OP4 E028E1 0 +OP4 E028E2 0 +OP4 E028E3 0 +OP4 E028E4 0 +OP4 E028E5 0 +OP4 E028E6 0 +OP4 E028E7 0 +OP4 E028E8 0 +OP4 E028E9 0 +OP4 E028EA 0 +OP4 E028EB 0 +OP4 E028EC 0 +OP4 E028ED 0 +OP4 E028EE 0 +OP4 E028EF 0 +OP4 E028F0 0 +OP4 E028F1 0 +OP4 E028F2 0 +OP4 E028F3 0 +OP4 E028F4 0 +OP4 E028F5 0 +OP4 E028F6 0 +OP4 E028F7 0 +OP4 E028F8 0 +OP4 E028F9 0 +OP4 E028FA 0 +OP4 E028FB 0 +OP4 E028FC 0 +OP4 E028FD 0 +OP4 E028FE 0 +OP4 E028FF 0 +OP4 E02900 0 +OP4 E02901 0 +OP4 E02902 0 +OP4 E02903 0 +OP4 E02904 0 +OP4 E02905 0 +OP4 E02906 0 +OP4 E02907 0 +OP4 E02908 0 +OP4 E02909 0 +OP4 E0290A 0 +OP4 E0290B 0 +OP4 E0290C 0 +OP4 E0290D 0 +OP4 E0290E 0 +OP4 E0290F 0 +OP4 E02910 0 +OP4 E02911 0 +OP4 E02912 0 +OP4 E02913 0 +OP4 E02914 0 +OP4 E02915 0 +OP4 E02916 0 +OP4 E02917 0 +OP4 E02918 0 +OP4 E02919 0 +OP4 E0291A 0 +OP4 E0291B 0 +OP4 E0291C 0 +OP4 E0291D 0 +OP4 E0291E 0 +OP4 E0291F 0 +OP4 E02920 0 +OP4 E02921 0 +OP4 E02922 0 +OP4 E02923 0 +OP4 E02924 0 +OP4 E02925 0 +OP4 E02926 0 +OP4 E02927 0 +OP4 E02928 0 +OP4 E02929 0 +OP4 E0292A 0 +OP4 E0292B 0 +OP4 E0292C 0 +OP4 E0292D 0 +OP4 E0292E 0 +OP4 E0292F 0 +OP4 E02930 0 +OP4 E02931 0 +OP4 E02932 0 +OP4 E02933 0 +OP4 E02934 0 +OP4 E02935 0 +OP4 E02936 0 +OP4 E02937 0 +OP4 E02938 0 +OP4 E02939 0 +OP4 E0293A 0 +OP4 E0293B 0 +OP4 E0293C 0 +OP4 E0293D 0 +OP4 E0293E 0 +OP4 E0293F 0 +OP4 E02940 0 +OP4 E02941 0 +OP4 E02942 0 +OP4 E02943 0 +OP4 E02944 0 +OP4 E02945 0 +OP4 E02946 0 +OP4 E02947 0 +OP4 E02948 0 +OP4 E02949 0 +OP4 E0294A 0 +OP4 E0294B 0 +OP4 E0294C 0 +OP4 E0294D 0 +OP4 E0294E 0 +OP4 E0294F 0 +OP4 E02950 0 +OP4 E02951 0 +OP4 E02952 0 +OP4 E02953 0 +OP4 E02954 0 +OP4 E02955 0 +OP4 E02956 0 +OP4 E02957 0 +OP4 E02958 0 +OP4 E02959 0 +OP4 E0295A 0 +OP4 E0295B 0 +OP4 E0295C 0 +OP4 E0295D 0 +OP4 E0295E 0 +OP4 E0295F 0 +OP4 E02960 0 +OP4 E02961 0 +OP4 E02962 0 +OP4 E02963 0 +OP4 E02964 0 +OP4 E02965 0 +OP4 E02966 0 +OP4 E02967 0 +OP4 E02968 0 +OP4 E02969 0 +OP4 E0296A 0 +OP4 E0296B 0 +OP4 E0296C 0 +OP4 E0296D 0 +OP4 E0296E 0 +OP4 E0296F 0 +OP4 E02970 0 +OP4 E02971 0 +OP4 E02972 0 +OP4 E02973 0 +OP4 E02974 0 +OP4 E02975 0 +OP4 E02976 0 +OP4 E02977 0 +OP4 E02978 0 +OP4 E02979 0 +OP4 E0297A 0 +OP4 E0297B 0 +OP4 E0297C 0 +OP4 E0297D 0 +OP4 E0297E 0 +OP4 E0297F 0 +OP4 E02980 0 +OP4 E02981 0 +OP4 E02982 0 +OP4 E02983 0 +OP4 E02984 0 +OP4 E02985 0 +OP4 E02986 0 +OP4 E02987 0 +OP4 E02988 0 +OP4 E02989 0 +OP4 E0298A 0 +OP4 E0298B 0 +OP4 E0298C 0 +OP4 E0298D 0 +OP4 E0298E 0 +OP4 E0298F 0 +OP4 E02990 0 +OP4 E02991 0 +OP4 E02992 0 +OP4 E02993 0 +OP4 E02994 0 +OP4 E02995 0 +OP4 E02996 0 +OP4 E02997 0 +OP4 E02998 0 +OP4 E02999 0 +OP4 E0299A 0 +OP4 E0299B 0 +OP4 E0299C 0 +OP4 E0299D 0 +OP4 E0299E 0 +OP4 E0299F 0 +OP4 E029A0 0 +OP4 E029A1 0 +OP4 E029A2 0 +OP4 E029A3 0 +OP4 E029A4 0 +OP4 E029A5 0 +OP4 E029A6 0 +OP4 E029A7 0 +OP4 E029A8 0 +OP4 E029A9 0 +OP4 E029AA 0 +OP4 E029AB 0 +OP4 E029AC 0 +OP4 E029AD 0 +OP4 E029AE 0 +OP4 E029AF 0 +OP4 E029B0 0 +OP4 E029B1 0 +OP4 E029B2 0 +OP4 E029B3 0 +OP4 E029B4 0 +OP4 E029B5 0 +OP4 E029B6 0 +OP4 E029B7 0 +OP4 E029B8 0 +OP4 E029B9 0 +OP4 E029BA 0 +OP4 E029BB 0 +OP4 E029BC 0 +OP4 E029BD 0 +OP4 E029BE 0 +OP4 E029BF 0 +OP4 E029C0 0 +OP4 E029C1 0 +OP4 E029C2 0 +OP4 E029C3 0 +OP4 E029C4 0 +OP4 E029C5 0 +OP4 E029C6 0 +OP4 E029C7 0 +OP4 E029C8 0 +OP4 E029C9 0 +OP4 E029CA 0 +OP4 E029CB 0 +OP4 E029CC 0 +OP4 E029CD 0 +OP4 E029CE 0 +OP4 E029CF 0 +OP4 E029D0 0 +OP4 E029D1 0 +OP4 E029D2 0 +OP4 E029D3 0 +OP4 E029D4 0 +OP4 E029D5 0 +OP4 E029D6 0 +OP4 E029D7 0 +OP4 E029D8 0 +OP4 E029D9 0 +OP4 E029DA 0 +OP4 E029DB 0 +OP4 E029DC 0 +OP4 E029DD 0 +OP4 E029DE 0 +OP4 E029DF 0 +OP4 E029E0 0 +OP4 E029E1 0 +OP4 E029E2 0 +OP4 E029E3 0 +OP4 E029E4 0 +OP4 E029E5 0 +OP4 E029E6 0 +OP4 E029E7 0 +OP4 E029E8 0 +OP4 E029E9 0 +OP4 E029EA 0 +OP4 E029EB 0 +OP4 E029EC 0 +OP4 E029ED 0 +OP4 E029EE 0 +OP4 E029EF 0 +OP4 E029F0 0 +OP4 E029F1 0 +OP4 E029F2 0 +OP4 E029F3 0 +OP4 E029F4 0 +OP4 E029F5 0 +OP4 E029F6 0 +OP4 E029F7 0 +OP4 E029F8 0 +OP4 E029F9 0 +OP4 E029FA 0 +OP4 E029FB 0 +OP4 E029FC 0 +OP4 E029FD 0 +OP4 E029FE 0 +OP4 E029FF 0 +OP4 E02A00 0 +OP4 E02A01 0 +OP4 E02A02 0 +OP4 E02A03 0 +OP4 E02A04 0 +OP4 E02A05 0 +OP4 E02A06 0 +OP4 E02A07 0 +OP4 E02A08 0 +OP4 E02A09 0 +OP4 E02A0A 0 +OP4 E02A0B 0 +OP4 E02A0C 0 +OP4 E02A0D 0 +OP4 E02A0E 0 +OP4 E02A0F 0 +OP4 E02A10 0 +OP4 E02A11 0 +OP4 E02A12 0 +OP4 E02A13 0 +OP4 E02A14 0 +OP4 E02A15 0 +OP4 E02A16 0 +OP4 E02A17 0 +OP4 E02A18 0 +OP4 E02A19 0 +OP4 E02A1A 0 +OP4 E02A1B 0 +OP4 E02A1C 0 +OP4 E02A1D 0 +OP4 E02A1E 0 +OP4 E02A1F 0 +OP4 E02A20 0 +OP4 E02A21 0 +OP4 E02A22 0 +OP4 E02A23 0 +OP4 E02A24 0 +OP4 E02A25 0 +OP4 E02A26 0 +OP4 E02A27 0 +OP4 E02A28 0 +OP4 E02A29 0 +OP4 E02A2A 0 +OP4 E02A2B 0 +OP4 E02A2C 0 +OP4 E02A2D 0 +OP4 E02A2E 0 +OP4 E02A2F 0 +OP4 E02A30 0 +OP4 E02A31 0 +OP4 E02A32 0 +OP4 E02A33 0 +OP4 E02A34 0 +OP4 E02A35 0 +OP4 E02A36 0 +OP4 E02A37 0 +OP4 E02A38 0 +OP4 E02A39 0 +OP4 E02A3A 0 +OP4 E02A3B 0 +OP4 E02A3C 0 +OP4 E02A3D 0 +OP4 E02A3E 0 +OP4 E02A3F 0 +OP4 E02A40 0 +OP4 E02A41 0 +OP4 E02A42 0 +OP4 E02A43 0 +OP4 E02A44 0 +OP4 E02A45 0 +OP4 E02A46 0 +OP4 E02A47 0 +OP4 E02A48 0 +OP4 E02A49 0 +OP4 E02A4A 0 +OP4 E02A4B 0 +OP4 E02A4C 0 +OP4 E02A4D 0 +OP4 E02A4E 0 +OP4 E02A4F 0 +OP4 E02A50 0 +OP4 E02A51 0 +OP4 E02A52 0 +OP4 E02A53 0 +OP4 E02A54 0 +OP4 E02A55 0 +OP4 E02A56 0 +OP4 E02A57 0 +OP4 E02A58 0 +OP4 E02A59 0 +OP4 E02A5A 0 +OP4 E02A5B 0 +OP4 E02A5C 0 +OP4 E02A5D 0 +OP4 E02A5E 0 +OP4 E02A5F 0 +OP4 E02A60 0 +OP4 E02A61 0 +OP4 E02A62 0 +OP4 E02A63 0 +OP4 E02A64 0 +OP4 E02A65 0 +OP4 E02A66 0 +OP4 E02A67 0 +OP4 E02A68 0 +OP4 E02A69 0 +OP4 E02A6A 0 +OP4 E02A6B 0 +OP4 E02A6C 0 +OP4 E02A6D 0 +OP4 E02A6E 0 +OP4 E02A6F 0 +OP4 E02A70 0 +OP4 E02A71 0 +OP4 E02A72 0 +OP4 E02A73 0 +OP4 E02A74 0 +OP4 E02A75 0 +OP4 E02A76 0 +OP4 E02A77 0 +OP4 E02A78 0 +OP4 E02A79 0 +OP4 E02A7A 0 +OP4 E02A7B 0 +OP4 E02A7C 0 +OP4 E02A7D 0 +OP4 E02A7E 0 +OP4 E02A7F 0 +OP4 E02A80 0 +OP4 E02A81 0 +OP4 E02A82 0 +OP4 E02A83 0 +OP4 E02A84 0 +OP4 E02A85 0 +OP4 E02A86 0 +OP4 E02A87 0 +OP4 E02A88 0 +OP4 E02A89 0 +OP4 E02A8A 0 +OP4 E02A8B 0 +OP4 E02A8C 0 +OP4 E02A8D 0 +OP4 E02A8E 0 +OP4 E02A8F 0 +OP4 E02A90 0 +OP4 E02A91 0 +OP4 E02A92 0 +OP4 E02A93 0 +OP4 E02A94 0 +OP4 E02A95 0 +OP4 E02A96 0 +OP4 E02A97 0 +OP4 E02A98 0 +OP4 E02A99 0 +OP4 E02A9A 0 +OP4 E02A9B 0 +OP4 E02A9C 0 +OP4 E02A9D 0 +OP4 E02A9E 0 +OP4 E02A9F 0 +OP4 E02AA0 0 +OP4 E02AA1 0 +OP4 E02AA2 0 +OP4 E02AA3 0 +OP4 E02AA4 0 +OP4 E02AA5 0 +OP4 E02AA6 0 +OP4 E02AA7 0 +OP4 E02AA8 0 +OP4 E02AA9 0 +OP4 E02AAA 0 +OP4 E02AAB 0 +OP4 E02AAC 0 +OP4 E02AAD 0 +OP4 E02AAE 0 +OP4 E02AAF 0 +OP4 E02AB0 0 +OP4 E02AB1 0 +OP4 E02AB2 0 +OP4 E02AB3 0 +OP4 E02AB4 0 +OP4 E02AB5 0 +OP4 E02AB6 0 +OP4 E02AB7 0 +OP4 E02AB8 0 +OP4 E02AB9 0 +OP4 E02ABA 0 +OP4 E02ABB 0 +OP4 E02ABC 0 +OP4 E02ABD 0 +OP4 E02ABE 0 +OP4 E02ABF 0 +OP4 E02AC0 0 +OP4 E02AC1 0 +OP4 E02AC2 0 +OP4 E02AC3 0 +OP4 E02AC4 0 +OP4 E02AC5 0 +OP4 E02AC6 0 +OP4 E02AC7 0 +OP4 E02AC8 0 +OP4 E02AC9 0 +OP4 E02ACA 0 +OP4 E02ACB 0 +OP4 E02ACC 0 +OP4 E02ACD 0 +OP4 E02ACE 0 +OP4 E02ACF 0 +OP4 E02AD0 0 +OP4 E02AD1 0 +OP4 E02AD2 0 +OP4 E02AD3 0 +OP4 E02AD4 0 +OP4 E02AD5 0 +OP4 E02AD6 0 +OP4 E02AD7 0 +OP4 E02AD8 0 +OP4 E02AD9 0 +OP4 E02ADA 0 +OP4 E02ADB 0 +OP4 E02ADC 0 +OP4 E02ADD 0 +OP4 E02ADE 0 +OP4 E02ADF 0 +OP4 E02AE0 0 +OP4 E02AE1 0 +OP4 E02AE2 0 +OP4 E02AE3 0 +OP4 E02AE4 0 +OP4 E02AE5 0 +OP4 E02AE6 0 +OP4 E02AE7 0 +OP4 E02AE8 0 +OP4 E02AE9 0 +OP4 E02AEA 0 +OP4 E02AEB 0 +OP4 E02AEC 0 +OP4 E02AED 0 +OP4 E02AEE 0 +OP4 E02AEF 0 +OP4 E02AF0 0 +OP4 E02AF1 0 +OP4 E02AF2 0 +OP4 E02AF3 0 +OP4 E02AF4 0 +OP4 E02AF5 0 +OP4 E02AF6 0 +OP4 E02AF7 0 +OP4 E02AF8 0 +OP4 E02AF9 0 +OP4 E02AFA 0 +OP4 E02AFB 0 +OP4 E02AFC 0 +OP4 E02AFD 0 +OP4 E02AFE 0 +OP4 E02AFF 0 +OP4 E02B00 0 +OP4 E02B01 0 +OP4 E02B02 0 +OP4 E02B03 0 +OP4 E02B04 0 +OP4 E02B05 0 +OP4 E02B06 0 +OP4 E02B07 0 +OP4 E02B08 0 +OP4 E02B09 0 +OP4 E02B0A 0 +OP4 E02B0B 0 +OP4 E02B0C 0 +OP4 E02B0D 0 +OP4 E02B0E 0 +OP4 E02B0F 0 +OP4 E02B10 0 +OP4 E02B11 0 +OP4 E02B12 0 +OP4 E02B13 0 +OP4 E02B14 0 +OP4 E02B15 0 +OP4 E02B16 0 +OP4 E02B17 0 +OP4 E02B18 0 +OP4 E02B19 0 +OP4 E02B1A 0 +OP4 E02B1B 0 +OP4 E02B1C 0 +OP4 E02B1D 0 +OP4 E02B1E 0 +OP4 E02B1F 0 +OP4 E02B20 0 +OP4 E02B21 0 +OP4 E02B22 0 +OP4 E02B23 0 +OP4 E02B24 0 +OP4 E02B25 0 +OP4 E02B26 0 +OP4 E02B27 0 +OP4 E02B28 0 +OP4 E02B29 0 +OP4 E02B2A 0 +OP4 E02B2B 0 +OP4 E02B2C 0 +OP4 E02B2D 0 +OP4 E02B2E 0 +OP4 E02B2F 0 +OP4 E02B30 0 +OP4 E02B31 0 +OP4 E02B32 0 +OP4 E02B33 0 +OP4 E02B34 0 +OP4 E02B35 0 +OP4 E02B36 0 +OP4 E02B37 0 +OP4 E02B38 0 +OP4 E02B39 0 +OP4 E02B3A 0 +OP4 E02B3B 0 +OP4 E02B3C 0 +OP4 E02B3D 0 +OP4 E02B3E 0 +OP4 E02B3F 0 +OP4 E02B40 0 +OP4 E02B41 0 +OP4 E02B42 0 +OP4 E02B43 0 +OP4 E02B44 0 +OP4 E02B45 0 +OP4 E02B46 0 +OP4 E02B47 0 +OP4 E02B48 0 +OP4 E02B49 0 +OP4 E02B4A 0 +OP4 E02B4B 0 +OP4 E02B4C 0 +OP4 E02B4D 0 +OP4 E02B4E 0 +OP4 E02B4F 0 +OP4 E02B50 0 +OP4 E02B51 0 +OP4 E02B52 0 +OP4 E02B53 0 +OP4 E02B54 0 +OP4 E02B55 0 +OP4 E02B56 0 +OP4 E02B57 0 +OP4 E02B58 0 +OP4 E02B59 0 +OP4 E02B5A 0 +OP4 E02B5B 0 +OP4 E02B5C 0 +OP4 E02B5D 0 +OP4 E02B5E 0 +OP4 E02B5F 0 +OP4 E02B60 0 +OP4 E02B61 0 +OP4 E02B62 0 +OP4 E02B63 0 +OP4 E02B64 0 +OP4 E02B65 0 +OP4 E02B66 0 +OP4 E02B67 0 +OP4 E02B68 0 +OP4 E02B69 0 +OP4 E02B6A 0 +OP4 E02B6B 0 +OP4 E02B6C 0 +OP4 E02B6D 0 +OP4 E02B6E 0 +OP4 E02B6F 0 +OP4 E02B70 0 +OP4 E02B71 0 +OP4 E02B72 0 +OP4 E02B73 0 +OP4 E02B74 0 +OP4 E02B75 0 +OP4 E02B76 0 +OP4 E02B77 0 +OP4 E02B78 0 +OP4 E02B79 0 +OP4 E02B7A 0 +OP4 E02B7B 0 +OP4 E02B7C 0 +OP4 E02B7D 0 +OP4 E02B7E 0 +OP4 E02B7F 0 +OP4 E02B80 0 +OP4 E02B81 0 +OP4 E02B82 0 +OP4 E02B83 0 +OP4 E02B84 0 +OP4 E02B85 0 +OP4 E02B86 0 +OP4 E02B87 0 +OP4 E02B88 0 +OP4 E02B89 0 +OP4 E02B8A 0 +OP4 E02B8B 0 +OP4 E02B8C 0 +OP4 E02B8D 0 +OP4 E02B8E 0 +OP4 E02B8F 0 +OP4 E02B90 0 +OP4 E02B91 0 +OP4 E02B92 0 +OP4 E02B93 0 +OP4 E02B94 0 +OP4 E02B95 0 +OP4 E02B96 0 +OP4 E02B97 0 +OP4 E02B98 0 +OP4 E02B99 0 +OP4 E02B9A 0 +OP4 E02B9B 0 +OP4 E02B9C 0 +OP4 E02B9D 0 +OP4 E02B9E 0 +OP4 E02B9F 0 +OP4 E02BA0 0 +OP4 E02BA1 0 +OP4 E02BA2 0 +OP4 E02BA3 0 +OP4 E02BA4 0 +OP4 E02BA5 0 +OP4 E02BA6 0 +OP4 E02BA7 0 +OP4 E02BA8 0 +OP4 E02BA9 0 +OP4 E02BAA 0 +OP4 E02BAB 0 +OP4 E02BAC 0 +OP4 E02BAD 0 +OP4 E02BAE 0 +OP4 E02BAF 0 +OP4 E02BB0 0 +OP4 E02BB1 0 +OP4 E02BB2 0 +OP4 E02BB3 0 +OP4 E02BB4 0 +OP4 E02BB5 0 +OP4 E02BB6 0 +OP4 E02BB7 0 +OP4 E02BB8 0 +OP4 E02BB9 0 +OP4 E02BBA 0 +OP4 E02BBB 0 +OP4 E02BBC 0 +OP4 E02BBD 0 +OP4 E02BBE 0 +OP4 E02BBF 0 +OP4 E02BC0 0 +OP4 E02BC1 0 +OP4 E02BC2 0 +OP4 E02BC3 0 +OP4 E02BC4 0 +OP4 E02BC5 0 +OP4 E02BC6 0 +OP4 E02BC7 0 +OP4 E02BC8 0 +OP4 E02BC9 0 +OP4 E02BCA 0 +OP4 E02BCB 0 +OP4 E02BCC 0 +OP4 E02BCD 0 +OP4 E02BCE 0 +OP4 E02BCF 0 +OP4 E02BD0 0 +OP4 E02BD1 0 +OP4 E02BD2 0 +OP4 E02BD3 0 +OP4 E02BD4 0 +OP4 E02BD5 0 +OP4 E02BD6 0 +OP4 E02BD7 0 +OP4 E02BD8 0 +OP4 E02BD9 0 +OP4 E02BDA 0 +OP4 E02BDB 0 +OP4 E02BDC 0 +OP4 E02BDD 0 +OP4 E02BDE 0 +OP4 E02BDF 0 +OP4 E02BE0 0 +OP4 E02BE1 0 +OP4 E02BE2 0 +OP4 E02BE3 0 +OP4 E02BE4 0 +OP4 E02BE5 0 +OP4 E02BE6 0 +OP4 E02BE7 0 +OP4 E02BE8 0 +OP4 E02BE9 0 +OP4 E02BEA 0 +OP4 E02BEB 0 +OP4 E02BEC 0 +OP4 E02BED 0 +OP4 E02BEE 0 +OP4 E02BEF 0 +OP4 E02BF0 0 +OP4 E02BF1 0 +OP4 E02BF2 0 +OP4 E02BF3 0 +OP4 E02BF4 0 +OP4 E02BF5 0 +OP4 E02BF6 0 +OP4 E02BF7 0 +OP4 E02BF8 0 +OP4 E02BF9 0 +OP4 E02BFA 0 +OP4 E02BFB 0 +OP4 E02BFC 0 +OP4 E02BFD 0 +OP4 E02BFE 0 +OP4 E02BFF 0 +OP4 E02C00 0 +OP4 E02C01 0 +OP4 E02C02 0 +OP4 E02C03 0 +OP4 E02C04 0 +OP4 E02C05 0 +OP4 E02C06 0 +OP4 E02C07 0 +OP4 E02C08 0 +OP4 E02C09 0 +OP4 E02C0A 0 +OP4 E02C0B 0 +OP4 E02C0C 0 +OP4 E02C0D 0 +OP4 E02C0E 0 +OP4 E02C0F 0 +OP4 E02C10 0 +OP4 E02C11 0 +OP4 E02C12 0 +OP4 E02C13 0 +OP4 E02C14 0 +OP4 E02C15 0 +OP4 E02C16 0 +OP4 E02C17 0 +OP4 E02C18 0 +OP4 E02C19 0 +OP4 E02C1A 0 +OP4 E02C1B 0 +OP4 E02C1C 0 +OP4 E02C1D 0 +OP4 E02C1E 0 +OP4 E02C1F 0 +OP4 E02C20 0 +OP4 E02C21 0 +OP4 E02C22 0 +OP4 E02C23 0 +OP4 E02C24 0 +OP4 E02C25 0 +OP4 E02C26 0 +OP4 E02C27 0 +OP4 E02C28 0 +OP4 E02C29 0 +OP4 E02C2A 0 +OP4 E02C2B 0 +OP4 E02C2C 0 +OP4 E02C2D 0 +OP4 E02C2E 0 +OP4 E02C2F 0 +OP4 E02C30 0 +OP4 E02C31 0 +OP4 E02C32 0 +OP4 E02C33 0 +OP4 E02C34 0 +OP4 E02C35 0 +OP4 E02C36 0 +OP4 E02C37 0 +OP4 E02C38 0 +OP4 E02C39 0 +OP4 E02C3A 0 +OP4 E02C3B 0 +OP4 E02C3C 0 +OP4 E02C3D 0 +OP4 E02C3E 0 +OP4 E02C3F 0 +OP4 E02C40 0 +OP4 E02C41 0 +OP4 E02C42 0 +OP4 E02C43 0 +OP4 E02C44 0 +OP4 E02C45 0 +OP4 E02C46 0 +OP4 E02C47 0 +OP4 E02C48 0 +OP4 E02C49 0 +OP4 E02C4A 0 +OP4 E02C4B 0 +OP4 E02C4C 0 +OP4 E02C4D 0 +OP4 E02C4E 0 +OP4 E02C4F 0 +OP4 E02C50 0 +OP4 E02C51 0 +OP4 E02C52 0 +OP4 E02C53 0 +OP4 E02C54 0 +OP4 E02C55 0 +OP4 E02C56 0 +OP4 E02C57 0 +OP4 E02C58 0 +OP4 E02C59 0 +OP4 E02C5A 0 +OP4 E02C5B 0 +OP4 E02C5C 0 +OP4 E02C5D 0 +OP4 E02C5E 0 +OP4 E02C5F 0 +OP4 E02C60 0 +OP4 E02C61 0 +OP4 E02C62 0 +OP4 E02C63 0 +OP4 E02C64 0 +OP4 E02C65 0 +OP4 E02C66 0 +OP4 E02C67 0 +OP4 E02C68 0 +OP4 E02C69 0 +OP4 E02C6A 0 +OP4 E02C6B 0 +OP4 E02C6C 0 +OP4 E02C6D 0 +OP4 E02C6E 0 +OP4 E02C6F 0 +OP4 E02C70 0 +OP4 E02C71 0 +OP4 E02C72 0 +OP4 E02C73 0 +OP4 E02C74 0 +OP4 E02C75 0 +OP4 E02C76 0 +OP4 E02C77 0 +OP4 E02C78 0 +OP4 E02C79 0 +OP4 E02C7A 0 +OP4 E02C7B 0 +OP4 E02C7C 0 +OP4 E02C7D 0 +OP4 E02C7E 0 +OP4 E02C7F 0 +OP4 E02C80 0 +OP4 E02C81 0 +OP4 E02C82 0 +OP4 E02C83 0 +OP4 E02C84 0 +OP4 E02C85 0 +OP4 E02C86 0 +OP4 E02C87 0 +OP4 E02C88 0 +OP4 E02C89 0 +OP4 E02C8A 0 +OP4 E02C8B 0 +OP4 E02C8C 0 +OP4 E02C8D 0 +OP4 E02C8E 0 +OP4 E02C8F 0 +OP4 E02C90 0 +OP4 E02C91 0 +OP4 E02C92 0 +OP4 E02C93 0 +OP4 E02C94 0 +OP4 E02C95 0 +OP4 E02C96 0 +OP4 E02C97 0 +OP4 E02C98 0 +OP4 E02C99 0 +OP4 E02C9A 0 +OP4 E02C9B 0 +OP4 E02C9C 0 +OP4 E02C9D 0 +OP4 E02C9E 0 +OP4 E02C9F 0 +OP4 E02CA0 0 +OP4 E02CA1 0 +OP4 E02CA2 0 +OP4 E02CA3 0 +OP4 E02CA4 0 +OP4 E02CA5 0 +OP4 E02CA6 0 +OP4 E02CA7 0 +OP4 E02CA8 0 +OP4 E02CA9 0 +OP4 E02CAA 0 +OP4 E02CAB 0 +OP4 E02CAC 0 +OP4 E02CAD 0 +OP4 E02CAE 0 +OP4 E02CAF 0 +OP4 E02CB0 0 +OP4 E02CB1 0 +OP4 E02CB2 0 +OP4 E02CB3 0 +OP4 E02CB4 0 +OP4 E02CB5 0 +OP4 E02CB6 0 +OP4 E02CB7 0 +OP4 E02CB8 0 +OP4 E02CB9 0 +OP4 E02CBA 0 +OP4 E02CBB 0 +OP4 E02CBC 0 +OP4 E02CBD 0 +OP4 E02CBE 0 +OP4 E02CBF 0 +OP4 E02CC0 0 +OP4 E02CC1 0 +OP4 E02CC2 0 +OP4 E02CC3 0 +OP4 E02CC4 0 +OP4 E02CC5 0 +OP4 E02CC6 0 +OP4 E02CC7 0 +OP4 E02CC8 0 +OP4 E02CC9 0 +OP4 E02CCA 0 +OP4 E02CCB 0 +OP4 E02CCC 0 +OP4 E02CCD 0 +OP4 E02CCE 0 +OP4 E02CCF 0 +OP4 E02CD0 0 +OP4 E02CD1 0 +OP4 E02CD2 0 +OP4 E02CD3 0 +OP4 E02CD4 0 +OP4 E02CD5 0 +OP4 E02CD6 0 +OP4 E02CD7 0 +OP4 E02CD8 0 +OP4 E02CD9 0 +OP4 E02CDA 0 +OP4 E02CDB 0 +OP4 E02CDC 0 +OP4 E02CDD 0 +OP4 E02CDE 0 +OP4 E02CDF 0 +OP4 E02CE0 0 +OP4 E02CE1 0 +OP4 E02CE2 0 +OP4 E02CE3 0 +OP4 E02CE4 0 +OP4 E02CE5 0 +OP4 E02CE6 0 +OP4 E02CE7 0 +OP4 E02CE8 0 +OP4 E02CE9 0 +OP4 E02CEA 0 +OP4 E02CEB 0 +OP4 E02CEC 0 +OP4 E02CED 0 +OP4 E02CEE 0 +OP4 E02CEF 0 +OP4 E02CF0 0 +OP4 E02CF1 0 +OP4 E02CF2 0 +OP4 E02CF3 0 +OP4 E02CF4 0 +OP4 E02CF5 0 +OP4 E02CF6 0 +OP4 E02CF7 0 +OP4 E02CF8 0 +OP4 E02CF9 0 +OP4 E02CFA 0 +OP4 E02CFB 0 +OP4 E02CFC 0 +OP4 E02CFD 0 +OP4 E02CFE 0 +OP4 E02CFF 0 +OP4 E02D00 0 +OP4 E02D01 0 +OP4 E02D02 0 +OP4 E02D03 0 +OP4 E02D04 0 +OP4 E02D05 0 +OP4 E02D06 0 +OP4 E02D07 0 +OP4 E02D08 0 +OP4 E02D09 0 +OP4 E02D0A 0 +OP4 E02D0B 0 +OP4 E02D0C 0 +OP4 E02D0D 0 +OP4 E02D0E 0 +OP4 E02D0F 0 +OP4 E02D10 0 +OP4 E02D11 0 +OP4 E02D12 0 +OP4 E02D13 0 +OP4 E02D14 0 +OP4 E02D15 0 +OP4 E02D16 0 +OP4 E02D17 0 +OP4 E02D18 0 +OP4 E02D19 0 +OP4 E02D1A 0 +OP4 E02D1B 0 +OP4 E02D1C 0 +OP4 E02D1D 0 +OP4 E02D1E 0 +OP4 E02D1F 0 +OP4 E02D20 0 +OP4 E02D21 0 +OP4 E02D22 0 +OP4 E02D23 0 +OP4 E02D24 0 +OP4 E02D25 0 +OP4 E02D26 0 +OP4 E02D27 0 +OP4 E02D28 0 +OP4 E02D29 0 +OP4 E02D2A 0 +OP4 E02D2B 0 +OP4 E02D2C 0 +OP4 E02D2D 0 +OP4 E02D2E 0 +OP4 E02D2F 0 +OP4 E02D30 0 +OP4 E02D31 0 +OP4 E02D32 0 +OP4 E02D33 0 +OP4 E02D34 0 +OP4 E02D35 0 +OP4 E02D36 0 +OP4 E02D37 0 +OP4 E02D38 0 +OP4 E02D39 0 +OP4 E02D3A 0 +OP4 E02D3B 0 +OP4 E02D3C 0 +OP4 E02D3D 0 +OP4 E02D3E 0 +OP4 E02D3F 0 +OP4 E02D40 0 +OP4 E02D41 0 +OP4 E02D42 0 +OP4 E02D43 0 +OP4 E02D44 0 +OP4 E02D45 0 +OP4 E02D46 0 +OP4 E02D47 0 +OP4 E02D48 0 +OP4 E02D49 0 +OP4 E02D4A 0 +OP4 E02D4B 0 +OP4 E02D4C 0 +OP4 E02D4D 0 +OP4 E02D4E 0 +OP4 E02D4F 0 +OP4 E02D50 0 +OP4 E02D51 0 +OP4 E02D52 0 +OP4 E02D53 0 +OP4 E02D54 0 +OP4 E02D55 0 +OP4 E02D56 0 +OP4 E02D57 0 +OP4 E02D58 0 +OP4 E02D59 0 +OP4 E02D5A 0 +OP4 E02D5B 0 +OP4 E02D5C 0 +OP4 E02D5D 0 +OP4 E02D5E 0 +OP4 E02D5F 0 +OP4 E02D60 0 +OP4 E02D61 0 +OP4 E02D62 0 +OP4 E02D63 0 +OP4 E02D64 0 +OP4 E02D65 0 +OP4 E02D66 0 +OP4 E02D67 0 +OP4 E02D68 0 +OP4 E02D69 0 +OP4 E02D6A 0 +OP4 E02D6B 0 +OP4 E02D6C 0 +OP4 E02D6D 0 +OP4 E02D6E 0 +OP4 E02D6F 0 +OP4 E02D70 0 +OP4 E02D71 0 +OP4 E02D72 0 +OP4 E02D73 0 +OP4 E02D74 0 +OP4 E02D75 0 +OP4 E02D76 0 +OP4 E02D77 0 +OP4 E02D78 0 +OP4 E02D79 0 +OP4 E02D7A 0 +OP4 E02D7B 0 +OP4 E02D7C 0 +OP4 E02D7D 0 +OP4 E02D7E 0 +OP4 E02D7F 0 +OP4 E02D80 0 +OP4 E02D81 0 +OP4 E02D82 0 +OP4 E02D83 0 +OP4 E02D84 0 +OP4 E02D85 0 +OP4 E02D86 0 +OP4 E02D87 0 +OP4 E02D88 0 +OP4 E02D89 0 +OP4 E02D8A 0 +OP4 E02D8B 0 +OP4 E02D8C 0 +OP4 E02D8D 0 +OP4 E02D8E 0 +OP4 E02D8F 0 +OP4 E02D90 0 +OP4 E02D91 0 +OP4 E02D92 0 +OP4 E02D93 0 +OP4 E02D94 0 +OP4 E02D95 0 +OP4 E02D96 0 +OP4 E02D97 0 +OP4 E02D98 0 +OP4 E02D99 0 +OP4 E02D9A 0 +OP4 E02D9B 0 +OP4 E02D9C 0 +OP4 E02D9D 0 +OP4 E02D9E 0 +OP4 E02D9F 0 +OP4 E02DA0 0 +OP4 E02DA1 0 +OP4 E02DA2 0 +OP4 E02DA3 0 +OP4 E02DA4 0 +OP4 E02DA5 0 +OP4 E02DA6 0 +OP4 E02DA7 0 +OP4 E02DA8 0 +OP4 E02DA9 0 +OP4 E02DAA 0 +OP4 E02DAB 0 +OP4 E02DAC 0 +OP4 E02DAD 0 +OP4 E02DAE 0 +OP4 E02DAF 0 +OP4 E02DB0 0 +OP4 E02DB1 0 +OP4 E02DB2 0 +OP4 E02DB3 0 +OP4 E02DB4 0 +OP4 E02DB5 0 +OP4 E02DB6 0 +OP4 E02DB7 0 +OP4 E02DB8 0 +OP4 E02DB9 0 +OP4 E02DBA 0 +OP4 E02DBB 0 +OP4 E02DBC 0 +OP4 E02DBD 0 +OP4 E02DBE 0 +OP4 E02DBF 0 +OP4 E02DC0 0 +OP4 E02DC1 0 +OP4 E02DC2 0 +OP4 E02DC3 0 +OP4 E02DC4 0 +OP4 E02DC5 0 +OP4 E02DC6 0 +OP4 E02DC7 0 +OP4 E02DC8 0 +OP4 E02DC9 0 +OP4 E02DCA 0 +OP4 E02DCB 0 +OP4 E02DCC 0 +OP4 E02DCD 0 +OP4 E02DCE 0 +OP4 E02DCF 0 +OP4 E02DD0 0 +OP4 E02DD1 0 +OP4 E02DD2 0 +OP4 E02DD3 0 +OP4 E02DD4 0 +OP4 E02DD5 0 +OP4 E02DD6 0 +OP4 E02DD7 0 +OP4 E02DD8 0 +OP4 E02DD9 0 +OP4 E02DDA 0 +OP4 E02DDB 0 +OP4 E02DDC 0 +OP4 E02DDD 0 +OP4 E02DDE 0 +OP4 E02DDF 0 +OP4 E02DE0 0 +OP4 E02DE1 0 +OP4 E02DE2 0 +OP4 E02DE3 0 +OP4 E02DE4 0 +OP4 E02DE5 0 +OP4 E02DE6 0 +OP4 E02DE7 0 +OP4 E02DE8 0 +OP4 E02DE9 0 +OP4 E02DEA 0 +OP4 E02DEB 0 +OP4 E02DEC 0 +OP4 E02DED 0 +OP4 E02DEE 0 +OP4 E02DEF 0 +OP4 E02DF0 0 +OP4 E02DF1 0 +OP4 E02DF2 0 +OP4 E02DF3 0 +OP4 E02DF4 0 +OP4 E02DF5 0 +OP4 E02DF6 0 +OP4 E02DF7 0 +OP4 E02DF8 0 +OP4 E02DF9 0 +OP4 E02DFA 0 +OP4 E02DFB 0 +OP4 E02DFC 0 +OP4 E02DFD 0 +OP4 E02DFE 0 +OP4 E02DFF 0 +OP4 E02E00 0 +OP4 E02E01 0 +OP4 E02E02 0 +OP4 E02E03 0 +OP4 E02E04 0 +OP4 E02E05 0 +OP4 E02E06 0 +OP4 E02E07 0 +OP4 E02E08 0 +OP4 E02E09 0 +OP4 E02E0A 0 +OP4 E02E0B 0 +OP4 E02E0C 0 +OP4 E02E0D 0 +OP4 E02E0E 0 +OP4 E02E0F 0 +OP4 E02E10 0 +OP4 E02E11 0 +OP4 E02E12 0 +OP4 E02E13 0 +OP4 E02E14 0 +OP4 E02E15 0 +OP4 E02E16 0 +OP4 E02E17 0 +OP4 E02E18 0 +OP4 E02E19 0 +OP4 E02E1A 0 +OP4 E02E1B 0 +OP4 E02E1C 0 +OP4 E02E1D 0 +OP4 E02E1E 0 +OP4 E02E1F 0 +OP4 E02E20 0 +OP4 E02E21 0 +OP4 E02E22 0 +OP4 E02E23 0 +OP4 E02E24 0 +OP4 E02E25 0 +OP4 E02E26 0 +OP4 E02E27 0 +OP4 E02E28 0 +OP4 E02E29 0 +OP4 E02E2A 0 +OP4 E02E2B 0 +OP4 E02E2C 0 +OP4 E02E2D 0 +OP4 E02E2E 0 +OP4 E02E2F 0 +OP4 E02E30 0 +OP4 E02E31 0 +OP4 E02E32 0 +OP4 E02E33 0 +OP4 E02E34 0 +OP4 E02E35 0 +OP4 E02E36 0 +OP4 E02E37 0 +OP4 E02E38 0 +OP4 E02E39 0 +OP4 E02E3A 0 +OP4 E02E3B 0 +OP4 E02E3C 0 +OP4 E02E3D 0 +OP4 E02E3E 0 +OP4 E02E3F 0 +OP4 E02E40 0 +OP4 E02E41 0 +OP4 E02E42 0 +OP4 E02E43 0 +OP4 E02E44 0 +OP4 E02E45 0 +OP4 E02E46 0 +OP4 E02E47 0 +OP4 E02E48 0 +OP4 E02E49 0 +OP4 E02E4A 0 +OP4 E02E4B 0 +OP4 E02E4C 0 +OP4 E02E4D 0 +OP4 E02E4E 0 +OP4 E02E4F 0 +OP4 E02E50 0 +OP4 E02E51 0 +OP4 E02E52 0 +OP4 E02E53 0 +OP4 E02E54 0 +OP4 E02E55 0 +OP4 E02E56 0 +OP4 E02E57 0 +OP4 E02E58 0 +OP4 E02E59 0 +OP4 E02E5A 0 +OP4 E02E5B 0 +OP4 E02E5C 0 +OP4 E02E5D 0 +OP4 E02E5E 0 +OP4 E02E5F 0 +OP4 E02E60 0 +OP4 E02E61 0 +OP4 E02E62 0 +OP4 E02E63 0 +OP4 E02E64 0 +OP4 E02E65 0 +OP4 E02E66 0 +OP4 E02E67 0 +OP4 E02E68 0 +OP4 E02E69 0 +OP4 E02E6A 0 +OP4 E02E6B 0 +OP4 E02E6C 0 +OP4 E02E6D 0 +OP4 E02E6E 0 +OP4 E02E6F 0 +OP4 E02E70 0 +OP4 E02E71 0 +OP4 E02E72 0 +OP4 E02E73 0 +OP4 E02E74 0 +OP4 E02E75 0 +OP4 E02E76 0 +OP4 E02E77 0 +OP4 E02E78 0 +OP4 E02E79 0 +OP4 E02E7A 0 +OP4 E02E7B 0 +OP4 E02E7C 0 +OP4 E02E7D 0 +OP4 E02E7E 0 +OP4 E02E7F 0 +OP4 E02E80 0 +OP4 E02E81 0 +OP4 E02E82 0 +OP4 E02E83 0 +OP4 E02E84 0 +OP4 E02E85 0 +OP4 E02E86 0 +OP4 E02E87 0 +OP4 E02E88 0 +OP4 E02E89 0 +OP4 E02E8A 0 +OP4 E02E8B 0 +OP4 E02E8C 0 +OP4 E02E8D 0 +OP4 E02E8E 0 +OP4 E02E8F 0 +OP4 E02E90 0 +OP4 E02E91 0 +OP4 E02E92 0 +OP4 E02E93 0 +OP4 E02E94 0 +OP4 E02E95 0 +OP4 E02E96 0 +OP4 E02E97 0 +OP4 E02E98 0 +OP4 E02E99 0 +OP4 E02E9A 0 +OP4 E02E9B 0 +OP4 E02E9C 0 +OP4 E02E9D 0 +OP4 E02E9E 0 +OP4 E02E9F 0 +OP4 E02EA0 0 +OP4 E02EA1 0 +OP4 E02EA2 0 +OP4 E02EA3 0 +OP4 E02EA4 0 +OP4 E02EA5 0 +OP4 E02EA6 0 +OP4 E02EA7 0 +OP4 E02EA8 0 +OP4 E02EA9 0 +OP4 E02EAA 0 +OP4 E02EAB 0 +OP4 E02EAC 0 +OP4 E02EAD 0 +OP4 E02EAE 0 +OP4 E02EAF 0 +OP4 E02EB0 0 +OP4 E02EB1 0 +OP4 E02EB2 0 +OP4 E02EB3 0 +OP4 E02EB4 0 +OP4 E02EB5 0 +OP4 E02EB6 0 +OP4 E02EB7 0 +OP4 E02EB8 0 +OP4 E02EB9 0 +OP4 E02EBA 0 +OP4 E02EBB 0 +OP4 E02EBC 0 +OP4 E02EBD 0 +OP4 E02EBE 0 +OP4 E02EBF 0 +OP4 E02EC0 0 +OP4 E02EC1 0 +OP4 E02EC2 0 +OP4 E02EC3 0 +OP4 E02EC4 0 +OP4 E02EC5 0 +OP4 E02EC6 0 +OP4 E02EC7 0 +OP4 E02EC8 0 +OP4 E02EC9 0 +OP4 E02ECA 0 +OP4 E02ECB 0 +OP4 E02ECC 0 +OP4 E02ECD 0 +OP4 E02ECE 0 +OP4 E02ECF 0 +OP4 E02ED0 0 +OP4 E02ED1 0 +OP4 E02ED2 0 +OP4 E02ED3 0 +OP4 E02ED4 0 +OP4 E02ED5 0 +OP4 E02ED6 0 +OP4 E02ED7 0 +OP4 E02ED8 0 +OP4 E02ED9 0 +OP4 E02EDA 0 +OP4 E02EDB 0 +OP4 E02EDC 0 +OP4 E02EDD 0 +OP4 E02EDE 0 +OP4 E02EDF 0 +OP4 E02EE0 0 +OP4 E02EE1 0 +OP4 E02EE2 0 +OP4 E02EE3 0 +OP4 E02EE4 0 +OP4 E02EE5 0 +OP4 E02EE6 0 +OP4 E02EE7 0 +OP4 E02EE8 0 +OP4 E02EE9 0 +OP4 E02EEA 0 +OP4 E02EEB 0 +OP4 E02EEC 0 +OP4 E02EED 0 +OP4 E02EEE 0 +OP4 E02EEF 0 +OP4 E02EF0 0 +OP4 E02EF1 0 +OP4 E02EF2 0 +OP4 E02EF3 0 +OP4 E02EF4 0 +OP4 E02EF5 0 +OP4 E02EF6 0 +OP4 E02EF7 0 +OP4 E02EF8 0 +OP4 E02EF9 0 +OP4 E02EFA 0 +OP4 E02EFB 0 +OP4 E02EFC 0 +OP4 E02EFD 0 +OP4 E02EFE 0 +OP4 E02EFF 0 +OP4 E02F00 0 +OP4 E02F01 0 +OP4 E02F02 0 +OP4 E02F03 0 +OP4 E02F04 0 +OP4 E02F05 0 +OP4 E02F06 0 +OP4 E02F07 0 +OP4 E02F08 0 +OP4 E02F09 0 +OP4 E02F0A 0 +OP4 E02F0B 0 +OP4 E02F0C 0 +OP4 E02F0D 0 +OP4 E02F0E 0 +OP4 E02F0F 0 +OP4 E02F10 0 +OP4 E02F11 0 +OP4 E02F12 0 +OP4 E02F13 0 +OP4 E02F14 0 +OP4 E02F15 0 +OP4 E02F16 0 +OP4 E02F17 0 +OP4 E02F18 0 +OP4 E02F19 0 +OP4 E02F1A 0 +OP4 E02F1B 0 +OP4 E02F1C 0 +OP4 E02F1D 0 +OP4 E02F1E 0 +OP4 E02F1F 0 +OP4 E02F20 0 +OP4 E02F21 0 +OP4 E02F22 0 +OP4 E02F23 0 +OP4 E02F24 0 +OP4 E02F25 0 +OP4 E02F26 0 +OP4 E02F27 0 +OP4 E02F28 0 +OP4 E02F29 0 +OP4 E02F2A 0 +OP4 E02F2B 0 +OP4 E02F2C 0 +OP4 E02F2D 0 +OP4 E02F2E 0 +OP4 E02F2F 0 +OP4 E02F30 0 +OP4 E02F31 0 +OP4 E02F32 0 +OP4 E02F33 0 +OP4 E02F34 0 +OP4 E02F35 0 +OP4 E02F36 0 +OP4 E02F37 0 +OP4 E02F38 0 +OP4 E02F39 0 +OP4 E02F3A 0 +OP4 E02F3B 0 +OP4 E02F3C 0 +OP4 E02F3D 0 +OP4 E02F3E 0 +OP4 E02F3F 0 +OP4 E02F40 0 +OP4 E02F41 0 +OP4 E02F42 0 +OP4 E02F43 0 +OP4 E02F44 0 +OP4 E02F45 0 +OP4 E02F46 0 +OP4 E02F47 0 +OP4 E02F48 0 +OP4 E02F49 0 +OP4 E02F4A 0 +OP4 E02F4B 0 +OP4 E02F4C 0 +OP4 E02F4D 0 +OP4 E02F4E 0 +OP4 E02F4F 0 +OP4 E02F50 0 +OP4 E02F51 0 +OP4 E02F52 0 +OP4 E02F53 0 +OP4 E02F54 0 +OP4 E02F55 0 +OP4 E02F56 0 +OP4 E02F57 0 +OP4 E02F58 0 +OP4 E02F59 0 +OP4 E02F5A 0 +OP4 E02F5B 0 +OP4 E02F5C 0 +OP4 E02F5D 0 +OP4 E02F5E 0 +OP4 E02F5F 0 +OP4 E02F60 0 +OP4 E02F61 0 +OP4 E02F62 0 +OP4 E02F63 0 +OP4 E02F64 0 +OP4 E02F65 0 +OP4 E02F66 0 +OP4 E02F67 0 +OP4 E02F68 0 +OP4 E02F69 0 +OP4 E02F6A 0 +OP4 E02F6B 0 +OP4 E02F6C 0 +OP4 E02F6D 0 +OP4 E02F6E 0 +OP4 E02F6F 0 +OP4 E02F70 0 +OP4 E02F71 0 +OP4 E02F72 0 +OP4 E02F73 0 +OP4 E02F74 0 +OP4 E02F75 0 +OP4 E02F76 0 +OP4 E02F77 0 +OP4 E02F78 0 +OP4 E02F79 0 +OP4 E02F7A 0 +OP4 E02F7B 0 +OP4 E02F7C 0 +OP4 E02F7D 0 +OP4 E02F7E 0 +OP4 E02F7F 0 +OP4 E02F80 0 +OP4 E02F81 0 +OP4 E02F82 0 +OP4 E02F83 0 +OP4 E02F84 0 +OP4 E02F85 0 +OP4 E02F86 0 +OP4 E02F87 0 +OP4 E02F88 0 +OP4 E02F89 0 +OP4 E02F8A 0 +OP4 E02F8B 0 +OP4 E02F8C 0 +OP4 E02F8D 0 +OP4 E02F8E 0 +OP4 E02F8F 0 +OP4 E02F90 0 +OP4 E02F91 0 +OP4 E02F92 0 +OP4 E02F93 0 +OP4 E02F94 0 +OP4 E02F95 0 +OP4 E02F96 0 +OP4 E02F97 0 +OP4 E02F98 0 +OP4 E02F99 0 +OP4 E02F9A 0 +OP4 E02F9B 0 +OP4 E02F9C 0 +OP4 E02F9D 0 +OP4 E02F9E 0 +OP4 E02F9F 0 +OP4 E02FA0 0 +OP4 E02FA1 0 +OP4 E02FA2 0 +OP4 E02FA3 0 +OP4 E02FA4 0 +OP4 E02FA5 0 +OP4 E02FA6 0 +OP4 E02FA7 0 +OP4 E02FA8 0 +OP4 E02FA9 0 +OP4 E02FAA 0 +OP4 E02FAB 0 +OP4 E02FAC 0 +OP4 E02FAD 0 +OP4 E02FAE 0 +OP4 E02FAF 0 +OP4 E02FB0 0 +OP4 E02FB1 0 +OP4 E02FB2 0 +OP4 E02FB3 0 +OP4 E02FB4 0 +OP4 E02FB5 0 +OP4 E02FB6 0 +OP4 E02FB7 0 +OP4 E02FB8 0 +OP4 E02FB9 0 +OP4 E02FBA 0 +OP4 E02FBB 0 +OP4 E02FBC 0 +OP4 E02FBD 0 +OP4 E02FBE 0 +OP4 E02FBF 0 +OP4 E02FC0 0 +OP4 E02FC1 0 +OP4 E02FC2 0 +OP4 E02FC3 0 +OP4 E02FC4 0 +OP4 E02FC5 0 +OP4 E02FC6 0 +OP4 E02FC7 0 +OP4 E02FC8 0 +OP4 E02FC9 0 +OP4 E02FCA 0 +OP4 E02FCB 0 +OP4 E02FCC 0 +OP4 E02FCD 0 +OP4 E02FCE 0 +OP4 E02FCF 0 +OP4 E02FD0 0 +OP4 E02FD1 0 +OP4 E02FD2 0 +OP4 E02FD3 0 +OP4 E02FD4 0 +OP4 E02FD5 0 +OP4 E02FD6 0 +OP4 E02FD7 0 +OP4 E02FD8 0 +OP4 E02FD9 0 +OP4 E02FDA 0 +OP4 E02FDB 0 +OP4 E02FDC 0 +OP4 E02FDD 0 +OP4 E02FDE 0 +OP4 E02FDF 0 +OP4 E02FE0 0 +OP4 E02FE1 0 +OP4 E02FE2 0 +OP4 E02FE3 0 +OP4 E02FE4 0 +OP4 E02FE5 0 +OP4 E02FE6 0 +OP4 E02FE7 0 +OP4 E02FE8 0 +OP4 E02FE9 0 +OP4 E02FEA 0 +OP4 E02FEB 0 +OP4 E02FEC 0 +OP4 E02FED 0 +OP4 E02FEE 0 +OP4 E02FEF 0 +OP4 E02FF0 0 +OP4 E02FF1 0 +OP4 E02FF2 0 +OP4 E02FF3 0 +OP4 E02FF4 0 +OP4 E02FF5 0 +OP4 E02FF6 0 +OP4 E02FF7 0 +OP4 E02FF8 0 +OP4 E02FF9 0 +OP4 E02FFA 0 +OP4 E02FFB 0 +OP4 E02FFC 0 +OP4 E02FFD 0 +OP4 E02FFE 0 +OP4 E02FFF 0 +OP4 E03000 0 +OP4 E03001 0 +OP4 E03002 0 +OP4 E03003 0 +OP4 E03004 0 +OP4 E03005 0 +OP4 E03006 0 +OP4 E03007 0 +OP4 E03008 0 +OP4 E03009 0 +OP4 E0300A 0 +OP4 E0300B 0 +OP4 E0300C 0 +OP4 E0300D 0 +OP4 E0300E 0 +OP4 E0300F 0 +OP4 E03010 0 +OP4 E03011 0 +OP4 E03012 0 +OP4 E03013 0 +OP4 E03014 0 +OP4 E03015 0 +OP4 E03016 0 +OP4 E03017 0 +OP4 E03018 0 +OP4 E03019 0 +OP4 E0301A 0 +OP4 E0301B 0 +OP4 E0301C 0 +OP4 E0301D 0 +OP4 E0301E 0 +OP4 E0301F 0 +OP4 E03020 0 +OP4 E03021 0 +OP4 E03022 0 +OP4 E03023 0 +OP4 E03024 0 +OP4 E03025 0 +OP4 E03026 0 +OP4 E03027 0 +OP4 E03028 0 +OP4 E03029 0 +OP4 E0302A 0 +OP4 E0302B 0 +OP4 E0302C 0 +OP4 E0302D 0 +OP4 E0302E 0 +OP4 E0302F 0 +OP4 E03030 0 +OP4 E03031 0 +OP4 E03032 0 +OP4 E03033 0 +OP4 E03034 0 +OP4 E03035 0 +OP4 E03036 0 +OP4 E03037 0 +OP4 E03038 0 +OP4 E03039 0 +OP4 E0303A 0 +OP4 E0303B 0 +OP4 E0303C 0 +OP4 E0303D 0 +OP4 E0303E 0 +OP4 E0303F 0 +OP4 E03040 0 +OP4 E03041 0 +OP4 E03042 0 +OP4 E03043 0 +OP4 E03044 0 +OP4 E03045 0 +OP4 E03046 0 +OP4 E03047 0 +OP4 E03048 0 +OP4 E03049 0 +OP4 E0304A 0 +OP4 E0304B 0 +OP4 E0304C 0 +OP4 E0304D 0 +OP4 E0304E 0 +OP4 E0304F 0 +OP4 E03050 0 +OP4 E03051 0 +OP4 E03052 0 +OP4 E03053 0 +OP4 E03054 0 +OP4 E03055 0 +OP4 E03056 0 +OP4 E03057 0 +OP4 E03058 0 +OP4 E03059 0 +OP4 E0305A 0 +OP4 E0305B 0 +OP4 E0305C 0 +OP4 E0305D 0 +OP4 E0305E 0 +OP4 E0305F 0 +OP4 E03060 0 +OP4 E03061 0 +OP4 E03062 0 +OP4 E03063 0 +OP4 E03064 0 +OP4 E03065 0 +OP4 E03066 0 +OP4 E03067 0 +OP4 E03068 0 +OP4 E03069 0 +OP4 E0306A 0 +OP4 E0306B 0 +OP4 E0306C 0 +OP4 E0306D 0 +OP4 E0306E 0 +OP4 E0306F 0 +OP4 E03070 0 +OP4 E03071 0 +OP4 E03072 0 +OP4 E03073 0 +OP4 E03074 0 +OP4 E03075 0 +OP4 E03076 0 +OP4 E03077 0 +OP4 E03078 0 +OP4 E03079 0 +OP4 E0307A 0 +OP4 E0307B 0 +OP4 E0307C 0 +OP4 E0307D 0 +OP4 E0307E 0 +OP4 E0307F 0 +OP4 E03080 0 +OP4 E03081 0 +OP4 E03082 0 +OP4 E03083 0 +OP4 E03084 0 +OP4 E03085 0 +OP4 E03086 0 +OP4 E03087 0 +OP4 E03088 0 +OP4 E03089 0 +OP4 E0308A 0 +OP4 E0308B 0 +OP4 E0308C 0 +OP4 E0308D 0 +OP4 E0308E 0 +OP4 E0308F 0 +OP4 E03090 0 +OP4 E03091 0 +OP4 E03092 0 +OP4 E03093 0 +OP4 E03094 0 +OP4 E03095 0 +OP4 E03096 0 +OP4 E03097 0 +OP4 E03098 0 +OP4 E03099 0 +OP4 E0309A 0 +OP4 E0309B 0 +OP4 E0309C 0 +OP4 E0309D 0 +OP4 E0309E 0 +OP4 E0309F 0 +OP4 E030A0 0 +OP4 E030A1 0 +OP4 E030A2 0 +OP4 E030A3 0 +OP4 E030A4 0 +OP4 E030A5 0 +OP4 E030A6 0 +OP4 E030A7 0 +OP4 E030A8 0 +OP4 E030A9 0 +OP4 E030AA 0 +OP4 E030AB 0 +OP4 E030AC 0 +OP4 E030AD 0 +OP4 E030AE 0 +OP4 E030AF 0 +OP4 E030B0 0 +OP4 E030B1 0 +OP4 E030B2 0 +OP4 E030B3 0 +OP4 E030B4 0 +OP4 E030B5 0 +OP4 E030B6 0 +OP4 E030B7 0 +OP4 E030B8 0 +OP4 E030B9 0 +OP4 E030BA 0 +OP4 E030BB 0 +OP4 E030BC 0 +OP4 E030BD 0 +OP4 E030BE 0 +OP4 E030BF 0 +OP4 E030C0 0 +OP4 E030C1 0 +OP4 E030C2 0 +OP4 E030C3 0 +OP4 E030C4 0 +OP4 E030C5 0 +OP4 E030C6 0 +OP4 E030C7 0 +OP4 E030C8 0 +OP4 E030C9 0 +OP4 E030CA 0 +OP4 E030CB 0 +OP4 E030CC 0 +OP4 E030CD 0 +OP4 E030CE 0 +OP4 E030CF 0 +OP4 E030D0 0 +OP4 E030D1 0 +OP4 E030D2 0 +OP4 E030D3 0 +OP4 E030D4 0 +OP4 E030D5 0 +OP4 E030D6 0 +OP4 E030D7 0 +OP4 E030D8 0 +OP4 E030D9 0 +OP4 E030DA 0 +OP4 E030DB 0 +OP4 E030DC 0 +OP4 E030DD 0 +OP4 E030DE 0 +OP4 E030DF 0 +OP4 E030E0 0 +OP4 E030E1 0 +OP4 E030E2 0 +OP4 E030E3 0 +OP4 E030E4 0 +OP4 E030E5 0 +OP4 E030E6 0 +OP4 E030E7 0 +OP4 E030E8 0 +OP4 E030E9 0 +OP4 E030EA 0 +OP4 E030EB 0 +OP4 E030EC 0 +OP4 E030ED 0 +OP4 E030EE 0 +OP4 E030EF 0 +OP4 E030F0 0 +OP4 E030F1 0 +OP4 E030F2 0 +OP4 E030F3 0 +OP4 E030F4 0 +OP4 E030F5 0 +OP4 E030F6 0 +OP4 E030F7 0 +OP4 E030F8 0 +OP4 E030F9 0 +OP4 E030FA 0 +OP4 E030FB 0 +OP4 E030FC 0 +OP4 E030FD 0 +OP4 E030FE 0 +OP4 E030FF 0 +OP4 E03100 0 +OP4 E03101 0 +OP4 E03102 0 +OP4 E03103 0 +OP4 E03104 0 +OP4 E03105 0 +OP4 E03106 0 +OP4 E03107 0 +OP4 E03108 0 +OP4 E03109 0 +OP4 E0310A 0 +OP4 E0310B 0 +OP4 E0310C 0 +OP4 E0310D 0 +OP4 E0310E 0 +OP4 E0310F 0 +OP4 E03110 0 +OP4 E03111 0 +OP4 E03112 0 +OP4 E03113 0 +OP4 E03114 0 +OP4 E03115 0 +OP4 E03116 0 +OP4 E03117 0 +OP4 E03118 0 +OP4 E03119 0 +OP4 E0311A 0 +OP4 E0311B 0 +OP4 E0311C 0 +OP4 E0311D 0 +OP4 E0311E 0 +OP4 E0311F 0 +OP4 E03120 0 +OP4 E03121 0 +OP4 E03122 0 +OP4 E03123 0 +OP4 E03124 0 +OP4 E03125 0 +OP4 E03126 0 +OP4 E03127 0 +OP4 E03128 0 +OP4 E03129 0 +OP4 E0312A 0 +OP4 E0312B 0 +OP4 E0312C 0 +OP4 E0312D 0 +OP4 E0312E 0 +OP4 E0312F 0 +OP4 E03130 0 +OP4 E03131 0 +OP4 E03132 0 +OP4 E03133 0 +OP4 E03134 0 +OP4 E03135 0 +OP4 E03136 0 +OP4 E03137 0 +OP4 E03138 0 +OP4 E03139 0 +OP4 E0313A 0 +OP4 E0313B 0 +OP4 E0313C 0 +OP4 E0313D 0 +OP4 E0313E 0 +OP4 E0313F 0 +OP4 E03140 0 +OP4 E03141 0 +OP4 E03142 0 +OP4 E03143 0 +OP4 E03144 0 +OP4 E03145 0 +OP4 E03146 0 +OP4 E03147 0 +OP4 E03148 0 +OP4 E03149 0 +OP4 E0314A 0 +OP4 E0314B 0 +OP4 E0314C 0 +OP4 E0314D 0 +OP4 E0314E 0 +OP4 E0314F 0 +OP4 E03150 0 +OP4 E03151 0 +OP4 E03152 0 +OP4 E03153 0 +OP4 E03154 0 +OP4 E03155 0 +OP4 E03156 0 +OP4 E03157 0 +OP4 E03158 0 +OP4 E03159 0 +OP4 E0315A 0 +OP4 E0315B 0 +OP4 E0315C 0 +OP4 E0315D 0 +OP4 E0315E 0 +OP4 E0315F 0 +OP4 E03160 0 +OP4 E03161 0 +OP4 E03162 0 +OP4 E03163 0 +OP4 E03164 0 +OP4 E03165 0 +OP4 E03166 0 +OP4 E03167 0 +OP4 E03168 0 +OP4 E03169 0 +OP4 E0316A 0 +OP4 E0316B 0 +OP4 E0316C 0 +OP4 E0316D 0 +OP4 E0316E 0 +OP4 E0316F 0 +OP4 E03170 0 +OP4 E03171 0 +OP4 E03172 0 +OP4 E03173 0 +OP4 E03174 0 +OP4 E03175 0 +OP4 E03176 0 +OP4 E03177 0 +OP4 E03178 0 +OP4 E03179 0 +OP4 E0317A 0 +OP4 E0317B 0 +OP4 E0317C 0 +OP4 E0317D 0 +OP4 E0317E 0 +OP4 E0317F 0 +OP4 E03180 0 +OP4 E03181 0 +OP4 E03182 0 +OP4 E03183 0 +OP4 E03184 0 +OP4 E03185 0 +OP4 E03186 0 +OP4 E03187 0 +OP4 E03188 0 +OP4 E03189 0 +OP4 E0318A 0 +OP4 E0318B 0 +OP4 E0318C 0 +OP4 E0318D 0 +OP4 E0318E 0 +OP4 E0318F 0 +OP4 E03190 0 +OP4 E03191 0 +OP4 E03192 0 +OP4 E03193 0 +OP4 E03194 0 +OP4 E03195 0 +OP4 E03196 0 +OP4 E03197 0 +OP4 E03198 0 +OP4 E03199 0 +OP4 E0319A 0 +OP4 E0319B 0 +OP4 E0319C 0 +OP4 E0319D 0 +OP4 E0319E 0 +OP4 E0319F 0 +OP4 E031A0 0 +OP4 E031A1 0 +OP4 E031A2 0 +OP4 E031A3 0 +OP4 E031A4 0 +OP4 E031A5 0 +OP4 E031A6 0 +OP4 E031A7 0 +OP4 E031A8 0 +OP4 E031A9 0 +OP4 E031AA 0 +OP4 E031AB 0 +OP4 E031AC 0 +OP4 E031AD 0 +OP4 E031AE 0 +OP4 E031AF 0 +OP4 E031B0 0 +OP4 E031B1 0 +OP4 E031B2 0 +OP4 E031B3 0 +OP4 E031B4 0 +OP4 E031B5 0 +OP4 E031B6 0 +OP4 E031B7 0 +OP4 E031B8 0 +OP4 E031B9 0 +OP4 E031BA 0 +OP4 E031BB 0 +OP4 E031BC 0 +OP4 E031BD 0 +OP4 E031BE 0 +OP4 E031BF 0 +OP4 E031C0 0 +OP4 E031C1 0 +OP4 E031C2 0 +OP4 E031C3 0 +OP4 E031C4 0 +OP4 E031C5 0 +OP4 E031C6 0 +OP4 E031C7 0 +OP4 E031C8 0 +OP4 E031C9 0 +OP4 E031CA 0 +OP4 E031CB 0 +OP4 E031CC 0 +OP4 E031CD 0 +OP4 E031CE 0 +OP4 E031CF 0 +OP4 E031D0 0 +OP4 E031D1 0 +OP4 E031D2 0 +OP4 E031D3 0 +OP4 E031D4 0 +OP4 E031D5 0 +OP4 E031D6 0 +OP4 E031D7 0 +OP4 E031D8 0 +OP4 E031D9 0 +OP4 E031DA 0 +OP4 E031DB 0 +OP4 E031DC 0 +OP4 E031DD 0 +OP4 E031DE 0 +OP4 E031DF 0 +OP4 E031E0 0 +OP4 E031E1 0 +OP4 E031E2 0 +OP4 E031E3 0 +OP4 E031E4 0 +OP4 E031E5 0 +OP4 E031E6 0 +OP4 E031E7 0 +OP4 E031E8 0 +OP4 E031E9 0 +OP4 E031EA 0 +OP4 E031EB 0 +OP4 E031EC 0 +OP4 E031ED 0 +OP4 E031EE 0 +OP4 E031EF 0 +OP4 E031F0 0 +OP4 E031F1 0 +OP4 E031F2 0 +OP4 E031F3 0 +OP4 E031F4 0 +OP4 E031F5 0 +OP4 E031F6 0 +OP4 E031F7 0 +OP4 E031F8 0 +OP4 E031F9 0 +OP4 E031FA 0 +OP4 E031FB 0 +OP4 E031FC 0 +OP4 E031FD 0 +OP4 E031FE 0 +OP4 E031FF 0 +OP4 E03200 0 +OP4 E03201 0 +OP4 E03202 0 +OP4 E03203 0 +OP4 E03204 0 +OP4 E03205 0 +OP4 E03206 0 +OP4 E03207 0 +OP4 E03208 0 +OP4 E03209 0 +OP4 E0320A 0 +OP4 E0320B 0 +OP4 E0320C 0 +OP4 E0320D 0 +OP4 E0320E 0 +OP4 E0320F 0 +OP4 E03210 0 +OP4 E03211 0 +OP4 E03212 0 +OP4 E03213 0 +OP4 E03214 0 +OP4 E03215 0 +OP4 E03216 0 +OP4 E03217 0 +OP4 E03218 0 +OP4 E03219 0 +OP4 E0321A 0 +OP4 E0321B 0 +OP4 E0321C 0 +OP4 E0321D 0 +OP4 E0321E 0 +OP4 E0321F 0 +OP4 E03220 0 +OP4 E03221 0 +OP4 E03222 0 +OP4 E03223 0 +OP4 E03224 0 +OP4 E03225 0 +OP4 E03226 0 +OP4 E03227 0 +OP4 E03228 0 +OP4 E03229 0 +OP4 E0322A 0 +OP4 E0322B 0 +OP4 E0322C 0 +OP4 E0322D 0 +OP4 E0322E 0 +OP4 E0322F 0 +OP4 E03230 0 +OP4 E03231 0 +OP4 E03232 0 +OP4 E03233 0 +OP4 E03234 0 +OP4 E03235 0 +OP4 E03236 0 +OP4 E03237 0 +OP4 E03238 0 +OP4 E03239 0 +OP4 E0323A 0 +OP4 E0323B 0 +OP4 E0323C 0 +OP4 E0323D 0 +OP4 E0323E 0 +OP4 E0323F 0 +OP4 E03240 0 +OP4 E03241 0 +OP4 E03242 0 +OP4 E03243 0 +OP4 E03244 0 +OP4 E03245 0 +OP4 E03246 0 +OP4 E03247 0 +OP4 E03248 0 +OP4 E03249 0 +OP4 E0324A 0 +OP4 E0324B 0 +OP4 E0324C 0 +OP4 E0324D 0 +OP4 E0324E 0 +OP4 E0324F 0 +OP4 E03250 0 +OP4 E03251 0 +OP4 E03252 0 +OP4 E03253 0 +OP4 E03254 0 +OP4 E03255 0 +OP4 E03256 0 +OP4 E03257 0 +OP4 E03258 0 +OP4 E03259 0 +OP4 E0325A 0 +OP4 E0325B 0 +OP4 E0325C 0 +OP4 E0325D 0 +OP4 E0325E 0 +OP4 E0325F 0 +OP4 E03260 0 +OP4 E03261 0 +OP4 E03262 0 +OP4 E03263 0 +OP4 E03264 0 +OP4 E03265 0 +OP4 E03266 0 +OP4 E03267 0 +OP4 E03268 0 +OP4 E03269 0 +OP4 E0326A 0 +OP4 E0326B 0 +OP4 E0326C 0 +OP4 E0326D 0 +OP4 E0326E 0 +OP4 E0326F 0 +OP4 E03270 0 +OP4 E03271 0 +OP4 E03272 0 +OP4 E03273 0 +OP4 E03274 0 +OP4 E03275 0 +OP4 E03276 0 +OP4 E03277 0 +OP4 E03278 0 +OP4 E03279 0 +OP4 E0327A 0 +OP4 E0327B 0 +OP4 E0327C 0 +OP4 E0327D 0 +OP4 E0327E 0 +OP4 E0327F 0 +OP4 E03280 0 +OP4 E03281 0 +OP4 E03282 0 +OP4 E03283 0 +OP4 E03284 0 +OP4 E03285 0 +OP4 E03286 0 +OP4 E03287 0 +OP4 E03288 0 +OP4 E03289 0 +OP4 E0328A 0 +OP4 E0328B 0 +OP4 E0328C 0 +OP4 E0328D 0 +OP4 E0328E 0 +OP4 E0328F 0 +OP4 E03290 0 +OP4 E03291 0 +OP4 E03292 0 +OP4 E03293 0 +OP4 E03294 0 +OP4 E03295 0 +OP4 E03296 0 +OP4 E03297 0 +OP4 E03298 0 +OP4 E03299 0 +OP4 E0329A 0 +OP4 E0329B 0 +OP4 E0329C 0 +OP4 E0329D 0 +OP4 E0329E 0 +OP4 E0329F 0 +OP4 E032A0 0 +OP4 E032A1 0 +OP4 E032A2 0 +OP4 E032A3 0 +OP4 E032A4 0 +OP4 E032A5 0 +OP4 E032A6 0 +OP4 E032A7 0 +OP4 E032A8 0 +OP4 E032A9 0 +OP4 E032AA 0 +OP4 E032AB 0 +OP4 E032AC 0 +OP4 E032AD 0 +OP4 E032AE 0 +OP4 E032AF 0 +OP4 E032B0 0 +OP4 E032B1 0 +OP4 E032B2 0 +OP4 E032B3 0 +OP4 E032B4 0 +OP4 E032B5 0 +OP4 E032B6 0 +OP4 E032B7 0 +OP4 E032B8 0 +OP4 E032B9 0 +OP4 E032BA 0 +OP4 E032BB 0 +OP4 E032BC 0 +OP4 E032BD 0 +OP4 E032BE 0 +OP4 E032BF 0 +OP4 E032C0 0 +OP4 E032C1 0 +OP4 E032C2 0 +OP4 E032C3 0 +OP4 E032C4 0 +OP4 E032C5 0 +OP4 E032C6 0 +OP4 E032C7 0 +OP4 E032C8 0 +OP4 E032C9 0 +OP4 E032CA 0 +OP4 E032CB 0 +OP4 E032CC 0 +OP4 E032CD 0 +OP4 E032CE 0 +OP4 E032CF 0 +OP4 E032D0 0 +OP4 E032D1 0 +OP4 E032D2 0 +OP4 E032D3 0 +OP4 E032D4 0 +OP4 E032D5 0 +OP4 E032D6 0 +OP4 E032D7 0 +OP4 E032D8 0 +OP4 E032D9 0 +OP4 E032DA 0 +OP4 E032DB 0 +OP4 E032DC 0 +OP4 E032DD 0 +OP4 E032DE 0 +OP4 E032DF 0 +OP4 E032E0 0 +OP4 E032E1 0 +OP4 E032E2 0 +OP4 E032E3 0 +OP4 E032E4 0 +OP4 E032E5 0 +OP4 E032E6 0 +OP4 E032E7 0 +OP4 E032E8 0 +OP4 E032E9 0 +OP4 E032EA 0 +OP4 E032EB 0 +OP4 E032EC 0 +OP4 E032ED 0 +OP4 E032EE 0 +OP4 E032EF 0 +OP4 E032F0 0 +OP4 E032F1 0 +OP4 E032F2 0 +OP4 E032F3 0 +OP4 E032F4 0 +OP4 E032F5 0 +OP4 E032F6 0 +OP4 E032F7 0 +OP4 E032F8 0 +OP4 E032F9 0 +OP4 E032FA 0 +OP4 E032FB 0 +OP4 E032FC 0 +OP4 E032FD 0 +OP4 E032FE 0 +OP4 E032FF 0 +OP4 E03300 0 +OP4 E03301 0 +OP4 E03302 0 +OP4 E03303 0 +OP4 E03304 0 +OP4 E03305 0 +OP4 E03306 0 +OP4 E03307 0 +OP4 E03308 0 +OP4 E03309 0 +OP4 E0330A 0 +OP4 E0330B 0 +OP4 E0330C 0 +OP4 E0330D 0 +OP4 E0330E 0 +OP4 E0330F 0 +OP4 E03310 0 +OP4 E03311 0 +OP4 E03312 0 +OP4 E03313 0 +OP4 E03314 0 +OP4 E03315 0 +OP4 E03316 0 +OP4 E03317 0 +OP4 E03318 0 +OP4 E03319 0 +OP4 E0331A 0 +OP4 E0331B 0 +OP4 E0331C 0 +OP4 E0331D 0 +OP4 E0331E 0 +OP4 E0331F 0 +OP4 E03320 0 +OP4 E03321 0 +OP4 E03322 0 +OP4 E03323 0 +OP4 E03324 0 +OP4 E03325 0 +OP4 E03326 0 +OP4 E03327 0 +OP4 E03328 0 +OP4 E03329 0 +OP4 E0332A 0 +OP4 E0332B 0 +OP4 E0332C 0 +OP4 E0332D 0 +OP4 E0332E 0 +OP4 E0332F 0 +OP4 E03330 0 +OP4 E03331 0 +OP4 E03332 0 +OP4 E03333 0 +OP4 E03334 0 +OP4 E03335 0 +OP4 E03336 0 +OP4 E03337 0 +OP4 E03338 0 +OP4 E03339 0 +OP4 E0333A 0 +OP4 E0333B 0 +OP4 E0333C 0 +OP4 E0333D 0 +OP4 E0333E 0 +OP4 E0333F 0 +OP4 E03340 0 +OP4 E03341 0 +OP4 E03342 0 +OP4 E03343 0 +OP4 E03344 0 +OP4 E03345 0 +OP4 E03346 0 +OP4 E03347 0 +OP4 E03348 0 +OP4 E03349 0 +OP4 E0334A 0 +OP4 E0334B 0 +OP4 E0334C 0 +OP4 E0334D 0 +OP4 E0334E 0 +OP4 E0334F 0 +OP4 E03350 0 +OP4 E03351 0 +OP4 E03352 0 +OP4 E03353 0 +OP4 E03354 0 +OP4 E03355 0 +OP4 E03356 0 +OP4 E03357 0 +OP4 E03358 0 +OP4 E03359 0 +OP4 E0335A 0 +OP4 E0335B 0 +OP4 E0335C 0 +OP4 E0335D 0 +OP4 E0335E 0 +OP4 E0335F 0 +OP4 E03360 0 +OP4 E03361 0 +OP4 E03362 0 +OP4 E03363 0 +OP4 E03364 0 +OP4 E03365 0 +OP4 E03366 0 +OP4 E03367 0 +OP4 E03368 0 +OP4 E03369 0 +OP4 E0336A 0 +OP4 E0336B 0 +OP4 E0336C 0 +OP4 E0336D 0 +OP4 E0336E 0 +OP4 E0336F 0 +OP4 E03370 0 +OP4 E03371 0 +OP4 E03372 0 +OP4 E03373 0 +OP4 E03374 0 +OP4 E03375 0 +OP4 E03376 0 +OP4 E03377 0 +OP4 E03378 0 +OP4 E03379 0 +OP4 E0337A 0 +OP4 E0337B 0 +OP4 E0337C 0 +OP4 E0337D 0 +OP4 E0337E 0 +OP4 E0337F 0 +OP4 E03380 0 +OP4 E03381 0 +OP4 E03382 0 +OP4 E03383 0 +OP4 E03384 0 +OP4 E03385 0 +OP4 E03386 0 +OP4 E03387 0 +OP4 E03388 0 +OP4 E03389 0 +OP4 E0338A 0 +OP4 E0338B 0 +OP4 E0338C 0 +OP4 E0338D 0 +OP4 E0338E 0 +OP4 E0338F 0 +OP4 E03390 0 +OP4 E03391 0 +OP4 E03392 0 +OP4 E03393 0 +OP4 E03394 0 +OP4 E03395 0 +OP4 E03396 0 +OP4 E03397 0 +OP4 E03398 0 +OP4 E03399 0 +OP4 E0339A 0 +OP4 E0339B 0 +OP4 E0339C 0 +OP4 E0339D 0 +OP4 E0339E 0 +OP4 E0339F 0 +OP4 E033A0 0 +OP4 E033A1 0 +OP4 E033A2 0 +OP4 E033A3 0 +OP4 E033A4 0 +OP4 E033A5 0 +OP4 E033A6 0 +OP4 E033A7 0 +OP4 E033A8 0 +OP4 E033A9 0 +OP4 E033AA 0 +OP4 E033AB 0 +OP4 E033AC 0 +OP4 E033AD 0 +OP4 E033AE 0 +OP4 E033AF 0 +OP4 E033B0 0 +OP4 E033B1 0 +OP4 E033B2 0 +OP4 E033B3 0 +OP4 E033B4 0 +OP4 E033B5 0 +OP4 E033B6 0 +OP4 E033B7 0 +OP4 E033B8 0 +OP4 E033B9 0 +OP4 E033BA 0 +OP4 E033BB 0 +OP4 E033BC 0 +OP4 E033BD 0 +OP4 E033BE 0 +OP4 E033BF 0 +OP4 E033C0 0 +OP4 E033C1 0 +OP4 E033C2 0 +OP4 E033C3 0 +OP4 E033C4 0 +OP4 E033C5 0 +OP4 E033C6 0 +OP4 E033C7 0 +OP4 E033C8 0 +OP4 E033C9 0 +OP4 E033CA 0 +OP4 E033CB 0 +OP4 E033CC 0 +OP4 E033CD 0 +OP4 E033CE 0 +OP4 E033CF 0 +OP4 E033D0 0 +OP4 E033D1 0 +OP4 E033D2 0 +OP4 E033D3 0 +OP4 E033D4 0 +OP4 E033D5 0 +OP4 E033D6 0 +OP4 E033D7 0 +OP4 E033D8 0 +OP4 E033D9 0 +OP4 E033DA 0 +OP4 E033DB 0 +OP4 E033DC 0 +OP4 E033DD 0 +OP4 E033DE 0 +OP4 E033DF 0 +OP4 E033E0 0 +OP4 E033E1 0 +OP4 E033E2 0 +OP4 E033E3 0 +OP4 E033E4 0 +OP4 E033E5 0 +OP4 E033E6 0 +OP4 E033E7 0 +OP4 E033E8 0 +OP4 E033E9 0 +OP4 E033EA 0 +OP4 E033EB 0 +OP4 E033EC 0 +OP4 E033ED 0 +OP4 E033EE 0 +OP4 E033EF 0 +OP4 E033F0 0 +OP4 E033F1 0 +OP4 E033F2 0 +OP4 E033F3 0 +OP4 E033F4 0 +OP4 E033F5 0 +OP4 E033F6 0 +OP4 E033F7 0 +OP4 E033F8 0 +OP4 E033F9 0 +OP4 E033FA 0 +OP4 E033FB 0 +OP4 E033FC 0 +OP4 E033FD 0 +OP4 E033FE 0 +OP4 E033FF 0 +OP4 E03400 0 +OP4 E03401 0 +OP4 E03402 0 +OP4 E03403 0 +OP4 E03404 0 +OP4 E03405 0 +OP4 E03406 0 +OP4 E03407 0 +OP4 E03408 0 +OP4 E03409 0 +OP4 E0340A 0 +OP4 E0340B 0 +OP4 E0340C 0 +OP4 E0340D 0 +OP4 E0340E 0 +OP4 E0340F 0 +OP4 E03410 0 +OP4 E03411 0 +OP4 E03412 0 +OP4 E03413 0 +OP4 E03414 0 +OP4 E03415 0 +OP4 E03416 0 +OP4 E03417 0 +OP4 E03418 0 +OP4 E03419 0 +OP4 E0341A 0 +OP4 E0341B 0 +OP4 E0341C 0 +OP4 E0341D 0 +OP4 E0341E 0 +OP4 E0341F 0 +OP4 E03420 0 +OP4 E03421 0 +OP4 E03422 0 +OP4 E03423 0 +OP4 E03424 0 +OP4 E03425 0 +OP4 E03426 0 +OP4 E03427 0 +OP4 E03428 0 +OP4 E03429 0 +OP4 E0342A 0 +OP4 E0342B 0 +OP4 E0342C 0 +OP4 E0342D 0 +OP4 E0342E 0 +OP4 E0342F 0 +OP4 E03430 0 +OP4 E03431 0 +OP4 E03432 0 +OP4 E03433 0 +OP4 E03434 0 +OP4 E03435 0 +OP4 E03436 0 +OP4 E03437 0 +OP4 E03438 0 +OP4 E03439 0 +OP4 E0343A 0 +OP4 E0343B 0 +OP4 E0343C 0 +OP4 E0343D 0 +OP4 E0343E 0 +OP4 E0343F 0 +OP4 E03440 0 +OP4 E03441 0 +OP4 E03442 0 +OP4 E03443 0 +OP4 E03444 0 +OP4 E03445 0 +OP4 E03446 0 +OP4 E03447 0 +OP4 E03448 0 +OP4 E03449 0 +OP4 E0344A 0 +OP4 E0344B 0 +OP4 E0344C 0 +OP4 E0344D 0 +OP4 E0344E 0 +OP4 E0344F 0 +OP4 E03450 0 +OP4 E03451 0 +OP4 E03452 0 +OP4 E03453 0 +OP4 E03454 0 +OP4 E03455 0 +OP4 E03456 0 +OP4 E03457 0 +OP4 E03458 0 +OP4 E03459 0 +OP4 E0345A 0 +OP4 E0345B 0 +OP4 E0345C 0 +OP4 E0345D 0 +OP4 E0345E 0 +OP4 E0345F 0 +OP4 E03460 0 +OP4 E03461 0 +OP4 E03462 0 +OP4 E03463 0 +OP4 E03464 0 +OP4 E03465 0 +OP4 E03466 0 +OP4 E03467 0 +OP4 E03468 0 +OP4 E03469 0 +OP4 E0346A 0 +OP4 E0346B 0 +OP4 E0346C 0 +OP4 E0346D 0 +OP4 E0346E 0 +OP4 E0346F 0 +OP4 E03470 0 +OP4 E03471 0 +OP4 E03472 0 +OP4 E03473 0 +OP4 E03474 0 +OP4 E03475 0 +OP4 E03476 0 +OP4 E03477 0 +OP4 E03478 0 +OP4 E03479 0 +OP4 E0347A 0 +OP4 E0347B 0 +OP4 E0347C 0 +OP4 E0347D 0 +OP4 E0347E 0 +OP4 E0347F 0 +OP4 E03480 0 +OP4 E03481 0 +OP4 E03482 0 +OP4 E03483 0 +OP4 E03484 0 +OP4 E03485 0 +OP4 E03486 0 +OP4 E03487 0 +OP4 E03488 0 +OP4 E03489 0 +OP4 E0348A 0 +OP4 E0348B 0 +OP4 E0348C 0 +OP4 E0348D 0 +OP4 E0348E 0 +OP4 E0348F 0 +OP4 E03490 0 +OP4 E03491 0 +OP4 E03492 0 +OP4 E03493 0 +OP4 E03494 0 +OP4 E03495 0 +OP4 E03496 0 +OP4 E03497 0 +OP4 E03498 0 +OP4 E03499 0 +OP4 E0349A 0 +OP4 E0349B 0 +OP4 E0349C 0 +OP4 E0349D 0 +OP4 E0349E 0 +OP4 E0349F 0 +OP4 E034A0 0 +OP4 E034A1 0 +OP4 E034A2 0 +OP4 E034A3 0 +OP4 E034A4 0 +OP4 E034A5 0 +OP4 E034A6 0 +OP4 E034A7 0 +OP4 E034A8 0 +OP4 E034A9 0 +OP4 E034AA 0 +OP4 E034AB 0 +OP4 E034AC 0 +OP4 E034AD 0 +OP4 E034AE 0 +OP4 E034AF 0 +OP4 E034B0 0 +OP4 E034B1 0 +OP4 E034B2 0 +OP4 E034B3 0 +OP4 E034B4 0 +OP4 E034B5 0 +OP4 E034B6 0 +OP4 E034B7 0 +OP4 E034B8 0 +OP4 E034B9 0 +OP4 E034BA 0 +OP4 E034BB 0 +OP4 E034BC 0 +OP4 E034BD 0 +OP4 E034BE 0 +OP4 E034BF 0 +OP4 E034C0 0 +OP4 E034C1 0 +OP4 E034C2 0 +OP4 E034C3 0 +OP4 E034C4 0 +OP4 E034C5 0 +OP4 E034C6 0 +OP4 E034C7 0 +OP4 E034C8 0 +OP4 E034C9 0 +OP4 E034CA 0 +OP4 E034CB 0 +OP4 E034CC 0 +OP4 E034CD 0 +OP4 E034CE 0 +OP4 E034CF 0 +OP4 E034D0 0 +OP4 E034D1 0 +OP4 E034D2 0 +OP4 E034D3 0 +OP4 E034D4 0 +OP4 E034D5 0 +OP4 E034D6 0 +OP4 E034D7 0 +OP4 E034D8 0 +OP4 E034D9 0 +OP4 E034DA 0 +OP4 E034DB 0 +OP4 E034DC 0 +OP4 E034DD 0 +OP4 E034DE 0 +OP4 E034DF 0 +OP4 E034E0 0 +OP4 E034E1 0 +OP4 E034E2 0 +OP4 E034E3 0 +OP4 E034E4 0 +OP4 E034E5 0 +OP4 E034E6 0 +OP4 E034E7 0 +OP4 E034E8 0 +OP4 E034E9 0 +OP4 E034EA 0 +OP4 E034EB 0 +OP4 E034EC 0 +OP4 E034ED 0 +OP4 E034EE 0 +OP4 E034EF 0 +OP4 E034F0 0 +OP4 E034F1 0 +OP4 E034F2 0 +OP4 E034F3 0 +OP4 E034F4 0 +OP4 E034F5 0 +OP4 E034F6 0 +OP4 E034F7 0 +OP4 E034F8 0 +OP4 E034F9 0 +OP4 E034FA 0 +OP4 E034FB 0 +OP4 E034FC 0 +OP4 E034FD 0 +OP4 E034FE 0 +OP4 E034FF 0 +OP4 E03500 0 +OP4 E03501 0 +OP4 E03502 0 +OP4 E03503 0 +OP4 E03504 0 +OP4 E03505 0 +OP4 E03506 0 +OP4 E03507 0 +OP4 E03508 0 +OP4 E03509 0 +OP4 E0350A 0 +OP4 E0350B 0 +OP4 E0350C 0 +OP4 E0350D 0 +OP4 E0350E 0 +OP4 E0350F 0 +OP4 E03510 0 +OP4 E03511 0 +OP4 E03512 0 +OP4 E03513 0 +OP4 E03514 0 +OP4 E03515 0 +OP4 E03516 0 +OP4 E03517 0 +OP4 E03518 0 +OP4 E03519 0 +OP4 E0351A 0 +OP4 E0351B 0 +OP4 E0351C 0 +OP4 E0351D 0 +OP4 E0351E 0 +OP4 E0351F 0 +OP4 E03520 0 +OP4 E03521 0 +OP4 E03522 0 +OP4 E03523 0 +OP4 E03524 0 +OP4 E03525 0 +OP4 E03526 0 +OP4 E03527 0 +OP4 E03528 0 +OP4 E03529 0 +OP4 E0352A 0 +OP4 E0352B 0 +OP4 E0352C 0 +OP4 E0352D 0 +OP4 E0352E 0 +OP4 E0352F 0 +OP4 E03530 0 +OP4 E03531 0 +OP4 E03532 0 +OP4 E03533 0 +OP4 E03534 0 +OP4 E03535 0 +OP4 E03536 0 +OP4 E03537 0 +OP4 E03538 0 +OP4 E03539 0 +OP4 E0353A 0 +OP4 E0353B 0 +OP4 E0353C 0 +OP4 E0353D 0 +OP4 E0353E 0 +OP4 E0353F 0 +OP4 E03540 0 +OP4 E03541 0 +OP4 E03542 0 +OP4 E03543 0 +OP4 E03544 0 +OP4 E03545 0 +OP4 E03546 0 +OP4 E03547 0 +OP4 E03548 0 +OP4 E03549 0 +OP4 E0354A 0 +OP4 E0354B 0 +OP4 E0354C 0 +OP4 E0354D 0 +OP4 E0354E 0 +OP4 E0354F 0 +OP4 E03550 0 +OP4 E03551 0 +OP4 E03552 0 +OP4 E03553 0 +OP4 E03554 0 +OP4 E03555 0 +OP4 E03556 0 +OP4 E03557 0 +OP4 E03558 0 +OP4 E03559 0 +OP4 E0355A 0 +OP4 E0355B 0 +OP4 E0355C 0 +OP4 E0355D 0 +OP4 E0355E 0 +OP4 E0355F 0 +OP4 E03560 0 +OP4 E03561 0 +OP4 E03562 0 +OP4 E03563 0 +OP4 E03564 0 +OP4 E03565 0 +OP4 E03566 0 +OP4 E03567 0 +OP4 E03568 0 +OP4 E03569 0 +OP4 E0356A 0 +OP4 E0356B 0 +OP4 E0356C 0 +OP4 E0356D 0 +OP4 E0356E 0 +OP4 E0356F 0 +OP4 E03570 0 +OP4 E03571 0 +OP4 E03572 0 +OP4 E03573 0 +OP4 E03574 0 +OP4 E03575 0 +OP4 E03576 0 +OP4 E03577 0 +OP4 E03578 0 +OP4 E03579 0 +OP4 E0357A 0 +OP4 E0357B 0 +OP4 E0357C 0 +OP4 E0357D 0 +OP4 E0357E 0 +OP4 E0357F 0 +OP4 E03580 0 +OP4 E03581 0 +OP4 E03582 0 +OP4 E03583 0 +OP4 E03584 0 +OP4 E03585 0 +OP4 E03586 0 +OP4 E03587 0 +OP4 E03588 0 +OP4 E03589 0 +OP4 E0358A 0 +OP4 E0358B 0 +OP4 E0358C 0 +OP4 E0358D 0 +OP4 E0358E 0 +OP4 E0358F 0 +OP4 E03590 0 +OP4 E03591 0 +OP4 E03592 0 +OP4 E03593 0 +OP4 E03594 0 +OP4 E03595 0 +OP4 E03596 0 +OP4 E03597 0 +OP4 E03598 0 +OP4 E03599 0 +OP4 E0359A 0 +OP4 E0359B 0 +OP4 E0359C 0 +OP4 E0359D 0 +OP4 E0359E 0 +OP4 E0359F 0 +OP4 E035A0 0 +OP4 E035A1 0 +OP4 E035A2 0 +OP4 E035A3 0 +OP4 E035A4 0 +OP4 E035A5 0 +OP4 E035A6 0 +OP4 E035A7 0 +OP4 E035A8 0 +OP4 E035A9 0 +OP4 E035AA 0 +OP4 E035AB 0 +OP4 E035AC 0 +OP4 E035AD 0 +OP4 E035AE 0 +OP4 E035AF 0 +OP4 E035B0 0 +OP4 E035B1 0 +OP4 E035B2 0 +OP4 E035B3 0 +OP4 E035B4 0 +OP4 E035B5 0 +OP4 E035B6 0 +OP4 E035B7 0 +OP4 E035B8 0 +OP4 E035B9 0 +OP4 E035BA 0 +OP4 E035BB 0 +OP4 E035BC 0 +OP4 E035BD 0 +OP4 E035BE 0 +OP4 E035BF 0 +OP4 E035C0 0 +OP4 E035C1 0 +OP4 E035C2 0 +OP4 E035C3 0 +OP4 E035C4 0 +OP4 E035C5 0 +OP4 E035C6 0 +OP4 E035C7 0 +OP4 E035C8 0 +OP4 E035C9 0 +OP4 E035CA 0 +OP4 E035CB 0 +OP4 E035CC 0 +OP4 E035CD 0 +OP4 E035CE 0 +OP4 E035CF 0 +OP4 E035D0 0 +OP4 E035D1 0 +OP4 E035D2 0 +OP4 E035D3 0 +OP4 E035D4 0 +OP4 E035D5 0 +OP4 E035D6 0 +OP4 E035D7 0 +OP4 E035D8 0 +OP4 E035D9 0 +OP4 E035DA 0 +OP4 E035DB 0 +OP4 E035DC 0 +OP4 E035DD 0 +OP4 E035DE 0 +OP4 E035DF 0 +OP4 E035E0 0 +OP4 E035E1 0 +OP4 E035E2 0 +OP4 E035E3 0 +OP4 E035E4 0 +OP4 E035E5 0 +OP4 E035E6 0 +OP4 E035E7 0 +OP4 E035E8 0 +OP4 E035E9 0 +OP4 E035EA 0 +OP4 E035EB 0 +OP4 E035EC 0 +OP4 E035ED 0 +OP4 E035EE 0 +OP4 E035EF 0 +OP4 E035F0 0 +OP4 E035F1 0 +OP4 E035F2 0 +OP4 E035F3 0 +OP4 E035F4 0 +OP4 E035F5 0 +OP4 E035F6 0 +OP4 E035F7 0 +OP4 E035F8 0 +OP4 E035F9 0 +OP4 E035FA 0 +OP4 E035FB 0 +OP4 E035FC 0 +OP4 E035FD 0 +OP4 E035FE 0 +OP4 E035FF 0 +OP4 E03600 0 +OP4 E03601 0 +OP4 E03602 0 +OP4 E03603 0 +OP4 E03604 0 +OP4 E03605 0 +OP4 E03606 0 +OP4 E03607 0 +OP4 E03608 0 +OP4 E03609 0 +OP4 E0360A 0 +OP4 E0360B 0 +OP4 E0360C 0 +OP4 E0360D 0 +OP4 E0360E 0 +OP4 E0360F 0 +OP4 E03610 0 +OP4 E03611 0 +OP4 E03612 0 +OP4 E03613 0 +OP4 E03614 0 +OP4 E03615 0 +OP4 E03616 0 +OP4 E03617 0 +OP4 E03618 0 +OP4 E03619 0 +OP4 E0361A 0 +OP4 E0361B 0 +OP4 E0361C 0 +OP4 E0361D 0 +OP4 E0361E 0 +OP4 E0361F 0 +OP4 E03620 0 +OP4 E03621 0 +OP4 E03622 0 +OP4 E03623 0 +OP4 E03624 0 +OP4 E03625 0 +OP4 E03626 0 +OP4 E03627 0 +OP4 E03628 0 +OP4 E03629 0 +OP4 E0362A 0 +OP4 E0362B 0 +OP4 E0362C 0 +OP4 E0362D 0 +OP4 E0362E 0 +OP4 E0362F 0 +OP4 E03630 0 +OP4 E03631 0 +OP4 E03632 0 +OP4 E03633 0 +OP4 E03634 0 +OP4 E03635 0 +OP4 E03636 0 +OP4 E03637 0 +OP4 E03638 0 +OP4 E03639 0 +OP4 E0363A 0 +OP4 E0363B 0 +OP4 E0363C 0 +OP4 E0363D 0 +OP4 E0363E 0 +OP4 E0363F 0 +OP4 E03640 0 +OP4 E03641 0 +OP4 E03642 0 +OP4 E03643 0 +OP4 E03644 0 +OP4 E03645 0 +OP4 E03646 0 +OP4 E03647 0 +OP4 E03648 0 +OP4 E03649 0 +OP4 E0364A 0 +OP4 E0364B 0 +OP4 E0364C 0 +OP4 E0364D 0 +OP4 E0364E 0 +OP4 E0364F 0 +OP4 E03650 0 +OP4 E03651 0 +OP4 E03652 0 +OP4 E03653 0 +OP4 E03654 0 +OP4 E03655 0 +OP4 E03656 0 +OP4 E03657 0 +OP4 E03658 0 +OP4 E03659 0 +OP4 E0365A 0 +OP4 E0365B 0 +OP4 E0365C 0 +OP4 E0365D 0 +OP4 E0365E 0 +OP4 E0365F 0 +OP4 E03660 0 +OP4 E03661 0 +OP4 E03662 0 +OP4 E03663 0 +OP4 E03664 0 +OP4 E03665 0 +OP4 E03666 0 +OP4 E03667 0 +OP4 E03668 0 +OP4 E03669 0 +OP4 E0366A 0 +OP4 E0366B 0 +OP4 E0366C 0 +OP4 E0366D 0 +OP4 E0366E 0 +OP4 E0366F 0 +OP4 E03670 0 +OP4 E03671 0 +OP4 E03672 0 +OP4 E03673 0 +OP4 E03674 0 +OP4 E03675 0 +OP4 E03676 0 +OP4 E03677 0 +OP4 E03678 0 +OP4 E03679 0 +OP4 E0367A 0 +OP4 E0367B 0 +OP4 E0367C 0 +OP4 E0367D 0 +OP4 E0367E 0 +OP4 E0367F 0 +OP4 E03680 0 +OP4 E03681 0 +OP4 E03682 0 +OP4 E03683 0 +OP4 E03684 0 +OP4 E03685 0 +OP4 E03686 0 +OP4 E03687 0 +OP4 E03688 0 +OP4 E03689 0 +OP4 E0368A 0 +OP4 E0368B 0 +OP4 E0368C 0 +OP4 E0368D 0 +OP4 E0368E 0 +OP4 E0368F 0 +OP4 E03690 0 +OP4 E03691 0 +OP4 E03692 0 +OP4 E03693 0 +OP4 E03694 0 +OP4 E03695 0 +OP4 E03696 0 +OP4 E03697 0 +OP4 E03698 0 +OP4 E03699 0 +OP4 E0369A 0 +OP4 E0369B 0 +OP4 E0369C 0 +OP4 E0369D 0 +OP4 E0369E 0 +OP4 E0369F 0 +OP4 E036A0 0 +OP4 E036A1 0 +OP4 E036A2 0 +OP4 E036A3 0 +OP4 E036A4 0 +OP4 E036A5 0 +OP4 E036A6 0 +OP4 E036A7 0 +OP4 E036A8 0 +OP4 E036A9 0 +OP4 E036AA 0 +OP4 E036AB 0 +OP4 E036AC 0 +OP4 E036AD 0 +OP4 E036AE 0 +OP4 E036AF 0 +OP4 E036B0 0 +OP4 E036B1 0 +OP4 E036B2 0 +OP4 E036B3 0 +OP4 E036B4 0 +OP4 E036B5 0 +OP4 E036B6 0 +OP4 E036B7 0 +OP4 E036B8 0 +OP4 E036B9 0 +OP4 E036BA 0 +OP4 E036BB 0 +OP4 E036BC 0 +OP4 E036BD 0 +OP4 E036BE 0 +OP4 E036BF 0 +OP4 E036C0 0 +OP4 E036C1 0 +OP4 E036C2 0 +OP4 E036C3 0 +OP4 E036C4 0 +OP4 E036C5 0 +OP4 E036C6 0 +OP4 E036C7 0 +OP4 E036C8 0 +OP4 E036C9 0 +OP4 E036CA 0 +OP4 E036CB 0 +OP4 E036CC 0 +OP4 E036CD 0 +OP4 E036CE 0 +OP4 E036CF 0 +OP4 E036D0 0 +OP4 E036D1 0 +OP4 E036D2 0 +OP4 E036D3 0 +OP4 E036D4 0 +OP4 E036D5 0 +OP4 E036D6 0 +OP4 E036D7 0 +OP4 E036D8 0 +OP4 E036D9 0 +OP4 E036DA 0 +OP4 E036DB 0 +OP4 E036DC 0 +OP4 E036DD 0 +OP4 E036DE 0 +OP4 E036DF 0 +OP4 E036E0 0 +OP4 E036E1 0 +OP4 E036E2 0 +OP4 E036E3 0 +OP4 E036E4 0 +OP4 E036E5 0 +OP4 E036E6 0 +OP4 E036E7 0 +OP4 E036E8 0 +OP4 E036E9 0 +OP4 E036EA 0 +OP4 E036EB 0 +OP4 E036EC 0 +OP4 E036ED 0 +OP4 E036EE 0 +OP4 E036EF 0 +OP4 E036F0 0 +OP4 E036F1 0 +OP4 E036F2 0 +OP4 E036F3 0 +OP4 E036F4 0 +OP4 E036F5 0 +OP4 E036F6 0 +OP4 E036F7 0 +OP4 E036F8 0 +OP4 E036F9 0 +OP4 E036FA 0 +OP4 E036FB 0 +OP4 E036FC 0 +OP4 E036FD 0 +OP4 E036FE 0 +OP4 E036FF 0 +OP4 E03700 0 +OP4 E03701 0 +OP4 E03702 0 +OP4 E03703 0 +OP4 E03704 0 +OP4 E03705 0 +OP4 E03706 0 +OP4 E03707 0 +OP4 E03708 0 +OP4 E03709 0 +OP4 E0370A 0 +OP4 E0370B 0 +OP4 E0370C 0 +OP4 E0370D 0 +OP4 E0370E 0 +OP4 E0370F 0 +OP4 E03710 0 +OP4 E03711 0 +OP4 E03712 0 +OP4 E03713 0 +OP4 E03714 0 +OP4 E03715 0 +OP4 E03716 0 +OP4 E03717 0 +OP4 E03718 0 +OP4 E03719 0 +OP4 E0371A 0 +OP4 E0371B 0 +OP4 E0371C 0 +OP4 E0371D 0 +OP4 E0371E 0 +OP4 E0371F 0 +OP4 E03720 0 +OP4 E03721 0 +OP4 E03722 0 +OP4 E03723 0 +OP4 E03724 0 +OP4 E03725 0 +OP4 E03726 0 +OP4 E03727 0 +OP4 E03728 0 +OP4 E03729 0 +OP4 E0372A 0 +OP4 E0372B 0 +OP4 E0372C 0 +OP4 E0372D 0 +OP4 E0372E 0 +OP4 E0372F 0 +OP4 E03730 0 +OP4 E03731 0 +OP4 E03732 0 +OP4 E03733 0 +OP4 E03734 0 +OP4 E03735 0 +OP4 E03736 0 +OP4 E03737 0 +OP4 E03738 0 +OP4 E03739 0 +OP4 E0373A 0 +OP4 E0373B 0 +OP4 E0373C 0 +OP4 E0373D 0 +OP4 E0373E 0 +OP4 E0373F 0 +OP4 E03740 0 +OP4 E03741 0 +OP4 E03742 0 +OP4 E03743 0 +OP4 E03744 0 +OP4 E03745 0 +OP4 E03746 0 +OP4 E03747 0 +OP4 E03748 0 +OP4 E03749 0 +OP4 E0374A 0 +OP4 E0374B 0 +OP4 E0374C 0 +OP4 E0374D 0 +OP4 E0374E 0 +OP4 E0374F 0 +OP4 E03750 0 +OP4 E03751 0 +OP4 E03752 0 +OP4 E03753 0 +OP4 E03754 0 +OP4 E03755 0 +OP4 E03756 0 +OP4 E03757 0 +OP4 E03758 0 +OP4 E03759 0 +OP4 E0375A 0 +OP4 E0375B 0 +OP4 E0375C 0 +OP4 E0375D 0 +OP4 E0375E 0 +OP4 E0375F 0 +OP4 E03760 0 +OP4 E03761 0 +OP4 E03762 0 +OP4 E03763 0 +OP4 E03764 0 +OP4 E03765 0 +OP4 E03766 0 +OP4 E03767 0 +OP4 E03768 0 +OP4 E03769 0 +OP4 E0376A 0 +OP4 E0376B 0 +OP4 E0376C 0 +OP4 E0376D 0 +OP4 E0376E 0 +OP4 E0376F 0 +OP4 E03770 0 +OP4 E03771 0 +OP4 E03772 0 +OP4 E03773 0 +OP4 E03774 0 +OP4 E03775 0 +OP4 E03776 0 +OP4 E03777 0 +OP4 E03778 0 +OP4 E03779 0 +OP4 E0377A 0 +OP4 E0377B 0 +OP4 E0377C 0 +OP4 E0377D 0 +OP4 E0377E 0 +OP4 E0377F 0 +OP4 E03780 0 +OP4 E03781 0 +OP4 E03782 0 +OP4 E03783 0 +OP4 E03784 0 +OP4 E03785 0 +OP4 E03786 0 +OP4 E03787 0 +OP4 E03788 0 +OP4 E03789 0 +OP4 E0378A 0 +OP4 E0378B 0 +OP4 E0378C 0 +OP4 E0378D 0 +OP4 E0378E 0 +OP4 E0378F 0 +OP4 E03790 0 +OP4 E03791 0 +OP4 E03792 0 +OP4 E03793 0 +OP4 E03794 0 +OP4 E03795 0 +OP4 E03796 0 +OP4 E03797 0 +OP4 E03798 0 +OP4 E03799 0 +OP4 E0379A 0 +OP4 E0379B 0 +OP4 E0379C 0 +OP4 E0379D 0 +OP4 E0379E 0 +OP4 E0379F 0 +OP4 E037A0 0 +OP4 E037A1 0 +OP4 E037A2 0 +OP4 E037A3 0 +OP4 E037A4 0 +OP4 E037A5 0 +OP4 E037A6 0 +OP4 E037A7 0 +OP4 E037A8 0 +OP4 E037A9 0 +OP4 E037AA 0 +OP4 E037AB 0 +OP4 E037AC 0 +OP4 E037AD 0 +OP4 E037AE 0 +OP4 E037AF 0 +OP4 E037B0 0 +OP4 E037B1 0 +OP4 E037B2 0 +OP4 E037B3 0 +OP4 E037B4 0 +OP4 E037B5 0 +OP4 E037B6 0 +OP4 E037B7 0 +OP4 E037B8 0 +OP4 E037B9 0 +OP4 E037BA 0 +OP4 E037BB 0 +OP4 E037BC 0 +OP4 E037BD 0 +OP4 E037BE 0 +OP4 E037BF 0 +OP4 E037C0 0 +OP4 E037C1 0 +OP4 E037C2 0 +OP4 E037C3 0 +OP4 E037C4 0 +OP4 E037C5 0 +OP4 E037C6 0 +OP4 E037C7 0 +OP4 E037C8 0 +OP4 E037C9 0 +OP4 E037CA 0 +OP4 E037CB 0 +OP4 E037CC 0 +OP4 E037CD 0 +OP4 E037CE 0 +OP4 E037CF 0 +OP4 E037D0 0 +OP4 E037D1 0 +OP4 E037D2 0 +OP4 E037D3 0 +OP4 E037D4 0 +OP4 E037D5 0 +OP4 E037D6 0 +OP4 E037D7 0 +OP4 E037D8 0 +OP4 E037D9 0 +OP4 E037DA 0 +OP4 E037DB 0 +OP4 E037DC 0 +OP4 E037DD 0 +OP4 E037DE 0 +OP4 E037DF 0 +OP4 E037E0 0 +OP4 E037E1 0 +OP4 E037E2 0 +OP4 E037E3 0 +OP4 E037E4 0 +OP4 E037E5 0 +OP4 E037E6 0 +OP4 E037E7 0 +OP4 E037E8 0 +OP4 E037E9 0 +OP4 E037EA 0 +OP4 E037EB 0 +OP4 E037EC 0 +OP4 E037ED 0 +OP4 E037EE 0 +OP4 E037EF 0 +OP4 E037F0 0 +OP4 E037F1 0 +OP4 E037F2 0 +OP4 E037F3 0 +OP4 E037F4 0 +OP4 E037F5 0 +OP4 E037F6 0 +OP4 E037F7 0 +OP4 E037F8 0 +OP4 E037F9 0 +OP4 E037FA 0 +OP4 E037FB 0 +OP4 E037FC 0 +OP4 E037FD 0 +OP4 E037FE 0 +OP4 E037FF 0 +OP4 E03800 0 +OP4 E03801 0 +OP4 E03802 0 +OP4 E03803 0 +OP4 E03804 0 +OP4 E03805 0 +OP4 E03806 0 +OP4 E03807 0 +OP4 E03808 0 +OP4 E03809 0 +OP4 E0380A 0 +OP4 E0380B 0 +OP4 E0380C 0 +OP4 E0380D 0 +OP4 E0380E 0 +OP4 E0380F 0 +OP4 E03810 0 +OP4 E03811 0 +OP4 E03812 0 +OP4 E03813 0 +OP4 E03814 0 +OP4 E03815 0 +OP4 E03816 0 +OP4 E03817 0 +OP4 E03818 0 +OP4 E03819 0 +OP4 E0381A 0 +OP4 E0381B 0 +OP4 E0381C 0 +OP4 E0381D 0 +OP4 E0381E 0 +OP4 E0381F 0 +OP4 E03820 0 +OP4 E03821 0 +OP4 E03822 0 +OP4 E03823 0 +OP4 E03824 0 +OP4 E03825 0 +OP4 E03826 0 +OP4 E03827 0 +OP4 E03828 0 +OP4 E03829 0 +OP4 E0382A 0 +OP4 E0382B 0 +OP4 E0382C 0 +OP4 E0382D 0 +OP4 E0382E 0 +OP4 E0382F 0 +OP4 E03830 0 +OP4 E03831 0 +OP4 E03832 0 +OP4 E03833 0 +OP4 E03834 0 +OP4 E03835 0 +OP4 E03836 0 +OP4 E03837 0 +OP4 E03838 0 +OP4 E03839 0 +OP4 E0383A 0 +OP4 E0383B 0 +OP4 E0383C 0 +OP4 E0383D 0 +OP4 E0383E 0 +OP4 E0383F 0 +OP4 E03840 0 +OP4 E03841 0 +OP4 E03842 0 +OP4 E03843 0 +OP4 E03844 0 +OP4 E03845 0 +OP4 E03846 0 +OP4 E03847 0 +OP4 E03848 0 +OP4 E03849 0 +OP4 E0384A 0 +OP4 E0384B 0 +OP4 E0384C 0 +OP4 E0384D 0 +OP4 E0384E 0 +OP4 E0384F 0 +OP4 E03850 0 +OP4 E03851 0 +OP4 E03852 0 +OP4 E03853 0 +OP4 E03854 0 +OP4 E03855 0 +OP4 E03856 0 +OP4 E03857 0 +OP4 E03858 0 +OP4 E03859 0 +OP4 E0385A 0 +OP4 E0385B 0 +OP4 E0385C 0 +OP4 E0385D 0 +OP4 E0385E 0 +OP4 E0385F 0 +OP4 E03860 0 +OP4 E03861 0 +OP4 E03862 0 +OP4 E03863 0 +OP4 E03864 0 +OP4 E03865 0 +OP4 E03866 0 +OP4 E03867 0 +OP4 E03868 0 +OP4 E03869 0 +OP4 E0386A 0 +OP4 E0386B 0 +OP4 E0386C 0 +OP4 E0386D 0 +OP4 E0386E 0 +OP4 E0386F 0 +OP4 E03870 0 +OP4 E03871 0 +OP4 E03872 0 +OP4 E03873 0 +OP4 E03874 0 +OP4 E03875 0 +OP4 E03876 0 +OP4 E03877 0 +OP4 E03878 0 +OP4 E03879 0 +OP4 E0387A 0 +OP4 E0387B 0 +OP4 E0387C 0 +OP4 E0387D 0 +OP4 E0387E 0 +OP4 E0387F 0 +OP4 E03880 0 +OP4 E03881 0 +OP4 E03882 0 +OP4 E03883 0 +OP4 E03884 0 +OP4 E03885 0 +OP4 E03886 0 +OP4 E03887 0 +OP4 E03888 0 +OP4 E03889 0 +OP4 E0388A 0 +OP4 E0388B 0 +OP4 E0388C 0 +OP4 E0388D 0 +OP4 E0388E 0 +OP4 E0388F 0 +OP4 E03890 0 +OP4 E03891 0 +OP4 E03892 0 +OP4 E03893 0 +OP4 E03894 0 +OP4 E03895 0 +OP4 E03896 0 +OP4 E03897 0 +OP4 E03898 0 +OP4 E03899 0 +OP4 E0389A 0 +OP4 E0389B 0 +OP4 E0389C 0 +OP4 E0389D 0 +OP4 E0389E 0 +OP4 E0389F 0 +OP4 E038A0 0 +OP4 E038A1 0 +OP4 E038A2 0 +OP4 E038A3 0 +OP4 E038A4 0 +OP4 E038A5 0 +OP4 E038A6 0 +OP4 E038A7 0 +OP4 E038A8 0 +OP4 E038A9 0 +OP4 E038AA 0 +OP4 E038AB 0 +OP4 E038AC 0 +OP4 E038AD 0 +OP4 E038AE 0 +OP4 E038AF 0 +OP4 E038B0 0 +OP4 E038B1 0 +OP4 E038B2 0 +OP4 E038B3 0 +OP4 E038B4 0 +OP4 E038B5 0 +OP4 E038B6 0 +OP4 E038B7 0 +OP4 E038B8 0 +OP4 E038B9 0 +OP4 E038BA 0 +OP4 E038BB 0 +OP4 E038BC 0 +OP4 E038BD 0 +OP4 E038BE 0 +OP4 E038BF 0 +OP4 E038C0 0 +OP4 E038C1 0 +OP4 E038C2 0 +OP4 E038C3 0 +OP4 E038C4 0 +OP4 E038C5 0 +OP4 E038C6 0 +OP4 E038C7 0 +OP4 E038C8 0 +OP4 E038C9 0 +OP4 E038CA 0 +OP4 E038CB 0 +OP4 E038CC 0 +OP4 E038CD 0 +OP4 E038CE 0 +OP4 E038CF 0 +OP4 E038D0 0 +OP4 E038D1 0 +OP4 E038D2 0 +OP4 E038D3 0 +OP4 E038D4 0 +OP4 E038D5 0 +OP4 E038D6 0 +OP4 E038D7 0 +OP4 E038D8 0 +OP4 E038D9 0 +OP4 E038DA 0 +OP4 E038DB 0 +OP4 E038DC 0 +OP4 E038DD 0 +OP4 E038DE 0 +OP4 E038DF 0 +OP4 E038E0 0 +OP4 E038E1 0 +OP4 E038E2 0 +OP4 E038E3 0 +OP4 E038E4 0 +OP4 E038E5 0 +OP4 E038E6 0 +OP4 E038E7 0 +OP4 E038E8 0 +OP4 E038E9 0 +OP4 E038EA 0 +OP4 E038EB 0 +OP4 E038EC 0 +OP4 E038ED 0 +OP4 E038EE 0 +OP4 E038EF 0 +OP4 E038F0 0 +OP4 E038F1 0 +OP4 E038F2 0 +OP4 E038F3 0 +OP4 E038F4 0 +OP4 E038F5 0 +OP4 E038F6 0 +OP4 E038F7 0 +OP4 E038F8 0 +OP4 E038F9 0 +OP4 E038FA 0 +OP4 E038FB 0 +OP4 E038FC 0 +OP4 E038FD 0 +OP4 E038FE 0 +OP4 E038FF 0 +OP4 E03900 0 +OP4 E03901 0 +OP4 E03902 0 +OP4 E03903 0 +OP4 E03904 0 +OP4 E03905 0 +OP4 E03906 0 +OP4 E03907 0 +OP4 E03908 0 +OP4 E03909 0 +OP4 E0390A 0 +OP4 E0390B 0 +OP4 E0390C 0 +OP4 E0390D 0 +OP4 E0390E 0 +OP4 E0390F 0 +OP4 E03910 0 +OP4 E03911 0 +OP4 E03912 0 +OP4 E03913 0 +OP4 E03914 0 +OP4 E03915 0 +OP4 E03916 0 +OP4 E03917 0 +OP4 E03918 0 +OP4 E03919 0 +OP4 E0391A 0 +OP4 E0391B 0 +OP4 E0391C 0 +OP4 E0391D 0 +OP4 E0391E 0 +OP4 E0391F 0 +OP4 E03920 0 +OP4 E03921 0 +OP4 E03922 0 +OP4 E03923 0 +OP4 E03924 0 +OP4 E03925 0 +OP4 E03926 0 +OP4 E03927 0 +OP4 E03928 0 +OP4 E03929 0 +OP4 E0392A 0 +OP4 E0392B 0 +OP4 E0392C 0 +OP4 E0392D 0 +OP4 E0392E 0 +OP4 E0392F 0 +OP4 E03930 0 +OP4 E03931 0 +OP4 E03932 0 +OP4 E03933 0 +OP4 E03934 0 +OP4 E03935 0 +OP4 E03936 0 +OP4 E03937 0 +OP4 E03938 0 +OP4 E03939 0 +OP4 E0393A 0 +OP4 E0393B 0 +OP4 E0393C 0 +OP4 E0393D 0 +OP4 E0393E 0 +OP4 E0393F 0 +OP4 E03940 0 +OP4 E03941 0 +OP4 E03942 0 +OP4 E03943 0 +OP4 E03944 0 +OP4 E03945 0 +OP4 E03946 0 +OP4 E03947 0 +OP4 E03948 0 +OP4 E03949 0 +OP4 E0394A 0 +OP4 E0394B 0 +OP4 E0394C 0 +OP4 E0394D 0 +OP4 E0394E 0 +OP4 E0394F 0 +OP4 E03950 0 +OP4 E03951 0 +OP4 E03952 0 +OP4 E03953 0 +OP4 E03954 0 +OP4 E03955 0 +OP4 E03956 0 +OP4 E03957 0 +OP4 E03958 0 +OP4 E03959 0 +OP4 E0395A 0 +OP4 E0395B 0 +OP4 E0395C 0 +OP4 E0395D 0 +OP4 E0395E 0 +OP4 E0395F 0 +OP4 E03960 0 +OP4 E03961 0 +OP4 E03962 0 +OP4 E03963 0 +OP4 E03964 0 +OP4 E03965 0 +OP4 E03966 0 +OP4 E03967 0 +OP4 E03968 0 +OP4 E03969 0 +OP4 E0396A 0 +OP4 E0396B 0 +OP4 E0396C 0 +OP4 E0396D 0 +OP4 E0396E 0 +OP4 E0396F 0 +OP4 E03970 0 +OP4 E03971 0 +OP4 E03972 0 +OP4 E03973 0 +OP4 E03974 0 +OP4 E03975 0 +OP4 E03976 0 +OP4 E03977 0 +OP4 E03978 0 +OP4 E03979 0 +OP4 E0397A 0 +OP4 E0397B 0 +OP4 E0397C 0 +OP4 E0397D 0 +OP4 E0397E 0 +OP4 E0397F 0 +OP4 E03980 0 +OP4 E03981 0 +OP4 E03982 0 +OP4 E03983 0 +OP4 E03984 0 +OP4 E03985 0 +OP4 E03986 0 +OP4 E03987 0 +OP4 E03988 0 +OP4 E03989 0 +OP4 E0398A 0 +OP4 E0398B 0 +OP4 E0398C 0 +OP4 E0398D 0 +OP4 E0398E 0 +OP4 E0398F 0 +OP4 E03990 0 +OP4 E03991 0 +OP4 E03992 0 +OP4 E03993 0 +OP4 E03994 0 +OP4 E03995 0 +OP4 E03996 0 +OP4 E03997 0 +OP4 E03998 0 +OP4 E03999 0 +OP4 E0399A 0 +OP4 E0399B 0 +OP4 E0399C 0 +OP4 E0399D 0 +OP4 E0399E 0 +OP4 E0399F 0 +OP4 E039A0 0 +OP4 E039A1 0 +OP4 E039A2 0 +OP4 E039A3 0 +OP4 E039A4 0 +OP4 E039A5 0 +OP4 E039A6 0 +OP4 E039A7 0 +OP4 E039A8 0 +OP4 E039A9 0 +OP4 E039AA 0 +OP4 E039AB 0 +OP4 E039AC 0 +OP4 E039AD 0 +OP4 E039AE 0 +OP4 E039AF 0 +OP4 E039B0 0 +OP4 E039B1 0 +OP4 E039B2 0 +OP4 E039B3 0 +OP4 E039B4 0 +OP4 E039B5 0 +OP4 E039B6 0 +OP4 E039B7 0 +OP4 E039B8 0 +OP4 E039B9 0 +OP4 E039BA 0 +OP4 E039BB 0 +OP4 E039BC 0 +OP4 E039BD 0 +OP4 E039BE 0 +OP4 E039BF 0 +OP4 E039C0 0 +OP4 E039C1 0 +OP4 E039C2 0 +OP4 E039C3 0 +OP4 E039C4 0 +OP4 E039C5 0 +OP4 E039C6 0 +OP4 E039C7 0 +OP4 E039C8 0 +OP4 E039C9 0 +OP4 E039CA 0 +OP4 E039CB 0 +OP4 E039CC 0 +OP4 E039CD 0 +OP4 E039CE 0 +OP4 E039CF 0 +OP4 E039D0 0 +OP4 E039D1 0 +OP4 E039D2 0 +OP4 E039D3 0 +OP4 E039D4 0 +OP4 E039D5 0 +OP4 E039D6 0 +OP4 E039D7 0 +OP4 E039D8 0 +OP4 E039D9 0 +OP4 E039DA 0 +OP4 E039DB 0 +OP4 E039DC 0 +OP4 E039DD 0 +OP4 E039DE 0 +OP4 E039DF 0 +OP4 E039E0 0 +OP4 E039E1 0 +OP4 E039E2 0 +OP4 E039E3 0 +OP4 E039E4 0 +OP4 E039E5 0 +OP4 E039E6 0 +OP4 E039E7 0 +OP4 E039E8 0 +OP4 E039E9 0 +OP4 E039EA 0 +OP4 E039EB 0 +OP4 E039EC 0 +OP4 E039ED 0 +OP4 E039EE 0 +OP4 E039EF 0 +OP4 E039F0 0 +OP4 E039F1 0 +OP4 E039F2 0 +OP4 E039F3 0 +OP4 E039F4 0 +OP4 E039F5 0 +OP4 E039F6 0 +OP4 E039F7 0 +OP4 E039F8 0 +OP4 E039F9 0 +OP4 E039FA 0 +OP4 E039FB 0 +OP4 E039FC 0 +OP4 E039FD 0 +OP4 E039FE 0 +OP4 E039FF 0 +OP4 E03A00 0 +OP4 E03A01 0 +OP4 E03A02 0 +OP4 E03A03 0 +OP4 E03A04 0 +OP4 E03A05 0 +OP4 E03A06 0 +OP4 E03A07 0 +OP4 E03A08 0 +OP4 E03A09 0 +OP4 E03A0A 0 +OP4 E03A0B 0 +OP4 E03A0C 0 +OP4 E03A0D 0 +OP4 E03A0E 0 +OP4 E03A0F 0 +OP4 E03A10 0 +OP4 E03A11 0 +OP4 E03A12 0 +OP4 E03A13 0 +OP4 E03A14 0 +OP4 E03A15 0 +OP4 E03A16 0 +OP4 E03A17 0 +OP4 E03A18 0 +OP4 E03A19 0 +OP4 E03A1A 0 +OP4 E03A1B 0 +OP4 E03A1C 0 +OP4 E03A1D 0 +OP4 E03A1E 0 +OP4 E03A1F 0 +OP4 E03A20 0 +OP4 E03A21 0 +OP4 E03A22 0 +OP4 E03A23 0 +OP4 E03A24 0 +OP4 E03A25 0 +OP4 E03A26 0 +OP4 E03A27 0 +OP4 E03A28 0 +OP4 E03A29 0 +OP4 E03A2A 0 +OP4 E03A2B 0 +OP4 E03A2C 0 +OP4 E03A2D 0 +OP4 E03A2E 0 +OP4 E03A2F 0 +OP4 E03A30 0 +OP4 E03A31 0 +OP4 E03A32 0 +OP4 E03A33 0 +OP4 E03A34 0 +OP4 E03A35 0 +OP4 E03A36 0 +OP4 E03A37 0 +OP4 E03A38 0 +OP4 E03A39 0 +OP4 E03A3A 0 +OP4 E03A3B 0 +OP4 E03A3C 0 +OP4 E03A3D 0 +OP4 E03A3E 0 +OP4 E03A3F 0 +OP4 E03A40 0 +OP4 E03A41 0 +OP4 E03A42 0 +OP4 E03A43 0 +OP4 E03A44 0 +OP4 E03A45 0 +OP4 E03A46 0 +OP4 E03A47 0 +OP4 E03A48 0 +OP4 E03A49 0 +OP4 E03A4A 0 +OP4 E03A4B 0 +OP4 E03A4C 0 +OP4 E03A4D 0 +OP4 E03A4E 0 +OP4 E03A4F 0 +OP4 E03A50 0 +OP4 E03A51 0 +OP4 E03A52 0 +OP4 E03A53 0 +OP4 E03A54 0 +OP4 E03A55 0 +OP4 E03A56 0 +OP4 E03A57 0 +OP4 E03A58 0 +OP4 E03A59 0 +OP4 E03A5A 0 +OP4 E03A5B 0 +OP4 E03A5C 0 +OP4 E03A5D 0 +OP4 E03A5E 0 +OP4 E03A5F 0 +OP4 E03A60 0 +OP4 E03A61 0 +OP4 E03A62 0 +OP4 E03A63 0 +OP4 E03A64 0 +OP4 E03A65 0 +OP4 E03A66 0 +OP4 E03A67 0 +OP4 E03A68 0 +OP4 E03A69 0 +OP4 E03A6A 0 +OP4 E03A6B 0 +OP4 E03A6C 0 +OP4 E03A6D 0 +OP4 E03A6E 0 +OP4 E03A6F 0 +OP4 E03A70 0 +OP4 E03A71 0 +OP4 E03A72 0 +OP4 E03A73 0 +OP4 E03A74 0 +OP4 E03A75 0 +OP4 E03A76 0 +OP4 E03A77 0 +OP4 E03A78 0 +OP4 E03A79 0 +OP4 E03A7A 0 +OP4 E03A7B 0 +OP4 E03A7C 0 +OP4 E03A7D 0 +OP4 E03A7E 0 +OP4 E03A7F 0 +OP4 E03A80 0 +OP4 E03A81 0 +OP4 E03A82 0 +OP4 E03A83 0 +OP4 E03A84 0 +OP4 E03A85 0 +OP4 E03A86 0 +OP4 E03A87 0 +OP4 E03A88 0 +OP4 E03A89 0 +OP4 E03A8A 0 +OP4 E03A8B 0 +OP4 E03A8C 0 +OP4 E03A8D 0 +OP4 E03A8E 0 +OP4 E03A8F 0 +OP4 E03A90 0 +OP4 E03A91 0 +OP4 E03A92 0 +OP4 E03A93 0 +OP4 E03A94 0 +OP4 E03A95 0 +OP4 E03A96 0 +OP4 E03A97 0 +OP4 E03A98 0 +OP4 E03A99 0 +OP4 E03A9A 0 +OP4 E03A9B 0 +OP4 E03A9C 0 +OP4 E03A9D 0 +OP4 E03A9E 0 +OP4 E03A9F 0 +OP4 E03AA0 0 +OP4 E03AA1 0 +OP4 E03AA2 0 +OP4 E03AA3 0 +OP4 E03AA4 0 +OP4 E03AA5 0 +OP4 E03AA6 0 +OP4 E03AA7 0 +OP4 E03AA8 0 +OP4 E03AA9 0 +OP4 E03AAA 0 +OP4 E03AAB 0 +OP4 E03AAC 0 +OP4 E03AAD 0 +OP4 E03AAE 0 +OP4 E03AAF 0 +OP4 E03AB0 0 +OP4 E03AB1 0 +OP4 E03AB2 0 +OP4 E03AB3 0 +OP4 E03AB4 0 +OP4 E03AB5 0 +OP4 E03AB6 0 +OP4 E03AB7 0 +OP4 E03AB8 0 +OP4 E03AB9 0 +OP4 E03ABA 0 +OP4 E03ABB 0 +OP4 E03ABC 0 +OP4 E03ABD 0 +OP4 E03ABE 0 +OP4 E03ABF 0 +OP4 E03AC0 0 +OP4 E03AC1 0 +OP4 E03AC2 0 +OP4 E03AC3 0 +OP4 E03AC4 0 +OP4 E03AC5 0 +OP4 E03AC6 0 +OP4 E03AC7 0 +OP4 E03AC8 0 +OP4 E03AC9 0 +OP4 E03ACA 0 +OP4 E03ACB 0 +OP4 E03ACC 0 +OP4 E03ACD 0 +OP4 E03ACE 0 +OP4 E03ACF 0 +OP4 E03AD0 0 +OP4 E03AD1 0 +OP4 E03AD2 0 +OP4 E03AD3 0 +OP4 E03AD4 0 +OP4 E03AD5 0 +OP4 E03AD6 0 +OP4 E03AD7 0 +OP4 E03AD8 0 +OP4 E03AD9 0 +OP4 E03ADA 0 +OP4 E03ADB 0 +OP4 E03ADC 0 +OP4 E03ADD 0 +OP4 E03ADE 0 +OP4 E03ADF 0 +OP4 E03AE0 0 +OP4 E03AE1 0 +OP4 E03AE2 0 +OP4 E03AE3 0 +OP4 E03AE4 0 +OP4 E03AE5 0 +OP4 E03AE6 0 +OP4 E03AE7 0 +OP4 E03AE8 0 +OP4 E03AE9 0 +OP4 E03AEA 0 +OP4 E03AEB 0 +OP4 E03AEC 0 +OP4 E03AED 0 +OP4 E03AEE 0 +OP4 E03AEF 0 +OP4 E03AF0 0 +OP4 E03AF1 0 +OP4 E03AF2 0 +OP4 E03AF3 0 +OP4 E03AF4 0 +OP4 E03AF5 0 +OP4 E03AF6 0 +OP4 E03AF7 0 +OP4 E03AF8 0 +OP4 E03AF9 0 +OP4 E03AFA 0 +OP4 E03AFB 0 +OP4 E03AFC 0 +OP4 E03AFD 0 +OP4 E03AFE 0 +OP4 E03AFF 0 +OP4 E03B00 0 +OP4 E03B01 0 +OP4 E03B02 0 +OP4 E03B03 0 +OP4 E03B04 0 +OP4 E03B05 0 +OP4 E03B06 0 +OP4 E03B07 0 +OP4 E03B08 0 +OP4 E03B09 0 +OP4 E03B0A 0 +OP4 E03B0B 0 +OP4 E03B0C 0 +OP4 E03B0D 0 +OP4 E03B0E 0 +OP4 E03B0F 0 +OP4 E03B10 0 +OP4 E03B11 0 +OP4 E03B12 0 +OP4 E03B13 0 +OP4 E03B14 0 +OP4 E03B15 0 +OP4 E03B16 0 +OP4 E03B17 0 +OP4 E03B18 0 +OP4 E03B19 0 +OP4 E03B1A 0 +OP4 E03B1B 0 +OP4 E03B1C 0 +OP4 E03B1D 0 +OP4 E03B1E 0 +OP4 E03B1F 0 +OP4 E03B20 0 +OP4 E03B21 0 +OP4 E03B22 0 +OP4 E03B23 0 +OP4 E03B24 0 +OP4 E03B25 0 +OP4 E03B26 0 +OP4 E03B27 0 +OP4 E03B28 0 +OP4 E03B29 0 +OP4 E03B2A 0 +OP4 E03B2B 0 +OP4 E03B2C 0 +OP4 E03B2D 0 +OP4 E03B2E 0 +OP4 E03B2F 0 +OP4 E03B30 0 +OP4 E03B31 0 +OP4 E03B32 0 +OP4 E03B33 0 +OP4 E03B34 0 +OP4 E03B35 0 +OP4 E03B36 0 +OP4 E03B37 0 +OP4 E03B38 0 +OP4 E03B39 0 +OP4 E03B3A 0 +OP4 E03B3B 0 +OP4 E03B3C 0 +OP4 E03B3D 0 +OP4 E03B3E 0 +OP4 E03B3F 0 +OP4 E03B40 0 +OP4 E03B41 0 +OP4 E03B42 0 +OP4 E03B43 0 +OP4 E03B44 0 +OP4 E03B45 0 +OP4 E03B46 0 +OP4 E03B47 0 +OP4 E03B48 0 +OP4 E03B49 0 +OP4 E03B4A 0 +OP4 E03B4B 0 +OP4 E03B4C 0 +OP4 E03B4D 0 +OP4 E03B4E 0 +OP4 E03B4F 0 +OP4 E03B50 0 +OP4 E03B51 0 +OP4 E03B52 0 +OP4 E03B53 0 +OP4 E03B54 0 +OP4 E03B55 0 +OP4 E03B56 0 +OP4 E03B57 0 +OP4 E03B58 0 +OP4 E03B59 0 +OP4 E03B5A 0 +OP4 E03B5B 0 +OP4 E03B5C 0 +OP4 E03B5D 0 +OP4 E03B5E 0 +OP4 E03B5F 0 +OP4 E03B60 0 +OP4 E03B61 0 +OP4 E03B62 0 +OP4 E03B63 0 +OP4 E03B64 0 +OP4 E03B65 0 +OP4 E03B66 0 +OP4 E03B67 0 +OP4 E03B68 0 +OP4 E03B69 0 +OP4 E03B6A 0 +OP4 E03B6B 0 +OP4 E03B6C 0 +OP4 E03B6D 0 +OP4 E03B6E 0 +OP4 E03B6F 0 +OP4 E03B70 0 +OP4 E03B71 0 +OP4 E03B72 0 +OP4 E03B73 0 +OP4 E03B74 0 +OP4 E03B75 0 +OP4 E03B76 0 +OP4 E03B77 0 +OP4 E03B78 0 +OP4 E03B79 0 +OP4 E03B7A 0 +OP4 E03B7B 0 +OP4 E03B7C 0 +OP4 E03B7D 0 +OP4 E03B7E 0 +OP4 E03B7F 0 +OP4 E03B80 0 +OP4 E03B81 0 +OP4 E03B82 0 +OP4 E03B83 0 +OP4 E03B84 0 +OP4 E03B85 0 +OP4 E03B86 0 +OP4 E03B87 0 +OP4 E03B88 0 +OP4 E03B89 0 +OP4 E03B8A 0 +OP4 E03B8B 0 +OP4 E03B8C 0 +OP4 E03B8D 0 +OP4 E03B8E 0 +OP4 E03B8F 0 +OP4 E03B90 0 +OP4 E03B91 0 +OP4 E03B92 0 +OP4 E03B93 0 +OP4 E03B94 0 +OP4 E03B95 0 +OP4 E03B96 0 +OP4 E03B97 0 +OP4 E03B98 0 +OP4 E03B99 0 +OP4 E03B9A 0 +OP4 E03B9B 0 +OP4 E03B9C 0 +OP4 E03B9D 0 +OP4 E03B9E 0 +OP4 E03B9F 0 +OP4 E03BA0 0 +OP4 E03BA1 0 +OP4 E03BA2 0 +OP4 E03BA3 0 +OP4 E03BA4 0 +OP4 E03BA5 0 +OP4 E03BA6 0 +OP4 E03BA7 0 +OP4 E03BA8 0 +OP4 E03BA9 0 +OP4 E03BAA 0 +OP4 E03BAB 0 +OP4 E03BAC 0 +OP4 E03BAD 0 +OP4 E03BAE 0 +OP4 E03BAF 0 +OP4 E03BB0 0 +OP4 E03BB1 0 +OP4 E03BB2 0 +OP4 E03BB3 0 +OP4 E03BB4 0 +OP4 E03BB5 0 +OP4 E03BB6 0 +OP4 E03BB7 0 +OP4 E03BB8 0 +OP4 E03BB9 0 +OP4 E03BBA 0 +OP4 E03BBB 0 +OP4 E03BBC 0 +OP4 E03BBD 0 +OP4 E03BBE 0 +OP4 E03BBF 0 +OP4 E03BC0 0 +OP4 E03BC1 0 +OP4 E03BC2 0 +OP4 E03BC3 0 +OP4 E03BC4 0 +OP4 E03BC5 0 +OP4 E03BC6 0 +OP4 E03BC7 0 +OP4 E03BC8 0 +OP4 E03BC9 0 +OP4 E03BCA 0 +OP4 E03BCB 0 +OP4 E03BCC 0 +OP4 E03BCD 0 +OP4 E03BCE 0 +OP4 E03BCF 0 +OP4 E03BD0 0 +OP4 E03BD1 0 +OP4 E03BD2 0 +OP4 E03BD3 0 +OP4 E03BD4 0 +OP4 E03BD5 0 +OP4 E03BD6 0 +OP4 E03BD7 0 +OP4 E03BD8 0 +OP4 E03BD9 0 +OP4 E03BDA 0 +OP4 E03BDB 0 +OP4 E03BDC 0 +OP4 E03BDD 0 +OP4 E03BDE 0 +OP4 E03BDF 0 +OP4 E03BE0 0 +OP4 E03BE1 0 +OP4 E03BE2 0 +OP4 E03BE3 0 +OP4 E03BE4 0 +OP4 E03BE5 0 +OP4 E03BE6 0 +OP4 E03BE7 0 +OP4 E03BE8 0 +OP4 E03BE9 0 +OP4 E03BEA 0 +OP4 E03BEB 0 +OP4 E03BEC 0 +OP4 E03BED 0 +OP4 E03BEE 0 +OP4 E03BEF 0 +OP4 E03BF0 0 +OP4 E03BF1 0 +OP4 E03BF2 0 +OP4 E03BF3 0 +OP4 E03BF4 0 +OP4 E03BF5 0 +OP4 E03BF6 0 +OP4 E03BF7 0 +OP4 E03BF8 0 +OP4 E03BF9 0 +OP4 E03BFA 0 +OP4 E03BFB 0 +OP4 E03BFC 0 +OP4 E03BFD 0 +OP4 E03BFE 0 +OP4 E03BFF 0 +OP4 E03C00 0 +OP4 E03C01 0 +OP4 E03C02 0 +OP4 E03C03 0 +OP4 E03C04 0 +OP4 E03C05 0 +OP4 E03C06 0 +OP4 E03C07 0 +OP4 E03C08 0 +OP4 E03C09 0 +OP4 E03C0A 0 +OP4 E03C0B 0 +OP4 E03C0C 0 +OP4 E03C0D 0 +OP4 E03C0E 0 +OP4 E03C0F 0 +OP4 E03C10 0 +OP4 E03C11 0 +OP4 E03C12 0 +OP4 E03C13 0 +OP4 E03C14 0 +OP4 E03C15 0 +OP4 E03C16 0 +OP4 E03C17 0 +OP4 E03C18 0 +OP4 E03C19 0 +OP4 E03C1A 0 +OP4 E03C1B 0 +OP4 E03C1C 0 +OP4 E03C1D 0 +OP4 E03C1E 0 +OP4 E03C1F 0 +OP4 E03C20 0 +OP4 E03C21 0 +OP4 E03C22 0 +OP4 E03C23 0 +OP4 E03C24 0 +OP4 E03C25 0 +OP4 E03C26 0 +OP4 E03C27 0 +OP4 E03C28 0 +OP4 E03C29 0 +OP4 E03C2A 0 +OP4 E03C2B 0 +OP4 E03C2C 0 +OP4 E03C2D 0 +OP4 E03C2E 0 +OP4 E03C2F 0 +OP4 E03C30 0 +OP4 E03C31 0 +OP4 E03C32 0 +OP4 E03C33 0 +OP4 E03C34 0 +OP4 E03C35 0 +OP4 E03C36 0 +OP4 E03C37 0 +OP4 E03C38 0 +OP4 E03C39 0 +OP4 E03C3A 0 +OP4 E03C3B 0 +OP4 E03C3C 0 +OP4 E03C3D 0 +OP4 E03C3E 0 +OP4 E03C3F 0 +OP4 E03C40 0 +OP4 E03C41 0 +OP4 E03C42 0 +OP4 E03C43 0 +OP4 E03C44 0 +OP4 E03C45 0 +OP4 E03C46 0 +OP4 E03C47 0 +OP4 E03C48 0 +OP4 E03C49 0 +OP4 E03C4A 0 +OP4 E03C4B 0 +OP4 E03C4C 0 +OP4 E03C4D 0 +OP4 E03C4E 0 +OP4 E03C4F 0 +OP4 E03C50 0 +OP4 E03C51 0 +OP4 E03C52 0 +OP4 E03C53 0 +OP4 E03C54 0 +OP4 E03C55 0 +OP4 E03C56 0 +OP4 E03C57 0 +OP4 E03C58 0 +OP4 E03C59 0 +OP4 E03C5A 0 +OP4 E03C5B 0 +OP4 E03C5C 0 +OP4 E03C5D 0 +OP4 E03C5E 0 +OP4 E03C5F 0 +OP4 E03C60 0 +OP4 E03C61 0 +OP4 E03C62 0 +OP4 E03C63 0 +OP4 E03C64 0 +OP4 E03C65 0 +OP4 E03C66 0 +OP4 E03C67 0 +OP4 E03C68 0 +OP4 E03C69 0 +OP4 E03C6A 0 +OP4 E03C6B 0 +OP4 E03C6C 0 +OP4 E03C6D 0 +OP4 E03C6E 0 +OP4 E03C6F 0 +OP4 E03C70 0 +OP4 E03C71 0 +OP4 E03C72 0 +OP4 E03C73 0 +OP4 E03C74 0 +OP4 E03C75 0 +OP4 E03C76 0 +OP4 E03C77 0 +OP4 E03C78 0 +OP4 E03C79 0 +OP4 E03C7A 0 +OP4 E03C7B 0 +OP4 E03C7C 0 +OP4 E03C7D 0 +OP4 E03C7E 0 +OP4 E03C7F 0 +OP4 E03C80 0 +OP4 E03C81 0 +OP4 E03C82 0 +OP4 E03C83 0 +OP4 E03C84 0 +OP4 E03C85 0 +OP4 E03C86 0 +OP4 E03C87 0 +OP4 E03C88 0 +OP4 E03C89 0 +OP4 E03C8A 0 +OP4 E03C8B 0 +OP4 E03C8C 0 +OP4 E03C8D 0 +OP4 E03C8E 0 +OP4 E03C8F 0 +OP4 E03C90 0 +OP4 E03C91 0 +OP4 E03C92 0 +OP4 E03C93 0 +OP4 E03C94 0 +OP4 E03C95 0 +OP4 E03C96 0 +OP4 E03C97 0 +OP4 E03C98 0 +OP4 E03C99 0 +OP4 E03C9A 0 +OP4 E03C9B 0 +OP4 E03C9C 0 +OP4 E03C9D 0 +OP4 E03C9E 0 +OP4 E03C9F 0 +OP4 E03CA0 0 +OP4 E03CA1 0 +OP4 E03CA2 0 +OP4 E03CA3 0 +OP4 E03CA4 0 +OP4 E03CA5 0 +OP4 E03CA6 0 +OP4 E03CA7 0 +OP4 E03CA8 0 +OP4 E03CA9 0 +OP4 E03CAA 0 +OP4 E03CAB 0 +OP4 E03CAC 0 +OP4 E03CAD 0 +OP4 E03CAE 0 +OP4 E03CAF 0 +OP4 E03CB0 0 +OP4 E03CB1 0 +OP4 E03CB2 0 +OP4 E03CB3 0 +OP4 E03CB4 0 +OP4 E03CB5 0 +OP4 E03CB6 0 +OP4 E03CB7 0 +OP4 E03CB8 0 +OP4 E03CB9 0 +OP4 E03CBA 0 +OP4 E03CBB 0 +OP4 E03CBC 0 +OP4 E03CBD 0 +OP4 E03CBE 0 +OP4 E03CBF 0 +OP4 E03CC0 0 +OP4 E03CC1 0 +OP4 E03CC2 0 +OP4 E03CC3 0 +OP4 E03CC4 0 +OP4 E03CC5 0 +OP4 E03CC6 0 +OP4 E03CC7 0 +OP4 E03CC8 0 +OP4 E03CC9 0 +OP4 E03CCA 0 +OP4 E03CCB 0 +OP4 E03CCC 0 +OP4 E03CCD 0 +OP4 E03CCE 0 +OP4 E03CCF 0 +OP4 E03CD0 0 +OP4 E03CD1 0 +OP4 E03CD2 0 +OP4 E03CD3 0 +OP4 E03CD4 0 +OP4 E03CD5 0 +OP4 E03CD6 0 +OP4 E03CD7 0 +OP4 E03CD8 0 +OP4 E03CD9 0 +OP4 E03CDA 0 +OP4 E03CDB 0 +OP4 E03CDC 0 +OP4 E03CDD 0 +OP4 E03CDE 0 +OP4 E03CDF 0 +OP4 E03CE0 0 +OP4 E03CE1 0 +OP4 E03CE2 0 +OP4 E03CE3 0 +OP4 E03CE4 0 +OP4 E03CE5 0 +OP4 E03CE6 0 +OP4 E03CE7 0 +OP4 E03CE8 0 +OP4 E03CE9 0 +OP4 E03CEA 0 +OP4 E03CEB 0 +OP4 E03CEC 0 +OP4 E03CED 0 +OP4 E03CEE 0 +OP4 E03CEF 0 +OP4 E03CF0 0 +OP4 E03CF1 0 +OP4 E03CF2 0 +OP4 E03CF3 0 +OP4 E03CF4 0 +OP4 E03CF5 0 +OP4 E03CF6 0 +OP4 E03CF7 0 +OP4 E03CF8 0 +OP4 E03CF9 0 +OP4 E03CFA 0 +OP4 E03CFB 0 +OP4 E03CFC 0 +OP4 E03CFD 0 +OP4 E03CFE 0 +OP4 E03CFF 0 +OP4 E03D00 0 +OP4 E03D01 0 +OP4 E03D02 0 +OP4 E03D03 0 +OP4 E03D04 0 +OP4 E03D05 0 +OP4 E03D06 0 +OP4 E03D07 0 +OP4 E03D08 0 +OP4 E03D09 0 +OP4 E03D0A 0 +OP4 E03D0B 0 +OP4 E03D0C 0 +OP4 E03D0D 0 +OP4 E03D0E 0 +OP4 E03D0F 0 +OP4 E03D10 0 +OP4 E03D11 0 +OP4 E03D12 0 +OP4 E03D13 0 +OP4 E03D14 0 +OP4 E03D15 0 +OP4 E03D16 0 +OP4 E03D17 0 +OP4 E03D18 0 +OP4 E03D19 0 +OP4 E03D1A 0 +OP4 E03D1B 0 +OP4 E03D1C 0 +OP4 E03D1D 0 +OP4 E03D1E 0 +OP4 E03D1F 0 +OP4 E03D20 0 +OP4 E03D21 0 +OP4 E03D22 0 +OP4 E03D23 0 +OP4 E03D24 0 +OP4 E03D25 0 +OP4 E03D26 0 +OP4 E03D27 0 +OP4 E03D28 0 +OP4 E03D29 0 +OP4 E03D2A 0 +OP4 E03D2B 0 +OP4 E03D2C 0 +OP4 E03D2D 0 +OP4 E03D2E 0 +OP4 E03D2F 0 +OP4 E03D30 0 +OP4 E03D31 0 +OP4 E03D32 0 +OP4 E03D33 0 +OP4 E03D34 0 +OP4 E03D35 0 +OP4 E03D36 0 +OP4 E03D37 0 +OP4 E03D38 0 +OP4 E03D39 0 +OP4 E03D3A 0 +OP4 E03D3B 0 +OP4 E03D3C 0 +OP4 E03D3D 0 +OP4 E03D3E 0 +OP4 E03D3F 0 +OP4 E03D40 0 +OP4 E03D41 0 +OP4 E03D42 0 +OP4 E03D43 0 +OP4 E03D44 0 +OP4 E03D45 0 +OP4 E03D46 0 +OP4 E03D47 0 +OP4 E03D48 0 +OP4 E03D49 0 +OP4 E03D4A 0 +OP4 E03D4B 0 +OP4 E03D4C 0 +OP4 E03D4D 0 +OP4 E03D4E 0 +OP4 E03D4F 0 +OP4 E03D50 0 +OP4 E03D51 0 +OP4 E03D52 0 +OP4 E03D53 0 +OP4 E03D54 0 +OP4 E03D55 0 +OP4 E03D56 0 +OP4 E03D57 0 +OP4 E03D58 0 +OP4 E03D59 0 +OP4 E03D5A 0 +OP4 E03D5B 0 +OP4 E03D5C 0 +OP4 E03D5D 0 +OP4 E03D5E 0 +OP4 E03D5F 0 +OP4 E03D60 0 +OP4 E03D61 0 +OP4 E03D62 0 +OP4 E03D63 0 +OP4 E03D64 0 +OP4 E03D65 0 +OP4 E03D66 0 +OP4 E03D67 0 +OP4 E03D68 0 +OP4 E03D69 0 +OP4 E03D6A 0 +OP4 E03D6B 0 +OP4 E03D6C 0 +OP4 E03D6D 0 +OP4 E03D6E 0 +OP4 E03D6F 0 +OP4 E03D70 0 +OP4 E03D71 0 +OP4 E03D72 0 +OP4 E03D73 0 +OP4 E03D74 0 +OP4 E03D75 0 +OP4 E03D76 0 +OP4 E03D77 0 +OP4 E03D78 0 +OP4 E03D79 0 +OP4 E03D7A 0 +OP4 E03D7B 0 +OP4 E03D7C 0 +OP4 E03D7D 0 +OP4 E03D7E 0 +OP4 E03D7F 0 +OP4 E03D80 0 +OP4 E03D81 0 +OP4 E03D82 0 +OP4 E03D83 0 +OP4 E03D84 0 +OP4 E03D85 0 +OP4 E03D86 0 +OP4 E03D87 0 +OP4 E03D88 0 +OP4 E03D89 0 +OP4 E03D8A 0 +OP4 E03D8B 0 +OP4 E03D8C 0 +OP4 E03D8D 0 +OP4 E03D8E 0 +OP4 E03D8F 0 +OP4 E03D90 0 +OP4 E03D91 0 +OP4 E03D92 0 +OP4 E03D93 0 +OP4 E03D94 0 +OP4 E03D95 0 +OP4 E03D96 0 +OP4 E03D97 0 +OP4 E03D98 0 +OP4 E03D99 0 +OP4 E03D9A 0 +OP4 E03D9B 0 +OP4 E03D9C 0 +OP4 E03D9D 0 +OP4 E03D9E 0 +OP4 E03D9F 0 +OP4 E03DA0 0 +OP4 E03DA1 0 +OP4 E03DA2 0 +OP4 E03DA3 0 +OP4 E03DA4 0 +OP4 E03DA5 0 +OP4 E03DA6 0 +OP4 E03DA7 0 +OP4 E03DA8 0 +OP4 E03DA9 0 +OP4 E03DAA 0 +OP4 E03DAB 0 +OP4 E03DAC 0 +OP4 E03DAD 0 +OP4 E03DAE 0 +OP4 E03DAF 0 +OP4 E03DB0 0 +OP4 E03DB1 0 +OP4 E03DB2 0 +OP4 E03DB3 0 +OP4 E03DB4 0 +OP4 E03DB5 0 +OP4 E03DB6 0 +OP4 E03DB7 0 +OP4 E03DB8 0 +OP4 E03DB9 0 +OP4 E03DBA 0 +OP4 E03DBB 0 +OP4 E03DBC 0 +OP4 E03DBD 0 +OP4 E03DBE 0 +OP4 E03DBF 0 +OP4 E03DC0 0 +OP4 E03DC1 0 +OP4 E03DC2 0 +OP4 E03DC3 0 +OP4 E03DC4 0 diff --git a/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum4_itrace_irisc3.cfg.ext b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum4_itrace_irisc3.cfg.ext new file mode 100644 index 000000000000..f709219258b2 --- /dev/null +++ b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum4_itrace_irisc3.cfg.ext @@ -0,0 +1,15814 @@ +OP1 Spectrum4 +OP4 ITRACE0 0 +OP4 ITRACE1 0 +OP4 ITRACE2 0 +OP4 ITRACE3 1 +OP4 ITRACE4 0 +OP4 ITRACE5 0 +OP4 ITRACE6 0 +OP4 ITRACE7 0 +OP4 ITRACE8 0 +OP4 ITRACE9 0 +OP4 Main_PhyUC 0 +OP4 TILE0_ITRACE0 0 +OP4 TILE0_ITRACE1 0 +OP4 TILE0_ITRACE2 0 +OP4 TILE0_ITRACE3 0 +OP4 TILE0_ITRACE4 0 +OP4 TILE0_PhyUC 0 +OP4 TILE1_ITRACE0 0 +OP4 TILE1_ITRACE1 0 +OP4 TILE1_ITRACE2 0 +OP4 TILE1_ITRACE3 0 +OP4 TILE1_ITRACE4 0 +OP4 TILE1_PhyUC 0 +OP4 TILE2_ITRACE0 0 +OP4 TILE2_ITRACE1 0 +OP4 TILE2_ITRACE2 0 +OP4 TILE2_ITRACE3 0 +OP4 TILE2_ITRACE4 0 +OP4 TILE2_PhyUC 0 +OP4 TILE3_ITRACE0 0 +OP4 TILE3_ITRACE1 0 +OP4 TILE3_ITRACE2 0 +OP4 TILE3_ITRACE3 0 +OP4 TILE3_ITRACE4 0 +OP4 TILE3_PhyUC 0 +OP4 TILE4_ITRACE0 0 +OP4 TILE4_ITRACE1 0 +OP4 TILE4_ITRACE2 0 +OP4 TILE4_ITRACE3 0 +OP4 TILE4_ITRACE4 0 +OP4 TILE4_PhyUC 0 +OP4 TILE5_ITRACE0 0 +OP4 TILE5_ITRACE1 0 +OP4 TILE5_ITRACE2 0 +OP4 TILE5_ITRACE3 0 +OP4 TILE5_ITRACE4 0 +OP4 TILE5_PhyUC 0 +OP4 TILE6_ITRACE0 0 +OP4 TILE6_ITRACE1 0 +OP4 TILE6_ITRACE2 0 +OP4 TILE6_ITRACE3 0 +OP4 TILE6_ITRACE4 0 +OP4 TILE6_PhyUC 0 +OP4 TILE7_ITRACE0 0 +OP4 TILE7_ITRACE1 0 +OP4 TILE7_ITRACE2 0 +OP4 TILE7_ITRACE3 0 +OP4 TILE7_ITRACE4 0 +OP4 TILE7_PhyUC 0 +OP4 E0003B 0 +OP4 E0003C 0 +OP4 E0003D 0 +OP4 E0003E 0 +OP4 E0003F 0 +OP4 E00040 0 +OP4 E00041 0 +OP4 E00042 0 +OP4 E00043 0 +OP4 E00044 0 +OP4 E00045 0 +OP4 E00046 0 +OP4 E00047 0 +OP4 E00048 0 +OP4 E00049 0 +OP4 E0004A 0 +OP4 E0004B 0 +OP4 E0004C 0 +OP4 E0004D 0 +OP4 E0004E 0 +OP4 E0004F 0 +OP4 E00050 0 +OP4 E00051 0 +OP4 E00052 0 +OP4 E00053 0 +OP4 E00054 0 +OP4 E00055 0 +OP4 E00056 0 +OP4 E00057 0 +OP4 E00058 0 +OP4 E00059 0 +OP4 E0005A 0 +OP4 E0005B 0 +OP4 E0005C 0 +OP4 E0005D 0 +OP4 E0005E 0 +OP4 E0005F 0 +OP4 E00060 0 +OP4 E00061 0 +OP4 E00062 0 +OP4 E00063 0 +OP4 E00064 0 +OP4 E00065 0 +OP4 E00066 0 +OP4 E00067 0 +OP4 E00068 0 +OP4 E00069 0 +OP4 E0006A 0 +OP4 E0006B 0 +OP4 E0006C 0 +OP4 E0006D 0 +OP4 E0006E 0 +OP4 E0006F 0 +OP4 E00070 0 +OP4 E00071 0 +OP4 E00072 0 +OP4 E00073 0 +OP4 E00074 0 +OP4 E00075 0 +OP4 E00076 0 +OP4 E00077 0 +OP4 E00078 0 +OP4 E00079 0 +OP4 E0007A 0 +OP4 E0007B 0 +OP4 E0007C 0 +OP4 E0007D 0 +OP4 E0007E 0 +OP4 E0007F 0 +OP4 E00080 0 +OP4 E00081 0 +OP4 E00082 0 +OP4 E00083 0 +OP4 E00084 0 +OP4 E00085 0 +OP4 E00086 0 +OP4 E00087 0 +OP4 E00088 0 +OP4 E00089 0 +OP4 E0008A 0 +OP4 E0008B 0 +OP4 E0008C 0 +OP4 E0008D 0 +OP4 E0008E 0 +OP4 E0008F 0 +OP4 E00090 0 +OP4 E00091 0 +OP4 E00092 0 +OP4 E00093 0 +OP4 E00094 0 +OP4 E00095 0 +OP4 E00096 0 +OP4 E00097 0 +OP4 E00098 0 +OP4 E00099 0 +OP4 E0009A 0 +OP4 E0009B 0 +OP4 E0009C 0 +OP4 E0009D 0 +OP4 E0009E 0 +OP4 E0009F 0 +OP4 E000A0 0 +OP4 E000A1 0 +OP4 E000A2 0 +OP4 E000A3 0 +OP4 E000A4 0 +OP4 E000A5 0 +OP4 E000A6 0 +OP4 E000A7 0 +OP4 E000A8 0 +OP4 E000A9 0 +OP4 E000AA 0 +OP4 E000AB 0 +OP4 E000AC 0 +OP4 E000AD 0 +OP4 E000AE 0 +OP4 E000AF 0 +OP4 E000B0 0 +OP4 E000B1 0 +OP4 E000B2 0 +OP4 E000B3 0 +OP4 E000B4 0 +OP4 E000B5 0 +OP4 E000B6 0 +OP4 E000B7 0 +OP4 E000B8 0 +OP4 E000B9 0 +OP4 E000BA 0 +OP4 E000BB 0 +OP4 E000BC 0 +OP4 E000BD 0 +OP4 E000BE 0 +OP4 E000BF 0 +OP4 E000C0 0 +OP4 E000C1 0 +OP4 E000C2 0 +OP4 E000C3 0 +OP4 E000C4 0 +OP4 E000C5 0 +OP4 E000C6 0 +OP4 E000C7 0 +OP4 E000C8 0 +OP4 E000C9 0 +OP4 E000CA 0 +OP4 E000CB 0 +OP4 E000CC 0 +OP4 E000CD 0 +OP4 E000CE 0 +OP4 E000CF 0 +OP4 E000D0 0 +OP4 E000D1 0 +OP4 E000D2 0 +OP4 E000D3 0 +OP4 E000D4 0 +OP4 E000D5 0 +OP4 E000D6 0 +OP4 E000D7 0 +OP4 E000D8 0 +OP4 E000D9 0 +OP4 E000DA 0 +OP4 E000DB 0 +OP4 E000DC 0 +OP4 E000DD 0 +OP4 E000DE 0 +OP4 E000DF 0 +OP4 E000E0 0 +OP4 E000E1 0 +OP4 E000E2 0 +OP4 E000E3 0 +OP4 E000E4 0 +OP4 E000E5 0 +OP4 E000E6 0 +OP4 E000E7 0 +OP4 E000E8 0 +OP4 E000E9 0 +OP4 E000EA 0 +OP4 E000EB 0 +OP4 E000EC 0 +OP4 E000ED 0 +OP4 E000EE 0 +OP4 E000EF 0 +OP4 E000F0 0 +OP4 E000F1 0 +OP4 E000F2 0 +OP4 E000F3 0 +OP4 E000F4 0 +OP4 E000F5 0 +OP4 E000F6 0 +OP4 E000F7 0 +OP4 E000F8 0 +OP4 E000F9 0 +OP4 E000FA 0 +OP4 E000FB 0 +OP4 E000FC 0 +OP4 E000FD 0 +OP4 E000FE 0 +OP4 E000FF 0 +OP4 E00100 0 +OP4 E00101 0 +OP4 E00102 0 +OP4 E00103 0 +OP4 E00104 0 +OP4 E00105 0 +OP4 E00106 0 +OP4 E00107 0 +OP4 E00108 0 +OP4 E00109 0 +OP4 E0010A 0 +OP4 E0010B 0 +OP4 E0010C 0 +OP4 E0010D 0 +OP4 E0010E 0 +OP4 E0010F 0 +OP4 E00110 0 +OP4 E00111 0 +OP4 E00112 0 +OP4 E00113 0 +OP4 E00114 0 +OP4 E00115 0 +OP4 E00116 0 +OP4 E00117 0 +OP4 E00118 0 +OP4 E00119 0 +OP4 E0011A 0 +OP4 E0011B 0 +OP4 E0011C 0 +OP4 E0011D 0 +OP4 E0011E 0 +OP4 E0011F 0 +OP4 E00120 0 +OP4 E00121 0 +OP4 E00122 0 +OP4 E00123 0 +OP4 E00124 0 +OP4 E00125 0 +OP4 E00126 0 +OP4 E00127 0 +OP4 E00128 0 +OP4 E00129 0 +OP4 E0012A 0 +OP4 E0012B 0 +OP4 E0012C 0 +OP4 E0012D 0 +OP4 E0012E 0 +OP4 E0012F 0 +OP4 E00130 0 +OP4 E00131 0 +OP4 E00132 0 +OP4 E00133 0 +OP4 E00134 0 +OP4 E00135 0 +OP4 E00136 0 +OP4 E00137 0 +OP4 E00138 0 +OP4 E00139 0 +OP4 E0013A 0 +OP4 E0013B 0 +OP4 E0013C 0 +OP4 E0013D 0 +OP4 E0013E 0 +OP4 E0013F 0 +OP4 E00140 0 +OP4 E00141 0 +OP4 E00142 0 +OP4 E00143 0 +OP4 E00144 0 +OP4 E00145 0 +OP4 E00146 0 +OP4 E00147 0 +OP4 E00148 0 +OP4 E00149 0 +OP4 E0014A 0 +OP4 E0014B 0 +OP4 E0014C 0 +OP4 E0014D 0 +OP4 E0014E 0 +OP4 E0014F 0 +OP4 E00150 0 +OP4 E00151 0 +OP4 E00152 0 +OP4 E00153 0 +OP4 E00154 0 +OP4 E00155 0 +OP4 E00156 0 +OP4 E00157 0 +OP4 E00158 0 +OP4 E00159 0 +OP4 E0015A 0 +OP4 E0015B 0 +OP4 E0015C 0 +OP4 E0015D 0 +OP4 E0015E 0 +OP4 E0015F 0 +OP4 E00160 0 +OP4 E00161 0 +OP4 E00162 0 +OP4 E00163 0 +OP4 E00164 0 +OP4 E00165 0 +OP4 E00166 0 +OP4 E00167 0 +OP4 E00168 0 +OP4 E00169 0 +OP4 E0016A 0 +OP4 E0016B 0 +OP4 E0016C 0 +OP4 E0016D 0 +OP4 E0016E 0 +OP4 E0016F 0 +OP4 E00170 0 +OP4 E00171 0 +OP4 E00172 0 +OP4 E00173 0 +OP4 E00174 0 +OP4 E00175 0 +OP4 E00176 0 +OP4 E00177 0 +OP4 E00178 0 +OP4 E00179 0 +OP4 E0017A 0 +OP4 E0017B 0 +OP4 E0017C 0 +OP4 E0017D 0 +OP4 E0017E 0 +OP4 E0017F 0 +OP4 E00180 0 +OP4 E00181 0 +OP4 E00182 0 +OP4 E00183 0 +OP4 E00184 0 +OP4 E00185 0 +OP4 E00186 0 +OP4 E00187 0 +OP4 E00188 0 +OP4 E00189 0 +OP4 E0018A 0 +OP4 E0018B 0 +OP4 E0018C 0 +OP4 E0018D 0 +OP4 E0018E 0 +OP4 E0018F 0 +OP4 E00190 0 +OP4 E00191 0 +OP4 E00192 0 +OP4 E00193 0 +OP4 E00194 0 +OP4 E00195 0 +OP4 E00196 0 +OP4 E00197 0 +OP4 E00198 0 +OP4 E00199 0 +OP4 E0019A 0 +OP4 E0019B 0 +OP4 E0019C 0 +OP4 E0019D 0 +OP4 E0019E 0 +OP4 E0019F 0 +OP4 E001A0 0 +OP4 E001A1 0 +OP4 E001A2 0 +OP4 E001A3 0 +OP4 E001A4 0 +OP4 E001A5 0 +OP4 E001A6 0 +OP4 E001A7 0 +OP4 E001A8 0 +OP4 E001A9 0 +OP4 E001AA 0 +OP4 E001AB 0 +OP4 E001AC 0 +OP4 E001AD 0 +OP4 E001AE 0 +OP4 E001AF 0 +OP4 E001B0 0 +OP4 E001B1 0 +OP4 E001B2 0 +OP4 E001B3 0 +OP4 E001B4 0 +OP4 E001B5 0 +OP4 E001B6 0 +OP4 E001B7 0 +OP4 E001B8 0 +OP4 E001B9 0 +OP4 E001BA 0 +OP4 E001BB 0 +OP4 E001BC 0 +OP4 E001BD 0 +OP4 E001BE 0 +OP4 E001BF 0 +OP4 E001C0 0 +OP4 E001C1 0 +OP4 E001C2 0 +OP4 E001C3 0 +OP4 E001C4 0 +OP4 E001C5 0 +OP4 E001C6 0 +OP4 E001C7 0 +OP4 E001C8 0 +OP4 E001C9 0 +OP4 E001CA 0 +OP4 E001CB 0 +OP4 E001CC 0 +OP4 E001CD 0 +OP4 E001CE 0 +OP4 E001CF 0 +OP4 E001D0 0 +OP4 E001D1 0 +OP4 E001D2 0 +OP4 E001D3 0 +OP4 E001D4 0 +OP4 E001D5 0 +OP4 E001D6 0 +OP4 E001D7 0 +OP4 E001D8 0 +OP4 E001D9 0 +OP4 E001DA 0 +OP4 E001DB 0 +OP4 E001DC 0 +OP4 E001DD 0 +OP4 E001DE 0 +OP4 E001DF 0 +OP4 E001E0 0 +OP4 E001E1 0 +OP4 E001E2 0 +OP4 E001E3 0 +OP4 E001E4 0 +OP4 E001E5 0 +OP4 E001E6 0 +OP4 E001E7 0 +OP4 E001E8 0 +OP4 E001E9 0 +OP4 E001EA 0 +OP4 E001EB 0 +OP4 E001EC 0 +OP4 E001ED 0 +OP4 E001EE 0 +OP4 E001EF 0 +OP4 E001F0 0 +OP4 E001F1 0 +OP4 E001F2 0 +OP4 E001F3 0 +OP4 E001F4 0 +OP4 E001F5 0 +OP4 E001F6 0 +OP4 E001F7 0 +OP4 E001F8 0 +OP4 E001F9 0 +OP4 E001FA 0 +OP4 E001FB 0 +OP4 E001FC 0 +OP4 E001FD 0 +OP4 E001FE 0 +OP4 E001FF 0 +OP4 E00200 0 +OP4 E00201 0 +OP4 E00202 0 +OP4 E00203 0 +OP4 E00204 0 +OP4 E00205 0 +OP4 E00206 0 +OP4 E00207 0 +OP4 E00208 0 +OP4 E00209 0 +OP4 E0020A 0 +OP4 E0020B 0 +OP4 E0020C 0 +OP4 E0020D 0 +OP4 E0020E 0 +OP4 E0020F 0 +OP4 E00210 0 +OP4 E00211 0 +OP4 E00212 0 +OP4 E00213 0 +OP4 E00214 0 +OP4 E00215 0 +OP4 E00216 0 +OP4 E00217 0 +OP4 E00218 0 +OP4 E00219 0 +OP4 E0021A 0 +OP4 E0021B 0 +OP4 E0021C 0 +OP4 E0021D 0 +OP4 E0021E 0 +OP4 E0021F 0 +OP4 E00220 0 +OP4 E00221 0 +OP4 E00222 0 +OP4 E00223 0 +OP4 E00224 0 +OP4 E00225 0 +OP4 E00226 0 +OP4 E00227 0 +OP4 E00228 0 +OP4 E00229 0 +OP4 E0022A 0 +OP4 E0022B 0 +OP4 E0022C 0 +OP4 E0022D 0 +OP4 E0022E 0 +OP4 E0022F 0 +OP4 E00230 0 +OP4 E00231 0 +OP4 E00232 0 +OP4 E00233 0 +OP4 E00234 0 +OP4 E00235 0 +OP4 E00236 0 +OP4 E00237 0 +OP4 E00238 0 +OP4 E00239 0 +OP4 E0023A 0 +OP4 E0023B 0 +OP4 E0023C 0 +OP4 E0023D 0 +OP4 E0023E 0 +OP4 E0023F 0 +OP4 E00240 0 +OP4 E00241 0 +OP4 E00242 0 +OP4 E00243 0 +OP4 E00244 0 +OP4 E00245 0 +OP4 E00246 0 +OP4 E00247 0 +OP4 E00248 0 +OP4 E00249 0 +OP4 E0024A 0 +OP4 E0024B 0 +OP4 E0024C 0 +OP4 E0024D 0 +OP4 E0024E 0 +OP4 E0024F 0 +OP4 E00250 0 +OP4 E00251 0 +OP4 E00252 0 +OP4 E00253 0 +OP4 E00254 0 +OP4 E00255 0 +OP4 E00256 0 +OP4 E00257 0 +OP4 E00258 0 +OP4 E00259 0 +OP4 E0025A 0 +OP4 E0025B 0 +OP4 E0025C 0 +OP4 E0025D 0 +OP4 E0025E 0 +OP4 E0025F 0 +OP4 E00260 0 +OP4 E00261 0 +OP4 E00262 0 +OP4 E00263 0 +OP4 E00264 0 +OP4 E00265 0 +OP4 E00266 0 +OP4 E00267 0 +OP4 E00268 0 +OP4 E00269 0 +OP4 E0026A 0 +OP4 E0026B 0 +OP4 E0026C 0 +OP4 E0026D 0 +OP4 E0026E 0 +OP4 E0026F 0 +OP4 E00270 0 +OP4 E00271 0 +OP4 E00272 0 +OP4 E00273 0 +OP4 E00274 0 +OP4 E00275 0 +OP4 E00276 0 +OP4 E00277 0 +OP4 E00278 0 +OP4 E00279 0 +OP4 E0027A 0 +OP4 E0027B 0 +OP4 E0027C 0 +OP4 E0027D 0 +OP4 E0027E 0 +OP4 E0027F 0 +OP4 E00280 0 +OP4 E00281 0 +OP4 E00282 0 +OP4 E00283 0 +OP4 E00284 0 +OP4 E00285 0 +OP4 E00286 0 +OP4 E00287 0 +OP4 E00288 0 +OP4 E00289 0 +OP4 E0028A 0 +OP4 E0028B 0 +OP4 E0028C 0 +OP4 E0028D 0 +OP4 E0028E 0 +OP4 E0028F 0 +OP4 E00290 0 +OP4 E00291 0 +OP4 E00292 0 +OP4 E00293 0 +OP4 E00294 0 +OP4 E00295 0 +OP4 E00296 0 +OP4 E00297 0 +OP4 E00298 0 +OP4 E00299 0 +OP4 E0029A 0 +OP4 E0029B 0 +OP4 E0029C 0 +OP4 E0029D 0 +OP4 E0029E 0 +OP4 E0029F 0 +OP4 E002A0 0 +OP4 E002A1 0 +OP4 E002A2 0 +OP4 E002A3 0 +OP4 E002A4 0 +OP4 E002A5 0 +OP4 E002A6 0 +OP4 E002A7 0 +OP4 E002A8 0 +OP4 E002A9 0 +OP4 E002AA 0 +OP4 E002AB 0 +OP4 E002AC 0 +OP4 E002AD 0 +OP4 E002AE 0 +OP4 E002AF 0 +OP4 E002B0 0 +OP4 E002B1 0 +OP4 E002B2 0 +OP4 E002B3 0 +OP4 E002B4 0 +OP4 E002B5 0 +OP4 E002B6 0 +OP4 E002B7 0 +OP4 E002B8 0 +OP4 E002B9 0 +OP4 E002BA 0 +OP4 E002BB 0 +OP4 E002BC 0 +OP4 E002BD 0 +OP4 E002BE 0 +OP4 E002BF 0 +OP4 E002C0 0 +OP4 E002C1 0 +OP4 E002C2 0 +OP4 E002C3 0 +OP4 E002C4 0 +OP4 E002C5 0 +OP4 E002C6 0 +OP4 E002C7 0 +OP4 E002C8 0 +OP4 E002C9 0 +OP4 E002CA 0 +OP4 E002CB 0 +OP4 E002CC 0 +OP4 E002CD 0 +OP4 E002CE 0 +OP4 E002CF 0 +OP4 E002D0 0 +OP4 E002D1 0 +OP4 E002D2 0 +OP4 E002D3 0 +OP4 E002D4 0 +OP4 E002D5 0 +OP4 E002D6 0 +OP4 E002D7 0 +OP4 E002D8 0 +OP4 E002D9 0 +OP4 E002DA 0 +OP4 E002DB 0 +OP4 E002DC 0 +OP4 E002DD 0 +OP4 E002DE 0 +OP4 E002DF 0 +OP4 E002E0 0 +OP4 E002E1 0 +OP4 E002E2 0 +OP4 E002E3 0 +OP4 E002E4 0 +OP4 E002E5 0 +OP4 E002E6 0 +OP4 E002E7 0 +OP4 E002E8 0 +OP4 E002E9 0 +OP4 E002EA 0 +OP4 E002EB 0 +OP4 E002EC 0 +OP4 E002ED 0 +OP4 E002EE 0 +OP4 E002EF 0 +OP4 E002F0 0 +OP4 E002F1 0 +OP4 E002F2 0 +OP4 E002F3 0 +OP4 E002F4 0 +OP4 E002F5 0 +OP4 E002F6 0 +OP4 E002F7 0 +OP4 E002F8 0 +OP4 E002F9 0 +OP4 E002FA 0 +OP4 E002FB 0 +OP4 E002FC 0 +OP4 E002FD 0 +OP4 E002FE 0 +OP4 E002FF 0 +OP4 E00300 0 +OP4 E00301 0 +OP4 E00302 0 +OP4 E00303 0 +OP4 E00304 0 +OP4 E00305 0 +OP4 E00306 0 +OP4 E00307 0 +OP4 E00308 0 +OP4 E00309 0 +OP4 E0030A 0 +OP4 E0030B 0 +OP4 E0030C 0 +OP4 E0030D 0 +OP4 E0030E 0 +OP4 E0030F 0 +OP4 E00310 0 +OP4 E00311 0 +OP4 E00312 0 +OP4 E00313 0 +OP4 E00314 0 +OP4 E00315 0 +OP4 E00316 0 +OP4 E00317 0 +OP4 E00318 0 +OP4 E00319 0 +OP4 E0031A 0 +OP4 E0031B 0 +OP4 E0031C 0 +OP4 E0031D 0 +OP4 E0031E 0 +OP4 E0031F 0 +OP4 E00320 0 +OP4 E00321 0 +OP4 E00322 0 +OP4 E00323 0 +OP4 E00324 0 +OP4 E00325 0 +OP4 E00326 0 +OP4 E00327 0 +OP4 E00328 0 +OP4 E00329 0 +OP4 E0032A 0 +OP4 E0032B 0 +OP4 E0032C 0 +OP4 E0032D 0 +OP4 E0032E 0 +OP4 E0032F 0 +OP4 E00330 0 +OP4 E00331 0 +OP4 E00332 0 +OP4 E00333 0 +OP4 E00334 0 +OP4 E00335 0 +OP4 E00336 0 +OP4 E00337 0 +OP4 E00338 0 +OP4 E00339 0 +OP4 E0033A 0 +OP4 E0033B 0 +OP4 E0033C 0 +OP4 E0033D 0 +OP4 E0033E 0 +OP4 E0033F 0 +OP4 E00340 0 +OP4 E00341 0 +OP4 E00342 0 +OP4 E00343 0 +OP4 E00344 0 +OP4 E00345 0 +OP4 E00346 0 +OP4 E00347 0 +OP4 E00348 0 +OP4 E00349 0 +OP4 E0034A 0 +OP4 E0034B 0 +OP4 E0034C 0 +OP4 E0034D 0 +OP4 E0034E 0 +OP4 E0034F 0 +OP4 E00350 0 +OP4 E00351 0 +OP4 E00352 0 +OP4 E00353 0 +OP4 E00354 0 +OP4 E00355 0 +OP4 E00356 0 +OP4 E00357 0 +OP4 E00358 0 +OP4 E00359 0 +OP4 E0035A 0 +OP4 E0035B 0 +OP4 E0035C 0 +OP4 E0035D 0 +OP4 E0035E 0 +OP4 E0035F 0 +OP4 E00360 0 +OP4 E00361 0 +OP4 E00362 0 +OP4 E00363 0 +OP4 E00364 0 +OP4 E00365 0 +OP4 E00366 0 +OP4 E00367 0 +OP4 E00368 0 +OP4 E00369 0 +OP4 E0036A 0 +OP4 E0036B 0 +OP4 E0036C 0 +OP4 E0036D 0 +OP4 E0036E 0 +OP4 E0036F 0 +OP4 E00370 0 +OP4 E00371 0 +OP4 E00372 0 +OP4 E00373 0 +OP4 E00374 0 +OP4 E00375 0 +OP4 E00376 0 +OP4 E00377 0 +OP4 E00378 0 +OP4 E00379 0 +OP4 E0037A 0 +OP4 E0037B 0 +OP4 E0037C 0 +OP4 E0037D 0 +OP4 E0037E 0 +OP4 E0037F 0 +OP4 E00380 0 +OP4 E00381 0 +OP4 E00382 0 +OP4 E00383 0 +OP4 E00384 0 +OP4 E00385 0 +OP4 E00386 0 +OP4 E00387 0 +OP4 E00388 0 +OP4 E00389 0 +OP4 E0038A 0 +OP4 E0038B 0 +OP4 E0038C 0 +OP4 E0038D 0 +OP4 E0038E 0 +OP4 E0038F 0 +OP4 E00390 0 +OP4 E00391 0 +OP4 E00392 0 +OP4 E00393 0 +OP4 E00394 0 +OP4 E00395 0 +OP4 E00396 0 +OP4 E00397 0 +OP4 E00398 0 +OP4 E00399 0 +OP4 E0039A 0 +OP4 E0039B 0 +OP4 E0039C 0 +OP4 E0039D 0 +OP4 E0039E 0 +OP4 E0039F 0 +OP4 E003A0 0 +OP4 E003A1 0 +OP4 E003A2 0 +OP4 E003A3 0 +OP4 E003A4 0 +OP4 E003A5 0 +OP4 E003A6 0 +OP4 E003A7 0 +OP4 E003A8 0 +OP4 E003A9 0 +OP4 E003AA 0 +OP4 E003AB 0 +OP4 E003AC 0 +OP4 E003AD 0 +OP4 E003AE 0 +OP4 E003AF 0 +OP4 E003B0 0 +OP4 E003B1 0 +OP4 E003B2 0 +OP4 E003B3 0 +OP4 E003B4 0 +OP4 E003B5 0 +OP4 E003B6 0 +OP4 E003B7 0 +OP4 E003B8 0 +OP4 E003B9 0 +OP4 E003BA 0 +OP4 E003BB 0 +OP4 E003BC 0 +OP4 E003BD 0 +OP4 E003BE 0 +OP4 E003BF 0 +OP4 E003C0 0 +OP4 E003C1 0 +OP4 E003C2 0 +OP4 E003C3 0 +OP4 E003C4 0 +OP4 E003C5 0 +OP4 E003C6 0 +OP4 E003C7 0 +OP4 E003C8 0 +OP4 E003C9 0 +OP4 E003CA 0 +OP4 E003CB 0 +OP4 E003CC 0 +OP4 E003CD 0 +OP4 E003CE 0 +OP4 E003CF 0 +OP4 E003D0 0 +OP4 E003D1 0 +OP4 E003D2 0 +OP4 E003D3 0 +OP4 E003D4 0 +OP4 E003D5 0 +OP4 E003D6 0 +OP4 E003D7 0 +OP4 E003D8 0 +OP4 E003D9 0 +OP4 E003DA 0 +OP4 E003DB 0 +OP4 E003DC 0 +OP4 E003DD 0 +OP4 E003DE 0 +OP4 E003DF 0 +OP4 E003E0 0 +OP4 E003E1 0 +OP4 E003E2 0 +OP4 E003E3 0 +OP4 E003E4 0 +OP4 E003E5 0 +OP4 E003E6 0 +OP4 E003E7 0 +OP4 E003E8 0 +OP4 E003E9 0 +OP4 E003EA 0 +OP4 E003EB 0 +OP4 E003EC 0 +OP4 E003ED 0 +OP4 E003EE 0 +OP4 E003EF 0 +OP4 E003F0 0 +OP4 E003F1 0 +OP4 E003F2 0 +OP4 E003F3 0 +OP4 E003F4 0 +OP4 E003F5 0 +OP4 E003F6 0 +OP4 E003F7 0 +OP4 E003F8 0 +OP4 E003F9 0 +OP4 E003FA 0 +OP4 E003FB 0 +OP4 E003FC 0 +OP4 E003FD 0 +OP4 E003FE 0 +OP4 E003FF 0 +OP4 E00400 0 +OP4 E00401 0 +OP4 E00402 0 +OP4 E00403 0 +OP4 E00404 0 +OP4 E00405 0 +OP4 E00406 0 +OP4 E00407 0 +OP4 E00408 0 +OP4 E00409 0 +OP4 E0040A 0 +OP4 E0040B 0 +OP4 E0040C 0 +OP4 E0040D 0 +OP4 E0040E 0 +OP4 E0040F 0 +OP4 E00410 0 +OP4 E00411 0 +OP4 E00412 0 +OP4 E00413 0 +OP4 E00414 0 +OP4 E00415 0 +OP4 E00416 0 +OP4 E00417 0 +OP4 E00418 0 +OP4 E00419 0 +OP4 E0041A 0 +OP4 E0041B 0 +OP4 E0041C 0 +OP4 E0041D 0 +OP4 E0041E 0 +OP4 E0041F 0 +OP4 E00420 0 +OP4 E00421 0 +OP4 E00422 0 +OP4 E00423 0 +OP4 E00424 0 +OP4 E00425 0 +OP4 E00426 0 +OP4 E00427 0 +OP4 E00428 0 +OP4 E00429 0 +OP4 E0042A 0 +OP4 E0042B 0 +OP4 E0042C 0 +OP4 E0042D 0 +OP4 E0042E 0 +OP4 E0042F 0 +OP4 E00430 0 +OP4 E00431 0 +OP4 E00432 0 +OP4 E00433 0 +OP4 E00434 0 +OP4 E00435 0 +OP4 E00436 0 +OP4 E00437 0 +OP4 E00438 0 +OP4 E00439 0 +OP4 E0043A 0 +OP4 E0043B 0 +OP4 E0043C 0 +OP4 E0043D 0 +OP4 E0043E 0 +OP4 E0043F 0 +OP4 E00440 0 +OP4 E00441 0 +OP4 E00442 0 +OP4 E00443 0 +OP4 E00444 0 +OP4 E00445 0 +OP4 E00446 0 +OP4 E00447 0 +OP4 E00448 0 +OP4 E00449 0 +OP4 E0044A 0 +OP4 E0044B 0 +OP4 E0044C 0 +OP4 E0044D 0 +OP4 E0044E 0 +OP4 E0044F 0 +OP4 E00450 0 +OP4 E00451 0 +OP4 E00452 0 +OP4 E00453 0 +OP4 E00454 0 +OP4 E00455 0 +OP4 E00456 0 +OP4 E00457 0 +OP4 E00458 0 +OP4 E00459 0 +OP4 E0045A 0 +OP4 E0045B 0 +OP4 E0045C 0 +OP4 E0045D 0 +OP4 E0045E 0 +OP4 E0045F 0 +OP4 E00460 0 +OP4 E00461 0 +OP4 E00462 0 +OP4 E00463 0 +OP4 E00464 0 +OP4 E00465 0 +OP4 E00466 0 +OP4 E00467 0 +OP4 E00468 0 +OP4 E00469 0 +OP4 E0046A 0 +OP4 E0046B 0 +OP4 E0046C 0 +OP4 E0046D 0 +OP4 E0046E 0 +OP4 E0046F 0 +OP4 E00470 0 +OP4 E00471 0 +OP4 E00472 0 +OP4 E00473 0 +OP4 E00474 0 +OP4 E00475 0 +OP4 E00476 0 +OP4 E00477 0 +OP4 E00478 0 +OP4 E00479 0 +OP4 E0047A 0 +OP4 E0047B 0 +OP4 E0047C 0 +OP4 E0047D 0 +OP4 E0047E 0 +OP4 E0047F 0 +OP4 E00480 0 +OP4 E00481 0 +OP4 E00482 0 +OP4 E00483 0 +OP4 E00484 0 +OP4 E00485 0 +OP4 E00486 0 +OP4 E00487 0 +OP4 E00488 0 +OP4 E00489 0 +OP4 E0048A 0 +OP4 E0048B 0 +OP4 E0048C 0 +OP4 E0048D 0 +OP4 E0048E 0 +OP4 E0048F 0 +OP4 E00490 0 +OP4 E00491 0 +OP4 E00492 0 +OP4 E00493 0 +OP4 E00494 0 +OP4 E00495 0 +OP4 E00496 0 +OP4 E00497 0 +OP4 E00498 0 +OP4 E00499 0 +OP4 E0049A 0 +OP4 E0049B 0 +OP4 E0049C 0 +OP4 E0049D 0 +OP4 E0049E 0 +OP4 E0049F 0 +OP4 E004A0 0 +OP4 E004A1 0 +OP4 E004A2 0 +OP4 E004A3 0 +OP4 E004A4 0 +OP4 E004A5 0 +OP4 E004A6 0 +OP4 E004A7 0 +OP4 E004A8 0 +OP4 E004A9 0 +OP4 E004AA 0 +OP4 E004AB 0 +OP4 E004AC 0 +OP4 E004AD 0 +OP4 E004AE 0 +OP4 E004AF 0 +OP4 E004B0 0 +OP4 E004B1 0 +OP4 E004B2 0 +OP4 E004B3 0 +OP4 E004B4 0 +OP4 E004B5 0 +OP4 E004B6 0 +OP4 E004B7 0 +OP4 E004B8 0 +OP4 E004B9 0 +OP4 E004BA 0 +OP4 E004BB 0 +OP4 E004BC 0 +OP4 E004BD 0 +OP4 E004BE 0 +OP4 E004BF 0 +OP4 E004C0 0 +OP4 E004C1 0 +OP4 E004C2 0 +OP4 E004C3 0 +OP4 E004C4 0 +OP4 E004C5 0 +OP4 E004C6 0 +OP4 E004C7 0 +OP4 E004C8 0 +OP4 E004C9 0 +OP4 E004CA 0 +OP4 E004CB 0 +OP4 E004CC 0 +OP4 E004CD 0 +OP4 E004CE 0 +OP4 E004CF 0 +OP4 E004D0 0 +OP4 E004D1 0 +OP4 E004D2 0 +OP4 E004D3 0 +OP4 E004D4 0 +OP4 E004D5 0 +OP4 E004D6 0 +OP4 E004D7 0 +OP4 E004D8 0 +OP4 E004D9 0 +OP4 E004DA 0 +OP4 E004DB 0 +OP4 E004DC 0 +OP4 E004DD 0 +OP4 E004DE 0 +OP4 E004DF 0 +OP4 E004E0 0 +OP4 E004E1 0 +OP4 E004E2 0 +OP4 E004E3 0 +OP4 E004E4 0 +OP4 E004E5 0 +OP4 E004E6 0 +OP4 E004E7 0 +OP4 E004E8 0 +OP4 E004E9 0 +OP4 E004EA 0 +OP4 E004EB 0 +OP4 E004EC 0 +OP4 E004ED 0 +OP4 E004EE 0 +OP4 E004EF 0 +OP4 E004F0 0 +OP4 E004F1 0 +OP4 E004F2 0 +OP4 E004F3 0 +OP4 E004F4 0 +OP4 E004F5 0 +OP4 E004F6 0 +OP4 E004F7 0 +OP4 E004F8 0 +OP4 E004F9 0 +OP4 E004FA 0 +OP4 E004FB 0 +OP4 E004FC 0 +OP4 E004FD 0 +OP4 E004FE 0 +OP4 E004FF 0 +OP4 E00500 0 +OP4 E00501 0 +OP4 E00502 0 +OP4 E00503 0 +OP4 E00504 0 +OP4 E00505 0 +OP4 E00506 0 +OP4 E00507 0 +OP4 E00508 0 +OP4 E00509 0 +OP4 E0050A 0 +OP4 E0050B 0 +OP4 E0050C 0 +OP4 E0050D 0 +OP4 E0050E 0 +OP4 E0050F 0 +OP4 E00510 0 +OP4 E00511 0 +OP4 E00512 0 +OP4 E00513 0 +OP4 E00514 0 +OP4 E00515 0 +OP4 E00516 0 +OP4 E00517 0 +OP4 E00518 0 +OP4 E00519 0 +OP4 E0051A 0 +OP4 E0051B 0 +OP4 E0051C 0 +OP4 E0051D 0 +OP4 E0051E 0 +OP4 E0051F 0 +OP4 E00520 0 +OP4 E00521 0 +OP4 E00522 0 +OP4 E00523 0 +OP4 E00524 0 +OP4 E00525 0 +OP4 E00526 0 +OP4 E00527 0 +OP4 E00528 0 +OP4 E00529 0 +OP4 E0052A 0 +OP4 E0052B 0 +OP4 E0052C 0 +OP4 E0052D 0 +OP4 E0052E 0 +OP4 E0052F 0 +OP4 E00530 0 +OP4 E00531 0 +OP4 E00532 0 +OP4 E00533 0 +OP4 E00534 0 +OP4 E00535 0 +OP4 E00536 0 +OP4 E00537 0 +OP4 E00538 0 +OP4 E00539 0 +OP4 E0053A 0 +OP4 E0053B 0 +OP4 E0053C 0 +OP4 E0053D 0 +OP4 E0053E 0 +OP4 E0053F 0 +OP4 E00540 0 +OP4 E00541 0 +OP4 E00542 0 +OP4 E00543 0 +OP4 E00544 0 +OP4 E00545 0 +OP4 E00546 0 +OP4 E00547 0 +OP4 E00548 0 +OP4 E00549 0 +OP4 E0054A 0 +OP4 E0054B 0 +OP4 E0054C 0 +OP4 E0054D 0 +OP4 E0054E 0 +OP4 E0054F 0 +OP4 E00550 0 +OP4 E00551 0 +OP4 E00552 0 +OP4 E00553 0 +OP4 E00554 0 +OP4 E00555 0 +OP4 E00556 0 +OP4 E00557 0 +OP4 E00558 0 +OP4 E00559 0 +OP4 E0055A 0 +OP4 E0055B 0 +OP4 E0055C 0 +OP4 E0055D 0 +OP4 E0055E 0 +OP4 E0055F 0 +OP4 E00560 0 +OP4 E00561 0 +OP4 E00562 0 +OP4 E00563 0 +OP4 E00564 0 +OP4 E00565 0 +OP4 E00566 0 +OP4 E00567 0 +OP4 E00568 0 +OP4 E00569 0 +OP4 E0056A 0 +OP4 E0056B 0 +OP4 E0056C 0 +OP4 E0056D 0 +OP4 E0056E 0 +OP4 E0056F 0 +OP4 E00570 0 +OP4 E00571 0 +OP4 E00572 0 +OP4 E00573 0 +OP4 E00574 0 +OP4 E00575 0 +OP4 E00576 0 +OP4 E00577 0 +OP4 E00578 0 +OP4 E00579 0 +OP4 E0057A 0 +OP4 E0057B 0 +OP4 E0057C 0 +OP4 E0057D 0 +OP4 E0057E 0 +OP4 E0057F 0 +OP4 E00580 0 +OP4 E00581 0 +OP4 E00582 0 +OP4 E00583 0 +OP4 E00584 0 +OP4 E00585 0 +OP4 E00586 0 +OP4 E00587 0 +OP4 E00588 0 +OP4 E00589 0 +OP4 E0058A 0 +OP4 E0058B 0 +OP4 E0058C 0 +OP4 E0058D 0 +OP4 E0058E 0 +OP4 E0058F 0 +OP4 E00590 0 +OP4 E00591 0 +OP4 E00592 0 +OP4 E00593 0 +OP4 E00594 0 +OP4 E00595 0 +OP4 E00596 0 +OP4 E00597 0 +OP4 E00598 0 +OP4 E00599 0 +OP4 E0059A 0 +OP4 E0059B 0 +OP4 E0059C 0 +OP4 E0059D 0 +OP4 E0059E 0 +OP4 E0059F 0 +OP4 E005A0 0 +OP4 E005A1 0 +OP4 E005A2 0 +OP4 E005A3 0 +OP4 E005A4 0 +OP4 E005A5 0 +OP4 E005A6 0 +OP4 E005A7 0 +OP4 E005A8 0 +OP4 E005A9 0 +OP4 E005AA 0 +OP4 E005AB 0 +OP4 E005AC 0 +OP4 E005AD 0 +OP4 E005AE 0 +OP4 E005AF 0 +OP4 E005B0 0 +OP4 E005B1 0 +OP4 E005B2 0 +OP4 E005B3 0 +OP4 E005B4 0 +OP4 E005B5 0 +OP4 E005B6 0 +OP4 E005B7 0 +OP4 E005B8 0 +OP4 E005B9 0 +OP4 E005BA 0 +OP4 E005BB 0 +OP4 E005BC 0 +OP4 E005BD 0 +OP4 E005BE 0 +OP4 E005BF 0 +OP4 E005C0 0 +OP4 E005C1 0 +OP4 E005C2 0 +OP4 E005C3 0 +OP4 E005C4 0 +OP4 E005C5 0 +OP4 E005C6 0 +OP4 E005C7 0 +OP4 E005C8 0 +OP4 E005C9 0 +OP4 E005CA 0 +OP4 E005CB 0 +OP4 E005CC 0 +OP4 E005CD 0 +OP4 E005CE 0 +OP4 E005CF 0 +OP4 E005D0 0 +OP4 E005D1 0 +OP4 E005D2 0 +OP4 E005D3 0 +OP4 E005D4 0 +OP4 E005D5 0 +OP4 E005D6 0 +OP4 E005D7 0 +OP4 E005D8 0 +OP4 E005D9 0 +OP4 E005DA 0 +OP4 E005DB 0 +OP4 E005DC 0 +OP4 E005DD 0 +OP4 E005DE 0 +OP4 E005DF 0 +OP4 E005E0 0 +OP4 E005E1 0 +OP4 E005E2 0 +OP4 E005E3 0 +OP4 E005E4 0 +OP4 E005E5 0 +OP4 E005E6 0 +OP4 E005E7 0 +OP4 E005E8 0 +OP4 E005E9 0 +OP4 E005EA 0 +OP4 E005EB 0 +OP4 E005EC 0 +OP4 E005ED 0 +OP4 E005EE 0 +OP4 E005EF 0 +OP4 E005F0 0 +OP4 E005F1 0 +OP4 E005F2 0 +OP4 E005F3 0 +OP4 E005F4 0 +OP4 E005F5 0 +OP4 E005F6 0 +OP4 E005F7 0 +OP4 E005F8 0 +OP4 E005F9 0 +OP4 E005FA 0 +OP4 E005FB 0 +OP4 E005FC 0 +OP4 E005FD 0 +OP4 E005FE 0 +OP4 E005FF 0 +OP4 E00600 0 +OP4 E00601 0 +OP4 E00602 0 +OP4 E00603 0 +OP4 E00604 0 +OP4 E00605 0 +OP4 E00606 0 +OP4 E00607 0 +OP4 E00608 0 +OP4 E00609 0 +OP4 E0060A 0 +OP4 E0060B 0 +OP4 E0060C 0 +OP4 E0060D 0 +OP4 E0060E 0 +OP4 E0060F 0 +OP4 E00610 0 +OP4 E00611 0 +OP4 E00612 0 +OP4 E00613 0 +OP4 E00614 0 +OP4 E00615 0 +OP4 E00616 0 +OP4 E00617 0 +OP4 E00618 0 +OP4 E00619 0 +OP4 E0061A 0 +OP4 E0061B 0 +OP4 E0061C 0 +OP4 E0061D 0 +OP4 E0061E 0 +OP4 E0061F 0 +OP4 E00620 0 +OP4 E00621 0 +OP4 E00622 0 +OP4 E00623 0 +OP4 E00624 0 +OP4 E00625 0 +OP4 E00626 0 +OP4 E00627 0 +OP4 E00628 0 +OP4 E00629 0 +OP4 E0062A 0 +OP4 E0062B 0 +OP4 E0062C 0 +OP4 E0062D 0 +OP4 E0062E 0 +OP4 E0062F 0 +OP4 E00630 0 +OP4 E00631 0 +OP4 E00632 0 +OP4 E00633 0 +OP4 E00634 0 +OP4 E00635 0 +OP4 E00636 0 +OP4 E00637 0 +OP4 E00638 0 +OP4 E00639 0 +OP4 E0063A 0 +OP4 E0063B 0 +OP4 E0063C 0 +OP4 E0063D 0 +OP4 E0063E 0 +OP4 E0063F 0 +OP4 E00640 0 +OP4 E00641 0 +OP4 E00642 0 +OP4 E00643 0 +OP4 E00644 0 +OP4 E00645 0 +OP4 E00646 0 +OP4 E00647 0 +OP4 E00648 0 +OP4 E00649 0 +OP4 E0064A 0 +OP4 E0064B 0 +OP4 E0064C 0 +OP4 E0064D 0 +OP4 E0064E 0 +OP4 E0064F 0 +OP4 E00650 0 +OP4 E00651 0 +OP4 E00652 0 +OP4 E00653 0 +OP4 E00654 0 +OP4 E00655 0 +OP4 E00656 0 +OP4 E00657 0 +OP4 E00658 0 +OP4 E00659 0 +OP4 E0065A 0 +OP4 E0065B 0 +OP4 E0065C 0 +OP4 E0065D 0 +OP4 E0065E 0 +OP4 E0065F 0 +OP4 E00660 0 +OP4 E00661 0 +OP4 E00662 0 +OP4 E00663 0 +OP4 E00664 0 +OP4 E00665 0 +OP4 E00666 0 +OP4 E00667 0 +OP4 E00668 0 +OP4 E00669 0 +OP4 E0066A 0 +OP4 E0066B 0 +OP4 E0066C 0 +OP4 E0066D 0 +OP4 E0066E 0 +OP4 E0066F 0 +OP4 E00670 0 +OP4 E00671 0 +OP4 E00672 0 +OP4 E00673 0 +OP4 E00674 0 +OP4 E00675 0 +OP4 E00676 0 +OP4 E00677 0 +OP4 E00678 0 +OP4 E00679 0 +OP4 E0067A 0 +OP4 E0067B 0 +OP4 E0067C 0 +OP4 E0067D 0 +OP4 E0067E 0 +OP4 E0067F 0 +OP4 E00680 0 +OP4 E00681 0 +OP4 E00682 0 +OP4 E00683 0 +OP4 E00684 0 +OP4 E00685 0 +OP4 E00686 0 +OP4 E00687 0 +OP4 E00688 0 +OP4 E00689 0 +OP4 E0068A 0 +OP4 E0068B 0 +OP4 E0068C 0 +OP4 E0068D 0 +OP4 E0068E 0 +OP4 E0068F 0 +OP4 E00690 0 +OP4 E00691 0 +OP4 E00692 0 +OP4 E00693 0 +OP4 E00694 0 +OP4 E00695 0 +OP4 E00696 0 +OP4 E00697 0 +OP4 E00698 0 +OP4 E00699 0 +OP4 E0069A 0 +OP4 E0069B 0 +OP4 E0069C 0 +OP4 E0069D 0 +OP4 E0069E 0 +OP4 E0069F 0 +OP4 E006A0 0 +OP4 E006A1 0 +OP4 E006A2 0 +OP4 E006A3 0 +OP4 E006A4 0 +OP4 E006A5 0 +OP4 E006A6 0 +OP4 E006A7 0 +OP4 E006A8 0 +OP4 E006A9 0 +OP4 E006AA 0 +OP4 E006AB 0 +OP4 E006AC 0 +OP4 E006AD 0 +OP4 E006AE 0 +OP4 E006AF 0 +OP4 E006B0 0 +OP4 E006B1 0 +OP4 E006B2 0 +OP4 E006B3 0 +OP4 E006B4 0 +OP4 E006B5 0 +OP4 E006B6 0 +OP4 E006B7 0 +OP4 E006B8 0 +OP4 E006B9 0 +OP4 E006BA 0 +OP4 E006BB 0 +OP4 E006BC 0 +OP4 E006BD 0 +OP4 E006BE 0 +OP4 E006BF 0 +OP4 E006C0 0 +OP4 E006C1 0 +OP4 E006C2 0 +OP4 E006C3 0 +OP4 E006C4 0 +OP4 E006C5 0 +OP4 E006C6 0 +OP4 E006C7 0 +OP4 E006C8 0 +OP4 E006C9 0 +OP4 E006CA 0 +OP4 E006CB 0 +OP4 E006CC 0 +OP4 E006CD 0 +OP4 E006CE 0 +OP4 E006CF 0 +OP4 E006D0 0 +OP4 E006D1 0 +OP4 E006D2 0 +OP4 E006D3 0 +OP4 E006D4 0 +OP4 E006D5 0 +OP4 E006D6 0 +OP4 E006D7 0 +OP4 E006D8 0 +OP4 E006D9 0 +OP4 E006DA 0 +OP4 E006DB 0 +OP4 E006DC 0 +OP4 E006DD 0 +OP4 E006DE 0 +OP4 E006DF 0 +OP4 E006E0 0 +OP4 E006E1 0 +OP4 E006E2 0 +OP4 E006E3 0 +OP4 E006E4 0 +OP4 E006E5 0 +OP4 E006E6 0 +OP4 E006E7 0 +OP4 E006E8 0 +OP4 E006E9 0 +OP4 E006EA 0 +OP4 E006EB 0 +OP4 E006EC 0 +OP4 E006ED 0 +OP4 E006EE 0 +OP4 E006EF 0 +OP4 E006F0 0 +OP4 E006F1 0 +OP4 E006F2 0 +OP4 E006F3 0 +OP4 E006F4 0 +OP4 E006F5 0 +OP4 E006F6 0 +OP4 E006F7 0 +OP4 E006F8 0 +OP4 E006F9 0 +OP4 E006FA 0 +OP4 E006FB 0 +OP4 E006FC 0 +OP4 E006FD 0 +OP4 E006FE 0 +OP4 E006FF 0 +OP4 E00700 0 +OP4 E00701 0 +OP4 E00702 0 +OP4 E00703 0 +OP4 E00704 0 +OP4 E00705 0 +OP4 E00706 0 +OP4 E00707 0 +OP4 E00708 0 +OP4 E00709 0 +OP4 E0070A 0 +OP4 E0070B 0 +OP4 E0070C 0 +OP4 E0070D 0 +OP4 E0070E 0 +OP4 E0070F 0 +OP4 E00710 0 +OP4 E00711 0 +OP4 E00712 0 +OP4 E00713 0 +OP4 E00714 0 +OP4 E00715 0 +OP4 E00716 0 +OP4 E00717 0 +OP4 E00718 0 +OP4 E00719 0 +OP4 E0071A 0 +OP4 E0071B 0 +OP4 E0071C 0 +OP4 E0071D 0 +OP4 E0071E 0 +OP4 E0071F 0 +OP4 E00720 0 +OP4 E00721 0 +OP4 E00722 0 +OP4 E00723 0 +OP4 E00724 0 +OP4 E00725 0 +OP4 E00726 0 +OP4 E00727 0 +OP4 E00728 0 +OP4 E00729 0 +OP4 E0072A 0 +OP4 E0072B 0 +OP4 E0072C 0 +OP4 E0072D 0 +OP4 E0072E 0 +OP4 E0072F 0 +OP4 E00730 0 +OP4 E00731 0 +OP4 E00732 0 +OP4 E00733 0 +OP4 E00734 0 +OP4 E00735 0 +OP4 E00736 0 +OP4 E00737 0 +OP4 E00738 0 +OP4 E00739 0 +OP4 E0073A 0 +OP4 E0073B 0 +OP4 E0073C 0 +OP4 E0073D 0 +OP4 E0073E 0 +OP4 E0073F 0 +OP4 E00740 0 +OP4 E00741 0 +OP4 E00742 0 +OP4 E00743 0 +OP4 E00744 0 +OP4 E00745 0 +OP4 E00746 0 +OP4 E00747 0 +OP4 E00748 0 +OP4 E00749 0 +OP4 E0074A 0 +OP4 E0074B 0 +OP4 E0074C 0 +OP4 E0074D 0 +OP4 E0074E 0 +OP4 E0074F 0 +OP4 E00750 0 +OP4 E00751 0 +OP4 E00752 0 +OP4 E00753 0 +OP4 E00754 0 +OP4 E00755 0 +OP4 E00756 0 +OP4 E00757 0 +OP4 E00758 0 +OP4 E00759 0 +OP4 E0075A 0 +OP4 E0075B 0 +OP4 E0075C 0 +OP4 E0075D 0 +OP4 E0075E 0 +OP4 E0075F 0 +OP4 E00760 0 +OP4 E00761 0 +OP4 E00762 0 +OP4 E00763 0 +OP4 E00764 0 +OP4 E00765 0 +OP4 E00766 0 +OP4 E00767 0 +OP4 E00768 0 +OP4 E00769 0 +OP4 E0076A 0 +OP4 E0076B 0 +OP4 E0076C 0 +OP4 E0076D 0 +OP4 E0076E 0 +OP4 E0076F 0 +OP4 E00770 0 +OP4 E00771 0 +OP4 E00772 0 +OP4 E00773 0 +OP4 E00774 0 +OP4 E00775 0 +OP4 E00776 0 +OP4 E00777 0 +OP4 E00778 0 +OP4 E00779 0 +OP4 E0077A 0 +OP4 E0077B 0 +OP4 E0077C 0 +OP4 E0077D 0 +OP4 E0077E 0 +OP4 E0077F 0 +OP4 E00780 0 +OP4 E00781 0 +OP4 E00782 0 +OP4 E00783 0 +OP4 E00784 0 +OP4 E00785 0 +OP4 E00786 0 +OP4 E00787 0 +OP4 E00788 0 +OP4 E00789 0 +OP4 E0078A 0 +OP4 E0078B 0 +OP4 E0078C 0 +OP4 E0078D 0 +OP4 E0078E 0 +OP4 E0078F 0 +OP4 E00790 0 +OP4 E00791 0 +OP4 E00792 0 +OP4 E00793 0 +OP4 E00794 0 +OP4 E00795 0 +OP4 E00796 0 +OP4 E00797 0 +OP4 E00798 0 +OP4 E00799 0 +OP4 E0079A 0 +OP4 E0079B 0 +OP4 E0079C 0 +OP4 E0079D 0 +OP4 E0079E 0 +OP4 E0079F 0 +OP4 E007A0 0 +OP4 E007A1 0 +OP4 E007A2 0 +OP4 E007A3 0 +OP4 E007A4 0 +OP4 E007A5 0 +OP4 E007A6 0 +OP4 E007A7 0 +OP4 E007A8 0 +OP4 E007A9 0 +OP4 E007AA 0 +OP4 E007AB 0 +OP4 E007AC 0 +OP4 E007AD 0 +OP4 E007AE 0 +OP4 E007AF 0 +OP4 E007B0 0 +OP4 E007B1 0 +OP4 E007B2 0 +OP4 E007B3 0 +OP4 E007B4 0 +OP4 E007B5 0 +OP4 E007B6 0 +OP4 E007B7 0 +OP4 E007B8 0 +OP4 E007B9 0 +OP4 E007BA 0 +OP4 E007BB 0 +OP4 E007BC 0 +OP4 E007BD 0 +OP4 E007BE 0 +OP4 E007BF 0 +OP4 E007C0 0 +OP4 E007C1 0 +OP4 E007C2 0 +OP4 E007C3 0 +OP4 E007C4 0 +OP4 E007C5 0 +OP4 E007C6 0 +OP4 E007C7 0 +OP4 E007C8 0 +OP4 E007C9 0 +OP4 E007CA 0 +OP4 E007CB 0 +OP4 E007CC 0 +OP4 E007CD 0 +OP4 E007CE 0 +OP4 E007CF 0 +OP4 E007D0 0 +OP4 E007D1 0 +OP4 E007D2 0 +OP4 E007D3 0 +OP4 E007D4 0 +OP4 E007D5 0 +OP4 E007D6 0 +OP4 E007D7 0 +OP4 E007D8 0 +OP4 E007D9 0 +OP4 E007DA 0 +OP4 E007DB 0 +OP4 E007DC 0 +OP4 E007DD 0 +OP4 E007DE 0 +OP4 E007DF 0 +OP4 E007E0 0 +OP4 E007E1 0 +OP4 E007E2 0 +OP4 E007E3 0 +OP4 E007E4 0 +OP4 E007E5 0 +OP4 E007E6 0 +OP4 E007E7 0 +OP4 E007E8 0 +OP4 E007E9 0 +OP4 E007EA 0 +OP4 E007EB 0 +OP4 E007EC 0 +OP4 E007ED 0 +OP4 E007EE 0 +OP4 E007EF 0 +OP4 E007F0 0 +OP4 E007F1 0 +OP4 E007F2 0 +OP4 E007F3 0 +OP4 E007F4 0 +OP4 E007F5 0 +OP4 E007F6 0 +OP4 E007F7 0 +OP4 E007F8 0 +OP4 E007F9 0 +OP4 E007FA 0 +OP4 E007FB 0 +OP4 E007FC 0 +OP4 E007FD 0 +OP4 E007FE 0 +OP4 E007FF 0 +OP4 E00800 0 +OP4 E00801 0 +OP4 E00802 0 +OP4 E00803 0 +OP4 E00804 0 +OP4 E00805 0 +OP4 E00806 0 +OP4 E00807 0 +OP4 E00808 0 +OP4 E00809 0 +OP4 E0080A 0 +OP4 E0080B 0 +OP4 E0080C 0 +OP4 E0080D 0 +OP4 E0080E 0 +OP4 E0080F 0 +OP4 E00810 0 +OP4 E00811 0 +OP4 E00812 0 +OP4 E00813 0 +OP4 E00814 0 +OP4 E00815 0 +OP4 E00816 0 +OP4 E00817 0 +OP4 E00818 0 +OP4 E00819 0 +OP4 E0081A 0 +OP4 E0081B 0 +OP4 E0081C 0 +OP4 E0081D 0 +OP4 E0081E 0 +OP4 E0081F 0 +OP4 E00820 0 +OP4 E00821 0 +OP4 E00822 0 +OP4 E00823 0 +OP4 E00824 0 +OP4 E00825 0 +OP4 E00826 0 +OP4 E00827 0 +OP4 E00828 0 +OP4 E00829 0 +OP4 E0082A 0 +OP4 E0082B 0 +OP4 E0082C 0 +OP4 E0082D 0 +OP4 E0082E 0 +OP4 E0082F 0 +OP4 E00830 0 +OP4 E00831 0 +OP4 E00832 0 +OP4 E00833 0 +OP4 E00834 0 +OP4 E00835 0 +OP4 E00836 0 +OP4 E00837 0 +OP4 E00838 0 +OP4 E00839 0 +OP4 E0083A 0 +OP4 E0083B 0 +OP4 E0083C 0 +OP4 E0083D 0 +OP4 E0083E 0 +OP4 E0083F 0 +OP4 E00840 0 +OP4 E00841 0 +OP4 E00842 0 +OP4 E00843 0 +OP4 E00844 0 +OP4 E00845 0 +OP4 E00846 0 +OP4 E00847 0 +OP4 E00848 0 +OP4 E00849 0 +OP4 E0084A 0 +OP4 E0084B 0 +OP4 E0084C 0 +OP4 E0084D 0 +OP4 E0084E 0 +OP4 E0084F 0 +OP4 E00850 0 +OP4 E00851 0 +OP4 E00852 0 +OP4 E00853 0 +OP4 E00854 0 +OP4 E00855 0 +OP4 E00856 0 +OP4 E00857 0 +OP4 E00858 0 +OP4 E00859 0 +OP4 E0085A 0 +OP4 E0085B 0 +OP4 E0085C 0 +OP4 E0085D 0 +OP4 E0085E 0 +OP4 E0085F 0 +OP4 E00860 0 +OP4 E00861 0 +OP4 E00862 0 +OP4 E00863 0 +OP4 E00864 0 +OP4 E00865 0 +OP4 E00866 0 +OP4 E00867 0 +OP4 E00868 0 +OP4 E00869 0 +OP4 E0086A 0 +OP4 E0086B 0 +OP4 E0086C 0 +OP4 E0086D 0 +OP4 E0086E 0 +OP4 E0086F 0 +OP4 E00870 0 +OP4 E00871 0 +OP4 E00872 0 +OP4 E00873 0 +OP4 E00874 0 +OP4 E00875 0 +OP4 E00876 0 +OP4 E00877 0 +OP4 E00878 0 +OP4 E00879 0 +OP4 E0087A 0 +OP4 E0087B 0 +OP4 E0087C 0 +OP4 E0087D 0 +OP4 E0087E 0 +OP4 E0087F 0 +OP4 E00880 0 +OP4 E00881 0 +OP4 E00882 0 +OP4 E00883 0 +OP4 E00884 0 +OP4 E00885 0 +OP4 E00886 0 +OP4 E00887 0 +OP4 E00888 0 +OP4 E00889 0 +OP4 E0088A 0 +OP4 E0088B 0 +OP4 E0088C 0 +OP4 E0088D 0 +OP4 E0088E 0 +OP4 E0088F 0 +OP4 E00890 0 +OP4 E00891 0 +OP4 E00892 0 +OP4 E00893 0 +OP4 E00894 0 +OP4 E00895 0 +OP4 E00896 0 +OP4 E00897 0 +OP4 E00898 0 +OP4 E00899 0 +OP4 E0089A 0 +OP4 E0089B 0 +OP4 E0089C 0 +OP4 E0089D 0 +OP4 E0089E 0 +OP4 E0089F 0 +OP4 E008A0 0 +OP4 E008A1 0 +OP4 E008A2 0 +OP4 E008A3 0 +OP4 E008A4 0 +OP4 E008A5 0 +OP4 E008A6 0 +OP4 E008A7 0 +OP4 E008A8 0 +OP4 E008A9 0 +OP4 E008AA 0 +OP4 E008AB 0 +OP4 E008AC 0 +OP4 E008AD 0 +OP4 E008AE 0 +OP4 E008AF 0 +OP4 E008B0 0 +OP4 E008B1 0 +OP4 E008B2 0 +OP4 E008B3 0 +OP4 E008B4 0 +OP4 E008B5 0 +OP4 E008B6 0 +OP4 E008B7 0 +OP4 E008B8 0 +OP4 E008B9 0 +OP4 E008BA 0 +OP4 E008BB 0 +OP4 E008BC 0 +OP4 E008BD 0 +OP4 E008BE 0 +OP4 E008BF 0 +OP4 E008C0 0 +OP4 E008C1 0 +OP4 E008C2 0 +OP4 E008C3 0 +OP4 E008C4 0 +OP4 E008C5 0 +OP4 E008C6 0 +OP4 E008C7 0 +OP4 E008C8 0 +OP4 E008C9 0 +OP4 E008CA 0 +OP4 E008CB 0 +OP4 E008CC 0 +OP4 E008CD 0 +OP4 E008CE 0 +OP4 E008CF 0 +OP4 E008D0 0 +OP4 E008D1 0 +OP4 E008D2 0 +OP4 E008D3 0 +OP4 E008D4 0 +OP4 E008D5 0 +OP4 E008D6 0 +OP4 E008D7 0 +OP4 E008D8 0 +OP4 E008D9 0 +OP4 E008DA 0 +OP4 E008DB 0 +OP4 E008DC 0 +OP4 E008DD 0 +OP4 E008DE 0 +OP4 E008DF 0 +OP4 E008E0 0 +OP4 E008E1 0 +OP4 E008E2 0 +OP4 E008E3 0 +OP4 E008E4 0 +OP4 E008E5 0 +OP4 E008E6 0 +OP4 E008E7 0 +OP4 E008E8 0 +OP4 E008E9 0 +OP4 E008EA 0 +OP4 E008EB 0 +OP4 E008EC 0 +OP4 E008ED 0 +OP4 E008EE 0 +OP4 E008EF 0 +OP4 E008F0 0 +OP4 E008F1 0 +OP4 E008F2 0 +OP4 E008F3 0 +OP4 E008F4 0 +OP4 E008F5 0 +OP4 E008F6 0 +OP4 E008F7 0 +OP4 E008F8 0 +OP4 E008F9 0 +OP4 E008FA 0 +OP4 E008FB 0 +OP4 E008FC 0 +OP4 E008FD 0 +OP4 E008FE 0 +OP4 E008FF 0 +OP4 E00900 0 +OP4 E00901 0 +OP4 E00902 0 +OP4 E00903 0 +OP4 E00904 0 +OP4 E00905 0 +OP4 E00906 0 +OP4 E00907 0 +OP4 E00908 0 +OP4 E00909 0 +OP4 E0090A 0 +OP4 E0090B 0 +OP4 E0090C 0 +OP4 E0090D 0 +OP4 E0090E 0 +OP4 E0090F 0 +OP4 E00910 0 +OP4 E00911 0 +OP4 E00912 0 +OP4 E00913 0 +OP4 E00914 0 +OP4 E00915 0 +OP4 E00916 0 +OP4 E00917 0 +OP4 E00918 0 +OP4 E00919 0 +OP4 E0091A 0 +OP4 E0091B 0 +OP4 E0091C 0 +OP4 E0091D 0 +OP4 E0091E 0 +OP4 E0091F 0 +OP4 E00920 0 +OP4 E00921 0 +OP4 E00922 0 +OP4 E00923 0 +OP4 E00924 0 +OP4 E00925 0 +OP4 E00926 0 +OP4 E00927 0 +OP4 E00928 0 +OP4 E00929 0 +OP4 E0092A 0 +OP4 E0092B 0 +OP4 E0092C 0 +OP4 E0092D 0 +OP4 E0092E 0 +OP4 E0092F 0 +OP4 E00930 0 +OP4 E00931 0 +OP4 E00932 0 +OP4 E00933 0 +OP4 E00934 0 +OP4 E00935 0 +OP4 E00936 0 +OP4 E00937 0 +OP4 E00938 0 +OP4 E00939 0 +OP4 E0093A 0 +OP4 E0093B 0 +OP4 E0093C 0 +OP4 E0093D 0 +OP4 E0093E 0 +OP4 E0093F 0 +OP4 E00940 0 +OP4 E00941 0 +OP4 E00942 0 +OP4 E00943 0 +OP4 E00944 0 +OP4 E00945 0 +OP4 E00946 0 +OP4 E00947 0 +OP4 E00948 0 +OP4 E00949 0 +OP4 E0094A 0 +OP4 E0094B 0 +OP4 E0094C 0 +OP4 E0094D 0 +OP4 E0094E 0 +OP4 E0094F 0 +OP4 E00950 0 +OP4 E00951 0 +OP4 E00952 0 +OP4 E00953 0 +OP4 E00954 0 +OP4 E00955 0 +OP4 E00956 0 +OP4 E00957 0 +OP4 E00958 0 +OP4 E00959 0 +OP4 E0095A 0 +OP4 E0095B 0 +OP4 E0095C 0 +OP4 E0095D 0 +OP4 E0095E 0 +OP4 E0095F 0 +OP4 E00960 0 +OP4 E00961 0 +OP4 E00962 0 +OP4 E00963 0 +OP4 E00964 0 +OP4 E00965 0 +OP4 E00966 0 +OP4 E00967 0 +OP4 E00968 0 +OP4 E00969 0 +OP4 E0096A 0 +OP4 E0096B 0 +OP4 E0096C 0 +OP4 E0096D 0 +OP4 E0096E 0 +OP4 E0096F 0 +OP4 E00970 0 +OP4 E00971 0 +OP4 E00972 0 +OP4 E00973 0 +OP4 E00974 0 +OP4 E00975 0 +OP4 E00976 0 +OP4 E00977 0 +OP4 E00978 0 +OP4 E00979 0 +OP4 E0097A 0 +OP4 E0097B 0 +OP4 E0097C 0 +OP4 E0097D 0 +OP4 E0097E 0 +OP4 E0097F 0 +OP4 E00980 0 +OP4 E00981 0 +OP4 E00982 0 +OP4 E00983 0 +OP4 E00984 0 +OP4 E00985 0 +OP4 E00986 0 +OP4 E00987 0 +OP4 E00988 0 +OP4 E00989 0 +OP4 E0098A 0 +OP4 E0098B 0 +OP4 E0098C 0 +OP4 E0098D 0 +OP4 E0098E 0 +OP4 E0098F 0 +OP4 E00990 0 +OP4 E00991 0 +OP4 E00992 0 +OP4 E00993 0 +OP4 E00994 0 +OP4 E00995 0 +OP4 E00996 0 +OP4 E00997 0 +OP4 E00998 0 +OP4 E00999 0 +OP4 E0099A 0 +OP4 E0099B 0 +OP4 E0099C 0 +OP4 E0099D 0 +OP4 E0099E 0 +OP4 E0099F 0 +OP4 E009A0 0 +OP4 E009A1 0 +OP4 E009A2 0 +OP4 E009A3 0 +OP4 E009A4 0 +OP4 E009A5 0 +OP4 E009A6 0 +OP4 E009A7 0 +OP4 E009A8 0 +OP4 E009A9 0 +OP4 E009AA 0 +OP4 E009AB 0 +OP4 E009AC 0 +OP4 E009AD 0 +OP4 E009AE 0 +OP4 E009AF 0 +OP4 E009B0 0 +OP4 E009B1 0 +OP4 E009B2 0 +OP4 E009B3 0 +OP4 E009B4 0 +OP4 E009B5 0 +OP4 E009B6 0 +OP4 E009B7 0 +OP4 E009B8 0 +OP4 E009B9 0 +OP4 E009BA 0 +OP4 E009BB 0 +OP4 E009BC 0 +OP4 E009BD 0 +OP4 E009BE 0 +OP4 E009BF 0 +OP4 E009C0 0 +OP4 E009C1 0 +OP4 E009C2 0 +OP4 E009C3 0 +OP4 E009C4 0 +OP4 E009C5 0 +OP4 E009C6 0 +OP4 E009C7 0 +OP4 E009C8 0 +OP4 E009C9 0 +OP4 E009CA 0 +OP4 E009CB 0 +OP4 E009CC 0 +OP4 E009CD 0 +OP4 E009CE 0 +OP4 E009CF 0 +OP4 E009D0 0 +OP4 E009D1 0 +OP4 E009D2 0 +OP4 E009D3 0 +OP4 E009D4 0 +OP4 E009D5 0 +OP4 E009D6 0 +OP4 E009D7 0 +OP4 E009D8 0 +OP4 E009D9 0 +OP4 E009DA 0 +OP4 E009DB 0 +OP4 E009DC 0 +OP4 E009DD 0 +OP4 E009DE 0 +OP4 E009DF 0 +OP4 E009E0 0 +OP4 E009E1 0 +OP4 E009E2 0 +OP4 E009E3 0 +OP4 E009E4 0 +OP4 E009E5 0 +OP4 E009E6 0 +OP4 E009E7 0 +OP4 E009E8 0 +OP4 E009E9 0 +OP4 E009EA 0 +OP4 E009EB 0 +OP4 E009EC 0 +OP4 E009ED 0 +OP4 E009EE 0 +OP4 E009EF 0 +OP4 E009F0 0 +OP4 E009F1 0 +OP4 E009F2 0 +OP4 E009F3 0 +OP4 E009F4 0 +OP4 E009F5 0 +OP4 E009F6 0 +OP4 E009F7 0 +OP4 E009F8 0 +OP4 E009F9 0 +OP4 E009FA 0 +OP4 E009FB 0 +OP4 E009FC 0 +OP4 E009FD 0 +OP4 E009FE 0 +OP4 E009FF 0 +OP4 E00A00 0 +OP4 E00A01 0 +OP4 E00A02 0 +OP4 E00A03 0 +OP4 E00A04 0 +OP4 E00A05 0 +OP4 E00A06 0 +OP4 E00A07 0 +OP4 E00A08 0 +OP4 E00A09 0 +OP4 E00A0A 0 +OP4 E00A0B 0 +OP4 E00A0C 0 +OP4 E00A0D 0 +OP4 E00A0E 0 +OP4 E00A0F 0 +OP4 E00A10 0 +OP4 E00A11 0 +OP4 E00A12 0 +OP4 E00A13 0 +OP4 E00A14 0 +OP4 E00A15 0 +OP4 E00A16 0 +OP4 E00A17 0 +OP4 E00A18 0 +OP4 E00A19 0 +OP4 E00A1A 0 +OP4 E00A1B 0 +OP4 E00A1C 0 +OP4 E00A1D 0 +OP4 E00A1E 0 +OP4 E00A1F 0 +OP4 E00A20 0 +OP4 E00A21 0 +OP4 E00A22 0 +OP4 E00A23 0 +OP4 E00A24 0 +OP4 E00A25 0 +OP4 E00A26 0 +OP4 E00A27 0 +OP4 E00A28 0 +OP4 E00A29 0 +OP4 E00A2A 0 +OP4 E00A2B 0 +OP4 E00A2C 0 +OP4 E00A2D 0 +OP4 E00A2E 0 +OP4 E00A2F 0 +OP4 E00A30 0 +OP4 E00A31 0 +OP4 E00A32 0 +OP4 E00A33 0 +OP4 E00A34 0 +OP4 E00A35 0 +OP4 E00A36 0 +OP4 E00A37 0 +OP4 E00A38 0 +OP4 E00A39 0 +OP4 E00A3A 0 +OP4 E00A3B 0 +OP4 E00A3C 0 +OP4 E00A3D 0 +OP4 E00A3E 0 +OP4 E00A3F 0 +OP4 E00A40 0 +OP4 E00A41 0 +OP4 E00A42 0 +OP4 E00A43 0 +OP4 E00A44 0 +OP4 E00A45 0 +OP4 E00A46 0 +OP4 E00A47 0 +OP4 E00A48 0 +OP4 E00A49 0 +OP4 E00A4A 0 +OP4 E00A4B 0 +OP4 E00A4C 0 +OP4 E00A4D 0 +OP4 E00A4E 0 +OP4 E00A4F 0 +OP4 E00A50 0 +OP4 E00A51 0 +OP4 E00A52 0 +OP4 E00A53 0 +OP4 E00A54 0 +OP4 E00A55 0 +OP4 E00A56 0 +OP4 E00A57 0 +OP4 E00A58 0 +OP4 E00A59 0 +OP4 E00A5A 0 +OP4 E00A5B 0 +OP4 E00A5C 0 +OP4 E00A5D 0 +OP4 E00A5E 0 +OP4 E00A5F 0 +OP4 E00A60 0 +OP4 E00A61 0 +OP4 E00A62 0 +OP4 E00A63 0 +OP4 E00A64 0 +OP4 E00A65 0 +OP4 E00A66 0 +OP4 E00A67 0 +OP4 E00A68 0 +OP4 E00A69 0 +OP4 E00A6A 0 +OP4 E00A6B 0 +OP4 E00A6C 0 +OP4 E00A6D 0 +OP4 E00A6E 0 +OP4 E00A6F 0 +OP4 E00A70 0 +OP4 E00A71 0 +OP4 E00A72 0 +OP4 E00A73 0 +OP4 E00A74 0 +OP4 E00A75 0 +OP4 E00A76 0 +OP4 E00A77 0 +OP4 E00A78 0 +OP4 E00A79 0 +OP4 E00A7A 0 +OP4 E00A7B 0 +OP4 E00A7C 0 +OP4 E00A7D 0 +OP4 E00A7E 0 +OP4 E00A7F 0 +OP4 E00A80 0 +OP4 E00A81 0 +OP4 E00A82 0 +OP4 E00A83 0 +OP4 E00A84 0 +OP4 E00A85 0 +OP4 E00A86 0 +OP4 E00A87 0 +OP4 E00A88 0 +OP4 E00A89 0 +OP4 E00A8A 0 +OP4 E00A8B 0 +OP4 E00A8C 0 +OP4 E00A8D 0 +OP4 E00A8E 0 +OP4 E00A8F 0 +OP4 E00A90 0 +OP4 E00A91 0 +OP4 E00A92 0 +OP4 E00A93 0 +OP4 E00A94 0 +OP4 E00A95 0 +OP4 E00A96 0 +OP4 E00A97 0 +OP4 E00A98 0 +OP4 E00A99 0 +OP4 E00A9A 0 +OP4 E00A9B 0 +OP4 E00A9C 0 +OP4 E00A9D 0 +OP4 E00A9E 0 +OP4 E00A9F 0 +OP4 E00AA0 0 +OP4 E00AA1 0 +OP4 E00AA2 0 +OP4 E00AA3 0 +OP4 E00AA4 0 +OP4 E00AA5 0 +OP4 E00AA6 0 +OP4 E00AA7 0 +OP4 E00AA8 0 +OP4 E00AA9 0 +OP4 E00AAA 0 +OP4 E00AAB 0 +OP4 E00AAC 0 +OP4 E00AAD 0 +OP4 E00AAE 0 +OP4 E00AAF 0 +OP4 E00AB0 0 +OP4 E00AB1 0 +OP4 E00AB2 0 +OP4 E00AB3 0 +OP4 E00AB4 0 +OP4 E00AB5 0 +OP4 E00AB6 0 +OP4 E00AB7 0 +OP4 E00AB8 0 +OP4 E00AB9 0 +OP4 E00ABA 0 +OP4 E00ABB 0 +OP4 E00ABC 0 +OP4 E00ABD 0 +OP4 E00ABE 0 +OP4 E00ABF 0 +OP4 E00AC0 0 +OP4 E00AC1 0 +OP4 E00AC2 0 +OP4 E00AC3 0 +OP4 E00AC4 0 +OP4 E00AC5 0 +OP4 E00AC6 0 +OP4 E00AC7 0 +OP4 E00AC8 0 +OP4 E00AC9 0 +OP4 E00ACA 0 +OP4 E00ACB 0 +OP4 E00ACC 0 +OP4 E00ACD 0 +OP4 E00ACE 0 +OP4 E00ACF 0 +OP4 E00AD0 0 +OP4 E00AD1 0 +OP4 E00AD2 0 +OP4 E00AD3 0 +OP4 E00AD4 0 +OP4 E00AD5 0 +OP4 E00AD6 0 +OP4 E00AD7 0 +OP4 E00AD8 0 +OP4 E00AD9 0 +OP4 E00ADA 0 +OP4 E00ADB 0 +OP4 E00ADC 0 +OP4 E00ADD 0 +OP4 E00ADE 0 +OP4 E00ADF 0 +OP4 E00AE0 0 +OP4 E00AE1 0 +OP4 E00AE2 0 +OP4 E00AE3 0 +OP4 E00AE4 0 +OP4 E00AE5 0 +OP4 E00AE6 0 +OP4 E00AE7 0 +OP4 E00AE8 0 +OP4 E00AE9 0 +OP4 E00AEA 0 +OP4 E00AEB 0 +OP4 E00AEC 0 +OP4 E00AED 0 +OP4 E00AEE 0 +OP4 E00AEF 0 +OP4 E00AF0 0 +OP4 E00AF1 0 +OP4 E00AF2 0 +OP4 E00AF3 0 +OP4 E00AF4 0 +OP4 E00AF5 0 +OP4 E00AF6 0 +OP4 E00AF7 0 +OP4 E00AF8 0 +OP4 E00AF9 0 +OP4 E00AFA 0 +OP4 E00AFB 0 +OP4 E00AFC 0 +OP4 E00AFD 0 +OP4 E00AFE 0 +OP4 E00AFF 0 +OP4 E00B00 0 +OP4 E00B01 0 +OP4 E00B02 0 +OP4 E00B03 0 +OP4 E00B04 0 +OP4 E00B05 0 +OP4 E00B06 0 +OP4 E00B07 0 +OP4 E00B08 0 +OP4 E00B09 0 +OP4 E00B0A 0 +OP4 E00B0B 0 +OP4 E00B0C 0 +OP4 E00B0D 0 +OP4 E00B0E 0 +OP4 E00B0F 0 +OP4 E00B10 0 +OP4 E00B11 0 +OP4 E00B12 0 +OP4 E00B13 0 +OP4 E00B14 0 +OP4 E00B15 0 +OP4 E00B16 0 +OP4 E00B17 0 +OP4 E00B18 0 +OP4 E00B19 0 +OP4 E00B1A 0 +OP4 E00B1B 0 +OP4 E00B1C 0 +OP4 E00B1D 0 +OP4 E00B1E 0 +OP4 E00B1F 0 +OP4 E00B20 0 +OP4 E00B21 0 +OP4 E00B22 0 +OP4 E00B23 0 +OP4 E00B24 0 +OP4 E00B25 0 +OP4 E00B26 0 +OP4 E00B27 0 +OP4 E00B28 0 +OP4 E00B29 0 +OP4 E00B2A 0 +OP4 E00B2B 0 +OP4 E00B2C 0 +OP4 E00B2D 0 +OP4 E00B2E 0 +OP4 E00B2F 0 +OP4 E00B30 0 +OP4 E00B31 0 +OP4 E00B32 0 +OP4 E00B33 0 +OP4 E00B34 0 +OP4 E00B35 0 +OP4 E00B36 0 +OP4 E00B37 0 +OP4 E00B38 0 +OP4 E00B39 0 +OP4 E00B3A 0 +OP4 E00B3B 0 +OP4 E00B3C 0 +OP4 E00B3D 0 +OP4 E00B3E 0 +OP4 E00B3F 0 +OP4 E00B40 0 +OP4 E00B41 0 +OP4 E00B42 0 +OP4 E00B43 0 +OP4 E00B44 0 +OP4 E00B45 0 +OP4 E00B46 0 +OP4 E00B47 0 +OP4 E00B48 0 +OP4 E00B49 0 +OP4 E00B4A 0 +OP4 E00B4B 0 +OP4 E00B4C 0 +OP4 E00B4D 0 +OP4 E00B4E 0 +OP4 E00B4F 0 +OP4 E00B50 0 +OP4 E00B51 0 +OP4 E00B52 0 +OP4 E00B53 0 +OP4 E00B54 0 +OP4 E00B55 0 +OP4 E00B56 0 +OP4 E00B57 0 +OP4 E00B58 0 +OP4 E00B59 0 +OP4 E00B5A 0 +OP4 E00B5B 0 +OP4 E00B5C 0 +OP4 E00B5D 0 +OP4 E00B5E 0 +OP4 E00B5F 0 +OP4 E00B60 0 +OP4 E00B61 0 +OP4 E00B62 0 +OP4 E00B63 0 +OP4 E00B64 0 +OP4 E00B65 0 +OP4 E00B66 0 +OP4 E00B67 0 +OP4 E00B68 0 +OP4 E00B69 0 +OP4 E00B6A 0 +OP4 E00B6B 0 +OP4 E00B6C 0 +OP4 E00B6D 0 +OP4 E00B6E 0 +OP4 E00B6F 0 +OP4 E00B70 0 +OP4 E00B71 0 +OP4 E00B72 0 +OP4 E00B73 0 +OP4 E00B74 0 +OP4 E00B75 0 +OP4 E00B76 0 +OP4 E00B77 0 +OP4 E00B78 0 +OP4 E00B79 0 +OP4 E00B7A 0 +OP4 E00B7B 0 +OP4 E00B7C 0 +OP4 E00B7D 0 +OP4 E00B7E 0 +OP4 E00B7F 0 +OP4 E00B80 0 +OP4 E00B81 0 +OP4 E00B82 0 +OP4 E00B83 0 +OP4 E00B84 0 +OP4 E00B85 0 +OP4 E00B86 0 +OP4 E00B87 0 +OP4 E00B88 0 +OP4 E00B89 0 +OP4 E00B8A 0 +OP4 E00B8B 0 +OP4 E00B8C 0 +OP4 E00B8D 0 +OP4 E00B8E 0 +OP4 E00B8F 0 +OP4 E00B90 0 +OP4 E00B91 0 +OP4 E00B92 0 +OP4 E00B93 0 +OP4 E00B94 0 +OP4 E00B95 0 +OP4 E00B96 0 +OP4 E00B97 0 +OP4 E00B98 0 +OP4 E00B99 0 +OP4 E00B9A 0 +OP4 E00B9B 0 +OP4 E00B9C 0 +OP4 E00B9D 0 +OP4 E00B9E 0 +OP4 E00B9F 0 +OP4 E00BA0 0 +OP4 E00BA1 0 +OP4 E00BA2 0 +OP4 E00BA3 0 +OP4 E00BA4 0 +OP4 E00BA5 0 +OP4 E00BA6 0 +OP4 E00BA7 0 +OP4 E00BA8 0 +OP4 E00BA9 0 +OP4 E00BAA 0 +OP4 E00BAB 0 +OP4 E00BAC 0 +OP4 E00BAD 0 +OP4 E00BAE 0 +OP4 E00BAF 0 +OP4 E00BB0 0 +OP4 E00BB1 0 +OP4 E00BB2 0 +OP4 E00BB3 0 +OP4 E00BB4 0 +OP4 E00BB5 0 +OP4 E00BB6 0 +OP4 E00BB7 0 +OP4 E00BB8 0 +OP4 E00BB9 0 +OP4 E00BBA 0 +OP4 E00BBB 0 +OP4 E00BBC 0 +OP4 E00BBD 0 +OP4 E00BBE 0 +OP4 E00BBF 0 +OP4 E00BC0 0 +OP4 E00BC1 0 +OP4 E00BC2 0 +OP4 E00BC3 0 +OP4 E00BC4 0 +OP4 E00BC5 0 +OP4 E00BC6 0 +OP4 E00BC7 0 +OP4 E00BC8 0 +OP4 E00BC9 0 +OP4 E00BCA 0 +OP4 E00BCB 0 +OP4 E00BCC 0 +OP4 E00BCD 0 +OP4 E00BCE 0 +OP4 E00BCF 0 +OP4 E00BD0 0 +OP4 E00BD1 0 +OP4 E00BD2 0 +OP4 E00BD3 0 +OP4 E00BD4 0 +OP4 E00BD5 0 +OP4 E00BD6 0 +OP4 E00BD7 0 +OP4 E00BD8 0 +OP4 E00BD9 0 +OP4 E00BDA 0 +OP4 E00BDB 0 +OP4 E00BDC 0 +OP4 E00BDD 0 +OP4 E00BDE 0 +OP4 E00BDF 0 +OP4 E00BE0 0 +OP4 E00BE1 0 +OP4 E00BE2 0 +OP4 E00BE3 0 +OP4 E00BE4 0 +OP4 E00BE5 0 +OP4 E00BE6 0 +OP4 E00BE7 0 +OP4 E00BE8 0 +OP4 E00BE9 0 +OP4 E00BEA 0 +OP4 E00BEB 0 +OP4 E00BEC 0 +OP4 E00BED 0 +OP4 E00BEE 0 +OP4 E00BEF 0 +OP4 E00BF0 0 +OP4 E00BF1 0 +OP4 E00BF2 0 +OP4 E00BF3 0 +OP4 E00BF4 0 +OP4 E00BF5 0 +OP4 E00BF6 0 +OP4 E00BF7 0 +OP4 E00BF8 0 +OP4 E00BF9 0 +OP4 E00BFA 0 +OP4 E00BFB 0 +OP4 E00BFC 0 +OP4 E00BFD 0 +OP4 E00BFE 0 +OP4 E00BFF 0 +OP4 E00C00 0 +OP4 E00C01 0 +OP4 E00C02 0 +OP4 E00C03 0 +OP4 E00C04 0 +OP4 E00C05 0 +OP4 E00C06 0 +OP4 E00C07 0 +OP4 E00C08 0 +OP4 E00C09 0 +OP4 E00C0A 0 +OP4 E00C0B 0 +OP4 E00C0C 0 +OP4 E00C0D 0 +OP4 E00C0E 0 +OP4 E00C0F 0 +OP4 E00C10 0 +OP4 E00C11 0 +OP4 E00C12 0 +OP4 E00C13 0 +OP4 E00C14 0 +OP4 E00C15 0 +OP4 E00C16 0 +OP4 E00C17 0 +OP4 E00C18 0 +OP4 E00C19 0 +OP4 E00C1A 0 +OP4 E00C1B 0 +OP4 E00C1C 0 +OP4 E00C1D 0 +OP4 E00C1E 0 +OP4 E00C1F 0 +OP4 E00C20 0 +OP4 E00C21 0 +OP4 E00C22 0 +OP4 E00C23 0 +OP4 E00C24 0 +OP4 E00C25 0 +OP4 E00C26 0 +OP4 E00C27 0 +OP4 E00C28 0 +OP4 E00C29 0 +OP4 E00C2A 0 +OP4 E00C2B 0 +OP4 E00C2C 0 +OP4 E00C2D 0 +OP4 E00C2E 0 +OP4 E00C2F 0 +OP4 E00C30 0 +OP4 E00C31 0 +OP4 E00C32 0 +OP4 E00C33 0 +OP4 E00C34 0 +OP4 E00C35 0 +OP4 E00C36 0 +OP4 E00C37 0 +OP4 E00C38 0 +OP4 E00C39 0 +OP4 E00C3A 0 +OP4 E00C3B 0 +OP4 E00C3C 0 +OP4 E00C3D 0 +OP4 E00C3E 0 +OP4 E00C3F 0 +OP4 E00C40 0 +OP4 E00C41 0 +OP4 E00C42 0 +OP4 E00C43 0 +OP4 E00C44 0 +OP4 E00C45 0 +OP4 E00C46 0 +OP4 E00C47 0 +OP4 E00C48 0 +OP4 E00C49 0 +OP4 E00C4A 0 +OP4 E00C4B 0 +OP4 E00C4C 0 +OP4 E00C4D 0 +OP4 E00C4E 0 +OP4 E00C4F 0 +OP4 E00C50 0 +OP4 E00C51 0 +OP4 E00C52 0 +OP4 E00C53 0 +OP4 E00C54 0 +OP4 E00C55 0 +OP4 E00C56 0 +OP4 E00C57 0 +OP4 E00C58 0 +OP4 E00C59 0 +OP4 E00C5A 0 +OP4 E00C5B 0 +OP4 E00C5C 0 +OP4 E00C5D 0 +OP4 E00C5E 0 +OP4 E00C5F 0 +OP4 E00C60 0 +OP4 E00C61 0 +OP4 E00C62 0 +OP4 E00C63 0 +OP4 E00C64 0 +OP4 E00C65 0 +OP4 E00C66 0 +OP4 E00C67 0 +OP4 E00C68 0 +OP4 E00C69 0 +OP4 E00C6A 0 +OP4 E00C6B 0 +OP4 E00C6C 0 +OP4 E00C6D 0 +OP4 E00C6E 0 +OP4 E00C6F 0 +OP4 E00C70 0 +OP4 E00C71 0 +OP4 E00C72 0 +OP4 E00C73 0 +OP4 E00C74 0 +OP4 E00C75 0 +OP4 E00C76 0 +OP4 E00C77 0 +OP4 E00C78 0 +OP4 E00C79 0 +OP4 E00C7A 0 +OP4 E00C7B 0 +OP4 E00C7C 0 +OP4 E00C7D 0 +OP4 E00C7E 0 +OP4 E00C7F 0 +OP4 E00C80 0 +OP4 E00C81 0 +OP4 E00C82 0 +OP4 E00C83 0 +OP4 E00C84 0 +OP4 E00C85 0 +OP4 E00C86 0 +OP4 E00C87 0 +OP4 E00C88 0 +OP4 E00C89 0 +OP4 E00C8A 0 +OP4 E00C8B 0 +OP4 E00C8C 0 +OP4 E00C8D 0 +OP4 E00C8E 0 +OP4 E00C8F 0 +OP4 E00C90 0 +OP4 E00C91 0 +OP4 E00C92 0 +OP4 E00C93 0 +OP4 E00C94 0 +OP4 E00C95 0 +OP4 E00C96 0 +OP4 E00C97 0 +OP4 E00C98 0 +OP4 E00C99 0 +OP4 E00C9A 0 +OP4 E00C9B 0 +OP4 E00C9C 0 +OP4 E00C9D 0 +OP4 E00C9E 0 +OP4 E00C9F 0 +OP4 E00CA0 0 +OP4 E00CA1 0 +OP4 E00CA2 0 +OP4 E00CA3 0 +OP4 E00CA4 0 +OP4 E00CA5 0 +OP4 E00CA6 0 +OP4 E00CA7 0 +OP4 E00CA8 0 +OP4 E00CA9 0 +OP4 E00CAA 0 +OP4 E00CAB 0 +OP4 E00CAC 0 +OP4 E00CAD 0 +OP4 E00CAE 0 +OP4 E00CAF 0 +OP4 E00CB0 0 +OP4 E00CB1 0 +OP4 E00CB2 0 +OP4 E00CB3 0 +OP4 E00CB4 0 +OP4 E00CB5 0 +OP4 E00CB6 0 +OP4 E00CB7 0 +OP4 E00CB8 0 +OP4 E00CB9 0 +OP4 E00CBA 0 +OP4 E00CBB 0 +OP4 E00CBC 0 +OP4 E00CBD 0 +OP4 E00CBE 0 +OP4 E00CBF 0 +OP4 E00CC0 0 +OP4 E00CC1 0 +OP4 E00CC2 0 +OP4 E00CC3 0 +OP4 E00CC4 0 +OP4 E00CC5 0 +OP4 E00CC6 0 +OP4 E00CC7 0 +OP4 E00CC8 0 +OP4 E00CC9 0 +OP4 E00CCA 0 +OP4 E00CCB 0 +OP4 E00CCC 0 +OP4 E00CCD 0 +OP4 E00CCE 0 +OP4 E00CCF 0 +OP4 E00CD0 0 +OP4 E00CD1 0 +OP4 E00CD2 0 +OP4 E00CD3 0 +OP4 E00CD4 0 +OP4 E00CD5 0 +OP4 E00CD6 0 +OP4 E00CD7 0 +OP4 E00CD8 0 +OP4 E00CD9 0 +OP4 E00CDA 0 +OP4 E00CDB 0 +OP4 E00CDC 0 +OP4 E00CDD 0 +OP4 E00CDE 0 +OP4 E00CDF 0 +OP4 E00CE0 0 +OP4 E00CE1 0 +OP4 E00CE2 0 +OP4 E00CE3 0 +OP4 E00CE4 0 +OP4 E00CE5 0 +OP4 E00CE6 0 +OP4 E00CE7 0 +OP4 E00CE8 0 +OP4 E00CE9 0 +OP4 E00CEA 0 +OP4 E00CEB 0 +OP4 E00CEC 0 +OP4 E00CED 0 +OP4 E00CEE 0 +OP4 E00CEF 0 +OP4 E00CF0 0 +OP4 E00CF1 0 +OP4 E00CF2 0 +OP4 E00CF3 0 +OP4 E00CF4 0 +OP4 E00CF5 0 +OP4 E00CF6 0 +OP4 E00CF7 0 +OP4 E00CF8 0 +OP4 E00CF9 0 +OP4 E00CFA 0 +OP4 E00CFB 0 +OP4 E00CFC 0 +OP4 E00CFD 0 +OP4 E00CFE 0 +OP4 E00CFF 0 +OP4 E00D00 0 +OP4 E00D01 0 +OP4 E00D02 0 +OP4 E00D03 0 +OP4 E00D04 0 +OP4 E00D05 0 +OP4 E00D06 0 +OP4 E00D07 0 +OP4 E00D08 0 +OP4 E00D09 0 +OP4 E00D0A 0 +OP4 E00D0B 0 +OP4 E00D0C 0 +OP4 E00D0D 0 +OP4 E00D0E 0 +OP4 E00D0F 0 +OP4 E00D10 0 +OP4 E00D11 0 +OP4 E00D12 0 +OP4 E00D13 0 +OP4 E00D14 0 +OP4 E00D15 0 +OP4 E00D16 0 +OP4 E00D17 0 +OP4 E00D18 0 +OP4 E00D19 0 +OP4 E00D1A 0 +OP4 E00D1B 0 +OP4 E00D1C 0 +OP4 E00D1D 0 +OP4 E00D1E 0 +OP4 E00D1F 0 +OP4 E00D20 0 +OP4 E00D21 0 +OP4 E00D22 0 +OP4 E00D23 0 +OP4 E00D24 0 +OP4 E00D25 0 +OP4 E00D26 0 +OP4 E00D27 0 +OP4 E00D28 0 +OP4 E00D29 0 +OP4 E00D2A 0 +OP4 E00D2B 0 +OP4 E00D2C 0 +OP4 E00D2D 0 +OP4 E00D2E 0 +OP4 E00D2F 0 +OP4 E00D30 0 +OP4 E00D31 0 +OP4 E00D32 0 +OP4 E00D33 0 +OP4 E00D34 0 +OP4 E00D35 0 +OP4 E00D36 0 +OP4 E00D37 0 +OP4 E00D38 0 +OP4 E00D39 0 +OP4 E00D3A 0 +OP4 E00D3B 0 +OP4 E00D3C 0 +OP4 E00D3D 0 +OP4 E00D3E 0 +OP4 E00D3F 0 +OP4 E00D40 0 +OP4 E00D41 0 +OP4 E00D42 0 +OP4 E00D43 0 +OP4 E00D44 0 +OP4 E00D45 0 +OP4 E00D46 0 +OP4 E00D47 0 +OP4 E00D48 0 +OP4 E00D49 0 +OP4 E00D4A 0 +OP4 E00D4B 0 +OP4 E00D4C 0 +OP4 E00D4D 0 +OP4 E00D4E 0 +OP4 E00D4F 0 +OP4 E00D50 0 +OP4 E00D51 0 +OP4 E00D52 0 +OP4 E00D53 0 +OP4 E00D54 0 +OP4 E00D55 0 +OP4 E00D56 0 +OP4 E00D57 0 +OP4 E00D58 0 +OP4 E00D59 0 +OP4 E00D5A 0 +OP4 E00D5B 0 +OP4 E00D5C 0 +OP4 E00D5D 0 +OP4 E00D5E 0 +OP4 E00D5F 0 +OP4 E00D60 0 +OP4 E00D61 0 +OP4 E00D62 0 +OP4 E00D63 0 +OP4 E00D64 0 +OP4 E00D65 0 +OP4 E00D66 0 +OP4 E00D67 0 +OP4 E00D68 0 +OP4 E00D69 0 +OP4 E00D6A 0 +OP4 E00D6B 0 +OP4 E00D6C 0 +OP4 E00D6D 0 +OP4 E00D6E 0 +OP4 E00D6F 0 +OP4 E00D70 0 +OP4 E00D71 0 +OP4 E00D72 0 +OP4 E00D73 0 +OP4 E00D74 0 +OP4 E00D75 0 +OP4 E00D76 0 +OP4 E00D77 0 +OP4 E00D78 0 +OP4 E00D79 0 +OP4 E00D7A 0 +OP4 E00D7B 0 +OP4 E00D7C 0 +OP4 E00D7D 0 +OP4 E00D7E 0 +OP4 E00D7F 0 +OP4 E00D80 0 +OP4 E00D81 0 +OP4 E00D82 0 +OP4 E00D83 0 +OP4 E00D84 0 +OP4 E00D85 0 +OP4 E00D86 0 +OP4 E00D87 0 +OP4 E00D88 0 +OP4 E00D89 0 +OP4 E00D8A 0 +OP4 E00D8B 0 +OP4 E00D8C 0 +OP4 E00D8D 0 +OP4 E00D8E 0 +OP4 E00D8F 0 +OP4 E00D90 0 +OP4 E00D91 0 +OP4 E00D92 0 +OP4 E00D93 0 +OP4 E00D94 0 +OP4 E00D95 0 +OP4 E00D96 0 +OP4 E00D97 0 +OP4 E00D98 0 +OP4 E00D99 0 +OP4 E00D9A 0 +OP4 E00D9B 0 +OP4 E00D9C 0 +OP4 E00D9D 0 +OP4 E00D9E 0 +OP4 E00D9F 0 +OP4 E00DA0 0 +OP4 E00DA1 0 +OP4 E00DA2 0 +OP4 E00DA3 0 +OP4 E00DA4 0 +OP4 E00DA5 0 +OP4 E00DA6 0 +OP4 E00DA7 0 +OP4 E00DA8 0 +OP4 E00DA9 0 +OP4 E00DAA 0 +OP4 E00DAB 0 +OP4 E00DAC 0 +OP4 E00DAD 0 +OP4 E00DAE 0 +OP4 E00DAF 0 +OP4 E00DB0 0 +OP4 E00DB1 0 +OP4 E00DB2 0 +OP4 E00DB3 0 +OP4 E00DB4 0 +OP4 E00DB5 0 +OP4 E00DB6 0 +OP4 E00DB7 0 +OP4 E00DB8 0 +OP4 E00DB9 0 +OP4 E00DBA 0 +OP4 E00DBB 0 +OP4 E00DBC 0 +OP4 E00DBD 0 +OP4 E00DBE 0 +OP4 E00DBF 0 +OP4 E00DC0 0 +OP4 E00DC1 0 +OP4 E00DC2 0 +OP4 E00DC3 0 +OP4 E00DC4 0 +OP4 E00DC5 0 +OP4 E00DC6 0 +OP4 E00DC7 0 +OP4 E00DC8 0 +OP4 E00DC9 0 +OP4 E00DCA 0 +OP4 E00DCB 0 +OP4 E00DCC 0 +OP4 E00DCD 0 +OP4 E00DCE 0 +OP4 E00DCF 0 +OP4 E00DD0 0 +OP4 E00DD1 0 +OP4 E00DD2 0 +OP4 E00DD3 0 +OP4 E00DD4 0 +OP4 E00DD5 0 +OP4 E00DD6 0 +OP4 E00DD7 0 +OP4 E00DD8 0 +OP4 E00DD9 0 +OP4 E00DDA 0 +OP4 E00DDB 0 +OP4 E00DDC 0 +OP4 E00DDD 0 +OP4 E00DDE 0 +OP4 E00DDF 0 +OP4 E00DE0 0 +OP4 E00DE1 0 +OP4 E00DE2 0 +OP4 E00DE3 0 +OP4 E00DE4 0 +OP4 E00DE5 0 +OP4 E00DE6 0 +OP4 E00DE7 0 +OP4 E00DE8 0 +OP4 E00DE9 0 +OP4 E00DEA 0 +OP4 E00DEB 0 +OP4 E00DEC 0 +OP4 E00DED 0 +OP4 E00DEE 0 +OP4 E00DEF 0 +OP4 E00DF0 0 +OP4 E00DF1 0 +OP4 E00DF2 0 +OP4 E00DF3 0 +OP4 E00DF4 0 +OP4 E00DF5 0 +OP4 E00DF6 0 +OP4 E00DF7 0 +OP4 E00DF8 0 +OP4 E00DF9 0 +OP4 E00DFA 0 +OP4 E00DFB 0 +OP4 E00DFC 0 +OP4 E00DFD 0 +OP4 E00DFE 0 +OP4 E00DFF 0 +OP4 E00E00 0 +OP4 E00E01 0 +OP4 E00E02 0 +OP4 E00E03 0 +OP4 E00E04 0 +OP4 E00E05 0 +OP4 E00E06 0 +OP4 E00E07 0 +OP4 E00E08 0 +OP4 E00E09 0 +OP4 E00E0A 0 +OP4 E00E0B 0 +OP4 E00E0C 0 +OP4 E00E0D 0 +OP4 E00E0E 0 +OP4 E00E0F 0 +OP4 E00E10 0 +OP4 E00E11 0 +OP4 E00E12 0 +OP4 E00E13 0 +OP4 E00E14 0 +OP4 E00E15 0 +OP4 E00E16 0 +OP4 E00E17 0 +OP4 E00E18 0 +OP4 E00E19 0 +OP4 E00E1A 0 +OP4 E00E1B 0 +OP4 E00E1C 0 +OP4 E00E1D 0 +OP4 E00E1E 0 +OP4 E00E1F 0 +OP4 E00E20 0 +OP4 E00E21 0 +OP4 E00E22 0 +OP4 E00E23 0 +OP4 E00E24 0 +OP4 E00E25 0 +OP4 E00E26 0 +OP4 E00E27 0 +OP4 E00E28 0 +OP4 E00E29 0 +OP4 E00E2A 0 +OP4 E00E2B 0 +OP4 E00E2C 0 +OP4 E00E2D 0 +OP4 E00E2E 0 +OP4 E00E2F 0 +OP4 E00E30 0 +OP4 E00E31 0 +OP4 E00E32 0 +OP4 E00E33 0 +OP4 E00E34 0 +OP4 E00E35 0 +OP4 E00E36 0 +OP4 E00E37 0 +OP4 E00E38 0 +OP4 E00E39 0 +OP4 E00E3A 0 +OP4 E00E3B 0 +OP4 E00E3C 0 +OP4 E00E3D 0 +OP4 E00E3E 0 +OP4 E00E3F 0 +OP4 E00E40 0 +OP4 E00E41 0 +OP4 E00E42 0 +OP4 E00E43 0 +OP4 E00E44 0 +OP4 E00E45 0 +OP4 E00E46 0 +OP4 E00E47 0 +OP4 E00E48 0 +OP4 E00E49 0 +OP4 E00E4A 0 +OP4 E00E4B 0 +OP4 E00E4C 0 +OP4 E00E4D 0 +OP4 E00E4E 0 +OP4 E00E4F 0 +OP4 E00E50 0 +OP4 E00E51 0 +OP4 E00E52 0 +OP4 E00E53 0 +OP4 E00E54 0 +OP4 E00E55 0 +OP4 E00E56 0 +OP4 E00E57 0 +OP4 E00E58 0 +OP4 E00E59 0 +OP4 E00E5A 0 +OP4 E00E5B 0 +OP4 E00E5C 0 +OP4 E00E5D 0 +OP4 E00E5E 0 +OP4 E00E5F 0 +OP4 E00E60 0 +OP4 E00E61 0 +OP4 E00E62 0 +OP4 E00E63 0 +OP4 E00E64 0 +OP4 E00E65 0 +OP4 E00E66 0 +OP4 E00E67 0 +OP4 E00E68 0 +OP4 E00E69 0 +OP4 E00E6A 0 +OP4 E00E6B 0 +OP4 E00E6C 0 +OP4 E00E6D 0 +OP4 E00E6E 0 +OP4 E00E6F 0 +OP4 E00E70 0 +OP4 E00E71 0 +OP4 E00E72 0 +OP4 E00E73 0 +OP4 E00E74 0 +OP4 E00E75 0 +OP4 E00E76 0 +OP4 E00E77 0 +OP4 E00E78 0 +OP4 E00E79 0 +OP4 E00E7A 0 +OP4 E00E7B 0 +OP4 E00E7C 0 +OP4 E00E7D 0 +OP4 E00E7E 0 +OP4 E00E7F 0 +OP4 E00E80 0 +OP4 E00E81 0 +OP4 E00E82 0 +OP4 E00E83 0 +OP4 E00E84 0 +OP4 E00E85 0 +OP4 E00E86 0 +OP4 E00E87 0 +OP4 E00E88 0 +OP4 E00E89 0 +OP4 E00E8A 0 +OP4 E00E8B 0 +OP4 E00E8C 0 +OP4 E00E8D 0 +OP4 E00E8E 0 +OP4 E00E8F 0 +OP4 E00E90 0 +OP4 E00E91 0 +OP4 E00E92 0 +OP4 E00E93 0 +OP4 E00E94 0 +OP4 E00E95 0 +OP4 E00E96 0 +OP4 E00E97 0 +OP4 E00E98 0 +OP4 E00E99 0 +OP4 E00E9A 0 +OP4 E00E9B 0 +OP4 E00E9C 0 +OP4 E00E9D 0 +OP4 E00E9E 0 +OP4 E00E9F 0 +OP4 E00EA0 0 +OP4 E00EA1 0 +OP4 E00EA2 0 +OP4 E00EA3 0 +OP4 E00EA4 0 +OP4 E00EA5 0 +OP4 E00EA6 0 +OP4 E00EA7 0 +OP4 E00EA8 0 +OP4 E00EA9 0 +OP4 E00EAA 0 +OP4 E00EAB 0 +OP4 E00EAC 0 +OP4 E00EAD 0 +OP4 E00EAE 0 +OP4 E00EAF 0 +OP4 E00EB0 0 +OP4 E00EB1 0 +OP4 E00EB2 0 +OP4 E00EB3 0 +OP4 E00EB4 0 +OP4 E00EB5 0 +OP4 E00EB6 0 +OP4 E00EB7 0 +OP4 E00EB8 0 +OP4 E00EB9 0 +OP4 E00EBA 0 +OP4 E00EBB 0 +OP4 E00EBC 0 +OP4 E00EBD 0 +OP4 E00EBE 0 +OP4 E00EBF 0 +OP4 E00EC0 0 +OP4 E00EC1 0 +OP4 E00EC2 0 +OP4 E00EC3 0 +OP4 E00EC4 0 +OP4 E00EC5 0 +OP4 E00EC6 0 +OP4 E00EC7 0 +OP4 E00EC8 0 +OP4 E00EC9 0 +OP4 E00ECA 0 +OP4 E00ECB 0 +OP4 E00ECC 0 +OP4 E00ECD 0 +OP4 E00ECE 0 +OP4 E00ECF 0 +OP4 E00ED0 0 +OP4 E00ED1 0 +OP4 E00ED2 0 +OP4 E00ED3 0 +OP4 E00ED4 0 +OP4 E00ED5 0 +OP4 E00ED6 0 +OP4 E00ED7 0 +OP4 E00ED8 0 +OP4 E00ED9 0 +OP4 E00EDA 0 +OP4 E00EDB 0 +OP4 E00EDC 0 +OP4 E00EDD 0 +OP4 E00EDE 0 +OP4 E00EDF 0 +OP4 E00EE0 0 +OP4 E00EE1 0 +OP4 E00EE2 0 +OP4 E00EE3 0 +OP4 E00EE4 0 +OP4 E00EE5 0 +OP4 E00EE6 0 +OP4 E00EE7 0 +OP4 E00EE8 0 +OP4 E00EE9 0 +OP4 E00EEA 0 +OP4 E00EEB 0 +OP4 E00EEC 0 +OP4 E00EED 0 +OP4 E00EEE 0 +OP4 E00EEF 0 +OP4 E00EF0 0 +OP4 E00EF1 0 +OP4 E00EF2 0 +OP4 E00EF3 0 +OP4 E00EF4 0 +OP4 E00EF5 0 +OP4 E00EF6 0 +OP4 E00EF7 0 +OP4 E00EF8 0 +OP4 E00EF9 0 +OP4 E00EFA 0 +OP4 E00EFB 0 +OP4 E00EFC 0 +OP4 E00EFD 0 +OP4 E00EFE 0 +OP4 E00EFF 0 +OP4 E00F00 0 +OP4 E00F01 0 +OP4 E00F02 0 +OP4 E00F03 0 +OP4 E00F04 0 +OP4 E00F05 0 +OP4 E00F06 0 +OP4 E00F07 0 +OP4 E00F08 0 +OP4 E00F09 0 +OP4 E00F0A 0 +OP4 E00F0B 0 +OP4 E00F0C 0 +OP4 E00F0D 0 +OP4 E00F0E 0 +OP4 E00F0F 0 +OP4 E00F10 0 +OP4 E00F11 0 +OP4 E00F12 0 +OP4 E00F13 0 +OP4 E00F14 0 +OP4 E00F15 0 +OP4 E00F16 0 +OP4 E00F17 0 +OP4 E00F18 0 +OP4 E00F19 0 +OP4 E00F1A 0 +OP4 E00F1B 0 +OP4 E00F1C 0 +OP4 E00F1D 0 +OP4 E00F1E 0 +OP4 E00F1F 0 +OP4 E00F20 0 +OP4 E00F21 0 +OP4 E00F22 0 +OP4 E00F23 0 +OP4 E00F24 0 +OP4 E00F25 0 +OP4 E00F26 0 +OP4 E00F27 0 +OP4 E00F28 0 +OP4 E00F29 0 +OP4 E00F2A 0 +OP4 E00F2B 0 +OP4 E00F2C 0 +OP4 E00F2D 0 +OP4 E00F2E 0 +OP4 E00F2F 0 +OP4 E00F30 0 +OP4 E00F31 0 +OP4 E00F32 0 +OP4 E00F33 0 +OP4 E00F34 0 +OP4 E00F35 0 +OP4 E00F36 0 +OP4 E00F37 0 +OP4 E00F38 0 +OP4 E00F39 0 +OP4 E00F3A 0 +OP4 E00F3B 0 +OP4 E00F3C 0 +OP4 E00F3D 0 +OP4 E00F3E 0 +OP4 E00F3F 0 +OP4 E00F40 0 +OP4 E00F41 0 +OP4 E00F42 0 +OP4 E00F43 0 +OP4 E00F44 0 +OP4 E00F45 0 +OP4 E00F46 0 +OP4 E00F47 0 +OP4 E00F48 0 +OP4 E00F49 0 +OP4 E00F4A 0 +OP4 E00F4B 0 +OP4 E00F4C 0 +OP4 E00F4D 0 +OP4 E00F4E 0 +OP4 E00F4F 0 +OP4 E00F50 0 +OP4 E00F51 0 +OP4 E00F52 0 +OP4 E00F53 0 +OP4 E00F54 0 +OP4 E00F55 0 +OP4 E00F56 0 +OP4 E00F57 0 +OP4 E00F58 0 +OP4 E00F59 0 +OP4 E00F5A 0 +OP4 E00F5B 0 +OP4 E00F5C 0 +OP4 E00F5D 0 +OP4 E00F5E 0 +OP4 E00F5F 0 +OP4 E00F60 0 +OP4 E00F61 0 +OP4 E00F62 0 +OP4 E00F63 0 +OP4 E00F64 0 +OP4 E00F65 0 +OP4 E00F66 0 +OP4 E00F67 0 +OP4 E00F68 0 +OP4 E00F69 0 +OP4 E00F6A 0 +OP4 E00F6B 0 +OP4 E00F6C 0 +OP4 E00F6D 0 +OP4 E00F6E 0 +OP4 E00F6F 0 +OP4 E00F70 0 +OP4 E00F71 0 +OP4 E00F72 0 +OP4 E00F73 0 +OP4 E00F74 0 +OP4 E00F75 0 +OP4 E00F76 0 +OP4 E00F77 0 +OP4 E00F78 0 +OP4 E00F79 0 +OP4 E00F7A 0 +OP4 E00F7B 0 +OP4 E00F7C 0 +OP4 E00F7D 0 +OP4 E00F7E 0 +OP4 E00F7F 0 +OP4 E00F80 0 +OP4 E00F81 0 +OP4 E00F82 0 +OP4 E00F83 0 +OP4 E00F84 0 +OP4 E00F85 0 +OP4 E00F86 0 +OP4 E00F87 0 +OP4 E00F88 0 +OP4 E00F89 0 +OP4 E00F8A 0 +OP4 E00F8B 0 +OP4 E00F8C 0 +OP4 E00F8D 0 +OP4 E00F8E 0 +OP4 E00F8F 0 +OP4 E00F90 0 +OP4 E00F91 0 +OP4 E00F92 0 +OP4 E00F93 0 +OP4 E00F94 0 +OP4 E00F95 0 +OP4 E00F96 0 +OP4 E00F97 0 +OP4 E00F98 0 +OP4 E00F99 0 +OP4 E00F9A 0 +OP4 E00F9B 0 +OP4 E00F9C 0 +OP4 E00F9D 0 +OP4 E00F9E 0 +OP4 E00F9F 0 +OP4 E00FA0 0 +OP4 E00FA1 0 +OP4 E00FA2 0 +OP4 E00FA3 0 +OP4 E00FA4 0 +OP4 E00FA5 0 +OP4 E00FA6 0 +OP4 E00FA7 0 +OP4 E00FA8 0 +OP4 E00FA9 0 +OP4 E00FAA 0 +OP4 E00FAB 0 +OP4 E00FAC 0 +OP4 E00FAD 0 +OP4 E00FAE 0 +OP4 E00FAF 0 +OP4 E00FB0 0 +OP4 E00FB1 0 +OP4 E00FB2 0 +OP4 E00FB3 0 +OP4 E00FB4 0 +OP4 E00FB5 0 +OP4 E00FB6 0 +OP4 E00FB7 0 +OP4 E00FB8 0 +OP4 E00FB9 0 +OP4 E00FBA 0 +OP4 E00FBB 0 +OP4 E00FBC 0 +OP4 E00FBD 0 +OP4 E00FBE 0 +OP4 E00FBF 0 +OP4 E00FC0 0 +OP4 E00FC1 0 +OP4 E00FC2 0 +OP4 E00FC3 0 +OP4 E00FC4 0 +OP4 E00FC5 0 +OP4 E00FC6 0 +OP4 E00FC7 0 +OP4 E00FC8 0 +OP4 E00FC9 0 +OP4 E00FCA 0 +OP4 E00FCB 0 +OP4 E00FCC 0 +OP4 E00FCD 0 +OP4 E00FCE 0 +OP4 E00FCF 0 +OP4 E00FD0 0 +OP4 E00FD1 0 +OP4 E00FD2 0 +OP4 E00FD3 0 +OP4 E00FD4 0 +OP4 E00FD5 0 +OP4 E00FD6 0 +OP4 E00FD7 0 +OP4 E00FD8 0 +OP4 E00FD9 0 +OP4 E00FDA 0 +OP4 E00FDB 0 +OP4 E00FDC 0 +OP4 E00FDD 0 +OP4 E00FDE 0 +OP4 E00FDF 0 +OP4 E00FE0 0 +OP4 E00FE1 0 +OP4 E00FE2 0 +OP4 E00FE3 0 +OP4 E00FE4 0 +OP4 E00FE5 0 +OP4 E00FE6 0 +OP4 E00FE7 0 +OP4 E00FE8 0 +OP4 E00FE9 0 +OP4 E00FEA 0 +OP4 E00FEB 0 +OP4 E00FEC 0 +OP4 E00FED 0 +OP4 E00FEE 0 +OP4 E00FEF 0 +OP4 E00FF0 0 +OP4 E00FF1 0 +OP4 E00FF2 0 +OP4 E00FF3 0 +OP4 E00FF4 0 +OP4 E00FF5 0 +OP4 E00FF6 0 +OP4 E00FF7 0 +OP4 E00FF8 0 +OP4 E00FF9 0 +OP4 E00FFA 0 +OP4 E00FFB 0 +OP4 E00FFC 0 +OP4 E00FFD 0 +OP4 E00FFE 0 +OP4 E00FFF 0 +OP4 E01000 0 +OP4 E01001 0 +OP4 E01002 0 +OP4 E01003 0 +OP4 E01004 0 +OP4 E01005 0 +OP4 E01006 0 +OP4 E01007 0 +OP4 E01008 0 +OP4 E01009 0 +OP4 E0100A 0 +OP4 E0100B 0 +OP4 E0100C 0 +OP4 E0100D 0 +OP4 E0100E 0 +OP4 E0100F 0 +OP4 E01010 0 +OP4 E01011 0 +OP4 E01012 0 +OP4 E01013 0 +OP4 E01014 0 +OP4 E01015 0 +OP4 E01016 0 +OP4 E01017 0 +OP4 E01018 0 +OP4 E01019 0 +OP4 E0101A 0 +OP4 E0101B 0 +OP4 E0101C 0 +OP4 E0101D 0 +OP4 E0101E 0 +OP4 E0101F 0 +OP4 E01020 0 +OP4 E01021 0 +OP4 E01022 0 +OP4 E01023 0 +OP4 E01024 0 +OP4 E01025 0 +OP4 E01026 0 +OP4 E01027 0 +OP4 E01028 0 +OP4 E01029 0 +OP4 E0102A 0 +OP4 E0102B 0 +OP4 E0102C 0 +OP4 E0102D 0 +OP4 E0102E 0 +OP4 E0102F 0 +OP4 E01030 0 +OP4 E01031 0 +OP4 E01032 0 +OP4 E01033 0 +OP4 E01034 0 +OP4 E01035 0 +OP4 E01036 0 +OP4 E01037 0 +OP4 E01038 0 +OP4 E01039 0 +OP4 E0103A 0 +OP4 E0103B 0 +OP4 E0103C 0 +OP4 E0103D 0 +OP4 E0103E 0 +OP4 E0103F 0 +OP4 E01040 0 +OP4 E01041 0 +OP4 E01042 0 +OP4 E01043 0 +OP4 E01044 0 +OP4 E01045 0 +OP4 E01046 0 +OP4 E01047 0 +OP4 E01048 0 +OP4 E01049 0 +OP4 E0104A 0 +OP4 E0104B 0 +OP4 E0104C 0 +OP4 E0104D 0 +OP4 E0104E 0 +OP4 E0104F 0 +OP4 E01050 0 +OP4 E01051 0 +OP4 E01052 0 +OP4 E01053 0 +OP4 E01054 0 +OP4 E01055 0 +OP4 E01056 0 +OP4 E01057 0 +OP4 E01058 0 +OP4 E01059 0 +OP4 E0105A 0 +OP4 E0105B 0 +OP4 E0105C 0 +OP4 E0105D 0 +OP4 E0105E 0 +OP4 E0105F 0 +OP4 E01060 0 +OP4 E01061 0 +OP4 E01062 0 +OP4 E01063 0 +OP4 E01064 0 +OP4 E01065 0 +OP4 E01066 0 +OP4 E01067 0 +OP4 E01068 0 +OP4 E01069 0 +OP4 E0106A 0 +OP4 E0106B 0 +OP4 E0106C 0 +OP4 E0106D 0 +OP4 E0106E 0 +OP4 E0106F 0 +OP4 E01070 0 +OP4 E01071 0 +OP4 E01072 0 +OP4 E01073 0 +OP4 E01074 0 +OP4 E01075 0 +OP4 E01076 0 +OP4 E01077 0 +OP4 E01078 0 +OP4 E01079 0 +OP4 E0107A 0 +OP4 E0107B 0 +OP4 E0107C 0 +OP4 E0107D 0 +OP4 E0107E 0 +OP4 E0107F 0 +OP4 E01080 0 +OP4 E01081 0 +OP4 E01082 0 +OP4 E01083 0 +OP4 E01084 0 +OP4 E01085 0 +OP4 E01086 0 +OP4 E01087 0 +OP4 E01088 0 +OP4 E01089 0 +OP4 E0108A 0 +OP4 E0108B 0 +OP4 E0108C 0 +OP4 E0108D 0 +OP4 E0108E 0 +OP4 E0108F 0 +OP4 E01090 0 +OP4 E01091 0 +OP4 E01092 0 +OP4 E01093 0 +OP4 E01094 0 +OP4 E01095 0 +OP4 E01096 0 +OP4 E01097 0 +OP4 E01098 0 +OP4 E01099 0 +OP4 E0109A 0 +OP4 E0109B 0 +OP4 E0109C 0 +OP4 E0109D 0 +OP4 E0109E 0 +OP4 E0109F 0 +OP4 E010A0 0 +OP4 E010A1 0 +OP4 E010A2 0 +OP4 E010A3 0 +OP4 E010A4 0 +OP4 E010A5 0 +OP4 E010A6 0 +OP4 E010A7 0 +OP4 E010A8 0 +OP4 E010A9 0 +OP4 E010AA 0 +OP4 E010AB 0 +OP4 E010AC 0 +OP4 E010AD 0 +OP4 E010AE 0 +OP4 E010AF 0 +OP4 E010B0 0 +OP4 E010B1 0 +OP4 E010B2 0 +OP4 E010B3 0 +OP4 E010B4 0 +OP4 E010B5 0 +OP4 E010B6 0 +OP4 E010B7 0 +OP4 E010B8 0 +OP4 E010B9 0 +OP4 E010BA 0 +OP4 E010BB 0 +OP4 E010BC 0 +OP4 E010BD 0 +OP4 E010BE 0 +OP4 E010BF 0 +OP4 E010C0 0 +OP4 E010C1 0 +OP4 E010C2 0 +OP4 E010C3 0 +OP4 E010C4 0 +OP4 E010C5 0 +OP4 E010C6 0 +OP4 E010C7 0 +OP4 E010C8 0 +OP4 E010C9 0 +OP4 E010CA 0 +OP4 E010CB 0 +OP4 E010CC 0 +OP4 E010CD 0 +OP4 E010CE 0 +OP4 E010CF 0 +OP4 E010D0 0 +OP4 E010D1 0 +OP4 E010D2 0 +OP4 E010D3 0 +OP4 E010D4 0 +OP4 E010D5 0 +OP4 E010D6 0 +OP4 E010D7 0 +OP4 E010D8 0 +OP4 E010D9 0 +OP4 E010DA 0 +OP4 E010DB 0 +OP4 E010DC 0 +OP4 E010DD 0 +OP4 E010DE 0 +OP4 E010DF 0 +OP4 E010E0 0 +OP4 E010E1 0 +OP4 E010E2 0 +OP4 E010E3 0 +OP4 E010E4 0 +OP4 E010E5 0 +OP4 E010E6 0 +OP4 E010E7 0 +OP4 E010E8 0 +OP4 E010E9 0 +OP4 E010EA 0 +OP4 E010EB 0 +OP4 E010EC 0 +OP4 E010ED 0 +OP4 E010EE 0 +OP4 E010EF 0 +OP4 E010F0 0 +OP4 E010F1 0 +OP4 E010F2 0 +OP4 E010F3 0 +OP4 E010F4 0 +OP4 E010F5 0 +OP4 E010F6 0 +OP4 E010F7 0 +OP4 E010F8 0 +OP4 E010F9 0 +OP4 E010FA 0 +OP4 E010FB 0 +OP4 E010FC 0 +OP4 E010FD 0 +OP4 E010FE 0 +OP4 E010FF 0 +OP4 E01100 0 +OP4 E01101 0 +OP4 E01102 0 +OP4 E01103 0 +OP4 E01104 0 +OP4 E01105 0 +OP4 E01106 0 +OP4 E01107 0 +OP4 E01108 0 +OP4 E01109 0 +OP4 E0110A 0 +OP4 E0110B 0 +OP4 E0110C 0 +OP4 E0110D 0 +OP4 E0110E 0 +OP4 E0110F 0 +OP4 E01110 0 +OP4 E01111 0 +OP4 E01112 0 +OP4 E01113 0 +OP4 E01114 0 +OP4 E01115 0 +OP4 E01116 0 +OP4 E01117 0 +OP4 E01118 0 +OP4 E01119 0 +OP4 E0111A 0 +OP4 E0111B 0 +OP4 E0111C 0 +OP4 E0111D 0 +OP4 E0111E 0 +OP4 E0111F 0 +OP4 E01120 0 +OP4 E01121 0 +OP4 E01122 0 +OP4 E01123 0 +OP4 E01124 0 +OP4 E01125 0 +OP4 E01126 0 +OP4 E01127 0 +OP4 E01128 0 +OP4 E01129 0 +OP4 E0112A 0 +OP4 E0112B 0 +OP4 E0112C 0 +OP4 E0112D 0 +OP4 E0112E 0 +OP4 E0112F 0 +OP4 E01130 0 +OP4 E01131 0 +OP4 E01132 0 +OP4 E01133 0 +OP4 E01134 0 +OP4 E01135 0 +OP4 E01136 0 +OP4 E01137 0 +OP4 E01138 0 +OP4 E01139 0 +OP4 E0113A 0 +OP4 E0113B 0 +OP4 E0113C 0 +OP4 E0113D 0 +OP4 E0113E 0 +OP4 E0113F 0 +OP4 E01140 0 +OP4 E01141 0 +OP4 E01142 0 +OP4 E01143 0 +OP4 E01144 0 +OP4 E01145 0 +OP4 E01146 0 +OP4 E01147 0 +OP4 E01148 0 +OP4 E01149 0 +OP4 E0114A 0 +OP4 E0114B 0 +OP4 E0114C 0 +OP4 E0114D 0 +OP4 E0114E 0 +OP4 E0114F 0 +OP4 E01150 0 +OP4 E01151 0 +OP4 E01152 0 +OP4 E01153 0 +OP4 E01154 0 +OP4 E01155 0 +OP4 E01156 0 +OP4 E01157 0 +OP4 E01158 0 +OP4 E01159 0 +OP4 E0115A 0 +OP4 E0115B 0 +OP4 E0115C 0 +OP4 E0115D 0 +OP4 E0115E 0 +OP4 E0115F 0 +OP4 E01160 0 +OP4 E01161 0 +OP4 E01162 0 +OP4 E01163 0 +OP4 E01164 0 +OP4 E01165 0 +OP4 E01166 0 +OP4 E01167 0 +OP4 E01168 0 +OP4 E01169 0 +OP4 E0116A 0 +OP4 E0116B 0 +OP4 E0116C 0 +OP4 E0116D 0 +OP4 E0116E 0 +OP4 E0116F 0 +OP4 E01170 0 +OP4 E01171 0 +OP4 E01172 0 +OP4 E01173 0 +OP4 E01174 0 +OP4 E01175 0 +OP4 E01176 0 +OP4 E01177 0 +OP4 E01178 0 +OP4 E01179 0 +OP4 E0117A 0 +OP4 E0117B 0 +OP4 E0117C 0 +OP4 E0117D 0 +OP4 E0117E 0 +OP4 E0117F 0 +OP4 E01180 0 +OP4 E01181 0 +OP4 E01182 0 +OP4 E01183 0 +OP4 E01184 0 +OP4 E01185 0 +OP4 E01186 0 +OP4 E01187 0 +OP4 E01188 0 +OP4 E01189 0 +OP4 E0118A 0 +OP4 E0118B 0 +OP4 E0118C 0 +OP4 E0118D 0 +OP4 E0118E 0 +OP4 E0118F 0 +OP4 E01190 0 +OP4 E01191 0 +OP4 E01192 0 +OP4 E01193 0 +OP4 E01194 0 +OP4 E01195 0 +OP4 E01196 0 +OP4 E01197 0 +OP4 E01198 0 +OP4 E01199 0 +OP4 E0119A 0 +OP4 E0119B 0 +OP4 E0119C 0 +OP4 E0119D 0 +OP4 E0119E 0 +OP4 E0119F 0 +OP4 E011A0 0 +OP4 E011A1 0 +OP4 E011A2 0 +OP4 E011A3 0 +OP4 E011A4 0 +OP4 E011A5 0 +OP4 E011A6 0 +OP4 E011A7 0 +OP4 E011A8 0 +OP4 E011A9 0 +OP4 E011AA 0 +OP4 E011AB 0 +OP4 E011AC 0 +OP4 E011AD 0 +OP4 E011AE 0 +OP4 E011AF 0 +OP4 E011B0 0 +OP4 E011B1 0 +OP4 E011B2 0 +OP4 E011B3 0 +OP4 E011B4 0 +OP4 E011B5 0 +OP4 E011B6 0 +OP4 E011B7 0 +OP4 E011B8 0 +OP4 E011B9 0 +OP4 E011BA 0 +OP4 E011BB 0 +OP4 E011BC 0 +OP4 E011BD 0 +OP4 E011BE 0 +OP4 E011BF 0 +OP4 E011C0 0 +OP4 E011C1 0 +OP4 E011C2 0 +OP4 E011C3 0 +OP4 E011C4 0 +OP4 E011C5 0 +OP4 E011C6 0 +OP4 E011C7 0 +OP4 E011C8 0 +OP4 E011C9 0 +OP4 E011CA 0 +OP4 E011CB 0 +OP4 E011CC 0 +OP4 E011CD 0 +OP4 E011CE 0 +OP4 E011CF 0 +OP4 E011D0 0 +OP4 E011D1 0 +OP4 E011D2 0 +OP4 E011D3 0 +OP4 E011D4 0 +OP4 E011D5 0 +OP4 E011D6 0 +OP4 E011D7 0 +OP4 E011D8 0 +OP4 E011D9 0 +OP4 E011DA 0 +OP4 E011DB 0 +OP4 E011DC 0 +OP4 E011DD 0 +OP4 E011DE 0 +OP4 E011DF 0 +OP4 E011E0 0 +OP4 E011E1 0 +OP4 E011E2 0 +OP4 E011E3 0 +OP4 E011E4 0 +OP4 E011E5 0 +OP4 E011E6 0 +OP4 E011E7 0 +OP4 E011E8 0 +OP4 E011E9 0 +OP4 E011EA 0 +OP4 E011EB 0 +OP4 E011EC 0 +OP4 E011ED 0 +OP4 E011EE 0 +OP4 E011EF 0 +OP4 E011F0 0 +OP4 E011F1 0 +OP4 E011F2 0 +OP4 E011F3 0 +OP4 E011F4 0 +OP4 E011F5 0 +OP4 E011F6 0 +OP4 E011F7 0 +OP4 E011F8 0 +OP4 E011F9 0 +OP4 E011FA 0 +OP4 E011FB 0 +OP4 E011FC 0 +OP4 E011FD 0 +OP4 E011FE 0 +OP4 E011FF 0 +OP4 E01200 0 +OP4 E01201 0 +OP4 E01202 0 +OP4 E01203 0 +OP4 E01204 0 +OP4 E01205 0 +OP4 E01206 0 +OP4 E01207 0 +OP4 E01208 0 +OP4 E01209 0 +OP4 E0120A 0 +OP4 E0120B 0 +OP4 E0120C 0 +OP4 E0120D 0 +OP4 E0120E 0 +OP4 E0120F 0 +OP4 E01210 0 +OP4 E01211 0 +OP4 E01212 0 +OP4 E01213 0 +OP4 E01214 0 +OP4 E01215 0 +OP4 E01216 0 +OP4 E01217 0 +OP4 E01218 0 +OP4 E01219 0 +OP4 E0121A 0 +OP4 E0121B 0 +OP4 E0121C 0 +OP4 E0121D 0 +OP4 E0121E 0 +OP4 E0121F 0 +OP4 E01220 0 +OP4 E01221 0 +OP4 E01222 0 +OP4 E01223 0 +OP4 E01224 0 +OP4 E01225 0 +OP4 E01226 0 +OP4 E01227 0 +OP4 E01228 0 +OP4 E01229 0 +OP4 E0122A 0 +OP4 E0122B 0 +OP4 E0122C 0 +OP4 E0122D 0 +OP4 E0122E 0 +OP4 E0122F 0 +OP4 E01230 0 +OP4 E01231 0 +OP4 E01232 0 +OP4 E01233 0 +OP4 E01234 0 +OP4 E01235 0 +OP4 E01236 0 +OP4 E01237 0 +OP4 E01238 0 +OP4 E01239 0 +OP4 E0123A 0 +OP4 E0123B 0 +OP4 E0123C 0 +OP4 E0123D 0 +OP4 E0123E 0 +OP4 E0123F 0 +OP4 E01240 0 +OP4 E01241 0 +OP4 E01242 0 +OP4 E01243 0 +OP4 E01244 0 +OP4 E01245 0 +OP4 E01246 0 +OP4 E01247 0 +OP4 E01248 0 +OP4 E01249 0 +OP4 E0124A 0 +OP4 E0124B 0 +OP4 E0124C 0 +OP4 E0124D 0 +OP4 E0124E 0 +OP4 E0124F 0 +OP4 E01250 0 +OP4 E01251 0 +OP4 E01252 0 +OP4 E01253 0 +OP4 E01254 0 +OP4 E01255 0 +OP4 E01256 0 +OP4 E01257 0 +OP4 E01258 0 +OP4 E01259 0 +OP4 E0125A 0 +OP4 E0125B 0 +OP4 E0125C 0 +OP4 E0125D 0 +OP4 E0125E 0 +OP4 E0125F 0 +OP4 E01260 0 +OP4 E01261 0 +OP4 E01262 0 +OP4 E01263 0 +OP4 E01264 0 +OP4 E01265 0 +OP4 E01266 0 +OP4 E01267 0 +OP4 E01268 0 +OP4 E01269 0 +OP4 E0126A 0 +OP4 E0126B 0 +OP4 E0126C 0 +OP4 E0126D 0 +OP4 E0126E 0 +OP4 E0126F 0 +OP4 E01270 0 +OP4 E01271 0 +OP4 E01272 0 +OP4 E01273 0 +OP4 E01274 0 +OP4 E01275 0 +OP4 E01276 0 +OP4 E01277 0 +OP4 E01278 0 +OP4 E01279 0 +OP4 E0127A 0 +OP4 E0127B 0 +OP4 E0127C 0 +OP4 E0127D 0 +OP4 E0127E 0 +OP4 E0127F 0 +OP4 E01280 0 +OP4 E01281 0 +OP4 E01282 0 +OP4 E01283 0 +OP4 E01284 0 +OP4 E01285 0 +OP4 E01286 0 +OP4 E01287 0 +OP4 E01288 0 +OP4 E01289 0 +OP4 E0128A 0 +OP4 E0128B 0 +OP4 E0128C 0 +OP4 E0128D 0 +OP4 E0128E 0 +OP4 E0128F 0 +OP4 E01290 0 +OP4 E01291 0 +OP4 E01292 0 +OP4 E01293 0 +OP4 E01294 0 +OP4 E01295 0 +OP4 E01296 0 +OP4 E01297 0 +OP4 E01298 0 +OP4 E01299 0 +OP4 E0129A 0 +OP4 E0129B 0 +OP4 E0129C 0 +OP4 E0129D 0 +OP4 E0129E 0 +OP4 E0129F 0 +OP4 E012A0 0 +OP4 E012A1 0 +OP4 E012A2 0 +OP4 E012A3 0 +OP4 E012A4 0 +OP4 E012A5 0 +OP4 E012A6 0 +OP4 E012A7 0 +OP4 E012A8 0 +OP4 E012A9 0 +OP4 E012AA 0 +OP4 E012AB 0 +OP4 E012AC 0 +OP4 E012AD 0 +OP4 E012AE 0 +OP4 E012AF 0 +OP4 E012B0 0 +OP4 E012B1 0 +OP4 E012B2 0 +OP4 E012B3 0 +OP4 E012B4 0 +OP4 E012B5 0 +OP4 E012B6 0 +OP4 E012B7 0 +OP4 E012B8 0 +OP4 E012B9 0 +OP4 E012BA 0 +OP4 E012BB 0 +OP4 E012BC 0 +OP4 E012BD 0 +OP4 E012BE 0 +OP4 E012BF 0 +OP4 E012C0 0 +OP4 E012C1 0 +OP4 E012C2 0 +OP4 E012C3 0 +OP4 E012C4 0 +OP4 E012C5 0 +OP4 E012C6 0 +OP4 E012C7 0 +OP4 E012C8 0 +OP4 E012C9 0 +OP4 E012CA 0 +OP4 E012CB 0 +OP4 E012CC 0 +OP4 E012CD 0 +OP4 E012CE 0 +OP4 E012CF 0 +OP4 E012D0 0 +OP4 E012D1 0 +OP4 E012D2 0 +OP4 E012D3 0 +OP4 E012D4 0 +OP4 E012D5 0 +OP4 E012D6 0 +OP4 E012D7 0 +OP4 E012D8 0 +OP4 E012D9 0 +OP4 E012DA 0 +OP4 E012DB 0 +OP4 E012DC 0 +OP4 E012DD 0 +OP4 E012DE 0 +OP4 E012DF 0 +OP4 E012E0 0 +OP4 E012E1 0 +OP4 E012E2 0 +OP4 E012E3 0 +OP4 E012E4 0 +OP4 E012E5 0 +OP4 E012E6 0 +OP4 E012E7 0 +OP4 E012E8 0 +OP4 E012E9 0 +OP4 E012EA 0 +OP4 E012EB 0 +OP4 E012EC 0 +OP4 E012ED 0 +OP4 E012EE 0 +OP4 E012EF 0 +OP4 E012F0 0 +OP4 E012F1 0 +OP4 E012F2 0 +OP4 E012F3 0 +OP4 E012F4 0 +OP4 E012F5 0 +OP4 E012F6 0 +OP4 E012F7 0 +OP4 E012F8 0 +OP4 E012F9 0 +OP4 E012FA 0 +OP4 E012FB 0 +OP4 E012FC 0 +OP4 E012FD 0 +OP4 E012FE 0 +OP4 E012FF 0 +OP4 E01300 0 +OP4 E01301 0 +OP4 E01302 0 +OP4 E01303 0 +OP4 E01304 0 +OP4 E01305 0 +OP4 E01306 0 +OP4 E01307 0 +OP4 E01308 0 +OP4 E01309 0 +OP4 E0130A 0 +OP4 E0130B 0 +OP4 E0130C 0 +OP4 E0130D 0 +OP4 E0130E 0 +OP4 E0130F 0 +OP4 E01310 0 +OP4 E01311 0 +OP4 E01312 0 +OP4 E01313 0 +OP4 E01314 0 +OP4 E01315 0 +OP4 E01316 0 +OP4 E01317 0 +OP4 E01318 0 +OP4 E01319 0 +OP4 E0131A 0 +OP4 E0131B 0 +OP4 E0131C 0 +OP4 E0131D 0 +OP4 E0131E 0 +OP4 E0131F 0 +OP4 E01320 0 +OP4 E01321 0 +OP4 E01322 0 +OP4 E01323 0 +OP4 E01324 0 +OP4 E01325 0 +OP4 E01326 0 +OP4 E01327 0 +OP4 E01328 0 +OP4 E01329 0 +OP4 E0132A 0 +OP4 E0132B 0 +OP4 E0132C 0 +OP4 E0132D 0 +OP4 E0132E 0 +OP4 E0132F 0 +OP4 E01330 0 +OP4 E01331 0 +OP4 E01332 0 +OP4 E01333 0 +OP4 E01334 0 +OP4 E01335 0 +OP4 E01336 0 +OP4 E01337 0 +OP4 E01338 0 +OP4 E01339 0 +OP4 E0133A 0 +OP4 E0133B 0 +OP4 E0133C 0 +OP4 E0133D 0 +OP4 E0133E 0 +OP4 E0133F 0 +OP4 E01340 0 +OP4 E01341 0 +OP4 E01342 0 +OP4 E01343 0 +OP4 E01344 0 +OP4 E01345 0 +OP4 E01346 0 +OP4 E01347 0 +OP4 E01348 0 +OP4 E01349 0 +OP4 E0134A 0 +OP4 E0134B 0 +OP4 E0134C 0 +OP4 E0134D 0 +OP4 E0134E 0 +OP4 E0134F 0 +OP4 E01350 0 +OP4 E01351 0 +OP4 E01352 0 +OP4 E01353 0 +OP4 E01354 0 +OP4 E01355 0 +OP4 E01356 0 +OP4 E01357 0 +OP4 E01358 0 +OP4 E01359 0 +OP4 E0135A 0 +OP4 E0135B 0 +OP4 E0135C 0 +OP4 E0135D 0 +OP4 E0135E 0 +OP4 E0135F 0 +OP4 E01360 0 +OP4 E01361 0 +OP4 E01362 0 +OP4 E01363 0 +OP4 E01364 0 +OP4 E01365 0 +OP4 E01366 0 +OP4 E01367 0 +OP4 E01368 0 +OP4 E01369 0 +OP4 E0136A 0 +OP4 E0136B 0 +OP4 E0136C 0 +OP4 E0136D 0 +OP4 E0136E 0 +OP4 E0136F 0 +OP4 E01370 0 +OP4 E01371 0 +OP4 E01372 0 +OP4 E01373 0 +OP4 E01374 0 +OP4 E01375 0 +OP4 E01376 0 +OP4 E01377 0 +OP4 E01378 0 +OP4 E01379 0 +OP4 E0137A 0 +OP4 E0137B 0 +OP4 E0137C 0 +OP4 E0137D 0 +OP4 E0137E 0 +OP4 E0137F 0 +OP4 E01380 0 +OP4 E01381 0 +OP4 E01382 0 +OP4 E01383 0 +OP4 E01384 0 +OP4 E01385 0 +OP4 E01386 0 +OP4 E01387 0 +OP4 E01388 0 +OP4 E01389 0 +OP4 E0138A 0 +OP4 E0138B 0 +OP4 E0138C 0 +OP4 E0138D 0 +OP4 E0138E 0 +OP4 E0138F 0 +OP4 E01390 0 +OP4 E01391 0 +OP4 E01392 0 +OP4 E01393 0 +OP4 E01394 0 +OP4 E01395 0 +OP4 E01396 0 +OP4 E01397 0 +OP4 E01398 0 +OP4 E01399 0 +OP4 E0139A 0 +OP4 E0139B 0 +OP4 E0139C 0 +OP4 E0139D 0 +OP4 E0139E 0 +OP4 E0139F 0 +OP4 E013A0 0 +OP4 E013A1 0 +OP4 E013A2 0 +OP4 E013A3 0 +OP4 E013A4 0 +OP4 E013A5 0 +OP4 E013A6 0 +OP4 E013A7 0 +OP4 E013A8 0 +OP4 E013A9 0 +OP4 E013AA 0 +OP4 E013AB 0 +OP4 E013AC 0 +OP4 E013AD 0 +OP4 E013AE 0 +OP4 E013AF 0 +OP4 E013B0 0 +OP4 E013B1 0 +OP4 E013B2 0 +OP4 E013B3 0 +OP4 E013B4 0 +OP4 E013B5 0 +OP4 E013B6 0 +OP4 E013B7 0 +OP4 E013B8 0 +OP4 E013B9 0 +OP4 E013BA 0 +OP4 E013BB 0 +OP4 E013BC 0 +OP4 E013BD 0 +OP4 E013BE 0 +OP4 E013BF 0 +OP4 E013C0 0 +OP4 E013C1 0 +OP4 E013C2 0 +OP4 E013C3 0 +OP4 E013C4 0 +OP4 E013C5 0 +OP4 E013C6 0 +OP4 E013C7 0 +OP4 E013C8 0 +OP4 E013C9 0 +OP4 E013CA 0 +OP4 E013CB 0 +OP4 E013CC 0 +OP4 E013CD 0 +OP4 E013CE 0 +OP4 E013CF 0 +OP4 E013D0 0 +OP4 E013D1 0 +OP4 E013D2 0 +OP4 E013D3 0 +OP4 E013D4 0 +OP4 E013D5 0 +OP4 E013D6 0 +OP4 E013D7 0 +OP4 E013D8 0 +OP4 E013D9 0 +OP4 E013DA 0 +OP4 E013DB 0 +OP4 E013DC 0 +OP4 E013DD 0 +OP4 E013DE 0 +OP4 E013DF 0 +OP4 E013E0 0 +OP4 E013E1 0 +OP4 E013E2 0 +OP4 E013E3 0 +OP4 E013E4 0 +OP4 E013E5 0 +OP4 E013E6 0 +OP4 E013E7 0 +OP4 E013E8 0 +OP4 E013E9 0 +OP4 E013EA 0 +OP4 E013EB 0 +OP4 E013EC 0 +OP4 E013ED 0 +OP4 E013EE 0 +OP4 E013EF 0 +OP4 E013F0 0 +OP4 E013F1 0 +OP4 E013F2 0 +OP4 E013F3 0 +OP4 E013F4 0 +OP4 E013F5 0 +OP4 E013F6 0 +OP4 E013F7 0 +OP4 E013F8 0 +OP4 E013F9 0 +OP4 E013FA 0 +OP4 E013FB 0 +OP4 E013FC 0 +OP4 E013FD 0 +OP4 E013FE 0 +OP4 E013FF 0 +OP4 E01400 0 +OP4 E01401 0 +OP4 E01402 0 +OP4 E01403 0 +OP4 E01404 0 +OP4 E01405 0 +OP4 E01406 0 +OP4 E01407 0 +OP4 E01408 0 +OP4 E01409 0 +OP4 E0140A 0 +OP4 E0140B 0 +OP4 E0140C 0 +OP4 E0140D 0 +OP4 E0140E 0 +OP4 E0140F 0 +OP4 E01410 0 +OP4 E01411 0 +OP4 E01412 0 +OP4 E01413 0 +OP4 E01414 0 +OP4 E01415 0 +OP4 E01416 0 +OP4 E01417 0 +OP4 E01418 0 +OP4 E01419 0 +OP4 E0141A 0 +OP4 E0141B 0 +OP4 E0141C 0 +OP4 E0141D 0 +OP4 E0141E 0 +OP4 E0141F 0 +OP4 E01420 0 +OP4 E01421 0 +OP4 E01422 0 +OP4 E01423 0 +OP4 E01424 0 +OP4 E01425 0 +OP4 E01426 0 +OP4 E01427 0 +OP4 E01428 0 +OP4 E01429 0 +OP4 E0142A 0 +OP4 E0142B 0 +OP4 E0142C 0 +OP4 E0142D 0 +OP4 E0142E 0 +OP4 E0142F 0 +OP4 E01430 0 +OP4 E01431 0 +OP4 E01432 0 +OP4 E01433 0 +OP4 E01434 0 +OP4 E01435 0 +OP4 E01436 0 +OP4 E01437 0 +OP4 E01438 0 +OP4 E01439 0 +OP4 E0143A 0 +OP4 E0143B 0 +OP4 E0143C 0 +OP4 E0143D 0 +OP4 E0143E 0 +OP4 E0143F 0 +OP4 E01440 0 +OP4 E01441 0 +OP4 E01442 0 +OP4 E01443 0 +OP4 E01444 0 +OP4 E01445 0 +OP4 E01446 0 +OP4 E01447 0 +OP4 E01448 0 +OP4 E01449 0 +OP4 E0144A 0 +OP4 E0144B 0 +OP4 E0144C 0 +OP4 E0144D 0 +OP4 E0144E 0 +OP4 E0144F 0 +OP4 E01450 0 +OP4 E01451 0 +OP4 E01452 0 +OP4 E01453 0 +OP4 E01454 0 +OP4 E01455 0 +OP4 E01456 0 +OP4 E01457 0 +OP4 E01458 0 +OP4 E01459 0 +OP4 E0145A 0 +OP4 E0145B 0 +OP4 E0145C 0 +OP4 E0145D 0 +OP4 E0145E 0 +OP4 E0145F 0 +OP4 E01460 0 +OP4 E01461 0 +OP4 E01462 0 +OP4 E01463 0 +OP4 E01464 0 +OP4 E01465 0 +OP4 E01466 0 +OP4 E01467 0 +OP4 E01468 0 +OP4 E01469 0 +OP4 E0146A 0 +OP4 E0146B 0 +OP4 E0146C 0 +OP4 E0146D 0 +OP4 E0146E 0 +OP4 E0146F 0 +OP4 E01470 0 +OP4 E01471 0 +OP4 E01472 0 +OP4 E01473 0 +OP4 E01474 0 +OP4 E01475 0 +OP4 E01476 0 +OP4 E01477 0 +OP4 E01478 0 +OP4 E01479 0 +OP4 E0147A 0 +OP4 E0147B 0 +OP4 E0147C 0 +OP4 E0147D 0 +OP4 E0147E 0 +OP4 E0147F 0 +OP4 E01480 0 +OP4 E01481 0 +OP4 E01482 0 +OP4 E01483 0 +OP4 E01484 0 +OP4 E01485 0 +OP4 E01486 0 +OP4 E01487 0 +OP4 E01488 0 +OP4 E01489 0 +OP4 E0148A 0 +OP4 E0148B 0 +OP4 E0148C 0 +OP4 E0148D 0 +OP4 E0148E 0 +OP4 E0148F 0 +OP4 E01490 0 +OP4 E01491 0 +OP4 E01492 0 +OP4 E01493 0 +OP4 E01494 0 +OP4 E01495 0 +OP4 E01496 0 +OP4 E01497 0 +OP4 E01498 0 +OP4 E01499 0 +OP4 E0149A 0 +OP4 E0149B 0 +OP4 E0149C 0 +OP4 E0149D 0 +OP4 E0149E 0 +OP4 E0149F 0 +OP4 E014A0 0 +OP4 E014A1 0 +OP4 E014A2 0 +OP4 E014A3 0 +OP4 E014A4 0 +OP4 E014A5 0 +OP4 E014A6 0 +OP4 E014A7 0 +OP4 E014A8 0 +OP4 E014A9 0 +OP4 E014AA 0 +OP4 E014AB 0 +OP4 E014AC 0 +OP4 E014AD 0 +OP4 E014AE 0 +OP4 E014AF 0 +OP4 E014B0 0 +OP4 E014B1 0 +OP4 E014B2 0 +OP4 E014B3 0 +OP4 E014B4 0 +OP4 E014B5 0 +OP4 E014B6 0 +OP4 E014B7 0 +OP4 E014B8 0 +OP4 E014B9 0 +OP4 E014BA 0 +OP4 E014BB 0 +OP4 E014BC 0 +OP4 E014BD 0 +OP4 E014BE 0 +OP4 E014BF 0 +OP4 E014C0 0 +OP4 E014C1 0 +OP4 E014C2 0 +OP4 E014C3 0 +OP4 E014C4 0 +OP4 E014C5 0 +OP4 E014C6 0 +OP4 E014C7 0 +OP4 E014C8 0 +OP4 E014C9 0 +OP4 E014CA 0 +OP4 E014CB 0 +OP4 E014CC 0 +OP4 E014CD 0 +OP4 E014CE 0 +OP4 E014CF 0 +OP4 E014D0 0 +OP4 E014D1 0 +OP4 E014D2 0 +OP4 E014D3 0 +OP4 E014D4 0 +OP4 E014D5 0 +OP4 E014D6 0 +OP4 E014D7 0 +OP4 E014D8 0 +OP4 E014D9 0 +OP4 E014DA 0 +OP4 E014DB 0 +OP4 E014DC 0 +OP4 E014DD 0 +OP4 E014DE 0 +OP4 E014DF 0 +OP4 E014E0 0 +OP4 E014E1 0 +OP4 E014E2 0 +OP4 E014E3 0 +OP4 E014E4 0 +OP4 E014E5 0 +OP4 E014E6 0 +OP4 E014E7 0 +OP4 E014E8 0 +OP4 E014E9 0 +OP4 E014EA 0 +OP4 E014EB 0 +OP4 E014EC 0 +OP4 E014ED 0 +OP4 E014EE 0 +OP4 E014EF 0 +OP4 E014F0 0 +OP4 E014F1 0 +OP4 E014F2 0 +OP4 E014F3 0 +OP4 E014F4 0 +OP4 E014F5 0 +OP4 E014F6 0 +OP4 E014F7 0 +OP4 E014F8 0 +OP4 E014F9 0 +OP4 E014FA 0 +OP4 E014FB 0 +OP4 E014FC 0 +OP4 E014FD 0 +OP4 E014FE 0 +OP4 E014FF 0 +OP4 E01500 0 +OP4 E01501 0 +OP4 E01502 0 +OP4 E01503 0 +OP4 E01504 0 +OP4 E01505 0 +OP4 E01506 0 +OP4 E01507 0 +OP4 E01508 0 +OP4 E01509 0 +OP4 E0150A 0 +OP4 E0150B 0 +OP4 E0150C 0 +OP4 E0150D 0 +OP4 E0150E 0 +OP4 E0150F 0 +OP4 E01510 0 +OP4 E01511 0 +OP4 E01512 0 +OP4 E01513 0 +OP4 E01514 0 +OP4 E01515 0 +OP4 E01516 0 +OP4 E01517 0 +OP4 E01518 0 +OP4 E01519 0 +OP4 E0151A 0 +OP4 E0151B 0 +OP4 E0151C 0 +OP4 E0151D 0 +OP4 E0151E 0 +OP4 E0151F 0 +OP4 E01520 0 +OP4 E01521 0 +OP4 E01522 0 +OP4 E01523 0 +OP4 E01524 0 +OP4 E01525 0 +OP4 E01526 0 +OP4 E01527 0 +OP4 E01528 0 +OP4 E01529 0 +OP4 E0152A 0 +OP4 E0152B 0 +OP4 E0152C 0 +OP4 E0152D 0 +OP4 E0152E 0 +OP4 E0152F 0 +OP4 E01530 0 +OP4 E01531 0 +OP4 E01532 0 +OP4 E01533 0 +OP4 E01534 0 +OP4 E01535 0 +OP4 E01536 0 +OP4 E01537 0 +OP4 E01538 0 +OP4 E01539 0 +OP4 E0153A 0 +OP4 E0153B 0 +OP4 E0153C 0 +OP4 E0153D 0 +OP4 E0153E 0 +OP4 E0153F 0 +OP4 E01540 0 +OP4 E01541 0 +OP4 E01542 0 +OP4 E01543 0 +OP4 E01544 0 +OP4 E01545 0 +OP4 E01546 0 +OP4 E01547 0 +OP4 E01548 0 +OP4 E01549 0 +OP4 E0154A 0 +OP4 E0154B 0 +OP4 E0154C 0 +OP4 E0154D 0 +OP4 E0154E 0 +OP4 E0154F 0 +OP4 E01550 0 +OP4 E01551 0 +OP4 E01552 0 +OP4 E01553 0 +OP4 E01554 0 +OP4 E01555 0 +OP4 E01556 0 +OP4 E01557 0 +OP4 E01558 0 +OP4 E01559 0 +OP4 E0155A 0 +OP4 E0155B 0 +OP4 E0155C 0 +OP4 E0155D 0 +OP4 E0155E 0 +OP4 E0155F 0 +OP4 E01560 0 +OP4 E01561 0 +OP4 E01562 0 +OP4 E01563 0 +OP4 E01564 0 +OP4 E01565 0 +OP4 E01566 0 +OP4 E01567 0 +OP4 E01568 0 +OP4 E01569 0 +OP4 E0156A 0 +OP4 E0156B 0 +OP4 E0156C 0 +OP4 E0156D 0 +OP4 E0156E 0 +OP4 E0156F 0 +OP4 E01570 0 +OP4 E01571 0 +OP4 E01572 0 +OP4 E01573 0 +OP4 E01574 0 +OP4 E01575 0 +OP4 E01576 0 +OP4 E01577 0 +OP4 E01578 0 +OP4 E01579 0 +OP4 E0157A 0 +OP4 E0157B 0 +OP4 E0157C 0 +OP4 E0157D 0 +OP4 E0157E 0 +OP4 E0157F 0 +OP4 E01580 0 +OP4 E01581 0 +OP4 E01582 0 +OP4 E01583 0 +OP4 E01584 0 +OP4 E01585 0 +OP4 E01586 0 +OP4 E01587 0 +OP4 E01588 0 +OP4 E01589 0 +OP4 E0158A 0 +OP4 E0158B 0 +OP4 E0158C 0 +OP4 E0158D 0 +OP4 E0158E 0 +OP4 E0158F 0 +OP4 E01590 0 +OP4 E01591 0 +OP4 E01592 0 +OP4 E01593 0 +OP4 E01594 0 +OP4 E01595 0 +OP4 E01596 0 +OP4 E01597 0 +OP4 E01598 0 +OP4 E01599 0 +OP4 E0159A 0 +OP4 E0159B 0 +OP4 E0159C 0 +OP4 E0159D 0 +OP4 E0159E 0 +OP4 E0159F 0 +OP4 E015A0 0 +OP4 E015A1 0 +OP4 E015A2 0 +OP4 E015A3 0 +OP4 E015A4 0 +OP4 E015A5 0 +OP4 E015A6 0 +OP4 E015A7 0 +OP4 E015A8 0 +OP4 E015A9 0 +OP4 E015AA 0 +OP4 E015AB 0 +OP4 E015AC 0 +OP4 E015AD 0 +OP4 E015AE 0 +OP4 E015AF 0 +OP4 E015B0 0 +OP4 E015B1 0 +OP4 E015B2 0 +OP4 E015B3 0 +OP4 E015B4 0 +OP4 E015B5 0 +OP4 E015B6 0 +OP4 E015B7 0 +OP4 E015B8 0 +OP4 E015B9 0 +OP4 E015BA 0 +OP4 E015BB 0 +OP4 E015BC 0 +OP4 E015BD 0 +OP4 E015BE 0 +OP4 E015BF 0 +OP4 E015C0 0 +OP4 E015C1 0 +OP4 E015C2 0 +OP4 E015C3 0 +OP4 E015C4 0 +OP4 E015C5 0 +OP4 E015C6 0 +OP4 E015C7 0 +OP4 E015C8 0 +OP4 E015C9 0 +OP4 E015CA 0 +OP4 E015CB 0 +OP4 E015CC 0 +OP4 E015CD 0 +OP4 E015CE 0 +OP4 E015CF 0 +OP4 E015D0 0 +OP4 E015D1 0 +OP4 E015D2 0 +OP4 E015D3 0 +OP4 E015D4 0 +OP4 E015D5 0 +OP4 E015D6 0 +OP4 E015D7 0 +OP4 E015D8 0 +OP4 E015D9 0 +OP4 E015DA 0 +OP4 E015DB 0 +OP4 E015DC 0 +OP4 E015DD 0 +OP4 E015DE 0 +OP4 E015DF 0 +OP4 E015E0 0 +OP4 E015E1 0 +OP4 E015E2 0 +OP4 E015E3 0 +OP4 E015E4 0 +OP4 E015E5 0 +OP4 E015E6 0 +OP4 E015E7 0 +OP4 E015E8 0 +OP4 E015E9 0 +OP4 E015EA 0 +OP4 E015EB 0 +OP4 E015EC 0 +OP4 E015ED 0 +OP4 E015EE 0 +OP4 E015EF 0 +OP4 E015F0 0 +OP4 E015F1 0 +OP4 E015F2 0 +OP4 E015F3 0 +OP4 E015F4 0 +OP4 E015F5 0 +OP4 E015F6 0 +OP4 E015F7 0 +OP4 E015F8 0 +OP4 E015F9 0 +OP4 E015FA 0 +OP4 E015FB 0 +OP4 E015FC 0 +OP4 E015FD 0 +OP4 E015FE 0 +OP4 E015FF 0 +OP4 E01600 0 +OP4 E01601 0 +OP4 E01602 0 +OP4 E01603 0 +OP4 E01604 0 +OP4 E01605 0 +OP4 E01606 0 +OP4 E01607 0 +OP4 E01608 0 +OP4 E01609 0 +OP4 E0160A 0 +OP4 E0160B 0 +OP4 E0160C 0 +OP4 E0160D 0 +OP4 E0160E 0 +OP4 E0160F 0 +OP4 E01610 0 +OP4 E01611 0 +OP4 E01612 0 +OP4 E01613 0 +OP4 E01614 0 +OP4 E01615 0 +OP4 E01616 0 +OP4 E01617 0 +OP4 E01618 0 +OP4 E01619 0 +OP4 E0161A 0 +OP4 E0161B 0 +OP4 E0161C 0 +OP4 E0161D 0 +OP4 E0161E 0 +OP4 E0161F 0 +OP4 E01620 0 +OP4 E01621 0 +OP4 E01622 0 +OP4 E01623 0 +OP4 E01624 0 +OP4 E01625 0 +OP4 E01626 0 +OP4 E01627 0 +OP4 E01628 0 +OP4 E01629 0 +OP4 E0162A 0 +OP4 E0162B 0 +OP4 E0162C 0 +OP4 E0162D 0 +OP4 E0162E 0 +OP4 E0162F 0 +OP4 E01630 0 +OP4 E01631 0 +OP4 E01632 0 +OP4 E01633 0 +OP4 E01634 0 +OP4 E01635 0 +OP4 E01636 0 +OP4 E01637 0 +OP4 E01638 0 +OP4 E01639 0 +OP4 E0163A 0 +OP4 E0163B 0 +OP4 E0163C 0 +OP4 E0163D 0 +OP4 E0163E 0 +OP4 E0163F 0 +OP4 E01640 0 +OP4 E01641 0 +OP4 E01642 0 +OP4 E01643 0 +OP4 E01644 0 +OP4 E01645 0 +OP4 E01646 0 +OP4 E01647 0 +OP4 E01648 0 +OP4 E01649 0 +OP4 E0164A 0 +OP4 E0164B 0 +OP4 E0164C 0 +OP4 E0164D 0 +OP4 E0164E 0 +OP4 E0164F 0 +OP4 E01650 0 +OP4 E01651 0 +OP4 E01652 0 +OP4 E01653 0 +OP4 E01654 0 +OP4 E01655 0 +OP4 E01656 0 +OP4 E01657 0 +OP4 E01658 0 +OP4 E01659 0 +OP4 E0165A 0 +OP4 E0165B 0 +OP4 E0165C 0 +OP4 E0165D 0 +OP4 E0165E 0 +OP4 E0165F 0 +OP4 E01660 0 +OP4 E01661 0 +OP4 E01662 0 +OP4 E01663 0 +OP4 E01664 0 +OP4 E01665 0 +OP4 E01666 0 +OP4 E01667 0 +OP4 E01668 0 +OP4 E01669 0 +OP4 E0166A 0 +OP4 E0166B 0 +OP4 E0166C 0 +OP4 E0166D 0 +OP4 E0166E 0 +OP4 E0166F 0 +OP4 E01670 0 +OP4 E01671 0 +OP4 E01672 0 +OP4 E01673 0 +OP4 E01674 0 +OP4 E01675 0 +OP4 E01676 0 +OP4 E01677 0 +OP4 E01678 0 +OP4 E01679 0 +OP4 E0167A 0 +OP4 E0167B 0 +OP4 E0167C 0 +OP4 E0167D 0 +OP4 E0167E 0 +OP4 E0167F 0 +OP4 E01680 0 +OP4 E01681 0 +OP4 E01682 0 +OP4 E01683 0 +OP4 E01684 0 +OP4 E01685 0 +OP4 E01686 0 +OP4 E01687 0 +OP4 E01688 0 +OP4 E01689 0 +OP4 E0168A 0 +OP4 E0168B 0 +OP4 E0168C 0 +OP4 E0168D 0 +OP4 E0168E 0 +OP4 E0168F 0 +OP4 E01690 0 +OP4 E01691 0 +OP4 E01692 0 +OP4 E01693 0 +OP4 E01694 0 +OP4 E01695 0 +OP4 E01696 0 +OP4 E01697 0 +OP4 E01698 0 +OP4 E01699 0 +OP4 E0169A 0 +OP4 E0169B 0 +OP4 E0169C 0 +OP4 E0169D 0 +OP4 E0169E 0 +OP4 E0169F 0 +OP4 E016A0 0 +OP4 E016A1 0 +OP4 E016A2 0 +OP4 E016A3 0 +OP4 E016A4 0 +OP4 E016A5 0 +OP4 E016A6 0 +OP4 E016A7 0 +OP4 E016A8 0 +OP4 E016A9 0 +OP4 E016AA 0 +OP4 E016AB 0 +OP4 E016AC 0 +OP4 E016AD 0 +OP4 E016AE 0 +OP4 E016AF 0 +OP4 E016B0 0 +OP4 E016B1 0 +OP4 E016B2 0 +OP4 E016B3 0 +OP4 E016B4 0 +OP4 E016B5 0 +OP4 E016B6 0 +OP4 E016B7 0 +OP4 E016B8 0 +OP4 E016B9 0 +OP4 E016BA 0 +OP4 E016BB 0 +OP4 E016BC 0 +OP4 E016BD 0 +OP4 E016BE 0 +OP4 E016BF 0 +OP4 E016C0 0 +OP4 E016C1 0 +OP4 E016C2 0 +OP4 E016C3 0 +OP4 E016C4 0 +OP4 E016C5 0 +OP4 E016C6 0 +OP4 E016C7 0 +OP4 E016C8 0 +OP4 E016C9 0 +OP4 E016CA 0 +OP4 E016CB 0 +OP4 E016CC 0 +OP4 E016CD 0 +OP4 E016CE 0 +OP4 E016CF 0 +OP4 E016D0 0 +OP4 E016D1 0 +OP4 E016D2 0 +OP4 E016D3 0 +OP4 E016D4 0 +OP4 E016D5 0 +OP4 E016D6 0 +OP4 E016D7 0 +OP4 E016D8 0 +OP4 E016D9 0 +OP4 E016DA 0 +OP4 E016DB 0 +OP4 E016DC 0 +OP4 E016DD 0 +OP4 E016DE 0 +OP4 E016DF 0 +OP4 E016E0 0 +OP4 E016E1 0 +OP4 E016E2 0 +OP4 E016E3 0 +OP4 E016E4 0 +OP4 E016E5 0 +OP4 E016E6 0 +OP4 E016E7 0 +OP4 E016E8 0 +OP4 E016E9 0 +OP4 E016EA 0 +OP4 E016EB 0 +OP4 E016EC 0 +OP4 E016ED 0 +OP4 E016EE 0 +OP4 E016EF 0 +OP4 E016F0 0 +OP4 E016F1 0 +OP4 E016F2 0 +OP4 E016F3 0 +OP4 E016F4 0 +OP4 E016F5 0 +OP4 E016F6 0 +OP4 E016F7 0 +OP4 E016F8 0 +OP4 E016F9 0 +OP4 E016FA 0 +OP4 E016FB 0 +OP4 E016FC 0 +OP4 E016FD 0 +OP4 E016FE 0 +OP4 E016FF 0 +OP4 E01700 0 +OP4 E01701 0 +OP4 E01702 0 +OP4 E01703 0 +OP4 E01704 0 +OP4 E01705 0 +OP4 E01706 0 +OP4 E01707 0 +OP4 E01708 0 +OP4 E01709 0 +OP4 E0170A 0 +OP4 E0170B 0 +OP4 E0170C 0 +OP4 E0170D 0 +OP4 E0170E 0 +OP4 E0170F 0 +OP4 E01710 0 +OP4 E01711 0 +OP4 E01712 0 +OP4 E01713 0 +OP4 E01714 0 +OP4 E01715 0 +OP4 E01716 0 +OP4 E01717 0 +OP4 E01718 0 +OP4 E01719 0 +OP4 E0171A 0 +OP4 E0171B 0 +OP4 E0171C 0 +OP4 E0171D 0 +OP4 E0171E 0 +OP4 E0171F 0 +OP4 E01720 0 +OP4 E01721 0 +OP4 E01722 0 +OP4 E01723 0 +OP4 E01724 0 +OP4 E01725 0 +OP4 E01726 0 +OP4 E01727 0 +OP4 E01728 0 +OP4 E01729 0 +OP4 E0172A 0 +OP4 E0172B 0 +OP4 E0172C 0 +OP4 E0172D 0 +OP4 E0172E 0 +OP4 E0172F 0 +OP4 E01730 0 +OP4 E01731 0 +OP4 E01732 0 +OP4 E01733 0 +OP4 E01734 0 +OP4 E01735 0 +OP4 E01736 0 +OP4 E01737 0 +OP4 E01738 0 +OP4 E01739 0 +OP4 E0173A 0 +OP4 E0173B 0 +OP4 E0173C 0 +OP4 E0173D 0 +OP4 E0173E 0 +OP4 E0173F 0 +OP4 E01740 0 +OP4 E01741 0 +OP4 E01742 0 +OP4 E01743 0 +OP4 E01744 0 +OP4 E01745 0 +OP4 E01746 0 +OP4 E01747 0 +OP4 E01748 0 +OP4 E01749 0 +OP4 E0174A 0 +OP4 E0174B 0 +OP4 E0174C 0 +OP4 E0174D 0 +OP4 E0174E 0 +OP4 E0174F 0 +OP4 E01750 0 +OP4 E01751 0 +OP4 E01752 0 +OP4 E01753 0 +OP4 E01754 0 +OP4 E01755 0 +OP4 E01756 0 +OP4 E01757 0 +OP4 E01758 0 +OP4 E01759 0 +OP4 E0175A 0 +OP4 E0175B 0 +OP4 E0175C 0 +OP4 E0175D 0 +OP4 E0175E 0 +OP4 E0175F 0 +OP4 E01760 0 +OP4 E01761 0 +OP4 E01762 0 +OP4 E01763 0 +OP4 E01764 0 +OP4 E01765 0 +OP4 E01766 0 +OP4 E01767 0 +OP4 E01768 0 +OP4 E01769 0 +OP4 E0176A 0 +OP4 E0176B 0 +OP4 E0176C 0 +OP4 E0176D 0 +OP4 E0176E 0 +OP4 E0176F 0 +OP4 E01770 0 +OP4 E01771 0 +OP4 E01772 0 +OP4 E01773 0 +OP4 E01774 0 +OP4 E01775 0 +OP4 E01776 0 +OP4 E01777 0 +OP4 E01778 0 +OP4 E01779 0 +OP4 E0177A 0 +OP4 E0177B 0 +OP4 E0177C 0 +OP4 E0177D 0 +OP4 E0177E 0 +OP4 E0177F 0 +OP4 E01780 0 +OP4 E01781 0 +OP4 E01782 0 +OP4 E01783 0 +OP4 E01784 0 +OP4 E01785 0 +OP4 E01786 0 +OP4 E01787 0 +OP4 E01788 0 +OP4 E01789 0 +OP4 E0178A 0 +OP4 E0178B 0 +OP4 E0178C 0 +OP4 E0178D 0 +OP4 E0178E 0 +OP4 E0178F 0 +OP4 E01790 0 +OP4 E01791 0 +OP4 E01792 0 +OP4 E01793 0 +OP4 E01794 0 +OP4 E01795 0 +OP4 E01796 0 +OP4 E01797 0 +OP4 E01798 0 +OP4 E01799 0 +OP4 E0179A 0 +OP4 E0179B 0 +OP4 E0179C 0 +OP4 E0179D 0 +OP4 E0179E 0 +OP4 E0179F 0 +OP4 E017A0 0 +OP4 E017A1 0 +OP4 E017A2 0 +OP4 E017A3 0 +OP4 E017A4 0 +OP4 E017A5 0 +OP4 E017A6 0 +OP4 E017A7 0 +OP4 E017A8 0 +OP4 E017A9 0 +OP4 E017AA 0 +OP4 E017AB 0 +OP4 E017AC 0 +OP4 E017AD 0 +OP4 E017AE 0 +OP4 E017AF 0 +OP4 E017B0 0 +OP4 E017B1 0 +OP4 E017B2 0 +OP4 E017B3 0 +OP4 E017B4 0 +OP4 E017B5 0 +OP4 E017B6 0 +OP4 E017B7 0 +OP4 E017B8 0 +OP4 E017B9 0 +OP4 E017BA 0 +OP4 E017BB 0 +OP4 E017BC 0 +OP4 E017BD 0 +OP4 E017BE 0 +OP4 E017BF 0 +OP4 E017C0 0 +OP4 E017C1 0 +OP4 E017C2 0 +OP4 E017C3 0 +OP4 E017C4 0 +OP4 E017C5 0 +OP4 E017C6 0 +OP4 E017C7 0 +OP4 E017C8 0 +OP4 E017C9 0 +OP4 E017CA 0 +OP4 E017CB 0 +OP4 E017CC 0 +OP4 E017CD 0 +OP4 E017CE 0 +OP4 E017CF 0 +OP4 E017D0 0 +OP4 E017D1 0 +OP4 E017D2 0 +OP4 E017D3 0 +OP4 E017D4 0 +OP4 E017D5 0 +OP4 E017D6 0 +OP4 E017D7 0 +OP4 E017D8 0 +OP4 E017D9 0 +OP4 E017DA 0 +OP4 E017DB 0 +OP4 E017DC 0 +OP4 E017DD 0 +OP4 E017DE 0 +OP4 E017DF 0 +OP4 E017E0 0 +OP4 E017E1 0 +OP4 E017E2 0 +OP4 E017E3 0 +OP4 E017E4 0 +OP4 E017E5 0 +OP4 E017E6 0 +OP4 E017E7 0 +OP4 E017E8 0 +OP4 E017E9 0 +OP4 E017EA 0 +OP4 E017EB 0 +OP4 E017EC 0 +OP4 E017ED 0 +OP4 E017EE 0 +OP4 E017EF 0 +OP4 E017F0 0 +OP4 E017F1 0 +OP4 E017F2 0 +OP4 E017F3 0 +OP4 E017F4 0 +OP4 E017F5 0 +OP4 E017F6 0 +OP4 E017F7 0 +OP4 E017F8 0 +OP4 E017F9 0 +OP4 E017FA 0 +OP4 E017FB 0 +OP4 E017FC 0 +OP4 E017FD 0 +OP4 E017FE 0 +OP4 E017FF 0 +OP4 E01800 0 +OP4 E01801 0 +OP4 E01802 0 +OP4 E01803 0 +OP4 E01804 0 +OP4 E01805 0 +OP4 E01806 0 +OP4 E01807 0 +OP4 E01808 0 +OP4 E01809 0 +OP4 E0180A 0 +OP4 E0180B 0 +OP4 E0180C 0 +OP4 E0180D 0 +OP4 E0180E 0 +OP4 E0180F 0 +OP4 E01810 0 +OP4 E01811 0 +OP4 E01812 0 +OP4 E01813 0 +OP4 E01814 0 +OP4 E01815 0 +OP4 E01816 0 +OP4 E01817 0 +OP4 E01818 0 +OP4 E01819 0 +OP4 E0181A 0 +OP4 E0181B 0 +OP4 E0181C 0 +OP4 E0181D 0 +OP4 E0181E 0 +OP4 E0181F 0 +OP4 E01820 0 +OP4 E01821 0 +OP4 E01822 0 +OP4 E01823 0 +OP4 E01824 0 +OP4 E01825 0 +OP4 E01826 0 +OP4 E01827 0 +OP4 E01828 0 +OP4 E01829 0 +OP4 E0182A 0 +OP4 E0182B 0 +OP4 E0182C 0 +OP4 E0182D 0 +OP4 E0182E 0 +OP4 E0182F 0 +OP4 E01830 0 +OP4 E01831 0 +OP4 E01832 0 +OP4 E01833 0 +OP4 E01834 0 +OP4 E01835 0 +OP4 E01836 0 +OP4 E01837 0 +OP4 E01838 0 +OP4 E01839 0 +OP4 E0183A 0 +OP4 E0183B 0 +OP4 E0183C 0 +OP4 E0183D 0 +OP4 E0183E 0 +OP4 E0183F 0 +OP4 E01840 0 +OP4 E01841 0 +OP4 E01842 0 +OP4 E01843 0 +OP4 E01844 0 +OP4 E01845 0 +OP4 E01846 0 +OP4 E01847 0 +OP4 E01848 0 +OP4 E01849 0 +OP4 E0184A 0 +OP4 E0184B 0 +OP4 E0184C 0 +OP4 E0184D 0 +OP4 E0184E 0 +OP4 E0184F 0 +OP4 E01850 0 +OP4 E01851 0 +OP4 E01852 0 +OP4 E01853 0 +OP4 E01854 0 +OP4 E01855 0 +OP4 E01856 0 +OP4 E01857 0 +OP4 E01858 0 +OP4 E01859 0 +OP4 E0185A 0 +OP4 E0185B 0 +OP4 E0185C 0 +OP4 E0185D 0 +OP4 E0185E 0 +OP4 E0185F 0 +OP4 E01860 0 +OP4 E01861 0 +OP4 E01862 0 +OP4 E01863 0 +OP4 E01864 0 +OP4 E01865 0 +OP4 E01866 0 +OP4 E01867 0 +OP4 E01868 0 +OP4 E01869 0 +OP4 E0186A 0 +OP4 E0186B 0 +OP4 E0186C 0 +OP4 E0186D 0 +OP4 E0186E 0 +OP4 E0186F 0 +OP4 E01870 0 +OP4 E01871 0 +OP4 E01872 0 +OP4 E01873 0 +OP4 E01874 0 +OP4 E01875 0 +OP4 E01876 0 +OP4 E01877 0 +OP4 E01878 0 +OP4 E01879 0 +OP4 E0187A 0 +OP4 E0187B 0 +OP4 E0187C 0 +OP4 E0187D 0 +OP4 E0187E 0 +OP4 E0187F 0 +OP4 E01880 0 +OP4 E01881 0 +OP4 E01882 0 +OP4 E01883 0 +OP4 E01884 0 +OP4 E01885 0 +OP4 E01886 0 +OP4 E01887 0 +OP4 E01888 0 +OP4 E01889 0 +OP4 E0188A 0 +OP4 E0188B 0 +OP4 E0188C 0 +OP4 E0188D 0 +OP4 E0188E 0 +OP4 E0188F 0 +OP4 E01890 0 +OP4 E01891 0 +OP4 E01892 0 +OP4 E01893 0 +OP4 E01894 0 +OP4 E01895 0 +OP4 E01896 0 +OP4 E01897 0 +OP4 E01898 0 +OP4 E01899 0 +OP4 E0189A 0 +OP4 E0189B 0 +OP4 E0189C 0 +OP4 E0189D 0 +OP4 E0189E 0 +OP4 E0189F 0 +OP4 E018A0 0 +OP4 E018A1 0 +OP4 E018A2 0 +OP4 E018A3 0 +OP4 E018A4 0 +OP4 E018A5 0 +OP4 E018A6 0 +OP4 E018A7 0 +OP4 E018A8 0 +OP4 E018A9 0 +OP4 E018AA 0 +OP4 E018AB 0 +OP4 E018AC 0 +OP4 E018AD 0 +OP4 E018AE 0 +OP4 E018AF 0 +OP4 E018B0 0 +OP4 E018B1 0 +OP4 E018B2 0 +OP4 E018B3 0 +OP4 E018B4 0 +OP4 E018B5 0 +OP4 E018B6 0 +OP4 E018B7 0 +OP4 E018B8 0 +OP4 E018B9 0 +OP4 E018BA 0 +OP4 E018BB 0 +OP4 E018BC 0 +OP4 E018BD 0 +OP4 E018BE 0 +OP4 E018BF 0 +OP4 E018C0 0 +OP4 E018C1 0 +OP4 E018C2 0 +OP4 E018C3 0 +OP4 E018C4 0 +OP4 E018C5 0 +OP4 E018C6 0 +OP4 E018C7 0 +OP4 E018C8 0 +OP4 E018C9 0 +OP4 E018CA 0 +OP4 E018CB 0 +OP4 E018CC 0 +OP4 E018CD 0 +OP4 E018CE 0 +OP4 E018CF 0 +OP4 E018D0 0 +OP4 E018D1 0 +OP4 E018D2 0 +OP4 E018D3 0 +OP4 E018D4 0 +OP4 E018D5 0 +OP4 E018D6 0 +OP4 E018D7 0 +OP4 E018D8 0 +OP4 E018D9 0 +OP4 E018DA 0 +OP4 E018DB 0 +OP4 E018DC 0 +OP4 E018DD 0 +OP4 E018DE 0 +OP4 E018DF 0 +OP4 E018E0 0 +OP4 E018E1 0 +OP4 E018E2 0 +OP4 E018E3 0 +OP4 E018E4 0 +OP4 E018E5 0 +OP4 E018E6 0 +OP4 E018E7 0 +OP4 E018E8 0 +OP4 E018E9 0 +OP4 E018EA 0 +OP4 E018EB 0 +OP4 E018EC 0 +OP4 E018ED 0 +OP4 E018EE 0 +OP4 E018EF 0 +OP4 E018F0 0 +OP4 E018F1 0 +OP4 E018F2 0 +OP4 E018F3 0 +OP4 E018F4 0 +OP4 E018F5 0 +OP4 E018F6 0 +OP4 E018F7 0 +OP4 E018F8 0 +OP4 E018F9 0 +OP4 E018FA 0 +OP4 E018FB 0 +OP4 E018FC 0 +OP4 E018FD 0 +OP4 E018FE 0 +OP4 E018FF 0 +OP4 E01900 0 +OP4 E01901 0 +OP4 E01902 0 +OP4 E01903 0 +OP4 E01904 0 +OP4 E01905 0 +OP4 E01906 0 +OP4 E01907 0 +OP4 E01908 0 +OP4 E01909 0 +OP4 E0190A 0 +OP4 E0190B 0 +OP4 E0190C 0 +OP4 E0190D 0 +OP4 E0190E 0 +OP4 E0190F 0 +OP4 E01910 0 +OP4 E01911 0 +OP4 E01912 0 +OP4 E01913 0 +OP4 E01914 0 +OP4 E01915 0 +OP4 E01916 0 +OP4 E01917 0 +OP4 E01918 0 +OP4 E01919 0 +OP4 E0191A 0 +OP4 E0191B 0 +OP4 E0191C 0 +OP4 E0191D 0 +OP4 E0191E 0 +OP4 E0191F 0 +OP4 E01920 0 +OP4 E01921 0 +OP4 E01922 0 +OP4 E01923 0 +OP4 E01924 0 +OP4 E01925 0 +OP4 E01926 0 +OP4 E01927 0 +OP4 E01928 0 +OP4 E01929 0 +OP4 E0192A 0 +OP4 E0192B 0 +OP4 E0192C 0 +OP4 E0192D 0 +OP4 E0192E 0 +OP4 E0192F 0 +OP4 E01930 0 +OP4 E01931 0 +OP4 E01932 0 +OP4 E01933 0 +OP4 E01934 0 +OP4 E01935 0 +OP4 E01936 0 +OP4 E01937 0 +OP4 E01938 0 +OP4 E01939 0 +OP4 E0193A 0 +OP4 E0193B 0 +OP4 E0193C 0 +OP4 E0193D 0 +OP4 E0193E 0 +OP4 E0193F 0 +OP4 E01940 0 +OP4 E01941 0 +OP4 E01942 0 +OP4 E01943 0 +OP4 E01944 0 +OP4 E01945 0 +OP4 E01946 0 +OP4 E01947 0 +OP4 E01948 0 +OP4 E01949 0 +OP4 E0194A 0 +OP4 E0194B 0 +OP4 E0194C 0 +OP4 E0194D 0 +OP4 E0194E 0 +OP4 E0194F 0 +OP4 E01950 0 +OP4 E01951 0 +OP4 E01952 0 +OP4 E01953 0 +OP4 E01954 0 +OP4 E01955 0 +OP4 E01956 0 +OP4 E01957 0 +OP4 E01958 0 +OP4 E01959 0 +OP4 E0195A 0 +OP4 E0195B 0 +OP4 E0195C 0 +OP4 E0195D 0 +OP4 E0195E 0 +OP4 E0195F 0 +OP4 E01960 0 +OP4 E01961 0 +OP4 E01962 0 +OP4 E01963 0 +OP4 E01964 0 +OP4 E01965 0 +OP4 E01966 0 +OP4 E01967 0 +OP4 E01968 0 +OP4 E01969 0 +OP4 E0196A 0 +OP4 E0196B 0 +OP4 E0196C 0 +OP4 E0196D 0 +OP4 E0196E 0 +OP4 E0196F 0 +OP4 E01970 0 +OP4 E01971 0 +OP4 E01972 0 +OP4 E01973 0 +OP4 E01974 0 +OP4 E01975 0 +OP4 E01976 0 +OP4 E01977 0 +OP4 E01978 0 +OP4 E01979 0 +OP4 E0197A 0 +OP4 E0197B 0 +OP4 E0197C 0 +OP4 E0197D 0 +OP4 E0197E 0 +OP4 E0197F 0 +OP4 E01980 0 +OP4 E01981 0 +OP4 E01982 0 +OP4 E01983 0 +OP4 E01984 0 +OP4 E01985 0 +OP4 E01986 0 +OP4 E01987 0 +OP4 E01988 0 +OP4 E01989 0 +OP4 E0198A 0 +OP4 E0198B 0 +OP4 E0198C 0 +OP4 E0198D 0 +OP4 E0198E 0 +OP4 E0198F 0 +OP4 E01990 0 +OP4 E01991 0 +OP4 E01992 0 +OP4 E01993 0 +OP4 E01994 0 +OP4 E01995 0 +OP4 E01996 0 +OP4 E01997 0 +OP4 E01998 0 +OP4 E01999 0 +OP4 E0199A 0 +OP4 E0199B 0 +OP4 E0199C 0 +OP4 E0199D 0 +OP4 E0199E 0 +OP4 E0199F 0 +OP4 E019A0 0 +OP4 E019A1 0 +OP4 E019A2 0 +OP4 E019A3 0 +OP4 E019A4 0 +OP4 E019A5 0 +OP4 E019A6 0 +OP4 E019A7 0 +OP4 E019A8 0 +OP4 E019A9 0 +OP4 E019AA 0 +OP4 E019AB 0 +OP4 E019AC 0 +OP4 E019AD 0 +OP4 E019AE 0 +OP4 E019AF 0 +OP4 E019B0 0 +OP4 E019B1 0 +OP4 E019B2 0 +OP4 E019B3 0 +OP4 E019B4 0 +OP4 E019B5 0 +OP4 E019B6 0 +OP4 E019B7 0 +OP4 E019B8 0 +OP4 E019B9 0 +OP4 E019BA 0 +OP4 E019BB 0 +OP4 E019BC 0 +OP4 E019BD 0 +OP4 E019BE 0 +OP4 E019BF 0 +OP4 E019C0 0 +OP4 E019C1 0 +OP4 E019C2 0 +OP4 E019C3 0 +OP4 E019C4 0 +OP4 E019C5 0 +OP4 E019C6 0 +OP4 E019C7 0 +OP4 E019C8 0 +OP4 E019C9 0 +OP4 E019CA 0 +OP4 E019CB 0 +OP4 E019CC 0 +OP4 E019CD 0 +OP4 E019CE 0 +OP4 E019CF 0 +OP4 E019D0 0 +OP4 E019D1 0 +OP4 E019D2 0 +OP4 E019D3 0 +OP4 E019D4 0 +OP4 E019D5 0 +OP4 E019D6 0 +OP4 E019D7 0 +OP4 E019D8 0 +OP4 E019D9 0 +OP4 E019DA 0 +OP4 E019DB 0 +OP4 E019DC 0 +OP4 E019DD 0 +OP4 E019DE 0 +OP4 E019DF 0 +OP4 E019E0 0 +OP4 E019E1 0 +OP4 E019E2 0 +OP4 E019E3 0 +OP4 E019E4 0 +OP4 E019E5 0 +OP4 E019E6 0 +OP4 E019E7 0 +OP4 E019E8 0 +OP4 E019E9 0 +OP4 E019EA 0 +OP4 E019EB 0 +OP4 E019EC 0 +OP4 E019ED 0 +OP4 E019EE 0 +OP4 E019EF 0 +OP4 E019F0 0 +OP4 E019F1 0 +OP4 E019F2 0 +OP4 E019F3 0 +OP4 E019F4 0 +OP4 E019F5 0 +OP4 E019F6 0 +OP4 E019F7 0 +OP4 E019F8 0 +OP4 E019F9 0 +OP4 E019FA 0 +OP4 E019FB 0 +OP4 E019FC 0 +OP4 E019FD 0 +OP4 E019FE 0 +OP4 E019FF 0 +OP4 E01A00 0 +OP4 E01A01 0 +OP4 E01A02 0 +OP4 E01A03 0 +OP4 E01A04 0 +OP4 E01A05 0 +OP4 E01A06 0 +OP4 E01A07 0 +OP4 E01A08 0 +OP4 E01A09 0 +OP4 E01A0A 0 +OP4 E01A0B 0 +OP4 E01A0C 0 +OP4 E01A0D 0 +OP4 E01A0E 0 +OP4 E01A0F 0 +OP4 E01A10 0 +OP4 E01A11 0 +OP4 E01A12 0 +OP4 E01A13 0 +OP4 E01A14 0 +OP4 E01A15 0 +OP4 E01A16 0 +OP4 E01A17 0 +OP4 E01A18 0 +OP4 E01A19 0 +OP4 E01A1A 0 +OP4 E01A1B 0 +OP4 E01A1C 0 +OP4 E01A1D 0 +OP4 E01A1E 0 +OP4 E01A1F 0 +OP4 E01A20 0 +OP4 E01A21 0 +OP4 E01A22 0 +OP4 E01A23 0 +OP4 E01A24 0 +OP4 E01A25 0 +OP4 E01A26 0 +OP4 E01A27 0 +OP4 E01A28 0 +OP4 E01A29 0 +OP4 E01A2A 0 +OP4 E01A2B 0 +OP4 E01A2C 0 +OP4 E01A2D 0 +OP4 E01A2E 0 +OP4 E01A2F 0 +OP4 E01A30 0 +OP4 E01A31 0 +OP4 E01A32 0 +OP4 E01A33 0 +OP4 E01A34 0 +OP4 E01A35 0 +OP4 E01A36 0 +OP4 E01A37 0 +OP4 E01A38 0 +OP4 E01A39 0 +OP4 E01A3A 0 +OP4 E01A3B 0 +OP4 E01A3C 0 +OP4 E01A3D 0 +OP4 E01A3E 0 +OP4 E01A3F 0 +OP4 E01A40 0 +OP4 E01A41 0 +OP4 E01A42 0 +OP4 E01A43 0 +OP4 E01A44 0 +OP4 E01A45 0 +OP4 E01A46 0 +OP4 E01A47 0 +OP4 E01A48 0 +OP4 E01A49 0 +OP4 E01A4A 0 +OP4 E01A4B 0 +OP4 E01A4C 0 +OP4 E01A4D 0 +OP4 E01A4E 0 +OP4 E01A4F 0 +OP4 E01A50 0 +OP4 E01A51 0 +OP4 E01A52 0 +OP4 E01A53 0 +OP4 E01A54 0 +OP4 E01A55 0 +OP4 E01A56 0 +OP4 E01A57 0 +OP4 E01A58 0 +OP4 E01A59 0 +OP4 E01A5A 0 +OP4 E01A5B 0 +OP4 E01A5C 0 +OP4 E01A5D 0 +OP4 E01A5E 0 +OP4 E01A5F 0 +OP4 E01A60 0 +OP4 E01A61 0 +OP4 E01A62 0 +OP4 E01A63 0 +OP4 E01A64 0 +OP4 E01A65 0 +OP4 E01A66 0 +OP4 E01A67 0 +OP4 E01A68 0 +OP4 E01A69 0 +OP4 E01A6A 0 +OP4 E01A6B 0 +OP4 E01A6C 0 +OP4 E01A6D 0 +OP4 E01A6E 0 +OP4 E01A6F 0 +OP4 E01A70 0 +OP4 E01A71 0 +OP4 E01A72 0 +OP4 E01A73 0 +OP4 E01A74 0 +OP4 E01A75 0 +OP4 E01A76 0 +OP4 E01A77 0 +OP4 E01A78 0 +OP4 E01A79 0 +OP4 E01A7A 0 +OP4 E01A7B 0 +OP4 E01A7C 0 +OP4 E01A7D 0 +OP4 E01A7E 0 +OP4 E01A7F 0 +OP4 E01A80 0 +OP4 E01A81 0 +OP4 E01A82 0 +OP4 E01A83 0 +OP4 E01A84 0 +OP4 E01A85 0 +OP4 E01A86 0 +OP4 E01A87 0 +OP4 E01A88 0 +OP4 E01A89 0 +OP4 E01A8A 0 +OP4 E01A8B 0 +OP4 E01A8C 0 +OP4 E01A8D 0 +OP4 E01A8E 0 +OP4 E01A8F 0 +OP4 E01A90 0 +OP4 E01A91 0 +OP4 E01A92 0 +OP4 E01A93 0 +OP4 E01A94 0 +OP4 E01A95 0 +OP4 E01A96 0 +OP4 E01A97 0 +OP4 E01A98 0 +OP4 E01A99 0 +OP4 E01A9A 0 +OP4 E01A9B 0 +OP4 E01A9C 0 +OP4 E01A9D 0 +OP4 E01A9E 0 +OP4 E01A9F 0 +OP4 E01AA0 0 +OP4 E01AA1 0 +OP4 E01AA2 0 +OP4 E01AA3 0 +OP4 E01AA4 0 +OP4 E01AA5 0 +OP4 E01AA6 0 +OP4 E01AA7 0 +OP4 E01AA8 0 +OP4 E01AA9 0 +OP4 E01AAA 0 +OP4 E01AAB 0 +OP4 E01AAC 0 +OP4 E01AAD 0 +OP4 E01AAE 0 +OP4 E01AAF 0 +OP4 E01AB0 0 +OP4 E01AB1 0 +OP4 E01AB2 0 +OP4 E01AB3 0 +OP4 E01AB4 0 +OP4 E01AB5 0 +OP4 E01AB6 0 +OP4 E01AB7 0 +OP4 E01AB8 0 +OP4 E01AB9 0 +OP4 E01ABA 0 +OP4 E01ABB 0 +OP4 E01ABC 0 +OP4 E01ABD 0 +OP4 E01ABE 0 +OP4 E01ABF 0 +OP4 E01AC0 0 +OP4 E01AC1 0 +OP4 E01AC2 0 +OP4 E01AC3 0 +OP4 E01AC4 0 +OP4 E01AC5 0 +OP4 E01AC6 0 +OP4 E01AC7 0 +OP4 E01AC8 0 +OP4 E01AC9 0 +OP4 E01ACA 0 +OP4 E01ACB 0 +OP4 E01ACC 0 +OP4 E01ACD 0 +OP4 E01ACE 0 +OP4 E01ACF 0 +OP4 E01AD0 0 +OP4 E01AD1 0 +OP4 E01AD2 0 +OP4 E01AD3 0 +OP4 E01AD4 0 +OP4 E01AD5 0 +OP4 E01AD6 0 +OP4 E01AD7 0 +OP4 E01AD8 0 +OP4 E01AD9 0 +OP4 E01ADA 0 +OP4 E01ADB 0 +OP4 E01ADC 0 +OP4 E01ADD 0 +OP4 E01ADE 0 +OP4 E01ADF 0 +OP4 E01AE0 0 +OP4 E01AE1 0 +OP4 E01AE2 0 +OP4 E01AE3 0 +OP4 E01AE4 0 +OP4 E01AE5 0 +OP4 E01AE6 0 +OP4 E01AE7 0 +OP4 E01AE8 0 +OP4 E01AE9 0 +OP4 E01AEA 0 +OP4 E01AEB 0 +OP4 E01AEC 0 +OP4 E01AED 0 +OP4 E01AEE 0 +OP4 E01AEF 0 +OP4 E01AF0 0 +OP4 E01AF1 0 +OP4 E01AF2 0 +OP4 E01AF3 0 +OP4 E01AF4 0 +OP4 E01AF5 0 +OP4 E01AF6 0 +OP4 E01AF7 0 +OP4 E01AF8 0 +OP4 E01AF9 0 +OP4 E01AFA 0 +OP4 E01AFB 0 +OP4 E01AFC 0 +OP4 E01AFD 0 +OP4 E01AFE 0 +OP4 E01AFF 0 +OP4 E01B00 0 +OP4 E01B01 0 +OP4 E01B02 0 +OP4 E01B03 0 +OP4 E01B04 0 +OP4 E01B05 0 +OP4 E01B06 0 +OP4 E01B07 0 +OP4 E01B08 0 +OP4 E01B09 0 +OP4 E01B0A 0 +OP4 E01B0B 0 +OP4 E01B0C 0 +OP4 E01B0D 0 +OP4 E01B0E 0 +OP4 E01B0F 0 +OP4 E01B10 0 +OP4 E01B11 0 +OP4 E01B12 0 +OP4 E01B13 0 +OP4 E01B14 0 +OP4 E01B15 0 +OP4 E01B16 0 +OP4 E01B17 0 +OP4 E01B18 0 +OP4 E01B19 0 +OP4 E01B1A 0 +OP4 E01B1B 0 +OP4 E01B1C 0 +OP4 E01B1D 0 +OP4 E01B1E 0 +OP4 E01B1F 0 +OP4 E01B20 0 +OP4 E01B21 0 +OP4 E01B22 0 +OP4 E01B23 0 +OP4 E01B24 0 +OP4 E01B25 0 +OP4 E01B26 0 +OP4 E01B27 0 +OP4 E01B28 0 +OP4 E01B29 0 +OP4 E01B2A 0 +OP4 E01B2B 0 +OP4 E01B2C 0 +OP4 E01B2D 0 +OP4 E01B2E 0 +OP4 E01B2F 0 +OP4 E01B30 0 +OP4 E01B31 0 +OP4 E01B32 0 +OP4 E01B33 0 +OP4 E01B34 0 +OP4 E01B35 0 +OP4 E01B36 0 +OP4 E01B37 0 +OP4 E01B38 0 +OP4 E01B39 0 +OP4 E01B3A 0 +OP4 E01B3B 0 +OP4 E01B3C 0 +OP4 E01B3D 0 +OP4 E01B3E 0 +OP4 E01B3F 0 +OP4 E01B40 0 +OP4 E01B41 0 +OP4 E01B42 0 +OP4 E01B43 0 +OP4 E01B44 0 +OP4 E01B45 0 +OP4 E01B46 0 +OP4 E01B47 0 +OP4 E01B48 0 +OP4 E01B49 0 +OP4 E01B4A 0 +OP4 E01B4B 0 +OP4 E01B4C 0 +OP4 E01B4D 0 +OP4 E01B4E 0 +OP4 E01B4F 0 +OP4 E01B50 0 +OP4 E01B51 0 +OP4 E01B52 0 +OP4 E01B53 0 +OP4 E01B54 0 +OP4 E01B55 0 +OP4 E01B56 0 +OP4 E01B57 0 +OP4 E01B58 0 +OP4 E01B59 0 +OP4 E01B5A 0 +OP4 E01B5B 0 +OP4 E01B5C 0 +OP4 E01B5D 0 +OP4 E01B5E 0 +OP4 E01B5F 0 +OP4 E01B60 0 +OP4 E01B61 0 +OP4 E01B62 0 +OP4 E01B63 0 +OP4 E01B64 0 +OP4 E01B65 0 +OP4 E01B66 0 +OP4 E01B67 0 +OP4 E01B68 0 +OP4 E01B69 0 +OP4 E01B6A 0 +OP4 E01B6B 0 +OP4 E01B6C 0 +OP4 E01B6D 0 +OP4 E01B6E 0 +OP4 E01B6F 0 +OP4 E01B70 0 +OP4 E01B71 0 +OP4 E01B72 0 +OP4 E01B73 0 +OP4 E01B74 0 +OP4 E01B75 0 +OP4 E01B76 0 +OP4 E01B77 0 +OP4 E01B78 0 +OP4 E01B79 0 +OP4 E01B7A 0 +OP4 E01B7B 0 +OP4 E01B7C 0 +OP4 E01B7D 0 +OP4 E01B7E 0 +OP4 E01B7F 0 +OP4 E01B80 0 +OP4 E01B81 0 +OP4 E01B82 0 +OP4 E01B83 0 +OP4 E01B84 0 +OP4 E01B85 0 +OP4 E01B86 0 +OP4 E01B87 0 +OP4 E01B88 0 +OP4 E01B89 0 +OP4 E01B8A 0 +OP4 E01B8B 0 +OP4 E01B8C 0 +OP4 E01B8D 0 +OP4 E01B8E 0 +OP4 E01B8F 0 +OP4 E01B90 0 +OP4 E01B91 0 +OP4 E01B92 0 +OP4 E01B93 0 +OP4 E01B94 0 +OP4 E01B95 0 +OP4 E01B96 0 +OP4 E01B97 0 +OP4 E01B98 0 +OP4 E01B99 0 +OP4 E01B9A 0 +OP4 E01B9B 0 +OP4 E01B9C 0 +OP4 E01B9D 0 +OP4 E01B9E 0 +OP4 E01B9F 0 +OP4 E01BA0 0 +OP4 E01BA1 0 +OP4 E01BA2 0 +OP4 E01BA3 0 +OP4 E01BA4 0 +OP4 E01BA5 0 +OP4 E01BA6 0 +OP4 E01BA7 0 +OP4 E01BA8 0 +OP4 E01BA9 0 +OP4 E01BAA 0 +OP4 E01BAB 0 +OP4 E01BAC 0 +OP4 E01BAD 0 +OP4 E01BAE 0 +OP4 E01BAF 0 +OP4 E01BB0 0 +OP4 E01BB1 0 +OP4 E01BB2 0 +OP4 E01BB3 0 +OP4 E01BB4 0 +OP4 E01BB5 0 +OP4 E01BB6 0 +OP4 E01BB7 0 +OP4 E01BB8 0 +OP4 E01BB9 0 +OP4 E01BBA 0 +OP4 E01BBB 0 +OP4 E01BBC 0 +OP4 E01BBD 0 +OP4 E01BBE 0 +OP4 E01BBF 0 +OP4 E01BC0 0 +OP4 E01BC1 0 +OP4 E01BC2 0 +OP4 E01BC3 0 +OP4 E01BC4 0 +OP4 E01BC5 0 +OP4 E01BC6 0 +OP4 E01BC7 0 +OP4 E01BC8 0 +OP4 E01BC9 0 +OP4 E01BCA 0 +OP4 E01BCB 0 +OP4 E01BCC 0 +OP4 E01BCD 0 +OP4 E01BCE 0 +OP4 E01BCF 0 +OP4 E01BD0 0 +OP4 E01BD1 0 +OP4 E01BD2 0 +OP4 E01BD3 0 +OP4 E01BD4 0 +OP4 E01BD5 0 +OP4 E01BD6 0 +OP4 E01BD7 0 +OP4 E01BD8 0 +OP4 E01BD9 0 +OP4 E01BDA 0 +OP4 E01BDB 0 +OP4 E01BDC 0 +OP4 E01BDD 0 +OP4 E01BDE 0 +OP4 E01BDF 0 +OP4 E01BE0 0 +OP4 E01BE1 0 +OP4 E01BE2 0 +OP4 E01BE3 0 +OP4 E01BE4 0 +OP4 E01BE5 0 +OP4 E01BE6 0 +OP4 E01BE7 0 +OP4 E01BE8 0 +OP4 E01BE9 0 +OP4 E01BEA 0 +OP4 E01BEB 0 +OP4 E01BEC 0 +OP4 E01BED 0 +OP4 E01BEE 0 +OP4 E01BEF 0 +OP4 E01BF0 0 +OP4 E01BF1 0 +OP4 E01BF2 0 +OP4 E01BF3 0 +OP4 E01BF4 0 +OP4 E01BF5 0 +OP4 E01BF6 0 +OP4 E01BF7 0 +OP4 E01BF8 0 +OP4 E01BF9 0 +OP4 E01BFA 0 +OP4 E01BFB 0 +OP4 E01BFC 0 +OP4 E01BFD 0 +OP4 E01BFE 0 +OP4 E01BFF 0 +OP4 E01C00 0 +OP4 E01C01 0 +OP4 E01C02 0 +OP4 E01C03 0 +OP4 E01C04 0 +OP4 E01C05 0 +OP4 E01C06 0 +OP4 E01C07 0 +OP4 E01C08 0 +OP4 E01C09 0 +OP4 E01C0A 0 +OP4 E01C0B 0 +OP4 E01C0C 0 +OP4 E01C0D 0 +OP4 E01C0E 0 +OP4 E01C0F 0 +OP4 E01C10 0 +OP4 E01C11 0 +OP4 E01C12 0 +OP4 E01C13 0 +OP4 E01C14 0 +OP4 E01C15 0 +OP4 E01C16 0 +OP4 E01C17 0 +OP4 E01C18 0 +OP4 E01C19 0 +OP4 E01C1A 0 +OP4 E01C1B 0 +OP4 E01C1C 0 +OP4 E01C1D 0 +OP4 E01C1E 0 +OP4 E01C1F 0 +OP4 E01C20 0 +OP4 E01C21 0 +OP4 E01C22 0 +OP4 E01C23 0 +OP4 E01C24 0 +OP4 E01C25 0 +OP4 E01C26 0 +OP4 E01C27 0 +OP4 E01C28 0 +OP4 E01C29 0 +OP4 E01C2A 0 +OP4 E01C2B 0 +OP4 E01C2C 0 +OP4 E01C2D 0 +OP4 E01C2E 0 +OP4 E01C2F 0 +OP4 E01C30 0 +OP4 E01C31 0 +OP4 E01C32 0 +OP4 E01C33 0 +OP4 E01C34 0 +OP4 E01C35 0 +OP4 E01C36 0 +OP4 E01C37 0 +OP4 E01C38 0 +OP4 E01C39 0 +OP4 E01C3A 0 +OP4 E01C3B 0 +OP4 E01C3C 0 +OP4 E01C3D 0 +OP4 E01C3E 0 +OP4 E01C3F 0 +OP4 E01C40 0 +OP4 E01C41 0 +OP4 E01C42 0 +OP4 E01C43 0 +OP4 E01C44 0 +OP4 E01C45 0 +OP4 E01C46 0 +OP4 E01C47 0 +OP4 E01C48 0 +OP4 E01C49 0 +OP4 E01C4A 0 +OP4 E01C4B 0 +OP4 E01C4C 0 +OP4 E01C4D 0 +OP4 E01C4E 0 +OP4 E01C4F 0 +OP4 E01C50 0 +OP4 E01C51 0 +OP4 E01C52 0 +OP4 E01C53 0 +OP4 E01C54 0 +OP4 E01C55 0 +OP4 E01C56 0 +OP4 E01C57 0 +OP4 E01C58 0 +OP4 E01C59 0 +OP4 E01C5A 0 +OP4 E01C5B 0 +OP4 E01C5C 0 +OP4 E01C5D 0 +OP4 E01C5E 0 +OP4 E01C5F 0 +OP4 E01C60 0 +OP4 E01C61 0 +OP4 E01C62 0 +OP4 E01C63 0 +OP4 E01C64 0 +OP4 E01C65 0 +OP4 E01C66 0 +OP4 E01C67 0 +OP4 E01C68 0 +OP4 E01C69 0 +OP4 E01C6A 0 +OP4 E01C6B 0 +OP4 E01C6C 0 +OP4 E01C6D 0 +OP4 E01C6E 0 +OP4 E01C6F 0 +OP4 E01C70 0 +OP4 E01C71 0 +OP4 E01C72 0 +OP4 E01C73 0 +OP4 E01C74 0 +OP4 E01C75 0 +OP4 E01C76 0 +OP4 E01C77 0 +OP4 E01C78 0 +OP4 E01C79 0 +OP4 E01C7A 0 +OP4 E01C7B 0 +OP4 E01C7C 0 +OP4 E01C7D 0 +OP4 E01C7E 0 +OP4 E01C7F 0 +OP4 E01C80 0 +OP4 E01C81 0 +OP4 E01C82 0 +OP4 E01C83 0 +OP4 E01C84 0 +OP4 E01C85 0 +OP4 E01C86 0 +OP4 E01C87 0 +OP4 E01C88 0 +OP4 E01C89 0 +OP4 E01C8A 0 +OP4 E01C8B 0 +OP4 E01C8C 0 +OP4 E01C8D 0 +OP4 E01C8E 0 +OP4 E01C8F 0 +OP4 E01C90 0 +OP4 E01C91 0 +OP4 E01C92 0 +OP4 E01C93 0 +OP4 E01C94 0 +OP4 E01C95 0 +OP4 E01C96 0 +OP4 E01C97 0 +OP4 E01C98 0 +OP4 E01C99 0 +OP4 E01C9A 0 +OP4 E01C9B 0 +OP4 E01C9C 0 +OP4 E01C9D 0 +OP4 E01C9E 0 +OP4 E01C9F 0 +OP4 E01CA0 0 +OP4 E01CA1 0 +OP4 E01CA2 0 +OP4 E01CA3 0 +OP4 E01CA4 0 +OP4 E01CA5 0 +OP4 E01CA6 0 +OP4 E01CA7 0 +OP4 E01CA8 0 +OP4 E01CA9 0 +OP4 E01CAA 0 +OP4 E01CAB 0 +OP4 E01CAC 0 +OP4 E01CAD 0 +OP4 E01CAE 0 +OP4 E01CAF 0 +OP4 E01CB0 0 +OP4 E01CB1 0 +OP4 E01CB2 0 +OP4 E01CB3 0 +OP4 E01CB4 0 +OP4 E01CB5 0 +OP4 E01CB6 0 +OP4 E01CB7 0 +OP4 E01CB8 0 +OP4 E01CB9 0 +OP4 E01CBA 0 +OP4 E01CBB 0 +OP4 E01CBC 0 +OP4 E01CBD 0 +OP4 E01CBE 0 +OP4 E01CBF 0 +OP4 E01CC0 0 +OP4 E01CC1 0 +OP4 E01CC2 0 +OP4 E01CC3 0 +OP4 E01CC4 0 +OP4 E01CC5 0 +OP4 E01CC6 0 +OP4 E01CC7 0 +OP4 E01CC8 0 +OP4 E01CC9 0 +OP4 E01CCA 0 +OP4 E01CCB 0 +OP4 E01CCC 0 +OP4 E01CCD 0 +OP4 E01CCE 0 +OP4 E01CCF 0 +OP4 E01CD0 0 +OP4 E01CD1 0 +OP4 E01CD2 0 +OP4 E01CD3 0 +OP4 E01CD4 0 +OP4 E01CD5 0 +OP4 E01CD6 0 +OP4 E01CD7 0 +OP4 E01CD8 0 +OP4 E01CD9 0 +OP4 E01CDA 0 +OP4 E01CDB 0 +OP4 E01CDC 0 +OP4 E01CDD 0 +OP4 E01CDE 0 +OP4 E01CDF 0 +OP4 E01CE0 0 +OP4 E01CE1 0 +OP4 E01CE2 0 +OP4 E01CE3 0 +OP4 E01CE4 0 +OP4 E01CE5 0 +OP4 E01CE6 0 +OP4 E01CE7 0 +OP4 E01CE8 0 +OP4 E01CE9 0 +OP4 E01CEA 0 +OP4 E01CEB 0 +OP4 E01CEC 0 +OP4 E01CED 0 +OP4 E01CEE 0 +OP4 E01CEF 0 +OP4 E01CF0 0 +OP4 E01CF1 0 +OP4 E01CF2 0 +OP4 E01CF3 0 +OP4 E01CF4 0 +OP4 E01CF5 0 +OP4 E01CF6 0 +OP4 E01CF7 0 +OP4 E01CF8 0 +OP4 E01CF9 0 +OP4 E01CFA 0 +OP4 E01CFB 0 +OP4 E01CFC 0 +OP4 E01CFD 0 +OP4 E01CFE 0 +OP4 E01CFF 0 +OP4 E01D00 0 +OP4 E01D01 0 +OP4 E01D02 0 +OP4 E01D03 0 +OP4 E01D04 0 +OP4 E01D05 0 +OP4 E01D06 0 +OP4 E01D07 0 +OP4 E01D08 0 +OP4 E01D09 0 +OP4 E01D0A 0 +OP4 E01D0B 0 +OP4 E01D0C 0 +OP4 E01D0D 0 +OP4 E01D0E 0 +OP4 E01D0F 0 +OP4 E01D10 0 +OP4 E01D11 0 +OP4 E01D12 0 +OP4 E01D13 0 +OP4 E01D14 0 +OP4 E01D15 0 +OP4 E01D16 0 +OP4 E01D17 0 +OP4 E01D18 0 +OP4 E01D19 0 +OP4 E01D1A 0 +OP4 E01D1B 0 +OP4 E01D1C 0 +OP4 E01D1D 0 +OP4 E01D1E 0 +OP4 E01D1F 0 +OP4 E01D20 0 +OP4 E01D21 0 +OP4 E01D22 0 +OP4 E01D23 0 +OP4 E01D24 0 +OP4 E01D25 0 +OP4 E01D26 0 +OP4 E01D27 0 +OP4 E01D28 0 +OP4 E01D29 0 +OP4 E01D2A 0 +OP4 E01D2B 0 +OP4 E01D2C 0 +OP4 E01D2D 0 +OP4 E01D2E 0 +OP4 E01D2F 0 +OP4 E01D30 0 +OP4 E01D31 0 +OP4 E01D32 0 +OP4 E01D33 0 +OP4 E01D34 0 +OP4 E01D35 0 +OP4 E01D36 0 +OP4 E01D37 0 +OP4 E01D38 0 +OP4 E01D39 0 +OP4 E01D3A 0 +OP4 E01D3B 0 +OP4 E01D3C 0 +OP4 E01D3D 0 +OP4 E01D3E 0 +OP4 E01D3F 0 +OP4 E01D40 0 +OP4 E01D41 0 +OP4 E01D42 0 +OP4 E01D43 0 +OP4 E01D44 0 +OP4 E01D45 0 +OP4 E01D46 0 +OP4 E01D47 0 +OP4 E01D48 0 +OP4 E01D49 0 +OP4 E01D4A 0 +OP4 E01D4B 0 +OP4 E01D4C 0 +OP4 E01D4D 0 +OP4 E01D4E 0 +OP4 E01D4F 0 +OP4 E01D50 0 +OP4 E01D51 0 +OP4 E01D52 0 +OP4 E01D53 0 +OP4 E01D54 0 +OP4 E01D55 0 +OP4 E01D56 0 +OP4 E01D57 0 +OP4 E01D58 0 +OP4 E01D59 0 +OP4 E01D5A 0 +OP4 E01D5B 0 +OP4 E01D5C 0 +OP4 E01D5D 0 +OP4 E01D5E 0 +OP4 E01D5F 0 +OP4 E01D60 0 +OP4 E01D61 0 +OP4 E01D62 0 +OP4 E01D63 0 +OP4 E01D64 0 +OP4 E01D65 0 +OP4 E01D66 0 +OP4 E01D67 0 +OP4 E01D68 0 +OP4 E01D69 0 +OP4 E01D6A 0 +OP4 E01D6B 0 +OP4 E01D6C 0 +OP4 E01D6D 0 +OP4 E01D6E 0 +OP4 E01D6F 0 +OP4 E01D70 0 +OP4 E01D71 0 +OP4 E01D72 0 +OP4 E01D73 0 +OP4 E01D74 0 +OP4 E01D75 0 +OP4 E01D76 0 +OP4 E01D77 0 +OP4 E01D78 0 +OP4 E01D79 0 +OP4 E01D7A 0 +OP4 E01D7B 0 +OP4 E01D7C 0 +OP4 E01D7D 0 +OP4 E01D7E 0 +OP4 E01D7F 0 +OP4 E01D80 0 +OP4 E01D81 0 +OP4 E01D82 0 +OP4 E01D83 0 +OP4 E01D84 0 +OP4 E01D85 0 +OP4 E01D86 0 +OP4 E01D87 0 +OP4 E01D88 0 +OP4 E01D89 0 +OP4 E01D8A 0 +OP4 E01D8B 0 +OP4 E01D8C 0 +OP4 E01D8D 0 +OP4 E01D8E 0 +OP4 E01D8F 0 +OP4 E01D90 0 +OP4 E01D91 0 +OP4 E01D92 0 +OP4 E01D93 0 +OP4 E01D94 0 +OP4 E01D95 0 +OP4 E01D96 0 +OP4 E01D97 0 +OP4 E01D98 0 +OP4 E01D99 0 +OP4 E01D9A 0 +OP4 E01D9B 0 +OP4 E01D9C 0 +OP4 E01D9D 0 +OP4 E01D9E 0 +OP4 E01D9F 0 +OP4 E01DA0 0 +OP4 E01DA1 0 +OP4 E01DA2 0 +OP4 E01DA3 0 +OP4 E01DA4 0 +OP4 E01DA5 0 +OP4 E01DA6 0 +OP4 E01DA7 0 +OP4 E01DA8 0 +OP4 E01DA9 0 +OP4 E01DAA 0 +OP4 E01DAB 0 +OP4 E01DAC 0 +OP4 E01DAD 0 +OP4 E01DAE 0 +OP4 E01DAF 0 +OP4 E01DB0 0 +OP4 E01DB1 0 +OP4 E01DB2 0 +OP4 E01DB3 0 +OP4 E01DB4 0 +OP4 E01DB5 0 +OP4 E01DB6 0 +OP4 E01DB7 0 +OP4 E01DB8 0 +OP4 E01DB9 0 +OP4 E01DBA 0 +OP4 E01DBB 0 +OP4 E01DBC 0 +OP4 E01DBD 0 +OP4 E01DBE 0 +OP4 E01DBF 0 +OP4 E01DC0 0 +OP4 E01DC1 0 +OP4 E01DC2 0 +OP4 E01DC3 0 +OP4 E01DC4 0 +OP4 E01DC5 0 +OP4 E01DC6 0 +OP4 E01DC7 0 +OP4 E01DC8 0 +OP4 E01DC9 0 +OP4 E01DCA 0 +OP4 E01DCB 0 +OP4 E01DCC 0 +OP4 E01DCD 0 +OP4 E01DCE 0 +OP4 E01DCF 0 +OP4 E01DD0 0 +OP4 E01DD1 0 +OP4 E01DD2 0 +OP4 E01DD3 0 +OP4 E01DD4 0 +OP4 E01DD5 0 +OP4 E01DD6 0 +OP4 E01DD7 0 +OP4 E01DD8 0 +OP4 E01DD9 0 +OP4 E01DDA 0 +OP4 E01DDB 0 +OP4 E01DDC 0 +OP4 E01DDD 0 +OP4 E01DDE 0 +OP4 E01DDF 0 +OP4 E01DE0 0 +OP4 E01DE1 0 +OP4 E01DE2 0 +OP4 E01DE3 0 +OP4 E01DE4 0 +OP4 E01DE5 0 +OP4 E01DE6 0 +OP4 E01DE7 0 +OP4 E01DE8 0 +OP4 E01DE9 0 +OP4 E01DEA 0 +OP4 E01DEB 0 +OP4 E01DEC 0 +OP4 E01DED 0 +OP4 E01DEE 0 +OP4 E01DEF 0 +OP4 E01DF0 0 +OP4 E01DF1 0 +OP4 E01DF2 0 +OP4 E01DF3 0 +OP4 E01DF4 0 +OP4 E01DF5 0 +OP4 E01DF6 0 +OP4 E01DF7 0 +OP4 E01DF8 0 +OP4 E01DF9 0 +OP4 E01DFA 0 +OP4 E01DFB 0 +OP4 E01DFC 0 +OP4 E01DFD 0 +OP4 E01DFE 0 +OP4 E01DFF 0 +OP4 E01E00 0 +OP4 E01E01 0 +OP4 E01E02 0 +OP4 E01E03 0 +OP4 E01E04 0 +OP4 E01E05 0 +OP4 E01E06 0 +OP4 E01E07 0 +OP4 E01E08 0 +OP4 E01E09 0 +OP4 E01E0A 0 +OP4 E01E0B 0 +OP4 E01E0C 0 +OP4 E01E0D 0 +OP4 E01E0E 0 +OP4 E01E0F 0 +OP4 E01E10 0 +OP4 E01E11 0 +OP4 E01E12 0 +OP4 E01E13 0 +OP4 E01E14 0 +OP4 E01E15 0 +OP4 E01E16 0 +OP4 E01E17 0 +OP4 E01E18 0 +OP4 E01E19 0 +OP4 E01E1A 0 +OP4 E01E1B 0 +OP4 E01E1C 0 +OP4 E01E1D 0 +OP4 E01E1E 0 +OP4 E01E1F 0 +OP4 E01E20 0 +OP4 E01E21 0 +OP4 E01E22 0 +OP4 E01E23 0 +OP4 E01E24 0 +OP4 E01E25 0 +OP4 E01E26 0 +OP4 E01E27 0 +OP4 E01E28 0 +OP4 E01E29 0 +OP4 E01E2A 0 +OP4 E01E2B 0 +OP4 E01E2C 0 +OP4 E01E2D 0 +OP4 E01E2E 0 +OP4 E01E2F 0 +OP4 E01E30 0 +OP4 E01E31 0 +OP4 E01E32 0 +OP4 E01E33 0 +OP4 E01E34 0 +OP4 E01E35 0 +OP4 E01E36 0 +OP4 E01E37 0 +OP4 E01E38 0 +OP4 E01E39 0 +OP4 E01E3A 0 +OP4 E01E3B 0 +OP4 E01E3C 0 +OP4 E01E3D 0 +OP4 E01E3E 0 +OP4 E01E3F 0 +OP4 E01E40 0 +OP4 E01E41 0 +OP4 E01E42 0 +OP4 E01E43 0 +OP4 E01E44 0 +OP4 E01E45 0 +OP4 E01E46 0 +OP4 E01E47 0 +OP4 E01E48 0 +OP4 E01E49 0 +OP4 E01E4A 0 +OP4 E01E4B 0 +OP4 E01E4C 0 +OP4 E01E4D 0 +OP4 E01E4E 0 +OP4 E01E4F 0 +OP4 E01E50 0 +OP4 E01E51 0 +OP4 E01E52 0 +OP4 E01E53 0 +OP4 E01E54 0 +OP4 E01E55 0 +OP4 E01E56 0 +OP4 E01E57 0 +OP4 E01E58 0 +OP4 E01E59 0 +OP4 E01E5A 0 +OP4 E01E5B 0 +OP4 E01E5C 0 +OP4 E01E5D 0 +OP4 E01E5E 0 +OP4 E01E5F 0 +OP4 E01E60 0 +OP4 E01E61 0 +OP4 E01E62 0 +OP4 E01E63 0 +OP4 E01E64 0 +OP4 E01E65 0 +OP4 E01E66 0 +OP4 E01E67 0 +OP4 E01E68 0 +OP4 E01E69 0 +OP4 E01E6A 0 +OP4 E01E6B 0 +OP4 E01E6C 0 +OP4 E01E6D 0 +OP4 E01E6E 0 +OP4 E01E6F 0 +OP4 E01E70 0 +OP4 E01E71 0 +OP4 E01E72 0 +OP4 E01E73 0 +OP4 E01E74 0 +OP4 E01E75 0 +OP4 E01E76 0 +OP4 E01E77 0 +OP4 E01E78 0 +OP4 E01E79 0 +OP4 E01E7A 0 +OP4 E01E7B 0 +OP4 E01E7C 0 +OP4 E01E7D 0 +OP4 E01E7E 0 +OP4 E01E7F 0 +OP4 E01E80 0 +OP4 E01E81 0 +OP4 E01E82 0 +OP4 E01E83 0 +OP4 E01E84 0 +OP4 E01E85 0 +OP4 E01E86 0 +OP4 E01E87 0 +OP4 E01E88 0 +OP4 E01E89 0 +OP4 E01E8A 0 +OP4 E01E8B 0 +OP4 E01E8C 0 +OP4 E01E8D 0 +OP4 E01E8E 0 +OP4 E01E8F 0 +OP4 E01E90 0 +OP4 E01E91 0 +OP4 E01E92 0 +OP4 E01E93 0 +OP4 E01E94 0 +OP4 E01E95 0 +OP4 E01E96 0 +OP4 E01E97 0 +OP4 E01E98 0 +OP4 E01E99 0 +OP4 E01E9A 0 +OP4 E01E9B 0 +OP4 E01E9C 0 +OP4 E01E9D 0 +OP4 E01E9E 0 +OP4 E01E9F 0 +OP4 E01EA0 0 +OP4 E01EA1 0 +OP4 E01EA2 0 +OP4 E01EA3 0 +OP4 E01EA4 0 +OP4 E01EA5 0 +OP4 E01EA6 0 +OP4 E01EA7 0 +OP4 E01EA8 0 +OP4 E01EA9 0 +OP4 E01EAA 0 +OP4 E01EAB 0 +OP4 E01EAC 0 +OP4 E01EAD 0 +OP4 E01EAE 0 +OP4 E01EAF 0 +OP4 E01EB0 0 +OP4 E01EB1 0 +OP4 E01EB2 0 +OP4 E01EB3 0 +OP4 E01EB4 0 +OP4 E01EB5 0 +OP4 E01EB6 0 +OP4 E01EB7 0 +OP4 E01EB8 0 +OP4 E01EB9 0 +OP4 E01EBA 0 +OP4 E01EBB 0 +OP4 E01EBC 0 +OP4 E01EBD 0 +OP4 E01EBE 0 +OP4 E01EBF 0 +OP4 E01EC0 0 +OP4 E01EC1 0 +OP4 E01EC2 0 +OP4 E01EC3 0 +OP4 E01EC4 0 +OP4 E01EC5 0 +OP4 E01EC6 0 +OP4 E01EC7 0 +OP4 E01EC8 0 +OP4 E01EC9 0 +OP4 E01ECA 0 +OP4 E01ECB 0 +OP4 E01ECC 0 +OP4 E01ECD 0 +OP4 E01ECE 0 +OP4 E01ECF 0 +OP4 E01ED0 0 +OP4 E01ED1 0 +OP4 E01ED2 0 +OP4 E01ED3 0 +OP4 E01ED4 0 +OP4 E01ED5 0 +OP4 E01ED6 0 +OP4 E01ED7 0 +OP4 E01ED8 0 +OP4 E01ED9 0 +OP4 E01EDA 0 +OP4 E01EDB 0 +OP4 E01EDC 0 +OP4 E01EDD 0 +OP4 E01EDE 0 +OP4 E01EDF 0 +OP4 E01EE0 0 +OP4 E01EE1 0 +OP4 E01EE2 0 +OP4 E01EE3 0 +OP4 E01EE4 0 +OP4 E01EE5 0 +OP4 E01EE6 0 +OP4 E01EE7 0 +OP4 E01EE8 0 +OP4 E01EE9 0 +OP4 E01EEA 0 +OP4 E01EEB 0 +OP4 E01EEC 0 +OP4 E01EED 0 +OP4 E01EEE 0 +OP4 E01EEF 0 +OP4 E01EF0 0 +OP4 E01EF1 0 +OP4 E01EF2 0 +OP4 E01EF3 0 +OP4 E01EF4 0 +OP4 E01EF5 0 +OP4 E01EF6 0 +OP4 E01EF7 0 +OP4 E01EF8 0 +OP4 E01EF9 0 +OP4 E01EFA 0 +OP4 E01EFB 0 +OP4 E01EFC 0 +OP4 E01EFD 0 +OP4 E01EFE 0 +OP4 E01EFF 0 +OP4 E01F00 0 +OP4 E01F01 0 +OP4 E01F02 0 +OP4 E01F03 0 +OP4 E01F04 0 +OP4 E01F05 0 +OP4 E01F06 0 +OP4 E01F07 0 +OP4 E01F08 0 +OP4 E01F09 0 +OP4 E01F0A 0 +OP4 E01F0B 0 +OP4 E01F0C 0 +OP4 E01F0D 0 +OP4 E01F0E 0 +OP4 E01F0F 0 +OP4 E01F10 0 +OP4 E01F11 0 +OP4 E01F12 0 +OP4 E01F13 0 +OP4 E01F14 0 +OP4 E01F15 0 +OP4 E01F16 0 +OP4 E01F17 0 +OP4 E01F18 0 +OP4 E01F19 0 +OP4 E01F1A 0 +OP4 E01F1B 0 +OP4 E01F1C 0 +OP4 E01F1D 0 +OP4 E01F1E 0 +OP4 E01F1F 0 +OP4 E01F20 0 +OP4 E01F21 0 +OP4 E01F22 0 +OP4 E01F23 0 +OP4 E01F24 0 +OP4 E01F25 0 +OP4 E01F26 0 +OP4 E01F27 0 +OP4 E01F28 0 +OP4 E01F29 0 +OP4 E01F2A 0 +OP4 E01F2B 0 +OP4 E01F2C 0 +OP4 E01F2D 0 +OP4 E01F2E 0 +OP4 E01F2F 0 +OP4 E01F30 0 +OP4 E01F31 0 +OP4 E01F32 0 +OP4 E01F33 0 +OP4 E01F34 0 +OP4 E01F35 0 +OP4 E01F36 0 +OP4 E01F37 0 +OP4 E01F38 0 +OP4 E01F39 0 +OP4 E01F3A 0 +OP4 E01F3B 0 +OP4 E01F3C 0 +OP4 E01F3D 0 +OP4 E01F3E 0 +OP4 E01F3F 0 +OP4 E01F40 0 +OP4 E01F41 0 +OP4 E01F42 0 +OP4 E01F43 0 +OP4 E01F44 0 +OP4 E01F45 0 +OP4 E01F46 0 +OP4 E01F47 0 +OP4 E01F48 0 +OP4 E01F49 0 +OP4 E01F4A 0 +OP4 E01F4B 0 +OP4 E01F4C 0 +OP4 E01F4D 0 +OP4 E01F4E 0 +OP4 E01F4F 0 +OP4 E01F50 0 +OP4 E01F51 0 +OP4 E01F52 0 +OP4 E01F53 0 +OP4 E01F54 0 +OP4 E01F55 0 +OP4 E01F56 0 +OP4 E01F57 0 +OP4 E01F58 0 +OP4 E01F59 0 +OP4 E01F5A 0 +OP4 E01F5B 0 +OP4 E01F5C 0 +OP4 E01F5D 0 +OP4 E01F5E 0 +OP4 E01F5F 0 +OP4 E01F60 0 +OP4 E01F61 0 +OP4 E01F62 0 +OP4 E01F63 0 +OP4 E01F64 0 +OP4 E01F65 0 +OP4 E01F66 0 +OP4 E01F67 0 +OP4 E01F68 0 +OP4 E01F69 0 +OP4 E01F6A 0 +OP4 E01F6B 0 +OP4 E01F6C 0 +OP4 E01F6D 0 +OP4 E01F6E 0 +OP4 E01F6F 0 +OP4 E01F70 0 +OP4 E01F71 0 +OP4 E01F72 0 +OP4 E01F73 0 +OP4 E01F74 0 +OP4 E01F75 0 +OP4 E01F76 0 +OP4 E01F77 0 +OP4 E01F78 0 +OP4 E01F79 0 +OP4 E01F7A 0 +OP4 E01F7B 0 +OP4 E01F7C 0 +OP4 E01F7D 0 +OP4 E01F7E 0 +OP4 E01F7F 0 +OP4 E01F80 0 +OP4 E01F81 0 +OP4 E01F82 0 +OP4 E01F83 0 +OP4 E01F84 0 +OP4 E01F85 0 +OP4 E01F86 0 +OP4 E01F87 0 +OP4 E01F88 0 +OP4 E01F89 0 +OP4 E01F8A 0 +OP4 E01F8B 0 +OP4 E01F8C 0 +OP4 E01F8D 0 +OP4 E01F8E 0 +OP4 E01F8F 0 +OP4 E01F90 0 +OP4 E01F91 0 +OP4 E01F92 0 +OP4 E01F93 0 +OP4 E01F94 0 +OP4 E01F95 0 +OP4 E01F96 0 +OP4 E01F97 0 +OP4 E01F98 0 +OP4 E01F99 0 +OP4 E01F9A 0 +OP4 E01F9B 0 +OP4 E01F9C 0 +OP4 E01F9D 0 +OP4 E01F9E 0 +OP4 E01F9F 0 +OP4 E01FA0 0 +OP4 E01FA1 0 +OP4 E01FA2 0 +OP4 E01FA3 0 +OP4 E01FA4 0 +OP4 E01FA5 0 +OP4 E01FA6 0 +OP4 E01FA7 0 +OP4 E01FA8 0 +OP4 E01FA9 0 +OP4 E01FAA 0 +OP4 E01FAB 0 +OP4 E01FAC 0 +OP4 E01FAD 0 +OP4 E01FAE 0 +OP4 E01FAF 0 +OP4 E01FB0 0 +OP4 E01FB1 0 +OP4 E01FB2 0 +OP4 E01FB3 0 +OP4 E01FB4 0 +OP4 E01FB5 0 +OP4 E01FB6 0 +OP4 E01FB7 0 +OP4 E01FB8 0 +OP4 E01FB9 0 +OP4 E01FBA 0 +OP4 E01FBB 0 +OP4 E01FBC 0 +OP4 E01FBD 0 +OP4 E01FBE 0 +OP4 E01FBF 0 +OP4 E01FC0 0 +OP4 E01FC1 0 +OP4 E01FC2 0 +OP4 E01FC3 0 +OP4 E01FC4 0 +OP4 E01FC5 0 +OP4 E01FC6 0 +OP4 E01FC7 0 +OP4 E01FC8 0 +OP4 E01FC9 0 +OP4 E01FCA 0 +OP4 E01FCB 0 +OP4 E01FCC 0 +OP4 E01FCD 0 +OP4 E01FCE 0 +OP4 E01FCF 0 +OP4 E01FD0 0 +OP4 E01FD1 0 +OP4 E01FD2 0 +OP4 E01FD3 0 +OP4 E01FD4 0 +OP4 E01FD5 0 +OP4 E01FD6 0 +OP4 E01FD7 0 +OP4 E01FD8 0 +OP4 E01FD9 0 +OP4 E01FDA 0 +OP4 E01FDB 0 +OP4 E01FDC 0 +OP4 E01FDD 0 +OP4 E01FDE 0 +OP4 E01FDF 0 +OP4 E01FE0 0 +OP4 E01FE1 0 +OP4 E01FE2 0 +OP4 E01FE3 0 +OP4 E01FE4 0 +OP4 E01FE5 0 +OP4 E01FE6 0 +OP4 E01FE7 0 +OP4 E01FE8 0 +OP4 E01FE9 0 +OP4 E01FEA 0 +OP4 E01FEB 0 +OP4 E01FEC 0 +OP4 E01FED 0 +OP4 E01FEE 0 +OP4 E01FEF 0 +OP4 E01FF0 0 +OP4 E01FF1 0 +OP4 E01FF2 0 +OP4 E01FF3 0 +OP4 E01FF4 0 +OP4 E01FF5 0 +OP4 E01FF6 0 +OP4 E01FF7 0 +OP4 E01FF8 0 +OP4 E01FF9 0 +OP4 E01FFA 0 +OP4 E01FFB 0 +OP4 E01FFC 0 +OP4 E01FFD 0 +OP4 E01FFE 0 +OP4 E01FFF 0 +OP4 E02000 0 +OP4 E02001 0 +OP4 E02002 0 +OP4 E02003 0 +OP4 E02004 0 +OP4 E02005 0 +OP4 E02006 0 +OP4 E02007 0 +OP4 E02008 0 +OP4 E02009 0 +OP4 E0200A 0 +OP4 E0200B 0 +OP4 E0200C 0 +OP4 E0200D 0 +OP4 E0200E 0 +OP4 E0200F 0 +OP4 E02010 0 +OP4 E02011 0 +OP4 E02012 0 +OP4 E02013 0 +OP4 E02014 0 +OP4 E02015 0 +OP4 E02016 0 +OP4 E02017 0 +OP4 E02018 0 +OP4 E02019 0 +OP4 E0201A 0 +OP4 E0201B 0 +OP4 E0201C 0 +OP4 E0201D 0 +OP4 E0201E 0 +OP4 E0201F 0 +OP4 E02020 0 +OP4 E02021 0 +OP4 E02022 0 +OP4 E02023 0 +OP4 E02024 0 +OP4 E02025 0 +OP4 E02026 0 +OP4 E02027 0 +OP4 E02028 0 +OP4 E02029 0 +OP4 E0202A 0 +OP4 E0202B 0 +OP4 E0202C 0 +OP4 E0202D 0 +OP4 E0202E 0 +OP4 E0202F 0 +OP4 E02030 0 +OP4 E02031 0 +OP4 E02032 0 +OP4 E02033 0 +OP4 E02034 0 +OP4 E02035 0 +OP4 E02036 0 +OP4 E02037 0 +OP4 E02038 0 +OP4 E02039 0 +OP4 E0203A 0 +OP4 E0203B 0 +OP4 E0203C 0 +OP4 E0203D 0 +OP4 E0203E 0 +OP4 E0203F 0 +OP4 E02040 0 +OP4 E02041 0 +OP4 E02042 0 +OP4 E02043 0 +OP4 E02044 0 +OP4 E02045 0 +OP4 E02046 0 +OP4 E02047 0 +OP4 E02048 0 +OP4 E02049 0 +OP4 E0204A 0 +OP4 E0204B 0 +OP4 E0204C 0 +OP4 E0204D 0 +OP4 E0204E 0 +OP4 E0204F 0 +OP4 E02050 0 +OP4 E02051 0 +OP4 E02052 0 +OP4 E02053 0 +OP4 E02054 0 +OP4 E02055 0 +OP4 E02056 0 +OP4 E02057 0 +OP4 E02058 0 +OP4 E02059 0 +OP4 E0205A 0 +OP4 E0205B 0 +OP4 E0205C 0 +OP4 E0205D 0 +OP4 E0205E 0 +OP4 E0205F 0 +OP4 E02060 0 +OP4 E02061 0 +OP4 E02062 0 +OP4 E02063 0 +OP4 E02064 0 +OP4 E02065 0 +OP4 E02066 0 +OP4 E02067 0 +OP4 E02068 0 +OP4 E02069 0 +OP4 E0206A 0 +OP4 E0206B 0 +OP4 E0206C 0 +OP4 E0206D 0 +OP4 E0206E 0 +OP4 E0206F 0 +OP4 E02070 0 +OP4 E02071 0 +OP4 E02072 0 +OP4 E02073 0 +OP4 E02074 0 +OP4 E02075 0 +OP4 E02076 0 +OP4 E02077 0 +OP4 E02078 0 +OP4 E02079 0 +OP4 E0207A 0 +OP4 E0207B 0 +OP4 E0207C 0 +OP4 E0207D 0 +OP4 E0207E 0 +OP4 E0207F 0 +OP4 E02080 0 +OP4 E02081 0 +OP4 E02082 0 +OP4 E02083 0 +OP4 E02084 0 +OP4 E02085 0 +OP4 E02086 0 +OP4 E02087 0 +OP4 E02088 0 +OP4 E02089 0 +OP4 E0208A 0 +OP4 E0208B 0 +OP4 E0208C 0 +OP4 E0208D 0 +OP4 E0208E 0 +OP4 E0208F 0 +OP4 E02090 0 +OP4 E02091 0 +OP4 E02092 0 +OP4 E02093 0 +OP4 E02094 0 +OP4 E02095 0 +OP4 E02096 0 +OP4 E02097 0 +OP4 E02098 0 +OP4 E02099 0 +OP4 E0209A 0 +OP4 E0209B 0 +OP4 E0209C 0 +OP4 E0209D 0 +OP4 E0209E 0 +OP4 E0209F 0 +OP4 E020A0 0 +OP4 E020A1 0 +OP4 E020A2 0 +OP4 E020A3 0 +OP4 E020A4 0 +OP4 E020A5 0 +OP4 E020A6 0 +OP4 E020A7 0 +OP4 E020A8 0 +OP4 E020A9 0 +OP4 E020AA 0 +OP4 E020AB 0 +OP4 E020AC 0 +OP4 E020AD 0 +OP4 E020AE 0 +OP4 E020AF 0 +OP4 E020B0 0 +OP4 E020B1 0 +OP4 E020B2 0 +OP4 E020B3 0 +OP4 E020B4 0 +OP4 E020B5 0 +OP4 E020B6 0 +OP4 E020B7 0 +OP4 E020B8 0 +OP4 E020B9 0 +OP4 E020BA 0 +OP4 E020BB 0 +OP4 E020BC 0 +OP4 E020BD 0 +OP4 E020BE 0 +OP4 E020BF 0 +OP4 E020C0 0 +OP4 E020C1 0 +OP4 E020C2 0 +OP4 E020C3 0 +OP4 E020C4 0 +OP4 E020C5 0 +OP4 E020C6 0 +OP4 E020C7 0 +OP4 E020C8 0 +OP4 E020C9 0 +OP4 E020CA 0 +OP4 E020CB 0 +OP4 E020CC 0 +OP4 E020CD 0 +OP4 E020CE 0 +OP4 E020CF 0 +OP4 E020D0 0 +OP4 E020D1 0 +OP4 E020D2 0 +OP4 E020D3 0 +OP4 E020D4 0 +OP4 E020D5 0 +OP4 E020D6 0 +OP4 E020D7 0 +OP4 E020D8 0 +OP4 E020D9 0 +OP4 E020DA 0 +OP4 E020DB 0 +OP4 E020DC 0 +OP4 E020DD 0 +OP4 E020DE 0 +OP4 E020DF 0 +OP4 E020E0 0 +OP4 E020E1 0 +OP4 E020E2 0 +OP4 E020E3 0 +OP4 E020E4 0 +OP4 E020E5 0 +OP4 E020E6 0 +OP4 E020E7 0 +OP4 E020E8 0 +OP4 E020E9 0 +OP4 E020EA 0 +OP4 E020EB 0 +OP4 E020EC 0 +OP4 E020ED 0 +OP4 E020EE 0 +OP4 E020EF 0 +OP4 E020F0 0 +OP4 E020F1 0 +OP4 E020F2 0 +OP4 E020F3 0 +OP4 E020F4 0 +OP4 E020F5 0 +OP4 E020F6 0 +OP4 E020F7 0 +OP4 E020F8 0 +OP4 E020F9 0 +OP4 E020FA 0 +OP4 E020FB 0 +OP4 E020FC 0 +OP4 E020FD 0 +OP4 E020FE 0 +OP4 E020FF 0 +OP4 E02100 0 +OP4 E02101 0 +OP4 E02102 0 +OP4 E02103 0 +OP4 E02104 0 +OP4 E02105 0 +OP4 E02106 0 +OP4 E02107 0 +OP4 E02108 0 +OP4 E02109 0 +OP4 E0210A 0 +OP4 E0210B 0 +OP4 E0210C 0 +OP4 E0210D 0 +OP4 E0210E 0 +OP4 E0210F 0 +OP4 E02110 0 +OP4 E02111 0 +OP4 E02112 0 +OP4 E02113 0 +OP4 E02114 0 +OP4 E02115 0 +OP4 E02116 0 +OP4 E02117 0 +OP4 E02118 0 +OP4 E02119 0 +OP4 E0211A 0 +OP4 E0211B 0 +OP4 E0211C 0 +OP4 E0211D 0 +OP4 E0211E 0 +OP4 E0211F 0 +OP4 E02120 0 +OP4 E02121 0 +OP4 E02122 0 +OP4 E02123 0 +OP4 E02124 0 +OP4 E02125 0 +OP4 E02126 0 +OP4 E02127 0 +OP4 E02128 0 +OP4 E02129 0 +OP4 E0212A 0 +OP4 E0212B 0 +OP4 E0212C 0 +OP4 E0212D 0 +OP4 E0212E 0 +OP4 E0212F 0 +OP4 E02130 0 +OP4 E02131 0 +OP4 E02132 0 +OP4 E02133 0 +OP4 E02134 0 +OP4 E02135 0 +OP4 E02136 0 +OP4 E02137 0 +OP4 E02138 0 +OP4 E02139 0 +OP4 E0213A 0 +OP4 E0213B 0 +OP4 E0213C 0 +OP4 E0213D 0 +OP4 E0213E 0 +OP4 E0213F 0 +OP4 E02140 0 +OP4 E02141 0 +OP4 E02142 0 +OP4 E02143 0 +OP4 E02144 0 +OP4 E02145 0 +OP4 E02146 0 +OP4 E02147 0 +OP4 E02148 0 +OP4 E02149 0 +OP4 E0214A 0 +OP4 E0214B 0 +OP4 E0214C 0 +OP4 E0214D 0 +OP4 E0214E 0 +OP4 E0214F 0 +OP4 E02150 0 +OP4 E02151 0 +OP4 E02152 0 +OP4 E02153 0 +OP4 E02154 0 +OP4 E02155 0 +OP4 E02156 0 +OP4 E02157 0 +OP4 E02158 0 +OP4 E02159 0 +OP4 E0215A 0 +OP4 E0215B 0 +OP4 E0215C 0 +OP4 E0215D 0 +OP4 E0215E 0 +OP4 E0215F 0 +OP4 E02160 0 +OP4 E02161 0 +OP4 E02162 0 +OP4 E02163 0 +OP4 E02164 0 +OP4 E02165 0 +OP4 E02166 0 +OP4 E02167 0 +OP4 E02168 0 +OP4 E02169 0 +OP4 E0216A 0 +OP4 E0216B 0 +OP4 E0216C 0 +OP4 E0216D 0 +OP4 E0216E 0 +OP4 E0216F 0 +OP4 E02170 0 +OP4 E02171 0 +OP4 E02172 0 +OP4 E02173 0 +OP4 E02174 0 +OP4 E02175 0 +OP4 E02176 0 +OP4 E02177 0 +OP4 E02178 0 +OP4 E02179 0 +OP4 E0217A 0 +OP4 E0217B 0 +OP4 E0217C 0 +OP4 E0217D 0 +OP4 E0217E 0 +OP4 E0217F 0 +OP4 E02180 0 +OP4 E02181 0 +OP4 E02182 0 +OP4 E02183 0 +OP4 E02184 0 +OP4 E02185 0 +OP4 E02186 0 +OP4 E02187 0 +OP4 E02188 0 +OP4 E02189 0 +OP4 E0218A 0 +OP4 E0218B 0 +OP4 E0218C 0 +OP4 E0218D 0 +OP4 E0218E 0 +OP4 E0218F 0 +OP4 E02190 0 +OP4 E02191 0 +OP4 E02192 0 +OP4 E02193 0 +OP4 E02194 0 +OP4 E02195 0 +OP4 E02196 0 +OP4 E02197 0 +OP4 E02198 0 +OP4 E02199 0 +OP4 E0219A 0 +OP4 E0219B 0 +OP4 E0219C 0 +OP4 E0219D 0 +OP4 E0219E 0 +OP4 E0219F 0 +OP4 E021A0 0 +OP4 E021A1 0 +OP4 E021A2 0 +OP4 E021A3 0 +OP4 E021A4 0 +OP4 E021A5 0 +OP4 E021A6 0 +OP4 E021A7 0 +OP4 E021A8 0 +OP4 E021A9 0 +OP4 E021AA 0 +OP4 E021AB 0 +OP4 E021AC 0 +OP4 E021AD 0 +OP4 E021AE 0 +OP4 E021AF 0 +OP4 E021B0 0 +OP4 E021B1 0 +OP4 E021B2 0 +OP4 E021B3 0 +OP4 E021B4 0 +OP4 E021B5 0 +OP4 E021B6 0 +OP4 E021B7 0 +OP4 E021B8 0 +OP4 E021B9 0 +OP4 E021BA 0 +OP4 E021BB 0 +OP4 E021BC 0 +OP4 E021BD 0 +OP4 E021BE 0 +OP4 E021BF 0 +OP4 E021C0 0 +OP4 E021C1 0 +OP4 E021C2 0 +OP4 E021C3 0 +OP4 E021C4 0 +OP4 E021C5 0 +OP4 E021C6 0 +OP4 E021C7 0 +OP4 E021C8 0 +OP4 E021C9 0 +OP4 E021CA 0 +OP4 E021CB 0 +OP4 E021CC 0 +OP4 E021CD 0 +OP4 E021CE 0 +OP4 E021CF 0 +OP4 E021D0 0 +OP4 E021D1 0 +OP4 E021D2 0 +OP4 E021D3 0 +OP4 E021D4 0 +OP4 E021D5 0 +OP4 E021D6 0 +OP4 E021D7 0 +OP4 E021D8 0 +OP4 E021D9 0 +OP4 E021DA 0 +OP4 E021DB 0 +OP4 E021DC 0 +OP4 E021DD 0 +OP4 E021DE 0 +OP4 E021DF 0 +OP4 E021E0 0 +OP4 E021E1 0 +OP4 E021E2 0 +OP4 E021E3 0 +OP4 E021E4 0 +OP4 E021E5 0 +OP4 E021E6 0 +OP4 E021E7 0 +OP4 E021E8 0 +OP4 E021E9 0 +OP4 E021EA 0 +OP4 E021EB 0 +OP4 E021EC 0 +OP4 E021ED 0 +OP4 E021EE 0 +OP4 E021EF 0 +OP4 E021F0 0 +OP4 E021F1 0 +OP4 E021F2 0 +OP4 E021F3 0 +OP4 E021F4 0 +OP4 E021F5 0 +OP4 E021F6 0 +OP4 E021F7 0 +OP4 E021F8 0 +OP4 E021F9 0 +OP4 E021FA 0 +OP4 E021FB 0 +OP4 E021FC 0 +OP4 E021FD 0 +OP4 E021FE 0 +OP4 E021FF 0 +OP4 E02200 0 +OP4 E02201 0 +OP4 E02202 0 +OP4 E02203 0 +OP4 E02204 0 +OP4 E02205 0 +OP4 E02206 0 +OP4 E02207 0 +OP4 E02208 0 +OP4 E02209 0 +OP4 E0220A 0 +OP4 E0220B 0 +OP4 E0220C 0 +OP4 E0220D 0 +OP4 E0220E 0 +OP4 E0220F 0 +OP4 E02210 0 +OP4 E02211 0 +OP4 E02212 0 +OP4 E02213 0 +OP4 E02214 0 +OP4 E02215 0 +OP4 E02216 0 +OP4 E02217 0 +OP4 E02218 0 +OP4 E02219 0 +OP4 E0221A 0 +OP4 E0221B 0 +OP4 E0221C 0 +OP4 E0221D 0 +OP4 E0221E 0 +OP4 E0221F 0 +OP4 E02220 0 +OP4 E02221 0 +OP4 E02222 0 +OP4 E02223 0 +OP4 E02224 0 +OP4 E02225 0 +OP4 E02226 0 +OP4 E02227 0 +OP4 E02228 0 +OP4 E02229 0 +OP4 E0222A 0 +OP4 E0222B 0 +OP4 E0222C 0 +OP4 E0222D 0 +OP4 E0222E 0 +OP4 E0222F 0 +OP4 E02230 0 +OP4 E02231 0 +OP4 E02232 0 +OP4 E02233 0 +OP4 E02234 0 +OP4 E02235 0 +OP4 E02236 0 +OP4 E02237 0 +OP4 E02238 0 +OP4 E02239 0 +OP4 E0223A 0 +OP4 E0223B 0 +OP4 E0223C 0 +OP4 E0223D 0 +OP4 E0223E 0 +OP4 E0223F 0 +OP4 E02240 0 +OP4 E02241 0 +OP4 E02242 0 +OP4 E02243 0 +OP4 E02244 0 +OP4 E02245 0 +OP4 E02246 0 +OP4 E02247 0 +OP4 E02248 0 +OP4 E02249 0 +OP4 E0224A 0 +OP4 E0224B 0 +OP4 E0224C 0 +OP4 E0224D 0 +OP4 E0224E 0 +OP4 E0224F 0 +OP4 E02250 0 +OP4 E02251 0 +OP4 E02252 0 +OP4 E02253 0 +OP4 E02254 0 +OP4 E02255 0 +OP4 E02256 0 +OP4 E02257 0 +OP4 E02258 0 +OP4 E02259 0 +OP4 E0225A 0 +OP4 E0225B 0 +OP4 E0225C 0 +OP4 E0225D 0 +OP4 E0225E 0 +OP4 E0225F 0 +OP4 E02260 0 +OP4 E02261 0 +OP4 E02262 0 +OP4 E02263 0 +OP4 E02264 0 +OP4 E02265 0 +OP4 E02266 0 +OP4 E02267 0 +OP4 E02268 0 +OP4 E02269 0 +OP4 E0226A 0 +OP4 E0226B 0 +OP4 E0226C 0 +OP4 E0226D 0 +OP4 E0226E 0 +OP4 E0226F 0 +OP4 E02270 0 +OP4 E02271 0 +OP4 E02272 0 +OP4 E02273 0 +OP4 E02274 0 +OP4 E02275 0 +OP4 E02276 0 +OP4 E02277 0 +OP4 E02278 0 +OP4 E02279 0 +OP4 E0227A 0 +OP4 E0227B 0 +OP4 E0227C 0 +OP4 E0227D 0 +OP4 E0227E 0 +OP4 E0227F 0 +OP4 E02280 0 +OP4 E02281 0 +OP4 E02282 0 +OP4 E02283 0 +OP4 E02284 0 +OP4 E02285 0 +OP4 E02286 0 +OP4 E02287 0 +OP4 E02288 0 +OP4 E02289 0 +OP4 E0228A 0 +OP4 E0228B 0 +OP4 E0228C 0 +OP4 E0228D 0 +OP4 E0228E 0 +OP4 E0228F 0 +OP4 E02290 0 +OP4 E02291 0 +OP4 E02292 0 +OP4 E02293 0 +OP4 E02294 0 +OP4 E02295 0 +OP4 E02296 0 +OP4 E02297 0 +OP4 E02298 0 +OP4 E02299 0 +OP4 E0229A 0 +OP4 E0229B 0 +OP4 E0229C 0 +OP4 E0229D 0 +OP4 E0229E 0 +OP4 E0229F 0 +OP4 E022A0 0 +OP4 E022A1 0 +OP4 E022A2 0 +OP4 E022A3 0 +OP4 E022A4 0 +OP4 E022A5 0 +OP4 E022A6 0 +OP4 E022A7 0 +OP4 E022A8 0 +OP4 E022A9 0 +OP4 E022AA 0 +OP4 E022AB 0 +OP4 E022AC 0 +OP4 E022AD 0 +OP4 E022AE 0 +OP4 E022AF 0 +OP4 E022B0 0 +OP4 E022B1 0 +OP4 E022B2 0 +OP4 E022B3 0 +OP4 E022B4 0 +OP4 E022B5 0 +OP4 E022B6 0 +OP4 E022B7 0 +OP4 E022B8 0 +OP4 E022B9 0 +OP4 E022BA 0 +OP4 E022BB 0 +OP4 E022BC 0 +OP4 E022BD 0 +OP4 E022BE 0 +OP4 E022BF 0 +OP4 E022C0 0 +OP4 E022C1 0 +OP4 E022C2 0 +OP4 E022C3 0 +OP4 E022C4 0 +OP4 E022C5 0 +OP4 E022C6 0 +OP4 E022C7 0 +OP4 E022C8 0 +OP4 E022C9 0 +OP4 E022CA 0 +OP4 E022CB 0 +OP4 E022CC 0 +OP4 E022CD 0 +OP4 E022CE 0 +OP4 E022CF 0 +OP4 E022D0 0 +OP4 E022D1 0 +OP4 E022D2 0 +OP4 E022D3 0 +OP4 E022D4 0 +OP4 E022D5 0 +OP4 E022D6 0 +OP4 E022D7 0 +OP4 E022D8 0 +OP4 E022D9 0 +OP4 E022DA 0 +OP4 E022DB 0 +OP4 E022DC 0 +OP4 E022DD 0 +OP4 E022DE 0 +OP4 E022DF 0 +OP4 E022E0 0 +OP4 E022E1 0 +OP4 E022E2 0 +OP4 E022E3 0 +OP4 E022E4 0 +OP4 E022E5 0 +OP4 E022E6 0 +OP4 E022E7 0 +OP4 E022E8 0 +OP4 E022E9 0 +OP4 E022EA 0 +OP4 E022EB 0 +OP4 E022EC 0 +OP4 E022ED 0 +OP4 E022EE 0 +OP4 E022EF 0 +OP4 E022F0 0 +OP4 E022F1 0 +OP4 E022F2 0 +OP4 E022F3 0 +OP4 E022F4 0 +OP4 E022F5 0 +OP4 E022F6 0 +OP4 E022F7 0 +OP4 E022F8 0 +OP4 E022F9 0 +OP4 E022FA 0 +OP4 E022FB 0 +OP4 E022FC 0 +OP4 E022FD 0 +OP4 E022FE 0 +OP4 E022FF 0 +OP4 E02300 0 +OP4 E02301 0 +OP4 E02302 0 +OP4 E02303 0 +OP4 E02304 0 +OP4 E02305 0 +OP4 E02306 0 +OP4 E02307 0 +OP4 E02308 0 +OP4 E02309 0 +OP4 E0230A 0 +OP4 E0230B 0 +OP4 E0230C 0 +OP4 E0230D 0 +OP4 E0230E 0 +OP4 E0230F 0 +OP4 E02310 0 +OP4 E02311 0 +OP4 E02312 0 +OP4 E02313 0 +OP4 E02314 0 +OP4 E02315 0 +OP4 E02316 0 +OP4 E02317 0 +OP4 E02318 0 +OP4 E02319 0 +OP4 E0231A 0 +OP4 E0231B 0 +OP4 E0231C 0 +OP4 E0231D 0 +OP4 E0231E 0 +OP4 E0231F 0 +OP4 E02320 0 +OP4 E02321 0 +OP4 E02322 0 +OP4 E02323 0 +OP4 E02324 0 +OP4 E02325 0 +OP4 E02326 0 +OP4 E02327 0 +OP4 E02328 0 +OP4 E02329 0 +OP4 E0232A 0 +OP4 E0232B 0 +OP4 E0232C 0 +OP4 E0232D 0 +OP4 E0232E 0 +OP4 E0232F 0 +OP4 E02330 0 +OP4 E02331 0 +OP4 E02332 0 +OP4 E02333 0 +OP4 E02334 0 +OP4 E02335 0 +OP4 E02336 0 +OP4 E02337 0 +OP4 E02338 0 +OP4 E02339 0 +OP4 E0233A 0 +OP4 E0233B 0 +OP4 E0233C 0 +OP4 E0233D 0 +OP4 E0233E 0 +OP4 E0233F 0 +OP4 E02340 0 +OP4 E02341 0 +OP4 E02342 0 +OP4 E02343 0 +OP4 E02344 0 +OP4 E02345 0 +OP4 E02346 0 +OP4 E02347 0 +OP4 E02348 0 +OP4 E02349 0 +OP4 E0234A 0 +OP4 E0234B 0 +OP4 E0234C 0 +OP4 E0234D 0 +OP4 E0234E 0 +OP4 E0234F 0 +OP4 E02350 0 +OP4 E02351 0 +OP4 E02352 0 +OP4 E02353 0 +OP4 E02354 0 +OP4 E02355 0 +OP4 E02356 0 +OP4 E02357 0 +OP4 E02358 0 +OP4 E02359 0 +OP4 E0235A 0 +OP4 E0235B 0 +OP4 E0235C 0 +OP4 E0235D 0 +OP4 E0235E 0 +OP4 E0235F 0 +OP4 E02360 0 +OP4 E02361 0 +OP4 E02362 0 +OP4 E02363 0 +OP4 E02364 0 +OP4 E02365 0 +OP4 E02366 0 +OP4 E02367 0 +OP4 E02368 0 +OP4 E02369 0 +OP4 E0236A 0 +OP4 E0236B 0 +OP4 E0236C 0 +OP4 E0236D 0 +OP4 E0236E 0 +OP4 E0236F 0 +OP4 E02370 0 +OP4 E02371 0 +OP4 E02372 0 +OP4 E02373 0 +OP4 E02374 0 +OP4 E02375 0 +OP4 E02376 0 +OP4 E02377 0 +OP4 E02378 0 +OP4 E02379 0 +OP4 E0237A 0 +OP4 E0237B 0 +OP4 E0237C 0 +OP4 E0237D 0 +OP4 E0237E 0 +OP4 E0237F 0 +OP4 E02380 0 +OP4 E02381 0 +OP4 E02382 0 +OP4 E02383 0 +OP4 E02384 0 +OP4 E02385 0 +OP4 E02386 0 +OP4 E02387 0 +OP4 E02388 0 +OP4 E02389 0 +OP4 E0238A 0 +OP4 E0238B 0 +OP4 E0238C 0 +OP4 E0238D 0 +OP4 E0238E 0 +OP4 E0238F 0 +OP4 E02390 0 +OP4 E02391 0 +OP4 E02392 0 +OP4 E02393 0 +OP4 E02394 0 +OP4 E02395 0 +OP4 E02396 0 +OP4 E02397 0 +OP4 E02398 0 +OP4 E02399 0 +OP4 E0239A 0 +OP4 E0239B 0 +OP4 E0239C 0 +OP4 E0239D 0 +OP4 E0239E 0 +OP4 E0239F 0 +OP4 E023A0 0 +OP4 E023A1 0 +OP4 E023A2 0 +OP4 E023A3 0 +OP4 E023A4 0 +OP4 E023A5 0 +OP4 E023A6 0 +OP4 E023A7 0 +OP4 E023A8 0 +OP4 E023A9 0 +OP4 E023AA 0 +OP4 E023AB 0 +OP4 E023AC 0 +OP4 E023AD 0 +OP4 E023AE 0 +OP4 E023AF 0 +OP4 E023B0 0 +OP4 E023B1 0 +OP4 E023B2 0 +OP4 E023B3 0 +OP4 E023B4 0 +OP4 E023B5 0 +OP4 E023B6 0 +OP4 E023B7 0 +OP4 E023B8 0 +OP4 E023B9 0 +OP4 E023BA 0 +OP4 E023BB 0 +OP4 E023BC 0 +OP4 E023BD 0 +OP4 E023BE 0 +OP4 E023BF 0 +OP4 E023C0 0 +OP4 E023C1 0 +OP4 E023C2 0 +OP4 E023C3 0 +OP4 E023C4 0 +OP4 E023C5 0 +OP4 E023C6 0 +OP4 E023C7 0 +OP4 E023C8 0 +OP4 E023C9 0 +OP4 E023CA 0 +OP4 E023CB 0 +OP4 E023CC 0 +OP4 E023CD 0 +OP4 E023CE 0 +OP4 E023CF 0 +OP4 E023D0 0 +OP4 E023D1 0 +OP4 E023D2 0 +OP4 E023D3 0 +OP4 E023D4 0 +OP4 E023D5 0 +OP4 E023D6 0 +OP4 E023D7 0 +OP4 E023D8 0 +OP4 E023D9 0 +OP4 E023DA 0 +OP4 E023DB 0 +OP4 E023DC 0 +OP4 E023DD 0 +OP4 E023DE 0 +OP4 E023DF 0 +OP4 E023E0 0 +OP4 E023E1 0 +OP4 E023E2 0 +OP4 E023E3 0 +OP4 E023E4 0 +OP4 E023E5 0 +OP4 E023E6 0 +OP4 E023E7 0 +OP4 E023E8 0 +OP4 E023E9 0 +OP4 E023EA 0 +OP4 E023EB 0 +OP4 E023EC 0 +OP4 E023ED 0 +OP4 E023EE 0 +OP4 E023EF 0 +OP4 E023F0 0 +OP4 E023F1 0 +OP4 E023F2 0 +OP4 E023F3 0 +OP4 E023F4 0 +OP4 E023F5 0 +OP4 E023F6 0 +OP4 E023F7 0 +OP4 E023F8 0 +OP4 E023F9 0 +OP4 E023FA 0 +OP4 E023FB 0 +OP4 E023FC 0 +OP4 E023FD 0 +OP4 E023FE 0 +OP4 E023FF 0 +OP4 E02400 0 +OP4 E02401 0 +OP4 E02402 0 +OP4 E02403 0 +OP4 E02404 0 +OP4 E02405 0 +OP4 E02406 0 +OP4 E02407 0 +OP4 E02408 0 +OP4 E02409 0 +OP4 E0240A 0 +OP4 E0240B 0 +OP4 E0240C 0 +OP4 E0240D 0 +OP4 E0240E 0 +OP4 E0240F 0 +OP4 E02410 0 +OP4 E02411 0 +OP4 E02412 0 +OP4 E02413 0 +OP4 E02414 0 +OP4 E02415 0 +OP4 E02416 0 +OP4 E02417 0 +OP4 E02418 0 +OP4 E02419 0 +OP4 E0241A 0 +OP4 E0241B 0 +OP4 E0241C 0 +OP4 E0241D 0 +OP4 E0241E 0 +OP4 E0241F 0 +OP4 E02420 0 +OP4 E02421 0 +OP4 E02422 0 +OP4 E02423 0 +OP4 E02424 0 +OP4 E02425 0 +OP4 E02426 0 +OP4 E02427 0 +OP4 E02428 0 +OP4 E02429 0 +OP4 E0242A 0 +OP4 E0242B 0 +OP4 E0242C 0 +OP4 E0242D 0 +OP4 E0242E 0 +OP4 E0242F 0 +OP4 E02430 0 +OP4 E02431 0 +OP4 E02432 0 +OP4 E02433 0 +OP4 E02434 0 +OP4 E02435 0 +OP4 E02436 0 +OP4 E02437 0 +OP4 E02438 0 +OP4 E02439 0 +OP4 E0243A 0 +OP4 E0243B 0 +OP4 E0243C 0 +OP4 E0243D 0 +OP4 E0243E 0 +OP4 E0243F 0 +OP4 E02440 0 +OP4 E02441 0 +OP4 E02442 0 +OP4 E02443 0 +OP4 E02444 0 +OP4 E02445 0 +OP4 E02446 0 +OP4 E02447 0 +OP4 E02448 0 +OP4 E02449 0 +OP4 E0244A 0 +OP4 E0244B 0 +OP4 E0244C 0 +OP4 E0244D 0 +OP4 E0244E 0 +OP4 E0244F 0 +OP4 E02450 0 +OP4 E02451 0 +OP4 E02452 0 +OP4 E02453 0 +OP4 E02454 0 +OP4 E02455 0 +OP4 E02456 0 +OP4 E02457 0 +OP4 E02458 0 +OP4 E02459 0 +OP4 E0245A 0 +OP4 E0245B 0 +OP4 E0245C 0 +OP4 E0245D 0 +OP4 E0245E 0 +OP4 E0245F 0 +OP4 E02460 0 +OP4 E02461 0 +OP4 E02462 0 +OP4 E02463 0 +OP4 E02464 0 +OP4 E02465 0 +OP4 E02466 0 +OP4 E02467 0 +OP4 E02468 0 +OP4 E02469 0 +OP4 E0246A 0 +OP4 E0246B 0 +OP4 E0246C 0 +OP4 E0246D 0 +OP4 E0246E 0 +OP4 E0246F 0 +OP4 E02470 0 +OP4 E02471 0 +OP4 E02472 0 +OP4 E02473 0 +OP4 E02474 0 +OP4 E02475 0 +OP4 E02476 0 +OP4 E02477 0 +OP4 E02478 0 +OP4 E02479 0 +OP4 E0247A 0 +OP4 E0247B 0 +OP4 E0247C 0 +OP4 E0247D 0 +OP4 E0247E 0 +OP4 E0247F 0 +OP4 E02480 0 +OP4 E02481 0 +OP4 E02482 0 +OP4 E02483 0 +OP4 E02484 0 +OP4 E02485 0 +OP4 E02486 0 +OP4 E02487 0 +OP4 E02488 0 +OP4 E02489 0 +OP4 E0248A 0 +OP4 E0248B 0 +OP4 E0248C 0 +OP4 E0248D 0 +OP4 E0248E 0 +OP4 E0248F 0 +OP4 E02490 0 +OP4 E02491 0 +OP4 E02492 0 +OP4 E02493 0 +OP4 E02494 0 +OP4 E02495 0 +OP4 E02496 0 +OP4 E02497 0 +OP4 E02498 0 +OP4 E02499 0 +OP4 E0249A 0 +OP4 E0249B 0 +OP4 E0249C 0 +OP4 E0249D 0 +OP4 E0249E 0 +OP4 E0249F 0 +OP4 E024A0 0 +OP4 E024A1 0 +OP4 E024A2 0 +OP4 E024A3 0 +OP4 E024A4 0 +OP4 E024A5 0 +OP4 E024A6 0 +OP4 E024A7 0 +OP4 E024A8 0 +OP4 E024A9 0 +OP4 E024AA 0 +OP4 E024AB 0 +OP4 E024AC 0 +OP4 E024AD 0 +OP4 E024AE 0 +OP4 E024AF 0 +OP4 E024B0 0 +OP4 E024B1 0 +OP4 E024B2 0 +OP4 E024B3 0 +OP4 E024B4 0 +OP4 E024B5 0 +OP4 E024B6 0 +OP4 E024B7 0 +OP4 E024B8 0 +OP4 E024B9 0 +OP4 E024BA 0 +OP4 E024BB 0 +OP4 E024BC 0 +OP4 E024BD 0 +OP4 E024BE 0 +OP4 E024BF 0 +OP4 E024C0 0 +OP4 E024C1 0 +OP4 E024C2 0 +OP4 E024C3 0 +OP4 E024C4 0 +OP4 E024C5 0 +OP4 E024C6 0 +OP4 E024C7 0 +OP4 E024C8 0 +OP4 E024C9 0 +OP4 E024CA 0 +OP4 E024CB 0 +OP4 E024CC 0 +OP4 E024CD 0 +OP4 E024CE 0 +OP4 E024CF 0 +OP4 E024D0 0 +OP4 E024D1 0 +OP4 E024D2 0 +OP4 E024D3 0 +OP4 E024D4 0 +OP4 E024D5 0 +OP4 E024D6 0 +OP4 E024D7 0 +OP4 E024D8 0 +OP4 E024D9 0 +OP4 E024DA 0 +OP4 E024DB 0 +OP4 E024DC 0 +OP4 E024DD 0 +OP4 E024DE 0 +OP4 E024DF 0 +OP4 E024E0 0 +OP4 E024E1 0 +OP4 E024E2 0 +OP4 E024E3 0 +OP4 E024E4 0 +OP4 E024E5 0 +OP4 E024E6 0 +OP4 E024E7 0 +OP4 E024E8 0 +OP4 E024E9 0 +OP4 E024EA 0 +OP4 E024EB 0 +OP4 E024EC 0 +OP4 E024ED 0 +OP4 E024EE 0 +OP4 E024EF 0 +OP4 E024F0 0 +OP4 E024F1 0 +OP4 E024F2 0 +OP4 E024F3 0 +OP4 E024F4 0 +OP4 E024F5 0 +OP4 E024F6 0 +OP4 E024F7 0 +OP4 E024F8 0 +OP4 E024F9 0 +OP4 E024FA 0 +OP4 E024FB 0 +OP4 E024FC 0 +OP4 E024FD 0 +OP4 E024FE 0 +OP4 E024FF 0 +OP4 E02500 0 +OP4 E02501 0 +OP4 E02502 0 +OP4 E02503 0 +OP4 E02504 0 +OP4 E02505 0 +OP4 E02506 0 +OP4 E02507 0 +OP4 E02508 0 +OP4 E02509 0 +OP4 E0250A 0 +OP4 E0250B 0 +OP4 E0250C 0 +OP4 E0250D 0 +OP4 E0250E 0 +OP4 E0250F 0 +OP4 E02510 0 +OP4 E02511 0 +OP4 E02512 0 +OP4 E02513 0 +OP4 E02514 0 +OP4 E02515 0 +OP4 E02516 0 +OP4 E02517 0 +OP4 E02518 0 +OP4 E02519 0 +OP4 E0251A 0 +OP4 E0251B 0 +OP4 E0251C 0 +OP4 E0251D 0 +OP4 E0251E 0 +OP4 E0251F 0 +OP4 E02520 0 +OP4 E02521 0 +OP4 E02522 0 +OP4 E02523 0 +OP4 E02524 0 +OP4 E02525 0 +OP4 E02526 0 +OP4 E02527 0 +OP4 E02528 0 +OP4 E02529 0 +OP4 E0252A 0 +OP4 E0252B 0 +OP4 E0252C 0 +OP4 E0252D 0 +OP4 E0252E 0 +OP4 E0252F 0 +OP4 E02530 0 +OP4 E02531 0 +OP4 E02532 0 +OP4 E02533 0 +OP4 E02534 0 +OP4 E02535 0 +OP4 E02536 0 +OP4 E02537 0 +OP4 E02538 0 +OP4 E02539 0 +OP4 E0253A 0 +OP4 E0253B 0 +OP4 E0253C 0 +OP4 E0253D 0 +OP4 E0253E 0 +OP4 E0253F 0 +OP4 E02540 0 +OP4 E02541 0 +OP4 E02542 0 +OP4 E02543 0 +OP4 E02544 0 +OP4 E02545 0 +OP4 E02546 0 +OP4 E02547 0 +OP4 E02548 0 +OP4 E02549 0 +OP4 E0254A 0 +OP4 E0254B 0 +OP4 E0254C 0 +OP4 E0254D 0 +OP4 E0254E 0 +OP4 E0254F 0 +OP4 E02550 0 +OP4 E02551 0 +OP4 E02552 0 +OP4 E02553 0 +OP4 E02554 0 +OP4 E02555 0 +OP4 E02556 0 +OP4 E02557 0 +OP4 E02558 0 +OP4 E02559 0 +OP4 E0255A 0 +OP4 E0255B 0 +OP4 E0255C 0 +OP4 E0255D 0 +OP4 E0255E 0 +OP4 E0255F 0 +OP4 E02560 0 +OP4 E02561 0 +OP4 E02562 0 +OP4 E02563 0 +OP4 E02564 0 +OP4 E02565 0 +OP4 E02566 0 +OP4 E02567 0 +OP4 E02568 0 +OP4 E02569 0 +OP4 E0256A 0 +OP4 E0256B 0 +OP4 E0256C 0 +OP4 E0256D 0 +OP4 E0256E 0 +OP4 E0256F 0 +OP4 E02570 0 +OP4 E02571 0 +OP4 E02572 0 +OP4 E02573 0 +OP4 E02574 0 +OP4 E02575 0 +OP4 E02576 0 +OP4 E02577 0 +OP4 E02578 0 +OP4 E02579 0 +OP4 E0257A 0 +OP4 E0257B 0 +OP4 E0257C 0 +OP4 E0257D 0 +OP4 E0257E 0 +OP4 E0257F 0 +OP4 E02580 0 +OP4 E02581 0 +OP4 E02582 0 +OP4 E02583 0 +OP4 E02584 0 +OP4 E02585 0 +OP4 E02586 0 +OP4 E02587 0 +OP4 E02588 0 +OP4 E02589 0 +OP4 E0258A 0 +OP4 E0258B 0 +OP4 E0258C 0 +OP4 E0258D 0 +OP4 E0258E 0 +OP4 E0258F 0 +OP4 E02590 0 +OP4 E02591 0 +OP4 E02592 0 +OP4 E02593 0 +OP4 E02594 0 +OP4 E02595 0 +OP4 E02596 0 +OP4 E02597 0 +OP4 E02598 0 +OP4 E02599 0 +OP4 E0259A 0 +OP4 E0259B 0 +OP4 E0259C 0 +OP4 E0259D 0 +OP4 E0259E 0 +OP4 E0259F 0 +OP4 E025A0 0 +OP4 E025A1 0 +OP4 E025A2 0 +OP4 E025A3 0 +OP4 E025A4 0 +OP4 E025A5 0 +OP4 E025A6 0 +OP4 E025A7 0 +OP4 E025A8 0 +OP4 E025A9 0 +OP4 E025AA 0 +OP4 E025AB 0 +OP4 E025AC 0 +OP4 E025AD 0 +OP4 E025AE 0 +OP4 E025AF 0 +OP4 E025B0 0 +OP4 E025B1 0 +OP4 E025B2 0 +OP4 E025B3 0 +OP4 E025B4 0 +OP4 E025B5 0 +OP4 E025B6 0 +OP4 E025B7 0 +OP4 E025B8 0 +OP4 E025B9 0 +OP4 E025BA 0 +OP4 E025BB 0 +OP4 E025BC 0 +OP4 E025BD 0 +OP4 E025BE 0 +OP4 E025BF 0 +OP4 E025C0 0 +OP4 E025C1 0 +OP4 E025C2 0 +OP4 E025C3 0 +OP4 E025C4 0 +OP4 E025C5 0 +OP4 E025C6 0 +OP4 E025C7 0 +OP4 E025C8 0 +OP4 E025C9 0 +OP4 E025CA 0 +OP4 E025CB 0 +OP4 E025CC 0 +OP4 E025CD 0 +OP4 E025CE 0 +OP4 E025CF 0 +OP4 E025D0 0 +OP4 E025D1 0 +OP4 E025D2 0 +OP4 E025D3 0 +OP4 E025D4 0 +OP4 E025D5 0 +OP4 E025D6 0 +OP4 E025D7 0 +OP4 E025D8 0 +OP4 E025D9 0 +OP4 E025DA 0 +OP4 E025DB 0 +OP4 E025DC 0 +OP4 E025DD 0 +OP4 E025DE 0 +OP4 E025DF 0 +OP4 E025E0 0 +OP4 E025E1 0 +OP4 E025E2 0 +OP4 E025E3 0 +OP4 E025E4 0 +OP4 E025E5 0 +OP4 E025E6 0 +OP4 E025E7 0 +OP4 E025E8 0 +OP4 E025E9 0 +OP4 E025EA 0 +OP4 E025EB 0 +OP4 E025EC 0 +OP4 E025ED 0 +OP4 E025EE 0 +OP4 E025EF 0 +OP4 E025F0 0 +OP4 E025F1 0 +OP4 E025F2 0 +OP4 E025F3 0 +OP4 E025F4 0 +OP4 E025F5 0 +OP4 E025F6 0 +OP4 E025F7 0 +OP4 E025F8 0 +OP4 E025F9 0 +OP4 E025FA 0 +OP4 E025FB 0 +OP4 E025FC 0 +OP4 E025FD 0 +OP4 E025FE 0 +OP4 E025FF 0 +OP4 E02600 0 +OP4 E02601 0 +OP4 E02602 0 +OP4 E02603 0 +OP4 E02604 0 +OP4 E02605 0 +OP4 E02606 0 +OP4 E02607 0 +OP4 E02608 0 +OP4 E02609 0 +OP4 E0260A 0 +OP4 E0260B 0 +OP4 E0260C 0 +OP4 E0260D 0 +OP4 E0260E 0 +OP4 E0260F 0 +OP4 E02610 0 +OP4 E02611 0 +OP4 E02612 0 +OP4 E02613 0 +OP4 E02614 0 +OP4 E02615 0 +OP4 E02616 0 +OP4 E02617 0 +OP4 E02618 0 +OP4 E02619 0 +OP4 E0261A 0 +OP4 E0261B 0 +OP4 E0261C 0 +OP4 E0261D 0 +OP4 E0261E 0 +OP4 E0261F 0 +OP4 E02620 0 +OP4 E02621 0 +OP4 E02622 0 +OP4 E02623 0 +OP4 E02624 0 +OP4 E02625 0 +OP4 E02626 0 +OP4 E02627 0 +OP4 E02628 0 +OP4 E02629 0 +OP4 E0262A 0 +OP4 E0262B 0 +OP4 E0262C 0 +OP4 E0262D 0 +OP4 E0262E 0 +OP4 E0262F 0 +OP4 E02630 0 +OP4 E02631 0 +OP4 E02632 0 +OP4 E02633 0 +OP4 E02634 0 +OP4 E02635 0 +OP4 E02636 0 +OP4 E02637 0 +OP4 E02638 0 +OP4 E02639 0 +OP4 E0263A 0 +OP4 E0263B 0 +OP4 E0263C 0 +OP4 E0263D 0 +OP4 E0263E 0 +OP4 E0263F 0 +OP4 E02640 0 +OP4 E02641 0 +OP4 E02642 0 +OP4 E02643 0 +OP4 E02644 0 +OP4 E02645 0 +OP4 E02646 0 +OP4 E02647 0 +OP4 E02648 0 +OP4 E02649 0 +OP4 E0264A 0 +OP4 E0264B 0 +OP4 E0264C 0 +OP4 E0264D 0 +OP4 E0264E 0 +OP4 E0264F 0 +OP4 E02650 0 +OP4 E02651 0 +OP4 E02652 0 +OP4 E02653 0 +OP4 E02654 0 +OP4 E02655 0 +OP4 E02656 0 +OP4 E02657 0 +OP4 E02658 0 +OP4 E02659 0 +OP4 E0265A 0 +OP4 E0265B 0 +OP4 E0265C 0 +OP4 E0265D 0 +OP4 E0265E 0 +OP4 E0265F 0 +OP4 E02660 0 +OP4 E02661 0 +OP4 E02662 0 +OP4 E02663 0 +OP4 E02664 0 +OP4 E02665 0 +OP4 E02666 0 +OP4 E02667 0 +OP4 E02668 0 +OP4 E02669 0 +OP4 E0266A 0 +OP4 E0266B 0 +OP4 E0266C 0 +OP4 E0266D 0 +OP4 E0266E 0 +OP4 E0266F 0 +OP4 E02670 0 +OP4 E02671 0 +OP4 E02672 0 +OP4 E02673 0 +OP4 E02674 0 +OP4 E02675 0 +OP4 E02676 0 +OP4 E02677 0 +OP4 E02678 0 +OP4 E02679 0 +OP4 E0267A 0 +OP4 E0267B 0 +OP4 E0267C 0 +OP4 E0267D 0 +OP4 E0267E 0 +OP4 E0267F 0 +OP4 E02680 0 +OP4 E02681 0 +OP4 E02682 0 +OP4 E02683 0 +OP4 E02684 0 +OP4 E02685 0 +OP4 E02686 0 +OP4 E02687 0 +OP4 E02688 0 +OP4 E02689 0 +OP4 E0268A 0 +OP4 E0268B 0 +OP4 E0268C 0 +OP4 E0268D 0 +OP4 E0268E 0 +OP4 E0268F 0 +OP4 E02690 0 +OP4 E02691 0 +OP4 E02692 0 +OP4 E02693 0 +OP4 E02694 0 +OP4 E02695 0 +OP4 E02696 0 +OP4 E02697 0 +OP4 E02698 0 +OP4 E02699 0 +OP4 E0269A 0 +OP4 E0269B 0 +OP4 E0269C 0 +OP4 E0269D 0 +OP4 E0269E 0 +OP4 E0269F 0 +OP4 E026A0 0 +OP4 E026A1 0 +OP4 E026A2 0 +OP4 E026A3 0 +OP4 E026A4 0 +OP4 E026A5 0 +OP4 E026A6 0 +OP4 E026A7 0 +OP4 E026A8 0 +OP4 E026A9 0 +OP4 E026AA 0 +OP4 E026AB 0 +OP4 E026AC 0 +OP4 E026AD 0 +OP4 E026AE 0 +OP4 E026AF 0 +OP4 E026B0 0 +OP4 E026B1 0 +OP4 E026B2 0 +OP4 E026B3 0 +OP4 E026B4 0 +OP4 E026B5 0 +OP4 E026B6 0 +OP4 E026B7 0 +OP4 E026B8 0 +OP4 E026B9 0 +OP4 E026BA 0 +OP4 E026BB 0 +OP4 E026BC 0 +OP4 E026BD 0 +OP4 E026BE 0 +OP4 E026BF 0 +OP4 E026C0 0 +OP4 E026C1 0 +OP4 E026C2 0 +OP4 E026C3 0 +OP4 E026C4 0 +OP4 E026C5 0 +OP4 E026C6 0 +OP4 E026C7 0 +OP4 E026C8 0 +OP4 E026C9 0 +OP4 E026CA 0 +OP4 E026CB 0 +OP4 E026CC 0 +OP4 E026CD 0 +OP4 E026CE 0 +OP4 E026CF 0 +OP4 E026D0 0 +OP4 E026D1 0 +OP4 E026D2 0 +OP4 E026D3 0 +OP4 E026D4 0 +OP4 E026D5 0 +OP4 E026D6 0 +OP4 E026D7 0 +OP4 E026D8 0 +OP4 E026D9 0 +OP4 E026DA 0 +OP4 E026DB 0 +OP4 E026DC 0 +OP4 E026DD 0 +OP4 E026DE 0 +OP4 E026DF 0 +OP4 E026E0 0 +OP4 E026E1 0 +OP4 E026E2 0 +OP4 E026E3 0 +OP4 E026E4 0 +OP4 E026E5 0 +OP4 E026E6 0 +OP4 E026E7 0 +OP4 E026E8 0 +OP4 E026E9 0 +OP4 E026EA 0 +OP4 E026EB 0 +OP4 E026EC 0 +OP4 E026ED 0 +OP4 E026EE 0 +OP4 E026EF 0 +OP4 E026F0 0 +OP4 E026F1 0 +OP4 E026F2 0 +OP4 E026F3 0 +OP4 E026F4 0 +OP4 E026F5 0 +OP4 E026F6 0 +OP4 E026F7 0 +OP4 E026F8 0 +OP4 E026F9 0 +OP4 E026FA 0 +OP4 E026FB 0 +OP4 E026FC 0 +OP4 E026FD 0 +OP4 E026FE 0 +OP4 E026FF 0 +OP4 E02700 0 +OP4 E02701 0 +OP4 E02702 0 +OP4 E02703 0 +OP4 E02704 0 +OP4 E02705 0 +OP4 E02706 0 +OP4 E02707 0 +OP4 E02708 0 +OP4 E02709 0 +OP4 E0270A 0 +OP4 E0270B 0 +OP4 E0270C 0 +OP4 E0270D 0 +OP4 E0270E 0 +OP4 E0270F 0 +OP4 E02710 0 +OP4 E02711 0 +OP4 E02712 0 +OP4 E02713 0 +OP4 E02714 0 +OP4 E02715 0 +OP4 E02716 0 +OP4 E02717 0 +OP4 E02718 0 +OP4 E02719 0 +OP4 E0271A 0 +OP4 E0271B 0 +OP4 E0271C 0 +OP4 E0271D 0 +OP4 E0271E 0 +OP4 E0271F 0 +OP4 E02720 0 +OP4 E02721 0 +OP4 E02722 0 +OP4 E02723 0 +OP4 E02724 0 +OP4 E02725 0 +OP4 E02726 0 +OP4 E02727 0 +OP4 E02728 0 +OP4 E02729 0 +OP4 E0272A 0 +OP4 E0272B 0 +OP4 E0272C 0 +OP4 E0272D 0 +OP4 E0272E 0 +OP4 E0272F 0 +OP4 E02730 0 +OP4 E02731 0 +OP4 E02732 0 +OP4 E02733 0 +OP4 E02734 0 +OP4 E02735 0 +OP4 E02736 0 +OP4 E02737 0 +OP4 E02738 0 +OP4 E02739 0 +OP4 E0273A 0 +OP4 E0273B 0 +OP4 E0273C 0 +OP4 E0273D 0 +OP4 E0273E 0 +OP4 E0273F 0 +OP4 E02740 0 +OP4 E02741 0 +OP4 E02742 0 +OP4 E02743 0 +OP4 E02744 0 +OP4 E02745 0 +OP4 E02746 0 +OP4 E02747 0 +OP4 E02748 0 +OP4 E02749 0 +OP4 E0274A 0 +OP4 E0274B 0 +OP4 E0274C 0 +OP4 E0274D 0 +OP4 E0274E 0 +OP4 E0274F 0 +OP4 E02750 0 +OP4 E02751 0 +OP4 E02752 0 +OP4 E02753 0 +OP4 E02754 0 +OP4 E02755 0 +OP4 E02756 0 +OP4 E02757 0 +OP4 E02758 0 +OP4 E02759 0 +OP4 E0275A 0 +OP4 E0275B 0 +OP4 E0275C 0 +OP4 E0275D 0 +OP4 E0275E 0 +OP4 E0275F 0 +OP4 E02760 0 +OP4 E02761 0 +OP4 E02762 0 +OP4 E02763 0 +OP4 E02764 0 +OP4 E02765 0 +OP4 E02766 0 +OP4 E02767 0 +OP4 E02768 0 +OP4 E02769 0 +OP4 E0276A 0 +OP4 E0276B 0 +OP4 E0276C 0 +OP4 E0276D 0 +OP4 E0276E 0 +OP4 E0276F 0 +OP4 E02770 0 +OP4 E02771 0 +OP4 E02772 0 +OP4 E02773 0 +OP4 E02774 0 +OP4 E02775 0 +OP4 E02776 0 +OP4 E02777 0 +OP4 E02778 0 +OP4 E02779 0 +OP4 E0277A 0 +OP4 E0277B 0 +OP4 E0277C 0 +OP4 E0277D 0 +OP4 E0277E 0 +OP4 E0277F 0 +OP4 E02780 0 +OP4 E02781 0 +OP4 E02782 0 +OP4 E02783 0 +OP4 E02784 0 +OP4 E02785 0 +OP4 E02786 0 +OP4 E02787 0 +OP4 E02788 0 +OP4 E02789 0 +OP4 E0278A 0 +OP4 E0278B 0 +OP4 E0278C 0 +OP4 E0278D 0 +OP4 E0278E 0 +OP4 E0278F 0 +OP4 E02790 0 +OP4 E02791 0 +OP4 E02792 0 +OP4 E02793 0 +OP4 E02794 0 +OP4 E02795 0 +OP4 E02796 0 +OP4 E02797 0 +OP4 E02798 0 +OP4 E02799 0 +OP4 E0279A 0 +OP4 E0279B 0 +OP4 E0279C 0 +OP4 E0279D 0 +OP4 E0279E 0 +OP4 E0279F 0 +OP4 E027A0 0 +OP4 E027A1 0 +OP4 E027A2 0 +OP4 E027A3 0 +OP4 E027A4 0 +OP4 E027A5 0 +OP4 E027A6 0 +OP4 E027A7 0 +OP4 E027A8 0 +OP4 E027A9 0 +OP4 E027AA 0 +OP4 E027AB 0 +OP4 E027AC 0 +OP4 E027AD 0 +OP4 E027AE 0 +OP4 E027AF 0 +OP4 E027B0 0 +OP4 E027B1 0 +OP4 E027B2 0 +OP4 E027B3 0 +OP4 E027B4 0 +OP4 E027B5 0 +OP4 E027B6 0 +OP4 E027B7 0 +OP4 E027B8 0 +OP4 E027B9 0 +OP4 E027BA 0 +OP4 E027BB 0 +OP4 E027BC 0 +OP4 E027BD 0 +OP4 E027BE 0 +OP4 E027BF 0 +OP4 E027C0 0 +OP4 E027C1 0 +OP4 E027C2 0 +OP4 E027C3 0 +OP4 E027C4 0 +OP4 E027C5 0 +OP4 E027C6 0 +OP4 E027C7 0 +OP4 E027C8 0 +OP4 E027C9 0 +OP4 E027CA 0 +OP4 E027CB 0 +OP4 E027CC 0 +OP4 E027CD 0 +OP4 E027CE 0 +OP4 E027CF 0 +OP4 E027D0 0 +OP4 E027D1 0 +OP4 E027D2 0 +OP4 E027D3 0 +OP4 E027D4 0 +OP4 E027D5 0 +OP4 E027D6 0 +OP4 E027D7 0 +OP4 E027D8 0 +OP4 E027D9 0 +OP4 E027DA 0 +OP4 E027DB 0 +OP4 E027DC 0 +OP4 E027DD 0 +OP4 E027DE 0 +OP4 E027DF 0 +OP4 E027E0 0 +OP4 E027E1 0 +OP4 E027E2 0 +OP4 E027E3 0 +OP4 E027E4 0 +OP4 E027E5 0 +OP4 E027E6 0 +OP4 E027E7 0 +OP4 E027E8 0 +OP4 E027E9 0 +OP4 E027EA 0 +OP4 E027EB 0 +OP4 E027EC 0 +OP4 E027ED 0 +OP4 E027EE 0 +OP4 E027EF 0 +OP4 E027F0 0 +OP4 E027F1 0 +OP4 E027F2 0 +OP4 E027F3 0 +OP4 E027F4 0 +OP4 E027F5 0 +OP4 E027F6 0 +OP4 E027F7 0 +OP4 E027F8 0 +OP4 E027F9 0 +OP4 E027FA 0 +OP4 E027FB 0 +OP4 E027FC 0 +OP4 E027FD 0 +OP4 E027FE 0 +OP4 E027FF 0 +OP4 E02800 0 +OP4 E02801 0 +OP4 E02802 0 +OP4 E02803 0 +OP4 E02804 0 +OP4 E02805 0 +OP4 E02806 0 +OP4 E02807 0 +OP4 E02808 0 +OP4 E02809 0 +OP4 E0280A 0 +OP4 E0280B 0 +OP4 E0280C 0 +OP4 E0280D 0 +OP4 E0280E 0 +OP4 E0280F 0 +OP4 E02810 0 +OP4 E02811 0 +OP4 E02812 0 +OP4 E02813 0 +OP4 E02814 0 +OP4 E02815 0 +OP4 E02816 0 +OP4 E02817 0 +OP4 E02818 0 +OP4 E02819 0 +OP4 E0281A 0 +OP4 E0281B 0 +OP4 E0281C 0 +OP4 E0281D 0 +OP4 E0281E 0 +OP4 E0281F 0 +OP4 E02820 0 +OP4 E02821 0 +OP4 E02822 0 +OP4 E02823 0 +OP4 E02824 0 +OP4 E02825 0 +OP4 E02826 0 +OP4 E02827 0 +OP4 E02828 0 +OP4 E02829 0 +OP4 E0282A 0 +OP4 E0282B 0 +OP4 E0282C 0 +OP4 E0282D 0 +OP4 E0282E 0 +OP4 E0282F 0 +OP4 E02830 0 +OP4 E02831 0 +OP4 E02832 0 +OP4 E02833 0 +OP4 E02834 0 +OP4 E02835 0 +OP4 E02836 0 +OP4 E02837 0 +OP4 E02838 0 +OP4 E02839 0 +OP4 E0283A 0 +OP4 E0283B 0 +OP4 E0283C 0 +OP4 E0283D 0 +OP4 E0283E 0 +OP4 E0283F 0 +OP4 E02840 0 +OP4 E02841 0 +OP4 E02842 0 +OP4 E02843 0 +OP4 E02844 0 +OP4 E02845 0 +OP4 E02846 0 +OP4 E02847 0 +OP4 E02848 0 +OP4 E02849 0 +OP4 E0284A 0 +OP4 E0284B 0 +OP4 E0284C 0 +OP4 E0284D 0 +OP4 E0284E 0 +OP4 E0284F 0 +OP4 E02850 0 +OP4 E02851 0 +OP4 E02852 0 +OP4 E02853 0 +OP4 E02854 0 +OP4 E02855 0 +OP4 E02856 0 +OP4 E02857 0 +OP4 E02858 0 +OP4 E02859 0 +OP4 E0285A 0 +OP4 E0285B 0 +OP4 E0285C 0 +OP4 E0285D 0 +OP4 E0285E 0 +OP4 E0285F 0 +OP4 E02860 0 +OP4 E02861 0 +OP4 E02862 0 +OP4 E02863 0 +OP4 E02864 0 +OP4 E02865 0 +OP4 E02866 0 +OP4 E02867 0 +OP4 E02868 0 +OP4 E02869 0 +OP4 E0286A 0 +OP4 E0286B 0 +OP4 E0286C 0 +OP4 E0286D 0 +OP4 E0286E 0 +OP4 E0286F 0 +OP4 E02870 0 +OP4 E02871 0 +OP4 E02872 0 +OP4 E02873 0 +OP4 E02874 0 +OP4 E02875 0 +OP4 E02876 0 +OP4 E02877 0 +OP4 E02878 0 +OP4 E02879 0 +OP4 E0287A 0 +OP4 E0287B 0 +OP4 E0287C 0 +OP4 E0287D 0 +OP4 E0287E 0 +OP4 E0287F 0 +OP4 E02880 0 +OP4 E02881 0 +OP4 E02882 0 +OP4 E02883 0 +OP4 E02884 0 +OP4 E02885 0 +OP4 E02886 0 +OP4 E02887 0 +OP4 E02888 0 +OP4 E02889 0 +OP4 E0288A 0 +OP4 E0288B 0 +OP4 E0288C 0 +OP4 E0288D 0 +OP4 E0288E 0 +OP4 E0288F 0 +OP4 E02890 0 +OP4 E02891 0 +OP4 E02892 0 +OP4 E02893 0 +OP4 E02894 0 +OP4 E02895 0 +OP4 E02896 0 +OP4 E02897 0 +OP4 E02898 0 +OP4 E02899 0 +OP4 E0289A 0 +OP4 E0289B 0 +OP4 E0289C 0 +OP4 E0289D 0 +OP4 E0289E 0 +OP4 E0289F 0 +OP4 E028A0 0 +OP4 E028A1 0 +OP4 E028A2 0 +OP4 E028A3 0 +OP4 E028A4 0 +OP4 E028A5 0 +OP4 E028A6 0 +OP4 E028A7 0 +OP4 E028A8 0 +OP4 E028A9 0 +OP4 E028AA 0 +OP4 E028AB 0 +OP4 E028AC 0 +OP4 E028AD 0 +OP4 E028AE 0 +OP4 E028AF 0 +OP4 E028B0 0 +OP4 E028B1 0 +OP4 E028B2 0 +OP4 E028B3 0 +OP4 E028B4 0 +OP4 E028B5 0 +OP4 E028B6 0 +OP4 E028B7 0 +OP4 E028B8 0 +OP4 E028B9 0 +OP4 E028BA 0 +OP4 E028BB 0 +OP4 E028BC 0 +OP4 E028BD 0 +OP4 E028BE 0 +OP4 E028BF 0 +OP4 E028C0 0 +OP4 E028C1 0 +OP4 E028C2 0 +OP4 E028C3 0 +OP4 E028C4 0 +OP4 E028C5 0 +OP4 E028C6 0 +OP4 E028C7 0 +OP4 E028C8 0 +OP4 E028C9 0 +OP4 E028CA 0 +OP4 E028CB 0 +OP4 E028CC 0 +OP4 E028CD 0 +OP4 E028CE 0 +OP4 E028CF 0 +OP4 E028D0 0 +OP4 E028D1 0 +OP4 E028D2 0 +OP4 E028D3 0 +OP4 E028D4 0 +OP4 E028D5 0 +OP4 E028D6 0 +OP4 E028D7 0 +OP4 E028D8 0 +OP4 E028D9 0 +OP4 E028DA 0 +OP4 E028DB 0 +OP4 E028DC 0 +OP4 E028DD 0 +OP4 E028DE 0 +OP4 E028DF 0 +OP4 E028E0 0 +OP4 E028E1 0 +OP4 E028E2 0 +OP4 E028E3 0 +OP4 E028E4 0 +OP4 E028E5 0 +OP4 E028E6 0 +OP4 E028E7 0 +OP4 E028E8 0 +OP4 E028E9 0 +OP4 E028EA 0 +OP4 E028EB 0 +OP4 E028EC 0 +OP4 E028ED 0 +OP4 E028EE 0 +OP4 E028EF 0 +OP4 E028F0 0 +OP4 E028F1 0 +OP4 E028F2 0 +OP4 E028F3 0 +OP4 E028F4 0 +OP4 E028F5 0 +OP4 E028F6 0 +OP4 E028F7 0 +OP4 E028F8 0 +OP4 E028F9 0 +OP4 E028FA 0 +OP4 E028FB 0 +OP4 E028FC 0 +OP4 E028FD 0 +OP4 E028FE 0 +OP4 E028FF 0 +OP4 E02900 0 +OP4 E02901 0 +OP4 E02902 0 +OP4 E02903 0 +OP4 E02904 0 +OP4 E02905 0 +OP4 E02906 0 +OP4 E02907 0 +OP4 E02908 0 +OP4 E02909 0 +OP4 E0290A 0 +OP4 E0290B 0 +OP4 E0290C 0 +OP4 E0290D 0 +OP4 E0290E 0 +OP4 E0290F 0 +OP4 E02910 0 +OP4 E02911 0 +OP4 E02912 0 +OP4 E02913 0 +OP4 E02914 0 +OP4 E02915 0 +OP4 E02916 0 +OP4 E02917 0 +OP4 E02918 0 +OP4 E02919 0 +OP4 E0291A 0 +OP4 E0291B 0 +OP4 E0291C 0 +OP4 E0291D 0 +OP4 E0291E 0 +OP4 E0291F 0 +OP4 E02920 0 +OP4 E02921 0 +OP4 E02922 0 +OP4 E02923 0 +OP4 E02924 0 +OP4 E02925 0 +OP4 E02926 0 +OP4 E02927 0 +OP4 E02928 0 +OP4 E02929 0 +OP4 E0292A 0 +OP4 E0292B 0 +OP4 E0292C 0 +OP4 E0292D 0 +OP4 E0292E 0 +OP4 E0292F 0 +OP4 E02930 0 +OP4 E02931 0 +OP4 E02932 0 +OP4 E02933 0 +OP4 E02934 0 +OP4 E02935 0 +OP4 E02936 0 +OP4 E02937 0 +OP4 E02938 0 +OP4 E02939 0 +OP4 E0293A 0 +OP4 E0293B 0 +OP4 E0293C 0 +OP4 E0293D 0 +OP4 E0293E 0 +OP4 E0293F 0 +OP4 E02940 0 +OP4 E02941 0 +OP4 E02942 0 +OP4 E02943 0 +OP4 E02944 0 +OP4 E02945 0 +OP4 E02946 0 +OP4 E02947 0 +OP4 E02948 0 +OP4 E02949 0 +OP4 E0294A 0 +OP4 E0294B 0 +OP4 E0294C 0 +OP4 E0294D 0 +OP4 E0294E 0 +OP4 E0294F 0 +OP4 E02950 0 +OP4 E02951 0 +OP4 E02952 0 +OP4 E02953 0 +OP4 E02954 0 +OP4 E02955 0 +OP4 E02956 0 +OP4 E02957 0 +OP4 E02958 0 +OP4 E02959 0 +OP4 E0295A 0 +OP4 E0295B 0 +OP4 E0295C 0 +OP4 E0295D 0 +OP4 E0295E 0 +OP4 E0295F 0 +OP4 E02960 0 +OP4 E02961 0 +OP4 E02962 0 +OP4 E02963 0 +OP4 E02964 0 +OP4 E02965 0 +OP4 E02966 0 +OP4 E02967 0 +OP4 E02968 0 +OP4 E02969 0 +OP4 E0296A 0 +OP4 E0296B 0 +OP4 E0296C 0 +OP4 E0296D 0 +OP4 E0296E 0 +OP4 E0296F 0 +OP4 E02970 0 +OP4 E02971 0 +OP4 E02972 0 +OP4 E02973 0 +OP4 E02974 0 +OP4 E02975 0 +OP4 E02976 0 +OP4 E02977 0 +OP4 E02978 0 +OP4 E02979 0 +OP4 E0297A 0 +OP4 E0297B 0 +OP4 E0297C 0 +OP4 E0297D 0 +OP4 E0297E 0 +OP4 E0297F 0 +OP4 E02980 0 +OP4 E02981 0 +OP4 E02982 0 +OP4 E02983 0 +OP4 E02984 0 +OP4 E02985 0 +OP4 E02986 0 +OP4 E02987 0 +OP4 E02988 0 +OP4 E02989 0 +OP4 E0298A 0 +OP4 E0298B 0 +OP4 E0298C 0 +OP4 E0298D 0 +OP4 E0298E 0 +OP4 E0298F 0 +OP4 E02990 0 +OP4 E02991 0 +OP4 E02992 0 +OP4 E02993 0 +OP4 E02994 0 +OP4 E02995 0 +OP4 E02996 0 +OP4 E02997 0 +OP4 E02998 0 +OP4 E02999 0 +OP4 E0299A 0 +OP4 E0299B 0 +OP4 E0299C 0 +OP4 E0299D 0 +OP4 E0299E 0 +OP4 E0299F 0 +OP4 E029A0 0 +OP4 E029A1 0 +OP4 E029A2 0 +OP4 E029A3 0 +OP4 E029A4 0 +OP4 E029A5 0 +OP4 E029A6 0 +OP4 E029A7 0 +OP4 E029A8 0 +OP4 E029A9 0 +OP4 E029AA 0 +OP4 E029AB 0 +OP4 E029AC 0 +OP4 E029AD 0 +OP4 E029AE 0 +OP4 E029AF 0 +OP4 E029B0 0 +OP4 E029B1 0 +OP4 E029B2 0 +OP4 E029B3 0 +OP4 E029B4 0 +OP4 E029B5 0 +OP4 E029B6 0 +OP4 E029B7 0 +OP4 E029B8 0 +OP4 E029B9 0 +OP4 E029BA 0 +OP4 E029BB 0 +OP4 E029BC 0 +OP4 E029BD 0 +OP4 E029BE 0 +OP4 E029BF 0 +OP4 E029C0 0 +OP4 E029C1 0 +OP4 E029C2 0 +OP4 E029C3 0 +OP4 E029C4 0 +OP4 E029C5 0 +OP4 E029C6 0 +OP4 E029C7 0 +OP4 E029C8 0 +OP4 E029C9 0 +OP4 E029CA 0 +OP4 E029CB 0 +OP4 E029CC 0 +OP4 E029CD 0 +OP4 E029CE 0 +OP4 E029CF 0 +OP4 E029D0 0 +OP4 E029D1 0 +OP4 E029D2 0 +OP4 E029D3 0 +OP4 E029D4 0 +OP4 E029D5 0 +OP4 E029D6 0 +OP4 E029D7 0 +OP4 E029D8 0 +OP4 E029D9 0 +OP4 E029DA 0 +OP4 E029DB 0 +OP4 E029DC 0 +OP4 E029DD 0 +OP4 E029DE 0 +OP4 E029DF 0 +OP4 E029E0 0 +OP4 E029E1 0 +OP4 E029E2 0 +OP4 E029E3 0 +OP4 E029E4 0 +OP4 E029E5 0 +OP4 E029E6 0 +OP4 E029E7 0 +OP4 E029E8 0 +OP4 E029E9 0 +OP4 E029EA 0 +OP4 E029EB 0 +OP4 E029EC 0 +OP4 E029ED 0 +OP4 E029EE 0 +OP4 E029EF 0 +OP4 E029F0 0 +OP4 E029F1 0 +OP4 E029F2 0 +OP4 E029F3 0 +OP4 E029F4 0 +OP4 E029F5 0 +OP4 E029F6 0 +OP4 E029F7 0 +OP4 E029F8 0 +OP4 E029F9 0 +OP4 E029FA 0 +OP4 E029FB 0 +OP4 E029FC 0 +OP4 E029FD 0 +OP4 E029FE 0 +OP4 E029FF 0 +OP4 E02A00 0 +OP4 E02A01 0 +OP4 E02A02 0 +OP4 E02A03 0 +OP4 E02A04 0 +OP4 E02A05 0 +OP4 E02A06 0 +OP4 E02A07 0 +OP4 E02A08 0 +OP4 E02A09 0 +OP4 E02A0A 0 +OP4 E02A0B 0 +OP4 E02A0C 0 +OP4 E02A0D 0 +OP4 E02A0E 0 +OP4 E02A0F 0 +OP4 E02A10 0 +OP4 E02A11 0 +OP4 E02A12 0 +OP4 E02A13 0 +OP4 E02A14 0 +OP4 E02A15 0 +OP4 E02A16 0 +OP4 E02A17 0 +OP4 E02A18 0 +OP4 E02A19 0 +OP4 E02A1A 0 +OP4 E02A1B 0 +OP4 E02A1C 0 +OP4 E02A1D 0 +OP4 E02A1E 0 +OP4 E02A1F 0 +OP4 E02A20 0 +OP4 E02A21 0 +OP4 E02A22 0 +OP4 E02A23 0 +OP4 E02A24 0 +OP4 E02A25 0 +OP4 E02A26 0 +OP4 E02A27 0 +OP4 E02A28 0 +OP4 E02A29 0 +OP4 E02A2A 0 +OP4 E02A2B 0 +OP4 E02A2C 0 +OP4 E02A2D 0 +OP4 E02A2E 0 +OP4 E02A2F 0 +OP4 E02A30 0 +OP4 E02A31 0 +OP4 E02A32 0 +OP4 E02A33 0 +OP4 E02A34 0 +OP4 E02A35 0 +OP4 E02A36 0 +OP4 E02A37 0 +OP4 E02A38 0 +OP4 E02A39 0 +OP4 E02A3A 0 +OP4 E02A3B 0 +OP4 E02A3C 0 +OP4 E02A3D 0 +OP4 E02A3E 0 +OP4 E02A3F 0 +OP4 E02A40 0 +OP4 E02A41 0 +OP4 E02A42 0 +OP4 E02A43 0 +OP4 E02A44 0 +OP4 E02A45 0 +OP4 E02A46 0 +OP4 E02A47 0 +OP4 E02A48 0 +OP4 E02A49 0 +OP4 E02A4A 0 +OP4 E02A4B 0 +OP4 E02A4C 0 +OP4 E02A4D 0 +OP4 E02A4E 0 +OP4 E02A4F 0 +OP4 E02A50 0 +OP4 E02A51 0 +OP4 E02A52 0 +OP4 E02A53 0 +OP4 E02A54 0 +OP4 E02A55 0 +OP4 E02A56 0 +OP4 E02A57 0 +OP4 E02A58 0 +OP4 E02A59 0 +OP4 E02A5A 0 +OP4 E02A5B 0 +OP4 E02A5C 0 +OP4 E02A5D 0 +OP4 E02A5E 0 +OP4 E02A5F 0 +OP4 E02A60 0 +OP4 E02A61 0 +OP4 E02A62 0 +OP4 E02A63 0 +OP4 E02A64 0 +OP4 E02A65 0 +OP4 E02A66 0 +OP4 E02A67 0 +OP4 E02A68 0 +OP4 E02A69 0 +OP4 E02A6A 0 +OP4 E02A6B 0 +OP4 E02A6C 0 +OP4 E02A6D 0 +OP4 E02A6E 0 +OP4 E02A6F 0 +OP4 E02A70 0 +OP4 E02A71 0 +OP4 E02A72 0 +OP4 E02A73 0 +OP4 E02A74 0 +OP4 E02A75 0 +OP4 E02A76 0 +OP4 E02A77 0 +OP4 E02A78 0 +OP4 E02A79 0 +OP4 E02A7A 0 +OP4 E02A7B 0 +OP4 E02A7C 0 +OP4 E02A7D 0 +OP4 E02A7E 0 +OP4 E02A7F 0 +OP4 E02A80 0 +OP4 E02A81 0 +OP4 E02A82 0 +OP4 E02A83 0 +OP4 E02A84 0 +OP4 E02A85 0 +OP4 E02A86 0 +OP4 E02A87 0 +OP4 E02A88 0 +OP4 E02A89 0 +OP4 E02A8A 0 +OP4 E02A8B 0 +OP4 E02A8C 0 +OP4 E02A8D 0 +OP4 E02A8E 0 +OP4 E02A8F 0 +OP4 E02A90 0 +OP4 E02A91 0 +OP4 E02A92 0 +OP4 E02A93 0 +OP4 E02A94 0 +OP4 E02A95 0 +OP4 E02A96 0 +OP4 E02A97 0 +OP4 E02A98 0 +OP4 E02A99 0 +OP4 E02A9A 0 +OP4 E02A9B 0 +OP4 E02A9C 0 +OP4 E02A9D 0 +OP4 E02A9E 0 +OP4 E02A9F 0 +OP4 E02AA0 0 +OP4 E02AA1 0 +OP4 E02AA2 0 +OP4 E02AA3 0 +OP4 E02AA4 0 +OP4 E02AA5 0 +OP4 E02AA6 0 +OP4 E02AA7 0 +OP4 E02AA8 0 +OP4 E02AA9 0 +OP4 E02AAA 0 +OP4 E02AAB 0 +OP4 E02AAC 0 +OP4 E02AAD 0 +OP4 E02AAE 0 +OP4 E02AAF 0 +OP4 E02AB0 0 +OP4 E02AB1 0 +OP4 E02AB2 0 +OP4 E02AB3 0 +OP4 E02AB4 0 +OP4 E02AB5 0 +OP4 E02AB6 0 +OP4 E02AB7 0 +OP4 E02AB8 0 +OP4 E02AB9 0 +OP4 E02ABA 0 +OP4 E02ABB 0 +OP4 E02ABC 0 +OP4 E02ABD 0 +OP4 E02ABE 0 +OP4 E02ABF 0 +OP4 E02AC0 0 +OP4 E02AC1 0 +OP4 E02AC2 0 +OP4 E02AC3 0 +OP4 E02AC4 0 +OP4 E02AC5 0 +OP4 E02AC6 0 +OP4 E02AC7 0 +OP4 E02AC8 0 +OP4 E02AC9 0 +OP4 E02ACA 0 +OP4 E02ACB 0 +OP4 E02ACC 0 +OP4 E02ACD 0 +OP4 E02ACE 0 +OP4 E02ACF 0 +OP4 E02AD0 0 +OP4 E02AD1 0 +OP4 E02AD2 0 +OP4 E02AD3 0 +OP4 E02AD4 0 +OP4 E02AD5 0 +OP4 E02AD6 0 +OP4 E02AD7 0 +OP4 E02AD8 0 +OP4 E02AD9 0 +OP4 E02ADA 0 +OP4 E02ADB 0 +OP4 E02ADC 0 +OP4 E02ADD 0 +OP4 E02ADE 0 +OP4 E02ADF 0 +OP4 E02AE0 0 +OP4 E02AE1 0 +OP4 E02AE2 0 +OP4 E02AE3 0 +OP4 E02AE4 0 +OP4 E02AE5 0 +OP4 E02AE6 0 +OP4 E02AE7 0 +OP4 E02AE8 0 +OP4 E02AE9 0 +OP4 E02AEA 0 +OP4 E02AEB 0 +OP4 E02AEC 0 +OP4 E02AED 0 +OP4 E02AEE 0 +OP4 E02AEF 0 +OP4 E02AF0 0 +OP4 E02AF1 0 +OP4 E02AF2 0 +OP4 E02AF3 0 +OP4 E02AF4 0 +OP4 E02AF5 0 +OP4 E02AF6 0 +OP4 E02AF7 0 +OP4 E02AF8 0 +OP4 E02AF9 0 +OP4 E02AFA 0 +OP4 E02AFB 0 +OP4 E02AFC 0 +OP4 E02AFD 0 +OP4 E02AFE 0 +OP4 E02AFF 0 +OP4 E02B00 0 +OP4 E02B01 0 +OP4 E02B02 0 +OP4 E02B03 0 +OP4 E02B04 0 +OP4 E02B05 0 +OP4 E02B06 0 +OP4 E02B07 0 +OP4 E02B08 0 +OP4 E02B09 0 +OP4 E02B0A 0 +OP4 E02B0B 0 +OP4 E02B0C 0 +OP4 E02B0D 0 +OP4 E02B0E 0 +OP4 E02B0F 0 +OP4 E02B10 0 +OP4 E02B11 0 +OP4 E02B12 0 +OP4 E02B13 0 +OP4 E02B14 0 +OP4 E02B15 0 +OP4 E02B16 0 +OP4 E02B17 0 +OP4 E02B18 0 +OP4 E02B19 0 +OP4 E02B1A 0 +OP4 E02B1B 0 +OP4 E02B1C 0 +OP4 E02B1D 0 +OP4 E02B1E 0 +OP4 E02B1F 0 +OP4 E02B20 0 +OP4 E02B21 0 +OP4 E02B22 0 +OP4 E02B23 0 +OP4 E02B24 0 +OP4 E02B25 0 +OP4 E02B26 0 +OP4 E02B27 0 +OP4 E02B28 0 +OP4 E02B29 0 +OP4 E02B2A 0 +OP4 E02B2B 0 +OP4 E02B2C 0 +OP4 E02B2D 0 +OP4 E02B2E 0 +OP4 E02B2F 0 +OP4 E02B30 0 +OP4 E02B31 0 +OP4 E02B32 0 +OP4 E02B33 0 +OP4 E02B34 0 +OP4 E02B35 0 +OP4 E02B36 0 +OP4 E02B37 0 +OP4 E02B38 0 +OP4 E02B39 0 +OP4 E02B3A 0 +OP4 E02B3B 0 +OP4 E02B3C 0 +OP4 E02B3D 0 +OP4 E02B3E 0 +OP4 E02B3F 0 +OP4 E02B40 0 +OP4 E02B41 0 +OP4 E02B42 0 +OP4 E02B43 0 +OP4 E02B44 0 +OP4 E02B45 0 +OP4 E02B46 0 +OP4 E02B47 0 +OP4 E02B48 0 +OP4 E02B49 0 +OP4 E02B4A 0 +OP4 E02B4B 0 +OP4 E02B4C 0 +OP4 E02B4D 0 +OP4 E02B4E 0 +OP4 E02B4F 0 +OP4 E02B50 0 +OP4 E02B51 0 +OP4 E02B52 0 +OP4 E02B53 0 +OP4 E02B54 0 +OP4 E02B55 0 +OP4 E02B56 0 +OP4 E02B57 0 +OP4 E02B58 0 +OP4 E02B59 0 +OP4 E02B5A 0 +OP4 E02B5B 0 +OP4 E02B5C 0 +OP4 E02B5D 0 +OP4 E02B5E 0 +OP4 E02B5F 0 +OP4 E02B60 0 +OP4 E02B61 0 +OP4 E02B62 0 +OP4 E02B63 0 +OP4 E02B64 0 +OP4 E02B65 0 +OP4 E02B66 0 +OP4 E02B67 0 +OP4 E02B68 0 +OP4 E02B69 0 +OP4 E02B6A 0 +OP4 E02B6B 0 +OP4 E02B6C 0 +OP4 E02B6D 0 +OP4 E02B6E 0 +OP4 E02B6F 0 +OP4 E02B70 0 +OP4 E02B71 0 +OP4 E02B72 0 +OP4 E02B73 0 +OP4 E02B74 0 +OP4 E02B75 0 +OP4 E02B76 0 +OP4 E02B77 0 +OP4 E02B78 0 +OP4 E02B79 0 +OP4 E02B7A 0 +OP4 E02B7B 0 +OP4 E02B7C 0 +OP4 E02B7D 0 +OP4 E02B7E 0 +OP4 E02B7F 0 +OP4 E02B80 0 +OP4 E02B81 0 +OP4 E02B82 0 +OP4 E02B83 0 +OP4 E02B84 0 +OP4 E02B85 0 +OP4 E02B86 0 +OP4 E02B87 0 +OP4 E02B88 0 +OP4 E02B89 0 +OP4 E02B8A 0 +OP4 E02B8B 0 +OP4 E02B8C 0 +OP4 E02B8D 0 +OP4 E02B8E 0 +OP4 E02B8F 0 +OP4 E02B90 0 +OP4 E02B91 0 +OP4 E02B92 0 +OP4 E02B93 0 +OP4 E02B94 0 +OP4 E02B95 0 +OP4 E02B96 0 +OP4 E02B97 0 +OP4 E02B98 0 +OP4 E02B99 0 +OP4 E02B9A 0 +OP4 E02B9B 0 +OP4 E02B9C 0 +OP4 E02B9D 0 +OP4 E02B9E 0 +OP4 E02B9F 0 +OP4 E02BA0 0 +OP4 E02BA1 0 +OP4 E02BA2 0 +OP4 E02BA3 0 +OP4 E02BA4 0 +OP4 E02BA5 0 +OP4 E02BA6 0 +OP4 E02BA7 0 +OP4 E02BA8 0 +OP4 E02BA9 0 +OP4 E02BAA 0 +OP4 E02BAB 0 +OP4 E02BAC 0 +OP4 E02BAD 0 +OP4 E02BAE 0 +OP4 E02BAF 0 +OP4 E02BB0 0 +OP4 E02BB1 0 +OP4 E02BB2 0 +OP4 E02BB3 0 +OP4 E02BB4 0 +OP4 E02BB5 0 +OP4 E02BB6 0 +OP4 E02BB7 0 +OP4 E02BB8 0 +OP4 E02BB9 0 +OP4 E02BBA 0 +OP4 E02BBB 0 +OP4 E02BBC 0 +OP4 E02BBD 0 +OP4 E02BBE 0 +OP4 E02BBF 0 +OP4 E02BC0 0 +OP4 E02BC1 0 +OP4 E02BC2 0 +OP4 E02BC3 0 +OP4 E02BC4 0 +OP4 E02BC5 0 +OP4 E02BC6 0 +OP4 E02BC7 0 +OP4 E02BC8 0 +OP4 E02BC9 0 +OP4 E02BCA 0 +OP4 E02BCB 0 +OP4 E02BCC 0 +OP4 E02BCD 0 +OP4 E02BCE 0 +OP4 E02BCF 0 +OP4 E02BD0 0 +OP4 E02BD1 0 +OP4 E02BD2 0 +OP4 E02BD3 0 +OP4 E02BD4 0 +OP4 E02BD5 0 +OP4 E02BD6 0 +OP4 E02BD7 0 +OP4 E02BD8 0 +OP4 E02BD9 0 +OP4 E02BDA 0 +OP4 E02BDB 0 +OP4 E02BDC 0 +OP4 E02BDD 0 +OP4 E02BDE 0 +OP4 E02BDF 0 +OP4 E02BE0 0 +OP4 E02BE1 0 +OP4 E02BE2 0 +OP4 E02BE3 0 +OP4 E02BE4 0 +OP4 E02BE5 0 +OP4 E02BE6 0 +OP4 E02BE7 0 +OP4 E02BE8 0 +OP4 E02BE9 0 +OP4 E02BEA 0 +OP4 E02BEB 0 +OP4 E02BEC 0 +OP4 E02BED 0 +OP4 E02BEE 0 +OP4 E02BEF 0 +OP4 E02BF0 0 +OP4 E02BF1 0 +OP4 E02BF2 0 +OP4 E02BF3 0 +OP4 E02BF4 0 +OP4 E02BF5 0 +OP4 E02BF6 0 +OP4 E02BF7 0 +OP4 E02BF8 0 +OP4 E02BF9 0 +OP4 E02BFA 0 +OP4 E02BFB 0 +OP4 E02BFC 0 +OP4 E02BFD 0 +OP4 E02BFE 0 +OP4 E02BFF 0 +OP4 E02C00 0 +OP4 E02C01 0 +OP4 E02C02 0 +OP4 E02C03 0 +OP4 E02C04 0 +OP4 E02C05 0 +OP4 E02C06 0 +OP4 E02C07 0 +OP4 E02C08 0 +OP4 E02C09 0 +OP4 E02C0A 0 +OP4 E02C0B 0 +OP4 E02C0C 0 +OP4 E02C0D 0 +OP4 E02C0E 0 +OP4 E02C0F 0 +OP4 E02C10 0 +OP4 E02C11 0 +OP4 E02C12 0 +OP4 E02C13 0 +OP4 E02C14 0 +OP4 E02C15 0 +OP4 E02C16 0 +OP4 E02C17 0 +OP4 E02C18 0 +OP4 E02C19 0 +OP4 E02C1A 0 +OP4 E02C1B 0 +OP4 E02C1C 0 +OP4 E02C1D 0 +OP4 E02C1E 0 +OP4 E02C1F 0 +OP4 E02C20 0 +OP4 E02C21 0 +OP4 E02C22 0 +OP4 E02C23 0 +OP4 E02C24 0 +OP4 E02C25 0 +OP4 E02C26 0 +OP4 E02C27 0 +OP4 E02C28 0 +OP4 E02C29 0 +OP4 E02C2A 0 +OP4 E02C2B 0 +OP4 E02C2C 0 +OP4 E02C2D 0 +OP4 E02C2E 0 +OP4 E02C2F 0 +OP4 E02C30 0 +OP4 E02C31 0 +OP4 E02C32 0 +OP4 E02C33 0 +OP4 E02C34 0 +OP4 E02C35 0 +OP4 E02C36 0 +OP4 E02C37 0 +OP4 E02C38 0 +OP4 E02C39 0 +OP4 E02C3A 0 +OP4 E02C3B 0 +OP4 E02C3C 0 +OP4 E02C3D 0 +OP4 E02C3E 0 +OP4 E02C3F 0 +OP4 E02C40 0 +OP4 E02C41 0 +OP4 E02C42 0 +OP4 E02C43 0 +OP4 E02C44 0 +OP4 E02C45 0 +OP4 E02C46 0 +OP4 E02C47 0 +OP4 E02C48 0 +OP4 E02C49 0 +OP4 E02C4A 0 +OP4 E02C4B 0 +OP4 E02C4C 0 +OP4 E02C4D 0 +OP4 E02C4E 0 +OP4 E02C4F 0 +OP4 E02C50 0 +OP4 E02C51 0 +OP4 E02C52 0 +OP4 E02C53 0 +OP4 E02C54 0 +OP4 E02C55 0 +OP4 E02C56 0 +OP4 E02C57 0 +OP4 E02C58 0 +OP4 E02C59 0 +OP4 E02C5A 0 +OP4 E02C5B 0 +OP4 E02C5C 0 +OP4 E02C5D 0 +OP4 E02C5E 0 +OP4 E02C5F 0 +OP4 E02C60 0 +OP4 E02C61 0 +OP4 E02C62 0 +OP4 E02C63 0 +OP4 E02C64 0 +OP4 E02C65 0 +OP4 E02C66 0 +OP4 E02C67 0 +OP4 E02C68 0 +OP4 E02C69 0 +OP4 E02C6A 0 +OP4 E02C6B 0 +OP4 E02C6C 0 +OP4 E02C6D 0 +OP4 E02C6E 0 +OP4 E02C6F 0 +OP4 E02C70 0 +OP4 E02C71 0 +OP4 E02C72 0 +OP4 E02C73 0 +OP4 E02C74 0 +OP4 E02C75 0 +OP4 E02C76 0 +OP4 E02C77 0 +OP4 E02C78 0 +OP4 E02C79 0 +OP4 E02C7A 0 +OP4 E02C7B 0 +OP4 E02C7C 0 +OP4 E02C7D 0 +OP4 E02C7E 0 +OP4 E02C7F 0 +OP4 E02C80 0 +OP4 E02C81 0 +OP4 E02C82 0 +OP4 E02C83 0 +OP4 E02C84 0 +OP4 E02C85 0 +OP4 E02C86 0 +OP4 E02C87 0 +OP4 E02C88 0 +OP4 E02C89 0 +OP4 E02C8A 0 +OP4 E02C8B 0 +OP4 E02C8C 0 +OP4 E02C8D 0 +OP4 E02C8E 0 +OP4 E02C8F 0 +OP4 E02C90 0 +OP4 E02C91 0 +OP4 E02C92 0 +OP4 E02C93 0 +OP4 E02C94 0 +OP4 E02C95 0 +OP4 E02C96 0 +OP4 E02C97 0 +OP4 E02C98 0 +OP4 E02C99 0 +OP4 E02C9A 0 +OP4 E02C9B 0 +OP4 E02C9C 0 +OP4 E02C9D 0 +OP4 E02C9E 0 +OP4 E02C9F 0 +OP4 E02CA0 0 +OP4 E02CA1 0 +OP4 E02CA2 0 +OP4 E02CA3 0 +OP4 E02CA4 0 +OP4 E02CA5 0 +OP4 E02CA6 0 +OP4 E02CA7 0 +OP4 E02CA8 0 +OP4 E02CA9 0 +OP4 E02CAA 0 +OP4 E02CAB 0 +OP4 E02CAC 0 +OP4 E02CAD 0 +OP4 E02CAE 0 +OP4 E02CAF 0 +OP4 E02CB0 0 +OP4 E02CB1 0 +OP4 E02CB2 0 +OP4 E02CB3 0 +OP4 E02CB4 0 +OP4 E02CB5 0 +OP4 E02CB6 0 +OP4 E02CB7 0 +OP4 E02CB8 0 +OP4 E02CB9 0 +OP4 E02CBA 0 +OP4 E02CBB 0 +OP4 E02CBC 0 +OP4 E02CBD 0 +OP4 E02CBE 0 +OP4 E02CBF 0 +OP4 E02CC0 0 +OP4 E02CC1 0 +OP4 E02CC2 0 +OP4 E02CC3 0 +OP4 E02CC4 0 +OP4 E02CC5 0 +OP4 E02CC6 0 +OP4 E02CC7 0 +OP4 E02CC8 0 +OP4 E02CC9 0 +OP4 E02CCA 0 +OP4 E02CCB 0 +OP4 E02CCC 0 +OP4 E02CCD 0 +OP4 E02CCE 0 +OP4 E02CCF 0 +OP4 E02CD0 0 +OP4 E02CD1 0 +OP4 E02CD2 0 +OP4 E02CD3 0 +OP4 E02CD4 0 +OP4 E02CD5 0 +OP4 E02CD6 0 +OP4 E02CD7 0 +OP4 E02CD8 0 +OP4 E02CD9 0 +OP4 E02CDA 0 +OP4 E02CDB 0 +OP4 E02CDC 0 +OP4 E02CDD 0 +OP4 E02CDE 0 +OP4 E02CDF 0 +OP4 E02CE0 0 +OP4 E02CE1 0 +OP4 E02CE2 0 +OP4 E02CE3 0 +OP4 E02CE4 0 +OP4 E02CE5 0 +OP4 E02CE6 0 +OP4 E02CE7 0 +OP4 E02CE8 0 +OP4 E02CE9 0 +OP4 E02CEA 0 +OP4 E02CEB 0 +OP4 E02CEC 0 +OP4 E02CED 0 +OP4 E02CEE 0 +OP4 E02CEF 0 +OP4 E02CF0 0 +OP4 E02CF1 0 +OP4 E02CF2 0 +OP4 E02CF3 0 +OP4 E02CF4 0 +OP4 E02CF5 0 +OP4 E02CF6 0 +OP4 E02CF7 0 +OP4 E02CF8 0 +OP4 E02CF9 0 +OP4 E02CFA 0 +OP4 E02CFB 0 +OP4 E02CFC 0 +OP4 E02CFD 0 +OP4 E02CFE 0 +OP4 E02CFF 0 +OP4 E02D00 0 +OP4 E02D01 0 +OP4 E02D02 0 +OP4 E02D03 0 +OP4 E02D04 0 +OP4 E02D05 0 +OP4 E02D06 0 +OP4 E02D07 0 +OP4 E02D08 0 +OP4 E02D09 0 +OP4 E02D0A 0 +OP4 E02D0B 0 +OP4 E02D0C 0 +OP4 E02D0D 0 +OP4 E02D0E 0 +OP4 E02D0F 0 +OP4 E02D10 0 +OP4 E02D11 0 +OP4 E02D12 0 +OP4 E02D13 0 +OP4 E02D14 0 +OP4 E02D15 0 +OP4 E02D16 0 +OP4 E02D17 0 +OP4 E02D18 0 +OP4 E02D19 0 +OP4 E02D1A 0 +OP4 E02D1B 0 +OP4 E02D1C 0 +OP4 E02D1D 0 +OP4 E02D1E 0 +OP4 E02D1F 0 +OP4 E02D20 0 +OP4 E02D21 0 +OP4 E02D22 0 +OP4 E02D23 0 +OP4 E02D24 0 +OP4 E02D25 0 +OP4 E02D26 0 +OP4 E02D27 0 +OP4 E02D28 0 +OP4 E02D29 0 +OP4 E02D2A 0 +OP4 E02D2B 0 +OP4 E02D2C 0 +OP4 E02D2D 0 +OP4 E02D2E 0 +OP4 E02D2F 0 +OP4 E02D30 0 +OP4 E02D31 0 +OP4 E02D32 0 +OP4 E02D33 0 +OP4 E02D34 0 +OP4 E02D35 0 +OP4 E02D36 0 +OP4 E02D37 0 +OP4 E02D38 0 +OP4 E02D39 0 +OP4 E02D3A 0 +OP4 E02D3B 0 +OP4 E02D3C 0 +OP4 E02D3D 0 +OP4 E02D3E 0 +OP4 E02D3F 0 +OP4 E02D40 0 +OP4 E02D41 0 +OP4 E02D42 0 +OP4 E02D43 0 +OP4 E02D44 0 +OP4 E02D45 0 +OP4 E02D46 0 +OP4 E02D47 0 +OP4 E02D48 0 +OP4 E02D49 0 +OP4 E02D4A 0 +OP4 E02D4B 0 +OP4 E02D4C 0 +OP4 E02D4D 0 +OP4 E02D4E 0 +OP4 E02D4F 0 +OP4 E02D50 0 +OP4 E02D51 0 +OP4 E02D52 0 +OP4 E02D53 0 +OP4 E02D54 0 +OP4 E02D55 0 +OP4 E02D56 0 +OP4 E02D57 0 +OP4 E02D58 0 +OP4 E02D59 0 +OP4 E02D5A 0 +OP4 E02D5B 0 +OP4 E02D5C 0 +OP4 E02D5D 0 +OP4 E02D5E 0 +OP4 E02D5F 0 +OP4 E02D60 0 +OP4 E02D61 0 +OP4 E02D62 0 +OP4 E02D63 0 +OP4 E02D64 0 +OP4 E02D65 0 +OP4 E02D66 0 +OP4 E02D67 0 +OP4 E02D68 0 +OP4 E02D69 0 +OP4 E02D6A 0 +OP4 E02D6B 0 +OP4 E02D6C 0 +OP4 E02D6D 0 +OP4 E02D6E 0 +OP4 E02D6F 0 +OP4 E02D70 0 +OP4 E02D71 0 +OP4 E02D72 0 +OP4 E02D73 0 +OP4 E02D74 0 +OP4 E02D75 0 +OP4 E02D76 0 +OP4 E02D77 0 +OP4 E02D78 0 +OP4 E02D79 0 +OP4 E02D7A 0 +OP4 E02D7B 0 +OP4 E02D7C 0 +OP4 E02D7D 0 +OP4 E02D7E 0 +OP4 E02D7F 0 +OP4 E02D80 0 +OP4 E02D81 0 +OP4 E02D82 0 +OP4 E02D83 0 +OP4 E02D84 0 +OP4 E02D85 0 +OP4 E02D86 0 +OP4 E02D87 0 +OP4 E02D88 0 +OP4 E02D89 0 +OP4 E02D8A 0 +OP4 E02D8B 0 +OP4 E02D8C 0 +OP4 E02D8D 0 +OP4 E02D8E 0 +OP4 E02D8F 0 +OP4 E02D90 0 +OP4 E02D91 0 +OP4 E02D92 0 +OP4 E02D93 0 +OP4 E02D94 0 +OP4 E02D95 0 +OP4 E02D96 0 +OP4 E02D97 0 +OP4 E02D98 0 +OP4 E02D99 0 +OP4 E02D9A 0 +OP4 E02D9B 0 +OP4 E02D9C 0 +OP4 E02D9D 0 +OP4 E02D9E 0 +OP4 E02D9F 0 +OP4 E02DA0 0 +OP4 E02DA1 0 +OP4 E02DA2 0 +OP4 E02DA3 0 +OP4 E02DA4 0 +OP4 E02DA5 0 +OP4 E02DA6 0 +OP4 E02DA7 0 +OP4 E02DA8 0 +OP4 E02DA9 0 +OP4 E02DAA 0 +OP4 E02DAB 0 +OP4 E02DAC 0 +OP4 E02DAD 0 +OP4 E02DAE 0 +OP4 E02DAF 0 +OP4 E02DB0 0 +OP4 E02DB1 0 +OP4 E02DB2 0 +OP4 E02DB3 0 +OP4 E02DB4 0 +OP4 E02DB5 0 +OP4 E02DB6 0 +OP4 E02DB7 0 +OP4 E02DB8 0 +OP4 E02DB9 0 +OP4 E02DBA 0 +OP4 E02DBB 0 +OP4 E02DBC 0 +OP4 E02DBD 0 +OP4 E02DBE 0 +OP4 E02DBF 0 +OP4 E02DC0 0 +OP4 E02DC1 0 +OP4 E02DC2 0 +OP4 E02DC3 0 +OP4 E02DC4 0 +OP4 E02DC5 0 +OP4 E02DC6 0 +OP4 E02DC7 0 +OP4 E02DC8 0 +OP4 E02DC9 0 +OP4 E02DCA 0 +OP4 E02DCB 0 +OP4 E02DCC 0 +OP4 E02DCD 0 +OP4 E02DCE 0 +OP4 E02DCF 0 +OP4 E02DD0 0 +OP4 E02DD1 0 +OP4 E02DD2 0 +OP4 E02DD3 0 +OP4 E02DD4 0 +OP4 E02DD5 0 +OP4 E02DD6 0 +OP4 E02DD7 0 +OP4 E02DD8 0 +OP4 E02DD9 0 +OP4 E02DDA 0 +OP4 E02DDB 0 +OP4 E02DDC 0 +OP4 E02DDD 0 +OP4 E02DDE 0 +OP4 E02DDF 0 +OP4 E02DE0 0 +OP4 E02DE1 0 +OP4 E02DE2 0 +OP4 E02DE3 0 +OP4 E02DE4 0 +OP4 E02DE5 0 +OP4 E02DE6 0 +OP4 E02DE7 0 +OP4 E02DE8 0 +OP4 E02DE9 0 +OP4 E02DEA 0 +OP4 E02DEB 0 +OP4 E02DEC 0 +OP4 E02DED 0 +OP4 E02DEE 0 +OP4 E02DEF 0 +OP4 E02DF0 0 +OP4 E02DF1 0 +OP4 E02DF2 0 +OP4 E02DF3 0 +OP4 E02DF4 0 +OP4 E02DF5 0 +OP4 E02DF6 0 +OP4 E02DF7 0 +OP4 E02DF8 0 +OP4 E02DF9 0 +OP4 E02DFA 0 +OP4 E02DFB 0 +OP4 E02DFC 0 +OP4 E02DFD 0 +OP4 E02DFE 0 +OP4 E02DFF 0 +OP4 E02E00 0 +OP4 E02E01 0 +OP4 E02E02 0 +OP4 E02E03 0 +OP4 E02E04 0 +OP4 E02E05 0 +OP4 E02E06 0 +OP4 E02E07 0 +OP4 E02E08 0 +OP4 E02E09 0 +OP4 E02E0A 0 +OP4 E02E0B 0 +OP4 E02E0C 0 +OP4 E02E0D 0 +OP4 E02E0E 0 +OP4 E02E0F 0 +OP4 E02E10 0 +OP4 E02E11 0 +OP4 E02E12 0 +OP4 E02E13 0 +OP4 E02E14 0 +OP4 E02E15 0 +OP4 E02E16 0 +OP4 E02E17 0 +OP4 E02E18 0 +OP4 E02E19 0 +OP4 E02E1A 0 +OP4 E02E1B 0 +OP4 E02E1C 0 +OP4 E02E1D 0 +OP4 E02E1E 0 +OP4 E02E1F 0 +OP4 E02E20 0 +OP4 E02E21 0 +OP4 E02E22 0 +OP4 E02E23 0 +OP4 E02E24 0 +OP4 E02E25 0 +OP4 E02E26 0 +OP4 E02E27 0 +OP4 E02E28 0 +OP4 E02E29 0 +OP4 E02E2A 0 +OP4 E02E2B 0 +OP4 E02E2C 0 +OP4 E02E2D 0 +OP4 E02E2E 0 +OP4 E02E2F 0 +OP4 E02E30 0 +OP4 E02E31 0 +OP4 E02E32 0 +OP4 E02E33 0 +OP4 E02E34 0 +OP4 E02E35 0 +OP4 E02E36 0 +OP4 E02E37 0 +OP4 E02E38 0 +OP4 E02E39 0 +OP4 E02E3A 0 +OP4 E02E3B 0 +OP4 E02E3C 0 +OP4 E02E3D 0 +OP4 E02E3E 0 +OP4 E02E3F 0 +OP4 E02E40 0 +OP4 E02E41 0 +OP4 E02E42 0 +OP4 E02E43 0 +OP4 E02E44 0 +OP4 E02E45 0 +OP4 E02E46 0 +OP4 E02E47 0 +OP4 E02E48 0 +OP4 E02E49 0 +OP4 E02E4A 0 +OP4 E02E4B 0 +OP4 E02E4C 0 +OP4 E02E4D 0 +OP4 E02E4E 0 +OP4 E02E4F 0 +OP4 E02E50 0 +OP4 E02E51 0 +OP4 E02E52 0 +OP4 E02E53 0 +OP4 E02E54 0 +OP4 E02E55 0 +OP4 E02E56 0 +OP4 E02E57 0 +OP4 E02E58 0 +OP4 E02E59 0 +OP4 E02E5A 0 +OP4 E02E5B 0 +OP4 E02E5C 0 +OP4 E02E5D 0 +OP4 E02E5E 0 +OP4 E02E5F 0 +OP4 E02E60 0 +OP4 E02E61 0 +OP4 E02E62 0 +OP4 E02E63 0 +OP4 E02E64 0 +OP4 E02E65 0 +OP4 E02E66 0 +OP4 E02E67 0 +OP4 E02E68 0 +OP4 E02E69 0 +OP4 E02E6A 0 +OP4 E02E6B 0 +OP4 E02E6C 0 +OP4 E02E6D 0 +OP4 E02E6E 0 +OP4 E02E6F 0 +OP4 E02E70 0 +OP4 E02E71 0 +OP4 E02E72 0 +OP4 E02E73 0 +OP4 E02E74 0 +OP4 E02E75 0 +OP4 E02E76 0 +OP4 E02E77 0 +OP4 E02E78 0 +OP4 E02E79 0 +OP4 E02E7A 0 +OP4 E02E7B 0 +OP4 E02E7C 0 +OP4 E02E7D 0 +OP4 E02E7E 0 +OP4 E02E7F 0 +OP4 E02E80 0 +OP4 E02E81 0 +OP4 E02E82 0 +OP4 E02E83 0 +OP4 E02E84 0 +OP4 E02E85 0 +OP4 E02E86 0 +OP4 E02E87 0 +OP4 E02E88 0 +OP4 E02E89 0 +OP4 E02E8A 0 +OP4 E02E8B 0 +OP4 E02E8C 0 +OP4 E02E8D 0 +OP4 E02E8E 0 +OP4 E02E8F 0 +OP4 E02E90 0 +OP4 E02E91 0 +OP4 E02E92 0 +OP4 E02E93 0 +OP4 E02E94 0 +OP4 E02E95 0 +OP4 E02E96 0 +OP4 E02E97 0 +OP4 E02E98 0 +OP4 E02E99 0 +OP4 E02E9A 0 +OP4 E02E9B 0 +OP4 E02E9C 0 +OP4 E02E9D 0 +OP4 E02E9E 0 +OP4 E02E9F 0 +OP4 E02EA0 0 +OP4 E02EA1 0 +OP4 E02EA2 0 +OP4 E02EA3 0 +OP4 E02EA4 0 +OP4 E02EA5 0 +OP4 E02EA6 0 +OP4 E02EA7 0 +OP4 E02EA8 0 +OP4 E02EA9 0 +OP4 E02EAA 0 +OP4 E02EAB 0 +OP4 E02EAC 0 +OP4 E02EAD 0 +OP4 E02EAE 0 +OP4 E02EAF 0 +OP4 E02EB0 0 +OP4 E02EB1 0 +OP4 E02EB2 0 +OP4 E02EB3 0 +OP4 E02EB4 0 +OP4 E02EB5 0 +OP4 E02EB6 0 +OP4 E02EB7 0 +OP4 E02EB8 0 +OP4 E02EB9 0 +OP4 E02EBA 0 +OP4 E02EBB 0 +OP4 E02EBC 0 +OP4 E02EBD 0 +OP4 E02EBE 0 +OP4 E02EBF 0 +OP4 E02EC0 0 +OP4 E02EC1 0 +OP4 E02EC2 0 +OP4 E02EC3 0 +OP4 E02EC4 0 +OP4 E02EC5 0 +OP4 E02EC6 0 +OP4 E02EC7 0 +OP4 E02EC8 0 +OP4 E02EC9 0 +OP4 E02ECA 0 +OP4 E02ECB 0 +OP4 E02ECC 0 +OP4 E02ECD 0 +OP4 E02ECE 0 +OP4 E02ECF 0 +OP4 E02ED0 0 +OP4 E02ED1 0 +OP4 E02ED2 0 +OP4 E02ED3 0 +OP4 E02ED4 0 +OP4 E02ED5 0 +OP4 E02ED6 0 +OP4 E02ED7 0 +OP4 E02ED8 0 +OP4 E02ED9 0 +OP4 E02EDA 0 +OP4 E02EDB 0 +OP4 E02EDC 0 +OP4 E02EDD 0 +OP4 E02EDE 0 +OP4 E02EDF 0 +OP4 E02EE0 0 +OP4 E02EE1 0 +OP4 E02EE2 0 +OP4 E02EE3 0 +OP4 E02EE4 0 +OP4 E02EE5 0 +OP4 E02EE6 0 +OP4 E02EE7 0 +OP4 E02EE8 0 +OP4 E02EE9 0 +OP4 E02EEA 0 +OP4 E02EEB 0 +OP4 E02EEC 0 +OP4 E02EED 0 +OP4 E02EEE 0 +OP4 E02EEF 0 +OP4 E02EF0 0 +OP4 E02EF1 0 +OP4 E02EF2 0 +OP4 E02EF3 0 +OP4 E02EF4 0 +OP4 E02EF5 0 +OP4 E02EF6 0 +OP4 E02EF7 0 +OP4 E02EF8 0 +OP4 E02EF9 0 +OP4 E02EFA 0 +OP4 E02EFB 0 +OP4 E02EFC 0 +OP4 E02EFD 0 +OP4 E02EFE 0 +OP4 E02EFF 0 +OP4 E02F00 0 +OP4 E02F01 0 +OP4 E02F02 0 +OP4 E02F03 0 +OP4 E02F04 0 +OP4 E02F05 0 +OP4 E02F06 0 +OP4 E02F07 0 +OP4 E02F08 0 +OP4 E02F09 0 +OP4 E02F0A 0 +OP4 E02F0B 0 +OP4 E02F0C 0 +OP4 E02F0D 0 +OP4 E02F0E 0 +OP4 E02F0F 0 +OP4 E02F10 0 +OP4 E02F11 0 +OP4 E02F12 0 +OP4 E02F13 0 +OP4 E02F14 0 +OP4 E02F15 0 +OP4 E02F16 0 +OP4 E02F17 0 +OP4 E02F18 0 +OP4 E02F19 0 +OP4 E02F1A 0 +OP4 E02F1B 0 +OP4 E02F1C 0 +OP4 E02F1D 0 +OP4 E02F1E 0 +OP4 E02F1F 0 +OP4 E02F20 0 +OP4 E02F21 0 +OP4 E02F22 0 +OP4 E02F23 0 +OP4 E02F24 0 +OP4 E02F25 0 +OP4 E02F26 0 +OP4 E02F27 0 +OP4 E02F28 0 +OP4 E02F29 0 +OP4 E02F2A 0 +OP4 E02F2B 0 +OP4 E02F2C 0 +OP4 E02F2D 0 +OP4 E02F2E 0 +OP4 E02F2F 0 +OP4 E02F30 0 +OP4 E02F31 0 +OP4 E02F32 0 +OP4 E02F33 0 +OP4 E02F34 0 +OP4 E02F35 0 +OP4 E02F36 0 +OP4 E02F37 0 +OP4 E02F38 0 +OP4 E02F39 0 +OP4 E02F3A 0 +OP4 E02F3B 0 +OP4 E02F3C 0 +OP4 E02F3D 0 +OP4 E02F3E 0 +OP4 E02F3F 0 +OP4 E02F40 0 +OP4 E02F41 0 +OP4 E02F42 0 +OP4 E02F43 0 +OP4 E02F44 0 +OP4 E02F45 0 +OP4 E02F46 0 +OP4 E02F47 0 +OP4 E02F48 0 +OP4 E02F49 0 +OP4 E02F4A 0 +OP4 E02F4B 0 +OP4 E02F4C 0 +OP4 E02F4D 0 +OP4 E02F4E 0 +OP4 E02F4F 0 +OP4 E02F50 0 +OP4 E02F51 0 +OP4 E02F52 0 +OP4 E02F53 0 +OP4 E02F54 0 +OP4 E02F55 0 +OP4 E02F56 0 +OP4 E02F57 0 +OP4 E02F58 0 +OP4 E02F59 0 +OP4 E02F5A 0 +OP4 E02F5B 0 +OP4 E02F5C 0 +OP4 E02F5D 0 +OP4 E02F5E 0 +OP4 E02F5F 0 +OP4 E02F60 0 +OP4 E02F61 0 +OP4 E02F62 0 +OP4 E02F63 0 +OP4 E02F64 0 +OP4 E02F65 0 +OP4 E02F66 0 +OP4 E02F67 0 +OP4 E02F68 0 +OP4 E02F69 0 +OP4 E02F6A 0 +OP4 E02F6B 0 +OP4 E02F6C 0 +OP4 E02F6D 0 +OP4 E02F6E 0 +OP4 E02F6F 0 +OP4 E02F70 0 +OP4 E02F71 0 +OP4 E02F72 0 +OP4 E02F73 0 +OP4 E02F74 0 +OP4 E02F75 0 +OP4 E02F76 0 +OP4 E02F77 0 +OP4 E02F78 0 +OP4 E02F79 0 +OP4 E02F7A 0 +OP4 E02F7B 0 +OP4 E02F7C 0 +OP4 E02F7D 0 +OP4 E02F7E 0 +OP4 E02F7F 0 +OP4 E02F80 0 +OP4 E02F81 0 +OP4 E02F82 0 +OP4 E02F83 0 +OP4 E02F84 0 +OP4 E02F85 0 +OP4 E02F86 0 +OP4 E02F87 0 +OP4 E02F88 0 +OP4 E02F89 0 +OP4 E02F8A 0 +OP4 E02F8B 0 +OP4 E02F8C 0 +OP4 E02F8D 0 +OP4 E02F8E 0 +OP4 E02F8F 0 +OP4 E02F90 0 +OP4 E02F91 0 +OP4 E02F92 0 +OP4 E02F93 0 +OP4 E02F94 0 +OP4 E02F95 0 +OP4 E02F96 0 +OP4 E02F97 0 +OP4 E02F98 0 +OP4 E02F99 0 +OP4 E02F9A 0 +OP4 E02F9B 0 +OP4 E02F9C 0 +OP4 E02F9D 0 +OP4 E02F9E 0 +OP4 E02F9F 0 +OP4 E02FA0 0 +OP4 E02FA1 0 +OP4 E02FA2 0 +OP4 E02FA3 0 +OP4 E02FA4 0 +OP4 E02FA5 0 +OP4 E02FA6 0 +OP4 E02FA7 0 +OP4 E02FA8 0 +OP4 E02FA9 0 +OP4 E02FAA 0 +OP4 E02FAB 0 +OP4 E02FAC 0 +OP4 E02FAD 0 +OP4 E02FAE 0 +OP4 E02FAF 0 +OP4 E02FB0 0 +OP4 E02FB1 0 +OP4 E02FB2 0 +OP4 E02FB3 0 +OP4 E02FB4 0 +OP4 E02FB5 0 +OP4 E02FB6 0 +OP4 E02FB7 0 +OP4 E02FB8 0 +OP4 E02FB9 0 +OP4 E02FBA 0 +OP4 E02FBB 0 +OP4 E02FBC 0 +OP4 E02FBD 0 +OP4 E02FBE 0 +OP4 E02FBF 0 +OP4 E02FC0 0 +OP4 E02FC1 0 +OP4 E02FC2 0 +OP4 E02FC3 0 +OP4 E02FC4 0 +OP4 E02FC5 0 +OP4 E02FC6 0 +OP4 E02FC7 0 +OP4 E02FC8 0 +OP4 E02FC9 0 +OP4 E02FCA 0 +OP4 E02FCB 0 +OP4 E02FCC 0 +OP4 E02FCD 0 +OP4 E02FCE 0 +OP4 E02FCF 0 +OP4 E02FD0 0 +OP4 E02FD1 0 +OP4 E02FD2 0 +OP4 E02FD3 0 +OP4 E02FD4 0 +OP4 E02FD5 0 +OP4 E02FD6 0 +OP4 E02FD7 0 +OP4 E02FD8 0 +OP4 E02FD9 0 +OP4 E02FDA 0 +OP4 E02FDB 0 +OP4 E02FDC 0 +OP4 E02FDD 0 +OP4 E02FDE 0 +OP4 E02FDF 0 +OP4 E02FE0 0 +OP4 E02FE1 0 +OP4 E02FE2 0 +OP4 E02FE3 0 +OP4 E02FE4 0 +OP4 E02FE5 0 +OP4 E02FE6 0 +OP4 E02FE7 0 +OP4 E02FE8 0 +OP4 E02FE9 0 +OP4 E02FEA 0 +OP4 E02FEB 0 +OP4 E02FEC 0 +OP4 E02FED 0 +OP4 E02FEE 0 +OP4 E02FEF 0 +OP4 E02FF0 0 +OP4 E02FF1 0 +OP4 E02FF2 0 +OP4 E02FF3 0 +OP4 E02FF4 0 +OP4 E02FF5 0 +OP4 E02FF6 0 +OP4 E02FF7 0 +OP4 E02FF8 0 +OP4 E02FF9 0 +OP4 E02FFA 0 +OP4 E02FFB 0 +OP4 E02FFC 0 +OP4 E02FFD 0 +OP4 E02FFE 0 +OP4 E02FFF 0 +OP4 E03000 0 +OP4 E03001 0 +OP4 E03002 0 +OP4 E03003 0 +OP4 E03004 0 +OP4 E03005 0 +OP4 E03006 0 +OP4 E03007 0 +OP4 E03008 0 +OP4 E03009 0 +OP4 E0300A 0 +OP4 E0300B 0 +OP4 E0300C 0 +OP4 E0300D 0 +OP4 E0300E 0 +OP4 E0300F 0 +OP4 E03010 0 +OP4 E03011 0 +OP4 E03012 0 +OP4 E03013 0 +OP4 E03014 0 +OP4 E03015 0 +OP4 E03016 0 +OP4 E03017 0 +OP4 E03018 0 +OP4 E03019 0 +OP4 E0301A 0 +OP4 E0301B 0 +OP4 E0301C 0 +OP4 E0301D 0 +OP4 E0301E 0 +OP4 E0301F 0 +OP4 E03020 0 +OP4 E03021 0 +OP4 E03022 0 +OP4 E03023 0 +OP4 E03024 0 +OP4 E03025 0 +OP4 E03026 0 +OP4 E03027 0 +OP4 E03028 0 +OP4 E03029 0 +OP4 E0302A 0 +OP4 E0302B 0 +OP4 E0302C 0 +OP4 E0302D 0 +OP4 E0302E 0 +OP4 E0302F 0 +OP4 E03030 0 +OP4 E03031 0 +OP4 E03032 0 +OP4 E03033 0 +OP4 E03034 0 +OP4 E03035 0 +OP4 E03036 0 +OP4 E03037 0 +OP4 E03038 0 +OP4 E03039 0 +OP4 E0303A 0 +OP4 E0303B 0 +OP4 E0303C 0 +OP4 E0303D 0 +OP4 E0303E 0 +OP4 E0303F 0 +OP4 E03040 0 +OP4 E03041 0 +OP4 E03042 0 +OP4 E03043 0 +OP4 E03044 0 +OP4 E03045 0 +OP4 E03046 0 +OP4 E03047 0 +OP4 E03048 0 +OP4 E03049 0 +OP4 E0304A 0 +OP4 E0304B 0 +OP4 E0304C 0 +OP4 E0304D 0 +OP4 E0304E 0 +OP4 E0304F 0 +OP4 E03050 0 +OP4 E03051 0 +OP4 E03052 0 +OP4 E03053 0 +OP4 E03054 0 +OP4 E03055 0 +OP4 E03056 0 +OP4 E03057 0 +OP4 E03058 0 +OP4 E03059 0 +OP4 E0305A 0 +OP4 E0305B 0 +OP4 E0305C 0 +OP4 E0305D 0 +OP4 E0305E 0 +OP4 E0305F 0 +OP4 E03060 0 +OP4 E03061 0 +OP4 E03062 0 +OP4 E03063 0 +OP4 E03064 0 +OP4 E03065 0 +OP4 E03066 0 +OP4 E03067 0 +OP4 E03068 0 +OP4 E03069 0 +OP4 E0306A 0 +OP4 E0306B 0 +OP4 E0306C 0 +OP4 E0306D 0 +OP4 E0306E 0 +OP4 E0306F 0 +OP4 E03070 0 +OP4 E03071 0 +OP4 E03072 0 +OP4 E03073 0 +OP4 E03074 0 +OP4 E03075 0 +OP4 E03076 0 +OP4 E03077 0 +OP4 E03078 0 +OP4 E03079 0 +OP4 E0307A 0 +OP4 E0307B 0 +OP4 E0307C 0 +OP4 E0307D 0 +OP4 E0307E 0 +OP4 E0307F 0 +OP4 E03080 0 +OP4 E03081 0 +OP4 E03082 0 +OP4 E03083 0 +OP4 E03084 0 +OP4 E03085 0 +OP4 E03086 0 +OP4 E03087 0 +OP4 E03088 0 +OP4 E03089 0 +OP4 E0308A 0 +OP4 E0308B 0 +OP4 E0308C 0 +OP4 E0308D 0 +OP4 E0308E 0 +OP4 E0308F 0 +OP4 E03090 0 +OP4 E03091 0 +OP4 E03092 0 +OP4 E03093 0 +OP4 E03094 0 +OP4 E03095 0 +OP4 E03096 0 +OP4 E03097 0 +OP4 E03098 0 +OP4 E03099 0 +OP4 E0309A 0 +OP4 E0309B 0 +OP4 E0309C 0 +OP4 E0309D 0 +OP4 E0309E 0 +OP4 E0309F 0 +OP4 E030A0 0 +OP4 E030A1 0 +OP4 E030A2 0 +OP4 E030A3 0 +OP4 E030A4 0 +OP4 E030A5 0 +OP4 E030A6 0 +OP4 E030A7 0 +OP4 E030A8 0 +OP4 E030A9 0 +OP4 E030AA 0 +OP4 E030AB 0 +OP4 E030AC 0 +OP4 E030AD 0 +OP4 E030AE 0 +OP4 E030AF 0 +OP4 E030B0 0 +OP4 E030B1 0 +OP4 E030B2 0 +OP4 E030B3 0 +OP4 E030B4 0 +OP4 E030B5 0 +OP4 E030B6 0 +OP4 E030B7 0 +OP4 E030B8 0 +OP4 E030B9 0 +OP4 E030BA 0 +OP4 E030BB 0 +OP4 E030BC 0 +OP4 E030BD 0 +OP4 E030BE 0 +OP4 E030BF 0 +OP4 E030C0 0 +OP4 E030C1 0 +OP4 E030C2 0 +OP4 E030C3 0 +OP4 E030C4 0 +OP4 E030C5 0 +OP4 E030C6 0 +OP4 E030C7 0 +OP4 E030C8 0 +OP4 E030C9 0 +OP4 E030CA 0 +OP4 E030CB 0 +OP4 E030CC 0 +OP4 E030CD 0 +OP4 E030CE 0 +OP4 E030CF 0 +OP4 E030D0 0 +OP4 E030D1 0 +OP4 E030D2 0 +OP4 E030D3 0 +OP4 E030D4 0 +OP4 E030D5 0 +OP4 E030D6 0 +OP4 E030D7 0 +OP4 E030D8 0 +OP4 E030D9 0 +OP4 E030DA 0 +OP4 E030DB 0 +OP4 E030DC 0 +OP4 E030DD 0 +OP4 E030DE 0 +OP4 E030DF 0 +OP4 E030E0 0 +OP4 E030E1 0 +OP4 E030E2 0 +OP4 E030E3 0 +OP4 E030E4 0 +OP4 E030E5 0 +OP4 E030E6 0 +OP4 E030E7 0 +OP4 E030E8 0 +OP4 E030E9 0 +OP4 E030EA 0 +OP4 E030EB 0 +OP4 E030EC 0 +OP4 E030ED 0 +OP4 E030EE 0 +OP4 E030EF 0 +OP4 E030F0 0 +OP4 E030F1 0 +OP4 E030F2 0 +OP4 E030F3 0 +OP4 E030F4 0 +OP4 E030F5 0 +OP4 E030F6 0 +OP4 E030F7 0 +OP4 E030F8 0 +OP4 E030F9 0 +OP4 E030FA 0 +OP4 E030FB 0 +OP4 E030FC 0 +OP4 E030FD 0 +OP4 E030FE 0 +OP4 E030FF 0 +OP4 E03100 0 +OP4 E03101 0 +OP4 E03102 0 +OP4 E03103 0 +OP4 E03104 0 +OP4 E03105 0 +OP4 E03106 0 +OP4 E03107 0 +OP4 E03108 0 +OP4 E03109 0 +OP4 E0310A 0 +OP4 E0310B 0 +OP4 E0310C 0 +OP4 E0310D 0 +OP4 E0310E 0 +OP4 E0310F 0 +OP4 E03110 0 +OP4 E03111 0 +OP4 E03112 0 +OP4 E03113 0 +OP4 E03114 0 +OP4 E03115 0 +OP4 E03116 0 +OP4 E03117 0 +OP4 E03118 0 +OP4 E03119 0 +OP4 E0311A 0 +OP4 E0311B 0 +OP4 E0311C 0 +OP4 E0311D 0 +OP4 E0311E 0 +OP4 E0311F 0 +OP4 E03120 0 +OP4 E03121 0 +OP4 E03122 0 +OP4 E03123 0 +OP4 E03124 0 +OP4 E03125 0 +OP4 E03126 0 +OP4 E03127 0 +OP4 E03128 0 +OP4 E03129 0 +OP4 E0312A 0 +OP4 E0312B 0 +OP4 E0312C 0 +OP4 E0312D 0 +OP4 E0312E 0 +OP4 E0312F 0 +OP4 E03130 0 +OP4 E03131 0 +OP4 E03132 0 +OP4 E03133 0 +OP4 E03134 0 +OP4 E03135 0 +OP4 E03136 0 +OP4 E03137 0 +OP4 E03138 0 +OP4 E03139 0 +OP4 E0313A 0 +OP4 E0313B 0 +OP4 E0313C 0 +OP4 E0313D 0 +OP4 E0313E 0 +OP4 E0313F 0 +OP4 E03140 0 +OP4 E03141 0 +OP4 E03142 0 +OP4 E03143 0 +OP4 E03144 0 +OP4 E03145 0 +OP4 E03146 0 +OP4 E03147 0 +OP4 E03148 0 +OP4 E03149 0 +OP4 E0314A 0 +OP4 E0314B 0 +OP4 E0314C 0 +OP4 E0314D 0 +OP4 E0314E 0 +OP4 E0314F 0 +OP4 E03150 0 +OP4 E03151 0 +OP4 E03152 0 +OP4 E03153 0 +OP4 E03154 0 +OP4 E03155 0 +OP4 E03156 0 +OP4 E03157 0 +OP4 E03158 0 +OP4 E03159 0 +OP4 E0315A 0 +OP4 E0315B 0 +OP4 E0315C 0 +OP4 E0315D 0 +OP4 E0315E 0 +OP4 E0315F 0 +OP4 E03160 0 +OP4 E03161 0 +OP4 E03162 0 +OP4 E03163 0 +OP4 E03164 0 +OP4 E03165 0 +OP4 E03166 0 +OP4 E03167 0 +OP4 E03168 0 +OP4 E03169 0 +OP4 E0316A 0 +OP4 E0316B 0 +OP4 E0316C 0 +OP4 E0316D 0 +OP4 E0316E 0 +OP4 E0316F 0 +OP4 E03170 0 +OP4 E03171 0 +OP4 E03172 0 +OP4 E03173 0 +OP4 E03174 0 +OP4 E03175 0 +OP4 E03176 0 +OP4 E03177 0 +OP4 E03178 0 +OP4 E03179 0 +OP4 E0317A 0 +OP4 E0317B 0 +OP4 E0317C 0 +OP4 E0317D 0 +OP4 E0317E 0 +OP4 E0317F 0 +OP4 E03180 0 +OP4 E03181 0 +OP4 E03182 0 +OP4 E03183 0 +OP4 E03184 0 +OP4 E03185 0 +OP4 E03186 0 +OP4 E03187 0 +OP4 E03188 0 +OP4 E03189 0 +OP4 E0318A 0 +OP4 E0318B 0 +OP4 E0318C 0 +OP4 E0318D 0 +OP4 E0318E 0 +OP4 E0318F 0 +OP4 E03190 0 +OP4 E03191 0 +OP4 E03192 0 +OP4 E03193 0 +OP4 E03194 0 +OP4 E03195 0 +OP4 E03196 0 +OP4 E03197 0 +OP4 E03198 0 +OP4 E03199 0 +OP4 E0319A 0 +OP4 E0319B 0 +OP4 E0319C 0 +OP4 E0319D 0 +OP4 E0319E 0 +OP4 E0319F 0 +OP4 E031A0 0 +OP4 E031A1 0 +OP4 E031A2 0 +OP4 E031A3 0 +OP4 E031A4 0 +OP4 E031A5 0 +OP4 E031A6 0 +OP4 E031A7 0 +OP4 E031A8 0 +OP4 E031A9 0 +OP4 E031AA 0 +OP4 E031AB 0 +OP4 E031AC 0 +OP4 E031AD 0 +OP4 E031AE 0 +OP4 E031AF 0 +OP4 E031B0 0 +OP4 E031B1 0 +OP4 E031B2 0 +OP4 E031B3 0 +OP4 E031B4 0 +OP4 E031B5 0 +OP4 E031B6 0 +OP4 E031B7 0 +OP4 E031B8 0 +OP4 E031B9 0 +OP4 E031BA 0 +OP4 E031BB 0 +OP4 E031BC 0 +OP4 E031BD 0 +OP4 E031BE 0 +OP4 E031BF 0 +OP4 E031C0 0 +OP4 E031C1 0 +OP4 E031C2 0 +OP4 E031C3 0 +OP4 E031C4 0 +OP4 E031C5 0 +OP4 E031C6 0 +OP4 E031C7 0 +OP4 E031C8 0 +OP4 E031C9 0 +OP4 E031CA 0 +OP4 E031CB 0 +OP4 E031CC 0 +OP4 E031CD 0 +OP4 E031CE 0 +OP4 E031CF 0 +OP4 E031D0 0 +OP4 E031D1 0 +OP4 E031D2 0 +OP4 E031D3 0 +OP4 E031D4 0 +OP4 E031D5 0 +OP4 E031D6 0 +OP4 E031D7 0 +OP4 E031D8 0 +OP4 E031D9 0 +OP4 E031DA 0 +OP4 E031DB 0 +OP4 E031DC 0 +OP4 E031DD 0 +OP4 E031DE 0 +OP4 E031DF 0 +OP4 E031E0 0 +OP4 E031E1 0 +OP4 E031E2 0 +OP4 E031E3 0 +OP4 E031E4 0 +OP4 E031E5 0 +OP4 E031E6 0 +OP4 E031E7 0 +OP4 E031E8 0 +OP4 E031E9 0 +OP4 E031EA 0 +OP4 E031EB 0 +OP4 E031EC 0 +OP4 E031ED 0 +OP4 E031EE 0 +OP4 E031EF 0 +OP4 E031F0 0 +OP4 E031F1 0 +OP4 E031F2 0 +OP4 E031F3 0 +OP4 E031F4 0 +OP4 E031F5 0 +OP4 E031F6 0 +OP4 E031F7 0 +OP4 E031F8 0 +OP4 E031F9 0 +OP4 E031FA 0 +OP4 E031FB 0 +OP4 E031FC 0 +OP4 E031FD 0 +OP4 E031FE 0 +OP4 E031FF 0 +OP4 E03200 0 +OP4 E03201 0 +OP4 E03202 0 +OP4 E03203 0 +OP4 E03204 0 +OP4 E03205 0 +OP4 E03206 0 +OP4 E03207 0 +OP4 E03208 0 +OP4 E03209 0 +OP4 E0320A 0 +OP4 E0320B 0 +OP4 E0320C 0 +OP4 E0320D 0 +OP4 E0320E 0 +OP4 E0320F 0 +OP4 E03210 0 +OP4 E03211 0 +OP4 E03212 0 +OP4 E03213 0 +OP4 E03214 0 +OP4 E03215 0 +OP4 E03216 0 +OP4 E03217 0 +OP4 E03218 0 +OP4 E03219 0 +OP4 E0321A 0 +OP4 E0321B 0 +OP4 E0321C 0 +OP4 E0321D 0 +OP4 E0321E 0 +OP4 E0321F 0 +OP4 E03220 0 +OP4 E03221 0 +OP4 E03222 0 +OP4 E03223 0 +OP4 E03224 0 +OP4 E03225 0 +OP4 E03226 0 +OP4 E03227 0 +OP4 E03228 0 +OP4 E03229 0 +OP4 E0322A 0 +OP4 E0322B 0 +OP4 E0322C 0 +OP4 E0322D 0 +OP4 E0322E 0 +OP4 E0322F 0 +OP4 E03230 0 +OP4 E03231 0 +OP4 E03232 0 +OP4 E03233 0 +OP4 E03234 0 +OP4 E03235 0 +OP4 E03236 0 +OP4 E03237 0 +OP4 E03238 0 +OP4 E03239 0 +OP4 E0323A 0 +OP4 E0323B 0 +OP4 E0323C 0 +OP4 E0323D 0 +OP4 E0323E 0 +OP4 E0323F 0 +OP4 E03240 0 +OP4 E03241 0 +OP4 E03242 0 +OP4 E03243 0 +OP4 E03244 0 +OP4 E03245 0 +OP4 E03246 0 +OP4 E03247 0 +OP4 E03248 0 +OP4 E03249 0 +OP4 E0324A 0 +OP4 E0324B 0 +OP4 E0324C 0 +OP4 E0324D 0 +OP4 E0324E 0 +OP4 E0324F 0 +OP4 E03250 0 +OP4 E03251 0 +OP4 E03252 0 +OP4 E03253 0 +OP4 E03254 0 +OP4 E03255 0 +OP4 E03256 0 +OP4 E03257 0 +OP4 E03258 0 +OP4 E03259 0 +OP4 E0325A 0 +OP4 E0325B 0 +OP4 E0325C 0 +OP4 E0325D 0 +OP4 E0325E 0 +OP4 E0325F 0 +OP4 E03260 0 +OP4 E03261 0 +OP4 E03262 0 +OP4 E03263 0 +OP4 E03264 0 +OP4 E03265 0 +OP4 E03266 0 +OP4 E03267 0 +OP4 E03268 0 +OP4 E03269 0 +OP4 E0326A 0 +OP4 E0326B 0 +OP4 E0326C 0 +OP4 E0326D 0 +OP4 E0326E 0 +OP4 E0326F 0 +OP4 E03270 0 +OP4 E03271 0 +OP4 E03272 0 +OP4 E03273 0 +OP4 E03274 0 +OP4 E03275 0 +OP4 E03276 0 +OP4 E03277 0 +OP4 E03278 0 +OP4 E03279 0 +OP4 E0327A 0 +OP4 E0327B 0 +OP4 E0327C 0 +OP4 E0327D 0 +OP4 E0327E 0 +OP4 E0327F 0 +OP4 E03280 0 +OP4 E03281 0 +OP4 E03282 0 +OP4 E03283 0 +OP4 E03284 0 +OP4 E03285 0 +OP4 E03286 0 +OP4 E03287 0 +OP4 E03288 0 +OP4 E03289 0 +OP4 E0328A 0 +OP4 E0328B 0 +OP4 E0328C 0 +OP4 E0328D 0 +OP4 E0328E 0 +OP4 E0328F 0 +OP4 E03290 0 +OP4 E03291 0 +OP4 E03292 0 +OP4 E03293 0 +OP4 E03294 0 +OP4 E03295 0 +OP4 E03296 0 +OP4 E03297 0 +OP4 E03298 0 +OP4 E03299 0 +OP4 E0329A 0 +OP4 E0329B 0 +OP4 E0329C 0 +OP4 E0329D 0 +OP4 E0329E 0 +OP4 E0329F 0 +OP4 E032A0 0 +OP4 E032A1 0 +OP4 E032A2 0 +OP4 E032A3 0 +OP4 E032A4 0 +OP4 E032A5 0 +OP4 E032A6 0 +OP4 E032A7 0 +OP4 E032A8 0 +OP4 E032A9 0 +OP4 E032AA 0 +OP4 E032AB 0 +OP4 E032AC 0 +OP4 E032AD 0 +OP4 E032AE 0 +OP4 E032AF 0 +OP4 E032B0 0 +OP4 E032B1 0 +OP4 E032B2 0 +OP4 E032B3 0 +OP4 E032B4 0 +OP4 E032B5 0 +OP4 E032B6 0 +OP4 E032B7 0 +OP4 E032B8 0 +OP4 E032B9 0 +OP4 E032BA 0 +OP4 E032BB 0 +OP4 E032BC 0 +OP4 E032BD 0 +OP4 E032BE 0 +OP4 E032BF 0 +OP4 E032C0 0 +OP4 E032C1 0 +OP4 E032C2 0 +OP4 E032C3 0 +OP4 E032C4 0 +OP4 E032C5 0 +OP4 E032C6 0 +OP4 E032C7 0 +OP4 E032C8 0 +OP4 E032C9 0 +OP4 E032CA 0 +OP4 E032CB 0 +OP4 E032CC 0 +OP4 E032CD 0 +OP4 E032CE 0 +OP4 E032CF 0 +OP4 E032D0 0 +OP4 E032D1 0 +OP4 E032D2 0 +OP4 E032D3 0 +OP4 E032D4 0 +OP4 E032D5 0 +OP4 E032D6 0 +OP4 E032D7 0 +OP4 E032D8 0 +OP4 E032D9 0 +OP4 E032DA 0 +OP4 E032DB 0 +OP4 E032DC 0 +OP4 E032DD 0 +OP4 E032DE 0 +OP4 E032DF 0 +OP4 E032E0 0 +OP4 E032E1 0 +OP4 E032E2 0 +OP4 E032E3 0 +OP4 E032E4 0 +OP4 E032E5 0 +OP4 E032E6 0 +OP4 E032E7 0 +OP4 E032E8 0 +OP4 E032E9 0 +OP4 E032EA 0 +OP4 E032EB 0 +OP4 E032EC 0 +OP4 E032ED 0 +OP4 E032EE 0 +OP4 E032EF 0 +OP4 E032F0 0 +OP4 E032F1 0 +OP4 E032F2 0 +OP4 E032F3 0 +OP4 E032F4 0 +OP4 E032F5 0 +OP4 E032F6 0 +OP4 E032F7 0 +OP4 E032F8 0 +OP4 E032F9 0 +OP4 E032FA 0 +OP4 E032FB 0 +OP4 E032FC 0 +OP4 E032FD 0 +OP4 E032FE 0 +OP4 E032FF 0 +OP4 E03300 0 +OP4 E03301 0 +OP4 E03302 0 +OP4 E03303 0 +OP4 E03304 0 +OP4 E03305 0 +OP4 E03306 0 +OP4 E03307 0 +OP4 E03308 0 +OP4 E03309 0 +OP4 E0330A 0 +OP4 E0330B 0 +OP4 E0330C 0 +OP4 E0330D 0 +OP4 E0330E 0 +OP4 E0330F 0 +OP4 E03310 0 +OP4 E03311 0 +OP4 E03312 0 +OP4 E03313 0 +OP4 E03314 0 +OP4 E03315 0 +OP4 E03316 0 +OP4 E03317 0 +OP4 E03318 0 +OP4 E03319 0 +OP4 E0331A 0 +OP4 E0331B 0 +OP4 E0331C 0 +OP4 E0331D 0 +OP4 E0331E 0 +OP4 E0331F 0 +OP4 E03320 0 +OP4 E03321 0 +OP4 E03322 0 +OP4 E03323 0 +OP4 E03324 0 +OP4 E03325 0 +OP4 E03326 0 +OP4 E03327 0 +OP4 E03328 0 +OP4 E03329 0 +OP4 E0332A 0 +OP4 E0332B 0 +OP4 E0332C 0 +OP4 E0332D 0 +OP4 E0332E 0 +OP4 E0332F 0 +OP4 E03330 0 +OP4 E03331 0 +OP4 E03332 0 +OP4 E03333 0 +OP4 E03334 0 +OP4 E03335 0 +OP4 E03336 0 +OP4 E03337 0 +OP4 E03338 0 +OP4 E03339 0 +OP4 E0333A 0 +OP4 E0333B 0 +OP4 E0333C 0 +OP4 E0333D 0 +OP4 E0333E 0 +OP4 E0333F 0 +OP4 E03340 0 +OP4 E03341 0 +OP4 E03342 0 +OP4 E03343 0 +OP4 E03344 0 +OP4 E03345 0 +OP4 E03346 0 +OP4 E03347 0 +OP4 E03348 0 +OP4 E03349 0 +OP4 E0334A 0 +OP4 E0334B 0 +OP4 E0334C 0 +OP4 E0334D 0 +OP4 E0334E 0 +OP4 E0334F 0 +OP4 E03350 0 +OP4 E03351 0 +OP4 E03352 0 +OP4 E03353 0 +OP4 E03354 0 +OP4 E03355 0 +OP4 E03356 0 +OP4 E03357 0 +OP4 E03358 0 +OP4 E03359 0 +OP4 E0335A 0 +OP4 E0335B 0 +OP4 E0335C 0 +OP4 E0335D 0 +OP4 E0335E 0 +OP4 E0335F 0 +OP4 E03360 0 +OP4 E03361 0 +OP4 E03362 0 +OP4 E03363 0 +OP4 E03364 0 +OP4 E03365 0 +OP4 E03366 0 +OP4 E03367 0 +OP4 E03368 0 +OP4 E03369 0 +OP4 E0336A 0 +OP4 E0336B 0 +OP4 E0336C 0 +OP4 E0336D 0 +OP4 E0336E 0 +OP4 E0336F 0 +OP4 E03370 0 +OP4 E03371 0 +OP4 E03372 0 +OP4 E03373 0 +OP4 E03374 0 +OP4 E03375 0 +OP4 E03376 0 +OP4 E03377 0 +OP4 E03378 0 +OP4 E03379 0 +OP4 E0337A 0 +OP4 E0337B 0 +OP4 E0337C 0 +OP4 E0337D 0 +OP4 E0337E 0 +OP4 E0337F 0 +OP4 E03380 0 +OP4 E03381 0 +OP4 E03382 0 +OP4 E03383 0 +OP4 E03384 0 +OP4 E03385 0 +OP4 E03386 0 +OP4 E03387 0 +OP4 E03388 0 +OP4 E03389 0 +OP4 E0338A 0 +OP4 E0338B 0 +OP4 E0338C 0 +OP4 E0338D 0 +OP4 E0338E 0 +OP4 E0338F 0 +OP4 E03390 0 +OP4 E03391 0 +OP4 E03392 0 +OP4 E03393 0 +OP4 E03394 0 +OP4 E03395 0 +OP4 E03396 0 +OP4 E03397 0 +OP4 E03398 0 +OP4 E03399 0 +OP4 E0339A 0 +OP4 E0339B 0 +OP4 E0339C 0 +OP4 E0339D 0 +OP4 E0339E 0 +OP4 E0339F 0 +OP4 E033A0 0 +OP4 E033A1 0 +OP4 E033A2 0 +OP4 E033A3 0 +OP4 E033A4 0 +OP4 E033A5 0 +OP4 E033A6 0 +OP4 E033A7 0 +OP4 E033A8 0 +OP4 E033A9 0 +OP4 E033AA 0 +OP4 E033AB 0 +OP4 E033AC 0 +OP4 E033AD 0 +OP4 E033AE 0 +OP4 E033AF 0 +OP4 E033B0 0 +OP4 E033B1 0 +OP4 E033B2 0 +OP4 E033B3 0 +OP4 E033B4 0 +OP4 E033B5 0 +OP4 E033B6 0 +OP4 E033B7 0 +OP4 E033B8 0 +OP4 E033B9 0 +OP4 E033BA 0 +OP4 E033BB 0 +OP4 E033BC 0 +OP4 E033BD 0 +OP4 E033BE 0 +OP4 E033BF 0 +OP4 E033C0 0 +OP4 E033C1 0 +OP4 E033C2 0 +OP4 E033C3 0 +OP4 E033C4 0 +OP4 E033C5 0 +OP4 E033C6 0 +OP4 E033C7 0 +OP4 E033C8 0 +OP4 E033C9 0 +OP4 E033CA 0 +OP4 E033CB 0 +OP4 E033CC 0 +OP4 E033CD 0 +OP4 E033CE 0 +OP4 E033CF 0 +OP4 E033D0 0 +OP4 E033D1 0 +OP4 E033D2 0 +OP4 E033D3 0 +OP4 E033D4 0 +OP4 E033D5 0 +OP4 E033D6 0 +OP4 E033D7 0 +OP4 E033D8 0 +OP4 E033D9 0 +OP4 E033DA 0 +OP4 E033DB 0 +OP4 E033DC 0 +OP4 E033DD 0 +OP4 E033DE 0 +OP4 E033DF 0 +OP4 E033E0 0 +OP4 E033E1 0 +OP4 E033E2 0 +OP4 E033E3 0 +OP4 E033E4 0 +OP4 E033E5 0 +OP4 E033E6 0 +OP4 E033E7 0 +OP4 E033E8 0 +OP4 E033E9 0 +OP4 E033EA 0 +OP4 E033EB 0 +OP4 E033EC 0 +OP4 E033ED 0 +OP4 E033EE 0 +OP4 E033EF 0 +OP4 E033F0 0 +OP4 E033F1 0 +OP4 E033F2 0 +OP4 E033F3 0 +OP4 E033F4 0 +OP4 E033F5 0 +OP4 E033F6 0 +OP4 E033F7 0 +OP4 E033F8 0 +OP4 E033F9 0 +OP4 E033FA 0 +OP4 E033FB 0 +OP4 E033FC 0 +OP4 E033FD 0 +OP4 E033FE 0 +OP4 E033FF 0 +OP4 E03400 0 +OP4 E03401 0 +OP4 E03402 0 +OP4 E03403 0 +OP4 E03404 0 +OP4 E03405 0 +OP4 E03406 0 +OP4 E03407 0 +OP4 E03408 0 +OP4 E03409 0 +OP4 E0340A 0 +OP4 E0340B 0 +OP4 E0340C 0 +OP4 E0340D 0 +OP4 E0340E 0 +OP4 E0340F 0 +OP4 E03410 0 +OP4 E03411 0 +OP4 E03412 0 +OP4 E03413 0 +OP4 E03414 0 +OP4 E03415 0 +OP4 E03416 0 +OP4 E03417 0 +OP4 E03418 0 +OP4 E03419 0 +OP4 E0341A 0 +OP4 E0341B 0 +OP4 E0341C 0 +OP4 E0341D 0 +OP4 E0341E 0 +OP4 E0341F 0 +OP4 E03420 0 +OP4 E03421 0 +OP4 E03422 0 +OP4 E03423 0 +OP4 E03424 0 +OP4 E03425 0 +OP4 E03426 0 +OP4 E03427 0 +OP4 E03428 0 +OP4 E03429 0 +OP4 E0342A 0 +OP4 E0342B 0 +OP4 E0342C 0 +OP4 E0342D 0 +OP4 E0342E 0 +OP4 E0342F 0 +OP4 E03430 0 +OP4 E03431 0 +OP4 E03432 0 +OP4 E03433 0 +OP4 E03434 0 +OP4 E03435 0 +OP4 E03436 0 +OP4 E03437 0 +OP4 E03438 0 +OP4 E03439 0 +OP4 E0343A 0 +OP4 E0343B 0 +OP4 E0343C 0 +OP4 E0343D 0 +OP4 E0343E 0 +OP4 E0343F 0 +OP4 E03440 0 +OP4 E03441 0 +OP4 E03442 0 +OP4 E03443 0 +OP4 E03444 0 +OP4 E03445 0 +OP4 E03446 0 +OP4 E03447 0 +OP4 E03448 0 +OP4 E03449 0 +OP4 E0344A 0 +OP4 E0344B 0 +OP4 E0344C 0 +OP4 E0344D 0 +OP4 E0344E 0 +OP4 E0344F 0 +OP4 E03450 0 +OP4 E03451 0 +OP4 E03452 0 +OP4 E03453 0 +OP4 E03454 0 +OP4 E03455 0 +OP4 E03456 0 +OP4 E03457 0 +OP4 E03458 0 +OP4 E03459 0 +OP4 E0345A 0 +OP4 E0345B 0 +OP4 E0345C 0 +OP4 E0345D 0 +OP4 E0345E 0 +OP4 E0345F 0 +OP4 E03460 0 +OP4 E03461 0 +OP4 E03462 0 +OP4 E03463 0 +OP4 E03464 0 +OP4 E03465 0 +OP4 E03466 0 +OP4 E03467 0 +OP4 E03468 0 +OP4 E03469 0 +OP4 E0346A 0 +OP4 E0346B 0 +OP4 E0346C 0 +OP4 E0346D 0 +OP4 E0346E 0 +OP4 E0346F 0 +OP4 E03470 0 +OP4 E03471 0 +OP4 E03472 0 +OP4 E03473 0 +OP4 E03474 0 +OP4 E03475 0 +OP4 E03476 0 +OP4 E03477 0 +OP4 E03478 0 +OP4 E03479 0 +OP4 E0347A 0 +OP4 E0347B 0 +OP4 E0347C 0 +OP4 E0347D 0 +OP4 E0347E 0 +OP4 E0347F 0 +OP4 E03480 0 +OP4 E03481 0 +OP4 E03482 0 +OP4 E03483 0 +OP4 E03484 0 +OP4 E03485 0 +OP4 E03486 0 +OP4 E03487 0 +OP4 E03488 0 +OP4 E03489 0 +OP4 E0348A 0 +OP4 E0348B 0 +OP4 E0348C 0 +OP4 E0348D 0 +OP4 E0348E 0 +OP4 E0348F 0 +OP4 E03490 0 +OP4 E03491 0 +OP4 E03492 0 +OP4 E03493 0 +OP4 E03494 0 +OP4 E03495 0 +OP4 E03496 0 +OP4 E03497 0 +OP4 E03498 0 +OP4 E03499 0 +OP4 E0349A 0 +OP4 E0349B 0 +OP4 E0349C 0 +OP4 E0349D 0 +OP4 E0349E 0 +OP4 E0349F 0 +OP4 E034A0 0 +OP4 E034A1 0 +OP4 E034A2 0 +OP4 E034A3 0 +OP4 E034A4 0 +OP4 E034A5 0 +OP4 E034A6 0 +OP4 E034A7 0 +OP4 E034A8 0 +OP4 E034A9 0 +OP4 E034AA 0 +OP4 E034AB 0 +OP4 E034AC 0 +OP4 E034AD 0 +OP4 E034AE 0 +OP4 E034AF 0 +OP4 E034B0 0 +OP4 E034B1 0 +OP4 E034B2 0 +OP4 E034B3 0 +OP4 E034B4 0 +OP4 E034B5 0 +OP4 E034B6 0 +OP4 E034B7 0 +OP4 E034B8 0 +OP4 E034B9 0 +OP4 E034BA 0 +OP4 E034BB 0 +OP4 E034BC 0 +OP4 E034BD 0 +OP4 E034BE 0 +OP4 E034BF 0 +OP4 E034C0 0 +OP4 E034C1 0 +OP4 E034C2 0 +OP4 E034C3 0 +OP4 E034C4 0 +OP4 E034C5 0 +OP4 E034C6 0 +OP4 E034C7 0 +OP4 E034C8 0 +OP4 E034C9 0 +OP4 E034CA 0 +OP4 E034CB 0 +OP4 E034CC 0 +OP4 E034CD 0 +OP4 E034CE 0 +OP4 E034CF 0 +OP4 E034D0 0 +OP4 E034D1 0 +OP4 E034D2 0 +OP4 E034D3 0 +OP4 E034D4 0 +OP4 E034D5 0 +OP4 E034D6 0 +OP4 E034D7 0 +OP4 E034D8 0 +OP4 E034D9 0 +OP4 E034DA 0 +OP4 E034DB 0 +OP4 E034DC 0 +OP4 E034DD 0 +OP4 E034DE 0 +OP4 E034DF 0 +OP4 E034E0 0 +OP4 E034E1 0 +OP4 E034E2 0 +OP4 E034E3 0 +OP4 E034E4 0 +OP4 E034E5 0 +OP4 E034E6 0 +OP4 E034E7 0 +OP4 E034E8 0 +OP4 E034E9 0 +OP4 E034EA 0 +OP4 E034EB 0 +OP4 E034EC 0 +OP4 E034ED 0 +OP4 E034EE 0 +OP4 E034EF 0 +OP4 E034F0 0 +OP4 E034F1 0 +OP4 E034F2 0 +OP4 E034F3 0 +OP4 E034F4 0 +OP4 E034F5 0 +OP4 E034F6 0 +OP4 E034F7 0 +OP4 E034F8 0 +OP4 E034F9 0 +OP4 E034FA 0 +OP4 E034FB 0 +OP4 E034FC 0 +OP4 E034FD 0 +OP4 E034FE 0 +OP4 E034FF 0 +OP4 E03500 0 +OP4 E03501 0 +OP4 E03502 0 +OP4 E03503 0 +OP4 E03504 0 +OP4 E03505 0 +OP4 E03506 0 +OP4 E03507 0 +OP4 E03508 0 +OP4 E03509 0 +OP4 E0350A 0 +OP4 E0350B 0 +OP4 E0350C 0 +OP4 E0350D 0 +OP4 E0350E 0 +OP4 E0350F 0 +OP4 E03510 0 +OP4 E03511 0 +OP4 E03512 0 +OP4 E03513 0 +OP4 E03514 0 +OP4 E03515 0 +OP4 E03516 0 +OP4 E03517 0 +OP4 E03518 0 +OP4 E03519 0 +OP4 E0351A 0 +OP4 E0351B 0 +OP4 E0351C 0 +OP4 E0351D 0 +OP4 E0351E 0 +OP4 E0351F 0 +OP4 E03520 0 +OP4 E03521 0 +OP4 E03522 0 +OP4 E03523 0 +OP4 E03524 0 +OP4 E03525 0 +OP4 E03526 0 +OP4 E03527 0 +OP4 E03528 0 +OP4 E03529 0 +OP4 E0352A 0 +OP4 E0352B 0 +OP4 E0352C 0 +OP4 E0352D 0 +OP4 E0352E 0 +OP4 E0352F 0 +OP4 E03530 0 +OP4 E03531 0 +OP4 E03532 0 +OP4 E03533 0 +OP4 E03534 0 +OP4 E03535 0 +OP4 E03536 0 +OP4 E03537 0 +OP4 E03538 0 +OP4 E03539 0 +OP4 E0353A 0 +OP4 E0353B 0 +OP4 E0353C 0 +OP4 E0353D 0 +OP4 E0353E 0 +OP4 E0353F 0 +OP4 E03540 0 +OP4 E03541 0 +OP4 E03542 0 +OP4 E03543 0 +OP4 E03544 0 +OP4 E03545 0 +OP4 E03546 0 +OP4 E03547 0 +OP4 E03548 0 +OP4 E03549 0 +OP4 E0354A 0 +OP4 E0354B 0 +OP4 E0354C 0 +OP4 E0354D 0 +OP4 E0354E 0 +OP4 E0354F 0 +OP4 E03550 0 +OP4 E03551 0 +OP4 E03552 0 +OP4 E03553 0 +OP4 E03554 0 +OP4 E03555 0 +OP4 E03556 0 +OP4 E03557 0 +OP4 E03558 0 +OP4 E03559 0 +OP4 E0355A 0 +OP4 E0355B 0 +OP4 E0355C 0 +OP4 E0355D 0 +OP4 E0355E 0 +OP4 E0355F 0 +OP4 E03560 0 +OP4 E03561 0 +OP4 E03562 0 +OP4 E03563 0 +OP4 E03564 0 +OP4 E03565 0 +OP4 E03566 0 +OP4 E03567 0 +OP4 E03568 0 +OP4 E03569 0 +OP4 E0356A 0 +OP4 E0356B 0 +OP4 E0356C 0 +OP4 E0356D 0 +OP4 E0356E 0 +OP4 E0356F 0 +OP4 E03570 0 +OP4 E03571 0 +OP4 E03572 0 +OP4 E03573 0 +OP4 E03574 0 +OP4 E03575 0 +OP4 E03576 0 +OP4 E03577 0 +OP4 E03578 0 +OP4 E03579 0 +OP4 E0357A 0 +OP4 E0357B 0 +OP4 E0357C 0 +OP4 E0357D 0 +OP4 E0357E 0 +OP4 E0357F 0 +OP4 E03580 0 +OP4 E03581 0 +OP4 E03582 0 +OP4 E03583 0 +OP4 E03584 0 +OP4 E03585 0 +OP4 E03586 0 +OP4 E03587 0 +OP4 E03588 0 +OP4 E03589 0 +OP4 E0358A 0 +OP4 E0358B 0 +OP4 E0358C 0 +OP4 E0358D 0 +OP4 E0358E 0 +OP4 E0358F 0 +OP4 E03590 0 +OP4 E03591 0 +OP4 E03592 0 +OP4 E03593 0 +OP4 E03594 0 +OP4 E03595 0 +OP4 E03596 0 +OP4 E03597 0 +OP4 E03598 0 +OP4 E03599 0 +OP4 E0359A 0 +OP4 E0359B 0 +OP4 E0359C 0 +OP4 E0359D 0 +OP4 E0359E 0 +OP4 E0359F 0 +OP4 E035A0 0 +OP4 E035A1 0 +OP4 E035A2 0 +OP4 E035A3 0 +OP4 E035A4 0 +OP4 E035A5 0 +OP4 E035A6 0 +OP4 E035A7 0 +OP4 E035A8 0 +OP4 E035A9 0 +OP4 E035AA 0 +OP4 E035AB 0 +OP4 E035AC 0 +OP4 E035AD 0 +OP4 E035AE 0 +OP4 E035AF 0 +OP4 E035B0 0 +OP4 E035B1 0 +OP4 E035B2 0 +OP4 E035B3 0 +OP4 E035B4 0 +OP4 E035B5 0 +OP4 E035B6 0 +OP4 E035B7 0 +OP4 E035B8 0 +OP4 E035B9 0 +OP4 E035BA 0 +OP4 E035BB 0 +OP4 E035BC 0 +OP4 E035BD 0 +OP4 E035BE 0 +OP4 E035BF 0 +OP4 E035C0 0 +OP4 E035C1 0 +OP4 E035C2 0 +OP4 E035C3 0 +OP4 E035C4 0 +OP4 E035C5 0 +OP4 E035C6 0 +OP4 E035C7 0 +OP4 E035C8 0 +OP4 E035C9 0 +OP4 E035CA 0 +OP4 E035CB 0 +OP4 E035CC 0 +OP4 E035CD 0 +OP4 E035CE 0 +OP4 E035CF 0 +OP4 E035D0 0 +OP4 E035D1 0 +OP4 E035D2 0 +OP4 E035D3 0 +OP4 E035D4 0 +OP4 E035D5 0 +OP4 E035D6 0 +OP4 E035D7 0 +OP4 E035D8 0 +OP4 E035D9 0 +OP4 E035DA 0 +OP4 E035DB 0 +OP4 E035DC 0 +OP4 E035DD 0 +OP4 E035DE 0 +OP4 E035DF 0 +OP4 E035E0 0 +OP4 E035E1 0 +OP4 E035E2 0 +OP4 E035E3 0 +OP4 E035E4 0 +OP4 E035E5 0 +OP4 E035E6 0 +OP4 E035E7 0 +OP4 E035E8 0 +OP4 E035E9 0 +OP4 E035EA 0 +OP4 E035EB 0 +OP4 E035EC 0 +OP4 E035ED 0 +OP4 E035EE 0 +OP4 E035EF 0 +OP4 E035F0 0 +OP4 E035F1 0 +OP4 E035F2 0 +OP4 E035F3 0 +OP4 E035F4 0 +OP4 E035F5 0 +OP4 E035F6 0 +OP4 E035F7 0 +OP4 E035F8 0 +OP4 E035F9 0 +OP4 E035FA 0 +OP4 E035FB 0 +OP4 E035FC 0 +OP4 E035FD 0 +OP4 E035FE 0 +OP4 E035FF 0 +OP4 E03600 0 +OP4 E03601 0 +OP4 E03602 0 +OP4 E03603 0 +OP4 E03604 0 +OP4 E03605 0 +OP4 E03606 0 +OP4 E03607 0 +OP4 E03608 0 +OP4 E03609 0 +OP4 E0360A 0 +OP4 E0360B 0 +OP4 E0360C 0 +OP4 E0360D 0 +OP4 E0360E 0 +OP4 E0360F 0 +OP4 E03610 0 +OP4 E03611 0 +OP4 E03612 0 +OP4 E03613 0 +OP4 E03614 0 +OP4 E03615 0 +OP4 E03616 0 +OP4 E03617 0 +OP4 E03618 0 +OP4 E03619 0 +OP4 E0361A 0 +OP4 E0361B 0 +OP4 E0361C 0 +OP4 E0361D 0 +OP4 E0361E 0 +OP4 E0361F 0 +OP4 E03620 0 +OP4 E03621 0 +OP4 E03622 0 +OP4 E03623 0 +OP4 E03624 0 +OP4 E03625 0 +OP4 E03626 0 +OP4 E03627 0 +OP4 E03628 0 +OP4 E03629 0 +OP4 E0362A 0 +OP4 E0362B 0 +OP4 E0362C 0 +OP4 E0362D 0 +OP4 E0362E 0 +OP4 E0362F 0 +OP4 E03630 0 +OP4 E03631 0 +OP4 E03632 0 +OP4 E03633 0 +OP4 E03634 0 +OP4 E03635 0 +OP4 E03636 0 +OP4 E03637 0 +OP4 E03638 0 +OP4 E03639 0 +OP4 E0363A 0 +OP4 E0363B 0 +OP4 E0363C 0 +OP4 E0363D 0 +OP4 E0363E 0 +OP4 E0363F 0 +OP4 E03640 0 +OP4 E03641 0 +OP4 E03642 0 +OP4 E03643 0 +OP4 E03644 0 +OP4 E03645 0 +OP4 E03646 0 +OP4 E03647 0 +OP4 E03648 0 +OP4 E03649 0 +OP4 E0364A 0 +OP4 E0364B 0 +OP4 E0364C 0 +OP4 E0364D 0 +OP4 E0364E 0 +OP4 E0364F 0 +OP4 E03650 0 +OP4 E03651 0 +OP4 E03652 0 +OP4 E03653 0 +OP4 E03654 0 +OP4 E03655 0 +OP4 E03656 0 +OP4 E03657 0 +OP4 E03658 0 +OP4 E03659 0 +OP4 E0365A 0 +OP4 E0365B 0 +OP4 E0365C 0 +OP4 E0365D 0 +OP4 E0365E 0 +OP4 E0365F 0 +OP4 E03660 0 +OP4 E03661 0 +OP4 E03662 0 +OP4 E03663 0 +OP4 E03664 0 +OP4 E03665 0 +OP4 E03666 0 +OP4 E03667 0 +OP4 E03668 0 +OP4 E03669 0 +OP4 E0366A 0 +OP4 E0366B 0 +OP4 E0366C 0 +OP4 E0366D 0 +OP4 E0366E 0 +OP4 E0366F 0 +OP4 E03670 0 +OP4 E03671 0 +OP4 E03672 0 +OP4 E03673 0 +OP4 E03674 0 +OP4 E03675 0 +OP4 E03676 0 +OP4 E03677 0 +OP4 E03678 0 +OP4 E03679 0 +OP4 E0367A 0 +OP4 E0367B 0 +OP4 E0367C 0 +OP4 E0367D 0 +OP4 E0367E 0 +OP4 E0367F 0 +OP4 E03680 0 +OP4 E03681 0 +OP4 E03682 0 +OP4 E03683 0 +OP4 E03684 0 +OP4 E03685 0 +OP4 E03686 0 +OP4 E03687 0 +OP4 E03688 0 +OP4 E03689 0 +OP4 E0368A 0 +OP4 E0368B 0 +OP4 E0368C 0 +OP4 E0368D 0 +OP4 E0368E 0 +OP4 E0368F 0 +OP4 E03690 0 +OP4 E03691 0 +OP4 E03692 0 +OP4 E03693 0 +OP4 E03694 0 +OP4 E03695 0 +OP4 E03696 0 +OP4 E03697 0 +OP4 E03698 0 +OP4 E03699 0 +OP4 E0369A 0 +OP4 E0369B 0 +OP4 E0369C 0 +OP4 E0369D 0 +OP4 E0369E 0 +OP4 E0369F 0 +OP4 E036A0 0 +OP4 E036A1 0 +OP4 E036A2 0 +OP4 E036A3 0 +OP4 E036A4 0 +OP4 E036A5 0 +OP4 E036A6 0 +OP4 E036A7 0 +OP4 E036A8 0 +OP4 E036A9 0 +OP4 E036AA 0 +OP4 E036AB 0 +OP4 E036AC 0 +OP4 E036AD 0 +OP4 E036AE 0 +OP4 E036AF 0 +OP4 E036B0 0 +OP4 E036B1 0 +OP4 E036B2 0 +OP4 E036B3 0 +OP4 E036B4 0 +OP4 E036B5 0 +OP4 E036B6 0 +OP4 E036B7 0 +OP4 E036B8 0 +OP4 E036B9 0 +OP4 E036BA 0 +OP4 E036BB 0 +OP4 E036BC 0 +OP4 E036BD 0 +OP4 E036BE 0 +OP4 E036BF 0 +OP4 E036C0 0 +OP4 E036C1 0 +OP4 E036C2 0 +OP4 E036C3 0 +OP4 E036C4 0 +OP4 E036C5 0 +OP4 E036C6 0 +OP4 E036C7 0 +OP4 E036C8 0 +OP4 E036C9 0 +OP4 E036CA 0 +OP4 E036CB 0 +OP4 E036CC 0 +OP4 E036CD 0 +OP4 E036CE 0 +OP4 E036CF 0 +OP4 E036D0 0 +OP4 E036D1 0 +OP4 E036D2 0 +OP4 E036D3 0 +OP4 E036D4 0 +OP4 E036D5 0 +OP4 E036D6 0 +OP4 E036D7 0 +OP4 E036D8 0 +OP4 E036D9 0 +OP4 E036DA 0 +OP4 E036DB 0 +OP4 E036DC 0 +OP4 E036DD 0 +OP4 E036DE 0 +OP4 E036DF 0 +OP4 E036E0 0 +OP4 E036E1 0 +OP4 E036E2 0 +OP4 E036E3 0 +OP4 E036E4 0 +OP4 E036E5 0 +OP4 E036E6 0 +OP4 E036E7 0 +OP4 E036E8 0 +OP4 E036E9 0 +OP4 E036EA 0 +OP4 E036EB 0 +OP4 E036EC 0 +OP4 E036ED 0 +OP4 E036EE 0 +OP4 E036EF 0 +OP4 E036F0 0 +OP4 E036F1 0 +OP4 E036F2 0 +OP4 E036F3 0 +OP4 E036F4 0 +OP4 E036F5 0 +OP4 E036F6 0 +OP4 E036F7 0 +OP4 E036F8 0 +OP4 E036F9 0 +OP4 E036FA 0 +OP4 E036FB 0 +OP4 E036FC 0 +OP4 E036FD 0 +OP4 E036FE 0 +OP4 E036FF 0 +OP4 E03700 0 +OP4 E03701 0 +OP4 E03702 0 +OP4 E03703 0 +OP4 E03704 0 +OP4 E03705 0 +OP4 E03706 0 +OP4 E03707 0 +OP4 E03708 0 +OP4 E03709 0 +OP4 E0370A 0 +OP4 E0370B 0 +OP4 E0370C 0 +OP4 E0370D 0 +OP4 E0370E 0 +OP4 E0370F 0 +OP4 E03710 0 +OP4 E03711 0 +OP4 E03712 0 +OP4 E03713 0 +OP4 E03714 0 +OP4 E03715 0 +OP4 E03716 0 +OP4 E03717 0 +OP4 E03718 0 +OP4 E03719 0 +OP4 E0371A 0 +OP4 E0371B 0 +OP4 E0371C 0 +OP4 E0371D 0 +OP4 E0371E 0 +OP4 E0371F 0 +OP4 E03720 0 +OP4 E03721 0 +OP4 E03722 0 +OP4 E03723 0 +OP4 E03724 0 +OP4 E03725 0 +OP4 E03726 0 +OP4 E03727 0 +OP4 E03728 0 +OP4 E03729 0 +OP4 E0372A 0 +OP4 E0372B 0 +OP4 E0372C 0 +OP4 E0372D 0 +OP4 E0372E 0 +OP4 E0372F 0 +OP4 E03730 0 +OP4 E03731 0 +OP4 E03732 0 +OP4 E03733 0 +OP4 E03734 0 +OP4 E03735 0 +OP4 E03736 0 +OP4 E03737 0 +OP4 E03738 0 +OP4 E03739 0 +OP4 E0373A 0 +OP4 E0373B 0 +OP4 E0373C 0 +OP4 E0373D 0 +OP4 E0373E 0 +OP4 E0373F 0 +OP4 E03740 0 +OP4 E03741 0 +OP4 E03742 0 +OP4 E03743 0 +OP4 E03744 0 +OP4 E03745 0 +OP4 E03746 0 +OP4 E03747 0 +OP4 E03748 0 +OP4 E03749 0 +OP4 E0374A 0 +OP4 E0374B 0 +OP4 E0374C 0 +OP4 E0374D 0 +OP4 E0374E 0 +OP4 E0374F 0 +OP4 E03750 0 +OP4 E03751 0 +OP4 E03752 0 +OP4 E03753 0 +OP4 E03754 0 +OP4 E03755 0 +OP4 E03756 0 +OP4 E03757 0 +OP4 E03758 0 +OP4 E03759 0 +OP4 E0375A 0 +OP4 E0375B 0 +OP4 E0375C 0 +OP4 E0375D 0 +OP4 E0375E 0 +OP4 E0375F 0 +OP4 E03760 0 +OP4 E03761 0 +OP4 E03762 0 +OP4 E03763 0 +OP4 E03764 0 +OP4 E03765 0 +OP4 E03766 0 +OP4 E03767 0 +OP4 E03768 0 +OP4 E03769 0 +OP4 E0376A 0 +OP4 E0376B 0 +OP4 E0376C 0 +OP4 E0376D 0 +OP4 E0376E 0 +OP4 E0376F 0 +OP4 E03770 0 +OP4 E03771 0 +OP4 E03772 0 +OP4 E03773 0 +OP4 E03774 0 +OP4 E03775 0 +OP4 E03776 0 +OP4 E03777 0 +OP4 E03778 0 +OP4 E03779 0 +OP4 E0377A 0 +OP4 E0377B 0 +OP4 E0377C 0 +OP4 E0377D 0 +OP4 E0377E 0 +OP4 E0377F 0 +OP4 E03780 0 +OP4 E03781 0 +OP4 E03782 0 +OP4 E03783 0 +OP4 E03784 0 +OP4 E03785 0 +OP4 E03786 0 +OP4 E03787 0 +OP4 E03788 0 +OP4 E03789 0 +OP4 E0378A 0 +OP4 E0378B 0 +OP4 E0378C 0 +OP4 E0378D 0 +OP4 E0378E 0 +OP4 E0378F 0 +OP4 E03790 0 +OP4 E03791 0 +OP4 E03792 0 +OP4 E03793 0 +OP4 E03794 0 +OP4 E03795 0 +OP4 E03796 0 +OP4 E03797 0 +OP4 E03798 0 +OP4 E03799 0 +OP4 E0379A 0 +OP4 E0379B 0 +OP4 E0379C 0 +OP4 E0379D 0 +OP4 E0379E 0 +OP4 E0379F 0 +OP4 E037A0 0 +OP4 E037A1 0 +OP4 E037A2 0 +OP4 E037A3 0 +OP4 E037A4 0 +OP4 E037A5 0 +OP4 E037A6 0 +OP4 E037A7 0 +OP4 E037A8 0 +OP4 E037A9 0 +OP4 E037AA 0 +OP4 E037AB 0 +OP4 E037AC 0 +OP4 E037AD 0 +OP4 E037AE 0 +OP4 E037AF 0 +OP4 E037B0 0 +OP4 E037B1 0 +OP4 E037B2 0 +OP4 E037B3 0 +OP4 E037B4 0 +OP4 E037B5 0 +OP4 E037B6 0 +OP4 E037B7 0 +OP4 E037B8 0 +OP4 E037B9 0 +OP4 E037BA 0 +OP4 E037BB 0 +OP4 E037BC 0 +OP4 E037BD 0 +OP4 E037BE 0 +OP4 E037BF 0 +OP4 E037C0 0 +OP4 E037C1 0 +OP4 E037C2 0 +OP4 E037C3 0 +OP4 E037C4 0 +OP4 E037C5 0 +OP4 E037C6 0 +OP4 E037C7 0 +OP4 E037C8 0 +OP4 E037C9 0 +OP4 E037CA 0 +OP4 E037CB 0 +OP4 E037CC 0 +OP4 E037CD 0 +OP4 E037CE 0 +OP4 E037CF 0 +OP4 E037D0 0 +OP4 E037D1 0 +OP4 E037D2 0 +OP4 E037D3 0 +OP4 E037D4 0 +OP4 E037D5 0 +OP4 E037D6 0 +OP4 E037D7 0 +OP4 E037D8 0 +OP4 E037D9 0 +OP4 E037DA 0 +OP4 E037DB 0 +OP4 E037DC 0 +OP4 E037DD 0 +OP4 E037DE 0 +OP4 E037DF 0 +OP4 E037E0 0 +OP4 E037E1 0 +OP4 E037E2 0 +OP4 E037E3 0 +OP4 E037E4 0 +OP4 E037E5 0 +OP4 E037E6 0 +OP4 E037E7 0 +OP4 E037E8 0 +OP4 E037E9 0 +OP4 E037EA 0 +OP4 E037EB 0 +OP4 E037EC 0 +OP4 E037ED 0 +OP4 E037EE 0 +OP4 E037EF 0 +OP4 E037F0 0 +OP4 E037F1 0 +OP4 E037F2 0 +OP4 E037F3 0 +OP4 E037F4 0 +OP4 E037F5 0 +OP4 E037F6 0 +OP4 E037F7 0 +OP4 E037F8 0 +OP4 E037F9 0 +OP4 E037FA 0 +OP4 E037FB 0 +OP4 E037FC 0 +OP4 E037FD 0 +OP4 E037FE 0 +OP4 E037FF 0 +OP4 E03800 0 +OP4 E03801 0 +OP4 E03802 0 +OP4 E03803 0 +OP4 E03804 0 +OP4 E03805 0 +OP4 E03806 0 +OP4 E03807 0 +OP4 E03808 0 +OP4 E03809 0 +OP4 E0380A 0 +OP4 E0380B 0 +OP4 E0380C 0 +OP4 E0380D 0 +OP4 E0380E 0 +OP4 E0380F 0 +OP4 E03810 0 +OP4 E03811 0 +OP4 E03812 0 +OP4 E03813 0 +OP4 E03814 0 +OP4 E03815 0 +OP4 E03816 0 +OP4 E03817 0 +OP4 E03818 0 +OP4 E03819 0 +OP4 E0381A 0 +OP4 E0381B 0 +OP4 E0381C 0 +OP4 E0381D 0 +OP4 E0381E 0 +OP4 E0381F 0 +OP4 E03820 0 +OP4 E03821 0 +OP4 E03822 0 +OP4 E03823 0 +OP4 E03824 0 +OP4 E03825 0 +OP4 E03826 0 +OP4 E03827 0 +OP4 E03828 0 +OP4 E03829 0 +OP4 E0382A 0 +OP4 E0382B 0 +OP4 E0382C 0 +OP4 E0382D 0 +OP4 E0382E 0 +OP4 E0382F 0 +OP4 E03830 0 +OP4 E03831 0 +OP4 E03832 0 +OP4 E03833 0 +OP4 E03834 0 +OP4 E03835 0 +OP4 E03836 0 +OP4 E03837 0 +OP4 E03838 0 +OP4 E03839 0 +OP4 E0383A 0 +OP4 E0383B 0 +OP4 E0383C 0 +OP4 E0383D 0 +OP4 E0383E 0 +OP4 E0383F 0 +OP4 E03840 0 +OP4 E03841 0 +OP4 E03842 0 +OP4 E03843 0 +OP4 E03844 0 +OP4 E03845 0 +OP4 E03846 0 +OP4 E03847 0 +OP4 E03848 0 +OP4 E03849 0 +OP4 E0384A 0 +OP4 E0384B 0 +OP4 E0384C 0 +OP4 E0384D 0 +OP4 E0384E 0 +OP4 E0384F 0 +OP4 E03850 0 +OP4 E03851 0 +OP4 E03852 0 +OP4 E03853 0 +OP4 E03854 0 +OP4 E03855 0 +OP4 E03856 0 +OP4 E03857 0 +OP4 E03858 0 +OP4 E03859 0 +OP4 E0385A 0 +OP4 E0385B 0 +OP4 E0385C 0 +OP4 E0385D 0 +OP4 E0385E 0 +OP4 E0385F 0 +OP4 E03860 0 +OP4 E03861 0 +OP4 E03862 0 +OP4 E03863 0 +OP4 E03864 0 +OP4 E03865 0 +OP4 E03866 0 +OP4 E03867 0 +OP4 E03868 0 +OP4 E03869 0 +OP4 E0386A 0 +OP4 E0386B 0 +OP4 E0386C 0 +OP4 E0386D 0 +OP4 E0386E 0 +OP4 E0386F 0 +OP4 E03870 0 +OP4 E03871 0 +OP4 E03872 0 +OP4 E03873 0 +OP4 E03874 0 +OP4 E03875 0 +OP4 E03876 0 +OP4 E03877 0 +OP4 E03878 0 +OP4 E03879 0 +OP4 E0387A 0 +OP4 E0387B 0 +OP4 E0387C 0 +OP4 E0387D 0 +OP4 E0387E 0 +OP4 E0387F 0 +OP4 E03880 0 +OP4 E03881 0 +OP4 E03882 0 +OP4 E03883 0 +OP4 E03884 0 +OP4 E03885 0 +OP4 E03886 0 +OP4 E03887 0 +OP4 E03888 0 +OP4 E03889 0 +OP4 E0388A 0 +OP4 E0388B 0 +OP4 E0388C 0 +OP4 E0388D 0 +OP4 E0388E 0 +OP4 E0388F 0 +OP4 E03890 0 +OP4 E03891 0 +OP4 E03892 0 +OP4 E03893 0 +OP4 E03894 0 +OP4 E03895 0 +OP4 E03896 0 +OP4 E03897 0 +OP4 E03898 0 +OP4 E03899 0 +OP4 E0389A 0 +OP4 E0389B 0 +OP4 E0389C 0 +OP4 E0389D 0 +OP4 E0389E 0 +OP4 E0389F 0 +OP4 E038A0 0 +OP4 E038A1 0 +OP4 E038A2 0 +OP4 E038A3 0 +OP4 E038A4 0 +OP4 E038A5 0 +OP4 E038A6 0 +OP4 E038A7 0 +OP4 E038A8 0 +OP4 E038A9 0 +OP4 E038AA 0 +OP4 E038AB 0 +OP4 E038AC 0 +OP4 E038AD 0 +OP4 E038AE 0 +OP4 E038AF 0 +OP4 E038B0 0 +OP4 E038B1 0 +OP4 E038B2 0 +OP4 E038B3 0 +OP4 E038B4 0 +OP4 E038B5 0 +OP4 E038B6 0 +OP4 E038B7 0 +OP4 E038B8 0 +OP4 E038B9 0 +OP4 E038BA 0 +OP4 E038BB 0 +OP4 E038BC 0 +OP4 E038BD 0 +OP4 E038BE 0 +OP4 E038BF 0 +OP4 E038C0 0 +OP4 E038C1 0 +OP4 E038C2 0 +OP4 E038C3 0 +OP4 E038C4 0 +OP4 E038C5 0 +OP4 E038C6 0 +OP4 E038C7 0 +OP4 E038C8 0 +OP4 E038C9 0 +OP4 E038CA 0 +OP4 E038CB 0 +OP4 E038CC 0 +OP4 E038CD 0 +OP4 E038CE 0 +OP4 E038CF 0 +OP4 E038D0 0 +OP4 E038D1 0 +OP4 E038D2 0 +OP4 E038D3 0 +OP4 E038D4 0 +OP4 E038D5 0 +OP4 E038D6 0 +OP4 E038D7 0 +OP4 E038D8 0 +OP4 E038D9 0 +OP4 E038DA 0 +OP4 E038DB 0 +OP4 E038DC 0 +OP4 E038DD 0 +OP4 E038DE 0 +OP4 E038DF 0 +OP4 E038E0 0 +OP4 E038E1 0 +OP4 E038E2 0 +OP4 E038E3 0 +OP4 E038E4 0 +OP4 E038E5 0 +OP4 E038E6 0 +OP4 E038E7 0 +OP4 E038E8 0 +OP4 E038E9 0 +OP4 E038EA 0 +OP4 E038EB 0 +OP4 E038EC 0 +OP4 E038ED 0 +OP4 E038EE 0 +OP4 E038EF 0 +OP4 E038F0 0 +OP4 E038F1 0 +OP4 E038F2 0 +OP4 E038F3 0 +OP4 E038F4 0 +OP4 E038F5 0 +OP4 E038F6 0 +OP4 E038F7 0 +OP4 E038F8 0 +OP4 E038F9 0 +OP4 E038FA 0 +OP4 E038FB 0 +OP4 E038FC 0 +OP4 E038FD 0 +OP4 E038FE 0 +OP4 E038FF 0 +OP4 E03900 0 +OP4 E03901 0 +OP4 E03902 0 +OP4 E03903 0 +OP4 E03904 0 +OP4 E03905 0 +OP4 E03906 0 +OP4 E03907 0 +OP4 E03908 0 +OP4 E03909 0 +OP4 E0390A 0 +OP4 E0390B 0 +OP4 E0390C 0 +OP4 E0390D 0 +OP4 E0390E 0 +OP4 E0390F 0 +OP4 E03910 0 +OP4 E03911 0 +OP4 E03912 0 +OP4 E03913 0 +OP4 E03914 0 +OP4 E03915 0 +OP4 E03916 0 +OP4 E03917 0 +OP4 E03918 0 +OP4 E03919 0 +OP4 E0391A 0 +OP4 E0391B 0 +OP4 E0391C 0 +OP4 E0391D 0 +OP4 E0391E 0 +OP4 E0391F 0 +OP4 E03920 0 +OP4 E03921 0 +OP4 E03922 0 +OP4 E03923 0 +OP4 E03924 0 +OP4 E03925 0 +OP4 E03926 0 +OP4 E03927 0 +OP4 E03928 0 +OP4 E03929 0 +OP4 E0392A 0 +OP4 E0392B 0 +OP4 E0392C 0 +OP4 E0392D 0 +OP4 E0392E 0 +OP4 E0392F 0 +OP4 E03930 0 +OP4 E03931 0 +OP4 E03932 0 +OP4 E03933 0 +OP4 E03934 0 +OP4 E03935 0 +OP4 E03936 0 +OP4 E03937 0 +OP4 E03938 0 +OP4 E03939 0 +OP4 E0393A 0 +OP4 E0393B 0 +OP4 E0393C 0 +OP4 E0393D 0 +OP4 E0393E 0 +OP4 E0393F 0 +OP4 E03940 0 +OP4 E03941 0 +OP4 E03942 0 +OP4 E03943 0 +OP4 E03944 0 +OP4 E03945 0 +OP4 E03946 0 +OP4 E03947 0 +OP4 E03948 0 +OP4 E03949 0 +OP4 E0394A 0 +OP4 E0394B 0 +OP4 E0394C 0 +OP4 E0394D 0 +OP4 E0394E 0 +OP4 E0394F 0 +OP4 E03950 0 +OP4 E03951 0 +OP4 E03952 0 +OP4 E03953 0 +OP4 E03954 0 +OP4 E03955 0 +OP4 E03956 0 +OP4 E03957 0 +OP4 E03958 0 +OP4 E03959 0 +OP4 E0395A 0 +OP4 E0395B 0 +OP4 E0395C 0 +OP4 E0395D 0 +OP4 E0395E 0 +OP4 E0395F 0 +OP4 E03960 0 +OP4 E03961 0 +OP4 E03962 0 +OP4 E03963 0 +OP4 E03964 0 +OP4 E03965 0 +OP4 E03966 0 +OP4 E03967 0 +OP4 E03968 0 +OP4 E03969 0 +OP4 E0396A 0 +OP4 E0396B 0 +OP4 E0396C 0 +OP4 E0396D 0 +OP4 E0396E 0 +OP4 E0396F 0 +OP4 E03970 0 +OP4 E03971 0 +OP4 E03972 0 +OP4 E03973 0 +OP4 E03974 0 +OP4 E03975 0 +OP4 E03976 0 +OP4 E03977 0 +OP4 E03978 0 +OP4 E03979 0 +OP4 E0397A 0 +OP4 E0397B 0 +OP4 E0397C 0 +OP4 E0397D 0 +OP4 E0397E 0 +OP4 E0397F 0 +OP4 E03980 0 +OP4 E03981 0 +OP4 E03982 0 +OP4 E03983 0 +OP4 E03984 0 +OP4 E03985 0 +OP4 E03986 0 +OP4 E03987 0 +OP4 E03988 0 +OP4 E03989 0 +OP4 E0398A 0 +OP4 E0398B 0 +OP4 E0398C 0 +OP4 E0398D 0 +OP4 E0398E 0 +OP4 E0398F 0 +OP4 E03990 0 +OP4 E03991 0 +OP4 E03992 0 +OP4 E03993 0 +OP4 E03994 0 +OP4 E03995 0 +OP4 E03996 0 +OP4 E03997 0 +OP4 E03998 0 +OP4 E03999 0 +OP4 E0399A 0 +OP4 E0399B 0 +OP4 E0399C 0 +OP4 E0399D 0 +OP4 E0399E 0 +OP4 E0399F 0 +OP4 E039A0 0 +OP4 E039A1 0 +OP4 E039A2 0 +OP4 E039A3 0 +OP4 E039A4 0 +OP4 E039A5 0 +OP4 E039A6 0 +OP4 E039A7 0 +OP4 E039A8 0 +OP4 E039A9 0 +OP4 E039AA 0 +OP4 E039AB 0 +OP4 E039AC 0 +OP4 E039AD 0 +OP4 E039AE 0 +OP4 E039AF 0 +OP4 E039B0 0 +OP4 E039B1 0 +OP4 E039B2 0 +OP4 E039B3 0 +OP4 E039B4 0 +OP4 E039B5 0 +OP4 E039B6 0 +OP4 E039B7 0 +OP4 E039B8 0 +OP4 E039B9 0 +OP4 E039BA 0 +OP4 E039BB 0 +OP4 E039BC 0 +OP4 E039BD 0 +OP4 E039BE 0 +OP4 E039BF 0 +OP4 E039C0 0 +OP4 E039C1 0 +OP4 E039C2 0 +OP4 E039C3 0 +OP4 E039C4 0 +OP4 E039C5 0 +OP4 E039C6 0 +OP4 E039C7 0 +OP4 E039C8 0 +OP4 E039C9 0 +OP4 E039CA 0 +OP4 E039CB 0 +OP4 E039CC 0 +OP4 E039CD 0 +OP4 E039CE 0 +OP4 E039CF 0 +OP4 E039D0 0 +OP4 E039D1 0 +OP4 E039D2 0 +OP4 E039D3 0 +OP4 E039D4 0 +OP4 E039D5 0 +OP4 E039D6 0 +OP4 E039D7 0 +OP4 E039D8 0 +OP4 E039D9 0 +OP4 E039DA 0 +OP4 E039DB 0 +OP4 E039DC 0 +OP4 E039DD 0 +OP4 E039DE 0 +OP4 E039DF 0 +OP4 E039E0 0 +OP4 E039E1 0 +OP4 E039E2 0 +OP4 E039E3 0 +OP4 E039E4 0 +OP4 E039E5 0 +OP4 E039E6 0 +OP4 E039E7 0 +OP4 E039E8 0 +OP4 E039E9 0 +OP4 E039EA 0 +OP4 E039EB 0 +OP4 E039EC 0 +OP4 E039ED 0 +OP4 E039EE 0 +OP4 E039EF 0 +OP4 E039F0 0 +OP4 E039F1 0 +OP4 E039F2 0 +OP4 E039F3 0 +OP4 E039F4 0 +OP4 E039F5 0 +OP4 E039F6 0 +OP4 E039F7 0 +OP4 E039F8 0 +OP4 E039F9 0 +OP4 E039FA 0 +OP4 E039FB 0 +OP4 E039FC 0 +OP4 E039FD 0 +OP4 E039FE 0 +OP4 E039FF 0 +OP4 E03A00 0 +OP4 E03A01 0 +OP4 E03A02 0 +OP4 E03A03 0 +OP4 E03A04 0 +OP4 E03A05 0 +OP4 E03A06 0 +OP4 E03A07 0 +OP4 E03A08 0 +OP4 E03A09 0 +OP4 E03A0A 0 +OP4 E03A0B 0 +OP4 E03A0C 0 +OP4 E03A0D 0 +OP4 E03A0E 0 +OP4 E03A0F 0 +OP4 E03A10 0 +OP4 E03A11 0 +OP4 E03A12 0 +OP4 E03A13 0 +OP4 E03A14 0 +OP4 E03A15 0 +OP4 E03A16 0 +OP4 E03A17 0 +OP4 E03A18 0 +OP4 E03A19 0 +OP4 E03A1A 0 +OP4 E03A1B 0 +OP4 E03A1C 0 +OP4 E03A1D 0 +OP4 E03A1E 0 +OP4 E03A1F 0 +OP4 E03A20 0 +OP4 E03A21 0 +OP4 E03A22 0 +OP4 E03A23 0 +OP4 E03A24 0 +OP4 E03A25 0 +OP4 E03A26 0 +OP4 E03A27 0 +OP4 E03A28 0 +OP4 E03A29 0 +OP4 E03A2A 0 +OP4 E03A2B 0 +OP4 E03A2C 0 +OP4 E03A2D 0 +OP4 E03A2E 0 +OP4 E03A2F 0 +OP4 E03A30 0 +OP4 E03A31 0 +OP4 E03A32 0 +OP4 E03A33 0 +OP4 E03A34 0 +OP4 E03A35 0 +OP4 E03A36 0 +OP4 E03A37 0 +OP4 E03A38 0 +OP4 E03A39 0 +OP4 E03A3A 0 +OP4 E03A3B 0 +OP4 E03A3C 0 +OP4 E03A3D 0 +OP4 E03A3E 0 +OP4 E03A3F 0 +OP4 E03A40 0 +OP4 E03A41 0 +OP4 E03A42 0 +OP4 E03A43 0 +OP4 E03A44 0 +OP4 E03A45 0 +OP4 E03A46 0 +OP4 E03A47 0 +OP4 E03A48 0 +OP4 E03A49 0 +OP4 E03A4A 0 +OP4 E03A4B 0 +OP4 E03A4C 0 +OP4 E03A4D 0 +OP4 E03A4E 0 +OP4 E03A4F 0 +OP4 E03A50 0 +OP4 E03A51 0 +OP4 E03A52 0 +OP4 E03A53 0 +OP4 E03A54 0 +OP4 E03A55 0 +OP4 E03A56 0 +OP4 E03A57 0 +OP4 E03A58 0 +OP4 E03A59 0 +OP4 E03A5A 0 +OP4 E03A5B 0 +OP4 E03A5C 0 +OP4 E03A5D 0 +OP4 E03A5E 0 +OP4 E03A5F 0 +OP4 E03A60 0 +OP4 E03A61 0 +OP4 E03A62 0 +OP4 E03A63 0 +OP4 E03A64 0 +OP4 E03A65 0 +OP4 E03A66 0 +OP4 E03A67 0 +OP4 E03A68 0 +OP4 E03A69 0 +OP4 E03A6A 0 +OP4 E03A6B 0 +OP4 E03A6C 0 +OP4 E03A6D 0 +OP4 E03A6E 0 +OP4 E03A6F 0 +OP4 E03A70 0 +OP4 E03A71 0 +OP4 E03A72 0 +OP4 E03A73 0 +OP4 E03A74 0 +OP4 E03A75 0 +OP4 E03A76 0 +OP4 E03A77 0 +OP4 E03A78 0 +OP4 E03A79 0 +OP4 E03A7A 0 +OP4 E03A7B 0 +OP4 E03A7C 0 +OP4 E03A7D 0 +OP4 E03A7E 0 +OP4 E03A7F 0 +OP4 E03A80 0 +OP4 E03A81 0 +OP4 E03A82 0 +OP4 E03A83 0 +OP4 E03A84 0 +OP4 E03A85 0 +OP4 E03A86 0 +OP4 E03A87 0 +OP4 E03A88 0 +OP4 E03A89 0 +OP4 E03A8A 0 +OP4 E03A8B 0 +OP4 E03A8C 0 +OP4 E03A8D 0 +OP4 E03A8E 0 +OP4 E03A8F 0 +OP4 E03A90 0 +OP4 E03A91 0 +OP4 E03A92 0 +OP4 E03A93 0 +OP4 E03A94 0 +OP4 E03A95 0 +OP4 E03A96 0 +OP4 E03A97 0 +OP4 E03A98 0 +OP4 E03A99 0 +OP4 E03A9A 0 +OP4 E03A9B 0 +OP4 E03A9C 0 +OP4 E03A9D 0 +OP4 E03A9E 0 +OP4 E03A9F 0 +OP4 E03AA0 0 +OP4 E03AA1 0 +OP4 E03AA2 0 +OP4 E03AA3 0 +OP4 E03AA4 0 +OP4 E03AA5 0 +OP4 E03AA6 0 +OP4 E03AA7 0 +OP4 E03AA8 0 +OP4 E03AA9 0 +OP4 E03AAA 0 +OP4 E03AAB 0 +OP4 E03AAC 0 +OP4 E03AAD 0 +OP4 E03AAE 0 +OP4 E03AAF 0 +OP4 E03AB0 0 +OP4 E03AB1 0 +OP4 E03AB2 0 +OP4 E03AB3 0 +OP4 E03AB4 0 +OP4 E03AB5 0 +OP4 E03AB6 0 +OP4 E03AB7 0 +OP4 E03AB8 0 +OP4 E03AB9 0 +OP4 E03ABA 0 +OP4 E03ABB 0 +OP4 E03ABC 0 +OP4 E03ABD 0 +OP4 E03ABE 0 +OP4 E03ABF 0 +OP4 E03AC0 0 +OP4 E03AC1 0 +OP4 E03AC2 0 +OP4 E03AC3 0 +OP4 E03AC4 0 +OP4 E03AC5 0 +OP4 E03AC6 0 +OP4 E03AC7 0 +OP4 E03AC8 0 +OP4 E03AC9 0 +OP4 E03ACA 0 +OP4 E03ACB 0 +OP4 E03ACC 0 +OP4 E03ACD 0 +OP4 E03ACE 0 +OP4 E03ACF 0 +OP4 E03AD0 0 +OP4 E03AD1 0 +OP4 E03AD2 0 +OP4 E03AD3 0 +OP4 E03AD4 0 +OP4 E03AD5 0 +OP4 E03AD6 0 +OP4 E03AD7 0 +OP4 E03AD8 0 +OP4 E03AD9 0 +OP4 E03ADA 0 +OP4 E03ADB 0 +OP4 E03ADC 0 +OP4 E03ADD 0 +OP4 E03ADE 0 +OP4 E03ADF 0 +OP4 E03AE0 0 +OP4 E03AE1 0 +OP4 E03AE2 0 +OP4 E03AE3 0 +OP4 E03AE4 0 +OP4 E03AE5 0 +OP4 E03AE6 0 +OP4 E03AE7 0 +OP4 E03AE8 0 +OP4 E03AE9 0 +OP4 E03AEA 0 +OP4 E03AEB 0 +OP4 E03AEC 0 +OP4 E03AED 0 +OP4 E03AEE 0 +OP4 E03AEF 0 +OP4 E03AF0 0 +OP4 E03AF1 0 +OP4 E03AF2 0 +OP4 E03AF3 0 +OP4 E03AF4 0 +OP4 E03AF5 0 +OP4 E03AF6 0 +OP4 E03AF7 0 +OP4 E03AF8 0 +OP4 E03AF9 0 +OP4 E03AFA 0 +OP4 E03AFB 0 +OP4 E03AFC 0 +OP4 E03AFD 0 +OP4 E03AFE 0 +OP4 E03AFF 0 +OP4 E03B00 0 +OP4 E03B01 0 +OP4 E03B02 0 +OP4 E03B03 0 +OP4 E03B04 0 +OP4 E03B05 0 +OP4 E03B06 0 +OP4 E03B07 0 +OP4 E03B08 0 +OP4 E03B09 0 +OP4 E03B0A 0 +OP4 E03B0B 0 +OP4 E03B0C 0 +OP4 E03B0D 0 +OP4 E03B0E 0 +OP4 E03B0F 0 +OP4 E03B10 0 +OP4 E03B11 0 +OP4 E03B12 0 +OP4 E03B13 0 +OP4 E03B14 0 +OP4 E03B15 0 +OP4 E03B16 0 +OP4 E03B17 0 +OP4 E03B18 0 +OP4 E03B19 0 +OP4 E03B1A 0 +OP4 E03B1B 0 +OP4 E03B1C 0 +OP4 E03B1D 0 +OP4 E03B1E 0 +OP4 E03B1F 0 +OP4 E03B20 0 +OP4 E03B21 0 +OP4 E03B22 0 +OP4 E03B23 0 +OP4 E03B24 0 +OP4 E03B25 0 +OP4 E03B26 0 +OP4 E03B27 0 +OP4 E03B28 0 +OP4 E03B29 0 +OP4 E03B2A 0 +OP4 E03B2B 0 +OP4 E03B2C 0 +OP4 E03B2D 0 +OP4 E03B2E 0 +OP4 E03B2F 0 +OP4 E03B30 0 +OP4 E03B31 0 +OP4 E03B32 0 +OP4 E03B33 0 +OP4 E03B34 0 +OP4 E03B35 0 +OP4 E03B36 0 +OP4 E03B37 0 +OP4 E03B38 0 +OP4 E03B39 0 +OP4 E03B3A 0 +OP4 E03B3B 0 +OP4 E03B3C 0 +OP4 E03B3D 0 +OP4 E03B3E 0 +OP4 E03B3F 0 +OP4 E03B40 0 +OP4 E03B41 0 +OP4 E03B42 0 +OP4 E03B43 0 +OP4 E03B44 0 +OP4 E03B45 0 +OP4 E03B46 0 +OP4 E03B47 0 +OP4 E03B48 0 +OP4 E03B49 0 +OP4 E03B4A 0 +OP4 E03B4B 0 +OP4 E03B4C 0 +OP4 E03B4D 0 +OP4 E03B4E 0 +OP4 E03B4F 0 +OP4 E03B50 0 +OP4 E03B51 0 +OP4 E03B52 0 +OP4 E03B53 0 +OP4 E03B54 0 +OP4 E03B55 0 +OP4 E03B56 0 +OP4 E03B57 0 +OP4 E03B58 0 +OP4 E03B59 0 +OP4 E03B5A 0 +OP4 E03B5B 0 +OP4 E03B5C 0 +OP4 E03B5D 0 +OP4 E03B5E 0 +OP4 E03B5F 0 +OP4 E03B60 0 +OP4 E03B61 0 +OP4 E03B62 0 +OP4 E03B63 0 +OP4 E03B64 0 +OP4 E03B65 0 +OP4 E03B66 0 +OP4 E03B67 0 +OP4 E03B68 0 +OP4 E03B69 0 +OP4 E03B6A 0 +OP4 E03B6B 0 +OP4 E03B6C 0 +OP4 E03B6D 0 +OP4 E03B6E 0 +OP4 E03B6F 0 +OP4 E03B70 0 +OP4 E03B71 0 +OP4 E03B72 0 +OP4 E03B73 0 +OP4 E03B74 0 +OP4 E03B75 0 +OP4 E03B76 0 +OP4 E03B77 0 +OP4 E03B78 0 +OP4 E03B79 0 +OP4 E03B7A 0 +OP4 E03B7B 0 +OP4 E03B7C 0 +OP4 E03B7D 0 +OP4 E03B7E 0 +OP4 E03B7F 0 +OP4 E03B80 0 +OP4 E03B81 0 +OP4 E03B82 0 +OP4 E03B83 0 +OP4 E03B84 0 +OP4 E03B85 0 +OP4 E03B86 0 +OP4 E03B87 0 +OP4 E03B88 0 +OP4 E03B89 0 +OP4 E03B8A 0 +OP4 E03B8B 0 +OP4 E03B8C 0 +OP4 E03B8D 0 +OP4 E03B8E 0 +OP4 E03B8F 0 +OP4 E03B90 0 +OP4 E03B91 0 +OP4 E03B92 0 +OP4 E03B93 0 +OP4 E03B94 0 +OP4 E03B95 0 +OP4 E03B96 0 +OP4 E03B97 0 +OP4 E03B98 0 +OP4 E03B99 0 +OP4 E03B9A 0 +OP4 E03B9B 0 +OP4 E03B9C 0 +OP4 E03B9D 0 +OP4 E03B9E 0 +OP4 E03B9F 0 +OP4 E03BA0 0 +OP4 E03BA1 0 +OP4 E03BA2 0 +OP4 E03BA3 0 +OP4 E03BA4 0 +OP4 E03BA5 0 +OP4 E03BA6 0 +OP4 E03BA7 0 +OP4 E03BA8 0 +OP4 E03BA9 0 +OP4 E03BAA 0 +OP4 E03BAB 0 +OP4 E03BAC 0 +OP4 E03BAD 0 +OP4 E03BAE 0 +OP4 E03BAF 0 +OP4 E03BB0 0 +OP4 E03BB1 0 +OP4 E03BB2 0 +OP4 E03BB3 0 +OP4 E03BB4 0 +OP4 E03BB5 0 +OP4 E03BB6 0 +OP4 E03BB7 0 +OP4 E03BB8 0 +OP4 E03BB9 0 +OP4 E03BBA 0 +OP4 E03BBB 0 +OP4 E03BBC 0 +OP4 E03BBD 0 +OP4 E03BBE 0 +OP4 E03BBF 0 +OP4 E03BC0 0 +OP4 E03BC1 0 +OP4 E03BC2 0 +OP4 E03BC3 0 +OP4 E03BC4 0 +OP4 E03BC5 0 +OP4 E03BC6 0 +OP4 E03BC7 0 +OP4 E03BC8 0 +OP4 E03BC9 0 +OP4 E03BCA 0 +OP4 E03BCB 0 +OP4 E03BCC 0 +OP4 E03BCD 0 +OP4 E03BCE 0 +OP4 E03BCF 0 +OP4 E03BD0 0 +OP4 E03BD1 0 +OP4 E03BD2 0 +OP4 E03BD3 0 +OP4 E03BD4 0 +OP4 E03BD5 0 +OP4 E03BD6 0 +OP4 E03BD7 0 +OP4 E03BD8 0 +OP4 E03BD9 0 +OP4 E03BDA 0 +OP4 E03BDB 0 +OP4 E03BDC 0 +OP4 E03BDD 0 +OP4 E03BDE 0 +OP4 E03BDF 0 +OP4 E03BE0 0 +OP4 E03BE1 0 +OP4 E03BE2 0 +OP4 E03BE3 0 +OP4 E03BE4 0 +OP4 E03BE5 0 +OP4 E03BE6 0 +OP4 E03BE7 0 +OP4 E03BE8 0 +OP4 E03BE9 0 +OP4 E03BEA 0 +OP4 E03BEB 0 +OP4 E03BEC 0 +OP4 E03BED 0 +OP4 E03BEE 0 +OP4 E03BEF 0 +OP4 E03BF0 0 +OP4 E03BF1 0 +OP4 E03BF2 0 +OP4 E03BF3 0 +OP4 E03BF4 0 +OP4 E03BF5 0 +OP4 E03BF6 0 +OP4 E03BF7 0 +OP4 E03BF8 0 +OP4 E03BF9 0 +OP4 E03BFA 0 +OP4 E03BFB 0 +OP4 E03BFC 0 +OP4 E03BFD 0 +OP4 E03BFE 0 +OP4 E03BFF 0 +OP4 E03C00 0 +OP4 E03C01 0 +OP4 E03C02 0 +OP4 E03C03 0 +OP4 E03C04 0 +OP4 E03C05 0 +OP4 E03C06 0 +OP4 E03C07 0 +OP4 E03C08 0 +OP4 E03C09 0 +OP4 E03C0A 0 +OP4 E03C0B 0 +OP4 E03C0C 0 +OP4 E03C0D 0 +OP4 E03C0E 0 +OP4 E03C0F 0 +OP4 E03C10 0 +OP4 E03C11 0 +OP4 E03C12 0 +OP4 E03C13 0 +OP4 E03C14 0 +OP4 E03C15 0 +OP4 E03C16 0 +OP4 E03C17 0 +OP4 E03C18 0 +OP4 E03C19 0 +OP4 E03C1A 0 +OP4 E03C1B 0 +OP4 E03C1C 0 +OP4 E03C1D 0 +OP4 E03C1E 0 +OP4 E03C1F 0 +OP4 E03C20 0 +OP4 E03C21 0 +OP4 E03C22 0 +OP4 E03C23 0 +OP4 E03C24 0 +OP4 E03C25 0 +OP4 E03C26 0 +OP4 E03C27 0 +OP4 E03C28 0 +OP4 E03C29 0 +OP4 E03C2A 0 +OP4 E03C2B 0 +OP4 E03C2C 0 +OP4 E03C2D 0 +OP4 E03C2E 0 +OP4 E03C2F 0 +OP4 E03C30 0 +OP4 E03C31 0 +OP4 E03C32 0 +OP4 E03C33 0 +OP4 E03C34 0 +OP4 E03C35 0 +OP4 E03C36 0 +OP4 E03C37 0 +OP4 E03C38 0 +OP4 E03C39 0 +OP4 E03C3A 0 +OP4 E03C3B 0 +OP4 E03C3C 0 +OP4 E03C3D 0 +OP4 E03C3E 0 +OP4 E03C3F 0 +OP4 E03C40 0 +OP4 E03C41 0 +OP4 E03C42 0 +OP4 E03C43 0 +OP4 E03C44 0 +OP4 E03C45 0 +OP4 E03C46 0 +OP4 E03C47 0 +OP4 E03C48 0 +OP4 E03C49 0 +OP4 E03C4A 0 +OP4 E03C4B 0 +OP4 E03C4C 0 +OP4 E03C4D 0 +OP4 E03C4E 0 +OP4 E03C4F 0 +OP4 E03C50 0 +OP4 E03C51 0 +OP4 E03C52 0 +OP4 E03C53 0 +OP4 E03C54 0 +OP4 E03C55 0 +OP4 E03C56 0 +OP4 E03C57 0 +OP4 E03C58 0 +OP4 E03C59 0 +OP4 E03C5A 0 +OP4 E03C5B 0 +OP4 E03C5C 0 +OP4 E03C5D 0 +OP4 E03C5E 0 +OP4 E03C5F 0 +OP4 E03C60 0 +OP4 E03C61 0 +OP4 E03C62 0 +OP4 E03C63 0 +OP4 E03C64 0 +OP4 E03C65 0 +OP4 E03C66 0 +OP4 E03C67 0 +OP4 E03C68 0 +OP4 E03C69 0 +OP4 E03C6A 0 +OP4 E03C6B 0 +OP4 E03C6C 0 +OP4 E03C6D 0 +OP4 E03C6E 0 +OP4 E03C6F 0 +OP4 E03C70 0 +OP4 E03C71 0 +OP4 E03C72 0 +OP4 E03C73 0 +OP4 E03C74 0 +OP4 E03C75 0 +OP4 E03C76 0 +OP4 E03C77 0 +OP4 E03C78 0 +OP4 E03C79 0 +OP4 E03C7A 0 +OP4 E03C7B 0 +OP4 E03C7C 0 +OP4 E03C7D 0 +OP4 E03C7E 0 +OP4 E03C7F 0 +OP4 E03C80 0 +OP4 E03C81 0 +OP4 E03C82 0 +OP4 E03C83 0 +OP4 E03C84 0 +OP4 E03C85 0 +OP4 E03C86 0 +OP4 E03C87 0 +OP4 E03C88 0 +OP4 E03C89 0 +OP4 E03C8A 0 +OP4 E03C8B 0 +OP4 E03C8C 0 +OP4 E03C8D 0 +OP4 E03C8E 0 +OP4 E03C8F 0 +OP4 E03C90 0 +OP4 E03C91 0 +OP4 E03C92 0 +OP4 E03C93 0 +OP4 E03C94 0 +OP4 E03C95 0 +OP4 E03C96 0 +OP4 E03C97 0 +OP4 E03C98 0 +OP4 E03C99 0 +OP4 E03C9A 0 +OP4 E03C9B 0 +OP4 E03C9C 0 +OP4 E03C9D 0 +OP4 E03C9E 0 +OP4 E03C9F 0 +OP4 E03CA0 0 +OP4 E03CA1 0 +OP4 E03CA2 0 +OP4 E03CA3 0 +OP4 E03CA4 0 +OP4 E03CA5 0 +OP4 E03CA6 0 +OP4 E03CA7 0 +OP4 E03CA8 0 +OP4 E03CA9 0 +OP4 E03CAA 0 +OP4 E03CAB 0 +OP4 E03CAC 0 +OP4 E03CAD 0 +OP4 E03CAE 0 +OP4 E03CAF 0 +OP4 E03CB0 0 +OP4 E03CB1 0 +OP4 E03CB2 0 +OP4 E03CB3 0 +OP4 E03CB4 0 +OP4 E03CB5 0 +OP4 E03CB6 0 +OP4 E03CB7 0 +OP4 E03CB8 0 +OP4 E03CB9 0 +OP4 E03CBA 0 +OP4 E03CBB 0 +OP4 E03CBC 0 +OP4 E03CBD 0 +OP4 E03CBE 0 +OP4 E03CBF 0 +OP4 E03CC0 0 +OP4 E03CC1 0 +OP4 E03CC2 0 +OP4 E03CC3 0 +OP4 E03CC4 0 +OP4 E03CC5 0 +OP4 E03CC6 0 +OP4 E03CC7 0 +OP4 E03CC8 0 +OP4 E03CC9 0 +OP4 E03CCA 0 +OP4 E03CCB 0 +OP4 E03CCC 0 +OP4 E03CCD 0 +OP4 E03CCE 0 +OP4 E03CCF 0 +OP4 E03CD0 0 +OP4 E03CD1 0 +OP4 E03CD2 0 +OP4 E03CD3 0 +OP4 E03CD4 0 +OP4 E03CD5 0 +OP4 E03CD6 0 +OP4 E03CD7 0 +OP4 E03CD8 0 +OP4 E03CD9 0 +OP4 E03CDA 0 +OP4 E03CDB 0 +OP4 E03CDC 0 +OP4 E03CDD 0 +OP4 E03CDE 0 +OP4 E03CDF 0 +OP4 E03CE0 0 +OP4 E03CE1 0 +OP4 E03CE2 0 +OP4 E03CE3 0 +OP4 E03CE4 0 +OP4 E03CE5 0 +OP4 E03CE6 0 +OP4 E03CE7 0 +OP4 E03CE8 0 +OP4 E03CE9 0 +OP4 E03CEA 0 +OP4 E03CEB 0 +OP4 E03CEC 0 +OP4 E03CED 0 +OP4 E03CEE 0 +OP4 E03CEF 0 +OP4 E03CF0 0 +OP4 E03CF1 0 +OP4 E03CF2 0 +OP4 E03CF3 0 +OP4 E03CF4 0 +OP4 E03CF5 0 +OP4 E03CF6 0 +OP4 E03CF7 0 +OP4 E03CF8 0 +OP4 E03CF9 0 +OP4 E03CFA 0 +OP4 E03CFB 0 +OP4 E03CFC 0 +OP4 E03CFD 0 +OP4 E03CFE 0 +OP4 E03CFF 0 +OP4 E03D00 0 +OP4 E03D01 0 +OP4 E03D02 0 +OP4 E03D03 0 +OP4 E03D04 0 +OP4 E03D05 0 +OP4 E03D06 0 +OP4 E03D07 0 +OP4 E03D08 0 +OP4 E03D09 0 +OP4 E03D0A 0 +OP4 E03D0B 0 +OP4 E03D0C 0 +OP4 E03D0D 0 +OP4 E03D0E 0 +OP4 E03D0F 0 +OP4 E03D10 0 +OP4 E03D11 0 +OP4 E03D12 0 +OP4 E03D13 0 +OP4 E03D14 0 +OP4 E03D15 0 +OP4 E03D16 0 +OP4 E03D17 0 +OP4 E03D18 0 +OP4 E03D19 0 +OP4 E03D1A 0 +OP4 E03D1B 0 +OP4 E03D1C 0 +OP4 E03D1D 0 +OP4 E03D1E 0 +OP4 E03D1F 0 +OP4 E03D20 0 +OP4 E03D21 0 +OP4 E03D22 0 +OP4 E03D23 0 +OP4 E03D24 0 +OP4 E03D25 0 +OP4 E03D26 0 +OP4 E03D27 0 +OP4 E03D28 0 +OP4 E03D29 0 +OP4 E03D2A 0 +OP4 E03D2B 0 +OP4 E03D2C 0 +OP4 E03D2D 0 +OP4 E03D2E 0 +OP4 E03D2F 0 +OP4 E03D30 0 +OP4 E03D31 0 +OP4 E03D32 0 +OP4 E03D33 0 +OP4 E03D34 0 +OP4 E03D35 0 +OP4 E03D36 0 +OP4 E03D37 0 +OP4 E03D38 0 +OP4 E03D39 0 +OP4 E03D3A 0 +OP4 E03D3B 0 +OP4 E03D3C 0 +OP4 E03D3D 0 +OP4 E03D3E 0 +OP4 E03D3F 0 +OP4 E03D40 0 +OP4 E03D41 0 +OP4 E03D42 0 +OP4 E03D43 0 +OP4 E03D44 0 +OP4 E03D45 0 +OP4 E03D46 0 +OP4 E03D47 0 +OP4 E03D48 0 +OP4 E03D49 0 +OP4 E03D4A 0 +OP4 E03D4B 0 +OP4 E03D4C 0 +OP4 E03D4D 0 +OP4 E03D4E 0 +OP4 E03D4F 0 +OP4 E03D50 0 +OP4 E03D51 0 +OP4 E03D52 0 +OP4 E03D53 0 +OP4 E03D54 0 +OP4 E03D55 0 +OP4 E03D56 0 +OP4 E03D57 0 +OP4 E03D58 0 +OP4 E03D59 0 +OP4 E03D5A 0 +OP4 E03D5B 0 +OP4 E03D5C 0 +OP4 E03D5D 0 +OP4 E03D5E 0 +OP4 E03D5F 0 +OP4 E03D60 0 +OP4 E03D61 0 +OP4 E03D62 0 +OP4 E03D63 0 +OP4 E03D64 0 +OP4 E03D65 0 +OP4 E03D66 0 +OP4 E03D67 0 +OP4 E03D68 0 +OP4 E03D69 0 +OP4 E03D6A 0 +OP4 E03D6B 0 +OP4 E03D6C 0 +OP4 E03D6D 0 +OP4 E03D6E 0 +OP4 E03D6F 0 +OP4 E03D70 0 +OP4 E03D71 0 +OP4 E03D72 0 +OP4 E03D73 0 +OP4 E03D74 0 +OP4 E03D75 0 +OP4 E03D76 0 +OP4 E03D77 0 +OP4 E03D78 0 +OP4 E03D79 0 +OP4 E03D7A 0 +OP4 E03D7B 0 +OP4 E03D7C 0 +OP4 E03D7D 0 +OP4 E03D7E 0 +OP4 E03D7F 0 +OP4 E03D80 0 +OP4 E03D81 0 +OP4 E03D82 0 +OP4 E03D83 0 +OP4 E03D84 0 +OP4 E03D85 0 +OP4 E03D86 0 +OP4 E03D87 0 +OP4 E03D88 0 +OP4 E03D89 0 +OP4 E03D8A 0 +OP4 E03D8B 0 +OP4 E03D8C 0 +OP4 E03D8D 0 +OP4 E03D8E 0 +OP4 E03D8F 0 +OP4 E03D90 0 +OP4 E03D91 0 +OP4 E03D92 0 +OP4 E03D93 0 +OP4 E03D94 0 +OP4 E03D95 0 +OP4 E03D96 0 +OP4 E03D97 0 +OP4 E03D98 0 +OP4 E03D99 0 +OP4 E03D9A 0 +OP4 E03D9B 0 +OP4 E03D9C 0 +OP4 E03D9D 0 +OP4 E03D9E 0 +OP4 E03D9F 0 +OP4 E03DA0 0 +OP4 E03DA1 0 +OP4 E03DA2 0 +OP4 E03DA3 0 +OP4 E03DA4 0 +OP4 E03DA5 0 +OP4 E03DA6 0 +OP4 E03DA7 0 +OP4 E03DA8 0 +OP4 E03DA9 0 +OP4 E03DAA 0 +OP4 E03DAB 0 +OP4 E03DAC 0 +OP4 E03DAD 0 +OP4 E03DAE 0 +OP4 E03DAF 0 +OP4 E03DB0 0 +OP4 E03DB1 0 +OP4 E03DB2 0 +OP4 E03DB3 0 +OP4 E03DB4 0 +OP4 E03DB5 0 +OP4 E03DB6 0 +OP4 E03DB7 0 +OP4 E03DB8 0 +OP4 E03DB9 0 +OP4 E03DBA 0 +OP4 E03DBB 0 +OP4 E03DBC 0 +OP4 E03DBD 0 +OP4 E03DBE 0 +OP4 E03DBF 0 +OP4 E03DC0 0 +OP4 E03DC1 0 +OP4 E03DC2 0 +OP4 E03DC3 0 +OP4 E03DC4 0 diff --git a/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum4_itrace_irisc4.cfg.ext b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum4_itrace_irisc4.cfg.ext new file mode 100644 index 000000000000..d5d67c815a76 --- /dev/null +++ b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum4_itrace_irisc4.cfg.ext @@ -0,0 +1,15814 @@ +OP1 Spectrum4 +OP4 ITRACE0 0 +OP4 ITRACE1 0 +OP4 ITRACE2 0 +OP4 ITRACE3 0 +OP4 ITRACE4 1 +OP4 ITRACE5 0 +OP4 ITRACE6 0 +OP4 ITRACE7 0 +OP4 ITRACE8 0 +OP4 ITRACE9 0 +OP4 Main_PhyUC 0 +OP4 TILE0_ITRACE0 0 +OP4 TILE0_ITRACE1 0 +OP4 TILE0_ITRACE2 0 +OP4 TILE0_ITRACE3 0 +OP4 TILE0_ITRACE4 0 +OP4 TILE0_PhyUC 0 +OP4 TILE1_ITRACE0 0 +OP4 TILE1_ITRACE1 0 +OP4 TILE1_ITRACE2 0 +OP4 TILE1_ITRACE3 0 +OP4 TILE1_ITRACE4 0 +OP4 TILE1_PhyUC 0 +OP4 TILE2_ITRACE0 0 +OP4 TILE2_ITRACE1 0 +OP4 TILE2_ITRACE2 0 +OP4 TILE2_ITRACE3 0 +OP4 TILE2_ITRACE4 0 +OP4 TILE2_PhyUC 0 +OP4 TILE3_ITRACE0 0 +OP4 TILE3_ITRACE1 0 +OP4 TILE3_ITRACE2 0 +OP4 TILE3_ITRACE3 0 +OP4 TILE3_ITRACE4 0 +OP4 TILE3_PhyUC 0 +OP4 TILE4_ITRACE0 0 +OP4 TILE4_ITRACE1 0 +OP4 TILE4_ITRACE2 0 +OP4 TILE4_ITRACE3 0 +OP4 TILE4_ITRACE4 0 +OP4 TILE4_PhyUC 0 +OP4 TILE5_ITRACE0 0 +OP4 TILE5_ITRACE1 0 +OP4 TILE5_ITRACE2 0 +OP4 TILE5_ITRACE3 0 +OP4 TILE5_ITRACE4 0 +OP4 TILE5_PhyUC 0 +OP4 TILE6_ITRACE0 0 +OP4 TILE6_ITRACE1 0 +OP4 TILE6_ITRACE2 0 +OP4 TILE6_ITRACE3 0 +OP4 TILE6_ITRACE4 0 +OP4 TILE6_PhyUC 0 +OP4 TILE7_ITRACE0 0 +OP4 TILE7_ITRACE1 0 +OP4 TILE7_ITRACE2 0 +OP4 TILE7_ITRACE3 0 +OP4 TILE7_ITRACE4 0 +OP4 TILE7_PhyUC 0 +OP4 E0003B 0 +OP4 E0003C 0 +OP4 E0003D 0 +OP4 E0003E 0 +OP4 E0003F 0 +OP4 E00040 0 +OP4 E00041 0 +OP4 E00042 0 +OP4 E00043 0 +OP4 E00044 0 +OP4 E00045 0 +OP4 E00046 0 +OP4 E00047 0 +OP4 E00048 0 +OP4 E00049 0 +OP4 E0004A 0 +OP4 E0004B 0 +OP4 E0004C 0 +OP4 E0004D 0 +OP4 E0004E 0 +OP4 E0004F 0 +OP4 E00050 0 +OP4 E00051 0 +OP4 E00052 0 +OP4 E00053 0 +OP4 E00054 0 +OP4 E00055 0 +OP4 E00056 0 +OP4 E00057 0 +OP4 E00058 0 +OP4 E00059 0 +OP4 E0005A 0 +OP4 E0005B 0 +OP4 E0005C 0 +OP4 E0005D 0 +OP4 E0005E 0 +OP4 E0005F 0 +OP4 E00060 0 +OP4 E00061 0 +OP4 E00062 0 +OP4 E00063 0 +OP4 E00064 0 +OP4 E00065 0 +OP4 E00066 0 +OP4 E00067 0 +OP4 E00068 0 +OP4 E00069 0 +OP4 E0006A 0 +OP4 E0006B 0 +OP4 E0006C 0 +OP4 E0006D 0 +OP4 E0006E 0 +OP4 E0006F 0 +OP4 E00070 0 +OP4 E00071 0 +OP4 E00072 0 +OP4 E00073 0 +OP4 E00074 0 +OP4 E00075 0 +OP4 E00076 0 +OP4 E00077 0 +OP4 E00078 0 +OP4 E00079 0 +OP4 E0007A 0 +OP4 E0007B 0 +OP4 E0007C 0 +OP4 E0007D 0 +OP4 E0007E 0 +OP4 E0007F 0 +OP4 E00080 0 +OP4 E00081 0 +OP4 E00082 0 +OP4 E00083 0 +OP4 E00084 0 +OP4 E00085 0 +OP4 E00086 0 +OP4 E00087 0 +OP4 E00088 0 +OP4 E00089 0 +OP4 E0008A 0 +OP4 E0008B 0 +OP4 E0008C 0 +OP4 E0008D 0 +OP4 E0008E 0 +OP4 E0008F 0 +OP4 E00090 0 +OP4 E00091 0 +OP4 E00092 0 +OP4 E00093 0 +OP4 E00094 0 +OP4 E00095 0 +OP4 E00096 0 +OP4 E00097 0 +OP4 E00098 0 +OP4 E00099 0 +OP4 E0009A 0 +OP4 E0009B 0 +OP4 E0009C 0 +OP4 E0009D 0 +OP4 E0009E 0 +OP4 E0009F 0 +OP4 E000A0 0 +OP4 E000A1 0 +OP4 E000A2 0 +OP4 E000A3 0 +OP4 E000A4 0 +OP4 E000A5 0 +OP4 E000A6 0 +OP4 E000A7 0 +OP4 E000A8 0 +OP4 E000A9 0 +OP4 E000AA 0 +OP4 E000AB 0 +OP4 E000AC 0 +OP4 E000AD 0 +OP4 E000AE 0 +OP4 E000AF 0 +OP4 E000B0 0 +OP4 E000B1 0 +OP4 E000B2 0 +OP4 E000B3 0 +OP4 E000B4 0 +OP4 E000B5 0 +OP4 E000B6 0 +OP4 E000B7 0 +OP4 E000B8 0 +OP4 E000B9 0 +OP4 E000BA 0 +OP4 E000BB 0 +OP4 E000BC 0 +OP4 E000BD 0 +OP4 E000BE 0 +OP4 E000BF 0 +OP4 E000C0 0 +OP4 E000C1 0 +OP4 E000C2 0 +OP4 E000C3 0 +OP4 E000C4 0 +OP4 E000C5 0 +OP4 E000C6 0 +OP4 E000C7 0 +OP4 E000C8 0 +OP4 E000C9 0 +OP4 E000CA 0 +OP4 E000CB 0 +OP4 E000CC 0 +OP4 E000CD 0 +OP4 E000CE 0 +OP4 E000CF 0 +OP4 E000D0 0 +OP4 E000D1 0 +OP4 E000D2 0 +OP4 E000D3 0 +OP4 E000D4 0 +OP4 E000D5 0 +OP4 E000D6 0 +OP4 E000D7 0 +OP4 E000D8 0 +OP4 E000D9 0 +OP4 E000DA 0 +OP4 E000DB 0 +OP4 E000DC 0 +OP4 E000DD 0 +OP4 E000DE 0 +OP4 E000DF 0 +OP4 E000E0 0 +OP4 E000E1 0 +OP4 E000E2 0 +OP4 E000E3 0 +OP4 E000E4 0 +OP4 E000E5 0 +OP4 E000E6 0 +OP4 E000E7 0 +OP4 E000E8 0 +OP4 E000E9 0 +OP4 E000EA 0 +OP4 E000EB 0 +OP4 E000EC 0 +OP4 E000ED 0 +OP4 E000EE 0 +OP4 E000EF 0 +OP4 E000F0 0 +OP4 E000F1 0 +OP4 E000F2 0 +OP4 E000F3 0 +OP4 E000F4 0 +OP4 E000F5 0 +OP4 E000F6 0 +OP4 E000F7 0 +OP4 E000F8 0 +OP4 E000F9 0 +OP4 E000FA 0 +OP4 E000FB 0 +OP4 E000FC 0 +OP4 E000FD 0 +OP4 E000FE 0 +OP4 E000FF 0 +OP4 E00100 0 +OP4 E00101 0 +OP4 E00102 0 +OP4 E00103 0 +OP4 E00104 0 +OP4 E00105 0 +OP4 E00106 0 +OP4 E00107 0 +OP4 E00108 0 +OP4 E00109 0 +OP4 E0010A 0 +OP4 E0010B 0 +OP4 E0010C 0 +OP4 E0010D 0 +OP4 E0010E 0 +OP4 E0010F 0 +OP4 E00110 0 +OP4 E00111 0 +OP4 E00112 0 +OP4 E00113 0 +OP4 E00114 0 +OP4 E00115 0 +OP4 E00116 0 +OP4 E00117 0 +OP4 E00118 0 +OP4 E00119 0 +OP4 E0011A 0 +OP4 E0011B 0 +OP4 E0011C 0 +OP4 E0011D 0 +OP4 E0011E 0 +OP4 E0011F 0 +OP4 E00120 0 +OP4 E00121 0 +OP4 E00122 0 +OP4 E00123 0 +OP4 E00124 0 +OP4 E00125 0 +OP4 E00126 0 +OP4 E00127 0 +OP4 E00128 0 +OP4 E00129 0 +OP4 E0012A 0 +OP4 E0012B 0 +OP4 E0012C 0 +OP4 E0012D 0 +OP4 E0012E 0 +OP4 E0012F 0 +OP4 E00130 0 +OP4 E00131 0 +OP4 E00132 0 +OP4 E00133 0 +OP4 E00134 0 +OP4 E00135 0 +OP4 E00136 0 +OP4 E00137 0 +OP4 E00138 0 +OP4 E00139 0 +OP4 E0013A 0 +OP4 E0013B 0 +OP4 E0013C 0 +OP4 E0013D 0 +OP4 E0013E 0 +OP4 E0013F 0 +OP4 E00140 0 +OP4 E00141 0 +OP4 E00142 0 +OP4 E00143 0 +OP4 E00144 0 +OP4 E00145 0 +OP4 E00146 0 +OP4 E00147 0 +OP4 E00148 0 +OP4 E00149 0 +OP4 E0014A 0 +OP4 E0014B 0 +OP4 E0014C 0 +OP4 E0014D 0 +OP4 E0014E 0 +OP4 E0014F 0 +OP4 E00150 0 +OP4 E00151 0 +OP4 E00152 0 +OP4 E00153 0 +OP4 E00154 0 +OP4 E00155 0 +OP4 E00156 0 +OP4 E00157 0 +OP4 E00158 0 +OP4 E00159 0 +OP4 E0015A 0 +OP4 E0015B 0 +OP4 E0015C 0 +OP4 E0015D 0 +OP4 E0015E 0 +OP4 E0015F 0 +OP4 E00160 0 +OP4 E00161 0 +OP4 E00162 0 +OP4 E00163 0 +OP4 E00164 0 +OP4 E00165 0 +OP4 E00166 0 +OP4 E00167 0 +OP4 E00168 0 +OP4 E00169 0 +OP4 E0016A 0 +OP4 E0016B 0 +OP4 E0016C 0 +OP4 E0016D 0 +OP4 E0016E 0 +OP4 E0016F 0 +OP4 E00170 0 +OP4 E00171 0 +OP4 E00172 0 +OP4 E00173 0 +OP4 E00174 0 +OP4 E00175 0 +OP4 E00176 0 +OP4 E00177 0 +OP4 E00178 0 +OP4 E00179 0 +OP4 E0017A 0 +OP4 E0017B 0 +OP4 E0017C 0 +OP4 E0017D 0 +OP4 E0017E 0 +OP4 E0017F 0 +OP4 E00180 0 +OP4 E00181 0 +OP4 E00182 0 +OP4 E00183 0 +OP4 E00184 0 +OP4 E00185 0 +OP4 E00186 0 +OP4 E00187 0 +OP4 E00188 0 +OP4 E00189 0 +OP4 E0018A 0 +OP4 E0018B 0 +OP4 E0018C 0 +OP4 E0018D 0 +OP4 E0018E 0 +OP4 E0018F 0 +OP4 E00190 0 +OP4 E00191 0 +OP4 E00192 0 +OP4 E00193 0 +OP4 E00194 0 +OP4 E00195 0 +OP4 E00196 0 +OP4 E00197 0 +OP4 E00198 0 +OP4 E00199 0 +OP4 E0019A 0 +OP4 E0019B 0 +OP4 E0019C 0 +OP4 E0019D 0 +OP4 E0019E 0 +OP4 E0019F 0 +OP4 E001A0 0 +OP4 E001A1 0 +OP4 E001A2 0 +OP4 E001A3 0 +OP4 E001A4 0 +OP4 E001A5 0 +OP4 E001A6 0 +OP4 E001A7 0 +OP4 E001A8 0 +OP4 E001A9 0 +OP4 E001AA 0 +OP4 E001AB 0 +OP4 E001AC 0 +OP4 E001AD 0 +OP4 E001AE 0 +OP4 E001AF 0 +OP4 E001B0 0 +OP4 E001B1 0 +OP4 E001B2 0 +OP4 E001B3 0 +OP4 E001B4 0 +OP4 E001B5 0 +OP4 E001B6 0 +OP4 E001B7 0 +OP4 E001B8 0 +OP4 E001B9 0 +OP4 E001BA 0 +OP4 E001BB 0 +OP4 E001BC 0 +OP4 E001BD 0 +OP4 E001BE 0 +OP4 E001BF 0 +OP4 E001C0 0 +OP4 E001C1 0 +OP4 E001C2 0 +OP4 E001C3 0 +OP4 E001C4 0 +OP4 E001C5 0 +OP4 E001C6 0 +OP4 E001C7 0 +OP4 E001C8 0 +OP4 E001C9 0 +OP4 E001CA 0 +OP4 E001CB 0 +OP4 E001CC 0 +OP4 E001CD 0 +OP4 E001CE 0 +OP4 E001CF 0 +OP4 E001D0 0 +OP4 E001D1 0 +OP4 E001D2 0 +OP4 E001D3 0 +OP4 E001D4 0 +OP4 E001D5 0 +OP4 E001D6 0 +OP4 E001D7 0 +OP4 E001D8 0 +OP4 E001D9 0 +OP4 E001DA 0 +OP4 E001DB 0 +OP4 E001DC 0 +OP4 E001DD 0 +OP4 E001DE 0 +OP4 E001DF 0 +OP4 E001E0 0 +OP4 E001E1 0 +OP4 E001E2 0 +OP4 E001E3 0 +OP4 E001E4 0 +OP4 E001E5 0 +OP4 E001E6 0 +OP4 E001E7 0 +OP4 E001E8 0 +OP4 E001E9 0 +OP4 E001EA 0 +OP4 E001EB 0 +OP4 E001EC 0 +OP4 E001ED 0 +OP4 E001EE 0 +OP4 E001EF 0 +OP4 E001F0 0 +OP4 E001F1 0 +OP4 E001F2 0 +OP4 E001F3 0 +OP4 E001F4 0 +OP4 E001F5 0 +OP4 E001F6 0 +OP4 E001F7 0 +OP4 E001F8 0 +OP4 E001F9 0 +OP4 E001FA 0 +OP4 E001FB 0 +OP4 E001FC 0 +OP4 E001FD 0 +OP4 E001FE 0 +OP4 E001FF 0 +OP4 E00200 0 +OP4 E00201 0 +OP4 E00202 0 +OP4 E00203 0 +OP4 E00204 0 +OP4 E00205 0 +OP4 E00206 0 +OP4 E00207 0 +OP4 E00208 0 +OP4 E00209 0 +OP4 E0020A 0 +OP4 E0020B 0 +OP4 E0020C 0 +OP4 E0020D 0 +OP4 E0020E 0 +OP4 E0020F 0 +OP4 E00210 0 +OP4 E00211 0 +OP4 E00212 0 +OP4 E00213 0 +OP4 E00214 0 +OP4 E00215 0 +OP4 E00216 0 +OP4 E00217 0 +OP4 E00218 0 +OP4 E00219 0 +OP4 E0021A 0 +OP4 E0021B 0 +OP4 E0021C 0 +OP4 E0021D 0 +OP4 E0021E 0 +OP4 E0021F 0 +OP4 E00220 0 +OP4 E00221 0 +OP4 E00222 0 +OP4 E00223 0 +OP4 E00224 0 +OP4 E00225 0 +OP4 E00226 0 +OP4 E00227 0 +OP4 E00228 0 +OP4 E00229 0 +OP4 E0022A 0 +OP4 E0022B 0 +OP4 E0022C 0 +OP4 E0022D 0 +OP4 E0022E 0 +OP4 E0022F 0 +OP4 E00230 0 +OP4 E00231 0 +OP4 E00232 0 +OP4 E00233 0 +OP4 E00234 0 +OP4 E00235 0 +OP4 E00236 0 +OP4 E00237 0 +OP4 E00238 0 +OP4 E00239 0 +OP4 E0023A 0 +OP4 E0023B 0 +OP4 E0023C 0 +OP4 E0023D 0 +OP4 E0023E 0 +OP4 E0023F 0 +OP4 E00240 0 +OP4 E00241 0 +OP4 E00242 0 +OP4 E00243 0 +OP4 E00244 0 +OP4 E00245 0 +OP4 E00246 0 +OP4 E00247 0 +OP4 E00248 0 +OP4 E00249 0 +OP4 E0024A 0 +OP4 E0024B 0 +OP4 E0024C 0 +OP4 E0024D 0 +OP4 E0024E 0 +OP4 E0024F 0 +OP4 E00250 0 +OP4 E00251 0 +OP4 E00252 0 +OP4 E00253 0 +OP4 E00254 0 +OP4 E00255 0 +OP4 E00256 0 +OP4 E00257 0 +OP4 E00258 0 +OP4 E00259 0 +OP4 E0025A 0 +OP4 E0025B 0 +OP4 E0025C 0 +OP4 E0025D 0 +OP4 E0025E 0 +OP4 E0025F 0 +OP4 E00260 0 +OP4 E00261 0 +OP4 E00262 0 +OP4 E00263 0 +OP4 E00264 0 +OP4 E00265 0 +OP4 E00266 0 +OP4 E00267 0 +OP4 E00268 0 +OP4 E00269 0 +OP4 E0026A 0 +OP4 E0026B 0 +OP4 E0026C 0 +OP4 E0026D 0 +OP4 E0026E 0 +OP4 E0026F 0 +OP4 E00270 0 +OP4 E00271 0 +OP4 E00272 0 +OP4 E00273 0 +OP4 E00274 0 +OP4 E00275 0 +OP4 E00276 0 +OP4 E00277 0 +OP4 E00278 0 +OP4 E00279 0 +OP4 E0027A 0 +OP4 E0027B 0 +OP4 E0027C 0 +OP4 E0027D 0 +OP4 E0027E 0 +OP4 E0027F 0 +OP4 E00280 0 +OP4 E00281 0 +OP4 E00282 0 +OP4 E00283 0 +OP4 E00284 0 +OP4 E00285 0 +OP4 E00286 0 +OP4 E00287 0 +OP4 E00288 0 +OP4 E00289 0 +OP4 E0028A 0 +OP4 E0028B 0 +OP4 E0028C 0 +OP4 E0028D 0 +OP4 E0028E 0 +OP4 E0028F 0 +OP4 E00290 0 +OP4 E00291 0 +OP4 E00292 0 +OP4 E00293 0 +OP4 E00294 0 +OP4 E00295 0 +OP4 E00296 0 +OP4 E00297 0 +OP4 E00298 0 +OP4 E00299 0 +OP4 E0029A 0 +OP4 E0029B 0 +OP4 E0029C 0 +OP4 E0029D 0 +OP4 E0029E 0 +OP4 E0029F 0 +OP4 E002A0 0 +OP4 E002A1 0 +OP4 E002A2 0 +OP4 E002A3 0 +OP4 E002A4 0 +OP4 E002A5 0 +OP4 E002A6 0 +OP4 E002A7 0 +OP4 E002A8 0 +OP4 E002A9 0 +OP4 E002AA 0 +OP4 E002AB 0 +OP4 E002AC 0 +OP4 E002AD 0 +OP4 E002AE 0 +OP4 E002AF 0 +OP4 E002B0 0 +OP4 E002B1 0 +OP4 E002B2 0 +OP4 E002B3 0 +OP4 E002B4 0 +OP4 E002B5 0 +OP4 E002B6 0 +OP4 E002B7 0 +OP4 E002B8 0 +OP4 E002B9 0 +OP4 E002BA 0 +OP4 E002BB 0 +OP4 E002BC 0 +OP4 E002BD 0 +OP4 E002BE 0 +OP4 E002BF 0 +OP4 E002C0 0 +OP4 E002C1 0 +OP4 E002C2 0 +OP4 E002C3 0 +OP4 E002C4 0 +OP4 E002C5 0 +OP4 E002C6 0 +OP4 E002C7 0 +OP4 E002C8 0 +OP4 E002C9 0 +OP4 E002CA 0 +OP4 E002CB 0 +OP4 E002CC 0 +OP4 E002CD 0 +OP4 E002CE 0 +OP4 E002CF 0 +OP4 E002D0 0 +OP4 E002D1 0 +OP4 E002D2 0 +OP4 E002D3 0 +OP4 E002D4 0 +OP4 E002D5 0 +OP4 E002D6 0 +OP4 E002D7 0 +OP4 E002D8 0 +OP4 E002D9 0 +OP4 E002DA 0 +OP4 E002DB 0 +OP4 E002DC 0 +OP4 E002DD 0 +OP4 E002DE 0 +OP4 E002DF 0 +OP4 E002E0 0 +OP4 E002E1 0 +OP4 E002E2 0 +OP4 E002E3 0 +OP4 E002E4 0 +OP4 E002E5 0 +OP4 E002E6 0 +OP4 E002E7 0 +OP4 E002E8 0 +OP4 E002E9 0 +OP4 E002EA 0 +OP4 E002EB 0 +OP4 E002EC 0 +OP4 E002ED 0 +OP4 E002EE 0 +OP4 E002EF 0 +OP4 E002F0 0 +OP4 E002F1 0 +OP4 E002F2 0 +OP4 E002F3 0 +OP4 E002F4 0 +OP4 E002F5 0 +OP4 E002F6 0 +OP4 E002F7 0 +OP4 E002F8 0 +OP4 E002F9 0 +OP4 E002FA 0 +OP4 E002FB 0 +OP4 E002FC 0 +OP4 E002FD 0 +OP4 E002FE 0 +OP4 E002FF 0 +OP4 E00300 0 +OP4 E00301 0 +OP4 E00302 0 +OP4 E00303 0 +OP4 E00304 0 +OP4 E00305 0 +OP4 E00306 0 +OP4 E00307 0 +OP4 E00308 0 +OP4 E00309 0 +OP4 E0030A 0 +OP4 E0030B 0 +OP4 E0030C 0 +OP4 E0030D 0 +OP4 E0030E 0 +OP4 E0030F 0 +OP4 E00310 0 +OP4 E00311 0 +OP4 E00312 0 +OP4 E00313 0 +OP4 E00314 0 +OP4 E00315 0 +OP4 E00316 0 +OP4 E00317 0 +OP4 E00318 0 +OP4 E00319 0 +OP4 E0031A 0 +OP4 E0031B 0 +OP4 E0031C 0 +OP4 E0031D 0 +OP4 E0031E 0 +OP4 E0031F 0 +OP4 E00320 0 +OP4 E00321 0 +OP4 E00322 0 +OP4 E00323 0 +OP4 E00324 0 +OP4 E00325 0 +OP4 E00326 0 +OP4 E00327 0 +OP4 E00328 0 +OP4 E00329 0 +OP4 E0032A 0 +OP4 E0032B 0 +OP4 E0032C 0 +OP4 E0032D 0 +OP4 E0032E 0 +OP4 E0032F 0 +OP4 E00330 0 +OP4 E00331 0 +OP4 E00332 0 +OP4 E00333 0 +OP4 E00334 0 +OP4 E00335 0 +OP4 E00336 0 +OP4 E00337 0 +OP4 E00338 0 +OP4 E00339 0 +OP4 E0033A 0 +OP4 E0033B 0 +OP4 E0033C 0 +OP4 E0033D 0 +OP4 E0033E 0 +OP4 E0033F 0 +OP4 E00340 0 +OP4 E00341 0 +OP4 E00342 0 +OP4 E00343 0 +OP4 E00344 0 +OP4 E00345 0 +OP4 E00346 0 +OP4 E00347 0 +OP4 E00348 0 +OP4 E00349 0 +OP4 E0034A 0 +OP4 E0034B 0 +OP4 E0034C 0 +OP4 E0034D 0 +OP4 E0034E 0 +OP4 E0034F 0 +OP4 E00350 0 +OP4 E00351 0 +OP4 E00352 0 +OP4 E00353 0 +OP4 E00354 0 +OP4 E00355 0 +OP4 E00356 0 +OP4 E00357 0 +OP4 E00358 0 +OP4 E00359 0 +OP4 E0035A 0 +OP4 E0035B 0 +OP4 E0035C 0 +OP4 E0035D 0 +OP4 E0035E 0 +OP4 E0035F 0 +OP4 E00360 0 +OP4 E00361 0 +OP4 E00362 0 +OP4 E00363 0 +OP4 E00364 0 +OP4 E00365 0 +OP4 E00366 0 +OP4 E00367 0 +OP4 E00368 0 +OP4 E00369 0 +OP4 E0036A 0 +OP4 E0036B 0 +OP4 E0036C 0 +OP4 E0036D 0 +OP4 E0036E 0 +OP4 E0036F 0 +OP4 E00370 0 +OP4 E00371 0 +OP4 E00372 0 +OP4 E00373 0 +OP4 E00374 0 +OP4 E00375 0 +OP4 E00376 0 +OP4 E00377 0 +OP4 E00378 0 +OP4 E00379 0 +OP4 E0037A 0 +OP4 E0037B 0 +OP4 E0037C 0 +OP4 E0037D 0 +OP4 E0037E 0 +OP4 E0037F 0 +OP4 E00380 0 +OP4 E00381 0 +OP4 E00382 0 +OP4 E00383 0 +OP4 E00384 0 +OP4 E00385 0 +OP4 E00386 0 +OP4 E00387 0 +OP4 E00388 0 +OP4 E00389 0 +OP4 E0038A 0 +OP4 E0038B 0 +OP4 E0038C 0 +OP4 E0038D 0 +OP4 E0038E 0 +OP4 E0038F 0 +OP4 E00390 0 +OP4 E00391 0 +OP4 E00392 0 +OP4 E00393 0 +OP4 E00394 0 +OP4 E00395 0 +OP4 E00396 0 +OP4 E00397 0 +OP4 E00398 0 +OP4 E00399 0 +OP4 E0039A 0 +OP4 E0039B 0 +OP4 E0039C 0 +OP4 E0039D 0 +OP4 E0039E 0 +OP4 E0039F 0 +OP4 E003A0 0 +OP4 E003A1 0 +OP4 E003A2 0 +OP4 E003A3 0 +OP4 E003A4 0 +OP4 E003A5 0 +OP4 E003A6 0 +OP4 E003A7 0 +OP4 E003A8 0 +OP4 E003A9 0 +OP4 E003AA 0 +OP4 E003AB 0 +OP4 E003AC 0 +OP4 E003AD 0 +OP4 E003AE 0 +OP4 E003AF 0 +OP4 E003B0 0 +OP4 E003B1 0 +OP4 E003B2 0 +OP4 E003B3 0 +OP4 E003B4 0 +OP4 E003B5 0 +OP4 E003B6 0 +OP4 E003B7 0 +OP4 E003B8 0 +OP4 E003B9 0 +OP4 E003BA 0 +OP4 E003BB 0 +OP4 E003BC 0 +OP4 E003BD 0 +OP4 E003BE 0 +OP4 E003BF 0 +OP4 E003C0 0 +OP4 E003C1 0 +OP4 E003C2 0 +OP4 E003C3 0 +OP4 E003C4 0 +OP4 E003C5 0 +OP4 E003C6 0 +OP4 E003C7 0 +OP4 E003C8 0 +OP4 E003C9 0 +OP4 E003CA 0 +OP4 E003CB 0 +OP4 E003CC 0 +OP4 E003CD 0 +OP4 E003CE 0 +OP4 E003CF 0 +OP4 E003D0 0 +OP4 E003D1 0 +OP4 E003D2 0 +OP4 E003D3 0 +OP4 E003D4 0 +OP4 E003D5 0 +OP4 E003D6 0 +OP4 E003D7 0 +OP4 E003D8 0 +OP4 E003D9 0 +OP4 E003DA 0 +OP4 E003DB 0 +OP4 E003DC 0 +OP4 E003DD 0 +OP4 E003DE 0 +OP4 E003DF 0 +OP4 E003E0 0 +OP4 E003E1 0 +OP4 E003E2 0 +OP4 E003E3 0 +OP4 E003E4 0 +OP4 E003E5 0 +OP4 E003E6 0 +OP4 E003E7 0 +OP4 E003E8 0 +OP4 E003E9 0 +OP4 E003EA 0 +OP4 E003EB 0 +OP4 E003EC 0 +OP4 E003ED 0 +OP4 E003EE 0 +OP4 E003EF 0 +OP4 E003F0 0 +OP4 E003F1 0 +OP4 E003F2 0 +OP4 E003F3 0 +OP4 E003F4 0 +OP4 E003F5 0 +OP4 E003F6 0 +OP4 E003F7 0 +OP4 E003F8 0 +OP4 E003F9 0 +OP4 E003FA 0 +OP4 E003FB 0 +OP4 E003FC 0 +OP4 E003FD 0 +OP4 E003FE 0 +OP4 E003FF 0 +OP4 E00400 0 +OP4 E00401 0 +OP4 E00402 0 +OP4 E00403 0 +OP4 E00404 0 +OP4 E00405 0 +OP4 E00406 0 +OP4 E00407 0 +OP4 E00408 0 +OP4 E00409 0 +OP4 E0040A 0 +OP4 E0040B 0 +OP4 E0040C 0 +OP4 E0040D 0 +OP4 E0040E 0 +OP4 E0040F 0 +OP4 E00410 0 +OP4 E00411 0 +OP4 E00412 0 +OP4 E00413 0 +OP4 E00414 0 +OP4 E00415 0 +OP4 E00416 0 +OP4 E00417 0 +OP4 E00418 0 +OP4 E00419 0 +OP4 E0041A 0 +OP4 E0041B 0 +OP4 E0041C 0 +OP4 E0041D 0 +OP4 E0041E 0 +OP4 E0041F 0 +OP4 E00420 0 +OP4 E00421 0 +OP4 E00422 0 +OP4 E00423 0 +OP4 E00424 0 +OP4 E00425 0 +OP4 E00426 0 +OP4 E00427 0 +OP4 E00428 0 +OP4 E00429 0 +OP4 E0042A 0 +OP4 E0042B 0 +OP4 E0042C 0 +OP4 E0042D 0 +OP4 E0042E 0 +OP4 E0042F 0 +OP4 E00430 0 +OP4 E00431 0 +OP4 E00432 0 +OP4 E00433 0 +OP4 E00434 0 +OP4 E00435 0 +OP4 E00436 0 +OP4 E00437 0 +OP4 E00438 0 +OP4 E00439 0 +OP4 E0043A 0 +OP4 E0043B 0 +OP4 E0043C 0 +OP4 E0043D 0 +OP4 E0043E 0 +OP4 E0043F 0 +OP4 E00440 0 +OP4 E00441 0 +OP4 E00442 0 +OP4 E00443 0 +OP4 E00444 0 +OP4 E00445 0 +OP4 E00446 0 +OP4 E00447 0 +OP4 E00448 0 +OP4 E00449 0 +OP4 E0044A 0 +OP4 E0044B 0 +OP4 E0044C 0 +OP4 E0044D 0 +OP4 E0044E 0 +OP4 E0044F 0 +OP4 E00450 0 +OP4 E00451 0 +OP4 E00452 0 +OP4 E00453 0 +OP4 E00454 0 +OP4 E00455 0 +OP4 E00456 0 +OP4 E00457 0 +OP4 E00458 0 +OP4 E00459 0 +OP4 E0045A 0 +OP4 E0045B 0 +OP4 E0045C 0 +OP4 E0045D 0 +OP4 E0045E 0 +OP4 E0045F 0 +OP4 E00460 0 +OP4 E00461 0 +OP4 E00462 0 +OP4 E00463 0 +OP4 E00464 0 +OP4 E00465 0 +OP4 E00466 0 +OP4 E00467 0 +OP4 E00468 0 +OP4 E00469 0 +OP4 E0046A 0 +OP4 E0046B 0 +OP4 E0046C 0 +OP4 E0046D 0 +OP4 E0046E 0 +OP4 E0046F 0 +OP4 E00470 0 +OP4 E00471 0 +OP4 E00472 0 +OP4 E00473 0 +OP4 E00474 0 +OP4 E00475 0 +OP4 E00476 0 +OP4 E00477 0 +OP4 E00478 0 +OP4 E00479 0 +OP4 E0047A 0 +OP4 E0047B 0 +OP4 E0047C 0 +OP4 E0047D 0 +OP4 E0047E 0 +OP4 E0047F 0 +OP4 E00480 0 +OP4 E00481 0 +OP4 E00482 0 +OP4 E00483 0 +OP4 E00484 0 +OP4 E00485 0 +OP4 E00486 0 +OP4 E00487 0 +OP4 E00488 0 +OP4 E00489 0 +OP4 E0048A 0 +OP4 E0048B 0 +OP4 E0048C 0 +OP4 E0048D 0 +OP4 E0048E 0 +OP4 E0048F 0 +OP4 E00490 0 +OP4 E00491 0 +OP4 E00492 0 +OP4 E00493 0 +OP4 E00494 0 +OP4 E00495 0 +OP4 E00496 0 +OP4 E00497 0 +OP4 E00498 0 +OP4 E00499 0 +OP4 E0049A 0 +OP4 E0049B 0 +OP4 E0049C 0 +OP4 E0049D 0 +OP4 E0049E 0 +OP4 E0049F 0 +OP4 E004A0 0 +OP4 E004A1 0 +OP4 E004A2 0 +OP4 E004A3 0 +OP4 E004A4 0 +OP4 E004A5 0 +OP4 E004A6 0 +OP4 E004A7 0 +OP4 E004A8 0 +OP4 E004A9 0 +OP4 E004AA 0 +OP4 E004AB 0 +OP4 E004AC 0 +OP4 E004AD 0 +OP4 E004AE 0 +OP4 E004AF 0 +OP4 E004B0 0 +OP4 E004B1 0 +OP4 E004B2 0 +OP4 E004B3 0 +OP4 E004B4 0 +OP4 E004B5 0 +OP4 E004B6 0 +OP4 E004B7 0 +OP4 E004B8 0 +OP4 E004B9 0 +OP4 E004BA 0 +OP4 E004BB 0 +OP4 E004BC 0 +OP4 E004BD 0 +OP4 E004BE 0 +OP4 E004BF 0 +OP4 E004C0 0 +OP4 E004C1 0 +OP4 E004C2 0 +OP4 E004C3 0 +OP4 E004C4 0 +OP4 E004C5 0 +OP4 E004C6 0 +OP4 E004C7 0 +OP4 E004C8 0 +OP4 E004C9 0 +OP4 E004CA 0 +OP4 E004CB 0 +OP4 E004CC 0 +OP4 E004CD 0 +OP4 E004CE 0 +OP4 E004CF 0 +OP4 E004D0 0 +OP4 E004D1 0 +OP4 E004D2 0 +OP4 E004D3 0 +OP4 E004D4 0 +OP4 E004D5 0 +OP4 E004D6 0 +OP4 E004D7 0 +OP4 E004D8 0 +OP4 E004D9 0 +OP4 E004DA 0 +OP4 E004DB 0 +OP4 E004DC 0 +OP4 E004DD 0 +OP4 E004DE 0 +OP4 E004DF 0 +OP4 E004E0 0 +OP4 E004E1 0 +OP4 E004E2 0 +OP4 E004E3 0 +OP4 E004E4 0 +OP4 E004E5 0 +OP4 E004E6 0 +OP4 E004E7 0 +OP4 E004E8 0 +OP4 E004E9 0 +OP4 E004EA 0 +OP4 E004EB 0 +OP4 E004EC 0 +OP4 E004ED 0 +OP4 E004EE 0 +OP4 E004EF 0 +OP4 E004F0 0 +OP4 E004F1 0 +OP4 E004F2 0 +OP4 E004F3 0 +OP4 E004F4 0 +OP4 E004F5 0 +OP4 E004F6 0 +OP4 E004F7 0 +OP4 E004F8 0 +OP4 E004F9 0 +OP4 E004FA 0 +OP4 E004FB 0 +OP4 E004FC 0 +OP4 E004FD 0 +OP4 E004FE 0 +OP4 E004FF 0 +OP4 E00500 0 +OP4 E00501 0 +OP4 E00502 0 +OP4 E00503 0 +OP4 E00504 0 +OP4 E00505 0 +OP4 E00506 0 +OP4 E00507 0 +OP4 E00508 0 +OP4 E00509 0 +OP4 E0050A 0 +OP4 E0050B 0 +OP4 E0050C 0 +OP4 E0050D 0 +OP4 E0050E 0 +OP4 E0050F 0 +OP4 E00510 0 +OP4 E00511 0 +OP4 E00512 0 +OP4 E00513 0 +OP4 E00514 0 +OP4 E00515 0 +OP4 E00516 0 +OP4 E00517 0 +OP4 E00518 0 +OP4 E00519 0 +OP4 E0051A 0 +OP4 E0051B 0 +OP4 E0051C 0 +OP4 E0051D 0 +OP4 E0051E 0 +OP4 E0051F 0 +OP4 E00520 0 +OP4 E00521 0 +OP4 E00522 0 +OP4 E00523 0 +OP4 E00524 0 +OP4 E00525 0 +OP4 E00526 0 +OP4 E00527 0 +OP4 E00528 0 +OP4 E00529 0 +OP4 E0052A 0 +OP4 E0052B 0 +OP4 E0052C 0 +OP4 E0052D 0 +OP4 E0052E 0 +OP4 E0052F 0 +OP4 E00530 0 +OP4 E00531 0 +OP4 E00532 0 +OP4 E00533 0 +OP4 E00534 0 +OP4 E00535 0 +OP4 E00536 0 +OP4 E00537 0 +OP4 E00538 0 +OP4 E00539 0 +OP4 E0053A 0 +OP4 E0053B 0 +OP4 E0053C 0 +OP4 E0053D 0 +OP4 E0053E 0 +OP4 E0053F 0 +OP4 E00540 0 +OP4 E00541 0 +OP4 E00542 0 +OP4 E00543 0 +OP4 E00544 0 +OP4 E00545 0 +OP4 E00546 0 +OP4 E00547 0 +OP4 E00548 0 +OP4 E00549 0 +OP4 E0054A 0 +OP4 E0054B 0 +OP4 E0054C 0 +OP4 E0054D 0 +OP4 E0054E 0 +OP4 E0054F 0 +OP4 E00550 0 +OP4 E00551 0 +OP4 E00552 0 +OP4 E00553 0 +OP4 E00554 0 +OP4 E00555 0 +OP4 E00556 0 +OP4 E00557 0 +OP4 E00558 0 +OP4 E00559 0 +OP4 E0055A 0 +OP4 E0055B 0 +OP4 E0055C 0 +OP4 E0055D 0 +OP4 E0055E 0 +OP4 E0055F 0 +OP4 E00560 0 +OP4 E00561 0 +OP4 E00562 0 +OP4 E00563 0 +OP4 E00564 0 +OP4 E00565 0 +OP4 E00566 0 +OP4 E00567 0 +OP4 E00568 0 +OP4 E00569 0 +OP4 E0056A 0 +OP4 E0056B 0 +OP4 E0056C 0 +OP4 E0056D 0 +OP4 E0056E 0 +OP4 E0056F 0 +OP4 E00570 0 +OP4 E00571 0 +OP4 E00572 0 +OP4 E00573 0 +OP4 E00574 0 +OP4 E00575 0 +OP4 E00576 0 +OP4 E00577 0 +OP4 E00578 0 +OP4 E00579 0 +OP4 E0057A 0 +OP4 E0057B 0 +OP4 E0057C 0 +OP4 E0057D 0 +OP4 E0057E 0 +OP4 E0057F 0 +OP4 E00580 0 +OP4 E00581 0 +OP4 E00582 0 +OP4 E00583 0 +OP4 E00584 0 +OP4 E00585 0 +OP4 E00586 0 +OP4 E00587 0 +OP4 E00588 0 +OP4 E00589 0 +OP4 E0058A 0 +OP4 E0058B 0 +OP4 E0058C 0 +OP4 E0058D 0 +OP4 E0058E 0 +OP4 E0058F 0 +OP4 E00590 0 +OP4 E00591 0 +OP4 E00592 0 +OP4 E00593 0 +OP4 E00594 0 +OP4 E00595 0 +OP4 E00596 0 +OP4 E00597 0 +OP4 E00598 0 +OP4 E00599 0 +OP4 E0059A 0 +OP4 E0059B 0 +OP4 E0059C 0 +OP4 E0059D 0 +OP4 E0059E 0 +OP4 E0059F 0 +OP4 E005A0 0 +OP4 E005A1 0 +OP4 E005A2 0 +OP4 E005A3 0 +OP4 E005A4 0 +OP4 E005A5 0 +OP4 E005A6 0 +OP4 E005A7 0 +OP4 E005A8 0 +OP4 E005A9 0 +OP4 E005AA 0 +OP4 E005AB 0 +OP4 E005AC 0 +OP4 E005AD 0 +OP4 E005AE 0 +OP4 E005AF 0 +OP4 E005B0 0 +OP4 E005B1 0 +OP4 E005B2 0 +OP4 E005B3 0 +OP4 E005B4 0 +OP4 E005B5 0 +OP4 E005B6 0 +OP4 E005B7 0 +OP4 E005B8 0 +OP4 E005B9 0 +OP4 E005BA 0 +OP4 E005BB 0 +OP4 E005BC 0 +OP4 E005BD 0 +OP4 E005BE 0 +OP4 E005BF 0 +OP4 E005C0 0 +OP4 E005C1 0 +OP4 E005C2 0 +OP4 E005C3 0 +OP4 E005C4 0 +OP4 E005C5 0 +OP4 E005C6 0 +OP4 E005C7 0 +OP4 E005C8 0 +OP4 E005C9 0 +OP4 E005CA 0 +OP4 E005CB 0 +OP4 E005CC 0 +OP4 E005CD 0 +OP4 E005CE 0 +OP4 E005CF 0 +OP4 E005D0 0 +OP4 E005D1 0 +OP4 E005D2 0 +OP4 E005D3 0 +OP4 E005D4 0 +OP4 E005D5 0 +OP4 E005D6 0 +OP4 E005D7 0 +OP4 E005D8 0 +OP4 E005D9 0 +OP4 E005DA 0 +OP4 E005DB 0 +OP4 E005DC 0 +OP4 E005DD 0 +OP4 E005DE 0 +OP4 E005DF 0 +OP4 E005E0 0 +OP4 E005E1 0 +OP4 E005E2 0 +OP4 E005E3 0 +OP4 E005E4 0 +OP4 E005E5 0 +OP4 E005E6 0 +OP4 E005E7 0 +OP4 E005E8 0 +OP4 E005E9 0 +OP4 E005EA 0 +OP4 E005EB 0 +OP4 E005EC 0 +OP4 E005ED 0 +OP4 E005EE 0 +OP4 E005EF 0 +OP4 E005F0 0 +OP4 E005F1 0 +OP4 E005F2 0 +OP4 E005F3 0 +OP4 E005F4 0 +OP4 E005F5 0 +OP4 E005F6 0 +OP4 E005F7 0 +OP4 E005F8 0 +OP4 E005F9 0 +OP4 E005FA 0 +OP4 E005FB 0 +OP4 E005FC 0 +OP4 E005FD 0 +OP4 E005FE 0 +OP4 E005FF 0 +OP4 E00600 0 +OP4 E00601 0 +OP4 E00602 0 +OP4 E00603 0 +OP4 E00604 0 +OP4 E00605 0 +OP4 E00606 0 +OP4 E00607 0 +OP4 E00608 0 +OP4 E00609 0 +OP4 E0060A 0 +OP4 E0060B 0 +OP4 E0060C 0 +OP4 E0060D 0 +OP4 E0060E 0 +OP4 E0060F 0 +OP4 E00610 0 +OP4 E00611 0 +OP4 E00612 0 +OP4 E00613 0 +OP4 E00614 0 +OP4 E00615 0 +OP4 E00616 0 +OP4 E00617 0 +OP4 E00618 0 +OP4 E00619 0 +OP4 E0061A 0 +OP4 E0061B 0 +OP4 E0061C 0 +OP4 E0061D 0 +OP4 E0061E 0 +OP4 E0061F 0 +OP4 E00620 0 +OP4 E00621 0 +OP4 E00622 0 +OP4 E00623 0 +OP4 E00624 0 +OP4 E00625 0 +OP4 E00626 0 +OP4 E00627 0 +OP4 E00628 0 +OP4 E00629 0 +OP4 E0062A 0 +OP4 E0062B 0 +OP4 E0062C 0 +OP4 E0062D 0 +OP4 E0062E 0 +OP4 E0062F 0 +OP4 E00630 0 +OP4 E00631 0 +OP4 E00632 0 +OP4 E00633 0 +OP4 E00634 0 +OP4 E00635 0 +OP4 E00636 0 +OP4 E00637 0 +OP4 E00638 0 +OP4 E00639 0 +OP4 E0063A 0 +OP4 E0063B 0 +OP4 E0063C 0 +OP4 E0063D 0 +OP4 E0063E 0 +OP4 E0063F 0 +OP4 E00640 0 +OP4 E00641 0 +OP4 E00642 0 +OP4 E00643 0 +OP4 E00644 0 +OP4 E00645 0 +OP4 E00646 0 +OP4 E00647 0 +OP4 E00648 0 +OP4 E00649 0 +OP4 E0064A 0 +OP4 E0064B 0 +OP4 E0064C 0 +OP4 E0064D 0 +OP4 E0064E 0 +OP4 E0064F 0 +OP4 E00650 0 +OP4 E00651 0 +OP4 E00652 0 +OP4 E00653 0 +OP4 E00654 0 +OP4 E00655 0 +OP4 E00656 0 +OP4 E00657 0 +OP4 E00658 0 +OP4 E00659 0 +OP4 E0065A 0 +OP4 E0065B 0 +OP4 E0065C 0 +OP4 E0065D 0 +OP4 E0065E 0 +OP4 E0065F 0 +OP4 E00660 0 +OP4 E00661 0 +OP4 E00662 0 +OP4 E00663 0 +OP4 E00664 0 +OP4 E00665 0 +OP4 E00666 0 +OP4 E00667 0 +OP4 E00668 0 +OP4 E00669 0 +OP4 E0066A 0 +OP4 E0066B 0 +OP4 E0066C 0 +OP4 E0066D 0 +OP4 E0066E 0 +OP4 E0066F 0 +OP4 E00670 0 +OP4 E00671 0 +OP4 E00672 0 +OP4 E00673 0 +OP4 E00674 0 +OP4 E00675 0 +OP4 E00676 0 +OP4 E00677 0 +OP4 E00678 0 +OP4 E00679 0 +OP4 E0067A 0 +OP4 E0067B 0 +OP4 E0067C 0 +OP4 E0067D 0 +OP4 E0067E 0 +OP4 E0067F 0 +OP4 E00680 0 +OP4 E00681 0 +OP4 E00682 0 +OP4 E00683 0 +OP4 E00684 0 +OP4 E00685 0 +OP4 E00686 0 +OP4 E00687 0 +OP4 E00688 0 +OP4 E00689 0 +OP4 E0068A 0 +OP4 E0068B 0 +OP4 E0068C 0 +OP4 E0068D 0 +OP4 E0068E 0 +OP4 E0068F 0 +OP4 E00690 0 +OP4 E00691 0 +OP4 E00692 0 +OP4 E00693 0 +OP4 E00694 0 +OP4 E00695 0 +OP4 E00696 0 +OP4 E00697 0 +OP4 E00698 0 +OP4 E00699 0 +OP4 E0069A 0 +OP4 E0069B 0 +OP4 E0069C 0 +OP4 E0069D 0 +OP4 E0069E 0 +OP4 E0069F 0 +OP4 E006A0 0 +OP4 E006A1 0 +OP4 E006A2 0 +OP4 E006A3 0 +OP4 E006A4 0 +OP4 E006A5 0 +OP4 E006A6 0 +OP4 E006A7 0 +OP4 E006A8 0 +OP4 E006A9 0 +OP4 E006AA 0 +OP4 E006AB 0 +OP4 E006AC 0 +OP4 E006AD 0 +OP4 E006AE 0 +OP4 E006AF 0 +OP4 E006B0 0 +OP4 E006B1 0 +OP4 E006B2 0 +OP4 E006B3 0 +OP4 E006B4 0 +OP4 E006B5 0 +OP4 E006B6 0 +OP4 E006B7 0 +OP4 E006B8 0 +OP4 E006B9 0 +OP4 E006BA 0 +OP4 E006BB 0 +OP4 E006BC 0 +OP4 E006BD 0 +OP4 E006BE 0 +OP4 E006BF 0 +OP4 E006C0 0 +OP4 E006C1 0 +OP4 E006C2 0 +OP4 E006C3 0 +OP4 E006C4 0 +OP4 E006C5 0 +OP4 E006C6 0 +OP4 E006C7 0 +OP4 E006C8 0 +OP4 E006C9 0 +OP4 E006CA 0 +OP4 E006CB 0 +OP4 E006CC 0 +OP4 E006CD 0 +OP4 E006CE 0 +OP4 E006CF 0 +OP4 E006D0 0 +OP4 E006D1 0 +OP4 E006D2 0 +OP4 E006D3 0 +OP4 E006D4 0 +OP4 E006D5 0 +OP4 E006D6 0 +OP4 E006D7 0 +OP4 E006D8 0 +OP4 E006D9 0 +OP4 E006DA 0 +OP4 E006DB 0 +OP4 E006DC 0 +OP4 E006DD 0 +OP4 E006DE 0 +OP4 E006DF 0 +OP4 E006E0 0 +OP4 E006E1 0 +OP4 E006E2 0 +OP4 E006E3 0 +OP4 E006E4 0 +OP4 E006E5 0 +OP4 E006E6 0 +OP4 E006E7 0 +OP4 E006E8 0 +OP4 E006E9 0 +OP4 E006EA 0 +OP4 E006EB 0 +OP4 E006EC 0 +OP4 E006ED 0 +OP4 E006EE 0 +OP4 E006EF 0 +OP4 E006F0 0 +OP4 E006F1 0 +OP4 E006F2 0 +OP4 E006F3 0 +OP4 E006F4 0 +OP4 E006F5 0 +OP4 E006F6 0 +OP4 E006F7 0 +OP4 E006F8 0 +OP4 E006F9 0 +OP4 E006FA 0 +OP4 E006FB 0 +OP4 E006FC 0 +OP4 E006FD 0 +OP4 E006FE 0 +OP4 E006FF 0 +OP4 E00700 0 +OP4 E00701 0 +OP4 E00702 0 +OP4 E00703 0 +OP4 E00704 0 +OP4 E00705 0 +OP4 E00706 0 +OP4 E00707 0 +OP4 E00708 0 +OP4 E00709 0 +OP4 E0070A 0 +OP4 E0070B 0 +OP4 E0070C 0 +OP4 E0070D 0 +OP4 E0070E 0 +OP4 E0070F 0 +OP4 E00710 0 +OP4 E00711 0 +OP4 E00712 0 +OP4 E00713 0 +OP4 E00714 0 +OP4 E00715 0 +OP4 E00716 0 +OP4 E00717 0 +OP4 E00718 0 +OP4 E00719 0 +OP4 E0071A 0 +OP4 E0071B 0 +OP4 E0071C 0 +OP4 E0071D 0 +OP4 E0071E 0 +OP4 E0071F 0 +OP4 E00720 0 +OP4 E00721 0 +OP4 E00722 0 +OP4 E00723 0 +OP4 E00724 0 +OP4 E00725 0 +OP4 E00726 0 +OP4 E00727 0 +OP4 E00728 0 +OP4 E00729 0 +OP4 E0072A 0 +OP4 E0072B 0 +OP4 E0072C 0 +OP4 E0072D 0 +OP4 E0072E 0 +OP4 E0072F 0 +OP4 E00730 0 +OP4 E00731 0 +OP4 E00732 0 +OP4 E00733 0 +OP4 E00734 0 +OP4 E00735 0 +OP4 E00736 0 +OP4 E00737 0 +OP4 E00738 0 +OP4 E00739 0 +OP4 E0073A 0 +OP4 E0073B 0 +OP4 E0073C 0 +OP4 E0073D 0 +OP4 E0073E 0 +OP4 E0073F 0 +OP4 E00740 0 +OP4 E00741 0 +OP4 E00742 0 +OP4 E00743 0 +OP4 E00744 0 +OP4 E00745 0 +OP4 E00746 0 +OP4 E00747 0 +OP4 E00748 0 +OP4 E00749 0 +OP4 E0074A 0 +OP4 E0074B 0 +OP4 E0074C 0 +OP4 E0074D 0 +OP4 E0074E 0 +OP4 E0074F 0 +OP4 E00750 0 +OP4 E00751 0 +OP4 E00752 0 +OP4 E00753 0 +OP4 E00754 0 +OP4 E00755 0 +OP4 E00756 0 +OP4 E00757 0 +OP4 E00758 0 +OP4 E00759 0 +OP4 E0075A 0 +OP4 E0075B 0 +OP4 E0075C 0 +OP4 E0075D 0 +OP4 E0075E 0 +OP4 E0075F 0 +OP4 E00760 0 +OP4 E00761 0 +OP4 E00762 0 +OP4 E00763 0 +OP4 E00764 0 +OP4 E00765 0 +OP4 E00766 0 +OP4 E00767 0 +OP4 E00768 0 +OP4 E00769 0 +OP4 E0076A 0 +OP4 E0076B 0 +OP4 E0076C 0 +OP4 E0076D 0 +OP4 E0076E 0 +OP4 E0076F 0 +OP4 E00770 0 +OP4 E00771 0 +OP4 E00772 0 +OP4 E00773 0 +OP4 E00774 0 +OP4 E00775 0 +OP4 E00776 0 +OP4 E00777 0 +OP4 E00778 0 +OP4 E00779 0 +OP4 E0077A 0 +OP4 E0077B 0 +OP4 E0077C 0 +OP4 E0077D 0 +OP4 E0077E 0 +OP4 E0077F 0 +OP4 E00780 0 +OP4 E00781 0 +OP4 E00782 0 +OP4 E00783 0 +OP4 E00784 0 +OP4 E00785 0 +OP4 E00786 0 +OP4 E00787 0 +OP4 E00788 0 +OP4 E00789 0 +OP4 E0078A 0 +OP4 E0078B 0 +OP4 E0078C 0 +OP4 E0078D 0 +OP4 E0078E 0 +OP4 E0078F 0 +OP4 E00790 0 +OP4 E00791 0 +OP4 E00792 0 +OP4 E00793 0 +OP4 E00794 0 +OP4 E00795 0 +OP4 E00796 0 +OP4 E00797 0 +OP4 E00798 0 +OP4 E00799 0 +OP4 E0079A 0 +OP4 E0079B 0 +OP4 E0079C 0 +OP4 E0079D 0 +OP4 E0079E 0 +OP4 E0079F 0 +OP4 E007A0 0 +OP4 E007A1 0 +OP4 E007A2 0 +OP4 E007A3 0 +OP4 E007A4 0 +OP4 E007A5 0 +OP4 E007A6 0 +OP4 E007A7 0 +OP4 E007A8 0 +OP4 E007A9 0 +OP4 E007AA 0 +OP4 E007AB 0 +OP4 E007AC 0 +OP4 E007AD 0 +OP4 E007AE 0 +OP4 E007AF 0 +OP4 E007B0 0 +OP4 E007B1 0 +OP4 E007B2 0 +OP4 E007B3 0 +OP4 E007B4 0 +OP4 E007B5 0 +OP4 E007B6 0 +OP4 E007B7 0 +OP4 E007B8 0 +OP4 E007B9 0 +OP4 E007BA 0 +OP4 E007BB 0 +OP4 E007BC 0 +OP4 E007BD 0 +OP4 E007BE 0 +OP4 E007BF 0 +OP4 E007C0 0 +OP4 E007C1 0 +OP4 E007C2 0 +OP4 E007C3 0 +OP4 E007C4 0 +OP4 E007C5 0 +OP4 E007C6 0 +OP4 E007C7 0 +OP4 E007C8 0 +OP4 E007C9 0 +OP4 E007CA 0 +OP4 E007CB 0 +OP4 E007CC 0 +OP4 E007CD 0 +OP4 E007CE 0 +OP4 E007CF 0 +OP4 E007D0 0 +OP4 E007D1 0 +OP4 E007D2 0 +OP4 E007D3 0 +OP4 E007D4 0 +OP4 E007D5 0 +OP4 E007D6 0 +OP4 E007D7 0 +OP4 E007D8 0 +OP4 E007D9 0 +OP4 E007DA 0 +OP4 E007DB 0 +OP4 E007DC 0 +OP4 E007DD 0 +OP4 E007DE 0 +OP4 E007DF 0 +OP4 E007E0 0 +OP4 E007E1 0 +OP4 E007E2 0 +OP4 E007E3 0 +OP4 E007E4 0 +OP4 E007E5 0 +OP4 E007E6 0 +OP4 E007E7 0 +OP4 E007E8 0 +OP4 E007E9 0 +OP4 E007EA 0 +OP4 E007EB 0 +OP4 E007EC 0 +OP4 E007ED 0 +OP4 E007EE 0 +OP4 E007EF 0 +OP4 E007F0 0 +OP4 E007F1 0 +OP4 E007F2 0 +OP4 E007F3 0 +OP4 E007F4 0 +OP4 E007F5 0 +OP4 E007F6 0 +OP4 E007F7 0 +OP4 E007F8 0 +OP4 E007F9 0 +OP4 E007FA 0 +OP4 E007FB 0 +OP4 E007FC 0 +OP4 E007FD 0 +OP4 E007FE 0 +OP4 E007FF 0 +OP4 E00800 0 +OP4 E00801 0 +OP4 E00802 0 +OP4 E00803 0 +OP4 E00804 0 +OP4 E00805 0 +OP4 E00806 0 +OP4 E00807 0 +OP4 E00808 0 +OP4 E00809 0 +OP4 E0080A 0 +OP4 E0080B 0 +OP4 E0080C 0 +OP4 E0080D 0 +OP4 E0080E 0 +OP4 E0080F 0 +OP4 E00810 0 +OP4 E00811 0 +OP4 E00812 0 +OP4 E00813 0 +OP4 E00814 0 +OP4 E00815 0 +OP4 E00816 0 +OP4 E00817 0 +OP4 E00818 0 +OP4 E00819 0 +OP4 E0081A 0 +OP4 E0081B 0 +OP4 E0081C 0 +OP4 E0081D 0 +OP4 E0081E 0 +OP4 E0081F 0 +OP4 E00820 0 +OP4 E00821 0 +OP4 E00822 0 +OP4 E00823 0 +OP4 E00824 0 +OP4 E00825 0 +OP4 E00826 0 +OP4 E00827 0 +OP4 E00828 0 +OP4 E00829 0 +OP4 E0082A 0 +OP4 E0082B 0 +OP4 E0082C 0 +OP4 E0082D 0 +OP4 E0082E 0 +OP4 E0082F 0 +OP4 E00830 0 +OP4 E00831 0 +OP4 E00832 0 +OP4 E00833 0 +OP4 E00834 0 +OP4 E00835 0 +OP4 E00836 0 +OP4 E00837 0 +OP4 E00838 0 +OP4 E00839 0 +OP4 E0083A 0 +OP4 E0083B 0 +OP4 E0083C 0 +OP4 E0083D 0 +OP4 E0083E 0 +OP4 E0083F 0 +OP4 E00840 0 +OP4 E00841 0 +OP4 E00842 0 +OP4 E00843 0 +OP4 E00844 0 +OP4 E00845 0 +OP4 E00846 0 +OP4 E00847 0 +OP4 E00848 0 +OP4 E00849 0 +OP4 E0084A 0 +OP4 E0084B 0 +OP4 E0084C 0 +OP4 E0084D 0 +OP4 E0084E 0 +OP4 E0084F 0 +OP4 E00850 0 +OP4 E00851 0 +OP4 E00852 0 +OP4 E00853 0 +OP4 E00854 0 +OP4 E00855 0 +OP4 E00856 0 +OP4 E00857 0 +OP4 E00858 0 +OP4 E00859 0 +OP4 E0085A 0 +OP4 E0085B 0 +OP4 E0085C 0 +OP4 E0085D 0 +OP4 E0085E 0 +OP4 E0085F 0 +OP4 E00860 0 +OP4 E00861 0 +OP4 E00862 0 +OP4 E00863 0 +OP4 E00864 0 +OP4 E00865 0 +OP4 E00866 0 +OP4 E00867 0 +OP4 E00868 0 +OP4 E00869 0 +OP4 E0086A 0 +OP4 E0086B 0 +OP4 E0086C 0 +OP4 E0086D 0 +OP4 E0086E 0 +OP4 E0086F 0 +OP4 E00870 0 +OP4 E00871 0 +OP4 E00872 0 +OP4 E00873 0 +OP4 E00874 0 +OP4 E00875 0 +OP4 E00876 0 +OP4 E00877 0 +OP4 E00878 0 +OP4 E00879 0 +OP4 E0087A 0 +OP4 E0087B 0 +OP4 E0087C 0 +OP4 E0087D 0 +OP4 E0087E 0 +OP4 E0087F 0 +OP4 E00880 0 +OP4 E00881 0 +OP4 E00882 0 +OP4 E00883 0 +OP4 E00884 0 +OP4 E00885 0 +OP4 E00886 0 +OP4 E00887 0 +OP4 E00888 0 +OP4 E00889 0 +OP4 E0088A 0 +OP4 E0088B 0 +OP4 E0088C 0 +OP4 E0088D 0 +OP4 E0088E 0 +OP4 E0088F 0 +OP4 E00890 0 +OP4 E00891 0 +OP4 E00892 0 +OP4 E00893 0 +OP4 E00894 0 +OP4 E00895 0 +OP4 E00896 0 +OP4 E00897 0 +OP4 E00898 0 +OP4 E00899 0 +OP4 E0089A 0 +OP4 E0089B 0 +OP4 E0089C 0 +OP4 E0089D 0 +OP4 E0089E 0 +OP4 E0089F 0 +OP4 E008A0 0 +OP4 E008A1 0 +OP4 E008A2 0 +OP4 E008A3 0 +OP4 E008A4 0 +OP4 E008A5 0 +OP4 E008A6 0 +OP4 E008A7 0 +OP4 E008A8 0 +OP4 E008A9 0 +OP4 E008AA 0 +OP4 E008AB 0 +OP4 E008AC 0 +OP4 E008AD 0 +OP4 E008AE 0 +OP4 E008AF 0 +OP4 E008B0 0 +OP4 E008B1 0 +OP4 E008B2 0 +OP4 E008B3 0 +OP4 E008B4 0 +OP4 E008B5 0 +OP4 E008B6 0 +OP4 E008B7 0 +OP4 E008B8 0 +OP4 E008B9 0 +OP4 E008BA 0 +OP4 E008BB 0 +OP4 E008BC 0 +OP4 E008BD 0 +OP4 E008BE 0 +OP4 E008BF 0 +OP4 E008C0 0 +OP4 E008C1 0 +OP4 E008C2 0 +OP4 E008C3 0 +OP4 E008C4 0 +OP4 E008C5 0 +OP4 E008C6 0 +OP4 E008C7 0 +OP4 E008C8 0 +OP4 E008C9 0 +OP4 E008CA 0 +OP4 E008CB 0 +OP4 E008CC 0 +OP4 E008CD 0 +OP4 E008CE 0 +OP4 E008CF 0 +OP4 E008D0 0 +OP4 E008D1 0 +OP4 E008D2 0 +OP4 E008D3 0 +OP4 E008D4 0 +OP4 E008D5 0 +OP4 E008D6 0 +OP4 E008D7 0 +OP4 E008D8 0 +OP4 E008D9 0 +OP4 E008DA 0 +OP4 E008DB 0 +OP4 E008DC 0 +OP4 E008DD 0 +OP4 E008DE 0 +OP4 E008DF 0 +OP4 E008E0 0 +OP4 E008E1 0 +OP4 E008E2 0 +OP4 E008E3 0 +OP4 E008E4 0 +OP4 E008E5 0 +OP4 E008E6 0 +OP4 E008E7 0 +OP4 E008E8 0 +OP4 E008E9 0 +OP4 E008EA 0 +OP4 E008EB 0 +OP4 E008EC 0 +OP4 E008ED 0 +OP4 E008EE 0 +OP4 E008EF 0 +OP4 E008F0 0 +OP4 E008F1 0 +OP4 E008F2 0 +OP4 E008F3 0 +OP4 E008F4 0 +OP4 E008F5 0 +OP4 E008F6 0 +OP4 E008F7 0 +OP4 E008F8 0 +OP4 E008F9 0 +OP4 E008FA 0 +OP4 E008FB 0 +OP4 E008FC 0 +OP4 E008FD 0 +OP4 E008FE 0 +OP4 E008FF 0 +OP4 E00900 0 +OP4 E00901 0 +OP4 E00902 0 +OP4 E00903 0 +OP4 E00904 0 +OP4 E00905 0 +OP4 E00906 0 +OP4 E00907 0 +OP4 E00908 0 +OP4 E00909 0 +OP4 E0090A 0 +OP4 E0090B 0 +OP4 E0090C 0 +OP4 E0090D 0 +OP4 E0090E 0 +OP4 E0090F 0 +OP4 E00910 0 +OP4 E00911 0 +OP4 E00912 0 +OP4 E00913 0 +OP4 E00914 0 +OP4 E00915 0 +OP4 E00916 0 +OP4 E00917 0 +OP4 E00918 0 +OP4 E00919 0 +OP4 E0091A 0 +OP4 E0091B 0 +OP4 E0091C 0 +OP4 E0091D 0 +OP4 E0091E 0 +OP4 E0091F 0 +OP4 E00920 0 +OP4 E00921 0 +OP4 E00922 0 +OP4 E00923 0 +OP4 E00924 0 +OP4 E00925 0 +OP4 E00926 0 +OP4 E00927 0 +OP4 E00928 0 +OP4 E00929 0 +OP4 E0092A 0 +OP4 E0092B 0 +OP4 E0092C 0 +OP4 E0092D 0 +OP4 E0092E 0 +OP4 E0092F 0 +OP4 E00930 0 +OP4 E00931 0 +OP4 E00932 0 +OP4 E00933 0 +OP4 E00934 0 +OP4 E00935 0 +OP4 E00936 0 +OP4 E00937 0 +OP4 E00938 0 +OP4 E00939 0 +OP4 E0093A 0 +OP4 E0093B 0 +OP4 E0093C 0 +OP4 E0093D 0 +OP4 E0093E 0 +OP4 E0093F 0 +OP4 E00940 0 +OP4 E00941 0 +OP4 E00942 0 +OP4 E00943 0 +OP4 E00944 0 +OP4 E00945 0 +OP4 E00946 0 +OP4 E00947 0 +OP4 E00948 0 +OP4 E00949 0 +OP4 E0094A 0 +OP4 E0094B 0 +OP4 E0094C 0 +OP4 E0094D 0 +OP4 E0094E 0 +OP4 E0094F 0 +OP4 E00950 0 +OP4 E00951 0 +OP4 E00952 0 +OP4 E00953 0 +OP4 E00954 0 +OP4 E00955 0 +OP4 E00956 0 +OP4 E00957 0 +OP4 E00958 0 +OP4 E00959 0 +OP4 E0095A 0 +OP4 E0095B 0 +OP4 E0095C 0 +OP4 E0095D 0 +OP4 E0095E 0 +OP4 E0095F 0 +OP4 E00960 0 +OP4 E00961 0 +OP4 E00962 0 +OP4 E00963 0 +OP4 E00964 0 +OP4 E00965 0 +OP4 E00966 0 +OP4 E00967 0 +OP4 E00968 0 +OP4 E00969 0 +OP4 E0096A 0 +OP4 E0096B 0 +OP4 E0096C 0 +OP4 E0096D 0 +OP4 E0096E 0 +OP4 E0096F 0 +OP4 E00970 0 +OP4 E00971 0 +OP4 E00972 0 +OP4 E00973 0 +OP4 E00974 0 +OP4 E00975 0 +OP4 E00976 0 +OP4 E00977 0 +OP4 E00978 0 +OP4 E00979 0 +OP4 E0097A 0 +OP4 E0097B 0 +OP4 E0097C 0 +OP4 E0097D 0 +OP4 E0097E 0 +OP4 E0097F 0 +OP4 E00980 0 +OP4 E00981 0 +OP4 E00982 0 +OP4 E00983 0 +OP4 E00984 0 +OP4 E00985 0 +OP4 E00986 0 +OP4 E00987 0 +OP4 E00988 0 +OP4 E00989 0 +OP4 E0098A 0 +OP4 E0098B 0 +OP4 E0098C 0 +OP4 E0098D 0 +OP4 E0098E 0 +OP4 E0098F 0 +OP4 E00990 0 +OP4 E00991 0 +OP4 E00992 0 +OP4 E00993 0 +OP4 E00994 0 +OP4 E00995 0 +OP4 E00996 0 +OP4 E00997 0 +OP4 E00998 0 +OP4 E00999 0 +OP4 E0099A 0 +OP4 E0099B 0 +OP4 E0099C 0 +OP4 E0099D 0 +OP4 E0099E 0 +OP4 E0099F 0 +OP4 E009A0 0 +OP4 E009A1 0 +OP4 E009A2 0 +OP4 E009A3 0 +OP4 E009A4 0 +OP4 E009A5 0 +OP4 E009A6 0 +OP4 E009A7 0 +OP4 E009A8 0 +OP4 E009A9 0 +OP4 E009AA 0 +OP4 E009AB 0 +OP4 E009AC 0 +OP4 E009AD 0 +OP4 E009AE 0 +OP4 E009AF 0 +OP4 E009B0 0 +OP4 E009B1 0 +OP4 E009B2 0 +OP4 E009B3 0 +OP4 E009B4 0 +OP4 E009B5 0 +OP4 E009B6 0 +OP4 E009B7 0 +OP4 E009B8 0 +OP4 E009B9 0 +OP4 E009BA 0 +OP4 E009BB 0 +OP4 E009BC 0 +OP4 E009BD 0 +OP4 E009BE 0 +OP4 E009BF 0 +OP4 E009C0 0 +OP4 E009C1 0 +OP4 E009C2 0 +OP4 E009C3 0 +OP4 E009C4 0 +OP4 E009C5 0 +OP4 E009C6 0 +OP4 E009C7 0 +OP4 E009C8 0 +OP4 E009C9 0 +OP4 E009CA 0 +OP4 E009CB 0 +OP4 E009CC 0 +OP4 E009CD 0 +OP4 E009CE 0 +OP4 E009CF 0 +OP4 E009D0 0 +OP4 E009D1 0 +OP4 E009D2 0 +OP4 E009D3 0 +OP4 E009D4 0 +OP4 E009D5 0 +OP4 E009D6 0 +OP4 E009D7 0 +OP4 E009D8 0 +OP4 E009D9 0 +OP4 E009DA 0 +OP4 E009DB 0 +OP4 E009DC 0 +OP4 E009DD 0 +OP4 E009DE 0 +OP4 E009DF 0 +OP4 E009E0 0 +OP4 E009E1 0 +OP4 E009E2 0 +OP4 E009E3 0 +OP4 E009E4 0 +OP4 E009E5 0 +OP4 E009E6 0 +OP4 E009E7 0 +OP4 E009E8 0 +OP4 E009E9 0 +OP4 E009EA 0 +OP4 E009EB 0 +OP4 E009EC 0 +OP4 E009ED 0 +OP4 E009EE 0 +OP4 E009EF 0 +OP4 E009F0 0 +OP4 E009F1 0 +OP4 E009F2 0 +OP4 E009F3 0 +OP4 E009F4 0 +OP4 E009F5 0 +OP4 E009F6 0 +OP4 E009F7 0 +OP4 E009F8 0 +OP4 E009F9 0 +OP4 E009FA 0 +OP4 E009FB 0 +OP4 E009FC 0 +OP4 E009FD 0 +OP4 E009FE 0 +OP4 E009FF 0 +OP4 E00A00 0 +OP4 E00A01 0 +OP4 E00A02 0 +OP4 E00A03 0 +OP4 E00A04 0 +OP4 E00A05 0 +OP4 E00A06 0 +OP4 E00A07 0 +OP4 E00A08 0 +OP4 E00A09 0 +OP4 E00A0A 0 +OP4 E00A0B 0 +OP4 E00A0C 0 +OP4 E00A0D 0 +OP4 E00A0E 0 +OP4 E00A0F 0 +OP4 E00A10 0 +OP4 E00A11 0 +OP4 E00A12 0 +OP4 E00A13 0 +OP4 E00A14 0 +OP4 E00A15 0 +OP4 E00A16 0 +OP4 E00A17 0 +OP4 E00A18 0 +OP4 E00A19 0 +OP4 E00A1A 0 +OP4 E00A1B 0 +OP4 E00A1C 0 +OP4 E00A1D 0 +OP4 E00A1E 0 +OP4 E00A1F 0 +OP4 E00A20 0 +OP4 E00A21 0 +OP4 E00A22 0 +OP4 E00A23 0 +OP4 E00A24 0 +OP4 E00A25 0 +OP4 E00A26 0 +OP4 E00A27 0 +OP4 E00A28 0 +OP4 E00A29 0 +OP4 E00A2A 0 +OP4 E00A2B 0 +OP4 E00A2C 0 +OP4 E00A2D 0 +OP4 E00A2E 0 +OP4 E00A2F 0 +OP4 E00A30 0 +OP4 E00A31 0 +OP4 E00A32 0 +OP4 E00A33 0 +OP4 E00A34 0 +OP4 E00A35 0 +OP4 E00A36 0 +OP4 E00A37 0 +OP4 E00A38 0 +OP4 E00A39 0 +OP4 E00A3A 0 +OP4 E00A3B 0 +OP4 E00A3C 0 +OP4 E00A3D 0 +OP4 E00A3E 0 +OP4 E00A3F 0 +OP4 E00A40 0 +OP4 E00A41 0 +OP4 E00A42 0 +OP4 E00A43 0 +OP4 E00A44 0 +OP4 E00A45 0 +OP4 E00A46 0 +OP4 E00A47 0 +OP4 E00A48 0 +OP4 E00A49 0 +OP4 E00A4A 0 +OP4 E00A4B 0 +OP4 E00A4C 0 +OP4 E00A4D 0 +OP4 E00A4E 0 +OP4 E00A4F 0 +OP4 E00A50 0 +OP4 E00A51 0 +OP4 E00A52 0 +OP4 E00A53 0 +OP4 E00A54 0 +OP4 E00A55 0 +OP4 E00A56 0 +OP4 E00A57 0 +OP4 E00A58 0 +OP4 E00A59 0 +OP4 E00A5A 0 +OP4 E00A5B 0 +OP4 E00A5C 0 +OP4 E00A5D 0 +OP4 E00A5E 0 +OP4 E00A5F 0 +OP4 E00A60 0 +OP4 E00A61 0 +OP4 E00A62 0 +OP4 E00A63 0 +OP4 E00A64 0 +OP4 E00A65 0 +OP4 E00A66 0 +OP4 E00A67 0 +OP4 E00A68 0 +OP4 E00A69 0 +OP4 E00A6A 0 +OP4 E00A6B 0 +OP4 E00A6C 0 +OP4 E00A6D 0 +OP4 E00A6E 0 +OP4 E00A6F 0 +OP4 E00A70 0 +OP4 E00A71 0 +OP4 E00A72 0 +OP4 E00A73 0 +OP4 E00A74 0 +OP4 E00A75 0 +OP4 E00A76 0 +OP4 E00A77 0 +OP4 E00A78 0 +OP4 E00A79 0 +OP4 E00A7A 0 +OP4 E00A7B 0 +OP4 E00A7C 0 +OP4 E00A7D 0 +OP4 E00A7E 0 +OP4 E00A7F 0 +OP4 E00A80 0 +OP4 E00A81 0 +OP4 E00A82 0 +OP4 E00A83 0 +OP4 E00A84 0 +OP4 E00A85 0 +OP4 E00A86 0 +OP4 E00A87 0 +OP4 E00A88 0 +OP4 E00A89 0 +OP4 E00A8A 0 +OP4 E00A8B 0 +OP4 E00A8C 0 +OP4 E00A8D 0 +OP4 E00A8E 0 +OP4 E00A8F 0 +OP4 E00A90 0 +OP4 E00A91 0 +OP4 E00A92 0 +OP4 E00A93 0 +OP4 E00A94 0 +OP4 E00A95 0 +OP4 E00A96 0 +OP4 E00A97 0 +OP4 E00A98 0 +OP4 E00A99 0 +OP4 E00A9A 0 +OP4 E00A9B 0 +OP4 E00A9C 0 +OP4 E00A9D 0 +OP4 E00A9E 0 +OP4 E00A9F 0 +OP4 E00AA0 0 +OP4 E00AA1 0 +OP4 E00AA2 0 +OP4 E00AA3 0 +OP4 E00AA4 0 +OP4 E00AA5 0 +OP4 E00AA6 0 +OP4 E00AA7 0 +OP4 E00AA8 0 +OP4 E00AA9 0 +OP4 E00AAA 0 +OP4 E00AAB 0 +OP4 E00AAC 0 +OP4 E00AAD 0 +OP4 E00AAE 0 +OP4 E00AAF 0 +OP4 E00AB0 0 +OP4 E00AB1 0 +OP4 E00AB2 0 +OP4 E00AB3 0 +OP4 E00AB4 0 +OP4 E00AB5 0 +OP4 E00AB6 0 +OP4 E00AB7 0 +OP4 E00AB8 0 +OP4 E00AB9 0 +OP4 E00ABA 0 +OP4 E00ABB 0 +OP4 E00ABC 0 +OP4 E00ABD 0 +OP4 E00ABE 0 +OP4 E00ABF 0 +OP4 E00AC0 0 +OP4 E00AC1 0 +OP4 E00AC2 0 +OP4 E00AC3 0 +OP4 E00AC4 0 +OP4 E00AC5 0 +OP4 E00AC6 0 +OP4 E00AC7 0 +OP4 E00AC8 0 +OP4 E00AC9 0 +OP4 E00ACA 0 +OP4 E00ACB 0 +OP4 E00ACC 0 +OP4 E00ACD 0 +OP4 E00ACE 0 +OP4 E00ACF 0 +OP4 E00AD0 0 +OP4 E00AD1 0 +OP4 E00AD2 0 +OP4 E00AD3 0 +OP4 E00AD4 0 +OP4 E00AD5 0 +OP4 E00AD6 0 +OP4 E00AD7 0 +OP4 E00AD8 0 +OP4 E00AD9 0 +OP4 E00ADA 0 +OP4 E00ADB 0 +OP4 E00ADC 0 +OP4 E00ADD 0 +OP4 E00ADE 0 +OP4 E00ADF 0 +OP4 E00AE0 0 +OP4 E00AE1 0 +OP4 E00AE2 0 +OP4 E00AE3 0 +OP4 E00AE4 0 +OP4 E00AE5 0 +OP4 E00AE6 0 +OP4 E00AE7 0 +OP4 E00AE8 0 +OP4 E00AE9 0 +OP4 E00AEA 0 +OP4 E00AEB 0 +OP4 E00AEC 0 +OP4 E00AED 0 +OP4 E00AEE 0 +OP4 E00AEF 0 +OP4 E00AF0 0 +OP4 E00AF1 0 +OP4 E00AF2 0 +OP4 E00AF3 0 +OP4 E00AF4 0 +OP4 E00AF5 0 +OP4 E00AF6 0 +OP4 E00AF7 0 +OP4 E00AF8 0 +OP4 E00AF9 0 +OP4 E00AFA 0 +OP4 E00AFB 0 +OP4 E00AFC 0 +OP4 E00AFD 0 +OP4 E00AFE 0 +OP4 E00AFF 0 +OP4 E00B00 0 +OP4 E00B01 0 +OP4 E00B02 0 +OP4 E00B03 0 +OP4 E00B04 0 +OP4 E00B05 0 +OP4 E00B06 0 +OP4 E00B07 0 +OP4 E00B08 0 +OP4 E00B09 0 +OP4 E00B0A 0 +OP4 E00B0B 0 +OP4 E00B0C 0 +OP4 E00B0D 0 +OP4 E00B0E 0 +OP4 E00B0F 0 +OP4 E00B10 0 +OP4 E00B11 0 +OP4 E00B12 0 +OP4 E00B13 0 +OP4 E00B14 0 +OP4 E00B15 0 +OP4 E00B16 0 +OP4 E00B17 0 +OP4 E00B18 0 +OP4 E00B19 0 +OP4 E00B1A 0 +OP4 E00B1B 0 +OP4 E00B1C 0 +OP4 E00B1D 0 +OP4 E00B1E 0 +OP4 E00B1F 0 +OP4 E00B20 0 +OP4 E00B21 0 +OP4 E00B22 0 +OP4 E00B23 0 +OP4 E00B24 0 +OP4 E00B25 0 +OP4 E00B26 0 +OP4 E00B27 0 +OP4 E00B28 0 +OP4 E00B29 0 +OP4 E00B2A 0 +OP4 E00B2B 0 +OP4 E00B2C 0 +OP4 E00B2D 0 +OP4 E00B2E 0 +OP4 E00B2F 0 +OP4 E00B30 0 +OP4 E00B31 0 +OP4 E00B32 0 +OP4 E00B33 0 +OP4 E00B34 0 +OP4 E00B35 0 +OP4 E00B36 0 +OP4 E00B37 0 +OP4 E00B38 0 +OP4 E00B39 0 +OP4 E00B3A 0 +OP4 E00B3B 0 +OP4 E00B3C 0 +OP4 E00B3D 0 +OP4 E00B3E 0 +OP4 E00B3F 0 +OP4 E00B40 0 +OP4 E00B41 0 +OP4 E00B42 0 +OP4 E00B43 0 +OP4 E00B44 0 +OP4 E00B45 0 +OP4 E00B46 0 +OP4 E00B47 0 +OP4 E00B48 0 +OP4 E00B49 0 +OP4 E00B4A 0 +OP4 E00B4B 0 +OP4 E00B4C 0 +OP4 E00B4D 0 +OP4 E00B4E 0 +OP4 E00B4F 0 +OP4 E00B50 0 +OP4 E00B51 0 +OP4 E00B52 0 +OP4 E00B53 0 +OP4 E00B54 0 +OP4 E00B55 0 +OP4 E00B56 0 +OP4 E00B57 0 +OP4 E00B58 0 +OP4 E00B59 0 +OP4 E00B5A 0 +OP4 E00B5B 0 +OP4 E00B5C 0 +OP4 E00B5D 0 +OP4 E00B5E 0 +OP4 E00B5F 0 +OP4 E00B60 0 +OP4 E00B61 0 +OP4 E00B62 0 +OP4 E00B63 0 +OP4 E00B64 0 +OP4 E00B65 0 +OP4 E00B66 0 +OP4 E00B67 0 +OP4 E00B68 0 +OP4 E00B69 0 +OP4 E00B6A 0 +OP4 E00B6B 0 +OP4 E00B6C 0 +OP4 E00B6D 0 +OP4 E00B6E 0 +OP4 E00B6F 0 +OP4 E00B70 0 +OP4 E00B71 0 +OP4 E00B72 0 +OP4 E00B73 0 +OP4 E00B74 0 +OP4 E00B75 0 +OP4 E00B76 0 +OP4 E00B77 0 +OP4 E00B78 0 +OP4 E00B79 0 +OP4 E00B7A 0 +OP4 E00B7B 0 +OP4 E00B7C 0 +OP4 E00B7D 0 +OP4 E00B7E 0 +OP4 E00B7F 0 +OP4 E00B80 0 +OP4 E00B81 0 +OP4 E00B82 0 +OP4 E00B83 0 +OP4 E00B84 0 +OP4 E00B85 0 +OP4 E00B86 0 +OP4 E00B87 0 +OP4 E00B88 0 +OP4 E00B89 0 +OP4 E00B8A 0 +OP4 E00B8B 0 +OP4 E00B8C 0 +OP4 E00B8D 0 +OP4 E00B8E 0 +OP4 E00B8F 0 +OP4 E00B90 0 +OP4 E00B91 0 +OP4 E00B92 0 +OP4 E00B93 0 +OP4 E00B94 0 +OP4 E00B95 0 +OP4 E00B96 0 +OP4 E00B97 0 +OP4 E00B98 0 +OP4 E00B99 0 +OP4 E00B9A 0 +OP4 E00B9B 0 +OP4 E00B9C 0 +OP4 E00B9D 0 +OP4 E00B9E 0 +OP4 E00B9F 0 +OP4 E00BA0 0 +OP4 E00BA1 0 +OP4 E00BA2 0 +OP4 E00BA3 0 +OP4 E00BA4 0 +OP4 E00BA5 0 +OP4 E00BA6 0 +OP4 E00BA7 0 +OP4 E00BA8 0 +OP4 E00BA9 0 +OP4 E00BAA 0 +OP4 E00BAB 0 +OP4 E00BAC 0 +OP4 E00BAD 0 +OP4 E00BAE 0 +OP4 E00BAF 0 +OP4 E00BB0 0 +OP4 E00BB1 0 +OP4 E00BB2 0 +OP4 E00BB3 0 +OP4 E00BB4 0 +OP4 E00BB5 0 +OP4 E00BB6 0 +OP4 E00BB7 0 +OP4 E00BB8 0 +OP4 E00BB9 0 +OP4 E00BBA 0 +OP4 E00BBB 0 +OP4 E00BBC 0 +OP4 E00BBD 0 +OP4 E00BBE 0 +OP4 E00BBF 0 +OP4 E00BC0 0 +OP4 E00BC1 0 +OP4 E00BC2 0 +OP4 E00BC3 0 +OP4 E00BC4 0 +OP4 E00BC5 0 +OP4 E00BC6 0 +OP4 E00BC7 0 +OP4 E00BC8 0 +OP4 E00BC9 0 +OP4 E00BCA 0 +OP4 E00BCB 0 +OP4 E00BCC 0 +OP4 E00BCD 0 +OP4 E00BCE 0 +OP4 E00BCF 0 +OP4 E00BD0 0 +OP4 E00BD1 0 +OP4 E00BD2 0 +OP4 E00BD3 0 +OP4 E00BD4 0 +OP4 E00BD5 0 +OP4 E00BD6 0 +OP4 E00BD7 0 +OP4 E00BD8 0 +OP4 E00BD9 0 +OP4 E00BDA 0 +OP4 E00BDB 0 +OP4 E00BDC 0 +OP4 E00BDD 0 +OP4 E00BDE 0 +OP4 E00BDF 0 +OP4 E00BE0 0 +OP4 E00BE1 0 +OP4 E00BE2 0 +OP4 E00BE3 0 +OP4 E00BE4 0 +OP4 E00BE5 0 +OP4 E00BE6 0 +OP4 E00BE7 0 +OP4 E00BE8 0 +OP4 E00BE9 0 +OP4 E00BEA 0 +OP4 E00BEB 0 +OP4 E00BEC 0 +OP4 E00BED 0 +OP4 E00BEE 0 +OP4 E00BEF 0 +OP4 E00BF0 0 +OP4 E00BF1 0 +OP4 E00BF2 0 +OP4 E00BF3 0 +OP4 E00BF4 0 +OP4 E00BF5 0 +OP4 E00BF6 0 +OP4 E00BF7 0 +OP4 E00BF8 0 +OP4 E00BF9 0 +OP4 E00BFA 0 +OP4 E00BFB 0 +OP4 E00BFC 0 +OP4 E00BFD 0 +OP4 E00BFE 0 +OP4 E00BFF 0 +OP4 E00C00 0 +OP4 E00C01 0 +OP4 E00C02 0 +OP4 E00C03 0 +OP4 E00C04 0 +OP4 E00C05 0 +OP4 E00C06 0 +OP4 E00C07 0 +OP4 E00C08 0 +OP4 E00C09 0 +OP4 E00C0A 0 +OP4 E00C0B 0 +OP4 E00C0C 0 +OP4 E00C0D 0 +OP4 E00C0E 0 +OP4 E00C0F 0 +OP4 E00C10 0 +OP4 E00C11 0 +OP4 E00C12 0 +OP4 E00C13 0 +OP4 E00C14 0 +OP4 E00C15 0 +OP4 E00C16 0 +OP4 E00C17 0 +OP4 E00C18 0 +OP4 E00C19 0 +OP4 E00C1A 0 +OP4 E00C1B 0 +OP4 E00C1C 0 +OP4 E00C1D 0 +OP4 E00C1E 0 +OP4 E00C1F 0 +OP4 E00C20 0 +OP4 E00C21 0 +OP4 E00C22 0 +OP4 E00C23 0 +OP4 E00C24 0 +OP4 E00C25 0 +OP4 E00C26 0 +OP4 E00C27 0 +OP4 E00C28 0 +OP4 E00C29 0 +OP4 E00C2A 0 +OP4 E00C2B 0 +OP4 E00C2C 0 +OP4 E00C2D 0 +OP4 E00C2E 0 +OP4 E00C2F 0 +OP4 E00C30 0 +OP4 E00C31 0 +OP4 E00C32 0 +OP4 E00C33 0 +OP4 E00C34 0 +OP4 E00C35 0 +OP4 E00C36 0 +OP4 E00C37 0 +OP4 E00C38 0 +OP4 E00C39 0 +OP4 E00C3A 0 +OP4 E00C3B 0 +OP4 E00C3C 0 +OP4 E00C3D 0 +OP4 E00C3E 0 +OP4 E00C3F 0 +OP4 E00C40 0 +OP4 E00C41 0 +OP4 E00C42 0 +OP4 E00C43 0 +OP4 E00C44 0 +OP4 E00C45 0 +OP4 E00C46 0 +OP4 E00C47 0 +OP4 E00C48 0 +OP4 E00C49 0 +OP4 E00C4A 0 +OP4 E00C4B 0 +OP4 E00C4C 0 +OP4 E00C4D 0 +OP4 E00C4E 0 +OP4 E00C4F 0 +OP4 E00C50 0 +OP4 E00C51 0 +OP4 E00C52 0 +OP4 E00C53 0 +OP4 E00C54 0 +OP4 E00C55 0 +OP4 E00C56 0 +OP4 E00C57 0 +OP4 E00C58 0 +OP4 E00C59 0 +OP4 E00C5A 0 +OP4 E00C5B 0 +OP4 E00C5C 0 +OP4 E00C5D 0 +OP4 E00C5E 0 +OP4 E00C5F 0 +OP4 E00C60 0 +OP4 E00C61 0 +OP4 E00C62 0 +OP4 E00C63 0 +OP4 E00C64 0 +OP4 E00C65 0 +OP4 E00C66 0 +OP4 E00C67 0 +OP4 E00C68 0 +OP4 E00C69 0 +OP4 E00C6A 0 +OP4 E00C6B 0 +OP4 E00C6C 0 +OP4 E00C6D 0 +OP4 E00C6E 0 +OP4 E00C6F 0 +OP4 E00C70 0 +OP4 E00C71 0 +OP4 E00C72 0 +OP4 E00C73 0 +OP4 E00C74 0 +OP4 E00C75 0 +OP4 E00C76 0 +OP4 E00C77 0 +OP4 E00C78 0 +OP4 E00C79 0 +OP4 E00C7A 0 +OP4 E00C7B 0 +OP4 E00C7C 0 +OP4 E00C7D 0 +OP4 E00C7E 0 +OP4 E00C7F 0 +OP4 E00C80 0 +OP4 E00C81 0 +OP4 E00C82 0 +OP4 E00C83 0 +OP4 E00C84 0 +OP4 E00C85 0 +OP4 E00C86 0 +OP4 E00C87 0 +OP4 E00C88 0 +OP4 E00C89 0 +OP4 E00C8A 0 +OP4 E00C8B 0 +OP4 E00C8C 0 +OP4 E00C8D 0 +OP4 E00C8E 0 +OP4 E00C8F 0 +OP4 E00C90 0 +OP4 E00C91 0 +OP4 E00C92 0 +OP4 E00C93 0 +OP4 E00C94 0 +OP4 E00C95 0 +OP4 E00C96 0 +OP4 E00C97 0 +OP4 E00C98 0 +OP4 E00C99 0 +OP4 E00C9A 0 +OP4 E00C9B 0 +OP4 E00C9C 0 +OP4 E00C9D 0 +OP4 E00C9E 0 +OP4 E00C9F 0 +OP4 E00CA0 0 +OP4 E00CA1 0 +OP4 E00CA2 0 +OP4 E00CA3 0 +OP4 E00CA4 0 +OP4 E00CA5 0 +OP4 E00CA6 0 +OP4 E00CA7 0 +OP4 E00CA8 0 +OP4 E00CA9 0 +OP4 E00CAA 0 +OP4 E00CAB 0 +OP4 E00CAC 0 +OP4 E00CAD 0 +OP4 E00CAE 0 +OP4 E00CAF 0 +OP4 E00CB0 0 +OP4 E00CB1 0 +OP4 E00CB2 0 +OP4 E00CB3 0 +OP4 E00CB4 0 +OP4 E00CB5 0 +OP4 E00CB6 0 +OP4 E00CB7 0 +OP4 E00CB8 0 +OP4 E00CB9 0 +OP4 E00CBA 0 +OP4 E00CBB 0 +OP4 E00CBC 0 +OP4 E00CBD 0 +OP4 E00CBE 0 +OP4 E00CBF 0 +OP4 E00CC0 0 +OP4 E00CC1 0 +OP4 E00CC2 0 +OP4 E00CC3 0 +OP4 E00CC4 0 +OP4 E00CC5 0 +OP4 E00CC6 0 +OP4 E00CC7 0 +OP4 E00CC8 0 +OP4 E00CC9 0 +OP4 E00CCA 0 +OP4 E00CCB 0 +OP4 E00CCC 0 +OP4 E00CCD 0 +OP4 E00CCE 0 +OP4 E00CCF 0 +OP4 E00CD0 0 +OP4 E00CD1 0 +OP4 E00CD2 0 +OP4 E00CD3 0 +OP4 E00CD4 0 +OP4 E00CD5 0 +OP4 E00CD6 0 +OP4 E00CD7 0 +OP4 E00CD8 0 +OP4 E00CD9 0 +OP4 E00CDA 0 +OP4 E00CDB 0 +OP4 E00CDC 0 +OP4 E00CDD 0 +OP4 E00CDE 0 +OP4 E00CDF 0 +OP4 E00CE0 0 +OP4 E00CE1 0 +OP4 E00CE2 0 +OP4 E00CE3 0 +OP4 E00CE4 0 +OP4 E00CE5 0 +OP4 E00CE6 0 +OP4 E00CE7 0 +OP4 E00CE8 0 +OP4 E00CE9 0 +OP4 E00CEA 0 +OP4 E00CEB 0 +OP4 E00CEC 0 +OP4 E00CED 0 +OP4 E00CEE 0 +OP4 E00CEF 0 +OP4 E00CF0 0 +OP4 E00CF1 0 +OP4 E00CF2 0 +OP4 E00CF3 0 +OP4 E00CF4 0 +OP4 E00CF5 0 +OP4 E00CF6 0 +OP4 E00CF7 0 +OP4 E00CF8 0 +OP4 E00CF9 0 +OP4 E00CFA 0 +OP4 E00CFB 0 +OP4 E00CFC 0 +OP4 E00CFD 0 +OP4 E00CFE 0 +OP4 E00CFF 0 +OP4 E00D00 0 +OP4 E00D01 0 +OP4 E00D02 0 +OP4 E00D03 0 +OP4 E00D04 0 +OP4 E00D05 0 +OP4 E00D06 0 +OP4 E00D07 0 +OP4 E00D08 0 +OP4 E00D09 0 +OP4 E00D0A 0 +OP4 E00D0B 0 +OP4 E00D0C 0 +OP4 E00D0D 0 +OP4 E00D0E 0 +OP4 E00D0F 0 +OP4 E00D10 0 +OP4 E00D11 0 +OP4 E00D12 0 +OP4 E00D13 0 +OP4 E00D14 0 +OP4 E00D15 0 +OP4 E00D16 0 +OP4 E00D17 0 +OP4 E00D18 0 +OP4 E00D19 0 +OP4 E00D1A 0 +OP4 E00D1B 0 +OP4 E00D1C 0 +OP4 E00D1D 0 +OP4 E00D1E 0 +OP4 E00D1F 0 +OP4 E00D20 0 +OP4 E00D21 0 +OP4 E00D22 0 +OP4 E00D23 0 +OP4 E00D24 0 +OP4 E00D25 0 +OP4 E00D26 0 +OP4 E00D27 0 +OP4 E00D28 0 +OP4 E00D29 0 +OP4 E00D2A 0 +OP4 E00D2B 0 +OP4 E00D2C 0 +OP4 E00D2D 0 +OP4 E00D2E 0 +OP4 E00D2F 0 +OP4 E00D30 0 +OP4 E00D31 0 +OP4 E00D32 0 +OP4 E00D33 0 +OP4 E00D34 0 +OP4 E00D35 0 +OP4 E00D36 0 +OP4 E00D37 0 +OP4 E00D38 0 +OP4 E00D39 0 +OP4 E00D3A 0 +OP4 E00D3B 0 +OP4 E00D3C 0 +OP4 E00D3D 0 +OP4 E00D3E 0 +OP4 E00D3F 0 +OP4 E00D40 0 +OP4 E00D41 0 +OP4 E00D42 0 +OP4 E00D43 0 +OP4 E00D44 0 +OP4 E00D45 0 +OP4 E00D46 0 +OP4 E00D47 0 +OP4 E00D48 0 +OP4 E00D49 0 +OP4 E00D4A 0 +OP4 E00D4B 0 +OP4 E00D4C 0 +OP4 E00D4D 0 +OP4 E00D4E 0 +OP4 E00D4F 0 +OP4 E00D50 0 +OP4 E00D51 0 +OP4 E00D52 0 +OP4 E00D53 0 +OP4 E00D54 0 +OP4 E00D55 0 +OP4 E00D56 0 +OP4 E00D57 0 +OP4 E00D58 0 +OP4 E00D59 0 +OP4 E00D5A 0 +OP4 E00D5B 0 +OP4 E00D5C 0 +OP4 E00D5D 0 +OP4 E00D5E 0 +OP4 E00D5F 0 +OP4 E00D60 0 +OP4 E00D61 0 +OP4 E00D62 0 +OP4 E00D63 0 +OP4 E00D64 0 +OP4 E00D65 0 +OP4 E00D66 0 +OP4 E00D67 0 +OP4 E00D68 0 +OP4 E00D69 0 +OP4 E00D6A 0 +OP4 E00D6B 0 +OP4 E00D6C 0 +OP4 E00D6D 0 +OP4 E00D6E 0 +OP4 E00D6F 0 +OP4 E00D70 0 +OP4 E00D71 0 +OP4 E00D72 0 +OP4 E00D73 0 +OP4 E00D74 0 +OP4 E00D75 0 +OP4 E00D76 0 +OP4 E00D77 0 +OP4 E00D78 0 +OP4 E00D79 0 +OP4 E00D7A 0 +OP4 E00D7B 0 +OP4 E00D7C 0 +OP4 E00D7D 0 +OP4 E00D7E 0 +OP4 E00D7F 0 +OP4 E00D80 0 +OP4 E00D81 0 +OP4 E00D82 0 +OP4 E00D83 0 +OP4 E00D84 0 +OP4 E00D85 0 +OP4 E00D86 0 +OP4 E00D87 0 +OP4 E00D88 0 +OP4 E00D89 0 +OP4 E00D8A 0 +OP4 E00D8B 0 +OP4 E00D8C 0 +OP4 E00D8D 0 +OP4 E00D8E 0 +OP4 E00D8F 0 +OP4 E00D90 0 +OP4 E00D91 0 +OP4 E00D92 0 +OP4 E00D93 0 +OP4 E00D94 0 +OP4 E00D95 0 +OP4 E00D96 0 +OP4 E00D97 0 +OP4 E00D98 0 +OP4 E00D99 0 +OP4 E00D9A 0 +OP4 E00D9B 0 +OP4 E00D9C 0 +OP4 E00D9D 0 +OP4 E00D9E 0 +OP4 E00D9F 0 +OP4 E00DA0 0 +OP4 E00DA1 0 +OP4 E00DA2 0 +OP4 E00DA3 0 +OP4 E00DA4 0 +OP4 E00DA5 0 +OP4 E00DA6 0 +OP4 E00DA7 0 +OP4 E00DA8 0 +OP4 E00DA9 0 +OP4 E00DAA 0 +OP4 E00DAB 0 +OP4 E00DAC 0 +OP4 E00DAD 0 +OP4 E00DAE 0 +OP4 E00DAF 0 +OP4 E00DB0 0 +OP4 E00DB1 0 +OP4 E00DB2 0 +OP4 E00DB3 0 +OP4 E00DB4 0 +OP4 E00DB5 0 +OP4 E00DB6 0 +OP4 E00DB7 0 +OP4 E00DB8 0 +OP4 E00DB9 0 +OP4 E00DBA 0 +OP4 E00DBB 0 +OP4 E00DBC 0 +OP4 E00DBD 0 +OP4 E00DBE 0 +OP4 E00DBF 0 +OP4 E00DC0 0 +OP4 E00DC1 0 +OP4 E00DC2 0 +OP4 E00DC3 0 +OP4 E00DC4 0 +OP4 E00DC5 0 +OP4 E00DC6 0 +OP4 E00DC7 0 +OP4 E00DC8 0 +OP4 E00DC9 0 +OP4 E00DCA 0 +OP4 E00DCB 0 +OP4 E00DCC 0 +OP4 E00DCD 0 +OP4 E00DCE 0 +OP4 E00DCF 0 +OP4 E00DD0 0 +OP4 E00DD1 0 +OP4 E00DD2 0 +OP4 E00DD3 0 +OP4 E00DD4 0 +OP4 E00DD5 0 +OP4 E00DD6 0 +OP4 E00DD7 0 +OP4 E00DD8 0 +OP4 E00DD9 0 +OP4 E00DDA 0 +OP4 E00DDB 0 +OP4 E00DDC 0 +OP4 E00DDD 0 +OP4 E00DDE 0 +OP4 E00DDF 0 +OP4 E00DE0 0 +OP4 E00DE1 0 +OP4 E00DE2 0 +OP4 E00DE3 0 +OP4 E00DE4 0 +OP4 E00DE5 0 +OP4 E00DE6 0 +OP4 E00DE7 0 +OP4 E00DE8 0 +OP4 E00DE9 0 +OP4 E00DEA 0 +OP4 E00DEB 0 +OP4 E00DEC 0 +OP4 E00DED 0 +OP4 E00DEE 0 +OP4 E00DEF 0 +OP4 E00DF0 0 +OP4 E00DF1 0 +OP4 E00DF2 0 +OP4 E00DF3 0 +OP4 E00DF4 0 +OP4 E00DF5 0 +OP4 E00DF6 0 +OP4 E00DF7 0 +OP4 E00DF8 0 +OP4 E00DF9 0 +OP4 E00DFA 0 +OP4 E00DFB 0 +OP4 E00DFC 0 +OP4 E00DFD 0 +OP4 E00DFE 0 +OP4 E00DFF 0 +OP4 E00E00 0 +OP4 E00E01 0 +OP4 E00E02 0 +OP4 E00E03 0 +OP4 E00E04 0 +OP4 E00E05 0 +OP4 E00E06 0 +OP4 E00E07 0 +OP4 E00E08 0 +OP4 E00E09 0 +OP4 E00E0A 0 +OP4 E00E0B 0 +OP4 E00E0C 0 +OP4 E00E0D 0 +OP4 E00E0E 0 +OP4 E00E0F 0 +OP4 E00E10 0 +OP4 E00E11 0 +OP4 E00E12 0 +OP4 E00E13 0 +OP4 E00E14 0 +OP4 E00E15 0 +OP4 E00E16 0 +OP4 E00E17 0 +OP4 E00E18 0 +OP4 E00E19 0 +OP4 E00E1A 0 +OP4 E00E1B 0 +OP4 E00E1C 0 +OP4 E00E1D 0 +OP4 E00E1E 0 +OP4 E00E1F 0 +OP4 E00E20 0 +OP4 E00E21 0 +OP4 E00E22 0 +OP4 E00E23 0 +OP4 E00E24 0 +OP4 E00E25 0 +OP4 E00E26 0 +OP4 E00E27 0 +OP4 E00E28 0 +OP4 E00E29 0 +OP4 E00E2A 0 +OP4 E00E2B 0 +OP4 E00E2C 0 +OP4 E00E2D 0 +OP4 E00E2E 0 +OP4 E00E2F 0 +OP4 E00E30 0 +OP4 E00E31 0 +OP4 E00E32 0 +OP4 E00E33 0 +OP4 E00E34 0 +OP4 E00E35 0 +OP4 E00E36 0 +OP4 E00E37 0 +OP4 E00E38 0 +OP4 E00E39 0 +OP4 E00E3A 0 +OP4 E00E3B 0 +OP4 E00E3C 0 +OP4 E00E3D 0 +OP4 E00E3E 0 +OP4 E00E3F 0 +OP4 E00E40 0 +OP4 E00E41 0 +OP4 E00E42 0 +OP4 E00E43 0 +OP4 E00E44 0 +OP4 E00E45 0 +OP4 E00E46 0 +OP4 E00E47 0 +OP4 E00E48 0 +OP4 E00E49 0 +OP4 E00E4A 0 +OP4 E00E4B 0 +OP4 E00E4C 0 +OP4 E00E4D 0 +OP4 E00E4E 0 +OP4 E00E4F 0 +OP4 E00E50 0 +OP4 E00E51 0 +OP4 E00E52 0 +OP4 E00E53 0 +OP4 E00E54 0 +OP4 E00E55 0 +OP4 E00E56 0 +OP4 E00E57 0 +OP4 E00E58 0 +OP4 E00E59 0 +OP4 E00E5A 0 +OP4 E00E5B 0 +OP4 E00E5C 0 +OP4 E00E5D 0 +OP4 E00E5E 0 +OP4 E00E5F 0 +OP4 E00E60 0 +OP4 E00E61 0 +OP4 E00E62 0 +OP4 E00E63 0 +OP4 E00E64 0 +OP4 E00E65 0 +OP4 E00E66 0 +OP4 E00E67 0 +OP4 E00E68 0 +OP4 E00E69 0 +OP4 E00E6A 0 +OP4 E00E6B 0 +OP4 E00E6C 0 +OP4 E00E6D 0 +OP4 E00E6E 0 +OP4 E00E6F 0 +OP4 E00E70 0 +OP4 E00E71 0 +OP4 E00E72 0 +OP4 E00E73 0 +OP4 E00E74 0 +OP4 E00E75 0 +OP4 E00E76 0 +OP4 E00E77 0 +OP4 E00E78 0 +OP4 E00E79 0 +OP4 E00E7A 0 +OP4 E00E7B 0 +OP4 E00E7C 0 +OP4 E00E7D 0 +OP4 E00E7E 0 +OP4 E00E7F 0 +OP4 E00E80 0 +OP4 E00E81 0 +OP4 E00E82 0 +OP4 E00E83 0 +OP4 E00E84 0 +OP4 E00E85 0 +OP4 E00E86 0 +OP4 E00E87 0 +OP4 E00E88 0 +OP4 E00E89 0 +OP4 E00E8A 0 +OP4 E00E8B 0 +OP4 E00E8C 0 +OP4 E00E8D 0 +OP4 E00E8E 0 +OP4 E00E8F 0 +OP4 E00E90 0 +OP4 E00E91 0 +OP4 E00E92 0 +OP4 E00E93 0 +OP4 E00E94 0 +OP4 E00E95 0 +OP4 E00E96 0 +OP4 E00E97 0 +OP4 E00E98 0 +OP4 E00E99 0 +OP4 E00E9A 0 +OP4 E00E9B 0 +OP4 E00E9C 0 +OP4 E00E9D 0 +OP4 E00E9E 0 +OP4 E00E9F 0 +OP4 E00EA0 0 +OP4 E00EA1 0 +OP4 E00EA2 0 +OP4 E00EA3 0 +OP4 E00EA4 0 +OP4 E00EA5 0 +OP4 E00EA6 0 +OP4 E00EA7 0 +OP4 E00EA8 0 +OP4 E00EA9 0 +OP4 E00EAA 0 +OP4 E00EAB 0 +OP4 E00EAC 0 +OP4 E00EAD 0 +OP4 E00EAE 0 +OP4 E00EAF 0 +OP4 E00EB0 0 +OP4 E00EB1 0 +OP4 E00EB2 0 +OP4 E00EB3 0 +OP4 E00EB4 0 +OP4 E00EB5 0 +OP4 E00EB6 0 +OP4 E00EB7 0 +OP4 E00EB8 0 +OP4 E00EB9 0 +OP4 E00EBA 0 +OP4 E00EBB 0 +OP4 E00EBC 0 +OP4 E00EBD 0 +OP4 E00EBE 0 +OP4 E00EBF 0 +OP4 E00EC0 0 +OP4 E00EC1 0 +OP4 E00EC2 0 +OP4 E00EC3 0 +OP4 E00EC4 0 +OP4 E00EC5 0 +OP4 E00EC6 0 +OP4 E00EC7 0 +OP4 E00EC8 0 +OP4 E00EC9 0 +OP4 E00ECA 0 +OP4 E00ECB 0 +OP4 E00ECC 0 +OP4 E00ECD 0 +OP4 E00ECE 0 +OP4 E00ECF 0 +OP4 E00ED0 0 +OP4 E00ED1 0 +OP4 E00ED2 0 +OP4 E00ED3 0 +OP4 E00ED4 0 +OP4 E00ED5 0 +OP4 E00ED6 0 +OP4 E00ED7 0 +OP4 E00ED8 0 +OP4 E00ED9 0 +OP4 E00EDA 0 +OP4 E00EDB 0 +OP4 E00EDC 0 +OP4 E00EDD 0 +OP4 E00EDE 0 +OP4 E00EDF 0 +OP4 E00EE0 0 +OP4 E00EE1 0 +OP4 E00EE2 0 +OP4 E00EE3 0 +OP4 E00EE4 0 +OP4 E00EE5 0 +OP4 E00EE6 0 +OP4 E00EE7 0 +OP4 E00EE8 0 +OP4 E00EE9 0 +OP4 E00EEA 0 +OP4 E00EEB 0 +OP4 E00EEC 0 +OP4 E00EED 0 +OP4 E00EEE 0 +OP4 E00EEF 0 +OP4 E00EF0 0 +OP4 E00EF1 0 +OP4 E00EF2 0 +OP4 E00EF3 0 +OP4 E00EF4 0 +OP4 E00EF5 0 +OP4 E00EF6 0 +OP4 E00EF7 0 +OP4 E00EF8 0 +OP4 E00EF9 0 +OP4 E00EFA 0 +OP4 E00EFB 0 +OP4 E00EFC 0 +OP4 E00EFD 0 +OP4 E00EFE 0 +OP4 E00EFF 0 +OP4 E00F00 0 +OP4 E00F01 0 +OP4 E00F02 0 +OP4 E00F03 0 +OP4 E00F04 0 +OP4 E00F05 0 +OP4 E00F06 0 +OP4 E00F07 0 +OP4 E00F08 0 +OP4 E00F09 0 +OP4 E00F0A 0 +OP4 E00F0B 0 +OP4 E00F0C 0 +OP4 E00F0D 0 +OP4 E00F0E 0 +OP4 E00F0F 0 +OP4 E00F10 0 +OP4 E00F11 0 +OP4 E00F12 0 +OP4 E00F13 0 +OP4 E00F14 0 +OP4 E00F15 0 +OP4 E00F16 0 +OP4 E00F17 0 +OP4 E00F18 0 +OP4 E00F19 0 +OP4 E00F1A 0 +OP4 E00F1B 0 +OP4 E00F1C 0 +OP4 E00F1D 0 +OP4 E00F1E 0 +OP4 E00F1F 0 +OP4 E00F20 0 +OP4 E00F21 0 +OP4 E00F22 0 +OP4 E00F23 0 +OP4 E00F24 0 +OP4 E00F25 0 +OP4 E00F26 0 +OP4 E00F27 0 +OP4 E00F28 0 +OP4 E00F29 0 +OP4 E00F2A 0 +OP4 E00F2B 0 +OP4 E00F2C 0 +OP4 E00F2D 0 +OP4 E00F2E 0 +OP4 E00F2F 0 +OP4 E00F30 0 +OP4 E00F31 0 +OP4 E00F32 0 +OP4 E00F33 0 +OP4 E00F34 0 +OP4 E00F35 0 +OP4 E00F36 0 +OP4 E00F37 0 +OP4 E00F38 0 +OP4 E00F39 0 +OP4 E00F3A 0 +OP4 E00F3B 0 +OP4 E00F3C 0 +OP4 E00F3D 0 +OP4 E00F3E 0 +OP4 E00F3F 0 +OP4 E00F40 0 +OP4 E00F41 0 +OP4 E00F42 0 +OP4 E00F43 0 +OP4 E00F44 0 +OP4 E00F45 0 +OP4 E00F46 0 +OP4 E00F47 0 +OP4 E00F48 0 +OP4 E00F49 0 +OP4 E00F4A 0 +OP4 E00F4B 0 +OP4 E00F4C 0 +OP4 E00F4D 0 +OP4 E00F4E 0 +OP4 E00F4F 0 +OP4 E00F50 0 +OP4 E00F51 0 +OP4 E00F52 0 +OP4 E00F53 0 +OP4 E00F54 0 +OP4 E00F55 0 +OP4 E00F56 0 +OP4 E00F57 0 +OP4 E00F58 0 +OP4 E00F59 0 +OP4 E00F5A 0 +OP4 E00F5B 0 +OP4 E00F5C 0 +OP4 E00F5D 0 +OP4 E00F5E 0 +OP4 E00F5F 0 +OP4 E00F60 0 +OP4 E00F61 0 +OP4 E00F62 0 +OP4 E00F63 0 +OP4 E00F64 0 +OP4 E00F65 0 +OP4 E00F66 0 +OP4 E00F67 0 +OP4 E00F68 0 +OP4 E00F69 0 +OP4 E00F6A 0 +OP4 E00F6B 0 +OP4 E00F6C 0 +OP4 E00F6D 0 +OP4 E00F6E 0 +OP4 E00F6F 0 +OP4 E00F70 0 +OP4 E00F71 0 +OP4 E00F72 0 +OP4 E00F73 0 +OP4 E00F74 0 +OP4 E00F75 0 +OP4 E00F76 0 +OP4 E00F77 0 +OP4 E00F78 0 +OP4 E00F79 0 +OP4 E00F7A 0 +OP4 E00F7B 0 +OP4 E00F7C 0 +OP4 E00F7D 0 +OP4 E00F7E 0 +OP4 E00F7F 0 +OP4 E00F80 0 +OP4 E00F81 0 +OP4 E00F82 0 +OP4 E00F83 0 +OP4 E00F84 0 +OP4 E00F85 0 +OP4 E00F86 0 +OP4 E00F87 0 +OP4 E00F88 0 +OP4 E00F89 0 +OP4 E00F8A 0 +OP4 E00F8B 0 +OP4 E00F8C 0 +OP4 E00F8D 0 +OP4 E00F8E 0 +OP4 E00F8F 0 +OP4 E00F90 0 +OP4 E00F91 0 +OP4 E00F92 0 +OP4 E00F93 0 +OP4 E00F94 0 +OP4 E00F95 0 +OP4 E00F96 0 +OP4 E00F97 0 +OP4 E00F98 0 +OP4 E00F99 0 +OP4 E00F9A 0 +OP4 E00F9B 0 +OP4 E00F9C 0 +OP4 E00F9D 0 +OP4 E00F9E 0 +OP4 E00F9F 0 +OP4 E00FA0 0 +OP4 E00FA1 0 +OP4 E00FA2 0 +OP4 E00FA3 0 +OP4 E00FA4 0 +OP4 E00FA5 0 +OP4 E00FA6 0 +OP4 E00FA7 0 +OP4 E00FA8 0 +OP4 E00FA9 0 +OP4 E00FAA 0 +OP4 E00FAB 0 +OP4 E00FAC 0 +OP4 E00FAD 0 +OP4 E00FAE 0 +OP4 E00FAF 0 +OP4 E00FB0 0 +OP4 E00FB1 0 +OP4 E00FB2 0 +OP4 E00FB3 0 +OP4 E00FB4 0 +OP4 E00FB5 0 +OP4 E00FB6 0 +OP4 E00FB7 0 +OP4 E00FB8 0 +OP4 E00FB9 0 +OP4 E00FBA 0 +OP4 E00FBB 0 +OP4 E00FBC 0 +OP4 E00FBD 0 +OP4 E00FBE 0 +OP4 E00FBF 0 +OP4 E00FC0 0 +OP4 E00FC1 0 +OP4 E00FC2 0 +OP4 E00FC3 0 +OP4 E00FC4 0 +OP4 E00FC5 0 +OP4 E00FC6 0 +OP4 E00FC7 0 +OP4 E00FC8 0 +OP4 E00FC9 0 +OP4 E00FCA 0 +OP4 E00FCB 0 +OP4 E00FCC 0 +OP4 E00FCD 0 +OP4 E00FCE 0 +OP4 E00FCF 0 +OP4 E00FD0 0 +OP4 E00FD1 0 +OP4 E00FD2 0 +OP4 E00FD3 0 +OP4 E00FD4 0 +OP4 E00FD5 0 +OP4 E00FD6 0 +OP4 E00FD7 0 +OP4 E00FD8 0 +OP4 E00FD9 0 +OP4 E00FDA 0 +OP4 E00FDB 0 +OP4 E00FDC 0 +OP4 E00FDD 0 +OP4 E00FDE 0 +OP4 E00FDF 0 +OP4 E00FE0 0 +OP4 E00FE1 0 +OP4 E00FE2 0 +OP4 E00FE3 0 +OP4 E00FE4 0 +OP4 E00FE5 0 +OP4 E00FE6 0 +OP4 E00FE7 0 +OP4 E00FE8 0 +OP4 E00FE9 0 +OP4 E00FEA 0 +OP4 E00FEB 0 +OP4 E00FEC 0 +OP4 E00FED 0 +OP4 E00FEE 0 +OP4 E00FEF 0 +OP4 E00FF0 0 +OP4 E00FF1 0 +OP4 E00FF2 0 +OP4 E00FF3 0 +OP4 E00FF4 0 +OP4 E00FF5 0 +OP4 E00FF6 0 +OP4 E00FF7 0 +OP4 E00FF8 0 +OP4 E00FF9 0 +OP4 E00FFA 0 +OP4 E00FFB 0 +OP4 E00FFC 0 +OP4 E00FFD 0 +OP4 E00FFE 0 +OP4 E00FFF 0 +OP4 E01000 0 +OP4 E01001 0 +OP4 E01002 0 +OP4 E01003 0 +OP4 E01004 0 +OP4 E01005 0 +OP4 E01006 0 +OP4 E01007 0 +OP4 E01008 0 +OP4 E01009 0 +OP4 E0100A 0 +OP4 E0100B 0 +OP4 E0100C 0 +OP4 E0100D 0 +OP4 E0100E 0 +OP4 E0100F 0 +OP4 E01010 0 +OP4 E01011 0 +OP4 E01012 0 +OP4 E01013 0 +OP4 E01014 0 +OP4 E01015 0 +OP4 E01016 0 +OP4 E01017 0 +OP4 E01018 0 +OP4 E01019 0 +OP4 E0101A 0 +OP4 E0101B 0 +OP4 E0101C 0 +OP4 E0101D 0 +OP4 E0101E 0 +OP4 E0101F 0 +OP4 E01020 0 +OP4 E01021 0 +OP4 E01022 0 +OP4 E01023 0 +OP4 E01024 0 +OP4 E01025 0 +OP4 E01026 0 +OP4 E01027 0 +OP4 E01028 0 +OP4 E01029 0 +OP4 E0102A 0 +OP4 E0102B 0 +OP4 E0102C 0 +OP4 E0102D 0 +OP4 E0102E 0 +OP4 E0102F 0 +OP4 E01030 0 +OP4 E01031 0 +OP4 E01032 0 +OP4 E01033 0 +OP4 E01034 0 +OP4 E01035 0 +OP4 E01036 0 +OP4 E01037 0 +OP4 E01038 0 +OP4 E01039 0 +OP4 E0103A 0 +OP4 E0103B 0 +OP4 E0103C 0 +OP4 E0103D 0 +OP4 E0103E 0 +OP4 E0103F 0 +OP4 E01040 0 +OP4 E01041 0 +OP4 E01042 0 +OP4 E01043 0 +OP4 E01044 0 +OP4 E01045 0 +OP4 E01046 0 +OP4 E01047 0 +OP4 E01048 0 +OP4 E01049 0 +OP4 E0104A 0 +OP4 E0104B 0 +OP4 E0104C 0 +OP4 E0104D 0 +OP4 E0104E 0 +OP4 E0104F 0 +OP4 E01050 0 +OP4 E01051 0 +OP4 E01052 0 +OP4 E01053 0 +OP4 E01054 0 +OP4 E01055 0 +OP4 E01056 0 +OP4 E01057 0 +OP4 E01058 0 +OP4 E01059 0 +OP4 E0105A 0 +OP4 E0105B 0 +OP4 E0105C 0 +OP4 E0105D 0 +OP4 E0105E 0 +OP4 E0105F 0 +OP4 E01060 0 +OP4 E01061 0 +OP4 E01062 0 +OP4 E01063 0 +OP4 E01064 0 +OP4 E01065 0 +OP4 E01066 0 +OP4 E01067 0 +OP4 E01068 0 +OP4 E01069 0 +OP4 E0106A 0 +OP4 E0106B 0 +OP4 E0106C 0 +OP4 E0106D 0 +OP4 E0106E 0 +OP4 E0106F 0 +OP4 E01070 0 +OP4 E01071 0 +OP4 E01072 0 +OP4 E01073 0 +OP4 E01074 0 +OP4 E01075 0 +OP4 E01076 0 +OP4 E01077 0 +OP4 E01078 0 +OP4 E01079 0 +OP4 E0107A 0 +OP4 E0107B 0 +OP4 E0107C 0 +OP4 E0107D 0 +OP4 E0107E 0 +OP4 E0107F 0 +OP4 E01080 0 +OP4 E01081 0 +OP4 E01082 0 +OP4 E01083 0 +OP4 E01084 0 +OP4 E01085 0 +OP4 E01086 0 +OP4 E01087 0 +OP4 E01088 0 +OP4 E01089 0 +OP4 E0108A 0 +OP4 E0108B 0 +OP4 E0108C 0 +OP4 E0108D 0 +OP4 E0108E 0 +OP4 E0108F 0 +OP4 E01090 0 +OP4 E01091 0 +OP4 E01092 0 +OP4 E01093 0 +OP4 E01094 0 +OP4 E01095 0 +OP4 E01096 0 +OP4 E01097 0 +OP4 E01098 0 +OP4 E01099 0 +OP4 E0109A 0 +OP4 E0109B 0 +OP4 E0109C 0 +OP4 E0109D 0 +OP4 E0109E 0 +OP4 E0109F 0 +OP4 E010A0 0 +OP4 E010A1 0 +OP4 E010A2 0 +OP4 E010A3 0 +OP4 E010A4 0 +OP4 E010A5 0 +OP4 E010A6 0 +OP4 E010A7 0 +OP4 E010A8 0 +OP4 E010A9 0 +OP4 E010AA 0 +OP4 E010AB 0 +OP4 E010AC 0 +OP4 E010AD 0 +OP4 E010AE 0 +OP4 E010AF 0 +OP4 E010B0 0 +OP4 E010B1 0 +OP4 E010B2 0 +OP4 E010B3 0 +OP4 E010B4 0 +OP4 E010B5 0 +OP4 E010B6 0 +OP4 E010B7 0 +OP4 E010B8 0 +OP4 E010B9 0 +OP4 E010BA 0 +OP4 E010BB 0 +OP4 E010BC 0 +OP4 E010BD 0 +OP4 E010BE 0 +OP4 E010BF 0 +OP4 E010C0 0 +OP4 E010C1 0 +OP4 E010C2 0 +OP4 E010C3 0 +OP4 E010C4 0 +OP4 E010C5 0 +OP4 E010C6 0 +OP4 E010C7 0 +OP4 E010C8 0 +OP4 E010C9 0 +OP4 E010CA 0 +OP4 E010CB 0 +OP4 E010CC 0 +OP4 E010CD 0 +OP4 E010CE 0 +OP4 E010CF 0 +OP4 E010D0 0 +OP4 E010D1 0 +OP4 E010D2 0 +OP4 E010D3 0 +OP4 E010D4 0 +OP4 E010D5 0 +OP4 E010D6 0 +OP4 E010D7 0 +OP4 E010D8 0 +OP4 E010D9 0 +OP4 E010DA 0 +OP4 E010DB 0 +OP4 E010DC 0 +OP4 E010DD 0 +OP4 E010DE 0 +OP4 E010DF 0 +OP4 E010E0 0 +OP4 E010E1 0 +OP4 E010E2 0 +OP4 E010E3 0 +OP4 E010E4 0 +OP4 E010E5 0 +OP4 E010E6 0 +OP4 E010E7 0 +OP4 E010E8 0 +OP4 E010E9 0 +OP4 E010EA 0 +OP4 E010EB 0 +OP4 E010EC 0 +OP4 E010ED 0 +OP4 E010EE 0 +OP4 E010EF 0 +OP4 E010F0 0 +OP4 E010F1 0 +OP4 E010F2 0 +OP4 E010F3 0 +OP4 E010F4 0 +OP4 E010F5 0 +OP4 E010F6 0 +OP4 E010F7 0 +OP4 E010F8 0 +OP4 E010F9 0 +OP4 E010FA 0 +OP4 E010FB 0 +OP4 E010FC 0 +OP4 E010FD 0 +OP4 E010FE 0 +OP4 E010FF 0 +OP4 E01100 0 +OP4 E01101 0 +OP4 E01102 0 +OP4 E01103 0 +OP4 E01104 0 +OP4 E01105 0 +OP4 E01106 0 +OP4 E01107 0 +OP4 E01108 0 +OP4 E01109 0 +OP4 E0110A 0 +OP4 E0110B 0 +OP4 E0110C 0 +OP4 E0110D 0 +OP4 E0110E 0 +OP4 E0110F 0 +OP4 E01110 0 +OP4 E01111 0 +OP4 E01112 0 +OP4 E01113 0 +OP4 E01114 0 +OP4 E01115 0 +OP4 E01116 0 +OP4 E01117 0 +OP4 E01118 0 +OP4 E01119 0 +OP4 E0111A 0 +OP4 E0111B 0 +OP4 E0111C 0 +OP4 E0111D 0 +OP4 E0111E 0 +OP4 E0111F 0 +OP4 E01120 0 +OP4 E01121 0 +OP4 E01122 0 +OP4 E01123 0 +OP4 E01124 0 +OP4 E01125 0 +OP4 E01126 0 +OP4 E01127 0 +OP4 E01128 0 +OP4 E01129 0 +OP4 E0112A 0 +OP4 E0112B 0 +OP4 E0112C 0 +OP4 E0112D 0 +OP4 E0112E 0 +OP4 E0112F 0 +OP4 E01130 0 +OP4 E01131 0 +OP4 E01132 0 +OP4 E01133 0 +OP4 E01134 0 +OP4 E01135 0 +OP4 E01136 0 +OP4 E01137 0 +OP4 E01138 0 +OP4 E01139 0 +OP4 E0113A 0 +OP4 E0113B 0 +OP4 E0113C 0 +OP4 E0113D 0 +OP4 E0113E 0 +OP4 E0113F 0 +OP4 E01140 0 +OP4 E01141 0 +OP4 E01142 0 +OP4 E01143 0 +OP4 E01144 0 +OP4 E01145 0 +OP4 E01146 0 +OP4 E01147 0 +OP4 E01148 0 +OP4 E01149 0 +OP4 E0114A 0 +OP4 E0114B 0 +OP4 E0114C 0 +OP4 E0114D 0 +OP4 E0114E 0 +OP4 E0114F 0 +OP4 E01150 0 +OP4 E01151 0 +OP4 E01152 0 +OP4 E01153 0 +OP4 E01154 0 +OP4 E01155 0 +OP4 E01156 0 +OP4 E01157 0 +OP4 E01158 0 +OP4 E01159 0 +OP4 E0115A 0 +OP4 E0115B 0 +OP4 E0115C 0 +OP4 E0115D 0 +OP4 E0115E 0 +OP4 E0115F 0 +OP4 E01160 0 +OP4 E01161 0 +OP4 E01162 0 +OP4 E01163 0 +OP4 E01164 0 +OP4 E01165 0 +OP4 E01166 0 +OP4 E01167 0 +OP4 E01168 0 +OP4 E01169 0 +OP4 E0116A 0 +OP4 E0116B 0 +OP4 E0116C 0 +OP4 E0116D 0 +OP4 E0116E 0 +OP4 E0116F 0 +OP4 E01170 0 +OP4 E01171 0 +OP4 E01172 0 +OP4 E01173 0 +OP4 E01174 0 +OP4 E01175 0 +OP4 E01176 0 +OP4 E01177 0 +OP4 E01178 0 +OP4 E01179 0 +OP4 E0117A 0 +OP4 E0117B 0 +OP4 E0117C 0 +OP4 E0117D 0 +OP4 E0117E 0 +OP4 E0117F 0 +OP4 E01180 0 +OP4 E01181 0 +OP4 E01182 0 +OP4 E01183 0 +OP4 E01184 0 +OP4 E01185 0 +OP4 E01186 0 +OP4 E01187 0 +OP4 E01188 0 +OP4 E01189 0 +OP4 E0118A 0 +OP4 E0118B 0 +OP4 E0118C 0 +OP4 E0118D 0 +OP4 E0118E 0 +OP4 E0118F 0 +OP4 E01190 0 +OP4 E01191 0 +OP4 E01192 0 +OP4 E01193 0 +OP4 E01194 0 +OP4 E01195 0 +OP4 E01196 0 +OP4 E01197 0 +OP4 E01198 0 +OP4 E01199 0 +OP4 E0119A 0 +OP4 E0119B 0 +OP4 E0119C 0 +OP4 E0119D 0 +OP4 E0119E 0 +OP4 E0119F 0 +OP4 E011A0 0 +OP4 E011A1 0 +OP4 E011A2 0 +OP4 E011A3 0 +OP4 E011A4 0 +OP4 E011A5 0 +OP4 E011A6 0 +OP4 E011A7 0 +OP4 E011A8 0 +OP4 E011A9 0 +OP4 E011AA 0 +OP4 E011AB 0 +OP4 E011AC 0 +OP4 E011AD 0 +OP4 E011AE 0 +OP4 E011AF 0 +OP4 E011B0 0 +OP4 E011B1 0 +OP4 E011B2 0 +OP4 E011B3 0 +OP4 E011B4 0 +OP4 E011B5 0 +OP4 E011B6 0 +OP4 E011B7 0 +OP4 E011B8 0 +OP4 E011B9 0 +OP4 E011BA 0 +OP4 E011BB 0 +OP4 E011BC 0 +OP4 E011BD 0 +OP4 E011BE 0 +OP4 E011BF 0 +OP4 E011C0 0 +OP4 E011C1 0 +OP4 E011C2 0 +OP4 E011C3 0 +OP4 E011C4 0 +OP4 E011C5 0 +OP4 E011C6 0 +OP4 E011C7 0 +OP4 E011C8 0 +OP4 E011C9 0 +OP4 E011CA 0 +OP4 E011CB 0 +OP4 E011CC 0 +OP4 E011CD 0 +OP4 E011CE 0 +OP4 E011CF 0 +OP4 E011D0 0 +OP4 E011D1 0 +OP4 E011D2 0 +OP4 E011D3 0 +OP4 E011D4 0 +OP4 E011D5 0 +OP4 E011D6 0 +OP4 E011D7 0 +OP4 E011D8 0 +OP4 E011D9 0 +OP4 E011DA 0 +OP4 E011DB 0 +OP4 E011DC 0 +OP4 E011DD 0 +OP4 E011DE 0 +OP4 E011DF 0 +OP4 E011E0 0 +OP4 E011E1 0 +OP4 E011E2 0 +OP4 E011E3 0 +OP4 E011E4 0 +OP4 E011E5 0 +OP4 E011E6 0 +OP4 E011E7 0 +OP4 E011E8 0 +OP4 E011E9 0 +OP4 E011EA 0 +OP4 E011EB 0 +OP4 E011EC 0 +OP4 E011ED 0 +OP4 E011EE 0 +OP4 E011EF 0 +OP4 E011F0 0 +OP4 E011F1 0 +OP4 E011F2 0 +OP4 E011F3 0 +OP4 E011F4 0 +OP4 E011F5 0 +OP4 E011F6 0 +OP4 E011F7 0 +OP4 E011F8 0 +OP4 E011F9 0 +OP4 E011FA 0 +OP4 E011FB 0 +OP4 E011FC 0 +OP4 E011FD 0 +OP4 E011FE 0 +OP4 E011FF 0 +OP4 E01200 0 +OP4 E01201 0 +OP4 E01202 0 +OP4 E01203 0 +OP4 E01204 0 +OP4 E01205 0 +OP4 E01206 0 +OP4 E01207 0 +OP4 E01208 0 +OP4 E01209 0 +OP4 E0120A 0 +OP4 E0120B 0 +OP4 E0120C 0 +OP4 E0120D 0 +OP4 E0120E 0 +OP4 E0120F 0 +OP4 E01210 0 +OP4 E01211 0 +OP4 E01212 0 +OP4 E01213 0 +OP4 E01214 0 +OP4 E01215 0 +OP4 E01216 0 +OP4 E01217 0 +OP4 E01218 0 +OP4 E01219 0 +OP4 E0121A 0 +OP4 E0121B 0 +OP4 E0121C 0 +OP4 E0121D 0 +OP4 E0121E 0 +OP4 E0121F 0 +OP4 E01220 0 +OP4 E01221 0 +OP4 E01222 0 +OP4 E01223 0 +OP4 E01224 0 +OP4 E01225 0 +OP4 E01226 0 +OP4 E01227 0 +OP4 E01228 0 +OP4 E01229 0 +OP4 E0122A 0 +OP4 E0122B 0 +OP4 E0122C 0 +OP4 E0122D 0 +OP4 E0122E 0 +OP4 E0122F 0 +OP4 E01230 0 +OP4 E01231 0 +OP4 E01232 0 +OP4 E01233 0 +OP4 E01234 0 +OP4 E01235 0 +OP4 E01236 0 +OP4 E01237 0 +OP4 E01238 0 +OP4 E01239 0 +OP4 E0123A 0 +OP4 E0123B 0 +OP4 E0123C 0 +OP4 E0123D 0 +OP4 E0123E 0 +OP4 E0123F 0 +OP4 E01240 0 +OP4 E01241 0 +OP4 E01242 0 +OP4 E01243 0 +OP4 E01244 0 +OP4 E01245 0 +OP4 E01246 0 +OP4 E01247 0 +OP4 E01248 0 +OP4 E01249 0 +OP4 E0124A 0 +OP4 E0124B 0 +OP4 E0124C 0 +OP4 E0124D 0 +OP4 E0124E 0 +OP4 E0124F 0 +OP4 E01250 0 +OP4 E01251 0 +OP4 E01252 0 +OP4 E01253 0 +OP4 E01254 0 +OP4 E01255 0 +OP4 E01256 0 +OP4 E01257 0 +OP4 E01258 0 +OP4 E01259 0 +OP4 E0125A 0 +OP4 E0125B 0 +OP4 E0125C 0 +OP4 E0125D 0 +OP4 E0125E 0 +OP4 E0125F 0 +OP4 E01260 0 +OP4 E01261 0 +OP4 E01262 0 +OP4 E01263 0 +OP4 E01264 0 +OP4 E01265 0 +OP4 E01266 0 +OP4 E01267 0 +OP4 E01268 0 +OP4 E01269 0 +OP4 E0126A 0 +OP4 E0126B 0 +OP4 E0126C 0 +OP4 E0126D 0 +OP4 E0126E 0 +OP4 E0126F 0 +OP4 E01270 0 +OP4 E01271 0 +OP4 E01272 0 +OP4 E01273 0 +OP4 E01274 0 +OP4 E01275 0 +OP4 E01276 0 +OP4 E01277 0 +OP4 E01278 0 +OP4 E01279 0 +OP4 E0127A 0 +OP4 E0127B 0 +OP4 E0127C 0 +OP4 E0127D 0 +OP4 E0127E 0 +OP4 E0127F 0 +OP4 E01280 0 +OP4 E01281 0 +OP4 E01282 0 +OP4 E01283 0 +OP4 E01284 0 +OP4 E01285 0 +OP4 E01286 0 +OP4 E01287 0 +OP4 E01288 0 +OP4 E01289 0 +OP4 E0128A 0 +OP4 E0128B 0 +OP4 E0128C 0 +OP4 E0128D 0 +OP4 E0128E 0 +OP4 E0128F 0 +OP4 E01290 0 +OP4 E01291 0 +OP4 E01292 0 +OP4 E01293 0 +OP4 E01294 0 +OP4 E01295 0 +OP4 E01296 0 +OP4 E01297 0 +OP4 E01298 0 +OP4 E01299 0 +OP4 E0129A 0 +OP4 E0129B 0 +OP4 E0129C 0 +OP4 E0129D 0 +OP4 E0129E 0 +OP4 E0129F 0 +OP4 E012A0 0 +OP4 E012A1 0 +OP4 E012A2 0 +OP4 E012A3 0 +OP4 E012A4 0 +OP4 E012A5 0 +OP4 E012A6 0 +OP4 E012A7 0 +OP4 E012A8 0 +OP4 E012A9 0 +OP4 E012AA 0 +OP4 E012AB 0 +OP4 E012AC 0 +OP4 E012AD 0 +OP4 E012AE 0 +OP4 E012AF 0 +OP4 E012B0 0 +OP4 E012B1 0 +OP4 E012B2 0 +OP4 E012B3 0 +OP4 E012B4 0 +OP4 E012B5 0 +OP4 E012B6 0 +OP4 E012B7 0 +OP4 E012B8 0 +OP4 E012B9 0 +OP4 E012BA 0 +OP4 E012BB 0 +OP4 E012BC 0 +OP4 E012BD 0 +OP4 E012BE 0 +OP4 E012BF 0 +OP4 E012C0 0 +OP4 E012C1 0 +OP4 E012C2 0 +OP4 E012C3 0 +OP4 E012C4 0 +OP4 E012C5 0 +OP4 E012C6 0 +OP4 E012C7 0 +OP4 E012C8 0 +OP4 E012C9 0 +OP4 E012CA 0 +OP4 E012CB 0 +OP4 E012CC 0 +OP4 E012CD 0 +OP4 E012CE 0 +OP4 E012CF 0 +OP4 E012D0 0 +OP4 E012D1 0 +OP4 E012D2 0 +OP4 E012D3 0 +OP4 E012D4 0 +OP4 E012D5 0 +OP4 E012D6 0 +OP4 E012D7 0 +OP4 E012D8 0 +OP4 E012D9 0 +OP4 E012DA 0 +OP4 E012DB 0 +OP4 E012DC 0 +OP4 E012DD 0 +OP4 E012DE 0 +OP4 E012DF 0 +OP4 E012E0 0 +OP4 E012E1 0 +OP4 E012E2 0 +OP4 E012E3 0 +OP4 E012E4 0 +OP4 E012E5 0 +OP4 E012E6 0 +OP4 E012E7 0 +OP4 E012E8 0 +OP4 E012E9 0 +OP4 E012EA 0 +OP4 E012EB 0 +OP4 E012EC 0 +OP4 E012ED 0 +OP4 E012EE 0 +OP4 E012EF 0 +OP4 E012F0 0 +OP4 E012F1 0 +OP4 E012F2 0 +OP4 E012F3 0 +OP4 E012F4 0 +OP4 E012F5 0 +OP4 E012F6 0 +OP4 E012F7 0 +OP4 E012F8 0 +OP4 E012F9 0 +OP4 E012FA 0 +OP4 E012FB 0 +OP4 E012FC 0 +OP4 E012FD 0 +OP4 E012FE 0 +OP4 E012FF 0 +OP4 E01300 0 +OP4 E01301 0 +OP4 E01302 0 +OP4 E01303 0 +OP4 E01304 0 +OP4 E01305 0 +OP4 E01306 0 +OP4 E01307 0 +OP4 E01308 0 +OP4 E01309 0 +OP4 E0130A 0 +OP4 E0130B 0 +OP4 E0130C 0 +OP4 E0130D 0 +OP4 E0130E 0 +OP4 E0130F 0 +OP4 E01310 0 +OP4 E01311 0 +OP4 E01312 0 +OP4 E01313 0 +OP4 E01314 0 +OP4 E01315 0 +OP4 E01316 0 +OP4 E01317 0 +OP4 E01318 0 +OP4 E01319 0 +OP4 E0131A 0 +OP4 E0131B 0 +OP4 E0131C 0 +OP4 E0131D 0 +OP4 E0131E 0 +OP4 E0131F 0 +OP4 E01320 0 +OP4 E01321 0 +OP4 E01322 0 +OP4 E01323 0 +OP4 E01324 0 +OP4 E01325 0 +OP4 E01326 0 +OP4 E01327 0 +OP4 E01328 0 +OP4 E01329 0 +OP4 E0132A 0 +OP4 E0132B 0 +OP4 E0132C 0 +OP4 E0132D 0 +OP4 E0132E 0 +OP4 E0132F 0 +OP4 E01330 0 +OP4 E01331 0 +OP4 E01332 0 +OP4 E01333 0 +OP4 E01334 0 +OP4 E01335 0 +OP4 E01336 0 +OP4 E01337 0 +OP4 E01338 0 +OP4 E01339 0 +OP4 E0133A 0 +OP4 E0133B 0 +OP4 E0133C 0 +OP4 E0133D 0 +OP4 E0133E 0 +OP4 E0133F 0 +OP4 E01340 0 +OP4 E01341 0 +OP4 E01342 0 +OP4 E01343 0 +OP4 E01344 0 +OP4 E01345 0 +OP4 E01346 0 +OP4 E01347 0 +OP4 E01348 0 +OP4 E01349 0 +OP4 E0134A 0 +OP4 E0134B 0 +OP4 E0134C 0 +OP4 E0134D 0 +OP4 E0134E 0 +OP4 E0134F 0 +OP4 E01350 0 +OP4 E01351 0 +OP4 E01352 0 +OP4 E01353 0 +OP4 E01354 0 +OP4 E01355 0 +OP4 E01356 0 +OP4 E01357 0 +OP4 E01358 0 +OP4 E01359 0 +OP4 E0135A 0 +OP4 E0135B 0 +OP4 E0135C 0 +OP4 E0135D 0 +OP4 E0135E 0 +OP4 E0135F 0 +OP4 E01360 0 +OP4 E01361 0 +OP4 E01362 0 +OP4 E01363 0 +OP4 E01364 0 +OP4 E01365 0 +OP4 E01366 0 +OP4 E01367 0 +OP4 E01368 0 +OP4 E01369 0 +OP4 E0136A 0 +OP4 E0136B 0 +OP4 E0136C 0 +OP4 E0136D 0 +OP4 E0136E 0 +OP4 E0136F 0 +OP4 E01370 0 +OP4 E01371 0 +OP4 E01372 0 +OP4 E01373 0 +OP4 E01374 0 +OP4 E01375 0 +OP4 E01376 0 +OP4 E01377 0 +OP4 E01378 0 +OP4 E01379 0 +OP4 E0137A 0 +OP4 E0137B 0 +OP4 E0137C 0 +OP4 E0137D 0 +OP4 E0137E 0 +OP4 E0137F 0 +OP4 E01380 0 +OP4 E01381 0 +OP4 E01382 0 +OP4 E01383 0 +OP4 E01384 0 +OP4 E01385 0 +OP4 E01386 0 +OP4 E01387 0 +OP4 E01388 0 +OP4 E01389 0 +OP4 E0138A 0 +OP4 E0138B 0 +OP4 E0138C 0 +OP4 E0138D 0 +OP4 E0138E 0 +OP4 E0138F 0 +OP4 E01390 0 +OP4 E01391 0 +OP4 E01392 0 +OP4 E01393 0 +OP4 E01394 0 +OP4 E01395 0 +OP4 E01396 0 +OP4 E01397 0 +OP4 E01398 0 +OP4 E01399 0 +OP4 E0139A 0 +OP4 E0139B 0 +OP4 E0139C 0 +OP4 E0139D 0 +OP4 E0139E 0 +OP4 E0139F 0 +OP4 E013A0 0 +OP4 E013A1 0 +OP4 E013A2 0 +OP4 E013A3 0 +OP4 E013A4 0 +OP4 E013A5 0 +OP4 E013A6 0 +OP4 E013A7 0 +OP4 E013A8 0 +OP4 E013A9 0 +OP4 E013AA 0 +OP4 E013AB 0 +OP4 E013AC 0 +OP4 E013AD 0 +OP4 E013AE 0 +OP4 E013AF 0 +OP4 E013B0 0 +OP4 E013B1 0 +OP4 E013B2 0 +OP4 E013B3 0 +OP4 E013B4 0 +OP4 E013B5 0 +OP4 E013B6 0 +OP4 E013B7 0 +OP4 E013B8 0 +OP4 E013B9 0 +OP4 E013BA 0 +OP4 E013BB 0 +OP4 E013BC 0 +OP4 E013BD 0 +OP4 E013BE 0 +OP4 E013BF 0 +OP4 E013C0 0 +OP4 E013C1 0 +OP4 E013C2 0 +OP4 E013C3 0 +OP4 E013C4 0 +OP4 E013C5 0 +OP4 E013C6 0 +OP4 E013C7 0 +OP4 E013C8 0 +OP4 E013C9 0 +OP4 E013CA 0 +OP4 E013CB 0 +OP4 E013CC 0 +OP4 E013CD 0 +OP4 E013CE 0 +OP4 E013CF 0 +OP4 E013D0 0 +OP4 E013D1 0 +OP4 E013D2 0 +OP4 E013D3 0 +OP4 E013D4 0 +OP4 E013D5 0 +OP4 E013D6 0 +OP4 E013D7 0 +OP4 E013D8 0 +OP4 E013D9 0 +OP4 E013DA 0 +OP4 E013DB 0 +OP4 E013DC 0 +OP4 E013DD 0 +OP4 E013DE 0 +OP4 E013DF 0 +OP4 E013E0 0 +OP4 E013E1 0 +OP4 E013E2 0 +OP4 E013E3 0 +OP4 E013E4 0 +OP4 E013E5 0 +OP4 E013E6 0 +OP4 E013E7 0 +OP4 E013E8 0 +OP4 E013E9 0 +OP4 E013EA 0 +OP4 E013EB 0 +OP4 E013EC 0 +OP4 E013ED 0 +OP4 E013EE 0 +OP4 E013EF 0 +OP4 E013F0 0 +OP4 E013F1 0 +OP4 E013F2 0 +OP4 E013F3 0 +OP4 E013F4 0 +OP4 E013F5 0 +OP4 E013F6 0 +OP4 E013F7 0 +OP4 E013F8 0 +OP4 E013F9 0 +OP4 E013FA 0 +OP4 E013FB 0 +OP4 E013FC 0 +OP4 E013FD 0 +OP4 E013FE 0 +OP4 E013FF 0 +OP4 E01400 0 +OP4 E01401 0 +OP4 E01402 0 +OP4 E01403 0 +OP4 E01404 0 +OP4 E01405 0 +OP4 E01406 0 +OP4 E01407 0 +OP4 E01408 0 +OP4 E01409 0 +OP4 E0140A 0 +OP4 E0140B 0 +OP4 E0140C 0 +OP4 E0140D 0 +OP4 E0140E 0 +OP4 E0140F 0 +OP4 E01410 0 +OP4 E01411 0 +OP4 E01412 0 +OP4 E01413 0 +OP4 E01414 0 +OP4 E01415 0 +OP4 E01416 0 +OP4 E01417 0 +OP4 E01418 0 +OP4 E01419 0 +OP4 E0141A 0 +OP4 E0141B 0 +OP4 E0141C 0 +OP4 E0141D 0 +OP4 E0141E 0 +OP4 E0141F 0 +OP4 E01420 0 +OP4 E01421 0 +OP4 E01422 0 +OP4 E01423 0 +OP4 E01424 0 +OP4 E01425 0 +OP4 E01426 0 +OP4 E01427 0 +OP4 E01428 0 +OP4 E01429 0 +OP4 E0142A 0 +OP4 E0142B 0 +OP4 E0142C 0 +OP4 E0142D 0 +OP4 E0142E 0 +OP4 E0142F 0 +OP4 E01430 0 +OP4 E01431 0 +OP4 E01432 0 +OP4 E01433 0 +OP4 E01434 0 +OP4 E01435 0 +OP4 E01436 0 +OP4 E01437 0 +OP4 E01438 0 +OP4 E01439 0 +OP4 E0143A 0 +OP4 E0143B 0 +OP4 E0143C 0 +OP4 E0143D 0 +OP4 E0143E 0 +OP4 E0143F 0 +OP4 E01440 0 +OP4 E01441 0 +OP4 E01442 0 +OP4 E01443 0 +OP4 E01444 0 +OP4 E01445 0 +OP4 E01446 0 +OP4 E01447 0 +OP4 E01448 0 +OP4 E01449 0 +OP4 E0144A 0 +OP4 E0144B 0 +OP4 E0144C 0 +OP4 E0144D 0 +OP4 E0144E 0 +OP4 E0144F 0 +OP4 E01450 0 +OP4 E01451 0 +OP4 E01452 0 +OP4 E01453 0 +OP4 E01454 0 +OP4 E01455 0 +OP4 E01456 0 +OP4 E01457 0 +OP4 E01458 0 +OP4 E01459 0 +OP4 E0145A 0 +OP4 E0145B 0 +OP4 E0145C 0 +OP4 E0145D 0 +OP4 E0145E 0 +OP4 E0145F 0 +OP4 E01460 0 +OP4 E01461 0 +OP4 E01462 0 +OP4 E01463 0 +OP4 E01464 0 +OP4 E01465 0 +OP4 E01466 0 +OP4 E01467 0 +OP4 E01468 0 +OP4 E01469 0 +OP4 E0146A 0 +OP4 E0146B 0 +OP4 E0146C 0 +OP4 E0146D 0 +OP4 E0146E 0 +OP4 E0146F 0 +OP4 E01470 0 +OP4 E01471 0 +OP4 E01472 0 +OP4 E01473 0 +OP4 E01474 0 +OP4 E01475 0 +OP4 E01476 0 +OP4 E01477 0 +OP4 E01478 0 +OP4 E01479 0 +OP4 E0147A 0 +OP4 E0147B 0 +OP4 E0147C 0 +OP4 E0147D 0 +OP4 E0147E 0 +OP4 E0147F 0 +OP4 E01480 0 +OP4 E01481 0 +OP4 E01482 0 +OP4 E01483 0 +OP4 E01484 0 +OP4 E01485 0 +OP4 E01486 0 +OP4 E01487 0 +OP4 E01488 0 +OP4 E01489 0 +OP4 E0148A 0 +OP4 E0148B 0 +OP4 E0148C 0 +OP4 E0148D 0 +OP4 E0148E 0 +OP4 E0148F 0 +OP4 E01490 0 +OP4 E01491 0 +OP4 E01492 0 +OP4 E01493 0 +OP4 E01494 0 +OP4 E01495 0 +OP4 E01496 0 +OP4 E01497 0 +OP4 E01498 0 +OP4 E01499 0 +OP4 E0149A 0 +OP4 E0149B 0 +OP4 E0149C 0 +OP4 E0149D 0 +OP4 E0149E 0 +OP4 E0149F 0 +OP4 E014A0 0 +OP4 E014A1 0 +OP4 E014A2 0 +OP4 E014A3 0 +OP4 E014A4 0 +OP4 E014A5 0 +OP4 E014A6 0 +OP4 E014A7 0 +OP4 E014A8 0 +OP4 E014A9 0 +OP4 E014AA 0 +OP4 E014AB 0 +OP4 E014AC 0 +OP4 E014AD 0 +OP4 E014AE 0 +OP4 E014AF 0 +OP4 E014B0 0 +OP4 E014B1 0 +OP4 E014B2 0 +OP4 E014B3 0 +OP4 E014B4 0 +OP4 E014B5 0 +OP4 E014B6 0 +OP4 E014B7 0 +OP4 E014B8 0 +OP4 E014B9 0 +OP4 E014BA 0 +OP4 E014BB 0 +OP4 E014BC 0 +OP4 E014BD 0 +OP4 E014BE 0 +OP4 E014BF 0 +OP4 E014C0 0 +OP4 E014C1 0 +OP4 E014C2 0 +OP4 E014C3 0 +OP4 E014C4 0 +OP4 E014C5 0 +OP4 E014C6 0 +OP4 E014C7 0 +OP4 E014C8 0 +OP4 E014C9 0 +OP4 E014CA 0 +OP4 E014CB 0 +OP4 E014CC 0 +OP4 E014CD 0 +OP4 E014CE 0 +OP4 E014CF 0 +OP4 E014D0 0 +OP4 E014D1 0 +OP4 E014D2 0 +OP4 E014D3 0 +OP4 E014D4 0 +OP4 E014D5 0 +OP4 E014D6 0 +OP4 E014D7 0 +OP4 E014D8 0 +OP4 E014D9 0 +OP4 E014DA 0 +OP4 E014DB 0 +OP4 E014DC 0 +OP4 E014DD 0 +OP4 E014DE 0 +OP4 E014DF 0 +OP4 E014E0 0 +OP4 E014E1 0 +OP4 E014E2 0 +OP4 E014E3 0 +OP4 E014E4 0 +OP4 E014E5 0 +OP4 E014E6 0 +OP4 E014E7 0 +OP4 E014E8 0 +OP4 E014E9 0 +OP4 E014EA 0 +OP4 E014EB 0 +OP4 E014EC 0 +OP4 E014ED 0 +OP4 E014EE 0 +OP4 E014EF 0 +OP4 E014F0 0 +OP4 E014F1 0 +OP4 E014F2 0 +OP4 E014F3 0 +OP4 E014F4 0 +OP4 E014F5 0 +OP4 E014F6 0 +OP4 E014F7 0 +OP4 E014F8 0 +OP4 E014F9 0 +OP4 E014FA 0 +OP4 E014FB 0 +OP4 E014FC 0 +OP4 E014FD 0 +OP4 E014FE 0 +OP4 E014FF 0 +OP4 E01500 0 +OP4 E01501 0 +OP4 E01502 0 +OP4 E01503 0 +OP4 E01504 0 +OP4 E01505 0 +OP4 E01506 0 +OP4 E01507 0 +OP4 E01508 0 +OP4 E01509 0 +OP4 E0150A 0 +OP4 E0150B 0 +OP4 E0150C 0 +OP4 E0150D 0 +OP4 E0150E 0 +OP4 E0150F 0 +OP4 E01510 0 +OP4 E01511 0 +OP4 E01512 0 +OP4 E01513 0 +OP4 E01514 0 +OP4 E01515 0 +OP4 E01516 0 +OP4 E01517 0 +OP4 E01518 0 +OP4 E01519 0 +OP4 E0151A 0 +OP4 E0151B 0 +OP4 E0151C 0 +OP4 E0151D 0 +OP4 E0151E 0 +OP4 E0151F 0 +OP4 E01520 0 +OP4 E01521 0 +OP4 E01522 0 +OP4 E01523 0 +OP4 E01524 0 +OP4 E01525 0 +OP4 E01526 0 +OP4 E01527 0 +OP4 E01528 0 +OP4 E01529 0 +OP4 E0152A 0 +OP4 E0152B 0 +OP4 E0152C 0 +OP4 E0152D 0 +OP4 E0152E 0 +OP4 E0152F 0 +OP4 E01530 0 +OP4 E01531 0 +OP4 E01532 0 +OP4 E01533 0 +OP4 E01534 0 +OP4 E01535 0 +OP4 E01536 0 +OP4 E01537 0 +OP4 E01538 0 +OP4 E01539 0 +OP4 E0153A 0 +OP4 E0153B 0 +OP4 E0153C 0 +OP4 E0153D 0 +OP4 E0153E 0 +OP4 E0153F 0 +OP4 E01540 0 +OP4 E01541 0 +OP4 E01542 0 +OP4 E01543 0 +OP4 E01544 0 +OP4 E01545 0 +OP4 E01546 0 +OP4 E01547 0 +OP4 E01548 0 +OP4 E01549 0 +OP4 E0154A 0 +OP4 E0154B 0 +OP4 E0154C 0 +OP4 E0154D 0 +OP4 E0154E 0 +OP4 E0154F 0 +OP4 E01550 0 +OP4 E01551 0 +OP4 E01552 0 +OP4 E01553 0 +OP4 E01554 0 +OP4 E01555 0 +OP4 E01556 0 +OP4 E01557 0 +OP4 E01558 0 +OP4 E01559 0 +OP4 E0155A 0 +OP4 E0155B 0 +OP4 E0155C 0 +OP4 E0155D 0 +OP4 E0155E 0 +OP4 E0155F 0 +OP4 E01560 0 +OP4 E01561 0 +OP4 E01562 0 +OP4 E01563 0 +OP4 E01564 0 +OP4 E01565 0 +OP4 E01566 0 +OP4 E01567 0 +OP4 E01568 0 +OP4 E01569 0 +OP4 E0156A 0 +OP4 E0156B 0 +OP4 E0156C 0 +OP4 E0156D 0 +OP4 E0156E 0 +OP4 E0156F 0 +OP4 E01570 0 +OP4 E01571 0 +OP4 E01572 0 +OP4 E01573 0 +OP4 E01574 0 +OP4 E01575 0 +OP4 E01576 0 +OP4 E01577 0 +OP4 E01578 0 +OP4 E01579 0 +OP4 E0157A 0 +OP4 E0157B 0 +OP4 E0157C 0 +OP4 E0157D 0 +OP4 E0157E 0 +OP4 E0157F 0 +OP4 E01580 0 +OP4 E01581 0 +OP4 E01582 0 +OP4 E01583 0 +OP4 E01584 0 +OP4 E01585 0 +OP4 E01586 0 +OP4 E01587 0 +OP4 E01588 0 +OP4 E01589 0 +OP4 E0158A 0 +OP4 E0158B 0 +OP4 E0158C 0 +OP4 E0158D 0 +OP4 E0158E 0 +OP4 E0158F 0 +OP4 E01590 0 +OP4 E01591 0 +OP4 E01592 0 +OP4 E01593 0 +OP4 E01594 0 +OP4 E01595 0 +OP4 E01596 0 +OP4 E01597 0 +OP4 E01598 0 +OP4 E01599 0 +OP4 E0159A 0 +OP4 E0159B 0 +OP4 E0159C 0 +OP4 E0159D 0 +OP4 E0159E 0 +OP4 E0159F 0 +OP4 E015A0 0 +OP4 E015A1 0 +OP4 E015A2 0 +OP4 E015A3 0 +OP4 E015A4 0 +OP4 E015A5 0 +OP4 E015A6 0 +OP4 E015A7 0 +OP4 E015A8 0 +OP4 E015A9 0 +OP4 E015AA 0 +OP4 E015AB 0 +OP4 E015AC 0 +OP4 E015AD 0 +OP4 E015AE 0 +OP4 E015AF 0 +OP4 E015B0 0 +OP4 E015B1 0 +OP4 E015B2 0 +OP4 E015B3 0 +OP4 E015B4 0 +OP4 E015B5 0 +OP4 E015B6 0 +OP4 E015B7 0 +OP4 E015B8 0 +OP4 E015B9 0 +OP4 E015BA 0 +OP4 E015BB 0 +OP4 E015BC 0 +OP4 E015BD 0 +OP4 E015BE 0 +OP4 E015BF 0 +OP4 E015C0 0 +OP4 E015C1 0 +OP4 E015C2 0 +OP4 E015C3 0 +OP4 E015C4 0 +OP4 E015C5 0 +OP4 E015C6 0 +OP4 E015C7 0 +OP4 E015C8 0 +OP4 E015C9 0 +OP4 E015CA 0 +OP4 E015CB 0 +OP4 E015CC 0 +OP4 E015CD 0 +OP4 E015CE 0 +OP4 E015CF 0 +OP4 E015D0 0 +OP4 E015D1 0 +OP4 E015D2 0 +OP4 E015D3 0 +OP4 E015D4 0 +OP4 E015D5 0 +OP4 E015D6 0 +OP4 E015D7 0 +OP4 E015D8 0 +OP4 E015D9 0 +OP4 E015DA 0 +OP4 E015DB 0 +OP4 E015DC 0 +OP4 E015DD 0 +OP4 E015DE 0 +OP4 E015DF 0 +OP4 E015E0 0 +OP4 E015E1 0 +OP4 E015E2 0 +OP4 E015E3 0 +OP4 E015E4 0 +OP4 E015E5 0 +OP4 E015E6 0 +OP4 E015E7 0 +OP4 E015E8 0 +OP4 E015E9 0 +OP4 E015EA 0 +OP4 E015EB 0 +OP4 E015EC 0 +OP4 E015ED 0 +OP4 E015EE 0 +OP4 E015EF 0 +OP4 E015F0 0 +OP4 E015F1 0 +OP4 E015F2 0 +OP4 E015F3 0 +OP4 E015F4 0 +OP4 E015F5 0 +OP4 E015F6 0 +OP4 E015F7 0 +OP4 E015F8 0 +OP4 E015F9 0 +OP4 E015FA 0 +OP4 E015FB 0 +OP4 E015FC 0 +OP4 E015FD 0 +OP4 E015FE 0 +OP4 E015FF 0 +OP4 E01600 0 +OP4 E01601 0 +OP4 E01602 0 +OP4 E01603 0 +OP4 E01604 0 +OP4 E01605 0 +OP4 E01606 0 +OP4 E01607 0 +OP4 E01608 0 +OP4 E01609 0 +OP4 E0160A 0 +OP4 E0160B 0 +OP4 E0160C 0 +OP4 E0160D 0 +OP4 E0160E 0 +OP4 E0160F 0 +OP4 E01610 0 +OP4 E01611 0 +OP4 E01612 0 +OP4 E01613 0 +OP4 E01614 0 +OP4 E01615 0 +OP4 E01616 0 +OP4 E01617 0 +OP4 E01618 0 +OP4 E01619 0 +OP4 E0161A 0 +OP4 E0161B 0 +OP4 E0161C 0 +OP4 E0161D 0 +OP4 E0161E 0 +OP4 E0161F 0 +OP4 E01620 0 +OP4 E01621 0 +OP4 E01622 0 +OP4 E01623 0 +OP4 E01624 0 +OP4 E01625 0 +OP4 E01626 0 +OP4 E01627 0 +OP4 E01628 0 +OP4 E01629 0 +OP4 E0162A 0 +OP4 E0162B 0 +OP4 E0162C 0 +OP4 E0162D 0 +OP4 E0162E 0 +OP4 E0162F 0 +OP4 E01630 0 +OP4 E01631 0 +OP4 E01632 0 +OP4 E01633 0 +OP4 E01634 0 +OP4 E01635 0 +OP4 E01636 0 +OP4 E01637 0 +OP4 E01638 0 +OP4 E01639 0 +OP4 E0163A 0 +OP4 E0163B 0 +OP4 E0163C 0 +OP4 E0163D 0 +OP4 E0163E 0 +OP4 E0163F 0 +OP4 E01640 0 +OP4 E01641 0 +OP4 E01642 0 +OP4 E01643 0 +OP4 E01644 0 +OP4 E01645 0 +OP4 E01646 0 +OP4 E01647 0 +OP4 E01648 0 +OP4 E01649 0 +OP4 E0164A 0 +OP4 E0164B 0 +OP4 E0164C 0 +OP4 E0164D 0 +OP4 E0164E 0 +OP4 E0164F 0 +OP4 E01650 0 +OP4 E01651 0 +OP4 E01652 0 +OP4 E01653 0 +OP4 E01654 0 +OP4 E01655 0 +OP4 E01656 0 +OP4 E01657 0 +OP4 E01658 0 +OP4 E01659 0 +OP4 E0165A 0 +OP4 E0165B 0 +OP4 E0165C 0 +OP4 E0165D 0 +OP4 E0165E 0 +OP4 E0165F 0 +OP4 E01660 0 +OP4 E01661 0 +OP4 E01662 0 +OP4 E01663 0 +OP4 E01664 0 +OP4 E01665 0 +OP4 E01666 0 +OP4 E01667 0 +OP4 E01668 0 +OP4 E01669 0 +OP4 E0166A 0 +OP4 E0166B 0 +OP4 E0166C 0 +OP4 E0166D 0 +OP4 E0166E 0 +OP4 E0166F 0 +OP4 E01670 0 +OP4 E01671 0 +OP4 E01672 0 +OP4 E01673 0 +OP4 E01674 0 +OP4 E01675 0 +OP4 E01676 0 +OP4 E01677 0 +OP4 E01678 0 +OP4 E01679 0 +OP4 E0167A 0 +OP4 E0167B 0 +OP4 E0167C 0 +OP4 E0167D 0 +OP4 E0167E 0 +OP4 E0167F 0 +OP4 E01680 0 +OP4 E01681 0 +OP4 E01682 0 +OP4 E01683 0 +OP4 E01684 0 +OP4 E01685 0 +OP4 E01686 0 +OP4 E01687 0 +OP4 E01688 0 +OP4 E01689 0 +OP4 E0168A 0 +OP4 E0168B 0 +OP4 E0168C 0 +OP4 E0168D 0 +OP4 E0168E 0 +OP4 E0168F 0 +OP4 E01690 0 +OP4 E01691 0 +OP4 E01692 0 +OP4 E01693 0 +OP4 E01694 0 +OP4 E01695 0 +OP4 E01696 0 +OP4 E01697 0 +OP4 E01698 0 +OP4 E01699 0 +OP4 E0169A 0 +OP4 E0169B 0 +OP4 E0169C 0 +OP4 E0169D 0 +OP4 E0169E 0 +OP4 E0169F 0 +OP4 E016A0 0 +OP4 E016A1 0 +OP4 E016A2 0 +OP4 E016A3 0 +OP4 E016A4 0 +OP4 E016A5 0 +OP4 E016A6 0 +OP4 E016A7 0 +OP4 E016A8 0 +OP4 E016A9 0 +OP4 E016AA 0 +OP4 E016AB 0 +OP4 E016AC 0 +OP4 E016AD 0 +OP4 E016AE 0 +OP4 E016AF 0 +OP4 E016B0 0 +OP4 E016B1 0 +OP4 E016B2 0 +OP4 E016B3 0 +OP4 E016B4 0 +OP4 E016B5 0 +OP4 E016B6 0 +OP4 E016B7 0 +OP4 E016B8 0 +OP4 E016B9 0 +OP4 E016BA 0 +OP4 E016BB 0 +OP4 E016BC 0 +OP4 E016BD 0 +OP4 E016BE 0 +OP4 E016BF 0 +OP4 E016C0 0 +OP4 E016C1 0 +OP4 E016C2 0 +OP4 E016C3 0 +OP4 E016C4 0 +OP4 E016C5 0 +OP4 E016C6 0 +OP4 E016C7 0 +OP4 E016C8 0 +OP4 E016C9 0 +OP4 E016CA 0 +OP4 E016CB 0 +OP4 E016CC 0 +OP4 E016CD 0 +OP4 E016CE 0 +OP4 E016CF 0 +OP4 E016D0 0 +OP4 E016D1 0 +OP4 E016D2 0 +OP4 E016D3 0 +OP4 E016D4 0 +OP4 E016D5 0 +OP4 E016D6 0 +OP4 E016D7 0 +OP4 E016D8 0 +OP4 E016D9 0 +OP4 E016DA 0 +OP4 E016DB 0 +OP4 E016DC 0 +OP4 E016DD 0 +OP4 E016DE 0 +OP4 E016DF 0 +OP4 E016E0 0 +OP4 E016E1 0 +OP4 E016E2 0 +OP4 E016E3 0 +OP4 E016E4 0 +OP4 E016E5 0 +OP4 E016E6 0 +OP4 E016E7 0 +OP4 E016E8 0 +OP4 E016E9 0 +OP4 E016EA 0 +OP4 E016EB 0 +OP4 E016EC 0 +OP4 E016ED 0 +OP4 E016EE 0 +OP4 E016EF 0 +OP4 E016F0 0 +OP4 E016F1 0 +OP4 E016F2 0 +OP4 E016F3 0 +OP4 E016F4 0 +OP4 E016F5 0 +OP4 E016F6 0 +OP4 E016F7 0 +OP4 E016F8 0 +OP4 E016F9 0 +OP4 E016FA 0 +OP4 E016FB 0 +OP4 E016FC 0 +OP4 E016FD 0 +OP4 E016FE 0 +OP4 E016FF 0 +OP4 E01700 0 +OP4 E01701 0 +OP4 E01702 0 +OP4 E01703 0 +OP4 E01704 0 +OP4 E01705 0 +OP4 E01706 0 +OP4 E01707 0 +OP4 E01708 0 +OP4 E01709 0 +OP4 E0170A 0 +OP4 E0170B 0 +OP4 E0170C 0 +OP4 E0170D 0 +OP4 E0170E 0 +OP4 E0170F 0 +OP4 E01710 0 +OP4 E01711 0 +OP4 E01712 0 +OP4 E01713 0 +OP4 E01714 0 +OP4 E01715 0 +OP4 E01716 0 +OP4 E01717 0 +OP4 E01718 0 +OP4 E01719 0 +OP4 E0171A 0 +OP4 E0171B 0 +OP4 E0171C 0 +OP4 E0171D 0 +OP4 E0171E 0 +OP4 E0171F 0 +OP4 E01720 0 +OP4 E01721 0 +OP4 E01722 0 +OP4 E01723 0 +OP4 E01724 0 +OP4 E01725 0 +OP4 E01726 0 +OP4 E01727 0 +OP4 E01728 0 +OP4 E01729 0 +OP4 E0172A 0 +OP4 E0172B 0 +OP4 E0172C 0 +OP4 E0172D 0 +OP4 E0172E 0 +OP4 E0172F 0 +OP4 E01730 0 +OP4 E01731 0 +OP4 E01732 0 +OP4 E01733 0 +OP4 E01734 0 +OP4 E01735 0 +OP4 E01736 0 +OP4 E01737 0 +OP4 E01738 0 +OP4 E01739 0 +OP4 E0173A 0 +OP4 E0173B 0 +OP4 E0173C 0 +OP4 E0173D 0 +OP4 E0173E 0 +OP4 E0173F 0 +OP4 E01740 0 +OP4 E01741 0 +OP4 E01742 0 +OP4 E01743 0 +OP4 E01744 0 +OP4 E01745 0 +OP4 E01746 0 +OP4 E01747 0 +OP4 E01748 0 +OP4 E01749 0 +OP4 E0174A 0 +OP4 E0174B 0 +OP4 E0174C 0 +OP4 E0174D 0 +OP4 E0174E 0 +OP4 E0174F 0 +OP4 E01750 0 +OP4 E01751 0 +OP4 E01752 0 +OP4 E01753 0 +OP4 E01754 0 +OP4 E01755 0 +OP4 E01756 0 +OP4 E01757 0 +OP4 E01758 0 +OP4 E01759 0 +OP4 E0175A 0 +OP4 E0175B 0 +OP4 E0175C 0 +OP4 E0175D 0 +OP4 E0175E 0 +OP4 E0175F 0 +OP4 E01760 0 +OP4 E01761 0 +OP4 E01762 0 +OP4 E01763 0 +OP4 E01764 0 +OP4 E01765 0 +OP4 E01766 0 +OP4 E01767 0 +OP4 E01768 0 +OP4 E01769 0 +OP4 E0176A 0 +OP4 E0176B 0 +OP4 E0176C 0 +OP4 E0176D 0 +OP4 E0176E 0 +OP4 E0176F 0 +OP4 E01770 0 +OP4 E01771 0 +OP4 E01772 0 +OP4 E01773 0 +OP4 E01774 0 +OP4 E01775 0 +OP4 E01776 0 +OP4 E01777 0 +OP4 E01778 0 +OP4 E01779 0 +OP4 E0177A 0 +OP4 E0177B 0 +OP4 E0177C 0 +OP4 E0177D 0 +OP4 E0177E 0 +OP4 E0177F 0 +OP4 E01780 0 +OP4 E01781 0 +OP4 E01782 0 +OP4 E01783 0 +OP4 E01784 0 +OP4 E01785 0 +OP4 E01786 0 +OP4 E01787 0 +OP4 E01788 0 +OP4 E01789 0 +OP4 E0178A 0 +OP4 E0178B 0 +OP4 E0178C 0 +OP4 E0178D 0 +OP4 E0178E 0 +OP4 E0178F 0 +OP4 E01790 0 +OP4 E01791 0 +OP4 E01792 0 +OP4 E01793 0 +OP4 E01794 0 +OP4 E01795 0 +OP4 E01796 0 +OP4 E01797 0 +OP4 E01798 0 +OP4 E01799 0 +OP4 E0179A 0 +OP4 E0179B 0 +OP4 E0179C 0 +OP4 E0179D 0 +OP4 E0179E 0 +OP4 E0179F 0 +OP4 E017A0 0 +OP4 E017A1 0 +OP4 E017A2 0 +OP4 E017A3 0 +OP4 E017A4 0 +OP4 E017A5 0 +OP4 E017A6 0 +OP4 E017A7 0 +OP4 E017A8 0 +OP4 E017A9 0 +OP4 E017AA 0 +OP4 E017AB 0 +OP4 E017AC 0 +OP4 E017AD 0 +OP4 E017AE 0 +OP4 E017AF 0 +OP4 E017B0 0 +OP4 E017B1 0 +OP4 E017B2 0 +OP4 E017B3 0 +OP4 E017B4 0 +OP4 E017B5 0 +OP4 E017B6 0 +OP4 E017B7 0 +OP4 E017B8 0 +OP4 E017B9 0 +OP4 E017BA 0 +OP4 E017BB 0 +OP4 E017BC 0 +OP4 E017BD 0 +OP4 E017BE 0 +OP4 E017BF 0 +OP4 E017C0 0 +OP4 E017C1 0 +OP4 E017C2 0 +OP4 E017C3 0 +OP4 E017C4 0 +OP4 E017C5 0 +OP4 E017C6 0 +OP4 E017C7 0 +OP4 E017C8 0 +OP4 E017C9 0 +OP4 E017CA 0 +OP4 E017CB 0 +OP4 E017CC 0 +OP4 E017CD 0 +OP4 E017CE 0 +OP4 E017CF 0 +OP4 E017D0 0 +OP4 E017D1 0 +OP4 E017D2 0 +OP4 E017D3 0 +OP4 E017D4 0 +OP4 E017D5 0 +OP4 E017D6 0 +OP4 E017D7 0 +OP4 E017D8 0 +OP4 E017D9 0 +OP4 E017DA 0 +OP4 E017DB 0 +OP4 E017DC 0 +OP4 E017DD 0 +OP4 E017DE 0 +OP4 E017DF 0 +OP4 E017E0 0 +OP4 E017E1 0 +OP4 E017E2 0 +OP4 E017E3 0 +OP4 E017E4 0 +OP4 E017E5 0 +OP4 E017E6 0 +OP4 E017E7 0 +OP4 E017E8 0 +OP4 E017E9 0 +OP4 E017EA 0 +OP4 E017EB 0 +OP4 E017EC 0 +OP4 E017ED 0 +OP4 E017EE 0 +OP4 E017EF 0 +OP4 E017F0 0 +OP4 E017F1 0 +OP4 E017F2 0 +OP4 E017F3 0 +OP4 E017F4 0 +OP4 E017F5 0 +OP4 E017F6 0 +OP4 E017F7 0 +OP4 E017F8 0 +OP4 E017F9 0 +OP4 E017FA 0 +OP4 E017FB 0 +OP4 E017FC 0 +OP4 E017FD 0 +OP4 E017FE 0 +OP4 E017FF 0 +OP4 E01800 0 +OP4 E01801 0 +OP4 E01802 0 +OP4 E01803 0 +OP4 E01804 0 +OP4 E01805 0 +OP4 E01806 0 +OP4 E01807 0 +OP4 E01808 0 +OP4 E01809 0 +OP4 E0180A 0 +OP4 E0180B 0 +OP4 E0180C 0 +OP4 E0180D 0 +OP4 E0180E 0 +OP4 E0180F 0 +OP4 E01810 0 +OP4 E01811 0 +OP4 E01812 0 +OP4 E01813 0 +OP4 E01814 0 +OP4 E01815 0 +OP4 E01816 0 +OP4 E01817 0 +OP4 E01818 0 +OP4 E01819 0 +OP4 E0181A 0 +OP4 E0181B 0 +OP4 E0181C 0 +OP4 E0181D 0 +OP4 E0181E 0 +OP4 E0181F 0 +OP4 E01820 0 +OP4 E01821 0 +OP4 E01822 0 +OP4 E01823 0 +OP4 E01824 0 +OP4 E01825 0 +OP4 E01826 0 +OP4 E01827 0 +OP4 E01828 0 +OP4 E01829 0 +OP4 E0182A 0 +OP4 E0182B 0 +OP4 E0182C 0 +OP4 E0182D 0 +OP4 E0182E 0 +OP4 E0182F 0 +OP4 E01830 0 +OP4 E01831 0 +OP4 E01832 0 +OP4 E01833 0 +OP4 E01834 0 +OP4 E01835 0 +OP4 E01836 0 +OP4 E01837 0 +OP4 E01838 0 +OP4 E01839 0 +OP4 E0183A 0 +OP4 E0183B 0 +OP4 E0183C 0 +OP4 E0183D 0 +OP4 E0183E 0 +OP4 E0183F 0 +OP4 E01840 0 +OP4 E01841 0 +OP4 E01842 0 +OP4 E01843 0 +OP4 E01844 0 +OP4 E01845 0 +OP4 E01846 0 +OP4 E01847 0 +OP4 E01848 0 +OP4 E01849 0 +OP4 E0184A 0 +OP4 E0184B 0 +OP4 E0184C 0 +OP4 E0184D 0 +OP4 E0184E 0 +OP4 E0184F 0 +OP4 E01850 0 +OP4 E01851 0 +OP4 E01852 0 +OP4 E01853 0 +OP4 E01854 0 +OP4 E01855 0 +OP4 E01856 0 +OP4 E01857 0 +OP4 E01858 0 +OP4 E01859 0 +OP4 E0185A 0 +OP4 E0185B 0 +OP4 E0185C 0 +OP4 E0185D 0 +OP4 E0185E 0 +OP4 E0185F 0 +OP4 E01860 0 +OP4 E01861 0 +OP4 E01862 0 +OP4 E01863 0 +OP4 E01864 0 +OP4 E01865 0 +OP4 E01866 0 +OP4 E01867 0 +OP4 E01868 0 +OP4 E01869 0 +OP4 E0186A 0 +OP4 E0186B 0 +OP4 E0186C 0 +OP4 E0186D 0 +OP4 E0186E 0 +OP4 E0186F 0 +OP4 E01870 0 +OP4 E01871 0 +OP4 E01872 0 +OP4 E01873 0 +OP4 E01874 0 +OP4 E01875 0 +OP4 E01876 0 +OP4 E01877 0 +OP4 E01878 0 +OP4 E01879 0 +OP4 E0187A 0 +OP4 E0187B 0 +OP4 E0187C 0 +OP4 E0187D 0 +OP4 E0187E 0 +OP4 E0187F 0 +OP4 E01880 0 +OP4 E01881 0 +OP4 E01882 0 +OP4 E01883 0 +OP4 E01884 0 +OP4 E01885 0 +OP4 E01886 0 +OP4 E01887 0 +OP4 E01888 0 +OP4 E01889 0 +OP4 E0188A 0 +OP4 E0188B 0 +OP4 E0188C 0 +OP4 E0188D 0 +OP4 E0188E 0 +OP4 E0188F 0 +OP4 E01890 0 +OP4 E01891 0 +OP4 E01892 0 +OP4 E01893 0 +OP4 E01894 0 +OP4 E01895 0 +OP4 E01896 0 +OP4 E01897 0 +OP4 E01898 0 +OP4 E01899 0 +OP4 E0189A 0 +OP4 E0189B 0 +OP4 E0189C 0 +OP4 E0189D 0 +OP4 E0189E 0 +OP4 E0189F 0 +OP4 E018A0 0 +OP4 E018A1 0 +OP4 E018A2 0 +OP4 E018A3 0 +OP4 E018A4 0 +OP4 E018A5 0 +OP4 E018A6 0 +OP4 E018A7 0 +OP4 E018A8 0 +OP4 E018A9 0 +OP4 E018AA 0 +OP4 E018AB 0 +OP4 E018AC 0 +OP4 E018AD 0 +OP4 E018AE 0 +OP4 E018AF 0 +OP4 E018B0 0 +OP4 E018B1 0 +OP4 E018B2 0 +OP4 E018B3 0 +OP4 E018B4 0 +OP4 E018B5 0 +OP4 E018B6 0 +OP4 E018B7 0 +OP4 E018B8 0 +OP4 E018B9 0 +OP4 E018BA 0 +OP4 E018BB 0 +OP4 E018BC 0 +OP4 E018BD 0 +OP4 E018BE 0 +OP4 E018BF 0 +OP4 E018C0 0 +OP4 E018C1 0 +OP4 E018C2 0 +OP4 E018C3 0 +OP4 E018C4 0 +OP4 E018C5 0 +OP4 E018C6 0 +OP4 E018C7 0 +OP4 E018C8 0 +OP4 E018C9 0 +OP4 E018CA 0 +OP4 E018CB 0 +OP4 E018CC 0 +OP4 E018CD 0 +OP4 E018CE 0 +OP4 E018CF 0 +OP4 E018D0 0 +OP4 E018D1 0 +OP4 E018D2 0 +OP4 E018D3 0 +OP4 E018D4 0 +OP4 E018D5 0 +OP4 E018D6 0 +OP4 E018D7 0 +OP4 E018D8 0 +OP4 E018D9 0 +OP4 E018DA 0 +OP4 E018DB 0 +OP4 E018DC 0 +OP4 E018DD 0 +OP4 E018DE 0 +OP4 E018DF 0 +OP4 E018E0 0 +OP4 E018E1 0 +OP4 E018E2 0 +OP4 E018E3 0 +OP4 E018E4 0 +OP4 E018E5 0 +OP4 E018E6 0 +OP4 E018E7 0 +OP4 E018E8 0 +OP4 E018E9 0 +OP4 E018EA 0 +OP4 E018EB 0 +OP4 E018EC 0 +OP4 E018ED 0 +OP4 E018EE 0 +OP4 E018EF 0 +OP4 E018F0 0 +OP4 E018F1 0 +OP4 E018F2 0 +OP4 E018F3 0 +OP4 E018F4 0 +OP4 E018F5 0 +OP4 E018F6 0 +OP4 E018F7 0 +OP4 E018F8 0 +OP4 E018F9 0 +OP4 E018FA 0 +OP4 E018FB 0 +OP4 E018FC 0 +OP4 E018FD 0 +OP4 E018FE 0 +OP4 E018FF 0 +OP4 E01900 0 +OP4 E01901 0 +OP4 E01902 0 +OP4 E01903 0 +OP4 E01904 0 +OP4 E01905 0 +OP4 E01906 0 +OP4 E01907 0 +OP4 E01908 0 +OP4 E01909 0 +OP4 E0190A 0 +OP4 E0190B 0 +OP4 E0190C 0 +OP4 E0190D 0 +OP4 E0190E 0 +OP4 E0190F 0 +OP4 E01910 0 +OP4 E01911 0 +OP4 E01912 0 +OP4 E01913 0 +OP4 E01914 0 +OP4 E01915 0 +OP4 E01916 0 +OP4 E01917 0 +OP4 E01918 0 +OP4 E01919 0 +OP4 E0191A 0 +OP4 E0191B 0 +OP4 E0191C 0 +OP4 E0191D 0 +OP4 E0191E 0 +OP4 E0191F 0 +OP4 E01920 0 +OP4 E01921 0 +OP4 E01922 0 +OP4 E01923 0 +OP4 E01924 0 +OP4 E01925 0 +OP4 E01926 0 +OP4 E01927 0 +OP4 E01928 0 +OP4 E01929 0 +OP4 E0192A 0 +OP4 E0192B 0 +OP4 E0192C 0 +OP4 E0192D 0 +OP4 E0192E 0 +OP4 E0192F 0 +OP4 E01930 0 +OP4 E01931 0 +OP4 E01932 0 +OP4 E01933 0 +OP4 E01934 0 +OP4 E01935 0 +OP4 E01936 0 +OP4 E01937 0 +OP4 E01938 0 +OP4 E01939 0 +OP4 E0193A 0 +OP4 E0193B 0 +OP4 E0193C 0 +OP4 E0193D 0 +OP4 E0193E 0 +OP4 E0193F 0 +OP4 E01940 0 +OP4 E01941 0 +OP4 E01942 0 +OP4 E01943 0 +OP4 E01944 0 +OP4 E01945 0 +OP4 E01946 0 +OP4 E01947 0 +OP4 E01948 0 +OP4 E01949 0 +OP4 E0194A 0 +OP4 E0194B 0 +OP4 E0194C 0 +OP4 E0194D 0 +OP4 E0194E 0 +OP4 E0194F 0 +OP4 E01950 0 +OP4 E01951 0 +OP4 E01952 0 +OP4 E01953 0 +OP4 E01954 0 +OP4 E01955 0 +OP4 E01956 0 +OP4 E01957 0 +OP4 E01958 0 +OP4 E01959 0 +OP4 E0195A 0 +OP4 E0195B 0 +OP4 E0195C 0 +OP4 E0195D 0 +OP4 E0195E 0 +OP4 E0195F 0 +OP4 E01960 0 +OP4 E01961 0 +OP4 E01962 0 +OP4 E01963 0 +OP4 E01964 0 +OP4 E01965 0 +OP4 E01966 0 +OP4 E01967 0 +OP4 E01968 0 +OP4 E01969 0 +OP4 E0196A 0 +OP4 E0196B 0 +OP4 E0196C 0 +OP4 E0196D 0 +OP4 E0196E 0 +OP4 E0196F 0 +OP4 E01970 0 +OP4 E01971 0 +OP4 E01972 0 +OP4 E01973 0 +OP4 E01974 0 +OP4 E01975 0 +OP4 E01976 0 +OP4 E01977 0 +OP4 E01978 0 +OP4 E01979 0 +OP4 E0197A 0 +OP4 E0197B 0 +OP4 E0197C 0 +OP4 E0197D 0 +OP4 E0197E 0 +OP4 E0197F 0 +OP4 E01980 0 +OP4 E01981 0 +OP4 E01982 0 +OP4 E01983 0 +OP4 E01984 0 +OP4 E01985 0 +OP4 E01986 0 +OP4 E01987 0 +OP4 E01988 0 +OP4 E01989 0 +OP4 E0198A 0 +OP4 E0198B 0 +OP4 E0198C 0 +OP4 E0198D 0 +OP4 E0198E 0 +OP4 E0198F 0 +OP4 E01990 0 +OP4 E01991 0 +OP4 E01992 0 +OP4 E01993 0 +OP4 E01994 0 +OP4 E01995 0 +OP4 E01996 0 +OP4 E01997 0 +OP4 E01998 0 +OP4 E01999 0 +OP4 E0199A 0 +OP4 E0199B 0 +OP4 E0199C 0 +OP4 E0199D 0 +OP4 E0199E 0 +OP4 E0199F 0 +OP4 E019A0 0 +OP4 E019A1 0 +OP4 E019A2 0 +OP4 E019A3 0 +OP4 E019A4 0 +OP4 E019A5 0 +OP4 E019A6 0 +OP4 E019A7 0 +OP4 E019A8 0 +OP4 E019A9 0 +OP4 E019AA 0 +OP4 E019AB 0 +OP4 E019AC 0 +OP4 E019AD 0 +OP4 E019AE 0 +OP4 E019AF 0 +OP4 E019B0 0 +OP4 E019B1 0 +OP4 E019B2 0 +OP4 E019B3 0 +OP4 E019B4 0 +OP4 E019B5 0 +OP4 E019B6 0 +OP4 E019B7 0 +OP4 E019B8 0 +OP4 E019B9 0 +OP4 E019BA 0 +OP4 E019BB 0 +OP4 E019BC 0 +OP4 E019BD 0 +OP4 E019BE 0 +OP4 E019BF 0 +OP4 E019C0 0 +OP4 E019C1 0 +OP4 E019C2 0 +OP4 E019C3 0 +OP4 E019C4 0 +OP4 E019C5 0 +OP4 E019C6 0 +OP4 E019C7 0 +OP4 E019C8 0 +OP4 E019C9 0 +OP4 E019CA 0 +OP4 E019CB 0 +OP4 E019CC 0 +OP4 E019CD 0 +OP4 E019CE 0 +OP4 E019CF 0 +OP4 E019D0 0 +OP4 E019D1 0 +OP4 E019D2 0 +OP4 E019D3 0 +OP4 E019D4 0 +OP4 E019D5 0 +OP4 E019D6 0 +OP4 E019D7 0 +OP4 E019D8 0 +OP4 E019D9 0 +OP4 E019DA 0 +OP4 E019DB 0 +OP4 E019DC 0 +OP4 E019DD 0 +OP4 E019DE 0 +OP4 E019DF 0 +OP4 E019E0 0 +OP4 E019E1 0 +OP4 E019E2 0 +OP4 E019E3 0 +OP4 E019E4 0 +OP4 E019E5 0 +OP4 E019E6 0 +OP4 E019E7 0 +OP4 E019E8 0 +OP4 E019E9 0 +OP4 E019EA 0 +OP4 E019EB 0 +OP4 E019EC 0 +OP4 E019ED 0 +OP4 E019EE 0 +OP4 E019EF 0 +OP4 E019F0 0 +OP4 E019F1 0 +OP4 E019F2 0 +OP4 E019F3 0 +OP4 E019F4 0 +OP4 E019F5 0 +OP4 E019F6 0 +OP4 E019F7 0 +OP4 E019F8 0 +OP4 E019F9 0 +OP4 E019FA 0 +OP4 E019FB 0 +OP4 E019FC 0 +OP4 E019FD 0 +OP4 E019FE 0 +OP4 E019FF 0 +OP4 E01A00 0 +OP4 E01A01 0 +OP4 E01A02 0 +OP4 E01A03 0 +OP4 E01A04 0 +OP4 E01A05 0 +OP4 E01A06 0 +OP4 E01A07 0 +OP4 E01A08 0 +OP4 E01A09 0 +OP4 E01A0A 0 +OP4 E01A0B 0 +OP4 E01A0C 0 +OP4 E01A0D 0 +OP4 E01A0E 0 +OP4 E01A0F 0 +OP4 E01A10 0 +OP4 E01A11 0 +OP4 E01A12 0 +OP4 E01A13 0 +OP4 E01A14 0 +OP4 E01A15 0 +OP4 E01A16 0 +OP4 E01A17 0 +OP4 E01A18 0 +OP4 E01A19 0 +OP4 E01A1A 0 +OP4 E01A1B 0 +OP4 E01A1C 0 +OP4 E01A1D 0 +OP4 E01A1E 0 +OP4 E01A1F 0 +OP4 E01A20 0 +OP4 E01A21 0 +OP4 E01A22 0 +OP4 E01A23 0 +OP4 E01A24 0 +OP4 E01A25 0 +OP4 E01A26 0 +OP4 E01A27 0 +OP4 E01A28 0 +OP4 E01A29 0 +OP4 E01A2A 0 +OP4 E01A2B 0 +OP4 E01A2C 0 +OP4 E01A2D 0 +OP4 E01A2E 0 +OP4 E01A2F 0 +OP4 E01A30 0 +OP4 E01A31 0 +OP4 E01A32 0 +OP4 E01A33 0 +OP4 E01A34 0 +OP4 E01A35 0 +OP4 E01A36 0 +OP4 E01A37 0 +OP4 E01A38 0 +OP4 E01A39 0 +OP4 E01A3A 0 +OP4 E01A3B 0 +OP4 E01A3C 0 +OP4 E01A3D 0 +OP4 E01A3E 0 +OP4 E01A3F 0 +OP4 E01A40 0 +OP4 E01A41 0 +OP4 E01A42 0 +OP4 E01A43 0 +OP4 E01A44 0 +OP4 E01A45 0 +OP4 E01A46 0 +OP4 E01A47 0 +OP4 E01A48 0 +OP4 E01A49 0 +OP4 E01A4A 0 +OP4 E01A4B 0 +OP4 E01A4C 0 +OP4 E01A4D 0 +OP4 E01A4E 0 +OP4 E01A4F 0 +OP4 E01A50 0 +OP4 E01A51 0 +OP4 E01A52 0 +OP4 E01A53 0 +OP4 E01A54 0 +OP4 E01A55 0 +OP4 E01A56 0 +OP4 E01A57 0 +OP4 E01A58 0 +OP4 E01A59 0 +OP4 E01A5A 0 +OP4 E01A5B 0 +OP4 E01A5C 0 +OP4 E01A5D 0 +OP4 E01A5E 0 +OP4 E01A5F 0 +OP4 E01A60 0 +OP4 E01A61 0 +OP4 E01A62 0 +OP4 E01A63 0 +OP4 E01A64 0 +OP4 E01A65 0 +OP4 E01A66 0 +OP4 E01A67 0 +OP4 E01A68 0 +OP4 E01A69 0 +OP4 E01A6A 0 +OP4 E01A6B 0 +OP4 E01A6C 0 +OP4 E01A6D 0 +OP4 E01A6E 0 +OP4 E01A6F 0 +OP4 E01A70 0 +OP4 E01A71 0 +OP4 E01A72 0 +OP4 E01A73 0 +OP4 E01A74 0 +OP4 E01A75 0 +OP4 E01A76 0 +OP4 E01A77 0 +OP4 E01A78 0 +OP4 E01A79 0 +OP4 E01A7A 0 +OP4 E01A7B 0 +OP4 E01A7C 0 +OP4 E01A7D 0 +OP4 E01A7E 0 +OP4 E01A7F 0 +OP4 E01A80 0 +OP4 E01A81 0 +OP4 E01A82 0 +OP4 E01A83 0 +OP4 E01A84 0 +OP4 E01A85 0 +OP4 E01A86 0 +OP4 E01A87 0 +OP4 E01A88 0 +OP4 E01A89 0 +OP4 E01A8A 0 +OP4 E01A8B 0 +OP4 E01A8C 0 +OP4 E01A8D 0 +OP4 E01A8E 0 +OP4 E01A8F 0 +OP4 E01A90 0 +OP4 E01A91 0 +OP4 E01A92 0 +OP4 E01A93 0 +OP4 E01A94 0 +OP4 E01A95 0 +OP4 E01A96 0 +OP4 E01A97 0 +OP4 E01A98 0 +OP4 E01A99 0 +OP4 E01A9A 0 +OP4 E01A9B 0 +OP4 E01A9C 0 +OP4 E01A9D 0 +OP4 E01A9E 0 +OP4 E01A9F 0 +OP4 E01AA0 0 +OP4 E01AA1 0 +OP4 E01AA2 0 +OP4 E01AA3 0 +OP4 E01AA4 0 +OP4 E01AA5 0 +OP4 E01AA6 0 +OP4 E01AA7 0 +OP4 E01AA8 0 +OP4 E01AA9 0 +OP4 E01AAA 0 +OP4 E01AAB 0 +OP4 E01AAC 0 +OP4 E01AAD 0 +OP4 E01AAE 0 +OP4 E01AAF 0 +OP4 E01AB0 0 +OP4 E01AB1 0 +OP4 E01AB2 0 +OP4 E01AB3 0 +OP4 E01AB4 0 +OP4 E01AB5 0 +OP4 E01AB6 0 +OP4 E01AB7 0 +OP4 E01AB8 0 +OP4 E01AB9 0 +OP4 E01ABA 0 +OP4 E01ABB 0 +OP4 E01ABC 0 +OP4 E01ABD 0 +OP4 E01ABE 0 +OP4 E01ABF 0 +OP4 E01AC0 0 +OP4 E01AC1 0 +OP4 E01AC2 0 +OP4 E01AC3 0 +OP4 E01AC4 0 +OP4 E01AC5 0 +OP4 E01AC6 0 +OP4 E01AC7 0 +OP4 E01AC8 0 +OP4 E01AC9 0 +OP4 E01ACA 0 +OP4 E01ACB 0 +OP4 E01ACC 0 +OP4 E01ACD 0 +OP4 E01ACE 0 +OP4 E01ACF 0 +OP4 E01AD0 0 +OP4 E01AD1 0 +OP4 E01AD2 0 +OP4 E01AD3 0 +OP4 E01AD4 0 +OP4 E01AD5 0 +OP4 E01AD6 0 +OP4 E01AD7 0 +OP4 E01AD8 0 +OP4 E01AD9 0 +OP4 E01ADA 0 +OP4 E01ADB 0 +OP4 E01ADC 0 +OP4 E01ADD 0 +OP4 E01ADE 0 +OP4 E01ADF 0 +OP4 E01AE0 0 +OP4 E01AE1 0 +OP4 E01AE2 0 +OP4 E01AE3 0 +OP4 E01AE4 0 +OP4 E01AE5 0 +OP4 E01AE6 0 +OP4 E01AE7 0 +OP4 E01AE8 0 +OP4 E01AE9 0 +OP4 E01AEA 0 +OP4 E01AEB 0 +OP4 E01AEC 0 +OP4 E01AED 0 +OP4 E01AEE 0 +OP4 E01AEF 0 +OP4 E01AF0 0 +OP4 E01AF1 0 +OP4 E01AF2 0 +OP4 E01AF3 0 +OP4 E01AF4 0 +OP4 E01AF5 0 +OP4 E01AF6 0 +OP4 E01AF7 0 +OP4 E01AF8 0 +OP4 E01AF9 0 +OP4 E01AFA 0 +OP4 E01AFB 0 +OP4 E01AFC 0 +OP4 E01AFD 0 +OP4 E01AFE 0 +OP4 E01AFF 0 +OP4 E01B00 0 +OP4 E01B01 0 +OP4 E01B02 0 +OP4 E01B03 0 +OP4 E01B04 0 +OP4 E01B05 0 +OP4 E01B06 0 +OP4 E01B07 0 +OP4 E01B08 0 +OP4 E01B09 0 +OP4 E01B0A 0 +OP4 E01B0B 0 +OP4 E01B0C 0 +OP4 E01B0D 0 +OP4 E01B0E 0 +OP4 E01B0F 0 +OP4 E01B10 0 +OP4 E01B11 0 +OP4 E01B12 0 +OP4 E01B13 0 +OP4 E01B14 0 +OP4 E01B15 0 +OP4 E01B16 0 +OP4 E01B17 0 +OP4 E01B18 0 +OP4 E01B19 0 +OP4 E01B1A 0 +OP4 E01B1B 0 +OP4 E01B1C 0 +OP4 E01B1D 0 +OP4 E01B1E 0 +OP4 E01B1F 0 +OP4 E01B20 0 +OP4 E01B21 0 +OP4 E01B22 0 +OP4 E01B23 0 +OP4 E01B24 0 +OP4 E01B25 0 +OP4 E01B26 0 +OP4 E01B27 0 +OP4 E01B28 0 +OP4 E01B29 0 +OP4 E01B2A 0 +OP4 E01B2B 0 +OP4 E01B2C 0 +OP4 E01B2D 0 +OP4 E01B2E 0 +OP4 E01B2F 0 +OP4 E01B30 0 +OP4 E01B31 0 +OP4 E01B32 0 +OP4 E01B33 0 +OP4 E01B34 0 +OP4 E01B35 0 +OP4 E01B36 0 +OP4 E01B37 0 +OP4 E01B38 0 +OP4 E01B39 0 +OP4 E01B3A 0 +OP4 E01B3B 0 +OP4 E01B3C 0 +OP4 E01B3D 0 +OP4 E01B3E 0 +OP4 E01B3F 0 +OP4 E01B40 0 +OP4 E01B41 0 +OP4 E01B42 0 +OP4 E01B43 0 +OP4 E01B44 0 +OP4 E01B45 0 +OP4 E01B46 0 +OP4 E01B47 0 +OP4 E01B48 0 +OP4 E01B49 0 +OP4 E01B4A 0 +OP4 E01B4B 0 +OP4 E01B4C 0 +OP4 E01B4D 0 +OP4 E01B4E 0 +OP4 E01B4F 0 +OP4 E01B50 0 +OP4 E01B51 0 +OP4 E01B52 0 +OP4 E01B53 0 +OP4 E01B54 0 +OP4 E01B55 0 +OP4 E01B56 0 +OP4 E01B57 0 +OP4 E01B58 0 +OP4 E01B59 0 +OP4 E01B5A 0 +OP4 E01B5B 0 +OP4 E01B5C 0 +OP4 E01B5D 0 +OP4 E01B5E 0 +OP4 E01B5F 0 +OP4 E01B60 0 +OP4 E01B61 0 +OP4 E01B62 0 +OP4 E01B63 0 +OP4 E01B64 0 +OP4 E01B65 0 +OP4 E01B66 0 +OP4 E01B67 0 +OP4 E01B68 0 +OP4 E01B69 0 +OP4 E01B6A 0 +OP4 E01B6B 0 +OP4 E01B6C 0 +OP4 E01B6D 0 +OP4 E01B6E 0 +OP4 E01B6F 0 +OP4 E01B70 0 +OP4 E01B71 0 +OP4 E01B72 0 +OP4 E01B73 0 +OP4 E01B74 0 +OP4 E01B75 0 +OP4 E01B76 0 +OP4 E01B77 0 +OP4 E01B78 0 +OP4 E01B79 0 +OP4 E01B7A 0 +OP4 E01B7B 0 +OP4 E01B7C 0 +OP4 E01B7D 0 +OP4 E01B7E 0 +OP4 E01B7F 0 +OP4 E01B80 0 +OP4 E01B81 0 +OP4 E01B82 0 +OP4 E01B83 0 +OP4 E01B84 0 +OP4 E01B85 0 +OP4 E01B86 0 +OP4 E01B87 0 +OP4 E01B88 0 +OP4 E01B89 0 +OP4 E01B8A 0 +OP4 E01B8B 0 +OP4 E01B8C 0 +OP4 E01B8D 0 +OP4 E01B8E 0 +OP4 E01B8F 0 +OP4 E01B90 0 +OP4 E01B91 0 +OP4 E01B92 0 +OP4 E01B93 0 +OP4 E01B94 0 +OP4 E01B95 0 +OP4 E01B96 0 +OP4 E01B97 0 +OP4 E01B98 0 +OP4 E01B99 0 +OP4 E01B9A 0 +OP4 E01B9B 0 +OP4 E01B9C 0 +OP4 E01B9D 0 +OP4 E01B9E 0 +OP4 E01B9F 0 +OP4 E01BA0 0 +OP4 E01BA1 0 +OP4 E01BA2 0 +OP4 E01BA3 0 +OP4 E01BA4 0 +OP4 E01BA5 0 +OP4 E01BA6 0 +OP4 E01BA7 0 +OP4 E01BA8 0 +OP4 E01BA9 0 +OP4 E01BAA 0 +OP4 E01BAB 0 +OP4 E01BAC 0 +OP4 E01BAD 0 +OP4 E01BAE 0 +OP4 E01BAF 0 +OP4 E01BB0 0 +OP4 E01BB1 0 +OP4 E01BB2 0 +OP4 E01BB3 0 +OP4 E01BB4 0 +OP4 E01BB5 0 +OP4 E01BB6 0 +OP4 E01BB7 0 +OP4 E01BB8 0 +OP4 E01BB9 0 +OP4 E01BBA 0 +OP4 E01BBB 0 +OP4 E01BBC 0 +OP4 E01BBD 0 +OP4 E01BBE 0 +OP4 E01BBF 0 +OP4 E01BC0 0 +OP4 E01BC1 0 +OP4 E01BC2 0 +OP4 E01BC3 0 +OP4 E01BC4 0 +OP4 E01BC5 0 +OP4 E01BC6 0 +OP4 E01BC7 0 +OP4 E01BC8 0 +OP4 E01BC9 0 +OP4 E01BCA 0 +OP4 E01BCB 0 +OP4 E01BCC 0 +OP4 E01BCD 0 +OP4 E01BCE 0 +OP4 E01BCF 0 +OP4 E01BD0 0 +OP4 E01BD1 0 +OP4 E01BD2 0 +OP4 E01BD3 0 +OP4 E01BD4 0 +OP4 E01BD5 0 +OP4 E01BD6 0 +OP4 E01BD7 0 +OP4 E01BD8 0 +OP4 E01BD9 0 +OP4 E01BDA 0 +OP4 E01BDB 0 +OP4 E01BDC 0 +OP4 E01BDD 0 +OP4 E01BDE 0 +OP4 E01BDF 0 +OP4 E01BE0 0 +OP4 E01BE1 0 +OP4 E01BE2 0 +OP4 E01BE3 0 +OP4 E01BE4 0 +OP4 E01BE5 0 +OP4 E01BE6 0 +OP4 E01BE7 0 +OP4 E01BE8 0 +OP4 E01BE9 0 +OP4 E01BEA 0 +OP4 E01BEB 0 +OP4 E01BEC 0 +OP4 E01BED 0 +OP4 E01BEE 0 +OP4 E01BEF 0 +OP4 E01BF0 0 +OP4 E01BF1 0 +OP4 E01BF2 0 +OP4 E01BF3 0 +OP4 E01BF4 0 +OP4 E01BF5 0 +OP4 E01BF6 0 +OP4 E01BF7 0 +OP4 E01BF8 0 +OP4 E01BF9 0 +OP4 E01BFA 0 +OP4 E01BFB 0 +OP4 E01BFC 0 +OP4 E01BFD 0 +OP4 E01BFE 0 +OP4 E01BFF 0 +OP4 E01C00 0 +OP4 E01C01 0 +OP4 E01C02 0 +OP4 E01C03 0 +OP4 E01C04 0 +OP4 E01C05 0 +OP4 E01C06 0 +OP4 E01C07 0 +OP4 E01C08 0 +OP4 E01C09 0 +OP4 E01C0A 0 +OP4 E01C0B 0 +OP4 E01C0C 0 +OP4 E01C0D 0 +OP4 E01C0E 0 +OP4 E01C0F 0 +OP4 E01C10 0 +OP4 E01C11 0 +OP4 E01C12 0 +OP4 E01C13 0 +OP4 E01C14 0 +OP4 E01C15 0 +OP4 E01C16 0 +OP4 E01C17 0 +OP4 E01C18 0 +OP4 E01C19 0 +OP4 E01C1A 0 +OP4 E01C1B 0 +OP4 E01C1C 0 +OP4 E01C1D 0 +OP4 E01C1E 0 +OP4 E01C1F 0 +OP4 E01C20 0 +OP4 E01C21 0 +OP4 E01C22 0 +OP4 E01C23 0 +OP4 E01C24 0 +OP4 E01C25 0 +OP4 E01C26 0 +OP4 E01C27 0 +OP4 E01C28 0 +OP4 E01C29 0 +OP4 E01C2A 0 +OP4 E01C2B 0 +OP4 E01C2C 0 +OP4 E01C2D 0 +OP4 E01C2E 0 +OP4 E01C2F 0 +OP4 E01C30 0 +OP4 E01C31 0 +OP4 E01C32 0 +OP4 E01C33 0 +OP4 E01C34 0 +OP4 E01C35 0 +OP4 E01C36 0 +OP4 E01C37 0 +OP4 E01C38 0 +OP4 E01C39 0 +OP4 E01C3A 0 +OP4 E01C3B 0 +OP4 E01C3C 0 +OP4 E01C3D 0 +OP4 E01C3E 0 +OP4 E01C3F 0 +OP4 E01C40 0 +OP4 E01C41 0 +OP4 E01C42 0 +OP4 E01C43 0 +OP4 E01C44 0 +OP4 E01C45 0 +OP4 E01C46 0 +OP4 E01C47 0 +OP4 E01C48 0 +OP4 E01C49 0 +OP4 E01C4A 0 +OP4 E01C4B 0 +OP4 E01C4C 0 +OP4 E01C4D 0 +OP4 E01C4E 0 +OP4 E01C4F 0 +OP4 E01C50 0 +OP4 E01C51 0 +OP4 E01C52 0 +OP4 E01C53 0 +OP4 E01C54 0 +OP4 E01C55 0 +OP4 E01C56 0 +OP4 E01C57 0 +OP4 E01C58 0 +OP4 E01C59 0 +OP4 E01C5A 0 +OP4 E01C5B 0 +OP4 E01C5C 0 +OP4 E01C5D 0 +OP4 E01C5E 0 +OP4 E01C5F 0 +OP4 E01C60 0 +OP4 E01C61 0 +OP4 E01C62 0 +OP4 E01C63 0 +OP4 E01C64 0 +OP4 E01C65 0 +OP4 E01C66 0 +OP4 E01C67 0 +OP4 E01C68 0 +OP4 E01C69 0 +OP4 E01C6A 0 +OP4 E01C6B 0 +OP4 E01C6C 0 +OP4 E01C6D 0 +OP4 E01C6E 0 +OP4 E01C6F 0 +OP4 E01C70 0 +OP4 E01C71 0 +OP4 E01C72 0 +OP4 E01C73 0 +OP4 E01C74 0 +OP4 E01C75 0 +OP4 E01C76 0 +OP4 E01C77 0 +OP4 E01C78 0 +OP4 E01C79 0 +OP4 E01C7A 0 +OP4 E01C7B 0 +OP4 E01C7C 0 +OP4 E01C7D 0 +OP4 E01C7E 0 +OP4 E01C7F 0 +OP4 E01C80 0 +OP4 E01C81 0 +OP4 E01C82 0 +OP4 E01C83 0 +OP4 E01C84 0 +OP4 E01C85 0 +OP4 E01C86 0 +OP4 E01C87 0 +OP4 E01C88 0 +OP4 E01C89 0 +OP4 E01C8A 0 +OP4 E01C8B 0 +OP4 E01C8C 0 +OP4 E01C8D 0 +OP4 E01C8E 0 +OP4 E01C8F 0 +OP4 E01C90 0 +OP4 E01C91 0 +OP4 E01C92 0 +OP4 E01C93 0 +OP4 E01C94 0 +OP4 E01C95 0 +OP4 E01C96 0 +OP4 E01C97 0 +OP4 E01C98 0 +OP4 E01C99 0 +OP4 E01C9A 0 +OP4 E01C9B 0 +OP4 E01C9C 0 +OP4 E01C9D 0 +OP4 E01C9E 0 +OP4 E01C9F 0 +OP4 E01CA0 0 +OP4 E01CA1 0 +OP4 E01CA2 0 +OP4 E01CA3 0 +OP4 E01CA4 0 +OP4 E01CA5 0 +OP4 E01CA6 0 +OP4 E01CA7 0 +OP4 E01CA8 0 +OP4 E01CA9 0 +OP4 E01CAA 0 +OP4 E01CAB 0 +OP4 E01CAC 0 +OP4 E01CAD 0 +OP4 E01CAE 0 +OP4 E01CAF 0 +OP4 E01CB0 0 +OP4 E01CB1 0 +OP4 E01CB2 0 +OP4 E01CB3 0 +OP4 E01CB4 0 +OP4 E01CB5 0 +OP4 E01CB6 0 +OP4 E01CB7 0 +OP4 E01CB8 0 +OP4 E01CB9 0 +OP4 E01CBA 0 +OP4 E01CBB 0 +OP4 E01CBC 0 +OP4 E01CBD 0 +OP4 E01CBE 0 +OP4 E01CBF 0 +OP4 E01CC0 0 +OP4 E01CC1 0 +OP4 E01CC2 0 +OP4 E01CC3 0 +OP4 E01CC4 0 +OP4 E01CC5 0 +OP4 E01CC6 0 +OP4 E01CC7 0 +OP4 E01CC8 0 +OP4 E01CC9 0 +OP4 E01CCA 0 +OP4 E01CCB 0 +OP4 E01CCC 0 +OP4 E01CCD 0 +OP4 E01CCE 0 +OP4 E01CCF 0 +OP4 E01CD0 0 +OP4 E01CD1 0 +OP4 E01CD2 0 +OP4 E01CD3 0 +OP4 E01CD4 0 +OP4 E01CD5 0 +OP4 E01CD6 0 +OP4 E01CD7 0 +OP4 E01CD8 0 +OP4 E01CD9 0 +OP4 E01CDA 0 +OP4 E01CDB 0 +OP4 E01CDC 0 +OP4 E01CDD 0 +OP4 E01CDE 0 +OP4 E01CDF 0 +OP4 E01CE0 0 +OP4 E01CE1 0 +OP4 E01CE2 0 +OP4 E01CE3 0 +OP4 E01CE4 0 +OP4 E01CE5 0 +OP4 E01CE6 0 +OP4 E01CE7 0 +OP4 E01CE8 0 +OP4 E01CE9 0 +OP4 E01CEA 0 +OP4 E01CEB 0 +OP4 E01CEC 0 +OP4 E01CED 0 +OP4 E01CEE 0 +OP4 E01CEF 0 +OP4 E01CF0 0 +OP4 E01CF1 0 +OP4 E01CF2 0 +OP4 E01CF3 0 +OP4 E01CF4 0 +OP4 E01CF5 0 +OP4 E01CF6 0 +OP4 E01CF7 0 +OP4 E01CF8 0 +OP4 E01CF9 0 +OP4 E01CFA 0 +OP4 E01CFB 0 +OP4 E01CFC 0 +OP4 E01CFD 0 +OP4 E01CFE 0 +OP4 E01CFF 0 +OP4 E01D00 0 +OP4 E01D01 0 +OP4 E01D02 0 +OP4 E01D03 0 +OP4 E01D04 0 +OP4 E01D05 0 +OP4 E01D06 0 +OP4 E01D07 0 +OP4 E01D08 0 +OP4 E01D09 0 +OP4 E01D0A 0 +OP4 E01D0B 0 +OP4 E01D0C 0 +OP4 E01D0D 0 +OP4 E01D0E 0 +OP4 E01D0F 0 +OP4 E01D10 0 +OP4 E01D11 0 +OP4 E01D12 0 +OP4 E01D13 0 +OP4 E01D14 0 +OP4 E01D15 0 +OP4 E01D16 0 +OP4 E01D17 0 +OP4 E01D18 0 +OP4 E01D19 0 +OP4 E01D1A 0 +OP4 E01D1B 0 +OP4 E01D1C 0 +OP4 E01D1D 0 +OP4 E01D1E 0 +OP4 E01D1F 0 +OP4 E01D20 0 +OP4 E01D21 0 +OP4 E01D22 0 +OP4 E01D23 0 +OP4 E01D24 0 +OP4 E01D25 0 +OP4 E01D26 0 +OP4 E01D27 0 +OP4 E01D28 0 +OP4 E01D29 0 +OP4 E01D2A 0 +OP4 E01D2B 0 +OP4 E01D2C 0 +OP4 E01D2D 0 +OP4 E01D2E 0 +OP4 E01D2F 0 +OP4 E01D30 0 +OP4 E01D31 0 +OP4 E01D32 0 +OP4 E01D33 0 +OP4 E01D34 0 +OP4 E01D35 0 +OP4 E01D36 0 +OP4 E01D37 0 +OP4 E01D38 0 +OP4 E01D39 0 +OP4 E01D3A 0 +OP4 E01D3B 0 +OP4 E01D3C 0 +OP4 E01D3D 0 +OP4 E01D3E 0 +OP4 E01D3F 0 +OP4 E01D40 0 +OP4 E01D41 0 +OP4 E01D42 0 +OP4 E01D43 0 +OP4 E01D44 0 +OP4 E01D45 0 +OP4 E01D46 0 +OP4 E01D47 0 +OP4 E01D48 0 +OP4 E01D49 0 +OP4 E01D4A 0 +OP4 E01D4B 0 +OP4 E01D4C 0 +OP4 E01D4D 0 +OP4 E01D4E 0 +OP4 E01D4F 0 +OP4 E01D50 0 +OP4 E01D51 0 +OP4 E01D52 0 +OP4 E01D53 0 +OP4 E01D54 0 +OP4 E01D55 0 +OP4 E01D56 0 +OP4 E01D57 0 +OP4 E01D58 0 +OP4 E01D59 0 +OP4 E01D5A 0 +OP4 E01D5B 0 +OP4 E01D5C 0 +OP4 E01D5D 0 +OP4 E01D5E 0 +OP4 E01D5F 0 +OP4 E01D60 0 +OP4 E01D61 0 +OP4 E01D62 0 +OP4 E01D63 0 +OP4 E01D64 0 +OP4 E01D65 0 +OP4 E01D66 0 +OP4 E01D67 0 +OP4 E01D68 0 +OP4 E01D69 0 +OP4 E01D6A 0 +OP4 E01D6B 0 +OP4 E01D6C 0 +OP4 E01D6D 0 +OP4 E01D6E 0 +OP4 E01D6F 0 +OP4 E01D70 0 +OP4 E01D71 0 +OP4 E01D72 0 +OP4 E01D73 0 +OP4 E01D74 0 +OP4 E01D75 0 +OP4 E01D76 0 +OP4 E01D77 0 +OP4 E01D78 0 +OP4 E01D79 0 +OP4 E01D7A 0 +OP4 E01D7B 0 +OP4 E01D7C 0 +OP4 E01D7D 0 +OP4 E01D7E 0 +OP4 E01D7F 0 +OP4 E01D80 0 +OP4 E01D81 0 +OP4 E01D82 0 +OP4 E01D83 0 +OP4 E01D84 0 +OP4 E01D85 0 +OP4 E01D86 0 +OP4 E01D87 0 +OP4 E01D88 0 +OP4 E01D89 0 +OP4 E01D8A 0 +OP4 E01D8B 0 +OP4 E01D8C 0 +OP4 E01D8D 0 +OP4 E01D8E 0 +OP4 E01D8F 0 +OP4 E01D90 0 +OP4 E01D91 0 +OP4 E01D92 0 +OP4 E01D93 0 +OP4 E01D94 0 +OP4 E01D95 0 +OP4 E01D96 0 +OP4 E01D97 0 +OP4 E01D98 0 +OP4 E01D99 0 +OP4 E01D9A 0 +OP4 E01D9B 0 +OP4 E01D9C 0 +OP4 E01D9D 0 +OP4 E01D9E 0 +OP4 E01D9F 0 +OP4 E01DA0 0 +OP4 E01DA1 0 +OP4 E01DA2 0 +OP4 E01DA3 0 +OP4 E01DA4 0 +OP4 E01DA5 0 +OP4 E01DA6 0 +OP4 E01DA7 0 +OP4 E01DA8 0 +OP4 E01DA9 0 +OP4 E01DAA 0 +OP4 E01DAB 0 +OP4 E01DAC 0 +OP4 E01DAD 0 +OP4 E01DAE 0 +OP4 E01DAF 0 +OP4 E01DB0 0 +OP4 E01DB1 0 +OP4 E01DB2 0 +OP4 E01DB3 0 +OP4 E01DB4 0 +OP4 E01DB5 0 +OP4 E01DB6 0 +OP4 E01DB7 0 +OP4 E01DB8 0 +OP4 E01DB9 0 +OP4 E01DBA 0 +OP4 E01DBB 0 +OP4 E01DBC 0 +OP4 E01DBD 0 +OP4 E01DBE 0 +OP4 E01DBF 0 +OP4 E01DC0 0 +OP4 E01DC1 0 +OP4 E01DC2 0 +OP4 E01DC3 0 +OP4 E01DC4 0 +OP4 E01DC5 0 +OP4 E01DC6 0 +OP4 E01DC7 0 +OP4 E01DC8 0 +OP4 E01DC9 0 +OP4 E01DCA 0 +OP4 E01DCB 0 +OP4 E01DCC 0 +OP4 E01DCD 0 +OP4 E01DCE 0 +OP4 E01DCF 0 +OP4 E01DD0 0 +OP4 E01DD1 0 +OP4 E01DD2 0 +OP4 E01DD3 0 +OP4 E01DD4 0 +OP4 E01DD5 0 +OP4 E01DD6 0 +OP4 E01DD7 0 +OP4 E01DD8 0 +OP4 E01DD9 0 +OP4 E01DDA 0 +OP4 E01DDB 0 +OP4 E01DDC 0 +OP4 E01DDD 0 +OP4 E01DDE 0 +OP4 E01DDF 0 +OP4 E01DE0 0 +OP4 E01DE1 0 +OP4 E01DE2 0 +OP4 E01DE3 0 +OP4 E01DE4 0 +OP4 E01DE5 0 +OP4 E01DE6 0 +OP4 E01DE7 0 +OP4 E01DE8 0 +OP4 E01DE9 0 +OP4 E01DEA 0 +OP4 E01DEB 0 +OP4 E01DEC 0 +OP4 E01DED 0 +OP4 E01DEE 0 +OP4 E01DEF 0 +OP4 E01DF0 0 +OP4 E01DF1 0 +OP4 E01DF2 0 +OP4 E01DF3 0 +OP4 E01DF4 0 +OP4 E01DF5 0 +OP4 E01DF6 0 +OP4 E01DF7 0 +OP4 E01DF8 0 +OP4 E01DF9 0 +OP4 E01DFA 0 +OP4 E01DFB 0 +OP4 E01DFC 0 +OP4 E01DFD 0 +OP4 E01DFE 0 +OP4 E01DFF 0 +OP4 E01E00 0 +OP4 E01E01 0 +OP4 E01E02 0 +OP4 E01E03 0 +OP4 E01E04 0 +OP4 E01E05 0 +OP4 E01E06 0 +OP4 E01E07 0 +OP4 E01E08 0 +OP4 E01E09 0 +OP4 E01E0A 0 +OP4 E01E0B 0 +OP4 E01E0C 0 +OP4 E01E0D 0 +OP4 E01E0E 0 +OP4 E01E0F 0 +OP4 E01E10 0 +OP4 E01E11 0 +OP4 E01E12 0 +OP4 E01E13 0 +OP4 E01E14 0 +OP4 E01E15 0 +OP4 E01E16 0 +OP4 E01E17 0 +OP4 E01E18 0 +OP4 E01E19 0 +OP4 E01E1A 0 +OP4 E01E1B 0 +OP4 E01E1C 0 +OP4 E01E1D 0 +OP4 E01E1E 0 +OP4 E01E1F 0 +OP4 E01E20 0 +OP4 E01E21 0 +OP4 E01E22 0 +OP4 E01E23 0 +OP4 E01E24 0 +OP4 E01E25 0 +OP4 E01E26 0 +OP4 E01E27 0 +OP4 E01E28 0 +OP4 E01E29 0 +OP4 E01E2A 0 +OP4 E01E2B 0 +OP4 E01E2C 0 +OP4 E01E2D 0 +OP4 E01E2E 0 +OP4 E01E2F 0 +OP4 E01E30 0 +OP4 E01E31 0 +OP4 E01E32 0 +OP4 E01E33 0 +OP4 E01E34 0 +OP4 E01E35 0 +OP4 E01E36 0 +OP4 E01E37 0 +OP4 E01E38 0 +OP4 E01E39 0 +OP4 E01E3A 0 +OP4 E01E3B 0 +OP4 E01E3C 0 +OP4 E01E3D 0 +OP4 E01E3E 0 +OP4 E01E3F 0 +OP4 E01E40 0 +OP4 E01E41 0 +OP4 E01E42 0 +OP4 E01E43 0 +OP4 E01E44 0 +OP4 E01E45 0 +OP4 E01E46 0 +OP4 E01E47 0 +OP4 E01E48 0 +OP4 E01E49 0 +OP4 E01E4A 0 +OP4 E01E4B 0 +OP4 E01E4C 0 +OP4 E01E4D 0 +OP4 E01E4E 0 +OP4 E01E4F 0 +OP4 E01E50 0 +OP4 E01E51 0 +OP4 E01E52 0 +OP4 E01E53 0 +OP4 E01E54 0 +OP4 E01E55 0 +OP4 E01E56 0 +OP4 E01E57 0 +OP4 E01E58 0 +OP4 E01E59 0 +OP4 E01E5A 0 +OP4 E01E5B 0 +OP4 E01E5C 0 +OP4 E01E5D 0 +OP4 E01E5E 0 +OP4 E01E5F 0 +OP4 E01E60 0 +OP4 E01E61 0 +OP4 E01E62 0 +OP4 E01E63 0 +OP4 E01E64 0 +OP4 E01E65 0 +OP4 E01E66 0 +OP4 E01E67 0 +OP4 E01E68 0 +OP4 E01E69 0 +OP4 E01E6A 0 +OP4 E01E6B 0 +OP4 E01E6C 0 +OP4 E01E6D 0 +OP4 E01E6E 0 +OP4 E01E6F 0 +OP4 E01E70 0 +OP4 E01E71 0 +OP4 E01E72 0 +OP4 E01E73 0 +OP4 E01E74 0 +OP4 E01E75 0 +OP4 E01E76 0 +OP4 E01E77 0 +OP4 E01E78 0 +OP4 E01E79 0 +OP4 E01E7A 0 +OP4 E01E7B 0 +OP4 E01E7C 0 +OP4 E01E7D 0 +OP4 E01E7E 0 +OP4 E01E7F 0 +OP4 E01E80 0 +OP4 E01E81 0 +OP4 E01E82 0 +OP4 E01E83 0 +OP4 E01E84 0 +OP4 E01E85 0 +OP4 E01E86 0 +OP4 E01E87 0 +OP4 E01E88 0 +OP4 E01E89 0 +OP4 E01E8A 0 +OP4 E01E8B 0 +OP4 E01E8C 0 +OP4 E01E8D 0 +OP4 E01E8E 0 +OP4 E01E8F 0 +OP4 E01E90 0 +OP4 E01E91 0 +OP4 E01E92 0 +OP4 E01E93 0 +OP4 E01E94 0 +OP4 E01E95 0 +OP4 E01E96 0 +OP4 E01E97 0 +OP4 E01E98 0 +OP4 E01E99 0 +OP4 E01E9A 0 +OP4 E01E9B 0 +OP4 E01E9C 0 +OP4 E01E9D 0 +OP4 E01E9E 0 +OP4 E01E9F 0 +OP4 E01EA0 0 +OP4 E01EA1 0 +OP4 E01EA2 0 +OP4 E01EA3 0 +OP4 E01EA4 0 +OP4 E01EA5 0 +OP4 E01EA6 0 +OP4 E01EA7 0 +OP4 E01EA8 0 +OP4 E01EA9 0 +OP4 E01EAA 0 +OP4 E01EAB 0 +OP4 E01EAC 0 +OP4 E01EAD 0 +OP4 E01EAE 0 +OP4 E01EAF 0 +OP4 E01EB0 0 +OP4 E01EB1 0 +OP4 E01EB2 0 +OP4 E01EB3 0 +OP4 E01EB4 0 +OP4 E01EB5 0 +OP4 E01EB6 0 +OP4 E01EB7 0 +OP4 E01EB8 0 +OP4 E01EB9 0 +OP4 E01EBA 0 +OP4 E01EBB 0 +OP4 E01EBC 0 +OP4 E01EBD 0 +OP4 E01EBE 0 +OP4 E01EBF 0 +OP4 E01EC0 0 +OP4 E01EC1 0 +OP4 E01EC2 0 +OP4 E01EC3 0 +OP4 E01EC4 0 +OP4 E01EC5 0 +OP4 E01EC6 0 +OP4 E01EC7 0 +OP4 E01EC8 0 +OP4 E01EC9 0 +OP4 E01ECA 0 +OP4 E01ECB 0 +OP4 E01ECC 0 +OP4 E01ECD 0 +OP4 E01ECE 0 +OP4 E01ECF 0 +OP4 E01ED0 0 +OP4 E01ED1 0 +OP4 E01ED2 0 +OP4 E01ED3 0 +OP4 E01ED4 0 +OP4 E01ED5 0 +OP4 E01ED6 0 +OP4 E01ED7 0 +OP4 E01ED8 0 +OP4 E01ED9 0 +OP4 E01EDA 0 +OP4 E01EDB 0 +OP4 E01EDC 0 +OP4 E01EDD 0 +OP4 E01EDE 0 +OP4 E01EDF 0 +OP4 E01EE0 0 +OP4 E01EE1 0 +OP4 E01EE2 0 +OP4 E01EE3 0 +OP4 E01EE4 0 +OP4 E01EE5 0 +OP4 E01EE6 0 +OP4 E01EE7 0 +OP4 E01EE8 0 +OP4 E01EE9 0 +OP4 E01EEA 0 +OP4 E01EEB 0 +OP4 E01EEC 0 +OP4 E01EED 0 +OP4 E01EEE 0 +OP4 E01EEF 0 +OP4 E01EF0 0 +OP4 E01EF1 0 +OP4 E01EF2 0 +OP4 E01EF3 0 +OP4 E01EF4 0 +OP4 E01EF5 0 +OP4 E01EF6 0 +OP4 E01EF7 0 +OP4 E01EF8 0 +OP4 E01EF9 0 +OP4 E01EFA 0 +OP4 E01EFB 0 +OP4 E01EFC 0 +OP4 E01EFD 0 +OP4 E01EFE 0 +OP4 E01EFF 0 +OP4 E01F00 0 +OP4 E01F01 0 +OP4 E01F02 0 +OP4 E01F03 0 +OP4 E01F04 0 +OP4 E01F05 0 +OP4 E01F06 0 +OP4 E01F07 0 +OP4 E01F08 0 +OP4 E01F09 0 +OP4 E01F0A 0 +OP4 E01F0B 0 +OP4 E01F0C 0 +OP4 E01F0D 0 +OP4 E01F0E 0 +OP4 E01F0F 0 +OP4 E01F10 0 +OP4 E01F11 0 +OP4 E01F12 0 +OP4 E01F13 0 +OP4 E01F14 0 +OP4 E01F15 0 +OP4 E01F16 0 +OP4 E01F17 0 +OP4 E01F18 0 +OP4 E01F19 0 +OP4 E01F1A 0 +OP4 E01F1B 0 +OP4 E01F1C 0 +OP4 E01F1D 0 +OP4 E01F1E 0 +OP4 E01F1F 0 +OP4 E01F20 0 +OP4 E01F21 0 +OP4 E01F22 0 +OP4 E01F23 0 +OP4 E01F24 0 +OP4 E01F25 0 +OP4 E01F26 0 +OP4 E01F27 0 +OP4 E01F28 0 +OP4 E01F29 0 +OP4 E01F2A 0 +OP4 E01F2B 0 +OP4 E01F2C 0 +OP4 E01F2D 0 +OP4 E01F2E 0 +OP4 E01F2F 0 +OP4 E01F30 0 +OP4 E01F31 0 +OP4 E01F32 0 +OP4 E01F33 0 +OP4 E01F34 0 +OP4 E01F35 0 +OP4 E01F36 0 +OP4 E01F37 0 +OP4 E01F38 0 +OP4 E01F39 0 +OP4 E01F3A 0 +OP4 E01F3B 0 +OP4 E01F3C 0 +OP4 E01F3D 0 +OP4 E01F3E 0 +OP4 E01F3F 0 +OP4 E01F40 0 +OP4 E01F41 0 +OP4 E01F42 0 +OP4 E01F43 0 +OP4 E01F44 0 +OP4 E01F45 0 +OP4 E01F46 0 +OP4 E01F47 0 +OP4 E01F48 0 +OP4 E01F49 0 +OP4 E01F4A 0 +OP4 E01F4B 0 +OP4 E01F4C 0 +OP4 E01F4D 0 +OP4 E01F4E 0 +OP4 E01F4F 0 +OP4 E01F50 0 +OP4 E01F51 0 +OP4 E01F52 0 +OP4 E01F53 0 +OP4 E01F54 0 +OP4 E01F55 0 +OP4 E01F56 0 +OP4 E01F57 0 +OP4 E01F58 0 +OP4 E01F59 0 +OP4 E01F5A 0 +OP4 E01F5B 0 +OP4 E01F5C 0 +OP4 E01F5D 0 +OP4 E01F5E 0 +OP4 E01F5F 0 +OP4 E01F60 0 +OP4 E01F61 0 +OP4 E01F62 0 +OP4 E01F63 0 +OP4 E01F64 0 +OP4 E01F65 0 +OP4 E01F66 0 +OP4 E01F67 0 +OP4 E01F68 0 +OP4 E01F69 0 +OP4 E01F6A 0 +OP4 E01F6B 0 +OP4 E01F6C 0 +OP4 E01F6D 0 +OP4 E01F6E 0 +OP4 E01F6F 0 +OP4 E01F70 0 +OP4 E01F71 0 +OP4 E01F72 0 +OP4 E01F73 0 +OP4 E01F74 0 +OP4 E01F75 0 +OP4 E01F76 0 +OP4 E01F77 0 +OP4 E01F78 0 +OP4 E01F79 0 +OP4 E01F7A 0 +OP4 E01F7B 0 +OP4 E01F7C 0 +OP4 E01F7D 0 +OP4 E01F7E 0 +OP4 E01F7F 0 +OP4 E01F80 0 +OP4 E01F81 0 +OP4 E01F82 0 +OP4 E01F83 0 +OP4 E01F84 0 +OP4 E01F85 0 +OP4 E01F86 0 +OP4 E01F87 0 +OP4 E01F88 0 +OP4 E01F89 0 +OP4 E01F8A 0 +OP4 E01F8B 0 +OP4 E01F8C 0 +OP4 E01F8D 0 +OP4 E01F8E 0 +OP4 E01F8F 0 +OP4 E01F90 0 +OP4 E01F91 0 +OP4 E01F92 0 +OP4 E01F93 0 +OP4 E01F94 0 +OP4 E01F95 0 +OP4 E01F96 0 +OP4 E01F97 0 +OP4 E01F98 0 +OP4 E01F99 0 +OP4 E01F9A 0 +OP4 E01F9B 0 +OP4 E01F9C 0 +OP4 E01F9D 0 +OP4 E01F9E 0 +OP4 E01F9F 0 +OP4 E01FA0 0 +OP4 E01FA1 0 +OP4 E01FA2 0 +OP4 E01FA3 0 +OP4 E01FA4 0 +OP4 E01FA5 0 +OP4 E01FA6 0 +OP4 E01FA7 0 +OP4 E01FA8 0 +OP4 E01FA9 0 +OP4 E01FAA 0 +OP4 E01FAB 0 +OP4 E01FAC 0 +OP4 E01FAD 0 +OP4 E01FAE 0 +OP4 E01FAF 0 +OP4 E01FB0 0 +OP4 E01FB1 0 +OP4 E01FB2 0 +OP4 E01FB3 0 +OP4 E01FB4 0 +OP4 E01FB5 0 +OP4 E01FB6 0 +OP4 E01FB7 0 +OP4 E01FB8 0 +OP4 E01FB9 0 +OP4 E01FBA 0 +OP4 E01FBB 0 +OP4 E01FBC 0 +OP4 E01FBD 0 +OP4 E01FBE 0 +OP4 E01FBF 0 +OP4 E01FC0 0 +OP4 E01FC1 0 +OP4 E01FC2 0 +OP4 E01FC3 0 +OP4 E01FC4 0 +OP4 E01FC5 0 +OP4 E01FC6 0 +OP4 E01FC7 0 +OP4 E01FC8 0 +OP4 E01FC9 0 +OP4 E01FCA 0 +OP4 E01FCB 0 +OP4 E01FCC 0 +OP4 E01FCD 0 +OP4 E01FCE 0 +OP4 E01FCF 0 +OP4 E01FD0 0 +OP4 E01FD1 0 +OP4 E01FD2 0 +OP4 E01FD3 0 +OP4 E01FD4 0 +OP4 E01FD5 0 +OP4 E01FD6 0 +OP4 E01FD7 0 +OP4 E01FD8 0 +OP4 E01FD9 0 +OP4 E01FDA 0 +OP4 E01FDB 0 +OP4 E01FDC 0 +OP4 E01FDD 0 +OP4 E01FDE 0 +OP4 E01FDF 0 +OP4 E01FE0 0 +OP4 E01FE1 0 +OP4 E01FE2 0 +OP4 E01FE3 0 +OP4 E01FE4 0 +OP4 E01FE5 0 +OP4 E01FE6 0 +OP4 E01FE7 0 +OP4 E01FE8 0 +OP4 E01FE9 0 +OP4 E01FEA 0 +OP4 E01FEB 0 +OP4 E01FEC 0 +OP4 E01FED 0 +OP4 E01FEE 0 +OP4 E01FEF 0 +OP4 E01FF0 0 +OP4 E01FF1 0 +OP4 E01FF2 0 +OP4 E01FF3 0 +OP4 E01FF4 0 +OP4 E01FF5 0 +OP4 E01FF6 0 +OP4 E01FF7 0 +OP4 E01FF8 0 +OP4 E01FF9 0 +OP4 E01FFA 0 +OP4 E01FFB 0 +OP4 E01FFC 0 +OP4 E01FFD 0 +OP4 E01FFE 0 +OP4 E01FFF 0 +OP4 E02000 0 +OP4 E02001 0 +OP4 E02002 0 +OP4 E02003 0 +OP4 E02004 0 +OP4 E02005 0 +OP4 E02006 0 +OP4 E02007 0 +OP4 E02008 0 +OP4 E02009 0 +OP4 E0200A 0 +OP4 E0200B 0 +OP4 E0200C 0 +OP4 E0200D 0 +OP4 E0200E 0 +OP4 E0200F 0 +OP4 E02010 0 +OP4 E02011 0 +OP4 E02012 0 +OP4 E02013 0 +OP4 E02014 0 +OP4 E02015 0 +OP4 E02016 0 +OP4 E02017 0 +OP4 E02018 0 +OP4 E02019 0 +OP4 E0201A 0 +OP4 E0201B 0 +OP4 E0201C 0 +OP4 E0201D 0 +OP4 E0201E 0 +OP4 E0201F 0 +OP4 E02020 0 +OP4 E02021 0 +OP4 E02022 0 +OP4 E02023 0 +OP4 E02024 0 +OP4 E02025 0 +OP4 E02026 0 +OP4 E02027 0 +OP4 E02028 0 +OP4 E02029 0 +OP4 E0202A 0 +OP4 E0202B 0 +OP4 E0202C 0 +OP4 E0202D 0 +OP4 E0202E 0 +OP4 E0202F 0 +OP4 E02030 0 +OP4 E02031 0 +OP4 E02032 0 +OP4 E02033 0 +OP4 E02034 0 +OP4 E02035 0 +OP4 E02036 0 +OP4 E02037 0 +OP4 E02038 0 +OP4 E02039 0 +OP4 E0203A 0 +OP4 E0203B 0 +OP4 E0203C 0 +OP4 E0203D 0 +OP4 E0203E 0 +OP4 E0203F 0 +OP4 E02040 0 +OP4 E02041 0 +OP4 E02042 0 +OP4 E02043 0 +OP4 E02044 0 +OP4 E02045 0 +OP4 E02046 0 +OP4 E02047 0 +OP4 E02048 0 +OP4 E02049 0 +OP4 E0204A 0 +OP4 E0204B 0 +OP4 E0204C 0 +OP4 E0204D 0 +OP4 E0204E 0 +OP4 E0204F 0 +OP4 E02050 0 +OP4 E02051 0 +OP4 E02052 0 +OP4 E02053 0 +OP4 E02054 0 +OP4 E02055 0 +OP4 E02056 0 +OP4 E02057 0 +OP4 E02058 0 +OP4 E02059 0 +OP4 E0205A 0 +OP4 E0205B 0 +OP4 E0205C 0 +OP4 E0205D 0 +OP4 E0205E 0 +OP4 E0205F 0 +OP4 E02060 0 +OP4 E02061 0 +OP4 E02062 0 +OP4 E02063 0 +OP4 E02064 0 +OP4 E02065 0 +OP4 E02066 0 +OP4 E02067 0 +OP4 E02068 0 +OP4 E02069 0 +OP4 E0206A 0 +OP4 E0206B 0 +OP4 E0206C 0 +OP4 E0206D 0 +OP4 E0206E 0 +OP4 E0206F 0 +OP4 E02070 0 +OP4 E02071 0 +OP4 E02072 0 +OP4 E02073 0 +OP4 E02074 0 +OP4 E02075 0 +OP4 E02076 0 +OP4 E02077 0 +OP4 E02078 0 +OP4 E02079 0 +OP4 E0207A 0 +OP4 E0207B 0 +OP4 E0207C 0 +OP4 E0207D 0 +OP4 E0207E 0 +OP4 E0207F 0 +OP4 E02080 0 +OP4 E02081 0 +OP4 E02082 0 +OP4 E02083 0 +OP4 E02084 0 +OP4 E02085 0 +OP4 E02086 0 +OP4 E02087 0 +OP4 E02088 0 +OP4 E02089 0 +OP4 E0208A 0 +OP4 E0208B 0 +OP4 E0208C 0 +OP4 E0208D 0 +OP4 E0208E 0 +OP4 E0208F 0 +OP4 E02090 0 +OP4 E02091 0 +OP4 E02092 0 +OP4 E02093 0 +OP4 E02094 0 +OP4 E02095 0 +OP4 E02096 0 +OP4 E02097 0 +OP4 E02098 0 +OP4 E02099 0 +OP4 E0209A 0 +OP4 E0209B 0 +OP4 E0209C 0 +OP4 E0209D 0 +OP4 E0209E 0 +OP4 E0209F 0 +OP4 E020A0 0 +OP4 E020A1 0 +OP4 E020A2 0 +OP4 E020A3 0 +OP4 E020A4 0 +OP4 E020A5 0 +OP4 E020A6 0 +OP4 E020A7 0 +OP4 E020A8 0 +OP4 E020A9 0 +OP4 E020AA 0 +OP4 E020AB 0 +OP4 E020AC 0 +OP4 E020AD 0 +OP4 E020AE 0 +OP4 E020AF 0 +OP4 E020B0 0 +OP4 E020B1 0 +OP4 E020B2 0 +OP4 E020B3 0 +OP4 E020B4 0 +OP4 E020B5 0 +OP4 E020B6 0 +OP4 E020B7 0 +OP4 E020B8 0 +OP4 E020B9 0 +OP4 E020BA 0 +OP4 E020BB 0 +OP4 E020BC 0 +OP4 E020BD 0 +OP4 E020BE 0 +OP4 E020BF 0 +OP4 E020C0 0 +OP4 E020C1 0 +OP4 E020C2 0 +OP4 E020C3 0 +OP4 E020C4 0 +OP4 E020C5 0 +OP4 E020C6 0 +OP4 E020C7 0 +OP4 E020C8 0 +OP4 E020C9 0 +OP4 E020CA 0 +OP4 E020CB 0 +OP4 E020CC 0 +OP4 E020CD 0 +OP4 E020CE 0 +OP4 E020CF 0 +OP4 E020D0 0 +OP4 E020D1 0 +OP4 E020D2 0 +OP4 E020D3 0 +OP4 E020D4 0 +OP4 E020D5 0 +OP4 E020D6 0 +OP4 E020D7 0 +OP4 E020D8 0 +OP4 E020D9 0 +OP4 E020DA 0 +OP4 E020DB 0 +OP4 E020DC 0 +OP4 E020DD 0 +OP4 E020DE 0 +OP4 E020DF 0 +OP4 E020E0 0 +OP4 E020E1 0 +OP4 E020E2 0 +OP4 E020E3 0 +OP4 E020E4 0 +OP4 E020E5 0 +OP4 E020E6 0 +OP4 E020E7 0 +OP4 E020E8 0 +OP4 E020E9 0 +OP4 E020EA 0 +OP4 E020EB 0 +OP4 E020EC 0 +OP4 E020ED 0 +OP4 E020EE 0 +OP4 E020EF 0 +OP4 E020F0 0 +OP4 E020F1 0 +OP4 E020F2 0 +OP4 E020F3 0 +OP4 E020F4 0 +OP4 E020F5 0 +OP4 E020F6 0 +OP4 E020F7 0 +OP4 E020F8 0 +OP4 E020F9 0 +OP4 E020FA 0 +OP4 E020FB 0 +OP4 E020FC 0 +OP4 E020FD 0 +OP4 E020FE 0 +OP4 E020FF 0 +OP4 E02100 0 +OP4 E02101 0 +OP4 E02102 0 +OP4 E02103 0 +OP4 E02104 0 +OP4 E02105 0 +OP4 E02106 0 +OP4 E02107 0 +OP4 E02108 0 +OP4 E02109 0 +OP4 E0210A 0 +OP4 E0210B 0 +OP4 E0210C 0 +OP4 E0210D 0 +OP4 E0210E 0 +OP4 E0210F 0 +OP4 E02110 0 +OP4 E02111 0 +OP4 E02112 0 +OP4 E02113 0 +OP4 E02114 0 +OP4 E02115 0 +OP4 E02116 0 +OP4 E02117 0 +OP4 E02118 0 +OP4 E02119 0 +OP4 E0211A 0 +OP4 E0211B 0 +OP4 E0211C 0 +OP4 E0211D 0 +OP4 E0211E 0 +OP4 E0211F 0 +OP4 E02120 0 +OP4 E02121 0 +OP4 E02122 0 +OP4 E02123 0 +OP4 E02124 0 +OP4 E02125 0 +OP4 E02126 0 +OP4 E02127 0 +OP4 E02128 0 +OP4 E02129 0 +OP4 E0212A 0 +OP4 E0212B 0 +OP4 E0212C 0 +OP4 E0212D 0 +OP4 E0212E 0 +OP4 E0212F 0 +OP4 E02130 0 +OP4 E02131 0 +OP4 E02132 0 +OP4 E02133 0 +OP4 E02134 0 +OP4 E02135 0 +OP4 E02136 0 +OP4 E02137 0 +OP4 E02138 0 +OP4 E02139 0 +OP4 E0213A 0 +OP4 E0213B 0 +OP4 E0213C 0 +OP4 E0213D 0 +OP4 E0213E 0 +OP4 E0213F 0 +OP4 E02140 0 +OP4 E02141 0 +OP4 E02142 0 +OP4 E02143 0 +OP4 E02144 0 +OP4 E02145 0 +OP4 E02146 0 +OP4 E02147 0 +OP4 E02148 0 +OP4 E02149 0 +OP4 E0214A 0 +OP4 E0214B 0 +OP4 E0214C 0 +OP4 E0214D 0 +OP4 E0214E 0 +OP4 E0214F 0 +OP4 E02150 0 +OP4 E02151 0 +OP4 E02152 0 +OP4 E02153 0 +OP4 E02154 0 +OP4 E02155 0 +OP4 E02156 0 +OP4 E02157 0 +OP4 E02158 0 +OP4 E02159 0 +OP4 E0215A 0 +OP4 E0215B 0 +OP4 E0215C 0 +OP4 E0215D 0 +OP4 E0215E 0 +OP4 E0215F 0 +OP4 E02160 0 +OP4 E02161 0 +OP4 E02162 0 +OP4 E02163 0 +OP4 E02164 0 +OP4 E02165 0 +OP4 E02166 0 +OP4 E02167 0 +OP4 E02168 0 +OP4 E02169 0 +OP4 E0216A 0 +OP4 E0216B 0 +OP4 E0216C 0 +OP4 E0216D 0 +OP4 E0216E 0 +OP4 E0216F 0 +OP4 E02170 0 +OP4 E02171 0 +OP4 E02172 0 +OP4 E02173 0 +OP4 E02174 0 +OP4 E02175 0 +OP4 E02176 0 +OP4 E02177 0 +OP4 E02178 0 +OP4 E02179 0 +OP4 E0217A 0 +OP4 E0217B 0 +OP4 E0217C 0 +OP4 E0217D 0 +OP4 E0217E 0 +OP4 E0217F 0 +OP4 E02180 0 +OP4 E02181 0 +OP4 E02182 0 +OP4 E02183 0 +OP4 E02184 0 +OP4 E02185 0 +OP4 E02186 0 +OP4 E02187 0 +OP4 E02188 0 +OP4 E02189 0 +OP4 E0218A 0 +OP4 E0218B 0 +OP4 E0218C 0 +OP4 E0218D 0 +OP4 E0218E 0 +OP4 E0218F 0 +OP4 E02190 0 +OP4 E02191 0 +OP4 E02192 0 +OP4 E02193 0 +OP4 E02194 0 +OP4 E02195 0 +OP4 E02196 0 +OP4 E02197 0 +OP4 E02198 0 +OP4 E02199 0 +OP4 E0219A 0 +OP4 E0219B 0 +OP4 E0219C 0 +OP4 E0219D 0 +OP4 E0219E 0 +OP4 E0219F 0 +OP4 E021A0 0 +OP4 E021A1 0 +OP4 E021A2 0 +OP4 E021A3 0 +OP4 E021A4 0 +OP4 E021A5 0 +OP4 E021A6 0 +OP4 E021A7 0 +OP4 E021A8 0 +OP4 E021A9 0 +OP4 E021AA 0 +OP4 E021AB 0 +OP4 E021AC 0 +OP4 E021AD 0 +OP4 E021AE 0 +OP4 E021AF 0 +OP4 E021B0 0 +OP4 E021B1 0 +OP4 E021B2 0 +OP4 E021B3 0 +OP4 E021B4 0 +OP4 E021B5 0 +OP4 E021B6 0 +OP4 E021B7 0 +OP4 E021B8 0 +OP4 E021B9 0 +OP4 E021BA 0 +OP4 E021BB 0 +OP4 E021BC 0 +OP4 E021BD 0 +OP4 E021BE 0 +OP4 E021BF 0 +OP4 E021C0 0 +OP4 E021C1 0 +OP4 E021C2 0 +OP4 E021C3 0 +OP4 E021C4 0 +OP4 E021C5 0 +OP4 E021C6 0 +OP4 E021C7 0 +OP4 E021C8 0 +OP4 E021C9 0 +OP4 E021CA 0 +OP4 E021CB 0 +OP4 E021CC 0 +OP4 E021CD 0 +OP4 E021CE 0 +OP4 E021CF 0 +OP4 E021D0 0 +OP4 E021D1 0 +OP4 E021D2 0 +OP4 E021D3 0 +OP4 E021D4 0 +OP4 E021D5 0 +OP4 E021D6 0 +OP4 E021D7 0 +OP4 E021D8 0 +OP4 E021D9 0 +OP4 E021DA 0 +OP4 E021DB 0 +OP4 E021DC 0 +OP4 E021DD 0 +OP4 E021DE 0 +OP4 E021DF 0 +OP4 E021E0 0 +OP4 E021E1 0 +OP4 E021E2 0 +OP4 E021E3 0 +OP4 E021E4 0 +OP4 E021E5 0 +OP4 E021E6 0 +OP4 E021E7 0 +OP4 E021E8 0 +OP4 E021E9 0 +OP4 E021EA 0 +OP4 E021EB 0 +OP4 E021EC 0 +OP4 E021ED 0 +OP4 E021EE 0 +OP4 E021EF 0 +OP4 E021F0 0 +OP4 E021F1 0 +OP4 E021F2 0 +OP4 E021F3 0 +OP4 E021F4 0 +OP4 E021F5 0 +OP4 E021F6 0 +OP4 E021F7 0 +OP4 E021F8 0 +OP4 E021F9 0 +OP4 E021FA 0 +OP4 E021FB 0 +OP4 E021FC 0 +OP4 E021FD 0 +OP4 E021FE 0 +OP4 E021FF 0 +OP4 E02200 0 +OP4 E02201 0 +OP4 E02202 0 +OP4 E02203 0 +OP4 E02204 0 +OP4 E02205 0 +OP4 E02206 0 +OP4 E02207 0 +OP4 E02208 0 +OP4 E02209 0 +OP4 E0220A 0 +OP4 E0220B 0 +OP4 E0220C 0 +OP4 E0220D 0 +OP4 E0220E 0 +OP4 E0220F 0 +OP4 E02210 0 +OP4 E02211 0 +OP4 E02212 0 +OP4 E02213 0 +OP4 E02214 0 +OP4 E02215 0 +OP4 E02216 0 +OP4 E02217 0 +OP4 E02218 0 +OP4 E02219 0 +OP4 E0221A 0 +OP4 E0221B 0 +OP4 E0221C 0 +OP4 E0221D 0 +OP4 E0221E 0 +OP4 E0221F 0 +OP4 E02220 0 +OP4 E02221 0 +OP4 E02222 0 +OP4 E02223 0 +OP4 E02224 0 +OP4 E02225 0 +OP4 E02226 0 +OP4 E02227 0 +OP4 E02228 0 +OP4 E02229 0 +OP4 E0222A 0 +OP4 E0222B 0 +OP4 E0222C 0 +OP4 E0222D 0 +OP4 E0222E 0 +OP4 E0222F 0 +OP4 E02230 0 +OP4 E02231 0 +OP4 E02232 0 +OP4 E02233 0 +OP4 E02234 0 +OP4 E02235 0 +OP4 E02236 0 +OP4 E02237 0 +OP4 E02238 0 +OP4 E02239 0 +OP4 E0223A 0 +OP4 E0223B 0 +OP4 E0223C 0 +OP4 E0223D 0 +OP4 E0223E 0 +OP4 E0223F 0 +OP4 E02240 0 +OP4 E02241 0 +OP4 E02242 0 +OP4 E02243 0 +OP4 E02244 0 +OP4 E02245 0 +OP4 E02246 0 +OP4 E02247 0 +OP4 E02248 0 +OP4 E02249 0 +OP4 E0224A 0 +OP4 E0224B 0 +OP4 E0224C 0 +OP4 E0224D 0 +OP4 E0224E 0 +OP4 E0224F 0 +OP4 E02250 0 +OP4 E02251 0 +OP4 E02252 0 +OP4 E02253 0 +OP4 E02254 0 +OP4 E02255 0 +OP4 E02256 0 +OP4 E02257 0 +OP4 E02258 0 +OP4 E02259 0 +OP4 E0225A 0 +OP4 E0225B 0 +OP4 E0225C 0 +OP4 E0225D 0 +OP4 E0225E 0 +OP4 E0225F 0 +OP4 E02260 0 +OP4 E02261 0 +OP4 E02262 0 +OP4 E02263 0 +OP4 E02264 0 +OP4 E02265 0 +OP4 E02266 0 +OP4 E02267 0 +OP4 E02268 0 +OP4 E02269 0 +OP4 E0226A 0 +OP4 E0226B 0 +OP4 E0226C 0 +OP4 E0226D 0 +OP4 E0226E 0 +OP4 E0226F 0 +OP4 E02270 0 +OP4 E02271 0 +OP4 E02272 0 +OP4 E02273 0 +OP4 E02274 0 +OP4 E02275 0 +OP4 E02276 0 +OP4 E02277 0 +OP4 E02278 0 +OP4 E02279 0 +OP4 E0227A 0 +OP4 E0227B 0 +OP4 E0227C 0 +OP4 E0227D 0 +OP4 E0227E 0 +OP4 E0227F 0 +OP4 E02280 0 +OP4 E02281 0 +OP4 E02282 0 +OP4 E02283 0 +OP4 E02284 0 +OP4 E02285 0 +OP4 E02286 0 +OP4 E02287 0 +OP4 E02288 0 +OP4 E02289 0 +OP4 E0228A 0 +OP4 E0228B 0 +OP4 E0228C 0 +OP4 E0228D 0 +OP4 E0228E 0 +OP4 E0228F 0 +OP4 E02290 0 +OP4 E02291 0 +OP4 E02292 0 +OP4 E02293 0 +OP4 E02294 0 +OP4 E02295 0 +OP4 E02296 0 +OP4 E02297 0 +OP4 E02298 0 +OP4 E02299 0 +OP4 E0229A 0 +OP4 E0229B 0 +OP4 E0229C 0 +OP4 E0229D 0 +OP4 E0229E 0 +OP4 E0229F 0 +OP4 E022A0 0 +OP4 E022A1 0 +OP4 E022A2 0 +OP4 E022A3 0 +OP4 E022A4 0 +OP4 E022A5 0 +OP4 E022A6 0 +OP4 E022A7 0 +OP4 E022A8 0 +OP4 E022A9 0 +OP4 E022AA 0 +OP4 E022AB 0 +OP4 E022AC 0 +OP4 E022AD 0 +OP4 E022AE 0 +OP4 E022AF 0 +OP4 E022B0 0 +OP4 E022B1 0 +OP4 E022B2 0 +OP4 E022B3 0 +OP4 E022B4 0 +OP4 E022B5 0 +OP4 E022B6 0 +OP4 E022B7 0 +OP4 E022B8 0 +OP4 E022B9 0 +OP4 E022BA 0 +OP4 E022BB 0 +OP4 E022BC 0 +OP4 E022BD 0 +OP4 E022BE 0 +OP4 E022BF 0 +OP4 E022C0 0 +OP4 E022C1 0 +OP4 E022C2 0 +OP4 E022C3 0 +OP4 E022C4 0 +OP4 E022C5 0 +OP4 E022C6 0 +OP4 E022C7 0 +OP4 E022C8 0 +OP4 E022C9 0 +OP4 E022CA 0 +OP4 E022CB 0 +OP4 E022CC 0 +OP4 E022CD 0 +OP4 E022CE 0 +OP4 E022CF 0 +OP4 E022D0 0 +OP4 E022D1 0 +OP4 E022D2 0 +OP4 E022D3 0 +OP4 E022D4 0 +OP4 E022D5 0 +OP4 E022D6 0 +OP4 E022D7 0 +OP4 E022D8 0 +OP4 E022D9 0 +OP4 E022DA 0 +OP4 E022DB 0 +OP4 E022DC 0 +OP4 E022DD 0 +OP4 E022DE 0 +OP4 E022DF 0 +OP4 E022E0 0 +OP4 E022E1 0 +OP4 E022E2 0 +OP4 E022E3 0 +OP4 E022E4 0 +OP4 E022E5 0 +OP4 E022E6 0 +OP4 E022E7 0 +OP4 E022E8 0 +OP4 E022E9 0 +OP4 E022EA 0 +OP4 E022EB 0 +OP4 E022EC 0 +OP4 E022ED 0 +OP4 E022EE 0 +OP4 E022EF 0 +OP4 E022F0 0 +OP4 E022F1 0 +OP4 E022F2 0 +OP4 E022F3 0 +OP4 E022F4 0 +OP4 E022F5 0 +OP4 E022F6 0 +OP4 E022F7 0 +OP4 E022F8 0 +OP4 E022F9 0 +OP4 E022FA 0 +OP4 E022FB 0 +OP4 E022FC 0 +OP4 E022FD 0 +OP4 E022FE 0 +OP4 E022FF 0 +OP4 E02300 0 +OP4 E02301 0 +OP4 E02302 0 +OP4 E02303 0 +OP4 E02304 0 +OP4 E02305 0 +OP4 E02306 0 +OP4 E02307 0 +OP4 E02308 0 +OP4 E02309 0 +OP4 E0230A 0 +OP4 E0230B 0 +OP4 E0230C 0 +OP4 E0230D 0 +OP4 E0230E 0 +OP4 E0230F 0 +OP4 E02310 0 +OP4 E02311 0 +OP4 E02312 0 +OP4 E02313 0 +OP4 E02314 0 +OP4 E02315 0 +OP4 E02316 0 +OP4 E02317 0 +OP4 E02318 0 +OP4 E02319 0 +OP4 E0231A 0 +OP4 E0231B 0 +OP4 E0231C 0 +OP4 E0231D 0 +OP4 E0231E 0 +OP4 E0231F 0 +OP4 E02320 0 +OP4 E02321 0 +OP4 E02322 0 +OP4 E02323 0 +OP4 E02324 0 +OP4 E02325 0 +OP4 E02326 0 +OP4 E02327 0 +OP4 E02328 0 +OP4 E02329 0 +OP4 E0232A 0 +OP4 E0232B 0 +OP4 E0232C 0 +OP4 E0232D 0 +OP4 E0232E 0 +OP4 E0232F 0 +OP4 E02330 0 +OP4 E02331 0 +OP4 E02332 0 +OP4 E02333 0 +OP4 E02334 0 +OP4 E02335 0 +OP4 E02336 0 +OP4 E02337 0 +OP4 E02338 0 +OP4 E02339 0 +OP4 E0233A 0 +OP4 E0233B 0 +OP4 E0233C 0 +OP4 E0233D 0 +OP4 E0233E 0 +OP4 E0233F 0 +OP4 E02340 0 +OP4 E02341 0 +OP4 E02342 0 +OP4 E02343 0 +OP4 E02344 0 +OP4 E02345 0 +OP4 E02346 0 +OP4 E02347 0 +OP4 E02348 0 +OP4 E02349 0 +OP4 E0234A 0 +OP4 E0234B 0 +OP4 E0234C 0 +OP4 E0234D 0 +OP4 E0234E 0 +OP4 E0234F 0 +OP4 E02350 0 +OP4 E02351 0 +OP4 E02352 0 +OP4 E02353 0 +OP4 E02354 0 +OP4 E02355 0 +OP4 E02356 0 +OP4 E02357 0 +OP4 E02358 0 +OP4 E02359 0 +OP4 E0235A 0 +OP4 E0235B 0 +OP4 E0235C 0 +OP4 E0235D 0 +OP4 E0235E 0 +OP4 E0235F 0 +OP4 E02360 0 +OP4 E02361 0 +OP4 E02362 0 +OP4 E02363 0 +OP4 E02364 0 +OP4 E02365 0 +OP4 E02366 0 +OP4 E02367 0 +OP4 E02368 0 +OP4 E02369 0 +OP4 E0236A 0 +OP4 E0236B 0 +OP4 E0236C 0 +OP4 E0236D 0 +OP4 E0236E 0 +OP4 E0236F 0 +OP4 E02370 0 +OP4 E02371 0 +OP4 E02372 0 +OP4 E02373 0 +OP4 E02374 0 +OP4 E02375 0 +OP4 E02376 0 +OP4 E02377 0 +OP4 E02378 0 +OP4 E02379 0 +OP4 E0237A 0 +OP4 E0237B 0 +OP4 E0237C 0 +OP4 E0237D 0 +OP4 E0237E 0 +OP4 E0237F 0 +OP4 E02380 0 +OP4 E02381 0 +OP4 E02382 0 +OP4 E02383 0 +OP4 E02384 0 +OP4 E02385 0 +OP4 E02386 0 +OP4 E02387 0 +OP4 E02388 0 +OP4 E02389 0 +OP4 E0238A 0 +OP4 E0238B 0 +OP4 E0238C 0 +OP4 E0238D 0 +OP4 E0238E 0 +OP4 E0238F 0 +OP4 E02390 0 +OP4 E02391 0 +OP4 E02392 0 +OP4 E02393 0 +OP4 E02394 0 +OP4 E02395 0 +OP4 E02396 0 +OP4 E02397 0 +OP4 E02398 0 +OP4 E02399 0 +OP4 E0239A 0 +OP4 E0239B 0 +OP4 E0239C 0 +OP4 E0239D 0 +OP4 E0239E 0 +OP4 E0239F 0 +OP4 E023A0 0 +OP4 E023A1 0 +OP4 E023A2 0 +OP4 E023A3 0 +OP4 E023A4 0 +OP4 E023A5 0 +OP4 E023A6 0 +OP4 E023A7 0 +OP4 E023A8 0 +OP4 E023A9 0 +OP4 E023AA 0 +OP4 E023AB 0 +OP4 E023AC 0 +OP4 E023AD 0 +OP4 E023AE 0 +OP4 E023AF 0 +OP4 E023B0 0 +OP4 E023B1 0 +OP4 E023B2 0 +OP4 E023B3 0 +OP4 E023B4 0 +OP4 E023B5 0 +OP4 E023B6 0 +OP4 E023B7 0 +OP4 E023B8 0 +OP4 E023B9 0 +OP4 E023BA 0 +OP4 E023BB 0 +OP4 E023BC 0 +OP4 E023BD 0 +OP4 E023BE 0 +OP4 E023BF 0 +OP4 E023C0 0 +OP4 E023C1 0 +OP4 E023C2 0 +OP4 E023C3 0 +OP4 E023C4 0 +OP4 E023C5 0 +OP4 E023C6 0 +OP4 E023C7 0 +OP4 E023C8 0 +OP4 E023C9 0 +OP4 E023CA 0 +OP4 E023CB 0 +OP4 E023CC 0 +OP4 E023CD 0 +OP4 E023CE 0 +OP4 E023CF 0 +OP4 E023D0 0 +OP4 E023D1 0 +OP4 E023D2 0 +OP4 E023D3 0 +OP4 E023D4 0 +OP4 E023D5 0 +OP4 E023D6 0 +OP4 E023D7 0 +OP4 E023D8 0 +OP4 E023D9 0 +OP4 E023DA 0 +OP4 E023DB 0 +OP4 E023DC 0 +OP4 E023DD 0 +OP4 E023DE 0 +OP4 E023DF 0 +OP4 E023E0 0 +OP4 E023E1 0 +OP4 E023E2 0 +OP4 E023E3 0 +OP4 E023E4 0 +OP4 E023E5 0 +OP4 E023E6 0 +OP4 E023E7 0 +OP4 E023E8 0 +OP4 E023E9 0 +OP4 E023EA 0 +OP4 E023EB 0 +OP4 E023EC 0 +OP4 E023ED 0 +OP4 E023EE 0 +OP4 E023EF 0 +OP4 E023F0 0 +OP4 E023F1 0 +OP4 E023F2 0 +OP4 E023F3 0 +OP4 E023F4 0 +OP4 E023F5 0 +OP4 E023F6 0 +OP4 E023F7 0 +OP4 E023F8 0 +OP4 E023F9 0 +OP4 E023FA 0 +OP4 E023FB 0 +OP4 E023FC 0 +OP4 E023FD 0 +OP4 E023FE 0 +OP4 E023FF 0 +OP4 E02400 0 +OP4 E02401 0 +OP4 E02402 0 +OP4 E02403 0 +OP4 E02404 0 +OP4 E02405 0 +OP4 E02406 0 +OP4 E02407 0 +OP4 E02408 0 +OP4 E02409 0 +OP4 E0240A 0 +OP4 E0240B 0 +OP4 E0240C 0 +OP4 E0240D 0 +OP4 E0240E 0 +OP4 E0240F 0 +OP4 E02410 0 +OP4 E02411 0 +OP4 E02412 0 +OP4 E02413 0 +OP4 E02414 0 +OP4 E02415 0 +OP4 E02416 0 +OP4 E02417 0 +OP4 E02418 0 +OP4 E02419 0 +OP4 E0241A 0 +OP4 E0241B 0 +OP4 E0241C 0 +OP4 E0241D 0 +OP4 E0241E 0 +OP4 E0241F 0 +OP4 E02420 0 +OP4 E02421 0 +OP4 E02422 0 +OP4 E02423 0 +OP4 E02424 0 +OP4 E02425 0 +OP4 E02426 0 +OP4 E02427 0 +OP4 E02428 0 +OP4 E02429 0 +OP4 E0242A 0 +OP4 E0242B 0 +OP4 E0242C 0 +OP4 E0242D 0 +OP4 E0242E 0 +OP4 E0242F 0 +OP4 E02430 0 +OP4 E02431 0 +OP4 E02432 0 +OP4 E02433 0 +OP4 E02434 0 +OP4 E02435 0 +OP4 E02436 0 +OP4 E02437 0 +OP4 E02438 0 +OP4 E02439 0 +OP4 E0243A 0 +OP4 E0243B 0 +OP4 E0243C 0 +OP4 E0243D 0 +OP4 E0243E 0 +OP4 E0243F 0 +OP4 E02440 0 +OP4 E02441 0 +OP4 E02442 0 +OP4 E02443 0 +OP4 E02444 0 +OP4 E02445 0 +OP4 E02446 0 +OP4 E02447 0 +OP4 E02448 0 +OP4 E02449 0 +OP4 E0244A 0 +OP4 E0244B 0 +OP4 E0244C 0 +OP4 E0244D 0 +OP4 E0244E 0 +OP4 E0244F 0 +OP4 E02450 0 +OP4 E02451 0 +OP4 E02452 0 +OP4 E02453 0 +OP4 E02454 0 +OP4 E02455 0 +OP4 E02456 0 +OP4 E02457 0 +OP4 E02458 0 +OP4 E02459 0 +OP4 E0245A 0 +OP4 E0245B 0 +OP4 E0245C 0 +OP4 E0245D 0 +OP4 E0245E 0 +OP4 E0245F 0 +OP4 E02460 0 +OP4 E02461 0 +OP4 E02462 0 +OP4 E02463 0 +OP4 E02464 0 +OP4 E02465 0 +OP4 E02466 0 +OP4 E02467 0 +OP4 E02468 0 +OP4 E02469 0 +OP4 E0246A 0 +OP4 E0246B 0 +OP4 E0246C 0 +OP4 E0246D 0 +OP4 E0246E 0 +OP4 E0246F 0 +OP4 E02470 0 +OP4 E02471 0 +OP4 E02472 0 +OP4 E02473 0 +OP4 E02474 0 +OP4 E02475 0 +OP4 E02476 0 +OP4 E02477 0 +OP4 E02478 0 +OP4 E02479 0 +OP4 E0247A 0 +OP4 E0247B 0 +OP4 E0247C 0 +OP4 E0247D 0 +OP4 E0247E 0 +OP4 E0247F 0 +OP4 E02480 0 +OP4 E02481 0 +OP4 E02482 0 +OP4 E02483 0 +OP4 E02484 0 +OP4 E02485 0 +OP4 E02486 0 +OP4 E02487 0 +OP4 E02488 0 +OP4 E02489 0 +OP4 E0248A 0 +OP4 E0248B 0 +OP4 E0248C 0 +OP4 E0248D 0 +OP4 E0248E 0 +OP4 E0248F 0 +OP4 E02490 0 +OP4 E02491 0 +OP4 E02492 0 +OP4 E02493 0 +OP4 E02494 0 +OP4 E02495 0 +OP4 E02496 0 +OP4 E02497 0 +OP4 E02498 0 +OP4 E02499 0 +OP4 E0249A 0 +OP4 E0249B 0 +OP4 E0249C 0 +OP4 E0249D 0 +OP4 E0249E 0 +OP4 E0249F 0 +OP4 E024A0 0 +OP4 E024A1 0 +OP4 E024A2 0 +OP4 E024A3 0 +OP4 E024A4 0 +OP4 E024A5 0 +OP4 E024A6 0 +OP4 E024A7 0 +OP4 E024A8 0 +OP4 E024A9 0 +OP4 E024AA 0 +OP4 E024AB 0 +OP4 E024AC 0 +OP4 E024AD 0 +OP4 E024AE 0 +OP4 E024AF 0 +OP4 E024B0 0 +OP4 E024B1 0 +OP4 E024B2 0 +OP4 E024B3 0 +OP4 E024B4 0 +OP4 E024B5 0 +OP4 E024B6 0 +OP4 E024B7 0 +OP4 E024B8 0 +OP4 E024B9 0 +OP4 E024BA 0 +OP4 E024BB 0 +OP4 E024BC 0 +OP4 E024BD 0 +OP4 E024BE 0 +OP4 E024BF 0 +OP4 E024C0 0 +OP4 E024C1 0 +OP4 E024C2 0 +OP4 E024C3 0 +OP4 E024C4 0 +OP4 E024C5 0 +OP4 E024C6 0 +OP4 E024C7 0 +OP4 E024C8 0 +OP4 E024C9 0 +OP4 E024CA 0 +OP4 E024CB 0 +OP4 E024CC 0 +OP4 E024CD 0 +OP4 E024CE 0 +OP4 E024CF 0 +OP4 E024D0 0 +OP4 E024D1 0 +OP4 E024D2 0 +OP4 E024D3 0 +OP4 E024D4 0 +OP4 E024D5 0 +OP4 E024D6 0 +OP4 E024D7 0 +OP4 E024D8 0 +OP4 E024D9 0 +OP4 E024DA 0 +OP4 E024DB 0 +OP4 E024DC 0 +OP4 E024DD 0 +OP4 E024DE 0 +OP4 E024DF 0 +OP4 E024E0 0 +OP4 E024E1 0 +OP4 E024E2 0 +OP4 E024E3 0 +OP4 E024E4 0 +OP4 E024E5 0 +OP4 E024E6 0 +OP4 E024E7 0 +OP4 E024E8 0 +OP4 E024E9 0 +OP4 E024EA 0 +OP4 E024EB 0 +OP4 E024EC 0 +OP4 E024ED 0 +OP4 E024EE 0 +OP4 E024EF 0 +OP4 E024F0 0 +OP4 E024F1 0 +OP4 E024F2 0 +OP4 E024F3 0 +OP4 E024F4 0 +OP4 E024F5 0 +OP4 E024F6 0 +OP4 E024F7 0 +OP4 E024F8 0 +OP4 E024F9 0 +OP4 E024FA 0 +OP4 E024FB 0 +OP4 E024FC 0 +OP4 E024FD 0 +OP4 E024FE 0 +OP4 E024FF 0 +OP4 E02500 0 +OP4 E02501 0 +OP4 E02502 0 +OP4 E02503 0 +OP4 E02504 0 +OP4 E02505 0 +OP4 E02506 0 +OP4 E02507 0 +OP4 E02508 0 +OP4 E02509 0 +OP4 E0250A 0 +OP4 E0250B 0 +OP4 E0250C 0 +OP4 E0250D 0 +OP4 E0250E 0 +OP4 E0250F 0 +OP4 E02510 0 +OP4 E02511 0 +OP4 E02512 0 +OP4 E02513 0 +OP4 E02514 0 +OP4 E02515 0 +OP4 E02516 0 +OP4 E02517 0 +OP4 E02518 0 +OP4 E02519 0 +OP4 E0251A 0 +OP4 E0251B 0 +OP4 E0251C 0 +OP4 E0251D 0 +OP4 E0251E 0 +OP4 E0251F 0 +OP4 E02520 0 +OP4 E02521 0 +OP4 E02522 0 +OP4 E02523 0 +OP4 E02524 0 +OP4 E02525 0 +OP4 E02526 0 +OP4 E02527 0 +OP4 E02528 0 +OP4 E02529 0 +OP4 E0252A 0 +OP4 E0252B 0 +OP4 E0252C 0 +OP4 E0252D 0 +OP4 E0252E 0 +OP4 E0252F 0 +OP4 E02530 0 +OP4 E02531 0 +OP4 E02532 0 +OP4 E02533 0 +OP4 E02534 0 +OP4 E02535 0 +OP4 E02536 0 +OP4 E02537 0 +OP4 E02538 0 +OP4 E02539 0 +OP4 E0253A 0 +OP4 E0253B 0 +OP4 E0253C 0 +OP4 E0253D 0 +OP4 E0253E 0 +OP4 E0253F 0 +OP4 E02540 0 +OP4 E02541 0 +OP4 E02542 0 +OP4 E02543 0 +OP4 E02544 0 +OP4 E02545 0 +OP4 E02546 0 +OP4 E02547 0 +OP4 E02548 0 +OP4 E02549 0 +OP4 E0254A 0 +OP4 E0254B 0 +OP4 E0254C 0 +OP4 E0254D 0 +OP4 E0254E 0 +OP4 E0254F 0 +OP4 E02550 0 +OP4 E02551 0 +OP4 E02552 0 +OP4 E02553 0 +OP4 E02554 0 +OP4 E02555 0 +OP4 E02556 0 +OP4 E02557 0 +OP4 E02558 0 +OP4 E02559 0 +OP4 E0255A 0 +OP4 E0255B 0 +OP4 E0255C 0 +OP4 E0255D 0 +OP4 E0255E 0 +OP4 E0255F 0 +OP4 E02560 0 +OP4 E02561 0 +OP4 E02562 0 +OP4 E02563 0 +OP4 E02564 0 +OP4 E02565 0 +OP4 E02566 0 +OP4 E02567 0 +OP4 E02568 0 +OP4 E02569 0 +OP4 E0256A 0 +OP4 E0256B 0 +OP4 E0256C 0 +OP4 E0256D 0 +OP4 E0256E 0 +OP4 E0256F 0 +OP4 E02570 0 +OP4 E02571 0 +OP4 E02572 0 +OP4 E02573 0 +OP4 E02574 0 +OP4 E02575 0 +OP4 E02576 0 +OP4 E02577 0 +OP4 E02578 0 +OP4 E02579 0 +OP4 E0257A 0 +OP4 E0257B 0 +OP4 E0257C 0 +OP4 E0257D 0 +OP4 E0257E 0 +OP4 E0257F 0 +OP4 E02580 0 +OP4 E02581 0 +OP4 E02582 0 +OP4 E02583 0 +OP4 E02584 0 +OP4 E02585 0 +OP4 E02586 0 +OP4 E02587 0 +OP4 E02588 0 +OP4 E02589 0 +OP4 E0258A 0 +OP4 E0258B 0 +OP4 E0258C 0 +OP4 E0258D 0 +OP4 E0258E 0 +OP4 E0258F 0 +OP4 E02590 0 +OP4 E02591 0 +OP4 E02592 0 +OP4 E02593 0 +OP4 E02594 0 +OP4 E02595 0 +OP4 E02596 0 +OP4 E02597 0 +OP4 E02598 0 +OP4 E02599 0 +OP4 E0259A 0 +OP4 E0259B 0 +OP4 E0259C 0 +OP4 E0259D 0 +OP4 E0259E 0 +OP4 E0259F 0 +OP4 E025A0 0 +OP4 E025A1 0 +OP4 E025A2 0 +OP4 E025A3 0 +OP4 E025A4 0 +OP4 E025A5 0 +OP4 E025A6 0 +OP4 E025A7 0 +OP4 E025A8 0 +OP4 E025A9 0 +OP4 E025AA 0 +OP4 E025AB 0 +OP4 E025AC 0 +OP4 E025AD 0 +OP4 E025AE 0 +OP4 E025AF 0 +OP4 E025B0 0 +OP4 E025B1 0 +OP4 E025B2 0 +OP4 E025B3 0 +OP4 E025B4 0 +OP4 E025B5 0 +OP4 E025B6 0 +OP4 E025B7 0 +OP4 E025B8 0 +OP4 E025B9 0 +OP4 E025BA 0 +OP4 E025BB 0 +OP4 E025BC 0 +OP4 E025BD 0 +OP4 E025BE 0 +OP4 E025BF 0 +OP4 E025C0 0 +OP4 E025C1 0 +OP4 E025C2 0 +OP4 E025C3 0 +OP4 E025C4 0 +OP4 E025C5 0 +OP4 E025C6 0 +OP4 E025C7 0 +OP4 E025C8 0 +OP4 E025C9 0 +OP4 E025CA 0 +OP4 E025CB 0 +OP4 E025CC 0 +OP4 E025CD 0 +OP4 E025CE 0 +OP4 E025CF 0 +OP4 E025D0 0 +OP4 E025D1 0 +OP4 E025D2 0 +OP4 E025D3 0 +OP4 E025D4 0 +OP4 E025D5 0 +OP4 E025D6 0 +OP4 E025D7 0 +OP4 E025D8 0 +OP4 E025D9 0 +OP4 E025DA 0 +OP4 E025DB 0 +OP4 E025DC 0 +OP4 E025DD 0 +OP4 E025DE 0 +OP4 E025DF 0 +OP4 E025E0 0 +OP4 E025E1 0 +OP4 E025E2 0 +OP4 E025E3 0 +OP4 E025E4 0 +OP4 E025E5 0 +OP4 E025E6 0 +OP4 E025E7 0 +OP4 E025E8 0 +OP4 E025E9 0 +OP4 E025EA 0 +OP4 E025EB 0 +OP4 E025EC 0 +OP4 E025ED 0 +OP4 E025EE 0 +OP4 E025EF 0 +OP4 E025F0 0 +OP4 E025F1 0 +OP4 E025F2 0 +OP4 E025F3 0 +OP4 E025F4 0 +OP4 E025F5 0 +OP4 E025F6 0 +OP4 E025F7 0 +OP4 E025F8 0 +OP4 E025F9 0 +OP4 E025FA 0 +OP4 E025FB 0 +OP4 E025FC 0 +OP4 E025FD 0 +OP4 E025FE 0 +OP4 E025FF 0 +OP4 E02600 0 +OP4 E02601 0 +OP4 E02602 0 +OP4 E02603 0 +OP4 E02604 0 +OP4 E02605 0 +OP4 E02606 0 +OP4 E02607 0 +OP4 E02608 0 +OP4 E02609 0 +OP4 E0260A 0 +OP4 E0260B 0 +OP4 E0260C 0 +OP4 E0260D 0 +OP4 E0260E 0 +OP4 E0260F 0 +OP4 E02610 0 +OP4 E02611 0 +OP4 E02612 0 +OP4 E02613 0 +OP4 E02614 0 +OP4 E02615 0 +OP4 E02616 0 +OP4 E02617 0 +OP4 E02618 0 +OP4 E02619 0 +OP4 E0261A 0 +OP4 E0261B 0 +OP4 E0261C 0 +OP4 E0261D 0 +OP4 E0261E 0 +OP4 E0261F 0 +OP4 E02620 0 +OP4 E02621 0 +OP4 E02622 0 +OP4 E02623 0 +OP4 E02624 0 +OP4 E02625 0 +OP4 E02626 0 +OP4 E02627 0 +OP4 E02628 0 +OP4 E02629 0 +OP4 E0262A 0 +OP4 E0262B 0 +OP4 E0262C 0 +OP4 E0262D 0 +OP4 E0262E 0 +OP4 E0262F 0 +OP4 E02630 0 +OP4 E02631 0 +OP4 E02632 0 +OP4 E02633 0 +OP4 E02634 0 +OP4 E02635 0 +OP4 E02636 0 +OP4 E02637 0 +OP4 E02638 0 +OP4 E02639 0 +OP4 E0263A 0 +OP4 E0263B 0 +OP4 E0263C 0 +OP4 E0263D 0 +OP4 E0263E 0 +OP4 E0263F 0 +OP4 E02640 0 +OP4 E02641 0 +OP4 E02642 0 +OP4 E02643 0 +OP4 E02644 0 +OP4 E02645 0 +OP4 E02646 0 +OP4 E02647 0 +OP4 E02648 0 +OP4 E02649 0 +OP4 E0264A 0 +OP4 E0264B 0 +OP4 E0264C 0 +OP4 E0264D 0 +OP4 E0264E 0 +OP4 E0264F 0 +OP4 E02650 0 +OP4 E02651 0 +OP4 E02652 0 +OP4 E02653 0 +OP4 E02654 0 +OP4 E02655 0 +OP4 E02656 0 +OP4 E02657 0 +OP4 E02658 0 +OP4 E02659 0 +OP4 E0265A 0 +OP4 E0265B 0 +OP4 E0265C 0 +OP4 E0265D 0 +OP4 E0265E 0 +OP4 E0265F 0 +OP4 E02660 0 +OP4 E02661 0 +OP4 E02662 0 +OP4 E02663 0 +OP4 E02664 0 +OP4 E02665 0 +OP4 E02666 0 +OP4 E02667 0 +OP4 E02668 0 +OP4 E02669 0 +OP4 E0266A 0 +OP4 E0266B 0 +OP4 E0266C 0 +OP4 E0266D 0 +OP4 E0266E 0 +OP4 E0266F 0 +OP4 E02670 0 +OP4 E02671 0 +OP4 E02672 0 +OP4 E02673 0 +OP4 E02674 0 +OP4 E02675 0 +OP4 E02676 0 +OP4 E02677 0 +OP4 E02678 0 +OP4 E02679 0 +OP4 E0267A 0 +OP4 E0267B 0 +OP4 E0267C 0 +OP4 E0267D 0 +OP4 E0267E 0 +OP4 E0267F 0 +OP4 E02680 0 +OP4 E02681 0 +OP4 E02682 0 +OP4 E02683 0 +OP4 E02684 0 +OP4 E02685 0 +OP4 E02686 0 +OP4 E02687 0 +OP4 E02688 0 +OP4 E02689 0 +OP4 E0268A 0 +OP4 E0268B 0 +OP4 E0268C 0 +OP4 E0268D 0 +OP4 E0268E 0 +OP4 E0268F 0 +OP4 E02690 0 +OP4 E02691 0 +OP4 E02692 0 +OP4 E02693 0 +OP4 E02694 0 +OP4 E02695 0 +OP4 E02696 0 +OP4 E02697 0 +OP4 E02698 0 +OP4 E02699 0 +OP4 E0269A 0 +OP4 E0269B 0 +OP4 E0269C 0 +OP4 E0269D 0 +OP4 E0269E 0 +OP4 E0269F 0 +OP4 E026A0 0 +OP4 E026A1 0 +OP4 E026A2 0 +OP4 E026A3 0 +OP4 E026A4 0 +OP4 E026A5 0 +OP4 E026A6 0 +OP4 E026A7 0 +OP4 E026A8 0 +OP4 E026A9 0 +OP4 E026AA 0 +OP4 E026AB 0 +OP4 E026AC 0 +OP4 E026AD 0 +OP4 E026AE 0 +OP4 E026AF 0 +OP4 E026B0 0 +OP4 E026B1 0 +OP4 E026B2 0 +OP4 E026B3 0 +OP4 E026B4 0 +OP4 E026B5 0 +OP4 E026B6 0 +OP4 E026B7 0 +OP4 E026B8 0 +OP4 E026B9 0 +OP4 E026BA 0 +OP4 E026BB 0 +OP4 E026BC 0 +OP4 E026BD 0 +OP4 E026BE 0 +OP4 E026BF 0 +OP4 E026C0 0 +OP4 E026C1 0 +OP4 E026C2 0 +OP4 E026C3 0 +OP4 E026C4 0 +OP4 E026C5 0 +OP4 E026C6 0 +OP4 E026C7 0 +OP4 E026C8 0 +OP4 E026C9 0 +OP4 E026CA 0 +OP4 E026CB 0 +OP4 E026CC 0 +OP4 E026CD 0 +OP4 E026CE 0 +OP4 E026CF 0 +OP4 E026D0 0 +OP4 E026D1 0 +OP4 E026D2 0 +OP4 E026D3 0 +OP4 E026D4 0 +OP4 E026D5 0 +OP4 E026D6 0 +OP4 E026D7 0 +OP4 E026D8 0 +OP4 E026D9 0 +OP4 E026DA 0 +OP4 E026DB 0 +OP4 E026DC 0 +OP4 E026DD 0 +OP4 E026DE 0 +OP4 E026DF 0 +OP4 E026E0 0 +OP4 E026E1 0 +OP4 E026E2 0 +OP4 E026E3 0 +OP4 E026E4 0 +OP4 E026E5 0 +OP4 E026E6 0 +OP4 E026E7 0 +OP4 E026E8 0 +OP4 E026E9 0 +OP4 E026EA 0 +OP4 E026EB 0 +OP4 E026EC 0 +OP4 E026ED 0 +OP4 E026EE 0 +OP4 E026EF 0 +OP4 E026F0 0 +OP4 E026F1 0 +OP4 E026F2 0 +OP4 E026F3 0 +OP4 E026F4 0 +OP4 E026F5 0 +OP4 E026F6 0 +OP4 E026F7 0 +OP4 E026F8 0 +OP4 E026F9 0 +OP4 E026FA 0 +OP4 E026FB 0 +OP4 E026FC 0 +OP4 E026FD 0 +OP4 E026FE 0 +OP4 E026FF 0 +OP4 E02700 0 +OP4 E02701 0 +OP4 E02702 0 +OP4 E02703 0 +OP4 E02704 0 +OP4 E02705 0 +OP4 E02706 0 +OP4 E02707 0 +OP4 E02708 0 +OP4 E02709 0 +OP4 E0270A 0 +OP4 E0270B 0 +OP4 E0270C 0 +OP4 E0270D 0 +OP4 E0270E 0 +OP4 E0270F 0 +OP4 E02710 0 +OP4 E02711 0 +OP4 E02712 0 +OP4 E02713 0 +OP4 E02714 0 +OP4 E02715 0 +OP4 E02716 0 +OP4 E02717 0 +OP4 E02718 0 +OP4 E02719 0 +OP4 E0271A 0 +OP4 E0271B 0 +OP4 E0271C 0 +OP4 E0271D 0 +OP4 E0271E 0 +OP4 E0271F 0 +OP4 E02720 0 +OP4 E02721 0 +OP4 E02722 0 +OP4 E02723 0 +OP4 E02724 0 +OP4 E02725 0 +OP4 E02726 0 +OP4 E02727 0 +OP4 E02728 0 +OP4 E02729 0 +OP4 E0272A 0 +OP4 E0272B 0 +OP4 E0272C 0 +OP4 E0272D 0 +OP4 E0272E 0 +OP4 E0272F 0 +OP4 E02730 0 +OP4 E02731 0 +OP4 E02732 0 +OP4 E02733 0 +OP4 E02734 0 +OP4 E02735 0 +OP4 E02736 0 +OP4 E02737 0 +OP4 E02738 0 +OP4 E02739 0 +OP4 E0273A 0 +OP4 E0273B 0 +OP4 E0273C 0 +OP4 E0273D 0 +OP4 E0273E 0 +OP4 E0273F 0 +OP4 E02740 0 +OP4 E02741 0 +OP4 E02742 0 +OP4 E02743 0 +OP4 E02744 0 +OP4 E02745 0 +OP4 E02746 0 +OP4 E02747 0 +OP4 E02748 0 +OP4 E02749 0 +OP4 E0274A 0 +OP4 E0274B 0 +OP4 E0274C 0 +OP4 E0274D 0 +OP4 E0274E 0 +OP4 E0274F 0 +OP4 E02750 0 +OP4 E02751 0 +OP4 E02752 0 +OP4 E02753 0 +OP4 E02754 0 +OP4 E02755 0 +OP4 E02756 0 +OP4 E02757 0 +OP4 E02758 0 +OP4 E02759 0 +OP4 E0275A 0 +OP4 E0275B 0 +OP4 E0275C 0 +OP4 E0275D 0 +OP4 E0275E 0 +OP4 E0275F 0 +OP4 E02760 0 +OP4 E02761 0 +OP4 E02762 0 +OP4 E02763 0 +OP4 E02764 0 +OP4 E02765 0 +OP4 E02766 0 +OP4 E02767 0 +OP4 E02768 0 +OP4 E02769 0 +OP4 E0276A 0 +OP4 E0276B 0 +OP4 E0276C 0 +OP4 E0276D 0 +OP4 E0276E 0 +OP4 E0276F 0 +OP4 E02770 0 +OP4 E02771 0 +OP4 E02772 0 +OP4 E02773 0 +OP4 E02774 0 +OP4 E02775 0 +OP4 E02776 0 +OP4 E02777 0 +OP4 E02778 0 +OP4 E02779 0 +OP4 E0277A 0 +OP4 E0277B 0 +OP4 E0277C 0 +OP4 E0277D 0 +OP4 E0277E 0 +OP4 E0277F 0 +OP4 E02780 0 +OP4 E02781 0 +OP4 E02782 0 +OP4 E02783 0 +OP4 E02784 0 +OP4 E02785 0 +OP4 E02786 0 +OP4 E02787 0 +OP4 E02788 0 +OP4 E02789 0 +OP4 E0278A 0 +OP4 E0278B 0 +OP4 E0278C 0 +OP4 E0278D 0 +OP4 E0278E 0 +OP4 E0278F 0 +OP4 E02790 0 +OP4 E02791 0 +OP4 E02792 0 +OP4 E02793 0 +OP4 E02794 0 +OP4 E02795 0 +OP4 E02796 0 +OP4 E02797 0 +OP4 E02798 0 +OP4 E02799 0 +OP4 E0279A 0 +OP4 E0279B 0 +OP4 E0279C 0 +OP4 E0279D 0 +OP4 E0279E 0 +OP4 E0279F 0 +OP4 E027A0 0 +OP4 E027A1 0 +OP4 E027A2 0 +OP4 E027A3 0 +OP4 E027A4 0 +OP4 E027A5 0 +OP4 E027A6 0 +OP4 E027A7 0 +OP4 E027A8 0 +OP4 E027A9 0 +OP4 E027AA 0 +OP4 E027AB 0 +OP4 E027AC 0 +OP4 E027AD 0 +OP4 E027AE 0 +OP4 E027AF 0 +OP4 E027B0 0 +OP4 E027B1 0 +OP4 E027B2 0 +OP4 E027B3 0 +OP4 E027B4 0 +OP4 E027B5 0 +OP4 E027B6 0 +OP4 E027B7 0 +OP4 E027B8 0 +OP4 E027B9 0 +OP4 E027BA 0 +OP4 E027BB 0 +OP4 E027BC 0 +OP4 E027BD 0 +OP4 E027BE 0 +OP4 E027BF 0 +OP4 E027C0 0 +OP4 E027C1 0 +OP4 E027C2 0 +OP4 E027C3 0 +OP4 E027C4 0 +OP4 E027C5 0 +OP4 E027C6 0 +OP4 E027C7 0 +OP4 E027C8 0 +OP4 E027C9 0 +OP4 E027CA 0 +OP4 E027CB 0 +OP4 E027CC 0 +OP4 E027CD 0 +OP4 E027CE 0 +OP4 E027CF 0 +OP4 E027D0 0 +OP4 E027D1 0 +OP4 E027D2 0 +OP4 E027D3 0 +OP4 E027D4 0 +OP4 E027D5 0 +OP4 E027D6 0 +OP4 E027D7 0 +OP4 E027D8 0 +OP4 E027D9 0 +OP4 E027DA 0 +OP4 E027DB 0 +OP4 E027DC 0 +OP4 E027DD 0 +OP4 E027DE 0 +OP4 E027DF 0 +OP4 E027E0 0 +OP4 E027E1 0 +OP4 E027E2 0 +OP4 E027E3 0 +OP4 E027E4 0 +OP4 E027E5 0 +OP4 E027E6 0 +OP4 E027E7 0 +OP4 E027E8 0 +OP4 E027E9 0 +OP4 E027EA 0 +OP4 E027EB 0 +OP4 E027EC 0 +OP4 E027ED 0 +OP4 E027EE 0 +OP4 E027EF 0 +OP4 E027F0 0 +OP4 E027F1 0 +OP4 E027F2 0 +OP4 E027F3 0 +OP4 E027F4 0 +OP4 E027F5 0 +OP4 E027F6 0 +OP4 E027F7 0 +OP4 E027F8 0 +OP4 E027F9 0 +OP4 E027FA 0 +OP4 E027FB 0 +OP4 E027FC 0 +OP4 E027FD 0 +OP4 E027FE 0 +OP4 E027FF 0 +OP4 E02800 0 +OP4 E02801 0 +OP4 E02802 0 +OP4 E02803 0 +OP4 E02804 0 +OP4 E02805 0 +OP4 E02806 0 +OP4 E02807 0 +OP4 E02808 0 +OP4 E02809 0 +OP4 E0280A 0 +OP4 E0280B 0 +OP4 E0280C 0 +OP4 E0280D 0 +OP4 E0280E 0 +OP4 E0280F 0 +OP4 E02810 0 +OP4 E02811 0 +OP4 E02812 0 +OP4 E02813 0 +OP4 E02814 0 +OP4 E02815 0 +OP4 E02816 0 +OP4 E02817 0 +OP4 E02818 0 +OP4 E02819 0 +OP4 E0281A 0 +OP4 E0281B 0 +OP4 E0281C 0 +OP4 E0281D 0 +OP4 E0281E 0 +OP4 E0281F 0 +OP4 E02820 0 +OP4 E02821 0 +OP4 E02822 0 +OP4 E02823 0 +OP4 E02824 0 +OP4 E02825 0 +OP4 E02826 0 +OP4 E02827 0 +OP4 E02828 0 +OP4 E02829 0 +OP4 E0282A 0 +OP4 E0282B 0 +OP4 E0282C 0 +OP4 E0282D 0 +OP4 E0282E 0 +OP4 E0282F 0 +OP4 E02830 0 +OP4 E02831 0 +OP4 E02832 0 +OP4 E02833 0 +OP4 E02834 0 +OP4 E02835 0 +OP4 E02836 0 +OP4 E02837 0 +OP4 E02838 0 +OP4 E02839 0 +OP4 E0283A 0 +OP4 E0283B 0 +OP4 E0283C 0 +OP4 E0283D 0 +OP4 E0283E 0 +OP4 E0283F 0 +OP4 E02840 0 +OP4 E02841 0 +OP4 E02842 0 +OP4 E02843 0 +OP4 E02844 0 +OP4 E02845 0 +OP4 E02846 0 +OP4 E02847 0 +OP4 E02848 0 +OP4 E02849 0 +OP4 E0284A 0 +OP4 E0284B 0 +OP4 E0284C 0 +OP4 E0284D 0 +OP4 E0284E 0 +OP4 E0284F 0 +OP4 E02850 0 +OP4 E02851 0 +OP4 E02852 0 +OP4 E02853 0 +OP4 E02854 0 +OP4 E02855 0 +OP4 E02856 0 +OP4 E02857 0 +OP4 E02858 0 +OP4 E02859 0 +OP4 E0285A 0 +OP4 E0285B 0 +OP4 E0285C 0 +OP4 E0285D 0 +OP4 E0285E 0 +OP4 E0285F 0 +OP4 E02860 0 +OP4 E02861 0 +OP4 E02862 0 +OP4 E02863 0 +OP4 E02864 0 +OP4 E02865 0 +OP4 E02866 0 +OP4 E02867 0 +OP4 E02868 0 +OP4 E02869 0 +OP4 E0286A 0 +OP4 E0286B 0 +OP4 E0286C 0 +OP4 E0286D 0 +OP4 E0286E 0 +OP4 E0286F 0 +OP4 E02870 0 +OP4 E02871 0 +OP4 E02872 0 +OP4 E02873 0 +OP4 E02874 0 +OP4 E02875 0 +OP4 E02876 0 +OP4 E02877 0 +OP4 E02878 0 +OP4 E02879 0 +OP4 E0287A 0 +OP4 E0287B 0 +OP4 E0287C 0 +OP4 E0287D 0 +OP4 E0287E 0 +OP4 E0287F 0 +OP4 E02880 0 +OP4 E02881 0 +OP4 E02882 0 +OP4 E02883 0 +OP4 E02884 0 +OP4 E02885 0 +OP4 E02886 0 +OP4 E02887 0 +OP4 E02888 0 +OP4 E02889 0 +OP4 E0288A 0 +OP4 E0288B 0 +OP4 E0288C 0 +OP4 E0288D 0 +OP4 E0288E 0 +OP4 E0288F 0 +OP4 E02890 0 +OP4 E02891 0 +OP4 E02892 0 +OP4 E02893 0 +OP4 E02894 0 +OP4 E02895 0 +OP4 E02896 0 +OP4 E02897 0 +OP4 E02898 0 +OP4 E02899 0 +OP4 E0289A 0 +OP4 E0289B 0 +OP4 E0289C 0 +OP4 E0289D 0 +OP4 E0289E 0 +OP4 E0289F 0 +OP4 E028A0 0 +OP4 E028A1 0 +OP4 E028A2 0 +OP4 E028A3 0 +OP4 E028A4 0 +OP4 E028A5 0 +OP4 E028A6 0 +OP4 E028A7 0 +OP4 E028A8 0 +OP4 E028A9 0 +OP4 E028AA 0 +OP4 E028AB 0 +OP4 E028AC 0 +OP4 E028AD 0 +OP4 E028AE 0 +OP4 E028AF 0 +OP4 E028B0 0 +OP4 E028B1 0 +OP4 E028B2 0 +OP4 E028B3 0 +OP4 E028B4 0 +OP4 E028B5 0 +OP4 E028B6 0 +OP4 E028B7 0 +OP4 E028B8 0 +OP4 E028B9 0 +OP4 E028BA 0 +OP4 E028BB 0 +OP4 E028BC 0 +OP4 E028BD 0 +OP4 E028BE 0 +OP4 E028BF 0 +OP4 E028C0 0 +OP4 E028C1 0 +OP4 E028C2 0 +OP4 E028C3 0 +OP4 E028C4 0 +OP4 E028C5 0 +OP4 E028C6 0 +OP4 E028C7 0 +OP4 E028C8 0 +OP4 E028C9 0 +OP4 E028CA 0 +OP4 E028CB 0 +OP4 E028CC 0 +OP4 E028CD 0 +OP4 E028CE 0 +OP4 E028CF 0 +OP4 E028D0 0 +OP4 E028D1 0 +OP4 E028D2 0 +OP4 E028D3 0 +OP4 E028D4 0 +OP4 E028D5 0 +OP4 E028D6 0 +OP4 E028D7 0 +OP4 E028D8 0 +OP4 E028D9 0 +OP4 E028DA 0 +OP4 E028DB 0 +OP4 E028DC 0 +OP4 E028DD 0 +OP4 E028DE 0 +OP4 E028DF 0 +OP4 E028E0 0 +OP4 E028E1 0 +OP4 E028E2 0 +OP4 E028E3 0 +OP4 E028E4 0 +OP4 E028E5 0 +OP4 E028E6 0 +OP4 E028E7 0 +OP4 E028E8 0 +OP4 E028E9 0 +OP4 E028EA 0 +OP4 E028EB 0 +OP4 E028EC 0 +OP4 E028ED 0 +OP4 E028EE 0 +OP4 E028EF 0 +OP4 E028F0 0 +OP4 E028F1 0 +OP4 E028F2 0 +OP4 E028F3 0 +OP4 E028F4 0 +OP4 E028F5 0 +OP4 E028F6 0 +OP4 E028F7 0 +OP4 E028F8 0 +OP4 E028F9 0 +OP4 E028FA 0 +OP4 E028FB 0 +OP4 E028FC 0 +OP4 E028FD 0 +OP4 E028FE 0 +OP4 E028FF 0 +OP4 E02900 0 +OP4 E02901 0 +OP4 E02902 0 +OP4 E02903 0 +OP4 E02904 0 +OP4 E02905 0 +OP4 E02906 0 +OP4 E02907 0 +OP4 E02908 0 +OP4 E02909 0 +OP4 E0290A 0 +OP4 E0290B 0 +OP4 E0290C 0 +OP4 E0290D 0 +OP4 E0290E 0 +OP4 E0290F 0 +OP4 E02910 0 +OP4 E02911 0 +OP4 E02912 0 +OP4 E02913 0 +OP4 E02914 0 +OP4 E02915 0 +OP4 E02916 0 +OP4 E02917 0 +OP4 E02918 0 +OP4 E02919 0 +OP4 E0291A 0 +OP4 E0291B 0 +OP4 E0291C 0 +OP4 E0291D 0 +OP4 E0291E 0 +OP4 E0291F 0 +OP4 E02920 0 +OP4 E02921 0 +OP4 E02922 0 +OP4 E02923 0 +OP4 E02924 0 +OP4 E02925 0 +OP4 E02926 0 +OP4 E02927 0 +OP4 E02928 0 +OP4 E02929 0 +OP4 E0292A 0 +OP4 E0292B 0 +OP4 E0292C 0 +OP4 E0292D 0 +OP4 E0292E 0 +OP4 E0292F 0 +OP4 E02930 0 +OP4 E02931 0 +OP4 E02932 0 +OP4 E02933 0 +OP4 E02934 0 +OP4 E02935 0 +OP4 E02936 0 +OP4 E02937 0 +OP4 E02938 0 +OP4 E02939 0 +OP4 E0293A 0 +OP4 E0293B 0 +OP4 E0293C 0 +OP4 E0293D 0 +OP4 E0293E 0 +OP4 E0293F 0 +OP4 E02940 0 +OP4 E02941 0 +OP4 E02942 0 +OP4 E02943 0 +OP4 E02944 0 +OP4 E02945 0 +OP4 E02946 0 +OP4 E02947 0 +OP4 E02948 0 +OP4 E02949 0 +OP4 E0294A 0 +OP4 E0294B 0 +OP4 E0294C 0 +OP4 E0294D 0 +OP4 E0294E 0 +OP4 E0294F 0 +OP4 E02950 0 +OP4 E02951 0 +OP4 E02952 0 +OP4 E02953 0 +OP4 E02954 0 +OP4 E02955 0 +OP4 E02956 0 +OP4 E02957 0 +OP4 E02958 0 +OP4 E02959 0 +OP4 E0295A 0 +OP4 E0295B 0 +OP4 E0295C 0 +OP4 E0295D 0 +OP4 E0295E 0 +OP4 E0295F 0 +OP4 E02960 0 +OP4 E02961 0 +OP4 E02962 0 +OP4 E02963 0 +OP4 E02964 0 +OP4 E02965 0 +OP4 E02966 0 +OP4 E02967 0 +OP4 E02968 0 +OP4 E02969 0 +OP4 E0296A 0 +OP4 E0296B 0 +OP4 E0296C 0 +OP4 E0296D 0 +OP4 E0296E 0 +OP4 E0296F 0 +OP4 E02970 0 +OP4 E02971 0 +OP4 E02972 0 +OP4 E02973 0 +OP4 E02974 0 +OP4 E02975 0 +OP4 E02976 0 +OP4 E02977 0 +OP4 E02978 0 +OP4 E02979 0 +OP4 E0297A 0 +OP4 E0297B 0 +OP4 E0297C 0 +OP4 E0297D 0 +OP4 E0297E 0 +OP4 E0297F 0 +OP4 E02980 0 +OP4 E02981 0 +OP4 E02982 0 +OP4 E02983 0 +OP4 E02984 0 +OP4 E02985 0 +OP4 E02986 0 +OP4 E02987 0 +OP4 E02988 0 +OP4 E02989 0 +OP4 E0298A 0 +OP4 E0298B 0 +OP4 E0298C 0 +OP4 E0298D 0 +OP4 E0298E 0 +OP4 E0298F 0 +OP4 E02990 0 +OP4 E02991 0 +OP4 E02992 0 +OP4 E02993 0 +OP4 E02994 0 +OP4 E02995 0 +OP4 E02996 0 +OP4 E02997 0 +OP4 E02998 0 +OP4 E02999 0 +OP4 E0299A 0 +OP4 E0299B 0 +OP4 E0299C 0 +OP4 E0299D 0 +OP4 E0299E 0 +OP4 E0299F 0 +OP4 E029A0 0 +OP4 E029A1 0 +OP4 E029A2 0 +OP4 E029A3 0 +OP4 E029A4 0 +OP4 E029A5 0 +OP4 E029A6 0 +OP4 E029A7 0 +OP4 E029A8 0 +OP4 E029A9 0 +OP4 E029AA 0 +OP4 E029AB 0 +OP4 E029AC 0 +OP4 E029AD 0 +OP4 E029AE 0 +OP4 E029AF 0 +OP4 E029B0 0 +OP4 E029B1 0 +OP4 E029B2 0 +OP4 E029B3 0 +OP4 E029B4 0 +OP4 E029B5 0 +OP4 E029B6 0 +OP4 E029B7 0 +OP4 E029B8 0 +OP4 E029B9 0 +OP4 E029BA 0 +OP4 E029BB 0 +OP4 E029BC 0 +OP4 E029BD 0 +OP4 E029BE 0 +OP4 E029BF 0 +OP4 E029C0 0 +OP4 E029C1 0 +OP4 E029C2 0 +OP4 E029C3 0 +OP4 E029C4 0 +OP4 E029C5 0 +OP4 E029C6 0 +OP4 E029C7 0 +OP4 E029C8 0 +OP4 E029C9 0 +OP4 E029CA 0 +OP4 E029CB 0 +OP4 E029CC 0 +OP4 E029CD 0 +OP4 E029CE 0 +OP4 E029CF 0 +OP4 E029D0 0 +OP4 E029D1 0 +OP4 E029D2 0 +OP4 E029D3 0 +OP4 E029D4 0 +OP4 E029D5 0 +OP4 E029D6 0 +OP4 E029D7 0 +OP4 E029D8 0 +OP4 E029D9 0 +OP4 E029DA 0 +OP4 E029DB 0 +OP4 E029DC 0 +OP4 E029DD 0 +OP4 E029DE 0 +OP4 E029DF 0 +OP4 E029E0 0 +OP4 E029E1 0 +OP4 E029E2 0 +OP4 E029E3 0 +OP4 E029E4 0 +OP4 E029E5 0 +OP4 E029E6 0 +OP4 E029E7 0 +OP4 E029E8 0 +OP4 E029E9 0 +OP4 E029EA 0 +OP4 E029EB 0 +OP4 E029EC 0 +OP4 E029ED 0 +OP4 E029EE 0 +OP4 E029EF 0 +OP4 E029F0 0 +OP4 E029F1 0 +OP4 E029F2 0 +OP4 E029F3 0 +OP4 E029F4 0 +OP4 E029F5 0 +OP4 E029F6 0 +OP4 E029F7 0 +OP4 E029F8 0 +OP4 E029F9 0 +OP4 E029FA 0 +OP4 E029FB 0 +OP4 E029FC 0 +OP4 E029FD 0 +OP4 E029FE 0 +OP4 E029FF 0 +OP4 E02A00 0 +OP4 E02A01 0 +OP4 E02A02 0 +OP4 E02A03 0 +OP4 E02A04 0 +OP4 E02A05 0 +OP4 E02A06 0 +OP4 E02A07 0 +OP4 E02A08 0 +OP4 E02A09 0 +OP4 E02A0A 0 +OP4 E02A0B 0 +OP4 E02A0C 0 +OP4 E02A0D 0 +OP4 E02A0E 0 +OP4 E02A0F 0 +OP4 E02A10 0 +OP4 E02A11 0 +OP4 E02A12 0 +OP4 E02A13 0 +OP4 E02A14 0 +OP4 E02A15 0 +OP4 E02A16 0 +OP4 E02A17 0 +OP4 E02A18 0 +OP4 E02A19 0 +OP4 E02A1A 0 +OP4 E02A1B 0 +OP4 E02A1C 0 +OP4 E02A1D 0 +OP4 E02A1E 0 +OP4 E02A1F 0 +OP4 E02A20 0 +OP4 E02A21 0 +OP4 E02A22 0 +OP4 E02A23 0 +OP4 E02A24 0 +OP4 E02A25 0 +OP4 E02A26 0 +OP4 E02A27 0 +OP4 E02A28 0 +OP4 E02A29 0 +OP4 E02A2A 0 +OP4 E02A2B 0 +OP4 E02A2C 0 +OP4 E02A2D 0 +OP4 E02A2E 0 +OP4 E02A2F 0 +OP4 E02A30 0 +OP4 E02A31 0 +OP4 E02A32 0 +OP4 E02A33 0 +OP4 E02A34 0 +OP4 E02A35 0 +OP4 E02A36 0 +OP4 E02A37 0 +OP4 E02A38 0 +OP4 E02A39 0 +OP4 E02A3A 0 +OP4 E02A3B 0 +OP4 E02A3C 0 +OP4 E02A3D 0 +OP4 E02A3E 0 +OP4 E02A3F 0 +OP4 E02A40 0 +OP4 E02A41 0 +OP4 E02A42 0 +OP4 E02A43 0 +OP4 E02A44 0 +OP4 E02A45 0 +OP4 E02A46 0 +OP4 E02A47 0 +OP4 E02A48 0 +OP4 E02A49 0 +OP4 E02A4A 0 +OP4 E02A4B 0 +OP4 E02A4C 0 +OP4 E02A4D 0 +OP4 E02A4E 0 +OP4 E02A4F 0 +OP4 E02A50 0 +OP4 E02A51 0 +OP4 E02A52 0 +OP4 E02A53 0 +OP4 E02A54 0 +OP4 E02A55 0 +OP4 E02A56 0 +OP4 E02A57 0 +OP4 E02A58 0 +OP4 E02A59 0 +OP4 E02A5A 0 +OP4 E02A5B 0 +OP4 E02A5C 0 +OP4 E02A5D 0 +OP4 E02A5E 0 +OP4 E02A5F 0 +OP4 E02A60 0 +OP4 E02A61 0 +OP4 E02A62 0 +OP4 E02A63 0 +OP4 E02A64 0 +OP4 E02A65 0 +OP4 E02A66 0 +OP4 E02A67 0 +OP4 E02A68 0 +OP4 E02A69 0 +OP4 E02A6A 0 +OP4 E02A6B 0 +OP4 E02A6C 0 +OP4 E02A6D 0 +OP4 E02A6E 0 +OP4 E02A6F 0 +OP4 E02A70 0 +OP4 E02A71 0 +OP4 E02A72 0 +OP4 E02A73 0 +OP4 E02A74 0 +OP4 E02A75 0 +OP4 E02A76 0 +OP4 E02A77 0 +OP4 E02A78 0 +OP4 E02A79 0 +OP4 E02A7A 0 +OP4 E02A7B 0 +OP4 E02A7C 0 +OP4 E02A7D 0 +OP4 E02A7E 0 +OP4 E02A7F 0 +OP4 E02A80 0 +OP4 E02A81 0 +OP4 E02A82 0 +OP4 E02A83 0 +OP4 E02A84 0 +OP4 E02A85 0 +OP4 E02A86 0 +OP4 E02A87 0 +OP4 E02A88 0 +OP4 E02A89 0 +OP4 E02A8A 0 +OP4 E02A8B 0 +OP4 E02A8C 0 +OP4 E02A8D 0 +OP4 E02A8E 0 +OP4 E02A8F 0 +OP4 E02A90 0 +OP4 E02A91 0 +OP4 E02A92 0 +OP4 E02A93 0 +OP4 E02A94 0 +OP4 E02A95 0 +OP4 E02A96 0 +OP4 E02A97 0 +OP4 E02A98 0 +OP4 E02A99 0 +OP4 E02A9A 0 +OP4 E02A9B 0 +OP4 E02A9C 0 +OP4 E02A9D 0 +OP4 E02A9E 0 +OP4 E02A9F 0 +OP4 E02AA0 0 +OP4 E02AA1 0 +OP4 E02AA2 0 +OP4 E02AA3 0 +OP4 E02AA4 0 +OP4 E02AA5 0 +OP4 E02AA6 0 +OP4 E02AA7 0 +OP4 E02AA8 0 +OP4 E02AA9 0 +OP4 E02AAA 0 +OP4 E02AAB 0 +OP4 E02AAC 0 +OP4 E02AAD 0 +OP4 E02AAE 0 +OP4 E02AAF 0 +OP4 E02AB0 0 +OP4 E02AB1 0 +OP4 E02AB2 0 +OP4 E02AB3 0 +OP4 E02AB4 0 +OP4 E02AB5 0 +OP4 E02AB6 0 +OP4 E02AB7 0 +OP4 E02AB8 0 +OP4 E02AB9 0 +OP4 E02ABA 0 +OP4 E02ABB 0 +OP4 E02ABC 0 +OP4 E02ABD 0 +OP4 E02ABE 0 +OP4 E02ABF 0 +OP4 E02AC0 0 +OP4 E02AC1 0 +OP4 E02AC2 0 +OP4 E02AC3 0 +OP4 E02AC4 0 +OP4 E02AC5 0 +OP4 E02AC6 0 +OP4 E02AC7 0 +OP4 E02AC8 0 +OP4 E02AC9 0 +OP4 E02ACA 0 +OP4 E02ACB 0 +OP4 E02ACC 0 +OP4 E02ACD 0 +OP4 E02ACE 0 +OP4 E02ACF 0 +OP4 E02AD0 0 +OP4 E02AD1 0 +OP4 E02AD2 0 +OP4 E02AD3 0 +OP4 E02AD4 0 +OP4 E02AD5 0 +OP4 E02AD6 0 +OP4 E02AD7 0 +OP4 E02AD8 0 +OP4 E02AD9 0 +OP4 E02ADA 0 +OP4 E02ADB 0 +OP4 E02ADC 0 +OP4 E02ADD 0 +OP4 E02ADE 0 +OP4 E02ADF 0 +OP4 E02AE0 0 +OP4 E02AE1 0 +OP4 E02AE2 0 +OP4 E02AE3 0 +OP4 E02AE4 0 +OP4 E02AE5 0 +OP4 E02AE6 0 +OP4 E02AE7 0 +OP4 E02AE8 0 +OP4 E02AE9 0 +OP4 E02AEA 0 +OP4 E02AEB 0 +OP4 E02AEC 0 +OP4 E02AED 0 +OP4 E02AEE 0 +OP4 E02AEF 0 +OP4 E02AF0 0 +OP4 E02AF1 0 +OP4 E02AF2 0 +OP4 E02AF3 0 +OP4 E02AF4 0 +OP4 E02AF5 0 +OP4 E02AF6 0 +OP4 E02AF7 0 +OP4 E02AF8 0 +OP4 E02AF9 0 +OP4 E02AFA 0 +OP4 E02AFB 0 +OP4 E02AFC 0 +OP4 E02AFD 0 +OP4 E02AFE 0 +OP4 E02AFF 0 +OP4 E02B00 0 +OP4 E02B01 0 +OP4 E02B02 0 +OP4 E02B03 0 +OP4 E02B04 0 +OP4 E02B05 0 +OP4 E02B06 0 +OP4 E02B07 0 +OP4 E02B08 0 +OP4 E02B09 0 +OP4 E02B0A 0 +OP4 E02B0B 0 +OP4 E02B0C 0 +OP4 E02B0D 0 +OP4 E02B0E 0 +OP4 E02B0F 0 +OP4 E02B10 0 +OP4 E02B11 0 +OP4 E02B12 0 +OP4 E02B13 0 +OP4 E02B14 0 +OP4 E02B15 0 +OP4 E02B16 0 +OP4 E02B17 0 +OP4 E02B18 0 +OP4 E02B19 0 +OP4 E02B1A 0 +OP4 E02B1B 0 +OP4 E02B1C 0 +OP4 E02B1D 0 +OP4 E02B1E 0 +OP4 E02B1F 0 +OP4 E02B20 0 +OP4 E02B21 0 +OP4 E02B22 0 +OP4 E02B23 0 +OP4 E02B24 0 +OP4 E02B25 0 +OP4 E02B26 0 +OP4 E02B27 0 +OP4 E02B28 0 +OP4 E02B29 0 +OP4 E02B2A 0 +OP4 E02B2B 0 +OP4 E02B2C 0 +OP4 E02B2D 0 +OP4 E02B2E 0 +OP4 E02B2F 0 +OP4 E02B30 0 +OP4 E02B31 0 +OP4 E02B32 0 +OP4 E02B33 0 +OP4 E02B34 0 +OP4 E02B35 0 +OP4 E02B36 0 +OP4 E02B37 0 +OP4 E02B38 0 +OP4 E02B39 0 +OP4 E02B3A 0 +OP4 E02B3B 0 +OP4 E02B3C 0 +OP4 E02B3D 0 +OP4 E02B3E 0 +OP4 E02B3F 0 +OP4 E02B40 0 +OP4 E02B41 0 +OP4 E02B42 0 +OP4 E02B43 0 +OP4 E02B44 0 +OP4 E02B45 0 +OP4 E02B46 0 +OP4 E02B47 0 +OP4 E02B48 0 +OP4 E02B49 0 +OP4 E02B4A 0 +OP4 E02B4B 0 +OP4 E02B4C 0 +OP4 E02B4D 0 +OP4 E02B4E 0 +OP4 E02B4F 0 +OP4 E02B50 0 +OP4 E02B51 0 +OP4 E02B52 0 +OP4 E02B53 0 +OP4 E02B54 0 +OP4 E02B55 0 +OP4 E02B56 0 +OP4 E02B57 0 +OP4 E02B58 0 +OP4 E02B59 0 +OP4 E02B5A 0 +OP4 E02B5B 0 +OP4 E02B5C 0 +OP4 E02B5D 0 +OP4 E02B5E 0 +OP4 E02B5F 0 +OP4 E02B60 0 +OP4 E02B61 0 +OP4 E02B62 0 +OP4 E02B63 0 +OP4 E02B64 0 +OP4 E02B65 0 +OP4 E02B66 0 +OP4 E02B67 0 +OP4 E02B68 0 +OP4 E02B69 0 +OP4 E02B6A 0 +OP4 E02B6B 0 +OP4 E02B6C 0 +OP4 E02B6D 0 +OP4 E02B6E 0 +OP4 E02B6F 0 +OP4 E02B70 0 +OP4 E02B71 0 +OP4 E02B72 0 +OP4 E02B73 0 +OP4 E02B74 0 +OP4 E02B75 0 +OP4 E02B76 0 +OP4 E02B77 0 +OP4 E02B78 0 +OP4 E02B79 0 +OP4 E02B7A 0 +OP4 E02B7B 0 +OP4 E02B7C 0 +OP4 E02B7D 0 +OP4 E02B7E 0 +OP4 E02B7F 0 +OP4 E02B80 0 +OP4 E02B81 0 +OP4 E02B82 0 +OP4 E02B83 0 +OP4 E02B84 0 +OP4 E02B85 0 +OP4 E02B86 0 +OP4 E02B87 0 +OP4 E02B88 0 +OP4 E02B89 0 +OP4 E02B8A 0 +OP4 E02B8B 0 +OP4 E02B8C 0 +OP4 E02B8D 0 +OP4 E02B8E 0 +OP4 E02B8F 0 +OP4 E02B90 0 +OP4 E02B91 0 +OP4 E02B92 0 +OP4 E02B93 0 +OP4 E02B94 0 +OP4 E02B95 0 +OP4 E02B96 0 +OP4 E02B97 0 +OP4 E02B98 0 +OP4 E02B99 0 +OP4 E02B9A 0 +OP4 E02B9B 0 +OP4 E02B9C 0 +OP4 E02B9D 0 +OP4 E02B9E 0 +OP4 E02B9F 0 +OP4 E02BA0 0 +OP4 E02BA1 0 +OP4 E02BA2 0 +OP4 E02BA3 0 +OP4 E02BA4 0 +OP4 E02BA5 0 +OP4 E02BA6 0 +OP4 E02BA7 0 +OP4 E02BA8 0 +OP4 E02BA9 0 +OP4 E02BAA 0 +OP4 E02BAB 0 +OP4 E02BAC 0 +OP4 E02BAD 0 +OP4 E02BAE 0 +OP4 E02BAF 0 +OP4 E02BB0 0 +OP4 E02BB1 0 +OP4 E02BB2 0 +OP4 E02BB3 0 +OP4 E02BB4 0 +OP4 E02BB5 0 +OP4 E02BB6 0 +OP4 E02BB7 0 +OP4 E02BB8 0 +OP4 E02BB9 0 +OP4 E02BBA 0 +OP4 E02BBB 0 +OP4 E02BBC 0 +OP4 E02BBD 0 +OP4 E02BBE 0 +OP4 E02BBF 0 +OP4 E02BC0 0 +OP4 E02BC1 0 +OP4 E02BC2 0 +OP4 E02BC3 0 +OP4 E02BC4 0 +OP4 E02BC5 0 +OP4 E02BC6 0 +OP4 E02BC7 0 +OP4 E02BC8 0 +OP4 E02BC9 0 +OP4 E02BCA 0 +OP4 E02BCB 0 +OP4 E02BCC 0 +OP4 E02BCD 0 +OP4 E02BCE 0 +OP4 E02BCF 0 +OP4 E02BD0 0 +OP4 E02BD1 0 +OP4 E02BD2 0 +OP4 E02BD3 0 +OP4 E02BD4 0 +OP4 E02BD5 0 +OP4 E02BD6 0 +OP4 E02BD7 0 +OP4 E02BD8 0 +OP4 E02BD9 0 +OP4 E02BDA 0 +OP4 E02BDB 0 +OP4 E02BDC 0 +OP4 E02BDD 0 +OP4 E02BDE 0 +OP4 E02BDF 0 +OP4 E02BE0 0 +OP4 E02BE1 0 +OP4 E02BE2 0 +OP4 E02BE3 0 +OP4 E02BE4 0 +OP4 E02BE5 0 +OP4 E02BE6 0 +OP4 E02BE7 0 +OP4 E02BE8 0 +OP4 E02BE9 0 +OP4 E02BEA 0 +OP4 E02BEB 0 +OP4 E02BEC 0 +OP4 E02BED 0 +OP4 E02BEE 0 +OP4 E02BEF 0 +OP4 E02BF0 0 +OP4 E02BF1 0 +OP4 E02BF2 0 +OP4 E02BF3 0 +OP4 E02BF4 0 +OP4 E02BF5 0 +OP4 E02BF6 0 +OP4 E02BF7 0 +OP4 E02BF8 0 +OP4 E02BF9 0 +OP4 E02BFA 0 +OP4 E02BFB 0 +OP4 E02BFC 0 +OP4 E02BFD 0 +OP4 E02BFE 0 +OP4 E02BFF 0 +OP4 E02C00 0 +OP4 E02C01 0 +OP4 E02C02 0 +OP4 E02C03 0 +OP4 E02C04 0 +OP4 E02C05 0 +OP4 E02C06 0 +OP4 E02C07 0 +OP4 E02C08 0 +OP4 E02C09 0 +OP4 E02C0A 0 +OP4 E02C0B 0 +OP4 E02C0C 0 +OP4 E02C0D 0 +OP4 E02C0E 0 +OP4 E02C0F 0 +OP4 E02C10 0 +OP4 E02C11 0 +OP4 E02C12 0 +OP4 E02C13 0 +OP4 E02C14 0 +OP4 E02C15 0 +OP4 E02C16 0 +OP4 E02C17 0 +OP4 E02C18 0 +OP4 E02C19 0 +OP4 E02C1A 0 +OP4 E02C1B 0 +OP4 E02C1C 0 +OP4 E02C1D 0 +OP4 E02C1E 0 +OP4 E02C1F 0 +OP4 E02C20 0 +OP4 E02C21 0 +OP4 E02C22 0 +OP4 E02C23 0 +OP4 E02C24 0 +OP4 E02C25 0 +OP4 E02C26 0 +OP4 E02C27 0 +OP4 E02C28 0 +OP4 E02C29 0 +OP4 E02C2A 0 +OP4 E02C2B 0 +OP4 E02C2C 0 +OP4 E02C2D 0 +OP4 E02C2E 0 +OP4 E02C2F 0 +OP4 E02C30 0 +OP4 E02C31 0 +OP4 E02C32 0 +OP4 E02C33 0 +OP4 E02C34 0 +OP4 E02C35 0 +OP4 E02C36 0 +OP4 E02C37 0 +OP4 E02C38 0 +OP4 E02C39 0 +OP4 E02C3A 0 +OP4 E02C3B 0 +OP4 E02C3C 0 +OP4 E02C3D 0 +OP4 E02C3E 0 +OP4 E02C3F 0 +OP4 E02C40 0 +OP4 E02C41 0 +OP4 E02C42 0 +OP4 E02C43 0 +OP4 E02C44 0 +OP4 E02C45 0 +OP4 E02C46 0 +OP4 E02C47 0 +OP4 E02C48 0 +OP4 E02C49 0 +OP4 E02C4A 0 +OP4 E02C4B 0 +OP4 E02C4C 0 +OP4 E02C4D 0 +OP4 E02C4E 0 +OP4 E02C4F 0 +OP4 E02C50 0 +OP4 E02C51 0 +OP4 E02C52 0 +OP4 E02C53 0 +OP4 E02C54 0 +OP4 E02C55 0 +OP4 E02C56 0 +OP4 E02C57 0 +OP4 E02C58 0 +OP4 E02C59 0 +OP4 E02C5A 0 +OP4 E02C5B 0 +OP4 E02C5C 0 +OP4 E02C5D 0 +OP4 E02C5E 0 +OP4 E02C5F 0 +OP4 E02C60 0 +OP4 E02C61 0 +OP4 E02C62 0 +OP4 E02C63 0 +OP4 E02C64 0 +OP4 E02C65 0 +OP4 E02C66 0 +OP4 E02C67 0 +OP4 E02C68 0 +OP4 E02C69 0 +OP4 E02C6A 0 +OP4 E02C6B 0 +OP4 E02C6C 0 +OP4 E02C6D 0 +OP4 E02C6E 0 +OP4 E02C6F 0 +OP4 E02C70 0 +OP4 E02C71 0 +OP4 E02C72 0 +OP4 E02C73 0 +OP4 E02C74 0 +OP4 E02C75 0 +OP4 E02C76 0 +OP4 E02C77 0 +OP4 E02C78 0 +OP4 E02C79 0 +OP4 E02C7A 0 +OP4 E02C7B 0 +OP4 E02C7C 0 +OP4 E02C7D 0 +OP4 E02C7E 0 +OP4 E02C7F 0 +OP4 E02C80 0 +OP4 E02C81 0 +OP4 E02C82 0 +OP4 E02C83 0 +OP4 E02C84 0 +OP4 E02C85 0 +OP4 E02C86 0 +OP4 E02C87 0 +OP4 E02C88 0 +OP4 E02C89 0 +OP4 E02C8A 0 +OP4 E02C8B 0 +OP4 E02C8C 0 +OP4 E02C8D 0 +OP4 E02C8E 0 +OP4 E02C8F 0 +OP4 E02C90 0 +OP4 E02C91 0 +OP4 E02C92 0 +OP4 E02C93 0 +OP4 E02C94 0 +OP4 E02C95 0 +OP4 E02C96 0 +OP4 E02C97 0 +OP4 E02C98 0 +OP4 E02C99 0 +OP4 E02C9A 0 +OP4 E02C9B 0 +OP4 E02C9C 0 +OP4 E02C9D 0 +OP4 E02C9E 0 +OP4 E02C9F 0 +OP4 E02CA0 0 +OP4 E02CA1 0 +OP4 E02CA2 0 +OP4 E02CA3 0 +OP4 E02CA4 0 +OP4 E02CA5 0 +OP4 E02CA6 0 +OP4 E02CA7 0 +OP4 E02CA8 0 +OP4 E02CA9 0 +OP4 E02CAA 0 +OP4 E02CAB 0 +OP4 E02CAC 0 +OP4 E02CAD 0 +OP4 E02CAE 0 +OP4 E02CAF 0 +OP4 E02CB0 0 +OP4 E02CB1 0 +OP4 E02CB2 0 +OP4 E02CB3 0 +OP4 E02CB4 0 +OP4 E02CB5 0 +OP4 E02CB6 0 +OP4 E02CB7 0 +OP4 E02CB8 0 +OP4 E02CB9 0 +OP4 E02CBA 0 +OP4 E02CBB 0 +OP4 E02CBC 0 +OP4 E02CBD 0 +OP4 E02CBE 0 +OP4 E02CBF 0 +OP4 E02CC0 0 +OP4 E02CC1 0 +OP4 E02CC2 0 +OP4 E02CC3 0 +OP4 E02CC4 0 +OP4 E02CC5 0 +OP4 E02CC6 0 +OP4 E02CC7 0 +OP4 E02CC8 0 +OP4 E02CC9 0 +OP4 E02CCA 0 +OP4 E02CCB 0 +OP4 E02CCC 0 +OP4 E02CCD 0 +OP4 E02CCE 0 +OP4 E02CCF 0 +OP4 E02CD0 0 +OP4 E02CD1 0 +OP4 E02CD2 0 +OP4 E02CD3 0 +OP4 E02CD4 0 +OP4 E02CD5 0 +OP4 E02CD6 0 +OP4 E02CD7 0 +OP4 E02CD8 0 +OP4 E02CD9 0 +OP4 E02CDA 0 +OP4 E02CDB 0 +OP4 E02CDC 0 +OP4 E02CDD 0 +OP4 E02CDE 0 +OP4 E02CDF 0 +OP4 E02CE0 0 +OP4 E02CE1 0 +OP4 E02CE2 0 +OP4 E02CE3 0 +OP4 E02CE4 0 +OP4 E02CE5 0 +OP4 E02CE6 0 +OP4 E02CE7 0 +OP4 E02CE8 0 +OP4 E02CE9 0 +OP4 E02CEA 0 +OP4 E02CEB 0 +OP4 E02CEC 0 +OP4 E02CED 0 +OP4 E02CEE 0 +OP4 E02CEF 0 +OP4 E02CF0 0 +OP4 E02CF1 0 +OP4 E02CF2 0 +OP4 E02CF3 0 +OP4 E02CF4 0 +OP4 E02CF5 0 +OP4 E02CF6 0 +OP4 E02CF7 0 +OP4 E02CF8 0 +OP4 E02CF9 0 +OP4 E02CFA 0 +OP4 E02CFB 0 +OP4 E02CFC 0 +OP4 E02CFD 0 +OP4 E02CFE 0 +OP4 E02CFF 0 +OP4 E02D00 0 +OP4 E02D01 0 +OP4 E02D02 0 +OP4 E02D03 0 +OP4 E02D04 0 +OP4 E02D05 0 +OP4 E02D06 0 +OP4 E02D07 0 +OP4 E02D08 0 +OP4 E02D09 0 +OP4 E02D0A 0 +OP4 E02D0B 0 +OP4 E02D0C 0 +OP4 E02D0D 0 +OP4 E02D0E 0 +OP4 E02D0F 0 +OP4 E02D10 0 +OP4 E02D11 0 +OP4 E02D12 0 +OP4 E02D13 0 +OP4 E02D14 0 +OP4 E02D15 0 +OP4 E02D16 0 +OP4 E02D17 0 +OP4 E02D18 0 +OP4 E02D19 0 +OP4 E02D1A 0 +OP4 E02D1B 0 +OP4 E02D1C 0 +OP4 E02D1D 0 +OP4 E02D1E 0 +OP4 E02D1F 0 +OP4 E02D20 0 +OP4 E02D21 0 +OP4 E02D22 0 +OP4 E02D23 0 +OP4 E02D24 0 +OP4 E02D25 0 +OP4 E02D26 0 +OP4 E02D27 0 +OP4 E02D28 0 +OP4 E02D29 0 +OP4 E02D2A 0 +OP4 E02D2B 0 +OP4 E02D2C 0 +OP4 E02D2D 0 +OP4 E02D2E 0 +OP4 E02D2F 0 +OP4 E02D30 0 +OP4 E02D31 0 +OP4 E02D32 0 +OP4 E02D33 0 +OP4 E02D34 0 +OP4 E02D35 0 +OP4 E02D36 0 +OP4 E02D37 0 +OP4 E02D38 0 +OP4 E02D39 0 +OP4 E02D3A 0 +OP4 E02D3B 0 +OP4 E02D3C 0 +OP4 E02D3D 0 +OP4 E02D3E 0 +OP4 E02D3F 0 +OP4 E02D40 0 +OP4 E02D41 0 +OP4 E02D42 0 +OP4 E02D43 0 +OP4 E02D44 0 +OP4 E02D45 0 +OP4 E02D46 0 +OP4 E02D47 0 +OP4 E02D48 0 +OP4 E02D49 0 +OP4 E02D4A 0 +OP4 E02D4B 0 +OP4 E02D4C 0 +OP4 E02D4D 0 +OP4 E02D4E 0 +OP4 E02D4F 0 +OP4 E02D50 0 +OP4 E02D51 0 +OP4 E02D52 0 +OP4 E02D53 0 +OP4 E02D54 0 +OP4 E02D55 0 +OP4 E02D56 0 +OP4 E02D57 0 +OP4 E02D58 0 +OP4 E02D59 0 +OP4 E02D5A 0 +OP4 E02D5B 0 +OP4 E02D5C 0 +OP4 E02D5D 0 +OP4 E02D5E 0 +OP4 E02D5F 0 +OP4 E02D60 0 +OP4 E02D61 0 +OP4 E02D62 0 +OP4 E02D63 0 +OP4 E02D64 0 +OP4 E02D65 0 +OP4 E02D66 0 +OP4 E02D67 0 +OP4 E02D68 0 +OP4 E02D69 0 +OP4 E02D6A 0 +OP4 E02D6B 0 +OP4 E02D6C 0 +OP4 E02D6D 0 +OP4 E02D6E 0 +OP4 E02D6F 0 +OP4 E02D70 0 +OP4 E02D71 0 +OP4 E02D72 0 +OP4 E02D73 0 +OP4 E02D74 0 +OP4 E02D75 0 +OP4 E02D76 0 +OP4 E02D77 0 +OP4 E02D78 0 +OP4 E02D79 0 +OP4 E02D7A 0 +OP4 E02D7B 0 +OP4 E02D7C 0 +OP4 E02D7D 0 +OP4 E02D7E 0 +OP4 E02D7F 0 +OP4 E02D80 0 +OP4 E02D81 0 +OP4 E02D82 0 +OP4 E02D83 0 +OP4 E02D84 0 +OP4 E02D85 0 +OP4 E02D86 0 +OP4 E02D87 0 +OP4 E02D88 0 +OP4 E02D89 0 +OP4 E02D8A 0 +OP4 E02D8B 0 +OP4 E02D8C 0 +OP4 E02D8D 0 +OP4 E02D8E 0 +OP4 E02D8F 0 +OP4 E02D90 0 +OP4 E02D91 0 +OP4 E02D92 0 +OP4 E02D93 0 +OP4 E02D94 0 +OP4 E02D95 0 +OP4 E02D96 0 +OP4 E02D97 0 +OP4 E02D98 0 +OP4 E02D99 0 +OP4 E02D9A 0 +OP4 E02D9B 0 +OP4 E02D9C 0 +OP4 E02D9D 0 +OP4 E02D9E 0 +OP4 E02D9F 0 +OP4 E02DA0 0 +OP4 E02DA1 0 +OP4 E02DA2 0 +OP4 E02DA3 0 +OP4 E02DA4 0 +OP4 E02DA5 0 +OP4 E02DA6 0 +OP4 E02DA7 0 +OP4 E02DA8 0 +OP4 E02DA9 0 +OP4 E02DAA 0 +OP4 E02DAB 0 +OP4 E02DAC 0 +OP4 E02DAD 0 +OP4 E02DAE 0 +OP4 E02DAF 0 +OP4 E02DB0 0 +OP4 E02DB1 0 +OP4 E02DB2 0 +OP4 E02DB3 0 +OP4 E02DB4 0 +OP4 E02DB5 0 +OP4 E02DB6 0 +OP4 E02DB7 0 +OP4 E02DB8 0 +OP4 E02DB9 0 +OP4 E02DBA 0 +OP4 E02DBB 0 +OP4 E02DBC 0 +OP4 E02DBD 0 +OP4 E02DBE 0 +OP4 E02DBF 0 +OP4 E02DC0 0 +OP4 E02DC1 0 +OP4 E02DC2 0 +OP4 E02DC3 0 +OP4 E02DC4 0 +OP4 E02DC5 0 +OP4 E02DC6 0 +OP4 E02DC7 0 +OP4 E02DC8 0 +OP4 E02DC9 0 +OP4 E02DCA 0 +OP4 E02DCB 0 +OP4 E02DCC 0 +OP4 E02DCD 0 +OP4 E02DCE 0 +OP4 E02DCF 0 +OP4 E02DD0 0 +OP4 E02DD1 0 +OP4 E02DD2 0 +OP4 E02DD3 0 +OP4 E02DD4 0 +OP4 E02DD5 0 +OP4 E02DD6 0 +OP4 E02DD7 0 +OP4 E02DD8 0 +OP4 E02DD9 0 +OP4 E02DDA 0 +OP4 E02DDB 0 +OP4 E02DDC 0 +OP4 E02DDD 0 +OP4 E02DDE 0 +OP4 E02DDF 0 +OP4 E02DE0 0 +OP4 E02DE1 0 +OP4 E02DE2 0 +OP4 E02DE3 0 +OP4 E02DE4 0 +OP4 E02DE5 0 +OP4 E02DE6 0 +OP4 E02DE7 0 +OP4 E02DE8 0 +OP4 E02DE9 0 +OP4 E02DEA 0 +OP4 E02DEB 0 +OP4 E02DEC 0 +OP4 E02DED 0 +OP4 E02DEE 0 +OP4 E02DEF 0 +OP4 E02DF0 0 +OP4 E02DF1 0 +OP4 E02DF2 0 +OP4 E02DF3 0 +OP4 E02DF4 0 +OP4 E02DF5 0 +OP4 E02DF6 0 +OP4 E02DF7 0 +OP4 E02DF8 0 +OP4 E02DF9 0 +OP4 E02DFA 0 +OP4 E02DFB 0 +OP4 E02DFC 0 +OP4 E02DFD 0 +OP4 E02DFE 0 +OP4 E02DFF 0 +OP4 E02E00 0 +OP4 E02E01 0 +OP4 E02E02 0 +OP4 E02E03 0 +OP4 E02E04 0 +OP4 E02E05 0 +OP4 E02E06 0 +OP4 E02E07 0 +OP4 E02E08 0 +OP4 E02E09 0 +OP4 E02E0A 0 +OP4 E02E0B 0 +OP4 E02E0C 0 +OP4 E02E0D 0 +OP4 E02E0E 0 +OP4 E02E0F 0 +OP4 E02E10 0 +OP4 E02E11 0 +OP4 E02E12 0 +OP4 E02E13 0 +OP4 E02E14 0 +OP4 E02E15 0 +OP4 E02E16 0 +OP4 E02E17 0 +OP4 E02E18 0 +OP4 E02E19 0 +OP4 E02E1A 0 +OP4 E02E1B 0 +OP4 E02E1C 0 +OP4 E02E1D 0 +OP4 E02E1E 0 +OP4 E02E1F 0 +OP4 E02E20 0 +OP4 E02E21 0 +OP4 E02E22 0 +OP4 E02E23 0 +OP4 E02E24 0 +OP4 E02E25 0 +OP4 E02E26 0 +OP4 E02E27 0 +OP4 E02E28 0 +OP4 E02E29 0 +OP4 E02E2A 0 +OP4 E02E2B 0 +OP4 E02E2C 0 +OP4 E02E2D 0 +OP4 E02E2E 0 +OP4 E02E2F 0 +OP4 E02E30 0 +OP4 E02E31 0 +OP4 E02E32 0 +OP4 E02E33 0 +OP4 E02E34 0 +OP4 E02E35 0 +OP4 E02E36 0 +OP4 E02E37 0 +OP4 E02E38 0 +OP4 E02E39 0 +OP4 E02E3A 0 +OP4 E02E3B 0 +OP4 E02E3C 0 +OP4 E02E3D 0 +OP4 E02E3E 0 +OP4 E02E3F 0 +OP4 E02E40 0 +OP4 E02E41 0 +OP4 E02E42 0 +OP4 E02E43 0 +OP4 E02E44 0 +OP4 E02E45 0 +OP4 E02E46 0 +OP4 E02E47 0 +OP4 E02E48 0 +OP4 E02E49 0 +OP4 E02E4A 0 +OP4 E02E4B 0 +OP4 E02E4C 0 +OP4 E02E4D 0 +OP4 E02E4E 0 +OP4 E02E4F 0 +OP4 E02E50 0 +OP4 E02E51 0 +OP4 E02E52 0 +OP4 E02E53 0 +OP4 E02E54 0 +OP4 E02E55 0 +OP4 E02E56 0 +OP4 E02E57 0 +OP4 E02E58 0 +OP4 E02E59 0 +OP4 E02E5A 0 +OP4 E02E5B 0 +OP4 E02E5C 0 +OP4 E02E5D 0 +OP4 E02E5E 0 +OP4 E02E5F 0 +OP4 E02E60 0 +OP4 E02E61 0 +OP4 E02E62 0 +OP4 E02E63 0 +OP4 E02E64 0 +OP4 E02E65 0 +OP4 E02E66 0 +OP4 E02E67 0 +OP4 E02E68 0 +OP4 E02E69 0 +OP4 E02E6A 0 +OP4 E02E6B 0 +OP4 E02E6C 0 +OP4 E02E6D 0 +OP4 E02E6E 0 +OP4 E02E6F 0 +OP4 E02E70 0 +OP4 E02E71 0 +OP4 E02E72 0 +OP4 E02E73 0 +OP4 E02E74 0 +OP4 E02E75 0 +OP4 E02E76 0 +OP4 E02E77 0 +OP4 E02E78 0 +OP4 E02E79 0 +OP4 E02E7A 0 +OP4 E02E7B 0 +OP4 E02E7C 0 +OP4 E02E7D 0 +OP4 E02E7E 0 +OP4 E02E7F 0 +OP4 E02E80 0 +OP4 E02E81 0 +OP4 E02E82 0 +OP4 E02E83 0 +OP4 E02E84 0 +OP4 E02E85 0 +OP4 E02E86 0 +OP4 E02E87 0 +OP4 E02E88 0 +OP4 E02E89 0 +OP4 E02E8A 0 +OP4 E02E8B 0 +OP4 E02E8C 0 +OP4 E02E8D 0 +OP4 E02E8E 0 +OP4 E02E8F 0 +OP4 E02E90 0 +OP4 E02E91 0 +OP4 E02E92 0 +OP4 E02E93 0 +OP4 E02E94 0 +OP4 E02E95 0 +OP4 E02E96 0 +OP4 E02E97 0 +OP4 E02E98 0 +OP4 E02E99 0 +OP4 E02E9A 0 +OP4 E02E9B 0 +OP4 E02E9C 0 +OP4 E02E9D 0 +OP4 E02E9E 0 +OP4 E02E9F 0 +OP4 E02EA0 0 +OP4 E02EA1 0 +OP4 E02EA2 0 +OP4 E02EA3 0 +OP4 E02EA4 0 +OP4 E02EA5 0 +OP4 E02EA6 0 +OP4 E02EA7 0 +OP4 E02EA8 0 +OP4 E02EA9 0 +OP4 E02EAA 0 +OP4 E02EAB 0 +OP4 E02EAC 0 +OP4 E02EAD 0 +OP4 E02EAE 0 +OP4 E02EAF 0 +OP4 E02EB0 0 +OP4 E02EB1 0 +OP4 E02EB2 0 +OP4 E02EB3 0 +OP4 E02EB4 0 +OP4 E02EB5 0 +OP4 E02EB6 0 +OP4 E02EB7 0 +OP4 E02EB8 0 +OP4 E02EB9 0 +OP4 E02EBA 0 +OP4 E02EBB 0 +OP4 E02EBC 0 +OP4 E02EBD 0 +OP4 E02EBE 0 +OP4 E02EBF 0 +OP4 E02EC0 0 +OP4 E02EC1 0 +OP4 E02EC2 0 +OP4 E02EC3 0 +OP4 E02EC4 0 +OP4 E02EC5 0 +OP4 E02EC6 0 +OP4 E02EC7 0 +OP4 E02EC8 0 +OP4 E02EC9 0 +OP4 E02ECA 0 +OP4 E02ECB 0 +OP4 E02ECC 0 +OP4 E02ECD 0 +OP4 E02ECE 0 +OP4 E02ECF 0 +OP4 E02ED0 0 +OP4 E02ED1 0 +OP4 E02ED2 0 +OP4 E02ED3 0 +OP4 E02ED4 0 +OP4 E02ED5 0 +OP4 E02ED6 0 +OP4 E02ED7 0 +OP4 E02ED8 0 +OP4 E02ED9 0 +OP4 E02EDA 0 +OP4 E02EDB 0 +OP4 E02EDC 0 +OP4 E02EDD 0 +OP4 E02EDE 0 +OP4 E02EDF 0 +OP4 E02EE0 0 +OP4 E02EE1 0 +OP4 E02EE2 0 +OP4 E02EE3 0 +OP4 E02EE4 0 +OP4 E02EE5 0 +OP4 E02EE6 0 +OP4 E02EE7 0 +OP4 E02EE8 0 +OP4 E02EE9 0 +OP4 E02EEA 0 +OP4 E02EEB 0 +OP4 E02EEC 0 +OP4 E02EED 0 +OP4 E02EEE 0 +OP4 E02EEF 0 +OP4 E02EF0 0 +OP4 E02EF1 0 +OP4 E02EF2 0 +OP4 E02EF3 0 +OP4 E02EF4 0 +OP4 E02EF5 0 +OP4 E02EF6 0 +OP4 E02EF7 0 +OP4 E02EF8 0 +OP4 E02EF9 0 +OP4 E02EFA 0 +OP4 E02EFB 0 +OP4 E02EFC 0 +OP4 E02EFD 0 +OP4 E02EFE 0 +OP4 E02EFF 0 +OP4 E02F00 0 +OP4 E02F01 0 +OP4 E02F02 0 +OP4 E02F03 0 +OP4 E02F04 0 +OP4 E02F05 0 +OP4 E02F06 0 +OP4 E02F07 0 +OP4 E02F08 0 +OP4 E02F09 0 +OP4 E02F0A 0 +OP4 E02F0B 0 +OP4 E02F0C 0 +OP4 E02F0D 0 +OP4 E02F0E 0 +OP4 E02F0F 0 +OP4 E02F10 0 +OP4 E02F11 0 +OP4 E02F12 0 +OP4 E02F13 0 +OP4 E02F14 0 +OP4 E02F15 0 +OP4 E02F16 0 +OP4 E02F17 0 +OP4 E02F18 0 +OP4 E02F19 0 +OP4 E02F1A 0 +OP4 E02F1B 0 +OP4 E02F1C 0 +OP4 E02F1D 0 +OP4 E02F1E 0 +OP4 E02F1F 0 +OP4 E02F20 0 +OP4 E02F21 0 +OP4 E02F22 0 +OP4 E02F23 0 +OP4 E02F24 0 +OP4 E02F25 0 +OP4 E02F26 0 +OP4 E02F27 0 +OP4 E02F28 0 +OP4 E02F29 0 +OP4 E02F2A 0 +OP4 E02F2B 0 +OP4 E02F2C 0 +OP4 E02F2D 0 +OP4 E02F2E 0 +OP4 E02F2F 0 +OP4 E02F30 0 +OP4 E02F31 0 +OP4 E02F32 0 +OP4 E02F33 0 +OP4 E02F34 0 +OP4 E02F35 0 +OP4 E02F36 0 +OP4 E02F37 0 +OP4 E02F38 0 +OP4 E02F39 0 +OP4 E02F3A 0 +OP4 E02F3B 0 +OP4 E02F3C 0 +OP4 E02F3D 0 +OP4 E02F3E 0 +OP4 E02F3F 0 +OP4 E02F40 0 +OP4 E02F41 0 +OP4 E02F42 0 +OP4 E02F43 0 +OP4 E02F44 0 +OP4 E02F45 0 +OP4 E02F46 0 +OP4 E02F47 0 +OP4 E02F48 0 +OP4 E02F49 0 +OP4 E02F4A 0 +OP4 E02F4B 0 +OP4 E02F4C 0 +OP4 E02F4D 0 +OP4 E02F4E 0 +OP4 E02F4F 0 +OP4 E02F50 0 +OP4 E02F51 0 +OP4 E02F52 0 +OP4 E02F53 0 +OP4 E02F54 0 +OP4 E02F55 0 +OP4 E02F56 0 +OP4 E02F57 0 +OP4 E02F58 0 +OP4 E02F59 0 +OP4 E02F5A 0 +OP4 E02F5B 0 +OP4 E02F5C 0 +OP4 E02F5D 0 +OP4 E02F5E 0 +OP4 E02F5F 0 +OP4 E02F60 0 +OP4 E02F61 0 +OP4 E02F62 0 +OP4 E02F63 0 +OP4 E02F64 0 +OP4 E02F65 0 +OP4 E02F66 0 +OP4 E02F67 0 +OP4 E02F68 0 +OP4 E02F69 0 +OP4 E02F6A 0 +OP4 E02F6B 0 +OP4 E02F6C 0 +OP4 E02F6D 0 +OP4 E02F6E 0 +OP4 E02F6F 0 +OP4 E02F70 0 +OP4 E02F71 0 +OP4 E02F72 0 +OP4 E02F73 0 +OP4 E02F74 0 +OP4 E02F75 0 +OP4 E02F76 0 +OP4 E02F77 0 +OP4 E02F78 0 +OP4 E02F79 0 +OP4 E02F7A 0 +OP4 E02F7B 0 +OP4 E02F7C 0 +OP4 E02F7D 0 +OP4 E02F7E 0 +OP4 E02F7F 0 +OP4 E02F80 0 +OP4 E02F81 0 +OP4 E02F82 0 +OP4 E02F83 0 +OP4 E02F84 0 +OP4 E02F85 0 +OP4 E02F86 0 +OP4 E02F87 0 +OP4 E02F88 0 +OP4 E02F89 0 +OP4 E02F8A 0 +OP4 E02F8B 0 +OP4 E02F8C 0 +OP4 E02F8D 0 +OP4 E02F8E 0 +OP4 E02F8F 0 +OP4 E02F90 0 +OP4 E02F91 0 +OP4 E02F92 0 +OP4 E02F93 0 +OP4 E02F94 0 +OP4 E02F95 0 +OP4 E02F96 0 +OP4 E02F97 0 +OP4 E02F98 0 +OP4 E02F99 0 +OP4 E02F9A 0 +OP4 E02F9B 0 +OP4 E02F9C 0 +OP4 E02F9D 0 +OP4 E02F9E 0 +OP4 E02F9F 0 +OP4 E02FA0 0 +OP4 E02FA1 0 +OP4 E02FA2 0 +OP4 E02FA3 0 +OP4 E02FA4 0 +OP4 E02FA5 0 +OP4 E02FA6 0 +OP4 E02FA7 0 +OP4 E02FA8 0 +OP4 E02FA9 0 +OP4 E02FAA 0 +OP4 E02FAB 0 +OP4 E02FAC 0 +OP4 E02FAD 0 +OP4 E02FAE 0 +OP4 E02FAF 0 +OP4 E02FB0 0 +OP4 E02FB1 0 +OP4 E02FB2 0 +OP4 E02FB3 0 +OP4 E02FB4 0 +OP4 E02FB5 0 +OP4 E02FB6 0 +OP4 E02FB7 0 +OP4 E02FB8 0 +OP4 E02FB9 0 +OP4 E02FBA 0 +OP4 E02FBB 0 +OP4 E02FBC 0 +OP4 E02FBD 0 +OP4 E02FBE 0 +OP4 E02FBF 0 +OP4 E02FC0 0 +OP4 E02FC1 0 +OP4 E02FC2 0 +OP4 E02FC3 0 +OP4 E02FC4 0 +OP4 E02FC5 0 +OP4 E02FC6 0 +OP4 E02FC7 0 +OP4 E02FC8 0 +OP4 E02FC9 0 +OP4 E02FCA 0 +OP4 E02FCB 0 +OP4 E02FCC 0 +OP4 E02FCD 0 +OP4 E02FCE 0 +OP4 E02FCF 0 +OP4 E02FD0 0 +OP4 E02FD1 0 +OP4 E02FD2 0 +OP4 E02FD3 0 +OP4 E02FD4 0 +OP4 E02FD5 0 +OP4 E02FD6 0 +OP4 E02FD7 0 +OP4 E02FD8 0 +OP4 E02FD9 0 +OP4 E02FDA 0 +OP4 E02FDB 0 +OP4 E02FDC 0 +OP4 E02FDD 0 +OP4 E02FDE 0 +OP4 E02FDF 0 +OP4 E02FE0 0 +OP4 E02FE1 0 +OP4 E02FE2 0 +OP4 E02FE3 0 +OP4 E02FE4 0 +OP4 E02FE5 0 +OP4 E02FE6 0 +OP4 E02FE7 0 +OP4 E02FE8 0 +OP4 E02FE9 0 +OP4 E02FEA 0 +OP4 E02FEB 0 +OP4 E02FEC 0 +OP4 E02FED 0 +OP4 E02FEE 0 +OP4 E02FEF 0 +OP4 E02FF0 0 +OP4 E02FF1 0 +OP4 E02FF2 0 +OP4 E02FF3 0 +OP4 E02FF4 0 +OP4 E02FF5 0 +OP4 E02FF6 0 +OP4 E02FF7 0 +OP4 E02FF8 0 +OP4 E02FF9 0 +OP4 E02FFA 0 +OP4 E02FFB 0 +OP4 E02FFC 0 +OP4 E02FFD 0 +OP4 E02FFE 0 +OP4 E02FFF 0 +OP4 E03000 0 +OP4 E03001 0 +OP4 E03002 0 +OP4 E03003 0 +OP4 E03004 0 +OP4 E03005 0 +OP4 E03006 0 +OP4 E03007 0 +OP4 E03008 0 +OP4 E03009 0 +OP4 E0300A 0 +OP4 E0300B 0 +OP4 E0300C 0 +OP4 E0300D 0 +OP4 E0300E 0 +OP4 E0300F 0 +OP4 E03010 0 +OP4 E03011 0 +OP4 E03012 0 +OP4 E03013 0 +OP4 E03014 0 +OP4 E03015 0 +OP4 E03016 0 +OP4 E03017 0 +OP4 E03018 0 +OP4 E03019 0 +OP4 E0301A 0 +OP4 E0301B 0 +OP4 E0301C 0 +OP4 E0301D 0 +OP4 E0301E 0 +OP4 E0301F 0 +OP4 E03020 0 +OP4 E03021 0 +OP4 E03022 0 +OP4 E03023 0 +OP4 E03024 0 +OP4 E03025 0 +OP4 E03026 0 +OP4 E03027 0 +OP4 E03028 0 +OP4 E03029 0 +OP4 E0302A 0 +OP4 E0302B 0 +OP4 E0302C 0 +OP4 E0302D 0 +OP4 E0302E 0 +OP4 E0302F 0 +OP4 E03030 0 +OP4 E03031 0 +OP4 E03032 0 +OP4 E03033 0 +OP4 E03034 0 +OP4 E03035 0 +OP4 E03036 0 +OP4 E03037 0 +OP4 E03038 0 +OP4 E03039 0 +OP4 E0303A 0 +OP4 E0303B 0 +OP4 E0303C 0 +OP4 E0303D 0 +OP4 E0303E 0 +OP4 E0303F 0 +OP4 E03040 0 +OP4 E03041 0 +OP4 E03042 0 +OP4 E03043 0 +OP4 E03044 0 +OP4 E03045 0 +OP4 E03046 0 +OP4 E03047 0 +OP4 E03048 0 +OP4 E03049 0 +OP4 E0304A 0 +OP4 E0304B 0 +OP4 E0304C 0 +OP4 E0304D 0 +OP4 E0304E 0 +OP4 E0304F 0 +OP4 E03050 0 +OP4 E03051 0 +OP4 E03052 0 +OP4 E03053 0 +OP4 E03054 0 +OP4 E03055 0 +OP4 E03056 0 +OP4 E03057 0 +OP4 E03058 0 +OP4 E03059 0 +OP4 E0305A 0 +OP4 E0305B 0 +OP4 E0305C 0 +OP4 E0305D 0 +OP4 E0305E 0 +OP4 E0305F 0 +OP4 E03060 0 +OP4 E03061 0 +OP4 E03062 0 +OP4 E03063 0 +OP4 E03064 0 +OP4 E03065 0 +OP4 E03066 0 +OP4 E03067 0 +OP4 E03068 0 +OP4 E03069 0 +OP4 E0306A 0 +OP4 E0306B 0 +OP4 E0306C 0 +OP4 E0306D 0 +OP4 E0306E 0 +OP4 E0306F 0 +OP4 E03070 0 +OP4 E03071 0 +OP4 E03072 0 +OP4 E03073 0 +OP4 E03074 0 +OP4 E03075 0 +OP4 E03076 0 +OP4 E03077 0 +OP4 E03078 0 +OP4 E03079 0 +OP4 E0307A 0 +OP4 E0307B 0 +OP4 E0307C 0 +OP4 E0307D 0 +OP4 E0307E 0 +OP4 E0307F 0 +OP4 E03080 0 +OP4 E03081 0 +OP4 E03082 0 +OP4 E03083 0 +OP4 E03084 0 +OP4 E03085 0 +OP4 E03086 0 +OP4 E03087 0 +OP4 E03088 0 +OP4 E03089 0 +OP4 E0308A 0 +OP4 E0308B 0 +OP4 E0308C 0 +OP4 E0308D 0 +OP4 E0308E 0 +OP4 E0308F 0 +OP4 E03090 0 +OP4 E03091 0 +OP4 E03092 0 +OP4 E03093 0 +OP4 E03094 0 +OP4 E03095 0 +OP4 E03096 0 +OP4 E03097 0 +OP4 E03098 0 +OP4 E03099 0 +OP4 E0309A 0 +OP4 E0309B 0 +OP4 E0309C 0 +OP4 E0309D 0 +OP4 E0309E 0 +OP4 E0309F 0 +OP4 E030A0 0 +OP4 E030A1 0 +OP4 E030A2 0 +OP4 E030A3 0 +OP4 E030A4 0 +OP4 E030A5 0 +OP4 E030A6 0 +OP4 E030A7 0 +OP4 E030A8 0 +OP4 E030A9 0 +OP4 E030AA 0 +OP4 E030AB 0 +OP4 E030AC 0 +OP4 E030AD 0 +OP4 E030AE 0 +OP4 E030AF 0 +OP4 E030B0 0 +OP4 E030B1 0 +OP4 E030B2 0 +OP4 E030B3 0 +OP4 E030B4 0 +OP4 E030B5 0 +OP4 E030B6 0 +OP4 E030B7 0 +OP4 E030B8 0 +OP4 E030B9 0 +OP4 E030BA 0 +OP4 E030BB 0 +OP4 E030BC 0 +OP4 E030BD 0 +OP4 E030BE 0 +OP4 E030BF 0 +OP4 E030C0 0 +OP4 E030C1 0 +OP4 E030C2 0 +OP4 E030C3 0 +OP4 E030C4 0 +OP4 E030C5 0 +OP4 E030C6 0 +OP4 E030C7 0 +OP4 E030C8 0 +OP4 E030C9 0 +OP4 E030CA 0 +OP4 E030CB 0 +OP4 E030CC 0 +OP4 E030CD 0 +OP4 E030CE 0 +OP4 E030CF 0 +OP4 E030D0 0 +OP4 E030D1 0 +OP4 E030D2 0 +OP4 E030D3 0 +OP4 E030D4 0 +OP4 E030D5 0 +OP4 E030D6 0 +OP4 E030D7 0 +OP4 E030D8 0 +OP4 E030D9 0 +OP4 E030DA 0 +OP4 E030DB 0 +OP4 E030DC 0 +OP4 E030DD 0 +OP4 E030DE 0 +OP4 E030DF 0 +OP4 E030E0 0 +OP4 E030E1 0 +OP4 E030E2 0 +OP4 E030E3 0 +OP4 E030E4 0 +OP4 E030E5 0 +OP4 E030E6 0 +OP4 E030E7 0 +OP4 E030E8 0 +OP4 E030E9 0 +OP4 E030EA 0 +OP4 E030EB 0 +OP4 E030EC 0 +OP4 E030ED 0 +OP4 E030EE 0 +OP4 E030EF 0 +OP4 E030F0 0 +OP4 E030F1 0 +OP4 E030F2 0 +OP4 E030F3 0 +OP4 E030F4 0 +OP4 E030F5 0 +OP4 E030F6 0 +OP4 E030F7 0 +OP4 E030F8 0 +OP4 E030F9 0 +OP4 E030FA 0 +OP4 E030FB 0 +OP4 E030FC 0 +OP4 E030FD 0 +OP4 E030FE 0 +OP4 E030FF 0 +OP4 E03100 0 +OP4 E03101 0 +OP4 E03102 0 +OP4 E03103 0 +OP4 E03104 0 +OP4 E03105 0 +OP4 E03106 0 +OP4 E03107 0 +OP4 E03108 0 +OP4 E03109 0 +OP4 E0310A 0 +OP4 E0310B 0 +OP4 E0310C 0 +OP4 E0310D 0 +OP4 E0310E 0 +OP4 E0310F 0 +OP4 E03110 0 +OP4 E03111 0 +OP4 E03112 0 +OP4 E03113 0 +OP4 E03114 0 +OP4 E03115 0 +OP4 E03116 0 +OP4 E03117 0 +OP4 E03118 0 +OP4 E03119 0 +OP4 E0311A 0 +OP4 E0311B 0 +OP4 E0311C 0 +OP4 E0311D 0 +OP4 E0311E 0 +OP4 E0311F 0 +OP4 E03120 0 +OP4 E03121 0 +OP4 E03122 0 +OP4 E03123 0 +OP4 E03124 0 +OP4 E03125 0 +OP4 E03126 0 +OP4 E03127 0 +OP4 E03128 0 +OP4 E03129 0 +OP4 E0312A 0 +OP4 E0312B 0 +OP4 E0312C 0 +OP4 E0312D 0 +OP4 E0312E 0 +OP4 E0312F 0 +OP4 E03130 0 +OP4 E03131 0 +OP4 E03132 0 +OP4 E03133 0 +OP4 E03134 0 +OP4 E03135 0 +OP4 E03136 0 +OP4 E03137 0 +OP4 E03138 0 +OP4 E03139 0 +OP4 E0313A 0 +OP4 E0313B 0 +OP4 E0313C 0 +OP4 E0313D 0 +OP4 E0313E 0 +OP4 E0313F 0 +OP4 E03140 0 +OP4 E03141 0 +OP4 E03142 0 +OP4 E03143 0 +OP4 E03144 0 +OP4 E03145 0 +OP4 E03146 0 +OP4 E03147 0 +OP4 E03148 0 +OP4 E03149 0 +OP4 E0314A 0 +OP4 E0314B 0 +OP4 E0314C 0 +OP4 E0314D 0 +OP4 E0314E 0 +OP4 E0314F 0 +OP4 E03150 0 +OP4 E03151 0 +OP4 E03152 0 +OP4 E03153 0 +OP4 E03154 0 +OP4 E03155 0 +OP4 E03156 0 +OP4 E03157 0 +OP4 E03158 0 +OP4 E03159 0 +OP4 E0315A 0 +OP4 E0315B 0 +OP4 E0315C 0 +OP4 E0315D 0 +OP4 E0315E 0 +OP4 E0315F 0 +OP4 E03160 0 +OP4 E03161 0 +OP4 E03162 0 +OP4 E03163 0 +OP4 E03164 0 +OP4 E03165 0 +OP4 E03166 0 +OP4 E03167 0 +OP4 E03168 0 +OP4 E03169 0 +OP4 E0316A 0 +OP4 E0316B 0 +OP4 E0316C 0 +OP4 E0316D 0 +OP4 E0316E 0 +OP4 E0316F 0 +OP4 E03170 0 +OP4 E03171 0 +OP4 E03172 0 +OP4 E03173 0 +OP4 E03174 0 +OP4 E03175 0 +OP4 E03176 0 +OP4 E03177 0 +OP4 E03178 0 +OP4 E03179 0 +OP4 E0317A 0 +OP4 E0317B 0 +OP4 E0317C 0 +OP4 E0317D 0 +OP4 E0317E 0 +OP4 E0317F 0 +OP4 E03180 0 +OP4 E03181 0 +OP4 E03182 0 +OP4 E03183 0 +OP4 E03184 0 +OP4 E03185 0 +OP4 E03186 0 +OP4 E03187 0 +OP4 E03188 0 +OP4 E03189 0 +OP4 E0318A 0 +OP4 E0318B 0 +OP4 E0318C 0 +OP4 E0318D 0 +OP4 E0318E 0 +OP4 E0318F 0 +OP4 E03190 0 +OP4 E03191 0 +OP4 E03192 0 +OP4 E03193 0 +OP4 E03194 0 +OP4 E03195 0 +OP4 E03196 0 +OP4 E03197 0 +OP4 E03198 0 +OP4 E03199 0 +OP4 E0319A 0 +OP4 E0319B 0 +OP4 E0319C 0 +OP4 E0319D 0 +OP4 E0319E 0 +OP4 E0319F 0 +OP4 E031A0 0 +OP4 E031A1 0 +OP4 E031A2 0 +OP4 E031A3 0 +OP4 E031A4 0 +OP4 E031A5 0 +OP4 E031A6 0 +OP4 E031A7 0 +OP4 E031A8 0 +OP4 E031A9 0 +OP4 E031AA 0 +OP4 E031AB 0 +OP4 E031AC 0 +OP4 E031AD 0 +OP4 E031AE 0 +OP4 E031AF 0 +OP4 E031B0 0 +OP4 E031B1 0 +OP4 E031B2 0 +OP4 E031B3 0 +OP4 E031B4 0 +OP4 E031B5 0 +OP4 E031B6 0 +OP4 E031B7 0 +OP4 E031B8 0 +OP4 E031B9 0 +OP4 E031BA 0 +OP4 E031BB 0 +OP4 E031BC 0 +OP4 E031BD 0 +OP4 E031BE 0 +OP4 E031BF 0 +OP4 E031C0 0 +OP4 E031C1 0 +OP4 E031C2 0 +OP4 E031C3 0 +OP4 E031C4 0 +OP4 E031C5 0 +OP4 E031C6 0 +OP4 E031C7 0 +OP4 E031C8 0 +OP4 E031C9 0 +OP4 E031CA 0 +OP4 E031CB 0 +OP4 E031CC 0 +OP4 E031CD 0 +OP4 E031CE 0 +OP4 E031CF 0 +OP4 E031D0 0 +OP4 E031D1 0 +OP4 E031D2 0 +OP4 E031D3 0 +OP4 E031D4 0 +OP4 E031D5 0 +OP4 E031D6 0 +OP4 E031D7 0 +OP4 E031D8 0 +OP4 E031D9 0 +OP4 E031DA 0 +OP4 E031DB 0 +OP4 E031DC 0 +OP4 E031DD 0 +OP4 E031DE 0 +OP4 E031DF 0 +OP4 E031E0 0 +OP4 E031E1 0 +OP4 E031E2 0 +OP4 E031E3 0 +OP4 E031E4 0 +OP4 E031E5 0 +OP4 E031E6 0 +OP4 E031E7 0 +OP4 E031E8 0 +OP4 E031E9 0 +OP4 E031EA 0 +OP4 E031EB 0 +OP4 E031EC 0 +OP4 E031ED 0 +OP4 E031EE 0 +OP4 E031EF 0 +OP4 E031F0 0 +OP4 E031F1 0 +OP4 E031F2 0 +OP4 E031F3 0 +OP4 E031F4 0 +OP4 E031F5 0 +OP4 E031F6 0 +OP4 E031F7 0 +OP4 E031F8 0 +OP4 E031F9 0 +OP4 E031FA 0 +OP4 E031FB 0 +OP4 E031FC 0 +OP4 E031FD 0 +OP4 E031FE 0 +OP4 E031FF 0 +OP4 E03200 0 +OP4 E03201 0 +OP4 E03202 0 +OP4 E03203 0 +OP4 E03204 0 +OP4 E03205 0 +OP4 E03206 0 +OP4 E03207 0 +OP4 E03208 0 +OP4 E03209 0 +OP4 E0320A 0 +OP4 E0320B 0 +OP4 E0320C 0 +OP4 E0320D 0 +OP4 E0320E 0 +OP4 E0320F 0 +OP4 E03210 0 +OP4 E03211 0 +OP4 E03212 0 +OP4 E03213 0 +OP4 E03214 0 +OP4 E03215 0 +OP4 E03216 0 +OP4 E03217 0 +OP4 E03218 0 +OP4 E03219 0 +OP4 E0321A 0 +OP4 E0321B 0 +OP4 E0321C 0 +OP4 E0321D 0 +OP4 E0321E 0 +OP4 E0321F 0 +OP4 E03220 0 +OP4 E03221 0 +OP4 E03222 0 +OP4 E03223 0 +OP4 E03224 0 +OP4 E03225 0 +OP4 E03226 0 +OP4 E03227 0 +OP4 E03228 0 +OP4 E03229 0 +OP4 E0322A 0 +OP4 E0322B 0 +OP4 E0322C 0 +OP4 E0322D 0 +OP4 E0322E 0 +OP4 E0322F 0 +OP4 E03230 0 +OP4 E03231 0 +OP4 E03232 0 +OP4 E03233 0 +OP4 E03234 0 +OP4 E03235 0 +OP4 E03236 0 +OP4 E03237 0 +OP4 E03238 0 +OP4 E03239 0 +OP4 E0323A 0 +OP4 E0323B 0 +OP4 E0323C 0 +OP4 E0323D 0 +OP4 E0323E 0 +OP4 E0323F 0 +OP4 E03240 0 +OP4 E03241 0 +OP4 E03242 0 +OP4 E03243 0 +OP4 E03244 0 +OP4 E03245 0 +OP4 E03246 0 +OP4 E03247 0 +OP4 E03248 0 +OP4 E03249 0 +OP4 E0324A 0 +OP4 E0324B 0 +OP4 E0324C 0 +OP4 E0324D 0 +OP4 E0324E 0 +OP4 E0324F 0 +OP4 E03250 0 +OP4 E03251 0 +OP4 E03252 0 +OP4 E03253 0 +OP4 E03254 0 +OP4 E03255 0 +OP4 E03256 0 +OP4 E03257 0 +OP4 E03258 0 +OP4 E03259 0 +OP4 E0325A 0 +OP4 E0325B 0 +OP4 E0325C 0 +OP4 E0325D 0 +OP4 E0325E 0 +OP4 E0325F 0 +OP4 E03260 0 +OP4 E03261 0 +OP4 E03262 0 +OP4 E03263 0 +OP4 E03264 0 +OP4 E03265 0 +OP4 E03266 0 +OP4 E03267 0 +OP4 E03268 0 +OP4 E03269 0 +OP4 E0326A 0 +OP4 E0326B 0 +OP4 E0326C 0 +OP4 E0326D 0 +OP4 E0326E 0 +OP4 E0326F 0 +OP4 E03270 0 +OP4 E03271 0 +OP4 E03272 0 +OP4 E03273 0 +OP4 E03274 0 +OP4 E03275 0 +OP4 E03276 0 +OP4 E03277 0 +OP4 E03278 0 +OP4 E03279 0 +OP4 E0327A 0 +OP4 E0327B 0 +OP4 E0327C 0 +OP4 E0327D 0 +OP4 E0327E 0 +OP4 E0327F 0 +OP4 E03280 0 +OP4 E03281 0 +OP4 E03282 0 +OP4 E03283 0 +OP4 E03284 0 +OP4 E03285 0 +OP4 E03286 0 +OP4 E03287 0 +OP4 E03288 0 +OP4 E03289 0 +OP4 E0328A 0 +OP4 E0328B 0 +OP4 E0328C 0 +OP4 E0328D 0 +OP4 E0328E 0 +OP4 E0328F 0 +OP4 E03290 0 +OP4 E03291 0 +OP4 E03292 0 +OP4 E03293 0 +OP4 E03294 0 +OP4 E03295 0 +OP4 E03296 0 +OP4 E03297 0 +OP4 E03298 0 +OP4 E03299 0 +OP4 E0329A 0 +OP4 E0329B 0 +OP4 E0329C 0 +OP4 E0329D 0 +OP4 E0329E 0 +OP4 E0329F 0 +OP4 E032A0 0 +OP4 E032A1 0 +OP4 E032A2 0 +OP4 E032A3 0 +OP4 E032A4 0 +OP4 E032A5 0 +OP4 E032A6 0 +OP4 E032A7 0 +OP4 E032A8 0 +OP4 E032A9 0 +OP4 E032AA 0 +OP4 E032AB 0 +OP4 E032AC 0 +OP4 E032AD 0 +OP4 E032AE 0 +OP4 E032AF 0 +OP4 E032B0 0 +OP4 E032B1 0 +OP4 E032B2 0 +OP4 E032B3 0 +OP4 E032B4 0 +OP4 E032B5 0 +OP4 E032B6 0 +OP4 E032B7 0 +OP4 E032B8 0 +OP4 E032B9 0 +OP4 E032BA 0 +OP4 E032BB 0 +OP4 E032BC 0 +OP4 E032BD 0 +OP4 E032BE 0 +OP4 E032BF 0 +OP4 E032C0 0 +OP4 E032C1 0 +OP4 E032C2 0 +OP4 E032C3 0 +OP4 E032C4 0 +OP4 E032C5 0 +OP4 E032C6 0 +OP4 E032C7 0 +OP4 E032C8 0 +OP4 E032C9 0 +OP4 E032CA 0 +OP4 E032CB 0 +OP4 E032CC 0 +OP4 E032CD 0 +OP4 E032CE 0 +OP4 E032CF 0 +OP4 E032D0 0 +OP4 E032D1 0 +OP4 E032D2 0 +OP4 E032D3 0 +OP4 E032D4 0 +OP4 E032D5 0 +OP4 E032D6 0 +OP4 E032D7 0 +OP4 E032D8 0 +OP4 E032D9 0 +OP4 E032DA 0 +OP4 E032DB 0 +OP4 E032DC 0 +OP4 E032DD 0 +OP4 E032DE 0 +OP4 E032DF 0 +OP4 E032E0 0 +OP4 E032E1 0 +OP4 E032E2 0 +OP4 E032E3 0 +OP4 E032E4 0 +OP4 E032E5 0 +OP4 E032E6 0 +OP4 E032E7 0 +OP4 E032E8 0 +OP4 E032E9 0 +OP4 E032EA 0 +OP4 E032EB 0 +OP4 E032EC 0 +OP4 E032ED 0 +OP4 E032EE 0 +OP4 E032EF 0 +OP4 E032F0 0 +OP4 E032F1 0 +OP4 E032F2 0 +OP4 E032F3 0 +OP4 E032F4 0 +OP4 E032F5 0 +OP4 E032F6 0 +OP4 E032F7 0 +OP4 E032F8 0 +OP4 E032F9 0 +OP4 E032FA 0 +OP4 E032FB 0 +OP4 E032FC 0 +OP4 E032FD 0 +OP4 E032FE 0 +OP4 E032FF 0 +OP4 E03300 0 +OP4 E03301 0 +OP4 E03302 0 +OP4 E03303 0 +OP4 E03304 0 +OP4 E03305 0 +OP4 E03306 0 +OP4 E03307 0 +OP4 E03308 0 +OP4 E03309 0 +OP4 E0330A 0 +OP4 E0330B 0 +OP4 E0330C 0 +OP4 E0330D 0 +OP4 E0330E 0 +OP4 E0330F 0 +OP4 E03310 0 +OP4 E03311 0 +OP4 E03312 0 +OP4 E03313 0 +OP4 E03314 0 +OP4 E03315 0 +OP4 E03316 0 +OP4 E03317 0 +OP4 E03318 0 +OP4 E03319 0 +OP4 E0331A 0 +OP4 E0331B 0 +OP4 E0331C 0 +OP4 E0331D 0 +OP4 E0331E 0 +OP4 E0331F 0 +OP4 E03320 0 +OP4 E03321 0 +OP4 E03322 0 +OP4 E03323 0 +OP4 E03324 0 +OP4 E03325 0 +OP4 E03326 0 +OP4 E03327 0 +OP4 E03328 0 +OP4 E03329 0 +OP4 E0332A 0 +OP4 E0332B 0 +OP4 E0332C 0 +OP4 E0332D 0 +OP4 E0332E 0 +OP4 E0332F 0 +OP4 E03330 0 +OP4 E03331 0 +OP4 E03332 0 +OP4 E03333 0 +OP4 E03334 0 +OP4 E03335 0 +OP4 E03336 0 +OP4 E03337 0 +OP4 E03338 0 +OP4 E03339 0 +OP4 E0333A 0 +OP4 E0333B 0 +OP4 E0333C 0 +OP4 E0333D 0 +OP4 E0333E 0 +OP4 E0333F 0 +OP4 E03340 0 +OP4 E03341 0 +OP4 E03342 0 +OP4 E03343 0 +OP4 E03344 0 +OP4 E03345 0 +OP4 E03346 0 +OP4 E03347 0 +OP4 E03348 0 +OP4 E03349 0 +OP4 E0334A 0 +OP4 E0334B 0 +OP4 E0334C 0 +OP4 E0334D 0 +OP4 E0334E 0 +OP4 E0334F 0 +OP4 E03350 0 +OP4 E03351 0 +OP4 E03352 0 +OP4 E03353 0 +OP4 E03354 0 +OP4 E03355 0 +OP4 E03356 0 +OP4 E03357 0 +OP4 E03358 0 +OP4 E03359 0 +OP4 E0335A 0 +OP4 E0335B 0 +OP4 E0335C 0 +OP4 E0335D 0 +OP4 E0335E 0 +OP4 E0335F 0 +OP4 E03360 0 +OP4 E03361 0 +OP4 E03362 0 +OP4 E03363 0 +OP4 E03364 0 +OP4 E03365 0 +OP4 E03366 0 +OP4 E03367 0 +OP4 E03368 0 +OP4 E03369 0 +OP4 E0336A 0 +OP4 E0336B 0 +OP4 E0336C 0 +OP4 E0336D 0 +OP4 E0336E 0 +OP4 E0336F 0 +OP4 E03370 0 +OP4 E03371 0 +OP4 E03372 0 +OP4 E03373 0 +OP4 E03374 0 +OP4 E03375 0 +OP4 E03376 0 +OP4 E03377 0 +OP4 E03378 0 +OP4 E03379 0 +OP4 E0337A 0 +OP4 E0337B 0 +OP4 E0337C 0 +OP4 E0337D 0 +OP4 E0337E 0 +OP4 E0337F 0 +OP4 E03380 0 +OP4 E03381 0 +OP4 E03382 0 +OP4 E03383 0 +OP4 E03384 0 +OP4 E03385 0 +OP4 E03386 0 +OP4 E03387 0 +OP4 E03388 0 +OP4 E03389 0 +OP4 E0338A 0 +OP4 E0338B 0 +OP4 E0338C 0 +OP4 E0338D 0 +OP4 E0338E 0 +OP4 E0338F 0 +OP4 E03390 0 +OP4 E03391 0 +OP4 E03392 0 +OP4 E03393 0 +OP4 E03394 0 +OP4 E03395 0 +OP4 E03396 0 +OP4 E03397 0 +OP4 E03398 0 +OP4 E03399 0 +OP4 E0339A 0 +OP4 E0339B 0 +OP4 E0339C 0 +OP4 E0339D 0 +OP4 E0339E 0 +OP4 E0339F 0 +OP4 E033A0 0 +OP4 E033A1 0 +OP4 E033A2 0 +OP4 E033A3 0 +OP4 E033A4 0 +OP4 E033A5 0 +OP4 E033A6 0 +OP4 E033A7 0 +OP4 E033A8 0 +OP4 E033A9 0 +OP4 E033AA 0 +OP4 E033AB 0 +OP4 E033AC 0 +OP4 E033AD 0 +OP4 E033AE 0 +OP4 E033AF 0 +OP4 E033B0 0 +OP4 E033B1 0 +OP4 E033B2 0 +OP4 E033B3 0 +OP4 E033B4 0 +OP4 E033B5 0 +OP4 E033B6 0 +OP4 E033B7 0 +OP4 E033B8 0 +OP4 E033B9 0 +OP4 E033BA 0 +OP4 E033BB 0 +OP4 E033BC 0 +OP4 E033BD 0 +OP4 E033BE 0 +OP4 E033BF 0 +OP4 E033C0 0 +OP4 E033C1 0 +OP4 E033C2 0 +OP4 E033C3 0 +OP4 E033C4 0 +OP4 E033C5 0 +OP4 E033C6 0 +OP4 E033C7 0 +OP4 E033C8 0 +OP4 E033C9 0 +OP4 E033CA 0 +OP4 E033CB 0 +OP4 E033CC 0 +OP4 E033CD 0 +OP4 E033CE 0 +OP4 E033CF 0 +OP4 E033D0 0 +OP4 E033D1 0 +OP4 E033D2 0 +OP4 E033D3 0 +OP4 E033D4 0 +OP4 E033D5 0 +OP4 E033D6 0 +OP4 E033D7 0 +OP4 E033D8 0 +OP4 E033D9 0 +OP4 E033DA 0 +OP4 E033DB 0 +OP4 E033DC 0 +OP4 E033DD 0 +OP4 E033DE 0 +OP4 E033DF 0 +OP4 E033E0 0 +OP4 E033E1 0 +OP4 E033E2 0 +OP4 E033E3 0 +OP4 E033E4 0 +OP4 E033E5 0 +OP4 E033E6 0 +OP4 E033E7 0 +OP4 E033E8 0 +OP4 E033E9 0 +OP4 E033EA 0 +OP4 E033EB 0 +OP4 E033EC 0 +OP4 E033ED 0 +OP4 E033EE 0 +OP4 E033EF 0 +OP4 E033F0 0 +OP4 E033F1 0 +OP4 E033F2 0 +OP4 E033F3 0 +OP4 E033F4 0 +OP4 E033F5 0 +OP4 E033F6 0 +OP4 E033F7 0 +OP4 E033F8 0 +OP4 E033F9 0 +OP4 E033FA 0 +OP4 E033FB 0 +OP4 E033FC 0 +OP4 E033FD 0 +OP4 E033FE 0 +OP4 E033FF 0 +OP4 E03400 0 +OP4 E03401 0 +OP4 E03402 0 +OP4 E03403 0 +OP4 E03404 0 +OP4 E03405 0 +OP4 E03406 0 +OP4 E03407 0 +OP4 E03408 0 +OP4 E03409 0 +OP4 E0340A 0 +OP4 E0340B 0 +OP4 E0340C 0 +OP4 E0340D 0 +OP4 E0340E 0 +OP4 E0340F 0 +OP4 E03410 0 +OP4 E03411 0 +OP4 E03412 0 +OP4 E03413 0 +OP4 E03414 0 +OP4 E03415 0 +OP4 E03416 0 +OP4 E03417 0 +OP4 E03418 0 +OP4 E03419 0 +OP4 E0341A 0 +OP4 E0341B 0 +OP4 E0341C 0 +OP4 E0341D 0 +OP4 E0341E 0 +OP4 E0341F 0 +OP4 E03420 0 +OP4 E03421 0 +OP4 E03422 0 +OP4 E03423 0 +OP4 E03424 0 +OP4 E03425 0 +OP4 E03426 0 +OP4 E03427 0 +OP4 E03428 0 +OP4 E03429 0 +OP4 E0342A 0 +OP4 E0342B 0 +OP4 E0342C 0 +OP4 E0342D 0 +OP4 E0342E 0 +OP4 E0342F 0 +OP4 E03430 0 +OP4 E03431 0 +OP4 E03432 0 +OP4 E03433 0 +OP4 E03434 0 +OP4 E03435 0 +OP4 E03436 0 +OP4 E03437 0 +OP4 E03438 0 +OP4 E03439 0 +OP4 E0343A 0 +OP4 E0343B 0 +OP4 E0343C 0 +OP4 E0343D 0 +OP4 E0343E 0 +OP4 E0343F 0 +OP4 E03440 0 +OP4 E03441 0 +OP4 E03442 0 +OP4 E03443 0 +OP4 E03444 0 +OP4 E03445 0 +OP4 E03446 0 +OP4 E03447 0 +OP4 E03448 0 +OP4 E03449 0 +OP4 E0344A 0 +OP4 E0344B 0 +OP4 E0344C 0 +OP4 E0344D 0 +OP4 E0344E 0 +OP4 E0344F 0 +OP4 E03450 0 +OP4 E03451 0 +OP4 E03452 0 +OP4 E03453 0 +OP4 E03454 0 +OP4 E03455 0 +OP4 E03456 0 +OP4 E03457 0 +OP4 E03458 0 +OP4 E03459 0 +OP4 E0345A 0 +OP4 E0345B 0 +OP4 E0345C 0 +OP4 E0345D 0 +OP4 E0345E 0 +OP4 E0345F 0 +OP4 E03460 0 +OP4 E03461 0 +OP4 E03462 0 +OP4 E03463 0 +OP4 E03464 0 +OP4 E03465 0 +OP4 E03466 0 +OP4 E03467 0 +OP4 E03468 0 +OP4 E03469 0 +OP4 E0346A 0 +OP4 E0346B 0 +OP4 E0346C 0 +OP4 E0346D 0 +OP4 E0346E 0 +OP4 E0346F 0 +OP4 E03470 0 +OP4 E03471 0 +OP4 E03472 0 +OP4 E03473 0 +OP4 E03474 0 +OP4 E03475 0 +OP4 E03476 0 +OP4 E03477 0 +OP4 E03478 0 +OP4 E03479 0 +OP4 E0347A 0 +OP4 E0347B 0 +OP4 E0347C 0 +OP4 E0347D 0 +OP4 E0347E 0 +OP4 E0347F 0 +OP4 E03480 0 +OP4 E03481 0 +OP4 E03482 0 +OP4 E03483 0 +OP4 E03484 0 +OP4 E03485 0 +OP4 E03486 0 +OP4 E03487 0 +OP4 E03488 0 +OP4 E03489 0 +OP4 E0348A 0 +OP4 E0348B 0 +OP4 E0348C 0 +OP4 E0348D 0 +OP4 E0348E 0 +OP4 E0348F 0 +OP4 E03490 0 +OP4 E03491 0 +OP4 E03492 0 +OP4 E03493 0 +OP4 E03494 0 +OP4 E03495 0 +OP4 E03496 0 +OP4 E03497 0 +OP4 E03498 0 +OP4 E03499 0 +OP4 E0349A 0 +OP4 E0349B 0 +OP4 E0349C 0 +OP4 E0349D 0 +OP4 E0349E 0 +OP4 E0349F 0 +OP4 E034A0 0 +OP4 E034A1 0 +OP4 E034A2 0 +OP4 E034A3 0 +OP4 E034A4 0 +OP4 E034A5 0 +OP4 E034A6 0 +OP4 E034A7 0 +OP4 E034A8 0 +OP4 E034A9 0 +OP4 E034AA 0 +OP4 E034AB 0 +OP4 E034AC 0 +OP4 E034AD 0 +OP4 E034AE 0 +OP4 E034AF 0 +OP4 E034B0 0 +OP4 E034B1 0 +OP4 E034B2 0 +OP4 E034B3 0 +OP4 E034B4 0 +OP4 E034B5 0 +OP4 E034B6 0 +OP4 E034B7 0 +OP4 E034B8 0 +OP4 E034B9 0 +OP4 E034BA 0 +OP4 E034BB 0 +OP4 E034BC 0 +OP4 E034BD 0 +OP4 E034BE 0 +OP4 E034BF 0 +OP4 E034C0 0 +OP4 E034C1 0 +OP4 E034C2 0 +OP4 E034C3 0 +OP4 E034C4 0 +OP4 E034C5 0 +OP4 E034C6 0 +OP4 E034C7 0 +OP4 E034C8 0 +OP4 E034C9 0 +OP4 E034CA 0 +OP4 E034CB 0 +OP4 E034CC 0 +OP4 E034CD 0 +OP4 E034CE 0 +OP4 E034CF 0 +OP4 E034D0 0 +OP4 E034D1 0 +OP4 E034D2 0 +OP4 E034D3 0 +OP4 E034D4 0 +OP4 E034D5 0 +OP4 E034D6 0 +OP4 E034D7 0 +OP4 E034D8 0 +OP4 E034D9 0 +OP4 E034DA 0 +OP4 E034DB 0 +OP4 E034DC 0 +OP4 E034DD 0 +OP4 E034DE 0 +OP4 E034DF 0 +OP4 E034E0 0 +OP4 E034E1 0 +OP4 E034E2 0 +OP4 E034E3 0 +OP4 E034E4 0 +OP4 E034E5 0 +OP4 E034E6 0 +OP4 E034E7 0 +OP4 E034E8 0 +OP4 E034E9 0 +OP4 E034EA 0 +OP4 E034EB 0 +OP4 E034EC 0 +OP4 E034ED 0 +OP4 E034EE 0 +OP4 E034EF 0 +OP4 E034F0 0 +OP4 E034F1 0 +OP4 E034F2 0 +OP4 E034F3 0 +OP4 E034F4 0 +OP4 E034F5 0 +OP4 E034F6 0 +OP4 E034F7 0 +OP4 E034F8 0 +OP4 E034F9 0 +OP4 E034FA 0 +OP4 E034FB 0 +OP4 E034FC 0 +OP4 E034FD 0 +OP4 E034FE 0 +OP4 E034FF 0 +OP4 E03500 0 +OP4 E03501 0 +OP4 E03502 0 +OP4 E03503 0 +OP4 E03504 0 +OP4 E03505 0 +OP4 E03506 0 +OP4 E03507 0 +OP4 E03508 0 +OP4 E03509 0 +OP4 E0350A 0 +OP4 E0350B 0 +OP4 E0350C 0 +OP4 E0350D 0 +OP4 E0350E 0 +OP4 E0350F 0 +OP4 E03510 0 +OP4 E03511 0 +OP4 E03512 0 +OP4 E03513 0 +OP4 E03514 0 +OP4 E03515 0 +OP4 E03516 0 +OP4 E03517 0 +OP4 E03518 0 +OP4 E03519 0 +OP4 E0351A 0 +OP4 E0351B 0 +OP4 E0351C 0 +OP4 E0351D 0 +OP4 E0351E 0 +OP4 E0351F 0 +OP4 E03520 0 +OP4 E03521 0 +OP4 E03522 0 +OP4 E03523 0 +OP4 E03524 0 +OP4 E03525 0 +OP4 E03526 0 +OP4 E03527 0 +OP4 E03528 0 +OP4 E03529 0 +OP4 E0352A 0 +OP4 E0352B 0 +OP4 E0352C 0 +OP4 E0352D 0 +OP4 E0352E 0 +OP4 E0352F 0 +OP4 E03530 0 +OP4 E03531 0 +OP4 E03532 0 +OP4 E03533 0 +OP4 E03534 0 +OP4 E03535 0 +OP4 E03536 0 +OP4 E03537 0 +OP4 E03538 0 +OP4 E03539 0 +OP4 E0353A 0 +OP4 E0353B 0 +OP4 E0353C 0 +OP4 E0353D 0 +OP4 E0353E 0 +OP4 E0353F 0 +OP4 E03540 0 +OP4 E03541 0 +OP4 E03542 0 +OP4 E03543 0 +OP4 E03544 0 +OP4 E03545 0 +OP4 E03546 0 +OP4 E03547 0 +OP4 E03548 0 +OP4 E03549 0 +OP4 E0354A 0 +OP4 E0354B 0 +OP4 E0354C 0 +OP4 E0354D 0 +OP4 E0354E 0 +OP4 E0354F 0 +OP4 E03550 0 +OP4 E03551 0 +OP4 E03552 0 +OP4 E03553 0 +OP4 E03554 0 +OP4 E03555 0 +OP4 E03556 0 +OP4 E03557 0 +OP4 E03558 0 +OP4 E03559 0 +OP4 E0355A 0 +OP4 E0355B 0 +OP4 E0355C 0 +OP4 E0355D 0 +OP4 E0355E 0 +OP4 E0355F 0 +OP4 E03560 0 +OP4 E03561 0 +OP4 E03562 0 +OP4 E03563 0 +OP4 E03564 0 +OP4 E03565 0 +OP4 E03566 0 +OP4 E03567 0 +OP4 E03568 0 +OP4 E03569 0 +OP4 E0356A 0 +OP4 E0356B 0 +OP4 E0356C 0 +OP4 E0356D 0 +OP4 E0356E 0 +OP4 E0356F 0 +OP4 E03570 0 +OP4 E03571 0 +OP4 E03572 0 +OP4 E03573 0 +OP4 E03574 0 +OP4 E03575 0 +OP4 E03576 0 +OP4 E03577 0 +OP4 E03578 0 +OP4 E03579 0 +OP4 E0357A 0 +OP4 E0357B 0 +OP4 E0357C 0 +OP4 E0357D 0 +OP4 E0357E 0 +OP4 E0357F 0 +OP4 E03580 0 +OP4 E03581 0 +OP4 E03582 0 +OP4 E03583 0 +OP4 E03584 0 +OP4 E03585 0 +OP4 E03586 0 +OP4 E03587 0 +OP4 E03588 0 +OP4 E03589 0 +OP4 E0358A 0 +OP4 E0358B 0 +OP4 E0358C 0 +OP4 E0358D 0 +OP4 E0358E 0 +OP4 E0358F 0 +OP4 E03590 0 +OP4 E03591 0 +OP4 E03592 0 +OP4 E03593 0 +OP4 E03594 0 +OP4 E03595 0 +OP4 E03596 0 +OP4 E03597 0 +OP4 E03598 0 +OP4 E03599 0 +OP4 E0359A 0 +OP4 E0359B 0 +OP4 E0359C 0 +OP4 E0359D 0 +OP4 E0359E 0 +OP4 E0359F 0 +OP4 E035A0 0 +OP4 E035A1 0 +OP4 E035A2 0 +OP4 E035A3 0 +OP4 E035A4 0 +OP4 E035A5 0 +OP4 E035A6 0 +OP4 E035A7 0 +OP4 E035A8 0 +OP4 E035A9 0 +OP4 E035AA 0 +OP4 E035AB 0 +OP4 E035AC 0 +OP4 E035AD 0 +OP4 E035AE 0 +OP4 E035AF 0 +OP4 E035B0 0 +OP4 E035B1 0 +OP4 E035B2 0 +OP4 E035B3 0 +OP4 E035B4 0 +OP4 E035B5 0 +OP4 E035B6 0 +OP4 E035B7 0 +OP4 E035B8 0 +OP4 E035B9 0 +OP4 E035BA 0 +OP4 E035BB 0 +OP4 E035BC 0 +OP4 E035BD 0 +OP4 E035BE 0 +OP4 E035BF 0 +OP4 E035C0 0 +OP4 E035C1 0 +OP4 E035C2 0 +OP4 E035C3 0 +OP4 E035C4 0 +OP4 E035C5 0 +OP4 E035C6 0 +OP4 E035C7 0 +OP4 E035C8 0 +OP4 E035C9 0 +OP4 E035CA 0 +OP4 E035CB 0 +OP4 E035CC 0 +OP4 E035CD 0 +OP4 E035CE 0 +OP4 E035CF 0 +OP4 E035D0 0 +OP4 E035D1 0 +OP4 E035D2 0 +OP4 E035D3 0 +OP4 E035D4 0 +OP4 E035D5 0 +OP4 E035D6 0 +OP4 E035D7 0 +OP4 E035D8 0 +OP4 E035D9 0 +OP4 E035DA 0 +OP4 E035DB 0 +OP4 E035DC 0 +OP4 E035DD 0 +OP4 E035DE 0 +OP4 E035DF 0 +OP4 E035E0 0 +OP4 E035E1 0 +OP4 E035E2 0 +OP4 E035E3 0 +OP4 E035E4 0 +OP4 E035E5 0 +OP4 E035E6 0 +OP4 E035E7 0 +OP4 E035E8 0 +OP4 E035E9 0 +OP4 E035EA 0 +OP4 E035EB 0 +OP4 E035EC 0 +OP4 E035ED 0 +OP4 E035EE 0 +OP4 E035EF 0 +OP4 E035F0 0 +OP4 E035F1 0 +OP4 E035F2 0 +OP4 E035F3 0 +OP4 E035F4 0 +OP4 E035F5 0 +OP4 E035F6 0 +OP4 E035F7 0 +OP4 E035F8 0 +OP4 E035F9 0 +OP4 E035FA 0 +OP4 E035FB 0 +OP4 E035FC 0 +OP4 E035FD 0 +OP4 E035FE 0 +OP4 E035FF 0 +OP4 E03600 0 +OP4 E03601 0 +OP4 E03602 0 +OP4 E03603 0 +OP4 E03604 0 +OP4 E03605 0 +OP4 E03606 0 +OP4 E03607 0 +OP4 E03608 0 +OP4 E03609 0 +OP4 E0360A 0 +OP4 E0360B 0 +OP4 E0360C 0 +OP4 E0360D 0 +OP4 E0360E 0 +OP4 E0360F 0 +OP4 E03610 0 +OP4 E03611 0 +OP4 E03612 0 +OP4 E03613 0 +OP4 E03614 0 +OP4 E03615 0 +OP4 E03616 0 +OP4 E03617 0 +OP4 E03618 0 +OP4 E03619 0 +OP4 E0361A 0 +OP4 E0361B 0 +OP4 E0361C 0 +OP4 E0361D 0 +OP4 E0361E 0 +OP4 E0361F 0 +OP4 E03620 0 +OP4 E03621 0 +OP4 E03622 0 +OP4 E03623 0 +OP4 E03624 0 +OP4 E03625 0 +OP4 E03626 0 +OP4 E03627 0 +OP4 E03628 0 +OP4 E03629 0 +OP4 E0362A 0 +OP4 E0362B 0 +OP4 E0362C 0 +OP4 E0362D 0 +OP4 E0362E 0 +OP4 E0362F 0 +OP4 E03630 0 +OP4 E03631 0 +OP4 E03632 0 +OP4 E03633 0 +OP4 E03634 0 +OP4 E03635 0 +OP4 E03636 0 +OP4 E03637 0 +OP4 E03638 0 +OP4 E03639 0 +OP4 E0363A 0 +OP4 E0363B 0 +OP4 E0363C 0 +OP4 E0363D 0 +OP4 E0363E 0 +OP4 E0363F 0 +OP4 E03640 0 +OP4 E03641 0 +OP4 E03642 0 +OP4 E03643 0 +OP4 E03644 0 +OP4 E03645 0 +OP4 E03646 0 +OP4 E03647 0 +OP4 E03648 0 +OP4 E03649 0 +OP4 E0364A 0 +OP4 E0364B 0 +OP4 E0364C 0 +OP4 E0364D 0 +OP4 E0364E 0 +OP4 E0364F 0 +OP4 E03650 0 +OP4 E03651 0 +OP4 E03652 0 +OP4 E03653 0 +OP4 E03654 0 +OP4 E03655 0 +OP4 E03656 0 +OP4 E03657 0 +OP4 E03658 0 +OP4 E03659 0 +OP4 E0365A 0 +OP4 E0365B 0 +OP4 E0365C 0 +OP4 E0365D 0 +OP4 E0365E 0 +OP4 E0365F 0 +OP4 E03660 0 +OP4 E03661 0 +OP4 E03662 0 +OP4 E03663 0 +OP4 E03664 0 +OP4 E03665 0 +OP4 E03666 0 +OP4 E03667 0 +OP4 E03668 0 +OP4 E03669 0 +OP4 E0366A 0 +OP4 E0366B 0 +OP4 E0366C 0 +OP4 E0366D 0 +OP4 E0366E 0 +OP4 E0366F 0 +OP4 E03670 0 +OP4 E03671 0 +OP4 E03672 0 +OP4 E03673 0 +OP4 E03674 0 +OP4 E03675 0 +OP4 E03676 0 +OP4 E03677 0 +OP4 E03678 0 +OP4 E03679 0 +OP4 E0367A 0 +OP4 E0367B 0 +OP4 E0367C 0 +OP4 E0367D 0 +OP4 E0367E 0 +OP4 E0367F 0 +OP4 E03680 0 +OP4 E03681 0 +OP4 E03682 0 +OP4 E03683 0 +OP4 E03684 0 +OP4 E03685 0 +OP4 E03686 0 +OP4 E03687 0 +OP4 E03688 0 +OP4 E03689 0 +OP4 E0368A 0 +OP4 E0368B 0 +OP4 E0368C 0 +OP4 E0368D 0 +OP4 E0368E 0 +OP4 E0368F 0 +OP4 E03690 0 +OP4 E03691 0 +OP4 E03692 0 +OP4 E03693 0 +OP4 E03694 0 +OP4 E03695 0 +OP4 E03696 0 +OP4 E03697 0 +OP4 E03698 0 +OP4 E03699 0 +OP4 E0369A 0 +OP4 E0369B 0 +OP4 E0369C 0 +OP4 E0369D 0 +OP4 E0369E 0 +OP4 E0369F 0 +OP4 E036A0 0 +OP4 E036A1 0 +OP4 E036A2 0 +OP4 E036A3 0 +OP4 E036A4 0 +OP4 E036A5 0 +OP4 E036A6 0 +OP4 E036A7 0 +OP4 E036A8 0 +OP4 E036A9 0 +OP4 E036AA 0 +OP4 E036AB 0 +OP4 E036AC 0 +OP4 E036AD 0 +OP4 E036AE 0 +OP4 E036AF 0 +OP4 E036B0 0 +OP4 E036B1 0 +OP4 E036B2 0 +OP4 E036B3 0 +OP4 E036B4 0 +OP4 E036B5 0 +OP4 E036B6 0 +OP4 E036B7 0 +OP4 E036B8 0 +OP4 E036B9 0 +OP4 E036BA 0 +OP4 E036BB 0 +OP4 E036BC 0 +OP4 E036BD 0 +OP4 E036BE 0 +OP4 E036BF 0 +OP4 E036C0 0 +OP4 E036C1 0 +OP4 E036C2 0 +OP4 E036C3 0 +OP4 E036C4 0 +OP4 E036C5 0 +OP4 E036C6 0 +OP4 E036C7 0 +OP4 E036C8 0 +OP4 E036C9 0 +OP4 E036CA 0 +OP4 E036CB 0 +OP4 E036CC 0 +OP4 E036CD 0 +OP4 E036CE 0 +OP4 E036CF 0 +OP4 E036D0 0 +OP4 E036D1 0 +OP4 E036D2 0 +OP4 E036D3 0 +OP4 E036D4 0 +OP4 E036D5 0 +OP4 E036D6 0 +OP4 E036D7 0 +OP4 E036D8 0 +OP4 E036D9 0 +OP4 E036DA 0 +OP4 E036DB 0 +OP4 E036DC 0 +OP4 E036DD 0 +OP4 E036DE 0 +OP4 E036DF 0 +OP4 E036E0 0 +OP4 E036E1 0 +OP4 E036E2 0 +OP4 E036E3 0 +OP4 E036E4 0 +OP4 E036E5 0 +OP4 E036E6 0 +OP4 E036E7 0 +OP4 E036E8 0 +OP4 E036E9 0 +OP4 E036EA 0 +OP4 E036EB 0 +OP4 E036EC 0 +OP4 E036ED 0 +OP4 E036EE 0 +OP4 E036EF 0 +OP4 E036F0 0 +OP4 E036F1 0 +OP4 E036F2 0 +OP4 E036F3 0 +OP4 E036F4 0 +OP4 E036F5 0 +OP4 E036F6 0 +OP4 E036F7 0 +OP4 E036F8 0 +OP4 E036F9 0 +OP4 E036FA 0 +OP4 E036FB 0 +OP4 E036FC 0 +OP4 E036FD 0 +OP4 E036FE 0 +OP4 E036FF 0 +OP4 E03700 0 +OP4 E03701 0 +OP4 E03702 0 +OP4 E03703 0 +OP4 E03704 0 +OP4 E03705 0 +OP4 E03706 0 +OP4 E03707 0 +OP4 E03708 0 +OP4 E03709 0 +OP4 E0370A 0 +OP4 E0370B 0 +OP4 E0370C 0 +OP4 E0370D 0 +OP4 E0370E 0 +OP4 E0370F 0 +OP4 E03710 0 +OP4 E03711 0 +OP4 E03712 0 +OP4 E03713 0 +OP4 E03714 0 +OP4 E03715 0 +OP4 E03716 0 +OP4 E03717 0 +OP4 E03718 0 +OP4 E03719 0 +OP4 E0371A 0 +OP4 E0371B 0 +OP4 E0371C 0 +OP4 E0371D 0 +OP4 E0371E 0 +OP4 E0371F 0 +OP4 E03720 0 +OP4 E03721 0 +OP4 E03722 0 +OP4 E03723 0 +OP4 E03724 0 +OP4 E03725 0 +OP4 E03726 0 +OP4 E03727 0 +OP4 E03728 0 +OP4 E03729 0 +OP4 E0372A 0 +OP4 E0372B 0 +OP4 E0372C 0 +OP4 E0372D 0 +OP4 E0372E 0 +OP4 E0372F 0 +OP4 E03730 0 +OP4 E03731 0 +OP4 E03732 0 +OP4 E03733 0 +OP4 E03734 0 +OP4 E03735 0 +OP4 E03736 0 +OP4 E03737 0 +OP4 E03738 0 +OP4 E03739 0 +OP4 E0373A 0 +OP4 E0373B 0 +OP4 E0373C 0 +OP4 E0373D 0 +OP4 E0373E 0 +OP4 E0373F 0 +OP4 E03740 0 +OP4 E03741 0 +OP4 E03742 0 +OP4 E03743 0 +OP4 E03744 0 +OP4 E03745 0 +OP4 E03746 0 +OP4 E03747 0 +OP4 E03748 0 +OP4 E03749 0 +OP4 E0374A 0 +OP4 E0374B 0 +OP4 E0374C 0 +OP4 E0374D 0 +OP4 E0374E 0 +OP4 E0374F 0 +OP4 E03750 0 +OP4 E03751 0 +OP4 E03752 0 +OP4 E03753 0 +OP4 E03754 0 +OP4 E03755 0 +OP4 E03756 0 +OP4 E03757 0 +OP4 E03758 0 +OP4 E03759 0 +OP4 E0375A 0 +OP4 E0375B 0 +OP4 E0375C 0 +OP4 E0375D 0 +OP4 E0375E 0 +OP4 E0375F 0 +OP4 E03760 0 +OP4 E03761 0 +OP4 E03762 0 +OP4 E03763 0 +OP4 E03764 0 +OP4 E03765 0 +OP4 E03766 0 +OP4 E03767 0 +OP4 E03768 0 +OP4 E03769 0 +OP4 E0376A 0 +OP4 E0376B 0 +OP4 E0376C 0 +OP4 E0376D 0 +OP4 E0376E 0 +OP4 E0376F 0 +OP4 E03770 0 +OP4 E03771 0 +OP4 E03772 0 +OP4 E03773 0 +OP4 E03774 0 +OP4 E03775 0 +OP4 E03776 0 +OP4 E03777 0 +OP4 E03778 0 +OP4 E03779 0 +OP4 E0377A 0 +OP4 E0377B 0 +OP4 E0377C 0 +OP4 E0377D 0 +OP4 E0377E 0 +OP4 E0377F 0 +OP4 E03780 0 +OP4 E03781 0 +OP4 E03782 0 +OP4 E03783 0 +OP4 E03784 0 +OP4 E03785 0 +OP4 E03786 0 +OP4 E03787 0 +OP4 E03788 0 +OP4 E03789 0 +OP4 E0378A 0 +OP4 E0378B 0 +OP4 E0378C 0 +OP4 E0378D 0 +OP4 E0378E 0 +OP4 E0378F 0 +OP4 E03790 0 +OP4 E03791 0 +OP4 E03792 0 +OP4 E03793 0 +OP4 E03794 0 +OP4 E03795 0 +OP4 E03796 0 +OP4 E03797 0 +OP4 E03798 0 +OP4 E03799 0 +OP4 E0379A 0 +OP4 E0379B 0 +OP4 E0379C 0 +OP4 E0379D 0 +OP4 E0379E 0 +OP4 E0379F 0 +OP4 E037A0 0 +OP4 E037A1 0 +OP4 E037A2 0 +OP4 E037A3 0 +OP4 E037A4 0 +OP4 E037A5 0 +OP4 E037A6 0 +OP4 E037A7 0 +OP4 E037A8 0 +OP4 E037A9 0 +OP4 E037AA 0 +OP4 E037AB 0 +OP4 E037AC 0 +OP4 E037AD 0 +OP4 E037AE 0 +OP4 E037AF 0 +OP4 E037B0 0 +OP4 E037B1 0 +OP4 E037B2 0 +OP4 E037B3 0 +OP4 E037B4 0 +OP4 E037B5 0 +OP4 E037B6 0 +OP4 E037B7 0 +OP4 E037B8 0 +OP4 E037B9 0 +OP4 E037BA 0 +OP4 E037BB 0 +OP4 E037BC 0 +OP4 E037BD 0 +OP4 E037BE 0 +OP4 E037BF 0 +OP4 E037C0 0 +OP4 E037C1 0 +OP4 E037C2 0 +OP4 E037C3 0 +OP4 E037C4 0 +OP4 E037C5 0 +OP4 E037C6 0 +OP4 E037C7 0 +OP4 E037C8 0 +OP4 E037C9 0 +OP4 E037CA 0 +OP4 E037CB 0 +OP4 E037CC 0 +OP4 E037CD 0 +OP4 E037CE 0 +OP4 E037CF 0 +OP4 E037D0 0 +OP4 E037D1 0 +OP4 E037D2 0 +OP4 E037D3 0 +OP4 E037D4 0 +OP4 E037D5 0 +OP4 E037D6 0 +OP4 E037D7 0 +OP4 E037D8 0 +OP4 E037D9 0 +OP4 E037DA 0 +OP4 E037DB 0 +OP4 E037DC 0 +OP4 E037DD 0 +OP4 E037DE 0 +OP4 E037DF 0 +OP4 E037E0 0 +OP4 E037E1 0 +OP4 E037E2 0 +OP4 E037E3 0 +OP4 E037E4 0 +OP4 E037E5 0 +OP4 E037E6 0 +OP4 E037E7 0 +OP4 E037E8 0 +OP4 E037E9 0 +OP4 E037EA 0 +OP4 E037EB 0 +OP4 E037EC 0 +OP4 E037ED 0 +OP4 E037EE 0 +OP4 E037EF 0 +OP4 E037F0 0 +OP4 E037F1 0 +OP4 E037F2 0 +OP4 E037F3 0 +OP4 E037F4 0 +OP4 E037F5 0 +OP4 E037F6 0 +OP4 E037F7 0 +OP4 E037F8 0 +OP4 E037F9 0 +OP4 E037FA 0 +OP4 E037FB 0 +OP4 E037FC 0 +OP4 E037FD 0 +OP4 E037FE 0 +OP4 E037FF 0 +OP4 E03800 0 +OP4 E03801 0 +OP4 E03802 0 +OP4 E03803 0 +OP4 E03804 0 +OP4 E03805 0 +OP4 E03806 0 +OP4 E03807 0 +OP4 E03808 0 +OP4 E03809 0 +OP4 E0380A 0 +OP4 E0380B 0 +OP4 E0380C 0 +OP4 E0380D 0 +OP4 E0380E 0 +OP4 E0380F 0 +OP4 E03810 0 +OP4 E03811 0 +OP4 E03812 0 +OP4 E03813 0 +OP4 E03814 0 +OP4 E03815 0 +OP4 E03816 0 +OP4 E03817 0 +OP4 E03818 0 +OP4 E03819 0 +OP4 E0381A 0 +OP4 E0381B 0 +OP4 E0381C 0 +OP4 E0381D 0 +OP4 E0381E 0 +OP4 E0381F 0 +OP4 E03820 0 +OP4 E03821 0 +OP4 E03822 0 +OP4 E03823 0 +OP4 E03824 0 +OP4 E03825 0 +OP4 E03826 0 +OP4 E03827 0 +OP4 E03828 0 +OP4 E03829 0 +OP4 E0382A 0 +OP4 E0382B 0 +OP4 E0382C 0 +OP4 E0382D 0 +OP4 E0382E 0 +OP4 E0382F 0 +OP4 E03830 0 +OP4 E03831 0 +OP4 E03832 0 +OP4 E03833 0 +OP4 E03834 0 +OP4 E03835 0 +OP4 E03836 0 +OP4 E03837 0 +OP4 E03838 0 +OP4 E03839 0 +OP4 E0383A 0 +OP4 E0383B 0 +OP4 E0383C 0 +OP4 E0383D 0 +OP4 E0383E 0 +OP4 E0383F 0 +OP4 E03840 0 +OP4 E03841 0 +OP4 E03842 0 +OP4 E03843 0 +OP4 E03844 0 +OP4 E03845 0 +OP4 E03846 0 +OP4 E03847 0 +OP4 E03848 0 +OP4 E03849 0 +OP4 E0384A 0 +OP4 E0384B 0 +OP4 E0384C 0 +OP4 E0384D 0 +OP4 E0384E 0 +OP4 E0384F 0 +OP4 E03850 0 +OP4 E03851 0 +OP4 E03852 0 +OP4 E03853 0 +OP4 E03854 0 +OP4 E03855 0 +OP4 E03856 0 +OP4 E03857 0 +OP4 E03858 0 +OP4 E03859 0 +OP4 E0385A 0 +OP4 E0385B 0 +OP4 E0385C 0 +OP4 E0385D 0 +OP4 E0385E 0 +OP4 E0385F 0 +OP4 E03860 0 +OP4 E03861 0 +OP4 E03862 0 +OP4 E03863 0 +OP4 E03864 0 +OP4 E03865 0 +OP4 E03866 0 +OP4 E03867 0 +OP4 E03868 0 +OP4 E03869 0 +OP4 E0386A 0 +OP4 E0386B 0 +OP4 E0386C 0 +OP4 E0386D 0 +OP4 E0386E 0 +OP4 E0386F 0 +OP4 E03870 0 +OP4 E03871 0 +OP4 E03872 0 +OP4 E03873 0 +OP4 E03874 0 +OP4 E03875 0 +OP4 E03876 0 +OP4 E03877 0 +OP4 E03878 0 +OP4 E03879 0 +OP4 E0387A 0 +OP4 E0387B 0 +OP4 E0387C 0 +OP4 E0387D 0 +OP4 E0387E 0 +OP4 E0387F 0 +OP4 E03880 0 +OP4 E03881 0 +OP4 E03882 0 +OP4 E03883 0 +OP4 E03884 0 +OP4 E03885 0 +OP4 E03886 0 +OP4 E03887 0 +OP4 E03888 0 +OP4 E03889 0 +OP4 E0388A 0 +OP4 E0388B 0 +OP4 E0388C 0 +OP4 E0388D 0 +OP4 E0388E 0 +OP4 E0388F 0 +OP4 E03890 0 +OP4 E03891 0 +OP4 E03892 0 +OP4 E03893 0 +OP4 E03894 0 +OP4 E03895 0 +OP4 E03896 0 +OP4 E03897 0 +OP4 E03898 0 +OP4 E03899 0 +OP4 E0389A 0 +OP4 E0389B 0 +OP4 E0389C 0 +OP4 E0389D 0 +OP4 E0389E 0 +OP4 E0389F 0 +OP4 E038A0 0 +OP4 E038A1 0 +OP4 E038A2 0 +OP4 E038A3 0 +OP4 E038A4 0 +OP4 E038A5 0 +OP4 E038A6 0 +OP4 E038A7 0 +OP4 E038A8 0 +OP4 E038A9 0 +OP4 E038AA 0 +OP4 E038AB 0 +OP4 E038AC 0 +OP4 E038AD 0 +OP4 E038AE 0 +OP4 E038AF 0 +OP4 E038B0 0 +OP4 E038B1 0 +OP4 E038B2 0 +OP4 E038B3 0 +OP4 E038B4 0 +OP4 E038B5 0 +OP4 E038B6 0 +OP4 E038B7 0 +OP4 E038B8 0 +OP4 E038B9 0 +OP4 E038BA 0 +OP4 E038BB 0 +OP4 E038BC 0 +OP4 E038BD 0 +OP4 E038BE 0 +OP4 E038BF 0 +OP4 E038C0 0 +OP4 E038C1 0 +OP4 E038C2 0 +OP4 E038C3 0 +OP4 E038C4 0 +OP4 E038C5 0 +OP4 E038C6 0 +OP4 E038C7 0 +OP4 E038C8 0 +OP4 E038C9 0 +OP4 E038CA 0 +OP4 E038CB 0 +OP4 E038CC 0 +OP4 E038CD 0 +OP4 E038CE 0 +OP4 E038CF 0 +OP4 E038D0 0 +OP4 E038D1 0 +OP4 E038D2 0 +OP4 E038D3 0 +OP4 E038D4 0 +OP4 E038D5 0 +OP4 E038D6 0 +OP4 E038D7 0 +OP4 E038D8 0 +OP4 E038D9 0 +OP4 E038DA 0 +OP4 E038DB 0 +OP4 E038DC 0 +OP4 E038DD 0 +OP4 E038DE 0 +OP4 E038DF 0 +OP4 E038E0 0 +OP4 E038E1 0 +OP4 E038E2 0 +OP4 E038E3 0 +OP4 E038E4 0 +OP4 E038E5 0 +OP4 E038E6 0 +OP4 E038E7 0 +OP4 E038E8 0 +OP4 E038E9 0 +OP4 E038EA 0 +OP4 E038EB 0 +OP4 E038EC 0 +OP4 E038ED 0 +OP4 E038EE 0 +OP4 E038EF 0 +OP4 E038F0 0 +OP4 E038F1 0 +OP4 E038F2 0 +OP4 E038F3 0 +OP4 E038F4 0 +OP4 E038F5 0 +OP4 E038F6 0 +OP4 E038F7 0 +OP4 E038F8 0 +OP4 E038F9 0 +OP4 E038FA 0 +OP4 E038FB 0 +OP4 E038FC 0 +OP4 E038FD 0 +OP4 E038FE 0 +OP4 E038FF 0 +OP4 E03900 0 +OP4 E03901 0 +OP4 E03902 0 +OP4 E03903 0 +OP4 E03904 0 +OP4 E03905 0 +OP4 E03906 0 +OP4 E03907 0 +OP4 E03908 0 +OP4 E03909 0 +OP4 E0390A 0 +OP4 E0390B 0 +OP4 E0390C 0 +OP4 E0390D 0 +OP4 E0390E 0 +OP4 E0390F 0 +OP4 E03910 0 +OP4 E03911 0 +OP4 E03912 0 +OP4 E03913 0 +OP4 E03914 0 +OP4 E03915 0 +OP4 E03916 0 +OP4 E03917 0 +OP4 E03918 0 +OP4 E03919 0 +OP4 E0391A 0 +OP4 E0391B 0 +OP4 E0391C 0 +OP4 E0391D 0 +OP4 E0391E 0 +OP4 E0391F 0 +OP4 E03920 0 +OP4 E03921 0 +OP4 E03922 0 +OP4 E03923 0 +OP4 E03924 0 +OP4 E03925 0 +OP4 E03926 0 +OP4 E03927 0 +OP4 E03928 0 +OP4 E03929 0 +OP4 E0392A 0 +OP4 E0392B 0 +OP4 E0392C 0 +OP4 E0392D 0 +OP4 E0392E 0 +OP4 E0392F 0 +OP4 E03930 0 +OP4 E03931 0 +OP4 E03932 0 +OP4 E03933 0 +OP4 E03934 0 +OP4 E03935 0 +OP4 E03936 0 +OP4 E03937 0 +OP4 E03938 0 +OP4 E03939 0 +OP4 E0393A 0 +OP4 E0393B 0 +OP4 E0393C 0 +OP4 E0393D 0 +OP4 E0393E 0 +OP4 E0393F 0 +OP4 E03940 0 +OP4 E03941 0 +OP4 E03942 0 +OP4 E03943 0 +OP4 E03944 0 +OP4 E03945 0 +OP4 E03946 0 +OP4 E03947 0 +OP4 E03948 0 +OP4 E03949 0 +OP4 E0394A 0 +OP4 E0394B 0 +OP4 E0394C 0 +OP4 E0394D 0 +OP4 E0394E 0 +OP4 E0394F 0 +OP4 E03950 0 +OP4 E03951 0 +OP4 E03952 0 +OP4 E03953 0 +OP4 E03954 0 +OP4 E03955 0 +OP4 E03956 0 +OP4 E03957 0 +OP4 E03958 0 +OP4 E03959 0 +OP4 E0395A 0 +OP4 E0395B 0 +OP4 E0395C 0 +OP4 E0395D 0 +OP4 E0395E 0 +OP4 E0395F 0 +OP4 E03960 0 +OP4 E03961 0 +OP4 E03962 0 +OP4 E03963 0 +OP4 E03964 0 +OP4 E03965 0 +OP4 E03966 0 +OP4 E03967 0 +OP4 E03968 0 +OP4 E03969 0 +OP4 E0396A 0 +OP4 E0396B 0 +OP4 E0396C 0 +OP4 E0396D 0 +OP4 E0396E 0 +OP4 E0396F 0 +OP4 E03970 0 +OP4 E03971 0 +OP4 E03972 0 +OP4 E03973 0 +OP4 E03974 0 +OP4 E03975 0 +OP4 E03976 0 +OP4 E03977 0 +OP4 E03978 0 +OP4 E03979 0 +OP4 E0397A 0 +OP4 E0397B 0 +OP4 E0397C 0 +OP4 E0397D 0 +OP4 E0397E 0 +OP4 E0397F 0 +OP4 E03980 0 +OP4 E03981 0 +OP4 E03982 0 +OP4 E03983 0 +OP4 E03984 0 +OP4 E03985 0 +OP4 E03986 0 +OP4 E03987 0 +OP4 E03988 0 +OP4 E03989 0 +OP4 E0398A 0 +OP4 E0398B 0 +OP4 E0398C 0 +OP4 E0398D 0 +OP4 E0398E 0 +OP4 E0398F 0 +OP4 E03990 0 +OP4 E03991 0 +OP4 E03992 0 +OP4 E03993 0 +OP4 E03994 0 +OP4 E03995 0 +OP4 E03996 0 +OP4 E03997 0 +OP4 E03998 0 +OP4 E03999 0 +OP4 E0399A 0 +OP4 E0399B 0 +OP4 E0399C 0 +OP4 E0399D 0 +OP4 E0399E 0 +OP4 E0399F 0 +OP4 E039A0 0 +OP4 E039A1 0 +OP4 E039A2 0 +OP4 E039A3 0 +OP4 E039A4 0 +OP4 E039A5 0 +OP4 E039A6 0 +OP4 E039A7 0 +OP4 E039A8 0 +OP4 E039A9 0 +OP4 E039AA 0 +OP4 E039AB 0 +OP4 E039AC 0 +OP4 E039AD 0 +OP4 E039AE 0 +OP4 E039AF 0 +OP4 E039B0 0 +OP4 E039B1 0 +OP4 E039B2 0 +OP4 E039B3 0 +OP4 E039B4 0 +OP4 E039B5 0 +OP4 E039B6 0 +OP4 E039B7 0 +OP4 E039B8 0 +OP4 E039B9 0 +OP4 E039BA 0 +OP4 E039BB 0 +OP4 E039BC 0 +OP4 E039BD 0 +OP4 E039BE 0 +OP4 E039BF 0 +OP4 E039C0 0 +OP4 E039C1 0 +OP4 E039C2 0 +OP4 E039C3 0 +OP4 E039C4 0 +OP4 E039C5 0 +OP4 E039C6 0 +OP4 E039C7 0 +OP4 E039C8 0 +OP4 E039C9 0 +OP4 E039CA 0 +OP4 E039CB 0 +OP4 E039CC 0 +OP4 E039CD 0 +OP4 E039CE 0 +OP4 E039CF 0 +OP4 E039D0 0 +OP4 E039D1 0 +OP4 E039D2 0 +OP4 E039D3 0 +OP4 E039D4 0 +OP4 E039D5 0 +OP4 E039D6 0 +OP4 E039D7 0 +OP4 E039D8 0 +OP4 E039D9 0 +OP4 E039DA 0 +OP4 E039DB 0 +OP4 E039DC 0 +OP4 E039DD 0 +OP4 E039DE 0 +OP4 E039DF 0 +OP4 E039E0 0 +OP4 E039E1 0 +OP4 E039E2 0 +OP4 E039E3 0 +OP4 E039E4 0 +OP4 E039E5 0 +OP4 E039E6 0 +OP4 E039E7 0 +OP4 E039E8 0 +OP4 E039E9 0 +OP4 E039EA 0 +OP4 E039EB 0 +OP4 E039EC 0 +OP4 E039ED 0 +OP4 E039EE 0 +OP4 E039EF 0 +OP4 E039F0 0 +OP4 E039F1 0 +OP4 E039F2 0 +OP4 E039F3 0 +OP4 E039F4 0 +OP4 E039F5 0 +OP4 E039F6 0 +OP4 E039F7 0 +OP4 E039F8 0 +OP4 E039F9 0 +OP4 E039FA 0 +OP4 E039FB 0 +OP4 E039FC 0 +OP4 E039FD 0 +OP4 E039FE 0 +OP4 E039FF 0 +OP4 E03A00 0 +OP4 E03A01 0 +OP4 E03A02 0 +OP4 E03A03 0 +OP4 E03A04 0 +OP4 E03A05 0 +OP4 E03A06 0 +OP4 E03A07 0 +OP4 E03A08 0 +OP4 E03A09 0 +OP4 E03A0A 0 +OP4 E03A0B 0 +OP4 E03A0C 0 +OP4 E03A0D 0 +OP4 E03A0E 0 +OP4 E03A0F 0 +OP4 E03A10 0 +OP4 E03A11 0 +OP4 E03A12 0 +OP4 E03A13 0 +OP4 E03A14 0 +OP4 E03A15 0 +OP4 E03A16 0 +OP4 E03A17 0 +OP4 E03A18 0 +OP4 E03A19 0 +OP4 E03A1A 0 +OP4 E03A1B 0 +OP4 E03A1C 0 +OP4 E03A1D 0 +OP4 E03A1E 0 +OP4 E03A1F 0 +OP4 E03A20 0 +OP4 E03A21 0 +OP4 E03A22 0 +OP4 E03A23 0 +OP4 E03A24 0 +OP4 E03A25 0 +OP4 E03A26 0 +OP4 E03A27 0 +OP4 E03A28 0 +OP4 E03A29 0 +OP4 E03A2A 0 +OP4 E03A2B 0 +OP4 E03A2C 0 +OP4 E03A2D 0 +OP4 E03A2E 0 +OP4 E03A2F 0 +OP4 E03A30 0 +OP4 E03A31 0 +OP4 E03A32 0 +OP4 E03A33 0 +OP4 E03A34 0 +OP4 E03A35 0 +OP4 E03A36 0 +OP4 E03A37 0 +OP4 E03A38 0 +OP4 E03A39 0 +OP4 E03A3A 0 +OP4 E03A3B 0 +OP4 E03A3C 0 +OP4 E03A3D 0 +OP4 E03A3E 0 +OP4 E03A3F 0 +OP4 E03A40 0 +OP4 E03A41 0 +OP4 E03A42 0 +OP4 E03A43 0 +OP4 E03A44 0 +OP4 E03A45 0 +OP4 E03A46 0 +OP4 E03A47 0 +OP4 E03A48 0 +OP4 E03A49 0 +OP4 E03A4A 0 +OP4 E03A4B 0 +OP4 E03A4C 0 +OP4 E03A4D 0 +OP4 E03A4E 0 +OP4 E03A4F 0 +OP4 E03A50 0 +OP4 E03A51 0 +OP4 E03A52 0 +OP4 E03A53 0 +OP4 E03A54 0 +OP4 E03A55 0 +OP4 E03A56 0 +OP4 E03A57 0 +OP4 E03A58 0 +OP4 E03A59 0 +OP4 E03A5A 0 +OP4 E03A5B 0 +OP4 E03A5C 0 +OP4 E03A5D 0 +OP4 E03A5E 0 +OP4 E03A5F 0 +OP4 E03A60 0 +OP4 E03A61 0 +OP4 E03A62 0 +OP4 E03A63 0 +OP4 E03A64 0 +OP4 E03A65 0 +OP4 E03A66 0 +OP4 E03A67 0 +OP4 E03A68 0 +OP4 E03A69 0 +OP4 E03A6A 0 +OP4 E03A6B 0 +OP4 E03A6C 0 +OP4 E03A6D 0 +OP4 E03A6E 0 +OP4 E03A6F 0 +OP4 E03A70 0 +OP4 E03A71 0 +OP4 E03A72 0 +OP4 E03A73 0 +OP4 E03A74 0 +OP4 E03A75 0 +OP4 E03A76 0 +OP4 E03A77 0 +OP4 E03A78 0 +OP4 E03A79 0 +OP4 E03A7A 0 +OP4 E03A7B 0 +OP4 E03A7C 0 +OP4 E03A7D 0 +OP4 E03A7E 0 +OP4 E03A7F 0 +OP4 E03A80 0 +OP4 E03A81 0 +OP4 E03A82 0 +OP4 E03A83 0 +OP4 E03A84 0 +OP4 E03A85 0 +OP4 E03A86 0 +OP4 E03A87 0 +OP4 E03A88 0 +OP4 E03A89 0 +OP4 E03A8A 0 +OP4 E03A8B 0 +OP4 E03A8C 0 +OP4 E03A8D 0 +OP4 E03A8E 0 +OP4 E03A8F 0 +OP4 E03A90 0 +OP4 E03A91 0 +OP4 E03A92 0 +OP4 E03A93 0 +OP4 E03A94 0 +OP4 E03A95 0 +OP4 E03A96 0 +OP4 E03A97 0 +OP4 E03A98 0 +OP4 E03A99 0 +OP4 E03A9A 0 +OP4 E03A9B 0 +OP4 E03A9C 0 +OP4 E03A9D 0 +OP4 E03A9E 0 +OP4 E03A9F 0 +OP4 E03AA0 0 +OP4 E03AA1 0 +OP4 E03AA2 0 +OP4 E03AA3 0 +OP4 E03AA4 0 +OP4 E03AA5 0 +OP4 E03AA6 0 +OP4 E03AA7 0 +OP4 E03AA8 0 +OP4 E03AA9 0 +OP4 E03AAA 0 +OP4 E03AAB 0 +OP4 E03AAC 0 +OP4 E03AAD 0 +OP4 E03AAE 0 +OP4 E03AAF 0 +OP4 E03AB0 0 +OP4 E03AB1 0 +OP4 E03AB2 0 +OP4 E03AB3 0 +OP4 E03AB4 0 +OP4 E03AB5 0 +OP4 E03AB6 0 +OP4 E03AB7 0 +OP4 E03AB8 0 +OP4 E03AB9 0 +OP4 E03ABA 0 +OP4 E03ABB 0 +OP4 E03ABC 0 +OP4 E03ABD 0 +OP4 E03ABE 0 +OP4 E03ABF 0 +OP4 E03AC0 0 +OP4 E03AC1 0 +OP4 E03AC2 0 +OP4 E03AC3 0 +OP4 E03AC4 0 +OP4 E03AC5 0 +OP4 E03AC6 0 +OP4 E03AC7 0 +OP4 E03AC8 0 +OP4 E03AC9 0 +OP4 E03ACA 0 +OP4 E03ACB 0 +OP4 E03ACC 0 +OP4 E03ACD 0 +OP4 E03ACE 0 +OP4 E03ACF 0 +OP4 E03AD0 0 +OP4 E03AD1 0 +OP4 E03AD2 0 +OP4 E03AD3 0 +OP4 E03AD4 0 +OP4 E03AD5 0 +OP4 E03AD6 0 +OP4 E03AD7 0 +OP4 E03AD8 0 +OP4 E03AD9 0 +OP4 E03ADA 0 +OP4 E03ADB 0 +OP4 E03ADC 0 +OP4 E03ADD 0 +OP4 E03ADE 0 +OP4 E03ADF 0 +OP4 E03AE0 0 +OP4 E03AE1 0 +OP4 E03AE2 0 +OP4 E03AE3 0 +OP4 E03AE4 0 +OP4 E03AE5 0 +OP4 E03AE6 0 +OP4 E03AE7 0 +OP4 E03AE8 0 +OP4 E03AE9 0 +OP4 E03AEA 0 +OP4 E03AEB 0 +OP4 E03AEC 0 +OP4 E03AED 0 +OP4 E03AEE 0 +OP4 E03AEF 0 +OP4 E03AF0 0 +OP4 E03AF1 0 +OP4 E03AF2 0 +OP4 E03AF3 0 +OP4 E03AF4 0 +OP4 E03AF5 0 +OP4 E03AF6 0 +OP4 E03AF7 0 +OP4 E03AF8 0 +OP4 E03AF9 0 +OP4 E03AFA 0 +OP4 E03AFB 0 +OP4 E03AFC 0 +OP4 E03AFD 0 +OP4 E03AFE 0 +OP4 E03AFF 0 +OP4 E03B00 0 +OP4 E03B01 0 +OP4 E03B02 0 +OP4 E03B03 0 +OP4 E03B04 0 +OP4 E03B05 0 +OP4 E03B06 0 +OP4 E03B07 0 +OP4 E03B08 0 +OP4 E03B09 0 +OP4 E03B0A 0 +OP4 E03B0B 0 +OP4 E03B0C 0 +OP4 E03B0D 0 +OP4 E03B0E 0 +OP4 E03B0F 0 +OP4 E03B10 0 +OP4 E03B11 0 +OP4 E03B12 0 +OP4 E03B13 0 +OP4 E03B14 0 +OP4 E03B15 0 +OP4 E03B16 0 +OP4 E03B17 0 +OP4 E03B18 0 +OP4 E03B19 0 +OP4 E03B1A 0 +OP4 E03B1B 0 +OP4 E03B1C 0 +OP4 E03B1D 0 +OP4 E03B1E 0 +OP4 E03B1F 0 +OP4 E03B20 0 +OP4 E03B21 0 +OP4 E03B22 0 +OP4 E03B23 0 +OP4 E03B24 0 +OP4 E03B25 0 +OP4 E03B26 0 +OP4 E03B27 0 +OP4 E03B28 0 +OP4 E03B29 0 +OP4 E03B2A 0 +OP4 E03B2B 0 +OP4 E03B2C 0 +OP4 E03B2D 0 +OP4 E03B2E 0 +OP4 E03B2F 0 +OP4 E03B30 0 +OP4 E03B31 0 +OP4 E03B32 0 +OP4 E03B33 0 +OP4 E03B34 0 +OP4 E03B35 0 +OP4 E03B36 0 +OP4 E03B37 0 +OP4 E03B38 0 +OP4 E03B39 0 +OP4 E03B3A 0 +OP4 E03B3B 0 +OP4 E03B3C 0 +OP4 E03B3D 0 +OP4 E03B3E 0 +OP4 E03B3F 0 +OP4 E03B40 0 +OP4 E03B41 0 +OP4 E03B42 0 +OP4 E03B43 0 +OP4 E03B44 0 +OP4 E03B45 0 +OP4 E03B46 0 +OP4 E03B47 0 +OP4 E03B48 0 +OP4 E03B49 0 +OP4 E03B4A 0 +OP4 E03B4B 0 +OP4 E03B4C 0 +OP4 E03B4D 0 +OP4 E03B4E 0 +OP4 E03B4F 0 +OP4 E03B50 0 +OP4 E03B51 0 +OP4 E03B52 0 +OP4 E03B53 0 +OP4 E03B54 0 +OP4 E03B55 0 +OP4 E03B56 0 +OP4 E03B57 0 +OP4 E03B58 0 +OP4 E03B59 0 +OP4 E03B5A 0 +OP4 E03B5B 0 +OP4 E03B5C 0 +OP4 E03B5D 0 +OP4 E03B5E 0 +OP4 E03B5F 0 +OP4 E03B60 0 +OP4 E03B61 0 +OP4 E03B62 0 +OP4 E03B63 0 +OP4 E03B64 0 +OP4 E03B65 0 +OP4 E03B66 0 +OP4 E03B67 0 +OP4 E03B68 0 +OP4 E03B69 0 +OP4 E03B6A 0 +OP4 E03B6B 0 +OP4 E03B6C 0 +OP4 E03B6D 0 +OP4 E03B6E 0 +OP4 E03B6F 0 +OP4 E03B70 0 +OP4 E03B71 0 +OP4 E03B72 0 +OP4 E03B73 0 +OP4 E03B74 0 +OP4 E03B75 0 +OP4 E03B76 0 +OP4 E03B77 0 +OP4 E03B78 0 +OP4 E03B79 0 +OP4 E03B7A 0 +OP4 E03B7B 0 +OP4 E03B7C 0 +OP4 E03B7D 0 +OP4 E03B7E 0 +OP4 E03B7F 0 +OP4 E03B80 0 +OP4 E03B81 0 +OP4 E03B82 0 +OP4 E03B83 0 +OP4 E03B84 0 +OP4 E03B85 0 +OP4 E03B86 0 +OP4 E03B87 0 +OP4 E03B88 0 +OP4 E03B89 0 +OP4 E03B8A 0 +OP4 E03B8B 0 +OP4 E03B8C 0 +OP4 E03B8D 0 +OP4 E03B8E 0 +OP4 E03B8F 0 +OP4 E03B90 0 +OP4 E03B91 0 +OP4 E03B92 0 +OP4 E03B93 0 +OP4 E03B94 0 +OP4 E03B95 0 +OP4 E03B96 0 +OP4 E03B97 0 +OP4 E03B98 0 +OP4 E03B99 0 +OP4 E03B9A 0 +OP4 E03B9B 0 +OP4 E03B9C 0 +OP4 E03B9D 0 +OP4 E03B9E 0 +OP4 E03B9F 0 +OP4 E03BA0 0 +OP4 E03BA1 0 +OP4 E03BA2 0 +OP4 E03BA3 0 +OP4 E03BA4 0 +OP4 E03BA5 0 +OP4 E03BA6 0 +OP4 E03BA7 0 +OP4 E03BA8 0 +OP4 E03BA9 0 +OP4 E03BAA 0 +OP4 E03BAB 0 +OP4 E03BAC 0 +OP4 E03BAD 0 +OP4 E03BAE 0 +OP4 E03BAF 0 +OP4 E03BB0 0 +OP4 E03BB1 0 +OP4 E03BB2 0 +OP4 E03BB3 0 +OP4 E03BB4 0 +OP4 E03BB5 0 +OP4 E03BB6 0 +OP4 E03BB7 0 +OP4 E03BB8 0 +OP4 E03BB9 0 +OP4 E03BBA 0 +OP4 E03BBB 0 +OP4 E03BBC 0 +OP4 E03BBD 0 +OP4 E03BBE 0 +OP4 E03BBF 0 +OP4 E03BC0 0 +OP4 E03BC1 0 +OP4 E03BC2 0 +OP4 E03BC3 0 +OP4 E03BC4 0 +OP4 E03BC5 0 +OP4 E03BC6 0 +OP4 E03BC7 0 +OP4 E03BC8 0 +OP4 E03BC9 0 +OP4 E03BCA 0 +OP4 E03BCB 0 +OP4 E03BCC 0 +OP4 E03BCD 0 +OP4 E03BCE 0 +OP4 E03BCF 0 +OP4 E03BD0 0 +OP4 E03BD1 0 +OP4 E03BD2 0 +OP4 E03BD3 0 +OP4 E03BD4 0 +OP4 E03BD5 0 +OP4 E03BD6 0 +OP4 E03BD7 0 +OP4 E03BD8 0 +OP4 E03BD9 0 +OP4 E03BDA 0 +OP4 E03BDB 0 +OP4 E03BDC 0 +OP4 E03BDD 0 +OP4 E03BDE 0 +OP4 E03BDF 0 +OP4 E03BE0 0 +OP4 E03BE1 0 +OP4 E03BE2 0 +OP4 E03BE3 0 +OP4 E03BE4 0 +OP4 E03BE5 0 +OP4 E03BE6 0 +OP4 E03BE7 0 +OP4 E03BE8 0 +OP4 E03BE9 0 +OP4 E03BEA 0 +OP4 E03BEB 0 +OP4 E03BEC 0 +OP4 E03BED 0 +OP4 E03BEE 0 +OP4 E03BEF 0 +OP4 E03BF0 0 +OP4 E03BF1 0 +OP4 E03BF2 0 +OP4 E03BF3 0 +OP4 E03BF4 0 +OP4 E03BF5 0 +OP4 E03BF6 0 +OP4 E03BF7 0 +OP4 E03BF8 0 +OP4 E03BF9 0 +OP4 E03BFA 0 +OP4 E03BFB 0 +OP4 E03BFC 0 +OP4 E03BFD 0 +OP4 E03BFE 0 +OP4 E03BFF 0 +OP4 E03C00 0 +OP4 E03C01 0 +OP4 E03C02 0 +OP4 E03C03 0 +OP4 E03C04 0 +OP4 E03C05 0 +OP4 E03C06 0 +OP4 E03C07 0 +OP4 E03C08 0 +OP4 E03C09 0 +OP4 E03C0A 0 +OP4 E03C0B 0 +OP4 E03C0C 0 +OP4 E03C0D 0 +OP4 E03C0E 0 +OP4 E03C0F 0 +OP4 E03C10 0 +OP4 E03C11 0 +OP4 E03C12 0 +OP4 E03C13 0 +OP4 E03C14 0 +OP4 E03C15 0 +OP4 E03C16 0 +OP4 E03C17 0 +OP4 E03C18 0 +OP4 E03C19 0 +OP4 E03C1A 0 +OP4 E03C1B 0 +OP4 E03C1C 0 +OP4 E03C1D 0 +OP4 E03C1E 0 +OP4 E03C1F 0 +OP4 E03C20 0 +OP4 E03C21 0 +OP4 E03C22 0 +OP4 E03C23 0 +OP4 E03C24 0 +OP4 E03C25 0 +OP4 E03C26 0 +OP4 E03C27 0 +OP4 E03C28 0 +OP4 E03C29 0 +OP4 E03C2A 0 +OP4 E03C2B 0 +OP4 E03C2C 0 +OP4 E03C2D 0 +OP4 E03C2E 0 +OP4 E03C2F 0 +OP4 E03C30 0 +OP4 E03C31 0 +OP4 E03C32 0 +OP4 E03C33 0 +OP4 E03C34 0 +OP4 E03C35 0 +OP4 E03C36 0 +OP4 E03C37 0 +OP4 E03C38 0 +OP4 E03C39 0 +OP4 E03C3A 0 +OP4 E03C3B 0 +OP4 E03C3C 0 +OP4 E03C3D 0 +OP4 E03C3E 0 +OP4 E03C3F 0 +OP4 E03C40 0 +OP4 E03C41 0 +OP4 E03C42 0 +OP4 E03C43 0 +OP4 E03C44 0 +OP4 E03C45 0 +OP4 E03C46 0 +OP4 E03C47 0 +OP4 E03C48 0 +OP4 E03C49 0 +OP4 E03C4A 0 +OP4 E03C4B 0 +OP4 E03C4C 0 +OP4 E03C4D 0 +OP4 E03C4E 0 +OP4 E03C4F 0 +OP4 E03C50 0 +OP4 E03C51 0 +OP4 E03C52 0 +OP4 E03C53 0 +OP4 E03C54 0 +OP4 E03C55 0 +OP4 E03C56 0 +OP4 E03C57 0 +OP4 E03C58 0 +OP4 E03C59 0 +OP4 E03C5A 0 +OP4 E03C5B 0 +OP4 E03C5C 0 +OP4 E03C5D 0 +OP4 E03C5E 0 +OP4 E03C5F 0 +OP4 E03C60 0 +OP4 E03C61 0 +OP4 E03C62 0 +OP4 E03C63 0 +OP4 E03C64 0 +OP4 E03C65 0 +OP4 E03C66 0 +OP4 E03C67 0 +OP4 E03C68 0 +OP4 E03C69 0 +OP4 E03C6A 0 +OP4 E03C6B 0 +OP4 E03C6C 0 +OP4 E03C6D 0 +OP4 E03C6E 0 +OP4 E03C6F 0 +OP4 E03C70 0 +OP4 E03C71 0 +OP4 E03C72 0 +OP4 E03C73 0 +OP4 E03C74 0 +OP4 E03C75 0 +OP4 E03C76 0 +OP4 E03C77 0 +OP4 E03C78 0 +OP4 E03C79 0 +OP4 E03C7A 0 +OP4 E03C7B 0 +OP4 E03C7C 0 +OP4 E03C7D 0 +OP4 E03C7E 0 +OP4 E03C7F 0 +OP4 E03C80 0 +OP4 E03C81 0 +OP4 E03C82 0 +OP4 E03C83 0 +OP4 E03C84 0 +OP4 E03C85 0 +OP4 E03C86 0 +OP4 E03C87 0 +OP4 E03C88 0 +OP4 E03C89 0 +OP4 E03C8A 0 +OP4 E03C8B 0 +OP4 E03C8C 0 +OP4 E03C8D 0 +OP4 E03C8E 0 +OP4 E03C8F 0 +OP4 E03C90 0 +OP4 E03C91 0 +OP4 E03C92 0 +OP4 E03C93 0 +OP4 E03C94 0 +OP4 E03C95 0 +OP4 E03C96 0 +OP4 E03C97 0 +OP4 E03C98 0 +OP4 E03C99 0 +OP4 E03C9A 0 +OP4 E03C9B 0 +OP4 E03C9C 0 +OP4 E03C9D 0 +OP4 E03C9E 0 +OP4 E03C9F 0 +OP4 E03CA0 0 +OP4 E03CA1 0 +OP4 E03CA2 0 +OP4 E03CA3 0 +OP4 E03CA4 0 +OP4 E03CA5 0 +OP4 E03CA6 0 +OP4 E03CA7 0 +OP4 E03CA8 0 +OP4 E03CA9 0 +OP4 E03CAA 0 +OP4 E03CAB 0 +OP4 E03CAC 0 +OP4 E03CAD 0 +OP4 E03CAE 0 +OP4 E03CAF 0 +OP4 E03CB0 0 +OP4 E03CB1 0 +OP4 E03CB2 0 +OP4 E03CB3 0 +OP4 E03CB4 0 +OP4 E03CB5 0 +OP4 E03CB6 0 +OP4 E03CB7 0 +OP4 E03CB8 0 +OP4 E03CB9 0 +OP4 E03CBA 0 +OP4 E03CBB 0 +OP4 E03CBC 0 +OP4 E03CBD 0 +OP4 E03CBE 0 +OP4 E03CBF 0 +OP4 E03CC0 0 +OP4 E03CC1 0 +OP4 E03CC2 0 +OP4 E03CC3 0 +OP4 E03CC4 0 +OP4 E03CC5 0 +OP4 E03CC6 0 +OP4 E03CC7 0 +OP4 E03CC8 0 +OP4 E03CC9 0 +OP4 E03CCA 0 +OP4 E03CCB 0 +OP4 E03CCC 0 +OP4 E03CCD 0 +OP4 E03CCE 0 +OP4 E03CCF 0 +OP4 E03CD0 0 +OP4 E03CD1 0 +OP4 E03CD2 0 +OP4 E03CD3 0 +OP4 E03CD4 0 +OP4 E03CD5 0 +OP4 E03CD6 0 +OP4 E03CD7 0 +OP4 E03CD8 0 +OP4 E03CD9 0 +OP4 E03CDA 0 +OP4 E03CDB 0 +OP4 E03CDC 0 +OP4 E03CDD 0 +OP4 E03CDE 0 +OP4 E03CDF 0 +OP4 E03CE0 0 +OP4 E03CE1 0 +OP4 E03CE2 0 +OP4 E03CE3 0 +OP4 E03CE4 0 +OP4 E03CE5 0 +OP4 E03CE6 0 +OP4 E03CE7 0 +OP4 E03CE8 0 +OP4 E03CE9 0 +OP4 E03CEA 0 +OP4 E03CEB 0 +OP4 E03CEC 0 +OP4 E03CED 0 +OP4 E03CEE 0 +OP4 E03CEF 0 +OP4 E03CF0 0 +OP4 E03CF1 0 +OP4 E03CF2 0 +OP4 E03CF3 0 +OP4 E03CF4 0 +OP4 E03CF5 0 +OP4 E03CF6 0 +OP4 E03CF7 0 +OP4 E03CF8 0 +OP4 E03CF9 0 +OP4 E03CFA 0 +OP4 E03CFB 0 +OP4 E03CFC 0 +OP4 E03CFD 0 +OP4 E03CFE 0 +OP4 E03CFF 0 +OP4 E03D00 0 +OP4 E03D01 0 +OP4 E03D02 0 +OP4 E03D03 0 +OP4 E03D04 0 +OP4 E03D05 0 +OP4 E03D06 0 +OP4 E03D07 0 +OP4 E03D08 0 +OP4 E03D09 0 +OP4 E03D0A 0 +OP4 E03D0B 0 +OP4 E03D0C 0 +OP4 E03D0D 0 +OP4 E03D0E 0 +OP4 E03D0F 0 +OP4 E03D10 0 +OP4 E03D11 0 +OP4 E03D12 0 +OP4 E03D13 0 +OP4 E03D14 0 +OP4 E03D15 0 +OP4 E03D16 0 +OP4 E03D17 0 +OP4 E03D18 0 +OP4 E03D19 0 +OP4 E03D1A 0 +OP4 E03D1B 0 +OP4 E03D1C 0 +OP4 E03D1D 0 +OP4 E03D1E 0 +OP4 E03D1F 0 +OP4 E03D20 0 +OP4 E03D21 0 +OP4 E03D22 0 +OP4 E03D23 0 +OP4 E03D24 0 +OP4 E03D25 0 +OP4 E03D26 0 +OP4 E03D27 0 +OP4 E03D28 0 +OP4 E03D29 0 +OP4 E03D2A 0 +OP4 E03D2B 0 +OP4 E03D2C 0 +OP4 E03D2D 0 +OP4 E03D2E 0 +OP4 E03D2F 0 +OP4 E03D30 0 +OP4 E03D31 0 +OP4 E03D32 0 +OP4 E03D33 0 +OP4 E03D34 0 +OP4 E03D35 0 +OP4 E03D36 0 +OP4 E03D37 0 +OP4 E03D38 0 +OP4 E03D39 0 +OP4 E03D3A 0 +OP4 E03D3B 0 +OP4 E03D3C 0 +OP4 E03D3D 0 +OP4 E03D3E 0 +OP4 E03D3F 0 +OP4 E03D40 0 +OP4 E03D41 0 +OP4 E03D42 0 +OP4 E03D43 0 +OP4 E03D44 0 +OP4 E03D45 0 +OP4 E03D46 0 +OP4 E03D47 0 +OP4 E03D48 0 +OP4 E03D49 0 +OP4 E03D4A 0 +OP4 E03D4B 0 +OP4 E03D4C 0 +OP4 E03D4D 0 +OP4 E03D4E 0 +OP4 E03D4F 0 +OP4 E03D50 0 +OP4 E03D51 0 +OP4 E03D52 0 +OP4 E03D53 0 +OP4 E03D54 0 +OP4 E03D55 0 +OP4 E03D56 0 +OP4 E03D57 0 +OP4 E03D58 0 +OP4 E03D59 0 +OP4 E03D5A 0 +OP4 E03D5B 0 +OP4 E03D5C 0 +OP4 E03D5D 0 +OP4 E03D5E 0 +OP4 E03D5F 0 +OP4 E03D60 0 +OP4 E03D61 0 +OP4 E03D62 0 +OP4 E03D63 0 +OP4 E03D64 0 +OP4 E03D65 0 +OP4 E03D66 0 +OP4 E03D67 0 +OP4 E03D68 0 +OP4 E03D69 0 +OP4 E03D6A 0 +OP4 E03D6B 0 +OP4 E03D6C 0 +OP4 E03D6D 0 +OP4 E03D6E 0 +OP4 E03D6F 0 +OP4 E03D70 0 +OP4 E03D71 0 +OP4 E03D72 0 +OP4 E03D73 0 +OP4 E03D74 0 +OP4 E03D75 0 +OP4 E03D76 0 +OP4 E03D77 0 +OP4 E03D78 0 +OP4 E03D79 0 +OP4 E03D7A 0 +OP4 E03D7B 0 +OP4 E03D7C 0 +OP4 E03D7D 0 +OP4 E03D7E 0 +OP4 E03D7F 0 +OP4 E03D80 0 +OP4 E03D81 0 +OP4 E03D82 0 +OP4 E03D83 0 +OP4 E03D84 0 +OP4 E03D85 0 +OP4 E03D86 0 +OP4 E03D87 0 +OP4 E03D88 0 +OP4 E03D89 0 +OP4 E03D8A 0 +OP4 E03D8B 0 +OP4 E03D8C 0 +OP4 E03D8D 0 +OP4 E03D8E 0 +OP4 E03D8F 0 +OP4 E03D90 0 +OP4 E03D91 0 +OP4 E03D92 0 +OP4 E03D93 0 +OP4 E03D94 0 +OP4 E03D95 0 +OP4 E03D96 0 +OP4 E03D97 0 +OP4 E03D98 0 +OP4 E03D99 0 +OP4 E03D9A 0 +OP4 E03D9B 0 +OP4 E03D9C 0 +OP4 E03D9D 0 +OP4 E03D9E 0 +OP4 E03D9F 0 +OP4 E03DA0 0 +OP4 E03DA1 0 +OP4 E03DA2 0 +OP4 E03DA3 0 +OP4 E03DA4 0 +OP4 E03DA5 0 +OP4 E03DA6 0 +OP4 E03DA7 0 +OP4 E03DA8 0 +OP4 E03DA9 0 +OP4 E03DAA 0 +OP4 E03DAB 0 +OP4 E03DAC 0 +OP4 E03DAD 0 +OP4 E03DAE 0 +OP4 E03DAF 0 +OP4 E03DB0 0 +OP4 E03DB1 0 +OP4 E03DB2 0 +OP4 E03DB3 0 +OP4 E03DB4 0 +OP4 E03DB5 0 +OP4 E03DB6 0 +OP4 E03DB7 0 +OP4 E03DB8 0 +OP4 E03DB9 0 +OP4 E03DBA 0 +OP4 E03DBB 0 +OP4 E03DBC 0 +OP4 E03DBD 0 +OP4 E03DBE 0 +OP4 E03DBF 0 +OP4 E03DC0 0 +OP4 E03DC1 0 +OP4 E03DC2 0 +OP4 E03DC3 0 +OP4 E03DC4 0 diff --git a/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum4_itrace_irisc5.cfg.ext b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum4_itrace_irisc5.cfg.ext new file mode 100644 index 000000000000..c966914c6de0 --- /dev/null +++ b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum4_itrace_irisc5.cfg.ext @@ -0,0 +1,15814 @@ +OP1 Spectrum4 +OP4 ITRACE0 0 +OP4 ITRACE1 0 +OP4 ITRACE2 0 +OP4 ITRACE3 0 +OP4 ITRACE4 0 +OP4 ITRACE5 1 +OP4 ITRACE6 0 +OP4 ITRACE7 0 +OP4 ITRACE8 0 +OP4 ITRACE9 0 +OP4 Main_PhyUC 0 +OP4 TILE0_ITRACE0 0 +OP4 TILE0_ITRACE1 0 +OP4 TILE0_ITRACE2 0 +OP4 TILE0_ITRACE3 0 +OP4 TILE0_ITRACE4 0 +OP4 TILE0_PhyUC 0 +OP4 TILE1_ITRACE0 0 +OP4 TILE1_ITRACE1 0 +OP4 TILE1_ITRACE2 0 +OP4 TILE1_ITRACE3 0 +OP4 TILE1_ITRACE4 0 +OP4 TILE1_PhyUC 0 +OP4 TILE2_ITRACE0 0 +OP4 TILE2_ITRACE1 0 +OP4 TILE2_ITRACE2 0 +OP4 TILE2_ITRACE3 0 +OP4 TILE2_ITRACE4 0 +OP4 TILE2_PhyUC 0 +OP4 TILE3_ITRACE0 0 +OP4 TILE3_ITRACE1 0 +OP4 TILE3_ITRACE2 0 +OP4 TILE3_ITRACE3 0 +OP4 TILE3_ITRACE4 0 +OP4 TILE3_PhyUC 0 +OP4 TILE4_ITRACE0 0 +OP4 TILE4_ITRACE1 0 +OP4 TILE4_ITRACE2 0 +OP4 TILE4_ITRACE3 0 +OP4 TILE4_ITRACE4 0 +OP4 TILE4_PhyUC 0 +OP4 TILE5_ITRACE0 0 +OP4 TILE5_ITRACE1 0 +OP4 TILE5_ITRACE2 0 +OP4 TILE5_ITRACE3 0 +OP4 TILE5_ITRACE4 0 +OP4 TILE5_PhyUC 0 +OP4 TILE6_ITRACE0 0 +OP4 TILE6_ITRACE1 0 +OP4 TILE6_ITRACE2 0 +OP4 TILE6_ITRACE3 0 +OP4 TILE6_ITRACE4 0 +OP4 TILE6_PhyUC 0 +OP4 TILE7_ITRACE0 0 +OP4 TILE7_ITRACE1 0 +OP4 TILE7_ITRACE2 0 +OP4 TILE7_ITRACE3 0 +OP4 TILE7_ITRACE4 0 +OP4 TILE7_PhyUC 0 +OP4 E0003B 0 +OP4 E0003C 0 +OP4 E0003D 0 +OP4 E0003E 0 +OP4 E0003F 0 +OP4 E00040 0 +OP4 E00041 0 +OP4 E00042 0 +OP4 E00043 0 +OP4 E00044 0 +OP4 E00045 0 +OP4 E00046 0 +OP4 E00047 0 +OP4 E00048 0 +OP4 E00049 0 +OP4 E0004A 0 +OP4 E0004B 0 +OP4 E0004C 0 +OP4 E0004D 0 +OP4 E0004E 0 +OP4 E0004F 0 +OP4 E00050 0 +OP4 E00051 0 +OP4 E00052 0 +OP4 E00053 0 +OP4 E00054 0 +OP4 E00055 0 +OP4 E00056 0 +OP4 E00057 0 +OP4 E00058 0 +OP4 E00059 0 +OP4 E0005A 0 +OP4 E0005B 0 +OP4 E0005C 0 +OP4 E0005D 0 +OP4 E0005E 0 +OP4 E0005F 0 +OP4 E00060 0 +OP4 E00061 0 +OP4 E00062 0 +OP4 E00063 0 +OP4 E00064 0 +OP4 E00065 0 +OP4 E00066 0 +OP4 E00067 0 +OP4 E00068 0 +OP4 E00069 0 +OP4 E0006A 0 +OP4 E0006B 0 +OP4 E0006C 0 +OP4 E0006D 0 +OP4 E0006E 0 +OP4 E0006F 0 +OP4 E00070 0 +OP4 E00071 0 +OP4 E00072 0 +OP4 E00073 0 +OP4 E00074 0 +OP4 E00075 0 +OP4 E00076 0 +OP4 E00077 0 +OP4 E00078 0 +OP4 E00079 0 +OP4 E0007A 0 +OP4 E0007B 0 +OP4 E0007C 0 +OP4 E0007D 0 +OP4 E0007E 0 +OP4 E0007F 0 +OP4 E00080 0 +OP4 E00081 0 +OP4 E00082 0 +OP4 E00083 0 +OP4 E00084 0 +OP4 E00085 0 +OP4 E00086 0 +OP4 E00087 0 +OP4 E00088 0 +OP4 E00089 0 +OP4 E0008A 0 +OP4 E0008B 0 +OP4 E0008C 0 +OP4 E0008D 0 +OP4 E0008E 0 +OP4 E0008F 0 +OP4 E00090 0 +OP4 E00091 0 +OP4 E00092 0 +OP4 E00093 0 +OP4 E00094 0 +OP4 E00095 0 +OP4 E00096 0 +OP4 E00097 0 +OP4 E00098 0 +OP4 E00099 0 +OP4 E0009A 0 +OP4 E0009B 0 +OP4 E0009C 0 +OP4 E0009D 0 +OP4 E0009E 0 +OP4 E0009F 0 +OP4 E000A0 0 +OP4 E000A1 0 +OP4 E000A2 0 +OP4 E000A3 0 +OP4 E000A4 0 +OP4 E000A5 0 +OP4 E000A6 0 +OP4 E000A7 0 +OP4 E000A8 0 +OP4 E000A9 0 +OP4 E000AA 0 +OP4 E000AB 0 +OP4 E000AC 0 +OP4 E000AD 0 +OP4 E000AE 0 +OP4 E000AF 0 +OP4 E000B0 0 +OP4 E000B1 0 +OP4 E000B2 0 +OP4 E000B3 0 +OP4 E000B4 0 +OP4 E000B5 0 +OP4 E000B6 0 +OP4 E000B7 0 +OP4 E000B8 0 +OP4 E000B9 0 +OP4 E000BA 0 +OP4 E000BB 0 +OP4 E000BC 0 +OP4 E000BD 0 +OP4 E000BE 0 +OP4 E000BF 0 +OP4 E000C0 0 +OP4 E000C1 0 +OP4 E000C2 0 +OP4 E000C3 0 +OP4 E000C4 0 +OP4 E000C5 0 +OP4 E000C6 0 +OP4 E000C7 0 +OP4 E000C8 0 +OP4 E000C9 0 +OP4 E000CA 0 +OP4 E000CB 0 +OP4 E000CC 0 +OP4 E000CD 0 +OP4 E000CE 0 +OP4 E000CF 0 +OP4 E000D0 0 +OP4 E000D1 0 +OP4 E000D2 0 +OP4 E000D3 0 +OP4 E000D4 0 +OP4 E000D5 0 +OP4 E000D6 0 +OP4 E000D7 0 +OP4 E000D8 0 +OP4 E000D9 0 +OP4 E000DA 0 +OP4 E000DB 0 +OP4 E000DC 0 +OP4 E000DD 0 +OP4 E000DE 0 +OP4 E000DF 0 +OP4 E000E0 0 +OP4 E000E1 0 +OP4 E000E2 0 +OP4 E000E3 0 +OP4 E000E4 0 +OP4 E000E5 0 +OP4 E000E6 0 +OP4 E000E7 0 +OP4 E000E8 0 +OP4 E000E9 0 +OP4 E000EA 0 +OP4 E000EB 0 +OP4 E000EC 0 +OP4 E000ED 0 +OP4 E000EE 0 +OP4 E000EF 0 +OP4 E000F0 0 +OP4 E000F1 0 +OP4 E000F2 0 +OP4 E000F3 0 +OP4 E000F4 0 +OP4 E000F5 0 +OP4 E000F6 0 +OP4 E000F7 0 +OP4 E000F8 0 +OP4 E000F9 0 +OP4 E000FA 0 +OP4 E000FB 0 +OP4 E000FC 0 +OP4 E000FD 0 +OP4 E000FE 0 +OP4 E000FF 0 +OP4 E00100 0 +OP4 E00101 0 +OP4 E00102 0 +OP4 E00103 0 +OP4 E00104 0 +OP4 E00105 0 +OP4 E00106 0 +OP4 E00107 0 +OP4 E00108 0 +OP4 E00109 0 +OP4 E0010A 0 +OP4 E0010B 0 +OP4 E0010C 0 +OP4 E0010D 0 +OP4 E0010E 0 +OP4 E0010F 0 +OP4 E00110 0 +OP4 E00111 0 +OP4 E00112 0 +OP4 E00113 0 +OP4 E00114 0 +OP4 E00115 0 +OP4 E00116 0 +OP4 E00117 0 +OP4 E00118 0 +OP4 E00119 0 +OP4 E0011A 0 +OP4 E0011B 0 +OP4 E0011C 0 +OP4 E0011D 0 +OP4 E0011E 0 +OP4 E0011F 0 +OP4 E00120 0 +OP4 E00121 0 +OP4 E00122 0 +OP4 E00123 0 +OP4 E00124 0 +OP4 E00125 0 +OP4 E00126 0 +OP4 E00127 0 +OP4 E00128 0 +OP4 E00129 0 +OP4 E0012A 0 +OP4 E0012B 0 +OP4 E0012C 0 +OP4 E0012D 0 +OP4 E0012E 0 +OP4 E0012F 0 +OP4 E00130 0 +OP4 E00131 0 +OP4 E00132 0 +OP4 E00133 0 +OP4 E00134 0 +OP4 E00135 0 +OP4 E00136 0 +OP4 E00137 0 +OP4 E00138 0 +OP4 E00139 0 +OP4 E0013A 0 +OP4 E0013B 0 +OP4 E0013C 0 +OP4 E0013D 0 +OP4 E0013E 0 +OP4 E0013F 0 +OP4 E00140 0 +OP4 E00141 0 +OP4 E00142 0 +OP4 E00143 0 +OP4 E00144 0 +OP4 E00145 0 +OP4 E00146 0 +OP4 E00147 0 +OP4 E00148 0 +OP4 E00149 0 +OP4 E0014A 0 +OP4 E0014B 0 +OP4 E0014C 0 +OP4 E0014D 0 +OP4 E0014E 0 +OP4 E0014F 0 +OP4 E00150 0 +OP4 E00151 0 +OP4 E00152 0 +OP4 E00153 0 +OP4 E00154 0 +OP4 E00155 0 +OP4 E00156 0 +OP4 E00157 0 +OP4 E00158 0 +OP4 E00159 0 +OP4 E0015A 0 +OP4 E0015B 0 +OP4 E0015C 0 +OP4 E0015D 0 +OP4 E0015E 0 +OP4 E0015F 0 +OP4 E00160 0 +OP4 E00161 0 +OP4 E00162 0 +OP4 E00163 0 +OP4 E00164 0 +OP4 E00165 0 +OP4 E00166 0 +OP4 E00167 0 +OP4 E00168 0 +OP4 E00169 0 +OP4 E0016A 0 +OP4 E0016B 0 +OP4 E0016C 0 +OP4 E0016D 0 +OP4 E0016E 0 +OP4 E0016F 0 +OP4 E00170 0 +OP4 E00171 0 +OP4 E00172 0 +OP4 E00173 0 +OP4 E00174 0 +OP4 E00175 0 +OP4 E00176 0 +OP4 E00177 0 +OP4 E00178 0 +OP4 E00179 0 +OP4 E0017A 0 +OP4 E0017B 0 +OP4 E0017C 0 +OP4 E0017D 0 +OP4 E0017E 0 +OP4 E0017F 0 +OP4 E00180 0 +OP4 E00181 0 +OP4 E00182 0 +OP4 E00183 0 +OP4 E00184 0 +OP4 E00185 0 +OP4 E00186 0 +OP4 E00187 0 +OP4 E00188 0 +OP4 E00189 0 +OP4 E0018A 0 +OP4 E0018B 0 +OP4 E0018C 0 +OP4 E0018D 0 +OP4 E0018E 0 +OP4 E0018F 0 +OP4 E00190 0 +OP4 E00191 0 +OP4 E00192 0 +OP4 E00193 0 +OP4 E00194 0 +OP4 E00195 0 +OP4 E00196 0 +OP4 E00197 0 +OP4 E00198 0 +OP4 E00199 0 +OP4 E0019A 0 +OP4 E0019B 0 +OP4 E0019C 0 +OP4 E0019D 0 +OP4 E0019E 0 +OP4 E0019F 0 +OP4 E001A0 0 +OP4 E001A1 0 +OP4 E001A2 0 +OP4 E001A3 0 +OP4 E001A4 0 +OP4 E001A5 0 +OP4 E001A6 0 +OP4 E001A7 0 +OP4 E001A8 0 +OP4 E001A9 0 +OP4 E001AA 0 +OP4 E001AB 0 +OP4 E001AC 0 +OP4 E001AD 0 +OP4 E001AE 0 +OP4 E001AF 0 +OP4 E001B0 0 +OP4 E001B1 0 +OP4 E001B2 0 +OP4 E001B3 0 +OP4 E001B4 0 +OP4 E001B5 0 +OP4 E001B6 0 +OP4 E001B7 0 +OP4 E001B8 0 +OP4 E001B9 0 +OP4 E001BA 0 +OP4 E001BB 0 +OP4 E001BC 0 +OP4 E001BD 0 +OP4 E001BE 0 +OP4 E001BF 0 +OP4 E001C0 0 +OP4 E001C1 0 +OP4 E001C2 0 +OP4 E001C3 0 +OP4 E001C4 0 +OP4 E001C5 0 +OP4 E001C6 0 +OP4 E001C7 0 +OP4 E001C8 0 +OP4 E001C9 0 +OP4 E001CA 0 +OP4 E001CB 0 +OP4 E001CC 0 +OP4 E001CD 0 +OP4 E001CE 0 +OP4 E001CF 0 +OP4 E001D0 0 +OP4 E001D1 0 +OP4 E001D2 0 +OP4 E001D3 0 +OP4 E001D4 0 +OP4 E001D5 0 +OP4 E001D6 0 +OP4 E001D7 0 +OP4 E001D8 0 +OP4 E001D9 0 +OP4 E001DA 0 +OP4 E001DB 0 +OP4 E001DC 0 +OP4 E001DD 0 +OP4 E001DE 0 +OP4 E001DF 0 +OP4 E001E0 0 +OP4 E001E1 0 +OP4 E001E2 0 +OP4 E001E3 0 +OP4 E001E4 0 +OP4 E001E5 0 +OP4 E001E6 0 +OP4 E001E7 0 +OP4 E001E8 0 +OP4 E001E9 0 +OP4 E001EA 0 +OP4 E001EB 0 +OP4 E001EC 0 +OP4 E001ED 0 +OP4 E001EE 0 +OP4 E001EF 0 +OP4 E001F0 0 +OP4 E001F1 0 +OP4 E001F2 0 +OP4 E001F3 0 +OP4 E001F4 0 +OP4 E001F5 0 +OP4 E001F6 0 +OP4 E001F7 0 +OP4 E001F8 0 +OP4 E001F9 0 +OP4 E001FA 0 +OP4 E001FB 0 +OP4 E001FC 0 +OP4 E001FD 0 +OP4 E001FE 0 +OP4 E001FF 0 +OP4 E00200 0 +OP4 E00201 0 +OP4 E00202 0 +OP4 E00203 0 +OP4 E00204 0 +OP4 E00205 0 +OP4 E00206 0 +OP4 E00207 0 +OP4 E00208 0 +OP4 E00209 0 +OP4 E0020A 0 +OP4 E0020B 0 +OP4 E0020C 0 +OP4 E0020D 0 +OP4 E0020E 0 +OP4 E0020F 0 +OP4 E00210 0 +OP4 E00211 0 +OP4 E00212 0 +OP4 E00213 0 +OP4 E00214 0 +OP4 E00215 0 +OP4 E00216 0 +OP4 E00217 0 +OP4 E00218 0 +OP4 E00219 0 +OP4 E0021A 0 +OP4 E0021B 0 +OP4 E0021C 0 +OP4 E0021D 0 +OP4 E0021E 0 +OP4 E0021F 0 +OP4 E00220 0 +OP4 E00221 0 +OP4 E00222 0 +OP4 E00223 0 +OP4 E00224 0 +OP4 E00225 0 +OP4 E00226 0 +OP4 E00227 0 +OP4 E00228 0 +OP4 E00229 0 +OP4 E0022A 0 +OP4 E0022B 0 +OP4 E0022C 0 +OP4 E0022D 0 +OP4 E0022E 0 +OP4 E0022F 0 +OP4 E00230 0 +OP4 E00231 0 +OP4 E00232 0 +OP4 E00233 0 +OP4 E00234 0 +OP4 E00235 0 +OP4 E00236 0 +OP4 E00237 0 +OP4 E00238 0 +OP4 E00239 0 +OP4 E0023A 0 +OP4 E0023B 0 +OP4 E0023C 0 +OP4 E0023D 0 +OP4 E0023E 0 +OP4 E0023F 0 +OP4 E00240 0 +OP4 E00241 0 +OP4 E00242 0 +OP4 E00243 0 +OP4 E00244 0 +OP4 E00245 0 +OP4 E00246 0 +OP4 E00247 0 +OP4 E00248 0 +OP4 E00249 0 +OP4 E0024A 0 +OP4 E0024B 0 +OP4 E0024C 0 +OP4 E0024D 0 +OP4 E0024E 0 +OP4 E0024F 0 +OP4 E00250 0 +OP4 E00251 0 +OP4 E00252 0 +OP4 E00253 0 +OP4 E00254 0 +OP4 E00255 0 +OP4 E00256 0 +OP4 E00257 0 +OP4 E00258 0 +OP4 E00259 0 +OP4 E0025A 0 +OP4 E0025B 0 +OP4 E0025C 0 +OP4 E0025D 0 +OP4 E0025E 0 +OP4 E0025F 0 +OP4 E00260 0 +OP4 E00261 0 +OP4 E00262 0 +OP4 E00263 0 +OP4 E00264 0 +OP4 E00265 0 +OP4 E00266 0 +OP4 E00267 0 +OP4 E00268 0 +OP4 E00269 0 +OP4 E0026A 0 +OP4 E0026B 0 +OP4 E0026C 0 +OP4 E0026D 0 +OP4 E0026E 0 +OP4 E0026F 0 +OP4 E00270 0 +OP4 E00271 0 +OP4 E00272 0 +OP4 E00273 0 +OP4 E00274 0 +OP4 E00275 0 +OP4 E00276 0 +OP4 E00277 0 +OP4 E00278 0 +OP4 E00279 0 +OP4 E0027A 0 +OP4 E0027B 0 +OP4 E0027C 0 +OP4 E0027D 0 +OP4 E0027E 0 +OP4 E0027F 0 +OP4 E00280 0 +OP4 E00281 0 +OP4 E00282 0 +OP4 E00283 0 +OP4 E00284 0 +OP4 E00285 0 +OP4 E00286 0 +OP4 E00287 0 +OP4 E00288 0 +OP4 E00289 0 +OP4 E0028A 0 +OP4 E0028B 0 +OP4 E0028C 0 +OP4 E0028D 0 +OP4 E0028E 0 +OP4 E0028F 0 +OP4 E00290 0 +OP4 E00291 0 +OP4 E00292 0 +OP4 E00293 0 +OP4 E00294 0 +OP4 E00295 0 +OP4 E00296 0 +OP4 E00297 0 +OP4 E00298 0 +OP4 E00299 0 +OP4 E0029A 0 +OP4 E0029B 0 +OP4 E0029C 0 +OP4 E0029D 0 +OP4 E0029E 0 +OP4 E0029F 0 +OP4 E002A0 0 +OP4 E002A1 0 +OP4 E002A2 0 +OP4 E002A3 0 +OP4 E002A4 0 +OP4 E002A5 0 +OP4 E002A6 0 +OP4 E002A7 0 +OP4 E002A8 0 +OP4 E002A9 0 +OP4 E002AA 0 +OP4 E002AB 0 +OP4 E002AC 0 +OP4 E002AD 0 +OP4 E002AE 0 +OP4 E002AF 0 +OP4 E002B0 0 +OP4 E002B1 0 +OP4 E002B2 0 +OP4 E002B3 0 +OP4 E002B4 0 +OP4 E002B5 0 +OP4 E002B6 0 +OP4 E002B7 0 +OP4 E002B8 0 +OP4 E002B9 0 +OP4 E002BA 0 +OP4 E002BB 0 +OP4 E002BC 0 +OP4 E002BD 0 +OP4 E002BE 0 +OP4 E002BF 0 +OP4 E002C0 0 +OP4 E002C1 0 +OP4 E002C2 0 +OP4 E002C3 0 +OP4 E002C4 0 +OP4 E002C5 0 +OP4 E002C6 0 +OP4 E002C7 0 +OP4 E002C8 0 +OP4 E002C9 0 +OP4 E002CA 0 +OP4 E002CB 0 +OP4 E002CC 0 +OP4 E002CD 0 +OP4 E002CE 0 +OP4 E002CF 0 +OP4 E002D0 0 +OP4 E002D1 0 +OP4 E002D2 0 +OP4 E002D3 0 +OP4 E002D4 0 +OP4 E002D5 0 +OP4 E002D6 0 +OP4 E002D7 0 +OP4 E002D8 0 +OP4 E002D9 0 +OP4 E002DA 0 +OP4 E002DB 0 +OP4 E002DC 0 +OP4 E002DD 0 +OP4 E002DE 0 +OP4 E002DF 0 +OP4 E002E0 0 +OP4 E002E1 0 +OP4 E002E2 0 +OP4 E002E3 0 +OP4 E002E4 0 +OP4 E002E5 0 +OP4 E002E6 0 +OP4 E002E7 0 +OP4 E002E8 0 +OP4 E002E9 0 +OP4 E002EA 0 +OP4 E002EB 0 +OP4 E002EC 0 +OP4 E002ED 0 +OP4 E002EE 0 +OP4 E002EF 0 +OP4 E002F0 0 +OP4 E002F1 0 +OP4 E002F2 0 +OP4 E002F3 0 +OP4 E002F4 0 +OP4 E002F5 0 +OP4 E002F6 0 +OP4 E002F7 0 +OP4 E002F8 0 +OP4 E002F9 0 +OP4 E002FA 0 +OP4 E002FB 0 +OP4 E002FC 0 +OP4 E002FD 0 +OP4 E002FE 0 +OP4 E002FF 0 +OP4 E00300 0 +OP4 E00301 0 +OP4 E00302 0 +OP4 E00303 0 +OP4 E00304 0 +OP4 E00305 0 +OP4 E00306 0 +OP4 E00307 0 +OP4 E00308 0 +OP4 E00309 0 +OP4 E0030A 0 +OP4 E0030B 0 +OP4 E0030C 0 +OP4 E0030D 0 +OP4 E0030E 0 +OP4 E0030F 0 +OP4 E00310 0 +OP4 E00311 0 +OP4 E00312 0 +OP4 E00313 0 +OP4 E00314 0 +OP4 E00315 0 +OP4 E00316 0 +OP4 E00317 0 +OP4 E00318 0 +OP4 E00319 0 +OP4 E0031A 0 +OP4 E0031B 0 +OP4 E0031C 0 +OP4 E0031D 0 +OP4 E0031E 0 +OP4 E0031F 0 +OP4 E00320 0 +OP4 E00321 0 +OP4 E00322 0 +OP4 E00323 0 +OP4 E00324 0 +OP4 E00325 0 +OP4 E00326 0 +OP4 E00327 0 +OP4 E00328 0 +OP4 E00329 0 +OP4 E0032A 0 +OP4 E0032B 0 +OP4 E0032C 0 +OP4 E0032D 0 +OP4 E0032E 0 +OP4 E0032F 0 +OP4 E00330 0 +OP4 E00331 0 +OP4 E00332 0 +OP4 E00333 0 +OP4 E00334 0 +OP4 E00335 0 +OP4 E00336 0 +OP4 E00337 0 +OP4 E00338 0 +OP4 E00339 0 +OP4 E0033A 0 +OP4 E0033B 0 +OP4 E0033C 0 +OP4 E0033D 0 +OP4 E0033E 0 +OP4 E0033F 0 +OP4 E00340 0 +OP4 E00341 0 +OP4 E00342 0 +OP4 E00343 0 +OP4 E00344 0 +OP4 E00345 0 +OP4 E00346 0 +OP4 E00347 0 +OP4 E00348 0 +OP4 E00349 0 +OP4 E0034A 0 +OP4 E0034B 0 +OP4 E0034C 0 +OP4 E0034D 0 +OP4 E0034E 0 +OP4 E0034F 0 +OP4 E00350 0 +OP4 E00351 0 +OP4 E00352 0 +OP4 E00353 0 +OP4 E00354 0 +OP4 E00355 0 +OP4 E00356 0 +OP4 E00357 0 +OP4 E00358 0 +OP4 E00359 0 +OP4 E0035A 0 +OP4 E0035B 0 +OP4 E0035C 0 +OP4 E0035D 0 +OP4 E0035E 0 +OP4 E0035F 0 +OP4 E00360 0 +OP4 E00361 0 +OP4 E00362 0 +OP4 E00363 0 +OP4 E00364 0 +OP4 E00365 0 +OP4 E00366 0 +OP4 E00367 0 +OP4 E00368 0 +OP4 E00369 0 +OP4 E0036A 0 +OP4 E0036B 0 +OP4 E0036C 0 +OP4 E0036D 0 +OP4 E0036E 0 +OP4 E0036F 0 +OP4 E00370 0 +OP4 E00371 0 +OP4 E00372 0 +OP4 E00373 0 +OP4 E00374 0 +OP4 E00375 0 +OP4 E00376 0 +OP4 E00377 0 +OP4 E00378 0 +OP4 E00379 0 +OP4 E0037A 0 +OP4 E0037B 0 +OP4 E0037C 0 +OP4 E0037D 0 +OP4 E0037E 0 +OP4 E0037F 0 +OP4 E00380 0 +OP4 E00381 0 +OP4 E00382 0 +OP4 E00383 0 +OP4 E00384 0 +OP4 E00385 0 +OP4 E00386 0 +OP4 E00387 0 +OP4 E00388 0 +OP4 E00389 0 +OP4 E0038A 0 +OP4 E0038B 0 +OP4 E0038C 0 +OP4 E0038D 0 +OP4 E0038E 0 +OP4 E0038F 0 +OP4 E00390 0 +OP4 E00391 0 +OP4 E00392 0 +OP4 E00393 0 +OP4 E00394 0 +OP4 E00395 0 +OP4 E00396 0 +OP4 E00397 0 +OP4 E00398 0 +OP4 E00399 0 +OP4 E0039A 0 +OP4 E0039B 0 +OP4 E0039C 0 +OP4 E0039D 0 +OP4 E0039E 0 +OP4 E0039F 0 +OP4 E003A0 0 +OP4 E003A1 0 +OP4 E003A2 0 +OP4 E003A3 0 +OP4 E003A4 0 +OP4 E003A5 0 +OP4 E003A6 0 +OP4 E003A7 0 +OP4 E003A8 0 +OP4 E003A9 0 +OP4 E003AA 0 +OP4 E003AB 0 +OP4 E003AC 0 +OP4 E003AD 0 +OP4 E003AE 0 +OP4 E003AF 0 +OP4 E003B0 0 +OP4 E003B1 0 +OP4 E003B2 0 +OP4 E003B3 0 +OP4 E003B4 0 +OP4 E003B5 0 +OP4 E003B6 0 +OP4 E003B7 0 +OP4 E003B8 0 +OP4 E003B9 0 +OP4 E003BA 0 +OP4 E003BB 0 +OP4 E003BC 0 +OP4 E003BD 0 +OP4 E003BE 0 +OP4 E003BF 0 +OP4 E003C0 0 +OP4 E003C1 0 +OP4 E003C2 0 +OP4 E003C3 0 +OP4 E003C4 0 +OP4 E003C5 0 +OP4 E003C6 0 +OP4 E003C7 0 +OP4 E003C8 0 +OP4 E003C9 0 +OP4 E003CA 0 +OP4 E003CB 0 +OP4 E003CC 0 +OP4 E003CD 0 +OP4 E003CE 0 +OP4 E003CF 0 +OP4 E003D0 0 +OP4 E003D1 0 +OP4 E003D2 0 +OP4 E003D3 0 +OP4 E003D4 0 +OP4 E003D5 0 +OP4 E003D6 0 +OP4 E003D7 0 +OP4 E003D8 0 +OP4 E003D9 0 +OP4 E003DA 0 +OP4 E003DB 0 +OP4 E003DC 0 +OP4 E003DD 0 +OP4 E003DE 0 +OP4 E003DF 0 +OP4 E003E0 0 +OP4 E003E1 0 +OP4 E003E2 0 +OP4 E003E3 0 +OP4 E003E4 0 +OP4 E003E5 0 +OP4 E003E6 0 +OP4 E003E7 0 +OP4 E003E8 0 +OP4 E003E9 0 +OP4 E003EA 0 +OP4 E003EB 0 +OP4 E003EC 0 +OP4 E003ED 0 +OP4 E003EE 0 +OP4 E003EF 0 +OP4 E003F0 0 +OP4 E003F1 0 +OP4 E003F2 0 +OP4 E003F3 0 +OP4 E003F4 0 +OP4 E003F5 0 +OP4 E003F6 0 +OP4 E003F7 0 +OP4 E003F8 0 +OP4 E003F9 0 +OP4 E003FA 0 +OP4 E003FB 0 +OP4 E003FC 0 +OP4 E003FD 0 +OP4 E003FE 0 +OP4 E003FF 0 +OP4 E00400 0 +OP4 E00401 0 +OP4 E00402 0 +OP4 E00403 0 +OP4 E00404 0 +OP4 E00405 0 +OP4 E00406 0 +OP4 E00407 0 +OP4 E00408 0 +OP4 E00409 0 +OP4 E0040A 0 +OP4 E0040B 0 +OP4 E0040C 0 +OP4 E0040D 0 +OP4 E0040E 0 +OP4 E0040F 0 +OP4 E00410 0 +OP4 E00411 0 +OP4 E00412 0 +OP4 E00413 0 +OP4 E00414 0 +OP4 E00415 0 +OP4 E00416 0 +OP4 E00417 0 +OP4 E00418 0 +OP4 E00419 0 +OP4 E0041A 0 +OP4 E0041B 0 +OP4 E0041C 0 +OP4 E0041D 0 +OP4 E0041E 0 +OP4 E0041F 0 +OP4 E00420 0 +OP4 E00421 0 +OP4 E00422 0 +OP4 E00423 0 +OP4 E00424 0 +OP4 E00425 0 +OP4 E00426 0 +OP4 E00427 0 +OP4 E00428 0 +OP4 E00429 0 +OP4 E0042A 0 +OP4 E0042B 0 +OP4 E0042C 0 +OP4 E0042D 0 +OP4 E0042E 0 +OP4 E0042F 0 +OP4 E00430 0 +OP4 E00431 0 +OP4 E00432 0 +OP4 E00433 0 +OP4 E00434 0 +OP4 E00435 0 +OP4 E00436 0 +OP4 E00437 0 +OP4 E00438 0 +OP4 E00439 0 +OP4 E0043A 0 +OP4 E0043B 0 +OP4 E0043C 0 +OP4 E0043D 0 +OP4 E0043E 0 +OP4 E0043F 0 +OP4 E00440 0 +OP4 E00441 0 +OP4 E00442 0 +OP4 E00443 0 +OP4 E00444 0 +OP4 E00445 0 +OP4 E00446 0 +OP4 E00447 0 +OP4 E00448 0 +OP4 E00449 0 +OP4 E0044A 0 +OP4 E0044B 0 +OP4 E0044C 0 +OP4 E0044D 0 +OP4 E0044E 0 +OP4 E0044F 0 +OP4 E00450 0 +OP4 E00451 0 +OP4 E00452 0 +OP4 E00453 0 +OP4 E00454 0 +OP4 E00455 0 +OP4 E00456 0 +OP4 E00457 0 +OP4 E00458 0 +OP4 E00459 0 +OP4 E0045A 0 +OP4 E0045B 0 +OP4 E0045C 0 +OP4 E0045D 0 +OP4 E0045E 0 +OP4 E0045F 0 +OP4 E00460 0 +OP4 E00461 0 +OP4 E00462 0 +OP4 E00463 0 +OP4 E00464 0 +OP4 E00465 0 +OP4 E00466 0 +OP4 E00467 0 +OP4 E00468 0 +OP4 E00469 0 +OP4 E0046A 0 +OP4 E0046B 0 +OP4 E0046C 0 +OP4 E0046D 0 +OP4 E0046E 0 +OP4 E0046F 0 +OP4 E00470 0 +OP4 E00471 0 +OP4 E00472 0 +OP4 E00473 0 +OP4 E00474 0 +OP4 E00475 0 +OP4 E00476 0 +OP4 E00477 0 +OP4 E00478 0 +OP4 E00479 0 +OP4 E0047A 0 +OP4 E0047B 0 +OP4 E0047C 0 +OP4 E0047D 0 +OP4 E0047E 0 +OP4 E0047F 0 +OP4 E00480 0 +OP4 E00481 0 +OP4 E00482 0 +OP4 E00483 0 +OP4 E00484 0 +OP4 E00485 0 +OP4 E00486 0 +OP4 E00487 0 +OP4 E00488 0 +OP4 E00489 0 +OP4 E0048A 0 +OP4 E0048B 0 +OP4 E0048C 0 +OP4 E0048D 0 +OP4 E0048E 0 +OP4 E0048F 0 +OP4 E00490 0 +OP4 E00491 0 +OP4 E00492 0 +OP4 E00493 0 +OP4 E00494 0 +OP4 E00495 0 +OP4 E00496 0 +OP4 E00497 0 +OP4 E00498 0 +OP4 E00499 0 +OP4 E0049A 0 +OP4 E0049B 0 +OP4 E0049C 0 +OP4 E0049D 0 +OP4 E0049E 0 +OP4 E0049F 0 +OP4 E004A0 0 +OP4 E004A1 0 +OP4 E004A2 0 +OP4 E004A3 0 +OP4 E004A4 0 +OP4 E004A5 0 +OP4 E004A6 0 +OP4 E004A7 0 +OP4 E004A8 0 +OP4 E004A9 0 +OP4 E004AA 0 +OP4 E004AB 0 +OP4 E004AC 0 +OP4 E004AD 0 +OP4 E004AE 0 +OP4 E004AF 0 +OP4 E004B0 0 +OP4 E004B1 0 +OP4 E004B2 0 +OP4 E004B3 0 +OP4 E004B4 0 +OP4 E004B5 0 +OP4 E004B6 0 +OP4 E004B7 0 +OP4 E004B8 0 +OP4 E004B9 0 +OP4 E004BA 0 +OP4 E004BB 0 +OP4 E004BC 0 +OP4 E004BD 0 +OP4 E004BE 0 +OP4 E004BF 0 +OP4 E004C0 0 +OP4 E004C1 0 +OP4 E004C2 0 +OP4 E004C3 0 +OP4 E004C4 0 +OP4 E004C5 0 +OP4 E004C6 0 +OP4 E004C7 0 +OP4 E004C8 0 +OP4 E004C9 0 +OP4 E004CA 0 +OP4 E004CB 0 +OP4 E004CC 0 +OP4 E004CD 0 +OP4 E004CE 0 +OP4 E004CF 0 +OP4 E004D0 0 +OP4 E004D1 0 +OP4 E004D2 0 +OP4 E004D3 0 +OP4 E004D4 0 +OP4 E004D5 0 +OP4 E004D6 0 +OP4 E004D7 0 +OP4 E004D8 0 +OP4 E004D9 0 +OP4 E004DA 0 +OP4 E004DB 0 +OP4 E004DC 0 +OP4 E004DD 0 +OP4 E004DE 0 +OP4 E004DF 0 +OP4 E004E0 0 +OP4 E004E1 0 +OP4 E004E2 0 +OP4 E004E3 0 +OP4 E004E4 0 +OP4 E004E5 0 +OP4 E004E6 0 +OP4 E004E7 0 +OP4 E004E8 0 +OP4 E004E9 0 +OP4 E004EA 0 +OP4 E004EB 0 +OP4 E004EC 0 +OP4 E004ED 0 +OP4 E004EE 0 +OP4 E004EF 0 +OP4 E004F0 0 +OP4 E004F1 0 +OP4 E004F2 0 +OP4 E004F3 0 +OP4 E004F4 0 +OP4 E004F5 0 +OP4 E004F6 0 +OP4 E004F7 0 +OP4 E004F8 0 +OP4 E004F9 0 +OP4 E004FA 0 +OP4 E004FB 0 +OP4 E004FC 0 +OP4 E004FD 0 +OP4 E004FE 0 +OP4 E004FF 0 +OP4 E00500 0 +OP4 E00501 0 +OP4 E00502 0 +OP4 E00503 0 +OP4 E00504 0 +OP4 E00505 0 +OP4 E00506 0 +OP4 E00507 0 +OP4 E00508 0 +OP4 E00509 0 +OP4 E0050A 0 +OP4 E0050B 0 +OP4 E0050C 0 +OP4 E0050D 0 +OP4 E0050E 0 +OP4 E0050F 0 +OP4 E00510 0 +OP4 E00511 0 +OP4 E00512 0 +OP4 E00513 0 +OP4 E00514 0 +OP4 E00515 0 +OP4 E00516 0 +OP4 E00517 0 +OP4 E00518 0 +OP4 E00519 0 +OP4 E0051A 0 +OP4 E0051B 0 +OP4 E0051C 0 +OP4 E0051D 0 +OP4 E0051E 0 +OP4 E0051F 0 +OP4 E00520 0 +OP4 E00521 0 +OP4 E00522 0 +OP4 E00523 0 +OP4 E00524 0 +OP4 E00525 0 +OP4 E00526 0 +OP4 E00527 0 +OP4 E00528 0 +OP4 E00529 0 +OP4 E0052A 0 +OP4 E0052B 0 +OP4 E0052C 0 +OP4 E0052D 0 +OP4 E0052E 0 +OP4 E0052F 0 +OP4 E00530 0 +OP4 E00531 0 +OP4 E00532 0 +OP4 E00533 0 +OP4 E00534 0 +OP4 E00535 0 +OP4 E00536 0 +OP4 E00537 0 +OP4 E00538 0 +OP4 E00539 0 +OP4 E0053A 0 +OP4 E0053B 0 +OP4 E0053C 0 +OP4 E0053D 0 +OP4 E0053E 0 +OP4 E0053F 0 +OP4 E00540 0 +OP4 E00541 0 +OP4 E00542 0 +OP4 E00543 0 +OP4 E00544 0 +OP4 E00545 0 +OP4 E00546 0 +OP4 E00547 0 +OP4 E00548 0 +OP4 E00549 0 +OP4 E0054A 0 +OP4 E0054B 0 +OP4 E0054C 0 +OP4 E0054D 0 +OP4 E0054E 0 +OP4 E0054F 0 +OP4 E00550 0 +OP4 E00551 0 +OP4 E00552 0 +OP4 E00553 0 +OP4 E00554 0 +OP4 E00555 0 +OP4 E00556 0 +OP4 E00557 0 +OP4 E00558 0 +OP4 E00559 0 +OP4 E0055A 0 +OP4 E0055B 0 +OP4 E0055C 0 +OP4 E0055D 0 +OP4 E0055E 0 +OP4 E0055F 0 +OP4 E00560 0 +OP4 E00561 0 +OP4 E00562 0 +OP4 E00563 0 +OP4 E00564 0 +OP4 E00565 0 +OP4 E00566 0 +OP4 E00567 0 +OP4 E00568 0 +OP4 E00569 0 +OP4 E0056A 0 +OP4 E0056B 0 +OP4 E0056C 0 +OP4 E0056D 0 +OP4 E0056E 0 +OP4 E0056F 0 +OP4 E00570 0 +OP4 E00571 0 +OP4 E00572 0 +OP4 E00573 0 +OP4 E00574 0 +OP4 E00575 0 +OP4 E00576 0 +OP4 E00577 0 +OP4 E00578 0 +OP4 E00579 0 +OP4 E0057A 0 +OP4 E0057B 0 +OP4 E0057C 0 +OP4 E0057D 0 +OP4 E0057E 0 +OP4 E0057F 0 +OP4 E00580 0 +OP4 E00581 0 +OP4 E00582 0 +OP4 E00583 0 +OP4 E00584 0 +OP4 E00585 0 +OP4 E00586 0 +OP4 E00587 0 +OP4 E00588 0 +OP4 E00589 0 +OP4 E0058A 0 +OP4 E0058B 0 +OP4 E0058C 0 +OP4 E0058D 0 +OP4 E0058E 0 +OP4 E0058F 0 +OP4 E00590 0 +OP4 E00591 0 +OP4 E00592 0 +OP4 E00593 0 +OP4 E00594 0 +OP4 E00595 0 +OP4 E00596 0 +OP4 E00597 0 +OP4 E00598 0 +OP4 E00599 0 +OP4 E0059A 0 +OP4 E0059B 0 +OP4 E0059C 0 +OP4 E0059D 0 +OP4 E0059E 0 +OP4 E0059F 0 +OP4 E005A0 0 +OP4 E005A1 0 +OP4 E005A2 0 +OP4 E005A3 0 +OP4 E005A4 0 +OP4 E005A5 0 +OP4 E005A6 0 +OP4 E005A7 0 +OP4 E005A8 0 +OP4 E005A9 0 +OP4 E005AA 0 +OP4 E005AB 0 +OP4 E005AC 0 +OP4 E005AD 0 +OP4 E005AE 0 +OP4 E005AF 0 +OP4 E005B0 0 +OP4 E005B1 0 +OP4 E005B2 0 +OP4 E005B3 0 +OP4 E005B4 0 +OP4 E005B5 0 +OP4 E005B6 0 +OP4 E005B7 0 +OP4 E005B8 0 +OP4 E005B9 0 +OP4 E005BA 0 +OP4 E005BB 0 +OP4 E005BC 0 +OP4 E005BD 0 +OP4 E005BE 0 +OP4 E005BF 0 +OP4 E005C0 0 +OP4 E005C1 0 +OP4 E005C2 0 +OP4 E005C3 0 +OP4 E005C4 0 +OP4 E005C5 0 +OP4 E005C6 0 +OP4 E005C7 0 +OP4 E005C8 0 +OP4 E005C9 0 +OP4 E005CA 0 +OP4 E005CB 0 +OP4 E005CC 0 +OP4 E005CD 0 +OP4 E005CE 0 +OP4 E005CF 0 +OP4 E005D0 0 +OP4 E005D1 0 +OP4 E005D2 0 +OP4 E005D3 0 +OP4 E005D4 0 +OP4 E005D5 0 +OP4 E005D6 0 +OP4 E005D7 0 +OP4 E005D8 0 +OP4 E005D9 0 +OP4 E005DA 0 +OP4 E005DB 0 +OP4 E005DC 0 +OP4 E005DD 0 +OP4 E005DE 0 +OP4 E005DF 0 +OP4 E005E0 0 +OP4 E005E1 0 +OP4 E005E2 0 +OP4 E005E3 0 +OP4 E005E4 0 +OP4 E005E5 0 +OP4 E005E6 0 +OP4 E005E7 0 +OP4 E005E8 0 +OP4 E005E9 0 +OP4 E005EA 0 +OP4 E005EB 0 +OP4 E005EC 0 +OP4 E005ED 0 +OP4 E005EE 0 +OP4 E005EF 0 +OP4 E005F0 0 +OP4 E005F1 0 +OP4 E005F2 0 +OP4 E005F3 0 +OP4 E005F4 0 +OP4 E005F5 0 +OP4 E005F6 0 +OP4 E005F7 0 +OP4 E005F8 0 +OP4 E005F9 0 +OP4 E005FA 0 +OP4 E005FB 0 +OP4 E005FC 0 +OP4 E005FD 0 +OP4 E005FE 0 +OP4 E005FF 0 +OP4 E00600 0 +OP4 E00601 0 +OP4 E00602 0 +OP4 E00603 0 +OP4 E00604 0 +OP4 E00605 0 +OP4 E00606 0 +OP4 E00607 0 +OP4 E00608 0 +OP4 E00609 0 +OP4 E0060A 0 +OP4 E0060B 0 +OP4 E0060C 0 +OP4 E0060D 0 +OP4 E0060E 0 +OP4 E0060F 0 +OP4 E00610 0 +OP4 E00611 0 +OP4 E00612 0 +OP4 E00613 0 +OP4 E00614 0 +OP4 E00615 0 +OP4 E00616 0 +OP4 E00617 0 +OP4 E00618 0 +OP4 E00619 0 +OP4 E0061A 0 +OP4 E0061B 0 +OP4 E0061C 0 +OP4 E0061D 0 +OP4 E0061E 0 +OP4 E0061F 0 +OP4 E00620 0 +OP4 E00621 0 +OP4 E00622 0 +OP4 E00623 0 +OP4 E00624 0 +OP4 E00625 0 +OP4 E00626 0 +OP4 E00627 0 +OP4 E00628 0 +OP4 E00629 0 +OP4 E0062A 0 +OP4 E0062B 0 +OP4 E0062C 0 +OP4 E0062D 0 +OP4 E0062E 0 +OP4 E0062F 0 +OP4 E00630 0 +OP4 E00631 0 +OP4 E00632 0 +OP4 E00633 0 +OP4 E00634 0 +OP4 E00635 0 +OP4 E00636 0 +OP4 E00637 0 +OP4 E00638 0 +OP4 E00639 0 +OP4 E0063A 0 +OP4 E0063B 0 +OP4 E0063C 0 +OP4 E0063D 0 +OP4 E0063E 0 +OP4 E0063F 0 +OP4 E00640 0 +OP4 E00641 0 +OP4 E00642 0 +OP4 E00643 0 +OP4 E00644 0 +OP4 E00645 0 +OP4 E00646 0 +OP4 E00647 0 +OP4 E00648 0 +OP4 E00649 0 +OP4 E0064A 0 +OP4 E0064B 0 +OP4 E0064C 0 +OP4 E0064D 0 +OP4 E0064E 0 +OP4 E0064F 0 +OP4 E00650 0 +OP4 E00651 0 +OP4 E00652 0 +OP4 E00653 0 +OP4 E00654 0 +OP4 E00655 0 +OP4 E00656 0 +OP4 E00657 0 +OP4 E00658 0 +OP4 E00659 0 +OP4 E0065A 0 +OP4 E0065B 0 +OP4 E0065C 0 +OP4 E0065D 0 +OP4 E0065E 0 +OP4 E0065F 0 +OP4 E00660 0 +OP4 E00661 0 +OP4 E00662 0 +OP4 E00663 0 +OP4 E00664 0 +OP4 E00665 0 +OP4 E00666 0 +OP4 E00667 0 +OP4 E00668 0 +OP4 E00669 0 +OP4 E0066A 0 +OP4 E0066B 0 +OP4 E0066C 0 +OP4 E0066D 0 +OP4 E0066E 0 +OP4 E0066F 0 +OP4 E00670 0 +OP4 E00671 0 +OP4 E00672 0 +OP4 E00673 0 +OP4 E00674 0 +OP4 E00675 0 +OP4 E00676 0 +OP4 E00677 0 +OP4 E00678 0 +OP4 E00679 0 +OP4 E0067A 0 +OP4 E0067B 0 +OP4 E0067C 0 +OP4 E0067D 0 +OP4 E0067E 0 +OP4 E0067F 0 +OP4 E00680 0 +OP4 E00681 0 +OP4 E00682 0 +OP4 E00683 0 +OP4 E00684 0 +OP4 E00685 0 +OP4 E00686 0 +OP4 E00687 0 +OP4 E00688 0 +OP4 E00689 0 +OP4 E0068A 0 +OP4 E0068B 0 +OP4 E0068C 0 +OP4 E0068D 0 +OP4 E0068E 0 +OP4 E0068F 0 +OP4 E00690 0 +OP4 E00691 0 +OP4 E00692 0 +OP4 E00693 0 +OP4 E00694 0 +OP4 E00695 0 +OP4 E00696 0 +OP4 E00697 0 +OP4 E00698 0 +OP4 E00699 0 +OP4 E0069A 0 +OP4 E0069B 0 +OP4 E0069C 0 +OP4 E0069D 0 +OP4 E0069E 0 +OP4 E0069F 0 +OP4 E006A0 0 +OP4 E006A1 0 +OP4 E006A2 0 +OP4 E006A3 0 +OP4 E006A4 0 +OP4 E006A5 0 +OP4 E006A6 0 +OP4 E006A7 0 +OP4 E006A8 0 +OP4 E006A9 0 +OP4 E006AA 0 +OP4 E006AB 0 +OP4 E006AC 0 +OP4 E006AD 0 +OP4 E006AE 0 +OP4 E006AF 0 +OP4 E006B0 0 +OP4 E006B1 0 +OP4 E006B2 0 +OP4 E006B3 0 +OP4 E006B4 0 +OP4 E006B5 0 +OP4 E006B6 0 +OP4 E006B7 0 +OP4 E006B8 0 +OP4 E006B9 0 +OP4 E006BA 0 +OP4 E006BB 0 +OP4 E006BC 0 +OP4 E006BD 0 +OP4 E006BE 0 +OP4 E006BF 0 +OP4 E006C0 0 +OP4 E006C1 0 +OP4 E006C2 0 +OP4 E006C3 0 +OP4 E006C4 0 +OP4 E006C5 0 +OP4 E006C6 0 +OP4 E006C7 0 +OP4 E006C8 0 +OP4 E006C9 0 +OP4 E006CA 0 +OP4 E006CB 0 +OP4 E006CC 0 +OP4 E006CD 0 +OP4 E006CE 0 +OP4 E006CF 0 +OP4 E006D0 0 +OP4 E006D1 0 +OP4 E006D2 0 +OP4 E006D3 0 +OP4 E006D4 0 +OP4 E006D5 0 +OP4 E006D6 0 +OP4 E006D7 0 +OP4 E006D8 0 +OP4 E006D9 0 +OP4 E006DA 0 +OP4 E006DB 0 +OP4 E006DC 0 +OP4 E006DD 0 +OP4 E006DE 0 +OP4 E006DF 0 +OP4 E006E0 0 +OP4 E006E1 0 +OP4 E006E2 0 +OP4 E006E3 0 +OP4 E006E4 0 +OP4 E006E5 0 +OP4 E006E6 0 +OP4 E006E7 0 +OP4 E006E8 0 +OP4 E006E9 0 +OP4 E006EA 0 +OP4 E006EB 0 +OP4 E006EC 0 +OP4 E006ED 0 +OP4 E006EE 0 +OP4 E006EF 0 +OP4 E006F0 0 +OP4 E006F1 0 +OP4 E006F2 0 +OP4 E006F3 0 +OP4 E006F4 0 +OP4 E006F5 0 +OP4 E006F6 0 +OP4 E006F7 0 +OP4 E006F8 0 +OP4 E006F9 0 +OP4 E006FA 0 +OP4 E006FB 0 +OP4 E006FC 0 +OP4 E006FD 0 +OP4 E006FE 0 +OP4 E006FF 0 +OP4 E00700 0 +OP4 E00701 0 +OP4 E00702 0 +OP4 E00703 0 +OP4 E00704 0 +OP4 E00705 0 +OP4 E00706 0 +OP4 E00707 0 +OP4 E00708 0 +OP4 E00709 0 +OP4 E0070A 0 +OP4 E0070B 0 +OP4 E0070C 0 +OP4 E0070D 0 +OP4 E0070E 0 +OP4 E0070F 0 +OP4 E00710 0 +OP4 E00711 0 +OP4 E00712 0 +OP4 E00713 0 +OP4 E00714 0 +OP4 E00715 0 +OP4 E00716 0 +OP4 E00717 0 +OP4 E00718 0 +OP4 E00719 0 +OP4 E0071A 0 +OP4 E0071B 0 +OP4 E0071C 0 +OP4 E0071D 0 +OP4 E0071E 0 +OP4 E0071F 0 +OP4 E00720 0 +OP4 E00721 0 +OP4 E00722 0 +OP4 E00723 0 +OP4 E00724 0 +OP4 E00725 0 +OP4 E00726 0 +OP4 E00727 0 +OP4 E00728 0 +OP4 E00729 0 +OP4 E0072A 0 +OP4 E0072B 0 +OP4 E0072C 0 +OP4 E0072D 0 +OP4 E0072E 0 +OP4 E0072F 0 +OP4 E00730 0 +OP4 E00731 0 +OP4 E00732 0 +OP4 E00733 0 +OP4 E00734 0 +OP4 E00735 0 +OP4 E00736 0 +OP4 E00737 0 +OP4 E00738 0 +OP4 E00739 0 +OP4 E0073A 0 +OP4 E0073B 0 +OP4 E0073C 0 +OP4 E0073D 0 +OP4 E0073E 0 +OP4 E0073F 0 +OP4 E00740 0 +OP4 E00741 0 +OP4 E00742 0 +OP4 E00743 0 +OP4 E00744 0 +OP4 E00745 0 +OP4 E00746 0 +OP4 E00747 0 +OP4 E00748 0 +OP4 E00749 0 +OP4 E0074A 0 +OP4 E0074B 0 +OP4 E0074C 0 +OP4 E0074D 0 +OP4 E0074E 0 +OP4 E0074F 0 +OP4 E00750 0 +OP4 E00751 0 +OP4 E00752 0 +OP4 E00753 0 +OP4 E00754 0 +OP4 E00755 0 +OP4 E00756 0 +OP4 E00757 0 +OP4 E00758 0 +OP4 E00759 0 +OP4 E0075A 0 +OP4 E0075B 0 +OP4 E0075C 0 +OP4 E0075D 0 +OP4 E0075E 0 +OP4 E0075F 0 +OP4 E00760 0 +OP4 E00761 0 +OP4 E00762 0 +OP4 E00763 0 +OP4 E00764 0 +OP4 E00765 0 +OP4 E00766 0 +OP4 E00767 0 +OP4 E00768 0 +OP4 E00769 0 +OP4 E0076A 0 +OP4 E0076B 0 +OP4 E0076C 0 +OP4 E0076D 0 +OP4 E0076E 0 +OP4 E0076F 0 +OP4 E00770 0 +OP4 E00771 0 +OP4 E00772 0 +OP4 E00773 0 +OP4 E00774 0 +OP4 E00775 0 +OP4 E00776 0 +OP4 E00777 0 +OP4 E00778 0 +OP4 E00779 0 +OP4 E0077A 0 +OP4 E0077B 0 +OP4 E0077C 0 +OP4 E0077D 0 +OP4 E0077E 0 +OP4 E0077F 0 +OP4 E00780 0 +OP4 E00781 0 +OP4 E00782 0 +OP4 E00783 0 +OP4 E00784 0 +OP4 E00785 0 +OP4 E00786 0 +OP4 E00787 0 +OP4 E00788 0 +OP4 E00789 0 +OP4 E0078A 0 +OP4 E0078B 0 +OP4 E0078C 0 +OP4 E0078D 0 +OP4 E0078E 0 +OP4 E0078F 0 +OP4 E00790 0 +OP4 E00791 0 +OP4 E00792 0 +OP4 E00793 0 +OP4 E00794 0 +OP4 E00795 0 +OP4 E00796 0 +OP4 E00797 0 +OP4 E00798 0 +OP4 E00799 0 +OP4 E0079A 0 +OP4 E0079B 0 +OP4 E0079C 0 +OP4 E0079D 0 +OP4 E0079E 0 +OP4 E0079F 0 +OP4 E007A0 0 +OP4 E007A1 0 +OP4 E007A2 0 +OP4 E007A3 0 +OP4 E007A4 0 +OP4 E007A5 0 +OP4 E007A6 0 +OP4 E007A7 0 +OP4 E007A8 0 +OP4 E007A9 0 +OP4 E007AA 0 +OP4 E007AB 0 +OP4 E007AC 0 +OP4 E007AD 0 +OP4 E007AE 0 +OP4 E007AF 0 +OP4 E007B0 0 +OP4 E007B1 0 +OP4 E007B2 0 +OP4 E007B3 0 +OP4 E007B4 0 +OP4 E007B5 0 +OP4 E007B6 0 +OP4 E007B7 0 +OP4 E007B8 0 +OP4 E007B9 0 +OP4 E007BA 0 +OP4 E007BB 0 +OP4 E007BC 0 +OP4 E007BD 0 +OP4 E007BE 0 +OP4 E007BF 0 +OP4 E007C0 0 +OP4 E007C1 0 +OP4 E007C2 0 +OP4 E007C3 0 +OP4 E007C4 0 +OP4 E007C5 0 +OP4 E007C6 0 +OP4 E007C7 0 +OP4 E007C8 0 +OP4 E007C9 0 +OP4 E007CA 0 +OP4 E007CB 0 +OP4 E007CC 0 +OP4 E007CD 0 +OP4 E007CE 0 +OP4 E007CF 0 +OP4 E007D0 0 +OP4 E007D1 0 +OP4 E007D2 0 +OP4 E007D3 0 +OP4 E007D4 0 +OP4 E007D5 0 +OP4 E007D6 0 +OP4 E007D7 0 +OP4 E007D8 0 +OP4 E007D9 0 +OP4 E007DA 0 +OP4 E007DB 0 +OP4 E007DC 0 +OP4 E007DD 0 +OP4 E007DE 0 +OP4 E007DF 0 +OP4 E007E0 0 +OP4 E007E1 0 +OP4 E007E2 0 +OP4 E007E3 0 +OP4 E007E4 0 +OP4 E007E5 0 +OP4 E007E6 0 +OP4 E007E7 0 +OP4 E007E8 0 +OP4 E007E9 0 +OP4 E007EA 0 +OP4 E007EB 0 +OP4 E007EC 0 +OP4 E007ED 0 +OP4 E007EE 0 +OP4 E007EF 0 +OP4 E007F0 0 +OP4 E007F1 0 +OP4 E007F2 0 +OP4 E007F3 0 +OP4 E007F4 0 +OP4 E007F5 0 +OP4 E007F6 0 +OP4 E007F7 0 +OP4 E007F8 0 +OP4 E007F9 0 +OP4 E007FA 0 +OP4 E007FB 0 +OP4 E007FC 0 +OP4 E007FD 0 +OP4 E007FE 0 +OP4 E007FF 0 +OP4 E00800 0 +OP4 E00801 0 +OP4 E00802 0 +OP4 E00803 0 +OP4 E00804 0 +OP4 E00805 0 +OP4 E00806 0 +OP4 E00807 0 +OP4 E00808 0 +OP4 E00809 0 +OP4 E0080A 0 +OP4 E0080B 0 +OP4 E0080C 0 +OP4 E0080D 0 +OP4 E0080E 0 +OP4 E0080F 0 +OP4 E00810 0 +OP4 E00811 0 +OP4 E00812 0 +OP4 E00813 0 +OP4 E00814 0 +OP4 E00815 0 +OP4 E00816 0 +OP4 E00817 0 +OP4 E00818 0 +OP4 E00819 0 +OP4 E0081A 0 +OP4 E0081B 0 +OP4 E0081C 0 +OP4 E0081D 0 +OP4 E0081E 0 +OP4 E0081F 0 +OP4 E00820 0 +OP4 E00821 0 +OP4 E00822 0 +OP4 E00823 0 +OP4 E00824 0 +OP4 E00825 0 +OP4 E00826 0 +OP4 E00827 0 +OP4 E00828 0 +OP4 E00829 0 +OP4 E0082A 0 +OP4 E0082B 0 +OP4 E0082C 0 +OP4 E0082D 0 +OP4 E0082E 0 +OP4 E0082F 0 +OP4 E00830 0 +OP4 E00831 0 +OP4 E00832 0 +OP4 E00833 0 +OP4 E00834 0 +OP4 E00835 0 +OP4 E00836 0 +OP4 E00837 0 +OP4 E00838 0 +OP4 E00839 0 +OP4 E0083A 0 +OP4 E0083B 0 +OP4 E0083C 0 +OP4 E0083D 0 +OP4 E0083E 0 +OP4 E0083F 0 +OP4 E00840 0 +OP4 E00841 0 +OP4 E00842 0 +OP4 E00843 0 +OP4 E00844 0 +OP4 E00845 0 +OP4 E00846 0 +OP4 E00847 0 +OP4 E00848 0 +OP4 E00849 0 +OP4 E0084A 0 +OP4 E0084B 0 +OP4 E0084C 0 +OP4 E0084D 0 +OP4 E0084E 0 +OP4 E0084F 0 +OP4 E00850 0 +OP4 E00851 0 +OP4 E00852 0 +OP4 E00853 0 +OP4 E00854 0 +OP4 E00855 0 +OP4 E00856 0 +OP4 E00857 0 +OP4 E00858 0 +OP4 E00859 0 +OP4 E0085A 0 +OP4 E0085B 0 +OP4 E0085C 0 +OP4 E0085D 0 +OP4 E0085E 0 +OP4 E0085F 0 +OP4 E00860 0 +OP4 E00861 0 +OP4 E00862 0 +OP4 E00863 0 +OP4 E00864 0 +OP4 E00865 0 +OP4 E00866 0 +OP4 E00867 0 +OP4 E00868 0 +OP4 E00869 0 +OP4 E0086A 0 +OP4 E0086B 0 +OP4 E0086C 0 +OP4 E0086D 0 +OP4 E0086E 0 +OP4 E0086F 0 +OP4 E00870 0 +OP4 E00871 0 +OP4 E00872 0 +OP4 E00873 0 +OP4 E00874 0 +OP4 E00875 0 +OP4 E00876 0 +OP4 E00877 0 +OP4 E00878 0 +OP4 E00879 0 +OP4 E0087A 0 +OP4 E0087B 0 +OP4 E0087C 0 +OP4 E0087D 0 +OP4 E0087E 0 +OP4 E0087F 0 +OP4 E00880 0 +OP4 E00881 0 +OP4 E00882 0 +OP4 E00883 0 +OP4 E00884 0 +OP4 E00885 0 +OP4 E00886 0 +OP4 E00887 0 +OP4 E00888 0 +OP4 E00889 0 +OP4 E0088A 0 +OP4 E0088B 0 +OP4 E0088C 0 +OP4 E0088D 0 +OP4 E0088E 0 +OP4 E0088F 0 +OP4 E00890 0 +OP4 E00891 0 +OP4 E00892 0 +OP4 E00893 0 +OP4 E00894 0 +OP4 E00895 0 +OP4 E00896 0 +OP4 E00897 0 +OP4 E00898 0 +OP4 E00899 0 +OP4 E0089A 0 +OP4 E0089B 0 +OP4 E0089C 0 +OP4 E0089D 0 +OP4 E0089E 0 +OP4 E0089F 0 +OP4 E008A0 0 +OP4 E008A1 0 +OP4 E008A2 0 +OP4 E008A3 0 +OP4 E008A4 0 +OP4 E008A5 0 +OP4 E008A6 0 +OP4 E008A7 0 +OP4 E008A8 0 +OP4 E008A9 0 +OP4 E008AA 0 +OP4 E008AB 0 +OP4 E008AC 0 +OP4 E008AD 0 +OP4 E008AE 0 +OP4 E008AF 0 +OP4 E008B0 0 +OP4 E008B1 0 +OP4 E008B2 0 +OP4 E008B3 0 +OP4 E008B4 0 +OP4 E008B5 0 +OP4 E008B6 0 +OP4 E008B7 0 +OP4 E008B8 0 +OP4 E008B9 0 +OP4 E008BA 0 +OP4 E008BB 0 +OP4 E008BC 0 +OP4 E008BD 0 +OP4 E008BE 0 +OP4 E008BF 0 +OP4 E008C0 0 +OP4 E008C1 0 +OP4 E008C2 0 +OP4 E008C3 0 +OP4 E008C4 0 +OP4 E008C5 0 +OP4 E008C6 0 +OP4 E008C7 0 +OP4 E008C8 0 +OP4 E008C9 0 +OP4 E008CA 0 +OP4 E008CB 0 +OP4 E008CC 0 +OP4 E008CD 0 +OP4 E008CE 0 +OP4 E008CF 0 +OP4 E008D0 0 +OP4 E008D1 0 +OP4 E008D2 0 +OP4 E008D3 0 +OP4 E008D4 0 +OP4 E008D5 0 +OP4 E008D6 0 +OP4 E008D7 0 +OP4 E008D8 0 +OP4 E008D9 0 +OP4 E008DA 0 +OP4 E008DB 0 +OP4 E008DC 0 +OP4 E008DD 0 +OP4 E008DE 0 +OP4 E008DF 0 +OP4 E008E0 0 +OP4 E008E1 0 +OP4 E008E2 0 +OP4 E008E3 0 +OP4 E008E4 0 +OP4 E008E5 0 +OP4 E008E6 0 +OP4 E008E7 0 +OP4 E008E8 0 +OP4 E008E9 0 +OP4 E008EA 0 +OP4 E008EB 0 +OP4 E008EC 0 +OP4 E008ED 0 +OP4 E008EE 0 +OP4 E008EF 0 +OP4 E008F0 0 +OP4 E008F1 0 +OP4 E008F2 0 +OP4 E008F3 0 +OP4 E008F4 0 +OP4 E008F5 0 +OP4 E008F6 0 +OP4 E008F7 0 +OP4 E008F8 0 +OP4 E008F9 0 +OP4 E008FA 0 +OP4 E008FB 0 +OP4 E008FC 0 +OP4 E008FD 0 +OP4 E008FE 0 +OP4 E008FF 0 +OP4 E00900 0 +OP4 E00901 0 +OP4 E00902 0 +OP4 E00903 0 +OP4 E00904 0 +OP4 E00905 0 +OP4 E00906 0 +OP4 E00907 0 +OP4 E00908 0 +OP4 E00909 0 +OP4 E0090A 0 +OP4 E0090B 0 +OP4 E0090C 0 +OP4 E0090D 0 +OP4 E0090E 0 +OP4 E0090F 0 +OP4 E00910 0 +OP4 E00911 0 +OP4 E00912 0 +OP4 E00913 0 +OP4 E00914 0 +OP4 E00915 0 +OP4 E00916 0 +OP4 E00917 0 +OP4 E00918 0 +OP4 E00919 0 +OP4 E0091A 0 +OP4 E0091B 0 +OP4 E0091C 0 +OP4 E0091D 0 +OP4 E0091E 0 +OP4 E0091F 0 +OP4 E00920 0 +OP4 E00921 0 +OP4 E00922 0 +OP4 E00923 0 +OP4 E00924 0 +OP4 E00925 0 +OP4 E00926 0 +OP4 E00927 0 +OP4 E00928 0 +OP4 E00929 0 +OP4 E0092A 0 +OP4 E0092B 0 +OP4 E0092C 0 +OP4 E0092D 0 +OP4 E0092E 0 +OP4 E0092F 0 +OP4 E00930 0 +OP4 E00931 0 +OP4 E00932 0 +OP4 E00933 0 +OP4 E00934 0 +OP4 E00935 0 +OP4 E00936 0 +OP4 E00937 0 +OP4 E00938 0 +OP4 E00939 0 +OP4 E0093A 0 +OP4 E0093B 0 +OP4 E0093C 0 +OP4 E0093D 0 +OP4 E0093E 0 +OP4 E0093F 0 +OP4 E00940 0 +OP4 E00941 0 +OP4 E00942 0 +OP4 E00943 0 +OP4 E00944 0 +OP4 E00945 0 +OP4 E00946 0 +OP4 E00947 0 +OP4 E00948 0 +OP4 E00949 0 +OP4 E0094A 0 +OP4 E0094B 0 +OP4 E0094C 0 +OP4 E0094D 0 +OP4 E0094E 0 +OP4 E0094F 0 +OP4 E00950 0 +OP4 E00951 0 +OP4 E00952 0 +OP4 E00953 0 +OP4 E00954 0 +OP4 E00955 0 +OP4 E00956 0 +OP4 E00957 0 +OP4 E00958 0 +OP4 E00959 0 +OP4 E0095A 0 +OP4 E0095B 0 +OP4 E0095C 0 +OP4 E0095D 0 +OP4 E0095E 0 +OP4 E0095F 0 +OP4 E00960 0 +OP4 E00961 0 +OP4 E00962 0 +OP4 E00963 0 +OP4 E00964 0 +OP4 E00965 0 +OP4 E00966 0 +OP4 E00967 0 +OP4 E00968 0 +OP4 E00969 0 +OP4 E0096A 0 +OP4 E0096B 0 +OP4 E0096C 0 +OP4 E0096D 0 +OP4 E0096E 0 +OP4 E0096F 0 +OP4 E00970 0 +OP4 E00971 0 +OP4 E00972 0 +OP4 E00973 0 +OP4 E00974 0 +OP4 E00975 0 +OP4 E00976 0 +OP4 E00977 0 +OP4 E00978 0 +OP4 E00979 0 +OP4 E0097A 0 +OP4 E0097B 0 +OP4 E0097C 0 +OP4 E0097D 0 +OP4 E0097E 0 +OP4 E0097F 0 +OP4 E00980 0 +OP4 E00981 0 +OP4 E00982 0 +OP4 E00983 0 +OP4 E00984 0 +OP4 E00985 0 +OP4 E00986 0 +OP4 E00987 0 +OP4 E00988 0 +OP4 E00989 0 +OP4 E0098A 0 +OP4 E0098B 0 +OP4 E0098C 0 +OP4 E0098D 0 +OP4 E0098E 0 +OP4 E0098F 0 +OP4 E00990 0 +OP4 E00991 0 +OP4 E00992 0 +OP4 E00993 0 +OP4 E00994 0 +OP4 E00995 0 +OP4 E00996 0 +OP4 E00997 0 +OP4 E00998 0 +OP4 E00999 0 +OP4 E0099A 0 +OP4 E0099B 0 +OP4 E0099C 0 +OP4 E0099D 0 +OP4 E0099E 0 +OP4 E0099F 0 +OP4 E009A0 0 +OP4 E009A1 0 +OP4 E009A2 0 +OP4 E009A3 0 +OP4 E009A4 0 +OP4 E009A5 0 +OP4 E009A6 0 +OP4 E009A7 0 +OP4 E009A8 0 +OP4 E009A9 0 +OP4 E009AA 0 +OP4 E009AB 0 +OP4 E009AC 0 +OP4 E009AD 0 +OP4 E009AE 0 +OP4 E009AF 0 +OP4 E009B0 0 +OP4 E009B1 0 +OP4 E009B2 0 +OP4 E009B3 0 +OP4 E009B4 0 +OP4 E009B5 0 +OP4 E009B6 0 +OP4 E009B7 0 +OP4 E009B8 0 +OP4 E009B9 0 +OP4 E009BA 0 +OP4 E009BB 0 +OP4 E009BC 0 +OP4 E009BD 0 +OP4 E009BE 0 +OP4 E009BF 0 +OP4 E009C0 0 +OP4 E009C1 0 +OP4 E009C2 0 +OP4 E009C3 0 +OP4 E009C4 0 +OP4 E009C5 0 +OP4 E009C6 0 +OP4 E009C7 0 +OP4 E009C8 0 +OP4 E009C9 0 +OP4 E009CA 0 +OP4 E009CB 0 +OP4 E009CC 0 +OP4 E009CD 0 +OP4 E009CE 0 +OP4 E009CF 0 +OP4 E009D0 0 +OP4 E009D1 0 +OP4 E009D2 0 +OP4 E009D3 0 +OP4 E009D4 0 +OP4 E009D5 0 +OP4 E009D6 0 +OP4 E009D7 0 +OP4 E009D8 0 +OP4 E009D9 0 +OP4 E009DA 0 +OP4 E009DB 0 +OP4 E009DC 0 +OP4 E009DD 0 +OP4 E009DE 0 +OP4 E009DF 0 +OP4 E009E0 0 +OP4 E009E1 0 +OP4 E009E2 0 +OP4 E009E3 0 +OP4 E009E4 0 +OP4 E009E5 0 +OP4 E009E6 0 +OP4 E009E7 0 +OP4 E009E8 0 +OP4 E009E9 0 +OP4 E009EA 0 +OP4 E009EB 0 +OP4 E009EC 0 +OP4 E009ED 0 +OP4 E009EE 0 +OP4 E009EF 0 +OP4 E009F0 0 +OP4 E009F1 0 +OP4 E009F2 0 +OP4 E009F3 0 +OP4 E009F4 0 +OP4 E009F5 0 +OP4 E009F6 0 +OP4 E009F7 0 +OP4 E009F8 0 +OP4 E009F9 0 +OP4 E009FA 0 +OP4 E009FB 0 +OP4 E009FC 0 +OP4 E009FD 0 +OP4 E009FE 0 +OP4 E009FF 0 +OP4 E00A00 0 +OP4 E00A01 0 +OP4 E00A02 0 +OP4 E00A03 0 +OP4 E00A04 0 +OP4 E00A05 0 +OP4 E00A06 0 +OP4 E00A07 0 +OP4 E00A08 0 +OP4 E00A09 0 +OP4 E00A0A 0 +OP4 E00A0B 0 +OP4 E00A0C 0 +OP4 E00A0D 0 +OP4 E00A0E 0 +OP4 E00A0F 0 +OP4 E00A10 0 +OP4 E00A11 0 +OP4 E00A12 0 +OP4 E00A13 0 +OP4 E00A14 0 +OP4 E00A15 0 +OP4 E00A16 0 +OP4 E00A17 0 +OP4 E00A18 0 +OP4 E00A19 0 +OP4 E00A1A 0 +OP4 E00A1B 0 +OP4 E00A1C 0 +OP4 E00A1D 0 +OP4 E00A1E 0 +OP4 E00A1F 0 +OP4 E00A20 0 +OP4 E00A21 0 +OP4 E00A22 0 +OP4 E00A23 0 +OP4 E00A24 0 +OP4 E00A25 0 +OP4 E00A26 0 +OP4 E00A27 0 +OP4 E00A28 0 +OP4 E00A29 0 +OP4 E00A2A 0 +OP4 E00A2B 0 +OP4 E00A2C 0 +OP4 E00A2D 0 +OP4 E00A2E 0 +OP4 E00A2F 0 +OP4 E00A30 0 +OP4 E00A31 0 +OP4 E00A32 0 +OP4 E00A33 0 +OP4 E00A34 0 +OP4 E00A35 0 +OP4 E00A36 0 +OP4 E00A37 0 +OP4 E00A38 0 +OP4 E00A39 0 +OP4 E00A3A 0 +OP4 E00A3B 0 +OP4 E00A3C 0 +OP4 E00A3D 0 +OP4 E00A3E 0 +OP4 E00A3F 0 +OP4 E00A40 0 +OP4 E00A41 0 +OP4 E00A42 0 +OP4 E00A43 0 +OP4 E00A44 0 +OP4 E00A45 0 +OP4 E00A46 0 +OP4 E00A47 0 +OP4 E00A48 0 +OP4 E00A49 0 +OP4 E00A4A 0 +OP4 E00A4B 0 +OP4 E00A4C 0 +OP4 E00A4D 0 +OP4 E00A4E 0 +OP4 E00A4F 0 +OP4 E00A50 0 +OP4 E00A51 0 +OP4 E00A52 0 +OP4 E00A53 0 +OP4 E00A54 0 +OP4 E00A55 0 +OP4 E00A56 0 +OP4 E00A57 0 +OP4 E00A58 0 +OP4 E00A59 0 +OP4 E00A5A 0 +OP4 E00A5B 0 +OP4 E00A5C 0 +OP4 E00A5D 0 +OP4 E00A5E 0 +OP4 E00A5F 0 +OP4 E00A60 0 +OP4 E00A61 0 +OP4 E00A62 0 +OP4 E00A63 0 +OP4 E00A64 0 +OP4 E00A65 0 +OP4 E00A66 0 +OP4 E00A67 0 +OP4 E00A68 0 +OP4 E00A69 0 +OP4 E00A6A 0 +OP4 E00A6B 0 +OP4 E00A6C 0 +OP4 E00A6D 0 +OP4 E00A6E 0 +OP4 E00A6F 0 +OP4 E00A70 0 +OP4 E00A71 0 +OP4 E00A72 0 +OP4 E00A73 0 +OP4 E00A74 0 +OP4 E00A75 0 +OP4 E00A76 0 +OP4 E00A77 0 +OP4 E00A78 0 +OP4 E00A79 0 +OP4 E00A7A 0 +OP4 E00A7B 0 +OP4 E00A7C 0 +OP4 E00A7D 0 +OP4 E00A7E 0 +OP4 E00A7F 0 +OP4 E00A80 0 +OP4 E00A81 0 +OP4 E00A82 0 +OP4 E00A83 0 +OP4 E00A84 0 +OP4 E00A85 0 +OP4 E00A86 0 +OP4 E00A87 0 +OP4 E00A88 0 +OP4 E00A89 0 +OP4 E00A8A 0 +OP4 E00A8B 0 +OP4 E00A8C 0 +OP4 E00A8D 0 +OP4 E00A8E 0 +OP4 E00A8F 0 +OP4 E00A90 0 +OP4 E00A91 0 +OP4 E00A92 0 +OP4 E00A93 0 +OP4 E00A94 0 +OP4 E00A95 0 +OP4 E00A96 0 +OP4 E00A97 0 +OP4 E00A98 0 +OP4 E00A99 0 +OP4 E00A9A 0 +OP4 E00A9B 0 +OP4 E00A9C 0 +OP4 E00A9D 0 +OP4 E00A9E 0 +OP4 E00A9F 0 +OP4 E00AA0 0 +OP4 E00AA1 0 +OP4 E00AA2 0 +OP4 E00AA3 0 +OP4 E00AA4 0 +OP4 E00AA5 0 +OP4 E00AA6 0 +OP4 E00AA7 0 +OP4 E00AA8 0 +OP4 E00AA9 0 +OP4 E00AAA 0 +OP4 E00AAB 0 +OP4 E00AAC 0 +OP4 E00AAD 0 +OP4 E00AAE 0 +OP4 E00AAF 0 +OP4 E00AB0 0 +OP4 E00AB1 0 +OP4 E00AB2 0 +OP4 E00AB3 0 +OP4 E00AB4 0 +OP4 E00AB5 0 +OP4 E00AB6 0 +OP4 E00AB7 0 +OP4 E00AB8 0 +OP4 E00AB9 0 +OP4 E00ABA 0 +OP4 E00ABB 0 +OP4 E00ABC 0 +OP4 E00ABD 0 +OP4 E00ABE 0 +OP4 E00ABF 0 +OP4 E00AC0 0 +OP4 E00AC1 0 +OP4 E00AC2 0 +OP4 E00AC3 0 +OP4 E00AC4 0 +OP4 E00AC5 0 +OP4 E00AC6 0 +OP4 E00AC7 0 +OP4 E00AC8 0 +OP4 E00AC9 0 +OP4 E00ACA 0 +OP4 E00ACB 0 +OP4 E00ACC 0 +OP4 E00ACD 0 +OP4 E00ACE 0 +OP4 E00ACF 0 +OP4 E00AD0 0 +OP4 E00AD1 0 +OP4 E00AD2 0 +OP4 E00AD3 0 +OP4 E00AD4 0 +OP4 E00AD5 0 +OP4 E00AD6 0 +OP4 E00AD7 0 +OP4 E00AD8 0 +OP4 E00AD9 0 +OP4 E00ADA 0 +OP4 E00ADB 0 +OP4 E00ADC 0 +OP4 E00ADD 0 +OP4 E00ADE 0 +OP4 E00ADF 0 +OP4 E00AE0 0 +OP4 E00AE1 0 +OP4 E00AE2 0 +OP4 E00AE3 0 +OP4 E00AE4 0 +OP4 E00AE5 0 +OP4 E00AE6 0 +OP4 E00AE7 0 +OP4 E00AE8 0 +OP4 E00AE9 0 +OP4 E00AEA 0 +OP4 E00AEB 0 +OP4 E00AEC 0 +OP4 E00AED 0 +OP4 E00AEE 0 +OP4 E00AEF 0 +OP4 E00AF0 0 +OP4 E00AF1 0 +OP4 E00AF2 0 +OP4 E00AF3 0 +OP4 E00AF4 0 +OP4 E00AF5 0 +OP4 E00AF6 0 +OP4 E00AF7 0 +OP4 E00AF8 0 +OP4 E00AF9 0 +OP4 E00AFA 0 +OP4 E00AFB 0 +OP4 E00AFC 0 +OP4 E00AFD 0 +OP4 E00AFE 0 +OP4 E00AFF 0 +OP4 E00B00 0 +OP4 E00B01 0 +OP4 E00B02 0 +OP4 E00B03 0 +OP4 E00B04 0 +OP4 E00B05 0 +OP4 E00B06 0 +OP4 E00B07 0 +OP4 E00B08 0 +OP4 E00B09 0 +OP4 E00B0A 0 +OP4 E00B0B 0 +OP4 E00B0C 0 +OP4 E00B0D 0 +OP4 E00B0E 0 +OP4 E00B0F 0 +OP4 E00B10 0 +OP4 E00B11 0 +OP4 E00B12 0 +OP4 E00B13 0 +OP4 E00B14 0 +OP4 E00B15 0 +OP4 E00B16 0 +OP4 E00B17 0 +OP4 E00B18 0 +OP4 E00B19 0 +OP4 E00B1A 0 +OP4 E00B1B 0 +OP4 E00B1C 0 +OP4 E00B1D 0 +OP4 E00B1E 0 +OP4 E00B1F 0 +OP4 E00B20 0 +OP4 E00B21 0 +OP4 E00B22 0 +OP4 E00B23 0 +OP4 E00B24 0 +OP4 E00B25 0 +OP4 E00B26 0 +OP4 E00B27 0 +OP4 E00B28 0 +OP4 E00B29 0 +OP4 E00B2A 0 +OP4 E00B2B 0 +OP4 E00B2C 0 +OP4 E00B2D 0 +OP4 E00B2E 0 +OP4 E00B2F 0 +OP4 E00B30 0 +OP4 E00B31 0 +OP4 E00B32 0 +OP4 E00B33 0 +OP4 E00B34 0 +OP4 E00B35 0 +OP4 E00B36 0 +OP4 E00B37 0 +OP4 E00B38 0 +OP4 E00B39 0 +OP4 E00B3A 0 +OP4 E00B3B 0 +OP4 E00B3C 0 +OP4 E00B3D 0 +OP4 E00B3E 0 +OP4 E00B3F 0 +OP4 E00B40 0 +OP4 E00B41 0 +OP4 E00B42 0 +OP4 E00B43 0 +OP4 E00B44 0 +OP4 E00B45 0 +OP4 E00B46 0 +OP4 E00B47 0 +OP4 E00B48 0 +OP4 E00B49 0 +OP4 E00B4A 0 +OP4 E00B4B 0 +OP4 E00B4C 0 +OP4 E00B4D 0 +OP4 E00B4E 0 +OP4 E00B4F 0 +OP4 E00B50 0 +OP4 E00B51 0 +OP4 E00B52 0 +OP4 E00B53 0 +OP4 E00B54 0 +OP4 E00B55 0 +OP4 E00B56 0 +OP4 E00B57 0 +OP4 E00B58 0 +OP4 E00B59 0 +OP4 E00B5A 0 +OP4 E00B5B 0 +OP4 E00B5C 0 +OP4 E00B5D 0 +OP4 E00B5E 0 +OP4 E00B5F 0 +OP4 E00B60 0 +OP4 E00B61 0 +OP4 E00B62 0 +OP4 E00B63 0 +OP4 E00B64 0 +OP4 E00B65 0 +OP4 E00B66 0 +OP4 E00B67 0 +OP4 E00B68 0 +OP4 E00B69 0 +OP4 E00B6A 0 +OP4 E00B6B 0 +OP4 E00B6C 0 +OP4 E00B6D 0 +OP4 E00B6E 0 +OP4 E00B6F 0 +OP4 E00B70 0 +OP4 E00B71 0 +OP4 E00B72 0 +OP4 E00B73 0 +OP4 E00B74 0 +OP4 E00B75 0 +OP4 E00B76 0 +OP4 E00B77 0 +OP4 E00B78 0 +OP4 E00B79 0 +OP4 E00B7A 0 +OP4 E00B7B 0 +OP4 E00B7C 0 +OP4 E00B7D 0 +OP4 E00B7E 0 +OP4 E00B7F 0 +OP4 E00B80 0 +OP4 E00B81 0 +OP4 E00B82 0 +OP4 E00B83 0 +OP4 E00B84 0 +OP4 E00B85 0 +OP4 E00B86 0 +OP4 E00B87 0 +OP4 E00B88 0 +OP4 E00B89 0 +OP4 E00B8A 0 +OP4 E00B8B 0 +OP4 E00B8C 0 +OP4 E00B8D 0 +OP4 E00B8E 0 +OP4 E00B8F 0 +OP4 E00B90 0 +OP4 E00B91 0 +OP4 E00B92 0 +OP4 E00B93 0 +OP4 E00B94 0 +OP4 E00B95 0 +OP4 E00B96 0 +OP4 E00B97 0 +OP4 E00B98 0 +OP4 E00B99 0 +OP4 E00B9A 0 +OP4 E00B9B 0 +OP4 E00B9C 0 +OP4 E00B9D 0 +OP4 E00B9E 0 +OP4 E00B9F 0 +OP4 E00BA0 0 +OP4 E00BA1 0 +OP4 E00BA2 0 +OP4 E00BA3 0 +OP4 E00BA4 0 +OP4 E00BA5 0 +OP4 E00BA6 0 +OP4 E00BA7 0 +OP4 E00BA8 0 +OP4 E00BA9 0 +OP4 E00BAA 0 +OP4 E00BAB 0 +OP4 E00BAC 0 +OP4 E00BAD 0 +OP4 E00BAE 0 +OP4 E00BAF 0 +OP4 E00BB0 0 +OP4 E00BB1 0 +OP4 E00BB2 0 +OP4 E00BB3 0 +OP4 E00BB4 0 +OP4 E00BB5 0 +OP4 E00BB6 0 +OP4 E00BB7 0 +OP4 E00BB8 0 +OP4 E00BB9 0 +OP4 E00BBA 0 +OP4 E00BBB 0 +OP4 E00BBC 0 +OP4 E00BBD 0 +OP4 E00BBE 0 +OP4 E00BBF 0 +OP4 E00BC0 0 +OP4 E00BC1 0 +OP4 E00BC2 0 +OP4 E00BC3 0 +OP4 E00BC4 0 +OP4 E00BC5 0 +OP4 E00BC6 0 +OP4 E00BC7 0 +OP4 E00BC8 0 +OP4 E00BC9 0 +OP4 E00BCA 0 +OP4 E00BCB 0 +OP4 E00BCC 0 +OP4 E00BCD 0 +OP4 E00BCE 0 +OP4 E00BCF 0 +OP4 E00BD0 0 +OP4 E00BD1 0 +OP4 E00BD2 0 +OP4 E00BD3 0 +OP4 E00BD4 0 +OP4 E00BD5 0 +OP4 E00BD6 0 +OP4 E00BD7 0 +OP4 E00BD8 0 +OP4 E00BD9 0 +OP4 E00BDA 0 +OP4 E00BDB 0 +OP4 E00BDC 0 +OP4 E00BDD 0 +OP4 E00BDE 0 +OP4 E00BDF 0 +OP4 E00BE0 0 +OP4 E00BE1 0 +OP4 E00BE2 0 +OP4 E00BE3 0 +OP4 E00BE4 0 +OP4 E00BE5 0 +OP4 E00BE6 0 +OP4 E00BE7 0 +OP4 E00BE8 0 +OP4 E00BE9 0 +OP4 E00BEA 0 +OP4 E00BEB 0 +OP4 E00BEC 0 +OP4 E00BED 0 +OP4 E00BEE 0 +OP4 E00BEF 0 +OP4 E00BF0 0 +OP4 E00BF1 0 +OP4 E00BF2 0 +OP4 E00BF3 0 +OP4 E00BF4 0 +OP4 E00BF5 0 +OP4 E00BF6 0 +OP4 E00BF7 0 +OP4 E00BF8 0 +OP4 E00BF9 0 +OP4 E00BFA 0 +OP4 E00BFB 0 +OP4 E00BFC 0 +OP4 E00BFD 0 +OP4 E00BFE 0 +OP4 E00BFF 0 +OP4 E00C00 0 +OP4 E00C01 0 +OP4 E00C02 0 +OP4 E00C03 0 +OP4 E00C04 0 +OP4 E00C05 0 +OP4 E00C06 0 +OP4 E00C07 0 +OP4 E00C08 0 +OP4 E00C09 0 +OP4 E00C0A 0 +OP4 E00C0B 0 +OP4 E00C0C 0 +OP4 E00C0D 0 +OP4 E00C0E 0 +OP4 E00C0F 0 +OP4 E00C10 0 +OP4 E00C11 0 +OP4 E00C12 0 +OP4 E00C13 0 +OP4 E00C14 0 +OP4 E00C15 0 +OP4 E00C16 0 +OP4 E00C17 0 +OP4 E00C18 0 +OP4 E00C19 0 +OP4 E00C1A 0 +OP4 E00C1B 0 +OP4 E00C1C 0 +OP4 E00C1D 0 +OP4 E00C1E 0 +OP4 E00C1F 0 +OP4 E00C20 0 +OP4 E00C21 0 +OP4 E00C22 0 +OP4 E00C23 0 +OP4 E00C24 0 +OP4 E00C25 0 +OP4 E00C26 0 +OP4 E00C27 0 +OP4 E00C28 0 +OP4 E00C29 0 +OP4 E00C2A 0 +OP4 E00C2B 0 +OP4 E00C2C 0 +OP4 E00C2D 0 +OP4 E00C2E 0 +OP4 E00C2F 0 +OP4 E00C30 0 +OP4 E00C31 0 +OP4 E00C32 0 +OP4 E00C33 0 +OP4 E00C34 0 +OP4 E00C35 0 +OP4 E00C36 0 +OP4 E00C37 0 +OP4 E00C38 0 +OP4 E00C39 0 +OP4 E00C3A 0 +OP4 E00C3B 0 +OP4 E00C3C 0 +OP4 E00C3D 0 +OP4 E00C3E 0 +OP4 E00C3F 0 +OP4 E00C40 0 +OP4 E00C41 0 +OP4 E00C42 0 +OP4 E00C43 0 +OP4 E00C44 0 +OP4 E00C45 0 +OP4 E00C46 0 +OP4 E00C47 0 +OP4 E00C48 0 +OP4 E00C49 0 +OP4 E00C4A 0 +OP4 E00C4B 0 +OP4 E00C4C 0 +OP4 E00C4D 0 +OP4 E00C4E 0 +OP4 E00C4F 0 +OP4 E00C50 0 +OP4 E00C51 0 +OP4 E00C52 0 +OP4 E00C53 0 +OP4 E00C54 0 +OP4 E00C55 0 +OP4 E00C56 0 +OP4 E00C57 0 +OP4 E00C58 0 +OP4 E00C59 0 +OP4 E00C5A 0 +OP4 E00C5B 0 +OP4 E00C5C 0 +OP4 E00C5D 0 +OP4 E00C5E 0 +OP4 E00C5F 0 +OP4 E00C60 0 +OP4 E00C61 0 +OP4 E00C62 0 +OP4 E00C63 0 +OP4 E00C64 0 +OP4 E00C65 0 +OP4 E00C66 0 +OP4 E00C67 0 +OP4 E00C68 0 +OP4 E00C69 0 +OP4 E00C6A 0 +OP4 E00C6B 0 +OP4 E00C6C 0 +OP4 E00C6D 0 +OP4 E00C6E 0 +OP4 E00C6F 0 +OP4 E00C70 0 +OP4 E00C71 0 +OP4 E00C72 0 +OP4 E00C73 0 +OP4 E00C74 0 +OP4 E00C75 0 +OP4 E00C76 0 +OP4 E00C77 0 +OP4 E00C78 0 +OP4 E00C79 0 +OP4 E00C7A 0 +OP4 E00C7B 0 +OP4 E00C7C 0 +OP4 E00C7D 0 +OP4 E00C7E 0 +OP4 E00C7F 0 +OP4 E00C80 0 +OP4 E00C81 0 +OP4 E00C82 0 +OP4 E00C83 0 +OP4 E00C84 0 +OP4 E00C85 0 +OP4 E00C86 0 +OP4 E00C87 0 +OP4 E00C88 0 +OP4 E00C89 0 +OP4 E00C8A 0 +OP4 E00C8B 0 +OP4 E00C8C 0 +OP4 E00C8D 0 +OP4 E00C8E 0 +OP4 E00C8F 0 +OP4 E00C90 0 +OP4 E00C91 0 +OP4 E00C92 0 +OP4 E00C93 0 +OP4 E00C94 0 +OP4 E00C95 0 +OP4 E00C96 0 +OP4 E00C97 0 +OP4 E00C98 0 +OP4 E00C99 0 +OP4 E00C9A 0 +OP4 E00C9B 0 +OP4 E00C9C 0 +OP4 E00C9D 0 +OP4 E00C9E 0 +OP4 E00C9F 0 +OP4 E00CA0 0 +OP4 E00CA1 0 +OP4 E00CA2 0 +OP4 E00CA3 0 +OP4 E00CA4 0 +OP4 E00CA5 0 +OP4 E00CA6 0 +OP4 E00CA7 0 +OP4 E00CA8 0 +OP4 E00CA9 0 +OP4 E00CAA 0 +OP4 E00CAB 0 +OP4 E00CAC 0 +OP4 E00CAD 0 +OP4 E00CAE 0 +OP4 E00CAF 0 +OP4 E00CB0 0 +OP4 E00CB1 0 +OP4 E00CB2 0 +OP4 E00CB3 0 +OP4 E00CB4 0 +OP4 E00CB5 0 +OP4 E00CB6 0 +OP4 E00CB7 0 +OP4 E00CB8 0 +OP4 E00CB9 0 +OP4 E00CBA 0 +OP4 E00CBB 0 +OP4 E00CBC 0 +OP4 E00CBD 0 +OP4 E00CBE 0 +OP4 E00CBF 0 +OP4 E00CC0 0 +OP4 E00CC1 0 +OP4 E00CC2 0 +OP4 E00CC3 0 +OP4 E00CC4 0 +OP4 E00CC5 0 +OP4 E00CC6 0 +OP4 E00CC7 0 +OP4 E00CC8 0 +OP4 E00CC9 0 +OP4 E00CCA 0 +OP4 E00CCB 0 +OP4 E00CCC 0 +OP4 E00CCD 0 +OP4 E00CCE 0 +OP4 E00CCF 0 +OP4 E00CD0 0 +OP4 E00CD1 0 +OP4 E00CD2 0 +OP4 E00CD3 0 +OP4 E00CD4 0 +OP4 E00CD5 0 +OP4 E00CD6 0 +OP4 E00CD7 0 +OP4 E00CD8 0 +OP4 E00CD9 0 +OP4 E00CDA 0 +OP4 E00CDB 0 +OP4 E00CDC 0 +OP4 E00CDD 0 +OP4 E00CDE 0 +OP4 E00CDF 0 +OP4 E00CE0 0 +OP4 E00CE1 0 +OP4 E00CE2 0 +OP4 E00CE3 0 +OP4 E00CE4 0 +OP4 E00CE5 0 +OP4 E00CE6 0 +OP4 E00CE7 0 +OP4 E00CE8 0 +OP4 E00CE9 0 +OP4 E00CEA 0 +OP4 E00CEB 0 +OP4 E00CEC 0 +OP4 E00CED 0 +OP4 E00CEE 0 +OP4 E00CEF 0 +OP4 E00CF0 0 +OP4 E00CF1 0 +OP4 E00CF2 0 +OP4 E00CF3 0 +OP4 E00CF4 0 +OP4 E00CF5 0 +OP4 E00CF6 0 +OP4 E00CF7 0 +OP4 E00CF8 0 +OP4 E00CF9 0 +OP4 E00CFA 0 +OP4 E00CFB 0 +OP4 E00CFC 0 +OP4 E00CFD 0 +OP4 E00CFE 0 +OP4 E00CFF 0 +OP4 E00D00 0 +OP4 E00D01 0 +OP4 E00D02 0 +OP4 E00D03 0 +OP4 E00D04 0 +OP4 E00D05 0 +OP4 E00D06 0 +OP4 E00D07 0 +OP4 E00D08 0 +OP4 E00D09 0 +OP4 E00D0A 0 +OP4 E00D0B 0 +OP4 E00D0C 0 +OP4 E00D0D 0 +OP4 E00D0E 0 +OP4 E00D0F 0 +OP4 E00D10 0 +OP4 E00D11 0 +OP4 E00D12 0 +OP4 E00D13 0 +OP4 E00D14 0 +OP4 E00D15 0 +OP4 E00D16 0 +OP4 E00D17 0 +OP4 E00D18 0 +OP4 E00D19 0 +OP4 E00D1A 0 +OP4 E00D1B 0 +OP4 E00D1C 0 +OP4 E00D1D 0 +OP4 E00D1E 0 +OP4 E00D1F 0 +OP4 E00D20 0 +OP4 E00D21 0 +OP4 E00D22 0 +OP4 E00D23 0 +OP4 E00D24 0 +OP4 E00D25 0 +OP4 E00D26 0 +OP4 E00D27 0 +OP4 E00D28 0 +OP4 E00D29 0 +OP4 E00D2A 0 +OP4 E00D2B 0 +OP4 E00D2C 0 +OP4 E00D2D 0 +OP4 E00D2E 0 +OP4 E00D2F 0 +OP4 E00D30 0 +OP4 E00D31 0 +OP4 E00D32 0 +OP4 E00D33 0 +OP4 E00D34 0 +OP4 E00D35 0 +OP4 E00D36 0 +OP4 E00D37 0 +OP4 E00D38 0 +OP4 E00D39 0 +OP4 E00D3A 0 +OP4 E00D3B 0 +OP4 E00D3C 0 +OP4 E00D3D 0 +OP4 E00D3E 0 +OP4 E00D3F 0 +OP4 E00D40 0 +OP4 E00D41 0 +OP4 E00D42 0 +OP4 E00D43 0 +OP4 E00D44 0 +OP4 E00D45 0 +OP4 E00D46 0 +OP4 E00D47 0 +OP4 E00D48 0 +OP4 E00D49 0 +OP4 E00D4A 0 +OP4 E00D4B 0 +OP4 E00D4C 0 +OP4 E00D4D 0 +OP4 E00D4E 0 +OP4 E00D4F 0 +OP4 E00D50 0 +OP4 E00D51 0 +OP4 E00D52 0 +OP4 E00D53 0 +OP4 E00D54 0 +OP4 E00D55 0 +OP4 E00D56 0 +OP4 E00D57 0 +OP4 E00D58 0 +OP4 E00D59 0 +OP4 E00D5A 0 +OP4 E00D5B 0 +OP4 E00D5C 0 +OP4 E00D5D 0 +OP4 E00D5E 0 +OP4 E00D5F 0 +OP4 E00D60 0 +OP4 E00D61 0 +OP4 E00D62 0 +OP4 E00D63 0 +OP4 E00D64 0 +OP4 E00D65 0 +OP4 E00D66 0 +OP4 E00D67 0 +OP4 E00D68 0 +OP4 E00D69 0 +OP4 E00D6A 0 +OP4 E00D6B 0 +OP4 E00D6C 0 +OP4 E00D6D 0 +OP4 E00D6E 0 +OP4 E00D6F 0 +OP4 E00D70 0 +OP4 E00D71 0 +OP4 E00D72 0 +OP4 E00D73 0 +OP4 E00D74 0 +OP4 E00D75 0 +OP4 E00D76 0 +OP4 E00D77 0 +OP4 E00D78 0 +OP4 E00D79 0 +OP4 E00D7A 0 +OP4 E00D7B 0 +OP4 E00D7C 0 +OP4 E00D7D 0 +OP4 E00D7E 0 +OP4 E00D7F 0 +OP4 E00D80 0 +OP4 E00D81 0 +OP4 E00D82 0 +OP4 E00D83 0 +OP4 E00D84 0 +OP4 E00D85 0 +OP4 E00D86 0 +OP4 E00D87 0 +OP4 E00D88 0 +OP4 E00D89 0 +OP4 E00D8A 0 +OP4 E00D8B 0 +OP4 E00D8C 0 +OP4 E00D8D 0 +OP4 E00D8E 0 +OP4 E00D8F 0 +OP4 E00D90 0 +OP4 E00D91 0 +OP4 E00D92 0 +OP4 E00D93 0 +OP4 E00D94 0 +OP4 E00D95 0 +OP4 E00D96 0 +OP4 E00D97 0 +OP4 E00D98 0 +OP4 E00D99 0 +OP4 E00D9A 0 +OP4 E00D9B 0 +OP4 E00D9C 0 +OP4 E00D9D 0 +OP4 E00D9E 0 +OP4 E00D9F 0 +OP4 E00DA0 0 +OP4 E00DA1 0 +OP4 E00DA2 0 +OP4 E00DA3 0 +OP4 E00DA4 0 +OP4 E00DA5 0 +OP4 E00DA6 0 +OP4 E00DA7 0 +OP4 E00DA8 0 +OP4 E00DA9 0 +OP4 E00DAA 0 +OP4 E00DAB 0 +OP4 E00DAC 0 +OP4 E00DAD 0 +OP4 E00DAE 0 +OP4 E00DAF 0 +OP4 E00DB0 0 +OP4 E00DB1 0 +OP4 E00DB2 0 +OP4 E00DB3 0 +OP4 E00DB4 0 +OP4 E00DB5 0 +OP4 E00DB6 0 +OP4 E00DB7 0 +OP4 E00DB8 0 +OP4 E00DB9 0 +OP4 E00DBA 0 +OP4 E00DBB 0 +OP4 E00DBC 0 +OP4 E00DBD 0 +OP4 E00DBE 0 +OP4 E00DBF 0 +OP4 E00DC0 0 +OP4 E00DC1 0 +OP4 E00DC2 0 +OP4 E00DC3 0 +OP4 E00DC4 0 +OP4 E00DC5 0 +OP4 E00DC6 0 +OP4 E00DC7 0 +OP4 E00DC8 0 +OP4 E00DC9 0 +OP4 E00DCA 0 +OP4 E00DCB 0 +OP4 E00DCC 0 +OP4 E00DCD 0 +OP4 E00DCE 0 +OP4 E00DCF 0 +OP4 E00DD0 0 +OP4 E00DD1 0 +OP4 E00DD2 0 +OP4 E00DD3 0 +OP4 E00DD4 0 +OP4 E00DD5 0 +OP4 E00DD6 0 +OP4 E00DD7 0 +OP4 E00DD8 0 +OP4 E00DD9 0 +OP4 E00DDA 0 +OP4 E00DDB 0 +OP4 E00DDC 0 +OP4 E00DDD 0 +OP4 E00DDE 0 +OP4 E00DDF 0 +OP4 E00DE0 0 +OP4 E00DE1 0 +OP4 E00DE2 0 +OP4 E00DE3 0 +OP4 E00DE4 0 +OP4 E00DE5 0 +OP4 E00DE6 0 +OP4 E00DE7 0 +OP4 E00DE8 0 +OP4 E00DE9 0 +OP4 E00DEA 0 +OP4 E00DEB 0 +OP4 E00DEC 0 +OP4 E00DED 0 +OP4 E00DEE 0 +OP4 E00DEF 0 +OP4 E00DF0 0 +OP4 E00DF1 0 +OP4 E00DF2 0 +OP4 E00DF3 0 +OP4 E00DF4 0 +OP4 E00DF5 0 +OP4 E00DF6 0 +OP4 E00DF7 0 +OP4 E00DF8 0 +OP4 E00DF9 0 +OP4 E00DFA 0 +OP4 E00DFB 0 +OP4 E00DFC 0 +OP4 E00DFD 0 +OP4 E00DFE 0 +OP4 E00DFF 0 +OP4 E00E00 0 +OP4 E00E01 0 +OP4 E00E02 0 +OP4 E00E03 0 +OP4 E00E04 0 +OP4 E00E05 0 +OP4 E00E06 0 +OP4 E00E07 0 +OP4 E00E08 0 +OP4 E00E09 0 +OP4 E00E0A 0 +OP4 E00E0B 0 +OP4 E00E0C 0 +OP4 E00E0D 0 +OP4 E00E0E 0 +OP4 E00E0F 0 +OP4 E00E10 0 +OP4 E00E11 0 +OP4 E00E12 0 +OP4 E00E13 0 +OP4 E00E14 0 +OP4 E00E15 0 +OP4 E00E16 0 +OP4 E00E17 0 +OP4 E00E18 0 +OP4 E00E19 0 +OP4 E00E1A 0 +OP4 E00E1B 0 +OP4 E00E1C 0 +OP4 E00E1D 0 +OP4 E00E1E 0 +OP4 E00E1F 0 +OP4 E00E20 0 +OP4 E00E21 0 +OP4 E00E22 0 +OP4 E00E23 0 +OP4 E00E24 0 +OP4 E00E25 0 +OP4 E00E26 0 +OP4 E00E27 0 +OP4 E00E28 0 +OP4 E00E29 0 +OP4 E00E2A 0 +OP4 E00E2B 0 +OP4 E00E2C 0 +OP4 E00E2D 0 +OP4 E00E2E 0 +OP4 E00E2F 0 +OP4 E00E30 0 +OP4 E00E31 0 +OP4 E00E32 0 +OP4 E00E33 0 +OP4 E00E34 0 +OP4 E00E35 0 +OP4 E00E36 0 +OP4 E00E37 0 +OP4 E00E38 0 +OP4 E00E39 0 +OP4 E00E3A 0 +OP4 E00E3B 0 +OP4 E00E3C 0 +OP4 E00E3D 0 +OP4 E00E3E 0 +OP4 E00E3F 0 +OP4 E00E40 0 +OP4 E00E41 0 +OP4 E00E42 0 +OP4 E00E43 0 +OP4 E00E44 0 +OP4 E00E45 0 +OP4 E00E46 0 +OP4 E00E47 0 +OP4 E00E48 0 +OP4 E00E49 0 +OP4 E00E4A 0 +OP4 E00E4B 0 +OP4 E00E4C 0 +OP4 E00E4D 0 +OP4 E00E4E 0 +OP4 E00E4F 0 +OP4 E00E50 0 +OP4 E00E51 0 +OP4 E00E52 0 +OP4 E00E53 0 +OP4 E00E54 0 +OP4 E00E55 0 +OP4 E00E56 0 +OP4 E00E57 0 +OP4 E00E58 0 +OP4 E00E59 0 +OP4 E00E5A 0 +OP4 E00E5B 0 +OP4 E00E5C 0 +OP4 E00E5D 0 +OP4 E00E5E 0 +OP4 E00E5F 0 +OP4 E00E60 0 +OP4 E00E61 0 +OP4 E00E62 0 +OP4 E00E63 0 +OP4 E00E64 0 +OP4 E00E65 0 +OP4 E00E66 0 +OP4 E00E67 0 +OP4 E00E68 0 +OP4 E00E69 0 +OP4 E00E6A 0 +OP4 E00E6B 0 +OP4 E00E6C 0 +OP4 E00E6D 0 +OP4 E00E6E 0 +OP4 E00E6F 0 +OP4 E00E70 0 +OP4 E00E71 0 +OP4 E00E72 0 +OP4 E00E73 0 +OP4 E00E74 0 +OP4 E00E75 0 +OP4 E00E76 0 +OP4 E00E77 0 +OP4 E00E78 0 +OP4 E00E79 0 +OP4 E00E7A 0 +OP4 E00E7B 0 +OP4 E00E7C 0 +OP4 E00E7D 0 +OP4 E00E7E 0 +OP4 E00E7F 0 +OP4 E00E80 0 +OP4 E00E81 0 +OP4 E00E82 0 +OP4 E00E83 0 +OP4 E00E84 0 +OP4 E00E85 0 +OP4 E00E86 0 +OP4 E00E87 0 +OP4 E00E88 0 +OP4 E00E89 0 +OP4 E00E8A 0 +OP4 E00E8B 0 +OP4 E00E8C 0 +OP4 E00E8D 0 +OP4 E00E8E 0 +OP4 E00E8F 0 +OP4 E00E90 0 +OP4 E00E91 0 +OP4 E00E92 0 +OP4 E00E93 0 +OP4 E00E94 0 +OP4 E00E95 0 +OP4 E00E96 0 +OP4 E00E97 0 +OP4 E00E98 0 +OP4 E00E99 0 +OP4 E00E9A 0 +OP4 E00E9B 0 +OP4 E00E9C 0 +OP4 E00E9D 0 +OP4 E00E9E 0 +OP4 E00E9F 0 +OP4 E00EA0 0 +OP4 E00EA1 0 +OP4 E00EA2 0 +OP4 E00EA3 0 +OP4 E00EA4 0 +OP4 E00EA5 0 +OP4 E00EA6 0 +OP4 E00EA7 0 +OP4 E00EA8 0 +OP4 E00EA9 0 +OP4 E00EAA 0 +OP4 E00EAB 0 +OP4 E00EAC 0 +OP4 E00EAD 0 +OP4 E00EAE 0 +OP4 E00EAF 0 +OP4 E00EB0 0 +OP4 E00EB1 0 +OP4 E00EB2 0 +OP4 E00EB3 0 +OP4 E00EB4 0 +OP4 E00EB5 0 +OP4 E00EB6 0 +OP4 E00EB7 0 +OP4 E00EB8 0 +OP4 E00EB9 0 +OP4 E00EBA 0 +OP4 E00EBB 0 +OP4 E00EBC 0 +OP4 E00EBD 0 +OP4 E00EBE 0 +OP4 E00EBF 0 +OP4 E00EC0 0 +OP4 E00EC1 0 +OP4 E00EC2 0 +OP4 E00EC3 0 +OP4 E00EC4 0 +OP4 E00EC5 0 +OP4 E00EC6 0 +OP4 E00EC7 0 +OP4 E00EC8 0 +OP4 E00EC9 0 +OP4 E00ECA 0 +OP4 E00ECB 0 +OP4 E00ECC 0 +OP4 E00ECD 0 +OP4 E00ECE 0 +OP4 E00ECF 0 +OP4 E00ED0 0 +OP4 E00ED1 0 +OP4 E00ED2 0 +OP4 E00ED3 0 +OP4 E00ED4 0 +OP4 E00ED5 0 +OP4 E00ED6 0 +OP4 E00ED7 0 +OP4 E00ED8 0 +OP4 E00ED9 0 +OP4 E00EDA 0 +OP4 E00EDB 0 +OP4 E00EDC 0 +OP4 E00EDD 0 +OP4 E00EDE 0 +OP4 E00EDF 0 +OP4 E00EE0 0 +OP4 E00EE1 0 +OP4 E00EE2 0 +OP4 E00EE3 0 +OP4 E00EE4 0 +OP4 E00EE5 0 +OP4 E00EE6 0 +OP4 E00EE7 0 +OP4 E00EE8 0 +OP4 E00EE9 0 +OP4 E00EEA 0 +OP4 E00EEB 0 +OP4 E00EEC 0 +OP4 E00EED 0 +OP4 E00EEE 0 +OP4 E00EEF 0 +OP4 E00EF0 0 +OP4 E00EF1 0 +OP4 E00EF2 0 +OP4 E00EF3 0 +OP4 E00EF4 0 +OP4 E00EF5 0 +OP4 E00EF6 0 +OP4 E00EF7 0 +OP4 E00EF8 0 +OP4 E00EF9 0 +OP4 E00EFA 0 +OP4 E00EFB 0 +OP4 E00EFC 0 +OP4 E00EFD 0 +OP4 E00EFE 0 +OP4 E00EFF 0 +OP4 E00F00 0 +OP4 E00F01 0 +OP4 E00F02 0 +OP4 E00F03 0 +OP4 E00F04 0 +OP4 E00F05 0 +OP4 E00F06 0 +OP4 E00F07 0 +OP4 E00F08 0 +OP4 E00F09 0 +OP4 E00F0A 0 +OP4 E00F0B 0 +OP4 E00F0C 0 +OP4 E00F0D 0 +OP4 E00F0E 0 +OP4 E00F0F 0 +OP4 E00F10 0 +OP4 E00F11 0 +OP4 E00F12 0 +OP4 E00F13 0 +OP4 E00F14 0 +OP4 E00F15 0 +OP4 E00F16 0 +OP4 E00F17 0 +OP4 E00F18 0 +OP4 E00F19 0 +OP4 E00F1A 0 +OP4 E00F1B 0 +OP4 E00F1C 0 +OP4 E00F1D 0 +OP4 E00F1E 0 +OP4 E00F1F 0 +OP4 E00F20 0 +OP4 E00F21 0 +OP4 E00F22 0 +OP4 E00F23 0 +OP4 E00F24 0 +OP4 E00F25 0 +OP4 E00F26 0 +OP4 E00F27 0 +OP4 E00F28 0 +OP4 E00F29 0 +OP4 E00F2A 0 +OP4 E00F2B 0 +OP4 E00F2C 0 +OP4 E00F2D 0 +OP4 E00F2E 0 +OP4 E00F2F 0 +OP4 E00F30 0 +OP4 E00F31 0 +OP4 E00F32 0 +OP4 E00F33 0 +OP4 E00F34 0 +OP4 E00F35 0 +OP4 E00F36 0 +OP4 E00F37 0 +OP4 E00F38 0 +OP4 E00F39 0 +OP4 E00F3A 0 +OP4 E00F3B 0 +OP4 E00F3C 0 +OP4 E00F3D 0 +OP4 E00F3E 0 +OP4 E00F3F 0 +OP4 E00F40 0 +OP4 E00F41 0 +OP4 E00F42 0 +OP4 E00F43 0 +OP4 E00F44 0 +OP4 E00F45 0 +OP4 E00F46 0 +OP4 E00F47 0 +OP4 E00F48 0 +OP4 E00F49 0 +OP4 E00F4A 0 +OP4 E00F4B 0 +OP4 E00F4C 0 +OP4 E00F4D 0 +OP4 E00F4E 0 +OP4 E00F4F 0 +OP4 E00F50 0 +OP4 E00F51 0 +OP4 E00F52 0 +OP4 E00F53 0 +OP4 E00F54 0 +OP4 E00F55 0 +OP4 E00F56 0 +OP4 E00F57 0 +OP4 E00F58 0 +OP4 E00F59 0 +OP4 E00F5A 0 +OP4 E00F5B 0 +OP4 E00F5C 0 +OP4 E00F5D 0 +OP4 E00F5E 0 +OP4 E00F5F 0 +OP4 E00F60 0 +OP4 E00F61 0 +OP4 E00F62 0 +OP4 E00F63 0 +OP4 E00F64 0 +OP4 E00F65 0 +OP4 E00F66 0 +OP4 E00F67 0 +OP4 E00F68 0 +OP4 E00F69 0 +OP4 E00F6A 0 +OP4 E00F6B 0 +OP4 E00F6C 0 +OP4 E00F6D 0 +OP4 E00F6E 0 +OP4 E00F6F 0 +OP4 E00F70 0 +OP4 E00F71 0 +OP4 E00F72 0 +OP4 E00F73 0 +OP4 E00F74 0 +OP4 E00F75 0 +OP4 E00F76 0 +OP4 E00F77 0 +OP4 E00F78 0 +OP4 E00F79 0 +OP4 E00F7A 0 +OP4 E00F7B 0 +OP4 E00F7C 0 +OP4 E00F7D 0 +OP4 E00F7E 0 +OP4 E00F7F 0 +OP4 E00F80 0 +OP4 E00F81 0 +OP4 E00F82 0 +OP4 E00F83 0 +OP4 E00F84 0 +OP4 E00F85 0 +OP4 E00F86 0 +OP4 E00F87 0 +OP4 E00F88 0 +OP4 E00F89 0 +OP4 E00F8A 0 +OP4 E00F8B 0 +OP4 E00F8C 0 +OP4 E00F8D 0 +OP4 E00F8E 0 +OP4 E00F8F 0 +OP4 E00F90 0 +OP4 E00F91 0 +OP4 E00F92 0 +OP4 E00F93 0 +OP4 E00F94 0 +OP4 E00F95 0 +OP4 E00F96 0 +OP4 E00F97 0 +OP4 E00F98 0 +OP4 E00F99 0 +OP4 E00F9A 0 +OP4 E00F9B 0 +OP4 E00F9C 0 +OP4 E00F9D 0 +OP4 E00F9E 0 +OP4 E00F9F 0 +OP4 E00FA0 0 +OP4 E00FA1 0 +OP4 E00FA2 0 +OP4 E00FA3 0 +OP4 E00FA4 0 +OP4 E00FA5 0 +OP4 E00FA6 0 +OP4 E00FA7 0 +OP4 E00FA8 0 +OP4 E00FA9 0 +OP4 E00FAA 0 +OP4 E00FAB 0 +OP4 E00FAC 0 +OP4 E00FAD 0 +OP4 E00FAE 0 +OP4 E00FAF 0 +OP4 E00FB0 0 +OP4 E00FB1 0 +OP4 E00FB2 0 +OP4 E00FB3 0 +OP4 E00FB4 0 +OP4 E00FB5 0 +OP4 E00FB6 0 +OP4 E00FB7 0 +OP4 E00FB8 0 +OP4 E00FB9 0 +OP4 E00FBA 0 +OP4 E00FBB 0 +OP4 E00FBC 0 +OP4 E00FBD 0 +OP4 E00FBE 0 +OP4 E00FBF 0 +OP4 E00FC0 0 +OP4 E00FC1 0 +OP4 E00FC2 0 +OP4 E00FC3 0 +OP4 E00FC4 0 +OP4 E00FC5 0 +OP4 E00FC6 0 +OP4 E00FC7 0 +OP4 E00FC8 0 +OP4 E00FC9 0 +OP4 E00FCA 0 +OP4 E00FCB 0 +OP4 E00FCC 0 +OP4 E00FCD 0 +OP4 E00FCE 0 +OP4 E00FCF 0 +OP4 E00FD0 0 +OP4 E00FD1 0 +OP4 E00FD2 0 +OP4 E00FD3 0 +OP4 E00FD4 0 +OP4 E00FD5 0 +OP4 E00FD6 0 +OP4 E00FD7 0 +OP4 E00FD8 0 +OP4 E00FD9 0 +OP4 E00FDA 0 +OP4 E00FDB 0 +OP4 E00FDC 0 +OP4 E00FDD 0 +OP4 E00FDE 0 +OP4 E00FDF 0 +OP4 E00FE0 0 +OP4 E00FE1 0 +OP4 E00FE2 0 +OP4 E00FE3 0 +OP4 E00FE4 0 +OP4 E00FE5 0 +OP4 E00FE6 0 +OP4 E00FE7 0 +OP4 E00FE8 0 +OP4 E00FE9 0 +OP4 E00FEA 0 +OP4 E00FEB 0 +OP4 E00FEC 0 +OP4 E00FED 0 +OP4 E00FEE 0 +OP4 E00FEF 0 +OP4 E00FF0 0 +OP4 E00FF1 0 +OP4 E00FF2 0 +OP4 E00FF3 0 +OP4 E00FF4 0 +OP4 E00FF5 0 +OP4 E00FF6 0 +OP4 E00FF7 0 +OP4 E00FF8 0 +OP4 E00FF9 0 +OP4 E00FFA 0 +OP4 E00FFB 0 +OP4 E00FFC 0 +OP4 E00FFD 0 +OP4 E00FFE 0 +OP4 E00FFF 0 +OP4 E01000 0 +OP4 E01001 0 +OP4 E01002 0 +OP4 E01003 0 +OP4 E01004 0 +OP4 E01005 0 +OP4 E01006 0 +OP4 E01007 0 +OP4 E01008 0 +OP4 E01009 0 +OP4 E0100A 0 +OP4 E0100B 0 +OP4 E0100C 0 +OP4 E0100D 0 +OP4 E0100E 0 +OP4 E0100F 0 +OP4 E01010 0 +OP4 E01011 0 +OP4 E01012 0 +OP4 E01013 0 +OP4 E01014 0 +OP4 E01015 0 +OP4 E01016 0 +OP4 E01017 0 +OP4 E01018 0 +OP4 E01019 0 +OP4 E0101A 0 +OP4 E0101B 0 +OP4 E0101C 0 +OP4 E0101D 0 +OP4 E0101E 0 +OP4 E0101F 0 +OP4 E01020 0 +OP4 E01021 0 +OP4 E01022 0 +OP4 E01023 0 +OP4 E01024 0 +OP4 E01025 0 +OP4 E01026 0 +OP4 E01027 0 +OP4 E01028 0 +OP4 E01029 0 +OP4 E0102A 0 +OP4 E0102B 0 +OP4 E0102C 0 +OP4 E0102D 0 +OP4 E0102E 0 +OP4 E0102F 0 +OP4 E01030 0 +OP4 E01031 0 +OP4 E01032 0 +OP4 E01033 0 +OP4 E01034 0 +OP4 E01035 0 +OP4 E01036 0 +OP4 E01037 0 +OP4 E01038 0 +OP4 E01039 0 +OP4 E0103A 0 +OP4 E0103B 0 +OP4 E0103C 0 +OP4 E0103D 0 +OP4 E0103E 0 +OP4 E0103F 0 +OP4 E01040 0 +OP4 E01041 0 +OP4 E01042 0 +OP4 E01043 0 +OP4 E01044 0 +OP4 E01045 0 +OP4 E01046 0 +OP4 E01047 0 +OP4 E01048 0 +OP4 E01049 0 +OP4 E0104A 0 +OP4 E0104B 0 +OP4 E0104C 0 +OP4 E0104D 0 +OP4 E0104E 0 +OP4 E0104F 0 +OP4 E01050 0 +OP4 E01051 0 +OP4 E01052 0 +OP4 E01053 0 +OP4 E01054 0 +OP4 E01055 0 +OP4 E01056 0 +OP4 E01057 0 +OP4 E01058 0 +OP4 E01059 0 +OP4 E0105A 0 +OP4 E0105B 0 +OP4 E0105C 0 +OP4 E0105D 0 +OP4 E0105E 0 +OP4 E0105F 0 +OP4 E01060 0 +OP4 E01061 0 +OP4 E01062 0 +OP4 E01063 0 +OP4 E01064 0 +OP4 E01065 0 +OP4 E01066 0 +OP4 E01067 0 +OP4 E01068 0 +OP4 E01069 0 +OP4 E0106A 0 +OP4 E0106B 0 +OP4 E0106C 0 +OP4 E0106D 0 +OP4 E0106E 0 +OP4 E0106F 0 +OP4 E01070 0 +OP4 E01071 0 +OP4 E01072 0 +OP4 E01073 0 +OP4 E01074 0 +OP4 E01075 0 +OP4 E01076 0 +OP4 E01077 0 +OP4 E01078 0 +OP4 E01079 0 +OP4 E0107A 0 +OP4 E0107B 0 +OP4 E0107C 0 +OP4 E0107D 0 +OP4 E0107E 0 +OP4 E0107F 0 +OP4 E01080 0 +OP4 E01081 0 +OP4 E01082 0 +OP4 E01083 0 +OP4 E01084 0 +OP4 E01085 0 +OP4 E01086 0 +OP4 E01087 0 +OP4 E01088 0 +OP4 E01089 0 +OP4 E0108A 0 +OP4 E0108B 0 +OP4 E0108C 0 +OP4 E0108D 0 +OP4 E0108E 0 +OP4 E0108F 0 +OP4 E01090 0 +OP4 E01091 0 +OP4 E01092 0 +OP4 E01093 0 +OP4 E01094 0 +OP4 E01095 0 +OP4 E01096 0 +OP4 E01097 0 +OP4 E01098 0 +OP4 E01099 0 +OP4 E0109A 0 +OP4 E0109B 0 +OP4 E0109C 0 +OP4 E0109D 0 +OP4 E0109E 0 +OP4 E0109F 0 +OP4 E010A0 0 +OP4 E010A1 0 +OP4 E010A2 0 +OP4 E010A3 0 +OP4 E010A4 0 +OP4 E010A5 0 +OP4 E010A6 0 +OP4 E010A7 0 +OP4 E010A8 0 +OP4 E010A9 0 +OP4 E010AA 0 +OP4 E010AB 0 +OP4 E010AC 0 +OP4 E010AD 0 +OP4 E010AE 0 +OP4 E010AF 0 +OP4 E010B0 0 +OP4 E010B1 0 +OP4 E010B2 0 +OP4 E010B3 0 +OP4 E010B4 0 +OP4 E010B5 0 +OP4 E010B6 0 +OP4 E010B7 0 +OP4 E010B8 0 +OP4 E010B9 0 +OP4 E010BA 0 +OP4 E010BB 0 +OP4 E010BC 0 +OP4 E010BD 0 +OP4 E010BE 0 +OP4 E010BF 0 +OP4 E010C0 0 +OP4 E010C1 0 +OP4 E010C2 0 +OP4 E010C3 0 +OP4 E010C4 0 +OP4 E010C5 0 +OP4 E010C6 0 +OP4 E010C7 0 +OP4 E010C8 0 +OP4 E010C9 0 +OP4 E010CA 0 +OP4 E010CB 0 +OP4 E010CC 0 +OP4 E010CD 0 +OP4 E010CE 0 +OP4 E010CF 0 +OP4 E010D0 0 +OP4 E010D1 0 +OP4 E010D2 0 +OP4 E010D3 0 +OP4 E010D4 0 +OP4 E010D5 0 +OP4 E010D6 0 +OP4 E010D7 0 +OP4 E010D8 0 +OP4 E010D9 0 +OP4 E010DA 0 +OP4 E010DB 0 +OP4 E010DC 0 +OP4 E010DD 0 +OP4 E010DE 0 +OP4 E010DF 0 +OP4 E010E0 0 +OP4 E010E1 0 +OP4 E010E2 0 +OP4 E010E3 0 +OP4 E010E4 0 +OP4 E010E5 0 +OP4 E010E6 0 +OP4 E010E7 0 +OP4 E010E8 0 +OP4 E010E9 0 +OP4 E010EA 0 +OP4 E010EB 0 +OP4 E010EC 0 +OP4 E010ED 0 +OP4 E010EE 0 +OP4 E010EF 0 +OP4 E010F0 0 +OP4 E010F1 0 +OP4 E010F2 0 +OP4 E010F3 0 +OP4 E010F4 0 +OP4 E010F5 0 +OP4 E010F6 0 +OP4 E010F7 0 +OP4 E010F8 0 +OP4 E010F9 0 +OP4 E010FA 0 +OP4 E010FB 0 +OP4 E010FC 0 +OP4 E010FD 0 +OP4 E010FE 0 +OP4 E010FF 0 +OP4 E01100 0 +OP4 E01101 0 +OP4 E01102 0 +OP4 E01103 0 +OP4 E01104 0 +OP4 E01105 0 +OP4 E01106 0 +OP4 E01107 0 +OP4 E01108 0 +OP4 E01109 0 +OP4 E0110A 0 +OP4 E0110B 0 +OP4 E0110C 0 +OP4 E0110D 0 +OP4 E0110E 0 +OP4 E0110F 0 +OP4 E01110 0 +OP4 E01111 0 +OP4 E01112 0 +OP4 E01113 0 +OP4 E01114 0 +OP4 E01115 0 +OP4 E01116 0 +OP4 E01117 0 +OP4 E01118 0 +OP4 E01119 0 +OP4 E0111A 0 +OP4 E0111B 0 +OP4 E0111C 0 +OP4 E0111D 0 +OP4 E0111E 0 +OP4 E0111F 0 +OP4 E01120 0 +OP4 E01121 0 +OP4 E01122 0 +OP4 E01123 0 +OP4 E01124 0 +OP4 E01125 0 +OP4 E01126 0 +OP4 E01127 0 +OP4 E01128 0 +OP4 E01129 0 +OP4 E0112A 0 +OP4 E0112B 0 +OP4 E0112C 0 +OP4 E0112D 0 +OP4 E0112E 0 +OP4 E0112F 0 +OP4 E01130 0 +OP4 E01131 0 +OP4 E01132 0 +OP4 E01133 0 +OP4 E01134 0 +OP4 E01135 0 +OP4 E01136 0 +OP4 E01137 0 +OP4 E01138 0 +OP4 E01139 0 +OP4 E0113A 0 +OP4 E0113B 0 +OP4 E0113C 0 +OP4 E0113D 0 +OP4 E0113E 0 +OP4 E0113F 0 +OP4 E01140 0 +OP4 E01141 0 +OP4 E01142 0 +OP4 E01143 0 +OP4 E01144 0 +OP4 E01145 0 +OP4 E01146 0 +OP4 E01147 0 +OP4 E01148 0 +OP4 E01149 0 +OP4 E0114A 0 +OP4 E0114B 0 +OP4 E0114C 0 +OP4 E0114D 0 +OP4 E0114E 0 +OP4 E0114F 0 +OP4 E01150 0 +OP4 E01151 0 +OP4 E01152 0 +OP4 E01153 0 +OP4 E01154 0 +OP4 E01155 0 +OP4 E01156 0 +OP4 E01157 0 +OP4 E01158 0 +OP4 E01159 0 +OP4 E0115A 0 +OP4 E0115B 0 +OP4 E0115C 0 +OP4 E0115D 0 +OP4 E0115E 0 +OP4 E0115F 0 +OP4 E01160 0 +OP4 E01161 0 +OP4 E01162 0 +OP4 E01163 0 +OP4 E01164 0 +OP4 E01165 0 +OP4 E01166 0 +OP4 E01167 0 +OP4 E01168 0 +OP4 E01169 0 +OP4 E0116A 0 +OP4 E0116B 0 +OP4 E0116C 0 +OP4 E0116D 0 +OP4 E0116E 0 +OP4 E0116F 0 +OP4 E01170 0 +OP4 E01171 0 +OP4 E01172 0 +OP4 E01173 0 +OP4 E01174 0 +OP4 E01175 0 +OP4 E01176 0 +OP4 E01177 0 +OP4 E01178 0 +OP4 E01179 0 +OP4 E0117A 0 +OP4 E0117B 0 +OP4 E0117C 0 +OP4 E0117D 0 +OP4 E0117E 0 +OP4 E0117F 0 +OP4 E01180 0 +OP4 E01181 0 +OP4 E01182 0 +OP4 E01183 0 +OP4 E01184 0 +OP4 E01185 0 +OP4 E01186 0 +OP4 E01187 0 +OP4 E01188 0 +OP4 E01189 0 +OP4 E0118A 0 +OP4 E0118B 0 +OP4 E0118C 0 +OP4 E0118D 0 +OP4 E0118E 0 +OP4 E0118F 0 +OP4 E01190 0 +OP4 E01191 0 +OP4 E01192 0 +OP4 E01193 0 +OP4 E01194 0 +OP4 E01195 0 +OP4 E01196 0 +OP4 E01197 0 +OP4 E01198 0 +OP4 E01199 0 +OP4 E0119A 0 +OP4 E0119B 0 +OP4 E0119C 0 +OP4 E0119D 0 +OP4 E0119E 0 +OP4 E0119F 0 +OP4 E011A0 0 +OP4 E011A1 0 +OP4 E011A2 0 +OP4 E011A3 0 +OP4 E011A4 0 +OP4 E011A5 0 +OP4 E011A6 0 +OP4 E011A7 0 +OP4 E011A8 0 +OP4 E011A9 0 +OP4 E011AA 0 +OP4 E011AB 0 +OP4 E011AC 0 +OP4 E011AD 0 +OP4 E011AE 0 +OP4 E011AF 0 +OP4 E011B0 0 +OP4 E011B1 0 +OP4 E011B2 0 +OP4 E011B3 0 +OP4 E011B4 0 +OP4 E011B5 0 +OP4 E011B6 0 +OP4 E011B7 0 +OP4 E011B8 0 +OP4 E011B9 0 +OP4 E011BA 0 +OP4 E011BB 0 +OP4 E011BC 0 +OP4 E011BD 0 +OP4 E011BE 0 +OP4 E011BF 0 +OP4 E011C0 0 +OP4 E011C1 0 +OP4 E011C2 0 +OP4 E011C3 0 +OP4 E011C4 0 +OP4 E011C5 0 +OP4 E011C6 0 +OP4 E011C7 0 +OP4 E011C8 0 +OP4 E011C9 0 +OP4 E011CA 0 +OP4 E011CB 0 +OP4 E011CC 0 +OP4 E011CD 0 +OP4 E011CE 0 +OP4 E011CF 0 +OP4 E011D0 0 +OP4 E011D1 0 +OP4 E011D2 0 +OP4 E011D3 0 +OP4 E011D4 0 +OP4 E011D5 0 +OP4 E011D6 0 +OP4 E011D7 0 +OP4 E011D8 0 +OP4 E011D9 0 +OP4 E011DA 0 +OP4 E011DB 0 +OP4 E011DC 0 +OP4 E011DD 0 +OP4 E011DE 0 +OP4 E011DF 0 +OP4 E011E0 0 +OP4 E011E1 0 +OP4 E011E2 0 +OP4 E011E3 0 +OP4 E011E4 0 +OP4 E011E5 0 +OP4 E011E6 0 +OP4 E011E7 0 +OP4 E011E8 0 +OP4 E011E9 0 +OP4 E011EA 0 +OP4 E011EB 0 +OP4 E011EC 0 +OP4 E011ED 0 +OP4 E011EE 0 +OP4 E011EF 0 +OP4 E011F0 0 +OP4 E011F1 0 +OP4 E011F2 0 +OP4 E011F3 0 +OP4 E011F4 0 +OP4 E011F5 0 +OP4 E011F6 0 +OP4 E011F7 0 +OP4 E011F8 0 +OP4 E011F9 0 +OP4 E011FA 0 +OP4 E011FB 0 +OP4 E011FC 0 +OP4 E011FD 0 +OP4 E011FE 0 +OP4 E011FF 0 +OP4 E01200 0 +OP4 E01201 0 +OP4 E01202 0 +OP4 E01203 0 +OP4 E01204 0 +OP4 E01205 0 +OP4 E01206 0 +OP4 E01207 0 +OP4 E01208 0 +OP4 E01209 0 +OP4 E0120A 0 +OP4 E0120B 0 +OP4 E0120C 0 +OP4 E0120D 0 +OP4 E0120E 0 +OP4 E0120F 0 +OP4 E01210 0 +OP4 E01211 0 +OP4 E01212 0 +OP4 E01213 0 +OP4 E01214 0 +OP4 E01215 0 +OP4 E01216 0 +OP4 E01217 0 +OP4 E01218 0 +OP4 E01219 0 +OP4 E0121A 0 +OP4 E0121B 0 +OP4 E0121C 0 +OP4 E0121D 0 +OP4 E0121E 0 +OP4 E0121F 0 +OP4 E01220 0 +OP4 E01221 0 +OP4 E01222 0 +OP4 E01223 0 +OP4 E01224 0 +OP4 E01225 0 +OP4 E01226 0 +OP4 E01227 0 +OP4 E01228 0 +OP4 E01229 0 +OP4 E0122A 0 +OP4 E0122B 0 +OP4 E0122C 0 +OP4 E0122D 0 +OP4 E0122E 0 +OP4 E0122F 0 +OP4 E01230 0 +OP4 E01231 0 +OP4 E01232 0 +OP4 E01233 0 +OP4 E01234 0 +OP4 E01235 0 +OP4 E01236 0 +OP4 E01237 0 +OP4 E01238 0 +OP4 E01239 0 +OP4 E0123A 0 +OP4 E0123B 0 +OP4 E0123C 0 +OP4 E0123D 0 +OP4 E0123E 0 +OP4 E0123F 0 +OP4 E01240 0 +OP4 E01241 0 +OP4 E01242 0 +OP4 E01243 0 +OP4 E01244 0 +OP4 E01245 0 +OP4 E01246 0 +OP4 E01247 0 +OP4 E01248 0 +OP4 E01249 0 +OP4 E0124A 0 +OP4 E0124B 0 +OP4 E0124C 0 +OP4 E0124D 0 +OP4 E0124E 0 +OP4 E0124F 0 +OP4 E01250 0 +OP4 E01251 0 +OP4 E01252 0 +OP4 E01253 0 +OP4 E01254 0 +OP4 E01255 0 +OP4 E01256 0 +OP4 E01257 0 +OP4 E01258 0 +OP4 E01259 0 +OP4 E0125A 0 +OP4 E0125B 0 +OP4 E0125C 0 +OP4 E0125D 0 +OP4 E0125E 0 +OP4 E0125F 0 +OP4 E01260 0 +OP4 E01261 0 +OP4 E01262 0 +OP4 E01263 0 +OP4 E01264 0 +OP4 E01265 0 +OP4 E01266 0 +OP4 E01267 0 +OP4 E01268 0 +OP4 E01269 0 +OP4 E0126A 0 +OP4 E0126B 0 +OP4 E0126C 0 +OP4 E0126D 0 +OP4 E0126E 0 +OP4 E0126F 0 +OP4 E01270 0 +OP4 E01271 0 +OP4 E01272 0 +OP4 E01273 0 +OP4 E01274 0 +OP4 E01275 0 +OP4 E01276 0 +OP4 E01277 0 +OP4 E01278 0 +OP4 E01279 0 +OP4 E0127A 0 +OP4 E0127B 0 +OP4 E0127C 0 +OP4 E0127D 0 +OP4 E0127E 0 +OP4 E0127F 0 +OP4 E01280 0 +OP4 E01281 0 +OP4 E01282 0 +OP4 E01283 0 +OP4 E01284 0 +OP4 E01285 0 +OP4 E01286 0 +OP4 E01287 0 +OP4 E01288 0 +OP4 E01289 0 +OP4 E0128A 0 +OP4 E0128B 0 +OP4 E0128C 0 +OP4 E0128D 0 +OP4 E0128E 0 +OP4 E0128F 0 +OP4 E01290 0 +OP4 E01291 0 +OP4 E01292 0 +OP4 E01293 0 +OP4 E01294 0 +OP4 E01295 0 +OP4 E01296 0 +OP4 E01297 0 +OP4 E01298 0 +OP4 E01299 0 +OP4 E0129A 0 +OP4 E0129B 0 +OP4 E0129C 0 +OP4 E0129D 0 +OP4 E0129E 0 +OP4 E0129F 0 +OP4 E012A0 0 +OP4 E012A1 0 +OP4 E012A2 0 +OP4 E012A3 0 +OP4 E012A4 0 +OP4 E012A5 0 +OP4 E012A6 0 +OP4 E012A7 0 +OP4 E012A8 0 +OP4 E012A9 0 +OP4 E012AA 0 +OP4 E012AB 0 +OP4 E012AC 0 +OP4 E012AD 0 +OP4 E012AE 0 +OP4 E012AF 0 +OP4 E012B0 0 +OP4 E012B1 0 +OP4 E012B2 0 +OP4 E012B3 0 +OP4 E012B4 0 +OP4 E012B5 0 +OP4 E012B6 0 +OP4 E012B7 0 +OP4 E012B8 0 +OP4 E012B9 0 +OP4 E012BA 0 +OP4 E012BB 0 +OP4 E012BC 0 +OP4 E012BD 0 +OP4 E012BE 0 +OP4 E012BF 0 +OP4 E012C0 0 +OP4 E012C1 0 +OP4 E012C2 0 +OP4 E012C3 0 +OP4 E012C4 0 +OP4 E012C5 0 +OP4 E012C6 0 +OP4 E012C7 0 +OP4 E012C8 0 +OP4 E012C9 0 +OP4 E012CA 0 +OP4 E012CB 0 +OP4 E012CC 0 +OP4 E012CD 0 +OP4 E012CE 0 +OP4 E012CF 0 +OP4 E012D0 0 +OP4 E012D1 0 +OP4 E012D2 0 +OP4 E012D3 0 +OP4 E012D4 0 +OP4 E012D5 0 +OP4 E012D6 0 +OP4 E012D7 0 +OP4 E012D8 0 +OP4 E012D9 0 +OP4 E012DA 0 +OP4 E012DB 0 +OP4 E012DC 0 +OP4 E012DD 0 +OP4 E012DE 0 +OP4 E012DF 0 +OP4 E012E0 0 +OP4 E012E1 0 +OP4 E012E2 0 +OP4 E012E3 0 +OP4 E012E4 0 +OP4 E012E5 0 +OP4 E012E6 0 +OP4 E012E7 0 +OP4 E012E8 0 +OP4 E012E9 0 +OP4 E012EA 0 +OP4 E012EB 0 +OP4 E012EC 0 +OP4 E012ED 0 +OP4 E012EE 0 +OP4 E012EF 0 +OP4 E012F0 0 +OP4 E012F1 0 +OP4 E012F2 0 +OP4 E012F3 0 +OP4 E012F4 0 +OP4 E012F5 0 +OP4 E012F6 0 +OP4 E012F7 0 +OP4 E012F8 0 +OP4 E012F9 0 +OP4 E012FA 0 +OP4 E012FB 0 +OP4 E012FC 0 +OP4 E012FD 0 +OP4 E012FE 0 +OP4 E012FF 0 +OP4 E01300 0 +OP4 E01301 0 +OP4 E01302 0 +OP4 E01303 0 +OP4 E01304 0 +OP4 E01305 0 +OP4 E01306 0 +OP4 E01307 0 +OP4 E01308 0 +OP4 E01309 0 +OP4 E0130A 0 +OP4 E0130B 0 +OP4 E0130C 0 +OP4 E0130D 0 +OP4 E0130E 0 +OP4 E0130F 0 +OP4 E01310 0 +OP4 E01311 0 +OP4 E01312 0 +OP4 E01313 0 +OP4 E01314 0 +OP4 E01315 0 +OP4 E01316 0 +OP4 E01317 0 +OP4 E01318 0 +OP4 E01319 0 +OP4 E0131A 0 +OP4 E0131B 0 +OP4 E0131C 0 +OP4 E0131D 0 +OP4 E0131E 0 +OP4 E0131F 0 +OP4 E01320 0 +OP4 E01321 0 +OP4 E01322 0 +OP4 E01323 0 +OP4 E01324 0 +OP4 E01325 0 +OP4 E01326 0 +OP4 E01327 0 +OP4 E01328 0 +OP4 E01329 0 +OP4 E0132A 0 +OP4 E0132B 0 +OP4 E0132C 0 +OP4 E0132D 0 +OP4 E0132E 0 +OP4 E0132F 0 +OP4 E01330 0 +OP4 E01331 0 +OP4 E01332 0 +OP4 E01333 0 +OP4 E01334 0 +OP4 E01335 0 +OP4 E01336 0 +OP4 E01337 0 +OP4 E01338 0 +OP4 E01339 0 +OP4 E0133A 0 +OP4 E0133B 0 +OP4 E0133C 0 +OP4 E0133D 0 +OP4 E0133E 0 +OP4 E0133F 0 +OP4 E01340 0 +OP4 E01341 0 +OP4 E01342 0 +OP4 E01343 0 +OP4 E01344 0 +OP4 E01345 0 +OP4 E01346 0 +OP4 E01347 0 +OP4 E01348 0 +OP4 E01349 0 +OP4 E0134A 0 +OP4 E0134B 0 +OP4 E0134C 0 +OP4 E0134D 0 +OP4 E0134E 0 +OP4 E0134F 0 +OP4 E01350 0 +OP4 E01351 0 +OP4 E01352 0 +OP4 E01353 0 +OP4 E01354 0 +OP4 E01355 0 +OP4 E01356 0 +OP4 E01357 0 +OP4 E01358 0 +OP4 E01359 0 +OP4 E0135A 0 +OP4 E0135B 0 +OP4 E0135C 0 +OP4 E0135D 0 +OP4 E0135E 0 +OP4 E0135F 0 +OP4 E01360 0 +OP4 E01361 0 +OP4 E01362 0 +OP4 E01363 0 +OP4 E01364 0 +OP4 E01365 0 +OP4 E01366 0 +OP4 E01367 0 +OP4 E01368 0 +OP4 E01369 0 +OP4 E0136A 0 +OP4 E0136B 0 +OP4 E0136C 0 +OP4 E0136D 0 +OP4 E0136E 0 +OP4 E0136F 0 +OP4 E01370 0 +OP4 E01371 0 +OP4 E01372 0 +OP4 E01373 0 +OP4 E01374 0 +OP4 E01375 0 +OP4 E01376 0 +OP4 E01377 0 +OP4 E01378 0 +OP4 E01379 0 +OP4 E0137A 0 +OP4 E0137B 0 +OP4 E0137C 0 +OP4 E0137D 0 +OP4 E0137E 0 +OP4 E0137F 0 +OP4 E01380 0 +OP4 E01381 0 +OP4 E01382 0 +OP4 E01383 0 +OP4 E01384 0 +OP4 E01385 0 +OP4 E01386 0 +OP4 E01387 0 +OP4 E01388 0 +OP4 E01389 0 +OP4 E0138A 0 +OP4 E0138B 0 +OP4 E0138C 0 +OP4 E0138D 0 +OP4 E0138E 0 +OP4 E0138F 0 +OP4 E01390 0 +OP4 E01391 0 +OP4 E01392 0 +OP4 E01393 0 +OP4 E01394 0 +OP4 E01395 0 +OP4 E01396 0 +OP4 E01397 0 +OP4 E01398 0 +OP4 E01399 0 +OP4 E0139A 0 +OP4 E0139B 0 +OP4 E0139C 0 +OP4 E0139D 0 +OP4 E0139E 0 +OP4 E0139F 0 +OP4 E013A0 0 +OP4 E013A1 0 +OP4 E013A2 0 +OP4 E013A3 0 +OP4 E013A4 0 +OP4 E013A5 0 +OP4 E013A6 0 +OP4 E013A7 0 +OP4 E013A8 0 +OP4 E013A9 0 +OP4 E013AA 0 +OP4 E013AB 0 +OP4 E013AC 0 +OP4 E013AD 0 +OP4 E013AE 0 +OP4 E013AF 0 +OP4 E013B0 0 +OP4 E013B1 0 +OP4 E013B2 0 +OP4 E013B3 0 +OP4 E013B4 0 +OP4 E013B5 0 +OP4 E013B6 0 +OP4 E013B7 0 +OP4 E013B8 0 +OP4 E013B9 0 +OP4 E013BA 0 +OP4 E013BB 0 +OP4 E013BC 0 +OP4 E013BD 0 +OP4 E013BE 0 +OP4 E013BF 0 +OP4 E013C0 0 +OP4 E013C1 0 +OP4 E013C2 0 +OP4 E013C3 0 +OP4 E013C4 0 +OP4 E013C5 0 +OP4 E013C6 0 +OP4 E013C7 0 +OP4 E013C8 0 +OP4 E013C9 0 +OP4 E013CA 0 +OP4 E013CB 0 +OP4 E013CC 0 +OP4 E013CD 0 +OP4 E013CE 0 +OP4 E013CF 0 +OP4 E013D0 0 +OP4 E013D1 0 +OP4 E013D2 0 +OP4 E013D3 0 +OP4 E013D4 0 +OP4 E013D5 0 +OP4 E013D6 0 +OP4 E013D7 0 +OP4 E013D8 0 +OP4 E013D9 0 +OP4 E013DA 0 +OP4 E013DB 0 +OP4 E013DC 0 +OP4 E013DD 0 +OP4 E013DE 0 +OP4 E013DF 0 +OP4 E013E0 0 +OP4 E013E1 0 +OP4 E013E2 0 +OP4 E013E3 0 +OP4 E013E4 0 +OP4 E013E5 0 +OP4 E013E6 0 +OP4 E013E7 0 +OP4 E013E8 0 +OP4 E013E9 0 +OP4 E013EA 0 +OP4 E013EB 0 +OP4 E013EC 0 +OP4 E013ED 0 +OP4 E013EE 0 +OP4 E013EF 0 +OP4 E013F0 0 +OP4 E013F1 0 +OP4 E013F2 0 +OP4 E013F3 0 +OP4 E013F4 0 +OP4 E013F5 0 +OP4 E013F6 0 +OP4 E013F7 0 +OP4 E013F8 0 +OP4 E013F9 0 +OP4 E013FA 0 +OP4 E013FB 0 +OP4 E013FC 0 +OP4 E013FD 0 +OP4 E013FE 0 +OP4 E013FF 0 +OP4 E01400 0 +OP4 E01401 0 +OP4 E01402 0 +OP4 E01403 0 +OP4 E01404 0 +OP4 E01405 0 +OP4 E01406 0 +OP4 E01407 0 +OP4 E01408 0 +OP4 E01409 0 +OP4 E0140A 0 +OP4 E0140B 0 +OP4 E0140C 0 +OP4 E0140D 0 +OP4 E0140E 0 +OP4 E0140F 0 +OP4 E01410 0 +OP4 E01411 0 +OP4 E01412 0 +OP4 E01413 0 +OP4 E01414 0 +OP4 E01415 0 +OP4 E01416 0 +OP4 E01417 0 +OP4 E01418 0 +OP4 E01419 0 +OP4 E0141A 0 +OP4 E0141B 0 +OP4 E0141C 0 +OP4 E0141D 0 +OP4 E0141E 0 +OP4 E0141F 0 +OP4 E01420 0 +OP4 E01421 0 +OP4 E01422 0 +OP4 E01423 0 +OP4 E01424 0 +OP4 E01425 0 +OP4 E01426 0 +OP4 E01427 0 +OP4 E01428 0 +OP4 E01429 0 +OP4 E0142A 0 +OP4 E0142B 0 +OP4 E0142C 0 +OP4 E0142D 0 +OP4 E0142E 0 +OP4 E0142F 0 +OP4 E01430 0 +OP4 E01431 0 +OP4 E01432 0 +OP4 E01433 0 +OP4 E01434 0 +OP4 E01435 0 +OP4 E01436 0 +OP4 E01437 0 +OP4 E01438 0 +OP4 E01439 0 +OP4 E0143A 0 +OP4 E0143B 0 +OP4 E0143C 0 +OP4 E0143D 0 +OP4 E0143E 0 +OP4 E0143F 0 +OP4 E01440 0 +OP4 E01441 0 +OP4 E01442 0 +OP4 E01443 0 +OP4 E01444 0 +OP4 E01445 0 +OP4 E01446 0 +OP4 E01447 0 +OP4 E01448 0 +OP4 E01449 0 +OP4 E0144A 0 +OP4 E0144B 0 +OP4 E0144C 0 +OP4 E0144D 0 +OP4 E0144E 0 +OP4 E0144F 0 +OP4 E01450 0 +OP4 E01451 0 +OP4 E01452 0 +OP4 E01453 0 +OP4 E01454 0 +OP4 E01455 0 +OP4 E01456 0 +OP4 E01457 0 +OP4 E01458 0 +OP4 E01459 0 +OP4 E0145A 0 +OP4 E0145B 0 +OP4 E0145C 0 +OP4 E0145D 0 +OP4 E0145E 0 +OP4 E0145F 0 +OP4 E01460 0 +OP4 E01461 0 +OP4 E01462 0 +OP4 E01463 0 +OP4 E01464 0 +OP4 E01465 0 +OP4 E01466 0 +OP4 E01467 0 +OP4 E01468 0 +OP4 E01469 0 +OP4 E0146A 0 +OP4 E0146B 0 +OP4 E0146C 0 +OP4 E0146D 0 +OP4 E0146E 0 +OP4 E0146F 0 +OP4 E01470 0 +OP4 E01471 0 +OP4 E01472 0 +OP4 E01473 0 +OP4 E01474 0 +OP4 E01475 0 +OP4 E01476 0 +OP4 E01477 0 +OP4 E01478 0 +OP4 E01479 0 +OP4 E0147A 0 +OP4 E0147B 0 +OP4 E0147C 0 +OP4 E0147D 0 +OP4 E0147E 0 +OP4 E0147F 0 +OP4 E01480 0 +OP4 E01481 0 +OP4 E01482 0 +OP4 E01483 0 +OP4 E01484 0 +OP4 E01485 0 +OP4 E01486 0 +OP4 E01487 0 +OP4 E01488 0 +OP4 E01489 0 +OP4 E0148A 0 +OP4 E0148B 0 +OP4 E0148C 0 +OP4 E0148D 0 +OP4 E0148E 0 +OP4 E0148F 0 +OP4 E01490 0 +OP4 E01491 0 +OP4 E01492 0 +OP4 E01493 0 +OP4 E01494 0 +OP4 E01495 0 +OP4 E01496 0 +OP4 E01497 0 +OP4 E01498 0 +OP4 E01499 0 +OP4 E0149A 0 +OP4 E0149B 0 +OP4 E0149C 0 +OP4 E0149D 0 +OP4 E0149E 0 +OP4 E0149F 0 +OP4 E014A0 0 +OP4 E014A1 0 +OP4 E014A2 0 +OP4 E014A3 0 +OP4 E014A4 0 +OP4 E014A5 0 +OP4 E014A6 0 +OP4 E014A7 0 +OP4 E014A8 0 +OP4 E014A9 0 +OP4 E014AA 0 +OP4 E014AB 0 +OP4 E014AC 0 +OP4 E014AD 0 +OP4 E014AE 0 +OP4 E014AF 0 +OP4 E014B0 0 +OP4 E014B1 0 +OP4 E014B2 0 +OP4 E014B3 0 +OP4 E014B4 0 +OP4 E014B5 0 +OP4 E014B6 0 +OP4 E014B7 0 +OP4 E014B8 0 +OP4 E014B9 0 +OP4 E014BA 0 +OP4 E014BB 0 +OP4 E014BC 0 +OP4 E014BD 0 +OP4 E014BE 0 +OP4 E014BF 0 +OP4 E014C0 0 +OP4 E014C1 0 +OP4 E014C2 0 +OP4 E014C3 0 +OP4 E014C4 0 +OP4 E014C5 0 +OP4 E014C6 0 +OP4 E014C7 0 +OP4 E014C8 0 +OP4 E014C9 0 +OP4 E014CA 0 +OP4 E014CB 0 +OP4 E014CC 0 +OP4 E014CD 0 +OP4 E014CE 0 +OP4 E014CF 0 +OP4 E014D0 0 +OP4 E014D1 0 +OP4 E014D2 0 +OP4 E014D3 0 +OP4 E014D4 0 +OP4 E014D5 0 +OP4 E014D6 0 +OP4 E014D7 0 +OP4 E014D8 0 +OP4 E014D9 0 +OP4 E014DA 0 +OP4 E014DB 0 +OP4 E014DC 0 +OP4 E014DD 0 +OP4 E014DE 0 +OP4 E014DF 0 +OP4 E014E0 0 +OP4 E014E1 0 +OP4 E014E2 0 +OP4 E014E3 0 +OP4 E014E4 0 +OP4 E014E5 0 +OP4 E014E6 0 +OP4 E014E7 0 +OP4 E014E8 0 +OP4 E014E9 0 +OP4 E014EA 0 +OP4 E014EB 0 +OP4 E014EC 0 +OP4 E014ED 0 +OP4 E014EE 0 +OP4 E014EF 0 +OP4 E014F0 0 +OP4 E014F1 0 +OP4 E014F2 0 +OP4 E014F3 0 +OP4 E014F4 0 +OP4 E014F5 0 +OP4 E014F6 0 +OP4 E014F7 0 +OP4 E014F8 0 +OP4 E014F9 0 +OP4 E014FA 0 +OP4 E014FB 0 +OP4 E014FC 0 +OP4 E014FD 0 +OP4 E014FE 0 +OP4 E014FF 0 +OP4 E01500 0 +OP4 E01501 0 +OP4 E01502 0 +OP4 E01503 0 +OP4 E01504 0 +OP4 E01505 0 +OP4 E01506 0 +OP4 E01507 0 +OP4 E01508 0 +OP4 E01509 0 +OP4 E0150A 0 +OP4 E0150B 0 +OP4 E0150C 0 +OP4 E0150D 0 +OP4 E0150E 0 +OP4 E0150F 0 +OP4 E01510 0 +OP4 E01511 0 +OP4 E01512 0 +OP4 E01513 0 +OP4 E01514 0 +OP4 E01515 0 +OP4 E01516 0 +OP4 E01517 0 +OP4 E01518 0 +OP4 E01519 0 +OP4 E0151A 0 +OP4 E0151B 0 +OP4 E0151C 0 +OP4 E0151D 0 +OP4 E0151E 0 +OP4 E0151F 0 +OP4 E01520 0 +OP4 E01521 0 +OP4 E01522 0 +OP4 E01523 0 +OP4 E01524 0 +OP4 E01525 0 +OP4 E01526 0 +OP4 E01527 0 +OP4 E01528 0 +OP4 E01529 0 +OP4 E0152A 0 +OP4 E0152B 0 +OP4 E0152C 0 +OP4 E0152D 0 +OP4 E0152E 0 +OP4 E0152F 0 +OP4 E01530 0 +OP4 E01531 0 +OP4 E01532 0 +OP4 E01533 0 +OP4 E01534 0 +OP4 E01535 0 +OP4 E01536 0 +OP4 E01537 0 +OP4 E01538 0 +OP4 E01539 0 +OP4 E0153A 0 +OP4 E0153B 0 +OP4 E0153C 0 +OP4 E0153D 0 +OP4 E0153E 0 +OP4 E0153F 0 +OP4 E01540 0 +OP4 E01541 0 +OP4 E01542 0 +OP4 E01543 0 +OP4 E01544 0 +OP4 E01545 0 +OP4 E01546 0 +OP4 E01547 0 +OP4 E01548 0 +OP4 E01549 0 +OP4 E0154A 0 +OP4 E0154B 0 +OP4 E0154C 0 +OP4 E0154D 0 +OP4 E0154E 0 +OP4 E0154F 0 +OP4 E01550 0 +OP4 E01551 0 +OP4 E01552 0 +OP4 E01553 0 +OP4 E01554 0 +OP4 E01555 0 +OP4 E01556 0 +OP4 E01557 0 +OP4 E01558 0 +OP4 E01559 0 +OP4 E0155A 0 +OP4 E0155B 0 +OP4 E0155C 0 +OP4 E0155D 0 +OP4 E0155E 0 +OP4 E0155F 0 +OP4 E01560 0 +OP4 E01561 0 +OP4 E01562 0 +OP4 E01563 0 +OP4 E01564 0 +OP4 E01565 0 +OP4 E01566 0 +OP4 E01567 0 +OP4 E01568 0 +OP4 E01569 0 +OP4 E0156A 0 +OP4 E0156B 0 +OP4 E0156C 0 +OP4 E0156D 0 +OP4 E0156E 0 +OP4 E0156F 0 +OP4 E01570 0 +OP4 E01571 0 +OP4 E01572 0 +OP4 E01573 0 +OP4 E01574 0 +OP4 E01575 0 +OP4 E01576 0 +OP4 E01577 0 +OP4 E01578 0 +OP4 E01579 0 +OP4 E0157A 0 +OP4 E0157B 0 +OP4 E0157C 0 +OP4 E0157D 0 +OP4 E0157E 0 +OP4 E0157F 0 +OP4 E01580 0 +OP4 E01581 0 +OP4 E01582 0 +OP4 E01583 0 +OP4 E01584 0 +OP4 E01585 0 +OP4 E01586 0 +OP4 E01587 0 +OP4 E01588 0 +OP4 E01589 0 +OP4 E0158A 0 +OP4 E0158B 0 +OP4 E0158C 0 +OP4 E0158D 0 +OP4 E0158E 0 +OP4 E0158F 0 +OP4 E01590 0 +OP4 E01591 0 +OP4 E01592 0 +OP4 E01593 0 +OP4 E01594 0 +OP4 E01595 0 +OP4 E01596 0 +OP4 E01597 0 +OP4 E01598 0 +OP4 E01599 0 +OP4 E0159A 0 +OP4 E0159B 0 +OP4 E0159C 0 +OP4 E0159D 0 +OP4 E0159E 0 +OP4 E0159F 0 +OP4 E015A0 0 +OP4 E015A1 0 +OP4 E015A2 0 +OP4 E015A3 0 +OP4 E015A4 0 +OP4 E015A5 0 +OP4 E015A6 0 +OP4 E015A7 0 +OP4 E015A8 0 +OP4 E015A9 0 +OP4 E015AA 0 +OP4 E015AB 0 +OP4 E015AC 0 +OP4 E015AD 0 +OP4 E015AE 0 +OP4 E015AF 0 +OP4 E015B0 0 +OP4 E015B1 0 +OP4 E015B2 0 +OP4 E015B3 0 +OP4 E015B4 0 +OP4 E015B5 0 +OP4 E015B6 0 +OP4 E015B7 0 +OP4 E015B8 0 +OP4 E015B9 0 +OP4 E015BA 0 +OP4 E015BB 0 +OP4 E015BC 0 +OP4 E015BD 0 +OP4 E015BE 0 +OP4 E015BF 0 +OP4 E015C0 0 +OP4 E015C1 0 +OP4 E015C2 0 +OP4 E015C3 0 +OP4 E015C4 0 +OP4 E015C5 0 +OP4 E015C6 0 +OP4 E015C7 0 +OP4 E015C8 0 +OP4 E015C9 0 +OP4 E015CA 0 +OP4 E015CB 0 +OP4 E015CC 0 +OP4 E015CD 0 +OP4 E015CE 0 +OP4 E015CF 0 +OP4 E015D0 0 +OP4 E015D1 0 +OP4 E015D2 0 +OP4 E015D3 0 +OP4 E015D4 0 +OP4 E015D5 0 +OP4 E015D6 0 +OP4 E015D7 0 +OP4 E015D8 0 +OP4 E015D9 0 +OP4 E015DA 0 +OP4 E015DB 0 +OP4 E015DC 0 +OP4 E015DD 0 +OP4 E015DE 0 +OP4 E015DF 0 +OP4 E015E0 0 +OP4 E015E1 0 +OP4 E015E2 0 +OP4 E015E3 0 +OP4 E015E4 0 +OP4 E015E5 0 +OP4 E015E6 0 +OP4 E015E7 0 +OP4 E015E8 0 +OP4 E015E9 0 +OP4 E015EA 0 +OP4 E015EB 0 +OP4 E015EC 0 +OP4 E015ED 0 +OP4 E015EE 0 +OP4 E015EF 0 +OP4 E015F0 0 +OP4 E015F1 0 +OP4 E015F2 0 +OP4 E015F3 0 +OP4 E015F4 0 +OP4 E015F5 0 +OP4 E015F6 0 +OP4 E015F7 0 +OP4 E015F8 0 +OP4 E015F9 0 +OP4 E015FA 0 +OP4 E015FB 0 +OP4 E015FC 0 +OP4 E015FD 0 +OP4 E015FE 0 +OP4 E015FF 0 +OP4 E01600 0 +OP4 E01601 0 +OP4 E01602 0 +OP4 E01603 0 +OP4 E01604 0 +OP4 E01605 0 +OP4 E01606 0 +OP4 E01607 0 +OP4 E01608 0 +OP4 E01609 0 +OP4 E0160A 0 +OP4 E0160B 0 +OP4 E0160C 0 +OP4 E0160D 0 +OP4 E0160E 0 +OP4 E0160F 0 +OP4 E01610 0 +OP4 E01611 0 +OP4 E01612 0 +OP4 E01613 0 +OP4 E01614 0 +OP4 E01615 0 +OP4 E01616 0 +OP4 E01617 0 +OP4 E01618 0 +OP4 E01619 0 +OP4 E0161A 0 +OP4 E0161B 0 +OP4 E0161C 0 +OP4 E0161D 0 +OP4 E0161E 0 +OP4 E0161F 0 +OP4 E01620 0 +OP4 E01621 0 +OP4 E01622 0 +OP4 E01623 0 +OP4 E01624 0 +OP4 E01625 0 +OP4 E01626 0 +OP4 E01627 0 +OP4 E01628 0 +OP4 E01629 0 +OP4 E0162A 0 +OP4 E0162B 0 +OP4 E0162C 0 +OP4 E0162D 0 +OP4 E0162E 0 +OP4 E0162F 0 +OP4 E01630 0 +OP4 E01631 0 +OP4 E01632 0 +OP4 E01633 0 +OP4 E01634 0 +OP4 E01635 0 +OP4 E01636 0 +OP4 E01637 0 +OP4 E01638 0 +OP4 E01639 0 +OP4 E0163A 0 +OP4 E0163B 0 +OP4 E0163C 0 +OP4 E0163D 0 +OP4 E0163E 0 +OP4 E0163F 0 +OP4 E01640 0 +OP4 E01641 0 +OP4 E01642 0 +OP4 E01643 0 +OP4 E01644 0 +OP4 E01645 0 +OP4 E01646 0 +OP4 E01647 0 +OP4 E01648 0 +OP4 E01649 0 +OP4 E0164A 0 +OP4 E0164B 0 +OP4 E0164C 0 +OP4 E0164D 0 +OP4 E0164E 0 +OP4 E0164F 0 +OP4 E01650 0 +OP4 E01651 0 +OP4 E01652 0 +OP4 E01653 0 +OP4 E01654 0 +OP4 E01655 0 +OP4 E01656 0 +OP4 E01657 0 +OP4 E01658 0 +OP4 E01659 0 +OP4 E0165A 0 +OP4 E0165B 0 +OP4 E0165C 0 +OP4 E0165D 0 +OP4 E0165E 0 +OP4 E0165F 0 +OP4 E01660 0 +OP4 E01661 0 +OP4 E01662 0 +OP4 E01663 0 +OP4 E01664 0 +OP4 E01665 0 +OP4 E01666 0 +OP4 E01667 0 +OP4 E01668 0 +OP4 E01669 0 +OP4 E0166A 0 +OP4 E0166B 0 +OP4 E0166C 0 +OP4 E0166D 0 +OP4 E0166E 0 +OP4 E0166F 0 +OP4 E01670 0 +OP4 E01671 0 +OP4 E01672 0 +OP4 E01673 0 +OP4 E01674 0 +OP4 E01675 0 +OP4 E01676 0 +OP4 E01677 0 +OP4 E01678 0 +OP4 E01679 0 +OP4 E0167A 0 +OP4 E0167B 0 +OP4 E0167C 0 +OP4 E0167D 0 +OP4 E0167E 0 +OP4 E0167F 0 +OP4 E01680 0 +OP4 E01681 0 +OP4 E01682 0 +OP4 E01683 0 +OP4 E01684 0 +OP4 E01685 0 +OP4 E01686 0 +OP4 E01687 0 +OP4 E01688 0 +OP4 E01689 0 +OP4 E0168A 0 +OP4 E0168B 0 +OP4 E0168C 0 +OP4 E0168D 0 +OP4 E0168E 0 +OP4 E0168F 0 +OP4 E01690 0 +OP4 E01691 0 +OP4 E01692 0 +OP4 E01693 0 +OP4 E01694 0 +OP4 E01695 0 +OP4 E01696 0 +OP4 E01697 0 +OP4 E01698 0 +OP4 E01699 0 +OP4 E0169A 0 +OP4 E0169B 0 +OP4 E0169C 0 +OP4 E0169D 0 +OP4 E0169E 0 +OP4 E0169F 0 +OP4 E016A0 0 +OP4 E016A1 0 +OP4 E016A2 0 +OP4 E016A3 0 +OP4 E016A4 0 +OP4 E016A5 0 +OP4 E016A6 0 +OP4 E016A7 0 +OP4 E016A8 0 +OP4 E016A9 0 +OP4 E016AA 0 +OP4 E016AB 0 +OP4 E016AC 0 +OP4 E016AD 0 +OP4 E016AE 0 +OP4 E016AF 0 +OP4 E016B0 0 +OP4 E016B1 0 +OP4 E016B2 0 +OP4 E016B3 0 +OP4 E016B4 0 +OP4 E016B5 0 +OP4 E016B6 0 +OP4 E016B7 0 +OP4 E016B8 0 +OP4 E016B9 0 +OP4 E016BA 0 +OP4 E016BB 0 +OP4 E016BC 0 +OP4 E016BD 0 +OP4 E016BE 0 +OP4 E016BF 0 +OP4 E016C0 0 +OP4 E016C1 0 +OP4 E016C2 0 +OP4 E016C3 0 +OP4 E016C4 0 +OP4 E016C5 0 +OP4 E016C6 0 +OP4 E016C7 0 +OP4 E016C8 0 +OP4 E016C9 0 +OP4 E016CA 0 +OP4 E016CB 0 +OP4 E016CC 0 +OP4 E016CD 0 +OP4 E016CE 0 +OP4 E016CF 0 +OP4 E016D0 0 +OP4 E016D1 0 +OP4 E016D2 0 +OP4 E016D3 0 +OP4 E016D4 0 +OP4 E016D5 0 +OP4 E016D6 0 +OP4 E016D7 0 +OP4 E016D8 0 +OP4 E016D9 0 +OP4 E016DA 0 +OP4 E016DB 0 +OP4 E016DC 0 +OP4 E016DD 0 +OP4 E016DE 0 +OP4 E016DF 0 +OP4 E016E0 0 +OP4 E016E1 0 +OP4 E016E2 0 +OP4 E016E3 0 +OP4 E016E4 0 +OP4 E016E5 0 +OP4 E016E6 0 +OP4 E016E7 0 +OP4 E016E8 0 +OP4 E016E9 0 +OP4 E016EA 0 +OP4 E016EB 0 +OP4 E016EC 0 +OP4 E016ED 0 +OP4 E016EE 0 +OP4 E016EF 0 +OP4 E016F0 0 +OP4 E016F1 0 +OP4 E016F2 0 +OP4 E016F3 0 +OP4 E016F4 0 +OP4 E016F5 0 +OP4 E016F6 0 +OP4 E016F7 0 +OP4 E016F8 0 +OP4 E016F9 0 +OP4 E016FA 0 +OP4 E016FB 0 +OP4 E016FC 0 +OP4 E016FD 0 +OP4 E016FE 0 +OP4 E016FF 0 +OP4 E01700 0 +OP4 E01701 0 +OP4 E01702 0 +OP4 E01703 0 +OP4 E01704 0 +OP4 E01705 0 +OP4 E01706 0 +OP4 E01707 0 +OP4 E01708 0 +OP4 E01709 0 +OP4 E0170A 0 +OP4 E0170B 0 +OP4 E0170C 0 +OP4 E0170D 0 +OP4 E0170E 0 +OP4 E0170F 0 +OP4 E01710 0 +OP4 E01711 0 +OP4 E01712 0 +OP4 E01713 0 +OP4 E01714 0 +OP4 E01715 0 +OP4 E01716 0 +OP4 E01717 0 +OP4 E01718 0 +OP4 E01719 0 +OP4 E0171A 0 +OP4 E0171B 0 +OP4 E0171C 0 +OP4 E0171D 0 +OP4 E0171E 0 +OP4 E0171F 0 +OP4 E01720 0 +OP4 E01721 0 +OP4 E01722 0 +OP4 E01723 0 +OP4 E01724 0 +OP4 E01725 0 +OP4 E01726 0 +OP4 E01727 0 +OP4 E01728 0 +OP4 E01729 0 +OP4 E0172A 0 +OP4 E0172B 0 +OP4 E0172C 0 +OP4 E0172D 0 +OP4 E0172E 0 +OP4 E0172F 0 +OP4 E01730 0 +OP4 E01731 0 +OP4 E01732 0 +OP4 E01733 0 +OP4 E01734 0 +OP4 E01735 0 +OP4 E01736 0 +OP4 E01737 0 +OP4 E01738 0 +OP4 E01739 0 +OP4 E0173A 0 +OP4 E0173B 0 +OP4 E0173C 0 +OP4 E0173D 0 +OP4 E0173E 0 +OP4 E0173F 0 +OP4 E01740 0 +OP4 E01741 0 +OP4 E01742 0 +OP4 E01743 0 +OP4 E01744 0 +OP4 E01745 0 +OP4 E01746 0 +OP4 E01747 0 +OP4 E01748 0 +OP4 E01749 0 +OP4 E0174A 0 +OP4 E0174B 0 +OP4 E0174C 0 +OP4 E0174D 0 +OP4 E0174E 0 +OP4 E0174F 0 +OP4 E01750 0 +OP4 E01751 0 +OP4 E01752 0 +OP4 E01753 0 +OP4 E01754 0 +OP4 E01755 0 +OP4 E01756 0 +OP4 E01757 0 +OP4 E01758 0 +OP4 E01759 0 +OP4 E0175A 0 +OP4 E0175B 0 +OP4 E0175C 0 +OP4 E0175D 0 +OP4 E0175E 0 +OP4 E0175F 0 +OP4 E01760 0 +OP4 E01761 0 +OP4 E01762 0 +OP4 E01763 0 +OP4 E01764 0 +OP4 E01765 0 +OP4 E01766 0 +OP4 E01767 0 +OP4 E01768 0 +OP4 E01769 0 +OP4 E0176A 0 +OP4 E0176B 0 +OP4 E0176C 0 +OP4 E0176D 0 +OP4 E0176E 0 +OP4 E0176F 0 +OP4 E01770 0 +OP4 E01771 0 +OP4 E01772 0 +OP4 E01773 0 +OP4 E01774 0 +OP4 E01775 0 +OP4 E01776 0 +OP4 E01777 0 +OP4 E01778 0 +OP4 E01779 0 +OP4 E0177A 0 +OP4 E0177B 0 +OP4 E0177C 0 +OP4 E0177D 0 +OP4 E0177E 0 +OP4 E0177F 0 +OP4 E01780 0 +OP4 E01781 0 +OP4 E01782 0 +OP4 E01783 0 +OP4 E01784 0 +OP4 E01785 0 +OP4 E01786 0 +OP4 E01787 0 +OP4 E01788 0 +OP4 E01789 0 +OP4 E0178A 0 +OP4 E0178B 0 +OP4 E0178C 0 +OP4 E0178D 0 +OP4 E0178E 0 +OP4 E0178F 0 +OP4 E01790 0 +OP4 E01791 0 +OP4 E01792 0 +OP4 E01793 0 +OP4 E01794 0 +OP4 E01795 0 +OP4 E01796 0 +OP4 E01797 0 +OP4 E01798 0 +OP4 E01799 0 +OP4 E0179A 0 +OP4 E0179B 0 +OP4 E0179C 0 +OP4 E0179D 0 +OP4 E0179E 0 +OP4 E0179F 0 +OP4 E017A0 0 +OP4 E017A1 0 +OP4 E017A2 0 +OP4 E017A3 0 +OP4 E017A4 0 +OP4 E017A5 0 +OP4 E017A6 0 +OP4 E017A7 0 +OP4 E017A8 0 +OP4 E017A9 0 +OP4 E017AA 0 +OP4 E017AB 0 +OP4 E017AC 0 +OP4 E017AD 0 +OP4 E017AE 0 +OP4 E017AF 0 +OP4 E017B0 0 +OP4 E017B1 0 +OP4 E017B2 0 +OP4 E017B3 0 +OP4 E017B4 0 +OP4 E017B5 0 +OP4 E017B6 0 +OP4 E017B7 0 +OP4 E017B8 0 +OP4 E017B9 0 +OP4 E017BA 0 +OP4 E017BB 0 +OP4 E017BC 0 +OP4 E017BD 0 +OP4 E017BE 0 +OP4 E017BF 0 +OP4 E017C0 0 +OP4 E017C1 0 +OP4 E017C2 0 +OP4 E017C3 0 +OP4 E017C4 0 +OP4 E017C5 0 +OP4 E017C6 0 +OP4 E017C7 0 +OP4 E017C8 0 +OP4 E017C9 0 +OP4 E017CA 0 +OP4 E017CB 0 +OP4 E017CC 0 +OP4 E017CD 0 +OP4 E017CE 0 +OP4 E017CF 0 +OP4 E017D0 0 +OP4 E017D1 0 +OP4 E017D2 0 +OP4 E017D3 0 +OP4 E017D4 0 +OP4 E017D5 0 +OP4 E017D6 0 +OP4 E017D7 0 +OP4 E017D8 0 +OP4 E017D9 0 +OP4 E017DA 0 +OP4 E017DB 0 +OP4 E017DC 0 +OP4 E017DD 0 +OP4 E017DE 0 +OP4 E017DF 0 +OP4 E017E0 0 +OP4 E017E1 0 +OP4 E017E2 0 +OP4 E017E3 0 +OP4 E017E4 0 +OP4 E017E5 0 +OP4 E017E6 0 +OP4 E017E7 0 +OP4 E017E8 0 +OP4 E017E9 0 +OP4 E017EA 0 +OP4 E017EB 0 +OP4 E017EC 0 +OP4 E017ED 0 +OP4 E017EE 0 +OP4 E017EF 0 +OP4 E017F0 0 +OP4 E017F1 0 +OP4 E017F2 0 +OP4 E017F3 0 +OP4 E017F4 0 +OP4 E017F5 0 +OP4 E017F6 0 +OP4 E017F7 0 +OP4 E017F8 0 +OP4 E017F9 0 +OP4 E017FA 0 +OP4 E017FB 0 +OP4 E017FC 0 +OP4 E017FD 0 +OP4 E017FE 0 +OP4 E017FF 0 +OP4 E01800 0 +OP4 E01801 0 +OP4 E01802 0 +OP4 E01803 0 +OP4 E01804 0 +OP4 E01805 0 +OP4 E01806 0 +OP4 E01807 0 +OP4 E01808 0 +OP4 E01809 0 +OP4 E0180A 0 +OP4 E0180B 0 +OP4 E0180C 0 +OP4 E0180D 0 +OP4 E0180E 0 +OP4 E0180F 0 +OP4 E01810 0 +OP4 E01811 0 +OP4 E01812 0 +OP4 E01813 0 +OP4 E01814 0 +OP4 E01815 0 +OP4 E01816 0 +OP4 E01817 0 +OP4 E01818 0 +OP4 E01819 0 +OP4 E0181A 0 +OP4 E0181B 0 +OP4 E0181C 0 +OP4 E0181D 0 +OP4 E0181E 0 +OP4 E0181F 0 +OP4 E01820 0 +OP4 E01821 0 +OP4 E01822 0 +OP4 E01823 0 +OP4 E01824 0 +OP4 E01825 0 +OP4 E01826 0 +OP4 E01827 0 +OP4 E01828 0 +OP4 E01829 0 +OP4 E0182A 0 +OP4 E0182B 0 +OP4 E0182C 0 +OP4 E0182D 0 +OP4 E0182E 0 +OP4 E0182F 0 +OP4 E01830 0 +OP4 E01831 0 +OP4 E01832 0 +OP4 E01833 0 +OP4 E01834 0 +OP4 E01835 0 +OP4 E01836 0 +OP4 E01837 0 +OP4 E01838 0 +OP4 E01839 0 +OP4 E0183A 0 +OP4 E0183B 0 +OP4 E0183C 0 +OP4 E0183D 0 +OP4 E0183E 0 +OP4 E0183F 0 +OP4 E01840 0 +OP4 E01841 0 +OP4 E01842 0 +OP4 E01843 0 +OP4 E01844 0 +OP4 E01845 0 +OP4 E01846 0 +OP4 E01847 0 +OP4 E01848 0 +OP4 E01849 0 +OP4 E0184A 0 +OP4 E0184B 0 +OP4 E0184C 0 +OP4 E0184D 0 +OP4 E0184E 0 +OP4 E0184F 0 +OP4 E01850 0 +OP4 E01851 0 +OP4 E01852 0 +OP4 E01853 0 +OP4 E01854 0 +OP4 E01855 0 +OP4 E01856 0 +OP4 E01857 0 +OP4 E01858 0 +OP4 E01859 0 +OP4 E0185A 0 +OP4 E0185B 0 +OP4 E0185C 0 +OP4 E0185D 0 +OP4 E0185E 0 +OP4 E0185F 0 +OP4 E01860 0 +OP4 E01861 0 +OP4 E01862 0 +OP4 E01863 0 +OP4 E01864 0 +OP4 E01865 0 +OP4 E01866 0 +OP4 E01867 0 +OP4 E01868 0 +OP4 E01869 0 +OP4 E0186A 0 +OP4 E0186B 0 +OP4 E0186C 0 +OP4 E0186D 0 +OP4 E0186E 0 +OP4 E0186F 0 +OP4 E01870 0 +OP4 E01871 0 +OP4 E01872 0 +OP4 E01873 0 +OP4 E01874 0 +OP4 E01875 0 +OP4 E01876 0 +OP4 E01877 0 +OP4 E01878 0 +OP4 E01879 0 +OP4 E0187A 0 +OP4 E0187B 0 +OP4 E0187C 0 +OP4 E0187D 0 +OP4 E0187E 0 +OP4 E0187F 0 +OP4 E01880 0 +OP4 E01881 0 +OP4 E01882 0 +OP4 E01883 0 +OP4 E01884 0 +OP4 E01885 0 +OP4 E01886 0 +OP4 E01887 0 +OP4 E01888 0 +OP4 E01889 0 +OP4 E0188A 0 +OP4 E0188B 0 +OP4 E0188C 0 +OP4 E0188D 0 +OP4 E0188E 0 +OP4 E0188F 0 +OP4 E01890 0 +OP4 E01891 0 +OP4 E01892 0 +OP4 E01893 0 +OP4 E01894 0 +OP4 E01895 0 +OP4 E01896 0 +OP4 E01897 0 +OP4 E01898 0 +OP4 E01899 0 +OP4 E0189A 0 +OP4 E0189B 0 +OP4 E0189C 0 +OP4 E0189D 0 +OP4 E0189E 0 +OP4 E0189F 0 +OP4 E018A0 0 +OP4 E018A1 0 +OP4 E018A2 0 +OP4 E018A3 0 +OP4 E018A4 0 +OP4 E018A5 0 +OP4 E018A6 0 +OP4 E018A7 0 +OP4 E018A8 0 +OP4 E018A9 0 +OP4 E018AA 0 +OP4 E018AB 0 +OP4 E018AC 0 +OP4 E018AD 0 +OP4 E018AE 0 +OP4 E018AF 0 +OP4 E018B0 0 +OP4 E018B1 0 +OP4 E018B2 0 +OP4 E018B3 0 +OP4 E018B4 0 +OP4 E018B5 0 +OP4 E018B6 0 +OP4 E018B7 0 +OP4 E018B8 0 +OP4 E018B9 0 +OP4 E018BA 0 +OP4 E018BB 0 +OP4 E018BC 0 +OP4 E018BD 0 +OP4 E018BE 0 +OP4 E018BF 0 +OP4 E018C0 0 +OP4 E018C1 0 +OP4 E018C2 0 +OP4 E018C3 0 +OP4 E018C4 0 +OP4 E018C5 0 +OP4 E018C6 0 +OP4 E018C7 0 +OP4 E018C8 0 +OP4 E018C9 0 +OP4 E018CA 0 +OP4 E018CB 0 +OP4 E018CC 0 +OP4 E018CD 0 +OP4 E018CE 0 +OP4 E018CF 0 +OP4 E018D0 0 +OP4 E018D1 0 +OP4 E018D2 0 +OP4 E018D3 0 +OP4 E018D4 0 +OP4 E018D5 0 +OP4 E018D6 0 +OP4 E018D7 0 +OP4 E018D8 0 +OP4 E018D9 0 +OP4 E018DA 0 +OP4 E018DB 0 +OP4 E018DC 0 +OP4 E018DD 0 +OP4 E018DE 0 +OP4 E018DF 0 +OP4 E018E0 0 +OP4 E018E1 0 +OP4 E018E2 0 +OP4 E018E3 0 +OP4 E018E4 0 +OP4 E018E5 0 +OP4 E018E6 0 +OP4 E018E7 0 +OP4 E018E8 0 +OP4 E018E9 0 +OP4 E018EA 0 +OP4 E018EB 0 +OP4 E018EC 0 +OP4 E018ED 0 +OP4 E018EE 0 +OP4 E018EF 0 +OP4 E018F0 0 +OP4 E018F1 0 +OP4 E018F2 0 +OP4 E018F3 0 +OP4 E018F4 0 +OP4 E018F5 0 +OP4 E018F6 0 +OP4 E018F7 0 +OP4 E018F8 0 +OP4 E018F9 0 +OP4 E018FA 0 +OP4 E018FB 0 +OP4 E018FC 0 +OP4 E018FD 0 +OP4 E018FE 0 +OP4 E018FF 0 +OP4 E01900 0 +OP4 E01901 0 +OP4 E01902 0 +OP4 E01903 0 +OP4 E01904 0 +OP4 E01905 0 +OP4 E01906 0 +OP4 E01907 0 +OP4 E01908 0 +OP4 E01909 0 +OP4 E0190A 0 +OP4 E0190B 0 +OP4 E0190C 0 +OP4 E0190D 0 +OP4 E0190E 0 +OP4 E0190F 0 +OP4 E01910 0 +OP4 E01911 0 +OP4 E01912 0 +OP4 E01913 0 +OP4 E01914 0 +OP4 E01915 0 +OP4 E01916 0 +OP4 E01917 0 +OP4 E01918 0 +OP4 E01919 0 +OP4 E0191A 0 +OP4 E0191B 0 +OP4 E0191C 0 +OP4 E0191D 0 +OP4 E0191E 0 +OP4 E0191F 0 +OP4 E01920 0 +OP4 E01921 0 +OP4 E01922 0 +OP4 E01923 0 +OP4 E01924 0 +OP4 E01925 0 +OP4 E01926 0 +OP4 E01927 0 +OP4 E01928 0 +OP4 E01929 0 +OP4 E0192A 0 +OP4 E0192B 0 +OP4 E0192C 0 +OP4 E0192D 0 +OP4 E0192E 0 +OP4 E0192F 0 +OP4 E01930 0 +OP4 E01931 0 +OP4 E01932 0 +OP4 E01933 0 +OP4 E01934 0 +OP4 E01935 0 +OP4 E01936 0 +OP4 E01937 0 +OP4 E01938 0 +OP4 E01939 0 +OP4 E0193A 0 +OP4 E0193B 0 +OP4 E0193C 0 +OP4 E0193D 0 +OP4 E0193E 0 +OP4 E0193F 0 +OP4 E01940 0 +OP4 E01941 0 +OP4 E01942 0 +OP4 E01943 0 +OP4 E01944 0 +OP4 E01945 0 +OP4 E01946 0 +OP4 E01947 0 +OP4 E01948 0 +OP4 E01949 0 +OP4 E0194A 0 +OP4 E0194B 0 +OP4 E0194C 0 +OP4 E0194D 0 +OP4 E0194E 0 +OP4 E0194F 0 +OP4 E01950 0 +OP4 E01951 0 +OP4 E01952 0 +OP4 E01953 0 +OP4 E01954 0 +OP4 E01955 0 +OP4 E01956 0 +OP4 E01957 0 +OP4 E01958 0 +OP4 E01959 0 +OP4 E0195A 0 +OP4 E0195B 0 +OP4 E0195C 0 +OP4 E0195D 0 +OP4 E0195E 0 +OP4 E0195F 0 +OP4 E01960 0 +OP4 E01961 0 +OP4 E01962 0 +OP4 E01963 0 +OP4 E01964 0 +OP4 E01965 0 +OP4 E01966 0 +OP4 E01967 0 +OP4 E01968 0 +OP4 E01969 0 +OP4 E0196A 0 +OP4 E0196B 0 +OP4 E0196C 0 +OP4 E0196D 0 +OP4 E0196E 0 +OP4 E0196F 0 +OP4 E01970 0 +OP4 E01971 0 +OP4 E01972 0 +OP4 E01973 0 +OP4 E01974 0 +OP4 E01975 0 +OP4 E01976 0 +OP4 E01977 0 +OP4 E01978 0 +OP4 E01979 0 +OP4 E0197A 0 +OP4 E0197B 0 +OP4 E0197C 0 +OP4 E0197D 0 +OP4 E0197E 0 +OP4 E0197F 0 +OP4 E01980 0 +OP4 E01981 0 +OP4 E01982 0 +OP4 E01983 0 +OP4 E01984 0 +OP4 E01985 0 +OP4 E01986 0 +OP4 E01987 0 +OP4 E01988 0 +OP4 E01989 0 +OP4 E0198A 0 +OP4 E0198B 0 +OP4 E0198C 0 +OP4 E0198D 0 +OP4 E0198E 0 +OP4 E0198F 0 +OP4 E01990 0 +OP4 E01991 0 +OP4 E01992 0 +OP4 E01993 0 +OP4 E01994 0 +OP4 E01995 0 +OP4 E01996 0 +OP4 E01997 0 +OP4 E01998 0 +OP4 E01999 0 +OP4 E0199A 0 +OP4 E0199B 0 +OP4 E0199C 0 +OP4 E0199D 0 +OP4 E0199E 0 +OP4 E0199F 0 +OP4 E019A0 0 +OP4 E019A1 0 +OP4 E019A2 0 +OP4 E019A3 0 +OP4 E019A4 0 +OP4 E019A5 0 +OP4 E019A6 0 +OP4 E019A7 0 +OP4 E019A8 0 +OP4 E019A9 0 +OP4 E019AA 0 +OP4 E019AB 0 +OP4 E019AC 0 +OP4 E019AD 0 +OP4 E019AE 0 +OP4 E019AF 0 +OP4 E019B0 0 +OP4 E019B1 0 +OP4 E019B2 0 +OP4 E019B3 0 +OP4 E019B4 0 +OP4 E019B5 0 +OP4 E019B6 0 +OP4 E019B7 0 +OP4 E019B8 0 +OP4 E019B9 0 +OP4 E019BA 0 +OP4 E019BB 0 +OP4 E019BC 0 +OP4 E019BD 0 +OP4 E019BE 0 +OP4 E019BF 0 +OP4 E019C0 0 +OP4 E019C1 0 +OP4 E019C2 0 +OP4 E019C3 0 +OP4 E019C4 0 +OP4 E019C5 0 +OP4 E019C6 0 +OP4 E019C7 0 +OP4 E019C8 0 +OP4 E019C9 0 +OP4 E019CA 0 +OP4 E019CB 0 +OP4 E019CC 0 +OP4 E019CD 0 +OP4 E019CE 0 +OP4 E019CF 0 +OP4 E019D0 0 +OP4 E019D1 0 +OP4 E019D2 0 +OP4 E019D3 0 +OP4 E019D4 0 +OP4 E019D5 0 +OP4 E019D6 0 +OP4 E019D7 0 +OP4 E019D8 0 +OP4 E019D9 0 +OP4 E019DA 0 +OP4 E019DB 0 +OP4 E019DC 0 +OP4 E019DD 0 +OP4 E019DE 0 +OP4 E019DF 0 +OP4 E019E0 0 +OP4 E019E1 0 +OP4 E019E2 0 +OP4 E019E3 0 +OP4 E019E4 0 +OP4 E019E5 0 +OP4 E019E6 0 +OP4 E019E7 0 +OP4 E019E8 0 +OP4 E019E9 0 +OP4 E019EA 0 +OP4 E019EB 0 +OP4 E019EC 0 +OP4 E019ED 0 +OP4 E019EE 0 +OP4 E019EF 0 +OP4 E019F0 0 +OP4 E019F1 0 +OP4 E019F2 0 +OP4 E019F3 0 +OP4 E019F4 0 +OP4 E019F5 0 +OP4 E019F6 0 +OP4 E019F7 0 +OP4 E019F8 0 +OP4 E019F9 0 +OP4 E019FA 0 +OP4 E019FB 0 +OP4 E019FC 0 +OP4 E019FD 0 +OP4 E019FE 0 +OP4 E019FF 0 +OP4 E01A00 0 +OP4 E01A01 0 +OP4 E01A02 0 +OP4 E01A03 0 +OP4 E01A04 0 +OP4 E01A05 0 +OP4 E01A06 0 +OP4 E01A07 0 +OP4 E01A08 0 +OP4 E01A09 0 +OP4 E01A0A 0 +OP4 E01A0B 0 +OP4 E01A0C 0 +OP4 E01A0D 0 +OP4 E01A0E 0 +OP4 E01A0F 0 +OP4 E01A10 0 +OP4 E01A11 0 +OP4 E01A12 0 +OP4 E01A13 0 +OP4 E01A14 0 +OP4 E01A15 0 +OP4 E01A16 0 +OP4 E01A17 0 +OP4 E01A18 0 +OP4 E01A19 0 +OP4 E01A1A 0 +OP4 E01A1B 0 +OP4 E01A1C 0 +OP4 E01A1D 0 +OP4 E01A1E 0 +OP4 E01A1F 0 +OP4 E01A20 0 +OP4 E01A21 0 +OP4 E01A22 0 +OP4 E01A23 0 +OP4 E01A24 0 +OP4 E01A25 0 +OP4 E01A26 0 +OP4 E01A27 0 +OP4 E01A28 0 +OP4 E01A29 0 +OP4 E01A2A 0 +OP4 E01A2B 0 +OP4 E01A2C 0 +OP4 E01A2D 0 +OP4 E01A2E 0 +OP4 E01A2F 0 +OP4 E01A30 0 +OP4 E01A31 0 +OP4 E01A32 0 +OP4 E01A33 0 +OP4 E01A34 0 +OP4 E01A35 0 +OP4 E01A36 0 +OP4 E01A37 0 +OP4 E01A38 0 +OP4 E01A39 0 +OP4 E01A3A 0 +OP4 E01A3B 0 +OP4 E01A3C 0 +OP4 E01A3D 0 +OP4 E01A3E 0 +OP4 E01A3F 0 +OP4 E01A40 0 +OP4 E01A41 0 +OP4 E01A42 0 +OP4 E01A43 0 +OP4 E01A44 0 +OP4 E01A45 0 +OP4 E01A46 0 +OP4 E01A47 0 +OP4 E01A48 0 +OP4 E01A49 0 +OP4 E01A4A 0 +OP4 E01A4B 0 +OP4 E01A4C 0 +OP4 E01A4D 0 +OP4 E01A4E 0 +OP4 E01A4F 0 +OP4 E01A50 0 +OP4 E01A51 0 +OP4 E01A52 0 +OP4 E01A53 0 +OP4 E01A54 0 +OP4 E01A55 0 +OP4 E01A56 0 +OP4 E01A57 0 +OP4 E01A58 0 +OP4 E01A59 0 +OP4 E01A5A 0 +OP4 E01A5B 0 +OP4 E01A5C 0 +OP4 E01A5D 0 +OP4 E01A5E 0 +OP4 E01A5F 0 +OP4 E01A60 0 +OP4 E01A61 0 +OP4 E01A62 0 +OP4 E01A63 0 +OP4 E01A64 0 +OP4 E01A65 0 +OP4 E01A66 0 +OP4 E01A67 0 +OP4 E01A68 0 +OP4 E01A69 0 +OP4 E01A6A 0 +OP4 E01A6B 0 +OP4 E01A6C 0 +OP4 E01A6D 0 +OP4 E01A6E 0 +OP4 E01A6F 0 +OP4 E01A70 0 +OP4 E01A71 0 +OP4 E01A72 0 +OP4 E01A73 0 +OP4 E01A74 0 +OP4 E01A75 0 +OP4 E01A76 0 +OP4 E01A77 0 +OP4 E01A78 0 +OP4 E01A79 0 +OP4 E01A7A 0 +OP4 E01A7B 0 +OP4 E01A7C 0 +OP4 E01A7D 0 +OP4 E01A7E 0 +OP4 E01A7F 0 +OP4 E01A80 0 +OP4 E01A81 0 +OP4 E01A82 0 +OP4 E01A83 0 +OP4 E01A84 0 +OP4 E01A85 0 +OP4 E01A86 0 +OP4 E01A87 0 +OP4 E01A88 0 +OP4 E01A89 0 +OP4 E01A8A 0 +OP4 E01A8B 0 +OP4 E01A8C 0 +OP4 E01A8D 0 +OP4 E01A8E 0 +OP4 E01A8F 0 +OP4 E01A90 0 +OP4 E01A91 0 +OP4 E01A92 0 +OP4 E01A93 0 +OP4 E01A94 0 +OP4 E01A95 0 +OP4 E01A96 0 +OP4 E01A97 0 +OP4 E01A98 0 +OP4 E01A99 0 +OP4 E01A9A 0 +OP4 E01A9B 0 +OP4 E01A9C 0 +OP4 E01A9D 0 +OP4 E01A9E 0 +OP4 E01A9F 0 +OP4 E01AA0 0 +OP4 E01AA1 0 +OP4 E01AA2 0 +OP4 E01AA3 0 +OP4 E01AA4 0 +OP4 E01AA5 0 +OP4 E01AA6 0 +OP4 E01AA7 0 +OP4 E01AA8 0 +OP4 E01AA9 0 +OP4 E01AAA 0 +OP4 E01AAB 0 +OP4 E01AAC 0 +OP4 E01AAD 0 +OP4 E01AAE 0 +OP4 E01AAF 0 +OP4 E01AB0 0 +OP4 E01AB1 0 +OP4 E01AB2 0 +OP4 E01AB3 0 +OP4 E01AB4 0 +OP4 E01AB5 0 +OP4 E01AB6 0 +OP4 E01AB7 0 +OP4 E01AB8 0 +OP4 E01AB9 0 +OP4 E01ABA 0 +OP4 E01ABB 0 +OP4 E01ABC 0 +OP4 E01ABD 0 +OP4 E01ABE 0 +OP4 E01ABF 0 +OP4 E01AC0 0 +OP4 E01AC1 0 +OP4 E01AC2 0 +OP4 E01AC3 0 +OP4 E01AC4 0 +OP4 E01AC5 0 +OP4 E01AC6 0 +OP4 E01AC7 0 +OP4 E01AC8 0 +OP4 E01AC9 0 +OP4 E01ACA 0 +OP4 E01ACB 0 +OP4 E01ACC 0 +OP4 E01ACD 0 +OP4 E01ACE 0 +OP4 E01ACF 0 +OP4 E01AD0 0 +OP4 E01AD1 0 +OP4 E01AD2 0 +OP4 E01AD3 0 +OP4 E01AD4 0 +OP4 E01AD5 0 +OP4 E01AD6 0 +OP4 E01AD7 0 +OP4 E01AD8 0 +OP4 E01AD9 0 +OP4 E01ADA 0 +OP4 E01ADB 0 +OP4 E01ADC 0 +OP4 E01ADD 0 +OP4 E01ADE 0 +OP4 E01ADF 0 +OP4 E01AE0 0 +OP4 E01AE1 0 +OP4 E01AE2 0 +OP4 E01AE3 0 +OP4 E01AE4 0 +OP4 E01AE5 0 +OP4 E01AE6 0 +OP4 E01AE7 0 +OP4 E01AE8 0 +OP4 E01AE9 0 +OP4 E01AEA 0 +OP4 E01AEB 0 +OP4 E01AEC 0 +OP4 E01AED 0 +OP4 E01AEE 0 +OP4 E01AEF 0 +OP4 E01AF0 0 +OP4 E01AF1 0 +OP4 E01AF2 0 +OP4 E01AF3 0 +OP4 E01AF4 0 +OP4 E01AF5 0 +OP4 E01AF6 0 +OP4 E01AF7 0 +OP4 E01AF8 0 +OP4 E01AF9 0 +OP4 E01AFA 0 +OP4 E01AFB 0 +OP4 E01AFC 0 +OP4 E01AFD 0 +OP4 E01AFE 0 +OP4 E01AFF 0 +OP4 E01B00 0 +OP4 E01B01 0 +OP4 E01B02 0 +OP4 E01B03 0 +OP4 E01B04 0 +OP4 E01B05 0 +OP4 E01B06 0 +OP4 E01B07 0 +OP4 E01B08 0 +OP4 E01B09 0 +OP4 E01B0A 0 +OP4 E01B0B 0 +OP4 E01B0C 0 +OP4 E01B0D 0 +OP4 E01B0E 0 +OP4 E01B0F 0 +OP4 E01B10 0 +OP4 E01B11 0 +OP4 E01B12 0 +OP4 E01B13 0 +OP4 E01B14 0 +OP4 E01B15 0 +OP4 E01B16 0 +OP4 E01B17 0 +OP4 E01B18 0 +OP4 E01B19 0 +OP4 E01B1A 0 +OP4 E01B1B 0 +OP4 E01B1C 0 +OP4 E01B1D 0 +OP4 E01B1E 0 +OP4 E01B1F 0 +OP4 E01B20 0 +OP4 E01B21 0 +OP4 E01B22 0 +OP4 E01B23 0 +OP4 E01B24 0 +OP4 E01B25 0 +OP4 E01B26 0 +OP4 E01B27 0 +OP4 E01B28 0 +OP4 E01B29 0 +OP4 E01B2A 0 +OP4 E01B2B 0 +OP4 E01B2C 0 +OP4 E01B2D 0 +OP4 E01B2E 0 +OP4 E01B2F 0 +OP4 E01B30 0 +OP4 E01B31 0 +OP4 E01B32 0 +OP4 E01B33 0 +OP4 E01B34 0 +OP4 E01B35 0 +OP4 E01B36 0 +OP4 E01B37 0 +OP4 E01B38 0 +OP4 E01B39 0 +OP4 E01B3A 0 +OP4 E01B3B 0 +OP4 E01B3C 0 +OP4 E01B3D 0 +OP4 E01B3E 0 +OP4 E01B3F 0 +OP4 E01B40 0 +OP4 E01B41 0 +OP4 E01B42 0 +OP4 E01B43 0 +OP4 E01B44 0 +OP4 E01B45 0 +OP4 E01B46 0 +OP4 E01B47 0 +OP4 E01B48 0 +OP4 E01B49 0 +OP4 E01B4A 0 +OP4 E01B4B 0 +OP4 E01B4C 0 +OP4 E01B4D 0 +OP4 E01B4E 0 +OP4 E01B4F 0 +OP4 E01B50 0 +OP4 E01B51 0 +OP4 E01B52 0 +OP4 E01B53 0 +OP4 E01B54 0 +OP4 E01B55 0 +OP4 E01B56 0 +OP4 E01B57 0 +OP4 E01B58 0 +OP4 E01B59 0 +OP4 E01B5A 0 +OP4 E01B5B 0 +OP4 E01B5C 0 +OP4 E01B5D 0 +OP4 E01B5E 0 +OP4 E01B5F 0 +OP4 E01B60 0 +OP4 E01B61 0 +OP4 E01B62 0 +OP4 E01B63 0 +OP4 E01B64 0 +OP4 E01B65 0 +OP4 E01B66 0 +OP4 E01B67 0 +OP4 E01B68 0 +OP4 E01B69 0 +OP4 E01B6A 0 +OP4 E01B6B 0 +OP4 E01B6C 0 +OP4 E01B6D 0 +OP4 E01B6E 0 +OP4 E01B6F 0 +OP4 E01B70 0 +OP4 E01B71 0 +OP4 E01B72 0 +OP4 E01B73 0 +OP4 E01B74 0 +OP4 E01B75 0 +OP4 E01B76 0 +OP4 E01B77 0 +OP4 E01B78 0 +OP4 E01B79 0 +OP4 E01B7A 0 +OP4 E01B7B 0 +OP4 E01B7C 0 +OP4 E01B7D 0 +OP4 E01B7E 0 +OP4 E01B7F 0 +OP4 E01B80 0 +OP4 E01B81 0 +OP4 E01B82 0 +OP4 E01B83 0 +OP4 E01B84 0 +OP4 E01B85 0 +OP4 E01B86 0 +OP4 E01B87 0 +OP4 E01B88 0 +OP4 E01B89 0 +OP4 E01B8A 0 +OP4 E01B8B 0 +OP4 E01B8C 0 +OP4 E01B8D 0 +OP4 E01B8E 0 +OP4 E01B8F 0 +OP4 E01B90 0 +OP4 E01B91 0 +OP4 E01B92 0 +OP4 E01B93 0 +OP4 E01B94 0 +OP4 E01B95 0 +OP4 E01B96 0 +OP4 E01B97 0 +OP4 E01B98 0 +OP4 E01B99 0 +OP4 E01B9A 0 +OP4 E01B9B 0 +OP4 E01B9C 0 +OP4 E01B9D 0 +OP4 E01B9E 0 +OP4 E01B9F 0 +OP4 E01BA0 0 +OP4 E01BA1 0 +OP4 E01BA2 0 +OP4 E01BA3 0 +OP4 E01BA4 0 +OP4 E01BA5 0 +OP4 E01BA6 0 +OP4 E01BA7 0 +OP4 E01BA8 0 +OP4 E01BA9 0 +OP4 E01BAA 0 +OP4 E01BAB 0 +OP4 E01BAC 0 +OP4 E01BAD 0 +OP4 E01BAE 0 +OP4 E01BAF 0 +OP4 E01BB0 0 +OP4 E01BB1 0 +OP4 E01BB2 0 +OP4 E01BB3 0 +OP4 E01BB4 0 +OP4 E01BB5 0 +OP4 E01BB6 0 +OP4 E01BB7 0 +OP4 E01BB8 0 +OP4 E01BB9 0 +OP4 E01BBA 0 +OP4 E01BBB 0 +OP4 E01BBC 0 +OP4 E01BBD 0 +OP4 E01BBE 0 +OP4 E01BBF 0 +OP4 E01BC0 0 +OP4 E01BC1 0 +OP4 E01BC2 0 +OP4 E01BC3 0 +OP4 E01BC4 0 +OP4 E01BC5 0 +OP4 E01BC6 0 +OP4 E01BC7 0 +OP4 E01BC8 0 +OP4 E01BC9 0 +OP4 E01BCA 0 +OP4 E01BCB 0 +OP4 E01BCC 0 +OP4 E01BCD 0 +OP4 E01BCE 0 +OP4 E01BCF 0 +OP4 E01BD0 0 +OP4 E01BD1 0 +OP4 E01BD2 0 +OP4 E01BD3 0 +OP4 E01BD4 0 +OP4 E01BD5 0 +OP4 E01BD6 0 +OP4 E01BD7 0 +OP4 E01BD8 0 +OP4 E01BD9 0 +OP4 E01BDA 0 +OP4 E01BDB 0 +OP4 E01BDC 0 +OP4 E01BDD 0 +OP4 E01BDE 0 +OP4 E01BDF 0 +OP4 E01BE0 0 +OP4 E01BE1 0 +OP4 E01BE2 0 +OP4 E01BE3 0 +OP4 E01BE4 0 +OP4 E01BE5 0 +OP4 E01BE6 0 +OP4 E01BE7 0 +OP4 E01BE8 0 +OP4 E01BE9 0 +OP4 E01BEA 0 +OP4 E01BEB 0 +OP4 E01BEC 0 +OP4 E01BED 0 +OP4 E01BEE 0 +OP4 E01BEF 0 +OP4 E01BF0 0 +OP4 E01BF1 0 +OP4 E01BF2 0 +OP4 E01BF3 0 +OP4 E01BF4 0 +OP4 E01BF5 0 +OP4 E01BF6 0 +OP4 E01BF7 0 +OP4 E01BF8 0 +OP4 E01BF9 0 +OP4 E01BFA 0 +OP4 E01BFB 0 +OP4 E01BFC 0 +OP4 E01BFD 0 +OP4 E01BFE 0 +OP4 E01BFF 0 +OP4 E01C00 0 +OP4 E01C01 0 +OP4 E01C02 0 +OP4 E01C03 0 +OP4 E01C04 0 +OP4 E01C05 0 +OP4 E01C06 0 +OP4 E01C07 0 +OP4 E01C08 0 +OP4 E01C09 0 +OP4 E01C0A 0 +OP4 E01C0B 0 +OP4 E01C0C 0 +OP4 E01C0D 0 +OP4 E01C0E 0 +OP4 E01C0F 0 +OP4 E01C10 0 +OP4 E01C11 0 +OP4 E01C12 0 +OP4 E01C13 0 +OP4 E01C14 0 +OP4 E01C15 0 +OP4 E01C16 0 +OP4 E01C17 0 +OP4 E01C18 0 +OP4 E01C19 0 +OP4 E01C1A 0 +OP4 E01C1B 0 +OP4 E01C1C 0 +OP4 E01C1D 0 +OP4 E01C1E 0 +OP4 E01C1F 0 +OP4 E01C20 0 +OP4 E01C21 0 +OP4 E01C22 0 +OP4 E01C23 0 +OP4 E01C24 0 +OP4 E01C25 0 +OP4 E01C26 0 +OP4 E01C27 0 +OP4 E01C28 0 +OP4 E01C29 0 +OP4 E01C2A 0 +OP4 E01C2B 0 +OP4 E01C2C 0 +OP4 E01C2D 0 +OP4 E01C2E 0 +OP4 E01C2F 0 +OP4 E01C30 0 +OP4 E01C31 0 +OP4 E01C32 0 +OP4 E01C33 0 +OP4 E01C34 0 +OP4 E01C35 0 +OP4 E01C36 0 +OP4 E01C37 0 +OP4 E01C38 0 +OP4 E01C39 0 +OP4 E01C3A 0 +OP4 E01C3B 0 +OP4 E01C3C 0 +OP4 E01C3D 0 +OP4 E01C3E 0 +OP4 E01C3F 0 +OP4 E01C40 0 +OP4 E01C41 0 +OP4 E01C42 0 +OP4 E01C43 0 +OP4 E01C44 0 +OP4 E01C45 0 +OP4 E01C46 0 +OP4 E01C47 0 +OP4 E01C48 0 +OP4 E01C49 0 +OP4 E01C4A 0 +OP4 E01C4B 0 +OP4 E01C4C 0 +OP4 E01C4D 0 +OP4 E01C4E 0 +OP4 E01C4F 0 +OP4 E01C50 0 +OP4 E01C51 0 +OP4 E01C52 0 +OP4 E01C53 0 +OP4 E01C54 0 +OP4 E01C55 0 +OP4 E01C56 0 +OP4 E01C57 0 +OP4 E01C58 0 +OP4 E01C59 0 +OP4 E01C5A 0 +OP4 E01C5B 0 +OP4 E01C5C 0 +OP4 E01C5D 0 +OP4 E01C5E 0 +OP4 E01C5F 0 +OP4 E01C60 0 +OP4 E01C61 0 +OP4 E01C62 0 +OP4 E01C63 0 +OP4 E01C64 0 +OP4 E01C65 0 +OP4 E01C66 0 +OP4 E01C67 0 +OP4 E01C68 0 +OP4 E01C69 0 +OP4 E01C6A 0 +OP4 E01C6B 0 +OP4 E01C6C 0 +OP4 E01C6D 0 +OP4 E01C6E 0 +OP4 E01C6F 0 +OP4 E01C70 0 +OP4 E01C71 0 +OP4 E01C72 0 +OP4 E01C73 0 +OP4 E01C74 0 +OP4 E01C75 0 +OP4 E01C76 0 +OP4 E01C77 0 +OP4 E01C78 0 +OP4 E01C79 0 +OP4 E01C7A 0 +OP4 E01C7B 0 +OP4 E01C7C 0 +OP4 E01C7D 0 +OP4 E01C7E 0 +OP4 E01C7F 0 +OP4 E01C80 0 +OP4 E01C81 0 +OP4 E01C82 0 +OP4 E01C83 0 +OP4 E01C84 0 +OP4 E01C85 0 +OP4 E01C86 0 +OP4 E01C87 0 +OP4 E01C88 0 +OP4 E01C89 0 +OP4 E01C8A 0 +OP4 E01C8B 0 +OP4 E01C8C 0 +OP4 E01C8D 0 +OP4 E01C8E 0 +OP4 E01C8F 0 +OP4 E01C90 0 +OP4 E01C91 0 +OP4 E01C92 0 +OP4 E01C93 0 +OP4 E01C94 0 +OP4 E01C95 0 +OP4 E01C96 0 +OP4 E01C97 0 +OP4 E01C98 0 +OP4 E01C99 0 +OP4 E01C9A 0 +OP4 E01C9B 0 +OP4 E01C9C 0 +OP4 E01C9D 0 +OP4 E01C9E 0 +OP4 E01C9F 0 +OP4 E01CA0 0 +OP4 E01CA1 0 +OP4 E01CA2 0 +OP4 E01CA3 0 +OP4 E01CA4 0 +OP4 E01CA5 0 +OP4 E01CA6 0 +OP4 E01CA7 0 +OP4 E01CA8 0 +OP4 E01CA9 0 +OP4 E01CAA 0 +OP4 E01CAB 0 +OP4 E01CAC 0 +OP4 E01CAD 0 +OP4 E01CAE 0 +OP4 E01CAF 0 +OP4 E01CB0 0 +OP4 E01CB1 0 +OP4 E01CB2 0 +OP4 E01CB3 0 +OP4 E01CB4 0 +OP4 E01CB5 0 +OP4 E01CB6 0 +OP4 E01CB7 0 +OP4 E01CB8 0 +OP4 E01CB9 0 +OP4 E01CBA 0 +OP4 E01CBB 0 +OP4 E01CBC 0 +OP4 E01CBD 0 +OP4 E01CBE 0 +OP4 E01CBF 0 +OP4 E01CC0 0 +OP4 E01CC1 0 +OP4 E01CC2 0 +OP4 E01CC3 0 +OP4 E01CC4 0 +OP4 E01CC5 0 +OP4 E01CC6 0 +OP4 E01CC7 0 +OP4 E01CC8 0 +OP4 E01CC9 0 +OP4 E01CCA 0 +OP4 E01CCB 0 +OP4 E01CCC 0 +OP4 E01CCD 0 +OP4 E01CCE 0 +OP4 E01CCF 0 +OP4 E01CD0 0 +OP4 E01CD1 0 +OP4 E01CD2 0 +OP4 E01CD3 0 +OP4 E01CD4 0 +OP4 E01CD5 0 +OP4 E01CD6 0 +OP4 E01CD7 0 +OP4 E01CD8 0 +OP4 E01CD9 0 +OP4 E01CDA 0 +OP4 E01CDB 0 +OP4 E01CDC 0 +OP4 E01CDD 0 +OP4 E01CDE 0 +OP4 E01CDF 0 +OP4 E01CE0 0 +OP4 E01CE1 0 +OP4 E01CE2 0 +OP4 E01CE3 0 +OP4 E01CE4 0 +OP4 E01CE5 0 +OP4 E01CE6 0 +OP4 E01CE7 0 +OP4 E01CE8 0 +OP4 E01CE9 0 +OP4 E01CEA 0 +OP4 E01CEB 0 +OP4 E01CEC 0 +OP4 E01CED 0 +OP4 E01CEE 0 +OP4 E01CEF 0 +OP4 E01CF0 0 +OP4 E01CF1 0 +OP4 E01CF2 0 +OP4 E01CF3 0 +OP4 E01CF4 0 +OP4 E01CF5 0 +OP4 E01CF6 0 +OP4 E01CF7 0 +OP4 E01CF8 0 +OP4 E01CF9 0 +OP4 E01CFA 0 +OP4 E01CFB 0 +OP4 E01CFC 0 +OP4 E01CFD 0 +OP4 E01CFE 0 +OP4 E01CFF 0 +OP4 E01D00 0 +OP4 E01D01 0 +OP4 E01D02 0 +OP4 E01D03 0 +OP4 E01D04 0 +OP4 E01D05 0 +OP4 E01D06 0 +OP4 E01D07 0 +OP4 E01D08 0 +OP4 E01D09 0 +OP4 E01D0A 0 +OP4 E01D0B 0 +OP4 E01D0C 0 +OP4 E01D0D 0 +OP4 E01D0E 0 +OP4 E01D0F 0 +OP4 E01D10 0 +OP4 E01D11 0 +OP4 E01D12 0 +OP4 E01D13 0 +OP4 E01D14 0 +OP4 E01D15 0 +OP4 E01D16 0 +OP4 E01D17 0 +OP4 E01D18 0 +OP4 E01D19 0 +OP4 E01D1A 0 +OP4 E01D1B 0 +OP4 E01D1C 0 +OP4 E01D1D 0 +OP4 E01D1E 0 +OP4 E01D1F 0 +OP4 E01D20 0 +OP4 E01D21 0 +OP4 E01D22 0 +OP4 E01D23 0 +OP4 E01D24 0 +OP4 E01D25 0 +OP4 E01D26 0 +OP4 E01D27 0 +OP4 E01D28 0 +OP4 E01D29 0 +OP4 E01D2A 0 +OP4 E01D2B 0 +OP4 E01D2C 0 +OP4 E01D2D 0 +OP4 E01D2E 0 +OP4 E01D2F 0 +OP4 E01D30 0 +OP4 E01D31 0 +OP4 E01D32 0 +OP4 E01D33 0 +OP4 E01D34 0 +OP4 E01D35 0 +OP4 E01D36 0 +OP4 E01D37 0 +OP4 E01D38 0 +OP4 E01D39 0 +OP4 E01D3A 0 +OP4 E01D3B 0 +OP4 E01D3C 0 +OP4 E01D3D 0 +OP4 E01D3E 0 +OP4 E01D3F 0 +OP4 E01D40 0 +OP4 E01D41 0 +OP4 E01D42 0 +OP4 E01D43 0 +OP4 E01D44 0 +OP4 E01D45 0 +OP4 E01D46 0 +OP4 E01D47 0 +OP4 E01D48 0 +OP4 E01D49 0 +OP4 E01D4A 0 +OP4 E01D4B 0 +OP4 E01D4C 0 +OP4 E01D4D 0 +OP4 E01D4E 0 +OP4 E01D4F 0 +OP4 E01D50 0 +OP4 E01D51 0 +OP4 E01D52 0 +OP4 E01D53 0 +OP4 E01D54 0 +OP4 E01D55 0 +OP4 E01D56 0 +OP4 E01D57 0 +OP4 E01D58 0 +OP4 E01D59 0 +OP4 E01D5A 0 +OP4 E01D5B 0 +OP4 E01D5C 0 +OP4 E01D5D 0 +OP4 E01D5E 0 +OP4 E01D5F 0 +OP4 E01D60 0 +OP4 E01D61 0 +OP4 E01D62 0 +OP4 E01D63 0 +OP4 E01D64 0 +OP4 E01D65 0 +OP4 E01D66 0 +OP4 E01D67 0 +OP4 E01D68 0 +OP4 E01D69 0 +OP4 E01D6A 0 +OP4 E01D6B 0 +OP4 E01D6C 0 +OP4 E01D6D 0 +OP4 E01D6E 0 +OP4 E01D6F 0 +OP4 E01D70 0 +OP4 E01D71 0 +OP4 E01D72 0 +OP4 E01D73 0 +OP4 E01D74 0 +OP4 E01D75 0 +OP4 E01D76 0 +OP4 E01D77 0 +OP4 E01D78 0 +OP4 E01D79 0 +OP4 E01D7A 0 +OP4 E01D7B 0 +OP4 E01D7C 0 +OP4 E01D7D 0 +OP4 E01D7E 0 +OP4 E01D7F 0 +OP4 E01D80 0 +OP4 E01D81 0 +OP4 E01D82 0 +OP4 E01D83 0 +OP4 E01D84 0 +OP4 E01D85 0 +OP4 E01D86 0 +OP4 E01D87 0 +OP4 E01D88 0 +OP4 E01D89 0 +OP4 E01D8A 0 +OP4 E01D8B 0 +OP4 E01D8C 0 +OP4 E01D8D 0 +OP4 E01D8E 0 +OP4 E01D8F 0 +OP4 E01D90 0 +OP4 E01D91 0 +OP4 E01D92 0 +OP4 E01D93 0 +OP4 E01D94 0 +OP4 E01D95 0 +OP4 E01D96 0 +OP4 E01D97 0 +OP4 E01D98 0 +OP4 E01D99 0 +OP4 E01D9A 0 +OP4 E01D9B 0 +OP4 E01D9C 0 +OP4 E01D9D 0 +OP4 E01D9E 0 +OP4 E01D9F 0 +OP4 E01DA0 0 +OP4 E01DA1 0 +OP4 E01DA2 0 +OP4 E01DA3 0 +OP4 E01DA4 0 +OP4 E01DA5 0 +OP4 E01DA6 0 +OP4 E01DA7 0 +OP4 E01DA8 0 +OP4 E01DA9 0 +OP4 E01DAA 0 +OP4 E01DAB 0 +OP4 E01DAC 0 +OP4 E01DAD 0 +OP4 E01DAE 0 +OP4 E01DAF 0 +OP4 E01DB0 0 +OP4 E01DB1 0 +OP4 E01DB2 0 +OP4 E01DB3 0 +OP4 E01DB4 0 +OP4 E01DB5 0 +OP4 E01DB6 0 +OP4 E01DB7 0 +OP4 E01DB8 0 +OP4 E01DB9 0 +OP4 E01DBA 0 +OP4 E01DBB 0 +OP4 E01DBC 0 +OP4 E01DBD 0 +OP4 E01DBE 0 +OP4 E01DBF 0 +OP4 E01DC0 0 +OP4 E01DC1 0 +OP4 E01DC2 0 +OP4 E01DC3 0 +OP4 E01DC4 0 +OP4 E01DC5 0 +OP4 E01DC6 0 +OP4 E01DC7 0 +OP4 E01DC8 0 +OP4 E01DC9 0 +OP4 E01DCA 0 +OP4 E01DCB 0 +OP4 E01DCC 0 +OP4 E01DCD 0 +OP4 E01DCE 0 +OP4 E01DCF 0 +OP4 E01DD0 0 +OP4 E01DD1 0 +OP4 E01DD2 0 +OP4 E01DD3 0 +OP4 E01DD4 0 +OP4 E01DD5 0 +OP4 E01DD6 0 +OP4 E01DD7 0 +OP4 E01DD8 0 +OP4 E01DD9 0 +OP4 E01DDA 0 +OP4 E01DDB 0 +OP4 E01DDC 0 +OP4 E01DDD 0 +OP4 E01DDE 0 +OP4 E01DDF 0 +OP4 E01DE0 0 +OP4 E01DE1 0 +OP4 E01DE2 0 +OP4 E01DE3 0 +OP4 E01DE4 0 +OP4 E01DE5 0 +OP4 E01DE6 0 +OP4 E01DE7 0 +OP4 E01DE8 0 +OP4 E01DE9 0 +OP4 E01DEA 0 +OP4 E01DEB 0 +OP4 E01DEC 0 +OP4 E01DED 0 +OP4 E01DEE 0 +OP4 E01DEF 0 +OP4 E01DF0 0 +OP4 E01DF1 0 +OP4 E01DF2 0 +OP4 E01DF3 0 +OP4 E01DF4 0 +OP4 E01DF5 0 +OP4 E01DF6 0 +OP4 E01DF7 0 +OP4 E01DF8 0 +OP4 E01DF9 0 +OP4 E01DFA 0 +OP4 E01DFB 0 +OP4 E01DFC 0 +OP4 E01DFD 0 +OP4 E01DFE 0 +OP4 E01DFF 0 +OP4 E01E00 0 +OP4 E01E01 0 +OP4 E01E02 0 +OP4 E01E03 0 +OP4 E01E04 0 +OP4 E01E05 0 +OP4 E01E06 0 +OP4 E01E07 0 +OP4 E01E08 0 +OP4 E01E09 0 +OP4 E01E0A 0 +OP4 E01E0B 0 +OP4 E01E0C 0 +OP4 E01E0D 0 +OP4 E01E0E 0 +OP4 E01E0F 0 +OP4 E01E10 0 +OP4 E01E11 0 +OP4 E01E12 0 +OP4 E01E13 0 +OP4 E01E14 0 +OP4 E01E15 0 +OP4 E01E16 0 +OP4 E01E17 0 +OP4 E01E18 0 +OP4 E01E19 0 +OP4 E01E1A 0 +OP4 E01E1B 0 +OP4 E01E1C 0 +OP4 E01E1D 0 +OP4 E01E1E 0 +OP4 E01E1F 0 +OP4 E01E20 0 +OP4 E01E21 0 +OP4 E01E22 0 +OP4 E01E23 0 +OP4 E01E24 0 +OP4 E01E25 0 +OP4 E01E26 0 +OP4 E01E27 0 +OP4 E01E28 0 +OP4 E01E29 0 +OP4 E01E2A 0 +OP4 E01E2B 0 +OP4 E01E2C 0 +OP4 E01E2D 0 +OP4 E01E2E 0 +OP4 E01E2F 0 +OP4 E01E30 0 +OP4 E01E31 0 +OP4 E01E32 0 +OP4 E01E33 0 +OP4 E01E34 0 +OP4 E01E35 0 +OP4 E01E36 0 +OP4 E01E37 0 +OP4 E01E38 0 +OP4 E01E39 0 +OP4 E01E3A 0 +OP4 E01E3B 0 +OP4 E01E3C 0 +OP4 E01E3D 0 +OP4 E01E3E 0 +OP4 E01E3F 0 +OP4 E01E40 0 +OP4 E01E41 0 +OP4 E01E42 0 +OP4 E01E43 0 +OP4 E01E44 0 +OP4 E01E45 0 +OP4 E01E46 0 +OP4 E01E47 0 +OP4 E01E48 0 +OP4 E01E49 0 +OP4 E01E4A 0 +OP4 E01E4B 0 +OP4 E01E4C 0 +OP4 E01E4D 0 +OP4 E01E4E 0 +OP4 E01E4F 0 +OP4 E01E50 0 +OP4 E01E51 0 +OP4 E01E52 0 +OP4 E01E53 0 +OP4 E01E54 0 +OP4 E01E55 0 +OP4 E01E56 0 +OP4 E01E57 0 +OP4 E01E58 0 +OP4 E01E59 0 +OP4 E01E5A 0 +OP4 E01E5B 0 +OP4 E01E5C 0 +OP4 E01E5D 0 +OP4 E01E5E 0 +OP4 E01E5F 0 +OP4 E01E60 0 +OP4 E01E61 0 +OP4 E01E62 0 +OP4 E01E63 0 +OP4 E01E64 0 +OP4 E01E65 0 +OP4 E01E66 0 +OP4 E01E67 0 +OP4 E01E68 0 +OP4 E01E69 0 +OP4 E01E6A 0 +OP4 E01E6B 0 +OP4 E01E6C 0 +OP4 E01E6D 0 +OP4 E01E6E 0 +OP4 E01E6F 0 +OP4 E01E70 0 +OP4 E01E71 0 +OP4 E01E72 0 +OP4 E01E73 0 +OP4 E01E74 0 +OP4 E01E75 0 +OP4 E01E76 0 +OP4 E01E77 0 +OP4 E01E78 0 +OP4 E01E79 0 +OP4 E01E7A 0 +OP4 E01E7B 0 +OP4 E01E7C 0 +OP4 E01E7D 0 +OP4 E01E7E 0 +OP4 E01E7F 0 +OP4 E01E80 0 +OP4 E01E81 0 +OP4 E01E82 0 +OP4 E01E83 0 +OP4 E01E84 0 +OP4 E01E85 0 +OP4 E01E86 0 +OP4 E01E87 0 +OP4 E01E88 0 +OP4 E01E89 0 +OP4 E01E8A 0 +OP4 E01E8B 0 +OP4 E01E8C 0 +OP4 E01E8D 0 +OP4 E01E8E 0 +OP4 E01E8F 0 +OP4 E01E90 0 +OP4 E01E91 0 +OP4 E01E92 0 +OP4 E01E93 0 +OP4 E01E94 0 +OP4 E01E95 0 +OP4 E01E96 0 +OP4 E01E97 0 +OP4 E01E98 0 +OP4 E01E99 0 +OP4 E01E9A 0 +OP4 E01E9B 0 +OP4 E01E9C 0 +OP4 E01E9D 0 +OP4 E01E9E 0 +OP4 E01E9F 0 +OP4 E01EA0 0 +OP4 E01EA1 0 +OP4 E01EA2 0 +OP4 E01EA3 0 +OP4 E01EA4 0 +OP4 E01EA5 0 +OP4 E01EA6 0 +OP4 E01EA7 0 +OP4 E01EA8 0 +OP4 E01EA9 0 +OP4 E01EAA 0 +OP4 E01EAB 0 +OP4 E01EAC 0 +OP4 E01EAD 0 +OP4 E01EAE 0 +OP4 E01EAF 0 +OP4 E01EB0 0 +OP4 E01EB1 0 +OP4 E01EB2 0 +OP4 E01EB3 0 +OP4 E01EB4 0 +OP4 E01EB5 0 +OP4 E01EB6 0 +OP4 E01EB7 0 +OP4 E01EB8 0 +OP4 E01EB9 0 +OP4 E01EBA 0 +OP4 E01EBB 0 +OP4 E01EBC 0 +OP4 E01EBD 0 +OP4 E01EBE 0 +OP4 E01EBF 0 +OP4 E01EC0 0 +OP4 E01EC1 0 +OP4 E01EC2 0 +OP4 E01EC3 0 +OP4 E01EC4 0 +OP4 E01EC5 0 +OP4 E01EC6 0 +OP4 E01EC7 0 +OP4 E01EC8 0 +OP4 E01EC9 0 +OP4 E01ECA 0 +OP4 E01ECB 0 +OP4 E01ECC 0 +OP4 E01ECD 0 +OP4 E01ECE 0 +OP4 E01ECF 0 +OP4 E01ED0 0 +OP4 E01ED1 0 +OP4 E01ED2 0 +OP4 E01ED3 0 +OP4 E01ED4 0 +OP4 E01ED5 0 +OP4 E01ED6 0 +OP4 E01ED7 0 +OP4 E01ED8 0 +OP4 E01ED9 0 +OP4 E01EDA 0 +OP4 E01EDB 0 +OP4 E01EDC 0 +OP4 E01EDD 0 +OP4 E01EDE 0 +OP4 E01EDF 0 +OP4 E01EE0 0 +OP4 E01EE1 0 +OP4 E01EE2 0 +OP4 E01EE3 0 +OP4 E01EE4 0 +OP4 E01EE5 0 +OP4 E01EE6 0 +OP4 E01EE7 0 +OP4 E01EE8 0 +OP4 E01EE9 0 +OP4 E01EEA 0 +OP4 E01EEB 0 +OP4 E01EEC 0 +OP4 E01EED 0 +OP4 E01EEE 0 +OP4 E01EEF 0 +OP4 E01EF0 0 +OP4 E01EF1 0 +OP4 E01EF2 0 +OP4 E01EF3 0 +OP4 E01EF4 0 +OP4 E01EF5 0 +OP4 E01EF6 0 +OP4 E01EF7 0 +OP4 E01EF8 0 +OP4 E01EF9 0 +OP4 E01EFA 0 +OP4 E01EFB 0 +OP4 E01EFC 0 +OP4 E01EFD 0 +OP4 E01EFE 0 +OP4 E01EFF 0 +OP4 E01F00 0 +OP4 E01F01 0 +OP4 E01F02 0 +OP4 E01F03 0 +OP4 E01F04 0 +OP4 E01F05 0 +OP4 E01F06 0 +OP4 E01F07 0 +OP4 E01F08 0 +OP4 E01F09 0 +OP4 E01F0A 0 +OP4 E01F0B 0 +OP4 E01F0C 0 +OP4 E01F0D 0 +OP4 E01F0E 0 +OP4 E01F0F 0 +OP4 E01F10 0 +OP4 E01F11 0 +OP4 E01F12 0 +OP4 E01F13 0 +OP4 E01F14 0 +OP4 E01F15 0 +OP4 E01F16 0 +OP4 E01F17 0 +OP4 E01F18 0 +OP4 E01F19 0 +OP4 E01F1A 0 +OP4 E01F1B 0 +OP4 E01F1C 0 +OP4 E01F1D 0 +OP4 E01F1E 0 +OP4 E01F1F 0 +OP4 E01F20 0 +OP4 E01F21 0 +OP4 E01F22 0 +OP4 E01F23 0 +OP4 E01F24 0 +OP4 E01F25 0 +OP4 E01F26 0 +OP4 E01F27 0 +OP4 E01F28 0 +OP4 E01F29 0 +OP4 E01F2A 0 +OP4 E01F2B 0 +OP4 E01F2C 0 +OP4 E01F2D 0 +OP4 E01F2E 0 +OP4 E01F2F 0 +OP4 E01F30 0 +OP4 E01F31 0 +OP4 E01F32 0 +OP4 E01F33 0 +OP4 E01F34 0 +OP4 E01F35 0 +OP4 E01F36 0 +OP4 E01F37 0 +OP4 E01F38 0 +OP4 E01F39 0 +OP4 E01F3A 0 +OP4 E01F3B 0 +OP4 E01F3C 0 +OP4 E01F3D 0 +OP4 E01F3E 0 +OP4 E01F3F 0 +OP4 E01F40 0 +OP4 E01F41 0 +OP4 E01F42 0 +OP4 E01F43 0 +OP4 E01F44 0 +OP4 E01F45 0 +OP4 E01F46 0 +OP4 E01F47 0 +OP4 E01F48 0 +OP4 E01F49 0 +OP4 E01F4A 0 +OP4 E01F4B 0 +OP4 E01F4C 0 +OP4 E01F4D 0 +OP4 E01F4E 0 +OP4 E01F4F 0 +OP4 E01F50 0 +OP4 E01F51 0 +OP4 E01F52 0 +OP4 E01F53 0 +OP4 E01F54 0 +OP4 E01F55 0 +OP4 E01F56 0 +OP4 E01F57 0 +OP4 E01F58 0 +OP4 E01F59 0 +OP4 E01F5A 0 +OP4 E01F5B 0 +OP4 E01F5C 0 +OP4 E01F5D 0 +OP4 E01F5E 0 +OP4 E01F5F 0 +OP4 E01F60 0 +OP4 E01F61 0 +OP4 E01F62 0 +OP4 E01F63 0 +OP4 E01F64 0 +OP4 E01F65 0 +OP4 E01F66 0 +OP4 E01F67 0 +OP4 E01F68 0 +OP4 E01F69 0 +OP4 E01F6A 0 +OP4 E01F6B 0 +OP4 E01F6C 0 +OP4 E01F6D 0 +OP4 E01F6E 0 +OP4 E01F6F 0 +OP4 E01F70 0 +OP4 E01F71 0 +OP4 E01F72 0 +OP4 E01F73 0 +OP4 E01F74 0 +OP4 E01F75 0 +OP4 E01F76 0 +OP4 E01F77 0 +OP4 E01F78 0 +OP4 E01F79 0 +OP4 E01F7A 0 +OP4 E01F7B 0 +OP4 E01F7C 0 +OP4 E01F7D 0 +OP4 E01F7E 0 +OP4 E01F7F 0 +OP4 E01F80 0 +OP4 E01F81 0 +OP4 E01F82 0 +OP4 E01F83 0 +OP4 E01F84 0 +OP4 E01F85 0 +OP4 E01F86 0 +OP4 E01F87 0 +OP4 E01F88 0 +OP4 E01F89 0 +OP4 E01F8A 0 +OP4 E01F8B 0 +OP4 E01F8C 0 +OP4 E01F8D 0 +OP4 E01F8E 0 +OP4 E01F8F 0 +OP4 E01F90 0 +OP4 E01F91 0 +OP4 E01F92 0 +OP4 E01F93 0 +OP4 E01F94 0 +OP4 E01F95 0 +OP4 E01F96 0 +OP4 E01F97 0 +OP4 E01F98 0 +OP4 E01F99 0 +OP4 E01F9A 0 +OP4 E01F9B 0 +OP4 E01F9C 0 +OP4 E01F9D 0 +OP4 E01F9E 0 +OP4 E01F9F 0 +OP4 E01FA0 0 +OP4 E01FA1 0 +OP4 E01FA2 0 +OP4 E01FA3 0 +OP4 E01FA4 0 +OP4 E01FA5 0 +OP4 E01FA6 0 +OP4 E01FA7 0 +OP4 E01FA8 0 +OP4 E01FA9 0 +OP4 E01FAA 0 +OP4 E01FAB 0 +OP4 E01FAC 0 +OP4 E01FAD 0 +OP4 E01FAE 0 +OP4 E01FAF 0 +OP4 E01FB0 0 +OP4 E01FB1 0 +OP4 E01FB2 0 +OP4 E01FB3 0 +OP4 E01FB4 0 +OP4 E01FB5 0 +OP4 E01FB6 0 +OP4 E01FB7 0 +OP4 E01FB8 0 +OP4 E01FB9 0 +OP4 E01FBA 0 +OP4 E01FBB 0 +OP4 E01FBC 0 +OP4 E01FBD 0 +OP4 E01FBE 0 +OP4 E01FBF 0 +OP4 E01FC0 0 +OP4 E01FC1 0 +OP4 E01FC2 0 +OP4 E01FC3 0 +OP4 E01FC4 0 +OP4 E01FC5 0 +OP4 E01FC6 0 +OP4 E01FC7 0 +OP4 E01FC8 0 +OP4 E01FC9 0 +OP4 E01FCA 0 +OP4 E01FCB 0 +OP4 E01FCC 0 +OP4 E01FCD 0 +OP4 E01FCE 0 +OP4 E01FCF 0 +OP4 E01FD0 0 +OP4 E01FD1 0 +OP4 E01FD2 0 +OP4 E01FD3 0 +OP4 E01FD4 0 +OP4 E01FD5 0 +OP4 E01FD6 0 +OP4 E01FD7 0 +OP4 E01FD8 0 +OP4 E01FD9 0 +OP4 E01FDA 0 +OP4 E01FDB 0 +OP4 E01FDC 0 +OP4 E01FDD 0 +OP4 E01FDE 0 +OP4 E01FDF 0 +OP4 E01FE0 0 +OP4 E01FE1 0 +OP4 E01FE2 0 +OP4 E01FE3 0 +OP4 E01FE4 0 +OP4 E01FE5 0 +OP4 E01FE6 0 +OP4 E01FE7 0 +OP4 E01FE8 0 +OP4 E01FE9 0 +OP4 E01FEA 0 +OP4 E01FEB 0 +OP4 E01FEC 0 +OP4 E01FED 0 +OP4 E01FEE 0 +OP4 E01FEF 0 +OP4 E01FF0 0 +OP4 E01FF1 0 +OP4 E01FF2 0 +OP4 E01FF3 0 +OP4 E01FF4 0 +OP4 E01FF5 0 +OP4 E01FF6 0 +OP4 E01FF7 0 +OP4 E01FF8 0 +OP4 E01FF9 0 +OP4 E01FFA 0 +OP4 E01FFB 0 +OP4 E01FFC 0 +OP4 E01FFD 0 +OP4 E01FFE 0 +OP4 E01FFF 0 +OP4 E02000 0 +OP4 E02001 0 +OP4 E02002 0 +OP4 E02003 0 +OP4 E02004 0 +OP4 E02005 0 +OP4 E02006 0 +OP4 E02007 0 +OP4 E02008 0 +OP4 E02009 0 +OP4 E0200A 0 +OP4 E0200B 0 +OP4 E0200C 0 +OP4 E0200D 0 +OP4 E0200E 0 +OP4 E0200F 0 +OP4 E02010 0 +OP4 E02011 0 +OP4 E02012 0 +OP4 E02013 0 +OP4 E02014 0 +OP4 E02015 0 +OP4 E02016 0 +OP4 E02017 0 +OP4 E02018 0 +OP4 E02019 0 +OP4 E0201A 0 +OP4 E0201B 0 +OP4 E0201C 0 +OP4 E0201D 0 +OP4 E0201E 0 +OP4 E0201F 0 +OP4 E02020 0 +OP4 E02021 0 +OP4 E02022 0 +OP4 E02023 0 +OP4 E02024 0 +OP4 E02025 0 +OP4 E02026 0 +OP4 E02027 0 +OP4 E02028 0 +OP4 E02029 0 +OP4 E0202A 0 +OP4 E0202B 0 +OP4 E0202C 0 +OP4 E0202D 0 +OP4 E0202E 0 +OP4 E0202F 0 +OP4 E02030 0 +OP4 E02031 0 +OP4 E02032 0 +OP4 E02033 0 +OP4 E02034 0 +OP4 E02035 0 +OP4 E02036 0 +OP4 E02037 0 +OP4 E02038 0 +OP4 E02039 0 +OP4 E0203A 0 +OP4 E0203B 0 +OP4 E0203C 0 +OP4 E0203D 0 +OP4 E0203E 0 +OP4 E0203F 0 +OP4 E02040 0 +OP4 E02041 0 +OP4 E02042 0 +OP4 E02043 0 +OP4 E02044 0 +OP4 E02045 0 +OP4 E02046 0 +OP4 E02047 0 +OP4 E02048 0 +OP4 E02049 0 +OP4 E0204A 0 +OP4 E0204B 0 +OP4 E0204C 0 +OP4 E0204D 0 +OP4 E0204E 0 +OP4 E0204F 0 +OP4 E02050 0 +OP4 E02051 0 +OP4 E02052 0 +OP4 E02053 0 +OP4 E02054 0 +OP4 E02055 0 +OP4 E02056 0 +OP4 E02057 0 +OP4 E02058 0 +OP4 E02059 0 +OP4 E0205A 0 +OP4 E0205B 0 +OP4 E0205C 0 +OP4 E0205D 0 +OP4 E0205E 0 +OP4 E0205F 0 +OP4 E02060 0 +OP4 E02061 0 +OP4 E02062 0 +OP4 E02063 0 +OP4 E02064 0 +OP4 E02065 0 +OP4 E02066 0 +OP4 E02067 0 +OP4 E02068 0 +OP4 E02069 0 +OP4 E0206A 0 +OP4 E0206B 0 +OP4 E0206C 0 +OP4 E0206D 0 +OP4 E0206E 0 +OP4 E0206F 0 +OP4 E02070 0 +OP4 E02071 0 +OP4 E02072 0 +OP4 E02073 0 +OP4 E02074 0 +OP4 E02075 0 +OP4 E02076 0 +OP4 E02077 0 +OP4 E02078 0 +OP4 E02079 0 +OP4 E0207A 0 +OP4 E0207B 0 +OP4 E0207C 0 +OP4 E0207D 0 +OP4 E0207E 0 +OP4 E0207F 0 +OP4 E02080 0 +OP4 E02081 0 +OP4 E02082 0 +OP4 E02083 0 +OP4 E02084 0 +OP4 E02085 0 +OP4 E02086 0 +OP4 E02087 0 +OP4 E02088 0 +OP4 E02089 0 +OP4 E0208A 0 +OP4 E0208B 0 +OP4 E0208C 0 +OP4 E0208D 0 +OP4 E0208E 0 +OP4 E0208F 0 +OP4 E02090 0 +OP4 E02091 0 +OP4 E02092 0 +OP4 E02093 0 +OP4 E02094 0 +OP4 E02095 0 +OP4 E02096 0 +OP4 E02097 0 +OP4 E02098 0 +OP4 E02099 0 +OP4 E0209A 0 +OP4 E0209B 0 +OP4 E0209C 0 +OP4 E0209D 0 +OP4 E0209E 0 +OP4 E0209F 0 +OP4 E020A0 0 +OP4 E020A1 0 +OP4 E020A2 0 +OP4 E020A3 0 +OP4 E020A4 0 +OP4 E020A5 0 +OP4 E020A6 0 +OP4 E020A7 0 +OP4 E020A8 0 +OP4 E020A9 0 +OP4 E020AA 0 +OP4 E020AB 0 +OP4 E020AC 0 +OP4 E020AD 0 +OP4 E020AE 0 +OP4 E020AF 0 +OP4 E020B0 0 +OP4 E020B1 0 +OP4 E020B2 0 +OP4 E020B3 0 +OP4 E020B4 0 +OP4 E020B5 0 +OP4 E020B6 0 +OP4 E020B7 0 +OP4 E020B8 0 +OP4 E020B9 0 +OP4 E020BA 0 +OP4 E020BB 0 +OP4 E020BC 0 +OP4 E020BD 0 +OP4 E020BE 0 +OP4 E020BF 0 +OP4 E020C0 0 +OP4 E020C1 0 +OP4 E020C2 0 +OP4 E020C3 0 +OP4 E020C4 0 +OP4 E020C5 0 +OP4 E020C6 0 +OP4 E020C7 0 +OP4 E020C8 0 +OP4 E020C9 0 +OP4 E020CA 0 +OP4 E020CB 0 +OP4 E020CC 0 +OP4 E020CD 0 +OP4 E020CE 0 +OP4 E020CF 0 +OP4 E020D0 0 +OP4 E020D1 0 +OP4 E020D2 0 +OP4 E020D3 0 +OP4 E020D4 0 +OP4 E020D5 0 +OP4 E020D6 0 +OP4 E020D7 0 +OP4 E020D8 0 +OP4 E020D9 0 +OP4 E020DA 0 +OP4 E020DB 0 +OP4 E020DC 0 +OP4 E020DD 0 +OP4 E020DE 0 +OP4 E020DF 0 +OP4 E020E0 0 +OP4 E020E1 0 +OP4 E020E2 0 +OP4 E020E3 0 +OP4 E020E4 0 +OP4 E020E5 0 +OP4 E020E6 0 +OP4 E020E7 0 +OP4 E020E8 0 +OP4 E020E9 0 +OP4 E020EA 0 +OP4 E020EB 0 +OP4 E020EC 0 +OP4 E020ED 0 +OP4 E020EE 0 +OP4 E020EF 0 +OP4 E020F0 0 +OP4 E020F1 0 +OP4 E020F2 0 +OP4 E020F3 0 +OP4 E020F4 0 +OP4 E020F5 0 +OP4 E020F6 0 +OP4 E020F7 0 +OP4 E020F8 0 +OP4 E020F9 0 +OP4 E020FA 0 +OP4 E020FB 0 +OP4 E020FC 0 +OP4 E020FD 0 +OP4 E020FE 0 +OP4 E020FF 0 +OP4 E02100 0 +OP4 E02101 0 +OP4 E02102 0 +OP4 E02103 0 +OP4 E02104 0 +OP4 E02105 0 +OP4 E02106 0 +OP4 E02107 0 +OP4 E02108 0 +OP4 E02109 0 +OP4 E0210A 0 +OP4 E0210B 0 +OP4 E0210C 0 +OP4 E0210D 0 +OP4 E0210E 0 +OP4 E0210F 0 +OP4 E02110 0 +OP4 E02111 0 +OP4 E02112 0 +OP4 E02113 0 +OP4 E02114 0 +OP4 E02115 0 +OP4 E02116 0 +OP4 E02117 0 +OP4 E02118 0 +OP4 E02119 0 +OP4 E0211A 0 +OP4 E0211B 0 +OP4 E0211C 0 +OP4 E0211D 0 +OP4 E0211E 0 +OP4 E0211F 0 +OP4 E02120 0 +OP4 E02121 0 +OP4 E02122 0 +OP4 E02123 0 +OP4 E02124 0 +OP4 E02125 0 +OP4 E02126 0 +OP4 E02127 0 +OP4 E02128 0 +OP4 E02129 0 +OP4 E0212A 0 +OP4 E0212B 0 +OP4 E0212C 0 +OP4 E0212D 0 +OP4 E0212E 0 +OP4 E0212F 0 +OP4 E02130 0 +OP4 E02131 0 +OP4 E02132 0 +OP4 E02133 0 +OP4 E02134 0 +OP4 E02135 0 +OP4 E02136 0 +OP4 E02137 0 +OP4 E02138 0 +OP4 E02139 0 +OP4 E0213A 0 +OP4 E0213B 0 +OP4 E0213C 0 +OP4 E0213D 0 +OP4 E0213E 0 +OP4 E0213F 0 +OP4 E02140 0 +OP4 E02141 0 +OP4 E02142 0 +OP4 E02143 0 +OP4 E02144 0 +OP4 E02145 0 +OP4 E02146 0 +OP4 E02147 0 +OP4 E02148 0 +OP4 E02149 0 +OP4 E0214A 0 +OP4 E0214B 0 +OP4 E0214C 0 +OP4 E0214D 0 +OP4 E0214E 0 +OP4 E0214F 0 +OP4 E02150 0 +OP4 E02151 0 +OP4 E02152 0 +OP4 E02153 0 +OP4 E02154 0 +OP4 E02155 0 +OP4 E02156 0 +OP4 E02157 0 +OP4 E02158 0 +OP4 E02159 0 +OP4 E0215A 0 +OP4 E0215B 0 +OP4 E0215C 0 +OP4 E0215D 0 +OP4 E0215E 0 +OP4 E0215F 0 +OP4 E02160 0 +OP4 E02161 0 +OP4 E02162 0 +OP4 E02163 0 +OP4 E02164 0 +OP4 E02165 0 +OP4 E02166 0 +OP4 E02167 0 +OP4 E02168 0 +OP4 E02169 0 +OP4 E0216A 0 +OP4 E0216B 0 +OP4 E0216C 0 +OP4 E0216D 0 +OP4 E0216E 0 +OP4 E0216F 0 +OP4 E02170 0 +OP4 E02171 0 +OP4 E02172 0 +OP4 E02173 0 +OP4 E02174 0 +OP4 E02175 0 +OP4 E02176 0 +OP4 E02177 0 +OP4 E02178 0 +OP4 E02179 0 +OP4 E0217A 0 +OP4 E0217B 0 +OP4 E0217C 0 +OP4 E0217D 0 +OP4 E0217E 0 +OP4 E0217F 0 +OP4 E02180 0 +OP4 E02181 0 +OP4 E02182 0 +OP4 E02183 0 +OP4 E02184 0 +OP4 E02185 0 +OP4 E02186 0 +OP4 E02187 0 +OP4 E02188 0 +OP4 E02189 0 +OP4 E0218A 0 +OP4 E0218B 0 +OP4 E0218C 0 +OP4 E0218D 0 +OP4 E0218E 0 +OP4 E0218F 0 +OP4 E02190 0 +OP4 E02191 0 +OP4 E02192 0 +OP4 E02193 0 +OP4 E02194 0 +OP4 E02195 0 +OP4 E02196 0 +OP4 E02197 0 +OP4 E02198 0 +OP4 E02199 0 +OP4 E0219A 0 +OP4 E0219B 0 +OP4 E0219C 0 +OP4 E0219D 0 +OP4 E0219E 0 +OP4 E0219F 0 +OP4 E021A0 0 +OP4 E021A1 0 +OP4 E021A2 0 +OP4 E021A3 0 +OP4 E021A4 0 +OP4 E021A5 0 +OP4 E021A6 0 +OP4 E021A7 0 +OP4 E021A8 0 +OP4 E021A9 0 +OP4 E021AA 0 +OP4 E021AB 0 +OP4 E021AC 0 +OP4 E021AD 0 +OP4 E021AE 0 +OP4 E021AF 0 +OP4 E021B0 0 +OP4 E021B1 0 +OP4 E021B2 0 +OP4 E021B3 0 +OP4 E021B4 0 +OP4 E021B5 0 +OP4 E021B6 0 +OP4 E021B7 0 +OP4 E021B8 0 +OP4 E021B9 0 +OP4 E021BA 0 +OP4 E021BB 0 +OP4 E021BC 0 +OP4 E021BD 0 +OP4 E021BE 0 +OP4 E021BF 0 +OP4 E021C0 0 +OP4 E021C1 0 +OP4 E021C2 0 +OP4 E021C3 0 +OP4 E021C4 0 +OP4 E021C5 0 +OP4 E021C6 0 +OP4 E021C7 0 +OP4 E021C8 0 +OP4 E021C9 0 +OP4 E021CA 0 +OP4 E021CB 0 +OP4 E021CC 0 +OP4 E021CD 0 +OP4 E021CE 0 +OP4 E021CF 0 +OP4 E021D0 0 +OP4 E021D1 0 +OP4 E021D2 0 +OP4 E021D3 0 +OP4 E021D4 0 +OP4 E021D5 0 +OP4 E021D6 0 +OP4 E021D7 0 +OP4 E021D8 0 +OP4 E021D9 0 +OP4 E021DA 0 +OP4 E021DB 0 +OP4 E021DC 0 +OP4 E021DD 0 +OP4 E021DE 0 +OP4 E021DF 0 +OP4 E021E0 0 +OP4 E021E1 0 +OP4 E021E2 0 +OP4 E021E3 0 +OP4 E021E4 0 +OP4 E021E5 0 +OP4 E021E6 0 +OP4 E021E7 0 +OP4 E021E8 0 +OP4 E021E9 0 +OP4 E021EA 0 +OP4 E021EB 0 +OP4 E021EC 0 +OP4 E021ED 0 +OP4 E021EE 0 +OP4 E021EF 0 +OP4 E021F0 0 +OP4 E021F1 0 +OP4 E021F2 0 +OP4 E021F3 0 +OP4 E021F4 0 +OP4 E021F5 0 +OP4 E021F6 0 +OP4 E021F7 0 +OP4 E021F8 0 +OP4 E021F9 0 +OP4 E021FA 0 +OP4 E021FB 0 +OP4 E021FC 0 +OP4 E021FD 0 +OP4 E021FE 0 +OP4 E021FF 0 +OP4 E02200 0 +OP4 E02201 0 +OP4 E02202 0 +OP4 E02203 0 +OP4 E02204 0 +OP4 E02205 0 +OP4 E02206 0 +OP4 E02207 0 +OP4 E02208 0 +OP4 E02209 0 +OP4 E0220A 0 +OP4 E0220B 0 +OP4 E0220C 0 +OP4 E0220D 0 +OP4 E0220E 0 +OP4 E0220F 0 +OP4 E02210 0 +OP4 E02211 0 +OP4 E02212 0 +OP4 E02213 0 +OP4 E02214 0 +OP4 E02215 0 +OP4 E02216 0 +OP4 E02217 0 +OP4 E02218 0 +OP4 E02219 0 +OP4 E0221A 0 +OP4 E0221B 0 +OP4 E0221C 0 +OP4 E0221D 0 +OP4 E0221E 0 +OP4 E0221F 0 +OP4 E02220 0 +OP4 E02221 0 +OP4 E02222 0 +OP4 E02223 0 +OP4 E02224 0 +OP4 E02225 0 +OP4 E02226 0 +OP4 E02227 0 +OP4 E02228 0 +OP4 E02229 0 +OP4 E0222A 0 +OP4 E0222B 0 +OP4 E0222C 0 +OP4 E0222D 0 +OP4 E0222E 0 +OP4 E0222F 0 +OP4 E02230 0 +OP4 E02231 0 +OP4 E02232 0 +OP4 E02233 0 +OP4 E02234 0 +OP4 E02235 0 +OP4 E02236 0 +OP4 E02237 0 +OP4 E02238 0 +OP4 E02239 0 +OP4 E0223A 0 +OP4 E0223B 0 +OP4 E0223C 0 +OP4 E0223D 0 +OP4 E0223E 0 +OP4 E0223F 0 +OP4 E02240 0 +OP4 E02241 0 +OP4 E02242 0 +OP4 E02243 0 +OP4 E02244 0 +OP4 E02245 0 +OP4 E02246 0 +OP4 E02247 0 +OP4 E02248 0 +OP4 E02249 0 +OP4 E0224A 0 +OP4 E0224B 0 +OP4 E0224C 0 +OP4 E0224D 0 +OP4 E0224E 0 +OP4 E0224F 0 +OP4 E02250 0 +OP4 E02251 0 +OP4 E02252 0 +OP4 E02253 0 +OP4 E02254 0 +OP4 E02255 0 +OP4 E02256 0 +OP4 E02257 0 +OP4 E02258 0 +OP4 E02259 0 +OP4 E0225A 0 +OP4 E0225B 0 +OP4 E0225C 0 +OP4 E0225D 0 +OP4 E0225E 0 +OP4 E0225F 0 +OP4 E02260 0 +OP4 E02261 0 +OP4 E02262 0 +OP4 E02263 0 +OP4 E02264 0 +OP4 E02265 0 +OP4 E02266 0 +OP4 E02267 0 +OP4 E02268 0 +OP4 E02269 0 +OP4 E0226A 0 +OP4 E0226B 0 +OP4 E0226C 0 +OP4 E0226D 0 +OP4 E0226E 0 +OP4 E0226F 0 +OP4 E02270 0 +OP4 E02271 0 +OP4 E02272 0 +OP4 E02273 0 +OP4 E02274 0 +OP4 E02275 0 +OP4 E02276 0 +OP4 E02277 0 +OP4 E02278 0 +OP4 E02279 0 +OP4 E0227A 0 +OP4 E0227B 0 +OP4 E0227C 0 +OP4 E0227D 0 +OP4 E0227E 0 +OP4 E0227F 0 +OP4 E02280 0 +OP4 E02281 0 +OP4 E02282 0 +OP4 E02283 0 +OP4 E02284 0 +OP4 E02285 0 +OP4 E02286 0 +OP4 E02287 0 +OP4 E02288 0 +OP4 E02289 0 +OP4 E0228A 0 +OP4 E0228B 0 +OP4 E0228C 0 +OP4 E0228D 0 +OP4 E0228E 0 +OP4 E0228F 0 +OP4 E02290 0 +OP4 E02291 0 +OP4 E02292 0 +OP4 E02293 0 +OP4 E02294 0 +OP4 E02295 0 +OP4 E02296 0 +OP4 E02297 0 +OP4 E02298 0 +OP4 E02299 0 +OP4 E0229A 0 +OP4 E0229B 0 +OP4 E0229C 0 +OP4 E0229D 0 +OP4 E0229E 0 +OP4 E0229F 0 +OP4 E022A0 0 +OP4 E022A1 0 +OP4 E022A2 0 +OP4 E022A3 0 +OP4 E022A4 0 +OP4 E022A5 0 +OP4 E022A6 0 +OP4 E022A7 0 +OP4 E022A8 0 +OP4 E022A9 0 +OP4 E022AA 0 +OP4 E022AB 0 +OP4 E022AC 0 +OP4 E022AD 0 +OP4 E022AE 0 +OP4 E022AF 0 +OP4 E022B0 0 +OP4 E022B1 0 +OP4 E022B2 0 +OP4 E022B3 0 +OP4 E022B4 0 +OP4 E022B5 0 +OP4 E022B6 0 +OP4 E022B7 0 +OP4 E022B8 0 +OP4 E022B9 0 +OP4 E022BA 0 +OP4 E022BB 0 +OP4 E022BC 0 +OP4 E022BD 0 +OP4 E022BE 0 +OP4 E022BF 0 +OP4 E022C0 0 +OP4 E022C1 0 +OP4 E022C2 0 +OP4 E022C3 0 +OP4 E022C4 0 +OP4 E022C5 0 +OP4 E022C6 0 +OP4 E022C7 0 +OP4 E022C8 0 +OP4 E022C9 0 +OP4 E022CA 0 +OP4 E022CB 0 +OP4 E022CC 0 +OP4 E022CD 0 +OP4 E022CE 0 +OP4 E022CF 0 +OP4 E022D0 0 +OP4 E022D1 0 +OP4 E022D2 0 +OP4 E022D3 0 +OP4 E022D4 0 +OP4 E022D5 0 +OP4 E022D6 0 +OP4 E022D7 0 +OP4 E022D8 0 +OP4 E022D9 0 +OP4 E022DA 0 +OP4 E022DB 0 +OP4 E022DC 0 +OP4 E022DD 0 +OP4 E022DE 0 +OP4 E022DF 0 +OP4 E022E0 0 +OP4 E022E1 0 +OP4 E022E2 0 +OP4 E022E3 0 +OP4 E022E4 0 +OP4 E022E5 0 +OP4 E022E6 0 +OP4 E022E7 0 +OP4 E022E8 0 +OP4 E022E9 0 +OP4 E022EA 0 +OP4 E022EB 0 +OP4 E022EC 0 +OP4 E022ED 0 +OP4 E022EE 0 +OP4 E022EF 0 +OP4 E022F0 0 +OP4 E022F1 0 +OP4 E022F2 0 +OP4 E022F3 0 +OP4 E022F4 0 +OP4 E022F5 0 +OP4 E022F6 0 +OP4 E022F7 0 +OP4 E022F8 0 +OP4 E022F9 0 +OP4 E022FA 0 +OP4 E022FB 0 +OP4 E022FC 0 +OP4 E022FD 0 +OP4 E022FE 0 +OP4 E022FF 0 +OP4 E02300 0 +OP4 E02301 0 +OP4 E02302 0 +OP4 E02303 0 +OP4 E02304 0 +OP4 E02305 0 +OP4 E02306 0 +OP4 E02307 0 +OP4 E02308 0 +OP4 E02309 0 +OP4 E0230A 0 +OP4 E0230B 0 +OP4 E0230C 0 +OP4 E0230D 0 +OP4 E0230E 0 +OP4 E0230F 0 +OP4 E02310 0 +OP4 E02311 0 +OP4 E02312 0 +OP4 E02313 0 +OP4 E02314 0 +OP4 E02315 0 +OP4 E02316 0 +OP4 E02317 0 +OP4 E02318 0 +OP4 E02319 0 +OP4 E0231A 0 +OP4 E0231B 0 +OP4 E0231C 0 +OP4 E0231D 0 +OP4 E0231E 0 +OP4 E0231F 0 +OP4 E02320 0 +OP4 E02321 0 +OP4 E02322 0 +OP4 E02323 0 +OP4 E02324 0 +OP4 E02325 0 +OP4 E02326 0 +OP4 E02327 0 +OP4 E02328 0 +OP4 E02329 0 +OP4 E0232A 0 +OP4 E0232B 0 +OP4 E0232C 0 +OP4 E0232D 0 +OP4 E0232E 0 +OP4 E0232F 0 +OP4 E02330 0 +OP4 E02331 0 +OP4 E02332 0 +OP4 E02333 0 +OP4 E02334 0 +OP4 E02335 0 +OP4 E02336 0 +OP4 E02337 0 +OP4 E02338 0 +OP4 E02339 0 +OP4 E0233A 0 +OP4 E0233B 0 +OP4 E0233C 0 +OP4 E0233D 0 +OP4 E0233E 0 +OP4 E0233F 0 +OP4 E02340 0 +OP4 E02341 0 +OP4 E02342 0 +OP4 E02343 0 +OP4 E02344 0 +OP4 E02345 0 +OP4 E02346 0 +OP4 E02347 0 +OP4 E02348 0 +OP4 E02349 0 +OP4 E0234A 0 +OP4 E0234B 0 +OP4 E0234C 0 +OP4 E0234D 0 +OP4 E0234E 0 +OP4 E0234F 0 +OP4 E02350 0 +OP4 E02351 0 +OP4 E02352 0 +OP4 E02353 0 +OP4 E02354 0 +OP4 E02355 0 +OP4 E02356 0 +OP4 E02357 0 +OP4 E02358 0 +OP4 E02359 0 +OP4 E0235A 0 +OP4 E0235B 0 +OP4 E0235C 0 +OP4 E0235D 0 +OP4 E0235E 0 +OP4 E0235F 0 +OP4 E02360 0 +OP4 E02361 0 +OP4 E02362 0 +OP4 E02363 0 +OP4 E02364 0 +OP4 E02365 0 +OP4 E02366 0 +OP4 E02367 0 +OP4 E02368 0 +OP4 E02369 0 +OP4 E0236A 0 +OP4 E0236B 0 +OP4 E0236C 0 +OP4 E0236D 0 +OP4 E0236E 0 +OP4 E0236F 0 +OP4 E02370 0 +OP4 E02371 0 +OP4 E02372 0 +OP4 E02373 0 +OP4 E02374 0 +OP4 E02375 0 +OP4 E02376 0 +OP4 E02377 0 +OP4 E02378 0 +OP4 E02379 0 +OP4 E0237A 0 +OP4 E0237B 0 +OP4 E0237C 0 +OP4 E0237D 0 +OP4 E0237E 0 +OP4 E0237F 0 +OP4 E02380 0 +OP4 E02381 0 +OP4 E02382 0 +OP4 E02383 0 +OP4 E02384 0 +OP4 E02385 0 +OP4 E02386 0 +OP4 E02387 0 +OP4 E02388 0 +OP4 E02389 0 +OP4 E0238A 0 +OP4 E0238B 0 +OP4 E0238C 0 +OP4 E0238D 0 +OP4 E0238E 0 +OP4 E0238F 0 +OP4 E02390 0 +OP4 E02391 0 +OP4 E02392 0 +OP4 E02393 0 +OP4 E02394 0 +OP4 E02395 0 +OP4 E02396 0 +OP4 E02397 0 +OP4 E02398 0 +OP4 E02399 0 +OP4 E0239A 0 +OP4 E0239B 0 +OP4 E0239C 0 +OP4 E0239D 0 +OP4 E0239E 0 +OP4 E0239F 0 +OP4 E023A0 0 +OP4 E023A1 0 +OP4 E023A2 0 +OP4 E023A3 0 +OP4 E023A4 0 +OP4 E023A5 0 +OP4 E023A6 0 +OP4 E023A7 0 +OP4 E023A8 0 +OP4 E023A9 0 +OP4 E023AA 0 +OP4 E023AB 0 +OP4 E023AC 0 +OP4 E023AD 0 +OP4 E023AE 0 +OP4 E023AF 0 +OP4 E023B0 0 +OP4 E023B1 0 +OP4 E023B2 0 +OP4 E023B3 0 +OP4 E023B4 0 +OP4 E023B5 0 +OP4 E023B6 0 +OP4 E023B7 0 +OP4 E023B8 0 +OP4 E023B9 0 +OP4 E023BA 0 +OP4 E023BB 0 +OP4 E023BC 0 +OP4 E023BD 0 +OP4 E023BE 0 +OP4 E023BF 0 +OP4 E023C0 0 +OP4 E023C1 0 +OP4 E023C2 0 +OP4 E023C3 0 +OP4 E023C4 0 +OP4 E023C5 0 +OP4 E023C6 0 +OP4 E023C7 0 +OP4 E023C8 0 +OP4 E023C9 0 +OP4 E023CA 0 +OP4 E023CB 0 +OP4 E023CC 0 +OP4 E023CD 0 +OP4 E023CE 0 +OP4 E023CF 0 +OP4 E023D0 0 +OP4 E023D1 0 +OP4 E023D2 0 +OP4 E023D3 0 +OP4 E023D4 0 +OP4 E023D5 0 +OP4 E023D6 0 +OP4 E023D7 0 +OP4 E023D8 0 +OP4 E023D9 0 +OP4 E023DA 0 +OP4 E023DB 0 +OP4 E023DC 0 +OP4 E023DD 0 +OP4 E023DE 0 +OP4 E023DF 0 +OP4 E023E0 0 +OP4 E023E1 0 +OP4 E023E2 0 +OP4 E023E3 0 +OP4 E023E4 0 +OP4 E023E5 0 +OP4 E023E6 0 +OP4 E023E7 0 +OP4 E023E8 0 +OP4 E023E9 0 +OP4 E023EA 0 +OP4 E023EB 0 +OP4 E023EC 0 +OP4 E023ED 0 +OP4 E023EE 0 +OP4 E023EF 0 +OP4 E023F0 0 +OP4 E023F1 0 +OP4 E023F2 0 +OP4 E023F3 0 +OP4 E023F4 0 +OP4 E023F5 0 +OP4 E023F6 0 +OP4 E023F7 0 +OP4 E023F8 0 +OP4 E023F9 0 +OP4 E023FA 0 +OP4 E023FB 0 +OP4 E023FC 0 +OP4 E023FD 0 +OP4 E023FE 0 +OP4 E023FF 0 +OP4 E02400 0 +OP4 E02401 0 +OP4 E02402 0 +OP4 E02403 0 +OP4 E02404 0 +OP4 E02405 0 +OP4 E02406 0 +OP4 E02407 0 +OP4 E02408 0 +OP4 E02409 0 +OP4 E0240A 0 +OP4 E0240B 0 +OP4 E0240C 0 +OP4 E0240D 0 +OP4 E0240E 0 +OP4 E0240F 0 +OP4 E02410 0 +OP4 E02411 0 +OP4 E02412 0 +OP4 E02413 0 +OP4 E02414 0 +OP4 E02415 0 +OP4 E02416 0 +OP4 E02417 0 +OP4 E02418 0 +OP4 E02419 0 +OP4 E0241A 0 +OP4 E0241B 0 +OP4 E0241C 0 +OP4 E0241D 0 +OP4 E0241E 0 +OP4 E0241F 0 +OP4 E02420 0 +OP4 E02421 0 +OP4 E02422 0 +OP4 E02423 0 +OP4 E02424 0 +OP4 E02425 0 +OP4 E02426 0 +OP4 E02427 0 +OP4 E02428 0 +OP4 E02429 0 +OP4 E0242A 0 +OP4 E0242B 0 +OP4 E0242C 0 +OP4 E0242D 0 +OP4 E0242E 0 +OP4 E0242F 0 +OP4 E02430 0 +OP4 E02431 0 +OP4 E02432 0 +OP4 E02433 0 +OP4 E02434 0 +OP4 E02435 0 +OP4 E02436 0 +OP4 E02437 0 +OP4 E02438 0 +OP4 E02439 0 +OP4 E0243A 0 +OP4 E0243B 0 +OP4 E0243C 0 +OP4 E0243D 0 +OP4 E0243E 0 +OP4 E0243F 0 +OP4 E02440 0 +OP4 E02441 0 +OP4 E02442 0 +OP4 E02443 0 +OP4 E02444 0 +OP4 E02445 0 +OP4 E02446 0 +OP4 E02447 0 +OP4 E02448 0 +OP4 E02449 0 +OP4 E0244A 0 +OP4 E0244B 0 +OP4 E0244C 0 +OP4 E0244D 0 +OP4 E0244E 0 +OP4 E0244F 0 +OP4 E02450 0 +OP4 E02451 0 +OP4 E02452 0 +OP4 E02453 0 +OP4 E02454 0 +OP4 E02455 0 +OP4 E02456 0 +OP4 E02457 0 +OP4 E02458 0 +OP4 E02459 0 +OP4 E0245A 0 +OP4 E0245B 0 +OP4 E0245C 0 +OP4 E0245D 0 +OP4 E0245E 0 +OP4 E0245F 0 +OP4 E02460 0 +OP4 E02461 0 +OP4 E02462 0 +OP4 E02463 0 +OP4 E02464 0 +OP4 E02465 0 +OP4 E02466 0 +OP4 E02467 0 +OP4 E02468 0 +OP4 E02469 0 +OP4 E0246A 0 +OP4 E0246B 0 +OP4 E0246C 0 +OP4 E0246D 0 +OP4 E0246E 0 +OP4 E0246F 0 +OP4 E02470 0 +OP4 E02471 0 +OP4 E02472 0 +OP4 E02473 0 +OP4 E02474 0 +OP4 E02475 0 +OP4 E02476 0 +OP4 E02477 0 +OP4 E02478 0 +OP4 E02479 0 +OP4 E0247A 0 +OP4 E0247B 0 +OP4 E0247C 0 +OP4 E0247D 0 +OP4 E0247E 0 +OP4 E0247F 0 +OP4 E02480 0 +OP4 E02481 0 +OP4 E02482 0 +OP4 E02483 0 +OP4 E02484 0 +OP4 E02485 0 +OP4 E02486 0 +OP4 E02487 0 +OP4 E02488 0 +OP4 E02489 0 +OP4 E0248A 0 +OP4 E0248B 0 +OP4 E0248C 0 +OP4 E0248D 0 +OP4 E0248E 0 +OP4 E0248F 0 +OP4 E02490 0 +OP4 E02491 0 +OP4 E02492 0 +OP4 E02493 0 +OP4 E02494 0 +OP4 E02495 0 +OP4 E02496 0 +OP4 E02497 0 +OP4 E02498 0 +OP4 E02499 0 +OP4 E0249A 0 +OP4 E0249B 0 +OP4 E0249C 0 +OP4 E0249D 0 +OP4 E0249E 0 +OP4 E0249F 0 +OP4 E024A0 0 +OP4 E024A1 0 +OP4 E024A2 0 +OP4 E024A3 0 +OP4 E024A4 0 +OP4 E024A5 0 +OP4 E024A6 0 +OP4 E024A7 0 +OP4 E024A8 0 +OP4 E024A9 0 +OP4 E024AA 0 +OP4 E024AB 0 +OP4 E024AC 0 +OP4 E024AD 0 +OP4 E024AE 0 +OP4 E024AF 0 +OP4 E024B0 0 +OP4 E024B1 0 +OP4 E024B2 0 +OP4 E024B3 0 +OP4 E024B4 0 +OP4 E024B5 0 +OP4 E024B6 0 +OP4 E024B7 0 +OP4 E024B8 0 +OP4 E024B9 0 +OP4 E024BA 0 +OP4 E024BB 0 +OP4 E024BC 0 +OP4 E024BD 0 +OP4 E024BE 0 +OP4 E024BF 0 +OP4 E024C0 0 +OP4 E024C1 0 +OP4 E024C2 0 +OP4 E024C3 0 +OP4 E024C4 0 +OP4 E024C5 0 +OP4 E024C6 0 +OP4 E024C7 0 +OP4 E024C8 0 +OP4 E024C9 0 +OP4 E024CA 0 +OP4 E024CB 0 +OP4 E024CC 0 +OP4 E024CD 0 +OP4 E024CE 0 +OP4 E024CF 0 +OP4 E024D0 0 +OP4 E024D1 0 +OP4 E024D2 0 +OP4 E024D3 0 +OP4 E024D4 0 +OP4 E024D5 0 +OP4 E024D6 0 +OP4 E024D7 0 +OP4 E024D8 0 +OP4 E024D9 0 +OP4 E024DA 0 +OP4 E024DB 0 +OP4 E024DC 0 +OP4 E024DD 0 +OP4 E024DE 0 +OP4 E024DF 0 +OP4 E024E0 0 +OP4 E024E1 0 +OP4 E024E2 0 +OP4 E024E3 0 +OP4 E024E4 0 +OP4 E024E5 0 +OP4 E024E6 0 +OP4 E024E7 0 +OP4 E024E8 0 +OP4 E024E9 0 +OP4 E024EA 0 +OP4 E024EB 0 +OP4 E024EC 0 +OP4 E024ED 0 +OP4 E024EE 0 +OP4 E024EF 0 +OP4 E024F0 0 +OP4 E024F1 0 +OP4 E024F2 0 +OP4 E024F3 0 +OP4 E024F4 0 +OP4 E024F5 0 +OP4 E024F6 0 +OP4 E024F7 0 +OP4 E024F8 0 +OP4 E024F9 0 +OP4 E024FA 0 +OP4 E024FB 0 +OP4 E024FC 0 +OP4 E024FD 0 +OP4 E024FE 0 +OP4 E024FF 0 +OP4 E02500 0 +OP4 E02501 0 +OP4 E02502 0 +OP4 E02503 0 +OP4 E02504 0 +OP4 E02505 0 +OP4 E02506 0 +OP4 E02507 0 +OP4 E02508 0 +OP4 E02509 0 +OP4 E0250A 0 +OP4 E0250B 0 +OP4 E0250C 0 +OP4 E0250D 0 +OP4 E0250E 0 +OP4 E0250F 0 +OP4 E02510 0 +OP4 E02511 0 +OP4 E02512 0 +OP4 E02513 0 +OP4 E02514 0 +OP4 E02515 0 +OP4 E02516 0 +OP4 E02517 0 +OP4 E02518 0 +OP4 E02519 0 +OP4 E0251A 0 +OP4 E0251B 0 +OP4 E0251C 0 +OP4 E0251D 0 +OP4 E0251E 0 +OP4 E0251F 0 +OP4 E02520 0 +OP4 E02521 0 +OP4 E02522 0 +OP4 E02523 0 +OP4 E02524 0 +OP4 E02525 0 +OP4 E02526 0 +OP4 E02527 0 +OP4 E02528 0 +OP4 E02529 0 +OP4 E0252A 0 +OP4 E0252B 0 +OP4 E0252C 0 +OP4 E0252D 0 +OP4 E0252E 0 +OP4 E0252F 0 +OP4 E02530 0 +OP4 E02531 0 +OP4 E02532 0 +OP4 E02533 0 +OP4 E02534 0 +OP4 E02535 0 +OP4 E02536 0 +OP4 E02537 0 +OP4 E02538 0 +OP4 E02539 0 +OP4 E0253A 0 +OP4 E0253B 0 +OP4 E0253C 0 +OP4 E0253D 0 +OP4 E0253E 0 +OP4 E0253F 0 +OP4 E02540 0 +OP4 E02541 0 +OP4 E02542 0 +OP4 E02543 0 +OP4 E02544 0 +OP4 E02545 0 +OP4 E02546 0 +OP4 E02547 0 +OP4 E02548 0 +OP4 E02549 0 +OP4 E0254A 0 +OP4 E0254B 0 +OP4 E0254C 0 +OP4 E0254D 0 +OP4 E0254E 0 +OP4 E0254F 0 +OP4 E02550 0 +OP4 E02551 0 +OP4 E02552 0 +OP4 E02553 0 +OP4 E02554 0 +OP4 E02555 0 +OP4 E02556 0 +OP4 E02557 0 +OP4 E02558 0 +OP4 E02559 0 +OP4 E0255A 0 +OP4 E0255B 0 +OP4 E0255C 0 +OP4 E0255D 0 +OP4 E0255E 0 +OP4 E0255F 0 +OP4 E02560 0 +OP4 E02561 0 +OP4 E02562 0 +OP4 E02563 0 +OP4 E02564 0 +OP4 E02565 0 +OP4 E02566 0 +OP4 E02567 0 +OP4 E02568 0 +OP4 E02569 0 +OP4 E0256A 0 +OP4 E0256B 0 +OP4 E0256C 0 +OP4 E0256D 0 +OP4 E0256E 0 +OP4 E0256F 0 +OP4 E02570 0 +OP4 E02571 0 +OP4 E02572 0 +OP4 E02573 0 +OP4 E02574 0 +OP4 E02575 0 +OP4 E02576 0 +OP4 E02577 0 +OP4 E02578 0 +OP4 E02579 0 +OP4 E0257A 0 +OP4 E0257B 0 +OP4 E0257C 0 +OP4 E0257D 0 +OP4 E0257E 0 +OP4 E0257F 0 +OP4 E02580 0 +OP4 E02581 0 +OP4 E02582 0 +OP4 E02583 0 +OP4 E02584 0 +OP4 E02585 0 +OP4 E02586 0 +OP4 E02587 0 +OP4 E02588 0 +OP4 E02589 0 +OP4 E0258A 0 +OP4 E0258B 0 +OP4 E0258C 0 +OP4 E0258D 0 +OP4 E0258E 0 +OP4 E0258F 0 +OP4 E02590 0 +OP4 E02591 0 +OP4 E02592 0 +OP4 E02593 0 +OP4 E02594 0 +OP4 E02595 0 +OP4 E02596 0 +OP4 E02597 0 +OP4 E02598 0 +OP4 E02599 0 +OP4 E0259A 0 +OP4 E0259B 0 +OP4 E0259C 0 +OP4 E0259D 0 +OP4 E0259E 0 +OP4 E0259F 0 +OP4 E025A0 0 +OP4 E025A1 0 +OP4 E025A2 0 +OP4 E025A3 0 +OP4 E025A4 0 +OP4 E025A5 0 +OP4 E025A6 0 +OP4 E025A7 0 +OP4 E025A8 0 +OP4 E025A9 0 +OP4 E025AA 0 +OP4 E025AB 0 +OP4 E025AC 0 +OP4 E025AD 0 +OP4 E025AE 0 +OP4 E025AF 0 +OP4 E025B0 0 +OP4 E025B1 0 +OP4 E025B2 0 +OP4 E025B3 0 +OP4 E025B4 0 +OP4 E025B5 0 +OP4 E025B6 0 +OP4 E025B7 0 +OP4 E025B8 0 +OP4 E025B9 0 +OP4 E025BA 0 +OP4 E025BB 0 +OP4 E025BC 0 +OP4 E025BD 0 +OP4 E025BE 0 +OP4 E025BF 0 +OP4 E025C0 0 +OP4 E025C1 0 +OP4 E025C2 0 +OP4 E025C3 0 +OP4 E025C4 0 +OP4 E025C5 0 +OP4 E025C6 0 +OP4 E025C7 0 +OP4 E025C8 0 +OP4 E025C9 0 +OP4 E025CA 0 +OP4 E025CB 0 +OP4 E025CC 0 +OP4 E025CD 0 +OP4 E025CE 0 +OP4 E025CF 0 +OP4 E025D0 0 +OP4 E025D1 0 +OP4 E025D2 0 +OP4 E025D3 0 +OP4 E025D4 0 +OP4 E025D5 0 +OP4 E025D6 0 +OP4 E025D7 0 +OP4 E025D8 0 +OP4 E025D9 0 +OP4 E025DA 0 +OP4 E025DB 0 +OP4 E025DC 0 +OP4 E025DD 0 +OP4 E025DE 0 +OP4 E025DF 0 +OP4 E025E0 0 +OP4 E025E1 0 +OP4 E025E2 0 +OP4 E025E3 0 +OP4 E025E4 0 +OP4 E025E5 0 +OP4 E025E6 0 +OP4 E025E7 0 +OP4 E025E8 0 +OP4 E025E9 0 +OP4 E025EA 0 +OP4 E025EB 0 +OP4 E025EC 0 +OP4 E025ED 0 +OP4 E025EE 0 +OP4 E025EF 0 +OP4 E025F0 0 +OP4 E025F1 0 +OP4 E025F2 0 +OP4 E025F3 0 +OP4 E025F4 0 +OP4 E025F5 0 +OP4 E025F6 0 +OP4 E025F7 0 +OP4 E025F8 0 +OP4 E025F9 0 +OP4 E025FA 0 +OP4 E025FB 0 +OP4 E025FC 0 +OP4 E025FD 0 +OP4 E025FE 0 +OP4 E025FF 0 +OP4 E02600 0 +OP4 E02601 0 +OP4 E02602 0 +OP4 E02603 0 +OP4 E02604 0 +OP4 E02605 0 +OP4 E02606 0 +OP4 E02607 0 +OP4 E02608 0 +OP4 E02609 0 +OP4 E0260A 0 +OP4 E0260B 0 +OP4 E0260C 0 +OP4 E0260D 0 +OP4 E0260E 0 +OP4 E0260F 0 +OP4 E02610 0 +OP4 E02611 0 +OP4 E02612 0 +OP4 E02613 0 +OP4 E02614 0 +OP4 E02615 0 +OP4 E02616 0 +OP4 E02617 0 +OP4 E02618 0 +OP4 E02619 0 +OP4 E0261A 0 +OP4 E0261B 0 +OP4 E0261C 0 +OP4 E0261D 0 +OP4 E0261E 0 +OP4 E0261F 0 +OP4 E02620 0 +OP4 E02621 0 +OP4 E02622 0 +OP4 E02623 0 +OP4 E02624 0 +OP4 E02625 0 +OP4 E02626 0 +OP4 E02627 0 +OP4 E02628 0 +OP4 E02629 0 +OP4 E0262A 0 +OP4 E0262B 0 +OP4 E0262C 0 +OP4 E0262D 0 +OP4 E0262E 0 +OP4 E0262F 0 +OP4 E02630 0 +OP4 E02631 0 +OP4 E02632 0 +OP4 E02633 0 +OP4 E02634 0 +OP4 E02635 0 +OP4 E02636 0 +OP4 E02637 0 +OP4 E02638 0 +OP4 E02639 0 +OP4 E0263A 0 +OP4 E0263B 0 +OP4 E0263C 0 +OP4 E0263D 0 +OP4 E0263E 0 +OP4 E0263F 0 +OP4 E02640 0 +OP4 E02641 0 +OP4 E02642 0 +OP4 E02643 0 +OP4 E02644 0 +OP4 E02645 0 +OP4 E02646 0 +OP4 E02647 0 +OP4 E02648 0 +OP4 E02649 0 +OP4 E0264A 0 +OP4 E0264B 0 +OP4 E0264C 0 +OP4 E0264D 0 +OP4 E0264E 0 +OP4 E0264F 0 +OP4 E02650 0 +OP4 E02651 0 +OP4 E02652 0 +OP4 E02653 0 +OP4 E02654 0 +OP4 E02655 0 +OP4 E02656 0 +OP4 E02657 0 +OP4 E02658 0 +OP4 E02659 0 +OP4 E0265A 0 +OP4 E0265B 0 +OP4 E0265C 0 +OP4 E0265D 0 +OP4 E0265E 0 +OP4 E0265F 0 +OP4 E02660 0 +OP4 E02661 0 +OP4 E02662 0 +OP4 E02663 0 +OP4 E02664 0 +OP4 E02665 0 +OP4 E02666 0 +OP4 E02667 0 +OP4 E02668 0 +OP4 E02669 0 +OP4 E0266A 0 +OP4 E0266B 0 +OP4 E0266C 0 +OP4 E0266D 0 +OP4 E0266E 0 +OP4 E0266F 0 +OP4 E02670 0 +OP4 E02671 0 +OP4 E02672 0 +OP4 E02673 0 +OP4 E02674 0 +OP4 E02675 0 +OP4 E02676 0 +OP4 E02677 0 +OP4 E02678 0 +OP4 E02679 0 +OP4 E0267A 0 +OP4 E0267B 0 +OP4 E0267C 0 +OP4 E0267D 0 +OP4 E0267E 0 +OP4 E0267F 0 +OP4 E02680 0 +OP4 E02681 0 +OP4 E02682 0 +OP4 E02683 0 +OP4 E02684 0 +OP4 E02685 0 +OP4 E02686 0 +OP4 E02687 0 +OP4 E02688 0 +OP4 E02689 0 +OP4 E0268A 0 +OP4 E0268B 0 +OP4 E0268C 0 +OP4 E0268D 0 +OP4 E0268E 0 +OP4 E0268F 0 +OP4 E02690 0 +OP4 E02691 0 +OP4 E02692 0 +OP4 E02693 0 +OP4 E02694 0 +OP4 E02695 0 +OP4 E02696 0 +OP4 E02697 0 +OP4 E02698 0 +OP4 E02699 0 +OP4 E0269A 0 +OP4 E0269B 0 +OP4 E0269C 0 +OP4 E0269D 0 +OP4 E0269E 0 +OP4 E0269F 0 +OP4 E026A0 0 +OP4 E026A1 0 +OP4 E026A2 0 +OP4 E026A3 0 +OP4 E026A4 0 +OP4 E026A5 0 +OP4 E026A6 0 +OP4 E026A7 0 +OP4 E026A8 0 +OP4 E026A9 0 +OP4 E026AA 0 +OP4 E026AB 0 +OP4 E026AC 0 +OP4 E026AD 0 +OP4 E026AE 0 +OP4 E026AF 0 +OP4 E026B0 0 +OP4 E026B1 0 +OP4 E026B2 0 +OP4 E026B3 0 +OP4 E026B4 0 +OP4 E026B5 0 +OP4 E026B6 0 +OP4 E026B7 0 +OP4 E026B8 0 +OP4 E026B9 0 +OP4 E026BA 0 +OP4 E026BB 0 +OP4 E026BC 0 +OP4 E026BD 0 +OP4 E026BE 0 +OP4 E026BF 0 +OP4 E026C0 0 +OP4 E026C1 0 +OP4 E026C2 0 +OP4 E026C3 0 +OP4 E026C4 0 +OP4 E026C5 0 +OP4 E026C6 0 +OP4 E026C7 0 +OP4 E026C8 0 +OP4 E026C9 0 +OP4 E026CA 0 +OP4 E026CB 0 +OP4 E026CC 0 +OP4 E026CD 0 +OP4 E026CE 0 +OP4 E026CF 0 +OP4 E026D0 0 +OP4 E026D1 0 +OP4 E026D2 0 +OP4 E026D3 0 +OP4 E026D4 0 +OP4 E026D5 0 +OP4 E026D6 0 +OP4 E026D7 0 +OP4 E026D8 0 +OP4 E026D9 0 +OP4 E026DA 0 +OP4 E026DB 0 +OP4 E026DC 0 +OP4 E026DD 0 +OP4 E026DE 0 +OP4 E026DF 0 +OP4 E026E0 0 +OP4 E026E1 0 +OP4 E026E2 0 +OP4 E026E3 0 +OP4 E026E4 0 +OP4 E026E5 0 +OP4 E026E6 0 +OP4 E026E7 0 +OP4 E026E8 0 +OP4 E026E9 0 +OP4 E026EA 0 +OP4 E026EB 0 +OP4 E026EC 0 +OP4 E026ED 0 +OP4 E026EE 0 +OP4 E026EF 0 +OP4 E026F0 0 +OP4 E026F1 0 +OP4 E026F2 0 +OP4 E026F3 0 +OP4 E026F4 0 +OP4 E026F5 0 +OP4 E026F6 0 +OP4 E026F7 0 +OP4 E026F8 0 +OP4 E026F9 0 +OP4 E026FA 0 +OP4 E026FB 0 +OP4 E026FC 0 +OP4 E026FD 0 +OP4 E026FE 0 +OP4 E026FF 0 +OP4 E02700 0 +OP4 E02701 0 +OP4 E02702 0 +OP4 E02703 0 +OP4 E02704 0 +OP4 E02705 0 +OP4 E02706 0 +OP4 E02707 0 +OP4 E02708 0 +OP4 E02709 0 +OP4 E0270A 0 +OP4 E0270B 0 +OP4 E0270C 0 +OP4 E0270D 0 +OP4 E0270E 0 +OP4 E0270F 0 +OP4 E02710 0 +OP4 E02711 0 +OP4 E02712 0 +OP4 E02713 0 +OP4 E02714 0 +OP4 E02715 0 +OP4 E02716 0 +OP4 E02717 0 +OP4 E02718 0 +OP4 E02719 0 +OP4 E0271A 0 +OP4 E0271B 0 +OP4 E0271C 0 +OP4 E0271D 0 +OP4 E0271E 0 +OP4 E0271F 0 +OP4 E02720 0 +OP4 E02721 0 +OP4 E02722 0 +OP4 E02723 0 +OP4 E02724 0 +OP4 E02725 0 +OP4 E02726 0 +OP4 E02727 0 +OP4 E02728 0 +OP4 E02729 0 +OP4 E0272A 0 +OP4 E0272B 0 +OP4 E0272C 0 +OP4 E0272D 0 +OP4 E0272E 0 +OP4 E0272F 0 +OP4 E02730 0 +OP4 E02731 0 +OP4 E02732 0 +OP4 E02733 0 +OP4 E02734 0 +OP4 E02735 0 +OP4 E02736 0 +OP4 E02737 0 +OP4 E02738 0 +OP4 E02739 0 +OP4 E0273A 0 +OP4 E0273B 0 +OP4 E0273C 0 +OP4 E0273D 0 +OP4 E0273E 0 +OP4 E0273F 0 +OP4 E02740 0 +OP4 E02741 0 +OP4 E02742 0 +OP4 E02743 0 +OP4 E02744 0 +OP4 E02745 0 +OP4 E02746 0 +OP4 E02747 0 +OP4 E02748 0 +OP4 E02749 0 +OP4 E0274A 0 +OP4 E0274B 0 +OP4 E0274C 0 +OP4 E0274D 0 +OP4 E0274E 0 +OP4 E0274F 0 +OP4 E02750 0 +OP4 E02751 0 +OP4 E02752 0 +OP4 E02753 0 +OP4 E02754 0 +OP4 E02755 0 +OP4 E02756 0 +OP4 E02757 0 +OP4 E02758 0 +OP4 E02759 0 +OP4 E0275A 0 +OP4 E0275B 0 +OP4 E0275C 0 +OP4 E0275D 0 +OP4 E0275E 0 +OP4 E0275F 0 +OP4 E02760 0 +OP4 E02761 0 +OP4 E02762 0 +OP4 E02763 0 +OP4 E02764 0 +OP4 E02765 0 +OP4 E02766 0 +OP4 E02767 0 +OP4 E02768 0 +OP4 E02769 0 +OP4 E0276A 0 +OP4 E0276B 0 +OP4 E0276C 0 +OP4 E0276D 0 +OP4 E0276E 0 +OP4 E0276F 0 +OP4 E02770 0 +OP4 E02771 0 +OP4 E02772 0 +OP4 E02773 0 +OP4 E02774 0 +OP4 E02775 0 +OP4 E02776 0 +OP4 E02777 0 +OP4 E02778 0 +OP4 E02779 0 +OP4 E0277A 0 +OP4 E0277B 0 +OP4 E0277C 0 +OP4 E0277D 0 +OP4 E0277E 0 +OP4 E0277F 0 +OP4 E02780 0 +OP4 E02781 0 +OP4 E02782 0 +OP4 E02783 0 +OP4 E02784 0 +OP4 E02785 0 +OP4 E02786 0 +OP4 E02787 0 +OP4 E02788 0 +OP4 E02789 0 +OP4 E0278A 0 +OP4 E0278B 0 +OP4 E0278C 0 +OP4 E0278D 0 +OP4 E0278E 0 +OP4 E0278F 0 +OP4 E02790 0 +OP4 E02791 0 +OP4 E02792 0 +OP4 E02793 0 +OP4 E02794 0 +OP4 E02795 0 +OP4 E02796 0 +OP4 E02797 0 +OP4 E02798 0 +OP4 E02799 0 +OP4 E0279A 0 +OP4 E0279B 0 +OP4 E0279C 0 +OP4 E0279D 0 +OP4 E0279E 0 +OP4 E0279F 0 +OP4 E027A0 0 +OP4 E027A1 0 +OP4 E027A2 0 +OP4 E027A3 0 +OP4 E027A4 0 +OP4 E027A5 0 +OP4 E027A6 0 +OP4 E027A7 0 +OP4 E027A8 0 +OP4 E027A9 0 +OP4 E027AA 0 +OP4 E027AB 0 +OP4 E027AC 0 +OP4 E027AD 0 +OP4 E027AE 0 +OP4 E027AF 0 +OP4 E027B0 0 +OP4 E027B1 0 +OP4 E027B2 0 +OP4 E027B3 0 +OP4 E027B4 0 +OP4 E027B5 0 +OP4 E027B6 0 +OP4 E027B7 0 +OP4 E027B8 0 +OP4 E027B9 0 +OP4 E027BA 0 +OP4 E027BB 0 +OP4 E027BC 0 +OP4 E027BD 0 +OP4 E027BE 0 +OP4 E027BF 0 +OP4 E027C0 0 +OP4 E027C1 0 +OP4 E027C2 0 +OP4 E027C3 0 +OP4 E027C4 0 +OP4 E027C5 0 +OP4 E027C6 0 +OP4 E027C7 0 +OP4 E027C8 0 +OP4 E027C9 0 +OP4 E027CA 0 +OP4 E027CB 0 +OP4 E027CC 0 +OP4 E027CD 0 +OP4 E027CE 0 +OP4 E027CF 0 +OP4 E027D0 0 +OP4 E027D1 0 +OP4 E027D2 0 +OP4 E027D3 0 +OP4 E027D4 0 +OP4 E027D5 0 +OP4 E027D6 0 +OP4 E027D7 0 +OP4 E027D8 0 +OP4 E027D9 0 +OP4 E027DA 0 +OP4 E027DB 0 +OP4 E027DC 0 +OP4 E027DD 0 +OP4 E027DE 0 +OP4 E027DF 0 +OP4 E027E0 0 +OP4 E027E1 0 +OP4 E027E2 0 +OP4 E027E3 0 +OP4 E027E4 0 +OP4 E027E5 0 +OP4 E027E6 0 +OP4 E027E7 0 +OP4 E027E8 0 +OP4 E027E9 0 +OP4 E027EA 0 +OP4 E027EB 0 +OP4 E027EC 0 +OP4 E027ED 0 +OP4 E027EE 0 +OP4 E027EF 0 +OP4 E027F0 0 +OP4 E027F1 0 +OP4 E027F2 0 +OP4 E027F3 0 +OP4 E027F4 0 +OP4 E027F5 0 +OP4 E027F6 0 +OP4 E027F7 0 +OP4 E027F8 0 +OP4 E027F9 0 +OP4 E027FA 0 +OP4 E027FB 0 +OP4 E027FC 0 +OP4 E027FD 0 +OP4 E027FE 0 +OP4 E027FF 0 +OP4 E02800 0 +OP4 E02801 0 +OP4 E02802 0 +OP4 E02803 0 +OP4 E02804 0 +OP4 E02805 0 +OP4 E02806 0 +OP4 E02807 0 +OP4 E02808 0 +OP4 E02809 0 +OP4 E0280A 0 +OP4 E0280B 0 +OP4 E0280C 0 +OP4 E0280D 0 +OP4 E0280E 0 +OP4 E0280F 0 +OP4 E02810 0 +OP4 E02811 0 +OP4 E02812 0 +OP4 E02813 0 +OP4 E02814 0 +OP4 E02815 0 +OP4 E02816 0 +OP4 E02817 0 +OP4 E02818 0 +OP4 E02819 0 +OP4 E0281A 0 +OP4 E0281B 0 +OP4 E0281C 0 +OP4 E0281D 0 +OP4 E0281E 0 +OP4 E0281F 0 +OP4 E02820 0 +OP4 E02821 0 +OP4 E02822 0 +OP4 E02823 0 +OP4 E02824 0 +OP4 E02825 0 +OP4 E02826 0 +OP4 E02827 0 +OP4 E02828 0 +OP4 E02829 0 +OP4 E0282A 0 +OP4 E0282B 0 +OP4 E0282C 0 +OP4 E0282D 0 +OP4 E0282E 0 +OP4 E0282F 0 +OP4 E02830 0 +OP4 E02831 0 +OP4 E02832 0 +OP4 E02833 0 +OP4 E02834 0 +OP4 E02835 0 +OP4 E02836 0 +OP4 E02837 0 +OP4 E02838 0 +OP4 E02839 0 +OP4 E0283A 0 +OP4 E0283B 0 +OP4 E0283C 0 +OP4 E0283D 0 +OP4 E0283E 0 +OP4 E0283F 0 +OP4 E02840 0 +OP4 E02841 0 +OP4 E02842 0 +OP4 E02843 0 +OP4 E02844 0 +OP4 E02845 0 +OP4 E02846 0 +OP4 E02847 0 +OP4 E02848 0 +OP4 E02849 0 +OP4 E0284A 0 +OP4 E0284B 0 +OP4 E0284C 0 +OP4 E0284D 0 +OP4 E0284E 0 +OP4 E0284F 0 +OP4 E02850 0 +OP4 E02851 0 +OP4 E02852 0 +OP4 E02853 0 +OP4 E02854 0 +OP4 E02855 0 +OP4 E02856 0 +OP4 E02857 0 +OP4 E02858 0 +OP4 E02859 0 +OP4 E0285A 0 +OP4 E0285B 0 +OP4 E0285C 0 +OP4 E0285D 0 +OP4 E0285E 0 +OP4 E0285F 0 +OP4 E02860 0 +OP4 E02861 0 +OP4 E02862 0 +OP4 E02863 0 +OP4 E02864 0 +OP4 E02865 0 +OP4 E02866 0 +OP4 E02867 0 +OP4 E02868 0 +OP4 E02869 0 +OP4 E0286A 0 +OP4 E0286B 0 +OP4 E0286C 0 +OP4 E0286D 0 +OP4 E0286E 0 +OP4 E0286F 0 +OP4 E02870 0 +OP4 E02871 0 +OP4 E02872 0 +OP4 E02873 0 +OP4 E02874 0 +OP4 E02875 0 +OP4 E02876 0 +OP4 E02877 0 +OP4 E02878 0 +OP4 E02879 0 +OP4 E0287A 0 +OP4 E0287B 0 +OP4 E0287C 0 +OP4 E0287D 0 +OP4 E0287E 0 +OP4 E0287F 0 +OP4 E02880 0 +OP4 E02881 0 +OP4 E02882 0 +OP4 E02883 0 +OP4 E02884 0 +OP4 E02885 0 +OP4 E02886 0 +OP4 E02887 0 +OP4 E02888 0 +OP4 E02889 0 +OP4 E0288A 0 +OP4 E0288B 0 +OP4 E0288C 0 +OP4 E0288D 0 +OP4 E0288E 0 +OP4 E0288F 0 +OP4 E02890 0 +OP4 E02891 0 +OP4 E02892 0 +OP4 E02893 0 +OP4 E02894 0 +OP4 E02895 0 +OP4 E02896 0 +OP4 E02897 0 +OP4 E02898 0 +OP4 E02899 0 +OP4 E0289A 0 +OP4 E0289B 0 +OP4 E0289C 0 +OP4 E0289D 0 +OP4 E0289E 0 +OP4 E0289F 0 +OP4 E028A0 0 +OP4 E028A1 0 +OP4 E028A2 0 +OP4 E028A3 0 +OP4 E028A4 0 +OP4 E028A5 0 +OP4 E028A6 0 +OP4 E028A7 0 +OP4 E028A8 0 +OP4 E028A9 0 +OP4 E028AA 0 +OP4 E028AB 0 +OP4 E028AC 0 +OP4 E028AD 0 +OP4 E028AE 0 +OP4 E028AF 0 +OP4 E028B0 0 +OP4 E028B1 0 +OP4 E028B2 0 +OP4 E028B3 0 +OP4 E028B4 0 +OP4 E028B5 0 +OP4 E028B6 0 +OP4 E028B7 0 +OP4 E028B8 0 +OP4 E028B9 0 +OP4 E028BA 0 +OP4 E028BB 0 +OP4 E028BC 0 +OP4 E028BD 0 +OP4 E028BE 0 +OP4 E028BF 0 +OP4 E028C0 0 +OP4 E028C1 0 +OP4 E028C2 0 +OP4 E028C3 0 +OP4 E028C4 0 +OP4 E028C5 0 +OP4 E028C6 0 +OP4 E028C7 0 +OP4 E028C8 0 +OP4 E028C9 0 +OP4 E028CA 0 +OP4 E028CB 0 +OP4 E028CC 0 +OP4 E028CD 0 +OP4 E028CE 0 +OP4 E028CF 0 +OP4 E028D0 0 +OP4 E028D1 0 +OP4 E028D2 0 +OP4 E028D3 0 +OP4 E028D4 0 +OP4 E028D5 0 +OP4 E028D6 0 +OP4 E028D7 0 +OP4 E028D8 0 +OP4 E028D9 0 +OP4 E028DA 0 +OP4 E028DB 0 +OP4 E028DC 0 +OP4 E028DD 0 +OP4 E028DE 0 +OP4 E028DF 0 +OP4 E028E0 0 +OP4 E028E1 0 +OP4 E028E2 0 +OP4 E028E3 0 +OP4 E028E4 0 +OP4 E028E5 0 +OP4 E028E6 0 +OP4 E028E7 0 +OP4 E028E8 0 +OP4 E028E9 0 +OP4 E028EA 0 +OP4 E028EB 0 +OP4 E028EC 0 +OP4 E028ED 0 +OP4 E028EE 0 +OP4 E028EF 0 +OP4 E028F0 0 +OP4 E028F1 0 +OP4 E028F2 0 +OP4 E028F3 0 +OP4 E028F4 0 +OP4 E028F5 0 +OP4 E028F6 0 +OP4 E028F7 0 +OP4 E028F8 0 +OP4 E028F9 0 +OP4 E028FA 0 +OP4 E028FB 0 +OP4 E028FC 0 +OP4 E028FD 0 +OP4 E028FE 0 +OP4 E028FF 0 +OP4 E02900 0 +OP4 E02901 0 +OP4 E02902 0 +OP4 E02903 0 +OP4 E02904 0 +OP4 E02905 0 +OP4 E02906 0 +OP4 E02907 0 +OP4 E02908 0 +OP4 E02909 0 +OP4 E0290A 0 +OP4 E0290B 0 +OP4 E0290C 0 +OP4 E0290D 0 +OP4 E0290E 0 +OP4 E0290F 0 +OP4 E02910 0 +OP4 E02911 0 +OP4 E02912 0 +OP4 E02913 0 +OP4 E02914 0 +OP4 E02915 0 +OP4 E02916 0 +OP4 E02917 0 +OP4 E02918 0 +OP4 E02919 0 +OP4 E0291A 0 +OP4 E0291B 0 +OP4 E0291C 0 +OP4 E0291D 0 +OP4 E0291E 0 +OP4 E0291F 0 +OP4 E02920 0 +OP4 E02921 0 +OP4 E02922 0 +OP4 E02923 0 +OP4 E02924 0 +OP4 E02925 0 +OP4 E02926 0 +OP4 E02927 0 +OP4 E02928 0 +OP4 E02929 0 +OP4 E0292A 0 +OP4 E0292B 0 +OP4 E0292C 0 +OP4 E0292D 0 +OP4 E0292E 0 +OP4 E0292F 0 +OP4 E02930 0 +OP4 E02931 0 +OP4 E02932 0 +OP4 E02933 0 +OP4 E02934 0 +OP4 E02935 0 +OP4 E02936 0 +OP4 E02937 0 +OP4 E02938 0 +OP4 E02939 0 +OP4 E0293A 0 +OP4 E0293B 0 +OP4 E0293C 0 +OP4 E0293D 0 +OP4 E0293E 0 +OP4 E0293F 0 +OP4 E02940 0 +OP4 E02941 0 +OP4 E02942 0 +OP4 E02943 0 +OP4 E02944 0 +OP4 E02945 0 +OP4 E02946 0 +OP4 E02947 0 +OP4 E02948 0 +OP4 E02949 0 +OP4 E0294A 0 +OP4 E0294B 0 +OP4 E0294C 0 +OP4 E0294D 0 +OP4 E0294E 0 +OP4 E0294F 0 +OP4 E02950 0 +OP4 E02951 0 +OP4 E02952 0 +OP4 E02953 0 +OP4 E02954 0 +OP4 E02955 0 +OP4 E02956 0 +OP4 E02957 0 +OP4 E02958 0 +OP4 E02959 0 +OP4 E0295A 0 +OP4 E0295B 0 +OP4 E0295C 0 +OP4 E0295D 0 +OP4 E0295E 0 +OP4 E0295F 0 +OP4 E02960 0 +OP4 E02961 0 +OP4 E02962 0 +OP4 E02963 0 +OP4 E02964 0 +OP4 E02965 0 +OP4 E02966 0 +OP4 E02967 0 +OP4 E02968 0 +OP4 E02969 0 +OP4 E0296A 0 +OP4 E0296B 0 +OP4 E0296C 0 +OP4 E0296D 0 +OP4 E0296E 0 +OP4 E0296F 0 +OP4 E02970 0 +OP4 E02971 0 +OP4 E02972 0 +OP4 E02973 0 +OP4 E02974 0 +OP4 E02975 0 +OP4 E02976 0 +OP4 E02977 0 +OP4 E02978 0 +OP4 E02979 0 +OP4 E0297A 0 +OP4 E0297B 0 +OP4 E0297C 0 +OP4 E0297D 0 +OP4 E0297E 0 +OP4 E0297F 0 +OP4 E02980 0 +OP4 E02981 0 +OP4 E02982 0 +OP4 E02983 0 +OP4 E02984 0 +OP4 E02985 0 +OP4 E02986 0 +OP4 E02987 0 +OP4 E02988 0 +OP4 E02989 0 +OP4 E0298A 0 +OP4 E0298B 0 +OP4 E0298C 0 +OP4 E0298D 0 +OP4 E0298E 0 +OP4 E0298F 0 +OP4 E02990 0 +OP4 E02991 0 +OP4 E02992 0 +OP4 E02993 0 +OP4 E02994 0 +OP4 E02995 0 +OP4 E02996 0 +OP4 E02997 0 +OP4 E02998 0 +OP4 E02999 0 +OP4 E0299A 0 +OP4 E0299B 0 +OP4 E0299C 0 +OP4 E0299D 0 +OP4 E0299E 0 +OP4 E0299F 0 +OP4 E029A0 0 +OP4 E029A1 0 +OP4 E029A2 0 +OP4 E029A3 0 +OP4 E029A4 0 +OP4 E029A5 0 +OP4 E029A6 0 +OP4 E029A7 0 +OP4 E029A8 0 +OP4 E029A9 0 +OP4 E029AA 0 +OP4 E029AB 0 +OP4 E029AC 0 +OP4 E029AD 0 +OP4 E029AE 0 +OP4 E029AF 0 +OP4 E029B0 0 +OP4 E029B1 0 +OP4 E029B2 0 +OP4 E029B3 0 +OP4 E029B4 0 +OP4 E029B5 0 +OP4 E029B6 0 +OP4 E029B7 0 +OP4 E029B8 0 +OP4 E029B9 0 +OP4 E029BA 0 +OP4 E029BB 0 +OP4 E029BC 0 +OP4 E029BD 0 +OP4 E029BE 0 +OP4 E029BF 0 +OP4 E029C0 0 +OP4 E029C1 0 +OP4 E029C2 0 +OP4 E029C3 0 +OP4 E029C4 0 +OP4 E029C5 0 +OP4 E029C6 0 +OP4 E029C7 0 +OP4 E029C8 0 +OP4 E029C9 0 +OP4 E029CA 0 +OP4 E029CB 0 +OP4 E029CC 0 +OP4 E029CD 0 +OP4 E029CE 0 +OP4 E029CF 0 +OP4 E029D0 0 +OP4 E029D1 0 +OP4 E029D2 0 +OP4 E029D3 0 +OP4 E029D4 0 +OP4 E029D5 0 +OP4 E029D6 0 +OP4 E029D7 0 +OP4 E029D8 0 +OP4 E029D9 0 +OP4 E029DA 0 +OP4 E029DB 0 +OP4 E029DC 0 +OP4 E029DD 0 +OP4 E029DE 0 +OP4 E029DF 0 +OP4 E029E0 0 +OP4 E029E1 0 +OP4 E029E2 0 +OP4 E029E3 0 +OP4 E029E4 0 +OP4 E029E5 0 +OP4 E029E6 0 +OP4 E029E7 0 +OP4 E029E8 0 +OP4 E029E9 0 +OP4 E029EA 0 +OP4 E029EB 0 +OP4 E029EC 0 +OP4 E029ED 0 +OP4 E029EE 0 +OP4 E029EF 0 +OP4 E029F0 0 +OP4 E029F1 0 +OP4 E029F2 0 +OP4 E029F3 0 +OP4 E029F4 0 +OP4 E029F5 0 +OP4 E029F6 0 +OP4 E029F7 0 +OP4 E029F8 0 +OP4 E029F9 0 +OP4 E029FA 0 +OP4 E029FB 0 +OP4 E029FC 0 +OP4 E029FD 0 +OP4 E029FE 0 +OP4 E029FF 0 +OP4 E02A00 0 +OP4 E02A01 0 +OP4 E02A02 0 +OP4 E02A03 0 +OP4 E02A04 0 +OP4 E02A05 0 +OP4 E02A06 0 +OP4 E02A07 0 +OP4 E02A08 0 +OP4 E02A09 0 +OP4 E02A0A 0 +OP4 E02A0B 0 +OP4 E02A0C 0 +OP4 E02A0D 0 +OP4 E02A0E 0 +OP4 E02A0F 0 +OP4 E02A10 0 +OP4 E02A11 0 +OP4 E02A12 0 +OP4 E02A13 0 +OP4 E02A14 0 +OP4 E02A15 0 +OP4 E02A16 0 +OP4 E02A17 0 +OP4 E02A18 0 +OP4 E02A19 0 +OP4 E02A1A 0 +OP4 E02A1B 0 +OP4 E02A1C 0 +OP4 E02A1D 0 +OP4 E02A1E 0 +OP4 E02A1F 0 +OP4 E02A20 0 +OP4 E02A21 0 +OP4 E02A22 0 +OP4 E02A23 0 +OP4 E02A24 0 +OP4 E02A25 0 +OP4 E02A26 0 +OP4 E02A27 0 +OP4 E02A28 0 +OP4 E02A29 0 +OP4 E02A2A 0 +OP4 E02A2B 0 +OP4 E02A2C 0 +OP4 E02A2D 0 +OP4 E02A2E 0 +OP4 E02A2F 0 +OP4 E02A30 0 +OP4 E02A31 0 +OP4 E02A32 0 +OP4 E02A33 0 +OP4 E02A34 0 +OP4 E02A35 0 +OP4 E02A36 0 +OP4 E02A37 0 +OP4 E02A38 0 +OP4 E02A39 0 +OP4 E02A3A 0 +OP4 E02A3B 0 +OP4 E02A3C 0 +OP4 E02A3D 0 +OP4 E02A3E 0 +OP4 E02A3F 0 +OP4 E02A40 0 +OP4 E02A41 0 +OP4 E02A42 0 +OP4 E02A43 0 +OP4 E02A44 0 +OP4 E02A45 0 +OP4 E02A46 0 +OP4 E02A47 0 +OP4 E02A48 0 +OP4 E02A49 0 +OP4 E02A4A 0 +OP4 E02A4B 0 +OP4 E02A4C 0 +OP4 E02A4D 0 +OP4 E02A4E 0 +OP4 E02A4F 0 +OP4 E02A50 0 +OP4 E02A51 0 +OP4 E02A52 0 +OP4 E02A53 0 +OP4 E02A54 0 +OP4 E02A55 0 +OP4 E02A56 0 +OP4 E02A57 0 +OP4 E02A58 0 +OP4 E02A59 0 +OP4 E02A5A 0 +OP4 E02A5B 0 +OP4 E02A5C 0 +OP4 E02A5D 0 +OP4 E02A5E 0 +OP4 E02A5F 0 +OP4 E02A60 0 +OP4 E02A61 0 +OP4 E02A62 0 +OP4 E02A63 0 +OP4 E02A64 0 +OP4 E02A65 0 +OP4 E02A66 0 +OP4 E02A67 0 +OP4 E02A68 0 +OP4 E02A69 0 +OP4 E02A6A 0 +OP4 E02A6B 0 +OP4 E02A6C 0 +OP4 E02A6D 0 +OP4 E02A6E 0 +OP4 E02A6F 0 +OP4 E02A70 0 +OP4 E02A71 0 +OP4 E02A72 0 +OP4 E02A73 0 +OP4 E02A74 0 +OP4 E02A75 0 +OP4 E02A76 0 +OP4 E02A77 0 +OP4 E02A78 0 +OP4 E02A79 0 +OP4 E02A7A 0 +OP4 E02A7B 0 +OP4 E02A7C 0 +OP4 E02A7D 0 +OP4 E02A7E 0 +OP4 E02A7F 0 +OP4 E02A80 0 +OP4 E02A81 0 +OP4 E02A82 0 +OP4 E02A83 0 +OP4 E02A84 0 +OP4 E02A85 0 +OP4 E02A86 0 +OP4 E02A87 0 +OP4 E02A88 0 +OP4 E02A89 0 +OP4 E02A8A 0 +OP4 E02A8B 0 +OP4 E02A8C 0 +OP4 E02A8D 0 +OP4 E02A8E 0 +OP4 E02A8F 0 +OP4 E02A90 0 +OP4 E02A91 0 +OP4 E02A92 0 +OP4 E02A93 0 +OP4 E02A94 0 +OP4 E02A95 0 +OP4 E02A96 0 +OP4 E02A97 0 +OP4 E02A98 0 +OP4 E02A99 0 +OP4 E02A9A 0 +OP4 E02A9B 0 +OP4 E02A9C 0 +OP4 E02A9D 0 +OP4 E02A9E 0 +OP4 E02A9F 0 +OP4 E02AA0 0 +OP4 E02AA1 0 +OP4 E02AA2 0 +OP4 E02AA3 0 +OP4 E02AA4 0 +OP4 E02AA5 0 +OP4 E02AA6 0 +OP4 E02AA7 0 +OP4 E02AA8 0 +OP4 E02AA9 0 +OP4 E02AAA 0 +OP4 E02AAB 0 +OP4 E02AAC 0 +OP4 E02AAD 0 +OP4 E02AAE 0 +OP4 E02AAF 0 +OP4 E02AB0 0 +OP4 E02AB1 0 +OP4 E02AB2 0 +OP4 E02AB3 0 +OP4 E02AB4 0 +OP4 E02AB5 0 +OP4 E02AB6 0 +OP4 E02AB7 0 +OP4 E02AB8 0 +OP4 E02AB9 0 +OP4 E02ABA 0 +OP4 E02ABB 0 +OP4 E02ABC 0 +OP4 E02ABD 0 +OP4 E02ABE 0 +OP4 E02ABF 0 +OP4 E02AC0 0 +OP4 E02AC1 0 +OP4 E02AC2 0 +OP4 E02AC3 0 +OP4 E02AC4 0 +OP4 E02AC5 0 +OP4 E02AC6 0 +OP4 E02AC7 0 +OP4 E02AC8 0 +OP4 E02AC9 0 +OP4 E02ACA 0 +OP4 E02ACB 0 +OP4 E02ACC 0 +OP4 E02ACD 0 +OP4 E02ACE 0 +OP4 E02ACF 0 +OP4 E02AD0 0 +OP4 E02AD1 0 +OP4 E02AD2 0 +OP4 E02AD3 0 +OP4 E02AD4 0 +OP4 E02AD5 0 +OP4 E02AD6 0 +OP4 E02AD7 0 +OP4 E02AD8 0 +OP4 E02AD9 0 +OP4 E02ADA 0 +OP4 E02ADB 0 +OP4 E02ADC 0 +OP4 E02ADD 0 +OP4 E02ADE 0 +OP4 E02ADF 0 +OP4 E02AE0 0 +OP4 E02AE1 0 +OP4 E02AE2 0 +OP4 E02AE3 0 +OP4 E02AE4 0 +OP4 E02AE5 0 +OP4 E02AE6 0 +OP4 E02AE7 0 +OP4 E02AE8 0 +OP4 E02AE9 0 +OP4 E02AEA 0 +OP4 E02AEB 0 +OP4 E02AEC 0 +OP4 E02AED 0 +OP4 E02AEE 0 +OP4 E02AEF 0 +OP4 E02AF0 0 +OP4 E02AF1 0 +OP4 E02AF2 0 +OP4 E02AF3 0 +OP4 E02AF4 0 +OP4 E02AF5 0 +OP4 E02AF6 0 +OP4 E02AF7 0 +OP4 E02AF8 0 +OP4 E02AF9 0 +OP4 E02AFA 0 +OP4 E02AFB 0 +OP4 E02AFC 0 +OP4 E02AFD 0 +OP4 E02AFE 0 +OP4 E02AFF 0 +OP4 E02B00 0 +OP4 E02B01 0 +OP4 E02B02 0 +OP4 E02B03 0 +OP4 E02B04 0 +OP4 E02B05 0 +OP4 E02B06 0 +OP4 E02B07 0 +OP4 E02B08 0 +OP4 E02B09 0 +OP4 E02B0A 0 +OP4 E02B0B 0 +OP4 E02B0C 0 +OP4 E02B0D 0 +OP4 E02B0E 0 +OP4 E02B0F 0 +OP4 E02B10 0 +OP4 E02B11 0 +OP4 E02B12 0 +OP4 E02B13 0 +OP4 E02B14 0 +OP4 E02B15 0 +OP4 E02B16 0 +OP4 E02B17 0 +OP4 E02B18 0 +OP4 E02B19 0 +OP4 E02B1A 0 +OP4 E02B1B 0 +OP4 E02B1C 0 +OP4 E02B1D 0 +OP4 E02B1E 0 +OP4 E02B1F 0 +OP4 E02B20 0 +OP4 E02B21 0 +OP4 E02B22 0 +OP4 E02B23 0 +OP4 E02B24 0 +OP4 E02B25 0 +OP4 E02B26 0 +OP4 E02B27 0 +OP4 E02B28 0 +OP4 E02B29 0 +OP4 E02B2A 0 +OP4 E02B2B 0 +OP4 E02B2C 0 +OP4 E02B2D 0 +OP4 E02B2E 0 +OP4 E02B2F 0 +OP4 E02B30 0 +OP4 E02B31 0 +OP4 E02B32 0 +OP4 E02B33 0 +OP4 E02B34 0 +OP4 E02B35 0 +OP4 E02B36 0 +OP4 E02B37 0 +OP4 E02B38 0 +OP4 E02B39 0 +OP4 E02B3A 0 +OP4 E02B3B 0 +OP4 E02B3C 0 +OP4 E02B3D 0 +OP4 E02B3E 0 +OP4 E02B3F 0 +OP4 E02B40 0 +OP4 E02B41 0 +OP4 E02B42 0 +OP4 E02B43 0 +OP4 E02B44 0 +OP4 E02B45 0 +OP4 E02B46 0 +OP4 E02B47 0 +OP4 E02B48 0 +OP4 E02B49 0 +OP4 E02B4A 0 +OP4 E02B4B 0 +OP4 E02B4C 0 +OP4 E02B4D 0 +OP4 E02B4E 0 +OP4 E02B4F 0 +OP4 E02B50 0 +OP4 E02B51 0 +OP4 E02B52 0 +OP4 E02B53 0 +OP4 E02B54 0 +OP4 E02B55 0 +OP4 E02B56 0 +OP4 E02B57 0 +OP4 E02B58 0 +OP4 E02B59 0 +OP4 E02B5A 0 +OP4 E02B5B 0 +OP4 E02B5C 0 +OP4 E02B5D 0 +OP4 E02B5E 0 +OP4 E02B5F 0 +OP4 E02B60 0 +OP4 E02B61 0 +OP4 E02B62 0 +OP4 E02B63 0 +OP4 E02B64 0 +OP4 E02B65 0 +OP4 E02B66 0 +OP4 E02B67 0 +OP4 E02B68 0 +OP4 E02B69 0 +OP4 E02B6A 0 +OP4 E02B6B 0 +OP4 E02B6C 0 +OP4 E02B6D 0 +OP4 E02B6E 0 +OP4 E02B6F 0 +OP4 E02B70 0 +OP4 E02B71 0 +OP4 E02B72 0 +OP4 E02B73 0 +OP4 E02B74 0 +OP4 E02B75 0 +OP4 E02B76 0 +OP4 E02B77 0 +OP4 E02B78 0 +OP4 E02B79 0 +OP4 E02B7A 0 +OP4 E02B7B 0 +OP4 E02B7C 0 +OP4 E02B7D 0 +OP4 E02B7E 0 +OP4 E02B7F 0 +OP4 E02B80 0 +OP4 E02B81 0 +OP4 E02B82 0 +OP4 E02B83 0 +OP4 E02B84 0 +OP4 E02B85 0 +OP4 E02B86 0 +OP4 E02B87 0 +OP4 E02B88 0 +OP4 E02B89 0 +OP4 E02B8A 0 +OP4 E02B8B 0 +OP4 E02B8C 0 +OP4 E02B8D 0 +OP4 E02B8E 0 +OP4 E02B8F 0 +OP4 E02B90 0 +OP4 E02B91 0 +OP4 E02B92 0 +OP4 E02B93 0 +OP4 E02B94 0 +OP4 E02B95 0 +OP4 E02B96 0 +OP4 E02B97 0 +OP4 E02B98 0 +OP4 E02B99 0 +OP4 E02B9A 0 +OP4 E02B9B 0 +OP4 E02B9C 0 +OP4 E02B9D 0 +OP4 E02B9E 0 +OP4 E02B9F 0 +OP4 E02BA0 0 +OP4 E02BA1 0 +OP4 E02BA2 0 +OP4 E02BA3 0 +OP4 E02BA4 0 +OP4 E02BA5 0 +OP4 E02BA6 0 +OP4 E02BA7 0 +OP4 E02BA8 0 +OP4 E02BA9 0 +OP4 E02BAA 0 +OP4 E02BAB 0 +OP4 E02BAC 0 +OP4 E02BAD 0 +OP4 E02BAE 0 +OP4 E02BAF 0 +OP4 E02BB0 0 +OP4 E02BB1 0 +OP4 E02BB2 0 +OP4 E02BB3 0 +OP4 E02BB4 0 +OP4 E02BB5 0 +OP4 E02BB6 0 +OP4 E02BB7 0 +OP4 E02BB8 0 +OP4 E02BB9 0 +OP4 E02BBA 0 +OP4 E02BBB 0 +OP4 E02BBC 0 +OP4 E02BBD 0 +OP4 E02BBE 0 +OP4 E02BBF 0 +OP4 E02BC0 0 +OP4 E02BC1 0 +OP4 E02BC2 0 +OP4 E02BC3 0 +OP4 E02BC4 0 +OP4 E02BC5 0 +OP4 E02BC6 0 +OP4 E02BC7 0 +OP4 E02BC8 0 +OP4 E02BC9 0 +OP4 E02BCA 0 +OP4 E02BCB 0 +OP4 E02BCC 0 +OP4 E02BCD 0 +OP4 E02BCE 0 +OP4 E02BCF 0 +OP4 E02BD0 0 +OP4 E02BD1 0 +OP4 E02BD2 0 +OP4 E02BD3 0 +OP4 E02BD4 0 +OP4 E02BD5 0 +OP4 E02BD6 0 +OP4 E02BD7 0 +OP4 E02BD8 0 +OP4 E02BD9 0 +OP4 E02BDA 0 +OP4 E02BDB 0 +OP4 E02BDC 0 +OP4 E02BDD 0 +OP4 E02BDE 0 +OP4 E02BDF 0 +OP4 E02BE0 0 +OP4 E02BE1 0 +OP4 E02BE2 0 +OP4 E02BE3 0 +OP4 E02BE4 0 +OP4 E02BE5 0 +OP4 E02BE6 0 +OP4 E02BE7 0 +OP4 E02BE8 0 +OP4 E02BE9 0 +OP4 E02BEA 0 +OP4 E02BEB 0 +OP4 E02BEC 0 +OP4 E02BED 0 +OP4 E02BEE 0 +OP4 E02BEF 0 +OP4 E02BF0 0 +OP4 E02BF1 0 +OP4 E02BF2 0 +OP4 E02BF3 0 +OP4 E02BF4 0 +OP4 E02BF5 0 +OP4 E02BF6 0 +OP4 E02BF7 0 +OP4 E02BF8 0 +OP4 E02BF9 0 +OP4 E02BFA 0 +OP4 E02BFB 0 +OP4 E02BFC 0 +OP4 E02BFD 0 +OP4 E02BFE 0 +OP4 E02BFF 0 +OP4 E02C00 0 +OP4 E02C01 0 +OP4 E02C02 0 +OP4 E02C03 0 +OP4 E02C04 0 +OP4 E02C05 0 +OP4 E02C06 0 +OP4 E02C07 0 +OP4 E02C08 0 +OP4 E02C09 0 +OP4 E02C0A 0 +OP4 E02C0B 0 +OP4 E02C0C 0 +OP4 E02C0D 0 +OP4 E02C0E 0 +OP4 E02C0F 0 +OP4 E02C10 0 +OP4 E02C11 0 +OP4 E02C12 0 +OP4 E02C13 0 +OP4 E02C14 0 +OP4 E02C15 0 +OP4 E02C16 0 +OP4 E02C17 0 +OP4 E02C18 0 +OP4 E02C19 0 +OP4 E02C1A 0 +OP4 E02C1B 0 +OP4 E02C1C 0 +OP4 E02C1D 0 +OP4 E02C1E 0 +OP4 E02C1F 0 +OP4 E02C20 0 +OP4 E02C21 0 +OP4 E02C22 0 +OP4 E02C23 0 +OP4 E02C24 0 +OP4 E02C25 0 +OP4 E02C26 0 +OP4 E02C27 0 +OP4 E02C28 0 +OP4 E02C29 0 +OP4 E02C2A 0 +OP4 E02C2B 0 +OP4 E02C2C 0 +OP4 E02C2D 0 +OP4 E02C2E 0 +OP4 E02C2F 0 +OP4 E02C30 0 +OP4 E02C31 0 +OP4 E02C32 0 +OP4 E02C33 0 +OP4 E02C34 0 +OP4 E02C35 0 +OP4 E02C36 0 +OP4 E02C37 0 +OP4 E02C38 0 +OP4 E02C39 0 +OP4 E02C3A 0 +OP4 E02C3B 0 +OP4 E02C3C 0 +OP4 E02C3D 0 +OP4 E02C3E 0 +OP4 E02C3F 0 +OP4 E02C40 0 +OP4 E02C41 0 +OP4 E02C42 0 +OP4 E02C43 0 +OP4 E02C44 0 +OP4 E02C45 0 +OP4 E02C46 0 +OP4 E02C47 0 +OP4 E02C48 0 +OP4 E02C49 0 +OP4 E02C4A 0 +OP4 E02C4B 0 +OP4 E02C4C 0 +OP4 E02C4D 0 +OP4 E02C4E 0 +OP4 E02C4F 0 +OP4 E02C50 0 +OP4 E02C51 0 +OP4 E02C52 0 +OP4 E02C53 0 +OP4 E02C54 0 +OP4 E02C55 0 +OP4 E02C56 0 +OP4 E02C57 0 +OP4 E02C58 0 +OP4 E02C59 0 +OP4 E02C5A 0 +OP4 E02C5B 0 +OP4 E02C5C 0 +OP4 E02C5D 0 +OP4 E02C5E 0 +OP4 E02C5F 0 +OP4 E02C60 0 +OP4 E02C61 0 +OP4 E02C62 0 +OP4 E02C63 0 +OP4 E02C64 0 +OP4 E02C65 0 +OP4 E02C66 0 +OP4 E02C67 0 +OP4 E02C68 0 +OP4 E02C69 0 +OP4 E02C6A 0 +OP4 E02C6B 0 +OP4 E02C6C 0 +OP4 E02C6D 0 +OP4 E02C6E 0 +OP4 E02C6F 0 +OP4 E02C70 0 +OP4 E02C71 0 +OP4 E02C72 0 +OP4 E02C73 0 +OP4 E02C74 0 +OP4 E02C75 0 +OP4 E02C76 0 +OP4 E02C77 0 +OP4 E02C78 0 +OP4 E02C79 0 +OP4 E02C7A 0 +OP4 E02C7B 0 +OP4 E02C7C 0 +OP4 E02C7D 0 +OP4 E02C7E 0 +OP4 E02C7F 0 +OP4 E02C80 0 +OP4 E02C81 0 +OP4 E02C82 0 +OP4 E02C83 0 +OP4 E02C84 0 +OP4 E02C85 0 +OP4 E02C86 0 +OP4 E02C87 0 +OP4 E02C88 0 +OP4 E02C89 0 +OP4 E02C8A 0 +OP4 E02C8B 0 +OP4 E02C8C 0 +OP4 E02C8D 0 +OP4 E02C8E 0 +OP4 E02C8F 0 +OP4 E02C90 0 +OP4 E02C91 0 +OP4 E02C92 0 +OP4 E02C93 0 +OP4 E02C94 0 +OP4 E02C95 0 +OP4 E02C96 0 +OP4 E02C97 0 +OP4 E02C98 0 +OP4 E02C99 0 +OP4 E02C9A 0 +OP4 E02C9B 0 +OP4 E02C9C 0 +OP4 E02C9D 0 +OP4 E02C9E 0 +OP4 E02C9F 0 +OP4 E02CA0 0 +OP4 E02CA1 0 +OP4 E02CA2 0 +OP4 E02CA3 0 +OP4 E02CA4 0 +OP4 E02CA5 0 +OP4 E02CA6 0 +OP4 E02CA7 0 +OP4 E02CA8 0 +OP4 E02CA9 0 +OP4 E02CAA 0 +OP4 E02CAB 0 +OP4 E02CAC 0 +OP4 E02CAD 0 +OP4 E02CAE 0 +OP4 E02CAF 0 +OP4 E02CB0 0 +OP4 E02CB1 0 +OP4 E02CB2 0 +OP4 E02CB3 0 +OP4 E02CB4 0 +OP4 E02CB5 0 +OP4 E02CB6 0 +OP4 E02CB7 0 +OP4 E02CB8 0 +OP4 E02CB9 0 +OP4 E02CBA 0 +OP4 E02CBB 0 +OP4 E02CBC 0 +OP4 E02CBD 0 +OP4 E02CBE 0 +OP4 E02CBF 0 +OP4 E02CC0 0 +OP4 E02CC1 0 +OP4 E02CC2 0 +OP4 E02CC3 0 +OP4 E02CC4 0 +OP4 E02CC5 0 +OP4 E02CC6 0 +OP4 E02CC7 0 +OP4 E02CC8 0 +OP4 E02CC9 0 +OP4 E02CCA 0 +OP4 E02CCB 0 +OP4 E02CCC 0 +OP4 E02CCD 0 +OP4 E02CCE 0 +OP4 E02CCF 0 +OP4 E02CD0 0 +OP4 E02CD1 0 +OP4 E02CD2 0 +OP4 E02CD3 0 +OP4 E02CD4 0 +OP4 E02CD5 0 +OP4 E02CD6 0 +OP4 E02CD7 0 +OP4 E02CD8 0 +OP4 E02CD9 0 +OP4 E02CDA 0 +OP4 E02CDB 0 +OP4 E02CDC 0 +OP4 E02CDD 0 +OP4 E02CDE 0 +OP4 E02CDF 0 +OP4 E02CE0 0 +OP4 E02CE1 0 +OP4 E02CE2 0 +OP4 E02CE3 0 +OP4 E02CE4 0 +OP4 E02CE5 0 +OP4 E02CE6 0 +OP4 E02CE7 0 +OP4 E02CE8 0 +OP4 E02CE9 0 +OP4 E02CEA 0 +OP4 E02CEB 0 +OP4 E02CEC 0 +OP4 E02CED 0 +OP4 E02CEE 0 +OP4 E02CEF 0 +OP4 E02CF0 0 +OP4 E02CF1 0 +OP4 E02CF2 0 +OP4 E02CF3 0 +OP4 E02CF4 0 +OP4 E02CF5 0 +OP4 E02CF6 0 +OP4 E02CF7 0 +OP4 E02CF8 0 +OP4 E02CF9 0 +OP4 E02CFA 0 +OP4 E02CFB 0 +OP4 E02CFC 0 +OP4 E02CFD 0 +OP4 E02CFE 0 +OP4 E02CFF 0 +OP4 E02D00 0 +OP4 E02D01 0 +OP4 E02D02 0 +OP4 E02D03 0 +OP4 E02D04 0 +OP4 E02D05 0 +OP4 E02D06 0 +OP4 E02D07 0 +OP4 E02D08 0 +OP4 E02D09 0 +OP4 E02D0A 0 +OP4 E02D0B 0 +OP4 E02D0C 0 +OP4 E02D0D 0 +OP4 E02D0E 0 +OP4 E02D0F 0 +OP4 E02D10 0 +OP4 E02D11 0 +OP4 E02D12 0 +OP4 E02D13 0 +OP4 E02D14 0 +OP4 E02D15 0 +OP4 E02D16 0 +OP4 E02D17 0 +OP4 E02D18 0 +OP4 E02D19 0 +OP4 E02D1A 0 +OP4 E02D1B 0 +OP4 E02D1C 0 +OP4 E02D1D 0 +OP4 E02D1E 0 +OP4 E02D1F 0 +OP4 E02D20 0 +OP4 E02D21 0 +OP4 E02D22 0 +OP4 E02D23 0 +OP4 E02D24 0 +OP4 E02D25 0 +OP4 E02D26 0 +OP4 E02D27 0 +OP4 E02D28 0 +OP4 E02D29 0 +OP4 E02D2A 0 +OP4 E02D2B 0 +OP4 E02D2C 0 +OP4 E02D2D 0 +OP4 E02D2E 0 +OP4 E02D2F 0 +OP4 E02D30 0 +OP4 E02D31 0 +OP4 E02D32 0 +OP4 E02D33 0 +OP4 E02D34 0 +OP4 E02D35 0 +OP4 E02D36 0 +OP4 E02D37 0 +OP4 E02D38 0 +OP4 E02D39 0 +OP4 E02D3A 0 +OP4 E02D3B 0 +OP4 E02D3C 0 +OP4 E02D3D 0 +OP4 E02D3E 0 +OP4 E02D3F 0 +OP4 E02D40 0 +OP4 E02D41 0 +OP4 E02D42 0 +OP4 E02D43 0 +OP4 E02D44 0 +OP4 E02D45 0 +OP4 E02D46 0 +OP4 E02D47 0 +OP4 E02D48 0 +OP4 E02D49 0 +OP4 E02D4A 0 +OP4 E02D4B 0 +OP4 E02D4C 0 +OP4 E02D4D 0 +OP4 E02D4E 0 +OP4 E02D4F 0 +OP4 E02D50 0 +OP4 E02D51 0 +OP4 E02D52 0 +OP4 E02D53 0 +OP4 E02D54 0 +OP4 E02D55 0 +OP4 E02D56 0 +OP4 E02D57 0 +OP4 E02D58 0 +OP4 E02D59 0 +OP4 E02D5A 0 +OP4 E02D5B 0 +OP4 E02D5C 0 +OP4 E02D5D 0 +OP4 E02D5E 0 +OP4 E02D5F 0 +OP4 E02D60 0 +OP4 E02D61 0 +OP4 E02D62 0 +OP4 E02D63 0 +OP4 E02D64 0 +OP4 E02D65 0 +OP4 E02D66 0 +OP4 E02D67 0 +OP4 E02D68 0 +OP4 E02D69 0 +OP4 E02D6A 0 +OP4 E02D6B 0 +OP4 E02D6C 0 +OP4 E02D6D 0 +OP4 E02D6E 0 +OP4 E02D6F 0 +OP4 E02D70 0 +OP4 E02D71 0 +OP4 E02D72 0 +OP4 E02D73 0 +OP4 E02D74 0 +OP4 E02D75 0 +OP4 E02D76 0 +OP4 E02D77 0 +OP4 E02D78 0 +OP4 E02D79 0 +OP4 E02D7A 0 +OP4 E02D7B 0 +OP4 E02D7C 0 +OP4 E02D7D 0 +OP4 E02D7E 0 +OP4 E02D7F 0 +OP4 E02D80 0 +OP4 E02D81 0 +OP4 E02D82 0 +OP4 E02D83 0 +OP4 E02D84 0 +OP4 E02D85 0 +OP4 E02D86 0 +OP4 E02D87 0 +OP4 E02D88 0 +OP4 E02D89 0 +OP4 E02D8A 0 +OP4 E02D8B 0 +OP4 E02D8C 0 +OP4 E02D8D 0 +OP4 E02D8E 0 +OP4 E02D8F 0 +OP4 E02D90 0 +OP4 E02D91 0 +OP4 E02D92 0 +OP4 E02D93 0 +OP4 E02D94 0 +OP4 E02D95 0 +OP4 E02D96 0 +OP4 E02D97 0 +OP4 E02D98 0 +OP4 E02D99 0 +OP4 E02D9A 0 +OP4 E02D9B 0 +OP4 E02D9C 0 +OP4 E02D9D 0 +OP4 E02D9E 0 +OP4 E02D9F 0 +OP4 E02DA0 0 +OP4 E02DA1 0 +OP4 E02DA2 0 +OP4 E02DA3 0 +OP4 E02DA4 0 +OP4 E02DA5 0 +OP4 E02DA6 0 +OP4 E02DA7 0 +OP4 E02DA8 0 +OP4 E02DA9 0 +OP4 E02DAA 0 +OP4 E02DAB 0 +OP4 E02DAC 0 +OP4 E02DAD 0 +OP4 E02DAE 0 +OP4 E02DAF 0 +OP4 E02DB0 0 +OP4 E02DB1 0 +OP4 E02DB2 0 +OP4 E02DB3 0 +OP4 E02DB4 0 +OP4 E02DB5 0 +OP4 E02DB6 0 +OP4 E02DB7 0 +OP4 E02DB8 0 +OP4 E02DB9 0 +OP4 E02DBA 0 +OP4 E02DBB 0 +OP4 E02DBC 0 +OP4 E02DBD 0 +OP4 E02DBE 0 +OP4 E02DBF 0 +OP4 E02DC0 0 +OP4 E02DC1 0 +OP4 E02DC2 0 +OP4 E02DC3 0 +OP4 E02DC4 0 +OP4 E02DC5 0 +OP4 E02DC6 0 +OP4 E02DC7 0 +OP4 E02DC8 0 +OP4 E02DC9 0 +OP4 E02DCA 0 +OP4 E02DCB 0 +OP4 E02DCC 0 +OP4 E02DCD 0 +OP4 E02DCE 0 +OP4 E02DCF 0 +OP4 E02DD0 0 +OP4 E02DD1 0 +OP4 E02DD2 0 +OP4 E02DD3 0 +OP4 E02DD4 0 +OP4 E02DD5 0 +OP4 E02DD6 0 +OP4 E02DD7 0 +OP4 E02DD8 0 +OP4 E02DD9 0 +OP4 E02DDA 0 +OP4 E02DDB 0 +OP4 E02DDC 0 +OP4 E02DDD 0 +OP4 E02DDE 0 +OP4 E02DDF 0 +OP4 E02DE0 0 +OP4 E02DE1 0 +OP4 E02DE2 0 +OP4 E02DE3 0 +OP4 E02DE4 0 +OP4 E02DE5 0 +OP4 E02DE6 0 +OP4 E02DE7 0 +OP4 E02DE8 0 +OP4 E02DE9 0 +OP4 E02DEA 0 +OP4 E02DEB 0 +OP4 E02DEC 0 +OP4 E02DED 0 +OP4 E02DEE 0 +OP4 E02DEF 0 +OP4 E02DF0 0 +OP4 E02DF1 0 +OP4 E02DF2 0 +OP4 E02DF3 0 +OP4 E02DF4 0 +OP4 E02DF5 0 +OP4 E02DF6 0 +OP4 E02DF7 0 +OP4 E02DF8 0 +OP4 E02DF9 0 +OP4 E02DFA 0 +OP4 E02DFB 0 +OP4 E02DFC 0 +OP4 E02DFD 0 +OP4 E02DFE 0 +OP4 E02DFF 0 +OP4 E02E00 0 +OP4 E02E01 0 +OP4 E02E02 0 +OP4 E02E03 0 +OP4 E02E04 0 +OP4 E02E05 0 +OP4 E02E06 0 +OP4 E02E07 0 +OP4 E02E08 0 +OP4 E02E09 0 +OP4 E02E0A 0 +OP4 E02E0B 0 +OP4 E02E0C 0 +OP4 E02E0D 0 +OP4 E02E0E 0 +OP4 E02E0F 0 +OP4 E02E10 0 +OP4 E02E11 0 +OP4 E02E12 0 +OP4 E02E13 0 +OP4 E02E14 0 +OP4 E02E15 0 +OP4 E02E16 0 +OP4 E02E17 0 +OP4 E02E18 0 +OP4 E02E19 0 +OP4 E02E1A 0 +OP4 E02E1B 0 +OP4 E02E1C 0 +OP4 E02E1D 0 +OP4 E02E1E 0 +OP4 E02E1F 0 +OP4 E02E20 0 +OP4 E02E21 0 +OP4 E02E22 0 +OP4 E02E23 0 +OP4 E02E24 0 +OP4 E02E25 0 +OP4 E02E26 0 +OP4 E02E27 0 +OP4 E02E28 0 +OP4 E02E29 0 +OP4 E02E2A 0 +OP4 E02E2B 0 +OP4 E02E2C 0 +OP4 E02E2D 0 +OP4 E02E2E 0 +OP4 E02E2F 0 +OP4 E02E30 0 +OP4 E02E31 0 +OP4 E02E32 0 +OP4 E02E33 0 +OP4 E02E34 0 +OP4 E02E35 0 +OP4 E02E36 0 +OP4 E02E37 0 +OP4 E02E38 0 +OP4 E02E39 0 +OP4 E02E3A 0 +OP4 E02E3B 0 +OP4 E02E3C 0 +OP4 E02E3D 0 +OP4 E02E3E 0 +OP4 E02E3F 0 +OP4 E02E40 0 +OP4 E02E41 0 +OP4 E02E42 0 +OP4 E02E43 0 +OP4 E02E44 0 +OP4 E02E45 0 +OP4 E02E46 0 +OP4 E02E47 0 +OP4 E02E48 0 +OP4 E02E49 0 +OP4 E02E4A 0 +OP4 E02E4B 0 +OP4 E02E4C 0 +OP4 E02E4D 0 +OP4 E02E4E 0 +OP4 E02E4F 0 +OP4 E02E50 0 +OP4 E02E51 0 +OP4 E02E52 0 +OP4 E02E53 0 +OP4 E02E54 0 +OP4 E02E55 0 +OP4 E02E56 0 +OP4 E02E57 0 +OP4 E02E58 0 +OP4 E02E59 0 +OP4 E02E5A 0 +OP4 E02E5B 0 +OP4 E02E5C 0 +OP4 E02E5D 0 +OP4 E02E5E 0 +OP4 E02E5F 0 +OP4 E02E60 0 +OP4 E02E61 0 +OP4 E02E62 0 +OP4 E02E63 0 +OP4 E02E64 0 +OP4 E02E65 0 +OP4 E02E66 0 +OP4 E02E67 0 +OP4 E02E68 0 +OP4 E02E69 0 +OP4 E02E6A 0 +OP4 E02E6B 0 +OP4 E02E6C 0 +OP4 E02E6D 0 +OP4 E02E6E 0 +OP4 E02E6F 0 +OP4 E02E70 0 +OP4 E02E71 0 +OP4 E02E72 0 +OP4 E02E73 0 +OP4 E02E74 0 +OP4 E02E75 0 +OP4 E02E76 0 +OP4 E02E77 0 +OP4 E02E78 0 +OP4 E02E79 0 +OP4 E02E7A 0 +OP4 E02E7B 0 +OP4 E02E7C 0 +OP4 E02E7D 0 +OP4 E02E7E 0 +OP4 E02E7F 0 +OP4 E02E80 0 +OP4 E02E81 0 +OP4 E02E82 0 +OP4 E02E83 0 +OP4 E02E84 0 +OP4 E02E85 0 +OP4 E02E86 0 +OP4 E02E87 0 +OP4 E02E88 0 +OP4 E02E89 0 +OP4 E02E8A 0 +OP4 E02E8B 0 +OP4 E02E8C 0 +OP4 E02E8D 0 +OP4 E02E8E 0 +OP4 E02E8F 0 +OP4 E02E90 0 +OP4 E02E91 0 +OP4 E02E92 0 +OP4 E02E93 0 +OP4 E02E94 0 +OP4 E02E95 0 +OP4 E02E96 0 +OP4 E02E97 0 +OP4 E02E98 0 +OP4 E02E99 0 +OP4 E02E9A 0 +OP4 E02E9B 0 +OP4 E02E9C 0 +OP4 E02E9D 0 +OP4 E02E9E 0 +OP4 E02E9F 0 +OP4 E02EA0 0 +OP4 E02EA1 0 +OP4 E02EA2 0 +OP4 E02EA3 0 +OP4 E02EA4 0 +OP4 E02EA5 0 +OP4 E02EA6 0 +OP4 E02EA7 0 +OP4 E02EA8 0 +OP4 E02EA9 0 +OP4 E02EAA 0 +OP4 E02EAB 0 +OP4 E02EAC 0 +OP4 E02EAD 0 +OP4 E02EAE 0 +OP4 E02EAF 0 +OP4 E02EB0 0 +OP4 E02EB1 0 +OP4 E02EB2 0 +OP4 E02EB3 0 +OP4 E02EB4 0 +OP4 E02EB5 0 +OP4 E02EB6 0 +OP4 E02EB7 0 +OP4 E02EB8 0 +OP4 E02EB9 0 +OP4 E02EBA 0 +OP4 E02EBB 0 +OP4 E02EBC 0 +OP4 E02EBD 0 +OP4 E02EBE 0 +OP4 E02EBF 0 +OP4 E02EC0 0 +OP4 E02EC1 0 +OP4 E02EC2 0 +OP4 E02EC3 0 +OP4 E02EC4 0 +OP4 E02EC5 0 +OP4 E02EC6 0 +OP4 E02EC7 0 +OP4 E02EC8 0 +OP4 E02EC9 0 +OP4 E02ECA 0 +OP4 E02ECB 0 +OP4 E02ECC 0 +OP4 E02ECD 0 +OP4 E02ECE 0 +OP4 E02ECF 0 +OP4 E02ED0 0 +OP4 E02ED1 0 +OP4 E02ED2 0 +OP4 E02ED3 0 +OP4 E02ED4 0 +OP4 E02ED5 0 +OP4 E02ED6 0 +OP4 E02ED7 0 +OP4 E02ED8 0 +OP4 E02ED9 0 +OP4 E02EDA 0 +OP4 E02EDB 0 +OP4 E02EDC 0 +OP4 E02EDD 0 +OP4 E02EDE 0 +OP4 E02EDF 0 +OP4 E02EE0 0 +OP4 E02EE1 0 +OP4 E02EE2 0 +OP4 E02EE3 0 +OP4 E02EE4 0 +OP4 E02EE5 0 +OP4 E02EE6 0 +OP4 E02EE7 0 +OP4 E02EE8 0 +OP4 E02EE9 0 +OP4 E02EEA 0 +OP4 E02EEB 0 +OP4 E02EEC 0 +OP4 E02EED 0 +OP4 E02EEE 0 +OP4 E02EEF 0 +OP4 E02EF0 0 +OP4 E02EF1 0 +OP4 E02EF2 0 +OP4 E02EF3 0 +OP4 E02EF4 0 +OP4 E02EF5 0 +OP4 E02EF6 0 +OP4 E02EF7 0 +OP4 E02EF8 0 +OP4 E02EF9 0 +OP4 E02EFA 0 +OP4 E02EFB 0 +OP4 E02EFC 0 +OP4 E02EFD 0 +OP4 E02EFE 0 +OP4 E02EFF 0 +OP4 E02F00 0 +OP4 E02F01 0 +OP4 E02F02 0 +OP4 E02F03 0 +OP4 E02F04 0 +OP4 E02F05 0 +OP4 E02F06 0 +OP4 E02F07 0 +OP4 E02F08 0 +OP4 E02F09 0 +OP4 E02F0A 0 +OP4 E02F0B 0 +OP4 E02F0C 0 +OP4 E02F0D 0 +OP4 E02F0E 0 +OP4 E02F0F 0 +OP4 E02F10 0 +OP4 E02F11 0 +OP4 E02F12 0 +OP4 E02F13 0 +OP4 E02F14 0 +OP4 E02F15 0 +OP4 E02F16 0 +OP4 E02F17 0 +OP4 E02F18 0 +OP4 E02F19 0 +OP4 E02F1A 0 +OP4 E02F1B 0 +OP4 E02F1C 0 +OP4 E02F1D 0 +OP4 E02F1E 0 +OP4 E02F1F 0 +OP4 E02F20 0 +OP4 E02F21 0 +OP4 E02F22 0 +OP4 E02F23 0 +OP4 E02F24 0 +OP4 E02F25 0 +OP4 E02F26 0 +OP4 E02F27 0 +OP4 E02F28 0 +OP4 E02F29 0 +OP4 E02F2A 0 +OP4 E02F2B 0 +OP4 E02F2C 0 +OP4 E02F2D 0 +OP4 E02F2E 0 +OP4 E02F2F 0 +OP4 E02F30 0 +OP4 E02F31 0 +OP4 E02F32 0 +OP4 E02F33 0 +OP4 E02F34 0 +OP4 E02F35 0 +OP4 E02F36 0 +OP4 E02F37 0 +OP4 E02F38 0 +OP4 E02F39 0 +OP4 E02F3A 0 +OP4 E02F3B 0 +OP4 E02F3C 0 +OP4 E02F3D 0 +OP4 E02F3E 0 +OP4 E02F3F 0 +OP4 E02F40 0 +OP4 E02F41 0 +OP4 E02F42 0 +OP4 E02F43 0 +OP4 E02F44 0 +OP4 E02F45 0 +OP4 E02F46 0 +OP4 E02F47 0 +OP4 E02F48 0 +OP4 E02F49 0 +OP4 E02F4A 0 +OP4 E02F4B 0 +OP4 E02F4C 0 +OP4 E02F4D 0 +OP4 E02F4E 0 +OP4 E02F4F 0 +OP4 E02F50 0 +OP4 E02F51 0 +OP4 E02F52 0 +OP4 E02F53 0 +OP4 E02F54 0 +OP4 E02F55 0 +OP4 E02F56 0 +OP4 E02F57 0 +OP4 E02F58 0 +OP4 E02F59 0 +OP4 E02F5A 0 +OP4 E02F5B 0 +OP4 E02F5C 0 +OP4 E02F5D 0 +OP4 E02F5E 0 +OP4 E02F5F 0 +OP4 E02F60 0 +OP4 E02F61 0 +OP4 E02F62 0 +OP4 E02F63 0 +OP4 E02F64 0 +OP4 E02F65 0 +OP4 E02F66 0 +OP4 E02F67 0 +OP4 E02F68 0 +OP4 E02F69 0 +OP4 E02F6A 0 +OP4 E02F6B 0 +OP4 E02F6C 0 +OP4 E02F6D 0 +OP4 E02F6E 0 +OP4 E02F6F 0 +OP4 E02F70 0 +OP4 E02F71 0 +OP4 E02F72 0 +OP4 E02F73 0 +OP4 E02F74 0 +OP4 E02F75 0 +OP4 E02F76 0 +OP4 E02F77 0 +OP4 E02F78 0 +OP4 E02F79 0 +OP4 E02F7A 0 +OP4 E02F7B 0 +OP4 E02F7C 0 +OP4 E02F7D 0 +OP4 E02F7E 0 +OP4 E02F7F 0 +OP4 E02F80 0 +OP4 E02F81 0 +OP4 E02F82 0 +OP4 E02F83 0 +OP4 E02F84 0 +OP4 E02F85 0 +OP4 E02F86 0 +OP4 E02F87 0 +OP4 E02F88 0 +OP4 E02F89 0 +OP4 E02F8A 0 +OP4 E02F8B 0 +OP4 E02F8C 0 +OP4 E02F8D 0 +OP4 E02F8E 0 +OP4 E02F8F 0 +OP4 E02F90 0 +OP4 E02F91 0 +OP4 E02F92 0 +OP4 E02F93 0 +OP4 E02F94 0 +OP4 E02F95 0 +OP4 E02F96 0 +OP4 E02F97 0 +OP4 E02F98 0 +OP4 E02F99 0 +OP4 E02F9A 0 +OP4 E02F9B 0 +OP4 E02F9C 0 +OP4 E02F9D 0 +OP4 E02F9E 0 +OP4 E02F9F 0 +OP4 E02FA0 0 +OP4 E02FA1 0 +OP4 E02FA2 0 +OP4 E02FA3 0 +OP4 E02FA4 0 +OP4 E02FA5 0 +OP4 E02FA6 0 +OP4 E02FA7 0 +OP4 E02FA8 0 +OP4 E02FA9 0 +OP4 E02FAA 0 +OP4 E02FAB 0 +OP4 E02FAC 0 +OP4 E02FAD 0 +OP4 E02FAE 0 +OP4 E02FAF 0 +OP4 E02FB0 0 +OP4 E02FB1 0 +OP4 E02FB2 0 +OP4 E02FB3 0 +OP4 E02FB4 0 +OP4 E02FB5 0 +OP4 E02FB6 0 +OP4 E02FB7 0 +OP4 E02FB8 0 +OP4 E02FB9 0 +OP4 E02FBA 0 +OP4 E02FBB 0 +OP4 E02FBC 0 +OP4 E02FBD 0 +OP4 E02FBE 0 +OP4 E02FBF 0 +OP4 E02FC0 0 +OP4 E02FC1 0 +OP4 E02FC2 0 +OP4 E02FC3 0 +OP4 E02FC4 0 +OP4 E02FC5 0 +OP4 E02FC6 0 +OP4 E02FC7 0 +OP4 E02FC8 0 +OP4 E02FC9 0 +OP4 E02FCA 0 +OP4 E02FCB 0 +OP4 E02FCC 0 +OP4 E02FCD 0 +OP4 E02FCE 0 +OP4 E02FCF 0 +OP4 E02FD0 0 +OP4 E02FD1 0 +OP4 E02FD2 0 +OP4 E02FD3 0 +OP4 E02FD4 0 +OP4 E02FD5 0 +OP4 E02FD6 0 +OP4 E02FD7 0 +OP4 E02FD8 0 +OP4 E02FD9 0 +OP4 E02FDA 0 +OP4 E02FDB 0 +OP4 E02FDC 0 +OP4 E02FDD 0 +OP4 E02FDE 0 +OP4 E02FDF 0 +OP4 E02FE0 0 +OP4 E02FE1 0 +OP4 E02FE2 0 +OP4 E02FE3 0 +OP4 E02FE4 0 +OP4 E02FE5 0 +OP4 E02FE6 0 +OP4 E02FE7 0 +OP4 E02FE8 0 +OP4 E02FE9 0 +OP4 E02FEA 0 +OP4 E02FEB 0 +OP4 E02FEC 0 +OP4 E02FED 0 +OP4 E02FEE 0 +OP4 E02FEF 0 +OP4 E02FF0 0 +OP4 E02FF1 0 +OP4 E02FF2 0 +OP4 E02FF3 0 +OP4 E02FF4 0 +OP4 E02FF5 0 +OP4 E02FF6 0 +OP4 E02FF7 0 +OP4 E02FF8 0 +OP4 E02FF9 0 +OP4 E02FFA 0 +OP4 E02FFB 0 +OP4 E02FFC 0 +OP4 E02FFD 0 +OP4 E02FFE 0 +OP4 E02FFF 0 +OP4 E03000 0 +OP4 E03001 0 +OP4 E03002 0 +OP4 E03003 0 +OP4 E03004 0 +OP4 E03005 0 +OP4 E03006 0 +OP4 E03007 0 +OP4 E03008 0 +OP4 E03009 0 +OP4 E0300A 0 +OP4 E0300B 0 +OP4 E0300C 0 +OP4 E0300D 0 +OP4 E0300E 0 +OP4 E0300F 0 +OP4 E03010 0 +OP4 E03011 0 +OP4 E03012 0 +OP4 E03013 0 +OP4 E03014 0 +OP4 E03015 0 +OP4 E03016 0 +OP4 E03017 0 +OP4 E03018 0 +OP4 E03019 0 +OP4 E0301A 0 +OP4 E0301B 0 +OP4 E0301C 0 +OP4 E0301D 0 +OP4 E0301E 0 +OP4 E0301F 0 +OP4 E03020 0 +OP4 E03021 0 +OP4 E03022 0 +OP4 E03023 0 +OP4 E03024 0 +OP4 E03025 0 +OP4 E03026 0 +OP4 E03027 0 +OP4 E03028 0 +OP4 E03029 0 +OP4 E0302A 0 +OP4 E0302B 0 +OP4 E0302C 0 +OP4 E0302D 0 +OP4 E0302E 0 +OP4 E0302F 0 +OP4 E03030 0 +OP4 E03031 0 +OP4 E03032 0 +OP4 E03033 0 +OP4 E03034 0 +OP4 E03035 0 +OP4 E03036 0 +OP4 E03037 0 +OP4 E03038 0 +OP4 E03039 0 +OP4 E0303A 0 +OP4 E0303B 0 +OP4 E0303C 0 +OP4 E0303D 0 +OP4 E0303E 0 +OP4 E0303F 0 +OP4 E03040 0 +OP4 E03041 0 +OP4 E03042 0 +OP4 E03043 0 +OP4 E03044 0 +OP4 E03045 0 +OP4 E03046 0 +OP4 E03047 0 +OP4 E03048 0 +OP4 E03049 0 +OP4 E0304A 0 +OP4 E0304B 0 +OP4 E0304C 0 +OP4 E0304D 0 +OP4 E0304E 0 +OP4 E0304F 0 +OP4 E03050 0 +OP4 E03051 0 +OP4 E03052 0 +OP4 E03053 0 +OP4 E03054 0 +OP4 E03055 0 +OP4 E03056 0 +OP4 E03057 0 +OP4 E03058 0 +OP4 E03059 0 +OP4 E0305A 0 +OP4 E0305B 0 +OP4 E0305C 0 +OP4 E0305D 0 +OP4 E0305E 0 +OP4 E0305F 0 +OP4 E03060 0 +OP4 E03061 0 +OP4 E03062 0 +OP4 E03063 0 +OP4 E03064 0 +OP4 E03065 0 +OP4 E03066 0 +OP4 E03067 0 +OP4 E03068 0 +OP4 E03069 0 +OP4 E0306A 0 +OP4 E0306B 0 +OP4 E0306C 0 +OP4 E0306D 0 +OP4 E0306E 0 +OP4 E0306F 0 +OP4 E03070 0 +OP4 E03071 0 +OP4 E03072 0 +OP4 E03073 0 +OP4 E03074 0 +OP4 E03075 0 +OP4 E03076 0 +OP4 E03077 0 +OP4 E03078 0 +OP4 E03079 0 +OP4 E0307A 0 +OP4 E0307B 0 +OP4 E0307C 0 +OP4 E0307D 0 +OP4 E0307E 0 +OP4 E0307F 0 +OP4 E03080 0 +OP4 E03081 0 +OP4 E03082 0 +OP4 E03083 0 +OP4 E03084 0 +OP4 E03085 0 +OP4 E03086 0 +OP4 E03087 0 +OP4 E03088 0 +OP4 E03089 0 +OP4 E0308A 0 +OP4 E0308B 0 +OP4 E0308C 0 +OP4 E0308D 0 +OP4 E0308E 0 +OP4 E0308F 0 +OP4 E03090 0 +OP4 E03091 0 +OP4 E03092 0 +OP4 E03093 0 +OP4 E03094 0 +OP4 E03095 0 +OP4 E03096 0 +OP4 E03097 0 +OP4 E03098 0 +OP4 E03099 0 +OP4 E0309A 0 +OP4 E0309B 0 +OP4 E0309C 0 +OP4 E0309D 0 +OP4 E0309E 0 +OP4 E0309F 0 +OP4 E030A0 0 +OP4 E030A1 0 +OP4 E030A2 0 +OP4 E030A3 0 +OP4 E030A4 0 +OP4 E030A5 0 +OP4 E030A6 0 +OP4 E030A7 0 +OP4 E030A8 0 +OP4 E030A9 0 +OP4 E030AA 0 +OP4 E030AB 0 +OP4 E030AC 0 +OP4 E030AD 0 +OP4 E030AE 0 +OP4 E030AF 0 +OP4 E030B0 0 +OP4 E030B1 0 +OP4 E030B2 0 +OP4 E030B3 0 +OP4 E030B4 0 +OP4 E030B5 0 +OP4 E030B6 0 +OP4 E030B7 0 +OP4 E030B8 0 +OP4 E030B9 0 +OP4 E030BA 0 +OP4 E030BB 0 +OP4 E030BC 0 +OP4 E030BD 0 +OP4 E030BE 0 +OP4 E030BF 0 +OP4 E030C0 0 +OP4 E030C1 0 +OP4 E030C2 0 +OP4 E030C3 0 +OP4 E030C4 0 +OP4 E030C5 0 +OP4 E030C6 0 +OP4 E030C7 0 +OP4 E030C8 0 +OP4 E030C9 0 +OP4 E030CA 0 +OP4 E030CB 0 +OP4 E030CC 0 +OP4 E030CD 0 +OP4 E030CE 0 +OP4 E030CF 0 +OP4 E030D0 0 +OP4 E030D1 0 +OP4 E030D2 0 +OP4 E030D3 0 +OP4 E030D4 0 +OP4 E030D5 0 +OP4 E030D6 0 +OP4 E030D7 0 +OP4 E030D8 0 +OP4 E030D9 0 +OP4 E030DA 0 +OP4 E030DB 0 +OP4 E030DC 0 +OP4 E030DD 0 +OP4 E030DE 0 +OP4 E030DF 0 +OP4 E030E0 0 +OP4 E030E1 0 +OP4 E030E2 0 +OP4 E030E3 0 +OP4 E030E4 0 +OP4 E030E5 0 +OP4 E030E6 0 +OP4 E030E7 0 +OP4 E030E8 0 +OP4 E030E9 0 +OP4 E030EA 0 +OP4 E030EB 0 +OP4 E030EC 0 +OP4 E030ED 0 +OP4 E030EE 0 +OP4 E030EF 0 +OP4 E030F0 0 +OP4 E030F1 0 +OP4 E030F2 0 +OP4 E030F3 0 +OP4 E030F4 0 +OP4 E030F5 0 +OP4 E030F6 0 +OP4 E030F7 0 +OP4 E030F8 0 +OP4 E030F9 0 +OP4 E030FA 0 +OP4 E030FB 0 +OP4 E030FC 0 +OP4 E030FD 0 +OP4 E030FE 0 +OP4 E030FF 0 +OP4 E03100 0 +OP4 E03101 0 +OP4 E03102 0 +OP4 E03103 0 +OP4 E03104 0 +OP4 E03105 0 +OP4 E03106 0 +OP4 E03107 0 +OP4 E03108 0 +OP4 E03109 0 +OP4 E0310A 0 +OP4 E0310B 0 +OP4 E0310C 0 +OP4 E0310D 0 +OP4 E0310E 0 +OP4 E0310F 0 +OP4 E03110 0 +OP4 E03111 0 +OP4 E03112 0 +OP4 E03113 0 +OP4 E03114 0 +OP4 E03115 0 +OP4 E03116 0 +OP4 E03117 0 +OP4 E03118 0 +OP4 E03119 0 +OP4 E0311A 0 +OP4 E0311B 0 +OP4 E0311C 0 +OP4 E0311D 0 +OP4 E0311E 0 +OP4 E0311F 0 +OP4 E03120 0 +OP4 E03121 0 +OP4 E03122 0 +OP4 E03123 0 +OP4 E03124 0 +OP4 E03125 0 +OP4 E03126 0 +OP4 E03127 0 +OP4 E03128 0 +OP4 E03129 0 +OP4 E0312A 0 +OP4 E0312B 0 +OP4 E0312C 0 +OP4 E0312D 0 +OP4 E0312E 0 +OP4 E0312F 0 +OP4 E03130 0 +OP4 E03131 0 +OP4 E03132 0 +OP4 E03133 0 +OP4 E03134 0 +OP4 E03135 0 +OP4 E03136 0 +OP4 E03137 0 +OP4 E03138 0 +OP4 E03139 0 +OP4 E0313A 0 +OP4 E0313B 0 +OP4 E0313C 0 +OP4 E0313D 0 +OP4 E0313E 0 +OP4 E0313F 0 +OP4 E03140 0 +OP4 E03141 0 +OP4 E03142 0 +OP4 E03143 0 +OP4 E03144 0 +OP4 E03145 0 +OP4 E03146 0 +OP4 E03147 0 +OP4 E03148 0 +OP4 E03149 0 +OP4 E0314A 0 +OP4 E0314B 0 +OP4 E0314C 0 +OP4 E0314D 0 +OP4 E0314E 0 +OP4 E0314F 0 +OP4 E03150 0 +OP4 E03151 0 +OP4 E03152 0 +OP4 E03153 0 +OP4 E03154 0 +OP4 E03155 0 +OP4 E03156 0 +OP4 E03157 0 +OP4 E03158 0 +OP4 E03159 0 +OP4 E0315A 0 +OP4 E0315B 0 +OP4 E0315C 0 +OP4 E0315D 0 +OP4 E0315E 0 +OP4 E0315F 0 +OP4 E03160 0 +OP4 E03161 0 +OP4 E03162 0 +OP4 E03163 0 +OP4 E03164 0 +OP4 E03165 0 +OP4 E03166 0 +OP4 E03167 0 +OP4 E03168 0 +OP4 E03169 0 +OP4 E0316A 0 +OP4 E0316B 0 +OP4 E0316C 0 +OP4 E0316D 0 +OP4 E0316E 0 +OP4 E0316F 0 +OP4 E03170 0 +OP4 E03171 0 +OP4 E03172 0 +OP4 E03173 0 +OP4 E03174 0 +OP4 E03175 0 +OP4 E03176 0 +OP4 E03177 0 +OP4 E03178 0 +OP4 E03179 0 +OP4 E0317A 0 +OP4 E0317B 0 +OP4 E0317C 0 +OP4 E0317D 0 +OP4 E0317E 0 +OP4 E0317F 0 +OP4 E03180 0 +OP4 E03181 0 +OP4 E03182 0 +OP4 E03183 0 +OP4 E03184 0 +OP4 E03185 0 +OP4 E03186 0 +OP4 E03187 0 +OP4 E03188 0 +OP4 E03189 0 +OP4 E0318A 0 +OP4 E0318B 0 +OP4 E0318C 0 +OP4 E0318D 0 +OP4 E0318E 0 +OP4 E0318F 0 +OP4 E03190 0 +OP4 E03191 0 +OP4 E03192 0 +OP4 E03193 0 +OP4 E03194 0 +OP4 E03195 0 +OP4 E03196 0 +OP4 E03197 0 +OP4 E03198 0 +OP4 E03199 0 +OP4 E0319A 0 +OP4 E0319B 0 +OP4 E0319C 0 +OP4 E0319D 0 +OP4 E0319E 0 +OP4 E0319F 0 +OP4 E031A0 0 +OP4 E031A1 0 +OP4 E031A2 0 +OP4 E031A3 0 +OP4 E031A4 0 +OP4 E031A5 0 +OP4 E031A6 0 +OP4 E031A7 0 +OP4 E031A8 0 +OP4 E031A9 0 +OP4 E031AA 0 +OP4 E031AB 0 +OP4 E031AC 0 +OP4 E031AD 0 +OP4 E031AE 0 +OP4 E031AF 0 +OP4 E031B0 0 +OP4 E031B1 0 +OP4 E031B2 0 +OP4 E031B3 0 +OP4 E031B4 0 +OP4 E031B5 0 +OP4 E031B6 0 +OP4 E031B7 0 +OP4 E031B8 0 +OP4 E031B9 0 +OP4 E031BA 0 +OP4 E031BB 0 +OP4 E031BC 0 +OP4 E031BD 0 +OP4 E031BE 0 +OP4 E031BF 0 +OP4 E031C0 0 +OP4 E031C1 0 +OP4 E031C2 0 +OP4 E031C3 0 +OP4 E031C4 0 +OP4 E031C5 0 +OP4 E031C6 0 +OP4 E031C7 0 +OP4 E031C8 0 +OP4 E031C9 0 +OP4 E031CA 0 +OP4 E031CB 0 +OP4 E031CC 0 +OP4 E031CD 0 +OP4 E031CE 0 +OP4 E031CF 0 +OP4 E031D0 0 +OP4 E031D1 0 +OP4 E031D2 0 +OP4 E031D3 0 +OP4 E031D4 0 +OP4 E031D5 0 +OP4 E031D6 0 +OP4 E031D7 0 +OP4 E031D8 0 +OP4 E031D9 0 +OP4 E031DA 0 +OP4 E031DB 0 +OP4 E031DC 0 +OP4 E031DD 0 +OP4 E031DE 0 +OP4 E031DF 0 +OP4 E031E0 0 +OP4 E031E1 0 +OP4 E031E2 0 +OP4 E031E3 0 +OP4 E031E4 0 +OP4 E031E5 0 +OP4 E031E6 0 +OP4 E031E7 0 +OP4 E031E8 0 +OP4 E031E9 0 +OP4 E031EA 0 +OP4 E031EB 0 +OP4 E031EC 0 +OP4 E031ED 0 +OP4 E031EE 0 +OP4 E031EF 0 +OP4 E031F0 0 +OP4 E031F1 0 +OP4 E031F2 0 +OP4 E031F3 0 +OP4 E031F4 0 +OP4 E031F5 0 +OP4 E031F6 0 +OP4 E031F7 0 +OP4 E031F8 0 +OP4 E031F9 0 +OP4 E031FA 0 +OP4 E031FB 0 +OP4 E031FC 0 +OP4 E031FD 0 +OP4 E031FE 0 +OP4 E031FF 0 +OP4 E03200 0 +OP4 E03201 0 +OP4 E03202 0 +OP4 E03203 0 +OP4 E03204 0 +OP4 E03205 0 +OP4 E03206 0 +OP4 E03207 0 +OP4 E03208 0 +OP4 E03209 0 +OP4 E0320A 0 +OP4 E0320B 0 +OP4 E0320C 0 +OP4 E0320D 0 +OP4 E0320E 0 +OP4 E0320F 0 +OP4 E03210 0 +OP4 E03211 0 +OP4 E03212 0 +OP4 E03213 0 +OP4 E03214 0 +OP4 E03215 0 +OP4 E03216 0 +OP4 E03217 0 +OP4 E03218 0 +OP4 E03219 0 +OP4 E0321A 0 +OP4 E0321B 0 +OP4 E0321C 0 +OP4 E0321D 0 +OP4 E0321E 0 +OP4 E0321F 0 +OP4 E03220 0 +OP4 E03221 0 +OP4 E03222 0 +OP4 E03223 0 +OP4 E03224 0 +OP4 E03225 0 +OP4 E03226 0 +OP4 E03227 0 +OP4 E03228 0 +OP4 E03229 0 +OP4 E0322A 0 +OP4 E0322B 0 +OP4 E0322C 0 +OP4 E0322D 0 +OP4 E0322E 0 +OP4 E0322F 0 +OP4 E03230 0 +OP4 E03231 0 +OP4 E03232 0 +OP4 E03233 0 +OP4 E03234 0 +OP4 E03235 0 +OP4 E03236 0 +OP4 E03237 0 +OP4 E03238 0 +OP4 E03239 0 +OP4 E0323A 0 +OP4 E0323B 0 +OP4 E0323C 0 +OP4 E0323D 0 +OP4 E0323E 0 +OP4 E0323F 0 +OP4 E03240 0 +OP4 E03241 0 +OP4 E03242 0 +OP4 E03243 0 +OP4 E03244 0 +OP4 E03245 0 +OP4 E03246 0 +OP4 E03247 0 +OP4 E03248 0 +OP4 E03249 0 +OP4 E0324A 0 +OP4 E0324B 0 +OP4 E0324C 0 +OP4 E0324D 0 +OP4 E0324E 0 +OP4 E0324F 0 +OP4 E03250 0 +OP4 E03251 0 +OP4 E03252 0 +OP4 E03253 0 +OP4 E03254 0 +OP4 E03255 0 +OP4 E03256 0 +OP4 E03257 0 +OP4 E03258 0 +OP4 E03259 0 +OP4 E0325A 0 +OP4 E0325B 0 +OP4 E0325C 0 +OP4 E0325D 0 +OP4 E0325E 0 +OP4 E0325F 0 +OP4 E03260 0 +OP4 E03261 0 +OP4 E03262 0 +OP4 E03263 0 +OP4 E03264 0 +OP4 E03265 0 +OP4 E03266 0 +OP4 E03267 0 +OP4 E03268 0 +OP4 E03269 0 +OP4 E0326A 0 +OP4 E0326B 0 +OP4 E0326C 0 +OP4 E0326D 0 +OP4 E0326E 0 +OP4 E0326F 0 +OP4 E03270 0 +OP4 E03271 0 +OP4 E03272 0 +OP4 E03273 0 +OP4 E03274 0 +OP4 E03275 0 +OP4 E03276 0 +OP4 E03277 0 +OP4 E03278 0 +OP4 E03279 0 +OP4 E0327A 0 +OP4 E0327B 0 +OP4 E0327C 0 +OP4 E0327D 0 +OP4 E0327E 0 +OP4 E0327F 0 +OP4 E03280 0 +OP4 E03281 0 +OP4 E03282 0 +OP4 E03283 0 +OP4 E03284 0 +OP4 E03285 0 +OP4 E03286 0 +OP4 E03287 0 +OP4 E03288 0 +OP4 E03289 0 +OP4 E0328A 0 +OP4 E0328B 0 +OP4 E0328C 0 +OP4 E0328D 0 +OP4 E0328E 0 +OP4 E0328F 0 +OP4 E03290 0 +OP4 E03291 0 +OP4 E03292 0 +OP4 E03293 0 +OP4 E03294 0 +OP4 E03295 0 +OP4 E03296 0 +OP4 E03297 0 +OP4 E03298 0 +OP4 E03299 0 +OP4 E0329A 0 +OP4 E0329B 0 +OP4 E0329C 0 +OP4 E0329D 0 +OP4 E0329E 0 +OP4 E0329F 0 +OP4 E032A0 0 +OP4 E032A1 0 +OP4 E032A2 0 +OP4 E032A3 0 +OP4 E032A4 0 +OP4 E032A5 0 +OP4 E032A6 0 +OP4 E032A7 0 +OP4 E032A8 0 +OP4 E032A9 0 +OP4 E032AA 0 +OP4 E032AB 0 +OP4 E032AC 0 +OP4 E032AD 0 +OP4 E032AE 0 +OP4 E032AF 0 +OP4 E032B0 0 +OP4 E032B1 0 +OP4 E032B2 0 +OP4 E032B3 0 +OP4 E032B4 0 +OP4 E032B5 0 +OP4 E032B6 0 +OP4 E032B7 0 +OP4 E032B8 0 +OP4 E032B9 0 +OP4 E032BA 0 +OP4 E032BB 0 +OP4 E032BC 0 +OP4 E032BD 0 +OP4 E032BE 0 +OP4 E032BF 0 +OP4 E032C0 0 +OP4 E032C1 0 +OP4 E032C2 0 +OP4 E032C3 0 +OP4 E032C4 0 +OP4 E032C5 0 +OP4 E032C6 0 +OP4 E032C7 0 +OP4 E032C8 0 +OP4 E032C9 0 +OP4 E032CA 0 +OP4 E032CB 0 +OP4 E032CC 0 +OP4 E032CD 0 +OP4 E032CE 0 +OP4 E032CF 0 +OP4 E032D0 0 +OP4 E032D1 0 +OP4 E032D2 0 +OP4 E032D3 0 +OP4 E032D4 0 +OP4 E032D5 0 +OP4 E032D6 0 +OP4 E032D7 0 +OP4 E032D8 0 +OP4 E032D9 0 +OP4 E032DA 0 +OP4 E032DB 0 +OP4 E032DC 0 +OP4 E032DD 0 +OP4 E032DE 0 +OP4 E032DF 0 +OP4 E032E0 0 +OP4 E032E1 0 +OP4 E032E2 0 +OP4 E032E3 0 +OP4 E032E4 0 +OP4 E032E5 0 +OP4 E032E6 0 +OP4 E032E7 0 +OP4 E032E8 0 +OP4 E032E9 0 +OP4 E032EA 0 +OP4 E032EB 0 +OP4 E032EC 0 +OP4 E032ED 0 +OP4 E032EE 0 +OP4 E032EF 0 +OP4 E032F0 0 +OP4 E032F1 0 +OP4 E032F2 0 +OP4 E032F3 0 +OP4 E032F4 0 +OP4 E032F5 0 +OP4 E032F6 0 +OP4 E032F7 0 +OP4 E032F8 0 +OP4 E032F9 0 +OP4 E032FA 0 +OP4 E032FB 0 +OP4 E032FC 0 +OP4 E032FD 0 +OP4 E032FE 0 +OP4 E032FF 0 +OP4 E03300 0 +OP4 E03301 0 +OP4 E03302 0 +OP4 E03303 0 +OP4 E03304 0 +OP4 E03305 0 +OP4 E03306 0 +OP4 E03307 0 +OP4 E03308 0 +OP4 E03309 0 +OP4 E0330A 0 +OP4 E0330B 0 +OP4 E0330C 0 +OP4 E0330D 0 +OP4 E0330E 0 +OP4 E0330F 0 +OP4 E03310 0 +OP4 E03311 0 +OP4 E03312 0 +OP4 E03313 0 +OP4 E03314 0 +OP4 E03315 0 +OP4 E03316 0 +OP4 E03317 0 +OP4 E03318 0 +OP4 E03319 0 +OP4 E0331A 0 +OP4 E0331B 0 +OP4 E0331C 0 +OP4 E0331D 0 +OP4 E0331E 0 +OP4 E0331F 0 +OP4 E03320 0 +OP4 E03321 0 +OP4 E03322 0 +OP4 E03323 0 +OP4 E03324 0 +OP4 E03325 0 +OP4 E03326 0 +OP4 E03327 0 +OP4 E03328 0 +OP4 E03329 0 +OP4 E0332A 0 +OP4 E0332B 0 +OP4 E0332C 0 +OP4 E0332D 0 +OP4 E0332E 0 +OP4 E0332F 0 +OP4 E03330 0 +OP4 E03331 0 +OP4 E03332 0 +OP4 E03333 0 +OP4 E03334 0 +OP4 E03335 0 +OP4 E03336 0 +OP4 E03337 0 +OP4 E03338 0 +OP4 E03339 0 +OP4 E0333A 0 +OP4 E0333B 0 +OP4 E0333C 0 +OP4 E0333D 0 +OP4 E0333E 0 +OP4 E0333F 0 +OP4 E03340 0 +OP4 E03341 0 +OP4 E03342 0 +OP4 E03343 0 +OP4 E03344 0 +OP4 E03345 0 +OP4 E03346 0 +OP4 E03347 0 +OP4 E03348 0 +OP4 E03349 0 +OP4 E0334A 0 +OP4 E0334B 0 +OP4 E0334C 0 +OP4 E0334D 0 +OP4 E0334E 0 +OP4 E0334F 0 +OP4 E03350 0 +OP4 E03351 0 +OP4 E03352 0 +OP4 E03353 0 +OP4 E03354 0 +OP4 E03355 0 +OP4 E03356 0 +OP4 E03357 0 +OP4 E03358 0 +OP4 E03359 0 +OP4 E0335A 0 +OP4 E0335B 0 +OP4 E0335C 0 +OP4 E0335D 0 +OP4 E0335E 0 +OP4 E0335F 0 +OP4 E03360 0 +OP4 E03361 0 +OP4 E03362 0 +OP4 E03363 0 +OP4 E03364 0 +OP4 E03365 0 +OP4 E03366 0 +OP4 E03367 0 +OP4 E03368 0 +OP4 E03369 0 +OP4 E0336A 0 +OP4 E0336B 0 +OP4 E0336C 0 +OP4 E0336D 0 +OP4 E0336E 0 +OP4 E0336F 0 +OP4 E03370 0 +OP4 E03371 0 +OP4 E03372 0 +OP4 E03373 0 +OP4 E03374 0 +OP4 E03375 0 +OP4 E03376 0 +OP4 E03377 0 +OP4 E03378 0 +OP4 E03379 0 +OP4 E0337A 0 +OP4 E0337B 0 +OP4 E0337C 0 +OP4 E0337D 0 +OP4 E0337E 0 +OP4 E0337F 0 +OP4 E03380 0 +OP4 E03381 0 +OP4 E03382 0 +OP4 E03383 0 +OP4 E03384 0 +OP4 E03385 0 +OP4 E03386 0 +OP4 E03387 0 +OP4 E03388 0 +OP4 E03389 0 +OP4 E0338A 0 +OP4 E0338B 0 +OP4 E0338C 0 +OP4 E0338D 0 +OP4 E0338E 0 +OP4 E0338F 0 +OP4 E03390 0 +OP4 E03391 0 +OP4 E03392 0 +OP4 E03393 0 +OP4 E03394 0 +OP4 E03395 0 +OP4 E03396 0 +OP4 E03397 0 +OP4 E03398 0 +OP4 E03399 0 +OP4 E0339A 0 +OP4 E0339B 0 +OP4 E0339C 0 +OP4 E0339D 0 +OP4 E0339E 0 +OP4 E0339F 0 +OP4 E033A0 0 +OP4 E033A1 0 +OP4 E033A2 0 +OP4 E033A3 0 +OP4 E033A4 0 +OP4 E033A5 0 +OP4 E033A6 0 +OP4 E033A7 0 +OP4 E033A8 0 +OP4 E033A9 0 +OP4 E033AA 0 +OP4 E033AB 0 +OP4 E033AC 0 +OP4 E033AD 0 +OP4 E033AE 0 +OP4 E033AF 0 +OP4 E033B0 0 +OP4 E033B1 0 +OP4 E033B2 0 +OP4 E033B3 0 +OP4 E033B4 0 +OP4 E033B5 0 +OP4 E033B6 0 +OP4 E033B7 0 +OP4 E033B8 0 +OP4 E033B9 0 +OP4 E033BA 0 +OP4 E033BB 0 +OP4 E033BC 0 +OP4 E033BD 0 +OP4 E033BE 0 +OP4 E033BF 0 +OP4 E033C0 0 +OP4 E033C1 0 +OP4 E033C2 0 +OP4 E033C3 0 +OP4 E033C4 0 +OP4 E033C5 0 +OP4 E033C6 0 +OP4 E033C7 0 +OP4 E033C8 0 +OP4 E033C9 0 +OP4 E033CA 0 +OP4 E033CB 0 +OP4 E033CC 0 +OP4 E033CD 0 +OP4 E033CE 0 +OP4 E033CF 0 +OP4 E033D0 0 +OP4 E033D1 0 +OP4 E033D2 0 +OP4 E033D3 0 +OP4 E033D4 0 +OP4 E033D5 0 +OP4 E033D6 0 +OP4 E033D7 0 +OP4 E033D8 0 +OP4 E033D9 0 +OP4 E033DA 0 +OP4 E033DB 0 +OP4 E033DC 0 +OP4 E033DD 0 +OP4 E033DE 0 +OP4 E033DF 0 +OP4 E033E0 0 +OP4 E033E1 0 +OP4 E033E2 0 +OP4 E033E3 0 +OP4 E033E4 0 +OP4 E033E5 0 +OP4 E033E6 0 +OP4 E033E7 0 +OP4 E033E8 0 +OP4 E033E9 0 +OP4 E033EA 0 +OP4 E033EB 0 +OP4 E033EC 0 +OP4 E033ED 0 +OP4 E033EE 0 +OP4 E033EF 0 +OP4 E033F0 0 +OP4 E033F1 0 +OP4 E033F2 0 +OP4 E033F3 0 +OP4 E033F4 0 +OP4 E033F5 0 +OP4 E033F6 0 +OP4 E033F7 0 +OP4 E033F8 0 +OP4 E033F9 0 +OP4 E033FA 0 +OP4 E033FB 0 +OP4 E033FC 0 +OP4 E033FD 0 +OP4 E033FE 0 +OP4 E033FF 0 +OP4 E03400 0 +OP4 E03401 0 +OP4 E03402 0 +OP4 E03403 0 +OP4 E03404 0 +OP4 E03405 0 +OP4 E03406 0 +OP4 E03407 0 +OP4 E03408 0 +OP4 E03409 0 +OP4 E0340A 0 +OP4 E0340B 0 +OP4 E0340C 0 +OP4 E0340D 0 +OP4 E0340E 0 +OP4 E0340F 0 +OP4 E03410 0 +OP4 E03411 0 +OP4 E03412 0 +OP4 E03413 0 +OP4 E03414 0 +OP4 E03415 0 +OP4 E03416 0 +OP4 E03417 0 +OP4 E03418 0 +OP4 E03419 0 +OP4 E0341A 0 +OP4 E0341B 0 +OP4 E0341C 0 +OP4 E0341D 0 +OP4 E0341E 0 +OP4 E0341F 0 +OP4 E03420 0 +OP4 E03421 0 +OP4 E03422 0 +OP4 E03423 0 +OP4 E03424 0 +OP4 E03425 0 +OP4 E03426 0 +OP4 E03427 0 +OP4 E03428 0 +OP4 E03429 0 +OP4 E0342A 0 +OP4 E0342B 0 +OP4 E0342C 0 +OP4 E0342D 0 +OP4 E0342E 0 +OP4 E0342F 0 +OP4 E03430 0 +OP4 E03431 0 +OP4 E03432 0 +OP4 E03433 0 +OP4 E03434 0 +OP4 E03435 0 +OP4 E03436 0 +OP4 E03437 0 +OP4 E03438 0 +OP4 E03439 0 +OP4 E0343A 0 +OP4 E0343B 0 +OP4 E0343C 0 +OP4 E0343D 0 +OP4 E0343E 0 +OP4 E0343F 0 +OP4 E03440 0 +OP4 E03441 0 +OP4 E03442 0 +OP4 E03443 0 +OP4 E03444 0 +OP4 E03445 0 +OP4 E03446 0 +OP4 E03447 0 +OP4 E03448 0 +OP4 E03449 0 +OP4 E0344A 0 +OP4 E0344B 0 +OP4 E0344C 0 +OP4 E0344D 0 +OP4 E0344E 0 +OP4 E0344F 0 +OP4 E03450 0 +OP4 E03451 0 +OP4 E03452 0 +OP4 E03453 0 +OP4 E03454 0 +OP4 E03455 0 +OP4 E03456 0 +OP4 E03457 0 +OP4 E03458 0 +OP4 E03459 0 +OP4 E0345A 0 +OP4 E0345B 0 +OP4 E0345C 0 +OP4 E0345D 0 +OP4 E0345E 0 +OP4 E0345F 0 +OP4 E03460 0 +OP4 E03461 0 +OP4 E03462 0 +OP4 E03463 0 +OP4 E03464 0 +OP4 E03465 0 +OP4 E03466 0 +OP4 E03467 0 +OP4 E03468 0 +OP4 E03469 0 +OP4 E0346A 0 +OP4 E0346B 0 +OP4 E0346C 0 +OP4 E0346D 0 +OP4 E0346E 0 +OP4 E0346F 0 +OP4 E03470 0 +OP4 E03471 0 +OP4 E03472 0 +OP4 E03473 0 +OP4 E03474 0 +OP4 E03475 0 +OP4 E03476 0 +OP4 E03477 0 +OP4 E03478 0 +OP4 E03479 0 +OP4 E0347A 0 +OP4 E0347B 0 +OP4 E0347C 0 +OP4 E0347D 0 +OP4 E0347E 0 +OP4 E0347F 0 +OP4 E03480 0 +OP4 E03481 0 +OP4 E03482 0 +OP4 E03483 0 +OP4 E03484 0 +OP4 E03485 0 +OP4 E03486 0 +OP4 E03487 0 +OP4 E03488 0 +OP4 E03489 0 +OP4 E0348A 0 +OP4 E0348B 0 +OP4 E0348C 0 +OP4 E0348D 0 +OP4 E0348E 0 +OP4 E0348F 0 +OP4 E03490 0 +OP4 E03491 0 +OP4 E03492 0 +OP4 E03493 0 +OP4 E03494 0 +OP4 E03495 0 +OP4 E03496 0 +OP4 E03497 0 +OP4 E03498 0 +OP4 E03499 0 +OP4 E0349A 0 +OP4 E0349B 0 +OP4 E0349C 0 +OP4 E0349D 0 +OP4 E0349E 0 +OP4 E0349F 0 +OP4 E034A0 0 +OP4 E034A1 0 +OP4 E034A2 0 +OP4 E034A3 0 +OP4 E034A4 0 +OP4 E034A5 0 +OP4 E034A6 0 +OP4 E034A7 0 +OP4 E034A8 0 +OP4 E034A9 0 +OP4 E034AA 0 +OP4 E034AB 0 +OP4 E034AC 0 +OP4 E034AD 0 +OP4 E034AE 0 +OP4 E034AF 0 +OP4 E034B0 0 +OP4 E034B1 0 +OP4 E034B2 0 +OP4 E034B3 0 +OP4 E034B4 0 +OP4 E034B5 0 +OP4 E034B6 0 +OP4 E034B7 0 +OP4 E034B8 0 +OP4 E034B9 0 +OP4 E034BA 0 +OP4 E034BB 0 +OP4 E034BC 0 +OP4 E034BD 0 +OP4 E034BE 0 +OP4 E034BF 0 +OP4 E034C0 0 +OP4 E034C1 0 +OP4 E034C2 0 +OP4 E034C3 0 +OP4 E034C4 0 +OP4 E034C5 0 +OP4 E034C6 0 +OP4 E034C7 0 +OP4 E034C8 0 +OP4 E034C9 0 +OP4 E034CA 0 +OP4 E034CB 0 +OP4 E034CC 0 +OP4 E034CD 0 +OP4 E034CE 0 +OP4 E034CF 0 +OP4 E034D0 0 +OP4 E034D1 0 +OP4 E034D2 0 +OP4 E034D3 0 +OP4 E034D4 0 +OP4 E034D5 0 +OP4 E034D6 0 +OP4 E034D7 0 +OP4 E034D8 0 +OP4 E034D9 0 +OP4 E034DA 0 +OP4 E034DB 0 +OP4 E034DC 0 +OP4 E034DD 0 +OP4 E034DE 0 +OP4 E034DF 0 +OP4 E034E0 0 +OP4 E034E1 0 +OP4 E034E2 0 +OP4 E034E3 0 +OP4 E034E4 0 +OP4 E034E5 0 +OP4 E034E6 0 +OP4 E034E7 0 +OP4 E034E8 0 +OP4 E034E9 0 +OP4 E034EA 0 +OP4 E034EB 0 +OP4 E034EC 0 +OP4 E034ED 0 +OP4 E034EE 0 +OP4 E034EF 0 +OP4 E034F0 0 +OP4 E034F1 0 +OP4 E034F2 0 +OP4 E034F3 0 +OP4 E034F4 0 +OP4 E034F5 0 +OP4 E034F6 0 +OP4 E034F7 0 +OP4 E034F8 0 +OP4 E034F9 0 +OP4 E034FA 0 +OP4 E034FB 0 +OP4 E034FC 0 +OP4 E034FD 0 +OP4 E034FE 0 +OP4 E034FF 0 +OP4 E03500 0 +OP4 E03501 0 +OP4 E03502 0 +OP4 E03503 0 +OP4 E03504 0 +OP4 E03505 0 +OP4 E03506 0 +OP4 E03507 0 +OP4 E03508 0 +OP4 E03509 0 +OP4 E0350A 0 +OP4 E0350B 0 +OP4 E0350C 0 +OP4 E0350D 0 +OP4 E0350E 0 +OP4 E0350F 0 +OP4 E03510 0 +OP4 E03511 0 +OP4 E03512 0 +OP4 E03513 0 +OP4 E03514 0 +OP4 E03515 0 +OP4 E03516 0 +OP4 E03517 0 +OP4 E03518 0 +OP4 E03519 0 +OP4 E0351A 0 +OP4 E0351B 0 +OP4 E0351C 0 +OP4 E0351D 0 +OP4 E0351E 0 +OP4 E0351F 0 +OP4 E03520 0 +OP4 E03521 0 +OP4 E03522 0 +OP4 E03523 0 +OP4 E03524 0 +OP4 E03525 0 +OP4 E03526 0 +OP4 E03527 0 +OP4 E03528 0 +OP4 E03529 0 +OP4 E0352A 0 +OP4 E0352B 0 +OP4 E0352C 0 +OP4 E0352D 0 +OP4 E0352E 0 +OP4 E0352F 0 +OP4 E03530 0 +OP4 E03531 0 +OP4 E03532 0 +OP4 E03533 0 +OP4 E03534 0 +OP4 E03535 0 +OP4 E03536 0 +OP4 E03537 0 +OP4 E03538 0 +OP4 E03539 0 +OP4 E0353A 0 +OP4 E0353B 0 +OP4 E0353C 0 +OP4 E0353D 0 +OP4 E0353E 0 +OP4 E0353F 0 +OP4 E03540 0 +OP4 E03541 0 +OP4 E03542 0 +OP4 E03543 0 +OP4 E03544 0 +OP4 E03545 0 +OP4 E03546 0 +OP4 E03547 0 +OP4 E03548 0 +OP4 E03549 0 +OP4 E0354A 0 +OP4 E0354B 0 +OP4 E0354C 0 +OP4 E0354D 0 +OP4 E0354E 0 +OP4 E0354F 0 +OP4 E03550 0 +OP4 E03551 0 +OP4 E03552 0 +OP4 E03553 0 +OP4 E03554 0 +OP4 E03555 0 +OP4 E03556 0 +OP4 E03557 0 +OP4 E03558 0 +OP4 E03559 0 +OP4 E0355A 0 +OP4 E0355B 0 +OP4 E0355C 0 +OP4 E0355D 0 +OP4 E0355E 0 +OP4 E0355F 0 +OP4 E03560 0 +OP4 E03561 0 +OP4 E03562 0 +OP4 E03563 0 +OP4 E03564 0 +OP4 E03565 0 +OP4 E03566 0 +OP4 E03567 0 +OP4 E03568 0 +OP4 E03569 0 +OP4 E0356A 0 +OP4 E0356B 0 +OP4 E0356C 0 +OP4 E0356D 0 +OP4 E0356E 0 +OP4 E0356F 0 +OP4 E03570 0 +OP4 E03571 0 +OP4 E03572 0 +OP4 E03573 0 +OP4 E03574 0 +OP4 E03575 0 +OP4 E03576 0 +OP4 E03577 0 +OP4 E03578 0 +OP4 E03579 0 +OP4 E0357A 0 +OP4 E0357B 0 +OP4 E0357C 0 +OP4 E0357D 0 +OP4 E0357E 0 +OP4 E0357F 0 +OP4 E03580 0 +OP4 E03581 0 +OP4 E03582 0 +OP4 E03583 0 +OP4 E03584 0 +OP4 E03585 0 +OP4 E03586 0 +OP4 E03587 0 +OP4 E03588 0 +OP4 E03589 0 +OP4 E0358A 0 +OP4 E0358B 0 +OP4 E0358C 0 +OP4 E0358D 0 +OP4 E0358E 0 +OP4 E0358F 0 +OP4 E03590 0 +OP4 E03591 0 +OP4 E03592 0 +OP4 E03593 0 +OP4 E03594 0 +OP4 E03595 0 +OP4 E03596 0 +OP4 E03597 0 +OP4 E03598 0 +OP4 E03599 0 +OP4 E0359A 0 +OP4 E0359B 0 +OP4 E0359C 0 +OP4 E0359D 0 +OP4 E0359E 0 +OP4 E0359F 0 +OP4 E035A0 0 +OP4 E035A1 0 +OP4 E035A2 0 +OP4 E035A3 0 +OP4 E035A4 0 +OP4 E035A5 0 +OP4 E035A6 0 +OP4 E035A7 0 +OP4 E035A8 0 +OP4 E035A9 0 +OP4 E035AA 0 +OP4 E035AB 0 +OP4 E035AC 0 +OP4 E035AD 0 +OP4 E035AE 0 +OP4 E035AF 0 +OP4 E035B0 0 +OP4 E035B1 0 +OP4 E035B2 0 +OP4 E035B3 0 +OP4 E035B4 0 +OP4 E035B5 0 +OP4 E035B6 0 +OP4 E035B7 0 +OP4 E035B8 0 +OP4 E035B9 0 +OP4 E035BA 0 +OP4 E035BB 0 +OP4 E035BC 0 +OP4 E035BD 0 +OP4 E035BE 0 +OP4 E035BF 0 +OP4 E035C0 0 +OP4 E035C1 0 +OP4 E035C2 0 +OP4 E035C3 0 +OP4 E035C4 0 +OP4 E035C5 0 +OP4 E035C6 0 +OP4 E035C7 0 +OP4 E035C8 0 +OP4 E035C9 0 +OP4 E035CA 0 +OP4 E035CB 0 +OP4 E035CC 0 +OP4 E035CD 0 +OP4 E035CE 0 +OP4 E035CF 0 +OP4 E035D0 0 +OP4 E035D1 0 +OP4 E035D2 0 +OP4 E035D3 0 +OP4 E035D4 0 +OP4 E035D5 0 +OP4 E035D6 0 +OP4 E035D7 0 +OP4 E035D8 0 +OP4 E035D9 0 +OP4 E035DA 0 +OP4 E035DB 0 +OP4 E035DC 0 +OP4 E035DD 0 +OP4 E035DE 0 +OP4 E035DF 0 +OP4 E035E0 0 +OP4 E035E1 0 +OP4 E035E2 0 +OP4 E035E3 0 +OP4 E035E4 0 +OP4 E035E5 0 +OP4 E035E6 0 +OP4 E035E7 0 +OP4 E035E8 0 +OP4 E035E9 0 +OP4 E035EA 0 +OP4 E035EB 0 +OP4 E035EC 0 +OP4 E035ED 0 +OP4 E035EE 0 +OP4 E035EF 0 +OP4 E035F0 0 +OP4 E035F1 0 +OP4 E035F2 0 +OP4 E035F3 0 +OP4 E035F4 0 +OP4 E035F5 0 +OP4 E035F6 0 +OP4 E035F7 0 +OP4 E035F8 0 +OP4 E035F9 0 +OP4 E035FA 0 +OP4 E035FB 0 +OP4 E035FC 0 +OP4 E035FD 0 +OP4 E035FE 0 +OP4 E035FF 0 +OP4 E03600 0 +OP4 E03601 0 +OP4 E03602 0 +OP4 E03603 0 +OP4 E03604 0 +OP4 E03605 0 +OP4 E03606 0 +OP4 E03607 0 +OP4 E03608 0 +OP4 E03609 0 +OP4 E0360A 0 +OP4 E0360B 0 +OP4 E0360C 0 +OP4 E0360D 0 +OP4 E0360E 0 +OP4 E0360F 0 +OP4 E03610 0 +OP4 E03611 0 +OP4 E03612 0 +OP4 E03613 0 +OP4 E03614 0 +OP4 E03615 0 +OP4 E03616 0 +OP4 E03617 0 +OP4 E03618 0 +OP4 E03619 0 +OP4 E0361A 0 +OP4 E0361B 0 +OP4 E0361C 0 +OP4 E0361D 0 +OP4 E0361E 0 +OP4 E0361F 0 +OP4 E03620 0 +OP4 E03621 0 +OP4 E03622 0 +OP4 E03623 0 +OP4 E03624 0 +OP4 E03625 0 +OP4 E03626 0 +OP4 E03627 0 +OP4 E03628 0 +OP4 E03629 0 +OP4 E0362A 0 +OP4 E0362B 0 +OP4 E0362C 0 +OP4 E0362D 0 +OP4 E0362E 0 +OP4 E0362F 0 +OP4 E03630 0 +OP4 E03631 0 +OP4 E03632 0 +OP4 E03633 0 +OP4 E03634 0 +OP4 E03635 0 +OP4 E03636 0 +OP4 E03637 0 +OP4 E03638 0 +OP4 E03639 0 +OP4 E0363A 0 +OP4 E0363B 0 +OP4 E0363C 0 +OP4 E0363D 0 +OP4 E0363E 0 +OP4 E0363F 0 +OP4 E03640 0 +OP4 E03641 0 +OP4 E03642 0 +OP4 E03643 0 +OP4 E03644 0 +OP4 E03645 0 +OP4 E03646 0 +OP4 E03647 0 +OP4 E03648 0 +OP4 E03649 0 +OP4 E0364A 0 +OP4 E0364B 0 +OP4 E0364C 0 +OP4 E0364D 0 +OP4 E0364E 0 +OP4 E0364F 0 +OP4 E03650 0 +OP4 E03651 0 +OP4 E03652 0 +OP4 E03653 0 +OP4 E03654 0 +OP4 E03655 0 +OP4 E03656 0 +OP4 E03657 0 +OP4 E03658 0 +OP4 E03659 0 +OP4 E0365A 0 +OP4 E0365B 0 +OP4 E0365C 0 +OP4 E0365D 0 +OP4 E0365E 0 +OP4 E0365F 0 +OP4 E03660 0 +OP4 E03661 0 +OP4 E03662 0 +OP4 E03663 0 +OP4 E03664 0 +OP4 E03665 0 +OP4 E03666 0 +OP4 E03667 0 +OP4 E03668 0 +OP4 E03669 0 +OP4 E0366A 0 +OP4 E0366B 0 +OP4 E0366C 0 +OP4 E0366D 0 +OP4 E0366E 0 +OP4 E0366F 0 +OP4 E03670 0 +OP4 E03671 0 +OP4 E03672 0 +OP4 E03673 0 +OP4 E03674 0 +OP4 E03675 0 +OP4 E03676 0 +OP4 E03677 0 +OP4 E03678 0 +OP4 E03679 0 +OP4 E0367A 0 +OP4 E0367B 0 +OP4 E0367C 0 +OP4 E0367D 0 +OP4 E0367E 0 +OP4 E0367F 0 +OP4 E03680 0 +OP4 E03681 0 +OP4 E03682 0 +OP4 E03683 0 +OP4 E03684 0 +OP4 E03685 0 +OP4 E03686 0 +OP4 E03687 0 +OP4 E03688 0 +OP4 E03689 0 +OP4 E0368A 0 +OP4 E0368B 0 +OP4 E0368C 0 +OP4 E0368D 0 +OP4 E0368E 0 +OP4 E0368F 0 +OP4 E03690 0 +OP4 E03691 0 +OP4 E03692 0 +OP4 E03693 0 +OP4 E03694 0 +OP4 E03695 0 +OP4 E03696 0 +OP4 E03697 0 +OP4 E03698 0 +OP4 E03699 0 +OP4 E0369A 0 +OP4 E0369B 0 +OP4 E0369C 0 +OP4 E0369D 0 +OP4 E0369E 0 +OP4 E0369F 0 +OP4 E036A0 0 +OP4 E036A1 0 +OP4 E036A2 0 +OP4 E036A3 0 +OP4 E036A4 0 +OP4 E036A5 0 +OP4 E036A6 0 +OP4 E036A7 0 +OP4 E036A8 0 +OP4 E036A9 0 +OP4 E036AA 0 +OP4 E036AB 0 +OP4 E036AC 0 +OP4 E036AD 0 +OP4 E036AE 0 +OP4 E036AF 0 +OP4 E036B0 0 +OP4 E036B1 0 +OP4 E036B2 0 +OP4 E036B3 0 +OP4 E036B4 0 +OP4 E036B5 0 +OP4 E036B6 0 +OP4 E036B7 0 +OP4 E036B8 0 +OP4 E036B9 0 +OP4 E036BA 0 +OP4 E036BB 0 +OP4 E036BC 0 +OP4 E036BD 0 +OP4 E036BE 0 +OP4 E036BF 0 +OP4 E036C0 0 +OP4 E036C1 0 +OP4 E036C2 0 +OP4 E036C3 0 +OP4 E036C4 0 +OP4 E036C5 0 +OP4 E036C6 0 +OP4 E036C7 0 +OP4 E036C8 0 +OP4 E036C9 0 +OP4 E036CA 0 +OP4 E036CB 0 +OP4 E036CC 0 +OP4 E036CD 0 +OP4 E036CE 0 +OP4 E036CF 0 +OP4 E036D0 0 +OP4 E036D1 0 +OP4 E036D2 0 +OP4 E036D3 0 +OP4 E036D4 0 +OP4 E036D5 0 +OP4 E036D6 0 +OP4 E036D7 0 +OP4 E036D8 0 +OP4 E036D9 0 +OP4 E036DA 0 +OP4 E036DB 0 +OP4 E036DC 0 +OP4 E036DD 0 +OP4 E036DE 0 +OP4 E036DF 0 +OP4 E036E0 0 +OP4 E036E1 0 +OP4 E036E2 0 +OP4 E036E3 0 +OP4 E036E4 0 +OP4 E036E5 0 +OP4 E036E6 0 +OP4 E036E7 0 +OP4 E036E8 0 +OP4 E036E9 0 +OP4 E036EA 0 +OP4 E036EB 0 +OP4 E036EC 0 +OP4 E036ED 0 +OP4 E036EE 0 +OP4 E036EF 0 +OP4 E036F0 0 +OP4 E036F1 0 +OP4 E036F2 0 +OP4 E036F3 0 +OP4 E036F4 0 +OP4 E036F5 0 +OP4 E036F6 0 +OP4 E036F7 0 +OP4 E036F8 0 +OP4 E036F9 0 +OP4 E036FA 0 +OP4 E036FB 0 +OP4 E036FC 0 +OP4 E036FD 0 +OP4 E036FE 0 +OP4 E036FF 0 +OP4 E03700 0 +OP4 E03701 0 +OP4 E03702 0 +OP4 E03703 0 +OP4 E03704 0 +OP4 E03705 0 +OP4 E03706 0 +OP4 E03707 0 +OP4 E03708 0 +OP4 E03709 0 +OP4 E0370A 0 +OP4 E0370B 0 +OP4 E0370C 0 +OP4 E0370D 0 +OP4 E0370E 0 +OP4 E0370F 0 +OP4 E03710 0 +OP4 E03711 0 +OP4 E03712 0 +OP4 E03713 0 +OP4 E03714 0 +OP4 E03715 0 +OP4 E03716 0 +OP4 E03717 0 +OP4 E03718 0 +OP4 E03719 0 +OP4 E0371A 0 +OP4 E0371B 0 +OP4 E0371C 0 +OP4 E0371D 0 +OP4 E0371E 0 +OP4 E0371F 0 +OP4 E03720 0 +OP4 E03721 0 +OP4 E03722 0 +OP4 E03723 0 +OP4 E03724 0 +OP4 E03725 0 +OP4 E03726 0 +OP4 E03727 0 +OP4 E03728 0 +OP4 E03729 0 +OP4 E0372A 0 +OP4 E0372B 0 +OP4 E0372C 0 +OP4 E0372D 0 +OP4 E0372E 0 +OP4 E0372F 0 +OP4 E03730 0 +OP4 E03731 0 +OP4 E03732 0 +OP4 E03733 0 +OP4 E03734 0 +OP4 E03735 0 +OP4 E03736 0 +OP4 E03737 0 +OP4 E03738 0 +OP4 E03739 0 +OP4 E0373A 0 +OP4 E0373B 0 +OP4 E0373C 0 +OP4 E0373D 0 +OP4 E0373E 0 +OP4 E0373F 0 +OP4 E03740 0 +OP4 E03741 0 +OP4 E03742 0 +OP4 E03743 0 +OP4 E03744 0 +OP4 E03745 0 +OP4 E03746 0 +OP4 E03747 0 +OP4 E03748 0 +OP4 E03749 0 +OP4 E0374A 0 +OP4 E0374B 0 +OP4 E0374C 0 +OP4 E0374D 0 +OP4 E0374E 0 +OP4 E0374F 0 +OP4 E03750 0 +OP4 E03751 0 +OP4 E03752 0 +OP4 E03753 0 +OP4 E03754 0 +OP4 E03755 0 +OP4 E03756 0 +OP4 E03757 0 +OP4 E03758 0 +OP4 E03759 0 +OP4 E0375A 0 +OP4 E0375B 0 +OP4 E0375C 0 +OP4 E0375D 0 +OP4 E0375E 0 +OP4 E0375F 0 +OP4 E03760 0 +OP4 E03761 0 +OP4 E03762 0 +OP4 E03763 0 +OP4 E03764 0 +OP4 E03765 0 +OP4 E03766 0 +OP4 E03767 0 +OP4 E03768 0 +OP4 E03769 0 +OP4 E0376A 0 +OP4 E0376B 0 +OP4 E0376C 0 +OP4 E0376D 0 +OP4 E0376E 0 +OP4 E0376F 0 +OP4 E03770 0 +OP4 E03771 0 +OP4 E03772 0 +OP4 E03773 0 +OP4 E03774 0 +OP4 E03775 0 +OP4 E03776 0 +OP4 E03777 0 +OP4 E03778 0 +OP4 E03779 0 +OP4 E0377A 0 +OP4 E0377B 0 +OP4 E0377C 0 +OP4 E0377D 0 +OP4 E0377E 0 +OP4 E0377F 0 +OP4 E03780 0 +OP4 E03781 0 +OP4 E03782 0 +OP4 E03783 0 +OP4 E03784 0 +OP4 E03785 0 +OP4 E03786 0 +OP4 E03787 0 +OP4 E03788 0 +OP4 E03789 0 +OP4 E0378A 0 +OP4 E0378B 0 +OP4 E0378C 0 +OP4 E0378D 0 +OP4 E0378E 0 +OP4 E0378F 0 +OP4 E03790 0 +OP4 E03791 0 +OP4 E03792 0 +OP4 E03793 0 +OP4 E03794 0 +OP4 E03795 0 +OP4 E03796 0 +OP4 E03797 0 +OP4 E03798 0 +OP4 E03799 0 +OP4 E0379A 0 +OP4 E0379B 0 +OP4 E0379C 0 +OP4 E0379D 0 +OP4 E0379E 0 +OP4 E0379F 0 +OP4 E037A0 0 +OP4 E037A1 0 +OP4 E037A2 0 +OP4 E037A3 0 +OP4 E037A4 0 +OP4 E037A5 0 +OP4 E037A6 0 +OP4 E037A7 0 +OP4 E037A8 0 +OP4 E037A9 0 +OP4 E037AA 0 +OP4 E037AB 0 +OP4 E037AC 0 +OP4 E037AD 0 +OP4 E037AE 0 +OP4 E037AF 0 +OP4 E037B0 0 +OP4 E037B1 0 +OP4 E037B2 0 +OP4 E037B3 0 +OP4 E037B4 0 +OP4 E037B5 0 +OP4 E037B6 0 +OP4 E037B7 0 +OP4 E037B8 0 +OP4 E037B9 0 +OP4 E037BA 0 +OP4 E037BB 0 +OP4 E037BC 0 +OP4 E037BD 0 +OP4 E037BE 0 +OP4 E037BF 0 +OP4 E037C0 0 +OP4 E037C1 0 +OP4 E037C2 0 +OP4 E037C3 0 +OP4 E037C4 0 +OP4 E037C5 0 +OP4 E037C6 0 +OP4 E037C7 0 +OP4 E037C8 0 +OP4 E037C9 0 +OP4 E037CA 0 +OP4 E037CB 0 +OP4 E037CC 0 +OP4 E037CD 0 +OP4 E037CE 0 +OP4 E037CF 0 +OP4 E037D0 0 +OP4 E037D1 0 +OP4 E037D2 0 +OP4 E037D3 0 +OP4 E037D4 0 +OP4 E037D5 0 +OP4 E037D6 0 +OP4 E037D7 0 +OP4 E037D8 0 +OP4 E037D9 0 +OP4 E037DA 0 +OP4 E037DB 0 +OP4 E037DC 0 +OP4 E037DD 0 +OP4 E037DE 0 +OP4 E037DF 0 +OP4 E037E0 0 +OP4 E037E1 0 +OP4 E037E2 0 +OP4 E037E3 0 +OP4 E037E4 0 +OP4 E037E5 0 +OP4 E037E6 0 +OP4 E037E7 0 +OP4 E037E8 0 +OP4 E037E9 0 +OP4 E037EA 0 +OP4 E037EB 0 +OP4 E037EC 0 +OP4 E037ED 0 +OP4 E037EE 0 +OP4 E037EF 0 +OP4 E037F0 0 +OP4 E037F1 0 +OP4 E037F2 0 +OP4 E037F3 0 +OP4 E037F4 0 +OP4 E037F5 0 +OP4 E037F6 0 +OP4 E037F7 0 +OP4 E037F8 0 +OP4 E037F9 0 +OP4 E037FA 0 +OP4 E037FB 0 +OP4 E037FC 0 +OP4 E037FD 0 +OP4 E037FE 0 +OP4 E037FF 0 +OP4 E03800 0 +OP4 E03801 0 +OP4 E03802 0 +OP4 E03803 0 +OP4 E03804 0 +OP4 E03805 0 +OP4 E03806 0 +OP4 E03807 0 +OP4 E03808 0 +OP4 E03809 0 +OP4 E0380A 0 +OP4 E0380B 0 +OP4 E0380C 0 +OP4 E0380D 0 +OP4 E0380E 0 +OP4 E0380F 0 +OP4 E03810 0 +OP4 E03811 0 +OP4 E03812 0 +OP4 E03813 0 +OP4 E03814 0 +OP4 E03815 0 +OP4 E03816 0 +OP4 E03817 0 +OP4 E03818 0 +OP4 E03819 0 +OP4 E0381A 0 +OP4 E0381B 0 +OP4 E0381C 0 +OP4 E0381D 0 +OP4 E0381E 0 +OP4 E0381F 0 +OP4 E03820 0 +OP4 E03821 0 +OP4 E03822 0 +OP4 E03823 0 +OP4 E03824 0 +OP4 E03825 0 +OP4 E03826 0 +OP4 E03827 0 +OP4 E03828 0 +OP4 E03829 0 +OP4 E0382A 0 +OP4 E0382B 0 +OP4 E0382C 0 +OP4 E0382D 0 +OP4 E0382E 0 +OP4 E0382F 0 +OP4 E03830 0 +OP4 E03831 0 +OP4 E03832 0 +OP4 E03833 0 +OP4 E03834 0 +OP4 E03835 0 +OP4 E03836 0 +OP4 E03837 0 +OP4 E03838 0 +OP4 E03839 0 +OP4 E0383A 0 +OP4 E0383B 0 +OP4 E0383C 0 +OP4 E0383D 0 +OP4 E0383E 0 +OP4 E0383F 0 +OP4 E03840 0 +OP4 E03841 0 +OP4 E03842 0 +OP4 E03843 0 +OP4 E03844 0 +OP4 E03845 0 +OP4 E03846 0 +OP4 E03847 0 +OP4 E03848 0 +OP4 E03849 0 +OP4 E0384A 0 +OP4 E0384B 0 +OP4 E0384C 0 +OP4 E0384D 0 +OP4 E0384E 0 +OP4 E0384F 0 +OP4 E03850 0 +OP4 E03851 0 +OP4 E03852 0 +OP4 E03853 0 +OP4 E03854 0 +OP4 E03855 0 +OP4 E03856 0 +OP4 E03857 0 +OP4 E03858 0 +OP4 E03859 0 +OP4 E0385A 0 +OP4 E0385B 0 +OP4 E0385C 0 +OP4 E0385D 0 +OP4 E0385E 0 +OP4 E0385F 0 +OP4 E03860 0 +OP4 E03861 0 +OP4 E03862 0 +OP4 E03863 0 +OP4 E03864 0 +OP4 E03865 0 +OP4 E03866 0 +OP4 E03867 0 +OP4 E03868 0 +OP4 E03869 0 +OP4 E0386A 0 +OP4 E0386B 0 +OP4 E0386C 0 +OP4 E0386D 0 +OP4 E0386E 0 +OP4 E0386F 0 +OP4 E03870 0 +OP4 E03871 0 +OP4 E03872 0 +OP4 E03873 0 +OP4 E03874 0 +OP4 E03875 0 +OP4 E03876 0 +OP4 E03877 0 +OP4 E03878 0 +OP4 E03879 0 +OP4 E0387A 0 +OP4 E0387B 0 +OP4 E0387C 0 +OP4 E0387D 0 +OP4 E0387E 0 +OP4 E0387F 0 +OP4 E03880 0 +OP4 E03881 0 +OP4 E03882 0 +OP4 E03883 0 +OP4 E03884 0 +OP4 E03885 0 +OP4 E03886 0 +OP4 E03887 0 +OP4 E03888 0 +OP4 E03889 0 +OP4 E0388A 0 +OP4 E0388B 0 +OP4 E0388C 0 +OP4 E0388D 0 +OP4 E0388E 0 +OP4 E0388F 0 +OP4 E03890 0 +OP4 E03891 0 +OP4 E03892 0 +OP4 E03893 0 +OP4 E03894 0 +OP4 E03895 0 +OP4 E03896 0 +OP4 E03897 0 +OP4 E03898 0 +OP4 E03899 0 +OP4 E0389A 0 +OP4 E0389B 0 +OP4 E0389C 0 +OP4 E0389D 0 +OP4 E0389E 0 +OP4 E0389F 0 +OP4 E038A0 0 +OP4 E038A1 0 +OP4 E038A2 0 +OP4 E038A3 0 +OP4 E038A4 0 +OP4 E038A5 0 +OP4 E038A6 0 +OP4 E038A7 0 +OP4 E038A8 0 +OP4 E038A9 0 +OP4 E038AA 0 +OP4 E038AB 0 +OP4 E038AC 0 +OP4 E038AD 0 +OP4 E038AE 0 +OP4 E038AF 0 +OP4 E038B0 0 +OP4 E038B1 0 +OP4 E038B2 0 +OP4 E038B3 0 +OP4 E038B4 0 +OP4 E038B5 0 +OP4 E038B6 0 +OP4 E038B7 0 +OP4 E038B8 0 +OP4 E038B9 0 +OP4 E038BA 0 +OP4 E038BB 0 +OP4 E038BC 0 +OP4 E038BD 0 +OP4 E038BE 0 +OP4 E038BF 0 +OP4 E038C0 0 +OP4 E038C1 0 +OP4 E038C2 0 +OP4 E038C3 0 +OP4 E038C4 0 +OP4 E038C5 0 +OP4 E038C6 0 +OP4 E038C7 0 +OP4 E038C8 0 +OP4 E038C9 0 +OP4 E038CA 0 +OP4 E038CB 0 +OP4 E038CC 0 +OP4 E038CD 0 +OP4 E038CE 0 +OP4 E038CF 0 +OP4 E038D0 0 +OP4 E038D1 0 +OP4 E038D2 0 +OP4 E038D3 0 +OP4 E038D4 0 +OP4 E038D5 0 +OP4 E038D6 0 +OP4 E038D7 0 +OP4 E038D8 0 +OP4 E038D9 0 +OP4 E038DA 0 +OP4 E038DB 0 +OP4 E038DC 0 +OP4 E038DD 0 +OP4 E038DE 0 +OP4 E038DF 0 +OP4 E038E0 0 +OP4 E038E1 0 +OP4 E038E2 0 +OP4 E038E3 0 +OP4 E038E4 0 +OP4 E038E5 0 +OP4 E038E6 0 +OP4 E038E7 0 +OP4 E038E8 0 +OP4 E038E9 0 +OP4 E038EA 0 +OP4 E038EB 0 +OP4 E038EC 0 +OP4 E038ED 0 +OP4 E038EE 0 +OP4 E038EF 0 +OP4 E038F0 0 +OP4 E038F1 0 +OP4 E038F2 0 +OP4 E038F3 0 +OP4 E038F4 0 +OP4 E038F5 0 +OP4 E038F6 0 +OP4 E038F7 0 +OP4 E038F8 0 +OP4 E038F9 0 +OP4 E038FA 0 +OP4 E038FB 0 +OP4 E038FC 0 +OP4 E038FD 0 +OP4 E038FE 0 +OP4 E038FF 0 +OP4 E03900 0 +OP4 E03901 0 +OP4 E03902 0 +OP4 E03903 0 +OP4 E03904 0 +OP4 E03905 0 +OP4 E03906 0 +OP4 E03907 0 +OP4 E03908 0 +OP4 E03909 0 +OP4 E0390A 0 +OP4 E0390B 0 +OP4 E0390C 0 +OP4 E0390D 0 +OP4 E0390E 0 +OP4 E0390F 0 +OP4 E03910 0 +OP4 E03911 0 +OP4 E03912 0 +OP4 E03913 0 +OP4 E03914 0 +OP4 E03915 0 +OP4 E03916 0 +OP4 E03917 0 +OP4 E03918 0 +OP4 E03919 0 +OP4 E0391A 0 +OP4 E0391B 0 +OP4 E0391C 0 +OP4 E0391D 0 +OP4 E0391E 0 +OP4 E0391F 0 +OP4 E03920 0 +OP4 E03921 0 +OP4 E03922 0 +OP4 E03923 0 +OP4 E03924 0 +OP4 E03925 0 +OP4 E03926 0 +OP4 E03927 0 +OP4 E03928 0 +OP4 E03929 0 +OP4 E0392A 0 +OP4 E0392B 0 +OP4 E0392C 0 +OP4 E0392D 0 +OP4 E0392E 0 +OP4 E0392F 0 +OP4 E03930 0 +OP4 E03931 0 +OP4 E03932 0 +OP4 E03933 0 +OP4 E03934 0 +OP4 E03935 0 +OP4 E03936 0 +OP4 E03937 0 +OP4 E03938 0 +OP4 E03939 0 +OP4 E0393A 0 +OP4 E0393B 0 +OP4 E0393C 0 +OP4 E0393D 0 +OP4 E0393E 0 +OP4 E0393F 0 +OP4 E03940 0 +OP4 E03941 0 +OP4 E03942 0 +OP4 E03943 0 +OP4 E03944 0 +OP4 E03945 0 +OP4 E03946 0 +OP4 E03947 0 +OP4 E03948 0 +OP4 E03949 0 +OP4 E0394A 0 +OP4 E0394B 0 +OP4 E0394C 0 +OP4 E0394D 0 +OP4 E0394E 0 +OP4 E0394F 0 +OP4 E03950 0 +OP4 E03951 0 +OP4 E03952 0 +OP4 E03953 0 +OP4 E03954 0 +OP4 E03955 0 +OP4 E03956 0 +OP4 E03957 0 +OP4 E03958 0 +OP4 E03959 0 +OP4 E0395A 0 +OP4 E0395B 0 +OP4 E0395C 0 +OP4 E0395D 0 +OP4 E0395E 0 +OP4 E0395F 0 +OP4 E03960 0 +OP4 E03961 0 +OP4 E03962 0 +OP4 E03963 0 +OP4 E03964 0 +OP4 E03965 0 +OP4 E03966 0 +OP4 E03967 0 +OP4 E03968 0 +OP4 E03969 0 +OP4 E0396A 0 +OP4 E0396B 0 +OP4 E0396C 0 +OP4 E0396D 0 +OP4 E0396E 0 +OP4 E0396F 0 +OP4 E03970 0 +OP4 E03971 0 +OP4 E03972 0 +OP4 E03973 0 +OP4 E03974 0 +OP4 E03975 0 +OP4 E03976 0 +OP4 E03977 0 +OP4 E03978 0 +OP4 E03979 0 +OP4 E0397A 0 +OP4 E0397B 0 +OP4 E0397C 0 +OP4 E0397D 0 +OP4 E0397E 0 +OP4 E0397F 0 +OP4 E03980 0 +OP4 E03981 0 +OP4 E03982 0 +OP4 E03983 0 +OP4 E03984 0 +OP4 E03985 0 +OP4 E03986 0 +OP4 E03987 0 +OP4 E03988 0 +OP4 E03989 0 +OP4 E0398A 0 +OP4 E0398B 0 +OP4 E0398C 0 +OP4 E0398D 0 +OP4 E0398E 0 +OP4 E0398F 0 +OP4 E03990 0 +OP4 E03991 0 +OP4 E03992 0 +OP4 E03993 0 +OP4 E03994 0 +OP4 E03995 0 +OP4 E03996 0 +OP4 E03997 0 +OP4 E03998 0 +OP4 E03999 0 +OP4 E0399A 0 +OP4 E0399B 0 +OP4 E0399C 0 +OP4 E0399D 0 +OP4 E0399E 0 +OP4 E0399F 0 +OP4 E039A0 0 +OP4 E039A1 0 +OP4 E039A2 0 +OP4 E039A3 0 +OP4 E039A4 0 +OP4 E039A5 0 +OP4 E039A6 0 +OP4 E039A7 0 +OP4 E039A8 0 +OP4 E039A9 0 +OP4 E039AA 0 +OP4 E039AB 0 +OP4 E039AC 0 +OP4 E039AD 0 +OP4 E039AE 0 +OP4 E039AF 0 +OP4 E039B0 0 +OP4 E039B1 0 +OP4 E039B2 0 +OP4 E039B3 0 +OP4 E039B4 0 +OP4 E039B5 0 +OP4 E039B6 0 +OP4 E039B7 0 +OP4 E039B8 0 +OP4 E039B9 0 +OP4 E039BA 0 +OP4 E039BB 0 +OP4 E039BC 0 +OP4 E039BD 0 +OP4 E039BE 0 +OP4 E039BF 0 +OP4 E039C0 0 +OP4 E039C1 0 +OP4 E039C2 0 +OP4 E039C3 0 +OP4 E039C4 0 +OP4 E039C5 0 +OP4 E039C6 0 +OP4 E039C7 0 +OP4 E039C8 0 +OP4 E039C9 0 +OP4 E039CA 0 +OP4 E039CB 0 +OP4 E039CC 0 +OP4 E039CD 0 +OP4 E039CE 0 +OP4 E039CF 0 +OP4 E039D0 0 +OP4 E039D1 0 +OP4 E039D2 0 +OP4 E039D3 0 +OP4 E039D4 0 +OP4 E039D5 0 +OP4 E039D6 0 +OP4 E039D7 0 +OP4 E039D8 0 +OP4 E039D9 0 +OP4 E039DA 0 +OP4 E039DB 0 +OP4 E039DC 0 +OP4 E039DD 0 +OP4 E039DE 0 +OP4 E039DF 0 +OP4 E039E0 0 +OP4 E039E1 0 +OP4 E039E2 0 +OP4 E039E3 0 +OP4 E039E4 0 +OP4 E039E5 0 +OP4 E039E6 0 +OP4 E039E7 0 +OP4 E039E8 0 +OP4 E039E9 0 +OP4 E039EA 0 +OP4 E039EB 0 +OP4 E039EC 0 +OP4 E039ED 0 +OP4 E039EE 0 +OP4 E039EF 0 +OP4 E039F0 0 +OP4 E039F1 0 +OP4 E039F2 0 +OP4 E039F3 0 +OP4 E039F4 0 +OP4 E039F5 0 +OP4 E039F6 0 +OP4 E039F7 0 +OP4 E039F8 0 +OP4 E039F9 0 +OP4 E039FA 0 +OP4 E039FB 0 +OP4 E039FC 0 +OP4 E039FD 0 +OP4 E039FE 0 +OP4 E039FF 0 +OP4 E03A00 0 +OP4 E03A01 0 +OP4 E03A02 0 +OP4 E03A03 0 +OP4 E03A04 0 +OP4 E03A05 0 +OP4 E03A06 0 +OP4 E03A07 0 +OP4 E03A08 0 +OP4 E03A09 0 +OP4 E03A0A 0 +OP4 E03A0B 0 +OP4 E03A0C 0 +OP4 E03A0D 0 +OP4 E03A0E 0 +OP4 E03A0F 0 +OP4 E03A10 0 +OP4 E03A11 0 +OP4 E03A12 0 +OP4 E03A13 0 +OP4 E03A14 0 +OP4 E03A15 0 +OP4 E03A16 0 +OP4 E03A17 0 +OP4 E03A18 0 +OP4 E03A19 0 +OP4 E03A1A 0 +OP4 E03A1B 0 +OP4 E03A1C 0 +OP4 E03A1D 0 +OP4 E03A1E 0 +OP4 E03A1F 0 +OP4 E03A20 0 +OP4 E03A21 0 +OP4 E03A22 0 +OP4 E03A23 0 +OP4 E03A24 0 +OP4 E03A25 0 +OP4 E03A26 0 +OP4 E03A27 0 +OP4 E03A28 0 +OP4 E03A29 0 +OP4 E03A2A 0 +OP4 E03A2B 0 +OP4 E03A2C 0 +OP4 E03A2D 0 +OP4 E03A2E 0 +OP4 E03A2F 0 +OP4 E03A30 0 +OP4 E03A31 0 +OP4 E03A32 0 +OP4 E03A33 0 +OP4 E03A34 0 +OP4 E03A35 0 +OP4 E03A36 0 +OP4 E03A37 0 +OP4 E03A38 0 +OP4 E03A39 0 +OP4 E03A3A 0 +OP4 E03A3B 0 +OP4 E03A3C 0 +OP4 E03A3D 0 +OP4 E03A3E 0 +OP4 E03A3F 0 +OP4 E03A40 0 +OP4 E03A41 0 +OP4 E03A42 0 +OP4 E03A43 0 +OP4 E03A44 0 +OP4 E03A45 0 +OP4 E03A46 0 +OP4 E03A47 0 +OP4 E03A48 0 +OP4 E03A49 0 +OP4 E03A4A 0 +OP4 E03A4B 0 +OP4 E03A4C 0 +OP4 E03A4D 0 +OP4 E03A4E 0 +OP4 E03A4F 0 +OP4 E03A50 0 +OP4 E03A51 0 +OP4 E03A52 0 +OP4 E03A53 0 +OP4 E03A54 0 +OP4 E03A55 0 +OP4 E03A56 0 +OP4 E03A57 0 +OP4 E03A58 0 +OP4 E03A59 0 +OP4 E03A5A 0 +OP4 E03A5B 0 +OP4 E03A5C 0 +OP4 E03A5D 0 +OP4 E03A5E 0 +OP4 E03A5F 0 +OP4 E03A60 0 +OP4 E03A61 0 +OP4 E03A62 0 +OP4 E03A63 0 +OP4 E03A64 0 +OP4 E03A65 0 +OP4 E03A66 0 +OP4 E03A67 0 +OP4 E03A68 0 +OP4 E03A69 0 +OP4 E03A6A 0 +OP4 E03A6B 0 +OP4 E03A6C 0 +OP4 E03A6D 0 +OP4 E03A6E 0 +OP4 E03A6F 0 +OP4 E03A70 0 +OP4 E03A71 0 +OP4 E03A72 0 +OP4 E03A73 0 +OP4 E03A74 0 +OP4 E03A75 0 +OP4 E03A76 0 +OP4 E03A77 0 +OP4 E03A78 0 +OP4 E03A79 0 +OP4 E03A7A 0 +OP4 E03A7B 0 +OP4 E03A7C 0 +OP4 E03A7D 0 +OP4 E03A7E 0 +OP4 E03A7F 0 +OP4 E03A80 0 +OP4 E03A81 0 +OP4 E03A82 0 +OP4 E03A83 0 +OP4 E03A84 0 +OP4 E03A85 0 +OP4 E03A86 0 +OP4 E03A87 0 +OP4 E03A88 0 +OP4 E03A89 0 +OP4 E03A8A 0 +OP4 E03A8B 0 +OP4 E03A8C 0 +OP4 E03A8D 0 +OP4 E03A8E 0 +OP4 E03A8F 0 +OP4 E03A90 0 +OP4 E03A91 0 +OP4 E03A92 0 +OP4 E03A93 0 +OP4 E03A94 0 +OP4 E03A95 0 +OP4 E03A96 0 +OP4 E03A97 0 +OP4 E03A98 0 +OP4 E03A99 0 +OP4 E03A9A 0 +OP4 E03A9B 0 +OP4 E03A9C 0 +OP4 E03A9D 0 +OP4 E03A9E 0 +OP4 E03A9F 0 +OP4 E03AA0 0 +OP4 E03AA1 0 +OP4 E03AA2 0 +OP4 E03AA3 0 +OP4 E03AA4 0 +OP4 E03AA5 0 +OP4 E03AA6 0 +OP4 E03AA7 0 +OP4 E03AA8 0 +OP4 E03AA9 0 +OP4 E03AAA 0 +OP4 E03AAB 0 +OP4 E03AAC 0 +OP4 E03AAD 0 +OP4 E03AAE 0 +OP4 E03AAF 0 +OP4 E03AB0 0 +OP4 E03AB1 0 +OP4 E03AB2 0 +OP4 E03AB3 0 +OP4 E03AB4 0 +OP4 E03AB5 0 +OP4 E03AB6 0 +OP4 E03AB7 0 +OP4 E03AB8 0 +OP4 E03AB9 0 +OP4 E03ABA 0 +OP4 E03ABB 0 +OP4 E03ABC 0 +OP4 E03ABD 0 +OP4 E03ABE 0 +OP4 E03ABF 0 +OP4 E03AC0 0 +OP4 E03AC1 0 +OP4 E03AC2 0 +OP4 E03AC3 0 +OP4 E03AC4 0 +OP4 E03AC5 0 +OP4 E03AC6 0 +OP4 E03AC7 0 +OP4 E03AC8 0 +OP4 E03AC9 0 +OP4 E03ACA 0 +OP4 E03ACB 0 +OP4 E03ACC 0 +OP4 E03ACD 0 +OP4 E03ACE 0 +OP4 E03ACF 0 +OP4 E03AD0 0 +OP4 E03AD1 0 +OP4 E03AD2 0 +OP4 E03AD3 0 +OP4 E03AD4 0 +OP4 E03AD5 0 +OP4 E03AD6 0 +OP4 E03AD7 0 +OP4 E03AD8 0 +OP4 E03AD9 0 +OP4 E03ADA 0 +OP4 E03ADB 0 +OP4 E03ADC 0 +OP4 E03ADD 0 +OP4 E03ADE 0 +OP4 E03ADF 0 +OP4 E03AE0 0 +OP4 E03AE1 0 +OP4 E03AE2 0 +OP4 E03AE3 0 +OP4 E03AE4 0 +OP4 E03AE5 0 +OP4 E03AE6 0 +OP4 E03AE7 0 +OP4 E03AE8 0 +OP4 E03AE9 0 +OP4 E03AEA 0 +OP4 E03AEB 0 +OP4 E03AEC 0 +OP4 E03AED 0 +OP4 E03AEE 0 +OP4 E03AEF 0 +OP4 E03AF0 0 +OP4 E03AF1 0 +OP4 E03AF2 0 +OP4 E03AF3 0 +OP4 E03AF4 0 +OP4 E03AF5 0 +OP4 E03AF6 0 +OP4 E03AF7 0 +OP4 E03AF8 0 +OP4 E03AF9 0 +OP4 E03AFA 0 +OP4 E03AFB 0 +OP4 E03AFC 0 +OP4 E03AFD 0 +OP4 E03AFE 0 +OP4 E03AFF 0 +OP4 E03B00 0 +OP4 E03B01 0 +OP4 E03B02 0 +OP4 E03B03 0 +OP4 E03B04 0 +OP4 E03B05 0 +OP4 E03B06 0 +OP4 E03B07 0 +OP4 E03B08 0 +OP4 E03B09 0 +OP4 E03B0A 0 +OP4 E03B0B 0 +OP4 E03B0C 0 +OP4 E03B0D 0 +OP4 E03B0E 0 +OP4 E03B0F 0 +OP4 E03B10 0 +OP4 E03B11 0 +OP4 E03B12 0 +OP4 E03B13 0 +OP4 E03B14 0 +OP4 E03B15 0 +OP4 E03B16 0 +OP4 E03B17 0 +OP4 E03B18 0 +OP4 E03B19 0 +OP4 E03B1A 0 +OP4 E03B1B 0 +OP4 E03B1C 0 +OP4 E03B1D 0 +OP4 E03B1E 0 +OP4 E03B1F 0 +OP4 E03B20 0 +OP4 E03B21 0 +OP4 E03B22 0 +OP4 E03B23 0 +OP4 E03B24 0 +OP4 E03B25 0 +OP4 E03B26 0 +OP4 E03B27 0 +OP4 E03B28 0 +OP4 E03B29 0 +OP4 E03B2A 0 +OP4 E03B2B 0 +OP4 E03B2C 0 +OP4 E03B2D 0 +OP4 E03B2E 0 +OP4 E03B2F 0 +OP4 E03B30 0 +OP4 E03B31 0 +OP4 E03B32 0 +OP4 E03B33 0 +OP4 E03B34 0 +OP4 E03B35 0 +OP4 E03B36 0 +OP4 E03B37 0 +OP4 E03B38 0 +OP4 E03B39 0 +OP4 E03B3A 0 +OP4 E03B3B 0 +OP4 E03B3C 0 +OP4 E03B3D 0 +OP4 E03B3E 0 +OP4 E03B3F 0 +OP4 E03B40 0 +OP4 E03B41 0 +OP4 E03B42 0 +OP4 E03B43 0 +OP4 E03B44 0 +OP4 E03B45 0 +OP4 E03B46 0 +OP4 E03B47 0 +OP4 E03B48 0 +OP4 E03B49 0 +OP4 E03B4A 0 +OP4 E03B4B 0 +OP4 E03B4C 0 +OP4 E03B4D 0 +OP4 E03B4E 0 +OP4 E03B4F 0 +OP4 E03B50 0 +OP4 E03B51 0 +OP4 E03B52 0 +OP4 E03B53 0 +OP4 E03B54 0 +OP4 E03B55 0 +OP4 E03B56 0 +OP4 E03B57 0 +OP4 E03B58 0 +OP4 E03B59 0 +OP4 E03B5A 0 +OP4 E03B5B 0 +OP4 E03B5C 0 +OP4 E03B5D 0 +OP4 E03B5E 0 +OP4 E03B5F 0 +OP4 E03B60 0 +OP4 E03B61 0 +OP4 E03B62 0 +OP4 E03B63 0 +OP4 E03B64 0 +OP4 E03B65 0 +OP4 E03B66 0 +OP4 E03B67 0 +OP4 E03B68 0 +OP4 E03B69 0 +OP4 E03B6A 0 +OP4 E03B6B 0 +OP4 E03B6C 0 +OP4 E03B6D 0 +OP4 E03B6E 0 +OP4 E03B6F 0 +OP4 E03B70 0 +OP4 E03B71 0 +OP4 E03B72 0 +OP4 E03B73 0 +OP4 E03B74 0 +OP4 E03B75 0 +OP4 E03B76 0 +OP4 E03B77 0 +OP4 E03B78 0 +OP4 E03B79 0 +OP4 E03B7A 0 +OP4 E03B7B 0 +OP4 E03B7C 0 +OP4 E03B7D 0 +OP4 E03B7E 0 +OP4 E03B7F 0 +OP4 E03B80 0 +OP4 E03B81 0 +OP4 E03B82 0 +OP4 E03B83 0 +OP4 E03B84 0 +OP4 E03B85 0 +OP4 E03B86 0 +OP4 E03B87 0 +OP4 E03B88 0 +OP4 E03B89 0 +OP4 E03B8A 0 +OP4 E03B8B 0 +OP4 E03B8C 0 +OP4 E03B8D 0 +OP4 E03B8E 0 +OP4 E03B8F 0 +OP4 E03B90 0 +OP4 E03B91 0 +OP4 E03B92 0 +OP4 E03B93 0 +OP4 E03B94 0 +OP4 E03B95 0 +OP4 E03B96 0 +OP4 E03B97 0 +OP4 E03B98 0 +OP4 E03B99 0 +OP4 E03B9A 0 +OP4 E03B9B 0 +OP4 E03B9C 0 +OP4 E03B9D 0 +OP4 E03B9E 0 +OP4 E03B9F 0 +OP4 E03BA0 0 +OP4 E03BA1 0 +OP4 E03BA2 0 +OP4 E03BA3 0 +OP4 E03BA4 0 +OP4 E03BA5 0 +OP4 E03BA6 0 +OP4 E03BA7 0 +OP4 E03BA8 0 +OP4 E03BA9 0 +OP4 E03BAA 0 +OP4 E03BAB 0 +OP4 E03BAC 0 +OP4 E03BAD 0 +OP4 E03BAE 0 +OP4 E03BAF 0 +OP4 E03BB0 0 +OP4 E03BB1 0 +OP4 E03BB2 0 +OP4 E03BB3 0 +OP4 E03BB4 0 +OP4 E03BB5 0 +OP4 E03BB6 0 +OP4 E03BB7 0 +OP4 E03BB8 0 +OP4 E03BB9 0 +OP4 E03BBA 0 +OP4 E03BBB 0 +OP4 E03BBC 0 +OP4 E03BBD 0 +OP4 E03BBE 0 +OP4 E03BBF 0 +OP4 E03BC0 0 +OP4 E03BC1 0 +OP4 E03BC2 0 +OP4 E03BC3 0 +OP4 E03BC4 0 +OP4 E03BC5 0 +OP4 E03BC6 0 +OP4 E03BC7 0 +OP4 E03BC8 0 +OP4 E03BC9 0 +OP4 E03BCA 0 +OP4 E03BCB 0 +OP4 E03BCC 0 +OP4 E03BCD 0 +OP4 E03BCE 0 +OP4 E03BCF 0 +OP4 E03BD0 0 +OP4 E03BD1 0 +OP4 E03BD2 0 +OP4 E03BD3 0 +OP4 E03BD4 0 +OP4 E03BD5 0 +OP4 E03BD6 0 +OP4 E03BD7 0 +OP4 E03BD8 0 +OP4 E03BD9 0 +OP4 E03BDA 0 +OP4 E03BDB 0 +OP4 E03BDC 0 +OP4 E03BDD 0 +OP4 E03BDE 0 +OP4 E03BDF 0 +OP4 E03BE0 0 +OP4 E03BE1 0 +OP4 E03BE2 0 +OP4 E03BE3 0 +OP4 E03BE4 0 +OP4 E03BE5 0 +OP4 E03BE6 0 +OP4 E03BE7 0 +OP4 E03BE8 0 +OP4 E03BE9 0 +OP4 E03BEA 0 +OP4 E03BEB 0 +OP4 E03BEC 0 +OP4 E03BED 0 +OP4 E03BEE 0 +OP4 E03BEF 0 +OP4 E03BF0 0 +OP4 E03BF1 0 +OP4 E03BF2 0 +OP4 E03BF3 0 +OP4 E03BF4 0 +OP4 E03BF5 0 +OP4 E03BF6 0 +OP4 E03BF7 0 +OP4 E03BF8 0 +OP4 E03BF9 0 +OP4 E03BFA 0 +OP4 E03BFB 0 +OP4 E03BFC 0 +OP4 E03BFD 0 +OP4 E03BFE 0 +OP4 E03BFF 0 +OP4 E03C00 0 +OP4 E03C01 0 +OP4 E03C02 0 +OP4 E03C03 0 +OP4 E03C04 0 +OP4 E03C05 0 +OP4 E03C06 0 +OP4 E03C07 0 +OP4 E03C08 0 +OP4 E03C09 0 +OP4 E03C0A 0 +OP4 E03C0B 0 +OP4 E03C0C 0 +OP4 E03C0D 0 +OP4 E03C0E 0 +OP4 E03C0F 0 +OP4 E03C10 0 +OP4 E03C11 0 +OP4 E03C12 0 +OP4 E03C13 0 +OP4 E03C14 0 +OP4 E03C15 0 +OP4 E03C16 0 +OP4 E03C17 0 +OP4 E03C18 0 +OP4 E03C19 0 +OP4 E03C1A 0 +OP4 E03C1B 0 +OP4 E03C1C 0 +OP4 E03C1D 0 +OP4 E03C1E 0 +OP4 E03C1F 0 +OP4 E03C20 0 +OP4 E03C21 0 +OP4 E03C22 0 +OP4 E03C23 0 +OP4 E03C24 0 +OP4 E03C25 0 +OP4 E03C26 0 +OP4 E03C27 0 +OP4 E03C28 0 +OP4 E03C29 0 +OP4 E03C2A 0 +OP4 E03C2B 0 +OP4 E03C2C 0 +OP4 E03C2D 0 +OP4 E03C2E 0 +OP4 E03C2F 0 +OP4 E03C30 0 +OP4 E03C31 0 +OP4 E03C32 0 +OP4 E03C33 0 +OP4 E03C34 0 +OP4 E03C35 0 +OP4 E03C36 0 +OP4 E03C37 0 +OP4 E03C38 0 +OP4 E03C39 0 +OP4 E03C3A 0 +OP4 E03C3B 0 +OP4 E03C3C 0 +OP4 E03C3D 0 +OP4 E03C3E 0 +OP4 E03C3F 0 +OP4 E03C40 0 +OP4 E03C41 0 +OP4 E03C42 0 +OP4 E03C43 0 +OP4 E03C44 0 +OP4 E03C45 0 +OP4 E03C46 0 +OP4 E03C47 0 +OP4 E03C48 0 +OP4 E03C49 0 +OP4 E03C4A 0 +OP4 E03C4B 0 +OP4 E03C4C 0 +OP4 E03C4D 0 +OP4 E03C4E 0 +OP4 E03C4F 0 +OP4 E03C50 0 +OP4 E03C51 0 +OP4 E03C52 0 +OP4 E03C53 0 +OP4 E03C54 0 +OP4 E03C55 0 +OP4 E03C56 0 +OP4 E03C57 0 +OP4 E03C58 0 +OP4 E03C59 0 +OP4 E03C5A 0 +OP4 E03C5B 0 +OP4 E03C5C 0 +OP4 E03C5D 0 +OP4 E03C5E 0 +OP4 E03C5F 0 +OP4 E03C60 0 +OP4 E03C61 0 +OP4 E03C62 0 +OP4 E03C63 0 +OP4 E03C64 0 +OP4 E03C65 0 +OP4 E03C66 0 +OP4 E03C67 0 +OP4 E03C68 0 +OP4 E03C69 0 +OP4 E03C6A 0 +OP4 E03C6B 0 +OP4 E03C6C 0 +OP4 E03C6D 0 +OP4 E03C6E 0 +OP4 E03C6F 0 +OP4 E03C70 0 +OP4 E03C71 0 +OP4 E03C72 0 +OP4 E03C73 0 +OP4 E03C74 0 +OP4 E03C75 0 +OP4 E03C76 0 +OP4 E03C77 0 +OP4 E03C78 0 +OP4 E03C79 0 +OP4 E03C7A 0 +OP4 E03C7B 0 +OP4 E03C7C 0 +OP4 E03C7D 0 +OP4 E03C7E 0 +OP4 E03C7F 0 +OP4 E03C80 0 +OP4 E03C81 0 +OP4 E03C82 0 +OP4 E03C83 0 +OP4 E03C84 0 +OP4 E03C85 0 +OP4 E03C86 0 +OP4 E03C87 0 +OP4 E03C88 0 +OP4 E03C89 0 +OP4 E03C8A 0 +OP4 E03C8B 0 +OP4 E03C8C 0 +OP4 E03C8D 0 +OP4 E03C8E 0 +OP4 E03C8F 0 +OP4 E03C90 0 +OP4 E03C91 0 +OP4 E03C92 0 +OP4 E03C93 0 +OP4 E03C94 0 +OP4 E03C95 0 +OP4 E03C96 0 +OP4 E03C97 0 +OP4 E03C98 0 +OP4 E03C99 0 +OP4 E03C9A 0 +OP4 E03C9B 0 +OP4 E03C9C 0 +OP4 E03C9D 0 +OP4 E03C9E 0 +OP4 E03C9F 0 +OP4 E03CA0 0 +OP4 E03CA1 0 +OP4 E03CA2 0 +OP4 E03CA3 0 +OP4 E03CA4 0 +OP4 E03CA5 0 +OP4 E03CA6 0 +OP4 E03CA7 0 +OP4 E03CA8 0 +OP4 E03CA9 0 +OP4 E03CAA 0 +OP4 E03CAB 0 +OP4 E03CAC 0 +OP4 E03CAD 0 +OP4 E03CAE 0 +OP4 E03CAF 0 +OP4 E03CB0 0 +OP4 E03CB1 0 +OP4 E03CB2 0 +OP4 E03CB3 0 +OP4 E03CB4 0 +OP4 E03CB5 0 +OP4 E03CB6 0 +OP4 E03CB7 0 +OP4 E03CB8 0 +OP4 E03CB9 0 +OP4 E03CBA 0 +OP4 E03CBB 0 +OP4 E03CBC 0 +OP4 E03CBD 0 +OP4 E03CBE 0 +OP4 E03CBF 0 +OP4 E03CC0 0 +OP4 E03CC1 0 +OP4 E03CC2 0 +OP4 E03CC3 0 +OP4 E03CC4 0 +OP4 E03CC5 0 +OP4 E03CC6 0 +OP4 E03CC7 0 +OP4 E03CC8 0 +OP4 E03CC9 0 +OP4 E03CCA 0 +OP4 E03CCB 0 +OP4 E03CCC 0 +OP4 E03CCD 0 +OP4 E03CCE 0 +OP4 E03CCF 0 +OP4 E03CD0 0 +OP4 E03CD1 0 +OP4 E03CD2 0 +OP4 E03CD3 0 +OP4 E03CD4 0 +OP4 E03CD5 0 +OP4 E03CD6 0 +OP4 E03CD7 0 +OP4 E03CD8 0 +OP4 E03CD9 0 +OP4 E03CDA 0 +OP4 E03CDB 0 +OP4 E03CDC 0 +OP4 E03CDD 0 +OP4 E03CDE 0 +OP4 E03CDF 0 +OP4 E03CE0 0 +OP4 E03CE1 0 +OP4 E03CE2 0 +OP4 E03CE3 0 +OP4 E03CE4 0 +OP4 E03CE5 0 +OP4 E03CE6 0 +OP4 E03CE7 0 +OP4 E03CE8 0 +OP4 E03CE9 0 +OP4 E03CEA 0 +OP4 E03CEB 0 +OP4 E03CEC 0 +OP4 E03CED 0 +OP4 E03CEE 0 +OP4 E03CEF 0 +OP4 E03CF0 0 +OP4 E03CF1 0 +OP4 E03CF2 0 +OP4 E03CF3 0 +OP4 E03CF4 0 +OP4 E03CF5 0 +OP4 E03CF6 0 +OP4 E03CF7 0 +OP4 E03CF8 0 +OP4 E03CF9 0 +OP4 E03CFA 0 +OP4 E03CFB 0 +OP4 E03CFC 0 +OP4 E03CFD 0 +OP4 E03CFE 0 +OP4 E03CFF 0 +OP4 E03D00 0 +OP4 E03D01 0 +OP4 E03D02 0 +OP4 E03D03 0 +OP4 E03D04 0 +OP4 E03D05 0 +OP4 E03D06 0 +OP4 E03D07 0 +OP4 E03D08 0 +OP4 E03D09 0 +OP4 E03D0A 0 +OP4 E03D0B 0 +OP4 E03D0C 0 +OP4 E03D0D 0 +OP4 E03D0E 0 +OP4 E03D0F 0 +OP4 E03D10 0 +OP4 E03D11 0 +OP4 E03D12 0 +OP4 E03D13 0 +OP4 E03D14 0 +OP4 E03D15 0 +OP4 E03D16 0 +OP4 E03D17 0 +OP4 E03D18 0 +OP4 E03D19 0 +OP4 E03D1A 0 +OP4 E03D1B 0 +OP4 E03D1C 0 +OP4 E03D1D 0 +OP4 E03D1E 0 +OP4 E03D1F 0 +OP4 E03D20 0 +OP4 E03D21 0 +OP4 E03D22 0 +OP4 E03D23 0 +OP4 E03D24 0 +OP4 E03D25 0 +OP4 E03D26 0 +OP4 E03D27 0 +OP4 E03D28 0 +OP4 E03D29 0 +OP4 E03D2A 0 +OP4 E03D2B 0 +OP4 E03D2C 0 +OP4 E03D2D 0 +OP4 E03D2E 0 +OP4 E03D2F 0 +OP4 E03D30 0 +OP4 E03D31 0 +OP4 E03D32 0 +OP4 E03D33 0 +OP4 E03D34 0 +OP4 E03D35 0 +OP4 E03D36 0 +OP4 E03D37 0 +OP4 E03D38 0 +OP4 E03D39 0 +OP4 E03D3A 0 +OP4 E03D3B 0 +OP4 E03D3C 0 +OP4 E03D3D 0 +OP4 E03D3E 0 +OP4 E03D3F 0 +OP4 E03D40 0 +OP4 E03D41 0 +OP4 E03D42 0 +OP4 E03D43 0 +OP4 E03D44 0 +OP4 E03D45 0 +OP4 E03D46 0 +OP4 E03D47 0 +OP4 E03D48 0 +OP4 E03D49 0 +OP4 E03D4A 0 +OP4 E03D4B 0 +OP4 E03D4C 0 +OP4 E03D4D 0 +OP4 E03D4E 0 +OP4 E03D4F 0 +OP4 E03D50 0 +OP4 E03D51 0 +OP4 E03D52 0 +OP4 E03D53 0 +OP4 E03D54 0 +OP4 E03D55 0 +OP4 E03D56 0 +OP4 E03D57 0 +OP4 E03D58 0 +OP4 E03D59 0 +OP4 E03D5A 0 +OP4 E03D5B 0 +OP4 E03D5C 0 +OP4 E03D5D 0 +OP4 E03D5E 0 +OP4 E03D5F 0 +OP4 E03D60 0 +OP4 E03D61 0 +OP4 E03D62 0 +OP4 E03D63 0 +OP4 E03D64 0 +OP4 E03D65 0 +OP4 E03D66 0 +OP4 E03D67 0 +OP4 E03D68 0 +OP4 E03D69 0 +OP4 E03D6A 0 +OP4 E03D6B 0 +OP4 E03D6C 0 +OP4 E03D6D 0 +OP4 E03D6E 0 +OP4 E03D6F 0 +OP4 E03D70 0 +OP4 E03D71 0 +OP4 E03D72 0 +OP4 E03D73 0 +OP4 E03D74 0 +OP4 E03D75 0 +OP4 E03D76 0 +OP4 E03D77 0 +OP4 E03D78 0 +OP4 E03D79 0 +OP4 E03D7A 0 +OP4 E03D7B 0 +OP4 E03D7C 0 +OP4 E03D7D 0 +OP4 E03D7E 0 +OP4 E03D7F 0 +OP4 E03D80 0 +OP4 E03D81 0 +OP4 E03D82 0 +OP4 E03D83 0 +OP4 E03D84 0 +OP4 E03D85 0 +OP4 E03D86 0 +OP4 E03D87 0 +OP4 E03D88 0 +OP4 E03D89 0 +OP4 E03D8A 0 +OP4 E03D8B 0 +OP4 E03D8C 0 +OP4 E03D8D 0 +OP4 E03D8E 0 +OP4 E03D8F 0 +OP4 E03D90 0 +OP4 E03D91 0 +OP4 E03D92 0 +OP4 E03D93 0 +OP4 E03D94 0 +OP4 E03D95 0 +OP4 E03D96 0 +OP4 E03D97 0 +OP4 E03D98 0 +OP4 E03D99 0 +OP4 E03D9A 0 +OP4 E03D9B 0 +OP4 E03D9C 0 +OP4 E03D9D 0 +OP4 E03D9E 0 +OP4 E03D9F 0 +OP4 E03DA0 0 +OP4 E03DA1 0 +OP4 E03DA2 0 +OP4 E03DA3 0 +OP4 E03DA4 0 +OP4 E03DA5 0 +OP4 E03DA6 0 +OP4 E03DA7 0 +OP4 E03DA8 0 +OP4 E03DA9 0 +OP4 E03DAA 0 +OP4 E03DAB 0 +OP4 E03DAC 0 +OP4 E03DAD 0 +OP4 E03DAE 0 +OP4 E03DAF 0 +OP4 E03DB0 0 +OP4 E03DB1 0 +OP4 E03DB2 0 +OP4 E03DB3 0 +OP4 E03DB4 0 +OP4 E03DB5 0 +OP4 E03DB6 0 +OP4 E03DB7 0 +OP4 E03DB8 0 +OP4 E03DB9 0 +OP4 E03DBA 0 +OP4 E03DBB 0 +OP4 E03DBC 0 +OP4 E03DBD 0 +OP4 E03DBE 0 +OP4 E03DBF 0 +OP4 E03DC0 0 +OP4 E03DC1 0 +OP4 E03DC2 0 +OP4 E03DC3 0 +OP4 E03DC4 0 diff --git a/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum4_itrace_irisc6.cfg.ext b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum4_itrace_irisc6.cfg.ext new file mode 100644 index 000000000000..5c1cfe1e8b9b --- /dev/null +++ b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum4_itrace_irisc6.cfg.ext @@ -0,0 +1,15814 @@ +OP1 Spectrum4 +OP4 ITRACE0 0 +OP4 ITRACE1 0 +OP4 ITRACE2 0 +OP4 ITRACE3 0 +OP4 ITRACE4 0 +OP4 ITRACE5 0 +OP4 ITRACE6 1 +OP4 ITRACE7 0 +OP4 ITRACE8 0 +OP4 ITRACE9 0 +OP4 Main_PhyUC 0 +OP4 TILE0_ITRACE0 0 +OP4 TILE0_ITRACE1 0 +OP4 TILE0_ITRACE2 0 +OP4 TILE0_ITRACE3 0 +OP4 TILE0_ITRACE4 0 +OP4 TILE0_PhyUC 0 +OP4 TILE1_ITRACE0 0 +OP4 TILE1_ITRACE1 0 +OP4 TILE1_ITRACE2 0 +OP4 TILE1_ITRACE3 0 +OP4 TILE1_ITRACE4 0 +OP4 TILE1_PhyUC 0 +OP4 TILE2_ITRACE0 0 +OP4 TILE2_ITRACE1 0 +OP4 TILE2_ITRACE2 0 +OP4 TILE2_ITRACE3 0 +OP4 TILE2_ITRACE4 0 +OP4 TILE2_PhyUC 0 +OP4 TILE3_ITRACE0 0 +OP4 TILE3_ITRACE1 0 +OP4 TILE3_ITRACE2 0 +OP4 TILE3_ITRACE3 0 +OP4 TILE3_ITRACE4 0 +OP4 TILE3_PhyUC 0 +OP4 TILE4_ITRACE0 0 +OP4 TILE4_ITRACE1 0 +OP4 TILE4_ITRACE2 0 +OP4 TILE4_ITRACE3 0 +OP4 TILE4_ITRACE4 0 +OP4 TILE4_PhyUC 0 +OP4 TILE5_ITRACE0 0 +OP4 TILE5_ITRACE1 0 +OP4 TILE5_ITRACE2 0 +OP4 TILE5_ITRACE3 0 +OP4 TILE5_ITRACE4 0 +OP4 TILE5_PhyUC 0 +OP4 TILE6_ITRACE0 0 +OP4 TILE6_ITRACE1 0 +OP4 TILE6_ITRACE2 0 +OP4 TILE6_ITRACE3 0 +OP4 TILE6_ITRACE4 0 +OP4 TILE6_PhyUC 0 +OP4 TILE7_ITRACE0 0 +OP4 TILE7_ITRACE1 0 +OP4 TILE7_ITRACE2 0 +OP4 TILE7_ITRACE3 0 +OP4 TILE7_ITRACE4 0 +OP4 TILE7_PhyUC 0 +OP4 E0003B 0 +OP4 E0003C 0 +OP4 E0003D 0 +OP4 E0003E 0 +OP4 E0003F 0 +OP4 E00040 0 +OP4 E00041 0 +OP4 E00042 0 +OP4 E00043 0 +OP4 E00044 0 +OP4 E00045 0 +OP4 E00046 0 +OP4 E00047 0 +OP4 E00048 0 +OP4 E00049 0 +OP4 E0004A 0 +OP4 E0004B 0 +OP4 E0004C 0 +OP4 E0004D 0 +OP4 E0004E 0 +OP4 E0004F 0 +OP4 E00050 0 +OP4 E00051 0 +OP4 E00052 0 +OP4 E00053 0 +OP4 E00054 0 +OP4 E00055 0 +OP4 E00056 0 +OP4 E00057 0 +OP4 E00058 0 +OP4 E00059 0 +OP4 E0005A 0 +OP4 E0005B 0 +OP4 E0005C 0 +OP4 E0005D 0 +OP4 E0005E 0 +OP4 E0005F 0 +OP4 E00060 0 +OP4 E00061 0 +OP4 E00062 0 +OP4 E00063 0 +OP4 E00064 0 +OP4 E00065 0 +OP4 E00066 0 +OP4 E00067 0 +OP4 E00068 0 +OP4 E00069 0 +OP4 E0006A 0 +OP4 E0006B 0 +OP4 E0006C 0 +OP4 E0006D 0 +OP4 E0006E 0 +OP4 E0006F 0 +OP4 E00070 0 +OP4 E00071 0 +OP4 E00072 0 +OP4 E00073 0 +OP4 E00074 0 +OP4 E00075 0 +OP4 E00076 0 +OP4 E00077 0 +OP4 E00078 0 +OP4 E00079 0 +OP4 E0007A 0 +OP4 E0007B 0 +OP4 E0007C 0 +OP4 E0007D 0 +OP4 E0007E 0 +OP4 E0007F 0 +OP4 E00080 0 +OP4 E00081 0 +OP4 E00082 0 +OP4 E00083 0 +OP4 E00084 0 +OP4 E00085 0 +OP4 E00086 0 +OP4 E00087 0 +OP4 E00088 0 +OP4 E00089 0 +OP4 E0008A 0 +OP4 E0008B 0 +OP4 E0008C 0 +OP4 E0008D 0 +OP4 E0008E 0 +OP4 E0008F 0 +OP4 E00090 0 +OP4 E00091 0 +OP4 E00092 0 +OP4 E00093 0 +OP4 E00094 0 +OP4 E00095 0 +OP4 E00096 0 +OP4 E00097 0 +OP4 E00098 0 +OP4 E00099 0 +OP4 E0009A 0 +OP4 E0009B 0 +OP4 E0009C 0 +OP4 E0009D 0 +OP4 E0009E 0 +OP4 E0009F 0 +OP4 E000A0 0 +OP4 E000A1 0 +OP4 E000A2 0 +OP4 E000A3 0 +OP4 E000A4 0 +OP4 E000A5 0 +OP4 E000A6 0 +OP4 E000A7 0 +OP4 E000A8 0 +OP4 E000A9 0 +OP4 E000AA 0 +OP4 E000AB 0 +OP4 E000AC 0 +OP4 E000AD 0 +OP4 E000AE 0 +OP4 E000AF 0 +OP4 E000B0 0 +OP4 E000B1 0 +OP4 E000B2 0 +OP4 E000B3 0 +OP4 E000B4 0 +OP4 E000B5 0 +OP4 E000B6 0 +OP4 E000B7 0 +OP4 E000B8 0 +OP4 E000B9 0 +OP4 E000BA 0 +OP4 E000BB 0 +OP4 E000BC 0 +OP4 E000BD 0 +OP4 E000BE 0 +OP4 E000BF 0 +OP4 E000C0 0 +OP4 E000C1 0 +OP4 E000C2 0 +OP4 E000C3 0 +OP4 E000C4 0 +OP4 E000C5 0 +OP4 E000C6 0 +OP4 E000C7 0 +OP4 E000C8 0 +OP4 E000C9 0 +OP4 E000CA 0 +OP4 E000CB 0 +OP4 E000CC 0 +OP4 E000CD 0 +OP4 E000CE 0 +OP4 E000CF 0 +OP4 E000D0 0 +OP4 E000D1 0 +OP4 E000D2 0 +OP4 E000D3 0 +OP4 E000D4 0 +OP4 E000D5 0 +OP4 E000D6 0 +OP4 E000D7 0 +OP4 E000D8 0 +OP4 E000D9 0 +OP4 E000DA 0 +OP4 E000DB 0 +OP4 E000DC 0 +OP4 E000DD 0 +OP4 E000DE 0 +OP4 E000DF 0 +OP4 E000E0 0 +OP4 E000E1 0 +OP4 E000E2 0 +OP4 E000E3 0 +OP4 E000E4 0 +OP4 E000E5 0 +OP4 E000E6 0 +OP4 E000E7 0 +OP4 E000E8 0 +OP4 E000E9 0 +OP4 E000EA 0 +OP4 E000EB 0 +OP4 E000EC 0 +OP4 E000ED 0 +OP4 E000EE 0 +OP4 E000EF 0 +OP4 E000F0 0 +OP4 E000F1 0 +OP4 E000F2 0 +OP4 E000F3 0 +OP4 E000F4 0 +OP4 E000F5 0 +OP4 E000F6 0 +OP4 E000F7 0 +OP4 E000F8 0 +OP4 E000F9 0 +OP4 E000FA 0 +OP4 E000FB 0 +OP4 E000FC 0 +OP4 E000FD 0 +OP4 E000FE 0 +OP4 E000FF 0 +OP4 E00100 0 +OP4 E00101 0 +OP4 E00102 0 +OP4 E00103 0 +OP4 E00104 0 +OP4 E00105 0 +OP4 E00106 0 +OP4 E00107 0 +OP4 E00108 0 +OP4 E00109 0 +OP4 E0010A 0 +OP4 E0010B 0 +OP4 E0010C 0 +OP4 E0010D 0 +OP4 E0010E 0 +OP4 E0010F 0 +OP4 E00110 0 +OP4 E00111 0 +OP4 E00112 0 +OP4 E00113 0 +OP4 E00114 0 +OP4 E00115 0 +OP4 E00116 0 +OP4 E00117 0 +OP4 E00118 0 +OP4 E00119 0 +OP4 E0011A 0 +OP4 E0011B 0 +OP4 E0011C 0 +OP4 E0011D 0 +OP4 E0011E 0 +OP4 E0011F 0 +OP4 E00120 0 +OP4 E00121 0 +OP4 E00122 0 +OP4 E00123 0 +OP4 E00124 0 +OP4 E00125 0 +OP4 E00126 0 +OP4 E00127 0 +OP4 E00128 0 +OP4 E00129 0 +OP4 E0012A 0 +OP4 E0012B 0 +OP4 E0012C 0 +OP4 E0012D 0 +OP4 E0012E 0 +OP4 E0012F 0 +OP4 E00130 0 +OP4 E00131 0 +OP4 E00132 0 +OP4 E00133 0 +OP4 E00134 0 +OP4 E00135 0 +OP4 E00136 0 +OP4 E00137 0 +OP4 E00138 0 +OP4 E00139 0 +OP4 E0013A 0 +OP4 E0013B 0 +OP4 E0013C 0 +OP4 E0013D 0 +OP4 E0013E 0 +OP4 E0013F 0 +OP4 E00140 0 +OP4 E00141 0 +OP4 E00142 0 +OP4 E00143 0 +OP4 E00144 0 +OP4 E00145 0 +OP4 E00146 0 +OP4 E00147 0 +OP4 E00148 0 +OP4 E00149 0 +OP4 E0014A 0 +OP4 E0014B 0 +OP4 E0014C 0 +OP4 E0014D 0 +OP4 E0014E 0 +OP4 E0014F 0 +OP4 E00150 0 +OP4 E00151 0 +OP4 E00152 0 +OP4 E00153 0 +OP4 E00154 0 +OP4 E00155 0 +OP4 E00156 0 +OP4 E00157 0 +OP4 E00158 0 +OP4 E00159 0 +OP4 E0015A 0 +OP4 E0015B 0 +OP4 E0015C 0 +OP4 E0015D 0 +OP4 E0015E 0 +OP4 E0015F 0 +OP4 E00160 0 +OP4 E00161 0 +OP4 E00162 0 +OP4 E00163 0 +OP4 E00164 0 +OP4 E00165 0 +OP4 E00166 0 +OP4 E00167 0 +OP4 E00168 0 +OP4 E00169 0 +OP4 E0016A 0 +OP4 E0016B 0 +OP4 E0016C 0 +OP4 E0016D 0 +OP4 E0016E 0 +OP4 E0016F 0 +OP4 E00170 0 +OP4 E00171 0 +OP4 E00172 0 +OP4 E00173 0 +OP4 E00174 0 +OP4 E00175 0 +OP4 E00176 0 +OP4 E00177 0 +OP4 E00178 0 +OP4 E00179 0 +OP4 E0017A 0 +OP4 E0017B 0 +OP4 E0017C 0 +OP4 E0017D 0 +OP4 E0017E 0 +OP4 E0017F 0 +OP4 E00180 0 +OP4 E00181 0 +OP4 E00182 0 +OP4 E00183 0 +OP4 E00184 0 +OP4 E00185 0 +OP4 E00186 0 +OP4 E00187 0 +OP4 E00188 0 +OP4 E00189 0 +OP4 E0018A 0 +OP4 E0018B 0 +OP4 E0018C 0 +OP4 E0018D 0 +OP4 E0018E 0 +OP4 E0018F 0 +OP4 E00190 0 +OP4 E00191 0 +OP4 E00192 0 +OP4 E00193 0 +OP4 E00194 0 +OP4 E00195 0 +OP4 E00196 0 +OP4 E00197 0 +OP4 E00198 0 +OP4 E00199 0 +OP4 E0019A 0 +OP4 E0019B 0 +OP4 E0019C 0 +OP4 E0019D 0 +OP4 E0019E 0 +OP4 E0019F 0 +OP4 E001A0 0 +OP4 E001A1 0 +OP4 E001A2 0 +OP4 E001A3 0 +OP4 E001A4 0 +OP4 E001A5 0 +OP4 E001A6 0 +OP4 E001A7 0 +OP4 E001A8 0 +OP4 E001A9 0 +OP4 E001AA 0 +OP4 E001AB 0 +OP4 E001AC 0 +OP4 E001AD 0 +OP4 E001AE 0 +OP4 E001AF 0 +OP4 E001B0 0 +OP4 E001B1 0 +OP4 E001B2 0 +OP4 E001B3 0 +OP4 E001B4 0 +OP4 E001B5 0 +OP4 E001B6 0 +OP4 E001B7 0 +OP4 E001B8 0 +OP4 E001B9 0 +OP4 E001BA 0 +OP4 E001BB 0 +OP4 E001BC 0 +OP4 E001BD 0 +OP4 E001BE 0 +OP4 E001BF 0 +OP4 E001C0 0 +OP4 E001C1 0 +OP4 E001C2 0 +OP4 E001C3 0 +OP4 E001C4 0 +OP4 E001C5 0 +OP4 E001C6 0 +OP4 E001C7 0 +OP4 E001C8 0 +OP4 E001C9 0 +OP4 E001CA 0 +OP4 E001CB 0 +OP4 E001CC 0 +OP4 E001CD 0 +OP4 E001CE 0 +OP4 E001CF 0 +OP4 E001D0 0 +OP4 E001D1 0 +OP4 E001D2 0 +OP4 E001D3 0 +OP4 E001D4 0 +OP4 E001D5 0 +OP4 E001D6 0 +OP4 E001D7 0 +OP4 E001D8 0 +OP4 E001D9 0 +OP4 E001DA 0 +OP4 E001DB 0 +OP4 E001DC 0 +OP4 E001DD 0 +OP4 E001DE 0 +OP4 E001DF 0 +OP4 E001E0 0 +OP4 E001E1 0 +OP4 E001E2 0 +OP4 E001E3 0 +OP4 E001E4 0 +OP4 E001E5 0 +OP4 E001E6 0 +OP4 E001E7 0 +OP4 E001E8 0 +OP4 E001E9 0 +OP4 E001EA 0 +OP4 E001EB 0 +OP4 E001EC 0 +OP4 E001ED 0 +OP4 E001EE 0 +OP4 E001EF 0 +OP4 E001F0 0 +OP4 E001F1 0 +OP4 E001F2 0 +OP4 E001F3 0 +OP4 E001F4 0 +OP4 E001F5 0 +OP4 E001F6 0 +OP4 E001F7 0 +OP4 E001F8 0 +OP4 E001F9 0 +OP4 E001FA 0 +OP4 E001FB 0 +OP4 E001FC 0 +OP4 E001FD 0 +OP4 E001FE 0 +OP4 E001FF 0 +OP4 E00200 0 +OP4 E00201 0 +OP4 E00202 0 +OP4 E00203 0 +OP4 E00204 0 +OP4 E00205 0 +OP4 E00206 0 +OP4 E00207 0 +OP4 E00208 0 +OP4 E00209 0 +OP4 E0020A 0 +OP4 E0020B 0 +OP4 E0020C 0 +OP4 E0020D 0 +OP4 E0020E 0 +OP4 E0020F 0 +OP4 E00210 0 +OP4 E00211 0 +OP4 E00212 0 +OP4 E00213 0 +OP4 E00214 0 +OP4 E00215 0 +OP4 E00216 0 +OP4 E00217 0 +OP4 E00218 0 +OP4 E00219 0 +OP4 E0021A 0 +OP4 E0021B 0 +OP4 E0021C 0 +OP4 E0021D 0 +OP4 E0021E 0 +OP4 E0021F 0 +OP4 E00220 0 +OP4 E00221 0 +OP4 E00222 0 +OP4 E00223 0 +OP4 E00224 0 +OP4 E00225 0 +OP4 E00226 0 +OP4 E00227 0 +OP4 E00228 0 +OP4 E00229 0 +OP4 E0022A 0 +OP4 E0022B 0 +OP4 E0022C 0 +OP4 E0022D 0 +OP4 E0022E 0 +OP4 E0022F 0 +OP4 E00230 0 +OP4 E00231 0 +OP4 E00232 0 +OP4 E00233 0 +OP4 E00234 0 +OP4 E00235 0 +OP4 E00236 0 +OP4 E00237 0 +OP4 E00238 0 +OP4 E00239 0 +OP4 E0023A 0 +OP4 E0023B 0 +OP4 E0023C 0 +OP4 E0023D 0 +OP4 E0023E 0 +OP4 E0023F 0 +OP4 E00240 0 +OP4 E00241 0 +OP4 E00242 0 +OP4 E00243 0 +OP4 E00244 0 +OP4 E00245 0 +OP4 E00246 0 +OP4 E00247 0 +OP4 E00248 0 +OP4 E00249 0 +OP4 E0024A 0 +OP4 E0024B 0 +OP4 E0024C 0 +OP4 E0024D 0 +OP4 E0024E 0 +OP4 E0024F 0 +OP4 E00250 0 +OP4 E00251 0 +OP4 E00252 0 +OP4 E00253 0 +OP4 E00254 0 +OP4 E00255 0 +OP4 E00256 0 +OP4 E00257 0 +OP4 E00258 0 +OP4 E00259 0 +OP4 E0025A 0 +OP4 E0025B 0 +OP4 E0025C 0 +OP4 E0025D 0 +OP4 E0025E 0 +OP4 E0025F 0 +OP4 E00260 0 +OP4 E00261 0 +OP4 E00262 0 +OP4 E00263 0 +OP4 E00264 0 +OP4 E00265 0 +OP4 E00266 0 +OP4 E00267 0 +OP4 E00268 0 +OP4 E00269 0 +OP4 E0026A 0 +OP4 E0026B 0 +OP4 E0026C 0 +OP4 E0026D 0 +OP4 E0026E 0 +OP4 E0026F 0 +OP4 E00270 0 +OP4 E00271 0 +OP4 E00272 0 +OP4 E00273 0 +OP4 E00274 0 +OP4 E00275 0 +OP4 E00276 0 +OP4 E00277 0 +OP4 E00278 0 +OP4 E00279 0 +OP4 E0027A 0 +OP4 E0027B 0 +OP4 E0027C 0 +OP4 E0027D 0 +OP4 E0027E 0 +OP4 E0027F 0 +OP4 E00280 0 +OP4 E00281 0 +OP4 E00282 0 +OP4 E00283 0 +OP4 E00284 0 +OP4 E00285 0 +OP4 E00286 0 +OP4 E00287 0 +OP4 E00288 0 +OP4 E00289 0 +OP4 E0028A 0 +OP4 E0028B 0 +OP4 E0028C 0 +OP4 E0028D 0 +OP4 E0028E 0 +OP4 E0028F 0 +OP4 E00290 0 +OP4 E00291 0 +OP4 E00292 0 +OP4 E00293 0 +OP4 E00294 0 +OP4 E00295 0 +OP4 E00296 0 +OP4 E00297 0 +OP4 E00298 0 +OP4 E00299 0 +OP4 E0029A 0 +OP4 E0029B 0 +OP4 E0029C 0 +OP4 E0029D 0 +OP4 E0029E 0 +OP4 E0029F 0 +OP4 E002A0 0 +OP4 E002A1 0 +OP4 E002A2 0 +OP4 E002A3 0 +OP4 E002A4 0 +OP4 E002A5 0 +OP4 E002A6 0 +OP4 E002A7 0 +OP4 E002A8 0 +OP4 E002A9 0 +OP4 E002AA 0 +OP4 E002AB 0 +OP4 E002AC 0 +OP4 E002AD 0 +OP4 E002AE 0 +OP4 E002AF 0 +OP4 E002B0 0 +OP4 E002B1 0 +OP4 E002B2 0 +OP4 E002B3 0 +OP4 E002B4 0 +OP4 E002B5 0 +OP4 E002B6 0 +OP4 E002B7 0 +OP4 E002B8 0 +OP4 E002B9 0 +OP4 E002BA 0 +OP4 E002BB 0 +OP4 E002BC 0 +OP4 E002BD 0 +OP4 E002BE 0 +OP4 E002BF 0 +OP4 E002C0 0 +OP4 E002C1 0 +OP4 E002C2 0 +OP4 E002C3 0 +OP4 E002C4 0 +OP4 E002C5 0 +OP4 E002C6 0 +OP4 E002C7 0 +OP4 E002C8 0 +OP4 E002C9 0 +OP4 E002CA 0 +OP4 E002CB 0 +OP4 E002CC 0 +OP4 E002CD 0 +OP4 E002CE 0 +OP4 E002CF 0 +OP4 E002D0 0 +OP4 E002D1 0 +OP4 E002D2 0 +OP4 E002D3 0 +OP4 E002D4 0 +OP4 E002D5 0 +OP4 E002D6 0 +OP4 E002D7 0 +OP4 E002D8 0 +OP4 E002D9 0 +OP4 E002DA 0 +OP4 E002DB 0 +OP4 E002DC 0 +OP4 E002DD 0 +OP4 E002DE 0 +OP4 E002DF 0 +OP4 E002E0 0 +OP4 E002E1 0 +OP4 E002E2 0 +OP4 E002E3 0 +OP4 E002E4 0 +OP4 E002E5 0 +OP4 E002E6 0 +OP4 E002E7 0 +OP4 E002E8 0 +OP4 E002E9 0 +OP4 E002EA 0 +OP4 E002EB 0 +OP4 E002EC 0 +OP4 E002ED 0 +OP4 E002EE 0 +OP4 E002EF 0 +OP4 E002F0 0 +OP4 E002F1 0 +OP4 E002F2 0 +OP4 E002F3 0 +OP4 E002F4 0 +OP4 E002F5 0 +OP4 E002F6 0 +OP4 E002F7 0 +OP4 E002F8 0 +OP4 E002F9 0 +OP4 E002FA 0 +OP4 E002FB 0 +OP4 E002FC 0 +OP4 E002FD 0 +OP4 E002FE 0 +OP4 E002FF 0 +OP4 E00300 0 +OP4 E00301 0 +OP4 E00302 0 +OP4 E00303 0 +OP4 E00304 0 +OP4 E00305 0 +OP4 E00306 0 +OP4 E00307 0 +OP4 E00308 0 +OP4 E00309 0 +OP4 E0030A 0 +OP4 E0030B 0 +OP4 E0030C 0 +OP4 E0030D 0 +OP4 E0030E 0 +OP4 E0030F 0 +OP4 E00310 0 +OP4 E00311 0 +OP4 E00312 0 +OP4 E00313 0 +OP4 E00314 0 +OP4 E00315 0 +OP4 E00316 0 +OP4 E00317 0 +OP4 E00318 0 +OP4 E00319 0 +OP4 E0031A 0 +OP4 E0031B 0 +OP4 E0031C 0 +OP4 E0031D 0 +OP4 E0031E 0 +OP4 E0031F 0 +OP4 E00320 0 +OP4 E00321 0 +OP4 E00322 0 +OP4 E00323 0 +OP4 E00324 0 +OP4 E00325 0 +OP4 E00326 0 +OP4 E00327 0 +OP4 E00328 0 +OP4 E00329 0 +OP4 E0032A 0 +OP4 E0032B 0 +OP4 E0032C 0 +OP4 E0032D 0 +OP4 E0032E 0 +OP4 E0032F 0 +OP4 E00330 0 +OP4 E00331 0 +OP4 E00332 0 +OP4 E00333 0 +OP4 E00334 0 +OP4 E00335 0 +OP4 E00336 0 +OP4 E00337 0 +OP4 E00338 0 +OP4 E00339 0 +OP4 E0033A 0 +OP4 E0033B 0 +OP4 E0033C 0 +OP4 E0033D 0 +OP4 E0033E 0 +OP4 E0033F 0 +OP4 E00340 0 +OP4 E00341 0 +OP4 E00342 0 +OP4 E00343 0 +OP4 E00344 0 +OP4 E00345 0 +OP4 E00346 0 +OP4 E00347 0 +OP4 E00348 0 +OP4 E00349 0 +OP4 E0034A 0 +OP4 E0034B 0 +OP4 E0034C 0 +OP4 E0034D 0 +OP4 E0034E 0 +OP4 E0034F 0 +OP4 E00350 0 +OP4 E00351 0 +OP4 E00352 0 +OP4 E00353 0 +OP4 E00354 0 +OP4 E00355 0 +OP4 E00356 0 +OP4 E00357 0 +OP4 E00358 0 +OP4 E00359 0 +OP4 E0035A 0 +OP4 E0035B 0 +OP4 E0035C 0 +OP4 E0035D 0 +OP4 E0035E 0 +OP4 E0035F 0 +OP4 E00360 0 +OP4 E00361 0 +OP4 E00362 0 +OP4 E00363 0 +OP4 E00364 0 +OP4 E00365 0 +OP4 E00366 0 +OP4 E00367 0 +OP4 E00368 0 +OP4 E00369 0 +OP4 E0036A 0 +OP4 E0036B 0 +OP4 E0036C 0 +OP4 E0036D 0 +OP4 E0036E 0 +OP4 E0036F 0 +OP4 E00370 0 +OP4 E00371 0 +OP4 E00372 0 +OP4 E00373 0 +OP4 E00374 0 +OP4 E00375 0 +OP4 E00376 0 +OP4 E00377 0 +OP4 E00378 0 +OP4 E00379 0 +OP4 E0037A 0 +OP4 E0037B 0 +OP4 E0037C 0 +OP4 E0037D 0 +OP4 E0037E 0 +OP4 E0037F 0 +OP4 E00380 0 +OP4 E00381 0 +OP4 E00382 0 +OP4 E00383 0 +OP4 E00384 0 +OP4 E00385 0 +OP4 E00386 0 +OP4 E00387 0 +OP4 E00388 0 +OP4 E00389 0 +OP4 E0038A 0 +OP4 E0038B 0 +OP4 E0038C 0 +OP4 E0038D 0 +OP4 E0038E 0 +OP4 E0038F 0 +OP4 E00390 0 +OP4 E00391 0 +OP4 E00392 0 +OP4 E00393 0 +OP4 E00394 0 +OP4 E00395 0 +OP4 E00396 0 +OP4 E00397 0 +OP4 E00398 0 +OP4 E00399 0 +OP4 E0039A 0 +OP4 E0039B 0 +OP4 E0039C 0 +OP4 E0039D 0 +OP4 E0039E 0 +OP4 E0039F 0 +OP4 E003A0 0 +OP4 E003A1 0 +OP4 E003A2 0 +OP4 E003A3 0 +OP4 E003A4 0 +OP4 E003A5 0 +OP4 E003A6 0 +OP4 E003A7 0 +OP4 E003A8 0 +OP4 E003A9 0 +OP4 E003AA 0 +OP4 E003AB 0 +OP4 E003AC 0 +OP4 E003AD 0 +OP4 E003AE 0 +OP4 E003AF 0 +OP4 E003B0 0 +OP4 E003B1 0 +OP4 E003B2 0 +OP4 E003B3 0 +OP4 E003B4 0 +OP4 E003B5 0 +OP4 E003B6 0 +OP4 E003B7 0 +OP4 E003B8 0 +OP4 E003B9 0 +OP4 E003BA 0 +OP4 E003BB 0 +OP4 E003BC 0 +OP4 E003BD 0 +OP4 E003BE 0 +OP4 E003BF 0 +OP4 E003C0 0 +OP4 E003C1 0 +OP4 E003C2 0 +OP4 E003C3 0 +OP4 E003C4 0 +OP4 E003C5 0 +OP4 E003C6 0 +OP4 E003C7 0 +OP4 E003C8 0 +OP4 E003C9 0 +OP4 E003CA 0 +OP4 E003CB 0 +OP4 E003CC 0 +OP4 E003CD 0 +OP4 E003CE 0 +OP4 E003CF 0 +OP4 E003D0 0 +OP4 E003D1 0 +OP4 E003D2 0 +OP4 E003D3 0 +OP4 E003D4 0 +OP4 E003D5 0 +OP4 E003D6 0 +OP4 E003D7 0 +OP4 E003D8 0 +OP4 E003D9 0 +OP4 E003DA 0 +OP4 E003DB 0 +OP4 E003DC 0 +OP4 E003DD 0 +OP4 E003DE 0 +OP4 E003DF 0 +OP4 E003E0 0 +OP4 E003E1 0 +OP4 E003E2 0 +OP4 E003E3 0 +OP4 E003E4 0 +OP4 E003E5 0 +OP4 E003E6 0 +OP4 E003E7 0 +OP4 E003E8 0 +OP4 E003E9 0 +OP4 E003EA 0 +OP4 E003EB 0 +OP4 E003EC 0 +OP4 E003ED 0 +OP4 E003EE 0 +OP4 E003EF 0 +OP4 E003F0 0 +OP4 E003F1 0 +OP4 E003F2 0 +OP4 E003F3 0 +OP4 E003F4 0 +OP4 E003F5 0 +OP4 E003F6 0 +OP4 E003F7 0 +OP4 E003F8 0 +OP4 E003F9 0 +OP4 E003FA 0 +OP4 E003FB 0 +OP4 E003FC 0 +OP4 E003FD 0 +OP4 E003FE 0 +OP4 E003FF 0 +OP4 E00400 0 +OP4 E00401 0 +OP4 E00402 0 +OP4 E00403 0 +OP4 E00404 0 +OP4 E00405 0 +OP4 E00406 0 +OP4 E00407 0 +OP4 E00408 0 +OP4 E00409 0 +OP4 E0040A 0 +OP4 E0040B 0 +OP4 E0040C 0 +OP4 E0040D 0 +OP4 E0040E 0 +OP4 E0040F 0 +OP4 E00410 0 +OP4 E00411 0 +OP4 E00412 0 +OP4 E00413 0 +OP4 E00414 0 +OP4 E00415 0 +OP4 E00416 0 +OP4 E00417 0 +OP4 E00418 0 +OP4 E00419 0 +OP4 E0041A 0 +OP4 E0041B 0 +OP4 E0041C 0 +OP4 E0041D 0 +OP4 E0041E 0 +OP4 E0041F 0 +OP4 E00420 0 +OP4 E00421 0 +OP4 E00422 0 +OP4 E00423 0 +OP4 E00424 0 +OP4 E00425 0 +OP4 E00426 0 +OP4 E00427 0 +OP4 E00428 0 +OP4 E00429 0 +OP4 E0042A 0 +OP4 E0042B 0 +OP4 E0042C 0 +OP4 E0042D 0 +OP4 E0042E 0 +OP4 E0042F 0 +OP4 E00430 0 +OP4 E00431 0 +OP4 E00432 0 +OP4 E00433 0 +OP4 E00434 0 +OP4 E00435 0 +OP4 E00436 0 +OP4 E00437 0 +OP4 E00438 0 +OP4 E00439 0 +OP4 E0043A 0 +OP4 E0043B 0 +OP4 E0043C 0 +OP4 E0043D 0 +OP4 E0043E 0 +OP4 E0043F 0 +OP4 E00440 0 +OP4 E00441 0 +OP4 E00442 0 +OP4 E00443 0 +OP4 E00444 0 +OP4 E00445 0 +OP4 E00446 0 +OP4 E00447 0 +OP4 E00448 0 +OP4 E00449 0 +OP4 E0044A 0 +OP4 E0044B 0 +OP4 E0044C 0 +OP4 E0044D 0 +OP4 E0044E 0 +OP4 E0044F 0 +OP4 E00450 0 +OP4 E00451 0 +OP4 E00452 0 +OP4 E00453 0 +OP4 E00454 0 +OP4 E00455 0 +OP4 E00456 0 +OP4 E00457 0 +OP4 E00458 0 +OP4 E00459 0 +OP4 E0045A 0 +OP4 E0045B 0 +OP4 E0045C 0 +OP4 E0045D 0 +OP4 E0045E 0 +OP4 E0045F 0 +OP4 E00460 0 +OP4 E00461 0 +OP4 E00462 0 +OP4 E00463 0 +OP4 E00464 0 +OP4 E00465 0 +OP4 E00466 0 +OP4 E00467 0 +OP4 E00468 0 +OP4 E00469 0 +OP4 E0046A 0 +OP4 E0046B 0 +OP4 E0046C 0 +OP4 E0046D 0 +OP4 E0046E 0 +OP4 E0046F 0 +OP4 E00470 0 +OP4 E00471 0 +OP4 E00472 0 +OP4 E00473 0 +OP4 E00474 0 +OP4 E00475 0 +OP4 E00476 0 +OP4 E00477 0 +OP4 E00478 0 +OP4 E00479 0 +OP4 E0047A 0 +OP4 E0047B 0 +OP4 E0047C 0 +OP4 E0047D 0 +OP4 E0047E 0 +OP4 E0047F 0 +OP4 E00480 0 +OP4 E00481 0 +OP4 E00482 0 +OP4 E00483 0 +OP4 E00484 0 +OP4 E00485 0 +OP4 E00486 0 +OP4 E00487 0 +OP4 E00488 0 +OP4 E00489 0 +OP4 E0048A 0 +OP4 E0048B 0 +OP4 E0048C 0 +OP4 E0048D 0 +OP4 E0048E 0 +OP4 E0048F 0 +OP4 E00490 0 +OP4 E00491 0 +OP4 E00492 0 +OP4 E00493 0 +OP4 E00494 0 +OP4 E00495 0 +OP4 E00496 0 +OP4 E00497 0 +OP4 E00498 0 +OP4 E00499 0 +OP4 E0049A 0 +OP4 E0049B 0 +OP4 E0049C 0 +OP4 E0049D 0 +OP4 E0049E 0 +OP4 E0049F 0 +OP4 E004A0 0 +OP4 E004A1 0 +OP4 E004A2 0 +OP4 E004A3 0 +OP4 E004A4 0 +OP4 E004A5 0 +OP4 E004A6 0 +OP4 E004A7 0 +OP4 E004A8 0 +OP4 E004A9 0 +OP4 E004AA 0 +OP4 E004AB 0 +OP4 E004AC 0 +OP4 E004AD 0 +OP4 E004AE 0 +OP4 E004AF 0 +OP4 E004B0 0 +OP4 E004B1 0 +OP4 E004B2 0 +OP4 E004B3 0 +OP4 E004B4 0 +OP4 E004B5 0 +OP4 E004B6 0 +OP4 E004B7 0 +OP4 E004B8 0 +OP4 E004B9 0 +OP4 E004BA 0 +OP4 E004BB 0 +OP4 E004BC 0 +OP4 E004BD 0 +OP4 E004BE 0 +OP4 E004BF 0 +OP4 E004C0 0 +OP4 E004C1 0 +OP4 E004C2 0 +OP4 E004C3 0 +OP4 E004C4 0 +OP4 E004C5 0 +OP4 E004C6 0 +OP4 E004C7 0 +OP4 E004C8 0 +OP4 E004C9 0 +OP4 E004CA 0 +OP4 E004CB 0 +OP4 E004CC 0 +OP4 E004CD 0 +OP4 E004CE 0 +OP4 E004CF 0 +OP4 E004D0 0 +OP4 E004D1 0 +OP4 E004D2 0 +OP4 E004D3 0 +OP4 E004D4 0 +OP4 E004D5 0 +OP4 E004D6 0 +OP4 E004D7 0 +OP4 E004D8 0 +OP4 E004D9 0 +OP4 E004DA 0 +OP4 E004DB 0 +OP4 E004DC 0 +OP4 E004DD 0 +OP4 E004DE 0 +OP4 E004DF 0 +OP4 E004E0 0 +OP4 E004E1 0 +OP4 E004E2 0 +OP4 E004E3 0 +OP4 E004E4 0 +OP4 E004E5 0 +OP4 E004E6 0 +OP4 E004E7 0 +OP4 E004E8 0 +OP4 E004E9 0 +OP4 E004EA 0 +OP4 E004EB 0 +OP4 E004EC 0 +OP4 E004ED 0 +OP4 E004EE 0 +OP4 E004EF 0 +OP4 E004F0 0 +OP4 E004F1 0 +OP4 E004F2 0 +OP4 E004F3 0 +OP4 E004F4 0 +OP4 E004F5 0 +OP4 E004F6 0 +OP4 E004F7 0 +OP4 E004F8 0 +OP4 E004F9 0 +OP4 E004FA 0 +OP4 E004FB 0 +OP4 E004FC 0 +OP4 E004FD 0 +OP4 E004FE 0 +OP4 E004FF 0 +OP4 E00500 0 +OP4 E00501 0 +OP4 E00502 0 +OP4 E00503 0 +OP4 E00504 0 +OP4 E00505 0 +OP4 E00506 0 +OP4 E00507 0 +OP4 E00508 0 +OP4 E00509 0 +OP4 E0050A 0 +OP4 E0050B 0 +OP4 E0050C 0 +OP4 E0050D 0 +OP4 E0050E 0 +OP4 E0050F 0 +OP4 E00510 0 +OP4 E00511 0 +OP4 E00512 0 +OP4 E00513 0 +OP4 E00514 0 +OP4 E00515 0 +OP4 E00516 0 +OP4 E00517 0 +OP4 E00518 0 +OP4 E00519 0 +OP4 E0051A 0 +OP4 E0051B 0 +OP4 E0051C 0 +OP4 E0051D 0 +OP4 E0051E 0 +OP4 E0051F 0 +OP4 E00520 0 +OP4 E00521 0 +OP4 E00522 0 +OP4 E00523 0 +OP4 E00524 0 +OP4 E00525 0 +OP4 E00526 0 +OP4 E00527 0 +OP4 E00528 0 +OP4 E00529 0 +OP4 E0052A 0 +OP4 E0052B 0 +OP4 E0052C 0 +OP4 E0052D 0 +OP4 E0052E 0 +OP4 E0052F 0 +OP4 E00530 0 +OP4 E00531 0 +OP4 E00532 0 +OP4 E00533 0 +OP4 E00534 0 +OP4 E00535 0 +OP4 E00536 0 +OP4 E00537 0 +OP4 E00538 0 +OP4 E00539 0 +OP4 E0053A 0 +OP4 E0053B 0 +OP4 E0053C 0 +OP4 E0053D 0 +OP4 E0053E 0 +OP4 E0053F 0 +OP4 E00540 0 +OP4 E00541 0 +OP4 E00542 0 +OP4 E00543 0 +OP4 E00544 0 +OP4 E00545 0 +OP4 E00546 0 +OP4 E00547 0 +OP4 E00548 0 +OP4 E00549 0 +OP4 E0054A 0 +OP4 E0054B 0 +OP4 E0054C 0 +OP4 E0054D 0 +OP4 E0054E 0 +OP4 E0054F 0 +OP4 E00550 0 +OP4 E00551 0 +OP4 E00552 0 +OP4 E00553 0 +OP4 E00554 0 +OP4 E00555 0 +OP4 E00556 0 +OP4 E00557 0 +OP4 E00558 0 +OP4 E00559 0 +OP4 E0055A 0 +OP4 E0055B 0 +OP4 E0055C 0 +OP4 E0055D 0 +OP4 E0055E 0 +OP4 E0055F 0 +OP4 E00560 0 +OP4 E00561 0 +OP4 E00562 0 +OP4 E00563 0 +OP4 E00564 0 +OP4 E00565 0 +OP4 E00566 0 +OP4 E00567 0 +OP4 E00568 0 +OP4 E00569 0 +OP4 E0056A 0 +OP4 E0056B 0 +OP4 E0056C 0 +OP4 E0056D 0 +OP4 E0056E 0 +OP4 E0056F 0 +OP4 E00570 0 +OP4 E00571 0 +OP4 E00572 0 +OP4 E00573 0 +OP4 E00574 0 +OP4 E00575 0 +OP4 E00576 0 +OP4 E00577 0 +OP4 E00578 0 +OP4 E00579 0 +OP4 E0057A 0 +OP4 E0057B 0 +OP4 E0057C 0 +OP4 E0057D 0 +OP4 E0057E 0 +OP4 E0057F 0 +OP4 E00580 0 +OP4 E00581 0 +OP4 E00582 0 +OP4 E00583 0 +OP4 E00584 0 +OP4 E00585 0 +OP4 E00586 0 +OP4 E00587 0 +OP4 E00588 0 +OP4 E00589 0 +OP4 E0058A 0 +OP4 E0058B 0 +OP4 E0058C 0 +OP4 E0058D 0 +OP4 E0058E 0 +OP4 E0058F 0 +OP4 E00590 0 +OP4 E00591 0 +OP4 E00592 0 +OP4 E00593 0 +OP4 E00594 0 +OP4 E00595 0 +OP4 E00596 0 +OP4 E00597 0 +OP4 E00598 0 +OP4 E00599 0 +OP4 E0059A 0 +OP4 E0059B 0 +OP4 E0059C 0 +OP4 E0059D 0 +OP4 E0059E 0 +OP4 E0059F 0 +OP4 E005A0 0 +OP4 E005A1 0 +OP4 E005A2 0 +OP4 E005A3 0 +OP4 E005A4 0 +OP4 E005A5 0 +OP4 E005A6 0 +OP4 E005A7 0 +OP4 E005A8 0 +OP4 E005A9 0 +OP4 E005AA 0 +OP4 E005AB 0 +OP4 E005AC 0 +OP4 E005AD 0 +OP4 E005AE 0 +OP4 E005AF 0 +OP4 E005B0 0 +OP4 E005B1 0 +OP4 E005B2 0 +OP4 E005B3 0 +OP4 E005B4 0 +OP4 E005B5 0 +OP4 E005B6 0 +OP4 E005B7 0 +OP4 E005B8 0 +OP4 E005B9 0 +OP4 E005BA 0 +OP4 E005BB 0 +OP4 E005BC 0 +OP4 E005BD 0 +OP4 E005BE 0 +OP4 E005BF 0 +OP4 E005C0 0 +OP4 E005C1 0 +OP4 E005C2 0 +OP4 E005C3 0 +OP4 E005C4 0 +OP4 E005C5 0 +OP4 E005C6 0 +OP4 E005C7 0 +OP4 E005C8 0 +OP4 E005C9 0 +OP4 E005CA 0 +OP4 E005CB 0 +OP4 E005CC 0 +OP4 E005CD 0 +OP4 E005CE 0 +OP4 E005CF 0 +OP4 E005D0 0 +OP4 E005D1 0 +OP4 E005D2 0 +OP4 E005D3 0 +OP4 E005D4 0 +OP4 E005D5 0 +OP4 E005D6 0 +OP4 E005D7 0 +OP4 E005D8 0 +OP4 E005D9 0 +OP4 E005DA 0 +OP4 E005DB 0 +OP4 E005DC 0 +OP4 E005DD 0 +OP4 E005DE 0 +OP4 E005DF 0 +OP4 E005E0 0 +OP4 E005E1 0 +OP4 E005E2 0 +OP4 E005E3 0 +OP4 E005E4 0 +OP4 E005E5 0 +OP4 E005E6 0 +OP4 E005E7 0 +OP4 E005E8 0 +OP4 E005E9 0 +OP4 E005EA 0 +OP4 E005EB 0 +OP4 E005EC 0 +OP4 E005ED 0 +OP4 E005EE 0 +OP4 E005EF 0 +OP4 E005F0 0 +OP4 E005F1 0 +OP4 E005F2 0 +OP4 E005F3 0 +OP4 E005F4 0 +OP4 E005F5 0 +OP4 E005F6 0 +OP4 E005F7 0 +OP4 E005F8 0 +OP4 E005F9 0 +OP4 E005FA 0 +OP4 E005FB 0 +OP4 E005FC 0 +OP4 E005FD 0 +OP4 E005FE 0 +OP4 E005FF 0 +OP4 E00600 0 +OP4 E00601 0 +OP4 E00602 0 +OP4 E00603 0 +OP4 E00604 0 +OP4 E00605 0 +OP4 E00606 0 +OP4 E00607 0 +OP4 E00608 0 +OP4 E00609 0 +OP4 E0060A 0 +OP4 E0060B 0 +OP4 E0060C 0 +OP4 E0060D 0 +OP4 E0060E 0 +OP4 E0060F 0 +OP4 E00610 0 +OP4 E00611 0 +OP4 E00612 0 +OP4 E00613 0 +OP4 E00614 0 +OP4 E00615 0 +OP4 E00616 0 +OP4 E00617 0 +OP4 E00618 0 +OP4 E00619 0 +OP4 E0061A 0 +OP4 E0061B 0 +OP4 E0061C 0 +OP4 E0061D 0 +OP4 E0061E 0 +OP4 E0061F 0 +OP4 E00620 0 +OP4 E00621 0 +OP4 E00622 0 +OP4 E00623 0 +OP4 E00624 0 +OP4 E00625 0 +OP4 E00626 0 +OP4 E00627 0 +OP4 E00628 0 +OP4 E00629 0 +OP4 E0062A 0 +OP4 E0062B 0 +OP4 E0062C 0 +OP4 E0062D 0 +OP4 E0062E 0 +OP4 E0062F 0 +OP4 E00630 0 +OP4 E00631 0 +OP4 E00632 0 +OP4 E00633 0 +OP4 E00634 0 +OP4 E00635 0 +OP4 E00636 0 +OP4 E00637 0 +OP4 E00638 0 +OP4 E00639 0 +OP4 E0063A 0 +OP4 E0063B 0 +OP4 E0063C 0 +OP4 E0063D 0 +OP4 E0063E 0 +OP4 E0063F 0 +OP4 E00640 0 +OP4 E00641 0 +OP4 E00642 0 +OP4 E00643 0 +OP4 E00644 0 +OP4 E00645 0 +OP4 E00646 0 +OP4 E00647 0 +OP4 E00648 0 +OP4 E00649 0 +OP4 E0064A 0 +OP4 E0064B 0 +OP4 E0064C 0 +OP4 E0064D 0 +OP4 E0064E 0 +OP4 E0064F 0 +OP4 E00650 0 +OP4 E00651 0 +OP4 E00652 0 +OP4 E00653 0 +OP4 E00654 0 +OP4 E00655 0 +OP4 E00656 0 +OP4 E00657 0 +OP4 E00658 0 +OP4 E00659 0 +OP4 E0065A 0 +OP4 E0065B 0 +OP4 E0065C 0 +OP4 E0065D 0 +OP4 E0065E 0 +OP4 E0065F 0 +OP4 E00660 0 +OP4 E00661 0 +OP4 E00662 0 +OP4 E00663 0 +OP4 E00664 0 +OP4 E00665 0 +OP4 E00666 0 +OP4 E00667 0 +OP4 E00668 0 +OP4 E00669 0 +OP4 E0066A 0 +OP4 E0066B 0 +OP4 E0066C 0 +OP4 E0066D 0 +OP4 E0066E 0 +OP4 E0066F 0 +OP4 E00670 0 +OP4 E00671 0 +OP4 E00672 0 +OP4 E00673 0 +OP4 E00674 0 +OP4 E00675 0 +OP4 E00676 0 +OP4 E00677 0 +OP4 E00678 0 +OP4 E00679 0 +OP4 E0067A 0 +OP4 E0067B 0 +OP4 E0067C 0 +OP4 E0067D 0 +OP4 E0067E 0 +OP4 E0067F 0 +OP4 E00680 0 +OP4 E00681 0 +OP4 E00682 0 +OP4 E00683 0 +OP4 E00684 0 +OP4 E00685 0 +OP4 E00686 0 +OP4 E00687 0 +OP4 E00688 0 +OP4 E00689 0 +OP4 E0068A 0 +OP4 E0068B 0 +OP4 E0068C 0 +OP4 E0068D 0 +OP4 E0068E 0 +OP4 E0068F 0 +OP4 E00690 0 +OP4 E00691 0 +OP4 E00692 0 +OP4 E00693 0 +OP4 E00694 0 +OP4 E00695 0 +OP4 E00696 0 +OP4 E00697 0 +OP4 E00698 0 +OP4 E00699 0 +OP4 E0069A 0 +OP4 E0069B 0 +OP4 E0069C 0 +OP4 E0069D 0 +OP4 E0069E 0 +OP4 E0069F 0 +OP4 E006A0 0 +OP4 E006A1 0 +OP4 E006A2 0 +OP4 E006A3 0 +OP4 E006A4 0 +OP4 E006A5 0 +OP4 E006A6 0 +OP4 E006A7 0 +OP4 E006A8 0 +OP4 E006A9 0 +OP4 E006AA 0 +OP4 E006AB 0 +OP4 E006AC 0 +OP4 E006AD 0 +OP4 E006AE 0 +OP4 E006AF 0 +OP4 E006B0 0 +OP4 E006B1 0 +OP4 E006B2 0 +OP4 E006B3 0 +OP4 E006B4 0 +OP4 E006B5 0 +OP4 E006B6 0 +OP4 E006B7 0 +OP4 E006B8 0 +OP4 E006B9 0 +OP4 E006BA 0 +OP4 E006BB 0 +OP4 E006BC 0 +OP4 E006BD 0 +OP4 E006BE 0 +OP4 E006BF 0 +OP4 E006C0 0 +OP4 E006C1 0 +OP4 E006C2 0 +OP4 E006C3 0 +OP4 E006C4 0 +OP4 E006C5 0 +OP4 E006C6 0 +OP4 E006C7 0 +OP4 E006C8 0 +OP4 E006C9 0 +OP4 E006CA 0 +OP4 E006CB 0 +OP4 E006CC 0 +OP4 E006CD 0 +OP4 E006CE 0 +OP4 E006CF 0 +OP4 E006D0 0 +OP4 E006D1 0 +OP4 E006D2 0 +OP4 E006D3 0 +OP4 E006D4 0 +OP4 E006D5 0 +OP4 E006D6 0 +OP4 E006D7 0 +OP4 E006D8 0 +OP4 E006D9 0 +OP4 E006DA 0 +OP4 E006DB 0 +OP4 E006DC 0 +OP4 E006DD 0 +OP4 E006DE 0 +OP4 E006DF 0 +OP4 E006E0 0 +OP4 E006E1 0 +OP4 E006E2 0 +OP4 E006E3 0 +OP4 E006E4 0 +OP4 E006E5 0 +OP4 E006E6 0 +OP4 E006E7 0 +OP4 E006E8 0 +OP4 E006E9 0 +OP4 E006EA 0 +OP4 E006EB 0 +OP4 E006EC 0 +OP4 E006ED 0 +OP4 E006EE 0 +OP4 E006EF 0 +OP4 E006F0 0 +OP4 E006F1 0 +OP4 E006F2 0 +OP4 E006F3 0 +OP4 E006F4 0 +OP4 E006F5 0 +OP4 E006F6 0 +OP4 E006F7 0 +OP4 E006F8 0 +OP4 E006F9 0 +OP4 E006FA 0 +OP4 E006FB 0 +OP4 E006FC 0 +OP4 E006FD 0 +OP4 E006FE 0 +OP4 E006FF 0 +OP4 E00700 0 +OP4 E00701 0 +OP4 E00702 0 +OP4 E00703 0 +OP4 E00704 0 +OP4 E00705 0 +OP4 E00706 0 +OP4 E00707 0 +OP4 E00708 0 +OP4 E00709 0 +OP4 E0070A 0 +OP4 E0070B 0 +OP4 E0070C 0 +OP4 E0070D 0 +OP4 E0070E 0 +OP4 E0070F 0 +OP4 E00710 0 +OP4 E00711 0 +OP4 E00712 0 +OP4 E00713 0 +OP4 E00714 0 +OP4 E00715 0 +OP4 E00716 0 +OP4 E00717 0 +OP4 E00718 0 +OP4 E00719 0 +OP4 E0071A 0 +OP4 E0071B 0 +OP4 E0071C 0 +OP4 E0071D 0 +OP4 E0071E 0 +OP4 E0071F 0 +OP4 E00720 0 +OP4 E00721 0 +OP4 E00722 0 +OP4 E00723 0 +OP4 E00724 0 +OP4 E00725 0 +OP4 E00726 0 +OP4 E00727 0 +OP4 E00728 0 +OP4 E00729 0 +OP4 E0072A 0 +OP4 E0072B 0 +OP4 E0072C 0 +OP4 E0072D 0 +OP4 E0072E 0 +OP4 E0072F 0 +OP4 E00730 0 +OP4 E00731 0 +OP4 E00732 0 +OP4 E00733 0 +OP4 E00734 0 +OP4 E00735 0 +OP4 E00736 0 +OP4 E00737 0 +OP4 E00738 0 +OP4 E00739 0 +OP4 E0073A 0 +OP4 E0073B 0 +OP4 E0073C 0 +OP4 E0073D 0 +OP4 E0073E 0 +OP4 E0073F 0 +OP4 E00740 0 +OP4 E00741 0 +OP4 E00742 0 +OP4 E00743 0 +OP4 E00744 0 +OP4 E00745 0 +OP4 E00746 0 +OP4 E00747 0 +OP4 E00748 0 +OP4 E00749 0 +OP4 E0074A 0 +OP4 E0074B 0 +OP4 E0074C 0 +OP4 E0074D 0 +OP4 E0074E 0 +OP4 E0074F 0 +OP4 E00750 0 +OP4 E00751 0 +OP4 E00752 0 +OP4 E00753 0 +OP4 E00754 0 +OP4 E00755 0 +OP4 E00756 0 +OP4 E00757 0 +OP4 E00758 0 +OP4 E00759 0 +OP4 E0075A 0 +OP4 E0075B 0 +OP4 E0075C 0 +OP4 E0075D 0 +OP4 E0075E 0 +OP4 E0075F 0 +OP4 E00760 0 +OP4 E00761 0 +OP4 E00762 0 +OP4 E00763 0 +OP4 E00764 0 +OP4 E00765 0 +OP4 E00766 0 +OP4 E00767 0 +OP4 E00768 0 +OP4 E00769 0 +OP4 E0076A 0 +OP4 E0076B 0 +OP4 E0076C 0 +OP4 E0076D 0 +OP4 E0076E 0 +OP4 E0076F 0 +OP4 E00770 0 +OP4 E00771 0 +OP4 E00772 0 +OP4 E00773 0 +OP4 E00774 0 +OP4 E00775 0 +OP4 E00776 0 +OP4 E00777 0 +OP4 E00778 0 +OP4 E00779 0 +OP4 E0077A 0 +OP4 E0077B 0 +OP4 E0077C 0 +OP4 E0077D 0 +OP4 E0077E 0 +OP4 E0077F 0 +OP4 E00780 0 +OP4 E00781 0 +OP4 E00782 0 +OP4 E00783 0 +OP4 E00784 0 +OP4 E00785 0 +OP4 E00786 0 +OP4 E00787 0 +OP4 E00788 0 +OP4 E00789 0 +OP4 E0078A 0 +OP4 E0078B 0 +OP4 E0078C 0 +OP4 E0078D 0 +OP4 E0078E 0 +OP4 E0078F 0 +OP4 E00790 0 +OP4 E00791 0 +OP4 E00792 0 +OP4 E00793 0 +OP4 E00794 0 +OP4 E00795 0 +OP4 E00796 0 +OP4 E00797 0 +OP4 E00798 0 +OP4 E00799 0 +OP4 E0079A 0 +OP4 E0079B 0 +OP4 E0079C 0 +OP4 E0079D 0 +OP4 E0079E 0 +OP4 E0079F 0 +OP4 E007A0 0 +OP4 E007A1 0 +OP4 E007A2 0 +OP4 E007A3 0 +OP4 E007A4 0 +OP4 E007A5 0 +OP4 E007A6 0 +OP4 E007A7 0 +OP4 E007A8 0 +OP4 E007A9 0 +OP4 E007AA 0 +OP4 E007AB 0 +OP4 E007AC 0 +OP4 E007AD 0 +OP4 E007AE 0 +OP4 E007AF 0 +OP4 E007B0 0 +OP4 E007B1 0 +OP4 E007B2 0 +OP4 E007B3 0 +OP4 E007B4 0 +OP4 E007B5 0 +OP4 E007B6 0 +OP4 E007B7 0 +OP4 E007B8 0 +OP4 E007B9 0 +OP4 E007BA 0 +OP4 E007BB 0 +OP4 E007BC 0 +OP4 E007BD 0 +OP4 E007BE 0 +OP4 E007BF 0 +OP4 E007C0 0 +OP4 E007C1 0 +OP4 E007C2 0 +OP4 E007C3 0 +OP4 E007C4 0 +OP4 E007C5 0 +OP4 E007C6 0 +OP4 E007C7 0 +OP4 E007C8 0 +OP4 E007C9 0 +OP4 E007CA 0 +OP4 E007CB 0 +OP4 E007CC 0 +OP4 E007CD 0 +OP4 E007CE 0 +OP4 E007CF 0 +OP4 E007D0 0 +OP4 E007D1 0 +OP4 E007D2 0 +OP4 E007D3 0 +OP4 E007D4 0 +OP4 E007D5 0 +OP4 E007D6 0 +OP4 E007D7 0 +OP4 E007D8 0 +OP4 E007D9 0 +OP4 E007DA 0 +OP4 E007DB 0 +OP4 E007DC 0 +OP4 E007DD 0 +OP4 E007DE 0 +OP4 E007DF 0 +OP4 E007E0 0 +OP4 E007E1 0 +OP4 E007E2 0 +OP4 E007E3 0 +OP4 E007E4 0 +OP4 E007E5 0 +OP4 E007E6 0 +OP4 E007E7 0 +OP4 E007E8 0 +OP4 E007E9 0 +OP4 E007EA 0 +OP4 E007EB 0 +OP4 E007EC 0 +OP4 E007ED 0 +OP4 E007EE 0 +OP4 E007EF 0 +OP4 E007F0 0 +OP4 E007F1 0 +OP4 E007F2 0 +OP4 E007F3 0 +OP4 E007F4 0 +OP4 E007F5 0 +OP4 E007F6 0 +OP4 E007F7 0 +OP4 E007F8 0 +OP4 E007F9 0 +OP4 E007FA 0 +OP4 E007FB 0 +OP4 E007FC 0 +OP4 E007FD 0 +OP4 E007FE 0 +OP4 E007FF 0 +OP4 E00800 0 +OP4 E00801 0 +OP4 E00802 0 +OP4 E00803 0 +OP4 E00804 0 +OP4 E00805 0 +OP4 E00806 0 +OP4 E00807 0 +OP4 E00808 0 +OP4 E00809 0 +OP4 E0080A 0 +OP4 E0080B 0 +OP4 E0080C 0 +OP4 E0080D 0 +OP4 E0080E 0 +OP4 E0080F 0 +OP4 E00810 0 +OP4 E00811 0 +OP4 E00812 0 +OP4 E00813 0 +OP4 E00814 0 +OP4 E00815 0 +OP4 E00816 0 +OP4 E00817 0 +OP4 E00818 0 +OP4 E00819 0 +OP4 E0081A 0 +OP4 E0081B 0 +OP4 E0081C 0 +OP4 E0081D 0 +OP4 E0081E 0 +OP4 E0081F 0 +OP4 E00820 0 +OP4 E00821 0 +OP4 E00822 0 +OP4 E00823 0 +OP4 E00824 0 +OP4 E00825 0 +OP4 E00826 0 +OP4 E00827 0 +OP4 E00828 0 +OP4 E00829 0 +OP4 E0082A 0 +OP4 E0082B 0 +OP4 E0082C 0 +OP4 E0082D 0 +OP4 E0082E 0 +OP4 E0082F 0 +OP4 E00830 0 +OP4 E00831 0 +OP4 E00832 0 +OP4 E00833 0 +OP4 E00834 0 +OP4 E00835 0 +OP4 E00836 0 +OP4 E00837 0 +OP4 E00838 0 +OP4 E00839 0 +OP4 E0083A 0 +OP4 E0083B 0 +OP4 E0083C 0 +OP4 E0083D 0 +OP4 E0083E 0 +OP4 E0083F 0 +OP4 E00840 0 +OP4 E00841 0 +OP4 E00842 0 +OP4 E00843 0 +OP4 E00844 0 +OP4 E00845 0 +OP4 E00846 0 +OP4 E00847 0 +OP4 E00848 0 +OP4 E00849 0 +OP4 E0084A 0 +OP4 E0084B 0 +OP4 E0084C 0 +OP4 E0084D 0 +OP4 E0084E 0 +OP4 E0084F 0 +OP4 E00850 0 +OP4 E00851 0 +OP4 E00852 0 +OP4 E00853 0 +OP4 E00854 0 +OP4 E00855 0 +OP4 E00856 0 +OP4 E00857 0 +OP4 E00858 0 +OP4 E00859 0 +OP4 E0085A 0 +OP4 E0085B 0 +OP4 E0085C 0 +OP4 E0085D 0 +OP4 E0085E 0 +OP4 E0085F 0 +OP4 E00860 0 +OP4 E00861 0 +OP4 E00862 0 +OP4 E00863 0 +OP4 E00864 0 +OP4 E00865 0 +OP4 E00866 0 +OP4 E00867 0 +OP4 E00868 0 +OP4 E00869 0 +OP4 E0086A 0 +OP4 E0086B 0 +OP4 E0086C 0 +OP4 E0086D 0 +OP4 E0086E 0 +OP4 E0086F 0 +OP4 E00870 0 +OP4 E00871 0 +OP4 E00872 0 +OP4 E00873 0 +OP4 E00874 0 +OP4 E00875 0 +OP4 E00876 0 +OP4 E00877 0 +OP4 E00878 0 +OP4 E00879 0 +OP4 E0087A 0 +OP4 E0087B 0 +OP4 E0087C 0 +OP4 E0087D 0 +OP4 E0087E 0 +OP4 E0087F 0 +OP4 E00880 0 +OP4 E00881 0 +OP4 E00882 0 +OP4 E00883 0 +OP4 E00884 0 +OP4 E00885 0 +OP4 E00886 0 +OP4 E00887 0 +OP4 E00888 0 +OP4 E00889 0 +OP4 E0088A 0 +OP4 E0088B 0 +OP4 E0088C 0 +OP4 E0088D 0 +OP4 E0088E 0 +OP4 E0088F 0 +OP4 E00890 0 +OP4 E00891 0 +OP4 E00892 0 +OP4 E00893 0 +OP4 E00894 0 +OP4 E00895 0 +OP4 E00896 0 +OP4 E00897 0 +OP4 E00898 0 +OP4 E00899 0 +OP4 E0089A 0 +OP4 E0089B 0 +OP4 E0089C 0 +OP4 E0089D 0 +OP4 E0089E 0 +OP4 E0089F 0 +OP4 E008A0 0 +OP4 E008A1 0 +OP4 E008A2 0 +OP4 E008A3 0 +OP4 E008A4 0 +OP4 E008A5 0 +OP4 E008A6 0 +OP4 E008A7 0 +OP4 E008A8 0 +OP4 E008A9 0 +OP4 E008AA 0 +OP4 E008AB 0 +OP4 E008AC 0 +OP4 E008AD 0 +OP4 E008AE 0 +OP4 E008AF 0 +OP4 E008B0 0 +OP4 E008B1 0 +OP4 E008B2 0 +OP4 E008B3 0 +OP4 E008B4 0 +OP4 E008B5 0 +OP4 E008B6 0 +OP4 E008B7 0 +OP4 E008B8 0 +OP4 E008B9 0 +OP4 E008BA 0 +OP4 E008BB 0 +OP4 E008BC 0 +OP4 E008BD 0 +OP4 E008BE 0 +OP4 E008BF 0 +OP4 E008C0 0 +OP4 E008C1 0 +OP4 E008C2 0 +OP4 E008C3 0 +OP4 E008C4 0 +OP4 E008C5 0 +OP4 E008C6 0 +OP4 E008C7 0 +OP4 E008C8 0 +OP4 E008C9 0 +OP4 E008CA 0 +OP4 E008CB 0 +OP4 E008CC 0 +OP4 E008CD 0 +OP4 E008CE 0 +OP4 E008CF 0 +OP4 E008D0 0 +OP4 E008D1 0 +OP4 E008D2 0 +OP4 E008D3 0 +OP4 E008D4 0 +OP4 E008D5 0 +OP4 E008D6 0 +OP4 E008D7 0 +OP4 E008D8 0 +OP4 E008D9 0 +OP4 E008DA 0 +OP4 E008DB 0 +OP4 E008DC 0 +OP4 E008DD 0 +OP4 E008DE 0 +OP4 E008DF 0 +OP4 E008E0 0 +OP4 E008E1 0 +OP4 E008E2 0 +OP4 E008E3 0 +OP4 E008E4 0 +OP4 E008E5 0 +OP4 E008E6 0 +OP4 E008E7 0 +OP4 E008E8 0 +OP4 E008E9 0 +OP4 E008EA 0 +OP4 E008EB 0 +OP4 E008EC 0 +OP4 E008ED 0 +OP4 E008EE 0 +OP4 E008EF 0 +OP4 E008F0 0 +OP4 E008F1 0 +OP4 E008F2 0 +OP4 E008F3 0 +OP4 E008F4 0 +OP4 E008F5 0 +OP4 E008F6 0 +OP4 E008F7 0 +OP4 E008F8 0 +OP4 E008F9 0 +OP4 E008FA 0 +OP4 E008FB 0 +OP4 E008FC 0 +OP4 E008FD 0 +OP4 E008FE 0 +OP4 E008FF 0 +OP4 E00900 0 +OP4 E00901 0 +OP4 E00902 0 +OP4 E00903 0 +OP4 E00904 0 +OP4 E00905 0 +OP4 E00906 0 +OP4 E00907 0 +OP4 E00908 0 +OP4 E00909 0 +OP4 E0090A 0 +OP4 E0090B 0 +OP4 E0090C 0 +OP4 E0090D 0 +OP4 E0090E 0 +OP4 E0090F 0 +OP4 E00910 0 +OP4 E00911 0 +OP4 E00912 0 +OP4 E00913 0 +OP4 E00914 0 +OP4 E00915 0 +OP4 E00916 0 +OP4 E00917 0 +OP4 E00918 0 +OP4 E00919 0 +OP4 E0091A 0 +OP4 E0091B 0 +OP4 E0091C 0 +OP4 E0091D 0 +OP4 E0091E 0 +OP4 E0091F 0 +OP4 E00920 0 +OP4 E00921 0 +OP4 E00922 0 +OP4 E00923 0 +OP4 E00924 0 +OP4 E00925 0 +OP4 E00926 0 +OP4 E00927 0 +OP4 E00928 0 +OP4 E00929 0 +OP4 E0092A 0 +OP4 E0092B 0 +OP4 E0092C 0 +OP4 E0092D 0 +OP4 E0092E 0 +OP4 E0092F 0 +OP4 E00930 0 +OP4 E00931 0 +OP4 E00932 0 +OP4 E00933 0 +OP4 E00934 0 +OP4 E00935 0 +OP4 E00936 0 +OP4 E00937 0 +OP4 E00938 0 +OP4 E00939 0 +OP4 E0093A 0 +OP4 E0093B 0 +OP4 E0093C 0 +OP4 E0093D 0 +OP4 E0093E 0 +OP4 E0093F 0 +OP4 E00940 0 +OP4 E00941 0 +OP4 E00942 0 +OP4 E00943 0 +OP4 E00944 0 +OP4 E00945 0 +OP4 E00946 0 +OP4 E00947 0 +OP4 E00948 0 +OP4 E00949 0 +OP4 E0094A 0 +OP4 E0094B 0 +OP4 E0094C 0 +OP4 E0094D 0 +OP4 E0094E 0 +OP4 E0094F 0 +OP4 E00950 0 +OP4 E00951 0 +OP4 E00952 0 +OP4 E00953 0 +OP4 E00954 0 +OP4 E00955 0 +OP4 E00956 0 +OP4 E00957 0 +OP4 E00958 0 +OP4 E00959 0 +OP4 E0095A 0 +OP4 E0095B 0 +OP4 E0095C 0 +OP4 E0095D 0 +OP4 E0095E 0 +OP4 E0095F 0 +OP4 E00960 0 +OP4 E00961 0 +OP4 E00962 0 +OP4 E00963 0 +OP4 E00964 0 +OP4 E00965 0 +OP4 E00966 0 +OP4 E00967 0 +OP4 E00968 0 +OP4 E00969 0 +OP4 E0096A 0 +OP4 E0096B 0 +OP4 E0096C 0 +OP4 E0096D 0 +OP4 E0096E 0 +OP4 E0096F 0 +OP4 E00970 0 +OP4 E00971 0 +OP4 E00972 0 +OP4 E00973 0 +OP4 E00974 0 +OP4 E00975 0 +OP4 E00976 0 +OP4 E00977 0 +OP4 E00978 0 +OP4 E00979 0 +OP4 E0097A 0 +OP4 E0097B 0 +OP4 E0097C 0 +OP4 E0097D 0 +OP4 E0097E 0 +OP4 E0097F 0 +OP4 E00980 0 +OP4 E00981 0 +OP4 E00982 0 +OP4 E00983 0 +OP4 E00984 0 +OP4 E00985 0 +OP4 E00986 0 +OP4 E00987 0 +OP4 E00988 0 +OP4 E00989 0 +OP4 E0098A 0 +OP4 E0098B 0 +OP4 E0098C 0 +OP4 E0098D 0 +OP4 E0098E 0 +OP4 E0098F 0 +OP4 E00990 0 +OP4 E00991 0 +OP4 E00992 0 +OP4 E00993 0 +OP4 E00994 0 +OP4 E00995 0 +OP4 E00996 0 +OP4 E00997 0 +OP4 E00998 0 +OP4 E00999 0 +OP4 E0099A 0 +OP4 E0099B 0 +OP4 E0099C 0 +OP4 E0099D 0 +OP4 E0099E 0 +OP4 E0099F 0 +OP4 E009A0 0 +OP4 E009A1 0 +OP4 E009A2 0 +OP4 E009A3 0 +OP4 E009A4 0 +OP4 E009A5 0 +OP4 E009A6 0 +OP4 E009A7 0 +OP4 E009A8 0 +OP4 E009A9 0 +OP4 E009AA 0 +OP4 E009AB 0 +OP4 E009AC 0 +OP4 E009AD 0 +OP4 E009AE 0 +OP4 E009AF 0 +OP4 E009B0 0 +OP4 E009B1 0 +OP4 E009B2 0 +OP4 E009B3 0 +OP4 E009B4 0 +OP4 E009B5 0 +OP4 E009B6 0 +OP4 E009B7 0 +OP4 E009B8 0 +OP4 E009B9 0 +OP4 E009BA 0 +OP4 E009BB 0 +OP4 E009BC 0 +OP4 E009BD 0 +OP4 E009BE 0 +OP4 E009BF 0 +OP4 E009C0 0 +OP4 E009C1 0 +OP4 E009C2 0 +OP4 E009C3 0 +OP4 E009C4 0 +OP4 E009C5 0 +OP4 E009C6 0 +OP4 E009C7 0 +OP4 E009C8 0 +OP4 E009C9 0 +OP4 E009CA 0 +OP4 E009CB 0 +OP4 E009CC 0 +OP4 E009CD 0 +OP4 E009CE 0 +OP4 E009CF 0 +OP4 E009D0 0 +OP4 E009D1 0 +OP4 E009D2 0 +OP4 E009D3 0 +OP4 E009D4 0 +OP4 E009D5 0 +OP4 E009D6 0 +OP4 E009D7 0 +OP4 E009D8 0 +OP4 E009D9 0 +OP4 E009DA 0 +OP4 E009DB 0 +OP4 E009DC 0 +OP4 E009DD 0 +OP4 E009DE 0 +OP4 E009DF 0 +OP4 E009E0 0 +OP4 E009E1 0 +OP4 E009E2 0 +OP4 E009E3 0 +OP4 E009E4 0 +OP4 E009E5 0 +OP4 E009E6 0 +OP4 E009E7 0 +OP4 E009E8 0 +OP4 E009E9 0 +OP4 E009EA 0 +OP4 E009EB 0 +OP4 E009EC 0 +OP4 E009ED 0 +OP4 E009EE 0 +OP4 E009EF 0 +OP4 E009F0 0 +OP4 E009F1 0 +OP4 E009F2 0 +OP4 E009F3 0 +OP4 E009F4 0 +OP4 E009F5 0 +OP4 E009F6 0 +OP4 E009F7 0 +OP4 E009F8 0 +OP4 E009F9 0 +OP4 E009FA 0 +OP4 E009FB 0 +OP4 E009FC 0 +OP4 E009FD 0 +OP4 E009FE 0 +OP4 E009FF 0 +OP4 E00A00 0 +OP4 E00A01 0 +OP4 E00A02 0 +OP4 E00A03 0 +OP4 E00A04 0 +OP4 E00A05 0 +OP4 E00A06 0 +OP4 E00A07 0 +OP4 E00A08 0 +OP4 E00A09 0 +OP4 E00A0A 0 +OP4 E00A0B 0 +OP4 E00A0C 0 +OP4 E00A0D 0 +OP4 E00A0E 0 +OP4 E00A0F 0 +OP4 E00A10 0 +OP4 E00A11 0 +OP4 E00A12 0 +OP4 E00A13 0 +OP4 E00A14 0 +OP4 E00A15 0 +OP4 E00A16 0 +OP4 E00A17 0 +OP4 E00A18 0 +OP4 E00A19 0 +OP4 E00A1A 0 +OP4 E00A1B 0 +OP4 E00A1C 0 +OP4 E00A1D 0 +OP4 E00A1E 0 +OP4 E00A1F 0 +OP4 E00A20 0 +OP4 E00A21 0 +OP4 E00A22 0 +OP4 E00A23 0 +OP4 E00A24 0 +OP4 E00A25 0 +OP4 E00A26 0 +OP4 E00A27 0 +OP4 E00A28 0 +OP4 E00A29 0 +OP4 E00A2A 0 +OP4 E00A2B 0 +OP4 E00A2C 0 +OP4 E00A2D 0 +OP4 E00A2E 0 +OP4 E00A2F 0 +OP4 E00A30 0 +OP4 E00A31 0 +OP4 E00A32 0 +OP4 E00A33 0 +OP4 E00A34 0 +OP4 E00A35 0 +OP4 E00A36 0 +OP4 E00A37 0 +OP4 E00A38 0 +OP4 E00A39 0 +OP4 E00A3A 0 +OP4 E00A3B 0 +OP4 E00A3C 0 +OP4 E00A3D 0 +OP4 E00A3E 0 +OP4 E00A3F 0 +OP4 E00A40 0 +OP4 E00A41 0 +OP4 E00A42 0 +OP4 E00A43 0 +OP4 E00A44 0 +OP4 E00A45 0 +OP4 E00A46 0 +OP4 E00A47 0 +OP4 E00A48 0 +OP4 E00A49 0 +OP4 E00A4A 0 +OP4 E00A4B 0 +OP4 E00A4C 0 +OP4 E00A4D 0 +OP4 E00A4E 0 +OP4 E00A4F 0 +OP4 E00A50 0 +OP4 E00A51 0 +OP4 E00A52 0 +OP4 E00A53 0 +OP4 E00A54 0 +OP4 E00A55 0 +OP4 E00A56 0 +OP4 E00A57 0 +OP4 E00A58 0 +OP4 E00A59 0 +OP4 E00A5A 0 +OP4 E00A5B 0 +OP4 E00A5C 0 +OP4 E00A5D 0 +OP4 E00A5E 0 +OP4 E00A5F 0 +OP4 E00A60 0 +OP4 E00A61 0 +OP4 E00A62 0 +OP4 E00A63 0 +OP4 E00A64 0 +OP4 E00A65 0 +OP4 E00A66 0 +OP4 E00A67 0 +OP4 E00A68 0 +OP4 E00A69 0 +OP4 E00A6A 0 +OP4 E00A6B 0 +OP4 E00A6C 0 +OP4 E00A6D 0 +OP4 E00A6E 0 +OP4 E00A6F 0 +OP4 E00A70 0 +OP4 E00A71 0 +OP4 E00A72 0 +OP4 E00A73 0 +OP4 E00A74 0 +OP4 E00A75 0 +OP4 E00A76 0 +OP4 E00A77 0 +OP4 E00A78 0 +OP4 E00A79 0 +OP4 E00A7A 0 +OP4 E00A7B 0 +OP4 E00A7C 0 +OP4 E00A7D 0 +OP4 E00A7E 0 +OP4 E00A7F 0 +OP4 E00A80 0 +OP4 E00A81 0 +OP4 E00A82 0 +OP4 E00A83 0 +OP4 E00A84 0 +OP4 E00A85 0 +OP4 E00A86 0 +OP4 E00A87 0 +OP4 E00A88 0 +OP4 E00A89 0 +OP4 E00A8A 0 +OP4 E00A8B 0 +OP4 E00A8C 0 +OP4 E00A8D 0 +OP4 E00A8E 0 +OP4 E00A8F 0 +OP4 E00A90 0 +OP4 E00A91 0 +OP4 E00A92 0 +OP4 E00A93 0 +OP4 E00A94 0 +OP4 E00A95 0 +OP4 E00A96 0 +OP4 E00A97 0 +OP4 E00A98 0 +OP4 E00A99 0 +OP4 E00A9A 0 +OP4 E00A9B 0 +OP4 E00A9C 0 +OP4 E00A9D 0 +OP4 E00A9E 0 +OP4 E00A9F 0 +OP4 E00AA0 0 +OP4 E00AA1 0 +OP4 E00AA2 0 +OP4 E00AA3 0 +OP4 E00AA4 0 +OP4 E00AA5 0 +OP4 E00AA6 0 +OP4 E00AA7 0 +OP4 E00AA8 0 +OP4 E00AA9 0 +OP4 E00AAA 0 +OP4 E00AAB 0 +OP4 E00AAC 0 +OP4 E00AAD 0 +OP4 E00AAE 0 +OP4 E00AAF 0 +OP4 E00AB0 0 +OP4 E00AB1 0 +OP4 E00AB2 0 +OP4 E00AB3 0 +OP4 E00AB4 0 +OP4 E00AB5 0 +OP4 E00AB6 0 +OP4 E00AB7 0 +OP4 E00AB8 0 +OP4 E00AB9 0 +OP4 E00ABA 0 +OP4 E00ABB 0 +OP4 E00ABC 0 +OP4 E00ABD 0 +OP4 E00ABE 0 +OP4 E00ABF 0 +OP4 E00AC0 0 +OP4 E00AC1 0 +OP4 E00AC2 0 +OP4 E00AC3 0 +OP4 E00AC4 0 +OP4 E00AC5 0 +OP4 E00AC6 0 +OP4 E00AC7 0 +OP4 E00AC8 0 +OP4 E00AC9 0 +OP4 E00ACA 0 +OP4 E00ACB 0 +OP4 E00ACC 0 +OP4 E00ACD 0 +OP4 E00ACE 0 +OP4 E00ACF 0 +OP4 E00AD0 0 +OP4 E00AD1 0 +OP4 E00AD2 0 +OP4 E00AD3 0 +OP4 E00AD4 0 +OP4 E00AD5 0 +OP4 E00AD6 0 +OP4 E00AD7 0 +OP4 E00AD8 0 +OP4 E00AD9 0 +OP4 E00ADA 0 +OP4 E00ADB 0 +OP4 E00ADC 0 +OP4 E00ADD 0 +OP4 E00ADE 0 +OP4 E00ADF 0 +OP4 E00AE0 0 +OP4 E00AE1 0 +OP4 E00AE2 0 +OP4 E00AE3 0 +OP4 E00AE4 0 +OP4 E00AE5 0 +OP4 E00AE6 0 +OP4 E00AE7 0 +OP4 E00AE8 0 +OP4 E00AE9 0 +OP4 E00AEA 0 +OP4 E00AEB 0 +OP4 E00AEC 0 +OP4 E00AED 0 +OP4 E00AEE 0 +OP4 E00AEF 0 +OP4 E00AF0 0 +OP4 E00AF1 0 +OP4 E00AF2 0 +OP4 E00AF3 0 +OP4 E00AF4 0 +OP4 E00AF5 0 +OP4 E00AF6 0 +OP4 E00AF7 0 +OP4 E00AF8 0 +OP4 E00AF9 0 +OP4 E00AFA 0 +OP4 E00AFB 0 +OP4 E00AFC 0 +OP4 E00AFD 0 +OP4 E00AFE 0 +OP4 E00AFF 0 +OP4 E00B00 0 +OP4 E00B01 0 +OP4 E00B02 0 +OP4 E00B03 0 +OP4 E00B04 0 +OP4 E00B05 0 +OP4 E00B06 0 +OP4 E00B07 0 +OP4 E00B08 0 +OP4 E00B09 0 +OP4 E00B0A 0 +OP4 E00B0B 0 +OP4 E00B0C 0 +OP4 E00B0D 0 +OP4 E00B0E 0 +OP4 E00B0F 0 +OP4 E00B10 0 +OP4 E00B11 0 +OP4 E00B12 0 +OP4 E00B13 0 +OP4 E00B14 0 +OP4 E00B15 0 +OP4 E00B16 0 +OP4 E00B17 0 +OP4 E00B18 0 +OP4 E00B19 0 +OP4 E00B1A 0 +OP4 E00B1B 0 +OP4 E00B1C 0 +OP4 E00B1D 0 +OP4 E00B1E 0 +OP4 E00B1F 0 +OP4 E00B20 0 +OP4 E00B21 0 +OP4 E00B22 0 +OP4 E00B23 0 +OP4 E00B24 0 +OP4 E00B25 0 +OP4 E00B26 0 +OP4 E00B27 0 +OP4 E00B28 0 +OP4 E00B29 0 +OP4 E00B2A 0 +OP4 E00B2B 0 +OP4 E00B2C 0 +OP4 E00B2D 0 +OP4 E00B2E 0 +OP4 E00B2F 0 +OP4 E00B30 0 +OP4 E00B31 0 +OP4 E00B32 0 +OP4 E00B33 0 +OP4 E00B34 0 +OP4 E00B35 0 +OP4 E00B36 0 +OP4 E00B37 0 +OP4 E00B38 0 +OP4 E00B39 0 +OP4 E00B3A 0 +OP4 E00B3B 0 +OP4 E00B3C 0 +OP4 E00B3D 0 +OP4 E00B3E 0 +OP4 E00B3F 0 +OP4 E00B40 0 +OP4 E00B41 0 +OP4 E00B42 0 +OP4 E00B43 0 +OP4 E00B44 0 +OP4 E00B45 0 +OP4 E00B46 0 +OP4 E00B47 0 +OP4 E00B48 0 +OP4 E00B49 0 +OP4 E00B4A 0 +OP4 E00B4B 0 +OP4 E00B4C 0 +OP4 E00B4D 0 +OP4 E00B4E 0 +OP4 E00B4F 0 +OP4 E00B50 0 +OP4 E00B51 0 +OP4 E00B52 0 +OP4 E00B53 0 +OP4 E00B54 0 +OP4 E00B55 0 +OP4 E00B56 0 +OP4 E00B57 0 +OP4 E00B58 0 +OP4 E00B59 0 +OP4 E00B5A 0 +OP4 E00B5B 0 +OP4 E00B5C 0 +OP4 E00B5D 0 +OP4 E00B5E 0 +OP4 E00B5F 0 +OP4 E00B60 0 +OP4 E00B61 0 +OP4 E00B62 0 +OP4 E00B63 0 +OP4 E00B64 0 +OP4 E00B65 0 +OP4 E00B66 0 +OP4 E00B67 0 +OP4 E00B68 0 +OP4 E00B69 0 +OP4 E00B6A 0 +OP4 E00B6B 0 +OP4 E00B6C 0 +OP4 E00B6D 0 +OP4 E00B6E 0 +OP4 E00B6F 0 +OP4 E00B70 0 +OP4 E00B71 0 +OP4 E00B72 0 +OP4 E00B73 0 +OP4 E00B74 0 +OP4 E00B75 0 +OP4 E00B76 0 +OP4 E00B77 0 +OP4 E00B78 0 +OP4 E00B79 0 +OP4 E00B7A 0 +OP4 E00B7B 0 +OP4 E00B7C 0 +OP4 E00B7D 0 +OP4 E00B7E 0 +OP4 E00B7F 0 +OP4 E00B80 0 +OP4 E00B81 0 +OP4 E00B82 0 +OP4 E00B83 0 +OP4 E00B84 0 +OP4 E00B85 0 +OP4 E00B86 0 +OP4 E00B87 0 +OP4 E00B88 0 +OP4 E00B89 0 +OP4 E00B8A 0 +OP4 E00B8B 0 +OP4 E00B8C 0 +OP4 E00B8D 0 +OP4 E00B8E 0 +OP4 E00B8F 0 +OP4 E00B90 0 +OP4 E00B91 0 +OP4 E00B92 0 +OP4 E00B93 0 +OP4 E00B94 0 +OP4 E00B95 0 +OP4 E00B96 0 +OP4 E00B97 0 +OP4 E00B98 0 +OP4 E00B99 0 +OP4 E00B9A 0 +OP4 E00B9B 0 +OP4 E00B9C 0 +OP4 E00B9D 0 +OP4 E00B9E 0 +OP4 E00B9F 0 +OP4 E00BA0 0 +OP4 E00BA1 0 +OP4 E00BA2 0 +OP4 E00BA3 0 +OP4 E00BA4 0 +OP4 E00BA5 0 +OP4 E00BA6 0 +OP4 E00BA7 0 +OP4 E00BA8 0 +OP4 E00BA9 0 +OP4 E00BAA 0 +OP4 E00BAB 0 +OP4 E00BAC 0 +OP4 E00BAD 0 +OP4 E00BAE 0 +OP4 E00BAF 0 +OP4 E00BB0 0 +OP4 E00BB1 0 +OP4 E00BB2 0 +OP4 E00BB3 0 +OP4 E00BB4 0 +OP4 E00BB5 0 +OP4 E00BB6 0 +OP4 E00BB7 0 +OP4 E00BB8 0 +OP4 E00BB9 0 +OP4 E00BBA 0 +OP4 E00BBB 0 +OP4 E00BBC 0 +OP4 E00BBD 0 +OP4 E00BBE 0 +OP4 E00BBF 0 +OP4 E00BC0 0 +OP4 E00BC1 0 +OP4 E00BC2 0 +OP4 E00BC3 0 +OP4 E00BC4 0 +OP4 E00BC5 0 +OP4 E00BC6 0 +OP4 E00BC7 0 +OP4 E00BC8 0 +OP4 E00BC9 0 +OP4 E00BCA 0 +OP4 E00BCB 0 +OP4 E00BCC 0 +OP4 E00BCD 0 +OP4 E00BCE 0 +OP4 E00BCF 0 +OP4 E00BD0 0 +OP4 E00BD1 0 +OP4 E00BD2 0 +OP4 E00BD3 0 +OP4 E00BD4 0 +OP4 E00BD5 0 +OP4 E00BD6 0 +OP4 E00BD7 0 +OP4 E00BD8 0 +OP4 E00BD9 0 +OP4 E00BDA 0 +OP4 E00BDB 0 +OP4 E00BDC 0 +OP4 E00BDD 0 +OP4 E00BDE 0 +OP4 E00BDF 0 +OP4 E00BE0 0 +OP4 E00BE1 0 +OP4 E00BE2 0 +OP4 E00BE3 0 +OP4 E00BE4 0 +OP4 E00BE5 0 +OP4 E00BE6 0 +OP4 E00BE7 0 +OP4 E00BE8 0 +OP4 E00BE9 0 +OP4 E00BEA 0 +OP4 E00BEB 0 +OP4 E00BEC 0 +OP4 E00BED 0 +OP4 E00BEE 0 +OP4 E00BEF 0 +OP4 E00BF0 0 +OP4 E00BF1 0 +OP4 E00BF2 0 +OP4 E00BF3 0 +OP4 E00BF4 0 +OP4 E00BF5 0 +OP4 E00BF6 0 +OP4 E00BF7 0 +OP4 E00BF8 0 +OP4 E00BF9 0 +OP4 E00BFA 0 +OP4 E00BFB 0 +OP4 E00BFC 0 +OP4 E00BFD 0 +OP4 E00BFE 0 +OP4 E00BFF 0 +OP4 E00C00 0 +OP4 E00C01 0 +OP4 E00C02 0 +OP4 E00C03 0 +OP4 E00C04 0 +OP4 E00C05 0 +OP4 E00C06 0 +OP4 E00C07 0 +OP4 E00C08 0 +OP4 E00C09 0 +OP4 E00C0A 0 +OP4 E00C0B 0 +OP4 E00C0C 0 +OP4 E00C0D 0 +OP4 E00C0E 0 +OP4 E00C0F 0 +OP4 E00C10 0 +OP4 E00C11 0 +OP4 E00C12 0 +OP4 E00C13 0 +OP4 E00C14 0 +OP4 E00C15 0 +OP4 E00C16 0 +OP4 E00C17 0 +OP4 E00C18 0 +OP4 E00C19 0 +OP4 E00C1A 0 +OP4 E00C1B 0 +OP4 E00C1C 0 +OP4 E00C1D 0 +OP4 E00C1E 0 +OP4 E00C1F 0 +OP4 E00C20 0 +OP4 E00C21 0 +OP4 E00C22 0 +OP4 E00C23 0 +OP4 E00C24 0 +OP4 E00C25 0 +OP4 E00C26 0 +OP4 E00C27 0 +OP4 E00C28 0 +OP4 E00C29 0 +OP4 E00C2A 0 +OP4 E00C2B 0 +OP4 E00C2C 0 +OP4 E00C2D 0 +OP4 E00C2E 0 +OP4 E00C2F 0 +OP4 E00C30 0 +OP4 E00C31 0 +OP4 E00C32 0 +OP4 E00C33 0 +OP4 E00C34 0 +OP4 E00C35 0 +OP4 E00C36 0 +OP4 E00C37 0 +OP4 E00C38 0 +OP4 E00C39 0 +OP4 E00C3A 0 +OP4 E00C3B 0 +OP4 E00C3C 0 +OP4 E00C3D 0 +OP4 E00C3E 0 +OP4 E00C3F 0 +OP4 E00C40 0 +OP4 E00C41 0 +OP4 E00C42 0 +OP4 E00C43 0 +OP4 E00C44 0 +OP4 E00C45 0 +OP4 E00C46 0 +OP4 E00C47 0 +OP4 E00C48 0 +OP4 E00C49 0 +OP4 E00C4A 0 +OP4 E00C4B 0 +OP4 E00C4C 0 +OP4 E00C4D 0 +OP4 E00C4E 0 +OP4 E00C4F 0 +OP4 E00C50 0 +OP4 E00C51 0 +OP4 E00C52 0 +OP4 E00C53 0 +OP4 E00C54 0 +OP4 E00C55 0 +OP4 E00C56 0 +OP4 E00C57 0 +OP4 E00C58 0 +OP4 E00C59 0 +OP4 E00C5A 0 +OP4 E00C5B 0 +OP4 E00C5C 0 +OP4 E00C5D 0 +OP4 E00C5E 0 +OP4 E00C5F 0 +OP4 E00C60 0 +OP4 E00C61 0 +OP4 E00C62 0 +OP4 E00C63 0 +OP4 E00C64 0 +OP4 E00C65 0 +OP4 E00C66 0 +OP4 E00C67 0 +OP4 E00C68 0 +OP4 E00C69 0 +OP4 E00C6A 0 +OP4 E00C6B 0 +OP4 E00C6C 0 +OP4 E00C6D 0 +OP4 E00C6E 0 +OP4 E00C6F 0 +OP4 E00C70 0 +OP4 E00C71 0 +OP4 E00C72 0 +OP4 E00C73 0 +OP4 E00C74 0 +OP4 E00C75 0 +OP4 E00C76 0 +OP4 E00C77 0 +OP4 E00C78 0 +OP4 E00C79 0 +OP4 E00C7A 0 +OP4 E00C7B 0 +OP4 E00C7C 0 +OP4 E00C7D 0 +OP4 E00C7E 0 +OP4 E00C7F 0 +OP4 E00C80 0 +OP4 E00C81 0 +OP4 E00C82 0 +OP4 E00C83 0 +OP4 E00C84 0 +OP4 E00C85 0 +OP4 E00C86 0 +OP4 E00C87 0 +OP4 E00C88 0 +OP4 E00C89 0 +OP4 E00C8A 0 +OP4 E00C8B 0 +OP4 E00C8C 0 +OP4 E00C8D 0 +OP4 E00C8E 0 +OP4 E00C8F 0 +OP4 E00C90 0 +OP4 E00C91 0 +OP4 E00C92 0 +OP4 E00C93 0 +OP4 E00C94 0 +OP4 E00C95 0 +OP4 E00C96 0 +OP4 E00C97 0 +OP4 E00C98 0 +OP4 E00C99 0 +OP4 E00C9A 0 +OP4 E00C9B 0 +OP4 E00C9C 0 +OP4 E00C9D 0 +OP4 E00C9E 0 +OP4 E00C9F 0 +OP4 E00CA0 0 +OP4 E00CA1 0 +OP4 E00CA2 0 +OP4 E00CA3 0 +OP4 E00CA4 0 +OP4 E00CA5 0 +OP4 E00CA6 0 +OP4 E00CA7 0 +OP4 E00CA8 0 +OP4 E00CA9 0 +OP4 E00CAA 0 +OP4 E00CAB 0 +OP4 E00CAC 0 +OP4 E00CAD 0 +OP4 E00CAE 0 +OP4 E00CAF 0 +OP4 E00CB0 0 +OP4 E00CB1 0 +OP4 E00CB2 0 +OP4 E00CB3 0 +OP4 E00CB4 0 +OP4 E00CB5 0 +OP4 E00CB6 0 +OP4 E00CB7 0 +OP4 E00CB8 0 +OP4 E00CB9 0 +OP4 E00CBA 0 +OP4 E00CBB 0 +OP4 E00CBC 0 +OP4 E00CBD 0 +OP4 E00CBE 0 +OP4 E00CBF 0 +OP4 E00CC0 0 +OP4 E00CC1 0 +OP4 E00CC2 0 +OP4 E00CC3 0 +OP4 E00CC4 0 +OP4 E00CC5 0 +OP4 E00CC6 0 +OP4 E00CC7 0 +OP4 E00CC8 0 +OP4 E00CC9 0 +OP4 E00CCA 0 +OP4 E00CCB 0 +OP4 E00CCC 0 +OP4 E00CCD 0 +OP4 E00CCE 0 +OP4 E00CCF 0 +OP4 E00CD0 0 +OP4 E00CD1 0 +OP4 E00CD2 0 +OP4 E00CD3 0 +OP4 E00CD4 0 +OP4 E00CD5 0 +OP4 E00CD6 0 +OP4 E00CD7 0 +OP4 E00CD8 0 +OP4 E00CD9 0 +OP4 E00CDA 0 +OP4 E00CDB 0 +OP4 E00CDC 0 +OP4 E00CDD 0 +OP4 E00CDE 0 +OP4 E00CDF 0 +OP4 E00CE0 0 +OP4 E00CE1 0 +OP4 E00CE2 0 +OP4 E00CE3 0 +OP4 E00CE4 0 +OP4 E00CE5 0 +OP4 E00CE6 0 +OP4 E00CE7 0 +OP4 E00CE8 0 +OP4 E00CE9 0 +OP4 E00CEA 0 +OP4 E00CEB 0 +OP4 E00CEC 0 +OP4 E00CED 0 +OP4 E00CEE 0 +OP4 E00CEF 0 +OP4 E00CF0 0 +OP4 E00CF1 0 +OP4 E00CF2 0 +OP4 E00CF3 0 +OP4 E00CF4 0 +OP4 E00CF5 0 +OP4 E00CF6 0 +OP4 E00CF7 0 +OP4 E00CF8 0 +OP4 E00CF9 0 +OP4 E00CFA 0 +OP4 E00CFB 0 +OP4 E00CFC 0 +OP4 E00CFD 0 +OP4 E00CFE 0 +OP4 E00CFF 0 +OP4 E00D00 0 +OP4 E00D01 0 +OP4 E00D02 0 +OP4 E00D03 0 +OP4 E00D04 0 +OP4 E00D05 0 +OP4 E00D06 0 +OP4 E00D07 0 +OP4 E00D08 0 +OP4 E00D09 0 +OP4 E00D0A 0 +OP4 E00D0B 0 +OP4 E00D0C 0 +OP4 E00D0D 0 +OP4 E00D0E 0 +OP4 E00D0F 0 +OP4 E00D10 0 +OP4 E00D11 0 +OP4 E00D12 0 +OP4 E00D13 0 +OP4 E00D14 0 +OP4 E00D15 0 +OP4 E00D16 0 +OP4 E00D17 0 +OP4 E00D18 0 +OP4 E00D19 0 +OP4 E00D1A 0 +OP4 E00D1B 0 +OP4 E00D1C 0 +OP4 E00D1D 0 +OP4 E00D1E 0 +OP4 E00D1F 0 +OP4 E00D20 0 +OP4 E00D21 0 +OP4 E00D22 0 +OP4 E00D23 0 +OP4 E00D24 0 +OP4 E00D25 0 +OP4 E00D26 0 +OP4 E00D27 0 +OP4 E00D28 0 +OP4 E00D29 0 +OP4 E00D2A 0 +OP4 E00D2B 0 +OP4 E00D2C 0 +OP4 E00D2D 0 +OP4 E00D2E 0 +OP4 E00D2F 0 +OP4 E00D30 0 +OP4 E00D31 0 +OP4 E00D32 0 +OP4 E00D33 0 +OP4 E00D34 0 +OP4 E00D35 0 +OP4 E00D36 0 +OP4 E00D37 0 +OP4 E00D38 0 +OP4 E00D39 0 +OP4 E00D3A 0 +OP4 E00D3B 0 +OP4 E00D3C 0 +OP4 E00D3D 0 +OP4 E00D3E 0 +OP4 E00D3F 0 +OP4 E00D40 0 +OP4 E00D41 0 +OP4 E00D42 0 +OP4 E00D43 0 +OP4 E00D44 0 +OP4 E00D45 0 +OP4 E00D46 0 +OP4 E00D47 0 +OP4 E00D48 0 +OP4 E00D49 0 +OP4 E00D4A 0 +OP4 E00D4B 0 +OP4 E00D4C 0 +OP4 E00D4D 0 +OP4 E00D4E 0 +OP4 E00D4F 0 +OP4 E00D50 0 +OP4 E00D51 0 +OP4 E00D52 0 +OP4 E00D53 0 +OP4 E00D54 0 +OP4 E00D55 0 +OP4 E00D56 0 +OP4 E00D57 0 +OP4 E00D58 0 +OP4 E00D59 0 +OP4 E00D5A 0 +OP4 E00D5B 0 +OP4 E00D5C 0 +OP4 E00D5D 0 +OP4 E00D5E 0 +OP4 E00D5F 0 +OP4 E00D60 0 +OP4 E00D61 0 +OP4 E00D62 0 +OP4 E00D63 0 +OP4 E00D64 0 +OP4 E00D65 0 +OP4 E00D66 0 +OP4 E00D67 0 +OP4 E00D68 0 +OP4 E00D69 0 +OP4 E00D6A 0 +OP4 E00D6B 0 +OP4 E00D6C 0 +OP4 E00D6D 0 +OP4 E00D6E 0 +OP4 E00D6F 0 +OP4 E00D70 0 +OP4 E00D71 0 +OP4 E00D72 0 +OP4 E00D73 0 +OP4 E00D74 0 +OP4 E00D75 0 +OP4 E00D76 0 +OP4 E00D77 0 +OP4 E00D78 0 +OP4 E00D79 0 +OP4 E00D7A 0 +OP4 E00D7B 0 +OP4 E00D7C 0 +OP4 E00D7D 0 +OP4 E00D7E 0 +OP4 E00D7F 0 +OP4 E00D80 0 +OP4 E00D81 0 +OP4 E00D82 0 +OP4 E00D83 0 +OP4 E00D84 0 +OP4 E00D85 0 +OP4 E00D86 0 +OP4 E00D87 0 +OP4 E00D88 0 +OP4 E00D89 0 +OP4 E00D8A 0 +OP4 E00D8B 0 +OP4 E00D8C 0 +OP4 E00D8D 0 +OP4 E00D8E 0 +OP4 E00D8F 0 +OP4 E00D90 0 +OP4 E00D91 0 +OP4 E00D92 0 +OP4 E00D93 0 +OP4 E00D94 0 +OP4 E00D95 0 +OP4 E00D96 0 +OP4 E00D97 0 +OP4 E00D98 0 +OP4 E00D99 0 +OP4 E00D9A 0 +OP4 E00D9B 0 +OP4 E00D9C 0 +OP4 E00D9D 0 +OP4 E00D9E 0 +OP4 E00D9F 0 +OP4 E00DA0 0 +OP4 E00DA1 0 +OP4 E00DA2 0 +OP4 E00DA3 0 +OP4 E00DA4 0 +OP4 E00DA5 0 +OP4 E00DA6 0 +OP4 E00DA7 0 +OP4 E00DA8 0 +OP4 E00DA9 0 +OP4 E00DAA 0 +OP4 E00DAB 0 +OP4 E00DAC 0 +OP4 E00DAD 0 +OP4 E00DAE 0 +OP4 E00DAF 0 +OP4 E00DB0 0 +OP4 E00DB1 0 +OP4 E00DB2 0 +OP4 E00DB3 0 +OP4 E00DB4 0 +OP4 E00DB5 0 +OP4 E00DB6 0 +OP4 E00DB7 0 +OP4 E00DB8 0 +OP4 E00DB9 0 +OP4 E00DBA 0 +OP4 E00DBB 0 +OP4 E00DBC 0 +OP4 E00DBD 0 +OP4 E00DBE 0 +OP4 E00DBF 0 +OP4 E00DC0 0 +OP4 E00DC1 0 +OP4 E00DC2 0 +OP4 E00DC3 0 +OP4 E00DC4 0 +OP4 E00DC5 0 +OP4 E00DC6 0 +OP4 E00DC7 0 +OP4 E00DC8 0 +OP4 E00DC9 0 +OP4 E00DCA 0 +OP4 E00DCB 0 +OP4 E00DCC 0 +OP4 E00DCD 0 +OP4 E00DCE 0 +OP4 E00DCF 0 +OP4 E00DD0 0 +OP4 E00DD1 0 +OP4 E00DD2 0 +OP4 E00DD3 0 +OP4 E00DD4 0 +OP4 E00DD5 0 +OP4 E00DD6 0 +OP4 E00DD7 0 +OP4 E00DD8 0 +OP4 E00DD9 0 +OP4 E00DDA 0 +OP4 E00DDB 0 +OP4 E00DDC 0 +OP4 E00DDD 0 +OP4 E00DDE 0 +OP4 E00DDF 0 +OP4 E00DE0 0 +OP4 E00DE1 0 +OP4 E00DE2 0 +OP4 E00DE3 0 +OP4 E00DE4 0 +OP4 E00DE5 0 +OP4 E00DE6 0 +OP4 E00DE7 0 +OP4 E00DE8 0 +OP4 E00DE9 0 +OP4 E00DEA 0 +OP4 E00DEB 0 +OP4 E00DEC 0 +OP4 E00DED 0 +OP4 E00DEE 0 +OP4 E00DEF 0 +OP4 E00DF0 0 +OP4 E00DF1 0 +OP4 E00DF2 0 +OP4 E00DF3 0 +OP4 E00DF4 0 +OP4 E00DF5 0 +OP4 E00DF6 0 +OP4 E00DF7 0 +OP4 E00DF8 0 +OP4 E00DF9 0 +OP4 E00DFA 0 +OP4 E00DFB 0 +OP4 E00DFC 0 +OP4 E00DFD 0 +OP4 E00DFE 0 +OP4 E00DFF 0 +OP4 E00E00 0 +OP4 E00E01 0 +OP4 E00E02 0 +OP4 E00E03 0 +OP4 E00E04 0 +OP4 E00E05 0 +OP4 E00E06 0 +OP4 E00E07 0 +OP4 E00E08 0 +OP4 E00E09 0 +OP4 E00E0A 0 +OP4 E00E0B 0 +OP4 E00E0C 0 +OP4 E00E0D 0 +OP4 E00E0E 0 +OP4 E00E0F 0 +OP4 E00E10 0 +OP4 E00E11 0 +OP4 E00E12 0 +OP4 E00E13 0 +OP4 E00E14 0 +OP4 E00E15 0 +OP4 E00E16 0 +OP4 E00E17 0 +OP4 E00E18 0 +OP4 E00E19 0 +OP4 E00E1A 0 +OP4 E00E1B 0 +OP4 E00E1C 0 +OP4 E00E1D 0 +OP4 E00E1E 0 +OP4 E00E1F 0 +OP4 E00E20 0 +OP4 E00E21 0 +OP4 E00E22 0 +OP4 E00E23 0 +OP4 E00E24 0 +OP4 E00E25 0 +OP4 E00E26 0 +OP4 E00E27 0 +OP4 E00E28 0 +OP4 E00E29 0 +OP4 E00E2A 0 +OP4 E00E2B 0 +OP4 E00E2C 0 +OP4 E00E2D 0 +OP4 E00E2E 0 +OP4 E00E2F 0 +OP4 E00E30 0 +OP4 E00E31 0 +OP4 E00E32 0 +OP4 E00E33 0 +OP4 E00E34 0 +OP4 E00E35 0 +OP4 E00E36 0 +OP4 E00E37 0 +OP4 E00E38 0 +OP4 E00E39 0 +OP4 E00E3A 0 +OP4 E00E3B 0 +OP4 E00E3C 0 +OP4 E00E3D 0 +OP4 E00E3E 0 +OP4 E00E3F 0 +OP4 E00E40 0 +OP4 E00E41 0 +OP4 E00E42 0 +OP4 E00E43 0 +OP4 E00E44 0 +OP4 E00E45 0 +OP4 E00E46 0 +OP4 E00E47 0 +OP4 E00E48 0 +OP4 E00E49 0 +OP4 E00E4A 0 +OP4 E00E4B 0 +OP4 E00E4C 0 +OP4 E00E4D 0 +OP4 E00E4E 0 +OP4 E00E4F 0 +OP4 E00E50 0 +OP4 E00E51 0 +OP4 E00E52 0 +OP4 E00E53 0 +OP4 E00E54 0 +OP4 E00E55 0 +OP4 E00E56 0 +OP4 E00E57 0 +OP4 E00E58 0 +OP4 E00E59 0 +OP4 E00E5A 0 +OP4 E00E5B 0 +OP4 E00E5C 0 +OP4 E00E5D 0 +OP4 E00E5E 0 +OP4 E00E5F 0 +OP4 E00E60 0 +OP4 E00E61 0 +OP4 E00E62 0 +OP4 E00E63 0 +OP4 E00E64 0 +OP4 E00E65 0 +OP4 E00E66 0 +OP4 E00E67 0 +OP4 E00E68 0 +OP4 E00E69 0 +OP4 E00E6A 0 +OP4 E00E6B 0 +OP4 E00E6C 0 +OP4 E00E6D 0 +OP4 E00E6E 0 +OP4 E00E6F 0 +OP4 E00E70 0 +OP4 E00E71 0 +OP4 E00E72 0 +OP4 E00E73 0 +OP4 E00E74 0 +OP4 E00E75 0 +OP4 E00E76 0 +OP4 E00E77 0 +OP4 E00E78 0 +OP4 E00E79 0 +OP4 E00E7A 0 +OP4 E00E7B 0 +OP4 E00E7C 0 +OP4 E00E7D 0 +OP4 E00E7E 0 +OP4 E00E7F 0 +OP4 E00E80 0 +OP4 E00E81 0 +OP4 E00E82 0 +OP4 E00E83 0 +OP4 E00E84 0 +OP4 E00E85 0 +OP4 E00E86 0 +OP4 E00E87 0 +OP4 E00E88 0 +OP4 E00E89 0 +OP4 E00E8A 0 +OP4 E00E8B 0 +OP4 E00E8C 0 +OP4 E00E8D 0 +OP4 E00E8E 0 +OP4 E00E8F 0 +OP4 E00E90 0 +OP4 E00E91 0 +OP4 E00E92 0 +OP4 E00E93 0 +OP4 E00E94 0 +OP4 E00E95 0 +OP4 E00E96 0 +OP4 E00E97 0 +OP4 E00E98 0 +OP4 E00E99 0 +OP4 E00E9A 0 +OP4 E00E9B 0 +OP4 E00E9C 0 +OP4 E00E9D 0 +OP4 E00E9E 0 +OP4 E00E9F 0 +OP4 E00EA0 0 +OP4 E00EA1 0 +OP4 E00EA2 0 +OP4 E00EA3 0 +OP4 E00EA4 0 +OP4 E00EA5 0 +OP4 E00EA6 0 +OP4 E00EA7 0 +OP4 E00EA8 0 +OP4 E00EA9 0 +OP4 E00EAA 0 +OP4 E00EAB 0 +OP4 E00EAC 0 +OP4 E00EAD 0 +OP4 E00EAE 0 +OP4 E00EAF 0 +OP4 E00EB0 0 +OP4 E00EB1 0 +OP4 E00EB2 0 +OP4 E00EB3 0 +OP4 E00EB4 0 +OP4 E00EB5 0 +OP4 E00EB6 0 +OP4 E00EB7 0 +OP4 E00EB8 0 +OP4 E00EB9 0 +OP4 E00EBA 0 +OP4 E00EBB 0 +OP4 E00EBC 0 +OP4 E00EBD 0 +OP4 E00EBE 0 +OP4 E00EBF 0 +OP4 E00EC0 0 +OP4 E00EC1 0 +OP4 E00EC2 0 +OP4 E00EC3 0 +OP4 E00EC4 0 +OP4 E00EC5 0 +OP4 E00EC6 0 +OP4 E00EC7 0 +OP4 E00EC8 0 +OP4 E00EC9 0 +OP4 E00ECA 0 +OP4 E00ECB 0 +OP4 E00ECC 0 +OP4 E00ECD 0 +OP4 E00ECE 0 +OP4 E00ECF 0 +OP4 E00ED0 0 +OP4 E00ED1 0 +OP4 E00ED2 0 +OP4 E00ED3 0 +OP4 E00ED4 0 +OP4 E00ED5 0 +OP4 E00ED6 0 +OP4 E00ED7 0 +OP4 E00ED8 0 +OP4 E00ED9 0 +OP4 E00EDA 0 +OP4 E00EDB 0 +OP4 E00EDC 0 +OP4 E00EDD 0 +OP4 E00EDE 0 +OP4 E00EDF 0 +OP4 E00EE0 0 +OP4 E00EE1 0 +OP4 E00EE2 0 +OP4 E00EE3 0 +OP4 E00EE4 0 +OP4 E00EE5 0 +OP4 E00EE6 0 +OP4 E00EE7 0 +OP4 E00EE8 0 +OP4 E00EE9 0 +OP4 E00EEA 0 +OP4 E00EEB 0 +OP4 E00EEC 0 +OP4 E00EED 0 +OP4 E00EEE 0 +OP4 E00EEF 0 +OP4 E00EF0 0 +OP4 E00EF1 0 +OP4 E00EF2 0 +OP4 E00EF3 0 +OP4 E00EF4 0 +OP4 E00EF5 0 +OP4 E00EF6 0 +OP4 E00EF7 0 +OP4 E00EF8 0 +OP4 E00EF9 0 +OP4 E00EFA 0 +OP4 E00EFB 0 +OP4 E00EFC 0 +OP4 E00EFD 0 +OP4 E00EFE 0 +OP4 E00EFF 0 +OP4 E00F00 0 +OP4 E00F01 0 +OP4 E00F02 0 +OP4 E00F03 0 +OP4 E00F04 0 +OP4 E00F05 0 +OP4 E00F06 0 +OP4 E00F07 0 +OP4 E00F08 0 +OP4 E00F09 0 +OP4 E00F0A 0 +OP4 E00F0B 0 +OP4 E00F0C 0 +OP4 E00F0D 0 +OP4 E00F0E 0 +OP4 E00F0F 0 +OP4 E00F10 0 +OP4 E00F11 0 +OP4 E00F12 0 +OP4 E00F13 0 +OP4 E00F14 0 +OP4 E00F15 0 +OP4 E00F16 0 +OP4 E00F17 0 +OP4 E00F18 0 +OP4 E00F19 0 +OP4 E00F1A 0 +OP4 E00F1B 0 +OP4 E00F1C 0 +OP4 E00F1D 0 +OP4 E00F1E 0 +OP4 E00F1F 0 +OP4 E00F20 0 +OP4 E00F21 0 +OP4 E00F22 0 +OP4 E00F23 0 +OP4 E00F24 0 +OP4 E00F25 0 +OP4 E00F26 0 +OP4 E00F27 0 +OP4 E00F28 0 +OP4 E00F29 0 +OP4 E00F2A 0 +OP4 E00F2B 0 +OP4 E00F2C 0 +OP4 E00F2D 0 +OP4 E00F2E 0 +OP4 E00F2F 0 +OP4 E00F30 0 +OP4 E00F31 0 +OP4 E00F32 0 +OP4 E00F33 0 +OP4 E00F34 0 +OP4 E00F35 0 +OP4 E00F36 0 +OP4 E00F37 0 +OP4 E00F38 0 +OP4 E00F39 0 +OP4 E00F3A 0 +OP4 E00F3B 0 +OP4 E00F3C 0 +OP4 E00F3D 0 +OP4 E00F3E 0 +OP4 E00F3F 0 +OP4 E00F40 0 +OP4 E00F41 0 +OP4 E00F42 0 +OP4 E00F43 0 +OP4 E00F44 0 +OP4 E00F45 0 +OP4 E00F46 0 +OP4 E00F47 0 +OP4 E00F48 0 +OP4 E00F49 0 +OP4 E00F4A 0 +OP4 E00F4B 0 +OP4 E00F4C 0 +OP4 E00F4D 0 +OP4 E00F4E 0 +OP4 E00F4F 0 +OP4 E00F50 0 +OP4 E00F51 0 +OP4 E00F52 0 +OP4 E00F53 0 +OP4 E00F54 0 +OP4 E00F55 0 +OP4 E00F56 0 +OP4 E00F57 0 +OP4 E00F58 0 +OP4 E00F59 0 +OP4 E00F5A 0 +OP4 E00F5B 0 +OP4 E00F5C 0 +OP4 E00F5D 0 +OP4 E00F5E 0 +OP4 E00F5F 0 +OP4 E00F60 0 +OP4 E00F61 0 +OP4 E00F62 0 +OP4 E00F63 0 +OP4 E00F64 0 +OP4 E00F65 0 +OP4 E00F66 0 +OP4 E00F67 0 +OP4 E00F68 0 +OP4 E00F69 0 +OP4 E00F6A 0 +OP4 E00F6B 0 +OP4 E00F6C 0 +OP4 E00F6D 0 +OP4 E00F6E 0 +OP4 E00F6F 0 +OP4 E00F70 0 +OP4 E00F71 0 +OP4 E00F72 0 +OP4 E00F73 0 +OP4 E00F74 0 +OP4 E00F75 0 +OP4 E00F76 0 +OP4 E00F77 0 +OP4 E00F78 0 +OP4 E00F79 0 +OP4 E00F7A 0 +OP4 E00F7B 0 +OP4 E00F7C 0 +OP4 E00F7D 0 +OP4 E00F7E 0 +OP4 E00F7F 0 +OP4 E00F80 0 +OP4 E00F81 0 +OP4 E00F82 0 +OP4 E00F83 0 +OP4 E00F84 0 +OP4 E00F85 0 +OP4 E00F86 0 +OP4 E00F87 0 +OP4 E00F88 0 +OP4 E00F89 0 +OP4 E00F8A 0 +OP4 E00F8B 0 +OP4 E00F8C 0 +OP4 E00F8D 0 +OP4 E00F8E 0 +OP4 E00F8F 0 +OP4 E00F90 0 +OP4 E00F91 0 +OP4 E00F92 0 +OP4 E00F93 0 +OP4 E00F94 0 +OP4 E00F95 0 +OP4 E00F96 0 +OP4 E00F97 0 +OP4 E00F98 0 +OP4 E00F99 0 +OP4 E00F9A 0 +OP4 E00F9B 0 +OP4 E00F9C 0 +OP4 E00F9D 0 +OP4 E00F9E 0 +OP4 E00F9F 0 +OP4 E00FA0 0 +OP4 E00FA1 0 +OP4 E00FA2 0 +OP4 E00FA3 0 +OP4 E00FA4 0 +OP4 E00FA5 0 +OP4 E00FA6 0 +OP4 E00FA7 0 +OP4 E00FA8 0 +OP4 E00FA9 0 +OP4 E00FAA 0 +OP4 E00FAB 0 +OP4 E00FAC 0 +OP4 E00FAD 0 +OP4 E00FAE 0 +OP4 E00FAF 0 +OP4 E00FB0 0 +OP4 E00FB1 0 +OP4 E00FB2 0 +OP4 E00FB3 0 +OP4 E00FB4 0 +OP4 E00FB5 0 +OP4 E00FB6 0 +OP4 E00FB7 0 +OP4 E00FB8 0 +OP4 E00FB9 0 +OP4 E00FBA 0 +OP4 E00FBB 0 +OP4 E00FBC 0 +OP4 E00FBD 0 +OP4 E00FBE 0 +OP4 E00FBF 0 +OP4 E00FC0 0 +OP4 E00FC1 0 +OP4 E00FC2 0 +OP4 E00FC3 0 +OP4 E00FC4 0 +OP4 E00FC5 0 +OP4 E00FC6 0 +OP4 E00FC7 0 +OP4 E00FC8 0 +OP4 E00FC9 0 +OP4 E00FCA 0 +OP4 E00FCB 0 +OP4 E00FCC 0 +OP4 E00FCD 0 +OP4 E00FCE 0 +OP4 E00FCF 0 +OP4 E00FD0 0 +OP4 E00FD1 0 +OP4 E00FD2 0 +OP4 E00FD3 0 +OP4 E00FD4 0 +OP4 E00FD5 0 +OP4 E00FD6 0 +OP4 E00FD7 0 +OP4 E00FD8 0 +OP4 E00FD9 0 +OP4 E00FDA 0 +OP4 E00FDB 0 +OP4 E00FDC 0 +OP4 E00FDD 0 +OP4 E00FDE 0 +OP4 E00FDF 0 +OP4 E00FE0 0 +OP4 E00FE1 0 +OP4 E00FE2 0 +OP4 E00FE3 0 +OP4 E00FE4 0 +OP4 E00FE5 0 +OP4 E00FE6 0 +OP4 E00FE7 0 +OP4 E00FE8 0 +OP4 E00FE9 0 +OP4 E00FEA 0 +OP4 E00FEB 0 +OP4 E00FEC 0 +OP4 E00FED 0 +OP4 E00FEE 0 +OP4 E00FEF 0 +OP4 E00FF0 0 +OP4 E00FF1 0 +OP4 E00FF2 0 +OP4 E00FF3 0 +OP4 E00FF4 0 +OP4 E00FF5 0 +OP4 E00FF6 0 +OP4 E00FF7 0 +OP4 E00FF8 0 +OP4 E00FF9 0 +OP4 E00FFA 0 +OP4 E00FFB 0 +OP4 E00FFC 0 +OP4 E00FFD 0 +OP4 E00FFE 0 +OP4 E00FFF 0 +OP4 E01000 0 +OP4 E01001 0 +OP4 E01002 0 +OP4 E01003 0 +OP4 E01004 0 +OP4 E01005 0 +OP4 E01006 0 +OP4 E01007 0 +OP4 E01008 0 +OP4 E01009 0 +OP4 E0100A 0 +OP4 E0100B 0 +OP4 E0100C 0 +OP4 E0100D 0 +OP4 E0100E 0 +OP4 E0100F 0 +OP4 E01010 0 +OP4 E01011 0 +OP4 E01012 0 +OP4 E01013 0 +OP4 E01014 0 +OP4 E01015 0 +OP4 E01016 0 +OP4 E01017 0 +OP4 E01018 0 +OP4 E01019 0 +OP4 E0101A 0 +OP4 E0101B 0 +OP4 E0101C 0 +OP4 E0101D 0 +OP4 E0101E 0 +OP4 E0101F 0 +OP4 E01020 0 +OP4 E01021 0 +OP4 E01022 0 +OP4 E01023 0 +OP4 E01024 0 +OP4 E01025 0 +OP4 E01026 0 +OP4 E01027 0 +OP4 E01028 0 +OP4 E01029 0 +OP4 E0102A 0 +OP4 E0102B 0 +OP4 E0102C 0 +OP4 E0102D 0 +OP4 E0102E 0 +OP4 E0102F 0 +OP4 E01030 0 +OP4 E01031 0 +OP4 E01032 0 +OP4 E01033 0 +OP4 E01034 0 +OP4 E01035 0 +OP4 E01036 0 +OP4 E01037 0 +OP4 E01038 0 +OP4 E01039 0 +OP4 E0103A 0 +OP4 E0103B 0 +OP4 E0103C 0 +OP4 E0103D 0 +OP4 E0103E 0 +OP4 E0103F 0 +OP4 E01040 0 +OP4 E01041 0 +OP4 E01042 0 +OP4 E01043 0 +OP4 E01044 0 +OP4 E01045 0 +OP4 E01046 0 +OP4 E01047 0 +OP4 E01048 0 +OP4 E01049 0 +OP4 E0104A 0 +OP4 E0104B 0 +OP4 E0104C 0 +OP4 E0104D 0 +OP4 E0104E 0 +OP4 E0104F 0 +OP4 E01050 0 +OP4 E01051 0 +OP4 E01052 0 +OP4 E01053 0 +OP4 E01054 0 +OP4 E01055 0 +OP4 E01056 0 +OP4 E01057 0 +OP4 E01058 0 +OP4 E01059 0 +OP4 E0105A 0 +OP4 E0105B 0 +OP4 E0105C 0 +OP4 E0105D 0 +OP4 E0105E 0 +OP4 E0105F 0 +OP4 E01060 0 +OP4 E01061 0 +OP4 E01062 0 +OP4 E01063 0 +OP4 E01064 0 +OP4 E01065 0 +OP4 E01066 0 +OP4 E01067 0 +OP4 E01068 0 +OP4 E01069 0 +OP4 E0106A 0 +OP4 E0106B 0 +OP4 E0106C 0 +OP4 E0106D 0 +OP4 E0106E 0 +OP4 E0106F 0 +OP4 E01070 0 +OP4 E01071 0 +OP4 E01072 0 +OP4 E01073 0 +OP4 E01074 0 +OP4 E01075 0 +OP4 E01076 0 +OP4 E01077 0 +OP4 E01078 0 +OP4 E01079 0 +OP4 E0107A 0 +OP4 E0107B 0 +OP4 E0107C 0 +OP4 E0107D 0 +OP4 E0107E 0 +OP4 E0107F 0 +OP4 E01080 0 +OP4 E01081 0 +OP4 E01082 0 +OP4 E01083 0 +OP4 E01084 0 +OP4 E01085 0 +OP4 E01086 0 +OP4 E01087 0 +OP4 E01088 0 +OP4 E01089 0 +OP4 E0108A 0 +OP4 E0108B 0 +OP4 E0108C 0 +OP4 E0108D 0 +OP4 E0108E 0 +OP4 E0108F 0 +OP4 E01090 0 +OP4 E01091 0 +OP4 E01092 0 +OP4 E01093 0 +OP4 E01094 0 +OP4 E01095 0 +OP4 E01096 0 +OP4 E01097 0 +OP4 E01098 0 +OP4 E01099 0 +OP4 E0109A 0 +OP4 E0109B 0 +OP4 E0109C 0 +OP4 E0109D 0 +OP4 E0109E 0 +OP4 E0109F 0 +OP4 E010A0 0 +OP4 E010A1 0 +OP4 E010A2 0 +OP4 E010A3 0 +OP4 E010A4 0 +OP4 E010A5 0 +OP4 E010A6 0 +OP4 E010A7 0 +OP4 E010A8 0 +OP4 E010A9 0 +OP4 E010AA 0 +OP4 E010AB 0 +OP4 E010AC 0 +OP4 E010AD 0 +OP4 E010AE 0 +OP4 E010AF 0 +OP4 E010B0 0 +OP4 E010B1 0 +OP4 E010B2 0 +OP4 E010B3 0 +OP4 E010B4 0 +OP4 E010B5 0 +OP4 E010B6 0 +OP4 E010B7 0 +OP4 E010B8 0 +OP4 E010B9 0 +OP4 E010BA 0 +OP4 E010BB 0 +OP4 E010BC 0 +OP4 E010BD 0 +OP4 E010BE 0 +OP4 E010BF 0 +OP4 E010C0 0 +OP4 E010C1 0 +OP4 E010C2 0 +OP4 E010C3 0 +OP4 E010C4 0 +OP4 E010C5 0 +OP4 E010C6 0 +OP4 E010C7 0 +OP4 E010C8 0 +OP4 E010C9 0 +OP4 E010CA 0 +OP4 E010CB 0 +OP4 E010CC 0 +OP4 E010CD 0 +OP4 E010CE 0 +OP4 E010CF 0 +OP4 E010D0 0 +OP4 E010D1 0 +OP4 E010D2 0 +OP4 E010D3 0 +OP4 E010D4 0 +OP4 E010D5 0 +OP4 E010D6 0 +OP4 E010D7 0 +OP4 E010D8 0 +OP4 E010D9 0 +OP4 E010DA 0 +OP4 E010DB 0 +OP4 E010DC 0 +OP4 E010DD 0 +OP4 E010DE 0 +OP4 E010DF 0 +OP4 E010E0 0 +OP4 E010E1 0 +OP4 E010E2 0 +OP4 E010E3 0 +OP4 E010E4 0 +OP4 E010E5 0 +OP4 E010E6 0 +OP4 E010E7 0 +OP4 E010E8 0 +OP4 E010E9 0 +OP4 E010EA 0 +OP4 E010EB 0 +OP4 E010EC 0 +OP4 E010ED 0 +OP4 E010EE 0 +OP4 E010EF 0 +OP4 E010F0 0 +OP4 E010F1 0 +OP4 E010F2 0 +OP4 E010F3 0 +OP4 E010F4 0 +OP4 E010F5 0 +OP4 E010F6 0 +OP4 E010F7 0 +OP4 E010F8 0 +OP4 E010F9 0 +OP4 E010FA 0 +OP4 E010FB 0 +OP4 E010FC 0 +OP4 E010FD 0 +OP4 E010FE 0 +OP4 E010FF 0 +OP4 E01100 0 +OP4 E01101 0 +OP4 E01102 0 +OP4 E01103 0 +OP4 E01104 0 +OP4 E01105 0 +OP4 E01106 0 +OP4 E01107 0 +OP4 E01108 0 +OP4 E01109 0 +OP4 E0110A 0 +OP4 E0110B 0 +OP4 E0110C 0 +OP4 E0110D 0 +OP4 E0110E 0 +OP4 E0110F 0 +OP4 E01110 0 +OP4 E01111 0 +OP4 E01112 0 +OP4 E01113 0 +OP4 E01114 0 +OP4 E01115 0 +OP4 E01116 0 +OP4 E01117 0 +OP4 E01118 0 +OP4 E01119 0 +OP4 E0111A 0 +OP4 E0111B 0 +OP4 E0111C 0 +OP4 E0111D 0 +OP4 E0111E 0 +OP4 E0111F 0 +OP4 E01120 0 +OP4 E01121 0 +OP4 E01122 0 +OP4 E01123 0 +OP4 E01124 0 +OP4 E01125 0 +OP4 E01126 0 +OP4 E01127 0 +OP4 E01128 0 +OP4 E01129 0 +OP4 E0112A 0 +OP4 E0112B 0 +OP4 E0112C 0 +OP4 E0112D 0 +OP4 E0112E 0 +OP4 E0112F 0 +OP4 E01130 0 +OP4 E01131 0 +OP4 E01132 0 +OP4 E01133 0 +OP4 E01134 0 +OP4 E01135 0 +OP4 E01136 0 +OP4 E01137 0 +OP4 E01138 0 +OP4 E01139 0 +OP4 E0113A 0 +OP4 E0113B 0 +OP4 E0113C 0 +OP4 E0113D 0 +OP4 E0113E 0 +OP4 E0113F 0 +OP4 E01140 0 +OP4 E01141 0 +OP4 E01142 0 +OP4 E01143 0 +OP4 E01144 0 +OP4 E01145 0 +OP4 E01146 0 +OP4 E01147 0 +OP4 E01148 0 +OP4 E01149 0 +OP4 E0114A 0 +OP4 E0114B 0 +OP4 E0114C 0 +OP4 E0114D 0 +OP4 E0114E 0 +OP4 E0114F 0 +OP4 E01150 0 +OP4 E01151 0 +OP4 E01152 0 +OP4 E01153 0 +OP4 E01154 0 +OP4 E01155 0 +OP4 E01156 0 +OP4 E01157 0 +OP4 E01158 0 +OP4 E01159 0 +OP4 E0115A 0 +OP4 E0115B 0 +OP4 E0115C 0 +OP4 E0115D 0 +OP4 E0115E 0 +OP4 E0115F 0 +OP4 E01160 0 +OP4 E01161 0 +OP4 E01162 0 +OP4 E01163 0 +OP4 E01164 0 +OP4 E01165 0 +OP4 E01166 0 +OP4 E01167 0 +OP4 E01168 0 +OP4 E01169 0 +OP4 E0116A 0 +OP4 E0116B 0 +OP4 E0116C 0 +OP4 E0116D 0 +OP4 E0116E 0 +OP4 E0116F 0 +OP4 E01170 0 +OP4 E01171 0 +OP4 E01172 0 +OP4 E01173 0 +OP4 E01174 0 +OP4 E01175 0 +OP4 E01176 0 +OP4 E01177 0 +OP4 E01178 0 +OP4 E01179 0 +OP4 E0117A 0 +OP4 E0117B 0 +OP4 E0117C 0 +OP4 E0117D 0 +OP4 E0117E 0 +OP4 E0117F 0 +OP4 E01180 0 +OP4 E01181 0 +OP4 E01182 0 +OP4 E01183 0 +OP4 E01184 0 +OP4 E01185 0 +OP4 E01186 0 +OP4 E01187 0 +OP4 E01188 0 +OP4 E01189 0 +OP4 E0118A 0 +OP4 E0118B 0 +OP4 E0118C 0 +OP4 E0118D 0 +OP4 E0118E 0 +OP4 E0118F 0 +OP4 E01190 0 +OP4 E01191 0 +OP4 E01192 0 +OP4 E01193 0 +OP4 E01194 0 +OP4 E01195 0 +OP4 E01196 0 +OP4 E01197 0 +OP4 E01198 0 +OP4 E01199 0 +OP4 E0119A 0 +OP4 E0119B 0 +OP4 E0119C 0 +OP4 E0119D 0 +OP4 E0119E 0 +OP4 E0119F 0 +OP4 E011A0 0 +OP4 E011A1 0 +OP4 E011A2 0 +OP4 E011A3 0 +OP4 E011A4 0 +OP4 E011A5 0 +OP4 E011A6 0 +OP4 E011A7 0 +OP4 E011A8 0 +OP4 E011A9 0 +OP4 E011AA 0 +OP4 E011AB 0 +OP4 E011AC 0 +OP4 E011AD 0 +OP4 E011AE 0 +OP4 E011AF 0 +OP4 E011B0 0 +OP4 E011B1 0 +OP4 E011B2 0 +OP4 E011B3 0 +OP4 E011B4 0 +OP4 E011B5 0 +OP4 E011B6 0 +OP4 E011B7 0 +OP4 E011B8 0 +OP4 E011B9 0 +OP4 E011BA 0 +OP4 E011BB 0 +OP4 E011BC 0 +OP4 E011BD 0 +OP4 E011BE 0 +OP4 E011BF 0 +OP4 E011C0 0 +OP4 E011C1 0 +OP4 E011C2 0 +OP4 E011C3 0 +OP4 E011C4 0 +OP4 E011C5 0 +OP4 E011C6 0 +OP4 E011C7 0 +OP4 E011C8 0 +OP4 E011C9 0 +OP4 E011CA 0 +OP4 E011CB 0 +OP4 E011CC 0 +OP4 E011CD 0 +OP4 E011CE 0 +OP4 E011CF 0 +OP4 E011D0 0 +OP4 E011D1 0 +OP4 E011D2 0 +OP4 E011D3 0 +OP4 E011D4 0 +OP4 E011D5 0 +OP4 E011D6 0 +OP4 E011D7 0 +OP4 E011D8 0 +OP4 E011D9 0 +OP4 E011DA 0 +OP4 E011DB 0 +OP4 E011DC 0 +OP4 E011DD 0 +OP4 E011DE 0 +OP4 E011DF 0 +OP4 E011E0 0 +OP4 E011E1 0 +OP4 E011E2 0 +OP4 E011E3 0 +OP4 E011E4 0 +OP4 E011E5 0 +OP4 E011E6 0 +OP4 E011E7 0 +OP4 E011E8 0 +OP4 E011E9 0 +OP4 E011EA 0 +OP4 E011EB 0 +OP4 E011EC 0 +OP4 E011ED 0 +OP4 E011EE 0 +OP4 E011EF 0 +OP4 E011F0 0 +OP4 E011F1 0 +OP4 E011F2 0 +OP4 E011F3 0 +OP4 E011F4 0 +OP4 E011F5 0 +OP4 E011F6 0 +OP4 E011F7 0 +OP4 E011F8 0 +OP4 E011F9 0 +OP4 E011FA 0 +OP4 E011FB 0 +OP4 E011FC 0 +OP4 E011FD 0 +OP4 E011FE 0 +OP4 E011FF 0 +OP4 E01200 0 +OP4 E01201 0 +OP4 E01202 0 +OP4 E01203 0 +OP4 E01204 0 +OP4 E01205 0 +OP4 E01206 0 +OP4 E01207 0 +OP4 E01208 0 +OP4 E01209 0 +OP4 E0120A 0 +OP4 E0120B 0 +OP4 E0120C 0 +OP4 E0120D 0 +OP4 E0120E 0 +OP4 E0120F 0 +OP4 E01210 0 +OP4 E01211 0 +OP4 E01212 0 +OP4 E01213 0 +OP4 E01214 0 +OP4 E01215 0 +OP4 E01216 0 +OP4 E01217 0 +OP4 E01218 0 +OP4 E01219 0 +OP4 E0121A 0 +OP4 E0121B 0 +OP4 E0121C 0 +OP4 E0121D 0 +OP4 E0121E 0 +OP4 E0121F 0 +OP4 E01220 0 +OP4 E01221 0 +OP4 E01222 0 +OP4 E01223 0 +OP4 E01224 0 +OP4 E01225 0 +OP4 E01226 0 +OP4 E01227 0 +OP4 E01228 0 +OP4 E01229 0 +OP4 E0122A 0 +OP4 E0122B 0 +OP4 E0122C 0 +OP4 E0122D 0 +OP4 E0122E 0 +OP4 E0122F 0 +OP4 E01230 0 +OP4 E01231 0 +OP4 E01232 0 +OP4 E01233 0 +OP4 E01234 0 +OP4 E01235 0 +OP4 E01236 0 +OP4 E01237 0 +OP4 E01238 0 +OP4 E01239 0 +OP4 E0123A 0 +OP4 E0123B 0 +OP4 E0123C 0 +OP4 E0123D 0 +OP4 E0123E 0 +OP4 E0123F 0 +OP4 E01240 0 +OP4 E01241 0 +OP4 E01242 0 +OP4 E01243 0 +OP4 E01244 0 +OP4 E01245 0 +OP4 E01246 0 +OP4 E01247 0 +OP4 E01248 0 +OP4 E01249 0 +OP4 E0124A 0 +OP4 E0124B 0 +OP4 E0124C 0 +OP4 E0124D 0 +OP4 E0124E 0 +OP4 E0124F 0 +OP4 E01250 0 +OP4 E01251 0 +OP4 E01252 0 +OP4 E01253 0 +OP4 E01254 0 +OP4 E01255 0 +OP4 E01256 0 +OP4 E01257 0 +OP4 E01258 0 +OP4 E01259 0 +OP4 E0125A 0 +OP4 E0125B 0 +OP4 E0125C 0 +OP4 E0125D 0 +OP4 E0125E 0 +OP4 E0125F 0 +OP4 E01260 0 +OP4 E01261 0 +OP4 E01262 0 +OP4 E01263 0 +OP4 E01264 0 +OP4 E01265 0 +OP4 E01266 0 +OP4 E01267 0 +OP4 E01268 0 +OP4 E01269 0 +OP4 E0126A 0 +OP4 E0126B 0 +OP4 E0126C 0 +OP4 E0126D 0 +OP4 E0126E 0 +OP4 E0126F 0 +OP4 E01270 0 +OP4 E01271 0 +OP4 E01272 0 +OP4 E01273 0 +OP4 E01274 0 +OP4 E01275 0 +OP4 E01276 0 +OP4 E01277 0 +OP4 E01278 0 +OP4 E01279 0 +OP4 E0127A 0 +OP4 E0127B 0 +OP4 E0127C 0 +OP4 E0127D 0 +OP4 E0127E 0 +OP4 E0127F 0 +OP4 E01280 0 +OP4 E01281 0 +OP4 E01282 0 +OP4 E01283 0 +OP4 E01284 0 +OP4 E01285 0 +OP4 E01286 0 +OP4 E01287 0 +OP4 E01288 0 +OP4 E01289 0 +OP4 E0128A 0 +OP4 E0128B 0 +OP4 E0128C 0 +OP4 E0128D 0 +OP4 E0128E 0 +OP4 E0128F 0 +OP4 E01290 0 +OP4 E01291 0 +OP4 E01292 0 +OP4 E01293 0 +OP4 E01294 0 +OP4 E01295 0 +OP4 E01296 0 +OP4 E01297 0 +OP4 E01298 0 +OP4 E01299 0 +OP4 E0129A 0 +OP4 E0129B 0 +OP4 E0129C 0 +OP4 E0129D 0 +OP4 E0129E 0 +OP4 E0129F 0 +OP4 E012A0 0 +OP4 E012A1 0 +OP4 E012A2 0 +OP4 E012A3 0 +OP4 E012A4 0 +OP4 E012A5 0 +OP4 E012A6 0 +OP4 E012A7 0 +OP4 E012A8 0 +OP4 E012A9 0 +OP4 E012AA 0 +OP4 E012AB 0 +OP4 E012AC 0 +OP4 E012AD 0 +OP4 E012AE 0 +OP4 E012AF 0 +OP4 E012B0 0 +OP4 E012B1 0 +OP4 E012B2 0 +OP4 E012B3 0 +OP4 E012B4 0 +OP4 E012B5 0 +OP4 E012B6 0 +OP4 E012B7 0 +OP4 E012B8 0 +OP4 E012B9 0 +OP4 E012BA 0 +OP4 E012BB 0 +OP4 E012BC 0 +OP4 E012BD 0 +OP4 E012BE 0 +OP4 E012BF 0 +OP4 E012C0 0 +OP4 E012C1 0 +OP4 E012C2 0 +OP4 E012C3 0 +OP4 E012C4 0 +OP4 E012C5 0 +OP4 E012C6 0 +OP4 E012C7 0 +OP4 E012C8 0 +OP4 E012C9 0 +OP4 E012CA 0 +OP4 E012CB 0 +OP4 E012CC 0 +OP4 E012CD 0 +OP4 E012CE 0 +OP4 E012CF 0 +OP4 E012D0 0 +OP4 E012D1 0 +OP4 E012D2 0 +OP4 E012D3 0 +OP4 E012D4 0 +OP4 E012D5 0 +OP4 E012D6 0 +OP4 E012D7 0 +OP4 E012D8 0 +OP4 E012D9 0 +OP4 E012DA 0 +OP4 E012DB 0 +OP4 E012DC 0 +OP4 E012DD 0 +OP4 E012DE 0 +OP4 E012DF 0 +OP4 E012E0 0 +OP4 E012E1 0 +OP4 E012E2 0 +OP4 E012E3 0 +OP4 E012E4 0 +OP4 E012E5 0 +OP4 E012E6 0 +OP4 E012E7 0 +OP4 E012E8 0 +OP4 E012E9 0 +OP4 E012EA 0 +OP4 E012EB 0 +OP4 E012EC 0 +OP4 E012ED 0 +OP4 E012EE 0 +OP4 E012EF 0 +OP4 E012F0 0 +OP4 E012F1 0 +OP4 E012F2 0 +OP4 E012F3 0 +OP4 E012F4 0 +OP4 E012F5 0 +OP4 E012F6 0 +OP4 E012F7 0 +OP4 E012F8 0 +OP4 E012F9 0 +OP4 E012FA 0 +OP4 E012FB 0 +OP4 E012FC 0 +OP4 E012FD 0 +OP4 E012FE 0 +OP4 E012FF 0 +OP4 E01300 0 +OP4 E01301 0 +OP4 E01302 0 +OP4 E01303 0 +OP4 E01304 0 +OP4 E01305 0 +OP4 E01306 0 +OP4 E01307 0 +OP4 E01308 0 +OP4 E01309 0 +OP4 E0130A 0 +OP4 E0130B 0 +OP4 E0130C 0 +OP4 E0130D 0 +OP4 E0130E 0 +OP4 E0130F 0 +OP4 E01310 0 +OP4 E01311 0 +OP4 E01312 0 +OP4 E01313 0 +OP4 E01314 0 +OP4 E01315 0 +OP4 E01316 0 +OP4 E01317 0 +OP4 E01318 0 +OP4 E01319 0 +OP4 E0131A 0 +OP4 E0131B 0 +OP4 E0131C 0 +OP4 E0131D 0 +OP4 E0131E 0 +OP4 E0131F 0 +OP4 E01320 0 +OP4 E01321 0 +OP4 E01322 0 +OP4 E01323 0 +OP4 E01324 0 +OP4 E01325 0 +OP4 E01326 0 +OP4 E01327 0 +OP4 E01328 0 +OP4 E01329 0 +OP4 E0132A 0 +OP4 E0132B 0 +OP4 E0132C 0 +OP4 E0132D 0 +OP4 E0132E 0 +OP4 E0132F 0 +OP4 E01330 0 +OP4 E01331 0 +OP4 E01332 0 +OP4 E01333 0 +OP4 E01334 0 +OP4 E01335 0 +OP4 E01336 0 +OP4 E01337 0 +OP4 E01338 0 +OP4 E01339 0 +OP4 E0133A 0 +OP4 E0133B 0 +OP4 E0133C 0 +OP4 E0133D 0 +OP4 E0133E 0 +OP4 E0133F 0 +OP4 E01340 0 +OP4 E01341 0 +OP4 E01342 0 +OP4 E01343 0 +OP4 E01344 0 +OP4 E01345 0 +OP4 E01346 0 +OP4 E01347 0 +OP4 E01348 0 +OP4 E01349 0 +OP4 E0134A 0 +OP4 E0134B 0 +OP4 E0134C 0 +OP4 E0134D 0 +OP4 E0134E 0 +OP4 E0134F 0 +OP4 E01350 0 +OP4 E01351 0 +OP4 E01352 0 +OP4 E01353 0 +OP4 E01354 0 +OP4 E01355 0 +OP4 E01356 0 +OP4 E01357 0 +OP4 E01358 0 +OP4 E01359 0 +OP4 E0135A 0 +OP4 E0135B 0 +OP4 E0135C 0 +OP4 E0135D 0 +OP4 E0135E 0 +OP4 E0135F 0 +OP4 E01360 0 +OP4 E01361 0 +OP4 E01362 0 +OP4 E01363 0 +OP4 E01364 0 +OP4 E01365 0 +OP4 E01366 0 +OP4 E01367 0 +OP4 E01368 0 +OP4 E01369 0 +OP4 E0136A 0 +OP4 E0136B 0 +OP4 E0136C 0 +OP4 E0136D 0 +OP4 E0136E 0 +OP4 E0136F 0 +OP4 E01370 0 +OP4 E01371 0 +OP4 E01372 0 +OP4 E01373 0 +OP4 E01374 0 +OP4 E01375 0 +OP4 E01376 0 +OP4 E01377 0 +OP4 E01378 0 +OP4 E01379 0 +OP4 E0137A 0 +OP4 E0137B 0 +OP4 E0137C 0 +OP4 E0137D 0 +OP4 E0137E 0 +OP4 E0137F 0 +OP4 E01380 0 +OP4 E01381 0 +OP4 E01382 0 +OP4 E01383 0 +OP4 E01384 0 +OP4 E01385 0 +OP4 E01386 0 +OP4 E01387 0 +OP4 E01388 0 +OP4 E01389 0 +OP4 E0138A 0 +OP4 E0138B 0 +OP4 E0138C 0 +OP4 E0138D 0 +OP4 E0138E 0 +OP4 E0138F 0 +OP4 E01390 0 +OP4 E01391 0 +OP4 E01392 0 +OP4 E01393 0 +OP4 E01394 0 +OP4 E01395 0 +OP4 E01396 0 +OP4 E01397 0 +OP4 E01398 0 +OP4 E01399 0 +OP4 E0139A 0 +OP4 E0139B 0 +OP4 E0139C 0 +OP4 E0139D 0 +OP4 E0139E 0 +OP4 E0139F 0 +OP4 E013A0 0 +OP4 E013A1 0 +OP4 E013A2 0 +OP4 E013A3 0 +OP4 E013A4 0 +OP4 E013A5 0 +OP4 E013A6 0 +OP4 E013A7 0 +OP4 E013A8 0 +OP4 E013A9 0 +OP4 E013AA 0 +OP4 E013AB 0 +OP4 E013AC 0 +OP4 E013AD 0 +OP4 E013AE 0 +OP4 E013AF 0 +OP4 E013B0 0 +OP4 E013B1 0 +OP4 E013B2 0 +OP4 E013B3 0 +OP4 E013B4 0 +OP4 E013B5 0 +OP4 E013B6 0 +OP4 E013B7 0 +OP4 E013B8 0 +OP4 E013B9 0 +OP4 E013BA 0 +OP4 E013BB 0 +OP4 E013BC 0 +OP4 E013BD 0 +OP4 E013BE 0 +OP4 E013BF 0 +OP4 E013C0 0 +OP4 E013C1 0 +OP4 E013C2 0 +OP4 E013C3 0 +OP4 E013C4 0 +OP4 E013C5 0 +OP4 E013C6 0 +OP4 E013C7 0 +OP4 E013C8 0 +OP4 E013C9 0 +OP4 E013CA 0 +OP4 E013CB 0 +OP4 E013CC 0 +OP4 E013CD 0 +OP4 E013CE 0 +OP4 E013CF 0 +OP4 E013D0 0 +OP4 E013D1 0 +OP4 E013D2 0 +OP4 E013D3 0 +OP4 E013D4 0 +OP4 E013D5 0 +OP4 E013D6 0 +OP4 E013D7 0 +OP4 E013D8 0 +OP4 E013D9 0 +OP4 E013DA 0 +OP4 E013DB 0 +OP4 E013DC 0 +OP4 E013DD 0 +OP4 E013DE 0 +OP4 E013DF 0 +OP4 E013E0 0 +OP4 E013E1 0 +OP4 E013E2 0 +OP4 E013E3 0 +OP4 E013E4 0 +OP4 E013E5 0 +OP4 E013E6 0 +OP4 E013E7 0 +OP4 E013E8 0 +OP4 E013E9 0 +OP4 E013EA 0 +OP4 E013EB 0 +OP4 E013EC 0 +OP4 E013ED 0 +OP4 E013EE 0 +OP4 E013EF 0 +OP4 E013F0 0 +OP4 E013F1 0 +OP4 E013F2 0 +OP4 E013F3 0 +OP4 E013F4 0 +OP4 E013F5 0 +OP4 E013F6 0 +OP4 E013F7 0 +OP4 E013F8 0 +OP4 E013F9 0 +OP4 E013FA 0 +OP4 E013FB 0 +OP4 E013FC 0 +OP4 E013FD 0 +OP4 E013FE 0 +OP4 E013FF 0 +OP4 E01400 0 +OP4 E01401 0 +OP4 E01402 0 +OP4 E01403 0 +OP4 E01404 0 +OP4 E01405 0 +OP4 E01406 0 +OP4 E01407 0 +OP4 E01408 0 +OP4 E01409 0 +OP4 E0140A 0 +OP4 E0140B 0 +OP4 E0140C 0 +OP4 E0140D 0 +OP4 E0140E 0 +OP4 E0140F 0 +OP4 E01410 0 +OP4 E01411 0 +OP4 E01412 0 +OP4 E01413 0 +OP4 E01414 0 +OP4 E01415 0 +OP4 E01416 0 +OP4 E01417 0 +OP4 E01418 0 +OP4 E01419 0 +OP4 E0141A 0 +OP4 E0141B 0 +OP4 E0141C 0 +OP4 E0141D 0 +OP4 E0141E 0 +OP4 E0141F 0 +OP4 E01420 0 +OP4 E01421 0 +OP4 E01422 0 +OP4 E01423 0 +OP4 E01424 0 +OP4 E01425 0 +OP4 E01426 0 +OP4 E01427 0 +OP4 E01428 0 +OP4 E01429 0 +OP4 E0142A 0 +OP4 E0142B 0 +OP4 E0142C 0 +OP4 E0142D 0 +OP4 E0142E 0 +OP4 E0142F 0 +OP4 E01430 0 +OP4 E01431 0 +OP4 E01432 0 +OP4 E01433 0 +OP4 E01434 0 +OP4 E01435 0 +OP4 E01436 0 +OP4 E01437 0 +OP4 E01438 0 +OP4 E01439 0 +OP4 E0143A 0 +OP4 E0143B 0 +OP4 E0143C 0 +OP4 E0143D 0 +OP4 E0143E 0 +OP4 E0143F 0 +OP4 E01440 0 +OP4 E01441 0 +OP4 E01442 0 +OP4 E01443 0 +OP4 E01444 0 +OP4 E01445 0 +OP4 E01446 0 +OP4 E01447 0 +OP4 E01448 0 +OP4 E01449 0 +OP4 E0144A 0 +OP4 E0144B 0 +OP4 E0144C 0 +OP4 E0144D 0 +OP4 E0144E 0 +OP4 E0144F 0 +OP4 E01450 0 +OP4 E01451 0 +OP4 E01452 0 +OP4 E01453 0 +OP4 E01454 0 +OP4 E01455 0 +OP4 E01456 0 +OP4 E01457 0 +OP4 E01458 0 +OP4 E01459 0 +OP4 E0145A 0 +OP4 E0145B 0 +OP4 E0145C 0 +OP4 E0145D 0 +OP4 E0145E 0 +OP4 E0145F 0 +OP4 E01460 0 +OP4 E01461 0 +OP4 E01462 0 +OP4 E01463 0 +OP4 E01464 0 +OP4 E01465 0 +OP4 E01466 0 +OP4 E01467 0 +OP4 E01468 0 +OP4 E01469 0 +OP4 E0146A 0 +OP4 E0146B 0 +OP4 E0146C 0 +OP4 E0146D 0 +OP4 E0146E 0 +OP4 E0146F 0 +OP4 E01470 0 +OP4 E01471 0 +OP4 E01472 0 +OP4 E01473 0 +OP4 E01474 0 +OP4 E01475 0 +OP4 E01476 0 +OP4 E01477 0 +OP4 E01478 0 +OP4 E01479 0 +OP4 E0147A 0 +OP4 E0147B 0 +OP4 E0147C 0 +OP4 E0147D 0 +OP4 E0147E 0 +OP4 E0147F 0 +OP4 E01480 0 +OP4 E01481 0 +OP4 E01482 0 +OP4 E01483 0 +OP4 E01484 0 +OP4 E01485 0 +OP4 E01486 0 +OP4 E01487 0 +OP4 E01488 0 +OP4 E01489 0 +OP4 E0148A 0 +OP4 E0148B 0 +OP4 E0148C 0 +OP4 E0148D 0 +OP4 E0148E 0 +OP4 E0148F 0 +OP4 E01490 0 +OP4 E01491 0 +OP4 E01492 0 +OP4 E01493 0 +OP4 E01494 0 +OP4 E01495 0 +OP4 E01496 0 +OP4 E01497 0 +OP4 E01498 0 +OP4 E01499 0 +OP4 E0149A 0 +OP4 E0149B 0 +OP4 E0149C 0 +OP4 E0149D 0 +OP4 E0149E 0 +OP4 E0149F 0 +OP4 E014A0 0 +OP4 E014A1 0 +OP4 E014A2 0 +OP4 E014A3 0 +OP4 E014A4 0 +OP4 E014A5 0 +OP4 E014A6 0 +OP4 E014A7 0 +OP4 E014A8 0 +OP4 E014A9 0 +OP4 E014AA 0 +OP4 E014AB 0 +OP4 E014AC 0 +OP4 E014AD 0 +OP4 E014AE 0 +OP4 E014AF 0 +OP4 E014B0 0 +OP4 E014B1 0 +OP4 E014B2 0 +OP4 E014B3 0 +OP4 E014B4 0 +OP4 E014B5 0 +OP4 E014B6 0 +OP4 E014B7 0 +OP4 E014B8 0 +OP4 E014B9 0 +OP4 E014BA 0 +OP4 E014BB 0 +OP4 E014BC 0 +OP4 E014BD 0 +OP4 E014BE 0 +OP4 E014BF 0 +OP4 E014C0 0 +OP4 E014C1 0 +OP4 E014C2 0 +OP4 E014C3 0 +OP4 E014C4 0 +OP4 E014C5 0 +OP4 E014C6 0 +OP4 E014C7 0 +OP4 E014C8 0 +OP4 E014C9 0 +OP4 E014CA 0 +OP4 E014CB 0 +OP4 E014CC 0 +OP4 E014CD 0 +OP4 E014CE 0 +OP4 E014CF 0 +OP4 E014D0 0 +OP4 E014D1 0 +OP4 E014D2 0 +OP4 E014D3 0 +OP4 E014D4 0 +OP4 E014D5 0 +OP4 E014D6 0 +OP4 E014D7 0 +OP4 E014D8 0 +OP4 E014D9 0 +OP4 E014DA 0 +OP4 E014DB 0 +OP4 E014DC 0 +OP4 E014DD 0 +OP4 E014DE 0 +OP4 E014DF 0 +OP4 E014E0 0 +OP4 E014E1 0 +OP4 E014E2 0 +OP4 E014E3 0 +OP4 E014E4 0 +OP4 E014E5 0 +OP4 E014E6 0 +OP4 E014E7 0 +OP4 E014E8 0 +OP4 E014E9 0 +OP4 E014EA 0 +OP4 E014EB 0 +OP4 E014EC 0 +OP4 E014ED 0 +OP4 E014EE 0 +OP4 E014EF 0 +OP4 E014F0 0 +OP4 E014F1 0 +OP4 E014F2 0 +OP4 E014F3 0 +OP4 E014F4 0 +OP4 E014F5 0 +OP4 E014F6 0 +OP4 E014F7 0 +OP4 E014F8 0 +OP4 E014F9 0 +OP4 E014FA 0 +OP4 E014FB 0 +OP4 E014FC 0 +OP4 E014FD 0 +OP4 E014FE 0 +OP4 E014FF 0 +OP4 E01500 0 +OP4 E01501 0 +OP4 E01502 0 +OP4 E01503 0 +OP4 E01504 0 +OP4 E01505 0 +OP4 E01506 0 +OP4 E01507 0 +OP4 E01508 0 +OP4 E01509 0 +OP4 E0150A 0 +OP4 E0150B 0 +OP4 E0150C 0 +OP4 E0150D 0 +OP4 E0150E 0 +OP4 E0150F 0 +OP4 E01510 0 +OP4 E01511 0 +OP4 E01512 0 +OP4 E01513 0 +OP4 E01514 0 +OP4 E01515 0 +OP4 E01516 0 +OP4 E01517 0 +OP4 E01518 0 +OP4 E01519 0 +OP4 E0151A 0 +OP4 E0151B 0 +OP4 E0151C 0 +OP4 E0151D 0 +OP4 E0151E 0 +OP4 E0151F 0 +OP4 E01520 0 +OP4 E01521 0 +OP4 E01522 0 +OP4 E01523 0 +OP4 E01524 0 +OP4 E01525 0 +OP4 E01526 0 +OP4 E01527 0 +OP4 E01528 0 +OP4 E01529 0 +OP4 E0152A 0 +OP4 E0152B 0 +OP4 E0152C 0 +OP4 E0152D 0 +OP4 E0152E 0 +OP4 E0152F 0 +OP4 E01530 0 +OP4 E01531 0 +OP4 E01532 0 +OP4 E01533 0 +OP4 E01534 0 +OP4 E01535 0 +OP4 E01536 0 +OP4 E01537 0 +OP4 E01538 0 +OP4 E01539 0 +OP4 E0153A 0 +OP4 E0153B 0 +OP4 E0153C 0 +OP4 E0153D 0 +OP4 E0153E 0 +OP4 E0153F 0 +OP4 E01540 0 +OP4 E01541 0 +OP4 E01542 0 +OP4 E01543 0 +OP4 E01544 0 +OP4 E01545 0 +OP4 E01546 0 +OP4 E01547 0 +OP4 E01548 0 +OP4 E01549 0 +OP4 E0154A 0 +OP4 E0154B 0 +OP4 E0154C 0 +OP4 E0154D 0 +OP4 E0154E 0 +OP4 E0154F 0 +OP4 E01550 0 +OP4 E01551 0 +OP4 E01552 0 +OP4 E01553 0 +OP4 E01554 0 +OP4 E01555 0 +OP4 E01556 0 +OP4 E01557 0 +OP4 E01558 0 +OP4 E01559 0 +OP4 E0155A 0 +OP4 E0155B 0 +OP4 E0155C 0 +OP4 E0155D 0 +OP4 E0155E 0 +OP4 E0155F 0 +OP4 E01560 0 +OP4 E01561 0 +OP4 E01562 0 +OP4 E01563 0 +OP4 E01564 0 +OP4 E01565 0 +OP4 E01566 0 +OP4 E01567 0 +OP4 E01568 0 +OP4 E01569 0 +OP4 E0156A 0 +OP4 E0156B 0 +OP4 E0156C 0 +OP4 E0156D 0 +OP4 E0156E 0 +OP4 E0156F 0 +OP4 E01570 0 +OP4 E01571 0 +OP4 E01572 0 +OP4 E01573 0 +OP4 E01574 0 +OP4 E01575 0 +OP4 E01576 0 +OP4 E01577 0 +OP4 E01578 0 +OP4 E01579 0 +OP4 E0157A 0 +OP4 E0157B 0 +OP4 E0157C 0 +OP4 E0157D 0 +OP4 E0157E 0 +OP4 E0157F 0 +OP4 E01580 0 +OP4 E01581 0 +OP4 E01582 0 +OP4 E01583 0 +OP4 E01584 0 +OP4 E01585 0 +OP4 E01586 0 +OP4 E01587 0 +OP4 E01588 0 +OP4 E01589 0 +OP4 E0158A 0 +OP4 E0158B 0 +OP4 E0158C 0 +OP4 E0158D 0 +OP4 E0158E 0 +OP4 E0158F 0 +OP4 E01590 0 +OP4 E01591 0 +OP4 E01592 0 +OP4 E01593 0 +OP4 E01594 0 +OP4 E01595 0 +OP4 E01596 0 +OP4 E01597 0 +OP4 E01598 0 +OP4 E01599 0 +OP4 E0159A 0 +OP4 E0159B 0 +OP4 E0159C 0 +OP4 E0159D 0 +OP4 E0159E 0 +OP4 E0159F 0 +OP4 E015A0 0 +OP4 E015A1 0 +OP4 E015A2 0 +OP4 E015A3 0 +OP4 E015A4 0 +OP4 E015A5 0 +OP4 E015A6 0 +OP4 E015A7 0 +OP4 E015A8 0 +OP4 E015A9 0 +OP4 E015AA 0 +OP4 E015AB 0 +OP4 E015AC 0 +OP4 E015AD 0 +OP4 E015AE 0 +OP4 E015AF 0 +OP4 E015B0 0 +OP4 E015B1 0 +OP4 E015B2 0 +OP4 E015B3 0 +OP4 E015B4 0 +OP4 E015B5 0 +OP4 E015B6 0 +OP4 E015B7 0 +OP4 E015B8 0 +OP4 E015B9 0 +OP4 E015BA 0 +OP4 E015BB 0 +OP4 E015BC 0 +OP4 E015BD 0 +OP4 E015BE 0 +OP4 E015BF 0 +OP4 E015C0 0 +OP4 E015C1 0 +OP4 E015C2 0 +OP4 E015C3 0 +OP4 E015C4 0 +OP4 E015C5 0 +OP4 E015C6 0 +OP4 E015C7 0 +OP4 E015C8 0 +OP4 E015C9 0 +OP4 E015CA 0 +OP4 E015CB 0 +OP4 E015CC 0 +OP4 E015CD 0 +OP4 E015CE 0 +OP4 E015CF 0 +OP4 E015D0 0 +OP4 E015D1 0 +OP4 E015D2 0 +OP4 E015D3 0 +OP4 E015D4 0 +OP4 E015D5 0 +OP4 E015D6 0 +OP4 E015D7 0 +OP4 E015D8 0 +OP4 E015D9 0 +OP4 E015DA 0 +OP4 E015DB 0 +OP4 E015DC 0 +OP4 E015DD 0 +OP4 E015DE 0 +OP4 E015DF 0 +OP4 E015E0 0 +OP4 E015E1 0 +OP4 E015E2 0 +OP4 E015E3 0 +OP4 E015E4 0 +OP4 E015E5 0 +OP4 E015E6 0 +OP4 E015E7 0 +OP4 E015E8 0 +OP4 E015E9 0 +OP4 E015EA 0 +OP4 E015EB 0 +OP4 E015EC 0 +OP4 E015ED 0 +OP4 E015EE 0 +OP4 E015EF 0 +OP4 E015F0 0 +OP4 E015F1 0 +OP4 E015F2 0 +OP4 E015F3 0 +OP4 E015F4 0 +OP4 E015F5 0 +OP4 E015F6 0 +OP4 E015F7 0 +OP4 E015F8 0 +OP4 E015F9 0 +OP4 E015FA 0 +OP4 E015FB 0 +OP4 E015FC 0 +OP4 E015FD 0 +OP4 E015FE 0 +OP4 E015FF 0 +OP4 E01600 0 +OP4 E01601 0 +OP4 E01602 0 +OP4 E01603 0 +OP4 E01604 0 +OP4 E01605 0 +OP4 E01606 0 +OP4 E01607 0 +OP4 E01608 0 +OP4 E01609 0 +OP4 E0160A 0 +OP4 E0160B 0 +OP4 E0160C 0 +OP4 E0160D 0 +OP4 E0160E 0 +OP4 E0160F 0 +OP4 E01610 0 +OP4 E01611 0 +OP4 E01612 0 +OP4 E01613 0 +OP4 E01614 0 +OP4 E01615 0 +OP4 E01616 0 +OP4 E01617 0 +OP4 E01618 0 +OP4 E01619 0 +OP4 E0161A 0 +OP4 E0161B 0 +OP4 E0161C 0 +OP4 E0161D 0 +OP4 E0161E 0 +OP4 E0161F 0 +OP4 E01620 0 +OP4 E01621 0 +OP4 E01622 0 +OP4 E01623 0 +OP4 E01624 0 +OP4 E01625 0 +OP4 E01626 0 +OP4 E01627 0 +OP4 E01628 0 +OP4 E01629 0 +OP4 E0162A 0 +OP4 E0162B 0 +OP4 E0162C 0 +OP4 E0162D 0 +OP4 E0162E 0 +OP4 E0162F 0 +OP4 E01630 0 +OP4 E01631 0 +OP4 E01632 0 +OP4 E01633 0 +OP4 E01634 0 +OP4 E01635 0 +OP4 E01636 0 +OP4 E01637 0 +OP4 E01638 0 +OP4 E01639 0 +OP4 E0163A 0 +OP4 E0163B 0 +OP4 E0163C 0 +OP4 E0163D 0 +OP4 E0163E 0 +OP4 E0163F 0 +OP4 E01640 0 +OP4 E01641 0 +OP4 E01642 0 +OP4 E01643 0 +OP4 E01644 0 +OP4 E01645 0 +OP4 E01646 0 +OP4 E01647 0 +OP4 E01648 0 +OP4 E01649 0 +OP4 E0164A 0 +OP4 E0164B 0 +OP4 E0164C 0 +OP4 E0164D 0 +OP4 E0164E 0 +OP4 E0164F 0 +OP4 E01650 0 +OP4 E01651 0 +OP4 E01652 0 +OP4 E01653 0 +OP4 E01654 0 +OP4 E01655 0 +OP4 E01656 0 +OP4 E01657 0 +OP4 E01658 0 +OP4 E01659 0 +OP4 E0165A 0 +OP4 E0165B 0 +OP4 E0165C 0 +OP4 E0165D 0 +OP4 E0165E 0 +OP4 E0165F 0 +OP4 E01660 0 +OP4 E01661 0 +OP4 E01662 0 +OP4 E01663 0 +OP4 E01664 0 +OP4 E01665 0 +OP4 E01666 0 +OP4 E01667 0 +OP4 E01668 0 +OP4 E01669 0 +OP4 E0166A 0 +OP4 E0166B 0 +OP4 E0166C 0 +OP4 E0166D 0 +OP4 E0166E 0 +OP4 E0166F 0 +OP4 E01670 0 +OP4 E01671 0 +OP4 E01672 0 +OP4 E01673 0 +OP4 E01674 0 +OP4 E01675 0 +OP4 E01676 0 +OP4 E01677 0 +OP4 E01678 0 +OP4 E01679 0 +OP4 E0167A 0 +OP4 E0167B 0 +OP4 E0167C 0 +OP4 E0167D 0 +OP4 E0167E 0 +OP4 E0167F 0 +OP4 E01680 0 +OP4 E01681 0 +OP4 E01682 0 +OP4 E01683 0 +OP4 E01684 0 +OP4 E01685 0 +OP4 E01686 0 +OP4 E01687 0 +OP4 E01688 0 +OP4 E01689 0 +OP4 E0168A 0 +OP4 E0168B 0 +OP4 E0168C 0 +OP4 E0168D 0 +OP4 E0168E 0 +OP4 E0168F 0 +OP4 E01690 0 +OP4 E01691 0 +OP4 E01692 0 +OP4 E01693 0 +OP4 E01694 0 +OP4 E01695 0 +OP4 E01696 0 +OP4 E01697 0 +OP4 E01698 0 +OP4 E01699 0 +OP4 E0169A 0 +OP4 E0169B 0 +OP4 E0169C 0 +OP4 E0169D 0 +OP4 E0169E 0 +OP4 E0169F 0 +OP4 E016A0 0 +OP4 E016A1 0 +OP4 E016A2 0 +OP4 E016A3 0 +OP4 E016A4 0 +OP4 E016A5 0 +OP4 E016A6 0 +OP4 E016A7 0 +OP4 E016A8 0 +OP4 E016A9 0 +OP4 E016AA 0 +OP4 E016AB 0 +OP4 E016AC 0 +OP4 E016AD 0 +OP4 E016AE 0 +OP4 E016AF 0 +OP4 E016B0 0 +OP4 E016B1 0 +OP4 E016B2 0 +OP4 E016B3 0 +OP4 E016B4 0 +OP4 E016B5 0 +OP4 E016B6 0 +OP4 E016B7 0 +OP4 E016B8 0 +OP4 E016B9 0 +OP4 E016BA 0 +OP4 E016BB 0 +OP4 E016BC 0 +OP4 E016BD 0 +OP4 E016BE 0 +OP4 E016BF 0 +OP4 E016C0 0 +OP4 E016C1 0 +OP4 E016C2 0 +OP4 E016C3 0 +OP4 E016C4 0 +OP4 E016C5 0 +OP4 E016C6 0 +OP4 E016C7 0 +OP4 E016C8 0 +OP4 E016C9 0 +OP4 E016CA 0 +OP4 E016CB 0 +OP4 E016CC 0 +OP4 E016CD 0 +OP4 E016CE 0 +OP4 E016CF 0 +OP4 E016D0 0 +OP4 E016D1 0 +OP4 E016D2 0 +OP4 E016D3 0 +OP4 E016D4 0 +OP4 E016D5 0 +OP4 E016D6 0 +OP4 E016D7 0 +OP4 E016D8 0 +OP4 E016D9 0 +OP4 E016DA 0 +OP4 E016DB 0 +OP4 E016DC 0 +OP4 E016DD 0 +OP4 E016DE 0 +OP4 E016DF 0 +OP4 E016E0 0 +OP4 E016E1 0 +OP4 E016E2 0 +OP4 E016E3 0 +OP4 E016E4 0 +OP4 E016E5 0 +OP4 E016E6 0 +OP4 E016E7 0 +OP4 E016E8 0 +OP4 E016E9 0 +OP4 E016EA 0 +OP4 E016EB 0 +OP4 E016EC 0 +OP4 E016ED 0 +OP4 E016EE 0 +OP4 E016EF 0 +OP4 E016F0 0 +OP4 E016F1 0 +OP4 E016F2 0 +OP4 E016F3 0 +OP4 E016F4 0 +OP4 E016F5 0 +OP4 E016F6 0 +OP4 E016F7 0 +OP4 E016F8 0 +OP4 E016F9 0 +OP4 E016FA 0 +OP4 E016FB 0 +OP4 E016FC 0 +OP4 E016FD 0 +OP4 E016FE 0 +OP4 E016FF 0 +OP4 E01700 0 +OP4 E01701 0 +OP4 E01702 0 +OP4 E01703 0 +OP4 E01704 0 +OP4 E01705 0 +OP4 E01706 0 +OP4 E01707 0 +OP4 E01708 0 +OP4 E01709 0 +OP4 E0170A 0 +OP4 E0170B 0 +OP4 E0170C 0 +OP4 E0170D 0 +OP4 E0170E 0 +OP4 E0170F 0 +OP4 E01710 0 +OP4 E01711 0 +OP4 E01712 0 +OP4 E01713 0 +OP4 E01714 0 +OP4 E01715 0 +OP4 E01716 0 +OP4 E01717 0 +OP4 E01718 0 +OP4 E01719 0 +OP4 E0171A 0 +OP4 E0171B 0 +OP4 E0171C 0 +OP4 E0171D 0 +OP4 E0171E 0 +OP4 E0171F 0 +OP4 E01720 0 +OP4 E01721 0 +OP4 E01722 0 +OP4 E01723 0 +OP4 E01724 0 +OP4 E01725 0 +OP4 E01726 0 +OP4 E01727 0 +OP4 E01728 0 +OP4 E01729 0 +OP4 E0172A 0 +OP4 E0172B 0 +OP4 E0172C 0 +OP4 E0172D 0 +OP4 E0172E 0 +OP4 E0172F 0 +OP4 E01730 0 +OP4 E01731 0 +OP4 E01732 0 +OP4 E01733 0 +OP4 E01734 0 +OP4 E01735 0 +OP4 E01736 0 +OP4 E01737 0 +OP4 E01738 0 +OP4 E01739 0 +OP4 E0173A 0 +OP4 E0173B 0 +OP4 E0173C 0 +OP4 E0173D 0 +OP4 E0173E 0 +OP4 E0173F 0 +OP4 E01740 0 +OP4 E01741 0 +OP4 E01742 0 +OP4 E01743 0 +OP4 E01744 0 +OP4 E01745 0 +OP4 E01746 0 +OP4 E01747 0 +OP4 E01748 0 +OP4 E01749 0 +OP4 E0174A 0 +OP4 E0174B 0 +OP4 E0174C 0 +OP4 E0174D 0 +OP4 E0174E 0 +OP4 E0174F 0 +OP4 E01750 0 +OP4 E01751 0 +OP4 E01752 0 +OP4 E01753 0 +OP4 E01754 0 +OP4 E01755 0 +OP4 E01756 0 +OP4 E01757 0 +OP4 E01758 0 +OP4 E01759 0 +OP4 E0175A 0 +OP4 E0175B 0 +OP4 E0175C 0 +OP4 E0175D 0 +OP4 E0175E 0 +OP4 E0175F 0 +OP4 E01760 0 +OP4 E01761 0 +OP4 E01762 0 +OP4 E01763 0 +OP4 E01764 0 +OP4 E01765 0 +OP4 E01766 0 +OP4 E01767 0 +OP4 E01768 0 +OP4 E01769 0 +OP4 E0176A 0 +OP4 E0176B 0 +OP4 E0176C 0 +OP4 E0176D 0 +OP4 E0176E 0 +OP4 E0176F 0 +OP4 E01770 0 +OP4 E01771 0 +OP4 E01772 0 +OP4 E01773 0 +OP4 E01774 0 +OP4 E01775 0 +OP4 E01776 0 +OP4 E01777 0 +OP4 E01778 0 +OP4 E01779 0 +OP4 E0177A 0 +OP4 E0177B 0 +OP4 E0177C 0 +OP4 E0177D 0 +OP4 E0177E 0 +OP4 E0177F 0 +OP4 E01780 0 +OP4 E01781 0 +OP4 E01782 0 +OP4 E01783 0 +OP4 E01784 0 +OP4 E01785 0 +OP4 E01786 0 +OP4 E01787 0 +OP4 E01788 0 +OP4 E01789 0 +OP4 E0178A 0 +OP4 E0178B 0 +OP4 E0178C 0 +OP4 E0178D 0 +OP4 E0178E 0 +OP4 E0178F 0 +OP4 E01790 0 +OP4 E01791 0 +OP4 E01792 0 +OP4 E01793 0 +OP4 E01794 0 +OP4 E01795 0 +OP4 E01796 0 +OP4 E01797 0 +OP4 E01798 0 +OP4 E01799 0 +OP4 E0179A 0 +OP4 E0179B 0 +OP4 E0179C 0 +OP4 E0179D 0 +OP4 E0179E 0 +OP4 E0179F 0 +OP4 E017A0 0 +OP4 E017A1 0 +OP4 E017A2 0 +OP4 E017A3 0 +OP4 E017A4 0 +OP4 E017A5 0 +OP4 E017A6 0 +OP4 E017A7 0 +OP4 E017A8 0 +OP4 E017A9 0 +OP4 E017AA 0 +OP4 E017AB 0 +OP4 E017AC 0 +OP4 E017AD 0 +OP4 E017AE 0 +OP4 E017AF 0 +OP4 E017B0 0 +OP4 E017B1 0 +OP4 E017B2 0 +OP4 E017B3 0 +OP4 E017B4 0 +OP4 E017B5 0 +OP4 E017B6 0 +OP4 E017B7 0 +OP4 E017B8 0 +OP4 E017B9 0 +OP4 E017BA 0 +OP4 E017BB 0 +OP4 E017BC 0 +OP4 E017BD 0 +OP4 E017BE 0 +OP4 E017BF 0 +OP4 E017C0 0 +OP4 E017C1 0 +OP4 E017C2 0 +OP4 E017C3 0 +OP4 E017C4 0 +OP4 E017C5 0 +OP4 E017C6 0 +OP4 E017C7 0 +OP4 E017C8 0 +OP4 E017C9 0 +OP4 E017CA 0 +OP4 E017CB 0 +OP4 E017CC 0 +OP4 E017CD 0 +OP4 E017CE 0 +OP4 E017CF 0 +OP4 E017D0 0 +OP4 E017D1 0 +OP4 E017D2 0 +OP4 E017D3 0 +OP4 E017D4 0 +OP4 E017D5 0 +OP4 E017D6 0 +OP4 E017D7 0 +OP4 E017D8 0 +OP4 E017D9 0 +OP4 E017DA 0 +OP4 E017DB 0 +OP4 E017DC 0 +OP4 E017DD 0 +OP4 E017DE 0 +OP4 E017DF 0 +OP4 E017E0 0 +OP4 E017E1 0 +OP4 E017E2 0 +OP4 E017E3 0 +OP4 E017E4 0 +OP4 E017E5 0 +OP4 E017E6 0 +OP4 E017E7 0 +OP4 E017E8 0 +OP4 E017E9 0 +OP4 E017EA 0 +OP4 E017EB 0 +OP4 E017EC 0 +OP4 E017ED 0 +OP4 E017EE 0 +OP4 E017EF 0 +OP4 E017F0 0 +OP4 E017F1 0 +OP4 E017F2 0 +OP4 E017F3 0 +OP4 E017F4 0 +OP4 E017F5 0 +OP4 E017F6 0 +OP4 E017F7 0 +OP4 E017F8 0 +OP4 E017F9 0 +OP4 E017FA 0 +OP4 E017FB 0 +OP4 E017FC 0 +OP4 E017FD 0 +OP4 E017FE 0 +OP4 E017FF 0 +OP4 E01800 0 +OP4 E01801 0 +OP4 E01802 0 +OP4 E01803 0 +OP4 E01804 0 +OP4 E01805 0 +OP4 E01806 0 +OP4 E01807 0 +OP4 E01808 0 +OP4 E01809 0 +OP4 E0180A 0 +OP4 E0180B 0 +OP4 E0180C 0 +OP4 E0180D 0 +OP4 E0180E 0 +OP4 E0180F 0 +OP4 E01810 0 +OP4 E01811 0 +OP4 E01812 0 +OP4 E01813 0 +OP4 E01814 0 +OP4 E01815 0 +OP4 E01816 0 +OP4 E01817 0 +OP4 E01818 0 +OP4 E01819 0 +OP4 E0181A 0 +OP4 E0181B 0 +OP4 E0181C 0 +OP4 E0181D 0 +OP4 E0181E 0 +OP4 E0181F 0 +OP4 E01820 0 +OP4 E01821 0 +OP4 E01822 0 +OP4 E01823 0 +OP4 E01824 0 +OP4 E01825 0 +OP4 E01826 0 +OP4 E01827 0 +OP4 E01828 0 +OP4 E01829 0 +OP4 E0182A 0 +OP4 E0182B 0 +OP4 E0182C 0 +OP4 E0182D 0 +OP4 E0182E 0 +OP4 E0182F 0 +OP4 E01830 0 +OP4 E01831 0 +OP4 E01832 0 +OP4 E01833 0 +OP4 E01834 0 +OP4 E01835 0 +OP4 E01836 0 +OP4 E01837 0 +OP4 E01838 0 +OP4 E01839 0 +OP4 E0183A 0 +OP4 E0183B 0 +OP4 E0183C 0 +OP4 E0183D 0 +OP4 E0183E 0 +OP4 E0183F 0 +OP4 E01840 0 +OP4 E01841 0 +OP4 E01842 0 +OP4 E01843 0 +OP4 E01844 0 +OP4 E01845 0 +OP4 E01846 0 +OP4 E01847 0 +OP4 E01848 0 +OP4 E01849 0 +OP4 E0184A 0 +OP4 E0184B 0 +OP4 E0184C 0 +OP4 E0184D 0 +OP4 E0184E 0 +OP4 E0184F 0 +OP4 E01850 0 +OP4 E01851 0 +OP4 E01852 0 +OP4 E01853 0 +OP4 E01854 0 +OP4 E01855 0 +OP4 E01856 0 +OP4 E01857 0 +OP4 E01858 0 +OP4 E01859 0 +OP4 E0185A 0 +OP4 E0185B 0 +OP4 E0185C 0 +OP4 E0185D 0 +OP4 E0185E 0 +OP4 E0185F 0 +OP4 E01860 0 +OP4 E01861 0 +OP4 E01862 0 +OP4 E01863 0 +OP4 E01864 0 +OP4 E01865 0 +OP4 E01866 0 +OP4 E01867 0 +OP4 E01868 0 +OP4 E01869 0 +OP4 E0186A 0 +OP4 E0186B 0 +OP4 E0186C 0 +OP4 E0186D 0 +OP4 E0186E 0 +OP4 E0186F 0 +OP4 E01870 0 +OP4 E01871 0 +OP4 E01872 0 +OP4 E01873 0 +OP4 E01874 0 +OP4 E01875 0 +OP4 E01876 0 +OP4 E01877 0 +OP4 E01878 0 +OP4 E01879 0 +OP4 E0187A 0 +OP4 E0187B 0 +OP4 E0187C 0 +OP4 E0187D 0 +OP4 E0187E 0 +OP4 E0187F 0 +OP4 E01880 0 +OP4 E01881 0 +OP4 E01882 0 +OP4 E01883 0 +OP4 E01884 0 +OP4 E01885 0 +OP4 E01886 0 +OP4 E01887 0 +OP4 E01888 0 +OP4 E01889 0 +OP4 E0188A 0 +OP4 E0188B 0 +OP4 E0188C 0 +OP4 E0188D 0 +OP4 E0188E 0 +OP4 E0188F 0 +OP4 E01890 0 +OP4 E01891 0 +OP4 E01892 0 +OP4 E01893 0 +OP4 E01894 0 +OP4 E01895 0 +OP4 E01896 0 +OP4 E01897 0 +OP4 E01898 0 +OP4 E01899 0 +OP4 E0189A 0 +OP4 E0189B 0 +OP4 E0189C 0 +OP4 E0189D 0 +OP4 E0189E 0 +OP4 E0189F 0 +OP4 E018A0 0 +OP4 E018A1 0 +OP4 E018A2 0 +OP4 E018A3 0 +OP4 E018A4 0 +OP4 E018A5 0 +OP4 E018A6 0 +OP4 E018A7 0 +OP4 E018A8 0 +OP4 E018A9 0 +OP4 E018AA 0 +OP4 E018AB 0 +OP4 E018AC 0 +OP4 E018AD 0 +OP4 E018AE 0 +OP4 E018AF 0 +OP4 E018B0 0 +OP4 E018B1 0 +OP4 E018B2 0 +OP4 E018B3 0 +OP4 E018B4 0 +OP4 E018B5 0 +OP4 E018B6 0 +OP4 E018B7 0 +OP4 E018B8 0 +OP4 E018B9 0 +OP4 E018BA 0 +OP4 E018BB 0 +OP4 E018BC 0 +OP4 E018BD 0 +OP4 E018BE 0 +OP4 E018BF 0 +OP4 E018C0 0 +OP4 E018C1 0 +OP4 E018C2 0 +OP4 E018C3 0 +OP4 E018C4 0 +OP4 E018C5 0 +OP4 E018C6 0 +OP4 E018C7 0 +OP4 E018C8 0 +OP4 E018C9 0 +OP4 E018CA 0 +OP4 E018CB 0 +OP4 E018CC 0 +OP4 E018CD 0 +OP4 E018CE 0 +OP4 E018CF 0 +OP4 E018D0 0 +OP4 E018D1 0 +OP4 E018D2 0 +OP4 E018D3 0 +OP4 E018D4 0 +OP4 E018D5 0 +OP4 E018D6 0 +OP4 E018D7 0 +OP4 E018D8 0 +OP4 E018D9 0 +OP4 E018DA 0 +OP4 E018DB 0 +OP4 E018DC 0 +OP4 E018DD 0 +OP4 E018DE 0 +OP4 E018DF 0 +OP4 E018E0 0 +OP4 E018E1 0 +OP4 E018E2 0 +OP4 E018E3 0 +OP4 E018E4 0 +OP4 E018E5 0 +OP4 E018E6 0 +OP4 E018E7 0 +OP4 E018E8 0 +OP4 E018E9 0 +OP4 E018EA 0 +OP4 E018EB 0 +OP4 E018EC 0 +OP4 E018ED 0 +OP4 E018EE 0 +OP4 E018EF 0 +OP4 E018F0 0 +OP4 E018F1 0 +OP4 E018F2 0 +OP4 E018F3 0 +OP4 E018F4 0 +OP4 E018F5 0 +OP4 E018F6 0 +OP4 E018F7 0 +OP4 E018F8 0 +OP4 E018F9 0 +OP4 E018FA 0 +OP4 E018FB 0 +OP4 E018FC 0 +OP4 E018FD 0 +OP4 E018FE 0 +OP4 E018FF 0 +OP4 E01900 0 +OP4 E01901 0 +OP4 E01902 0 +OP4 E01903 0 +OP4 E01904 0 +OP4 E01905 0 +OP4 E01906 0 +OP4 E01907 0 +OP4 E01908 0 +OP4 E01909 0 +OP4 E0190A 0 +OP4 E0190B 0 +OP4 E0190C 0 +OP4 E0190D 0 +OP4 E0190E 0 +OP4 E0190F 0 +OP4 E01910 0 +OP4 E01911 0 +OP4 E01912 0 +OP4 E01913 0 +OP4 E01914 0 +OP4 E01915 0 +OP4 E01916 0 +OP4 E01917 0 +OP4 E01918 0 +OP4 E01919 0 +OP4 E0191A 0 +OP4 E0191B 0 +OP4 E0191C 0 +OP4 E0191D 0 +OP4 E0191E 0 +OP4 E0191F 0 +OP4 E01920 0 +OP4 E01921 0 +OP4 E01922 0 +OP4 E01923 0 +OP4 E01924 0 +OP4 E01925 0 +OP4 E01926 0 +OP4 E01927 0 +OP4 E01928 0 +OP4 E01929 0 +OP4 E0192A 0 +OP4 E0192B 0 +OP4 E0192C 0 +OP4 E0192D 0 +OP4 E0192E 0 +OP4 E0192F 0 +OP4 E01930 0 +OP4 E01931 0 +OP4 E01932 0 +OP4 E01933 0 +OP4 E01934 0 +OP4 E01935 0 +OP4 E01936 0 +OP4 E01937 0 +OP4 E01938 0 +OP4 E01939 0 +OP4 E0193A 0 +OP4 E0193B 0 +OP4 E0193C 0 +OP4 E0193D 0 +OP4 E0193E 0 +OP4 E0193F 0 +OP4 E01940 0 +OP4 E01941 0 +OP4 E01942 0 +OP4 E01943 0 +OP4 E01944 0 +OP4 E01945 0 +OP4 E01946 0 +OP4 E01947 0 +OP4 E01948 0 +OP4 E01949 0 +OP4 E0194A 0 +OP4 E0194B 0 +OP4 E0194C 0 +OP4 E0194D 0 +OP4 E0194E 0 +OP4 E0194F 0 +OP4 E01950 0 +OP4 E01951 0 +OP4 E01952 0 +OP4 E01953 0 +OP4 E01954 0 +OP4 E01955 0 +OP4 E01956 0 +OP4 E01957 0 +OP4 E01958 0 +OP4 E01959 0 +OP4 E0195A 0 +OP4 E0195B 0 +OP4 E0195C 0 +OP4 E0195D 0 +OP4 E0195E 0 +OP4 E0195F 0 +OP4 E01960 0 +OP4 E01961 0 +OP4 E01962 0 +OP4 E01963 0 +OP4 E01964 0 +OP4 E01965 0 +OP4 E01966 0 +OP4 E01967 0 +OP4 E01968 0 +OP4 E01969 0 +OP4 E0196A 0 +OP4 E0196B 0 +OP4 E0196C 0 +OP4 E0196D 0 +OP4 E0196E 0 +OP4 E0196F 0 +OP4 E01970 0 +OP4 E01971 0 +OP4 E01972 0 +OP4 E01973 0 +OP4 E01974 0 +OP4 E01975 0 +OP4 E01976 0 +OP4 E01977 0 +OP4 E01978 0 +OP4 E01979 0 +OP4 E0197A 0 +OP4 E0197B 0 +OP4 E0197C 0 +OP4 E0197D 0 +OP4 E0197E 0 +OP4 E0197F 0 +OP4 E01980 0 +OP4 E01981 0 +OP4 E01982 0 +OP4 E01983 0 +OP4 E01984 0 +OP4 E01985 0 +OP4 E01986 0 +OP4 E01987 0 +OP4 E01988 0 +OP4 E01989 0 +OP4 E0198A 0 +OP4 E0198B 0 +OP4 E0198C 0 +OP4 E0198D 0 +OP4 E0198E 0 +OP4 E0198F 0 +OP4 E01990 0 +OP4 E01991 0 +OP4 E01992 0 +OP4 E01993 0 +OP4 E01994 0 +OP4 E01995 0 +OP4 E01996 0 +OP4 E01997 0 +OP4 E01998 0 +OP4 E01999 0 +OP4 E0199A 0 +OP4 E0199B 0 +OP4 E0199C 0 +OP4 E0199D 0 +OP4 E0199E 0 +OP4 E0199F 0 +OP4 E019A0 0 +OP4 E019A1 0 +OP4 E019A2 0 +OP4 E019A3 0 +OP4 E019A4 0 +OP4 E019A5 0 +OP4 E019A6 0 +OP4 E019A7 0 +OP4 E019A8 0 +OP4 E019A9 0 +OP4 E019AA 0 +OP4 E019AB 0 +OP4 E019AC 0 +OP4 E019AD 0 +OP4 E019AE 0 +OP4 E019AF 0 +OP4 E019B0 0 +OP4 E019B1 0 +OP4 E019B2 0 +OP4 E019B3 0 +OP4 E019B4 0 +OP4 E019B5 0 +OP4 E019B6 0 +OP4 E019B7 0 +OP4 E019B8 0 +OP4 E019B9 0 +OP4 E019BA 0 +OP4 E019BB 0 +OP4 E019BC 0 +OP4 E019BD 0 +OP4 E019BE 0 +OP4 E019BF 0 +OP4 E019C0 0 +OP4 E019C1 0 +OP4 E019C2 0 +OP4 E019C3 0 +OP4 E019C4 0 +OP4 E019C5 0 +OP4 E019C6 0 +OP4 E019C7 0 +OP4 E019C8 0 +OP4 E019C9 0 +OP4 E019CA 0 +OP4 E019CB 0 +OP4 E019CC 0 +OP4 E019CD 0 +OP4 E019CE 0 +OP4 E019CF 0 +OP4 E019D0 0 +OP4 E019D1 0 +OP4 E019D2 0 +OP4 E019D3 0 +OP4 E019D4 0 +OP4 E019D5 0 +OP4 E019D6 0 +OP4 E019D7 0 +OP4 E019D8 0 +OP4 E019D9 0 +OP4 E019DA 0 +OP4 E019DB 0 +OP4 E019DC 0 +OP4 E019DD 0 +OP4 E019DE 0 +OP4 E019DF 0 +OP4 E019E0 0 +OP4 E019E1 0 +OP4 E019E2 0 +OP4 E019E3 0 +OP4 E019E4 0 +OP4 E019E5 0 +OP4 E019E6 0 +OP4 E019E7 0 +OP4 E019E8 0 +OP4 E019E9 0 +OP4 E019EA 0 +OP4 E019EB 0 +OP4 E019EC 0 +OP4 E019ED 0 +OP4 E019EE 0 +OP4 E019EF 0 +OP4 E019F0 0 +OP4 E019F1 0 +OP4 E019F2 0 +OP4 E019F3 0 +OP4 E019F4 0 +OP4 E019F5 0 +OP4 E019F6 0 +OP4 E019F7 0 +OP4 E019F8 0 +OP4 E019F9 0 +OP4 E019FA 0 +OP4 E019FB 0 +OP4 E019FC 0 +OP4 E019FD 0 +OP4 E019FE 0 +OP4 E019FF 0 +OP4 E01A00 0 +OP4 E01A01 0 +OP4 E01A02 0 +OP4 E01A03 0 +OP4 E01A04 0 +OP4 E01A05 0 +OP4 E01A06 0 +OP4 E01A07 0 +OP4 E01A08 0 +OP4 E01A09 0 +OP4 E01A0A 0 +OP4 E01A0B 0 +OP4 E01A0C 0 +OP4 E01A0D 0 +OP4 E01A0E 0 +OP4 E01A0F 0 +OP4 E01A10 0 +OP4 E01A11 0 +OP4 E01A12 0 +OP4 E01A13 0 +OP4 E01A14 0 +OP4 E01A15 0 +OP4 E01A16 0 +OP4 E01A17 0 +OP4 E01A18 0 +OP4 E01A19 0 +OP4 E01A1A 0 +OP4 E01A1B 0 +OP4 E01A1C 0 +OP4 E01A1D 0 +OP4 E01A1E 0 +OP4 E01A1F 0 +OP4 E01A20 0 +OP4 E01A21 0 +OP4 E01A22 0 +OP4 E01A23 0 +OP4 E01A24 0 +OP4 E01A25 0 +OP4 E01A26 0 +OP4 E01A27 0 +OP4 E01A28 0 +OP4 E01A29 0 +OP4 E01A2A 0 +OP4 E01A2B 0 +OP4 E01A2C 0 +OP4 E01A2D 0 +OP4 E01A2E 0 +OP4 E01A2F 0 +OP4 E01A30 0 +OP4 E01A31 0 +OP4 E01A32 0 +OP4 E01A33 0 +OP4 E01A34 0 +OP4 E01A35 0 +OP4 E01A36 0 +OP4 E01A37 0 +OP4 E01A38 0 +OP4 E01A39 0 +OP4 E01A3A 0 +OP4 E01A3B 0 +OP4 E01A3C 0 +OP4 E01A3D 0 +OP4 E01A3E 0 +OP4 E01A3F 0 +OP4 E01A40 0 +OP4 E01A41 0 +OP4 E01A42 0 +OP4 E01A43 0 +OP4 E01A44 0 +OP4 E01A45 0 +OP4 E01A46 0 +OP4 E01A47 0 +OP4 E01A48 0 +OP4 E01A49 0 +OP4 E01A4A 0 +OP4 E01A4B 0 +OP4 E01A4C 0 +OP4 E01A4D 0 +OP4 E01A4E 0 +OP4 E01A4F 0 +OP4 E01A50 0 +OP4 E01A51 0 +OP4 E01A52 0 +OP4 E01A53 0 +OP4 E01A54 0 +OP4 E01A55 0 +OP4 E01A56 0 +OP4 E01A57 0 +OP4 E01A58 0 +OP4 E01A59 0 +OP4 E01A5A 0 +OP4 E01A5B 0 +OP4 E01A5C 0 +OP4 E01A5D 0 +OP4 E01A5E 0 +OP4 E01A5F 0 +OP4 E01A60 0 +OP4 E01A61 0 +OP4 E01A62 0 +OP4 E01A63 0 +OP4 E01A64 0 +OP4 E01A65 0 +OP4 E01A66 0 +OP4 E01A67 0 +OP4 E01A68 0 +OP4 E01A69 0 +OP4 E01A6A 0 +OP4 E01A6B 0 +OP4 E01A6C 0 +OP4 E01A6D 0 +OP4 E01A6E 0 +OP4 E01A6F 0 +OP4 E01A70 0 +OP4 E01A71 0 +OP4 E01A72 0 +OP4 E01A73 0 +OP4 E01A74 0 +OP4 E01A75 0 +OP4 E01A76 0 +OP4 E01A77 0 +OP4 E01A78 0 +OP4 E01A79 0 +OP4 E01A7A 0 +OP4 E01A7B 0 +OP4 E01A7C 0 +OP4 E01A7D 0 +OP4 E01A7E 0 +OP4 E01A7F 0 +OP4 E01A80 0 +OP4 E01A81 0 +OP4 E01A82 0 +OP4 E01A83 0 +OP4 E01A84 0 +OP4 E01A85 0 +OP4 E01A86 0 +OP4 E01A87 0 +OP4 E01A88 0 +OP4 E01A89 0 +OP4 E01A8A 0 +OP4 E01A8B 0 +OP4 E01A8C 0 +OP4 E01A8D 0 +OP4 E01A8E 0 +OP4 E01A8F 0 +OP4 E01A90 0 +OP4 E01A91 0 +OP4 E01A92 0 +OP4 E01A93 0 +OP4 E01A94 0 +OP4 E01A95 0 +OP4 E01A96 0 +OP4 E01A97 0 +OP4 E01A98 0 +OP4 E01A99 0 +OP4 E01A9A 0 +OP4 E01A9B 0 +OP4 E01A9C 0 +OP4 E01A9D 0 +OP4 E01A9E 0 +OP4 E01A9F 0 +OP4 E01AA0 0 +OP4 E01AA1 0 +OP4 E01AA2 0 +OP4 E01AA3 0 +OP4 E01AA4 0 +OP4 E01AA5 0 +OP4 E01AA6 0 +OP4 E01AA7 0 +OP4 E01AA8 0 +OP4 E01AA9 0 +OP4 E01AAA 0 +OP4 E01AAB 0 +OP4 E01AAC 0 +OP4 E01AAD 0 +OP4 E01AAE 0 +OP4 E01AAF 0 +OP4 E01AB0 0 +OP4 E01AB1 0 +OP4 E01AB2 0 +OP4 E01AB3 0 +OP4 E01AB4 0 +OP4 E01AB5 0 +OP4 E01AB6 0 +OP4 E01AB7 0 +OP4 E01AB8 0 +OP4 E01AB9 0 +OP4 E01ABA 0 +OP4 E01ABB 0 +OP4 E01ABC 0 +OP4 E01ABD 0 +OP4 E01ABE 0 +OP4 E01ABF 0 +OP4 E01AC0 0 +OP4 E01AC1 0 +OP4 E01AC2 0 +OP4 E01AC3 0 +OP4 E01AC4 0 +OP4 E01AC5 0 +OP4 E01AC6 0 +OP4 E01AC7 0 +OP4 E01AC8 0 +OP4 E01AC9 0 +OP4 E01ACA 0 +OP4 E01ACB 0 +OP4 E01ACC 0 +OP4 E01ACD 0 +OP4 E01ACE 0 +OP4 E01ACF 0 +OP4 E01AD0 0 +OP4 E01AD1 0 +OP4 E01AD2 0 +OP4 E01AD3 0 +OP4 E01AD4 0 +OP4 E01AD5 0 +OP4 E01AD6 0 +OP4 E01AD7 0 +OP4 E01AD8 0 +OP4 E01AD9 0 +OP4 E01ADA 0 +OP4 E01ADB 0 +OP4 E01ADC 0 +OP4 E01ADD 0 +OP4 E01ADE 0 +OP4 E01ADF 0 +OP4 E01AE0 0 +OP4 E01AE1 0 +OP4 E01AE2 0 +OP4 E01AE3 0 +OP4 E01AE4 0 +OP4 E01AE5 0 +OP4 E01AE6 0 +OP4 E01AE7 0 +OP4 E01AE8 0 +OP4 E01AE9 0 +OP4 E01AEA 0 +OP4 E01AEB 0 +OP4 E01AEC 0 +OP4 E01AED 0 +OP4 E01AEE 0 +OP4 E01AEF 0 +OP4 E01AF0 0 +OP4 E01AF1 0 +OP4 E01AF2 0 +OP4 E01AF3 0 +OP4 E01AF4 0 +OP4 E01AF5 0 +OP4 E01AF6 0 +OP4 E01AF7 0 +OP4 E01AF8 0 +OP4 E01AF9 0 +OP4 E01AFA 0 +OP4 E01AFB 0 +OP4 E01AFC 0 +OP4 E01AFD 0 +OP4 E01AFE 0 +OP4 E01AFF 0 +OP4 E01B00 0 +OP4 E01B01 0 +OP4 E01B02 0 +OP4 E01B03 0 +OP4 E01B04 0 +OP4 E01B05 0 +OP4 E01B06 0 +OP4 E01B07 0 +OP4 E01B08 0 +OP4 E01B09 0 +OP4 E01B0A 0 +OP4 E01B0B 0 +OP4 E01B0C 0 +OP4 E01B0D 0 +OP4 E01B0E 0 +OP4 E01B0F 0 +OP4 E01B10 0 +OP4 E01B11 0 +OP4 E01B12 0 +OP4 E01B13 0 +OP4 E01B14 0 +OP4 E01B15 0 +OP4 E01B16 0 +OP4 E01B17 0 +OP4 E01B18 0 +OP4 E01B19 0 +OP4 E01B1A 0 +OP4 E01B1B 0 +OP4 E01B1C 0 +OP4 E01B1D 0 +OP4 E01B1E 0 +OP4 E01B1F 0 +OP4 E01B20 0 +OP4 E01B21 0 +OP4 E01B22 0 +OP4 E01B23 0 +OP4 E01B24 0 +OP4 E01B25 0 +OP4 E01B26 0 +OP4 E01B27 0 +OP4 E01B28 0 +OP4 E01B29 0 +OP4 E01B2A 0 +OP4 E01B2B 0 +OP4 E01B2C 0 +OP4 E01B2D 0 +OP4 E01B2E 0 +OP4 E01B2F 0 +OP4 E01B30 0 +OP4 E01B31 0 +OP4 E01B32 0 +OP4 E01B33 0 +OP4 E01B34 0 +OP4 E01B35 0 +OP4 E01B36 0 +OP4 E01B37 0 +OP4 E01B38 0 +OP4 E01B39 0 +OP4 E01B3A 0 +OP4 E01B3B 0 +OP4 E01B3C 0 +OP4 E01B3D 0 +OP4 E01B3E 0 +OP4 E01B3F 0 +OP4 E01B40 0 +OP4 E01B41 0 +OP4 E01B42 0 +OP4 E01B43 0 +OP4 E01B44 0 +OP4 E01B45 0 +OP4 E01B46 0 +OP4 E01B47 0 +OP4 E01B48 0 +OP4 E01B49 0 +OP4 E01B4A 0 +OP4 E01B4B 0 +OP4 E01B4C 0 +OP4 E01B4D 0 +OP4 E01B4E 0 +OP4 E01B4F 0 +OP4 E01B50 0 +OP4 E01B51 0 +OP4 E01B52 0 +OP4 E01B53 0 +OP4 E01B54 0 +OP4 E01B55 0 +OP4 E01B56 0 +OP4 E01B57 0 +OP4 E01B58 0 +OP4 E01B59 0 +OP4 E01B5A 0 +OP4 E01B5B 0 +OP4 E01B5C 0 +OP4 E01B5D 0 +OP4 E01B5E 0 +OP4 E01B5F 0 +OP4 E01B60 0 +OP4 E01B61 0 +OP4 E01B62 0 +OP4 E01B63 0 +OP4 E01B64 0 +OP4 E01B65 0 +OP4 E01B66 0 +OP4 E01B67 0 +OP4 E01B68 0 +OP4 E01B69 0 +OP4 E01B6A 0 +OP4 E01B6B 0 +OP4 E01B6C 0 +OP4 E01B6D 0 +OP4 E01B6E 0 +OP4 E01B6F 0 +OP4 E01B70 0 +OP4 E01B71 0 +OP4 E01B72 0 +OP4 E01B73 0 +OP4 E01B74 0 +OP4 E01B75 0 +OP4 E01B76 0 +OP4 E01B77 0 +OP4 E01B78 0 +OP4 E01B79 0 +OP4 E01B7A 0 +OP4 E01B7B 0 +OP4 E01B7C 0 +OP4 E01B7D 0 +OP4 E01B7E 0 +OP4 E01B7F 0 +OP4 E01B80 0 +OP4 E01B81 0 +OP4 E01B82 0 +OP4 E01B83 0 +OP4 E01B84 0 +OP4 E01B85 0 +OP4 E01B86 0 +OP4 E01B87 0 +OP4 E01B88 0 +OP4 E01B89 0 +OP4 E01B8A 0 +OP4 E01B8B 0 +OP4 E01B8C 0 +OP4 E01B8D 0 +OP4 E01B8E 0 +OP4 E01B8F 0 +OP4 E01B90 0 +OP4 E01B91 0 +OP4 E01B92 0 +OP4 E01B93 0 +OP4 E01B94 0 +OP4 E01B95 0 +OP4 E01B96 0 +OP4 E01B97 0 +OP4 E01B98 0 +OP4 E01B99 0 +OP4 E01B9A 0 +OP4 E01B9B 0 +OP4 E01B9C 0 +OP4 E01B9D 0 +OP4 E01B9E 0 +OP4 E01B9F 0 +OP4 E01BA0 0 +OP4 E01BA1 0 +OP4 E01BA2 0 +OP4 E01BA3 0 +OP4 E01BA4 0 +OP4 E01BA5 0 +OP4 E01BA6 0 +OP4 E01BA7 0 +OP4 E01BA8 0 +OP4 E01BA9 0 +OP4 E01BAA 0 +OP4 E01BAB 0 +OP4 E01BAC 0 +OP4 E01BAD 0 +OP4 E01BAE 0 +OP4 E01BAF 0 +OP4 E01BB0 0 +OP4 E01BB1 0 +OP4 E01BB2 0 +OP4 E01BB3 0 +OP4 E01BB4 0 +OP4 E01BB5 0 +OP4 E01BB6 0 +OP4 E01BB7 0 +OP4 E01BB8 0 +OP4 E01BB9 0 +OP4 E01BBA 0 +OP4 E01BBB 0 +OP4 E01BBC 0 +OP4 E01BBD 0 +OP4 E01BBE 0 +OP4 E01BBF 0 +OP4 E01BC0 0 +OP4 E01BC1 0 +OP4 E01BC2 0 +OP4 E01BC3 0 +OP4 E01BC4 0 +OP4 E01BC5 0 +OP4 E01BC6 0 +OP4 E01BC7 0 +OP4 E01BC8 0 +OP4 E01BC9 0 +OP4 E01BCA 0 +OP4 E01BCB 0 +OP4 E01BCC 0 +OP4 E01BCD 0 +OP4 E01BCE 0 +OP4 E01BCF 0 +OP4 E01BD0 0 +OP4 E01BD1 0 +OP4 E01BD2 0 +OP4 E01BD3 0 +OP4 E01BD4 0 +OP4 E01BD5 0 +OP4 E01BD6 0 +OP4 E01BD7 0 +OP4 E01BD8 0 +OP4 E01BD9 0 +OP4 E01BDA 0 +OP4 E01BDB 0 +OP4 E01BDC 0 +OP4 E01BDD 0 +OP4 E01BDE 0 +OP4 E01BDF 0 +OP4 E01BE0 0 +OP4 E01BE1 0 +OP4 E01BE2 0 +OP4 E01BE3 0 +OP4 E01BE4 0 +OP4 E01BE5 0 +OP4 E01BE6 0 +OP4 E01BE7 0 +OP4 E01BE8 0 +OP4 E01BE9 0 +OP4 E01BEA 0 +OP4 E01BEB 0 +OP4 E01BEC 0 +OP4 E01BED 0 +OP4 E01BEE 0 +OP4 E01BEF 0 +OP4 E01BF0 0 +OP4 E01BF1 0 +OP4 E01BF2 0 +OP4 E01BF3 0 +OP4 E01BF4 0 +OP4 E01BF5 0 +OP4 E01BF6 0 +OP4 E01BF7 0 +OP4 E01BF8 0 +OP4 E01BF9 0 +OP4 E01BFA 0 +OP4 E01BFB 0 +OP4 E01BFC 0 +OP4 E01BFD 0 +OP4 E01BFE 0 +OP4 E01BFF 0 +OP4 E01C00 0 +OP4 E01C01 0 +OP4 E01C02 0 +OP4 E01C03 0 +OP4 E01C04 0 +OP4 E01C05 0 +OP4 E01C06 0 +OP4 E01C07 0 +OP4 E01C08 0 +OP4 E01C09 0 +OP4 E01C0A 0 +OP4 E01C0B 0 +OP4 E01C0C 0 +OP4 E01C0D 0 +OP4 E01C0E 0 +OP4 E01C0F 0 +OP4 E01C10 0 +OP4 E01C11 0 +OP4 E01C12 0 +OP4 E01C13 0 +OP4 E01C14 0 +OP4 E01C15 0 +OP4 E01C16 0 +OP4 E01C17 0 +OP4 E01C18 0 +OP4 E01C19 0 +OP4 E01C1A 0 +OP4 E01C1B 0 +OP4 E01C1C 0 +OP4 E01C1D 0 +OP4 E01C1E 0 +OP4 E01C1F 0 +OP4 E01C20 0 +OP4 E01C21 0 +OP4 E01C22 0 +OP4 E01C23 0 +OP4 E01C24 0 +OP4 E01C25 0 +OP4 E01C26 0 +OP4 E01C27 0 +OP4 E01C28 0 +OP4 E01C29 0 +OP4 E01C2A 0 +OP4 E01C2B 0 +OP4 E01C2C 0 +OP4 E01C2D 0 +OP4 E01C2E 0 +OP4 E01C2F 0 +OP4 E01C30 0 +OP4 E01C31 0 +OP4 E01C32 0 +OP4 E01C33 0 +OP4 E01C34 0 +OP4 E01C35 0 +OP4 E01C36 0 +OP4 E01C37 0 +OP4 E01C38 0 +OP4 E01C39 0 +OP4 E01C3A 0 +OP4 E01C3B 0 +OP4 E01C3C 0 +OP4 E01C3D 0 +OP4 E01C3E 0 +OP4 E01C3F 0 +OP4 E01C40 0 +OP4 E01C41 0 +OP4 E01C42 0 +OP4 E01C43 0 +OP4 E01C44 0 +OP4 E01C45 0 +OP4 E01C46 0 +OP4 E01C47 0 +OP4 E01C48 0 +OP4 E01C49 0 +OP4 E01C4A 0 +OP4 E01C4B 0 +OP4 E01C4C 0 +OP4 E01C4D 0 +OP4 E01C4E 0 +OP4 E01C4F 0 +OP4 E01C50 0 +OP4 E01C51 0 +OP4 E01C52 0 +OP4 E01C53 0 +OP4 E01C54 0 +OP4 E01C55 0 +OP4 E01C56 0 +OP4 E01C57 0 +OP4 E01C58 0 +OP4 E01C59 0 +OP4 E01C5A 0 +OP4 E01C5B 0 +OP4 E01C5C 0 +OP4 E01C5D 0 +OP4 E01C5E 0 +OP4 E01C5F 0 +OP4 E01C60 0 +OP4 E01C61 0 +OP4 E01C62 0 +OP4 E01C63 0 +OP4 E01C64 0 +OP4 E01C65 0 +OP4 E01C66 0 +OP4 E01C67 0 +OP4 E01C68 0 +OP4 E01C69 0 +OP4 E01C6A 0 +OP4 E01C6B 0 +OP4 E01C6C 0 +OP4 E01C6D 0 +OP4 E01C6E 0 +OP4 E01C6F 0 +OP4 E01C70 0 +OP4 E01C71 0 +OP4 E01C72 0 +OP4 E01C73 0 +OP4 E01C74 0 +OP4 E01C75 0 +OP4 E01C76 0 +OP4 E01C77 0 +OP4 E01C78 0 +OP4 E01C79 0 +OP4 E01C7A 0 +OP4 E01C7B 0 +OP4 E01C7C 0 +OP4 E01C7D 0 +OP4 E01C7E 0 +OP4 E01C7F 0 +OP4 E01C80 0 +OP4 E01C81 0 +OP4 E01C82 0 +OP4 E01C83 0 +OP4 E01C84 0 +OP4 E01C85 0 +OP4 E01C86 0 +OP4 E01C87 0 +OP4 E01C88 0 +OP4 E01C89 0 +OP4 E01C8A 0 +OP4 E01C8B 0 +OP4 E01C8C 0 +OP4 E01C8D 0 +OP4 E01C8E 0 +OP4 E01C8F 0 +OP4 E01C90 0 +OP4 E01C91 0 +OP4 E01C92 0 +OP4 E01C93 0 +OP4 E01C94 0 +OP4 E01C95 0 +OP4 E01C96 0 +OP4 E01C97 0 +OP4 E01C98 0 +OP4 E01C99 0 +OP4 E01C9A 0 +OP4 E01C9B 0 +OP4 E01C9C 0 +OP4 E01C9D 0 +OP4 E01C9E 0 +OP4 E01C9F 0 +OP4 E01CA0 0 +OP4 E01CA1 0 +OP4 E01CA2 0 +OP4 E01CA3 0 +OP4 E01CA4 0 +OP4 E01CA5 0 +OP4 E01CA6 0 +OP4 E01CA7 0 +OP4 E01CA8 0 +OP4 E01CA9 0 +OP4 E01CAA 0 +OP4 E01CAB 0 +OP4 E01CAC 0 +OP4 E01CAD 0 +OP4 E01CAE 0 +OP4 E01CAF 0 +OP4 E01CB0 0 +OP4 E01CB1 0 +OP4 E01CB2 0 +OP4 E01CB3 0 +OP4 E01CB4 0 +OP4 E01CB5 0 +OP4 E01CB6 0 +OP4 E01CB7 0 +OP4 E01CB8 0 +OP4 E01CB9 0 +OP4 E01CBA 0 +OP4 E01CBB 0 +OP4 E01CBC 0 +OP4 E01CBD 0 +OP4 E01CBE 0 +OP4 E01CBF 0 +OP4 E01CC0 0 +OP4 E01CC1 0 +OP4 E01CC2 0 +OP4 E01CC3 0 +OP4 E01CC4 0 +OP4 E01CC5 0 +OP4 E01CC6 0 +OP4 E01CC7 0 +OP4 E01CC8 0 +OP4 E01CC9 0 +OP4 E01CCA 0 +OP4 E01CCB 0 +OP4 E01CCC 0 +OP4 E01CCD 0 +OP4 E01CCE 0 +OP4 E01CCF 0 +OP4 E01CD0 0 +OP4 E01CD1 0 +OP4 E01CD2 0 +OP4 E01CD3 0 +OP4 E01CD4 0 +OP4 E01CD5 0 +OP4 E01CD6 0 +OP4 E01CD7 0 +OP4 E01CD8 0 +OP4 E01CD9 0 +OP4 E01CDA 0 +OP4 E01CDB 0 +OP4 E01CDC 0 +OP4 E01CDD 0 +OP4 E01CDE 0 +OP4 E01CDF 0 +OP4 E01CE0 0 +OP4 E01CE1 0 +OP4 E01CE2 0 +OP4 E01CE3 0 +OP4 E01CE4 0 +OP4 E01CE5 0 +OP4 E01CE6 0 +OP4 E01CE7 0 +OP4 E01CE8 0 +OP4 E01CE9 0 +OP4 E01CEA 0 +OP4 E01CEB 0 +OP4 E01CEC 0 +OP4 E01CED 0 +OP4 E01CEE 0 +OP4 E01CEF 0 +OP4 E01CF0 0 +OP4 E01CF1 0 +OP4 E01CF2 0 +OP4 E01CF3 0 +OP4 E01CF4 0 +OP4 E01CF5 0 +OP4 E01CF6 0 +OP4 E01CF7 0 +OP4 E01CF8 0 +OP4 E01CF9 0 +OP4 E01CFA 0 +OP4 E01CFB 0 +OP4 E01CFC 0 +OP4 E01CFD 0 +OP4 E01CFE 0 +OP4 E01CFF 0 +OP4 E01D00 0 +OP4 E01D01 0 +OP4 E01D02 0 +OP4 E01D03 0 +OP4 E01D04 0 +OP4 E01D05 0 +OP4 E01D06 0 +OP4 E01D07 0 +OP4 E01D08 0 +OP4 E01D09 0 +OP4 E01D0A 0 +OP4 E01D0B 0 +OP4 E01D0C 0 +OP4 E01D0D 0 +OP4 E01D0E 0 +OP4 E01D0F 0 +OP4 E01D10 0 +OP4 E01D11 0 +OP4 E01D12 0 +OP4 E01D13 0 +OP4 E01D14 0 +OP4 E01D15 0 +OP4 E01D16 0 +OP4 E01D17 0 +OP4 E01D18 0 +OP4 E01D19 0 +OP4 E01D1A 0 +OP4 E01D1B 0 +OP4 E01D1C 0 +OP4 E01D1D 0 +OP4 E01D1E 0 +OP4 E01D1F 0 +OP4 E01D20 0 +OP4 E01D21 0 +OP4 E01D22 0 +OP4 E01D23 0 +OP4 E01D24 0 +OP4 E01D25 0 +OP4 E01D26 0 +OP4 E01D27 0 +OP4 E01D28 0 +OP4 E01D29 0 +OP4 E01D2A 0 +OP4 E01D2B 0 +OP4 E01D2C 0 +OP4 E01D2D 0 +OP4 E01D2E 0 +OP4 E01D2F 0 +OP4 E01D30 0 +OP4 E01D31 0 +OP4 E01D32 0 +OP4 E01D33 0 +OP4 E01D34 0 +OP4 E01D35 0 +OP4 E01D36 0 +OP4 E01D37 0 +OP4 E01D38 0 +OP4 E01D39 0 +OP4 E01D3A 0 +OP4 E01D3B 0 +OP4 E01D3C 0 +OP4 E01D3D 0 +OP4 E01D3E 0 +OP4 E01D3F 0 +OP4 E01D40 0 +OP4 E01D41 0 +OP4 E01D42 0 +OP4 E01D43 0 +OP4 E01D44 0 +OP4 E01D45 0 +OP4 E01D46 0 +OP4 E01D47 0 +OP4 E01D48 0 +OP4 E01D49 0 +OP4 E01D4A 0 +OP4 E01D4B 0 +OP4 E01D4C 0 +OP4 E01D4D 0 +OP4 E01D4E 0 +OP4 E01D4F 0 +OP4 E01D50 0 +OP4 E01D51 0 +OP4 E01D52 0 +OP4 E01D53 0 +OP4 E01D54 0 +OP4 E01D55 0 +OP4 E01D56 0 +OP4 E01D57 0 +OP4 E01D58 0 +OP4 E01D59 0 +OP4 E01D5A 0 +OP4 E01D5B 0 +OP4 E01D5C 0 +OP4 E01D5D 0 +OP4 E01D5E 0 +OP4 E01D5F 0 +OP4 E01D60 0 +OP4 E01D61 0 +OP4 E01D62 0 +OP4 E01D63 0 +OP4 E01D64 0 +OP4 E01D65 0 +OP4 E01D66 0 +OP4 E01D67 0 +OP4 E01D68 0 +OP4 E01D69 0 +OP4 E01D6A 0 +OP4 E01D6B 0 +OP4 E01D6C 0 +OP4 E01D6D 0 +OP4 E01D6E 0 +OP4 E01D6F 0 +OP4 E01D70 0 +OP4 E01D71 0 +OP4 E01D72 0 +OP4 E01D73 0 +OP4 E01D74 0 +OP4 E01D75 0 +OP4 E01D76 0 +OP4 E01D77 0 +OP4 E01D78 0 +OP4 E01D79 0 +OP4 E01D7A 0 +OP4 E01D7B 0 +OP4 E01D7C 0 +OP4 E01D7D 0 +OP4 E01D7E 0 +OP4 E01D7F 0 +OP4 E01D80 0 +OP4 E01D81 0 +OP4 E01D82 0 +OP4 E01D83 0 +OP4 E01D84 0 +OP4 E01D85 0 +OP4 E01D86 0 +OP4 E01D87 0 +OP4 E01D88 0 +OP4 E01D89 0 +OP4 E01D8A 0 +OP4 E01D8B 0 +OP4 E01D8C 0 +OP4 E01D8D 0 +OP4 E01D8E 0 +OP4 E01D8F 0 +OP4 E01D90 0 +OP4 E01D91 0 +OP4 E01D92 0 +OP4 E01D93 0 +OP4 E01D94 0 +OP4 E01D95 0 +OP4 E01D96 0 +OP4 E01D97 0 +OP4 E01D98 0 +OP4 E01D99 0 +OP4 E01D9A 0 +OP4 E01D9B 0 +OP4 E01D9C 0 +OP4 E01D9D 0 +OP4 E01D9E 0 +OP4 E01D9F 0 +OP4 E01DA0 0 +OP4 E01DA1 0 +OP4 E01DA2 0 +OP4 E01DA3 0 +OP4 E01DA4 0 +OP4 E01DA5 0 +OP4 E01DA6 0 +OP4 E01DA7 0 +OP4 E01DA8 0 +OP4 E01DA9 0 +OP4 E01DAA 0 +OP4 E01DAB 0 +OP4 E01DAC 0 +OP4 E01DAD 0 +OP4 E01DAE 0 +OP4 E01DAF 0 +OP4 E01DB0 0 +OP4 E01DB1 0 +OP4 E01DB2 0 +OP4 E01DB3 0 +OP4 E01DB4 0 +OP4 E01DB5 0 +OP4 E01DB6 0 +OP4 E01DB7 0 +OP4 E01DB8 0 +OP4 E01DB9 0 +OP4 E01DBA 0 +OP4 E01DBB 0 +OP4 E01DBC 0 +OP4 E01DBD 0 +OP4 E01DBE 0 +OP4 E01DBF 0 +OP4 E01DC0 0 +OP4 E01DC1 0 +OP4 E01DC2 0 +OP4 E01DC3 0 +OP4 E01DC4 0 +OP4 E01DC5 0 +OP4 E01DC6 0 +OP4 E01DC7 0 +OP4 E01DC8 0 +OP4 E01DC9 0 +OP4 E01DCA 0 +OP4 E01DCB 0 +OP4 E01DCC 0 +OP4 E01DCD 0 +OP4 E01DCE 0 +OP4 E01DCF 0 +OP4 E01DD0 0 +OP4 E01DD1 0 +OP4 E01DD2 0 +OP4 E01DD3 0 +OP4 E01DD4 0 +OP4 E01DD5 0 +OP4 E01DD6 0 +OP4 E01DD7 0 +OP4 E01DD8 0 +OP4 E01DD9 0 +OP4 E01DDA 0 +OP4 E01DDB 0 +OP4 E01DDC 0 +OP4 E01DDD 0 +OP4 E01DDE 0 +OP4 E01DDF 0 +OP4 E01DE0 0 +OP4 E01DE1 0 +OP4 E01DE2 0 +OP4 E01DE3 0 +OP4 E01DE4 0 +OP4 E01DE5 0 +OP4 E01DE6 0 +OP4 E01DE7 0 +OP4 E01DE8 0 +OP4 E01DE9 0 +OP4 E01DEA 0 +OP4 E01DEB 0 +OP4 E01DEC 0 +OP4 E01DED 0 +OP4 E01DEE 0 +OP4 E01DEF 0 +OP4 E01DF0 0 +OP4 E01DF1 0 +OP4 E01DF2 0 +OP4 E01DF3 0 +OP4 E01DF4 0 +OP4 E01DF5 0 +OP4 E01DF6 0 +OP4 E01DF7 0 +OP4 E01DF8 0 +OP4 E01DF9 0 +OP4 E01DFA 0 +OP4 E01DFB 0 +OP4 E01DFC 0 +OP4 E01DFD 0 +OP4 E01DFE 0 +OP4 E01DFF 0 +OP4 E01E00 0 +OP4 E01E01 0 +OP4 E01E02 0 +OP4 E01E03 0 +OP4 E01E04 0 +OP4 E01E05 0 +OP4 E01E06 0 +OP4 E01E07 0 +OP4 E01E08 0 +OP4 E01E09 0 +OP4 E01E0A 0 +OP4 E01E0B 0 +OP4 E01E0C 0 +OP4 E01E0D 0 +OP4 E01E0E 0 +OP4 E01E0F 0 +OP4 E01E10 0 +OP4 E01E11 0 +OP4 E01E12 0 +OP4 E01E13 0 +OP4 E01E14 0 +OP4 E01E15 0 +OP4 E01E16 0 +OP4 E01E17 0 +OP4 E01E18 0 +OP4 E01E19 0 +OP4 E01E1A 0 +OP4 E01E1B 0 +OP4 E01E1C 0 +OP4 E01E1D 0 +OP4 E01E1E 0 +OP4 E01E1F 0 +OP4 E01E20 0 +OP4 E01E21 0 +OP4 E01E22 0 +OP4 E01E23 0 +OP4 E01E24 0 +OP4 E01E25 0 +OP4 E01E26 0 +OP4 E01E27 0 +OP4 E01E28 0 +OP4 E01E29 0 +OP4 E01E2A 0 +OP4 E01E2B 0 +OP4 E01E2C 0 +OP4 E01E2D 0 +OP4 E01E2E 0 +OP4 E01E2F 0 +OP4 E01E30 0 +OP4 E01E31 0 +OP4 E01E32 0 +OP4 E01E33 0 +OP4 E01E34 0 +OP4 E01E35 0 +OP4 E01E36 0 +OP4 E01E37 0 +OP4 E01E38 0 +OP4 E01E39 0 +OP4 E01E3A 0 +OP4 E01E3B 0 +OP4 E01E3C 0 +OP4 E01E3D 0 +OP4 E01E3E 0 +OP4 E01E3F 0 +OP4 E01E40 0 +OP4 E01E41 0 +OP4 E01E42 0 +OP4 E01E43 0 +OP4 E01E44 0 +OP4 E01E45 0 +OP4 E01E46 0 +OP4 E01E47 0 +OP4 E01E48 0 +OP4 E01E49 0 +OP4 E01E4A 0 +OP4 E01E4B 0 +OP4 E01E4C 0 +OP4 E01E4D 0 +OP4 E01E4E 0 +OP4 E01E4F 0 +OP4 E01E50 0 +OP4 E01E51 0 +OP4 E01E52 0 +OP4 E01E53 0 +OP4 E01E54 0 +OP4 E01E55 0 +OP4 E01E56 0 +OP4 E01E57 0 +OP4 E01E58 0 +OP4 E01E59 0 +OP4 E01E5A 0 +OP4 E01E5B 0 +OP4 E01E5C 0 +OP4 E01E5D 0 +OP4 E01E5E 0 +OP4 E01E5F 0 +OP4 E01E60 0 +OP4 E01E61 0 +OP4 E01E62 0 +OP4 E01E63 0 +OP4 E01E64 0 +OP4 E01E65 0 +OP4 E01E66 0 +OP4 E01E67 0 +OP4 E01E68 0 +OP4 E01E69 0 +OP4 E01E6A 0 +OP4 E01E6B 0 +OP4 E01E6C 0 +OP4 E01E6D 0 +OP4 E01E6E 0 +OP4 E01E6F 0 +OP4 E01E70 0 +OP4 E01E71 0 +OP4 E01E72 0 +OP4 E01E73 0 +OP4 E01E74 0 +OP4 E01E75 0 +OP4 E01E76 0 +OP4 E01E77 0 +OP4 E01E78 0 +OP4 E01E79 0 +OP4 E01E7A 0 +OP4 E01E7B 0 +OP4 E01E7C 0 +OP4 E01E7D 0 +OP4 E01E7E 0 +OP4 E01E7F 0 +OP4 E01E80 0 +OP4 E01E81 0 +OP4 E01E82 0 +OP4 E01E83 0 +OP4 E01E84 0 +OP4 E01E85 0 +OP4 E01E86 0 +OP4 E01E87 0 +OP4 E01E88 0 +OP4 E01E89 0 +OP4 E01E8A 0 +OP4 E01E8B 0 +OP4 E01E8C 0 +OP4 E01E8D 0 +OP4 E01E8E 0 +OP4 E01E8F 0 +OP4 E01E90 0 +OP4 E01E91 0 +OP4 E01E92 0 +OP4 E01E93 0 +OP4 E01E94 0 +OP4 E01E95 0 +OP4 E01E96 0 +OP4 E01E97 0 +OP4 E01E98 0 +OP4 E01E99 0 +OP4 E01E9A 0 +OP4 E01E9B 0 +OP4 E01E9C 0 +OP4 E01E9D 0 +OP4 E01E9E 0 +OP4 E01E9F 0 +OP4 E01EA0 0 +OP4 E01EA1 0 +OP4 E01EA2 0 +OP4 E01EA3 0 +OP4 E01EA4 0 +OP4 E01EA5 0 +OP4 E01EA6 0 +OP4 E01EA7 0 +OP4 E01EA8 0 +OP4 E01EA9 0 +OP4 E01EAA 0 +OP4 E01EAB 0 +OP4 E01EAC 0 +OP4 E01EAD 0 +OP4 E01EAE 0 +OP4 E01EAF 0 +OP4 E01EB0 0 +OP4 E01EB1 0 +OP4 E01EB2 0 +OP4 E01EB3 0 +OP4 E01EB4 0 +OP4 E01EB5 0 +OP4 E01EB6 0 +OP4 E01EB7 0 +OP4 E01EB8 0 +OP4 E01EB9 0 +OP4 E01EBA 0 +OP4 E01EBB 0 +OP4 E01EBC 0 +OP4 E01EBD 0 +OP4 E01EBE 0 +OP4 E01EBF 0 +OP4 E01EC0 0 +OP4 E01EC1 0 +OP4 E01EC2 0 +OP4 E01EC3 0 +OP4 E01EC4 0 +OP4 E01EC5 0 +OP4 E01EC6 0 +OP4 E01EC7 0 +OP4 E01EC8 0 +OP4 E01EC9 0 +OP4 E01ECA 0 +OP4 E01ECB 0 +OP4 E01ECC 0 +OP4 E01ECD 0 +OP4 E01ECE 0 +OP4 E01ECF 0 +OP4 E01ED0 0 +OP4 E01ED1 0 +OP4 E01ED2 0 +OP4 E01ED3 0 +OP4 E01ED4 0 +OP4 E01ED5 0 +OP4 E01ED6 0 +OP4 E01ED7 0 +OP4 E01ED8 0 +OP4 E01ED9 0 +OP4 E01EDA 0 +OP4 E01EDB 0 +OP4 E01EDC 0 +OP4 E01EDD 0 +OP4 E01EDE 0 +OP4 E01EDF 0 +OP4 E01EE0 0 +OP4 E01EE1 0 +OP4 E01EE2 0 +OP4 E01EE3 0 +OP4 E01EE4 0 +OP4 E01EE5 0 +OP4 E01EE6 0 +OP4 E01EE7 0 +OP4 E01EE8 0 +OP4 E01EE9 0 +OP4 E01EEA 0 +OP4 E01EEB 0 +OP4 E01EEC 0 +OP4 E01EED 0 +OP4 E01EEE 0 +OP4 E01EEF 0 +OP4 E01EF0 0 +OP4 E01EF1 0 +OP4 E01EF2 0 +OP4 E01EF3 0 +OP4 E01EF4 0 +OP4 E01EF5 0 +OP4 E01EF6 0 +OP4 E01EF7 0 +OP4 E01EF8 0 +OP4 E01EF9 0 +OP4 E01EFA 0 +OP4 E01EFB 0 +OP4 E01EFC 0 +OP4 E01EFD 0 +OP4 E01EFE 0 +OP4 E01EFF 0 +OP4 E01F00 0 +OP4 E01F01 0 +OP4 E01F02 0 +OP4 E01F03 0 +OP4 E01F04 0 +OP4 E01F05 0 +OP4 E01F06 0 +OP4 E01F07 0 +OP4 E01F08 0 +OP4 E01F09 0 +OP4 E01F0A 0 +OP4 E01F0B 0 +OP4 E01F0C 0 +OP4 E01F0D 0 +OP4 E01F0E 0 +OP4 E01F0F 0 +OP4 E01F10 0 +OP4 E01F11 0 +OP4 E01F12 0 +OP4 E01F13 0 +OP4 E01F14 0 +OP4 E01F15 0 +OP4 E01F16 0 +OP4 E01F17 0 +OP4 E01F18 0 +OP4 E01F19 0 +OP4 E01F1A 0 +OP4 E01F1B 0 +OP4 E01F1C 0 +OP4 E01F1D 0 +OP4 E01F1E 0 +OP4 E01F1F 0 +OP4 E01F20 0 +OP4 E01F21 0 +OP4 E01F22 0 +OP4 E01F23 0 +OP4 E01F24 0 +OP4 E01F25 0 +OP4 E01F26 0 +OP4 E01F27 0 +OP4 E01F28 0 +OP4 E01F29 0 +OP4 E01F2A 0 +OP4 E01F2B 0 +OP4 E01F2C 0 +OP4 E01F2D 0 +OP4 E01F2E 0 +OP4 E01F2F 0 +OP4 E01F30 0 +OP4 E01F31 0 +OP4 E01F32 0 +OP4 E01F33 0 +OP4 E01F34 0 +OP4 E01F35 0 +OP4 E01F36 0 +OP4 E01F37 0 +OP4 E01F38 0 +OP4 E01F39 0 +OP4 E01F3A 0 +OP4 E01F3B 0 +OP4 E01F3C 0 +OP4 E01F3D 0 +OP4 E01F3E 0 +OP4 E01F3F 0 +OP4 E01F40 0 +OP4 E01F41 0 +OP4 E01F42 0 +OP4 E01F43 0 +OP4 E01F44 0 +OP4 E01F45 0 +OP4 E01F46 0 +OP4 E01F47 0 +OP4 E01F48 0 +OP4 E01F49 0 +OP4 E01F4A 0 +OP4 E01F4B 0 +OP4 E01F4C 0 +OP4 E01F4D 0 +OP4 E01F4E 0 +OP4 E01F4F 0 +OP4 E01F50 0 +OP4 E01F51 0 +OP4 E01F52 0 +OP4 E01F53 0 +OP4 E01F54 0 +OP4 E01F55 0 +OP4 E01F56 0 +OP4 E01F57 0 +OP4 E01F58 0 +OP4 E01F59 0 +OP4 E01F5A 0 +OP4 E01F5B 0 +OP4 E01F5C 0 +OP4 E01F5D 0 +OP4 E01F5E 0 +OP4 E01F5F 0 +OP4 E01F60 0 +OP4 E01F61 0 +OP4 E01F62 0 +OP4 E01F63 0 +OP4 E01F64 0 +OP4 E01F65 0 +OP4 E01F66 0 +OP4 E01F67 0 +OP4 E01F68 0 +OP4 E01F69 0 +OP4 E01F6A 0 +OP4 E01F6B 0 +OP4 E01F6C 0 +OP4 E01F6D 0 +OP4 E01F6E 0 +OP4 E01F6F 0 +OP4 E01F70 0 +OP4 E01F71 0 +OP4 E01F72 0 +OP4 E01F73 0 +OP4 E01F74 0 +OP4 E01F75 0 +OP4 E01F76 0 +OP4 E01F77 0 +OP4 E01F78 0 +OP4 E01F79 0 +OP4 E01F7A 0 +OP4 E01F7B 0 +OP4 E01F7C 0 +OP4 E01F7D 0 +OP4 E01F7E 0 +OP4 E01F7F 0 +OP4 E01F80 0 +OP4 E01F81 0 +OP4 E01F82 0 +OP4 E01F83 0 +OP4 E01F84 0 +OP4 E01F85 0 +OP4 E01F86 0 +OP4 E01F87 0 +OP4 E01F88 0 +OP4 E01F89 0 +OP4 E01F8A 0 +OP4 E01F8B 0 +OP4 E01F8C 0 +OP4 E01F8D 0 +OP4 E01F8E 0 +OP4 E01F8F 0 +OP4 E01F90 0 +OP4 E01F91 0 +OP4 E01F92 0 +OP4 E01F93 0 +OP4 E01F94 0 +OP4 E01F95 0 +OP4 E01F96 0 +OP4 E01F97 0 +OP4 E01F98 0 +OP4 E01F99 0 +OP4 E01F9A 0 +OP4 E01F9B 0 +OP4 E01F9C 0 +OP4 E01F9D 0 +OP4 E01F9E 0 +OP4 E01F9F 0 +OP4 E01FA0 0 +OP4 E01FA1 0 +OP4 E01FA2 0 +OP4 E01FA3 0 +OP4 E01FA4 0 +OP4 E01FA5 0 +OP4 E01FA6 0 +OP4 E01FA7 0 +OP4 E01FA8 0 +OP4 E01FA9 0 +OP4 E01FAA 0 +OP4 E01FAB 0 +OP4 E01FAC 0 +OP4 E01FAD 0 +OP4 E01FAE 0 +OP4 E01FAF 0 +OP4 E01FB0 0 +OP4 E01FB1 0 +OP4 E01FB2 0 +OP4 E01FB3 0 +OP4 E01FB4 0 +OP4 E01FB5 0 +OP4 E01FB6 0 +OP4 E01FB7 0 +OP4 E01FB8 0 +OP4 E01FB9 0 +OP4 E01FBA 0 +OP4 E01FBB 0 +OP4 E01FBC 0 +OP4 E01FBD 0 +OP4 E01FBE 0 +OP4 E01FBF 0 +OP4 E01FC0 0 +OP4 E01FC1 0 +OP4 E01FC2 0 +OP4 E01FC3 0 +OP4 E01FC4 0 +OP4 E01FC5 0 +OP4 E01FC6 0 +OP4 E01FC7 0 +OP4 E01FC8 0 +OP4 E01FC9 0 +OP4 E01FCA 0 +OP4 E01FCB 0 +OP4 E01FCC 0 +OP4 E01FCD 0 +OP4 E01FCE 0 +OP4 E01FCF 0 +OP4 E01FD0 0 +OP4 E01FD1 0 +OP4 E01FD2 0 +OP4 E01FD3 0 +OP4 E01FD4 0 +OP4 E01FD5 0 +OP4 E01FD6 0 +OP4 E01FD7 0 +OP4 E01FD8 0 +OP4 E01FD9 0 +OP4 E01FDA 0 +OP4 E01FDB 0 +OP4 E01FDC 0 +OP4 E01FDD 0 +OP4 E01FDE 0 +OP4 E01FDF 0 +OP4 E01FE0 0 +OP4 E01FE1 0 +OP4 E01FE2 0 +OP4 E01FE3 0 +OP4 E01FE4 0 +OP4 E01FE5 0 +OP4 E01FE6 0 +OP4 E01FE7 0 +OP4 E01FE8 0 +OP4 E01FE9 0 +OP4 E01FEA 0 +OP4 E01FEB 0 +OP4 E01FEC 0 +OP4 E01FED 0 +OP4 E01FEE 0 +OP4 E01FEF 0 +OP4 E01FF0 0 +OP4 E01FF1 0 +OP4 E01FF2 0 +OP4 E01FF3 0 +OP4 E01FF4 0 +OP4 E01FF5 0 +OP4 E01FF6 0 +OP4 E01FF7 0 +OP4 E01FF8 0 +OP4 E01FF9 0 +OP4 E01FFA 0 +OP4 E01FFB 0 +OP4 E01FFC 0 +OP4 E01FFD 0 +OP4 E01FFE 0 +OP4 E01FFF 0 +OP4 E02000 0 +OP4 E02001 0 +OP4 E02002 0 +OP4 E02003 0 +OP4 E02004 0 +OP4 E02005 0 +OP4 E02006 0 +OP4 E02007 0 +OP4 E02008 0 +OP4 E02009 0 +OP4 E0200A 0 +OP4 E0200B 0 +OP4 E0200C 0 +OP4 E0200D 0 +OP4 E0200E 0 +OP4 E0200F 0 +OP4 E02010 0 +OP4 E02011 0 +OP4 E02012 0 +OP4 E02013 0 +OP4 E02014 0 +OP4 E02015 0 +OP4 E02016 0 +OP4 E02017 0 +OP4 E02018 0 +OP4 E02019 0 +OP4 E0201A 0 +OP4 E0201B 0 +OP4 E0201C 0 +OP4 E0201D 0 +OP4 E0201E 0 +OP4 E0201F 0 +OP4 E02020 0 +OP4 E02021 0 +OP4 E02022 0 +OP4 E02023 0 +OP4 E02024 0 +OP4 E02025 0 +OP4 E02026 0 +OP4 E02027 0 +OP4 E02028 0 +OP4 E02029 0 +OP4 E0202A 0 +OP4 E0202B 0 +OP4 E0202C 0 +OP4 E0202D 0 +OP4 E0202E 0 +OP4 E0202F 0 +OP4 E02030 0 +OP4 E02031 0 +OP4 E02032 0 +OP4 E02033 0 +OP4 E02034 0 +OP4 E02035 0 +OP4 E02036 0 +OP4 E02037 0 +OP4 E02038 0 +OP4 E02039 0 +OP4 E0203A 0 +OP4 E0203B 0 +OP4 E0203C 0 +OP4 E0203D 0 +OP4 E0203E 0 +OP4 E0203F 0 +OP4 E02040 0 +OP4 E02041 0 +OP4 E02042 0 +OP4 E02043 0 +OP4 E02044 0 +OP4 E02045 0 +OP4 E02046 0 +OP4 E02047 0 +OP4 E02048 0 +OP4 E02049 0 +OP4 E0204A 0 +OP4 E0204B 0 +OP4 E0204C 0 +OP4 E0204D 0 +OP4 E0204E 0 +OP4 E0204F 0 +OP4 E02050 0 +OP4 E02051 0 +OP4 E02052 0 +OP4 E02053 0 +OP4 E02054 0 +OP4 E02055 0 +OP4 E02056 0 +OP4 E02057 0 +OP4 E02058 0 +OP4 E02059 0 +OP4 E0205A 0 +OP4 E0205B 0 +OP4 E0205C 0 +OP4 E0205D 0 +OP4 E0205E 0 +OP4 E0205F 0 +OP4 E02060 0 +OP4 E02061 0 +OP4 E02062 0 +OP4 E02063 0 +OP4 E02064 0 +OP4 E02065 0 +OP4 E02066 0 +OP4 E02067 0 +OP4 E02068 0 +OP4 E02069 0 +OP4 E0206A 0 +OP4 E0206B 0 +OP4 E0206C 0 +OP4 E0206D 0 +OP4 E0206E 0 +OP4 E0206F 0 +OP4 E02070 0 +OP4 E02071 0 +OP4 E02072 0 +OP4 E02073 0 +OP4 E02074 0 +OP4 E02075 0 +OP4 E02076 0 +OP4 E02077 0 +OP4 E02078 0 +OP4 E02079 0 +OP4 E0207A 0 +OP4 E0207B 0 +OP4 E0207C 0 +OP4 E0207D 0 +OP4 E0207E 0 +OP4 E0207F 0 +OP4 E02080 0 +OP4 E02081 0 +OP4 E02082 0 +OP4 E02083 0 +OP4 E02084 0 +OP4 E02085 0 +OP4 E02086 0 +OP4 E02087 0 +OP4 E02088 0 +OP4 E02089 0 +OP4 E0208A 0 +OP4 E0208B 0 +OP4 E0208C 0 +OP4 E0208D 0 +OP4 E0208E 0 +OP4 E0208F 0 +OP4 E02090 0 +OP4 E02091 0 +OP4 E02092 0 +OP4 E02093 0 +OP4 E02094 0 +OP4 E02095 0 +OP4 E02096 0 +OP4 E02097 0 +OP4 E02098 0 +OP4 E02099 0 +OP4 E0209A 0 +OP4 E0209B 0 +OP4 E0209C 0 +OP4 E0209D 0 +OP4 E0209E 0 +OP4 E0209F 0 +OP4 E020A0 0 +OP4 E020A1 0 +OP4 E020A2 0 +OP4 E020A3 0 +OP4 E020A4 0 +OP4 E020A5 0 +OP4 E020A6 0 +OP4 E020A7 0 +OP4 E020A8 0 +OP4 E020A9 0 +OP4 E020AA 0 +OP4 E020AB 0 +OP4 E020AC 0 +OP4 E020AD 0 +OP4 E020AE 0 +OP4 E020AF 0 +OP4 E020B0 0 +OP4 E020B1 0 +OP4 E020B2 0 +OP4 E020B3 0 +OP4 E020B4 0 +OP4 E020B5 0 +OP4 E020B6 0 +OP4 E020B7 0 +OP4 E020B8 0 +OP4 E020B9 0 +OP4 E020BA 0 +OP4 E020BB 0 +OP4 E020BC 0 +OP4 E020BD 0 +OP4 E020BE 0 +OP4 E020BF 0 +OP4 E020C0 0 +OP4 E020C1 0 +OP4 E020C2 0 +OP4 E020C3 0 +OP4 E020C4 0 +OP4 E020C5 0 +OP4 E020C6 0 +OP4 E020C7 0 +OP4 E020C8 0 +OP4 E020C9 0 +OP4 E020CA 0 +OP4 E020CB 0 +OP4 E020CC 0 +OP4 E020CD 0 +OP4 E020CE 0 +OP4 E020CF 0 +OP4 E020D0 0 +OP4 E020D1 0 +OP4 E020D2 0 +OP4 E020D3 0 +OP4 E020D4 0 +OP4 E020D5 0 +OP4 E020D6 0 +OP4 E020D7 0 +OP4 E020D8 0 +OP4 E020D9 0 +OP4 E020DA 0 +OP4 E020DB 0 +OP4 E020DC 0 +OP4 E020DD 0 +OP4 E020DE 0 +OP4 E020DF 0 +OP4 E020E0 0 +OP4 E020E1 0 +OP4 E020E2 0 +OP4 E020E3 0 +OP4 E020E4 0 +OP4 E020E5 0 +OP4 E020E6 0 +OP4 E020E7 0 +OP4 E020E8 0 +OP4 E020E9 0 +OP4 E020EA 0 +OP4 E020EB 0 +OP4 E020EC 0 +OP4 E020ED 0 +OP4 E020EE 0 +OP4 E020EF 0 +OP4 E020F0 0 +OP4 E020F1 0 +OP4 E020F2 0 +OP4 E020F3 0 +OP4 E020F4 0 +OP4 E020F5 0 +OP4 E020F6 0 +OP4 E020F7 0 +OP4 E020F8 0 +OP4 E020F9 0 +OP4 E020FA 0 +OP4 E020FB 0 +OP4 E020FC 0 +OP4 E020FD 0 +OP4 E020FE 0 +OP4 E020FF 0 +OP4 E02100 0 +OP4 E02101 0 +OP4 E02102 0 +OP4 E02103 0 +OP4 E02104 0 +OP4 E02105 0 +OP4 E02106 0 +OP4 E02107 0 +OP4 E02108 0 +OP4 E02109 0 +OP4 E0210A 0 +OP4 E0210B 0 +OP4 E0210C 0 +OP4 E0210D 0 +OP4 E0210E 0 +OP4 E0210F 0 +OP4 E02110 0 +OP4 E02111 0 +OP4 E02112 0 +OP4 E02113 0 +OP4 E02114 0 +OP4 E02115 0 +OP4 E02116 0 +OP4 E02117 0 +OP4 E02118 0 +OP4 E02119 0 +OP4 E0211A 0 +OP4 E0211B 0 +OP4 E0211C 0 +OP4 E0211D 0 +OP4 E0211E 0 +OP4 E0211F 0 +OP4 E02120 0 +OP4 E02121 0 +OP4 E02122 0 +OP4 E02123 0 +OP4 E02124 0 +OP4 E02125 0 +OP4 E02126 0 +OP4 E02127 0 +OP4 E02128 0 +OP4 E02129 0 +OP4 E0212A 0 +OP4 E0212B 0 +OP4 E0212C 0 +OP4 E0212D 0 +OP4 E0212E 0 +OP4 E0212F 0 +OP4 E02130 0 +OP4 E02131 0 +OP4 E02132 0 +OP4 E02133 0 +OP4 E02134 0 +OP4 E02135 0 +OP4 E02136 0 +OP4 E02137 0 +OP4 E02138 0 +OP4 E02139 0 +OP4 E0213A 0 +OP4 E0213B 0 +OP4 E0213C 0 +OP4 E0213D 0 +OP4 E0213E 0 +OP4 E0213F 0 +OP4 E02140 0 +OP4 E02141 0 +OP4 E02142 0 +OP4 E02143 0 +OP4 E02144 0 +OP4 E02145 0 +OP4 E02146 0 +OP4 E02147 0 +OP4 E02148 0 +OP4 E02149 0 +OP4 E0214A 0 +OP4 E0214B 0 +OP4 E0214C 0 +OP4 E0214D 0 +OP4 E0214E 0 +OP4 E0214F 0 +OP4 E02150 0 +OP4 E02151 0 +OP4 E02152 0 +OP4 E02153 0 +OP4 E02154 0 +OP4 E02155 0 +OP4 E02156 0 +OP4 E02157 0 +OP4 E02158 0 +OP4 E02159 0 +OP4 E0215A 0 +OP4 E0215B 0 +OP4 E0215C 0 +OP4 E0215D 0 +OP4 E0215E 0 +OP4 E0215F 0 +OP4 E02160 0 +OP4 E02161 0 +OP4 E02162 0 +OP4 E02163 0 +OP4 E02164 0 +OP4 E02165 0 +OP4 E02166 0 +OP4 E02167 0 +OP4 E02168 0 +OP4 E02169 0 +OP4 E0216A 0 +OP4 E0216B 0 +OP4 E0216C 0 +OP4 E0216D 0 +OP4 E0216E 0 +OP4 E0216F 0 +OP4 E02170 0 +OP4 E02171 0 +OP4 E02172 0 +OP4 E02173 0 +OP4 E02174 0 +OP4 E02175 0 +OP4 E02176 0 +OP4 E02177 0 +OP4 E02178 0 +OP4 E02179 0 +OP4 E0217A 0 +OP4 E0217B 0 +OP4 E0217C 0 +OP4 E0217D 0 +OP4 E0217E 0 +OP4 E0217F 0 +OP4 E02180 0 +OP4 E02181 0 +OP4 E02182 0 +OP4 E02183 0 +OP4 E02184 0 +OP4 E02185 0 +OP4 E02186 0 +OP4 E02187 0 +OP4 E02188 0 +OP4 E02189 0 +OP4 E0218A 0 +OP4 E0218B 0 +OP4 E0218C 0 +OP4 E0218D 0 +OP4 E0218E 0 +OP4 E0218F 0 +OP4 E02190 0 +OP4 E02191 0 +OP4 E02192 0 +OP4 E02193 0 +OP4 E02194 0 +OP4 E02195 0 +OP4 E02196 0 +OP4 E02197 0 +OP4 E02198 0 +OP4 E02199 0 +OP4 E0219A 0 +OP4 E0219B 0 +OP4 E0219C 0 +OP4 E0219D 0 +OP4 E0219E 0 +OP4 E0219F 0 +OP4 E021A0 0 +OP4 E021A1 0 +OP4 E021A2 0 +OP4 E021A3 0 +OP4 E021A4 0 +OP4 E021A5 0 +OP4 E021A6 0 +OP4 E021A7 0 +OP4 E021A8 0 +OP4 E021A9 0 +OP4 E021AA 0 +OP4 E021AB 0 +OP4 E021AC 0 +OP4 E021AD 0 +OP4 E021AE 0 +OP4 E021AF 0 +OP4 E021B0 0 +OP4 E021B1 0 +OP4 E021B2 0 +OP4 E021B3 0 +OP4 E021B4 0 +OP4 E021B5 0 +OP4 E021B6 0 +OP4 E021B7 0 +OP4 E021B8 0 +OP4 E021B9 0 +OP4 E021BA 0 +OP4 E021BB 0 +OP4 E021BC 0 +OP4 E021BD 0 +OP4 E021BE 0 +OP4 E021BF 0 +OP4 E021C0 0 +OP4 E021C1 0 +OP4 E021C2 0 +OP4 E021C3 0 +OP4 E021C4 0 +OP4 E021C5 0 +OP4 E021C6 0 +OP4 E021C7 0 +OP4 E021C8 0 +OP4 E021C9 0 +OP4 E021CA 0 +OP4 E021CB 0 +OP4 E021CC 0 +OP4 E021CD 0 +OP4 E021CE 0 +OP4 E021CF 0 +OP4 E021D0 0 +OP4 E021D1 0 +OP4 E021D2 0 +OP4 E021D3 0 +OP4 E021D4 0 +OP4 E021D5 0 +OP4 E021D6 0 +OP4 E021D7 0 +OP4 E021D8 0 +OP4 E021D9 0 +OP4 E021DA 0 +OP4 E021DB 0 +OP4 E021DC 0 +OP4 E021DD 0 +OP4 E021DE 0 +OP4 E021DF 0 +OP4 E021E0 0 +OP4 E021E1 0 +OP4 E021E2 0 +OP4 E021E3 0 +OP4 E021E4 0 +OP4 E021E5 0 +OP4 E021E6 0 +OP4 E021E7 0 +OP4 E021E8 0 +OP4 E021E9 0 +OP4 E021EA 0 +OP4 E021EB 0 +OP4 E021EC 0 +OP4 E021ED 0 +OP4 E021EE 0 +OP4 E021EF 0 +OP4 E021F0 0 +OP4 E021F1 0 +OP4 E021F2 0 +OP4 E021F3 0 +OP4 E021F4 0 +OP4 E021F5 0 +OP4 E021F6 0 +OP4 E021F7 0 +OP4 E021F8 0 +OP4 E021F9 0 +OP4 E021FA 0 +OP4 E021FB 0 +OP4 E021FC 0 +OP4 E021FD 0 +OP4 E021FE 0 +OP4 E021FF 0 +OP4 E02200 0 +OP4 E02201 0 +OP4 E02202 0 +OP4 E02203 0 +OP4 E02204 0 +OP4 E02205 0 +OP4 E02206 0 +OP4 E02207 0 +OP4 E02208 0 +OP4 E02209 0 +OP4 E0220A 0 +OP4 E0220B 0 +OP4 E0220C 0 +OP4 E0220D 0 +OP4 E0220E 0 +OP4 E0220F 0 +OP4 E02210 0 +OP4 E02211 0 +OP4 E02212 0 +OP4 E02213 0 +OP4 E02214 0 +OP4 E02215 0 +OP4 E02216 0 +OP4 E02217 0 +OP4 E02218 0 +OP4 E02219 0 +OP4 E0221A 0 +OP4 E0221B 0 +OP4 E0221C 0 +OP4 E0221D 0 +OP4 E0221E 0 +OP4 E0221F 0 +OP4 E02220 0 +OP4 E02221 0 +OP4 E02222 0 +OP4 E02223 0 +OP4 E02224 0 +OP4 E02225 0 +OP4 E02226 0 +OP4 E02227 0 +OP4 E02228 0 +OP4 E02229 0 +OP4 E0222A 0 +OP4 E0222B 0 +OP4 E0222C 0 +OP4 E0222D 0 +OP4 E0222E 0 +OP4 E0222F 0 +OP4 E02230 0 +OP4 E02231 0 +OP4 E02232 0 +OP4 E02233 0 +OP4 E02234 0 +OP4 E02235 0 +OP4 E02236 0 +OP4 E02237 0 +OP4 E02238 0 +OP4 E02239 0 +OP4 E0223A 0 +OP4 E0223B 0 +OP4 E0223C 0 +OP4 E0223D 0 +OP4 E0223E 0 +OP4 E0223F 0 +OP4 E02240 0 +OP4 E02241 0 +OP4 E02242 0 +OP4 E02243 0 +OP4 E02244 0 +OP4 E02245 0 +OP4 E02246 0 +OP4 E02247 0 +OP4 E02248 0 +OP4 E02249 0 +OP4 E0224A 0 +OP4 E0224B 0 +OP4 E0224C 0 +OP4 E0224D 0 +OP4 E0224E 0 +OP4 E0224F 0 +OP4 E02250 0 +OP4 E02251 0 +OP4 E02252 0 +OP4 E02253 0 +OP4 E02254 0 +OP4 E02255 0 +OP4 E02256 0 +OP4 E02257 0 +OP4 E02258 0 +OP4 E02259 0 +OP4 E0225A 0 +OP4 E0225B 0 +OP4 E0225C 0 +OP4 E0225D 0 +OP4 E0225E 0 +OP4 E0225F 0 +OP4 E02260 0 +OP4 E02261 0 +OP4 E02262 0 +OP4 E02263 0 +OP4 E02264 0 +OP4 E02265 0 +OP4 E02266 0 +OP4 E02267 0 +OP4 E02268 0 +OP4 E02269 0 +OP4 E0226A 0 +OP4 E0226B 0 +OP4 E0226C 0 +OP4 E0226D 0 +OP4 E0226E 0 +OP4 E0226F 0 +OP4 E02270 0 +OP4 E02271 0 +OP4 E02272 0 +OP4 E02273 0 +OP4 E02274 0 +OP4 E02275 0 +OP4 E02276 0 +OP4 E02277 0 +OP4 E02278 0 +OP4 E02279 0 +OP4 E0227A 0 +OP4 E0227B 0 +OP4 E0227C 0 +OP4 E0227D 0 +OP4 E0227E 0 +OP4 E0227F 0 +OP4 E02280 0 +OP4 E02281 0 +OP4 E02282 0 +OP4 E02283 0 +OP4 E02284 0 +OP4 E02285 0 +OP4 E02286 0 +OP4 E02287 0 +OP4 E02288 0 +OP4 E02289 0 +OP4 E0228A 0 +OP4 E0228B 0 +OP4 E0228C 0 +OP4 E0228D 0 +OP4 E0228E 0 +OP4 E0228F 0 +OP4 E02290 0 +OP4 E02291 0 +OP4 E02292 0 +OP4 E02293 0 +OP4 E02294 0 +OP4 E02295 0 +OP4 E02296 0 +OP4 E02297 0 +OP4 E02298 0 +OP4 E02299 0 +OP4 E0229A 0 +OP4 E0229B 0 +OP4 E0229C 0 +OP4 E0229D 0 +OP4 E0229E 0 +OP4 E0229F 0 +OP4 E022A0 0 +OP4 E022A1 0 +OP4 E022A2 0 +OP4 E022A3 0 +OP4 E022A4 0 +OP4 E022A5 0 +OP4 E022A6 0 +OP4 E022A7 0 +OP4 E022A8 0 +OP4 E022A9 0 +OP4 E022AA 0 +OP4 E022AB 0 +OP4 E022AC 0 +OP4 E022AD 0 +OP4 E022AE 0 +OP4 E022AF 0 +OP4 E022B0 0 +OP4 E022B1 0 +OP4 E022B2 0 +OP4 E022B3 0 +OP4 E022B4 0 +OP4 E022B5 0 +OP4 E022B6 0 +OP4 E022B7 0 +OP4 E022B8 0 +OP4 E022B9 0 +OP4 E022BA 0 +OP4 E022BB 0 +OP4 E022BC 0 +OP4 E022BD 0 +OP4 E022BE 0 +OP4 E022BF 0 +OP4 E022C0 0 +OP4 E022C1 0 +OP4 E022C2 0 +OP4 E022C3 0 +OP4 E022C4 0 +OP4 E022C5 0 +OP4 E022C6 0 +OP4 E022C7 0 +OP4 E022C8 0 +OP4 E022C9 0 +OP4 E022CA 0 +OP4 E022CB 0 +OP4 E022CC 0 +OP4 E022CD 0 +OP4 E022CE 0 +OP4 E022CF 0 +OP4 E022D0 0 +OP4 E022D1 0 +OP4 E022D2 0 +OP4 E022D3 0 +OP4 E022D4 0 +OP4 E022D5 0 +OP4 E022D6 0 +OP4 E022D7 0 +OP4 E022D8 0 +OP4 E022D9 0 +OP4 E022DA 0 +OP4 E022DB 0 +OP4 E022DC 0 +OP4 E022DD 0 +OP4 E022DE 0 +OP4 E022DF 0 +OP4 E022E0 0 +OP4 E022E1 0 +OP4 E022E2 0 +OP4 E022E3 0 +OP4 E022E4 0 +OP4 E022E5 0 +OP4 E022E6 0 +OP4 E022E7 0 +OP4 E022E8 0 +OP4 E022E9 0 +OP4 E022EA 0 +OP4 E022EB 0 +OP4 E022EC 0 +OP4 E022ED 0 +OP4 E022EE 0 +OP4 E022EF 0 +OP4 E022F0 0 +OP4 E022F1 0 +OP4 E022F2 0 +OP4 E022F3 0 +OP4 E022F4 0 +OP4 E022F5 0 +OP4 E022F6 0 +OP4 E022F7 0 +OP4 E022F8 0 +OP4 E022F9 0 +OP4 E022FA 0 +OP4 E022FB 0 +OP4 E022FC 0 +OP4 E022FD 0 +OP4 E022FE 0 +OP4 E022FF 0 +OP4 E02300 0 +OP4 E02301 0 +OP4 E02302 0 +OP4 E02303 0 +OP4 E02304 0 +OP4 E02305 0 +OP4 E02306 0 +OP4 E02307 0 +OP4 E02308 0 +OP4 E02309 0 +OP4 E0230A 0 +OP4 E0230B 0 +OP4 E0230C 0 +OP4 E0230D 0 +OP4 E0230E 0 +OP4 E0230F 0 +OP4 E02310 0 +OP4 E02311 0 +OP4 E02312 0 +OP4 E02313 0 +OP4 E02314 0 +OP4 E02315 0 +OP4 E02316 0 +OP4 E02317 0 +OP4 E02318 0 +OP4 E02319 0 +OP4 E0231A 0 +OP4 E0231B 0 +OP4 E0231C 0 +OP4 E0231D 0 +OP4 E0231E 0 +OP4 E0231F 0 +OP4 E02320 0 +OP4 E02321 0 +OP4 E02322 0 +OP4 E02323 0 +OP4 E02324 0 +OP4 E02325 0 +OP4 E02326 0 +OP4 E02327 0 +OP4 E02328 0 +OP4 E02329 0 +OP4 E0232A 0 +OP4 E0232B 0 +OP4 E0232C 0 +OP4 E0232D 0 +OP4 E0232E 0 +OP4 E0232F 0 +OP4 E02330 0 +OP4 E02331 0 +OP4 E02332 0 +OP4 E02333 0 +OP4 E02334 0 +OP4 E02335 0 +OP4 E02336 0 +OP4 E02337 0 +OP4 E02338 0 +OP4 E02339 0 +OP4 E0233A 0 +OP4 E0233B 0 +OP4 E0233C 0 +OP4 E0233D 0 +OP4 E0233E 0 +OP4 E0233F 0 +OP4 E02340 0 +OP4 E02341 0 +OP4 E02342 0 +OP4 E02343 0 +OP4 E02344 0 +OP4 E02345 0 +OP4 E02346 0 +OP4 E02347 0 +OP4 E02348 0 +OP4 E02349 0 +OP4 E0234A 0 +OP4 E0234B 0 +OP4 E0234C 0 +OP4 E0234D 0 +OP4 E0234E 0 +OP4 E0234F 0 +OP4 E02350 0 +OP4 E02351 0 +OP4 E02352 0 +OP4 E02353 0 +OP4 E02354 0 +OP4 E02355 0 +OP4 E02356 0 +OP4 E02357 0 +OP4 E02358 0 +OP4 E02359 0 +OP4 E0235A 0 +OP4 E0235B 0 +OP4 E0235C 0 +OP4 E0235D 0 +OP4 E0235E 0 +OP4 E0235F 0 +OP4 E02360 0 +OP4 E02361 0 +OP4 E02362 0 +OP4 E02363 0 +OP4 E02364 0 +OP4 E02365 0 +OP4 E02366 0 +OP4 E02367 0 +OP4 E02368 0 +OP4 E02369 0 +OP4 E0236A 0 +OP4 E0236B 0 +OP4 E0236C 0 +OP4 E0236D 0 +OP4 E0236E 0 +OP4 E0236F 0 +OP4 E02370 0 +OP4 E02371 0 +OP4 E02372 0 +OP4 E02373 0 +OP4 E02374 0 +OP4 E02375 0 +OP4 E02376 0 +OP4 E02377 0 +OP4 E02378 0 +OP4 E02379 0 +OP4 E0237A 0 +OP4 E0237B 0 +OP4 E0237C 0 +OP4 E0237D 0 +OP4 E0237E 0 +OP4 E0237F 0 +OP4 E02380 0 +OP4 E02381 0 +OP4 E02382 0 +OP4 E02383 0 +OP4 E02384 0 +OP4 E02385 0 +OP4 E02386 0 +OP4 E02387 0 +OP4 E02388 0 +OP4 E02389 0 +OP4 E0238A 0 +OP4 E0238B 0 +OP4 E0238C 0 +OP4 E0238D 0 +OP4 E0238E 0 +OP4 E0238F 0 +OP4 E02390 0 +OP4 E02391 0 +OP4 E02392 0 +OP4 E02393 0 +OP4 E02394 0 +OP4 E02395 0 +OP4 E02396 0 +OP4 E02397 0 +OP4 E02398 0 +OP4 E02399 0 +OP4 E0239A 0 +OP4 E0239B 0 +OP4 E0239C 0 +OP4 E0239D 0 +OP4 E0239E 0 +OP4 E0239F 0 +OP4 E023A0 0 +OP4 E023A1 0 +OP4 E023A2 0 +OP4 E023A3 0 +OP4 E023A4 0 +OP4 E023A5 0 +OP4 E023A6 0 +OP4 E023A7 0 +OP4 E023A8 0 +OP4 E023A9 0 +OP4 E023AA 0 +OP4 E023AB 0 +OP4 E023AC 0 +OP4 E023AD 0 +OP4 E023AE 0 +OP4 E023AF 0 +OP4 E023B0 0 +OP4 E023B1 0 +OP4 E023B2 0 +OP4 E023B3 0 +OP4 E023B4 0 +OP4 E023B5 0 +OP4 E023B6 0 +OP4 E023B7 0 +OP4 E023B8 0 +OP4 E023B9 0 +OP4 E023BA 0 +OP4 E023BB 0 +OP4 E023BC 0 +OP4 E023BD 0 +OP4 E023BE 0 +OP4 E023BF 0 +OP4 E023C0 0 +OP4 E023C1 0 +OP4 E023C2 0 +OP4 E023C3 0 +OP4 E023C4 0 +OP4 E023C5 0 +OP4 E023C6 0 +OP4 E023C7 0 +OP4 E023C8 0 +OP4 E023C9 0 +OP4 E023CA 0 +OP4 E023CB 0 +OP4 E023CC 0 +OP4 E023CD 0 +OP4 E023CE 0 +OP4 E023CF 0 +OP4 E023D0 0 +OP4 E023D1 0 +OP4 E023D2 0 +OP4 E023D3 0 +OP4 E023D4 0 +OP4 E023D5 0 +OP4 E023D6 0 +OP4 E023D7 0 +OP4 E023D8 0 +OP4 E023D9 0 +OP4 E023DA 0 +OP4 E023DB 0 +OP4 E023DC 0 +OP4 E023DD 0 +OP4 E023DE 0 +OP4 E023DF 0 +OP4 E023E0 0 +OP4 E023E1 0 +OP4 E023E2 0 +OP4 E023E3 0 +OP4 E023E4 0 +OP4 E023E5 0 +OP4 E023E6 0 +OP4 E023E7 0 +OP4 E023E8 0 +OP4 E023E9 0 +OP4 E023EA 0 +OP4 E023EB 0 +OP4 E023EC 0 +OP4 E023ED 0 +OP4 E023EE 0 +OP4 E023EF 0 +OP4 E023F0 0 +OP4 E023F1 0 +OP4 E023F2 0 +OP4 E023F3 0 +OP4 E023F4 0 +OP4 E023F5 0 +OP4 E023F6 0 +OP4 E023F7 0 +OP4 E023F8 0 +OP4 E023F9 0 +OP4 E023FA 0 +OP4 E023FB 0 +OP4 E023FC 0 +OP4 E023FD 0 +OP4 E023FE 0 +OP4 E023FF 0 +OP4 E02400 0 +OP4 E02401 0 +OP4 E02402 0 +OP4 E02403 0 +OP4 E02404 0 +OP4 E02405 0 +OP4 E02406 0 +OP4 E02407 0 +OP4 E02408 0 +OP4 E02409 0 +OP4 E0240A 0 +OP4 E0240B 0 +OP4 E0240C 0 +OP4 E0240D 0 +OP4 E0240E 0 +OP4 E0240F 0 +OP4 E02410 0 +OP4 E02411 0 +OP4 E02412 0 +OP4 E02413 0 +OP4 E02414 0 +OP4 E02415 0 +OP4 E02416 0 +OP4 E02417 0 +OP4 E02418 0 +OP4 E02419 0 +OP4 E0241A 0 +OP4 E0241B 0 +OP4 E0241C 0 +OP4 E0241D 0 +OP4 E0241E 0 +OP4 E0241F 0 +OP4 E02420 0 +OP4 E02421 0 +OP4 E02422 0 +OP4 E02423 0 +OP4 E02424 0 +OP4 E02425 0 +OP4 E02426 0 +OP4 E02427 0 +OP4 E02428 0 +OP4 E02429 0 +OP4 E0242A 0 +OP4 E0242B 0 +OP4 E0242C 0 +OP4 E0242D 0 +OP4 E0242E 0 +OP4 E0242F 0 +OP4 E02430 0 +OP4 E02431 0 +OP4 E02432 0 +OP4 E02433 0 +OP4 E02434 0 +OP4 E02435 0 +OP4 E02436 0 +OP4 E02437 0 +OP4 E02438 0 +OP4 E02439 0 +OP4 E0243A 0 +OP4 E0243B 0 +OP4 E0243C 0 +OP4 E0243D 0 +OP4 E0243E 0 +OP4 E0243F 0 +OP4 E02440 0 +OP4 E02441 0 +OP4 E02442 0 +OP4 E02443 0 +OP4 E02444 0 +OP4 E02445 0 +OP4 E02446 0 +OP4 E02447 0 +OP4 E02448 0 +OP4 E02449 0 +OP4 E0244A 0 +OP4 E0244B 0 +OP4 E0244C 0 +OP4 E0244D 0 +OP4 E0244E 0 +OP4 E0244F 0 +OP4 E02450 0 +OP4 E02451 0 +OP4 E02452 0 +OP4 E02453 0 +OP4 E02454 0 +OP4 E02455 0 +OP4 E02456 0 +OP4 E02457 0 +OP4 E02458 0 +OP4 E02459 0 +OP4 E0245A 0 +OP4 E0245B 0 +OP4 E0245C 0 +OP4 E0245D 0 +OP4 E0245E 0 +OP4 E0245F 0 +OP4 E02460 0 +OP4 E02461 0 +OP4 E02462 0 +OP4 E02463 0 +OP4 E02464 0 +OP4 E02465 0 +OP4 E02466 0 +OP4 E02467 0 +OP4 E02468 0 +OP4 E02469 0 +OP4 E0246A 0 +OP4 E0246B 0 +OP4 E0246C 0 +OP4 E0246D 0 +OP4 E0246E 0 +OP4 E0246F 0 +OP4 E02470 0 +OP4 E02471 0 +OP4 E02472 0 +OP4 E02473 0 +OP4 E02474 0 +OP4 E02475 0 +OP4 E02476 0 +OP4 E02477 0 +OP4 E02478 0 +OP4 E02479 0 +OP4 E0247A 0 +OP4 E0247B 0 +OP4 E0247C 0 +OP4 E0247D 0 +OP4 E0247E 0 +OP4 E0247F 0 +OP4 E02480 0 +OP4 E02481 0 +OP4 E02482 0 +OP4 E02483 0 +OP4 E02484 0 +OP4 E02485 0 +OP4 E02486 0 +OP4 E02487 0 +OP4 E02488 0 +OP4 E02489 0 +OP4 E0248A 0 +OP4 E0248B 0 +OP4 E0248C 0 +OP4 E0248D 0 +OP4 E0248E 0 +OP4 E0248F 0 +OP4 E02490 0 +OP4 E02491 0 +OP4 E02492 0 +OP4 E02493 0 +OP4 E02494 0 +OP4 E02495 0 +OP4 E02496 0 +OP4 E02497 0 +OP4 E02498 0 +OP4 E02499 0 +OP4 E0249A 0 +OP4 E0249B 0 +OP4 E0249C 0 +OP4 E0249D 0 +OP4 E0249E 0 +OP4 E0249F 0 +OP4 E024A0 0 +OP4 E024A1 0 +OP4 E024A2 0 +OP4 E024A3 0 +OP4 E024A4 0 +OP4 E024A5 0 +OP4 E024A6 0 +OP4 E024A7 0 +OP4 E024A8 0 +OP4 E024A9 0 +OP4 E024AA 0 +OP4 E024AB 0 +OP4 E024AC 0 +OP4 E024AD 0 +OP4 E024AE 0 +OP4 E024AF 0 +OP4 E024B0 0 +OP4 E024B1 0 +OP4 E024B2 0 +OP4 E024B3 0 +OP4 E024B4 0 +OP4 E024B5 0 +OP4 E024B6 0 +OP4 E024B7 0 +OP4 E024B8 0 +OP4 E024B9 0 +OP4 E024BA 0 +OP4 E024BB 0 +OP4 E024BC 0 +OP4 E024BD 0 +OP4 E024BE 0 +OP4 E024BF 0 +OP4 E024C0 0 +OP4 E024C1 0 +OP4 E024C2 0 +OP4 E024C3 0 +OP4 E024C4 0 +OP4 E024C5 0 +OP4 E024C6 0 +OP4 E024C7 0 +OP4 E024C8 0 +OP4 E024C9 0 +OP4 E024CA 0 +OP4 E024CB 0 +OP4 E024CC 0 +OP4 E024CD 0 +OP4 E024CE 0 +OP4 E024CF 0 +OP4 E024D0 0 +OP4 E024D1 0 +OP4 E024D2 0 +OP4 E024D3 0 +OP4 E024D4 0 +OP4 E024D5 0 +OP4 E024D6 0 +OP4 E024D7 0 +OP4 E024D8 0 +OP4 E024D9 0 +OP4 E024DA 0 +OP4 E024DB 0 +OP4 E024DC 0 +OP4 E024DD 0 +OP4 E024DE 0 +OP4 E024DF 0 +OP4 E024E0 0 +OP4 E024E1 0 +OP4 E024E2 0 +OP4 E024E3 0 +OP4 E024E4 0 +OP4 E024E5 0 +OP4 E024E6 0 +OP4 E024E7 0 +OP4 E024E8 0 +OP4 E024E9 0 +OP4 E024EA 0 +OP4 E024EB 0 +OP4 E024EC 0 +OP4 E024ED 0 +OP4 E024EE 0 +OP4 E024EF 0 +OP4 E024F0 0 +OP4 E024F1 0 +OP4 E024F2 0 +OP4 E024F3 0 +OP4 E024F4 0 +OP4 E024F5 0 +OP4 E024F6 0 +OP4 E024F7 0 +OP4 E024F8 0 +OP4 E024F9 0 +OP4 E024FA 0 +OP4 E024FB 0 +OP4 E024FC 0 +OP4 E024FD 0 +OP4 E024FE 0 +OP4 E024FF 0 +OP4 E02500 0 +OP4 E02501 0 +OP4 E02502 0 +OP4 E02503 0 +OP4 E02504 0 +OP4 E02505 0 +OP4 E02506 0 +OP4 E02507 0 +OP4 E02508 0 +OP4 E02509 0 +OP4 E0250A 0 +OP4 E0250B 0 +OP4 E0250C 0 +OP4 E0250D 0 +OP4 E0250E 0 +OP4 E0250F 0 +OP4 E02510 0 +OP4 E02511 0 +OP4 E02512 0 +OP4 E02513 0 +OP4 E02514 0 +OP4 E02515 0 +OP4 E02516 0 +OP4 E02517 0 +OP4 E02518 0 +OP4 E02519 0 +OP4 E0251A 0 +OP4 E0251B 0 +OP4 E0251C 0 +OP4 E0251D 0 +OP4 E0251E 0 +OP4 E0251F 0 +OP4 E02520 0 +OP4 E02521 0 +OP4 E02522 0 +OP4 E02523 0 +OP4 E02524 0 +OP4 E02525 0 +OP4 E02526 0 +OP4 E02527 0 +OP4 E02528 0 +OP4 E02529 0 +OP4 E0252A 0 +OP4 E0252B 0 +OP4 E0252C 0 +OP4 E0252D 0 +OP4 E0252E 0 +OP4 E0252F 0 +OP4 E02530 0 +OP4 E02531 0 +OP4 E02532 0 +OP4 E02533 0 +OP4 E02534 0 +OP4 E02535 0 +OP4 E02536 0 +OP4 E02537 0 +OP4 E02538 0 +OP4 E02539 0 +OP4 E0253A 0 +OP4 E0253B 0 +OP4 E0253C 0 +OP4 E0253D 0 +OP4 E0253E 0 +OP4 E0253F 0 +OP4 E02540 0 +OP4 E02541 0 +OP4 E02542 0 +OP4 E02543 0 +OP4 E02544 0 +OP4 E02545 0 +OP4 E02546 0 +OP4 E02547 0 +OP4 E02548 0 +OP4 E02549 0 +OP4 E0254A 0 +OP4 E0254B 0 +OP4 E0254C 0 +OP4 E0254D 0 +OP4 E0254E 0 +OP4 E0254F 0 +OP4 E02550 0 +OP4 E02551 0 +OP4 E02552 0 +OP4 E02553 0 +OP4 E02554 0 +OP4 E02555 0 +OP4 E02556 0 +OP4 E02557 0 +OP4 E02558 0 +OP4 E02559 0 +OP4 E0255A 0 +OP4 E0255B 0 +OP4 E0255C 0 +OP4 E0255D 0 +OP4 E0255E 0 +OP4 E0255F 0 +OP4 E02560 0 +OP4 E02561 0 +OP4 E02562 0 +OP4 E02563 0 +OP4 E02564 0 +OP4 E02565 0 +OP4 E02566 0 +OP4 E02567 0 +OP4 E02568 0 +OP4 E02569 0 +OP4 E0256A 0 +OP4 E0256B 0 +OP4 E0256C 0 +OP4 E0256D 0 +OP4 E0256E 0 +OP4 E0256F 0 +OP4 E02570 0 +OP4 E02571 0 +OP4 E02572 0 +OP4 E02573 0 +OP4 E02574 0 +OP4 E02575 0 +OP4 E02576 0 +OP4 E02577 0 +OP4 E02578 0 +OP4 E02579 0 +OP4 E0257A 0 +OP4 E0257B 0 +OP4 E0257C 0 +OP4 E0257D 0 +OP4 E0257E 0 +OP4 E0257F 0 +OP4 E02580 0 +OP4 E02581 0 +OP4 E02582 0 +OP4 E02583 0 +OP4 E02584 0 +OP4 E02585 0 +OP4 E02586 0 +OP4 E02587 0 +OP4 E02588 0 +OP4 E02589 0 +OP4 E0258A 0 +OP4 E0258B 0 +OP4 E0258C 0 +OP4 E0258D 0 +OP4 E0258E 0 +OP4 E0258F 0 +OP4 E02590 0 +OP4 E02591 0 +OP4 E02592 0 +OP4 E02593 0 +OP4 E02594 0 +OP4 E02595 0 +OP4 E02596 0 +OP4 E02597 0 +OP4 E02598 0 +OP4 E02599 0 +OP4 E0259A 0 +OP4 E0259B 0 +OP4 E0259C 0 +OP4 E0259D 0 +OP4 E0259E 0 +OP4 E0259F 0 +OP4 E025A0 0 +OP4 E025A1 0 +OP4 E025A2 0 +OP4 E025A3 0 +OP4 E025A4 0 +OP4 E025A5 0 +OP4 E025A6 0 +OP4 E025A7 0 +OP4 E025A8 0 +OP4 E025A9 0 +OP4 E025AA 0 +OP4 E025AB 0 +OP4 E025AC 0 +OP4 E025AD 0 +OP4 E025AE 0 +OP4 E025AF 0 +OP4 E025B0 0 +OP4 E025B1 0 +OP4 E025B2 0 +OP4 E025B3 0 +OP4 E025B4 0 +OP4 E025B5 0 +OP4 E025B6 0 +OP4 E025B7 0 +OP4 E025B8 0 +OP4 E025B9 0 +OP4 E025BA 0 +OP4 E025BB 0 +OP4 E025BC 0 +OP4 E025BD 0 +OP4 E025BE 0 +OP4 E025BF 0 +OP4 E025C0 0 +OP4 E025C1 0 +OP4 E025C2 0 +OP4 E025C3 0 +OP4 E025C4 0 +OP4 E025C5 0 +OP4 E025C6 0 +OP4 E025C7 0 +OP4 E025C8 0 +OP4 E025C9 0 +OP4 E025CA 0 +OP4 E025CB 0 +OP4 E025CC 0 +OP4 E025CD 0 +OP4 E025CE 0 +OP4 E025CF 0 +OP4 E025D0 0 +OP4 E025D1 0 +OP4 E025D2 0 +OP4 E025D3 0 +OP4 E025D4 0 +OP4 E025D5 0 +OP4 E025D6 0 +OP4 E025D7 0 +OP4 E025D8 0 +OP4 E025D9 0 +OP4 E025DA 0 +OP4 E025DB 0 +OP4 E025DC 0 +OP4 E025DD 0 +OP4 E025DE 0 +OP4 E025DF 0 +OP4 E025E0 0 +OP4 E025E1 0 +OP4 E025E2 0 +OP4 E025E3 0 +OP4 E025E4 0 +OP4 E025E5 0 +OP4 E025E6 0 +OP4 E025E7 0 +OP4 E025E8 0 +OP4 E025E9 0 +OP4 E025EA 0 +OP4 E025EB 0 +OP4 E025EC 0 +OP4 E025ED 0 +OP4 E025EE 0 +OP4 E025EF 0 +OP4 E025F0 0 +OP4 E025F1 0 +OP4 E025F2 0 +OP4 E025F3 0 +OP4 E025F4 0 +OP4 E025F5 0 +OP4 E025F6 0 +OP4 E025F7 0 +OP4 E025F8 0 +OP4 E025F9 0 +OP4 E025FA 0 +OP4 E025FB 0 +OP4 E025FC 0 +OP4 E025FD 0 +OP4 E025FE 0 +OP4 E025FF 0 +OP4 E02600 0 +OP4 E02601 0 +OP4 E02602 0 +OP4 E02603 0 +OP4 E02604 0 +OP4 E02605 0 +OP4 E02606 0 +OP4 E02607 0 +OP4 E02608 0 +OP4 E02609 0 +OP4 E0260A 0 +OP4 E0260B 0 +OP4 E0260C 0 +OP4 E0260D 0 +OP4 E0260E 0 +OP4 E0260F 0 +OP4 E02610 0 +OP4 E02611 0 +OP4 E02612 0 +OP4 E02613 0 +OP4 E02614 0 +OP4 E02615 0 +OP4 E02616 0 +OP4 E02617 0 +OP4 E02618 0 +OP4 E02619 0 +OP4 E0261A 0 +OP4 E0261B 0 +OP4 E0261C 0 +OP4 E0261D 0 +OP4 E0261E 0 +OP4 E0261F 0 +OP4 E02620 0 +OP4 E02621 0 +OP4 E02622 0 +OP4 E02623 0 +OP4 E02624 0 +OP4 E02625 0 +OP4 E02626 0 +OP4 E02627 0 +OP4 E02628 0 +OP4 E02629 0 +OP4 E0262A 0 +OP4 E0262B 0 +OP4 E0262C 0 +OP4 E0262D 0 +OP4 E0262E 0 +OP4 E0262F 0 +OP4 E02630 0 +OP4 E02631 0 +OP4 E02632 0 +OP4 E02633 0 +OP4 E02634 0 +OP4 E02635 0 +OP4 E02636 0 +OP4 E02637 0 +OP4 E02638 0 +OP4 E02639 0 +OP4 E0263A 0 +OP4 E0263B 0 +OP4 E0263C 0 +OP4 E0263D 0 +OP4 E0263E 0 +OP4 E0263F 0 +OP4 E02640 0 +OP4 E02641 0 +OP4 E02642 0 +OP4 E02643 0 +OP4 E02644 0 +OP4 E02645 0 +OP4 E02646 0 +OP4 E02647 0 +OP4 E02648 0 +OP4 E02649 0 +OP4 E0264A 0 +OP4 E0264B 0 +OP4 E0264C 0 +OP4 E0264D 0 +OP4 E0264E 0 +OP4 E0264F 0 +OP4 E02650 0 +OP4 E02651 0 +OP4 E02652 0 +OP4 E02653 0 +OP4 E02654 0 +OP4 E02655 0 +OP4 E02656 0 +OP4 E02657 0 +OP4 E02658 0 +OP4 E02659 0 +OP4 E0265A 0 +OP4 E0265B 0 +OP4 E0265C 0 +OP4 E0265D 0 +OP4 E0265E 0 +OP4 E0265F 0 +OP4 E02660 0 +OP4 E02661 0 +OP4 E02662 0 +OP4 E02663 0 +OP4 E02664 0 +OP4 E02665 0 +OP4 E02666 0 +OP4 E02667 0 +OP4 E02668 0 +OP4 E02669 0 +OP4 E0266A 0 +OP4 E0266B 0 +OP4 E0266C 0 +OP4 E0266D 0 +OP4 E0266E 0 +OP4 E0266F 0 +OP4 E02670 0 +OP4 E02671 0 +OP4 E02672 0 +OP4 E02673 0 +OP4 E02674 0 +OP4 E02675 0 +OP4 E02676 0 +OP4 E02677 0 +OP4 E02678 0 +OP4 E02679 0 +OP4 E0267A 0 +OP4 E0267B 0 +OP4 E0267C 0 +OP4 E0267D 0 +OP4 E0267E 0 +OP4 E0267F 0 +OP4 E02680 0 +OP4 E02681 0 +OP4 E02682 0 +OP4 E02683 0 +OP4 E02684 0 +OP4 E02685 0 +OP4 E02686 0 +OP4 E02687 0 +OP4 E02688 0 +OP4 E02689 0 +OP4 E0268A 0 +OP4 E0268B 0 +OP4 E0268C 0 +OP4 E0268D 0 +OP4 E0268E 0 +OP4 E0268F 0 +OP4 E02690 0 +OP4 E02691 0 +OP4 E02692 0 +OP4 E02693 0 +OP4 E02694 0 +OP4 E02695 0 +OP4 E02696 0 +OP4 E02697 0 +OP4 E02698 0 +OP4 E02699 0 +OP4 E0269A 0 +OP4 E0269B 0 +OP4 E0269C 0 +OP4 E0269D 0 +OP4 E0269E 0 +OP4 E0269F 0 +OP4 E026A0 0 +OP4 E026A1 0 +OP4 E026A2 0 +OP4 E026A3 0 +OP4 E026A4 0 +OP4 E026A5 0 +OP4 E026A6 0 +OP4 E026A7 0 +OP4 E026A8 0 +OP4 E026A9 0 +OP4 E026AA 0 +OP4 E026AB 0 +OP4 E026AC 0 +OP4 E026AD 0 +OP4 E026AE 0 +OP4 E026AF 0 +OP4 E026B0 0 +OP4 E026B1 0 +OP4 E026B2 0 +OP4 E026B3 0 +OP4 E026B4 0 +OP4 E026B5 0 +OP4 E026B6 0 +OP4 E026B7 0 +OP4 E026B8 0 +OP4 E026B9 0 +OP4 E026BA 0 +OP4 E026BB 0 +OP4 E026BC 0 +OP4 E026BD 0 +OP4 E026BE 0 +OP4 E026BF 0 +OP4 E026C0 0 +OP4 E026C1 0 +OP4 E026C2 0 +OP4 E026C3 0 +OP4 E026C4 0 +OP4 E026C5 0 +OP4 E026C6 0 +OP4 E026C7 0 +OP4 E026C8 0 +OP4 E026C9 0 +OP4 E026CA 0 +OP4 E026CB 0 +OP4 E026CC 0 +OP4 E026CD 0 +OP4 E026CE 0 +OP4 E026CF 0 +OP4 E026D0 0 +OP4 E026D1 0 +OP4 E026D2 0 +OP4 E026D3 0 +OP4 E026D4 0 +OP4 E026D5 0 +OP4 E026D6 0 +OP4 E026D7 0 +OP4 E026D8 0 +OP4 E026D9 0 +OP4 E026DA 0 +OP4 E026DB 0 +OP4 E026DC 0 +OP4 E026DD 0 +OP4 E026DE 0 +OP4 E026DF 0 +OP4 E026E0 0 +OP4 E026E1 0 +OP4 E026E2 0 +OP4 E026E3 0 +OP4 E026E4 0 +OP4 E026E5 0 +OP4 E026E6 0 +OP4 E026E7 0 +OP4 E026E8 0 +OP4 E026E9 0 +OP4 E026EA 0 +OP4 E026EB 0 +OP4 E026EC 0 +OP4 E026ED 0 +OP4 E026EE 0 +OP4 E026EF 0 +OP4 E026F0 0 +OP4 E026F1 0 +OP4 E026F2 0 +OP4 E026F3 0 +OP4 E026F4 0 +OP4 E026F5 0 +OP4 E026F6 0 +OP4 E026F7 0 +OP4 E026F8 0 +OP4 E026F9 0 +OP4 E026FA 0 +OP4 E026FB 0 +OP4 E026FC 0 +OP4 E026FD 0 +OP4 E026FE 0 +OP4 E026FF 0 +OP4 E02700 0 +OP4 E02701 0 +OP4 E02702 0 +OP4 E02703 0 +OP4 E02704 0 +OP4 E02705 0 +OP4 E02706 0 +OP4 E02707 0 +OP4 E02708 0 +OP4 E02709 0 +OP4 E0270A 0 +OP4 E0270B 0 +OP4 E0270C 0 +OP4 E0270D 0 +OP4 E0270E 0 +OP4 E0270F 0 +OP4 E02710 0 +OP4 E02711 0 +OP4 E02712 0 +OP4 E02713 0 +OP4 E02714 0 +OP4 E02715 0 +OP4 E02716 0 +OP4 E02717 0 +OP4 E02718 0 +OP4 E02719 0 +OP4 E0271A 0 +OP4 E0271B 0 +OP4 E0271C 0 +OP4 E0271D 0 +OP4 E0271E 0 +OP4 E0271F 0 +OP4 E02720 0 +OP4 E02721 0 +OP4 E02722 0 +OP4 E02723 0 +OP4 E02724 0 +OP4 E02725 0 +OP4 E02726 0 +OP4 E02727 0 +OP4 E02728 0 +OP4 E02729 0 +OP4 E0272A 0 +OP4 E0272B 0 +OP4 E0272C 0 +OP4 E0272D 0 +OP4 E0272E 0 +OP4 E0272F 0 +OP4 E02730 0 +OP4 E02731 0 +OP4 E02732 0 +OP4 E02733 0 +OP4 E02734 0 +OP4 E02735 0 +OP4 E02736 0 +OP4 E02737 0 +OP4 E02738 0 +OP4 E02739 0 +OP4 E0273A 0 +OP4 E0273B 0 +OP4 E0273C 0 +OP4 E0273D 0 +OP4 E0273E 0 +OP4 E0273F 0 +OP4 E02740 0 +OP4 E02741 0 +OP4 E02742 0 +OP4 E02743 0 +OP4 E02744 0 +OP4 E02745 0 +OP4 E02746 0 +OP4 E02747 0 +OP4 E02748 0 +OP4 E02749 0 +OP4 E0274A 0 +OP4 E0274B 0 +OP4 E0274C 0 +OP4 E0274D 0 +OP4 E0274E 0 +OP4 E0274F 0 +OP4 E02750 0 +OP4 E02751 0 +OP4 E02752 0 +OP4 E02753 0 +OP4 E02754 0 +OP4 E02755 0 +OP4 E02756 0 +OP4 E02757 0 +OP4 E02758 0 +OP4 E02759 0 +OP4 E0275A 0 +OP4 E0275B 0 +OP4 E0275C 0 +OP4 E0275D 0 +OP4 E0275E 0 +OP4 E0275F 0 +OP4 E02760 0 +OP4 E02761 0 +OP4 E02762 0 +OP4 E02763 0 +OP4 E02764 0 +OP4 E02765 0 +OP4 E02766 0 +OP4 E02767 0 +OP4 E02768 0 +OP4 E02769 0 +OP4 E0276A 0 +OP4 E0276B 0 +OP4 E0276C 0 +OP4 E0276D 0 +OP4 E0276E 0 +OP4 E0276F 0 +OP4 E02770 0 +OP4 E02771 0 +OP4 E02772 0 +OP4 E02773 0 +OP4 E02774 0 +OP4 E02775 0 +OP4 E02776 0 +OP4 E02777 0 +OP4 E02778 0 +OP4 E02779 0 +OP4 E0277A 0 +OP4 E0277B 0 +OP4 E0277C 0 +OP4 E0277D 0 +OP4 E0277E 0 +OP4 E0277F 0 +OP4 E02780 0 +OP4 E02781 0 +OP4 E02782 0 +OP4 E02783 0 +OP4 E02784 0 +OP4 E02785 0 +OP4 E02786 0 +OP4 E02787 0 +OP4 E02788 0 +OP4 E02789 0 +OP4 E0278A 0 +OP4 E0278B 0 +OP4 E0278C 0 +OP4 E0278D 0 +OP4 E0278E 0 +OP4 E0278F 0 +OP4 E02790 0 +OP4 E02791 0 +OP4 E02792 0 +OP4 E02793 0 +OP4 E02794 0 +OP4 E02795 0 +OP4 E02796 0 +OP4 E02797 0 +OP4 E02798 0 +OP4 E02799 0 +OP4 E0279A 0 +OP4 E0279B 0 +OP4 E0279C 0 +OP4 E0279D 0 +OP4 E0279E 0 +OP4 E0279F 0 +OP4 E027A0 0 +OP4 E027A1 0 +OP4 E027A2 0 +OP4 E027A3 0 +OP4 E027A4 0 +OP4 E027A5 0 +OP4 E027A6 0 +OP4 E027A7 0 +OP4 E027A8 0 +OP4 E027A9 0 +OP4 E027AA 0 +OP4 E027AB 0 +OP4 E027AC 0 +OP4 E027AD 0 +OP4 E027AE 0 +OP4 E027AF 0 +OP4 E027B0 0 +OP4 E027B1 0 +OP4 E027B2 0 +OP4 E027B3 0 +OP4 E027B4 0 +OP4 E027B5 0 +OP4 E027B6 0 +OP4 E027B7 0 +OP4 E027B8 0 +OP4 E027B9 0 +OP4 E027BA 0 +OP4 E027BB 0 +OP4 E027BC 0 +OP4 E027BD 0 +OP4 E027BE 0 +OP4 E027BF 0 +OP4 E027C0 0 +OP4 E027C1 0 +OP4 E027C2 0 +OP4 E027C3 0 +OP4 E027C4 0 +OP4 E027C5 0 +OP4 E027C6 0 +OP4 E027C7 0 +OP4 E027C8 0 +OP4 E027C9 0 +OP4 E027CA 0 +OP4 E027CB 0 +OP4 E027CC 0 +OP4 E027CD 0 +OP4 E027CE 0 +OP4 E027CF 0 +OP4 E027D0 0 +OP4 E027D1 0 +OP4 E027D2 0 +OP4 E027D3 0 +OP4 E027D4 0 +OP4 E027D5 0 +OP4 E027D6 0 +OP4 E027D7 0 +OP4 E027D8 0 +OP4 E027D9 0 +OP4 E027DA 0 +OP4 E027DB 0 +OP4 E027DC 0 +OP4 E027DD 0 +OP4 E027DE 0 +OP4 E027DF 0 +OP4 E027E0 0 +OP4 E027E1 0 +OP4 E027E2 0 +OP4 E027E3 0 +OP4 E027E4 0 +OP4 E027E5 0 +OP4 E027E6 0 +OP4 E027E7 0 +OP4 E027E8 0 +OP4 E027E9 0 +OP4 E027EA 0 +OP4 E027EB 0 +OP4 E027EC 0 +OP4 E027ED 0 +OP4 E027EE 0 +OP4 E027EF 0 +OP4 E027F0 0 +OP4 E027F1 0 +OP4 E027F2 0 +OP4 E027F3 0 +OP4 E027F4 0 +OP4 E027F5 0 +OP4 E027F6 0 +OP4 E027F7 0 +OP4 E027F8 0 +OP4 E027F9 0 +OP4 E027FA 0 +OP4 E027FB 0 +OP4 E027FC 0 +OP4 E027FD 0 +OP4 E027FE 0 +OP4 E027FF 0 +OP4 E02800 0 +OP4 E02801 0 +OP4 E02802 0 +OP4 E02803 0 +OP4 E02804 0 +OP4 E02805 0 +OP4 E02806 0 +OP4 E02807 0 +OP4 E02808 0 +OP4 E02809 0 +OP4 E0280A 0 +OP4 E0280B 0 +OP4 E0280C 0 +OP4 E0280D 0 +OP4 E0280E 0 +OP4 E0280F 0 +OP4 E02810 0 +OP4 E02811 0 +OP4 E02812 0 +OP4 E02813 0 +OP4 E02814 0 +OP4 E02815 0 +OP4 E02816 0 +OP4 E02817 0 +OP4 E02818 0 +OP4 E02819 0 +OP4 E0281A 0 +OP4 E0281B 0 +OP4 E0281C 0 +OP4 E0281D 0 +OP4 E0281E 0 +OP4 E0281F 0 +OP4 E02820 0 +OP4 E02821 0 +OP4 E02822 0 +OP4 E02823 0 +OP4 E02824 0 +OP4 E02825 0 +OP4 E02826 0 +OP4 E02827 0 +OP4 E02828 0 +OP4 E02829 0 +OP4 E0282A 0 +OP4 E0282B 0 +OP4 E0282C 0 +OP4 E0282D 0 +OP4 E0282E 0 +OP4 E0282F 0 +OP4 E02830 0 +OP4 E02831 0 +OP4 E02832 0 +OP4 E02833 0 +OP4 E02834 0 +OP4 E02835 0 +OP4 E02836 0 +OP4 E02837 0 +OP4 E02838 0 +OP4 E02839 0 +OP4 E0283A 0 +OP4 E0283B 0 +OP4 E0283C 0 +OP4 E0283D 0 +OP4 E0283E 0 +OP4 E0283F 0 +OP4 E02840 0 +OP4 E02841 0 +OP4 E02842 0 +OP4 E02843 0 +OP4 E02844 0 +OP4 E02845 0 +OP4 E02846 0 +OP4 E02847 0 +OP4 E02848 0 +OP4 E02849 0 +OP4 E0284A 0 +OP4 E0284B 0 +OP4 E0284C 0 +OP4 E0284D 0 +OP4 E0284E 0 +OP4 E0284F 0 +OP4 E02850 0 +OP4 E02851 0 +OP4 E02852 0 +OP4 E02853 0 +OP4 E02854 0 +OP4 E02855 0 +OP4 E02856 0 +OP4 E02857 0 +OP4 E02858 0 +OP4 E02859 0 +OP4 E0285A 0 +OP4 E0285B 0 +OP4 E0285C 0 +OP4 E0285D 0 +OP4 E0285E 0 +OP4 E0285F 0 +OP4 E02860 0 +OP4 E02861 0 +OP4 E02862 0 +OP4 E02863 0 +OP4 E02864 0 +OP4 E02865 0 +OP4 E02866 0 +OP4 E02867 0 +OP4 E02868 0 +OP4 E02869 0 +OP4 E0286A 0 +OP4 E0286B 0 +OP4 E0286C 0 +OP4 E0286D 0 +OP4 E0286E 0 +OP4 E0286F 0 +OP4 E02870 0 +OP4 E02871 0 +OP4 E02872 0 +OP4 E02873 0 +OP4 E02874 0 +OP4 E02875 0 +OP4 E02876 0 +OP4 E02877 0 +OP4 E02878 0 +OP4 E02879 0 +OP4 E0287A 0 +OP4 E0287B 0 +OP4 E0287C 0 +OP4 E0287D 0 +OP4 E0287E 0 +OP4 E0287F 0 +OP4 E02880 0 +OP4 E02881 0 +OP4 E02882 0 +OP4 E02883 0 +OP4 E02884 0 +OP4 E02885 0 +OP4 E02886 0 +OP4 E02887 0 +OP4 E02888 0 +OP4 E02889 0 +OP4 E0288A 0 +OP4 E0288B 0 +OP4 E0288C 0 +OP4 E0288D 0 +OP4 E0288E 0 +OP4 E0288F 0 +OP4 E02890 0 +OP4 E02891 0 +OP4 E02892 0 +OP4 E02893 0 +OP4 E02894 0 +OP4 E02895 0 +OP4 E02896 0 +OP4 E02897 0 +OP4 E02898 0 +OP4 E02899 0 +OP4 E0289A 0 +OP4 E0289B 0 +OP4 E0289C 0 +OP4 E0289D 0 +OP4 E0289E 0 +OP4 E0289F 0 +OP4 E028A0 0 +OP4 E028A1 0 +OP4 E028A2 0 +OP4 E028A3 0 +OP4 E028A4 0 +OP4 E028A5 0 +OP4 E028A6 0 +OP4 E028A7 0 +OP4 E028A8 0 +OP4 E028A9 0 +OP4 E028AA 0 +OP4 E028AB 0 +OP4 E028AC 0 +OP4 E028AD 0 +OP4 E028AE 0 +OP4 E028AF 0 +OP4 E028B0 0 +OP4 E028B1 0 +OP4 E028B2 0 +OP4 E028B3 0 +OP4 E028B4 0 +OP4 E028B5 0 +OP4 E028B6 0 +OP4 E028B7 0 +OP4 E028B8 0 +OP4 E028B9 0 +OP4 E028BA 0 +OP4 E028BB 0 +OP4 E028BC 0 +OP4 E028BD 0 +OP4 E028BE 0 +OP4 E028BF 0 +OP4 E028C0 0 +OP4 E028C1 0 +OP4 E028C2 0 +OP4 E028C3 0 +OP4 E028C4 0 +OP4 E028C5 0 +OP4 E028C6 0 +OP4 E028C7 0 +OP4 E028C8 0 +OP4 E028C9 0 +OP4 E028CA 0 +OP4 E028CB 0 +OP4 E028CC 0 +OP4 E028CD 0 +OP4 E028CE 0 +OP4 E028CF 0 +OP4 E028D0 0 +OP4 E028D1 0 +OP4 E028D2 0 +OP4 E028D3 0 +OP4 E028D4 0 +OP4 E028D5 0 +OP4 E028D6 0 +OP4 E028D7 0 +OP4 E028D8 0 +OP4 E028D9 0 +OP4 E028DA 0 +OP4 E028DB 0 +OP4 E028DC 0 +OP4 E028DD 0 +OP4 E028DE 0 +OP4 E028DF 0 +OP4 E028E0 0 +OP4 E028E1 0 +OP4 E028E2 0 +OP4 E028E3 0 +OP4 E028E4 0 +OP4 E028E5 0 +OP4 E028E6 0 +OP4 E028E7 0 +OP4 E028E8 0 +OP4 E028E9 0 +OP4 E028EA 0 +OP4 E028EB 0 +OP4 E028EC 0 +OP4 E028ED 0 +OP4 E028EE 0 +OP4 E028EF 0 +OP4 E028F0 0 +OP4 E028F1 0 +OP4 E028F2 0 +OP4 E028F3 0 +OP4 E028F4 0 +OP4 E028F5 0 +OP4 E028F6 0 +OP4 E028F7 0 +OP4 E028F8 0 +OP4 E028F9 0 +OP4 E028FA 0 +OP4 E028FB 0 +OP4 E028FC 0 +OP4 E028FD 0 +OP4 E028FE 0 +OP4 E028FF 0 +OP4 E02900 0 +OP4 E02901 0 +OP4 E02902 0 +OP4 E02903 0 +OP4 E02904 0 +OP4 E02905 0 +OP4 E02906 0 +OP4 E02907 0 +OP4 E02908 0 +OP4 E02909 0 +OP4 E0290A 0 +OP4 E0290B 0 +OP4 E0290C 0 +OP4 E0290D 0 +OP4 E0290E 0 +OP4 E0290F 0 +OP4 E02910 0 +OP4 E02911 0 +OP4 E02912 0 +OP4 E02913 0 +OP4 E02914 0 +OP4 E02915 0 +OP4 E02916 0 +OP4 E02917 0 +OP4 E02918 0 +OP4 E02919 0 +OP4 E0291A 0 +OP4 E0291B 0 +OP4 E0291C 0 +OP4 E0291D 0 +OP4 E0291E 0 +OP4 E0291F 0 +OP4 E02920 0 +OP4 E02921 0 +OP4 E02922 0 +OP4 E02923 0 +OP4 E02924 0 +OP4 E02925 0 +OP4 E02926 0 +OP4 E02927 0 +OP4 E02928 0 +OP4 E02929 0 +OP4 E0292A 0 +OP4 E0292B 0 +OP4 E0292C 0 +OP4 E0292D 0 +OP4 E0292E 0 +OP4 E0292F 0 +OP4 E02930 0 +OP4 E02931 0 +OP4 E02932 0 +OP4 E02933 0 +OP4 E02934 0 +OP4 E02935 0 +OP4 E02936 0 +OP4 E02937 0 +OP4 E02938 0 +OP4 E02939 0 +OP4 E0293A 0 +OP4 E0293B 0 +OP4 E0293C 0 +OP4 E0293D 0 +OP4 E0293E 0 +OP4 E0293F 0 +OP4 E02940 0 +OP4 E02941 0 +OP4 E02942 0 +OP4 E02943 0 +OP4 E02944 0 +OP4 E02945 0 +OP4 E02946 0 +OP4 E02947 0 +OP4 E02948 0 +OP4 E02949 0 +OP4 E0294A 0 +OP4 E0294B 0 +OP4 E0294C 0 +OP4 E0294D 0 +OP4 E0294E 0 +OP4 E0294F 0 +OP4 E02950 0 +OP4 E02951 0 +OP4 E02952 0 +OP4 E02953 0 +OP4 E02954 0 +OP4 E02955 0 +OP4 E02956 0 +OP4 E02957 0 +OP4 E02958 0 +OP4 E02959 0 +OP4 E0295A 0 +OP4 E0295B 0 +OP4 E0295C 0 +OP4 E0295D 0 +OP4 E0295E 0 +OP4 E0295F 0 +OP4 E02960 0 +OP4 E02961 0 +OP4 E02962 0 +OP4 E02963 0 +OP4 E02964 0 +OP4 E02965 0 +OP4 E02966 0 +OP4 E02967 0 +OP4 E02968 0 +OP4 E02969 0 +OP4 E0296A 0 +OP4 E0296B 0 +OP4 E0296C 0 +OP4 E0296D 0 +OP4 E0296E 0 +OP4 E0296F 0 +OP4 E02970 0 +OP4 E02971 0 +OP4 E02972 0 +OP4 E02973 0 +OP4 E02974 0 +OP4 E02975 0 +OP4 E02976 0 +OP4 E02977 0 +OP4 E02978 0 +OP4 E02979 0 +OP4 E0297A 0 +OP4 E0297B 0 +OP4 E0297C 0 +OP4 E0297D 0 +OP4 E0297E 0 +OP4 E0297F 0 +OP4 E02980 0 +OP4 E02981 0 +OP4 E02982 0 +OP4 E02983 0 +OP4 E02984 0 +OP4 E02985 0 +OP4 E02986 0 +OP4 E02987 0 +OP4 E02988 0 +OP4 E02989 0 +OP4 E0298A 0 +OP4 E0298B 0 +OP4 E0298C 0 +OP4 E0298D 0 +OP4 E0298E 0 +OP4 E0298F 0 +OP4 E02990 0 +OP4 E02991 0 +OP4 E02992 0 +OP4 E02993 0 +OP4 E02994 0 +OP4 E02995 0 +OP4 E02996 0 +OP4 E02997 0 +OP4 E02998 0 +OP4 E02999 0 +OP4 E0299A 0 +OP4 E0299B 0 +OP4 E0299C 0 +OP4 E0299D 0 +OP4 E0299E 0 +OP4 E0299F 0 +OP4 E029A0 0 +OP4 E029A1 0 +OP4 E029A2 0 +OP4 E029A3 0 +OP4 E029A4 0 +OP4 E029A5 0 +OP4 E029A6 0 +OP4 E029A7 0 +OP4 E029A8 0 +OP4 E029A9 0 +OP4 E029AA 0 +OP4 E029AB 0 +OP4 E029AC 0 +OP4 E029AD 0 +OP4 E029AE 0 +OP4 E029AF 0 +OP4 E029B0 0 +OP4 E029B1 0 +OP4 E029B2 0 +OP4 E029B3 0 +OP4 E029B4 0 +OP4 E029B5 0 +OP4 E029B6 0 +OP4 E029B7 0 +OP4 E029B8 0 +OP4 E029B9 0 +OP4 E029BA 0 +OP4 E029BB 0 +OP4 E029BC 0 +OP4 E029BD 0 +OP4 E029BE 0 +OP4 E029BF 0 +OP4 E029C0 0 +OP4 E029C1 0 +OP4 E029C2 0 +OP4 E029C3 0 +OP4 E029C4 0 +OP4 E029C5 0 +OP4 E029C6 0 +OP4 E029C7 0 +OP4 E029C8 0 +OP4 E029C9 0 +OP4 E029CA 0 +OP4 E029CB 0 +OP4 E029CC 0 +OP4 E029CD 0 +OP4 E029CE 0 +OP4 E029CF 0 +OP4 E029D0 0 +OP4 E029D1 0 +OP4 E029D2 0 +OP4 E029D3 0 +OP4 E029D4 0 +OP4 E029D5 0 +OP4 E029D6 0 +OP4 E029D7 0 +OP4 E029D8 0 +OP4 E029D9 0 +OP4 E029DA 0 +OP4 E029DB 0 +OP4 E029DC 0 +OP4 E029DD 0 +OP4 E029DE 0 +OP4 E029DF 0 +OP4 E029E0 0 +OP4 E029E1 0 +OP4 E029E2 0 +OP4 E029E3 0 +OP4 E029E4 0 +OP4 E029E5 0 +OP4 E029E6 0 +OP4 E029E7 0 +OP4 E029E8 0 +OP4 E029E9 0 +OP4 E029EA 0 +OP4 E029EB 0 +OP4 E029EC 0 +OP4 E029ED 0 +OP4 E029EE 0 +OP4 E029EF 0 +OP4 E029F0 0 +OP4 E029F1 0 +OP4 E029F2 0 +OP4 E029F3 0 +OP4 E029F4 0 +OP4 E029F5 0 +OP4 E029F6 0 +OP4 E029F7 0 +OP4 E029F8 0 +OP4 E029F9 0 +OP4 E029FA 0 +OP4 E029FB 0 +OP4 E029FC 0 +OP4 E029FD 0 +OP4 E029FE 0 +OP4 E029FF 0 +OP4 E02A00 0 +OP4 E02A01 0 +OP4 E02A02 0 +OP4 E02A03 0 +OP4 E02A04 0 +OP4 E02A05 0 +OP4 E02A06 0 +OP4 E02A07 0 +OP4 E02A08 0 +OP4 E02A09 0 +OP4 E02A0A 0 +OP4 E02A0B 0 +OP4 E02A0C 0 +OP4 E02A0D 0 +OP4 E02A0E 0 +OP4 E02A0F 0 +OP4 E02A10 0 +OP4 E02A11 0 +OP4 E02A12 0 +OP4 E02A13 0 +OP4 E02A14 0 +OP4 E02A15 0 +OP4 E02A16 0 +OP4 E02A17 0 +OP4 E02A18 0 +OP4 E02A19 0 +OP4 E02A1A 0 +OP4 E02A1B 0 +OP4 E02A1C 0 +OP4 E02A1D 0 +OP4 E02A1E 0 +OP4 E02A1F 0 +OP4 E02A20 0 +OP4 E02A21 0 +OP4 E02A22 0 +OP4 E02A23 0 +OP4 E02A24 0 +OP4 E02A25 0 +OP4 E02A26 0 +OP4 E02A27 0 +OP4 E02A28 0 +OP4 E02A29 0 +OP4 E02A2A 0 +OP4 E02A2B 0 +OP4 E02A2C 0 +OP4 E02A2D 0 +OP4 E02A2E 0 +OP4 E02A2F 0 +OP4 E02A30 0 +OP4 E02A31 0 +OP4 E02A32 0 +OP4 E02A33 0 +OP4 E02A34 0 +OP4 E02A35 0 +OP4 E02A36 0 +OP4 E02A37 0 +OP4 E02A38 0 +OP4 E02A39 0 +OP4 E02A3A 0 +OP4 E02A3B 0 +OP4 E02A3C 0 +OP4 E02A3D 0 +OP4 E02A3E 0 +OP4 E02A3F 0 +OP4 E02A40 0 +OP4 E02A41 0 +OP4 E02A42 0 +OP4 E02A43 0 +OP4 E02A44 0 +OP4 E02A45 0 +OP4 E02A46 0 +OP4 E02A47 0 +OP4 E02A48 0 +OP4 E02A49 0 +OP4 E02A4A 0 +OP4 E02A4B 0 +OP4 E02A4C 0 +OP4 E02A4D 0 +OP4 E02A4E 0 +OP4 E02A4F 0 +OP4 E02A50 0 +OP4 E02A51 0 +OP4 E02A52 0 +OP4 E02A53 0 +OP4 E02A54 0 +OP4 E02A55 0 +OP4 E02A56 0 +OP4 E02A57 0 +OP4 E02A58 0 +OP4 E02A59 0 +OP4 E02A5A 0 +OP4 E02A5B 0 +OP4 E02A5C 0 +OP4 E02A5D 0 +OP4 E02A5E 0 +OP4 E02A5F 0 +OP4 E02A60 0 +OP4 E02A61 0 +OP4 E02A62 0 +OP4 E02A63 0 +OP4 E02A64 0 +OP4 E02A65 0 +OP4 E02A66 0 +OP4 E02A67 0 +OP4 E02A68 0 +OP4 E02A69 0 +OP4 E02A6A 0 +OP4 E02A6B 0 +OP4 E02A6C 0 +OP4 E02A6D 0 +OP4 E02A6E 0 +OP4 E02A6F 0 +OP4 E02A70 0 +OP4 E02A71 0 +OP4 E02A72 0 +OP4 E02A73 0 +OP4 E02A74 0 +OP4 E02A75 0 +OP4 E02A76 0 +OP4 E02A77 0 +OP4 E02A78 0 +OP4 E02A79 0 +OP4 E02A7A 0 +OP4 E02A7B 0 +OP4 E02A7C 0 +OP4 E02A7D 0 +OP4 E02A7E 0 +OP4 E02A7F 0 +OP4 E02A80 0 +OP4 E02A81 0 +OP4 E02A82 0 +OP4 E02A83 0 +OP4 E02A84 0 +OP4 E02A85 0 +OP4 E02A86 0 +OP4 E02A87 0 +OP4 E02A88 0 +OP4 E02A89 0 +OP4 E02A8A 0 +OP4 E02A8B 0 +OP4 E02A8C 0 +OP4 E02A8D 0 +OP4 E02A8E 0 +OP4 E02A8F 0 +OP4 E02A90 0 +OP4 E02A91 0 +OP4 E02A92 0 +OP4 E02A93 0 +OP4 E02A94 0 +OP4 E02A95 0 +OP4 E02A96 0 +OP4 E02A97 0 +OP4 E02A98 0 +OP4 E02A99 0 +OP4 E02A9A 0 +OP4 E02A9B 0 +OP4 E02A9C 0 +OP4 E02A9D 0 +OP4 E02A9E 0 +OP4 E02A9F 0 +OP4 E02AA0 0 +OP4 E02AA1 0 +OP4 E02AA2 0 +OP4 E02AA3 0 +OP4 E02AA4 0 +OP4 E02AA5 0 +OP4 E02AA6 0 +OP4 E02AA7 0 +OP4 E02AA8 0 +OP4 E02AA9 0 +OP4 E02AAA 0 +OP4 E02AAB 0 +OP4 E02AAC 0 +OP4 E02AAD 0 +OP4 E02AAE 0 +OP4 E02AAF 0 +OP4 E02AB0 0 +OP4 E02AB1 0 +OP4 E02AB2 0 +OP4 E02AB3 0 +OP4 E02AB4 0 +OP4 E02AB5 0 +OP4 E02AB6 0 +OP4 E02AB7 0 +OP4 E02AB8 0 +OP4 E02AB9 0 +OP4 E02ABA 0 +OP4 E02ABB 0 +OP4 E02ABC 0 +OP4 E02ABD 0 +OP4 E02ABE 0 +OP4 E02ABF 0 +OP4 E02AC0 0 +OP4 E02AC1 0 +OP4 E02AC2 0 +OP4 E02AC3 0 +OP4 E02AC4 0 +OP4 E02AC5 0 +OP4 E02AC6 0 +OP4 E02AC7 0 +OP4 E02AC8 0 +OP4 E02AC9 0 +OP4 E02ACA 0 +OP4 E02ACB 0 +OP4 E02ACC 0 +OP4 E02ACD 0 +OP4 E02ACE 0 +OP4 E02ACF 0 +OP4 E02AD0 0 +OP4 E02AD1 0 +OP4 E02AD2 0 +OP4 E02AD3 0 +OP4 E02AD4 0 +OP4 E02AD5 0 +OP4 E02AD6 0 +OP4 E02AD7 0 +OP4 E02AD8 0 +OP4 E02AD9 0 +OP4 E02ADA 0 +OP4 E02ADB 0 +OP4 E02ADC 0 +OP4 E02ADD 0 +OP4 E02ADE 0 +OP4 E02ADF 0 +OP4 E02AE0 0 +OP4 E02AE1 0 +OP4 E02AE2 0 +OP4 E02AE3 0 +OP4 E02AE4 0 +OP4 E02AE5 0 +OP4 E02AE6 0 +OP4 E02AE7 0 +OP4 E02AE8 0 +OP4 E02AE9 0 +OP4 E02AEA 0 +OP4 E02AEB 0 +OP4 E02AEC 0 +OP4 E02AED 0 +OP4 E02AEE 0 +OP4 E02AEF 0 +OP4 E02AF0 0 +OP4 E02AF1 0 +OP4 E02AF2 0 +OP4 E02AF3 0 +OP4 E02AF4 0 +OP4 E02AF5 0 +OP4 E02AF6 0 +OP4 E02AF7 0 +OP4 E02AF8 0 +OP4 E02AF9 0 +OP4 E02AFA 0 +OP4 E02AFB 0 +OP4 E02AFC 0 +OP4 E02AFD 0 +OP4 E02AFE 0 +OP4 E02AFF 0 +OP4 E02B00 0 +OP4 E02B01 0 +OP4 E02B02 0 +OP4 E02B03 0 +OP4 E02B04 0 +OP4 E02B05 0 +OP4 E02B06 0 +OP4 E02B07 0 +OP4 E02B08 0 +OP4 E02B09 0 +OP4 E02B0A 0 +OP4 E02B0B 0 +OP4 E02B0C 0 +OP4 E02B0D 0 +OP4 E02B0E 0 +OP4 E02B0F 0 +OP4 E02B10 0 +OP4 E02B11 0 +OP4 E02B12 0 +OP4 E02B13 0 +OP4 E02B14 0 +OP4 E02B15 0 +OP4 E02B16 0 +OP4 E02B17 0 +OP4 E02B18 0 +OP4 E02B19 0 +OP4 E02B1A 0 +OP4 E02B1B 0 +OP4 E02B1C 0 +OP4 E02B1D 0 +OP4 E02B1E 0 +OP4 E02B1F 0 +OP4 E02B20 0 +OP4 E02B21 0 +OP4 E02B22 0 +OP4 E02B23 0 +OP4 E02B24 0 +OP4 E02B25 0 +OP4 E02B26 0 +OP4 E02B27 0 +OP4 E02B28 0 +OP4 E02B29 0 +OP4 E02B2A 0 +OP4 E02B2B 0 +OP4 E02B2C 0 +OP4 E02B2D 0 +OP4 E02B2E 0 +OP4 E02B2F 0 +OP4 E02B30 0 +OP4 E02B31 0 +OP4 E02B32 0 +OP4 E02B33 0 +OP4 E02B34 0 +OP4 E02B35 0 +OP4 E02B36 0 +OP4 E02B37 0 +OP4 E02B38 0 +OP4 E02B39 0 +OP4 E02B3A 0 +OP4 E02B3B 0 +OP4 E02B3C 0 +OP4 E02B3D 0 +OP4 E02B3E 0 +OP4 E02B3F 0 +OP4 E02B40 0 +OP4 E02B41 0 +OP4 E02B42 0 +OP4 E02B43 0 +OP4 E02B44 0 +OP4 E02B45 0 +OP4 E02B46 0 +OP4 E02B47 0 +OP4 E02B48 0 +OP4 E02B49 0 +OP4 E02B4A 0 +OP4 E02B4B 0 +OP4 E02B4C 0 +OP4 E02B4D 0 +OP4 E02B4E 0 +OP4 E02B4F 0 +OP4 E02B50 0 +OP4 E02B51 0 +OP4 E02B52 0 +OP4 E02B53 0 +OP4 E02B54 0 +OP4 E02B55 0 +OP4 E02B56 0 +OP4 E02B57 0 +OP4 E02B58 0 +OP4 E02B59 0 +OP4 E02B5A 0 +OP4 E02B5B 0 +OP4 E02B5C 0 +OP4 E02B5D 0 +OP4 E02B5E 0 +OP4 E02B5F 0 +OP4 E02B60 0 +OP4 E02B61 0 +OP4 E02B62 0 +OP4 E02B63 0 +OP4 E02B64 0 +OP4 E02B65 0 +OP4 E02B66 0 +OP4 E02B67 0 +OP4 E02B68 0 +OP4 E02B69 0 +OP4 E02B6A 0 +OP4 E02B6B 0 +OP4 E02B6C 0 +OP4 E02B6D 0 +OP4 E02B6E 0 +OP4 E02B6F 0 +OP4 E02B70 0 +OP4 E02B71 0 +OP4 E02B72 0 +OP4 E02B73 0 +OP4 E02B74 0 +OP4 E02B75 0 +OP4 E02B76 0 +OP4 E02B77 0 +OP4 E02B78 0 +OP4 E02B79 0 +OP4 E02B7A 0 +OP4 E02B7B 0 +OP4 E02B7C 0 +OP4 E02B7D 0 +OP4 E02B7E 0 +OP4 E02B7F 0 +OP4 E02B80 0 +OP4 E02B81 0 +OP4 E02B82 0 +OP4 E02B83 0 +OP4 E02B84 0 +OP4 E02B85 0 +OP4 E02B86 0 +OP4 E02B87 0 +OP4 E02B88 0 +OP4 E02B89 0 +OP4 E02B8A 0 +OP4 E02B8B 0 +OP4 E02B8C 0 +OP4 E02B8D 0 +OP4 E02B8E 0 +OP4 E02B8F 0 +OP4 E02B90 0 +OP4 E02B91 0 +OP4 E02B92 0 +OP4 E02B93 0 +OP4 E02B94 0 +OP4 E02B95 0 +OP4 E02B96 0 +OP4 E02B97 0 +OP4 E02B98 0 +OP4 E02B99 0 +OP4 E02B9A 0 +OP4 E02B9B 0 +OP4 E02B9C 0 +OP4 E02B9D 0 +OP4 E02B9E 0 +OP4 E02B9F 0 +OP4 E02BA0 0 +OP4 E02BA1 0 +OP4 E02BA2 0 +OP4 E02BA3 0 +OP4 E02BA4 0 +OP4 E02BA5 0 +OP4 E02BA6 0 +OP4 E02BA7 0 +OP4 E02BA8 0 +OP4 E02BA9 0 +OP4 E02BAA 0 +OP4 E02BAB 0 +OP4 E02BAC 0 +OP4 E02BAD 0 +OP4 E02BAE 0 +OP4 E02BAF 0 +OP4 E02BB0 0 +OP4 E02BB1 0 +OP4 E02BB2 0 +OP4 E02BB3 0 +OP4 E02BB4 0 +OP4 E02BB5 0 +OP4 E02BB6 0 +OP4 E02BB7 0 +OP4 E02BB8 0 +OP4 E02BB9 0 +OP4 E02BBA 0 +OP4 E02BBB 0 +OP4 E02BBC 0 +OP4 E02BBD 0 +OP4 E02BBE 0 +OP4 E02BBF 0 +OP4 E02BC0 0 +OP4 E02BC1 0 +OP4 E02BC2 0 +OP4 E02BC3 0 +OP4 E02BC4 0 +OP4 E02BC5 0 +OP4 E02BC6 0 +OP4 E02BC7 0 +OP4 E02BC8 0 +OP4 E02BC9 0 +OP4 E02BCA 0 +OP4 E02BCB 0 +OP4 E02BCC 0 +OP4 E02BCD 0 +OP4 E02BCE 0 +OP4 E02BCF 0 +OP4 E02BD0 0 +OP4 E02BD1 0 +OP4 E02BD2 0 +OP4 E02BD3 0 +OP4 E02BD4 0 +OP4 E02BD5 0 +OP4 E02BD6 0 +OP4 E02BD7 0 +OP4 E02BD8 0 +OP4 E02BD9 0 +OP4 E02BDA 0 +OP4 E02BDB 0 +OP4 E02BDC 0 +OP4 E02BDD 0 +OP4 E02BDE 0 +OP4 E02BDF 0 +OP4 E02BE0 0 +OP4 E02BE1 0 +OP4 E02BE2 0 +OP4 E02BE3 0 +OP4 E02BE4 0 +OP4 E02BE5 0 +OP4 E02BE6 0 +OP4 E02BE7 0 +OP4 E02BE8 0 +OP4 E02BE9 0 +OP4 E02BEA 0 +OP4 E02BEB 0 +OP4 E02BEC 0 +OP4 E02BED 0 +OP4 E02BEE 0 +OP4 E02BEF 0 +OP4 E02BF0 0 +OP4 E02BF1 0 +OP4 E02BF2 0 +OP4 E02BF3 0 +OP4 E02BF4 0 +OP4 E02BF5 0 +OP4 E02BF6 0 +OP4 E02BF7 0 +OP4 E02BF8 0 +OP4 E02BF9 0 +OP4 E02BFA 0 +OP4 E02BFB 0 +OP4 E02BFC 0 +OP4 E02BFD 0 +OP4 E02BFE 0 +OP4 E02BFF 0 +OP4 E02C00 0 +OP4 E02C01 0 +OP4 E02C02 0 +OP4 E02C03 0 +OP4 E02C04 0 +OP4 E02C05 0 +OP4 E02C06 0 +OP4 E02C07 0 +OP4 E02C08 0 +OP4 E02C09 0 +OP4 E02C0A 0 +OP4 E02C0B 0 +OP4 E02C0C 0 +OP4 E02C0D 0 +OP4 E02C0E 0 +OP4 E02C0F 0 +OP4 E02C10 0 +OP4 E02C11 0 +OP4 E02C12 0 +OP4 E02C13 0 +OP4 E02C14 0 +OP4 E02C15 0 +OP4 E02C16 0 +OP4 E02C17 0 +OP4 E02C18 0 +OP4 E02C19 0 +OP4 E02C1A 0 +OP4 E02C1B 0 +OP4 E02C1C 0 +OP4 E02C1D 0 +OP4 E02C1E 0 +OP4 E02C1F 0 +OP4 E02C20 0 +OP4 E02C21 0 +OP4 E02C22 0 +OP4 E02C23 0 +OP4 E02C24 0 +OP4 E02C25 0 +OP4 E02C26 0 +OP4 E02C27 0 +OP4 E02C28 0 +OP4 E02C29 0 +OP4 E02C2A 0 +OP4 E02C2B 0 +OP4 E02C2C 0 +OP4 E02C2D 0 +OP4 E02C2E 0 +OP4 E02C2F 0 +OP4 E02C30 0 +OP4 E02C31 0 +OP4 E02C32 0 +OP4 E02C33 0 +OP4 E02C34 0 +OP4 E02C35 0 +OP4 E02C36 0 +OP4 E02C37 0 +OP4 E02C38 0 +OP4 E02C39 0 +OP4 E02C3A 0 +OP4 E02C3B 0 +OP4 E02C3C 0 +OP4 E02C3D 0 +OP4 E02C3E 0 +OP4 E02C3F 0 +OP4 E02C40 0 +OP4 E02C41 0 +OP4 E02C42 0 +OP4 E02C43 0 +OP4 E02C44 0 +OP4 E02C45 0 +OP4 E02C46 0 +OP4 E02C47 0 +OP4 E02C48 0 +OP4 E02C49 0 +OP4 E02C4A 0 +OP4 E02C4B 0 +OP4 E02C4C 0 +OP4 E02C4D 0 +OP4 E02C4E 0 +OP4 E02C4F 0 +OP4 E02C50 0 +OP4 E02C51 0 +OP4 E02C52 0 +OP4 E02C53 0 +OP4 E02C54 0 +OP4 E02C55 0 +OP4 E02C56 0 +OP4 E02C57 0 +OP4 E02C58 0 +OP4 E02C59 0 +OP4 E02C5A 0 +OP4 E02C5B 0 +OP4 E02C5C 0 +OP4 E02C5D 0 +OP4 E02C5E 0 +OP4 E02C5F 0 +OP4 E02C60 0 +OP4 E02C61 0 +OP4 E02C62 0 +OP4 E02C63 0 +OP4 E02C64 0 +OP4 E02C65 0 +OP4 E02C66 0 +OP4 E02C67 0 +OP4 E02C68 0 +OP4 E02C69 0 +OP4 E02C6A 0 +OP4 E02C6B 0 +OP4 E02C6C 0 +OP4 E02C6D 0 +OP4 E02C6E 0 +OP4 E02C6F 0 +OP4 E02C70 0 +OP4 E02C71 0 +OP4 E02C72 0 +OP4 E02C73 0 +OP4 E02C74 0 +OP4 E02C75 0 +OP4 E02C76 0 +OP4 E02C77 0 +OP4 E02C78 0 +OP4 E02C79 0 +OP4 E02C7A 0 +OP4 E02C7B 0 +OP4 E02C7C 0 +OP4 E02C7D 0 +OP4 E02C7E 0 +OP4 E02C7F 0 +OP4 E02C80 0 +OP4 E02C81 0 +OP4 E02C82 0 +OP4 E02C83 0 +OP4 E02C84 0 +OP4 E02C85 0 +OP4 E02C86 0 +OP4 E02C87 0 +OP4 E02C88 0 +OP4 E02C89 0 +OP4 E02C8A 0 +OP4 E02C8B 0 +OP4 E02C8C 0 +OP4 E02C8D 0 +OP4 E02C8E 0 +OP4 E02C8F 0 +OP4 E02C90 0 +OP4 E02C91 0 +OP4 E02C92 0 +OP4 E02C93 0 +OP4 E02C94 0 +OP4 E02C95 0 +OP4 E02C96 0 +OP4 E02C97 0 +OP4 E02C98 0 +OP4 E02C99 0 +OP4 E02C9A 0 +OP4 E02C9B 0 +OP4 E02C9C 0 +OP4 E02C9D 0 +OP4 E02C9E 0 +OP4 E02C9F 0 +OP4 E02CA0 0 +OP4 E02CA1 0 +OP4 E02CA2 0 +OP4 E02CA3 0 +OP4 E02CA4 0 +OP4 E02CA5 0 +OP4 E02CA6 0 +OP4 E02CA7 0 +OP4 E02CA8 0 +OP4 E02CA9 0 +OP4 E02CAA 0 +OP4 E02CAB 0 +OP4 E02CAC 0 +OP4 E02CAD 0 +OP4 E02CAE 0 +OP4 E02CAF 0 +OP4 E02CB0 0 +OP4 E02CB1 0 +OP4 E02CB2 0 +OP4 E02CB3 0 +OP4 E02CB4 0 +OP4 E02CB5 0 +OP4 E02CB6 0 +OP4 E02CB7 0 +OP4 E02CB8 0 +OP4 E02CB9 0 +OP4 E02CBA 0 +OP4 E02CBB 0 +OP4 E02CBC 0 +OP4 E02CBD 0 +OP4 E02CBE 0 +OP4 E02CBF 0 +OP4 E02CC0 0 +OP4 E02CC1 0 +OP4 E02CC2 0 +OP4 E02CC3 0 +OP4 E02CC4 0 +OP4 E02CC5 0 +OP4 E02CC6 0 +OP4 E02CC7 0 +OP4 E02CC8 0 +OP4 E02CC9 0 +OP4 E02CCA 0 +OP4 E02CCB 0 +OP4 E02CCC 0 +OP4 E02CCD 0 +OP4 E02CCE 0 +OP4 E02CCF 0 +OP4 E02CD0 0 +OP4 E02CD1 0 +OP4 E02CD2 0 +OP4 E02CD3 0 +OP4 E02CD4 0 +OP4 E02CD5 0 +OP4 E02CD6 0 +OP4 E02CD7 0 +OP4 E02CD8 0 +OP4 E02CD9 0 +OP4 E02CDA 0 +OP4 E02CDB 0 +OP4 E02CDC 0 +OP4 E02CDD 0 +OP4 E02CDE 0 +OP4 E02CDF 0 +OP4 E02CE0 0 +OP4 E02CE1 0 +OP4 E02CE2 0 +OP4 E02CE3 0 +OP4 E02CE4 0 +OP4 E02CE5 0 +OP4 E02CE6 0 +OP4 E02CE7 0 +OP4 E02CE8 0 +OP4 E02CE9 0 +OP4 E02CEA 0 +OP4 E02CEB 0 +OP4 E02CEC 0 +OP4 E02CED 0 +OP4 E02CEE 0 +OP4 E02CEF 0 +OP4 E02CF0 0 +OP4 E02CF1 0 +OP4 E02CF2 0 +OP4 E02CF3 0 +OP4 E02CF4 0 +OP4 E02CF5 0 +OP4 E02CF6 0 +OP4 E02CF7 0 +OP4 E02CF8 0 +OP4 E02CF9 0 +OP4 E02CFA 0 +OP4 E02CFB 0 +OP4 E02CFC 0 +OP4 E02CFD 0 +OP4 E02CFE 0 +OP4 E02CFF 0 +OP4 E02D00 0 +OP4 E02D01 0 +OP4 E02D02 0 +OP4 E02D03 0 +OP4 E02D04 0 +OP4 E02D05 0 +OP4 E02D06 0 +OP4 E02D07 0 +OP4 E02D08 0 +OP4 E02D09 0 +OP4 E02D0A 0 +OP4 E02D0B 0 +OP4 E02D0C 0 +OP4 E02D0D 0 +OP4 E02D0E 0 +OP4 E02D0F 0 +OP4 E02D10 0 +OP4 E02D11 0 +OP4 E02D12 0 +OP4 E02D13 0 +OP4 E02D14 0 +OP4 E02D15 0 +OP4 E02D16 0 +OP4 E02D17 0 +OP4 E02D18 0 +OP4 E02D19 0 +OP4 E02D1A 0 +OP4 E02D1B 0 +OP4 E02D1C 0 +OP4 E02D1D 0 +OP4 E02D1E 0 +OP4 E02D1F 0 +OP4 E02D20 0 +OP4 E02D21 0 +OP4 E02D22 0 +OP4 E02D23 0 +OP4 E02D24 0 +OP4 E02D25 0 +OP4 E02D26 0 +OP4 E02D27 0 +OP4 E02D28 0 +OP4 E02D29 0 +OP4 E02D2A 0 +OP4 E02D2B 0 +OP4 E02D2C 0 +OP4 E02D2D 0 +OP4 E02D2E 0 +OP4 E02D2F 0 +OP4 E02D30 0 +OP4 E02D31 0 +OP4 E02D32 0 +OP4 E02D33 0 +OP4 E02D34 0 +OP4 E02D35 0 +OP4 E02D36 0 +OP4 E02D37 0 +OP4 E02D38 0 +OP4 E02D39 0 +OP4 E02D3A 0 +OP4 E02D3B 0 +OP4 E02D3C 0 +OP4 E02D3D 0 +OP4 E02D3E 0 +OP4 E02D3F 0 +OP4 E02D40 0 +OP4 E02D41 0 +OP4 E02D42 0 +OP4 E02D43 0 +OP4 E02D44 0 +OP4 E02D45 0 +OP4 E02D46 0 +OP4 E02D47 0 +OP4 E02D48 0 +OP4 E02D49 0 +OP4 E02D4A 0 +OP4 E02D4B 0 +OP4 E02D4C 0 +OP4 E02D4D 0 +OP4 E02D4E 0 +OP4 E02D4F 0 +OP4 E02D50 0 +OP4 E02D51 0 +OP4 E02D52 0 +OP4 E02D53 0 +OP4 E02D54 0 +OP4 E02D55 0 +OP4 E02D56 0 +OP4 E02D57 0 +OP4 E02D58 0 +OP4 E02D59 0 +OP4 E02D5A 0 +OP4 E02D5B 0 +OP4 E02D5C 0 +OP4 E02D5D 0 +OP4 E02D5E 0 +OP4 E02D5F 0 +OP4 E02D60 0 +OP4 E02D61 0 +OP4 E02D62 0 +OP4 E02D63 0 +OP4 E02D64 0 +OP4 E02D65 0 +OP4 E02D66 0 +OP4 E02D67 0 +OP4 E02D68 0 +OP4 E02D69 0 +OP4 E02D6A 0 +OP4 E02D6B 0 +OP4 E02D6C 0 +OP4 E02D6D 0 +OP4 E02D6E 0 +OP4 E02D6F 0 +OP4 E02D70 0 +OP4 E02D71 0 +OP4 E02D72 0 +OP4 E02D73 0 +OP4 E02D74 0 +OP4 E02D75 0 +OP4 E02D76 0 +OP4 E02D77 0 +OP4 E02D78 0 +OP4 E02D79 0 +OP4 E02D7A 0 +OP4 E02D7B 0 +OP4 E02D7C 0 +OP4 E02D7D 0 +OP4 E02D7E 0 +OP4 E02D7F 0 +OP4 E02D80 0 +OP4 E02D81 0 +OP4 E02D82 0 +OP4 E02D83 0 +OP4 E02D84 0 +OP4 E02D85 0 +OP4 E02D86 0 +OP4 E02D87 0 +OP4 E02D88 0 +OP4 E02D89 0 +OP4 E02D8A 0 +OP4 E02D8B 0 +OP4 E02D8C 0 +OP4 E02D8D 0 +OP4 E02D8E 0 +OP4 E02D8F 0 +OP4 E02D90 0 +OP4 E02D91 0 +OP4 E02D92 0 +OP4 E02D93 0 +OP4 E02D94 0 +OP4 E02D95 0 +OP4 E02D96 0 +OP4 E02D97 0 +OP4 E02D98 0 +OP4 E02D99 0 +OP4 E02D9A 0 +OP4 E02D9B 0 +OP4 E02D9C 0 +OP4 E02D9D 0 +OP4 E02D9E 0 +OP4 E02D9F 0 +OP4 E02DA0 0 +OP4 E02DA1 0 +OP4 E02DA2 0 +OP4 E02DA3 0 +OP4 E02DA4 0 +OP4 E02DA5 0 +OP4 E02DA6 0 +OP4 E02DA7 0 +OP4 E02DA8 0 +OP4 E02DA9 0 +OP4 E02DAA 0 +OP4 E02DAB 0 +OP4 E02DAC 0 +OP4 E02DAD 0 +OP4 E02DAE 0 +OP4 E02DAF 0 +OP4 E02DB0 0 +OP4 E02DB1 0 +OP4 E02DB2 0 +OP4 E02DB3 0 +OP4 E02DB4 0 +OP4 E02DB5 0 +OP4 E02DB6 0 +OP4 E02DB7 0 +OP4 E02DB8 0 +OP4 E02DB9 0 +OP4 E02DBA 0 +OP4 E02DBB 0 +OP4 E02DBC 0 +OP4 E02DBD 0 +OP4 E02DBE 0 +OP4 E02DBF 0 +OP4 E02DC0 0 +OP4 E02DC1 0 +OP4 E02DC2 0 +OP4 E02DC3 0 +OP4 E02DC4 0 +OP4 E02DC5 0 +OP4 E02DC6 0 +OP4 E02DC7 0 +OP4 E02DC8 0 +OP4 E02DC9 0 +OP4 E02DCA 0 +OP4 E02DCB 0 +OP4 E02DCC 0 +OP4 E02DCD 0 +OP4 E02DCE 0 +OP4 E02DCF 0 +OP4 E02DD0 0 +OP4 E02DD1 0 +OP4 E02DD2 0 +OP4 E02DD3 0 +OP4 E02DD4 0 +OP4 E02DD5 0 +OP4 E02DD6 0 +OP4 E02DD7 0 +OP4 E02DD8 0 +OP4 E02DD9 0 +OP4 E02DDA 0 +OP4 E02DDB 0 +OP4 E02DDC 0 +OP4 E02DDD 0 +OP4 E02DDE 0 +OP4 E02DDF 0 +OP4 E02DE0 0 +OP4 E02DE1 0 +OP4 E02DE2 0 +OP4 E02DE3 0 +OP4 E02DE4 0 +OP4 E02DE5 0 +OP4 E02DE6 0 +OP4 E02DE7 0 +OP4 E02DE8 0 +OP4 E02DE9 0 +OP4 E02DEA 0 +OP4 E02DEB 0 +OP4 E02DEC 0 +OP4 E02DED 0 +OP4 E02DEE 0 +OP4 E02DEF 0 +OP4 E02DF0 0 +OP4 E02DF1 0 +OP4 E02DF2 0 +OP4 E02DF3 0 +OP4 E02DF4 0 +OP4 E02DF5 0 +OP4 E02DF6 0 +OP4 E02DF7 0 +OP4 E02DF8 0 +OP4 E02DF9 0 +OP4 E02DFA 0 +OP4 E02DFB 0 +OP4 E02DFC 0 +OP4 E02DFD 0 +OP4 E02DFE 0 +OP4 E02DFF 0 +OP4 E02E00 0 +OP4 E02E01 0 +OP4 E02E02 0 +OP4 E02E03 0 +OP4 E02E04 0 +OP4 E02E05 0 +OP4 E02E06 0 +OP4 E02E07 0 +OP4 E02E08 0 +OP4 E02E09 0 +OP4 E02E0A 0 +OP4 E02E0B 0 +OP4 E02E0C 0 +OP4 E02E0D 0 +OP4 E02E0E 0 +OP4 E02E0F 0 +OP4 E02E10 0 +OP4 E02E11 0 +OP4 E02E12 0 +OP4 E02E13 0 +OP4 E02E14 0 +OP4 E02E15 0 +OP4 E02E16 0 +OP4 E02E17 0 +OP4 E02E18 0 +OP4 E02E19 0 +OP4 E02E1A 0 +OP4 E02E1B 0 +OP4 E02E1C 0 +OP4 E02E1D 0 +OP4 E02E1E 0 +OP4 E02E1F 0 +OP4 E02E20 0 +OP4 E02E21 0 +OP4 E02E22 0 +OP4 E02E23 0 +OP4 E02E24 0 +OP4 E02E25 0 +OP4 E02E26 0 +OP4 E02E27 0 +OP4 E02E28 0 +OP4 E02E29 0 +OP4 E02E2A 0 +OP4 E02E2B 0 +OP4 E02E2C 0 +OP4 E02E2D 0 +OP4 E02E2E 0 +OP4 E02E2F 0 +OP4 E02E30 0 +OP4 E02E31 0 +OP4 E02E32 0 +OP4 E02E33 0 +OP4 E02E34 0 +OP4 E02E35 0 +OP4 E02E36 0 +OP4 E02E37 0 +OP4 E02E38 0 +OP4 E02E39 0 +OP4 E02E3A 0 +OP4 E02E3B 0 +OP4 E02E3C 0 +OP4 E02E3D 0 +OP4 E02E3E 0 +OP4 E02E3F 0 +OP4 E02E40 0 +OP4 E02E41 0 +OP4 E02E42 0 +OP4 E02E43 0 +OP4 E02E44 0 +OP4 E02E45 0 +OP4 E02E46 0 +OP4 E02E47 0 +OP4 E02E48 0 +OP4 E02E49 0 +OP4 E02E4A 0 +OP4 E02E4B 0 +OP4 E02E4C 0 +OP4 E02E4D 0 +OP4 E02E4E 0 +OP4 E02E4F 0 +OP4 E02E50 0 +OP4 E02E51 0 +OP4 E02E52 0 +OP4 E02E53 0 +OP4 E02E54 0 +OP4 E02E55 0 +OP4 E02E56 0 +OP4 E02E57 0 +OP4 E02E58 0 +OP4 E02E59 0 +OP4 E02E5A 0 +OP4 E02E5B 0 +OP4 E02E5C 0 +OP4 E02E5D 0 +OP4 E02E5E 0 +OP4 E02E5F 0 +OP4 E02E60 0 +OP4 E02E61 0 +OP4 E02E62 0 +OP4 E02E63 0 +OP4 E02E64 0 +OP4 E02E65 0 +OP4 E02E66 0 +OP4 E02E67 0 +OP4 E02E68 0 +OP4 E02E69 0 +OP4 E02E6A 0 +OP4 E02E6B 0 +OP4 E02E6C 0 +OP4 E02E6D 0 +OP4 E02E6E 0 +OP4 E02E6F 0 +OP4 E02E70 0 +OP4 E02E71 0 +OP4 E02E72 0 +OP4 E02E73 0 +OP4 E02E74 0 +OP4 E02E75 0 +OP4 E02E76 0 +OP4 E02E77 0 +OP4 E02E78 0 +OP4 E02E79 0 +OP4 E02E7A 0 +OP4 E02E7B 0 +OP4 E02E7C 0 +OP4 E02E7D 0 +OP4 E02E7E 0 +OP4 E02E7F 0 +OP4 E02E80 0 +OP4 E02E81 0 +OP4 E02E82 0 +OP4 E02E83 0 +OP4 E02E84 0 +OP4 E02E85 0 +OP4 E02E86 0 +OP4 E02E87 0 +OP4 E02E88 0 +OP4 E02E89 0 +OP4 E02E8A 0 +OP4 E02E8B 0 +OP4 E02E8C 0 +OP4 E02E8D 0 +OP4 E02E8E 0 +OP4 E02E8F 0 +OP4 E02E90 0 +OP4 E02E91 0 +OP4 E02E92 0 +OP4 E02E93 0 +OP4 E02E94 0 +OP4 E02E95 0 +OP4 E02E96 0 +OP4 E02E97 0 +OP4 E02E98 0 +OP4 E02E99 0 +OP4 E02E9A 0 +OP4 E02E9B 0 +OP4 E02E9C 0 +OP4 E02E9D 0 +OP4 E02E9E 0 +OP4 E02E9F 0 +OP4 E02EA0 0 +OP4 E02EA1 0 +OP4 E02EA2 0 +OP4 E02EA3 0 +OP4 E02EA4 0 +OP4 E02EA5 0 +OP4 E02EA6 0 +OP4 E02EA7 0 +OP4 E02EA8 0 +OP4 E02EA9 0 +OP4 E02EAA 0 +OP4 E02EAB 0 +OP4 E02EAC 0 +OP4 E02EAD 0 +OP4 E02EAE 0 +OP4 E02EAF 0 +OP4 E02EB0 0 +OP4 E02EB1 0 +OP4 E02EB2 0 +OP4 E02EB3 0 +OP4 E02EB4 0 +OP4 E02EB5 0 +OP4 E02EB6 0 +OP4 E02EB7 0 +OP4 E02EB8 0 +OP4 E02EB9 0 +OP4 E02EBA 0 +OP4 E02EBB 0 +OP4 E02EBC 0 +OP4 E02EBD 0 +OP4 E02EBE 0 +OP4 E02EBF 0 +OP4 E02EC0 0 +OP4 E02EC1 0 +OP4 E02EC2 0 +OP4 E02EC3 0 +OP4 E02EC4 0 +OP4 E02EC5 0 +OP4 E02EC6 0 +OP4 E02EC7 0 +OP4 E02EC8 0 +OP4 E02EC9 0 +OP4 E02ECA 0 +OP4 E02ECB 0 +OP4 E02ECC 0 +OP4 E02ECD 0 +OP4 E02ECE 0 +OP4 E02ECF 0 +OP4 E02ED0 0 +OP4 E02ED1 0 +OP4 E02ED2 0 +OP4 E02ED3 0 +OP4 E02ED4 0 +OP4 E02ED5 0 +OP4 E02ED6 0 +OP4 E02ED7 0 +OP4 E02ED8 0 +OP4 E02ED9 0 +OP4 E02EDA 0 +OP4 E02EDB 0 +OP4 E02EDC 0 +OP4 E02EDD 0 +OP4 E02EDE 0 +OP4 E02EDF 0 +OP4 E02EE0 0 +OP4 E02EE1 0 +OP4 E02EE2 0 +OP4 E02EE3 0 +OP4 E02EE4 0 +OP4 E02EE5 0 +OP4 E02EE6 0 +OP4 E02EE7 0 +OP4 E02EE8 0 +OP4 E02EE9 0 +OP4 E02EEA 0 +OP4 E02EEB 0 +OP4 E02EEC 0 +OP4 E02EED 0 +OP4 E02EEE 0 +OP4 E02EEF 0 +OP4 E02EF0 0 +OP4 E02EF1 0 +OP4 E02EF2 0 +OP4 E02EF3 0 +OP4 E02EF4 0 +OP4 E02EF5 0 +OP4 E02EF6 0 +OP4 E02EF7 0 +OP4 E02EF8 0 +OP4 E02EF9 0 +OP4 E02EFA 0 +OP4 E02EFB 0 +OP4 E02EFC 0 +OP4 E02EFD 0 +OP4 E02EFE 0 +OP4 E02EFF 0 +OP4 E02F00 0 +OP4 E02F01 0 +OP4 E02F02 0 +OP4 E02F03 0 +OP4 E02F04 0 +OP4 E02F05 0 +OP4 E02F06 0 +OP4 E02F07 0 +OP4 E02F08 0 +OP4 E02F09 0 +OP4 E02F0A 0 +OP4 E02F0B 0 +OP4 E02F0C 0 +OP4 E02F0D 0 +OP4 E02F0E 0 +OP4 E02F0F 0 +OP4 E02F10 0 +OP4 E02F11 0 +OP4 E02F12 0 +OP4 E02F13 0 +OP4 E02F14 0 +OP4 E02F15 0 +OP4 E02F16 0 +OP4 E02F17 0 +OP4 E02F18 0 +OP4 E02F19 0 +OP4 E02F1A 0 +OP4 E02F1B 0 +OP4 E02F1C 0 +OP4 E02F1D 0 +OP4 E02F1E 0 +OP4 E02F1F 0 +OP4 E02F20 0 +OP4 E02F21 0 +OP4 E02F22 0 +OP4 E02F23 0 +OP4 E02F24 0 +OP4 E02F25 0 +OP4 E02F26 0 +OP4 E02F27 0 +OP4 E02F28 0 +OP4 E02F29 0 +OP4 E02F2A 0 +OP4 E02F2B 0 +OP4 E02F2C 0 +OP4 E02F2D 0 +OP4 E02F2E 0 +OP4 E02F2F 0 +OP4 E02F30 0 +OP4 E02F31 0 +OP4 E02F32 0 +OP4 E02F33 0 +OP4 E02F34 0 +OP4 E02F35 0 +OP4 E02F36 0 +OP4 E02F37 0 +OP4 E02F38 0 +OP4 E02F39 0 +OP4 E02F3A 0 +OP4 E02F3B 0 +OP4 E02F3C 0 +OP4 E02F3D 0 +OP4 E02F3E 0 +OP4 E02F3F 0 +OP4 E02F40 0 +OP4 E02F41 0 +OP4 E02F42 0 +OP4 E02F43 0 +OP4 E02F44 0 +OP4 E02F45 0 +OP4 E02F46 0 +OP4 E02F47 0 +OP4 E02F48 0 +OP4 E02F49 0 +OP4 E02F4A 0 +OP4 E02F4B 0 +OP4 E02F4C 0 +OP4 E02F4D 0 +OP4 E02F4E 0 +OP4 E02F4F 0 +OP4 E02F50 0 +OP4 E02F51 0 +OP4 E02F52 0 +OP4 E02F53 0 +OP4 E02F54 0 +OP4 E02F55 0 +OP4 E02F56 0 +OP4 E02F57 0 +OP4 E02F58 0 +OP4 E02F59 0 +OP4 E02F5A 0 +OP4 E02F5B 0 +OP4 E02F5C 0 +OP4 E02F5D 0 +OP4 E02F5E 0 +OP4 E02F5F 0 +OP4 E02F60 0 +OP4 E02F61 0 +OP4 E02F62 0 +OP4 E02F63 0 +OP4 E02F64 0 +OP4 E02F65 0 +OP4 E02F66 0 +OP4 E02F67 0 +OP4 E02F68 0 +OP4 E02F69 0 +OP4 E02F6A 0 +OP4 E02F6B 0 +OP4 E02F6C 0 +OP4 E02F6D 0 +OP4 E02F6E 0 +OP4 E02F6F 0 +OP4 E02F70 0 +OP4 E02F71 0 +OP4 E02F72 0 +OP4 E02F73 0 +OP4 E02F74 0 +OP4 E02F75 0 +OP4 E02F76 0 +OP4 E02F77 0 +OP4 E02F78 0 +OP4 E02F79 0 +OP4 E02F7A 0 +OP4 E02F7B 0 +OP4 E02F7C 0 +OP4 E02F7D 0 +OP4 E02F7E 0 +OP4 E02F7F 0 +OP4 E02F80 0 +OP4 E02F81 0 +OP4 E02F82 0 +OP4 E02F83 0 +OP4 E02F84 0 +OP4 E02F85 0 +OP4 E02F86 0 +OP4 E02F87 0 +OP4 E02F88 0 +OP4 E02F89 0 +OP4 E02F8A 0 +OP4 E02F8B 0 +OP4 E02F8C 0 +OP4 E02F8D 0 +OP4 E02F8E 0 +OP4 E02F8F 0 +OP4 E02F90 0 +OP4 E02F91 0 +OP4 E02F92 0 +OP4 E02F93 0 +OP4 E02F94 0 +OP4 E02F95 0 +OP4 E02F96 0 +OP4 E02F97 0 +OP4 E02F98 0 +OP4 E02F99 0 +OP4 E02F9A 0 +OP4 E02F9B 0 +OP4 E02F9C 0 +OP4 E02F9D 0 +OP4 E02F9E 0 +OP4 E02F9F 0 +OP4 E02FA0 0 +OP4 E02FA1 0 +OP4 E02FA2 0 +OP4 E02FA3 0 +OP4 E02FA4 0 +OP4 E02FA5 0 +OP4 E02FA6 0 +OP4 E02FA7 0 +OP4 E02FA8 0 +OP4 E02FA9 0 +OP4 E02FAA 0 +OP4 E02FAB 0 +OP4 E02FAC 0 +OP4 E02FAD 0 +OP4 E02FAE 0 +OP4 E02FAF 0 +OP4 E02FB0 0 +OP4 E02FB1 0 +OP4 E02FB2 0 +OP4 E02FB3 0 +OP4 E02FB4 0 +OP4 E02FB5 0 +OP4 E02FB6 0 +OP4 E02FB7 0 +OP4 E02FB8 0 +OP4 E02FB9 0 +OP4 E02FBA 0 +OP4 E02FBB 0 +OP4 E02FBC 0 +OP4 E02FBD 0 +OP4 E02FBE 0 +OP4 E02FBF 0 +OP4 E02FC0 0 +OP4 E02FC1 0 +OP4 E02FC2 0 +OP4 E02FC3 0 +OP4 E02FC4 0 +OP4 E02FC5 0 +OP4 E02FC6 0 +OP4 E02FC7 0 +OP4 E02FC8 0 +OP4 E02FC9 0 +OP4 E02FCA 0 +OP4 E02FCB 0 +OP4 E02FCC 0 +OP4 E02FCD 0 +OP4 E02FCE 0 +OP4 E02FCF 0 +OP4 E02FD0 0 +OP4 E02FD1 0 +OP4 E02FD2 0 +OP4 E02FD3 0 +OP4 E02FD4 0 +OP4 E02FD5 0 +OP4 E02FD6 0 +OP4 E02FD7 0 +OP4 E02FD8 0 +OP4 E02FD9 0 +OP4 E02FDA 0 +OP4 E02FDB 0 +OP4 E02FDC 0 +OP4 E02FDD 0 +OP4 E02FDE 0 +OP4 E02FDF 0 +OP4 E02FE0 0 +OP4 E02FE1 0 +OP4 E02FE2 0 +OP4 E02FE3 0 +OP4 E02FE4 0 +OP4 E02FE5 0 +OP4 E02FE6 0 +OP4 E02FE7 0 +OP4 E02FE8 0 +OP4 E02FE9 0 +OP4 E02FEA 0 +OP4 E02FEB 0 +OP4 E02FEC 0 +OP4 E02FED 0 +OP4 E02FEE 0 +OP4 E02FEF 0 +OP4 E02FF0 0 +OP4 E02FF1 0 +OP4 E02FF2 0 +OP4 E02FF3 0 +OP4 E02FF4 0 +OP4 E02FF5 0 +OP4 E02FF6 0 +OP4 E02FF7 0 +OP4 E02FF8 0 +OP4 E02FF9 0 +OP4 E02FFA 0 +OP4 E02FFB 0 +OP4 E02FFC 0 +OP4 E02FFD 0 +OP4 E02FFE 0 +OP4 E02FFF 0 +OP4 E03000 0 +OP4 E03001 0 +OP4 E03002 0 +OP4 E03003 0 +OP4 E03004 0 +OP4 E03005 0 +OP4 E03006 0 +OP4 E03007 0 +OP4 E03008 0 +OP4 E03009 0 +OP4 E0300A 0 +OP4 E0300B 0 +OP4 E0300C 0 +OP4 E0300D 0 +OP4 E0300E 0 +OP4 E0300F 0 +OP4 E03010 0 +OP4 E03011 0 +OP4 E03012 0 +OP4 E03013 0 +OP4 E03014 0 +OP4 E03015 0 +OP4 E03016 0 +OP4 E03017 0 +OP4 E03018 0 +OP4 E03019 0 +OP4 E0301A 0 +OP4 E0301B 0 +OP4 E0301C 0 +OP4 E0301D 0 +OP4 E0301E 0 +OP4 E0301F 0 +OP4 E03020 0 +OP4 E03021 0 +OP4 E03022 0 +OP4 E03023 0 +OP4 E03024 0 +OP4 E03025 0 +OP4 E03026 0 +OP4 E03027 0 +OP4 E03028 0 +OP4 E03029 0 +OP4 E0302A 0 +OP4 E0302B 0 +OP4 E0302C 0 +OP4 E0302D 0 +OP4 E0302E 0 +OP4 E0302F 0 +OP4 E03030 0 +OP4 E03031 0 +OP4 E03032 0 +OP4 E03033 0 +OP4 E03034 0 +OP4 E03035 0 +OP4 E03036 0 +OP4 E03037 0 +OP4 E03038 0 +OP4 E03039 0 +OP4 E0303A 0 +OP4 E0303B 0 +OP4 E0303C 0 +OP4 E0303D 0 +OP4 E0303E 0 +OP4 E0303F 0 +OP4 E03040 0 +OP4 E03041 0 +OP4 E03042 0 +OP4 E03043 0 +OP4 E03044 0 +OP4 E03045 0 +OP4 E03046 0 +OP4 E03047 0 +OP4 E03048 0 +OP4 E03049 0 +OP4 E0304A 0 +OP4 E0304B 0 +OP4 E0304C 0 +OP4 E0304D 0 +OP4 E0304E 0 +OP4 E0304F 0 +OP4 E03050 0 +OP4 E03051 0 +OP4 E03052 0 +OP4 E03053 0 +OP4 E03054 0 +OP4 E03055 0 +OP4 E03056 0 +OP4 E03057 0 +OP4 E03058 0 +OP4 E03059 0 +OP4 E0305A 0 +OP4 E0305B 0 +OP4 E0305C 0 +OP4 E0305D 0 +OP4 E0305E 0 +OP4 E0305F 0 +OP4 E03060 0 +OP4 E03061 0 +OP4 E03062 0 +OP4 E03063 0 +OP4 E03064 0 +OP4 E03065 0 +OP4 E03066 0 +OP4 E03067 0 +OP4 E03068 0 +OP4 E03069 0 +OP4 E0306A 0 +OP4 E0306B 0 +OP4 E0306C 0 +OP4 E0306D 0 +OP4 E0306E 0 +OP4 E0306F 0 +OP4 E03070 0 +OP4 E03071 0 +OP4 E03072 0 +OP4 E03073 0 +OP4 E03074 0 +OP4 E03075 0 +OP4 E03076 0 +OP4 E03077 0 +OP4 E03078 0 +OP4 E03079 0 +OP4 E0307A 0 +OP4 E0307B 0 +OP4 E0307C 0 +OP4 E0307D 0 +OP4 E0307E 0 +OP4 E0307F 0 +OP4 E03080 0 +OP4 E03081 0 +OP4 E03082 0 +OP4 E03083 0 +OP4 E03084 0 +OP4 E03085 0 +OP4 E03086 0 +OP4 E03087 0 +OP4 E03088 0 +OP4 E03089 0 +OP4 E0308A 0 +OP4 E0308B 0 +OP4 E0308C 0 +OP4 E0308D 0 +OP4 E0308E 0 +OP4 E0308F 0 +OP4 E03090 0 +OP4 E03091 0 +OP4 E03092 0 +OP4 E03093 0 +OP4 E03094 0 +OP4 E03095 0 +OP4 E03096 0 +OP4 E03097 0 +OP4 E03098 0 +OP4 E03099 0 +OP4 E0309A 0 +OP4 E0309B 0 +OP4 E0309C 0 +OP4 E0309D 0 +OP4 E0309E 0 +OP4 E0309F 0 +OP4 E030A0 0 +OP4 E030A1 0 +OP4 E030A2 0 +OP4 E030A3 0 +OP4 E030A4 0 +OP4 E030A5 0 +OP4 E030A6 0 +OP4 E030A7 0 +OP4 E030A8 0 +OP4 E030A9 0 +OP4 E030AA 0 +OP4 E030AB 0 +OP4 E030AC 0 +OP4 E030AD 0 +OP4 E030AE 0 +OP4 E030AF 0 +OP4 E030B0 0 +OP4 E030B1 0 +OP4 E030B2 0 +OP4 E030B3 0 +OP4 E030B4 0 +OP4 E030B5 0 +OP4 E030B6 0 +OP4 E030B7 0 +OP4 E030B8 0 +OP4 E030B9 0 +OP4 E030BA 0 +OP4 E030BB 0 +OP4 E030BC 0 +OP4 E030BD 0 +OP4 E030BE 0 +OP4 E030BF 0 +OP4 E030C0 0 +OP4 E030C1 0 +OP4 E030C2 0 +OP4 E030C3 0 +OP4 E030C4 0 +OP4 E030C5 0 +OP4 E030C6 0 +OP4 E030C7 0 +OP4 E030C8 0 +OP4 E030C9 0 +OP4 E030CA 0 +OP4 E030CB 0 +OP4 E030CC 0 +OP4 E030CD 0 +OP4 E030CE 0 +OP4 E030CF 0 +OP4 E030D0 0 +OP4 E030D1 0 +OP4 E030D2 0 +OP4 E030D3 0 +OP4 E030D4 0 +OP4 E030D5 0 +OP4 E030D6 0 +OP4 E030D7 0 +OP4 E030D8 0 +OP4 E030D9 0 +OP4 E030DA 0 +OP4 E030DB 0 +OP4 E030DC 0 +OP4 E030DD 0 +OP4 E030DE 0 +OP4 E030DF 0 +OP4 E030E0 0 +OP4 E030E1 0 +OP4 E030E2 0 +OP4 E030E3 0 +OP4 E030E4 0 +OP4 E030E5 0 +OP4 E030E6 0 +OP4 E030E7 0 +OP4 E030E8 0 +OP4 E030E9 0 +OP4 E030EA 0 +OP4 E030EB 0 +OP4 E030EC 0 +OP4 E030ED 0 +OP4 E030EE 0 +OP4 E030EF 0 +OP4 E030F0 0 +OP4 E030F1 0 +OP4 E030F2 0 +OP4 E030F3 0 +OP4 E030F4 0 +OP4 E030F5 0 +OP4 E030F6 0 +OP4 E030F7 0 +OP4 E030F8 0 +OP4 E030F9 0 +OP4 E030FA 0 +OP4 E030FB 0 +OP4 E030FC 0 +OP4 E030FD 0 +OP4 E030FE 0 +OP4 E030FF 0 +OP4 E03100 0 +OP4 E03101 0 +OP4 E03102 0 +OP4 E03103 0 +OP4 E03104 0 +OP4 E03105 0 +OP4 E03106 0 +OP4 E03107 0 +OP4 E03108 0 +OP4 E03109 0 +OP4 E0310A 0 +OP4 E0310B 0 +OP4 E0310C 0 +OP4 E0310D 0 +OP4 E0310E 0 +OP4 E0310F 0 +OP4 E03110 0 +OP4 E03111 0 +OP4 E03112 0 +OP4 E03113 0 +OP4 E03114 0 +OP4 E03115 0 +OP4 E03116 0 +OP4 E03117 0 +OP4 E03118 0 +OP4 E03119 0 +OP4 E0311A 0 +OP4 E0311B 0 +OP4 E0311C 0 +OP4 E0311D 0 +OP4 E0311E 0 +OP4 E0311F 0 +OP4 E03120 0 +OP4 E03121 0 +OP4 E03122 0 +OP4 E03123 0 +OP4 E03124 0 +OP4 E03125 0 +OP4 E03126 0 +OP4 E03127 0 +OP4 E03128 0 +OP4 E03129 0 +OP4 E0312A 0 +OP4 E0312B 0 +OP4 E0312C 0 +OP4 E0312D 0 +OP4 E0312E 0 +OP4 E0312F 0 +OP4 E03130 0 +OP4 E03131 0 +OP4 E03132 0 +OP4 E03133 0 +OP4 E03134 0 +OP4 E03135 0 +OP4 E03136 0 +OP4 E03137 0 +OP4 E03138 0 +OP4 E03139 0 +OP4 E0313A 0 +OP4 E0313B 0 +OP4 E0313C 0 +OP4 E0313D 0 +OP4 E0313E 0 +OP4 E0313F 0 +OP4 E03140 0 +OP4 E03141 0 +OP4 E03142 0 +OP4 E03143 0 +OP4 E03144 0 +OP4 E03145 0 +OP4 E03146 0 +OP4 E03147 0 +OP4 E03148 0 +OP4 E03149 0 +OP4 E0314A 0 +OP4 E0314B 0 +OP4 E0314C 0 +OP4 E0314D 0 +OP4 E0314E 0 +OP4 E0314F 0 +OP4 E03150 0 +OP4 E03151 0 +OP4 E03152 0 +OP4 E03153 0 +OP4 E03154 0 +OP4 E03155 0 +OP4 E03156 0 +OP4 E03157 0 +OP4 E03158 0 +OP4 E03159 0 +OP4 E0315A 0 +OP4 E0315B 0 +OP4 E0315C 0 +OP4 E0315D 0 +OP4 E0315E 0 +OP4 E0315F 0 +OP4 E03160 0 +OP4 E03161 0 +OP4 E03162 0 +OP4 E03163 0 +OP4 E03164 0 +OP4 E03165 0 +OP4 E03166 0 +OP4 E03167 0 +OP4 E03168 0 +OP4 E03169 0 +OP4 E0316A 0 +OP4 E0316B 0 +OP4 E0316C 0 +OP4 E0316D 0 +OP4 E0316E 0 +OP4 E0316F 0 +OP4 E03170 0 +OP4 E03171 0 +OP4 E03172 0 +OP4 E03173 0 +OP4 E03174 0 +OP4 E03175 0 +OP4 E03176 0 +OP4 E03177 0 +OP4 E03178 0 +OP4 E03179 0 +OP4 E0317A 0 +OP4 E0317B 0 +OP4 E0317C 0 +OP4 E0317D 0 +OP4 E0317E 0 +OP4 E0317F 0 +OP4 E03180 0 +OP4 E03181 0 +OP4 E03182 0 +OP4 E03183 0 +OP4 E03184 0 +OP4 E03185 0 +OP4 E03186 0 +OP4 E03187 0 +OP4 E03188 0 +OP4 E03189 0 +OP4 E0318A 0 +OP4 E0318B 0 +OP4 E0318C 0 +OP4 E0318D 0 +OP4 E0318E 0 +OP4 E0318F 0 +OP4 E03190 0 +OP4 E03191 0 +OP4 E03192 0 +OP4 E03193 0 +OP4 E03194 0 +OP4 E03195 0 +OP4 E03196 0 +OP4 E03197 0 +OP4 E03198 0 +OP4 E03199 0 +OP4 E0319A 0 +OP4 E0319B 0 +OP4 E0319C 0 +OP4 E0319D 0 +OP4 E0319E 0 +OP4 E0319F 0 +OP4 E031A0 0 +OP4 E031A1 0 +OP4 E031A2 0 +OP4 E031A3 0 +OP4 E031A4 0 +OP4 E031A5 0 +OP4 E031A6 0 +OP4 E031A7 0 +OP4 E031A8 0 +OP4 E031A9 0 +OP4 E031AA 0 +OP4 E031AB 0 +OP4 E031AC 0 +OP4 E031AD 0 +OP4 E031AE 0 +OP4 E031AF 0 +OP4 E031B0 0 +OP4 E031B1 0 +OP4 E031B2 0 +OP4 E031B3 0 +OP4 E031B4 0 +OP4 E031B5 0 +OP4 E031B6 0 +OP4 E031B7 0 +OP4 E031B8 0 +OP4 E031B9 0 +OP4 E031BA 0 +OP4 E031BB 0 +OP4 E031BC 0 +OP4 E031BD 0 +OP4 E031BE 0 +OP4 E031BF 0 +OP4 E031C0 0 +OP4 E031C1 0 +OP4 E031C2 0 +OP4 E031C3 0 +OP4 E031C4 0 +OP4 E031C5 0 +OP4 E031C6 0 +OP4 E031C7 0 +OP4 E031C8 0 +OP4 E031C9 0 +OP4 E031CA 0 +OP4 E031CB 0 +OP4 E031CC 0 +OP4 E031CD 0 +OP4 E031CE 0 +OP4 E031CF 0 +OP4 E031D0 0 +OP4 E031D1 0 +OP4 E031D2 0 +OP4 E031D3 0 +OP4 E031D4 0 +OP4 E031D5 0 +OP4 E031D6 0 +OP4 E031D7 0 +OP4 E031D8 0 +OP4 E031D9 0 +OP4 E031DA 0 +OP4 E031DB 0 +OP4 E031DC 0 +OP4 E031DD 0 +OP4 E031DE 0 +OP4 E031DF 0 +OP4 E031E0 0 +OP4 E031E1 0 +OP4 E031E2 0 +OP4 E031E3 0 +OP4 E031E4 0 +OP4 E031E5 0 +OP4 E031E6 0 +OP4 E031E7 0 +OP4 E031E8 0 +OP4 E031E9 0 +OP4 E031EA 0 +OP4 E031EB 0 +OP4 E031EC 0 +OP4 E031ED 0 +OP4 E031EE 0 +OP4 E031EF 0 +OP4 E031F0 0 +OP4 E031F1 0 +OP4 E031F2 0 +OP4 E031F3 0 +OP4 E031F4 0 +OP4 E031F5 0 +OP4 E031F6 0 +OP4 E031F7 0 +OP4 E031F8 0 +OP4 E031F9 0 +OP4 E031FA 0 +OP4 E031FB 0 +OP4 E031FC 0 +OP4 E031FD 0 +OP4 E031FE 0 +OP4 E031FF 0 +OP4 E03200 0 +OP4 E03201 0 +OP4 E03202 0 +OP4 E03203 0 +OP4 E03204 0 +OP4 E03205 0 +OP4 E03206 0 +OP4 E03207 0 +OP4 E03208 0 +OP4 E03209 0 +OP4 E0320A 0 +OP4 E0320B 0 +OP4 E0320C 0 +OP4 E0320D 0 +OP4 E0320E 0 +OP4 E0320F 0 +OP4 E03210 0 +OP4 E03211 0 +OP4 E03212 0 +OP4 E03213 0 +OP4 E03214 0 +OP4 E03215 0 +OP4 E03216 0 +OP4 E03217 0 +OP4 E03218 0 +OP4 E03219 0 +OP4 E0321A 0 +OP4 E0321B 0 +OP4 E0321C 0 +OP4 E0321D 0 +OP4 E0321E 0 +OP4 E0321F 0 +OP4 E03220 0 +OP4 E03221 0 +OP4 E03222 0 +OP4 E03223 0 +OP4 E03224 0 +OP4 E03225 0 +OP4 E03226 0 +OP4 E03227 0 +OP4 E03228 0 +OP4 E03229 0 +OP4 E0322A 0 +OP4 E0322B 0 +OP4 E0322C 0 +OP4 E0322D 0 +OP4 E0322E 0 +OP4 E0322F 0 +OP4 E03230 0 +OP4 E03231 0 +OP4 E03232 0 +OP4 E03233 0 +OP4 E03234 0 +OP4 E03235 0 +OP4 E03236 0 +OP4 E03237 0 +OP4 E03238 0 +OP4 E03239 0 +OP4 E0323A 0 +OP4 E0323B 0 +OP4 E0323C 0 +OP4 E0323D 0 +OP4 E0323E 0 +OP4 E0323F 0 +OP4 E03240 0 +OP4 E03241 0 +OP4 E03242 0 +OP4 E03243 0 +OP4 E03244 0 +OP4 E03245 0 +OP4 E03246 0 +OP4 E03247 0 +OP4 E03248 0 +OP4 E03249 0 +OP4 E0324A 0 +OP4 E0324B 0 +OP4 E0324C 0 +OP4 E0324D 0 +OP4 E0324E 0 +OP4 E0324F 0 +OP4 E03250 0 +OP4 E03251 0 +OP4 E03252 0 +OP4 E03253 0 +OP4 E03254 0 +OP4 E03255 0 +OP4 E03256 0 +OP4 E03257 0 +OP4 E03258 0 +OP4 E03259 0 +OP4 E0325A 0 +OP4 E0325B 0 +OP4 E0325C 0 +OP4 E0325D 0 +OP4 E0325E 0 +OP4 E0325F 0 +OP4 E03260 0 +OP4 E03261 0 +OP4 E03262 0 +OP4 E03263 0 +OP4 E03264 0 +OP4 E03265 0 +OP4 E03266 0 +OP4 E03267 0 +OP4 E03268 0 +OP4 E03269 0 +OP4 E0326A 0 +OP4 E0326B 0 +OP4 E0326C 0 +OP4 E0326D 0 +OP4 E0326E 0 +OP4 E0326F 0 +OP4 E03270 0 +OP4 E03271 0 +OP4 E03272 0 +OP4 E03273 0 +OP4 E03274 0 +OP4 E03275 0 +OP4 E03276 0 +OP4 E03277 0 +OP4 E03278 0 +OP4 E03279 0 +OP4 E0327A 0 +OP4 E0327B 0 +OP4 E0327C 0 +OP4 E0327D 0 +OP4 E0327E 0 +OP4 E0327F 0 +OP4 E03280 0 +OP4 E03281 0 +OP4 E03282 0 +OP4 E03283 0 +OP4 E03284 0 +OP4 E03285 0 +OP4 E03286 0 +OP4 E03287 0 +OP4 E03288 0 +OP4 E03289 0 +OP4 E0328A 0 +OP4 E0328B 0 +OP4 E0328C 0 +OP4 E0328D 0 +OP4 E0328E 0 +OP4 E0328F 0 +OP4 E03290 0 +OP4 E03291 0 +OP4 E03292 0 +OP4 E03293 0 +OP4 E03294 0 +OP4 E03295 0 +OP4 E03296 0 +OP4 E03297 0 +OP4 E03298 0 +OP4 E03299 0 +OP4 E0329A 0 +OP4 E0329B 0 +OP4 E0329C 0 +OP4 E0329D 0 +OP4 E0329E 0 +OP4 E0329F 0 +OP4 E032A0 0 +OP4 E032A1 0 +OP4 E032A2 0 +OP4 E032A3 0 +OP4 E032A4 0 +OP4 E032A5 0 +OP4 E032A6 0 +OP4 E032A7 0 +OP4 E032A8 0 +OP4 E032A9 0 +OP4 E032AA 0 +OP4 E032AB 0 +OP4 E032AC 0 +OP4 E032AD 0 +OP4 E032AE 0 +OP4 E032AF 0 +OP4 E032B0 0 +OP4 E032B1 0 +OP4 E032B2 0 +OP4 E032B3 0 +OP4 E032B4 0 +OP4 E032B5 0 +OP4 E032B6 0 +OP4 E032B7 0 +OP4 E032B8 0 +OP4 E032B9 0 +OP4 E032BA 0 +OP4 E032BB 0 +OP4 E032BC 0 +OP4 E032BD 0 +OP4 E032BE 0 +OP4 E032BF 0 +OP4 E032C0 0 +OP4 E032C1 0 +OP4 E032C2 0 +OP4 E032C3 0 +OP4 E032C4 0 +OP4 E032C5 0 +OP4 E032C6 0 +OP4 E032C7 0 +OP4 E032C8 0 +OP4 E032C9 0 +OP4 E032CA 0 +OP4 E032CB 0 +OP4 E032CC 0 +OP4 E032CD 0 +OP4 E032CE 0 +OP4 E032CF 0 +OP4 E032D0 0 +OP4 E032D1 0 +OP4 E032D2 0 +OP4 E032D3 0 +OP4 E032D4 0 +OP4 E032D5 0 +OP4 E032D6 0 +OP4 E032D7 0 +OP4 E032D8 0 +OP4 E032D9 0 +OP4 E032DA 0 +OP4 E032DB 0 +OP4 E032DC 0 +OP4 E032DD 0 +OP4 E032DE 0 +OP4 E032DF 0 +OP4 E032E0 0 +OP4 E032E1 0 +OP4 E032E2 0 +OP4 E032E3 0 +OP4 E032E4 0 +OP4 E032E5 0 +OP4 E032E6 0 +OP4 E032E7 0 +OP4 E032E8 0 +OP4 E032E9 0 +OP4 E032EA 0 +OP4 E032EB 0 +OP4 E032EC 0 +OP4 E032ED 0 +OP4 E032EE 0 +OP4 E032EF 0 +OP4 E032F0 0 +OP4 E032F1 0 +OP4 E032F2 0 +OP4 E032F3 0 +OP4 E032F4 0 +OP4 E032F5 0 +OP4 E032F6 0 +OP4 E032F7 0 +OP4 E032F8 0 +OP4 E032F9 0 +OP4 E032FA 0 +OP4 E032FB 0 +OP4 E032FC 0 +OP4 E032FD 0 +OP4 E032FE 0 +OP4 E032FF 0 +OP4 E03300 0 +OP4 E03301 0 +OP4 E03302 0 +OP4 E03303 0 +OP4 E03304 0 +OP4 E03305 0 +OP4 E03306 0 +OP4 E03307 0 +OP4 E03308 0 +OP4 E03309 0 +OP4 E0330A 0 +OP4 E0330B 0 +OP4 E0330C 0 +OP4 E0330D 0 +OP4 E0330E 0 +OP4 E0330F 0 +OP4 E03310 0 +OP4 E03311 0 +OP4 E03312 0 +OP4 E03313 0 +OP4 E03314 0 +OP4 E03315 0 +OP4 E03316 0 +OP4 E03317 0 +OP4 E03318 0 +OP4 E03319 0 +OP4 E0331A 0 +OP4 E0331B 0 +OP4 E0331C 0 +OP4 E0331D 0 +OP4 E0331E 0 +OP4 E0331F 0 +OP4 E03320 0 +OP4 E03321 0 +OP4 E03322 0 +OP4 E03323 0 +OP4 E03324 0 +OP4 E03325 0 +OP4 E03326 0 +OP4 E03327 0 +OP4 E03328 0 +OP4 E03329 0 +OP4 E0332A 0 +OP4 E0332B 0 +OP4 E0332C 0 +OP4 E0332D 0 +OP4 E0332E 0 +OP4 E0332F 0 +OP4 E03330 0 +OP4 E03331 0 +OP4 E03332 0 +OP4 E03333 0 +OP4 E03334 0 +OP4 E03335 0 +OP4 E03336 0 +OP4 E03337 0 +OP4 E03338 0 +OP4 E03339 0 +OP4 E0333A 0 +OP4 E0333B 0 +OP4 E0333C 0 +OP4 E0333D 0 +OP4 E0333E 0 +OP4 E0333F 0 +OP4 E03340 0 +OP4 E03341 0 +OP4 E03342 0 +OP4 E03343 0 +OP4 E03344 0 +OP4 E03345 0 +OP4 E03346 0 +OP4 E03347 0 +OP4 E03348 0 +OP4 E03349 0 +OP4 E0334A 0 +OP4 E0334B 0 +OP4 E0334C 0 +OP4 E0334D 0 +OP4 E0334E 0 +OP4 E0334F 0 +OP4 E03350 0 +OP4 E03351 0 +OP4 E03352 0 +OP4 E03353 0 +OP4 E03354 0 +OP4 E03355 0 +OP4 E03356 0 +OP4 E03357 0 +OP4 E03358 0 +OP4 E03359 0 +OP4 E0335A 0 +OP4 E0335B 0 +OP4 E0335C 0 +OP4 E0335D 0 +OP4 E0335E 0 +OP4 E0335F 0 +OP4 E03360 0 +OP4 E03361 0 +OP4 E03362 0 +OP4 E03363 0 +OP4 E03364 0 +OP4 E03365 0 +OP4 E03366 0 +OP4 E03367 0 +OP4 E03368 0 +OP4 E03369 0 +OP4 E0336A 0 +OP4 E0336B 0 +OP4 E0336C 0 +OP4 E0336D 0 +OP4 E0336E 0 +OP4 E0336F 0 +OP4 E03370 0 +OP4 E03371 0 +OP4 E03372 0 +OP4 E03373 0 +OP4 E03374 0 +OP4 E03375 0 +OP4 E03376 0 +OP4 E03377 0 +OP4 E03378 0 +OP4 E03379 0 +OP4 E0337A 0 +OP4 E0337B 0 +OP4 E0337C 0 +OP4 E0337D 0 +OP4 E0337E 0 +OP4 E0337F 0 +OP4 E03380 0 +OP4 E03381 0 +OP4 E03382 0 +OP4 E03383 0 +OP4 E03384 0 +OP4 E03385 0 +OP4 E03386 0 +OP4 E03387 0 +OP4 E03388 0 +OP4 E03389 0 +OP4 E0338A 0 +OP4 E0338B 0 +OP4 E0338C 0 +OP4 E0338D 0 +OP4 E0338E 0 +OP4 E0338F 0 +OP4 E03390 0 +OP4 E03391 0 +OP4 E03392 0 +OP4 E03393 0 +OP4 E03394 0 +OP4 E03395 0 +OP4 E03396 0 +OP4 E03397 0 +OP4 E03398 0 +OP4 E03399 0 +OP4 E0339A 0 +OP4 E0339B 0 +OP4 E0339C 0 +OP4 E0339D 0 +OP4 E0339E 0 +OP4 E0339F 0 +OP4 E033A0 0 +OP4 E033A1 0 +OP4 E033A2 0 +OP4 E033A3 0 +OP4 E033A4 0 +OP4 E033A5 0 +OP4 E033A6 0 +OP4 E033A7 0 +OP4 E033A8 0 +OP4 E033A9 0 +OP4 E033AA 0 +OP4 E033AB 0 +OP4 E033AC 0 +OP4 E033AD 0 +OP4 E033AE 0 +OP4 E033AF 0 +OP4 E033B0 0 +OP4 E033B1 0 +OP4 E033B2 0 +OP4 E033B3 0 +OP4 E033B4 0 +OP4 E033B5 0 +OP4 E033B6 0 +OP4 E033B7 0 +OP4 E033B8 0 +OP4 E033B9 0 +OP4 E033BA 0 +OP4 E033BB 0 +OP4 E033BC 0 +OP4 E033BD 0 +OP4 E033BE 0 +OP4 E033BF 0 +OP4 E033C0 0 +OP4 E033C1 0 +OP4 E033C2 0 +OP4 E033C3 0 +OP4 E033C4 0 +OP4 E033C5 0 +OP4 E033C6 0 +OP4 E033C7 0 +OP4 E033C8 0 +OP4 E033C9 0 +OP4 E033CA 0 +OP4 E033CB 0 +OP4 E033CC 0 +OP4 E033CD 0 +OP4 E033CE 0 +OP4 E033CF 0 +OP4 E033D0 0 +OP4 E033D1 0 +OP4 E033D2 0 +OP4 E033D3 0 +OP4 E033D4 0 +OP4 E033D5 0 +OP4 E033D6 0 +OP4 E033D7 0 +OP4 E033D8 0 +OP4 E033D9 0 +OP4 E033DA 0 +OP4 E033DB 0 +OP4 E033DC 0 +OP4 E033DD 0 +OP4 E033DE 0 +OP4 E033DF 0 +OP4 E033E0 0 +OP4 E033E1 0 +OP4 E033E2 0 +OP4 E033E3 0 +OP4 E033E4 0 +OP4 E033E5 0 +OP4 E033E6 0 +OP4 E033E7 0 +OP4 E033E8 0 +OP4 E033E9 0 +OP4 E033EA 0 +OP4 E033EB 0 +OP4 E033EC 0 +OP4 E033ED 0 +OP4 E033EE 0 +OP4 E033EF 0 +OP4 E033F0 0 +OP4 E033F1 0 +OP4 E033F2 0 +OP4 E033F3 0 +OP4 E033F4 0 +OP4 E033F5 0 +OP4 E033F6 0 +OP4 E033F7 0 +OP4 E033F8 0 +OP4 E033F9 0 +OP4 E033FA 0 +OP4 E033FB 0 +OP4 E033FC 0 +OP4 E033FD 0 +OP4 E033FE 0 +OP4 E033FF 0 +OP4 E03400 0 +OP4 E03401 0 +OP4 E03402 0 +OP4 E03403 0 +OP4 E03404 0 +OP4 E03405 0 +OP4 E03406 0 +OP4 E03407 0 +OP4 E03408 0 +OP4 E03409 0 +OP4 E0340A 0 +OP4 E0340B 0 +OP4 E0340C 0 +OP4 E0340D 0 +OP4 E0340E 0 +OP4 E0340F 0 +OP4 E03410 0 +OP4 E03411 0 +OP4 E03412 0 +OP4 E03413 0 +OP4 E03414 0 +OP4 E03415 0 +OP4 E03416 0 +OP4 E03417 0 +OP4 E03418 0 +OP4 E03419 0 +OP4 E0341A 0 +OP4 E0341B 0 +OP4 E0341C 0 +OP4 E0341D 0 +OP4 E0341E 0 +OP4 E0341F 0 +OP4 E03420 0 +OP4 E03421 0 +OP4 E03422 0 +OP4 E03423 0 +OP4 E03424 0 +OP4 E03425 0 +OP4 E03426 0 +OP4 E03427 0 +OP4 E03428 0 +OP4 E03429 0 +OP4 E0342A 0 +OP4 E0342B 0 +OP4 E0342C 0 +OP4 E0342D 0 +OP4 E0342E 0 +OP4 E0342F 0 +OP4 E03430 0 +OP4 E03431 0 +OP4 E03432 0 +OP4 E03433 0 +OP4 E03434 0 +OP4 E03435 0 +OP4 E03436 0 +OP4 E03437 0 +OP4 E03438 0 +OP4 E03439 0 +OP4 E0343A 0 +OP4 E0343B 0 +OP4 E0343C 0 +OP4 E0343D 0 +OP4 E0343E 0 +OP4 E0343F 0 +OP4 E03440 0 +OP4 E03441 0 +OP4 E03442 0 +OP4 E03443 0 +OP4 E03444 0 +OP4 E03445 0 +OP4 E03446 0 +OP4 E03447 0 +OP4 E03448 0 +OP4 E03449 0 +OP4 E0344A 0 +OP4 E0344B 0 +OP4 E0344C 0 +OP4 E0344D 0 +OP4 E0344E 0 +OP4 E0344F 0 +OP4 E03450 0 +OP4 E03451 0 +OP4 E03452 0 +OP4 E03453 0 +OP4 E03454 0 +OP4 E03455 0 +OP4 E03456 0 +OP4 E03457 0 +OP4 E03458 0 +OP4 E03459 0 +OP4 E0345A 0 +OP4 E0345B 0 +OP4 E0345C 0 +OP4 E0345D 0 +OP4 E0345E 0 +OP4 E0345F 0 +OP4 E03460 0 +OP4 E03461 0 +OP4 E03462 0 +OP4 E03463 0 +OP4 E03464 0 +OP4 E03465 0 +OP4 E03466 0 +OP4 E03467 0 +OP4 E03468 0 +OP4 E03469 0 +OP4 E0346A 0 +OP4 E0346B 0 +OP4 E0346C 0 +OP4 E0346D 0 +OP4 E0346E 0 +OP4 E0346F 0 +OP4 E03470 0 +OP4 E03471 0 +OP4 E03472 0 +OP4 E03473 0 +OP4 E03474 0 +OP4 E03475 0 +OP4 E03476 0 +OP4 E03477 0 +OP4 E03478 0 +OP4 E03479 0 +OP4 E0347A 0 +OP4 E0347B 0 +OP4 E0347C 0 +OP4 E0347D 0 +OP4 E0347E 0 +OP4 E0347F 0 +OP4 E03480 0 +OP4 E03481 0 +OP4 E03482 0 +OP4 E03483 0 +OP4 E03484 0 +OP4 E03485 0 +OP4 E03486 0 +OP4 E03487 0 +OP4 E03488 0 +OP4 E03489 0 +OP4 E0348A 0 +OP4 E0348B 0 +OP4 E0348C 0 +OP4 E0348D 0 +OP4 E0348E 0 +OP4 E0348F 0 +OP4 E03490 0 +OP4 E03491 0 +OP4 E03492 0 +OP4 E03493 0 +OP4 E03494 0 +OP4 E03495 0 +OP4 E03496 0 +OP4 E03497 0 +OP4 E03498 0 +OP4 E03499 0 +OP4 E0349A 0 +OP4 E0349B 0 +OP4 E0349C 0 +OP4 E0349D 0 +OP4 E0349E 0 +OP4 E0349F 0 +OP4 E034A0 0 +OP4 E034A1 0 +OP4 E034A2 0 +OP4 E034A3 0 +OP4 E034A4 0 +OP4 E034A5 0 +OP4 E034A6 0 +OP4 E034A7 0 +OP4 E034A8 0 +OP4 E034A9 0 +OP4 E034AA 0 +OP4 E034AB 0 +OP4 E034AC 0 +OP4 E034AD 0 +OP4 E034AE 0 +OP4 E034AF 0 +OP4 E034B0 0 +OP4 E034B1 0 +OP4 E034B2 0 +OP4 E034B3 0 +OP4 E034B4 0 +OP4 E034B5 0 +OP4 E034B6 0 +OP4 E034B7 0 +OP4 E034B8 0 +OP4 E034B9 0 +OP4 E034BA 0 +OP4 E034BB 0 +OP4 E034BC 0 +OP4 E034BD 0 +OP4 E034BE 0 +OP4 E034BF 0 +OP4 E034C0 0 +OP4 E034C1 0 +OP4 E034C2 0 +OP4 E034C3 0 +OP4 E034C4 0 +OP4 E034C5 0 +OP4 E034C6 0 +OP4 E034C7 0 +OP4 E034C8 0 +OP4 E034C9 0 +OP4 E034CA 0 +OP4 E034CB 0 +OP4 E034CC 0 +OP4 E034CD 0 +OP4 E034CE 0 +OP4 E034CF 0 +OP4 E034D0 0 +OP4 E034D1 0 +OP4 E034D2 0 +OP4 E034D3 0 +OP4 E034D4 0 +OP4 E034D5 0 +OP4 E034D6 0 +OP4 E034D7 0 +OP4 E034D8 0 +OP4 E034D9 0 +OP4 E034DA 0 +OP4 E034DB 0 +OP4 E034DC 0 +OP4 E034DD 0 +OP4 E034DE 0 +OP4 E034DF 0 +OP4 E034E0 0 +OP4 E034E1 0 +OP4 E034E2 0 +OP4 E034E3 0 +OP4 E034E4 0 +OP4 E034E5 0 +OP4 E034E6 0 +OP4 E034E7 0 +OP4 E034E8 0 +OP4 E034E9 0 +OP4 E034EA 0 +OP4 E034EB 0 +OP4 E034EC 0 +OP4 E034ED 0 +OP4 E034EE 0 +OP4 E034EF 0 +OP4 E034F0 0 +OP4 E034F1 0 +OP4 E034F2 0 +OP4 E034F3 0 +OP4 E034F4 0 +OP4 E034F5 0 +OP4 E034F6 0 +OP4 E034F7 0 +OP4 E034F8 0 +OP4 E034F9 0 +OP4 E034FA 0 +OP4 E034FB 0 +OP4 E034FC 0 +OP4 E034FD 0 +OP4 E034FE 0 +OP4 E034FF 0 +OP4 E03500 0 +OP4 E03501 0 +OP4 E03502 0 +OP4 E03503 0 +OP4 E03504 0 +OP4 E03505 0 +OP4 E03506 0 +OP4 E03507 0 +OP4 E03508 0 +OP4 E03509 0 +OP4 E0350A 0 +OP4 E0350B 0 +OP4 E0350C 0 +OP4 E0350D 0 +OP4 E0350E 0 +OP4 E0350F 0 +OP4 E03510 0 +OP4 E03511 0 +OP4 E03512 0 +OP4 E03513 0 +OP4 E03514 0 +OP4 E03515 0 +OP4 E03516 0 +OP4 E03517 0 +OP4 E03518 0 +OP4 E03519 0 +OP4 E0351A 0 +OP4 E0351B 0 +OP4 E0351C 0 +OP4 E0351D 0 +OP4 E0351E 0 +OP4 E0351F 0 +OP4 E03520 0 +OP4 E03521 0 +OP4 E03522 0 +OP4 E03523 0 +OP4 E03524 0 +OP4 E03525 0 +OP4 E03526 0 +OP4 E03527 0 +OP4 E03528 0 +OP4 E03529 0 +OP4 E0352A 0 +OP4 E0352B 0 +OP4 E0352C 0 +OP4 E0352D 0 +OP4 E0352E 0 +OP4 E0352F 0 +OP4 E03530 0 +OP4 E03531 0 +OP4 E03532 0 +OP4 E03533 0 +OP4 E03534 0 +OP4 E03535 0 +OP4 E03536 0 +OP4 E03537 0 +OP4 E03538 0 +OP4 E03539 0 +OP4 E0353A 0 +OP4 E0353B 0 +OP4 E0353C 0 +OP4 E0353D 0 +OP4 E0353E 0 +OP4 E0353F 0 +OP4 E03540 0 +OP4 E03541 0 +OP4 E03542 0 +OP4 E03543 0 +OP4 E03544 0 +OP4 E03545 0 +OP4 E03546 0 +OP4 E03547 0 +OP4 E03548 0 +OP4 E03549 0 +OP4 E0354A 0 +OP4 E0354B 0 +OP4 E0354C 0 +OP4 E0354D 0 +OP4 E0354E 0 +OP4 E0354F 0 +OP4 E03550 0 +OP4 E03551 0 +OP4 E03552 0 +OP4 E03553 0 +OP4 E03554 0 +OP4 E03555 0 +OP4 E03556 0 +OP4 E03557 0 +OP4 E03558 0 +OP4 E03559 0 +OP4 E0355A 0 +OP4 E0355B 0 +OP4 E0355C 0 +OP4 E0355D 0 +OP4 E0355E 0 +OP4 E0355F 0 +OP4 E03560 0 +OP4 E03561 0 +OP4 E03562 0 +OP4 E03563 0 +OP4 E03564 0 +OP4 E03565 0 +OP4 E03566 0 +OP4 E03567 0 +OP4 E03568 0 +OP4 E03569 0 +OP4 E0356A 0 +OP4 E0356B 0 +OP4 E0356C 0 +OP4 E0356D 0 +OP4 E0356E 0 +OP4 E0356F 0 +OP4 E03570 0 +OP4 E03571 0 +OP4 E03572 0 +OP4 E03573 0 +OP4 E03574 0 +OP4 E03575 0 +OP4 E03576 0 +OP4 E03577 0 +OP4 E03578 0 +OP4 E03579 0 +OP4 E0357A 0 +OP4 E0357B 0 +OP4 E0357C 0 +OP4 E0357D 0 +OP4 E0357E 0 +OP4 E0357F 0 +OP4 E03580 0 +OP4 E03581 0 +OP4 E03582 0 +OP4 E03583 0 +OP4 E03584 0 +OP4 E03585 0 +OP4 E03586 0 +OP4 E03587 0 +OP4 E03588 0 +OP4 E03589 0 +OP4 E0358A 0 +OP4 E0358B 0 +OP4 E0358C 0 +OP4 E0358D 0 +OP4 E0358E 0 +OP4 E0358F 0 +OP4 E03590 0 +OP4 E03591 0 +OP4 E03592 0 +OP4 E03593 0 +OP4 E03594 0 +OP4 E03595 0 +OP4 E03596 0 +OP4 E03597 0 +OP4 E03598 0 +OP4 E03599 0 +OP4 E0359A 0 +OP4 E0359B 0 +OP4 E0359C 0 +OP4 E0359D 0 +OP4 E0359E 0 +OP4 E0359F 0 +OP4 E035A0 0 +OP4 E035A1 0 +OP4 E035A2 0 +OP4 E035A3 0 +OP4 E035A4 0 +OP4 E035A5 0 +OP4 E035A6 0 +OP4 E035A7 0 +OP4 E035A8 0 +OP4 E035A9 0 +OP4 E035AA 0 +OP4 E035AB 0 +OP4 E035AC 0 +OP4 E035AD 0 +OP4 E035AE 0 +OP4 E035AF 0 +OP4 E035B0 0 +OP4 E035B1 0 +OP4 E035B2 0 +OP4 E035B3 0 +OP4 E035B4 0 +OP4 E035B5 0 +OP4 E035B6 0 +OP4 E035B7 0 +OP4 E035B8 0 +OP4 E035B9 0 +OP4 E035BA 0 +OP4 E035BB 0 +OP4 E035BC 0 +OP4 E035BD 0 +OP4 E035BE 0 +OP4 E035BF 0 +OP4 E035C0 0 +OP4 E035C1 0 +OP4 E035C2 0 +OP4 E035C3 0 +OP4 E035C4 0 +OP4 E035C5 0 +OP4 E035C6 0 +OP4 E035C7 0 +OP4 E035C8 0 +OP4 E035C9 0 +OP4 E035CA 0 +OP4 E035CB 0 +OP4 E035CC 0 +OP4 E035CD 0 +OP4 E035CE 0 +OP4 E035CF 0 +OP4 E035D0 0 +OP4 E035D1 0 +OP4 E035D2 0 +OP4 E035D3 0 +OP4 E035D4 0 +OP4 E035D5 0 +OP4 E035D6 0 +OP4 E035D7 0 +OP4 E035D8 0 +OP4 E035D9 0 +OP4 E035DA 0 +OP4 E035DB 0 +OP4 E035DC 0 +OP4 E035DD 0 +OP4 E035DE 0 +OP4 E035DF 0 +OP4 E035E0 0 +OP4 E035E1 0 +OP4 E035E2 0 +OP4 E035E3 0 +OP4 E035E4 0 +OP4 E035E5 0 +OP4 E035E6 0 +OP4 E035E7 0 +OP4 E035E8 0 +OP4 E035E9 0 +OP4 E035EA 0 +OP4 E035EB 0 +OP4 E035EC 0 +OP4 E035ED 0 +OP4 E035EE 0 +OP4 E035EF 0 +OP4 E035F0 0 +OP4 E035F1 0 +OP4 E035F2 0 +OP4 E035F3 0 +OP4 E035F4 0 +OP4 E035F5 0 +OP4 E035F6 0 +OP4 E035F7 0 +OP4 E035F8 0 +OP4 E035F9 0 +OP4 E035FA 0 +OP4 E035FB 0 +OP4 E035FC 0 +OP4 E035FD 0 +OP4 E035FE 0 +OP4 E035FF 0 +OP4 E03600 0 +OP4 E03601 0 +OP4 E03602 0 +OP4 E03603 0 +OP4 E03604 0 +OP4 E03605 0 +OP4 E03606 0 +OP4 E03607 0 +OP4 E03608 0 +OP4 E03609 0 +OP4 E0360A 0 +OP4 E0360B 0 +OP4 E0360C 0 +OP4 E0360D 0 +OP4 E0360E 0 +OP4 E0360F 0 +OP4 E03610 0 +OP4 E03611 0 +OP4 E03612 0 +OP4 E03613 0 +OP4 E03614 0 +OP4 E03615 0 +OP4 E03616 0 +OP4 E03617 0 +OP4 E03618 0 +OP4 E03619 0 +OP4 E0361A 0 +OP4 E0361B 0 +OP4 E0361C 0 +OP4 E0361D 0 +OP4 E0361E 0 +OP4 E0361F 0 +OP4 E03620 0 +OP4 E03621 0 +OP4 E03622 0 +OP4 E03623 0 +OP4 E03624 0 +OP4 E03625 0 +OP4 E03626 0 +OP4 E03627 0 +OP4 E03628 0 +OP4 E03629 0 +OP4 E0362A 0 +OP4 E0362B 0 +OP4 E0362C 0 +OP4 E0362D 0 +OP4 E0362E 0 +OP4 E0362F 0 +OP4 E03630 0 +OP4 E03631 0 +OP4 E03632 0 +OP4 E03633 0 +OP4 E03634 0 +OP4 E03635 0 +OP4 E03636 0 +OP4 E03637 0 +OP4 E03638 0 +OP4 E03639 0 +OP4 E0363A 0 +OP4 E0363B 0 +OP4 E0363C 0 +OP4 E0363D 0 +OP4 E0363E 0 +OP4 E0363F 0 +OP4 E03640 0 +OP4 E03641 0 +OP4 E03642 0 +OP4 E03643 0 +OP4 E03644 0 +OP4 E03645 0 +OP4 E03646 0 +OP4 E03647 0 +OP4 E03648 0 +OP4 E03649 0 +OP4 E0364A 0 +OP4 E0364B 0 +OP4 E0364C 0 +OP4 E0364D 0 +OP4 E0364E 0 +OP4 E0364F 0 +OP4 E03650 0 +OP4 E03651 0 +OP4 E03652 0 +OP4 E03653 0 +OP4 E03654 0 +OP4 E03655 0 +OP4 E03656 0 +OP4 E03657 0 +OP4 E03658 0 +OP4 E03659 0 +OP4 E0365A 0 +OP4 E0365B 0 +OP4 E0365C 0 +OP4 E0365D 0 +OP4 E0365E 0 +OP4 E0365F 0 +OP4 E03660 0 +OP4 E03661 0 +OP4 E03662 0 +OP4 E03663 0 +OP4 E03664 0 +OP4 E03665 0 +OP4 E03666 0 +OP4 E03667 0 +OP4 E03668 0 +OP4 E03669 0 +OP4 E0366A 0 +OP4 E0366B 0 +OP4 E0366C 0 +OP4 E0366D 0 +OP4 E0366E 0 +OP4 E0366F 0 +OP4 E03670 0 +OP4 E03671 0 +OP4 E03672 0 +OP4 E03673 0 +OP4 E03674 0 +OP4 E03675 0 +OP4 E03676 0 +OP4 E03677 0 +OP4 E03678 0 +OP4 E03679 0 +OP4 E0367A 0 +OP4 E0367B 0 +OP4 E0367C 0 +OP4 E0367D 0 +OP4 E0367E 0 +OP4 E0367F 0 +OP4 E03680 0 +OP4 E03681 0 +OP4 E03682 0 +OP4 E03683 0 +OP4 E03684 0 +OP4 E03685 0 +OP4 E03686 0 +OP4 E03687 0 +OP4 E03688 0 +OP4 E03689 0 +OP4 E0368A 0 +OP4 E0368B 0 +OP4 E0368C 0 +OP4 E0368D 0 +OP4 E0368E 0 +OP4 E0368F 0 +OP4 E03690 0 +OP4 E03691 0 +OP4 E03692 0 +OP4 E03693 0 +OP4 E03694 0 +OP4 E03695 0 +OP4 E03696 0 +OP4 E03697 0 +OP4 E03698 0 +OP4 E03699 0 +OP4 E0369A 0 +OP4 E0369B 0 +OP4 E0369C 0 +OP4 E0369D 0 +OP4 E0369E 0 +OP4 E0369F 0 +OP4 E036A0 0 +OP4 E036A1 0 +OP4 E036A2 0 +OP4 E036A3 0 +OP4 E036A4 0 +OP4 E036A5 0 +OP4 E036A6 0 +OP4 E036A7 0 +OP4 E036A8 0 +OP4 E036A9 0 +OP4 E036AA 0 +OP4 E036AB 0 +OP4 E036AC 0 +OP4 E036AD 0 +OP4 E036AE 0 +OP4 E036AF 0 +OP4 E036B0 0 +OP4 E036B1 0 +OP4 E036B2 0 +OP4 E036B3 0 +OP4 E036B4 0 +OP4 E036B5 0 +OP4 E036B6 0 +OP4 E036B7 0 +OP4 E036B8 0 +OP4 E036B9 0 +OP4 E036BA 0 +OP4 E036BB 0 +OP4 E036BC 0 +OP4 E036BD 0 +OP4 E036BE 0 +OP4 E036BF 0 +OP4 E036C0 0 +OP4 E036C1 0 +OP4 E036C2 0 +OP4 E036C3 0 +OP4 E036C4 0 +OP4 E036C5 0 +OP4 E036C6 0 +OP4 E036C7 0 +OP4 E036C8 0 +OP4 E036C9 0 +OP4 E036CA 0 +OP4 E036CB 0 +OP4 E036CC 0 +OP4 E036CD 0 +OP4 E036CE 0 +OP4 E036CF 0 +OP4 E036D0 0 +OP4 E036D1 0 +OP4 E036D2 0 +OP4 E036D3 0 +OP4 E036D4 0 +OP4 E036D5 0 +OP4 E036D6 0 +OP4 E036D7 0 +OP4 E036D8 0 +OP4 E036D9 0 +OP4 E036DA 0 +OP4 E036DB 0 +OP4 E036DC 0 +OP4 E036DD 0 +OP4 E036DE 0 +OP4 E036DF 0 +OP4 E036E0 0 +OP4 E036E1 0 +OP4 E036E2 0 +OP4 E036E3 0 +OP4 E036E4 0 +OP4 E036E5 0 +OP4 E036E6 0 +OP4 E036E7 0 +OP4 E036E8 0 +OP4 E036E9 0 +OP4 E036EA 0 +OP4 E036EB 0 +OP4 E036EC 0 +OP4 E036ED 0 +OP4 E036EE 0 +OP4 E036EF 0 +OP4 E036F0 0 +OP4 E036F1 0 +OP4 E036F2 0 +OP4 E036F3 0 +OP4 E036F4 0 +OP4 E036F5 0 +OP4 E036F6 0 +OP4 E036F7 0 +OP4 E036F8 0 +OP4 E036F9 0 +OP4 E036FA 0 +OP4 E036FB 0 +OP4 E036FC 0 +OP4 E036FD 0 +OP4 E036FE 0 +OP4 E036FF 0 +OP4 E03700 0 +OP4 E03701 0 +OP4 E03702 0 +OP4 E03703 0 +OP4 E03704 0 +OP4 E03705 0 +OP4 E03706 0 +OP4 E03707 0 +OP4 E03708 0 +OP4 E03709 0 +OP4 E0370A 0 +OP4 E0370B 0 +OP4 E0370C 0 +OP4 E0370D 0 +OP4 E0370E 0 +OP4 E0370F 0 +OP4 E03710 0 +OP4 E03711 0 +OP4 E03712 0 +OP4 E03713 0 +OP4 E03714 0 +OP4 E03715 0 +OP4 E03716 0 +OP4 E03717 0 +OP4 E03718 0 +OP4 E03719 0 +OP4 E0371A 0 +OP4 E0371B 0 +OP4 E0371C 0 +OP4 E0371D 0 +OP4 E0371E 0 +OP4 E0371F 0 +OP4 E03720 0 +OP4 E03721 0 +OP4 E03722 0 +OP4 E03723 0 +OP4 E03724 0 +OP4 E03725 0 +OP4 E03726 0 +OP4 E03727 0 +OP4 E03728 0 +OP4 E03729 0 +OP4 E0372A 0 +OP4 E0372B 0 +OP4 E0372C 0 +OP4 E0372D 0 +OP4 E0372E 0 +OP4 E0372F 0 +OP4 E03730 0 +OP4 E03731 0 +OP4 E03732 0 +OP4 E03733 0 +OP4 E03734 0 +OP4 E03735 0 +OP4 E03736 0 +OP4 E03737 0 +OP4 E03738 0 +OP4 E03739 0 +OP4 E0373A 0 +OP4 E0373B 0 +OP4 E0373C 0 +OP4 E0373D 0 +OP4 E0373E 0 +OP4 E0373F 0 +OP4 E03740 0 +OP4 E03741 0 +OP4 E03742 0 +OP4 E03743 0 +OP4 E03744 0 +OP4 E03745 0 +OP4 E03746 0 +OP4 E03747 0 +OP4 E03748 0 +OP4 E03749 0 +OP4 E0374A 0 +OP4 E0374B 0 +OP4 E0374C 0 +OP4 E0374D 0 +OP4 E0374E 0 +OP4 E0374F 0 +OP4 E03750 0 +OP4 E03751 0 +OP4 E03752 0 +OP4 E03753 0 +OP4 E03754 0 +OP4 E03755 0 +OP4 E03756 0 +OP4 E03757 0 +OP4 E03758 0 +OP4 E03759 0 +OP4 E0375A 0 +OP4 E0375B 0 +OP4 E0375C 0 +OP4 E0375D 0 +OP4 E0375E 0 +OP4 E0375F 0 +OP4 E03760 0 +OP4 E03761 0 +OP4 E03762 0 +OP4 E03763 0 +OP4 E03764 0 +OP4 E03765 0 +OP4 E03766 0 +OP4 E03767 0 +OP4 E03768 0 +OP4 E03769 0 +OP4 E0376A 0 +OP4 E0376B 0 +OP4 E0376C 0 +OP4 E0376D 0 +OP4 E0376E 0 +OP4 E0376F 0 +OP4 E03770 0 +OP4 E03771 0 +OP4 E03772 0 +OP4 E03773 0 +OP4 E03774 0 +OP4 E03775 0 +OP4 E03776 0 +OP4 E03777 0 +OP4 E03778 0 +OP4 E03779 0 +OP4 E0377A 0 +OP4 E0377B 0 +OP4 E0377C 0 +OP4 E0377D 0 +OP4 E0377E 0 +OP4 E0377F 0 +OP4 E03780 0 +OP4 E03781 0 +OP4 E03782 0 +OP4 E03783 0 +OP4 E03784 0 +OP4 E03785 0 +OP4 E03786 0 +OP4 E03787 0 +OP4 E03788 0 +OP4 E03789 0 +OP4 E0378A 0 +OP4 E0378B 0 +OP4 E0378C 0 +OP4 E0378D 0 +OP4 E0378E 0 +OP4 E0378F 0 +OP4 E03790 0 +OP4 E03791 0 +OP4 E03792 0 +OP4 E03793 0 +OP4 E03794 0 +OP4 E03795 0 +OP4 E03796 0 +OP4 E03797 0 +OP4 E03798 0 +OP4 E03799 0 +OP4 E0379A 0 +OP4 E0379B 0 +OP4 E0379C 0 +OP4 E0379D 0 +OP4 E0379E 0 +OP4 E0379F 0 +OP4 E037A0 0 +OP4 E037A1 0 +OP4 E037A2 0 +OP4 E037A3 0 +OP4 E037A4 0 +OP4 E037A5 0 +OP4 E037A6 0 +OP4 E037A7 0 +OP4 E037A8 0 +OP4 E037A9 0 +OP4 E037AA 0 +OP4 E037AB 0 +OP4 E037AC 0 +OP4 E037AD 0 +OP4 E037AE 0 +OP4 E037AF 0 +OP4 E037B0 0 +OP4 E037B1 0 +OP4 E037B2 0 +OP4 E037B3 0 +OP4 E037B4 0 +OP4 E037B5 0 +OP4 E037B6 0 +OP4 E037B7 0 +OP4 E037B8 0 +OP4 E037B9 0 +OP4 E037BA 0 +OP4 E037BB 0 +OP4 E037BC 0 +OP4 E037BD 0 +OP4 E037BE 0 +OP4 E037BF 0 +OP4 E037C0 0 +OP4 E037C1 0 +OP4 E037C2 0 +OP4 E037C3 0 +OP4 E037C4 0 +OP4 E037C5 0 +OP4 E037C6 0 +OP4 E037C7 0 +OP4 E037C8 0 +OP4 E037C9 0 +OP4 E037CA 0 +OP4 E037CB 0 +OP4 E037CC 0 +OP4 E037CD 0 +OP4 E037CE 0 +OP4 E037CF 0 +OP4 E037D0 0 +OP4 E037D1 0 +OP4 E037D2 0 +OP4 E037D3 0 +OP4 E037D4 0 +OP4 E037D5 0 +OP4 E037D6 0 +OP4 E037D7 0 +OP4 E037D8 0 +OP4 E037D9 0 +OP4 E037DA 0 +OP4 E037DB 0 +OP4 E037DC 0 +OP4 E037DD 0 +OP4 E037DE 0 +OP4 E037DF 0 +OP4 E037E0 0 +OP4 E037E1 0 +OP4 E037E2 0 +OP4 E037E3 0 +OP4 E037E4 0 +OP4 E037E5 0 +OP4 E037E6 0 +OP4 E037E7 0 +OP4 E037E8 0 +OP4 E037E9 0 +OP4 E037EA 0 +OP4 E037EB 0 +OP4 E037EC 0 +OP4 E037ED 0 +OP4 E037EE 0 +OP4 E037EF 0 +OP4 E037F0 0 +OP4 E037F1 0 +OP4 E037F2 0 +OP4 E037F3 0 +OP4 E037F4 0 +OP4 E037F5 0 +OP4 E037F6 0 +OP4 E037F7 0 +OP4 E037F8 0 +OP4 E037F9 0 +OP4 E037FA 0 +OP4 E037FB 0 +OP4 E037FC 0 +OP4 E037FD 0 +OP4 E037FE 0 +OP4 E037FF 0 +OP4 E03800 0 +OP4 E03801 0 +OP4 E03802 0 +OP4 E03803 0 +OP4 E03804 0 +OP4 E03805 0 +OP4 E03806 0 +OP4 E03807 0 +OP4 E03808 0 +OP4 E03809 0 +OP4 E0380A 0 +OP4 E0380B 0 +OP4 E0380C 0 +OP4 E0380D 0 +OP4 E0380E 0 +OP4 E0380F 0 +OP4 E03810 0 +OP4 E03811 0 +OP4 E03812 0 +OP4 E03813 0 +OP4 E03814 0 +OP4 E03815 0 +OP4 E03816 0 +OP4 E03817 0 +OP4 E03818 0 +OP4 E03819 0 +OP4 E0381A 0 +OP4 E0381B 0 +OP4 E0381C 0 +OP4 E0381D 0 +OP4 E0381E 0 +OP4 E0381F 0 +OP4 E03820 0 +OP4 E03821 0 +OP4 E03822 0 +OP4 E03823 0 +OP4 E03824 0 +OP4 E03825 0 +OP4 E03826 0 +OP4 E03827 0 +OP4 E03828 0 +OP4 E03829 0 +OP4 E0382A 0 +OP4 E0382B 0 +OP4 E0382C 0 +OP4 E0382D 0 +OP4 E0382E 0 +OP4 E0382F 0 +OP4 E03830 0 +OP4 E03831 0 +OP4 E03832 0 +OP4 E03833 0 +OP4 E03834 0 +OP4 E03835 0 +OP4 E03836 0 +OP4 E03837 0 +OP4 E03838 0 +OP4 E03839 0 +OP4 E0383A 0 +OP4 E0383B 0 +OP4 E0383C 0 +OP4 E0383D 0 +OP4 E0383E 0 +OP4 E0383F 0 +OP4 E03840 0 +OP4 E03841 0 +OP4 E03842 0 +OP4 E03843 0 +OP4 E03844 0 +OP4 E03845 0 +OP4 E03846 0 +OP4 E03847 0 +OP4 E03848 0 +OP4 E03849 0 +OP4 E0384A 0 +OP4 E0384B 0 +OP4 E0384C 0 +OP4 E0384D 0 +OP4 E0384E 0 +OP4 E0384F 0 +OP4 E03850 0 +OP4 E03851 0 +OP4 E03852 0 +OP4 E03853 0 +OP4 E03854 0 +OP4 E03855 0 +OP4 E03856 0 +OP4 E03857 0 +OP4 E03858 0 +OP4 E03859 0 +OP4 E0385A 0 +OP4 E0385B 0 +OP4 E0385C 0 +OP4 E0385D 0 +OP4 E0385E 0 +OP4 E0385F 0 +OP4 E03860 0 +OP4 E03861 0 +OP4 E03862 0 +OP4 E03863 0 +OP4 E03864 0 +OP4 E03865 0 +OP4 E03866 0 +OP4 E03867 0 +OP4 E03868 0 +OP4 E03869 0 +OP4 E0386A 0 +OP4 E0386B 0 +OP4 E0386C 0 +OP4 E0386D 0 +OP4 E0386E 0 +OP4 E0386F 0 +OP4 E03870 0 +OP4 E03871 0 +OP4 E03872 0 +OP4 E03873 0 +OP4 E03874 0 +OP4 E03875 0 +OP4 E03876 0 +OP4 E03877 0 +OP4 E03878 0 +OP4 E03879 0 +OP4 E0387A 0 +OP4 E0387B 0 +OP4 E0387C 0 +OP4 E0387D 0 +OP4 E0387E 0 +OP4 E0387F 0 +OP4 E03880 0 +OP4 E03881 0 +OP4 E03882 0 +OP4 E03883 0 +OP4 E03884 0 +OP4 E03885 0 +OP4 E03886 0 +OP4 E03887 0 +OP4 E03888 0 +OP4 E03889 0 +OP4 E0388A 0 +OP4 E0388B 0 +OP4 E0388C 0 +OP4 E0388D 0 +OP4 E0388E 0 +OP4 E0388F 0 +OP4 E03890 0 +OP4 E03891 0 +OP4 E03892 0 +OP4 E03893 0 +OP4 E03894 0 +OP4 E03895 0 +OP4 E03896 0 +OP4 E03897 0 +OP4 E03898 0 +OP4 E03899 0 +OP4 E0389A 0 +OP4 E0389B 0 +OP4 E0389C 0 +OP4 E0389D 0 +OP4 E0389E 0 +OP4 E0389F 0 +OP4 E038A0 0 +OP4 E038A1 0 +OP4 E038A2 0 +OP4 E038A3 0 +OP4 E038A4 0 +OP4 E038A5 0 +OP4 E038A6 0 +OP4 E038A7 0 +OP4 E038A8 0 +OP4 E038A9 0 +OP4 E038AA 0 +OP4 E038AB 0 +OP4 E038AC 0 +OP4 E038AD 0 +OP4 E038AE 0 +OP4 E038AF 0 +OP4 E038B0 0 +OP4 E038B1 0 +OP4 E038B2 0 +OP4 E038B3 0 +OP4 E038B4 0 +OP4 E038B5 0 +OP4 E038B6 0 +OP4 E038B7 0 +OP4 E038B8 0 +OP4 E038B9 0 +OP4 E038BA 0 +OP4 E038BB 0 +OP4 E038BC 0 +OP4 E038BD 0 +OP4 E038BE 0 +OP4 E038BF 0 +OP4 E038C0 0 +OP4 E038C1 0 +OP4 E038C2 0 +OP4 E038C3 0 +OP4 E038C4 0 +OP4 E038C5 0 +OP4 E038C6 0 +OP4 E038C7 0 +OP4 E038C8 0 +OP4 E038C9 0 +OP4 E038CA 0 +OP4 E038CB 0 +OP4 E038CC 0 +OP4 E038CD 0 +OP4 E038CE 0 +OP4 E038CF 0 +OP4 E038D0 0 +OP4 E038D1 0 +OP4 E038D2 0 +OP4 E038D3 0 +OP4 E038D4 0 +OP4 E038D5 0 +OP4 E038D6 0 +OP4 E038D7 0 +OP4 E038D8 0 +OP4 E038D9 0 +OP4 E038DA 0 +OP4 E038DB 0 +OP4 E038DC 0 +OP4 E038DD 0 +OP4 E038DE 0 +OP4 E038DF 0 +OP4 E038E0 0 +OP4 E038E1 0 +OP4 E038E2 0 +OP4 E038E3 0 +OP4 E038E4 0 +OP4 E038E5 0 +OP4 E038E6 0 +OP4 E038E7 0 +OP4 E038E8 0 +OP4 E038E9 0 +OP4 E038EA 0 +OP4 E038EB 0 +OP4 E038EC 0 +OP4 E038ED 0 +OP4 E038EE 0 +OP4 E038EF 0 +OP4 E038F0 0 +OP4 E038F1 0 +OP4 E038F2 0 +OP4 E038F3 0 +OP4 E038F4 0 +OP4 E038F5 0 +OP4 E038F6 0 +OP4 E038F7 0 +OP4 E038F8 0 +OP4 E038F9 0 +OP4 E038FA 0 +OP4 E038FB 0 +OP4 E038FC 0 +OP4 E038FD 0 +OP4 E038FE 0 +OP4 E038FF 0 +OP4 E03900 0 +OP4 E03901 0 +OP4 E03902 0 +OP4 E03903 0 +OP4 E03904 0 +OP4 E03905 0 +OP4 E03906 0 +OP4 E03907 0 +OP4 E03908 0 +OP4 E03909 0 +OP4 E0390A 0 +OP4 E0390B 0 +OP4 E0390C 0 +OP4 E0390D 0 +OP4 E0390E 0 +OP4 E0390F 0 +OP4 E03910 0 +OP4 E03911 0 +OP4 E03912 0 +OP4 E03913 0 +OP4 E03914 0 +OP4 E03915 0 +OP4 E03916 0 +OP4 E03917 0 +OP4 E03918 0 +OP4 E03919 0 +OP4 E0391A 0 +OP4 E0391B 0 +OP4 E0391C 0 +OP4 E0391D 0 +OP4 E0391E 0 +OP4 E0391F 0 +OP4 E03920 0 +OP4 E03921 0 +OP4 E03922 0 +OP4 E03923 0 +OP4 E03924 0 +OP4 E03925 0 +OP4 E03926 0 +OP4 E03927 0 +OP4 E03928 0 +OP4 E03929 0 +OP4 E0392A 0 +OP4 E0392B 0 +OP4 E0392C 0 +OP4 E0392D 0 +OP4 E0392E 0 +OP4 E0392F 0 +OP4 E03930 0 +OP4 E03931 0 +OP4 E03932 0 +OP4 E03933 0 +OP4 E03934 0 +OP4 E03935 0 +OP4 E03936 0 +OP4 E03937 0 +OP4 E03938 0 +OP4 E03939 0 +OP4 E0393A 0 +OP4 E0393B 0 +OP4 E0393C 0 +OP4 E0393D 0 +OP4 E0393E 0 +OP4 E0393F 0 +OP4 E03940 0 +OP4 E03941 0 +OP4 E03942 0 +OP4 E03943 0 +OP4 E03944 0 +OP4 E03945 0 +OP4 E03946 0 +OP4 E03947 0 +OP4 E03948 0 +OP4 E03949 0 +OP4 E0394A 0 +OP4 E0394B 0 +OP4 E0394C 0 +OP4 E0394D 0 +OP4 E0394E 0 +OP4 E0394F 0 +OP4 E03950 0 +OP4 E03951 0 +OP4 E03952 0 +OP4 E03953 0 +OP4 E03954 0 +OP4 E03955 0 +OP4 E03956 0 +OP4 E03957 0 +OP4 E03958 0 +OP4 E03959 0 +OP4 E0395A 0 +OP4 E0395B 0 +OP4 E0395C 0 +OP4 E0395D 0 +OP4 E0395E 0 +OP4 E0395F 0 +OP4 E03960 0 +OP4 E03961 0 +OP4 E03962 0 +OP4 E03963 0 +OP4 E03964 0 +OP4 E03965 0 +OP4 E03966 0 +OP4 E03967 0 +OP4 E03968 0 +OP4 E03969 0 +OP4 E0396A 0 +OP4 E0396B 0 +OP4 E0396C 0 +OP4 E0396D 0 +OP4 E0396E 0 +OP4 E0396F 0 +OP4 E03970 0 +OP4 E03971 0 +OP4 E03972 0 +OP4 E03973 0 +OP4 E03974 0 +OP4 E03975 0 +OP4 E03976 0 +OP4 E03977 0 +OP4 E03978 0 +OP4 E03979 0 +OP4 E0397A 0 +OP4 E0397B 0 +OP4 E0397C 0 +OP4 E0397D 0 +OP4 E0397E 0 +OP4 E0397F 0 +OP4 E03980 0 +OP4 E03981 0 +OP4 E03982 0 +OP4 E03983 0 +OP4 E03984 0 +OP4 E03985 0 +OP4 E03986 0 +OP4 E03987 0 +OP4 E03988 0 +OP4 E03989 0 +OP4 E0398A 0 +OP4 E0398B 0 +OP4 E0398C 0 +OP4 E0398D 0 +OP4 E0398E 0 +OP4 E0398F 0 +OP4 E03990 0 +OP4 E03991 0 +OP4 E03992 0 +OP4 E03993 0 +OP4 E03994 0 +OP4 E03995 0 +OP4 E03996 0 +OP4 E03997 0 +OP4 E03998 0 +OP4 E03999 0 +OP4 E0399A 0 +OP4 E0399B 0 +OP4 E0399C 0 +OP4 E0399D 0 +OP4 E0399E 0 +OP4 E0399F 0 +OP4 E039A0 0 +OP4 E039A1 0 +OP4 E039A2 0 +OP4 E039A3 0 +OP4 E039A4 0 +OP4 E039A5 0 +OP4 E039A6 0 +OP4 E039A7 0 +OP4 E039A8 0 +OP4 E039A9 0 +OP4 E039AA 0 +OP4 E039AB 0 +OP4 E039AC 0 +OP4 E039AD 0 +OP4 E039AE 0 +OP4 E039AF 0 +OP4 E039B0 0 +OP4 E039B1 0 +OP4 E039B2 0 +OP4 E039B3 0 +OP4 E039B4 0 +OP4 E039B5 0 +OP4 E039B6 0 +OP4 E039B7 0 +OP4 E039B8 0 +OP4 E039B9 0 +OP4 E039BA 0 +OP4 E039BB 0 +OP4 E039BC 0 +OP4 E039BD 0 +OP4 E039BE 0 +OP4 E039BF 0 +OP4 E039C0 0 +OP4 E039C1 0 +OP4 E039C2 0 +OP4 E039C3 0 +OP4 E039C4 0 +OP4 E039C5 0 +OP4 E039C6 0 +OP4 E039C7 0 +OP4 E039C8 0 +OP4 E039C9 0 +OP4 E039CA 0 +OP4 E039CB 0 +OP4 E039CC 0 +OP4 E039CD 0 +OP4 E039CE 0 +OP4 E039CF 0 +OP4 E039D0 0 +OP4 E039D1 0 +OP4 E039D2 0 +OP4 E039D3 0 +OP4 E039D4 0 +OP4 E039D5 0 +OP4 E039D6 0 +OP4 E039D7 0 +OP4 E039D8 0 +OP4 E039D9 0 +OP4 E039DA 0 +OP4 E039DB 0 +OP4 E039DC 0 +OP4 E039DD 0 +OP4 E039DE 0 +OP4 E039DF 0 +OP4 E039E0 0 +OP4 E039E1 0 +OP4 E039E2 0 +OP4 E039E3 0 +OP4 E039E4 0 +OP4 E039E5 0 +OP4 E039E6 0 +OP4 E039E7 0 +OP4 E039E8 0 +OP4 E039E9 0 +OP4 E039EA 0 +OP4 E039EB 0 +OP4 E039EC 0 +OP4 E039ED 0 +OP4 E039EE 0 +OP4 E039EF 0 +OP4 E039F0 0 +OP4 E039F1 0 +OP4 E039F2 0 +OP4 E039F3 0 +OP4 E039F4 0 +OP4 E039F5 0 +OP4 E039F6 0 +OP4 E039F7 0 +OP4 E039F8 0 +OP4 E039F9 0 +OP4 E039FA 0 +OP4 E039FB 0 +OP4 E039FC 0 +OP4 E039FD 0 +OP4 E039FE 0 +OP4 E039FF 0 +OP4 E03A00 0 +OP4 E03A01 0 +OP4 E03A02 0 +OP4 E03A03 0 +OP4 E03A04 0 +OP4 E03A05 0 +OP4 E03A06 0 +OP4 E03A07 0 +OP4 E03A08 0 +OP4 E03A09 0 +OP4 E03A0A 0 +OP4 E03A0B 0 +OP4 E03A0C 0 +OP4 E03A0D 0 +OP4 E03A0E 0 +OP4 E03A0F 0 +OP4 E03A10 0 +OP4 E03A11 0 +OP4 E03A12 0 +OP4 E03A13 0 +OP4 E03A14 0 +OP4 E03A15 0 +OP4 E03A16 0 +OP4 E03A17 0 +OP4 E03A18 0 +OP4 E03A19 0 +OP4 E03A1A 0 +OP4 E03A1B 0 +OP4 E03A1C 0 +OP4 E03A1D 0 +OP4 E03A1E 0 +OP4 E03A1F 0 +OP4 E03A20 0 +OP4 E03A21 0 +OP4 E03A22 0 +OP4 E03A23 0 +OP4 E03A24 0 +OP4 E03A25 0 +OP4 E03A26 0 +OP4 E03A27 0 +OP4 E03A28 0 +OP4 E03A29 0 +OP4 E03A2A 0 +OP4 E03A2B 0 +OP4 E03A2C 0 +OP4 E03A2D 0 +OP4 E03A2E 0 +OP4 E03A2F 0 +OP4 E03A30 0 +OP4 E03A31 0 +OP4 E03A32 0 +OP4 E03A33 0 +OP4 E03A34 0 +OP4 E03A35 0 +OP4 E03A36 0 +OP4 E03A37 0 +OP4 E03A38 0 +OP4 E03A39 0 +OP4 E03A3A 0 +OP4 E03A3B 0 +OP4 E03A3C 0 +OP4 E03A3D 0 +OP4 E03A3E 0 +OP4 E03A3F 0 +OP4 E03A40 0 +OP4 E03A41 0 +OP4 E03A42 0 +OP4 E03A43 0 +OP4 E03A44 0 +OP4 E03A45 0 +OP4 E03A46 0 +OP4 E03A47 0 +OP4 E03A48 0 +OP4 E03A49 0 +OP4 E03A4A 0 +OP4 E03A4B 0 +OP4 E03A4C 0 +OP4 E03A4D 0 +OP4 E03A4E 0 +OP4 E03A4F 0 +OP4 E03A50 0 +OP4 E03A51 0 +OP4 E03A52 0 +OP4 E03A53 0 +OP4 E03A54 0 +OP4 E03A55 0 +OP4 E03A56 0 +OP4 E03A57 0 +OP4 E03A58 0 +OP4 E03A59 0 +OP4 E03A5A 0 +OP4 E03A5B 0 +OP4 E03A5C 0 +OP4 E03A5D 0 +OP4 E03A5E 0 +OP4 E03A5F 0 +OP4 E03A60 0 +OP4 E03A61 0 +OP4 E03A62 0 +OP4 E03A63 0 +OP4 E03A64 0 +OP4 E03A65 0 +OP4 E03A66 0 +OP4 E03A67 0 +OP4 E03A68 0 +OP4 E03A69 0 +OP4 E03A6A 0 +OP4 E03A6B 0 +OP4 E03A6C 0 +OP4 E03A6D 0 +OP4 E03A6E 0 +OP4 E03A6F 0 +OP4 E03A70 0 +OP4 E03A71 0 +OP4 E03A72 0 +OP4 E03A73 0 +OP4 E03A74 0 +OP4 E03A75 0 +OP4 E03A76 0 +OP4 E03A77 0 +OP4 E03A78 0 +OP4 E03A79 0 +OP4 E03A7A 0 +OP4 E03A7B 0 +OP4 E03A7C 0 +OP4 E03A7D 0 +OP4 E03A7E 0 +OP4 E03A7F 0 +OP4 E03A80 0 +OP4 E03A81 0 +OP4 E03A82 0 +OP4 E03A83 0 +OP4 E03A84 0 +OP4 E03A85 0 +OP4 E03A86 0 +OP4 E03A87 0 +OP4 E03A88 0 +OP4 E03A89 0 +OP4 E03A8A 0 +OP4 E03A8B 0 +OP4 E03A8C 0 +OP4 E03A8D 0 +OP4 E03A8E 0 +OP4 E03A8F 0 +OP4 E03A90 0 +OP4 E03A91 0 +OP4 E03A92 0 +OP4 E03A93 0 +OP4 E03A94 0 +OP4 E03A95 0 +OP4 E03A96 0 +OP4 E03A97 0 +OP4 E03A98 0 +OP4 E03A99 0 +OP4 E03A9A 0 +OP4 E03A9B 0 +OP4 E03A9C 0 +OP4 E03A9D 0 +OP4 E03A9E 0 +OP4 E03A9F 0 +OP4 E03AA0 0 +OP4 E03AA1 0 +OP4 E03AA2 0 +OP4 E03AA3 0 +OP4 E03AA4 0 +OP4 E03AA5 0 +OP4 E03AA6 0 +OP4 E03AA7 0 +OP4 E03AA8 0 +OP4 E03AA9 0 +OP4 E03AAA 0 +OP4 E03AAB 0 +OP4 E03AAC 0 +OP4 E03AAD 0 +OP4 E03AAE 0 +OP4 E03AAF 0 +OP4 E03AB0 0 +OP4 E03AB1 0 +OP4 E03AB2 0 +OP4 E03AB3 0 +OP4 E03AB4 0 +OP4 E03AB5 0 +OP4 E03AB6 0 +OP4 E03AB7 0 +OP4 E03AB8 0 +OP4 E03AB9 0 +OP4 E03ABA 0 +OP4 E03ABB 0 +OP4 E03ABC 0 +OP4 E03ABD 0 +OP4 E03ABE 0 +OP4 E03ABF 0 +OP4 E03AC0 0 +OP4 E03AC1 0 +OP4 E03AC2 0 +OP4 E03AC3 0 +OP4 E03AC4 0 +OP4 E03AC5 0 +OP4 E03AC6 0 +OP4 E03AC7 0 +OP4 E03AC8 0 +OP4 E03AC9 0 +OP4 E03ACA 0 +OP4 E03ACB 0 +OP4 E03ACC 0 +OP4 E03ACD 0 +OP4 E03ACE 0 +OP4 E03ACF 0 +OP4 E03AD0 0 +OP4 E03AD1 0 +OP4 E03AD2 0 +OP4 E03AD3 0 +OP4 E03AD4 0 +OP4 E03AD5 0 +OP4 E03AD6 0 +OP4 E03AD7 0 +OP4 E03AD8 0 +OP4 E03AD9 0 +OP4 E03ADA 0 +OP4 E03ADB 0 +OP4 E03ADC 0 +OP4 E03ADD 0 +OP4 E03ADE 0 +OP4 E03ADF 0 +OP4 E03AE0 0 +OP4 E03AE1 0 +OP4 E03AE2 0 +OP4 E03AE3 0 +OP4 E03AE4 0 +OP4 E03AE5 0 +OP4 E03AE6 0 +OP4 E03AE7 0 +OP4 E03AE8 0 +OP4 E03AE9 0 +OP4 E03AEA 0 +OP4 E03AEB 0 +OP4 E03AEC 0 +OP4 E03AED 0 +OP4 E03AEE 0 +OP4 E03AEF 0 +OP4 E03AF0 0 +OP4 E03AF1 0 +OP4 E03AF2 0 +OP4 E03AF3 0 +OP4 E03AF4 0 +OP4 E03AF5 0 +OP4 E03AF6 0 +OP4 E03AF7 0 +OP4 E03AF8 0 +OP4 E03AF9 0 +OP4 E03AFA 0 +OP4 E03AFB 0 +OP4 E03AFC 0 +OP4 E03AFD 0 +OP4 E03AFE 0 +OP4 E03AFF 0 +OP4 E03B00 0 +OP4 E03B01 0 +OP4 E03B02 0 +OP4 E03B03 0 +OP4 E03B04 0 +OP4 E03B05 0 +OP4 E03B06 0 +OP4 E03B07 0 +OP4 E03B08 0 +OP4 E03B09 0 +OP4 E03B0A 0 +OP4 E03B0B 0 +OP4 E03B0C 0 +OP4 E03B0D 0 +OP4 E03B0E 0 +OP4 E03B0F 0 +OP4 E03B10 0 +OP4 E03B11 0 +OP4 E03B12 0 +OP4 E03B13 0 +OP4 E03B14 0 +OP4 E03B15 0 +OP4 E03B16 0 +OP4 E03B17 0 +OP4 E03B18 0 +OP4 E03B19 0 +OP4 E03B1A 0 +OP4 E03B1B 0 +OP4 E03B1C 0 +OP4 E03B1D 0 +OP4 E03B1E 0 +OP4 E03B1F 0 +OP4 E03B20 0 +OP4 E03B21 0 +OP4 E03B22 0 +OP4 E03B23 0 +OP4 E03B24 0 +OP4 E03B25 0 +OP4 E03B26 0 +OP4 E03B27 0 +OP4 E03B28 0 +OP4 E03B29 0 +OP4 E03B2A 0 +OP4 E03B2B 0 +OP4 E03B2C 0 +OP4 E03B2D 0 +OP4 E03B2E 0 +OP4 E03B2F 0 +OP4 E03B30 0 +OP4 E03B31 0 +OP4 E03B32 0 +OP4 E03B33 0 +OP4 E03B34 0 +OP4 E03B35 0 +OP4 E03B36 0 +OP4 E03B37 0 +OP4 E03B38 0 +OP4 E03B39 0 +OP4 E03B3A 0 +OP4 E03B3B 0 +OP4 E03B3C 0 +OP4 E03B3D 0 +OP4 E03B3E 0 +OP4 E03B3F 0 +OP4 E03B40 0 +OP4 E03B41 0 +OP4 E03B42 0 +OP4 E03B43 0 +OP4 E03B44 0 +OP4 E03B45 0 +OP4 E03B46 0 +OP4 E03B47 0 +OP4 E03B48 0 +OP4 E03B49 0 +OP4 E03B4A 0 +OP4 E03B4B 0 +OP4 E03B4C 0 +OP4 E03B4D 0 +OP4 E03B4E 0 +OP4 E03B4F 0 +OP4 E03B50 0 +OP4 E03B51 0 +OP4 E03B52 0 +OP4 E03B53 0 +OP4 E03B54 0 +OP4 E03B55 0 +OP4 E03B56 0 +OP4 E03B57 0 +OP4 E03B58 0 +OP4 E03B59 0 +OP4 E03B5A 0 +OP4 E03B5B 0 +OP4 E03B5C 0 +OP4 E03B5D 0 +OP4 E03B5E 0 +OP4 E03B5F 0 +OP4 E03B60 0 +OP4 E03B61 0 +OP4 E03B62 0 +OP4 E03B63 0 +OP4 E03B64 0 +OP4 E03B65 0 +OP4 E03B66 0 +OP4 E03B67 0 +OP4 E03B68 0 +OP4 E03B69 0 +OP4 E03B6A 0 +OP4 E03B6B 0 +OP4 E03B6C 0 +OP4 E03B6D 0 +OP4 E03B6E 0 +OP4 E03B6F 0 +OP4 E03B70 0 +OP4 E03B71 0 +OP4 E03B72 0 +OP4 E03B73 0 +OP4 E03B74 0 +OP4 E03B75 0 +OP4 E03B76 0 +OP4 E03B77 0 +OP4 E03B78 0 +OP4 E03B79 0 +OP4 E03B7A 0 +OP4 E03B7B 0 +OP4 E03B7C 0 +OP4 E03B7D 0 +OP4 E03B7E 0 +OP4 E03B7F 0 +OP4 E03B80 0 +OP4 E03B81 0 +OP4 E03B82 0 +OP4 E03B83 0 +OP4 E03B84 0 +OP4 E03B85 0 +OP4 E03B86 0 +OP4 E03B87 0 +OP4 E03B88 0 +OP4 E03B89 0 +OP4 E03B8A 0 +OP4 E03B8B 0 +OP4 E03B8C 0 +OP4 E03B8D 0 +OP4 E03B8E 0 +OP4 E03B8F 0 +OP4 E03B90 0 +OP4 E03B91 0 +OP4 E03B92 0 +OP4 E03B93 0 +OP4 E03B94 0 +OP4 E03B95 0 +OP4 E03B96 0 +OP4 E03B97 0 +OP4 E03B98 0 +OP4 E03B99 0 +OP4 E03B9A 0 +OP4 E03B9B 0 +OP4 E03B9C 0 +OP4 E03B9D 0 +OP4 E03B9E 0 +OP4 E03B9F 0 +OP4 E03BA0 0 +OP4 E03BA1 0 +OP4 E03BA2 0 +OP4 E03BA3 0 +OP4 E03BA4 0 +OP4 E03BA5 0 +OP4 E03BA6 0 +OP4 E03BA7 0 +OP4 E03BA8 0 +OP4 E03BA9 0 +OP4 E03BAA 0 +OP4 E03BAB 0 +OP4 E03BAC 0 +OP4 E03BAD 0 +OP4 E03BAE 0 +OP4 E03BAF 0 +OP4 E03BB0 0 +OP4 E03BB1 0 +OP4 E03BB2 0 +OP4 E03BB3 0 +OP4 E03BB4 0 +OP4 E03BB5 0 +OP4 E03BB6 0 +OP4 E03BB7 0 +OP4 E03BB8 0 +OP4 E03BB9 0 +OP4 E03BBA 0 +OP4 E03BBB 0 +OP4 E03BBC 0 +OP4 E03BBD 0 +OP4 E03BBE 0 +OP4 E03BBF 0 +OP4 E03BC0 0 +OP4 E03BC1 0 +OP4 E03BC2 0 +OP4 E03BC3 0 +OP4 E03BC4 0 +OP4 E03BC5 0 +OP4 E03BC6 0 +OP4 E03BC7 0 +OP4 E03BC8 0 +OP4 E03BC9 0 +OP4 E03BCA 0 +OP4 E03BCB 0 +OP4 E03BCC 0 +OP4 E03BCD 0 +OP4 E03BCE 0 +OP4 E03BCF 0 +OP4 E03BD0 0 +OP4 E03BD1 0 +OP4 E03BD2 0 +OP4 E03BD3 0 +OP4 E03BD4 0 +OP4 E03BD5 0 +OP4 E03BD6 0 +OP4 E03BD7 0 +OP4 E03BD8 0 +OP4 E03BD9 0 +OP4 E03BDA 0 +OP4 E03BDB 0 +OP4 E03BDC 0 +OP4 E03BDD 0 +OP4 E03BDE 0 +OP4 E03BDF 0 +OP4 E03BE0 0 +OP4 E03BE1 0 +OP4 E03BE2 0 +OP4 E03BE3 0 +OP4 E03BE4 0 +OP4 E03BE5 0 +OP4 E03BE6 0 +OP4 E03BE7 0 +OP4 E03BE8 0 +OP4 E03BE9 0 +OP4 E03BEA 0 +OP4 E03BEB 0 +OP4 E03BEC 0 +OP4 E03BED 0 +OP4 E03BEE 0 +OP4 E03BEF 0 +OP4 E03BF0 0 +OP4 E03BF1 0 +OP4 E03BF2 0 +OP4 E03BF3 0 +OP4 E03BF4 0 +OP4 E03BF5 0 +OP4 E03BF6 0 +OP4 E03BF7 0 +OP4 E03BF8 0 +OP4 E03BF9 0 +OP4 E03BFA 0 +OP4 E03BFB 0 +OP4 E03BFC 0 +OP4 E03BFD 0 +OP4 E03BFE 0 +OP4 E03BFF 0 +OP4 E03C00 0 +OP4 E03C01 0 +OP4 E03C02 0 +OP4 E03C03 0 +OP4 E03C04 0 +OP4 E03C05 0 +OP4 E03C06 0 +OP4 E03C07 0 +OP4 E03C08 0 +OP4 E03C09 0 +OP4 E03C0A 0 +OP4 E03C0B 0 +OP4 E03C0C 0 +OP4 E03C0D 0 +OP4 E03C0E 0 +OP4 E03C0F 0 +OP4 E03C10 0 +OP4 E03C11 0 +OP4 E03C12 0 +OP4 E03C13 0 +OP4 E03C14 0 +OP4 E03C15 0 +OP4 E03C16 0 +OP4 E03C17 0 +OP4 E03C18 0 +OP4 E03C19 0 +OP4 E03C1A 0 +OP4 E03C1B 0 +OP4 E03C1C 0 +OP4 E03C1D 0 +OP4 E03C1E 0 +OP4 E03C1F 0 +OP4 E03C20 0 +OP4 E03C21 0 +OP4 E03C22 0 +OP4 E03C23 0 +OP4 E03C24 0 +OP4 E03C25 0 +OP4 E03C26 0 +OP4 E03C27 0 +OP4 E03C28 0 +OP4 E03C29 0 +OP4 E03C2A 0 +OP4 E03C2B 0 +OP4 E03C2C 0 +OP4 E03C2D 0 +OP4 E03C2E 0 +OP4 E03C2F 0 +OP4 E03C30 0 +OP4 E03C31 0 +OP4 E03C32 0 +OP4 E03C33 0 +OP4 E03C34 0 +OP4 E03C35 0 +OP4 E03C36 0 +OP4 E03C37 0 +OP4 E03C38 0 +OP4 E03C39 0 +OP4 E03C3A 0 +OP4 E03C3B 0 +OP4 E03C3C 0 +OP4 E03C3D 0 +OP4 E03C3E 0 +OP4 E03C3F 0 +OP4 E03C40 0 +OP4 E03C41 0 +OP4 E03C42 0 +OP4 E03C43 0 +OP4 E03C44 0 +OP4 E03C45 0 +OP4 E03C46 0 +OP4 E03C47 0 +OP4 E03C48 0 +OP4 E03C49 0 +OP4 E03C4A 0 +OP4 E03C4B 0 +OP4 E03C4C 0 +OP4 E03C4D 0 +OP4 E03C4E 0 +OP4 E03C4F 0 +OP4 E03C50 0 +OP4 E03C51 0 +OP4 E03C52 0 +OP4 E03C53 0 +OP4 E03C54 0 +OP4 E03C55 0 +OP4 E03C56 0 +OP4 E03C57 0 +OP4 E03C58 0 +OP4 E03C59 0 +OP4 E03C5A 0 +OP4 E03C5B 0 +OP4 E03C5C 0 +OP4 E03C5D 0 +OP4 E03C5E 0 +OP4 E03C5F 0 +OP4 E03C60 0 +OP4 E03C61 0 +OP4 E03C62 0 +OP4 E03C63 0 +OP4 E03C64 0 +OP4 E03C65 0 +OP4 E03C66 0 +OP4 E03C67 0 +OP4 E03C68 0 +OP4 E03C69 0 +OP4 E03C6A 0 +OP4 E03C6B 0 +OP4 E03C6C 0 +OP4 E03C6D 0 +OP4 E03C6E 0 +OP4 E03C6F 0 +OP4 E03C70 0 +OP4 E03C71 0 +OP4 E03C72 0 +OP4 E03C73 0 +OP4 E03C74 0 +OP4 E03C75 0 +OP4 E03C76 0 +OP4 E03C77 0 +OP4 E03C78 0 +OP4 E03C79 0 +OP4 E03C7A 0 +OP4 E03C7B 0 +OP4 E03C7C 0 +OP4 E03C7D 0 +OP4 E03C7E 0 +OP4 E03C7F 0 +OP4 E03C80 0 +OP4 E03C81 0 +OP4 E03C82 0 +OP4 E03C83 0 +OP4 E03C84 0 +OP4 E03C85 0 +OP4 E03C86 0 +OP4 E03C87 0 +OP4 E03C88 0 +OP4 E03C89 0 +OP4 E03C8A 0 +OP4 E03C8B 0 +OP4 E03C8C 0 +OP4 E03C8D 0 +OP4 E03C8E 0 +OP4 E03C8F 0 +OP4 E03C90 0 +OP4 E03C91 0 +OP4 E03C92 0 +OP4 E03C93 0 +OP4 E03C94 0 +OP4 E03C95 0 +OP4 E03C96 0 +OP4 E03C97 0 +OP4 E03C98 0 +OP4 E03C99 0 +OP4 E03C9A 0 +OP4 E03C9B 0 +OP4 E03C9C 0 +OP4 E03C9D 0 +OP4 E03C9E 0 +OP4 E03C9F 0 +OP4 E03CA0 0 +OP4 E03CA1 0 +OP4 E03CA2 0 +OP4 E03CA3 0 +OP4 E03CA4 0 +OP4 E03CA5 0 +OP4 E03CA6 0 +OP4 E03CA7 0 +OP4 E03CA8 0 +OP4 E03CA9 0 +OP4 E03CAA 0 +OP4 E03CAB 0 +OP4 E03CAC 0 +OP4 E03CAD 0 +OP4 E03CAE 0 +OP4 E03CAF 0 +OP4 E03CB0 0 +OP4 E03CB1 0 +OP4 E03CB2 0 +OP4 E03CB3 0 +OP4 E03CB4 0 +OP4 E03CB5 0 +OP4 E03CB6 0 +OP4 E03CB7 0 +OP4 E03CB8 0 +OP4 E03CB9 0 +OP4 E03CBA 0 +OP4 E03CBB 0 +OP4 E03CBC 0 +OP4 E03CBD 0 +OP4 E03CBE 0 +OP4 E03CBF 0 +OP4 E03CC0 0 +OP4 E03CC1 0 +OP4 E03CC2 0 +OP4 E03CC3 0 +OP4 E03CC4 0 +OP4 E03CC5 0 +OP4 E03CC6 0 +OP4 E03CC7 0 +OP4 E03CC8 0 +OP4 E03CC9 0 +OP4 E03CCA 0 +OP4 E03CCB 0 +OP4 E03CCC 0 +OP4 E03CCD 0 +OP4 E03CCE 0 +OP4 E03CCF 0 +OP4 E03CD0 0 +OP4 E03CD1 0 +OP4 E03CD2 0 +OP4 E03CD3 0 +OP4 E03CD4 0 +OP4 E03CD5 0 +OP4 E03CD6 0 +OP4 E03CD7 0 +OP4 E03CD8 0 +OP4 E03CD9 0 +OP4 E03CDA 0 +OP4 E03CDB 0 +OP4 E03CDC 0 +OP4 E03CDD 0 +OP4 E03CDE 0 +OP4 E03CDF 0 +OP4 E03CE0 0 +OP4 E03CE1 0 +OP4 E03CE2 0 +OP4 E03CE3 0 +OP4 E03CE4 0 +OP4 E03CE5 0 +OP4 E03CE6 0 +OP4 E03CE7 0 +OP4 E03CE8 0 +OP4 E03CE9 0 +OP4 E03CEA 0 +OP4 E03CEB 0 +OP4 E03CEC 0 +OP4 E03CED 0 +OP4 E03CEE 0 +OP4 E03CEF 0 +OP4 E03CF0 0 +OP4 E03CF1 0 +OP4 E03CF2 0 +OP4 E03CF3 0 +OP4 E03CF4 0 +OP4 E03CF5 0 +OP4 E03CF6 0 +OP4 E03CF7 0 +OP4 E03CF8 0 +OP4 E03CF9 0 +OP4 E03CFA 0 +OP4 E03CFB 0 +OP4 E03CFC 0 +OP4 E03CFD 0 +OP4 E03CFE 0 +OP4 E03CFF 0 +OP4 E03D00 0 +OP4 E03D01 0 +OP4 E03D02 0 +OP4 E03D03 0 +OP4 E03D04 0 +OP4 E03D05 0 +OP4 E03D06 0 +OP4 E03D07 0 +OP4 E03D08 0 +OP4 E03D09 0 +OP4 E03D0A 0 +OP4 E03D0B 0 +OP4 E03D0C 0 +OP4 E03D0D 0 +OP4 E03D0E 0 +OP4 E03D0F 0 +OP4 E03D10 0 +OP4 E03D11 0 +OP4 E03D12 0 +OP4 E03D13 0 +OP4 E03D14 0 +OP4 E03D15 0 +OP4 E03D16 0 +OP4 E03D17 0 +OP4 E03D18 0 +OP4 E03D19 0 +OP4 E03D1A 0 +OP4 E03D1B 0 +OP4 E03D1C 0 +OP4 E03D1D 0 +OP4 E03D1E 0 +OP4 E03D1F 0 +OP4 E03D20 0 +OP4 E03D21 0 +OP4 E03D22 0 +OP4 E03D23 0 +OP4 E03D24 0 +OP4 E03D25 0 +OP4 E03D26 0 +OP4 E03D27 0 +OP4 E03D28 0 +OP4 E03D29 0 +OP4 E03D2A 0 +OP4 E03D2B 0 +OP4 E03D2C 0 +OP4 E03D2D 0 +OP4 E03D2E 0 +OP4 E03D2F 0 +OP4 E03D30 0 +OP4 E03D31 0 +OP4 E03D32 0 +OP4 E03D33 0 +OP4 E03D34 0 +OP4 E03D35 0 +OP4 E03D36 0 +OP4 E03D37 0 +OP4 E03D38 0 +OP4 E03D39 0 +OP4 E03D3A 0 +OP4 E03D3B 0 +OP4 E03D3C 0 +OP4 E03D3D 0 +OP4 E03D3E 0 +OP4 E03D3F 0 +OP4 E03D40 0 +OP4 E03D41 0 +OP4 E03D42 0 +OP4 E03D43 0 +OP4 E03D44 0 +OP4 E03D45 0 +OP4 E03D46 0 +OP4 E03D47 0 +OP4 E03D48 0 +OP4 E03D49 0 +OP4 E03D4A 0 +OP4 E03D4B 0 +OP4 E03D4C 0 +OP4 E03D4D 0 +OP4 E03D4E 0 +OP4 E03D4F 0 +OP4 E03D50 0 +OP4 E03D51 0 +OP4 E03D52 0 +OP4 E03D53 0 +OP4 E03D54 0 +OP4 E03D55 0 +OP4 E03D56 0 +OP4 E03D57 0 +OP4 E03D58 0 +OP4 E03D59 0 +OP4 E03D5A 0 +OP4 E03D5B 0 +OP4 E03D5C 0 +OP4 E03D5D 0 +OP4 E03D5E 0 +OP4 E03D5F 0 +OP4 E03D60 0 +OP4 E03D61 0 +OP4 E03D62 0 +OP4 E03D63 0 +OP4 E03D64 0 +OP4 E03D65 0 +OP4 E03D66 0 +OP4 E03D67 0 +OP4 E03D68 0 +OP4 E03D69 0 +OP4 E03D6A 0 +OP4 E03D6B 0 +OP4 E03D6C 0 +OP4 E03D6D 0 +OP4 E03D6E 0 +OP4 E03D6F 0 +OP4 E03D70 0 +OP4 E03D71 0 +OP4 E03D72 0 +OP4 E03D73 0 +OP4 E03D74 0 +OP4 E03D75 0 +OP4 E03D76 0 +OP4 E03D77 0 +OP4 E03D78 0 +OP4 E03D79 0 +OP4 E03D7A 0 +OP4 E03D7B 0 +OP4 E03D7C 0 +OP4 E03D7D 0 +OP4 E03D7E 0 +OP4 E03D7F 0 +OP4 E03D80 0 +OP4 E03D81 0 +OP4 E03D82 0 +OP4 E03D83 0 +OP4 E03D84 0 +OP4 E03D85 0 +OP4 E03D86 0 +OP4 E03D87 0 +OP4 E03D88 0 +OP4 E03D89 0 +OP4 E03D8A 0 +OP4 E03D8B 0 +OP4 E03D8C 0 +OP4 E03D8D 0 +OP4 E03D8E 0 +OP4 E03D8F 0 +OP4 E03D90 0 +OP4 E03D91 0 +OP4 E03D92 0 +OP4 E03D93 0 +OP4 E03D94 0 +OP4 E03D95 0 +OP4 E03D96 0 +OP4 E03D97 0 +OP4 E03D98 0 +OP4 E03D99 0 +OP4 E03D9A 0 +OP4 E03D9B 0 +OP4 E03D9C 0 +OP4 E03D9D 0 +OP4 E03D9E 0 +OP4 E03D9F 0 +OP4 E03DA0 0 +OP4 E03DA1 0 +OP4 E03DA2 0 +OP4 E03DA3 0 +OP4 E03DA4 0 +OP4 E03DA5 0 +OP4 E03DA6 0 +OP4 E03DA7 0 +OP4 E03DA8 0 +OP4 E03DA9 0 +OP4 E03DAA 0 +OP4 E03DAB 0 +OP4 E03DAC 0 +OP4 E03DAD 0 +OP4 E03DAE 0 +OP4 E03DAF 0 +OP4 E03DB0 0 +OP4 E03DB1 0 +OP4 E03DB2 0 +OP4 E03DB3 0 +OP4 E03DB4 0 +OP4 E03DB5 0 +OP4 E03DB6 0 +OP4 E03DB7 0 +OP4 E03DB8 0 +OP4 E03DB9 0 +OP4 E03DBA 0 +OP4 E03DBB 0 +OP4 E03DBC 0 +OP4 E03DBD 0 +OP4 E03DBE 0 +OP4 E03DBF 0 +OP4 E03DC0 0 +OP4 E03DC1 0 +OP4 E03DC2 0 +OP4 E03DC3 0 +OP4 E03DC4 0 diff --git a/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum4_itrace_irisc7.cfg.ext b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum4_itrace_irisc7.cfg.ext new file mode 100644 index 000000000000..e7485ae3a586 --- /dev/null +++ b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum4_itrace_irisc7.cfg.ext @@ -0,0 +1,15814 @@ +OP1 Spectrum4 +OP4 ITRACE0 0 +OP4 ITRACE1 0 +OP4 ITRACE2 0 +OP4 ITRACE3 0 +OP4 ITRACE4 0 +OP4 ITRACE5 0 +OP4 ITRACE6 0 +OP4 ITRACE7 1 +OP4 ITRACE8 0 +OP4 ITRACE9 0 +OP4 Main_PhyUC 0 +OP4 TILE0_ITRACE0 0 +OP4 TILE0_ITRACE1 0 +OP4 TILE0_ITRACE2 0 +OP4 TILE0_ITRACE3 0 +OP4 TILE0_ITRACE4 0 +OP4 TILE0_PhyUC 0 +OP4 TILE1_ITRACE0 0 +OP4 TILE1_ITRACE1 0 +OP4 TILE1_ITRACE2 0 +OP4 TILE1_ITRACE3 0 +OP4 TILE1_ITRACE4 0 +OP4 TILE1_PhyUC 0 +OP4 TILE2_ITRACE0 0 +OP4 TILE2_ITRACE1 0 +OP4 TILE2_ITRACE2 0 +OP4 TILE2_ITRACE3 0 +OP4 TILE2_ITRACE4 0 +OP4 TILE2_PhyUC 0 +OP4 TILE3_ITRACE0 0 +OP4 TILE3_ITRACE1 0 +OP4 TILE3_ITRACE2 0 +OP4 TILE3_ITRACE3 0 +OP4 TILE3_ITRACE4 0 +OP4 TILE3_PhyUC 0 +OP4 TILE4_ITRACE0 0 +OP4 TILE4_ITRACE1 0 +OP4 TILE4_ITRACE2 0 +OP4 TILE4_ITRACE3 0 +OP4 TILE4_ITRACE4 0 +OP4 TILE4_PhyUC 0 +OP4 TILE5_ITRACE0 0 +OP4 TILE5_ITRACE1 0 +OP4 TILE5_ITRACE2 0 +OP4 TILE5_ITRACE3 0 +OP4 TILE5_ITRACE4 0 +OP4 TILE5_PhyUC 0 +OP4 TILE6_ITRACE0 0 +OP4 TILE6_ITRACE1 0 +OP4 TILE6_ITRACE2 0 +OP4 TILE6_ITRACE3 0 +OP4 TILE6_ITRACE4 0 +OP4 TILE6_PhyUC 0 +OP4 TILE7_ITRACE0 0 +OP4 TILE7_ITRACE1 0 +OP4 TILE7_ITRACE2 0 +OP4 TILE7_ITRACE3 0 +OP4 TILE7_ITRACE4 0 +OP4 TILE7_PhyUC 0 +OP4 E0003B 0 +OP4 E0003C 0 +OP4 E0003D 0 +OP4 E0003E 0 +OP4 E0003F 0 +OP4 E00040 0 +OP4 E00041 0 +OP4 E00042 0 +OP4 E00043 0 +OP4 E00044 0 +OP4 E00045 0 +OP4 E00046 0 +OP4 E00047 0 +OP4 E00048 0 +OP4 E00049 0 +OP4 E0004A 0 +OP4 E0004B 0 +OP4 E0004C 0 +OP4 E0004D 0 +OP4 E0004E 0 +OP4 E0004F 0 +OP4 E00050 0 +OP4 E00051 0 +OP4 E00052 0 +OP4 E00053 0 +OP4 E00054 0 +OP4 E00055 0 +OP4 E00056 0 +OP4 E00057 0 +OP4 E00058 0 +OP4 E00059 0 +OP4 E0005A 0 +OP4 E0005B 0 +OP4 E0005C 0 +OP4 E0005D 0 +OP4 E0005E 0 +OP4 E0005F 0 +OP4 E00060 0 +OP4 E00061 0 +OP4 E00062 0 +OP4 E00063 0 +OP4 E00064 0 +OP4 E00065 0 +OP4 E00066 0 +OP4 E00067 0 +OP4 E00068 0 +OP4 E00069 0 +OP4 E0006A 0 +OP4 E0006B 0 +OP4 E0006C 0 +OP4 E0006D 0 +OP4 E0006E 0 +OP4 E0006F 0 +OP4 E00070 0 +OP4 E00071 0 +OP4 E00072 0 +OP4 E00073 0 +OP4 E00074 0 +OP4 E00075 0 +OP4 E00076 0 +OP4 E00077 0 +OP4 E00078 0 +OP4 E00079 0 +OP4 E0007A 0 +OP4 E0007B 0 +OP4 E0007C 0 +OP4 E0007D 0 +OP4 E0007E 0 +OP4 E0007F 0 +OP4 E00080 0 +OP4 E00081 0 +OP4 E00082 0 +OP4 E00083 0 +OP4 E00084 0 +OP4 E00085 0 +OP4 E00086 0 +OP4 E00087 0 +OP4 E00088 0 +OP4 E00089 0 +OP4 E0008A 0 +OP4 E0008B 0 +OP4 E0008C 0 +OP4 E0008D 0 +OP4 E0008E 0 +OP4 E0008F 0 +OP4 E00090 0 +OP4 E00091 0 +OP4 E00092 0 +OP4 E00093 0 +OP4 E00094 0 +OP4 E00095 0 +OP4 E00096 0 +OP4 E00097 0 +OP4 E00098 0 +OP4 E00099 0 +OP4 E0009A 0 +OP4 E0009B 0 +OP4 E0009C 0 +OP4 E0009D 0 +OP4 E0009E 0 +OP4 E0009F 0 +OP4 E000A0 0 +OP4 E000A1 0 +OP4 E000A2 0 +OP4 E000A3 0 +OP4 E000A4 0 +OP4 E000A5 0 +OP4 E000A6 0 +OP4 E000A7 0 +OP4 E000A8 0 +OP4 E000A9 0 +OP4 E000AA 0 +OP4 E000AB 0 +OP4 E000AC 0 +OP4 E000AD 0 +OP4 E000AE 0 +OP4 E000AF 0 +OP4 E000B0 0 +OP4 E000B1 0 +OP4 E000B2 0 +OP4 E000B3 0 +OP4 E000B4 0 +OP4 E000B5 0 +OP4 E000B6 0 +OP4 E000B7 0 +OP4 E000B8 0 +OP4 E000B9 0 +OP4 E000BA 0 +OP4 E000BB 0 +OP4 E000BC 0 +OP4 E000BD 0 +OP4 E000BE 0 +OP4 E000BF 0 +OP4 E000C0 0 +OP4 E000C1 0 +OP4 E000C2 0 +OP4 E000C3 0 +OP4 E000C4 0 +OP4 E000C5 0 +OP4 E000C6 0 +OP4 E000C7 0 +OP4 E000C8 0 +OP4 E000C9 0 +OP4 E000CA 0 +OP4 E000CB 0 +OP4 E000CC 0 +OP4 E000CD 0 +OP4 E000CE 0 +OP4 E000CF 0 +OP4 E000D0 0 +OP4 E000D1 0 +OP4 E000D2 0 +OP4 E000D3 0 +OP4 E000D4 0 +OP4 E000D5 0 +OP4 E000D6 0 +OP4 E000D7 0 +OP4 E000D8 0 +OP4 E000D9 0 +OP4 E000DA 0 +OP4 E000DB 0 +OP4 E000DC 0 +OP4 E000DD 0 +OP4 E000DE 0 +OP4 E000DF 0 +OP4 E000E0 0 +OP4 E000E1 0 +OP4 E000E2 0 +OP4 E000E3 0 +OP4 E000E4 0 +OP4 E000E5 0 +OP4 E000E6 0 +OP4 E000E7 0 +OP4 E000E8 0 +OP4 E000E9 0 +OP4 E000EA 0 +OP4 E000EB 0 +OP4 E000EC 0 +OP4 E000ED 0 +OP4 E000EE 0 +OP4 E000EF 0 +OP4 E000F0 0 +OP4 E000F1 0 +OP4 E000F2 0 +OP4 E000F3 0 +OP4 E000F4 0 +OP4 E000F5 0 +OP4 E000F6 0 +OP4 E000F7 0 +OP4 E000F8 0 +OP4 E000F9 0 +OP4 E000FA 0 +OP4 E000FB 0 +OP4 E000FC 0 +OP4 E000FD 0 +OP4 E000FE 0 +OP4 E000FF 0 +OP4 E00100 0 +OP4 E00101 0 +OP4 E00102 0 +OP4 E00103 0 +OP4 E00104 0 +OP4 E00105 0 +OP4 E00106 0 +OP4 E00107 0 +OP4 E00108 0 +OP4 E00109 0 +OP4 E0010A 0 +OP4 E0010B 0 +OP4 E0010C 0 +OP4 E0010D 0 +OP4 E0010E 0 +OP4 E0010F 0 +OP4 E00110 0 +OP4 E00111 0 +OP4 E00112 0 +OP4 E00113 0 +OP4 E00114 0 +OP4 E00115 0 +OP4 E00116 0 +OP4 E00117 0 +OP4 E00118 0 +OP4 E00119 0 +OP4 E0011A 0 +OP4 E0011B 0 +OP4 E0011C 0 +OP4 E0011D 0 +OP4 E0011E 0 +OP4 E0011F 0 +OP4 E00120 0 +OP4 E00121 0 +OP4 E00122 0 +OP4 E00123 0 +OP4 E00124 0 +OP4 E00125 0 +OP4 E00126 0 +OP4 E00127 0 +OP4 E00128 0 +OP4 E00129 0 +OP4 E0012A 0 +OP4 E0012B 0 +OP4 E0012C 0 +OP4 E0012D 0 +OP4 E0012E 0 +OP4 E0012F 0 +OP4 E00130 0 +OP4 E00131 0 +OP4 E00132 0 +OP4 E00133 0 +OP4 E00134 0 +OP4 E00135 0 +OP4 E00136 0 +OP4 E00137 0 +OP4 E00138 0 +OP4 E00139 0 +OP4 E0013A 0 +OP4 E0013B 0 +OP4 E0013C 0 +OP4 E0013D 0 +OP4 E0013E 0 +OP4 E0013F 0 +OP4 E00140 0 +OP4 E00141 0 +OP4 E00142 0 +OP4 E00143 0 +OP4 E00144 0 +OP4 E00145 0 +OP4 E00146 0 +OP4 E00147 0 +OP4 E00148 0 +OP4 E00149 0 +OP4 E0014A 0 +OP4 E0014B 0 +OP4 E0014C 0 +OP4 E0014D 0 +OP4 E0014E 0 +OP4 E0014F 0 +OP4 E00150 0 +OP4 E00151 0 +OP4 E00152 0 +OP4 E00153 0 +OP4 E00154 0 +OP4 E00155 0 +OP4 E00156 0 +OP4 E00157 0 +OP4 E00158 0 +OP4 E00159 0 +OP4 E0015A 0 +OP4 E0015B 0 +OP4 E0015C 0 +OP4 E0015D 0 +OP4 E0015E 0 +OP4 E0015F 0 +OP4 E00160 0 +OP4 E00161 0 +OP4 E00162 0 +OP4 E00163 0 +OP4 E00164 0 +OP4 E00165 0 +OP4 E00166 0 +OP4 E00167 0 +OP4 E00168 0 +OP4 E00169 0 +OP4 E0016A 0 +OP4 E0016B 0 +OP4 E0016C 0 +OP4 E0016D 0 +OP4 E0016E 0 +OP4 E0016F 0 +OP4 E00170 0 +OP4 E00171 0 +OP4 E00172 0 +OP4 E00173 0 +OP4 E00174 0 +OP4 E00175 0 +OP4 E00176 0 +OP4 E00177 0 +OP4 E00178 0 +OP4 E00179 0 +OP4 E0017A 0 +OP4 E0017B 0 +OP4 E0017C 0 +OP4 E0017D 0 +OP4 E0017E 0 +OP4 E0017F 0 +OP4 E00180 0 +OP4 E00181 0 +OP4 E00182 0 +OP4 E00183 0 +OP4 E00184 0 +OP4 E00185 0 +OP4 E00186 0 +OP4 E00187 0 +OP4 E00188 0 +OP4 E00189 0 +OP4 E0018A 0 +OP4 E0018B 0 +OP4 E0018C 0 +OP4 E0018D 0 +OP4 E0018E 0 +OP4 E0018F 0 +OP4 E00190 0 +OP4 E00191 0 +OP4 E00192 0 +OP4 E00193 0 +OP4 E00194 0 +OP4 E00195 0 +OP4 E00196 0 +OP4 E00197 0 +OP4 E00198 0 +OP4 E00199 0 +OP4 E0019A 0 +OP4 E0019B 0 +OP4 E0019C 0 +OP4 E0019D 0 +OP4 E0019E 0 +OP4 E0019F 0 +OP4 E001A0 0 +OP4 E001A1 0 +OP4 E001A2 0 +OP4 E001A3 0 +OP4 E001A4 0 +OP4 E001A5 0 +OP4 E001A6 0 +OP4 E001A7 0 +OP4 E001A8 0 +OP4 E001A9 0 +OP4 E001AA 0 +OP4 E001AB 0 +OP4 E001AC 0 +OP4 E001AD 0 +OP4 E001AE 0 +OP4 E001AF 0 +OP4 E001B0 0 +OP4 E001B1 0 +OP4 E001B2 0 +OP4 E001B3 0 +OP4 E001B4 0 +OP4 E001B5 0 +OP4 E001B6 0 +OP4 E001B7 0 +OP4 E001B8 0 +OP4 E001B9 0 +OP4 E001BA 0 +OP4 E001BB 0 +OP4 E001BC 0 +OP4 E001BD 0 +OP4 E001BE 0 +OP4 E001BF 0 +OP4 E001C0 0 +OP4 E001C1 0 +OP4 E001C2 0 +OP4 E001C3 0 +OP4 E001C4 0 +OP4 E001C5 0 +OP4 E001C6 0 +OP4 E001C7 0 +OP4 E001C8 0 +OP4 E001C9 0 +OP4 E001CA 0 +OP4 E001CB 0 +OP4 E001CC 0 +OP4 E001CD 0 +OP4 E001CE 0 +OP4 E001CF 0 +OP4 E001D0 0 +OP4 E001D1 0 +OP4 E001D2 0 +OP4 E001D3 0 +OP4 E001D4 0 +OP4 E001D5 0 +OP4 E001D6 0 +OP4 E001D7 0 +OP4 E001D8 0 +OP4 E001D9 0 +OP4 E001DA 0 +OP4 E001DB 0 +OP4 E001DC 0 +OP4 E001DD 0 +OP4 E001DE 0 +OP4 E001DF 0 +OP4 E001E0 0 +OP4 E001E1 0 +OP4 E001E2 0 +OP4 E001E3 0 +OP4 E001E4 0 +OP4 E001E5 0 +OP4 E001E6 0 +OP4 E001E7 0 +OP4 E001E8 0 +OP4 E001E9 0 +OP4 E001EA 0 +OP4 E001EB 0 +OP4 E001EC 0 +OP4 E001ED 0 +OP4 E001EE 0 +OP4 E001EF 0 +OP4 E001F0 0 +OP4 E001F1 0 +OP4 E001F2 0 +OP4 E001F3 0 +OP4 E001F4 0 +OP4 E001F5 0 +OP4 E001F6 0 +OP4 E001F7 0 +OP4 E001F8 0 +OP4 E001F9 0 +OP4 E001FA 0 +OP4 E001FB 0 +OP4 E001FC 0 +OP4 E001FD 0 +OP4 E001FE 0 +OP4 E001FF 0 +OP4 E00200 0 +OP4 E00201 0 +OP4 E00202 0 +OP4 E00203 0 +OP4 E00204 0 +OP4 E00205 0 +OP4 E00206 0 +OP4 E00207 0 +OP4 E00208 0 +OP4 E00209 0 +OP4 E0020A 0 +OP4 E0020B 0 +OP4 E0020C 0 +OP4 E0020D 0 +OP4 E0020E 0 +OP4 E0020F 0 +OP4 E00210 0 +OP4 E00211 0 +OP4 E00212 0 +OP4 E00213 0 +OP4 E00214 0 +OP4 E00215 0 +OP4 E00216 0 +OP4 E00217 0 +OP4 E00218 0 +OP4 E00219 0 +OP4 E0021A 0 +OP4 E0021B 0 +OP4 E0021C 0 +OP4 E0021D 0 +OP4 E0021E 0 +OP4 E0021F 0 +OP4 E00220 0 +OP4 E00221 0 +OP4 E00222 0 +OP4 E00223 0 +OP4 E00224 0 +OP4 E00225 0 +OP4 E00226 0 +OP4 E00227 0 +OP4 E00228 0 +OP4 E00229 0 +OP4 E0022A 0 +OP4 E0022B 0 +OP4 E0022C 0 +OP4 E0022D 0 +OP4 E0022E 0 +OP4 E0022F 0 +OP4 E00230 0 +OP4 E00231 0 +OP4 E00232 0 +OP4 E00233 0 +OP4 E00234 0 +OP4 E00235 0 +OP4 E00236 0 +OP4 E00237 0 +OP4 E00238 0 +OP4 E00239 0 +OP4 E0023A 0 +OP4 E0023B 0 +OP4 E0023C 0 +OP4 E0023D 0 +OP4 E0023E 0 +OP4 E0023F 0 +OP4 E00240 0 +OP4 E00241 0 +OP4 E00242 0 +OP4 E00243 0 +OP4 E00244 0 +OP4 E00245 0 +OP4 E00246 0 +OP4 E00247 0 +OP4 E00248 0 +OP4 E00249 0 +OP4 E0024A 0 +OP4 E0024B 0 +OP4 E0024C 0 +OP4 E0024D 0 +OP4 E0024E 0 +OP4 E0024F 0 +OP4 E00250 0 +OP4 E00251 0 +OP4 E00252 0 +OP4 E00253 0 +OP4 E00254 0 +OP4 E00255 0 +OP4 E00256 0 +OP4 E00257 0 +OP4 E00258 0 +OP4 E00259 0 +OP4 E0025A 0 +OP4 E0025B 0 +OP4 E0025C 0 +OP4 E0025D 0 +OP4 E0025E 0 +OP4 E0025F 0 +OP4 E00260 0 +OP4 E00261 0 +OP4 E00262 0 +OP4 E00263 0 +OP4 E00264 0 +OP4 E00265 0 +OP4 E00266 0 +OP4 E00267 0 +OP4 E00268 0 +OP4 E00269 0 +OP4 E0026A 0 +OP4 E0026B 0 +OP4 E0026C 0 +OP4 E0026D 0 +OP4 E0026E 0 +OP4 E0026F 0 +OP4 E00270 0 +OP4 E00271 0 +OP4 E00272 0 +OP4 E00273 0 +OP4 E00274 0 +OP4 E00275 0 +OP4 E00276 0 +OP4 E00277 0 +OP4 E00278 0 +OP4 E00279 0 +OP4 E0027A 0 +OP4 E0027B 0 +OP4 E0027C 0 +OP4 E0027D 0 +OP4 E0027E 0 +OP4 E0027F 0 +OP4 E00280 0 +OP4 E00281 0 +OP4 E00282 0 +OP4 E00283 0 +OP4 E00284 0 +OP4 E00285 0 +OP4 E00286 0 +OP4 E00287 0 +OP4 E00288 0 +OP4 E00289 0 +OP4 E0028A 0 +OP4 E0028B 0 +OP4 E0028C 0 +OP4 E0028D 0 +OP4 E0028E 0 +OP4 E0028F 0 +OP4 E00290 0 +OP4 E00291 0 +OP4 E00292 0 +OP4 E00293 0 +OP4 E00294 0 +OP4 E00295 0 +OP4 E00296 0 +OP4 E00297 0 +OP4 E00298 0 +OP4 E00299 0 +OP4 E0029A 0 +OP4 E0029B 0 +OP4 E0029C 0 +OP4 E0029D 0 +OP4 E0029E 0 +OP4 E0029F 0 +OP4 E002A0 0 +OP4 E002A1 0 +OP4 E002A2 0 +OP4 E002A3 0 +OP4 E002A4 0 +OP4 E002A5 0 +OP4 E002A6 0 +OP4 E002A7 0 +OP4 E002A8 0 +OP4 E002A9 0 +OP4 E002AA 0 +OP4 E002AB 0 +OP4 E002AC 0 +OP4 E002AD 0 +OP4 E002AE 0 +OP4 E002AF 0 +OP4 E002B0 0 +OP4 E002B1 0 +OP4 E002B2 0 +OP4 E002B3 0 +OP4 E002B4 0 +OP4 E002B5 0 +OP4 E002B6 0 +OP4 E002B7 0 +OP4 E002B8 0 +OP4 E002B9 0 +OP4 E002BA 0 +OP4 E002BB 0 +OP4 E002BC 0 +OP4 E002BD 0 +OP4 E002BE 0 +OP4 E002BF 0 +OP4 E002C0 0 +OP4 E002C1 0 +OP4 E002C2 0 +OP4 E002C3 0 +OP4 E002C4 0 +OP4 E002C5 0 +OP4 E002C6 0 +OP4 E002C7 0 +OP4 E002C8 0 +OP4 E002C9 0 +OP4 E002CA 0 +OP4 E002CB 0 +OP4 E002CC 0 +OP4 E002CD 0 +OP4 E002CE 0 +OP4 E002CF 0 +OP4 E002D0 0 +OP4 E002D1 0 +OP4 E002D2 0 +OP4 E002D3 0 +OP4 E002D4 0 +OP4 E002D5 0 +OP4 E002D6 0 +OP4 E002D7 0 +OP4 E002D8 0 +OP4 E002D9 0 +OP4 E002DA 0 +OP4 E002DB 0 +OP4 E002DC 0 +OP4 E002DD 0 +OP4 E002DE 0 +OP4 E002DF 0 +OP4 E002E0 0 +OP4 E002E1 0 +OP4 E002E2 0 +OP4 E002E3 0 +OP4 E002E4 0 +OP4 E002E5 0 +OP4 E002E6 0 +OP4 E002E7 0 +OP4 E002E8 0 +OP4 E002E9 0 +OP4 E002EA 0 +OP4 E002EB 0 +OP4 E002EC 0 +OP4 E002ED 0 +OP4 E002EE 0 +OP4 E002EF 0 +OP4 E002F0 0 +OP4 E002F1 0 +OP4 E002F2 0 +OP4 E002F3 0 +OP4 E002F4 0 +OP4 E002F5 0 +OP4 E002F6 0 +OP4 E002F7 0 +OP4 E002F8 0 +OP4 E002F9 0 +OP4 E002FA 0 +OP4 E002FB 0 +OP4 E002FC 0 +OP4 E002FD 0 +OP4 E002FE 0 +OP4 E002FF 0 +OP4 E00300 0 +OP4 E00301 0 +OP4 E00302 0 +OP4 E00303 0 +OP4 E00304 0 +OP4 E00305 0 +OP4 E00306 0 +OP4 E00307 0 +OP4 E00308 0 +OP4 E00309 0 +OP4 E0030A 0 +OP4 E0030B 0 +OP4 E0030C 0 +OP4 E0030D 0 +OP4 E0030E 0 +OP4 E0030F 0 +OP4 E00310 0 +OP4 E00311 0 +OP4 E00312 0 +OP4 E00313 0 +OP4 E00314 0 +OP4 E00315 0 +OP4 E00316 0 +OP4 E00317 0 +OP4 E00318 0 +OP4 E00319 0 +OP4 E0031A 0 +OP4 E0031B 0 +OP4 E0031C 0 +OP4 E0031D 0 +OP4 E0031E 0 +OP4 E0031F 0 +OP4 E00320 0 +OP4 E00321 0 +OP4 E00322 0 +OP4 E00323 0 +OP4 E00324 0 +OP4 E00325 0 +OP4 E00326 0 +OP4 E00327 0 +OP4 E00328 0 +OP4 E00329 0 +OP4 E0032A 0 +OP4 E0032B 0 +OP4 E0032C 0 +OP4 E0032D 0 +OP4 E0032E 0 +OP4 E0032F 0 +OP4 E00330 0 +OP4 E00331 0 +OP4 E00332 0 +OP4 E00333 0 +OP4 E00334 0 +OP4 E00335 0 +OP4 E00336 0 +OP4 E00337 0 +OP4 E00338 0 +OP4 E00339 0 +OP4 E0033A 0 +OP4 E0033B 0 +OP4 E0033C 0 +OP4 E0033D 0 +OP4 E0033E 0 +OP4 E0033F 0 +OP4 E00340 0 +OP4 E00341 0 +OP4 E00342 0 +OP4 E00343 0 +OP4 E00344 0 +OP4 E00345 0 +OP4 E00346 0 +OP4 E00347 0 +OP4 E00348 0 +OP4 E00349 0 +OP4 E0034A 0 +OP4 E0034B 0 +OP4 E0034C 0 +OP4 E0034D 0 +OP4 E0034E 0 +OP4 E0034F 0 +OP4 E00350 0 +OP4 E00351 0 +OP4 E00352 0 +OP4 E00353 0 +OP4 E00354 0 +OP4 E00355 0 +OP4 E00356 0 +OP4 E00357 0 +OP4 E00358 0 +OP4 E00359 0 +OP4 E0035A 0 +OP4 E0035B 0 +OP4 E0035C 0 +OP4 E0035D 0 +OP4 E0035E 0 +OP4 E0035F 0 +OP4 E00360 0 +OP4 E00361 0 +OP4 E00362 0 +OP4 E00363 0 +OP4 E00364 0 +OP4 E00365 0 +OP4 E00366 0 +OP4 E00367 0 +OP4 E00368 0 +OP4 E00369 0 +OP4 E0036A 0 +OP4 E0036B 0 +OP4 E0036C 0 +OP4 E0036D 0 +OP4 E0036E 0 +OP4 E0036F 0 +OP4 E00370 0 +OP4 E00371 0 +OP4 E00372 0 +OP4 E00373 0 +OP4 E00374 0 +OP4 E00375 0 +OP4 E00376 0 +OP4 E00377 0 +OP4 E00378 0 +OP4 E00379 0 +OP4 E0037A 0 +OP4 E0037B 0 +OP4 E0037C 0 +OP4 E0037D 0 +OP4 E0037E 0 +OP4 E0037F 0 +OP4 E00380 0 +OP4 E00381 0 +OP4 E00382 0 +OP4 E00383 0 +OP4 E00384 0 +OP4 E00385 0 +OP4 E00386 0 +OP4 E00387 0 +OP4 E00388 0 +OP4 E00389 0 +OP4 E0038A 0 +OP4 E0038B 0 +OP4 E0038C 0 +OP4 E0038D 0 +OP4 E0038E 0 +OP4 E0038F 0 +OP4 E00390 0 +OP4 E00391 0 +OP4 E00392 0 +OP4 E00393 0 +OP4 E00394 0 +OP4 E00395 0 +OP4 E00396 0 +OP4 E00397 0 +OP4 E00398 0 +OP4 E00399 0 +OP4 E0039A 0 +OP4 E0039B 0 +OP4 E0039C 0 +OP4 E0039D 0 +OP4 E0039E 0 +OP4 E0039F 0 +OP4 E003A0 0 +OP4 E003A1 0 +OP4 E003A2 0 +OP4 E003A3 0 +OP4 E003A4 0 +OP4 E003A5 0 +OP4 E003A6 0 +OP4 E003A7 0 +OP4 E003A8 0 +OP4 E003A9 0 +OP4 E003AA 0 +OP4 E003AB 0 +OP4 E003AC 0 +OP4 E003AD 0 +OP4 E003AE 0 +OP4 E003AF 0 +OP4 E003B0 0 +OP4 E003B1 0 +OP4 E003B2 0 +OP4 E003B3 0 +OP4 E003B4 0 +OP4 E003B5 0 +OP4 E003B6 0 +OP4 E003B7 0 +OP4 E003B8 0 +OP4 E003B9 0 +OP4 E003BA 0 +OP4 E003BB 0 +OP4 E003BC 0 +OP4 E003BD 0 +OP4 E003BE 0 +OP4 E003BF 0 +OP4 E003C0 0 +OP4 E003C1 0 +OP4 E003C2 0 +OP4 E003C3 0 +OP4 E003C4 0 +OP4 E003C5 0 +OP4 E003C6 0 +OP4 E003C7 0 +OP4 E003C8 0 +OP4 E003C9 0 +OP4 E003CA 0 +OP4 E003CB 0 +OP4 E003CC 0 +OP4 E003CD 0 +OP4 E003CE 0 +OP4 E003CF 0 +OP4 E003D0 0 +OP4 E003D1 0 +OP4 E003D2 0 +OP4 E003D3 0 +OP4 E003D4 0 +OP4 E003D5 0 +OP4 E003D6 0 +OP4 E003D7 0 +OP4 E003D8 0 +OP4 E003D9 0 +OP4 E003DA 0 +OP4 E003DB 0 +OP4 E003DC 0 +OP4 E003DD 0 +OP4 E003DE 0 +OP4 E003DF 0 +OP4 E003E0 0 +OP4 E003E1 0 +OP4 E003E2 0 +OP4 E003E3 0 +OP4 E003E4 0 +OP4 E003E5 0 +OP4 E003E6 0 +OP4 E003E7 0 +OP4 E003E8 0 +OP4 E003E9 0 +OP4 E003EA 0 +OP4 E003EB 0 +OP4 E003EC 0 +OP4 E003ED 0 +OP4 E003EE 0 +OP4 E003EF 0 +OP4 E003F0 0 +OP4 E003F1 0 +OP4 E003F2 0 +OP4 E003F3 0 +OP4 E003F4 0 +OP4 E003F5 0 +OP4 E003F6 0 +OP4 E003F7 0 +OP4 E003F8 0 +OP4 E003F9 0 +OP4 E003FA 0 +OP4 E003FB 0 +OP4 E003FC 0 +OP4 E003FD 0 +OP4 E003FE 0 +OP4 E003FF 0 +OP4 E00400 0 +OP4 E00401 0 +OP4 E00402 0 +OP4 E00403 0 +OP4 E00404 0 +OP4 E00405 0 +OP4 E00406 0 +OP4 E00407 0 +OP4 E00408 0 +OP4 E00409 0 +OP4 E0040A 0 +OP4 E0040B 0 +OP4 E0040C 0 +OP4 E0040D 0 +OP4 E0040E 0 +OP4 E0040F 0 +OP4 E00410 0 +OP4 E00411 0 +OP4 E00412 0 +OP4 E00413 0 +OP4 E00414 0 +OP4 E00415 0 +OP4 E00416 0 +OP4 E00417 0 +OP4 E00418 0 +OP4 E00419 0 +OP4 E0041A 0 +OP4 E0041B 0 +OP4 E0041C 0 +OP4 E0041D 0 +OP4 E0041E 0 +OP4 E0041F 0 +OP4 E00420 0 +OP4 E00421 0 +OP4 E00422 0 +OP4 E00423 0 +OP4 E00424 0 +OP4 E00425 0 +OP4 E00426 0 +OP4 E00427 0 +OP4 E00428 0 +OP4 E00429 0 +OP4 E0042A 0 +OP4 E0042B 0 +OP4 E0042C 0 +OP4 E0042D 0 +OP4 E0042E 0 +OP4 E0042F 0 +OP4 E00430 0 +OP4 E00431 0 +OP4 E00432 0 +OP4 E00433 0 +OP4 E00434 0 +OP4 E00435 0 +OP4 E00436 0 +OP4 E00437 0 +OP4 E00438 0 +OP4 E00439 0 +OP4 E0043A 0 +OP4 E0043B 0 +OP4 E0043C 0 +OP4 E0043D 0 +OP4 E0043E 0 +OP4 E0043F 0 +OP4 E00440 0 +OP4 E00441 0 +OP4 E00442 0 +OP4 E00443 0 +OP4 E00444 0 +OP4 E00445 0 +OP4 E00446 0 +OP4 E00447 0 +OP4 E00448 0 +OP4 E00449 0 +OP4 E0044A 0 +OP4 E0044B 0 +OP4 E0044C 0 +OP4 E0044D 0 +OP4 E0044E 0 +OP4 E0044F 0 +OP4 E00450 0 +OP4 E00451 0 +OP4 E00452 0 +OP4 E00453 0 +OP4 E00454 0 +OP4 E00455 0 +OP4 E00456 0 +OP4 E00457 0 +OP4 E00458 0 +OP4 E00459 0 +OP4 E0045A 0 +OP4 E0045B 0 +OP4 E0045C 0 +OP4 E0045D 0 +OP4 E0045E 0 +OP4 E0045F 0 +OP4 E00460 0 +OP4 E00461 0 +OP4 E00462 0 +OP4 E00463 0 +OP4 E00464 0 +OP4 E00465 0 +OP4 E00466 0 +OP4 E00467 0 +OP4 E00468 0 +OP4 E00469 0 +OP4 E0046A 0 +OP4 E0046B 0 +OP4 E0046C 0 +OP4 E0046D 0 +OP4 E0046E 0 +OP4 E0046F 0 +OP4 E00470 0 +OP4 E00471 0 +OP4 E00472 0 +OP4 E00473 0 +OP4 E00474 0 +OP4 E00475 0 +OP4 E00476 0 +OP4 E00477 0 +OP4 E00478 0 +OP4 E00479 0 +OP4 E0047A 0 +OP4 E0047B 0 +OP4 E0047C 0 +OP4 E0047D 0 +OP4 E0047E 0 +OP4 E0047F 0 +OP4 E00480 0 +OP4 E00481 0 +OP4 E00482 0 +OP4 E00483 0 +OP4 E00484 0 +OP4 E00485 0 +OP4 E00486 0 +OP4 E00487 0 +OP4 E00488 0 +OP4 E00489 0 +OP4 E0048A 0 +OP4 E0048B 0 +OP4 E0048C 0 +OP4 E0048D 0 +OP4 E0048E 0 +OP4 E0048F 0 +OP4 E00490 0 +OP4 E00491 0 +OP4 E00492 0 +OP4 E00493 0 +OP4 E00494 0 +OP4 E00495 0 +OP4 E00496 0 +OP4 E00497 0 +OP4 E00498 0 +OP4 E00499 0 +OP4 E0049A 0 +OP4 E0049B 0 +OP4 E0049C 0 +OP4 E0049D 0 +OP4 E0049E 0 +OP4 E0049F 0 +OP4 E004A0 0 +OP4 E004A1 0 +OP4 E004A2 0 +OP4 E004A3 0 +OP4 E004A4 0 +OP4 E004A5 0 +OP4 E004A6 0 +OP4 E004A7 0 +OP4 E004A8 0 +OP4 E004A9 0 +OP4 E004AA 0 +OP4 E004AB 0 +OP4 E004AC 0 +OP4 E004AD 0 +OP4 E004AE 0 +OP4 E004AF 0 +OP4 E004B0 0 +OP4 E004B1 0 +OP4 E004B2 0 +OP4 E004B3 0 +OP4 E004B4 0 +OP4 E004B5 0 +OP4 E004B6 0 +OP4 E004B7 0 +OP4 E004B8 0 +OP4 E004B9 0 +OP4 E004BA 0 +OP4 E004BB 0 +OP4 E004BC 0 +OP4 E004BD 0 +OP4 E004BE 0 +OP4 E004BF 0 +OP4 E004C0 0 +OP4 E004C1 0 +OP4 E004C2 0 +OP4 E004C3 0 +OP4 E004C4 0 +OP4 E004C5 0 +OP4 E004C6 0 +OP4 E004C7 0 +OP4 E004C8 0 +OP4 E004C9 0 +OP4 E004CA 0 +OP4 E004CB 0 +OP4 E004CC 0 +OP4 E004CD 0 +OP4 E004CE 0 +OP4 E004CF 0 +OP4 E004D0 0 +OP4 E004D1 0 +OP4 E004D2 0 +OP4 E004D3 0 +OP4 E004D4 0 +OP4 E004D5 0 +OP4 E004D6 0 +OP4 E004D7 0 +OP4 E004D8 0 +OP4 E004D9 0 +OP4 E004DA 0 +OP4 E004DB 0 +OP4 E004DC 0 +OP4 E004DD 0 +OP4 E004DE 0 +OP4 E004DF 0 +OP4 E004E0 0 +OP4 E004E1 0 +OP4 E004E2 0 +OP4 E004E3 0 +OP4 E004E4 0 +OP4 E004E5 0 +OP4 E004E6 0 +OP4 E004E7 0 +OP4 E004E8 0 +OP4 E004E9 0 +OP4 E004EA 0 +OP4 E004EB 0 +OP4 E004EC 0 +OP4 E004ED 0 +OP4 E004EE 0 +OP4 E004EF 0 +OP4 E004F0 0 +OP4 E004F1 0 +OP4 E004F2 0 +OP4 E004F3 0 +OP4 E004F4 0 +OP4 E004F5 0 +OP4 E004F6 0 +OP4 E004F7 0 +OP4 E004F8 0 +OP4 E004F9 0 +OP4 E004FA 0 +OP4 E004FB 0 +OP4 E004FC 0 +OP4 E004FD 0 +OP4 E004FE 0 +OP4 E004FF 0 +OP4 E00500 0 +OP4 E00501 0 +OP4 E00502 0 +OP4 E00503 0 +OP4 E00504 0 +OP4 E00505 0 +OP4 E00506 0 +OP4 E00507 0 +OP4 E00508 0 +OP4 E00509 0 +OP4 E0050A 0 +OP4 E0050B 0 +OP4 E0050C 0 +OP4 E0050D 0 +OP4 E0050E 0 +OP4 E0050F 0 +OP4 E00510 0 +OP4 E00511 0 +OP4 E00512 0 +OP4 E00513 0 +OP4 E00514 0 +OP4 E00515 0 +OP4 E00516 0 +OP4 E00517 0 +OP4 E00518 0 +OP4 E00519 0 +OP4 E0051A 0 +OP4 E0051B 0 +OP4 E0051C 0 +OP4 E0051D 0 +OP4 E0051E 0 +OP4 E0051F 0 +OP4 E00520 0 +OP4 E00521 0 +OP4 E00522 0 +OP4 E00523 0 +OP4 E00524 0 +OP4 E00525 0 +OP4 E00526 0 +OP4 E00527 0 +OP4 E00528 0 +OP4 E00529 0 +OP4 E0052A 0 +OP4 E0052B 0 +OP4 E0052C 0 +OP4 E0052D 0 +OP4 E0052E 0 +OP4 E0052F 0 +OP4 E00530 0 +OP4 E00531 0 +OP4 E00532 0 +OP4 E00533 0 +OP4 E00534 0 +OP4 E00535 0 +OP4 E00536 0 +OP4 E00537 0 +OP4 E00538 0 +OP4 E00539 0 +OP4 E0053A 0 +OP4 E0053B 0 +OP4 E0053C 0 +OP4 E0053D 0 +OP4 E0053E 0 +OP4 E0053F 0 +OP4 E00540 0 +OP4 E00541 0 +OP4 E00542 0 +OP4 E00543 0 +OP4 E00544 0 +OP4 E00545 0 +OP4 E00546 0 +OP4 E00547 0 +OP4 E00548 0 +OP4 E00549 0 +OP4 E0054A 0 +OP4 E0054B 0 +OP4 E0054C 0 +OP4 E0054D 0 +OP4 E0054E 0 +OP4 E0054F 0 +OP4 E00550 0 +OP4 E00551 0 +OP4 E00552 0 +OP4 E00553 0 +OP4 E00554 0 +OP4 E00555 0 +OP4 E00556 0 +OP4 E00557 0 +OP4 E00558 0 +OP4 E00559 0 +OP4 E0055A 0 +OP4 E0055B 0 +OP4 E0055C 0 +OP4 E0055D 0 +OP4 E0055E 0 +OP4 E0055F 0 +OP4 E00560 0 +OP4 E00561 0 +OP4 E00562 0 +OP4 E00563 0 +OP4 E00564 0 +OP4 E00565 0 +OP4 E00566 0 +OP4 E00567 0 +OP4 E00568 0 +OP4 E00569 0 +OP4 E0056A 0 +OP4 E0056B 0 +OP4 E0056C 0 +OP4 E0056D 0 +OP4 E0056E 0 +OP4 E0056F 0 +OP4 E00570 0 +OP4 E00571 0 +OP4 E00572 0 +OP4 E00573 0 +OP4 E00574 0 +OP4 E00575 0 +OP4 E00576 0 +OP4 E00577 0 +OP4 E00578 0 +OP4 E00579 0 +OP4 E0057A 0 +OP4 E0057B 0 +OP4 E0057C 0 +OP4 E0057D 0 +OP4 E0057E 0 +OP4 E0057F 0 +OP4 E00580 0 +OP4 E00581 0 +OP4 E00582 0 +OP4 E00583 0 +OP4 E00584 0 +OP4 E00585 0 +OP4 E00586 0 +OP4 E00587 0 +OP4 E00588 0 +OP4 E00589 0 +OP4 E0058A 0 +OP4 E0058B 0 +OP4 E0058C 0 +OP4 E0058D 0 +OP4 E0058E 0 +OP4 E0058F 0 +OP4 E00590 0 +OP4 E00591 0 +OP4 E00592 0 +OP4 E00593 0 +OP4 E00594 0 +OP4 E00595 0 +OP4 E00596 0 +OP4 E00597 0 +OP4 E00598 0 +OP4 E00599 0 +OP4 E0059A 0 +OP4 E0059B 0 +OP4 E0059C 0 +OP4 E0059D 0 +OP4 E0059E 0 +OP4 E0059F 0 +OP4 E005A0 0 +OP4 E005A1 0 +OP4 E005A2 0 +OP4 E005A3 0 +OP4 E005A4 0 +OP4 E005A5 0 +OP4 E005A6 0 +OP4 E005A7 0 +OP4 E005A8 0 +OP4 E005A9 0 +OP4 E005AA 0 +OP4 E005AB 0 +OP4 E005AC 0 +OP4 E005AD 0 +OP4 E005AE 0 +OP4 E005AF 0 +OP4 E005B0 0 +OP4 E005B1 0 +OP4 E005B2 0 +OP4 E005B3 0 +OP4 E005B4 0 +OP4 E005B5 0 +OP4 E005B6 0 +OP4 E005B7 0 +OP4 E005B8 0 +OP4 E005B9 0 +OP4 E005BA 0 +OP4 E005BB 0 +OP4 E005BC 0 +OP4 E005BD 0 +OP4 E005BE 0 +OP4 E005BF 0 +OP4 E005C0 0 +OP4 E005C1 0 +OP4 E005C2 0 +OP4 E005C3 0 +OP4 E005C4 0 +OP4 E005C5 0 +OP4 E005C6 0 +OP4 E005C7 0 +OP4 E005C8 0 +OP4 E005C9 0 +OP4 E005CA 0 +OP4 E005CB 0 +OP4 E005CC 0 +OP4 E005CD 0 +OP4 E005CE 0 +OP4 E005CF 0 +OP4 E005D0 0 +OP4 E005D1 0 +OP4 E005D2 0 +OP4 E005D3 0 +OP4 E005D4 0 +OP4 E005D5 0 +OP4 E005D6 0 +OP4 E005D7 0 +OP4 E005D8 0 +OP4 E005D9 0 +OP4 E005DA 0 +OP4 E005DB 0 +OP4 E005DC 0 +OP4 E005DD 0 +OP4 E005DE 0 +OP4 E005DF 0 +OP4 E005E0 0 +OP4 E005E1 0 +OP4 E005E2 0 +OP4 E005E3 0 +OP4 E005E4 0 +OP4 E005E5 0 +OP4 E005E6 0 +OP4 E005E7 0 +OP4 E005E8 0 +OP4 E005E9 0 +OP4 E005EA 0 +OP4 E005EB 0 +OP4 E005EC 0 +OP4 E005ED 0 +OP4 E005EE 0 +OP4 E005EF 0 +OP4 E005F0 0 +OP4 E005F1 0 +OP4 E005F2 0 +OP4 E005F3 0 +OP4 E005F4 0 +OP4 E005F5 0 +OP4 E005F6 0 +OP4 E005F7 0 +OP4 E005F8 0 +OP4 E005F9 0 +OP4 E005FA 0 +OP4 E005FB 0 +OP4 E005FC 0 +OP4 E005FD 0 +OP4 E005FE 0 +OP4 E005FF 0 +OP4 E00600 0 +OP4 E00601 0 +OP4 E00602 0 +OP4 E00603 0 +OP4 E00604 0 +OP4 E00605 0 +OP4 E00606 0 +OP4 E00607 0 +OP4 E00608 0 +OP4 E00609 0 +OP4 E0060A 0 +OP4 E0060B 0 +OP4 E0060C 0 +OP4 E0060D 0 +OP4 E0060E 0 +OP4 E0060F 0 +OP4 E00610 0 +OP4 E00611 0 +OP4 E00612 0 +OP4 E00613 0 +OP4 E00614 0 +OP4 E00615 0 +OP4 E00616 0 +OP4 E00617 0 +OP4 E00618 0 +OP4 E00619 0 +OP4 E0061A 0 +OP4 E0061B 0 +OP4 E0061C 0 +OP4 E0061D 0 +OP4 E0061E 0 +OP4 E0061F 0 +OP4 E00620 0 +OP4 E00621 0 +OP4 E00622 0 +OP4 E00623 0 +OP4 E00624 0 +OP4 E00625 0 +OP4 E00626 0 +OP4 E00627 0 +OP4 E00628 0 +OP4 E00629 0 +OP4 E0062A 0 +OP4 E0062B 0 +OP4 E0062C 0 +OP4 E0062D 0 +OP4 E0062E 0 +OP4 E0062F 0 +OP4 E00630 0 +OP4 E00631 0 +OP4 E00632 0 +OP4 E00633 0 +OP4 E00634 0 +OP4 E00635 0 +OP4 E00636 0 +OP4 E00637 0 +OP4 E00638 0 +OP4 E00639 0 +OP4 E0063A 0 +OP4 E0063B 0 +OP4 E0063C 0 +OP4 E0063D 0 +OP4 E0063E 0 +OP4 E0063F 0 +OP4 E00640 0 +OP4 E00641 0 +OP4 E00642 0 +OP4 E00643 0 +OP4 E00644 0 +OP4 E00645 0 +OP4 E00646 0 +OP4 E00647 0 +OP4 E00648 0 +OP4 E00649 0 +OP4 E0064A 0 +OP4 E0064B 0 +OP4 E0064C 0 +OP4 E0064D 0 +OP4 E0064E 0 +OP4 E0064F 0 +OP4 E00650 0 +OP4 E00651 0 +OP4 E00652 0 +OP4 E00653 0 +OP4 E00654 0 +OP4 E00655 0 +OP4 E00656 0 +OP4 E00657 0 +OP4 E00658 0 +OP4 E00659 0 +OP4 E0065A 0 +OP4 E0065B 0 +OP4 E0065C 0 +OP4 E0065D 0 +OP4 E0065E 0 +OP4 E0065F 0 +OP4 E00660 0 +OP4 E00661 0 +OP4 E00662 0 +OP4 E00663 0 +OP4 E00664 0 +OP4 E00665 0 +OP4 E00666 0 +OP4 E00667 0 +OP4 E00668 0 +OP4 E00669 0 +OP4 E0066A 0 +OP4 E0066B 0 +OP4 E0066C 0 +OP4 E0066D 0 +OP4 E0066E 0 +OP4 E0066F 0 +OP4 E00670 0 +OP4 E00671 0 +OP4 E00672 0 +OP4 E00673 0 +OP4 E00674 0 +OP4 E00675 0 +OP4 E00676 0 +OP4 E00677 0 +OP4 E00678 0 +OP4 E00679 0 +OP4 E0067A 0 +OP4 E0067B 0 +OP4 E0067C 0 +OP4 E0067D 0 +OP4 E0067E 0 +OP4 E0067F 0 +OP4 E00680 0 +OP4 E00681 0 +OP4 E00682 0 +OP4 E00683 0 +OP4 E00684 0 +OP4 E00685 0 +OP4 E00686 0 +OP4 E00687 0 +OP4 E00688 0 +OP4 E00689 0 +OP4 E0068A 0 +OP4 E0068B 0 +OP4 E0068C 0 +OP4 E0068D 0 +OP4 E0068E 0 +OP4 E0068F 0 +OP4 E00690 0 +OP4 E00691 0 +OP4 E00692 0 +OP4 E00693 0 +OP4 E00694 0 +OP4 E00695 0 +OP4 E00696 0 +OP4 E00697 0 +OP4 E00698 0 +OP4 E00699 0 +OP4 E0069A 0 +OP4 E0069B 0 +OP4 E0069C 0 +OP4 E0069D 0 +OP4 E0069E 0 +OP4 E0069F 0 +OP4 E006A0 0 +OP4 E006A1 0 +OP4 E006A2 0 +OP4 E006A3 0 +OP4 E006A4 0 +OP4 E006A5 0 +OP4 E006A6 0 +OP4 E006A7 0 +OP4 E006A8 0 +OP4 E006A9 0 +OP4 E006AA 0 +OP4 E006AB 0 +OP4 E006AC 0 +OP4 E006AD 0 +OP4 E006AE 0 +OP4 E006AF 0 +OP4 E006B0 0 +OP4 E006B1 0 +OP4 E006B2 0 +OP4 E006B3 0 +OP4 E006B4 0 +OP4 E006B5 0 +OP4 E006B6 0 +OP4 E006B7 0 +OP4 E006B8 0 +OP4 E006B9 0 +OP4 E006BA 0 +OP4 E006BB 0 +OP4 E006BC 0 +OP4 E006BD 0 +OP4 E006BE 0 +OP4 E006BF 0 +OP4 E006C0 0 +OP4 E006C1 0 +OP4 E006C2 0 +OP4 E006C3 0 +OP4 E006C4 0 +OP4 E006C5 0 +OP4 E006C6 0 +OP4 E006C7 0 +OP4 E006C8 0 +OP4 E006C9 0 +OP4 E006CA 0 +OP4 E006CB 0 +OP4 E006CC 0 +OP4 E006CD 0 +OP4 E006CE 0 +OP4 E006CF 0 +OP4 E006D0 0 +OP4 E006D1 0 +OP4 E006D2 0 +OP4 E006D3 0 +OP4 E006D4 0 +OP4 E006D5 0 +OP4 E006D6 0 +OP4 E006D7 0 +OP4 E006D8 0 +OP4 E006D9 0 +OP4 E006DA 0 +OP4 E006DB 0 +OP4 E006DC 0 +OP4 E006DD 0 +OP4 E006DE 0 +OP4 E006DF 0 +OP4 E006E0 0 +OP4 E006E1 0 +OP4 E006E2 0 +OP4 E006E3 0 +OP4 E006E4 0 +OP4 E006E5 0 +OP4 E006E6 0 +OP4 E006E7 0 +OP4 E006E8 0 +OP4 E006E9 0 +OP4 E006EA 0 +OP4 E006EB 0 +OP4 E006EC 0 +OP4 E006ED 0 +OP4 E006EE 0 +OP4 E006EF 0 +OP4 E006F0 0 +OP4 E006F1 0 +OP4 E006F2 0 +OP4 E006F3 0 +OP4 E006F4 0 +OP4 E006F5 0 +OP4 E006F6 0 +OP4 E006F7 0 +OP4 E006F8 0 +OP4 E006F9 0 +OP4 E006FA 0 +OP4 E006FB 0 +OP4 E006FC 0 +OP4 E006FD 0 +OP4 E006FE 0 +OP4 E006FF 0 +OP4 E00700 0 +OP4 E00701 0 +OP4 E00702 0 +OP4 E00703 0 +OP4 E00704 0 +OP4 E00705 0 +OP4 E00706 0 +OP4 E00707 0 +OP4 E00708 0 +OP4 E00709 0 +OP4 E0070A 0 +OP4 E0070B 0 +OP4 E0070C 0 +OP4 E0070D 0 +OP4 E0070E 0 +OP4 E0070F 0 +OP4 E00710 0 +OP4 E00711 0 +OP4 E00712 0 +OP4 E00713 0 +OP4 E00714 0 +OP4 E00715 0 +OP4 E00716 0 +OP4 E00717 0 +OP4 E00718 0 +OP4 E00719 0 +OP4 E0071A 0 +OP4 E0071B 0 +OP4 E0071C 0 +OP4 E0071D 0 +OP4 E0071E 0 +OP4 E0071F 0 +OP4 E00720 0 +OP4 E00721 0 +OP4 E00722 0 +OP4 E00723 0 +OP4 E00724 0 +OP4 E00725 0 +OP4 E00726 0 +OP4 E00727 0 +OP4 E00728 0 +OP4 E00729 0 +OP4 E0072A 0 +OP4 E0072B 0 +OP4 E0072C 0 +OP4 E0072D 0 +OP4 E0072E 0 +OP4 E0072F 0 +OP4 E00730 0 +OP4 E00731 0 +OP4 E00732 0 +OP4 E00733 0 +OP4 E00734 0 +OP4 E00735 0 +OP4 E00736 0 +OP4 E00737 0 +OP4 E00738 0 +OP4 E00739 0 +OP4 E0073A 0 +OP4 E0073B 0 +OP4 E0073C 0 +OP4 E0073D 0 +OP4 E0073E 0 +OP4 E0073F 0 +OP4 E00740 0 +OP4 E00741 0 +OP4 E00742 0 +OP4 E00743 0 +OP4 E00744 0 +OP4 E00745 0 +OP4 E00746 0 +OP4 E00747 0 +OP4 E00748 0 +OP4 E00749 0 +OP4 E0074A 0 +OP4 E0074B 0 +OP4 E0074C 0 +OP4 E0074D 0 +OP4 E0074E 0 +OP4 E0074F 0 +OP4 E00750 0 +OP4 E00751 0 +OP4 E00752 0 +OP4 E00753 0 +OP4 E00754 0 +OP4 E00755 0 +OP4 E00756 0 +OP4 E00757 0 +OP4 E00758 0 +OP4 E00759 0 +OP4 E0075A 0 +OP4 E0075B 0 +OP4 E0075C 0 +OP4 E0075D 0 +OP4 E0075E 0 +OP4 E0075F 0 +OP4 E00760 0 +OP4 E00761 0 +OP4 E00762 0 +OP4 E00763 0 +OP4 E00764 0 +OP4 E00765 0 +OP4 E00766 0 +OP4 E00767 0 +OP4 E00768 0 +OP4 E00769 0 +OP4 E0076A 0 +OP4 E0076B 0 +OP4 E0076C 0 +OP4 E0076D 0 +OP4 E0076E 0 +OP4 E0076F 0 +OP4 E00770 0 +OP4 E00771 0 +OP4 E00772 0 +OP4 E00773 0 +OP4 E00774 0 +OP4 E00775 0 +OP4 E00776 0 +OP4 E00777 0 +OP4 E00778 0 +OP4 E00779 0 +OP4 E0077A 0 +OP4 E0077B 0 +OP4 E0077C 0 +OP4 E0077D 0 +OP4 E0077E 0 +OP4 E0077F 0 +OP4 E00780 0 +OP4 E00781 0 +OP4 E00782 0 +OP4 E00783 0 +OP4 E00784 0 +OP4 E00785 0 +OP4 E00786 0 +OP4 E00787 0 +OP4 E00788 0 +OP4 E00789 0 +OP4 E0078A 0 +OP4 E0078B 0 +OP4 E0078C 0 +OP4 E0078D 0 +OP4 E0078E 0 +OP4 E0078F 0 +OP4 E00790 0 +OP4 E00791 0 +OP4 E00792 0 +OP4 E00793 0 +OP4 E00794 0 +OP4 E00795 0 +OP4 E00796 0 +OP4 E00797 0 +OP4 E00798 0 +OP4 E00799 0 +OP4 E0079A 0 +OP4 E0079B 0 +OP4 E0079C 0 +OP4 E0079D 0 +OP4 E0079E 0 +OP4 E0079F 0 +OP4 E007A0 0 +OP4 E007A1 0 +OP4 E007A2 0 +OP4 E007A3 0 +OP4 E007A4 0 +OP4 E007A5 0 +OP4 E007A6 0 +OP4 E007A7 0 +OP4 E007A8 0 +OP4 E007A9 0 +OP4 E007AA 0 +OP4 E007AB 0 +OP4 E007AC 0 +OP4 E007AD 0 +OP4 E007AE 0 +OP4 E007AF 0 +OP4 E007B0 0 +OP4 E007B1 0 +OP4 E007B2 0 +OP4 E007B3 0 +OP4 E007B4 0 +OP4 E007B5 0 +OP4 E007B6 0 +OP4 E007B7 0 +OP4 E007B8 0 +OP4 E007B9 0 +OP4 E007BA 0 +OP4 E007BB 0 +OP4 E007BC 0 +OP4 E007BD 0 +OP4 E007BE 0 +OP4 E007BF 0 +OP4 E007C0 0 +OP4 E007C1 0 +OP4 E007C2 0 +OP4 E007C3 0 +OP4 E007C4 0 +OP4 E007C5 0 +OP4 E007C6 0 +OP4 E007C7 0 +OP4 E007C8 0 +OP4 E007C9 0 +OP4 E007CA 0 +OP4 E007CB 0 +OP4 E007CC 0 +OP4 E007CD 0 +OP4 E007CE 0 +OP4 E007CF 0 +OP4 E007D0 0 +OP4 E007D1 0 +OP4 E007D2 0 +OP4 E007D3 0 +OP4 E007D4 0 +OP4 E007D5 0 +OP4 E007D6 0 +OP4 E007D7 0 +OP4 E007D8 0 +OP4 E007D9 0 +OP4 E007DA 0 +OP4 E007DB 0 +OP4 E007DC 0 +OP4 E007DD 0 +OP4 E007DE 0 +OP4 E007DF 0 +OP4 E007E0 0 +OP4 E007E1 0 +OP4 E007E2 0 +OP4 E007E3 0 +OP4 E007E4 0 +OP4 E007E5 0 +OP4 E007E6 0 +OP4 E007E7 0 +OP4 E007E8 0 +OP4 E007E9 0 +OP4 E007EA 0 +OP4 E007EB 0 +OP4 E007EC 0 +OP4 E007ED 0 +OP4 E007EE 0 +OP4 E007EF 0 +OP4 E007F0 0 +OP4 E007F1 0 +OP4 E007F2 0 +OP4 E007F3 0 +OP4 E007F4 0 +OP4 E007F5 0 +OP4 E007F6 0 +OP4 E007F7 0 +OP4 E007F8 0 +OP4 E007F9 0 +OP4 E007FA 0 +OP4 E007FB 0 +OP4 E007FC 0 +OP4 E007FD 0 +OP4 E007FE 0 +OP4 E007FF 0 +OP4 E00800 0 +OP4 E00801 0 +OP4 E00802 0 +OP4 E00803 0 +OP4 E00804 0 +OP4 E00805 0 +OP4 E00806 0 +OP4 E00807 0 +OP4 E00808 0 +OP4 E00809 0 +OP4 E0080A 0 +OP4 E0080B 0 +OP4 E0080C 0 +OP4 E0080D 0 +OP4 E0080E 0 +OP4 E0080F 0 +OP4 E00810 0 +OP4 E00811 0 +OP4 E00812 0 +OP4 E00813 0 +OP4 E00814 0 +OP4 E00815 0 +OP4 E00816 0 +OP4 E00817 0 +OP4 E00818 0 +OP4 E00819 0 +OP4 E0081A 0 +OP4 E0081B 0 +OP4 E0081C 0 +OP4 E0081D 0 +OP4 E0081E 0 +OP4 E0081F 0 +OP4 E00820 0 +OP4 E00821 0 +OP4 E00822 0 +OP4 E00823 0 +OP4 E00824 0 +OP4 E00825 0 +OP4 E00826 0 +OP4 E00827 0 +OP4 E00828 0 +OP4 E00829 0 +OP4 E0082A 0 +OP4 E0082B 0 +OP4 E0082C 0 +OP4 E0082D 0 +OP4 E0082E 0 +OP4 E0082F 0 +OP4 E00830 0 +OP4 E00831 0 +OP4 E00832 0 +OP4 E00833 0 +OP4 E00834 0 +OP4 E00835 0 +OP4 E00836 0 +OP4 E00837 0 +OP4 E00838 0 +OP4 E00839 0 +OP4 E0083A 0 +OP4 E0083B 0 +OP4 E0083C 0 +OP4 E0083D 0 +OP4 E0083E 0 +OP4 E0083F 0 +OP4 E00840 0 +OP4 E00841 0 +OP4 E00842 0 +OP4 E00843 0 +OP4 E00844 0 +OP4 E00845 0 +OP4 E00846 0 +OP4 E00847 0 +OP4 E00848 0 +OP4 E00849 0 +OP4 E0084A 0 +OP4 E0084B 0 +OP4 E0084C 0 +OP4 E0084D 0 +OP4 E0084E 0 +OP4 E0084F 0 +OP4 E00850 0 +OP4 E00851 0 +OP4 E00852 0 +OP4 E00853 0 +OP4 E00854 0 +OP4 E00855 0 +OP4 E00856 0 +OP4 E00857 0 +OP4 E00858 0 +OP4 E00859 0 +OP4 E0085A 0 +OP4 E0085B 0 +OP4 E0085C 0 +OP4 E0085D 0 +OP4 E0085E 0 +OP4 E0085F 0 +OP4 E00860 0 +OP4 E00861 0 +OP4 E00862 0 +OP4 E00863 0 +OP4 E00864 0 +OP4 E00865 0 +OP4 E00866 0 +OP4 E00867 0 +OP4 E00868 0 +OP4 E00869 0 +OP4 E0086A 0 +OP4 E0086B 0 +OP4 E0086C 0 +OP4 E0086D 0 +OP4 E0086E 0 +OP4 E0086F 0 +OP4 E00870 0 +OP4 E00871 0 +OP4 E00872 0 +OP4 E00873 0 +OP4 E00874 0 +OP4 E00875 0 +OP4 E00876 0 +OP4 E00877 0 +OP4 E00878 0 +OP4 E00879 0 +OP4 E0087A 0 +OP4 E0087B 0 +OP4 E0087C 0 +OP4 E0087D 0 +OP4 E0087E 0 +OP4 E0087F 0 +OP4 E00880 0 +OP4 E00881 0 +OP4 E00882 0 +OP4 E00883 0 +OP4 E00884 0 +OP4 E00885 0 +OP4 E00886 0 +OP4 E00887 0 +OP4 E00888 0 +OP4 E00889 0 +OP4 E0088A 0 +OP4 E0088B 0 +OP4 E0088C 0 +OP4 E0088D 0 +OP4 E0088E 0 +OP4 E0088F 0 +OP4 E00890 0 +OP4 E00891 0 +OP4 E00892 0 +OP4 E00893 0 +OP4 E00894 0 +OP4 E00895 0 +OP4 E00896 0 +OP4 E00897 0 +OP4 E00898 0 +OP4 E00899 0 +OP4 E0089A 0 +OP4 E0089B 0 +OP4 E0089C 0 +OP4 E0089D 0 +OP4 E0089E 0 +OP4 E0089F 0 +OP4 E008A0 0 +OP4 E008A1 0 +OP4 E008A2 0 +OP4 E008A3 0 +OP4 E008A4 0 +OP4 E008A5 0 +OP4 E008A6 0 +OP4 E008A7 0 +OP4 E008A8 0 +OP4 E008A9 0 +OP4 E008AA 0 +OP4 E008AB 0 +OP4 E008AC 0 +OP4 E008AD 0 +OP4 E008AE 0 +OP4 E008AF 0 +OP4 E008B0 0 +OP4 E008B1 0 +OP4 E008B2 0 +OP4 E008B3 0 +OP4 E008B4 0 +OP4 E008B5 0 +OP4 E008B6 0 +OP4 E008B7 0 +OP4 E008B8 0 +OP4 E008B9 0 +OP4 E008BA 0 +OP4 E008BB 0 +OP4 E008BC 0 +OP4 E008BD 0 +OP4 E008BE 0 +OP4 E008BF 0 +OP4 E008C0 0 +OP4 E008C1 0 +OP4 E008C2 0 +OP4 E008C3 0 +OP4 E008C4 0 +OP4 E008C5 0 +OP4 E008C6 0 +OP4 E008C7 0 +OP4 E008C8 0 +OP4 E008C9 0 +OP4 E008CA 0 +OP4 E008CB 0 +OP4 E008CC 0 +OP4 E008CD 0 +OP4 E008CE 0 +OP4 E008CF 0 +OP4 E008D0 0 +OP4 E008D1 0 +OP4 E008D2 0 +OP4 E008D3 0 +OP4 E008D4 0 +OP4 E008D5 0 +OP4 E008D6 0 +OP4 E008D7 0 +OP4 E008D8 0 +OP4 E008D9 0 +OP4 E008DA 0 +OP4 E008DB 0 +OP4 E008DC 0 +OP4 E008DD 0 +OP4 E008DE 0 +OP4 E008DF 0 +OP4 E008E0 0 +OP4 E008E1 0 +OP4 E008E2 0 +OP4 E008E3 0 +OP4 E008E4 0 +OP4 E008E5 0 +OP4 E008E6 0 +OP4 E008E7 0 +OP4 E008E8 0 +OP4 E008E9 0 +OP4 E008EA 0 +OP4 E008EB 0 +OP4 E008EC 0 +OP4 E008ED 0 +OP4 E008EE 0 +OP4 E008EF 0 +OP4 E008F0 0 +OP4 E008F1 0 +OP4 E008F2 0 +OP4 E008F3 0 +OP4 E008F4 0 +OP4 E008F5 0 +OP4 E008F6 0 +OP4 E008F7 0 +OP4 E008F8 0 +OP4 E008F9 0 +OP4 E008FA 0 +OP4 E008FB 0 +OP4 E008FC 0 +OP4 E008FD 0 +OP4 E008FE 0 +OP4 E008FF 0 +OP4 E00900 0 +OP4 E00901 0 +OP4 E00902 0 +OP4 E00903 0 +OP4 E00904 0 +OP4 E00905 0 +OP4 E00906 0 +OP4 E00907 0 +OP4 E00908 0 +OP4 E00909 0 +OP4 E0090A 0 +OP4 E0090B 0 +OP4 E0090C 0 +OP4 E0090D 0 +OP4 E0090E 0 +OP4 E0090F 0 +OP4 E00910 0 +OP4 E00911 0 +OP4 E00912 0 +OP4 E00913 0 +OP4 E00914 0 +OP4 E00915 0 +OP4 E00916 0 +OP4 E00917 0 +OP4 E00918 0 +OP4 E00919 0 +OP4 E0091A 0 +OP4 E0091B 0 +OP4 E0091C 0 +OP4 E0091D 0 +OP4 E0091E 0 +OP4 E0091F 0 +OP4 E00920 0 +OP4 E00921 0 +OP4 E00922 0 +OP4 E00923 0 +OP4 E00924 0 +OP4 E00925 0 +OP4 E00926 0 +OP4 E00927 0 +OP4 E00928 0 +OP4 E00929 0 +OP4 E0092A 0 +OP4 E0092B 0 +OP4 E0092C 0 +OP4 E0092D 0 +OP4 E0092E 0 +OP4 E0092F 0 +OP4 E00930 0 +OP4 E00931 0 +OP4 E00932 0 +OP4 E00933 0 +OP4 E00934 0 +OP4 E00935 0 +OP4 E00936 0 +OP4 E00937 0 +OP4 E00938 0 +OP4 E00939 0 +OP4 E0093A 0 +OP4 E0093B 0 +OP4 E0093C 0 +OP4 E0093D 0 +OP4 E0093E 0 +OP4 E0093F 0 +OP4 E00940 0 +OP4 E00941 0 +OP4 E00942 0 +OP4 E00943 0 +OP4 E00944 0 +OP4 E00945 0 +OP4 E00946 0 +OP4 E00947 0 +OP4 E00948 0 +OP4 E00949 0 +OP4 E0094A 0 +OP4 E0094B 0 +OP4 E0094C 0 +OP4 E0094D 0 +OP4 E0094E 0 +OP4 E0094F 0 +OP4 E00950 0 +OP4 E00951 0 +OP4 E00952 0 +OP4 E00953 0 +OP4 E00954 0 +OP4 E00955 0 +OP4 E00956 0 +OP4 E00957 0 +OP4 E00958 0 +OP4 E00959 0 +OP4 E0095A 0 +OP4 E0095B 0 +OP4 E0095C 0 +OP4 E0095D 0 +OP4 E0095E 0 +OP4 E0095F 0 +OP4 E00960 0 +OP4 E00961 0 +OP4 E00962 0 +OP4 E00963 0 +OP4 E00964 0 +OP4 E00965 0 +OP4 E00966 0 +OP4 E00967 0 +OP4 E00968 0 +OP4 E00969 0 +OP4 E0096A 0 +OP4 E0096B 0 +OP4 E0096C 0 +OP4 E0096D 0 +OP4 E0096E 0 +OP4 E0096F 0 +OP4 E00970 0 +OP4 E00971 0 +OP4 E00972 0 +OP4 E00973 0 +OP4 E00974 0 +OP4 E00975 0 +OP4 E00976 0 +OP4 E00977 0 +OP4 E00978 0 +OP4 E00979 0 +OP4 E0097A 0 +OP4 E0097B 0 +OP4 E0097C 0 +OP4 E0097D 0 +OP4 E0097E 0 +OP4 E0097F 0 +OP4 E00980 0 +OP4 E00981 0 +OP4 E00982 0 +OP4 E00983 0 +OP4 E00984 0 +OP4 E00985 0 +OP4 E00986 0 +OP4 E00987 0 +OP4 E00988 0 +OP4 E00989 0 +OP4 E0098A 0 +OP4 E0098B 0 +OP4 E0098C 0 +OP4 E0098D 0 +OP4 E0098E 0 +OP4 E0098F 0 +OP4 E00990 0 +OP4 E00991 0 +OP4 E00992 0 +OP4 E00993 0 +OP4 E00994 0 +OP4 E00995 0 +OP4 E00996 0 +OP4 E00997 0 +OP4 E00998 0 +OP4 E00999 0 +OP4 E0099A 0 +OP4 E0099B 0 +OP4 E0099C 0 +OP4 E0099D 0 +OP4 E0099E 0 +OP4 E0099F 0 +OP4 E009A0 0 +OP4 E009A1 0 +OP4 E009A2 0 +OP4 E009A3 0 +OP4 E009A4 0 +OP4 E009A5 0 +OP4 E009A6 0 +OP4 E009A7 0 +OP4 E009A8 0 +OP4 E009A9 0 +OP4 E009AA 0 +OP4 E009AB 0 +OP4 E009AC 0 +OP4 E009AD 0 +OP4 E009AE 0 +OP4 E009AF 0 +OP4 E009B0 0 +OP4 E009B1 0 +OP4 E009B2 0 +OP4 E009B3 0 +OP4 E009B4 0 +OP4 E009B5 0 +OP4 E009B6 0 +OP4 E009B7 0 +OP4 E009B8 0 +OP4 E009B9 0 +OP4 E009BA 0 +OP4 E009BB 0 +OP4 E009BC 0 +OP4 E009BD 0 +OP4 E009BE 0 +OP4 E009BF 0 +OP4 E009C0 0 +OP4 E009C1 0 +OP4 E009C2 0 +OP4 E009C3 0 +OP4 E009C4 0 +OP4 E009C5 0 +OP4 E009C6 0 +OP4 E009C7 0 +OP4 E009C8 0 +OP4 E009C9 0 +OP4 E009CA 0 +OP4 E009CB 0 +OP4 E009CC 0 +OP4 E009CD 0 +OP4 E009CE 0 +OP4 E009CF 0 +OP4 E009D0 0 +OP4 E009D1 0 +OP4 E009D2 0 +OP4 E009D3 0 +OP4 E009D4 0 +OP4 E009D5 0 +OP4 E009D6 0 +OP4 E009D7 0 +OP4 E009D8 0 +OP4 E009D9 0 +OP4 E009DA 0 +OP4 E009DB 0 +OP4 E009DC 0 +OP4 E009DD 0 +OP4 E009DE 0 +OP4 E009DF 0 +OP4 E009E0 0 +OP4 E009E1 0 +OP4 E009E2 0 +OP4 E009E3 0 +OP4 E009E4 0 +OP4 E009E5 0 +OP4 E009E6 0 +OP4 E009E7 0 +OP4 E009E8 0 +OP4 E009E9 0 +OP4 E009EA 0 +OP4 E009EB 0 +OP4 E009EC 0 +OP4 E009ED 0 +OP4 E009EE 0 +OP4 E009EF 0 +OP4 E009F0 0 +OP4 E009F1 0 +OP4 E009F2 0 +OP4 E009F3 0 +OP4 E009F4 0 +OP4 E009F5 0 +OP4 E009F6 0 +OP4 E009F7 0 +OP4 E009F8 0 +OP4 E009F9 0 +OP4 E009FA 0 +OP4 E009FB 0 +OP4 E009FC 0 +OP4 E009FD 0 +OP4 E009FE 0 +OP4 E009FF 0 +OP4 E00A00 0 +OP4 E00A01 0 +OP4 E00A02 0 +OP4 E00A03 0 +OP4 E00A04 0 +OP4 E00A05 0 +OP4 E00A06 0 +OP4 E00A07 0 +OP4 E00A08 0 +OP4 E00A09 0 +OP4 E00A0A 0 +OP4 E00A0B 0 +OP4 E00A0C 0 +OP4 E00A0D 0 +OP4 E00A0E 0 +OP4 E00A0F 0 +OP4 E00A10 0 +OP4 E00A11 0 +OP4 E00A12 0 +OP4 E00A13 0 +OP4 E00A14 0 +OP4 E00A15 0 +OP4 E00A16 0 +OP4 E00A17 0 +OP4 E00A18 0 +OP4 E00A19 0 +OP4 E00A1A 0 +OP4 E00A1B 0 +OP4 E00A1C 0 +OP4 E00A1D 0 +OP4 E00A1E 0 +OP4 E00A1F 0 +OP4 E00A20 0 +OP4 E00A21 0 +OP4 E00A22 0 +OP4 E00A23 0 +OP4 E00A24 0 +OP4 E00A25 0 +OP4 E00A26 0 +OP4 E00A27 0 +OP4 E00A28 0 +OP4 E00A29 0 +OP4 E00A2A 0 +OP4 E00A2B 0 +OP4 E00A2C 0 +OP4 E00A2D 0 +OP4 E00A2E 0 +OP4 E00A2F 0 +OP4 E00A30 0 +OP4 E00A31 0 +OP4 E00A32 0 +OP4 E00A33 0 +OP4 E00A34 0 +OP4 E00A35 0 +OP4 E00A36 0 +OP4 E00A37 0 +OP4 E00A38 0 +OP4 E00A39 0 +OP4 E00A3A 0 +OP4 E00A3B 0 +OP4 E00A3C 0 +OP4 E00A3D 0 +OP4 E00A3E 0 +OP4 E00A3F 0 +OP4 E00A40 0 +OP4 E00A41 0 +OP4 E00A42 0 +OP4 E00A43 0 +OP4 E00A44 0 +OP4 E00A45 0 +OP4 E00A46 0 +OP4 E00A47 0 +OP4 E00A48 0 +OP4 E00A49 0 +OP4 E00A4A 0 +OP4 E00A4B 0 +OP4 E00A4C 0 +OP4 E00A4D 0 +OP4 E00A4E 0 +OP4 E00A4F 0 +OP4 E00A50 0 +OP4 E00A51 0 +OP4 E00A52 0 +OP4 E00A53 0 +OP4 E00A54 0 +OP4 E00A55 0 +OP4 E00A56 0 +OP4 E00A57 0 +OP4 E00A58 0 +OP4 E00A59 0 +OP4 E00A5A 0 +OP4 E00A5B 0 +OP4 E00A5C 0 +OP4 E00A5D 0 +OP4 E00A5E 0 +OP4 E00A5F 0 +OP4 E00A60 0 +OP4 E00A61 0 +OP4 E00A62 0 +OP4 E00A63 0 +OP4 E00A64 0 +OP4 E00A65 0 +OP4 E00A66 0 +OP4 E00A67 0 +OP4 E00A68 0 +OP4 E00A69 0 +OP4 E00A6A 0 +OP4 E00A6B 0 +OP4 E00A6C 0 +OP4 E00A6D 0 +OP4 E00A6E 0 +OP4 E00A6F 0 +OP4 E00A70 0 +OP4 E00A71 0 +OP4 E00A72 0 +OP4 E00A73 0 +OP4 E00A74 0 +OP4 E00A75 0 +OP4 E00A76 0 +OP4 E00A77 0 +OP4 E00A78 0 +OP4 E00A79 0 +OP4 E00A7A 0 +OP4 E00A7B 0 +OP4 E00A7C 0 +OP4 E00A7D 0 +OP4 E00A7E 0 +OP4 E00A7F 0 +OP4 E00A80 0 +OP4 E00A81 0 +OP4 E00A82 0 +OP4 E00A83 0 +OP4 E00A84 0 +OP4 E00A85 0 +OP4 E00A86 0 +OP4 E00A87 0 +OP4 E00A88 0 +OP4 E00A89 0 +OP4 E00A8A 0 +OP4 E00A8B 0 +OP4 E00A8C 0 +OP4 E00A8D 0 +OP4 E00A8E 0 +OP4 E00A8F 0 +OP4 E00A90 0 +OP4 E00A91 0 +OP4 E00A92 0 +OP4 E00A93 0 +OP4 E00A94 0 +OP4 E00A95 0 +OP4 E00A96 0 +OP4 E00A97 0 +OP4 E00A98 0 +OP4 E00A99 0 +OP4 E00A9A 0 +OP4 E00A9B 0 +OP4 E00A9C 0 +OP4 E00A9D 0 +OP4 E00A9E 0 +OP4 E00A9F 0 +OP4 E00AA0 0 +OP4 E00AA1 0 +OP4 E00AA2 0 +OP4 E00AA3 0 +OP4 E00AA4 0 +OP4 E00AA5 0 +OP4 E00AA6 0 +OP4 E00AA7 0 +OP4 E00AA8 0 +OP4 E00AA9 0 +OP4 E00AAA 0 +OP4 E00AAB 0 +OP4 E00AAC 0 +OP4 E00AAD 0 +OP4 E00AAE 0 +OP4 E00AAF 0 +OP4 E00AB0 0 +OP4 E00AB1 0 +OP4 E00AB2 0 +OP4 E00AB3 0 +OP4 E00AB4 0 +OP4 E00AB5 0 +OP4 E00AB6 0 +OP4 E00AB7 0 +OP4 E00AB8 0 +OP4 E00AB9 0 +OP4 E00ABA 0 +OP4 E00ABB 0 +OP4 E00ABC 0 +OP4 E00ABD 0 +OP4 E00ABE 0 +OP4 E00ABF 0 +OP4 E00AC0 0 +OP4 E00AC1 0 +OP4 E00AC2 0 +OP4 E00AC3 0 +OP4 E00AC4 0 +OP4 E00AC5 0 +OP4 E00AC6 0 +OP4 E00AC7 0 +OP4 E00AC8 0 +OP4 E00AC9 0 +OP4 E00ACA 0 +OP4 E00ACB 0 +OP4 E00ACC 0 +OP4 E00ACD 0 +OP4 E00ACE 0 +OP4 E00ACF 0 +OP4 E00AD0 0 +OP4 E00AD1 0 +OP4 E00AD2 0 +OP4 E00AD3 0 +OP4 E00AD4 0 +OP4 E00AD5 0 +OP4 E00AD6 0 +OP4 E00AD7 0 +OP4 E00AD8 0 +OP4 E00AD9 0 +OP4 E00ADA 0 +OP4 E00ADB 0 +OP4 E00ADC 0 +OP4 E00ADD 0 +OP4 E00ADE 0 +OP4 E00ADF 0 +OP4 E00AE0 0 +OP4 E00AE1 0 +OP4 E00AE2 0 +OP4 E00AE3 0 +OP4 E00AE4 0 +OP4 E00AE5 0 +OP4 E00AE6 0 +OP4 E00AE7 0 +OP4 E00AE8 0 +OP4 E00AE9 0 +OP4 E00AEA 0 +OP4 E00AEB 0 +OP4 E00AEC 0 +OP4 E00AED 0 +OP4 E00AEE 0 +OP4 E00AEF 0 +OP4 E00AF0 0 +OP4 E00AF1 0 +OP4 E00AF2 0 +OP4 E00AF3 0 +OP4 E00AF4 0 +OP4 E00AF5 0 +OP4 E00AF6 0 +OP4 E00AF7 0 +OP4 E00AF8 0 +OP4 E00AF9 0 +OP4 E00AFA 0 +OP4 E00AFB 0 +OP4 E00AFC 0 +OP4 E00AFD 0 +OP4 E00AFE 0 +OP4 E00AFF 0 +OP4 E00B00 0 +OP4 E00B01 0 +OP4 E00B02 0 +OP4 E00B03 0 +OP4 E00B04 0 +OP4 E00B05 0 +OP4 E00B06 0 +OP4 E00B07 0 +OP4 E00B08 0 +OP4 E00B09 0 +OP4 E00B0A 0 +OP4 E00B0B 0 +OP4 E00B0C 0 +OP4 E00B0D 0 +OP4 E00B0E 0 +OP4 E00B0F 0 +OP4 E00B10 0 +OP4 E00B11 0 +OP4 E00B12 0 +OP4 E00B13 0 +OP4 E00B14 0 +OP4 E00B15 0 +OP4 E00B16 0 +OP4 E00B17 0 +OP4 E00B18 0 +OP4 E00B19 0 +OP4 E00B1A 0 +OP4 E00B1B 0 +OP4 E00B1C 0 +OP4 E00B1D 0 +OP4 E00B1E 0 +OP4 E00B1F 0 +OP4 E00B20 0 +OP4 E00B21 0 +OP4 E00B22 0 +OP4 E00B23 0 +OP4 E00B24 0 +OP4 E00B25 0 +OP4 E00B26 0 +OP4 E00B27 0 +OP4 E00B28 0 +OP4 E00B29 0 +OP4 E00B2A 0 +OP4 E00B2B 0 +OP4 E00B2C 0 +OP4 E00B2D 0 +OP4 E00B2E 0 +OP4 E00B2F 0 +OP4 E00B30 0 +OP4 E00B31 0 +OP4 E00B32 0 +OP4 E00B33 0 +OP4 E00B34 0 +OP4 E00B35 0 +OP4 E00B36 0 +OP4 E00B37 0 +OP4 E00B38 0 +OP4 E00B39 0 +OP4 E00B3A 0 +OP4 E00B3B 0 +OP4 E00B3C 0 +OP4 E00B3D 0 +OP4 E00B3E 0 +OP4 E00B3F 0 +OP4 E00B40 0 +OP4 E00B41 0 +OP4 E00B42 0 +OP4 E00B43 0 +OP4 E00B44 0 +OP4 E00B45 0 +OP4 E00B46 0 +OP4 E00B47 0 +OP4 E00B48 0 +OP4 E00B49 0 +OP4 E00B4A 0 +OP4 E00B4B 0 +OP4 E00B4C 0 +OP4 E00B4D 0 +OP4 E00B4E 0 +OP4 E00B4F 0 +OP4 E00B50 0 +OP4 E00B51 0 +OP4 E00B52 0 +OP4 E00B53 0 +OP4 E00B54 0 +OP4 E00B55 0 +OP4 E00B56 0 +OP4 E00B57 0 +OP4 E00B58 0 +OP4 E00B59 0 +OP4 E00B5A 0 +OP4 E00B5B 0 +OP4 E00B5C 0 +OP4 E00B5D 0 +OP4 E00B5E 0 +OP4 E00B5F 0 +OP4 E00B60 0 +OP4 E00B61 0 +OP4 E00B62 0 +OP4 E00B63 0 +OP4 E00B64 0 +OP4 E00B65 0 +OP4 E00B66 0 +OP4 E00B67 0 +OP4 E00B68 0 +OP4 E00B69 0 +OP4 E00B6A 0 +OP4 E00B6B 0 +OP4 E00B6C 0 +OP4 E00B6D 0 +OP4 E00B6E 0 +OP4 E00B6F 0 +OP4 E00B70 0 +OP4 E00B71 0 +OP4 E00B72 0 +OP4 E00B73 0 +OP4 E00B74 0 +OP4 E00B75 0 +OP4 E00B76 0 +OP4 E00B77 0 +OP4 E00B78 0 +OP4 E00B79 0 +OP4 E00B7A 0 +OP4 E00B7B 0 +OP4 E00B7C 0 +OP4 E00B7D 0 +OP4 E00B7E 0 +OP4 E00B7F 0 +OP4 E00B80 0 +OP4 E00B81 0 +OP4 E00B82 0 +OP4 E00B83 0 +OP4 E00B84 0 +OP4 E00B85 0 +OP4 E00B86 0 +OP4 E00B87 0 +OP4 E00B88 0 +OP4 E00B89 0 +OP4 E00B8A 0 +OP4 E00B8B 0 +OP4 E00B8C 0 +OP4 E00B8D 0 +OP4 E00B8E 0 +OP4 E00B8F 0 +OP4 E00B90 0 +OP4 E00B91 0 +OP4 E00B92 0 +OP4 E00B93 0 +OP4 E00B94 0 +OP4 E00B95 0 +OP4 E00B96 0 +OP4 E00B97 0 +OP4 E00B98 0 +OP4 E00B99 0 +OP4 E00B9A 0 +OP4 E00B9B 0 +OP4 E00B9C 0 +OP4 E00B9D 0 +OP4 E00B9E 0 +OP4 E00B9F 0 +OP4 E00BA0 0 +OP4 E00BA1 0 +OP4 E00BA2 0 +OP4 E00BA3 0 +OP4 E00BA4 0 +OP4 E00BA5 0 +OP4 E00BA6 0 +OP4 E00BA7 0 +OP4 E00BA8 0 +OP4 E00BA9 0 +OP4 E00BAA 0 +OP4 E00BAB 0 +OP4 E00BAC 0 +OP4 E00BAD 0 +OP4 E00BAE 0 +OP4 E00BAF 0 +OP4 E00BB0 0 +OP4 E00BB1 0 +OP4 E00BB2 0 +OP4 E00BB3 0 +OP4 E00BB4 0 +OP4 E00BB5 0 +OP4 E00BB6 0 +OP4 E00BB7 0 +OP4 E00BB8 0 +OP4 E00BB9 0 +OP4 E00BBA 0 +OP4 E00BBB 0 +OP4 E00BBC 0 +OP4 E00BBD 0 +OP4 E00BBE 0 +OP4 E00BBF 0 +OP4 E00BC0 0 +OP4 E00BC1 0 +OP4 E00BC2 0 +OP4 E00BC3 0 +OP4 E00BC4 0 +OP4 E00BC5 0 +OP4 E00BC6 0 +OP4 E00BC7 0 +OP4 E00BC8 0 +OP4 E00BC9 0 +OP4 E00BCA 0 +OP4 E00BCB 0 +OP4 E00BCC 0 +OP4 E00BCD 0 +OP4 E00BCE 0 +OP4 E00BCF 0 +OP4 E00BD0 0 +OP4 E00BD1 0 +OP4 E00BD2 0 +OP4 E00BD3 0 +OP4 E00BD4 0 +OP4 E00BD5 0 +OP4 E00BD6 0 +OP4 E00BD7 0 +OP4 E00BD8 0 +OP4 E00BD9 0 +OP4 E00BDA 0 +OP4 E00BDB 0 +OP4 E00BDC 0 +OP4 E00BDD 0 +OP4 E00BDE 0 +OP4 E00BDF 0 +OP4 E00BE0 0 +OP4 E00BE1 0 +OP4 E00BE2 0 +OP4 E00BE3 0 +OP4 E00BE4 0 +OP4 E00BE5 0 +OP4 E00BE6 0 +OP4 E00BE7 0 +OP4 E00BE8 0 +OP4 E00BE9 0 +OP4 E00BEA 0 +OP4 E00BEB 0 +OP4 E00BEC 0 +OP4 E00BED 0 +OP4 E00BEE 0 +OP4 E00BEF 0 +OP4 E00BF0 0 +OP4 E00BF1 0 +OP4 E00BF2 0 +OP4 E00BF3 0 +OP4 E00BF4 0 +OP4 E00BF5 0 +OP4 E00BF6 0 +OP4 E00BF7 0 +OP4 E00BF8 0 +OP4 E00BF9 0 +OP4 E00BFA 0 +OP4 E00BFB 0 +OP4 E00BFC 0 +OP4 E00BFD 0 +OP4 E00BFE 0 +OP4 E00BFF 0 +OP4 E00C00 0 +OP4 E00C01 0 +OP4 E00C02 0 +OP4 E00C03 0 +OP4 E00C04 0 +OP4 E00C05 0 +OP4 E00C06 0 +OP4 E00C07 0 +OP4 E00C08 0 +OP4 E00C09 0 +OP4 E00C0A 0 +OP4 E00C0B 0 +OP4 E00C0C 0 +OP4 E00C0D 0 +OP4 E00C0E 0 +OP4 E00C0F 0 +OP4 E00C10 0 +OP4 E00C11 0 +OP4 E00C12 0 +OP4 E00C13 0 +OP4 E00C14 0 +OP4 E00C15 0 +OP4 E00C16 0 +OP4 E00C17 0 +OP4 E00C18 0 +OP4 E00C19 0 +OP4 E00C1A 0 +OP4 E00C1B 0 +OP4 E00C1C 0 +OP4 E00C1D 0 +OP4 E00C1E 0 +OP4 E00C1F 0 +OP4 E00C20 0 +OP4 E00C21 0 +OP4 E00C22 0 +OP4 E00C23 0 +OP4 E00C24 0 +OP4 E00C25 0 +OP4 E00C26 0 +OP4 E00C27 0 +OP4 E00C28 0 +OP4 E00C29 0 +OP4 E00C2A 0 +OP4 E00C2B 0 +OP4 E00C2C 0 +OP4 E00C2D 0 +OP4 E00C2E 0 +OP4 E00C2F 0 +OP4 E00C30 0 +OP4 E00C31 0 +OP4 E00C32 0 +OP4 E00C33 0 +OP4 E00C34 0 +OP4 E00C35 0 +OP4 E00C36 0 +OP4 E00C37 0 +OP4 E00C38 0 +OP4 E00C39 0 +OP4 E00C3A 0 +OP4 E00C3B 0 +OP4 E00C3C 0 +OP4 E00C3D 0 +OP4 E00C3E 0 +OP4 E00C3F 0 +OP4 E00C40 0 +OP4 E00C41 0 +OP4 E00C42 0 +OP4 E00C43 0 +OP4 E00C44 0 +OP4 E00C45 0 +OP4 E00C46 0 +OP4 E00C47 0 +OP4 E00C48 0 +OP4 E00C49 0 +OP4 E00C4A 0 +OP4 E00C4B 0 +OP4 E00C4C 0 +OP4 E00C4D 0 +OP4 E00C4E 0 +OP4 E00C4F 0 +OP4 E00C50 0 +OP4 E00C51 0 +OP4 E00C52 0 +OP4 E00C53 0 +OP4 E00C54 0 +OP4 E00C55 0 +OP4 E00C56 0 +OP4 E00C57 0 +OP4 E00C58 0 +OP4 E00C59 0 +OP4 E00C5A 0 +OP4 E00C5B 0 +OP4 E00C5C 0 +OP4 E00C5D 0 +OP4 E00C5E 0 +OP4 E00C5F 0 +OP4 E00C60 0 +OP4 E00C61 0 +OP4 E00C62 0 +OP4 E00C63 0 +OP4 E00C64 0 +OP4 E00C65 0 +OP4 E00C66 0 +OP4 E00C67 0 +OP4 E00C68 0 +OP4 E00C69 0 +OP4 E00C6A 0 +OP4 E00C6B 0 +OP4 E00C6C 0 +OP4 E00C6D 0 +OP4 E00C6E 0 +OP4 E00C6F 0 +OP4 E00C70 0 +OP4 E00C71 0 +OP4 E00C72 0 +OP4 E00C73 0 +OP4 E00C74 0 +OP4 E00C75 0 +OP4 E00C76 0 +OP4 E00C77 0 +OP4 E00C78 0 +OP4 E00C79 0 +OP4 E00C7A 0 +OP4 E00C7B 0 +OP4 E00C7C 0 +OP4 E00C7D 0 +OP4 E00C7E 0 +OP4 E00C7F 0 +OP4 E00C80 0 +OP4 E00C81 0 +OP4 E00C82 0 +OP4 E00C83 0 +OP4 E00C84 0 +OP4 E00C85 0 +OP4 E00C86 0 +OP4 E00C87 0 +OP4 E00C88 0 +OP4 E00C89 0 +OP4 E00C8A 0 +OP4 E00C8B 0 +OP4 E00C8C 0 +OP4 E00C8D 0 +OP4 E00C8E 0 +OP4 E00C8F 0 +OP4 E00C90 0 +OP4 E00C91 0 +OP4 E00C92 0 +OP4 E00C93 0 +OP4 E00C94 0 +OP4 E00C95 0 +OP4 E00C96 0 +OP4 E00C97 0 +OP4 E00C98 0 +OP4 E00C99 0 +OP4 E00C9A 0 +OP4 E00C9B 0 +OP4 E00C9C 0 +OP4 E00C9D 0 +OP4 E00C9E 0 +OP4 E00C9F 0 +OP4 E00CA0 0 +OP4 E00CA1 0 +OP4 E00CA2 0 +OP4 E00CA3 0 +OP4 E00CA4 0 +OP4 E00CA5 0 +OP4 E00CA6 0 +OP4 E00CA7 0 +OP4 E00CA8 0 +OP4 E00CA9 0 +OP4 E00CAA 0 +OP4 E00CAB 0 +OP4 E00CAC 0 +OP4 E00CAD 0 +OP4 E00CAE 0 +OP4 E00CAF 0 +OP4 E00CB0 0 +OP4 E00CB1 0 +OP4 E00CB2 0 +OP4 E00CB3 0 +OP4 E00CB4 0 +OP4 E00CB5 0 +OP4 E00CB6 0 +OP4 E00CB7 0 +OP4 E00CB8 0 +OP4 E00CB9 0 +OP4 E00CBA 0 +OP4 E00CBB 0 +OP4 E00CBC 0 +OP4 E00CBD 0 +OP4 E00CBE 0 +OP4 E00CBF 0 +OP4 E00CC0 0 +OP4 E00CC1 0 +OP4 E00CC2 0 +OP4 E00CC3 0 +OP4 E00CC4 0 +OP4 E00CC5 0 +OP4 E00CC6 0 +OP4 E00CC7 0 +OP4 E00CC8 0 +OP4 E00CC9 0 +OP4 E00CCA 0 +OP4 E00CCB 0 +OP4 E00CCC 0 +OP4 E00CCD 0 +OP4 E00CCE 0 +OP4 E00CCF 0 +OP4 E00CD0 0 +OP4 E00CD1 0 +OP4 E00CD2 0 +OP4 E00CD3 0 +OP4 E00CD4 0 +OP4 E00CD5 0 +OP4 E00CD6 0 +OP4 E00CD7 0 +OP4 E00CD8 0 +OP4 E00CD9 0 +OP4 E00CDA 0 +OP4 E00CDB 0 +OP4 E00CDC 0 +OP4 E00CDD 0 +OP4 E00CDE 0 +OP4 E00CDF 0 +OP4 E00CE0 0 +OP4 E00CE1 0 +OP4 E00CE2 0 +OP4 E00CE3 0 +OP4 E00CE4 0 +OP4 E00CE5 0 +OP4 E00CE6 0 +OP4 E00CE7 0 +OP4 E00CE8 0 +OP4 E00CE9 0 +OP4 E00CEA 0 +OP4 E00CEB 0 +OP4 E00CEC 0 +OP4 E00CED 0 +OP4 E00CEE 0 +OP4 E00CEF 0 +OP4 E00CF0 0 +OP4 E00CF1 0 +OP4 E00CF2 0 +OP4 E00CF3 0 +OP4 E00CF4 0 +OP4 E00CF5 0 +OP4 E00CF6 0 +OP4 E00CF7 0 +OP4 E00CF8 0 +OP4 E00CF9 0 +OP4 E00CFA 0 +OP4 E00CFB 0 +OP4 E00CFC 0 +OP4 E00CFD 0 +OP4 E00CFE 0 +OP4 E00CFF 0 +OP4 E00D00 0 +OP4 E00D01 0 +OP4 E00D02 0 +OP4 E00D03 0 +OP4 E00D04 0 +OP4 E00D05 0 +OP4 E00D06 0 +OP4 E00D07 0 +OP4 E00D08 0 +OP4 E00D09 0 +OP4 E00D0A 0 +OP4 E00D0B 0 +OP4 E00D0C 0 +OP4 E00D0D 0 +OP4 E00D0E 0 +OP4 E00D0F 0 +OP4 E00D10 0 +OP4 E00D11 0 +OP4 E00D12 0 +OP4 E00D13 0 +OP4 E00D14 0 +OP4 E00D15 0 +OP4 E00D16 0 +OP4 E00D17 0 +OP4 E00D18 0 +OP4 E00D19 0 +OP4 E00D1A 0 +OP4 E00D1B 0 +OP4 E00D1C 0 +OP4 E00D1D 0 +OP4 E00D1E 0 +OP4 E00D1F 0 +OP4 E00D20 0 +OP4 E00D21 0 +OP4 E00D22 0 +OP4 E00D23 0 +OP4 E00D24 0 +OP4 E00D25 0 +OP4 E00D26 0 +OP4 E00D27 0 +OP4 E00D28 0 +OP4 E00D29 0 +OP4 E00D2A 0 +OP4 E00D2B 0 +OP4 E00D2C 0 +OP4 E00D2D 0 +OP4 E00D2E 0 +OP4 E00D2F 0 +OP4 E00D30 0 +OP4 E00D31 0 +OP4 E00D32 0 +OP4 E00D33 0 +OP4 E00D34 0 +OP4 E00D35 0 +OP4 E00D36 0 +OP4 E00D37 0 +OP4 E00D38 0 +OP4 E00D39 0 +OP4 E00D3A 0 +OP4 E00D3B 0 +OP4 E00D3C 0 +OP4 E00D3D 0 +OP4 E00D3E 0 +OP4 E00D3F 0 +OP4 E00D40 0 +OP4 E00D41 0 +OP4 E00D42 0 +OP4 E00D43 0 +OP4 E00D44 0 +OP4 E00D45 0 +OP4 E00D46 0 +OP4 E00D47 0 +OP4 E00D48 0 +OP4 E00D49 0 +OP4 E00D4A 0 +OP4 E00D4B 0 +OP4 E00D4C 0 +OP4 E00D4D 0 +OP4 E00D4E 0 +OP4 E00D4F 0 +OP4 E00D50 0 +OP4 E00D51 0 +OP4 E00D52 0 +OP4 E00D53 0 +OP4 E00D54 0 +OP4 E00D55 0 +OP4 E00D56 0 +OP4 E00D57 0 +OP4 E00D58 0 +OP4 E00D59 0 +OP4 E00D5A 0 +OP4 E00D5B 0 +OP4 E00D5C 0 +OP4 E00D5D 0 +OP4 E00D5E 0 +OP4 E00D5F 0 +OP4 E00D60 0 +OP4 E00D61 0 +OP4 E00D62 0 +OP4 E00D63 0 +OP4 E00D64 0 +OP4 E00D65 0 +OP4 E00D66 0 +OP4 E00D67 0 +OP4 E00D68 0 +OP4 E00D69 0 +OP4 E00D6A 0 +OP4 E00D6B 0 +OP4 E00D6C 0 +OP4 E00D6D 0 +OP4 E00D6E 0 +OP4 E00D6F 0 +OP4 E00D70 0 +OP4 E00D71 0 +OP4 E00D72 0 +OP4 E00D73 0 +OP4 E00D74 0 +OP4 E00D75 0 +OP4 E00D76 0 +OP4 E00D77 0 +OP4 E00D78 0 +OP4 E00D79 0 +OP4 E00D7A 0 +OP4 E00D7B 0 +OP4 E00D7C 0 +OP4 E00D7D 0 +OP4 E00D7E 0 +OP4 E00D7F 0 +OP4 E00D80 0 +OP4 E00D81 0 +OP4 E00D82 0 +OP4 E00D83 0 +OP4 E00D84 0 +OP4 E00D85 0 +OP4 E00D86 0 +OP4 E00D87 0 +OP4 E00D88 0 +OP4 E00D89 0 +OP4 E00D8A 0 +OP4 E00D8B 0 +OP4 E00D8C 0 +OP4 E00D8D 0 +OP4 E00D8E 0 +OP4 E00D8F 0 +OP4 E00D90 0 +OP4 E00D91 0 +OP4 E00D92 0 +OP4 E00D93 0 +OP4 E00D94 0 +OP4 E00D95 0 +OP4 E00D96 0 +OP4 E00D97 0 +OP4 E00D98 0 +OP4 E00D99 0 +OP4 E00D9A 0 +OP4 E00D9B 0 +OP4 E00D9C 0 +OP4 E00D9D 0 +OP4 E00D9E 0 +OP4 E00D9F 0 +OP4 E00DA0 0 +OP4 E00DA1 0 +OP4 E00DA2 0 +OP4 E00DA3 0 +OP4 E00DA4 0 +OP4 E00DA5 0 +OP4 E00DA6 0 +OP4 E00DA7 0 +OP4 E00DA8 0 +OP4 E00DA9 0 +OP4 E00DAA 0 +OP4 E00DAB 0 +OP4 E00DAC 0 +OP4 E00DAD 0 +OP4 E00DAE 0 +OP4 E00DAF 0 +OP4 E00DB0 0 +OP4 E00DB1 0 +OP4 E00DB2 0 +OP4 E00DB3 0 +OP4 E00DB4 0 +OP4 E00DB5 0 +OP4 E00DB6 0 +OP4 E00DB7 0 +OP4 E00DB8 0 +OP4 E00DB9 0 +OP4 E00DBA 0 +OP4 E00DBB 0 +OP4 E00DBC 0 +OP4 E00DBD 0 +OP4 E00DBE 0 +OP4 E00DBF 0 +OP4 E00DC0 0 +OP4 E00DC1 0 +OP4 E00DC2 0 +OP4 E00DC3 0 +OP4 E00DC4 0 +OP4 E00DC5 0 +OP4 E00DC6 0 +OP4 E00DC7 0 +OP4 E00DC8 0 +OP4 E00DC9 0 +OP4 E00DCA 0 +OP4 E00DCB 0 +OP4 E00DCC 0 +OP4 E00DCD 0 +OP4 E00DCE 0 +OP4 E00DCF 0 +OP4 E00DD0 0 +OP4 E00DD1 0 +OP4 E00DD2 0 +OP4 E00DD3 0 +OP4 E00DD4 0 +OP4 E00DD5 0 +OP4 E00DD6 0 +OP4 E00DD7 0 +OP4 E00DD8 0 +OP4 E00DD9 0 +OP4 E00DDA 0 +OP4 E00DDB 0 +OP4 E00DDC 0 +OP4 E00DDD 0 +OP4 E00DDE 0 +OP4 E00DDF 0 +OP4 E00DE0 0 +OP4 E00DE1 0 +OP4 E00DE2 0 +OP4 E00DE3 0 +OP4 E00DE4 0 +OP4 E00DE5 0 +OP4 E00DE6 0 +OP4 E00DE7 0 +OP4 E00DE8 0 +OP4 E00DE9 0 +OP4 E00DEA 0 +OP4 E00DEB 0 +OP4 E00DEC 0 +OP4 E00DED 0 +OP4 E00DEE 0 +OP4 E00DEF 0 +OP4 E00DF0 0 +OP4 E00DF1 0 +OP4 E00DF2 0 +OP4 E00DF3 0 +OP4 E00DF4 0 +OP4 E00DF5 0 +OP4 E00DF6 0 +OP4 E00DF7 0 +OP4 E00DF8 0 +OP4 E00DF9 0 +OP4 E00DFA 0 +OP4 E00DFB 0 +OP4 E00DFC 0 +OP4 E00DFD 0 +OP4 E00DFE 0 +OP4 E00DFF 0 +OP4 E00E00 0 +OP4 E00E01 0 +OP4 E00E02 0 +OP4 E00E03 0 +OP4 E00E04 0 +OP4 E00E05 0 +OP4 E00E06 0 +OP4 E00E07 0 +OP4 E00E08 0 +OP4 E00E09 0 +OP4 E00E0A 0 +OP4 E00E0B 0 +OP4 E00E0C 0 +OP4 E00E0D 0 +OP4 E00E0E 0 +OP4 E00E0F 0 +OP4 E00E10 0 +OP4 E00E11 0 +OP4 E00E12 0 +OP4 E00E13 0 +OP4 E00E14 0 +OP4 E00E15 0 +OP4 E00E16 0 +OP4 E00E17 0 +OP4 E00E18 0 +OP4 E00E19 0 +OP4 E00E1A 0 +OP4 E00E1B 0 +OP4 E00E1C 0 +OP4 E00E1D 0 +OP4 E00E1E 0 +OP4 E00E1F 0 +OP4 E00E20 0 +OP4 E00E21 0 +OP4 E00E22 0 +OP4 E00E23 0 +OP4 E00E24 0 +OP4 E00E25 0 +OP4 E00E26 0 +OP4 E00E27 0 +OP4 E00E28 0 +OP4 E00E29 0 +OP4 E00E2A 0 +OP4 E00E2B 0 +OP4 E00E2C 0 +OP4 E00E2D 0 +OP4 E00E2E 0 +OP4 E00E2F 0 +OP4 E00E30 0 +OP4 E00E31 0 +OP4 E00E32 0 +OP4 E00E33 0 +OP4 E00E34 0 +OP4 E00E35 0 +OP4 E00E36 0 +OP4 E00E37 0 +OP4 E00E38 0 +OP4 E00E39 0 +OP4 E00E3A 0 +OP4 E00E3B 0 +OP4 E00E3C 0 +OP4 E00E3D 0 +OP4 E00E3E 0 +OP4 E00E3F 0 +OP4 E00E40 0 +OP4 E00E41 0 +OP4 E00E42 0 +OP4 E00E43 0 +OP4 E00E44 0 +OP4 E00E45 0 +OP4 E00E46 0 +OP4 E00E47 0 +OP4 E00E48 0 +OP4 E00E49 0 +OP4 E00E4A 0 +OP4 E00E4B 0 +OP4 E00E4C 0 +OP4 E00E4D 0 +OP4 E00E4E 0 +OP4 E00E4F 0 +OP4 E00E50 0 +OP4 E00E51 0 +OP4 E00E52 0 +OP4 E00E53 0 +OP4 E00E54 0 +OP4 E00E55 0 +OP4 E00E56 0 +OP4 E00E57 0 +OP4 E00E58 0 +OP4 E00E59 0 +OP4 E00E5A 0 +OP4 E00E5B 0 +OP4 E00E5C 0 +OP4 E00E5D 0 +OP4 E00E5E 0 +OP4 E00E5F 0 +OP4 E00E60 0 +OP4 E00E61 0 +OP4 E00E62 0 +OP4 E00E63 0 +OP4 E00E64 0 +OP4 E00E65 0 +OP4 E00E66 0 +OP4 E00E67 0 +OP4 E00E68 0 +OP4 E00E69 0 +OP4 E00E6A 0 +OP4 E00E6B 0 +OP4 E00E6C 0 +OP4 E00E6D 0 +OP4 E00E6E 0 +OP4 E00E6F 0 +OP4 E00E70 0 +OP4 E00E71 0 +OP4 E00E72 0 +OP4 E00E73 0 +OP4 E00E74 0 +OP4 E00E75 0 +OP4 E00E76 0 +OP4 E00E77 0 +OP4 E00E78 0 +OP4 E00E79 0 +OP4 E00E7A 0 +OP4 E00E7B 0 +OP4 E00E7C 0 +OP4 E00E7D 0 +OP4 E00E7E 0 +OP4 E00E7F 0 +OP4 E00E80 0 +OP4 E00E81 0 +OP4 E00E82 0 +OP4 E00E83 0 +OP4 E00E84 0 +OP4 E00E85 0 +OP4 E00E86 0 +OP4 E00E87 0 +OP4 E00E88 0 +OP4 E00E89 0 +OP4 E00E8A 0 +OP4 E00E8B 0 +OP4 E00E8C 0 +OP4 E00E8D 0 +OP4 E00E8E 0 +OP4 E00E8F 0 +OP4 E00E90 0 +OP4 E00E91 0 +OP4 E00E92 0 +OP4 E00E93 0 +OP4 E00E94 0 +OP4 E00E95 0 +OP4 E00E96 0 +OP4 E00E97 0 +OP4 E00E98 0 +OP4 E00E99 0 +OP4 E00E9A 0 +OP4 E00E9B 0 +OP4 E00E9C 0 +OP4 E00E9D 0 +OP4 E00E9E 0 +OP4 E00E9F 0 +OP4 E00EA0 0 +OP4 E00EA1 0 +OP4 E00EA2 0 +OP4 E00EA3 0 +OP4 E00EA4 0 +OP4 E00EA5 0 +OP4 E00EA6 0 +OP4 E00EA7 0 +OP4 E00EA8 0 +OP4 E00EA9 0 +OP4 E00EAA 0 +OP4 E00EAB 0 +OP4 E00EAC 0 +OP4 E00EAD 0 +OP4 E00EAE 0 +OP4 E00EAF 0 +OP4 E00EB0 0 +OP4 E00EB1 0 +OP4 E00EB2 0 +OP4 E00EB3 0 +OP4 E00EB4 0 +OP4 E00EB5 0 +OP4 E00EB6 0 +OP4 E00EB7 0 +OP4 E00EB8 0 +OP4 E00EB9 0 +OP4 E00EBA 0 +OP4 E00EBB 0 +OP4 E00EBC 0 +OP4 E00EBD 0 +OP4 E00EBE 0 +OP4 E00EBF 0 +OP4 E00EC0 0 +OP4 E00EC1 0 +OP4 E00EC2 0 +OP4 E00EC3 0 +OP4 E00EC4 0 +OP4 E00EC5 0 +OP4 E00EC6 0 +OP4 E00EC7 0 +OP4 E00EC8 0 +OP4 E00EC9 0 +OP4 E00ECA 0 +OP4 E00ECB 0 +OP4 E00ECC 0 +OP4 E00ECD 0 +OP4 E00ECE 0 +OP4 E00ECF 0 +OP4 E00ED0 0 +OP4 E00ED1 0 +OP4 E00ED2 0 +OP4 E00ED3 0 +OP4 E00ED4 0 +OP4 E00ED5 0 +OP4 E00ED6 0 +OP4 E00ED7 0 +OP4 E00ED8 0 +OP4 E00ED9 0 +OP4 E00EDA 0 +OP4 E00EDB 0 +OP4 E00EDC 0 +OP4 E00EDD 0 +OP4 E00EDE 0 +OP4 E00EDF 0 +OP4 E00EE0 0 +OP4 E00EE1 0 +OP4 E00EE2 0 +OP4 E00EE3 0 +OP4 E00EE4 0 +OP4 E00EE5 0 +OP4 E00EE6 0 +OP4 E00EE7 0 +OP4 E00EE8 0 +OP4 E00EE9 0 +OP4 E00EEA 0 +OP4 E00EEB 0 +OP4 E00EEC 0 +OP4 E00EED 0 +OP4 E00EEE 0 +OP4 E00EEF 0 +OP4 E00EF0 0 +OP4 E00EF1 0 +OP4 E00EF2 0 +OP4 E00EF3 0 +OP4 E00EF4 0 +OP4 E00EF5 0 +OP4 E00EF6 0 +OP4 E00EF7 0 +OP4 E00EF8 0 +OP4 E00EF9 0 +OP4 E00EFA 0 +OP4 E00EFB 0 +OP4 E00EFC 0 +OP4 E00EFD 0 +OP4 E00EFE 0 +OP4 E00EFF 0 +OP4 E00F00 0 +OP4 E00F01 0 +OP4 E00F02 0 +OP4 E00F03 0 +OP4 E00F04 0 +OP4 E00F05 0 +OP4 E00F06 0 +OP4 E00F07 0 +OP4 E00F08 0 +OP4 E00F09 0 +OP4 E00F0A 0 +OP4 E00F0B 0 +OP4 E00F0C 0 +OP4 E00F0D 0 +OP4 E00F0E 0 +OP4 E00F0F 0 +OP4 E00F10 0 +OP4 E00F11 0 +OP4 E00F12 0 +OP4 E00F13 0 +OP4 E00F14 0 +OP4 E00F15 0 +OP4 E00F16 0 +OP4 E00F17 0 +OP4 E00F18 0 +OP4 E00F19 0 +OP4 E00F1A 0 +OP4 E00F1B 0 +OP4 E00F1C 0 +OP4 E00F1D 0 +OP4 E00F1E 0 +OP4 E00F1F 0 +OP4 E00F20 0 +OP4 E00F21 0 +OP4 E00F22 0 +OP4 E00F23 0 +OP4 E00F24 0 +OP4 E00F25 0 +OP4 E00F26 0 +OP4 E00F27 0 +OP4 E00F28 0 +OP4 E00F29 0 +OP4 E00F2A 0 +OP4 E00F2B 0 +OP4 E00F2C 0 +OP4 E00F2D 0 +OP4 E00F2E 0 +OP4 E00F2F 0 +OP4 E00F30 0 +OP4 E00F31 0 +OP4 E00F32 0 +OP4 E00F33 0 +OP4 E00F34 0 +OP4 E00F35 0 +OP4 E00F36 0 +OP4 E00F37 0 +OP4 E00F38 0 +OP4 E00F39 0 +OP4 E00F3A 0 +OP4 E00F3B 0 +OP4 E00F3C 0 +OP4 E00F3D 0 +OP4 E00F3E 0 +OP4 E00F3F 0 +OP4 E00F40 0 +OP4 E00F41 0 +OP4 E00F42 0 +OP4 E00F43 0 +OP4 E00F44 0 +OP4 E00F45 0 +OP4 E00F46 0 +OP4 E00F47 0 +OP4 E00F48 0 +OP4 E00F49 0 +OP4 E00F4A 0 +OP4 E00F4B 0 +OP4 E00F4C 0 +OP4 E00F4D 0 +OP4 E00F4E 0 +OP4 E00F4F 0 +OP4 E00F50 0 +OP4 E00F51 0 +OP4 E00F52 0 +OP4 E00F53 0 +OP4 E00F54 0 +OP4 E00F55 0 +OP4 E00F56 0 +OP4 E00F57 0 +OP4 E00F58 0 +OP4 E00F59 0 +OP4 E00F5A 0 +OP4 E00F5B 0 +OP4 E00F5C 0 +OP4 E00F5D 0 +OP4 E00F5E 0 +OP4 E00F5F 0 +OP4 E00F60 0 +OP4 E00F61 0 +OP4 E00F62 0 +OP4 E00F63 0 +OP4 E00F64 0 +OP4 E00F65 0 +OP4 E00F66 0 +OP4 E00F67 0 +OP4 E00F68 0 +OP4 E00F69 0 +OP4 E00F6A 0 +OP4 E00F6B 0 +OP4 E00F6C 0 +OP4 E00F6D 0 +OP4 E00F6E 0 +OP4 E00F6F 0 +OP4 E00F70 0 +OP4 E00F71 0 +OP4 E00F72 0 +OP4 E00F73 0 +OP4 E00F74 0 +OP4 E00F75 0 +OP4 E00F76 0 +OP4 E00F77 0 +OP4 E00F78 0 +OP4 E00F79 0 +OP4 E00F7A 0 +OP4 E00F7B 0 +OP4 E00F7C 0 +OP4 E00F7D 0 +OP4 E00F7E 0 +OP4 E00F7F 0 +OP4 E00F80 0 +OP4 E00F81 0 +OP4 E00F82 0 +OP4 E00F83 0 +OP4 E00F84 0 +OP4 E00F85 0 +OP4 E00F86 0 +OP4 E00F87 0 +OP4 E00F88 0 +OP4 E00F89 0 +OP4 E00F8A 0 +OP4 E00F8B 0 +OP4 E00F8C 0 +OP4 E00F8D 0 +OP4 E00F8E 0 +OP4 E00F8F 0 +OP4 E00F90 0 +OP4 E00F91 0 +OP4 E00F92 0 +OP4 E00F93 0 +OP4 E00F94 0 +OP4 E00F95 0 +OP4 E00F96 0 +OP4 E00F97 0 +OP4 E00F98 0 +OP4 E00F99 0 +OP4 E00F9A 0 +OP4 E00F9B 0 +OP4 E00F9C 0 +OP4 E00F9D 0 +OP4 E00F9E 0 +OP4 E00F9F 0 +OP4 E00FA0 0 +OP4 E00FA1 0 +OP4 E00FA2 0 +OP4 E00FA3 0 +OP4 E00FA4 0 +OP4 E00FA5 0 +OP4 E00FA6 0 +OP4 E00FA7 0 +OP4 E00FA8 0 +OP4 E00FA9 0 +OP4 E00FAA 0 +OP4 E00FAB 0 +OP4 E00FAC 0 +OP4 E00FAD 0 +OP4 E00FAE 0 +OP4 E00FAF 0 +OP4 E00FB0 0 +OP4 E00FB1 0 +OP4 E00FB2 0 +OP4 E00FB3 0 +OP4 E00FB4 0 +OP4 E00FB5 0 +OP4 E00FB6 0 +OP4 E00FB7 0 +OP4 E00FB8 0 +OP4 E00FB9 0 +OP4 E00FBA 0 +OP4 E00FBB 0 +OP4 E00FBC 0 +OP4 E00FBD 0 +OP4 E00FBE 0 +OP4 E00FBF 0 +OP4 E00FC0 0 +OP4 E00FC1 0 +OP4 E00FC2 0 +OP4 E00FC3 0 +OP4 E00FC4 0 +OP4 E00FC5 0 +OP4 E00FC6 0 +OP4 E00FC7 0 +OP4 E00FC8 0 +OP4 E00FC9 0 +OP4 E00FCA 0 +OP4 E00FCB 0 +OP4 E00FCC 0 +OP4 E00FCD 0 +OP4 E00FCE 0 +OP4 E00FCF 0 +OP4 E00FD0 0 +OP4 E00FD1 0 +OP4 E00FD2 0 +OP4 E00FD3 0 +OP4 E00FD4 0 +OP4 E00FD5 0 +OP4 E00FD6 0 +OP4 E00FD7 0 +OP4 E00FD8 0 +OP4 E00FD9 0 +OP4 E00FDA 0 +OP4 E00FDB 0 +OP4 E00FDC 0 +OP4 E00FDD 0 +OP4 E00FDE 0 +OP4 E00FDF 0 +OP4 E00FE0 0 +OP4 E00FE1 0 +OP4 E00FE2 0 +OP4 E00FE3 0 +OP4 E00FE4 0 +OP4 E00FE5 0 +OP4 E00FE6 0 +OP4 E00FE7 0 +OP4 E00FE8 0 +OP4 E00FE9 0 +OP4 E00FEA 0 +OP4 E00FEB 0 +OP4 E00FEC 0 +OP4 E00FED 0 +OP4 E00FEE 0 +OP4 E00FEF 0 +OP4 E00FF0 0 +OP4 E00FF1 0 +OP4 E00FF2 0 +OP4 E00FF3 0 +OP4 E00FF4 0 +OP4 E00FF5 0 +OP4 E00FF6 0 +OP4 E00FF7 0 +OP4 E00FF8 0 +OP4 E00FF9 0 +OP4 E00FFA 0 +OP4 E00FFB 0 +OP4 E00FFC 0 +OP4 E00FFD 0 +OP4 E00FFE 0 +OP4 E00FFF 0 +OP4 E01000 0 +OP4 E01001 0 +OP4 E01002 0 +OP4 E01003 0 +OP4 E01004 0 +OP4 E01005 0 +OP4 E01006 0 +OP4 E01007 0 +OP4 E01008 0 +OP4 E01009 0 +OP4 E0100A 0 +OP4 E0100B 0 +OP4 E0100C 0 +OP4 E0100D 0 +OP4 E0100E 0 +OP4 E0100F 0 +OP4 E01010 0 +OP4 E01011 0 +OP4 E01012 0 +OP4 E01013 0 +OP4 E01014 0 +OP4 E01015 0 +OP4 E01016 0 +OP4 E01017 0 +OP4 E01018 0 +OP4 E01019 0 +OP4 E0101A 0 +OP4 E0101B 0 +OP4 E0101C 0 +OP4 E0101D 0 +OP4 E0101E 0 +OP4 E0101F 0 +OP4 E01020 0 +OP4 E01021 0 +OP4 E01022 0 +OP4 E01023 0 +OP4 E01024 0 +OP4 E01025 0 +OP4 E01026 0 +OP4 E01027 0 +OP4 E01028 0 +OP4 E01029 0 +OP4 E0102A 0 +OP4 E0102B 0 +OP4 E0102C 0 +OP4 E0102D 0 +OP4 E0102E 0 +OP4 E0102F 0 +OP4 E01030 0 +OP4 E01031 0 +OP4 E01032 0 +OP4 E01033 0 +OP4 E01034 0 +OP4 E01035 0 +OP4 E01036 0 +OP4 E01037 0 +OP4 E01038 0 +OP4 E01039 0 +OP4 E0103A 0 +OP4 E0103B 0 +OP4 E0103C 0 +OP4 E0103D 0 +OP4 E0103E 0 +OP4 E0103F 0 +OP4 E01040 0 +OP4 E01041 0 +OP4 E01042 0 +OP4 E01043 0 +OP4 E01044 0 +OP4 E01045 0 +OP4 E01046 0 +OP4 E01047 0 +OP4 E01048 0 +OP4 E01049 0 +OP4 E0104A 0 +OP4 E0104B 0 +OP4 E0104C 0 +OP4 E0104D 0 +OP4 E0104E 0 +OP4 E0104F 0 +OP4 E01050 0 +OP4 E01051 0 +OP4 E01052 0 +OP4 E01053 0 +OP4 E01054 0 +OP4 E01055 0 +OP4 E01056 0 +OP4 E01057 0 +OP4 E01058 0 +OP4 E01059 0 +OP4 E0105A 0 +OP4 E0105B 0 +OP4 E0105C 0 +OP4 E0105D 0 +OP4 E0105E 0 +OP4 E0105F 0 +OP4 E01060 0 +OP4 E01061 0 +OP4 E01062 0 +OP4 E01063 0 +OP4 E01064 0 +OP4 E01065 0 +OP4 E01066 0 +OP4 E01067 0 +OP4 E01068 0 +OP4 E01069 0 +OP4 E0106A 0 +OP4 E0106B 0 +OP4 E0106C 0 +OP4 E0106D 0 +OP4 E0106E 0 +OP4 E0106F 0 +OP4 E01070 0 +OP4 E01071 0 +OP4 E01072 0 +OP4 E01073 0 +OP4 E01074 0 +OP4 E01075 0 +OP4 E01076 0 +OP4 E01077 0 +OP4 E01078 0 +OP4 E01079 0 +OP4 E0107A 0 +OP4 E0107B 0 +OP4 E0107C 0 +OP4 E0107D 0 +OP4 E0107E 0 +OP4 E0107F 0 +OP4 E01080 0 +OP4 E01081 0 +OP4 E01082 0 +OP4 E01083 0 +OP4 E01084 0 +OP4 E01085 0 +OP4 E01086 0 +OP4 E01087 0 +OP4 E01088 0 +OP4 E01089 0 +OP4 E0108A 0 +OP4 E0108B 0 +OP4 E0108C 0 +OP4 E0108D 0 +OP4 E0108E 0 +OP4 E0108F 0 +OP4 E01090 0 +OP4 E01091 0 +OP4 E01092 0 +OP4 E01093 0 +OP4 E01094 0 +OP4 E01095 0 +OP4 E01096 0 +OP4 E01097 0 +OP4 E01098 0 +OP4 E01099 0 +OP4 E0109A 0 +OP4 E0109B 0 +OP4 E0109C 0 +OP4 E0109D 0 +OP4 E0109E 0 +OP4 E0109F 0 +OP4 E010A0 0 +OP4 E010A1 0 +OP4 E010A2 0 +OP4 E010A3 0 +OP4 E010A4 0 +OP4 E010A5 0 +OP4 E010A6 0 +OP4 E010A7 0 +OP4 E010A8 0 +OP4 E010A9 0 +OP4 E010AA 0 +OP4 E010AB 0 +OP4 E010AC 0 +OP4 E010AD 0 +OP4 E010AE 0 +OP4 E010AF 0 +OP4 E010B0 0 +OP4 E010B1 0 +OP4 E010B2 0 +OP4 E010B3 0 +OP4 E010B4 0 +OP4 E010B5 0 +OP4 E010B6 0 +OP4 E010B7 0 +OP4 E010B8 0 +OP4 E010B9 0 +OP4 E010BA 0 +OP4 E010BB 0 +OP4 E010BC 0 +OP4 E010BD 0 +OP4 E010BE 0 +OP4 E010BF 0 +OP4 E010C0 0 +OP4 E010C1 0 +OP4 E010C2 0 +OP4 E010C3 0 +OP4 E010C4 0 +OP4 E010C5 0 +OP4 E010C6 0 +OP4 E010C7 0 +OP4 E010C8 0 +OP4 E010C9 0 +OP4 E010CA 0 +OP4 E010CB 0 +OP4 E010CC 0 +OP4 E010CD 0 +OP4 E010CE 0 +OP4 E010CF 0 +OP4 E010D0 0 +OP4 E010D1 0 +OP4 E010D2 0 +OP4 E010D3 0 +OP4 E010D4 0 +OP4 E010D5 0 +OP4 E010D6 0 +OP4 E010D7 0 +OP4 E010D8 0 +OP4 E010D9 0 +OP4 E010DA 0 +OP4 E010DB 0 +OP4 E010DC 0 +OP4 E010DD 0 +OP4 E010DE 0 +OP4 E010DF 0 +OP4 E010E0 0 +OP4 E010E1 0 +OP4 E010E2 0 +OP4 E010E3 0 +OP4 E010E4 0 +OP4 E010E5 0 +OP4 E010E6 0 +OP4 E010E7 0 +OP4 E010E8 0 +OP4 E010E9 0 +OP4 E010EA 0 +OP4 E010EB 0 +OP4 E010EC 0 +OP4 E010ED 0 +OP4 E010EE 0 +OP4 E010EF 0 +OP4 E010F0 0 +OP4 E010F1 0 +OP4 E010F2 0 +OP4 E010F3 0 +OP4 E010F4 0 +OP4 E010F5 0 +OP4 E010F6 0 +OP4 E010F7 0 +OP4 E010F8 0 +OP4 E010F9 0 +OP4 E010FA 0 +OP4 E010FB 0 +OP4 E010FC 0 +OP4 E010FD 0 +OP4 E010FE 0 +OP4 E010FF 0 +OP4 E01100 0 +OP4 E01101 0 +OP4 E01102 0 +OP4 E01103 0 +OP4 E01104 0 +OP4 E01105 0 +OP4 E01106 0 +OP4 E01107 0 +OP4 E01108 0 +OP4 E01109 0 +OP4 E0110A 0 +OP4 E0110B 0 +OP4 E0110C 0 +OP4 E0110D 0 +OP4 E0110E 0 +OP4 E0110F 0 +OP4 E01110 0 +OP4 E01111 0 +OP4 E01112 0 +OP4 E01113 0 +OP4 E01114 0 +OP4 E01115 0 +OP4 E01116 0 +OP4 E01117 0 +OP4 E01118 0 +OP4 E01119 0 +OP4 E0111A 0 +OP4 E0111B 0 +OP4 E0111C 0 +OP4 E0111D 0 +OP4 E0111E 0 +OP4 E0111F 0 +OP4 E01120 0 +OP4 E01121 0 +OP4 E01122 0 +OP4 E01123 0 +OP4 E01124 0 +OP4 E01125 0 +OP4 E01126 0 +OP4 E01127 0 +OP4 E01128 0 +OP4 E01129 0 +OP4 E0112A 0 +OP4 E0112B 0 +OP4 E0112C 0 +OP4 E0112D 0 +OP4 E0112E 0 +OP4 E0112F 0 +OP4 E01130 0 +OP4 E01131 0 +OP4 E01132 0 +OP4 E01133 0 +OP4 E01134 0 +OP4 E01135 0 +OP4 E01136 0 +OP4 E01137 0 +OP4 E01138 0 +OP4 E01139 0 +OP4 E0113A 0 +OP4 E0113B 0 +OP4 E0113C 0 +OP4 E0113D 0 +OP4 E0113E 0 +OP4 E0113F 0 +OP4 E01140 0 +OP4 E01141 0 +OP4 E01142 0 +OP4 E01143 0 +OP4 E01144 0 +OP4 E01145 0 +OP4 E01146 0 +OP4 E01147 0 +OP4 E01148 0 +OP4 E01149 0 +OP4 E0114A 0 +OP4 E0114B 0 +OP4 E0114C 0 +OP4 E0114D 0 +OP4 E0114E 0 +OP4 E0114F 0 +OP4 E01150 0 +OP4 E01151 0 +OP4 E01152 0 +OP4 E01153 0 +OP4 E01154 0 +OP4 E01155 0 +OP4 E01156 0 +OP4 E01157 0 +OP4 E01158 0 +OP4 E01159 0 +OP4 E0115A 0 +OP4 E0115B 0 +OP4 E0115C 0 +OP4 E0115D 0 +OP4 E0115E 0 +OP4 E0115F 0 +OP4 E01160 0 +OP4 E01161 0 +OP4 E01162 0 +OP4 E01163 0 +OP4 E01164 0 +OP4 E01165 0 +OP4 E01166 0 +OP4 E01167 0 +OP4 E01168 0 +OP4 E01169 0 +OP4 E0116A 0 +OP4 E0116B 0 +OP4 E0116C 0 +OP4 E0116D 0 +OP4 E0116E 0 +OP4 E0116F 0 +OP4 E01170 0 +OP4 E01171 0 +OP4 E01172 0 +OP4 E01173 0 +OP4 E01174 0 +OP4 E01175 0 +OP4 E01176 0 +OP4 E01177 0 +OP4 E01178 0 +OP4 E01179 0 +OP4 E0117A 0 +OP4 E0117B 0 +OP4 E0117C 0 +OP4 E0117D 0 +OP4 E0117E 0 +OP4 E0117F 0 +OP4 E01180 0 +OP4 E01181 0 +OP4 E01182 0 +OP4 E01183 0 +OP4 E01184 0 +OP4 E01185 0 +OP4 E01186 0 +OP4 E01187 0 +OP4 E01188 0 +OP4 E01189 0 +OP4 E0118A 0 +OP4 E0118B 0 +OP4 E0118C 0 +OP4 E0118D 0 +OP4 E0118E 0 +OP4 E0118F 0 +OP4 E01190 0 +OP4 E01191 0 +OP4 E01192 0 +OP4 E01193 0 +OP4 E01194 0 +OP4 E01195 0 +OP4 E01196 0 +OP4 E01197 0 +OP4 E01198 0 +OP4 E01199 0 +OP4 E0119A 0 +OP4 E0119B 0 +OP4 E0119C 0 +OP4 E0119D 0 +OP4 E0119E 0 +OP4 E0119F 0 +OP4 E011A0 0 +OP4 E011A1 0 +OP4 E011A2 0 +OP4 E011A3 0 +OP4 E011A4 0 +OP4 E011A5 0 +OP4 E011A6 0 +OP4 E011A7 0 +OP4 E011A8 0 +OP4 E011A9 0 +OP4 E011AA 0 +OP4 E011AB 0 +OP4 E011AC 0 +OP4 E011AD 0 +OP4 E011AE 0 +OP4 E011AF 0 +OP4 E011B0 0 +OP4 E011B1 0 +OP4 E011B2 0 +OP4 E011B3 0 +OP4 E011B4 0 +OP4 E011B5 0 +OP4 E011B6 0 +OP4 E011B7 0 +OP4 E011B8 0 +OP4 E011B9 0 +OP4 E011BA 0 +OP4 E011BB 0 +OP4 E011BC 0 +OP4 E011BD 0 +OP4 E011BE 0 +OP4 E011BF 0 +OP4 E011C0 0 +OP4 E011C1 0 +OP4 E011C2 0 +OP4 E011C3 0 +OP4 E011C4 0 +OP4 E011C5 0 +OP4 E011C6 0 +OP4 E011C7 0 +OP4 E011C8 0 +OP4 E011C9 0 +OP4 E011CA 0 +OP4 E011CB 0 +OP4 E011CC 0 +OP4 E011CD 0 +OP4 E011CE 0 +OP4 E011CF 0 +OP4 E011D0 0 +OP4 E011D1 0 +OP4 E011D2 0 +OP4 E011D3 0 +OP4 E011D4 0 +OP4 E011D5 0 +OP4 E011D6 0 +OP4 E011D7 0 +OP4 E011D8 0 +OP4 E011D9 0 +OP4 E011DA 0 +OP4 E011DB 0 +OP4 E011DC 0 +OP4 E011DD 0 +OP4 E011DE 0 +OP4 E011DF 0 +OP4 E011E0 0 +OP4 E011E1 0 +OP4 E011E2 0 +OP4 E011E3 0 +OP4 E011E4 0 +OP4 E011E5 0 +OP4 E011E6 0 +OP4 E011E7 0 +OP4 E011E8 0 +OP4 E011E9 0 +OP4 E011EA 0 +OP4 E011EB 0 +OP4 E011EC 0 +OP4 E011ED 0 +OP4 E011EE 0 +OP4 E011EF 0 +OP4 E011F0 0 +OP4 E011F1 0 +OP4 E011F2 0 +OP4 E011F3 0 +OP4 E011F4 0 +OP4 E011F5 0 +OP4 E011F6 0 +OP4 E011F7 0 +OP4 E011F8 0 +OP4 E011F9 0 +OP4 E011FA 0 +OP4 E011FB 0 +OP4 E011FC 0 +OP4 E011FD 0 +OP4 E011FE 0 +OP4 E011FF 0 +OP4 E01200 0 +OP4 E01201 0 +OP4 E01202 0 +OP4 E01203 0 +OP4 E01204 0 +OP4 E01205 0 +OP4 E01206 0 +OP4 E01207 0 +OP4 E01208 0 +OP4 E01209 0 +OP4 E0120A 0 +OP4 E0120B 0 +OP4 E0120C 0 +OP4 E0120D 0 +OP4 E0120E 0 +OP4 E0120F 0 +OP4 E01210 0 +OP4 E01211 0 +OP4 E01212 0 +OP4 E01213 0 +OP4 E01214 0 +OP4 E01215 0 +OP4 E01216 0 +OP4 E01217 0 +OP4 E01218 0 +OP4 E01219 0 +OP4 E0121A 0 +OP4 E0121B 0 +OP4 E0121C 0 +OP4 E0121D 0 +OP4 E0121E 0 +OP4 E0121F 0 +OP4 E01220 0 +OP4 E01221 0 +OP4 E01222 0 +OP4 E01223 0 +OP4 E01224 0 +OP4 E01225 0 +OP4 E01226 0 +OP4 E01227 0 +OP4 E01228 0 +OP4 E01229 0 +OP4 E0122A 0 +OP4 E0122B 0 +OP4 E0122C 0 +OP4 E0122D 0 +OP4 E0122E 0 +OP4 E0122F 0 +OP4 E01230 0 +OP4 E01231 0 +OP4 E01232 0 +OP4 E01233 0 +OP4 E01234 0 +OP4 E01235 0 +OP4 E01236 0 +OP4 E01237 0 +OP4 E01238 0 +OP4 E01239 0 +OP4 E0123A 0 +OP4 E0123B 0 +OP4 E0123C 0 +OP4 E0123D 0 +OP4 E0123E 0 +OP4 E0123F 0 +OP4 E01240 0 +OP4 E01241 0 +OP4 E01242 0 +OP4 E01243 0 +OP4 E01244 0 +OP4 E01245 0 +OP4 E01246 0 +OP4 E01247 0 +OP4 E01248 0 +OP4 E01249 0 +OP4 E0124A 0 +OP4 E0124B 0 +OP4 E0124C 0 +OP4 E0124D 0 +OP4 E0124E 0 +OP4 E0124F 0 +OP4 E01250 0 +OP4 E01251 0 +OP4 E01252 0 +OP4 E01253 0 +OP4 E01254 0 +OP4 E01255 0 +OP4 E01256 0 +OP4 E01257 0 +OP4 E01258 0 +OP4 E01259 0 +OP4 E0125A 0 +OP4 E0125B 0 +OP4 E0125C 0 +OP4 E0125D 0 +OP4 E0125E 0 +OP4 E0125F 0 +OP4 E01260 0 +OP4 E01261 0 +OP4 E01262 0 +OP4 E01263 0 +OP4 E01264 0 +OP4 E01265 0 +OP4 E01266 0 +OP4 E01267 0 +OP4 E01268 0 +OP4 E01269 0 +OP4 E0126A 0 +OP4 E0126B 0 +OP4 E0126C 0 +OP4 E0126D 0 +OP4 E0126E 0 +OP4 E0126F 0 +OP4 E01270 0 +OP4 E01271 0 +OP4 E01272 0 +OP4 E01273 0 +OP4 E01274 0 +OP4 E01275 0 +OP4 E01276 0 +OP4 E01277 0 +OP4 E01278 0 +OP4 E01279 0 +OP4 E0127A 0 +OP4 E0127B 0 +OP4 E0127C 0 +OP4 E0127D 0 +OP4 E0127E 0 +OP4 E0127F 0 +OP4 E01280 0 +OP4 E01281 0 +OP4 E01282 0 +OP4 E01283 0 +OP4 E01284 0 +OP4 E01285 0 +OP4 E01286 0 +OP4 E01287 0 +OP4 E01288 0 +OP4 E01289 0 +OP4 E0128A 0 +OP4 E0128B 0 +OP4 E0128C 0 +OP4 E0128D 0 +OP4 E0128E 0 +OP4 E0128F 0 +OP4 E01290 0 +OP4 E01291 0 +OP4 E01292 0 +OP4 E01293 0 +OP4 E01294 0 +OP4 E01295 0 +OP4 E01296 0 +OP4 E01297 0 +OP4 E01298 0 +OP4 E01299 0 +OP4 E0129A 0 +OP4 E0129B 0 +OP4 E0129C 0 +OP4 E0129D 0 +OP4 E0129E 0 +OP4 E0129F 0 +OP4 E012A0 0 +OP4 E012A1 0 +OP4 E012A2 0 +OP4 E012A3 0 +OP4 E012A4 0 +OP4 E012A5 0 +OP4 E012A6 0 +OP4 E012A7 0 +OP4 E012A8 0 +OP4 E012A9 0 +OP4 E012AA 0 +OP4 E012AB 0 +OP4 E012AC 0 +OP4 E012AD 0 +OP4 E012AE 0 +OP4 E012AF 0 +OP4 E012B0 0 +OP4 E012B1 0 +OP4 E012B2 0 +OP4 E012B3 0 +OP4 E012B4 0 +OP4 E012B5 0 +OP4 E012B6 0 +OP4 E012B7 0 +OP4 E012B8 0 +OP4 E012B9 0 +OP4 E012BA 0 +OP4 E012BB 0 +OP4 E012BC 0 +OP4 E012BD 0 +OP4 E012BE 0 +OP4 E012BF 0 +OP4 E012C0 0 +OP4 E012C1 0 +OP4 E012C2 0 +OP4 E012C3 0 +OP4 E012C4 0 +OP4 E012C5 0 +OP4 E012C6 0 +OP4 E012C7 0 +OP4 E012C8 0 +OP4 E012C9 0 +OP4 E012CA 0 +OP4 E012CB 0 +OP4 E012CC 0 +OP4 E012CD 0 +OP4 E012CE 0 +OP4 E012CF 0 +OP4 E012D0 0 +OP4 E012D1 0 +OP4 E012D2 0 +OP4 E012D3 0 +OP4 E012D4 0 +OP4 E012D5 0 +OP4 E012D6 0 +OP4 E012D7 0 +OP4 E012D8 0 +OP4 E012D9 0 +OP4 E012DA 0 +OP4 E012DB 0 +OP4 E012DC 0 +OP4 E012DD 0 +OP4 E012DE 0 +OP4 E012DF 0 +OP4 E012E0 0 +OP4 E012E1 0 +OP4 E012E2 0 +OP4 E012E3 0 +OP4 E012E4 0 +OP4 E012E5 0 +OP4 E012E6 0 +OP4 E012E7 0 +OP4 E012E8 0 +OP4 E012E9 0 +OP4 E012EA 0 +OP4 E012EB 0 +OP4 E012EC 0 +OP4 E012ED 0 +OP4 E012EE 0 +OP4 E012EF 0 +OP4 E012F0 0 +OP4 E012F1 0 +OP4 E012F2 0 +OP4 E012F3 0 +OP4 E012F4 0 +OP4 E012F5 0 +OP4 E012F6 0 +OP4 E012F7 0 +OP4 E012F8 0 +OP4 E012F9 0 +OP4 E012FA 0 +OP4 E012FB 0 +OP4 E012FC 0 +OP4 E012FD 0 +OP4 E012FE 0 +OP4 E012FF 0 +OP4 E01300 0 +OP4 E01301 0 +OP4 E01302 0 +OP4 E01303 0 +OP4 E01304 0 +OP4 E01305 0 +OP4 E01306 0 +OP4 E01307 0 +OP4 E01308 0 +OP4 E01309 0 +OP4 E0130A 0 +OP4 E0130B 0 +OP4 E0130C 0 +OP4 E0130D 0 +OP4 E0130E 0 +OP4 E0130F 0 +OP4 E01310 0 +OP4 E01311 0 +OP4 E01312 0 +OP4 E01313 0 +OP4 E01314 0 +OP4 E01315 0 +OP4 E01316 0 +OP4 E01317 0 +OP4 E01318 0 +OP4 E01319 0 +OP4 E0131A 0 +OP4 E0131B 0 +OP4 E0131C 0 +OP4 E0131D 0 +OP4 E0131E 0 +OP4 E0131F 0 +OP4 E01320 0 +OP4 E01321 0 +OP4 E01322 0 +OP4 E01323 0 +OP4 E01324 0 +OP4 E01325 0 +OP4 E01326 0 +OP4 E01327 0 +OP4 E01328 0 +OP4 E01329 0 +OP4 E0132A 0 +OP4 E0132B 0 +OP4 E0132C 0 +OP4 E0132D 0 +OP4 E0132E 0 +OP4 E0132F 0 +OP4 E01330 0 +OP4 E01331 0 +OP4 E01332 0 +OP4 E01333 0 +OP4 E01334 0 +OP4 E01335 0 +OP4 E01336 0 +OP4 E01337 0 +OP4 E01338 0 +OP4 E01339 0 +OP4 E0133A 0 +OP4 E0133B 0 +OP4 E0133C 0 +OP4 E0133D 0 +OP4 E0133E 0 +OP4 E0133F 0 +OP4 E01340 0 +OP4 E01341 0 +OP4 E01342 0 +OP4 E01343 0 +OP4 E01344 0 +OP4 E01345 0 +OP4 E01346 0 +OP4 E01347 0 +OP4 E01348 0 +OP4 E01349 0 +OP4 E0134A 0 +OP4 E0134B 0 +OP4 E0134C 0 +OP4 E0134D 0 +OP4 E0134E 0 +OP4 E0134F 0 +OP4 E01350 0 +OP4 E01351 0 +OP4 E01352 0 +OP4 E01353 0 +OP4 E01354 0 +OP4 E01355 0 +OP4 E01356 0 +OP4 E01357 0 +OP4 E01358 0 +OP4 E01359 0 +OP4 E0135A 0 +OP4 E0135B 0 +OP4 E0135C 0 +OP4 E0135D 0 +OP4 E0135E 0 +OP4 E0135F 0 +OP4 E01360 0 +OP4 E01361 0 +OP4 E01362 0 +OP4 E01363 0 +OP4 E01364 0 +OP4 E01365 0 +OP4 E01366 0 +OP4 E01367 0 +OP4 E01368 0 +OP4 E01369 0 +OP4 E0136A 0 +OP4 E0136B 0 +OP4 E0136C 0 +OP4 E0136D 0 +OP4 E0136E 0 +OP4 E0136F 0 +OP4 E01370 0 +OP4 E01371 0 +OP4 E01372 0 +OP4 E01373 0 +OP4 E01374 0 +OP4 E01375 0 +OP4 E01376 0 +OP4 E01377 0 +OP4 E01378 0 +OP4 E01379 0 +OP4 E0137A 0 +OP4 E0137B 0 +OP4 E0137C 0 +OP4 E0137D 0 +OP4 E0137E 0 +OP4 E0137F 0 +OP4 E01380 0 +OP4 E01381 0 +OP4 E01382 0 +OP4 E01383 0 +OP4 E01384 0 +OP4 E01385 0 +OP4 E01386 0 +OP4 E01387 0 +OP4 E01388 0 +OP4 E01389 0 +OP4 E0138A 0 +OP4 E0138B 0 +OP4 E0138C 0 +OP4 E0138D 0 +OP4 E0138E 0 +OP4 E0138F 0 +OP4 E01390 0 +OP4 E01391 0 +OP4 E01392 0 +OP4 E01393 0 +OP4 E01394 0 +OP4 E01395 0 +OP4 E01396 0 +OP4 E01397 0 +OP4 E01398 0 +OP4 E01399 0 +OP4 E0139A 0 +OP4 E0139B 0 +OP4 E0139C 0 +OP4 E0139D 0 +OP4 E0139E 0 +OP4 E0139F 0 +OP4 E013A0 0 +OP4 E013A1 0 +OP4 E013A2 0 +OP4 E013A3 0 +OP4 E013A4 0 +OP4 E013A5 0 +OP4 E013A6 0 +OP4 E013A7 0 +OP4 E013A8 0 +OP4 E013A9 0 +OP4 E013AA 0 +OP4 E013AB 0 +OP4 E013AC 0 +OP4 E013AD 0 +OP4 E013AE 0 +OP4 E013AF 0 +OP4 E013B0 0 +OP4 E013B1 0 +OP4 E013B2 0 +OP4 E013B3 0 +OP4 E013B4 0 +OP4 E013B5 0 +OP4 E013B6 0 +OP4 E013B7 0 +OP4 E013B8 0 +OP4 E013B9 0 +OP4 E013BA 0 +OP4 E013BB 0 +OP4 E013BC 0 +OP4 E013BD 0 +OP4 E013BE 0 +OP4 E013BF 0 +OP4 E013C0 0 +OP4 E013C1 0 +OP4 E013C2 0 +OP4 E013C3 0 +OP4 E013C4 0 +OP4 E013C5 0 +OP4 E013C6 0 +OP4 E013C7 0 +OP4 E013C8 0 +OP4 E013C9 0 +OP4 E013CA 0 +OP4 E013CB 0 +OP4 E013CC 0 +OP4 E013CD 0 +OP4 E013CE 0 +OP4 E013CF 0 +OP4 E013D0 0 +OP4 E013D1 0 +OP4 E013D2 0 +OP4 E013D3 0 +OP4 E013D4 0 +OP4 E013D5 0 +OP4 E013D6 0 +OP4 E013D7 0 +OP4 E013D8 0 +OP4 E013D9 0 +OP4 E013DA 0 +OP4 E013DB 0 +OP4 E013DC 0 +OP4 E013DD 0 +OP4 E013DE 0 +OP4 E013DF 0 +OP4 E013E0 0 +OP4 E013E1 0 +OP4 E013E2 0 +OP4 E013E3 0 +OP4 E013E4 0 +OP4 E013E5 0 +OP4 E013E6 0 +OP4 E013E7 0 +OP4 E013E8 0 +OP4 E013E9 0 +OP4 E013EA 0 +OP4 E013EB 0 +OP4 E013EC 0 +OP4 E013ED 0 +OP4 E013EE 0 +OP4 E013EF 0 +OP4 E013F0 0 +OP4 E013F1 0 +OP4 E013F2 0 +OP4 E013F3 0 +OP4 E013F4 0 +OP4 E013F5 0 +OP4 E013F6 0 +OP4 E013F7 0 +OP4 E013F8 0 +OP4 E013F9 0 +OP4 E013FA 0 +OP4 E013FB 0 +OP4 E013FC 0 +OP4 E013FD 0 +OP4 E013FE 0 +OP4 E013FF 0 +OP4 E01400 0 +OP4 E01401 0 +OP4 E01402 0 +OP4 E01403 0 +OP4 E01404 0 +OP4 E01405 0 +OP4 E01406 0 +OP4 E01407 0 +OP4 E01408 0 +OP4 E01409 0 +OP4 E0140A 0 +OP4 E0140B 0 +OP4 E0140C 0 +OP4 E0140D 0 +OP4 E0140E 0 +OP4 E0140F 0 +OP4 E01410 0 +OP4 E01411 0 +OP4 E01412 0 +OP4 E01413 0 +OP4 E01414 0 +OP4 E01415 0 +OP4 E01416 0 +OP4 E01417 0 +OP4 E01418 0 +OP4 E01419 0 +OP4 E0141A 0 +OP4 E0141B 0 +OP4 E0141C 0 +OP4 E0141D 0 +OP4 E0141E 0 +OP4 E0141F 0 +OP4 E01420 0 +OP4 E01421 0 +OP4 E01422 0 +OP4 E01423 0 +OP4 E01424 0 +OP4 E01425 0 +OP4 E01426 0 +OP4 E01427 0 +OP4 E01428 0 +OP4 E01429 0 +OP4 E0142A 0 +OP4 E0142B 0 +OP4 E0142C 0 +OP4 E0142D 0 +OP4 E0142E 0 +OP4 E0142F 0 +OP4 E01430 0 +OP4 E01431 0 +OP4 E01432 0 +OP4 E01433 0 +OP4 E01434 0 +OP4 E01435 0 +OP4 E01436 0 +OP4 E01437 0 +OP4 E01438 0 +OP4 E01439 0 +OP4 E0143A 0 +OP4 E0143B 0 +OP4 E0143C 0 +OP4 E0143D 0 +OP4 E0143E 0 +OP4 E0143F 0 +OP4 E01440 0 +OP4 E01441 0 +OP4 E01442 0 +OP4 E01443 0 +OP4 E01444 0 +OP4 E01445 0 +OP4 E01446 0 +OP4 E01447 0 +OP4 E01448 0 +OP4 E01449 0 +OP4 E0144A 0 +OP4 E0144B 0 +OP4 E0144C 0 +OP4 E0144D 0 +OP4 E0144E 0 +OP4 E0144F 0 +OP4 E01450 0 +OP4 E01451 0 +OP4 E01452 0 +OP4 E01453 0 +OP4 E01454 0 +OP4 E01455 0 +OP4 E01456 0 +OP4 E01457 0 +OP4 E01458 0 +OP4 E01459 0 +OP4 E0145A 0 +OP4 E0145B 0 +OP4 E0145C 0 +OP4 E0145D 0 +OP4 E0145E 0 +OP4 E0145F 0 +OP4 E01460 0 +OP4 E01461 0 +OP4 E01462 0 +OP4 E01463 0 +OP4 E01464 0 +OP4 E01465 0 +OP4 E01466 0 +OP4 E01467 0 +OP4 E01468 0 +OP4 E01469 0 +OP4 E0146A 0 +OP4 E0146B 0 +OP4 E0146C 0 +OP4 E0146D 0 +OP4 E0146E 0 +OP4 E0146F 0 +OP4 E01470 0 +OP4 E01471 0 +OP4 E01472 0 +OP4 E01473 0 +OP4 E01474 0 +OP4 E01475 0 +OP4 E01476 0 +OP4 E01477 0 +OP4 E01478 0 +OP4 E01479 0 +OP4 E0147A 0 +OP4 E0147B 0 +OP4 E0147C 0 +OP4 E0147D 0 +OP4 E0147E 0 +OP4 E0147F 0 +OP4 E01480 0 +OP4 E01481 0 +OP4 E01482 0 +OP4 E01483 0 +OP4 E01484 0 +OP4 E01485 0 +OP4 E01486 0 +OP4 E01487 0 +OP4 E01488 0 +OP4 E01489 0 +OP4 E0148A 0 +OP4 E0148B 0 +OP4 E0148C 0 +OP4 E0148D 0 +OP4 E0148E 0 +OP4 E0148F 0 +OP4 E01490 0 +OP4 E01491 0 +OP4 E01492 0 +OP4 E01493 0 +OP4 E01494 0 +OP4 E01495 0 +OP4 E01496 0 +OP4 E01497 0 +OP4 E01498 0 +OP4 E01499 0 +OP4 E0149A 0 +OP4 E0149B 0 +OP4 E0149C 0 +OP4 E0149D 0 +OP4 E0149E 0 +OP4 E0149F 0 +OP4 E014A0 0 +OP4 E014A1 0 +OP4 E014A2 0 +OP4 E014A3 0 +OP4 E014A4 0 +OP4 E014A5 0 +OP4 E014A6 0 +OP4 E014A7 0 +OP4 E014A8 0 +OP4 E014A9 0 +OP4 E014AA 0 +OP4 E014AB 0 +OP4 E014AC 0 +OP4 E014AD 0 +OP4 E014AE 0 +OP4 E014AF 0 +OP4 E014B0 0 +OP4 E014B1 0 +OP4 E014B2 0 +OP4 E014B3 0 +OP4 E014B4 0 +OP4 E014B5 0 +OP4 E014B6 0 +OP4 E014B7 0 +OP4 E014B8 0 +OP4 E014B9 0 +OP4 E014BA 0 +OP4 E014BB 0 +OP4 E014BC 0 +OP4 E014BD 0 +OP4 E014BE 0 +OP4 E014BF 0 +OP4 E014C0 0 +OP4 E014C1 0 +OP4 E014C2 0 +OP4 E014C3 0 +OP4 E014C4 0 +OP4 E014C5 0 +OP4 E014C6 0 +OP4 E014C7 0 +OP4 E014C8 0 +OP4 E014C9 0 +OP4 E014CA 0 +OP4 E014CB 0 +OP4 E014CC 0 +OP4 E014CD 0 +OP4 E014CE 0 +OP4 E014CF 0 +OP4 E014D0 0 +OP4 E014D1 0 +OP4 E014D2 0 +OP4 E014D3 0 +OP4 E014D4 0 +OP4 E014D5 0 +OP4 E014D6 0 +OP4 E014D7 0 +OP4 E014D8 0 +OP4 E014D9 0 +OP4 E014DA 0 +OP4 E014DB 0 +OP4 E014DC 0 +OP4 E014DD 0 +OP4 E014DE 0 +OP4 E014DF 0 +OP4 E014E0 0 +OP4 E014E1 0 +OP4 E014E2 0 +OP4 E014E3 0 +OP4 E014E4 0 +OP4 E014E5 0 +OP4 E014E6 0 +OP4 E014E7 0 +OP4 E014E8 0 +OP4 E014E9 0 +OP4 E014EA 0 +OP4 E014EB 0 +OP4 E014EC 0 +OP4 E014ED 0 +OP4 E014EE 0 +OP4 E014EF 0 +OP4 E014F0 0 +OP4 E014F1 0 +OP4 E014F2 0 +OP4 E014F3 0 +OP4 E014F4 0 +OP4 E014F5 0 +OP4 E014F6 0 +OP4 E014F7 0 +OP4 E014F8 0 +OP4 E014F9 0 +OP4 E014FA 0 +OP4 E014FB 0 +OP4 E014FC 0 +OP4 E014FD 0 +OP4 E014FE 0 +OP4 E014FF 0 +OP4 E01500 0 +OP4 E01501 0 +OP4 E01502 0 +OP4 E01503 0 +OP4 E01504 0 +OP4 E01505 0 +OP4 E01506 0 +OP4 E01507 0 +OP4 E01508 0 +OP4 E01509 0 +OP4 E0150A 0 +OP4 E0150B 0 +OP4 E0150C 0 +OP4 E0150D 0 +OP4 E0150E 0 +OP4 E0150F 0 +OP4 E01510 0 +OP4 E01511 0 +OP4 E01512 0 +OP4 E01513 0 +OP4 E01514 0 +OP4 E01515 0 +OP4 E01516 0 +OP4 E01517 0 +OP4 E01518 0 +OP4 E01519 0 +OP4 E0151A 0 +OP4 E0151B 0 +OP4 E0151C 0 +OP4 E0151D 0 +OP4 E0151E 0 +OP4 E0151F 0 +OP4 E01520 0 +OP4 E01521 0 +OP4 E01522 0 +OP4 E01523 0 +OP4 E01524 0 +OP4 E01525 0 +OP4 E01526 0 +OP4 E01527 0 +OP4 E01528 0 +OP4 E01529 0 +OP4 E0152A 0 +OP4 E0152B 0 +OP4 E0152C 0 +OP4 E0152D 0 +OP4 E0152E 0 +OP4 E0152F 0 +OP4 E01530 0 +OP4 E01531 0 +OP4 E01532 0 +OP4 E01533 0 +OP4 E01534 0 +OP4 E01535 0 +OP4 E01536 0 +OP4 E01537 0 +OP4 E01538 0 +OP4 E01539 0 +OP4 E0153A 0 +OP4 E0153B 0 +OP4 E0153C 0 +OP4 E0153D 0 +OP4 E0153E 0 +OP4 E0153F 0 +OP4 E01540 0 +OP4 E01541 0 +OP4 E01542 0 +OP4 E01543 0 +OP4 E01544 0 +OP4 E01545 0 +OP4 E01546 0 +OP4 E01547 0 +OP4 E01548 0 +OP4 E01549 0 +OP4 E0154A 0 +OP4 E0154B 0 +OP4 E0154C 0 +OP4 E0154D 0 +OP4 E0154E 0 +OP4 E0154F 0 +OP4 E01550 0 +OP4 E01551 0 +OP4 E01552 0 +OP4 E01553 0 +OP4 E01554 0 +OP4 E01555 0 +OP4 E01556 0 +OP4 E01557 0 +OP4 E01558 0 +OP4 E01559 0 +OP4 E0155A 0 +OP4 E0155B 0 +OP4 E0155C 0 +OP4 E0155D 0 +OP4 E0155E 0 +OP4 E0155F 0 +OP4 E01560 0 +OP4 E01561 0 +OP4 E01562 0 +OP4 E01563 0 +OP4 E01564 0 +OP4 E01565 0 +OP4 E01566 0 +OP4 E01567 0 +OP4 E01568 0 +OP4 E01569 0 +OP4 E0156A 0 +OP4 E0156B 0 +OP4 E0156C 0 +OP4 E0156D 0 +OP4 E0156E 0 +OP4 E0156F 0 +OP4 E01570 0 +OP4 E01571 0 +OP4 E01572 0 +OP4 E01573 0 +OP4 E01574 0 +OP4 E01575 0 +OP4 E01576 0 +OP4 E01577 0 +OP4 E01578 0 +OP4 E01579 0 +OP4 E0157A 0 +OP4 E0157B 0 +OP4 E0157C 0 +OP4 E0157D 0 +OP4 E0157E 0 +OP4 E0157F 0 +OP4 E01580 0 +OP4 E01581 0 +OP4 E01582 0 +OP4 E01583 0 +OP4 E01584 0 +OP4 E01585 0 +OP4 E01586 0 +OP4 E01587 0 +OP4 E01588 0 +OP4 E01589 0 +OP4 E0158A 0 +OP4 E0158B 0 +OP4 E0158C 0 +OP4 E0158D 0 +OP4 E0158E 0 +OP4 E0158F 0 +OP4 E01590 0 +OP4 E01591 0 +OP4 E01592 0 +OP4 E01593 0 +OP4 E01594 0 +OP4 E01595 0 +OP4 E01596 0 +OP4 E01597 0 +OP4 E01598 0 +OP4 E01599 0 +OP4 E0159A 0 +OP4 E0159B 0 +OP4 E0159C 0 +OP4 E0159D 0 +OP4 E0159E 0 +OP4 E0159F 0 +OP4 E015A0 0 +OP4 E015A1 0 +OP4 E015A2 0 +OP4 E015A3 0 +OP4 E015A4 0 +OP4 E015A5 0 +OP4 E015A6 0 +OP4 E015A7 0 +OP4 E015A8 0 +OP4 E015A9 0 +OP4 E015AA 0 +OP4 E015AB 0 +OP4 E015AC 0 +OP4 E015AD 0 +OP4 E015AE 0 +OP4 E015AF 0 +OP4 E015B0 0 +OP4 E015B1 0 +OP4 E015B2 0 +OP4 E015B3 0 +OP4 E015B4 0 +OP4 E015B5 0 +OP4 E015B6 0 +OP4 E015B7 0 +OP4 E015B8 0 +OP4 E015B9 0 +OP4 E015BA 0 +OP4 E015BB 0 +OP4 E015BC 0 +OP4 E015BD 0 +OP4 E015BE 0 +OP4 E015BF 0 +OP4 E015C0 0 +OP4 E015C1 0 +OP4 E015C2 0 +OP4 E015C3 0 +OP4 E015C4 0 +OP4 E015C5 0 +OP4 E015C6 0 +OP4 E015C7 0 +OP4 E015C8 0 +OP4 E015C9 0 +OP4 E015CA 0 +OP4 E015CB 0 +OP4 E015CC 0 +OP4 E015CD 0 +OP4 E015CE 0 +OP4 E015CF 0 +OP4 E015D0 0 +OP4 E015D1 0 +OP4 E015D2 0 +OP4 E015D3 0 +OP4 E015D4 0 +OP4 E015D5 0 +OP4 E015D6 0 +OP4 E015D7 0 +OP4 E015D8 0 +OP4 E015D9 0 +OP4 E015DA 0 +OP4 E015DB 0 +OP4 E015DC 0 +OP4 E015DD 0 +OP4 E015DE 0 +OP4 E015DF 0 +OP4 E015E0 0 +OP4 E015E1 0 +OP4 E015E2 0 +OP4 E015E3 0 +OP4 E015E4 0 +OP4 E015E5 0 +OP4 E015E6 0 +OP4 E015E7 0 +OP4 E015E8 0 +OP4 E015E9 0 +OP4 E015EA 0 +OP4 E015EB 0 +OP4 E015EC 0 +OP4 E015ED 0 +OP4 E015EE 0 +OP4 E015EF 0 +OP4 E015F0 0 +OP4 E015F1 0 +OP4 E015F2 0 +OP4 E015F3 0 +OP4 E015F4 0 +OP4 E015F5 0 +OP4 E015F6 0 +OP4 E015F7 0 +OP4 E015F8 0 +OP4 E015F9 0 +OP4 E015FA 0 +OP4 E015FB 0 +OP4 E015FC 0 +OP4 E015FD 0 +OP4 E015FE 0 +OP4 E015FF 0 +OP4 E01600 0 +OP4 E01601 0 +OP4 E01602 0 +OP4 E01603 0 +OP4 E01604 0 +OP4 E01605 0 +OP4 E01606 0 +OP4 E01607 0 +OP4 E01608 0 +OP4 E01609 0 +OP4 E0160A 0 +OP4 E0160B 0 +OP4 E0160C 0 +OP4 E0160D 0 +OP4 E0160E 0 +OP4 E0160F 0 +OP4 E01610 0 +OP4 E01611 0 +OP4 E01612 0 +OP4 E01613 0 +OP4 E01614 0 +OP4 E01615 0 +OP4 E01616 0 +OP4 E01617 0 +OP4 E01618 0 +OP4 E01619 0 +OP4 E0161A 0 +OP4 E0161B 0 +OP4 E0161C 0 +OP4 E0161D 0 +OP4 E0161E 0 +OP4 E0161F 0 +OP4 E01620 0 +OP4 E01621 0 +OP4 E01622 0 +OP4 E01623 0 +OP4 E01624 0 +OP4 E01625 0 +OP4 E01626 0 +OP4 E01627 0 +OP4 E01628 0 +OP4 E01629 0 +OP4 E0162A 0 +OP4 E0162B 0 +OP4 E0162C 0 +OP4 E0162D 0 +OP4 E0162E 0 +OP4 E0162F 0 +OP4 E01630 0 +OP4 E01631 0 +OP4 E01632 0 +OP4 E01633 0 +OP4 E01634 0 +OP4 E01635 0 +OP4 E01636 0 +OP4 E01637 0 +OP4 E01638 0 +OP4 E01639 0 +OP4 E0163A 0 +OP4 E0163B 0 +OP4 E0163C 0 +OP4 E0163D 0 +OP4 E0163E 0 +OP4 E0163F 0 +OP4 E01640 0 +OP4 E01641 0 +OP4 E01642 0 +OP4 E01643 0 +OP4 E01644 0 +OP4 E01645 0 +OP4 E01646 0 +OP4 E01647 0 +OP4 E01648 0 +OP4 E01649 0 +OP4 E0164A 0 +OP4 E0164B 0 +OP4 E0164C 0 +OP4 E0164D 0 +OP4 E0164E 0 +OP4 E0164F 0 +OP4 E01650 0 +OP4 E01651 0 +OP4 E01652 0 +OP4 E01653 0 +OP4 E01654 0 +OP4 E01655 0 +OP4 E01656 0 +OP4 E01657 0 +OP4 E01658 0 +OP4 E01659 0 +OP4 E0165A 0 +OP4 E0165B 0 +OP4 E0165C 0 +OP4 E0165D 0 +OP4 E0165E 0 +OP4 E0165F 0 +OP4 E01660 0 +OP4 E01661 0 +OP4 E01662 0 +OP4 E01663 0 +OP4 E01664 0 +OP4 E01665 0 +OP4 E01666 0 +OP4 E01667 0 +OP4 E01668 0 +OP4 E01669 0 +OP4 E0166A 0 +OP4 E0166B 0 +OP4 E0166C 0 +OP4 E0166D 0 +OP4 E0166E 0 +OP4 E0166F 0 +OP4 E01670 0 +OP4 E01671 0 +OP4 E01672 0 +OP4 E01673 0 +OP4 E01674 0 +OP4 E01675 0 +OP4 E01676 0 +OP4 E01677 0 +OP4 E01678 0 +OP4 E01679 0 +OP4 E0167A 0 +OP4 E0167B 0 +OP4 E0167C 0 +OP4 E0167D 0 +OP4 E0167E 0 +OP4 E0167F 0 +OP4 E01680 0 +OP4 E01681 0 +OP4 E01682 0 +OP4 E01683 0 +OP4 E01684 0 +OP4 E01685 0 +OP4 E01686 0 +OP4 E01687 0 +OP4 E01688 0 +OP4 E01689 0 +OP4 E0168A 0 +OP4 E0168B 0 +OP4 E0168C 0 +OP4 E0168D 0 +OP4 E0168E 0 +OP4 E0168F 0 +OP4 E01690 0 +OP4 E01691 0 +OP4 E01692 0 +OP4 E01693 0 +OP4 E01694 0 +OP4 E01695 0 +OP4 E01696 0 +OP4 E01697 0 +OP4 E01698 0 +OP4 E01699 0 +OP4 E0169A 0 +OP4 E0169B 0 +OP4 E0169C 0 +OP4 E0169D 0 +OP4 E0169E 0 +OP4 E0169F 0 +OP4 E016A0 0 +OP4 E016A1 0 +OP4 E016A2 0 +OP4 E016A3 0 +OP4 E016A4 0 +OP4 E016A5 0 +OP4 E016A6 0 +OP4 E016A7 0 +OP4 E016A8 0 +OP4 E016A9 0 +OP4 E016AA 0 +OP4 E016AB 0 +OP4 E016AC 0 +OP4 E016AD 0 +OP4 E016AE 0 +OP4 E016AF 0 +OP4 E016B0 0 +OP4 E016B1 0 +OP4 E016B2 0 +OP4 E016B3 0 +OP4 E016B4 0 +OP4 E016B5 0 +OP4 E016B6 0 +OP4 E016B7 0 +OP4 E016B8 0 +OP4 E016B9 0 +OP4 E016BA 0 +OP4 E016BB 0 +OP4 E016BC 0 +OP4 E016BD 0 +OP4 E016BE 0 +OP4 E016BF 0 +OP4 E016C0 0 +OP4 E016C1 0 +OP4 E016C2 0 +OP4 E016C3 0 +OP4 E016C4 0 +OP4 E016C5 0 +OP4 E016C6 0 +OP4 E016C7 0 +OP4 E016C8 0 +OP4 E016C9 0 +OP4 E016CA 0 +OP4 E016CB 0 +OP4 E016CC 0 +OP4 E016CD 0 +OP4 E016CE 0 +OP4 E016CF 0 +OP4 E016D0 0 +OP4 E016D1 0 +OP4 E016D2 0 +OP4 E016D3 0 +OP4 E016D4 0 +OP4 E016D5 0 +OP4 E016D6 0 +OP4 E016D7 0 +OP4 E016D8 0 +OP4 E016D9 0 +OP4 E016DA 0 +OP4 E016DB 0 +OP4 E016DC 0 +OP4 E016DD 0 +OP4 E016DE 0 +OP4 E016DF 0 +OP4 E016E0 0 +OP4 E016E1 0 +OP4 E016E2 0 +OP4 E016E3 0 +OP4 E016E4 0 +OP4 E016E5 0 +OP4 E016E6 0 +OP4 E016E7 0 +OP4 E016E8 0 +OP4 E016E9 0 +OP4 E016EA 0 +OP4 E016EB 0 +OP4 E016EC 0 +OP4 E016ED 0 +OP4 E016EE 0 +OP4 E016EF 0 +OP4 E016F0 0 +OP4 E016F1 0 +OP4 E016F2 0 +OP4 E016F3 0 +OP4 E016F4 0 +OP4 E016F5 0 +OP4 E016F6 0 +OP4 E016F7 0 +OP4 E016F8 0 +OP4 E016F9 0 +OP4 E016FA 0 +OP4 E016FB 0 +OP4 E016FC 0 +OP4 E016FD 0 +OP4 E016FE 0 +OP4 E016FF 0 +OP4 E01700 0 +OP4 E01701 0 +OP4 E01702 0 +OP4 E01703 0 +OP4 E01704 0 +OP4 E01705 0 +OP4 E01706 0 +OP4 E01707 0 +OP4 E01708 0 +OP4 E01709 0 +OP4 E0170A 0 +OP4 E0170B 0 +OP4 E0170C 0 +OP4 E0170D 0 +OP4 E0170E 0 +OP4 E0170F 0 +OP4 E01710 0 +OP4 E01711 0 +OP4 E01712 0 +OP4 E01713 0 +OP4 E01714 0 +OP4 E01715 0 +OP4 E01716 0 +OP4 E01717 0 +OP4 E01718 0 +OP4 E01719 0 +OP4 E0171A 0 +OP4 E0171B 0 +OP4 E0171C 0 +OP4 E0171D 0 +OP4 E0171E 0 +OP4 E0171F 0 +OP4 E01720 0 +OP4 E01721 0 +OP4 E01722 0 +OP4 E01723 0 +OP4 E01724 0 +OP4 E01725 0 +OP4 E01726 0 +OP4 E01727 0 +OP4 E01728 0 +OP4 E01729 0 +OP4 E0172A 0 +OP4 E0172B 0 +OP4 E0172C 0 +OP4 E0172D 0 +OP4 E0172E 0 +OP4 E0172F 0 +OP4 E01730 0 +OP4 E01731 0 +OP4 E01732 0 +OP4 E01733 0 +OP4 E01734 0 +OP4 E01735 0 +OP4 E01736 0 +OP4 E01737 0 +OP4 E01738 0 +OP4 E01739 0 +OP4 E0173A 0 +OP4 E0173B 0 +OP4 E0173C 0 +OP4 E0173D 0 +OP4 E0173E 0 +OP4 E0173F 0 +OP4 E01740 0 +OP4 E01741 0 +OP4 E01742 0 +OP4 E01743 0 +OP4 E01744 0 +OP4 E01745 0 +OP4 E01746 0 +OP4 E01747 0 +OP4 E01748 0 +OP4 E01749 0 +OP4 E0174A 0 +OP4 E0174B 0 +OP4 E0174C 0 +OP4 E0174D 0 +OP4 E0174E 0 +OP4 E0174F 0 +OP4 E01750 0 +OP4 E01751 0 +OP4 E01752 0 +OP4 E01753 0 +OP4 E01754 0 +OP4 E01755 0 +OP4 E01756 0 +OP4 E01757 0 +OP4 E01758 0 +OP4 E01759 0 +OP4 E0175A 0 +OP4 E0175B 0 +OP4 E0175C 0 +OP4 E0175D 0 +OP4 E0175E 0 +OP4 E0175F 0 +OP4 E01760 0 +OP4 E01761 0 +OP4 E01762 0 +OP4 E01763 0 +OP4 E01764 0 +OP4 E01765 0 +OP4 E01766 0 +OP4 E01767 0 +OP4 E01768 0 +OP4 E01769 0 +OP4 E0176A 0 +OP4 E0176B 0 +OP4 E0176C 0 +OP4 E0176D 0 +OP4 E0176E 0 +OP4 E0176F 0 +OP4 E01770 0 +OP4 E01771 0 +OP4 E01772 0 +OP4 E01773 0 +OP4 E01774 0 +OP4 E01775 0 +OP4 E01776 0 +OP4 E01777 0 +OP4 E01778 0 +OP4 E01779 0 +OP4 E0177A 0 +OP4 E0177B 0 +OP4 E0177C 0 +OP4 E0177D 0 +OP4 E0177E 0 +OP4 E0177F 0 +OP4 E01780 0 +OP4 E01781 0 +OP4 E01782 0 +OP4 E01783 0 +OP4 E01784 0 +OP4 E01785 0 +OP4 E01786 0 +OP4 E01787 0 +OP4 E01788 0 +OP4 E01789 0 +OP4 E0178A 0 +OP4 E0178B 0 +OP4 E0178C 0 +OP4 E0178D 0 +OP4 E0178E 0 +OP4 E0178F 0 +OP4 E01790 0 +OP4 E01791 0 +OP4 E01792 0 +OP4 E01793 0 +OP4 E01794 0 +OP4 E01795 0 +OP4 E01796 0 +OP4 E01797 0 +OP4 E01798 0 +OP4 E01799 0 +OP4 E0179A 0 +OP4 E0179B 0 +OP4 E0179C 0 +OP4 E0179D 0 +OP4 E0179E 0 +OP4 E0179F 0 +OP4 E017A0 0 +OP4 E017A1 0 +OP4 E017A2 0 +OP4 E017A3 0 +OP4 E017A4 0 +OP4 E017A5 0 +OP4 E017A6 0 +OP4 E017A7 0 +OP4 E017A8 0 +OP4 E017A9 0 +OP4 E017AA 0 +OP4 E017AB 0 +OP4 E017AC 0 +OP4 E017AD 0 +OP4 E017AE 0 +OP4 E017AF 0 +OP4 E017B0 0 +OP4 E017B1 0 +OP4 E017B2 0 +OP4 E017B3 0 +OP4 E017B4 0 +OP4 E017B5 0 +OP4 E017B6 0 +OP4 E017B7 0 +OP4 E017B8 0 +OP4 E017B9 0 +OP4 E017BA 0 +OP4 E017BB 0 +OP4 E017BC 0 +OP4 E017BD 0 +OP4 E017BE 0 +OP4 E017BF 0 +OP4 E017C0 0 +OP4 E017C1 0 +OP4 E017C2 0 +OP4 E017C3 0 +OP4 E017C4 0 +OP4 E017C5 0 +OP4 E017C6 0 +OP4 E017C7 0 +OP4 E017C8 0 +OP4 E017C9 0 +OP4 E017CA 0 +OP4 E017CB 0 +OP4 E017CC 0 +OP4 E017CD 0 +OP4 E017CE 0 +OP4 E017CF 0 +OP4 E017D0 0 +OP4 E017D1 0 +OP4 E017D2 0 +OP4 E017D3 0 +OP4 E017D4 0 +OP4 E017D5 0 +OP4 E017D6 0 +OP4 E017D7 0 +OP4 E017D8 0 +OP4 E017D9 0 +OP4 E017DA 0 +OP4 E017DB 0 +OP4 E017DC 0 +OP4 E017DD 0 +OP4 E017DE 0 +OP4 E017DF 0 +OP4 E017E0 0 +OP4 E017E1 0 +OP4 E017E2 0 +OP4 E017E3 0 +OP4 E017E4 0 +OP4 E017E5 0 +OP4 E017E6 0 +OP4 E017E7 0 +OP4 E017E8 0 +OP4 E017E9 0 +OP4 E017EA 0 +OP4 E017EB 0 +OP4 E017EC 0 +OP4 E017ED 0 +OP4 E017EE 0 +OP4 E017EF 0 +OP4 E017F0 0 +OP4 E017F1 0 +OP4 E017F2 0 +OP4 E017F3 0 +OP4 E017F4 0 +OP4 E017F5 0 +OP4 E017F6 0 +OP4 E017F7 0 +OP4 E017F8 0 +OP4 E017F9 0 +OP4 E017FA 0 +OP4 E017FB 0 +OP4 E017FC 0 +OP4 E017FD 0 +OP4 E017FE 0 +OP4 E017FF 0 +OP4 E01800 0 +OP4 E01801 0 +OP4 E01802 0 +OP4 E01803 0 +OP4 E01804 0 +OP4 E01805 0 +OP4 E01806 0 +OP4 E01807 0 +OP4 E01808 0 +OP4 E01809 0 +OP4 E0180A 0 +OP4 E0180B 0 +OP4 E0180C 0 +OP4 E0180D 0 +OP4 E0180E 0 +OP4 E0180F 0 +OP4 E01810 0 +OP4 E01811 0 +OP4 E01812 0 +OP4 E01813 0 +OP4 E01814 0 +OP4 E01815 0 +OP4 E01816 0 +OP4 E01817 0 +OP4 E01818 0 +OP4 E01819 0 +OP4 E0181A 0 +OP4 E0181B 0 +OP4 E0181C 0 +OP4 E0181D 0 +OP4 E0181E 0 +OP4 E0181F 0 +OP4 E01820 0 +OP4 E01821 0 +OP4 E01822 0 +OP4 E01823 0 +OP4 E01824 0 +OP4 E01825 0 +OP4 E01826 0 +OP4 E01827 0 +OP4 E01828 0 +OP4 E01829 0 +OP4 E0182A 0 +OP4 E0182B 0 +OP4 E0182C 0 +OP4 E0182D 0 +OP4 E0182E 0 +OP4 E0182F 0 +OP4 E01830 0 +OP4 E01831 0 +OP4 E01832 0 +OP4 E01833 0 +OP4 E01834 0 +OP4 E01835 0 +OP4 E01836 0 +OP4 E01837 0 +OP4 E01838 0 +OP4 E01839 0 +OP4 E0183A 0 +OP4 E0183B 0 +OP4 E0183C 0 +OP4 E0183D 0 +OP4 E0183E 0 +OP4 E0183F 0 +OP4 E01840 0 +OP4 E01841 0 +OP4 E01842 0 +OP4 E01843 0 +OP4 E01844 0 +OP4 E01845 0 +OP4 E01846 0 +OP4 E01847 0 +OP4 E01848 0 +OP4 E01849 0 +OP4 E0184A 0 +OP4 E0184B 0 +OP4 E0184C 0 +OP4 E0184D 0 +OP4 E0184E 0 +OP4 E0184F 0 +OP4 E01850 0 +OP4 E01851 0 +OP4 E01852 0 +OP4 E01853 0 +OP4 E01854 0 +OP4 E01855 0 +OP4 E01856 0 +OP4 E01857 0 +OP4 E01858 0 +OP4 E01859 0 +OP4 E0185A 0 +OP4 E0185B 0 +OP4 E0185C 0 +OP4 E0185D 0 +OP4 E0185E 0 +OP4 E0185F 0 +OP4 E01860 0 +OP4 E01861 0 +OP4 E01862 0 +OP4 E01863 0 +OP4 E01864 0 +OP4 E01865 0 +OP4 E01866 0 +OP4 E01867 0 +OP4 E01868 0 +OP4 E01869 0 +OP4 E0186A 0 +OP4 E0186B 0 +OP4 E0186C 0 +OP4 E0186D 0 +OP4 E0186E 0 +OP4 E0186F 0 +OP4 E01870 0 +OP4 E01871 0 +OP4 E01872 0 +OP4 E01873 0 +OP4 E01874 0 +OP4 E01875 0 +OP4 E01876 0 +OP4 E01877 0 +OP4 E01878 0 +OP4 E01879 0 +OP4 E0187A 0 +OP4 E0187B 0 +OP4 E0187C 0 +OP4 E0187D 0 +OP4 E0187E 0 +OP4 E0187F 0 +OP4 E01880 0 +OP4 E01881 0 +OP4 E01882 0 +OP4 E01883 0 +OP4 E01884 0 +OP4 E01885 0 +OP4 E01886 0 +OP4 E01887 0 +OP4 E01888 0 +OP4 E01889 0 +OP4 E0188A 0 +OP4 E0188B 0 +OP4 E0188C 0 +OP4 E0188D 0 +OP4 E0188E 0 +OP4 E0188F 0 +OP4 E01890 0 +OP4 E01891 0 +OP4 E01892 0 +OP4 E01893 0 +OP4 E01894 0 +OP4 E01895 0 +OP4 E01896 0 +OP4 E01897 0 +OP4 E01898 0 +OP4 E01899 0 +OP4 E0189A 0 +OP4 E0189B 0 +OP4 E0189C 0 +OP4 E0189D 0 +OP4 E0189E 0 +OP4 E0189F 0 +OP4 E018A0 0 +OP4 E018A1 0 +OP4 E018A2 0 +OP4 E018A3 0 +OP4 E018A4 0 +OP4 E018A5 0 +OP4 E018A6 0 +OP4 E018A7 0 +OP4 E018A8 0 +OP4 E018A9 0 +OP4 E018AA 0 +OP4 E018AB 0 +OP4 E018AC 0 +OP4 E018AD 0 +OP4 E018AE 0 +OP4 E018AF 0 +OP4 E018B0 0 +OP4 E018B1 0 +OP4 E018B2 0 +OP4 E018B3 0 +OP4 E018B4 0 +OP4 E018B5 0 +OP4 E018B6 0 +OP4 E018B7 0 +OP4 E018B8 0 +OP4 E018B9 0 +OP4 E018BA 0 +OP4 E018BB 0 +OP4 E018BC 0 +OP4 E018BD 0 +OP4 E018BE 0 +OP4 E018BF 0 +OP4 E018C0 0 +OP4 E018C1 0 +OP4 E018C2 0 +OP4 E018C3 0 +OP4 E018C4 0 +OP4 E018C5 0 +OP4 E018C6 0 +OP4 E018C7 0 +OP4 E018C8 0 +OP4 E018C9 0 +OP4 E018CA 0 +OP4 E018CB 0 +OP4 E018CC 0 +OP4 E018CD 0 +OP4 E018CE 0 +OP4 E018CF 0 +OP4 E018D0 0 +OP4 E018D1 0 +OP4 E018D2 0 +OP4 E018D3 0 +OP4 E018D4 0 +OP4 E018D5 0 +OP4 E018D6 0 +OP4 E018D7 0 +OP4 E018D8 0 +OP4 E018D9 0 +OP4 E018DA 0 +OP4 E018DB 0 +OP4 E018DC 0 +OP4 E018DD 0 +OP4 E018DE 0 +OP4 E018DF 0 +OP4 E018E0 0 +OP4 E018E1 0 +OP4 E018E2 0 +OP4 E018E3 0 +OP4 E018E4 0 +OP4 E018E5 0 +OP4 E018E6 0 +OP4 E018E7 0 +OP4 E018E8 0 +OP4 E018E9 0 +OP4 E018EA 0 +OP4 E018EB 0 +OP4 E018EC 0 +OP4 E018ED 0 +OP4 E018EE 0 +OP4 E018EF 0 +OP4 E018F0 0 +OP4 E018F1 0 +OP4 E018F2 0 +OP4 E018F3 0 +OP4 E018F4 0 +OP4 E018F5 0 +OP4 E018F6 0 +OP4 E018F7 0 +OP4 E018F8 0 +OP4 E018F9 0 +OP4 E018FA 0 +OP4 E018FB 0 +OP4 E018FC 0 +OP4 E018FD 0 +OP4 E018FE 0 +OP4 E018FF 0 +OP4 E01900 0 +OP4 E01901 0 +OP4 E01902 0 +OP4 E01903 0 +OP4 E01904 0 +OP4 E01905 0 +OP4 E01906 0 +OP4 E01907 0 +OP4 E01908 0 +OP4 E01909 0 +OP4 E0190A 0 +OP4 E0190B 0 +OP4 E0190C 0 +OP4 E0190D 0 +OP4 E0190E 0 +OP4 E0190F 0 +OP4 E01910 0 +OP4 E01911 0 +OP4 E01912 0 +OP4 E01913 0 +OP4 E01914 0 +OP4 E01915 0 +OP4 E01916 0 +OP4 E01917 0 +OP4 E01918 0 +OP4 E01919 0 +OP4 E0191A 0 +OP4 E0191B 0 +OP4 E0191C 0 +OP4 E0191D 0 +OP4 E0191E 0 +OP4 E0191F 0 +OP4 E01920 0 +OP4 E01921 0 +OP4 E01922 0 +OP4 E01923 0 +OP4 E01924 0 +OP4 E01925 0 +OP4 E01926 0 +OP4 E01927 0 +OP4 E01928 0 +OP4 E01929 0 +OP4 E0192A 0 +OP4 E0192B 0 +OP4 E0192C 0 +OP4 E0192D 0 +OP4 E0192E 0 +OP4 E0192F 0 +OP4 E01930 0 +OP4 E01931 0 +OP4 E01932 0 +OP4 E01933 0 +OP4 E01934 0 +OP4 E01935 0 +OP4 E01936 0 +OP4 E01937 0 +OP4 E01938 0 +OP4 E01939 0 +OP4 E0193A 0 +OP4 E0193B 0 +OP4 E0193C 0 +OP4 E0193D 0 +OP4 E0193E 0 +OP4 E0193F 0 +OP4 E01940 0 +OP4 E01941 0 +OP4 E01942 0 +OP4 E01943 0 +OP4 E01944 0 +OP4 E01945 0 +OP4 E01946 0 +OP4 E01947 0 +OP4 E01948 0 +OP4 E01949 0 +OP4 E0194A 0 +OP4 E0194B 0 +OP4 E0194C 0 +OP4 E0194D 0 +OP4 E0194E 0 +OP4 E0194F 0 +OP4 E01950 0 +OP4 E01951 0 +OP4 E01952 0 +OP4 E01953 0 +OP4 E01954 0 +OP4 E01955 0 +OP4 E01956 0 +OP4 E01957 0 +OP4 E01958 0 +OP4 E01959 0 +OP4 E0195A 0 +OP4 E0195B 0 +OP4 E0195C 0 +OP4 E0195D 0 +OP4 E0195E 0 +OP4 E0195F 0 +OP4 E01960 0 +OP4 E01961 0 +OP4 E01962 0 +OP4 E01963 0 +OP4 E01964 0 +OP4 E01965 0 +OP4 E01966 0 +OP4 E01967 0 +OP4 E01968 0 +OP4 E01969 0 +OP4 E0196A 0 +OP4 E0196B 0 +OP4 E0196C 0 +OP4 E0196D 0 +OP4 E0196E 0 +OP4 E0196F 0 +OP4 E01970 0 +OP4 E01971 0 +OP4 E01972 0 +OP4 E01973 0 +OP4 E01974 0 +OP4 E01975 0 +OP4 E01976 0 +OP4 E01977 0 +OP4 E01978 0 +OP4 E01979 0 +OP4 E0197A 0 +OP4 E0197B 0 +OP4 E0197C 0 +OP4 E0197D 0 +OP4 E0197E 0 +OP4 E0197F 0 +OP4 E01980 0 +OP4 E01981 0 +OP4 E01982 0 +OP4 E01983 0 +OP4 E01984 0 +OP4 E01985 0 +OP4 E01986 0 +OP4 E01987 0 +OP4 E01988 0 +OP4 E01989 0 +OP4 E0198A 0 +OP4 E0198B 0 +OP4 E0198C 0 +OP4 E0198D 0 +OP4 E0198E 0 +OP4 E0198F 0 +OP4 E01990 0 +OP4 E01991 0 +OP4 E01992 0 +OP4 E01993 0 +OP4 E01994 0 +OP4 E01995 0 +OP4 E01996 0 +OP4 E01997 0 +OP4 E01998 0 +OP4 E01999 0 +OP4 E0199A 0 +OP4 E0199B 0 +OP4 E0199C 0 +OP4 E0199D 0 +OP4 E0199E 0 +OP4 E0199F 0 +OP4 E019A0 0 +OP4 E019A1 0 +OP4 E019A2 0 +OP4 E019A3 0 +OP4 E019A4 0 +OP4 E019A5 0 +OP4 E019A6 0 +OP4 E019A7 0 +OP4 E019A8 0 +OP4 E019A9 0 +OP4 E019AA 0 +OP4 E019AB 0 +OP4 E019AC 0 +OP4 E019AD 0 +OP4 E019AE 0 +OP4 E019AF 0 +OP4 E019B0 0 +OP4 E019B1 0 +OP4 E019B2 0 +OP4 E019B3 0 +OP4 E019B4 0 +OP4 E019B5 0 +OP4 E019B6 0 +OP4 E019B7 0 +OP4 E019B8 0 +OP4 E019B9 0 +OP4 E019BA 0 +OP4 E019BB 0 +OP4 E019BC 0 +OP4 E019BD 0 +OP4 E019BE 0 +OP4 E019BF 0 +OP4 E019C0 0 +OP4 E019C1 0 +OP4 E019C2 0 +OP4 E019C3 0 +OP4 E019C4 0 +OP4 E019C5 0 +OP4 E019C6 0 +OP4 E019C7 0 +OP4 E019C8 0 +OP4 E019C9 0 +OP4 E019CA 0 +OP4 E019CB 0 +OP4 E019CC 0 +OP4 E019CD 0 +OP4 E019CE 0 +OP4 E019CF 0 +OP4 E019D0 0 +OP4 E019D1 0 +OP4 E019D2 0 +OP4 E019D3 0 +OP4 E019D4 0 +OP4 E019D5 0 +OP4 E019D6 0 +OP4 E019D7 0 +OP4 E019D8 0 +OP4 E019D9 0 +OP4 E019DA 0 +OP4 E019DB 0 +OP4 E019DC 0 +OP4 E019DD 0 +OP4 E019DE 0 +OP4 E019DF 0 +OP4 E019E0 0 +OP4 E019E1 0 +OP4 E019E2 0 +OP4 E019E3 0 +OP4 E019E4 0 +OP4 E019E5 0 +OP4 E019E6 0 +OP4 E019E7 0 +OP4 E019E8 0 +OP4 E019E9 0 +OP4 E019EA 0 +OP4 E019EB 0 +OP4 E019EC 0 +OP4 E019ED 0 +OP4 E019EE 0 +OP4 E019EF 0 +OP4 E019F0 0 +OP4 E019F1 0 +OP4 E019F2 0 +OP4 E019F3 0 +OP4 E019F4 0 +OP4 E019F5 0 +OP4 E019F6 0 +OP4 E019F7 0 +OP4 E019F8 0 +OP4 E019F9 0 +OP4 E019FA 0 +OP4 E019FB 0 +OP4 E019FC 0 +OP4 E019FD 0 +OP4 E019FE 0 +OP4 E019FF 0 +OP4 E01A00 0 +OP4 E01A01 0 +OP4 E01A02 0 +OP4 E01A03 0 +OP4 E01A04 0 +OP4 E01A05 0 +OP4 E01A06 0 +OP4 E01A07 0 +OP4 E01A08 0 +OP4 E01A09 0 +OP4 E01A0A 0 +OP4 E01A0B 0 +OP4 E01A0C 0 +OP4 E01A0D 0 +OP4 E01A0E 0 +OP4 E01A0F 0 +OP4 E01A10 0 +OP4 E01A11 0 +OP4 E01A12 0 +OP4 E01A13 0 +OP4 E01A14 0 +OP4 E01A15 0 +OP4 E01A16 0 +OP4 E01A17 0 +OP4 E01A18 0 +OP4 E01A19 0 +OP4 E01A1A 0 +OP4 E01A1B 0 +OP4 E01A1C 0 +OP4 E01A1D 0 +OP4 E01A1E 0 +OP4 E01A1F 0 +OP4 E01A20 0 +OP4 E01A21 0 +OP4 E01A22 0 +OP4 E01A23 0 +OP4 E01A24 0 +OP4 E01A25 0 +OP4 E01A26 0 +OP4 E01A27 0 +OP4 E01A28 0 +OP4 E01A29 0 +OP4 E01A2A 0 +OP4 E01A2B 0 +OP4 E01A2C 0 +OP4 E01A2D 0 +OP4 E01A2E 0 +OP4 E01A2F 0 +OP4 E01A30 0 +OP4 E01A31 0 +OP4 E01A32 0 +OP4 E01A33 0 +OP4 E01A34 0 +OP4 E01A35 0 +OP4 E01A36 0 +OP4 E01A37 0 +OP4 E01A38 0 +OP4 E01A39 0 +OP4 E01A3A 0 +OP4 E01A3B 0 +OP4 E01A3C 0 +OP4 E01A3D 0 +OP4 E01A3E 0 +OP4 E01A3F 0 +OP4 E01A40 0 +OP4 E01A41 0 +OP4 E01A42 0 +OP4 E01A43 0 +OP4 E01A44 0 +OP4 E01A45 0 +OP4 E01A46 0 +OP4 E01A47 0 +OP4 E01A48 0 +OP4 E01A49 0 +OP4 E01A4A 0 +OP4 E01A4B 0 +OP4 E01A4C 0 +OP4 E01A4D 0 +OP4 E01A4E 0 +OP4 E01A4F 0 +OP4 E01A50 0 +OP4 E01A51 0 +OP4 E01A52 0 +OP4 E01A53 0 +OP4 E01A54 0 +OP4 E01A55 0 +OP4 E01A56 0 +OP4 E01A57 0 +OP4 E01A58 0 +OP4 E01A59 0 +OP4 E01A5A 0 +OP4 E01A5B 0 +OP4 E01A5C 0 +OP4 E01A5D 0 +OP4 E01A5E 0 +OP4 E01A5F 0 +OP4 E01A60 0 +OP4 E01A61 0 +OP4 E01A62 0 +OP4 E01A63 0 +OP4 E01A64 0 +OP4 E01A65 0 +OP4 E01A66 0 +OP4 E01A67 0 +OP4 E01A68 0 +OP4 E01A69 0 +OP4 E01A6A 0 +OP4 E01A6B 0 +OP4 E01A6C 0 +OP4 E01A6D 0 +OP4 E01A6E 0 +OP4 E01A6F 0 +OP4 E01A70 0 +OP4 E01A71 0 +OP4 E01A72 0 +OP4 E01A73 0 +OP4 E01A74 0 +OP4 E01A75 0 +OP4 E01A76 0 +OP4 E01A77 0 +OP4 E01A78 0 +OP4 E01A79 0 +OP4 E01A7A 0 +OP4 E01A7B 0 +OP4 E01A7C 0 +OP4 E01A7D 0 +OP4 E01A7E 0 +OP4 E01A7F 0 +OP4 E01A80 0 +OP4 E01A81 0 +OP4 E01A82 0 +OP4 E01A83 0 +OP4 E01A84 0 +OP4 E01A85 0 +OP4 E01A86 0 +OP4 E01A87 0 +OP4 E01A88 0 +OP4 E01A89 0 +OP4 E01A8A 0 +OP4 E01A8B 0 +OP4 E01A8C 0 +OP4 E01A8D 0 +OP4 E01A8E 0 +OP4 E01A8F 0 +OP4 E01A90 0 +OP4 E01A91 0 +OP4 E01A92 0 +OP4 E01A93 0 +OP4 E01A94 0 +OP4 E01A95 0 +OP4 E01A96 0 +OP4 E01A97 0 +OP4 E01A98 0 +OP4 E01A99 0 +OP4 E01A9A 0 +OP4 E01A9B 0 +OP4 E01A9C 0 +OP4 E01A9D 0 +OP4 E01A9E 0 +OP4 E01A9F 0 +OP4 E01AA0 0 +OP4 E01AA1 0 +OP4 E01AA2 0 +OP4 E01AA3 0 +OP4 E01AA4 0 +OP4 E01AA5 0 +OP4 E01AA6 0 +OP4 E01AA7 0 +OP4 E01AA8 0 +OP4 E01AA9 0 +OP4 E01AAA 0 +OP4 E01AAB 0 +OP4 E01AAC 0 +OP4 E01AAD 0 +OP4 E01AAE 0 +OP4 E01AAF 0 +OP4 E01AB0 0 +OP4 E01AB1 0 +OP4 E01AB2 0 +OP4 E01AB3 0 +OP4 E01AB4 0 +OP4 E01AB5 0 +OP4 E01AB6 0 +OP4 E01AB7 0 +OP4 E01AB8 0 +OP4 E01AB9 0 +OP4 E01ABA 0 +OP4 E01ABB 0 +OP4 E01ABC 0 +OP4 E01ABD 0 +OP4 E01ABE 0 +OP4 E01ABF 0 +OP4 E01AC0 0 +OP4 E01AC1 0 +OP4 E01AC2 0 +OP4 E01AC3 0 +OP4 E01AC4 0 +OP4 E01AC5 0 +OP4 E01AC6 0 +OP4 E01AC7 0 +OP4 E01AC8 0 +OP4 E01AC9 0 +OP4 E01ACA 0 +OP4 E01ACB 0 +OP4 E01ACC 0 +OP4 E01ACD 0 +OP4 E01ACE 0 +OP4 E01ACF 0 +OP4 E01AD0 0 +OP4 E01AD1 0 +OP4 E01AD2 0 +OP4 E01AD3 0 +OP4 E01AD4 0 +OP4 E01AD5 0 +OP4 E01AD6 0 +OP4 E01AD7 0 +OP4 E01AD8 0 +OP4 E01AD9 0 +OP4 E01ADA 0 +OP4 E01ADB 0 +OP4 E01ADC 0 +OP4 E01ADD 0 +OP4 E01ADE 0 +OP4 E01ADF 0 +OP4 E01AE0 0 +OP4 E01AE1 0 +OP4 E01AE2 0 +OP4 E01AE3 0 +OP4 E01AE4 0 +OP4 E01AE5 0 +OP4 E01AE6 0 +OP4 E01AE7 0 +OP4 E01AE8 0 +OP4 E01AE9 0 +OP4 E01AEA 0 +OP4 E01AEB 0 +OP4 E01AEC 0 +OP4 E01AED 0 +OP4 E01AEE 0 +OP4 E01AEF 0 +OP4 E01AF0 0 +OP4 E01AF1 0 +OP4 E01AF2 0 +OP4 E01AF3 0 +OP4 E01AF4 0 +OP4 E01AF5 0 +OP4 E01AF6 0 +OP4 E01AF7 0 +OP4 E01AF8 0 +OP4 E01AF9 0 +OP4 E01AFA 0 +OP4 E01AFB 0 +OP4 E01AFC 0 +OP4 E01AFD 0 +OP4 E01AFE 0 +OP4 E01AFF 0 +OP4 E01B00 0 +OP4 E01B01 0 +OP4 E01B02 0 +OP4 E01B03 0 +OP4 E01B04 0 +OP4 E01B05 0 +OP4 E01B06 0 +OP4 E01B07 0 +OP4 E01B08 0 +OP4 E01B09 0 +OP4 E01B0A 0 +OP4 E01B0B 0 +OP4 E01B0C 0 +OP4 E01B0D 0 +OP4 E01B0E 0 +OP4 E01B0F 0 +OP4 E01B10 0 +OP4 E01B11 0 +OP4 E01B12 0 +OP4 E01B13 0 +OP4 E01B14 0 +OP4 E01B15 0 +OP4 E01B16 0 +OP4 E01B17 0 +OP4 E01B18 0 +OP4 E01B19 0 +OP4 E01B1A 0 +OP4 E01B1B 0 +OP4 E01B1C 0 +OP4 E01B1D 0 +OP4 E01B1E 0 +OP4 E01B1F 0 +OP4 E01B20 0 +OP4 E01B21 0 +OP4 E01B22 0 +OP4 E01B23 0 +OP4 E01B24 0 +OP4 E01B25 0 +OP4 E01B26 0 +OP4 E01B27 0 +OP4 E01B28 0 +OP4 E01B29 0 +OP4 E01B2A 0 +OP4 E01B2B 0 +OP4 E01B2C 0 +OP4 E01B2D 0 +OP4 E01B2E 0 +OP4 E01B2F 0 +OP4 E01B30 0 +OP4 E01B31 0 +OP4 E01B32 0 +OP4 E01B33 0 +OP4 E01B34 0 +OP4 E01B35 0 +OP4 E01B36 0 +OP4 E01B37 0 +OP4 E01B38 0 +OP4 E01B39 0 +OP4 E01B3A 0 +OP4 E01B3B 0 +OP4 E01B3C 0 +OP4 E01B3D 0 +OP4 E01B3E 0 +OP4 E01B3F 0 +OP4 E01B40 0 +OP4 E01B41 0 +OP4 E01B42 0 +OP4 E01B43 0 +OP4 E01B44 0 +OP4 E01B45 0 +OP4 E01B46 0 +OP4 E01B47 0 +OP4 E01B48 0 +OP4 E01B49 0 +OP4 E01B4A 0 +OP4 E01B4B 0 +OP4 E01B4C 0 +OP4 E01B4D 0 +OP4 E01B4E 0 +OP4 E01B4F 0 +OP4 E01B50 0 +OP4 E01B51 0 +OP4 E01B52 0 +OP4 E01B53 0 +OP4 E01B54 0 +OP4 E01B55 0 +OP4 E01B56 0 +OP4 E01B57 0 +OP4 E01B58 0 +OP4 E01B59 0 +OP4 E01B5A 0 +OP4 E01B5B 0 +OP4 E01B5C 0 +OP4 E01B5D 0 +OP4 E01B5E 0 +OP4 E01B5F 0 +OP4 E01B60 0 +OP4 E01B61 0 +OP4 E01B62 0 +OP4 E01B63 0 +OP4 E01B64 0 +OP4 E01B65 0 +OP4 E01B66 0 +OP4 E01B67 0 +OP4 E01B68 0 +OP4 E01B69 0 +OP4 E01B6A 0 +OP4 E01B6B 0 +OP4 E01B6C 0 +OP4 E01B6D 0 +OP4 E01B6E 0 +OP4 E01B6F 0 +OP4 E01B70 0 +OP4 E01B71 0 +OP4 E01B72 0 +OP4 E01B73 0 +OP4 E01B74 0 +OP4 E01B75 0 +OP4 E01B76 0 +OP4 E01B77 0 +OP4 E01B78 0 +OP4 E01B79 0 +OP4 E01B7A 0 +OP4 E01B7B 0 +OP4 E01B7C 0 +OP4 E01B7D 0 +OP4 E01B7E 0 +OP4 E01B7F 0 +OP4 E01B80 0 +OP4 E01B81 0 +OP4 E01B82 0 +OP4 E01B83 0 +OP4 E01B84 0 +OP4 E01B85 0 +OP4 E01B86 0 +OP4 E01B87 0 +OP4 E01B88 0 +OP4 E01B89 0 +OP4 E01B8A 0 +OP4 E01B8B 0 +OP4 E01B8C 0 +OP4 E01B8D 0 +OP4 E01B8E 0 +OP4 E01B8F 0 +OP4 E01B90 0 +OP4 E01B91 0 +OP4 E01B92 0 +OP4 E01B93 0 +OP4 E01B94 0 +OP4 E01B95 0 +OP4 E01B96 0 +OP4 E01B97 0 +OP4 E01B98 0 +OP4 E01B99 0 +OP4 E01B9A 0 +OP4 E01B9B 0 +OP4 E01B9C 0 +OP4 E01B9D 0 +OP4 E01B9E 0 +OP4 E01B9F 0 +OP4 E01BA0 0 +OP4 E01BA1 0 +OP4 E01BA2 0 +OP4 E01BA3 0 +OP4 E01BA4 0 +OP4 E01BA5 0 +OP4 E01BA6 0 +OP4 E01BA7 0 +OP4 E01BA8 0 +OP4 E01BA9 0 +OP4 E01BAA 0 +OP4 E01BAB 0 +OP4 E01BAC 0 +OP4 E01BAD 0 +OP4 E01BAE 0 +OP4 E01BAF 0 +OP4 E01BB0 0 +OP4 E01BB1 0 +OP4 E01BB2 0 +OP4 E01BB3 0 +OP4 E01BB4 0 +OP4 E01BB5 0 +OP4 E01BB6 0 +OP4 E01BB7 0 +OP4 E01BB8 0 +OP4 E01BB9 0 +OP4 E01BBA 0 +OP4 E01BBB 0 +OP4 E01BBC 0 +OP4 E01BBD 0 +OP4 E01BBE 0 +OP4 E01BBF 0 +OP4 E01BC0 0 +OP4 E01BC1 0 +OP4 E01BC2 0 +OP4 E01BC3 0 +OP4 E01BC4 0 +OP4 E01BC5 0 +OP4 E01BC6 0 +OP4 E01BC7 0 +OP4 E01BC8 0 +OP4 E01BC9 0 +OP4 E01BCA 0 +OP4 E01BCB 0 +OP4 E01BCC 0 +OP4 E01BCD 0 +OP4 E01BCE 0 +OP4 E01BCF 0 +OP4 E01BD0 0 +OP4 E01BD1 0 +OP4 E01BD2 0 +OP4 E01BD3 0 +OP4 E01BD4 0 +OP4 E01BD5 0 +OP4 E01BD6 0 +OP4 E01BD7 0 +OP4 E01BD8 0 +OP4 E01BD9 0 +OP4 E01BDA 0 +OP4 E01BDB 0 +OP4 E01BDC 0 +OP4 E01BDD 0 +OP4 E01BDE 0 +OP4 E01BDF 0 +OP4 E01BE0 0 +OP4 E01BE1 0 +OP4 E01BE2 0 +OP4 E01BE3 0 +OP4 E01BE4 0 +OP4 E01BE5 0 +OP4 E01BE6 0 +OP4 E01BE7 0 +OP4 E01BE8 0 +OP4 E01BE9 0 +OP4 E01BEA 0 +OP4 E01BEB 0 +OP4 E01BEC 0 +OP4 E01BED 0 +OP4 E01BEE 0 +OP4 E01BEF 0 +OP4 E01BF0 0 +OP4 E01BF1 0 +OP4 E01BF2 0 +OP4 E01BF3 0 +OP4 E01BF4 0 +OP4 E01BF5 0 +OP4 E01BF6 0 +OP4 E01BF7 0 +OP4 E01BF8 0 +OP4 E01BF9 0 +OP4 E01BFA 0 +OP4 E01BFB 0 +OP4 E01BFC 0 +OP4 E01BFD 0 +OP4 E01BFE 0 +OP4 E01BFF 0 +OP4 E01C00 0 +OP4 E01C01 0 +OP4 E01C02 0 +OP4 E01C03 0 +OP4 E01C04 0 +OP4 E01C05 0 +OP4 E01C06 0 +OP4 E01C07 0 +OP4 E01C08 0 +OP4 E01C09 0 +OP4 E01C0A 0 +OP4 E01C0B 0 +OP4 E01C0C 0 +OP4 E01C0D 0 +OP4 E01C0E 0 +OP4 E01C0F 0 +OP4 E01C10 0 +OP4 E01C11 0 +OP4 E01C12 0 +OP4 E01C13 0 +OP4 E01C14 0 +OP4 E01C15 0 +OP4 E01C16 0 +OP4 E01C17 0 +OP4 E01C18 0 +OP4 E01C19 0 +OP4 E01C1A 0 +OP4 E01C1B 0 +OP4 E01C1C 0 +OP4 E01C1D 0 +OP4 E01C1E 0 +OP4 E01C1F 0 +OP4 E01C20 0 +OP4 E01C21 0 +OP4 E01C22 0 +OP4 E01C23 0 +OP4 E01C24 0 +OP4 E01C25 0 +OP4 E01C26 0 +OP4 E01C27 0 +OP4 E01C28 0 +OP4 E01C29 0 +OP4 E01C2A 0 +OP4 E01C2B 0 +OP4 E01C2C 0 +OP4 E01C2D 0 +OP4 E01C2E 0 +OP4 E01C2F 0 +OP4 E01C30 0 +OP4 E01C31 0 +OP4 E01C32 0 +OP4 E01C33 0 +OP4 E01C34 0 +OP4 E01C35 0 +OP4 E01C36 0 +OP4 E01C37 0 +OP4 E01C38 0 +OP4 E01C39 0 +OP4 E01C3A 0 +OP4 E01C3B 0 +OP4 E01C3C 0 +OP4 E01C3D 0 +OP4 E01C3E 0 +OP4 E01C3F 0 +OP4 E01C40 0 +OP4 E01C41 0 +OP4 E01C42 0 +OP4 E01C43 0 +OP4 E01C44 0 +OP4 E01C45 0 +OP4 E01C46 0 +OP4 E01C47 0 +OP4 E01C48 0 +OP4 E01C49 0 +OP4 E01C4A 0 +OP4 E01C4B 0 +OP4 E01C4C 0 +OP4 E01C4D 0 +OP4 E01C4E 0 +OP4 E01C4F 0 +OP4 E01C50 0 +OP4 E01C51 0 +OP4 E01C52 0 +OP4 E01C53 0 +OP4 E01C54 0 +OP4 E01C55 0 +OP4 E01C56 0 +OP4 E01C57 0 +OP4 E01C58 0 +OP4 E01C59 0 +OP4 E01C5A 0 +OP4 E01C5B 0 +OP4 E01C5C 0 +OP4 E01C5D 0 +OP4 E01C5E 0 +OP4 E01C5F 0 +OP4 E01C60 0 +OP4 E01C61 0 +OP4 E01C62 0 +OP4 E01C63 0 +OP4 E01C64 0 +OP4 E01C65 0 +OP4 E01C66 0 +OP4 E01C67 0 +OP4 E01C68 0 +OP4 E01C69 0 +OP4 E01C6A 0 +OP4 E01C6B 0 +OP4 E01C6C 0 +OP4 E01C6D 0 +OP4 E01C6E 0 +OP4 E01C6F 0 +OP4 E01C70 0 +OP4 E01C71 0 +OP4 E01C72 0 +OP4 E01C73 0 +OP4 E01C74 0 +OP4 E01C75 0 +OP4 E01C76 0 +OP4 E01C77 0 +OP4 E01C78 0 +OP4 E01C79 0 +OP4 E01C7A 0 +OP4 E01C7B 0 +OP4 E01C7C 0 +OP4 E01C7D 0 +OP4 E01C7E 0 +OP4 E01C7F 0 +OP4 E01C80 0 +OP4 E01C81 0 +OP4 E01C82 0 +OP4 E01C83 0 +OP4 E01C84 0 +OP4 E01C85 0 +OP4 E01C86 0 +OP4 E01C87 0 +OP4 E01C88 0 +OP4 E01C89 0 +OP4 E01C8A 0 +OP4 E01C8B 0 +OP4 E01C8C 0 +OP4 E01C8D 0 +OP4 E01C8E 0 +OP4 E01C8F 0 +OP4 E01C90 0 +OP4 E01C91 0 +OP4 E01C92 0 +OP4 E01C93 0 +OP4 E01C94 0 +OP4 E01C95 0 +OP4 E01C96 0 +OP4 E01C97 0 +OP4 E01C98 0 +OP4 E01C99 0 +OP4 E01C9A 0 +OP4 E01C9B 0 +OP4 E01C9C 0 +OP4 E01C9D 0 +OP4 E01C9E 0 +OP4 E01C9F 0 +OP4 E01CA0 0 +OP4 E01CA1 0 +OP4 E01CA2 0 +OP4 E01CA3 0 +OP4 E01CA4 0 +OP4 E01CA5 0 +OP4 E01CA6 0 +OP4 E01CA7 0 +OP4 E01CA8 0 +OP4 E01CA9 0 +OP4 E01CAA 0 +OP4 E01CAB 0 +OP4 E01CAC 0 +OP4 E01CAD 0 +OP4 E01CAE 0 +OP4 E01CAF 0 +OP4 E01CB0 0 +OP4 E01CB1 0 +OP4 E01CB2 0 +OP4 E01CB3 0 +OP4 E01CB4 0 +OP4 E01CB5 0 +OP4 E01CB6 0 +OP4 E01CB7 0 +OP4 E01CB8 0 +OP4 E01CB9 0 +OP4 E01CBA 0 +OP4 E01CBB 0 +OP4 E01CBC 0 +OP4 E01CBD 0 +OP4 E01CBE 0 +OP4 E01CBF 0 +OP4 E01CC0 0 +OP4 E01CC1 0 +OP4 E01CC2 0 +OP4 E01CC3 0 +OP4 E01CC4 0 +OP4 E01CC5 0 +OP4 E01CC6 0 +OP4 E01CC7 0 +OP4 E01CC8 0 +OP4 E01CC9 0 +OP4 E01CCA 0 +OP4 E01CCB 0 +OP4 E01CCC 0 +OP4 E01CCD 0 +OP4 E01CCE 0 +OP4 E01CCF 0 +OP4 E01CD0 0 +OP4 E01CD1 0 +OP4 E01CD2 0 +OP4 E01CD3 0 +OP4 E01CD4 0 +OP4 E01CD5 0 +OP4 E01CD6 0 +OP4 E01CD7 0 +OP4 E01CD8 0 +OP4 E01CD9 0 +OP4 E01CDA 0 +OP4 E01CDB 0 +OP4 E01CDC 0 +OP4 E01CDD 0 +OP4 E01CDE 0 +OP4 E01CDF 0 +OP4 E01CE0 0 +OP4 E01CE1 0 +OP4 E01CE2 0 +OP4 E01CE3 0 +OP4 E01CE4 0 +OP4 E01CE5 0 +OP4 E01CE6 0 +OP4 E01CE7 0 +OP4 E01CE8 0 +OP4 E01CE9 0 +OP4 E01CEA 0 +OP4 E01CEB 0 +OP4 E01CEC 0 +OP4 E01CED 0 +OP4 E01CEE 0 +OP4 E01CEF 0 +OP4 E01CF0 0 +OP4 E01CF1 0 +OP4 E01CF2 0 +OP4 E01CF3 0 +OP4 E01CF4 0 +OP4 E01CF5 0 +OP4 E01CF6 0 +OP4 E01CF7 0 +OP4 E01CF8 0 +OP4 E01CF9 0 +OP4 E01CFA 0 +OP4 E01CFB 0 +OP4 E01CFC 0 +OP4 E01CFD 0 +OP4 E01CFE 0 +OP4 E01CFF 0 +OP4 E01D00 0 +OP4 E01D01 0 +OP4 E01D02 0 +OP4 E01D03 0 +OP4 E01D04 0 +OP4 E01D05 0 +OP4 E01D06 0 +OP4 E01D07 0 +OP4 E01D08 0 +OP4 E01D09 0 +OP4 E01D0A 0 +OP4 E01D0B 0 +OP4 E01D0C 0 +OP4 E01D0D 0 +OP4 E01D0E 0 +OP4 E01D0F 0 +OP4 E01D10 0 +OP4 E01D11 0 +OP4 E01D12 0 +OP4 E01D13 0 +OP4 E01D14 0 +OP4 E01D15 0 +OP4 E01D16 0 +OP4 E01D17 0 +OP4 E01D18 0 +OP4 E01D19 0 +OP4 E01D1A 0 +OP4 E01D1B 0 +OP4 E01D1C 0 +OP4 E01D1D 0 +OP4 E01D1E 0 +OP4 E01D1F 0 +OP4 E01D20 0 +OP4 E01D21 0 +OP4 E01D22 0 +OP4 E01D23 0 +OP4 E01D24 0 +OP4 E01D25 0 +OP4 E01D26 0 +OP4 E01D27 0 +OP4 E01D28 0 +OP4 E01D29 0 +OP4 E01D2A 0 +OP4 E01D2B 0 +OP4 E01D2C 0 +OP4 E01D2D 0 +OP4 E01D2E 0 +OP4 E01D2F 0 +OP4 E01D30 0 +OP4 E01D31 0 +OP4 E01D32 0 +OP4 E01D33 0 +OP4 E01D34 0 +OP4 E01D35 0 +OP4 E01D36 0 +OP4 E01D37 0 +OP4 E01D38 0 +OP4 E01D39 0 +OP4 E01D3A 0 +OP4 E01D3B 0 +OP4 E01D3C 0 +OP4 E01D3D 0 +OP4 E01D3E 0 +OP4 E01D3F 0 +OP4 E01D40 0 +OP4 E01D41 0 +OP4 E01D42 0 +OP4 E01D43 0 +OP4 E01D44 0 +OP4 E01D45 0 +OP4 E01D46 0 +OP4 E01D47 0 +OP4 E01D48 0 +OP4 E01D49 0 +OP4 E01D4A 0 +OP4 E01D4B 0 +OP4 E01D4C 0 +OP4 E01D4D 0 +OP4 E01D4E 0 +OP4 E01D4F 0 +OP4 E01D50 0 +OP4 E01D51 0 +OP4 E01D52 0 +OP4 E01D53 0 +OP4 E01D54 0 +OP4 E01D55 0 +OP4 E01D56 0 +OP4 E01D57 0 +OP4 E01D58 0 +OP4 E01D59 0 +OP4 E01D5A 0 +OP4 E01D5B 0 +OP4 E01D5C 0 +OP4 E01D5D 0 +OP4 E01D5E 0 +OP4 E01D5F 0 +OP4 E01D60 0 +OP4 E01D61 0 +OP4 E01D62 0 +OP4 E01D63 0 +OP4 E01D64 0 +OP4 E01D65 0 +OP4 E01D66 0 +OP4 E01D67 0 +OP4 E01D68 0 +OP4 E01D69 0 +OP4 E01D6A 0 +OP4 E01D6B 0 +OP4 E01D6C 0 +OP4 E01D6D 0 +OP4 E01D6E 0 +OP4 E01D6F 0 +OP4 E01D70 0 +OP4 E01D71 0 +OP4 E01D72 0 +OP4 E01D73 0 +OP4 E01D74 0 +OP4 E01D75 0 +OP4 E01D76 0 +OP4 E01D77 0 +OP4 E01D78 0 +OP4 E01D79 0 +OP4 E01D7A 0 +OP4 E01D7B 0 +OP4 E01D7C 0 +OP4 E01D7D 0 +OP4 E01D7E 0 +OP4 E01D7F 0 +OP4 E01D80 0 +OP4 E01D81 0 +OP4 E01D82 0 +OP4 E01D83 0 +OP4 E01D84 0 +OP4 E01D85 0 +OP4 E01D86 0 +OP4 E01D87 0 +OP4 E01D88 0 +OP4 E01D89 0 +OP4 E01D8A 0 +OP4 E01D8B 0 +OP4 E01D8C 0 +OP4 E01D8D 0 +OP4 E01D8E 0 +OP4 E01D8F 0 +OP4 E01D90 0 +OP4 E01D91 0 +OP4 E01D92 0 +OP4 E01D93 0 +OP4 E01D94 0 +OP4 E01D95 0 +OP4 E01D96 0 +OP4 E01D97 0 +OP4 E01D98 0 +OP4 E01D99 0 +OP4 E01D9A 0 +OP4 E01D9B 0 +OP4 E01D9C 0 +OP4 E01D9D 0 +OP4 E01D9E 0 +OP4 E01D9F 0 +OP4 E01DA0 0 +OP4 E01DA1 0 +OP4 E01DA2 0 +OP4 E01DA3 0 +OP4 E01DA4 0 +OP4 E01DA5 0 +OP4 E01DA6 0 +OP4 E01DA7 0 +OP4 E01DA8 0 +OP4 E01DA9 0 +OP4 E01DAA 0 +OP4 E01DAB 0 +OP4 E01DAC 0 +OP4 E01DAD 0 +OP4 E01DAE 0 +OP4 E01DAF 0 +OP4 E01DB0 0 +OP4 E01DB1 0 +OP4 E01DB2 0 +OP4 E01DB3 0 +OP4 E01DB4 0 +OP4 E01DB5 0 +OP4 E01DB6 0 +OP4 E01DB7 0 +OP4 E01DB8 0 +OP4 E01DB9 0 +OP4 E01DBA 0 +OP4 E01DBB 0 +OP4 E01DBC 0 +OP4 E01DBD 0 +OP4 E01DBE 0 +OP4 E01DBF 0 +OP4 E01DC0 0 +OP4 E01DC1 0 +OP4 E01DC2 0 +OP4 E01DC3 0 +OP4 E01DC4 0 +OP4 E01DC5 0 +OP4 E01DC6 0 +OP4 E01DC7 0 +OP4 E01DC8 0 +OP4 E01DC9 0 +OP4 E01DCA 0 +OP4 E01DCB 0 +OP4 E01DCC 0 +OP4 E01DCD 0 +OP4 E01DCE 0 +OP4 E01DCF 0 +OP4 E01DD0 0 +OP4 E01DD1 0 +OP4 E01DD2 0 +OP4 E01DD3 0 +OP4 E01DD4 0 +OP4 E01DD5 0 +OP4 E01DD6 0 +OP4 E01DD7 0 +OP4 E01DD8 0 +OP4 E01DD9 0 +OP4 E01DDA 0 +OP4 E01DDB 0 +OP4 E01DDC 0 +OP4 E01DDD 0 +OP4 E01DDE 0 +OP4 E01DDF 0 +OP4 E01DE0 0 +OP4 E01DE1 0 +OP4 E01DE2 0 +OP4 E01DE3 0 +OP4 E01DE4 0 +OP4 E01DE5 0 +OP4 E01DE6 0 +OP4 E01DE7 0 +OP4 E01DE8 0 +OP4 E01DE9 0 +OP4 E01DEA 0 +OP4 E01DEB 0 +OP4 E01DEC 0 +OP4 E01DED 0 +OP4 E01DEE 0 +OP4 E01DEF 0 +OP4 E01DF0 0 +OP4 E01DF1 0 +OP4 E01DF2 0 +OP4 E01DF3 0 +OP4 E01DF4 0 +OP4 E01DF5 0 +OP4 E01DF6 0 +OP4 E01DF7 0 +OP4 E01DF8 0 +OP4 E01DF9 0 +OP4 E01DFA 0 +OP4 E01DFB 0 +OP4 E01DFC 0 +OP4 E01DFD 0 +OP4 E01DFE 0 +OP4 E01DFF 0 +OP4 E01E00 0 +OP4 E01E01 0 +OP4 E01E02 0 +OP4 E01E03 0 +OP4 E01E04 0 +OP4 E01E05 0 +OP4 E01E06 0 +OP4 E01E07 0 +OP4 E01E08 0 +OP4 E01E09 0 +OP4 E01E0A 0 +OP4 E01E0B 0 +OP4 E01E0C 0 +OP4 E01E0D 0 +OP4 E01E0E 0 +OP4 E01E0F 0 +OP4 E01E10 0 +OP4 E01E11 0 +OP4 E01E12 0 +OP4 E01E13 0 +OP4 E01E14 0 +OP4 E01E15 0 +OP4 E01E16 0 +OP4 E01E17 0 +OP4 E01E18 0 +OP4 E01E19 0 +OP4 E01E1A 0 +OP4 E01E1B 0 +OP4 E01E1C 0 +OP4 E01E1D 0 +OP4 E01E1E 0 +OP4 E01E1F 0 +OP4 E01E20 0 +OP4 E01E21 0 +OP4 E01E22 0 +OP4 E01E23 0 +OP4 E01E24 0 +OP4 E01E25 0 +OP4 E01E26 0 +OP4 E01E27 0 +OP4 E01E28 0 +OP4 E01E29 0 +OP4 E01E2A 0 +OP4 E01E2B 0 +OP4 E01E2C 0 +OP4 E01E2D 0 +OP4 E01E2E 0 +OP4 E01E2F 0 +OP4 E01E30 0 +OP4 E01E31 0 +OP4 E01E32 0 +OP4 E01E33 0 +OP4 E01E34 0 +OP4 E01E35 0 +OP4 E01E36 0 +OP4 E01E37 0 +OP4 E01E38 0 +OP4 E01E39 0 +OP4 E01E3A 0 +OP4 E01E3B 0 +OP4 E01E3C 0 +OP4 E01E3D 0 +OP4 E01E3E 0 +OP4 E01E3F 0 +OP4 E01E40 0 +OP4 E01E41 0 +OP4 E01E42 0 +OP4 E01E43 0 +OP4 E01E44 0 +OP4 E01E45 0 +OP4 E01E46 0 +OP4 E01E47 0 +OP4 E01E48 0 +OP4 E01E49 0 +OP4 E01E4A 0 +OP4 E01E4B 0 +OP4 E01E4C 0 +OP4 E01E4D 0 +OP4 E01E4E 0 +OP4 E01E4F 0 +OP4 E01E50 0 +OP4 E01E51 0 +OP4 E01E52 0 +OP4 E01E53 0 +OP4 E01E54 0 +OP4 E01E55 0 +OP4 E01E56 0 +OP4 E01E57 0 +OP4 E01E58 0 +OP4 E01E59 0 +OP4 E01E5A 0 +OP4 E01E5B 0 +OP4 E01E5C 0 +OP4 E01E5D 0 +OP4 E01E5E 0 +OP4 E01E5F 0 +OP4 E01E60 0 +OP4 E01E61 0 +OP4 E01E62 0 +OP4 E01E63 0 +OP4 E01E64 0 +OP4 E01E65 0 +OP4 E01E66 0 +OP4 E01E67 0 +OP4 E01E68 0 +OP4 E01E69 0 +OP4 E01E6A 0 +OP4 E01E6B 0 +OP4 E01E6C 0 +OP4 E01E6D 0 +OP4 E01E6E 0 +OP4 E01E6F 0 +OP4 E01E70 0 +OP4 E01E71 0 +OP4 E01E72 0 +OP4 E01E73 0 +OP4 E01E74 0 +OP4 E01E75 0 +OP4 E01E76 0 +OP4 E01E77 0 +OP4 E01E78 0 +OP4 E01E79 0 +OP4 E01E7A 0 +OP4 E01E7B 0 +OP4 E01E7C 0 +OP4 E01E7D 0 +OP4 E01E7E 0 +OP4 E01E7F 0 +OP4 E01E80 0 +OP4 E01E81 0 +OP4 E01E82 0 +OP4 E01E83 0 +OP4 E01E84 0 +OP4 E01E85 0 +OP4 E01E86 0 +OP4 E01E87 0 +OP4 E01E88 0 +OP4 E01E89 0 +OP4 E01E8A 0 +OP4 E01E8B 0 +OP4 E01E8C 0 +OP4 E01E8D 0 +OP4 E01E8E 0 +OP4 E01E8F 0 +OP4 E01E90 0 +OP4 E01E91 0 +OP4 E01E92 0 +OP4 E01E93 0 +OP4 E01E94 0 +OP4 E01E95 0 +OP4 E01E96 0 +OP4 E01E97 0 +OP4 E01E98 0 +OP4 E01E99 0 +OP4 E01E9A 0 +OP4 E01E9B 0 +OP4 E01E9C 0 +OP4 E01E9D 0 +OP4 E01E9E 0 +OP4 E01E9F 0 +OP4 E01EA0 0 +OP4 E01EA1 0 +OP4 E01EA2 0 +OP4 E01EA3 0 +OP4 E01EA4 0 +OP4 E01EA5 0 +OP4 E01EA6 0 +OP4 E01EA7 0 +OP4 E01EA8 0 +OP4 E01EA9 0 +OP4 E01EAA 0 +OP4 E01EAB 0 +OP4 E01EAC 0 +OP4 E01EAD 0 +OP4 E01EAE 0 +OP4 E01EAF 0 +OP4 E01EB0 0 +OP4 E01EB1 0 +OP4 E01EB2 0 +OP4 E01EB3 0 +OP4 E01EB4 0 +OP4 E01EB5 0 +OP4 E01EB6 0 +OP4 E01EB7 0 +OP4 E01EB8 0 +OP4 E01EB9 0 +OP4 E01EBA 0 +OP4 E01EBB 0 +OP4 E01EBC 0 +OP4 E01EBD 0 +OP4 E01EBE 0 +OP4 E01EBF 0 +OP4 E01EC0 0 +OP4 E01EC1 0 +OP4 E01EC2 0 +OP4 E01EC3 0 +OP4 E01EC4 0 +OP4 E01EC5 0 +OP4 E01EC6 0 +OP4 E01EC7 0 +OP4 E01EC8 0 +OP4 E01EC9 0 +OP4 E01ECA 0 +OP4 E01ECB 0 +OP4 E01ECC 0 +OP4 E01ECD 0 +OP4 E01ECE 0 +OP4 E01ECF 0 +OP4 E01ED0 0 +OP4 E01ED1 0 +OP4 E01ED2 0 +OP4 E01ED3 0 +OP4 E01ED4 0 +OP4 E01ED5 0 +OP4 E01ED6 0 +OP4 E01ED7 0 +OP4 E01ED8 0 +OP4 E01ED9 0 +OP4 E01EDA 0 +OP4 E01EDB 0 +OP4 E01EDC 0 +OP4 E01EDD 0 +OP4 E01EDE 0 +OP4 E01EDF 0 +OP4 E01EE0 0 +OP4 E01EE1 0 +OP4 E01EE2 0 +OP4 E01EE3 0 +OP4 E01EE4 0 +OP4 E01EE5 0 +OP4 E01EE6 0 +OP4 E01EE7 0 +OP4 E01EE8 0 +OP4 E01EE9 0 +OP4 E01EEA 0 +OP4 E01EEB 0 +OP4 E01EEC 0 +OP4 E01EED 0 +OP4 E01EEE 0 +OP4 E01EEF 0 +OP4 E01EF0 0 +OP4 E01EF1 0 +OP4 E01EF2 0 +OP4 E01EF3 0 +OP4 E01EF4 0 +OP4 E01EF5 0 +OP4 E01EF6 0 +OP4 E01EF7 0 +OP4 E01EF8 0 +OP4 E01EF9 0 +OP4 E01EFA 0 +OP4 E01EFB 0 +OP4 E01EFC 0 +OP4 E01EFD 0 +OP4 E01EFE 0 +OP4 E01EFF 0 +OP4 E01F00 0 +OP4 E01F01 0 +OP4 E01F02 0 +OP4 E01F03 0 +OP4 E01F04 0 +OP4 E01F05 0 +OP4 E01F06 0 +OP4 E01F07 0 +OP4 E01F08 0 +OP4 E01F09 0 +OP4 E01F0A 0 +OP4 E01F0B 0 +OP4 E01F0C 0 +OP4 E01F0D 0 +OP4 E01F0E 0 +OP4 E01F0F 0 +OP4 E01F10 0 +OP4 E01F11 0 +OP4 E01F12 0 +OP4 E01F13 0 +OP4 E01F14 0 +OP4 E01F15 0 +OP4 E01F16 0 +OP4 E01F17 0 +OP4 E01F18 0 +OP4 E01F19 0 +OP4 E01F1A 0 +OP4 E01F1B 0 +OP4 E01F1C 0 +OP4 E01F1D 0 +OP4 E01F1E 0 +OP4 E01F1F 0 +OP4 E01F20 0 +OP4 E01F21 0 +OP4 E01F22 0 +OP4 E01F23 0 +OP4 E01F24 0 +OP4 E01F25 0 +OP4 E01F26 0 +OP4 E01F27 0 +OP4 E01F28 0 +OP4 E01F29 0 +OP4 E01F2A 0 +OP4 E01F2B 0 +OP4 E01F2C 0 +OP4 E01F2D 0 +OP4 E01F2E 0 +OP4 E01F2F 0 +OP4 E01F30 0 +OP4 E01F31 0 +OP4 E01F32 0 +OP4 E01F33 0 +OP4 E01F34 0 +OP4 E01F35 0 +OP4 E01F36 0 +OP4 E01F37 0 +OP4 E01F38 0 +OP4 E01F39 0 +OP4 E01F3A 0 +OP4 E01F3B 0 +OP4 E01F3C 0 +OP4 E01F3D 0 +OP4 E01F3E 0 +OP4 E01F3F 0 +OP4 E01F40 0 +OP4 E01F41 0 +OP4 E01F42 0 +OP4 E01F43 0 +OP4 E01F44 0 +OP4 E01F45 0 +OP4 E01F46 0 +OP4 E01F47 0 +OP4 E01F48 0 +OP4 E01F49 0 +OP4 E01F4A 0 +OP4 E01F4B 0 +OP4 E01F4C 0 +OP4 E01F4D 0 +OP4 E01F4E 0 +OP4 E01F4F 0 +OP4 E01F50 0 +OP4 E01F51 0 +OP4 E01F52 0 +OP4 E01F53 0 +OP4 E01F54 0 +OP4 E01F55 0 +OP4 E01F56 0 +OP4 E01F57 0 +OP4 E01F58 0 +OP4 E01F59 0 +OP4 E01F5A 0 +OP4 E01F5B 0 +OP4 E01F5C 0 +OP4 E01F5D 0 +OP4 E01F5E 0 +OP4 E01F5F 0 +OP4 E01F60 0 +OP4 E01F61 0 +OP4 E01F62 0 +OP4 E01F63 0 +OP4 E01F64 0 +OP4 E01F65 0 +OP4 E01F66 0 +OP4 E01F67 0 +OP4 E01F68 0 +OP4 E01F69 0 +OP4 E01F6A 0 +OP4 E01F6B 0 +OP4 E01F6C 0 +OP4 E01F6D 0 +OP4 E01F6E 0 +OP4 E01F6F 0 +OP4 E01F70 0 +OP4 E01F71 0 +OP4 E01F72 0 +OP4 E01F73 0 +OP4 E01F74 0 +OP4 E01F75 0 +OP4 E01F76 0 +OP4 E01F77 0 +OP4 E01F78 0 +OP4 E01F79 0 +OP4 E01F7A 0 +OP4 E01F7B 0 +OP4 E01F7C 0 +OP4 E01F7D 0 +OP4 E01F7E 0 +OP4 E01F7F 0 +OP4 E01F80 0 +OP4 E01F81 0 +OP4 E01F82 0 +OP4 E01F83 0 +OP4 E01F84 0 +OP4 E01F85 0 +OP4 E01F86 0 +OP4 E01F87 0 +OP4 E01F88 0 +OP4 E01F89 0 +OP4 E01F8A 0 +OP4 E01F8B 0 +OP4 E01F8C 0 +OP4 E01F8D 0 +OP4 E01F8E 0 +OP4 E01F8F 0 +OP4 E01F90 0 +OP4 E01F91 0 +OP4 E01F92 0 +OP4 E01F93 0 +OP4 E01F94 0 +OP4 E01F95 0 +OP4 E01F96 0 +OP4 E01F97 0 +OP4 E01F98 0 +OP4 E01F99 0 +OP4 E01F9A 0 +OP4 E01F9B 0 +OP4 E01F9C 0 +OP4 E01F9D 0 +OP4 E01F9E 0 +OP4 E01F9F 0 +OP4 E01FA0 0 +OP4 E01FA1 0 +OP4 E01FA2 0 +OP4 E01FA3 0 +OP4 E01FA4 0 +OP4 E01FA5 0 +OP4 E01FA6 0 +OP4 E01FA7 0 +OP4 E01FA8 0 +OP4 E01FA9 0 +OP4 E01FAA 0 +OP4 E01FAB 0 +OP4 E01FAC 0 +OP4 E01FAD 0 +OP4 E01FAE 0 +OP4 E01FAF 0 +OP4 E01FB0 0 +OP4 E01FB1 0 +OP4 E01FB2 0 +OP4 E01FB3 0 +OP4 E01FB4 0 +OP4 E01FB5 0 +OP4 E01FB6 0 +OP4 E01FB7 0 +OP4 E01FB8 0 +OP4 E01FB9 0 +OP4 E01FBA 0 +OP4 E01FBB 0 +OP4 E01FBC 0 +OP4 E01FBD 0 +OP4 E01FBE 0 +OP4 E01FBF 0 +OP4 E01FC0 0 +OP4 E01FC1 0 +OP4 E01FC2 0 +OP4 E01FC3 0 +OP4 E01FC4 0 +OP4 E01FC5 0 +OP4 E01FC6 0 +OP4 E01FC7 0 +OP4 E01FC8 0 +OP4 E01FC9 0 +OP4 E01FCA 0 +OP4 E01FCB 0 +OP4 E01FCC 0 +OP4 E01FCD 0 +OP4 E01FCE 0 +OP4 E01FCF 0 +OP4 E01FD0 0 +OP4 E01FD1 0 +OP4 E01FD2 0 +OP4 E01FD3 0 +OP4 E01FD4 0 +OP4 E01FD5 0 +OP4 E01FD6 0 +OP4 E01FD7 0 +OP4 E01FD8 0 +OP4 E01FD9 0 +OP4 E01FDA 0 +OP4 E01FDB 0 +OP4 E01FDC 0 +OP4 E01FDD 0 +OP4 E01FDE 0 +OP4 E01FDF 0 +OP4 E01FE0 0 +OP4 E01FE1 0 +OP4 E01FE2 0 +OP4 E01FE3 0 +OP4 E01FE4 0 +OP4 E01FE5 0 +OP4 E01FE6 0 +OP4 E01FE7 0 +OP4 E01FE8 0 +OP4 E01FE9 0 +OP4 E01FEA 0 +OP4 E01FEB 0 +OP4 E01FEC 0 +OP4 E01FED 0 +OP4 E01FEE 0 +OP4 E01FEF 0 +OP4 E01FF0 0 +OP4 E01FF1 0 +OP4 E01FF2 0 +OP4 E01FF3 0 +OP4 E01FF4 0 +OP4 E01FF5 0 +OP4 E01FF6 0 +OP4 E01FF7 0 +OP4 E01FF8 0 +OP4 E01FF9 0 +OP4 E01FFA 0 +OP4 E01FFB 0 +OP4 E01FFC 0 +OP4 E01FFD 0 +OP4 E01FFE 0 +OP4 E01FFF 0 +OP4 E02000 0 +OP4 E02001 0 +OP4 E02002 0 +OP4 E02003 0 +OP4 E02004 0 +OP4 E02005 0 +OP4 E02006 0 +OP4 E02007 0 +OP4 E02008 0 +OP4 E02009 0 +OP4 E0200A 0 +OP4 E0200B 0 +OP4 E0200C 0 +OP4 E0200D 0 +OP4 E0200E 0 +OP4 E0200F 0 +OP4 E02010 0 +OP4 E02011 0 +OP4 E02012 0 +OP4 E02013 0 +OP4 E02014 0 +OP4 E02015 0 +OP4 E02016 0 +OP4 E02017 0 +OP4 E02018 0 +OP4 E02019 0 +OP4 E0201A 0 +OP4 E0201B 0 +OP4 E0201C 0 +OP4 E0201D 0 +OP4 E0201E 0 +OP4 E0201F 0 +OP4 E02020 0 +OP4 E02021 0 +OP4 E02022 0 +OP4 E02023 0 +OP4 E02024 0 +OP4 E02025 0 +OP4 E02026 0 +OP4 E02027 0 +OP4 E02028 0 +OP4 E02029 0 +OP4 E0202A 0 +OP4 E0202B 0 +OP4 E0202C 0 +OP4 E0202D 0 +OP4 E0202E 0 +OP4 E0202F 0 +OP4 E02030 0 +OP4 E02031 0 +OP4 E02032 0 +OP4 E02033 0 +OP4 E02034 0 +OP4 E02035 0 +OP4 E02036 0 +OP4 E02037 0 +OP4 E02038 0 +OP4 E02039 0 +OP4 E0203A 0 +OP4 E0203B 0 +OP4 E0203C 0 +OP4 E0203D 0 +OP4 E0203E 0 +OP4 E0203F 0 +OP4 E02040 0 +OP4 E02041 0 +OP4 E02042 0 +OP4 E02043 0 +OP4 E02044 0 +OP4 E02045 0 +OP4 E02046 0 +OP4 E02047 0 +OP4 E02048 0 +OP4 E02049 0 +OP4 E0204A 0 +OP4 E0204B 0 +OP4 E0204C 0 +OP4 E0204D 0 +OP4 E0204E 0 +OP4 E0204F 0 +OP4 E02050 0 +OP4 E02051 0 +OP4 E02052 0 +OP4 E02053 0 +OP4 E02054 0 +OP4 E02055 0 +OP4 E02056 0 +OP4 E02057 0 +OP4 E02058 0 +OP4 E02059 0 +OP4 E0205A 0 +OP4 E0205B 0 +OP4 E0205C 0 +OP4 E0205D 0 +OP4 E0205E 0 +OP4 E0205F 0 +OP4 E02060 0 +OP4 E02061 0 +OP4 E02062 0 +OP4 E02063 0 +OP4 E02064 0 +OP4 E02065 0 +OP4 E02066 0 +OP4 E02067 0 +OP4 E02068 0 +OP4 E02069 0 +OP4 E0206A 0 +OP4 E0206B 0 +OP4 E0206C 0 +OP4 E0206D 0 +OP4 E0206E 0 +OP4 E0206F 0 +OP4 E02070 0 +OP4 E02071 0 +OP4 E02072 0 +OP4 E02073 0 +OP4 E02074 0 +OP4 E02075 0 +OP4 E02076 0 +OP4 E02077 0 +OP4 E02078 0 +OP4 E02079 0 +OP4 E0207A 0 +OP4 E0207B 0 +OP4 E0207C 0 +OP4 E0207D 0 +OP4 E0207E 0 +OP4 E0207F 0 +OP4 E02080 0 +OP4 E02081 0 +OP4 E02082 0 +OP4 E02083 0 +OP4 E02084 0 +OP4 E02085 0 +OP4 E02086 0 +OP4 E02087 0 +OP4 E02088 0 +OP4 E02089 0 +OP4 E0208A 0 +OP4 E0208B 0 +OP4 E0208C 0 +OP4 E0208D 0 +OP4 E0208E 0 +OP4 E0208F 0 +OP4 E02090 0 +OP4 E02091 0 +OP4 E02092 0 +OP4 E02093 0 +OP4 E02094 0 +OP4 E02095 0 +OP4 E02096 0 +OP4 E02097 0 +OP4 E02098 0 +OP4 E02099 0 +OP4 E0209A 0 +OP4 E0209B 0 +OP4 E0209C 0 +OP4 E0209D 0 +OP4 E0209E 0 +OP4 E0209F 0 +OP4 E020A0 0 +OP4 E020A1 0 +OP4 E020A2 0 +OP4 E020A3 0 +OP4 E020A4 0 +OP4 E020A5 0 +OP4 E020A6 0 +OP4 E020A7 0 +OP4 E020A8 0 +OP4 E020A9 0 +OP4 E020AA 0 +OP4 E020AB 0 +OP4 E020AC 0 +OP4 E020AD 0 +OP4 E020AE 0 +OP4 E020AF 0 +OP4 E020B0 0 +OP4 E020B1 0 +OP4 E020B2 0 +OP4 E020B3 0 +OP4 E020B4 0 +OP4 E020B5 0 +OP4 E020B6 0 +OP4 E020B7 0 +OP4 E020B8 0 +OP4 E020B9 0 +OP4 E020BA 0 +OP4 E020BB 0 +OP4 E020BC 0 +OP4 E020BD 0 +OP4 E020BE 0 +OP4 E020BF 0 +OP4 E020C0 0 +OP4 E020C1 0 +OP4 E020C2 0 +OP4 E020C3 0 +OP4 E020C4 0 +OP4 E020C5 0 +OP4 E020C6 0 +OP4 E020C7 0 +OP4 E020C8 0 +OP4 E020C9 0 +OP4 E020CA 0 +OP4 E020CB 0 +OP4 E020CC 0 +OP4 E020CD 0 +OP4 E020CE 0 +OP4 E020CF 0 +OP4 E020D0 0 +OP4 E020D1 0 +OP4 E020D2 0 +OP4 E020D3 0 +OP4 E020D4 0 +OP4 E020D5 0 +OP4 E020D6 0 +OP4 E020D7 0 +OP4 E020D8 0 +OP4 E020D9 0 +OP4 E020DA 0 +OP4 E020DB 0 +OP4 E020DC 0 +OP4 E020DD 0 +OP4 E020DE 0 +OP4 E020DF 0 +OP4 E020E0 0 +OP4 E020E1 0 +OP4 E020E2 0 +OP4 E020E3 0 +OP4 E020E4 0 +OP4 E020E5 0 +OP4 E020E6 0 +OP4 E020E7 0 +OP4 E020E8 0 +OP4 E020E9 0 +OP4 E020EA 0 +OP4 E020EB 0 +OP4 E020EC 0 +OP4 E020ED 0 +OP4 E020EE 0 +OP4 E020EF 0 +OP4 E020F0 0 +OP4 E020F1 0 +OP4 E020F2 0 +OP4 E020F3 0 +OP4 E020F4 0 +OP4 E020F5 0 +OP4 E020F6 0 +OP4 E020F7 0 +OP4 E020F8 0 +OP4 E020F9 0 +OP4 E020FA 0 +OP4 E020FB 0 +OP4 E020FC 0 +OP4 E020FD 0 +OP4 E020FE 0 +OP4 E020FF 0 +OP4 E02100 0 +OP4 E02101 0 +OP4 E02102 0 +OP4 E02103 0 +OP4 E02104 0 +OP4 E02105 0 +OP4 E02106 0 +OP4 E02107 0 +OP4 E02108 0 +OP4 E02109 0 +OP4 E0210A 0 +OP4 E0210B 0 +OP4 E0210C 0 +OP4 E0210D 0 +OP4 E0210E 0 +OP4 E0210F 0 +OP4 E02110 0 +OP4 E02111 0 +OP4 E02112 0 +OP4 E02113 0 +OP4 E02114 0 +OP4 E02115 0 +OP4 E02116 0 +OP4 E02117 0 +OP4 E02118 0 +OP4 E02119 0 +OP4 E0211A 0 +OP4 E0211B 0 +OP4 E0211C 0 +OP4 E0211D 0 +OP4 E0211E 0 +OP4 E0211F 0 +OP4 E02120 0 +OP4 E02121 0 +OP4 E02122 0 +OP4 E02123 0 +OP4 E02124 0 +OP4 E02125 0 +OP4 E02126 0 +OP4 E02127 0 +OP4 E02128 0 +OP4 E02129 0 +OP4 E0212A 0 +OP4 E0212B 0 +OP4 E0212C 0 +OP4 E0212D 0 +OP4 E0212E 0 +OP4 E0212F 0 +OP4 E02130 0 +OP4 E02131 0 +OP4 E02132 0 +OP4 E02133 0 +OP4 E02134 0 +OP4 E02135 0 +OP4 E02136 0 +OP4 E02137 0 +OP4 E02138 0 +OP4 E02139 0 +OP4 E0213A 0 +OP4 E0213B 0 +OP4 E0213C 0 +OP4 E0213D 0 +OP4 E0213E 0 +OP4 E0213F 0 +OP4 E02140 0 +OP4 E02141 0 +OP4 E02142 0 +OP4 E02143 0 +OP4 E02144 0 +OP4 E02145 0 +OP4 E02146 0 +OP4 E02147 0 +OP4 E02148 0 +OP4 E02149 0 +OP4 E0214A 0 +OP4 E0214B 0 +OP4 E0214C 0 +OP4 E0214D 0 +OP4 E0214E 0 +OP4 E0214F 0 +OP4 E02150 0 +OP4 E02151 0 +OP4 E02152 0 +OP4 E02153 0 +OP4 E02154 0 +OP4 E02155 0 +OP4 E02156 0 +OP4 E02157 0 +OP4 E02158 0 +OP4 E02159 0 +OP4 E0215A 0 +OP4 E0215B 0 +OP4 E0215C 0 +OP4 E0215D 0 +OP4 E0215E 0 +OP4 E0215F 0 +OP4 E02160 0 +OP4 E02161 0 +OP4 E02162 0 +OP4 E02163 0 +OP4 E02164 0 +OP4 E02165 0 +OP4 E02166 0 +OP4 E02167 0 +OP4 E02168 0 +OP4 E02169 0 +OP4 E0216A 0 +OP4 E0216B 0 +OP4 E0216C 0 +OP4 E0216D 0 +OP4 E0216E 0 +OP4 E0216F 0 +OP4 E02170 0 +OP4 E02171 0 +OP4 E02172 0 +OP4 E02173 0 +OP4 E02174 0 +OP4 E02175 0 +OP4 E02176 0 +OP4 E02177 0 +OP4 E02178 0 +OP4 E02179 0 +OP4 E0217A 0 +OP4 E0217B 0 +OP4 E0217C 0 +OP4 E0217D 0 +OP4 E0217E 0 +OP4 E0217F 0 +OP4 E02180 0 +OP4 E02181 0 +OP4 E02182 0 +OP4 E02183 0 +OP4 E02184 0 +OP4 E02185 0 +OP4 E02186 0 +OP4 E02187 0 +OP4 E02188 0 +OP4 E02189 0 +OP4 E0218A 0 +OP4 E0218B 0 +OP4 E0218C 0 +OP4 E0218D 0 +OP4 E0218E 0 +OP4 E0218F 0 +OP4 E02190 0 +OP4 E02191 0 +OP4 E02192 0 +OP4 E02193 0 +OP4 E02194 0 +OP4 E02195 0 +OP4 E02196 0 +OP4 E02197 0 +OP4 E02198 0 +OP4 E02199 0 +OP4 E0219A 0 +OP4 E0219B 0 +OP4 E0219C 0 +OP4 E0219D 0 +OP4 E0219E 0 +OP4 E0219F 0 +OP4 E021A0 0 +OP4 E021A1 0 +OP4 E021A2 0 +OP4 E021A3 0 +OP4 E021A4 0 +OP4 E021A5 0 +OP4 E021A6 0 +OP4 E021A7 0 +OP4 E021A8 0 +OP4 E021A9 0 +OP4 E021AA 0 +OP4 E021AB 0 +OP4 E021AC 0 +OP4 E021AD 0 +OP4 E021AE 0 +OP4 E021AF 0 +OP4 E021B0 0 +OP4 E021B1 0 +OP4 E021B2 0 +OP4 E021B3 0 +OP4 E021B4 0 +OP4 E021B5 0 +OP4 E021B6 0 +OP4 E021B7 0 +OP4 E021B8 0 +OP4 E021B9 0 +OP4 E021BA 0 +OP4 E021BB 0 +OP4 E021BC 0 +OP4 E021BD 0 +OP4 E021BE 0 +OP4 E021BF 0 +OP4 E021C0 0 +OP4 E021C1 0 +OP4 E021C2 0 +OP4 E021C3 0 +OP4 E021C4 0 +OP4 E021C5 0 +OP4 E021C6 0 +OP4 E021C7 0 +OP4 E021C8 0 +OP4 E021C9 0 +OP4 E021CA 0 +OP4 E021CB 0 +OP4 E021CC 0 +OP4 E021CD 0 +OP4 E021CE 0 +OP4 E021CF 0 +OP4 E021D0 0 +OP4 E021D1 0 +OP4 E021D2 0 +OP4 E021D3 0 +OP4 E021D4 0 +OP4 E021D5 0 +OP4 E021D6 0 +OP4 E021D7 0 +OP4 E021D8 0 +OP4 E021D9 0 +OP4 E021DA 0 +OP4 E021DB 0 +OP4 E021DC 0 +OP4 E021DD 0 +OP4 E021DE 0 +OP4 E021DF 0 +OP4 E021E0 0 +OP4 E021E1 0 +OP4 E021E2 0 +OP4 E021E3 0 +OP4 E021E4 0 +OP4 E021E5 0 +OP4 E021E6 0 +OP4 E021E7 0 +OP4 E021E8 0 +OP4 E021E9 0 +OP4 E021EA 0 +OP4 E021EB 0 +OP4 E021EC 0 +OP4 E021ED 0 +OP4 E021EE 0 +OP4 E021EF 0 +OP4 E021F0 0 +OP4 E021F1 0 +OP4 E021F2 0 +OP4 E021F3 0 +OP4 E021F4 0 +OP4 E021F5 0 +OP4 E021F6 0 +OP4 E021F7 0 +OP4 E021F8 0 +OP4 E021F9 0 +OP4 E021FA 0 +OP4 E021FB 0 +OP4 E021FC 0 +OP4 E021FD 0 +OP4 E021FE 0 +OP4 E021FF 0 +OP4 E02200 0 +OP4 E02201 0 +OP4 E02202 0 +OP4 E02203 0 +OP4 E02204 0 +OP4 E02205 0 +OP4 E02206 0 +OP4 E02207 0 +OP4 E02208 0 +OP4 E02209 0 +OP4 E0220A 0 +OP4 E0220B 0 +OP4 E0220C 0 +OP4 E0220D 0 +OP4 E0220E 0 +OP4 E0220F 0 +OP4 E02210 0 +OP4 E02211 0 +OP4 E02212 0 +OP4 E02213 0 +OP4 E02214 0 +OP4 E02215 0 +OP4 E02216 0 +OP4 E02217 0 +OP4 E02218 0 +OP4 E02219 0 +OP4 E0221A 0 +OP4 E0221B 0 +OP4 E0221C 0 +OP4 E0221D 0 +OP4 E0221E 0 +OP4 E0221F 0 +OP4 E02220 0 +OP4 E02221 0 +OP4 E02222 0 +OP4 E02223 0 +OP4 E02224 0 +OP4 E02225 0 +OP4 E02226 0 +OP4 E02227 0 +OP4 E02228 0 +OP4 E02229 0 +OP4 E0222A 0 +OP4 E0222B 0 +OP4 E0222C 0 +OP4 E0222D 0 +OP4 E0222E 0 +OP4 E0222F 0 +OP4 E02230 0 +OP4 E02231 0 +OP4 E02232 0 +OP4 E02233 0 +OP4 E02234 0 +OP4 E02235 0 +OP4 E02236 0 +OP4 E02237 0 +OP4 E02238 0 +OP4 E02239 0 +OP4 E0223A 0 +OP4 E0223B 0 +OP4 E0223C 0 +OP4 E0223D 0 +OP4 E0223E 0 +OP4 E0223F 0 +OP4 E02240 0 +OP4 E02241 0 +OP4 E02242 0 +OP4 E02243 0 +OP4 E02244 0 +OP4 E02245 0 +OP4 E02246 0 +OP4 E02247 0 +OP4 E02248 0 +OP4 E02249 0 +OP4 E0224A 0 +OP4 E0224B 0 +OP4 E0224C 0 +OP4 E0224D 0 +OP4 E0224E 0 +OP4 E0224F 0 +OP4 E02250 0 +OP4 E02251 0 +OP4 E02252 0 +OP4 E02253 0 +OP4 E02254 0 +OP4 E02255 0 +OP4 E02256 0 +OP4 E02257 0 +OP4 E02258 0 +OP4 E02259 0 +OP4 E0225A 0 +OP4 E0225B 0 +OP4 E0225C 0 +OP4 E0225D 0 +OP4 E0225E 0 +OP4 E0225F 0 +OP4 E02260 0 +OP4 E02261 0 +OP4 E02262 0 +OP4 E02263 0 +OP4 E02264 0 +OP4 E02265 0 +OP4 E02266 0 +OP4 E02267 0 +OP4 E02268 0 +OP4 E02269 0 +OP4 E0226A 0 +OP4 E0226B 0 +OP4 E0226C 0 +OP4 E0226D 0 +OP4 E0226E 0 +OP4 E0226F 0 +OP4 E02270 0 +OP4 E02271 0 +OP4 E02272 0 +OP4 E02273 0 +OP4 E02274 0 +OP4 E02275 0 +OP4 E02276 0 +OP4 E02277 0 +OP4 E02278 0 +OP4 E02279 0 +OP4 E0227A 0 +OP4 E0227B 0 +OP4 E0227C 0 +OP4 E0227D 0 +OP4 E0227E 0 +OP4 E0227F 0 +OP4 E02280 0 +OP4 E02281 0 +OP4 E02282 0 +OP4 E02283 0 +OP4 E02284 0 +OP4 E02285 0 +OP4 E02286 0 +OP4 E02287 0 +OP4 E02288 0 +OP4 E02289 0 +OP4 E0228A 0 +OP4 E0228B 0 +OP4 E0228C 0 +OP4 E0228D 0 +OP4 E0228E 0 +OP4 E0228F 0 +OP4 E02290 0 +OP4 E02291 0 +OP4 E02292 0 +OP4 E02293 0 +OP4 E02294 0 +OP4 E02295 0 +OP4 E02296 0 +OP4 E02297 0 +OP4 E02298 0 +OP4 E02299 0 +OP4 E0229A 0 +OP4 E0229B 0 +OP4 E0229C 0 +OP4 E0229D 0 +OP4 E0229E 0 +OP4 E0229F 0 +OP4 E022A0 0 +OP4 E022A1 0 +OP4 E022A2 0 +OP4 E022A3 0 +OP4 E022A4 0 +OP4 E022A5 0 +OP4 E022A6 0 +OP4 E022A7 0 +OP4 E022A8 0 +OP4 E022A9 0 +OP4 E022AA 0 +OP4 E022AB 0 +OP4 E022AC 0 +OP4 E022AD 0 +OP4 E022AE 0 +OP4 E022AF 0 +OP4 E022B0 0 +OP4 E022B1 0 +OP4 E022B2 0 +OP4 E022B3 0 +OP4 E022B4 0 +OP4 E022B5 0 +OP4 E022B6 0 +OP4 E022B7 0 +OP4 E022B8 0 +OP4 E022B9 0 +OP4 E022BA 0 +OP4 E022BB 0 +OP4 E022BC 0 +OP4 E022BD 0 +OP4 E022BE 0 +OP4 E022BF 0 +OP4 E022C0 0 +OP4 E022C1 0 +OP4 E022C2 0 +OP4 E022C3 0 +OP4 E022C4 0 +OP4 E022C5 0 +OP4 E022C6 0 +OP4 E022C7 0 +OP4 E022C8 0 +OP4 E022C9 0 +OP4 E022CA 0 +OP4 E022CB 0 +OP4 E022CC 0 +OP4 E022CD 0 +OP4 E022CE 0 +OP4 E022CF 0 +OP4 E022D0 0 +OP4 E022D1 0 +OP4 E022D2 0 +OP4 E022D3 0 +OP4 E022D4 0 +OP4 E022D5 0 +OP4 E022D6 0 +OP4 E022D7 0 +OP4 E022D8 0 +OP4 E022D9 0 +OP4 E022DA 0 +OP4 E022DB 0 +OP4 E022DC 0 +OP4 E022DD 0 +OP4 E022DE 0 +OP4 E022DF 0 +OP4 E022E0 0 +OP4 E022E1 0 +OP4 E022E2 0 +OP4 E022E3 0 +OP4 E022E4 0 +OP4 E022E5 0 +OP4 E022E6 0 +OP4 E022E7 0 +OP4 E022E8 0 +OP4 E022E9 0 +OP4 E022EA 0 +OP4 E022EB 0 +OP4 E022EC 0 +OP4 E022ED 0 +OP4 E022EE 0 +OP4 E022EF 0 +OP4 E022F0 0 +OP4 E022F1 0 +OP4 E022F2 0 +OP4 E022F3 0 +OP4 E022F4 0 +OP4 E022F5 0 +OP4 E022F6 0 +OP4 E022F7 0 +OP4 E022F8 0 +OP4 E022F9 0 +OP4 E022FA 0 +OP4 E022FB 0 +OP4 E022FC 0 +OP4 E022FD 0 +OP4 E022FE 0 +OP4 E022FF 0 +OP4 E02300 0 +OP4 E02301 0 +OP4 E02302 0 +OP4 E02303 0 +OP4 E02304 0 +OP4 E02305 0 +OP4 E02306 0 +OP4 E02307 0 +OP4 E02308 0 +OP4 E02309 0 +OP4 E0230A 0 +OP4 E0230B 0 +OP4 E0230C 0 +OP4 E0230D 0 +OP4 E0230E 0 +OP4 E0230F 0 +OP4 E02310 0 +OP4 E02311 0 +OP4 E02312 0 +OP4 E02313 0 +OP4 E02314 0 +OP4 E02315 0 +OP4 E02316 0 +OP4 E02317 0 +OP4 E02318 0 +OP4 E02319 0 +OP4 E0231A 0 +OP4 E0231B 0 +OP4 E0231C 0 +OP4 E0231D 0 +OP4 E0231E 0 +OP4 E0231F 0 +OP4 E02320 0 +OP4 E02321 0 +OP4 E02322 0 +OP4 E02323 0 +OP4 E02324 0 +OP4 E02325 0 +OP4 E02326 0 +OP4 E02327 0 +OP4 E02328 0 +OP4 E02329 0 +OP4 E0232A 0 +OP4 E0232B 0 +OP4 E0232C 0 +OP4 E0232D 0 +OP4 E0232E 0 +OP4 E0232F 0 +OP4 E02330 0 +OP4 E02331 0 +OP4 E02332 0 +OP4 E02333 0 +OP4 E02334 0 +OP4 E02335 0 +OP4 E02336 0 +OP4 E02337 0 +OP4 E02338 0 +OP4 E02339 0 +OP4 E0233A 0 +OP4 E0233B 0 +OP4 E0233C 0 +OP4 E0233D 0 +OP4 E0233E 0 +OP4 E0233F 0 +OP4 E02340 0 +OP4 E02341 0 +OP4 E02342 0 +OP4 E02343 0 +OP4 E02344 0 +OP4 E02345 0 +OP4 E02346 0 +OP4 E02347 0 +OP4 E02348 0 +OP4 E02349 0 +OP4 E0234A 0 +OP4 E0234B 0 +OP4 E0234C 0 +OP4 E0234D 0 +OP4 E0234E 0 +OP4 E0234F 0 +OP4 E02350 0 +OP4 E02351 0 +OP4 E02352 0 +OP4 E02353 0 +OP4 E02354 0 +OP4 E02355 0 +OP4 E02356 0 +OP4 E02357 0 +OP4 E02358 0 +OP4 E02359 0 +OP4 E0235A 0 +OP4 E0235B 0 +OP4 E0235C 0 +OP4 E0235D 0 +OP4 E0235E 0 +OP4 E0235F 0 +OP4 E02360 0 +OP4 E02361 0 +OP4 E02362 0 +OP4 E02363 0 +OP4 E02364 0 +OP4 E02365 0 +OP4 E02366 0 +OP4 E02367 0 +OP4 E02368 0 +OP4 E02369 0 +OP4 E0236A 0 +OP4 E0236B 0 +OP4 E0236C 0 +OP4 E0236D 0 +OP4 E0236E 0 +OP4 E0236F 0 +OP4 E02370 0 +OP4 E02371 0 +OP4 E02372 0 +OP4 E02373 0 +OP4 E02374 0 +OP4 E02375 0 +OP4 E02376 0 +OP4 E02377 0 +OP4 E02378 0 +OP4 E02379 0 +OP4 E0237A 0 +OP4 E0237B 0 +OP4 E0237C 0 +OP4 E0237D 0 +OP4 E0237E 0 +OP4 E0237F 0 +OP4 E02380 0 +OP4 E02381 0 +OP4 E02382 0 +OP4 E02383 0 +OP4 E02384 0 +OP4 E02385 0 +OP4 E02386 0 +OP4 E02387 0 +OP4 E02388 0 +OP4 E02389 0 +OP4 E0238A 0 +OP4 E0238B 0 +OP4 E0238C 0 +OP4 E0238D 0 +OP4 E0238E 0 +OP4 E0238F 0 +OP4 E02390 0 +OP4 E02391 0 +OP4 E02392 0 +OP4 E02393 0 +OP4 E02394 0 +OP4 E02395 0 +OP4 E02396 0 +OP4 E02397 0 +OP4 E02398 0 +OP4 E02399 0 +OP4 E0239A 0 +OP4 E0239B 0 +OP4 E0239C 0 +OP4 E0239D 0 +OP4 E0239E 0 +OP4 E0239F 0 +OP4 E023A0 0 +OP4 E023A1 0 +OP4 E023A2 0 +OP4 E023A3 0 +OP4 E023A4 0 +OP4 E023A5 0 +OP4 E023A6 0 +OP4 E023A7 0 +OP4 E023A8 0 +OP4 E023A9 0 +OP4 E023AA 0 +OP4 E023AB 0 +OP4 E023AC 0 +OP4 E023AD 0 +OP4 E023AE 0 +OP4 E023AF 0 +OP4 E023B0 0 +OP4 E023B1 0 +OP4 E023B2 0 +OP4 E023B3 0 +OP4 E023B4 0 +OP4 E023B5 0 +OP4 E023B6 0 +OP4 E023B7 0 +OP4 E023B8 0 +OP4 E023B9 0 +OP4 E023BA 0 +OP4 E023BB 0 +OP4 E023BC 0 +OP4 E023BD 0 +OP4 E023BE 0 +OP4 E023BF 0 +OP4 E023C0 0 +OP4 E023C1 0 +OP4 E023C2 0 +OP4 E023C3 0 +OP4 E023C4 0 +OP4 E023C5 0 +OP4 E023C6 0 +OP4 E023C7 0 +OP4 E023C8 0 +OP4 E023C9 0 +OP4 E023CA 0 +OP4 E023CB 0 +OP4 E023CC 0 +OP4 E023CD 0 +OP4 E023CE 0 +OP4 E023CF 0 +OP4 E023D0 0 +OP4 E023D1 0 +OP4 E023D2 0 +OP4 E023D3 0 +OP4 E023D4 0 +OP4 E023D5 0 +OP4 E023D6 0 +OP4 E023D7 0 +OP4 E023D8 0 +OP4 E023D9 0 +OP4 E023DA 0 +OP4 E023DB 0 +OP4 E023DC 0 +OP4 E023DD 0 +OP4 E023DE 0 +OP4 E023DF 0 +OP4 E023E0 0 +OP4 E023E1 0 +OP4 E023E2 0 +OP4 E023E3 0 +OP4 E023E4 0 +OP4 E023E5 0 +OP4 E023E6 0 +OP4 E023E7 0 +OP4 E023E8 0 +OP4 E023E9 0 +OP4 E023EA 0 +OP4 E023EB 0 +OP4 E023EC 0 +OP4 E023ED 0 +OP4 E023EE 0 +OP4 E023EF 0 +OP4 E023F0 0 +OP4 E023F1 0 +OP4 E023F2 0 +OP4 E023F3 0 +OP4 E023F4 0 +OP4 E023F5 0 +OP4 E023F6 0 +OP4 E023F7 0 +OP4 E023F8 0 +OP4 E023F9 0 +OP4 E023FA 0 +OP4 E023FB 0 +OP4 E023FC 0 +OP4 E023FD 0 +OP4 E023FE 0 +OP4 E023FF 0 +OP4 E02400 0 +OP4 E02401 0 +OP4 E02402 0 +OP4 E02403 0 +OP4 E02404 0 +OP4 E02405 0 +OP4 E02406 0 +OP4 E02407 0 +OP4 E02408 0 +OP4 E02409 0 +OP4 E0240A 0 +OP4 E0240B 0 +OP4 E0240C 0 +OP4 E0240D 0 +OP4 E0240E 0 +OP4 E0240F 0 +OP4 E02410 0 +OP4 E02411 0 +OP4 E02412 0 +OP4 E02413 0 +OP4 E02414 0 +OP4 E02415 0 +OP4 E02416 0 +OP4 E02417 0 +OP4 E02418 0 +OP4 E02419 0 +OP4 E0241A 0 +OP4 E0241B 0 +OP4 E0241C 0 +OP4 E0241D 0 +OP4 E0241E 0 +OP4 E0241F 0 +OP4 E02420 0 +OP4 E02421 0 +OP4 E02422 0 +OP4 E02423 0 +OP4 E02424 0 +OP4 E02425 0 +OP4 E02426 0 +OP4 E02427 0 +OP4 E02428 0 +OP4 E02429 0 +OP4 E0242A 0 +OP4 E0242B 0 +OP4 E0242C 0 +OP4 E0242D 0 +OP4 E0242E 0 +OP4 E0242F 0 +OP4 E02430 0 +OP4 E02431 0 +OP4 E02432 0 +OP4 E02433 0 +OP4 E02434 0 +OP4 E02435 0 +OP4 E02436 0 +OP4 E02437 0 +OP4 E02438 0 +OP4 E02439 0 +OP4 E0243A 0 +OP4 E0243B 0 +OP4 E0243C 0 +OP4 E0243D 0 +OP4 E0243E 0 +OP4 E0243F 0 +OP4 E02440 0 +OP4 E02441 0 +OP4 E02442 0 +OP4 E02443 0 +OP4 E02444 0 +OP4 E02445 0 +OP4 E02446 0 +OP4 E02447 0 +OP4 E02448 0 +OP4 E02449 0 +OP4 E0244A 0 +OP4 E0244B 0 +OP4 E0244C 0 +OP4 E0244D 0 +OP4 E0244E 0 +OP4 E0244F 0 +OP4 E02450 0 +OP4 E02451 0 +OP4 E02452 0 +OP4 E02453 0 +OP4 E02454 0 +OP4 E02455 0 +OP4 E02456 0 +OP4 E02457 0 +OP4 E02458 0 +OP4 E02459 0 +OP4 E0245A 0 +OP4 E0245B 0 +OP4 E0245C 0 +OP4 E0245D 0 +OP4 E0245E 0 +OP4 E0245F 0 +OP4 E02460 0 +OP4 E02461 0 +OP4 E02462 0 +OP4 E02463 0 +OP4 E02464 0 +OP4 E02465 0 +OP4 E02466 0 +OP4 E02467 0 +OP4 E02468 0 +OP4 E02469 0 +OP4 E0246A 0 +OP4 E0246B 0 +OP4 E0246C 0 +OP4 E0246D 0 +OP4 E0246E 0 +OP4 E0246F 0 +OP4 E02470 0 +OP4 E02471 0 +OP4 E02472 0 +OP4 E02473 0 +OP4 E02474 0 +OP4 E02475 0 +OP4 E02476 0 +OP4 E02477 0 +OP4 E02478 0 +OP4 E02479 0 +OP4 E0247A 0 +OP4 E0247B 0 +OP4 E0247C 0 +OP4 E0247D 0 +OP4 E0247E 0 +OP4 E0247F 0 +OP4 E02480 0 +OP4 E02481 0 +OP4 E02482 0 +OP4 E02483 0 +OP4 E02484 0 +OP4 E02485 0 +OP4 E02486 0 +OP4 E02487 0 +OP4 E02488 0 +OP4 E02489 0 +OP4 E0248A 0 +OP4 E0248B 0 +OP4 E0248C 0 +OP4 E0248D 0 +OP4 E0248E 0 +OP4 E0248F 0 +OP4 E02490 0 +OP4 E02491 0 +OP4 E02492 0 +OP4 E02493 0 +OP4 E02494 0 +OP4 E02495 0 +OP4 E02496 0 +OP4 E02497 0 +OP4 E02498 0 +OP4 E02499 0 +OP4 E0249A 0 +OP4 E0249B 0 +OP4 E0249C 0 +OP4 E0249D 0 +OP4 E0249E 0 +OP4 E0249F 0 +OP4 E024A0 0 +OP4 E024A1 0 +OP4 E024A2 0 +OP4 E024A3 0 +OP4 E024A4 0 +OP4 E024A5 0 +OP4 E024A6 0 +OP4 E024A7 0 +OP4 E024A8 0 +OP4 E024A9 0 +OP4 E024AA 0 +OP4 E024AB 0 +OP4 E024AC 0 +OP4 E024AD 0 +OP4 E024AE 0 +OP4 E024AF 0 +OP4 E024B0 0 +OP4 E024B1 0 +OP4 E024B2 0 +OP4 E024B3 0 +OP4 E024B4 0 +OP4 E024B5 0 +OP4 E024B6 0 +OP4 E024B7 0 +OP4 E024B8 0 +OP4 E024B9 0 +OP4 E024BA 0 +OP4 E024BB 0 +OP4 E024BC 0 +OP4 E024BD 0 +OP4 E024BE 0 +OP4 E024BF 0 +OP4 E024C0 0 +OP4 E024C1 0 +OP4 E024C2 0 +OP4 E024C3 0 +OP4 E024C4 0 +OP4 E024C5 0 +OP4 E024C6 0 +OP4 E024C7 0 +OP4 E024C8 0 +OP4 E024C9 0 +OP4 E024CA 0 +OP4 E024CB 0 +OP4 E024CC 0 +OP4 E024CD 0 +OP4 E024CE 0 +OP4 E024CF 0 +OP4 E024D0 0 +OP4 E024D1 0 +OP4 E024D2 0 +OP4 E024D3 0 +OP4 E024D4 0 +OP4 E024D5 0 +OP4 E024D6 0 +OP4 E024D7 0 +OP4 E024D8 0 +OP4 E024D9 0 +OP4 E024DA 0 +OP4 E024DB 0 +OP4 E024DC 0 +OP4 E024DD 0 +OP4 E024DE 0 +OP4 E024DF 0 +OP4 E024E0 0 +OP4 E024E1 0 +OP4 E024E2 0 +OP4 E024E3 0 +OP4 E024E4 0 +OP4 E024E5 0 +OP4 E024E6 0 +OP4 E024E7 0 +OP4 E024E8 0 +OP4 E024E9 0 +OP4 E024EA 0 +OP4 E024EB 0 +OP4 E024EC 0 +OP4 E024ED 0 +OP4 E024EE 0 +OP4 E024EF 0 +OP4 E024F0 0 +OP4 E024F1 0 +OP4 E024F2 0 +OP4 E024F3 0 +OP4 E024F4 0 +OP4 E024F5 0 +OP4 E024F6 0 +OP4 E024F7 0 +OP4 E024F8 0 +OP4 E024F9 0 +OP4 E024FA 0 +OP4 E024FB 0 +OP4 E024FC 0 +OP4 E024FD 0 +OP4 E024FE 0 +OP4 E024FF 0 +OP4 E02500 0 +OP4 E02501 0 +OP4 E02502 0 +OP4 E02503 0 +OP4 E02504 0 +OP4 E02505 0 +OP4 E02506 0 +OP4 E02507 0 +OP4 E02508 0 +OP4 E02509 0 +OP4 E0250A 0 +OP4 E0250B 0 +OP4 E0250C 0 +OP4 E0250D 0 +OP4 E0250E 0 +OP4 E0250F 0 +OP4 E02510 0 +OP4 E02511 0 +OP4 E02512 0 +OP4 E02513 0 +OP4 E02514 0 +OP4 E02515 0 +OP4 E02516 0 +OP4 E02517 0 +OP4 E02518 0 +OP4 E02519 0 +OP4 E0251A 0 +OP4 E0251B 0 +OP4 E0251C 0 +OP4 E0251D 0 +OP4 E0251E 0 +OP4 E0251F 0 +OP4 E02520 0 +OP4 E02521 0 +OP4 E02522 0 +OP4 E02523 0 +OP4 E02524 0 +OP4 E02525 0 +OP4 E02526 0 +OP4 E02527 0 +OP4 E02528 0 +OP4 E02529 0 +OP4 E0252A 0 +OP4 E0252B 0 +OP4 E0252C 0 +OP4 E0252D 0 +OP4 E0252E 0 +OP4 E0252F 0 +OP4 E02530 0 +OP4 E02531 0 +OP4 E02532 0 +OP4 E02533 0 +OP4 E02534 0 +OP4 E02535 0 +OP4 E02536 0 +OP4 E02537 0 +OP4 E02538 0 +OP4 E02539 0 +OP4 E0253A 0 +OP4 E0253B 0 +OP4 E0253C 0 +OP4 E0253D 0 +OP4 E0253E 0 +OP4 E0253F 0 +OP4 E02540 0 +OP4 E02541 0 +OP4 E02542 0 +OP4 E02543 0 +OP4 E02544 0 +OP4 E02545 0 +OP4 E02546 0 +OP4 E02547 0 +OP4 E02548 0 +OP4 E02549 0 +OP4 E0254A 0 +OP4 E0254B 0 +OP4 E0254C 0 +OP4 E0254D 0 +OP4 E0254E 0 +OP4 E0254F 0 +OP4 E02550 0 +OP4 E02551 0 +OP4 E02552 0 +OP4 E02553 0 +OP4 E02554 0 +OP4 E02555 0 +OP4 E02556 0 +OP4 E02557 0 +OP4 E02558 0 +OP4 E02559 0 +OP4 E0255A 0 +OP4 E0255B 0 +OP4 E0255C 0 +OP4 E0255D 0 +OP4 E0255E 0 +OP4 E0255F 0 +OP4 E02560 0 +OP4 E02561 0 +OP4 E02562 0 +OP4 E02563 0 +OP4 E02564 0 +OP4 E02565 0 +OP4 E02566 0 +OP4 E02567 0 +OP4 E02568 0 +OP4 E02569 0 +OP4 E0256A 0 +OP4 E0256B 0 +OP4 E0256C 0 +OP4 E0256D 0 +OP4 E0256E 0 +OP4 E0256F 0 +OP4 E02570 0 +OP4 E02571 0 +OP4 E02572 0 +OP4 E02573 0 +OP4 E02574 0 +OP4 E02575 0 +OP4 E02576 0 +OP4 E02577 0 +OP4 E02578 0 +OP4 E02579 0 +OP4 E0257A 0 +OP4 E0257B 0 +OP4 E0257C 0 +OP4 E0257D 0 +OP4 E0257E 0 +OP4 E0257F 0 +OP4 E02580 0 +OP4 E02581 0 +OP4 E02582 0 +OP4 E02583 0 +OP4 E02584 0 +OP4 E02585 0 +OP4 E02586 0 +OP4 E02587 0 +OP4 E02588 0 +OP4 E02589 0 +OP4 E0258A 0 +OP4 E0258B 0 +OP4 E0258C 0 +OP4 E0258D 0 +OP4 E0258E 0 +OP4 E0258F 0 +OP4 E02590 0 +OP4 E02591 0 +OP4 E02592 0 +OP4 E02593 0 +OP4 E02594 0 +OP4 E02595 0 +OP4 E02596 0 +OP4 E02597 0 +OP4 E02598 0 +OP4 E02599 0 +OP4 E0259A 0 +OP4 E0259B 0 +OP4 E0259C 0 +OP4 E0259D 0 +OP4 E0259E 0 +OP4 E0259F 0 +OP4 E025A0 0 +OP4 E025A1 0 +OP4 E025A2 0 +OP4 E025A3 0 +OP4 E025A4 0 +OP4 E025A5 0 +OP4 E025A6 0 +OP4 E025A7 0 +OP4 E025A8 0 +OP4 E025A9 0 +OP4 E025AA 0 +OP4 E025AB 0 +OP4 E025AC 0 +OP4 E025AD 0 +OP4 E025AE 0 +OP4 E025AF 0 +OP4 E025B0 0 +OP4 E025B1 0 +OP4 E025B2 0 +OP4 E025B3 0 +OP4 E025B4 0 +OP4 E025B5 0 +OP4 E025B6 0 +OP4 E025B7 0 +OP4 E025B8 0 +OP4 E025B9 0 +OP4 E025BA 0 +OP4 E025BB 0 +OP4 E025BC 0 +OP4 E025BD 0 +OP4 E025BE 0 +OP4 E025BF 0 +OP4 E025C0 0 +OP4 E025C1 0 +OP4 E025C2 0 +OP4 E025C3 0 +OP4 E025C4 0 +OP4 E025C5 0 +OP4 E025C6 0 +OP4 E025C7 0 +OP4 E025C8 0 +OP4 E025C9 0 +OP4 E025CA 0 +OP4 E025CB 0 +OP4 E025CC 0 +OP4 E025CD 0 +OP4 E025CE 0 +OP4 E025CF 0 +OP4 E025D0 0 +OP4 E025D1 0 +OP4 E025D2 0 +OP4 E025D3 0 +OP4 E025D4 0 +OP4 E025D5 0 +OP4 E025D6 0 +OP4 E025D7 0 +OP4 E025D8 0 +OP4 E025D9 0 +OP4 E025DA 0 +OP4 E025DB 0 +OP4 E025DC 0 +OP4 E025DD 0 +OP4 E025DE 0 +OP4 E025DF 0 +OP4 E025E0 0 +OP4 E025E1 0 +OP4 E025E2 0 +OP4 E025E3 0 +OP4 E025E4 0 +OP4 E025E5 0 +OP4 E025E6 0 +OP4 E025E7 0 +OP4 E025E8 0 +OP4 E025E9 0 +OP4 E025EA 0 +OP4 E025EB 0 +OP4 E025EC 0 +OP4 E025ED 0 +OP4 E025EE 0 +OP4 E025EF 0 +OP4 E025F0 0 +OP4 E025F1 0 +OP4 E025F2 0 +OP4 E025F3 0 +OP4 E025F4 0 +OP4 E025F5 0 +OP4 E025F6 0 +OP4 E025F7 0 +OP4 E025F8 0 +OP4 E025F9 0 +OP4 E025FA 0 +OP4 E025FB 0 +OP4 E025FC 0 +OP4 E025FD 0 +OP4 E025FE 0 +OP4 E025FF 0 +OP4 E02600 0 +OP4 E02601 0 +OP4 E02602 0 +OP4 E02603 0 +OP4 E02604 0 +OP4 E02605 0 +OP4 E02606 0 +OP4 E02607 0 +OP4 E02608 0 +OP4 E02609 0 +OP4 E0260A 0 +OP4 E0260B 0 +OP4 E0260C 0 +OP4 E0260D 0 +OP4 E0260E 0 +OP4 E0260F 0 +OP4 E02610 0 +OP4 E02611 0 +OP4 E02612 0 +OP4 E02613 0 +OP4 E02614 0 +OP4 E02615 0 +OP4 E02616 0 +OP4 E02617 0 +OP4 E02618 0 +OP4 E02619 0 +OP4 E0261A 0 +OP4 E0261B 0 +OP4 E0261C 0 +OP4 E0261D 0 +OP4 E0261E 0 +OP4 E0261F 0 +OP4 E02620 0 +OP4 E02621 0 +OP4 E02622 0 +OP4 E02623 0 +OP4 E02624 0 +OP4 E02625 0 +OP4 E02626 0 +OP4 E02627 0 +OP4 E02628 0 +OP4 E02629 0 +OP4 E0262A 0 +OP4 E0262B 0 +OP4 E0262C 0 +OP4 E0262D 0 +OP4 E0262E 0 +OP4 E0262F 0 +OP4 E02630 0 +OP4 E02631 0 +OP4 E02632 0 +OP4 E02633 0 +OP4 E02634 0 +OP4 E02635 0 +OP4 E02636 0 +OP4 E02637 0 +OP4 E02638 0 +OP4 E02639 0 +OP4 E0263A 0 +OP4 E0263B 0 +OP4 E0263C 0 +OP4 E0263D 0 +OP4 E0263E 0 +OP4 E0263F 0 +OP4 E02640 0 +OP4 E02641 0 +OP4 E02642 0 +OP4 E02643 0 +OP4 E02644 0 +OP4 E02645 0 +OP4 E02646 0 +OP4 E02647 0 +OP4 E02648 0 +OP4 E02649 0 +OP4 E0264A 0 +OP4 E0264B 0 +OP4 E0264C 0 +OP4 E0264D 0 +OP4 E0264E 0 +OP4 E0264F 0 +OP4 E02650 0 +OP4 E02651 0 +OP4 E02652 0 +OP4 E02653 0 +OP4 E02654 0 +OP4 E02655 0 +OP4 E02656 0 +OP4 E02657 0 +OP4 E02658 0 +OP4 E02659 0 +OP4 E0265A 0 +OP4 E0265B 0 +OP4 E0265C 0 +OP4 E0265D 0 +OP4 E0265E 0 +OP4 E0265F 0 +OP4 E02660 0 +OP4 E02661 0 +OP4 E02662 0 +OP4 E02663 0 +OP4 E02664 0 +OP4 E02665 0 +OP4 E02666 0 +OP4 E02667 0 +OP4 E02668 0 +OP4 E02669 0 +OP4 E0266A 0 +OP4 E0266B 0 +OP4 E0266C 0 +OP4 E0266D 0 +OP4 E0266E 0 +OP4 E0266F 0 +OP4 E02670 0 +OP4 E02671 0 +OP4 E02672 0 +OP4 E02673 0 +OP4 E02674 0 +OP4 E02675 0 +OP4 E02676 0 +OP4 E02677 0 +OP4 E02678 0 +OP4 E02679 0 +OP4 E0267A 0 +OP4 E0267B 0 +OP4 E0267C 0 +OP4 E0267D 0 +OP4 E0267E 0 +OP4 E0267F 0 +OP4 E02680 0 +OP4 E02681 0 +OP4 E02682 0 +OP4 E02683 0 +OP4 E02684 0 +OP4 E02685 0 +OP4 E02686 0 +OP4 E02687 0 +OP4 E02688 0 +OP4 E02689 0 +OP4 E0268A 0 +OP4 E0268B 0 +OP4 E0268C 0 +OP4 E0268D 0 +OP4 E0268E 0 +OP4 E0268F 0 +OP4 E02690 0 +OP4 E02691 0 +OP4 E02692 0 +OP4 E02693 0 +OP4 E02694 0 +OP4 E02695 0 +OP4 E02696 0 +OP4 E02697 0 +OP4 E02698 0 +OP4 E02699 0 +OP4 E0269A 0 +OP4 E0269B 0 +OP4 E0269C 0 +OP4 E0269D 0 +OP4 E0269E 0 +OP4 E0269F 0 +OP4 E026A0 0 +OP4 E026A1 0 +OP4 E026A2 0 +OP4 E026A3 0 +OP4 E026A4 0 +OP4 E026A5 0 +OP4 E026A6 0 +OP4 E026A7 0 +OP4 E026A8 0 +OP4 E026A9 0 +OP4 E026AA 0 +OP4 E026AB 0 +OP4 E026AC 0 +OP4 E026AD 0 +OP4 E026AE 0 +OP4 E026AF 0 +OP4 E026B0 0 +OP4 E026B1 0 +OP4 E026B2 0 +OP4 E026B3 0 +OP4 E026B4 0 +OP4 E026B5 0 +OP4 E026B6 0 +OP4 E026B7 0 +OP4 E026B8 0 +OP4 E026B9 0 +OP4 E026BA 0 +OP4 E026BB 0 +OP4 E026BC 0 +OP4 E026BD 0 +OP4 E026BE 0 +OP4 E026BF 0 +OP4 E026C0 0 +OP4 E026C1 0 +OP4 E026C2 0 +OP4 E026C3 0 +OP4 E026C4 0 +OP4 E026C5 0 +OP4 E026C6 0 +OP4 E026C7 0 +OP4 E026C8 0 +OP4 E026C9 0 +OP4 E026CA 0 +OP4 E026CB 0 +OP4 E026CC 0 +OP4 E026CD 0 +OP4 E026CE 0 +OP4 E026CF 0 +OP4 E026D0 0 +OP4 E026D1 0 +OP4 E026D2 0 +OP4 E026D3 0 +OP4 E026D4 0 +OP4 E026D5 0 +OP4 E026D6 0 +OP4 E026D7 0 +OP4 E026D8 0 +OP4 E026D9 0 +OP4 E026DA 0 +OP4 E026DB 0 +OP4 E026DC 0 +OP4 E026DD 0 +OP4 E026DE 0 +OP4 E026DF 0 +OP4 E026E0 0 +OP4 E026E1 0 +OP4 E026E2 0 +OP4 E026E3 0 +OP4 E026E4 0 +OP4 E026E5 0 +OP4 E026E6 0 +OP4 E026E7 0 +OP4 E026E8 0 +OP4 E026E9 0 +OP4 E026EA 0 +OP4 E026EB 0 +OP4 E026EC 0 +OP4 E026ED 0 +OP4 E026EE 0 +OP4 E026EF 0 +OP4 E026F0 0 +OP4 E026F1 0 +OP4 E026F2 0 +OP4 E026F3 0 +OP4 E026F4 0 +OP4 E026F5 0 +OP4 E026F6 0 +OP4 E026F7 0 +OP4 E026F8 0 +OP4 E026F9 0 +OP4 E026FA 0 +OP4 E026FB 0 +OP4 E026FC 0 +OP4 E026FD 0 +OP4 E026FE 0 +OP4 E026FF 0 +OP4 E02700 0 +OP4 E02701 0 +OP4 E02702 0 +OP4 E02703 0 +OP4 E02704 0 +OP4 E02705 0 +OP4 E02706 0 +OP4 E02707 0 +OP4 E02708 0 +OP4 E02709 0 +OP4 E0270A 0 +OP4 E0270B 0 +OP4 E0270C 0 +OP4 E0270D 0 +OP4 E0270E 0 +OP4 E0270F 0 +OP4 E02710 0 +OP4 E02711 0 +OP4 E02712 0 +OP4 E02713 0 +OP4 E02714 0 +OP4 E02715 0 +OP4 E02716 0 +OP4 E02717 0 +OP4 E02718 0 +OP4 E02719 0 +OP4 E0271A 0 +OP4 E0271B 0 +OP4 E0271C 0 +OP4 E0271D 0 +OP4 E0271E 0 +OP4 E0271F 0 +OP4 E02720 0 +OP4 E02721 0 +OP4 E02722 0 +OP4 E02723 0 +OP4 E02724 0 +OP4 E02725 0 +OP4 E02726 0 +OP4 E02727 0 +OP4 E02728 0 +OP4 E02729 0 +OP4 E0272A 0 +OP4 E0272B 0 +OP4 E0272C 0 +OP4 E0272D 0 +OP4 E0272E 0 +OP4 E0272F 0 +OP4 E02730 0 +OP4 E02731 0 +OP4 E02732 0 +OP4 E02733 0 +OP4 E02734 0 +OP4 E02735 0 +OP4 E02736 0 +OP4 E02737 0 +OP4 E02738 0 +OP4 E02739 0 +OP4 E0273A 0 +OP4 E0273B 0 +OP4 E0273C 0 +OP4 E0273D 0 +OP4 E0273E 0 +OP4 E0273F 0 +OP4 E02740 0 +OP4 E02741 0 +OP4 E02742 0 +OP4 E02743 0 +OP4 E02744 0 +OP4 E02745 0 +OP4 E02746 0 +OP4 E02747 0 +OP4 E02748 0 +OP4 E02749 0 +OP4 E0274A 0 +OP4 E0274B 0 +OP4 E0274C 0 +OP4 E0274D 0 +OP4 E0274E 0 +OP4 E0274F 0 +OP4 E02750 0 +OP4 E02751 0 +OP4 E02752 0 +OP4 E02753 0 +OP4 E02754 0 +OP4 E02755 0 +OP4 E02756 0 +OP4 E02757 0 +OP4 E02758 0 +OP4 E02759 0 +OP4 E0275A 0 +OP4 E0275B 0 +OP4 E0275C 0 +OP4 E0275D 0 +OP4 E0275E 0 +OP4 E0275F 0 +OP4 E02760 0 +OP4 E02761 0 +OP4 E02762 0 +OP4 E02763 0 +OP4 E02764 0 +OP4 E02765 0 +OP4 E02766 0 +OP4 E02767 0 +OP4 E02768 0 +OP4 E02769 0 +OP4 E0276A 0 +OP4 E0276B 0 +OP4 E0276C 0 +OP4 E0276D 0 +OP4 E0276E 0 +OP4 E0276F 0 +OP4 E02770 0 +OP4 E02771 0 +OP4 E02772 0 +OP4 E02773 0 +OP4 E02774 0 +OP4 E02775 0 +OP4 E02776 0 +OP4 E02777 0 +OP4 E02778 0 +OP4 E02779 0 +OP4 E0277A 0 +OP4 E0277B 0 +OP4 E0277C 0 +OP4 E0277D 0 +OP4 E0277E 0 +OP4 E0277F 0 +OP4 E02780 0 +OP4 E02781 0 +OP4 E02782 0 +OP4 E02783 0 +OP4 E02784 0 +OP4 E02785 0 +OP4 E02786 0 +OP4 E02787 0 +OP4 E02788 0 +OP4 E02789 0 +OP4 E0278A 0 +OP4 E0278B 0 +OP4 E0278C 0 +OP4 E0278D 0 +OP4 E0278E 0 +OP4 E0278F 0 +OP4 E02790 0 +OP4 E02791 0 +OP4 E02792 0 +OP4 E02793 0 +OP4 E02794 0 +OP4 E02795 0 +OP4 E02796 0 +OP4 E02797 0 +OP4 E02798 0 +OP4 E02799 0 +OP4 E0279A 0 +OP4 E0279B 0 +OP4 E0279C 0 +OP4 E0279D 0 +OP4 E0279E 0 +OP4 E0279F 0 +OP4 E027A0 0 +OP4 E027A1 0 +OP4 E027A2 0 +OP4 E027A3 0 +OP4 E027A4 0 +OP4 E027A5 0 +OP4 E027A6 0 +OP4 E027A7 0 +OP4 E027A8 0 +OP4 E027A9 0 +OP4 E027AA 0 +OP4 E027AB 0 +OP4 E027AC 0 +OP4 E027AD 0 +OP4 E027AE 0 +OP4 E027AF 0 +OP4 E027B0 0 +OP4 E027B1 0 +OP4 E027B2 0 +OP4 E027B3 0 +OP4 E027B4 0 +OP4 E027B5 0 +OP4 E027B6 0 +OP4 E027B7 0 +OP4 E027B8 0 +OP4 E027B9 0 +OP4 E027BA 0 +OP4 E027BB 0 +OP4 E027BC 0 +OP4 E027BD 0 +OP4 E027BE 0 +OP4 E027BF 0 +OP4 E027C0 0 +OP4 E027C1 0 +OP4 E027C2 0 +OP4 E027C3 0 +OP4 E027C4 0 +OP4 E027C5 0 +OP4 E027C6 0 +OP4 E027C7 0 +OP4 E027C8 0 +OP4 E027C9 0 +OP4 E027CA 0 +OP4 E027CB 0 +OP4 E027CC 0 +OP4 E027CD 0 +OP4 E027CE 0 +OP4 E027CF 0 +OP4 E027D0 0 +OP4 E027D1 0 +OP4 E027D2 0 +OP4 E027D3 0 +OP4 E027D4 0 +OP4 E027D5 0 +OP4 E027D6 0 +OP4 E027D7 0 +OP4 E027D8 0 +OP4 E027D9 0 +OP4 E027DA 0 +OP4 E027DB 0 +OP4 E027DC 0 +OP4 E027DD 0 +OP4 E027DE 0 +OP4 E027DF 0 +OP4 E027E0 0 +OP4 E027E1 0 +OP4 E027E2 0 +OP4 E027E3 0 +OP4 E027E4 0 +OP4 E027E5 0 +OP4 E027E6 0 +OP4 E027E7 0 +OP4 E027E8 0 +OP4 E027E9 0 +OP4 E027EA 0 +OP4 E027EB 0 +OP4 E027EC 0 +OP4 E027ED 0 +OP4 E027EE 0 +OP4 E027EF 0 +OP4 E027F0 0 +OP4 E027F1 0 +OP4 E027F2 0 +OP4 E027F3 0 +OP4 E027F4 0 +OP4 E027F5 0 +OP4 E027F6 0 +OP4 E027F7 0 +OP4 E027F8 0 +OP4 E027F9 0 +OP4 E027FA 0 +OP4 E027FB 0 +OP4 E027FC 0 +OP4 E027FD 0 +OP4 E027FE 0 +OP4 E027FF 0 +OP4 E02800 0 +OP4 E02801 0 +OP4 E02802 0 +OP4 E02803 0 +OP4 E02804 0 +OP4 E02805 0 +OP4 E02806 0 +OP4 E02807 0 +OP4 E02808 0 +OP4 E02809 0 +OP4 E0280A 0 +OP4 E0280B 0 +OP4 E0280C 0 +OP4 E0280D 0 +OP4 E0280E 0 +OP4 E0280F 0 +OP4 E02810 0 +OP4 E02811 0 +OP4 E02812 0 +OP4 E02813 0 +OP4 E02814 0 +OP4 E02815 0 +OP4 E02816 0 +OP4 E02817 0 +OP4 E02818 0 +OP4 E02819 0 +OP4 E0281A 0 +OP4 E0281B 0 +OP4 E0281C 0 +OP4 E0281D 0 +OP4 E0281E 0 +OP4 E0281F 0 +OP4 E02820 0 +OP4 E02821 0 +OP4 E02822 0 +OP4 E02823 0 +OP4 E02824 0 +OP4 E02825 0 +OP4 E02826 0 +OP4 E02827 0 +OP4 E02828 0 +OP4 E02829 0 +OP4 E0282A 0 +OP4 E0282B 0 +OP4 E0282C 0 +OP4 E0282D 0 +OP4 E0282E 0 +OP4 E0282F 0 +OP4 E02830 0 +OP4 E02831 0 +OP4 E02832 0 +OP4 E02833 0 +OP4 E02834 0 +OP4 E02835 0 +OP4 E02836 0 +OP4 E02837 0 +OP4 E02838 0 +OP4 E02839 0 +OP4 E0283A 0 +OP4 E0283B 0 +OP4 E0283C 0 +OP4 E0283D 0 +OP4 E0283E 0 +OP4 E0283F 0 +OP4 E02840 0 +OP4 E02841 0 +OP4 E02842 0 +OP4 E02843 0 +OP4 E02844 0 +OP4 E02845 0 +OP4 E02846 0 +OP4 E02847 0 +OP4 E02848 0 +OP4 E02849 0 +OP4 E0284A 0 +OP4 E0284B 0 +OP4 E0284C 0 +OP4 E0284D 0 +OP4 E0284E 0 +OP4 E0284F 0 +OP4 E02850 0 +OP4 E02851 0 +OP4 E02852 0 +OP4 E02853 0 +OP4 E02854 0 +OP4 E02855 0 +OP4 E02856 0 +OP4 E02857 0 +OP4 E02858 0 +OP4 E02859 0 +OP4 E0285A 0 +OP4 E0285B 0 +OP4 E0285C 0 +OP4 E0285D 0 +OP4 E0285E 0 +OP4 E0285F 0 +OP4 E02860 0 +OP4 E02861 0 +OP4 E02862 0 +OP4 E02863 0 +OP4 E02864 0 +OP4 E02865 0 +OP4 E02866 0 +OP4 E02867 0 +OP4 E02868 0 +OP4 E02869 0 +OP4 E0286A 0 +OP4 E0286B 0 +OP4 E0286C 0 +OP4 E0286D 0 +OP4 E0286E 0 +OP4 E0286F 0 +OP4 E02870 0 +OP4 E02871 0 +OP4 E02872 0 +OP4 E02873 0 +OP4 E02874 0 +OP4 E02875 0 +OP4 E02876 0 +OP4 E02877 0 +OP4 E02878 0 +OP4 E02879 0 +OP4 E0287A 0 +OP4 E0287B 0 +OP4 E0287C 0 +OP4 E0287D 0 +OP4 E0287E 0 +OP4 E0287F 0 +OP4 E02880 0 +OP4 E02881 0 +OP4 E02882 0 +OP4 E02883 0 +OP4 E02884 0 +OP4 E02885 0 +OP4 E02886 0 +OP4 E02887 0 +OP4 E02888 0 +OP4 E02889 0 +OP4 E0288A 0 +OP4 E0288B 0 +OP4 E0288C 0 +OP4 E0288D 0 +OP4 E0288E 0 +OP4 E0288F 0 +OP4 E02890 0 +OP4 E02891 0 +OP4 E02892 0 +OP4 E02893 0 +OP4 E02894 0 +OP4 E02895 0 +OP4 E02896 0 +OP4 E02897 0 +OP4 E02898 0 +OP4 E02899 0 +OP4 E0289A 0 +OP4 E0289B 0 +OP4 E0289C 0 +OP4 E0289D 0 +OP4 E0289E 0 +OP4 E0289F 0 +OP4 E028A0 0 +OP4 E028A1 0 +OP4 E028A2 0 +OP4 E028A3 0 +OP4 E028A4 0 +OP4 E028A5 0 +OP4 E028A6 0 +OP4 E028A7 0 +OP4 E028A8 0 +OP4 E028A9 0 +OP4 E028AA 0 +OP4 E028AB 0 +OP4 E028AC 0 +OP4 E028AD 0 +OP4 E028AE 0 +OP4 E028AF 0 +OP4 E028B0 0 +OP4 E028B1 0 +OP4 E028B2 0 +OP4 E028B3 0 +OP4 E028B4 0 +OP4 E028B5 0 +OP4 E028B6 0 +OP4 E028B7 0 +OP4 E028B8 0 +OP4 E028B9 0 +OP4 E028BA 0 +OP4 E028BB 0 +OP4 E028BC 0 +OP4 E028BD 0 +OP4 E028BE 0 +OP4 E028BF 0 +OP4 E028C0 0 +OP4 E028C1 0 +OP4 E028C2 0 +OP4 E028C3 0 +OP4 E028C4 0 +OP4 E028C5 0 +OP4 E028C6 0 +OP4 E028C7 0 +OP4 E028C8 0 +OP4 E028C9 0 +OP4 E028CA 0 +OP4 E028CB 0 +OP4 E028CC 0 +OP4 E028CD 0 +OP4 E028CE 0 +OP4 E028CF 0 +OP4 E028D0 0 +OP4 E028D1 0 +OP4 E028D2 0 +OP4 E028D3 0 +OP4 E028D4 0 +OP4 E028D5 0 +OP4 E028D6 0 +OP4 E028D7 0 +OP4 E028D8 0 +OP4 E028D9 0 +OP4 E028DA 0 +OP4 E028DB 0 +OP4 E028DC 0 +OP4 E028DD 0 +OP4 E028DE 0 +OP4 E028DF 0 +OP4 E028E0 0 +OP4 E028E1 0 +OP4 E028E2 0 +OP4 E028E3 0 +OP4 E028E4 0 +OP4 E028E5 0 +OP4 E028E6 0 +OP4 E028E7 0 +OP4 E028E8 0 +OP4 E028E9 0 +OP4 E028EA 0 +OP4 E028EB 0 +OP4 E028EC 0 +OP4 E028ED 0 +OP4 E028EE 0 +OP4 E028EF 0 +OP4 E028F0 0 +OP4 E028F1 0 +OP4 E028F2 0 +OP4 E028F3 0 +OP4 E028F4 0 +OP4 E028F5 0 +OP4 E028F6 0 +OP4 E028F7 0 +OP4 E028F8 0 +OP4 E028F9 0 +OP4 E028FA 0 +OP4 E028FB 0 +OP4 E028FC 0 +OP4 E028FD 0 +OP4 E028FE 0 +OP4 E028FF 0 +OP4 E02900 0 +OP4 E02901 0 +OP4 E02902 0 +OP4 E02903 0 +OP4 E02904 0 +OP4 E02905 0 +OP4 E02906 0 +OP4 E02907 0 +OP4 E02908 0 +OP4 E02909 0 +OP4 E0290A 0 +OP4 E0290B 0 +OP4 E0290C 0 +OP4 E0290D 0 +OP4 E0290E 0 +OP4 E0290F 0 +OP4 E02910 0 +OP4 E02911 0 +OP4 E02912 0 +OP4 E02913 0 +OP4 E02914 0 +OP4 E02915 0 +OP4 E02916 0 +OP4 E02917 0 +OP4 E02918 0 +OP4 E02919 0 +OP4 E0291A 0 +OP4 E0291B 0 +OP4 E0291C 0 +OP4 E0291D 0 +OP4 E0291E 0 +OP4 E0291F 0 +OP4 E02920 0 +OP4 E02921 0 +OP4 E02922 0 +OP4 E02923 0 +OP4 E02924 0 +OP4 E02925 0 +OP4 E02926 0 +OP4 E02927 0 +OP4 E02928 0 +OP4 E02929 0 +OP4 E0292A 0 +OP4 E0292B 0 +OP4 E0292C 0 +OP4 E0292D 0 +OP4 E0292E 0 +OP4 E0292F 0 +OP4 E02930 0 +OP4 E02931 0 +OP4 E02932 0 +OP4 E02933 0 +OP4 E02934 0 +OP4 E02935 0 +OP4 E02936 0 +OP4 E02937 0 +OP4 E02938 0 +OP4 E02939 0 +OP4 E0293A 0 +OP4 E0293B 0 +OP4 E0293C 0 +OP4 E0293D 0 +OP4 E0293E 0 +OP4 E0293F 0 +OP4 E02940 0 +OP4 E02941 0 +OP4 E02942 0 +OP4 E02943 0 +OP4 E02944 0 +OP4 E02945 0 +OP4 E02946 0 +OP4 E02947 0 +OP4 E02948 0 +OP4 E02949 0 +OP4 E0294A 0 +OP4 E0294B 0 +OP4 E0294C 0 +OP4 E0294D 0 +OP4 E0294E 0 +OP4 E0294F 0 +OP4 E02950 0 +OP4 E02951 0 +OP4 E02952 0 +OP4 E02953 0 +OP4 E02954 0 +OP4 E02955 0 +OP4 E02956 0 +OP4 E02957 0 +OP4 E02958 0 +OP4 E02959 0 +OP4 E0295A 0 +OP4 E0295B 0 +OP4 E0295C 0 +OP4 E0295D 0 +OP4 E0295E 0 +OP4 E0295F 0 +OP4 E02960 0 +OP4 E02961 0 +OP4 E02962 0 +OP4 E02963 0 +OP4 E02964 0 +OP4 E02965 0 +OP4 E02966 0 +OP4 E02967 0 +OP4 E02968 0 +OP4 E02969 0 +OP4 E0296A 0 +OP4 E0296B 0 +OP4 E0296C 0 +OP4 E0296D 0 +OP4 E0296E 0 +OP4 E0296F 0 +OP4 E02970 0 +OP4 E02971 0 +OP4 E02972 0 +OP4 E02973 0 +OP4 E02974 0 +OP4 E02975 0 +OP4 E02976 0 +OP4 E02977 0 +OP4 E02978 0 +OP4 E02979 0 +OP4 E0297A 0 +OP4 E0297B 0 +OP4 E0297C 0 +OP4 E0297D 0 +OP4 E0297E 0 +OP4 E0297F 0 +OP4 E02980 0 +OP4 E02981 0 +OP4 E02982 0 +OP4 E02983 0 +OP4 E02984 0 +OP4 E02985 0 +OP4 E02986 0 +OP4 E02987 0 +OP4 E02988 0 +OP4 E02989 0 +OP4 E0298A 0 +OP4 E0298B 0 +OP4 E0298C 0 +OP4 E0298D 0 +OP4 E0298E 0 +OP4 E0298F 0 +OP4 E02990 0 +OP4 E02991 0 +OP4 E02992 0 +OP4 E02993 0 +OP4 E02994 0 +OP4 E02995 0 +OP4 E02996 0 +OP4 E02997 0 +OP4 E02998 0 +OP4 E02999 0 +OP4 E0299A 0 +OP4 E0299B 0 +OP4 E0299C 0 +OP4 E0299D 0 +OP4 E0299E 0 +OP4 E0299F 0 +OP4 E029A0 0 +OP4 E029A1 0 +OP4 E029A2 0 +OP4 E029A3 0 +OP4 E029A4 0 +OP4 E029A5 0 +OP4 E029A6 0 +OP4 E029A7 0 +OP4 E029A8 0 +OP4 E029A9 0 +OP4 E029AA 0 +OP4 E029AB 0 +OP4 E029AC 0 +OP4 E029AD 0 +OP4 E029AE 0 +OP4 E029AF 0 +OP4 E029B0 0 +OP4 E029B1 0 +OP4 E029B2 0 +OP4 E029B3 0 +OP4 E029B4 0 +OP4 E029B5 0 +OP4 E029B6 0 +OP4 E029B7 0 +OP4 E029B8 0 +OP4 E029B9 0 +OP4 E029BA 0 +OP4 E029BB 0 +OP4 E029BC 0 +OP4 E029BD 0 +OP4 E029BE 0 +OP4 E029BF 0 +OP4 E029C0 0 +OP4 E029C1 0 +OP4 E029C2 0 +OP4 E029C3 0 +OP4 E029C4 0 +OP4 E029C5 0 +OP4 E029C6 0 +OP4 E029C7 0 +OP4 E029C8 0 +OP4 E029C9 0 +OP4 E029CA 0 +OP4 E029CB 0 +OP4 E029CC 0 +OP4 E029CD 0 +OP4 E029CE 0 +OP4 E029CF 0 +OP4 E029D0 0 +OP4 E029D1 0 +OP4 E029D2 0 +OP4 E029D3 0 +OP4 E029D4 0 +OP4 E029D5 0 +OP4 E029D6 0 +OP4 E029D7 0 +OP4 E029D8 0 +OP4 E029D9 0 +OP4 E029DA 0 +OP4 E029DB 0 +OP4 E029DC 0 +OP4 E029DD 0 +OP4 E029DE 0 +OP4 E029DF 0 +OP4 E029E0 0 +OP4 E029E1 0 +OP4 E029E2 0 +OP4 E029E3 0 +OP4 E029E4 0 +OP4 E029E5 0 +OP4 E029E6 0 +OP4 E029E7 0 +OP4 E029E8 0 +OP4 E029E9 0 +OP4 E029EA 0 +OP4 E029EB 0 +OP4 E029EC 0 +OP4 E029ED 0 +OP4 E029EE 0 +OP4 E029EF 0 +OP4 E029F0 0 +OP4 E029F1 0 +OP4 E029F2 0 +OP4 E029F3 0 +OP4 E029F4 0 +OP4 E029F5 0 +OP4 E029F6 0 +OP4 E029F7 0 +OP4 E029F8 0 +OP4 E029F9 0 +OP4 E029FA 0 +OP4 E029FB 0 +OP4 E029FC 0 +OP4 E029FD 0 +OP4 E029FE 0 +OP4 E029FF 0 +OP4 E02A00 0 +OP4 E02A01 0 +OP4 E02A02 0 +OP4 E02A03 0 +OP4 E02A04 0 +OP4 E02A05 0 +OP4 E02A06 0 +OP4 E02A07 0 +OP4 E02A08 0 +OP4 E02A09 0 +OP4 E02A0A 0 +OP4 E02A0B 0 +OP4 E02A0C 0 +OP4 E02A0D 0 +OP4 E02A0E 0 +OP4 E02A0F 0 +OP4 E02A10 0 +OP4 E02A11 0 +OP4 E02A12 0 +OP4 E02A13 0 +OP4 E02A14 0 +OP4 E02A15 0 +OP4 E02A16 0 +OP4 E02A17 0 +OP4 E02A18 0 +OP4 E02A19 0 +OP4 E02A1A 0 +OP4 E02A1B 0 +OP4 E02A1C 0 +OP4 E02A1D 0 +OP4 E02A1E 0 +OP4 E02A1F 0 +OP4 E02A20 0 +OP4 E02A21 0 +OP4 E02A22 0 +OP4 E02A23 0 +OP4 E02A24 0 +OP4 E02A25 0 +OP4 E02A26 0 +OP4 E02A27 0 +OP4 E02A28 0 +OP4 E02A29 0 +OP4 E02A2A 0 +OP4 E02A2B 0 +OP4 E02A2C 0 +OP4 E02A2D 0 +OP4 E02A2E 0 +OP4 E02A2F 0 +OP4 E02A30 0 +OP4 E02A31 0 +OP4 E02A32 0 +OP4 E02A33 0 +OP4 E02A34 0 +OP4 E02A35 0 +OP4 E02A36 0 +OP4 E02A37 0 +OP4 E02A38 0 +OP4 E02A39 0 +OP4 E02A3A 0 +OP4 E02A3B 0 +OP4 E02A3C 0 +OP4 E02A3D 0 +OP4 E02A3E 0 +OP4 E02A3F 0 +OP4 E02A40 0 +OP4 E02A41 0 +OP4 E02A42 0 +OP4 E02A43 0 +OP4 E02A44 0 +OP4 E02A45 0 +OP4 E02A46 0 +OP4 E02A47 0 +OP4 E02A48 0 +OP4 E02A49 0 +OP4 E02A4A 0 +OP4 E02A4B 0 +OP4 E02A4C 0 +OP4 E02A4D 0 +OP4 E02A4E 0 +OP4 E02A4F 0 +OP4 E02A50 0 +OP4 E02A51 0 +OP4 E02A52 0 +OP4 E02A53 0 +OP4 E02A54 0 +OP4 E02A55 0 +OP4 E02A56 0 +OP4 E02A57 0 +OP4 E02A58 0 +OP4 E02A59 0 +OP4 E02A5A 0 +OP4 E02A5B 0 +OP4 E02A5C 0 +OP4 E02A5D 0 +OP4 E02A5E 0 +OP4 E02A5F 0 +OP4 E02A60 0 +OP4 E02A61 0 +OP4 E02A62 0 +OP4 E02A63 0 +OP4 E02A64 0 +OP4 E02A65 0 +OP4 E02A66 0 +OP4 E02A67 0 +OP4 E02A68 0 +OP4 E02A69 0 +OP4 E02A6A 0 +OP4 E02A6B 0 +OP4 E02A6C 0 +OP4 E02A6D 0 +OP4 E02A6E 0 +OP4 E02A6F 0 +OP4 E02A70 0 +OP4 E02A71 0 +OP4 E02A72 0 +OP4 E02A73 0 +OP4 E02A74 0 +OP4 E02A75 0 +OP4 E02A76 0 +OP4 E02A77 0 +OP4 E02A78 0 +OP4 E02A79 0 +OP4 E02A7A 0 +OP4 E02A7B 0 +OP4 E02A7C 0 +OP4 E02A7D 0 +OP4 E02A7E 0 +OP4 E02A7F 0 +OP4 E02A80 0 +OP4 E02A81 0 +OP4 E02A82 0 +OP4 E02A83 0 +OP4 E02A84 0 +OP4 E02A85 0 +OP4 E02A86 0 +OP4 E02A87 0 +OP4 E02A88 0 +OP4 E02A89 0 +OP4 E02A8A 0 +OP4 E02A8B 0 +OP4 E02A8C 0 +OP4 E02A8D 0 +OP4 E02A8E 0 +OP4 E02A8F 0 +OP4 E02A90 0 +OP4 E02A91 0 +OP4 E02A92 0 +OP4 E02A93 0 +OP4 E02A94 0 +OP4 E02A95 0 +OP4 E02A96 0 +OP4 E02A97 0 +OP4 E02A98 0 +OP4 E02A99 0 +OP4 E02A9A 0 +OP4 E02A9B 0 +OP4 E02A9C 0 +OP4 E02A9D 0 +OP4 E02A9E 0 +OP4 E02A9F 0 +OP4 E02AA0 0 +OP4 E02AA1 0 +OP4 E02AA2 0 +OP4 E02AA3 0 +OP4 E02AA4 0 +OP4 E02AA5 0 +OP4 E02AA6 0 +OP4 E02AA7 0 +OP4 E02AA8 0 +OP4 E02AA9 0 +OP4 E02AAA 0 +OP4 E02AAB 0 +OP4 E02AAC 0 +OP4 E02AAD 0 +OP4 E02AAE 0 +OP4 E02AAF 0 +OP4 E02AB0 0 +OP4 E02AB1 0 +OP4 E02AB2 0 +OP4 E02AB3 0 +OP4 E02AB4 0 +OP4 E02AB5 0 +OP4 E02AB6 0 +OP4 E02AB7 0 +OP4 E02AB8 0 +OP4 E02AB9 0 +OP4 E02ABA 0 +OP4 E02ABB 0 +OP4 E02ABC 0 +OP4 E02ABD 0 +OP4 E02ABE 0 +OP4 E02ABF 0 +OP4 E02AC0 0 +OP4 E02AC1 0 +OP4 E02AC2 0 +OP4 E02AC3 0 +OP4 E02AC4 0 +OP4 E02AC5 0 +OP4 E02AC6 0 +OP4 E02AC7 0 +OP4 E02AC8 0 +OP4 E02AC9 0 +OP4 E02ACA 0 +OP4 E02ACB 0 +OP4 E02ACC 0 +OP4 E02ACD 0 +OP4 E02ACE 0 +OP4 E02ACF 0 +OP4 E02AD0 0 +OP4 E02AD1 0 +OP4 E02AD2 0 +OP4 E02AD3 0 +OP4 E02AD4 0 +OP4 E02AD5 0 +OP4 E02AD6 0 +OP4 E02AD7 0 +OP4 E02AD8 0 +OP4 E02AD9 0 +OP4 E02ADA 0 +OP4 E02ADB 0 +OP4 E02ADC 0 +OP4 E02ADD 0 +OP4 E02ADE 0 +OP4 E02ADF 0 +OP4 E02AE0 0 +OP4 E02AE1 0 +OP4 E02AE2 0 +OP4 E02AE3 0 +OP4 E02AE4 0 +OP4 E02AE5 0 +OP4 E02AE6 0 +OP4 E02AE7 0 +OP4 E02AE8 0 +OP4 E02AE9 0 +OP4 E02AEA 0 +OP4 E02AEB 0 +OP4 E02AEC 0 +OP4 E02AED 0 +OP4 E02AEE 0 +OP4 E02AEF 0 +OP4 E02AF0 0 +OP4 E02AF1 0 +OP4 E02AF2 0 +OP4 E02AF3 0 +OP4 E02AF4 0 +OP4 E02AF5 0 +OP4 E02AF6 0 +OP4 E02AF7 0 +OP4 E02AF8 0 +OP4 E02AF9 0 +OP4 E02AFA 0 +OP4 E02AFB 0 +OP4 E02AFC 0 +OP4 E02AFD 0 +OP4 E02AFE 0 +OP4 E02AFF 0 +OP4 E02B00 0 +OP4 E02B01 0 +OP4 E02B02 0 +OP4 E02B03 0 +OP4 E02B04 0 +OP4 E02B05 0 +OP4 E02B06 0 +OP4 E02B07 0 +OP4 E02B08 0 +OP4 E02B09 0 +OP4 E02B0A 0 +OP4 E02B0B 0 +OP4 E02B0C 0 +OP4 E02B0D 0 +OP4 E02B0E 0 +OP4 E02B0F 0 +OP4 E02B10 0 +OP4 E02B11 0 +OP4 E02B12 0 +OP4 E02B13 0 +OP4 E02B14 0 +OP4 E02B15 0 +OP4 E02B16 0 +OP4 E02B17 0 +OP4 E02B18 0 +OP4 E02B19 0 +OP4 E02B1A 0 +OP4 E02B1B 0 +OP4 E02B1C 0 +OP4 E02B1D 0 +OP4 E02B1E 0 +OP4 E02B1F 0 +OP4 E02B20 0 +OP4 E02B21 0 +OP4 E02B22 0 +OP4 E02B23 0 +OP4 E02B24 0 +OP4 E02B25 0 +OP4 E02B26 0 +OP4 E02B27 0 +OP4 E02B28 0 +OP4 E02B29 0 +OP4 E02B2A 0 +OP4 E02B2B 0 +OP4 E02B2C 0 +OP4 E02B2D 0 +OP4 E02B2E 0 +OP4 E02B2F 0 +OP4 E02B30 0 +OP4 E02B31 0 +OP4 E02B32 0 +OP4 E02B33 0 +OP4 E02B34 0 +OP4 E02B35 0 +OP4 E02B36 0 +OP4 E02B37 0 +OP4 E02B38 0 +OP4 E02B39 0 +OP4 E02B3A 0 +OP4 E02B3B 0 +OP4 E02B3C 0 +OP4 E02B3D 0 +OP4 E02B3E 0 +OP4 E02B3F 0 +OP4 E02B40 0 +OP4 E02B41 0 +OP4 E02B42 0 +OP4 E02B43 0 +OP4 E02B44 0 +OP4 E02B45 0 +OP4 E02B46 0 +OP4 E02B47 0 +OP4 E02B48 0 +OP4 E02B49 0 +OP4 E02B4A 0 +OP4 E02B4B 0 +OP4 E02B4C 0 +OP4 E02B4D 0 +OP4 E02B4E 0 +OP4 E02B4F 0 +OP4 E02B50 0 +OP4 E02B51 0 +OP4 E02B52 0 +OP4 E02B53 0 +OP4 E02B54 0 +OP4 E02B55 0 +OP4 E02B56 0 +OP4 E02B57 0 +OP4 E02B58 0 +OP4 E02B59 0 +OP4 E02B5A 0 +OP4 E02B5B 0 +OP4 E02B5C 0 +OP4 E02B5D 0 +OP4 E02B5E 0 +OP4 E02B5F 0 +OP4 E02B60 0 +OP4 E02B61 0 +OP4 E02B62 0 +OP4 E02B63 0 +OP4 E02B64 0 +OP4 E02B65 0 +OP4 E02B66 0 +OP4 E02B67 0 +OP4 E02B68 0 +OP4 E02B69 0 +OP4 E02B6A 0 +OP4 E02B6B 0 +OP4 E02B6C 0 +OP4 E02B6D 0 +OP4 E02B6E 0 +OP4 E02B6F 0 +OP4 E02B70 0 +OP4 E02B71 0 +OP4 E02B72 0 +OP4 E02B73 0 +OP4 E02B74 0 +OP4 E02B75 0 +OP4 E02B76 0 +OP4 E02B77 0 +OP4 E02B78 0 +OP4 E02B79 0 +OP4 E02B7A 0 +OP4 E02B7B 0 +OP4 E02B7C 0 +OP4 E02B7D 0 +OP4 E02B7E 0 +OP4 E02B7F 0 +OP4 E02B80 0 +OP4 E02B81 0 +OP4 E02B82 0 +OP4 E02B83 0 +OP4 E02B84 0 +OP4 E02B85 0 +OP4 E02B86 0 +OP4 E02B87 0 +OP4 E02B88 0 +OP4 E02B89 0 +OP4 E02B8A 0 +OP4 E02B8B 0 +OP4 E02B8C 0 +OP4 E02B8D 0 +OP4 E02B8E 0 +OP4 E02B8F 0 +OP4 E02B90 0 +OP4 E02B91 0 +OP4 E02B92 0 +OP4 E02B93 0 +OP4 E02B94 0 +OP4 E02B95 0 +OP4 E02B96 0 +OP4 E02B97 0 +OP4 E02B98 0 +OP4 E02B99 0 +OP4 E02B9A 0 +OP4 E02B9B 0 +OP4 E02B9C 0 +OP4 E02B9D 0 +OP4 E02B9E 0 +OP4 E02B9F 0 +OP4 E02BA0 0 +OP4 E02BA1 0 +OP4 E02BA2 0 +OP4 E02BA3 0 +OP4 E02BA4 0 +OP4 E02BA5 0 +OP4 E02BA6 0 +OP4 E02BA7 0 +OP4 E02BA8 0 +OP4 E02BA9 0 +OP4 E02BAA 0 +OP4 E02BAB 0 +OP4 E02BAC 0 +OP4 E02BAD 0 +OP4 E02BAE 0 +OP4 E02BAF 0 +OP4 E02BB0 0 +OP4 E02BB1 0 +OP4 E02BB2 0 +OP4 E02BB3 0 +OP4 E02BB4 0 +OP4 E02BB5 0 +OP4 E02BB6 0 +OP4 E02BB7 0 +OP4 E02BB8 0 +OP4 E02BB9 0 +OP4 E02BBA 0 +OP4 E02BBB 0 +OP4 E02BBC 0 +OP4 E02BBD 0 +OP4 E02BBE 0 +OP4 E02BBF 0 +OP4 E02BC0 0 +OP4 E02BC1 0 +OP4 E02BC2 0 +OP4 E02BC3 0 +OP4 E02BC4 0 +OP4 E02BC5 0 +OP4 E02BC6 0 +OP4 E02BC7 0 +OP4 E02BC8 0 +OP4 E02BC9 0 +OP4 E02BCA 0 +OP4 E02BCB 0 +OP4 E02BCC 0 +OP4 E02BCD 0 +OP4 E02BCE 0 +OP4 E02BCF 0 +OP4 E02BD0 0 +OP4 E02BD1 0 +OP4 E02BD2 0 +OP4 E02BD3 0 +OP4 E02BD4 0 +OP4 E02BD5 0 +OP4 E02BD6 0 +OP4 E02BD7 0 +OP4 E02BD8 0 +OP4 E02BD9 0 +OP4 E02BDA 0 +OP4 E02BDB 0 +OP4 E02BDC 0 +OP4 E02BDD 0 +OP4 E02BDE 0 +OP4 E02BDF 0 +OP4 E02BE0 0 +OP4 E02BE1 0 +OP4 E02BE2 0 +OP4 E02BE3 0 +OP4 E02BE4 0 +OP4 E02BE5 0 +OP4 E02BE6 0 +OP4 E02BE7 0 +OP4 E02BE8 0 +OP4 E02BE9 0 +OP4 E02BEA 0 +OP4 E02BEB 0 +OP4 E02BEC 0 +OP4 E02BED 0 +OP4 E02BEE 0 +OP4 E02BEF 0 +OP4 E02BF0 0 +OP4 E02BF1 0 +OP4 E02BF2 0 +OP4 E02BF3 0 +OP4 E02BF4 0 +OP4 E02BF5 0 +OP4 E02BF6 0 +OP4 E02BF7 0 +OP4 E02BF8 0 +OP4 E02BF9 0 +OP4 E02BFA 0 +OP4 E02BFB 0 +OP4 E02BFC 0 +OP4 E02BFD 0 +OP4 E02BFE 0 +OP4 E02BFF 0 +OP4 E02C00 0 +OP4 E02C01 0 +OP4 E02C02 0 +OP4 E02C03 0 +OP4 E02C04 0 +OP4 E02C05 0 +OP4 E02C06 0 +OP4 E02C07 0 +OP4 E02C08 0 +OP4 E02C09 0 +OP4 E02C0A 0 +OP4 E02C0B 0 +OP4 E02C0C 0 +OP4 E02C0D 0 +OP4 E02C0E 0 +OP4 E02C0F 0 +OP4 E02C10 0 +OP4 E02C11 0 +OP4 E02C12 0 +OP4 E02C13 0 +OP4 E02C14 0 +OP4 E02C15 0 +OP4 E02C16 0 +OP4 E02C17 0 +OP4 E02C18 0 +OP4 E02C19 0 +OP4 E02C1A 0 +OP4 E02C1B 0 +OP4 E02C1C 0 +OP4 E02C1D 0 +OP4 E02C1E 0 +OP4 E02C1F 0 +OP4 E02C20 0 +OP4 E02C21 0 +OP4 E02C22 0 +OP4 E02C23 0 +OP4 E02C24 0 +OP4 E02C25 0 +OP4 E02C26 0 +OP4 E02C27 0 +OP4 E02C28 0 +OP4 E02C29 0 +OP4 E02C2A 0 +OP4 E02C2B 0 +OP4 E02C2C 0 +OP4 E02C2D 0 +OP4 E02C2E 0 +OP4 E02C2F 0 +OP4 E02C30 0 +OP4 E02C31 0 +OP4 E02C32 0 +OP4 E02C33 0 +OP4 E02C34 0 +OP4 E02C35 0 +OP4 E02C36 0 +OP4 E02C37 0 +OP4 E02C38 0 +OP4 E02C39 0 +OP4 E02C3A 0 +OP4 E02C3B 0 +OP4 E02C3C 0 +OP4 E02C3D 0 +OP4 E02C3E 0 +OP4 E02C3F 0 +OP4 E02C40 0 +OP4 E02C41 0 +OP4 E02C42 0 +OP4 E02C43 0 +OP4 E02C44 0 +OP4 E02C45 0 +OP4 E02C46 0 +OP4 E02C47 0 +OP4 E02C48 0 +OP4 E02C49 0 +OP4 E02C4A 0 +OP4 E02C4B 0 +OP4 E02C4C 0 +OP4 E02C4D 0 +OP4 E02C4E 0 +OP4 E02C4F 0 +OP4 E02C50 0 +OP4 E02C51 0 +OP4 E02C52 0 +OP4 E02C53 0 +OP4 E02C54 0 +OP4 E02C55 0 +OP4 E02C56 0 +OP4 E02C57 0 +OP4 E02C58 0 +OP4 E02C59 0 +OP4 E02C5A 0 +OP4 E02C5B 0 +OP4 E02C5C 0 +OP4 E02C5D 0 +OP4 E02C5E 0 +OP4 E02C5F 0 +OP4 E02C60 0 +OP4 E02C61 0 +OP4 E02C62 0 +OP4 E02C63 0 +OP4 E02C64 0 +OP4 E02C65 0 +OP4 E02C66 0 +OP4 E02C67 0 +OP4 E02C68 0 +OP4 E02C69 0 +OP4 E02C6A 0 +OP4 E02C6B 0 +OP4 E02C6C 0 +OP4 E02C6D 0 +OP4 E02C6E 0 +OP4 E02C6F 0 +OP4 E02C70 0 +OP4 E02C71 0 +OP4 E02C72 0 +OP4 E02C73 0 +OP4 E02C74 0 +OP4 E02C75 0 +OP4 E02C76 0 +OP4 E02C77 0 +OP4 E02C78 0 +OP4 E02C79 0 +OP4 E02C7A 0 +OP4 E02C7B 0 +OP4 E02C7C 0 +OP4 E02C7D 0 +OP4 E02C7E 0 +OP4 E02C7F 0 +OP4 E02C80 0 +OP4 E02C81 0 +OP4 E02C82 0 +OP4 E02C83 0 +OP4 E02C84 0 +OP4 E02C85 0 +OP4 E02C86 0 +OP4 E02C87 0 +OP4 E02C88 0 +OP4 E02C89 0 +OP4 E02C8A 0 +OP4 E02C8B 0 +OP4 E02C8C 0 +OP4 E02C8D 0 +OP4 E02C8E 0 +OP4 E02C8F 0 +OP4 E02C90 0 +OP4 E02C91 0 +OP4 E02C92 0 +OP4 E02C93 0 +OP4 E02C94 0 +OP4 E02C95 0 +OP4 E02C96 0 +OP4 E02C97 0 +OP4 E02C98 0 +OP4 E02C99 0 +OP4 E02C9A 0 +OP4 E02C9B 0 +OP4 E02C9C 0 +OP4 E02C9D 0 +OP4 E02C9E 0 +OP4 E02C9F 0 +OP4 E02CA0 0 +OP4 E02CA1 0 +OP4 E02CA2 0 +OP4 E02CA3 0 +OP4 E02CA4 0 +OP4 E02CA5 0 +OP4 E02CA6 0 +OP4 E02CA7 0 +OP4 E02CA8 0 +OP4 E02CA9 0 +OP4 E02CAA 0 +OP4 E02CAB 0 +OP4 E02CAC 0 +OP4 E02CAD 0 +OP4 E02CAE 0 +OP4 E02CAF 0 +OP4 E02CB0 0 +OP4 E02CB1 0 +OP4 E02CB2 0 +OP4 E02CB3 0 +OP4 E02CB4 0 +OP4 E02CB5 0 +OP4 E02CB6 0 +OP4 E02CB7 0 +OP4 E02CB8 0 +OP4 E02CB9 0 +OP4 E02CBA 0 +OP4 E02CBB 0 +OP4 E02CBC 0 +OP4 E02CBD 0 +OP4 E02CBE 0 +OP4 E02CBF 0 +OP4 E02CC0 0 +OP4 E02CC1 0 +OP4 E02CC2 0 +OP4 E02CC3 0 +OP4 E02CC4 0 +OP4 E02CC5 0 +OP4 E02CC6 0 +OP4 E02CC7 0 +OP4 E02CC8 0 +OP4 E02CC9 0 +OP4 E02CCA 0 +OP4 E02CCB 0 +OP4 E02CCC 0 +OP4 E02CCD 0 +OP4 E02CCE 0 +OP4 E02CCF 0 +OP4 E02CD0 0 +OP4 E02CD1 0 +OP4 E02CD2 0 +OP4 E02CD3 0 +OP4 E02CD4 0 +OP4 E02CD5 0 +OP4 E02CD6 0 +OP4 E02CD7 0 +OP4 E02CD8 0 +OP4 E02CD9 0 +OP4 E02CDA 0 +OP4 E02CDB 0 +OP4 E02CDC 0 +OP4 E02CDD 0 +OP4 E02CDE 0 +OP4 E02CDF 0 +OP4 E02CE0 0 +OP4 E02CE1 0 +OP4 E02CE2 0 +OP4 E02CE3 0 +OP4 E02CE4 0 +OP4 E02CE5 0 +OP4 E02CE6 0 +OP4 E02CE7 0 +OP4 E02CE8 0 +OP4 E02CE9 0 +OP4 E02CEA 0 +OP4 E02CEB 0 +OP4 E02CEC 0 +OP4 E02CED 0 +OP4 E02CEE 0 +OP4 E02CEF 0 +OP4 E02CF0 0 +OP4 E02CF1 0 +OP4 E02CF2 0 +OP4 E02CF3 0 +OP4 E02CF4 0 +OP4 E02CF5 0 +OP4 E02CF6 0 +OP4 E02CF7 0 +OP4 E02CF8 0 +OP4 E02CF9 0 +OP4 E02CFA 0 +OP4 E02CFB 0 +OP4 E02CFC 0 +OP4 E02CFD 0 +OP4 E02CFE 0 +OP4 E02CFF 0 +OP4 E02D00 0 +OP4 E02D01 0 +OP4 E02D02 0 +OP4 E02D03 0 +OP4 E02D04 0 +OP4 E02D05 0 +OP4 E02D06 0 +OP4 E02D07 0 +OP4 E02D08 0 +OP4 E02D09 0 +OP4 E02D0A 0 +OP4 E02D0B 0 +OP4 E02D0C 0 +OP4 E02D0D 0 +OP4 E02D0E 0 +OP4 E02D0F 0 +OP4 E02D10 0 +OP4 E02D11 0 +OP4 E02D12 0 +OP4 E02D13 0 +OP4 E02D14 0 +OP4 E02D15 0 +OP4 E02D16 0 +OP4 E02D17 0 +OP4 E02D18 0 +OP4 E02D19 0 +OP4 E02D1A 0 +OP4 E02D1B 0 +OP4 E02D1C 0 +OP4 E02D1D 0 +OP4 E02D1E 0 +OP4 E02D1F 0 +OP4 E02D20 0 +OP4 E02D21 0 +OP4 E02D22 0 +OP4 E02D23 0 +OP4 E02D24 0 +OP4 E02D25 0 +OP4 E02D26 0 +OP4 E02D27 0 +OP4 E02D28 0 +OP4 E02D29 0 +OP4 E02D2A 0 +OP4 E02D2B 0 +OP4 E02D2C 0 +OP4 E02D2D 0 +OP4 E02D2E 0 +OP4 E02D2F 0 +OP4 E02D30 0 +OP4 E02D31 0 +OP4 E02D32 0 +OP4 E02D33 0 +OP4 E02D34 0 +OP4 E02D35 0 +OP4 E02D36 0 +OP4 E02D37 0 +OP4 E02D38 0 +OP4 E02D39 0 +OP4 E02D3A 0 +OP4 E02D3B 0 +OP4 E02D3C 0 +OP4 E02D3D 0 +OP4 E02D3E 0 +OP4 E02D3F 0 +OP4 E02D40 0 +OP4 E02D41 0 +OP4 E02D42 0 +OP4 E02D43 0 +OP4 E02D44 0 +OP4 E02D45 0 +OP4 E02D46 0 +OP4 E02D47 0 +OP4 E02D48 0 +OP4 E02D49 0 +OP4 E02D4A 0 +OP4 E02D4B 0 +OP4 E02D4C 0 +OP4 E02D4D 0 +OP4 E02D4E 0 +OP4 E02D4F 0 +OP4 E02D50 0 +OP4 E02D51 0 +OP4 E02D52 0 +OP4 E02D53 0 +OP4 E02D54 0 +OP4 E02D55 0 +OP4 E02D56 0 +OP4 E02D57 0 +OP4 E02D58 0 +OP4 E02D59 0 +OP4 E02D5A 0 +OP4 E02D5B 0 +OP4 E02D5C 0 +OP4 E02D5D 0 +OP4 E02D5E 0 +OP4 E02D5F 0 +OP4 E02D60 0 +OP4 E02D61 0 +OP4 E02D62 0 +OP4 E02D63 0 +OP4 E02D64 0 +OP4 E02D65 0 +OP4 E02D66 0 +OP4 E02D67 0 +OP4 E02D68 0 +OP4 E02D69 0 +OP4 E02D6A 0 +OP4 E02D6B 0 +OP4 E02D6C 0 +OP4 E02D6D 0 +OP4 E02D6E 0 +OP4 E02D6F 0 +OP4 E02D70 0 +OP4 E02D71 0 +OP4 E02D72 0 +OP4 E02D73 0 +OP4 E02D74 0 +OP4 E02D75 0 +OP4 E02D76 0 +OP4 E02D77 0 +OP4 E02D78 0 +OP4 E02D79 0 +OP4 E02D7A 0 +OP4 E02D7B 0 +OP4 E02D7C 0 +OP4 E02D7D 0 +OP4 E02D7E 0 +OP4 E02D7F 0 +OP4 E02D80 0 +OP4 E02D81 0 +OP4 E02D82 0 +OP4 E02D83 0 +OP4 E02D84 0 +OP4 E02D85 0 +OP4 E02D86 0 +OP4 E02D87 0 +OP4 E02D88 0 +OP4 E02D89 0 +OP4 E02D8A 0 +OP4 E02D8B 0 +OP4 E02D8C 0 +OP4 E02D8D 0 +OP4 E02D8E 0 +OP4 E02D8F 0 +OP4 E02D90 0 +OP4 E02D91 0 +OP4 E02D92 0 +OP4 E02D93 0 +OP4 E02D94 0 +OP4 E02D95 0 +OP4 E02D96 0 +OP4 E02D97 0 +OP4 E02D98 0 +OP4 E02D99 0 +OP4 E02D9A 0 +OP4 E02D9B 0 +OP4 E02D9C 0 +OP4 E02D9D 0 +OP4 E02D9E 0 +OP4 E02D9F 0 +OP4 E02DA0 0 +OP4 E02DA1 0 +OP4 E02DA2 0 +OP4 E02DA3 0 +OP4 E02DA4 0 +OP4 E02DA5 0 +OP4 E02DA6 0 +OP4 E02DA7 0 +OP4 E02DA8 0 +OP4 E02DA9 0 +OP4 E02DAA 0 +OP4 E02DAB 0 +OP4 E02DAC 0 +OP4 E02DAD 0 +OP4 E02DAE 0 +OP4 E02DAF 0 +OP4 E02DB0 0 +OP4 E02DB1 0 +OP4 E02DB2 0 +OP4 E02DB3 0 +OP4 E02DB4 0 +OP4 E02DB5 0 +OP4 E02DB6 0 +OP4 E02DB7 0 +OP4 E02DB8 0 +OP4 E02DB9 0 +OP4 E02DBA 0 +OP4 E02DBB 0 +OP4 E02DBC 0 +OP4 E02DBD 0 +OP4 E02DBE 0 +OP4 E02DBF 0 +OP4 E02DC0 0 +OP4 E02DC1 0 +OP4 E02DC2 0 +OP4 E02DC3 0 +OP4 E02DC4 0 +OP4 E02DC5 0 +OP4 E02DC6 0 +OP4 E02DC7 0 +OP4 E02DC8 0 +OP4 E02DC9 0 +OP4 E02DCA 0 +OP4 E02DCB 0 +OP4 E02DCC 0 +OP4 E02DCD 0 +OP4 E02DCE 0 +OP4 E02DCF 0 +OP4 E02DD0 0 +OP4 E02DD1 0 +OP4 E02DD2 0 +OP4 E02DD3 0 +OP4 E02DD4 0 +OP4 E02DD5 0 +OP4 E02DD6 0 +OP4 E02DD7 0 +OP4 E02DD8 0 +OP4 E02DD9 0 +OP4 E02DDA 0 +OP4 E02DDB 0 +OP4 E02DDC 0 +OP4 E02DDD 0 +OP4 E02DDE 0 +OP4 E02DDF 0 +OP4 E02DE0 0 +OP4 E02DE1 0 +OP4 E02DE2 0 +OP4 E02DE3 0 +OP4 E02DE4 0 +OP4 E02DE5 0 +OP4 E02DE6 0 +OP4 E02DE7 0 +OP4 E02DE8 0 +OP4 E02DE9 0 +OP4 E02DEA 0 +OP4 E02DEB 0 +OP4 E02DEC 0 +OP4 E02DED 0 +OP4 E02DEE 0 +OP4 E02DEF 0 +OP4 E02DF0 0 +OP4 E02DF1 0 +OP4 E02DF2 0 +OP4 E02DF3 0 +OP4 E02DF4 0 +OP4 E02DF5 0 +OP4 E02DF6 0 +OP4 E02DF7 0 +OP4 E02DF8 0 +OP4 E02DF9 0 +OP4 E02DFA 0 +OP4 E02DFB 0 +OP4 E02DFC 0 +OP4 E02DFD 0 +OP4 E02DFE 0 +OP4 E02DFF 0 +OP4 E02E00 0 +OP4 E02E01 0 +OP4 E02E02 0 +OP4 E02E03 0 +OP4 E02E04 0 +OP4 E02E05 0 +OP4 E02E06 0 +OP4 E02E07 0 +OP4 E02E08 0 +OP4 E02E09 0 +OP4 E02E0A 0 +OP4 E02E0B 0 +OP4 E02E0C 0 +OP4 E02E0D 0 +OP4 E02E0E 0 +OP4 E02E0F 0 +OP4 E02E10 0 +OP4 E02E11 0 +OP4 E02E12 0 +OP4 E02E13 0 +OP4 E02E14 0 +OP4 E02E15 0 +OP4 E02E16 0 +OP4 E02E17 0 +OP4 E02E18 0 +OP4 E02E19 0 +OP4 E02E1A 0 +OP4 E02E1B 0 +OP4 E02E1C 0 +OP4 E02E1D 0 +OP4 E02E1E 0 +OP4 E02E1F 0 +OP4 E02E20 0 +OP4 E02E21 0 +OP4 E02E22 0 +OP4 E02E23 0 +OP4 E02E24 0 +OP4 E02E25 0 +OP4 E02E26 0 +OP4 E02E27 0 +OP4 E02E28 0 +OP4 E02E29 0 +OP4 E02E2A 0 +OP4 E02E2B 0 +OP4 E02E2C 0 +OP4 E02E2D 0 +OP4 E02E2E 0 +OP4 E02E2F 0 +OP4 E02E30 0 +OP4 E02E31 0 +OP4 E02E32 0 +OP4 E02E33 0 +OP4 E02E34 0 +OP4 E02E35 0 +OP4 E02E36 0 +OP4 E02E37 0 +OP4 E02E38 0 +OP4 E02E39 0 +OP4 E02E3A 0 +OP4 E02E3B 0 +OP4 E02E3C 0 +OP4 E02E3D 0 +OP4 E02E3E 0 +OP4 E02E3F 0 +OP4 E02E40 0 +OP4 E02E41 0 +OP4 E02E42 0 +OP4 E02E43 0 +OP4 E02E44 0 +OP4 E02E45 0 +OP4 E02E46 0 +OP4 E02E47 0 +OP4 E02E48 0 +OP4 E02E49 0 +OP4 E02E4A 0 +OP4 E02E4B 0 +OP4 E02E4C 0 +OP4 E02E4D 0 +OP4 E02E4E 0 +OP4 E02E4F 0 +OP4 E02E50 0 +OP4 E02E51 0 +OP4 E02E52 0 +OP4 E02E53 0 +OP4 E02E54 0 +OP4 E02E55 0 +OP4 E02E56 0 +OP4 E02E57 0 +OP4 E02E58 0 +OP4 E02E59 0 +OP4 E02E5A 0 +OP4 E02E5B 0 +OP4 E02E5C 0 +OP4 E02E5D 0 +OP4 E02E5E 0 +OP4 E02E5F 0 +OP4 E02E60 0 +OP4 E02E61 0 +OP4 E02E62 0 +OP4 E02E63 0 +OP4 E02E64 0 +OP4 E02E65 0 +OP4 E02E66 0 +OP4 E02E67 0 +OP4 E02E68 0 +OP4 E02E69 0 +OP4 E02E6A 0 +OP4 E02E6B 0 +OP4 E02E6C 0 +OP4 E02E6D 0 +OP4 E02E6E 0 +OP4 E02E6F 0 +OP4 E02E70 0 +OP4 E02E71 0 +OP4 E02E72 0 +OP4 E02E73 0 +OP4 E02E74 0 +OP4 E02E75 0 +OP4 E02E76 0 +OP4 E02E77 0 +OP4 E02E78 0 +OP4 E02E79 0 +OP4 E02E7A 0 +OP4 E02E7B 0 +OP4 E02E7C 0 +OP4 E02E7D 0 +OP4 E02E7E 0 +OP4 E02E7F 0 +OP4 E02E80 0 +OP4 E02E81 0 +OP4 E02E82 0 +OP4 E02E83 0 +OP4 E02E84 0 +OP4 E02E85 0 +OP4 E02E86 0 +OP4 E02E87 0 +OP4 E02E88 0 +OP4 E02E89 0 +OP4 E02E8A 0 +OP4 E02E8B 0 +OP4 E02E8C 0 +OP4 E02E8D 0 +OP4 E02E8E 0 +OP4 E02E8F 0 +OP4 E02E90 0 +OP4 E02E91 0 +OP4 E02E92 0 +OP4 E02E93 0 +OP4 E02E94 0 +OP4 E02E95 0 +OP4 E02E96 0 +OP4 E02E97 0 +OP4 E02E98 0 +OP4 E02E99 0 +OP4 E02E9A 0 +OP4 E02E9B 0 +OP4 E02E9C 0 +OP4 E02E9D 0 +OP4 E02E9E 0 +OP4 E02E9F 0 +OP4 E02EA0 0 +OP4 E02EA1 0 +OP4 E02EA2 0 +OP4 E02EA3 0 +OP4 E02EA4 0 +OP4 E02EA5 0 +OP4 E02EA6 0 +OP4 E02EA7 0 +OP4 E02EA8 0 +OP4 E02EA9 0 +OP4 E02EAA 0 +OP4 E02EAB 0 +OP4 E02EAC 0 +OP4 E02EAD 0 +OP4 E02EAE 0 +OP4 E02EAF 0 +OP4 E02EB0 0 +OP4 E02EB1 0 +OP4 E02EB2 0 +OP4 E02EB3 0 +OP4 E02EB4 0 +OP4 E02EB5 0 +OP4 E02EB6 0 +OP4 E02EB7 0 +OP4 E02EB8 0 +OP4 E02EB9 0 +OP4 E02EBA 0 +OP4 E02EBB 0 +OP4 E02EBC 0 +OP4 E02EBD 0 +OP4 E02EBE 0 +OP4 E02EBF 0 +OP4 E02EC0 0 +OP4 E02EC1 0 +OP4 E02EC2 0 +OP4 E02EC3 0 +OP4 E02EC4 0 +OP4 E02EC5 0 +OP4 E02EC6 0 +OP4 E02EC7 0 +OP4 E02EC8 0 +OP4 E02EC9 0 +OP4 E02ECA 0 +OP4 E02ECB 0 +OP4 E02ECC 0 +OP4 E02ECD 0 +OP4 E02ECE 0 +OP4 E02ECF 0 +OP4 E02ED0 0 +OP4 E02ED1 0 +OP4 E02ED2 0 +OP4 E02ED3 0 +OP4 E02ED4 0 +OP4 E02ED5 0 +OP4 E02ED6 0 +OP4 E02ED7 0 +OP4 E02ED8 0 +OP4 E02ED9 0 +OP4 E02EDA 0 +OP4 E02EDB 0 +OP4 E02EDC 0 +OP4 E02EDD 0 +OP4 E02EDE 0 +OP4 E02EDF 0 +OP4 E02EE0 0 +OP4 E02EE1 0 +OP4 E02EE2 0 +OP4 E02EE3 0 +OP4 E02EE4 0 +OP4 E02EE5 0 +OP4 E02EE6 0 +OP4 E02EE7 0 +OP4 E02EE8 0 +OP4 E02EE9 0 +OP4 E02EEA 0 +OP4 E02EEB 0 +OP4 E02EEC 0 +OP4 E02EED 0 +OP4 E02EEE 0 +OP4 E02EEF 0 +OP4 E02EF0 0 +OP4 E02EF1 0 +OP4 E02EF2 0 +OP4 E02EF3 0 +OP4 E02EF4 0 +OP4 E02EF5 0 +OP4 E02EF6 0 +OP4 E02EF7 0 +OP4 E02EF8 0 +OP4 E02EF9 0 +OP4 E02EFA 0 +OP4 E02EFB 0 +OP4 E02EFC 0 +OP4 E02EFD 0 +OP4 E02EFE 0 +OP4 E02EFF 0 +OP4 E02F00 0 +OP4 E02F01 0 +OP4 E02F02 0 +OP4 E02F03 0 +OP4 E02F04 0 +OP4 E02F05 0 +OP4 E02F06 0 +OP4 E02F07 0 +OP4 E02F08 0 +OP4 E02F09 0 +OP4 E02F0A 0 +OP4 E02F0B 0 +OP4 E02F0C 0 +OP4 E02F0D 0 +OP4 E02F0E 0 +OP4 E02F0F 0 +OP4 E02F10 0 +OP4 E02F11 0 +OP4 E02F12 0 +OP4 E02F13 0 +OP4 E02F14 0 +OP4 E02F15 0 +OP4 E02F16 0 +OP4 E02F17 0 +OP4 E02F18 0 +OP4 E02F19 0 +OP4 E02F1A 0 +OP4 E02F1B 0 +OP4 E02F1C 0 +OP4 E02F1D 0 +OP4 E02F1E 0 +OP4 E02F1F 0 +OP4 E02F20 0 +OP4 E02F21 0 +OP4 E02F22 0 +OP4 E02F23 0 +OP4 E02F24 0 +OP4 E02F25 0 +OP4 E02F26 0 +OP4 E02F27 0 +OP4 E02F28 0 +OP4 E02F29 0 +OP4 E02F2A 0 +OP4 E02F2B 0 +OP4 E02F2C 0 +OP4 E02F2D 0 +OP4 E02F2E 0 +OP4 E02F2F 0 +OP4 E02F30 0 +OP4 E02F31 0 +OP4 E02F32 0 +OP4 E02F33 0 +OP4 E02F34 0 +OP4 E02F35 0 +OP4 E02F36 0 +OP4 E02F37 0 +OP4 E02F38 0 +OP4 E02F39 0 +OP4 E02F3A 0 +OP4 E02F3B 0 +OP4 E02F3C 0 +OP4 E02F3D 0 +OP4 E02F3E 0 +OP4 E02F3F 0 +OP4 E02F40 0 +OP4 E02F41 0 +OP4 E02F42 0 +OP4 E02F43 0 +OP4 E02F44 0 +OP4 E02F45 0 +OP4 E02F46 0 +OP4 E02F47 0 +OP4 E02F48 0 +OP4 E02F49 0 +OP4 E02F4A 0 +OP4 E02F4B 0 +OP4 E02F4C 0 +OP4 E02F4D 0 +OP4 E02F4E 0 +OP4 E02F4F 0 +OP4 E02F50 0 +OP4 E02F51 0 +OP4 E02F52 0 +OP4 E02F53 0 +OP4 E02F54 0 +OP4 E02F55 0 +OP4 E02F56 0 +OP4 E02F57 0 +OP4 E02F58 0 +OP4 E02F59 0 +OP4 E02F5A 0 +OP4 E02F5B 0 +OP4 E02F5C 0 +OP4 E02F5D 0 +OP4 E02F5E 0 +OP4 E02F5F 0 +OP4 E02F60 0 +OP4 E02F61 0 +OP4 E02F62 0 +OP4 E02F63 0 +OP4 E02F64 0 +OP4 E02F65 0 +OP4 E02F66 0 +OP4 E02F67 0 +OP4 E02F68 0 +OP4 E02F69 0 +OP4 E02F6A 0 +OP4 E02F6B 0 +OP4 E02F6C 0 +OP4 E02F6D 0 +OP4 E02F6E 0 +OP4 E02F6F 0 +OP4 E02F70 0 +OP4 E02F71 0 +OP4 E02F72 0 +OP4 E02F73 0 +OP4 E02F74 0 +OP4 E02F75 0 +OP4 E02F76 0 +OP4 E02F77 0 +OP4 E02F78 0 +OP4 E02F79 0 +OP4 E02F7A 0 +OP4 E02F7B 0 +OP4 E02F7C 0 +OP4 E02F7D 0 +OP4 E02F7E 0 +OP4 E02F7F 0 +OP4 E02F80 0 +OP4 E02F81 0 +OP4 E02F82 0 +OP4 E02F83 0 +OP4 E02F84 0 +OP4 E02F85 0 +OP4 E02F86 0 +OP4 E02F87 0 +OP4 E02F88 0 +OP4 E02F89 0 +OP4 E02F8A 0 +OP4 E02F8B 0 +OP4 E02F8C 0 +OP4 E02F8D 0 +OP4 E02F8E 0 +OP4 E02F8F 0 +OP4 E02F90 0 +OP4 E02F91 0 +OP4 E02F92 0 +OP4 E02F93 0 +OP4 E02F94 0 +OP4 E02F95 0 +OP4 E02F96 0 +OP4 E02F97 0 +OP4 E02F98 0 +OP4 E02F99 0 +OP4 E02F9A 0 +OP4 E02F9B 0 +OP4 E02F9C 0 +OP4 E02F9D 0 +OP4 E02F9E 0 +OP4 E02F9F 0 +OP4 E02FA0 0 +OP4 E02FA1 0 +OP4 E02FA2 0 +OP4 E02FA3 0 +OP4 E02FA4 0 +OP4 E02FA5 0 +OP4 E02FA6 0 +OP4 E02FA7 0 +OP4 E02FA8 0 +OP4 E02FA9 0 +OP4 E02FAA 0 +OP4 E02FAB 0 +OP4 E02FAC 0 +OP4 E02FAD 0 +OP4 E02FAE 0 +OP4 E02FAF 0 +OP4 E02FB0 0 +OP4 E02FB1 0 +OP4 E02FB2 0 +OP4 E02FB3 0 +OP4 E02FB4 0 +OP4 E02FB5 0 +OP4 E02FB6 0 +OP4 E02FB7 0 +OP4 E02FB8 0 +OP4 E02FB9 0 +OP4 E02FBA 0 +OP4 E02FBB 0 +OP4 E02FBC 0 +OP4 E02FBD 0 +OP4 E02FBE 0 +OP4 E02FBF 0 +OP4 E02FC0 0 +OP4 E02FC1 0 +OP4 E02FC2 0 +OP4 E02FC3 0 +OP4 E02FC4 0 +OP4 E02FC5 0 +OP4 E02FC6 0 +OP4 E02FC7 0 +OP4 E02FC8 0 +OP4 E02FC9 0 +OP4 E02FCA 0 +OP4 E02FCB 0 +OP4 E02FCC 0 +OP4 E02FCD 0 +OP4 E02FCE 0 +OP4 E02FCF 0 +OP4 E02FD0 0 +OP4 E02FD1 0 +OP4 E02FD2 0 +OP4 E02FD3 0 +OP4 E02FD4 0 +OP4 E02FD5 0 +OP4 E02FD6 0 +OP4 E02FD7 0 +OP4 E02FD8 0 +OP4 E02FD9 0 +OP4 E02FDA 0 +OP4 E02FDB 0 +OP4 E02FDC 0 +OP4 E02FDD 0 +OP4 E02FDE 0 +OP4 E02FDF 0 +OP4 E02FE0 0 +OP4 E02FE1 0 +OP4 E02FE2 0 +OP4 E02FE3 0 +OP4 E02FE4 0 +OP4 E02FE5 0 +OP4 E02FE6 0 +OP4 E02FE7 0 +OP4 E02FE8 0 +OP4 E02FE9 0 +OP4 E02FEA 0 +OP4 E02FEB 0 +OP4 E02FEC 0 +OP4 E02FED 0 +OP4 E02FEE 0 +OP4 E02FEF 0 +OP4 E02FF0 0 +OP4 E02FF1 0 +OP4 E02FF2 0 +OP4 E02FF3 0 +OP4 E02FF4 0 +OP4 E02FF5 0 +OP4 E02FF6 0 +OP4 E02FF7 0 +OP4 E02FF8 0 +OP4 E02FF9 0 +OP4 E02FFA 0 +OP4 E02FFB 0 +OP4 E02FFC 0 +OP4 E02FFD 0 +OP4 E02FFE 0 +OP4 E02FFF 0 +OP4 E03000 0 +OP4 E03001 0 +OP4 E03002 0 +OP4 E03003 0 +OP4 E03004 0 +OP4 E03005 0 +OP4 E03006 0 +OP4 E03007 0 +OP4 E03008 0 +OP4 E03009 0 +OP4 E0300A 0 +OP4 E0300B 0 +OP4 E0300C 0 +OP4 E0300D 0 +OP4 E0300E 0 +OP4 E0300F 0 +OP4 E03010 0 +OP4 E03011 0 +OP4 E03012 0 +OP4 E03013 0 +OP4 E03014 0 +OP4 E03015 0 +OP4 E03016 0 +OP4 E03017 0 +OP4 E03018 0 +OP4 E03019 0 +OP4 E0301A 0 +OP4 E0301B 0 +OP4 E0301C 0 +OP4 E0301D 0 +OP4 E0301E 0 +OP4 E0301F 0 +OP4 E03020 0 +OP4 E03021 0 +OP4 E03022 0 +OP4 E03023 0 +OP4 E03024 0 +OP4 E03025 0 +OP4 E03026 0 +OP4 E03027 0 +OP4 E03028 0 +OP4 E03029 0 +OP4 E0302A 0 +OP4 E0302B 0 +OP4 E0302C 0 +OP4 E0302D 0 +OP4 E0302E 0 +OP4 E0302F 0 +OP4 E03030 0 +OP4 E03031 0 +OP4 E03032 0 +OP4 E03033 0 +OP4 E03034 0 +OP4 E03035 0 +OP4 E03036 0 +OP4 E03037 0 +OP4 E03038 0 +OP4 E03039 0 +OP4 E0303A 0 +OP4 E0303B 0 +OP4 E0303C 0 +OP4 E0303D 0 +OP4 E0303E 0 +OP4 E0303F 0 +OP4 E03040 0 +OP4 E03041 0 +OP4 E03042 0 +OP4 E03043 0 +OP4 E03044 0 +OP4 E03045 0 +OP4 E03046 0 +OP4 E03047 0 +OP4 E03048 0 +OP4 E03049 0 +OP4 E0304A 0 +OP4 E0304B 0 +OP4 E0304C 0 +OP4 E0304D 0 +OP4 E0304E 0 +OP4 E0304F 0 +OP4 E03050 0 +OP4 E03051 0 +OP4 E03052 0 +OP4 E03053 0 +OP4 E03054 0 +OP4 E03055 0 +OP4 E03056 0 +OP4 E03057 0 +OP4 E03058 0 +OP4 E03059 0 +OP4 E0305A 0 +OP4 E0305B 0 +OP4 E0305C 0 +OP4 E0305D 0 +OP4 E0305E 0 +OP4 E0305F 0 +OP4 E03060 0 +OP4 E03061 0 +OP4 E03062 0 +OP4 E03063 0 +OP4 E03064 0 +OP4 E03065 0 +OP4 E03066 0 +OP4 E03067 0 +OP4 E03068 0 +OP4 E03069 0 +OP4 E0306A 0 +OP4 E0306B 0 +OP4 E0306C 0 +OP4 E0306D 0 +OP4 E0306E 0 +OP4 E0306F 0 +OP4 E03070 0 +OP4 E03071 0 +OP4 E03072 0 +OP4 E03073 0 +OP4 E03074 0 +OP4 E03075 0 +OP4 E03076 0 +OP4 E03077 0 +OP4 E03078 0 +OP4 E03079 0 +OP4 E0307A 0 +OP4 E0307B 0 +OP4 E0307C 0 +OP4 E0307D 0 +OP4 E0307E 0 +OP4 E0307F 0 +OP4 E03080 0 +OP4 E03081 0 +OP4 E03082 0 +OP4 E03083 0 +OP4 E03084 0 +OP4 E03085 0 +OP4 E03086 0 +OP4 E03087 0 +OP4 E03088 0 +OP4 E03089 0 +OP4 E0308A 0 +OP4 E0308B 0 +OP4 E0308C 0 +OP4 E0308D 0 +OP4 E0308E 0 +OP4 E0308F 0 +OP4 E03090 0 +OP4 E03091 0 +OP4 E03092 0 +OP4 E03093 0 +OP4 E03094 0 +OP4 E03095 0 +OP4 E03096 0 +OP4 E03097 0 +OP4 E03098 0 +OP4 E03099 0 +OP4 E0309A 0 +OP4 E0309B 0 +OP4 E0309C 0 +OP4 E0309D 0 +OP4 E0309E 0 +OP4 E0309F 0 +OP4 E030A0 0 +OP4 E030A1 0 +OP4 E030A2 0 +OP4 E030A3 0 +OP4 E030A4 0 +OP4 E030A5 0 +OP4 E030A6 0 +OP4 E030A7 0 +OP4 E030A8 0 +OP4 E030A9 0 +OP4 E030AA 0 +OP4 E030AB 0 +OP4 E030AC 0 +OP4 E030AD 0 +OP4 E030AE 0 +OP4 E030AF 0 +OP4 E030B0 0 +OP4 E030B1 0 +OP4 E030B2 0 +OP4 E030B3 0 +OP4 E030B4 0 +OP4 E030B5 0 +OP4 E030B6 0 +OP4 E030B7 0 +OP4 E030B8 0 +OP4 E030B9 0 +OP4 E030BA 0 +OP4 E030BB 0 +OP4 E030BC 0 +OP4 E030BD 0 +OP4 E030BE 0 +OP4 E030BF 0 +OP4 E030C0 0 +OP4 E030C1 0 +OP4 E030C2 0 +OP4 E030C3 0 +OP4 E030C4 0 +OP4 E030C5 0 +OP4 E030C6 0 +OP4 E030C7 0 +OP4 E030C8 0 +OP4 E030C9 0 +OP4 E030CA 0 +OP4 E030CB 0 +OP4 E030CC 0 +OP4 E030CD 0 +OP4 E030CE 0 +OP4 E030CF 0 +OP4 E030D0 0 +OP4 E030D1 0 +OP4 E030D2 0 +OP4 E030D3 0 +OP4 E030D4 0 +OP4 E030D5 0 +OP4 E030D6 0 +OP4 E030D7 0 +OP4 E030D8 0 +OP4 E030D9 0 +OP4 E030DA 0 +OP4 E030DB 0 +OP4 E030DC 0 +OP4 E030DD 0 +OP4 E030DE 0 +OP4 E030DF 0 +OP4 E030E0 0 +OP4 E030E1 0 +OP4 E030E2 0 +OP4 E030E3 0 +OP4 E030E4 0 +OP4 E030E5 0 +OP4 E030E6 0 +OP4 E030E7 0 +OP4 E030E8 0 +OP4 E030E9 0 +OP4 E030EA 0 +OP4 E030EB 0 +OP4 E030EC 0 +OP4 E030ED 0 +OP4 E030EE 0 +OP4 E030EF 0 +OP4 E030F0 0 +OP4 E030F1 0 +OP4 E030F2 0 +OP4 E030F3 0 +OP4 E030F4 0 +OP4 E030F5 0 +OP4 E030F6 0 +OP4 E030F7 0 +OP4 E030F8 0 +OP4 E030F9 0 +OP4 E030FA 0 +OP4 E030FB 0 +OP4 E030FC 0 +OP4 E030FD 0 +OP4 E030FE 0 +OP4 E030FF 0 +OP4 E03100 0 +OP4 E03101 0 +OP4 E03102 0 +OP4 E03103 0 +OP4 E03104 0 +OP4 E03105 0 +OP4 E03106 0 +OP4 E03107 0 +OP4 E03108 0 +OP4 E03109 0 +OP4 E0310A 0 +OP4 E0310B 0 +OP4 E0310C 0 +OP4 E0310D 0 +OP4 E0310E 0 +OP4 E0310F 0 +OP4 E03110 0 +OP4 E03111 0 +OP4 E03112 0 +OP4 E03113 0 +OP4 E03114 0 +OP4 E03115 0 +OP4 E03116 0 +OP4 E03117 0 +OP4 E03118 0 +OP4 E03119 0 +OP4 E0311A 0 +OP4 E0311B 0 +OP4 E0311C 0 +OP4 E0311D 0 +OP4 E0311E 0 +OP4 E0311F 0 +OP4 E03120 0 +OP4 E03121 0 +OP4 E03122 0 +OP4 E03123 0 +OP4 E03124 0 +OP4 E03125 0 +OP4 E03126 0 +OP4 E03127 0 +OP4 E03128 0 +OP4 E03129 0 +OP4 E0312A 0 +OP4 E0312B 0 +OP4 E0312C 0 +OP4 E0312D 0 +OP4 E0312E 0 +OP4 E0312F 0 +OP4 E03130 0 +OP4 E03131 0 +OP4 E03132 0 +OP4 E03133 0 +OP4 E03134 0 +OP4 E03135 0 +OP4 E03136 0 +OP4 E03137 0 +OP4 E03138 0 +OP4 E03139 0 +OP4 E0313A 0 +OP4 E0313B 0 +OP4 E0313C 0 +OP4 E0313D 0 +OP4 E0313E 0 +OP4 E0313F 0 +OP4 E03140 0 +OP4 E03141 0 +OP4 E03142 0 +OP4 E03143 0 +OP4 E03144 0 +OP4 E03145 0 +OP4 E03146 0 +OP4 E03147 0 +OP4 E03148 0 +OP4 E03149 0 +OP4 E0314A 0 +OP4 E0314B 0 +OP4 E0314C 0 +OP4 E0314D 0 +OP4 E0314E 0 +OP4 E0314F 0 +OP4 E03150 0 +OP4 E03151 0 +OP4 E03152 0 +OP4 E03153 0 +OP4 E03154 0 +OP4 E03155 0 +OP4 E03156 0 +OP4 E03157 0 +OP4 E03158 0 +OP4 E03159 0 +OP4 E0315A 0 +OP4 E0315B 0 +OP4 E0315C 0 +OP4 E0315D 0 +OP4 E0315E 0 +OP4 E0315F 0 +OP4 E03160 0 +OP4 E03161 0 +OP4 E03162 0 +OP4 E03163 0 +OP4 E03164 0 +OP4 E03165 0 +OP4 E03166 0 +OP4 E03167 0 +OP4 E03168 0 +OP4 E03169 0 +OP4 E0316A 0 +OP4 E0316B 0 +OP4 E0316C 0 +OP4 E0316D 0 +OP4 E0316E 0 +OP4 E0316F 0 +OP4 E03170 0 +OP4 E03171 0 +OP4 E03172 0 +OP4 E03173 0 +OP4 E03174 0 +OP4 E03175 0 +OP4 E03176 0 +OP4 E03177 0 +OP4 E03178 0 +OP4 E03179 0 +OP4 E0317A 0 +OP4 E0317B 0 +OP4 E0317C 0 +OP4 E0317D 0 +OP4 E0317E 0 +OP4 E0317F 0 +OP4 E03180 0 +OP4 E03181 0 +OP4 E03182 0 +OP4 E03183 0 +OP4 E03184 0 +OP4 E03185 0 +OP4 E03186 0 +OP4 E03187 0 +OP4 E03188 0 +OP4 E03189 0 +OP4 E0318A 0 +OP4 E0318B 0 +OP4 E0318C 0 +OP4 E0318D 0 +OP4 E0318E 0 +OP4 E0318F 0 +OP4 E03190 0 +OP4 E03191 0 +OP4 E03192 0 +OP4 E03193 0 +OP4 E03194 0 +OP4 E03195 0 +OP4 E03196 0 +OP4 E03197 0 +OP4 E03198 0 +OP4 E03199 0 +OP4 E0319A 0 +OP4 E0319B 0 +OP4 E0319C 0 +OP4 E0319D 0 +OP4 E0319E 0 +OP4 E0319F 0 +OP4 E031A0 0 +OP4 E031A1 0 +OP4 E031A2 0 +OP4 E031A3 0 +OP4 E031A4 0 +OP4 E031A5 0 +OP4 E031A6 0 +OP4 E031A7 0 +OP4 E031A8 0 +OP4 E031A9 0 +OP4 E031AA 0 +OP4 E031AB 0 +OP4 E031AC 0 +OP4 E031AD 0 +OP4 E031AE 0 +OP4 E031AF 0 +OP4 E031B0 0 +OP4 E031B1 0 +OP4 E031B2 0 +OP4 E031B3 0 +OP4 E031B4 0 +OP4 E031B5 0 +OP4 E031B6 0 +OP4 E031B7 0 +OP4 E031B8 0 +OP4 E031B9 0 +OP4 E031BA 0 +OP4 E031BB 0 +OP4 E031BC 0 +OP4 E031BD 0 +OP4 E031BE 0 +OP4 E031BF 0 +OP4 E031C0 0 +OP4 E031C1 0 +OP4 E031C2 0 +OP4 E031C3 0 +OP4 E031C4 0 +OP4 E031C5 0 +OP4 E031C6 0 +OP4 E031C7 0 +OP4 E031C8 0 +OP4 E031C9 0 +OP4 E031CA 0 +OP4 E031CB 0 +OP4 E031CC 0 +OP4 E031CD 0 +OP4 E031CE 0 +OP4 E031CF 0 +OP4 E031D0 0 +OP4 E031D1 0 +OP4 E031D2 0 +OP4 E031D3 0 +OP4 E031D4 0 +OP4 E031D5 0 +OP4 E031D6 0 +OP4 E031D7 0 +OP4 E031D8 0 +OP4 E031D9 0 +OP4 E031DA 0 +OP4 E031DB 0 +OP4 E031DC 0 +OP4 E031DD 0 +OP4 E031DE 0 +OP4 E031DF 0 +OP4 E031E0 0 +OP4 E031E1 0 +OP4 E031E2 0 +OP4 E031E3 0 +OP4 E031E4 0 +OP4 E031E5 0 +OP4 E031E6 0 +OP4 E031E7 0 +OP4 E031E8 0 +OP4 E031E9 0 +OP4 E031EA 0 +OP4 E031EB 0 +OP4 E031EC 0 +OP4 E031ED 0 +OP4 E031EE 0 +OP4 E031EF 0 +OP4 E031F0 0 +OP4 E031F1 0 +OP4 E031F2 0 +OP4 E031F3 0 +OP4 E031F4 0 +OP4 E031F5 0 +OP4 E031F6 0 +OP4 E031F7 0 +OP4 E031F8 0 +OP4 E031F9 0 +OP4 E031FA 0 +OP4 E031FB 0 +OP4 E031FC 0 +OP4 E031FD 0 +OP4 E031FE 0 +OP4 E031FF 0 +OP4 E03200 0 +OP4 E03201 0 +OP4 E03202 0 +OP4 E03203 0 +OP4 E03204 0 +OP4 E03205 0 +OP4 E03206 0 +OP4 E03207 0 +OP4 E03208 0 +OP4 E03209 0 +OP4 E0320A 0 +OP4 E0320B 0 +OP4 E0320C 0 +OP4 E0320D 0 +OP4 E0320E 0 +OP4 E0320F 0 +OP4 E03210 0 +OP4 E03211 0 +OP4 E03212 0 +OP4 E03213 0 +OP4 E03214 0 +OP4 E03215 0 +OP4 E03216 0 +OP4 E03217 0 +OP4 E03218 0 +OP4 E03219 0 +OP4 E0321A 0 +OP4 E0321B 0 +OP4 E0321C 0 +OP4 E0321D 0 +OP4 E0321E 0 +OP4 E0321F 0 +OP4 E03220 0 +OP4 E03221 0 +OP4 E03222 0 +OP4 E03223 0 +OP4 E03224 0 +OP4 E03225 0 +OP4 E03226 0 +OP4 E03227 0 +OP4 E03228 0 +OP4 E03229 0 +OP4 E0322A 0 +OP4 E0322B 0 +OP4 E0322C 0 +OP4 E0322D 0 +OP4 E0322E 0 +OP4 E0322F 0 +OP4 E03230 0 +OP4 E03231 0 +OP4 E03232 0 +OP4 E03233 0 +OP4 E03234 0 +OP4 E03235 0 +OP4 E03236 0 +OP4 E03237 0 +OP4 E03238 0 +OP4 E03239 0 +OP4 E0323A 0 +OP4 E0323B 0 +OP4 E0323C 0 +OP4 E0323D 0 +OP4 E0323E 0 +OP4 E0323F 0 +OP4 E03240 0 +OP4 E03241 0 +OP4 E03242 0 +OP4 E03243 0 +OP4 E03244 0 +OP4 E03245 0 +OP4 E03246 0 +OP4 E03247 0 +OP4 E03248 0 +OP4 E03249 0 +OP4 E0324A 0 +OP4 E0324B 0 +OP4 E0324C 0 +OP4 E0324D 0 +OP4 E0324E 0 +OP4 E0324F 0 +OP4 E03250 0 +OP4 E03251 0 +OP4 E03252 0 +OP4 E03253 0 +OP4 E03254 0 +OP4 E03255 0 +OP4 E03256 0 +OP4 E03257 0 +OP4 E03258 0 +OP4 E03259 0 +OP4 E0325A 0 +OP4 E0325B 0 +OP4 E0325C 0 +OP4 E0325D 0 +OP4 E0325E 0 +OP4 E0325F 0 +OP4 E03260 0 +OP4 E03261 0 +OP4 E03262 0 +OP4 E03263 0 +OP4 E03264 0 +OP4 E03265 0 +OP4 E03266 0 +OP4 E03267 0 +OP4 E03268 0 +OP4 E03269 0 +OP4 E0326A 0 +OP4 E0326B 0 +OP4 E0326C 0 +OP4 E0326D 0 +OP4 E0326E 0 +OP4 E0326F 0 +OP4 E03270 0 +OP4 E03271 0 +OP4 E03272 0 +OP4 E03273 0 +OP4 E03274 0 +OP4 E03275 0 +OP4 E03276 0 +OP4 E03277 0 +OP4 E03278 0 +OP4 E03279 0 +OP4 E0327A 0 +OP4 E0327B 0 +OP4 E0327C 0 +OP4 E0327D 0 +OP4 E0327E 0 +OP4 E0327F 0 +OP4 E03280 0 +OP4 E03281 0 +OP4 E03282 0 +OP4 E03283 0 +OP4 E03284 0 +OP4 E03285 0 +OP4 E03286 0 +OP4 E03287 0 +OP4 E03288 0 +OP4 E03289 0 +OP4 E0328A 0 +OP4 E0328B 0 +OP4 E0328C 0 +OP4 E0328D 0 +OP4 E0328E 0 +OP4 E0328F 0 +OP4 E03290 0 +OP4 E03291 0 +OP4 E03292 0 +OP4 E03293 0 +OP4 E03294 0 +OP4 E03295 0 +OP4 E03296 0 +OP4 E03297 0 +OP4 E03298 0 +OP4 E03299 0 +OP4 E0329A 0 +OP4 E0329B 0 +OP4 E0329C 0 +OP4 E0329D 0 +OP4 E0329E 0 +OP4 E0329F 0 +OP4 E032A0 0 +OP4 E032A1 0 +OP4 E032A2 0 +OP4 E032A3 0 +OP4 E032A4 0 +OP4 E032A5 0 +OP4 E032A6 0 +OP4 E032A7 0 +OP4 E032A8 0 +OP4 E032A9 0 +OP4 E032AA 0 +OP4 E032AB 0 +OP4 E032AC 0 +OP4 E032AD 0 +OP4 E032AE 0 +OP4 E032AF 0 +OP4 E032B0 0 +OP4 E032B1 0 +OP4 E032B2 0 +OP4 E032B3 0 +OP4 E032B4 0 +OP4 E032B5 0 +OP4 E032B6 0 +OP4 E032B7 0 +OP4 E032B8 0 +OP4 E032B9 0 +OP4 E032BA 0 +OP4 E032BB 0 +OP4 E032BC 0 +OP4 E032BD 0 +OP4 E032BE 0 +OP4 E032BF 0 +OP4 E032C0 0 +OP4 E032C1 0 +OP4 E032C2 0 +OP4 E032C3 0 +OP4 E032C4 0 +OP4 E032C5 0 +OP4 E032C6 0 +OP4 E032C7 0 +OP4 E032C8 0 +OP4 E032C9 0 +OP4 E032CA 0 +OP4 E032CB 0 +OP4 E032CC 0 +OP4 E032CD 0 +OP4 E032CE 0 +OP4 E032CF 0 +OP4 E032D0 0 +OP4 E032D1 0 +OP4 E032D2 0 +OP4 E032D3 0 +OP4 E032D4 0 +OP4 E032D5 0 +OP4 E032D6 0 +OP4 E032D7 0 +OP4 E032D8 0 +OP4 E032D9 0 +OP4 E032DA 0 +OP4 E032DB 0 +OP4 E032DC 0 +OP4 E032DD 0 +OP4 E032DE 0 +OP4 E032DF 0 +OP4 E032E0 0 +OP4 E032E1 0 +OP4 E032E2 0 +OP4 E032E3 0 +OP4 E032E4 0 +OP4 E032E5 0 +OP4 E032E6 0 +OP4 E032E7 0 +OP4 E032E8 0 +OP4 E032E9 0 +OP4 E032EA 0 +OP4 E032EB 0 +OP4 E032EC 0 +OP4 E032ED 0 +OP4 E032EE 0 +OP4 E032EF 0 +OP4 E032F0 0 +OP4 E032F1 0 +OP4 E032F2 0 +OP4 E032F3 0 +OP4 E032F4 0 +OP4 E032F5 0 +OP4 E032F6 0 +OP4 E032F7 0 +OP4 E032F8 0 +OP4 E032F9 0 +OP4 E032FA 0 +OP4 E032FB 0 +OP4 E032FC 0 +OP4 E032FD 0 +OP4 E032FE 0 +OP4 E032FF 0 +OP4 E03300 0 +OP4 E03301 0 +OP4 E03302 0 +OP4 E03303 0 +OP4 E03304 0 +OP4 E03305 0 +OP4 E03306 0 +OP4 E03307 0 +OP4 E03308 0 +OP4 E03309 0 +OP4 E0330A 0 +OP4 E0330B 0 +OP4 E0330C 0 +OP4 E0330D 0 +OP4 E0330E 0 +OP4 E0330F 0 +OP4 E03310 0 +OP4 E03311 0 +OP4 E03312 0 +OP4 E03313 0 +OP4 E03314 0 +OP4 E03315 0 +OP4 E03316 0 +OP4 E03317 0 +OP4 E03318 0 +OP4 E03319 0 +OP4 E0331A 0 +OP4 E0331B 0 +OP4 E0331C 0 +OP4 E0331D 0 +OP4 E0331E 0 +OP4 E0331F 0 +OP4 E03320 0 +OP4 E03321 0 +OP4 E03322 0 +OP4 E03323 0 +OP4 E03324 0 +OP4 E03325 0 +OP4 E03326 0 +OP4 E03327 0 +OP4 E03328 0 +OP4 E03329 0 +OP4 E0332A 0 +OP4 E0332B 0 +OP4 E0332C 0 +OP4 E0332D 0 +OP4 E0332E 0 +OP4 E0332F 0 +OP4 E03330 0 +OP4 E03331 0 +OP4 E03332 0 +OP4 E03333 0 +OP4 E03334 0 +OP4 E03335 0 +OP4 E03336 0 +OP4 E03337 0 +OP4 E03338 0 +OP4 E03339 0 +OP4 E0333A 0 +OP4 E0333B 0 +OP4 E0333C 0 +OP4 E0333D 0 +OP4 E0333E 0 +OP4 E0333F 0 +OP4 E03340 0 +OP4 E03341 0 +OP4 E03342 0 +OP4 E03343 0 +OP4 E03344 0 +OP4 E03345 0 +OP4 E03346 0 +OP4 E03347 0 +OP4 E03348 0 +OP4 E03349 0 +OP4 E0334A 0 +OP4 E0334B 0 +OP4 E0334C 0 +OP4 E0334D 0 +OP4 E0334E 0 +OP4 E0334F 0 +OP4 E03350 0 +OP4 E03351 0 +OP4 E03352 0 +OP4 E03353 0 +OP4 E03354 0 +OP4 E03355 0 +OP4 E03356 0 +OP4 E03357 0 +OP4 E03358 0 +OP4 E03359 0 +OP4 E0335A 0 +OP4 E0335B 0 +OP4 E0335C 0 +OP4 E0335D 0 +OP4 E0335E 0 +OP4 E0335F 0 +OP4 E03360 0 +OP4 E03361 0 +OP4 E03362 0 +OP4 E03363 0 +OP4 E03364 0 +OP4 E03365 0 +OP4 E03366 0 +OP4 E03367 0 +OP4 E03368 0 +OP4 E03369 0 +OP4 E0336A 0 +OP4 E0336B 0 +OP4 E0336C 0 +OP4 E0336D 0 +OP4 E0336E 0 +OP4 E0336F 0 +OP4 E03370 0 +OP4 E03371 0 +OP4 E03372 0 +OP4 E03373 0 +OP4 E03374 0 +OP4 E03375 0 +OP4 E03376 0 +OP4 E03377 0 +OP4 E03378 0 +OP4 E03379 0 +OP4 E0337A 0 +OP4 E0337B 0 +OP4 E0337C 0 +OP4 E0337D 0 +OP4 E0337E 0 +OP4 E0337F 0 +OP4 E03380 0 +OP4 E03381 0 +OP4 E03382 0 +OP4 E03383 0 +OP4 E03384 0 +OP4 E03385 0 +OP4 E03386 0 +OP4 E03387 0 +OP4 E03388 0 +OP4 E03389 0 +OP4 E0338A 0 +OP4 E0338B 0 +OP4 E0338C 0 +OP4 E0338D 0 +OP4 E0338E 0 +OP4 E0338F 0 +OP4 E03390 0 +OP4 E03391 0 +OP4 E03392 0 +OP4 E03393 0 +OP4 E03394 0 +OP4 E03395 0 +OP4 E03396 0 +OP4 E03397 0 +OP4 E03398 0 +OP4 E03399 0 +OP4 E0339A 0 +OP4 E0339B 0 +OP4 E0339C 0 +OP4 E0339D 0 +OP4 E0339E 0 +OP4 E0339F 0 +OP4 E033A0 0 +OP4 E033A1 0 +OP4 E033A2 0 +OP4 E033A3 0 +OP4 E033A4 0 +OP4 E033A5 0 +OP4 E033A6 0 +OP4 E033A7 0 +OP4 E033A8 0 +OP4 E033A9 0 +OP4 E033AA 0 +OP4 E033AB 0 +OP4 E033AC 0 +OP4 E033AD 0 +OP4 E033AE 0 +OP4 E033AF 0 +OP4 E033B0 0 +OP4 E033B1 0 +OP4 E033B2 0 +OP4 E033B3 0 +OP4 E033B4 0 +OP4 E033B5 0 +OP4 E033B6 0 +OP4 E033B7 0 +OP4 E033B8 0 +OP4 E033B9 0 +OP4 E033BA 0 +OP4 E033BB 0 +OP4 E033BC 0 +OP4 E033BD 0 +OP4 E033BE 0 +OP4 E033BF 0 +OP4 E033C0 0 +OP4 E033C1 0 +OP4 E033C2 0 +OP4 E033C3 0 +OP4 E033C4 0 +OP4 E033C5 0 +OP4 E033C6 0 +OP4 E033C7 0 +OP4 E033C8 0 +OP4 E033C9 0 +OP4 E033CA 0 +OP4 E033CB 0 +OP4 E033CC 0 +OP4 E033CD 0 +OP4 E033CE 0 +OP4 E033CF 0 +OP4 E033D0 0 +OP4 E033D1 0 +OP4 E033D2 0 +OP4 E033D3 0 +OP4 E033D4 0 +OP4 E033D5 0 +OP4 E033D6 0 +OP4 E033D7 0 +OP4 E033D8 0 +OP4 E033D9 0 +OP4 E033DA 0 +OP4 E033DB 0 +OP4 E033DC 0 +OP4 E033DD 0 +OP4 E033DE 0 +OP4 E033DF 0 +OP4 E033E0 0 +OP4 E033E1 0 +OP4 E033E2 0 +OP4 E033E3 0 +OP4 E033E4 0 +OP4 E033E5 0 +OP4 E033E6 0 +OP4 E033E7 0 +OP4 E033E8 0 +OP4 E033E9 0 +OP4 E033EA 0 +OP4 E033EB 0 +OP4 E033EC 0 +OP4 E033ED 0 +OP4 E033EE 0 +OP4 E033EF 0 +OP4 E033F0 0 +OP4 E033F1 0 +OP4 E033F2 0 +OP4 E033F3 0 +OP4 E033F4 0 +OP4 E033F5 0 +OP4 E033F6 0 +OP4 E033F7 0 +OP4 E033F8 0 +OP4 E033F9 0 +OP4 E033FA 0 +OP4 E033FB 0 +OP4 E033FC 0 +OP4 E033FD 0 +OP4 E033FE 0 +OP4 E033FF 0 +OP4 E03400 0 +OP4 E03401 0 +OP4 E03402 0 +OP4 E03403 0 +OP4 E03404 0 +OP4 E03405 0 +OP4 E03406 0 +OP4 E03407 0 +OP4 E03408 0 +OP4 E03409 0 +OP4 E0340A 0 +OP4 E0340B 0 +OP4 E0340C 0 +OP4 E0340D 0 +OP4 E0340E 0 +OP4 E0340F 0 +OP4 E03410 0 +OP4 E03411 0 +OP4 E03412 0 +OP4 E03413 0 +OP4 E03414 0 +OP4 E03415 0 +OP4 E03416 0 +OP4 E03417 0 +OP4 E03418 0 +OP4 E03419 0 +OP4 E0341A 0 +OP4 E0341B 0 +OP4 E0341C 0 +OP4 E0341D 0 +OP4 E0341E 0 +OP4 E0341F 0 +OP4 E03420 0 +OP4 E03421 0 +OP4 E03422 0 +OP4 E03423 0 +OP4 E03424 0 +OP4 E03425 0 +OP4 E03426 0 +OP4 E03427 0 +OP4 E03428 0 +OP4 E03429 0 +OP4 E0342A 0 +OP4 E0342B 0 +OP4 E0342C 0 +OP4 E0342D 0 +OP4 E0342E 0 +OP4 E0342F 0 +OP4 E03430 0 +OP4 E03431 0 +OP4 E03432 0 +OP4 E03433 0 +OP4 E03434 0 +OP4 E03435 0 +OP4 E03436 0 +OP4 E03437 0 +OP4 E03438 0 +OP4 E03439 0 +OP4 E0343A 0 +OP4 E0343B 0 +OP4 E0343C 0 +OP4 E0343D 0 +OP4 E0343E 0 +OP4 E0343F 0 +OP4 E03440 0 +OP4 E03441 0 +OP4 E03442 0 +OP4 E03443 0 +OP4 E03444 0 +OP4 E03445 0 +OP4 E03446 0 +OP4 E03447 0 +OP4 E03448 0 +OP4 E03449 0 +OP4 E0344A 0 +OP4 E0344B 0 +OP4 E0344C 0 +OP4 E0344D 0 +OP4 E0344E 0 +OP4 E0344F 0 +OP4 E03450 0 +OP4 E03451 0 +OP4 E03452 0 +OP4 E03453 0 +OP4 E03454 0 +OP4 E03455 0 +OP4 E03456 0 +OP4 E03457 0 +OP4 E03458 0 +OP4 E03459 0 +OP4 E0345A 0 +OP4 E0345B 0 +OP4 E0345C 0 +OP4 E0345D 0 +OP4 E0345E 0 +OP4 E0345F 0 +OP4 E03460 0 +OP4 E03461 0 +OP4 E03462 0 +OP4 E03463 0 +OP4 E03464 0 +OP4 E03465 0 +OP4 E03466 0 +OP4 E03467 0 +OP4 E03468 0 +OP4 E03469 0 +OP4 E0346A 0 +OP4 E0346B 0 +OP4 E0346C 0 +OP4 E0346D 0 +OP4 E0346E 0 +OP4 E0346F 0 +OP4 E03470 0 +OP4 E03471 0 +OP4 E03472 0 +OP4 E03473 0 +OP4 E03474 0 +OP4 E03475 0 +OP4 E03476 0 +OP4 E03477 0 +OP4 E03478 0 +OP4 E03479 0 +OP4 E0347A 0 +OP4 E0347B 0 +OP4 E0347C 0 +OP4 E0347D 0 +OP4 E0347E 0 +OP4 E0347F 0 +OP4 E03480 0 +OP4 E03481 0 +OP4 E03482 0 +OP4 E03483 0 +OP4 E03484 0 +OP4 E03485 0 +OP4 E03486 0 +OP4 E03487 0 +OP4 E03488 0 +OP4 E03489 0 +OP4 E0348A 0 +OP4 E0348B 0 +OP4 E0348C 0 +OP4 E0348D 0 +OP4 E0348E 0 +OP4 E0348F 0 +OP4 E03490 0 +OP4 E03491 0 +OP4 E03492 0 +OP4 E03493 0 +OP4 E03494 0 +OP4 E03495 0 +OP4 E03496 0 +OP4 E03497 0 +OP4 E03498 0 +OP4 E03499 0 +OP4 E0349A 0 +OP4 E0349B 0 +OP4 E0349C 0 +OP4 E0349D 0 +OP4 E0349E 0 +OP4 E0349F 0 +OP4 E034A0 0 +OP4 E034A1 0 +OP4 E034A2 0 +OP4 E034A3 0 +OP4 E034A4 0 +OP4 E034A5 0 +OP4 E034A6 0 +OP4 E034A7 0 +OP4 E034A8 0 +OP4 E034A9 0 +OP4 E034AA 0 +OP4 E034AB 0 +OP4 E034AC 0 +OP4 E034AD 0 +OP4 E034AE 0 +OP4 E034AF 0 +OP4 E034B0 0 +OP4 E034B1 0 +OP4 E034B2 0 +OP4 E034B3 0 +OP4 E034B4 0 +OP4 E034B5 0 +OP4 E034B6 0 +OP4 E034B7 0 +OP4 E034B8 0 +OP4 E034B9 0 +OP4 E034BA 0 +OP4 E034BB 0 +OP4 E034BC 0 +OP4 E034BD 0 +OP4 E034BE 0 +OP4 E034BF 0 +OP4 E034C0 0 +OP4 E034C1 0 +OP4 E034C2 0 +OP4 E034C3 0 +OP4 E034C4 0 +OP4 E034C5 0 +OP4 E034C6 0 +OP4 E034C7 0 +OP4 E034C8 0 +OP4 E034C9 0 +OP4 E034CA 0 +OP4 E034CB 0 +OP4 E034CC 0 +OP4 E034CD 0 +OP4 E034CE 0 +OP4 E034CF 0 +OP4 E034D0 0 +OP4 E034D1 0 +OP4 E034D2 0 +OP4 E034D3 0 +OP4 E034D4 0 +OP4 E034D5 0 +OP4 E034D6 0 +OP4 E034D7 0 +OP4 E034D8 0 +OP4 E034D9 0 +OP4 E034DA 0 +OP4 E034DB 0 +OP4 E034DC 0 +OP4 E034DD 0 +OP4 E034DE 0 +OP4 E034DF 0 +OP4 E034E0 0 +OP4 E034E1 0 +OP4 E034E2 0 +OP4 E034E3 0 +OP4 E034E4 0 +OP4 E034E5 0 +OP4 E034E6 0 +OP4 E034E7 0 +OP4 E034E8 0 +OP4 E034E9 0 +OP4 E034EA 0 +OP4 E034EB 0 +OP4 E034EC 0 +OP4 E034ED 0 +OP4 E034EE 0 +OP4 E034EF 0 +OP4 E034F0 0 +OP4 E034F1 0 +OP4 E034F2 0 +OP4 E034F3 0 +OP4 E034F4 0 +OP4 E034F5 0 +OP4 E034F6 0 +OP4 E034F7 0 +OP4 E034F8 0 +OP4 E034F9 0 +OP4 E034FA 0 +OP4 E034FB 0 +OP4 E034FC 0 +OP4 E034FD 0 +OP4 E034FE 0 +OP4 E034FF 0 +OP4 E03500 0 +OP4 E03501 0 +OP4 E03502 0 +OP4 E03503 0 +OP4 E03504 0 +OP4 E03505 0 +OP4 E03506 0 +OP4 E03507 0 +OP4 E03508 0 +OP4 E03509 0 +OP4 E0350A 0 +OP4 E0350B 0 +OP4 E0350C 0 +OP4 E0350D 0 +OP4 E0350E 0 +OP4 E0350F 0 +OP4 E03510 0 +OP4 E03511 0 +OP4 E03512 0 +OP4 E03513 0 +OP4 E03514 0 +OP4 E03515 0 +OP4 E03516 0 +OP4 E03517 0 +OP4 E03518 0 +OP4 E03519 0 +OP4 E0351A 0 +OP4 E0351B 0 +OP4 E0351C 0 +OP4 E0351D 0 +OP4 E0351E 0 +OP4 E0351F 0 +OP4 E03520 0 +OP4 E03521 0 +OP4 E03522 0 +OP4 E03523 0 +OP4 E03524 0 +OP4 E03525 0 +OP4 E03526 0 +OP4 E03527 0 +OP4 E03528 0 +OP4 E03529 0 +OP4 E0352A 0 +OP4 E0352B 0 +OP4 E0352C 0 +OP4 E0352D 0 +OP4 E0352E 0 +OP4 E0352F 0 +OP4 E03530 0 +OP4 E03531 0 +OP4 E03532 0 +OP4 E03533 0 +OP4 E03534 0 +OP4 E03535 0 +OP4 E03536 0 +OP4 E03537 0 +OP4 E03538 0 +OP4 E03539 0 +OP4 E0353A 0 +OP4 E0353B 0 +OP4 E0353C 0 +OP4 E0353D 0 +OP4 E0353E 0 +OP4 E0353F 0 +OP4 E03540 0 +OP4 E03541 0 +OP4 E03542 0 +OP4 E03543 0 +OP4 E03544 0 +OP4 E03545 0 +OP4 E03546 0 +OP4 E03547 0 +OP4 E03548 0 +OP4 E03549 0 +OP4 E0354A 0 +OP4 E0354B 0 +OP4 E0354C 0 +OP4 E0354D 0 +OP4 E0354E 0 +OP4 E0354F 0 +OP4 E03550 0 +OP4 E03551 0 +OP4 E03552 0 +OP4 E03553 0 +OP4 E03554 0 +OP4 E03555 0 +OP4 E03556 0 +OP4 E03557 0 +OP4 E03558 0 +OP4 E03559 0 +OP4 E0355A 0 +OP4 E0355B 0 +OP4 E0355C 0 +OP4 E0355D 0 +OP4 E0355E 0 +OP4 E0355F 0 +OP4 E03560 0 +OP4 E03561 0 +OP4 E03562 0 +OP4 E03563 0 +OP4 E03564 0 +OP4 E03565 0 +OP4 E03566 0 +OP4 E03567 0 +OP4 E03568 0 +OP4 E03569 0 +OP4 E0356A 0 +OP4 E0356B 0 +OP4 E0356C 0 +OP4 E0356D 0 +OP4 E0356E 0 +OP4 E0356F 0 +OP4 E03570 0 +OP4 E03571 0 +OP4 E03572 0 +OP4 E03573 0 +OP4 E03574 0 +OP4 E03575 0 +OP4 E03576 0 +OP4 E03577 0 +OP4 E03578 0 +OP4 E03579 0 +OP4 E0357A 0 +OP4 E0357B 0 +OP4 E0357C 0 +OP4 E0357D 0 +OP4 E0357E 0 +OP4 E0357F 0 +OP4 E03580 0 +OP4 E03581 0 +OP4 E03582 0 +OP4 E03583 0 +OP4 E03584 0 +OP4 E03585 0 +OP4 E03586 0 +OP4 E03587 0 +OP4 E03588 0 +OP4 E03589 0 +OP4 E0358A 0 +OP4 E0358B 0 +OP4 E0358C 0 +OP4 E0358D 0 +OP4 E0358E 0 +OP4 E0358F 0 +OP4 E03590 0 +OP4 E03591 0 +OP4 E03592 0 +OP4 E03593 0 +OP4 E03594 0 +OP4 E03595 0 +OP4 E03596 0 +OP4 E03597 0 +OP4 E03598 0 +OP4 E03599 0 +OP4 E0359A 0 +OP4 E0359B 0 +OP4 E0359C 0 +OP4 E0359D 0 +OP4 E0359E 0 +OP4 E0359F 0 +OP4 E035A0 0 +OP4 E035A1 0 +OP4 E035A2 0 +OP4 E035A3 0 +OP4 E035A4 0 +OP4 E035A5 0 +OP4 E035A6 0 +OP4 E035A7 0 +OP4 E035A8 0 +OP4 E035A9 0 +OP4 E035AA 0 +OP4 E035AB 0 +OP4 E035AC 0 +OP4 E035AD 0 +OP4 E035AE 0 +OP4 E035AF 0 +OP4 E035B0 0 +OP4 E035B1 0 +OP4 E035B2 0 +OP4 E035B3 0 +OP4 E035B4 0 +OP4 E035B5 0 +OP4 E035B6 0 +OP4 E035B7 0 +OP4 E035B8 0 +OP4 E035B9 0 +OP4 E035BA 0 +OP4 E035BB 0 +OP4 E035BC 0 +OP4 E035BD 0 +OP4 E035BE 0 +OP4 E035BF 0 +OP4 E035C0 0 +OP4 E035C1 0 +OP4 E035C2 0 +OP4 E035C3 0 +OP4 E035C4 0 +OP4 E035C5 0 +OP4 E035C6 0 +OP4 E035C7 0 +OP4 E035C8 0 +OP4 E035C9 0 +OP4 E035CA 0 +OP4 E035CB 0 +OP4 E035CC 0 +OP4 E035CD 0 +OP4 E035CE 0 +OP4 E035CF 0 +OP4 E035D0 0 +OP4 E035D1 0 +OP4 E035D2 0 +OP4 E035D3 0 +OP4 E035D4 0 +OP4 E035D5 0 +OP4 E035D6 0 +OP4 E035D7 0 +OP4 E035D8 0 +OP4 E035D9 0 +OP4 E035DA 0 +OP4 E035DB 0 +OP4 E035DC 0 +OP4 E035DD 0 +OP4 E035DE 0 +OP4 E035DF 0 +OP4 E035E0 0 +OP4 E035E1 0 +OP4 E035E2 0 +OP4 E035E3 0 +OP4 E035E4 0 +OP4 E035E5 0 +OP4 E035E6 0 +OP4 E035E7 0 +OP4 E035E8 0 +OP4 E035E9 0 +OP4 E035EA 0 +OP4 E035EB 0 +OP4 E035EC 0 +OP4 E035ED 0 +OP4 E035EE 0 +OP4 E035EF 0 +OP4 E035F0 0 +OP4 E035F1 0 +OP4 E035F2 0 +OP4 E035F3 0 +OP4 E035F4 0 +OP4 E035F5 0 +OP4 E035F6 0 +OP4 E035F7 0 +OP4 E035F8 0 +OP4 E035F9 0 +OP4 E035FA 0 +OP4 E035FB 0 +OP4 E035FC 0 +OP4 E035FD 0 +OP4 E035FE 0 +OP4 E035FF 0 +OP4 E03600 0 +OP4 E03601 0 +OP4 E03602 0 +OP4 E03603 0 +OP4 E03604 0 +OP4 E03605 0 +OP4 E03606 0 +OP4 E03607 0 +OP4 E03608 0 +OP4 E03609 0 +OP4 E0360A 0 +OP4 E0360B 0 +OP4 E0360C 0 +OP4 E0360D 0 +OP4 E0360E 0 +OP4 E0360F 0 +OP4 E03610 0 +OP4 E03611 0 +OP4 E03612 0 +OP4 E03613 0 +OP4 E03614 0 +OP4 E03615 0 +OP4 E03616 0 +OP4 E03617 0 +OP4 E03618 0 +OP4 E03619 0 +OP4 E0361A 0 +OP4 E0361B 0 +OP4 E0361C 0 +OP4 E0361D 0 +OP4 E0361E 0 +OP4 E0361F 0 +OP4 E03620 0 +OP4 E03621 0 +OP4 E03622 0 +OP4 E03623 0 +OP4 E03624 0 +OP4 E03625 0 +OP4 E03626 0 +OP4 E03627 0 +OP4 E03628 0 +OP4 E03629 0 +OP4 E0362A 0 +OP4 E0362B 0 +OP4 E0362C 0 +OP4 E0362D 0 +OP4 E0362E 0 +OP4 E0362F 0 +OP4 E03630 0 +OP4 E03631 0 +OP4 E03632 0 +OP4 E03633 0 +OP4 E03634 0 +OP4 E03635 0 +OP4 E03636 0 +OP4 E03637 0 +OP4 E03638 0 +OP4 E03639 0 +OP4 E0363A 0 +OP4 E0363B 0 +OP4 E0363C 0 +OP4 E0363D 0 +OP4 E0363E 0 +OP4 E0363F 0 +OP4 E03640 0 +OP4 E03641 0 +OP4 E03642 0 +OP4 E03643 0 +OP4 E03644 0 +OP4 E03645 0 +OP4 E03646 0 +OP4 E03647 0 +OP4 E03648 0 +OP4 E03649 0 +OP4 E0364A 0 +OP4 E0364B 0 +OP4 E0364C 0 +OP4 E0364D 0 +OP4 E0364E 0 +OP4 E0364F 0 +OP4 E03650 0 +OP4 E03651 0 +OP4 E03652 0 +OP4 E03653 0 +OP4 E03654 0 +OP4 E03655 0 +OP4 E03656 0 +OP4 E03657 0 +OP4 E03658 0 +OP4 E03659 0 +OP4 E0365A 0 +OP4 E0365B 0 +OP4 E0365C 0 +OP4 E0365D 0 +OP4 E0365E 0 +OP4 E0365F 0 +OP4 E03660 0 +OP4 E03661 0 +OP4 E03662 0 +OP4 E03663 0 +OP4 E03664 0 +OP4 E03665 0 +OP4 E03666 0 +OP4 E03667 0 +OP4 E03668 0 +OP4 E03669 0 +OP4 E0366A 0 +OP4 E0366B 0 +OP4 E0366C 0 +OP4 E0366D 0 +OP4 E0366E 0 +OP4 E0366F 0 +OP4 E03670 0 +OP4 E03671 0 +OP4 E03672 0 +OP4 E03673 0 +OP4 E03674 0 +OP4 E03675 0 +OP4 E03676 0 +OP4 E03677 0 +OP4 E03678 0 +OP4 E03679 0 +OP4 E0367A 0 +OP4 E0367B 0 +OP4 E0367C 0 +OP4 E0367D 0 +OP4 E0367E 0 +OP4 E0367F 0 +OP4 E03680 0 +OP4 E03681 0 +OP4 E03682 0 +OP4 E03683 0 +OP4 E03684 0 +OP4 E03685 0 +OP4 E03686 0 +OP4 E03687 0 +OP4 E03688 0 +OP4 E03689 0 +OP4 E0368A 0 +OP4 E0368B 0 +OP4 E0368C 0 +OP4 E0368D 0 +OP4 E0368E 0 +OP4 E0368F 0 +OP4 E03690 0 +OP4 E03691 0 +OP4 E03692 0 +OP4 E03693 0 +OP4 E03694 0 +OP4 E03695 0 +OP4 E03696 0 +OP4 E03697 0 +OP4 E03698 0 +OP4 E03699 0 +OP4 E0369A 0 +OP4 E0369B 0 +OP4 E0369C 0 +OP4 E0369D 0 +OP4 E0369E 0 +OP4 E0369F 0 +OP4 E036A0 0 +OP4 E036A1 0 +OP4 E036A2 0 +OP4 E036A3 0 +OP4 E036A4 0 +OP4 E036A5 0 +OP4 E036A6 0 +OP4 E036A7 0 +OP4 E036A8 0 +OP4 E036A9 0 +OP4 E036AA 0 +OP4 E036AB 0 +OP4 E036AC 0 +OP4 E036AD 0 +OP4 E036AE 0 +OP4 E036AF 0 +OP4 E036B0 0 +OP4 E036B1 0 +OP4 E036B2 0 +OP4 E036B3 0 +OP4 E036B4 0 +OP4 E036B5 0 +OP4 E036B6 0 +OP4 E036B7 0 +OP4 E036B8 0 +OP4 E036B9 0 +OP4 E036BA 0 +OP4 E036BB 0 +OP4 E036BC 0 +OP4 E036BD 0 +OP4 E036BE 0 +OP4 E036BF 0 +OP4 E036C0 0 +OP4 E036C1 0 +OP4 E036C2 0 +OP4 E036C3 0 +OP4 E036C4 0 +OP4 E036C5 0 +OP4 E036C6 0 +OP4 E036C7 0 +OP4 E036C8 0 +OP4 E036C9 0 +OP4 E036CA 0 +OP4 E036CB 0 +OP4 E036CC 0 +OP4 E036CD 0 +OP4 E036CE 0 +OP4 E036CF 0 +OP4 E036D0 0 +OP4 E036D1 0 +OP4 E036D2 0 +OP4 E036D3 0 +OP4 E036D4 0 +OP4 E036D5 0 +OP4 E036D6 0 +OP4 E036D7 0 +OP4 E036D8 0 +OP4 E036D9 0 +OP4 E036DA 0 +OP4 E036DB 0 +OP4 E036DC 0 +OP4 E036DD 0 +OP4 E036DE 0 +OP4 E036DF 0 +OP4 E036E0 0 +OP4 E036E1 0 +OP4 E036E2 0 +OP4 E036E3 0 +OP4 E036E4 0 +OP4 E036E5 0 +OP4 E036E6 0 +OP4 E036E7 0 +OP4 E036E8 0 +OP4 E036E9 0 +OP4 E036EA 0 +OP4 E036EB 0 +OP4 E036EC 0 +OP4 E036ED 0 +OP4 E036EE 0 +OP4 E036EF 0 +OP4 E036F0 0 +OP4 E036F1 0 +OP4 E036F2 0 +OP4 E036F3 0 +OP4 E036F4 0 +OP4 E036F5 0 +OP4 E036F6 0 +OP4 E036F7 0 +OP4 E036F8 0 +OP4 E036F9 0 +OP4 E036FA 0 +OP4 E036FB 0 +OP4 E036FC 0 +OP4 E036FD 0 +OP4 E036FE 0 +OP4 E036FF 0 +OP4 E03700 0 +OP4 E03701 0 +OP4 E03702 0 +OP4 E03703 0 +OP4 E03704 0 +OP4 E03705 0 +OP4 E03706 0 +OP4 E03707 0 +OP4 E03708 0 +OP4 E03709 0 +OP4 E0370A 0 +OP4 E0370B 0 +OP4 E0370C 0 +OP4 E0370D 0 +OP4 E0370E 0 +OP4 E0370F 0 +OP4 E03710 0 +OP4 E03711 0 +OP4 E03712 0 +OP4 E03713 0 +OP4 E03714 0 +OP4 E03715 0 +OP4 E03716 0 +OP4 E03717 0 +OP4 E03718 0 +OP4 E03719 0 +OP4 E0371A 0 +OP4 E0371B 0 +OP4 E0371C 0 +OP4 E0371D 0 +OP4 E0371E 0 +OP4 E0371F 0 +OP4 E03720 0 +OP4 E03721 0 +OP4 E03722 0 +OP4 E03723 0 +OP4 E03724 0 +OP4 E03725 0 +OP4 E03726 0 +OP4 E03727 0 +OP4 E03728 0 +OP4 E03729 0 +OP4 E0372A 0 +OP4 E0372B 0 +OP4 E0372C 0 +OP4 E0372D 0 +OP4 E0372E 0 +OP4 E0372F 0 +OP4 E03730 0 +OP4 E03731 0 +OP4 E03732 0 +OP4 E03733 0 +OP4 E03734 0 +OP4 E03735 0 +OP4 E03736 0 +OP4 E03737 0 +OP4 E03738 0 +OP4 E03739 0 +OP4 E0373A 0 +OP4 E0373B 0 +OP4 E0373C 0 +OP4 E0373D 0 +OP4 E0373E 0 +OP4 E0373F 0 +OP4 E03740 0 +OP4 E03741 0 +OP4 E03742 0 +OP4 E03743 0 +OP4 E03744 0 +OP4 E03745 0 +OP4 E03746 0 +OP4 E03747 0 +OP4 E03748 0 +OP4 E03749 0 +OP4 E0374A 0 +OP4 E0374B 0 +OP4 E0374C 0 +OP4 E0374D 0 +OP4 E0374E 0 +OP4 E0374F 0 +OP4 E03750 0 +OP4 E03751 0 +OP4 E03752 0 +OP4 E03753 0 +OP4 E03754 0 +OP4 E03755 0 +OP4 E03756 0 +OP4 E03757 0 +OP4 E03758 0 +OP4 E03759 0 +OP4 E0375A 0 +OP4 E0375B 0 +OP4 E0375C 0 +OP4 E0375D 0 +OP4 E0375E 0 +OP4 E0375F 0 +OP4 E03760 0 +OP4 E03761 0 +OP4 E03762 0 +OP4 E03763 0 +OP4 E03764 0 +OP4 E03765 0 +OP4 E03766 0 +OP4 E03767 0 +OP4 E03768 0 +OP4 E03769 0 +OP4 E0376A 0 +OP4 E0376B 0 +OP4 E0376C 0 +OP4 E0376D 0 +OP4 E0376E 0 +OP4 E0376F 0 +OP4 E03770 0 +OP4 E03771 0 +OP4 E03772 0 +OP4 E03773 0 +OP4 E03774 0 +OP4 E03775 0 +OP4 E03776 0 +OP4 E03777 0 +OP4 E03778 0 +OP4 E03779 0 +OP4 E0377A 0 +OP4 E0377B 0 +OP4 E0377C 0 +OP4 E0377D 0 +OP4 E0377E 0 +OP4 E0377F 0 +OP4 E03780 0 +OP4 E03781 0 +OP4 E03782 0 +OP4 E03783 0 +OP4 E03784 0 +OP4 E03785 0 +OP4 E03786 0 +OP4 E03787 0 +OP4 E03788 0 +OP4 E03789 0 +OP4 E0378A 0 +OP4 E0378B 0 +OP4 E0378C 0 +OP4 E0378D 0 +OP4 E0378E 0 +OP4 E0378F 0 +OP4 E03790 0 +OP4 E03791 0 +OP4 E03792 0 +OP4 E03793 0 +OP4 E03794 0 +OP4 E03795 0 +OP4 E03796 0 +OP4 E03797 0 +OP4 E03798 0 +OP4 E03799 0 +OP4 E0379A 0 +OP4 E0379B 0 +OP4 E0379C 0 +OP4 E0379D 0 +OP4 E0379E 0 +OP4 E0379F 0 +OP4 E037A0 0 +OP4 E037A1 0 +OP4 E037A2 0 +OP4 E037A3 0 +OP4 E037A4 0 +OP4 E037A5 0 +OP4 E037A6 0 +OP4 E037A7 0 +OP4 E037A8 0 +OP4 E037A9 0 +OP4 E037AA 0 +OP4 E037AB 0 +OP4 E037AC 0 +OP4 E037AD 0 +OP4 E037AE 0 +OP4 E037AF 0 +OP4 E037B0 0 +OP4 E037B1 0 +OP4 E037B2 0 +OP4 E037B3 0 +OP4 E037B4 0 +OP4 E037B5 0 +OP4 E037B6 0 +OP4 E037B7 0 +OP4 E037B8 0 +OP4 E037B9 0 +OP4 E037BA 0 +OP4 E037BB 0 +OP4 E037BC 0 +OP4 E037BD 0 +OP4 E037BE 0 +OP4 E037BF 0 +OP4 E037C0 0 +OP4 E037C1 0 +OP4 E037C2 0 +OP4 E037C3 0 +OP4 E037C4 0 +OP4 E037C5 0 +OP4 E037C6 0 +OP4 E037C7 0 +OP4 E037C8 0 +OP4 E037C9 0 +OP4 E037CA 0 +OP4 E037CB 0 +OP4 E037CC 0 +OP4 E037CD 0 +OP4 E037CE 0 +OP4 E037CF 0 +OP4 E037D0 0 +OP4 E037D1 0 +OP4 E037D2 0 +OP4 E037D3 0 +OP4 E037D4 0 +OP4 E037D5 0 +OP4 E037D6 0 +OP4 E037D7 0 +OP4 E037D8 0 +OP4 E037D9 0 +OP4 E037DA 0 +OP4 E037DB 0 +OP4 E037DC 0 +OP4 E037DD 0 +OP4 E037DE 0 +OP4 E037DF 0 +OP4 E037E0 0 +OP4 E037E1 0 +OP4 E037E2 0 +OP4 E037E3 0 +OP4 E037E4 0 +OP4 E037E5 0 +OP4 E037E6 0 +OP4 E037E7 0 +OP4 E037E8 0 +OP4 E037E9 0 +OP4 E037EA 0 +OP4 E037EB 0 +OP4 E037EC 0 +OP4 E037ED 0 +OP4 E037EE 0 +OP4 E037EF 0 +OP4 E037F0 0 +OP4 E037F1 0 +OP4 E037F2 0 +OP4 E037F3 0 +OP4 E037F4 0 +OP4 E037F5 0 +OP4 E037F6 0 +OP4 E037F7 0 +OP4 E037F8 0 +OP4 E037F9 0 +OP4 E037FA 0 +OP4 E037FB 0 +OP4 E037FC 0 +OP4 E037FD 0 +OP4 E037FE 0 +OP4 E037FF 0 +OP4 E03800 0 +OP4 E03801 0 +OP4 E03802 0 +OP4 E03803 0 +OP4 E03804 0 +OP4 E03805 0 +OP4 E03806 0 +OP4 E03807 0 +OP4 E03808 0 +OP4 E03809 0 +OP4 E0380A 0 +OP4 E0380B 0 +OP4 E0380C 0 +OP4 E0380D 0 +OP4 E0380E 0 +OP4 E0380F 0 +OP4 E03810 0 +OP4 E03811 0 +OP4 E03812 0 +OP4 E03813 0 +OP4 E03814 0 +OP4 E03815 0 +OP4 E03816 0 +OP4 E03817 0 +OP4 E03818 0 +OP4 E03819 0 +OP4 E0381A 0 +OP4 E0381B 0 +OP4 E0381C 0 +OP4 E0381D 0 +OP4 E0381E 0 +OP4 E0381F 0 +OP4 E03820 0 +OP4 E03821 0 +OP4 E03822 0 +OP4 E03823 0 +OP4 E03824 0 +OP4 E03825 0 +OP4 E03826 0 +OP4 E03827 0 +OP4 E03828 0 +OP4 E03829 0 +OP4 E0382A 0 +OP4 E0382B 0 +OP4 E0382C 0 +OP4 E0382D 0 +OP4 E0382E 0 +OP4 E0382F 0 +OP4 E03830 0 +OP4 E03831 0 +OP4 E03832 0 +OP4 E03833 0 +OP4 E03834 0 +OP4 E03835 0 +OP4 E03836 0 +OP4 E03837 0 +OP4 E03838 0 +OP4 E03839 0 +OP4 E0383A 0 +OP4 E0383B 0 +OP4 E0383C 0 +OP4 E0383D 0 +OP4 E0383E 0 +OP4 E0383F 0 +OP4 E03840 0 +OP4 E03841 0 +OP4 E03842 0 +OP4 E03843 0 +OP4 E03844 0 +OP4 E03845 0 +OP4 E03846 0 +OP4 E03847 0 +OP4 E03848 0 +OP4 E03849 0 +OP4 E0384A 0 +OP4 E0384B 0 +OP4 E0384C 0 +OP4 E0384D 0 +OP4 E0384E 0 +OP4 E0384F 0 +OP4 E03850 0 +OP4 E03851 0 +OP4 E03852 0 +OP4 E03853 0 +OP4 E03854 0 +OP4 E03855 0 +OP4 E03856 0 +OP4 E03857 0 +OP4 E03858 0 +OP4 E03859 0 +OP4 E0385A 0 +OP4 E0385B 0 +OP4 E0385C 0 +OP4 E0385D 0 +OP4 E0385E 0 +OP4 E0385F 0 +OP4 E03860 0 +OP4 E03861 0 +OP4 E03862 0 +OP4 E03863 0 +OP4 E03864 0 +OP4 E03865 0 +OP4 E03866 0 +OP4 E03867 0 +OP4 E03868 0 +OP4 E03869 0 +OP4 E0386A 0 +OP4 E0386B 0 +OP4 E0386C 0 +OP4 E0386D 0 +OP4 E0386E 0 +OP4 E0386F 0 +OP4 E03870 0 +OP4 E03871 0 +OP4 E03872 0 +OP4 E03873 0 +OP4 E03874 0 +OP4 E03875 0 +OP4 E03876 0 +OP4 E03877 0 +OP4 E03878 0 +OP4 E03879 0 +OP4 E0387A 0 +OP4 E0387B 0 +OP4 E0387C 0 +OP4 E0387D 0 +OP4 E0387E 0 +OP4 E0387F 0 +OP4 E03880 0 +OP4 E03881 0 +OP4 E03882 0 +OP4 E03883 0 +OP4 E03884 0 +OP4 E03885 0 +OP4 E03886 0 +OP4 E03887 0 +OP4 E03888 0 +OP4 E03889 0 +OP4 E0388A 0 +OP4 E0388B 0 +OP4 E0388C 0 +OP4 E0388D 0 +OP4 E0388E 0 +OP4 E0388F 0 +OP4 E03890 0 +OP4 E03891 0 +OP4 E03892 0 +OP4 E03893 0 +OP4 E03894 0 +OP4 E03895 0 +OP4 E03896 0 +OP4 E03897 0 +OP4 E03898 0 +OP4 E03899 0 +OP4 E0389A 0 +OP4 E0389B 0 +OP4 E0389C 0 +OP4 E0389D 0 +OP4 E0389E 0 +OP4 E0389F 0 +OP4 E038A0 0 +OP4 E038A1 0 +OP4 E038A2 0 +OP4 E038A3 0 +OP4 E038A4 0 +OP4 E038A5 0 +OP4 E038A6 0 +OP4 E038A7 0 +OP4 E038A8 0 +OP4 E038A9 0 +OP4 E038AA 0 +OP4 E038AB 0 +OP4 E038AC 0 +OP4 E038AD 0 +OP4 E038AE 0 +OP4 E038AF 0 +OP4 E038B0 0 +OP4 E038B1 0 +OP4 E038B2 0 +OP4 E038B3 0 +OP4 E038B4 0 +OP4 E038B5 0 +OP4 E038B6 0 +OP4 E038B7 0 +OP4 E038B8 0 +OP4 E038B9 0 +OP4 E038BA 0 +OP4 E038BB 0 +OP4 E038BC 0 +OP4 E038BD 0 +OP4 E038BE 0 +OP4 E038BF 0 +OP4 E038C0 0 +OP4 E038C1 0 +OP4 E038C2 0 +OP4 E038C3 0 +OP4 E038C4 0 +OP4 E038C5 0 +OP4 E038C6 0 +OP4 E038C7 0 +OP4 E038C8 0 +OP4 E038C9 0 +OP4 E038CA 0 +OP4 E038CB 0 +OP4 E038CC 0 +OP4 E038CD 0 +OP4 E038CE 0 +OP4 E038CF 0 +OP4 E038D0 0 +OP4 E038D1 0 +OP4 E038D2 0 +OP4 E038D3 0 +OP4 E038D4 0 +OP4 E038D5 0 +OP4 E038D6 0 +OP4 E038D7 0 +OP4 E038D8 0 +OP4 E038D9 0 +OP4 E038DA 0 +OP4 E038DB 0 +OP4 E038DC 0 +OP4 E038DD 0 +OP4 E038DE 0 +OP4 E038DF 0 +OP4 E038E0 0 +OP4 E038E1 0 +OP4 E038E2 0 +OP4 E038E3 0 +OP4 E038E4 0 +OP4 E038E5 0 +OP4 E038E6 0 +OP4 E038E7 0 +OP4 E038E8 0 +OP4 E038E9 0 +OP4 E038EA 0 +OP4 E038EB 0 +OP4 E038EC 0 +OP4 E038ED 0 +OP4 E038EE 0 +OP4 E038EF 0 +OP4 E038F0 0 +OP4 E038F1 0 +OP4 E038F2 0 +OP4 E038F3 0 +OP4 E038F4 0 +OP4 E038F5 0 +OP4 E038F6 0 +OP4 E038F7 0 +OP4 E038F8 0 +OP4 E038F9 0 +OP4 E038FA 0 +OP4 E038FB 0 +OP4 E038FC 0 +OP4 E038FD 0 +OP4 E038FE 0 +OP4 E038FF 0 +OP4 E03900 0 +OP4 E03901 0 +OP4 E03902 0 +OP4 E03903 0 +OP4 E03904 0 +OP4 E03905 0 +OP4 E03906 0 +OP4 E03907 0 +OP4 E03908 0 +OP4 E03909 0 +OP4 E0390A 0 +OP4 E0390B 0 +OP4 E0390C 0 +OP4 E0390D 0 +OP4 E0390E 0 +OP4 E0390F 0 +OP4 E03910 0 +OP4 E03911 0 +OP4 E03912 0 +OP4 E03913 0 +OP4 E03914 0 +OP4 E03915 0 +OP4 E03916 0 +OP4 E03917 0 +OP4 E03918 0 +OP4 E03919 0 +OP4 E0391A 0 +OP4 E0391B 0 +OP4 E0391C 0 +OP4 E0391D 0 +OP4 E0391E 0 +OP4 E0391F 0 +OP4 E03920 0 +OP4 E03921 0 +OP4 E03922 0 +OP4 E03923 0 +OP4 E03924 0 +OP4 E03925 0 +OP4 E03926 0 +OP4 E03927 0 +OP4 E03928 0 +OP4 E03929 0 +OP4 E0392A 0 +OP4 E0392B 0 +OP4 E0392C 0 +OP4 E0392D 0 +OP4 E0392E 0 +OP4 E0392F 0 +OP4 E03930 0 +OP4 E03931 0 +OP4 E03932 0 +OP4 E03933 0 +OP4 E03934 0 +OP4 E03935 0 +OP4 E03936 0 +OP4 E03937 0 +OP4 E03938 0 +OP4 E03939 0 +OP4 E0393A 0 +OP4 E0393B 0 +OP4 E0393C 0 +OP4 E0393D 0 +OP4 E0393E 0 +OP4 E0393F 0 +OP4 E03940 0 +OP4 E03941 0 +OP4 E03942 0 +OP4 E03943 0 +OP4 E03944 0 +OP4 E03945 0 +OP4 E03946 0 +OP4 E03947 0 +OP4 E03948 0 +OP4 E03949 0 +OP4 E0394A 0 +OP4 E0394B 0 +OP4 E0394C 0 +OP4 E0394D 0 +OP4 E0394E 0 +OP4 E0394F 0 +OP4 E03950 0 +OP4 E03951 0 +OP4 E03952 0 +OP4 E03953 0 +OP4 E03954 0 +OP4 E03955 0 +OP4 E03956 0 +OP4 E03957 0 +OP4 E03958 0 +OP4 E03959 0 +OP4 E0395A 0 +OP4 E0395B 0 +OP4 E0395C 0 +OP4 E0395D 0 +OP4 E0395E 0 +OP4 E0395F 0 +OP4 E03960 0 +OP4 E03961 0 +OP4 E03962 0 +OP4 E03963 0 +OP4 E03964 0 +OP4 E03965 0 +OP4 E03966 0 +OP4 E03967 0 +OP4 E03968 0 +OP4 E03969 0 +OP4 E0396A 0 +OP4 E0396B 0 +OP4 E0396C 0 +OP4 E0396D 0 +OP4 E0396E 0 +OP4 E0396F 0 +OP4 E03970 0 +OP4 E03971 0 +OP4 E03972 0 +OP4 E03973 0 +OP4 E03974 0 +OP4 E03975 0 +OP4 E03976 0 +OP4 E03977 0 +OP4 E03978 0 +OP4 E03979 0 +OP4 E0397A 0 +OP4 E0397B 0 +OP4 E0397C 0 +OP4 E0397D 0 +OP4 E0397E 0 +OP4 E0397F 0 +OP4 E03980 0 +OP4 E03981 0 +OP4 E03982 0 +OP4 E03983 0 +OP4 E03984 0 +OP4 E03985 0 +OP4 E03986 0 +OP4 E03987 0 +OP4 E03988 0 +OP4 E03989 0 +OP4 E0398A 0 +OP4 E0398B 0 +OP4 E0398C 0 +OP4 E0398D 0 +OP4 E0398E 0 +OP4 E0398F 0 +OP4 E03990 0 +OP4 E03991 0 +OP4 E03992 0 +OP4 E03993 0 +OP4 E03994 0 +OP4 E03995 0 +OP4 E03996 0 +OP4 E03997 0 +OP4 E03998 0 +OP4 E03999 0 +OP4 E0399A 0 +OP4 E0399B 0 +OP4 E0399C 0 +OP4 E0399D 0 +OP4 E0399E 0 +OP4 E0399F 0 +OP4 E039A0 0 +OP4 E039A1 0 +OP4 E039A2 0 +OP4 E039A3 0 +OP4 E039A4 0 +OP4 E039A5 0 +OP4 E039A6 0 +OP4 E039A7 0 +OP4 E039A8 0 +OP4 E039A9 0 +OP4 E039AA 0 +OP4 E039AB 0 +OP4 E039AC 0 +OP4 E039AD 0 +OP4 E039AE 0 +OP4 E039AF 0 +OP4 E039B0 0 +OP4 E039B1 0 +OP4 E039B2 0 +OP4 E039B3 0 +OP4 E039B4 0 +OP4 E039B5 0 +OP4 E039B6 0 +OP4 E039B7 0 +OP4 E039B8 0 +OP4 E039B9 0 +OP4 E039BA 0 +OP4 E039BB 0 +OP4 E039BC 0 +OP4 E039BD 0 +OP4 E039BE 0 +OP4 E039BF 0 +OP4 E039C0 0 +OP4 E039C1 0 +OP4 E039C2 0 +OP4 E039C3 0 +OP4 E039C4 0 +OP4 E039C5 0 +OP4 E039C6 0 +OP4 E039C7 0 +OP4 E039C8 0 +OP4 E039C9 0 +OP4 E039CA 0 +OP4 E039CB 0 +OP4 E039CC 0 +OP4 E039CD 0 +OP4 E039CE 0 +OP4 E039CF 0 +OP4 E039D0 0 +OP4 E039D1 0 +OP4 E039D2 0 +OP4 E039D3 0 +OP4 E039D4 0 +OP4 E039D5 0 +OP4 E039D6 0 +OP4 E039D7 0 +OP4 E039D8 0 +OP4 E039D9 0 +OP4 E039DA 0 +OP4 E039DB 0 +OP4 E039DC 0 +OP4 E039DD 0 +OP4 E039DE 0 +OP4 E039DF 0 +OP4 E039E0 0 +OP4 E039E1 0 +OP4 E039E2 0 +OP4 E039E3 0 +OP4 E039E4 0 +OP4 E039E5 0 +OP4 E039E6 0 +OP4 E039E7 0 +OP4 E039E8 0 +OP4 E039E9 0 +OP4 E039EA 0 +OP4 E039EB 0 +OP4 E039EC 0 +OP4 E039ED 0 +OP4 E039EE 0 +OP4 E039EF 0 +OP4 E039F0 0 +OP4 E039F1 0 +OP4 E039F2 0 +OP4 E039F3 0 +OP4 E039F4 0 +OP4 E039F5 0 +OP4 E039F6 0 +OP4 E039F7 0 +OP4 E039F8 0 +OP4 E039F9 0 +OP4 E039FA 0 +OP4 E039FB 0 +OP4 E039FC 0 +OP4 E039FD 0 +OP4 E039FE 0 +OP4 E039FF 0 +OP4 E03A00 0 +OP4 E03A01 0 +OP4 E03A02 0 +OP4 E03A03 0 +OP4 E03A04 0 +OP4 E03A05 0 +OP4 E03A06 0 +OP4 E03A07 0 +OP4 E03A08 0 +OP4 E03A09 0 +OP4 E03A0A 0 +OP4 E03A0B 0 +OP4 E03A0C 0 +OP4 E03A0D 0 +OP4 E03A0E 0 +OP4 E03A0F 0 +OP4 E03A10 0 +OP4 E03A11 0 +OP4 E03A12 0 +OP4 E03A13 0 +OP4 E03A14 0 +OP4 E03A15 0 +OP4 E03A16 0 +OP4 E03A17 0 +OP4 E03A18 0 +OP4 E03A19 0 +OP4 E03A1A 0 +OP4 E03A1B 0 +OP4 E03A1C 0 +OP4 E03A1D 0 +OP4 E03A1E 0 +OP4 E03A1F 0 +OP4 E03A20 0 +OP4 E03A21 0 +OP4 E03A22 0 +OP4 E03A23 0 +OP4 E03A24 0 +OP4 E03A25 0 +OP4 E03A26 0 +OP4 E03A27 0 +OP4 E03A28 0 +OP4 E03A29 0 +OP4 E03A2A 0 +OP4 E03A2B 0 +OP4 E03A2C 0 +OP4 E03A2D 0 +OP4 E03A2E 0 +OP4 E03A2F 0 +OP4 E03A30 0 +OP4 E03A31 0 +OP4 E03A32 0 +OP4 E03A33 0 +OP4 E03A34 0 +OP4 E03A35 0 +OP4 E03A36 0 +OP4 E03A37 0 +OP4 E03A38 0 +OP4 E03A39 0 +OP4 E03A3A 0 +OP4 E03A3B 0 +OP4 E03A3C 0 +OP4 E03A3D 0 +OP4 E03A3E 0 +OP4 E03A3F 0 +OP4 E03A40 0 +OP4 E03A41 0 +OP4 E03A42 0 +OP4 E03A43 0 +OP4 E03A44 0 +OP4 E03A45 0 +OP4 E03A46 0 +OP4 E03A47 0 +OP4 E03A48 0 +OP4 E03A49 0 +OP4 E03A4A 0 +OP4 E03A4B 0 +OP4 E03A4C 0 +OP4 E03A4D 0 +OP4 E03A4E 0 +OP4 E03A4F 0 +OP4 E03A50 0 +OP4 E03A51 0 +OP4 E03A52 0 +OP4 E03A53 0 +OP4 E03A54 0 +OP4 E03A55 0 +OP4 E03A56 0 +OP4 E03A57 0 +OP4 E03A58 0 +OP4 E03A59 0 +OP4 E03A5A 0 +OP4 E03A5B 0 +OP4 E03A5C 0 +OP4 E03A5D 0 +OP4 E03A5E 0 +OP4 E03A5F 0 +OP4 E03A60 0 +OP4 E03A61 0 +OP4 E03A62 0 +OP4 E03A63 0 +OP4 E03A64 0 +OP4 E03A65 0 +OP4 E03A66 0 +OP4 E03A67 0 +OP4 E03A68 0 +OP4 E03A69 0 +OP4 E03A6A 0 +OP4 E03A6B 0 +OP4 E03A6C 0 +OP4 E03A6D 0 +OP4 E03A6E 0 +OP4 E03A6F 0 +OP4 E03A70 0 +OP4 E03A71 0 +OP4 E03A72 0 +OP4 E03A73 0 +OP4 E03A74 0 +OP4 E03A75 0 +OP4 E03A76 0 +OP4 E03A77 0 +OP4 E03A78 0 +OP4 E03A79 0 +OP4 E03A7A 0 +OP4 E03A7B 0 +OP4 E03A7C 0 +OP4 E03A7D 0 +OP4 E03A7E 0 +OP4 E03A7F 0 +OP4 E03A80 0 +OP4 E03A81 0 +OP4 E03A82 0 +OP4 E03A83 0 +OP4 E03A84 0 +OP4 E03A85 0 +OP4 E03A86 0 +OP4 E03A87 0 +OP4 E03A88 0 +OP4 E03A89 0 +OP4 E03A8A 0 +OP4 E03A8B 0 +OP4 E03A8C 0 +OP4 E03A8D 0 +OP4 E03A8E 0 +OP4 E03A8F 0 +OP4 E03A90 0 +OP4 E03A91 0 +OP4 E03A92 0 +OP4 E03A93 0 +OP4 E03A94 0 +OP4 E03A95 0 +OP4 E03A96 0 +OP4 E03A97 0 +OP4 E03A98 0 +OP4 E03A99 0 +OP4 E03A9A 0 +OP4 E03A9B 0 +OP4 E03A9C 0 +OP4 E03A9D 0 +OP4 E03A9E 0 +OP4 E03A9F 0 +OP4 E03AA0 0 +OP4 E03AA1 0 +OP4 E03AA2 0 +OP4 E03AA3 0 +OP4 E03AA4 0 +OP4 E03AA5 0 +OP4 E03AA6 0 +OP4 E03AA7 0 +OP4 E03AA8 0 +OP4 E03AA9 0 +OP4 E03AAA 0 +OP4 E03AAB 0 +OP4 E03AAC 0 +OP4 E03AAD 0 +OP4 E03AAE 0 +OP4 E03AAF 0 +OP4 E03AB0 0 +OP4 E03AB1 0 +OP4 E03AB2 0 +OP4 E03AB3 0 +OP4 E03AB4 0 +OP4 E03AB5 0 +OP4 E03AB6 0 +OP4 E03AB7 0 +OP4 E03AB8 0 +OP4 E03AB9 0 +OP4 E03ABA 0 +OP4 E03ABB 0 +OP4 E03ABC 0 +OP4 E03ABD 0 +OP4 E03ABE 0 +OP4 E03ABF 0 +OP4 E03AC0 0 +OP4 E03AC1 0 +OP4 E03AC2 0 +OP4 E03AC3 0 +OP4 E03AC4 0 +OP4 E03AC5 0 +OP4 E03AC6 0 +OP4 E03AC7 0 +OP4 E03AC8 0 +OP4 E03AC9 0 +OP4 E03ACA 0 +OP4 E03ACB 0 +OP4 E03ACC 0 +OP4 E03ACD 0 +OP4 E03ACE 0 +OP4 E03ACF 0 +OP4 E03AD0 0 +OP4 E03AD1 0 +OP4 E03AD2 0 +OP4 E03AD3 0 +OP4 E03AD4 0 +OP4 E03AD5 0 +OP4 E03AD6 0 +OP4 E03AD7 0 +OP4 E03AD8 0 +OP4 E03AD9 0 +OP4 E03ADA 0 +OP4 E03ADB 0 +OP4 E03ADC 0 +OP4 E03ADD 0 +OP4 E03ADE 0 +OP4 E03ADF 0 +OP4 E03AE0 0 +OP4 E03AE1 0 +OP4 E03AE2 0 +OP4 E03AE3 0 +OP4 E03AE4 0 +OP4 E03AE5 0 +OP4 E03AE6 0 +OP4 E03AE7 0 +OP4 E03AE8 0 +OP4 E03AE9 0 +OP4 E03AEA 0 +OP4 E03AEB 0 +OP4 E03AEC 0 +OP4 E03AED 0 +OP4 E03AEE 0 +OP4 E03AEF 0 +OP4 E03AF0 0 +OP4 E03AF1 0 +OP4 E03AF2 0 +OP4 E03AF3 0 +OP4 E03AF4 0 +OP4 E03AF5 0 +OP4 E03AF6 0 +OP4 E03AF7 0 +OP4 E03AF8 0 +OP4 E03AF9 0 +OP4 E03AFA 0 +OP4 E03AFB 0 +OP4 E03AFC 0 +OP4 E03AFD 0 +OP4 E03AFE 0 +OP4 E03AFF 0 +OP4 E03B00 0 +OP4 E03B01 0 +OP4 E03B02 0 +OP4 E03B03 0 +OP4 E03B04 0 +OP4 E03B05 0 +OP4 E03B06 0 +OP4 E03B07 0 +OP4 E03B08 0 +OP4 E03B09 0 +OP4 E03B0A 0 +OP4 E03B0B 0 +OP4 E03B0C 0 +OP4 E03B0D 0 +OP4 E03B0E 0 +OP4 E03B0F 0 +OP4 E03B10 0 +OP4 E03B11 0 +OP4 E03B12 0 +OP4 E03B13 0 +OP4 E03B14 0 +OP4 E03B15 0 +OP4 E03B16 0 +OP4 E03B17 0 +OP4 E03B18 0 +OP4 E03B19 0 +OP4 E03B1A 0 +OP4 E03B1B 0 +OP4 E03B1C 0 +OP4 E03B1D 0 +OP4 E03B1E 0 +OP4 E03B1F 0 +OP4 E03B20 0 +OP4 E03B21 0 +OP4 E03B22 0 +OP4 E03B23 0 +OP4 E03B24 0 +OP4 E03B25 0 +OP4 E03B26 0 +OP4 E03B27 0 +OP4 E03B28 0 +OP4 E03B29 0 +OP4 E03B2A 0 +OP4 E03B2B 0 +OP4 E03B2C 0 +OP4 E03B2D 0 +OP4 E03B2E 0 +OP4 E03B2F 0 +OP4 E03B30 0 +OP4 E03B31 0 +OP4 E03B32 0 +OP4 E03B33 0 +OP4 E03B34 0 +OP4 E03B35 0 +OP4 E03B36 0 +OP4 E03B37 0 +OP4 E03B38 0 +OP4 E03B39 0 +OP4 E03B3A 0 +OP4 E03B3B 0 +OP4 E03B3C 0 +OP4 E03B3D 0 +OP4 E03B3E 0 +OP4 E03B3F 0 +OP4 E03B40 0 +OP4 E03B41 0 +OP4 E03B42 0 +OP4 E03B43 0 +OP4 E03B44 0 +OP4 E03B45 0 +OP4 E03B46 0 +OP4 E03B47 0 +OP4 E03B48 0 +OP4 E03B49 0 +OP4 E03B4A 0 +OP4 E03B4B 0 +OP4 E03B4C 0 +OP4 E03B4D 0 +OP4 E03B4E 0 +OP4 E03B4F 0 +OP4 E03B50 0 +OP4 E03B51 0 +OP4 E03B52 0 +OP4 E03B53 0 +OP4 E03B54 0 +OP4 E03B55 0 +OP4 E03B56 0 +OP4 E03B57 0 +OP4 E03B58 0 +OP4 E03B59 0 +OP4 E03B5A 0 +OP4 E03B5B 0 +OP4 E03B5C 0 +OP4 E03B5D 0 +OP4 E03B5E 0 +OP4 E03B5F 0 +OP4 E03B60 0 +OP4 E03B61 0 +OP4 E03B62 0 +OP4 E03B63 0 +OP4 E03B64 0 +OP4 E03B65 0 +OP4 E03B66 0 +OP4 E03B67 0 +OP4 E03B68 0 +OP4 E03B69 0 +OP4 E03B6A 0 +OP4 E03B6B 0 +OP4 E03B6C 0 +OP4 E03B6D 0 +OP4 E03B6E 0 +OP4 E03B6F 0 +OP4 E03B70 0 +OP4 E03B71 0 +OP4 E03B72 0 +OP4 E03B73 0 +OP4 E03B74 0 +OP4 E03B75 0 +OP4 E03B76 0 +OP4 E03B77 0 +OP4 E03B78 0 +OP4 E03B79 0 +OP4 E03B7A 0 +OP4 E03B7B 0 +OP4 E03B7C 0 +OP4 E03B7D 0 +OP4 E03B7E 0 +OP4 E03B7F 0 +OP4 E03B80 0 +OP4 E03B81 0 +OP4 E03B82 0 +OP4 E03B83 0 +OP4 E03B84 0 +OP4 E03B85 0 +OP4 E03B86 0 +OP4 E03B87 0 +OP4 E03B88 0 +OP4 E03B89 0 +OP4 E03B8A 0 +OP4 E03B8B 0 +OP4 E03B8C 0 +OP4 E03B8D 0 +OP4 E03B8E 0 +OP4 E03B8F 0 +OP4 E03B90 0 +OP4 E03B91 0 +OP4 E03B92 0 +OP4 E03B93 0 +OP4 E03B94 0 +OP4 E03B95 0 +OP4 E03B96 0 +OP4 E03B97 0 +OP4 E03B98 0 +OP4 E03B99 0 +OP4 E03B9A 0 +OP4 E03B9B 0 +OP4 E03B9C 0 +OP4 E03B9D 0 +OP4 E03B9E 0 +OP4 E03B9F 0 +OP4 E03BA0 0 +OP4 E03BA1 0 +OP4 E03BA2 0 +OP4 E03BA3 0 +OP4 E03BA4 0 +OP4 E03BA5 0 +OP4 E03BA6 0 +OP4 E03BA7 0 +OP4 E03BA8 0 +OP4 E03BA9 0 +OP4 E03BAA 0 +OP4 E03BAB 0 +OP4 E03BAC 0 +OP4 E03BAD 0 +OP4 E03BAE 0 +OP4 E03BAF 0 +OP4 E03BB0 0 +OP4 E03BB1 0 +OP4 E03BB2 0 +OP4 E03BB3 0 +OP4 E03BB4 0 +OP4 E03BB5 0 +OP4 E03BB6 0 +OP4 E03BB7 0 +OP4 E03BB8 0 +OP4 E03BB9 0 +OP4 E03BBA 0 +OP4 E03BBB 0 +OP4 E03BBC 0 +OP4 E03BBD 0 +OP4 E03BBE 0 +OP4 E03BBF 0 +OP4 E03BC0 0 +OP4 E03BC1 0 +OP4 E03BC2 0 +OP4 E03BC3 0 +OP4 E03BC4 0 +OP4 E03BC5 0 +OP4 E03BC6 0 +OP4 E03BC7 0 +OP4 E03BC8 0 +OP4 E03BC9 0 +OP4 E03BCA 0 +OP4 E03BCB 0 +OP4 E03BCC 0 +OP4 E03BCD 0 +OP4 E03BCE 0 +OP4 E03BCF 0 +OP4 E03BD0 0 +OP4 E03BD1 0 +OP4 E03BD2 0 +OP4 E03BD3 0 +OP4 E03BD4 0 +OP4 E03BD5 0 +OP4 E03BD6 0 +OP4 E03BD7 0 +OP4 E03BD8 0 +OP4 E03BD9 0 +OP4 E03BDA 0 +OP4 E03BDB 0 +OP4 E03BDC 0 +OP4 E03BDD 0 +OP4 E03BDE 0 +OP4 E03BDF 0 +OP4 E03BE0 0 +OP4 E03BE1 0 +OP4 E03BE2 0 +OP4 E03BE3 0 +OP4 E03BE4 0 +OP4 E03BE5 0 +OP4 E03BE6 0 +OP4 E03BE7 0 +OP4 E03BE8 0 +OP4 E03BE9 0 +OP4 E03BEA 0 +OP4 E03BEB 0 +OP4 E03BEC 0 +OP4 E03BED 0 +OP4 E03BEE 0 +OP4 E03BEF 0 +OP4 E03BF0 0 +OP4 E03BF1 0 +OP4 E03BF2 0 +OP4 E03BF3 0 +OP4 E03BF4 0 +OP4 E03BF5 0 +OP4 E03BF6 0 +OP4 E03BF7 0 +OP4 E03BF8 0 +OP4 E03BF9 0 +OP4 E03BFA 0 +OP4 E03BFB 0 +OP4 E03BFC 0 +OP4 E03BFD 0 +OP4 E03BFE 0 +OP4 E03BFF 0 +OP4 E03C00 0 +OP4 E03C01 0 +OP4 E03C02 0 +OP4 E03C03 0 +OP4 E03C04 0 +OP4 E03C05 0 +OP4 E03C06 0 +OP4 E03C07 0 +OP4 E03C08 0 +OP4 E03C09 0 +OP4 E03C0A 0 +OP4 E03C0B 0 +OP4 E03C0C 0 +OP4 E03C0D 0 +OP4 E03C0E 0 +OP4 E03C0F 0 +OP4 E03C10 0 +OP4 E03C11 0 +OP4 E03C12 0 +OP4 E03C13 0 +OP4 E03C14 0 +OP4 E03C15 0 +OP4 E03C16 0 +OP4 E03C17 0 +OP4 E03C18 0 +OP4 E03C19 0 +OP4 E03C1A 0 +OP4 E03C1B 0 +OP4 E03C1C 0 +OP4 E03C1D 0 +OP4 E03C1E 0 +OP4 E03C1F 0 +OP4 E03C20 0 +OP4 E03C21 0 +OP4 E03C22 0 +OP4 E03C23 0 +OP4 E03C24 0 +OP4 E03C25 0 +OP4 E03C26 0 +OP4 E03C27 0 +OP4 E03C28 0 +OP4 E03C29 0 +OP4 E03C2A 0 +OP4 E03C2B 0 +OP4 E03C2C 0 +OP4 E03C2D 0 +OP4 E03C2E 0 +OP4 E03C2F 0 +OP4 E03C30 0 +OP4 E03C31 0 +OP4 E03C32 0 +OP4 E03C33 0 +OP4 E03C34 0 +OP4 E03C35 0 +OP4 E03C36 0 +OP4 E03C37 0 +OP4 E03C38 0 +OP4 E03C39 0 +OP4 E03C3A 0 +OP4 E03C3B 0 +OP4 E03C3C 0 +OP4 E03C3D 0 +OP4 E03C3E 0 +OP4 E03C3F 0 +OP4 E03C40 0 +OP4 E03C41 0 +OP4 E03C42 0 +OP4 E03C43 0 +OP4 E03C44 0 +OP4 E03C45 0 +OP4 E03C46 0 +OP4 E03C47 0 +OP4 E03C48 0 +OP4 E03C49 0 +OP4 E03C4A 0 +OP4 E03C4B 0 +OP4 E03C4C 0 +OP4 E03C4D 0 +OP4 E03C4E 0 +OP4 E03C4F 0 +OP4 E03C50 0 +OP4 E03C51 0 +OP4 E03C52 0 +OP4 E03C53 0 +OP4 E03C54 0 +OP4 E03C55 0 +OP4 E03C56 0 +OP4 E03C57 0 +OP4 E03C58 0 +OP4 E03C59 0 +OP4 E03C5A 0 +OP4 E03C5B 0 +OP4 E03C5C 0 +OP4 E03C5D 0 +OP4 E03C5E 0 +OP4 E03C5F 0 +OP4 E03C60 0 +OP4 E03C61 0 +OP4 E03C62 0 +OP4 E03C63 0 +OP4 E03C64 0 +OP4 E03C65 0 +OP4 E03C66 0 +OP4 E03C67 0 +OP4 E03C68 0 +OP4 E03C69 0 +OP4 E03C6A 0 +OP4 E03C6B 0 +OP4 E03C6C 0 +OP4 E03C6D 0 +OP4 E03C6E 0 +OP4 E03C6F 0 +OP4 E03C70 0 +OP4 E03C71 0 +OP4 E03C72 0 +OP4 E03C73 0 +OP4 E03C74 0 +OP4 E03C75 0 +OP4 E03C76 0 +OP4 E03C77 0 +OP4 E03C78 0 +OP4 E03C79 0 +OP4 E03C7A 0 +OP4 E03C7B 0 +OP4 E03C7C 0 +OP4 E03C7D 0 +OP4 E03C7E 0 +OP4 E03C7F 0 +OP4 E03C80 0 +OP4 E03C81 0 +OP4 E03C82 0 +OP4 E03C83 0 +OP4 E03C84 0 +OP4 E03C85 0 +OP4 E03C86 0 +OP4 E03C87 0 +OP4 E03C88 0 +OP4 E03C89 0 +OP4 E03C8A 0 +OP4 E03C8B 0 +OP4 E03C8C 0 +OP4 E03C8D 0 +OP4 E03C8E 0 +OP4 E03C8F 0 +OP4 E03C90 0 +OP4 E03C91 0 +OP4 E03C92 0 +OP4 E03C93 0 +OP4 E03C94 0 +OP4 E03C95 0 +OP4 E03C96 0 +OP4 E03C97 0 +OP4 E03C98 0 +OP4 E03C99 0 +OP4 E03C9A 0 +OP4 E03C9B 0 +OP4 E03C9C 0 +OP4 E03C9D 0 +OP4 E03C9E 0 +OP4 E03C9F 0 +OP4 E03CA0 0 +OP4 E03CA1 0 +OP4 E03CA2 0 +OP4 E03CA3 0 +OP4 E03CA4 0 +OP4 E03CA5 0 +OP4 E03CA6 0 +OP4 E03CA7 0 +OP4 E03CA8 0 +OP4 E03CA9 0 +OP4 E03CAA 0 +OP4 E03CAB 0 +OP4 E03CAC 0 +OP4 E03CAD 0 +OP4 E03CAE 0 +OP4 E03CAF 0 +OP4 E03CB0 0 +OP4 E03CB1 0 +OP4 E03CB2 0 +OP4 E03CB3 0 +OP4 E03CB4 0 +OP4 E03CB5 0 +OP4 E03CB6 0 +OP4 E03CB7 0 +OP4 E03CB8 0 +OP4 E03CB9 0 +OP4 E03CBA 0 +OP4 E03CBB 0 +OP4 E03CBC 0 +OP4 E03CBD 0 +OP4 E03CBE 0 +OP4 E03CBF 0 +OP4 E03CC0 0 +OP4 E03CC1 0 +OP4 E03CC2 0 +OP4 E03CC3 0 +OP4 E03CC4 0 +OP4 E03CC5 0 +OP4 E03CC6 0 +OP4 E03CC7 0 +OP4 E03CC8 0 +OP4 E03CC9 0 +OP4 E03CCA 0 +OP4 E03CCB 0 +OP4 E03CCC 0 +OP4 E03CCD 0 +OP4 E03CCE 0 +OP4 E03CCF 0 +OP4 E03CD0 0 +OP4 E03CD1 0 +OP4 E03CD2 0 +OP4 E03CD3 0 +OP4 E03CD4 0 +OP4 E03CD5 0 +OP4 E03CD6 0 +OP4 E03CD7 0 +OP4 E03CD8 0 +OP4 E03CD9 0 +OP4 E03CDA 0 +OP4 E03CDB 0 +OP4 E03CDC 0 +OP4 E03CDD 0 +OP4 E03CDE 0 +OP4 E03CDF 0 +OP4 E03CE0 0 +OP4 E03CE1 0 +OP4 E03CE2 0 +OP4 E03CE3 0 +OP4 E03CE4 0 +OP4 E03CE5 0 +OP4 E03CE6 0 +OP4 E03CE7 0 +OP4 E03CE8 0 +OP4 E03CE9 0 +OP4 E03CEA 0 +OP4 E03CEB 0 +OP4 E03CEC 0 +OP4 E03CED 0 +OP4 E03CEE 0 +OP4 E03CEF 0 +OP4 E03CF0 0 +OP4 E03CF1 0 +OP4 E03CF2 0 +OP4 E03CF3 0 +OP4 E03CF4 0 +OP4 E03CF5 0 +OP4 E03CF6 0 +OP4 E03CF7 0 +OP4 E03CF8 0 +OP4 E03CF9 0 +OP4 E03CFA 0 +OP4 E03CFB 0 +OP4 E03CFC 0 +OP4 E03CFD 0 +OP4 E03CFE 0 +OP4 E03CFF 0 +OP4 E03D00 0 +OP4 E03D01 0 +OP4 E03D02 0 +OP4 E03D03 0 +OP4 E03D04 0 +OP4 E03D05 0 +OP4 E03D06 0 +OP4 E03D07 0 +OP4 E03D08 0 +OP4 E03D09 0 +OP4 E03D0A 0 +OP4 E03D0B 0 +OP4 E03D0C 0 +OP4 E03D0D 0 +OP4 E03D0E 0 +OP4 E03D0F 0 +OP4 E03D10 0 +OP4 E03D11 0 +OP4 E03D12 0 +OP4 E03D13 0 +OP4 E03D14 0 +OP4 E03D15 0 +OP4 E03D16 0 +OP4 E03D17 0 +OP4 E03D18 0 +OP4 E03D19 0 +OP4 E03D1A 0 +OP4 E03D1B 0 +OP4 E03D1C 0 +OP4 E03D1D 0 +OP4 E03D1E 0 +OP4 E03D1F 0 +OP4 E03D20 0 +OP4 E03D21 0 +OP4 E03D22 0 +OP4 E03D23 0 +OP4 E03D24 0 +OP4 E03D25 0 +OP4 E03D26 0 +OP4 E03D27 0 +OP4 E03D28 0 +OP4 E03D29 0 +OP4 E03D2A 0 +OP4 E03D2B 0 +OP4 E03D2C 0 +OP4 E03D2D 0 +OP4 E03D2E 0 +OP4 E03D2F 0 +OP4 E03D30 0 +OP4 E03D31 0 +OP4 E03D32 0 +OP4 E03D33 0 +OP4 E03D34 0 +OP4 E03D35 0 +OP4 E03D36 0 +OP4 E03D37 0 +OP4 E03D38 0 +OP4 E03D39 0 +OP4 E03D3A 0 +OP4 E03D3B 0 +OP4 E03D3C 0 +OP4 E03D3D 0 +OP4 E03D3E 0 +OP4 E03D3F 0 +OP4 E03D40 0 +OP4 E03D41 0 +OP4 E03D42 0 +OP4 E03D43 0 +OP4 E03D44 0 +OP4 E03D45 0 +OP4 E03D46 0 +OP4 E03D47 0 +OP4 E03D48 0 +OP4 E03D49 0 +OP4 E03D4A 0 +OP4 E03D4B 0 +OP4 E03D4C 0 +OP4 E03D4D 0 +OP4 E03D4E 0 +OP4 E03D4F 0 +OP4 E03D50 0 +OP4 E03D51 0 +OP4 E03D52 0 +OP4 E03D53 0 +OP4 E03D54 0 +OP4 E03D55 0 +OP4 E03D56 0 +OP4 E03D57 0 +OP4 E03D58 0 +OP4 E03D59 0 +OP4 E03D5A 0 +OP4 E03D5B 0 +OP4 E03D5C 0 +OP4 E03D5D 0 +OP4 E03D5E 0 +OP4 E03D5F 0 +OP4 E03D60 0 +OP4 E03D61 0 +OP4 E03D62 0 +OP4 E03D63 0 +OP4 E03D64 0 +OP4 E03D65 0 +OP4 E03D66 0 +OP4 E03D67 0 +OP4 E03D68 0 +OP4 E03D69 0 +OP4 E03D6A 0 +OP4 E03D6B 0 +OP4 E03D6C 0 +OP4 E03D6D 0 +OP4 E03D6E 0 +OP4 E03D6F 0 +OP4 E03D70 0 +OP4 E03D71 0 +OP4 E03D72 0 +OP4 E03D73 0 +OP4 E03D74 0 +OP4 E03D75 0 +OP4 E03D76 0 +OP4 E03D77 0 +OP4 E03D78 0 +OP4 E03D79 0 +OP4 E03D7A 0 +OP4 E03D7B 0 +OP4 E03D7C 0 +OP4 E03D7D 0 +OP4 E03D7E 0 +OP4 E03D7F 0 +OP4 E03D80 0 +OP4 E03D81 0 +OP4 E03D82 0 +OP4 E03D83 0 +OP4 E03D84 0 +OP4 E03D85 0 +OP4 E03D86 0 +OP4 E03D87 0 +OP4 E03D88 0 +OP4 E03D89 0 +OP4 E03D8A 0 +OP4 E03D8B 0 +OP4 E03D8C 0 +OP4 E03D8D 0 +OP4 E03D8E 0 +OP4 E03D8F 0 +OP4 E03D90 0 +OP4 E03D91 0 +OP4 E03D92 0 +OP4 E03D93 0 +OP4 E03D94 0 +OP4 E03D95 0 +OP4 E03D96 0 +OP4 E03D97 0 +OP4 E03D98 0 +OP4 E03D99 0 +OP4 E03D9A 0 +OP4 E03D9B 0 +OP4 E03D9C 0 +OP4 E03D9D 0 +OP4 E03D9E 0 +OP4 E03D9F 0 +OP4 E03DA0 0 +OP4 E03DA1 0 +OP4 E03DA2 0 +OP4 E03DA3 0 +OP4 E03DA4 0 +OP4 E03DA5 0 +OP4 E03DA6 0 +OP4 E03DA7 0 +OP4 E03DA8 0 +OP4 E03DA9 0 +OP4 E03DAA 0 +OP4 E03DAB 0 +OP4 E03DAC 0 +OP4 E03DAD 0 +OP4 E03DAE 0 +OP4 E03DAF 0 +OP4 E03DB0 0 +OP4 E03DB1 0 +OP4 E03DB2 0 +OP4 E03DB3 0 +OP4 E03DB4 0 +OP4 E03DB5 0 +OP4 E03DB6 0 +OP4 E03DB7 0 +OP4 E03DB8 0 +OP4 E03DB9 0 +OP4 E03DBA 0 +OP4 E03DBB 0 +OP4 E03DBC 0 +OP4 E03DBD 0 +OP4 E03DBE 0 +OP4 E03DBF 0 +OP4 E03DC0 0 +OP4 E03DC1 0 +OP4 E03DC2 0 +OP4 E03DC3 0 +OP4 E03DC4 0 diff --git a/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum4_itrace_irisc8.cfg.ext b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum4_itrace_irisc8.cfg.ext new file mode 100644 index 000000000000..0f40a4ae74f1 --- /dev/null +++ b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum4_itrace_irisc8.cfg.ext @@ -0,0 +1,15814 @@ +OP1 Spectrum4 +OP4 ITRACE0 0 +OP4 ITRACE1 0 +OP4 ITRACE2 0 +OP4 ITRACE3 0 +OP4 ITRACE4 0 +OP4 ITRACE5 0 +OP4 ITRACE6 0 +OP4 ITRACE7 0 +OP4 ITRACE8 1 +OP4 ITRACE9 0 +OP4 Main_PhyUC 0 +OP4 TILE0_ITRACE0 0 +OP4 TILE0_ITRACE1 0 +OP4 TILE0_ITRACE2 0 +OP4 TILE0_ITRACE3 0 +OP4 TILE0_ITRACE4 0 +OP4 TILE0_PhyUC 0 +OP4 TILE1_ITRACE0 0 +OP4 TILE1_ITRACE1 0 +OP4 TILE1_ITRACE2 0 +OP4 TILE1_ITRACE3 0 +OP4 TILE1_ITRACE4 0 +OP4 TILE1_PhyUC 0 +OP4 TILE2_ITRACE0 0 +OP4 TILE2_ITRACE1 0 +OP4 TILE2_ITRACE2 0 +OP4 TILE2_ITRACE3 0 +OP4 TILE2_ITRACE4 0 +OP4 TILE2_PhyUC 0 +OP4 TILE3_ITRACE0 0 +OP4 TILE3_ITRACE1 0 +OP4 TILE3_ITRACE2 0 +OP4 TILE3_ITRACE3 0 +OP4 TILE3_ITRACE4 0 +OP4 TILE3_PhyUC 0 +OP4 TILE4_ITRACE0 0 +OP4 TILE4_ITRACE1 0 +OP4 TILE4_ITRACE2 0 +OP4 TILE4_ITRACE3 0 +OP4 TILE4_ITRACE4 0 +OP4 TILE4_PhyUC 0 +OP4 TILE5_ITRACE0 0 +OP4 TILE5_ITRACE1 0 +OP4 TILE5_ITRACE2 0 +OP4 TILE5_ITRACE3 0 +OP4 TILE5_ITRACE4 0 +OP4 TILE5_PhyUC 0 +OP4 TILE6_ITRACE0 0 +OP4 TILE6_ITRACE1 0 +OP4 TILE6_ITRACE2 0 +OP4 TILE6_ITRACE3 0 +OP4 TILE6_ITRACE4 0 +OP4 TILE6_PhyUC 0 +OP4 TILE7_ITRACE0 0 +OP4 TILE7_ITRACE1 0 +OP4 TILE7_ITRACE2 0 +OP4 TILE7_ITRACE3 0 +OP4 TILE7_ITRACE4 0 +OP4 TILE7_PhyUC 0 +OP4 E0003B 0 +OP4 E0003C 0 +OP4 E0003D 0 +OP4 E0003E 0 +OP4 E0003F 0 +OP4 E00040 0 +OP4 E00041 0 +OP4 E00042 0 +OP4 E00043 0 +OP4 E00044 0 +OP4 E00045 0 +OP4 E00046 0 +OP4 E00047 0 +OP4 E00048 0 +OP4 E00049 0 +OP4 E0004A 0 +OP4 E0004B 0 +OP4 E0004C 0 +OP4 E0004D 0 +OP4 E0004E 0 +OP4 E0004F 0 +OP4 E00050 0 +OP4 E00051 0 +OP4 E00052 0 +OP4 E00053 0 +OP4 E00054 0 +OP4 E00055 0 +OP4 E00056 0 +OP4 E00057 0 +OP4 E00058 0 +OP4 E00059 0 +OP4 E0005A 0 +OP4 E0005B 0 +OP4 E0005C 0 +OP4 E0005D 0 +OP4 E0005E 0 +OP4 E0005F 0 +OP4 E00060 0 +OP4 E00061 0 +OP4 E00062 0 +OP4 E00063 0 +OP4 E00064 0 +OP4 E00065 0 +OP4 E00066 0 +OP4 E00067 0 +OP4 E00068 0 +OP4 E00069 0 +OP4 E0006A 0 +OP4 E0006B 0 +OP4 E0006C 0 +OP4 E0006D 0 +OP4 E0006E 0 +OP4 E0006F 0 +OP4 E00070 0 +OP4 E00071 0 +OP4 E00072 0 +OP4 E00073 0 +OP4 E00074 0 +OP4 E00075 0 +OP4 E00076 0 +OP4 E00077 0 +OP4 E00078 0 +OP4 E00079 0 +OP4 E0007A 0 +OP4 E0007B 0 +OP4 E0007C 0 +OP4 E0007D 0 +OP4 E0007E 0 +OP4 E0007F 0 +OP4 E00080 0 +OP4 E00081 0 +OP4 E00082 0 +OP4 E00083 0 +OP4 E00084 0 +OP4 E00085 0 +OP4 E00086 0 +OP4 E00087 0 +OP4 E00088 0 +OP4 E00089 0 +OP4 E0008A 0 +OP4 E0008B 0 +OP4 E0008C 0 +OP4 E0008D 0 +OP4 E0008E 0 +OP4 E0008F 0 +OP4 E00090 0 +OP4 E00091 0 +OP4 E00092 0 +OP4 E00093 0 +OP4 E00094 0 +OP4 E00095 0 +OP4 E00096 0 +OP4 E00097 0 +OP4 E00098 0 +OP4 E00099 0 +OP4 E0009A 0 +OP4 E0009B 0 +OP4 E0009C 0 +OP4 E0009D 0 +OP4 E0009E 0 +OP4 E0009F 0 +OP4 E000A0 0 +OP4 E000A1 0 +OP4 E000A2 0 +OP4 E000A3 0 +OP4 E000A4 0 +OP4 E000A5 0 +OP4 E000A6 0 +OP4 E000A7 0 +OP4 E000A8 0 +OP4 E000A9 0 +OP4 E000AA 0 +OP4 E000AB 0 +OP4 E000AC 0 +OP4 E000AD 0 +OP4 E000AE 0 +OP4 E000AF 0 +OP4 E000B0 0 +OP4 E000B1 0 +OP4 E000B2 0 +OP4 E000B3 0 +OP4 E000B4 0 +OP4 E000B5 0 +OP4 E000B6 0 +OP4 E000B7 0 +OP4 E000B8 0 +OP4 E000B9 0 +OP4 E000BA 0 +OP4 E000BB 0 +OP4 E000BC 0 +OP4 E000BD 0 +OP4 E000BE 0 +OP4 E000BF 0 +OP4 E000C0 0 +OP4 E000C1 0 +OP4 E000C2 0 +OP4 E000C3 0 +OP4 E000C4 0 +OP4 E000C5 0 +OP4 E000C6 0 +OP4 E000C7 0 +OP4 E000C8 0 +OP4 E000C9 0 +OP4 E000CA 0 +OP4 E000CB 0 +OP4 E000CC 0 +OP4 E000CD 0 +OP4 E000CE 0 +OP4 E000CF 0 +OP4 E000D0 0 +OP4 E000D1 0 +OP4 E000D2 0 +OP4 E000D3 0 +OP4 E000D4 0 +OP4 E000D5 0 +OP4 E000D6 0 +OP4 E000D7 0 +OP4 E000D8 0 +OP4 E000D9 0 +OP4 E000DA 0 +OP4 E000DB 0 +OP4 E000DC 0 +OP4 E000DD 0 +OP4 E000DE 0 +OP4 E000DF 0 +OP4 E000E0 0 +OP4 E000E1 0 +OP4 E000E2 0 +OP4 E000E3 0 +OP4 E000E4 0 +OP4 E000E5 0 +OP4 E000E6 0 +OP4 E000E7 0 +OP4 E000E8 0 +OP4 E000E9 0 +OP4 E000EA 0 +OP4 E000EB 0 +OP4 E000EC 0 +OP4 E000ED 0 +OP4 E000EE 0 +OP4 E000EF 0 +OP4 E000F0 0 +OP4 E000F1 0 +OP4 E000F2 0 +OP4 E000F3 0 +OP4 E000F4 0 +OP4 E000F5 0 +OP4 E000F6 0 +OP4 E000F7 0 +OP4 E000F8 0 +OP4 E000F9 0 +OP4 E000FA 0 +OP4 E000FB 0 +OP4 E000FC 0 +OP4 E000FD 0 +OP4 E000FE 0 +OP4 E000FF 0 +OP4 E00100 0 +OP4 E00101 0 +OP4 E00102 0 +OP4 E00103 0 +OP4 E00104 0 +OP4 E00105 0 +OP4 E00106 0 +OP4 E00107 0 +OP4 E00108 0 +OP4 E00109 0 +OP4 E0010A 0 +OP4 E0010B 0 +OP4 E0010C 0 +OP4 E0010D 0 +OP4 E0010E 0 +OP4 E0010F 0 +OP4 E00110 0 +OP4 E00111 0 +OP4 E00112 0 +OP4 E00113 0 +OP4 E00114 0 +OP4 E00115 0 +OP4 E00116 0 +OP4 E00117 0 +OP4 E00118 0 +OP4 E00119 0 +OP4 E0011A 0 +OP4 E0011B 0 +OP4 E0011C 0 +OP4 E0011D 0 +OP4 E0011E 0 +OP4 E0011F 0 +OP4 E00120 0 +OP4 E00121 0 +OP4 E00122 0 +OP4 E00123 0 +OP4 E00124 0 +OP4 E00125 0 +OP4 E00126 0 +OP4 E00127 0 +OP4 E00128 0 +OP4 E00129 0 +OP4 E0012A 0 +OP4 E0012B 0 +OP4 E0012C 0 +OP4 E0012D 0 +OP4 E0012E 0 +OP4 E0012F 0 +OP4 E00130 0 +OP4 E00131 0 +OP4 E00132 0 +OP4 E00133 0 +OP4 E00134 0 +OP4 E00135 0 +OP4 E00136 0 +OP4 E00137 0 +OP4 E00138 0 +OP4 E00139 0 +OP4 E0013A 0 +OP4 E0013B 0 +OP4 E0013C 0 +OP4 E0013D 0 +OP4 E0013E 0 +OP4 E0013F 0 +OP4 E00140 0 +OP4 E00141 0 +OP4 E00142 0 +OP4 E00143 0 +OP4 E00144 0 +OP4 E00145 0 +OP4 E00146 0 +OP4 E00147 0 +OP4 E00148 0 +OP4 E00149 0 +OP4 E0014A 0 +OP4 E0014B 0 +OP4 E0014C 0 +OP4 E0014D 0 +OP4 E0014E 0 +OP4 E0014F 0 +OP4 E00150 0 +OP4 E00151 0 +OP4 E00152 0 +OP4 E00153 0 +OP4 E00154 0 +OP4 E00155 0 +OP4 E00156 0 +OP4 E00157 0 +OP4 E00158 0 +OP4 E00159 0 +OP4 E0015A 0 +OP4 E0015B 0 +OP4 E0015C 0 +OP4 E0015D 0 +OP4 E0015E 0 +OP4 E0015F 0 +OP4 E00160 0 +OP4 E00161 0 +OP4 E00162 0 +OP4 E00163 0 +OP4 E00164 0 +OP4 E00165 0 +OP4 E00166 0 +OP4 E00167 0 +OP4 E00168 0 +OP4 E00169 0 +OP4 E0016A 0 +OP4 E0016B 0 +OP4 E0016C 0 +OP4 E0016D 0 +OP4 E0016E 0 +OP4 E0016F 0 +OP4 E00170 0 +OP4 E00171 0 +OP4 E00172 0 +OP4 E00173 0 +OP4 E00174 0 +OP4 E00175 0 +OP4 E00176 0 +OP4 E00177 0 +OP4 E00178 0 +OP4 E00179 0 +OP4 E0017A 0 +OP4 E0017B 0 +OP4 E0017C 0 +OP4 E0017D 0 +OP4 E0017E 0 +OP4 E0017F 0 +OP4 E00180 0 +OP4 E00181 0 +OP4 E00182 0 +OP4 E00183 0 +OP4 E00184 0 +OP4 E00185 0 +OP4 E00186 0 +OP4 E00187 0 +OP4 E00188 0 +OP4 E00189 0 +OP4 E0018A 0 +OP4 E0018B 0 +OP4 E0018C 0 +OP4 E0018D 0 +OP4 E0018E 0 +OP4 E0018F 0 +OP4 E00190 0 +OP4 E00191 0 +OP4 E00192 0 +OP4 E00193 0 +OP4 E00194 0 +OP4 E00195 0 +OP4 E00196 0 +OP4 E00197 0 +OP4 E00198 0 +OP4 E00199 0 +OP4 E0019A 0 +OP4 E0019B 0 +OP4 E0019C 0 +OP4 E0019D 0 +OP4 E0019E 0 +OP4 E0019F 0 +OP4 E001A0 0 +OP4 E001A1 0 +OP4 E001A2 0 +OP4 E001A3 0 +OP4 E001A4 0 +OP4 E001A5 0 +OP4 E001A6 0 +OP4 E001A7 0 +OP4 E001A8 0 +OP4 E001A9 0 +OP4 E001AA 0 +OP4 E001AB 0 +OP4 E001AC 0 +OP4 E001AD 0 +OP4 E001AE 0 +OP4 E001AF 0 +OP4 E001B0 0 +OP4 E001B1 0 +OP4 E001B2 0 +OP4 E001B3 0 +OP4 E001B4 0 +OP4 E001B5 0 +OP4 E001B6 0 +OP4 E001B7 0 +OP4 E001B8 0 +OP4 E001B9 0 +OP4 E001BA 0 +OP4 E001BB 0 +OP4 E001BC 0 +OP4 E001BD 0 +OP4 E001BE 0 +OP4 E001BF 0 +OP4 E001C0 0 +OP4 E001C1 0 +OP4 E001C2 0 +OP4 E001C3 0 +OP4 E001C4 0 +OP4 E001C5 0 +OP4 E001C6 0 +OP4 E001C7 0 +OP4 E001C8 0 +OP4 E001C9 0 +OP4 E001CA 0 +OP4 E001CB 0 +OP4 E001CC 0 +OP4 E001CD 0 +OP4 E001CE 0 +OP4 E001CF 0 +OP4 E001D0 0 +OP4 E001D1 0 +OP4 E001D2 0 +OP4 E001D3 0 +OP4 E001D4 0 +OP4 E001D5 0 +OP4 E001D6 0 +OP4 E001D7 0 +OP4 E001D8 0 +OP4 E001D9 0 +OP4 E001DA 0 +OP4 E001DB 0 +OP4 E001DC 0 +OP4 E001DD 0 +OP4 E001DE 0 +OP4 E001DF 0 +OP4 E001E0 0 +OP4 E001E1 0 +OP4 E001E2 0 +OP4 E001E3 0 +OP4 E001E4 0 +OP4 E001E5 0 +OP4 E001E6 0 +OP4 E001E7 0 +OP4 E001E8 0 +OP4 E001E9 0 +OP4 E001EA 0 +OP4 E001EB 0 +OP4 E001EC 0 +OP4 E001ED 0 +OP4 E001EE 0 +OP4 E001EF 0 +OP4 E001F0 0 +OP4 E001F1 0 +OP4 E001F2 0 +OP4 E001F3 0 +OP4 E001F4 0 +OP4 E001F5 0 +OP4 E001F6 0 +OP4 E001F7 0 +OP4 E001F8 0 +OP4 E001F9 0 +OP4 E001FA 0 +OP4 E001FB 0 +OP4 E001FC 0 +OP4 E001FD 0 +OP4 E001FE 0 +OP4 E001FF 0 +OP4 E00200 0 +OP4 E00201 0 +OP4 E00202 0 +OP4 E00203 0 +OP4 E00204 0 +OP4 E00205 0 +OP4 E00206 0 +OP4 E00207 0 +OP4 E00208 0 +OP4 E00209 0 +OP4 E0020A 0 +OP4 E0020B 0 +OP4 E0020C 0 +OP4 E0020D 0 +OP4 E0020E 0 +OP4 E0020F 0 +OP4 E00210 0 +OP4 E00211 0 +OP4 E00212 0 +OP4 E00213 0 +OP4 E00214 0 +OP4 E00215 0 +OP4 E00216 0 +OP4 E00217 0 +OP4 E00218 0 +OP4 E00219 0 +OP4 E0021A 0 +OP4 E0021B 0 +OP4 E0021C 0 +OP4 E0021D 0 +OP4 E0021E 0 +OP4 E0021F 0 +OP4 E00220 0 +OP4 E00221 0 +OP4 E00222 0 +OP4 E00223 0 +OP4 E00224 0 +OP4 E00225 0 +OP4 E00226 0 +OP4 E00227 0 +OP4 E00228 0 +OP4 E00229 0 +OP4 E0022A 0 +OP4 E0022B 0 +OP4 E0022C 0 +OP4 E0022D 0 +OP4 E0022E 0 +OP4 E0022F 0 +OP4 E00230 0 +OP4 E00231 0 +OP4 E00232 0 +OP4 E00233 0 +OP4 E00234 0 +OP4 E00235 0 +OP4 E00236 0 +OP4 E00237 0 +OP4 E00238 0 +OP4 E00239 0 +OP4 E0023A 0 +OP4 E0023B 0 +OP4 E0023C 0 +OP4 E0023D 0 +OP4 E0023E 0 +OP4 E0023F 0 +OP4 E00240 0 +OP4 E00241 0 +OP4 E00242 0 +OP4 E00243 0 +OP4 E00244 0 +OP4 E00245 0 +OP4 E00246 0 +OP4 E00247 0 +OP4 E00248 0 +OP4 E00249 0 +OP4 E0024A 0 +OP4 E0024B 0 +OP4 E0024C 0 +OP4 E0024D 0 +OP4 E0024E 0 +OP4 E0024F 0 +OP4 E00250 0 +OP4 E00251 0 +OP4 E00252 0 +OP4 E00253 0 +OP4 E00254 0 +OP4 E00255 0 +OP4 E00256 0 +OP4 E00257 0 +OP4 E00258 0 +OP4 E00259 0 +OP4 E0025A 0 +OP4 E0025B 0 +OP4 E0025C 0 +OP4 E0025D 0 +OP4 E0025E 0 +OP4 E0025F 0 +OP4 E00260 0 +OP4 E00261 0 +OP4 E00262 0 +OP4 E00263 0 +OP4 E00264 0 +OP4 E00265 0 +OP4 E00266 0 +OP4 E00267 0 +OP4 E00268 0 +OP4 E00269 0 +OP4 E0026A 0 +OP4 E0026B 0 +OP4 E0026C 0 +OP4 E0026D 0 +OP4 E0026E 0 +OP4 E0026F 0 +OP4 E00270 0 +OP4 E00271 0 +OP4 E00272 0 +OP4 E00273 0 +OP4 E00274 0 +OP4 E00275 0 +OP4 E00276 0 +OP4 E00277 0 +OP4 E00278 0 +OP4 E00279 0 +OP4 E0027A 0 +OP4 E0027B 0 +OP4 E0027C 0 +OP4 E0027D 0 +OP4 E0027E 0 +OP4 E0027F 0 +OP4 E00280 0 +OP4 E00281 0 +OP4 E00282 0 +OP4 E00283 0 +OP4 E00284 0 +OP4 E00285 0 +OP4 E00286 0 +OP4 E00287 0 +OP4 E00288 0 +OP4 E00289 0 +OP4 E0028A 0 +OP4 E0028B 0 +OP4 E0028C 0 +OP4 E0028D 0 +OP4 E0028E 0 +OP4 E0028F 0 +OP4 E00290 0 +OP4 E00291 0 +OP4 E00292 0 +OP4 E00293 0 +OP4 E00294 0 +OP4 E00295 0 +OP4 E00296 0 +OP4 E00297 0 +OP4 E00298 0 +OP4 E00299 0 +OP4 E0029A 0 +OP4 E0029B 0 +OP4 E0029C 0 +OP4 E0029D 0 +OP4 E0029E 0 +OP4 E0029F 0 +OP4 E002A0 0 +OP4 E002A1 0 +OP4 E002A2 0 +OP4 E002A3 0 +OP4 E002A4 0 +OP4 E002A5 0 +OP4 E002A6 0 +OP4 E002A7 0 +OP4 E002A8 0 +OP4 E002A9 0 +OP4 E002AA 0 +OP4 E002AB 0 +OP4 E002AC 0 +OP4 E002AD 0 +OP4 E002AE 0 +OP4 E002AF 0 +OP4 E002B0 0 +OP4 E002B1 0 +OP4 E002B2 0 +OP4 E002B3 0 +OP4 E002B4 0 +OP4 E002B5 0 +OP4 E002B6 0 +OP4 E002B7 0 +OP4 E002B8 0 +OP4 E002B9 0 +OP4 E002BA 0 +OP4 E002BB 0 +OP4 E002BC 0 +OP4 E002BD 0 +OP4 E002BE 0 +OP4 E002BF 0 +OP4 E002C0 0 +OP4 E002C1 0 +OP4 E002C2 0 +OP4 E002C3 0 +OP4 E002C4 0 +OP4 E002C5 0 +OP4 E002C6 0 +OP4 E002C7 0 +OP4 E002C8 0 +OP4 E002C9 0 +OP4 E002CA 0 +OP4 E002CB 0 +OP4 E002CC 0 +OP4 E002CD 0 +OP4 E002CE 0 +OP4 E002CF 0 +OP4 E002D0 0 +OP4 E002D1 0 +OP4 E002D2 0 +OP4 E002D3 0 +OP4 E002D4 0 +OP4 E002D5 0 +OP4 E002D6 0 +OP4 E002D7 0 +OP4 E002D8 0 +OP4 E002D9 0 +OP4 E002DA 0 +OP4 E002DB 0 +OP4 E002DC 0 +OP4 E002DD 0 +OP4 E002DE 0 +OP4 E002DF 0 +OP4 E002E0 0 +OP4 E002E1 0 +OP4 E002E2 0 +OP4 E002E3 0 +OP4 E002E4 0 +OP4 E002E5 0 +OP4 E002E6 0 +OP4 E002E7 0 +OP4 E002E8 0 +OP4 E002E9 0 +OP4 E002EA 0 +OP4 E002EB 0 +OP4 E002EC 0 +OP4 E002ED 0 +OP4 E002EE 0 +OP4 E002EF 0 +OP4 E002F0 0 +OP4 E002F1 0 +OP4 E002F2 0 +OP4 E002F3 0 +OP4 E002F4 0 +OP4 E002F5 0 +OP4 E002F6 0 +OP4 E002F7 0 +OP4 E002F8 0 +OP4 E002F9 0 +OP4 E002FA 0 +OP4 E002FB 0 +OP4 E002FC 0 +OP4 E002FD 0 +OP4 E002FE 0 +OP4 E002FF 0 +OP4 E00300 0 +OP4 E00301 0 +OP4 E00302 0 +OP4 E00303 0 +OP4 E00304 0 +OP4 E00305 0 +OP4 E00306 0 +OP4 E00307 0 +OP4 E00308 0 +OP4 E00309 0 +OP4 E0030A 0 +OP4 E0030B 0 +OP4 E0030C 0 +OP4 E0030D 0 +OP4 E0030E 0 +OP4 E0030F 0 +OP4 E00310 0 +OP4 E00311 0 +OP4 E00312 0 +OP4 E00313 0 +OP4 E00314 0 +OP4 E00315 0 +OP4 E00316 0 +OP4 E00317 0 +OP4 E00318 0 +OP4 E00319 0 +OP4 E0031A 0 +OP4 E0031B 0 +OP4 E0031C 0 +OP4 E0031D 0 +OP4 E0031E 0 +OP4 E0031F 0 +OP4 E00320 0 +OP4 E00321 0 +OP4 E00322 0 +OP4 E00323 0 +OP4 E00324 0 +OP4 E00325 0 +OP4 E00326 0 +OP4 E00327 0 +OP4 E00328 0 +OP4 E00329 0 +OP4 E0032A 0 +OP4 E0032B 0 +OP4 E0032C 0 +OP4 E0032D 0 +OP4 E0032E 0 +OP4 E0032F 0 +OP4 E00330 0 +OP4 E00331 0 +OP4 E00332 0 +OP4 E00333 0 +OP4 E00334 0 +OP4 E00335 0 +OP4 E00336 0 +OP4 E00337 0 +OP4 E00338 0 +OP4 E00339 0 +OP4 E0033A 0 +OP4 E0033B 0 +OP4 E0033C 0 +OP4 E0033D 0 +OP4 E0033E 0 +OP4 E0033F 0 +OP4 E00340 0 +OP4 E00341 0 +OP4 E00342 0 +OP4 E00343 0 +OP4 E00344 0 +OP4 E00345 0 +OP4 E00346 0 +OP4 E00347 0 +OP4 E00348 0 +OP4 E00349 0 +OP4 E0034A 0 +OP4 E0034B 0 +OP4 E0034C 0 +OP4 E0034D 0 +OP4 E0034E 0 +OP4 E0034F 0 +OP4 E00350 0 +OP4 E00351 0 +OP4 E00352 0 +OP4 E00353 0 +OP4 E00354 0 +OP4 E00355 0 +OP4 E00356 0 +OP4 E00357 0 +OP4 E00358 0 +OP4 E00359 0 +OP4 E0035A 0 +OP4 E0035B 0 +OP4 E0035C 0 +OP4 E0035D 0 +OP4 E0035E 0 +OP4 E0035F 0 +OP4 E00360 0 +OP4 E00361 0 +OP4 E00362 0 +OP4 E00363 0 +OP4 E00364 0 +OP4 E00365 0 +OP4 E00366 0 +OP4 E00367 0 +OP4 E00368 0 +OP4 E00369 0 +OP4 E0036A 0 +OP4 E0036B 0 +OP4 E0036C 0 +OP4 E0036D 0 +OP4 E0036E 0 +OP4 E0036F 0 +OP4 E00370 0 +OP4 E00371 0 +OP4 E00372 0 +OP4 E00373 0 +OP4 E00374 0 +OP4 E00375 0 +OP4 E00376 0 +OP4 E00377 0 +OP4 E00378 0 +OP4 E00379 0 +OP4 E0037A 0 +OP4 E0037B 0 +OP4 E0037C 0 +OP4 E0037D 0 +OP4 E0037E 0 +OP4 E0037F 0 +OP4 E00380 0 +OP4 E00381 0 +OP4 E00382 0 +OP4 E00383 0 +OP4 E00384 0 +OP4 E00385 0 +OP4 E00386 0 +OP4 E00387 0 +OP4 E00388 0 +OP4 E00389 0 +OP4 E0038A 0 +OP4 E0038B 0 +OP4 E0038C 0 +OP4 E0038D 0 +OP4 E0038E 0 +OP4 E0038F 0 +OP4 E00390 0 +OP4 E00391 0 +OP4 E00392 0 +OP4 E00393 0 +OP4 E00394 0 +OP4 E00395 0 +OP4 E00396 0 +OP4 E00397 0 +OP4 E00398 0 +OP4 E00399 0 +OP4 E0039A 0 +OP4 E0039B 0 +OP4 E0039C 0 +OP4 E0039D 0 +OP4 E0039E 0 +OP4 E0039F 0 +OP4 E003A0 0 +OP4 E003A1 0 +OP4 E003A2 0 +OP4 E003A3 0 +OP4 E003A4 0 +OP4 E003A5 0 +OP4 E003A6 0 +OP4 E003A7 0 +OP4 E003A8 0 +OP4 E003A9 0 +OP4 E003AA 0 +OP4 E003AB 0 +OP4 E003AC 0 +OP4 E003AD 0 +OP4 E003AE 0 +OP4 E003AF 0 +OP4 E003B0 0 +OP4 E003B1 0 +OP4 E003B2 0 +OP4 E003B3 0 +OP4 E003B4 0 +OP4 E003B5 0 +OP4 E003B6 0 +OP4 E003B7 0 +OP4 E003B8 0 +OP4 E003B9 0 +OP4 E003BA 0 +OP4 E003BB 0 +OP4 E003BC 0 +OP4 E003BD 0 +OP4 E003BE 0 +OP4 E003BF 0 +OP4 E003C0 0 +OP4 E003C1 0 +OP4 E003C2 0 +OP4 E003C3 0 +OP4 E003C4 0 +OP4 E003C5 0 +OP4 E003C6 0 +OP4 E003C7 0 +OP4 E003C8 0 +OP4 E003C9 0 +OP4 E003CA 0 +OP4 E003CB 0 +OP4 E003CC 0 +OP4 E003CD 0 +OP4 E003CE 0 +OP4 E003CF 0 +OP4 E003D0 0 +OP4 E003D1 0 +OP4 E003D2 0 +OP4 E003D3 0 +OP4 E003D4 0 +OP4 E003D5 0 +OP4 E003D6 0 +OP4 E003D7 0 +OP4 E003D8 0 +OP4 E003D9 0 +OP4 E003DA 0 +OP4 E003DB 0 +OP4 E003DC 0 +OP4 E003DD 0 +OP4 E003DE 0 +OP4 E003DF 0 +OP4 E003E0 0 +OP4 E003E1 0 +OP4 E003E2 0 +OP4 E003E3 0 +OP4 E003E4 0 +OP4 E003E5 0 +OP4 E003E6 0 +OP4 E003E7 0 +OP4 E003E8 0 +OP4 E003E9 0 +OP4 E003EA 0 +OP4 E003EB 0 +OP4 E003EC 0 +OP4 E003ED 0 +OP4 E003EE 0 +OP4 E003EF 0 +OP4 E003F0 0 +OP4 E003F1 0 +OP4 E003F2 0 +OP4 E003F3 0 +OP4 E003F4 0 +OP4 E003F5 0 +OP4 E003F6 0 +OP4 E003F7 0 +OP4 E003F8 0 +OP4 E003F9 0 +OP4 E003FA 0 +OP4 E003FB 0 +OP4 E003FC 0 +OP4 E003FD 0 +OP4 E003FE 0 +OP4 E003FF 0 +OP4 E00400 0 +OP4 E00401 0 +OP4 E00402 0 +OP4 E00403 0 +OP4 E00404 0 +OP4 E00405 0 +OP4 E00406 0 +OP4 E00407 0 +OP4 E00408 0 +OP4 E00409 0 +OP4 E0040A 0 +OP4 E0040B 0 +OP4 E0040C 0 +OP4 E0040D 0 +OP4 E0040E 0 +OP4 E0040F 0 +OP4 E00410 0 +OP4 E00411 0 +OP4 E00412 0 +OP4 E00413 0 +OP4 E00414 0 +OP4 E00415 0 +OP4 E00416 0 +OP4 E00417 0 +OP4 E00418 0 +OP4 E00419 0 +OP4 E0041A 0 +OP4 E0041B 0 +OP4 E0041C 0 +OP4 E0041D 0 +OP4 E0041E 0 +OP4 E0041F 0 +OP4 E00420 0 +OP4 E00421 0 +OP4 E00422 0 +OP4 E00423 0 +OP4 E00424 0 +OP4 E00425 0 +OP4 E00426 0 +OP4 E00427 0 +OP4 E00428 0 +OP4 E00429 0 +OP4 E0042A 0 +OP4 E0042B 0 +OP4 E0042C 0 +OP4 E0042D 0 +OP4 E0042E 0 +OP4 E0042F 0 +OP4 E00430 0 +OP4 E00431 0 +OP4 E00432 0 +OP4 E00433 0 +OP4 E00434 0 +OP4 E00435 0 +OP4 E00436 0 +OP4 E00437 0 +OP4 E00438 0 +OP4 E00439 0 +OP4 E0043A 0 +OP4 E0043B 0 +OP4 E0043C 0 +OP4 E0043D 0 +OP4 E0043E 0 +OP4 E0043F 0 +OP4 E00440 0 +OP4 E00441 0 +OP4 E00442 0 +OP4 E00443 0 +OP4 E00444 0 +OP4 E00445 0 +OP4 E00446 0 +OP4 E00447 0 +OP4 E00448 0 +OP4 E00449 0 +OP4 E0044A 0 +OP4 E0044B 0 +OP4 E0044C 0 +OP4 E0044D 0 +OP4 E0044E 0 +OP4 E0044F 0 +OP4 E00450 0 +OP4 E00451 0 +OP4 E00452 0 +OP4 E00453 0 +OP4 E00454 0 +OP4 E00455 0 +OP4 E00456 0 +OP4 E00457 0 +OP4 E00458 0 +OP4 E00459 0 +OP4 E0045A 0 +OP4 E0045B 0 +OP4 E0045C 0 +OP4 E0045D 0 +OP4 E0045E 0 +OP4 E0045F 0 +OP4 E00460 0 +OP4 E00461 0 +OP4 E00462 0 +OP4 E00463 0 +OP4 E00464 0 +OP4 E00465 0 +OP4 E00466 0 +OP4 E00467 0 +OP4 E00468 0 +OP4 E00469 0 +OP4 E0046A 0 +OP4 E0046B 0 +OP4 E0046C 0 +OP4 E0046D 0 +OP4 E0046E 0 +OP4 E0046F 0 +OP4 E00470 0 +OP4 E00471 0 +OP4 E00472 0 +OP4 E00473 0 +OP4 E00474 0 +OP4 E00475 0 +OP4 E00476 0 +OP4 E00477 0 +OP4 E00478 0 +OP4 E00479 0 +OP4 E0047A 0 +OP4 E0047B 0 +OP4 E0047C 0 +OP4 E0047D 0 +OP4 E0047E 0 +OP4 E0047F 0 +OP4 E00480 0 +OP4 E00481 0 +OP4 E00482 0 +OP4 E00483 0 +OP4 E00484 0 +OP4 E00485 0 +OP4 E00486 0 +OP4 E00487 0 +OP4 E00488 0 +OP4 E00489 0 +OP4 E0048A 0 +OP4 E0048B 0 +OP4 E0048C 0 +OP4 E0048D 0 +OP4 E0048E 0 +OP4 E0048F 0 +OP4 E00490 0 +OP4 E00491 0 +OP4 E00492 0 +OP4 E00493 0 +OP4 E00494 0 +OP4 E00495 0 +OP4 E00496 0 +OP4 E00497 0 +OP4 E00498 0 +OP4 E00499 0 +OP4 E0049A 0 +OP4 E0049B 0 +OP4 E0049C 0 +OP4 E0049D 0 +OP4 E0049E 0 +OP4 E0049F 0 +OP4 E004A0 0 +OP4 E004A1 0 +OP4 E004A2 0 +OP4 E004A3 0 +OP4 E004A4 0 +OP4 E004A5 0 +OP4 E004A6 0 +OP4 E004A7 0 +OP4 E004A8 0 +OP4 E004A9 0 +OP4 E004AA 0 +OP4 E004AB 0 +OP4 E004AC 0 +OP4 E004AD 0 +OP4 E004AE 0 +OP4 E004AF 0 +OP4 E004B0 0 +OP4 E004B1 0 +OP4 E004B2 0 +OP4 E004B3 0 +OP4 E004B4 0 +OP4 E004B5 0 +OP4 E004B6 0 +OP4 E004B7 0 +OP4 E004B8 0 +OP4 E004B9 0 +OP4 E004BA 0 +OP4 E004BB 0 +OP4 E004BC 0 +OP4 E004BD 0 +OP4 E004BE 0 +OP4 E004BF 0 +OP4 E004C0 0 +OP4 E004C1 0 +OP4 E004C2 0 +OP4 E004C3 0 +OP4 E004C4 0 +OP4 E004C5 0 +OP4 E004C6 0 +OP4 E004C7 0 +OP4 E004C8 0 +OP4 E004C9 0 +OP4 E004CA 0 +OP4 E004CB 0 +OP4 E004CC 0 +OP4 E004CD 0 +OP4 E004CE 0 +OP4 E004CF 0 +OP4 E004D0 0 +OP4 E004D1 0 +OP4 E004D2 0 +OP4 E004D3 0 +OP4 E004D4 0 +OP4 E004D5 0 +OP4 E004D6 0 +OP4 E004D7 0 +OP4 E004D8 0 +OP4 E004D9 0 +OP4 E004DA 0 +OP4 E004DB 0 +OP4 E004DC 0 +OP4 E004DD 0 +OP4 E004DE 0 +OP4 E004DF 0 +OP4 E004E0 0 +OP4 E004E1 0 +OP4 E004E2 0 +OP4 E004E3 0 +OP4 E004E4 0 +OP4 E004E5 0 +OP4 E004E6 0 +OP4 E004E7 0 +OP4 E004E8 0 +OP4 E004E9 0 +OP4 E004EA 0 +OP4 E004EB 0 +OP4 E004EC 0 +OP4 E004ED 0 +OP4 E004EE 0 +OP4 E004EF 0 +OP4 E004F0 0 +OP4 E004F1 0 +OP4 E004F2 0 +OP4 E004F3 0 +OP4 E004F4 0 +OP4 E004F5 0 +OP4 E004F6 0 +OP4 E004F7 0 +OP4 E004F8 0 +OP4 E004F9 0 +OP4 E004FA 0 +OP4 E004FB 0 +OP4 E004FC 0 +OP4 E004FD 0 +OP4 E004FE 0 +OP4 E004FF 0 +OP4 E00500 0 +OP4 E00501 0 +OP4 E00502 0 +OP4 E00503 0 +OP4 E00504 0 +OP4 E00505 0 +OP4 E00506 0 +OP4 E00507 0 +OP4 E00508 0 +OP4 E00509 0 +OP4 E0050A 0 +OP4 E0050B 0 +OP4 E0050C 0 +OP4 E0050D 0 +OP4 E0050E 0 +OP4 E0050F 0 +OP4 E00510 0 +OP4 E00511 0 +OP4 E00512 0 +OP4 E00513 0 +OP4 E00514 0 +OP4 E00515 0 +OP4 E00516 0 +OP4 E00517 0 +OP4 E00518 0 +OP4 E00519 0 +OP4 E0051A 0 +OP4 E0051B 0 +OP4 E0051C 0 +OP4 E0051D 0 +OP4 E0051E 0 +OP4 E0051F 0 +OP4 E00520 0 +OP4 E00521 0 +OP4 E00522 0 +OP4 E00523 0 +OP4 E00524 0 +OP4 E00525 0 +OP4 E00526 0 +OP4 E00527 0 +OP4 E00528 0 +OP4 E00529 0 +OP4 E0052A 0 +OP4 E0052B 0 +OP4 E0052C 0 +OP4 E0052D 0 +OP4 E0052E 0 +OP4 E0052F 0 +OP4 E00530 0 +OP4 E00531 0 +OP4 E00532 0 +OP4 E00533 0 +OP4 E00534 0 +OP4 E00535 0 +OP4 E00536 0 +OP4 E00537 0 +OP4 E00538 0 +OP4 E00539 0 +OP4 E0053A 0 +OP4 E0053B 0 +OP4 E0053C 0 +OP4 E0053D 0 +OP4 E0053E 0 +OP4 E0053F 0 +OP4 E00540 0 +OP4 E00541 0 +OP4 E00542 0 +OP4 E00543 0 +OP4 E00544 0 +OP4 E00545 0 +OP4 E00546 0 +OP4 E00547 0 +OP4 E00548 0 +OP4 E00549 0 +OP4 E0054A 0 +OP4 E0054B 0 +OP4 E0054C 0 +OP4 E0054D 0 +OP4 E0054E 0 +OP4 E0054F 0 +OP4 E00550 0 +OP4 E00551 0 +OP4 E00552 0 +OP4 E00553 0 +OP4 E00554 0 +OP4 E00555 0 +OP4 E00556 0 +OP4 E00557 0 +OP4 E00558 0 +OP4 E00559 0 +OP4 E0055A 0 +OP4 E0055B 0 +OP4 E0055C 0 +OP4 E0055D 0 +OP4 E0055E 0 +OP4 E0055F 0 +OP4 E00560 0 +OP4 E00561 0 +OP4 E00562 0 +OP4 E00563 0 +OP4 E00564 0 +OP4 E00565 0 +OP4 E00566 0 +OP4 E00567 0 +OP4 E00568 0 +OP4 E00569 0 +OP4 E0056A 0 +OP4 E0056B 0 +OP4 E0056C 0 +OP4 E0056D 0 +OP4 E0056E 0 +OP4 E0056F 0 +OP4 E00570 0 +OP4 E00571 0 +OP4 E00572 0 +OP4 E00573 0 +OP4 E00574 0 +OP4 E00575 0 +OP4 E00576 0 +OP4 E00577 0 +OP4 E00578 0 +OP4 E00579 0 +OP4 E0057A 0 +OP4 E0057B 0 +OP4 E0057C 0 +OP4 E0057D 0 +OP4 E0057E 0 +OP4 E0057F 0 +OP4 E00580 0 +OP4 E00581 0 +OP4 E00582 0 +OP4 E00583 0 +OP4 E00584 0 +OP4 E00585 0 +OP4 E00586 0 +OP4 E00587 0 +OP4 E00588 0 +OP4 E00589 0 +OP4 E0058A 0 +OP4 E0058B 0 +OP4 E0058C 0 +OP4 E0058D 0 +OP4 E0058E 0 +OP4 E0058F 0 +OP4 E00590 0 +OP4 E00591 0 +OP4 E00592 0 +OP4 E00593 0 +OP4 E00594 0 +OP4 E00595 0 +OP4 E00596 0 +OP4 E00597 0 +OP4 E00598 0 +OP4 E00599 0 +OP4 E0059A 0 +OP4 E0059B 0 +OP4 E0059C 0 +OP4 E0059D 0 +OP4 E0059E 0 +OP4 E0059F 0 +OP4 E005A0 0 +OP4 E005A1 0 +OP4 E005A2 0 +OP4 E005A3 0 +OP4 E005A4 0 +OP4 E005A5 0 +OP4 E005A6 0 +OP4 E005A7 0 +OP4 E005A8 0 +OP4 E005A9 0 +OP4 E005AA 0 +OP4 E005AB 0 +OP4 E005AC 0 +OP4 E005AD 0 +OP4 E005AE 0 +OP4 E005AF 0 +OP4 E005B0 0 +OP4 E005B1 0 +OP4 E005B2 0 +OP4 E005B3 0 +OP4 E005B4 0 +OP4 E005B5 0 +OP4 E005B6 0 +OP4 E005B7 0 +OP4 E005B8 0 +OP4 E005B9 0 +OP4 E005BA 0 +OP4 E005BB 0 +OP4 E005BC 0 +OP4 E005BD 0 +OP4 E005BE 0 +OP4 E005BF 0 +OP4 E005C0 0 +OP4 E005C1 0 +OP4 E005C2 0 +OP4 E005C3 0 +OP4 E005C4 0 +OP4 E005C5 0 +OP4 E005C6 0 +OP4 E005C7 0 +OP4 E005C8 0 +OP4 E005C9 0 +OP4 E005CA 0 +OP4 E005CB 0 +OP4 E005CC 0 +OP4 E005CD 0 +OP4 E005CE 0 +OP4 E005CF 0 +OP4 E005D0 0 +OP4 E005D1 0 +OP4 E005D2 0 +OP4 E005D3 0 +OP4 E005D4 0 +OP4 E005D5 0 +OP4 E005D6 0 +OP4 E005D7 0 +OP4 E005D8 0 +OP4 E005D9 0 +OP4 E005DA 0 +OP4 E005DB 0 +OP4 E005DC 0 +OP4 E005DD 0 +OP4 E005DE 0 +OP4 E005DF 0 +OP4 E005E0 0 +OP4 E005E1 0 +OP4 E005E2 0 +OP4 E005E3 0 +OP4 E005E4 0 +OP4 E005E5 0 +OP4 E005E6 0 +OP4 E005E7 0 +OP4 E005E8 0 +OP4 E005E9 0 +OP4 E005EA 0 +OP4 E005EB 0 +OP4 E005EC 0 +OP4 E005ED 0 +OP4 E005EE 0 +OP4 E005EF 0 +OP4 E005F0 0 +OP4 E005F1 0 +OP4 E005F2 0 +OP4 E005F3 0 +OP4 E005F4 0 +OP4 E005F5 0 +OP4 E005F6 0 +OP4 E005F7 0 +OP4 E005F8 0 +OP4 E005F9 0 +OP4 E005FA 0 +OP4 E005FB 0 +OP4 E005FC 0 +OP4 E005FD 0 +OP4 E005FE 0 +OP4 E005FF 0 +OP4 E00600 0 +OP4 E00601 0 +OP4 E00602 0 +OP4 E00603 0 +OP4 E00604 0 +OP4 E00605 0 +OP4 E00606 0 +OP4 E00607 0 +OP4 E00608 0 +OP4 E00609 0 +OP4 E0060A 0 +OP4 E0060B 0 +OP4 E0060C 0 +OP4 E0060D 0 +OP4 E0060E 0 +OP4 E0060F 0 +OP4 E00610 0 +OP4 E00611 0 +OP4 E00612 0 +OP4 E00613 0 +OP4 E00614 0 +OP4 E00615 0 +OP4 E00616 0 +OP4 E00617 0 +OP4 E00618 0 +OP4 E00619 0 +OP4 E0061A 0 +OP4 E0061B 0 +OP4 E0061C 0 +OP4 E0061D 0 +OP4 E0061E 0 +OP4 E0061F 0 +OP4 E00620 0 +OP4 E00621 0 +OP4 E00622 0 +OP4 E00623 0 +OP4 E00624 0 +OP4 E00625 0 +OP4 E00626 0 +OP4 E00627 0 +OP4 E00628 0 +OP4 E00629 0 +OP4 E0062A 0 +OP4 E0062B 0 +OP4 E0062C 0 +OP4 E0062D 0 +OP4 E0062E 0 +OP4 E0062F 0 +OP4 E00630 0 +OP4 E00631 0 +OP4 E00632 0 +OP4 E00633 0 +OP4 E00634 0 +OP4 E00635 0 +OP4 E00636 0 +OP4 E00637 0 +OP4 E00638 0 +OP4 E00639 0 +OP4 E0063A 0 +OP4 E0063B 0 +OP4 E0063C 0 +OP4 E0063D 0 +OP4 E0063E 0 +OP4 E0063F 0 +OP4 E00640 0 +OP4 E00641 0 +OP4 E00642 0 +OP4 E00643 0 +OP4 E00644 0 +OP4 E00645 0 +OP4 E00646 0 +OP4 E00647 0 +OP4 E00648 0 +OP4 E00649 0 +OP4 E0064A 0 +OP4 E0064B 0 +OP4 E0064C 0 +OP4 E0064D 0 +OP4 E0064E 0 +OP4 E0064F 0 +OP4 E00650 0 +OP4 E00651 0 +OP4 E00652 0 +OP4 E00653 0 +OP4 E00654 0 +OP4 E00655 0 +OP4 E00656 0 +OP4 E00657 0 +OP4 E00658 0 +OP4 E00659 0 +OP4 E0065A 0 +OP4 E0065B 0 +OP4 E0065C 0 +OP4 E0065D 0 +OP4 E0065E 0 +OP4 E0065F 0 +OP4 E00660 0 +OP4 E00661 0 +OP4 E00662 0 +OP4 E00663 0 +OP4 E00664 0 +OP4 E00665 0 +OP4 E00666 0 +OP4 E00667 0 +OP4 E00668 0 +OP4 E00669 0 +OP4 E0066A 0 +OP4 E0066B 0 +OP4 E0066C 0 +OP4 E0066D 0 +OP4 E0066E 0 +OP4 E0066F 0 +OP4 E00670 0 +OP4 E00671 0 +OP4 E00672 0 +OP4 E00673 0 +OP4 E00674 0 +OP4 E00675 0 +OP4 E00676 0 +OP4 E00677 0 +OP4 E00678 0 +OP4 E00679 0 +OP4 E0067A 0 +OP4 E0067B 0 +OP4 E0067C 0 +OP4 E0067D 0 +OP4 E0067E 0 +OP4 E0067F 0 +OP4 E00680 0 +OP4 E00681 0 +OP4 E00682 0 +OP4 E00683 0 +OP4 E00684 0 +OP4 E00685 0 +OP4 E00686 0 +OP4 E00687 0 +OP4 E00688 0 +OP4 E00689 0 +OP4 E0068A 0 +OP4 E0068B 0 +OP4 E0068C 0 +OP4 E0068D 0 +OP4 E0068E 0 +OP4 E0068F 0 +OP4 E00690 0 +OP4 E00691 0 +OP4 E00692 0 +OP4 E00693 0 +OP4 E00694 0 +OP4 E00695 0 +OP4 E00696 0 +OP4 E00697 0 +OP4 E00698 0 +OP4 E00699 0 +OP4 E0069A 0 +OP4 E0069B 0 +OP4 E0069C 0 +OP4 E0069D 0 +OP4 E0069E 0 +OP4 E0069F 0 +OP4 E006A0 0 +OP4 E006A1 0 +OP4 E006A2 0 +OP4 E006A3 0 +OP4 E006A4 0 +OP4 E006A5 0 +OP4 E006A6 0 +OP4 E006A7 0 +OP4 E006A8 0 +OP4 E006A9 0 +OP4 E006AA 0 +OP4 E006AB 0 +OP4 E006AC 0 +OP4 E006AD 0 +OP4 E006AE 0 +OP4 E006AF 0 +OP4 E006B0 0 +OP4 E006B1 0 +OP4 E006B2 0 +OP4 E006B3 0 +OP4 E006B4 0 +OP4 E006B5 0 +OP4 E006B6 0 +OP4 E006B7 0 +OP4 E006B8 0 +OP4 E006B9 0 +OP4 E006BA 0 +OP4 E006BB 0 +OP4 E006BC 0 +OP4 E006BD 0 +OP4 E006BE 0 +OP4 E006BF 0 +OP4 E006C0 0 +OP4 E006C1 0 +OP4 E006C2 0 +OP4 E006C3 0 +OP4 E006C4 0 +OP4 E006C5 0 +OP4 E006C6 0 +OP4 E006C7 0 +OP4 E006C8 0 +OP4 E006C9 0 +OP4 E006CA 0 +OP4 E006CB 0 +OP4 E006CC 0 +OP4 E006CD 0 +OP4 E006CE 0 +OP4 E006CF 0 +OP4 E006D0 0 +OP4 E006D1 0 +OP4 E006D2 0 +OP4 E006D3 0 +OP4 E006D4 0 +OP4 E006D5 0 +OP4 E006D6 0 +OP4 E006D7 0 +OP4 E006D8 0 +OP4 E006D9 0 +OP4 E006DA 0 +OP4 E006DB 0 +OP4 E006DC 0 +OP4 E006DD 0 +OP4 E006DE 0 +OP4 E006DF 0 +OP4 E006E0 0 +OP4 E006E1 0 +OP4 E006E2 0 +OP4 E006E3 0 +OP4 E006E4 0 +OP4 E006E5 0 +OP4 E006E6 0 +OP4 E006E7 0 +OP4 E006E8 0 +OP4 E006E9 0 +OP4 E006EA 0 +OP4 E006EB 0 +OP4 E006EC 0 +OP4 E006ED 0 +OP4 E006EE 0 +OP4 E006EF 0 +OP4 E006F0 0 +OP4 E006F1 0 +OP4 E006F2 0 +OP4 E006F3 0 +OP4 E006F4 0 +OP4 E006F5 0 +OP4 E006F6 0 +OP4 E006F7 0 +OP4 E006F8 0 +OP4 E006F9 0 +OP4 E006FA 0 +OP4 E006FB 0 +OP4 E006FC 0 +OP4 E006FD 0 +OP4 E006FE 0 +OP4 E006FF 0 +OP4 E00700 0 +OP4 E00701 0 +OP4 E00702 0 +OP4 E00703 0 +OP4 E00704 0 +OP4 E00705 0 +OP4 E00706 0 +OP4 E00707 0 +OP4 E00708 0 +OP4 E00709 0 +OP4 E0070A 0 +OP4 E0070B 0 +OP4 E0070C 0 +OP4 E0070D 0 +OP4 E0070E 0 +OP4 E0070F 0 +OP4 E00710 0 +OP4 E00711 0 +OP4 E00712 0 +OP4 E00713 0 +OP4 E00714 0 +OP4 E00715 0 +OP4 E00716 0 +OP4 E00717 0 +OP4 E00718 0 +OP4 E00719 0 +OP4 E0071A 0 +OP4 E0071B 0 +OP4 E0071C 0 +OP4 E0071D 0 +OP4 E0071E 0 +OP4 E0071F 0 +OP4 E00720 0 +OP4 E00721 0 +OP4 E00722 0 +OP4 E00723 0 +OP4 E00724 0 +OP4 E00725 0 +OP4 E00726 0 +OP4 E00727 0 +OP4 E00728 0 +OP4 E00729 0 +OP4 E0072A 0 +OP4 E0072B 0 +OP4 E0072C 0 +OP4 E0072D 0 +OP4 E0072E 0 +OP4 E0072F 0 +OP4 E00730 0 +OP4 E00731 0 +OP4 E00732 0 +OP4 E00733 0 +OP4 E00734 0 +OP4 E00735 0 +OP4 E00736 0 +OP4 E00737 0 +OP4 E00738 0 +OP4 E00739 0 +OP4 E0073A 0 +OP4 E0073B 0 +OP4 E0073C 0 +OP4 E0073D 0 +OP4 E0073E 0 +OP4 E0073F 0 +OP4 E00740 0 +OP4 E00741 0 +OP4 E00742 0 +OP4 E00743 0 +OP4 E00744 0 +OP4 E00745 0 +OP4 E00746 0 +OP4 E00747 0 +OP4 E00748 0 +OP4 E00749 0 +OP4 E0074A 0 +OP4 E0074B 0 +OP4 E0074C 0 +OP4 E0074D 0 +OP4 E0074E 0 +OP4 E0074F 0 +OP4 E00750 0 +OP4 E00751 0 +OP4 E00752 0 +OP4 E00753 0 +OP4 E00754 0 +OP4 E00755 0 +OP4 E00756 0 +OP4 E00757 0 +OP4 E00758 0 +OP4 E00759 0 +OP4 E0075A 0 +OP4 E0075B 0 +OP4 E0075C 0 +OP4 E0075D 0 +OP4 E0075E 0 +OP4 E0075F 0 +OP4 E00760 0 +OP4 E00761 0 +OP4 E00762 0 +OP4 E00763 0 +OP4 E00764 0 +OP4 E00765 0 +OP4 E00766 0 +OP4 E00767 0 +OP4 E00768 0 +OP4 E00769 0 +OP4 E0076A 0 +OP4 E0076B 0 +OP4 E0076C 0 +OP4 E0076D 0 +OP4 E0076E 0 +OP4 E0076F 0 +OP4 E00770 0 +OP4 E00771 0 +OP4 E00772 0 +OP4 E00773 0 +OP4 E00774 0 +OP4 E00775 0 +OP4 E00776 0 +OP4 E00777 0 +OP4 E00778 0 +OP4 E00779 0 +OP4 E0077A 0 +OP4 E0077B 0 +OP4 E0077C 0 +OP4 E0077D 0 +OP4 E0077E 0 +OP4 E0077F 0 +OP4 E00780 0 +OP4 E00781 0 +OP4 E00782 0 +OP4 E00783 0 +OP4 E00784 0 +OP4 E00785 0 +OP4 E00786 0 +OP4 E00787 0 +OP4 E00788 0 +OP4 E00789 0 +OP4 E0078A 0 +OP4 E0078B 0 +OP4 E0078C 0 +OP4 E0078D 0 +OP4 E0078E 0 +OP4 E0078F 0 +OP4 E00790 0 +OP4 E00791 0 +OP4 E00792 0 +OP4 E00793 0 +OP4 E00794 0 +OP4 E00795 0 +OP4 E00796 0 +OP4 E00797 0 +OP4 E00798 0 +OP4 E00799 0 +OP4 E0079A 0 +OP4 E0079B 0 +OP4 E0079C 0 +OP4 E0079D 0 +OP4 E0079E 0 +OP4 E0079F 0 +OP4 E007A0 0 +OP4 E007A1 0 +OP4 E007A2 0 +OP4 E007A3 0 +OP4 E007A4 0 +OP4 E007A5 0 +OP4 E007A6 0 +OP4 E007A7 0 +OP4 E007A8 0 +OP4 E007A9 0 +OP4 E007AA 0 +OP4 E007AB 0 +OP4 E007AC 0 +OP4 E007AD 0 +OP4 E007AE 0 +OP4 E007AF 0 +OP4 E007B0 0 +OP4 E007B1 0 +OP4 E007B2 0 +OP4 E007B3 0 +OP4 E007B4 0 +OP4 E007B5 0 +OP4 E007B6 0 +OP4 E007B7 0 +OP4 E007B8 0 +OP4 E007B9 0 +OP4 E007BA 0 +OP4 E007BB 0 +OP4 E007BC 0 +OP4 E007BD 0 +OP4 E007BE 0 +OP4 E007BF 0 +OP4 E007C0 0 +OP4 E007C1 0 +OP4 E007C2 0 +OP4 E007C3 0 +OP4 E007C4 0 +OP4 E007C5 0 +OP4 E007C6 0 +OP4 E007C7 0 +OP4 E007C8 0 +OP4 E007C9 0 +OP4 E007CA 0 +OP4 E007CB 0 +OP4 E007CC 0 +OP4 E007CD 0 +OP4 E007CE 0 +OP4 E007CF 0 +OP4 E007D0 0 +OP4 E007D1 0 +OP4 E007D2 0 +OP4 E007D3 0 +OP4 E007D4 0 +OP4 E007D5 0 +OP4 E007D6 0 +OP4 E007D7 0 +OP4 E007D8 0 +OP4 E007D9 0 +OP4 E007DA 0 +OP4 E007DB 0 +OP4 E007DC 0 +OP4 E007DD 0 +OP4 E007DE 0 +OP4 E007DF 0 +OP4 E007E0 0 +OP4 E007E1 0 +OP4 E007E2 0 +OP4 E007E3 0 +OP4 E007E4 0 +OP4 E007E5 0 +OP4 E007E6 0 +OP4 E007E7 0 +OP4 E007E8 0 +OP4 E007E9 0 +OP4 E007EA 0 +OP4 E007EB 0 +OP4 E007EC 0 +OP4 E007ED 0 +OP4 E007EE 0 +OP4 E007EF 0 +OP4 E007F0 0 +OP4 E007F1 0 +OP4 E007F2 0 +OP4 E007F3 0 +OP4 E007F4 0 +OP4 E007F5 0 +OP4 E007F6 0 +OP4 E007F7 0 +OP4 E007F8 0 +OP4 E007F9 0 +OP4 E007FA 0 +OP4 E007FB 0 +OP4 E007FC 0 +OP4 E007FD 0 +OP4 E007FE 0 +OP4 E007FF 0 +OP4 E00800 0 +OP4 E00801 0 +OP4 E00802 0 +OP4 E00803 0 +OP4 E00804 0 +OP4 E00805 0 +OP4 E00806 0 +OP4 E00807 0 +OP4 E00808 0 +OP4 E00809 0 +OP4 E0080A 0 +OP4 E0080B 0 +OP4 E0080C 0 +OP4 E0080D 0 +OP4 E0080E 0 +OP4 E0080F 0 +OP4 E00810 0 +OP4 E00811 0 +OP4 E00812 0 +OP4 E00813 0 +OP4 E00814 0 +OP4 E00815 0 +OP4 E00816 0 +OP4 E00817 0 +OP4 E00818 0 +OP4 E00819 0 +OP4 E0081A 0 +OP4 E0081B 0 +OP4 E0081C 0 +OP4 E0081D 0 +OP4 E0081E 0 +OP4 E0081F 0 +OP4 E00820 0 +OP4 E00821 0 +OP4 E00822 0 +OP4 E00823 0 +OP4 E00824 0 +OP4 E00825 0 +OP4 E00826 0 +OP4 E00827 0 +OP4 E00828 0 +OP4 E00829 0 +OP4 E0082A 0 +OP4 E0082B 0 +OP4 E0082C 0 +OP4 E0082D 0 +OP4 E0082E 0 +OP4 E0082F 0 +OP4 E00830 0 +OP4 E00831 0 +OP4 E00832 0 +OP4 E00833 0 +OP4 E00834 0 +OP4 E00835 0 +OP4 E00836 0 +OP4 E00837 0 +OP4 E00838 0 +OP4 E00839 0 +OP4 E0083A 0 +OP4 E0083B 0 +OP4 E0083C 0 +OP4 E0083D 0 +OP4 E0083E 0 +OP4 E0083F 0 +OP4 E00840 0 +OP4 E00841 0 +OP4 E00842 0 +OP4 E00843 0 +OP4 E00844 0 +OP4 E00845 0 +OP4 E00846 0 +OP4 E00847 0 +OP4 E00848 0 +OP4 E00849 0 +OP4 E0084A 0 +OP4 E0084B 0 +OP4 E0084C 0 +OP4 E0084D 0 +OP4 E0084E 0 +OP4 E0084F 0 +OP4 E00850 0 +OP4 E00851 0 +OP4 E00852 0 +OP4 E00853 0 +OP4 E00854 0 +OP4 E00855 0 +OP4 E00856 0 +OP4 E00857 0 +OP4 E00858 0 +OP4 E00859 0 +OP4 E0085A 0 +OP4 E0085B 0 +OP4 E0085C 0 +OP4 E0085D 0 +OP4 E0085E 0 +OP4 E0085F 0 +OP4 E00860 0 +OP4 E00861 0 +OP4 E00862 0 +OP4 E00863 0 +OP4 E00864 0 +OP4 E00865 0 +OP4 E00866 0 +OP4 E00867 0 +OP4 E00868 0 +OP4 E00869 0 +OP4 E0086A 0 +OP4 E0086B 0 +OP4 E0086C 0 +OP4 E0086D 0 +OP4 E0086E 0 +OP4 E0086F 0 +OP4 E00870 0 +OP4 E00871 0 +OP4 E00872 0 +OP4 E00873 0 +OP4 E00874 0 +OP4 E00875 0 +OP4 E00876 0 +OP4 E00877 0 +OP4 E00878 0 +OP4 E00879 0 +OP4 E0087A 0 +OP4 E0087B 0 +OP4 E0087C 0 +OP4 E0087D 0 +OP4 E0087E 0 +OP4 E0087F 0 +OP4 E00880 0 +OP4 E00881 0 +OP4 E00882 0 +OP4 E00883 0 +OP4 E00884 0 +OP4 E00885 0 +OP4 E00886 0 +OP4 E00887 0 +OP4 E00888 0 +OP4 E00889 0 +OP4 E0088A 0 +OP4 E0088B 0 +OP4 E0088C 0 +OP4 E0088D 0 +OP4 E0088E 0 +OP4 E0088F 0 +OP4 E00890 0 +OP4 E00891 0 +OP4 E00892 0 +OP4 E00893 0 +OP4 E00894 0 +OP4 E00895 0 +OP4 E00896 0 +OP4 E00897 0 +OP4 E00898 0 +OP4 E00899 0 +OP4 E0089A 0 +OP4 E0089B 0 +OP4 E0089C 0 +OP4 E0089D 0 +OP4 E0089E 0 +OP4 E0089F 0 +OP4 E008A0 0 +OP4 E008A1 0 +OP4 E008A2 0 +OP4 E008A3 0 +OP4 E008A4 0 +OP4 E008A5 0 +OP4 E008A6 0 +OP4 E008A7 0 +OP4 E008A8 0 +OP4 E008A9 0 +OP4 E008AA 0 +OP4 E008AB 0 +OP4 E008AC 0 +OP4 E008AD 0 +OP4 E008AE 0 +OP4 E008AF 0 +OP4 E008B0 0 +OP4 E008B1 0 +OP4 E008B2 0 +OP4 E008B3 0 +OP4 E008B4 0 +OP4 E008B5 0 +OP4 E008B6 0 +OP4 E008B7 0 +OP4 E008B8 0 +OP4 E008B9 0 +OP4 E008BA 0 +OP4 E008BB 0 +OP4 E008BC 0 +OP4 E008BD 0 +OP4 E008BE 0 +OP4 E008BF 0 +OP4 E008C0 0 +OP4 E008C1 0 +OP4 E008C2 0 +OP4 E008C3 0 +OP4 E008C4 0 +OP4 E008C5 0 +OP4 E008C6 0 +OP4 E008C7 0 +OP4 E008C8 0 +OP4 E008C9 0 +OP4 E008CA 0 +OP4 E008CB 0 +OP4 E008CC 0 +OP4 E008CD 0 +OP4 E008CE 0 +OP4 E008CF 0 +OP4 E008D0 0 +OP4 E008D1 0 +OP4 E008D2 0 +OP4 E008D3 0 +OP4 E008D4 0 +OP4 E008D5 0 +OP4 E008D6 0 +OP4 E008D7 0 +OP4 E008D8 0 +OP4 E008D9 0 +OP4 E008DA 0 +OP4 E008DB 0 +OP4 E008DC 0 +OP4 E008DD 0 +OP4 E008DE 0 +OP4 E008DF 0 +OP4 E008E0 0 +OP4 E008E1 0 +OP4 E008E2 0 +OP4 E008E3 0 +OP4 E008E4 0 +OP4 E008E5 0 +OP4 E008E6 0 +OP4 E008E7 0 +OP4 E008E8 0 +OP4 E008E9 0 +OP4 E008EA 0 +OP4 E008EB 0 +OP4 E008EC 0 +OP4 E008ED 0 +OP4 E008EE 0 +OP4 E008EF 0 +OP4 E008F0 0 +OP4 E008F1 0 +OP4 E008F2 0 +OP4 E008F3 0 +OP4 E008F4 0 +OP4 E008F5 0 +OP4 E008F6 0 +OP4 E008F7 0 +OP4 E008F8 0 +OP4 E008F9 0 +OP4 E008FA 0 +OP4 E008FB 0 +OP4 E008FC 0 +OP4 E008FD 0 +OP4 E008FE 0 +OP4 E008FF 0 +OP4 E00900 0 +OP4 E00901 0 +OP4 E00902 0 +OP4 E00903 0 +OP4 E00904 0 +OP4 E00905 0 +OP4 E00906 0 +OP4 E00907 0 +OP4 E00908 0 +OP4 E00909 0 +OP4 E0090A 0 +OP4 E0090B 0 +OP4 E0090C 0 +OP4 E0090D 0 +OP4 E0090E 0 +OP4 E0090F 0 +OP4 E00910 0 +OP4 E00911 0 +OP4 E00912 0 +OP4 E00913 0 +OP4 E00914 0 +OP4 E00915 0 +OP4 E00916 0 +OP4 E00917 0 +OP4 E00918 0 +OP4 E00919 0 +OP4 E0091A 0 +OP4 E0091B 0 +OP4 E0091C 0 +OP4 E0091D 0 +OP4 E0091E 0 +OP4 E0091F 0 +OP4 E00920 0 +OP4 E00921 0 +OP4 E00922 0 +OP4 E00923 0 +OP4 E00924 0 +OP4 E00925 0 +OP4 E00926 0 +OP4 E00927 0 +OP4 E00928 0 +OP4 E00929 0 +OP4 E0092A 0 +OP4 E0092B 0 +OP4 E0092C 0 +OP4 E0092D 0 +OP4 E0092E 0 +OP4 E0092F 0 +OP4 E00930 0 +OP4 E00931 0 +OP4 E00932 0 +OP4 E00933 0 +OP4 E00934 0 +OP4 E00935 0 +OP4 E00936 0 +OP4 E00937 0 +OP4 E00938 0 +OP4 E00939 0 +OP4 E0093A 0 +OP4 E0093B 0 +OP4 E0093C 0 +OP4 E0093D 0 +OP4 E0093E 0 +OP4 E0093F 0 +OP4 E00940 0 +OP4 E00941 0 +OP4 E00942 0 +OP4 E00943 0 +OP4 E00944 0 +OP4 E00945 0 +OP4 E00946 0 +OP4 E00947 0 +OP4 E00948 0 +OP4 E00949 0 +OP4 E0094A 0 +OP4 E0094B 0 +OP4 E0094C 0 +OP4 E0094D 0 +OP4 E0094E 0 +OP4 E0094F 0 +OP4 E00950 0 +OP4 E00951 0 +OP4 E00952 0 +OP4 E00953 0 +OP4 E00954 0 +OP4 E00955 0 +OP4 E00956 0 +OP4 E00957 0 +OP4 E00958 0 +OP4 E00959 0 +OP4 E0095A 0 +OP4 E0095B 0 +OP4 E0095C 0 +OP4 E0095D 0 +OP4 E0095E 0 +OP4 E0095F 0 +OP4 E00960 0 +OP4 E00961 0 +OP4 E00962 0 +OP4 E00963 0 +OP4 E00964 0 +OP4 E00965 0 +OP4 E00966 0 +OP4 E00967 0 +OP4 E00968 0 +OP4 E00969 0 +OP4 E0096A 0 +OP4 E0096B 0 +OP4 E0096C 0 +OP4 E0096D 0 +OP4 E0096E 0 +OP4 E0096F 0 +OP4 E00970 0 +OP4 E00971 0 +OP4 E00972 0 +OP4 E00973 0 +OP4 E00974 0 +OP4 E00975 0 +OP4 E00976 0 +OP4 E00977 0 +OP4 E00978 0 +OP4 E00979 0 +OP4 E0097A 0 +OP4 E0097B 0 +OP4 E0097C 0 +OP4 E0097D 0 +OP4 E0097E 0 +OP4 E0097F 0 +OP4 E00980 0 +OP4 E00981 0 +OP4 E00982 0 +OP4 E00983 0 +OP4 E00984 0 +OP4 E00985 0 +OP4 E00986 0 +OP4 E00987 0 +OP4 E00988 0 +OP4 E00989 0 +OP4 E0098A 0 +OP4 E0098B 0 +OP4 E0098C 0 +OP4 E0098D 0 +OP4 E0098E 0 +OP4 E0098F 0 +OP4 E00990 0 +OP4 E00991 0 +OP4 E00992 0 +OP4 E00993 0 +OP4 E00994 0 +OP4 E00995 0 +OP4 E00996 0 +OP4 E00997 0 +OP4 E00998 0 +OP4 E00999 0 +OP4 E0099A 0 +OP4 E0099B 0 +OP4 E0099C 0 +OP4 E0099D 0 +OP4 E0099E 0 +OP4 E0099F 0 +OP4 E009A0 0 +OP4 E009A1 0 +OP4 E009A2 0 +OP4 E009A3 0 +OP4 E009A4 0 +OP4 E009A5 0 +OP4 E009A6 0 +OP4 E009A7 0 +OP4 E009A8 0 +OP4 E009A9 0 +OP4 E009AA 0 +OP4 E009AB 0 +OP4 E009AC 0 +OP4 E009AD 0 +OP4 E009AE 0 +OP4 E009AF 0 +OP4 E009B0 0 +OP4 E009B1 0 +OP4 E009B2 0 +OP4 E009B3 0 +OP4 E009B4 0 +OP4 E009B5 0 +OP4 E009B6 0 +OP4 E009B7 0 +OP4 E009B8 0 +OP4 E009B9 0 +OP4 E009BA 0 +OP4 E009BB 0 +OP4 E009BC 0 +OP4 E009BD 0 +OP4 E009BE 0 +OP4 E009BF 0 +OP4 E009C0 0 +OP4 E009C1 0 +OP4 E009C2 0 +OP4 E009C3 0 +OP4 E009C4 0 +OP4 E009C5 0 +OP4 E009C6 0 +OP4 E009C7 0 +OP4 E009C8 0 +OP4 E009C9 0 +OP4 E009CA 0 +OP4 E009CB 0 +OP4 E009CC 0 +OP4 E009CD 0 +OP4 E009CE 0 +OP4 E009CF 0 +OP4 E009D0 0 +OP4 E009D1 0 +OP4 E009D2 0 +OP4 E009D3 0 +OP4 E009D4 0 +OP4 E009D5 0 +OP4 E009D6 0 +OP4 E009D7 0 +OP4 E009D8 0 +OP4 E009D9 0 +OP4 E009DA 0 +OP4 E009DB 0 +OP4 E009DC 0 +OP4 E009DD 0 +OP4 E009DE 0 +OP4 E009DF 0 +OP4 E009E0 0 +OP4 E009E1 0 +OP4 E009E2 0 +OP4 E009E3 0 +OP4 E009E4 0 +OP4 E009E5 0 +OP4 E009E6 0 +OP4 E009E7 0 +OP4 E009E8 0 +OP4 E009E9 0 +OP4 E009EA 0 +OP4 E009EB 0 +OP4 E009EC 0 +OP4 E009ED 0 +OP4 E009EE 0 +OP4 E009EF 0 +OP4 E009F0 0 +OP4 E009F1 0 +OP4 E009F2 0 +OP4 E009F3 0 +OP4 E009F4 0 +OP4 E009F5 0 +OP4 E009F6 0 +OP4 E009F7 0 +OP4 E009F8 0 +OP4 E009F9 0 +OP4 E009FA 0 +OP4 E009FB 0 +OP4 E009FC 0 +OP4 E009FD 0 +OP4 E009FE 0 +OP4 E009FF 0 +OP4 E00A00 0 +OP4 E00A01 0 +OP4 E00A02 0 +OP4 E00A03 0 +OP4 E00A04 0 +OP4 E00A05 0 +OP4 E00A06 0 +OP4 E00A07 0 +OP4 E00A08 0 +OP4 E00A09 0 +OP4 E00A0A 0 +OP4 E00A0B 0 +OP4 E00A0C 0 +OP4 E00A0D 0 +OP4 E00A0E 0 +OP4 E00A0F 0 +OP4 E00A10 0 +OP4 E00A11 0 +OP4 E00A12 0 +OP4 E00A13 0 +OP4 E00A14 0 +OP4 E00A15 0 +OP4 E00A16 0 +OP4 E00A17 0 +OP4 E00A18 0 +OP4 E00A19 0 +OP4 E00A1A 0 +OP4 E00A1B 0 +OP4 E00A1C 0 +OP4 E00A1D 0 +OP4 E00A1E 0 +OP4 E00A1F 0 +OP4 E00A20 0 +OP4 E00A21 0 +OP4 E00A22 0 +OP4 E00A23 0 +OP4 E00A24 0 +OP4 E00A25 0 +OP4 E00A26 0 +OP4 E00A27 0 +OP4 E00A28 0 +OP4 E00A29 0 +OP4 E00A2A 0 +OP4 E00A2B 0 +OP4 E00A2C 0 +OP4 E00A2D 0 +OP4 E00A2E 0 +OP4 E00A2F 0 +OP4 E00A30 0 +OP4 E00A31 0 +OP4 E00A32 0 +OP4 E00A33 0 +OP4 E00A34 0 +OP4 E00A35 0 +OP4 E00A36 0 +OP4 E00A37 0 +OP4 E00A38 0 +OP4 E00A39 0 +OP4 E00A3A 0 +OP4 E00A3B 0 +OP4 E00A3C 0 +OP4 E00A3D 0 +OP4 E00A3E 0 +OP4 E00A3F 0 +OP4 E00A40 0 +OP4 E00A41 0 +OP4 E00A42 0 +OP4 E00A43 0 +OP4 E00A44 0 +OP4 E00A45 0 +OP4 E00A46 0 +OP4 E00A47 0 +OP4 E00A48 0 +OP4 E00A49 0 +OP4 E00A4A 0 +OP4 E00A4B 0 +OP4 E00A4C 0 +OP4 E00A4D 0 +OP4 E00A4E 0 +OP4 E00A4F 0 +OP4 E00A50 0 +OP4 E00A51 0 +OP4 E00A52 0 +OP4 E00A53 0 +OP4 E00A54 0 +OP4 E00A55 0 +OP4 E00A56 0 +OP4 E00A57 0 +OP4 E00A58 0 +OP4 E00A59 0 +OP4 E00A5A 0 +OP4 E00A5B 0 +OP4 E00A5C 0 +OP4 E00A5D 0 +OP4 E00A5E 0 +OP4 E00A5F 0 +OP4 E00A60 0 +OP4 E00A61 0 +OP4 E00A62 0 +OP4 E00A63 0 +OP4 E00A64 0 +OP4 E00A65 0 +OP4 E00A66 0 +OP4 E00A67 0 +OP4 E00A68 0 +OP4 E00A69 0 +OP4 E00A6A 0 +OP4 E00A6B 0 +OP4 E00A6C 0 +OP4 E00A6D 0 +OP4 E00A6E 0 +OP4 E00A6F 0 +OP4 E00A70 0 +OP4 E00A71 0 +OP4 E00A72 0 +OP4 E00A73 0 +OP4 E00A74 0 +OP4 E00A75 0 +OP4 E00A76 0 +OP4 E00A77 0 +OP4 E00A78 0 +OP4 E00A79 0 +OP4 E00A7A 0 +OP4 E00A7B 0 +OP4 E00A7C 0 +OP4 E00A7D 0 +OP4 E00A7E 0 +OP4 E00A7F 0 +OP4 E00A80 0 +OP4 E00A81 0 +OP4 E00A82 0 +OP4 E00A83 0 +OP4 E00A84 0 +OP4 E00A85 0 +OP4 E00A86 0 +OP4 E00A87 0 +OP4 E00A88 0 +OP4 E00A89 0 +OP4 E00A8A 0 +OP4 E00A8B 0 +OP4 E00A8C 0 +OP4 E00A8D 0 +OP4 E00A8E 0 +OP4 E00A8F 0 +OP4 E00A90 0 +OP4 E00A91 0 +OP4 E00A92 0 +OP4 E00A93 0 +OP4 E00A94 0 +OP4 E00A95 0 +OP4 E00A96 0 +OP4 E00A97 0 +OP4 E00A98 0 +OP4 E00A99 0 +OP4 E00A9A 0 +OP4 E00A9B 0 +OP4 E00A9C 0 +OP4 E00A9D 0 +OP4 E00A9E 0 +OP4 E00A9F 0 +OP4 E00AA0 0 +OP4 E00AA1 0 +OP4 E00AA2 0 +OP4 E00AA3 0 +OP4 E00AA4 0 +OP4 E00AA5 0 +OP4 E00AA6 0 +OP4 E00AA7 0 +OP4 E00AA8 0 +OP4 E00AA9 0 +OP4 E00AAA 0 +OP4 E00AAB 0 +OP4 E00AAC 0 +OP4 E00AAD 0 +OP4 E00AAE 0 +OP4 E00AAF 0 +OP4 E00AB0 0 +OP4 E00AB1 0 +OP4 E00AB2 0 +OP4 E00AB3 0 +OP4 E00AB4 0 +OP4 E00AB5 0 +OP4 E00AB6 0 +OP4 E00AB7 0 +OP4 E00AB8 0 +OP4 E00AB9 0 +OP4 E00ABA 0 +OP4 E00ABB 0 +OP4 E00ABC 0 +OP4 E00ABD 0 +OP4 E00ABE 0 +OP4 E00ABF 0 +OP4 E00AC0 0 +OP4 E00AC1 0 +OP4 E00AC2 0 +OP4 E00AC3 0 +OP4 E00AC4 0 +OP4 E00AC5 0 +OP4 E00AC6 0 +OP4 E00AC7 0 +OP4 E00AC8 0 +OP4 E00AC9 0 +OP4 E00ACA 0 +OP4 E00ACB 0 +OP4 E00ACC 0 +OP4 E00ACD 0 +OP4 E00ACE 0 +OP4 E00ACF 0 +OP4 E00AD0 0 +OP4 E00AD1 0 +OP4 E00AD2 0 +OP4 E00AD3 0 +OP4 E00AD4 0 +OP4 E00AD5 0 +OP4 E00AD6 0 +OP4 E00AD7 0 +OP4 E00AD8 0 +OP4 E00AD9 0 +OP4 E00ADA 0 +OP4 E00ADB 0 +OP4 E00ADC 0 +OP4 E00ADD 0 +OP4 E00ADE 0 +OP4 E00ADF 0 +OP4 E00AE0 0 +OP4 E00AE1 0 +OP4 E00AE2 0 +OP4 E00AE3 0 +OP4 E00AE4 0 +OP4 E00AE5 0 +OP4 E00AE6 0 +OP4 E00AE7 0 +OP4 E00AE8 0 +OP4 E00AE9 0 +OP4 E00AEA 0 +OP4 E00AEB 0 +OP4 E00AEC 0 +OP4 E00AED 0 +OP4 E00AEE 0 +OP4 E00AEF 0 +OP4 E00AF0 0 +OP4 E00AF1 0 +OP4 E00AF2 0 +OP4 E00AF3 0 +OP4 E00AF4 0 +OP4 E00AF5 0 +OP4 E00AF6 0 +OP4 E00AF7 0 +OP4 E00AF8 0 +OP4 E00AF9 0 +OP4 E00AFA 0 +OP4 E00AFB 0 +OP4 E00AFC 0 +OP4 E00AFD 0 +OP4 E00AFE 0 +OP4 E00AFF 0 +OP4 E00B00 0 +OP4 E00B01 0 +OP4 E00B02 0 +OP4 E00B03 0 +OP4 E00B04 0 +OP4 E00B05 0 +OP4 E00B06 0 +OP4 E00B07 0 +OP4 E00B08 0 +OP4 E00B09 0 +OP4 E00B0A 0 +OP4 E00B0B 0 +OP4 E00B0C 0 +OP4 E00B0D 0 +OP4 E00B0E 0 +OP4 E00B0F 0 +OP4 E00B10 0 +OP4 E00B11 0 +OP4 E00B12 0 +OP4 E00B13 0 +OP4 E00B14 0 +OP4 E00B15 0 +OP4 E00B16 0 +OP4 E00B17 0 +OP4 E00B18 0 +OP4 E00B19 0 +OP4 E00B1A 0 +OP4 E00B1B 0 +OP4 E00B1C 0 +OP4 E00B1D 0 +OP4 E00B1E 0 +OP4 E00B1F 0 +OP4 E00B20 0 +OP4 E00B21 0 +OP4 E00B22 0 +OP4 E00B23 0 +OP4 E00B24 0 +OP4 E00B25 0 +OP4 E00B26 0 +OP4 E00B27 0 +OP4 E00B28 0 +OP4 E00B29 0 +OP4 E00B2A 0 +OP4 E00B2B 0 +OP4 E00B2C 0 +OP4 E00B2D 0 +OP4 E00B2E 0 +OP4 E00B2F 0 +OP4 E00B30 0 +OP4 E00B31 0 +OP4 E00B32 0 +OP4 E00B33 0 +OP4 E00B34 0 +OP4 E00B35 0 +OP4 E00B36 0 +OP4 E00B37 0 +OP4 E00B38 0 +OP4 E00B39 0 +OP4 E00B3A 0 +OP4 E00B3B 0 +OP4 E00B3C 0 +OP4 E00B3D 0 +OP4 E00B3E 0 +OP4 E00B3F 0 +OP4 E00B40 0 +OP4 E00B41 0 +OP4 E00B42 0 +OP4 E00B43 0 +OP4 E00B44 0 +OP4 E00B45 0 +OP4 E00B46 0 +OP4 E00B47 0 +OP4 E00B48 0 +OP4 E00B49 0 +OP4 E00B4A 0 +OP4 E00B4B 0 +OP4 E00B4C 0 +OP4 E00B4D 0 +OP4 E00B4E 0 +OP4 E00B4F 0 +OP4 E00B50 0 +OP4 E00B51 0 +OP4 E00B52 0 +OP4 E00B53 0 +OP4 E00B54 0 +OP4 E00B55 0 +OP4 E00B56 0 +OP4 E00B57 0 +OP4 E00B58 0 +OP4 E00B59 0 +OP4 E00B5A 0 +OP4 E00B5B 0 +OP4 E00B5C 0 +OP4 E00B5D 0 +OP4 E00B5E 0 +OP4 E00B5F 0 +OP4 E00B60 0 +OP4 E00B61 0 +OP4 E00B62 0 +OP4 E00B63 0 +OP4 E00B64 0 +OP4 E00B65 0 +OP4 E00B66 0 +OP4 E00B67 0 +OP4 E00B68 0 +OP4 E00B69 0 +OP4 E00B6A 0 +OP4 E00B6B 0 +OP4 E00B6C 0 +OP4 E00B6D 0 +OP4 E00B6E 0 +OP4 E00B6F 0 +OP4 E00B70 0 +OP4 E00B71 0 +OP4 E00B72 0 +OP4 E00B73 0 +OP4 E00B74 0 +OP4 E00B75 0 +OP4 E00B76 0 +OP4 E00B77 0 +OP4 E00B78 0 +OP4 E00B79 0 +OP4 E00B7A 0 +OP4 E00B7B 0 +OP4 E00B7C 0 +OP4 E00B7D 0 +OP4 E00B7E 0 +OP4 E00B7F 0 +OP4 E00B80 0 +OP4 E00B81 0 +OP4 E00B82 0 +OP4 E00B83 0 +OP4 E00B84 0 +OP4 E00B85 0 +OP4 E00B86 0 +OP4 E00B87 0 +OP4 E00B88 0 +OP4 E00B89 0 +OP4 E00B8A 0 +OP4 E00B8B 0 +OP4 E00B8C 0 +OP4 E00B8D 0 +OP4 E00B8E 0 +OP4 E00B8F 0 +OP4 E00B90 0 +OP4 E00B91 0 +OP4 E00B92 0 +OP4 E00B93 0 +OP4 E00B94 0 +OP4 E00B95 0 +OP4 E00B96 0 +OP4 E00B97 0 +OP4 E00B98 0 +OP4 E00B99 0 +OP4 E00B9A 0 +OP4 E00B9B 0 +OP4 E00B9C 0 +OP4 E00B9D 0 +OP4 E00B9E 0 +OP4 E00B9F 0 +OP4 E00BA0 0 +OP4 E00BA1 0 +OP4 E00BA2 0 +OP4 E00BA3 0 +OP4 E00BA4 0 +OP4 E00BA5 0 +OP4 E00BA6 0 +OP4 E00BA7 0 +OP4 E00BA8 0 +OP4 E00BA9 0 +OP4 E00BAA 0 +OP4 E00BAB 0 +OP4 E00BAC 0 +OP4 E00BAD 0 +OP4 E00BAE 0 +OP4 E00BAF 0 +OP4 E00BB0 0 +OP4 E00BB1 0 +OP4 E00BB2 0 +OP4 E00BB3 0 +OP4 E00BB4 0 +OP4 E00BB5 0 +OP4 E00BB6 0 +OP4 E00BB7 0 +OP4 E00BB8 0 +OP4 E00BB9 0 +OP4 E00BBA 0 +OP4 E00BBB 0 +OP4 E00BBC 0 +OP4 E00BBD 0 +OP4 E00BBE 0 +OP4 E00BBF 0 +OP4 E00BC0 0 +OP4 E00BC1 0 +OP4 E00BC2 0 +OP4 E00BC3 0 +OP4 E00BC4 0 +OP4 E00BC5 0 +OP4 E00BC6 0 +OP4 E00BC7 0 +OP4 E00BC8 0 +OP4 E00BC9 0 +OP4 E00BCA 0 +OP4 E00BCB 0 +OP4 E00BCC 0 +OP4 E00BCD 0 +OP4 E00BCE 0 +OP4 E00BCF 0 +OP4 E00BD0 0 +OP4 E00BD1 0 +OP4 E00BD2 0 +OP4 E00BD3 0 +OP4 E00BD4 0 +OP4 E00BD5 0 +OP4 E00BD6 0 +OP4 E00BD7 0 +OP4 E00BD8 0 +OP4 E00BD9 0 +OP4 E00BDA 0 +OP4 E00BDB 0 +OP4 E00BDC 0 +OP4 E00BDD 0 +OP4 E00BDE 0 +OP4 E00BDF 0 +OP4 E00BE0 0 +OP4 E00BE1 0 +OP4 E00BE2 0 +OP4 E00BE3 0 +OP4 E00BE4 0 +OP4 E00BE5 0 +OP4 E00BE6 0 +OP4 E00BE7 0 +OP4 E00BE8 0 +OP4 E00BE9 0 +OP4 E00BEA 0 +OP4 E00BEB 0 +OP4 E00BEC 0 +OP4 E00BED 0 +OP4 E00BEE 0 +OP4 E00BEF 0 +OP4 E00BF0 0 +OP4 E00BF1 0 +OP4 E00BF2 0 +OP4 E00BF3 0 +OP4 E00BF4 0 +OP4 E00BF5 0 +OP4 E00BF6 0 +OP4 E00BF7 0 +OP4 E00BF8 0 +OP4 E00BF9 0 +OP4 E00BFA 0 +OP4 E00BFB 0 +OP4 E00BFC 0 +OP4 E00BFD 0 +OP4 E00BFE 0 +OP4 E00BFF 0 +OP4 E00C00 0 +OP4 E00C01 0 +OP4 E00C02 0 +OP4 E00C03 0 +OP4 E00C04 0 +OP4 E00C05 0 +OP4 E00C06 0 +OP4 E00C07 0 +OP4 E00C08 0 +OP4 E00C09 0 +OP4 E00C0A 0 +OP4 E00C0B 0 +OP4 E00C0C 0 +OP4 E00C0D 0 +OP4 E00C0E 0 +OP4 E00C0F 0 +OP4 E00C10 0 +OP4 E00C11 0 +OP4 E00C12 0 +OP4 E00C13 0 +OP4 E00C14 0 +OP4 E00C15 0 +OP4 E00C16 0 +OP4 E00C17 0 +OP4 E00C18 0 +OP4 E00C19 0 +OP4 E00C1A 0 +OP4 E00C1B 0 +OP4 E00C1C 0 +OP4 E00C1D 0 +OP4 E00C1E 0 +OP4 E00C1F 0 +OP4 E00C20 0 +OP4 E00C21 0 +OP4 E00C22 0 +OP4 E00C23 0 +OP4 E00C24 0 +OP4 E00C25 0 +OP4 E00C26 0 +OP4 E00C27 0 +OP4 E00C28 0 +OP4 E00C29 0 +OP4 E00C2A 0 +OP4 E00C2B 0 +OP4 E00C2C 0 +OP4 E00C2D 0 +OP4 E00C2E 0 +OP4 E00C2F 0 +OP4 E00C30 0 +OP4 E00C31 0 +OP4 E00C32 0 +OP4 E00C33 0 +OP4 E00C34 0 +OP4 E00C35 0 +OP4 E00C36 0 +OP4 E00C37 0 +OP4 E00C38 0 +OP4 E00C39 0 +OP4 E00C3A 0 +OP4 E00C3B 0 +OP4 E00C3C 0 +OP4 E00C3D 0 +OP4 E00C3E 0 +OP4 E00C3F 0 +OP4 E00C40 0 +OP4 E00C41 0 +OP4 E00C42 0 +OP4 E00C43 0 +OP4 E00C44 0 +OP4 E00C45 0 +OP4 E00C46 0 +OP4 E00C47 0 +OP4 E00C48 0 +OP4 E00C49 0 +OP4 E00C4A 0 +OP4 E00C4B 0 +OP4 E00C4C 0 +OP4 E00C4D 0 +OP4 E00C4E 0 +OP4 E00C4F 0 +OP4 E00C50 0 +OP4 E00C51 0 +OP4 E00C52 0 +OP4 E00C53 0 +OP4 E00C54 0 +OP4 E00C55 0 +OP4 E00C56 0 +OP4 E00C57 0 +OP4 E00C58 0 +OP4 E00C59 0 +OP4 E00C5A 0 +OP4 E00C5B 0 +OP4 E00C5C 0 +OP4 E00C5D 0 +OP4 E00C5E 0 +OP4 E00C5F 0 +OP4 E00C60 0 +OP4 E00C61 0 +OP4 E00C62 0 +OP4 E00C63 0 +OP4 E00C64 0 +OP4 E00C65 0 +OP4 E00C66 0 +OP4 E00C67 0 +OP4 E00C68 0 +OP4 E00C69 0 +OP4 E00C6A 0 +OP4 E00C6B 0 +OP4 E00C6C 0 +OP4 E00C6D 0 +OP4 E00C6E 0 +OP4 E00C6F 0 +OP4 E00C70 0 +OP4 E00C71 0 +OP4 E00C72 0 +OP4 E00C73 0 +OP4 E00C74 0 +OP4 E00C75 0 +OP4 E00C76 0 +OP4 E00C77 0 +OP4 E00C78 0 +OP4 E00C79 0 +OP4 E00C7A 0 +OP4 E00C7B 0 +OP4 E00C7C 0 +OP4 E00C7D 0 +OP4 E00C7E 0 +OP4 E00C7F 0 +OP4 E00C80 0 +OP4 E00C81 0 +OP4 E00C82 0 +OP4 E00C83 0 +OP4 E00C84 0 +OP4 E00C85 0 +OP4 E00C86 0 +OP4 E00C87 0 +OP4 E00C88 0 +OP4 E00C89 0 +OP4 E00C8A 0 +OP4 E00C8B 0 +OP4 E00C8C 0 +OP4 E00C8D 0 +OP4 E00C8E 0 +OP4 E00C8F 0 +OP4 E00C90 0 +OP4 E00C91 0 +OP4 E00C92 0 +OP4 E00C93 0 +OP4 E00C94 0 +OP4 E00C95 0 +OP4 E00C96 0 +OP4 E00C97 0 +OP4 E00C98 0 +OP4 E00C99 0 +OP4 E00C9A 0 +OP4 E00C9B 0 +OP4 E00C9C 0 +OP4 E00C9D 0 +OP4 E00C9E 0 +OP4 E00C9F 0 +OP4 E00CA0 0 +OP4 E00CA1 0 +OP4 E00CA2 0 +OP4 E00CA3 0 +OP4 E00CA4 0 +OP4 E00CA5 0 +OP4 E00CA6 0 +OP4 E00CA7 0 +OP4 E00CA8 0 +OP4 E00CA9 0 +OP4 E00CAA 0 +OP4 E00CAB 0 +OP4 E00CAC 0 +OP4 E00CAD 0 +OP4 E00CAE 0 +OP4 E00CAF 0 +OP4 E00CB0 0 +OP4 E00CB1 0 +OP4 E00CB2 0 +OP4 E00CB3 0 +OP4 E00CB4 0 +OP4 E00CB5 0 +OP4 E00CB6 0 +OP4 E00CB7 0 +OP4 E00CB8 0 +OP4 E00CB9 0 +OP4 E00CBA 0 +OP4 E00CBB 0 +OP4 E00CBC 0 +OP4 E00CBD 0 +OP4 E00CBE 0 +OP4 E00CBF 0 +OP4 E00CC0 0 +OP4 E00CC1 0 +OP4 E00CC2 0 +OP4 E00CC3 0 +OP4 E00CC4 0 +OP4 E00CC5 0 +OP4 E00CC6 0 +OP4 E00CC7 0 +OP4 E00CC8 0 +OP4 E00CC9 0 +OP4 E00CCA 0 +OP4 E00CCB 0 +OP4 E00CCC 0 +OP4 E00CCD 0 +OP4 E00CCE 0 +OP4 E00CCF 0 +OP4 E00CD0 0 +OP4 E00CD1 0 +OP4 E00CD2 0 +OP4 E00CD3 0 +OP4 E00CD4 0 +OP4 E00CD5 0 +OP4 E00CD6 0 +OP4 E00CD7 0 +OP4 E00CD8 0 +OP4 E00CD9 0 +OP4 E00CDA 0 +OP4 E00CDB 0 +OP4 E00CDC 0 +OP4 E00CDD 0 +OP4 E00CDE 0 +OP4 E00CDF 0 +OP4 E00CE0 0 +OP4 E00CE1 0 +OP4 E00CE2 0 +OP4 E00CE3 0 +OP4 E00CE4 0 +OP4 E00CE5 0 +OP4 E00CE6 0 +OP4 E00CE7 0 +OP4 E00CE8 0 +OP4 E00CE9 0 +OP4 E00CEA 0 +OP4 E00CEB 0 +OP4 E00CEC 0 +OP4 E00CED 0 +OP4 E00CEE 0 +OP4 E00CEF 0 +OP4 E00CF0 0 +OP4 E00CF1 0 +OP4 E00CF2 0 +OP4 E00CF3 0 +OP4 E00CF4 0 +OP4 E00CF5 0 +OP4 E00CF6 0 +OP4 E00CF7 0 +OP4 E00CF8 0 +OP4 E00CF9 0 +OP4 E00CFA 0 +OP4 E00CFB 0 +OP4 E00CFC 0 +OP4 E00CFD 0 +OP4 E00CFE 0 +OP4 E00CFF 0 +OP4 E00D00 0 +OP4 E00D01 0 +OP4 E00D02 0 +OP4 E00D03 0 +OP4 E00D04 0 +OP4 E00D05 0 +OP4 E00D06 0 +OP4 E00D07 0 +OP4 E00D08 0 +OP4 E00D09 0 +OP4 E00D0A 0 +OP4 E00D0B 0 +OP4 E00D0C 0 +OP4 E00D0D 0 +OP4 E00D0E 0 +OP4 E00D0F 0 +OP4 E00D10 0 +OP4 E00D11 0 +OP4 E00D12 0 +OP4 E00D13 0 +OP4 E00D14 0 +OP4 E00D15 0 +OP4 E00D16 0 +OP4 E00D17 0 +OP4 E00D18 0 +OP4 E00D19 0 +OP4 E00D1A 0 +OP4 E00D1B 0 +OP4 E00D1C 0 +OP4 E00D1D 0 +OP4 E00D1E 0 +OP4 E00D1F 0 +OP4 E00D20 0 +OP4 E00D21 0 +OP4 E00D22 0 +OP4 E00D23 0 +OP4 E00D24 0 +OP4 E00D25 0 +OP4 E00D26 0 +OP4 E00D27 0 +OP4 E00D28 0 +OP4 E00D29 0 +OP4 E00D2A 0 +OP4 E00D2B 0 +OP4 E00D2C 0 +OP4 E00D2D 0 +OP4 E00D2E 0 +OP4 E00D2F 0 +OP4 E00D30 0 +OP4 E00D31 0 +OP4 E00D32 0 +OP4 E00D33 0 +OP4 E00D34 0 +OP4 E00D35 0 +OP4 E00D36 0 +OP4 E00D37 0 +OP4 E00D38 0 +OP4 E00D39 0 +OP4 E00D3A 0 +OP4 E00D3B 0 +OP4 E00D3C 0 +OP4 E00D3D 0 +OP4 E00D3E 0 +OP4 E00D3F 0 +OP4 E00D40 0 +OP4 E00D41 0 +OP4 E00D42 0 +OP4 E00D43 0 +OP4 E00D44 0 +OP4 E00D45 0 +OP4 E00D46 0 +OP4 E00D47 0 +OP4 E00D48 0 +OP4 E00D49 0 +OP4 E00D4A 0 +OP4 E00D4B 0 +OP4 E00D4C 0 +OP4 E00D4D 0 +OP4 E00D4E 0 +OP4 E00D4F 0 +OP4 E00D50 0 +OP4 E00D51 0 +OP4 E00D52 0 +OP4 E00D53 0 +OP4 E00D54 0 +OP4 E00D55 0 +OP4 E00D56 0 +OP4 E00D57 0 +OP4 E00D58 0 +OP4 E00D59 0 +OP4 E00D5A 0 +OP4 E00D5B 0 +OP4 E00D5C 0 +OP4 E00D5D 0 +OP4 E00D5E 0 +OP4 E00D5F 0 +OP4 E00D60 0 +OP4 E00D61 0 +OP4 E00D62 0 +OP4 E00D63 0 +OP4 E00D64 0 +OP4 E00D65 0 +OP4 E00D66 0 +OP4 E00D67 0 +OP4 E00D68 0 +OP4 E00D69 0 +OP4 E00D6A 0 +OP4 E00D6B 0 +OP4 E00D6C 0 +OP4 E00D6D 0 +OP4 E00D6E 0 +OP4 E00D6F 0 +OP4 E00D70 0 +OP4 E00D71 0 +OP4 E00D72 0 +OP4 E00D73 0 +OP4 E00D74 0 +OP4 E00D75 0 +OP4 E00D76 0 +OP4 E00D77 0 +OP4 E00D78 0 +OP4 E00D79 0 +OP4 E00D7A 0 +OP4 E00D7B 0 +OP4 E00D7C 0 +OP4 E00D7D 0 +OP4 E00D7E 0 +OP4 E00D7F 0 +OP4 E00D80 0 +OP4 E00D81 0 +OP4 E00D82 0 +OP4 E00D83 0 +OP4 E00D84 0 +OP4 E00D85 0 +OP4 E00D86 0 +OP4 E00D87 0 +OP4 E00D88 0 +OP4 E00D89 0 +OP4 E00D8A 0 +OP4 E00D8B 0 +OP4 E00D8C 0 +OP4 E00D8D 0 +OP4 E00D8E 0 +OP4 E00D8F 0 +OP4 E00D90 0 +OP4 E00D91 0 +OP4 E00D92 0 +OP4 E00D93 0 +OP4 E00D94 0 +OP4 E00D95 0 +OP4 E00D96 0 +OP4 E00D97 0 +OP4 E00D98 0 +OP4 E00D99 0 +OP4 E00D9A 0 +OP4 E00D9B 0 +OP4 E00D9C 0 +OP4 E00D9D 0 +OP4 E00D9E 0 +OP4 E00D9F 0 +OP4 E00DA0 0 +OP4 E00DA1 0 +OP4 E00DA2 0 +OP4 E00DA3 0 +OP4 E00DA4 0 +OP4 E00DA5 0 +OP4 E00DA6 0 +OP4 E00DA7 0 +OP4 E00DA8 0 +OP4 E00DA9 0 +OP4 E00DAA 0 +OP4 E00DAB 0 +OP4 E00DAC 0 +OP4 E00DAD 0 +OP4 E00DAE 0 +OP4 E00DAF 0 +OP4 E00DB0 0 +OP4 E00DB1 0 +OP4 E00DB2 0 +OP4 E00DB3 0 +OP4 E00DB4 0 +OP4 E00DB5 0 +OP4 E00DB6 0 +OP4 E00DB7 0 +OP4 E00DB8 0 +OP4 E00DB9 0 +OP4 E00DBA 0 +OP4 E00DBB 0 +OP4 E00DBC 0 +OP4 E00DBD 0 +OP4 E00DBE 0 +OP4 E00DBF 0 +OP4 E00DC0 0 +OP4 E00DC1 0 +OP4 E00DC2 0 +OP4 E00DC3 0 +OP4 E00DC4 0 +OP4 E00DC5 0 +OP4 E00DC6 0 +OP4 E00DC7 0 +OP4 E00DC8 0 +OP4 E00DC9 0 +OP4 E00DCA 0 +OP4 E00DCB 0 +OP4 E00DCC 0 +OP4 E00DCD 0 +OP4 E00DCE 0 +OP4 E00DCF 0 +OP4 E00DD0 0 +OP4 E00DD1 0 +OP4 E00DD2 0 +OP4 E00DD3 0 +OP4 E00DD4 0 +OP4 E00DD5 0 +OP4 E00DD6 0 +OP4 E00DD7 0 +OP4 E00DD8 0 +OP4 E00DD9 0 +OP4 E00DDA 0 +OP4 E00DDB 0 +OP4 E00DDC 0 +OP4 E00DDD 0 +OP4 E00DDE 0 +OP4 E00DDF 0 +OP4 E00DE0 0 +OP4 E00DE1 0 +OP4 E00DE2 0 +OP4 E00DE3 0 +OP4 E00DE4 0 +OP4 E00DE5 0 +OP4 E00DE6 0 +OP4 E00DE7 0 +OP4 E00DE8 0 +OP4 E00DE9 0 +OP4 E00DEA 0 +OP4 E00DEB 0 +OP4 E00DEC 0 +OP4 E00DED 0 +OP4 E00DEE 0 +OP4 E00DEF 0 +OP4 E00DF0 0 +OP4 E00DF1 0 +OP4 E00DF2 0 +OP4 E00DF3 0 +OP4 E00DF4 0 +OP4 E00DF5 0 +OP4 E00DF6 0 +OP4 E00DF7 0 +OP4 E00DF8 0 +OP4 E00DF9 0 +OP4 E00DFA 0 +OP4 E00DFB 0 +OP4 E00DFC 0 +OP4 E00DFD 0 +OP4 E00DFE 0 +OP4 E00DFF 0 +OP4 E00E00 0 +OP4 E00E01 0 +OP4 E00E02 0 +OP4 E00E03 0 +OP4 E00E04 0 +OP4 E00E05 0 +OP4 E00E06 0 +OP4 E00E07 0 +OP4 E00E08 0 +OP4 E00E09 0 +OP4 E00E0A 0 +OP4 E00E0B 0 +OP4 E00E0C 0 +OP4 E00E0D 0 +OP4 E00E0E 0 +OP4 E00E0F 0 +OP4 E00E10 0 +OP4 E00E11 0 +OP4 E00E12 0 +OP4 E00E13 0 +OP4 E00E14 0 +OP4 E00E15 0 +OP4 E00E16 0 +OP4 E00E17 0 +OP4 E00E18 0 +OP4 E00E19 0 +OP4 E00E1A 0 +OP4 E00E1B 0 +OP4 E00E1C 0 +OP4 E00E1D 0 +OP4 E00E1E 0 +OP4 E00E1F 0 +OP4 E00E20 0 +OP4 E00E21 0 +OP4 E00E22 0 +OP4 E00E23 0 +OP4 E00E24 0 +OP4 E00E25 0 +OP4 E00E26 0 +OP4 E00E27 0 +OP4 E00E28 0 +OP4 E00E29 0 +OP4 E00E2A 0 +OP4 E00E2B 0 +OP4 E00E2C 0 +OP4 E00E2D 0 +OP4 E00E2E 0 +OP4 E00E2F 0 +OP4 E00E30 0 +OP4 E00E31 0 +OP4 E00E32 0 +OP4 E00E33 0 +OP4 E00E34 0 +OP4 E00E35 0 +OP4 E00E36 0 +OP4 E00E37 0 +OP4 E00E38 0 +OP4 E00E39 0 +OP4 E00E3A 0 +OP4 E00E3B 0 +OP4 E00E3C 0 +OP4 E00E3D 0 +OP4 E00E3E 0 +OP4 E00E3F 0 +OP4 E00E40 0 +OP4 E00E41 0 +OP4 E00E42 0 +OP4 E00E43 0 +OP4 E00E44 0 +OP4 E00E45 0 +OP4 E00E46 0 +OP4 E00E47 0 +OP4 E00E48 0 +OP4 E00E49 0 +OP4 E00E4A 0 +OP4 E00E4B 0 +OP4 E00E4C 0 +OP4 E00E4D 0 +OP4 E00E4E 0 +OP4 E00E4F 0 +OP4 E00E50 0 +OP4 E00E51 0 +OP4 E00E52 0 +OP4 E00E53 0 +OP4 E00E54 0 +OP4 E00E55 0 +OP4 E00E56 0 +OP4 E00E57 0 +OP4 E00E58 0 +OP4 E00E59 0 +OP4 E00E5A 0 +OP4 E00E5B 0 +OP4 E00E5C 0 +OP4 E00E5D 0 +OP4 E00E5E 0 +OP4 E00E5F 0 +OP4 E00E60 0 +OP4 E00E61 0 +OP4 E00E62 0 +OP4 E00E63 0 +OP4 E00E64 0 +OP4 E00E65 0 +OP4 E00E66 0 +OP4 E00E67 0 +OP4 E00E68 0 +OP4 E00E69 0 +OP4 E00E6A 0 +OP4 E00E6B 0 +OP4 E00E6C 0 +OP4 E00E6D 0 +OP4 E00E6E 0 +OP4 E00E6F 0 +OP4 E00E70 0 +OP4 E00E71 0 +OP4 E00E72 0 +OP4 E00E73 0 +OP4 E00E74 0 +OP4 E00E75 0 +OP4 E00E76 0 +OP4 E00E77 0 +OP4 E00E78 0 +OP4 E00E79 0 +OP4 E00E7A 0 +OP4 E00E7B 0 +OP4 E00E7C 0 +OP4 E00E7D 0 +OP4 E00E7E 0 +OP4 E00E7F 0 +OP4 E00E80 0 +OP4 E00E81 0 +OP4 E00E82 0 +OP4 E00E83 0 +OP4 E00E84 0 +OP4 E00E85 0 +OP4 E00E86 0 +OP4 E00E87 0 +OP4 E00E88 0 +OP4 E00E89 0 +OP4 E00E8A 0 +OP4 E00E8B 0 +OP4 E00E8C 0 +OP4 E00E8D 0 +OP4 E00E8E 0 +OP4 E00E8F 0 +OP4 E00E90 0 +OP4 E00E91 0 +OP4 E00E92 0 +OP4 E00E93 0 +OP4 E00E94 0 +OP4 E00E95 0 +OP4 E00E96 0 +OP4 E00E97 0 +OP4 E00E98 0 +OP4 E00E99 0 +OP4 E00E9A 0 +OP4 E00E9B 0 +OP4 E00E9C 0 +OP4 E00E9D 0 +OP4 E00E9E 0 +OP4 E00E9F 0 +OP4 E00EA0 0 +OP4 E00EA1 0 +OP4 E00EA2 0 +OP4 E00EA3 0 +OP4 E00EA4 0 +OP4 E00EA5 0 +OP4 E00EA6 0 +OP4 E00EA7 0 +OP4 E00EA8 0 +OP4 E00EA9 0 +OP4 E00EAA 0 +OP4 E00EAB 0 +OP4 E00EAC 0 +OP4 E00EAD 0 +OP4 E00EAE 0 +OP4 E00EAF 0 +OP4 E00EB0 0 +OP4 E00EB1 0 +OP4 E00EB2 0 +OP4 E00EB3 0 +OP4 E00EB4 0 +OP4 E00EB5 0 +OP4 E00EB6 0 +OP4 E00EB7 0 +OP4 E00EB8 0 +OP4 E00EB9 0 +OP4 E00EBA 0 +OP4 E00EBB 0 +OP4 E00EBC 0 +OP4 E00EBD 0 +OP4 E00EBE 0 +OP4 E00EBF 0 +OP4 E00EC0 0 +OP4 E00EC1 0 +OP4 E00EC2 0 +OP4 E00EC3 0 +OP4 E00EC4 0 +OP4 E00EC5 0 +OP4 E00EC6 0 +OP4 E00EC7 0 +OP4 E00EC8 0 +OP4 E00EC9 0 +OP4 E00ECA 0 +OP4 E00ECB 0 +OP4 E00ECC 0 +OP4 E00ECD 0 +OP4 E00ECE 0 +OP4 E00ECF 0 +OP4 E00ED0 0 +OP4 E00ED1 0 +OP4 E00ED2 0 +OP4 E00ED3 0 +OP4 E00ED4 0 +OP4 E00ED5 0 +OP4 E00ED6 0 +OP4 E00ED7 0 +OP4 E00ED8 0 +OP4 E00ED9 0 +OP4 E00EDA 0 +OP4 E00EDB 0 +OP4 E00EDC 0 +OP4 E00EDD 0 +OP4 E00EDE 0 +OP4 E00EDF 0 +OP4 E00EE0 0 +OP4 E00EE1 0 +OP4 E00EE2 0 +OP4 E00EE3 0 +OP4 E00EE4 0 +OP4 E00EE5 0 +OP4 E00EE6 0 +OP4 E00EE7 0 +OP4 E00EE8 0 +OP4 E00EE9 0 +OP4 E00EEA 0 +OP4 E00EEB 0 +OP4 E00EEC 0 +OP4 E00EED 0 +OP4 E00EEE 0 +OP4 E00EEF 0 +OP4 E00EF0 0 +OP4 E00EF1 0 +OP4 E00EF2 0 +OP4 E00EF3 0 +OP4 E00EF4 0 +OP4 E00EF5 0 +OP4 E00EF6 0 +OP4 E00EF7 0 +OP4 E00EF8 0 +OP4 E00EF9 0 +OP4 E00EFA 0 +OP4 E00EFB 0 +OP4 E00EFC 0 +OP4 E00EFD 0 +OP4 E00EFE 0 +OP4 E00EFF 0 +OP4 E00F00 0 +OP4 E00F01 0 +OP4 E00F02 0 +OP4 E00F03 0 +OP4 E00F04 0 +OP4 E00F05 0 +OP4 E00F06 0 +OP4 E00F07 0 +OP4 E00F08 0 +OP4 E00F09 0 +OP4 E00F0A 0 +OP4 E00F0B 0 +OP4 E00F0C 0 +OP4 E00F0D 0 +OP4 E00F0E 0 +OP4 E00F0F 0 +OP4 E00F10 0 +OP4 E00F11 0 +OP4 E00F12 0 +OP4 E00F13 0 +OP4 E00F14 0 +OP4 E00F15 0 +OP4 E00F16 0 +OP4 E00F17 0 +OP4 E00F18 0 +OP4 E00F19 0 +OP4 E00F1A 0 +OP4 E00F1B 0 +OP4 E00F1C 0 +OP4 E00F1D 0 +OP4 E00F1E 0 +OP4 E00F1F 0 +OP4 E00F20 0 +OP4 E00F21 0 +OP4 E00F22 0 +OP4 E00F23 0 +OP4 E00F24 0 +OP4 E00F25 0 +OP4 E00F26 0 +OP4 E00F27 0 +OP4 E00F28 0 +OP4 E00F29 0 +OP4 E00F2A 0 +OP4 E00F2B 0 +OP4 E00F2C 0 +OP4 E00F2D 0 +OP4 E00F2E 0 +OP4 E00F2F 0 +OP4 E00F30 0 +OP4 E00F31 0 +OP4 E00F32 0 +OP4 E00F33 0 +OP4 E00F34 0 +OP4 E00F35 0 +OP4 E00F36 0 +OP4 E00F37 0 +OP4 E00F38 0 +OP4 E00F39 0 +OP4 E00F3A 0 +OP4 E00F3B 0 +OP4 E00F3C 0 +OP4 E00F3D 0 +OP4 E00F3E 0 +OP4 E00F3F 0 +OP4 E00F40 0 +OP4 E00F41 0 +OP4 E00F42 0 +OP4 E00F43 0 +OP4 E00F44 0 +OP4 E00F45 0 +OP4 E00F46 0 +OP4 E00F47 0 +OP4 E00F48 0 +OP4 E00F49 0 +OP4 E00F4A 0 +OP4 E00F4B 0 +OP4 E00F4C 0 +OP4 E00F4D 0 +OP4 E00F4E 0 +OP4 E00F4F 0 +OP4 E00F50 0 +OP4 E00F51 0 +OP4 E00F52 0 +OP4 E00F53 0 +OP4 E00F54 0 +OP4 E00F55 0 +OP4 E00F56 0 +OP4 E00F57 0 +OP4 E00F58 0 +OP4 E00F59 0 +OP4 E00F5A 0 +OP4 E00F5B 0 +OP4 E00F5C 0 +OP4 E00F5D 0 +OP4 E00F5E 0 +OP4 E00F5F 0 +OP4 E00F60 0 +OP4 E00F61 0 +OP4 E00F62 0 +OP4 E00F63 0 +OP4 E00F64 0 +OP4 E00F65 0 +OP4 E00F66 0 +OP4 E00F67 0 +OP4 E00F68 0 +OP4 E00F69 0 +OP4 E00F6A 0 +OP4 E00F6B 0 +OP4 E00F6C 0 +OP4 E00F6D 0 +OP4 E00F6E 0 +OP4 E00F6F 0 +OP4 E00F70 0 +OP4 E00F71 0 +OP4 E00F72 0 +OP4 E00F73 0 +OP4 E00F74 0 +OP4 E00F75 0 +OP4 E00F76 0 +OP4 E00F77 0 +OP4 E00F78 0 +OP4 E00F79 0 +OP4 E00F7A 0 +OP4 E00F7B 0 +OP4 E00F7C 0 +OP4 E00F7D 0 +OP4 E00F7E 0 +OP4 E00F7F 0 +OP4 E00F80 0 +OP4 E00F81 0 +OP4 E00F82 0 +OP4 E00F83 0 +OP4 E00F84 0 +OP4 E00F85 0 +OP4 E00F86 0 +OP4 E00F87 0 +OP4 E00F88 0 +OP4 E00F89 0 +OP4 E00F8A 0 +OP4 E00F8B 0 +OP4 E00F8C 0 +OP4 E00F8D 0 +OP4 E00F8E 0 +OP4 E00F8F 0 +OP4 E00F90 0 +OP4 E00F91 0 +OP4 E00F92 0 +OP4 E00F93 0 +OP4 E00F94 0 +OP4 E00F95 0 +OP4 E00F96 0 +OP4 E00F97 0 +OP4 E00F98 0 +OP4 E00F99 0 +OP4 E00F9A 0 +OP4 E00F9B 0 +OP4 E00F9C 0 +OP4 E00F9D 0 +OP4 E00F9E 0 +OP4 E00F9F 0 +OP4 E00FA0 0 +OP4 E00FA1 0 +OP4 E00FA2 0 +OP4 E00FA3 0 +OP4 E00FA4 0 +OP4 E00FA5 0 +OP4 E00FA6 0 +OP4 E00FA7 0 +OP4 E00FA8 0 +OP4 E00FA9 0 +OP4 E00FAA 0 +OP4 E00FAB 0 +OP4 E00FAC 0 +OP4 E00FAD 0 +OP4 E00FAE 0 +OP4 E00FAF 0 +OP4 E00FB0 0 +OP4 E00FB1 0 +OP4 E00FB2 0 +OP4 E00FB3 0 +OP4 E00FB4 0 +OP4 E00FB5 0 +OP4 E00FB6 0 +OP4 E00FB7 0 +OP4 E00FB8 0 +OP4 E00FB9 0 +OP4 E00FBA 0 +OP4 E00FBB 0 +OP4 E00FBC 0 +OP4 E00FBD 0 +OP4 E00FBE 0 +OP4 E00FBF 0 +OP4 E00FC0 0 +OP4 E00FC1 0 +OP4 E00FC2 0 +OP4 E00FC3 0 +OP4 E00FC4 0 +OP4 E00FC5 0 +OP4 E00FC6 0 +OP4 E00FC7 0 +OP4 E00FC8 0 +OP4 E00FC9 0 +OP4 E00FCA 0 +OP4 E00FCB 0 +OP4 E00FCC 0 +OP4 E00FCD 0 +OP4 E00FCE 0 +OP4 E00FCF 0 +OP4 E00FD0 0 +OP4 E00FD1 0 +OP4 E00FD2 0 +OP4 E00FD3 0 +OP4 E00FD4 0 +OP4 E00FD5 0 +OP4 E00FD6 0 +OP4 E00FD7 0 +OP4 E00FD8 0 +OP4 E00FD9 0 +OP4 E00FDA 0 +OP4 E00FDB 0 +OP4 E00FDC 0 +OP4 E00FDD 0 +OP4 E00FDE 0 +OP4 E00FDF 0 +OP4 E00FE0 0 +OP4 E00FE1 0 +OP4 E00FE2 0 +OP4 E00FE3 0 +OP4 E00FE4 0 +OP4 E00FE5 0 +OP4 E00FE6 0 +OP4 E00FE7 0 +OP4 E00FE8 0 +OP4 E00FE9 0 +OP4 E00FEA 0 +OP4 E00FEB 0 +OP4 E00FEC 0 +OP4 E00FED 0 +OP4 E00FEE 0 +OP4 E00FEF 0 +OP4 E00FF0 0 +OP4 E00FF1 0 +OP4 E00FF2 0 +OP4 E00FF3 0 +OP4 E00FF4 0 +OP4 E00FF5 0 +OP4 E00FF6 0 +OP4 E00FF7 0 +OP4 E00FF8 0 +OP4 E00FF9 0 +OP4 E00FFA 0 +OP4 E00FFB 0 +OP4 E00FFC 0 +OP4 E00FFD 0 +OP4 E00FFE 0 +OP4 E00FFF 0 +OP4 E01000 0 +OP4 E01001 0 +OP4 E01002 0 +OP4 E01003 0 +OP4 E01004 0 +OP4 E01005 0 +OP4 E01006 0 +OP4 E01007 0 +OP4 E01008 0 +OP4 E01009 0 +OP4 E0100A 0 +OP4 E0100B 0 +OP4 E0100C 0 +OP4 E0100D 0 +OP4 E0100E 0 +OP4 E0100F 0 +OP4 E01010 0 +OP4 E01011 0 +OP4 E01012 0 +OP4 E01013 0 +OP4 E01014 0 +OP4 E01015 0 +OP4 E01016 0 +OP4 E01017 0 +OP4 E01018 0 +OP4 E01019 0 +OP4 E0101A 0 +OP4 E0101B 0 +OP4 E0101C 0 +OP4 E0101D 0 +OP4 E0101E 0 +OP4 E0101F 0 +OP4 E01020 0 +OP4 E01021 0 +OP4 E01022 0 +OP4 E01023 0 +OP4 E01024 0 +OP4 E01025 0 +OP4 E01026 0 +OP4 E01027 0 +OP4 E01028 0 +OP4 E01029 0 +OP4 E0102A 0 +OP4 E0102B 0 +OP4 E0102C 0 +OP4 E0102D 0 +OP4 E0102E 0 +OP4 E0102F 0 +OP4 E01030 0 +OP4 E01031 0 +OP4 E01032 0 +OP4 E01033 0 +OP4 E01034 0 +OP4 E01035 0 +OP4 E01036 0 +OP4 E01037 0 +OP4 E01038 0 +OP4 E01039 0 +OP4 E0103A 0 +OP4 E0103B 0 +OP4 E0103C 0 +OP4 E0103D 0 +OP4 E0103E 0 +OP4 E0103F 0 +OP4 E01040 0 +OP4 E01041 0 +OP4 E01042 0 +OP4 E01043 0 +OP4 E01044 0 +OP4 E01045 0 +OP4 E01046 0 +OP4 E01047 0 +OP4 E01048 0 +OP4 E01049 0 +OP4 E0104A 0 +OP4 E0104B 0 +OP4 E0104C 0 +OP4 E0104D 0 +OP4 E0104E 0 +OP4 E0104F 0 +OP4 E01050 0 +OP4 E01051 0 +OP4 E01052 0 +OP4 E01053 0 +OP4 E01054 0 +OP4 E01055 0 +OP4 E01056 0 +OP4 E01057 0 +OP4 E01058 0 +OP4 E01059 0 +OP4 E0105A 0 +OP4 E0105B 0 +OP4 E0105C 0 +OP4 E0105D 0 +OP4 E0105E 0 +OP4 E0105F 0 +OP4 E01060 0 +OP4 E01061 0 +OP4 E01062 0 +OP4 E01063 0 +OP4 E01064 0 +OP4 E01065 0 +OP4 E01066 0 +OP4 E01067 0 +OP4 E01068 0 +OP4 E01069 0 +OP4 E0106A 0 +OP4 E0106B 0 +OP4 E0106C 0 +OP4 E0106D 0 +OP4 E0106E 0 +OP4 E0106F 0 +OP4 E01070 0 +OP4 E01071 0 +OP4 E01072 0 +OP4 E01073 0 +OP4 E01074 0 +OP4 E01075 0 +OP4 E01076 0 +OP4 E01077 0 +OP4 E01078 0 +OP4 E01079 0 +OP4 E0107A 0 +OP4 E0107B 0 +OP4 E0107C 0 +OP4 E0107D 0 +OP4 E0107E 0 +OP4 E0107F 0 +OP4 E01080 0 +OP4 E01081 0 +OP4 E01082 0 +OP4 E01083 0 +OP4 E01084 0 +OP4 E01085 0 +OP4 E01086 0 +OP4 E01087 0 +OP4 E01088 0 +OP4 E01089 0 +OP4 E0108A 0 +OP4 E0108B 0 +OP4 E0108C 0 +OP4 E0108D 0 +OP4 E0108E 0 +OP4 E0108F 0 +OP4 E01090 0 +OP4 E01091 0 +OP4 E01092 0 +OP4 E01093 0 +OP4 E01094 0 +OP4 E01095 0 +OP4 E01096 0 +OP4 E01097 0 +OP4 E01098 0 +OP4 E01099 0 +OP4 E0109A 0 +OP4 E0109B 0 +OP4 E0109C 0 +OP4 E0109D 0 +OP4 E0109E 0 +OP4 E0109F 0 +OP4 E010A0 0 +OP4 E010A1 0 +OP4 E010A2 0 +OP4 E010A3 0 +OP4 E010A4 0 +OP4 E010A5 0 +OP4 E010A6 0 +OP4 E010A7 0 +OP4 E010A8 0 +OP4 E010A9 0 +OP4 E010AA 0 +OP4 E010AB 0 +OP4 E010AC 0 +OP4 E010AD 0 +OP4 E010AE 0 +OP4 E010AF 0 +OP4 E010B0 0 +OP4 E010B1 0 +OP4 E010B2 0 +OP4 E010B3 0 +OP4 E010B4 0 +OP4 E010B5 0 +OP4 E010B6 0 +OP4 E010B7 0 +OP4 E010B8 0 +OP4 E010B9 0 +OP4 E010BA 0 +OP4 E010BB 0 +OP4 E010BC 0 +OP4 E010BD 0 +OP4 E010BE 0 +OP4 E010BF 0 +OP4 E010C0 0 +OP4 E010C1 0 +OP4 E010C2 0 +OP4 E010C3 0 +OP4 E010C4 0 +OP4 E010C5 0 +OP4 E010C6 0 +OP4 E010C7 0 +OP4 E010C8 0 +OP4 E010C9 0 +OP4 E010CA 0 +OP4 E010CB 0 +OP4 E010CC 0 +OP4 E010CD 0 +OP4 E010CE 0 +OP4 E010CF 0 +OP4 E010D0 0 +OP4 E010D1 0 +OP4 E010D2 0 +OP4 E010D3 0 +OP4 E010D4 0 +OP4 E010D5 0 +OP4 E010D6 0 +OP4 E010D7 0 +OP4 E010D8 0 +OP4 E010D9 0 +OP4 E010DA 0 +OP4 E010DB 0 +OP4 E010DC 0 +OP4 E010DD 0 +OP4 E010DE 0 +OP4 E010DF 0 +OP4 E010E0 0 +OP4 E010E1 0 +OP4 E010E2 0 +OP4 E010E3 0 +OP4 E010E4 0 +OP4 E010E5 0 +OP4 E010E6 0 +OP4 E010E7 0 +OP4 E010E8 0 +OP4 E010E9 0 +OP4 E010EA 0 +OP4 E010EB 0 +OP4 E010EC 0 +OP4 E010ED 0 +OP4 E010EE 0 +OP4 E010EF 0 +OP4 E010F0 0 +OP4 E010F1 0 +OP4 E010F2 0 +OP4 E010F3 0 +OP4 E010F4 0 +OP4 E010F5 0 +OP4 E010F6 0 +OP4 E010F7 0 +OP4 E010F8 0 +OP4 E010F9 0 +OP4 E010FA 0 +OP4 E010FB 0 +OP4 E010FC 0 +OP4 E010FD 0 +OP4 E010FE 0 +OP4 E010FF 0 +OP4 E01100 0 +OP4 E01101 0 +OP4 E01102 0 +OP4 E01103 0 +OP4 E01104 0 +OP4 E01105 0 +OP4 E01106 0 +OP4 E01107 0 +OP4 E01108 0 +OP4 E01109 0 +OP4 E0110A 0 +OP4 E0110B 0 +OP4 E0110C 0 +OP4 E0110D 0 +OP4 E0110E 0 +OP4 E0110F 0 +OP4 E01110 0 +OP4 E01111 0 +OP4 E01112 0 +OP4 E01113 0 +OP4 E01114 0 +OP4 E01115 0 +OP4 E01116 0 +OP4 E01117 0 +OP4 E01118 0 +OP4 E01119 0 +OP4 E0111A 0 +OP4 E0111B 0 +OP4 E0111C 0 +OP4 E0111D 0 +OP4 E0111E 0 +OP4 E0111F 0 +OP4 E01120 0 +OP4 E01121 0 +OP4 E01122 0 +OP4 E01123 0 +OP4 E01124 0 +OP4 E01125 0 +OP4 E01126 0 +OP4 E01127 0 +OP4 E01128 0 +OP4 E01129 0 +OP4 E0112A 0 +OP4 E0112B 0 +OP4 E0112C 0 +OP4 E0112D 0 +OP4 E0112E 0 +OP4 E0112F 0 +OP4 E01130 0 +OP4 E01131 0 +OP4 E01132 0 +OP4 E01133 0 +OP4 E01134 0 +OP4 E01135 0 +OP4 E01136 0 +OP4 E01137 0 +OP4 E01138 0 +OP4 E01139 0 +OP4 E0113A 0 +OP4 E0113B 0 +OP4 E0113C 0 +OP4 E0113D 0 +OP4 E0113E 0 +OP4 E0113F 0 +OP4 E01140 0 +OP4 E01141 0 +OP4 E01142 0 +OP4 E01143 0 +OP4 E01144 0 +OP4 E01145 0 +OP4 E01146 0 +OP4 E01147 0 +OP4 E01148 0 +OP4 E01149 0 +OP4 E0114A 0 +OP4 E0114B 0 +OP4 E0114C 0 +OP4 E0114D 0 +OP4 E0114E 0 +OP4 E0114F 0 +OP4 E01150 0 +OP4 E01151 0 +OP4 E01152 0 +OP4 E01153 0 +OP4 E01154 0 +OP4 E01155 0 +OP4 E01156 0 +OP4 E01157 0 +OP4 E01158 0 +OP4 E01159 0 +OP4 E0115A 0 +OP4 E0115B 0 +OP4 E0115C 0 +OP4 E0115D 0 +OP4 E0115E 0 +OP4 E0115F 0 +OP4 E01160 0 +OP4 E01161 0 +OP4 E01162 0 +OP4 E01163 0 +OP4 E01164 0 +OP4 E01165 0 +OP4 E01166 0 +OP4 E01167 0 +OP4 E01168 0 +OP4 E01169 0 +OP4 E0116A 0 +OP4 E0116B 0 +OP4 E0116C 0 +OP4 E0116D 0 +OP4 E0116E 0 +OP4 E0116F 0 +OP4 E01170 0 +OP4 E01171 0 +OP4 E01172 0 +OP4 E01173 0 +OP4 E01174 0 +OP4 E01175 0 +OP4 E01176 0 +OP4 E01177 0 +OP4 E01178 0 +OP4 E01179 0 +OP4 E0117A 0 +OP4 E0117B 0 +OP4 E0117C 0 +OP4 E0117D 0 +OP4 E0117E 0 +OP4 E0117F 0 +OP4 E01180 0 +OP4 E01181 0 +OP4 E01182 0 +OP4 E01183 0 +OP4 E01184 0 +OP4 E01185 0 +OP4 E01186 0 +OP4 E01187 0 +OP4 E01188 0 +OP4 E01189 0 +OP4 E0118A 0 +OP4 E0118B 0 +OP4 E0118C 0 +OP4 E0118D 0 +OP4 E0118E 0 +OP4 E0118F 0 +OP4 E01190 0 +OP4 E01191 0 +OP4 E01192 0 +OP4 E01193 0 +OP4 E01194 0 +OP4 E01195 0 +OP4 E01196 0 +OP4 E01197 0 +OP4 E01198 0 +OP4 E01199 0 +OP4 E0119A 0 +OP4 E0119B 0 +OP4 E0119C 0 +OP4 E0119D 0 +OP4 E0119E 0 +OP4 E0119F 0 +OP4 E011A0 0 +OP4 E011A1 0 +OP4 E011A2 0 +OP4 E011A3 0 +OP4 E011A4 0 +OP4 E011A5 0 +OP4 E011A6 0 +OP4 E011A7 0 +OP4 E011A8 0 +OP4 E011A9 0 +OP4 E011AA 0 +OP4 E011AB 0 +OP4 E011AC 0 +OP4 E011AD 0 +OP4 E011AE 0 +OP4 E011AF 0 +OP4 E011B0 0 +OP4 E011B1 0 +OP4 E011B2 0 +OP4 E011B3 0 +OP4 E011B4 0 +OP4 E011B5 0 +OP4 E011B6 0 +OP4 E011B7 0 +OP4 E011B8 0 +OP4 E011B9 0 +OP4 E011BA 0 +OP4 E011BB 0 +OP4 E011BC 0 +OP4 E011BD 0 +OP4 E011BE 0 +OP4 E011BF 0 +OP4 E011C0 0 +OP4 E011C1 0 +OP4 E011C2 0 +OP4 E011C3 0 +OP4 E011C4 0 +OP4 E011C5 0 +OP4 E011C6 0 +OP4 E011C7 0 +OP4 E011C8 0 +OP4 E011C9 0 +OP4 E011CA 0 +OP4 E011CB 0 +OP4 E011CC 0 +OP4 E011CD 0 +OP4 E011CE 0 +OP4 E011CF 0 +OP4 E011D0 0 +OP4 E011D1 0 +OP4 E011D2 0 +OP4 E011D3 0 +OP4 E011D4 0 +OP4 E011D5 0 +OP4 E011D6 0 +OP4 E011D7 0 +OP4 E011D8 0 +OP4 E011D9 0 +OP4 E011DA 0 +OP4 E011DB 0 +OP4 E011DC 0 +OP4 E011DD 0 +OP4 E011DE 0 +OP4 E011DF 0 +OP4 E011E0 0 +OP4 E011E1 0 +OP4 E011E2 0 +OP4 E011E3 0 +OP4 E011E4 0 +OP4 E011E5 0 +OP4 E011E6 0 +OP4 E011E7 0 +OP4 E011E8 0 +OP4 E011E9 0 +OP4 E011EA 0 +OP4 E011EB 0 +OP4 E011EC 0 +OP4 E011ED 0 +OP4 E011EE 0 +OP4 E011EF 0 +OP4 E011F0 0 +OP4 E011F1 0 +OP4 E011F2 0 +OP4 E011F3 0 +OP4 E011F4 0 +OP4 E011F5 0 +OP4 E011F6 0 +OP4 E011F7 0 +OP4 E011F8 0 +OP4 E011F9 0 +OP4 E011FA 0 +OP4 E011FB 0 +OP4 E011FC 0 +OP4 E011FD 0 +OP4 E011FE 0 +OP4 E011FF 0 +OP4 E01200 0 +OP4 E01201 0 +OP4 E01202 0 +OP4 E01203 0 +OP4 E01204 0 +OP4 E01205 0 +OP4 E01206 0 +OP4 E01207 0 +OP4 E01208 0 +OP4 E01209 0 +OP4 E0120A 0 +OP4 E0120B 0 +OP4 E0120C 0 +OP4 E0120D 0 +OP4 E0120E 0 +OP4 E0120F 0 +OP4 E01210 0 +OP4 E01211 0 +OP4 E01212 0 +OP4 E01213 0 +OP4 E01214 0 +OP4 E01215 0 +OP4 E01216 0 +OP4 E01217 0 +OP4 E01218 0 +OP4 E01219 0 +OP4 E0121A 0 +OP4 E0121B 0 +OP4 E0121C 0 +OP4 E0121D 0 +OP4 E0121E 0 +OP4 E0121F 0 +OP4 E01220 0 +OP4 E01221 0 +OP4 E01222 0 +OP4 E01223 0 +OP4 E01224 0 +OP4 E01225 0 +OP4 E01226 0 +OP4 E01227 0 +OP4 E01228 0 +OP4 E01229 0 +OP4 E0122A 0 +OP4 E0122B 0 +OP4 E0122C 0 +OP4 E0122D 0 +OP4 E0122E 0 +OP4 E0122F 0 +OP4 E01230 0 +OP4 E01231 0 +OP4 E01232 0 +OP4 E01233 0 +OP4 E01234 0 +OP4 E01235 0 +OP4 E01236 0 +OP4 E01237 0 +OP4 E01238 0 +OP4 E01239 0 +OP4 E0123A 0 +OP4 E0123B 0 +OP4 E0123C 0 +OP4 E0123D 0 +OP4 E0123E 0 +OP4 E0123F 0 +OP4 E01240 0 +OP4 E01241 0 +OP4 E01242 0 +OP4 E01243 0 +OP4 E01244 0 +OP4 E01245 0 +OP4 E01246 0 +OP4 E01247 0 +OP4 E01248 0 +OP4 E01249 0 +OP4 E0124A 0 +OP4 E0124B 0 +OP4 E0124C 0 +OP4 E0124D 0 +OP4 E0124E 0 +OP4 E0124F 0 +OP4 E01250 0 +OP4 E01251 0 +OP4 E01252 0 +OP4 E01253 0 +OP4 E01254 0 +OP4 E01255 0 +OP4 E01256 0 +OP4 E01257 0 +OP4 E01258 0 +OP4 E01259 0 +OP4 E0125A 0 +OP4 E0125B 0 +OP4 E0125C 0 +OP4 E0125D 0 +OP4 E0125E 0 +OP4 E0125F 0 +OP4 E01260 0 +OP4 E01261 0 +OP4 E01262 0 +OP4 E01263 0 +OP4 E01264 0 +OP4 E01265 0 +OP4 E01266 0 +OP4 E01267 0 +OP4 E01268 0 +OP4 E01269 0 +OP4 E0126A 0 +OP4 E0126B 0 +OP4 E0126C 0 +OP4 E0126D 0 +OP4 E0126E 0 +OP4 E0126F 0 +OP4 E01270 0 +OP4 E01271 0 +OP4 E01272 0 +OP4 E01273 0 +OP4 E01274 0 +OP4 E01275 0 +OP4 E01276 0 +OP4 E01277 0 +OP4 E01278 0 +OP4 E01279 0 +OP4 E0127A 0 +OP4 E0127B 0 +OP4 E0127C 0 +OP4 E0127D 0 +OP4 E0127E 0 +OP4 E0127F 0 +OP4 E01280 0 +OP4 E01281 0 +OP4 E01282 0 +OP4 E01283 0 +OP4 E01284 0 +OP4 E01285 0 +OP4 E01286 0 +OP4 E01287 0 +OP4 E01288 0 +OP4 E01289 0 +OP4 E0128A 0 +OP4 E0128B 0 +OP4 E0128C 0 +OP4 E0128D 0 +OP4 E0128E 0 +OP4 E0128F 0 +OP4 E01290 0 +OP4 E01291 0 +OP4 E01292 0 +OP4 E01293 0 +OP4 E01294 0 +OP4 E01295 0 +OP4 E01296 0 +OP4 E01297 0 +OP4 E01298 0 +OP4 E01299 0 +OP4 E0129A 0 +OP4 E0129B 0 +OP4 E0129C 0 +OP4 E0129D 0 +OP4 E0129E 0 +OP4 E0129F 0 +OP4 E012A0 0 +OP4 E012A1 0 +OP4 E012A2 0 +OP4 E012A3 0 +OP4 E012A4 0 +OP4 E012A5 0 +OP4 E012A6 0 +OP4 E012A7 0 +OP4 E012A8 0 +OP4 E012A9 0 +OP4 E012AA 0 +OP4 E012AB 0 +OP4 E012AC 0 +OP4 E012AD 0 +OP4 E012AE 0 +OP4 E012AF 0 +OP4 E012B0 0 +OP4 E012B1 0 +OP4 E012B2 0 +OP4 E012B3 0 +OP4 E012B4 0 +OP4 E012B5 0 +OP4 E012B6 0 +OP4 E012B7 0 +OP4 E012B8 0 +OP4 E012B9 0 +OP4 E012BA 0 +OP4 E012BB 0 +OP4 E012BC 0 +OP4 E012BD 0 +OP4 E012BE 0 +OP4 E012BF 0 +OP4 E012C0 0 +OP4 E012C1 0 +OP4 E012C2 0 +OP4 E012C3 0 +OP4 E012C4 0 +OP4 E012C5 0 +OP4 E012C6 0 +OP4 E012C7 0 +OP4 E012C8 0 +OP4 E012C9 0 +OP4 E012CA 0 +OP4 E012CB 0 +OP4 E012CC 0 +OP4 E012CD 0 +OP4 E012CE 0 +OP4 E012CF 0 +OP4 E012D0 0 +OP4 E012D1 0 +OP4 E012D2 0 +OP4 E012D3 0 +OP4 E012D4 0 +OP4 E012D5 0 +OP4 E012D6 0 +OP4 E012D7 0 +OP4 E012D8 0 +OP4 E012D9 0 +OP4 E012DA 0 +OP4 E012DB 0 +OP4 E012DC 0 +OP4 E012DD 0 +OP4 E012DE 0 +OP4 E012DF 0 +OP4 E012E0 0 +OP4 E012E1 0 +OP4 E012E2 0 +OP4 E012E3 0 +OP4 E012E4 0 +OP4 E012E5 0 +OP4 E012E6 0 +OP4 E012E7 0 +OP4 E012E8 0 +OP4 E012E9 0 +OP4 E012EA 0 +OP4 E012EB 0 +OP4 E012EC 0 +OP4 E012ED 0 +OP4 E012EE 0 +OP4 E012EF 0 +OP4 E012F0 0 +OP4 E012F1 0 +OP4 E012F2 0 +OP4 E012F3 0 +OP4 E012F4 0 +OP4 E012F5 0 +OP4 E012F6 0 +OP4 E012F7 0 +OP4 E012F8 0 +OP4 E012F9 0 +OP4 E012FA 0 +OP4 E012FB 0 +OP4 E012FC 0 +OP4 E012FD 0 +OP4 E012FE 0 +OP4 E012FF 0 +OP4 E01300 0 +OP4 E01301 0 +OP4 E01302 0 +OP4 E01303 0 +OP4 E01304 0 +OP4 E01305 0 +OP4 E01306 0 +OP4 E01307 0 +OP4 E01308 0 +OP4 E01309 0 +OP4 E0130A 0 +OP4 E0130B 0 +OP4 E0130C 0 +OP4 E0130D 0 +OP4 E0130E 0 +OP4 E0130F 0 +OP4 E01310 0 +OP4 E01311 0 +OP4 E01312 0 +OP4 E01313 0 +OP4 E01314 0 +OP4 E01315 0 +OP4 E01316 0 +OP4 E01317 0 +OP4 E01318 0 +OP4 E01319 0 +OP4 E0131A 0 +OP4 E0131B 0 +OP4 E0131C 0 +OP4 E0131D 0 +OP4 E0131E 0 +OP4 E0131F 0 +OP4 E01320 0 +OP4 E01321 0 +OP4 E01322 0 +OP4 E01323 0 +OP4 E01324 0 +OP4 E01325 0 +OP4 E01326 0 +OP4 E01327 0 +OP4 E01328 0 +OP4 E01329 0 +OP4 E0132A 0 +OP4 E0132B 0 +OP4 E0132C 0 +OP4 E0132D 0 +OP4 E0132E 0 +OP4 E0132F 0 +OP4 E01330 0 +OP4 E01331 0 +OP4 E01332 0 +OP4 E01333 0 +OP4 E01334 0 +OP4 E01335 0 +OP4 E01336 0 +OP4 E01337 0 +OP4 E01338 0 +OP4 E01339 0 +OP4 E0133A 0 +OP4 E0133B 0 +OP4 E0133C 0 +OP4 E0133D 0 +OP4 E0133E 0 +OP4 E0133F 0 +OP4 E01340 0 +OP4 E01341 0 +OP4 E01342 0 +OP4 E01343 0 +OP4 E01344 0 +OP4 E01345 0 +OP4 E01346 0 +OP4 E01347 0 +OP4 E01348 0 +OP4 E01349 0 +OP4 E0134A 0 +OP4 E0134B 0 +OP4 E0134C 0 +OP4 E0134D 0 +OP4 E0134E 0 +OP4 E0134F 0 +OP4 E01350 0 +OP4 E01351 0 +OP4 E01352 0 +OP4 E01353 0 +OP4 E01354 0 +OP4 E01355 0 +OP4 E01356 0 +OP4 E01357 0 +OP4 E01358 0 +OP4 E01359 0 +OP4 E0135A 0 +OP4 E0135B 0 +OP4 E0135C 0 +OP4 E0135D 0 +OP4 E0135E 0 +OP4 E0135F 0 +OP4 E01360 0 +OP4 E01361 0 +OP4 E01362 0 +OP4 E01363 0 +OP4 E01364 0 +OP4 E01365 0 +OP4 E01366 0 +OP4 E01367 0 +OP4 E01368 0 +OP4 E01369 0 +OP4 E0136A 0 +OP4 E0136B 0 +OP4 E0136C 0 +OP4 E0136D 0 +OP4 E0136E 0 +OP4 E0136F 0 +OP4 E01370 0 +OP4 E01371 0 +OP4 E01372 0 +OP4 E01373 0 +OP4 E01374 0 +OP4 E01375 0 +OP4 E01376 0 +OP4 E01377 0 +OP4 E01378 0 +OP4 E01379 0 +OP4 E0137A 0 +OP4 E0137B 0 +OP4 E0137C 0 +OP4 E0137D 0 +OP4 E0137E 0 +OP4 E0137F 0 +OP4 E01380 0 +OP4 E01381 0 +OP4 E01382 0 +OP4 E01383 0 +OP4 E01384 0 +OP4 E01385 0 +OP4 E01386 0 +OP4 E01387 0 +OP4 E01388 0 +OP4 E01389 0 +OP4 E0138A 0 +OP4 E0138B 0 +OP4 E0138C 0 +OP4 E0138D 0 +OP4 E0138E 0 +OP4 E0138F 0 +OP4 E01390 0 +OP4 E01391 0 +OP4 E01392 0 +OP4 E01393 0 +OP4 E01394 0 +OP4 E01395 0 +OP4 E01396 0 +OP4 E01397 0 +OP4 E01398 0 +OP4 E01399 0 +OP4 E0139A 0 +OP4 E0139B 0 +OP4 E0139C 0 +OP4 E0139D 0 +OP4 E0139E 0 +OP4 E0139F 0 +OP4 E013A0 0 +OP4 E013A1 0 +OP4 E013A2 0 +OP4 E013A3 0 +OP4 E013A4 0 +OP4 E013A5 0 +OP4 E013A6 0 +OP4 E013A7 0 +OP4 E013A8 0 +OP4 E013A9 0 +OP4 E013AA 0 +OP4 E013AB 0 +OP4 E013AC 0 +OP4 E013AD 0 +OP4 E013AE 0 +OP4 E013AF 0 +OP4 E013B0 0 +OP4 E013B1 0 +OP4 E013B2 0 +OP4 E013B3 0 +OP4 E013B4 0 +OP4 E013B5 0 +OP4 E013B6 0 +OP4 E013B7 0 +OP4 E013B8 0 +OP4 E013B9 0 +OP4 E013BA 0 +OP4 E013BB 0 +OP4 E013BC 0 +OP4 E013BD 0 +OP4 E013BE 0 +OP4 E013BF 0 +OP4 E013C0 0 +OP4 E013C1 0 +OP4 E013C2 0 +OP4 E013C3 0 +OP4 E013C4 0 +OP4 E013C5 0 +OP4 E013C6 0 +OP4 E013C7 0 +OP4 E013C8 0 +OP4 E013C9 0 +OP4 E013CA 0 +OP4 E013CB 0 +OP4 E013CC 0 +OP4 E013CD 0 +OP4 E013CE 0 +OP4 E013CF 0 +OP4 E013D0 0 +OP4 E013D1 0 +OP4 E013D2 0 +OP4 E013D3 0 +OP4 E013D4 0 +OP4 E013D5 0 +OP4 E013D6 0 +OP4 E013D7 0 +OP4 E013D8 0 +OP4 E013D9 0 +OP4 E013DA 0 +OP4 E013DB 0 +OP4 E013DC 0 +OP4 E013DD 0 +OP4 E013DE 0 +OP4 E013DF 0 +OP4 E013E0 0 +OP4 E013E1 0 +OP4 E013E2 0 +OP4 E013E3 0 +OP4 E013E4 0 +OP4 E013E5 0 +OP4 E013E6 0 +OP4 E013E7 0 +OP4 E013E8 0 +OP4 E013E9 0 +OP4 E013EA 0 +OP4 E013EB 0 +OP4 E013EC 0 +OP4 E013ED 0 +OP4 E013EE 0 +OP4 E013EF 0 +OP4 E013F0 0 +OP4 E013F1 0 +OP4 E013F2 0 +OP4 E013F3 0 +OP4 E013F4 0 +OP4 E013F5 0 +OP4 E013F6 0 +OP4 E013F7 0 +OP4 E013F8 0 +OP4 E013F9 0 +OP4 E013FA 0 +OP4 E013FB 0 +OP4 E013FC 0 +OP4 E013FD 0 +OP4 E013FE 0 +OP4 E013FF 0 +OP4 E01400 0 +OP4 E01401 0 +OP4 E01402 0 +OP4 E01403 0 +OP4 E01404 0 +OP4 E01405 0 +OP4 E01406 0 +OP4 E01407 0 +OP4 E01408 0 +OP4 E01409 0 +OP4 E0140A 0 +OP4 E0140B 0 +OP4 E0140C 0 +OP4 E0140D 0 +OP4 E0140E 0 +OP4 E0140F 0 +OP4 E01410 0 +OP4 E01411 0 +OP4 E01412 0 +OP4 E01413 0 +OP4 E01414 0 +OP4 E01415 0 +OP4 E01416 0 +OP4 E01417 0 +OP4 E01418 0 +OP4 E01419 0 +OP4 E0141A 0 +OP4 E0141B 0 +OP4 E0141C 0 +OP4 E0141D 0 +OP4 E0141E 0 +OP4 E0141F 0 +OP4 E01420 0 +OP4 E01421 0 +OP4 E01422 0 +OP4 E01423 0 +OP4 E01424 0 +OP4 E01425 0 +OP4 E01426 0 +OP4 E01427 0 +OP4 E01428 0 +OP4 E01429 0 +OP4 E0142A 0 +OP4 E0142B 0 +OP4 E0142C 0 +OP4 E0142D 0 +OP4 E0142E 0 +OP4 E0142F 0 +OP4 E01430 0 +OP4 E01431 0 +OP4 E01432 0 +OP4 E01433 0 +OP4 E01434 0 +OP4 E01435 0 +OP4 E01436 0 +OP4 E01437 0 +OP4 E01438 0 +OP4 E01439 0 +OP4 E0143A 0 +OP4 E0143B 0 +OP4 E0143C 0 +OP4 E0143D 0 +OP4 E0143E 0 +OP4 E0143F 0 +OP4 E01440 0 +OP4 E01441 0 +OP4 E01442 0 +OP4 E01443 0 +OP4 E01444 0 +OP4 E01445 0 +OP4 E01446 0 +OP4 E01447 0 +OP4 E01448 0 +OP4 E01449 0 +OP4 E0144A 0 +OP4 E0144B 0 +OP4 E0144C 0 +OP4 E0144D 0 +OP4 E0144E 0 +OP4 E0144F 0 +OP4 E01450 0 +OP4 E01451 0 +OP4 E01452 0 +OP4 E01453 0 +OP4 E01454 0 +OP4 E01455 0 +OP4 E01456 0 +OP4 E01457 0 +OP4 E01458 0 +OP4 E01459 0 +OP4 E0145A 0 +OP4 E0145B 0 +OP4 E0145C 0 +OP4 E0145D 0 +OP4 E0145E 0 +OP4 E0145F 0 +OP4 E01460 0 +OP4 E01461 0 +OP4 E01462 0 +OP4 E01463 0 +OP4 E01464 0 +OP4 E01465 0 +OP4 E01466 0 +OP4 E01467 0 +OP4 E01468 0 +OP4 E01469 0 +OP4 E0146A 0 +OP4 E0146B 0 +OP4 E0146C 0 +OP4 E0146D 0 +OP4 E0146E 0 +OP4 E0146F 0 +OP4 E01470 0 +OP4 E01471 0 +OP4 E01472 0 +OP4 E01473 0 +OP4 E01474 0 +OP4 E01475 0 +OP4 E01476 0 +OP4 E01477 0 +OP4 E01478 0 +OP4 E01479 0 +OP4 E0147A 0 +OP4 E0147B 0 +OP4 E0147C 0 +OP4 E0147D 0 +OP4 E0147E 0 +OP4 E0147F 0 +OP4 E01480 0 +OP4 E01481 0 +OP4 E01482 0 +OP4 E01483 0 +OP4 E01484 0 +OP4 E01485 0 +OP4 E01486 0 +OP4 E01487 0 +OP4 E01488 0 +OP4 E01489 0 +OP4 E0148A 0 +OP4 E0148B 0 +OP4 E0148C 0 +OP4 E0148D 0 +OP4 E0148E 0 +OP4 E0148F 0 +OP4 E01490 0 +OP4 E01491 0 +OP4 E01492 0 +OP4 E01493 0 +OP4 E01494 0 +OP4 E01495 0 +OP4 E01496 0 +OP4 E01497 0 +OP4 E01498 0 +OP4 E01499 0 +OP4 E0149A 0 +OP4 E0149B 0 +OP4 E0149C 0 +OP4 E0149D 0 +OP4 E0149E 0 +OP4 E0149F 0 +OP4 E014A0 0 +OP4 E014A1 0 +OP4 E014A2 0 +OP4 E014A3 0 +OP4 E014A4 0 +OP4 E014A5 0 +OP4 E014A6 0 +OP4 E014A7 0 +OP4 E014A8 0 +OP4 E014A9 0 +OP4 E014AA 0 +OP4 E014AB 0 +OP4 E014AC 0 +OP4 E014AD 0 +OP4 E014AE 0 +OP4 E014AF 0 +OP4 E014B0 0 +OP4 E014B1 0 +OP4 E014B2 0 +OP4 E014B3 0 +OP4 E014B4 0 +OP4 E014B5 0 +OP4 E014B6 0 +OP4 E014B7 0 +OP4 E014B8 0 +OP4 E014B9 0 +OP4 E014BA 0 +OP4 E014BB 0 +OP4 E014BC 0 +OP4 E014BD 0 +OP4 E014BE 0 +OP4 E014BF 0 +OP4 E014C0 0 +OP4 E014C1 0 +OP4 E014C2 0 +OP4 E014C3 0 +OP4 E014C4 0 +OP4 E014C5 0 +OP4 E014C6 0 +OP4 E014C7 0 +OP4 E014C8 0 +OP4 E014C9 0 +OP4 E014CA 0 +OP4 E014CB 0 +OP4 E014CC 0 +OP4 E014CD 0 +OP4 E014CE 0 +OP4 E014CF 0 +OP4 E014D0 0 +OP4 E014D1 0 +OP4 E014D2 0 +OP4 E014D3 0 +OP4 E014D4 0 +OP4 E014D5 0 +OP4 E014D6 0 +OP4 E014D7 0 +OP4 E014D8 0 +OP4 E014D9 0 +OP4 E014DA 0 +OP4 E014DB 0 +OP4 E014DC 0 +OP4 E014DD 0 +OP4 E014DE 0 +OP4 E014DF 0 +OP4 E014E0 0 +OP4 E014E1 0 +OP4 E014E2 0 +OP4 E014E3 0 +OP4 E014E4 0 +OP4 E014E5 0 +OP4 E014E6 0 +OP4 E014E7 0 +OP4 E014E8 0 +OP4 E014E9 0 +OP4 E014EA 0 +OP4 E014EB 0 +OP4 E014EC 0 +OP4 E014ED 0 +OP4 E014EE 0 +OP4 E014EF 0 +OP4 E014F0 0 +OP4 E014F1 0 +OP4 E014F2 0 +OP4 E014F3 0 +OP4 E014F4 0 +OP4 E014F5 0 +OP4 E014F6 0 +OP4 E014F7 0 +OP4 E014F8 0 +OP4 E014F9 0 +OP4 E014FA 0 +OP4 E014FB 0 +OP4 E014FC 0 +OP4 E014FD 0 +OP4 E014FE 0 +OP4 E014FF 0 +OP4 E01500 0 +OP4 E01501 0 +OP4 E01502 0 +OP4 E01503 0 +OP4 E01504 0 +OP4 E01505 0 +OP4 E01506 0 +OP4 E01507 0 +OP4 E01508 0 +OP4 E01509 0 +OP4 E0150A 0 +OP4 E0150B 0 +OP4 E0150C 0 +OP4 E0150D 0 +OP4 E0150E 0 +OP4 E0150F 0 +OP4 E01510 0 +OP4 E01511 0 +OP4 E01512 0 +OP4 E01513 0 +OP4 E01514 0 +OP4 E01515 0 +OP4 E01516 0 +OP4 E01517 0 +OP4 E01518 0 +OP4 E01519 0 +OP4 E0151A 0 +OP4 E0151B 0 +OP4 E0151C 0 +OP4 E0151D 0 +OP4 E0151E 0 +OP4 E0151F 0 +OP4 E01520 0 +OP4 E01521 0 +OP4 E01522 0 +OP4 E01523 0 +OP4 E01524 0 +OP4 E01525 0 +OP4 E01526 0 +OP4 E01527 0 +OP4 E01528 0 +OP4 E01529 0 +OP4 E0152A 0 +OP4 E0152B 0 +OP4 E0152C 0 +OP4 E0152D 0 +OP4 E0152E 0 +OP4 E0152F 0 +OP4 E01530 0 +OP4 E01531 0 +OP4 E01532 0 +OP4 E01533 0 +OP4 E01534 0 +OP4 E01535 0 +OP4 E01536 0 +OP4 E01537 0 +OP4 E01538 0 +OP4 E01539 0 +OP4 E0153A 0 +OP4 E0153B 0 +OP4 E0153C 0 +OP4 E0153D 0 +OP4 E0153E 0 +OP4 E0153F 0 +OP4 E01540 0 +OP4 E01541 0 +OP4 E01542 0 +OP4 E01543 0 +OP4 E01544 0 +OP4 E01545 0 +OP4 E01546 0 +OP4 E01547 0 +OP4 E01548 0 +OP4 E01549 0 +OP4 E0154A 0 +OP4 E0154B 0 +OP4 E0154C 0 +OP4 E0154D 0 +OP4 E0154E 0 +OP4 E0154F 0 +OP4 E01550 0 +OP4 E01551 0 +OP4 E01552 0 +OP4 E01553 0 +OP4 E01554 0 +OP4 E01555 0 +OP4 E01556 0 +OP4 E01557 0 +OP4 E01558 0 +OP4 E01559 0 +OP4 E0155A 0 +OP4 E0155B 0 +OP4 E0155C 0 +OP4 E0155D 0 +OP4 E0155E 0 +OP4 E0155F 0 +OP4 E01560 0 +OP4 E01561 0 +OP4 E01562 0 +OP4 E01563 0 +OP4 E01564 0 +OP4 E01565 0 +OP4 E01566 0 +OP4 E01567 0 +OP4 E01568 0 +OP4 E01569 0 +OP4 E0156A 0 +OP4 E0156B 0 +OP4 E0156C 0 +OP4 E0156D 0 +OP4 E0156E 0 +OP4 E0156F 0 +OP4 E01570 0 +OP4 E01571 0 +OP4 E01572 0 +OP4 E01573 0 +OP4 E01574 0 +OP4 E01575 0 +OP4 E01576 0 +OP4 E01577 0 +OP4 E01578 0 +OP4 E01579 0 +OP4 E0157A 0 +OP4 E0157B 0 +OP4 E0157C 0 +OP4 E0157D 0 +OP4 E0157E 0 +OP4 E0157F 0 +OP4 E01580 0 +OP4 E01581 0 +OP4 E01582 0 +OP4 E01583 0 +OP4 E01584 0 +OP4 E01585 0 +OP4 E01586 0 +OP4 E01587 0 +OP4 E01588 0 +OP4 E01589 0 +OP4 E0158A 0 +OP4 E0158B 0 +OP4 E0158C 0 +OP4 E0158D 0 +OP4 E0158E 0 +OP4 E0158F 0 +OP4 E01590 0 +OP4 E01591 0 +OP4 E01592 0 +OP4 E01593 0 +OP4 E01594 0 +OP4 E01595 0 +OP4 E01596 0 +OP4 E01597 0 +OP4 E01598 0 +OP4 E01599 0 +OP4 E0159A 0 +OP4 E0159B 0 +OP4 E0159C 0 +OP4 E0159D 0 +OP4 E0159E 0 +OP4 E0159F 0 +OP4 E015A0 0 +OP4 E015A1 0 +OP4 E015A2 0 +OP4 E015A3 0 +OP4 E015A4 0 +OP4 E015A5 0 +OP4 E015A6 0 +OP4 E015A7 0 +OP4 E015A8 0 +OP4 E015A9 0 +OP4 E015AA 0 +OP4 E015AB 0 +OP4 E015AC 0 +OP4 E015AD 0 +OP4 E015AE 0 +OP4 E015AF 0 +OP4 E015B0 0 +OP4 E015B1 0 +OP4 E015B2 0 +OP4 E015B3 0 +OP4 E015B4 0 +OP4 E015B5 0 +OP4 E015B6 0 +OP4 E015B7 0 +OP4 E015B8 0 +OP4 E015B9 0 +OP4 E015BA 0 +OP4 E015BB 0 +OP4 E015BC 0 +OP4 E015BD 0 +OP4 E015BE 0 +OP4 E015BF 0 +OP4 E015C0 0 +OP4 E015C1 0 +OP4 E015C2 0 +OP4 E015C3 0 +OP4 E015C4 0 +OP4 E015C5 0 +OP4 E015C6 0 +OP4 E015C7 0 +OP4 E015C8 0 +OP4 E015C9 0 +OP4 E015CA 0 +OP4 E015CB 0 +OP4 E015CC 0 +OP4 E015CD 0 +OP4 E015CE 0 +OP4 E015CF 0 +OP4 E015D0 0 +OP4 E015D1 0 +OP4 E015D2 0 +OP4 E015D3 0 +OP4 E015D4 0 +OP4 E015D5 0 +OP4 E015D6 0 +OP4 E015D7 0 +OP4 E015D8 0 +OP4 E015D9 0 +OP4 E015DA 0 +OP4 E015DB 0 +OP4 E015DC 0 +OP4 E015DD 0 +OP4 E015DE 0 +OP4 E015DF 0 +OP4 E015E0 0 +OP4 E015E1 0 +OP4 E015E2 0 +OP4 E015E3 0 +OP4 E015E4 0 +OP4 E015E5 0 +OP4 E015E6 0 +OP4 E015E7 0 +OP4 E015E8 0 +OP4 E015E9 0 +OP4 E015EA 0 +OP4 E015EB 0 +OP4 E015EC 0 +OP4 E015ED 0 +OP4 E015EE 0 +OP4 E015EF 0 +OP4 E015F0 0 +OP4 E015F1 0 +OP4 E015F2 0 +OP4 E015F3 0 +OP4 E015F4 0 +OP4 E015F5 0 +OP4 E015F6 0 +OP4 E015F7 0 +OP4 E015F8 0 +OP4 E015F9 0 +OP4 E015FA 0 +OP4 E015FB 0 +OP4 E015FC 0 +OP4 E015FD 0 +OP4 E015FE 0 +OP4 E015FF 0 +OP4 E01600 0 +OP4 E01601 0 +OP4 E01602 0 +OP4 E01603 0 +OP4 E01604 0 +OP4 E01605 0 +OP4 E01606 0 +OP4 E01607 0 +OP4 E01608 0 +OP4 E01609 0 +OP4 E0160A 0 +OP4 E0160B 0 +OP4 E0160C 0 +OP4 E0160D 0 +OP4 E0160E 0 +OP4 E0160F 0 +OP4 E01610 0 +OP4 E01611 0 +OP4 E01612 0 +OP4 E01613 0 +OP4 E01614 0 +OP4 E01615 0 +OP4 E01616 0 +OP4 E01617 0 +OP4 E01618 0 +OP4 E01619 0 +OP4 E0161A 0 +OP4 E0161B 0 +OP4 E0161C 0 +OP4 E0161D 0 +OP4 E0161E 0 +OP4 E0161F 0 +OP4 E01620 0 +OP4 E01621 0 +OP4 E01622 0 +OP4 E01623 0 +OP4 E01624 0 +OP4 E01625 0 +OP4 E01626 0 +OP4 E01627 0 +OP4 E01628 0 +OP4 E01629 0 +OP4 E0162A 0 +OP4 E0162B 0 +OP4 E0162C 0 +OP4 E0162D 0 +OP4 E0162E 0 +OP4 E0162F 0 +OP4 E01630 0 +OP4 E01631 0 +OP4 E01632 0 +OP4 E01633 0 +OP4 E01634 0 +OP4 E01635 0 +OP4 E01636 0 +OP4 E01637 0 +OP4 E01638 0 +OP4 E01639 0 +OP4 E0163A 0 +OP4 E0163B 0 +OP4 E0163C 0 +OP4 E0163D 0 +OP4 E0163E 0 +OP4 E0163F 0 +OP4 E01640 0 +OP4 E01641 0 +OP4 E01642 0 +OP4 E01643 0 +OP4 E01644 0 +OP4 E01645 0 +OP4 E01646 0 +OP4 E01647 0 +OP4 E01648 0 +OP4 E01649 0 +OP4 E0164A 0 +OP4 E0164B 0 +OP4 E0164C 0 +OP4 E0164D 0 +OP4 E0164E 0 +OP4 E0164F 0 +OP4 E01650 0 +OP4 E01651 0 +OP4 E01652 0 +OP4 E01653 0 +OP4 E01654 0 +OP4 E01655 0 +OP4 E01656 0 +OP4 E01657 0 +OP4 E01658 0 +OP4 E01659 0 +OP4 E0165A 0 +OP4 E0165B 0 +OP4 E0165C 0 +OP4 E0165D 0 +OP4 E0165E 0 +OP4 E0165F 0 +OP4 E01660 0 +OP4 E01661 0 +OP4 E01662 0 +OP4 E01663 0 +OP4 E01664 0 +OP4 E01665 0 +OP4 E01666 0 +OP4 E01667 0 +OP4 E01668 0 +OP4 E01669 0 +OP4 E0166A 0 +OP4 E0166B 0 +OP4 E0166C 0 +OP4 E0166D 0 +OP4 E0166E 0 +OP4 E0166F 0 +OP4 E01670 0 +OP4 E01671 0 +OP4 E01672 0 +OP4 E01673 0 +OP4 E01674 0 +OP4 E01675 0 +OP4 E01676 0 +OP4 E01677 0 +OP4 E01678 0 +OP4 E01679 0 +OP4 E0167A 0 +OP4 E0167B 0 +OP4 E0167C 0 +OP4 E0167D 0 +OP4 E0167E 0 +OP4 E0167F 0 +OP4 E01680 0 +OP4 E01681 0 +OP4 E01682 0 +OP4 E01683 0 +OP4 E01684 0 +OP4 E01685 0 +OP4 E01686 0 +OP4 E01687 0 +OP4 E01688 0 +OP4 E01689 0 +OP4 E0168A 0 +OP4 E0168B 0 +OP4 E0168C 0 +OP4 E0168D 0 +OP4 E0168E 0 +OP4 E0168F 0 +OP4 E01690 0 +OP4 E01691 0 +OP4 E01692 0 +OP4 E01693 0 +OP4 E01694 0 +OP4 E01695 0 +OP4 E01696 0 +OP4 E01697 0 +OP4 E01698 0 +OP4 E01699 0 +OP4 E0169A 0 +OP4 E0169B 0 +OP4 E0169C 0 +OP4 E0169D 0 +OP4 E0169E 0 +OP4 E0169F 0 +OP4 E016A0 0 +OP4 E016A1 0 +OP4 E016A2 0 +OP4 E016A3 0 +OP4 E016A4 0 +OP4 E016A5 0 +OP4 E016A6 0 +OP4 E016A7 0 +OP4 E016A8 0 +OP4 E016A9 0 +OP4 E016AA 0 +OP4 E016AB 0 +OP4 E016AC 0 +OP4 E016AD 0 +OP4 E016AE 0 +OP4 E016AF 0 +OP4 E016B0 0 +OP4 E016B1 0 +OP4 E016B2 0 +OP4 E016B3 0 +OP4 E016B4 0 +OP4 E016B5 0 +OP4 E016B6 0 +OP4 E016B7 0 +OP4 E016B8 0 +OP4 E016B9 0 +OP4 E016BA 0 +OP4 E016BB 0 +OP4 E016BC 0 +OP4 E016BD 0 +OP4 E016BE 0 +OP4 E016BF 0 +OP4 E016C0 0 +OP4 E016C1 0 +OP4 E016C2 0 +OP4 E016C3 0 +OP4 E016C4 0 +OP4 E016C5 0 +OP4 E016C6 0 +OP4 E016C7 0 +OP4 E016C8 0 +OP4 E016C9 0 +OP4 E016CA 0 +OP4 E016CB 0 +OP4 E016CC 0 +OP4 E016CD 0 +OP4 E016CE 0 +OP4 E016CF 0 +OP4 E016D0 0 +OP4 E016D1 0 +OP4 E016D2 0 +OP4 E016D3 0 +OP4 E016D4 0 +OP4 E016D5 0 +OP4 E016D6 0 +OP4 E016D7 0 +OP4 E016D8 0 +OP4 E016D9 0 +OP4 E016DA 0 +OP4 E016DB 0 +OP4 E016DC 0 +OP4 E016DD 0 +OP4 E016DE 0 +OP4 E016DF 0 +OP4 E016E0 0 +OP4 E016E1 0 +OP4 E016E2 0 +OP4 E016E3 0 +OP4 E016E4 0 +OP4 E016E5 0 +OP4 E016E6 0 +OP4 E016E7 0 +OP4 E016E8 0 +OP4 E016E9 0 +OP4 E016EA 0 +OP4 E016EB 0 +OP4 E016EC 0 +OP4 E016ED 0 +OP4 E016EE 0 +OP4 E016EF 0 +OP4 E016F0 0 +OP4 E016F1 0 +OP4 E016F2 0 +OP4 E016F3 0 +OP4 E016F4 0 +OP4 E016F5 0 +OP4 E016F6 0 +OP4 E016F7 0 +OP4 E016F8 0 +OP4 E016F9 0 +OP4 E016FA 0 +OP4 E016FB 0 +OP4 E016FC 0 +OP4 E016FD 0 +OP4 E016FE 0 +OP4 E016FF 0 +OP4 E01700 0 +OP4 E01701 0 +OP4 E01702 0 +OP4 E01703 0 +OP4 E01704 0 +OP4 E01705 0 +OP4 E01706 0 +OP4 E01707 0 +OP4 E01708 0 +OP4 E01709 0 +OP4 E0170A 0 +OP4 E0170B 0 +OP4 E0170C 0 +OP4 E0170D 0 +OP4 E0170E 0 +OP4 E0170F 0 +OP4 E01710 0 +OP4 E01711 0 +OP4 E01712 0 +OP4 E01713 0 +OP4 E01714 0 +OP4 E01715 0 +OP4 E01716 0 +OP4 E01717 0 +OP4 E01718 0 +OP4 E01719 0 +OP4 E0171A 0 +OP4 E0171B 0 +OP4 E0171C 0 +OP4 E0171D 0 +OP4 E0171E 0 +OP4 E0171F 0 +OP4 E01720 0 +OP4 E01721 0 +OP4 E01722 0 +OP4 E01723 0 +OP4 E01724 0 +OP4 E01725 0 +OP4 E01726 0 +OP4 E01727 0 +OP4 E01728 0 +OP4 E01729 0 +OP4 E0172A 0 +OP4 E0172B 0 +OP4 E0172C 0 +OP4 E0172D 0 +OP4 E0172E 0 +OP4 E0172F 0 +OP4 E01730 0 +OP4 E01731 0 +OP4 E01732 0 +OP4 E01733 0 +OP4 E01734 0 +OP4 E01735 0 +OP4 E01736 0 +OP4 E01737 0 +OP4 E01738 0 +OP4 E01739 0 +OP4 E0173A 0 +OP4 E0173B 0 +OP4 E0173C 0 +OP4 E0173D 0 +OP4 E0173E 0 +OP4 E0173F 0 +OP4 E01740 0 +OP4 E01741 0 +OP4 E01742 0 +OP4 E01743 0 +OP4 E01744 0 +OP4 E01745 0 +OP4 E01746 0 +OP4 E01747 0 +OP4 E01748 0 +OP4 E01749 0 +OP4 E0174A 0 +OP4 E0174B 0 +OP4 E0174C 0 +OP4 E0174D 0 +OP4 E0174E 0 +OP4 E0174F 0 +OP4 E01750 0 +OP4 E01751 0 +OP4 E01752 0 +OP4 E01753 0 +OP4 E01754 0 +OP4 E01755 0 +OP4 E01756 0 +OP4 E01757 0 +OP4 E01758 0 +OP4 E01759 0 +OP4 E0175A 0 +OP4 E0175B 0 +OP4 E0175C 0 +OP4 E0175D 0 +OP4 E0175E 0 +OP4 E0175F 0 +OP4 E01760 0 +OP4 E01761 0 +OP4 E01762 0 +OP4 E01763 0 +OP4 E01764 0 +OP4 E01765 0 +OP4 E01766 0 +OP4 E01767 0 +OP4 E01768 0 +OP4 E01769 0 +OP4 E0176A 0 +OP4 E0176B 0 +OP4 E0176C 0 +OP4 E0176D 0 +OP4 E0176E 0 +OP4 E0176F 0 +OP4 E01770 0 +OP4 E01771 0 +OP4 E01772 0 +OP4 E01773 0 +OP4 E01774 0 +OP4 E01775 0 +OP4 E01776 0 +OP4 E01777 0 +OP4 E01778 0 +OP4 E01779 0 +OP4 E0177A 0 +OP4 E0177B 0 +OP4 E0177C 0 +OP4 E0177D 0 +OP4 E0177E 0 +OP4 E0177F 0 +OP4 E01780 0 +OP4 E01781 0 +OP4 E01782 0 +OP4 E01783 0 +OP4 E01784 0 +OP4 E01785 0 +OP4 E01786 0 +OP4 E01787 0 +OP4 E01788 0 +OP4 E01789 0 +OP4 E0178A 0 +OP4 E0178B 0 +OP4 E0178C 0 +OP4 E0178D 0 +OP4 E0178E 0 +OP4 E0178F 0 +OP4 E01790 0 +OP4 E01791 0 +OP4 E01792 0 +OP4 E01793 0 +OP4 E01794 0 +OP4 E01795 0 +OP4 E01796 0 +OP4 E01797 0 +OP4 E01798 0 +OP4 E01799 0 +OP4 E0179A 0 +OP4 E0179B 0 +OP4 E0179C 0 +OP4 E0179D 0 +OP4 E0179E 0 +OP4 E0179F 0 +OP4 E017A0 0 +OP4 E017A1 0 +OP4 E017A2 0 +OP4 E017A3 0 +OP4 E017A4 0 +OP4 E017A5 0 +OP4 E017A6 0 +OP4 E017A7 0 +OP4 E017A8 0 +OP4 E017A9 0 +OP4 E017AA 0 +OP4 E017AB 0 +OP4 E017AC 0 +OP4 E017AD 0 +OP4 E017AE 0 +OP4 E017AF 0 +OP4 E017B0 0 +OP4 E017B1 0 +OP4 E017B2 0 +OP4 E017B3 0 +OP4 E017B4 0 +OP4 E017B5 0 +OP4 E017B6 0 +OP4 E017B7 0 +OP4 E017B8 0 +OP4 E017B9 0 +OP4 E017BA 0 +OP4 E017BB 0 +OP4 E017BC 0 +OP4 E017BD 0 +OP4 E017BE 0 +OP4 E017BF 0 +OP4 E017C0 0 +OP4 E017C1 0 +OP4 E017C2 0 +OP4 E017C3 0 +OP4 E017C4 0 +OP4 E017C5 0 +OP4 E017C6 0 +OP4 E017C7 0 +OP4 E017C8 0 +OP4 E017C9 0 +OP4 E017CA 0 +OP4 E017CB 0 +OP4 E017CC 0 +OP4 E017CD 0 +OP4 E017CE 0 +OP4 E017CF 0 +OP4 E017D0 0 +OP4 E017D1 0 +OP4 E017D2 0 +OP4 E017D3 0 +OP4 E017D4 0 +OP4 E017D5 0 +OP4 E017D6 0 +OP4 E017D7 0 +OP4 E017D8 0 +OP4 E017D9 0 +OP4 E017DA 0 +OP4 E017DB 0 +OP4 E017DC 0 +OP4 E017DD 0 +OP4 E017DE 0 +OP4 E017DF 0 +OP4 E017E0 0 +OP4 E017E1 0 +OP4 E017E2 0 +OP4 E017E3 0 +OP4 E017E4 0 +OP4 E017E5 0 +OP4 E017E6 0 +OP4 E017E7 0 +OP4 E017E8 0 +OP4 E017E9 0 +OP4 E017EA 0 +OP4 E017EB 0 +OP4 E017EC 0 +OP4 E017ED 0 +OP4 E017EE 0 +OP4 E017EF 0 +OP4 E017F0 0 +OP4 E017F1 0 +OP4 E017F2 0 +OP4 E017F3 0 +OP4 E017F4 0 +OP4 E017F5 0 +OP4 E017F6 0 +OP4 E017F7 0 +OP4 E017F8 0 +OP4 E017F9 0 +OP4 E017FA 0 +OP4 E017FB 0 +OP4 E017FC 0 +OP4 E017FD 0 +OP4 E017FE 0 +OP4 E017FF 0 +OP4 E01800 0 +OP4 E01801 0 +OP4 E01802 0 +OP4 E01803 0 +OP4 E01804 0 +OP4 E01805 0 +OP4 E01806 0 +OP4 E01807 0 +OP4 E01808 0 +OP4 E01809 0 +OP4 E0180A 0 +OP4 E0180B 0 +OP4 E0180C 0 +OP4 E0180D 0 +OP4 E0180E 0 +OP4 E0180F 0 +OP4 E01810 0 +OP4 E01811 0 +OP4 E01812 0 +OP4 E01813 0 +OP4 E01814 0 +OP4 E01815 0 +OP4 E01816 0 +OP4 E01817 0 +OP4 E01818 0 +OP4 E01819 0 +OP4 E0181A 0 +OP4 E0181B 0 +OP4 E0181C 0 +OP4 E0181D 0 +OP4 E0181E 0 +OP4 E0181F 0 +OP4 E01820 0 +OP4 E01821 0 +OP4 E01822 0 +OP4 E01823 0 +OP4 E01824 0 +OP4 E01825 0 +OP4 E01826 0 +OP4 E01827 0 +OP4 E01828 0 +OP4 E01829 0 +OP4 E0182A 0 +OP4 E0182B 0 +OP4 E0182C 0 +OP4 E0182D 0 +OP4 E0182E 0 +OP4 E0182F 0 +OP4 E01830 0 +OP4 E01831 0 +OP4 E01832 0 +OP4 E01833 0 +OP4 E01834 0 +OP4 E01835 0 +OP4 E01836 0 +OP4 E01837 0 +OP4 E01838 0 +OP4 E01839 0 +OP4 E0183A 0 +OP4 E0183B 0 +OP4 E0183C 0 +OP4 E0183D 0 +OP4 E0183E 0 +OP4 E0183F 0 +OP4 E01840 0 +OP4 E01841 0 +OP4 E01842 0 +OP4 E01843 0 +OP4 E01844 0 +OP4 E01845 0 +OP4 E01846 0 +OP4 E01847 0 +OP4 E01848 0 +OP4 E01849 0 +OP4 E0184A 0 +OP4 E0184B 0 +OP4 E0184C 0 +OP4 E0184D 0 +OP4 E0184E 0 +OP4 E0184F 0 +OP4 E01850 0 +OP4 E01851 0 +OP4 E01852 0 +OP4 E01853 0 +OP4 E01854 0 +OP4 E01855 0 +OP4 E01856 0 +OP4 E01857 0 +OP4 E01858 0 +OP4 E01859 0 +OP4 E0185A 0 +OP4 E0185B 0 +OP4 E0185C 0 +OP4 E0185D 0 +OP4 E0185E 0 +OP4 E0185F 0 +OP4 E01860 0 +OP4 E01861 0 +OP4 E01862 0 +OP4 E01863 0 +OP4 E01864 0 +OP4 E01865 0 +OP4 E01866 0 +OP4 E01867 0 +OP4 E01868 0 +OP4 E01869 0 +OP4 E0186A 0 +OP4 E0186B 0 +OP4 E0186C 0 +OP4 E0186D 0 +OP4 E0186E 0 +OP4 E0186F 0 +OP4 E01870 0 +OP4 E01871 0 +OP4 E01872 0 +OP4 E01873 0 +OP4 E01874 0 +OP4 E01875 0 +OP4 E01876 0 +OP4 E01877 0 +OP4 E01878 0 +OP4 E01879 0 +OP4 E0187A 0 +OP4 E0187B 0 +OP4 E0187C 0 +OP4 E0187D 0 +OP4 E0187E 0 +OP4 E0187F 0 +OP4 E01880 0 +OP4 E01881 0 +OP4 E01882 0 +OP4 E01883 0 +OP4 E01884 0 +OP4 E01885 0 +OP4 E01886 0 +OP4 E01887 0 +OP4 E01888 0 +OP4 E01889 0 +OP4 E0188A 0 +OP4 E0188B 0 +OP4 E0188C 0 +OP4 E0188D 0 +OP4 E0188E 0 +OP4 E0188F 0 +OP4 E01890 0 +OP4 E01891 0 +OP4 E01892 0 +OP4 E01893 0 +OP4 E01894 0 +OP4 E01895 0 +OP4 E01896 0 +OP4 E01897 0 +OP4 E01898 0 +OP4 E01899 0 +OP4 E0189A 0 +OP4 E0189B 0 +OP4 E0189C 0 +OP4 E0189D 0 +OP4 E0189E 0 +OP4 E0189F 0 +OP4 E018A0 0 +OP4 E018A1 0 +OP4 E018A2 0 +OP4 E018A3 0 +OP4 E018A4 0 +OP4 E018A5 0 +OP4 E018A6 0 +OP4 E018A7 0 +OP4 E018A8 0 +OP4 E018A9 0 +OP4 E018AA 0 +OP4 E018AB 0 +OP4 E018AC 0 +OP4 E018AD 0 +OP4 E018AE 0 +OP4 E018AF 0 +OP4 E018B0 0 +OP4 E018B1 0 +OP4 E018B2 0 +OP4 E018B3 0 +OP4 E018B4 0 +OP4 E018B5 0 +OP4 E018B6 0 +OP4 E018B7 0 +OP4 E018B8 0 +OP4 E018B9 0 +OP4 E018BA 0 +OP4 E018BB 0 +OP4 E018BC 0 +OP4 E018BD 0 +OP4 E018BE 0 +OP4 E018BF 0 +OP4 E018C0 0 +OP4 E018C1 0 +OP4 E018C2 0 +OP4 E018C3 0 +OP4 E018C4 0 +OP4 E018C5 0 +OP4 E018C6 0 +OP4 E018C7 0 +OP4 E018C8 0 +OP4 E018C9 0 +OP4 E018CA 0 +OP4 E018CB 0 +OP4 E018CC 0 +OP4 E018CD 0 +OP4 E018CE 0 +OP4 E018CF 0 +OP4 E018D0 0 +OP4 E018D1 0 +OP4 E018D2 0 +OP4 E018D3 0 +OP4 E018D4 0 +OP4 E018D5 0 +OP4 E018D6 0 +OP4 E018D7 0 +OP4 E018D8 0 +OP4 E018D9 0 +OP4 E018DA 0 +OP4 E018DB 0 +OP4 E018DC 0 +OP4 E018DD 0 +OP4 E018DE 0 +OP4 E018DF 0 +OP4 E018E0 0 +OP4 E018E1 0 +OP4 E018E2 0 +OP4 E018E3 0 +OP4 E018E4 0 +OP4 E018E5 0 +OP4 E018E6 0 +OP4 E018E7 0 +OP4 E018E8 0 +OP4 E018E9 0 +OP4 E018EA 0 +OP4 E018EB 0 +OP4 E018EC 0 +OP4 E018ED 0 +OP4 E018EE 0 +OP4 E018EF 0 +OP4 E018F0 0 +OP4 E018F1 0 +OP4 E018F2 0 +OP4 E018F3 0 +OP4 E018F4 0 +OP4 E018F5 0 +OP4 E018F6 0 +OP4 E018F7 0 +OP4 E018F8 0 +OP4 E018F9 0 +OP4 E018FA 0 +OP4 E018FB 0 +OP4 E018FC 0 +OP4 E018FD 0 +OP4 E018FE 0 +OP4 E018FF 0 +OP4 E01900 0 +OP4 E01901 0 +OP4 E01902 0 +OP4 E01903 0 +OP4 E01904 0 +OP4 E01905 0 +OP4 E01906 0 +OP4 E01907 0 +OP4 E01908 0 +OP4 E01909 0 +OP4 E0190A 0 +OP4 E0190B 0 +OP4 E0190C 0 +OP4 E0190D 0 +OP4 E0190E 0 +OP4 E0190F 0 +OP4 E01910 0 +OP4 E01911 0 +OP4 E01912 0 +OP4 E01913 0 +OP4 E01914 0 +OP4 E01915 0 +OP4 E01916 0 +OP4 E01917 0 +OP4 E01918 0 +OP4 E01919 0 +OP4 E0191A 0 +OP4 E0191B 0 +OP4 E0191C 0 +OP4 E0191D 0 +OP4 E0191E 0 +OP4 E0191F 0 +OP4 E01920 0 +OP4 E01921 0 +OP4 E01922 0 +OP4 E01923 0 +OP4 E01924 0 +OP4 E01925 0 +OP4 E01926 0 +OP4 E01927 0 +OP4 E01928 0 +OP4 E01929 0 +OP4 E0192A 0 +OP4 E0192B 0 +OP4 E0192C 0 +OP4 E0192D 0 +OP4 E0192E 0 +OP4 E0192F 0 +OP4 E01930 0 +OP4 E01931 0 +OP4 E01932 0 +OP4 E01933 0 +OP4 E01934 0 +OP4 E01935 0 +OP4 E01936 0 +OP4 E01937 0 +OP4 E01938 0 +OP4 E01939 0 +OP4 E0193A 0 +OP4 E0193B 0 +OP4 E0193C 0 +OP4 E0193D 0 +OP4 E0193E 0 +OP4 E0193F 0 +OP4 E01940 0 +OP4 E01941 0 +OP4 E01942 0 +OP4 E01943 0 +OP4 E01944 0 +OP4 E01945 0 +OP4 E01946 0 +OP4 E01947 0 +OP4 E01948 0 +OP4 E01949 0 +OP4 E0194A 0 +OP4 E0194B 0 +OP4 E0194C 0 +OP4 E0194D 0 +OP4 E0194E 0 +OP4 E0194F 0 +OP4 E01950 0 +OP4 E01951 0 +OP4 E01952 0 +OP4 E01953 0 +OP4 E01954 0 +OP4 E01955 0 +OP4 E01956 0 +OP4 E01957 0 +OP4 E01958 0 +OP4 E01959 0 +OP4 E0195A 0 +OP4 E0195B 0 +OP4 E0195C 0 +OP4 E0195D 0 +OP4 E0195E 0 +OP4 E0195F 0 +OP4 E01960 0 +OP4 E01961 0 +OP4 E01962 0 +OP4 E01963 0 +OP4 E01964 0 +OP4 E01965 0 +OP4 E01966 0 +OP4 E01967 0 +OP4 E01968 0 +OP4 E01969 0 +OP4 E0196A 0 +OP4 E0196B 0 +OP4 E0196C 0 +OP4 E0196D 0 +OP4 E0196E 0 +OP4 E0196F 0 +OP4 E01970 0 +OP4 E01971 0 +OP4 E01972 0 +OP4 E01973 0 +OP4 E01974 0 +OP4 E01975 0 +OP4 E01976 0 +OP4 E01977 0 +OP4 E01978 0 +OP4 E01979 0 +OP4 E0197A 0 +OP4 E0197B 0 +OP4 E0197C 0 +OP4 E0197D 0 +OP4 E0197E 0 +OP4 E0197F 0 +OP4 E01980 0 +OP4 E01981 0 +OP4 E01982 0 +OP4 E01983 0 +OP4 E01984 0 +OP4 E01985 0 +OP4 E01986 0 +OP4 E01987 0 +OP4 E01988 0 +OP4 E01989 0 +OP4 E0198A 0 +OP4 E0198B 0 +OP4 E0198C 0 +OP4 E0198D 0 +OP4 E0198E 0 +OP4 E0198F 0 +OP4 E01990 0 +OP4 E01991 0 +OP4 E01992 0 +OP4 E01993 0 +OP4 E01994 0 +OP4 E01995 0 +OP4 E01996 0 +OP4 E01997 0 +OP4 E01998 0 +OP4 E01999 0 +OP4 E0199A 0 +OP4 E0199B 0 +OP4 E0199C 0 +OP4 E0199D 0 +OP4 E0199E 0 +OP4 E0199F 0 +OP4 E019A0 0 +OP4 E019A1 0 +OP4 E019A2 0 +OP4 E019A3 0 +OP4 E019A4 0 +OP4 E019A5 0 +OP4 E019A6 0 +OP4 E019A7 0 +OP4 E019A8 0 +OP4 E019A9 0 +OP4 E019AA 0 +OP4 E019AB 0 +OP4 E019AC 0 +OP4 E019AD 0 +OP4 E019AE 0 +OP4 E019AF 0 +OP4 E019B0 0 +OP4 E019B1 0 +OP4 E019B2 0 +OP4 E019B3 0 +OP4 E019B4 0 +OP4 E019B5 0 +OP4 E019B6 0 +OP4 E019B7 0 +OP4 E019B8 0 +OP4 E019B9 0 +OP4 E019BA 0 +OP4 E019BB 0 +OP4 E019BC 0 +OP4 E019BD 0 +OP4 E019BE 0 +OP4 E019BF 0 +OP4 E019C0 0 +OP4 E019C1 0 +OP4 E019C2 0 +OP4 E019C3 0 +OP4 E019C4 0 +OP4 E019C5 0 +OP4 E019C6 0 +OP4 E019C7 0 +OP4 E019C8 0 +OP4 E019C9 0 +OP4 E019CA 0 +OP4 E019CB 0 +OP4 E019CC 0 +OP4 E019CD 0 +OP4 E019CE 0 +OP4 E019CF 0 +OP4 E019D0 0 +OP4 E019D1 0 +OP4 E019D2 0 +OP4 E019D3 0 +OP4 E019D4 0 +OP4 E019D5 0 +OP4 E019D6 0 +OP4 E019D7 0 +OP4 E019D8 0 +OP4 E019D9 0 +OP4 E019DA 0 +OP4 E019DB 0 +OP4 E019DC 0 +OP4 E019DD 0 +OP4 E019DE 0 +OP4 E019DF 0 +OP4 E019E0 0 +OP4 E019E1 0 +OP4 E019E2 0 +OP4 E019E3 0 +OP4 E019E4 0 +OP4 E019E5 0 +OP4 E019E6 0 +OP4 E019E7 0 +OP4 E019E8 0 +OP4 E019E9 0 +OP4 E019EA 0 +OP4 E019EB 0 +OP4 E019EC 0 +OP4 E019ED 0 +OP4 E019EE 0 +OP4 E019EF 0 +OP4 E019F0 0 +OP4 E019F1 0 +OP4 E019F2 0 +OP4 E019F3 0 +OP4 E019F4 0 +OP4 E019F5 0 +OP4 E019F6 0 +OP4 E019F7 0 +OP4 E019F8 0 +OP4 E019F9 0 +OP4 E019FA 0 +OP4 E019FB 0 +OP4 E019FC 0 +OP4 E019FD 0 +OP4 E019FE 0 +OP4 E019FF 0 +OP4 E01A00 0 +OP4 E01A01 0 +OP4 E01A02 0 +OP4 E01A03 0 +OP4 E01A04 0 +OP4 E01A05 0 +OP4 E01A06 0 +OP4 E01A07 0 +OP4 E01A08 0 +OP4 E01A09 0 +OP4 E01A0A 0 +OP4 E01A0B 0 +OP4 E01A0C 0 +OP4 E01A0D 0 +OP4 E01A0E 0 +OP4 E01A0F 0 +OP4 E01A10 0 +OP4 E01A11 0 +OP4 E01A12 0 +OP4 E01A13 0 +OP4 E01A14 0 +OP4 E01A15 0 +OP4 E01A16 0 +OP4 E01A17 0 +OP4 E01A18 0 +OP4 E01A19 0 +OP4 E01A1A 0 +OP4 E01A1B 0 +OP4 E01A1C 0 +OP4 E01A1D 0 +OP4 E01A1E 0 +OP4 E01A1F 0 +OP4 E01A20 0 +OP4 E01A21 0 +OP4 E01A22 0 +OP4 E01A23 0 +OP4 E01A24 0 +OP4 E01A25 0 +OP4 E01A26 0 +OP4 E01A27 0 +OP4 E01A28 0 +OP4 E01A29 0 +OP4 E01A2A 0 +OP4 E01A2B 0 +OP4 E01A2C 0 +OP4 E01A2D 0 +OP4 E01A2E 0 +OP4 E01A2F 0 +OP4 E01A30 0 +OP4 E01A31 0 +OP4 E01A32 0 +OP4 E01A33 0 +OP4 E01A34 0 +OP4 E01A35 0 +OP4 E01A36 0 +OP4 E01A37 0 +OP4 E01A38 0 +OP4 E01A39 0 +OP4 E01A3A 0 +OP4 E01A3B 0 +OP4 E01A3C 0 +OP4 E01A3D 0 +OP4 E01A3E 0 +OP4 E01A3F 0 +OP4 E01A40 0 +OP4 E01A41 0 +OP4 E01A42 0 +OP4 E01A43 0 +OP4 E01A44 0 +OP4 E01A45 0 +OP4 E01A46 0 +OP4 E01A47 0 +OP4 E01A48 0 +OP4 E01A49 0 +OP4 E01A4A 0 +OP4 E01A4B 0 +OP4 E01A4C 0 +OP4 E01A4D 0 +OP4 E01A4E 0 +OP4 E01A4F 0 +OP4 E01A50 0 +OP4 E01A51 0 +OP4 E01A52 0 +OP4 E01A53 0 +OP4 E01A54 0 +OP4 E01A55 0 +OP4 E01A56 0 +OP4 E01A57 0 +OP4 E01A58 0 +OP4 E01A59 0 +OP4 E01A5A 0 +OP4 E01A5B 0 +OP4 E01A5C 0 +OP4 E01A5D 0 +OP4 E01A5E 0 +OP4 E01A5F 0 +OP4 E01A60 0 +OP4 E01A61 0 +OP4 E01A62 0 +OP4 E01A63 0 +OP4 E01A64 0 +OP4 E01A65 0 +OP4 E01A66 0 +OP4 E01A67 0 +OP4 E01A68 0 +OP4 E01A69 0 +OP4 E01A6A 0 +OP4 E01A6B 0 +OP4 E01A6C 0 +OP4 E01A6D 0 +OP4 E01A6E 0 +OP4 E01A6F 0 +OP4 E01A70 0 +OP4 E01A71 0 +OP4 E01A72 0 +OP4 E01A73 0 +OP4 E01A74 0 +OP4 E01A75 0 +OP4 E01A76 0 +OP4 E01A77 0 +OP4 E01A78 0 +OP4 E01A79 0 +OP4 E01A7A 0 +OP4 E01A7B 0 +OP4 E01A7C 0 +OP4 E01A7D 0 +OP4 E01A7E 0 +OP4 E01A7F 0 +OP4 E01A80 0 +OP4 E01A81 0 +OP4 E01A82 0 +OP4 E01A83 0 +OP4 E01A84 0 +OP4 E01A85 0 +OP4 E01A86 0 +OP4 E01A87 0 +OP4 E01A88 0 +OP4 E01A89 0 +OP4 E01A8A 0 +OP4 E01A8B 0 +OP4 E01A8C 0 +OP4 E01A8D 0 +OP4 E01A8E 0 +OP4 E01A8F 0 +OP4 E01A90 0 +OP4 E01A91 0 +OP4 E01A92 0 +OP4 E01A93 0 +OP4 E01A94 0 +OP4 E01A95 0 +OP4 E01A96 0 +OP4 E01A97 0 +OP4 E01A98 0 +OP4 E01A99 0 +OP4 E01A9A 0 +OP4 E01A9B 0 +OP4 E01A9C 0 +OP4 E01A9D 0 +OP4 E01A9E 0 +OP4 E01A9F 0 +OP4 E01AA0 0 +OP4 E01AA1 0 +OP4 E01AA2 0 +OP4 E01AA3 0 +OP4 E01AA4 0 +OP4 E01AA5 0 +OP4 E01AA6 0 +OP4 E01AA7 0 +OP4 E01AA8 0 +OP4 E01AA9 0 +OP4 E01AAA 0 +OP4 E01AAB 0 +OP4 E01AAC 0 +OP4 E01AAD 0 +OP4 E01AAE 0 +OP4 E01AAF 0 +OP4 E01AB0 0 +OP4 E01AB1 0 +OP4 E01AB2 0 +OP4 E01AB3 0 +OP4 E01AB4 0 +OP4 E01AB5 0 +OP4 E01AB6 0 +OP4 E01AB7 0 +OP4 E01AB8 0 +OP4 E01AB9 0 +OP4 E01ABA 0 +OP4 E01ABB 0 +OP4 E01ABC 0 +OP4 E01ABD 0 +OP4 E01ABE 0 +OP4 E01ABF 0 +OP4 E01AC0 0 +OP4 E01AC1 0 +OP4 E01AC2 0 +OP4 E01AC3 0 +OP4 E01AC4 0 +OP4 E01AC5 0 +OP4 E01AC6 0 +OP4 E01AC7 0 +OP4 E01AC8 0 +OP4 E01AC9 0 +OP4 E01ACA 0 +OP4 E01ACB 0 +OP4 E01ACC 0 +OP4 E01ACD 0 +OP4 E01ACE 0 +OP4 E01ACF 0 +OP4 E01AD0 0 +OP4 E01AD1 0 +OP4 E01AD2 0 +OP4 E01AD3 0 +OP4 E01AD4 0 +OP4 E01AD5 0 +OP4 E01AD6 0 +OP4 E01AD7 0 +OP4 E01AD8 0 +OP4 E01AD9 0 +OP4 E01ADA 0 +OP4 E01ADB 0 +OP4 E01ADC 0 +OP4 E01ADD 0 +OP4 E01ADE 0 +OP4 E01ADF 0 +OP4 E01AE0 0 +OP4 E01AE1 0 +OP4 E01AE2 0 +OP4 E01AE3 0 +OP4 E01AE4 0 +OP4 E01AE5 0 +OP4 E01AE6 0 +OP4 E01AE7 0 +OP4 E01AE8 0 +OP4 E01AE9 0 +OP4 E01AEA 0 +OP4 E01AEB 0 +OP4 E01AEC 0 +OP4 E01AED 0 +OP4 E01AEE 0 +OP4 E01AEF 0 +OP4 E01AF0 0 +OP4 E01AF1 0 +OP4 E01AF2 0 +OP4 E01AF3 0 +OP4 E01AF4 0 +OP4 E01AF5 0 +OP4 E01AF6 0 +OP4 E01AF7 0 +OP4 E01AF8 0 +OP4 E01AF9 0 +OP4 E01AFA 0 +OP4 E01AFB 0 +OP4 E01AFC 0 +OP4 E01AFD 0 +OP4 E01AFE 0 +OP4 E01AFF 0 +OP4 E01B00 0 +OP4 E01B01 0 +OP4 E01B02 0 +OP4 E01B03 0 +OP4 E01B04 0 +OP4 E01B05 0 +OP4 E01B06 0 +OP4 E01B07 0 +OP4 E01B08 0 +OP4 E01B09 0 +OP4 E01B0A 0 +OP4 E01B0B 0 +OP4 E01B0C 0 +OP4 E01B0D 0 +OP4 E01B0E 0 +OP4 E01B0F 0 +OP4 E01B10 0 +OP4 E01B11 0 +OP4 E01B12 0 +OP4 E01B13 0 +OP4 E01B14 0 +OP4 E01B15 0 +OP4 E01B16 0 +OP4 E01B17 0 +OP4 E01B18 0 +OP4 E01B19 0 +OP4 E01B1A 0 +OP4 E01B1B 0 +OP4 E01B1C 0 +OP4 E01B1D 0 +OP4 E01B1E 0 +OP4 E01B1F 0 +OP4 E01B20 0 +OP4 E01B21 0 +OP4 E01B22 0 +OP4 E01B23 0 +OP4 E01B24 0 +OP4 E01B25 0 +OP4 E01B26 0 +OP4 E01B27 0 +OP4 E01B28 0 +OP4 E01B29 0 +OP4 E01B2A 0 +OP4 E01B2B 0 +OP4 E01B2C 0 +OP4 E01B2D 0 +OP4 E01B2E 0 +OP4 E01B2F 0 +OP4 E01B30 0 +OP4 E01B31 0 +OP4 E01B32 0 +OP4 E01B33 0 +OP4 E01B34 0 +OP4 E01B35 0 +OP4 E01B36 0 +OP4 E01B37 0 +OP4 E01B38 0 +OP4 E01B39 0 +OP4 E01B3A 0 +OP4 E01B3B 0 +OP4 E01B3C 0 +OP4 E01B3D 0 +OP4 E01B3E 0 +OP4 E01B3F 0 +OP4 E01B40 0 +OP4 E01B41 0 +OP4 E01B42 0 +OP4 E01B43 0 +OP4 E01B44 0 +OP4 E01B45 0 +OP4 E01B46 0 +OP4 E01B47 0 +OP4 E01B48 0 +OP4 E01B49 0 +OP4 E01B4A 0 +OP4 E01B4B 0 +OP4 E01B4C 0 +OP4 E01B4D 0 +OP4 E01B4E 0 +OP4 E01B4F 0 +OP4 E01B50 0 +OP4 E01B51 0 +OP4 E01B52 0 +OP4 E01B53 0 +OP4 E01B54 0 +OP4 E01B55 0 +OP4 E01B56 0 +OP4 E01B57 0 +OP4 E01B58 0 +OP4 E01B59 0 +OP4 E01B5A 0 +OP4 E01B5B 0 +OP4 E01B5C 0 +OP4 E01B5D 0 +OP4 E01B5E 0 +OP4 E01B5F 0 +OP4 E01B60 0 +OP4 E01B61 0 +OP4 E01B62 0 +OP4 E01B63 0 +OP4 E01B64 0 +OP4 E01B65 0 +OP4 E01B66 0 +OP4 E01B67 0 +OP4 E01B68 0 +OP4 E01B69 0 +OP4 E01B6A 0 +OP4 E01B6B 0 +OP4 E01B6C 0 +OP4 E01B6D 0 +OP4 E01B6E 0 +OP4 E01B6F 0 +OP4 E01B70 0 +OP4 E01B71 0 +OP4 E01B72 0 +OP4 E01B73 0 +OP4 E01B74 0 +OP4 E01B75 0 +OP4 E01B76 0 +OP4 E01B77 0 +OP4 E01B78 0 +OP4 E01B79 0 +OP4 E01B7A 0 +OP4 E01B7B 0 +OP4 E01B7C 0 +OP4 E01B7D 0 +OP4 E01B7E 0 +OP4 E01B7F 0 +OP4 E01B80 0 +OP4 E01B81 0 +OP4 E01B82 0 +OP4 E01B83 0 +OP4 E01B84 0 +OP4 E01B85 0 +OP4 E01B86 0 +OP4 E01B87 0 +OP4 E01B88 0 +OP4 E01B89 0 +OP4 E01B8A 0 +OP4 E01B8B 0 +OP4 E01B8C 0 +OP4 E01B8D 0 +OP4 E01B8E 0 +OP4 E01B8F 0 +OP4 E01B90 0 +OP4 E01B91 0 +OP4 E01B92 0 +OP4 E01B93 0 +OP4 E01B94 0 +OP4 E01B95 0 +OP4 E01B96 0 +OP4 E01B97 0 +OP4 E01B98 0 +OP4 E01B99 0 +OP4 E01B9A 0 +OP4 E01B9B 0 +OP4 E01B9C 0 +OP4 E01B9D 0 +OP4 E01B9E 0 +OP4 E01B9F 0 +OP4 E01BA0 0 +OP4 E01BA1 0 +OP4 E01BA2 0 +OP4 E01BA3 0 +OP4 E01BA4 0 +OP4 E01BA5 0 +OP4 E01BA6 0 +OP4 E01BA7 0 +OP4 E01BA8 0 +OP4 E01BA9 0 +OP4 E01BAA 0 +OP4 E01BAB 0 +OP4 E01BAC 0 +OP4 E01BAD 0 +OP4 E01BAE 0 +OP4 E01BAF 0 +OP4 E01BB0 0 +OP4 E01BB1 0 +OP4 E01BB2 0 +OP4 E01BB3 0 +OP4 E01BB4 0 +OP4 E01BB5 0 +OP4 E01BB6 0 +OP4 E01BB7 0 +OP4 E01BB8 0 +OP4 E01BB9 0 +OP4 E01BBA 0 +OP4 E01BBB 0 +OP4 E01BBC 0 +OP4 E01BBD 0 +OP4 E01BBE 0 +OP4 E01BBF 0 +OP4 E01BC0 0 +OP4 E01BC1 0 +OP4 E01BC2 0 +OP4 E01BC3 0 +OP4 E01BC4 0 +OP4 E01BC5 0 +OP4 E01BC6 0 +OP4 E01BC7 0 +OP4 E01BC8 0 +OP4 E01BC9 0 +OP4 E01BCA 0 +OP4 E01BCB 0 +OP4 E01BCC 0 +OP4 E01BCD 0 +OP4 E01BCE 0 +OP4 E01BCF 0 +OP4 E01BD0 0 +OP4 E01BD1 0 +OP4 E01BD2 0 +OP4 E01BD3 0 +OP4 E01BD4 0 +OP4 E01BD5 0 +OP4 E01BD6 0 +OP4 E01BD7 0 +OP4 E01BD8 0 +OP4 E01BD9 0 +OP4 E01BDA 0 +OP4 E01BDB 0 +OP4 E01BDC 0 +OP4 E01BDD 0 +OP4 E01BDE 0 +OP4 E01BDF 0 +OP4 E01BE0 0 +OP4 E01BE1 0 +OP4 E01BE2 0 +OP4 E01BE3 0 +OP4 E01BE4 0 +OP4 E01BE5 0 +OP4 E01BE6 0 +OP4 E01BE7 0 +OP4 E01BE8 0 +OP4 E01BE9 0 +OP4 E01BEA 0 +OP4 E01BEB 0 +OP4 E01BEC 0 +OP4 E01BED 0 +OP4 E01BEE 0 +OP4 E01BEF 0 +OP4 E01BF0 0 +OP4 E01BF1 0 +OP4 E01BF2 0 +OP4 E01BF3 0 +OP4 E01BF4 0 +OP4 E01BF5 0 +OP4 E01BF6 0 +OP4 E01BF7 0 +OP4 E01BF8 0 +OP4 E01BF9 0 +OP4 E01BFA 0 +OP4 E01BFB 0 +OP4 E01BFC 0 +OP4 E01BFD 0 +OP4 E01BFE 0 +OP4 E01BFF 0 +OP4 E01C00 0 +OP4 E01C01 0 +OP4 E01C02 0 +OP4 E01C03 0 +OP4 E01C04 0 +OP4 E01C05 0 +OP4 E01C06 0 +OP4 E01C07 0 +OP4 E01C08 0 +OP4 E01C09 0 +OP4 E01C0A 0 +OP4 E01C0B 0 +OP4 E01C0C 0 +OP4 E01C0D 0 +OP4 E01C0E 0 +OP4 E01C0F 0 +OP4 E01C10 0 +OP4 E01C11 0 +OP4 E01C12 0 +OP4 E01C13 0 +OP4 E01C14 0 +OP4 E01C15 0 +OP4 E01C16 0 +OP4 E01C17 0 +OP4 E01C18 0 +OP4 E01C19 0 +OP4 E01C1A 0 +OP4 E01C1B 0 +OP4 E01C1C 0 +OP4 E01C1D 0 +OP4 E01C1E 0 +OP4 E01C1F 0 +OP4 E01C20 0 +OP4 E01C21 0 +OP4 E01C22 0 +OP4 E01C23 0 +OP4 E01C24 0 +OP4 E01C25 0 +OP4 E01C26 0 +OP4 E01C27 0 +OP4 E01C28 0 +OP4 E01C29 0 +OP4 E01C2A 0 +OP4 E01C2B 0 +OP4 E01C2C 0 +OP4 E01C2D 0 +OP4 E01C2E 0 +OP4 E01C2F 0 +OP4 E01C30 0 +OP4 E01C31 0 +OP4 E01C32 0 +OP4 E01C33 0 +OP4 E01C34 0 +OP4 E01C35 0 +OP4 E01C36 0 +OP4 E01C37 0 +OP4 E01C38 0 +OP4 E01C39 0 +OP4 E01C3A 0 +OP4 E01C3B 0 +OP4 E01C3C 0 +OP4 E01C3D 0 +OP4 E01C3E 0 +OP4 E01C3F 0 +OP4 E01C40 0 +OP4 E01C41 0 +OP4 E01C42 0 +OP4 E01C43 0 +OP4 E01C44 0 +OP4 E01C45 0 +OP4 E01C46 0 +OP4 E01C47 0 +OP4 E01C48 0 +OP4 E01C49 0 +OP4 E01C4A 0 +OP4 E01C4B 0 +OP4 E01C4C 0 +OP4 E01C4D 0 +OP4 E01C4E 0 +OP4 E01C4F 0 +OP4 E01C50 0 +OP4 E01C51 0 +OP4 E01C52 0 +OP4 E01C53 0 +OP4 E01C54 0 +OP4 E01C55 0 +OP4 E01C56 0 +OP4 E01C57 0 +OP4 E01C58 0 +OP4 E01C59 0 +OP4 E01C5A 0 +OP4 E01C5B 0 +OP4 E01C5C 0 +OP4 E01C5D 0 +OP4 E01C5E 0 +OP4 E01C5F 0 +OP4 E01C60 0 +OP4 E01C61 0 +OP4 E01C62 0 +OP4 E01C63 0 +OP4 E01C64 0 +OP4 E01C65 0 +OP4 E01C66 0 +OP4 E01C67 0 +OP4 E01C68 0 +OP4 E01C69 0 +OP4 E01C6A 0 +OP4 E01C6B 0 +OP4 E01C6C 0 +OP4 E01C6D 0 +OP4 E01C6E 0 +OP4 E01C6F 0 +OP4 E01C70 0 +OP4 E01C71 0 +OP4 E01C72 0 +OP4 E01C73 0 +OP4 E01C74 0 +OP4 E01C75 0 +OP4 E01C76 0 +OP4 E01C77 0 +OP4 E01C78 0 +OP4 E01C79 0 +OP4 E01C7A 0 +OP4 E01C7B 0 +OP4 E01C7C 0 +OP4 E01C7D 0 +OP4 E01C7E 0 +OP4 E01C7F 0 +OP4 E01C80 0 +OP4 E01C81 0 +OP4 E01C82 0 +OP4 E01C83 0 +OP4 E01C84 0 +OP4 E01C85 0 +OP4 E01C86 0 +OP4 E01C87 0 +OP4 E01C88 0 +OP4 E01C89 0 +OP4 E01C8A 0 +OP4 E01C8B 0 +OP4 E01C8C 0 +OP4 E01C8D 0 +OP4 E01C8E 0 +OP4 E01C8F 0 +OP4 E01C90 0 +OP4 E01C91 0 +OP4 E01C92 0 +OP4 E01C93 0 +OP4 E01C94 0 +OP4 E01C95 0 +OP4 E01C96 0 +OP4 E01C97 0 +OP4 E01C98 0 +OP4 E01C99 0 +OP4 E01C9A 0 +OP4 E01C9B 0 +OP4 E01C9C 0 +OP4 E01C9D 0 +OP4 E01C9E 0 +OP4 E01C9F 0 +OP4 E01CA0 0 +OP4 E01CA1 0 +OP4 E01CA2 0 +OP4 E01CA3 0 +OP4 E01CA4 0 +OP4 E01CA5 0 +OP4 E01CA6 0 +OP4 E01CA7 0 +OP4 E01CA8 0 +OP4 E01CA9 0 +OP4 E01CAA 0 +OP4 E01CAB 0 +OP4 E01CAC 0 +OP4 E01CAD 0 +OP4 E01CAE 0 +OP4 E01CAF 0 +OP4 E01CB0 0 +OP4 E01CB1 0 +OP4 E01CB2 0 +OP4 E01CB3 0 +OP4 E01CB4 0 +OP4 E01CB5 0 +OP4 E01CB6 0 +OP4 E01CB7 0 +OP4 E01CB8 0 +OP4 E01CB9 0 +OP4 E01CBA 0 +OP4 E01CBB 0 +OP4 E01CBC 0 +OP4 E01CBD 0 +OP4 E01CBE 0 +OP4 E01CBF 0 +OP4 E01CC0 0 +OP4 E01CC1 0 +OP4 E01CC2 0 +OP4 E01CC3 0 +OP4 E01CC4 0 +OP4 E01CC5 0 +OP4 E01CC6 0 +OP4 E01CC7 0 +OP4 E01CC8 0 +OP4 E01CC9 0 +OP4 E01CCA 0 +OP4 E01CCB 0 +OP4 E01CCC 0 +OP4 E01CCD 0 +OP4 E01CCE 0 +OP4 E01CCF 0 +OP4 E01CD0 0 +OP4 E01CD1 0 +OP4 E01CD2 0 +OP4 E01CD3 0 +OP4 E01CD4 0 +OP4 E01CD5 0 +OP4 E01CD6 0 +OP4 E01CD7 0 +OP4 E01CD8 0 +OP4 E01CD9 0 +OP4 E01CDA 0 +OP4 E01CDB 0 +OP4 E01CDC 0 +OP4 E01CDD 0 +OP4 E01CDE 0 +OP4 E01CDF 0 +OP4 E01CE0 0 +OP4 E01CE1 0 +OP4 E01CE2 0 +OP4 E01CE3 0 +OP4 E01CE4 0 +OP4 E01CE5 0 +OP4 E01CE6 0 +OP4 E01CE7 0 +OP4 E01CE8 0 +OP4 E01CE9 0 +OP4 E01CEA 0 +OP4 E01CEB 0 +OP4 E01CEC 0 +OP4 E01CED 0 +OP4 E01CEE 0 +OP4 E01CEF 0 +OP4 E01CF0 0 +OP4 E01CF1 0 +OP4 E01CF2 0 +OP4 E01CF3 0 +OP4 E01CF4 0 +OP4 E01CF5 0 +OP4 E01CF6 0 +OP4 E01CF7 0 +OP4 E01CF8 0 +OP4 E01CF9 0 +OP4 E01CFA 0 +OP4 E01CFB 0 +OP4 E01CFC 0 +OP4 E01CFD 0 +OP4 E01CFE 0 +OP4 E01CFF 0 +OP4 E01D00 0 +OP4 E01D01 0 +OP4 E01D02 0 +OP4 E01D03 0 +OP4 E01D04 0 +OP4 E01D05 0 +OP4 E01D06 0 +OP4 E01D07 0 +OP4 E01D08 0 +OP4 E01D09 0 +OP4 E01D0A 0 +OP4 E01D0B 0 +OP4 E01D0C 0 +OP4 E01D0D 0 +OP4 E01D0E 0 +OP4 E01D0F 0 +OP4 E01D10 0 +OP4 E01D11 0 +OP4 E01D12 0 +OP4 E01D13 0 +OP4 E01D14 0 +OP4 E01D15 0 +OP4 E01D16 0 +OP4 E01D17 0 +OP4 E01D18 0 +OP4 E01D19 0 +OP4 E01D1A 0 +OP4 E01D1B 0 +OP4 E01D1C 0 +OP4 E01D1D 0 +OP4 E01D1E 0 +OP4 E01D1F 0 +OP4 E01D20 0 +OP4 E01D21 0 +OP4 E01D22 0 +OP4 E01D23 0 +OP4 E01D24 0 +OP4 E01D25 0 +OP4 E01D26 0 +OP4 E01D27 0 +OP4 E01D28 0 +OP4 E01D29 0 +OP4 E01D2A 0 +OP4 E01D2B 0 +OP4 E01D2C 0 +OP4 E01D2D 0 +OP4 E01D2E 0 +OP4 E01D2F 0 +OP4 E01D30 0 +OP4 E01D31 0 +OP4 E01D32 0 +OP4 E01D33 0 +OP4 E01D34 0 +OP4 E01D35 0 +OP4 E01D36 0 +OP4 E01D37 0 +OP4 E01D38 0 +OP4 E01D39 0 +OP4 E01D3A 0 +OP4 E01D3B 0 +OP4 E01D3C 0 +OP4 E01D3D 0 +OP4 E01D3E 0 +OP4 E01D3F 0 +OP4 E01D40 0 +OP4 E01D41 0 +OP4 E01D42 0 +OP4 E01D43 0 +OP4 E01D44 0 +OP4 E01D45 0 +OP4 E01D46 0 +OP4 E01D47 0 +OP4 E01D48 0 +OP4 E01D49 0 +OP4 E01D4A 0 +OP4 E01D4B 0 +OP4 E01D4C 0 +OP4 E01D4D 0 +OP4 E01D4E 0 +OP4 E01D4F 0 +OP4 E01D50 0 +OP4 E01D51 0 +OP4 E01D52 0 +OP4 E01D53 0 +OP4 E01D54 0 +OP4 E01D55 0 +OP4 E01D56 0 +OP4 E01D57 0 +OP4 E01D58 0 +OP4 E01D59 0 +OP4 E01D5A 0 +OP4 E01D5B 0 +OP4 E01D5C 0 +OP4 E01D5D 0 +OP4 E01D5E 0 +OP4 E01D5F 0 +OP4 E01D60 0 +OP4 E01D61 0 +OP4 E01D62 0 +OP4 E01D63 0 +OP4 E01D64 0 +OP4 E01D65 0 +OP4 E01D66 0 +OP4 E01D67 0 +OP4 E01D68 0 +OP4 E01D69 0 +OP4 E01D6A 0 +OP4 E01D6B 0 +OP4 E01D6C 0 +OP4 E01D6D 0 +OP4 E01D6E 0 +OP4 E01D6F 0 +OP4 E01D70 0 +OP4 E01D71 0 +OP4 E01D72 0 +OP4 E01D73 0 +OP4 E01D74 0 +OP4 E01D75 0 +OP4 E01D76 0 +OP4 E01D77 0 +OP4 E01D78 0 +OP4 E01D79 0 +OP4 E01D7A 0 +OP4 E01D7B 0 +OP4 E01D7C 0 +OP4 E01D7D 0 +OP4 E01D7E 0 +OP4 E01D7F 0 +OP4 E01D80 0 +OP4 E01D81 0 +OP4 E01D82 0 +OP4 E01D83 0 +OP4 E01D84 0 +OP4 E01D85 0 +OP4 E01D86 0 +OP4 E01D87 0 +OP4 E01D88 0 +OP4 E01D89 0 +OP4 E01D8A 0 +OP4 E01D8B 0 +OP4 E01D8C 0 +OP4 E01D8D 0 +OP4 E01D8E 0 +OP4 E01D8F 0 +OP4 E01D90 0 +OP4 E01D91 0 +OP4 E01D92 0 +OP4 E01D93 0 +OP4 E01D94 0 +OP4 E01D95 0 +OP4 E01D96 0 +OP4 E01D97 0 +OP4 E01D98 0 +OP4 E01D99 0 +OP4 E01D9A 0 +OP4 E01D9B 0 +OP4 E01D9C 0 +OP4 E01D9D 0 +OP4 E01D9E 0 +OP4 E01D9F 0 +OP4 E01DA0 0 +OP4 E01DA1 0 +OP4 E01DA2 0 +OP4 E01DA3 0 +OP4 E01DA4 0 +OP4 E01DA5 0 +OP4 E01DA6 0 +OP4 E01DA7 0 +OP4 E01DA8 0 +OP4 E01DA9 0 +OP4 E01DAA 0 +OP4 E01DAB 0 +OP4 E01DAC 0 +OP4 E01DAD 0 +OP4 E01DAE 0 +OP4 E01DAF 0 +OP4 E01DB0 0 +OP4 E01DB1 0 +OP4 E01DB2 0 +OP4 E01DB3 0 +OP4 E01DB4 0 +OP4 E01DB5 0 +OP4 E01DB6 0 +OP4 E01DB7 0 +OP4 E01DB8 0 +OP4 E01DB9 0 +OP4 E01DBA 0 +OP4 E01DBB 0 +OP4 E01DBC 0 +OP4 E01DBD 0 +OP4 E01DBE 0 +OP4 E01DBF 0 +OP4 E01DC0 0 +OP4 E01DC1 0 +OP4 E01DC2 0 +OP4 E01DC3 0 +OP4 E01DC4 0 +OP4 E01DC5 0 +OP4 E01DC6 0 +OP4 E01DC7 0 +OP4 E01DC8 0 +OP4 E01DC9 0 +OP4 E01DCA 0 +OP4 E01DCB 0 +OP4 E01DCC 0 +OP4 E01DCD 0 +OP4 E01DCE 0 +OP4 E01DCF 0 +OP4 E01DD0 0 +OP4 E01DD1 0 +OP4 E01DD2 0 +OP4 E01DD3 0 +OP4 E01DD4 0 +OP4 E01DD5 0 +OP4 E01DD6 0 +OP4 E01DD7 0 +OP4 E01DD8 0 +OP4 E01DD9 0 +OP4 E01DDA 0 +OP4 E01DDB 0 +OP4 E01DDC 0 +OP4 E01DDD 0 +OP4 E01DDE 0 +OP4 E01DDF 0 +OP4 E01DE0 0 +OP4 E01DE1 0 +OP4 E01DE2 0 +OP4 E01DE3 0 +OP4 E01DE4 0 +OP4 E01DE5 0 +OP4 E01DE6 0 +OP4 E01DE7 0 +OP4 E01DE8 0 +OP4 E01DE9 0 +OP4 E01DEA 0 +OP4 E01DEB 0 +OP4 E01DEC 0 +OP4 E01DED 0 +OP4 E01DEE 0 +OP4 E01DEF 0 +OP4 E01DF0 0 +OP4 E01DF1 0 +OP4 E01DF2 0 +OP4 E01DF3 0 +OP4 E01DF4 0 +OP4 E01DF5 0 +OP4 E01DF6 0 +OP4 E01DF7 0 +OP4 E01DF8 0 +OP4 E01DF9 0 +OP4 E01DFA 0 +OP4 E01DFB 0 +OP4 E01DFC 0 +OP4 E01DFD 0 +OP4 E01DFE 0 +OP4 E01DFF 0 +OP4 E01E00 0 +OP4 E01E01 0 +OP4 E01E02 0 +OP4 E01E03 0 +OP4 E01E04 0 +OP4 E01E05 0 +OP4 E01E06 0 +OP4 E01E07 0 +OP4 E01E08 0 +OP4 E01E09 0 +OP4 E01E0A 0 +OP4 E01E0B 0 +OP4 E01E0C 0 +OP4 E01E0D 0 +OP4 E01E0E 0 +OP4 E01E0F 0 +OP4 E01E10 0 +OP4 E01E11 0 +OP4 E01E12 0 +OP4 E01E13 0 +OP4 E01E14 0 +OP4 E01E15 0 +OP4 E01E16 0 +OP4 E01E17 0 +OP4 E01E18 0 +OP4 E01E19 0 +OP4 E01E1A 0 +OP4 E01E1B 0 +OP4 E01E1C 0 +OP4 E01E1D 0 +OP4 E01E1E 0 +OP4 E01E1F 0 +OP4 E01E20 0 +OP4 E01E21 0 +OP4 E01E22 0 +OP4 E01E23 0 +OP4 E01E24 0 +OP4 E01E25 0 +OP4 E01E26 0 +OP4 E01E27 0 +OP4 E01E28 0 +OP4 E01E29 0 +OP4 E01E2A 0 +OP4 E01E2B 0 +OP4 E01E2C 0 +OP4 E01E2D 0 +OP4 E01E2E 0 +OP4 E01E2F 0 +OP4 E01E30 0 +OP4 E01E31 0 +OP4 E01E32 0 +OP4 E01E33 0 +OP4 E01E34 0 +OP4 E01E35 0 +OP4 E01E36 0 +OP4 E01E37 0 +OP4 E01E38 0 +OP4 E01E39 0 +OP4 E01E3A 0 +OP4 E01E3B 0 +OP4 E01E3C 0 +OP4 E01E3D 0 +OP4 E01E3E 0 +OP4 E01E3F 0 +OP4 E01E40 0 +OP4 E01E41 0 +OP4 E01E42 0 +OP4 E01E43 0 +OP4 E01E44 0 +OP4 E01E45 0 +OP4 E01E46 0 +OP4 E01E47 0 +OP4 E01E48 0 +OP4 E01E49 0 +OP4 E01E4A 0 +OP4 E01E4B 0 +OP4 E01E4C 0 +OP4 E01E4D 0 +OP4 E01E4E 0 +OP4 E01E4F 0 +OP4 E01E50 0 +OP4 E01E51 0 +OP4 E01E52 0 +OP4 E01E53 0 +OP4 E01E54 0 +OP4 E01E55 0 +OP4 E01E56 0 +OP4 E01E57 0 +OP4 E01E58 0 +OP4 E01E59 0 +OP4 E01E5A 0 +OP4 E01E5B 0 +OP4 E01E5C 0 +OP4 E01E5D 0 +OP4 E01E5E 0 +OP4 E01E5F 0 +OP4 E01E60 0 +OP4 E01E61 0 +OP4 E01E62 0 +OP4 E01E63 0 +OP4 E01E64 0 +OP4 E01E65 0 +OP4 E01E66 0 +OP4 E01E67 0 +OP4 E01E68 0 +OP4 E01E69 0 +OP4 E01E6A 0 +OP4 E01E6B 0 +OP4 E01E6C 0 +OP4 E01E6D 0 +OP4 E01E6E 0 +OP4 E01E6F 0 +OP4 E01E70 0 +OP4 E01E71 0 +OP4 E01E72 0 +OP4 E01E73 0 +OP4 E01E74 0 +OP4 E01E75 0 +OP4 E01E76 0 +OP4 E01E77 0 +OP4 E01E78 0 +OP4 E01E79 0 +OP4 E01E7A 0 +OP4 E01E7B 0 +OP4 E01E7C 0 +OP4 E01E7D 0 +OP4 E01E7E 0 +OP4 E01E7F 0 +OP4 E01E80 0 +OP4 E01E81 0 +OP4 E01E82 0 +OP4 E01E83 0 +OP4 E01E84 0 +OP4 E01E85 0 +OP4 E01E86 0 +OP4 E01E87 0 +OP4 E01E88 0 +OP4 E01E89 0 +OP4 E01E8A 0 +OP4 E01E8B 0 +OP4 E01E8C 0 +OP4 E01E8D 0 +OP4 E01E8E 0 +OP4 E01E8F 0 +OP4 E01E90 0 +OP4 E01E91 0 +OP4 E01E92 0 +OP4 E01E93 0 +OP4 E01E94 0 +OP4 E01E95 0 +OP4 E01E96 0 +OP4 E01E97 0 +OP4 E01E98 0 +OP4 E01E99 0 +OP4 E01E9A 0 +OP4 E01E9B 0 +OP4 E01E9C 0 +OP4 E01E9D 0 +OP4 E01E9E 0 +OP4 E01E9F 0 +OP4 E01EA0 0 +OP4 E01EA1 0 +OP4 E01EA2 0 +OP4 E01EA3 0 +OP4 E01EA4 0 +OP4 E01EA5 0 +OP4 E01EA6 0 +OP4 E01EA7 0 +OP4 E01EA8 0 +OP4 E01EA9 0 +OP4 E01EAA 0 +OP4 E01EAB 0 +OP4 E01EAC 0 +OP4 E01EAD 0 +OP4 E01EAE 0 +OP4 E01EAF 0 +OP4 E01EB0 0 +OP4 E01EB1 0 +OP4 E01EB2 0 +OP4 E01EB3 0 +OP4 E01EB4 0 +OP4 E01EB5 0 +OP4 E01EB6 0 +OP4 E01EB7 0 +OP4 E01EB8 0 +OP4 E01EB9 0 +OP4 E01EBA 0 +OP4 E01EBB 0 +OP4 E01EBC 0 +OP4 E01EBD 0 +OP4 E01EBE 0 +OP4 E01EBF 0 +OP4 E01EC0 0 +OP4 E01EC1 0 +OP4 E01EC2 0 +OP4 E01EC3 0 +OP4 E01EC4 0 +OP4 E01EC5 0 +OP4 E01EC6 0 +OP4 E01EC7 0 +OP4 E01EC8 0 +OP4 E01EC9 0 +OP4 E01ECA 0 +OP4 E01ECB 0 +OP4 E01ECC 0 +OP4 E01ECD 0 +OP4 E01ECE 0 +OP4 E01ECF 0 +OP4 E01ED0 0 +OP4 E01ED1 0 +OP4 E01ED2 0 +OP4 E01ED3 0 +OP4 E01ED4 0 +OP4 E01ED5 0 +OP4 E01ED6 0 +OP4 E01ED7 0 +OP4 E01ED8 0 +OP4 E01ED9 0 +OP4 E01EDA 0 +OP4 E01EDB 0 +OP4 E01EDC 0 +OP4 E01EDD 0 +OP4 E01EDE 0 +OP4 E01EDF 0 +OP4 E01EE0 0 +OP4 E01EE1 0 +OP4 E01EE2 0 +OP4 E01EE3 0 +OP4 E01EE4 0 +OP4 E01EE5 0 +OP4 E01EE6 0 +OP4 E01EE7 0 +OP4 E01EE8 0 +OP4 E01EE9 0 +OP4 E01EEA 0 +OP4 E01EEB 0 +OP4 E01EEC 0 +OP4 E01EED 0 +OP4 E01EEE 0 +OP4 E01EEF 0 +OP4 E01EF0 0 +OP4 E01EF1 0 +OP4 E01EF2 0 +OP4 E01EF3 0 +OP4 E01EF4 0 +OP4 E01EF5 0 +OP4 E01EF6 0 +OP4 E01EF7 0 +OP4 E01EF8 0 +OP4 E01EF9 0 +OP4 E01EFA 0 +OP4 E01EFB 0 +OP4 E01EFC 0 +OP4 E01EFD 0 +OP4 E01EFE 0 +OP4 E01EFF 0 +OP4 E01F00 0 +OP4 E01F01 0 +OP4 E01F02 0 +OP4 E01F03 0 +OP4 E01F04 0 +OP4 E01F05 0 +OP4 E01F06 0 +OP4 E01F07 0 +OP4 E01F08 0 +OP4 E01F09 0 +OP4 E01F0A 0 +OP4 E01F0B 0 +OP4 E01F0C 0 +OP4 E01F0D 0 +OP4 E01F0E 0 +OP4 E01F0F 0 +OP4 E01F10 0 +OP4 E01F11 0 +OP4 E01F12 0 +OP4 E01F13 0 +OP4 E01F14 0 +OP4 E01F15 0 +OP4 E01F16 0 +OP4 E01F17 0 +OP4 E01F18 0 +OP4 E01F19 0 +OP4 E01F1A 0 +OP4 E01F1B 0 +OP4 E01F1C 0 +OP4 E01F1D 0 +OP4 E01F1E 0 +OP4 E01F1F 0 +OP4 E01F20 0 +OP4 E01F21 0 +OP4 E01F22 0 +OP4 E01F23 0 +OP4 E01F24 0 +OP4 E01F25 0 +OP4 E01F26 0 +OP4 E01F27 0 +OP4 E01F28 0 +OP4 E01F29 0 +OP4 E01F2A 0 +OP4 E01F2B 0 +OP4 E01F2C 0 +OP4 E01F2D 0 +OP4 E01F2E 0 +OP4 E01F2F 0 +OP4 E01F30 0 +OP4 E01F31 0 +OP4 E01F32 0 +OP4 E01F33 0 +OP4 E01F34 0 +OP4 E01F35 0 +OP4 E01F36 0 +OP4 E01F37 0 +OP4 E01F38 0 +OP4 E01F39 0 +OP4 E01F3A 0 +OP4 E01F3B 0 +OP4 E01F3C 0 +OP4 E01F3D 0 +OP4 E01F3E 0 +OP4 E01F3F 0 +OP4 E01F40 0 +OP4 E01F41 0 +OP4 E01F42 0 +OP4 E01F43 0 +OP4 E01F44 0 +OP4 E01F45 0 +OP4 E01F46 0 +OP4 E01F47 0 +OP4 E01F48 0 +OP4 E01F49 0 +OP4 E01F4A 0 +OP4 E01F4B 0 +OP4 E01F4C 0 +OP4 E01F4D 0 +OP4 E01F4E 0 +OP4 E01F4F 0 +OP4 E01F50 0 +OP4 E01F51 0 +OP4 E01F52 0 +OP4 E01F53 0 +OP4 E01F54 0 +OP4 E01F55 0 +OP4 E01F56 0 +OP4 E01F57 0 +OP4 E01F58 0 +OP4 E01F59 0 +OP4 E01F5A 0 +OP4 E01F5B 0 +OP4 E01F5C 0 +OP4 E01F5D 0 +OP4 E01F5E 0 +OP4 E01F5F 0 +OP4 E01F60 0 +OP4 E01F61 0 +OP4 E01F62 0 +OP4 E01F63 0 +OP4 E01F64 0 +OP4 E01F65 0 +OP4 E01F66 0 +OP4 E01F67 0 +OP4 E01F68 0 +OP4 E01F69 0 +OP4 E01F6A 0 +OP4 E01F6B 0 +OP4 E01F6C 0 +OP4 E01F6D 0 +OP4 E01F6E 0 +OP4 E01F6F 0 +OP4 E01F70 0 +OP4 E01F71 0 +OP4 E01F72 0 +OP4 E01F73 0 +OP4 E01F74 0 +OP4 E01F75 0 +OP4 E01F76 0 +OP4 E01F77 0 +OP4 E01F78 0 +OP4 E01F79 0 +OP4 E01F7A 0 +OP4 E01F7B 0 +OP4 E01F7C 0 +OP4 E01F7D 0 +OP4 E01F7E 0 +OP4 E01F7F 0 +OP4 E01F80 0 +OP4 E01F81 0 +OP4 E01F82 0 +OP4 E01F83 0 +OP4 E01F84 0 +OP4 E01F85 0 +OP4 E01F86 0 +OP4 E01F87 0 +OP4 E01F88 0 +OP4 E01F89 0 +OP4 E01F8A 0 +OP4 E01F8B 0 +OP4 E01F8C 0 +OP4 E01F8D 0 +OP4 E01F8E 0 +OP4 E01F8F 0 +OP4 E01F90 0 +OP4 E01F91 0 +OP4 E01F92 0 +OP4 E01F93 0 +OP4 E01F94 0 +OP4 E01F95 0 +OP4 E01F96 0 +OP4 E01F97 0 +OP4 E01F98 0 +OP4 E01F99 0 +OP4 E01F9A 0 +OP4 E01F9B 0 +OP4 E01F9C 0 +OP4 E01F9D 0 +OP4 E01F9E 0 +OP4 E01F9F 0 +OP4 E01FA0 0 +OP4 E01FA1 0 +OP4 E01FA2 0 +OP4 E01FA3 0 +OP4 E01FA4 0 +OP4 E01FA5 0 +OP4 E01FA6 0 +OP4 E01FA7 0 +OP4 E01FA8 0 +OP4 E01FA9 0 +OP4 E01FAA 0 +OP4 E01FAB 0 +OP4 E01FAC 0 +OP4 E01FAD 0 +OP4 E01FAE 0 +OP4 E01FAF 0 +OP4 E01FB0 0 +OP4 E01FB1 0 +OP4 E01FB2 0 +OP4 E01FB3 0 +OP4 E01FB4 0 +OP4 E01FB5 0 +OP4 E01FB6 0 +OP4 E01FB7 0 +OP4 E01FB8 0 +OP4 E01FB9 0 +OP4 E01FBA 0 +OP4 E01FBB 0 +OP4 E01FBC 0 +OP4 E01FBD 0 +OP4 E01FBE 0 +OP4 E01FBF 0 +OP4 E01FC0 0 +OP4 E01FC1 0 +OP4 E01FC2 0 +OP4 E01FC3 0 +OP4 E01FC4 0 +OP4 E01FC5 0 +OP4 E01FC6 0 +OP4 E01FC7 0 +OP4 E01FC8 0 +OP4 E01FC9 0 +OP4 E01FCA 0 +OP4 E01FCB 0 +OP4 E01FCC 0 +OP4 E01FCD 0 +OP4 E01FCE 0 +OP4 E01FCF 0 +OP4 E01FD0 0 +OP4 E01FD1 0 +OP4 E01FD2 0 +OP4 E01FD3 0 +OP4 E01FD4 0 +OP4 E01FD5 0 +OP4 E01FD6 0 +OP4 E01FD7 0 +OP4 E01FD8 0 +OP4 E01FD9 0 +OP4 E01FDA 0 +OP4 E01FDB 0 +OP4 E01FDC 0 +OP4 E01FDD 0 +OP4 E01FDE 0 +OP4 E01FDF 0 +OP4 E01FE0 0 +OP4 E01FE1 0 +OP4 E01FE2 0 +OP4 E01FE3 0 +OP4 E01FE4 0 +OP4 E01FE5 0 +OP4 E01FE6 0 +OP4 E01FE7 0 +OP4 E01FE8 0 +OP4 E01FE9 0 +OP4 E01FEA 0 +OP4 E01FEB 0 +OP4 E01FEC 0 +OP4 E01FED 0 +OP4 E01FEE 0 +OP4 E01FEF 0 +OP4 E01FF0 0 +OP4 E01FF1 0 +OP4 E01FF2 0 +OP4 E01FF3 0 +OP4 E01FF4 0 +OP4 E01FF5 0 +OP4 E01FF6 0 +OP4 E01FF7 0 +OP4 E01FF8 0 +OP4 E01FF9 0 +OP4 E01FFA 0 +OP4 E01FFB 0 +OP4 E01FFC 0 +OP4 E01FFD 0 +OP4 E01FFE 0 +OP4 E01FFF 0 +OP4 E02000 0 +OP4 E02001 0 +OP4 E02002 0 +OP4 E02003 0 +OP4 E02004 0 +OP4 E02005 0 +OP4 E02006 0 +OP4 E02007 0 +OP4 E02008 0 +OP4 E02009 0 +OP4 E0200A 0 +OP4 E0200B 0 +OP4 E0200C 0 +OP4 E0200D 0 +OP4 E0200E 0 +OP4 E0200F 0 +OP4 E02010 0 +OP4 E02011 0 +OP4 E02012 0 +OP4 E02013 0 +OP4 E02014 0 +OP4 E02015 0 +OP4 E02016 0 +OP4 E02017 0 +OP4 E02018 0 +OP4 E02019 0 +OP4 E0201A 0 +OP4 E0201B 0 +OP4 E0201C 0 +OP4 E0201D 0 +OP4 E0201E 0 +OP4 E0201F 0 +OP4 E02020 0 +OP4 E02021 0 +OP4 E02022 0 +OP4 E02023 0 +OP4 E02024 0 +OP4 E02025 0 +OP4 E02026 0 +OP4 E02027 0 +OP4 E02028 0 +OP4 E02029 0 +OP4 E0202A 0 +OP4 E0202B 0 +OP4 E0202C 0 +OP4 E0202D 0 +OP4 E0202E 0 +OP4 E0202F 0 +OP4 E02030 0 +OP4 E02031 0 +OP4 E02032 0 +OP4 E02033 0 +OP4 E02034 0 +OP4 E02035 0 +OP4 E02036 0 +OP4 E02037 0 +OP4 E02038 0 +OP4 E02039 0 +OP4 E0203A 0 +OP4 E0203B 0 +OP4 E0203C 0 +OP4 E0203D 0 +OP4 E0203E 0 +OP4 E0203F 0 +OP4 E02040 0 +OP4 E02041 0 +OP4 E02042 0 +OP4 E02043 0 +OP4 E02044 0 +OP4 E02045 0 +OP4 E02046 0 +OP4 E02047 0 +OP4 E02048 0 +OP4 E02049 0 +OP4 E0204A 0 +OP4 E0204B 0 +OP4 E0204C 0 +OP4 E0204D 0 +OP4 E0204E 0 +OP4 E0204F 0 +OP4 E02050 0 +OP4 E02051 0 +OP4 E02052 0 +OP4 E02053 0 +OP4 E02054 0 +OP4 E02055 0 +OP4 E02056 0 +OP4 E02057 0 +OP4 E02058 0 +OP4 E02059 0 +OP4 E0205A 0 +OP4 E0205B 0 +OP4 E0205C 0 +OP4 E0205D 0 +OP4 E0205E 0 +OP4 E0205F 0 +OP4 E02060 0 +OP4 E02061 0 +OP4 E02062 0 +OP4 E02063 0 +OP4 E02064 0 +OP4 E02065 0 +OP4 E02066 0 +OP4 E02067 0 +OP4 E02068 0 +OP4 E02069 0 +OP4 E0206A 0 +OP4 E0206B 0 +OP4 E0206C 0 +OP4 E0206D 0 +OP4 E0206E 0 +OP4 E0206F 0 +OP4 E02070 0 +OP4 E02071 0 +OP4 E02072 0 +OP4 E02073 0 +OP4 E02074 0 +OP4 E02075 0 +OP4 E02076 0 +OP4 E02077 0 +OP4 E02078 0 +OP4 E02079 0 +OP4 E0207A 0 +OP4 E0207B 0 +OP4 E0207C 0 +OP4 E0207D 0 +OP4 E0207E 0 +OP4 E0207F 0 +OP4 E02080 0 +OP4 E02081 0 +OP4 E02082 0 +OP4 E02083 0 +OP4 E02084 0 +OP4 E02085 0 +OP4 E02086 0 +OP4 E02087 0 +OP4 E02088 0 +OP4 E02089 0 +OP4 E0208A 0 +OP4 E0208B 0 +OP4 E0208C 0 +OP4 E0208D 0 +OP4 E0208E 0 +OP4 E0208F 0 +OP4 E02090 0 +OP4 E02091 0 +OP4 E02092 0 +OP4 E02093 0 +OP4 E02094 0 +OP4 E02095 0 +OP4 E02096 0 +OP4 E02097 0 +OP4 E02098 0 +OP4 E02099 0 +OP4 E0209A 0 +OP4 E0209B 0 +OP4 E0209C 0 +OP4 E0209D 0 +OP4 E0209E 0 +OP4 E0209F 0 +OP4 E020A0 0 +OP4 E020A1 0 +OP4 E020A2 0 +OP4 E020A3 0 +OP4 E020A4 0 +OP4 E020A5 0 +OP4 E020A6 0 +OP4 E020A7 0 +OP4 E020A8 0 +OP4 E020A9 0 +OP4 E020AA 0 +OP4 E020AB 0 +OP4 E020AC 0 +OP4 E020AD 0 +OP4 E020AE 0 +OP4 E020AF 0 +OP4 E020B0 0 +OP4 E020B1 0 +OP4 E020B2 0 +OP4 E020B3 0 +OP4 E020B4 0 +OP4 E020B5 0 +OP4 E020B6 0 +OP4 E020B7 0 +OP4 E020B8 0 +OP4 E020B9 0 +OP4 E020BA 0 +OP4 E020BB 0 +OP4 E020BC 0 +OP4 E020BD 0 +OP4 E020BE 0 +OP4 E020BF 0 +OP4 E020C0 0 +OP4 E020C1 0 +OP4 E020C2 0 +OP4 E020C3 0 +OP4 E020C4 0 +OP4 E020C5 0 +OP4 E020C6 0 +OP4 E020C7 0 +OP4 E020C8 0 +OP4 E020C9 0 +OP4 E020CA 0 +OP4 E020CB 0 +OP4 E020CC 0 +OP4 E020CD 0 +OP4 E020CE 0 +OP4 E020CF 0 +OP4 E020D0 0 +OP4 E020D1 0 +OP4 E020D2 0 +OP4 E020D3 0 +OP4 E020D4 0 +OP4 E020D5 0 +OP4 E020D6 0 +OP4 E020D7 0 +OP4 E020D8 0 +OP4 E020D9 0 +OP4 E020DA 0 +OP4 E020DB 0 +OP4 E020DC 0 +OP4 E020DD 0 +OP4 E020DE 0 +OP4 E020DF 0 +OP4 E020E0 0 +OP4 E020E1 0 +OP4 E020E2 0 +OP4 E020E3 0 +OP4 E020E4 0 +OP4 E020E5 0 +OP4 E020E6 0 +OP4 E020E7 0 +OP4 E020E8 0 +OP4 E020E9 0 +OP4 E020EA 0 +OP4 E020EB 0 +OP4 E020EC 0 +OP4 E020ED 0 +OP4 E020EE 0 +OP4 E020EF 0 +OP4 E020F0 0 +OP4 E020F1 0 +OP4 E020F2 0 +OP4 E020F3 0 +OP4 E020F4 0 +OP4 E020F5 0 +OP4 E020F6 0 +OP4 E020F7 0 +OP4 E020F8 0 +OP4 E020F9 0 +OP4 E020FA 0 +OP4 E020FB 0 +OP4 E020FC 0 +OP4 E020FD 0 +OP4 E020FE 0 +OP4 E020FF 0 +OP4 E02100 0 +OP4 E02101 0 +OP4 E02102 0 +OP4 E02103 0 +OP4 E02104 0 +OP4 E02105 0 +OP4 E02106 0 +OP4 E02107 0 +OP4 E02108 0 +OP4 E02109 0 +OP4 E0210A 0 +OP4 E0210B 0 +OP4 E0210C 0 +OP4 E0210D 0 +OP4 E0210E 0 +OP4 E0210F 0 +OP4 E02110 0 +OP4 E02111 0 +OP4 E02112 0 +OP4 E02113 0 +OP4 E02114 0 +OP4 E02115 0 +OP4 E02116 0 +OP4 E02117 0 +OP4 E02118 0 +OP4 E02119 0 +OP4 E0211A 0 +OP4 E0211B 0 +OP4 E0211C 0 +OP4 E0211D 0 +OP4 E0211E 0 +OP4 E0211F 0 +OP4 E02120 0 +OP4 E02121 0 +OP4 E02122 0 +OP4 E02123 0 +OP4 E02124 0 +OP4 E02125 0 +OP4 E02126 0 +OP4 E02127 0 +OP4 E02128 0 +OP4 E02129 0 +OP4 E0212A 0 +OP4 E0212B 0 +OP4 E0212C 0 +OP4 E0212D 0 +OP4 E0212E 0 +OP4 E0212F 0 +OP4 E02130 0 +OP4 E02131 0 +OP4 E02132 0 +OP4 E02133 0 +OP4 E02134 0 +OP4 E02135 0 +OP4 E02136 0 +OP4 E02137 0 +OP4 E02138 0 +OP4 E02139 0 +OP4 E0213A 0 +OP4 E0213B 0 +OP4 E0213C 0 +OP4 E0213D 0 +OP4 E0213E 0 +OP4 E0213F 0 +OP4 E02140 0 +OP4 E02141 0 +OP4 E02142 0 +OP4 E02143 0 +OP4 E02144 0 +OP4 E02145 0 +OP4 E02146 0 +OP4 E02147 0 +OP4 E02148 0 +OP4 E02149 0 +OP4 E0214A 0 +OP4 E0214B 0 +OP4 E0214C 0 +OP4 E0214D 0 +OP4 E0214E 0 +OP4 E0214F 0 +OP4 E02150 0 +OP4 E02151 0 +OP4 E02152 0 +OP4 E02153 0 +OP4 E02154 0 +OP4 E02155 0 +OP4 E02156 0 +OP4 E02157 0 +OP4 E02158 0 +OP4 E02159 0 +OP4 E0215A 0 +OP4 E0215B 0 +OP4 E0215C 0 +OP4 E0215D 0 +OP4 E0215E 0 +OP4 E0215F 0 +OP4 E02160 0 +OP4 E02161 0 +OP4 E02162 0 +OP4 E02163 0 +OP4 E02164 0 +OP4 E02165 0 +OP4 E02166 0 +OP4 E02167 0 +OP4 E02168 0 +OP4 E02169 0 +OP4 E0216A 0 +OP4 E0216B 0 +OP4 E0216C 0 +OP4 E0216D 0 +OP4 E0216E 0 +OP4 E0216F 0 +OP4 E02170 0 +OP4 E02171 0 +OP4 E02172 0 +OP4 E02173 0 +OP4 E02174 0 +OP4 E02175 0 +OP4 E02176 0 +OP4 E02177 0 +OP4 E02178 0 +OP4 E02179 0 +OP4 E0217A 0 +OP4 E0217B 0 +OP4 E0217C 0 +OP4 E0217D 0 +OP4 E0217E 0 +OP4 E0217F 0 +OP4 E02180 0 +OP4 E02181 0 +OP4 E02182 0 +OP4 E02183 0 +OP4 E02184 0 +OP4 E02185 0 +OP4 E02186 0 +OP4 E02187 0 +OP4 E02188 0 +OP4 E02189 0 +OP4 E0218A 0 +OP4 E0218B 0 +OP4 E0218C 0 +OP4 E0218D 0 +OP4 E0218E 0 +OP4 E0218F 0 +OP4 E02190 0 +OP4 E02191 0 +OP4 E02192 0 +OP4 E02193 0 +OP4 E02194 0 +OP4 E02195 0 +OP4 E02196 0 +OP4 E02197 0 +OP4 E02198 0 +OP4 E02199 0 +OP4 E0219A 0 +OP4 E0219B 0 +OP4 E0219C 0 +OP4 E0219D 0 +OP4 E0219E 0 +OP4 E0219F 0 +OP4 E021A0 0 +OP4 E021A1 0 +OP4 E021A2 0 +OP4 E021A3 0 +OP4 E021A4 0 +OP4 E021A5 0 +OP4 E021A6 0 +OP4 E021A7 0 +OP4 E021A8 0 +OP4 E021A9 0 +OP4 E021AA 0 +OP4 E021AB 0 +OP4 E021AC 0 +OP4 E021AD 0 +OP4 E021AE 0 +OP4 E021AF 0 +OP4 E021B0 0 +OP4 E021B1 0 +OP4 E021B2 0 +OP4 E021B3 0 +OP4 E021B4 0 +OP4 E021B5 0 +OP4 E021B6 0 +OP4 E021B7 0 +OP4 E021B8 0 +OP4 E021B9 0 +OP4 E021BA 0 +OP4 E021BB 0 +OP4 E021BC 0 +OP4 E021BD 0 +OP4 E021BE 0 +OP4 E021BF 0 +OP4 E021C0 0 +OP4 E021C1 0 +OP4 E021C2 0 +OP4 E021C3 0 +OP4 E021C4 0 +OP4 E021C5 0 +OP4 E021C6 0 +OP4 E021C7 0 +OP4 E021C8 0 +OP4 E021C9 0 +OP4 E021CA 0 +OP4 E021CB 0 +OP4 E021CC 0 +OP4 E021CD 0 +OP4 E021CE 0 +OP4 E021CF 0 +OP4 E021D0 0 +OP4 E021D1 0 +OP4 E021D2 0 +OP4 E021D3 0 +OP4 E021D4 0 +OP4 E021D5 0 +OP4 E021D6 0 +OP4 E021D7 0 +OP4 E021D8 0 +OP4 E021D9 0 +OP4 E021DA 0 +OP4 E021DB 0 +OP4 E021DC 0 +OP4 E021DD 0 +OP4 E021DE 0 +OP4 E021DF 0 +OP4 E021E0 0 +OP4 E021E1 0 +OP4 E021E2 0 +OP4 E021E3 0 +OP4 E021E4 0 +OP4 E021E5 0 +OP4 E021E6 0 +OP4 E021E7 0 +OP4 E021E8 0 +OP4 E021E9 0 +OP4 E021EA 0 +OP4 E021EB 0 +OP4 E021EC 0 +OP4 E021ED 0 +OP4 E021EE 0 +OP4 E021EF 0 +OP4 E021F0 0 +OP4 E021F1 0 +OP4 E021F2 0 +OP4 E021F3 0 +OP4 E021F4 0 +OP4 E021F5 0 +OP4 E021F6 0 +OP4 E021F7 0 +OP4 E021F8 0 +OP4 E021F9 0 +OP4 E021FA 0 +OP4 E021FB 0 +OP4 E021FC 0 +OP4 E021FD 0 +OP4 E021FE 0 +OP4 E021FF 0 +OP4 E02200 0 +OP4 E02201 0 +OP4 E02202 0 +OP4 E02203 0 +OP4 E02204 0 +OP4 E02205 0 +OP4 E02206 0 +OP4 E02207 0 +OP4 E02208 0 +OP4 E02209 0 +OP4 E0220A 0 +OP4 E0220B 0 +OP4 E0220C 0 +OP4 E0220D 0 +OP4 E0220E 0 +OP4 E0220F 0 +OP4 E02210 0 +OP4 E02211 0 +OP4 E02212 0 +OP4 E02213 0 +OP4 E02214 0 +OP4 E02215 0 +OP4 E02216 0 +OP4 E02217 0 +OP4 E02218 0 +OP4 E02219 0 +OP4 E0221A 0 +OP4 E0221B 0 +OP4 E0221C 0 +OP4 E0221D 0 +OP4 E0221E 0 +OP4 E0221F 0 +OP4 E02220 0 +OP4 E02221 0 +OP4 E02222 0 +OP4 E02223 0 +OP4 E02224 0 +OP4 E02225 0 +OP4 E02226 0 +OP4 E02227 0 +OP4 E02228 0 +OP4 E02229 0 +OP4 E0222A 0 +OP4 E0222B 0 +OP4 E0222C 0 +OP4 E0222D 0 +OP4 E0222E 0 +OP4 E0222F 0 +OP4 E02230 0 +OP4 E02231 0 +OP4 E02232 0 +OP4 E02233 0 +OP4 E02234 0 +OP4 E02235 0 +OP4 E02236 0 +OP4 E02237 0 +OP4 E02238 0 +OP4 E02239 0 +OP4 E0223A 0 +OP4 E0223B 0 +OP4 E0223C 0 +OP4 E0223D 0 +OP4 E0223E 0 +OP4 E0223F 0 +OP4 E02240 0 +OP4 E02241 0 +OP4 E02242 0 +OP4 E02243 0 +OP4 E02244 0 +OP4 E02245 0 +OP4 E02246 0 +OP4 E02247 0 +OP4 E02248 0 +OP4 E02249 0 +OP4 E0224A 0 +OP4 E0224B 0 +OP4 E0224C 0 +OP4 E0224D 0 +OP4 E0224E 0 +OP4 E0224F 0 +OP4 E02250 0 +OP4 E02251 0 +OP4 E02252 0 +OP4 E02253 0 +OP4 E02254 0 +OP4 E02255 0 +OP4 E02256 0 +OP4 E02257 0 +OP4 E02258 0 +OP4 E02259 0 +OP4 E0225A 0 +OP4 E0225B 0 +OP4 E0225C 0 +OP4 E0225D 0 +OP4 E0225E 0 +OP4 E0225F 0 +OP4 E02260 0 +OP4 E02261 0 +OP4 E02262 0 +OP4 E02263 0 +OP4 E02264 0 +OP4 E02265 0 +OP4 E02266 0 +OP4 E02267 0 +OP4 E02268 0 +OP4 E02269 0 +OP4 E0226A 0 +OP4 E0226B 0 +OP4 E0226C 0 +OP4 E0226D 0 +OP4 E0226E 0 +OP4 E0226F 0 +OP4 E02270 0 +OP4 E02271 0 +OP4 E02272 0 +OP4 E02273 0 +OP4 E02274 0 +OP4 E02275 0 +OP4 E02276 0 +OP4 E02277 0 +OP4 E02278 0 +OP4 E02279 0 +OP4 E0227A 0 +OP4 E0227B 0 +OP4 E0227C 0 +OP4 E0227D 0 +OP4 E0227E 0 +OP4 E0227F 0 +OP4 E02280 0 +OP4 E02281 0 +OP4 E02282 0 +OP4 E02283 0 +OP4 E02284 0 +OP4 E02285 0 +OP4 E02286 0 +OP4 E02287 0 +OP4 E02288 0 +OP4 E02289 0 +OP4 E0228A 0 +OP4 E0228B 0 +OP4 E0228C 0 +OP4 E0228D 0 +OP4 E0228E 0 +OP4 E0228F 0 +OP4 E02290 0 +OP4 E02291 0 +OP4 E02292 0 +OP4 E02293 0 +OP4 E02294 0 +OP4 E02295 0 +OP4 E02296 0 +OP4 E02297 0 +OP4 E02298 0 +OP4 E02299 0 +OP4 E0229A 0 +OP4 E0229B 0 +OP4 E0229C 0 +OP4 E0229D 0 +OP4 E0229E 0 +OP4 E0229F 0 +OP4 E022A0 0 +OP4 E022A1 0 +OP4 E022A2 0 +OP4 E022A3 0 +OP4 E022A4 0 +OP4 E022A5 0 +OP4 E022A6 0 +OP4 E022A7 0 +OP4 E022A8 0 +OP4 E022A9 0 +OP4 E022AA 0 +OP4 E022AB 0 +OP4 E022AC 0 +OP4 E022AD 0 +OP4 E022AE 0 +OP4 E022AF 0 +OP4 E022B0 0 +OP4 E022B1 0 +OP4 E022B2 0 +OP4 E022B3 0 +OP4 E022B4 0 +OP4 E022B5 0 +OP4 E022B6 0 +OP4 E022B7 0 +OP4 E022B8 0 +OP4 E022B9 0 +OP4 E022BA 0 +OP4 E022BB 0 +OP4 E022BC 0 +OP4 E022BD 0 +OP4 E022BE 0 +OP4 E022BF 0 +OP4 E022C0 0 +OP4 E022C1 0 +OP4 E022C2 0 +OP4 E022C3 0 +OP4 E022C4 0 +OP4 E022C5 0 +OP4 E022C6 0 +OP4 E022C7 0 +OP4 E022C8 0 +OP4 E022C9 0 +OP4 E022CA 0 +OP4 E022CB 0 +OP4 E022CC 0 +OP4 E022CD 0 +OP4 E022CE 0 +OP4 E022CF 0 +OP4 E022D0 0 +OP4 E022D1 0 +OP4 E022D2 0 +OP4 E022D3 0 +OP4 E022D4 0 +OP4 E022D5 0 +OP4 E022D6 0 +OP4 E022D7 0 +OP4 E022D8 0 +OP4 E022D9 0 +OP4 E022DA 0 +OP4 E022DB 0 +OP4 E022DC 0 +OP4 E022DD 0 +OP4 E022DE 0 +OP4 E022DF 0 +OP4 E022E0 0 +OP4 E022E1 0 +OP4 E022E2 0 +OP4 E022E3 0 +OP4 E022E4 0 +OP4 E022E5 0 +OP4 E022E6 0 +OP4 E022E7 0 +OP4 E022E8 0 +OP4 E022E9 0 +OP4 E022EA 0 +OP4 E022EB 0 +OP4 E022EC 0 +OP4 E022ED 0 +OP4 E022EE 0 +OP4 E022EF 0 +OP4 E022F0 0 +OP4 E022F1 0 +OP4 E022F2 0 +OP4 E022F3 0 +OP4 E022F4 0 +OP4 E022F5 0 +OP4 E022F6 0 +OP4 E022F7 0 +OP4 E022F8 0 +OP4 E022F9 0 +OP4 E022FA 0 +OP4 E022FB 0 +OP4 E022FC 0 +OP4 E022FD 0 +OP4 E022FE 0 +OP4 E022FF 0 +OP4 E02300 0 +OP4 E02301 0 +OP4 E02302 0 +OP4 E02303 0 +OP4 E02304 0 +OP4 E02305 0 +OP4 E02306 0 +OP4 E02307 0 +OP4 E02308 0 +OP4 E02309 0 +OP4 E0230A 0 +OP4 E0230B 0 +OP4 E0230C 0 +OP4 E0230D 0 +OP4 E0230E 0 +OP4 E0230F 0 +OP4 E02310 0 +OP4 E02311 0 +OP4 E02312 0 +OP4 E02313 0 +OP4 E02314 0 +OP4 E02315 0 +OP4 E02316 0 +OP4 E02317 0 +OP4 E02318 0 +OP4 E02319 0 +OP4 E0231A 0 +OP4 E0231B 0 +OP4 E0231C 0 +OP4 E0231D 0 +OP4 E0231E 0 +OP4 E0231F 0 +OP4 E02320 0 +OP4 E02321 0 +OP4 E02322 0 +OP4 E02323 0 +OP4 E02324 0 +OP4 E02325 0 +OP4 E02326 0 +OP4 E02327 0 +OP4 E02328 0 +OP4 E02329 0 +OP4 E0232A 0 +OP4 E0232B 0 +OP4 E0232C 0 +OP4 E0232D 0 +OP4 E0232E 0 +OP4 E0232F 0 +OP4 E02330 0 +OP4 E02331 0 +OP4 E02332 0 +OP4 E02333 0 +OP4 E02334 0 +OP4 E02335 0 +OP4 E02336 0 +OP4 E02337 0 +OP4 E02338 0 +OP4 E02339 0 +OP4 E0233A 0 +OP4 E0233B 0 +OP4 E0233C 0 +OP4 E0233D 0 +OP4 E0233E 0 +OP4 E0233F 0 +OP4 E02340 0 +OP4 E02341 0 +OP4 E02342 0 +OP4 E02343 0 +OP4 E02344 0 +OP4 E02345 0 +OP4 E02346 0 +OP4 E02347 0 +OP4 E02348 0 +OP4 E02349 0 +OP4 E0234A 0 +OP4 E0234B 0 +OP4 E0234C 0 +OP4 E0234D 0 +OP4 E0234E 0 +OP4 E0234F 0 +OP4 E02350 0 +OP4 E02351 0 +OP4 E02352 0 +OP4 E02353 0 +OP4 E02354 0 +OP4 E02355 0 +OP4 E02356 0 +OP4 E02357 0 +OP4 E02358 0 +OP4 E02359 0 +OP4 E0235A 0 +OP4 E0235B 0 +OP4 E0235C 0 +OP4 E0235D 0 +OP4 E0235E 0 +OP4 E0235F 0 +OP4 E02360 0 +OP4 E02361 0 +OP4 E02362 0 +OP4 E02363 0 +OP4 E02364 0 +OP4 E02365 0 +OP4 E02366 0 +OP4 E02367 0 +OP4 E02368 0 +OP4 E02369 0 +OP4 E0236A 0 +OP4 E0236B 0 +OP4 E0236C 0 +OP4 E0236D 0 +OP4 E0236E 0 +OP4 E0236F 0 +OP4 E02370 0 +OP4 E02371 0 +OP4 E02372 0 +OP4 E02373 0 +OP4 E02374 0 +OP4 E02375 0 +OP4 E02376 0 +OP4 E02377 0 +OP4 E02378 0 +OP4 E02379 0 +OP4 E0237A 0 +OP4 E0237B 0 +OP4 E0237C 0 +OP4 E0237D 0 +OP4 E0237E 0 +OP4 E0237F 0 +OP4 E02380 0 +OP4 E02381 0 +OP4 E02382 0 +OP4 E02383 0 +OP4 E02384 0 +OP4 E02385 0 +OP4 E02386 0 +OP4 E02387 0 +OP4 E02388 0 +OP4 E02389 0 +OP4 E0238A 0 +OP4 E0238B 0 +OP4 E0238C 0 +OP4 E0238D 0 +OP4 E0238E 0 +OP4 E0238F 0 +OP4 E02390 0 +OP4 E02391 0 +OP4 E02392 0 +OP4 E02393 0 +OP4 E02394 0 +OP4 E02395 0 +OP4 E02396 0 +OP4 E02397 0 +OP4 E02398 0 +OP4 E02399 0 +OP4 E0239A 0 +OP4 E0239B 0 +OP4 E0239C 0 +OP4 E0239D 0 +OP4 E0239E 0 +OP4 E0239F 0 +OP4 E023A0 0 +OP4 E023A1 0 +OP4 E023A2 0 +OP4 E023A3 0 +OP4 E023A4 0 +OP4 E023A5 0 +OP4 E023A6 0 +OP4 E023A7 0 +OP4 E023A8 0 +OP4 E023A9 0 +OP4 E023AA 0 +OP4 E023AB 0 +OP4 E023AC 0 +OP4 E023AD 0 +OP4 E023AE 0 +OP4 E023AF 0 +OP4 E023B0 0 +OP4 E023B1 0 +OP4 E023B2 0 +OP4 E023B3 0 +OP4 E023B4 0 +OP4 E023B5 0 +OP4 E023B6 0 +OP4 E023B7 0 +OP4 E023B8 0 +OP4 E023B9 0 +OP4 E023BA 0 +OP4 E023BB 0 +OP4 E023BC 0 +OP4 E023BD 0 +OP4 E023BE 0 +OP4 E023BF 0 +OP4 E023C0 0 +OP4 E023C1 0 +OP4 E023C2 0 +OP4 E023C3 0 +OP4 E023C4 0 +OP4 E023C5 0 +OP4 E023C6 0 +OP4 E023C7 0 +OP4 E023C8 0 +OP4 E023C9 0 +OP4 E023CA 0 +OP4 E023CB 0 +OP4 E023CC 0 +OP4 E023CD 0 +OP4 E023CE 0 +OP4 E023CF 0 +OP4 E023D0 0 +OP4 E023D1 0 +OP4 E023D2 0 +OP4 E023D3 0 +OP4 E023D4 0 +OP4 E023D5 0 +OP4 E023D6 0 +OP4 E023D7 0 +OP4 E023D8 0 +OP4 E023D9 0 +OP4 E023DA 0 +OP4 E023DB 0 +OP4 E023DC 0 +OP4 E023DD 0 +OP4 E023DE 0 +OP4 E023DF 0 +OP4 E023E0 0 +OP4 E023E1 0 +OP4 E023E2 0 +OP4 E023E3 0 +OP4 E023E4 0 +OP4 E023E5 0 +OP4 E023E6 0 +OP4 E023E7 0 +OP4 E023E8 0 +OP4 E023E9 0 +OP4 E023EA 0 +OP4 E023EB 0 +OP4 E023EC 0 +OP4 E023ED 0 +OP4 E023EE 0 +OP4 E023EF 0 +OP4 E023F0 0 +OP4 E023F1 0 +OP4 E023F2 0 +OP4 E023F3 0 +OP4 E023F4 0 +OP4 E023F5 0 +OP4 E023F6 0 +OP4 E023F7 0 +OP4 E023F8 0 +OP4 E023F9 0 +OP4 E023FA 0 +OP4 E023FB 0 +OP4 E023FC 0 +OP4 E023FD 0 +OP4 E023FE 0 +OP4 E023FF 0 +OP4 E02400 0 +OP4 E02401 0 +OP4 E02402 0 +OP4 E02403 0 +OP4 E02404 0 +OP4 E02405 0 +OP4 E02406 0 +OP4 E02407 0 +OP4 E02408 0 +OP4 E02409 0 +OP4 E0240A 0 +OP4 E0240B 0 +OP4 E0240C 0 +OP4 E0240D 0 +OP4 E0240E 0 +OP4 E0240F 0 +OP4 E02410 0 +OP4 E02411 0 +OP4 E02412 0 +OP4 E02413 0 +OP4 E02414 0 +OP4 E02415 0 +OP4 E02416 0 +OP4 E02417 0 +OP4 E02418 0 +OP4 E02419 0 +OP4 E0241A 0 +OP4 E0241B 0 +OP4 E0241C 0 +OP4 E0241D 0 +OP4 E0241E 0 +OP4 E0241F 0 +OP4 E02420 0 +OP4 E02421 0 +OP4 E02422 0 +OP4 E02423 0 +OP4 E02424 0 +OP4 E02425 0 +OP4 E02426 0 +OP4 E02427 0 +OP4 E02428 0 +OP4 E02429 0 +OP4 E0242A 0 +OP4 E0242B 0 +OP4 E0242C 0 +OP4 E0242D 0 +OP4 E0242E 0 +OP4 E0242F 0 +OP4 E02430 0 +OP4 E02431 0 +OP4 E02432 0 +OP4 E02433 0 +OP4 E02434 0 +OP4 E02435 0 +OP4 E02436 0 +OP4 E02437 0 +OP4 E02438 0 +OP4 E02439 0 +OP4 E0243A 0 +OP4 E0243B 0 +OP4 E0243C 0 +OP4 E0243D 0 +OP4 E0243E 0 +OP4 E0243F 0 +OP4 E02440 0 +OP4 E02441 0 +OP4 E02442 0 +OP4 E02443 0 +OP4 E02444 0 +OP4 E02445 0 +OP4 E02446 0 +OP4 E02447 0 +OP4 E02448 0 +OP4 E02449 0 +OP4 E0244A 0 +OP4 E0244B 0 +OP4 E0244C 0 +OP4 E0244D 0 +OP4 E0244E 0 +OP4 E0244F 0 +OP4 E02450 0 +OP4 E02451 0 +OP4 E02452 0 +OP4 E02453 0 +OP4 E02454 0 +OP4 E02455 0 +OP4 E02456 0 +OP4 E02457 0 +OP4 E02458 0 +OP4 E02459 0 +OP4 E0245A 0 +OP4 E0245B 0 +OP4 E0245C 0 +OP4 E0245D 0 +OP4 E0245E 0 +OP4 E0245F 0 +OP4 E02460 0 +OP4 E02461 0 +OP4 E02462 0 +OP4 E02463 0 +OP4 E02464 0 +OP4 E02465 0 +OP4 E02466 0 +OP4 E02467 0 +OP4 E02468 0 +OP4 E02469 0 +OP4 E0246A 0 +OP4 E0246B 0 +OP4 E0246C 0 +OP4 E0246D 0 +OP4 E0246E 0 +OP4 E0246F 0 +OP4 E02470 0 +OP4 E02471 0 +OP4 E02472 0 +OP4 E02473 0 +OP4 E02474 0 +OP4 E02475 0 +OP4 E02476 0 +OP4 E02477 0 +OP4 E02478 0 +OP4 E02479 0 +OP4 E0247A 0 +OP4 E0247B 0 +OP4 E0247C 0 +OP4 E0247D 0 +OP4 E0247E 0 +OP4 E0247F 0 +OP4 E02480 0 +OP4 E02481 0 +OP4 E02482 0 +OP4 E02483 0 +OP4 E02484 0 +OP4 E02485 0 +OP4 E02486 0 +OP4 E02487 0 +OP4 E02488 0 +OP4 E02489 0 +OP4 E0248A 0 +OP4 E0248B 0 +OP4 E0248C 0 +OP4 E0248D 0 +OP4 E0248E 0 +OP4 E0248F 0 +OP4 E02490 0 +OP4 E02491 0 +OP4 E02492 0 +OP4 E02493 0 +OP4 E02494 0 +OP4 E02495 0 +OP4 E02496 0 +OP4 E02497 0 +OP4 E02498 0 +OP4 E02499 0 +OP4 E0249A 0 +OP4 E0249B 0 +OP4 E0249C 0 +OP4 E0249D 0 +OP4 E0249E 0 +OP4 E0249F 0 +OP4 E024A0 0 +OP4 E024A1 0 +OP4 E024A2 0 +OP4 E024A3 0 +OP4 E024A4 0 +OP4 E024A5 0 +OP4 E024A6 0 +OP4 E024A7 0 +OP4 E024A8 0 +OP4 E024A9 0 +OP4 E024AA 0 +OP4 E024AB 0 +OP4 E024AC 0 +OP4 E024AD 0 +OP4 E024AE 0 +OP4 E024AF 0 +OP4 E024B0 0 +OP4 E024B1 0 +OP4 E024B2 0 +OP4 E024B3 0 +OP4 E024B4 0 +OP4 E024B5 0 +OP4 E024B6 0 +OP4 E024B7 0 +OP4 E024B8 0 +OP4 E024B9 0 +OP4 E024BA 0 +OP4 E024BB 0 +OP4 E024BC 0 +OP4 E024BD 0 +OP4 E024BE 0 +OP4 E024BF 0 +OP4 E024C0 0 +OP4 E024C1 0 +OP4 E024C2 0 +OP4 E024C3 0 +OP4 E024C4 0 +OP4 E024C5 0 +OP4 E024C6 0 +OP4 E024C7 0 +OP4 E024C8 0 +OP4 E024C9 0 +OP4 E024CA 0 +OP4 E024CB 0 +OP4 E024CC 0 +OP4 E024CD 0 +OP4 E024CE 0 +OP4 E024CF 0 +OP4 E024D0 0 +OP4 E024D1 0 +OP4 E024D2 0 +OP4 E024D3 0 +OP4 E024D4 0 +OP4 E024D5 0 +OP4 E024D6 0 +OP4 E024D7 0 +OP4 E024D8 0 +OP4 E024D9 0 +OP4 E024DA 0 +OP4 E024DB 0 +OP4 E024DC 0 +OP4 E024DD 0 +OP4 E024DE 0 +OP4 E024DF 0 +OP4 E024E0 0 +OP4 E024E1 0 +OP4 E024E2 0 +OP4 E024E3 0 +OP4 E024E4 0 +OP4 E024E5 0 +OP4 E024E6 0 +OP4 E024E7 0 +OP4 E024E8 0 +OP4 E024E9 0 +OP4 E024EA 0 +OP4 E024EB 0 +OP4 E024EC 0 +OP4 E024ED 0 +OP4 E024EE 0 +OP4 E024EF 0 +OP4 E024F0 0 +OP4 E024F1 0 +OP4 E024F2 0 +OP4 E024F3 0 +OP4 E024F4 0 +OP4 E024F5 0 +OP4 E024F6 0 +OP4 E024F7 0 +OP4 E024F8 0 +OP4 E024F9 0 +OP4 E024FA 0 +OP4 E024FB 0 +OP4 E024FC 0 +OP4 E024FD 0 +OP4 E024FE 0 +OP4 E024FF 0 +OP4 E02500 0 +OP4 E02501 0 +OP4 E02502 0 +OP4 E02503 0 +OP4 E02504 0 +OP4 E02505 0 +OP4 E02506 0 +OP4 E02507 0 +OP4 E02508 0 +OP4 E02509 0 +OP4 E0250A 0 +OP4 E0250B 0 +OP4 E0250C 0 +OP4 E0250D 0 +OP4 E0250E 0 +OP4 E0250F 0 +OP4 E02510 0 +OP4 E02511 0 +OP4 E02512 0 +OP4 E02513 0 +OP4 E02514 0 +OP4 E02515 0 +OP4 E02516 0 +OP4 E02517 0 +OP4 E02518 0 +OP4 E02519 0 +OP4 E0251A 0 +OP4 E0251B 0 +OP4 E0251C 0 +OP4 E0251D 0 +OP4 E0251E 0 +OP4 E0251F 0 +OP4 E02520 0 +OP4 E02521 0 +OP4 E02522 0 +OP4 E02523 0 +OP4 E02524 0 +OP4 E02525 0 +OP4 E02526 0 +OP4 E02527 0 +OP4 E02528 0 +OP4 E02529 0 +OP4 E0252A 0 +OP4 E0252B 0 +OP4 E0252C 0 +OP4 E0252D 0 +OP4 E0252E 0 +OP4 E0252F 0 +OP4 E02530 0 +OP4 E02531 0 +OP4 E02532 0 +OP4 E02533 0 +OP4 E02534 0 +OP4 E02535 0 +OP4 E02536 0 +OP4 E02537 0 +OP4 E02538 0 +OP4 E02539 0 +OP4 E0253A 0 +OP4 E0253B 0 +OP4 E0253C 0 +OP4 E0253D 0 +OP4 E0253E 0 +OP4 E0253F 0 +OP4 E02540 0 +OP4 E02541 0 +OP4 E02542 0 +OP4 E02543 0 +OP4 E02544 0 +OP4 E02545 0 +OP4 E02546 0 +OP4 E02547 0 +OP4 E02548 0 +OP4 E02549 0 +OP4 E0254A 0 +OP4 E0254B 0 +OP4 E0254C 0 +OP4 E0254D 0 +OP4 E0254E 0 +OP4 E0254F 0 +OP4 E02550 0 +OP4 E02551 0 +OP4 E02552 0 +OP4 E02553 0 +OP4 E02554 0 +OP4 E02555 0 +OP4 E02556 0 +OP4 E02557 0 +OP4 E02558 0 +OP4 E02559 0 +OP4 E0255A 0 +OP4 E0255B 0 +OP4 E0255C 0 +OP4 E0255D 0 +OP4 E0255E 0 +OP4 E0255F 0 +OP4 E02560 0 +OP4 E02561 0 +OP4 E02562 0 +OP4 E02563 0 +OP4 E02564 0 +OP4 E02565 0 +OP4 E02566 0 +OP4 E02567 0 +OP4 E02568 0 +OP4 E02569 0 +OP4 E0256A 0 +OP4 E0256B 0 +OP4 E0256C 0 +OP4 E0256D 0 +OP4 E0256E 0 +OP4 E0256F 0 +OP4 E02570 0 +OP4 E02571 0 +OP4 E02572 0 +OP4 E02573 0 +OP4 E02574 0 +OP4 E02575 0 +OP4 E02576 0 +OP4 E02577 0 +OP4 E02578 0 +OP4 E02579 0 +OP4 E0257A 0 +OP4 E0257B 0 +OP4 E0257C 0 +OP4 E0257D 0 +OP4 E0257E 0 +OP4 E0257F 0 +OP4 E02580 0 +OP4 E02581 0 +OP4 E02582 0 +OP4 E02583 0 +OP4 E02584 0 +OP4 E02585 0 +OP4 E02586 0 +OP4 E02587 0 +OP4 E02588 0 +OP4 E02589 0 +OP4 E0258A 0 +OP4 E0258B 0 +OP4 E0258C 0 +OP4 E0258D 0 +OP4 E0258E 0 +OP4 E0258F 0 +OP4 E02590 0 +OP4 E02591 0 +OP4 E02592 0 +OP4 E02593 0 +OP4 E02594 0 +OP4 E02595 0 +OP4 E02596 0 +OP4 E02597 0 +OP4 E02598 0 +OP4 E02599 0 +OP4 E0259A 0 +OP4 E0259B 0 +OP4 E0259C 0 +OP4 E0259D 0 +OP4 E0259E 0 +OP4 E0259F 0 +OP4 E025A0 0 +OP4 E025A1 0 +OP4 E025A2 0 +OP4 E025A3 0 +OP4 E025A4 0 +OP4 E025A5 0 +OP4 E025A6 0 +OP4 E025A7 0 +OP4 E025A8 0 +OP4 E025A9 0 +OP4 E025AA 0 +OP4 E025AB 0 +OP4 E025AC 0 +OP4 E025AD 0 +OP4 E025AE 0 +OP4 E025AF 0 +OP4 E025B0 0 +OP4 E025B1 0 +OP4 E025B2 0 +OP4 E025B3 0 +OP4 E025B4 0 +OP4 E025B5 0 +OP4 E025B6 0 +OP4 E025B7 0 +OP4 E025B8 0 +OP4 E025B9 0 +OP4 E025BA 0 +OP4 E025BB 0 +OP4 E025BC 0 +OP4 E025BD 0 +OP4 E025BE 0 +OP4 E025BF 0 +OP4 E025C0 0 +OP4 E025C1 0 +OP4 E025C2 0 +OP4 E025C3 0 +OP4 E025C4 0 +OP4 E025C5 0 +OP4 E025C6 0 +OP4 E025C7 0 +OP4 E025C8 0 +OP4 E025C9 0 +OP4 E025CA 0 +OP4 E025CB 0 +OP4 E025CC 0 +OP4 E025CD 0 +OP4 E025CE 0 +OP4 E025CF 0 +OP4 E025D0 0 +OP4 E025D1 0 +OP4 E025D2 0 +OP4 E025D3 0 +OP4 E025D4 0 +OP4 E025D5 0 +OP4 E025D6 0 +OP4 E025D7 0 +OP4 E025D8 0 +OP4 E025D9 0 +OP4 E025DA 0 +OP4 E025DB 0 +OP4 E025DC 0 +OP4 E025DD 0 +OP4 E025DE 0 +OP4 E025DF 0 +OP4 E025E0 0 +OP4 E025E1 0 +OP4 E025E2 0 +OP4 E025E3 0 +OP4 E025E4 0 +OP4 E025E5 0 +OP4 E025E6 0 +OP4 E025E7 0 +OP4 E025E8 0 +OP4 E025E9 0 +OP4 E025EA 0 +OP4 E025EB 0 +OP4 E025EC 0 +OP4 E025ED 0 +OP4 E025EE 0 +OP4 E025EF 0 +OP4 E025F0 0 +OP4 E025F1 0 +OP4 E025F2 0 +OP4 E025F3 0 +OP4 E025F4 0 +OP4 E025F5 0 +OP4 E025F6 0 +OP4 E025F7 0 +OP4 E025F8 0 +OP4 E025F9 0 +OP4 E025FA 0 +OP4 E025FB 0 +OP4 E025FC 0 +OP4 E025FD 0 +OP4 E025FE 0 +OP4 E025FF 0 +OP4 E02600 0 +OP4 E02601 0 +OP4 E02602 0 +OP4 E02603 0 +OP4 E02604 0 +OP4 E02605 0 +OP4 E02606 0 +OP4 E02607 0 +OP4 E02608 0 +OP4 E02609 0 +OP4 E0260A 0 +OP4 E0260B 0 +OP4 E0260C 0 +OP4 E0260D 0 +OP4 E0260E 0 +OP4 E0260F 0 +OP4 E02610 0 +OP4 E02611 0 +OP4 E02612 0 +OP4 E02613 0 +OP4 E02614 0 +OP4 E02615 0 +OP4 E02616 0 +OP4 E02617 0 +OP4 E02618 0 +OP4 E02619 0 +OP4 E0261A 0 +OP4 E0261B 0 +OP4 E0261C 0 +OP4 E0261D 0 +OP4 E0261E 0 +OP4 E0261F 0 +OP4 E02620 0 +OP4 E02621 0 +OP4 E02622 0 +OP4 E02623 0 +OP4 E02624 0 +OP4 E02625 0 +OP4 E02626 0 +OP4 E02627 0 +OP4 E02628 0 +OP4 E02629 0 +OP4 E0262A 0 +OP4 E0262B 0 +OP4 E0262C 0 +OP4 E0262D 0 +OP4 E0262E 0 +OP4 E0262F 0 +OP4 E02630 0 +OP4 E02631 0 +OP4 E02632 0 +OP4 E02633 0 +OP4 E02634 0 +OP4 E02635 0 +OP4 E02636 0 +OP4 E02637 0 +OP4 E02638 0 +OP4 E02639 0 +OP4 E0263A 0 +OP4 E0263B 0 +OP4 E0263C 0 +OP4 E0263D 0 +OP4 E0263E 0 +OP4 E0263F 0 +OP4 E02640 0 +OP4 E02641 0 +OP4 E02642 0 +OP4 E02643 0 +OP4 E02644 0 +OP4 E02645 0 +OP4 E02646 0 +OP4 E02647 0 +OP4 E02648 0 +OP4 E02649 0 +OP4 E0264A 0 +OP4 E0264B 0 +OP4 E0264C 0 +OP4 E0264D 0 +OP4 E0264E 0 +OP4 E0264F 0 +OP4 E02650 0 +OP4 E02651 0 +OP4 E02652 0 +OP4 E02653 0 +OP4 E02654 0 +OP4 E02655 0 +OP4 E02656 0 +OP4 E02657 0 +OP4 E02658 0 +OP4 E02659 0 +OP4 E0265A 0 +OP4 E0265B 0 +OP4 E0265C 0 +OP4 E0265D 0 +OP4 E0265E 0 +OP4 E0265F 0 +OP4 E02660 0 +OP4 E02661 0 +OP4 E02662 0 +OP4 E02663 0 +OP4 E02664 0 +OP4 E02665 0 +OP4 E02666 0 +OP4 E02667 0 +OP4 E02668 0 +OP4 E02669 0 +OP4 E0266A 0 +OP4 E0266B 0 +OP4 E0266C 0 +OP4 E0266D 0 +OP4 E0266E 0 +OP4 E0266F 0 +OP4 E02670 0 +OP4 E02671 0 +OP4 E02672 0 +OP4 E02673 0 +OP4 E02674 0 +OP4 E02675 0 +OP4 E02676 0 +OP4 E02677 0 +OP4 E02678 0 +OP4 E02679 0 +OP4 E0267A 0 +OP4 E0267B 0 +OP4 E0267C 0 +OP4 E0267D 0 +OP4 E0267E 0 +OP4 E0267F 0 +OP4 E02680 0 +OP4 E02681 0 +OP4 E02682 0 +OP4 E02683 0 +OP4 E02684 0 +OP4 E02685 0 +OP4 E02686 0 +OP4 E02687 0 +OP4 E02688 0 +OP4 E02689 0 +OP4 E0268A 0 +OP4 E0268B 0 +OP4 E0268C 0 +OP4 E0268D 0 +OP4 E0268E 0 +OP4 E0268F 0 +OP4 E02690 0 +OP4 E02691 0 +OP4 E02692 0 +OP4 E02693 0 +OP4 E02694 0 +OP4 E02695 0 +OP4 E02696 0 +OP4 E02697 0 +OP4 E02698 0 +OP4 E02699 0 +OP4 E0269A 0 +OP4 E0269B 0 +OP4 E0269C 0 +OP4 E0269D 0 +OP4 E0269E 0 +OP4 E0269F 0 +OP4 E026A0 0 +OP4 E026A1 0 +OP4 E026A2 0 +OP4 E026A3 0 +OP4 E026A4 0 +OP4 E026A5 0 +OP4 E026A6 0 +OP4 E026A7 0 +OP4 E026A8 0 +OP4 E026A9 0 +OP4 E026AA 0 +OP4 E026AB 0 +OP4 E026AC 0 +OP4 E026AD 0 +OP4 E026AE 0 +OP4 E026AF 0 +OP4 E026B0 0 +OP4 E026B1 0 +OP4 E026B2 0 +OP4 E026B3 0 +OP4 E026B4 0 +OP4 E026B5 0 +OP4 E026B6 0 +OP4 E026B7 0 +OP4 E026B8 0 +OP4 E026B9 0 +OP4 E026BA 0 +OP4 E026BB 0 +OP4 E026BC 0 +OP4 E026BD 0 +OP4 E026BE 0 +OP4 E026BF 0 +OP4 E026C0 0 +OP4 E026C1 0 +OP4 E026C2 0 +OP4 E026C3 0 +OP4 E026C4 0 +OP4 E026C5 0 +OP4 E026C6 0 +OP4 E026C7 0 +OP4 E026C8 0 +OP4 E026C9 0 +OP4 E026CA 0 +OP4 E026CB 0 +OP4 E026CC 0 +OP4 E026CD 0 +OP4 E026CE 0 +OP4 E026CF 0 +OP4 E026D0 0 +OP4 E026D1 0 +OP4 E026D2 0 +OP4 E026D3 0 +OP4 E026D4 0 +OP4 E026D5 0 +OP4 E026D6 0 +OP4 E026D7 0 +OP4 E026D8 0 +OP4 E026D9 0 +OP4 E026DA 0 +OP4 E026DB 0 +OP4 E026DC 0 +OP4 E026DD 0 +OP4 E026DE 0 +OP4 E026DF 0 +OP4 E026E0 0 +OP4 E026E1 0 +OP4 E026E2 0 +OP4 E026E3 0 +OP4 E026E4 0 +OP4 E026E5 0 +OP4 E026E6 0 +OP4 E026E7 0 +OP4 E026E8 0 +OP4 E026E9 0 +OP4 E026EA 0 +OP4 E026EB 0 +OP4 E026EC 0 +OP4 E026ED 0 +OP4 E026EE 0 +OP4 E026EF 0 +OP4 E026F0 0 +OP4 E026F1 0 +OP4 E026F2 0 +OP4 E026F3 0 +OP4 E026F4 0 +OP4 E026F5 0 +OP4 E026F6 0 +OP4 E026F7 0 +OP4 E026F8 0 +OP4 E026F9 0 +OP4 E026FA 0 +OP4 E026FB 0 +OP4 E026FC 0 +OP4 E026FD 0 +OP4 E026FE 0 +OP4 E026FF 0 +OP4 E02700 0 +OP4 E02701 0 +OP4 E02702 0 +OP4 E02703 0 +OP4 E02704 0 +OP4 E02705 0 +OP4 E02706 0 +OP4 E02707 0 +OP4 E02708 0 +OP4 E02709 0 +OP4 E0270A 0 +OP4 E0270B 0 +OP4 E0270C 0 +OP4 E0270D 0 +OP4 E0270E 0 +OP4 E0270F 0 +OP4 E02710 0 +OP4 E02711 0 +OP4 E02712 0 +OP4 E02713 0 +OP4 E02714 0 +OP4 E02715 0 +OP4 E02716 0 +OP4 E02717 0 +OP4 E02718 0 +OP4 E02719 0 +OP4 E0271A 0 +OP4 E0271B 0 +OP4 E0271C 0 +OP4 E0271D 0 +OP4 E0271E 0 +OP4 E0271F 0 +OP4 E02720 0 +OP4 E02721 0 +OP4 E02722 0 +OP4 E02723 0 +OP4 E02724 0 +OP4 E02725 0 +OP4 E02726 0 +OP4 E02727 0 +OP4 E02728 0 +OP4 E02729 0 +OP4 E0272A 0 +OP4 E0272B 0 +OP4 E0272C 0 +OP4 E0272D 0 +OP4 E0272E 0 +OP4 E0272F 0 +OP4 E02730 0 +OP4 E02731 0 +OP4 E02732 0 +OP4 E02733 0 +OP4 E02734 0 +OP4 E02735 0 +OP4 E02736 0 +OP4 E02737 0 +OP4 E02738 0 +OP4 E02739 0 +OP4 E0273A 0 +OP4 E0273B 0 +OP4 E0273C 0 +OP4 E0273D 0 +OP4 E0273E 0 +OP4 E0273F 0 +OP4 E02740 0 +OP4 E02741 0 +OP4 E02742 0 +OP4 E02743 0 +OP4 E02744 0 +OP4 E02745 0 +OP4 E02746 0 +OP4 E02747 0 +OP4 E02748 0 +OP4 E02749 0 +OP4 E0274A 0 +OP4 E0274B 0 +OP4 E0274C 0 +OP4 E0274D 0 +OP4 E0274E 0 +OP4 E0274F 0 +OP4 E02750 0 +OP4 E02751 0 +OP4 E02752 0 +OP4 E02753 0 +OP4 E02754 0 +OP4 E02755 0 +OP4 E02756 0 +OP4 E02757 0 +OP4 E02758 0 +OP4 E02759 0 +OP4 E0275A 0 +OP4 E0275B 0 +OP4 E0275C 0 +OP4 E0275D 0 +OP4 E0275E 0 +OP4 E0275F 0 +OP4 E02760 0 +OP4 E02761 0 +OP4 E02762 0 +OP4 E02763 0 +OP4 E02764 0 +OP4 E02765 0 +OP4 E02766 0 +OP4 E02767 0 +OP4 E02768 0 +OP4 E02769 0 +OP4 E0276A 0 +OP4 E0276B 0 +OP4 E0276C 0 +OP4 E0276D 0 +OP4 E0276E 0 +OP4 E0276F 0 +OP4 E02770 0 +OP4 E02771 0 +OP4 E02772 0 +OP4 E02773 0 +OP4 E02774 0 +OP4 E02775 0 +OP4 E02776 0 +OP4 E02777 0 +OP4 E02778 0 +OP4 E02779 0 +OP4 E0277A 0 +OP4 E0277B 0 +OP4 E0277C 0 +OP4 E0277D 0 +OP4 E0277E 0 +OP4 E0277F 0 +OP4 E02780 0 +OP4 E02781 0 +OP4 E02782 0 +OP4 E02783 0 +OP4 E02784 0 +OP4 E02785 0 +OP4 E02786 0 +OP4 E02787 0 +OP4 E02788 0 +OP4 E02789 0 +OP4 E0278A 0 +OP4 E0278B 0 +OP4 E0278C 0 +OP4 E0278D 0 +OP4 E0278E 0 +OP4 E0278F 0 +OP4 E02790 0 +OP4 E02791 0 +OP4 E02792 0 +OP4 E02793 0 +OP4 E02794 0 +OP4 E02795 0 +OP4 E02796 0 +OP4 E02797 0 +OP4 E02798 0 +OP4 E02799 0 +OP4 E0279A 0 +OP4 E0279B 0 +OP4 E0279C 0 +OP4 E0279D 0 +OP4 E0279E 0 +OP4 E0279F 0 +OP4 E027A0 0 +OP4 E027A1 0 +OP4 E027A2 0 +OP4 E027A3 0 +OP4 E027A4 0 +OP4 E027A5 0 +OP4 E027A6 0 +OP4 E027A7 0 +OP4 E027A8 0 +OP4 E027A9 0 +OP4 E027AA 0 +OP4 E027AB 0 +OP4 E027AC 0 +OP4 E027AD 0 +OP4 E027AE 0 +OP4 E027AF 0 +OP4 E027B0 0 +OP4 E027B1 0 +OP4 E027B2 0 +OP4 E027B3 0 +OP4 E027B4 0 +OP4 E027B5 0 +OP4 E027B6 0 +OP4 E027B7 0 +OP4 E027B8 0 +OP4 E027B9 0 +OP4 E027BA 0 +OP4 E027BB 0 +OP4 E027BC 0 +OP4 E027BD 0 +OP4 E027BE 0 +OP4 E027BF 0 +OP4 E027C0 0 +OP4 E027C1 0 +OP4 E027C2 0 +OP4 E027C3 0 +OP4 E027C4 0 +OP4 E027C5 0 +OP4 E027C6 0 +OP4 E027C7 0 +OP4 E027C8 0 +OP4 E027C9 0 +OP4 E027CA 0 +OP4 E027CB 0 +OP4 E027CC 0 +OP4 E027CD 0 +OP4 E027CE 0 +OP4 E027CF 0 +OP4 E027D0 0 +OP4 E027D1 0 +OP4 E027D2 0 +OP4 E027D3 0 +OP4 E027D4 0 +OP4 E027D5 0 +OP4 E027D6 0 +OP4 E027D7 0 +OP4 E027D8 0 +OP4 E027D9 0 +OP4 E027DA 0 +OP4 E027DB 0 +OP4 E027DC 0 +OP4 E027DD 0 +OP4 E027DE 0 +OP4 E027DF 0 +OP4 E027E0 0 +OP4 E027E1 0 +OP4 E027E2 0 +OP4 E027E3 0 +OP4 E027E4 0 +OP4 E027E5 0 +OP4 E027E6 0 +OP4 E027E7 0 +OP4 E027E8 0 +OP4 E027E9 0 +OP4 E027EA 0 +OP4 E027EB 0 +OP4 E027EC 0 +OP4 E027ED 0 +OP4 E027EE 0 +OP4 E027EF 0 +OP4 E027F0 0 +OP4 E027F1 0 +OP4 E027F2 0 +OP4 E027F3 0 +OP4 E027F4 0 +OP4 E027F5 0 +OP4 E027F6 0 +OP4 E027F7 0 +OP4 E027F8 0 +OP4 E027F9 0 +OP4 E027FA 0 +OP4 E027FB 0 +OP4 E027FC 0 +OP4 E027FD 0 +OP4 E027FE 0 +OP4 E027FF 0 +OP4 E02800 0 +OP4 E02801 0 +OP4 E02802 0 +OP4 E02803 0 +OP4 E02804 0 +OP4 E02805 0 +OP4 E02806 0 +OP4 E02807 0 +OP4 E02808 0 +OP4 E02809 0 +OP4 E0280A 0 +OP4 E0280B 0 +OP4 E0280C 0 +OP4 E0280D 0 +OP4 E0280E 0 +OP4 E0280F 0 +OP4 E02810 0 +OP4 E02811 0 +OP4 E02812 0 +OP4 E02813 0 +OP4 E02814 0 +OP4 E02815 0 +OP4 E02816 0 +OP4 E02817 0 +OP4 E02818 0 +OP4 E02819 0 +OP4 E0281A 0 +OP4 E0281B 0 +OP4 E0281C 0 +OP4 E0281D 0 +OP4 E0281E 0 +OP4 E0281F 0 +OP4 E02820 0 +OP4 E02821 0 +OP4 E02822 0 +OP4 E02823 0 +OP4 E02824 0 +OP4 E02825 0 +OP4 E02826 0 +OP4 E02827 0 +OP4 E02828 0 +OP4 E02829 0 +OP4 E0282A 0 +OP4 E0282B 0 +OP4 E0282C 0 +OP4 E0282D 0 +OP4 E0282E 0 +OP4 E0282F 0 +OP4 E02830 0 +OP4 E02831 0 +OP4 E02832 0 +OP4 E02833 0 +OP4 E02834 0 +OP4 E02835 0 +OP4 E02836 0 +OP4 E02837 0 +OP4 E02838 0 +OP4 E02839 0 +OP4 E0283A 0 +OP4 E0283B 0 +OP4 E0283C 0 +OP4 E0283D 0 +OP4 E0283E 0 +OP4 E0283F 0 +OP4 E02840 0 +OP4 E02841 0 +OP4 E02842 0 +OP4 E02843 0 +OP4 E02844 0 +OP4 E02845 0 +OP4 E02846 0 +OP4 E02847 0 +OP4 E02848 0 +OP4 E02849 0 +OP4 E0284A 0 +OP4 E0284B 0 +OP4 E0284C 0 +OP4 E0284D 0 +OP4 E0284E 0 +OP4 E0284F 0 +OP4 E02850 0 +OP4 E02851 0 +OP4 E02852 0 +OP4 E02853 0 +OP4 E02854 0 +OP4 E02855 0 +OP4 E02856 0 +OP4 E02857 0 +OP4 E02858 0 +OP4 E02859 0 +OP4 E0285A 0 +OP4 E0285B 0 +OP4 E0285C 0 +OP4 E0285D 0 +OP4 E0285E 0 +OP4 E0285F 0 +OP4 E02860 0 +OP4 E02861 0 +OP4 E02862 0 +OP4 E02863 0 +OP4 E02864 0 +OP4 E02865 0 +OP4 E02866 0 +OP4 E02867 0 +OP4 E02868 0 +OP4 E02869 0 +OP4 E0286A 0 +OP4 E0286B 0 +OP4 E0286C 0 +OP4 E0286D 0 +OP4 E0286E 0 +OP4 E0286F 0 +OP4 E02870 0 +OP4 E02871 0 +OP4 E02872 0 +OP4 E02873 0 +OP4 E02874 0 +OP4 E02875 0 +OP4 E02876 0 +OP4 E02877 0 +OP4 E02878 0 +OP4 E02879 0 +OP4 E0287A 0 +OP4 E0287B 0 +OP4 E0287C 0 +OP4 E0287D 0 +OP4 E0287E 0 +OP4 E0287F 0 +OP4 E02880 0 +OP4 E02881 0 +OP4 E02882 0 +OP4 E02883 0 +OP4 E02884 0 +OP4 E02885 0 +OP4 E02886 0 +OP4 E02887 0 +OP4 E02888 0 +OP4 E02889 0 +OP4 E0288A 0 +OP4 E0288B 0 +OP4 E0288C 0 +OP4 E0288D 0 +OP4 E0288E 0 +OP4 E0288F 0 +OP4 E02890 0 +OP4 E02891 0 +OP4 E02892 0 +OP4 E02893 0 +OP4 E02894 0 +OP4 E02895 0 +OP4 E02896 0 +OP4 E02897 0 +OP4 E02898 0 +OP4 E02899 0 +OP4 E0289A 0 +OP4 E0289B 0 +OP4 E0289C 0 +OP4 E0289D 0 +OP4 E0289E 0 +OP4 E0289F 0 +OP4 E028A0 0 +OP4 E028A1 0 +OP4 E028A2 0 +OP4 E028A3 0 +OP4 E028A4 0 +OP4 E028A5 0 +OP4 E028A6 0 +OP4 E028A7 0 +OP4 E028A8 0 +OP4 E028A9 0 +OP4 E028AA 0 +OP4 E028AB 0 +OP4 E028AC 0 +OP4 E028AD 0 +OP4 E028AE 0 +OP4 E028AF 0 +OP4 E028B0 0 +OP4 E028B1 0 +OP4 E028B2 0 +OP4 E028B3 0 +OP4 E028B4 0 +OP4 E028B5 0 +OP4 E028B6 0 +OP4 E028B7 0 +OP4 E028B8 0 +OP4 E028B9 0 +OP4 E028BA 0 +OP4 E028BB 0 +OP4 E028BC 0 +OP4 E028BD 0 +OP4 E028BE 0 +OP4 E028BF 0 +OP4 E028C0 0 +OP4 E028C1 0 +OP4 E028C2 0 +OP4 E028C3 0 +OP4 E028C4 0 +OP4 E028C5 0 +OP4 E028C6 0 +OP4 E028C7 0 +OP4 E028C8 0 +OP4 E028C9 0 +OP4 E028CA 0 +OP4 E028CB 0 +OP4 E028CC 0 +OP4 E028CD 0 +OP4 E028CE 0 +OP4 E028CF 0 +OP4 E028D0 0 +OP4 E028D1 0 +OP4 E028D2 0 +OP4 E028D3 0 +OP4 E028D4 0 +OP4 E028D5 0 +OP4 E028D6 0 +OP4 E028D7 0 +OP4 E028D8 0 +OP4 E028D9 0 +OP4 E028DA 0 +OP4 E028DB 0 +OP4 E028DC 0 +OP4 E028DD 0 +OP4 E028DE 0 +OP4 E028DF 0 +OP4 E028E0 0 +OP4 E028E1 0 +OP4 E028E2 0 +OP4 E028E3 0 +OP4 E028E4 0 +OP4 E028E5 0 +OP4 E028E6 0 +OP4 E028E7 0 +OP4 E028E8 0 +OP4 E028E9 0 +OP4 E028EA 0 +OP4 E028EB 0 +OP4 E028EC 0 +OP4 E028ED 0 +OP4 E028EE 0 +OP4 E028EF 0 +OP4 E028F0 0 +OP4 E028F1 0 +OP4 E028F2 0 +OP4 E028F3 0 +OP4 E028F4 0 +OP4 E028F5 0 +OP4 E028F6 0 +OP4 E028F7 0 +OP4 E028F8 0 +OP4 E028F9 0 +OP4 E028FA 0 +OP4 E028FB 0 +OP4 E028FC 0 +OP4 E028FD 0 +OP4 E028FE 0 +OP4 E028FF 0 +OP4 E02900 0 +OP4 E02901 0 +OP4 E02902 0 +OP4 E02903 0 +OP4 E02904 0 +OP4 E02905 0 +OP4 E02906 0 +OP4 E02907 0 +OP4 E02908 0 +OP4 E02909 0 +OP4 E0290A 0 +OP4 E0290B 0 +OP4 E0290C 0 +OP4 E0290D 0 +OP4 E0290E 0 +OP4 E0290F 0 +OP4 E02910 0 +OP4 E02911 0 +OP4 E02912 0 +OP4 E02913 0 +OP4 E02914 0 +OP4 E02915 0 +OP4 E02916 0 +OP4 E02917 0 +OP4 E02918 0 +OP4 E02919 0 +OP4 E0291A 0 +OP4 E0291B 0 +OP4 E0291C 0 +OP4 E0291D 0 +OP4 E0291E 0 +OP4 E0291F 0 +OP4 E02920 0 +OP4 E02921 0 +OP4 E02922 0 +OP4 E02923 0 +OP4 E02924 0 +OP4 E02925 0 +OP4 E02926 0 +OP4 E02927 0 +OP4 E02928 0 +OP4 E02929 0 +OP4 E0292A 0 +OP4 E0292B 0 +OP4 E0292C 0 +OP4 E0292D 0 +OP4 E0292E 0 +OP4 E0292F 0 +OP4 E02930 0 +OP4 E02931 0 +OP4 E02932 0 +OP4 E02933 0 +OP4 E02934 0 +OP4 E02935 0 +OP4 E02936 0 +OP4 E02937 0 +OP4 E02938 0 +OP4 E02939 0 +OP4 E0293A 0 +OP4 E0293B 0 +OP4 E0293C 0 +OP4 E0293D 0 +OP4 E0293E 0 +OP4 E0293F 0 +OP4 E02940 0 +OP4 E02941 0 +OP4 E02942 0 +OP4 E02943 0 +OP4 E02944 0 +OP4 E02945 0 +OP4 E02946 0 +OP4 E02947 0 +OP4 E02948 0 +OP4 E02949 0 +OP4 E0294A 0 +OP4 E0294B 0 +OP4 E0294C 0 +OP4 E0294D 0 +OP4 E0294E 0 +OP4 E0294F 0 +OP4 E02950 0 +OP4 E02951 0 +OP4 E02952 0 +OP4 E02953 0 +OP4 E02954 0 +OP4 E02955 0 +OP4 E02956 0 +OP4 E02957 0 +OP4 E02958 0 +OP4 E02959 0 +OP4 E0295A 0 +OP4 E0295B 0 +OP4 E0295C 0 +OP4 E0295D 0 +OP4 E0295E 0 +OP4 E0295F 0 +OP4 E02960 0 +OP4 E02961 0 +OP4 E02962 0 +OP4 E02963 0 +OP4 E02964 0 +OP4 E02965 0 +OP4 E02966 0 +OP4 E02967 0 +OP4 E02968 0 +OP4 E02969 0 +OP4 E0296A 0 +OP4 E0296B 0 +OP4 E0296C 0 +OP4 E0296D 0 +OP4 E0296E 0 +OP4 E0296F 0 +OP4 E02970 0 +OP4 E02971 0 +OP4 E02972 0 +OP4 E02973 0 +OP4 E02974 0 +OP4 E02975 0 +OP4 E02976 0 +OP4 E02977 0 +OP4 E02978 0 +OP4 E02979 0 +OP4 E0297A 0 +OP4 E0297B 0 +OP4 E0297C 0 +OP4 E0297D 0 +OP4 E0297E 0 +OP4 E0297F 0 +OP4 E02980 0 +OP4 E02981 0 +OP4 E02982 0 +OP4 E02983 0 +OP4 E02984 0 +OP4 E02985 0 +OP4 E02986 0 +OP4 E02987 0 +OP4 E02988 0 +OP4 E02989 0 +OP4 E0298A 0 +OP4 E0298B 0 +OP4 E0298C 0 +OP4 E0298D 0 +OP4 E0298E 0 +OP4 E0298F 0 +OP4 E02990 0 +OP4 E02991 0 +OP4 E02992 0 +OP4 E02993 0 +OP4 E02994 0 +OP4 E02995 0 +OP4 E02996 0 +OP4 E02997 0 +OP4 E02998 0 +OP4 E02999 0 +OP4 E0299A 0 +OP4 E0299B 0 +OP4 E0299C 0 +OP4 E0299D 0 +OP4 E0299E 0 +OP4 E0299F 0 +OP4 E029A0 0 +OP4 E029A1 0 +OP4 E029A2 0 +OP4 E029A3 0 +OP4 E029A4 0 +OP4 E029A5 0 +OP4 E029A6 0 +OP4 E029A7 0 +OP4 E029A8 0 +OP4 E029A9 0 +OP4 E029AA 0 +OP4 E029AB 0 +OP4 E029AC 0 +OP4 E029AD 0 +OP4 E029AE 0 +OP4 E029AF 0 +OP4 E029B0 0 +OP4 E029B1 0 +OP4 E029B2 0 +OP4 E029B3 0 +OP4 E029B4 0 +OP4 E029B5 0 +OP4 E029B6 0 +OP4 E029B7 0 +OP4 E029B8 0 +OP4 E029B9 0 +OP4 E029BA 0 +OP4 E029BB 0 +OP4 E029BC 0 +OP4 E029BD 0 +OP4 E029BE 0 +OP4 E029BF 0 +OP4 E029C0 0 +OP4 E029C1 0 +OP4 E029C2 0 +OP4 E029C3 0 +OP4 E029C4 0 +OP4 E029C5 0 +OP4 E029C6 0 +OP4 E029C7 0 +OP4 E029C8 0 +OP4 E029C9 0 +OP4 E029CA 0 +OP4 E029CB 0 +OP4 E029CC 0 +OP4 E029CD 0 +OP4 E029CE 0 +OP4 E029CF 0 +OP4 E029D0 0 +OP4 E029D1 0 +OP4 E029D2 0 +OP4 E029D3 0 +OP4 E029D4 0 +OP4 E029D5 0 +OP4 E029D6 0 +OP4 E029D7 0 +OP4 E029D8 0 +OP4 E029D9 0 +OP4 E029DA 0 +OP4 E029DB 0 +OP4 E029DC 0 +OP4 E029DD 0 +OP4 E029DE 0 +OP4 E029DF 0 +OP4 E029E0 0 +OP4 E029E1 0 +OP4 E029E2 0 +OP4 E029E3 0 +OP4 E029E4 0 +OP4 E029E5 0 +OP4 E029E6 0 +OP4 E029E7 0 +OP4 E029E8 0 +OP4 E029E9 0 +OP4 E029EA 0 +OP4 E029EB 0 +OP4 E029EC 0 +OP4 E029ED 0 +OP4 E029EE 0 +OP4 E029EF 0 +OP4 E029F0 0 +OP4 E029F1 0 +OP4 E029F2 0 +OP4 E029F3 0 +OP4 E029F4 0 +OP4 E029F5 0 +OP4 E029F6 0 +OP4 E029F7 0 +OP4 E029F8 0 +OP4 E029F9 0 +OP4 E029FA 0 +OP4 E029FB 0 +OP4 E029FC 0 +OP4 E029FD 0 +OP4 E029FE 0 +OP4 E029FF 0 +OP4 E02A00 0 +OP4 E02A01 0 +OP4 E02A02 0 +OP4 E02A03 0 +OP4 E02A04 0 +OP4 E02A05 0 +OP4 E02A06 0 +OP4 E02A07 0 +OP4 E02A08 0 +OP4 E02A09 0 +OP4 E02A0A 0 +OP4 E02A0B 0 +OP4 E02A0C 0 +OP4 E02A0D 0 +OP4 E02A0E 0 +OP4 E02A0F 0 +OP4 E02A10 0 +OP4 E02A11 0 +OP4 E02A12 0 +OP4 E02A13 0 +OP4 E02A14 0 +OP4 E02A15 0 +OP4 E02A16 0 +OP4 E02A17 0 +OP4 E02A18 0 +OP4 E02A19 0 +OP4 E02A1A 0 +OP4 E02A1B 0 +OP4 E02A1C 0 +OP4 E02A1D 0 +OP4 E02A1E 0 +OP4 E02A1F 0 +OP4 E02A20 0 +OP4 E02A21 0 +OP4 E02A22 0 +OP4 E02A23 0 +OP4 E02A24 0 +OP4 E02A25 0 +OP4 E02A26 0 +OP4 E02A27 0 +OP4 E02A28 0 +OP4 E02A29 0 +OP4 E02A2A 0 +OP4 E02A2B 0 +OP4 E02A2C 0 +OP4 E02A2D 0 +OP4 E02A2E 0 +OP4 E02A2F 0 +OP4 E02A30 0 +OP4 E02A31 0 +OP4 E02A32 0 +OP4 E02A33 0 +OP4 E02A34 0 +OP4 E02A35 0 +OP4 E02A36 0 +OP4 E02A37 0 +OP4 E02A38 0 +OP4 E02A39 0 +OP4 E02A3A 0 +OP4 E02A3B 0 +OP4 E02A3C 0 +OP4 E02A3D 0 +OP4 E02A3E 0 +OP4 E02A3F 0 +OP4 E02A40 0 +OP4 E02A41 0 +OP4 E02A42 0 +OP4 E02A43 0 +OP4 E02A44 0 +OP4 E02A45 0 +OP4 E02A46 0 +OP4 E02A47 0 +OP4 E02A48 0 +OP4 E02A49 0 +OP4 E02A4A 0 +OP4 E02A4B 0 +OP4 E02A4C 0 +OP4 E02A4D 0 +OP4 E02A4E 0 +OP4 E02A4F 0 +OP4 E02A50 0 +OP4 E02A51 0 +OP4 E02A52 0 +OP4 E02A53 0 +OP4 E02A54 0 +OP4 E02A55 0 +OP4 E02A56 0 +OP4 E02A57 0 +OP4 E02A58 0 +OP4 E02A59 0 +OP4 E02A5A 0 +OP4 E02A5B 0 +OP4 E02A5C 0 +OP4 E02A5D 0 +OP4 E02A5E 0 +OP4 E02A5F 0 +OP4 E02A60 0 +OP4 E02A61 0 +OP4 E02A62 0 +OP4 E02A63 0 +OP4 E02A64 0 +OP4 E02A65 0 +OP4 E02A66 0 +OP4 E02A67 0 +OP4 E02A68 0 +OP4 E02A69 0 +OP4 E02A6A 0 +OP4 E02A6B 0 +OP4 E02A6C 0 +OP4 E02A6D 0 +OP4 E02A6E 0 +OP4 E02A6F 0 +OP4 E02A70 0 +OP4 E02A71 0 +OP4 E02A72 0 +OP4 E02A73 0 +OP4 E02A74 0 +OP4 E02A75 0 +OP4 E02A76 0 +OP4 E02A77 0 +OP4 E02A78 0 +OP4 E02A79 0 +OP4 E02A7A 0 +OP4 E02A7B 0 +OP4 E02A7C 0 +OP4 E02A7D 0 +OP4 E02A7E 0 +OP4 E02A7F 0 +OP4 E02A80 0 +OP4 E02A81 0 +OP4 E02A82 0 +OP4 E02A83 0 +OP4 E02A84 0 +OP4 E02A85 0 +OP4 E02A86 0 +OP4 E02A87 0 +OP4 E02A88 0 +OP4 E02A89 0 +OP4 E02A8A 0 +OP4 E02A8B 0 +OP4 E02A8C 0 +OP4 E02A8D 0 +OP4 E02A8E 0 +OP4 E02A8F 0 +OP4 E02A90 0 +OP4 E02A91 0 +OP4 E02A92 0 +OP4 E02A93 0 +OP4 E02A94 0 +OP4 E02A95 0 +OP4 E02A96 0 +OP4 E02A97 0 +OP4 E02A98 0 +OP4 E02A99 0 +OP4 E02A9A 0 +OP4 E02A9B 0 +OP4 E02A9C 0 +OP4 E02A9D 0 +OP4 E02A9E 0 +OP4 E02A9F 0 +OP4 E02AA0 0 +OP4 E02AA1 0 +OP4 E02AA2 0 +OP4 E02AA3 0 +OP4 E02AA4 0 +OP4 E02AA5 0 +OP4 E02AA6 0 +OP4 E02AA7 0 +OP4 E02AA8 0 +OP4 E02AA9 0 +OP4 E02AAA 0 +OP4 E02AAB 0 +OP4 E02AAC 0 +OP4 E02AAD 0 +OP4 E02AAE 0 +OP4 E02AAF 0 +OP4 E02AB0 0 +OP4 E02AB1 0 +OP4 E02AB2 0 +OP4 E02AB3 0 +OP4 E02AB4 0 +OP4 E02AB5 0 +OP4 E02AB6 0 +OP4 E02AB7 0 +OP4 E02AB8 0 +OP4 E02AB9 0 +OP4 E02ABA 0 +OP4 E02ABB 0 +OP4 E02ABC 0 +OP4 E02ABD 0 +OP4 E02ABE 0 +OP4 E02ABF 0 +OP4 E02AC0 0 +OP4 E02AC1 0 +OP4 E02AC2 0 +OP4 E02AC3 0 +OP4 E02AC4 0 +OP4 E02AC5 0 +OP4 E02AC6 0 +OP4 E02AC7 0 +OP4 E02AC8 0 +OP4 E02AC9 0 +OP4 E02ACA 0 +OP4 E02ACB 0 +OP4 E02ACC 0 +OP4 E02ACD 0 +OP4 E02ACE 0 +OP4 E02ACF 0 +OP4 E02AD0 0 +OP4 E02AD1 0 +OP4 E02AD2 0 +OP4 E02AD3 0 +OP4 E02AD4 0 +OP4 E02AD5 0 +OP4 E02AD6 0 +OP4 E02AD7 0 +OP4 E02AD8 0 +OP4 E02AD9 0 +OP4 E02ADA 0 +OP4 E02ADB 0 +OP4 E02ADC 0 +OP4 E02ADD 0 +OP4 E02ADE 0 +OP4 E02ADF 0 +OP4 E02AE0 0 +OP4 E02AE1 0 +OP4 E02AE2 0 +OP4 E02AE3 0 +OP4 E02AE4 0 +OP4 E02AE5 0 +OP4 E02AE6 0 +OP4 E02AE7 0 +OP4 E02AE8 0 +OP4 E02AE9 0 +OP4 E02AEA 0 +OP4 E02AEB 0 +OP4 E02AEC 0 +OP4 E02AED 0 +OP4 E02AEE 0 +OP4 E02AEF 0 +OP4 E02AF0 0 +OP4 E02AF1 0 +OP4 E02AF2 0 +OP4 E02AF3 0 +OP4 E02AF4 0 +OP4 E02AF5 0 +OP4 E02AF6 0 +OP4 E02AF7 0 +OP4 E02AF8 0 +OP4 E02AF9 0 +OP4 E02AFA 0 +OP4 E02AFB 0 +OP4 E02AFC 0 +OP4 E02AFD 0 +OP4 E02AFE 0 +OP4 E02AFF 0 +OP4 E02B00 0 +OP4 E02B01 0 +OP4 E02B02 0 +OP4 E02B03 0 +OP4 E02B04 0 +OP4 E02B05 0 +OP4 E02B06 0 +OP4 E02B07 0 +OP4 E02B08 0 +OP4 E02B09 0 +OP4 E02B0A 0 +OP4 E02B0B 0 +OP4 E02B0C 0 +OP4 E02B0D 0 +OP4 E02B0E 0 +OP4 E02B0F 0 +OP4 E02B10 0 +OP4 E02B11 0 +OP4 E02B12 0 +OP4 E02B13 0 +OP4 E02B14 0 +OP4 E02B15 0 +OP4 E02B16 0 +OP4 E02B17 0 +OP4 E02B18 0 +OP4 E02B19 0 +OP4 E02B1A 0 +OP4 E02B1B 0 +OP4 E02B1C 0 +OP4 E02B1D 0 +OP4 E02B1E 0 +OP4 E02B1F 0 +OP4 E02B20 0 +OP4 E02B21 0 +OP4 E02B22 0 +OP4 E02B23 0 +OP4 E02B24 0 +OP4 E02B25 0 +OP4 E02B26 0 +OP4 E02B27 0 +OP4 E02B28 0 +OP4 E02B29 0 +OP4 E02B2A 0 +OP4 E02B2B 0 +OP4 E02B2C 0 +OP4 E02B2D 0 +OP4 E02B2E 0 +OP4 E02B2F 0 +OP4 E02B30 0 +OP4 E02B31 0 +OP4 E02B32 0 +OP4 E02B33 0 +OP4 E02B34 0 +OP4 E02B35 0 +OP4 E02B36 0 +OP4 E02B37 0 +OP4 E02B38 0 +OP4 E02B39 0 +OP4 E02B3A 0 +OP4 E02B3B 0 +OP4 E02B3C 0 +OP4 E02B3D 0 +OP4 E02B3E 0 +OP4 E02B3F 0 +OP4 E02B40 0 +OP4 E02B41 0 +OP4 E02B42 0 +OP4 E02B43 0 +OP4 E02B44 0 +OP4 E02B45 0 +OP4 E02B46 0 +OP4 E02B47 0 +OP4 E02B48 0 +OP4 E02B49 0 +OP4 E02B4A 0 +OP4 E02B4B 0 +OP4 E02B4C 0 +OP4 E02B4D 0 +OP4 E02B4E 0 +OP4 E02B4F 0 +OP4 E02B50 0 +OP4 E02B51 0 +OP4 E02B52 0 +OP4 E02B53 0 +OP4 E02B54 0 +OP4 E02B55 0 +OP4 E02B56 0 +OP4 E02B57 0 +OP4 E02B58 0 +OP4 E02B59 0 +OP4 E02B5A 0 +OP4 E02B5B 0 +OP4 E02B5C 0 +OP4 E02B5D 0 +OP4 E02B5E 0 +OP4 E02B5F 0 +OP4 E02B60 0 +OP4 E02B61 0 +OP4 E02B62 0 +OP4 E02B63 0 +OP4 E02B64 0 +OP4 E02B65 0 +OP4 E02B66 0 +OP4 E02B67 0 +OP4 E02B68 0 +OP4 E02B69 0 +OP4 E02B6A 0 +OP4 E02B6B 0 +OP4 E02B6C 0 +OP4 E02B6D 0 +OP4 E02B6E 0 +OP4 E02B6F 0 +OP4 E02B70 0 +OP4 E02B71 0 +OP4 E02B72 0 +OP4 E02B73 0 +OP4 E02B74 0 +OP4 E02B75 0 +OP4 E02B76 0 +OP4 E02B77 0 +OP4 E02B78 0 +OP4 E02B79 0 +OP4 E02B7A 0 +OP4 E02B7B 0 +OP4 E02B7C 0 +OP4 E02B7D 0 +OP4 E02B7E 0 +OP4 E02B7F 0 +OP4 E02B80 0 +OP4 E02B81 0 +OP4 E02B82 0 +OP4 E02B83 0 +OP4 E02B84 0 +OP4 E02B85 0 +OP4 E02B86 0 +OP4 E02B87 0 +OP4 E02B88 0 +OP4 E02B89 0 +OP4 E02B8A 0 +OP4 E02B8B 0 +OP4 E02B8C 0 +OP4 E02B8D 0 +OP4 E02B8E 0 +OP4 E02B8F 0 +OP4 E02B90 0 +OP4 E02B91 0 +OP4 E02B92 0 +OP4 E02B93 0 +OP4 E02B94 0 +OP4 E02B95 0 +OP4 E02B96 0 +OP4 E02B97 0 +OP4 E02B98 0 +OP4 E02B99 0 +OP4 E02B9A 0 +OP4 E02B9B 0 +OP4 E02B9C 0 +OP4 E02B9D 0 +OP4 E02B9E 0 +OP4 E02B9F 0 +OP4 E02BA0 0 +OP4 E02BA1 0 +OP4 E02BA2 0 +OP4 E02BA3 0 +OP4 E02BA4 0 +OP4 E02BA5 0 +OP4 E02BA6 0 +OP4 E02BA7 0 +OP4 E02BA8 0 +OP4 E02BA9 0 +OP4 E02BAA 0 +OP4 E02BAB 0 +OP4 E02BAC 0 +OP4 E02BAD 0 +OP4 E02BAE 0 +OP4 E02BAF 0 +OP4 E02BB0 0 +OP4 E02BB1 0 +OP4 E02BB2 0 +OP4 E02BB3 0 +OP4 E02BB4 0 +OP4 E02BB5 0 +OP4 E02BB6 0 +OP4 E02BB7 0 +OP4 E02BB8 0 +OP4 E02BB9 0 +OP4 E02BBA 0 +OP4 E02BBB 0 +OP4 E02BBC 0 +OP4 E02BBD 0 +OP4 E02BBE 0 +OP4 E02BBF 0 +OP4 E02BC0 0 +OP4 E02BC1 0 +OP4 E02BC2 0 +OP4 E02BC3 0 +OP4 E02BC4 0 +OP4 E02BC5 0 +OP4 E02BC6 0 +OP4 E02BC7 0 +OP4 E02BC8 0 +OP4 E02BC9 0 +OP4 E02BCA 0 +OP4 E02BCB 0 +OP4 E02BCC 0 +OP4 E02BCD 0 +OP4 E02BCE 0 +OP4 E02BCF 0 +OP4 E02BD0 0 +OP4 E02BD1 0 +OP4 E02BD2 0 +OP4 E02BD3 0 +OP4 E02BD4 0 +OP4 E02BD5 0 +OP4 E02BD6 0 +OP4 E02BD7 0 +OP4 E02BD8 0 +OP4 E02BD9 0 +OP4 E02BDA 0 +OP4 E02BDB 0 +OP4 E02BDC 0 +OP4 E02BDD 0 +OP4 E02BDE 0 +OP4 E02BDF 0 +OP4 E02BE0 0 +OP4 E02BE1 0 +OP4 E02BE2 0 +OP4 E02BE3 0 +OP4 E02BE4 0 +OP4 E02BE5 0 +OP4 E02BE6 0 +OP4 E02BE7 0 +OP4 E02BE8 0 +OP4 E02BE9 0 +OP4 E02BEA 0 +OP4 E02BEB 0 +OP4 E02BEC 0 +OP4 E02BED 0 +OP4 E02BEE 0 +OP4 E02BEF 0 +OP4 E02BF0 0 +OP4 E02BF1 0 +OP4 E02BF2 0 +OP4 E02BF3 0 +OP4 E02BF4 0 +OP4 E02BF5 0 +OP4 E02BF6 0 +OP4 E02BF7 0 +OP4 E02BF8 0 +OP4 E02BF9 0 +OP4 E02BFA 0 +OP4 E02BFB 0 +OP4 E02BFC 0 +OP4 E02BFD 0 +OP4 E02BFE 0 +OP4 E02BFF 0 +OP4 E02C00 0 +OP4 E02C01 0 +OP4 E02C02 0 +OP4 E02C03 0 +OP4 E02C04 0 +OP4 E02C05 0 +OP4 E02C06 0 +OP4 E02C07 0 +OP4 E02C08 0 +OP4 E02C09 0 +OP4 E02C0A 0 +OP4 E02C0B 0 +OP4 E02C0C 0 +OP4 E02C0D 0 +OP4 E02C0E 0 +OP4 E02C0F 0 +OP4 E02C10 0 +OP4 E02C11 0 +OP4 E02C12 0 +OP4 E02C13 0 +OP4 E02C14 0 +OP4 E02C15 0 +OP4 E02C16 0 +OP4 E02C17 0 +OP4 E02C18 0 +OP4 E02C19 0 +OP4 E02C1A 0 +OP4 E02C1B 0 +OP4 E02C1C 0 +OP4 E02C1D 0 +OP4 E02C1E 0 +OP4 E02C1F 0 +OP4 E02C20 0 +OP4 E02C21 0 +OP4 E02C22 0 +OP4 E02C23 0 +OP4 E02C24 0 +OP4 E02C25 0 +OP4 E02C26 0 +OP4 E02C27 0 +OP4 E02C28 0 +OP4 E02C29 0 +OP4 E02C2A 0 +OP4 E02C2B 0 +OP4 E02C2C 0 +OP4 E02C2D 0 +OP4 E02C2E 0 +OP4 E02C2F 0 +OP4 E02C30 0 +OP4 E02C31 0 +OP4 E02C32 0 +OP4 E02C33 0 +OP4 E02C34 0 +OP4 E02C35 0 +OP4 E02C36 0 +OP4 E02C37 0 +OP4 E02C38 0 +OP4 E02C39 0 +OP4 E02C3A 0 +OP4 E02C3B 0 +OP4 E02C3C 0 +OP4 E02C3D 0 +OP4 E02C3E 0 +OP4 E02C3F 0 +OP4 E02C40 0 +OP4 E02C41 0 +OP4 E02C42 0 +OP4 E02C43 0 +OP4 E02C44 0 +OP4 E02C45 0 +OP4 E02C46 0 +OP4 E02C47 0 +OP4 E02C48 0 +OP4 E02C49 0 +OP4 E02C4A 0 +OP4 E02C4B 0 +OP4 E02C4C 0 +OP4 E02C4D 0 +OP4 E02C4E 0 +OP4 E02C4F 0 +OP4 E02C50 0 +OP4 E02C51 0 +OP4 E02C52 0 +OP4 E02C53 0 +OP4 E02C54 0 +OP4 E02C55 0 +OP4 E02C56 0 +OP4 E02C57 0 +OP4 E02C58 0 +OP4 E02C59 0 +OP4 E02C5A 0 +OP4 E02C5B 0 +OP4 E02C5C 0 +OP4 E02C5D 0 +OP4 E02C5E 0 +OP4 E02C5F 0 +OP4 E02C60 0 +OP4 E02C61 0 +OP4 E02C62 0 +OP4 E02C63 0 +OP4 E02C64 0 +OP4 E02C65 0 +OP4 E02C66 0 +OP4 E02C67 0 +OP4 E02C68 0 +OP4 E02C69 0 +OP4 E02C6A 0 +OP4 E02C6B 0 +OP4 E02C6C 0 +OP4 E02C6D 0 +OP4 E02C6E 0 +OP4 E02C6F 0 +OP4 E02C70 0 +OP4 E02C71 0 +OP4 E02C72 0 +OP4 E02C73 0 +OP4 E02C74 0 +OP4 E02C75 0 +OP4 E02C76 0 +OP4 E02C77 0 +OP4 E02C78 0 +OP4 E02C79 0 +OP4 E02C7A 0 +OP4 E02C7B 0 +OP4 E02C7C 0 +OP4 E02C7D 0 +OP4 E02C7E 0 +OP4 E02C7F 0 +OP4 E02C80 0 +OP4 E02C81 0 +OP4 E02C82 0 +OP4 E02C83 0 +OP4 E02C84 0 +OP4 E02C85 0 +OP4 E02C86 0 +OP4 E02C87 0 +OP4 E02C88 0 +OP4 E02C89 0 +OP4 E02C8A 0 +OP4 E02C8B 0 +OP4 E02C8C 0 +OP4 E02C8D 0 +OP4 E02C8E 0 +OP4 E02C8F 0 +OP4 E02C90 0 +OP4 E02C91 0 +OP4 E02C92 0 +OP4 E02C93 0 +OP4 E02C94 0 +OP4 E02C95 0 +OP4 E02C96 0 +OP4 E02C97 0 +OP4 E02C98 0 +OP4 E02C99 0 +OP4 E02C9A 0 +OP4 E02C9B 0 +OP4 E02C9C 0 +OP4 E02C9D 0 +OP4 E02C9E 0 +OP4 E02C9F 0 +OP4 E02CA0 0 +OP4 E02CA1 0 +OP4 E02CA2 0 +OP4 E02CA3 0 +OP4 E02CA4 0 +OP4 E02CA5 0 +OP4 E02CA6 0 +OP4 E02CA7 0 +OP4 E02CA8 0 +OP4 E02CA9 0 +OP4 E02CAA 0 +OP4 E02CAB 0 +OP4 E02CAC 0 +OP4 E02CAD 0 +OP4 E02CAE 0 +OP4 E02CAF 0 +OP4 E02CB0 0 +OP4 E02CB1 0 +OP4 E02CB2 0 +OP4 E02CB3 0 +OP4 E02CB4 0 +OP4 E02CB5 0 +OP4 E02CB6 0 +OP4 E02CB7 0 +OP4 E02CB8 0 +OP4 E02CB9 0 +OP4 E02CBA 0 +OP4 E02CBB 0 +OP4 E02CBC 0 +OP4 E02CBD 0 +OP4 E02CBE 0 +OP4 E02CBF 0 +OP4 E02CC0 0 +OP4 E02CC1 0 +OP4 E02CC2 0 +OP4 E02CC3 0 +OP4 E02CC4 0 +OP4 E02CC5 0 +OP4 E02CC6 0 +OP4 E02CC7 0 +OP4 E02CC8 0 +OP4 E02CC9 0 +OP4 E02CCA 0 +OP4 E02CCB 0 +OP4 E02CCC 0 +OP4 E02CCD 0 +OP4 E02CCE 0 +OP4 E02CCF 0 +OP4 E02CD0 0 +OP4 E02CD1 0 +OP4 E02CD2 0 +OP4 E02CD3 0 +OP4 E02CD4 0 +OP4 E02CD5 0 +OP4 E02CD6 0 +OP4 E02CD7 0 +OP4 E02CD8 0 +OP4 E02CD9 0 +OP4 E02CDA 0 +OP4 E02CDB 0 +OP4 E02CDC 0 +OP4 E02CDD 0 +OP4 E02CDE 0 +OP4 E02CDF 0 +OP4 E02CE0 0 +OP4 E02CE1 0 +OP4 E02CE2 0 +OP4 E02CE3 0 +OP4 E02CE4 0 +OP4 E02CE5 0 +OP4 E02CE6 0 +OP4 E02CE7 0 +OP4 E02CE8 0 +OP4 E02CE9 0 +OP4 E02CEA 0 +OP4 E02CEB 0 +OP4 E02CEC 0 +OP4 E02CED 0 +OP4 E02CEE 0 +OP4 E02CEF 0 +OP4 E02CF0 0 +OP4 E02CF1 0 +OP4 E02CF2 0 +OP4 E02CF3 0 +OP4 E02CF4 0 +OP4 E02CF5 0 +OP4 E02CF6 0 +OP4 E02CF7 0 +OP4 E02CF8 0 +OP4 E02CF9 0 +OP4 E02CFA 0 +OP4 E02CFB 0 +OP4 E02CFC 0 +OP4 E02CFD 0 +OP4 E02CFE 0 +OP4 E02CFF 0 +OP4 E02D00 0 +OP4 E02D01 0 +OP4 E02D02 0 +OP4 E02D03 0 +OP4 E02D04 0 +OP4 E02D05 0 +OP4 E02D06 0 +OP4 E02D07 0 +OP4 E02D08 0 +OP4 E02D09 0 +OP4 E02D0A 0 +OP4 E02D0B 0 +OP4 E02D0C 0 +OP4 E02D0D 0 +OP4 E02D0E 0 +OP4 E02D0F 0 +OP4 E02D10 0 +OP4 E02D11 0 +OP4 E02D12 0 +OP4 E02D13 0 +OP4 E02D14 0 +OP4 E02D15 0 +OP4 E02D16 0 +OP4 E02D17 0 +OP4 E02D18 0 +OP4 E02D19 0 +OP4 E02D1A 0 +OP4 E02D1B 0 +OP4 E02D1C 0 +OP4 E02D1D 0 +OP4 E02D1E 0 +OP4 E02D1F 0 +OP4 E02D20 0 +OP4 E02D21 0 +OP4 E02D22 0 +OP4 E02D23 0 +OP4 E02D24 0 +OP4 E02D25 0 +OP4 E02D26 0 +OP4 E02D27 0 +OP4 E02D28 0 +OP4 E02D29 0 +OP4 E02D2A 0 +OP4 E02D2B 0 +OP4 E02D2C 0 +OP4 E02D2D 0 +OP4 E02D2E 0 +OP4 E02D2F 0 +OP4 E02D30 0 +OP4 E02D31 0 +OP4 E02D32 0 +OP4 E02D33 0 +OP4 E02D34 0 +OP4 E02D35 0 +OP4 E02D36 0 +OP4 E02D37 0 +OP4 E02D38 0 +OP4 E02D39 0 +OP4 E02D3A 0 +OP4 E02D3B 0 +OP4 E02D3C 0 +OP4 E02D3D 0 +OP4 E02D3E 0 +OP4 E02D3F 0 +OP4 E02D40 0 +OP4 E02D41 0 +OP4 E02D42 0 +OP4 E02D43 0 +OP4 E02D44 0 +OP4 E02D45 0 +OP4 E02D46 0 +OP4 E02D47 0 +OP4 E02D48 0 +OP4 E02D49 0 +OP4 E02D4A 0 +OP4 E02D4B 0 +OP4 E02D4C 0 +OP4 E02D4D 0 +OP4 E02D4E 0 +OP4 E02D4F 0 +OP4 E02D50 0 +OP4 E02D51 0 +OP4 E02D52 0 +OP4 E02D53 0 +OP4 E02D54 0 +OP4 E02D55 0 +OP4 E02D56 0 +OP4 E02D57 0 +OP4 E02D58 0 +OP4 E02D59 0 +OP4 E02D5A 0 +OP4 E02D5B 0 +OP4 E02D5C 0 +OP4 E02D5D 0 +OP4 E02D5E 0 +OP4 E02D5F 0 +OP4 E02D60 0 +OP4 E02D61 0 +OP4 E02D62 0 +OP4 E02D63 0 +OP4 E02D64 0 +OP4 E02D65 0 +OP4 E02D66 0 +OP4 E02D67 0 +OP4 E02D68 0 +OP4 E02D69 0 +OP4 E02D6A 0 +OP4 E02D6B 0 +OP4 E02D6C 0 +OP4 E02D6D 0 +OP4 E02D6E 0 +OP4 E02D6F 0 +OP4 E02D70 0 +OP4 E02D71 0 +OP4 E02D72 0 +OP4 E02D73 0 +OP4 E02D74 0 +OP4 E02D75 0 +OP4 E02D76 0 +OP4 E02D77 0 +OP4 E02D78 0 +OP4 E02D79 0 +OP4 E02D7A 0 +OP4 E02D7B 0 +OP4 E02D7C 0 +OP4 E02D7D 0 +OP4 E02D7E 0 +OP4 E02D7F 0 +OP4 E02D80 0 +OP4 E02D81 0 +OP4 E02D82 0 +OP4 E02D83 0 +OP4 E02D84 0 +OP4 E02D85 0 +OP4 E02D86 0 +OP4 E02D87 0 +OP4 E02D88 0 +OP4 E02D89 0 +OP4 E02D8A 0 +OP4 E02D8B 0 +OP4 E02D8C 0 +OP4 E02D8D 0 +OP4 E02D8E 0 +OP4 E02D8F 0 +OP4 E02D90 0 +OP4 E02D91 0 +OP4 E02D92 0 +OP4 E02D93 0 +OP4 E02D94 0 +OP4 E02D95 0 +OP4 E02D96 0 +OP4 E02D97 0 +OP4 E02D98 0 +OP4 E02D99 0 +OP4 E02D9A 0 +OP4 E02D9B 0 +OP4 E02D9C 0 +OP4 E02D9D 0 +OP4 E02D9E 0 +OP4 E02D9F 0 +OP4 E02DA0 0 +OP4 E02DA1 0 +OP4 E02DA2 0 +OP4 E02DA3 0 +OP4 E02DA4 0 +OP4 E02DA5 0 +OP4 E02DA6 0 +OP4 E02DA7 0 +OP4 E02DA8 0 +OP4 E02DA9 0 +OP4 E02DAA 0 +OP4 E02DAB 0 +OP4 E02DAC 0 +OP4 E02DAD 0 +OP4 E02DAE 0 +OP4 E02DAF 0 +OP4 E02DB0 0 +OP4 E02DB1 0 +OP4 E02DB2 0 +OP4 E02DB3 0 +OP4 E02DB4 0 +OP4 E02DB5 0 +OP4 E02DB6 0 +OP4 E02DB7 0 +OP4 E02DB8 0 +OP4 E02DB9 0 +OP4 E02DBA 0 +OP4 E02DBB 0 +OP4 E02DBC 0 +OP4 E02DBD 0 +OP4 E02DBE 0 +OP4 E02DBF 0 +OP4 E02DC0 0 +OP4 E02DC1 0 +OP4 E02DC2 0 +OP4 E02DC3 0 +OP4 E02DC4 0 +OP4 E02DC5 0 +OP4 E02DC6 0 +OP4 E02DC7 0 +OP4 E02DC8 0 +OP4 E02DC9 0 +OP4 E02DCA 0 +OP4 E02DCB 0 +OP4 E02DCC 0 +OP4 E02DCD 0 +OP4 E02DCE 0 +OP4 E02DCF 0 +OP4 E02DD0 0 +OP4 E02DD1 0 +OP4 E02DD2 0 +OP4 E02DD3 0 +OP4 E02DD4 0 +OP4 E02DD5 0 +OP4 E02DD6 0 +OP4 E02DD7 0 +OP4 E02DD8 0 +OP4 E02DD9 0 +OP4 E02DDA 0 +OP4 E02DDB 0 +OP4 E02DDC 0 +OP4 E02DDD 0 +OP4 E02DDE 0 +OP4 E02DDF 0 +OP4 E02DE0 0 +OP4 E02DE1 0 +OP4 E02DE2 0 +OP4 E02DE3 0 +OP4 E02DE4 0 +OP4 E02DE5 0 +OP4 E02DE6 0 +OP4 E02DE7 0 +OP4 E02DE8 0 +OP4 E02DE9 0 +OP4 E02DEA 0 +OP4 E02DEB 0 +OP4 E02DEC 0 +OP4 E02DED 0 +OP4 E02DEE 0 +OP4 E02DEF 0 +OP4 E02DF0 0 +OP4 E02DF1 0 +OP4 E02DF2 0 +OP4 E02DF3 0 +OP4 E02DF4 0 +OP4 E02DF5 0 +OP4 E02DF6 0 +OP4 E02DF7 0 +OP4 E02DF8 0 +OP4 E02DF9 0 +OP4 E02DFA 0 +OP4 E02DFB 0 +OP4 E02DFC 0 +OP4 E02DFD 0 +OP4 E02DFE 0 +OP4 E02DFF 0 +OP4 E02E00 0 +OP4 E02E01 0 +OP4 E02E02 0 +OP4 E02E03 0 +OP4 E02E04 0 +OP4 E02E05 0 +OP4 E02E06 0 +OP4 E02E07 0 +OP4 E02E08 0 +OP4 E02E09 0 +OP4 E02E0A 0 +OP4 E02E0B 0 +OP4 E02E0C 0 +OP4 E02E0D 0 +OP4 E02E0E 0 +OP4 E02E0F 0 +OP4 E02E10 0 +OP4 E02E11 0 +OP4 E02E12 0 +OP4 E02E13 0 +OP4 E02E14 0 +OP4 E02E15 0 +OP4 E02E16 0 +OP4 E02E17 0 +OP4 E02E18 0 +OP4 E02E19 0 +OP4 E02E1A 0 +OP4 E02E1B 0 +OP4 E02E1C 0 +OP4 E02E1D 0 +OP4 E02E1E 0 +OP4 E02E1F 0 +OP4 E02E20 0 +OP4 E02E21 0 +OP4 E02E22 0 +OP4 E02E23 0 +OP4 E02E24 0 +OP4 E02E25 0 +OP4 E02E26 0 +OP4 E02E27 0 +OP4 E02E28 0 +OP4 E02E29 0 +OP4 E02E2A 0 +OP4 E02E2B 0 +OP4 E02E2C 0 +OP4 E02E2D 0 +OP4 E02E2E 0 +OP4 E02E2F 0 +OP4 E02E30 0 +OP4 E02E31 0 +OP4 E02E32 0 +OP4 E02E33 0 +OP4 E02E34 0 +OP4 E02E35 0 +OP4 E02E36 0 +OP4 E02E37 0 +OP4 E02E38 0 +OP4 E02E39 0 +OP4 E02E3A 0 +OP4 E02E3B 0 +OP4 E02E3C 0 +OP4 E02E3D 0 +OP4 E02E3E 0 +OP4 E02E3F 0 +OP4 E02E40 0 +OP4 E02E41 0 +OP4 E02E42 0 +OP4 E02E43 0 +OP4 E02E44 0 +OP4 E02E45 0 +OP4 E02E46 0 +OP4 E02E47 0 +OP4 E02E48 0 +OP4 E02E49 0 +OP4 E02E4A 0 +OP4 E02E4B 0 +OP4 E02E4C 0 +OP4 E02E4D 0 +OP4 E02E4E 0 +OP4 E02E4F 0 +OP4 E02E50 0 +OP4 E02E51 0 +OP4 E02E52 0 +OP4 E02E53 0 +OP4 E02E54 0 +OP4 E02E55 0 +OP4 E02E56 0 +OP4 E02E57 0 +OP4 E02E58 0 +OP4 E02E59 0 +OP4 E02E5A 0 +OP4 E02E5B 0 +OP4 E02E5C 0 +OP4 E02E5D 0 +OP4 E02E5E 0 +OP4 E02E5F 0 +OP4 E02E60 0 +OP4 E02E61 0 +OP4 E02E62 0 +OP4 E02E63 0 +OP4 E02E64 0 +OP4 E02E65 0 +OP4 E02E66 0 +OP4 E02E67 0 +OP4 E02E68 0 +OP4 E02E69 0 +OP4 E02E6A 0 +OP4 E02E6B 0 +OP4 E02E6C 0 +OP4 E02E6D 0 +OP4 E02E6E 0 +OP4 E02E6F 0 +OP4 E02E70 0 +OP4 E02E71 0 +OP4 E02E72 0 +OP4 E02E73 0 +OP4 E02E74 0 +OP4 E02E75 0 +OP4 E02E76 0 +OP4 E02E77 0 +OP4 E02E78 0 +OP4 E02E79 0 +OP4 E02E7A 0 +OP4 E02E7B 0 +OP4 E02E7C 0 +OP4 E02E7D 0 +OP4 E02E7E 0 +OP4 E02E7F 0 +OP4 E02E80 0 +OP4 E02E81 0 +OP4 E02E82 0 +OP4 E02E83 0 +OP4 E02E84 0 +OP4 E02E85 0 +OP4 E02E86 0 +OP4 E02E87 0 +OP4 E02E88 0 +OP4 E02E89 0 +OP4 E02E8A 0 +OP4 E02E8B 0 +OP4 E02E8C 0 +OP4 E02E8D 0 +OP4 E02E8E 0 +OP4 E02E8F 0 +OP4 E02E90 0 +OP4 E02E91 0 +OP4 E02E92 0 +OP4 E02E93 0 +OP4 E02E94 0 +OP4 E02E95 0 +OP4 E02E96 0 +OP4 E02E97 0 +OP4 E02E98 0 +OP4 E02E99 0 +OP4 E02E9A 0 +OP4 E02E9B 0 +OP4 E02E9C 0 +OP4 E02E9D 0 +OP4 E02E9E 0 +OP4 E02E9F 0 +OP4 E02EA0 0 +OP4 E02EA1 0 +OP4 E02EA2 0 +OP4 E02EA3 0 +OP4 E02EA4 0 +OP4 E02EA5 0 +OP4 E02EA6 0 +OP4 E02EA7 0 +OP4 E02EA8 0 +OP4 E02EA9 0 +OP4 E02EAA 0 +OP4 E02EAB 0 +OP4 E02EAC 0 +OP4 E02EAD 0 +OP4 E02EAE 0 +OP4 E02EAF 0 +OP4 E02EB0 0 +OP4 E02EB1 0 +OP4 E02EB2 0 +OP4 E02EB3 0 +OP4 E02EB4 0 +OP4 E02EB5 0 +OP4 E02EB6 0 +OP4 E02EB7 0 +OP4 E02EB8 0 +OP4 E02EB9 0 +OP4 E02EBA 0 +OP4 E02EBB 0 +OP4 E02EBC 0 +OP4 E02EBD 0 +OP4 E02EBE 0 +OP4 E02EBF 0 +OP4 E02EC0 0 +OP4 E02EC1 0 +OP4 E02EC2 0 +OP4 E02EC3 0 +OP4 E02EC4 0 +OP4 E02EC5 0 +OP4 E02EC6 0 +OP4 E02EC7 0 +OP4 E02EC8 0 +OP4 E02EC9 0 +OP4 E02ECA 0 +OP4 E02ECB 0 +OP4 E02ECC 0 +OP4 E02ECD 0 +OP4 E02ECE 0 +OP4 E02ECF 0 +OP4 E02ED0 0 +OP4 E02ED1 0 +OP4 E02ED2 0 +OP4 E02ED3 0 +OP4 E02ED4 0 +OP4 E02ED5 0 +OP4 E02ED6 0 +OP4 E02ED7 0 +OP4 E02ED8 0 +OP4 E02ED9 0 +OP4 E02EDA 0 +OP4 E02EDB 0 +OP4 E02EDC 0 +OP4 E02EDD 0 +OP4 E02EDE 0 +OP4 E02EDF 0 +OP4 E02EE0 0 +OP4 E02EE1 0 +OP4 E02EE2 0 +OP4 E02EE3 0 +OP4 E02EE4 0 +OP4 E02EE5 0 +OP4 E02EE6 0 +OP4 E02EE7 0 +OP4 E02EE8 0 +OP4 E02EE9 0 +OP4 E02EEA 0 +OP4 E02EEB 0 +OP4 E02EEC 0 +OP4 E02EED 0 +OP4 E02EEE 0 +OP4 E02EEF 0 +OP4 E02EF0 0 +OP4 E02EF1 0 +OP4 E02EF2 0 +OP4 E02EF3 0 +OP4 E02EF4 0 +OP4 E02EF5 0 +OP4 E02EF6 0 +OP4 E02EF7 0 +OP4 E02EF8 0 +OP4 E02EF9 0 +OP4 E02EFA 0 +OP4 E02EFB 0 +OP4 E02EFC 0 +OP4 E02EFD 0 +OP4 E02EFE 0 +OP4 E02EFF 0 +OP4 E02F00 0 +OP4 E02F01 0 +OP4 E02F02 0 +OP4 E02F03 0 +OP4 E02F04 0 +OP4 E02F05 0 +OP4 E02F06 0 +OP4 E02F07 0 +OP4 E02F08 0 +OP4 E02F09 0 +OP4 E02F0A 0 +OP4 E02F0B 0 +OP4 E02F0C 0 +OP4 E02F0D 0 +OP4 E02F0E 0 +OP4 E02F0F 0 +OP4 E02F10 0 +OP4 E02F11 0 +OP4 E02F12 0 +OP4 E02F13 0 +OP4 E02F14 0 +OP4 E02F15 0 +OP4 E02F16 0 +OP4 E02F17 0 +OP4 E02F18 0 +OP4 E02F19 0 +OP4 E02F1A 0 +OP4 E02F1B 0 +OP4 E02F1C 0 +OP4 E02F1D 0 +OP4 E02F1E 0 +OP4 E02F1F 0 +OP4 E02F20 0 +OP4 E02F21 0 +OP4 E02F22 0 +OP4 E02F23 0 +OP4 E02F24 0 +OP4 E02F25 0 +OP4 E02F26 0 +OP4 E02F27 0 +OP4 E02F28 0 +OP4 E02F29 0 +OP4 E02F2A 0 +OP4 E02F2B 0 +OP4 E02F2C 0 +OP4 E02F2D 0 +OP4 E02F2E 0 +OP4 E02F2F 0 +OP4 E02F30 0 +OP4 E02F31 0 +OP4 E02F32 0 +OP4 E02F33 0 +OP4 E02F34 0 +OP4 E02F35 0 +OP4 E02F36 0 +OP4 E02F37 0 +OP4 E02F38 0 +OP4 E02F39 0 +OP4 E02F3A 0 +OP4 E02F3B 0 +OP4 E02F3C 0 +OP4 E02F3D 0 +OP4 E02F3E 0 +OP4 E02F3F 0 +OP4 E02F40 0 +OP4 E02F41 0 +OP4 E02F42 0 +OP4 E02F43 0 +OP4 E02F44 0 +OP4 E02F45 0 +OP4 E02F46 0 +OP4 E02F47 0 +OP4 E02F48 0 +OP4 E02F49 0 +OP4 E02F4A 0 +OP4 E02F4B 0 +OP4 E02F4C 0 +OP4 E02F4D 0 +OP4 E02F4E 0 +OP4 E02F4F 0 +OP4 E02F50 0 +OP4 E02F51 0 +OP4 E02F52 0 +OP4 E02F53 0 +OP4 E02F54 0 +OP4 E02F55 0 +OP4 E02F56 0 +OP4 E02F57 0 +OP4 E02F58 0 +OP4 E02F59 0 +OP4 E02F5A 0 +OP4 E02F5B 0 +OP4 E02F5C 0 +OP4 E02F5D 0 +OP4 E02F5E 0 +OP4 E02F5F 0 +OP4 E02F60 0 +OP4 E02F61 0 +OP4 E02F62 0 +OP4 E02F63 0 +OP4 E02F64 0 +OP4 E02F65 0 +OP4 E02F66 0 +OP4 E02F67 0 +OP4 E02F68 0 +OP4 E02F69 0 +OP4 E02F6A 0 +OP4 E02F6B 0 +OP4 E02F6C 0 +OP4 E02F6D 0 +OP4 E02F6E 0 +OP4 E02F6F 0 +OP4 E02F70 0 +OP4 E02F71 0 +OP4 E02F72 0 +OP4 E02F73 0 +OP4 E02F74 0 +OP4 E02F75 0 +OP4 E02F76 0 +OP4 E02F77 0 +OP4 E02F78 0 +OP4 E02F79 0 +OP4 E02F7A 0 +OP4 E02F7B 0 +OP4 E02F7C 0 +OP4 E02F7D 0 +OP4 E02F7E 0 +OP4 E02F7F 0 +OP4 E02F80 0 +OP4 E02F81 0 +OP4 E02F82 0 +OP4 E02F83 0 +OP4 E02F84 0 +OP4 E02F85 0 +OP4 E02F86 0 +OP4 E02F87 0 +OP4 E02F88 0 +OP4 E02F89 0 +OP4 E02F8A 0 +OP4 E02F8B 0 +OP4 E02F8C 0 +OP4 E02F8D 0 +OP4 E02F8E 0 +OP4 E02F8F 0 +OP4 E02F90 0 +OP4 E02F91 0 +OP4 E02F92 0 +OP4 E02F93 0 +OP4 E02F94 0 +OP4 E02F95 0 +OP4 E02F96 0 +OP4 E02F97 0 +OP4 E02F98 0 +OP4 E02F99 0 +OP4 E02F9A 0 +OP4 E02F9B 0 +OP4 E02F9C 0 +OP4 E02F9D 0 +OP4 E02F9E 0 +OP4 E02F9F 0 +OP4 E02FA0 0 +OP4 E02FA1 0 +OP4 E02FA2 0 +OP4 E02FA3 0 +OP4 E02FA4 0 +OP4 E02FA5 0 +OP4 E02FA6 0 +OP4 E02FA7 0 +OP4 E02FA8 0 +OP4 E02FA9 0 +OP4 E02FAA 0 +OP4 E02FAB 0 +OP4 E02FAC 0 +OP4 E02FAD 0 +OP4 E02FAE 0 +OP4 E02FAF 0 +OP4 E02FB0 0 +OP4 E02FB1 0 +OP4 E02FB2 0 +OP4 E02FB3 0 +OP4 E02FB4 0 +OP4 E02FB5 0 +OP4 E02FB6 0 +OP4 E02FB7 0 +OP4 E02FB8 0 +OP4 E02FB9 0 +OP4 E02FBA 0 +OP4 E02FBB 0 +OP4 E02FBC 0 +OP4 E02FBD 0 +OP4 E02FBE 0 +OP4 E02FBF 0 +OP4 E02FC0 0 +OP4 E02FC1 0 +OP4 E02FC2 0 +OP4 E02FC3 0 +OP4 E02FC4 0 +OP4 E02FC5 0 +OP4 E02FC6 0 +OP4 E02FC7 0 +OP4 E02FC8 0 +OP4 E02FC9 0 +OP4 E02FCA 0 +OP4 E02FCB 0 +OP4 E02FCC 0 +OP4 E02FCD 0 +OP4 E02FCE 0 +OP4 E02FCF 0 +OP4 E02FD0 0 +OP4 E02FD1 0 +OP4 E02FD2 0 +OP4 E02FD3 0 +OP4 E02FD4 0 +OP4 E02FD5 0 +OP4 E02FD6 0 +OP4 E02FD7 0 +OP4 E02FD8 0 +OP4 E02FD9 0 +OP4 E02FDA 0 +OP4 E02FDB 0 +OP4 E02FDC 0 +OP4 E02FDD 0 +OP4 E02FDE 0 +OP4 E02FDF 0 +OP4 E02FE0 0 +OP4 E02FE1 0 +OP4 E02FE2 0 +OP4 E02FE3 0 +OP4 E02FE4 0 +OP4 E02FE5 0 +OP4 E02FE6 0 +OP4 E02FE7 0 +OP4 E02FE8 0 +OP4 E02FE9 0 +OP4 E02FEA 0 +OP4 E02FEB 0 +OP4 E02FEC 0 +OP4 E02FED 0 +OP4 E02FEE 0 +OP4 E02FEF 0 +OP4 E02FF0 0 +OP4 E02FF1 0 +OP4 E02FF2 0 +OP4 E02FF3 0 +OP4 E02FF4 0 +OP4 E02FF5 0 +OP4 E02FF6 0 +OP4 E02FF7 0 +OP4 E02FF8 0 +OP4 E02FF9 0 +OP4 E02FFA 0 +OP4 E02FFB 0 +OP4 E02FFC 0 +OP4 E02FFD 0 +OP4 E02FFE 0 +OP4 E02FFF 0 +OP4 E03000 0 +OP4 E03001 0 +OP4 E03002 0 +OP4 E03003 0 +OP4 E03004 0 +OP4 E03005 0 +OP4 E03006 0 +OP4 E03007 0 +OP4 E03008 0 +OP4 E03009 0 +OP4 E0300A 0 +OP4 E0300B 0 +OP4 E0300C 0 +OP4 E0300D 0 +OP4 E0300E 0 +OP4 E0300F 0 +OP4 E03010 0 +OP4 E03011 0 +OP4 E03012 0 +OP4 E03013 0 +OP4 E03014 0 +OP4 E03015 0 +OP4 E03016 0 +OP4 E03017 0 +OP4 E03018 0 +OP4 E03019 0 +OP4 E0301A 0 +OP4 E0301B 0 +OP4 E0301C 0 +OP4 E0301D 0 +OP4 E0301E 0 +OP4 E0301F 0 +OP4 E03020 0 +OP4 E03021 0 +OP4 E03022 0 +OP4 E03023 0 +OP4 E03024 0 +OP4 E03025 0 +OP4 E03026 0 +OP4 E03027 0 +OP4 E03028 0 +OP4 E03029 0 +OP4 E0302A 0 +OP4 E0302B 0 +OP4 E0302C 0 +OP4 E0302D 0 +OP4 E0302E 0 +OP4 E0302F 0 +OP4 E03030 0 +OP4 E03031 0 +OP4 E03032 0 +OP4 E03033 0 +OP4 E03034 0 +OP4 E03035 0 +OP4 E03036 0 +OP4 E03037 0 +OP4 E03038 0 +OP4 E03039 0 +OP4 E0303A 0 +OP4 E0303B 0 +OP4 E0303C 0 +OP4 E0303D 0 +OP4 E0303E 0 +OP4 E0303F 0 +OP4 E03040 0 +OP4 E03041 0 +OP4 E03042 0 +OP4 E03043 0 +OP4 E03044 0 +OP4 E03045 0 +OP4 E03046 0 +OP4 E03047 0 +OP4 E03048 0 +OP4 E03049 0 +OP4 E0304A 0 +OP4 E0304B 0 +OP4 E0304C 0 +OP4 E0304D 0 +OP4 E0304E 0 +OP4 E0304F 0 +OP4 E03050 0 +OP4 E03051 0 +OP4 E03052 0 +OP4 E03053 0 +OP4 E03054 0 +OP4 E03055 0 +OP4 E03056 0 +OP4 E03057 0 +OP4 E03058 0 +OP4 E03059 0 +OP4 E0305A 0 +OP4 E0305B 0 +OP4 E0305C 0 +OP4 E0305D 0 +OP4 E0305E 0 +OP4 E0305F 0 +OP4 E03060 0 +OP4 E03061 0 +OP4 E03062 0 +OP4 E03063 0 +OP4 E03064 0 +OP4 E03065 0 +OP4 E03066 0 +OP4 E03067 0 +OP4 E03068 0 +OP4 E03069 0 +OP4 E0306A 0 +OP4 E0306B 0 +OP4 E0306C 0 +OP4 E0306D 0 +OP4 E0306E 0 +OP4 E0306F 0 +OP4 E03070 0 +OP4 E03071 0 +OP4 E03072 0 +OP4 E03073 0 +OP4 E03074 0 +OP4 E03075 0 +OP4 E03076 0 +OP4 E03077 0 +OP4 E03078 0 +OP4 E03079 0 +OP4 E0307A 0 +OP4 E0307B 0 +OP4 E0307C 0 +OP4 E0307D 0 +OP4 E0307E 0 +OP4 E0307F 0 +OP4 E03080 0 +OP4 E03081 0 +OP4 E03082 0 +OP4 E03083 0 +OP4 E03084 0 +OP4 E03085 0 +OP4 E03086 0 +OP4 E03087 0 +OP4 E03088 0 +OP4 E03089 0 +OP4 E0308A 0 +OP4 E0308B 0 +OP4 E0308C 0 +OP4 E0308D 0 +OP4 E0308E 0 +OP4 E0308F 0 +OP4 E03090 0 +OP4 E03091 0 +OP4 E03092 0 +OP4 E03093 0 +OP4 E03094 0 +OP4 E03095 0 +OP4 E03096 0 +OP4 E03097 0 +OP4 E03098 0 +OP4 E03099 0 +OP4 E0309A 0 +OP4 E0309B 0 +OP4 E0309C 0 +OP4 E0309D 0 +OP4 E0309E 0 +OP4 E0309F 0 +OP4 E030A0 0 +OP4 E030A1 0 +OP4 E030A2 0 +OP4 E030A3 0 +OP4 E030A4 0 +OP4 E030A5 0 +OP4 E030A6 0 +OP4 E030A7 0 +OP4 E030A8 0 +OP4 E030A9 0 +OP4 E030AA 0 +OP4 E030AB 0 +OP4 E030AC 0 +OP4 E030AD 0 +OP4 E030AE 0 +OP4 E030AF 0 +OP4 E030B0 0 +OP4 E030B1 0 +OP4 E030B2 0 +OP4 E030B3 0 +OP4 E030B4 0 +OP4 E030B5 0 +OP4 E030B6 0 +OP4 E030B7 0 +OP4 E030B8 0 +OP4 E030B9 0 +OP4 E030BA 0 +OP4 E030BB 0 +OP4 E030BC 0 +OP4 E030BD 0 +OP4 E030BE 0 +OP4 E030BF 0 +OP4 E030C0 0 +OP4 E030C1 0 +OP4 E030C2 0 +OP4 E030C3 0 +OP4 E030C4 0 +OP4 E030C5 0 +OP4 E030C6 0 +OP4 E030C7 0 +OP4 E030C8 0 +OP4 E030C9 0 +OP4 E030CA 0 +OP4 E030CB 0 +OP4 E030CC 0 +OP4 E030CD 0 +OP4 E030CE 0 +OP4 E030CF 0 +OP4 E030D0 0 +OP4 E030D1 0 +OP4 E030D2 0 +OP4 E030D3 0 +OP4 E030D4 0 +OP4 E030D5 0 +OP4 E030D6 0 +OP4 E030D7 0 +OP4 E030D8 0 +OP4 E030D9 0 +OP4 E030DA 0 +OP4 E030DB 0 +OP4 E030DC 0 +OP4 E030DD 0 +OP4 E030DE 0 +OP4 E030DF 0 +OP4 E030E0 0 +OP4 E030E1 0 +OP4 E030E2 0 +OP4 E030E3 0 +OP4 E030E4 0 +OP4 E030E5 0 +OP4 E030E6 0 +OP4 E030E7 0 +OP4 E030E8 0 +OP4 E030E9 0 +OP4 E030EA 0 +OP4 E030EB 0 +OP4 E030EC 0 +OP4 E030ED 0 +OP4 E030EE 0 +OP4 E030EF 0 +OP4 E030F0 0 +OP4 E030F1 0 +OP4 E030F2 0 +OP4 E030F3 0 +OP4 E030F4 0 +OP4 E030F5 0 +OP4 E030F6 0 +OP4 E030F7 0 +OP4 E030F8 0 +OP4 E030F9 0 +OP4 E030FA 0 +OP4 E030FB 0 +OP4 E030FC 0 +OP4 E030FD 0 +OP4 E030FE 0 +OP4 E030FF 0 +OP4 E03100 0 +OP4 E03101 0 +OP4 E03102 0 +OP4 E03103 0 +OP4 E03104 0 +OP4 E03105 0 +OP4 E03106 0 +OP4 E03107 0 +OP4 E03108 0 +OP4 E03109 0 +OP4 E0310A 0 +OP4 E0310B 0 +OP4 E0310C 0 +OP4 E0310D 0 +OP4 E0310E 0 +OP4 E0310F 0 +OP4 E03110 0 +OP4 E03111 0 +OP4 E03112 0 +OP4 E03113 0 +OP4 E03114 0 +OP4 E03115 0 +OP4 E03116 0 +OP4 E03117 0 +OP4 E03118 0 +OP4 E03119 0 +OP4 E0311A 0 +OP4 E0311B 0 +OP4 E0311C 0 +OP4 E0311D 0 +OP4 E0311E 0 +OP4 E0311F 0 +OP4 E03120 0 +OP4 E03121 0 +OP4 E03122 0 +OP4 E03123 0 +OP4 E03124 0 +OP4 E03125 0 +OP4 E03126 0 +OP4 E03127 0 +OP4 E03128 0 +OP4 E03129 0 +OP4 E0312A 0 +OP4 E0312B 0 +OP4 E0312C 0 +OP4 E0312D 0 +OP4 E0312E 0 +OP4 E0312F 0 +OP4 E03130 0 +OP4 E03131 0 +OP4 E03132 0 +OP4 E03133 0 +OP4 E03134 0 +OP4 E03135 0 +OP4 E03136 0 +OP4 E03137 0 +OP4 E03138 0 +OP4 E03139 0 +OP4 E0313A 0 +OP4 E0313B 0 +OP4 E0313C 0 +OP4 E0313D 0 +OP4 E0313E 0 +OP4 E0313F 0 +OP4 E03140 0 +OP4 E03141 0 +OP4 E03142 0 +OP4 E03143 0 +OP4 E03144 0 +OP4 E03145 0 +OP4 E03146 0 +OP4 E03147 0 +OP4 E03148 0 +OP4 E03149 0 +OP4 E0314A 0 +OP4 E0314B 0 +OP4 E0314C 0 +OP4 E0314D 0 +OP4 E0314E 0 +OP4 E0314F 0 +OP4 E03150 0 +OP4 E03151 0 +OP4 E03152 0 +OP4 E03153 0 +OP4 E03154 0 +OP4 E03155 0 +OP4 E03156 0 +OP4 E03157 0 +OP4 E03158 0 +OP4 E03159 0 +OP4 E0315A 0 +OP4 E0315B 0 +OP4 E0315C 0 +OP4 E0315D 0 +OP4 E0315E 0 +OP4 E0315F 0 +OP4 E03160 0 +OP4 E03161 0 +OP4 E03162 0 +OP4 E03163 0 +OP4 E03164 0 +OP4 E03165 0 +OP4 E03166 0 +OP4 E03167 0 +OP4 E03168 0 +OP4 E03169 0 +OP4 E0316A 0 +OP4 E0316B 0 +OP4 E0316C 0 +OP4 E0316D 0 +OP4 E0316E 0 +OP4 E0316F 0 +OP4 E03170 0 +OP4 E03171 0 +OP4 E03172 0 +OP4 E03173 0 +OP4 E03174 0 +OP4 E03175 0 +OP4 E03176 0 +OP4 E03177 0 +OP4 E03178 0 +OP4 E03179 0 +OP4 E0317A 0 +OP4 E0317B 0 +OP4 E0317C 0 +OP4 E0317D 0 +OP4 E0317E 0 +OP4 E0317F 0 +OP4 E03180 0 +OP4 E03181 0 +OP4 E03182 0 +OP4 E03183 0 +OP4 E03184 0 +OP4 E03185 0 +OP4 E03186 0 +OP4 E03187 0 +OP4 E03188 0 +OP4 E03189 0 +OP4 E0318A 0 +OP4 E0318B 0 +OP4 E0318C 0 +OP4 E0318D 0 +OP4 E0318E 0 +OP4 E0318F 0 +OP4 E03190 0 +OP4 E03191 0 +OP4 E03192 0 +OP4 E03193 0 +OP4 E03194 0 +OP4 E03195 0 +OP4 E03196 0 +OP4 E03197 0 +OP4 E03198 0 +OP4 E03199 0 +OP4 E0319A 0 +OP4 E0319B 0 +OP4 E0319C 0 +OP4 E0319D 0 +OP4 E0319E 0 +OP4 E0319F 0 +OP4 E031A0 0 +OP4 E031A1 0 +OP4 E031A2 0 +OP4 E031A3 0 +OP4 E031A4 0 +OP4 E031A5 0 +OP4 E031A6 0 +OP4 E031A7 0 +OP4 E031A8 0 +OP4 E031A9 0 +OP4 E031AA 0 +OP4 E031AB 0 +OP4 E031AC 0 +OP4 E031AD 0 +OP4 E031AE 0 +OP4 E031AF 0 +OP4 E031B0 0 +OP4 E031B1 0 +OP4 E031B2 0 +OP4 E031B3 0 +OP4 E031B4 0 +OP4 E031B5 0 +OP4 E031B6 0 +OP4 E031B7 0 +OP4 E031B8 0 +OP4 E031B9 0 +OP4 E031BA 0 +OP4 E031BB 0 +OP4 E031BC 0 +OP4 E031BD 0 +OP4 E031BE 0 +OP4 E031BF 0 +OP4 E031C0 0 +OP4 E031C1 0 +OP4 E031C2 0 +OP4 E031C3 0 +OP4 E031C4 0 +OP4 E031C5 0 +OP4 E031C6 0 +OP4 E031C7 0 +OP4 E031C8 0 +OP4 E031C9 0 +OP4 E031CA 0 +OP4 E031CB 0 +OP4 E031CC 0 +OP4 E031CD 0 +OP4 E031CE 0 +OP4 E031CF 0 +OP4 E031D0 0 +OP4 E031D1 0 +OP4 E031D2 0 +OP4 E031D3 0 +OP4 E031D4 0 +OP4 E031D5 0 +OP4 E031D6 0 +OP4 E031D7 0 +OP4 E031D8 0 +OP4 E031D9 0 +OP4 E031DA 0 +OP4 E031DB 0 +OP4 E031DC 0 +OP4 E031DD 0 +OP4 E031DE 0 +OP4 E031DF 0 +OP4 E031E0 0 +OP4 E031E1 0 +OP4 E031E2 0 +OP4 E031E3 0 +OP4 E031E4 0 +OP4 E031E5 0 +OP4 E031E6 0 +OP4 E031E7 0 +OP4 E031E8 0 +OP4 E031E9 0 +OP4 E031EA 0 +OP4 E031EB 0 +OP4 E031EC 0 +OP4 E031ED 0 +OP4 E031EE 0 +OP4 E031EF 0 +OP4 E031F0 0 +OP4 E031F1 0 +OP4 E031F2 0 +OP4 E031F3 0 +OP4 E031F4 0 +OP4 E031F5 0 +OP4 E031F6 0 +OP4 E031F7 0 +OP4 E031F8 0 +OP4 E031F9 0 +OP4 E031FA 0 +OP4 E031FB 0 +OP4 E031FC 0 +OP4 E031FD 0 +OP4 E031FE 0 +OP4 E031FF 0 +OP4 E03200 0 +OP4 E03201 0 +OP4 E03202 0 +OP4 E03203 0 +OP4 E03204 0 +OP4 E03205 0 +OP4 E03206 0 +OP4 E03207 0 +OP4 E03208 0 +OP4 E03209 0 +OP4 E0320A 0 +OP4 E0320B 0 +OP4 E0320C 0 +OP4 E0320D 0 +OP4 E0320E 0 +OP4 E0320F 0 +OP4 E03210 0 +OP4 E03211 0 +OP4 E03212 0 +OP4 E03213 0 +OP4 E03214 0 +OP4 E03215 0 +OP4 E03216 0 +OP4 E03217 0 +OP4 E03218 0 +OP4 E03219 0 +OP4 E0321A 0 +OP4 E0321B 0 +OP4 E0321C 0 +OP4 E0321D 0 +OP4 E0321E 0 +OP4 E0321F 0 +OP4 E03220 0 +OP4 E03221 0 +OP4 E03222 0 +OP4 E03223 0 +OP4 E03224 0 +OP4 E03225 0 +OP4 E03226 0 +OP4 E03227 0 +OP4 E03228 0 +OP4 E03229 0 +OP4 E0322A 0 +OP4 E0322B 0 +OP4 E0322C 0 +OP4 E0322D 0 +OP4 E0322E 0 +OP4 E0322F 0 +OP4 E03230 0 +OP4 E03231 0 +OP4 E03232 0 +OP4 E03233 0 +OP4 E03234 0 +OP4 E03235 0 +OP4 E03236 0 +OP4 E03237 0 +OP4 E03238 0 +OP4 E03239 0 +OP4 E0323A 0 +OP4 E0323B 0 +OP4 E0323C 0 +OP4 E0323D 0 +OP4 E0323E 0 +OP4 E0323F 0 +OP4 E03240 0 +OP4 E03241 0 +OP4 E03242 0 +OP4 E03243 0 +OP4 E03244 0 +OP4 E03245 0 +OP4 E03246 0 +OP4 E03247 0 +OP4 E03248 0 +OP4 E03249 0 +OP4 E0324A 0 +OP4 E0324B 0 +OP4 E0324C 0 +OP4 E0324D 0 +OP4 E0324E 0 +OP4 E0324F 0 +OP4 E03250 0 +OP4 E03251 0 +OP4 E03252 0 +OP4 E03253 0 +OP4 E03254 0 +OP4 E03255 0 +OP4 E03256 0 +OP4 E03257 0 +OP4 E03258 0 +OP4 E03259 0 +OP4 E0325A 0 +OP4 E0325B 0 +OP4 E0325C 0 +OP4 E0325D 0 +OP4 E0325E 0 +OP4 E0325F 0 +OP4 E03260 0 +OP4 E03261 0 +OP4 E03262 0 +OP4 E03263 0 +OP4 E03264 0 +OP4 E03265 0 +OP4 E03266 0 +OP4 E03267 0 +OP4 E03268 0 +OP4 E03269 0 +OP4 E0326A 0 +OP4 E0326B 0 +OP4 E0326C 0 +OP4 E0326D 0 +OP4 E0326E 0 +OP4 E0326F 0 +OP4 E03270 0 +OP4 E03271 0 +OP4 E03272 0 +OP4 E03273 0 +OP4 E03274 0 +OP4 E03275 0 +OP4 E03276 0 +OP4 E03277 0 +OP4 E03278 0 +OP4 E03279 0 +OP4 E0327A 0 +OP4 E0327B 0 +OP4 E0327C 0 +OP4 E0327D 0 +OP4 E0327E 0 +OP4 E0327F 0 +OP4 E03280 0 +OP4 E03281 0 +OP4 E03282 0 +OP4 E03283 0 +OP4 E03284 0 +OP4 E03285 0 +OP4 E03286 0 +OP4 E03287 0 +OP4 E03288 0 +OP4 E03289 0 +OP4 E0328A 0 +OP4 E0328B 0 +OP4 E0328C 0 +OP4 E0328D 0 +OP4 E0328E 0 +OP4 E0328F 0 +OP4 E03290 0 +OP4 E03291 0 +OP4 E03292 0 +OP4 E03293 0 +OP4 E03294 0 +OP4 E03295 0 +OP4 E03296 0 +OP4 E03297 0 +OP4 E03298 0 +OP4 E03299 0 +OP4 E0329A 0 +OP4 E0329B 0 +OP4 E0329C 0 +OP4 E0329D 0 +OP4 E0329E 0 +OP4 E0329F 0 +OP4 E032A0 0 +OP4 E032A1 0 +OP4 E032A2 0 +OP4 E032A3 0 +OP4 E032A4 0 +OP4 E032A5 0 +OP4 E032A6 0 +OP4 E032A7 0 +OP4 E032A8 0 +OP4 E032A9 0 +OP4 E032AA 0 +OP4 E032AB 0 +OP4 E032AC 0 +OP4 E032AD 0 +OP4 E032AE 0 +OP4 E032AF 0 +OP4 E032B0 0 +OP4 E032B1 0 +OP4 E032B2 0 +OP4 E032B3 0 +OP4 E032B4 0 +OP4 E032B5 0 +OP4 E032B6 0 +OP4 E032B7 0 +OP4 E032B8 0 +OP4 E032B9 0 +OP4 E032BA 0 +OP4 E032BB 0 +OP4 E032BC 0 +OP4 E032BD 0 +OP4 E032BE 0 +OP4 E032BF 0 +OP4 E032C0 0 +OP4 E032C1 0 +OP4 E032C2 0 +OP4 E032C3 0 +OP4 E032C4 0 +OP4 E032C5 0 +OP4 E032C6 0 +OP4 E032C7 0 +OP4 E032C8 0 +OP4 E032C9 0 +OP4 E032CA 0 +OP4 E032CB 0 +OP4 E032CC 0 +OP4 E032CD 0 +OP4 E032CE 0 +OP4 E032CF 0 +OP4 E032D0 0 +OP4 E032D1 0 +OP4 E032D2 0 +OP4 E032D3 0 +OP4 E032D4 0 +OP4 E032D5 0 +OP4 E032D6 0 +OP4 E032D7 0 +OP4 E032D8 0 +OP4 E032D9 0 +OP4 E032DA 0 +OP4 E032DB 0 +OP4 E032DC 0 +OP4 E032DD 0 +OP4 E032DE 0 +OP4 E032DF 0 +OP4 E032E0 0 +OP4 E032E1 0 +OP4 E032E2 0 +OP4 E032E3 0 +OP4 E032E4 0 +OP4 E032E5 0 +OP4 E032E6 0 +OP4 E032E7 0 +OP4 E032E8 0 +OP4 E032E9 0 +OP4 E032EA 0 +OP4 E032EB 0 +OP4 E032EC 0 +OP4 E032ED 0 +OP4 E032EE 0 +OP4 E032EF 0 +OP4 E032F0 0 +OP4 E032F1 0 +OP4 E032F2 0 +OP4 E032F3 0 +OP4 E032F4 0 +OP4 E032F5 0 +OP4 E032F6 0 +OP4 E032F7 0 +OP4 E032F8 0 +OP4 E032F9 0 +OP4 E032FA 0 +OP4 E032FB 0 +OP4 E032FC 0 +OP4 E032FD 0 +OP4 E032FE 0 +OP4 E032FF 0 +OP4 E03300 0 +OP4 E03301 0 +OP4 E03302 0 +OP4 E03303 0 +OP4 E03304 0 +OP4 E03305 0 +OP4 E03306 0 +OP4 E03307 0 +OP4 E03308 0 +OP4 E03309 0 +OP4 E0330A 0 +OP4 E0330B 0 +OP4 E0330C 0 +OP4 E0330D 0 +OP4 E0330E 0 +OP4 E0330F 0 +OP4 E03310 0 +OP4 E03311 0 +OP4 E03312 0 +OP4 E03313 0 +OP4 E03314 0 +OP4 E03315 0 +OP4 E03316 0 +OP4 E03317 0 +OP4 E03318 0 +OP4 E03319 0 +OP4 E0331A 0 +OP4 E0331B 0 +OP4 E0331C 0 +OP4 E0331D 0 +OP4 E0331E 0 +OP4 E0331F 0 +OP4 E03320 0 +OP4 E03321 0 +OP4 E03322 0 +OP4 E03323 0 +OP4 E03324 0 +OP4 E03325 0 +OP4 E03326 0 +OP4 E03327 0 +OP4 E03328 0 +OP4 E03329 0 +OP4 E0332A 0 +OP4 E0332B 0 +OP4 E0332C 0 +OP4 E0332D 0 +OP4 E0332E 0 +OP4 E0332F 0 +OP4 E03330 0 +OP4 E03331 0 +OP4 E03332 0 +OP4 E03333 0 +OP4 E03334 0 +OP4 E03335 0 +OP4 E03336 0 +OP4 E03337 0 +OP4 E03338 0 +OP4 E03339 0 +OP4 E0333A 0 +OP4 E0333B 0 +OP4 E0333C 0 +OP4 E0333D 0 +OP4 E0333E 0 +OP4 E0333F 0 +OP4 E03340 0 +OP4 E03341 0 +OP4 E03342 0 +OP4 E03343 0 +OP4 E03344 0 +OP4 E03345 0 +OP4 E03346 0 +OP4 E03347 0 +OP4 E03348 0 +OP4 E03349 0 +OP4 E0334A 0 +OP4 E0334B 0 +OP4 E0334C 0 +OP4 E0334D 0 +OP4 E0334E 0 +OP4 E0334F 0 +OP4 E03350 0 +OP4 E03351 0 +OP4 E03352 0 +OP4 E03353 0 +OP4 E03354 0 +OP4 E03355 0 +OP4 E03356 0 +OP4 E03357 0 +OP4 E03358 0 +OP4 E03359 0 +OP4 E0335A 0 +OP4 E0335B 0 +OP4 E0335C 0 +OP4 E0335D 0 +OP4 E0335E 0 +OP4 E0335F 0 +OP4 E03360 0 +OP4 E03361 0 +OP4 E03362 0 +OP4 E03363 0 +OP4 E03364 0 +OP4 E03365 0 +OP4 E03366 0 +OP4 E03367 0 +OP4 E03368 0 +OP4 E03369 0 +OP4 E0336A 0 +OP4 E0336B 0 +OP4 E0336C 0 +OP4 E0336D 0 +OP4 E0336E 0 +OP4 E0336F 0 +OP4 E03370 0 +OP4 E03371 0 +OP4 E03372 0 +OP4 E03373 0 +OP4 E03374 0 +OP4 E03375 0 +OP4 E03376 0 +OP4 E03377 0 +OP4 E03378 0 +OP4 E03379 0 +OP4 E0337A 0 +OP4 E0337B 0 +OP4 E0337C 0 +OP4 E0337D 0 +OP4 E0337E 0 +OP4 E0337F 0 +OP4 E03380 0 +OP4 E03381 0 +OP4 E03382 0 +OP4 E03383 0 +OP4 E03384 0 +OP4 E03385 0 +OP4 E03386 0 +OP4 E03387 0 +OP4 E03388 0 +OP4 E03389 0 +OP4 E0338A 0 +OP4 E0338B 0 +OP4 E0338C 0 +OP4 E0338D 0 +OP4 E0338E 0 +OP4 E0338F 0 +OP4 E03390 0 +OP4 E03391 0 +OP4 E03392 0 +OP4 E03393 0 +OP4 E03394 0 +OP4 E03395 0 +OP4 E03396 0 +OP4 E03397 0 +OP4 E03398 0 +OP4 E03399 0 +OP4 E0339A 0 +OP4 E0339B 0 +OP4 E0339C 0 +OP4 E0339D 0 +OP4 E0339E 0 +OP4 E0339F 0 +OP4 E033A0 0 +OP4 E033A1 0 +OP4 E033A2 0 +OP4 E033A3 0 +OP4 E033A4 0 +OP4 E033A5 0 +OP4 E033A6 0 +OP4 E033A7 0 +OP4 E033A8 0 +OP4 E033A9 0 +OP4 E033AA 0 +OP4 E033AB 0 +OP4 E033AC 0 +OP4 E033AD 0 +OP4 E033AE 0 +OP4 E033AF 0 +OP4 E033B0 0 +OP4 E033B1 0 +OP4 E033B2 0 +OP4 E033B3 0 +OP4 E033B4 0 +OP4 E033B5 0 +OP4 E033B6 0 +OP4 E033B7 0 +OP4 E033B8 0 +OP4 E033B9 0 +OP4 E033BA 0 +OP4 E033BB 0 +OP4 E033BC 0 +OP4 E033BD 0 +OP4 E033BE 0 +OP4 E033BF 0 +OP4 E033C0 0 +OP4 E033C1 0 +OP4 E033C2 0 +OP4 E033C3 0 +OP4 E033C4 0 +OP4 E033C5 0 +OP4 E033C6 0 +OP4 E033C7 0 +OP4 E033C8 0 +OP4 E033C9 0 +OP4 E033CA 0 +OP4 E033CB 0 +OP4 E033CC 0 +OP4 E033CD 0 +OP4 E033CE 0 +OP4 E033CF 0 +OP4 E033D0 0 +OP4 E033D1 0 +OP4 E033D2 0 +OP4 E033D3 0 +OP4 E033D4 0 +OP4 E033D5 0 +OP4 E033D6 0 +OP4 E033D7 0 +OP4 E033D8 0 +OP4 E033D9 0 +OP4 E033DA 0 +OP4 E033DB 0 +OP4 E033DC 0 +OP4 E033DD 0 +OP4 E033DE 0 +OP4 E033DF 0 +OP4 E033E0 0 +OP4 E033E1 0 +OP4 E033E2 0 +OP4 E033E3 0 +OP4 E033E4 0 +OP4 E033E5 0 +OP4 E033E6 0 +OP4 E033E7 0 +OP4 E033E8 0 +OP4 E033E9 0 +OP4 E033EA 0 +OP4 E033EB 0 +OP4 E033EC 0 +OP4 E033ED 0 +OP4 E033EE 0 +OP4 E033EF 0 +OP4 E033F0 0 +OP4 E033F1 0 +OP4 E033F2 0 +OP4 E033F3 0 +OP4 E033F4 0 +OP4 E033F5 0 +OP4 E033F6 0 +OP4 E033F7 0 +OP4 E033F8 0 +OP4 E033F9 0 +OP4 E033FA 0 +OP4 E033FB 0 +OP4 E033FC 0 +OP4 E033FD 0 +OP4 E033FE 0 +OP4 E033FF 0 +OP4 E03400 0 +OP4 E03401 0 +OP4 E03402 0 +OP4 E03403 0 +OP4 E03404 0 +OP4 E03405 0 +OP4 E03406 0 +OP4 E03407 0 +OP4 E03408 0 +OP4 E03409 0 +OP4 E0340A 0 +OP4 E0340B 0 +OP4 E0340C 0 +OP4 E0340D 0 +OP4 E0340E 0 +OP4 E0340F 0 +OP4 E03410 0 +OP4 E03411 0 +OP4 E03412 0 +OP4 E03413 0 +OP4 E03414 0 +OP4 E03415 0 +OP4 E03416 0 +OP4 E03417 0 +OP4 E03418 0 +OP4 E03419 0 +OP4 E0341A 0 +OP4 E0341B 0 +OP4 E0341C 0 +OP4 E0341D 0 +OP4 E0341E 0 +OP4 E0341F 0 +OP4 E03420 0 +OP4 E03421 0 +OP4 E03422 0 +OP4 E03423 0 +OP4 E03424 0 +OP4 E03425 0 +OP4 E03426 0 +OP4 E03427 0 +OP4 E03428 0 +OP4 E03429 0 +OP4 E0342A 0 +OP4 E0342B 0 +OP4 E0342C 0 +OP4 E0342D 0 +OP4 E0342E 0 +OP4 E0342F 0 +OP4 E03430 0 +OP4 E03431 0 +OP4 E03432 0 +OP4 E03433 0 +OP4 E03434 0 +OP4 E03435 0 +OP4 E03436 0 +OP4 E03437 0 +OP4 E03438 0 +OP4 E03439 0 +OP4 E0343A 0 +OP4 E0343B 0 +OP4 E0343C 0 +OP4 E0343D 0 +OP4 E0343E 0 +OP4 E0343F 0 +OP4 E03440 0 +OP4 E03441 0 +OP4 E03442 0 +OP4 E03443 0 +OP4 E03444 0 +OP4 E03445 0 +OP4 E03446 0 +OP4 E03447 0 +OP4 E03448 0 +OP4 E03449 0 +OP4 E0344A 0 +OP4 E0344B 0 +OP4 E0344C 0 +OP4 E0344D 0 +OP4 E0344E 0 +OP4 E0344F 0 +OP4 E03450 0 +OP4 E03451 0 +OP4 E03452 0 +OP4 E03453 0 +OP4 E03454 0 +OP4 E03455 0 +OP4 E03456 0 +OP4 E03457 0 +OP4 E03458 0 +OP4 E03459 0 +OP4 E0345A 0 +OP4 E0345B 0 +OP4 E0345C 0 +OP4 E0345D 0 +OP4 E0345E 0 +OP4 E0345F 0 +OP4 E03460 0 +OP4 E03461 0 +OP4 E03462 0 +OP4 E03463 0 +OP4 E03464 0 +OP4 E03465 0 +OP4 E03466 0 +OP4 E03467 0 +OP4 E03468 0 +OP4 E03469 0 +OP4 E0346A 0 +OP4 E0346B 0 +OP4 E0346C 0 +OP4 E0346D 0 +OP4 E0346E 0 +OP4 E0346F 0 +OP4 E03470 0 +OP4 E03471 0 +OP4 E03472 0 +OP4 E03473 0 +OP4 E03474 0 +OP4 E03475 0 +OP4 E03476 0 +OP4 E03477 0 +OP4 E03478 0 +OP4 E03479 0 +OP4 E0347A 0 +OP4 E0347B 0 +OP4 E0347C 0 +OP4 E0347D 0 +OP4 E0347E 0 +OP4 E0347F 0 +OP4 E03480 0 +OP4 E03481 0 +OP4 E03482 0 +OP4 E03483 0 +OP4 E03484 0 +OP4 E03485 0 +OP4 E03486 0 +OP4 E03487 0 +OP4 E03488 0 +OP4 E03489 0 +OP4 E0348A 0 +OP4 E0348B 0 +OP4 E0348C 0 +OP4 E0348D 0 +OP4 E0348E 0 +OP4 E0348F 0 +OP4 E03490 0 +OP4 E03491 0 +OP4 E03492 0 +OP4 E03493 0 +OP4 E03494 0 +OP4 E03495 0 +OP4 E03496 0 +OP4 E03497 0 +OP4 E03498 0 +OP4 E03499 0 +OP4 E0349A 0 +OP4 E0349B 0 +OP4 E0349C 0 +OP4 E0349D 0 +OP4 E0349E 0 +OP4 E0349F 0 +OP4 E034A0 0 +OP4 E034A1 0 +OP4 E034A2 0 +OP4 E034A3 0 +OP4 E034A4 0 +OP4 E034A5 0 +OP4 E034A6 0 +OP4 E034A7 0 +OP4 E034A8 0 +OP4 E034A9 0 +OP4 E034AA 0 +OP4 E034AB 0 +OP4 E034AC 0 +OP4 E034AD 0 +OP4 E034AE 0 +OP4 E034AF 0 +OP4 E034B0 0 +OP4 E034B1 0 +OP4 E034B2 0 +OP4 E034B3 0 +OP4 E034B4 0 +OP4 E034B5 0 +OP4 E034B6 0 +OP4 E034B7 0 +OP4 E034B8 0 +OP4 E034B9 0 +OP4 E034BA 0 +OP4 E034BB 0 +OP4 E034BC 0 +OP4 E034BD 0 +OP4 E034BE 0 +OP4 E034BF 0 +OP4 E034C0 0 +OP4 E034C1 0 +OP4 E034C2 0 +OP4 E034C3 0 +OP4 E034C4 0 +OP4 E034C5 0 +OP4 E034C6 0 +OP4 E034C7 0 +OP4 E034C8 0 +OP4 E034C9 0 +OP4 E034CA 0 +OP4 E034CB 0 +OP4 E034CC 0 +OP4 E034CD 0 +OP4 E034CE 0 +OP4 E034CF 0 +OP4 E034D0 0 +OP4 E034D1 0 +OP4 E034D2 0 +OP4 E034D3 0 +OP4 E034D4 0 +OP4 E034D5 0 +OP4 E034D6 0 +OP4 E034D7 0 +OP4 E034D8 0 +OP4 E034D9 0 +OP4 E034DA 0 +OP4 E034DB 0 +OP4 E034DC 0 +OP4 E034DD 0 +OP4 E034DE 0 +OP4 E034DF 0 +OP4 E034E0 0 +OP4 E034E1 0 +OP4 E034E2 0 +OP4 E034E3 0 +OP4 E034E4 0 +OP4 E034E5 0 +OP4 E034E6 0 +OP4 E034E7 0 +OP4 E034E8 0 +OP4 E034E9 0 +OP4 E034EA 0 +OP4 E034EB 0 +OP4 E034EC 0 +OP4 E034ED 0 +OP4 E034EE 0 +OP4 E034EF 0 +OP4 E034F0 0 +OP4 E034F1 0 +OP4 E034F2 0 +OP4 E034F3 0 +OP4 E034F4 0 +OP4 E034F5 0 +OP4 E034F6 0 +OP4 E034F7 0 +OP4 E034F8 0 +OP4 E034F9 0 +OP4 E034FA 0 +OP4 E034FB 0 +OP4 E034FC 0 +OP4 E034FD 0 +OP4 E034FE 0 +OP4 E034FF 0 +OP4 E03500 0 +OP4 E03501 0 +OP4 E03502 0 +OP4 E03503 0 +OP4 E03504 0 +OP4 E03505 0 +OP4 E03506 0 +OP4 E03507 0 +OP4 E03508 0 +OP4 E03509 0 +OP4 E0350A 0 +OP4 E0350B 0 +OP4 E0350C 0 +OP4 E0350D 0 +OP4 E0350E 0 +OP4 E0350F 0 +OP4 E03510 0 +OP4 E03511 0 +OP4 E03512 0 +OP4 E03513 0 +OP4 E03514 0 +OP4 E03515 0 +OP4 E03516 0 +OP4 E03517 0 +OP4 E03518 0 +OP4 E03519 0 +OP4 E0351A 0 +OP4 E0351B 0 +OP4 E0351C 0 +OP4 E0351D 0 +OP4 E0351E 0 +OP4 E0351F 0 +OP4 E03520 0 +OP4 E03521 0 +OP4 E03522 0 +OP4 E03523 0 +OP4 E03524 0 +OP4 E03525 0 +OP4 E03526 0 +OP4 E03527 0 +OP4 E03528 0 +OP4 E03529 0 +OP4 E0352A 0 +OP4 E0352B 0 +OP4 E0352C 0 +OP4 E0352D 0 +OP4 E0352E 0 +OP4 E0352F 0 +OP4 E03530 0 +OP4 E03531 0 +OP4 E03532 0 +OP4 E03533 0 +OP4 E03534 0 +OP4 E03535 0 +OP4 E03536 0 +OP4 E03537 0 +OP4 E03538 0 +OP4 E03539 0 +OP4 E0353A 0 +OP4 E0353B 0 +OP4 E0353C 0 +OP4 E0353D 0 +OP4 E0353E 0 +OP4 E0353F 0 +OP4 E03540 0 +OP4 E03541 0 +OP4 E03542 0 +OP4 E03543 0 +OP4 E03544 0 +OP4 E03545 0 +OP4 E03546 0 +OP4 E03547 0 +OP4 E03548 0 +OP4 E03549 0 +OP4 E0354A 0 +OP4 E0354B 0 +OP4 E0354C 0 +OP4 E0354D 0 +OP4 E0354E 0 +OP4 E0354F 0 +OP4 E03550 0 +OP4 E03551 0 +OP4 E03552 0 +OP4 E03553 0 +OP4 E03554 0 +OP4 E03555 0 +OP4 E03556 0 +OP4 E03557 0 +OP4 E03558 0 +OP4 E03559 0 +OP4 E0355A 0 +OP4 E0355B 0 +OP4 E0355C 0 +OP4 E0355D 0 +OP4 E0355E 0 +OP4 E0355F 0 +OP4 E03560 0 +OP4 E03561 0 +OP4 E03562 0 +OP4 E03563 0 +OP4 E03564 0 +OP4 E03565 0 +OP4 E03566 0 +OP4 E03567 0 +OP4 E03568 0 +OP4 E03569 0 +OP4 E0356A 0 +OP4 E0356B 0 +OP4 E0356C 0 +OP4 E0356D 0 +OP4 E0356E 0 +OP4 E0356F 0 +OP4 E03570 0 +OP4 E03571 0 +OP4 E03572 0 +OP4 E03573 0 +OP4 E03574 0 +OP4 E03575 0 +OP4 E03576 0 +OP4 E03577 0 +OP4 E03578 0 +OP4 E03579 0 +OP4 E0357A 0 +OP4 E0357B 0 +OP4 E0357C 0 +OP4 E0357D 0 +OP4 E0357E 0 +OP4 E0357F 0 +OP4 E03580 0 +OP4 E03581 0 +OP4 E03582 0 +OP4 E03583 0 +OP4 E03584 0 +OP4 E03585 0 +OP4 E03586 0 +OP4 E03587 0 +OP4 E03588 0 +OP4 E03589 0 +OP4 E0358A 0 +OP4 E0358B 0 +OP4 E0358C 0 +OP4 E0358D 0 +OP4 E0358E 0 +OP4 E0358F 0 +OP4 E03590 0 +OP4 E03591 0 +OP4 E03592 0 +OP4 E03593 0 +OP4 E03594 0 +OP4 E03595 0 +OP4 E03596 0 +OP4 E03597 0 +OP4 E03598 0 +OP4 E03599 0 +OP4 E0359A 0 +OP4 E0359B 0 +OP4 E0359C 0 +OP4 E0359D 0 +OP4 E0359E 0 +OP4 E0359F 0 +OP4 E035A0 0 +OP4 E035A1 0 +OP4 E035A2 0 +OP4 E035A3 0 +OP4 E035A4 0 +OP4 E035A5 0 +OP4 E035A6 0 +OP4 E035A7 0 +OP4 E035A8 0 +OP4 E035A9 0 +OP4 E035AA 0 +OP4 E035AB 0 +OP4 E035AC 0 +OP4 E035AD 0 +OP4 E035AE 0 +OP4 E035AF 0 +OP4 E035B0 0 +OP4 E035B1 0 +OP4 E035B2 0 +OP4 E035B3 0 +OP4 E035B4 0 +OP4 E035B5 0 +OP4 E035B6 0 +OP4 E035B7 0 +OP4 E035B8 0 +OP4 E035B9 0 +OP4 E035BA 0 +OP4 E035BB 0 +OP4 E035BC 0 +OP4 E035BD 0 +OP4 E035BE 0 +OP4 E035BF 0 +OP4 E035C0 0 +OP4 E035C1 0 +OP4 E035C2 0 +OP4 E035C3 0 +OP4 E035C4 0 +OP4 E035C5 0 +OP4 E035C6 0 +OP4 E035C7 0 +OP4 E035C8 0 +OP4 E035C9 0 +OP4 E035CA 0 +OP4 E035CB 0 +OP4 E035CC 0 +OP4 E035CD 0 +OP4 E035CE 0 +OP4 E035CF 0 +OP4 E035D0 0 +OP4 E035D1 0 +OP4 E035D2 0 +OP4 E035D3 0 +OP4 E035D4 0 +OP4 E035D5 0 +OP4 E035D6 0 +OP4 E035D7 0 +OP4 E035D8 0 +OP4 E035D9 0 +OP4 E035DA 0 +OP4 E035DB 0 +OP4 E035DC 0 +OP4 E035DD 0 +OP4 E035DE 0 +OP4 E035DF 0 +OP4 E035E0 0 +OP4 E035E1 0 +OP4 E035E2 0 +OP4 E035E3 0 +OP4 E035E4 0 +OP4 E035E5 0 +OP4 E035E6 0 +OP4 E035E7 0 +OP4 E035E8 0 +OP4 E035E9 0 +OP4 E035EA 0 +OP4 E035EB 0 +OP4 E035EC 0 +OP4 E035ED 0 +OP4 E035EE 0 +OP4 E035EF 0 +OP4 E035F0 0 +OP4 E035F1 0 +OP4 E035F2 0 +OP4 E035F3 0 +OP4 E035F4 0 +OP4 E035F5 0 +OP4 E035F6 0 +OP4 E035F7 0 +OP4 E035F8 0 +OP4 E035F9 0 +OP4 E035FA 0 +OP4 E035FB 0 +OP4 E035FC 0 +OP4 E035FD 0 +OP4 E035FE 0 +OP4 E035FF 0 +OP4 E03600 0 +OP4 E03601 0 +OP4 E03602 0 +OP4 E03603 0 +OP4 E03604 0 +OP4 E03605 0 +OP4 E03606 0 +OP4 E03607 0 +OP4 E03608 0 +OP4 E03609 0 +OP4 E0360A 0 +OP4 E0360B 0 +OP4 E0360C 0 +OP4 E0360D 0 +OP4 E0360E 0 +OP4 E0360F 0 +OP4 E03610 0 +OP4 E03611 0 +OP4 E03612 0 +OP4 E03613 0 +OP4 E03614 0 +OP4 E03615 0 +OP4 E03616 0 +OP4 E03617 0 +OP4 E03618 0 +OP4 E03619 0 +OP4 E0361A 0 +OP4 E0361B 0 +OP4 E0361C 0 +OP4 E0361D 0 +OP4 E0361E 0 +OP4 E0361F 0 +OP4 E03620 0 +OP4 E03621 0 +OP4 E03622 0 +OP4 E03623 0 +OP4 E03624 0 +OP4 E03625 0 +OP4 E03626 0 +OP4 E03627 0 +OP4 E03628 0 +OP4 E03629 0 +OP4 E0362A 0 +OP4 E0362B 0 +OP4 E0362C 0 +OP4 E0362D 0 +OP4 E0362E 0 +OP4 E0362F 0 +OP4 E03630 0 +OP4 E03631 0 +OP4 E03632 0 +OP4 E03633 0 +OP4 E03634 0 +OP4 E03635 0 +OP4 E03636 0 +OP4 E03637 0 +OP4 E03638 0 +OP4 E03639 0 +OP4 E0363A 0 +OP4 E0363B 0 +OP4 E0363C 0 +OP4 E0363D 0 +OP4 E0363E 0 +OP4 E0363F 0 +OP4 E03640 0 +OP4 E03641 0 +OP4 E03642 0 +OP4 E03643 0 +OP4 E03644 0 +OP4 E03645 0 +OP4 E03646 0 +OP4 E03647 0 +OP4 E03648 0 +OP4 E03649 0 +OP4 E0364A 0 +OP4 E0364B 0 +OP4 E0364C 0 +OP4 E0364D 0 +OP4 E0364E 0 +OP4 E0364F 0 +OP4 E03650 0 +OP4 E03651 0 +OP4 E03652 0 +OP4 E03653 0 +OP4 E03654 0 +OP4 E03655 0 +OP4 E03656 0 +OP4 E03657 0 +OP4 E03658 0 +OP4 E03659 0 +OP4 E0365A 0 +OP4 E0365B 0 +OP4 E0365C 0 +OP4 E0365D 0 +OP4 E0365E 0 +OP4 E0365F 0 +OP4 E03660 0 +OP4 E03661 0 +OP4 E03662 0 +OP4 E03663 0 +OP4 E03664 0 +OP4 E03665 0 +OP4 E03666 0 +OP4 E03667 0 +OP4 E03668 0 +OP4 E03669 0 +OP4 E0366A 0 +OP4 E0366B 0 +OP4 E0366C 0 +OP4 E0366D 0 +OP4 E0366E 0 +OP4 E0366F 0 +OP4 E03670 0 +OP4 E03671 0 +OP4 E03672 0 +OP4 E03673 0 +OP4 E03674 0 +OP4 E03675 0 +OP4 E03676 0 +OP4 E03677 0 +OP4 E03678 0 +OP4 E03679 0 +OP4 E0367A 0 +OP4 E0367B 0 +OP4 E0367C 0 +OP4 E0367D 0 +OP4 E0367E 0 +OP4 E0367F 0 +OP4 E03680 0 +OP4 E03681 0 +OP4 E03682 0 +OP4 E03683 0 +OP4 E03684 0 +OP4 E03685 0 +OP4 E03686 0 +OP4 E03687 0 +OP4 E03688 0 +OP4 E03689 0 +OP4 E0368A 0 +OP4 E0368B 0 +OP4 E0368C 0 +OP4 E0368D 0 +OP4 E0368E 0 +OP4 E0368F 0 +OP4 E03690 0 +OP4 E03691 0 +OP4 E03692 0 +OP4 E03693 0 +OP4 E03694 0 +OP4 E03695 0 +OP4 E03696 0 +OP4 E03697 0 +OP4 E03698 0 +OP4 E03699 0 +OP4 E0369A 0 +OP4 E0369B 0 +OP4 E0369C 0 +OP4 E0369D 0 +OP4 E0369E 0 +OP4 E0369F 0 +OP4 E036A0 0 +OP4 E036A1 0 +OP4 E036A2 0 +OP4 E036A3 0 +OP4 E036A4 0 +OP4 E036A5 0 +OP4 E036A6 0 +OP4 E036A7 0 +OP4 E036A8 0 +OP4 E036A9 0 +OP4 E036AA 0 +OP4 E036AB 0 +OP4 E036AC 0 +OP4 E036AD 0 +OP4 E036AE 0 +OP4 E036AF 0 +OP4 E036B0 0 +OP4 E036B1 0 +OP4 E036B2 0 +OP4 E036B3 0 +OP4 E036B4 0 +OP4 E036B5 0 +OP4 E036B6 0 +OP4 E036B7 0 +OP4 E036B8 0 +OP4 E036B9 0 +OP4 E036BA 0 +OP4 E036BB 0 +OP4 E036BC 0 +OP4 E036BD 0 +OP4 E036BE 0 +OP4 E036BF 0 +OP4 E036C0 0 +OP4 E036C1 0 +OP4 E036C2 0 +OP4 E036C3 0 +OP4 E036C4 0 +OP4 E036C5 0 +OP4 E036C6 0 +OP4 E036C7 0 +OP4 E036C8 0 +OP4 E036C9 0 +OP4 E036CA 0 +OP4 E036CB 0 +OP4 E036CC 0 +OP4 E036CD 0 +OP4 E036CE 0 +OP4 E036CF 0 +OP4 E036D0 0 +OP4 E036D1 0 +OP4 E036D2 0 +OP4 E036D3 0 +OP4 E036D4 0 +OP4 E036D5 0 +OP4 E036D6 0 +OP4 E036D7 0 +OP4 E036D8 0 +OP4 E036D9 0 +OP4 E036DA 0 +OP4 E036DB 0 +OP4 E036DC 0 +OP4 E036DD 0 +OP4 E036DE 0 +OP4 E036DF 0 +OP4 E036E0 0 +OP4 E036E1 0 +OP4 E036E2 0 +OP4 E036E3 0 +OP4 E036E4 0 +OP4 E036E5 0 +OP4 E036E6 0 +OP4 E036E7 0 +OP4 E036E8 0 +OP4 E036E9 0 +OP4 E036EA 0 +OP4 E036EB 0 +OP4 E036EC 0 +OP4 E036ED 0 +OP4 E036EE 0 +OP4 E036EF 0 +OP4 E036F0 0 +OP4 E036F1 0 +OP4 E036F2 0 +OP4 E036F3 0 +OP4 E036F4 0 +OP4 E036F5 0 +OP4 E036F6 0 +OP4 E036F7 0 +OP4 E036F8 0 +OP4 E036F9 0 +OP4 E036FA 0 +OP4 E036FB 0 +OP4 E036FC 0 +OP4 E036FD 0 +OP4 E036FE 0 +OP4 E036FF 0 +OP4 E03700 0 +OP4 E03701 0 +OP4 E03702 0 +OP4 E03703 0 +OP4 E03704 0 +OP4 E03705 0 +OP4 E03706 0 +OP4 E03707 0 +OP4 E03708 0 +OP4 E03709 0 +OP4 E0370A 0 +OP4 E0370B 0 +OP4 E0370C 0 +OP4 E0370D 0 +OP4 E0370E 0 +OP4 E0370F 0 +OP4 E03710 0 +OP4 E03711 0 +OP4 E03712 0 +OP4 E03713 0 +OP4 E03714 0 +OP4 E03715 0 +OP4 E03716 0 +OP4 E03717 0 +OP4 E03718 0 +OP4 E03719 0 +OP4 E0371A 0 +OP4 E0371B 0 +OP4 E0371C 0 +OP4 E0371D 0 +OP4 E0371E 0 +OP4 E0371F 0 +OP4 E03720 0 +OP4 E03721 0 +OP4 E03722 0 +OP4 E03723 0 +OP4 E03724 0 +OP4 E03725 0 +OP4 E03726 0 +OP4 E03727 0 +OP4 E03728 0 +OP4 E03729 0 +OP4 E0372A 0 +OP4 E0372B 0 +OP4 E0372C 0 +OP4 E0372D 0 +OP4 E0372E 0 +OP4 E0372F 0 +OP4 E03730 0 +OP4 E03731 0 +OP4 E03732 0 +OP4 E03733 0 +OP4 E03734 0 +OP4 E03735 0 +OP4 E03736 0 +OP4 E03737 0 +OP4 E03738 0 +OP4 E03739 0 +OP4 E0373A 0 +OP4 E0373B 0 +OP4 E0373C 0 +OP4 E0373D 0 +OP4 E0373E 0 +OP4 E0373F 0 +OP4 E03740 0 +OP4 E03741 0 +OP4 E03742 0 +OP4 E03743 0 +OP4 E03744 0 +OP4 E03745 0 +OP4 E03746 0 +OP4 E03747 0 +OP4 E03748 0 +OP4 E03749 0 +OP4 E0374A 0 +OP4 E0374B 0 +OP4 E0374C 0 +OP4 E0374D 0 +OP4 E0374E 0 +OP4 E0374F 0 +OP4 E03750 0 +OP4 E03751 0 +OP4 E03752 0 +OP4 E03753 0 +OP4 E03754 0 +OP4 E03755 0 +OP4 E03756 0 +OP4 E03757 0 +OP4 E03758 0 +OP4 E03759 0 +OP4 E0375A 0 +OP4 E0375B 0 +OP4 E0375C 0 +OP4 E0375D 0 +OP4 E0375E 0 +OP4 E0375F 0 +OP4 E03760 0 +OP4 E03761 0 +OP4 E03762 0 +OP4 E03763 0 +OP4 E03764 0 +OP4 E03765 0 +OP4 E03766 0 +OP4 E03767 0 +OP4 E03768 0 +OP4 E03769 0 +OP4 E0376A 0 +OP4 E0376B 0 +OP4 E0376C 0 +OP4 E0376D 0 +OP4 E0376E 0 +OP4 E0376F 0 +OP4 E03770 0 +OP4 E03771 0 +OP4 E03772 0 +OP4 E03773 0 +OP4 E03774 0 +OP4 E03775 0 +OP4 E03776 0 +OP4 E03777 0 +OP4 E03778 0 +OP4 E03779 0 +OP4 E0377A 0 +OP4 E0377B 0 +OP4 E0377C 0 +OP4 E0377D 0 +OP4 E0377E 0 +OP4 E0377F 0 +OP4 E03780 0 +OP4 E03781 0 +OP4 E03782 0 +OP4 E03783 0 +OP4 E03784 0 +OP4 E03785 0 +OP4 E03786 0 +OP4 E03787 0 +OP4 E03788 0 +OP4 E03789 0 +OP4 E0378A 0 +OP4 E0378B 0 +OP4 E0378C 0 +OP4 E0378D 0 +OP4 E0378E 0 +OP4 E0378F 0 +OP4 E03790 0 +OP4 E03791 0 +OP4 E03792 0 +OP4 E03793 0 +OP4 E03794 0 +OP4 E03795 0 +OP4 E03796 0 +OP4 E03797 0 +OP4 E03798 0 +OP4 E03799 0 +OP4 E0379A 0 +OP4 E0379B 0 +OP4 E0379C 0 +OP4 E0379D 0 +OP4 E0379E 0 +OP4 E0379F 0 +OP4 E037A0 0 +OP4 E037A1 0 +OP4 E037A2 0 +OP4 E037A3 0 +OP4 E037A4 0 +OP4 E037A5 0 +OP4 E037A6 0 +OP4 E037A7 0 +OP4 E037A8 0 +OP4 E037A9 0 +OP4 E037AA 0 +OP4 E037AB 0 +OP4 E037AC 0 +OP4 E037AD 0 +OP4 E037AE 0 +OP4 E037AF 0 +OP4 E037B0 0 +OP4 E037B1 0 +OP4 E037B2 0 +OP4 E037B3 0 +OP4 E037B4 0 +OP4 E037B5 0 +OP4 E037B6 0 +OP4 E037B7 0 +OP4 E037B8 0 +OP4 E037B9 0 +OP4 E037BA 0 +OP4 E037BB 0 +OP4 E037BC 0 +OP4 E037BD 0 +OP4 E037BE 0 +OP4 E037BF 0 +OP4 E037C0 0 +OP4 E037C1 0 +OP4 E037C2 0 +OP4 E037C3 0 +OP4 E037C4 0 +OP4 E037C5 0 +OP4 E037C6 0 +OP4 E037C7 0 +OP4 E037C8 0 +OP4 E037C9 0 +OP4 E037CA 0 +OP4 E037CB 0 +OP4 E037CC 0 +OP4 E037CD 0 +OP4 E037CE 0 +OP4 E037CF 0 +OP4 E037D0 0 +OP4 E037D1 0 +OP4 E037D2 0 +OP4 E037D3 0 +OP4 E037D4 0 +OP4 E037D5 0 +OP4 E037D6 0 +OP4 E037D7 0 +OP4 E037D8 0 +OP4 E037D9 0 +OP4 E037DA 0 +OP4 E037DB 0 +OP4 E037DC 0 +OP4 E037DD 0 +OP4 E037DE 0 +OP4 E037DF 0 +OP4 E037E0 0 +OP4 E037E1 0 +OP4 E037E2 0 +OP4 E037E3 0 +OP4 E037E4 0 +OP4 E037E5 0 +OP4 E037E6 0 +OP4 E037E7 0 +OP4 E037E8 0 +OP4 E037E9 0 +OP4 E037EA 0 +OP4 E037EB 0 +OP4 E037EC 0 +OP4 E037ED 0 +OP4 E037EE 0 +OP4 E037EF 0 +OP4 E037F0 0 +OP4 E037F1 0 +OP4 E037F2 0 +OP4 E037F3 0 +OP4 E037F4 0 +OP4 E037F5 0 +OP4 E037F6 0 +OP4 E037F7 0 +OP4 E037F8 0 +OP4 E037F9 0 +OP4 E037FA 0 +OP4 E037FB 0 +OP4 E037FC 0 +OP4 E037FD 0 +OP4 E037FE 0 +OP4 E037FF 0 +OP4 E03800 0 +OP4 E03801 0 +OP4 E03802 0 +OP4 E03803 0 +OP4 E03804 0 +OP4 E03805 0 +OP4 E03806 0 +OP4 E03807 0 +OP4 E03808 0 +OP4 E03809 0 +OP4 E0380A 0 +OP4 E0380B 0 +OP4 E0380C 0 +OP4 E0380D 0 +OP4 E0380E 0 +OP4 E0380F 0 +OP4 E03810 0 +OP4 E03811 0 +OP4 E03812 0 +OP4 E03813 0 +OP4 E03814 0 +OP4 E03815 0 +OP4 E03816 0 +OP4 E03817 0 +OP4 E03818 0 +OP4 E03819 0 +OP4 E0381A 0 +OP4 E0381B 0 +OP4 E0381C 0 +OP4 E0381D 0 +OP4 E0381E 0 +OP4 E0381F 0 +OP4 E03820 0 +OP4 E03821 0 +OP4 E03822 0 +OP4 E03823 0 +OP4 E03824 0 +OP4 E03825 0 +OP4 E03826 0 +OP4 E03827 0 +OP4 E03828 0 +OP4 E03829 0 +OP4 E0382A 0 +OP4 E0382B 0 +OP4 E0382C 0 +OP4 E0382D 0 +OP4 E0382E 0 +OP4 E0382F 0 +OP4 E03830 0 +OP4 E03831 0 +OP4 E03832 0 +OP4 E03833 0 +OP4 E03834 0 +OP4 E03835 0 +OP4 E03836 0 +OP4 E03837 0 +OP4 E03838 0 +OP4 E03839 0 +OP4 E0383A 0 +OP4 E0383B 0 +OP4 E0383C 0 +OP4 E0383D 0 +OP4 E0383E 0 +OP4 E0383F 0 +OP4 E03840 0 +OP4 E03841 0 +OP4 E03842 0 +OP4 E03843 0 +OP4 E03844 0 +OP4 E03845 0 +OP4 E03846 0 +OP4 E03847 0 +OP4 E03848 0 +OP4 E03849 0 +OP4 E0384A 0 +OP4 E0384B 0 +OP4 E0384C 0 +OP4 E0384D 0 +OP4 E0384E 0 +OP4 E0384F 0 +OP4 E03850 0 +OP4 E03851 0 +OP4 E03852 0 +OP4 E03853 0 +OP4 E03854 0 +OP4 E03855 0 +OP4 E03856 0 +OP4 E03857 0 +OP4 E03858 0 +OP4 E03859 0 +OP4 E0385A 0 +OP4 E0385B 0 +OP4 E0385C 0 +OP4 E0385D 0 +OP4 E0385E 0 +OP4 E0385F 0 +OP4 E03860 0 +OP4 E03861 0 +OP4 E03862 0 +OP4 E03863 0 +OP4 E03864 0 +OP4 E03865 0 +OP4 E03866 0 +OP4 E03867 0 +OP4 E03868 0 +OP4 E03869 0 +OP4 E0386A 0 +OP4 E0386B 0 +OP4 E0386C 0 +OP4 E0386D 0 +OP4 E0386E 0 +OP4 E0386F 0 +OP4 E03870 0 +OP4 E03871 0 +OP4 E03872 0 +OP4 E03873 0 +OP4 E03874 0 +OP4 E03875 0 +OP4 E03876 0 +OP4 E03877 0 +OP4 E03878 0 +OP4 E03879 0 +OP4 E0387A 0 +OP4 E0387B 0 +OP4 E0387C 0 +OP4 E0387D 0 +OP4 E0387E 0 +OP4 E0387F 0 +OP4 E03880 0 +OP4 E03881 0 +OP4 E03882 0 +OP4 E03883 0 +OP4 E03884 0 +OP4 E03885 0 +OP4 E03886 0 +OP4 E03887 0 +OP4 E03888 0 +OP4 E03889 0 +OP4 E0388A 0 +OP4 E0388B 0 +OP4 E0388C 0 +OP4 E0388D 0 +OP4 E0388E 0 +OP4 E0388F 0 +OP4 E03890 0 +OP4 E03891 0 +OP4 E03892 0 +OP4 E03893 0 +OP4 E03894 0 +OP4 E03895 0 +OP4 E03896 0 +OP4 E03897 0 +OP4 E03898 0 +OP4 E03899 0 +OP4 E0389A 0 +OP4 E0389B 0 +OP4 E0389C 0 +OP4 E0389D 0 +OP4 E0389E 0 +OP4 E0389F 0 +OP4 E038A0 0 +OP4 E038A1 0 +OP4 E038A2 0 +OP4 E038A3 0 +OP4 E038A4 0 +OP4 E038A5 0 +OP4 E038A6 0 +OP4 E038A7 0 +OP4 E038A8 0 +OP4 E038A9 0 +OP4 E038AA 0 +OP4 E038AB 0 +OP4 E038AC 0 +OP4 E038AD 0 +OP4 E038AE 0 +OP4 E038AF 0 +OP4 E038B0 0 +OP4 E038B1 0 +OP4 E038B2 0 +OP4 E038B3 0 +OP4 E038B4 0 +OP4 E038B5 0 +OP4 E038B6 0 +OP4 E038B7 0 +OP4 E038B8 0 +OP4 E038B9 0 +OP4 E038BA 0 +OP4 E038BB 0 +OP4 E038BC 0 +OP4 E038BD 0 +OP4 E038BE 0 +OP4 E038BF 0 +OP4 E038C0 0 +OP4 E038C1 0 +OP4 E038C2 0 +OP4 E038C3 0 +OP4 E038C4 0 +OP4 E038C5 0 +OP4 E038C6 0 +OP4 E038C7 0 +OP4 E038C8 0 +OP4 E038C9 0 +OP4 E038CA 0 +OP4 E038CB 0 +OP4 E038CC 0 +OP4 E038CD 0 +OP4 E038CE 0 +OP4 E038CF 0 +OP4 E038D0 0 +OP4 E038D1 0 +OP4 E038D2 0 +OP4 E038D3 0 +OP4 E038D4 0 +OP4 E038D5 0 +OP4 E038D6 0 +OP4 E038D7 0 +OP4 E038D8 0 +OP4 E038D9 0 +OP4 E038DA 0 +OP4 E038DB 0 +OP4 E038DC 0 +OP4 E038DD 0 +OP4 E038DE 0 +OP4 E038DF 0 +OP4 E038E0 0 +OP4 E038E1 0 +OP4 E038E2 0 +OP4 E038E3 0 +OP4 E038E4 0 +OP4 E038E5 0 +OP4 E038E6 0 +OP4 E038E7 0 +OP4 E038E8 0 +OP4 E038E9 0 +OP4 E038EA 0 +OP4 E038EB 0 +OP4 E038EC 0 +OP4 E038ED 0 +OP4 E038EE 0 +OP4 E038EF 0 +OP4 E038F0 0 +OP4 E038F1 0 +OP4 E038F2 0 +OP4 E038F3 0 +OP4 E038F4 0 +OP4 E038F5 0 +OP4 E038F6 0 +OP4 E038F7 0 +OP4 E038F8 0 +OP4 E038F9 0 +OP4 E038FA 0 +OP4 E038FB 0 +OP4 E038FC 0 +OP4 E038FD 0 +OP4 E038FE 0 +OP4 E038FF 0 +OP4 E03900 0 +OP4 E03901 0 +OP4 E03902 0 +OP4 E03903 0 +OP4 E03904 0 +OP4 E03905 0 +OP4 E03906 0 +OP4 E03907 0 +OP4 E03908 0 +OP4 E03909 0 +OP4 E0390A 0 +OP4 E0390B 0 +OP4 E0390C 0 +OP4 E0390D 0 +OP4 E0390E 0 +OP4 E0390F 0 +OP4 E03910 0 +OP4 E03911 0 +OP4 E03912 0 +OP4 E03913 0 +OP4 E03914 0 +OP4 E03915 0 +OP4 E03916 0 +OP4 E03917 0 +OP4 E03918 0 +OP4 E03919 0 +OP4 E0391A 0 +OP4 E0391B 0 +OP4 E0391C 0 +OP4 E0391D 0 +OP4 E0391E 0 +OP4 E0391F 0 +OP4 E03920 0 +OP4 E03921 0 +OP4 E03922 0 +OP4 E03923 0 +OP4 E03924 0 +OP4 E03925 0 +OP4 E03926 0 +OP4 E03927 0 +OP4 E03928 0 +OP4 E03929 0 +OP4 E0392A 0 +OP4 E0392B 0 +OP4 E0392C 0 +OP4 E0392D 0 +OP4 E0392E 0 +OP4 E0392F 0 +OP4 E03930 0 +OP4 E03931 0 +OP4 E03932 0 +OP4 E03933 0 +OP4 E03934 0 +OP4 E03935 0 +OP4 E03936 0 +OP4 E03937 0 +OP4 E03938 0 +OP4 E03939 0 +OP4 E0393A 0 +OP4 E0393B 0 +OP4 E0393C 0 +OP4 E0393D 0 +OP4 E0393E 0 +OP4 E0393F 0 +OP4 E03940 0 +OP4 E03941 0 +OP4 E03942 0 +OP4 E03943 0 +OP4 E03944 0 +OP4 E03945 0 +OP4 E03946 0 +OP4 E03947 0 +OP4 E03948 0 +OP4 E03949 0 +OP4 E0394A 0 +OP4 E0394B 0 +OP4 E0394C 0 +OP4 E0394D 0 +OP4 E0394E 0 +OP4 E0394F 0 +OP4 E03950 0 +OP4 E03951 0 +OP4 E03952 0 +OP4 E03953 0 +OP4 E03954 0 +OP4 E03955 0 +OP4 E03956 0 +OP4 E03957 0 +OP4 E03958 0 +OP4 E03959 0 +OP4 E0395A 0 +OP4 E0395B 0 +OP4 E0395C 0 +OP4 E0395D 0 +OP4 E0395E 0 +OP4 E0395F 0 +OP4 E03960 0 +OP4 E03961 0 +OP4 E03962 0 +OP4 E03963 0 +OP4 E03964 0 +OP4 E03965 0 +OP4 E03966 0 +OP4 E03967 0 +OP4 E03968 0 +OP4 E03969 0 +OP4 E0396A 0 +OP4 E0396B 0 +OP4 E0396C 0 +OP4 E0396D 0 +OP4 E0396E 0 +OP4 E0396F 0 +OP4 E03970 0 +OP4 E03971 0 +OP4 E03972 0 +OP4 E03973 0 +OP4 E03974 0 +OP4 E03975 0 +OP4 E03976 0 +OP4 E03977 0 +OP4 E03978 0 +OP4 E03979 0 +OP4 E0397A 0 +OP4 E0397B 0 +OP4 E0397C 0 +OP4 E0397D 0 +OP4 E0397E 0 +OP4 E0397F 0 +OP4 E03980 0 +OP4 E03981 0 +OP4 E03982 0 +OP4 E03983 0 +OP4 E03984 0 +OP4 E03985 0 +OP4 E03986 0 +OP4 E03987 0 +OP4 E03988 0 +OP4 E03989 0 +OP4 E0398A 0 +OP4 E0398B 0 +OP4 E0398C 0 +OP4 E0398D 0 +OP4 E0398E 0 +OP4 E0398F 0 +OP4 E03990 0 +OP4 E03991 0 +OP4 E03992 0 +OP4 E03993 0 +OP4 E03994 0 +OP4 E03995 0 +OP4 E03996 0 +OP4 E03997 0 +OP4 E03998 0 +OP4 E03999 0 +OP4 E0399A 0 +OP4 E0399B 0 +OP4 E0399C 0 +OP4 E0399D 0 +OP4 E0399E 0 +OP4 E0399F 0 +OP4 E039A0 0 +OP4 E039A1 0 +OP4 E039A2 0 +OP4 E039A3 0 +OP4 E039A4 0 +OP4 E039A5 0 +OP4 E039A6 0 +OP4 E039A7 0 +OP4 E039A8 0 +OP4 E039A9 0 +OP4 E039AA 0 +OP4 E039AB 0 +OP4 E039AC 0 +OP4 E039AD 0 +OP4 E039AE 0 +OP4 E039AF 0 +OP4 E039B0 0 +OP4 E039B1 0 +OP4 E039B2 0 +OP4 E039B3 0 +OP4 E039B4 0 +OP4 E039B5 0 +OP4 E039B6 0 +OP4 E039B7 0 +OP4 E039B8 0 +OP4 E039B9 0 +OP4 E039BA 0 +OP4 E039BB 0 +OP4 E039BC 0 +OP4 E039BD 0 +OP4 E039BE 0 +OP4 E039BF 0 +OP4 E039C0 0 +OP4 E039C1 0 +OP4 E039C2 0 +OP4 E039C3 0 +OP4 E039C4 0 +OP4 E039C5 0 +OP4 E039C6 0 +OP4 E039C7 0 +OP4 E039C8 0 +OP4 E039C9 0 +OP4 E039CA 0 +OP4 E039CB 0 +OP4 E039CC 0 +OP4 E039CD 0 +OP4 E039CE 0 +OP4 E039CF 0 +OP4 E039D0 0 +OP4 E039D1 0 +OP4 E039D2 0 +OP4 E039D3 0 +OP4 E039D4 0 +OP4 E039D5 0 +OP4 E039D6 0 +OP4 E039D7 0 +OP4 E039D8 0 +OP4 E039D9 0 +OP4 E039DA 0 +OP4 E039DB 0 +OP4 E039DC 0 +OP4 E039DD 0 +OP4 E039DE 0 +OP4 E039DF 0 +OP4 E039E0 0 +OP4 E039E1 0 +OP4 E039E2 0 +OP4 E039E3 0 +OP4 E039E4 0 +OP4 E039E5 0 +OP4 E039E6 0 +OP4 E039E7 0 +OP4 E039E8 0 +OP4 E039E9 0 +OP4 E039EA 0 +OP4 E039EB 0 +OP4 E039EC 0 +OP4 E039ED 0 +OP4 E039EE 0 +OP4 E039EF 0 +OP4 E039F0 0 +OP4 E039F1 0 +OP4 E039F2 0 +OP4 E039F3 0 +OP4 E039F4 0 +OP4 E039F5 0 +OP4 E039F6 0 +OP4 E039F7 0 +OP4 E039F8 0 +OP4 E039F9 0 +OP4 E039FA 0 +OP4 E039FB 0 +OP4 E039FC 0 +OP4 E039FD 0 +OP4 E039FE 0 +OP4 E039FF 0 +OP4 E03A00 0 +OP4 E03A01 0 +OP4 E03A02 0 +OP4 E03A03 0 +OP4 E03A04 0 +OP4 E03A05 0 +OP4 E03A06 0 +OP4 E03A07 0 +OP4 E03A08 0 +OP4 E03A09 0 +OP4 E03A0A 0 +OP4 E03A0B 0 +OP4 E03A0C 0 +OP4 E03A0D 0 +OP4 E03A0E 0 +OP4 E03A0F 0 +OP4 E03A10 0 +OP4 E03A11 0 +OP4 E03A12 0 +OP4 E03A13 0 +OP4 E03A14 0 +OP4 E03A15 0 +OP4 E03A16 0 +OP4 E03A17 0 +OP4 E03A18 0 +OP4 E03A19 0 +OP4 E03A1A 0 +OP4 E03A1B 0 +OP4 E03A1C 0 +OP4 E03A1D 0 +OP4 E03A1E 0 +OP4 E03A1F 0 +OP4 E03A20 0 +OP4 E03A21 0 +OP4 E03A22 0 +OP4 E03A23 0 +OP4 E03A24 0 +OP4 E03A25 0 +OP4 E03A26 0 +OP4 E03A27 0 +OP4 E03A28 0 +OP4 E03A29 0 +OP4 E03A2A 0 +OP4 E03A2B 0 +OP4 E03A2C 0 +OP4 E03A2D 0 +OP4 E03A2E 0 +OP4 E03A2F 0 +OP4 E03A30 0 +OP4 E03A31 0 +OP4 E03A32 0 +OP4 E03A33 0 +OP4 E03A34 0 +OP4 E03A35 0 +OP4 E03A36 0 +OP4 E03A37 0 +OP4 E03A38 0 +OP4 E03A39 0 +OP4 E03A3A 0 +OP4 E03A3B 0 +OP4 E03A3C 0 +OP4 E03A3D 0 +OP4 E03A3E 0 +OP4 E03A3F 0 +OP4 E03A40 0 +OP4 E03A41 0 +OP4 E03A42 0 +OP4 E03A43 0 +OP4 E03A44 0 +OP4 E03A45 0 +OP4 E03A46 0 +OP4 E03A47 0 +OP4 E03A48 0 +OP4 E03A49 0 +OP4 E03A4A 0 +OP4 E03A4B 0 +OP4 E03A4C 0 +OP4 E03A4D 0 +OP4 E03A4E 0 +OP4 E03A4F 0 +OP4 E03A50 0 +OP4 E03A51 0 +OP4 E03A52 0 +OP4 E03A53 0 +OP4 E03A54 0 +OP4 E03A55 0 +OP4 E03A56 0 +OP4 E03A57 0 +OP4 E03A58 0 +OP4 E03A59 0 +OP4 E03A5A 0 +OP4 E03A5B 0 +OP4 E03A5C 0 +OP4 E03A5D 0 +OP4 E03A5E 0 +OP4 E03A5F 0 +OP4 E03A60 0 +OP4 E03A61 0 +OP4 E03A62 0 +OP4 E03A63 0 +OP4 E03A64 0 +OP4 E03A65 0 +OP4 E03A66 0 +OP4 E03A67 0 +OP4 E03A68 0 +OP4 E03A69 0 +OP4 E03A6A 0 +OP4 E03A6B 0 +OP4 E03A6C 0 +OP4 E03A6D 0 +OP4 E03A6E 0 +OP4 E03A6F 0 +OP4 E03A70 0 +OP4 E03A71 0 +OP4 E03A72 0 +OP4 E03A73 0 +OP4 E03A74 0 +OP4 E03A75 0 +OP4 E03A76 0 +OP4 E03A77 0 +OP4 E03A78 0 +OP4 E03A79 0 +OP4 E03A7A 0 +OP4 E03A7B 0 +OP4 E03A7C 0 +OP4 E03A7D 0 +OP4 E03A7E 0 +OP4 E03A7F 0 +OP4 E03A80 0 +OP4 E03A81 0 +OP4 E03A82 0 +OP4 E03A83 0 +OP4 E03A84 0 +OP4 E03A85 0 +OP4 E03A86 0 +OP4 E03A87 0 +OP4 E03A88 0 +OP4 E03A89 0 +OP4 E03A8A 0 +OP4 E03A8B 0 +OP4 E03A8C 0 +OP4 E03A8D 0 +OP4 E03A8E 0 +OP4 E03A8F 0 +OP4 E03A90 0 +OP4 E03A91 0 +OP4 E03A92 0 +OP4 E03A93 0 +OP4 E03A94 0 +OP4 E03A95 0 +OP4 E03A96 0 +OP4 E03A97 0 +OP4 E03A98 0 +OP4 E03A99 0 +OP4 E03A9A 0 +OP4 E03A9B 0 +OP4 E03A9C 0 +OP4 E03A9D 0 +OP4 E03A9E 0 +OP4 E03A9F 0 +OP4 E03AA0 0 +OP4 E03AA1 0 +OP4 E03AA2 0 +OP4 E03AA3 0 +OP4 E03AA4 0 +OP4 E03AA5 0 +OP4 E03AA6 0 +OP4 E03AA7 0 +OP4 E03AA8 0 +OP4 E03AA9 0 +OP4 E03AAA 0 +OP4 E03AAB 0 +OP4 E03AAC 0 +OP4 E03AAD 0 +OP4 E03AAE 0 +OP4 E03AAF 0 +OP4 E03AB0 0 +OP4 E03AB1 0 +OP4 E03AB2 0 +OP4 E03AB3 0 +OP4 E03AB4 0 +OP4 E03AB5 0 +OP4 E03AB6 0 +OP4 E03AB7 0 +OP4 E03AB8 0 +OP4 E03AB9 0 +OP4 E03ABA 0 +OP4 E03ABB 0 +OP4 E03ABC 0 +OP4 E03ABD 0 +OP4 E03ABE 0 +OP4 E03ABF 0 +OP4 E03AC0 0 +OP4 E03AC1 0 +OP4 E03AC2 0 +OP4 E03AC3 0 +OP4 E03AC4 0 +OP4 E03AC5 0 +OP4 E03AC6 0 +OP4 E03AC7 0 +OP4 E03AC8 0 +OP4 E03AC9 0 +OP4 E03ACA 0 +OP4 E03ACB 0 +OP4 E03ACC 0 +OP4 E03ACD 0 +OP4 E03ACE 0 +OP4 E03ACF 0 +OP4 E03AD0 0 +OP4 E03AD1 0 +OP4 E03AD2 0 +OP4 E03AD3 0 +OP4 E03AD4 0 +OP4 E03AD5 0 +OP4 E03AD6 0 +OP4 E03AD7 0 +OP4 E03AD8 0 +OP4 E03AD9 0 +OP4 E03ADA 0 +OP4 E03ADB 0 +OP4 E03ADC 0 +OP4 E03ADD 0 +OP4 E03ADE 0 +OP4 E03ADF 0 +OP4 E03AE0 0 +OP4 E03AE1 0 +OP4 E03AE2 0 +OP4 E03AE3 0 +OP4 E03AE4 0 +OP4 E03AE5 0 +OP4 E03AE6 0 +OP4 E03AE7 0 +OP4 E03AE8 0 +OP4 E03AE9 0 +OP4 E03AEA 0 +OP4 E03AEB 0 +OP4 E03AEC 0 +OP4 E03AED 0 +OP4 E03AEE 0 +OP4 E03AEF 0 +OP4 E03AF0 0 +OP4 E03AF1 0 +OP4 E03AF2 0 +OP4 E03AF3 0 +OP4 E03AF4 0 +OP4 E03AF5 0 +OP4 E03AF6 0 +OP4 E03AF7 0 +OP4 E03AF8 0 +OP4 E03AF9 0 +OP4 E03AFA 0 +OP4 E03AFB 0 +OP4 E03AFC 0 +OP4 E03AFD 0 +OP4 E03AFE 0 +OP4 E03AFF 0 +OP4 E03B00 0 +OP4 E03B01 0 +OP4 E03B02 0 +OP4 E03B03 0 +OP4 E03B04 0 +OP4 E03B05 0 +OP4 E03B06 0 +OP4 E03B07 0 +OP4 E03B08 0 +OP4 E03B09 0 +OP4 E03B0A 0 +OP4 E03B0B 0 +OP4 E03B0C 0 +OP4 E03B0D 0 +OP4 E03B0E 0 +OP4 E03B0F 0 +OP4 E03B10 0 +OP4 E03B11 0 +OP4 E03B12 0 +OP4 E03B13 0 +OP4 E03B14 0 +OP4 E03B15 0 +OP4 E03B16 0 +OP4 E03B17 0 +OP4 E03B18 0 +OP4 E03B19 0 +OP4 E03B1A 0 +OP4 E03B1B 0 +OP4 E03B1C 0 +OP4 E03B1D 0 +OP4 E03B1E 0 +OP4 E03B1F 0 +OP4 E03B20 0 +OP4 E03B21 0 +OP4 E03B22 0 +OP4 E03B23 0 +OP4 E03B24 0 +OP4 E03B25 0 +OP4 E03B26 0 +OP4 E03B27 0 +OP4 E03B28 0 +OP4 E03B29 0 +OP4 E03B2A 0 +OP4 E03B2B 0 +OP4 E03B2C 0 +OP4 E03B2D 0 +OP4 E03B2E 0 +OP4 E03B2F 0 +OP4 E03B30 0 +OP4 E03B31 0 +OP4 E03B32 0 +OP4 E03B33 0 +OP4 E03B34 0 +OP4 E03B35 0 +OP4 E03B36 0 +OP4 E03B37 0 +OP4 E03B38 0 +OP4 E03B39 0 +OP4 E03B3A 0 +OP4 E03B3B 0 +OP4 E03B3C 0 +OP4 E03B3D 0 +OP4 E03B3E 0 +OP4 E03B3F 0 +OP4 E03B40 0 +OP4 E03B41 0 +OP4 E03B42 0 +OP4 E03B43 0 +OP4 E03B44 0 +OP4 E03B45 0 +OP4 E03B46 0 +OP4 E03B47 0 +OP4 E03B48 0 +OP4 E03B49 0 +OP4 E03B4A 0 +OP4 E03B4B 0 +OP4 E03B4C 0 +OP4 E03B4D 0 +OP4 E03B4E 0 +OP4 E03B4F 0 +OP4 E03B50 0 +OP4 E03B51 0 +OP4 E03B52 0 +OP4 E03B53 0 +OP4 E03B54 0 +OP4 E03B55 0 +OP4 E03B56 0 +OP4 E03B57 0 +OP4 E03B58 0 +OP4 E03B59 0 +OP4 E03B5A 0 +OP4 E03B5B 0 +OP4 E03B5C 0 +OP4 E03B5D 0 +OP4 E03B5E 0 +OP4 E03B5F 0 +OP4 E03B60 0 +OP4 E03B61 0 +OP4 E03B62 0 +OP4 E03B63 0 +OP4 E03B64 0 +OP4 E03B65 0 +OP4 E03B66 0 +OP4 E03B67 0 +OP4 E03B68 0 +OP4 E03B69 0 +OP4 E03B6A 0 +OP4 E03B6B 0 +OP4 E03B6C 0 +OP4 E03B6D 0 +OP4 E03B6E 0 +OP4 E03B6F 0 +OP4 E03B70 0 +OP4 E03B71 0 +OP4 E03B72 0 +OP4 E03B73 0 +OP4 E03B74 0 +OP4 E03B75 0 +OP4 E03B76 0 +OP4 E03B77 0 +OP4 E03B78 0 +OP4 E03B79 0 +OP4 E03B7A 0 +OP4 E03B7B 0 +OP4 E03B7C 0 +OP4 E03B7D 0 +OP4 E03B7E 0 +OP4 E03B7F 0 +OP4 E03B80 0 +OP4 E03B81 0 +OP4 E03B82 0 +OP4 E03B83 0 +OP4 E03B84 0 +OP4 E03B85 0 +OP4 E03B86 0 +OP4 E03B87 0 +OP4 E03B88 0 +OP4 E03B89 0 +OP4 E03B8A 0 +OP4 E03B8B 0 +OP4 E03B8C 0 +OP4 E03B8D 0 +OP4 E03B8E 0 +OP4 E03B8F 0 +OP4 E03B90 0 +OP4 E03B91 0 +OP4 E03B92 0 +OP4 E03B93 0 +OP4 E03B94 0 +OP4 E03B95 0 +OP4 E03B96 0 +OP4 E03B97 0 +OP4 E03B98 0 +OP4 E03B99 0 +OP4 E03B9A 0 +OP4 E03B9B 0 +OP4 E03B9C 0 +OP4 E03B9D 0 +OP4 E03B9E 0 +OP4 E03B9F 0 +OP4 E03BA0 0 +OP4 E03BA1 0 +OP4 E03BA2 0 +OP4 E03BA3 0 +OP4 E03BA4 0 +OP4 E03BA5 0 +OP4 E03BA6 0 +OP4 E03BA7 0 +OP4 E03BA8 0 +OP4 E03BA9 0 +OP4 E03BAA 0 +OP4 E03BAB 0 +OP4 E03BAC 0 +OP4 E03BAD 0 +OP4 E03BAE 0 +OP4 E03BAF 0 +OP4 E03BB0 0 +OP4 E03BB1 0 +OP4 E03BB2 0 +OP4 E03BB3 0 +OP4 E03BB4 0 +OP4 E03BB5 0 +OP4 E03BB6 0 +OP4 E03BB7 0 +OP4 E03BB8 0 +OP4 E03BB9 0 +OP4 E03BBA 0 +OP4 E03BBB 0 +OP4 E03BBC 0 +OP4 E03BBD 0 +OP4 E03BBE 0 +OP4 E03BBF 0 +OP4 E03BC0 0 +OP4 E03BC1 0 +OP4 E03BC2 0 +OP4 E03BC3 0 +OP4 E03BC4 0 +OP4 E03BC5 0 +OP4 E03BC6 0 +OP4 E03BC7 0 +OP4 E03BC8 0 +OP4 E03BC9 0 +OP4 E03BCA 0 +OP4 E03BCB 0 +OP4 E03BCC 0 +OP4 E03BCD 0 +OP4 E03BCE 0 +OP4 E03BCF 0 +OP4 E03BD0 0 +OP4 E03BD1 0 +OP4 E03BD2 0 +OP4 E03BD3 0 +OP4 E03BD4 0 +OP4 E03BD5 0 +OP4 E03BD6 0 +OP4 E03BD7 0 +OP4 E03BD8 0 +OP4 E03BD9 0 +OP4 E03BDA 0 +OP4 E03BDB 0 +OP4 E03BDC 0 +OP4 E03BDD 0 +OP4 E03BDE 0 +OP4 E03BDF 0 +OP4 E03BE0 0 +OP4 E03BE1 0 +OP4 E03BE2 0 +OP4 E03BE3 0 +OP4 E03BE4 0 +OP4 E03BE5 0 +OP4 E03BE6 0 +OP4 E03BE7 0 +OP4 E03BE8 0 +OP4 E03BE9 0 +OP4 E03BEA 0 +OP4 E03BEB 0 +OP4 E03BEC 0 +OP4 E03BED 0 +OP4 E03BEE 0 +OP4 E03BEF 0 +OP4 E03BF0 0 +OP4 E03BF1 0 +OP4 E03BF2 0 +OP4 E03BF3 0 +OP4 E03BF4 0 +OP4 E03BF5 0 +OP4 E03BF6 0 +OP4 E03BF7 0 +OP4 E03BF8 0 +OP4 E03BF9 0 +OP4 E03BFA 0 +OP4 E03BFB 0 +OP4 E03BFC 0 +OP4 E03BFD 0 +OP4 E03BFE 0 +OP4 E03BFF 0 +OP4 E03C00 0 +OP4 E03C01 0 +OP4 E03C02 0 +OP4 E03C03 0 +OP4 E03C04 0 +OP4 E03C05 0 +OP4 E03C06 0 +OP4 E03C07 0 +OP4 E03C08 0 +OP4 E03C09 0 +OP4 E03C0A 0 +OP4 E03C0B 0 +OP4 E03C0C 0 +OP4 E03C0D 0 +OP4 E03C0E 0 +OP4 E03C0F 0 +OP4 E03C10 0 +OP4 E03C11 0 +OP4 E03C12 0 +OP4 E03C13 0 +OP4 E03C14 0 +OP4 E03C15 0 +OP4 E03C16 0 +OP4 E03C17 0 +OP4 E03C18 0 +OP4 E03C19 0 +OP4 E03C1A 0 +OP4 E03C1B 0 +OP4 E03C1C 0 +OP4 E03C1D 0 +OP4 E03C1E 0 +OP4 E03C1F 0 +OP4 E03C20 0 +OP4 E03C21 0 +OP4 E03C22 0 +OP4 E03C23 0 +OP4 E03C24 0 +OP4 E03C25 0 +OP4 E03C26 0 +OP4 E03C27 0 +OP4 E03C28 0 +OP4 E03C29 0 +OP4 E03C2A 0 +OP4 E03C2B 0 +OP4 E03C2C 0 +OP4 E03C2D 0 +OP4 E03C2E 0 +OP4 E03C2F 0 +OP4 E03C30 0 +OP4 E03C31 0 +OP4 E03C32 0 +OP4 E03C33 0 +OP4 E03C34 0 +OP4 E03C35 0 +OP4 E03C36 0 +OP4 E03C37 0 +OP4 E03C38 0 +OP4 E03C39 0 +OP4 E03C3A 0 +OP4 E03C3B 0 +OP4 E03C3C 0 +OP4 E03C3D 0 +OP4 E03C3E 0 +OP4 E03C3F 0 +OP4 E03C40 0 +OP4 E03C41 0 +OP4 E03C42 0 +OP4 E03C43 0 +OP4 E03C44 0 +OP4 E03C45 0 +OP4 E03C46 0 +OP4 E03C47 0 +OP4 E03C48 0 +OP4 E03C49 0 +OP4 E03C4A 0 +OP4 E03C4B 0 +OP4 E03C4C 0 +OP4 E03C4D 0 +OP4 E03C4E 0 +OP4 E03C4F 0 +OP4 E03C50 0 +OP4 E03C51 0 +OP4 E03C52 0 +OP4 E03C53 0 +OP4 E03C54 0 +OP4 E03C55 0 +OP4 E03C56 0 +OP4 E03C57 0 +OP4 E03C58 0 +OP4 E03C59 0 +OP4 E03C5A 0 +OP4 E03C5B 0 +OP4 E03C5C 0 +OP4 E03C5D 0 +OP4 E03C5E 0 +OP4 E03C5F 0 +OP4 E03C60 0 +OP4 E03C61 0 +OP4 E03C62 0 +OP4 E03C63 0 +OP4 E03C64 0 +OP4 E03C65 0 +OP4 E03C66 0 +OP4 E03C67 0 +OP4 E03C68 0 +OP4 E03C69 0 +OP4 E03C6A 0 +OP4 E03C6B 0 +OP4 E03C6C 0 +OP4 E03C6D 0 +OP4 E03C6E 0 +OP4 E03C6F 0 +OP4 E03C70 0 +OP4 E03C71 0 +OP4 E03C72 0 +OP4 E03C73 0 +OP4 E03C74 0 +OP4 E03C75 0 +OP4 E03C76 0 +OP4 E03C77 0 +OP4 E03C78 0 +OP4 E03C79 0 +OP4 E03C7A 0 +OP4 E03C7B 0 +OP4 E03C7C 0 +OP4 E03C7D 0 +OP4 E03C7E 0 +OP4 E03C7F 0 +OP4 E03C80 0 +OP4 E03C81 0 +OP4 E03C82 0 +OP4 E03C83 0 +OP4 E03C84 0 +OP4 E03C85 0 +OP4 E03C86 0 +OP4 E03C87 0 +OP4 E03C88 0 +OP4 E03C89 0 +OP4 E03C8A 0 +OP4 E03C8B 0 +OP4 E03C8C 0 +OP4 E03C8D 0 +OP4 E03C8E 0 +OP4 E03C8F 0 +OP4 E03C90 0 +OP4 E03C91 0 +OP4 E03C92 0 +OP4 E03C93 0 +OP4 E03C94 0 +OP4 E03C95 0 +OP4 E03C96 0 +OP4 E03C97 0 +OP4 E03C98 0 +OP4 E03C99 0 +OP4 E03C9A 0 +OP4 E03C9B 0 +OP4 E03C9C 0 +OP4 E03C9D 0 +OP4 E03C9E 0 +OP4 E03C9F 0 +OP4 E03CA0 0 +OP4 E03CA1 0 +OP4 E03CA2 0 +OP4 E03CA3 0 +OP4 E03CA4 0 +OP4 E03CA5 0 +OP4 E03CA6 0 +OP4 E03CA7 0 +OP4 E03CA8 0 +OP4 E03CA9 0 +OP4 E03CAA 0 +OP4 E03CAB 0 +OP4 E03CAC 0 +OP4 E03CAD 0 +OP4 E03CAE 0 +OP4 E03CAF 0 +OP4 E03CB0 0 +OP4 E03CB1 0 +OP4 E03CB2 0 +OP4 E03CB3 0 +OP4 E03CB4 0 +OP4 E03CB5 0 +OP4 E03CB6 0 +OP4 E03CB7 0 +OP4 E03CB8 0 +OP4 E03CB9 0 +OP4 E03CBA 0 +OP4 E03CBB 0 +OP4 E03CBC 0 +OP4 E03CBD 0 +OP4 E03CBE 0 +OP4 E03CBF 0 +OP4 E03CC0 0 +OP4 E03CC1 0 +OP4 E03CC2 0 +OP4 E03CC3 0 +OP4 E03CC4 0 +OP4 E03CC5 0 +OP4 E03CC6 0 +OP4 E03CC7 0 +OP4 E03CC8 0 +OP4 E03CC9 0 +OP4 E03CCA 0 +OP4 E03CCB 0 +OP4 E03CCC 0 +OP4 E03CCD 0 +OP4 E03CCE 0 +OP4 E03CCF 0 +OP4 E03CD0 0 +OP4 E03CD1 0 +OP4 E03CD2 0 +OP4 E03CD3 0 +OP4 E03CD4 0 +OP4 E03CD5 0 +OP4 E03CD6 0 +OP4 E03CD7 0 +OP4 E03CD8 0 +OP4 E03CD9 0 +OP4 E03CDA 0 +OP4 E03CDB 0 +OP4 E03CDC 0 +OP4 E03CDD 0 +OP4 E03CDE 0 +OP4 E03CDF 0 +OP4 E03CE0 0 +OP4 E03CE1 0 +OP4 E03CE2 0 +OP4 E03CE3 0 +OP4 E03CE4 0 +OP4 E03CE5 0 +OP4 E03CE6 0 +OP4 E03CE7 0 +OP4 E03CE8 0 +OP4 E03CE9 0 +OP4 E03CEA 0 +OP4 E03CEB 0 +OP4 E03CEC 0 +OP4 E03CED 0 +OP4 E03CEE 0 +OP4 E03CEF 0 +OP4 E03CF0 0 +OP4 E03CF1 0 +OP4 E03CF2 0 +OP4 E03CF3 0 +OP4 E03CF4 0 +OP4 E03CF5 0 +OP4 E03CF6 0 +OP4 E03CF7 0 +OP4 E03CF8 0 +OP4 E03CF9 0 +OP4 E03CFA 0 +OP4 E03CFB 0 +OP4 E03CFC 0 +OP4 E03CFD 0 +OP4 E03CFE 0 +OP4 E03CFF 0 +OP4 E03D00 0 +OP4 E03D01 0 +OP4 E03D02 0 +OP4 E03D03 0 +OP4 E03D04 0 +OP4 E03D05 0 +OP4 E03D06 0 +OP4 E03D07 0 +OP4 E03D08 0 +OP4 E03D09 0 +OP4 E03D0A 0 +OP4 E03D0B 0 +OP4 E03D0C 0 +OP4 E03D0D 0 +OP4 E03D0E 0 +OP4 E03D0F 0 +OP4 E03D10 0 +OP4 E03D11 0 +OP4 E03D12 0 +OP4 E03D13 0 +OP4 E03D14 0 +OP4 E03D15 0 +OP4 E03D16 0 +OP4 E03D17 0 +OP4 E03D18 0 +OP4 E03D19 0 +OP4 E03D1A 0 +OP4 E03D1B 0 +OP4 E03D1C 0 +OP4 E03D1D 0 +OP4 E03D1E 0 +OP4 E03D1F 0 +OP4 E03D20 0 +OP4 E03D21 0 +OP4 E03D22 0 +OP4 E03D23 0 +OP4 E03D24 0 +OP4 E03D25 0 +OP4 E03D26 0 +OP4 E03D27 0 +OP4 E03D28 0 +OP4 E03D29 0 +OP4 E03D2A 0 +OP4 E03D2B 0 +OP4 E03D2C 0 +OP4 E03D2D 0 +OP4 E03D2E 0 +OP4 E03D2F 0 +OP4 E03D30 0 +OP4 E03D31 0 +OP4 E03D32 0 +OP4 E03D33 0 +OP4 E03D34 0 +OP4 E03D35 0 +OP4 E03D36 0 +OP4 E03D37 0 +OP4 E03D38 0 +OP4 E03D39 0 +OP4 E03D3A 0 +OP4 E03D3B 0 +OP4 E03D3C 0 +OP4 E03D3D 0 +OP4 E03D3E 0 +OP4 E03D3F 0 +OP4 E03D40 0 +OP4 E03D41 0 +OP4 E03D42 0 +OP4 E03D43 0 +OP4 E03D44 0 +OP4 E03D45 0 +OP4 E03D46 0 +OP4 E03D47 0 +OP4 E03D48 0 +OP4 E03D49 0 +OP4 E03D4A 0 +OP4 E03D4B 0 +OP4 E03D4C 0 +OP4 E03D4D 0 +OP4 E03D4E 0 +OP4 E03D4F 0 +OP4 E03D50 0 +OP4 E03D51 0 +OP4 E03D52 0 +OP4 E03D53 0 +OP4 E03D54 0 +OP4 E03D55 0 +OP4 E03D56 0 +OP4 E03D57 0 +OP4 E03D58 0 +OP4 E03D59 0 +OP4 E03D5A 0 +OP4 E03D5B 0 +OP4 E03D5C 0 +OP4 E03D5D 0 +OP4 E03D5E 0 +OP4 E03D5F 0 +OP4 E03D60 0 +OP4 E03D61 0 +OP4 E03D62 0 +OP4 E03D63 0 +OP4 E03D64 0 +OP4 E03D65 0 +OP4 E03D66 0 +OP4 E03D67 0 +OP4 E03D68 0 +OP4 E03D69 0 +OP4 E03D6A 0 +OP4 E03D6B 0 +OP4 E03D6C 0 +OP4 E03D6D 0 +OP4 E03D6E 0 +OP4 E03D6F 0 +OP4 E03D70 0 +OP4 E03D71 0 +OP4 E03D72 0 +OP4 E03D73 0 +OP4 E03D74 0 +OP4 E03D75 0 +OP4 E03D76 0 +OP4 E03D77 0 +OP4 E03D78 0 +OP4 E03D79 0 +OP4 E03D7A 0 +OP4 E03D7B 0 +OP4 E03D7C 0 +OP4 E03D7D 0 +OP4 E03D7E 0 +OP4 E03D7F 0 +OP4 E03D80 0 +OP4 E03D81 0 +OP4 E03D82 0 +OP4 E03D83 0 +OP4 E03D84 0 +OP4 E03D85 0 +OP4 E03D86 0 +OP4 E03D87 0 +OP4 E03D88 0 +OP4 E03D89 0 +OP4 E03D8A 0 +OP4 E03D8B 0 +OP4 E03D8C 0 +OP4 E03D8D 0 +OP4 E03D8E 0 +OP4 E03D8F 0 +OP4 E03D90 0 +OP4 E03D91 0 +OP4 E03D92 0 +OP4 E03D93 0 +OP4 E03D94 0 +OP4 E03D95 0 +OP4 E03D96 0 +OP4 E03D97 0 +OP4 E03D98 0 +OP4 E03D99 0 +OP4 E03D9A 0 +OP4 E03D9B 0 +OP4 E03D9C 0 +OP4 E03D9D 0 +OP4 E03D9E 0 +OP4 E03D9F 0 +OP4 E03DA0 0 +OP4 E03DA1 0 +OP4 E03DA2 0 +OP4 E03DA3 0 +OP4 E03DA4 0 +OP4 E03DA5 0 +OP4 E03DA6 0 +OP4 E03DA7 0 +OP4 E03DA8 0 +OP4 E03DA9 0 +OP4 E03DAA 0 +OP4 E03DAB 0 +OP4 E03DAC 0 +OP4 E03DAD 0 +OP4 E03DAE 0 +OP4 E03DAF 0 +OP4 E03DB0 0 +OP4 E03DB1 0 +OP4 E03DB2 0 +OP4 E03DB3 0 +OP4 E03DB4 0 +OP4 E03DB5 0 +OP4 E03DB6 0 +OP4 E03DB7 0 +OP4 E03DB8 0 +OP4 E03DB9 0 +OP4 E03DBA 0 +OP4 E03DBB 0 +OP4 E03DBC 0 +OP4 E03DBD 0 +OP4 E03DBE 0 +OP4 E03DBF 0 +OP4 E03DC0 0 +OP4 E03DC1 0 +OP4 E03DC2 0 +OP4 E03DC3 0 +OP4 E03DC4 0 diff --git a/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum4_itrace_irisc9.cfg.ext b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum4_itrace_irisc9.cfg.ext new file mode 100644 index 000000000000..a7aa8b4515d0 --- /dev/null +++ b/platform/mellanox/mft-fwtrace-cfg/etc/mft/fwtrace_cfg/mlxtrace_spectrum4_itrace_irisc9.cfg.ext @@ -0,0 +1,15814 @@ +OP1 Spectrum4 +OP4 ITRACE0 0 +OP4 ITRACE1 0 +OP4 ITRACE2 0 +OP4 ITRACE3 0 +OP4 ITRACE4 0 +OP4 ITRACE5 0 +OP4 ITRACE6 0 +OP4 ITRACE7 0 +OP4 ITRACE8 0 +OP4 ITRACE9 1 +OP4 Main_PhyUC 0 +OP4 TILE0_ITRACE0 0 +OP4 TILE0_ITRACE1 0 +OP4 TILE0_ITRACE2 0 +OP4 TILE0_ITRACE3 0 +OP4 TILE0_ITRACE4 0 +OP4 TILE0_PhyUC 0 +OP4 TILE1_ITRACE0 0 +OP4 TILE1_ITRACE1 0 +OP4 TILE1_ITRACE2 0 +OP4 TILE1_ITRACE3 0 +OP4 TILE1_ITRACE4 0 +OP4 TILE1_PhyUC 0 +OP4 TILE2_ITRACE0 0 +OP4 TILE2_ITRACE1 0 +OP4 TILE2_ITRACE2 0 +OP4 TILE2_ITRACE3 0 +OP4 TILE2_ITRACE4 0 +OP4 TILE2_PhyUC 0 +OP4 TILE3_ITRACE0 0 +OP4 TILE3_ITRACE1 0 +OP4 TILE3_ITRACE2 0 +OP4 TILE3_ITRACE3 0 +OP4 TILE3_ITRACE4 0 +OP4 TILE3_PhyUC 0 +OP4 TILE4_ITRACE0 0 +OP4 TILE4_ITRACE1 0 +OP4 TILE4_ITRACE2 0 +OP4 TILE4_ITRACE3 0 +OP4 TILE4_ITRACE4 0 +OP4 TILE4_PhyUC 0 +OP4 TILE5_ITRACE0 0 +OP4 TILE5_ITRACE1 0 +OP4 TILE5_ITRACE2 0 +OP4 TILE5_ITRACE3 0 +OP4 TILE5_ITRACE4 0 +OP4 TILE5_PhyUC 0 +OP4 TILE6_ITRACE0 0 +OP4 TILE6_ITRACE1 0 +OP4 TILE6_ITRACE2 0 +OP4 TILE6_ITRACE3 0 +OP4 TILE6_ITRACE4 0 +OP4 TILE6_PhyUC 0 +OP4 TILE7_ITRACE0 0 +OP4 TILE7_ITRACE1 0 +OP4 TILE7_ITRACE2 0 +OP4 TILE7_ITRACE3 0 +OP4 TILE7_ITRACE4 0 +OP4 TILE7_PhyUC 0 +OP4 E0003B 0 +OP4 E0003C 0 +OP4 E0003D 0 +OP4 E0003E 0 +OP4 E0003F 0 +OP4 E00040 0 +OP4 E00041 0 +OP4 E00042 0 +OP4 E00043 0 +OP4 E00044 0 +OP4 E00045 0 +OP4 E00046 0 +OP4 E00047 0 +OP4 E00048 0 +OP4 E00049 0 +OP4 E0004A 0 +OP4 E0004B 0 +OP4 E0004C 0 +OP4 E0004D 0 +OP4 E0004E 0 +OP4 E0004F 0 +OP4 E00050 0 +OP4 E00051 0 +OP4 E00052 0 +OP4 E00053 0 +OP4 E00054 0 +OP4 E00055 0 +OP4 E00056 0 +OP4 E00057 0 +OP4 E00058 0 +OP4 E00059 0 +OP4 E0005A 0 +OP4 E0005B 0 +OP4 E0005C 0 +OP4 E0005D 0 +OP4 E0005E 0 +OP4 E0005F 0 +OP4 E00060 0 +OP4 E00061 0 +OP4 E00062 0 +OP4 E00063 0 +OP4 E00064 0 +OP4 E00065 0 +OP4 E00066 0 +OP4 E00067 0 +OP4 E00068 0 +OP4 E00069 0 +OP4 E0006A 0 +OP4 E0006B 0 +OP4 E0006C 0 +OP4 E0006D 0 +OP4 E0006E 0 +OP4 E0006F 0 +OP4 E00070 0 +OP4 E00071 0 +OP4 E00072 0 +OP4 E00073 0 +OP4 E00074 0 +OP4 E00075 0 +OP4 E00076 0 +OP4 E00077 0 +OP4 E00078 0 +OP4 E00079 0 +OP4 E0007A 0 +OP4 E0007B 0 +OP4 E0007C 0 +OP4 E0007D 0 +OP4 E0007E 0 +OP4 E0007F 0 +OP4 E00080 0 +OP4 E00081 0 +OP4 E00082 0 +OP4 E00083 0 +OP4 E00084 0 +OP4 E00085 0 +OP4 E00086 0 +OP4 E00087 0 +OP4 E00088 0 +OP4 E00089 0 +OP4 E0008A 0 +OP4 E0008B 0 +OP4 E0008C 0 +OP4 E0008D 0 +OP4 E0008E 0 +OP4 E0008F 0 +OP4 E00090 0 +OP4 E00091 0 +OP4 E00092 0 +OP4 E00093 0 +OP4 E00094 0 +OP4 E00095 0 +OP4 E00096 0 +OP4 E00097 0 +OP4 E00098 0 +OP4 E00099 0 +OP4 E0009A 0 +OP4 E0009B 0 +OP4 E0009C 0 +OP4 E0009D 0 +OP4 E0009E 0 +OP4 E0009F 0 +OP4 E000A0 0 +OP4 E000A1 0 +OP4 E000A2 0 +OP4 E000A3 0 +OP4 E000A4 0 +OP4 E000A5 0 +OP4 E000A6 0 +OP4 E000A7 0 +OP4 E000A8 0 +OP4 E000A9 0 +OP4 E000AA 0 +OP4 E000AB 0 +OP4 E000AC 0 +OP4 E000AD 0 +OP4 E000AE 0 +OP4 E000AF 0 +OP4 E000B0 0 +OP4 E000B1 0 +OP4 E000B2 0 +OP4 E000B3 0 +OP4 E000B4 0 +OP4 E000B5 0 +OP4 E000B6 0 +OP4 E000B7 0 +OP4 E000B8 0 +OP4 E000B9 0 +OP4 E000BA 0 +OP4 E000BB 0 +OP4 E000BC 0 +OP4 E000BD 0 +OP4 E000BE 0 +OP4 E000BF 0 +OP4 E000C0 0 +OP4 E000C1 0 +OP4 E000C2 0 +OP4 E000C3 0 +OP4 E000C4 0 +OP4 E000C5 0 +OP4 E000C6 0 +OP4 E000C7 0 +OP4 E000C8 0 +OP4 E000C9 0 +OP4 E000CA 0 +OP4 E000CB 0 +OP4 E000CC 0 +OP4 E000CD 0 +OP4 E000CE 0 +OP4 E000CF 0 +OP4 E000D0 0 +OP4 E000D1 0 +OP4 E000D2 0 +OP4 E000D3 0 +OP4 E000D4 0 +OP4 E000D5 0 +OP4 E000D6 0 +OP4 E000D7 0 +OP4 E000D8 0 +OP4 E000D9 0 +OP4 E000DA 0 +OP4 E000DB 0 +OP4 E000DC 0 +OP4 E000DD 0 +OP4 E000DE 0 +OP4 E000DF 0 +OP4 E000E0 0 +OP4 E000E1 0 +OP4 E000E2 0 +OP4 E000E3 0 +OP4 E000E4 0 +OP4 E000E5 0 +OP4 E000E6 0 +OP4 E000E7 0 +OP4 E000E8 0 +OP4 E000E9 0 +OP4 E000EA 0 +OP4 E000EB 0 +OP4 E000EC 0 +OP4 E000ED 0 +OP4 E000EE 0 +OP4 E000EF 0 +OP4 E000F0 0 +OP4 E000F1 0 +OP4 E000F2 0 +OP4 E000F3 0 +OP4 E000F4 0 +OP4 E000F5 0 +OP4 E000F6 0 +OP4 E000F7 0 +OP4 E000F8 0 +OP4 E000F9 0 +OP4 E000FA 0 +OP4 E000FB 0 +OP4 E000FC 0 +OP4 E000FD 0 +OP4 E000FE 0 +OP4 E000FF 0 +OP4 E00100 0 +OP4 E00101 0 +OP4 E00102 0 +OP4 E00103 0 +OP4 E00104 0 +OP4 E00105 0 +OP4 E00106 0 +OP4 E00107 0 +OP4 E00108 0 +OP4 E00109 0 +OP4 E0010A 0 +OP4 E0010B 0 +OP4 E0010C 0 +OP4 E0010D 0 +OP4 E0010E 0 +OP4 E0010F 0 +OP4 E00110 0 +OP4 E00111 0 +OP4 E00112 0 +OP4 E00113 0 +OP4 E00114 0 +OP4 E00115 0 +OP4 E00116 0 +OP4 E00117 0 +OP4 E00118 0 +OP4 E00119 0 +OP4 E0011A 0 +OP4 E0011B 0 +OP4 E0011C 0 +OP4 E0011D 0 +OP4 E0011E 0 +OP4 E0011F 0 +OP4 E00120 0 +OP4 E00121 0 +OP4 E00122 0 +OP4 E00123 0 +OP4 E00124 0 +OP4 E00125 0 +OP4 E00126 0 +OP4 E00127 0 +OP4 E00128 0 +OP4 E00129 0 +OP4 E0012A 0 +OP4 E0012B 0 +OP4 E0012C 0 +OP4 E0012D 0 +OP4 E0012E 0 +OP4 E0012F 0 +OP4 E00130 0 +OP4 E00131 0 +OP4 E00132 0 +OP4 E00133 0 +OP4 E00134 0 +OP4 E00135 0 +OP4 E00136 0 +OP4 E00137 0 +OP4 E00138 0 +OP4 E00139 0 +OP4 E0013A 0 +OP4 E0013B 0 +OP4 E0013C 0 +OP4 E0013D 0 +OP4 E0013E 0 +OP4 E0013F 0 +OP4 E00140 0 +OP4 E00141 0 +OP4 E00142 0 +OP4 E00143 0 +OP4 E00144 0 +OP4 E00145 0 +OP4 E00146 0 +OP4 E00147 0 +OP4 E00148 0 +OP4 E00149 0 +OP4 E0014A 0 +OP4 E0014B 0 +OP4 E0014C 0 +OP4 E0014D 0 +OP4 E0014E 0 +OP4 E0014F 0 +OP4 E00150 0 +OP4 E00151 0 +OP4 E00152 0 +OP4 E00153 0 +OP4 E00154 0 +OP4 E00155 0 +OP4 E00156 0 +OP4 E00157 0 +OP4 E00158 0 +OP4 E00159 0 +OP4 E0015A 0 +OP4 E0015B 0 +OP4 E0015C 0 +OP4 E0015D 0 +OP4 E0015E 0 +OP4 E0015F 0 +OP4 E00160 0 +OP4 E00161 0 +OP4 E00162 0 +OP4 E00163 0 +OP4 E00164 0 +OP4 E00165 0 +OP4 E00166 0 +OP4 E00167 0 +OP4 E00168 0 +OP4 E00169 0 +OP4 E0016A 0 +OP4 E0016B 0 +OP4 E0016C 0 +OP4 E0016D 0 +OP4 E0016E 0 +OP4 E0016F 0 +OP4 E00170 0 +OP4 E00171 0 +OP4 E00172 0 +OP4 E00173 0 +OP4 E00174 0 +OP4 E00175 0 +OP4 E00176 0 +OP4 E00177 0 +OP4 E00178 0 +OP4 E00179 0 +OP4 E0017A 0 +OP4 E0017B 0 +OP4 E0017C 0 +OP4 E0017D 0 +OP4 E0017E 0 +OP4 E0017F 0 +OP4 E00180 0 +OP4 E00181 0 +OP4 E00182 0 +OP4 E00183 0 +OP4 E00184 0 +OP4 E00185 0 +OP4 E00186 0 +OP4 E00187 0 +OP4 E00188 0 +OP4 E00189 0 +OP4 E0018A 0 +OP4 E0018B 0 +OP4 E0018C 0 +OP4 E0018D 0 +OP4 E0018E 0 +OP4 E0018F 0 +OP4 E00190 0 +OP4 E00191 0 +OP4 E00192 0 +OP4 E00193 0 +OP4 E00194 0 +OP4 E00195 0 +OP4 E00196 0 +OP4 E00197 0 +OP4 E00198 0 +OP4 E00199 0 +OP4 E0019A 0 +OP4 E0019B 0 +OP4 E0019C 0 +OP4 E0019D 0 +OP4 E0019E 0 +OP4 E0019F 0 +OP4 E001A0 0 +OP4 E001A1 0 +OP4 E001A2 0 +OP4 E001A3 0 +OP4 E001A4 0 +OP4 E001A5 0 +OP4 E001A6 0 +OP4 E001A7 0 +OP4 E001A8 0 +OP4 E001A9 0 +OP4 E001AA 0 +OP4 E001AB 0 +OP4 E001AC 0 +OP4 E001AD 0 +OP4 E001AE 0 +OP4 E001AF 0 +OP4 E001B0 0 +OP4 E001B1 0 +OP4 E001B2 0 +OP4 E001B3 0 +OP4 E001B4 0 +OP4 E001B5 0 +OP4 E001B6 0 +OP4 E001B7 0 +OP4 E001B8 0 +OP4 E001B9 0 +OP4 E001BA 0 +OP4 E001BB 0 +OP4 E001BC 0 +OP4 E001BD 0 +OP4 E001BE 0 +OP4 E001BF 0 +OP4 E001C0 0 +OP4 E001C1 0 +OP4 E001C2 0 +OP4 E001C3 0 +OP4 E001C4 0 +OP4 E001C5 0 +OP4 E001C6 0 +OP4 E001C7 0 +OP4 E001C8 0 +OP4 E001C9 0 +OP4 E001CA 0 +OP4 E001CB 0 +OP4 E001CC 0 +OP4 E001CD 0 +OP4 E001CE 0 +OP4 E001CF 0 +OP4 E001D0 0 +OP4 E001D1 0 +OP4 E001D2 0 +OP4 E001D3 0 +OP4 E001D4 0 +OP4 E001D5 0 +OP4 E001D6 0 +OP4 E001D7 0 +OP4 E001D8 0 +OP4 E001D9 0 +OP4 E001DA 0 +OP4 E001DB 0 +OP4 E001DC 0 +OP4 E001DD 0 +OP4 E001DE 0 +OP4 E001DF 0 +OP4 E001E0 0 +OP4 E001E1 0 +OP4 E001E2 0 +OP4 E001E3 0 +OP4 E001E4 0 +OP4 E001E5 0 +OP4 E001E6 0 +OP4 E001E7 0 +OP4 E001E8 0 +OP4 E001E9 0 +OP4 E001EA 0 +OP4 E001EB 0 +OP4 E001EC 0 +OP4 E001ED 0 +OP4 E001EE 0 +OP4 E001EF 0 +OP4 E001F0 0 +OP4 E001F1 0 +OP4 E001F2 0 +OP4 E001F3 0 +OP4 E001F4 0 +OP4 E001F5 0 +OP4 E001F6 0 +OP4 E001F7 0 +OP4 E001F8 0 +OP4 E001F9 0 +OP4 E001FA 0 +OP4 E001FB 0 +OP4 E001FC 0 +OP4 E001FD 0 +OP4 E001FE 0 +OP4 E001FF 0 +OP4 E00200 0 +OP4 E00201 0 +OP4 E00202 0 +OP4 E00203 0 +OP4 E00204 0 +OP4 E00205 0 +OP4 E00206 0 +OP4 E00207 0 +OP4 E00208 0 +OP4 E00209 0 +OP4 E0020A 0 +OP4 E0020B 0 +OP4 E0020C 0 +OP4 E0020D 0 +OP4 E0020E 0 +OP4 E0020F 0 +OP4 E00210 0 +OP4 E00211 0 +OP4 E00212 0 +OP4 E00213 0 +OP4 E00214 0 +OP4 E00215 0 +OP4 E00216 0 +OP4 E00217 0 +OP4 E00218 0 +OP4 E00219 0 +OP4 E0021A 0 +OP4 E0021B 0 +OP4 E0021C 0 +OP4 E0021D 0 +OP4 E0021E 0 +OP4 E0021F 0 +OP4 E00220 0 +OP4 E00221 0 +OP4 E00222 0 +OP4 E00223 0 +OP4 E00224 0 +OP4 E00225 0 +OP4 E00226 0 +OP4 E00227 0 +OP4 E00228 0 +OP4 E00229 0 +OP4 E0022A 0 +OP4 E0022B 0 +OP4 E0022C 0 +OP4 E0022D 0 +OP4 E0022E 0 +OP4 E0022F 0 +OP4 E00230 0 +OP4 E00231 0 +OP4 E00232 0 +OP4 E00233 0 +OP4 E00234 0 +OP4 E00235 0 +OP4 E00236 0 +OP4 E00237 0 +OP4 E00238 0 +OP4 E00239 0 +OP4 E0023A 0 +OP4 E0023B 0 +OP4 E0023C 0 +OP4 E0023D 0 +OP4 E0023E 0 +OP4 E0023F 0 +OP4 E00240 0 +OP4 E00241 0 +OP4 E00242 0 +OP4 E00243 0 +OP4 E00244 0 +OP4 E00245 0 +OP4 E00246 0 +OP4 E00247 0 +OP4 E00248 0 +OP4 E00249 0 +OP4 E0024A 0 +OP4 E0024B 0 +OP4 E0024C 0 +OP4 E0024D 0 +OP4 E0024E 0 +OP4 E0024F 0 +OP4 E00250 0 +OP4 E00251 0 +OP4 E00252 0 +OP4 E00253 0 +OP4 E00254 0 +OP4 E00255 0 +OP4 E00256 0 +OP4 E00257 0 +OP4 E00258 0 +OP4 E00259 0 +OP4 E0025A 0 +OP4 E0025B 0 +OP4 E0025C 0 +OP4 E0025D 0 +OP4 E0025E 0 +OP4 E0025F 0 +OP4 E00260 0 +OP4 E00261 0 +OP4 E00262 0 +OP4 E00263 0 +OP4 E00264 0 +OP4 E00265 0 +OP4 E00266 0 +OP4 E00267 0 +OP4 E00268 0 +OP4 E00269 0 +OP4 E0026A 0 +OP4 E0026B 0 +OP4 E0026C 0 +OP4 E0026D 0 +OP4 E0026E 0 +OP4 E0026F 0 +OP4 E00270 0 +OP4 E00271 0 +OP4 E00272 0 +OP4 E00273 0 +OP4 E00274 0 +OP4 E00275 0 +OP4 E00276 0 +OP4 E00277 0 +OP4 E00278 0 +OP4 E00279 0 +OP4 E0027A 0 +OP4 E0027B 0 +OP4 E0027C 0 +OP4 E0027D 0 +OP4 E0027E 0 +OP4 E0027F 0 +OP4 E00280 0 +OP4 E00281 0 +OP4 E00282 0 +OP4 E00283 0 +OP4 E00284 0 +OP4 E00285 0 +OP4 E00286 0 +OP4 E00287 0 +OP4 E00288 0 +OP4 E00289 0 +OP4 E0028A 0 +OP4 E0028B 0 +OP4 E0028C 0 +OP4 E0028D 0 +OP4 E0028E 0 +OP4 E0028F 0 +OP4 E00290 0 +OP4 E00291 0 +OP4 E00292 0 +OP4 E00293 0 +OP4 E00294 0 +OP4 E00295 0 +OP4 E00296 0 +OP4 E00297 0 +OP4 E00298 0 +OP4 E00299 0 +OP4 E0029A 0 +OP4 E0029B 0 +OP4 E0029C 0 +OP4 E0029D 0 +OP4 E0029E 0 +OP4 E0029F 0 +OP4 E002A0 0 +OP4 E002A1 0 +OP4 E002A2 0 +OP4 E002A3 0 +OP4 E002A4 0 +OP4 E002A5 0 +OP4 E002A6 0 +OP4 E002A7 0 +OP4 E002A8 0 +OP4 E002A9 0 +OP4 E002AA 0 +OP4 E002AB 0 +OP4 E002AC 0 +OP4 E002AD 0 +OP4 E002AE 0 +OP4 E002AF 0 +OP4 E002B0 0 +OP4 E002B1 0 +OP4 E002B2 0 +OP4 E002B3 0 +OP4 E002B4 0 +OP4 E002B5 0 +OP4 E002B6 0 +OP4 E002B7 0 +OP4 E002B8 0 +OP4 E002B9 0 +OP4 E002BA 0 +OP4 E002BB 0 +OP4 E002BC 0 +OP4 E002BD 0 +OP4 E002BE 0 +OP4 E002BF 0 +OP4 E002C0 0 +OP4 E002C1 0 +OP4 E002C2 0 +OP4 E002C3 0 +OP4 E002C4 0 +OP4 E002C5 0 +OP4 E002C6 0 +OP4 E002C7 0 +OP4 E002C8 0 +OP4 E002C9 0 +OP4 E002CA 0 +OP4 E002CB 0 +OP4 E002CC 0 +OP4 E002CD 0 +OP4 E002CE 0 +OP4 E002CF 0 +OP4 E002D0 0 +OP4 E002D1 0 +OP4 E002D2 0 +OP4 E002D3 0 +OP4 E002D4 0 +OP4 E002D5 0 +OP4 E002D6 0 +OP4 E002D7 0 +OP4 E002D8 0 +OP4 E002D9 0 +OP4 E002DA 0 +OP4 E002DB 0 +OP4 E002DC 0 +OP4 E002DD 0 +OP4 E002DE 0 +OP4 E002DF 0 +OP4 E002E0 0 +OP4 E002E1 0 +OP4 E002E2 0 +OP4 E002E3 0 +OP4 E002E4 0 +OP4 E002E5 0 +OP4 E002E6 0 +OP4 E002E7 0 +OP4 E002E8 0 +OP4 E002E9 0 +OP4 E002EA 0 +OP4 E002EB 0 +OP4 E002EC 0 +OP4 E002ED 0 +OP4 E002EE 0 +OP4 E002EF 0 +OP4 E002F0 0 +OP4 E002F1 0 +OP4 E002F2 0 +OP4 E002F3 0 +OP4 E002F4 0 +OP4 E002F5 0 +OP4 E002F6 0 +OP4 E002F7 0 +OP4 E002F8 0 +OP4 E002F9 0 +OP4 E002FA 0 +OP4 E002FB 0 +OP4 E002FC 0 +OP4 E002FD 0 +OP4 E002FE 0 +OP4 E002FF 0 +OP4 E00300 0 +OP4 E00301 0 +OP4 E00302 0 +OP4 E00303 0 +OP4 E00304 0 +OP4 E00305 0 +OP4 E00306 0 +OP4 E00307 0 +OP4 E00308 0 +OP4 E00309 0 +OP4 E0030A 0 +OP4 E0030B 0 +OP4 E0030C 0 +OP4 E0030D 0 +OP4 E0030E 0 +OP4 E0030F 0 +OP4 E00310 0 +OP4 E00311 0 +OP4 E00312 0 +OP4 E00313 0 +OP4 E00314 0 +OP4 E00315 0 +OP4 E00316 0 +OP4 E00317 0 +OP4 E00318 0 +OP4 E00319 0 +OP4 E0031A 0 +OP4 E0031B 0 +OP4 E0031C 0 +OP4 E0031D 0 +OP4 E0031E 0 +OP4 E0031F 0 +OP4 E00320 0 +OP4 E00321 0 +OP4 E00322 0 +OP4 E00323 0 +OP4 E00324 0 +OP4 E00325 0 +OP4 E00326 0 +OP4 E00327 0 +OP4 E00328 0 +OP4 E00329 0 +OP4 E0032A 0 +OP4 E0032B 0 +OP4 E0032C 0 +OP4 E0032D 0 +OP4 E0032E 0 +OP4 E0032F 0 +OP4 E00330 0 +OP4 E00331 0 +OP4 E00332 0 +OP4 E00333 0 +OP4 E00334 0 +OP4 E00335 0 +OP4 E00336 0 +OP4 E00337 0 +OP4 E00338 0 +OP4 E00339 0 +OP4 E0033A 0 +OP4 E0033B 0 +OP4 E0033C 0 +OP4 E0033D 0 +OP4 E0033E 0 +OP4 E0033F 0 +OP4 E00340 0 +OP4 E00341 0 +OP4 E00342 0 +OP4 E00343 0 +OP4 E00344 0 +OP4 E00345 0 +OP4 E00346 0 +OP4 E00347 0 +OP4 E00348 0 +OP4 E00349 0 +OP4 E0034A 0 +OP4 E0034B 0 +OP4 E0034C 0 +OP4 E0034D 0 +OP4 E0034E 0 +OP4 E0034F 0 +OP4 E00350 0 +OP4 E00351 0 +OP4 E00352 0 +OP4 E00353 0 +OP4 E00354 0 +OP4 E00355 0 +OP4 E00356 0 +OP4 E00357 0 +OP4 E00358 0 +OP4 E00359 0 +OP4 E0035A 0 +OP4 E0035B 0 +OP4 E0035C 0 +OP4 E0035D 0 +OP4 E0035E 0 +OP4 E0035F 0 +OP4 E00360 0 +OP4 E00361 0 +OP4 E00362 0 +OP4 E00363 0 +OP4 E00364 0 +OP4 E00365 0 +OP4 E00366 0 +OP4 E00367 0 +OP4 E00368 0 +OP4 E00369 0 +OP4 E0036A 0 +OP4 E0036B 0 +OP4 E0036C 0 +OP4 E0036D 0 +OP4 E0036E 0 +OP4 E0036F 0 +OP4 E00370 0 +OP4 E00371 0 +OP4 E00372 0 +OP4 E00373 0 +OP4 E00374 0 +OP4 E00375 0 +OP4 E00376 0 +OP4 E00377 0 +OP4 E00378 0 +OP4 E00379 0 +OP4 E0037A 0 +OP4 E0037B 0 +OP4 E0037C 0 +OP4 E0037D 0 +OP4 E0037E 0 +OP4 E0037F 0 +OP4 E00380 0 +OP4 E00381 0 +OP4 E00382 0 +OP4 E00383 0 +OP4 E00384 0 +OP4 E00385 0 +OP4 E00386 0 +OP4 E00387 0 +OP4 E00388 0 +OP4 E00389 0 +OP4 E0038A 0 +OP4 E0038B 0 +OP4 E0038C 0 +OP4 E0038D 0 +OP4 E0038E 0 +OP4 E0038F 0 +OP4 E00390 0 +OP4 E00391 0 +OP4 E00392 0 +OP4 E00393 0 +OP4 E00394 0 +OP4 E00395 0 +OP4 E00396 0 +OP4 E00397 0 +OP4 E00398 0 +OP4 E00399 0 +OP4 E0039A 0 +OP4 E0039B 0 +OP4 E0039C 0 +OP4 E0039D 0 +OP4 E0039E 0 +OP4 E0039F 0 +OP4 E003A0 0 +OP4 E003A1 0 +OP4 E003A2 0 +OP4 E003A3 0 +OP4 E003A4 0 +OP4 E003A5 0 +OP4 E003A6 0 +OP4 E003A7 0 +OP4 E003A8 0 +OP4 E003A9 0 +OP4 E003AA 0 +OP4 E003AB 0 +OP4 E003AC 0 +OP4 E003AD 0 +OP4 E003AE 0 +OP4 E003AF 0 +OP4 E003B0 0 +OP4 E003B1 0 +OP4 E003B2 0 +OP4 E003B3 0 +OP4 E003B4 0 +OP4 E003B5 0 +OP4 E003B6 0 +OP4 E003B7 0 +OP4 E003B8 0 +OP4 E003B9 0 +OP4 E003BA 0 +OP4 E003BB 0 +OP4 E003BC 0 +OP4 E003BD 0 +OP4 E003BE 0 +OP4 E003BF 0 +OP4 E003C0 0 +OP4 E003C1 0 +OP4 E003C2 0 +OP4 E003C3 0 +OP4 E003C4 0 +OP4 E003C5 0 +OP4 E003C6 0 +OP4 E003C7 0 +OP4 E003C8 0 +OP4 E003C9 0 +OP4 E003CA 0 +OP4 E003CB 0 +OP4 E003CC 0 +OP4 E003CD 0 +OP4 E003CE 0 +OP4 E003CF 0 +OP4 E003D0 0 +OP4 E003D1 0 +OP4 E003D2 0 +OP4 E003D3 0 +OP4 E003D4 0 +OP4 E003D5 0 +OP4 E003D6 0 +OP4 E003D7 0 +OP4 E003D8 0 +OP4 E003D9 0 +OP4 E003DA 0 +OP4 E003DB 0 +OP4 E003DC 0 +OP4 E003DD 0 +OP4 E003DE 0 +OP4 E003DF 0 +OP4 E003E0 0 +OP4 E003E1 0 +OP4 E003E2 0 +OP4 E003E3 0 +OP4 E003E4 0 +OP4 E003E5 0 +OP4 E003E6 0 +OP4 E003E7 0 +OP4 E003E8 0 +OP4 E003E9 0 +OP4 E003EA 0 +OP4 E003EB 0 +OP4 E003EC 0 +OP4 E003ED 0 +OP4 E003EE 0 +OP4 E003EF 0 +OP4 E003F0 0 +OP4 E003F1 0 +OP4 E003F2 0 +OP4 E003F3 0 +OP4 E003F4 0 +OP4 E003F5 0 +OP4 E003F6 0 +OP4 E003F7 0 +OP4 E003F8 0 +OP4 E003F9 0 +OP4 E003FA 0 +OP4 E003FB 0 +OP4 E003FC 0 +OP4 E003FD 0 +OP4 E003FE 0 +OP4 E003FF 0 +OP4 E00400 0 +OP4 E00401 0 +OP4 E00402 0 +OP4 E00403 0 +OP4 E00404 0 +OP4 E00405 0 +OP4 E00406 0 +OP4 E00407 0 +OP4 E00408 0 +OP4 E00409 0 +OP4 E0040A 0 +OP4 E0040B 0 +OP4 E0040C 0 +OP4 E0040D 0 +OP4 E0040E 0 +OP4 E0040F 0 +OP4 E00410 0 +OP4 E00411 0 +OP4 E00412 0 +OP4 E00413 0 +OP4 E00414 0 +OP4 E00415 0 +OP4 E00416 0 +OP4 E00417 0 +OP4 E00418 0 +OP4 E00419 0 +OP4 E0041A 0 +OP4 E0041B 0 +OP4 E0041C 0 +OP4 E0041D 0 +OP4 E0041E 0 +OP4 E0041F 0 +OP4 E00420 0 +OP4 E00421 0 +OP4 E00422 0 +OP4 E00423 0 +OP4 E00424 0 +OP4 E00425 0 +OP4 E00426 0 +OP4 E00427 0 +OP4 E00428 0 +OP4 E00429 0 +OP4 E0042A 0 +OP4 E0042B 0 +OP4 E0042C 0 +OP4 E0042D 0 +OP4 E0042E 0 +OP4 E0042F 0 +OP4 E00430 0 +OP4 E00431 0 +OP4 E00432 0 +OP4 E00433 0 +OP4 E00434 0 +OP4 E00435 0 +OP4 E00436 0 +OP4 E00437 0 +OP4 E00438 0 +OP4 E00439 0 +OP4 E0043A 0 +OP4 E0043B 0 +OP4 E0043C 0 +OP4 E0043D 0 +OP4 E0043E 0 +OP4 E0043F 0 +OP4 E00440 0 +OP4 E00441 0 +OP4 E00442 0 +OP4 E00443 0 +OP4 E00444 0 +OP4 E00445 0 +OP4 E00446 0 +OP4 E00447 0 +OP4 E00448 0 +OP4 E00449 0 +OP4 E0044A 0 +OP4 E0044B 0 +OP4 E0044C 0 +OP4 E0044D 0 +OP4 E0044E 0 +OP4 E0044F 0 +OP4 E00450 0 +OP4 E00451 0 +OP4 E00452 0 +OP4 E00453 0 +OP4 E00454 0 +OP4 E00455 0 +OP4 E00456 0 +OP4 E00457 0 +OP4 E00458 0 +OP4 E00459 0 +OP4 E0045A 0 +OP4 E0045B 0 +OP4 E0045C 0 +OP4 E0045D 0 +OP4 E0045E 0 +OP4 E0045F 0 +OP4 E00460 0 +OP4 E00461 0 +OP4 E00462 0 +OP4 E00463 0 +OP4 E00464 0 +OP4 E00465 0 +OP4 E00466 0 +OP4 E00467 0 +OP4 E00468 0 +OP4 E00469 0 +OP4 E0046A 0 +OP4 E0046B 0 +OP4 E0046C 0 +OP4 E0046D 0 +OP4 E0046E 0 +OP4 E0046F 0 +OP4 E00470 0 +OP4 E00471 0 +OP4 E00472 0 +OP4 E00473 0 +OP4 E00474 0 +OP4 E00475 0 +OP4 E00476 0 +OP4 E00477 0 +OP4 E00478 0 +OP4 E00479 0 +OP4 E0047A 0 +OP4 E0047B 0 +OP4 E0047C 0 +OP4 E0047D 0 +OP4 E0047E 0 +OP4 E0047F 0 +OP4 E00480 0 +OP4 E00481 0 +OP4 E00482 0 +OP4 E00483 0 +OP4 E00484 0 +OP4 E00485 0 +OP4 E00486 0 +OP4 E00487 0 +OP4 E00488 0 +OP4 E00489 0 +OP4 E0048A 0 +OP4 E0048B 0 +OP4 E0048C 0 +OP4 E0048D 0 +OP4 E0048E 0 +OP4 E0048F 0 +OP4 E00490 0 +OP4 E00491 0 +OP4 E00492 0 +OP4 E00493 0 +OP4 E00494 0 +OP4 E00495 0 +OP4 E00496 0 +OP4 E00497 0 +OP4 E00498 0 +OP4 E00499 0 +OP4 E0049A 0 +OP4 E0049B 0 +OP4 E0049C 0 +OP4 E0049D 0 +OP4 E0049E 0 +OP4 E0049F 0 +OP4 E004A0 0 +OP4 E004A1 0 +OP4 E004A2 0 +OP4 E004A3 0 +OP4 E004A4 0 +OP4 E004A5 0 +OP4 E004A6 0 +OP4 E004A7 0 +OP4 E004A8 0 +OP4 E004A9 0 +OP4 E004AA 0 +OP4 E004AB 0 +OP4 E004AC 0 +OP4 E004AD 0 +OP4 E004AE 0 +OP4 E004AF 0 +OP4 E004B0 0 +OP4 E004B1 0 +OP4 E004B2 0 +OP4 E004B3 0 +OP4 E004B4 0 +OP4 E004B5 0 +OP4 E004B6 0 +OP4 E004B7 0 +OP4 E004B8 0 +OP4 E004B9 0 +OP4 E004BA 0 +OP4 E004BB 0 +OP4 E004BC 0 +OP4 E004BD 0 +OP4 E004BE 0 +OP4 E004BF 0 +OP4 E004C0 0 +OP4 E004C1 0 +OP4 E004C2 0 +OP4 E004C3 0 +OP4 E004C4 0 +OP4 E004C5 0 +OP4 E004C6 0 +OP4 E004C7 0 +OP4 E004C8 0 +OP4 E004C9 0 +OP4 E004CA 0 +OP4 E004CB 0 +OP4 E004CC 0 +OP4 E004CD 0 +OP4 E004CE 0 +OP4 E004CF 0 +OP4 E004D0 0 +OP4 E004D1 0 +OP4 E004D2 0 +OP4 E004D3 0 +OP4 E004D4 0 +OP4 E004D5 0 +OP4 E004D6 0 +OP4 E004D7 0 +OP4 E004D8 0 +OP4 E004D9 0 +OP4 E004DA 0 +OP4 E004DB 0 +OP4 E004DC 0 +OP4 E004DD 0 +OP4 E004DE 0 +OP4 E004DF 0 +OP4 E004E0 0 +OP4 E004E1 0 +OP4 E004E2 0 +OP4 E004E3 0 +OP4 E004E4 0 +OP4 E004E5 0 +OP4 E004E6 0 +OP4 E004E7 0 +OP4 E004E8 0 +OP4 E004E9 0 +OP4 E004EA 0 +OP4 E004EB 0 +OP4 E004EC 0 +OP4 E004ED 0 +OP4 E004EE 0 +OP4 E004EF 0 +OP4 E004F0 0 +OP4 E004F1 0 +OP4 E004F2 0 +OP4 E004F3 0 +OP4 E004F4 0 +OP4 E004F5 0 +OP4 E004F6 0 +OP4 E004F7 0 +OP4 E004F8 0 +OP4 E004F9 0 +OP4 E004FA 0 +OP4 E004FB 0 +OP4 E004FC 0 +OP4 E004FD 0 +OP4 E004FE 0 +OP4 E004FF 0 +OP4 E00500 0 +OP4 E00501 0 +OP4 E00502 0 +OP4 E00503 0 +OP4 E00504 0 +OP4 E00505 0 +OP4 E00506 0 +OP4 E00507 0 +OP4 E00508 0 +OP4 E00509 0 +OP4 E0050A 0 +OP4 E0050B 0 +OP4 E0050C 0 +OP4 E0050D 0 +OP4 E0050E 0 +OP4 E0050F 0 +OP4 E00510 0 +OP4 E00511 0 +OP4 E00512 0 +OP4 E00513 0 +OP4 E00514 0 +OP4 E00515 0 +OP4 E00516 0 +OP4 E00517 0 +OP4 E00518 0 +OP4 E00519 0 +OP4 E0051A 0 +OP4 E0051B 0 +OP4 E0051C 0 +OP4 E0051D 0 +OP4 E0051E 0 +OP4 E0051F 0 +OP4 E00520 0 +OP4 E00521 0 +OP4 E00522 0 +OP4 E00523 0 +OP4 E00524 0 +OP4 E00525 0 +OP4 E00526 0 +OP4 E00527 0 +OP4 E00528 0 +OP4 E00529 0 +OP4 E0052A 0 +OP4 E0052B 0 +OP4 E0052C 0 +OP4 E0052D 0 +OP4 E0052E 0 +OP4 E0052F 0 +OP4 E00530 0 +OP4 E00531 0 +OP4 E00532 0 +OP4 E00533 0 +OP4 E00534 0 +OP4 E00535 0 +OP4 E00536 0 +OP4 E00537 0 +OP4 E00538 0 +OP4 E00539 0 +OP4 E0053A 0 +OP4 E0053B 0 +OP4 E0053C 0 +OP4 E0053D 0 +OP4 E0053E 0 +OP4 E0053F 0 +OP4 E00540 0 +OP4 E00541 0 +OP4 E00542 0 +OP4 E00543 0 +OP4 E00544 0 +OP4 E00545 0 +OP4 E00546 0 +OP4 E00547 0 +OP4 E00548 0 +OP4 E00549 0 +OP4 E0054A 0 +OP4 E0054B 0 +OP4 E0054C 0 +OP4 E0054D 0 +OP4 E0054E 0 +OP4 E0054F 0 +OP4 E00550 0 +OP4 E00551 0 +OP4 E00552 0 +OP4 E00553 0 +OP4 E00554 0 +OP4 E00555 0 +OP4 E00556 0 +OP4 E00557 0 +OP4 E00558 0 +OP4 E00559 0 +OP4 E0055A 0 +OP4 E0055B 0 +OP4 E0055C 0 +OP4 E0055D 0 +OP4 E0055E 0 +OP4 E0055F 0 +OP4 E00560 0 +OP4 E00561 0 +OP4 E00562 0 +OP4 E00563 0 +OP4 E00564 0 +OP4 E00565 0 +OP4 E00566 0 +OP4 E00567 0 +OP4 E00568 0 +OP4 E00569 0 +OP4 E0056A 0 +OP4 E0056B 0 +OP4 E0056C 0 +OP4 E0056D 0 +OP4 E0056E 0 +OP4 E0056F 0 +OP4 E00570 0 +OP4 E00571 0 +OP4 E00572 0 +OP4 E00573 0 +OP4 E00574 0 +OP4 E00575 0 +OP4 E00576 0 +OP4 E00577 0 +OP4 E00578 0 +OP4 E00579 0 +OP4 E0057A 0 +OP4 E0057B 0 +OP4 E0057C 0 +OP4 E0057D 0 +OP4 E0057E 0 +OP4 E0057F 0 +OP4 E00580 0 +OP4 E00581 0 +OP4 E00582 0 +OP4 E00583 0 +OP4 E00584 0 +OP4 E00585 0 +OP4 E00586 0 +OP4 E00587 0 +OP4 E00588 0 +OP4 E00589 0 +OP4 E0058A 0 +OP4 E0058B 0 +OP4 E0058C 0 +OP4 E0058D 0 +OP4 E0058E 0 +OP4 E0058F 0 +OP4 E00590 0 +OP4 E00591 0 +OP4 E00592 0 +OP4 E00593 0 +OP4 E00594 0 +OP4 E00595 0 +OP4 E00596 0 +OP4 E00597 0 +OP4 E00598 0 +OP4 E00599 0 +OP4 E0059A 0 +OP4 E0059B 0 +OP4 E0059C 0 +OP4 E0059D 0 +OP4 E0059E 0 +OP4 E0059F 0 +OP4 E005A0 0 +OP4 E005A1 0 +OP4 E005A2 0 +OP4 E005A3 0 +OP4 E005A4 0 +OP4 E005A5 0 +OP4 E005A6 0 +OP4 E005A7 0 +OP4 E005A8 0 +OP4 E005A9 0 +OP4 E005AA 0 +OP4 E005AB 0 +OP4 E005AC 0 +OP4 E005AD 0 +OP4 E005AE 0 +OP4 E005AF 0 +OP4 E005B0 0 +OP4 E005B1 0 +OP4 E005B2 0 +OP4 E005B3 0 +OP4 E005B4 0 +OP4 E005B5 0 +OP4 E005B6 0 +OP4 E005B7 0 +OP4 E005B8 0 +OP4 E005B9 0 +OP4 E005BA 0 +OP4 E005BB 0 +OP4 E005BC 0 +OP4 E005BD 0 +OP4 E005BE 0 +OP4 E005BF 0 +OP4 E005C0 0 +OP4 E005C1 0 +OP4 E005C2 0 +OP4 E005C3 0 +OP4 E005C4 0 +OP4 E005C5 0 +OP4 E005C6 0 +OP4 E005C7 0 +OP4 E005C8 0 +OP4 E005C9 0 +OP4 E005CA 0 +OP4 E005CB 0 +OP4 E005CC 0 +OP4 E005CD 0 +OP4 E005CE 0 +OP4 E005CF 0 +OP4 E005D0 0 +OP4 E005D1 0 +OP4 E005D2 0 +OP4 E005D3 0 +OP4 E005D4 0 +OP4 E005D5 0 +OP4 E005D6 0 +OP4 E005D7 0 +OP4 E005D8 0 +OP4 E005D9 0 +OP4 E005DA 0 +OP4 E005DB 0 +OP4 E005DC 0 +OP4 E005DD 0 +OP4 E005DE 0 +OP4 E005DF 0 +OP4 E005E0 0 +OP4 E005E1 0 +OP4 E005E2 0 +OP4 E005E3 0 +OP4 E005E4 0 +OP4 E005E5 0 +OP4 E005E6 0 +OP4 E005E7 0 +OP4 E005E8 0 +OP4 E005E9 0 +OP4 E005EA 0 +OP4 E005EB 0 +OP4 E005EC 0 +OP4 E005ED 0 +OP4 E005EE 0 +OP4 E005EF 0 +OP4 E005F0 0 +OP4 E005F1 0 +OP4 E005F2 0 +OP4 E005F3 0 +OP4 E005F4 0 +OP4 E005F5 0 +OP4 E005F6 0 +OP4 E005F7 0 +OP4 E005F8 0 +OP4 E005F9 0 +OP4 E005FA 0 +OP4 E005FB 0 +OP4 E005FC 0 +OP4 E005FD 0 +OP4 E005FE 0 +OP4 E005FF 0 +OP4 E00600 0 +OP4 E00601 0 +OP4 E00602 0 +OP4 E00603 0 +OP4 E00604 0 +OP4 E00605 0 +OP4 E00606 0 +OP4 E00607 0 +OP4 E00608 0 +OP4 E00609 0 +OP4 E0060A 0 +OP4 E0060B 0 +OP4 E0060C 0 +OP4 E0060D 0 +OP4 E0060E 0 +OP4 E0060F 0 +OP4 E00610 0 +OP4 E00611 0 +OP4 E00612 0 +OP4 E00613 0 +OP4 E00614 0 +OP4 E00615 0 +OP4 E00616 0 +OP4 E00617 0 +OP4 E00618 0 +OP4 E00619 0 +OP4 E0061A 0 +OP4 E0061B 0 +OP4 E0061C 0 +OP4 E0061D 0 +OP4 E0061E 0 +OP4 E0061F 0 +OP4 E00620 0 +OP4 E00621 0 +OP4 E00622 0 +OP4 E00623 0 +OP4 E00624 0 +OP4 E00625 0 +OP4 E00626 0 +OP4 E00627 0 +OP4 E00628 0 +OP4 E00629 0 +OP4 E0062A 0 +OP4 E0062B 0 +OP4 E0062C 0 +OP4 E0062D 0 +OP4 E0062E 0 +OP4 E0062F 0 +OP4 E00630 0 +OP4 E00631 0 +OP4 E00632 0 +OP4 E00633 0 +OP4 E00634 0 +OP4 E00635 0 +OP4 E00636 0 +OP4 E00637 0 +OP4 E00638 0 +OP4 E00639 0 +OP4 E0063A 0 +OP4 E0063B 0 +OP4 E0063C 0 +OP4 E0063D 0 +OP4 E0063E 0 +OP4 E0063F 0 +OP4 E00640 0 +OP4 E00641 0 +OP4 E00642 0 +OP4 E00643 0 +OP4 E00644 0 +OP4 E00645 0 +OP4 E00646 0 +OP4 E00647 0 +OP4 E00648 0 +OP4 E00649 0 +OP4 E0064A 0 +OP4 E0064B 0 +OP4 E0064C 0 +OP4 E0064D 0 +OP4 E0064E 0 +OP4 E0064F 0 +OP4 E00650 0 +OP4 E00651 0 +OP4 E00652 0 +OP4 E00653 0 +OP4 E00654 0 +OP4 E00655 0 +OP4 E00656 0 +OP4 E00657 0 +OP4 E00658 0 +OP4 E00659 0 +OP4 E0065A 0 +OP4 E0065B 0 +OP4 E0065C 0 +OP4 E0065D 0 +OP4 E0065E 0 +OP4 E0065F 0 +OP4 E00660 0 +OP4 E00661 0 +OP4 E00662 0 +OP4 E00663 0 +OP4 E00664 0 +OP4 E00665 0 +OP4 E00666 0 +OP4 E00667 0 +OP4 E00668 0 +OP4 E00669 0 +OP4 E0066A 0 +OP4 E0066B 0 +OP4 E0066C 0 +OP4 E0066D 0 +OP4 E0066E 0 +OP4 E0066F 0 +OP4 E00670 0 +OP4 E00671 0 +OP4 E00672 0 +OP4 E00673 0 +OP4 E00674 0 +OP4 E00675 0 +OP4 E00676 0 +OP4 E00677 0 +OP4 E00678 0 +OP4 E00679 0 +OP4 E0067A 0 +OP4 E0067B 0 +OP4 E0067C 0 +OP4 E0067D 0 +OP4 E0067E 0 +OP4 E0067F 0 +OP4 E00680 0 +OP4 E00681 0 +OP4 E00682 0 +OP4 E00683 0 +OP4 E00684 0 +OP4 E00685 0 +OP4 E00686 0 +OP4 E00687 0 +OP4 E00688 0 +OP4 E00689 0 +OP4 E0068A 0 +OP4 E0068B 0 +OP4 E0068C 0 +OP4 E0068D 0 +OP4 E0068E 0 +OP4 E0068F 0 +OP4 E00690 0 +OP4 E00691 0 +OP4 E00692 0 +OP4 E00693 0 +OP4 E00694 0 +OP4 E00695 0 +OP4 E00696 0 +OP4 E00697 0 +OP4 E00698 0 +OP4 E00699 0 +OP4 E0069A 0 +OP4 E0069B 0 +OP4 E0069C 0 +OP4 E0069D 0 +OP4 E0069E 0 +OP4 E0069F 0 +OP4 E006A0 0 +OP4 E006A1 0 +OP4 E006A2 0 +OP4 E006A3 0 +OP4 E006A4 0 +OP4 E006A5 0 +OP4 E006A6 0 +OP4 E006A7 0 +OP4 E006A8 0 +OP4 E006A9 0 +OP4 E006AA 0 +OP4 E006AB 0 +OP4 E006AC 0 +OP4 E006AD 0 +OP4 E006AE 0 +OP4 E006AF 0 +OP4 E006B0 0 +OP4 E006B1 0 +OP4 E006B2 0 +OP4 E006B3 0 +OP4 E006B4 0 +OP4 E006B5 0 +OP4 E006B6 0 +OP4 E006B7 0 +OP4 E006B8 0 +OP4 E006B9 0 +OP4 E006BA 0 +OP4 E006BB 0 +OP4 E006BC 0 +OP4 E006BD 0 +OP4 E006BE 0 +OP4 E006BF 0 +OP4 E006C0 0 +OP4 E006C1 0 +OP4 E006C2 0 +OP4 E006C3 0 +OP4 E006C4 0 +OP4 E006C5 0 +OP4 E006C6 0 +OP4 E006C7 0 +OP4 E006C8 0 +OP4 E006C9 0 +OP4 E006CA 0 +OP4 E006CB 0 +OP4 E006CC 0 +OP4 E006CD 0 +OP4 E006CE 0 +OP4 E006CF 0 +OP4 E006D0 0 +OP4 E006D1 0 +OP4 E006D2 0 +OP4 E006D3 0 +OP4 E006D4 0 +OP4 E006D5 0 +OP4 E006D6 0 +OP4 E006D7 0 +OP4 E006D8 0 +OP4 E006D9 0 +OP4 E006DA 0 +OP4 E006DB 0 +OP4 E006DC 0 +OP4 E006DD 0 +OP4 E006DE 0 +OP4 E006DF 0 +OP4 E006E0 0 +OP4 E006E1 0 +OP4 E006E2 0 +OP4 E006E3 0 +OP4 E006E4 0 +OP4 E006E5 0 +OP4 E006E6 0 +OP4 E006E7 0 +OP4 E006E8 0 +OP4 E006E9 0 +OP4 E006EA 0 +OP4 E006EB 0 +OP4 E006EC 0 +OP4 E006ED 0 +OP4 E006EE 0 +OP4 E006EF 0 +OP4 E006F0 0 +OP4 E006F1 0 +OP4 E006F2 0 +OP4 E006F3 0 +OP4 E006F4 0 +OP4 E006F5 0 +OP4 E006F6 0 +OP4 E006F7 0 +OP4 E006F8 0 +OP4 E006F9 0 +OP4 E006FA 0 +OP4 E006FB 0 +OP4 E006FC 0 +OP4 E006FD 0 +OP4 E006FE 0 +OP4 E006FF 0 +OP4 E00700 0 +OP4 E00701 0 +OP4 E00702 0 +OP4 E00703 0 +OP4 E00704 0 +OP4 E00705 0 +OP4 E00706 0 +OP4 E00707 0 +OP4 E00708 0 +OP4 E00709 0 +OP4 E0070A 0 +OP4 E0070B 0 +OP4 E0070C 0 +OP4 E0070D 0 +OP4 E0070E 0 +OP4 E0070F 0 +OP4 E00710 0 +OP4 E00711 0 +OP4 E00712 0 +OP4 E00713 0 +OP4 E00714 0 +OP4 E00715 0 +OP4 E00716 0 +OP4 E00717 0 +OP4 E00718 0 +OP4 E00719 0 +OP4 E0071A 0 +OP4 E0071B 0 +OP4 E0071C 0 +OP4 E0071D 0 +OP4 E0071E 0 +OP4 E0071F 0 +OP4 E00720 0 +OP4 E00721 0 +OP4 E00722 0 +OP4 E00723 0 +OP4 E00724 0 +OP4 E00725 0 +OP4 E00726 0 +OP4 E00727 0 +OP4 E00728 0 +OP4 E00729 0 +OP4 E0072A 0 +OP4 E0072B 0 +OP4 E0072C 0 +OP4 E0072D 0 +OP4 E0072E 0 +OP4 E0072F 0 +OP4 E00730 0 +OP4 E00731 0 +OP4 E00732 0 +OP4 E00733 0 +OP4 E00734 0 +OP4 E00735 0 +OP4 E00736 0 +OP4 E00737 0 +OP4 E00738 0 +OP4 E00739 0 +OP4 E0073A 0 +OP4 E0073B 0 +OP4 E0073C 0 +OP4 E0073D 0 +OP4 E0073E 0 +OP4 E0073F 0 +OP4 E00740 0 +OP4 E00741 0 +OP4 E00742 0 +OP4 E00743 0 +OP4 E00744 0 +OP4 E00745 0 +OP4 E00746 0 +OP4 E00747 0 +OP4 E00748 0 +OP4 E00749 0 +OP4 E0074A 0 +OP4 E0074B 0 +OP4 E0074C 0 +OP4 E0074D 0 +OP4 E0074E 0 +OP4 E0074F 0 +OP4 E00750 0 +OP4 E00751 0 +OP4 E00752 0 +OP4 E00753 0 +OP4 E00754 0 +OP4 E00755 0 +OP4 E00756 0 +OP4 E00757 0 +OP4 E00758 0 +OP4 E00759 0 +OP4 E0075A 0 +OP4 E0075B 0 +OP4 E0075C 0 +OP4 E0075D 0 +OP4 E0075E 0 +OP4 E0075F 0 +OP4 E00760 0 +OP4 E00761 0 +OP4 E00762 0 +OP4 E00763 0 +OP4 E00764 0 +OP4 E00765 0 +OP4 E00766 0 +OP4 E00767 0 +OP4 E00768 0 +OP4 E00769 0 +OP4 E0076A 0 +OP4 E0076B 0 +OP4 E0076C 0 +OP4 E0076D 0 +OP4 E0076E 0 +OP4 E0076F 0 +OP4 E00770 0 +OP4 E00771 0 +OP4 E00772 0 +OP4 E00773 0 +OP4 E00774 0 +OP4 E00775 0 +OP4 E00776 0 +OP4 E00777 0 +OP4 E00778 0 +OP4 E00779 0 +OP4 E0077A 0 +OP4 E0077B 0 +OP4 E0077C 0 +OP4 E0077D 0 +OP4 E0077E 0 +OP4 E0077F 0 +OP4 E00780 0 +OP4 E00781 0 +OP4 E00782 0 +OP4 E00783 0 +OP4 E00784 0 +OP4 E00785 0 +OP4 E00786 0 +OP4 E00787 0 +OP4 E00788 0 +OP4 E00789 0 +OP4 E0078A 0 +OP4 E0078B 0 +OP4 E0078C 0 +OP4 E0078D 0 +OP4 E0078E 0 +OP4 E0078F 0 +OP4 E00790 0 +OP4 E00791 0 +OP4 E00792 0 +OP4 E00793 0 +OP4 E00794 0 +OP4 E00795 0 +OP4 E00796 0 +OP4 E00797 0 +OP4 E00798 0 +OP4 E00799 0 +OP4 E0079A 0 +OP4 E0079B 0 +OP4 E0079C 0 +OP4 E0079D 0 +OP4 E0079E 0 +OP4 E0079F 0 +OP4 E007A0 0 +OP4 E007A1 0 +OP4 E007A2 0 +OP4 E007A3 0 +OP4 E007A4 0 +OP4 E007A5 0 +OP4 E007A6 0 +OP4 E007A7 0 +OP4 E007A8 0 +OP4 E007A9 0 +OP4 E007AA 0 +OP4 E007AB 0 +OP4 E007AC 0 +OP4 E007AD 0 +OP4 E007AE 0 +OP4 E007AF 0 +OP4 E007B0 0 +OP4 E007B1 0 +OP4 E007B2 0 +OP4 E007B3 0 +OP4 E007B4 0 +OP4 E007B5 0 +OP4 E007B6 0 +OP4 E007B7 0 +OP4 E007B8 0 +OP4 E007B9 0 +OP4 E007BA 0 +OP4 E007BB 0 +OP4 E007BC 0 +OP4 E007BD 0 +OP4 E007BE 0 +OP4 E007BF 0 +OP4 E007C0 0 +OP4 E007C1 0 +OP4 E007C2 0 +OP4 E007C3 0 +OP4 E007C4 0 +OP4 E007C5 0 +OP4 E007C6 0 +OP4 E007C7 0 +OP4 E007C8 0 +OP4 E007C9 0 +OP4 E007CA 0 +OP4 E007CB 0 +OP4 E007CC 0 +OP4 E007CD 0 +OP4 E007CE 0 +OP4 E007CF 0 +OP4 E007D0 0 +OP4 E007D1 0 +OP4 E007D2 0 +OP4 E007D3 0 +OP4 E007D4 0 +OP4 E007D5 0 +OP4 E007D6 0 +OP4 E007D7 0 +OP4 E007D8 0 +OP4 E007D9 0 +OP4 E007DA 0 +OP4 E007DB 0 +OP4 E007DC 0 +OP4 E007DD 0 +OP4 E007DE 0 +OP4 E007DF 0 +OP4 E007E0 0 +OP4 E007E1 0 +OP4 E007E2 0 +OP4 E007E3 0 +OP4 E007E4 0 +OP4 E007E5 0 +OP4 E007E6 0 +OP4 E007E7 0 +OP4 E007E8 0 +OP4 E007E9 0 +OP4 E007EA 0 +OP4 E007EB 0 +OP4 E007EC 0 +OP4 E007ED 0 +OP4 E007EE 0 +OP4 E007EF 0 +OP4 E007F0 0 +OP4 E007F1 0 +OP4 E007F2 0 +OP4 E007F3 0 +OP4 E007F4 0 +OP4 E007F5 0 +OP4 E007F6 0 +OP4 E007F7 0 +OP4 E007F8 0 +OP4 E007F9 0 +OP4 E007FA 0 +OP4 E007FB 0 +OP4 E007FC 0 +OP4 E007FD 0 +OP4 E007FE 0 +OP4 E007FF 0 +OP4 E00800 0 +OP4 E00801 0 +OP4 E00802 0 +OP4 E00803 0 +OP4 E00804 0 +OP4 E00805 0 +OP4 E00806 0 +OP4 E00807 0 +OP4 E00808 0 +OP4 E00809 0 +OP4 E0080A 0 +OP4 E0080B 0 +OP4 E0080C 0 +OP4 E0080D 0 +OP4 E0080E 0 +OP4 E0080F 0 +OP4 E00810 0 +OP4 E00811 0 +OP4 E00812 0 +OP4 E00813 0 +OP4 E00814 0 +OP4 E00815 0 +OP4 E00816 0 +OP4 E00817 0 +OP4 E00818 0 +OP4 E00819 0 +OP4 E0081A 0 +OP4 E0081B 0 +OP4 E0081C 0 +OP4 E0081D 0 +OP4 E0081E 0 +OP4 E0081F 0 +OP4 E00820 0 +OP4 E00821 0 +OP4 E00822 0 +OP4 E00823 0 +OP4 E00824 0 +OP4 E00825 0 +OP4 E00826 0 +OP4 E00827 0 +OP4 E00828 0 +OP4 E00829 0 +OP4 E0082A 0 +OP4 E0082B 0 +OP4 E0082C 0 +OP4 E0082D 0 +OP4 E0082E 0 +OP4 E0082F 0 +OP4 E00830 0 +OP4 E00831 0 +OP4 E00832 0 +OP4 E00833 0 +OP4 E00834 0 +OP4 E00835 0 +OP4 E00836 0 +OP4 E00837 0 +OP4 E00838 0 +OP4 E00839 0 +OP4 E0083A 0 +OP4 E0083B 0 +OP4 E0083C 0 +OP4 E0083D 0 +OP4 E0083E 0 +OP4 E0083F 0 +OP4 E00840 0 +OP4 E00841 0 +OP4 E00842 0 +OP4 E00843 0 +OP4 E00844 0 +OP4 E00845 0 +OP4 E00846 0 +OP4 E00847 0 +OP4 E00848 0 +OP4 E00849 0 +OP4 E0084A 0 +OP4 E0084B 0 +OP4 E0084C 0 +OP4 E0084D 0 +OP4 E0084E 0 +OP4 E0084F 0 +OP4 E00850 0 +OP4 E00851 0 +OP4 E00852 0 +OP4 E00853 0 +OP4 E00854 0 +OP4 E00855 0 +OP4 E00856 0 +OP4 E00857 0 +OP4 E00858 0 +OP4 E00859 0 +OP4 E0085A 0 +OP4 E0085B 0 +OP4 E0085C 0 +OP4 E0085D 0 +OP4 E0085E 0 +OP4 E0085F 0 +OP4 E00860 0 +OP4 E00861 0 +OP4 E00862 0 +OP4 E00863 0 +OP4 E00864 0 +OP4 E00865 0 +OP4 E00866 0 +OP4 E00867 0 +OP4 E00868 0 +OP4 E00869 0 +OP4 E0086A 0 +OP4 E0086B 0 +OP4 E0086C 0 +OP4 E0086D 0 +OP4 E0086E 0 +OP4 E0086F 0 +OP4 E00870 0 +OP4 E00871 0 +OP4 E00872 0 +OP4 E00873 0 +OP4 E00874 0 +OP4 E00875 0 +OP4 E00876 0 +OP4 E00877 0 +OP4 E00878 0 +OP4 E00879 0 +OP4 E0087A 0 +OP4 E0087B 0 +OP4 E0087C 0 +OP4 E0087D 0 +OP4 E0087E 0 +OP4 E0087F 0 +OP4 E00880 0 +OP4 E00881 0 +OP4 E00882 0 +OP4 E00883 0 +OP4 E00884 0 +OP4 E00885 0 +OP4 E00886 0 +OP4 E00887 0 +OP4 E00888 0 +OP4 E00889 0 +OP4 E0088A 0 +OP4 E0088B 0 +OP4 E0088C 0 +OP4 E0088D 0 +OP4 E0088E 0 +OP4 E0088F 0 +OP4 E00890 0 +OP4 E00891 0 +OP4 E00892 0 +OP4 E00893 0 +OP4 E00894 0 +OP4 E00895 0 +OP4 E00896 0 +OP4 E00897 0 +OP4 E00898 0 +OP4 E00899 0 +OP4 E0089A 0 +OP4 E0089B 0 +OP4 E0089C 0 +OP4 E0089D 0 +OP4 E0089E 0 +OP4 E0089F 0 +OP4 E008A0 0 +OP4 E008A1 0 +OP4 E008A2 0 +OP4 E008A3 0 +OP4 E008A4 0 +OP4 E008A5 0 +OP4 E008A6 0 +OP4 E008A7 0 +OP4 E008A8 0 +OP4 E008A9 0 +OP4 E008AA 0 +OP4 E008AB 0 +OP4 E008AC 0 +OP4 E008AD 0 +OP4 E008AE 0 +OP4 E008AF 0 +OP4 E008B0 0 +OP4 E008B1 0 +OP4 E008B2 0 +OP4 E008B3 0 +OP4 E008B4 0 +OP4 E008B5 0 +OP4 E008B6 0 +OP4 E008B7 0 +OP4 E008B8 0 +OP4 E008B9 0 +OP4 E008BA 0 +OP4 E008BB 0 +OP4 E008BC 0 +OP4 E008BD 0 +OP4 E008BE 0 +OP4 E008BF 0 +OP4 E008C0 0 +OP4 E008C1 0 +OP4 E008C2 0 +OP4 E008C3 0 +OP4 E008C4 0 +OP4 E008C5 0 +OP4 E008C6 0 +OP4 E008C7 0 +OP4 E008C8 0 +OP4 E008C9 0 +OP4 E008CA 0 +OP4 E008CB 0 +OP4 E008CC 0 +OP4 E008CD 0 +OP4 E008CE 0 +OP4 E008CF 0 +OP4 E008D0 0 +OP4 E008D1 0 +OP4 E008D2 0 +OP4 E008D3 0 +OP4 E008D4 0 +OP4 E008D5 0 +OP4 E008D6 0 +OP4 E008D7 0 +OP4 E008D8 0 +OP4 E008D9 0 +OP4 E008DA 0 +OP4 E008DB 0 +OP4 E008DC 0 +OP4 E008DD 0 +OP4 E008DE 0 +OP4 E008DF 0 +OP4 E008E0 0 +OP4 E008E1 0 +OP4 E008E2 0 +OP4 E008E3 0 +OP4 E008E4 0 +OP4 E008E5 0 +OP4 E008E6 0 +OP4 E008E7 0 +OP4 E008E8 0 +OP4 E008E9 0 +OP4 E008EA 0 +OP4 E008EB 0 +OP4 E008EC 0 +OP4 E008ED 0 +OP4 E008EE 0 +OP4 E008EF 0 +OP4 E008F0 0 +OP4 E008F1 0 +OP4 E008F2 0 +OP4 E008F3 0 +OP4 E008F4 0 +OP4 E008F5 0 +OP4 E008F6 0 +OP4 E008F7 0 +OP4 E008F8 0 +OP4 E008F9 0 +OP4 E008FA 0 +OP4 E008FB 0 +OP4 E008FC 0 +OP4 E008FD 0 +OP4 E008FE 0 +OP4 E008FF 0 +OP4 E00900 0 +OP4 E00901 0 +OP4 E00902 0 +OP4 E00903 0 +OP4 E00904 0 +OP4 E00905 0 +OP4 E00906 0 +OP4 E00907 0 +OP4 E00908 0 +OP4 E00909 0 +OP4 E0090A 0 +OP4 E0090B 0 +OP4 E0090C 0 +OP4 E0090D 0 +OP4 E0090E 0 +OP4 E0090F 0 +OP4 E00910 0 +OP4 E00911 0 +OP4 E00912 0 +OP4 E00913 0 +OP4 E00914 0 +OP4 E00915 0 +OP4 E00916 0 +OP4 E00917 0 +OP4 E00918 0 +OP4 E00919 0 +OP4 E0091A 0 +OP4 E0091B 0 +OP4 E0091C 0 +OP4 E0091D 0 +OP4 E0091E 0 +OP4 E0091F 0 +OP4 E00920 0 +OP4 E00921 0 +OP4 E00922 0 +OP4 E00923 0 +OP4 E00924 0 +OP4 E00925 0 +OP4 E00926 0 +OP4 E00927 0 +OP4 E00928 0 +OP4 E00929 0 +OP4 E0092A 0 +OP4 E0092B 0 +OP4 E0092C 0 +OP4 E0092D 0 +OP4 E0092E 0 +OP4 E0092F 0 +OP4 E00930 0 +OP4 E00931 0 +OP4 E00932 0 +OP4 E00933 0 +OP4 E00934 0 +OP4 E00935 0 +OP4 E00936 0 +OP4 E00937 0 +OP4 E00938 0 +OP4 E00939 0 +OP4 E0093A 0 +OP4 E0093B 0 +OP4 E0093C 0 +OP4 E0093D 0 +OP4 E0093E 0 +OP4 E0093F 0 +OP4 E00940 0 +OP4 E00941 0 +OP4 E00942 0 +OP4 E00943 0 +OP4 E00944 0 +OP4 E00945 0 +OP4 E00946 0 +OP4 E00947 0 +OP4 E00948 0 +OP4 E00949 0 +OP4 E0094A 0 +OP4 E0094B 0 +OP4 E0094C 0 +OP4 E0094D 0 +OP4 E0094E 0 +OP4 E0094F 0 +OP4 E00950 0 +OP4 E00951 0 +OP4 E00952 0 +OP4 E00953 0 +OP4 E00954 0 +OP4 E00955 0 +OP4 E00956 0 +OP4 E00957 0 +OP4 E00958 0 +OP4 E00959 0 +OP4 E0095A 0 +OP4 E0095B 0 +OP4 E0095C 0 +OP4 E0095D 0 +OP4 E0095E 0 +OP4 E0095F 0 +OP4 E00960 0 +OP4 E00961 0 +OP4 E00962 0 +OP4 E00963 0 +OP4 E00964 0 +OP4 E00965 0 +OP4 E00966 0 +OP4 E00967 0 +OP4 E00968 0 +OP4 E00969 0 +OP4 E0096A 0 +OP4 E0096B 0 +OP4 E0096C 0 +OP4 E0096D 0 +OP4 E0096E 0 +OP4 E0096F 0 +OP4 E00970 0 +OP4 E00971 0 +OP4 E00972 0 +OP4 E00973 0 +OP4 E00974 0 +OP4 E00975 0 +OP4 E00976 0 +OP4 E00977 0 +OP4 E00978 0 +OP4 E00979 0 +OP4 E0097A 0 +OP4 E0097B 0 +OP4 E0097C 0 +OP4 E0097D 0 +OP4 E0097E 0 +OP4 E0097F 0 +OP4 E00980 0 +OP4 E00981 0 +OP4 E00982 0 +OP4 E00983 0 +OP4 E00984 0 +OP4 E00985 0 +OP4 E00986 0 +OP4 E00987 0 +OP4 E00988 0 +OP4 E00989 0 +OP4 E0098A 0 +OP4 E0098B 0 +OP4 E0098C 0 +OP4 E0098D 0 +OP4 E0098E 0 +OP4 E0098F 0 +OP4 E00990 0 +OP4 E00991 0 +OP4 E00992 0 +OP4 E00993 0 +OP4 E00994 0 +OP4 E00995 0 +OP4 E00996 0 +OP4 E00997 0 +OP4 E00998 0 +OP4 E00999 0 +OP4 E0099A 0 +OP4 E0099B 0 +OP4 E0099C 0 +OP4 E0099D 0 +OP4 E0099E 0 +OP4 E0099F 0 +OP4 E009A0 0 +OP4 E009A1 0 +OP4 E009A2 0 +OP4 E009A3 0 +OP4 E009A4 0 +OP4 E009A5 0 +OP4 E009A6 0 +OP4 E009A7 0 +OP4 E009A8 0 +OP4 E009A9 0 +OP4 E009AA 0 +OP4 E009AB 0 +OP4 E009AC 0 +OP4 E009AD 0 +OP4 E009AE 0 +OP4 E009AF 0 +OP4 E009B0 0 +OP4 E009B1 0 +OP4 E009B2 0 +OP4 E009B3 0 +OP4 E009B4 0 +OP4 E009B5 0 +OP4 E009B6 0 +OP4 E009B7 0 +OP4 E009B8 0 +OP4 E009B9 0 +OP4 E009BA 0 +OP4 E009BB 0 +OP4 E009BC 0 +OP4 E009BD 0 +OP4 E009BE 0 +OP4 E009BF 0 +OP4 E009C0 0 +OP4 E009C1 0 +OP4 E009C2 0 +OP4 E009C3 0 +OP4 E009C4 0 +OP4 E009C5 0 +OP4 E009C6 0 +OP4 E009C7 0 +OP4 E009C8 0 +OP4 E009C9 0 +OP4 E009CA 0 +OP4 E009CB 0 +OP4 E009CC 0 +OP4 E009CD 0 +OP4 E009CE 0 +OP4 E009CF 0 +OP4 E009D0 0 +OP4 E009D1 0 +OP4 E009D2 0 +OP4 E009D3 0 +OP4 E009D4 0 +OP4 E009D5 0 +OP4 E009D6 0 +OP4 E009D7 0 +OP4 E009D8 0 +OP4 E009D9 0 +OP4 E009DA 0 +OP4 E009DB 0 +OP4 E009DC 0 +OP4 E009DD 0 +OP4 E009DE 0 +OP4 E009DF 0 +OP4 E009E0 0 +OP4 E009E1 0 +OP4 E009E2 0 +OP4 E009E3 0 +OP4 E009E4 0 +OP4 E009E5 0 +OP4 E009E6 0 +OP4 E009E7 0 +OP4 E009E8 0 +OP4 E009E9 0 +OP4 E009EA 0 +OP4 E009EB 0 +OP4 E009EC 0 +OP4 E009ED 0 +OP4 E009EE 0 +OP4 E009EF 0 +OP4 E009F0 0 +OP4 E009F1 0 +OP4 E009F2 0 +OP4 E009F3 0 +OP4 E009F4 0 +OP4 E009F5 0 +OP4 E009F6 0 +OP4 E009F7 0 +OP4 E009F8 0 +OP4 E009F9 0 +OP4 E009FA 0 +OP4 E009FB 0 +OP4 E009FC 0 +OP4 E009FD 0 +OP4 E009FE 0 +OP4 E009FF 0 +OP4 E00A00 0 +OP4 E00A01 0 +OP4 E00A02 0 +OP4 E00A03 0 +OP4 E00A04 0 +OP4 E00A05 0 +OP4 E00A06 0 +OP4 E00A07 0 +OP4 E00A08 0 +OP4 E00A09 0 +OP4 E00A0A 0 +OP4 E00A0B 0 +OP4 E00A0C 0 +OP4 E00A0D 0 +OP4 E00A0E 0 +OP4 E00A0F 0 +OP4 E00A10 0 +OP4 E00A11 0 +OP4 E00A12 0 +OP4 E00A13 0 +OP4 E00A14 0 +OP4 E00A15 0 +OP4 E00A16 0 +OP4 E00A17 0 +OP4 E00A18 0 +OP4 E00A19 0 +OP4 E00A1A 0 +OP4 E00A1B 0 +OP4 E00A1C 0 +OP4 E00A1D 0 +OP4 E00A1E 0 +OP4 E00A1F 0 +OP4 E00A20 0 +OP4 E00A21 0 +OP4 E00A22 0 +OP4 E00A23 0 +OP4 E00A24 0 +OP4 E00A25 0 +OP4 E00A26 0 +OP4 E00A27 0 +OP4 E00A28 0 +OP4 E00A29 0 +OP4 E00A2A 0 +OP4 E00A2B 0 +OP4 E00A2C 0 +OP4 E00A2D 0 +OP4 E00A2E 0 +OP4 E00A2F 0 +OP4 E00A30 0 +OP4 E00A31 0 +OP4 E00A32 0 +OP4 E00A33 0 +OP4 E00A34 0 +OP4 E00A35 0 +OP4 E00A36 0 +OP4 E00A37 0 +OP4 E00A38 0 +OP4 E00A39 0 +OP4 E00A3A 0 +OP4 E00A3B 0 +OP4 E00A3C 0 +OP4 E00A3D 0 +OP4 E00A3E 0 +OP4 E00A3F 0 +OP4 E00A40 0 +OP4 E00A41 0 +OP4 E00A42 0 +OP4 E00A43 0 +OP4 E00A44 0 +OP4 E00A45 0 +OP4 E00A46 0 +OP4 E00A47 0 +OP4 E00A48 0 +OP4 E00A49 0 +OP4 E00A4A 0 +OP4 E00A4B 0 +OP4 E00A4C 0 +OP4 E00A4D 0 +OP4 E00A4E 0 +OP4 E00A4F 0 +OP4 E00A50 0 +OP4 E00A51 0 +OP4 E00A52 0 +OP4 E00A53 0 +OP4 E00A54 0 +OP4 E00A55 0 +OP4 E00A56 0 +OP4 E00A57 0 +OP4 E00A58 0 +OP4 E00A59 0 +OP4 E00A5A 0 +OP4 E00A5B 0 +OP4 E00A5C 0 +OP4 E00A5D 0 +OP4 E00A5E 0 +OP4 E00A5F 0 +OP4 E00A60 0 +OP4 E00A61 0 +OP4 E00A62 0 +OP4 E00A63 0 +OP4 E00A64 0 +OP4 E00A65 0 +OP4 E00A66 0 +OP4 E00A67 0 +OP4 E00A68 0 +OP4 E00A69 0 +OP4 E00A6A 0 +OP4 E00A6B 0 +OP4 E00A6C 0 +OP4 E00A6D 0 +OP4 E00A6E 0 +OP4 E00A6F 0 +OP4 E00A70 0 +OP4 E00A71 0 +OP4 E00A72 0 +OP4 E00A73 0 +OP4 E00A74 0 +OP4 E00A75 0 +OP4 E00A76 0 +OP4 E00A77 0 +OP4 E00A78 0 +OP4 E00A79 0 +OP4 E00A7A 0 +OP4 E00A7B 0 +OP4 E00A7C 0 +OP4 E00A7D 0 +OP4 E00A7E 0 +OP4 E00A7F 0 +OP4 E00A80 0 +OP4 E00A81 0 +OP4 E00A82 0 +OP4 E00A83 0 +OP4 E00A84 0 +OP4 E00A85 0 +OP4 E00A86 0 +OP4 E00A87 0 +OP4 E00A88 0 +OP4 E00A89 0 +OP4 E00A8A 0 +OP4 E00A8B 0 +OP4 E00A8C 0 +OP4 E00A8D 0 +OP4 E00A8E 0 +OP4 E00A8F 0 +OP4 E00A90 0 +OP4 E00A91 0 +OP4 E00A92 0 +OP4 E00A93 0 +OP4 E00A94 0 +OP4 E00A95 0 +OP4 E00A96 0 +OP4 E00A97 0 +OP4 E00A98 0 +OP4 E00A99 0 +OP4 E00A9A 0 +OP4 E00A9B 0 +OP4 E00A9C 0 +OP4 E00A9D 0 +OP4 E00A9E 0 +OP4 E00A9F 0 +OP4 E00AA0 0 +OP4 E00AA1 0 +OP4 E00AA2 0 +OP4 E00AA3 0 +OP4 E00AA4 0 +OP4 E00AA5 0 +OP4 E00AA6 0 +OP4 E00AA7 0 +OP4 E00AA8 0 +OP4 E00AA9 0 +OP4 E00AAA 0 +OP4 E00AAB 0 +OP4 E00AAC 0 +OP4 E00AAD 0 +OP4 E00AAE 0 +OP4 E00AAF 0 +OP4 E00AB0 0 +OP4 E00AB1 0 +OP4 E00AB2 0 +OP4 E00AB3 0 +OP4 E00AB4 0 +OP4 E00AB5 0 +OP4 E00AB6 0 +OP4 E00AB7 0 +OP4 E00AB8 0 +OP4 E00AB9 0 +OP4 E00ABA 0 +OP4 E00ABB 0 +OP4 E00ABC 0 +OP4 E00ABD 0 +OP4 E00ABE 0 +OP4 E00ABF 0 +OP4 E00AC0 0 +OP4 E00AC1 0 +OP4 E00AC2 0 +OP4 E00AC3 0 +OP4 E00AC4 0 +OP4 E00AC5 0 +OP4 E00AC6 0 +OP4 E00AC7 0 +OP4 E00AC8 0 +OP4 E00AC9 0 +OP4 E00ACA 0 +OP4 E00ACB 0 +OP4 E00ACC 0 +OP4 E00ACD 0 +OP4 E00ACE 0 +OP4 E00ACF 0 +OP4 E00AD0 0 +OP4 E00AD1 0 +OP4 E00AD2 0 +OP4 E00AD3 0 +OP4 E00AD4 0 +OP4 E00AD5 0 +OP4 E00AD6 0 +OP4 E00AD7 0 +OP4 E00AD8 0 +OP4 E00AD9 0 +OP4 E00ADA 0 +OP4 E00ADB 0 +OP4 E00ADC 0 +OP4 E00ADD 0 +OP4 E00ADE 0 +OP4 E00ADF 0 +OP4 E00AE0 0 +OP4 E00AE1 0 +OP4 E00AE2 0 +OP4 E00AE3 0 +OP4 E00AE4 0 +OP4 E00AE5 0 +OP4 E00AE6 0 +OP4 E00AE7 0 +OP4 E00AE8 0 +OP4 E00AE9 0 +OP4 E00AEA 0 +OP4 E00AEB 0 +OP4 E00AEC 0 +OP4 E00AED 0 +OP4 E00AEE 0 +OP4 E00AEF 0 +OP4 E00AF0 0 +OP4 E00AF1 0 +OP4 E00AF2 0 +OP4 E00AF3 0 +OP4 E00AF4 0 +OP4 E00AF5 0 +OP4 E00AF6 0 +OP4 E00AF7 0 +OP4 E00AF8 0 +OP4 E00AF9 0 +OP4 E00AFA 0 +OP4 E00AFB 0 +OP4 E00AFC 0 +OP4 E00AFD 0 +OP4 E00AFE 0 +OP4 E00AFF 0 +OP4 E00B00 0 +OP4 E00B01 0 +OP4 E00B02 0 +OP4 E00B03 0 +OP4 E00B04 0 +OP4 E00B05 0 +OP4 E00B06 0 +OP4 E00B07 0 +OP4 E00B08 0 +OP4 E00B09 0 +OP4 E00B0A 0 +OP4 E00B0B 0 +OP4 E00B0C 0 +OP4 E00B0D 0 +OP4 E00B0E 0 +OP4 E00B0F 0 +OP4 E00B10 0 +OP4 E00B11 0 +OP4 E00B12 0 +OP4 E00B13 0 +OP4 E00B14 0 +OP4 E00B15 0 +OP4 E00B16 0 +OP4 E00B17 0 +OP4 E00B18 0 +OP4 E00B19 0 +OP4 E00B1A 0 +OP4 E00B1B 0 +OP4 E00B1C 0 +OP4 E00B1D 0 +OP4 E00B1E 0 +OP4 E00B1F 0 +OP4 E00B20 0 +OP4 E00B21 0 +OP4 E00B22 0 +OP4 E00B23 0 +OP4 E00B24 0 +OP4 E00B25 0 +OP4 E00B26 0 +OP4 E00B27 0 +OP4 E00B28 0 +OP4 E00B29 0 +OP4 E00B2A 0 +OP4 E00B2B 0 +OP4 E00B2C 0 +OP4 E00B2D 0 +OP4 E00B2E 0 +OP4 E00B2F 0 +OP4 E00B30 0 +OP4 E00B31 0 +OP4 E00B32 0 +OP4 E00B33 0 +OP4 E00B34 0 +OP4 E00B35 0 +OP4 E00B36 0 +OP4 E00B37 0 +OP4 E00B38 0 +OP4 E00B39 0 +OP4 E00B3A 0 +OP4 E00B3B 0 +OP4 E00B3C 0 +OP4 E00B3D 0 +OP4 E00B3E 0 +OP4 E00B3F 0 +OP4 E00B40 0 +OP4 E00B41 0 +OP4 E00B42 0 +OP4 E00B43 0 +OP4 E00B44 0 +OP4 E00B45 0 +OP4 E00B46 0 +OP4 E00B47 0 +OP4 E00B48 0 +OP4 E00B49 0 +OP4 E00B4A 0 +OP4 E00B4B 0 +OP4 E00B4C 0 +OP4 E00B4D 0 +OP4 E00B4E 0 +OP4 E00B4F 0 +OP4 E00B50 0 +OP4 E00B51 0 +OP4 E00B52 0 +OP4 E00B53 0 +OP4 E00B54 0 +OP4 E00B55 0 +OP4 E00B56 0 +OP4 E00B57 0 +OP4 E00B58 0 +OP4 E00B59 0 +OP4 E00B5A 0 +OP4 E00B5B 0 +OP4 E00B5C 0 +OP4 E00B5D 0 +OP4 E00B5E 0 +OP4 E00B5F 0 +OP4 E00B60 0 +OP4 E00B61 0 +OP4 E00B62 0 +OP4 E00B63 0 +OP4 E00B64 0 +OP4 E00B65 0 +OP4 E00B66 0 +OP4 E00B67 0 +OP4 E00B68 0 +OP4 E00B69 0 +OP4 E00B6A 0 +OP4 E00B6B 0 +OP4 E00B6C 0 +OP4 E00B6D 0 +OP4 E00B6E 0 +OP4 E00B6F 0 +OP4 E00B70 0 +OP4 E00B71 0 +OP4 E00B72 0 +OP4 E00B73 0 +OP4 E00B74 0 +OP4 E00B75 0 +OP4 E00B76 0 +OP4 E00B77 0 +OP4 E00B78 0 +OP4 E00B79 0 +OP4 E00B7A 0 +OP4 E00B7B 0 +OP4 E00B7C 0 +OP4 E00B7D 0 +OP4 E00B7E 0 +OP4 E00B7F 0 +OP4 E00B80 0 +OP4 E00B81 0 +OP4 E00B82 0 +OP4 E00B83 0 +OP4 E00B84 0 +OP4 E00B85 0 +OP4 E00B86 0 +OP4 E00B87 0 +OP4 E00B88 0 +OP4 E00B89 0 +OP4 E00B8A 0 +OP4 E00B8B 0 +OP4 E00B8C 0 +OP4 E00B8D 0 +OP4 E00B8E 0 +OP4 E00B8F 0 +OP4 E00B90 0 +OP4 E00B91 0 +OP4 E00B92 0 +OP4 E00B93 0 +OP4 E00B94 0 +OP4 E00B95 0 +OP4 E00B96 0 +OP4 E00B97 0 +OP4 E00B98 0 +OP4 E00B99 0 +OP4 E00B9A 0 +OP4 E00B9B 0 +OP4 E00B9C 0 +OP4 E00B9D 0 +OP4 E00B9E 0 +OP4 E00B9F 0 +OP4 E00BA0 0 +OP4 E00BA1 0 +OP4 E00BA2 0 +OP4 E00BA3 0 +OP4 E00BA4 0 +OP4 E00BA5 0 +OP4 E00BA6 0 +OP4 E00BA7 0 +OP4 E00BA8 0 +OP4 E00BA9 0 +OP4 E00BAA 0 +OP4 E00BAB 0 +OP4 E00BAC 0 +OP4 E00BAD 0 +OP4 E00BAE 0 +OP4 E00BAF 0 +OP4 E00BB0 0 +OP4 E00BB1 0 +OP4 E00BB2 0 +OP4 E00BB3 0 +OP4 E00BB4 0 +OP4 E00BB5 0 +OP4 E00BB6 0 +OP4 E00BB7 0 +OP4 E00BB8 0 +OP4 E00BB9 0 +OP4 E00BBA 0 +OP4 E00BBB 0 +OP4 E00BBC 0 +OP4 E00BBD 0 +OP4 E00BBE 0 +OP4 E00BBF 0 +OP4 E00BC0 0 +OP4 E00BC1 0 +OP4 E00BC2 0 +OP4 E00BC3 0 +OP4 E00BC4 0 +OP4 E00BC5 0 +OP4 E00BC6 0 +OP4 E00BC7 0 +OP4 E00BC8 0 +OP4 E00BC9 0 +OP4 E00BCA 0 +OP4 E00BCB 0 +OP4 E00BCC 0 +OP4 E00BCD 0 +OP4 E00BCE 0 +OP4 E00BCF 0 +OP4 E00BD0 0 +OP4 E00BD1 0 +OP4 E00BD2 0 +OP4 E00BD3 0 +OP4 E00BD4 0 +OP4 E00BD5 0 +OP4 E00BD6 0 +OP4 E00BD7 0 +OP4 E00BD8 0 +OP4 E00BD9 0 +OP4 E00BDA 0 +OP4 E00BDB 0 +OP4 E00BDC 0 +OP4 E00BDD 0 +OP4 E00BDE 0 +OP4 E00BDF 0 +OP4 E00BE0 0 +OP4 E00BE1 0 +OP4 E00BE2 0 +OP4 E00BE3 0 +OP4 E00BE4 0 +OP4 E00BE5 0 +OP4 E00BE6 0 +OP4 E00BE7 0 +OP4 E00BE8 0 +OP4 E00BE9 0 +OP4 E00BEA 0 +OP4 E00BEB 0 +OP4 E00BEC 0 +OP4 E00BED 0 +OP4 E00BEE 0 +OP4 E00BEF 0 +OP4 E00BF0 0 +OP4 E00BF1 0 +OP4 E00BF2 0 +OP4 E00BF3 0 +OP4 E00BF4 0 +OP4 E00BF5 0 +OP4 E00BF6 0 +OP4 E00BF7 0 +OP4 E00BF8 0 +OP4 E00BF9 0 +OP4 E00BFA 0 +OP4 E00BFB 0 +OP4 E00BFC 0 +OP4 E00BFD 0 +OP4 E00BFE 0 +OP4 E00BFF 0 +OP4 E00C00 0 +OP4 E00C01 0 +OP4 E00C02 0 +OP4 E00C03 0 +OP4 E00C04 0 +OP4 E00C05 0 +OP4 E00C06 0 +OP4 E00C07 0 +OP4 E00C08 0 +OP4 E00C09 0 +OP4 E00C0A 0 +OP4 E00C0B 0 +OP4 E00C0C 0 +OP4 E00C0D 0 +OP4 E00C0E 0 +OP4 E00C0F 0 +OP4 E00C10 0 +OP4 E00C11 0 +OP4 E00C12 0 +OP4 E00C13 0 +OP4 E00C14 0 +OP4 E00C15 0 +OP4 E00C16 0 +OP4 E00C17 0 +OP4 E00C18 0 +OP4 E00C19 0 +OP4 E00C1A 0 +OP4 E00C1B 0 +OP4 E00C1C 0 +OP4 E00C1D 0 +OP4 E00C1E 0 +OP4 E00C1F 0 +OP4 E00C20 0 +OP4 E00C21 0 +OP4 E00C22 0 +OP4 E00C23 0 +OP4 E00C24 0 +OP4 E00C25 0 +OP4 E00C26 0 +OP4 E00C27 0 +OP4 E00C28 0 +OP4 E00C29 0 +OP4 E00C2A 0 +OP4 E00C2B 0 +OP4 E00C2C 0 +OP4 E00C2D 0 +OP4 E00C2E 0 +OP4 E00C2F 0 +OP4 E00C30 0 +OP4 E00C31 0 +OP4 E00C32 0 +OP4 E00C33 0 +OP4 E00C34 0 +OP4 E00C35 0 +OP4 E00C36 0 +OP4 E00C37 0 +OP4 E00C38 0 +OP4 E00C39 0 +OP4 E00C3A 0 +OP4 E00C3B 0 +OP4 E00C3C 0 +OP4 E00C3D 0 +OP4 E00C3E 0 +OP4 E00C3F 0 +OP4 E00C40 0 +OP4 E00C41 0 +OP4 E00C42 0 +OP4 E00C43 0 +OP4 E00C44 0 +OP4 E00C45 0 +OP4 E00C46 0 +OP4 E00C47 0 +OP4 E00C48 0 +OP4 E00C49 0 +OP4 E00C4A 0 +OP4 E00C4B 0 +OP4 E00C4C 0 +OP4 E00C4D 0 +OP4 E00C4E 0 +OP4 E00C4F 0 +OP4 E00C50 0 +OP4 E00C51 0 +OP4 E00C52 0 +OP4 E00C53 0 +OP4 E00C54 0 +OP4 E00C55 0 +OP4 E00C56 0 +OP4 E00C57 0 +OP4 E00C58 0 +OP4 E00C59 0 +OP4 E00C5A 0 +OP4 E00C5B 0 +OP4 E00C5C 0 +OP4 E00C5D 0 +OP4 E00C5E 0 +OP4 E00C5F 0 +OP4 E00C60 0 +OP4 E00C61 0 +OP4 E00C62 0 +OP4 E00C63 0 +OP4 E00C64 0 +OP4 E00C65 0 +OP4 E00C66 0 +OP4 E00C67 0 +OP4 E00C68 0 +OP4 E00C69 0 +OP4 E00C6A 0 +OP4 E00C6B 0 +OP4 E00C6C 0 +OP4 E00C6D 0 +OP4 E00C6E 0 +OP4 E00C6F 0 +OP4 E00C70 0 +OP4 E00C71 0 +OP4 E00C72 0 +OP4 E00C73 0 +OP4 E00C74 0 +OP4 E00C75 0 +OP4 E00C76 0 +OP4 E00C77 0 +OP4 E00C78 0 +OP4 E00C79 0 +OP4 E00C7A 0 +OP4 E00C7B 0 +OP4 E00C7C 0 +OP4 E00C7D 0 +OP4 E00C7E 0 +OP4 E00C7F 0 +OP4 E00C80 0 +OP4 E00C81 0 +OP4 E00C82 0 +OP4 E00C83 0 +OP4 E00C84 0 +OP4 E00C85 0 +OP4 E00C86 0 +OP4 E00C87 0 +OP4 E00C88 0 +OP4 E00C89 0 +OP4 E00C8A 0 +OP4 E00C8B 0 +OP4 E00C8C 0 +OP4 E00C8D 0 +OP4 E00C8E 0 +OP4 E00C8F 0 +OP4 E00C90 0 +OP4 E00C91 0 +OP4 E00C92 0 +OP4 E00C93 0 +OP4 E00C94 0 +OP4 E00C95 0 +OP4 E00C96 0 +OP4 E00C97 0 +OP4 E00C98 0 +OP4 E00C99 0 +OP4 E00C9A 0 +OP4 E00C9B 0 +OP4 E00C9C 0 +OP4 E00C9D 0 +OP4 E00C9E 0 +OP4 E00C9F 0 +OP4 E00CA0 0 +OP4 E00CA1 0 +OP4 E00CA2 0 +OP4 E00CA3 0 +OP4 E00CA4 0 +OP4 E00CA5 0 +OP4 E00CA6 0 +OP4 E00CA7 0 +OP4 E00CA8 0 +OP4 E00CA9 0 +OP4 E00CAA 0 +OP4 E00CAB 0 +OP4 E00CAC 0 +OP4 E00CAD 0 +OP4 E00CAE 0 +OP4 E00CAF 0 +OP4 E00CB0 0 +OP4 E00CB1 0 +OP4 E00CB2 0 +OP4 E00CB3 0 +OP4 E00CB4 0 +OP4 E00CB5 0 +OP4 E00CB6 0 +OP4 E00CB7 0 +OP4 E00CB8 0 +OP4 E00CB9 0 +OP4 E00CBA 0 +OP4 E00CBB 0 +OP4 E00CBC 0 +OP4 E00CBD 0 +OP4 E00CBE 0 +OP4 E00CBF 0 +OP4 E00CC0 0 +OP4 E00CC1 0 +OP4 E00CC2 0 +OP4 E00CC3 0 +OP4 E00CC4 0 +OP4 E00CC5 0 +OP4 E00CC6 0 +OP4 E00CC7 0 +OP4 E00CC8 0 +OP4 E00CC9 0 +OP4 E00CCA 0 +OP4 E00CCB 0 +OP4 E00CCC 0 +OP4 E00CCD 0 +OP4 E00CCE 0 +OP4 E00CCF 0 +OP4 E00CD0 0 +OP4 E00CD1 0 +OP4 E00CD2 0 +OP4 E00CD3 0 +OP4 E00CD4 0 +OP4 E00CD5 0 +OP4 E00CD6 0 +OP4 E00CD7 0 +OP4 E00CD8 0 +OP4 E00CD9 0 +OP4 E00CDA 0 +OP4 E00CDB 0 +OP4 E00CDC 0 +OP4 E00CDD 0 +OP4 E00CDE 0 +OP4 E00CDF 0 +OP4 E00CE0 0 +OP4 E00CE1 0 +OP4 E00CE2 0 +OP4 E00CE3 0 +OP4 E00CE4 0 +OP4 E00CE5 0 +OP4 E00CE6 0 +OP4 E00CE7 0 +OP4 E00CE8 0 +OP4 E00CE9 0 +OP4 E00CEA 0 +OP4 E00CEB 0 +OP4 E00CEC 0 +OP4 E00CED 0 +OP4 E00CEE 0 +OP4 E00CEF 0 +OP4 E00CF0 0 +OP4 E00CF1 0 +OP4 E00CF2 0 +OP4 E00CF3 0 +OP4 E00CF4 0 +OP4 E00CF5 0 +OP4 E00CF6 0 +OP4 E00CF7 0 +OP4 E00CF8 0 +OP4 E00CF9 0 +OP4 E00CFA 0 +OP4 E00CFB 0 +OP4 E00CFC 0 +OP4 E00CFD 0 +OP4 E00CFE 0 +OP4 E00CFF 0 +OP4 E00D00 0 +OP4 E00D01 0 +OP4 E00D02 0 +OP4 E00D03 0 +OP4 E00D04 0 +OP4 E00D05 0 +OP4 E00D06 0 +OP4 E00D07 0 +OP4 E00D08 0 +OP4 E00D09 0 +OP4 E00D0A 0 +OP4 E00D0B 0 +OP4 E00D0C 0 +OP4 E00D0D 0 +OP4 E00D0E 0 +OP4 E00D0F 0 +OP4 E00D10 0 +OP4 E00D11 0 +OP4 E00D12 0 +OP4 E00D13 0 +OP4 E00D14 0 +OP4 E00D15 0 +OP4 E00D16 0 +OP4 E00D17 0 +OP4 E00D18 0 +OP4 E00D19 0 +OP4 E00D1A 0 +OP4 E00D1B 0 +OP4 E00D1C 0 +OP4 E00D1D 0 +OP4 E00D1E 0 +OP4 E00D1F 0 +OP4 E00D20 0 +OP4 E00D21 0 +OP4 E00D22 0 +OP4 E00D23 0 +OP4 E00D24 0 +OP4 E00D25 0 +OP4 E00D26 0 +OP4 E00D27 0 +OP4 E00D28 0 +OP4 E00D29 0 +OP4 E00D2A 0 +OP4 E00D2B 0 +OP4 E00D2C 0 +OP4 E00D2D 0 +OP4 E00D2E 0 +OP4 E00D2F 0 +OP4 E00D30 0 +OP4 E00D31 0 +OP4 E00D32 0 +OP4 E00D33 0 +OP4 E00D34 0 +OP4 E00D35 0 +OP4 E00D36 0 +OP4 E00D37 0 +OP4 E00D38 0 +OP4 E00D39 0 +OP4 E00D3A 0 +OP4 E00D3B 0 +OP4 E00D3C 0 +OP4 E00D3D 0 +OP4 E00D3E 0 +OP4 E00D3F 0 +OP4 E00D40 0 +OP4 E00D41 0 +OP4 E00D42 0 +OP4 E00D43 0 +OP4 E00D44 0 +OP4 E00D45 0 +OP4 E00D46 0 +OP4 E00D47 0 +OP4 E00D48 0 +OP4 E00D49 0 +OP4 E00D4A 0 +OP4 E00D4B 0 +OP4 E00D4C 0 +OP4 E00D4D 0 +OP4 E00D4E 0 +OP4 E00D4F 0 +OP4 E00D50 0 +OP4 E00D51 0 +OP4 E00D52 0 +OP4 E00D53 0 +OP4 E00D54 0 +OP4 E00D55 0 +OP4 E00D56 0 +OP4 E00D57 0 +OP4 E00D58 0 +OP4 E00D59 0 +OP4 E00D5A 0 +OP4 E00D5B 0 +OP4 E00D5C 0 +OP4 E00D5D 0 +OP4 E00D5E 0 +OP4 E00D5F 0 +OP4 E00D60 0 +OP4 E00D61 0 +OP4 E00D62 0 +OP4 E00D63 0 +OP4 E00D64 0 +OP4 E00D65 0 +OP4 E00D66 0 +OP4 E00D67 0 +OP4 E00D68 0 +OP4 E00D69 0 +OP4 E00D6A 0 +OP4 E00D6B 0 +OP4 E00D6C 0 +OP4 E00D6D 0 +OP4 E00D6E 0 +OP4 E00D6F 0 +OP4 E00D70 0 +OP4 E00D71 0 +OP4 E00D72 0 +OP4 E00D73 0 +OP4 E00D74 0 +OP4 E00D75 0 +OP4 E00D76 0 +OP4 E00D77 0 +OP4 E00D78 0 +OP4 E00D79 0 +OP4 E00D7A 0 +OP4 E00D7B 0 +OP4 E00D7C 0 +OP4 E00D7D 0 +OP4 E00D7E 0 +OP4 E00D7F 0 +OP4 E00D80 0 +OP4 E00D81 0 +OP4 E00D82 0 +OP4 E00D83 0 +OP4 E00D84 0 +OP4 E00D85 0 +OP4 E00D86 0 +OP4 E00D87 0 +OP4 E00D88 0 +OP4 E00D89 0 +OP4 E00D8A 0 +OP4 E00D8B 0 +OP4 E00D8C 0 +OP4 E00D8D 0 +OP4 E00D8E 0 +OP4 E00D8F 0 +OP4 E00D90 0 +OP4 E00D91 0 +OP4 E00D92 0 +OP4 E00D93 0 +OP4 E00D94 0 +OP4 E00D95 0 +OP4 E00D96 0 +OP4 E00D97 0 +OP4 E00D98 0 +OP4 E00D99 0 +OP4 E00D9A 0 +OP4 E00D9B 0 +OP4 E00D9C 0 +OP4 E00D9D 0 +OP4 E00D9E 0 +OP4 E00D9F 0 +OP4 E00DA0 0 +OP4 E00DA1 0 +OP4 E00DA2 0 +OP4 E00DA3 0 +OP4 E00DA4 0 +OP4 E00DA5 0 +OP4 E00DA6 0 +OP4 E00DA7 0 +OP4 E00DA8 0 +OP4 E00DA9 0 +OP4 E00DAA 0 +OP4 E00DAB 0 +OP4 E00DAC 0 +OP4 E00DAD 0 +OP4 E00DAE 0 +OP4 E00DAF 0 +OP4 E00DB0 0 +OP4 E00DB1 0 +OP4 E00DB2 0 +OP4 E00DB3 0 +OP4 E00DB4 0 +OP4 E00DB5 0 +OP4 E00DB6 0 +OP4 E00DB7 0 +OP4 E00DB8 0 +OP4 E00DB9 0 +OP4 E00DBA 0 +OP4 E00DBB 0 +OP4 E00DBC 0 +OP4 E00DBD 0 +OP4 E00DBE 0 +OP4 E00DBF 0 +OP4 E00DC0 0 +OP4 E00DC1 0 +OP4 E00DC2 0 +OP4 E00DC3 0 +OP4 E00DC4 0 +OP4 E00DC5 0 +OP4 E00DC6 0 +OP4 E00DC7 0 +OP4 E00DC8 0 +OP4 E00DC9 0 +OP4 E00DCA 0 +OP4 E00DCB 0 +OP4 E00DCC 0 +OP4 E00DCD 0 +OP4 E00DCE 0 +OP4 E00DCF 0 +OP4 E00DD0 0 +OP4 E00DD1 0 +OP4 E00DD2 0 +OP4 E00DD3 0 +OP4 E00DD4 0 +OP4 E00DD5 0 +OP4 E00DD6 0 +OP4 E00DD7 0 +OP4 E00DD8 0 +OP4 E00DD9 0 +OP4 E00DDA 0 +OP4 E00DDB 0 +OP4 E00DDC 0 +OP4 E00DDD 0 +OP4 E00DDE 0 +OP4 E00DDF 0 +OP4 E00DE0 0 +OP4 E00DE1 0 +OP4 E00DE2 0 +OP4 E00DE3 0 +OP4 E00DE4 0 +OP4 E00DE5 0 +OP4 E00DE6 0 +OP4 E00DE7 0 +OP4 E00DE8 0 +OP4 E00DE9 0 +OP4 E00DEA 0 +OP4 E00DEB 0 +OP4 E00DEC 0 +OP4 E00DED 0 +OP4 E00DEE 0 +OP4 E00DEF 0 +OP4 E00DF0 0 +OP4 E00DF1 0 +OP4 E00DF2 0 +OP4 E00DF3 0 +OP4 E00DF4 0 +OP4 E00DF5 0 +OP4 E00DF6 0 +OP4 E00DF7 0 +OP4 E00DF8 0 +OP4 E00DF9 0 +OP4 E00DFA 0 +OP4 E00DFB 0 +OP4 E00DFC 0 +OP4 E00DFD 0 +OP4 E00DFE 0 +OP4 E00DFF 0 +OP4 E00E00 0 +OP4 E00E01 0 +OP4 E00E02 0 +OP4 E00E03 0 +OP4 E00E04 0 +OP4 E00E05 0 +OP4 E00E06 0 +OP4 E00E07 0 +OP4 E00E08 0 +OP4 E00E09 0 +OP4 E00E0A 0 +OP4 E00E0B 0 +OP4 E00E0C 0 +OP4 E00E0D 0 +OP4 E00E0E 0 +OP4 E00E0F 0 +OP4 E00E10 0 +OP4 E00E11 0 +OP4 E00E12 0 +OP4 E00E13 0 +OP4 E00E14 0 +OP4 E00E15 0 +OP4 E00E16 0 +OP4 E00E17 0 +OP4 E00E18 0 +OP4 E00E19 0 +OP4 E00E1A 0 +OP4 E00E1B 0 +OP4 E00E1C 0 +OP4 E00E1D 0 +OP4 E00E1E 0 +OP4 E00E1F 0 +OP4 E00E20 0 +OP4 E00E21 0 +OP4 E00E22 0 +OP4 E00E23 0 +OP4 E00E24 0 +OP4 E00E25 0 +OP4 E00E26 0 +OP4 E00E27 0 +OP4 E00E28 0 +OP4 E00E29 0 +OP4 E00E2A 0 +OP4 E00E2B 0 +OP4 E00E2C 0 +OP4 E00E2D 0 +OP4 E00E2E 0 +OP4 E00E2F 0 +OP4 E00E30 0 +OP4 E00E31 0 +OP4 E00E32 0 +OP4 E00E33 0 +OP4 E00E34 0 +OP4 E00E35 0 +OP4 E00E36 0 +OP4 E00E37 0 +OP4 E00E38 0 +OP4 E00E39 0 +OP4 E00E3A 0 +OP4 E00E3B 0 +OP4 E00E3C 0 +OP4 E00E3D 0 +OP4 E00E3E 0 +OP4 E00E3F 0 +OP4 E00E40 0 +OP4 E00E41 0 +OP4 E00E42 0 +OP4 E00E43 0 +OP4 E00E44 0 +OP4 E00E45 0 +OP4 E00E46 0 +OP4 E00E47 0 +OP4 E00E48 0 +OP4 E00E49 0 +OP4 E00E4A 0 +OP4 E00E4B 0 +OP4 E00E4C 0 +OP4 E00E4D 0 +OP4 E00E4E 0 +OP4 E00E4F 0 +OP4 E00E50 0 +OP4 E00E51 0 +OP4 E00E52 0 +OP4 E00E53 0 +OP4 E00E54 0 +OP4 E00E55 0 +OP4 E00E56 0 +OP4 E00E57 0 +OP4 E00E58 0 +OP4 E00E59 0 +OP4 E00E5A 0 +OP4 E00E5B 0 +OP4 E00E5C 0 +OP4 E00E5D 0 +OP4 E00E5E 0 +OP4 E00E5F 0 +OP4 E00E60 0 +OP4 E00E61 0 +OP4 E00E62 0 +OP4 E00E63 0 +OP4 E00E64 0 +OP4 E00E65 0 +OP4 E00E66 0 +OP4 E00E67 0 +OP4 E00E68 0 +OP4 E00E69 0 +OP4 E00E6A 0 +OP4 E00E6B 0 +OP4 E00E6C 0 +OP4 E00E6D 0 +OP4 E00E6E 0 +OP4 E00E6F 0 +OP4 E00E70 0 +OP4 E00E71 0 +OP4 E00E72 0 +OP4 E00E73 0 +OP4 E00E74 0 +OP4 E00E75 0 +OP4 E00E76 0 +OP4 E00E77 0 +OP4 E00E78 0 +OP4 E00E79 0 +OP4 E00E7A 0 +OP4 E00E7B 0 +OP4 E00E7C 0 +OP4 E00E7D 0 +OP4 E00E7E 0 +OP4 E00E7F 0 +OP4 E00E80 0 +OP4 E00E81 0 +OP4 E00E82 0 +OP4 E00E83 0 +OP4 E00E84 0 +OP4 E00E85 0 +OP4 E00E86 0 +OP4 E00E87 0 +OP4 E00E88 0 +OP4 E00E89 0 +OP4 E00E8A 0 +OP4 E00E8B 0 +OP4 E00E8C 0 +OP4 E00E8D 0 +OP4 E00E8E 0 +OP4 E00E8F 0 +OP4 E00E90 0 +OP4 E00E91 0 +OP4 E00E92 0 +OP4 E00E93 0 +OP4 E00E94 0 +OP4 E00E95 0 +OP4 E00E96 0 +OP4 E00E97 0 +OP4 E00E98 0 +OP4 E00E99 0 +OP4 E00E9A 0 +OP4 E00E9B 0 +OP4 E00E9C 0 +OP4 E00E9D 0 +OP4 E00E9E 0 +OP4 E00E9F 0 +OP4 E00EA0 0 +OP4 E00EA1 0 +OP4 E00EA2 0 +OP4 E00EA3 0 +OP4 E00EA4 0 +OP4 E00EA5 0 +OP4 E00EA6 0 +OP4 E00EA7 0 +OP4 E00EA8 0 +OP4 E00EA9 0 +OP4 E00EAA 0 +OP4 E00EAB 0 +OP4 E00EAC 0 +OP4 E00EAD 0 +OP4 E00EAE 0 +OP4 E00EAF 0 +OP4 E00EB0 0 +OP4 E00EB1 0 +OP4 E00EB2 0 +OP4 E00EB3 0 +OP4 E00EB4 0 +OP4 E00EB5 0 +OP4 E00EB6 0 +OP4 E00EB7 0 +OP4 E00EB8 0 +OP4 E00EB9 0 +OP4 E00EBA 0 +OP4 E00EBB 0 +OP4 E00EBC 0 +OP4 E00EBD 0 +OP4 E00EBE 0 +OP4 E00EBF 0 +OP4 E00EC0 0 +OP4 E00EC1 0 +OP4 E00EC2 0 +OP4 E00EC3 0 +OP4 E00EC4 0 +OP4 E00EC5 0 +OP4 E00EC6 0 +OP4 E00EC7 0 +OP4 E00EC8 0 +OP4 E00EC9 0 +OP4 E00ECA 0 +OP4 E00ECB 0 +OP4 E00ECC 0 +OP4 E00ECD 0 +OP4 E00ECE 0 +OP4 E00ECF 0 +OP4 E00ED0 0 +OP4 E00ED1 0 +OP4 E00ED2 0 +OP4 E00ED3 0 +OP4 E00ED4 0 +OP4 E00ED5 0 +OP4 E00ED6 0 +OP4 E00ED7 0 +OP4 E00ED8 0 +OP4 E00ED9 0 +OP4 E00EDA 0 +OP4 E00EDB 0 +OP4 E00EDC 0 +OP4 E00EDD 0 +OP4 E00EDE 0 +OP4 E00EDF 0 +OP4 E00EE0 0 +OP4 E00EE1 0 +OP4 E00EE2 0 +OP4 E00EE3 0 +OP4 E00EE4 0 +OP4 E00EE5 0 +OP4 E00EE6 0 +OP4 E00EE7 0 +OP4 E00EE8 0 +OP4 E00EE9 0 +OP4 E00EEA 0 +OP4 E00EEB 0 +OP4 E00EEC 0 +OP4 E00EED 0 +OP4 E00EEE 0 +OP4 E00EEF 0 +OP4 E00EF0 0 +OP4 E00EF1 0 +OP4 E00EF2 0 +OP4 E00EF3 0 +OP4 E00EF4 0 +OP4 E00EF5 0 +OP4 E00EF6 0 +OP4 E00EF7 0 +OP4 E00EF8 0 +OP4 E00EF9 0 +OP4 E00EFA 0 +OP4 E00EFB 0 +OP4 E00EFC 0 +OP4 E00EFD 0 +OP4 E00EFE 0 +OP4 E00EFF 0 +OP4 E00F00 0 +OP4 E00F01 0 +OP4 E00F02 0 +OP4 E00F03 0 +OP4 E00F04 0 +OP4 E00F05 0 +OP4 E00F06 0 +OP4 E00F07 0 +OP4 E00F08 0 +OP4 E00F09 0 +OP4 E00F0A 0 +OP4 E00F0B 0 +OP4 E00F0C 0 +OP4 E00F0D 0 +OP4 E00F0E 0 +OP4 E00F0F 0 +OP4 E00F10 0 +OP4 E00F11 0 +OP4 E00F12 0 +OP4 E00F13 0 +OP4 E00F14 0 +OP4 E00F15 0 +OP4 E00F16 0 +OP4 E00F17 0 +OP4 E00F18 0 +OP4 E00F19 0 +OP4 E00F1A 0 +OP4 E00F1B 0 +OP4 E00F1C 0 +OP4 E00F1D 0 +OP4 E00F1E 0 +OP4 E00F1F 0 +OP4 E00F20 0 +OP4 E00F21 0 +OP4 E00F22 0 +OP4 E00F23 0 +OP4 E00F24 0 +OP4 E00F25 0 +OP4 E00F26 0 +OP4 E00F27 0 +OP4 E00F28 0 +OP4 E00F29 0 +OP4 E00F2A 0 +OP4 E00F2B 0 +OP4 E00F2C 0 +OP4 E00F2D 0 +OP4 E00F2E 0 +OP4 E00F2F 0 +OP4 E00F30 0 +OP4 E00F31 0 +OP4 E00F32 0 +OP4 E00F33 0 +OP4 E00F34 0 +OP4 E00F35 0 +OP4 E00F36 0 +OP4 E00F37 0 +OP4 E00F38 0 +OP4 E00F39 0 +OP4 E00F3A 0 +OP4 E00F3B 0 +OP4 E00F3C 0 +OP4 E00F3D 0 +OP4 E00F3E 0 +OP4 E00F3F 0 +OP4 E00F40 0 +OP4 E00F41 0 +OP4 E00F42 0 +OP4 E00F43 0 +OP4 E00F44 0 +OP4 E00F45 0 +OP4 E00F46 0 +OP4 E00F47 0 +OP4 E00F48 0 +OP4 E00F49 0 +OP4 E00F4A 0 +OP4 E00F4B 0 +OP4 E00F4C 0 +OP4 E00F4D 0 +OP4 E00F4E 0 +OP4 E00F4F 0 +OP4 E00F50 0 +OP4 E00F51 0 +OP4 E00F52 0 +OP4 E00F53 0 +OP4 E00F54 0 +OP4 E00F55 0 +OP4 E00F56 0 +OP4 E00F57 0 +OP4 E00F58 0 +OP4 E00F59 0 +OP4 E00F5A 0 +OP4 E00F5B 0 +OP4 E00F5C 0 +OP4 E00F5D 0 +OP4 E00F5E 0 +OP4 E00F5F 0 +OP4 E00F60 0 +OP4 E00F61 0 +OP4 E00F62 0 +OP4 E00F63 0 +OP4 E00F64 0 +OP4 E00F65 0 +OP4 E00F66 0 +OP4 E00F67 0 +OP4 E00F68 0 +OP4 E00F69 0 +OP4 E00F6A 0 +OP4 E00F6B 0 +OP4 E00F6C 0 +OP4 E00F6D 0 +OP4 E00F6E 0 +OP4 E00F6F 0 +OP4 E00F70 0 +OP4 E00F71 0 +OP4 E00F72 0 +OP4 E00F73 0 +OP4 E00F74 0 +OP4 E00F75 0 +OP4 E00F76 0 +OP4 E00F77 0 +OP4 E00F78 0 +OP4 E00F79 0 +OP4 E00F7A 0 +OP4 E00F7B 0 +OP4 E00F7C 0 +OP4 E00F7D 0 +OP4 E00F7E 0 +OP4 E00F7F 0 +OP4 E00F80 0 +OP4 E00F81 0 +OP4 E00F82 0 +OP4 E00F83 0 +OP4 E00F84 0 +OP4 E00F85 0 +OP4 E00F86 0 +OP4 E00F87 0 +OP4 E00F88 0 +OP4 E00F89 0 +OP4 E00F8A 0 +OP4 E00F8B 0 +OP4 E00F8C 0 +OP4 E00F8D 0 +OP4 E00F8E 0 +OP4 E00F8F 0 +OP4 E00F90 0 +OP4 E00F91 0 +OP4 E00F92 0 +OP4 E00F93 0 +OP4 E00F94 0 +OP4 E00F95 0 +OP4 E00F96 0 +OP4 E00F97 0 +OP4 E00F98 0 +OP4 E00F99 0 +OP4 E00F9A 0 +OP4 E00F9B 0 +OP4 E00F9C 0 +OP4 E00F9D 0 +OP4 E00F9E 0 +OP4 E00F9F 0 +OP4 E00FA0 0 +OP4 E00FA1 0 +OP4 E00FA2 0 +OP4 E00FA3 0 +OP4 E00FA4 0 +OP4 E00FA5 0 +OP4 E00FA6 0 +OP4 E00FA7 0 +OP4 E00FA8 0 +OP4 E00FA9 0 +OP4 E00FAA 0 +OP4 E00FAB 0 +OP4 E00FAC 0 +OP4 E00FAD 0 +OP4 E00FAE 0 +OP4 E00FAF 0 +OP4 E00FB0 0 +OP4 E00FB1 0 +OP4 E00FB2 0 +OP4 E00FB3 0 +OP4 E00FB4 0 +OP4 E00FB5 0 +OP4 E00FB6 0 +OP4 E00FB7 0 +OP4 E00FB8 0 +OP4 E00FB9 0 +OP4 E00FBA 0 +OP4 E00FBB 0 +OP4 E00FBC 0 +OP4 E00FBD 0 +OP4 E00FBE 0 +OP4 E00FBF 0 +OP4 E00FC0 0 +OP4 E00FC1 0 +OP4 E00FC2 0 +OP4 E00FC3 0 +OP4 E00FC4 0 +OP4 E00FC5 0 +OP4 E00FC6 0 +OP4 E00FC7 0 +OP4 E00FC8 0 +OP4 E00FC9 0 +OP4 E00FCA 0 +OP4 E00FCB 0 +OP4 E00FCC 0 +OP4 E00FCD 0 +OP4 E00FCE 0 +OP4 E00FCF 0 +OP4 E00FD0 0 +OP4 E00FD1 0 +OP4 E00FD2 0 +OP4 E00FD3 0 +OP4 E00FD4 0 +OP4 E00FD5 0 +OP4 E00FD6 0 +OP4 E00FD7 0 +OP4 E00FD8 0 +OP4 E00FD9 0 +OP4 E00FDA 0 +OP4 E00FDB 0 +OP4 E00FDC 0 +OP4 E00FDD 0 +OP4 E00FDE 0 +OP4 E00FDF 0 +OP4 E00FE0 0 +OP4 E00FE1 0 +OP4 E00FE2 0 +OP4 E00FE3 0 +OP4 E00FE4 0 +OP4 E00FE5 0 +OP4 E00FE6 0 +OP4 E00FE7 0 +OP4 E00FE8 0 +OP4 E00FE9 0 +OP4 E00FEA 0 +OP4 E00FEB 0 +OP4 E00FEC 0 +OP4 E00FED 0 +OP4 E00FEE 0 +OP4 E00FEF 0 +OP4 E00FF0 0 +OP4 E00FF1 0 +OP4 E00FF2 0 +OP4 E00FF3 0 +OP4 E00FF4 0 +OP4 E00FF5 0 +OP4 E00FF6 0 +OP4 E00FF7 0 +OP4 E00FF8 0 +OP4 E00FF9 0 +OP4 E00FFA 0 +OP4 E00FFB 0 +OP4 E00FFC 0 +OP4 E00FFD 0 +OP4 E00FFE 0 +OP4 E00FFF 0 +OP4 E01000 0 +OP4 E01001 0 +OP4 E01002 0 +OP4 E01003 0 +OP4 E01004 0 +OP4 E01005 0 +OP4 E01006 0 +OP4 E01007 0 +OP4 E01008 0 +OP4 E01009 0 +OP4 E0100A 0 +OP4 E0100B 0 +OP4 E0100C 0 +OP4 E0100D 0 +OP4 E0100E 0 +OP4 E0100F 0 +OP4 E01010 0 +OP4 E01011 0 +OP4 E01012 0 +OP4 E01013 0 +OP4 E01014 0 +OP4 E01015 0 +OP4 E01016 0 +OP4 E01017 0 +OP4 E01018 0 +OP4 E01019 0 +OP4 E0101A 0 +OP4 E0101B 0 +OP4 E0101C 0 +OP4 E0101D 0 +OP4 E0101E 0 +OP4 E0101F 0 +OP4 E01020 0 +OP4 E01021 0 +OP4 E01022 0 +OP4 E01023 0 +OP4 E01024 0 +OP4 E01025 0 +OP4 E01026 0 +OP4 E01027 0 +OP4 E01028 0 +OP4 E01029 0 +OP4 E0102A 0 +OP4 E0102B 0 +OP4 E0102C 0 +OP4 E0102D 0 +OP4 E0102E 0 +OP4 E0102F 0 +OP4 E01030 0 +OP4 E01031 0 +OP4 E01032 0 +OP4 E01033 0 +OP4 E01034 0 +OP4 E01035 0 +OP4 E01036 0 +OP4 E01037 0 +OP4 E01038 0 +OP4 E01039 0 +OP4 E0103A 0 +OP4 E0103B 0 +OP4 E0103C 0 +OP4 E0103D 0 +OP4 E0103E 0 +OP4 E0103F 0 +OP4 E01040 0 +OP4 E01041 0 +OP4 E01042 0 +OP4 E01043 0 +OP4 E01044 0 +OP4 E01045 0 +OP4 E01046 0 +OP4 E01047 0 +OP4 E01048 0 +OP4 E01049 0 +OP4 E0104A 0 +OP4 E0104B 0 +OP4 E0104C 0 +OP4 E0104D 0 +OP4 E0104E 0 +OP4 E0104F 0 +OP4 E01050 0 +OP4 E01051 0 +OP4 E01052 0 +OP4 E01053 0 +OP4 E01054 0 +OP4 E01055 0 +OP4 E01056 0 +OP4 E01057 0 +OP4 E01058 0 +OP4 E01059 0 +OP4 E0105A 0 +OP4 E0105B 0 +OP4 E0105C 0 +OP4 E0105D 0 +OP4 E0105E 0 +OP4 E0105F 0 +OP4 E01060 0 +OP4 E01061 0 +OP4 E01062 0 +OP4 E01063 0 +OP4 E01064 0 +OP4 E01065 0 +OP4 E01066 0 +OP4 E01067 0 +OP4 E01068 0 +OP4 E01069 0 +OP4 E0106A 0 +OP4 E0106B 0 +OP4 E0106C 0 +OP4 E0106D 0 +OP4 E0106E 0 +OP4 E0106F 0 +OP4 E01070 0 +OP4 E01071 0 +OP4 E01072 0 +OP4 E01073 0 +OP4 E01074 0 +OP4 E01075 0 +OP4 E01076 0 +OP4 E01077 0 +OP4 E01078 0 +OP4 E01079 0 +OP4 E0107A 0 +OP4 E0107B 0 +OP4 E0107C 0 +OP4 E0107D 0 +OP4 E0107E 0 +OP4 E0107F 0 +OP4 E01080 0 +OP4 E01081 0 +OP4 E01082 0 +OP4 E01083 0 +OP4 E01084 0 +OP4 E01085 0 +OP4 E01086 0 +OP4 E01087 0 +OP4 E01088 0 +OP4 E01089 0 +OP4 E0108A 0 +OP4 E0108B 0 +OP4 E0108C 0 +OP4 E0108D 0 +OP4 E0108E 0 +OP4 E0108F 0 +OP4 E01090 0 +OP4 E01091 0 +OP4 E01092 0 +OP4 E01093 0 +OP4 E01094 0 +OP4 E01095 0 +OP4 E01096 0 +OP4 E01097 0 +OP4 E01098 0 +OP4 E01099 0 +OP4 E0109A 0 +OP4 E0109B 0 +OP4 E0109C 0 +OP4 E0109D 0 +OP4 E0109E 0 +OP4 E0109F 0 +OP4 E010A0 0 +OP4 E010A1 0 +OP4 E010A2 0 +OP4 E010A3 0 +OP4 E010A4 0 +OP4 E010A5 0 +OP4 E010A6 0 +OP4 E010A7 0 +OP4 E010A8 0 +OP4 E010A9 0 +OP4 E010AA 0 +OP4 E010AB 0 +OP4 E010AC 0 +OP4 E010AD 0 +OP4 E010AE 0 +OP4 E010AF 0 +OP4 E010B0 0 +OP4 E010B1 0 +OP4 E010B2 0 +OP4 E010B3 0 +OP4 E010B4 0 +OP4 E010B5 0 +OP4 E010B6 0 +OP4 E010B7 0 +OP4 E010B8 0 +OP4 E010B9 0 +OP4 E010BA 0 +OP4 E010BB 0 +OP4 E010BC 0 +OP4 E010BD 0 +OP4 E010BE 0 +OP4 E010BF 0 +OP4 E010C0 0 +OP4 E010C1 0 +OP4 E010C2 0 +OP4 E010C3 0 +OP4 E010C4 0 +OP4 E010C5 0 +OP4 E010C6 0 +OP4 E010C7 0 +OP4 E010C8 0 +OP4 E010C9 0 +OP4 E010CA 0 +OP4 E010CB 0 +OP4 E010CC 0 +OP4 E010CD 0 +OP4 E010CE 0 +OP4 E010CF 0 +OP4 E010D0 0 +OP4 E010D1 0 +OP4 E010D2 0 +OP4 E010D3 0 +OP4 E010D4 0 +OP4 E010D5 0 +OP4 E010D6 0 +OP4 E010D7 0 +OP4 E010D8 0 +OP4 E010D9 0 +OP4 E010DA 0 +OP4 E010DB 0 +OP4 E010DC 0 +OP4 E010DD 0 +OP4 E010DE 0 +OP4 E010DF 0 +OP4 E010E0 0 +OP4 E010E1 0 +OP4 E010E2 0 +OP4 E010E3 0 +OP4 E010E4 0 +OP4 E010E5 0 +OP4 E010E6 0 +OP4 E010E7 0 +OP4 E010E8 0 +OP4 E010E9 0 +OP4 E010EA 0 +OP4 E010EB 0 +OP4 E010EC 0 +OP4 E010ED 0 +OP4 E010EE 0 +OP4 E010EF 0 +OP4 E010F0 0 +OP4 E010F1 0 +OP4 E010F2 0 +OP4 E010F3 0 +OP4 E010F4 0 +OP4 E010F5 0 +OP4 E010F6 0 +OP4 E010F7 0 +OP4 E010F8 0 +OP4 E010F9 0 +OP4 E010FA 0 +OP4 E010FB 0 +OP4 E010FC 0 +OP4 E010FD 0 +OP4 E010FE 0 +OP4 E010FF 0 +OP4 E01100 0 +OP4 E01101 0 +OP4 E01102 0 +OP4 E01103 0 +OP4 E01104 0 +OP4 E01105 0 +OP4 E01106 0 +OP4 E01107 0 +OP4 E01108 0 +OP4 E01109 0 +OP4 E0110A 0 +OP4 E0110B 0 +OP4 E0110C 0 +OP4 E0110D 0 +OP4 E0110E 0 +OP4 E0110F 0 +OP4 E01110 0 +OP4 E01111 0 +OP4 E01112 0 +OP4 E01113 0 +OP4 E01114 0 +OP4 E01115 0 +OP4 E01116 0 +OP4 E01117 0 +OP4 E01118 0 +OP4 E01119 0 +OP4 E0111A 0 +OP4 E0111B 0 +OP4 E0111C 0 +OP4 E0111D 0 +OP4 E0111E 0 +OP4 E0111F 0 +OP4 E01120 0 +OP4 E01121 0 +OP4 E01122 0 +OP4 E01123 0 +OP4 E01124 0 +OP4 E01125 0 +OP4 E01126 0 +OP4 E01127 0 +OP4 E01128 0 +OP4 E01129 0 +OP4 E0112A 0 +OP4 E0112B 0 +OP4 E0112C 0 +OP4 E0112D 0 +OP4 E0112E 0 +OP4 E0112F 0 +OP4 E01130 0 +OP4 E01131 0 +OP4 E01132 0 +OP4 E01133 0 +OP4 E01134 0 +OP4 E01135 0 +OP4 E01136 0 +OP4 E01137 0 +OP4 E01138 0 +OP4 E01139 0 +OP4 E0113A 0 +OP4 E0113B 0 +OP4 E0113C 0 +OP4 E0113D 0 +OP4 E0113E 0 +OP4 E0113F 0 +OP4 E01140 0 +OP4 E01141 0 +OP4 E01142 0 +OP4 E01143 0 +OP4 E01144 0 +OP4 E01145 0 +OP4 E01146 0 +OP4 E01147 0 +OP4 E01148 0 +OP4 E01149 0 +OP4 E0114A 0 +OP4 E0114B 0 +OP4 E0114C 0 +OP4 E0114D 0 +OP4 E0114E 0 +OP4 E0114F 0 +OP4 E01150 0 +OP4 E01151 0 +OP4 E01152 0 +OP4 E01153 0 +OP4 E01154 0 +OP4 E01155 0 +OP4 E01156 0 +OP4 E01157 0 +OP4 E01158 0 +OP4 E01159 0 +OP4 E0115A 0 +OP4 E0115B 0 +OP4 E0115C 0 +OP4 E0115D 0 +OP4 E0115E 0 +OP4 E0115F 0 +OP4 E01160 0 +OP4 E01161 0 +OP4 E01162 0 +OP4 E01163 0 +OP4 E01164 0 +OP4 E01165 0 +OP4 E01166 0 +OP4 E01167 0 +OP4 E01168 0 +OP4 E01169 0 +OP4 E0116A 0 +OP4 E0116B 0 +OP4 E0116C 0 +OP4 E0116D 0 +OP4 E0116E 0 +OP4 E0116F 0 +OP4 E01170 0 +OP4 E01171 0 +OP4 E01172 0 +OP4 E01173 0 +OP4 E01174 0 +OP4 E01175 0 +OP4 E01176 0 +OP4 E01177 0 +OP4 E01178 0 +OP4 E01179 0 +OP4 E0117A 0 +OP4 E0117B 0 +OP4 E0117C 0 +OP4 E0117D 0 +OP4 E0117E 0 +OP4 E0117F 0 +OP4 E01180 0 +OP4 E01181 0 +OP4 E01182 0 +OP4 E01183 0 +OP4 E01184 0 +OP4 E01185 0 +OP4 E01186 0 +OP4 E01187 0 +OP4 E01188 0 +OP4 E01189 0 +OP4 E0118A 0 +OP4 E0118B 0 +OP4 E0118C 0 +OP4 E0118D 0 +OP4 E0118E 0 +OP4 E0118F 0 +OP4 E01190 0 +OP4 E01191 0 +OP4 E01192 0 +OP4 E01193 0 +OP4 E01194 0 +OP4 E01195 0 +OP4 E01196 0 +OP4 E01197 0 +OP4 E01198 0 +OP4 E01199 0 +OP4 E0119A 0 +OP4 E0119B 0 +OP4 E0119C 0 +OP4 E0119D 0 +OP4 E0119E 0 +OP4 E0119F 0 +OP4 E011A0 0 +OP4 E011A1 0 +OP4 E011A2 0 +OP4 E011A3 0 +OP4 E011A4 0 +OP4 E011A5 0 +OP4 E011A6 0 +OP4 E011A7 0 +OP4 E011A8 0 +OP4 E011A9 0 +OP4 E011AA 0 +OP4 E011AB 0 +OP4 E011AC 0 +OP4 E011AD 0 +OP4 E011AE 0 +OP4 E011AF 0 +OP4 E011B0 0 +OP4 E011B1 0 +OP4 E011B2 0 +OP4 E011B3 0 +OP4 E011B4 0 +OP4 E011B5 0 +OP4 E011B6 0 +OP4 E011B7 0 +OP4 E011B8 0 +OP4 E011B9 0 +OP4 E011BA 0 +OP4 E011BB 0 +OP4 E011BC 0 +OP4 E011BD 0 +OP4 E011BE 0 +OP4 E011BF 0 +OP4 E011C0 0 +OP4 E011C1 0 +OP4 E011C2 0 +OP4 E011C3 0 +OP4 E011C4 0 +OP4 E011C5 0 +OP4 E011C6 0 +OP4 E011C7 0 +OP4 E011C8 0 +OP4 E011C9 0 +OP4 E011CA 0 +OP4 E011CB 0 +OP4 E011CC 0 +OP4 E011CD 0 +OP4 E011CE 0 +OP4 E011CF 0 +OP4 E011D0 0 +OP4 E011D1 0 +OP4 E011D2 0 +OP4 E011D3 0 +OP4 E011D4 0 +OP4 E011D5 0 +OP4 E011D6 0 +OP4 E011D7 0 +OP4 E011D8 0 +OP4 E011D9 0 +OP4 E011DA 0 +OP4 E011DB 0 +OP4 E011DC 0 +OP4 E011DD 0 +OP4 E011DE 0 +OP4 E011DF 0 +OP4 E011E0 0 +OP4 E011E1 0 +OP4 E011E2 0 +OP4 E011E3 0 +OP4 E011E4 0 +OP4 E011E5 0 +OP4 E011E6 0 +OP4 E011E7 0 +OP4 E011E8 0 +OP4 E011E9 0 +OP4 E011EA 0 +OP4 E011EB 0 +OP4 E011EC 0 +OP4 E011ED 0 +OP4 E011EE 0 +OP4 E011EF 0 +OP4 E011F0 0 +OP4 E011F1 0 +OP4 E011F2 0 +OP4 E011F3 0 +OP4 E011F4 0 +OP4 E011F5 0 +OP4 E011F6 0 +OP4 E011F7 0 +OP4 E011F8 0 +OP4 E011F9 0 +OP4 E011FA 0 +OP4 E011FB 0 +OP4 E011FC 0 +OP4 E011FD 0 +OP4 E011FE 0 +OP4 E011FF 0 +OP4 E01200 0 +OP4 E01201 0 +OP4 E01202 0 +OP4 E01203 0 +OP4 E01204 0 +OP4 E01205 0 +OP4 E01206 0 +OP4 E01207 0 +OP4 E01208 0 +OP4 E01209 0 +OP4 E0120A 0 +OP4 E0120B 0 +OP4 E0120C 0 +OP4 E0120D 0 +OP4 E0120E 0 +OP4 E0120F 0 +OP4 E01210 0 +OP4 E01211 0 +OP4 E01212 0 +OP4 E01213 0 +OP4 E01214 0 +OP4 E01215 0 +OP4 E01216 0 +OP4 E01217 0 +OP4 E01218 0 +OP4 E01219 0 +OP4 E0121A 0 +OP4 E0121B 0 +OP4 E0121C 0 +OP4 E0121D 0 +OP4 E0121E 0 +OP4 E0121F 0 +OP4 E01220 0 +OP4 E01221 0 +OP4 E01222 0 +OP4 E01223 0 +OP4 E01224 0 +OP4 E01225 0 +OP4 E01226 0 +OP4 E01227 0 +OP4 E01228 0 +OP4 E01229 0 +OP4 E0122A 0 +OP4 E0122B 0 +OP4 E0122C 0 +OP4 E0122D 0 +OP4 E0122E 0 +OP4 E0122F 0 +OP4 E01230 0 +OP4 E01231 0 +OP4 E01232 0 +OP4 E01233 0 +OP4 E01234 0 +OP4 E01235 0 +OP4 E01236 0 +OP4 E01237 0 +OP4 E01238 0 +OP4 E01239 0 +OP4 E0123A 0 +OP4 E0123B 0 +OP4 E0123C 0 +OP4 E0123D 0 +OP4 E0123E 0 +OP4 E0123F 0 +OP4 E01240 0 +OP4 E01241 0 +OP4 E01242 0 +OP4 E01243 0 +OP4 E01244 0 +OP4 E01245 0 +OP4 E01246 0 +OP4 E01247 0 +OP4 E01248 0 +OP4 E01249 0 +OP4 E0124A 0 +OP4 E0124B 0 +OP4 E0124C 0 +OP4 E0124D 0 +OP4 E0124E 0 +OP4 E0124F 0 +OP4 E01250 0 +OP4 E01251 0 +OP4 E01252 0 +OP4 E01253 0 +OP4 E01254 0 +OP4 E01255 0 +OP4 E01256 0 +OP4 E01257 0 +OP4 E01258 0 +OP4 E01259 0 +OP4 E0125A 0 +OP4 E0125B 0 +OP4 E0125C 0 +OP4 E0125D 0 +OP4 E0125E 0 +OP4 E0125F 0 +OP4 E01260 0 +OP4 E01261 0 +OP4 E01262 0 +OP4 E01263 0 +OP4 E01264 0 +OP4 E01265 0 +OP4 E01266 0 +OP4 E01267 0 +OP4 E01268 0 +OP4 E01269 0 +OP4 E0126A 0 +OP4 E0126B 0 +OP4 E0126C 0 +OP4 E0126D 0 +OP4 E0126E 0 +OP4 E0126F 0 +OP4 E01270 0 +OP4 E01271 0 +OP4 E01272 0 +OP4 E01273 0 +OP4 E01274 0 +OP4 E01275 0 +OP4 E01276 0 +OP4 E01277 0 +OP4 E01278 0 +OP4 E01279 0 +OP4 E0127A 0 +OP4 E0127B 0 +OP4 E0127C 0 +OP4 E0127D 0 +OP4 E0127E 0 +OP4 E0127F 0 +OP4 E01280 0 +OP4 E01281 0 +OP4 E01282 0 +OP4 E01283 0 +OP4 E01284 0 +OP4 E01285 0 +OP4 E01286 0 +OP4 E01287 0 +OP4 E01288 0 +OP4 E01289 0 +OP4 E0128A 0 +OP4 E0128B 0 +OP4 E0128C 0 +OP4 E0128D 0 +OP4 E0128E 0 +OP4 E0128F 0 +OP4 E01290 0 +OP4 E01291 0 +OP4 E01292 0 +OP4 E01293 0 +OP4 E01294 0 +OP4 E01295 0 +OP4 E01296 0 +OP4 E01297 0 +OP4 E01298 0 +OP4 E01299 0 +OP4 E0129A 0 +OP4 E0129B 0 +OP4 E0129C 0 +OP4 E0129D 0 +OP4 E0129E 0 +OP4 E0129F 0 +OP4 E012A0 0 +OP4 E012A1 0 +OP4 E012A2 0 +OP4 E012A3 0 +OP4 E012A4 0 +OP4 E012A5 0 +OP4 E012A6 0 +OP4 E012A7 0 +OP4 E012A8 0 +OP4 E012A9 0 +OP4 E012AA 0 +OP4 E012AB 0 +OP4 E012AC 0 +OP4 E012AD 0 +OP4 E012AE 0 +OP4 E012AF 0 +OP4 E012B0 0 +OP4 E012B1 0 +OP4 E012B2 0 +OP4 E012B3 0 +OP4 E012B4 0 +OP4 E012B5 0 +OP4 E012B6 0 +OP4 E012B7 0 +OP4 E012B8 0 +OP4 E012B9 0 +OP4 E012BA 0 +OP4 E012BB 0 +OP4 E012BC 0 +OP4 E012BD 0 +OP4 E012BE 0 +OP4 E012BF 0 +OP4 E012C0 0 +OP4 E012C1 0 +OP4 E012C2 0 +OP4 E012C3 0 +OP4 E012C4 0 +OP4 E012C5 0 +OP4 E012C6 0 +OP4 E012C7 0 +OP4 E012C8 0 +OP4 E012C9 0 +OP4 E012CA 0 +OP4 E012CB 0 +OP4 E012CC 0 +OP4 E012CD 0 +OP4 E012CE 0 +OP4 E012CF 0 +OP4 E012D0 0 +OP4 E012D1 0 +OP4 E012D2 0 +OP4 E012D3 0 +OP4 E012D4 0 +OP4 E012D5 0 +OP4 E012D6 0 +OP4 E012D7 0 +OP4 E012D8 0 +OP4 E012D9 0 +OP4 E012DA 0 +OP4 E012DB 0 +OP4 E012DC 0 +OP4 E012DD 0 +OP4 E012DE 0 +OP4 E012DF 0 +OP4 E012E0 0 +OP4 E012E1 0 +OP4 E012E2 0 +OP4 E012E3 0 +OP4 E012E4 0 +OP4 E012E5 0 +OP4 E012E6 0 +OP4 E012E7 0 +OP4 E012E8 0 +OP4 E012E9 0 +OP4 E012EA 0 +OP4 E012EB 0 +OP4 E012EC 0 +OP4 E012ED 0 +OP4 E012EE 0 +OP4 E012EF 0 +OP4 E012F0 0 +OP4 E012F1 0 +OP4 E012F2 0 +OP4 E012F3 0 +OP4 E012F4 0 +OP4 E012F5 0 +OP4 E012F6 0 +OP4 E012F7 0 +OP4 E012F8 0 +OP4 E012F9 0 +OP4 E012FA 0 +OP4 E012FB 0 +OP4 E012FC 0 +OP4 E012FD 0 +OP4 E012FE 0 +OP4 E012FF 0 +OP4 E01300 0 +OP4 E01301 0 +OP4 E01302 0 +OP4 E01303 0 +OP4 E01304 0 +OP4 E01305 0 +OP4 E01306 0 +OP4 E01307 0 +OP4 E01308 0 +OP4 E01309 0 +OP4 E0130A 0 +OP4 E0130B 0 +OP4 E0130C 0 +OP4 E0130D 0 +OP4 E0130E 0 +OP4 E0130F 0 +OP4 E01310 0 +OP4 E01311 0 +OP4 E01312 0 +OP4 E01313 0 +OP4 E01314 0 +OP4 E01315 0 +OP4 E01316 0 +OP4 E01317 0 +OP4 E01318 0 +OP4 E01319 0 +OP4 E0131A 0 +OP4 E0131B 0 +OP4 E0131C 0 +OP4 E0131D 0 +OP4 E0131E 0 +OP4 E0131F 0 +OP4 E01320 0 +OP4 E01321 0 +OP4 E01322 0 +OP4 E01323 0 +OP4 E01324 0 +OP4 E01325 0 +OP4 E01326 0 +OP4 E01327 0 +OP4 E01328 0 +OP4 E01329 0 +OP4 E0132A 0 +OP4 E0132B 0 +OP4 E0132C 0 +OP4 E0132D 0 +OP4 E0132E 0 +OP4 E0132F 0 +OP4 E01330 0 +OP4 E01331 0 +OP4 E01332 0 +OP4 E01333 0 +OP4 E01334 0 +OP4 E01335 0 +OP4 E01336 0 +OP4 E01337 0 +OP4 E01338 0 +OP4 E01339 0 +OP4 E0133A 0 +OP4 E0133B 0 +OP4 E0133C 0 +OP4 E0133D 0 +OP4 E0133E 0 +OP4 E0133F 0 +OP4 E01340 0 +OP4 E01341 0 +OP4 E01342 0 +OP4 E01343 0 +OP4 E01344 0 +OP4 E01345 0 +OP4 E01346 0 +OP4 E01347 0 +OP4 E01348 0 +OP4 E01349 0 +OP4 E0134A 0 +OP4 E0134B 0 +OP4 E0134C 0 +OP4 E0134D 0 +OP4 E0134E 0 +OP4 E0134F 0 +OP4 E01350 0 +OP4 E01351 0 +OP4 E01352 0 +OP4 E01353 0 +OP4 E01354 0 +OP4 E01355 0 +OP4 E01356 0 +OP4 E01357 0 +OP4 E01358 0 +OP4 E01359 0 +OP4 E0135A 0 +OP4 E0135B 0 +OP4 E0135C 0 +OP4 E0135D 0 +OP4 E0135E 0 +OP4 E0135F 0 +OP4 E01360 0 +OP4 E01361 0 +OP4 E01362 0 +OP4 E01363 0 +OP4 E01364 0 +OP4 E01365 0 +OP4 E01366 0 +OP4 E01367 0 +OP4 E01368 0 +OP4 E01369 0 +OP4 E0136A 0 +OP4 E0136B 0 +OP4 E0136C 0 +OP4 E0136D 0 +OP4 E0136E 0 +OP4 E0136F 0 +OP4 E01370 0 +OP4 E01371 0 +OP4 E01372 0 +OP4 E01373 0 +OP4 E01374 0 +OP4 E01375 0 +OP4 E01376 0 +OP4 E01377 0 +OP4 E01378 0 +OP4 E01379 0 +OP4 E0137A 0 +OP4 E0137B 0 +OP4 E0137C 0 +OP4 E0137D 0 +OP4 E0137E 0 +OP4 E0137F 0 +OP4 E01380 0 +OP4 E01381 0 +OP4 E01382 0 +OP4 E01383 0 +OP4 E01384 0 +OP4 E01385 0 +OP4 E01386 0 +OP4 E01387 0 +OP4 E01388 0 +OP4 E01389 0 +OP4 E0138A 0 +OP4 E0138B 0 +OP4 E0138C 0 +OP4 E0138D 0 +OP4 E0138E 0 +OP4 E0138F 0 +OP4 E01390 0 +OP4 E01391 0 +OP4 E01392 0 +OP4 E01393 0 +OP4 E01394 0 +OP4 E01395 0 +OP4 E01396 0 +OP4 E01397 0 +OP4 E01398 0 +OP4 E01399 0 +OP4 E0139A 0 +OP4 E0139B 0 +OP4 E0139C 0 +OP4 E0139D 0 +OP4 E0139E 0 +OP4 E0139F 0 +OP4 E013A0 0 +OP4 E013A1 0 +OP4 E013A2 0 +OP4 E013A3 0 +OP4 E013A4 0 +OP4 E013A5 0 +OP4 E013A6 0 +OP4 E013A7 0 +OP4 E013A8 0 +OP4 E013A9 0 +OP4 E013AA 0 +OP4 E013AB 0 +OP4 E013AC 0 +OP4 E013AD 0 +OP4 E013AE 0 +OP4 E013AF 0 +OP4 E013B0 0 +OP4 E013B1 0 +OP4 E013B2 0 +OP4 E013B3 0 +OP4 E013B4 0 +OP4 E013B5 0 +OP4 E013B6 0 +OP4 E013B7 0 +OP4 E013B8 0 +OP4 E013B9 0 +OP4 E013BA 0 +OP4 E013BB 0 +OP4 E013BC 0 +OP4 E013BD 0 +OP4 E013BE 0 +OP4 E013BF 0 +OP4 E013C0 0 +OP4 E013C1 0 +OP4 E013C2 0 +OP4 E013C3 0 +OP4 E013C4 0 +OP4 E013C5 0 +OP4 E013C6 0 +OP4 E013C7 0 +OP4 E013C8 0 +OP4 E013C9 0 +OP4 E013CA 0 +OP4 E013CB 0 +OP4 E013CC 0 +OP4 E013CD 0 +OP4 E013CE 0 +OP4 E013CF 0 +OP4 E013D0 0 +OP4 E013D1 0 +OP4 E013D2 0 +OP4 E013D3 0 +OP4 E013D4 0 +OP4 E013D5 0 +OP4 E013D6 0 +OP4 E013D7 0 +OP4 E013D8 0 +OP4 E013D9 0 +OP4 E013DA 0 +OP4 E013DB 0 +OP4 E013DC 0 +OP4 E013DD 0 +OP4 E013DE 0 +OP4 E013DF 0 +OP4 E013E0 0 +OP4 E013E1 0 +OP4 E013E2 0 +OP4 E013E3 0 +OP4 E013E4 0 +OP4 E013E5 0 +OP4 E013E6 0 +OP4 E013E7 0 +OP4 E013E8 0 +OP4 E013E9 0 +OP4 E013EA 0 +OP4 E013EB 0 +OP4 E013EC 0 +OP4 E013ED 0 +OP4 E013EE 0 +OP4 E013EF 0 +OP4 E013F0 0 +OP4 E013F1 0 +OP4 E013F2 0 +OP4 E013F3 0 +OP4 E013F4 0 +OP4 E013F5 0 +OP4 E013F6 0 +OP4 E013F7 0 +OP4 E013F8 0 +OP4 E013F9 0 +OP4 E013FA 0 +OP4 E013FB 0 +OP4 E013FC 0 +OP4 E013FD 0 +OP4 E013FE 0 +OP4 E013FF 0 +OP4 E01400 0 +OP4 E01401 0 +OP4 E01402 0 +OP4 E01403 0 +OP4 E01404 0 +OP4 E01405 0 +OP4 E01406 0 +OP4 E01407 0 +OP4 E01408 0 +OP4 E01409 0 +OP4 E0140A 0 +OP4 E0140B 0 +OP4 E0140C 0 +OP4 E0140D 0 +OP4 E0140E 0 +OP4 E0140F 0 +OP4 E01410 0 +OP4 E01411 0 +OP4 E01412 0 +OP4 E01413 0 +OP4 E01414 0 +OP4 E01415 0 +OP4 E01416 0 +OP4 E01417 0 +OP4 E01418 0 +OP4 E01419 0 +OP4 E0141A 0 +OP4 E0141B 0 +OP4 E0141C 0 +OP4 E0141D 0 +OP4 E0141E 0 +OP4 E0141F 0 +OP4 E01420 0 +OP4 E01421 0 +OP4 E01422 0 +OP4 E01423 0 +OP4 E01424 0 +OP4 E01425 0 +OP4 E01426 0 +OP4 E01427 0 +OP4 E01428 0 +OP4 E01429 0 +OP4 E0142A 0 +OP4 E0142B 0 +OP4 E0142C 0 +OP4 E0142D 0 +OP4 E0142E 0 +OP4 E0142F 0 +OP4 E01430 0 +OP4 E01431 0 +OP4 E01432 0 +OP4 E01433 0 +OP4 E01434 0 +OP4 E01435 0 +OP4 E01436 0 +OP4 E01437 0 +OP4 E01438 0 +OP4 E01439 0 +OP4 E0143A 0 +OP4 E0143B 0 +OP4 E0143C 0 +OP4 E0143D 0 +OP4 E0143E 0 +OP4 E0143F 0 +OP4 E01440 0 +OP4 E01441 0 +OP4 E01442 0 +OP4 E01443 0 +OP4 E01444 0 +OP4 E01445 0 +OP4 E01446 0 +OP4 E01447 0 +OP4 E01448 0 +OP4 E01449 0 +OP4 E0144A 0 +OP4 E0144B 0 +OP4 E0144C 0 +OP4 E0144D 0 +OP4 E0144E 0 +OP4 E0144F 0 +OP4 E01450 0 +OP4 E01451 0 +OP4 E01452 0 +OP4 E01453 0 +OP4 E01454 0 +OP4 E01455 0 +OP4 E01456 0 +OP4 E01457 0 +OP4 E01458 0 +OP4 E01459 0 +OP4 E0145A 0 +OP4 E0145B 0 +OP4 E0145C 0 +OP4 E0145D 0 +OP4 E0145E 0 +OP4 E0145F 0 +OP4 E01460 0 +OP4 E01461 0 +OP4 E01462 0 +OP4 E01463 0 +OP4 E01464 0 +OP4 E01465 0 +OP4 E01466 0 +OP4 E01467 0 +OP4 E01468 0 +OP4 E01469 0 +OP4 E0146A 0 +OP4 E0146B 0 +OP4 E0146C 0 +OP4 E0146D 0 +OP4 E0146E 0 +OP4 E0146F 0 +OP4 E01470 0 +OP4 E01471 0 +OP4 E01472 0 +OP4 E01473 0 +OP4 E01474 0 +OP4 E01475 0 +OP4 E01476 0 +OP4 E01477 0 +OP4 E01478 0 +OP4 E01479 0 +OP4 E0147A 0 +OP4 E0147B 0 +OP4 E0147C 0 +OP4 E0147D 0 +OP4 E0147E 0 +OP4 E0147F 0 +OP4 E01480 0 +OP4 E01481 0 +OP4 E01482 0 +OP4 E01483 0 +OP4 E01484 0 +OP4 E01485 0 +OP4 E01486 0 +OP4 E01487 0 +OP4 E01488 0 +OP4 E01489 0 +OP4 E0148A 0 +OP4 E0148B 0 +OP4 E0148C 0 +OP4 E0148D 0 +OP4 E0148E 0 +OP4 E0148F 0 +OP4 E01490 0 +OP4 E01491 0 +OP4 E01492 0 +OP4 E01493 0 +OP4 E01494 0 +OP4 E01495 0 +OP4 E01496 0 +OP4 E01497 0 +OP4 E01498 0 +OP4 E01499 0 +OP4 E0149A 0 +OP4 E0149B 0 +OP4 E0149C 0 +OP4 E0149D 0 +OP4 E0149E 0 +OP4 E0149F 0 +OP4 E014A0 0 +OP4 E014A1 0 +OP4 E014A2 0 +OP4 E014A3 0 +OP4 E014A4 0 +OP4 E014A5 0 +OP4 E014A6 0 +OP4 E014A7 0 +OP4 E014A8 0 +OP4 E014A9 0 +OP4 E014AA 0 +OP4 E014AB 0 +OP4 E014AC 0 +OP4 E014AD 0 +OP4 E014AE 0 +OP4 E014AF 0 +OP4 E014B0 0 +OP4 E014B1 0 +OP4 E014B2 0 +OP4 E014B3 0 +OP4 E014B4 0 +OP4 E014B5 0 +OP4 E014B6 0 +OP4 E014B7 0 +OP4 E014B8 0 +OP4 E014B9 0 +OP4 E014BA 0 +OP4 E014BB 0 +OP4 E014BC 0 +OP4 E014BD 0 +OP4 E014BE 0 +OP4 E014BF 0 +OP4 E014C0 0 +OP4 E014C1 0 +OP4 E014C2 0 +OP4 E014C3 0 +OP4 E014C4 0 +OP4 E014C5 0 +OP4 E014C6 0 +OP4 E014C7 0 +OP4 E014C8 0 +OP4 E014C9 0 +OP4 E014CA 0 +OP4 E014CB 0 +OP4 E014CC 0 +OP4 E014CD 0 +OP4 E014CE 0 +OP4 E014CF 0 +OP4 E014D0 0 +OP4 E014D1 0 +OP4 E014D2 0 +OP4 E014D3 0 +OP4 E014D4 0 +OP4 E014D5 0 +OP4 E014D6 0 +OP4 E014D7 0 +OP4 E014D8 0 +OP4 E014D9 0 +OP4 E014DA 0 +OP4 E014DB 0 +OP4 E014DC 0 +OP4 E014DD 0 +OP4 E014DE 0 +OP4 E014DF 0 +OP4 E014E0 0 +OP4 E014E1 0 +OP4 E014E2 0 +OP4 E014E3 0 +OP4 E014E4 0 +OP4 E014E5 0 +OP4 E014E6 0 +OP4 E014E7 0 +OP4 E014E8 0 +OP4 E014E9 0 +OP4 E014EA 0 +OP4 E014EB 0 +OP4 E014EC 0 +OP4 E014ED 0 +OP4 E014EE 0 +OP4 E014EF 0 +OP4 E014F0 0 +OP4 E014F1 0 +OP4 E014F2 0 +OP4 E014F3 0 +OP4 E014F4 0 +OP4 E014F5 0 +OP4 E014F6 0 +OP4 E014F7 0 +OP4 E014F8 0 +OP4 E014F9 0 +OP4 E014FA 0 +OP4 E014FB 0 +OP4 E014FC 0 +OP4 E014FD 0 +OP4 E014FE 0 +OP4 E014FF 0 +OP4 E01500 0 +OP4 E01501 0 +OP4 E01502 0 +OP4 E01503 0 +OP4 E01504 0 +OP4 E01505 0 +OP4 E01506 0 +OP4 E01507 0 +OP4 E01508 0 +OP4 E01509 0 +OP4 E0150A 0 +OP4 E0150B 0 +OP4 E0150C 0 +OP4 E0150D 0 +OP4 E0150E 0 +OP4 E0150F 0 +OP4 E01510 0 +OP4 E01511 0 +OP4 E01512 0 +OP4 E01513 0 +OP4 E01514 0 +OP4 E01515 0 +OP4 E01516 0 +OP4 E01517 0 +OP4 E01518 0 +OP4 E01519 0 +OP4 E0151A 0 +OP4 E0151B 0 +OP4 E0151C 0 +OP4 E0151D 0 +OP4 E0151E 0 +OP4 E0151F 0 +OP4 E01520 0 +OP4 E01521 0 +OP4 E01522 0 +OP4 E01523 0 +OP4 E01524 0 +OP4 E01525 0 +OP4 E01526 0 +OP4 E01527 0 +OP4 E01528 0 +OP4 E01529 0 +OP4 E0152A 0 +OP4 E0152B 0 +OP4 E0152C 0 +OP4 E0152D 0 +OP4 E0152E 0 +OP4 E0152F 0 +OP4 E01530 0 +OP4 E01531 0 +OP4 E01532 0 +OP4 E01533 0 +OP4 E01534 0 +OP4 E01535 0 +OP4 E01536 0 +OP4 E01537 0 +OP4 E01538 0 +OP4 E01539 0 +OP4 E0153A 0 +OP4 E0153B 0 +OP4 E0153C 0 +OP4 E0153D 0 +OP4 E0153E 0 +OP4 E0153F 0 +OP4 E01540 0 +OP4 E01541 0 +OP4 E01542 0 +OP4 E01543 0 +OP4 E01544 0 +OP4 E01545 0 +OP4 E01546 0 +OP4 E01547 0 +OP4 E01548 0 +OP4 E01549 0 +OP4 E0154A 0 +OP4 E0154B 0 +OP4 E0154C 0 +OP4 E0154D 0 +OP4 E0154E 0 +OP4 E0154F 0 +OP4 E01550 0 +OP4 E01551 0 +OP4 E01552 0 +OP4 E01553 0 +OP4 E01554 0 +OP4 E01555 0 +OP4 E01556 0 +OP4 E01557 0 +OP4 E01558 0 +OP4 E01559 0 +OP4 E0155A 0 +OP4 E0155B 0 +OP4 E0155C 0 +OP4 E0155D 0 +OP4 E0155E 0 +OP4 E0155F 0 +OP4 E01560 0 +OP4 E01561 0 +OP4 E01562 0 +OP4 E01563 0 +OP4 E01564 0 +OP4 E01565 0 +OP4 E01566 0 +OP4 E01567 0 +OP4 E01568 0 +OP4 E01569 0 +OP4 E0156A 0 +OP4 E0156B 0 +OP4 E0156C 0 +OP4 E0156D 0 +OP4 E0156E 0 +OP4 E0156F 0 +OP4 E01570 0 +OP4 E01571 0 +OP4 E01572 0 +OP4 E01573 0 +OP4 E01574 0 +OP4 E01575 0 +OP4 E01576 0 +OP4 E01577 0 +OP4 E01578 0 +OP4 E01579 0 +OP4 E0157A 0 +OP4 E0157B 0 +OP4 E0157C 0 +OP4 E0157D 0 +OP4 E0157E 0 +OP4 E0157F 0 +OP4 E01580 0 +OP4 E01581 0 +OP4 E01582 0 +OP4 E01583 0 +OP4 E01584 0 +OP4 E01585 0 +OP4 E01586 0 +OP4 E01587 0 +OP4 E01588 0 +OP4 E01589 0 +OP4 E0158A 0 +OP4 E0158B 0 +OP4 E0158C 0 +OP4 E0158D 0 +OP4 E0158E 0 +OP4 E0158F 0 +OP4 E01590 0 +OP4 E01591 0 +OP4 E01592 0 +OP4 E01593 0 +OP4 E01594 0 +OP4 E01595 0 +OP4 E01596 0 +OP4 E01597 0 +OP4 E01598 0 +OP4 E01599 0 +OP4 E0159A 0 +OP4 E0159B 0 +OP4 E0159C 0 +OP4 E0159D 0 +OP4 E0159E 0 +OP4 E0159F 0 +OP4 E015A0 0 +OP4 E015A1 0 +OP4 E015A2 0 +OP4 E015A3 0 +OP4 E015A4 0 +OP4 E015A5 0 +OP4 E015A6 0 +OP4 E015A7 0 +OP4 E015A8 0 +OP4 E015A9 0 +OP4 E015AA 0 +OP4 E015AB 0 +OP4 E015AC 0 +OP4 E015AD 0 +OP4 E015AE 0 +OP4 E015AF 0 +OP4 E015B0 0 +OP4 E015B1 0 +OP4 E015B2 0 +OP4 E015B3 0 +OP4 E015B4 0 +OP4 E015B5 0 +OP4 E015B6 0 +OP4 E015B7 0 +OP4 E015B8 0 +OP4 E015B9 0 +OP4 E015BA 0 +OP4 E015BB 0 +OP4 E015BC 0 +OP4 E015BD 0 +OP4 E015BE 0 +OP4 E015BF 0 +OP4 E015C0 0 +OP4 E015C1 0 +OP4 E015C2 0 +OP4 E015C3 0 +OP4 E015C4 0 +OP4 E015C5 0 +OP4 E015C6 0 +OP4 E015C7 0 +OP4 E015C8 0 +OP4 E015C9 0 +OP4 E015CA 0 +OP4 E015CB 0 +OP4 E015CC 0 +OP4 E015CD 0 +OP4 E015CE 0 +OP4 E015CF 0 +OP4 E015D0 0 +OP4 E015D1 0 +OP4 E015D2 0 +OP4 E015D3 0 +OP4 E015D4 0 +OP4 E015D5 0 +OP4 E015D6 0 +OP4 E015D7 0 +OP4 E015D8 0 +OP4 E015D9 0 +OP4 E015DA 0 +OP4 E015DB 0 +OP4 E015DC 0 +OP4 E015DD 0 +OP4 E015DE 0 +OP4 E015DF 0 +OP4 E015E0 0 +OP4 E015E1 0 +OP4 E015E2 0 +OP4 E015E3 0 +OP4 E015E4 0 +OP4 E015E5 0 +OP4 E015E6 0 +OP4 E015E7 0 +OP4 E015E8 0 +OP4 E015E9 0 +OP4 E015EA 0 +OP4 E015EB 0 +OP4 E015EC 0 +OP4 E015ED 0 +OP4 E015EE 0 +OP4 E015EF 0 +OP4 E015F0 0 +OP4 E015F1 0 +OP4 E015F2 0 +OP4 E015F3 0 +OP4 E015F4 0 +OP4 E015F5 0 +OP4 E015F6 0 +OP4 E015F7 0 +OP4 E015F8 0 +OP4 E015F9 0 +OP4 E015FA 0 +OP4 E015FB 0 +OP4 E015FC 0 +OP4 E015FD 0 +OP4 E015FE 0 +OP4 E015FF 0 +OP4 E01600 0 +OP4 E01601 0 +OP4 E01602 0 +OP4 E01603 0 +OP4 E01604 0 +OP4 E01605 0 +OP4 E01606 0 +OP4 E01607 0 +OP4 E01608 0 +OP4 E01609 0 +OP4 E0160A 0 +OP4 E0160B 0 +OP4 E0160C 0 +OP4 E0160D 0 +OP4 E0160E 0 +OP4 E0160F 0 +OP4 E01610 0 +OP4 E01611 0 +OP4 E01612 0 +OP4 E01613 0 +OP4 E01614 0 +OP4 E01615 0 +OP4 E01616 0 +OP4 E01617 0 +OP4 E01618 0 +OP4 E01619 0 +OP4 E0161A 0 +OP4 E0161B 0 +OP4 E0161C 0 +OP4 E0161D 0 +OP4 E0161E 0 +OP4 E0161F 0 +OP4 E01620 0 +OP4 E01621 0 +OP4 E01622 0 +OP4 E01623 0 +OP4 E01624 0 +OP4 E01625 0 +OP4 E01626 0 +OP4 E01627 0 +OP4 E01628 0 +OP4 E01629 0 +OP4 E0162A 0 +OP4 E0162B 0 +OP4 E0162C 0 +OP4 E0162D 0 +OP4 E0162E 0 +OP4 E0162F 0 +OP4 E01630 0 +OP4 E01631 0 +OP4 E01632 0 +OP4 E01633 0 +OP4 E01634 0 +OP4 E01635 0 +OP4 E01636 0 +OP4 E01637 0 +OP4 E01638 0 +OP4 E01639 0 +OP4 E0163A 0 +OP4 E0163B 0 +OP4 E0163C 0 +OP4 E0163D 0 +OP4 E0163E 0 +OP4 E0163F 0 +OP4 E01640 0 +OP4 E01641 0 +OP4 E01642 0 +OP4 E01643 0 +OP4 E01644 0 +OP4 E01645 0 +OP4 E01646 0 +OP4 E01647 0 +OP4 E01648 0 +OP4 E01649 0 +OP4 E0164A 0 +OP4 E0164B 0 +OP4 E0164C 0 +OP4 E0164D 0 +OP4 E0164E 0 +OP4 E0164F 0 +OP4 E01650 0 +OP4 E01651 0 +OP4 E01652 0 +OP4 E01653 0 +OP4 E01654 0 +OP4 E01655 0 +OP4 E01656 0 +OP4 E01657 0 +OP4 E01658 0 +OP4 E01659 0 +OP4 E0165A 0 +OP4 E0165B 0 +OP4 E0165C 0 +OP4 E0165D 0 +OP4 E0165E 0 +OP4 E0165F 0 +OP4 E01660 0 +OP4 E01661 0 +OP4 E01662 0 +OP4 E01663 0 +OP4 E01664 0 +OP4 E01665 0 +OP4 E01666 0 +OP4 E01667 0 +OP4 E01668 0 +OP4 E01669 0 +OP4 E0166A 0 +OP4 E0166B 0 +OP4 E0166C 0 +OP4 E0166D 0 +OP4 E0166E 0 +OP4 E0166F 0 +OP4 E01670 0 +OP4 E01671 0 +OP4 E01672 0 +OP4 E01673 0 +OP4 E01674 0 +OP4 E01675 0 +OP4 E01676 0 +OP4 E01677 0 +OP4 E01678 0 +OP4 E01679 0 +OP4 E0167A 0 +OP4 E0167B 0 +OP4 E0167C 0 +OP4 E0167D 0 +OP4 E0167E 0 +OP4 E0167F 0 +OP4 E01680 0 +OP4 E01681 0 +OP4 E01682 0 +OP4 E01683 0 +OP4 E01684 0 +OP4 E01685 0 +OP4 E01686 0 +OP4 E01687 0 +OP4 E01688 0 +OP4 E01689 0 +OP4 E0168A 0 +OP4 E0168B 0 +OP4 E0168C 0 +OP4 E0168D 0 +OP4 E0168E 0 +OP4 E0168F 0 +OP4 E01690 0 +OP4 E01691 0 +OP4 E01692 0 +OP4 E01693 0 +OP4 E01694 0 +OP4 E01695 0 +OP4 E01696 0 +OP4 E01697 0 +OP4 E01698 0 +OP4 E01699 0 +OP4 E0169A 0 +OP4 E0169B 0 +OP4 E0169C 0 +OP4 E0169D 0 +OP4 E0169E 0 +OP4 E0169F 0 +OP4 E016A0 0 +OP4 E016A1 0 +OP4 E016A2 0 +OP4 E016A3 0 +OP4 E016A4 0 +OP4 E016A5 0 +OP4 E016A6 0 +OP4 E016A7 0 +OP4 E016A8 0 +OP4 E016A9 0 +OP4 E016AA 0 +OP4 E016AB 0 +OP4 E016AC 0 +OP4 E016AD 0 +OP4 E016AE 0 +OP4 E016AF 0 +OP4 E016B0 0 +OP4 E016B1 0 +OP4 E016B2 0 +OP4 E016B3 0 +OP4 E016B4 0 +OP4 E016B5 0 +OP4 E016B6 0 +OP4 E016B7 0 +OP4 E016B8 0 +OP4 E016B9 0 +OP4 E016BA 0 +OP4 E016BB 0 +OP4 E016BC 0 +OP4 E016BD 0 +OP4 E016BE 0 +OP4 E016BF 0 +OP4 E016C0 0 +OP4 E016C1 0 +OP4 E016C2 0 +OP4 E016C3 0 +OP4 E016C4 0 +OP4 E016C5 0 +OP4 E016C6 0 +OP4 E016C7 0 +OP4 E016C8 0 +OP4 E016C9 0 +OP4 E016CA 0 +OP4 E016CB 0 +OP4 E016CC 0 +OP4 E016CD 0 +OP4 E016CE 0 +OP4 E016CF 0 +OP4 E016D0 0 +OP4 E016D1 0 +OP4 E016D2 0 +OP4 E016D3 0 +OP4 E016D4 0 +OP4 E016D5 0 +OP4 E016D6 0 +OP4 E016D7 0 +OP4 E016D8 0 +OP4 E016D9 0 +OP4 E016DA 0 +OP4 E016DB 0 +OP4 E016DC 0 +OP4 E016DD 0 +OP4 E016DE 0 +OP4 E016DF 0 +OP4 E016E0 0 +OP4 E016E1 0 +OP4 E016E2 0 +OP4 E016E3 0 +OP4 E016E4 0 +OP4 E016E5 0 +OP4 E016E6 0 +OP4 E016E7 0 +OP4 E016E8 0 +OP4 E016E9 0 +OP4 E016EA 0 +OP4 E016EB 0 +OP4 E016EC 0 +OP4 E016ED 0 +OP4 E016EE 0 +OP4 E016EF 0 +OP4 E016F0 0 +OP4 E016F1 0 +OP4 E016F2 0 +OP4 E016F3 0 +OP4 E016F4 0 +OP4 E016F5 0 +OP4 E016F6 0 +OP4 E016F7 0 +OP4 E016F8 0 +OP4 E016F9 0 +OP4 E016FA 0 +OP4 E016FB 0 +OP4 E016FC 0 +OP4 E016FD 0 +OP4 E016FE 0 +OP4 E016FF 0 +OP4 E01700 0 +OP4 E01701 0 +OP4 E01702 0 +OP4 E01703 0 +OP4 E01704 0 +OP4 E01705 0 +OP4 E01706 0 +OP4 E01707 0 +OP4 E01708 0 +OP4 E01709 0 +OP4 E0170A 0 +OP4 E0170B 0 +OP4 E0170C 0 +OP4 E0170D 0 +OP4 E0170E 0 +OP4 E0170F 0 +OP4 E01710 0 +OP4 E01711 0 +OP4 E01712 0 +OP4 E01713 0 +OP4 E01714 0 +OP4 E01715 0 +OP4 E01716 0 +OP4 E01717 0 +OP4 E01718 0 +OP4 E01719 0 +OP4 E0171A 0 +OP4 E0171B 0 +OP4 E0171C 0 +OP4 E0171D 0 +OP4 E0171E 0 +OP4 E0171F 0 +OP4 E01720 0 +OP4 E01721 0 +OP4 E01722 0 +OP4 E01723 0 +OP4 E01724 0 +OP4 E01725 0 +OP4 E01726 0 +OP4 E01727 0 +OP4 E01728 0 +OP4 E01729 0 +OP4 E0172A 0 +OP4 E0172B 0 +OP4 E0172C 0 +OP4 E0172D 0 +OP4 E0172E 0 +OP4 E0172F 0 +OP4 E01730 0 +OP4 E01731 0 +OP4 E01732 0 +OP4 E01733 0 +OP4 E01734 0 +OP4 E01735 0 +OP4 E01736 0 +OP4 E01737 0 +OP4 E01738 0 +OP4 E01739 0 +OP4 E0173A 0 +OP4 E0173B 0 +OP4 E0173C 0 +OP4 E0173D 0 +OP4 E0173E 0 +OP4 E0173F 0 +OP4 E01740 0 +OP4 E01741 0 +OP4 E01742 0 +OP4 E01743 0 +OP4 E01744 0 +OP4 E01745 0 +OP4 E01746 0 +OP4 E01747 0 +OP4 E01748 0 +OP4 E01749 0 +OP4 E0174A 0 +OP4 E0174B 0 +OP4 E0174C 0 +OP4 E0174D 0 +OP4 E0174E 0 +OP4 E0174F 0 +OP4 E01750 0 +OP4 E01751 0 +OP4 E01752 0 +OP4 E01753 0 +OP4 E01754 0 +OP4 E01755 0 +OP4 E01756 0 +OP4 E01757 0 +OP4 E01758 0 +OP4 E01759 0 +OP4 E0175A 0 +OP4 E0175B 0 +OP4 E0175C 0 +OP4 E0175D 0 +OP4 E0175E 0 +OP4 E0175F 0 +OP4 E01760 0 +OP4 E01761 0 +OP4 E01762 0 +OP4 E01763 0 +OP4 E01764 0 +OP4 E01765 0 +OP4 E01766 0 +OP4 E01767 0 +OP4 E01768 0 +OP4 E01769 0 +OP4 E0176A 0 +OP4 E0176B 0 +OP4 E0176C 0 +OP4 E0176D 0 +OP4 E0176E 0 +OP4 E0176F 0 +OP4 E01770 0 +OP4 E01771 0 +OP4 E01772 0 +OP4 E01773 0 +OP4 E01774 0 +OP4 E01775 0 +OP4 E01776 0 +OP4 E01777 0 +OP4 E01778 0 +OP4 E01779 0 +OP4 E0177A 0 +OP4 E0177B 0 +OP4 E0177C 0 +OP4 E0177D 0 +OP4 E0177E 0 +OP4 E0177F 0 +OP4 E01780 0 +OP4 E01781 0 +OP4 E01782 0 +OP4 E01783 0 +OP4 E01784 0 +OP4 E01785 0 +OP4 E01786 0 +OP4 E01787 0 +OP4 E01788 0 +OP4 E01789 0 +OP4 E0178A 0 +OP4 E0178B 0 +OP4 E0178C 0 +OP4 E0178D 0 +OP4 E0178E 0 +OP4 E0178F 0 +OP4 E01790 0 +OP4 E01791 0 +OP4 E01792 0 +OP4 E01793 0 +OP4 E01794 0 +OP4 E01795 0 +OP4 E01796 0 +OP4 E01797 0 +OP4 E01798 0 +OP4 E01799 0 +OP4 E0179A 0 +OP4 E0179B 0 +OP4 E0179C 0 +OP4 E0179D 0 +OP4 E0179E 0 +OP4 E0179F 0 +OP4 E017A0 0 +OP4 E017A1 0 +OP4 E017A2 0 +OP4 E017A3 0 +OP4 E017A4 0 +OP4 E017A5 0 +OP4 E017A6 0 +OP4 E017A7 0 +OP4 E017A8 0 +OP4 E017A9 0 +OP4 E017AA 0 +OP4 E017AB 0 +OP4 E017AC 0 +OP4 E017AD 0 +OP4 E017AE 0 +OP4 E017AF 0 +OP4 E017B0 0 +OP4 E017B1 0 +OP4 E017B2 0 +OP4 E017B3 0 +OP4 E017B4 0 +OP4 E017B5 0 +OP4 E017B6 0 +OP4 E017B7 0 +OP4 E017B8 0 +OP4 E017B9 0 +OP4 E017BA 0 +OP4 E017BB 0 +OP4 E017BC 0 +OP4 E017BD 0 +OP4 E017BE 0 +OP4 E017BF 0 +OP4 E017C0 0 +OP4 E017C1 0 +OP4 E017C2 0 +OP4 E017C3 0 +OP4 E017C4 0 +OP4 E017C5 0 +OP4 E017C6 0 +OP4 E017C7 0 +OP4 E017C8 0 +OP4 E017C9 0 +OP4 E017CA 0 +OP4 E017CB 0 +OP4 E017CC 0 +OP4 E017CD 0 +OP4 E017CE 0 +OP4 E017CF 0 +OP4 E017D0 0 +OP4 E017D1 0 +OP4 E017D2 0 +OP4 E017D3 0 +OP4 E017D4 0 +OP4 E017D5 0 +OP4 E017D6 0 +OP4 E017D7 0 +OP4 E017D8 0 +OP4 E017D9 0 +OP4 E017DA 0 +OP4 E017DB 0 +OP4 E017DC 0 +OP4 E017DD 0 +OP4 E017DE 0 +OP4 E017DF 0 +OP4 E017E0 0 +OP4 E017E1 0 +OP4 E017E2 0 +OP4 E017E3 0 +OP4 E017E4 0 +OP4 E017E5 0 +OP4 E017E6 0 +OP4 E017E7 0 +OP4 E017E8 0 +OP4 E017E9 0 +OP4 E017EA 0 +OP4 E017EB 0 +OP4 E017EC 0 +OP4 E017ED 0 +OP4 E017EE 0 +OP4 E017EF 0 +OP4 E017F0 0 +OP4 E017F1 0 +OP4 E017F2 0 +OP4 E017F3 0 +OP4 E017F4 0 +OP4 E017F5 0 +OP4 E017F6 0 +OP4 E017F7 0 +OP4 E017F8 0 +OP4 E017F9 0 +OP4 E017FA 0 +OP4 E017FB 0 +OP4 E017FC 0 +OP4 E017FD 0 +OP4 E017FE 0 +OP4 E017FF 0 +OP4 E01800 0 +OP4 E01801 0 +OP4 E01802 0 +OP4 E01803 0 +OP4 E01804 0 +OP4 E01805 0 +OP4 E01806 0 +OP4 E01807 0 +OP4 E01808 0 +OP4 E01809 0 +OP4 E0180A 0 +OP4 E0180B 0 +OP4 E0180C 0 +OP4 E0180D 0 +OP4 E0180E 0 +OP4 E0180F 0 +OP4 E01810 0 +OP4 E01811 0 +OP4 E01812 0 +OP4 E01813 0 +OP4 E01814 0 +OP4 E01815 0 +OP4 E01816 0 +OP4 E01817 0 +OP4 E01818 0 +OP4 E01819 0 +OP4 E0181A 0 +OP4 E0181B 0 +OP4 E0181C 0 +OP4 E0181D 0 +OP4 E0181E 0 +OP4 E0181F 0 +OP4 E01820 0 +OP4 E01821 0 +OP4 E01822 0 +OP4 E01823 0 +OP4 E01824 0 +OP4 E01825 0 +OP4 E01826 0 +OP4 E01827 0 +OP4 E01828 0 +OP4 E01829 0 +OP4 E0182A 0 +OP4 E0182B 0 +OP4 E0182C 0 +OP4 E0182D 0 +OP4 E0182E 0 +OP4 E0182F 0 +OP4 E01830 0 +OP4 E01831 0 +OP4 E01832 0 +OP4 E01833 0 +OP4 E01834 0 +OP4 E01835 0 +OP4 E01836 0 +OP4 E01837 0 +OP4 E01838 0 +OP4 E01839 0 +OP4 E0183A 0 +OP4 E0183B 0 +OP4 E0183C 0 +OP4 E0183D 0 +OP4 E0183E 0 +OP4 E0183F 0 +OP4 E01840 0 +OP4 E01841 0 +OP4 E01842 0 +OP4 E01843 0 +OP4 E01844 0 +OP4 E01845 0 +OP4 E01846 0 +OP4 E01847 0 +OP4 E01848 0 +OP4 E01849 0 +OP4 E0184A 0 +OP4 E0184B 0 +OP4 E0184C 0 +OP4 E0184D 0 +OP4 E0184E 0 +OP4 E0184F 0 +OP4 E01850 0 +OP4 E01851 0 +OP4 E01852 0 +OP4 E01853 0 +OP4 E01854 0 +OP4 E01855 0 +OP4 E01856 0 +OP4 E01857 0 +OP4 E01858 0 +OP4 E01859 0 +OP4 E0185A 0 +OP4 E0185B 0 +OP4 E0185C 0 +OP4 E0185D 0 +OP4 E0185E 0 +OP4 E0185F 0 +OP4 E01860 0 +OP4 E01861 0 +OP4 E01862 0 +OP4 E01863 0 +OP4 E01864 0 +OP4 E01865 0 +OP4 E01866 0 +OP4 E01867 0 +OP4 E01868 0 +OP4 E01869 0 +OP4 E0186A 0 +OP4 E0186B 0 +OP4 E0186C 0 +OP4 E0186D 0 +OP4 E0186E 0 +OP4 E0186F 0 +OP4 E01870 0 +OP4 E01871 0 +OP4 E01872 0 +OP4 E01873 0 +OP4 E01874 0 +OP4 E01875 0 +OP4 E01876 0 +OP4 E01877 0 +OP4 E01878 0 +OP4 E01879 0 +OP4 E0187A 0 +OP4 E0187B 0 +OP4 E0187C 0 +OP4 E0187D 0 +OP4 E0187E 0 +OP4 E0187F 0 +OP4 E01880 0 +OP4 E01881 0 +OP4 E01882 0 +OP4 E01883 0 +OP4 E01884 0 +OP4 E01885 0 +OP4 E01886 0 +OP4 E01887 0 +OP4 E01888 0 +OP4 E01889 0 +OP4 E0188A 0 +OP4 E0188B 0 +OP4 E0188C 0 +OP4 E0188D 0 +OP4 E0188E 0 +OP4 E0188F 0 +OP4 E01890 0 +OP4 E01891 0 +OP4 E01892 0 +OP4 E01893 0 +OP4 E01894 0 +OP4 E01895 0 +OP4 E01896 0 +OP4 E01897 0 +OP4 E01898 0 +OP4 E01899 0 +OP4 E0189A 0 +OP4 E0189B 0 +OP4 E0189C 0 +OP4 E0189D 0 +OP4 E0189E 0 +OP4 E0189F 0 +OP4 E018A0 0 +OP4 E018A1 0 +OP4 E018A2 0 +OP4 E018A3 0 +OP4 E018A4 0 +OP4 E018A5 0 +OP4 E018A6 0 +OP4 E018A7 0 +OP4 E018A8 0 +OP4 E018A9 0 +OP4 E018AA 0 +OP4 E018AB 0 +OP4 E018AC 0 +OP4 E018AD 0 +OP4 E018AE 0 +OP4 E018AF 0 +OP4 E018B0 0 +OP4 E018B1 0 +OP4 E018B2 0 +OP4 E018B3 0 +OP4 E018B4 0 +OP4 E018B5 0 +OP4 E018B6 0 +OP4 E018B7 0 +OP4 E018B8 0 +OP4 E018B9 0 +OP4 E018BA 0 +OP4 E018BB 0 +OP4 E018BC 0 +OP4 E018BD 0 +OP4 E018BE 0 +OP4 E018BF 0 +OP4 E018C0 0 +OP4 E018C1 0 +OP4 E018C2 0 +OP4 E018C3 0 +OP4 E018C4 0 +OP4 E018C5 0 +OP4 E018C6 0 +OP4 E018C7 0 +OP4 E018C8 0 +OP4 E018C9 0 +OP4 E018CA 0 +OP4 E018CB 0 +OP4 E018CC 0 +OP4 E018CD 0 +OP4 E018CE 0 +OP4 E018CF 0 +OP4 E018D0 0 +OP4 E018D1 0 +OP4 E018D2 0 +OP4 E018D3 0 +OP4 E018D4 0 +OP4 E018D5 0 +OP4 E018D6 0 +OP4 E018D7 0 +OP4 E018D8 0 +OP4 E018D9 0 +OP4 E018DA 0 +OP4 E018DB 0 +OP4 E018DC 0 +OP4 E018DD 0 +OP4 E018DE 0 +OP4 E018DF 0 +OP4 E018E0 0 +OP4 E018E1 0 +OP4 E018E2 0 +OP4 E018E3 0 +OP4 E018E4 0 +OP4 E018E5 0 +OP4 E018E6 0 +OP4 E018E7 0 +OP4 E018E8 0 +OP4 E018E9 0 +OP4 E018EA 0 +OP4 E018EB 0 +OP4 E018EC 0 +OP4 E018ED 0 +OP4 E018EE 0 +OP4 E018EF 0 +OP4 E018F0 0 +OP4 E018F1 0 +OP4 E018F2 0 +OP4 E018F3 0 +OP4 E018F4 0 +OP4 E018F5 0 +OP4 E018F6 0 +OP4 E018F7 0 +OP4 E018F8 0 +OP4 E018F9 0 +OP4 E018FA 0 +OP4 E018FB 0 +OP4 E018FC 0 +OP4 E018FD 0 +OP4 E018FE 0 +OP4 E018FF 0 +OP4 E01900 0 +OP4 E01901 0 +OP4 E01902 0 +OP4 E01903 0 +OP4 E01904 0 +OP4 E01905 0 +OP4 E01906 0 +OP4 E01907 0 +OP4 E01908 0 +OP4 E01909 0 +OP4 E0190A 0 +OP4 E0190B 0 +OP4 E0190C 0 +OP4 E0190D 0 +OP4 E0190E 0 +OP4 E0190F 0 +OP4 E01910 0 +OP4 E01911 0 +OP4 E01912 0 +OP4 E01913 0 +OP4 E01914 0 +OP4 E01915 0 +OP4 E01916 0 +OP4 E01917 0 +OP4 E01918 0 +OP4 E01919 0 +OP4 E0191A 0 +OP4 E0191B 0 +OP4 E0191C 0 +OP4 E0191D 0 +OP4 E0191E 0 +OP4 E0191F 0 +OP4 E01920 0 +OP4 E01921 0 +OP4 E01922 0 +OP4 E01923 0 +OP4 E01924 0 +OP4 E01925 0 +OP4 E01926 0 +OP4 E01927 0 +OP4 E01928 0 +OP4 E01929 0 +OP4 E0192A 0 +OP4 E0192B 0 +OP4 E0192C 0 +OP4 E0192D 0 +OP4 E0192E 0 +OP4 E0192F 0 +OP4 E01930 0 +OP4 E01931 0 +OP4 E01932 0 +OP4 E01933 0 +OP4 E01934 0 +OP4 E01935 0 +OP4 E01936 0 +OP4 E01937 0 +OP4 E01938 0 +OP4 E01939 0 +OP4 E0193A 0 +OP4 E0193B 0 +OP4 E0193C 0 +OP4 E0193D 0 +OP4 E0193E 0 +OP4 E0193F 0 +OP4 E01940 0 +OP4 E01941 0 +OP4 E01942 0 +OP4 E01943 0 +OP4 E01944 0 +OP4 E01945 0 +OP4 E01946 0 +OP4 E01947 0 +OP4 E01948 0 +OP4 E01949 0 +OP4 E0194A 0 +OP4 E0194B 0 +OP4 E0194C 0 +OP4 E0194D 0 +OP4 E0194E 0 +OP4 E0194F 0 +OP4 E01950 0 +OP4 E01951 0 +OP4 E01952 0 +OP4 E01953 0 +OP4 E01954 0 +OP4 E01955 0 +OP4 E01956 0 +OP4 E01957 0 +OP4 E01958 0 +OP4 E01959 0 +OP4 E0195A 0 +OP4 E0195B 0 +OP4 E0195C 0 +OP4 E0195D 0 +OP4 E0195E 0 +OP4 E0195F 0 +OP4 E01960 0 +OP4 E01961 0 +OP4 E01962 0 +OP4 E01963 0 +OP4 E01964 0 +OP4 E01965 0 +OP4 E01966 0 +OP4 E01967 0 +OP4 E01968 0 +OP4 E01969 0 +OP4 E0196A 0 +OP4 E0196B 0 +OP4 E0196C 0 +OP4 E0196D 0 +OP4 E0196E 0 +OP4 E0196F 0 +OP4 E01970 0 +OP4 E01971 0 +OP4 E01972 0 +OP4 E01973 0 +OP4 E01974 0 +OP4 E01975 0 +OP4 E01976 0 +OP4 E01977 0 +OP4 E01978 0 +OP4 E01979 0 +OP4 E0197A 0 +OP4 E0197B 0 +OP4 E0197C 0 +OP4 E0197D 0 +OP4 E0197E 0 +OP4 E0197F 0 +OP4 E01980 0 +OP4 E01981 0 +OP4 E01982 0 +OP4 E01983 0 +OP4 E01984 0 +OP4 E01985 0 +OP4 E01986 0 +OP4 E01987 0 +OP4 E01988 0 +OP4 E01989 0 +OP4 E0198A 0 +OP4 E0198B 0 +OP4 E0198C 0 +OP4 E0198D 0 +OP4 E0198E 0 +OP4 E0198F 0 +OP4 E01990 0 +OP4 E01991 0 +OP4 E01992 0 +OP4 E01993 0 +OP4 E01994 0 +OP4 E01995 0 +OP4 E01996 0 +OP4 E01997 0 +OP4 E01998 0 +OP4 E01999 0 +OP4 E0199A 0 +OP4 E0199B 0 +OP4 E0199C 0 +OP4 E0199D 0 +OP4 E0199E 0 +OP4 E0199F 0 +OP4 E019A0 0 +OP4 E019A1 0 +OP4 E019A2 0 +OP4 E019A3 0 +OP4 E019A4 0 +OP4 E019A5 0 +OP4 E019A6 0 +OP4 E019A7 0 +OP4 E019A8 0 +OP4 E019A9 0 +OP4 E019AA 0 +OP4 E019AB 0 +OP4 E019AC 0 +OP4 E019AD 0 +OP4 E019AE 0 +OP4 E019AF 0 +OP4 E019B0 0 +OP4 E019B1 0 +OP4 E019B2 0 +OP4 E019B3 0 +OP4 E019B4 0 +OP4 E019B5 0 +OP4 E019B6 0 +OP4 E019B7 0 +OP4 E019B8 0 +OP4 E019B9 0 +OP4 E019BA 0 +OP4 E019BB 0 +OP4 E019BC 0 +OP4 E019BD 0 +OP4 E019BE 0 +OP4 E019BF 0 +OP4 E019C0 0 +OP4 E019C1 0 +OP4 E019C2 0 +OP4 E019C3 0 +OP4 E019C4 0 +OP4 E019C5 0 +OP4 E019C6 0 +OP4 E019C7 0 +OP4 E019C8 0 +OP4 E019C9 0 +OP4 E019CA 0 +OP4 E019CB 0 +OP4 E019CC 0 +OP4 E019CD 0 +OP4 E019CE 0 +OP4 E019CF 0 +OP4 E019D0 0 +OP4 E019D1 0 +OP4 E019D2 0 +OP4 E019D3 0 +OP4 E019D4 0 +OP4 E019D5 0 +OP4 E019D6 0 +OP4 E019D7 0 +OP4 E019D8 0 +OP4 E019D9 0 +OP4 E019DA 0 +OP4 E019DB 0 +OP4 E019DC 0 +OP4 E019DD 0 +OP4 E019DE 0 +OP4 E019DF 0 +OP4 E019E0 0 +OP4 E019E1 0 +OP4 E019E2 0 +OP4 E019E3 0 +OP4 E019E4 0 +OP4 E019E5 0 +OP4 E019E6 0 +OP4 E019E7 0 +OP4 E019E8 0 +OP4 E019E9 0 +OP4 E019EA 0 +OP4 E019EB 0 +OP4 E019EC 0 +OP4 E019ED 0 +OP4 E019EE 0 +OP4 E019EF 0 +OP4 E019F0 0 +OP4 E019F1 0 +OP4 E019F2 0 +OP4 E019F3 0 +OP4 E019F4 0 +OP4 E019F5 0 +OP4 E019F6 0 +OP4 E019F7 0 +OP4 E019F8 0 +OP4 E019F9 0 +OP4 E019FA 0 +OP4 E019FB 0 +OP4 E019FC 0 +OP4 E019FD 0 +OP4 E019FE 0 +OP4 E019FF 0 +OP4 E01A00 0 +OP4 E01A01 0 +OP4 E01A02 0 +OP4 E01A03 0 +OP4 E01A04 0 +OP4 E01A05 0 +OP4 E01A06 0 +OP4 E01A07 0 +OP4 E01A08 0 +OP4 E01A09 0 +OP4 E01A0A 0 +OP4 E01A0B 0 +OP4 E01A0C 0 +OP4 E01A0D 0 +OP4 E01A0E 0 +OP4 E01A0F 0 +OP4 E01A10 0 +OP4 E01A11 0 +OP4 E01A12 0 +OP4 E01A13 0 +OP4 E01A14 0 +OP4 E01A15 0 +OP4 E01A16 0 +OP4 E01A17 0 +OP4 E01A18 0 +OP4 E01A19 0 +OP4 E01A1A 0 +OP4 E01A1B 0 +OP4 E01A1C 0 +OP4 E01A1D 0 +OP4 E01A1E 0 +OP4 E01A1F 0 +OP4 E01A20 0 +OP4 E01A21 0 +OP4 E01A22 0 +OP4 E01A23 0 +OP4 E01A24 0 +OP4 E01A25 0 +OP4 E01A26 0 +OP4 E01A27 0 +OP4 E01A28 0 +OP4 E01A29 0 +OP4 E01A2A 0 +OP4 E01A2B 0 +OP4 E01A2C 0 +OP4 E01A2D 0 +OP4 E01A2E 0 +OP4 E01A2F 0 +OP4 E01A30 0 +OP4 E01A31 0 +OP4 E01A32 0 +OP4 E01A33 0 +OP4 E01A34 0 +OP4 E01A35 0 +OP4 E01A36 0 +OP4 E01A37 0 +OP4 E01A38 0 +OP4 E01A39 0 +OP4 E01A3A 0 +OP4 E01A3B 0 +OP4 E01A3C 0 +OP4 E01A3D 0 +OP4 E01A3E 0 +OP4 E01A3F 0 +OP4 E01A40 0 +OP4 E01A41 0 +OP4 E01A42 0 +OP4 E01A43 0 +OP4 E01A44 0 +OP4 E01A45 0 +OP4 E01A46 0 +OP4 E01A47 0 +OP4 E01A48 0 +OP4 E01A49 0 +OP4 E01A4A 0 +OP4 E01A4B 0 +OP4 E01A4C 0 +OP4 E01A4D 0 +OP4 E01A4E 0 +OP4 E01A4F 0 +OP4 E01A50 0 +OP4 E01A51 0 +OP4 E01A52 0 +OP4 E01A53 0 +OP4 E01A54 0 +OP4 E01A55 0 +OP4 E01A56 0 +OP4 E01A57 0 +OP4 E01A58 0 +OP4 E01A59 0 +OP4 E01A5A 0 +OP4 E01A5B 0 +OP4 E01A5C 0 +OP4 E01A5D 0 +OP4 E01A5E 0 +OP4 E01A5F 0 +OP4 E01A60 0 +OP4 E01A61 0 +OP4 E01A62 0 +OP4 E01A63 0 +OP4 E01A64 0 +OP4 E01A65 0 +OP4 E01A66 0 +OP4 E01A67 0 +OP4 E01A68 0 +OP4 E01A69 0 +OP4 E01A6A 0 +OP4 E01A6B 0 +OP4 E01A6C 0 +OP4 E01A6D 0 +OP4 E01A6E 0 +OP4 E01A6F 0 +OP4 E01A70 0 +OP4 E01A71 0 +OP4 E01A72 0 +OP4 E01A73 0 +OP4 E01A74 0 +OP4 E01A75 0 +OP4 E01A76 0 +OP4 E01A77 0 +OP4 E01A78 0 +OP4 E01A79 0 +OP4 E01A7A 0 +OP4 E01A7B 0 +OP4 E01A7C 0 +OP4 E01A7D 0 +OP4 E01A7E 0 +OP4 E01A7F 0 +OP4 E01A80 0 +OP4 E01A81 0 +OP4 E01A82 0 +OP4 E01A83 0 +OP4 E01A84 0 +OP4 E01A85 0 +OP4 E01A86 0 +OP4 E01A87 0 +OP4 E01A88 0 +OP4 E01A89 0 +OP4 E01A8A 0 +OP4 E01A8B 0 +OP4 E01A8C 0 +OP4 E01A8D 0 +OP4 E01A8E 0 +OP4 E01A8F 0 +OP4 E01A90 0 +OP4 E01A91 0 +OP4 E01A92 0 +OP4 E01A93 0 +OP4 E01A94 0 +OP4 E01A95 0 +OP4 E01A96 0 +OP4 E01A97 0 +OP4 E01A98 0 +OP4 E01A99 0 +OP4 E01A9A 0 +OP4 E01A9B 0 +OP4 E01A9C 0 +OP4 E01A9D 0 +OP4 E01A9E 0 +OP4 E01A9F 0 +OP4 E01AA0 0 +OP4 E01AA1 0 +OP4 E01AA2 0 +OP4 E01AA3 0 +OP4 E01AA4 0 +OP4 E01AA5 0 +OP4 E01AA6 0 +OP4 E01AA7 0 +OP4 E01AA8 0 +OP4 E01AA9 0 +OP4 E01AAA 0 +OP4 E01AAB 0 +OP4 E01AAC 0 +OP4 E01AAD 0 +OP4 E01AAE 0 +OP4 E01AAF 0 +OP4 E01AB0 0 +OP4 E01AB1 0 +OP4 E01AB2 0 +OP4 E01AB3 0 +OP4 E01AB4 0 +OP4 E01AB5 0 +OP4 E01AB6 0 +OP4 E01AB7 0 +OP4 E01AB8 0 +OP4 E01AB9 0 +OP4 E01ABA 0 +OP4 E01ABB 0 +OP4 E01ABC 0 +OP4 E01ABD 0 +OP4 E01ABE 0 +OP4 E01ABF 0 +OP4 E01AC0 0 +OP4 E01AC1 0 +OP4 E01AC2 0 +OP4 E01AC3 0 +OP4 E01AC4 0 +OP4 E01AC5 0 +OP4 E01AC6 0 +OP4 E01AC7 0 +OP4 E01AC8 0 +OP4 E01AC9 0 +OP4 E01ACA 0 +OP4 E01ACB 0 +OP4 E01ACC 0 +OP4 E01ACD 0 +OP4 E01ACE 0 +OP4 E01ACF 0 +OP4 E01AD0 0 +OP4 E01AD1 0 +OP4 E01AD2 0 +OP4 E01AD3 0 +OP4 E01AD4 0 +OP4 E01AD5 0 +OP4 E01AD6 0 +OP4 E01AD7 0 +OP4 E01AD8 0 +OP4 E01AD9 0 +OP4 E01ADA 0 +OP4 E01ADB 0 +OP4 E01ADC 0 +OP4 E01ADD 0 +OP4 E01ADE 0 +OP4 E01ADF 0 +OP4 E01AE0 0 +OP4 E01AE1 0 +OP4 E01AE2 0 +OP4 E01AE3 0 +OP4 E01AE4 0 +OP4 E01AE5 0 +OP4 E01AE6 0 +OP4 E01AE7 0 +OP4 E01AE8 0 +OP4 E01AE9 0 +OP4 E01AEA 0 +OP4 E01AEB 0 +OP4 E01AEC 0 +OP4 E01AED 0 +OP4 E01AEE 0 +OP4 E01AEF 0 +OP4 E01AF0 0 +OP4 E01AF1 0 +OP4 E01AF2 0 +OP4 E01AF3 0 +OP4 E01AF4 0 +OP4 E01AF5 0 +OP4 E01AF6 0 +OP4 E01AF7 0 +OP4 E01AF8 0 +OP4 E01AF9 0 +OP4 E01AFA 0 +OP4 E01AFB 0 +OP4 E01AFC 0 +OP4 E01AFD 0 +OP4 E01AFE 0 +OP4 E01AFF 0 +OP4 E01B00 0 +OP4 E01B01 0 +OP4 E01B02 0 +OP4 E01B03 0 +OP4 E01B04 0 +OP4 E01B05 0 +OP4 E01B06 0 +OP4 E01B07 0 +OP4 E01B08 0 +OP4 E01B09 0 +OP4 E01B0A 0 +OP4 E01B0B 0 +OP4 E01B0C 0 +OP4 E01B0D 0 +OP4 E01B0E 0 +OP4 E01B0F 0 +OP4 E01B10 0 +OP4 E01B11 0 +OP4 E01B12 0 +OP4 E01B13 0 +OP4 E01B14 0 +OP4 E01B15 0 +OP4 E01B16 0 +OP4 E01B17 0 +OP4 E01B18 0 +OP4 E01B19 0 +OP4 E01B1A 0 +OP4 E01B1B 0 +OP4 E01B1C 0 +OP4 E01B1D 0 +OP4 E01B1E 0 +OP4 E01B1F 0 +OP4 E01B20 0 +OP4 E01B21 0 +OP4 E01B22 0 +OP4 E01B23 0 +OP4 E01B24 0 +OP4 E01B25 0 +OP4 E01B26 0 +OP4 E01B27 0 +OP4 E01B28 0 +OP4 E01B29 0 +OP4 E01B2A 0 +OP4 E01B2B 0 +OP4 E01B2C 0 +OP4 E01B2D 0 +OP4 E01B2E 0 +OP4 E01B2F 0 +OP4 E01B30 0 +OP4 E01B31 0 +OP4 E01B32 0 +OP4 E01B33 0 +OP4 E01B34 0 +OP4 E01B35 0 +OP4 E01B36 0 +OP4 E01B37 0 +OP4 E01B38 0 +OP4 E01B39 0 +OP4 E01B3A 0 +OP4 E01B3B 0 +OP4 E01B3C 0 +OP4 E01B3D 0 +OP4 E01B3E 0 +OP4 E01B3F 0 +OP4 E01B40 0 +OP4 E01B41 0 +OP4 E01B42 0 +OP4 E01B43 0 +OP4 E01B44 0 +OP4 E01B45 0 +OP4 E01B46 0 +OP4 E01B47 0 +OP4 E01B48 0 +OP4 E01B49 0 +OP4 E01B4A 0 +OP4 E01B4B 0 +OP4 E01B4C 0 +OP4 E01B4D 0 +OP4 E01B4E 0 +OP4 E01B4F 0 +OP4 E01B50 0 +OP4 E01B51 0 +OP4 E01B52 0 +OP4 E01B53 0 +OP4 E01B54 0 +OP4 E01B55 0 +OP4 E01B56 0 +OP4 E01B57 0 +OP4 E01B58 0 +OP4 E01B59 0 +OP4 E01B5A 0 +OP4 E01B5B 0 +OP4 E01B5C 0 +OP4 E01B5D 0 +OP4 E01B5E 0 +OP4 E01B5F 0 +OP4 E01B60 0 +OP4 E01B61 0 +OP4 E01B62 0 +OP4 E01B63 0 +OP4 E01B64 0 +OP4 E01B65 0 +OP4 E01B66 0 +OP4 E01B67 0 +OP4 E01B68 0 +OP4 E01B69 0 +OP4 E01B6A 0 +OP4 E01B6B 0 +OP4 E01B6C 0 +OP4 E01B6D 0 +OP4 E01B6E 0 +OP4 E01B6F 0 +OP4 E01B70 0 +OP4 E01B71 0 +OP4 E01B72 0 +OP4 E01B73 0 +OP4 E01B74 0 +OP4 E01B75 0 +OP4 E01B76 0 +OP4 E01B77 0 +OP4 E01B78 0 +OP4 E01B79 0 +OP4 E01B7A 0 +OP4 E01B7B 0 +OP4 E01B7C 0 +OP4 E01B7D 0 +OP4 E01B7E 0 +OP4 E01B7F 0 +OP4 E01B80 0 +OP4 E01B81 0 +OP4 E01B82 0 +OP4 E01B83 0 +OP4 E01B84 0 +OP4 E01B85 0 +OP4 E01B86 0 +OP4 E01B87 0 +OP4 E01B88 0 +OP4 E01B89 0 +OP4 E01B8A 0 +OP4 E01B8B 0 +OP4 E01B8C 0 +OP4 E01B8D 0 +OP4 E01B8E 0 +OP4 E01B8F 0 +OP4 E01B90 0 +OP4 E01B91 0 +OP4 E01B92 0 +OP4 E01B93 0 +OP4 E01B94 0 +OP4 E01B95 0 +OP4 E01B96 0 +OP4 E01B97 0 +OP4 E01B98 0 +OP4 E01B99 0 +OP4 E01B9A 0 +OP4 E01B9B 0 +OP4 E01B9C 0 +OP4 E01B9D 0 +OP4 E01B9E 0 +OP4 E01B9F 0 +OP4 E01BA0 0 +OP4 E01BA1 0 +OP4 E01BA2 0 +OP4 E01BA3 0 +OP4 E01BA4 0 +OP4 E01BA5 0 +OP4 E01BA6 0 +OP4 E01BA7 0 +OP4 E01BA8 0 +OP4 E01BA9 0 +OP4 E01BAA 0 +OP4 E01BAB 0 +OP4 E01BAC 0 +OP4 E01BAD 0 +OP4 E01BAE 0 +OP4 E01BAF 0 +OP4 E01BB0 0 +OP4 E01BB1 0 +OP4 E01BB2 0 +OP4 E01BB3 0 +OP4 E01BB4 0 +OP4 E01BB5 0 +OP4 E01BB6 0 +OP4 E01BB7 0 +OP4 E01BB8 0 +OP4 E01BB9 0 +OP4 E01BBA 0 +OP4 E01BBB 0 +OP4 E01BBC 0 +OP4 E01BBD 0 +OP4 E01BBE 0 +OP4 E01BBF 0 +OP4 E01BC0 0 +OP4 E01BC1 0 +OP4 E01BC2 0 +OP4 E01BC3 0 +OP4 E01BC4 0 +OP4 E01BC5 0 +OP4 E01BC6 0 +OP4 E01BC7 0 +OP4 E01BC8 0 +OP4 E01BC9 0 +OP4 E01BCA 0 +OP4 E01BCB 0 +OP4 E01BCC 0 +OP4 E01BCD 0 +OP4 E01BCE 0 +OP4 E01BCF 0 +OP4 E01BD0 0 +OP4 E01BD1 0 +OP4 E01BD2 0 +OP4 E01BD3 0 +OP4 E01BD4 0 +OP4 E01BD5 0 +OP4 E01BD6 0 +OP4 E01BD7 0 +OP4 E01BD8 0 +OP4 E01BD9 0 +OP4 E01BDA 0 +OP4 E01BDB 0 +OP4 E01BDC 0 +OP4 E01BDD 0 +OP4 E01BDE 0 +OP4 E01BDF 0 +OP4 E01BE0 0 +OP4 E01BE1 0 +OP4 E01BE2 0 +OP4 E01BE3 0 +OP4 E01BE4 0 +OP4 E01BE5 0 +OP4 E01BE6 0 +OP4 E01BE7 0 +OP4 E01BE8 0 +OP4 E01BE9 0 +OP4 E01BEA 0 +OP4 E01BEB 0 +OP4 E01BEC 0 +OP4 E01BED 0 +OP4 E01BEE 0 +OP4 E01BEF 0 +OP4 E01BF0 0 +OP4 E01BF1 0 +OP4 E01BF2 0 +OP4 E01BF3 0 +OP4 E01BF4 0 +OP4 E01BF5 0 +OP4 E01BF6 0 +OP4 E01BF7 0 +OP4 E01BF8 0 +OP4 E01BF9 0 +OP4 E01BFA 0 +OP4 E01BFB 0 +OP4 E01BFC 0 +OP4 E01BFD 0 +OP4 E01BFE 0 +OP4 E01BFF 0 +OP4 E01C00 0 +OP4 E01C01 0 +OP4 E01C02 0 +OP4 E01C03 0 +OP4 E01C04 0 +OP4 E01C05 0 +OP4 E01C06 0 +OP4 E01C07 0 +OP4 E01C08 0 +OP4 E01C09 0 +OP4 E01C0A 0 +OP4 E01C0B 0 +OP4 E01C0C 0 +OP4 E01C0D 0 +OP4 E01C0E 0 +OP4 E01C0F 0 +OP4 E01C10 0 +OP4 E01C11 0 +OP4 E01C12 0 +OP4 E01C13 0 +OP4 E01C14 0 +OP4 E01C15 0 +OP4 E01C16 0 +OP4 E01C17 0 +OP4 E01C18 0 +OP4 E01C19 0 +OP4 E01C1A 0 +OP4 E01C1B 0 +OP4 E01C1C 0 +OP4 E01C1D 0 +OP4 E01C1E 0 +OP4 E01C1F 0 +OP4 E01C20 0 +OP4 E01C21 0 +OP4 E01C22 0 +OP4 E01C23 0 +OP4 E01C24 0 +OP4 E01C25 0 +OP4 E01C26 0 +OP4 E01C27 0 +OP4 E01C28 0 +OP4 E01C29 0 +OP4 E01C2A 0 +OP4 E01C2B 0 +OP4 E01C2C 0 +OP4 E01C2D 0 +OP4 E01C2E 0 +OP4 E01C2F 0 +OP4 E01C30 0 +OP4 E01C31 0 +OP4 E01C32 0 +OP4 E01C33 0 +OP4 E01C34 0 +OP4 E01C35 0 +OP4 E01C36 0 +OP4 E01C37 0 +OP4 E01C38 0 +OP4 E01C39 0 +OP4 E01C3A 0 +OP4 E01C3B 0 +OP4 E01C3C 0 +OP4 E01C3D 0 +OP4 E01C3E 0 +OP4 E01C3F 0 +OP4 E01C40 0 +OP4 E01C41 0 +OP4 E01C42 0 +OP4 E01C43 0 +OP4 E01C44 0 +OP4 E01C45 0 +OP4 E01C46 0 +OP4 E01C47 0 +OP4 E01C48 0 +OP4 E01C49 0 +OP4 E01C4A 0 +OP4 E01C4B 0 +OP4 E01C4C 0 +OP4 E01C4D 0 +OP4 E01C4E 0 +OP4 E01C4F 0 +OP4 E01C50 0 +OP4 E01C51 0 +OP4 E01C52 0 +OP4 E01C53 0 +OP4 E01C54 0 +OP4 E01C55 0 +OP4 E01C56 0 +OP4 E01C57 0 +OP4 E01C58 0 +OP4 E01C59 0 +OP4 E01C5A 0 +OP4 E01C5B 0 +OP4 E01C5C 0 +OP4 E01C5D 0 +OP4 E01C5E 0 +OP4 E01C5F 0 +OP4 E01C60 0 +OP4 E01C61 0 +OP4 E01C62 0 +OP4 E01C63 0 +OP4 E01C64 0 +OP4 E01C65 0 +OP4 E01C66 0 +OP4 E01C67 0 +OP4 E01C68 0 +OP4 E01C69 0 +OP4 E01C6A 0 +OP4 E01C6B 0 +OP4 E01C6C 0 +OP4 E01C6D 0 +OP4 E01C6E 0 +OP4 E01C6F 0 +OP4 E01C70 0 +OP4 E01C71 0 +OP4 E01C72 0 +OP4 E01C73 0 +OP4 E01C74 0 +OP4 E01C75 0 +OP4 E01C76 0 +OP4 E01C77 0 +OP4 E01C78 0 +OP4 E01C79 0 +OP4 E01C7A 0 +OP4 E01C7B 0 +OP4 E01C7C 0 +OP4 E01C7D 0 +OP4 E01C7E 0 +OP4 E01C7F 0 +OP4 E01C80 0 +OP4 E01C81 0 +OP4 E01C82 0 +OP4 E01C83 0 +OP4 E01C84 0 +OP4 E01C85 0 +OP4 E01C86 0 +OP4 E01C87 0 +OP4 E01C88 0 +OP4 E01C89 0 +OP4 E01C8A 0 +OP4 E01C8B 0 +OP4 E01C8C 0 +OP4 E01C8D 0 +OP4 E01C8E 0 +OP4 E01C8F 0 +OP4 E01C90 0 +OP4 E01C91 0 +OP4 E01C92 0 +OP4 E01C93 0 +OP4 E01C94 0 +OP4 E01C95 0 +OP4 E01C96 0 +OP4 E01C97 0 +OP4 E01C98 0 +OP4 E01C99 0 +OP4 E01C9A 0 +OP4 E01C9B 0 +OP4 E01C9C 0 +OP4 E01C9D 0 +OP4 E01C9E 0 +OP4 E01C9F 0 +OP4 E01CA0 0 +OP4 E01CA1 0 +OP4 E01CA2 0 +OP4 E01CA3 0 +OP4 E01CA4 0 +OP4 E01CA5 0 +OP4 E01CA6 0 +OP4 E01CA7 0 +OP4 E01CA8 0 +OP4 E01CA9 0 +OP4 E01CAA 0 +OP4 E01CAB 0 +OP4 E01CAC 0 +OP4 E01CAD 0 +OP4 E01CAE 0 +OP4 E01CAF 0 +OP4 E01CB0 0 +OP4 E01CB1 0 +OP4 E01CB2 0 +OP4 E01CB3 0 +OP4 E01CB4 0 +OP4 E01CB5 0 +OP4 E01CB6 0 +OP4 E01CB7 0 +OP4 E01CB8 0 +OP4 E01CB9 0 +OP4 E01CBA 0 +OP4 E01CBB 0 +OP4 E01CBC 0 +OP4 E01CBD 0 +OP4 E01CBE 0 +OP4 E01CBF 0 +OP4 E01CC0 0 +OP4 E01CC1 0 +OP4 E01CC2 0 +OP4 E01CC3 0 +OP4 E01CC4 0 +OP4 E01CC5 0 +OP4 E01CC6 0 +OP4 E01CC7 0 +OP4 E01CC8 0 +OP4 E01CC9 0 +OP4 E01CCA 0 +OP4 E01CCB 0 +OP4 E01CCC 0 +OP4 E01CCD 0 +OP4 E01CCE 0 +OP4 E01CCF 0 +OP4 E01CD0 0 +OP4 E01CD1 0 +OP4 E01CD2 0 +OP4 E01CD3 0 +OP4 E01CD4 0 +OP4 E01CD5 0 +OP4 E01CD6 0 +OP4 E01CD7 0 +OP4 E01CD8 0 +OP4 E01CD9 0 +OP4 E01CDA 0 +OP4 E01CDB 0 +OP4 E01CDC 0 +OP4 E01CDD 0 +OP4 E01CDE 0 +OP4 E01CDF 0 +OP4 E01CE0 0 +OP4 E01CE1 0 +OP4 E01CE2 0 +OP4 E01CE3 0 +OP4 E01CE4 0 +OP4 E01CE5 0 +OP4 E01CE6 0 +OP4 E01CE7 0 +OP4 E01CE8 0 +OP4 E01CE9 0 +OP4 E01CEA 0 +OP4 E01CEB 0 +OP4 E01CEC 0 +OP4 E01CED 0 +OP4 E01CEE 0 +OP4 E01CEF 0 +OP4 E01CF0 0 +OP4 E01CF1 0 +OP4 E01CF2 0 +OP4 E01CF3 0 +OP4 E01CF4 0 +OP4 E01CF5 0 +OP4 E01CF6 0 +OP4 E01CF7 0 +OP4 E01CF8 0 +OP4 E01CF9 0 +OP4 E01CFA 0 +OP4 E01CFB 0 +OP4 E01CFC 0 +OP4 E01CFD 0 +OP4 E01CFE 0 +OP4 E01CFF 0 +OP4 E01D00 0 +OP4 E01D01 0 +OP4 E01D02 0 +OP4 E01D03 0 +OP4 E01D04 0 +OP4 E01D05 0 +OP4 E01D06 0 +OP4 E01D07 0 +OP4 E01D08 0 +OP4 E01D09 0 +OP4 E01D0A 0 +OP4 E01D0B 0 +OP4 E01D0C 0 +OP4 E01D0D 0 +OP4 E01D0E 0 +OP4 E01D0F 0 +OP4 E01D10 0 +OP4 E01D11 0 +OP4 E01D12 0 +OP4 E01D13 0 +OP4 E01D14 0 +OP4 E01D15 0 +OP4 E01D16 0 +OP4 E01D17 0 +OP4 E01D18 0 +OP4 E01D19 0 +OP4 E01D1A 0 +OP4 E01D1B 0 +OP4 E01D1C 0 +OP4 E01D1D 0 +OP4 E01D1E 0 +OP4 E01D1F 0 +OP4 E01D20 0 +OP4 E01D21 0 +OP4 E01D22 0 +OP4 E01D23 0 +OP4 E01D24 0 +OP4 E01D25 0 +OP4 E01D26 0 +OP4 E01D27 0 +OP4 E01D28 0 +OP4 E01D29 0 +OP4 E01D2A 0 +OP4 E01D2B 0 +OP4 E01D2C 0 +OP4 E01D2D 0 +OP4 E01D2E 0 +OP4 E01D2F 0 +OP4 E01D30 0 +OP4 E01D31 0 +OP4 E01D32 0 +OP4 E01D33 0 +OP4 E01D34 0 +OP4 E01D35 0 +OP4 E01D36 0 +OP4 E01D37 0 +OP4 E01D38 0 +OP4 E01D39 0 +OP4 E01D3A 0 +OP4 E01D3B 0 +OP4 E01D3C 0 +OP4 E01D3D 0 +OP4 E01D3E 0 +OP4 E01D3F 0 +OP4 E01D40 0 +OP4 E01D41 0 +OP4 E01D42 0 +OP4 E01D43 0 +OP4 E01D44 0 +OP4 E01D45 0 +OP4 E01D46 0 +OP4 E01D47 0 +OP4 E01D48 0 +OP4 E01D49 0 +OP4 E01D4A 0 +OP4 E01D4B 0 +OP4 E01D4C 0 +OP4 E01D4D 0 +OP4 E01D4E 0 +OP4 E01D4F 0 +OP4 E01D50 0 +OP4 E01D51 0 +OP4 E01D52 0 +OP4 E01D53 0 +OP4 E01D54 0 +OP4 E01D55 0 +OP4 E01D56 0 +OP4 E01D57 0 +OP4 E01D58 0 +OP4 E01D59 0 +OP4 E01D5A 0 +OP4 E01D5B 0 +OP4 E01D5C 0 +OP4 E01D5D 0 +OP4 E01D5E 0 +OP4 E01D5F 0 +OP4 E01D60 0 +OP4 E01D61 0 +OP4 E01D62 0 +OP4 E01D63 0 +OP4 E01D64 0 +OP4 E01D65 0 +OP4 E01D66 0 +OP4 E01D67 0 +OP4 E01D68 0 +OP4 E01D69 0 +OP4 E01D6A 0 +OP4 E01D6B 0 +OP4 E01D6C 0 +OP4 E01D6D 0 +OP4 E01D6E 0 +OP4 E01D6F 0 +OP4 E01D70 0 +OP4 E01D71 0 +OP4 E01D72 0 +OP4 E01D73 0 +OP4 E01D74 0 +OP4 E01D75 0 +OP4 E01D76 0 +OP4 E01D77 0 +OP4 E01D78 0 +OP4 E01D79 0 +OP4 E01D7A 0 +OP4 E01D7B 0 +OP4 E01D7C 0 +OP4 E01D7D 0 +OP4 E01D7E 0 +OP4 E01D7F 0 +OP4 E01D80 0 +OP4 E01D81 0 +OP4 E01D82 0 +OP4 E01D83 0 +OP4 E01D84 0 +OP4 E01D85 0 +OP4 E01D86 0 +OP4 E01D87 0 +OP4 E01D88 0 +OP4 E01D89 0 +OP4 E01D8A 0 +OP4 E01D8B 0 +OP4 E01D8C 0 +OP4 E01D8D 0 +OP4 E01D8E 0 +OP4 E01D8F 0 +OP4 E01D90 0 +OP4 E01D91 0 +OP4 E01D92 0 +OP4 E01D93 0 +OP4 E01D94 0 +OP4 E01D95 0 +OP4 E01D96 0 +OP4 E01D97 0 +OP4 E01D98 0 +OP4 E01D99 0 +OP4 E01D9A 0 +OP4 E01D9B 0 +OP4 E01D9C 0 +OP4 E01D9D 0 +OP4 E01D9E 0 +OP4 E01D9F 0 +OP4 E01DA0 0 +OP4 E01DA1 0 +OP4 E01DA2 0 +OP4 E01DA3 0 +OP4 E01DA4 0 +OP4 E01DA5 0 +OP4 E01DA6 0 +OP4 E01DA7 0 +OP4 E01DA8 0 +OP4 E01DA9 0 +OP4 E01DAA 0 +OP4 E01DAB 0 +OP4 E01DAC 0 +OP4 E01DAD 0 +OP4 E01DAE 0 +OP4 E01DAF 0 +OP4 E01DB0 0 +OP4 E01DB1 0 +OP4 E01DB2 0 +OP4 E01DB3 0 +OP4 E01DB4 0 +OP4 E01DB5 0 +OP4 E01DB6 0 +OP4 E01DB7 0 +OP4 E01DB8 0 +OP4 E01DB9 0 +OP4 E01DBA 0 +OP4 E01DBB 0 +OP4 E01DBC 0 +OP4 E01DBD 0 +OP4 E01DBE 0 +OP4 E01DBF 0 +OP4 E01DC0 0 +OP4 E01DC1 0 +OP4 E01DC2 0 +OP4 E01DC3 0 +OP4 E01DC4 0 +OP4 E01DC5 0 +OP4 E01DC6 0 +OP4 E01DC7 0 +OP4 E01DC8 0 +OP4 E01DC9 0 +OP4 E01DCA 0 +OP4 E01DCB 0 +OP4 E01DCC 0 +OP4 E01DCD 0 +OP4 E01DCE 0 +OP4 E01DCF 0 +OP4 E01DD0 0 +OP4 E01DD1 0 +OP4 E01DD2 0 +OP4 E01DD3 0 +OP4 E01DD4 0 +OP4 E01DD5 0 +OP4 E01DD6 0 +OP4 E01DD7 0 +OP4 E01DD8 0 +OP4 E01DD9 0 +OP4 E01DDA 0 +OP4 E01DDB 0 +OP4 E01DDC 0 +OP4 E01DDD 0 +OP4 E01DDE 0 +OP4 E01DDF 0 +OP4 E01DE0 0 +OP4 E01DE1 0 +OP4 E01DE2 0 +OP4 E01DE3 0 +OP4 E01DE4 0 +OP4 E01DE5 0 +OP4 E01DE6 0 +OP4 E01DE7 0 +OP4 E01DE8 0 +OP4 E01DE9 0 +OP4 E01DEA 0 +OP4 E01DEB 0 +OP4 E01DEC 0 +OP4 E01DED 0 +OP4 E01DEE 0 +OP4 E01DEF 0 +OP4 E01DF0 0 +OP4 E01DF1 0 +OP4 E01DF2 0 +OP4 E01DF3 0 +OP4 E01DF4 0 +OP4 E01DF5 0 +OP4 E01DF6 0 +OP4 E01DF7 0 +OP4 E01DF8 0 +OP4 E01DF9 0 +OP4 E01DFA 0 +OP4 E01DFB 0 +OP4 E01DFC 0 +OP4 E01DFD 0 +OP4 E01DFE 0 +OP4 E01DFF 0 +OP4 E01E00 0 +OP4 E01E01 0 +OP4 E01E02 0 +OP4 E01E03 0 +OP4 E01E04 0 +OP4 E01E05 0 +OP4 E01E06 0 +OP4 E01E07 0 +OP4 E01E08 0 +OP4 E01E09 0 +OP4 E01E0A 0 +OP4 E01E0B 0 +OP4 E01E0C 0 +OP4 E01E0D 0 +OP4 E01E0E 0 +OP4 E01E0F 0 +OP4 E01E10 0 +OP4 E01E11 0 +OP4 E01E12 0 +OP4 E01E13 0 +OP4 E01E14 0 +OP4 E01E15 0 +OP4 E01E16 0 +OP4 E01E17 0 +OP4 E01E18 0 +OP4 E01E19 0 +OP4 E01E1A 0 +OP4 E01E1B 0 +OP4 E01E1C 0 +OP4 E01E1D 0 +OP4 E01E1E 0 +OP4 E01E1F 0 +OP4 E01E20 0 +OP4 E01E21 0 +OP4 E01E22 0 +OP4 E01E23 0 +OP4 E01E24 0 +OP4 E01E25 0 +OP4 E01E26 0 +OP4 E01E27 0 +OP4 E01E28 0 +OP4 E01E29 0 +OP4 E01E2A 0 +OP4 E01E2B 0 +OP4 E01E2C 0 +OP4 E01E2D 0 +OP4 E01E2E 0 +OP4 E01E2F 0 +OP4 E01E30 0 +OP4 E01E31 0 +OP4 E01E32 0 +OP4 E01E33 0 +OP4 E01E34 0 +OP4 E01E35 0 +OP4 E01E36 0 +OP4 E01E37 0 +OP4 E01E38 0 +OP4 E01E39 0 +OP4 E01E3A 0 +OP4 E01E3B 0 +OP4 E01E3C 0 +OP4 E01E3D 0 +OP4 E01E3E 0 +OP4 E01E3F 0 +OP4 E01E40 0 +OP4 E01E41 0 +OP4 E01E42 0 +OP4 E01E43 0 +OP4 E01E44 0 +OP4 E01E45 0 +OP4 E01E46 0 +OP4 E01E47 0 +OP4 E01E48 0 +OP4 E01E49 0 +OP4 E01E4A 0 +OP4 E01E4B 0 +OP4 E01E4C 0 +OP4 E01E4D 0 +OP4 E01E4E 0 +OP4 E01E4F 0 +OP4 E01E50 0 +OP4 E01E51 0 +OP4 E01E52 0 +OP4 E01E53 0 +OP4 E01E54 0 +OP4 E01E55 0 +OP4 E01E56 0 +OP4 E01E57 0 +OP4 E01E58 0 +OP4 E01E59 0 +OP4 E01E5A 0 +OP4 E01E5B 0 +OP4 E01E5C 0 +OP4 E01E5D 0 +OP4 E01E5E 0 +OP4 E01E5F 0 +OP4 E01E60 0 +OP4 E01E61 0 +OP4 E01E62 0 +OP4 E01E63 0 +OP4 E01E64 0 +OP4 E01E65 0 +OP4 E01E66 0 +OP4 E01E67 0 +OP4 E01E68 0 +OP4 E01E69 0 +OP4 E01E6A 0 +OP4 E01E6B 0 +OP4 E01E6C 0 +OP4 E01E6D 0 +OP4 E01E6E 0 +OP4 E01E6F 0 +OP4 E01E70 0 +OP4 E01E71 0 +OP4 E01E72 0 +OP4 E01E73 0 +OP4 E01E74 0 +OP4 E01E75 0 +OP4 E01E76 0 +OP4 E01E77 0 +OP4 E01E78 0 +OP4 E01E79 0 +OP4 E01E7A 0 +OP4 E01E7B 0 +OP4 E01E7C 0 +OP4 E01E7D 0 +OP4 E01E7E 0 +OP4 E01E7F 0 +OP4 E01E80 0 +OP4 E01E81 0 +OP4 E01E82 0 +OP4 E01E83 0 +OP4 E01E84 0 +OP4 E01E85 0 +OP4 E01E86 0 +OP4 E01E87 0 +OP4 E01E88 0 +OP4 E01E89 0 +OP4 E01E8A 0 +OP4 E01E8B 0 +OP4 E01E8C 0 +OP4 E01E8D 0 +OP4 E01E8E 0 +OP4 E01E8F 0 +OP4 E01E90 0 +OP4 E01E91 0 +OP4 E01E92 0 +OP4 E01E93 0 +OP4 E01E94 0 +OP4 E01E95 0 +OP4 E01E96 0 +OP4 E01E97 0 +OP4 E01E98 0 +OP4 E01E99 0 +OP4 E01E9A 0 +OP4 E01E9B 0 +OP4 E01E9C 0 +OP4 E01E9D 0 +OP4 E01E9E 0 +OP4 E01E9F 0 +OP4 E01EA0 0 +OP4 E01EA1 0 +OP4 E01EA2 0 +OP4 E01EA3 0 +OP4 E01EA4 0 +OP4 E01EA5 0 +OP4 E01EA6 0 +OP4 E01EA7 0 +OP4 E01EA8 0 +OP4 E01EA9 0 +OP4 E01EAA 0 +OP4 E01EAB 0 +OP4 E01EAC 0 +OP4 E01EAD 0 +OP4 E01EAE 0 +OP4 E01EAF 0 +OP4 E01EB0 0 +OP4 E01EB1 0 +OP4 E01EB2 0 +OP4 E01EB3 0 +OP4 E01EB4 0 +OP4 E01EB5 0 +OP4 E01EB6 0 +OP4 E01EB7 0 +OP4 E01EB8 0 +OP4 E01EB9 0 +OP4 E01EBA 0 +OP4 E01EBB 0 +OP4 E01EBC 0 +OP4 E01EBD 0 +OP4 E01EBE 0 +OP4 E01EBF 0 +OP4 E01EC0 0 +OP4 E01EC1 0 +OP4 E01EC2 0 +OP4 E01EC3 0 +OP4 E01EC4 0 +OP4 E01EC5 0 +OP4 E01EC6 0 +OP4 E01EC7 0 +OP4 E01EC8 0 +OP4 E01EC9 0 +OP4 E01ECA 0 +OP4 E01ECB 0 +OP4 E01ECC 0 +OP4 E01ECD 0 +OP4 E01ECE 0 +OP4 E01ECF 0 +OP4 E01ED0 0 +OP4 E01ED1 0 +OP4 E01ED2 0 +OP4 E01ED3 0 +OP4 E01ED4 0 +OP4 E01ED5 0 +OP4 E01ED6 0 +OP4 E01ED7 0 +OP4 E01ED8 0 +OP4 E01ED9 0 +OP4 E01EDA 0 +OP4 E01EDB 0 +OP4 E01EDC 0 +OP4 E01EDD 0 +OP4 E01EDE 0 +OP4 E01EDF 0 +OP4 E01EE0 0 +OP4 E01EE1 0 +OP4 E01EE2 0 +OP4 E01EE3 0 +OP4 E01EE4 0 +OP4 E01EE5 0 +OP4 E01EE6 0 +OP4 E01EE7 0 +OP4 E01EE8 0 +OP4 E01EE9 0 +OP4 E01EEA 0 +OP4 E01EEB 0 +OP4 E01EEC 0 +OP4 E01EED 0 +OP4 E01EEE 0 +OP4 E01EEF 0 +OP4 E01EF0 0 +OP4 E01EF1 0 +OP4 E01EF2 0 +OP4 E01EF3 0 +OP4 E01EF4 0 +OP4 E01EF5 0 +OP4 E01EF6 0 +OP4 E01EF7 0 +OP4 E01EF8 0 +OP4 E01EF9 0 +OP4 E01EFA 0 +OP4 E01EFB 0 +OP4 E01EFC 0 +OP4 E01EFD 0 +OP4 E01EFE 0 +OP4 E01EFF 0 +OP4 E01F00 0 +OP4 E01F01 0 +OP4 E01F02 0 +OP4 E01F03 0 +OP4 E01F04 0 +OP4 E01F05 0 +OP4 E01F06 0 +OP4 E01F07 0 +OP4 E01F08 0 +OP4 E01F09 0 +OP4 E01F0A 0 +OP4 E01F0B 0 +OP4 E01F0C 0 +OP4 E01F0D 0 +OP4 E01F0E 0 +OP4 E01F0F 0 +OP4 E01F10 0 +OP4 E01F11 0 +OP4 E01F12 0 +OP4 E01F13 0 +OP4 E01F14 0 +OP4 E01F15 0 +OP4 E01F16 0 +OP4 E01F17 0 +OP4 E01F18 0 +OP4 E01F19 0 +OP4 E01F1A 0 +OP4 E01F1B 0 +OP4 E01F1C 0 +OP4 E01F1D 0 +OP4 E01F1E 0 +OP4 E01F1F 0 +OP4 E01F20 0 +OP4 E01F21 0 +OP4 E01F22 0 +OP4 E01F23 0 +OP4 E01F24 0 +OP4 E01F25 0 +OP4 E01F26 0 +OP4 E01F27 0 +OP4 E01F28 0 +OP4 E01F29 0 +OP4 E01F2A 0 +OP4 E01F2B 0 +OP4 E01F2C 0 +OP4 E01F2D 0 +OP4 E01F2E 0 +OP4 E01F2F 0 +OP4 E01F30 0 +OP4 E01F31 0 +OP4 E01F32 0 +OP4 E01F33 0 +OP4 E01F34 0 +OP4 E01F35 0 +OP4 E01F36 0 +OP4 E01F37 0 +OP4 E01F38 0 +OP4 E01F39 0 +OP4 E01F3A 0 +OP4 E01F3B 0 +OP4 E01F3C 0 +OP4 E01F3D 0 +OP4 E01F3E 0 +OP4 E01F3F 0 +OP4 E01F40 0 +OP4 E01F41 0 +OP4 E01F42 0 +OP4 E01F43 0 +OP4 E01F44 0 +OP4 E01F45 0 +OP4 E01F46 0 +OP4 E01F47 0 +OP4 E01F48 0 +OP4 E01F49 0 +OP4 E01F4A 0 +OP4 E01F4B 0 +OP4 E01F4C 0 +OP4 E01F4D 0 +OP4 E01F4E 0 +OP4 E01F4F 0 +OP4 E01F50 0 +OP4 E01F51 0 +OP4 E01F52 0 +OP4 E01F53 0 +OP4 E01F54 0 +OP4 E01F55 0 +OP4 E01F56 0 +OP4 E01F57 0 +OP4 E01F58 0 +OP4 E01F59 0 +OP4 E01F5A 0 +OP4 E01F5B 0 +OP4 E01F5C 0 +OP4 E01F5D 0 +OP4 E01F5E 0 +OP4 E01F5F 0 +OP4 E01F60 0 +OP4 E01F61 0 +OP4 E01F62 0 +OP4 E01F63 0 +OP4 E01F64 0 +OP4 E01F65 0 +OP4 E01F66 0 +OP4 E01F67 0 +OP4 E01F68 0 +OP4 E01F69 0 +OP4 E01F6A 0 +OP4 E01F6B 0 +OP4 E01F6C 0 +OP4 E01F6D 0 +OP4 E01F6E 0 +OP4 E01F6F 0 +OP4 E01F70 0 +OP4 E01F71 0 +OP4 E01F72 0 +OP4 E01F73 0 +OP4 E01F74 0 +OP4 E01F75 0 +OP4 E01F76 0 +OP4 E01F77 0 +OP4 E01F78 0 +OP4 E01F79 0 +OP4 E01F7A 0 +OP4 E01F7B 0 +OP4 E01F7C 0 +OP4 E01F7D 0 +OP4 E01F7E 0 +OP4 E01F7F 0 +OP4 E01F80 0 +OP4 E01F81 0 +OP4 E01F82 0 +OP4 E01F83 0 +OP4 E01F84 0 +OP4 E01F85 0 +OP4 E01F86 0 +OP4 E01F87 0 +OP4 E01F88 0 +OP4 E01F89 0 +OP4 E01F8A 0 +OP4 E01F8B 0 +OP4 E01F8C 0 +OP4 E01F8D 0 +OP4 E01F8E 0 +OP4 E01F8F 0 +OP4 E01F90 0 +OP4 E01F91 0 +OP4 E01F92 0 +OP4 E01F93 0 +OP4 E01F94 0 +OP4 E01F95 0 +OP4 E01F96 0 +OP4 E01F97 0 +OP4 E01F98 0 +OP4 E01F99 0 +OP4 E01F9A 0 +OP4 E01F9B 0 +OP4 E01F9C 0 +OP4 E01F9D 0 +OP4 E01F9E 0 +OP4 E01F9F 0 +OP4 E01FA0 0 +OP4 E01FA1 0 +OP4 E01FA2 0 +OP4 E01FA3 0 +OP4 E01FA4 0 +OP4 E01FA5 0 +OP4 E01FA6 0 +OP4 E01FA7 0 +OP4 E01FA8 0 +OP4 E01FA9 0 +OP4 E01FAA 0 +OP4 E01FAB 0 +OP4 E01FAC 0 +OP4 E01FAD 0 +OP4 E01FAE 0 +OP4 E01FAF 0 +OP4 E01FB0 0 +OP4 E01FB1 0 +OP4 E01FB2 0 +OP4 E01FB3 0 +OP4 E01FB4 0 +OP4 E01FB5 0 +OP4 E01FB6 0 +OP4 E01FB7 0 +OP4 E01FB8 0 +OP4 E01FB9 0 +OP4 E01FBA 0 +OP4 E01FBB 0 +OP4 E01FBC 0 +OP4 E01FBD 0 +OP4 E01FBE 0 +OP4 E01FBF 0 +OP4 E01FC0 0 +OP4 E01FC1 0 +OP4 E01FC2 0 +OP4 E01FC3 0 +OP4 E01FC4 0 +OP4 E01FC5 0 +OP4 E01FC6 0 +OP4 E01FC7 0 +OP4 E01FC8 0 +OP4 E01FC9 0 +OP4 E01FCA 0 +OP4 E01FCB 0 +OP4 E01FCC 0 +OP4 E01FCD 0 +OP4 E01FCE 0 +OP4 E01FCF 0 +OP4 E01FD0 0 +OP4 E01FD1 0 +OP4 E01FD2 0 +OP4 E01FD3 0 +OP4 E01FD4 0 +OP4 E01FD5 0 +OP4 E01FD6 0 +OP4 E01FD7 0 +OP4 E01FD8 0 +OP4 E01FD9 0 +OP4 E01FDA 0 +OP4 E01FDB 0 +OP4 E01FDC 0 +OP4 E01FDD 0 +OP4 E01FDE 0 +OP4 E01FDF 0 +OP4 E01FE0 0 +OP4 E01FE1 0 +OP4 E01FE2 0 +OP4 E01FE3 0 +OP4 E01FE4 0 +OP4 E01FE5 0 +OP4 E01FE6 0 +OP4 E01FE7 0 +OP4 E01FE8 0 +OP4 E01FE9 0 +OP4 E01FEA 0 +OP4 E01FEB 0 +OP4 E01FEC 0 +OP4 E01FED 0 +OP4 E01FEE 0 +OP4 E01FEF 0 +OP4 E01FF0 0 +OP4 E01FF1 0 +OP4 E01FF2 0 +OP4 E01FF3 0 +OP4 E01FF4 0 +OP4 E01FF5 0 +OP4 E01FF6 0 +OP4 E01FF7 0 +OP4 E01FF8 0 +OP4 E01FF9 0 +OP4 E01FFA 0 +OP4 E01FFB 0 +OP4 E01FFC 0 +OP4 E01FFD 0 +OP4 E01FFE 0 +OP4 E01FFF 0 +OP4 E02000 0 +OP4 E02001 0 +OP4 E02002 0 +OP4 E02003 0 +OP4 E02004 0 +OP4 E02005 0 +OP4 E02006 0 +OP4 E02007 0 +OP4 E02008 0 +OP4 E02009 0 +OP4 E0200A 0 +OP4 E0200B 0 +OP4 E0200C 0 +OP4 E0200D 0 +OP4 E0200E 0 +OP4 E0200F 0 +OP4 E02010 0 +OP4 E02011 0 +OP4 E02012 0 +OP4 E02013 0 +OP4 E02014 0 +OP4 E02015 0 +OP4 E02016 0 +OP4 E02017 0 +OP4 E02018 0 +OP4 E02019 0 +OP4 E0201A 0 +OP4 E0201B 0 +OP4 E0201C 0 +OP4 E0201D 0 +OP4 E0201E 0 +OP4 E0201F 0 +OP4 E02020 0 +OP4 E02021 0 +OP4 E02022 0 +OP4 E02023 0 +OP4 E02024 0 +OP4 E02025 0 +OP4 E02026 0 +OP4 E02027 0 +OP4 E02028 0 +OP4 E02029 0 +OP4 E0202A 0 +OP4 E0202B 0 +OP4 E0202C 0 +OP4 E0202D 0 +OP4 E0202E 0 +OP4 E0202F 0 +OP4 E02030 0 +OP4 E02031 0 +OP4 E02032 0 +OP4 E02033 0 +OP4 E02034 0 +OP4 E02035 0 +OP4 E02036 0 +OP4 E02037 0 +OP4 E02038 0 +OP4 E02039 0 +OP4 E0203A 0 +OP4 E0203B 0 +OP4 E0203C 0 +OP4 E0203D 0 +OP4 E0203E 0 +OP4 E0203F 0 +OP4 E02040 0 +OP4 E02041 0 +OP4 E02042 0 +OP4 E02043 0 +OP4 E02044 0 +OP4 E02045 0 +OP4 E02046 0 +OP4 E02047 0 +OP4 E02048 0 +OP4 E02049 0 +OP4 E0204A 0 +OP4 E0204B 0 +OP4 E0204C 0 +OP4 E0204D 0 +OP4 E0204E 0 +OP4 E0204F 0 +OP4 E02050 0 +OP4 E02051 0 +OP4 E02052 0 +OP4 E02053 0 +OP4 E02054 0 +OP4 E02055 0 +OP4 E02056 0 +OP4 E02057 0 +OP4 E02058 0 +OP4 E02059 0 +OP4 E0205A 0 +OP4 E0205B 0 +OP4 E0205C 0 +OP4 E0205D 0 +OP4 E0205E 0 +OP4 E0205F 0 +OP4 E02060 0 +OP4 E02061 0 +OP4 E02062 0 +OP4 E02063 0 +OP4 E02064 0 +OP4 E02065 0 +OP4 E02066 0 +OP4 E02067 0 +OP4 E02068 0 +OP4 E02069 0 +OP4 E0206A 0 +OP4 E0206B 0 +OP4 E0206C 0 +OP4 E0206D 0 +OP4 E0206E 0 +OP4 E0206F 0 +OP4 E02070 0 +OP4 E02071 0 +OP4 E02072 0 +OP4 E02073 0 +OP4 E02074 0 +OP4 E02075 0 +OP4 E02076 0 +OP4 E02077 0 +OP4 E02078 0 +OP4 E02079 0 +OP4 E0207A 0 +OP4 E0207B 0 +OP4 E0207C 0 +OP4 E0207D 0 +OP4 E0207E 0 +OP4 E0207F 0 +OP4 E02080 0 +OP4 E02081 0 +OP4 E02082 0 +OP4 E02083 0 +OP4 E02084 0 +OP4 E02085 0 +OP4 E02086 0 +OP4 E02087 0 +OP4 E02088 0 +OP4 E02089 0 +OP4 E0208A 0 +OP4 E0208B 0 +OP4 E0208C 0 +OP4 E0208D 0 +OP4 E0208E 0 +OP4 E0208F 0 +OP4 E02090 0 +OP4 E02091 0 +OP4 E02092 0 +OP4 E02093 0 +OP4 E02094 0 +OP4 E02095 0 +OP4 E02096 0 +OP4 E02097 0 +OP4 E02098 0 +OP4 E02099 0 +OP4 E0209A 0 +OP4 E0209B 0 +OP4 E0209C 0 +OP4 E0209D 0 +OP4 E0209E 0 +OP4 E0209F 0 +OP4 E020A0 0 +OP4 E020A1 0 +OP4 E020A2 0 +OP4 E020A3 0 +OP4 E020A4 0 +OP4 E020A5 0 +OP4 E020A6 0 +OP4 E020A7 0 +OP4 E020A8 0 +OP4 E020A9 0 +OP4 E020AA 0 +OP4 E020AB 0 +OP4 E020AC 0 +OP4 E020AD 0 +OP4 E020AE 0 +OP4 E020AF 0 +OP4 E020B0 0 +OP4 E020B1 0 +OP4 E020B2 0 +OP4 E020B3 0 +OP4 E020B4 0 +OP4 E020B5 0 +OP4 E020B6 0 +OP4 E020B7 0 +OP4 E020B8 0 +OP4 E020B9 0 +OP4 E020BA 0 +OP4 E020BB 0 +OP4 E020BC 0 +OP4 E020BD 0 +OP4 E020BE 0 +OP4 E020BF 0 +OP4 E020C0 0 +OP4 E020C1 0 +OP4 E020C2 0 +OP4 E020C3 0 +OP4 E020C4 0 +OP4 E020C5 0 +OP4 E020C6 0 +OP4 E020C7 0 +OP4 E020C8 0 +OP4 E020C9 0 +OP4 E020CA 0 +OP4 E020CB 0 +OP4 E020CC 0 +OP4 E020CD 0 +OP4 E020CE 0 +OP4 E020CF 0 +OP4 E020D0 0 +OP4 E020D1 0 +OP4 E020D2 0 +OP4 E020D3 0 +OP4 E020D4 0 +OP4 E020D5 0 +OP4 E020D6 0 +OP4 E020D7 0 +OP4 E020D8 0 +OP4 E020D9 0 +OP4 E020DA 0 +OP4 E020DB 0 +OP4 E020DC 0 +OP4 E020DD 0 +OP4 E020DE 0 +OP4 E020DF 0 +OP4 E020E0 0 +OP4 E020E1 0 +OP4 E020E2 0 +OP4 E020E3 0 +OP4 E020E4 0 +OP4 E020E5 0 +OP4 E020E6 0 +OP4 E020E7 0 +OP4 E020E8 0 +OP4 E020E9 0 +OP4 E020EA 0 +OP4 E020EB 0 +OP4 E020EC 0 +OP4 E020ED 0 +OP4 E020EE 0 +OP4 E020EF 0 +OP4 E020F0 0 +OP4 E020F1 0 +OP4 E020F2 0 +OP4 E020F3 0 +OP4 E020F4 0 +OP4 E020F5 0 +OP4 E020F6 0 +OP4 E020F7 0 +OP4 E020F8 0 +OP4 E020F9 0 +OP4 E020FA 0 +OP4 E020FB 0 +OP4 E020FC 0 +OP4 E020FD 0 +OP4 E020FE 0 +OP4 E020FF 0 +OP4 E02100 0 +OP4 E02101 0 +OP4 E02102 0 +OP4 E02103 0 +OP4 E02104 0 +OP4 E02105 0 +OP4 E02106 0 +OP4 E02107 0 +OP4 E02108 0 +OP4 E02109 0 +OP4 E0210A 0 +OP4 E0210B 0 +OP4 E0210C 0 +OP4 E0210D 0 +OP4 E0210E 0 +OP4 E0210F 0 +OP4 E02110 0 +OP4 E02111 0 +OP4 E02112 0 +OP4 E02113 0 +OP4 E02114 0 +OP4 E02115 0 +OP4 E02116 0 +OP4 E02117 0 +OP4 E02118 0 +OP4 E02119 0 +OP4 E0211A 0 +OP4 E0211B 0 +OP4 E0211C 0 +OP4 E0211D 0 +OP4 E0211E 0 +OP4 E0211F 0 +OP4 E02120 0 +OP4 E02121 0 +OP4 E02122 0 +OP4 E02123 0 +OP4 E02124 0 +OP4 E02125 0 +OP4 E02126 0 +OP4 E02127 0 +OP4 E02128 0 +OP4 E02129 0 +OP4 E0212A 0 +OP4 E0212B 0 +OP4 E0212C 0 +OP4 E0212D 0 +OP4 E0212E 0 +OP4 E0212F 0 +OP4 E02130 0 +OP4 E02131 0 +OP4 E02132 0 +OP4 E02133 0 +OP4 E02134 0 +OP4 E02135 0 +OP4 E02136 0 +OP4 E02137 0 +OP4 E02138 0 +OP4 E02139 0 +OP4 E0213A 0 +OP4 E0213B 0 +OP4 E0213C 0 +OP4 E0213D 0 +OP4 E0213E 0 +OP4 E0213F 0 +OP4 E02140 0 +OP4 E02141 0 +OP4 E02142 0 +OP4 E02143 0 +OP4 E02144 0 +OP4 E02145 0 +OP4 E02146 0 +OP4 E02147 0 +OP4 E02148 0 +OP4 E02149 0 +OP4 E0214A 0 +OP4 E0214B 0 +OP4 E0214C 0 +OP4 E0214D 0 +OP4 E0214E 0 +OP4 E0214F 0 +OP4 E02150 0 +OP4 E02151 0 +OP4 E02152 0 +OP4 E02153 0 +OP4 E02154 0 +OP4 E02155 0 +OP4 E02156 0 +OP4 E02157 0 +OP4 E02158 0 +OP4 E02159 0 +OP4 E0215A 0 +OP4 E0215B 0 +OP4 E0215C 0 +OP4 E0215D 0 +OP4 E0215E 0 +OP4 E0215F 0 +OP4 E02160 0 +OP4 E02161 0 +OP4 E02162 0 +OP4 E02163 0 +OP4 E02164 0 +OP4 E02165 0 +OP4 E02166 0 +OP4 E02167 0 +OP4 E02168 0 +OP4 E02169 0 +OP4 E0216A 0 +OP4 E0216B 0 +OP4 E0216C 0 +OP4 E0216D 0 +OP4 E0216E 0 +OP4 E0216F 0 +OP4 E02170 0 +OP4 E02171 0 +OP4 E02172 0 +OP4 E02173 0 +OP4 E02174 0 +OP4 E02175 0 +OP4 E02176 0 +OP4 E02177 0 +OP4 E02178 0 +OP4 E02179 0 +OP4 E0217A 0 +OP4 E0217B 0 +OP4 E0217C 0 +OP4 E0217D 0 +OP4 E0217E 0 +OP4 E0217F 0 +OP4 E02180 0 +OP4 E02181 0 +OP4 E02182 0 +OP4 E02183 0 +OP4 E02184 0 +OP4 E02185 0 +OP4 E02186 0 +OP4 E02187 0 +OP4 E02188 0 +OP4 E02189 0 +OP4 E0218A 0 +OP4 E0218B 0 +OP4 E0218C 0 +OP4 E0218D 0 +OP4 E0218E 0 +OP4 E0218F 0 +OP4 E02190 0 +OP4 E02191 0 +OP4 E02192 0 +OP4 E02193 0 +OP4 E02194 0 +OP4 E02195 0 +OP4 E02196 0 +OP4 E02197 0 +OP4 E02198 0 +OP4 E02199 0 +OP4 E0219A 0 +OP4 E0219B 0 +OP4 E0219C 0 +OP4 E0219D 0 +OP4 E0219E 0 +OP4 E0219F 0 +OP4 E021A0 0 +OP4 E021A1 0 +OP4 E021A2 0 +OP4 E021A3 0 +OP4 E021A4 0 +OP4 E021A5 0 +OP4 E021A6 0 +OP4 E021A7 0 +OP4 E021A8 0 +OP4 E021A9 0 +OP4 E021AA 0 +OP4 E021AB 0 +OP4 E021AC 0 +OP4 E021AD 0 +OP4 E021AE 0 +OP4 E021AF 0 +OP4 E021B0 0 +OP4 E021B1 0 +OP4 E021B2 0 +OP4 E021B3 0 +OP4 E021B4 0 +OP4 E021B5 0 +OP4 E021B6 0 +OP4 E021B7 0 +OP4 E021B8 0 +OP4 E021B9 0 +OP4 E021BA 0 +OP4 E021BB 0 +OP4 E021BC 0 +OP4 E021BD 0 +OP4 E021BE 0 +OP4 E021BF 0 +OP4 E021C0 0 +OP4 E021C1 0 +OP4 E021C2 0 +OP4 E021C3 0 +OP4 E021C4 0 +OP4 E021C5 0 +OP4 E021C6 0 +OP4 E021C7 0 +OP4 E021C8 0 +OP4 E021C9 0 +OP4 E021CA 0 +OP4 E021CB 0 +OP4 E021CC 0 +OP4 E021CD 0 +OP4 E021CE 0 +OP4 E021CF 0 +OP4 E021D0 0 +OP4 E021D1 0 +OP4 E021D2 0 +OP4 E021D3 0 +OP4 E021D4 0 +OP4 E021D5 0 +OP4 E021D6 0 +OP4 E021D7 0 +OP4 E021D8 0 +OP4 E021D9 0 +OP4 E021DA 0 +OP4 E021DB 0 +OP4 E021DC 0 +OP4 E021DD 0 +OP4 E021DE 0 +OP4 E021DF 0 +OP4 E021E0 0 +OP4 E021E1 0 +OP4 E021E2 0 +OP4 E021E3 0 +OP4 E021E4 0 +OP4 E021E5 0 +OP4 E021E6 0 +OP4 E021E7 0 +OP4 E021E8 0 +OP4 E021E9 0 +OP4 E021EA 0 +OP4 E021EB 0 +OP4 E021EC 0 +OP4 E021ED 0 +OP4 E021EE 0 +OP4 E021EF 0 +OP4 E021F0 0 +OP4 E021F1 0 +OP4 E021F2 0 +OP4 E021F3 0 +OP4 E021F4 0 +OP4 E021F5 0 +OP4 E021F6 0 +OP4 E021F7 0 +OP4 E021F8 0 +OP4 E021F9 0 +OP4 E021FA 0 +OP4 E021FB 0 +OP4 E021FC 0 +OP4 E021FD 0 +OP4 E021FE 0 +OP4 E021FF 0 +OP4 E02200 0 +OP4 E02201 0 +OP4 E02202 0 +OP4 E02203 0 +OP4 E02204 0 +OP4 E02205 0 +OP4 E02206 0 +OP4 E02207 0 +OP4 E02208 0 +OP4 E02209 0 +OP4 E0220A 0 +OP4 E0220B 0 +OP4 E0220C 0 +OP4 E0220D 0 +OP4 E0220E 0 +OP4 E0220F 0 +OP4 E02210 0 +OP4 E02211 0 +OP4 E02212 0 +OP4 E02213 0 +OP4 E02214 0 +OP4 E02215 0 +OP4 E02216 0 +OP4 E02217 0 +OP4 E02218 0 +OP4 E02219 0 +OP4 E0221A 0 +OP4 E0221B 0 +OP4 E0221C 0 +OP4 E0221D 0 +OP4 E0221E 0 +OP4 E0221F 0 +OP4 E02220 0 +OP4 E02221 0 +OP4 E02222 0 +OP4 E02223 0 +OP4 E02224 0 +OP4 E02225 0 +OP4 E02226 0 +OP4 E02227 0 +OP4 E02228 0 +OP4 E02229 0 +OP4 E0222A 0 +OP4 E0222B 0 +OP4 E0222C 0 +OP4 E0222D 0 +OP4 E0222E 0 +OP4 E0222F 0 +OP4 E02230 0 +OP4 E02231 0 +OP4 E02232 0 +OP4 E02233 0 +OP4 E02234 0 +OP4 E02235 0 +OP4 E02236 0 +OP4 E02237 0 +OP4 E02238 0 +OP4 E02239 0 +OP4 E0223A 0 +OP4 E0223B 0 +OP4 E0223C 0 +OP4 E0223D 0 +OP4 E0223E 0 +OP4 E0223F 0 +OP4 E02240 0 +OP4 E02241 0 +OP4 E02242 0 +OP4 E02243 0 +OP4 E02244 0 +OP4 E02245 0 +OP4 E02246 0 +OP4 E02247 0 +OP4 E02248 0 +OP4 E02249 0 +OP4 E0224A 0 +OP4 E0224B 0 +OP4 E0224C 0 +OP4 E0224D 0 +OP4 E0224E 0 +OP4 E0224F 0 +OP4 E02250 0 +OP4 E02251 0 +OP4 E02252 0 +OP4 E02253 0 +OP4 E02254 0 +OP4 E02255 0 +OP4 E02256 0 +OP4 E02257 0 +OP4 E02258 0 +OP4 E02259 0 +OP4 E0225A 0 +OP4 E0225B 0 +OP4 E0225C 0 +OP4 E0225D 0 +OP4 E0225E 0 +OP4 E0225F 0 +OP4 E02260 0 +OP4 E02261 0 +OP4 E02262 0 +OP4 E02263 0 +OP4 E02264 0 +OP4 E02265 0 +OP4 E02266 0 +OP4 E02267 0 +OP4 E02268 0 +OP4 E02269 0 +OP4 E0226A 0 +OP4 E0226B 0 +OP4 E0226C 0 +OP4 E0226D 0 +OP4 E0226E 0 +OP4 E0226F 0 +OP4 E02270 0 +OP4 E02271 0 +OP4 E02272 0 +OP4 E02273 0 +OP4 E02274 0 +OP4 E02275 0 +OP4 E02276 0 +OP4 E02277 0 +OP4 E02278 0 +OP4 E02279 0 +OP4 E0227A 0 +OP4 E0227B 0 +OP4 E0227C 0 +OP4 E0227D 0 +OP4 E0227E 0 +OP4 E0227F 0 +OP4 E02280 0 +OP4 E02281 0 +OP4 E02282 0 +OP4 E02283 0 +OP4 E02284 0 +OP4 E02285 0 +OP4 E02286 0 +OP4 E02287 0 +OP4 E02288 0 +OP4 E02289 0 +OP4 E0228A 0 +OP4 E0228B 0 +OP4 E0228C 0 +OP4 E0228D 0 +OP4 E0228E 0 +OP4 E0228F 0 +OP4 E02290 0 +OP4 E02291 0 +OP4 E02292 0 +OP4 E02293 0 +OP4 E02294 0 +OP4 E02295 0 +OP4 E02296 0 +OP4 E02297 0 +OP4 E02298 0 +OP4 E02299 0 +OP4 E0229A 0 +OP4 E0229B 0 +OP4 E0229C 0 +OP4 E0229D 0 +OP4 E0229E 0 +OP4 E0229F 0 +OP4 E022A0 0 +OP4 E022A1 0 +OP4 E022A2 0 +OP4 E022A3 0 +OP4 E022A4 0 +OP4 E022A5 0 +OP4 E022A6 0 +OP4 E022A7 0 +OP4 E022A8 0 +OP4 E022A9 0 +OP4 E022AA 0 +OP4 E022AB 0 +OP4 E022AC 0 +OP4 E022AD 0 +OP4 E022AE 0 +OP4 E022AF 0 +OP4 E022B0 0 +OP4 E022B1 0 +OP4 E022B2 0 +OP4 E022B3 0 +OP4 E022B4 0 +OP4 E022B5 0 +OP4 E022B6 0 +OP4 E022B7 0 +OP4 E022B8 0 +OP4 E022B9 0 +OP4 E022BA 0 +OP4 E022BB 0 +OP4 E022BC 0 +OP4 E022BD 0 +OP4 E022BE 0 +OP4 E022BF 0 +OP4 E022C0 0 +OP4 E022C1 0 +OP4 E022C2 0 +OP4 E022C3 0 +OP4 E022C4 0 +OP4 E022C5 0 +OP4 E022C6 0 +OP4 E022C7 0 +OP4 E022C8 0 +OP4 E022C9 0 +OP4 E022CA 0 +OP4 E022CB 0 +OP4 E022CC 0 +OP4 E022CD 0 +OP4 E022CE 0 +OP4 E022CF 0 +OP4 E022D0 0 +OP4 E022D1 0 +OP4 E022D2 0 +OP4 E022D3 0 +OP4 E022D4 0 +OP4 E022D5 0 +OP4 E022D6 0 +OP4 E022D7 0 +OP4 E022D8 0 +OP4 E022D9 0 +OP4 E022DA 0 +OP4 E022DB 0 +OP4 E022DC 0 +OP4 E022DD 0 +OP4 E022DE 0 +OP4 E022DF 0 +OP4 E022E0 0 +OP4 E022E1 0 +OP4 E022E2 0 +OP4 E022E3 0 +OP4 E022E4 0 +OP4 E022E5 0 +OP4 E022E6 0 +OP4 E022E7 0 +OP4 E022E8 0 +OP4 E022E9 0 +OP4 E022EA 0 +OP4 E022EB 0 +OP4 E022EC 0 +OP4 E022ED 0 +OP4 E022EE 0 +OP4 E022EF 0 +OP4 E022F0 0 +OP4 E022F1 0 +OP4 E022F2 0 +OP4 E022F3 0 +OP4 E022F4 0 +OP4 E022F5 0 +OP4 E022F6 0 +OP4 E022F7 0 +OP4 E022F8 0 +OP4 E022F9 0 +OP4 E022FA 0 +OP4 E022FB 0 +OP4 E022FC 0 +OP4 E022FD 0 +OP4 E022FE 0 +OP4 E022FF 0 +OP4 E02300 0 +OP4 E02301 0 +OP4 E02302 0 +OP4 E02303 0 +OP4 E02304 0 +OP4 E02305 0 +OP4 E02306 0 +OP4 E02307 0 +OP4 E02308 0 +OP4 E02309 0 +OP4 E0230A 0 +OP4 E0230B 0 +OP4 E0230C 0 +OP4 E0230D 0 +OP4 E0230E 0 +OP4 E0230F 0 +OP4 E02310 0 +OP4 E02311 0 +OP4 E02312 0 +OP4 E02313 0 +OP4 E02314 0 +OP4 E02315 0 +OP4 E02316 0 +OP4 E02317 0 +OP4 E02318 0 +OP4 E02319 0 +OP4 E0231A 0 +OP4 E0231B 0 +OP4 E0231C 0 +OP4 E0231D 0 +OP4 E0231E 0 +OP4 E0231F 0 +OP4 E02320 0 +OP4 E02321 0 +OP4 E02322 0 +OP4 E02323 0 +OP4 E02324 0 +OP4 E02325 0 +OP4 E02326 0 +OP4 E02327 0 +OP4 E02328 0 +OP4 E02329 0 +OP4 E0232A 0 +OP4 E0232B 0 +OP4 E0232C 0 +OP4 E0232D 0 +OP4 E0232E 0 +OP4 E0232F 0 +OP4 E02330 0 +OP4 E02331 0 +OP4 E02332 0 +OP4 E02333 0 +OP4 E02334 0 +OP4 E02335 0 +OP4 E02336 0 +OP4 E02337 0 +OP4 E02338 0 +OP4 E02339 0 +OP4 E0233A 0 +OP4 E0233B 0 +OP4 E0233C 0 +OP4 E0233D 0 +OP4 E0233E 0 +OP4 E0233F 0 +OP4 E02340 0 +OP4 E02341 0 +OP4 E02342 0 +OP4 E02343 0 +OP4 E02344 0 +OP4 E02345 0 +OP4 E02346 0 +OP4 E02347 0 +OP4 E02348 0 +OP4 E02349 0 +OP4 E0234A 0 +OP4 E0234B 0 +OP4 E0234C 0 +OP4 E0234D 0 +OP4 E0234E 0 +OP4 E0234F 0 +OP4 E02350 0 +OP4 E02351 0 +OP4 E02352 0 +OP4 E02353 0 +OP4 E02354 0 +OP4 E02355 0 +OP4 E02356 0 +OP4 E02357 0 +OP4 E02358 0 +OP4 E02359 0 +OP4 E0235A 0 +OP4 E0235B 0 +OP4 E0235C 0 +OP4 E0235D 0 +OP4 E0235E 0 +OP4 E0235F 0 +OP4 E02360 0 +OP4 E02361 0 +OP4 E02362 0 +OP4 E02363 0 +OP4 E02364 0 +OP4 E02365 0 +OP4 E02366 0 +OP4 E02367 0 +OP4 E02368 0 +OP4 E02369 0 +OP4 E0236A 0 +OP4 E0236B 0 +OP4 E0236C 0 +OP4 E0236D 0 +OP4 E0236E 0 +OP4 E0236F 0 +OP4 E02370 0 +OP4 E02371 0 +OP4 E02372 0 +OP4 E02373 0 +OP4 E02374 0 +OP4 E02375 0 +OP4 E02376 0 +OP4 E02377 0 +OP4 E02378 0 +OP4 E02379 0 +OP4 E0237A 0 +OP4 E0237B 0 +OP4 E0237C 0 +OP4 E0237D 0 +OP4 E0237E 0 +OP4 E0237F 0 +OP4 E02380 0 +OP4 E02381 0 +OP4 E02382 0 +OP4 E02383 0 +OP4 E02384 0 +OP4 E02385 0 +OP4 E02386 0 +OP4 E02387 0 +OP4 E02388 0 +OP4 E02389 0 +OP4 E0238A 0 +OP4 E0238B 0 +OP4 E0238C 0 +OP4 E0238D 0 +OP4 E0238E 0 +OP4 E0238F 0 +OP4 E02390 0 +OP4 E02391 0 +OP4 E02392 0 +OP4 E02393 0 +OP4 E02394 0 +OP4 E02395 0 +OP4 E02396 0 +OP4 E02397 0 +OP4 E02398 0 +OP4 E02399 0 +OP4 E0239A 0 +OP4 E0239B 0 +OP4 E0239C 0 +OP4 E0239D 0 +OP4 E0239E 0 +OP4 E0239F 0 +OP4 E023A0 0 +OP4 E023A1 0 +OP4 E023A2 0 +OP4 E023A3 0 +OP4 E023A4 0 +OP4 E023A5 0 +OP4 E023A6 0 +OP4 E023A7 0 +OP4 E023A8 0 +OP4 E023A9 0 +OP4 E023AA 0 +OP4 E023AB 0 +OP4 E023AC 0 +OP4 E023AD 0 +OP4 E023AE 0 +OP4 E023AF 0 +OP4 E023B0 0 +OP4 E023B1 0 +OP4 E023B2 0 +OP4 E023B3 0 +OP4 E023B4 0 +OP4 E023B5 0 +OP4 E023B6 0 +OP4 E023B7 0 +OP4 E023B8 0 +OP4 E023B9 0 +OP4 E023BA 0 +OP4 E023BB 0 +OP4 E023BC 0 +OP4 E023BD 0 +OP4 E023BE 0 +OP4 E023BF 0 +OP4 E023C0 0 +OP4 E023C1 0 +OP4 E023C2 0 +OP4 E023C3 0 +OP4 E023C4 0 +OP4 E023C5 0 +OP4 E023C6 0 +OP4 E023C7 0 +OP4 E023C8 0 +OP4 E023C9 0 +OP4 E023CA 0 +OP4 E023CB 0 +OP4 E023CC 0 +OP4 E023CD 0 +OP4 E023CE 0 +OP4 E023CF 0 +OP4 E023D0 0 +OP4 E023D1 0 +OP4 E023D2 0 +OP4 E023D3 0 +OP4 E023D4 0 +OP4 E023D5 0 +OP4 E023D6 0 +OP4 E023D7 0 +OP4 E023D8 0 +OP4 E023D9 0 +OP4 E023DA 0 +OP4 E023DB 0 +OP4 E023DC 0 +OP4 E023DD 0 +OP4 E023DE 0 +OP4 E023DF 0 +OP4 E023E0 0 +OP4 E023E1 0 +OP4 E023E2 0 +OP4 E023E3 0 +OP4 E023E4 0 +OP4 E023E5 0 +OP4 E023E6 0 +OP4 E023E7 0 +OP4 E023E8 0 +OP4 E023E9 0 +OP4 E023EA 0 +OP4 E023EB 0 +OP4 E023EC 0 +OP4 E023ED 0 +OP4 E023EE 0 +OP4 E023EF 0 +OP4 E023F0 0 +OP4 E023F1 0 +OP4 E023F2 0 +OP4 E023F3 0 +OP4 E023F4 0 +OP4 E023F5 0 +OP4 E023F6 0 +OP4 E023F7 0 +OP4 E023F8 0 +OP4 E023F9 0 +OP4 E023FA 0 +OP4 E023FB 0 +OP4 E023FC 0 +OP4 E023FD 0 +OP4 E023FE 0 +OP4 E023FF 0 +OP4 E02400 0 +OP4 E02401 0 +OP4 E02402 0 +OP4 E02403 0 +OP4 E02404 0 +OP4 E02405 0 +OP4 E02406 0 +OP4 E02407 0 +OP4 E02408 0 +OP4 E02409 0 +OP4 E0240A 0 +OP4 E0240B 0 +OP4 E0240C 0 +OP4 E0240D 0 +OP4 E0240E 0 +OP4 E0240F 0 +OP4 E02410 0 +OP4 E02411 0 +OP4 E02412 0 +OP4 E02413 0 +OP4 E02414 0 +OP4 E02415 0 +OP4 E02416 0 +OP4 E02417 0 +OP4 E02418 0 +OP4 E02419 0 +OP4 E0241A 0 +OP4 E0241B 0 +OP4 E0241C 0 +OP4 E0241D 0 +OP4 E0241E 0 +OP4 E0241F 0 +OP4 E02420 0 +OP4 E02421 0 +OP4 E02422 0 +OP4 E02423 0 +OP4 E02424 0 +OP4 E02425 0 +OP4 E02426 0 +OP4 E02427 0 +OP4 E02428 0 +OP4 E02429 0 +OP4 E0242A 0 +OP4 E0242B 0 +OP4 E0242C 0 +OP4 E0242D 0 +OP4 E0242E 0 +OP4 E0242F 0 +OP4 E02430 0 +OP4 E02431 0 +OP4 E02432 0 +OP4 E02433 0 +OP4 E02434 0 +OP4 E02435 0 +OP4 E02436 0 +OP4 E02437 0 +OP4 E02438 0 +OP4 E02439 0 +OP4 E0243A 0 +OP4 E0243B 0 +OP4 E0243C 0 +OP4 E0243D 0 +OP4 E0243E 0 +OP4 E0243F 0 +OP4 E02440 0 +OP4 E02441 0 +OP4 E02442 0 +OP4 E02443 0 +OP4 E02444 0 +OP4 E02445 0 +OP4 E02446 0 +OP4 E02447 0 +OP4 E02448 0 +OP4 E02449 0 +OP4 E0244A 0 +OP4 E0244B 0 +OP4 E0244C 0 +OP4 E0244D 0 +OP4 E0244E 0 +OP4 E0244F 0 +OP4 E02450 0 +OP4 E02451 0 +OP4 E02452 0 +OP4 E02453 0 +OP4 E02454 0 +OP4 E02455 0 +OP4 E02456 0 +OP4 E02457 0 +OP4 E02458 0 +OP4 E02459 0 +OP4 E0245A 0 +OP4 E0245B 0 +OP4 E0245C 0 +OP4 E0245D 0 +OP4 E0245E 0 +OP4 E0245F 0 +OP4 E02460 0 +OP4 E02461 0 +OP4 E02462 0 +OP4 E02463 0 +OP4 E02464 0 +OP4 E02465 0 +OP4 E02466 0 +OP4 E02467 0 +OP4 E02468 0 +OP4 E02469 0 +OP4 E0246A 0 +OP4 E0246B 0 +OP4 E0246C 0 +OP4 E0246D 0 +OP4 E0246E 0 +OP4 E0246F 0 +OP4 E02470 0 +OP4 E02471 0 +OP4 E02472 0 +OP4 E02473 0 +OP4 E02474 0 +OP4 E02475 0 +OP4 E02476 0 +OP4 E02477 0 +OP4 E02478 0 +OP4 E02479 0 +OP4 E0247A 0 +OP4 E0247B 0 +OP4 E0247C 0 +OP4 E0247D 0 +OP4 E0247E 0 +OP4 E0247F 0 +OP4 E02480 0 +OP4 E02481 0 +OP4 E02482 0 +OP4 E02483 0 +OP4 E02484 0 +OP4 E02485 0 +OP4 E02486 0 +OP4 E02487 0 +OP4 E02488 0 +OP4 E02489 0 +OP4 E0248A 0 +OP4 E0248B 0 +OP4 E0248C 0 +OP4 E0248D 0 +OP4 E0248E 0 +OP4 E0248F 0 +OP4 E02490 0 +OP4 E02491 0 +OP4 E02492 0 +OP4 E02493 0 +OP4 E02494 0 +OP4 E02495 0 +OP4 E02496 0 +OP4 E02497 0 +OP4 E02498 0 +OP4 E02499 0 +OP4 E0249A 0 +OP4 E0249B 0 +OP4 E0249C 0 +OP4 E0249D 0 +OP4 E0249E 0 +OP4 E0249F 0 +OP4 E024A0 0 +OP4 E024A1 0 +OP4 E024A2 0 +OP4 E024A3 0 +OP4 E024A4 0 +OP4 E024A5 0 +OP4 E024A6 0 +OP4 E024A7 0 +OP4 E024A8 0 +OP4 E024A9 0 +OP4 E024AA 0 +OP4 E024AB 0 +OP4 E024AC 0 +OP4 E024AD 0 +OP4 E024AE 0 +OP4 E024AF 0 +OP4 E024B0 0 +OP4 E024B1 0 +OP4 E024B2 0 +OP4 E024B3 0 +OP4 E024B4 0 +OP4 E024B5 0 +OP4 E024B6 0 +OP4 E024B7 0 +OP4 E024B8 0 +OP4 E024B9 0 +OP4 E024BA 0 +OP4 E024BB 0 +OP4 E024BC 0 +OP4 E024BD 0 +OP4 E024BE 0 +OP4 E024BF 0 +OP4 E024C0 0 +OP4 E024C1 0 +OP4 E024C2 0 +OP4 E024C3 0 +OP4 E024C4 0 +OP4 E024C5 0 +OP4 E024C6 0 +OP4 E024C7 0 +OP4 E024C8 0 +OP4 E024C9 0 +OP4 E024CA 0 +OP4 E024CB 0 +OP4 E024CC 0 +OP4 E024CD 0 +OP4 E024CE 0 +OP4 E024CF 0 +OP4 E024D0 0 +OP4 E024D1 0 +OP4 E024D2 0 +OP4 E024D3 0 +OP4 E024D4 0 +OP4 E024D5 0 +OP4 E024D6 0 +OP4 E024D7 0 +OP4 E024D8 0 +OP4 E024D9 0 +OP4 E024DA 0 +OP4 E024DB 0 +OP4 E024DC 0 +OP4 E024DD 0 +OP4 E024DE 0 +OP4 E024DF 0 +OP4 E024E0 0 +OP4 E024E1 0 +OP4 E024E2 0 +OP4 E024E3 0 +OP4 E024E4 0 +OP4 E024E5 0 +OP4 E024E6 0 +OP4 E024E7 0 +OP4 E024E8 0 +OP4 E024E9 0 +OP4 E024EA 0 +OP4 E024EB 0 +OP4 E024EC 0 +OP4 E024ED 0 +OP4 E024EE 0 +OP4 E024EF 0 +OP4 E024F0 0 +OP4 E024F1 0 +OP4 E024F2 0 +OP4 E024F3 0 +OP4 E024F4 0 +OP4 E024F5 0 +OP4 E024F6 0 +OP4 E024F7 0 +OP4 E024F8 0 +OP4 E024F9 0 +OP4 E024FA 0 +OP4 E024FB 0 +OP4 E024FC 0 +OP4 E024FD 0 +OP4 E024FE 0 +OP4 E024FF 0 +OP4 E02500 0 +OP4 E02501 0 +OP4 E02502 0 +OP4 E02503 0 +OP4 E02504 0 +OP4 E02505 0 +OP4 E02506 0 +OP4 E02507 0 +OP4 E02508 0 +OP4 E02509 0 +OP4 E0250A 0 +OP4 E0250B 0 +OP4 E0250C 0 +OP4 E0250D 0 +OP4 E0250E 0 +OP4 E0250F 0 +OP4 E02510 0 +OP4 E02511 0 +OP4 E02512 0 +OP4 E02513 0 +OP4 E02514 0 +OP4 E02515 0 +OP4 E02516 0 +OP4 E02517 0 +OP4 E02518 0 +OP4 E02519 0 +OP4 E0251A 0 +OP4 E0251B 0 +OP4 E0251C 0 +OP4 E0251D 0 +OP4 E0251E 0 +OP4 E0251F 0 +OP4 E02520 0 +OP4 E02521 0 +OP4 E02522 0 +OP4 E02523 0 +OP4 E02524 0 +OP4 E02525 0 +OP4 E02526 0 +OP4 E02527 0 +OP4 E02528 0 +OP4 E02529 0 +OP4 E0252A 0 +OP4 E0252B 0 +OP4 E0252C 0 +OP4 E0252D 0 +OP4 E0252E 0 +OP4 E0252F 0 +OP4 E02530 0 +OP4 E02531 0 +OP4 E02532 0 +OP4 E02533 0 +OP4 E02534 0 +OP4 E02535 0 +OP4 E02536 0 +OP4 E02537 0 +OP4 E02538 0 +OP4 E02539 0 +OP4 E0253A 0 +OP4 E0253B 0 +OP4 E0253C 0 +OP4 E0253D 0 +OP4 E0253E 0 +OP4 E0253F 0 +OP4 E02540 0 +OP4 E02541 0 +OP4 E02542 0 +OP4 E02543 0 +OP4 E02544 0 +OP4 E02545 0 +OP4 E02546 0 +OP4 E02547 0 +OP4 E02548 0 +OP4 E02549 0 +OP4 E0254A 0 +OP4 E0254B 0 +OP4 E0254C 0 +OP4 E0254D 0 +OP4 E0254E 0 +OP4 E0254F 0 +OP4 E02550 0 +OP4 E02551 0 +OP4 E02552 0 +OP4 E02553 0 +OP4 E02554 0 +OP4 E02555 0 +OP4 E02556 0 +OP4 E02557 0 +OP4 E02558 0 +OP4 E02559 0 +OP4 E0255A 0 +OP4 E0255B 0 +OP4 E0255C 0 +OP4 E0255D 0 +OP4 E0255E 0 +OP4 E0255F 0 +OP4 E02560 0 +OP4 E02561 0 +OP4 E02562 0 +OP4 E02563 0 +OP4 E02564 0 +OP4 E02565 0 +OP4 E02566 0 +OP4 E02567 0 +OP4 E02568 0 +OP4 E02569 0 +OP4 E0256A 0 +OP4 E0256B 0 +OP4 E0256C 0 +OP4 E0256D 0 +OP4 E0256E 0 +OP4 E0256F 0 +OP4 E02570 0 +OP4 E02571 0 +OP4 E02572 0 +OP4 E02573 0 +OP4 E02574 0 +OP4 E02575 0 +OP4 E02576 0 +OP4 E02577 0 +OP4 E02578 0 +OP4 E02579 0 +OP4 E0257A 0 +OP4 E0257B 0 +OP4 E0257C 0 +OP4 E0257D 0 +OP4 E0257E 0 +OP4 E0257F 0 +OP4 E02580 0 +OP4 E02581 0 +OP4 E02582 0 +OP4 E02583 0 +OP4 E02584 0 +OP4 E02585 0 +OP4 E02586 0 +OP4 E02587 0 +OP4 E02588 0 +OP4 E02589 0 +OP4 E0258A 0 +OP4 E0258B 0 +OP4 E0258C 0 +OP4 E0258D 0 +OP4 E0258E 0 +OP4 E0258F 0 +OP4 E02590 0 +OP4 E02591 0 +OP4 E02592 0 +OP4 E02593 0 +OP4 E02594 0 +OP4 E02595 0 +OP4 E02596 0 +OP4 E02597 0 +OP4 E02598 0 +OP4 E02599 0 +OP4 E0259A 0 +OP4 E0259B 0 +OP4 E0259C 0 +OP4 E0259D 0 +OP4 E0259E 0 +OP4 E0259F 0 +OP4 E025A0 0 +OP4 E025A1 0 +OP4 E025A2 0 +OP4 E025A3 0 +OP4 E025A4 0 +OP4 E025A5 0 +OP4 E025A6 0 +OP4 E025A7 0 +OP4 E025A8 0 +OP4 E025A9 0 +OP4 E025AA 0 +OP4 E025AB 0 +OP4 E025AC 0 +OP4 E025AD 0 +OP4 E025AE 0 +OP4 E025AF 0 +OP4 E025B0 0 +OP4 E025B1 0 +OP4 E025B2 0 +OP4 E025B3 0 +OP4 E025B4 0 +OP4 E025B5 0 +OP4 E025B6 0 +OP4 E025B7 0 +OP4 E025B8 0 +OP4 E025B9 0 +OP4 E025BA 0 +OP4 E025BB 0 +OP4 E025BC 0 +OP4 E025BD 0 +OP4 E025BE 0 +OP4 E025BF 0 +OP4 E025C0 0 +OP4 E025C1 0 +OP4 E025C2 0 +OP4 E025C3 0 +OP4 E025C4 0 +OP4 E025C5 0 +OP4 E025C6 0 +OP4 E025C7 0 +OP4 E025C8 0 +OP4 E025C9 0 +OP4 E025CA 0 +OP4 E025CB 0 +OP4 E025CC 0 +OP4 E025CD 0 +OP4 E025CE 0 +OP4 E025CF 0 +OP4 E025D0 0 +OP4 E025D1 0 +OP4 E025D2 0 +OP4 E025D3 0 +OP4 E025D4 0 +OP4 E025D5 0 +OP4 E025D6 0 +OP4 E025D7 0 +OP4 E025D8 0 +OP4 E025D9 0 +OP4 E025DA 0 +OP4 E025DB 0 +OP4 E025DC 0 +OP4 E025DD 0 +OP4 E025DE 0 +OP4 E025DF 0 +OP4 E025E0 0 +OP4 E025E1 0 +OP4 E025E2 0 +OP4 E025E3 0 +OP4 E025E4 0 +OP4 E025E5 0 +OP4 E025E6 0 +OP4 E025E7 0 +OP4 E025E8 0 +OP4 E025E9 0 +OP4 E025EA 0 +OP4 E025EB 0 +OP4 E025EC 0 +OP4 E025ED 0 +OP4 E025EE 0 +OP4 E025EF 0 +OP4 E025F0 0 +OP4 E025F1 0 +OP4 E025F2 0 +OP4 E025F3 0 +OP4 E025F4 0 +OP4 E025F5 0 +OP4 E025F6 0 +OP4 E025F7 0 +OP4 E025F8 0 +OP4 E025F9 0 +OP4 E025FA 0 +OP4 E025FB 0 +OP4 E025FC 0 +OP4 E025FD 0 +OP4 E025FE 0 +OP4 E025FF 0 +OP4 E02600 0 +OP4 E02601 0 +OP4 E02602 0 +OP4 E02603 0 +OP4 E02604 0 +OP4 E02605 0 +OP4 E02606 0 +OP4 E02607 0 +OP4 E02608 0 +OP4 E02609 0 +OP4 E0260A 0 +OP4 E0260B 0 +OP4 E0260C 0 +OP4 E0260D 0 +OP4 E0260E 0 +OP4 E0260F 0 +OP4 E02610 0 +OP4 E02611 0 +OP4 E02612 0 +OP4 E02613 0 +OP4 E02614 0 +OP4 E02615 0 +OP4 E02616 0 +OP4 E02617 0 +OP4 E02618 0 +OP4 E02619 0 +OP4 E0261A 0 +OP4 E0261B 0 +OP4 E0261C 0 +OP4 E0261D 0 +OP4 E0261E 0 +OP4 E0261F 0 +OP4 E02620 0 +OP4 E02621 0 +OP4 E02622 0 +OP4 E02623 0 +OP4 E02624 0 +OP4 E02625 0 +OP4 E02626 0 +OP4 E02627 0 +OP4 E02628 0 +OP4 E02629 0 +OP4 E0262A 0 +OP4 E0262B 0 +OP4 E0262C 0 +OP4 E0262D 0 +OP4 E0262E 0 +OP4 E0262F 0 +OP4 E02630 0 +OP4 E02631 0 +OP4 E02632 0 +OP4 E02633 0 +OP4 E02634 0 +OP4 E02635 0 +OP4 E02636 0 +OP4 E02637 0 +OP4 E02638 0 +OP4 E02639 0 +OP4 E0263A 0 +OP4 E0263B 0 +OP4 E0263C 0 +OP4 E0263D 0 +OP4 E0263E 0 +OP4 E0263F 0 +OP4 E02640 0 +OP4 E02641 0 +OP4 E02642 0 +OP4 E02643 0 +OP4 E02644 0 +OP4 E02645 0 +OP4 E02646 0 +OP4 E02647 0 +OP4 E02648 0 +OP4 E02649 0 +OP4 E0264A 0 +OP4 E0264B 0 +OP4 E0264C 0 +OP4 E0264D 0 +OP4 E0264E 0 +OP4 E0264F 0 +OP4 E02650 0 +OP4 E02651 0 +OP4 E02652 0 +OP4 E02653 0 +OP4 E02654 0 +OP4 E02655 0 +OP4 E02656 0 +OP4 E02657 0 +OP4 E02658 0 +OP4 E02659 0 +OP4 E0265A 0 +OP4 E0265B 0 +OP4 E0265C 0 +OP4 E0265D 0 +OP4 E0265E 0 +OP4 E0265F 0 +OP4 E02660 0 +OP4 E02661 0 +OP4 E02662 0 +OP4 E02663 0 +OP4 E02664 0 +OP4 E02665 0 +OP4 E02666 0 +OP4 E02667 0 +OP4 E02668 0 +OP4 E02669 0 +OP4 E0266A 0 +OP4 E0266B 0 +OP4 E0266C 0 +OP4 E0266D 0 +OP4 E0266E 0 +OP4 E0266F 0 +OP4 E02670 0 +OP4 E02671 0 +OP4 E02672 0 +OP4 E02673 0 +OP4 E02674 0 +OP4 E02675 0 +OP4 E02676 0 +OP4 E02677 0 +OP4 E02678 0 +OP4 E02679 0 +OP4 E0267A 0 +OP4 E0267B 0 +OP4 E0267C 0 +OP4 E0267D 0 +OP4 E0267E 0 +OP4 E0267F 0 +OP4 E02680 0 +OP4 E02681 0 +OP4 E02682 0 +OP4 E02683 0 +OP4 E02684 0 +OP4 E02685 0 +OP4 E02686 0 +OP4 E02687 0 +OP4 E02688 0 +OP4 E02689 0 +OP4 E0268A 0 +OP4 E0268B 0 +OP4 E0268C 0 +OP4 E0268D 0 +OP4 E0268E 0 +OP4 E0268F 0 +OP4 E02690 0 +OP4 E02691 0 +OP4 E02692 0 +OP4 E02693 0 +OP4 E02694 0 +OP4 E02695 0 +OP4 E02696 0 +OP4 E02697 0 +OP4 E02698 0 +OP4 E02699 0 +OP4 E0269A 0 +OP4 E0269B 0 +OP4 E0269C 0 +OP4 E0269D 0 +OP4 E0269E 0 +OP4 E0269F 0 +OP4 E026A0 0 +OP4 E026A1 0 +OP4 E026A2 0 +OP4 E026A3 0 +OP4 E026A4 0 +OP4 E026A5 0 +OP4 E026A6 0 +OP4 E026A7 0 +OP4 E026A8 0 +OP4 E026A9 0 +OP4 E026AA 0 +OP4 E026AB 0 +OP4 E026AC 0 +OP4 E026AD 0 +OP4 E026AE 0 +OP4 E026AF 0 +OP4 E026B0 0 +OP4 E026B1 0 +OP4 E026B2 0 +OP4 E026B3 0 +OP4 E026B4 0 +OP4 E026B5 0 +OP4 E026B6 0 +OP4 E026B7 0 +OP4 E026B8 0 +OP4 E026B9 0 +OP4 E026BA 0 +OP4 E026BB 0 +OP4 E026BC 0 +OP4 E026BD 0 +OP4 E026BE 0 +OP4 E026BF 0 +OP4 E026C0 0 +OP4 E026C1 0 +OP4 E026C2 0 +OP4 E026C3 0 +OP4 E026C4 0 +OP4 E026C5 0 +OP4 E026C6 0 +OP4 E026C7 0 +OP4 E026C8 0 +OP4 E026C9 0 +OP4 E026CA 0 +OP4 E026CB 0 +OP4 E026CC 0 +OP4 E026CD 0 +OP4 E026CE 0 +OP4 E026CF 0 +OP4 E026D0 0 +OP4 E026D1 0 +OP4 E026D2 0 +OP4 E026D3 0 +OP4 E026D4 0 +OP4 E026D5 0 +OP4 E026D6 0 +OP4 E026D7 0 +OP4 E026D8 0 +OP4 E026D9 0 +OP4 E026DA 0 +OP4 E026DB 0 +OP4 E026DC 0 +OP4 E026DD 0 +OP4 E026DE 0 +OP4 E026DF 0 +OP4 E026E0 0 +OP4 E026E1 0 +OP4 E026E2 0 +OP4 E026E3 0 +OP4 E026E4 0 +OP4 E026E5 0 +OP4 E026E6 0 +OP4 E026E7 0 +OP4 E026E8 0 +OP4 E026E9 0 +OP4 E026EA 0 +OP4 E026EB 0 +OP4 E026EC 0 +OP4 E026ED 0 +OP4 E026EE 0 +OP4 E026EF 0 +OP4 E026F0 0 +OP4 E026F1 0 +OP4 E026F2 0 +OP4 E026F3 0 +OP4 E026F4 0 +OP4 E026F5 0 +OP4 E026F6 0 +OP4 E026F7 0 +OP4 E026F8 0 +OP4 E026F9 0 +OP4 E026FA 0 +OP4 E026FB 0 +OP4 E026FC 0 +OP4 E026FD 0 +OP4 E026FE 0 +OP4 E026FF 0 +OP4 E02700 0 +OP4 E02701 0 +OP4 E02702 0 +OP4 E02703 0 +OP4 E02704 0 +OP4 E02705 0 +OP4 E02706 0 +OP4 E02707 0 +OP4 E02708 0 +OP4 E02709 0 +OP4 E0270A 0 +OP4 E0270B 0 +OP4 E0270C 0 +OP4 E0270D 0 +OP4 E0270E 0 +OP4 E0270F 0 +OP4 E02710 0 +OP4 E02711 0 +OP4 E02712 0 +OP4 E02713 0 +OP4 E02714 0 +OP4 E02715 0 +OP4 E02716 0 +OP4 E02717 0 +OP4 E02718 0 +OP4 E02719 0 +OP4 E0271A 0 +OP4 E0271B 0 +OP4 E0271C 0 +OP4 E0271D 0 +OP4 E0271E 0 +OP4 E0271F 0 +OP4 E02720 0 +OP4 E02721 0 +OP4 E02722 0 +OP4 E02723 0 +OP4 E02724 0 +OP4 E02725 0 +OP4 E02726 0 +OP4 E02727 0 +OP4 E02728 0 +OP4 E02729 0 +OP4 E0272A 0 +OP4 E0272B 0 +OP4 E0272C 0 +OP4 E0272D 0 +OP4 E0272E 0 +OP4 E0272F 0 +OP4 E02730 0 +OP4 E02731 0 +OP4 E02732 0 +OP4 E02733 0 +OP4 E02734 0 +OP4 E02735 0 +OP4 E02736 0 +OP4 E02737 0 +OP4 E02738 0 +OP4 E02739 0 +OP4 E0273A 0 +OP4 E0273B 0 +OP4 E0273C 0 +OP4 E0273D 0 +OP4 E0273E 0 +OP4 E0273F 0 +OP4 E02740 0 +OP4 E02741 0 +OP4 E02742 0 +OP4 E02743 0 +OP4 E02744 0 +OP4 E02745 0 +OP4 E02746 0 +OP4 E02747 0 +OP4 E02748 0 +OP4 E02749 0 +OP4 E0274A 0 +OP4 E0274B 0 +OP4 E0274C 0 +OP4 E0274D 0 +OP4 E0274E 0 +OP4 E0274F 0 +OP4 E02750 0 +OP4 E02751 0 +OP4 E02752 0 +OP4 E02753 0 +OP4 E02754 0 +OP4 E02755 0 +OP4 E02756 0 +OP4 E02757 0 +OP4 E02758 0 +OP4 E02759 0 +OP4 E0275A 0 +OP4 E0275B 0 +OP4 E0275C 0 +OP4 E0275D 0 +OP4 E0275E 0 +OP4 E0275F 0 +OP4 E02760 0 +OP4 E02761 0 +OP4 E02762 0 +OP4 E02763 0 +OP4 E02764 0 +OP4 E02765 0 +OP4 E02766 0 +OP4 E02767 0 +OP4 E02768 0 +OP4 E02769 0 +OP4 E0276A 0 +OP4 E0276B 0 +OP4 E0276C 0 +OP4 E0276D 0 +OP4 E0276E 0 +OP4 E0276F 0 +OP4 E02770 0 +OP4 E02771 0 +OP4 E02772 0 +OP4 E02773 0 +OP4 E02774 0 +OP4 E02775 0 +OP4 E02776 0 +OP4 E02777 0 +OP4 E02778 0 +OP4 E02779 0 +OP4 E0277A 0 +OP4 E0277B 0 +OP4 E0277C 0 +OP4 E0277D 0 +OP4 E0277E 0 +OP4 E0277F 0 +OP4 E02780 0 +OP4 E02781 0 +OP4 E02782 0 +OP4 E02783 0 +OP4 E02784 0 +OP4 E02785 0 +OP4 E02786 0 +OP4 E02787 0 +OP4 E02788 0 +OP4 E02789 0 +OP4 E0278A 0 +OP4 E0278B 0 +OP4 E0278C 0 +OP4 E0278D 0 +OP4 E0278E 0 +OP4 E0278F 0 +OP4 E02790 0 +OP4 E02791 0 +OP4 E02792 0 +OP4 E02793 0 +OP4 E02794 0 +OP4 E02795 0 +OP4 E02796 0 +OP4 E02797 0 +OP4 E02798 0 +OP4 E02799 0 +OP4 E0279A 0 +OP4 E0279B 0 +OP4 E0279C 0 +OP4 E0279D 0 +OP4 E0279E 0 +OP4 E0279F 0 +OP4 E027A0 0 +OP4 E027A1 0 +OP4 E027A2 0 +OP4 E027A3 0 +OP4 E027A4 0 +OP4 E027A5 0 +OP4 E027A6 0 +OP4 E027A7 0 +OP4 E027A8 0 +OP4 E027A9 0 +OP4 E027AA 0 +OP4 E027AB 0 +OP4 E027AC 0 +OP4 E027AD 0 +OP4 E027AE 0 +OP4 E027AF 0 +OP4 E027B0 0 +OP4 E027B1 0 +OP4 E027B2 0 +OP4 E027B3 0 +OP4 E027B4 0 +OP4 E027B5 0 +OP4 E027B6 0 +OP4 E027B7 0 +OP4 E027B8 0 +OP4 E027B9 0 +OP4 E027BA 0 +OP4 E027BB 0 +OP4 E027BC 0 +OP4 E027BD 0 +OP4 E027BE 0 +OP4 E027BF 0 +OP4 E027C0 0 +OP4 E027C1 0 +OP4 E027C2 0 +OP4 E027C3 0 +OP4 E027C4 0 +OP4 E027C5 0 +OP4 E027C6 0 +OP4 E027C7 0 +OP4 E027C8 0 +OP4 E027C9 0 +OP4 E027CA 0 +OP4 E027CB 0 +OP4 E027CC 0 +OP4 E027CD 0 +OP4 E027CE 0 +OP4 E027CF 0 +OP4 E027D0 0 +OP4 E027D1 0 +OP4 E027D2 0 +OP4 E027D3 0 +OP4 E027D4 0 +OP4 E027D5 0 +OP4 E027D6 0 +OP4 E027D7 0 +OP4 E027D8 0 +OP4 E027D9 0 +OP4 E027DA 0 +OP4 E027DB 0 +OP4 E027DC 0 +OP4 E027DD 0 +OP4 E027DE 0 +OP4 E027DF 0 +OP4 E027E0 0 +OP4 E027E1 0 +OP4 E027E2 0 +OP4 E027E3 0 +OP4 E027E4 0 +OP4 E027E5 0 +OP4 E027E6 0 +OP4 E027E7 0 +OP4 E027E8 0 +OP4 E027E9 0 +OP4 E027EA 0 +OP4 E027EB 0 +OP4 E027EC 0 +OP4 E027ED 0 +OP4 E027EE 0 +OP4 E027EF 0 +OP4 E027F0 0 +OP4 E027F1 0 +OP4 E027F2 0 +OP4 E027F3 0 +OP4 E027F4 0 +OP4 E027F5 0 +OP4 E027F6 0 +OP4 E027F7 0 +OP4 E027F8 0 +OP4 E027F9 0 +OP4 E027FA 0 +OP4 E027FB 0 +OP4 E027FC 0 +OP4 E027FD 0 +OP4 E027FE 0 +OP4 E027FF 0 +OP4 E02800 0 +OP4 E02801 0 +OP4 E02802 0 +OP4 E02803 0 +OP4 E02804 0 +OP4 E02805 0 +OP4 E02806 0 +OP4 E02807 0 +OP4 E02808 0 +OP4 E02809 0 +OP4 E0280A 0 +OP4 E0280B 0 +OP4 E0280C 0 +OP4 E0280D 0 +OP4 E0280E 0 +OP4 E0280F 0 +OP4 E02810 0 +OP4 E02811 0 +OP4 E02812 0 +OP4 E02813 0 +OP4 E02814 0 +OP4 E02815 0 +OP4 E02816 0 +OP4 E02817 0 +OP4 E02818 0 +OP4 E02819 0 +OP4 E0281A 0 +OP4 E0281B 0 +OP4 E0281C 0 +OP4 E0281D 0 +OP4 E0281E 0 +OP4 E0281F 0 +OP4 E02820 0 +OP4 E02821 0 +OP4 E02822 0 +OP4 E02823 0 +OP4 E02824 0 +OP4 E02825 0 +OP4 E02826 0 +OP4 E02827 0 +OP4 E02828 0 +OP4 E02829 0 +OP4 E0282A 0 +OP4 E0282B 0 +OP4 E0282C 0 +OP4 E0282D 0 +OP4 E0282E 0 +OP4 E0282F 0 +OP4 E02830 0 +OP4 E02831 0 +OP4 E02832 0 +OP4 E02833 0 +OP4 E02834 0 +OP4 E02835 0 +OP4 E02836 0 +OP4 E02837 0 +OP4 E02838 0 +OP4 E02839 0 +OP4 E0283A 0 +OP4 E0283B 0 +OP4 E0283C 0 +OP4 E0283D 0 +OP4 E0283E 0 +OP4 E0283F 0 +OP4 E02840 0 +OP4 E02841 0 +OP4 E02842 0 +OP4 E02843 0 +OP4 E02844 0 +OP4 E02845 0 +OP4 E02846 0 +OP4 E02847 0 +OP4 E02848 0 +OP4 E02849 0 +OP4 E0284A 0 +OP4 E0284B 0 +OP4 E0284C 0 +OP4 E0284D 0 +OP4 E0284E 0 +OP4 E0284F 0 +OP4 E02850 0 +OP4 E02851 0 +OP4 E02852 0 +OP4 E02853 0 +OP4 E02854 0 +OP4 E02855 0 +OP4 E02856 0 +OP4 E02857 0 +OP4 E02858 0 +OP4 E02859 0 +OP4 E0285A 0 +OP4 E0285B 0 +OP4 E0285C 0 +OP4 E0285D 0 +OP4 E0285E 0 +OP4 E0285F 0 +OP4 E02860 0 +OP4 E02861 0 +OP4 E02862 0 +OP4 E02863 0 +OP4 E02864 0 +OP4 E02865 0 +OP4 E02866 0 +OP4 E02867 0 +OP4 E02868 0 +OP4 E02869 0 +OP4 E0286A 0 +OP4 E0286B 0 +OP4 E0286C 0 +OP4 E0286D 0 +OP4 E0286E 0 +OP4 E0286F 0 +OP4 E02870 0 +OP4 E02871 0 +OP4 E02872 0 +OP4 E02873 0 +OP4 E02874 0 +OP4 E02875 0 +OP4 E02876 0 +OP4 E02877 0 +OP4 E02878 0 +OP4 E02879 0 +OP4 E0287A 0 +OP4 E0287B 0 +OP4 E0287C 0 +OP4 E0287D 0 +OP4 E0287E 0 +OP4 E0287F 0 +OP4 E02880 0 +OP4 E02881 0 +OP4 E02882 0 +OP4 E02883 0 +OP4 E02884 0 +OP4 E02885 0 +OP4 E02886 0 +OP4 E02887 0 +OP4 E02888 0 +OP4 E02889 0 +OP4 E0288A 0 +OP4 E0288B 0 +OP4 E0288C 0 +OP4 E0288D 0 +OP4 E0288E 0 +OP4 E0288F 0 +OP4 E02890 0 +OP4 E02891 0 +OP4 E02892 0 +OP4 E02893 0 +OP4 E02894 0 +OP4 E02895 0 +OP4 E02896 0 +OP4 E02897 0 +OP4 E02898 0 +OP4 E02899 0 +OP4 E0289A 0 +OP4 E0289B 0 +OP4 E0289C 0 +OP4 E0289D 0 +OP4 E0289E 0 +OP4 E0289F 0 +OP4 E028A0 0 +OP4 E028A1 0 +OP4 E028A2 0 +OP4 E028A3 0 +OP4 E028A4 0 +OP4 E028A5 0 +OP4 E028A6 0 +OP4 E028A7 0 +OP4 E028A8 0 +OP4 E028A9 0 +OP4 E028AA 0 +OP4 E028AB 0 +OP4 E028AC 0 +OP4 E028AD 0 +OP4 E028AE 0 +OP4 E028AF 0 +OP4 E028B0 0 +OP4 E028B1 0 +OP4 E028B2 0 +OP4 E028B3 0 +OP4 E028B4 0 +OP4 E028B5 0 +OP4 E028B6 0 +OP4 E028B7 0 +OP4 E028B8 0 +OP4 E028B9 0 +OP4 E028BA 0 +OP4 E028BB 0 +OP4 E028BC 0 +OP4 E028BD 0 +OP4 E028BE 0 +OP4 E028BF 0 +OP4 E028C0 0 +OP4 E028C1 0 +OP4 E028C2 0 +OP4 E028C3 0 +OP4 E028C4 0 +OP4 E028C5 0 +OP4 E028C6 0 +OP4 E028C7 0 +OP4 E028C8 0 +OP4 E028C9 0 +OP4 E028CA 0 +OP4 E028CB 0 +OP4 E028CC 0 +OP4 E028CD 0 +OP4 E028CE 0 +OP4 E028CF 0 +OP4 E028D0 0 +OP4 E028D1 0 +OP4 E028D2 0 +OP4 E028D3 0 +OP4 E028D4 0 +OP4 E028D5 0 +OP4 E028D6 0 +OP4 E028D7 0 +OP4 E028D8 0 +OP4 E028D9 0 +OP4 E028DA 0 +OP4 E028DB 0 +OP4 E028DC 0 +OP4 E028DD 0 +OP4 E028DE 0 +OP4 E028DF 0 +OP4 E028E0 0 +OP4 E028E1 0 +OP4 E028E2 0 +OP4 E028E3 0 +OP4 E028E4 0 +OP4 E028E5 0 +OP4 E028E6 0 +OP4 E028E7 0 +OP4 E028E8 0 +OP4 E028E9 0 +OP4 E028EA 0 +OP4 E028EB 0 +OP4 E028EC 0 +OP4 E028ED 0 +OP4 E028EE 0 +OP4 E028EF 0 +OP4 E028F0 0 +OP4 E028F1 0 +OP4 E028F2 0 +OP4 E028F3 0 +OP4 E028F4 0 +OP4 E028F5 0 +OP4 E028F6 0 +OP4 E028F7 0 +OP4 E028F8 0 +OP4 E028F9 0 +OP4 E028FA 0 +OP4 E028FB 0 +OP4 E028FC 0 +OP4 E028FD 0 +OP4 E028FE 0 +OP4 E028FF 0 +OP4 E02900 0 +OP4 E02901 0 +OP4 E02902 0 +OP4 E02903 0 +OP4 E02904 0 +OP4 E02905 0 +OP4 E02906 0 +OP4 E02907 0 +OP4 E02908 0 +OP4 E02909 0 +OP4 E0290A 0 +OP4 E0290B 0 +OP4 E0290C 0 +OP4 E0290D 0 +OP4 E0290E 0 +OP4 E0290F 0 +OP4 E02910 0 +OP4 E02911 0 +OP4 E02912 0 +OP4 E02913 0 +OP4 E02914 0 +OP4 E02915 0 +OP4 E02916 0 +OP4 E02917 0 +OP4 E02918 0 +OP4 E02919 0 +OP4 E0291A 0 +OP4 E0291B 0 +OP4 E0291C 0 +OP4 E0291D 0 +OP4 E0291E 0 +OP4 E0291F 0 +OP4 E02920 0 +OP4 E02921 0 +OP4 E02922 0 +OP4 E02923 0 +OP4 E02924 0 +OP4 E02925 0 +OP4 E02926 0 +OP4 E02927 0 +OP4 E02928 0 +OP4 E02929 0 +OP4 E0292A 0 +OP4 E0292B 0 +OP4 E0292C 0 +OP4 E0292D 0 +OP4 E0292E 0 +OP4 E0292F 0 +OP4 E02930 0 +OP4 E02931 0 +OP4 E02932 0 +OP4 E02933 0 +OP4 E02934 0 +OP4 E02935 0 +OP4 E02936 0 +OP4 E02937 0 +OP4 E02938 0 +OP4 E02939 0 +OP4 E0293A 0 +OP4 E0293B 0 +OP4 E0293C 0 +OP4 E0293D 0 +OP4 E0293E 0 +OP4 E0293F 0 +OP4 E02940 0 +OP4 E02941 0 +OP4 E02942 0 +OP4 E02943 0 +OP4 E02944 0 +OP4 E02945 0 +OP4 E02946 0 +OP4 E02947 0 +OP4 E02948 0 +OP4 E02949 0 +OP4 E0294A 0 +OP4 E0294B 0 +OP4 E0294C 0 +OP4 E0294D 0 +OP4 E0294E 0 +OP4 E0294F 0 +OP4 E02950 0 +OP4 E02951 0 +OP4 E02952 0 +OP4 E02953 0 +OP4 E02954 0 +OP4 E02955 0 +OP4 E02956 0 +OP4 E02957 0 +OP4 E02958 0 +OP4 E02959 0 +OP4 E0295A 0 +OP4 E0295B 0 +OP4 E0295C 0 +OP4 E0295D 0 +OP4 E0295E 0 +OP4 E0295F 0 +OP4 E02960 0 +OP4 E02961 0 +OP4 E02962 0 +OP4 E02963 0 +OP4 E02964 0 +OP4 E02965 0 +OP4 E02966 0 +OP4 E02967 0 +OP4 E02968 0 +OP4 E02969 0 +OP4 E0296A 0 +OP4 E0296B 0 +OP4 E0296C 0 +OP4 E0296D 0 +OP4 E0296E 0 +OP4 E0296F 0 +OP4 E02970 0 +OP4 E02971 0 +OP4 E02972 0 +OP4 E02973 0 +OP4 E02974 0 +OP4 E02975 0 +OP4 E02976 0 +OP4 E02977 0 +OP4 E02978 0 +OP4 E02979 0 +OP4 E0297A 0 +OP4 E0297B 0 +OP4 E0297C 0 +OP4 E0297D 0 +OP4 E0297E 0 +OP4 E0297F 0 +OP4 E02980 0 +OP4 E02981 0 +OP4 E02982 0 +OP4 E02983 0 +OP4 E02984 0 +OP4 E02985 0 +OP4 E02986 0 +OP4 E02987 0 +OP4 E02988 0 +OP4 E02989 0 +OP4 E0298A 0 +OP4 E0298B 0 +OP4 E0298C 0 +OP4 E0298D 0 +OP4 E0298E 0 +OP4 E0298F 0 +OP4 E02990 0 +OP4 E02991 0 +OP4 E02992 0 +OP4 E02993 0 +OP4 E02994 0 +OP4 E02995 0 +OP4 E02996 0 +OP4 E02997 0 +OP4 E02998 0 +OP4 E02999 0 +OP4 E0299A 0 +OP4 E0299B 0 +OP4 E0299C 0 +OP4 E0299D 0 +OP4 E0299E 0 +OP4 E0299F 0 +OP4 E029A0 0 +OP4 E029A1 0 +OP4 E029A2 0 +OP4 E029A3 0 +OP4 E029A4 0 +OP4 E029A5 0 +OP4 E029A6 0 +OP4 E029A7 0 +OP4 E029A8 0 +OP4 E029A9 0 +OP4 E029AA 0 +OP4 E029AB 0 +OP4 E029AC 0 +OP4 E029AD 0 +OP4 E029AE 0 +OP4 E029AF 0 +OP4 E029B0 0 +OP4 E029B1 0 +OP4 E029B2 0 +OP4 E029B3 0 +OP4 E029B4 0 +OP4 E029B5 0 +OP4 E029B6 0 +OP4 E029B7 0 +OP4 E029B8 0 +OP4 E029B9 0 +OP4 E029BA 0 +OP4 E029BB 0 +OP4 E029BC 0 +OP4 E029BD 0 +OP4 E029BE 0 +OP4 E029BF 0 +OP4 E029C0 0 +OP4 E029C1 0 +OP4 E029C2 0 +OP4 E029C3 0 +OP4 E029C4 0 +OP4 E029C5 0 +OP4 E029C6 0 +OP4 E029C7 0 +OP4 E029C8 0 +OP4 E029C9 0 +OP4 E029CA 0 +OP4 E029CB 0 +OP4 E029CC 0 +OP4 E029CD 0 +OP4 E029CE 0 +OP4 E029CF 0 +OP4 E029D0 0 +OP4 E029D1 0 +OP4 E029D2 0 +OP4 E029D3 0 +OP4 E029D4 0 +OP4 E029D5 0 +OP4 E029D6 0 +OP4 E029D7 0 +OP4 E029D8 0 +OP4 E029D9 0 +OP4 E029DA 0 +OP4 E029DB 0 +OP4 E029DC 0 +OP4 E029DD 0 +OP4 E029DE 0 +OP4 E029DF 0 +OP4 E029E0 0 +OP4 E029E1 0 +OP4 E029E2 0 +OP4 E029E3 0 +OP4 E029E4 0 +OP4 E029E5 0 +OP4 E029E6 0 +OP4 E029E7 0 +OP4 E029E8 0 +OP4 E029E9 0 +OP4 E029EA 0 +OP4 E029EB 0 +OP4 E029EC 0 +OP4 E029ED 0 +OP4 E029EE 0 +OP4 E029EF 0 +OP4 E029F0 0 +OP4 E029F1 0 +OP4 E029F2 0 +OP4 E029F3 0 +OP4 E029F4 0 +OP4 E029F5 0 +OP4 E029F6 0 +OP4 E029F7 0 +OP4 E029F8 0 +OP4 E029F9 0 +OP4 E029FA 0 +OP4 E029FB 0 +OP4 E029FC 0 +OP4 E029FD 0 +OP4 E029FE 0 +OP4 E029FF 0 +OP4 E02A00 0 +OP4 E02A01 0 +OP4 E02A02 0 +OP4 E02A03 0 +OP4 E02A04 0 +OP4 E02A05 0 +OP4 E02A06 0 +OP4 E02A07 0 +OP4 E02A08 0 +OP4 E02A09 0 +OP4 E02A0A 0 +OP4 E02A0B 0 +OP4 E02A0C 0 +OP4 E02A0D 0 +OP4 E02A0E 0 +OP4 E02A0F 0 +OP4 E02A10 0 +OP4 E02A11 0 +OP4 E02A12 0 +OP4 E02A13 0 +OP4 E02A14 0 +OP4 E02A15 0 +OP4 E02A16 0 +OP4 E02A17 0 +OP4 E02A18 0 +OP4 E02A19 0 +OP4 E02A1A 0 +OP4 E02A1B 0 +OP4 E02A1C 0 +OP4 E02A1D 0 +OP4 E02A1E 0 +OP4 E02A1F 0 +OP4 E02A20 0 +OP4 E02A21 0 +OP4 E02A22 0 +OP4 E02A23 0 +OP4 E02A24 0 +OP4 E02A25 0 +OP4 E02A26 0 +OP4 E02A27 0 +OP4 E02A28 0 +OP4 E02A29 0 +OP4 E02A2A 0 +OP4 E02A2B 0 +OP4 E02A2C 0 +OP4 E02A2D 0 +OP4 E02A2E 0 +OP4 E02A2F 0 +OP4 E02A30 0 +OP4 E02A31 0 +OP4 E02A32 0 +OP4 E02A33 0 +OP4 E02A34 0 +OP4 E02A35 0 +OP4 E02A36 0 +OP4 E02A37 0 +OP4 E02A38 0 +OP4 E02A39 0 +OP4 E02A3A 0 +OP4 E02A3B 0 +OP4 E02A3C 0 +OP4 E02A3D 0 +OP4 E02A3E 0 +OP4 E02A3F 0 +OP4 E02A40 0 +OP4 E02A41 0 +OP4 E02A42 0 +OP4 E02A43 0 +OP4 E02A44 0 +OP4 E02A45 0 +OP4 E02A46 0 +OP4 E02A47 0 +OP4 E02A48 0 +OP4 E02A49 0 +OP4 E02A4A 0 +OP4 E02A4B 0 +OP4 E02A4C 0 +OP4 E02A4D 0 +OP4 E02A4E 0 +OP4 E02A4F 0 +OP4 E02A50 0 +OP4 E02A51 0 +OP4 E02A52 0 +OP4 E02A53 0 +OP4 E02A54 0 +OP4 E02A55 0 +OP4 E02A56 0 +OP4 E02A57 0 +OP4 E02A58 0 +OP4 E02A59 0 +OP4 E02A5A 0 +OP4 E02A5B 0 +OP4 E02A5C 0 +OP4 E02A5D 0 +OP4 E02A5E 0 +OP4 E02A5F 0 +OP4 E02A60 0 +OP4 E02A61 0 +OP4 E02A62 0 +OP4 E02A63 0 +OP4 E02A64 0 +OP4 E02A65 0 +OP4 E02A66 0 +OP4 E02A67 0 +OP4 E02A68 0 +OP4 E02A69 0 +OP4 E02A6A 0 +OP4 E02A6B 0 +OP4 E02A6C 0 +OP4 E02A6D 0 +OP4 E02A6E 0 +OP4 E02A6F 0 +OP4 E02A70 0 +OP4 E02A71 0 +OP4 E02A72 0 +OP4 E02A73 0 +OP4 E02A74 0 +OP4 E02A75 0 +OP4 E02A76 0 +OP4 E02A77 0 +OP4 E02A78 0 +OP4 E02A79 0 +OP4 E02A7A 0 +OP4 E02A7B 0 +OP4 E02A7C 0 +OP4 E02A7D 0 +OP4 E02A7E 0 +OP4 E02A7F 0 +OP4 E02A80 0 +OP4 E02A81 0 +OP4 E02A82 0 +OP4 E02A83 0 +OP4 E02A84 0 +OP4 E02A85 0 +OP4 E02A86 0 +OP4 E02A87 0 +OP4 E02A88 0 +OP4 E02A89 0 +OP4 E02A8A 0 +OP4 E02A8B 0 +OP4 E02A8C 0 +OP4 E02A8D 0 +OP4 E02A8E 0 +OP4 E02A8F 0 +OP4 E02A90 0 +OP4 E02A91 0 +OP4 E02A92 0 +OP4 E02A93 0 +OP4 E02A94 0 +OP4 E02A95 0 +OP4 E02A96 0 +OP4 E02A97 0 +OP4 E02A98 0 +OP4 E02A99 0 +OP4 E02A9A 0 +OP4 E02A9B 0 +OP4 E02A9C 0 +OP4 E02A9D 0 +OP4 E02A9E 0 +OP4 E02A9F 0 +OP4 E02AA0 0 +OP4 E02AA1 0 +OP4 E02AA2 0 +OP4 E02AA3 0 +OP4 E02AA4 0 +OP4 E02AA5 0 +OP4 E02AA6 0 +OP4 E02AA7 0 +OP4 E02AA8 0 +OP4 E02AA9 0 +OP4 E02AAA 0 +OP4 E02AAB 0 +OP4 E02AAC 0 +OP4 E02AAD 0 +OP4 E02AAE 0 +OP4 E02AAF 0 +OP4 E02AB0 0 +OP4 E02AB1 0 +OP4 E02AB2 0 +OP4 E02AB3 0 +OP4 E02AB4 0 +OP4 E02AB5 0 +OP4 E02AB6 0 +OP4 E02AB7 0 +OP4 E02AB8 0 +OP4 E02AB9 0 +OP4 E02ABA 0 +OP4 E02ABB 0 +OP4 E02ABC 0 +OP4 E02ABD 0 +OP4 E02ABE 0 +OP4 E02ABF 0 +OP4 E02AC0 0 +OP4 E02AC1 0 +OP4 E02AC2 0 +OP4 E02AC3 0 +OP4 E02AC4 0 +OP4 E02AC5 0 +OP4 E02AC6 0 +OP4 E02AC7 0 +OP4 E02AC8 0 +OP4 E02AC9 0 +OP4 E02ACA 0 +OP4 E02ACB 0 +OP4 E02ACC 0 +OP4 E02ACD 0 +OP4 E02ACE 0 +OP4 E02ACF 0 +OP4 E02AD0 0 +OP4 E02AD1 0 +OP4 E02AD2 0 +OP4 E02AD3 0 +OP4 E02AD4 0 +OP4 E02AD5 0 +OP4 E02AD6 0 +OP4 E02AD7 0 +OP4 E02AD8 0 +OP4 E02AD9 0 +OP4 E02ADA 0 +OP4 E02ADB 0 +OP4 E02ADC 0 +OP4 E02ADD 0 +OP4 E02ADE 0 +OP4 E02ADF 0 +OP4 E02AE0 0 +OP4 E02AE1 0 +OP4 E02AE2 0 +OP4 E02AE3 0 +OP4 E02AE4 0 +OP4 E02AE5 0 +OP4 E02AE6 0 +OP4 E02AE7 0 +OP4 E02AE8 0 +OP4 E02AE9 0 +OP4 E02AEA 0 +OP4 E02AEB 0 +OP4 E02AEC 0 +OP4 E02AED 0 +OP4 E02AEE 0 +OP4 E02AEF 0 +OP4 E02AF0 0 +OP4 E02AF1 0 +OP4 E02AF2 0 +OP4 E02AF3 0 +OP4 E02AF4 0 +OP4 E02AF5 0 +OP4 E02AF6 0 +OP4 E02AF7 0 +OP4 E02AF8 0 +OP4 E02AF9 0 +OP4 E02AFA 0 +OP4 E02AFB 0 +OP4 E02AFC 0 +OP4 E02AFD 0 +OP4 E02AFE 0 +OP4 E02AFF 0 +OP4 E02B00 0 +OP4 E02B01 0 +OP4 E02B02 0 +OP4 E02B03 0 +OP4 E02B04 0 +OP4 E02B05 0 +OP4 E02B06 0 +OP4 E02B07 0 +OP4 E02B08 0 +OP4 E02B09 0 +OP4 E02B0A 0 +OP4 E02B0B 0 +OP4 E02B0C 0 +OP4 E02B0D 0 +OP4 E02B0E 0 +OP4 E02B0F 0 +OP4 E02B10 0 +OP4 E02B11 0 +OP4 E02B12 0 +OP4 E02B13 0 +OP4 E02B14 0 +OP4 E02B15 0 +OP4 E02B16 0 +OP4 E02B17 0 +OP4 E02B18 0 +OP4 E02B19 0 +OP4 E02B1A 0 +OP4 E02B1B 0 +OP4 E02B1C 0 +OP4 E02B1D 0 +OP4 E02B1E 0 +OP4 E02B1F 0 +OP4 E02B20 0 +OP4 E02B21 0 +OP4 E02B22 0 +OP4 E02B23 0 +OP4 E02B24 0 +OP4 E02B25 0 +OP4 E02B26 0 +OP4 E02B27 0 +OP4 E02B28 0 +OP4 E02B29 0 +OP4 E02B2A 0 +OP4 E02B2B 0 +OP4 E02B2C 0 +OP4 E02B2D 0 +OP4 E02B2E 0 +OP4 E02B2F 0 +OP4 E02B30 0 +OP4 E02B31 0 +OP4 E02B32 0 +OP4 E02B33 0 +OP4 E02B34 0 +OP4 E02B35 0 +OP4 E02B36 0 +OP4 E02B37 0 +OP4 E02B38 0 +OP4 E02B39 0 +OP4 E02B3A 0 +OP4 E02B3B 0 +OP4 E02B3C 0 +OP4 E02B3D 0 +OP4 E02B3E 0 +OP4 E02B3F 0 +OP4 E02B40 0 +OP4 E02B41 0 +OP4 E02B42 0 +OP4 E02B43 0 +OP4 E02B44 0 +OP4 E02B45 0 +OP4 E02B46 0 +OP4 E02B47 0 +OP4 E02B48 0 +OP4 E02B49 0 +OP4 E02B4A 0 +OP4 E02B4B 0 +OP4 E02B4C 0 +OP4 E02B4D 0 +OP4 E02B4E 0 +OP4 E02B4F 0 +OP4 E02B50 0 +OP4 E02B51 0 +OP4 E02B52 0 +OP4 E02B53 0 +OP4 E02B54 0 +OP4 E02B55 0 +OP4 E02B56 0 +OP4 E02B57 0 +OP4 E02B58 0 +OP4 E02B59 0 +OP4 E02B5A 0 +OP4 E02B5B 0 +OP4 E02B5C 0 +OP4 E02B5D 0 +OP4 E02B5E 0 +OP4 E02B5F 0 +OP4 E02B60 0 +OP4 E02B61 0 +OP4 E02B62 0 +OP4 E02B63 0 +OP4 E02B64 0 +OP4 E02B65 0 +OP4 E02B66 0 +OP4 E02B67 0 +OP4 E02B68 0 +OP4 E02B69 0 +OP4 E02B6A 0 +OP4 E02B6B 0 +OP4 E02B6C 0 +OP4 E02B6D 0 +OP4 E02B6E 0 +OP4 E02B6F 0 +OP4 E02B70 0 +OP4 E02B71 0 +OP4 E02B72 0 +OP4 E02B73 0 +OP4 E02B74 0 +OP4 E02B75 0 +OP4 E02B76 0 +OP4 E02B77 0 +OP4 E02B78 0 +OP4 E02B79 0 +OP4 E02B7A 0 +OP4 E02B7B 0 +OP4 E02B7C 0 +OP4 E02B7D 0 +OP4 E02B7E 0 +OP4 E02B7F 0 +OP4 E02B80 0 +OP4 E02B81 0 +OP4 E02B82 0 +OP4 E02B83 0 +OP4 E02B84 0 +OP4 E02B85 0 +OP4 E02B86 0 +OP4 E02B87 0 +OP4 E02B88 0 +OP4 E02B89 0 +OP4 E02B8A 0 +OP4 E02B8B 0 +OP4 E02B8C 0 +OP4 E02B8D 0 +OP4 E02B8E 0 +OP4 E02B8F 0 +OP4 E02B90 0 +OP4 E02B91 0 +OP4 E02B92 0 +OP4 E02B93 0 +OP4 E02B94 0 +OP4 E02B95 0 +OP4 E02B96 0 +OP4 E02B97 0 +OP4 E02B98 0 +OP4 E02B99 0 +OP4 E02B9A 0 +OP4 E02B9B 0 +OP4 E02B9C 0 +OP4 E02B9D 0 +OP4 E02B9E 0 +OP4 E02B9F 0 +OP4 E02BA0 0 +OP4 E02BA1 0 +OP4 E02BA2 0 +OP4 E02BA3 0 +OP4 E02BA4 0 +OP4 E02BA5 0 +OP4 E02BA6 0 +OP4 E02BA7 0 +OP4 E02BA8 0 +OP4 E02BA9 0 +OP4 E02BAA 0 +OP4 E02BAB 0 +OP4 E02BAC 0 +OP4 E02BAD 0 +OP4 E02BAE 0 +OP4 E02BAF 0 +OP4 E02BB0 0 +OP4 E02BB1 0 +OP4 E02BB2 0 +OP4 E02BB3 0 +OP4 E02BB4 0 +OP4 E02BB5 0 +OP4 E02BB6 0 +OP4 E02BB7 0 +OP4 E02BB8 0 +OP4 E02BB9 0 +OP4 E02BBA 0 +OP4 E02BBB 0 +OP4 E02BBC 0 +OP4 E02BBD 0 +OP4 E02BBE 0 +OP4 E02BBF 0 +OP4 E02BC0 0 +OP4 E02BC1 0 +OP4 E02BC2 0 +OP4 E02BC3 0 +OP4 E02BC4 0 +OP4 E02BC5 0 +OP4 E02BC6 0 +OP4 E02BC7 0 +OP4 E02BC8 0 +OP4 E02BC9 0 +OP4 E02BCA 0 +OP4 E02BCB 0 +OP4 E02BCC 0 +OP4 E02BCD 0 +OP4 E02BCE 0 +OP4 E02BCF 0 +OP4 E02BD0 0 +OP4 E02BD1 0 +OP4 E02BD2 0 +OP4 E02BD3 0 +OP4 E02BD4 0 +OP4 E02BD5 0 +OP4 E02BD6 0 +OP4 E02BD7 0 +OP4 E02BD8 0 +OP4 E02BD9 0 +OP4 E02BDA 0 +OP4 E02BDB 0 +OP4 E02BDC 0 +OP4 E02BDD 0 +OP4 E02BDE 0 +OP4 E02BDF 0 +OP4 E02BE0 0 +OP4 E02BE1 0 +OP4 E02BE2 0 +OP4 E02BE3 0 +OP4 E02BE4 0 +OP4 E02BE5 0 +OP4 E02BE6 0 +OP4 E02BE7 0 +OP4 E02BE8 0 +OP4 E02BE9 0 +OP4 E02BEA 0 +OP4 E02BEB 0 +OP4 E02BEC 0 +OP4 E02BED 0 +OP4 E02BEE 0 +OP4 E02BEF 0 +OP4 E02BF0 0 +OP4 E02BF1 0 +OP4 E02BF2 0 +OP4 E02BF3 0 +OP4 E02BF4 0 +OP4 E02BF5 0 +OP4 E02BF6 0 +OP4 E02BF7 0 +OP4 E02BF8 0 +OP4 E02BF9 0 +OP4 E02BFA 0 +OP4 E02BFB 0 +OP4 E02BFC 0 +OP4 E02BFD 0 +OP4 E02BFE 0 +OP4 E02BFF 0 +OP4 E02C00 0 +OP4 E02C01 0 +OP4 E02C02 0 +OP4 E02C03 0 +OP4 E02C04 0 +OP4 E02C05 0 +OP4 E02C06 0 +OP4 E02C07 0 +OP4 E02C08 0 +OP4 E02C09 0 +OP4 E02C0A 0 +OP4 E02C0B 0 +OP4 E02C0C 0 +OP4 E02C0D 0 +OP4 E02C0E 0 +OP4 E02C0F 0 +OP4 E02C10 0 +OP4 E02C11 0 +OP4 E02C12 0 +OP4 E02C13 0 +OP4 E02C14 0 +OP4 E02C15 0 +OP4 E02C16 0 +OP4 E02C17 0 +OP4 E02C18 0 +OP4 E02C19 0 +OP4 E02C1A 0 +OP4 E02C1B 0 +OP4 E02C1C 0 +OP4 E02C1D 0 +OP4 E02C1E 0 +OP4 E02C1F 0 +OP4 E02C20 0 +OP4 E02C21 0 +OP4 E02C22 0 +OP4 E02C23 0 +OP4 E02C24 0 +OP4 E02C25 0 +OP4 E02C26 0 +OP4 E02C27 0 +OP4 E02C28 0 +OP4 E02C29 0 +OP4 E02C2A 0 +OP4 E02C2B 0 +OP4 E02C2C 0 +OP4 E02C2D 0 +OP4 E02C2E 0 +OP4 E02C2F 0 +OP4 E02C30 0 +OP4 E02C31 0 +OP4 E02C32 0 +OP4 E02C33 0 +OP4 E02C34 0 +OP4 E02C35 0 +OP4 E02C36 0 +OP4 E02C37 0 +OP4 E02C38 0 +OP4 E02C39 0 +OP4 E02C3A 0 +OP4 E02C3B 0 +OP4 E02C3C 0 +OP4 E02C3D 0 +OP4 E02C3E 0 +OP4 E02C3F 0 +OP4 E02C40 0 +OP4 E02C41 0 +OP4 E02C42 0 +OP4 E02C43 0 +OP4 E02C44 0 +OP4 E02C45 0 +OP4 E02C46 0 +OP4 E02C47 0 +OP4 E02C48 0 +OP4 E02C49 0 +OP4 E02C4A 0 +OP4 E02C4B 0 +OP4 E02C4C 0 +OP4 E02C4D 0 +OP4 E02C4E 0 +OP4 E02C4F 0 +OP4 E02C50 0 +OP4 E02C51 0 +OP4 E02C52 0 +OP4 E02C53 0 +OP4 E02C54 0 +OP4 E02C55 0 +OP4 E02C56 0 +OP4 E02C57 0 +OP4 E02C58 0 +OP4 E02C59 0 +OP4 E02C5A 0 +OP4 E02C5B 0 +OP4 E02C5C 0 +OP4 E02C5D 0 +OP4 E02C5E 0 +OP4 E02C5F 0 +OP4 E02C60 0 +OP4 E02C61 0 +OP4 E02C62 0 +OP4 E02C63 0 +OP4 E02C64 0 +OP4 E02C65 0 +OP4 E02C66 0 +OP4 E02C67 0 +OP4 E02C68 0 +OP4 E02C69 0 +OP4 E02C6A 0 +OP4 E02C6B 0 +OP4 E02C6C 0 +OP4 E02C6D 0 +OP4 E02C6E 0 +OP4 E02C6F 0 +OP4 E02C70 0 +OP4 E02C71 0 +OP4 E02C72 0 +OP4 E02C73 0 +OP4 E02C74 0 +OP4 E02C75 0 +OP4 E02C76 0 +OP4 E02C77 0 +OP4 E02C78 0 +OP4 E02C79 0 +OP4 E02C7A 0 +OP4 E02C7B 0 +OP4 E02C7C 0 +OP4 E02C7D 0 +OP4 E02C7E 0 +OP4 E02C7F 0 +OP4 E02C80 0 +OP4 E02C81 0 +OP4 E02C82 0 +OP4 E02C83 0 +OP4 E02C84 0 +OP4 E02C85 0 +OP4 E02C86 0 +OP4 E02C87 0 +OP4 E02C88 0 +OP4 E02C89 0 +OP4 E02C8A 0 +OP4 E02C8B 0 +OP4 E02C8C 0 +OP4 E02C8D 0 +OP4 E02C8E 0 +OP4 E02C8F 0 +OP4 E02C90 0 +OP4 E02C91 0 +OP4 E02C92 0 +OP4 E02C93 0 +OP4 E02C94 0 +OP4 E02C95 0 +OP4 E02C96 0 +OP4 E02C97 0 +OP4 E02C98 0 +OP4 E02C99 0 +OP4 E02C9A 0 +OP4 E02C9B 0 +OP4 E02C9C 0 +OP4 E02C9D 0 +OP4 E02C9E 0 +OP4 E02C9F 0 +OP4 E02CA0 0 +OP4 E02CA1 0 +OP4 E02CA2 0 +OP4 E02CA3 0 +OP4 E02CA4 0 +OP4 E02CA5 0 +OP4 E02CA6 0 +OP4 E02CA7 0 +OP4 E02CA8 0 +OP4 E02CA9 0 +OP4 E02CAA 0 +OP4 E02CAB 0 +OP4 E02CAC 0 +OP4 E02CAD 0 +OP4 E02CAE 0 +OP4 E02CAF 0 +OP4 E02CB0 0 +OP4 E02CB1 0 +OP4 E02CB2 0 +OP4 E02CB3 0 +OP4 E02CB4 0 +OP4 E02CB5 0 +OP4 E02CB6 0 +OP4 E02CB7 0 +OP4 E02CB8 0 +OP4 E02CB9 0 +OP4 E02CBA 0 +OP4 E02CBB 0 +OP4 E02CBC 0 +OP4 E02CBD 0 +OP4 E02CBE 0 +OP4 E02CBF 0 +OP4 E02CC0 0 +OP4 E02CC1 0 +OP4 E02CC2 0 +OP4 E02CC3 0 +OP4 E02CC4 0 +OP4 E02CC5 0 +OP4 E02CC6 0 +OP4 E02CC7 0 +OP4 E02CC8 0 +OP4 E02CC9 0 +OP4 E02CCA 0 +OP4 E02CCB 0 +OP4 E02CCC 0 +OP4 E02CCD 0 +OP4 E02CCE 0 +OP4 E02CCF 0 +OP4 E02CD0 0 +OP4 E02CD1 0 +OP4 E02CD2 0 +OP4 E02CD3 0 +OP4 E02CD4 0 +OP4 E02CD5 0 +OP4 E02CD6 0 +OP4 E02CD7 0 +OP4 E02CD8 0 +OP4 E02CD9 0 +OP4 E02CDA 0 +OP4 E02CDB 0 +OP4 E02CDC 0 +OP4 E02CDD 0 +OP4 E02CDE 0 +OP4 E02CDF 0 +OP4 E02CE0 0 +OP4 E02CE1 0 +OP4 E02CE2 0 +OP4 E02CE3 0 +OP4 E02CE4 0 +OP4 E02CE5 0 +OP4 E02CE6 0 +OP4 E02CE7 0 +OP4 E02CE8 0 +OP4 E02CE9 0 +OP4 E02CEA 0 +OP4 E02CEB 0 +OP4 E02CEC 0 +OP4 E02CED 0 +OP4 E02CEE 0 +OP4 E02CEF 0 +OP4 E02CF0 0 +OP4 E02CF1 0 +OP4 E02CF2 0 +OP4 E02CF3 0 +OP4 E02CF4 0 +OP4 E02CF5 0 +OP4 E02CF6 0 +OP4 E02CF7 0 +OP4 E02CF8 0 +OP4 E02CF9 0 +OP4 E02CFA 0 +OP4 E02CFB 0 +OP4 E02CFC 0 +OP4 E02CFD 0 +OP4 E02CFE 0 +OP4 E02CFF 0 +OP4 E02D00 0 +OP4 E02D01 0 +OP4 E02D02 0 +OP4 E02D03 0 +OP4 E02D04 0 +OP4 E02D05 0 +OP4 E02D06 0 +OP4 E02D07 0 +OP4 E02D08 0 +OP4 E02D09 0 +OP4 E02D0A 0 +OP4 E02D0B 0 +OP4 E02D0C 0 +OP4 E02D0D 0 +OP4 E02D0E 0 +OP4 E02D0F 0 +OP4 E02D10 0 +OP4 E02D11 0 +OP4 E02D12 0 +OP4 E02D13 0 +OP4 E02D14 0 +OP4 E02D15 0 +OP4 E02D16 0 +OP4 E02D17 0 +OP4 E02D18 0 +OP4 E02D19 0 +OP4 E02D1A 0 +OP4 E02D1B 0 +OP4 E02D1C 0 +OP4 E02D1D 0 +OP4 E02D1E 0 +OP4 E02D1F 0 +OP4 E02D20 0 +OP4 E02D21 0 +OP4 E02D22 0 +OP4 E02D23 0 +OP4 E02D24 0 +OP4 E02D25 0 +OP4 E02D26 0 +OP4 E02D27 0 +OP4 E02D28 0 +OP4 E02D29 0 +OP4 E02D2A 0 +OP4 E02D2B 0 +OP4 E02D2C 0 +OP4 E02D2D 0 +OP4 E02D2E 0 +OP4 E02D2F 0 +OP4 E02D30 0 +OP4 E02D31 0 +OP4 E02D32 0 +OP4 E02D33 0 +OP4 E02D34 0 +OP4 E02D35 0 +OP4 E02D36 0 +OP4 E02D37 0 +OP4 E02D38 0 +OP4 E02D39 0 +OP4 E02D3A 0 +OP4 E02D3B 0 +OP4 E02D3C 0 +OP4 E02D3D 0 +OP4 E02D3E 0 +OP4 E02D3F 0 +OP4 E02D40 0 +OP4 E02D41 0 +OP4 E02D42 0 +OP4 E02D43 0 +OP4 E02D44 0 +OP4 E02D45 0 +OP4 E02D46 0 +OP4 E02D47 0 +OP4 E02D48 0 +OP4 E02D49 0 +OP4 E02D4A 0 +OP4 E02D4B 0 +OP4 E02D4C 0 +OP4 E02D4D 0 +OP4 E02D4E 0 +OP4 E02D4F 0 +OP4 E02D50 0 +OP4 E02D51 0 +OP4 E02D52 0 +OP4 E02D53 0 +OP4 E02D54 0 +OP4 E02D55 0 +OP4 E02D56 0 +OP4 E02D57 0 +OP4 E02D58 0 +OP4 E02D59 0 +OP4 E02D5A 0 +OP4 E02D5B 0 +OP4 E02D5C 0 +OP4 E02D5D 0 +OP4 E02D5E 0 +OP4 E02D5F 0 +OP4 E02D60 0 +OP4 E02D61 0 +OP4 E02D62 0 +OP4 E02D63 0 +OP4 E02D64 0 +OP4 E02D65 0 +OP4 E02D66 0 +OP4 E02D67 0 +OP4 E02D68 0 +OP4 E02D69 0 +OP4 E02D6A 0 +OP4 E02D6B 0 +OP4 E02D6C 0 +OP4 E02D6D 0 +OP4 E02D6E 0 +OP4 E02D6F 0 +OP4 E02D70 0 +OP4 E02D71 0 +OP4 E02D72 0 +OP4 E02D73 0 +OP4 E02D74 0 +OP4 E02D75 0 +OP4 E02D76 0 +OP4 E02D77 0 +OP4 E02D78 0 +OP4 E02D79 0 +OP4 E02D7A 0 +OP4 E02D7B 0 +OP4 E02D7C 0 +OP4 E02D7D 0 +OP4 E02D7E 0 +OP4 E02D7F 0 +OP4 E02D80 0 +OP4 E02D81 0 +OP4 E02D82 0 +OP4 E02D83 0 +OP4 E02D84 0 +OP4 E02D85 0 +OP4 E02D86 0 +OP4 E02D87 0 +OP4 E02D88 0 +OP4 E02D89 0 +OP4 E02D8A 0 +OP4 E02D8B 0 +OP4 E02D8C 0 +OP4 E02D8D 0 +OP4 E02D8E 0 +OP4 E02D8F 0 +OP4 E02D90 0 +OP4 E02D91 0 +OP4 E02D92 0 +OP4 E02D93 0 +OP4 E02D94 0 +OP4 E02D95 0 +OP4 E02D96 0 +OP4 E02D97 0 +OP4 E02D98 0 +OP4 E02D99 0 +OP4 E02D9A 0 +OP4 E02D9B 0 +OP4 E02D9C 0 +OP4 E02D9D 0 +OP4 E02D9E 0 +OP4 E02D9F 0 +OP4 E02DA0 0 +OP4 E02DA1 0 +OP4 E02DA2 0 +OP4 E02DA3 0 +OP4 E02DA4 0 +OP4 E02DA5 0 +OP4 E02DA6 0 +OP4 E02DA7 0 +OP4 E02DA8 0 +OP4 E02DA9 0 +OP4 E02DAA 0 +OP4 E02DAB 0 +OP4 E02DAC 0 +OP4 E02DAD 0 +OP4 E02DAE 0 +OP4 E02DAF 0 +OP4 E02DB0 0 +OP4 E02DB1 0 +OP4 E02DB2 0 +OP4 E02DB3 0 +OP4 E02DB4 0 +OP4 E02DB5 0 +OP4 E02DB6 0 +OP4 E02DB7 0 +OP4 E02DB8 0 +OP4 E02DB9 0 +OP4 E02DBA 0 +OP4 E02DBB 0 +OP4 E02DBC 0 +OP4 E02DBD 0 +OP4 E02DBE 0 +OP4 E02DBF 0 +OP4 E02DC0 0 +OP4 E02DC1 0 +OP4 E02DC2 0 +OP4 E02DC3 0 +OP4 E02DC4 0 +OP4 E02DC5 0 +OP4 E02DC6 0 +OP4 E02DC7 0 +OP4 E02DC8 0 +OP4 E02DC9 0 +OP4 E02DCA 0 +OP4 E02DCB 0 +OP4 E02DCC 0 +OP4 E02DCD 0 +OP4 E02DCE 0 +OP4 E02DCF 0 +OP4 E02DD0 0 +OP4 E02DD1 0 +OP4 E02DD2 0 +OP4 E02DD3 0 +OP4 E02DD4 0 +OP4 E02DD5 0 +OP4 E02DD6 0 +OP4 E02DD7 0 +OP4 E02DD8 0 +OP4 E02DD9 0 +OP4 E02DDA 0 +OP4 E02DDB 0 +OP4 E02DDC 0 +OP4 E02DDD 0 +OP4 E02DDE 0 +OP4 E02DDF 0 +OP4 E02DE0 0 +OP4 E02DE1 0 +OP4 E02DE2 0 +OP4 E02DE3 0 +OP4 E02DE4 0 +OP4 E02DE5 0 +OP4 E02DE6 0 +OP4 E02DE7 0 +OP4 E02DE8 0 +OP4 E02DE9 0 +OP4 E02DEA 0 +OP4 E02DEB 0 +OP4 E02DEC 0 +OP4 E02DED 0 +OP4 E02DEE 0 +OP4 E02DEF 0 +OP4 E02DF0 0 +OP4 E02DF1 0 +OP4 E02DF2 0 +OP4 E02DF3 0 +OP4 E02DF4 0 +OP4 E02DF5 0 +OP4 E02DF6 0 +OP4 E02DF7 0 +OP4 E02DF8 0 +OP4 E02DF9 0 +OP4 E02DFA 0 +OP4 E02DFB 0 +OP4 E02DFC 0 +OP4 E02DFD 0 +OP4 E02DFE 0 +OP4 E02DFF 0 +OP4 E02E00 0 +OP4 E02E01 0 +OP4 E02E02 0 +OP4 E02E03 0 +OP4 E02E04 0 +OP4 E02E05 0 +OP4 E02E06 0 +OP4 E02E07 0 +OP4 E02E08 0 +OP4 E02E09 0 +OP4 E02E0A 0 +OP4 E02E0B 0 +OP4 E02E0C 0 +OP4 E02E0D 0 +OP4 E02E0E 0 +OP4 E02E0F 0 +OP4 E02E10 0 +OP4 E02E11 0 +OP4 E02E12 0 +OP4 E02E13 0 +OP4 E02E14 0 +OP4 E02E15 0 +OP4 E02E16 0 +OP4 E02E17 0 +OP4 E02E18 0 +OP4 E02E19 0 +OP4 E02E1A 0 +OP4 E02E1B 0 +OP4 E02E1C 0 +OP4 E02E1D 0 +OP4 E02E1E 0 +OP4 E02E1F 0 +OP4 E02E20 0 +OP4 E02E21 0 +OP4 E02E22 0 +OP4 E02E23 0 +OP4 E02E24 0 +OP4 E02E25 0 +OP4 E02E26 0 +OP4 E02E27 0 +OP4 E02E28 0 +OP4 E02E29 0 +OP4 E02E2A 0 +OP4 E02E2B 0 +OP4 E02E2C 0 +OP4 E02E2D 0 +OP4 E02E2E 0 +OP4 E02E2F 0 +OP4 E02E30 0 +OP4 E02E31 0 +OP4 E02E32 0 +OP4 E02E33 0 +OP4 E02E34 0 +OP4 E02E35 0 +OP4 E02E36 0 +OP4 E02E37 0 +OP4 E02E38 0 +OP4 E02E39 0 +OP4 E02E3A 0 +OP4 E02E3B 0 +OP4 E02E3C 0 +OP4 E02E3D 0 +OP4 E02E3E 0 +OP4 E02E3F 0 +OP4 E02E40 0 +OP4 E02E41 0 +OP4 E02E42 0 +OP4 E02E43 0 +OP4 E02E44 0 +OP4 E02E45 0 +OP4 E02E46 0 +OP4 E02E47 0 +OP4 E02E48 0 +OP4 E02E49 0 +OP4 E02E4A 0 +OP4 E02E4B 0 +OP4 E02E4C 0 +OP4 E02E4D 0 +OP4 E02E4E 0 +OP4 E02E4F 0 +OP4 E02E50 0 +OP4 E02E51 0 +OP4 E02E52 0 +OP4 E02E53 0 +OP4 E02E54 0 +OP4 E02E55 0 +OP4 E02E56 0 +OP4 E02E57 0 +OP4 E02E58 0 +OP4 E02E59 0 +OP4 E02E5A 0 +OP4 E02E5B 0 +OP4 E02E5C 0 +OP4 E02E5D 0 +OP4 E02E5E 0 +OP4 E02E5F 0 +OP4 E02E60 0 +OP4 E02E61 0 +OP4 E02E62 0 +OP4 E02E63 0 +OP4 E02E64 0 +OP4 E02E65 0 +OP4 E02E66 0 +OP4 E02E67 0 +OP4 E02E68 0 +OP4 E02E69 0 +OP4 E02E6A 0 +OP4 E02E6B 0 +OP4 E02E6C 0 +OP4 E02E6D 0 +OP4 E02E6E 0 +OP4 E02E6F 0 +OP4 E02E70 0 +OP4 E02E71 0 +OP4 E02E72 0 +OP4 E02E73 0 +OP4 E02E74 0 +OP4 E02E75 0 +OP4 E02E76 0 +OP4 E02E77 0 +OP4 E02E78 0 +OP4 E02E79 0 +OP4 E02E7A 0 +OP4 E02E7B 0 +OP4 E02E7C 0 +OP4 E02E7D 0 +OP4 E02E7E 0 +OP4 E02E7F 0 +OP4 E02E80 0 +OP4 E02E81 0 +OP4 E02E82 0 +OP4 E02E83 0 +OP4 E02E84 0 +OP4 E02E85 0 +OP4 E02E86 0 +OP4 E02E87 0 +OP4 E02E88 0 +OP4 E02E89 0 +OP4 E02E8A 0 +OP4 E02E8B 0 +OP4 E02E8C 0 +OP4 E02E8D 0 +OP4 E02E8E 0 +OP4 E02E8F 0 +OP4 E02E90 0 +OP4 E02E91 0 +OP4 E02E92 0 +OP4 E02E93 0 +OP4 E02E94 0 +OP4 E02E95 0 +OP4 E02E96 0 +OP4 E02E97 0 +OP4 E02E98 0 +OP4 E02E99 0 +OP4 E02E9A 0 +OP4 E02E9B 0 +OP4 E02E9C 0 +OP4 E02E9D 0 +OP4 E02E9E 0 +OP4 E02E9F 0 +OP4 E02EA0 0 +OP4 E02EA1 0 +OP4 E02EA2 0 +OP4 E02EA3 0 +OP4 E02EA4 0 +OP4 E02EA5 0 +OP4 E02EA6 0 +OP4 E02EA7 0 +OP4 E02EA8 0 +OP4 E02EA9 0 +OP4 E02EAA 0 +OP4 E02EAB 0 +OP4 E02EAC 0 +OP4 E02EAD 0 +OP4 E02EAE 0 +OP4 E02EAF 0 +OP4 E02EB0 0 +OP4 E02EB1 0 +OP4 E02EB2 0 +OP4 E02EB3 0 +OP4 E02EB4 0 +OP4 E02EB5 0 +OP4 E02EB6 0 +OP4 E02EB7 0 +OP4 E02EB8 0 +OP4 E02EB9 0 +OP4 E02EBA 0 +OP4 E02EBB 0 +OP4 E02EBC 0 +OP4 E02EBD 0 +OP4 E02EBE 0 +OP4 E02EBF 0 +OP4 E02EC0 0 +OP4 E02EC1 0 +OP4 E02EC2 0 +OP4 E02EC3 0 +OP4 E02EC4 0 +OP4 E02EC5 0 +OP4 E02EC6 0 +OP4 E02EC7 0 +OP4 E02EC8 0 +OP4 E02EC9 0 +OP4 E02ECA 0 +OP4 E02ECB 0 +OP4 E02ECC 0 +OP4 E02ECD 0 +OP4 E02ECE 0 +OP4 E02ECF 0 +OP4 E02ED0 0 +OP4 E02ED1 0 +OP4 E02ED2 0 +OP4 E02ED3 0 +OP4 E02ED4 0 +OP4 E02ED5 0 +OP4 E02ED6 0 +OP4 E02ED7 0 +OP4 E02ED8 0 +OP4 E02ED9 0 +OP4 E02EDA 0 +OP4 E02EDB 0 +OP4 E02EDC 0 +OP4 E02EDD 0 +OP4 E02EDE 0 +OP4 E02EDF 0 +OP4 E02EE0 0 +OP4 E02EE1 0 +OP4 E02EE2 0 +OP4 E02EE3 0 +OP4 E02EE4 0 +OP4 E02EE5 0 +OP4 E02EE6 0 +OP4 E02EE7 0 +OP4 E02EE8 0 +OP4 E02EE9 0 +OP4 E02EEA 0 +OP4 E02EEB 0 +OP4 E02EEC 0 +OP4 E02EED 0 +OP4 E02EEE 0 +OP4 E02EEF 0 +OP4 E02EF0 0 +OP4 E02EF1 0 +OP4 E02EF2 0 +OP4 E02EF3 0 +OP4 E02EF4 0 +OP4 E02EF5 0 +OP4 E02EF6 0 +OP4 E02EF7 0 +OP4 E02EF8 0 +OP4 E02EF9 0 +OP4 E02EFA 0 +OP4 E02EFB 0 +OP4 E02EFC 0 +OP4 E02EFD 0 +OP4 E02EFE 0 +OP4 E02EFF 0 +OP4 E02F00 0 +OP4 E02F01 0 +OP4 E02F02 0 +OP4 E02F03 0 +OP4 E02F04 0 +OP4 E02F05 0 +OP4 E02F06 0 +OP4 E02F07 0 +OP4 E02F08 0 +OP4 E02F09 0 +OP4 E02F0A 0 +OP4 E02F0B 0 +OP4 E02F0C 0 +OP4 E02F0D 0 +OP4 E02F0E 0 +OP4 E02F0F 0 +OP4 E02F10 0 +OP4 E02F11 0 +OP4 E02F12 0 +OP4 E02F13 0 +OP4 E02F14 0 +OP4 E02F15 0 +OP4 E02F16 0 +OP4 E02F17 0 +OP4 E02F18 0 +OP4 E02F19 0 +OP4 E02F1A 0 +OP4 E02F1B 0 +OP4 E02F1C 0 +OP4 E02F1D 0 +OP4 E02F1E 0 +OP4 E02F1F 0 +OP4 E02F20 0 +OP4 E02F21 0 +OP4 E02F22 0 +OP4 E02F23 0 +OP4 E02F24 0 +OP4 E02F25 0 +OP4 E02F26 0 +OP4 E02F27 0 +OP4 E02F28 0 +OP4 E02F29 0 +OP4 E02F2A 0 +OP4 E02F2B 0 +OP4 E02F2C 0 +OP4 E02F2D 0 +OP4 E02F2E 0 +OP4 E02F2F 0 +OP4 E02F30 0 +OP4 E02F31 0 +OP4 E02F32 0 +OP4 E02F33 0 +OP4 E02F34 0 +OP4 E02F35 0 +OP4 E02F36 0 +OP4 E02F37 0 +OP4 E02F38 0 +OP4 E02F39 0 +OP4 E02F3A 0 +OP4 E02F3B 0 +OP4 E02F3C 0 +OP4 E02F3D 0 +OP4 E02F3E 0 +OP4 E02F3F 0 +OP4 E02F40 0 +OP4 E02F41 0 +OP4 E02F42 0 +OP4 E02F43 0 +OP4 E02F44 0 +OP4 E02F45 0 +OP4 E02F46 0 +OP4 E02F47 0 +OP4 E02F48 0 +OP4 E02F49 0 +OP4 E02F4A 0 +OP4 E02F4B 0 +OP4 E02F4C 0 +OP4 E02F4D 0 +OP4 E02F4E 0 +OP4 E02F4F 0 +OP4 E02F50 0 +OP4 E02F51 0 +OP4 E02F52 0 +OP4 E02F53 0 +OP4 E02F54 0 +OP4 E02F55 0 +OP4 E02F56 0 +OP4 E02F57 0 +OP4 E02F58 0 +OP4 E02F59 0 +OP4 E02F5A 0 +OP4 E02F5B 0 +OP4 E02F5C 0 +OP4 E02F5D 0 +OP4 E02F5E 0 +OP4 E02F5F 0 +OP4 E02F60 0 +OP4 E02F61 0 +OP4 E02F62 0 +OP4 E02F63 0 +OP4 E02F64 0 +OP4 E02F65 0 +OP4 E02F66 0 +OP4 E02F67 0 +OP4 E02F68 0 +OP4 E02F69 0 +OP4 E02F6A 0 +OP4 E02F6B 0 +OP4 E02F6C 0 +OP4 E02F6D 0 +OP4 E02F6E 0 +OP4 E02F6F 0 +OP4 E02F70 0 +OP4 E02F71 0 +OP4 E02F72 0 +OP4 E02F73 0 +OP4 E02F74 0 +OP4 E02F75 0 +OP4 E02F76 0 +OP4 E02F77 0 +OP4 E02F78 0 +OP4 E02F79 0 +OP4 E02F7A 0 +OP4 E02F7B 0 +OP4 E02F7C 0 +OP4 E02F7D 0 +OP4 E02F7E 0 +OP4 E02F7F 0 +OP4 E02F80 0 +OP4 E02F81 0 +OP4 E02F82 0 +OP4 E02F83 0 +OP4 E02F84 0 +OP4 E02F85 0 +OP4 E02F86 0 +OP4 E02F87 0 +OP4 E02F88 0 +OP4 E02F89 0 +OP4 E02F8A 0 +OP4 E02F8B 0 +OP4 E02F8C 0 +OP4 E02F8D 0 +OP4 E02F8E 0 +OP4 E02F8F 0 +OP4 E02F90 0 +OP4 E02F91 0 +OP4 E02F92 0 +OP4 E02F93 0 +OP4 E02F94 0 +OP4 E02F95 0 +OP4 E02F96 0 +OP4 E02F97 0 +OP4 E02F98 0 +OP4 E02F99 0 +OP4 E02F9A 0 +OP4 E02F9B 0 +OP4 E02F9C 0 +OP4 E02F9D 0 +OP4 E02F9E 0 +OP4 E02F9F 0 +OP4 E02FA0 0 +OP4 E02FA1 0 +OP4 E02FA2 0 +OP4 E02FA3 0 +OP4 E02FA4 0 +OP4 E02FA5 0 +OP4 E02FA6 0 +OP4 E02FA7 0 +OP4 E02FA8 0 +OP4 E02FA9 0 +OP4 E02FAA 0 +OP4 E02FAB 0 +OP4 E02FAC 0 +OP4 E02FAD 0 +OP4 E02FAE 0 +OP4 E02FAF 0 +OP4 E02FB0 0 +OP4 E02FB1 0 +OP4 E02FB2 0 +OP4 E02FB3 0 +OP4 E02FB4 0 +OP4 E02FB5 0 +OP4 E02FB6 0 +OP4 E02FB7 0 +OP4 E02FB8 0 +OP4 E02FB9 0 +OP4 E02FBA 0 +OP4 E02FBB 0 +OP4 E02FBC 0 +OP4 E02FBD 0 +OP4 E02FBE 0 +OP4 E02FBF 0 +OP4 E02FC0 0 +OP4 E02FC1 0 +OP4 E02FC2 0 +OP4 E02FC3 0 +OP4 E02FC4 0 +OP4 E02FC5 0 +OP4 E02FC6 0 +OP4 E02FC7 0 +OP4 E02FC8 0 +OP4 E02FC9 0 +OP4 E02FCA 0 +OP4 E02FCB 0 +OP4 E02FCC 0 +OP4 E02FCD 0 +OP4 E02FCE 0 +OP4 E02FCF 0 +OP4 E02FD0 0 +OP4 E02FD1 0 +OP4 E02FD2 0 +OP4 E02FD3 0 +OP4 E02FD4 0 +OP4 E02FD5 0 +OP4 E02FD6 0 +OP4 E02FD7 0 +OP4 E02FD8 0 +OP4 E02FD9 0 +OP4 E02FDA 0 +OP4 E02FDB 0 +OP4 E02FDC 0 +OP4 E02FDD 0 +OP4 E02FDE 0 +OP4 E02FDF 0 +OP4 E02FE0 0 +OP4 E02FE1 0 +OP4 E02FE2 0 +OP4 E02FE3 0 +OP4 E02FE4 0 +OP4 E02FE5 0 +OP4 E02FE6 0 +OP4 E02FE7 0 +OP4 E02FE8 0 +OP4 E02FE9 0 +OP4 E02FEA 0 +OP4 E02FEB 0 +OP4 E02FEC 0 +OP4 E02FED 0 +OP4 E02FEE 0 +OP4 E02FEF 0 +OP4 E02FF0 0 +OP4 E02FF1 0 +OP4 E02FF2 0 +OP4 E02FF3 0 +OP4 E02FF4 0 +OP4 E02FF5 0 +OP4 E02FF6 0 +OP4 E02FF7 0 +OP4 E02FF8 0 +OP4 E02FF9 0 +OP4 E02FFA 0 +OP4 E02FFB 0 +OP4 E02FFC 0 +OP4 E02FFD 0 +OP4 E02FFE 0 +OP4 E02FFF 0 +OP4 E03000 0 +OP4 E03001 0 +OP4 E03002 0 +OP4 E03003 0 +OP4 E03004 0 +OP4 E03005 0 +OP4 E03006 0 +OP4 E03007 0 +OP4 E03008 0 +OP4 E03009 0 +OP4 E0300A 0 +OP4 E0300B 0 +OP4 E0300C 0 +OP4 E0300D 0 +OP4 E0300E 0 +OP4 E0300F 0 +OP4 E03010 0 +OP4 E03011 0 +OP4 E03012 0 +OP4 E03013 0 +OP4 E03014 0 +OP4 E03015 0 +OP4 E03016 0 +OP4 E03017 0 +OP4 E03018 0 +OP4 E03019 0 +OP4 E0301A 0 +OP4 E0301B 0 +OP4 E0301C 0 +OP4 E0301D 0 +OP4 E0301E 0 +OP4 E0301F 0 +OP4 E03020 0 +OP4 E03021 0 +OP4 E03022 0 +OP4 E03023 0 +OP4 E03024 0 +OP4 E03025 0 +OP4 E03026 0 +OP4 E03027 0 +OP4 E03028 0 +OP4 E03029 0 +OP4 E0302A 0 +OP4 E0302B 0 +OP4 E0302C 0 +OP4 E0302D 0 +OP4 E0302E 0 +OP4 E0302F 0 +OP4 E03030 0 +OP4 E03031 0 +OP4 E03032 0 +OP4 E03033 0 +OP4 E03034 0 +OP4 E03035 0 +OP4 E03036 0 +OP4 E03037 0 +OP4 E03038 0 +OP4 E03039 0 +OP4 E0303A 0 +OP4 E0303B 0 +OP4 E0303C 0 +OP4 E0303D 0 +OP4 E0303E 0 +OP4 E0303F 0 +OP4 E03040 0 +OP4 E03041 0 +OP4 E03042 0 +OP4 E03043 0 +OP4 E03044 0 +OP4 E03045 0 +OP4 E03046 0 +OP4 E03047 0 +OP4 E03048 0 +OP4 E03049 0 +OP4 E0304A 0 +OP4 E0304B 0 +OP4 E0304C 0 +OP4 E0304D 0 +OP4 E0304E 0 +OP4 E0304F 0 +OP4 E03050 0 +OP4 E03051 0 +OP4 E03052 0 +OP4 E03053 0 +OP4 E03054 0 +OP4 E03055 0 +OP4 E03056 0 +OP4 E03057 0 +OP4 E03058 0 +OP4 E03059 0 +OP4 E0305A 0 +OP4 E0305B 0 +OP4 E0305C 0 +OP4 E0305D 0 +OP4 E0305E 0 +OP4 E0305F 0 +OP4 E03060 0 +OP4 E03061 0 +OP4 E03062 0 +OP4 E03063 0 +OP4 E03064 0 +OP4 E03065 0 +OP4 E03066 0 +OP4 E03067 0 +OP4 E03068 0 +OP4 E03069 0 +OP4 E0306A 0 +OP4 E0306B 0 +OP4 E0306C 0 +OP4 E0306D 0 +OP4 E0306E 0 +OP4 E0306F 0 +OP4 E03070 0 +OP4 E03071 0 +OP4 E03072 0 +OP4 E03073 0 +OP4 E03074 0 +OP4 E03075 0 +OP4 E03076 0 +OP4 E03077 0 +OP4 E03078 0 +OP4 E03079 0 +OP4 E0307A 0 +OP4 E0307B 0 +OP4 E0307C 0 +OP4 E0307D 0 +OP4 E0307E 0 +OP4 E0307F 0 +OP4 E03080 0 +OP4 E03081 0 +OP4 E03082 0 +OP4 E03083 0 +OP4 E03084 0 +OP4 E03085 0 +OP4 E03086 0 +OP4 E03087 0 +OP4 E03088 0 +OP4 E03089 0 +OP4 E0308A 0 +OP4 E0308B 0 +OP4 E0308C 0 +OP4 E0308D 0 +OP4 E0308E 0 +OP4 E0308F 0 +OP4 E03090 0 +OP4 E03091 0 +OP4 E03092 0 +OP4 E03093 0 +OP4 E03094 0 +OP4 E03095 0 +OP4 E03096 0 +OP4 E03097 0 +OP4 E03098 0 +OP4 E03099 0 +OP4 E0309A 0 +OP4 E0309B 0 +OP4 E0309C 0 +OP4 E0309D 0 +OP4 E0309E 0 +OP4 E0309F 0 +OP4 E030A0 0 +OP4 E030A1 0 +OP4 E030A2 0 +OP4 E030A3 0 +OP4 E030A4 0 +OP4 E030A5 0 +OP4 E030A6 0 +OP4 E030A7 0 +OP4 E030A8 0 +OP4 E030A9 0 +OP4 E030AA 0 +OP4 E030AB 0 +OP4 E030AC 0 +OP4 E030AD 0 +OP4 E030AE 0 +OP4 E030AF 0 +OP4 E030B0 0 +OP4 E030B1 0 +OP4 E030B2 0 +OP4 E030B3 0 +OP4 E030B4 0 +OP4 E030B5 0 +OP4 E030B6 0 +OP4 E030B7 0 +OP4 E030B8 0 +OP4 E030B9 0 +OP4 E030BA 0 +OP4 E030BB 0 +OP4 E030BC 0 +OP4 E030BD 0 +OP4 E030BE 0 +OP4 E030BF 0 +OP4 E030C0 0 +OP4 E030C1 0 +OP4 E030C2 0 +OP4 E030C3 0 +OP4 E030C4 0 +OP4 E030C5 0 +OP4 E030C6 0 +OP4 E030C7 0 +OP4 E030C8 0 +OP4 E030C9 0 +OP4 E030CA 0 +OP4 E030CB 0 +OP4 E030CC 0 +OP4 E030CD 0 +OP4 E030CE 0 +OP4 E030CF 0 +OP4 E030D0 0 +OP4 E030D1 0 +OP4 E030D2 0 +OP4 E030D3 0 +OP4 E030D4 0 +OP4 E030D5 0 +OP4 E030D6 0 +OP4 E030D7 0 +OP4 E030D8 0 +OP4 E030D9 0 +OP4 E030DA 0 +OP4 E030DB 0 +OP4 E030DC 0 +OP4 E030DD 0 +OP4 E030DE 0 +OP4 E030DF 0 +OP4 E030E0 0 +OP4 E030E1 0 +OP4 E030E2 0 +OP4 E030E3 0 +OP4 E030E4 0 +OP4 E030E5 0 +OP4 E030E6 0 +OP4 E030E7 0 +OP4 E030E8 0 +OP4 E030E9 0 +OP4 E030EA 0 +OP4 E030EB 0 +OP4 E030EC 0 +OP4 E030ED 0 +OP4 E030EE 0 +OP4 E030EF 0 +OP4 E030F0 0 +OP4 E030F1 0 +OP4 E030F2 0 +OP4 E030F3 0 +OP4 E030F4 0 +OP4 E030F5 0 +OP4 E030F6 0 +OP4 E030F7 0 +OP4 E030F8 0 +OP4 E030F9 0 +OP4 E030FA 0 +OP4 E030FB 0 +OP4 E030FC 0 +OP4 E030FD 0 +OP4 E030FE 0 +OP4 E030FF 0 +OP4 E03100 0 +OP4 E03101 0 +OP4 E03102 0 +OP4 E03103 0 +OP4 E03104 0 +OP4 E03105 0 +OP4 E03106 0 +OP4 E03107 0 +OP4 E03108 0 +OP4 E03109 0 +OP4 E0310A 0 +OP4 E0310B 0 +OP4 E0310C 0 +OP4 E0310D 0 +OP4 E0310E 0 +OP4 E0310F 0 +OP4 E03110 0 +OP4 E03111 0 +OP4 E03112 0 +OP4 E03113 0 +OP4 E03114 0 +OP4 E03115 0 +OP4 E03116 0 +OP4 E03117 0 +OP4 E03118 0 +OP4 E03119 0 +OP4 E0311A 0 +OP4 E0311B 0 +OP4 E0311C 0 +OP4 E0311D 0 +OP4 E0311E 0 +OP4 E0311F 0 +OP4 E03120 0 +OP4 E03121 0 +OP4 E03122 0 +OP4 E03123 0 +OP4 E03124 0 +OP4 E03125 0 +OP4 E03126 0 +OP4 E03127 0 +OP4 E03128 0 +OP4 E03129 0 +OP4 E0312A 0 +OP4 E0312B 0 +OP4 E0312C 0 +OP4 E0312D 0 +OP4 E0312E 0 +OP4 E0312F 0 +OP4 E03130 0 +OP4 E03131 0 +OP4 E03132 0 +OP4 E03133 0 +OP4 E03134 0 +OP4 E03135 0 +OP4 E03136 0 +OP4 E03137 0 +OP4 E03138 0 +OP4 E03139 0 +OP4 E0313A 0 +OP4 E0313B 0 +OP4 E0313C 0 +OP4 E0313D 0 +OP4 E0313E 0 +OP4 E0313F 0 +OP4 E03140 0 +OP4 E03141 0 +OP4 E03142 0 +OP4 E03143 0 +OP4 E03144 0 +OP4 E03145 0 +OP4 E03146 0 +OP4 E03147 0 +OP4 E03148 0 +OP4 E03149 0 +OP4 E0314A 0 +OP4 E0314B 0 +OP4 E0314C 0 +OP4 E0314D 0 +OP4 E0314E 0 +OP4 E0314F 0 +OP4 E03150 0 +OP4 E03151 0 +OP4 E03152 0 +OP4 E03153 0 +OP4 E03154 0 +OP4 E03155 0 +OP4 E03156 0 +OP4 E03157 0 +OP4 E03158 0 +OP4 E03159 0 +OP4 E0315A 0 +OP4 E0315B 0 +OP4 E0315C 0 +OP4 E0315D 0 +OP4 E0315E 0 +OP4 E0315F 0 +OP4 E03160 0 +OP4 E03161 0 +OP4 E03162 0 +OP4 E03163 0 +OP4 E03164 0 +OP4 E03165 0 +OP4 E03166 0 +OP4 E03167 0 +OP4 E03168 0 +OP4 E03169 0 +OP4 E0316A 0 +OP4 E0316B 0 +OP4 E0316C 0 +OP4 E0316D 0 +OP4 E0316E 0 +OP4 E0316F 0 +OP4 E03170 0 +OP4 E03171 0 +OP4 E03172 0 +OP4 E03173 0 +OP4 E03174 0 +OP4 E03175 0 +OP4 E03176 0 +OP4 E03177 0 +OP4 E03178 0 +OP4 E03179 0 +OP4 E0317A 0 +OP4 E0317B 0 +OP4 E0317C 0 +OP4 E0317D 0 +OP4 E0317E 0 +OP4 E0317F 0 +OP4 E03180 0 +OP4 E03181 0 +OP4 E03182 0 +OP4 E03183 0 +OP4 E03184 0 +OP4 E03185 0 +OP4 E03186 0 +OP4 E03187 0 +OP4 E03188 0 +OP4 E03189 0 +OP4 E0318A 0 +OP4 E0318B 0 +OP4 E0318C 0 +OP4 E0318D 0 +OP4 E0318E 0 +OP4 E0318F 0 +OP4 E03190 0 +OP4 E03191 0 +OP4 E03192 0 +OP4 E03193 0 +OP4 E03194 0 +OP4 E03195 0 +OP4 E03196 0 +OP4 E03197 0 +OP4 E03198 0 +OP4 E03199 0 +OP4 E0319A 0 +OP4 E0319B 0 +OP4 E0319C 0 +OP4 E0319D 0 +OP4 E0319E 0 +OP4 E0319F 0 +OP4 E031A0 0 +OP4 E031A1 0 +OP4 E031A2 0 +OP4 E031A3 0 +OP4 E031A4 0 +OP4 E031A5 0 +OP4 E031A6 0 +OP4 E031A7 0 +OP4 E031A8 0 +OP4 E031A9 0 +OP4 E031AA 0 +OP4 E031AB 0 +OP4 E031AC 0 +OP4 E031AD 0 +OP4 E031AE 0 +OP4 E031AF 0 +OP4 E031B0 0 +OP4 E031B1 0 +OP4 E031B2 0 +OP4 E031B3 0 +OP4 E031B4 0 +OP4 E031B5 0 +OP4 E031B6 0 +OP4 E031B7 0 +OP4 E031B8 0 +OP4 E031B9 0 +OP4 E031BA 0 +OP4 E031BB 0 +OP4 E031BC 0 +OP4 E031BD 0 +OP4 E031BE 0 +OP4 E031BF 0 +OP4 E031C0 0 +OP4 E031C1 0 +OP4 E031C2 0 +OP4 E031C3 0 +OP4 E031C4 0 +OP4 E031C5 0 +OP4 E031C6 0 +OP4 E031C7 0 +OP4 E031C8 0 +OP4 E031C9 0 +OP4 E031CA 0 +OP4 E031CB 0 +OP4 E031CC 0 +OP4 E031CD 0 +OP4 E031CE 0 +OP4 E031CF 0 +OP4 E031D0 0 +OP4 E031D1 0 +OP4 E031D2 0 +OP4 E031D3 0 +OP4 E031D4 0 +OP4 E031D5 0 +OP4 E031D6 0 +OP4 E031D7 0 +OP4 E031D8 0 +OP4 E031D9 0 +OP4 E031DA 0 +OP4 E031DB 0 +OP4 E031DC 0 +OP4 E031DD 0 +OP4 E031DE 0 +OP4 E031DF 0 +OP4 E031E0 0 +OP4 E031E1 0 +OP4 E031E2 0 +OP4 E031E3 0 +OP4 E031E4 0 +OP4 E031E5 0 +OP4 E031E6 0 +OP4 E031E7 0 +OP4 E031E8 0 +OP4 E031E9 0 +OP4 E031EA 0 +OP4 E031EB 0 +OP4 E031EC 0 +OP4 E031ED 0 +OP4 E031EE 0 +OP4 E031EF 0 +OP4 E031F0 0 +OP4 E031F1 0 +OP4 E031F2 0 +OP4 E031F3 0 +OP4 E031F4 0 +OP4 E031F5 0 +OP4 E031F6 0 +OP4 E031F7 0 +OP4 E031F8 0 +OP4 E031F9 0 +OP4 E031FA 0 +OP4 E031FB 0 +OP4 E031FC 0 +OP4 E031FD 0 +OP4 E031FE 0 +OP4 E031FF 0 +OP4 E03200 0 +OP4 E03201 0 +OP4 E03202 0 +OP4 E03203 0 +OP4 E03204 0 +OP4 E03205 0 +OP4 E03206 0 +OP4 E03207 0 +OP4 E03208 0 +OP4 E03209 0 +OP4 E0320A 0 +OP4 E0320B 0 +OP4 E0320C 0 +OP4 E0320D 0 +OP4 E0320E 0 +OP4 E0320F 0 +OP4 E03210 0 +OP4 E03211 0 +OP4 E03212 0 +OP4 E03213 0 +OP4 E03214 0 +OP4 E03215 0 +OP4 E03216 0 +OP4 E03217 0 +OP4 E03218 0 +OP4 E03219 0 +OP4 E0321A 0 +OP4 E0321B 0 +OP4 E0321C 0 +OP4 E0321D 0 +OP4 E0321E 0 +OP4 E0321F 0 +OP4 E03220 0 +OP4 E03221 0 +OP4 E03222 0 +OP4 E03223 0 +OP4 E03224 0 +OP4 E03225 0 +OP4 E03226 0 +OP4 E03227 0 +OP4 E03228 0 +OP4 E03229 0 +OP4 E0322A 0 +OP4 E0322B 0 +OP4 E0322C 0 +OP4 E0322D 0 +OP4 E0322E 0 +OP4 E0322F 0 +OP4 E03230 0 +OP4 E03231 0 +OP4 E03232 0 +OP4 E03233 0 +OP4 E03234 0 +OP4 E03235 0 +OP4 E03236 0 +OP4 E03237 0 +OP4 E03238 0 +OP4 E03239 0 +OP4 E0323A 0 +OP4 E0323B 0 +OP4 E0323C 0 +OP4 E0323D 0 +OP4 E0323E 0 +OP4 E0323F 0 +OP4 E03240 0 +OP4 E03241 0 +OP4 E03242 0 +OP4 E03243 0 +OP4 E03244 0 +OP4 E03245 0 +OP4 E03246 0 +OP4 E03247 0 +OP4 E03248 0 +OP4 E03249 0 +OP4 E0324A 0 +OP4 E0324B 0 +OP4 E0324C 0 +OP4 E0324D 0 +OP4 E0324E 0 +OP4 E0324F 0 +OP4 E03250 0 +OP4 E03251 0 +OP4 E03252 0 +OP4 E03253 0 +OP4 E03254 0 +OP4 E03255 0 +OP4 E03256 0 +OP4 E03257 0 +OP4 E03258 0 +OP4 E03259 0 +OP4 E0325A 0 +OP4 E0325B 0 +OP4 E0325C 0 +OP4 E0325D 0 +OP4 E0325E 0 +OP4 E0325F 0 +OP4 E03260 0 +OP4 E03261 0 +OP4 E03262 0 +OP4 E03263 0 +OP4 E03264 0 +OP4 E03265 0 +OP4 E03266 0 +OP4 E03267 0 +OP4 E03268 0 +OP4 E03269 0 +OP4 E0326A 0 +OP4 E0326B 0 +OP4 E0326C 0 +OP4 E0326D 0 +OP4 E0326E 0 +OP4 E0326F 0 +OP4 E03270 0 +OP4 E03271 0 +OP4 E03272 0 +OP4 E03273 0 +OP4 E03274 0 +OP4 E03275 0 +OP4 E03276 0 +OP4 E03277 0 +OP4 E03278 0 +OP4 E03279 0 +OP4 E0327A 0 +OP4 E0327B 0 +OP4 E0327C 0 +OP4 E0327D 0 +OP4 E0327E 0 +OP4 E0327F 0 +OP4 E03280 0 +OP4 E03281 0 +OP4 E03282 0 +OP4 E03283 0 +OP4 E03284 0 +OP4 E03285 0 +OP4 E03286 0 +OP4 E03287 0 +OP4 E03288 0 +OP4 E03289 0 +OP4 E0328A 0 +OP4 E0328B 0 +OP4 E0328C 0 +OP4 E0328D 0 +OP4 E0328E 0 +OP4 E0328F 0 +OP4 E03290 0 +OP4 E03291 0 +OP4 E03292 0 +OP4 E03293 0 +OP4 E03294 0 +OP4 E03295 0 +OP4 E03296 0 +OP4 E03297 0 +OP4 E03298 0 +OP4 E03299 0 +OP4 E0329A 0 +OP4 E0329B 0 +OP4 E0329C 0 +OP4 E0329D 0 +OP4 E0329E 0 +OP4 E0329F 0 +OP4 E032A0 0 +OP4 E032A1 0 +OP4 E032A2 0 +OP4 E032A3 0 +OP4 E032A4 0 +OP4 E032A5 0 +OP4 E032A6 0 +OP4 E032A7 0 +OP4 E032A8 0 +OP4 E032A9 0 +OP4 E032AA 0 +OP4 E032AB 0 +OP4 E032AC 0 +OP4 E032AD 0 +OP4 E032AE 0 +OP4 E032AF 0 +OP4 E032B0 0 +OP4 E032B1 0 +OP4 E032B2 0 +OP4 E032B3 0 +OP4 E032B4 0 +OP4 E032B5 0 +OP4 E032B6 0 +OP4 E032B7 0 +OP4 E032B8 0 +OP4 E032B9 0 +OP4 E032BA 0 +OP4 E032BB 0 +OP4 E032BC 0 +OP4 E032BD 0 +OP4 E032BE 0 +OP4 E032BF 0 +OP4 E032C0 0 +OP4 E032C1 0 +OP4 E032C2 0 +OP4 E032C3 0 +OP4 E032C4 0 +OP4 E032C5 0 +OP4 E032C6 0 +OP4 E032C7 0 +OP4 E032C8 0 +OP4 E032C9 0 +OP4 E032CA 0 +OP4 E032CB 0 +OP4 E032CC 0 +OP4 E032CD 0 +OP4 E032CE 0 +OP4 E032CF 0 +OP4 E032D0 0 +OP4 E032D1 0 +OP4 E032D2 0 +OP4 E032D3 0 +OP4 E032D4 0 +OP4 E032D5 0 +OP4 E032D6 0 +OP4 E032D7 0 +OP4 E032D8 0 +OP4 E032D9 0 +OP4 E032DA 0 +OP4 E032DB 0 +OP4 E032DC 0 +OP4 E032DD 0 +OP4 E032DE 0 +OP4 E032DF 0 +OP4 E032E0 0 +OP4 E032E1 0 +OP4 E032E2 0 +OP4 E032E3 0 +OP4 E032E4 0 +OP4 E032E5 0 +OP4 E032E6 0 +OP4 E032E7 0 +OP4 E032E8 0 +OP4 E032E9 0 +OP4 E032EA 0 +OP4 E032EB 0 +OP4 E032EC 0 +OP4 E032ED 0 +OP4 E032EE 0 +OP4 E032EF 0 +OP4 E032F0 0 +OP4 E032F1 0 +OP4 E032F2 0 +OP4 E032F3 0 +OP4 E032F4 0 +OP4 E032F5 0 +OP4 E032F6 0 +OP4 E032F7 0 +OP4 E032F8 0 +OP4 E032F9 0 +OP4 E032FA 0 +OP4 E032FB 0 +OP4 E032FC 0 +OP4 E032FD 0 +OP4 E032FE 0 +OP4 E032FF 0 +OP4 E03300 0 +OP4 E03301 0 +OP4 E03302 0 +OP4 E03303 0 +OP4 E03304 0 +OP4 E03305 0 +OP4 E03306 0 +OP4 E03307 0 +OP4 E03308 0 +OP4 E03309 0 +OP4 E0330A 0 +OP4 E0330B 0 +OP4 E0330C 0 +OP4 E0330D 0 +OP4 E0330E 0 +OP4 E0330F 0 +OP4 E03310 0 +OP4 E03311 0 +OP4 E03312 0 +OP4 E03313 0 +OP4 E03314 0 +OP4 E03315 0 +OP4 E03316 0 +OP4 E03317 0 +OP4 E03318 0 +OP4 E03319 0 +OP4 E0331A 0 +OP4 E0331B 0 +OP4 E0331C 0 +OP4 E0331D 0 +OP4 E0331E 0 +OP4 E0331F 0 +OP4 E03320 0 +OP4 E03321 0 +OP4 E03322 0 +OP4 E03323 0 +OP4 E03324 0 +OP4 E03325 0 +OP4 E03326 0 +OP4 E03327 0 +OP4 E03328 0 +OP4 E03329 0 +OP4 E0332A 0 +OP4 E0332B 0 +OP4 E0332C 0 +OP4 E0332D 0 +OP4 E0332E 0 +OP4 E0332F 0 +OP4 E03330 0 +OP4 E03331 0 +OP4 E03332 0 +OP4 E03333 0 +OP4 E03334 0 +OP4 E03335 0 +OP4 E03336 0 +OP4 E03337 0 +OP4 E03338 0 +OP4 E03339 0 +OP4 E0333A 0 +OP4 E0333B 0 +OP4 E0333C 0 +OP4 E0333D 0 +OP4 E0333E 0 +OP4 E0333F 0 +OP4 E03340 0 +OP4 E03341 0 +OP4 E03342 0 +OP4 E03343 0 +OP4 E03344 0 +OP4 E03345 0 +OP4 E03346 0 +OP4 E03347 0 +OP4 E03348 0 +OP4 E03349 0 +OP4 E0334A 0 +OP4 E0334B 0 +OP4 E0334C 0 +OP4 E0334D 0 +OP4 E0334E 0 +OP4 E0334F 0 +OP4 E03350 0 +OP4 E03351 0 +OP4 E03352 0 +OP4 E03353 0 +OP4 E03354 0 +OP4 E03355 0 +OP4 E03356 0 +OP4 E03357 0 +OP4 E03358 0 +OP4 E03359 0 +OP4 E0335A 0 +OP4 E0335B 0 +OP4 E0335C 0 +OP4 E0335D 0 +OP4 E0335E 0 +OP4 E0335F 0 +OP4 E03360 0 +OP4 E03361 0 +OP4 E03362 0 +OP4 E03363 0 +OP4 E03364 0 +OP4 E03365 0 +OP4 E03366 0 +OP4 E03367 0 +OP4 E03368 0 +OP4 E03369 0 +OP4 E0336A 0 +OP4 E0336B 0 +OP4 E0336C 0 +OP4 E0336D 0 +OP4 E0336E 0 +OP4 E0336F 0 +OP4 E03370 0 +OP4 E03371 0 +OP4 E03372 0 +OP4 E03373 0 +OP4 E03374 0 +OP4 E03375 0 +OP4 E03376 0 +OP4 E03377 0 +OP4 E03378 0 +OP4 E03379 0 +OP4 E0337A 0 +OP4 E0337B 0 +OP4 E0337C 0 +OP4 E0337D 0 +OP4 E0337E 0 +OP4 E0337F 0 +OP4 E03380 0 +OP4 E03381 0 +OP4 E03382 0 +OP4 E03383 0 +OP4 E03384 0 +OP4 E03385 0 +OP4 E03386 0 +OP4 E03387 0 +OP4 E03388 0 +OP4 E03389 0 +OP4 E0338A 0 +OP4 E0338B 0 +OP4 E0338C 0 +OP4 E0338D 0 +OP4 E0338E 0 +OP4 E0338F 0 +OP4 E03390 0 +OP4 E03391 0 +OP4 E03392 0 +OP4 E03393 0 +OP4 E03394 0 +OP4 E03395 0 +OP4 E03396 0 +OP4 E03397 0 +OP4 E03398 0 +OP4 E03399 0 +OP4 E0339A 0 +OP4 E0339B 0 +OP4 E0339C 0 +OP4 E0339D 0 +OP4 E0339E 0 +OP4 E0339F 0 +OP4 E033A0 0 +OP4 E033A1 0 +OP4 E033A2 0 +OP4 E033A3 0 +OP4 E033A4 0 +OP4 E033A5 0 +OP4 E033A6 0 +OP4 E033A7 0 +OP4 E033A8 0 +OP4 E033A9 0 +OP4 E033AA 0 +OP4 E033AB 0 +OP4 E033AC 0 +OP4 E033AD 0 +OP4 E033AE 0 +OP4 E033AF 0 +OP4 E033B0 0 +OP4 E033B1 0 +OP4 E033B2 0 +OP4 E033B3 0 +OP4 E033B4 0 +OP4 E033B5 0 +OP4 E033B6 0 +OP4 E033B7 0 +OP4 E033B8 0 +OP4 E033B9 0 +OP4 E033BA 0 +OP4 E033BB 0 +OP4 E033BC 0 +OP4 E033BD 0 +OP4 E033BE 0 +OP4 E033BF 0 +OP4 E033C0 0 +OP4 E033C1 0 +OP4 E033C2 0 +OP4 E033C3 0 +OP4 E033C4 0 +OP4 E033C5 0 +OP4 E033C6 0 +OP4 E033C7 0 +OP4 E033C8 0 +OP4 E033C9 0 +OP4 E033CA 0 +OP4 E033CB 0 +OP4 E033CC 0 +OP4 E033CD 0 +OP4 E033CE 0 +OP4 E033CF 0 +OP4 E033D0 0 +OP4 E033D1 0 +OP4 E033D2 0 +OP4 E033D3 0 +OP4 E033D4 0 +OP4 E033D5 0 +OP4 E033D6 0 +OP4 E033D7 0 +OP4 E033D8 0 +OP4 E033D9 0 +OP4 E033DA 0 +OP4 E033DB 0 +OP4 E033DC 0 +OP4 E033DD 0 +OP4 E033DE 0 +OP4 E033DF 0 +OP4 E033E0 0 +OP4 E033E1 0 +OP4 E033E2 0 +OP4 E033E3 0 +OP4 E033E4 0 +OP4 E033E5 0 +OP4 E033E6 0 +OP4 E033E7 0 +OP4 E033E8 0 +OP4 E033E9 0 +OP4 E033EA 0 +OP4 E033EB 0 +OP4 E033EC 0 +OP4 E033ED 0 +OP4 E033EE 0 +OP4 E033EF 0 +OP4 E033F0 0 +OP4 E033F1 0 +OP4 E033F2 0 +OP4 E033F3 0 +OP4 E033F4 0 +OP4 E033F5 0 +OP4 E033F6 0 +OP4 E033F7 0 +OP4 E033F8 0 +OP4 E033F9 0 +OP4 E033FA 0 +OP4 E033FB 0 +OP4 E033FC 0 +OP4 E033FD 0 +OP4 E033FE 0 +OP4 E033FF 0 +OP4 E03400 0 +OP4 E03401 0 +OP4 E03402 0 +OP4 E03403 0 +OP4 E03404 0 +OP4 E03405 0 +OP4 E03406 0 +OP4 E03407 0 +OP4 E03408 0 +OP4 E03409 0 +OP4 E0340A 0 +OP4 E0340B 0 +OP4 E0340C 0 +OP4 E0340D 0 +OP4 E0340E 0 +OP4 E0340F 0 +OP4 E03410 0 +OP4 E03411 0 +OP4 E03412 0 +OP4 E03413 0 +OP4 E03414 0 +OP4 E03415 0 +OP4 E03416 0 +OP4 E03417 0 +OP4 E03418 0 +OP4 E03419 0 +OP4 E0341A 0 +OP4 E0341B 0 +OP4 E0341C 0 +OP4 E0341D 0 +OP4 E0341E 0 +OP4 E0341F 0 +OP4 E03420 0 +OP4 E03421 0 +OP4 E03422 0 +OP4 E03423 0 +OP4 E03424 0 +OP4 E03425 0 +OP4 E03426 0 +OP4 E03427 0 +OP4 E03428 0 +OP4 E03429 0 +OP4 E0342A 0 +OP4 E0342B 0 +OP4 E0342C 0 +OP4 E0342D 0 +OP4 E0342E 0 +OP4 E0342F 0 +OP4 E03430 0 +OP4 E03431 0 +OP4 E03432 0 +OP4 E03433 0 +OP4 E03434 0 +OP4 E03435 0 +OP4 E03436 0 +OP4 E03437 0 +OP4 E03438 0 +OP4 E03439 0 +OP4 E0343A 0 +OP4 E0343B 0 +OP4 E0343C 0 +OP4 E0343D 0 +OP4 E0343E 0 +OP4 E0343F 0 +OP4 E03440 0 +OP4 E03441 0 +OP4 E03442 0 +OP4 E03443 0 +OP4 E03444 0 +OP4 E03445 0 +OP4 E03446 0 +OP4 E03447 0 +OP4 E03448 0 +OP4 E03449 0 +OP4 E0344A 0 +OP4 E0344B 0 +OP4 E0344C 0 +OP4 E0344D 0 +OP4 E0344E 0 +OP4 E0344F 0 +OP4 E03450 0 +OP4 E03451 0 +OP4 E03452 0 +OP4 E03453 0 +OP4 E03454 0 +OP4 E03455 0 +OP4 E03456 0 +OP4 E03457 0 +OP4 E03458 0 +OP4 E03459 0 +OP4 E0345A 0 +OP4 E0345B 0 +OP4 E0345C 0 +OP4 E0345D 0 +OP4 E0345E 0 +OP4 E0345F 0 +OP4 E03460 0 +OP4 E03461 0 +OP4 E03462 0 +OP4 E03463 0 +OP4 E03464 0 +OP4 E03465 0 +OP4 E03466 0 +OP4 E03467 0 +OP4 E03468 0 +OP4 E03469 0 +OP4 E0346A 0 +OP4 E0346B 0 +OP4 E0346C 0 +OP4 E0346D 0 +OP4 E0346E 0 +OP4 E0346F 0 +OP4 E03470 0 +OP4 E03471 0 +OP4 E03472 0 +OP4 E03473 0 +OP4 E03474 0 +OP4 E03475 0 +OP4 E03476 0 +OP4 E03477 0 +OP4 E03478 0 +OP4 E03479 0 +OP4 E0347A 0 +OP4 E0347B 0 +OP4 E0347C 0 +OP4 E0347D 0 +OP4 E0347E 0 +OP4 E0347F 0 +OP4 E03480 0 +OP4 E03481 0 +OP4 E03482 0 +OP4 E03483 0 +OP4 E03484 0 +OP4 E03485 0 +OP4 E03486 0 +OP4 E03487 0 +OP4 E03488 0 +OP4 E03489 0 +OP4 E0348A 0 +OP4 E0348B 0 +OP4 E0348C 0 +OP4 E0348D 0 +OP4 E0348E 0 +OP4 E0348F 0 +OP4 E03490 0 +OP4 E03491 0 +OP4 E03492 0 +OP4 E03493 0 +OP4 E03494 0 +OP4 E03495 0 +OP4 E03496 0 +OP4 E03497 0 +OP4 E03498 0 +OP4 E03499 0 +OP4 E0349A 0 +OP4 E0349B 0 +OP4 E0349C 0 +OP4 E0349D 0 +OP4 E0349E 0 +OP4 E0349F 0 +OP4 E034A0 0 +OP4 E034A1 0 +OP4 E034A2 0 +OP4 E034A3 0 +OP4 E034A4 0 +OP4 E034A5 0 +OP4 E034A6 0 +OP4 E034A7 0 +OP4 E034A8 0 +OP4 E034A9 0 +OP4 E034AA 0 +OP4 E034AB 0 +OP4 E034AC 0 +OP4 E034AD 0 +OP4 E034AE 0 +OP4 E034AF 0 +OP4 E034B0 0 +OP4 E034B1 0 +OP4 E034B2 0 +OP4 E034B3 0 +OP4 E034B4 0 +OP4 E034B5 0 +OP4 E034B6 0 +OP4 E034B7 0 +OP4 E034B8 0 +OP4 E034B9 0 +OP4 E034BA 0 +OP4 E034BB 0 +OP4 E034BC 0 +OP4 E034BD 0 +OP4 E034BE 0 +OP4 E034BF 0 +OP4 E034C0 0 +OP4 E034C1 0 +OP4 E034C2 0 +OP4 E034C3 0 +OP4 E034C4 0 +OP4 E034C5 0 +OP4 E034C6 0 +OP4 E034C7 0 +OP4 E034C8 0 +OP4 E034C9 0 +OP4 E034CA 0 +OP4 E034CB 0 +OP4 E034CC 0 +OP4 E034CD 0 +OP4 E034CE 0 +OP4 E034CF 0 +OP4 E034D0 0 +OP4 E034D1 0 +OP4 E034D2 0 +OP4 E034D3 0 +OP4 E034D4 0 +OP4 E034D5 0 +OP4 E034D6 0 +OP4 E034D7 0 +OP4 E034D8 0 +OP4 E034D9 0 +OP4 E034DA 0 +OP4 E034DB 0 +OP4 E034DC 0 +OP4 E034DD 0 +OP4 E034DE 0 +OP4 E034DF 0 +OP4 E034E0 0 +OP4 E034E1 0 +OP4 E034E2 0 +OP4 E034E3 0 +OP4 E034E4 0 +OP4 E034E5 0 +OP4 E034E6 0 +OP4 E034E7 0 +OP4 E034E8 0 +OP4 E034E9 0 +OP4 E034EA 0 +OP4 E034EB 0 +OP4 E034EC 0 +OP4 E034ED 0 +OP4 E034EE 0 +OP4 E034EF 0 +OP4 E034F0 0 +OP4 E034F1 0 +OP4 E034F2 0 +OP4 E034F3 0 +OP4 E034F4 0 +OP4 E034F5 0 +OP4 E034F6 0 +OP4 E034F7 0 +OP4 E034F8 0 +OP4 E034F9 0 +OP4 E034FA 0 +OP4 E034FB 0 +OP4 E034FC 0 +OP4 E034FD 0 +OP4 E034FE 0 +OP4 E034FF 0 +OP4 E03500 0 +OP4 E03501 0 +OP4 E03502 0 +OP4 E03503 0 +OP4 E03504 0 +OP4 E03505 0 +OP4 E03506 0 +OP4 E03507 0 +OP4 E03508 0 +OP4 E03509 0 +OP4 E0350A 0 +OP4 E0350B 0 +OP4 E0350C 0 +OP4 E0350D 0 +OP4 E0350E 0 +OP4 E0350F 0 +OP4 E03510 0 +OP4 E03511 0 +OP4 E03512 0 +OP4 E03513 0 +OP4 E03514 0 +OP4 E03515 0 +OP4 E03516 0 +OP4 E03517 0 +OP4 E03518 0 +OP4 E03519 0 +OP4 E0351A 0 +OP4 E0351B 0 +OP4 E0351C 0 +OP4 E0351D 0 +OP4 E0351E 0 +OP4 E0351F 0 +OP4 E03520 0 +OP4 E03521 0 +OP4 E03522 0 +OP4 E03523 0 +OP4 E03524 0 +OP4 E03525 0 +OP4 E03526 0 +OP4 E03527 0 +OP4 E03528 0 +OP4 E03529 0 +OP4 E0352A 0 +OP4 E0352B 0 +OP4 E0352C 0 +OP4 E0352D 0 +OP4 E0352E 0 +OP4 E0352F 0 +OP4 E03530 0 +OP4 E03531 0 +OP4 E03532 0 +OP4 E03533 0 +OP4 E03534 0 +OP4 E03535 0 +OP4 E03536 0 +OP4 E03537 0 +OP4 E03538 0 +OP4 E03539 0 +OP4 E0353A 0 +OP4 E0353B 0 +OP4 E0353C 0 +OP4 E0353D 0 +OP4 E0353E 0 +OP4 E0353F 0 +OP4 E03540 0 +OP4 E03541 0 +OP4 E03542 0 +OP4 E03543 0 +OP4 E03544 0 +OP4 E03545 0 +OP4 E03546 0 +OP4 E03547 0 +OP4 E03548 0 +OP4 E03549 0 +OP4 E0354A 0 +OP4 E0354B 0 +OP4 E0354C 0 +OP4 E0354D 0 +OP4 E0354E 0 +OP4 E0354F 0 +OP4 E03550 0 +OP4 E03551 0 +OP4 E03552 0 +OP4 E03553 0 +OP4 E03554 0 +OP4 E03555 0 +OP4 E03556 0 +OP4 E03557 0 +OP4 E03558 0 +OP4 E03559 0 +OP4 E0355A 0 +OP4 E0355B 0 +OP4 E0355C 0 +OP4 E0355D 0 +OP4 E0355E 0 +OP4 E0355F 0 +OP4 E03560 0 +OP4 E03561 0 +OP4 E03562 0 +OP4 E03563 0 +OP4 E03564 0 +OP4 E03565 0 +OP4 E03566 0 +OP4 E03567 0 +OP4 E03568 0 +OP4 E03569 0 +OP4 E0356A 0 +OP4 E0356B 0 +OP4 E0356C 0 +OP4 E0356D 0 +OP4 E0356E 0 +OP4 E0356F 0 +OP4 E03570 0 +OP4 E03571 0 +OP4 E03572 0 +OP4 E03573 0 +OP4 E03574 0 +OP4 E03575 0 +OP4 E03576 0 +OP4 E03577 0 +OP4 E03578 0 +OP4 E03579 0 +OP4 E0357A 0 +OP4 E0357B 0 +OP4 E0357C 0 +OP4 E0357D 0 +OP4 E0357E 0 +OP4 E0357F 0 +OP4 E03580 0 +OP4 E03581 0 +OP4 E03582 0 +OP4 E03583 0 +OP4 E03584 0 +OP4 E03585 0 +OP4 E03586 0 +OP4 E03587 0 +OP4 E03588 0 +OP4 E03589 0 +OP4 E0358A 0 +OP4 E0358B 0 +OP4 E0358C 0 +OP4 E0358D 0 +OP4 E0358E 0 +OP4 E0358F 0 +OP4 E03590 0 +OP4 E03591 0 +OP4 E03592 0 +OP4 E03593 0 +OP4 E03594 0 +OP4 E03595 0 +OP4 E03596 0 +OP4 E03597 0 +OP4 E03598 0 +OP4 E03599 0 +OP4 E0359A 0 +OP4 E0359B 0 +OP4 E0359C 0 +OP4 E0359D 0 +OP4 E0359E 0 +OP4 E0359F 0 +OP4 E035A0 0 +OP4 E035A1 0 +OP4 E035A2 0 +OP4 E035A3 0 +OP4 E035A4 0 +OP4 E035A5 0 +OP4 E035A6 0 +OP4 E035A7 0 +OP4 E035A8 0 +OP4 E035A9 0 +OP4 E035AA 0 +OP4 E035AB 0 +OP4 E035AC 0 +OP4 E035AD 0 +OP4 E035AE 0 +OP4 E035AF 0 +OP4 E035B0 0 +OP4 E035B1 0 +OP4 E035B2 0 +OP4 E035B3 0 +OP4 E035B4 0 +OP4 E035B5 0 +OP4 E035B6 0 +OP4 E035B7 0 +OP4 E035B8 0 +OP4 E035B9 0 +OP4 E035BA 0 +OP4 E035BB 0 +OP4 E035BC 0 +OP4 E035BD 0 +OP4 E035BE 0 +OP4 E035BF 0 +OP4 E035C0 0 +OP4 E035C1 0 +OP4 E035C2 0 +OP4 E035C3 0 +OP4 E035C4 0 +OP4 E035C5 0 +OP4 E035C6 0 +OP4 E035C7 0 +OP4 E035C8 0 +OP4 E035C9 0 +OP4 E035CA 0 +OP4 E035CB 0 +OP4 E035CC 0 +OP4 E035CD 0 +OP4 E035CE 0 +OP4 E035CF 0 +OP4 E035D0 0 +OP4 E035D1 0 +OP4 E035D2 0 +OP4 E035D3 0 +OP4 E035D4 0 +OP4 E035D5 0 +OP4 E035D6 0 +OP4 E035D7 0 +OP4 E035D8 0 +OP4 E035D9 0 +OP4 E035DA 0 +OP4 E035DB 0 +OP4 E035DC 0 +OP4 E035DD 0 +OP4 E035DE 0 +OP4 E035DF 0 +OP4 E035E0 0 +OP4 E035E1 0 +OP4 E035E2 0 +OP4 E035E3 0 +OP4 E035E4 0 +OP4 E035E5 0 +OP4 E035E6 0 +OP4 E035E7 0 +OP4 E035E8 0 +OP4 E035E9 0 +OP4 E035EA 0 +OP4 E035EB 0 +OP4 E035EC 0 +OP4 E035ED 0 +OP4 E035EE 0 +OP4 E035EF 0 +OP4 E035F0 0 +OP4 E035F1 0 +OP4 E035F2 0 +OP4 E035F3 0 +OP4 E035F4 0 +OP4 E035F5 0 +OP4 E035F6 0 +OP4 E035F7 0 +OP4 E035F8 0 +OP4 E035F9 0 +OP4 E035FA 0 +OP4 E035FB 0 +OP4 E035FC 0 +OP4 E035FD 0 +OP4 E035FE 0 +OP4 E035FF 0 +OP4 E03600 0 +OP4 E03601 0 +OP4 E03602 0 +OP4 E03603 0 +OP4 E03604 0 +OP4 E03605 0 +OP4 E03606 0 +OP4 E03607 0 +OP4 E03608 0 +OP4 E03609 0 +OP4 E0360A 0 +OP4 E0360B 0 +OP4 E0360C 0 +OP4 E0360D 0 +OP4 E0360E 0 +OP4 E0360F 0 +OP4 E03610 0 +OP4 E03611 0 +OP4 E03612 0 +OP4 E03613 0 +OP4 E03614 0 +OP4 E03615 0 +OP4 E03616 0 +OP4 E03617 0 +OP4 E03618 0 +OP4 E03619 0 +OP4 E0361A 0 +OP4 E0361B 0 +OP4 E0361C 0 +OP4 E0361D 0 +OP4 E0361E 0 +OP4 E0361F 0 +OP4 E03620 0 +OP4 E03621 0 +OP4 E03622 0 +OP4 E03623 0 +OP4 E03624 0 +OP4 E03625 0 +OP4 E03626 0 +OP4 E03627 0 +OP4 E03628 0 +OP4 E03629 0 +OP4 E0362A 0 +OP4 E0362B 0 +OP4 E0362C 0 +OP4 E0362D 0 +OP4 E0362E 0 +OP4 E0362F 0 +OP4 E03630 0 +OP4 E03631 0 +OP4 E03632 0 +OP4 E03633 0 +OP4 E03634 0 +OP4 E03635 0 +OP4 E03636 0 +OP4 E03637 0 +OP4 E03638 0 +OP4 E03639 0 +OP4 E0363A 0 +OP4 E0363B 0 +OP4 E0363C 0 +OP4 E0363D 0 +OP4 E0363E 0 +OP4 E0363F 0 +OP4 E03640 0 +OP4 E03641 0 +OP4 E03642 0 +OP4 E03643 0 +OP4 E03644 0 +OP4 E03645 0 +OP4 E03646 0 +OP4 E03647 0 +OP4 E03648 0 +OP4 E03649 0 +OP4 E0364A 0 +OP4 E0364B 0 +OP4 E0364C 0 +OP4 E0364D 0 +OP4 E0364E 0 +OP4 E0364F 0 +OP4 E03650 0 +OP4 E03651 0 +OP4 E03652 0 +OP4 E03653 0 +OP4 E03654 0 +OP4 E03655 0 +OP4 E03656 0 +OP4 E03657 0 +OP4 E03658 0 +OP4 E03659 0 +OP4 E0365A 0 +OP4 E0365B 0 +OP4 E0365C 0 +OP4 E0365D 0 +OP4 E0365E 0 +OP4 E0365F 0 +OP4 E03660 0 +OP4 E03661 0 +OP4 E03662 0 +OP4 E03663 0 +OP4 E03664 0 +OP4 E03665 0 +OP4 E03666 0 +OP4 E03667 0 +OP4 E03668 0 +OP4 E03669 0 +OP4 E0366A 0 +OP4 E0366B 0 +OP4 E0366C 0 +OP4 E0366D 0 +OP4 E0366E 0 +OP4 E0366F 0 +OP4 E03670 0 +OP4 E03671 0 +OP4 E03672 0 +OP4 E03673 0 +OP4 E03674 0 +OP4 E03675 0 +OP4 E03676 0 +OP4 E03677 0 +OP4 E03678 0 +OP4 E03679 0 +OP4 E0367A 0 +OP4 E0367B 0 +OP4 E0367C 0 +OP4 E0367D 0 +OP4 E0367E 0 +OP4 E0367F 0 +OP4 E03680 0 +OP4 E03681 0 +OP4 E03682 0 +OP4 E03683 0 +OP4 E03684 0 +OP4 E03685 0 +OP4 E03686 0 +OP4 E03687 0 +OP4 E03688 0 +OP4 E03689 0 +OP4 E0368A 0 +OP4 E0368B 0 +OP4 E0368C 0 +OP4 E0368D 0 +OP4 E0368E 0 +OP4 E0368F 0 +OP4 E03690 0 +OP4 E03691 0 +OP4 E03692 0 +OP4 E03693 0 +OP4 E03694 0 +OP4 E03695 0 +OP4 E03696 0 +OP4 E03697 0 +OP4 E03698 0 +OP4 E03699 0 +OP4 E0369A 0 +OP4 E0369B 0 +OP4 E0369C 0 +OP4 E0369D 0 +OP4 E0369E 0 +OP4 E0369F 0 +OP4 E036A0 0 +OP4 E036A1 0 +OP4 E036A2 0 +OP4 E036A3 0 +OP4 E036A4 0 +OP4 E036A5 0 +OP4 E036A6 0 +OP4 E036A7 0 +OP4 E036A8 0 +OP4 E036A9 0 +OP4 E036AA 0 +OP4 E036AB 0 +OP4 E036AC 0 +OP4 E036AD 0 +OP4 E036AE 0 +OP4 E036AF 0 +OP4 E036B0 0 +OP4 E036B1 0 +OP4 E036B2 0 +OP4 E036B3 0 +OP4 E036B4 0 +OP4 E036B5 0 +OP4 E036B6 0 +OP4 E036B7 0 +OP4 E036B8 0 +OP4 E036B9 0 +OP4 E036BA 0 +OP4 E036BB 0 +OP4 E036BC 0 +OP4 E036BD 0 +OP4 E036BE 0 +OP4 E036BF 0 +OP4 E036C0 0 +OP4 E036C1 0 +OP4 E036C2 0 +OP4 E036C3 0 +OP4 E036C4 0 +OP4 E036C5 0 +OP4 E036C6 0 +OP4 E036C7 0 +OP4 E036C8 0 +OP4 E036C9 0 +OP4 E036CA 0 +OP4 E036CB 0 +OP4 E036CC 0 +OP4 E036CD 0 +OP4 E036CE 0 +OP4 E036CF 0 +OP4 E036D0 0 +OP4 E036D1 0 +OP4 E036D2 0 +OP4 E036D3 0 +OP4 E036D4 0 +OP4 E036D5 0 +OP4 E036D6 0 +OP4 E036D7 0 +OP4 E036D8 0 +OP4 E036D9 0 +OP4 E036DA 0 +OP4 E036DB 0 +OP4 E036DC 0 +OP4 E036DD 0 +OP4 E036DE 0 +OP4 E036DF 0 +OP4 E036E0 0 +OP4 E036E1 0 +OP4 E036E2 0 +OP4 E036E3 0 +OP4 E036E4 0 +OP4 E036E5 0 +OP4 E036E6 0 +OP4 E036E7 0 +OP4 E036E8 0 +OP4 E036E9 0 +OP4 E036EA 0 +OP4 E036EB 0 +OP4 E036EC 0 +OP4 E036ED 0 +OP4 E036EE 0 +OP4 E036EF 0 +OP4 E036F0 0 +OP4 E036F1 0 +OP4 E036F2 0 +OP4 E036F3 0 +OP4 E036F4 0 +OP4 E036F5 0 +OP4 E036F6 0 +OP4 E036F7 0 +OP4 E036F8 0 +OP4 E036F9 0 +OP4 E036FA 0 +OP4 E036FB 0 +OP4 E036FC 0 +OP4 E036FD 0 +OP4 E036FE 0 +OP4 E036FF 0 +OP4 E03700 0 +OP4 E03701 0 +OP4 E03702 0 +OP4 E03703 0 +OP4 E03704 0 +OP4 E03705 0 +OP4 E03706 0 +OP4 E03707 0 +OP4 E03708 0 +OP4 E03709 0 +OP4 E0370A 0 +OP4 E0370B 0 +OP4 E0370C 0 +OP4 E0370D 0 +OP4 E0370E 0 +OP4 E0370F 0 +OP4 E03710 0 +OP4 E03711 0 +OP4 E03712 0 +OP4 E03713 0 +OP4 E03714 0 +OP4 E03715 0 +OP4 E03716 0 +OP4 E03717 0 +OP4 E03718 0 +OP4 E03719 0 +OP4 E0371A 0 +OP4 E0371B 0 +OP4 E0371C 0 +OP4 E0371D 0 +OP4 E0371E 0 +OP4 E0371F 0 +OP4 E03720 0 +OP4 E03721 0 +OP4 E03722 0 +OP4 E03723 0 +OP4 E03724 0 +OP4 E03725 0 +OP4 E03726 0 +OP4 E03727 0 +OP4 E03728 0 +OP4 E03729 0 +OP4 E0372A 0 +OP4 E0372B 0 +OP4 E0372C 0 +OP4 E0372D 0 +OP4 E0372E 0 +OP4 E0372F 0 +OP4 E03730 0 +OP4 E03731 0 +OP4 E03732 0 +OP4 E03733 0 +OP4 E03734 0 +OP4 E03735 0 +OP4 E03736 0 +OP4 E03737 0 +OP4 E03738 0 +OP4 E03739 0 +OP4 E0373A 0 +OP4 E0373B 0 +OP4 E0373C 0 +OP4 E0373D 0 +OP4 E0373E 0 +OP4 E0373F 0 +OP4 E03740 0 +OP4 E03741 0 +OP4 E03742 0 +OP4 E03743 0 +OP4 E03744 0 +OP4 E03745 0 +OP4 E03746 0 +OP4 E03747 0 +OP4 E03748 0 +OP4 E03749 0 +OP4 E0374A 0 +OP4 E0374B 0 +OP4 E0374C 0 +OP4 E0374D 0 +OP4 E0374E 0 +OP4 E0374F 0 +OP4 E03750 0 +OP4 E03751 0 +OP4 E03752 0 +OP4 E03753 0 +OP4 E03754 0 +OP4 E03755 0 +OP4 E03756 0 +OP4 E03757 0 +OP4 E03758 0 +OP4 E03759 0 +OP4 E0375A 0 +OP4 E0375B 0 +OP4 E0375C 0 +OP4 E0375D 0 +OP4 E0375E 0 +OP4 E0375F 0 +OP4 E03760 0 +OP4 E03761 0 +OP4 E03762 0 +OP4 E03763 0 +OP4 E03764 0 +OP4 E03765 0 +OP4 E03766 0 +OP4 E03767 0 +OP4 E03768 0 +OP4 E03769 0 +OP4 E0376A 0 +OP4 E0376B 0 +OP4 E0376C 0 +OP4 E0376D 0 +OP4 E0376E 0 +OP4 E0376F 0 +OP4 E03770 0 +OP4 E03771 0 +OP4 E03772 0 +OP4 E03773 0 +OP4 E03774 0 +OP4 E03775 0 +OP4 E03776 0 +OP4 E03777 0 +OP4 E03778 0 +OP4 E03779 0 +OP4 E0377A 0 +OP4 E0377B 0 +OP4 E0377C 0 +OP4 E0377D 0 +OP4 E0377E 0 +OP4 E0377F 0 +OP4 E03780 0 +OP4 E03781 0 +OP4 E03782 0 +OP4 E03783 0 +OP4 E03784 0 +OP4 E03785 0 +OP4 E03786 0 +OP4 E03787 0 +OP4 E03788 0 +OP4 E03789 0 +OP4 E0378A 0 +OP4 E0378B 0 +OP4 E0378C 0 +OP4 E0378D 0 +OP4 E0378E 0 +OP4 E0378F 0 +OP4 E03790 0 +OP4 E03791 0 +OP4 E03792 0 +OP4 E03793 0 +OP4 E03794 0 +OP4 E03795 0 +OP4 E03796 0 +OP4 E03797 0 +OP4 E03798 0 +OP4 E03799 0 +OP4 E0379A 0 +OP4 E0379B 0 +OP4 E0379C 0 +OP4 E0379D 0 +OP4 E0379E 0 +OP4 E0379F 0 +OP4 E037A0 0 +OP4 E037A1 0 +OP4 E037A2 0 +OP4 E037A3 0 +OP4 E037A4 0 +OP4 E037A5 0 +OP4 E037A6 0 +OP4 E037A7 0 +OP4 E037A8 0 +OP4 E037A9 0 +OP4 E037AA 0 +OP4 E037AB 0 +OP4 E037AC 0 +OP4 E037AD 0 +OP4 E037AE 0 +OP4 E037AF 0 +OP4 E037B0 0 +OP4 E037B1 0 +OP4 E037B2 0 +OP4 E037B3 0 +OP4 E037B4 0 +OP4 E037B5 0 +OP4 E037B6 0 +OP4 E037B7 0 +OP4 E037B8 0 +OP4 E037B9 0 +OP4 E037BA 0 +OP4 E037BB 0 +OP4 E037BC 0 +OP4 E037BD 0 +OP4 E037BE 0 +OP4 E037BF 0 +OP4 E037C0 0 +OP4 E037C1 0 +OP4 E037C2 0 +OP4 E037C3 0 +OP4 E037C4 0 +OP4 E037C5 0 +OP4 E037C6 0 +OP4 E037C7 0 +OP4 E037C8 0 +OP4 E037C9 0 +OP4 E037CA 0 +OP4 E037CB 0 +OP4 E037CC 0 +OP4 E037CD 0 +OP4 E037CE 0 +OP4 E037CF 0 +OP4 E037D0 0 +OP4 E037D1 0 +OP4 E037D2 0 +OP4 E037D3 0 +OP4 E037D4 0 +OP4 E037D5 0 +OP4 E037D6 0 +OP4 E037D7 0 +OP4 E037D8 0 +OP4 E037D9 0 +OP4 E037DA 0 +OP4 E037DB 0 +OP4 E037DC 0 +OP4 E037DD 0 +OP4 E037DE 0 +OP4 E037DF 0 +OP4 E037E0 0 +OP4 E037E1 0 +OP4 E037E2 0 +OP4 E037E3 0 +OP4 E037E4 0 +OP4 E037E5 0 +OP4 E037E6 0 +OP4 E037E7 0 +OP4 E037E8 0 +OP4 E037E9 0 +OP4 E037EA 0 +OP4 E037EB 0 +OP4 E037EC 0 +OP4 E037ED 0 +OP4 E037EE 0 +OP4 E037EF 0 +OP4 E037F0 0 +OP4 E037F1 0 +OP4 E037F2 0 +OP4 E037F3 0 +OP4 E037F4 0 +OP4 E037F5 0 +OP4 E037F6 0 +OP4 E037F7 0 +OP4 E037F8 0 +OP4 E037F9 0 +OP4 E037FA 0 +OP4 E037FB 0 +OP4 E037FC 0 +OP4 E037FD 0 +OP4 E037FE 0 +OP4 E037FF 0 +OP4 E03800 0 +OP4 E03801 0 +OP4 E03802 0 +OP4 E03803 0 +OP4 E03804 0 +OP4 E03805 0 +OP4 E03806 0 +OP4 E03807 0 +OP4 E03808 0 +OP4 E03809 0 +OP4 E0380A 0 +OP4 E0380B 0 +OP4 E0380C 0 +OP4 E0380D 0 +OP4 E0380E 0 +OP4 E0380F 0 +OP4 E03810 0 +OP4 E03811 0 +OP4 E03812 0 +OP4 E03813 0 +OP4 E03814 0 +OP4 E03815 0 +OP4 E03816 0 +OP4 E03817 0 +OP4 E03818 0 +OP4 E03819 0 +OP4 E0381A 0 +OP4 E0381B 0 +OP4 E0381C 0 +OP4 E0381D 0 +OP4 E0381E 0 +OP4 E0381F 0 +OP4 E03820 0 +OP4 E03821 0 +OP4 E03822 0 +OP4 E03823 0 +OP4 E03824 0 +OP4 E03825 0 +OP4 E03826 0 +OP4 E03827 0 +OP4 E03828 0 +OP4 E03829 0 +OP4 E0382A 0 +OP4 E0382B 0 +OP4 E0382C 0 +OP4 E0382D 0 +OP4 E0382E 0 +OP4 E0382F 0 +OP4 E03830 0 +OP4 E03831 0 +OP4 E03832 0 +OP4 E03833 0 +OP4 E03834 0 +OP4 E03835 0 +OP4 E03836 0 +OP4 E03837 0 +OP4 E03838 0 +OP4 E03839 0 +OP4 E0383A 0 +OP4 E0383B 0 +OP4 E0383C 0 +OP4 E0383D 0 +OP4 E0383E 0 +OP4 E0383F 0 +OP4 E03840 0 +OP4 E03841 0 +OP4 E03842 0 +OP4 E03843 0 +OP4 E03844 0 +OP4 E03845 0 +OP4 E03846 0 +OP4 E03847 0 +OP4 E03848 0 +OP4 E03849 0 +OP4 E0384A 0 +OP4 E0384B 0 +OP4 E0384C 0 +OP4 E0384D 0 +OP4 E0384E 0 +OP4 E0384F 0 +OP4 E03850 0 +OP4 E03851 0 +OP4 E03852 0 +OP4 E03853 0 +OP4 E03854 0 +OP4 E03855 0 +OP4 E03856 0 +OP4 E03857 0 +OP4 E03858 0 +OP4 E03859 0 +OP4 E0385A 0 +OP4 E0385B 0 +OP4 E0385C 0 +OP4 E0385D 0 +OP4 E0385E 0 +OP4 E0385F 0 +OP4 E03860 0 +OP4 E03861 0 +OP4 E03862 0 +OP4 E03863 0 +OP4 E03864 0 +OP4 E03865 0 +OP4 E03866 0 +OP4 E03867 0 +OP4 E03868 0 +OP4 E03869 0 +OP4 E0386A 0 +OP4 E0386B 0 +OP4 E0386C 0 +OP4 E0386D 0 +OP4 E0386E 0 +OP4 E0386F 0 +OP4 E03870 0 +OP4 E03871 0 +OP4 E03872 0 +OP4 E03873 0 +OP4 E03874 0 +OP4 E03875 0 +OP4 E03876 0 +OP4 E03877 0 +OP4 E03878 0 +OP4 E03879 0 +OP4 E0387A 0 +OP4 E0387B 0 +OP4 E0387C 0 +OP4 E0387D 0 +OP4 E0387E 0 +OP4 E0387F 0 +OP4 E03880 0 +OP4 E03881 0 +OP4 E03882 0 +OP4 E03883 0 +OP4 E03884 0 +OP4 E03885 0 +OP4 E03886 0 +OP4 E03887 0 +OP4 E03888 0 +OP4 E03889 0 +OP4 E0388A 0 +OP4 E0388B 0 +OP4 E0388C 0 +OP4 E0388D 0 +OP4 E0388E 0 +OP4 E0388F 0 +OP4 E03890 0 +OP4 E03891 0 +OP4 E03892 0 +OP4 E03893 0 +OP4 E03894 0 +OP4 E03895 0 +OP4 E03896 0 +OP4 E03897 0 +OP4 E03898 0 +OP4 E03899 0 +OP4 E0389A 0 +OP4 E0389B 0 +OP4 E0389C 0 +OP4 E0389D 0 +OP4 E0389E 0 +OP4 E0389F 0 +OP4 E038A0 0 +OP4 E038A1 0 +OP4 E038A2 0 +OP4 E038A3 0 +OP4 E038A4 0 +OP4 E038A5 0 +OP4 E038A6 0 +OP4 E038A7 0 +OP4 E038A8 0 +OP4 E038A9 0 +OP4 E038AA 0 +OP4 E038AB 0 +OP4 E038AC 0 +OP4 E038AD 0 +OP4 E038AE 0 +OP4 E038AF 0 +OP4 E038B0 0 +OP4 E038B1 0 +OP4 E038B2 0 +OP4 E038B3 0 +OP4 E038B4 0 +OP4 E038B5 0 +OP4 E038B6 0 +OP4 E038B7 0 +OP4 E038B8 0 +OP4 E038B9 0 +OP4 E038BA 0 +OP4 E038BB 0 +OP4 E038BC 0 +OP4 E038BD 0 +OP4 E038BE 0 +OP4 E038BF 0 +OP4 E038C0 0 +OP4 E038C1 0 +OP4 E038C2 0 +OP4 E038C3 0 +OP4 E038C4 0 +OP4 E038C5 0 +OP4 E038C6 0 +OP4 E038C7 0 +OP4 E038C8 0 +OP4 E038C9 0 +OP4 E038CA 0 +OP4 E038CB 0 +OP4 E038CC 0 +OP4 E038CD 0 +OP4 E038CE 0 +OP4 E038CF 0 +OP4 E038D0 0 +OP4 E038D1 0 +OP4 E038D2 0 +OP4 E038D3 0 +OP4 E038D4 0 +OP4 E038D5 0 +OP4 E038D6 0 +OP4 E038D7 0 +OP4 E038D8 0 +OP4 E038D9 0 +OP4 E038DA 0 +OP4 E038DB 0 +OP4 E038DC 0 +OP4 E038DD 0 +OP4 E038DE 0 +OP4 E038DF 0 +OP4 E038E0 0 +OP4 E038E1 0 +OP4 E038E2 0 +OP4 E038E3 0 +OP4 E038E4 0 +OP4 E038E5 0 +OP4 E038E6 0 +OP4 E038E7 0 +OP4 E038E8 0 +OP4 E038E9 0 +OP4 E038EA 0 +OP4 E038EB 0 +OP4 E038EC 0 +OP4 E038ED 0 +OP4 E038EE 0 +OP4 E038EF 0 +OP4 E038F0 0 +OP4 E038F1 0 +OP4 E038F2 0 +OP4 E038F3 0 +OP4 E038F4 0 +OP4 E038F5 0 +OP4 E038F6 0 +OP4 E038F7 0 +OP4 E038F8 0 +OP4 E038F9 0 +OP4 E038FA 0 +OP4 E038FB 0 +OP4 E038FC 0 +OP4 E038FD 0 +OP4 E038FE 0 +OP4 E038FF 0 +OP4 E03900 0 +OP4 E03901 0 +OP4 E03902 0 +OP4 E03903 0 +OP4 E03904 0 +OP4 E03905 0 +OP4 E03906 0 +OP4 E03907 0 +OP4 E03908 0 +OP4 E03909 0 +OP4 E0390A 0 +OP4 E0390B 0 +OP4 E0390C 0 +OP4 E0390D 0 +OP4 E0390E 0 +OP4 E0390F 0 +OP4 E03910 0 +OP4 E03911 0 +OP4 E03912 0 +OP4 E03913 0 +OP4 E03914 0 +OP4 E03915 0 +OP4 E03916 0 +OP4 E03917 0 +OP4 E03918 0 +OP4 E03919 0 +OP4 E0391A 0 +OP4 E0391B 0 +OP4 E0391C 0 +OP4 E0391D 0 +OP4 E0391E 0 +OP4 E0391F 0 +OP4 E03920 0 +OP4 E03921 0 +OP4 E03922 0 +OP4 E03923 0 +OP4 E03924 0 +OP4 E03925 0 +OP4 E03926 0 +OP4 E03927 0 +OP4 E03928 0 +OP4 E03929 0 +OP4 E0392A 0 +OP4 E0392B 0 +OP4 E0392C 0 +OP4 E0392D 0 +OP4 E0392E 0 +OP4 E0392F 0 +OP4 E03930 0 +OP4 E03931 0 +OP4 E03932 0 +OP4 E03933 0 +OP4 E03934 0 +OP4 E03935 0 +OP4 E03936 0 +OP4 E03937 0 +OP4 E03938 0 +OP4 E03939 0 +OP4 E0393A 0 +OP4 E0393B 0 +OP4 E0393C 0 +OP4 E0393D 0 +OP4 E0393E 0 +OP4 E0393F 0 +OP4 E03940 0 +OP4 E03941 0 +OP4 E03942 0 +OP4 E03943 0 +OP4 E03944 0 +OP4 E03945 0 +OP4 E03946 0 +OP4 E03947 0 +OP4 E03948 0 +OP4 E03949 0 +OP4 E0394A 0 +OP4 E0394B 0 +OP4 E0394C 0 +OP4 E0394D 0 +OP4 E0394E 0 +OP4 E0394F 0 +OP4 E03950 0 +OP4 E03951 0 +OP4 E03952 0 +OP4 E03953 0 +OP4 E03954 0 +OP4 E03955 0 +OP4 E03956 0 +OP4 E03957 0 +OP4 E03958 0 +OP4 E03959 0 +OP4 E0395A 0 +OP4 E0395B 0 +OP4 E0395C 0 +OP4 E0395D 0 +OP4 E0395E 0 +OP4 E0395F 0 +OP4 E03960 0 +OP4 E03961 0 +OP4 E03962 0 +OP4 E03963 0 +OP4 E03964 0 +OP4 E03965 0 +OP4 E03966 0 +OP4 E03967 0 +OP4 E03968 0 +OP4 E03969 0 +OP4 E0396A 0 +OP4 E0396B 0 +OP4 E0396C 0 +OP4 E0396D 0 +OP4 E0396E 0 +OP4 E0396F 0 +OP4 E03970 0 +OP4 E03971 0 +OP4 E03972 0 +OP4 E03973 0 +OP4 E03974 0 +OP4 E03975 0 +OP4 E03976 0 +OP4 E03977 0 +OP4 E03978 0 +OP4 E03979 0 +OP4 E0397A 0 +OP4 E0397B 0 +OP4 E0397C 0 +OP4 E0397D 0 +OP4 E0397E 0 +OP4 E0397F 0 +OP4 E03980 0 +OP4 E03981 0 +OP4 E03982 0 +OP4 E03983 0 +OP4 E03984 0 +OP4 E03985 0 +OP4 E03986 0 +OP4 E03987 0 +OP4 E03988 0 +OP4 E03989 0 +OP4 E0398A 0 +OP4 E0398B 0 +OP4 E0398C 0 +OP4 E0398D 0 +OP4 E0398E 0 +OP4 E0398F 0 +OP4 E03990 0 +OP4 E03991 0 +OP4 E03992 0 +OP4 E03993 0 +OP4 E03994 0 +OP4 E03995 0 +OP4 E03996 0 +OP4 E03997 0 +OP4 E03998 0 +OP4 E03999 0 +OP4 E0399A 0 +OP4 E0399B 0 +OP4 E0399C 0 +OP4 E0399D 0 +OP4 E0399E 0 +OP4 E0399F 0 +OP4 E039A0 0 +OP4 E039A1 0 +OP4 E039A2 0 +OP4 E039A3 0 +OP4 E039A4 0 +OP4 E039A5 0 +OP4 E039A6 0 +OP4 E039A7 0 +OP4 E039A8 0 +OP4 E039A9 0 +OP4 E039AA 0 +OP4 E039AB 0 +OP4 E039AC 0 +OP4 E039AD 0 +OP4 E039AE 0 +OP4 E039AF 0 +OP4 E039B0 0 +OP4 E039B1 0 +OP4 E039B2 0 +OP4 E039B3 0 +OP4 E039B4 0 +OP4 E039B5 0 +OP4 E039B6 0 +OP4 E039B7 0 +OP4 E039B8 0 +OP4 E039B9 0 +OP4 E039BA 0 +OP4 E039BB 0 +OP4 E039BC 0 +OP4 E039BD 0 +OP4 E039BE 0 +OP4 E039BF 0 +OP4 E039C0 0 +OP4 E039C1 0 +OP4 E039C2 0 +OP4 E039C3 0 +OP4 E039C4 0 +OP4 E039C5 0 +OP4 E039C6 0 +OP4 E039C7 0 +OP4 E039C8 0 +OP4 E039C9 0 +OP4 E039CA 0 +OP4 E039CB 0 +OP4 E039CC 0 +OP4 E039CD 0 +OP4 E039CE 0 +OP4 E039CF 0 +OP4 E039D0 0 +OP4 E039D1 0 +OP4 E039D2 0 +OP4 E039D3 0 +OP4 E039D4 0 +OP4 E039D5 0 +OP4 E039D6 0 +OP4 E039D7 0 +OP4 E039D8 0 +OP4 E039D9 0 +OP4 E039DA 0 +OP4 E039DB 0 +OP4 E039DC 0 +OP4 E039DD 0 +OP4 E039DE 0 +OP4 E039DF 0 +OP4 E039E0 0 +OP4 E039E1 0 +OP4 E039E2 0 +OP4 E039E3 0 +OP4 E039E4 0 +OP4 E039E5 0 +OP4 E039E6 0 +OP4 E039E7 0 +OP4 E039E8 0 +OP4 E039E9 0 +OP4 E039EA 0 +OP4 E039EB 0 +OP4 E039EC 0 +OP4 E039ED 0 +OP4 E039EE 0 +OP4 E039EF 0 +OP4 E039F0 0 +OP4 E039F1 0 +OP4 E039F2 0 +OP4 E039F3 0 +OP4 E039F4 0 +OP4 E039F5 0 +OP4 E039F6 0 +OP4 E039F7 0 +OP4 E039F8 0 +OP4 E039F9 0 +OP4 E039FA 0 +OP4 E039FB 0 +OP4 E039FC 0 +OP4 E039FD 0 +OP4 E039FE 0 +OP4 E039FF 0 +OP4 E03A00 0 +OP4 E03A01 0 +OP4 E03A02 0 +OP4 E03A03 0 +OP4 E03A04 0 +OP4 E03A05 0 +OP4 E03A06 0 +OP4 E03A07 0 +OP4 E03A08 0 +OP4 E03A09 0 +OP4 E03A0A 0 +OP4 E03A0B 0 +OP4 E03A0C 0 +OP4 E03A0D 0 +OP4 E03A0E 0 +OP4 E03A0F 0 +OP4 E03A10 0 +OP4 E03A11 0 +OP4 E03A12 0 +OP4 E03A13 0 +OP4 E03A14 0 +OP4 E03A15 0 +OP4 E03A16 0 +OP4 E03A17 0 +OP4 E03A18 0 +OP4 E03A19 0 +OP4 E03A1A 0 +OP4 E03A1B 0 +OP4 E03A1C 0 +OP4 E03A1D 0 +OP4 E03A1E 0 +OP4 E03A1F 0 +OP4 E03A20 0 +OP4 E03A21 0 +OP4 E03A22 0 +OP4 E03A23 0 +OP4 E03A24 0 +OP4 E03A25 0 +OP4 E03A26 0 +OP4 E03A27 0 +OP4 E03A28 0 +OP4 E03A29 0 +OP4 E03A2A 0 +OP4 E03A2B 0 +OP4 E03A2C 0 +OP4 E03A2D 0 +OP4 E03A2E 0 +OP4 E03A2F 0 +OP4 E03A30 0 +OP4 E03A31 0 +OP4 E03A32 0 +OP4 E03A33 0 +OP4 E03A34 0 +OP4 E03A35 0 +OP4 E03A36 0 +OP4 E03A37 0 +OP4 E03A38 0 +OP4 E03A39 0 +OP4 E03A3A 0 +OP4 E03A3B 0 +OP4 E03A3C 0 +OP4 E03A3D 0 +OP4 E03A3E 0 +OP4 E03A3F 0 +OP4 E03A40 0 +OP4 E03A41 0 +OP4 E03A42 0 +OP4 E03A43 0 +OP4 E03A44 0 +OP4 E03A45 0 +OP4 E03A46 0 +OP4 E03A47 0 +OP4 E03A48 0 +OP4 E03A49 0 +OP4 E03A4A 0 +OP4 E03A4B 0 +OP4 E03A4C 0 +OP4 E03A4D 0 +OP4 E03A4E 0 +OP4 E03A4F 0 +OP4 E03A50 0 +OP4 E03A51 0 +OP4 E03A52 0 +OP4 E03A53 0 +OP4 E03A54 0 +OP4 E03A55 0 +OP4 E03A56 0 +OP4 E03A57 0 +OP4 E03A58 0 +OP4 E03A59 0 +OP4 E03A5A 0 +OP4 E03A5B 0 +OP4 E03A5C 0 +OP4 E03A5D 0 +OP4 E03A5E 0 +OP4 E03A5F 0 +OP4 E03A60 0 +OP4 E03A61 0 +OP4 E03A62 0 +OP4 E03A63 0 +OP4 E03A64 0 +OP4 E03A65 0 +OP4 E03A66 0 +OP4 E03A67 0 +OP4 E03A68 0 +OP4 E03A69 0 +OP4 E03A6A 0 +OP4 E03A6B 0 +OP4 E03A6C 0 +OP4 E03A6D 0 +OP4 E03A6E 0 +OP4 E03A6F 0 +OP4 E03A70 0 +OP4 E03A71 0 +OP4 E03A72 0 +OP4 E03A73 0 +OP4 E03A74 0 +OP4 E03A75 0 +OP4 E03A76 0 +OP4 E03A77 0 +OP4 E03A78 0 +OP4 E03A79 0 +OP4 E03A7A 0 +OP4 E03A7B 0 +OP4 E03A7C 0 +OP4 E03A7D 0 +OP4 E03A7E 0 +OP4 E03A7F 0 +OP4 E03A80 0 +OP4 E03A81 0 +OP4 E03A82 0 +OP4 E03A83 0 +OP4 E03A84 0 +OP4 E03A85 0 +OP4 E03A86 0 +OP4 E03A87 0 +OP4 E03A88 0 +OP4 E03A89 0 +OP4 E03A8A 0 +OP4 E03A8B 0 +OP4 E03A8C 0 +OP4 E03A8D 0 +OP4 E03A8E 0 +OP4 E03A8F 0 +OP4 E03A90 0 +OP4 E03A91 0 +OP4 E03A92 0 +OP4 E03A93 0 +OP4 E03A94 0 +OP4 E03A95 0 +OP4 E03A96 0 +OP4 E03A97 0 +OP4 E03A98 0 +OP4 E03A99 0 +OP4 E03A9A 0 +OP4 E03A9B 0 +OP4 E03A9C 0 +OP4 E03A9D 0 +OP4 E03A9E 0 +OP4 E03A9F 0 +OP4 E03AA0 0 +OP4 E03AA1 0 +OP4 E03AA2 0 +OP4 E03AA3 0 +OP4 E03AA4 0 +OP4 E03AA5 0 +OP4 E03AA6 0 +OP4 E03AA7 0 +OP4 E03AA8 0 +OP4 E03AA9 0 +OP4 E03AAA 0 +OP4 E03AAB 0 +OP4 E03AAC 0 +OP4 E03AAD 0 +OP4 E03AAE 0 +OP4 E03AAF 0 +OP4 E03AB0 0 +OP4 E03AB1 0 +OP4 E03AB2 0 +OP4 E03AB3 0 +OP4 E03AB4 0 +OP4 E03AB5 0 +OP4 E03AB6 0 +OP4 E03AB7 0 +OP4 E03AB8 0 +OP4 E03AB9 0 +OP4 E03ABA 0 +OP4 E03ABB 0 +OP4 E03ABC 0 +OP4 E03ABD 0 +OP4 E03ABE 0 +OP4 E03ABF 0 +OP4 E03AC0 0 +OP4 E03AC1 0 +OP4 E03AC2 0 +OP4 E03AC3 0 +OP4 E03AC4 0 +OP4 E03AC5 0 +OP4 E03AC6 0 +OP4 E03AC7 0 +OP4 E03AC8 0 +OP4 E03AC9 0 +OP4 E03ACA 0 +OP4 E03ACB 0 +OP4 E03ACC 0 +OP4 E03ACD 0 +OP4 E03ACE 0 +OP4 E03ACF 0 +OP4 E03AD0 0 +OP4 E03AD1 0 +OP4 E03AD2 0 +OP4 E03AD3 0 +OP4 E03AD4 0 +OP4 E03AD5 0 +OP4 E03AD6 0 +OP4 E03AD7 0 +OP4 E03AD8 0 +OP4 E03AD9 0 +OP4 E03ADA 0 +OP4 E03ADB 0 +OP4 E03ADC 0 +OP4 E03ADD 0 +OP4 E03ADE 0 +OP4 E03ADF 0 +OP4 E03AE0 0 +OP4 E03AE1 0 +OP4 E03AE2 0 +OP4 E03AE3 0 +OP4 E03AE4 0 +OP4 E03AE5 0 +OP4 E03AE6 0 +OP4 E03AE7 0 +OP4 E03AE8 0 +OP4 E03AE9 0 +OP4 E03AEA 0 +OP4 E03AEB 0 +OP4 E03AEC 0 +OP4 E03AED 0 +OP4 E03AEE 0 +OP4 E03AEF 0 +OP4 E03AF0 0 +OP4 E03AF1 0 +OP4 E03AF2 0 +OP4 E03AF3 0 +OP4 E03AF4 0 +OP4 E03AF5 0 +OP4 E03AF6 0 +OP4 E03AF7 0 +OP4 E03AF8 0 +OP4 E03AF9 0 +OP4 E03AFA 0 +OP4 E03AFB 0 +OP4 E03AFC 0 +OP4 E03AFD 0 +OP4 E03AFE 0 +OP4 E03AFF 0 +OP4 E03B00 0 +OP4 E03B01 0 +OP4 E03B02 0 +OP4 E03B03 0 +OP4 E03B04 0 +OP4 E03B05 0 +OP4 E03B06 0 +OP4 E03B07 0 +OP4 E03B08 0 +OP4 E03B09 0 +OP4 E03B0A 0 +OP4 E03B0B 0 +OP4 E03B0C 0 +OP4 E03B0D 0 +OP4 E03B0E 0 +OP4 E03B0F 0 +OP4 E03B10 0 +OP4 E03B11 0 +OP4 E03B12 0 +OP4 E03B13 0 +OP4 E03B14 0 +OP4 E03B15 0 +OP4 E03B16 0 +OP4 E03B17 0 +OP4 E03B18 0 +OP4 E03B19 0 +OP4 E03B1A 0 +OP4 E03B1B 0 +OP4 E03B1C 0 +OP4 E03B1D 0 +OP4 E03B1E 0 +OP4 E03B1F 0 +OP4 E03B20 0 +OP4 E03B21 0 +OP4 E03B22 0 +OP4 E03B23 0 +OP4 E03B24 0 +OP4 E03B25 0 +OP4 E03B26 0 +OP4 E03B27 0 +OP4 E03B28 0 +OP4 E03B29 0 +OP4 E03B2A 0 +OP4 E03B2B 0 +OP4 E03B2C 0 +OP4 E03B2D 0 +OP4 E03B2E 0 +OP4 E03B2F 0 +OP4 E03B30 0 +OP4 E03B31 0 +OP4 E03B32 0 +OP4 E03B33 0 +OP4 E03B34 0 +OP4 E03B35 0 +OP4 E03B36 0 +OP4 E03B37 0 +OP4 E03B38 0 +OP4 E03B39 0 +OP4 E03B3A 0 +OP4 E03B3B 0 +OP4 E03B3C 0 +OP4 E03B3D 0 +OP4 E03B3E 0 +OP4 E03B3F 0 +OP4 E03B40 0 +OP4 E03B41 0 +OP4 E03B42 0 +OP4 E03B43 0 +OP4 E03B44 0 +OP4 E03B45 0 +OP4 E03B46 0 +OP4 E03B47 0 +OP4 E03B48 0 +OP4 E03B49 0 +OP4 E03B4A 0 +OP4 E03B4B 0 +OP4 E03B4C 0 +OP4 E03B4D 0 +OP4 E03B4E 0 +OP4 E03B4F 0 +OP4 E03B50 0 +OP4 E03B51 0 +OP4 E03B52 0 +OP4 E03B53 0 +OP4 E03B54 0 +OP4 E03B55 0 +OP4 E03B56 0 +OP4 E03B57 0 +OP4 E03B58 0 +OP4 E03B59 0 +OP4 E03B5A 0 +OP4 E03B5B 0 +OP4 E03B5C 0 +OP4 E03B5D 0 +OP4 E03B5E 0 +OP4 E03B5F 0 +OP4 E03B60 0 +OP4 E03B61 0 +OP4 E03B62 0 +OP4 E03B63 0 +OP4 E03B64 0 +OP4 E03B65 0 +OP4 E03B66 0 +OP4 E03B67 0 +OP4 E03B68 0 +OP4 E03B69 0 +OP4 E03B6A 0 +OP4 E03B6B 0 +OP4 E03B6C 0 +OP4 E03B6D 0 +OP4 E03B6E 0 +OP4 E03B6F 0 +OP4 E03B70 0 +OP4 E03B71 0 +OP4 E03B72 0 +OP4 E03B73 0 +OP4 E03B74 0 +OP4 E03B75 0 +OP4 E03B76 0 +OP4 E03B77 0 +OP4 E03B78 0 +OP4 E03B79 0 +OP4 E03B7A 0 +OP4 E03B7B 0 +OP4 E03B7C 0 +OP4 E03B7D 0 +OP4 E03B7E 0 +OP4 E03B7F 0 +OP4 E03B80 0 +OP4 E03B81 0 +OP4 E03B82 0 +OP4 E03B83 0 +OP4 E03B84 0 +OP4 E03B85 0 +OP4 E03B86 0 +OP4 E03B87 0 +OP4 E03B88 0 +OP4 E03B89 0 +OP4 E03B8A 0 +OP4 E03B8B 0 +OP4 E03B8C 0 +OP4 E03B8D 0 +OP4 E03B8E 0 +OP4 E03B8F 0 +OP4 E03B90 0 +OP4 E03B91 0 +OP4 E03B92 0 +OP4 E03B93 0 +OP4 E03B94 0 +OP4 E03B95 0 +OP4 E03B96 0 +OP4 E03B97 0 +OP4 E03B98 0 +OP4 E03B99 0 +OP4 E03B9A 0 +OP4 E03B9B 0 +OP4 E03B9C 0 +OP4 E03B9D 0 +OP4 E03B9E 0 +OP4 E03B9F 0 +OP4 E03BA0 0 +OP4 E03BA1 0 +OP4 E03BA2 0 +OP4 E03BA3 0 +OP4 E03BA4 0 +OP4 E03BA5 0 +OP4 E03BA6 0 +OP4 E03BA7 0 +OP4 E03BA8 0 +OP4 E03BA9 0 +OP4 E03BAA 0 +OP4 E03BAB 0 +OP4 E03BAC 0 +OP4 E03BAD 0 +OP4 E03BAE 0 +OP4 E03BAF 0 +OP4 E03BB0 0 +OP4 E03BB1 0 +OP4 E03BB2 0 +OP4 E03BB3 0 +OP4 E03BB4 0 +OP4 E03BB5 0 +OP4 E03BB6 0 +OP4 E03BB7 0 +OP4 E03BB8 0 +OP4 E03BB9 0 +OP4 E03BBA 0 +OP4 E03BBB 0 +OP4 E03BBC 0 +OP4 E03BBD 0 +OP4 E03BBE 0 +OP4 E03BBF 0 +OP4 E03BC0 0 +OP4 E03BC1 0 +OP4 E03BC2 0 +OP4 E03BC3 0 +OP4 E03BC4 0 +OP4 E03BC5 0 +OP4 E03BC6 0 +OP4 E03BC7 0 +OP4 E03BC8 0 +OP4 E03BC9 0 +OP4 E03BCA 0 +OP4 E03BCB 0 +OP4 E03BCC 0 +OP4 E03BCD 0 +OP4 E03BCE 0 +OP4 E03BCF 0 +OP4 E03BD0 0 +OP4 E03BD1 0 +OP4 E03BD2 0 +OP4 E03BD3 0 +OP4 E03BD4 0 +OP4 E03BD5 0 +OP4 E03BD6 0 +OP4 E03BD7 0 +OP4 E03BD8 0 +OP4 E03BD9 0 +OP4 E03BDA 0 +OP4 E03BDB 0 +OP4 E03BDC 0 +OP4 E03BDD 0 +OP4 E03BDE 0 +OP4 E03BDF 0 +OP4 E03BE0 0 +OP4 E03BE1 0 +OP4 E03BE2 0 +OP4 E03BE3 0 +OP4 E03BE4 0 +OP4 E03BE5 0 +OP4 E03BE6 0 +OP4 E03BE7 0 +OP4 E03BE8 0 +OP4 E03BE9 0 +OP4 E03BEA 0 +OP4 E03BEB 0 +OP4 E03BEC 0 +OP4 E03BED 0 +OP4 E03BEE 0 +OP4 E03BEF 0 +OP4 E03BF0 0 +OP4 E03BF1 0 +OP4 E03BF2 0 +OP4 E03BF3 0 +OP4 E03BF4 0 +OP4 E03BF5 0 +OP4 E03BF6 0 +OP4 E03BF7 0 +OP4 E03BF8 0 +OP4 E03BF9 0 +OP4 E03BFA 0 +OP4 E03BFB 0 +OP4 E03BFC 0 +OP4 E03BFD 0 +OP4 E03BFE 0 +OP4 E03BFF 0 +OP4 E03C00 0 +OP4 E03C01 0 +OP4 E03C02 0 +OP4 E03C03 0 +OP4 E03C04 0 +OP4 E03C05 0 +OP4 E03C06 0 +OP4 E03C07 0 +OP4 E03C08 0 +OP4 E03C09 0 +OP4 E03C0A 0 +OP4 E03C0B 0 +OP4 E03C0C 0 +OP4 E03C0D 0 +OP4 E03C0E 0 +OP4 E03C0F 0 +OP4 E03C10 0 +OP4 E03C11 0 +OP4 E03C12 0 +OP4 E03C13 0 +OP4 E03C14 0 +OP4 E03C15 0 +OP4 E03C16 0 +OP4 E03C17 0 +OP4 E03C18 0 +OP4 E03C19 0 +OP4 E03C1A 0 +OP4 E03C1B 0 +OP4 E03C1C 0 +OP4 E03C1D 0 +OP4 E03C1E 0 +OP4 E03C1F 0 +OP4 E03C20 0 +OP4 E03C21 0 +OP4 E03C22 0 +OP4 E03C23 0 +OP4 E03C24 0 +OP4 E03C25 0 +OP4 E03C26 0 +OP4 E03C27 0 +OP4 E03C28 0 +OP4 E03C29 0 +OP4 E03C2A 0 +OP4 E03C2B 0 +OP4 E03C2C 0 +OP4 E03C2D 0 +OP4 E03C2E 0 +OP4 E03C2F 0 +OP4 E03C30 0 +OP4 E03C31 0 +OP4 E03C32 0 +OP4 E03C33 0 +OP4 E03C34 0 +OP4 E03C35 0 +OP4 E03C36 0 +OP4 E03C37 0 +OP4 E03C38 0 +OP4 E03C39 0 +OP4 E03C3A 0 +OP4 E03C3B 0 +OP4 E03C3C 0 +OP4 E03C3D 0 +OP4 E03C3E 0 +OP4 E03C3F 0 +OP4 E03C40 0 +OP4 E03C41 0 +OP4 E03C42 0 +OP4 E03C43 0 +OP4 E03C44 0 +OP4 E03C45 0 +OP4 E03C46 0 +OP4 E03C47 0 +OP4 E03C48 0 +OP4 E03C49 0 +OP4 E03C4A 0 +OP4 E03C4B 0 +OP4 E03C4C 0 +OP4 E03C4D 0 +OP4 E03C4E 0 +OP4 E03C4F 0 +OP4 E03C50 0 +OP4 E03C51 0 +OP4 E03C52 0 +OP4 E03C53 0 +OP4 E03C54 0 +OP4 E03C55 0 +OP4 E03C56 0 +OP4 E03C57 0 +OP4 E03C58 0 +OP4 E03C59 0 +OP4 E03C5A 0 +OP4 E03C5B 0 +OP4 E03C5C 0 +OP4 E03C5D 0 +OP4 E03C5E 0 +OP4 E03C5F 0 +OP4 E03C60 0 +OP4 E03C61 0 +OP4 E03C62 0 +OP4 E03C63 0 +OP4 E03C64 0 +OP4 E03C65 0 +OP4 E03C66 0 +OP4 E03C67 0 +OP4 E03C68 0 +OP4 E03C69 0 +OP4 E03C6A 0 +OP4 E03C6B 0 +OP4 E03C6C 0 +OP4 E03C6D 0 +OP4 E03C6E 0 +OP4 E03C6F 0 +OP4 E03C70 0 +OP4 E03C71 0 +OP4 E03C72 0 +OP4 E03C73 0 +OP4 E03C74 0 +OP4 E03C75 0 +OP4 E03C76 0 +OP4 E03C77 0 +OP4 E03C78 0 +OP4 E03C79 0 +OP4 E03C7A 0 +OP4 E03C7B 0 +OP4 E03C7C 0 +OP4 E03C7D 0 +OP4 E03C7E 0 +OP4 E03C7F 0 +OP4 E03C80 0 +OP4 E03C81 0 +OP4 E03C82 0 +OP4 E03C83 0 +OP4 E03C84 0 +OP4 E03C85 0 +OP4 E03C86 0 +OP4 E03C87 0 +OP4 E03C88 0 +OP4 E03C89 0 +OP4 E03C8A 0 +OP4 E03C8B 0 +OP4 E03C8C 0 +OP4 E03C8D 0 +OP4 E03C8E 0 +OP4 E03C8F 0 +OP4 E03C90 0 +OP4 E03C91 0 +OP4 E03C92 0 +OP4 E03C93 0 +OP4 E03C94 0 +OP4 E03C95 0 +OP4 E03C96 0 +OP4 E03C97 0 +OP4 E03C98 0 +OP4 E03C99 0 +OP4 E03C9A 0 +OP4 E03C9B 0 +OP4 E03C9C 0 +OP4 E03C9D 0 +OP4 E03C9E 0 +OP4 E03C9F 0 +OP4 E03CA0 0 +OP4 E03CA1 0 +OP4 E03CA2 0 +OP4 E03CA3 0 +OP4 E03CA4 0 +OP4 E03CA5 0 +OP4 E03CA6 0 +OP4 E03CA7 0 +OP4 E03CA8 0 +OP4 E03CA9 0 +OP4 E03CAA 0 +OP4 E03CAB 0 +OP4 E03CAC 0 +OP4 E03CAD 0 +OP4 E03CAE 0 +OP4 E03CAF 0 +OP4 E03CB0 0 +OP4 E03CB1 0 +OP4 E03CB2 0 +OP4 E03CB3 0 +OP4 E03CB4 0 +OP4 E03CB5 0 +OP4 E03CB6 0 +OP4 E03CB7 0 +OP4 E03CB8 0 +OP4 E03CB9 0 +OP4 E03CBA 0 +OP4 E03CBB 0 +OP4 E03CBC 0 +OP4 E03CBD 0 +OP4 E03CBE 0 +OP4 E03CBF 0 +OP4 E03CC0 0 +OP4 E03CC1 0 +OP4 E03CC2 0 +OP4 E03CC3 0 +OP4 E03CC4 0 +OP4 E03CC5 0 +OP4 E03CC6 0 +OP4 E03CC7 0 +OP4 E03CC8 0 +OP4 E03CC9 0 +OP4 E03CCA 0 +OP4 E03CCB 0 +OP4 E03CCC 0 +OP4 E03CCD 0 +OP4 E03CCE 0 +OP4 E03CCF 0 +OP4 E03CD0 0 +OP4 E03CD1 0 +OP4 E03CD2 0 +OP4 E03CD3 0 +OP4 E03CD4 0 +OP4 E03CD5 0 +OP4 E03CD6 0 +OP4 E03CD7 0 +OP4 E03CD8 0 +OP4 E03CD9 0 +OP4 E03CDA 0 +OP4 E03CDB 0 +OP4 E03CDC 0 +OP4 E03CDD 0 +OP4 E03CDE 0 +OP4 E03CDF 0 +OP4 E03CE0 0 +OP4 E03CE1 0 +OP4 E03CE2 0 +OP4 E03CE3 0 +OP4 E03CE4 0 +OP4 E03CE5 0 +OP4 E03CE6 0 +OP4 E03CE7 0 +OP4 E03CE8 0 +OP4 E03CE9 0 +OP4 E03CEA 0 +OP4 E03CEB 0 +OP4 E03CEC 0 +OP4 E03CED 0 +OP4 E03CEE 0 +OP4 E03CEF 0 +OP4 E03CF0 0 +OP4 E03CF1 0 +OP4 E03CF2 0 +OP4 E03CF3 0 +OP4 E03CF4 0 +OP4 E03CF5 0 +OP4 E03CF6 0 +OP4 E03CF7 0 +OP4 E03CF8 0 +OP4 E03CF9 0 +OP4 E03CFA 0 +OP4 E03CFB 0 +OP4 E03CFC 0 +OP4 E03CFD 0 +OP4 E03CFE 0 +OP4 E03CFF 0 +OP4 E03D00 0 +OP4 E03D01 0 +OP4 E03D02 0 +OP4 E03D03 0 +OP4 E03D04 0 +OP4 E03D05 0 +OP4 E03D06 0 +OP4 E03D07 0 +OP4 E03D08 0 +OP4 E03D09 0 +OP4 E03D0A 0 +OP4 E03D0B 0 +OP4 E03D0C 0 +OP4 E03D0D 0 +OP4 E03D0E 0 +OP4 E03D0F 0 +OP4 E03D10 0 +OP4 E03D11 0 +OP4 E03D12 0 +OP4 E03D13 0 +OP4 E03D14 0 +OP4 E03D15 0 +OP4 E03D16 0 +OP4 E03D17 0 +OP4 E03D18 0 +OP4 E03D19 0 +OP4 E03D1A 0 +OP4 E03D1B 0 +OP4 E03D1C 0 +OP4 E03D1D 0 +OP4 E03D1E 0 +OP4 E03D1F 0 +OP4 E03D20 0 +OP4 E03D21 0 +OP4 E03D22 0 +OP4 E03D23 0 +OP4 E03D24 0 +OP4 E03D25 0 +OP4 E03D26 0 +OP4 E03D27 0 +OP4 E03D28 0 +OP4 E03D29 0 +OP4 E03D2A 0 +OP4 E03D2B 0 +OP4 E03D2C 0 +OP4 E03D2D 0 +OP4 E03D2E 0 +OP4 E03D2F 0 +OP4 E03D30 0 +OP4 E03D31 0 +OP4 E03D32 0 +OP4 E03D33 0 +OP4 E03D34 0 +OP4 E03D35 0 +OP4 E03D36 0 +OP4 E03D37 0 +OP4 E03D38 0 +OP4 E03D39 0 +OP4 E03D3A 0 +OP4 E03D3B 0 +OP4 E03D3C 0 +OP4 E03D3D 0 +OP4 E03D3E 0 +OP4 E03D3F 0 +OP4 E03D40 0 +OP4 E03D41 0 +OP4 E03D42 0 +OP4 E03D43 0 +OP4 E03D44 0 +OP4 E03D45 0 +OP4 E03D46 0 +OP4 E03D47 0 +OP4 E03D48 0 +OP4 E03D49 0 +OP4 E03D4A 0 +OP4 E03D4B 0 +OP4 E03D4C 0 +OP4 E03D4D 0 +OP4 E03D4E 0 +OP4 E03D4F 0 +OP4 E03D50 0 +OP4 E03D51 0 +OP4 E03D52 0 +OP4 E03D53 0 +OP4 E03D54 0 +OP4 E03D55 0 +OP4 E03D56 0 +OP4 E03D57 0 +OP4 E03D58 0 +OP4 E03D59 0 +OP4 E03D5A 0 +OP4 E03D5B 0 +OP4 E03D5C 0 +OP4 E03D5D 0 +OP4 E03D5E 0 +OP4 E03D5F 0 +OP4 E03D60 0 +OP4 E03D61 0 +OP4 E03D62 0 +OP4 E03D63 0 +OP4 E03D64 0 +OP4 E03D65 0 +OP4 E03D66 0 +OP4 E03D67 0 +OP4 E03D68 0 +OP4 E03D69 0 +OP4 E03D6A 0 +OP4 E03D6B 0 +OP4 E03D6C 0 +OP4 E03D6D 0 +OP4 E03D6E 0 +OP4 E03D6F 0 +OP4 E03D70 0 +OP4 E03D71 0 +OP4 E03D72 0 +OP4 E03D73 0 +OP4 E03D74 0 +OP4 E03D75 0 +OP4 E03D76 0 +OP4 E03D77 0 +OP4 E03D78 0 +OP4 E03D79 0 +OP4 E03D7A 0 +OP4 E03D7B 0 +OP4 E03D7C 0 +OP4 E03D7D 0 +OP4 E03D7E 0 +OP4 E03D7F 0 +OP4 E03D80 0 +OP4 E03D81 0 +OP4 E03D82 0 +OP4 E03D83 0 +OP4 E03D84 0 +OP4 E03D85 0 +OP4 E03D86 0 +OP4 E03D87 0 +OP4 E03D88 0 +OP4 E03D89 0 +OP4 E03D8A 0 +OP4 E03D8B 0 +OP4 E03D8C 0 +OP4 E03D8D 0 +OP4 E03D8E 0 +OP4 E03D8F 0 +OP4 E03D90 0 +OP4 E03D91 0 +OP4 E03D92 0 +OP4 E03D93 0 +OP4 E03D94 0 +OP4 E03D95 0 +OP4 E03D96 0 +OP4 E03D97 0 +OP4 E03D98 0 +OP4 E03D99 0 +OP4 E03D9A 0 +OP4 E03D9B 0 +OP4 E03D9C 0 +OP4 E03D9D 0 +OP4 E03D9E 0 +OP4 E03D9F 0 +OP4 E03DA0 0 +OP4 E03DA1 0 +OP4 E03DA2 0 +OP4 E03DA3 0 +OP4 E03DA4 0 +OP4 E03DA5 0 +OP4 E03DA6 0 +OP4 E03DA7 0 +OP4 E03DA8 0 +OP4 E03DA9 0 +OP4 E03DAA 0 +OP4 E03DAB 0 +OP4 E03DAC 0 +OP4 E03DAD 0 +OP4 E03DAE 0 +OP4 E03DAF 0 +OP4 E03DB0 0 +OP4 E03DB1 0 +OP4 E03DB2 0 +OP4 E03DB3 0 +OP4 E03DB4 0 +OP4 E03DB5 0 +OP4 E03DB6 0 +OP4 E03DB7 0 +OP4 E03DB8 0 +OP4 E03DB9 0 +OP4 E03DBA 0 +OP4 E03DBB 0 +OP4 E03DBC 0 +OP4 E03DBD 0 +OP4 E03DBE 0 +OP4 E03DBF 0 +OP4 E03DC0 0 +OP4 E03DC1 0 +OP4 E03DC2 0 +OP4 E03DC3 0 +OP4 E03DC4 0 diff --git a/platform/mellanox/mft.mk b/platform/mellanox/mft.mk index 1c0efa6a3df3..5ef30af77c55 100644 --- a/platform/mellanox/mft.mk +++ b/platform/mellanox/mft.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. +# Copyright (c) 2016-2023 NVIDIA CORPORATION & AFFILIATES. # Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -16,8 +16,8 @@ # # Mellanox SAI -MFT_VERSION = 4.22.1 -MFT_REVISION = 15 +MFT_VERSION = 4.25.0 +MFT_REVISION = 62 MLNX_MFT_INTERNAL_SOURCE_BASE_URL = diff --git a/platform/mellanox/mlnx-fw-upgrade.j2 b/platform/mellanox/mlnx-fw-upgrade.j2 index 676d07cf3e49..188aa0bfa58f 100755 --- a/platform/mellanox/mlnx-fw-upgrade.j2 +++ b/platform/mellanox/mlnx-fw-upgrade.j2 @@ -1,3 +1,16 @@ +{# + Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. + Apache-2.0 + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + http://www.apache.org/licenses/LICENSE-2.0 + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +#} #!/bin/bash declare -r SCRIPT_NAME="$(basename "$0")" @@ -28,6 +41,7 @@ declare -r LIST_CONTENT_FILE="/tmp/mlxfwmanager-list-content.log" declare -r SPC1_ASIC="spc1" declare -r SPC2_ASIC="spc2" declare -r SPC3_ASIC="spc3" +declare -r SPC4_ASIC="spc4" declare -r UNKN_ASIC="unknown" declare -r UNKN_MST="unknown" @@ -35,6 +49,7 @@ declare -rA FW_FILE_MAP=( \ [$SPC1_ASIC]="fw-SPC.mfa" \ [$SPC2_ASIC]="fw-SPC2.mfa" \ [$SPC3_ASIC]="fw-SPC3.mfa" \ + [$SPC4_ASIC]="fw-SPC4.mfa" \ ) IMAGE_UPGRADE="${NO_PARAM}" @@ -160,6 +175,7 @@ function GetAsicType() { local -r SPC1_PRODUCT_ID="cb84" local -r SPC2_PRODUCT_ID="cf6c" local -r SPC3_PRODUCT_ID="cf70" + local -r SPC4_PRODUCT_ID="cf80" if lspci -n | grep "${VENDOR_ID}:${SPC1_PRODUCT_ID}" &>/dev/null; then echo "${SPC1_ASIC}" @@ -170,6 +186,9 @@ function GetAsicType() { elif lspci -n | grep "${VENDOR_ID}:${SPC3_PRODUCT_ID}" &>/dev/null; then echo "${SPC3_ASIC}" exit "${EXIT_SUCCESS}" + elif lspci -n | grep "${VENDOR_ID}:${SPC4_PRODUCT_ID}" &>/dev/null; then + echo "${SPC4_ASIC}" + exit "${EXIT_SUCCESS}" fi echo "${UNKN_ASIC}" diff --git a/platform/mellanox/mlnx-platform-api/sonic_platform/chassis.py b/platform/mellanox/mlnx-platform-api/sonic_platform/chassis.py index 5a2aaa59a769..e911c9617e1a 100644 --- a/platform/mellanox/mlnx-platform-api/sonic_platform/chassis.py +++ b/platform/mellanox/mlnx-platform-api/sonic_platform/chassis.py @@ -765,7 +765,6 @@ def initialize_reboot_cause(self): 'reset_hotswap_or_halt' : self.REBOOT_CAUSE_HARDWARE_OTHER, 'reset_voltmon_upgrade_fail': self.REBOOT_CAUSE_HARDWARE_OTHER, 'reset_reload_bios' : self.REBOOT_CAUSE_HARDWARE_BIOS, - 'reset_from_comex' : self.REBOOT_CAUSE_HARDWARE_CPU, 'reset_fw_reset' : self.REBOOT_CAUSE_HARDWARE_RESET_FROM_ASIC, 'reset_from_asic' : self.REBOOT_CAUSE_HARDWARE_RESET_FROM_ASIC, 'reset_long_pb' : self.REBOOT_CAUSE_HARDWARE_BUTTON, diff --git a/platform/mellanox/mlnx-platform-api/sonic_platform/component.py b/platform/mellanox/mlnx-platform-api/sonic_platform/component.py index 4befc7998425..ef1713f8f3be 100644 --- a/platform/mellanox/mlnx-platform-api/sonic_platform/component.py +++ b/platform/mellanox/mlnx-platform-api/sonic_platform/component.py @@ -1,5 +1,5 @@ # -# Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. +# Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. # Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -130,7 +130,7 @@ class ONIEUpdater(object): ONIE_FW_UPDATE_CMD_INSTALL = ['/usr/bin/mlnx-onie-fw-update.sh', 'update', '--no-reboot'] ONIE_FW_UPDATE_CMD_SHOW_PENDING = ['/usr/bin/mlnx-onie-fw-update.sh', 'show-pending'] - ONIE_VERSION_PARSE_PATTERN = '([0-9]{4})\.([0-9]{2})-([0-9]+)\.([0-9]+)\.([0-9]+)-([0-9]+)' + ONIE_VERSION_PARSE_PATTERN = '([0-9]{4})\.([0-9]{2})-([0-9]+)\.([0-9]+)\.([0-9]+)-?(dev)?-([0-9]+)' ONIE_VERSION_BASE_PARSE_PATTERN = '([0-9]+)\.([0-9]+)\.([0-9]+)' ONIE_VERSION_REQUIRED = '5.2.0016' @@ -145,14 +145,16 @@ class ONIEUpdater(object): # For SN2201, upgrading fireware from ONIE is supported from day one so we do not need to check it. PLATFORM_ALWAYS_SUPPORT_UPGRADE = ['x86_64-nvidia_sn2201-r0'] - BIOS_UPDATE_FILE_EXT = '.rom' - + BIOS_UPDATE_FILE_EXT_ROM = '.rom' + BIOS_UPDATE_FILE_EXT_CAB = '.cab' def __init__(self): self.platform = device_info.get_platform() def __add_prefix(self, image_path): - if self.BIOS_UPDATE_FILE_EXT not in image_path: + if image_path.endswith(self.BIOS_UPDATE_FILE_EXT_CAB): + return image_path; + elif self.BIOS_UPDATE_FILE_EXT_ROM not in image_path: rename_path = "/tmp/00-{}".format(os.path.basename(image_path)) else: rename_path = "/tmp/99-{}".format(os.path.basename(image_path)) @@ -279,7 +281,8 @@ def parse_onie_version(self, version, is_base=False): onie_major = m.group(3) onie_minor = m.group(4) onie_release = m.group(5) - onie_baudrate = m.group(6) + onie_signtype = m.group(6) + onie_baudrate = m.group(7) return onie_year, onie_month, onie_major, onie_minor, onie_release, onie_baudrate @@ -422,7 +425,7 @@ def _check_file_validity(self, image_path): name_list = os.path.splitext(image_path) if self.image_ext_name is not None: - if name_list[1] != self.image_ext_name: + if name_list[1] not in self.image_ext_name: print("ERROR: Extend name of file {} is wrong. Image for {} should have extend name {}".format(image_path, self.name, self.image_ext_name)) return False @@ -478,7 +481,7 @@ def update_firmware(self, image_path): class ComponentSSD(Component): COMPONENT_NAME = 'SSD' COMPONENT_DESCRIPTION = 'SSD - Solid-State Drive' - COMPONENT_FIRMWARE_EXTENSION = '.pkg' + COMPONENT_FIRMWARE_EXTENSION = ['.pkg'] FIRMWARE_VERSION_ATTR = 'Firmware Version' AVAILABLE_FIRMWARE_VERSION_ATTR = 'Available Firmware Version' @@ -533,8 +536,8 @@ def auto_update_firmware(self, image_path, boot_action): try: reboot_required = self.get_firmware_update_notification(image_path) is not None except RuntimeError as e: - return FW_AUTO_ERR_UNKNOWN - + return FW_AUTO_ERR_UNKNOWN + # Update if no reboot needed if not reboot_required: self.update_firmware(image_path) @@ -641,7 +644,7 @@ def update_firmware(self, image_path): class ComponentBIOS(Component): COMPONENT_NAME = 'BIOS' COMPONENT_DESCRIPTION = 'BIOS - Basic Input/Output System' - COMPONENT_FIRMWARE_EXTENSION = '.rom' + COMPONENT_FIRMWARE_EXTENSION = ['.rom', '.cab'] BIOS_VERSION_COMMAND = ['dmidecode', '--oem-string', '1'] @@ -725,7 +728,7 @@ def get_firmware_version(self): class ComponentCPLD(Component): COMPONENT_NAME = 'CPLD{}' COMPONENT_DESCRIPTION = 'CPLD - Complex Programmable Logic Device' - COMPONENT_FIRMWARE_EXTENSION = '.vme' + COMPONENT_FIRMWARE_EXTENSION = ['.vme'] MST_DEVICE_PATH = '/dev/mst' MST_DEVICE_PATTERN = 'mt[0-9]*_pci_cr0' @@ -807,9 +810,9 @@ def auto_update_firmware(self, image_path, boot_action): # Install burn. Error if fail. if not self.install_firmware(image_path): return FW_AUTO_ERR_UNKNOWN - + # Schedule refresh - return FW_AUTO_SCHEDULED + return FW_AUTO_SCHEDULED def get_firmware_version(self): part_number_file = self.CPLD_PART_NUMBER_FILE.format(self.idx) @@ -841,7 +844,7 @@ def get_available_firmware_version(self, image_path): def get_firmware_update_notification(self, image_path): name, ext = os.path.splitext(os.path.basename(image_path)) - if ext == self.COMPONENT_FIRMWARE_EXTENSION: + if ext in self.COMPONENT_FIRMWARE_EXTENSION: return "Power cycle (with 30 sec delay) or refresh image is required to complete {} firmware update".format(self.name) return "Immediate power cycle is required to complete {} firmware update".format(self.name) diff --git a/platform/mellanox/mlnx-platform-api/sonic_platform/sfp.py b/platform/mellanox/mlnx-platform-api/sonic_platform/sfp.py index 1011bd7cf1fd..aa83fd1455ec 100644 --- a/platform/mellanox/mlnx-platform-api/sonic_platform/sfp.py +++ b/platform/mellanox/mlnx-platform-api/sonic_platform/sfp.py @@ -1,5 +1,5 @@ # -# Copyright (c) 2019-2021 NVIDIA CORPORATION & AFFILIATES. +# Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. # Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -198,18 +198,6 @@ def deinitialize_sdk_handle(sdk_handle): return False -class SdkHandleContext(object): - def __init__(self): - self.sdk_handle = None - - def __enter__(self): - self.sdk_handle = initialize_sdk_handle() - return self.sdk_handle - - def __exit__(self, exc_type, exc_val, exc_tb): - deinitialize_sdk_handle(self.sdk_handle) - - class NvidiaSFPCommon(SfpOptoeBase): def __init__(self, sfp_index): super(NvidiaSFPCommon, self).__init__() diff --git a/platform/mellanox/mlnx-platform-api/sonic_platform/watchdog.py b/platform/mellanox/mlnx-platform-api/sonic_platform/watchdog.py index 879aabfd3530..2a032d3131f2 100644 --- a/platform/mellanox/mlnx-platform-api/sonic_platform/watchdog.py +++ b/platform/mellanox/mlnx-platform-api/sonic_platform/watchdog.py @@ -1,5 +1,5 @@ # -# Copyright (c) 2019-2021 NVIDIA CORPORATION & AFFILIATES. +# Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. # Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -80,7 +80,7 @@ def __init__(self, wd_device_path): super(WatchdogImplBase, self).__init__() self.watchdog_path = wd_device_path - self.watchdog = os.open(self.watchdog_path, os.O_WRONLY) + self.watchdog = self.open_handle() # Opening a watchdog descriptor starts # watchdog timer; @@ -90,6 +90,9 @@ def __init__(self, wd_device_path): self.timeout = self._gettimeout() + def open_handle(self): + return os.open(self.watchdog_path, os.O_WRONLY) + def _enablecard(self): """ Turn on the watchdog timer @@ -290,6 +293,7 @@ def get_watchdog(): for device in os.listdir("/dev/"): if device.startswith("watchdog") and is_mlnx_wd_main(device): watchdog_main_device_name = device + break if watchdog_main_device_name is None: return None diff --git a/platform/mellanox/mlnx-platform-api/tests/dmi_file b/platform/mellanox/mlnx-platform-api/tests/dmi_file new file mode 100644 index 000000000000..f9b1cdcd505b Binary files /dev/null and b/platform/mellanox/mlnx-platform-api/tests/dmi_file differ diff --git a/platform/mellanox/mlnx-platform-api/tests/test_chassis.py b/platform/mellanox/mlnx-platform-api/tests/test_chassis.py index cffdd437695f..d3a1fd95a7d1 100644 --- a/platform/mellanox/mlnx-platform-api/tests/test_chassis.py +++ b/platform/mellanox/mlnx-platform-api/tests/test_chassis.py @@ -1,5 +1,5 @@ # -# Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. +# Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. # Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -326,3 +326,8 @@ def test_get_port_or_cage_type(self): exceptionRaised = True assert exceptionRaised + + def test_parse_dmi(self): + chassis = Chassis() + content = chassis._parse_dmi(os.path.join(test_path, 'dmi_file')) + assert content.get('Version') == 'A4' diff --git a/platform/mellanox/mlnx-platform-api/tests/test_component.py b/platform/mellanox/mlnx-platform-api/tests/test_component.py new file mode 100644 index 000000000000..131220c27f90 --- /dev/null +++ b/platform/mellanox/mlnx-platform-api/tests/test_component.py @@ -0,0 +1,519 @@ +# +# Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. +# Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +import os +import pytest +import subprocess +import sys +if sys.version_info.major == 3: + from unittest import mock +else: + import mock + +test_path = os.path.dirname(os.path.abspath(__file__)) +modules_path = os.path.dirname(test_path) +sys.path.insert(0, modules_path) + +from sonic_platform.chassis import Chassis +from sonic_platform.component import ComponentONIE, \ + ComponentSSD, \ + ComponentBIOS, \ + ComponentBIOSSN2201, \ + ComponentCPLD, \ + ComponentCPLDSN2201, \ + MPFAManager, \ + ONIEUpdater, \ + Component +from sonic_platform_base.component_base import FW_AUTO_INSTALLED, \ + FW_AUTO_UPDATED, \ + FW_AUTO_SCHEDULED, \ + FW_AUTO_ERR_BOOT_TYPE, \ + FW_AUTO_ERR_IMAGE, \ + FW_AUTO_ERR_UNKNOWN + + +class TestComponent: + @mock.patch('sonic_platform.chassis.utils.is_host') + @mock.patch('sonic_platform.chassis.DeviceDataManager.get_cpld_component_list', mock.MagicMock(return_value=[])) + def test_chassis_component(self, mock_is_host): + mock_is_host.return_value = False + c = Chassis() + assert not c.get_all_components() + mock_is_host.return_value = True + component_list = c.get_all_components() + assert len(component_list) > 0 + assert c.get_num_components() > 0 + assert c.get_component(0) is not None + + @mock.patch('sonic_platform.component.ComponentONIE._check_file_validity') + @mock.patch('sonic_platform.component.ONIEUpdater', mock.MagicMock()) + def test_onie_component(self, mock_check_file): + c = ComponentONIE() + assert c.get_name() == 'ONIE' + assert c.get_description() == 'ONIE - Open Network Install Environment' + c.onie_updater.get_onie_version = mock.MagicMock(return_value='1.0') + assert c.get_firmware_version() == '1.0' + + c.onie_updater.get_onie_firmware_info = mock.MagicMock(return_value={}) + with pytest.raises(RuntimeError): + c.get_available_firmware_version('') + + c.onie_updater.get_onie_firmware_info = mock.MagicMock(return_value={'image_version': '1.1'}) + assert c.get_available_firmware_version('') == '1.1' + + assert c.get_firmware_update_notification('') == \ + 'Immediate cold reboot is required to complete ONIE firmware update' + + mock_check_file.return_value = False + assert not c.install_firmware('') + c.update_firmware('') + + mock_check_file.return_value = True + c.onie_updater.update_firmware = mock.MagicMock() + assert c.install_firmware('') + + c.onie_updater.update_firmware.side_effect = RuntimeError('') + assert not c.install_firmware('') + + @mock.patch('sonic_platform.component.os.path.exists') + @mock.patch('sonic_platform.component.subprocess.check_call') + @mock.patch('sonic_platform.component.subprocess.check_output') + def test_ssd_component(self, mock_check_output, mock_check_call, mock_exists): + c = ComponentSSD() + firmware_info = [ + 'Firmware Version:1.0', + 'Available Firmware Version:1.1', + 'Upgrade Required:yes', + 'Power Cycle Required:yes' + ] + mock_check_output.return_value = '\n'.join(firmware_info) + assert c.get_firmware_version() == '1.0' + assert c.get_available_firmware_version('') == '1.1' + assert c.get_firmware_update_notification('') == \ + 'Immediate power cycle is required to complete SSD firmware update' + mock_check_output.return_value = '' + with pytest.raises(RuntimeError): + c.get_firmware_version() + with pytest.raises(RuntimeError): + c.get_available_firmware_version('') + + mock_check_output.return_value = 'Upgrade Required:invalid' + with pytest.raises(RuntimeError): + c.get_available_firmware_version('') + with pytest.raises(RuntimeError): + c.get_firmware_update_notification('') + mock_check_output.return_value = 'Upgrade Required:no' + with pytest.raises(RuntimeError): + c.get_available_firmware_version('') + assert c.get_firmware_update_notification('') is None + mock_check_output.return_value = 'Upgrade Required:yes' + with pytest.raises(RuntimeError): + c.get_available_firmware_version('') + firmware_info = [ + 'Power Cycle Required:invalid', + 'Upgrade Required:yes' + ] + mock_check_output.return_value = '\n'.join(firmware_info) + with pytest.raises(RuntimeError): + c.get_firmware_update_notification('') + firmware_info = [ + 'Firmware Version:1.0', + 'Upgrade Required:yes' + ] + mock_check_output.side_effect = subprocess.CalledProcessError(1, None) + with pytest.raises(RuntimeError): + c.get_firmware_version() + with pytest.raises(RuntimeError): + c.get_available_firmware_version('') + with pytest.raises(RuntimeError): + c.get_firmware_update_notification('') + + # install firmware + c._check_file_validity = mock.MagicMock(return_value=False) + assert not c.install_firmware('') + c.update_firmware('') + + c._check_file_validity = mock.MagicMock(return_value=True) + assert c.install_firmware('') + mock_check_call.assert_called_with(c.SSD_FIRMWARE_UPDATE_COMMAND, universal_newlines=True) + assert c.install_firmware('', False) + mock_check_call.assert_called_with(c.SSD_FIRMWARE_INSTALL_COMMAND, universal_newlines=True) + mock_check_call.side_effect = subprocess.CalledProcessError(1, None) + assert not c.install_firmware('') + + # auto update firmware + mock_exists.return_value = False + assert c.auto_update_firmware('', '') == FW_AUTO_ERR_IMAGE + c.get_firmware_update_notification = mock.MagicMock(side_effect=RuntimeError('')) + mock_exists.return_value = True + assert c.auto_update_firmware('', '') == FW_AUTO_ERR_UNKNOWN + c.update_firmware = mock.MagicMock() + c.get_firmware_update_notification = mock.MagicMock(return_value=None) + assert c.auto_update_firmware('', '') == FW_AUTO_UPDATED + c.get_firmware_update_notification = mock.MagicMock(return_value='yes') + assert c.auto_update_firmware('', '') == FW_AUTO_ERR_BOOT_TYPE + assert c.auto_update_firmware('', 'cold') == FW_AUTO_SCHEDULED + + @mock.patch('sonic_platform.component.subprocess.check_output') + def test_bios_component(self, mock_check_output): + c = ComponentBIOS() + mock_check_output.return_value = '1.0' + assert c.get_firmware_version() == '1.0' + mock_check_output.side_effect = subprocess.CalledProcessError(1, None) + with pytest.raises(RuntimeError): + c.get_firmware_version() + with pytest.raises(RuntimeError): + c.get_available_firmware_version('') + assert c.get_firmware_update_notification('') == \ + 'Immediate cold reboot is required to complete BIOS firmware update' + c.onie_updater.is_non_onie_firmware_update_supported = mock.MagicMock(return_value=False) + assert not c.install_firmware('') + c.update_firmware('') + c.onie_updater.is_non_onie_firmware_update_supported = mock.MagicMock(return_value=True) + c._check_file_validity = mock.MagicMock(return_value=False) + assert not c.install_firmware('') + c._check_file_validity = mock.MagicMock(return_value=True) + c.onie_updater.update_firmware = mock.MagicMock() + assert c.install_firmware('') + c.onie_updater.update_firmware = mock.MagicMock(side_effect=RuntimeError('')) + assert not c.install_firmware('') + + @mock.patch('sonic_platform.component.subprocess.check_output') + def test_bios_2201_component(self, mock_check_output): + c = ComponentBIOSSN2201() + mock_check_output.return_value = 'Version: 1.0' + assert c.get_firmware_version() == '1.0' + mock_check_output.return_value = '' + assert c.get_firmware_version() == 'Unknown version' + mock_check_output.side_effect = subprocess.CalledProcessError(1, None) + with pytest.raises(RuntimeError): + c.get_firmware_version() + + @mock.patch('sonic_platform.component.MPFAManager.cleanup', mock.MagicMock()) + @mock.patch('sonic_platform.component.MPFAManager.extract', mock.MagicMock()) + @mock.patch('sonic_platform.component.subprocess.check_call') + @mock.patch('sonic_platform.component.MPFAManager.get_path') + @mock.patch('sonic_platform.component.MPFAManager.get_metadata') + @mock.patch('sonic_platform.component.os.path.exists') + def test_cpld_component(self, mock_exists, mock_get_meta_data, mock_get_path, mock_check_call): + c = ComponentCPLD(1) + c._read_generic_file = mock.MagicMock(side_effect=[None, '1', None]) + assert c.get_firmware_version() == 'CPLD000000_REV0100' + + assert c.get_firmware_update_notification('a.txt') == \ + 'Immediate power cycle is required to complete CPLD1 firmware update' + assert c.get_firmware_update_notification('a.vme') == \ + 'Power cycle (with 30 sec delay) or refresh image is required to complete CPLD1 firmware update' + + mock_meta_data = mock.MagicMock() + mock_meta_data.has_option = mock.MagicMock(return_value=False) + mock_get_meta_data.return_value = mock_meta_data + with pytest.raises(RuntimeError): + c.get_available_firmware_version('') + mock_meta_data.has_option = mock.MagicMock(return_value=True) + mock_meta_data.get = mock.MagicMock(return_value='1.1') + assert c.get_available_firmware_version('') == '1.1' + + c._check_file_validity = mock.MagicMock(return_value=False) + assert not c._install_firmware('') + c._check_file_validity = mock.MagicMock(return_value=True) + c._ComponentCPLD__get_mst_device = mock.MagicMock(return_value=None) + assert not c._install_firmware('') + c._ComponentCPLD__get_mst_device = mock.MagicMock(return_value='some dev') + assert c._install_firmware('') + mock_check_call.side_effect = subprocess.CalledProcessError(1, None) + assert not c._install_firmware('') + + c._install_firmware = mock.MagicMock() + mock_meta_data.has_option = mock.MagicMock(return_value=False) + with pytest.raises(RuntimeError): + c.install_firmware('a.mpfa') + mock_get_path.return_value = '/tmp' + mock_meta_data.has_option = mock.MagicMock(return_value=True) + mock_meta_data.get = mock.MagicMock(return_value='some_firmware') + c.install_firmware('a.mpfa') + c._install_firmware.assert_called_with('/tmp/some_firmware') + c._install_firmware.reset_mock() + c.install_firmware('a.txt') + c._install_firmware.assert_called_with('a.txt') + + mock_meta_data.has_option = mock.MagicMock(return_value=False) + with pytest.raises(RuntimeError): + c.update_firmware('a.mpfa') + mock_meta_data.has_option = mock.MagicMock(side_effect=[True, False]) + with pytest.raises(RuntimeError): + c.update_firmware('a.mpfa') + mock_meta_data.has_option = mock.MagicMock(return_value=True) + mock_meta_data.get = mock.MagicMock(side_effect=['burn', 'refresh']) + c._install_firmware.reset_mock() + c.update_firmware('a.mpfa') + assert c._install_firmware.call_count == 2 + c._install_firmware.reset_mock() + c._install_firmware.return_value = False + mock_meta_data.get = mock.MagicMock(side_effect=['burn', 'refresh']) + c.update_firmware('a.mpfa') + assert c._install_firmware.call_count == 1 + + mock_exists.return_value = False + assert c.auto_update_firmware('', '') == FW_AUTO_ERR_IMAGE + mock_exists.return_value = True + assert c.auto_update_firmware('', '') == FW_AUTO_ERR_BOOT_TYPE + c.install_firmware = mock.MagicMock(return_value=False) + assert c.auto_update_firmware('', 'cold') == FW_AUTO_ERR_UNKNOWN + c.install_firmware = mock.MagicMock(return_value=True) + assert c.auto_update_firmware('', 'cold') == FW_AUTO_SCHEDULED + + @mock.patch('sonic_platform.component.ComponentCPLD._read_generic_file', mock.MagicMock(return_value='3')) + def test_cpld_get_component_list(self): + component_list = ComponentCPLD.get_component_list() + assert len(component_list) == 3 + for index, item in enumerate(component_list): + assert item.name == 'CPLD{}'.format(index + 1) + + def test_cpld_get_mst_device(self): + ComponentCPLD.MST_DEVICE_PATH = '/tmp/mst' + os.system('rm -rf /tmp/mst') + c = ComponentCPLD(1) + assert c._ComponentCPLD__get_mst_device() is None + os.makedirs(ComponentCPLD.MST_DEVICE_PATH) + assert c._ComponentCPLD__get_mst_device() is None + with open('/tmp/mst/mt0_pci_cr0', 'w+') as f: + f.write('dummy') + assert c._ComponentCPLD__get_mst_device() == '/tmp/mst/mt0_pci_cr0' + + @mock.patch('sonic_platform.component.subprocess.check_call') + def test_cpld_2201_component(self, mock_check_call): + c = ComponentCPLDSN2201(1) + assert c._install_firmware('') + mock_check_call.side_effect = subprocess.CalledProcessError(1, None) + assert not c._install_firmware('') + + @mock.patch('sonic_platform.component.MPFAManager.cleanup') + @mock.patch('sonic_platform.component.MPFAManager.extract') + def test_mpfa_manager_context(self, mock_extract, mock_cleanup): + with MPFAManager('some_path') as mpfa: + assert isinstance(mpfa, MPFAManager) + mock_extract.assert_called_once() + mock_cleanup.assert_not_called() + mock_cleanup.assert_called_once() + + @mock.patch('sonic_platform.component.tempfile.mkdtemp', mock.MagicMock(return_value='/tmp/mpfa')) + @mock.patch('sonic_platform.component.subprocess.check_call', mock.MagicMock()) + @mock.patch('sonic_platform.component.os.path.isfile') + def test_mpfa_manager_extract_cleanup(self, mock_isfile): + m = MPFAManager('some_path') + mock_isfile.return_value = False + with pytest.raises(RuntimeError): + m.extract() + mock_isfile.return_value = True + with pytest.raises(RuntimeError): + m.extract() + m = MPFAManager('some_path.mpfa') + mock_isfile.side_effect = [True, False] + with pytest.raises(RuntimeError): + m.extract() + mock_isfile.side_effect = None + os.makedirs('/tmp/mpfa', exist_ok=True) + with open('/tmp/mpfa/metadata.ini', 'w+') as f: + f.write('[section1]\n') + f.write('a=b') + m = MPFAManager('some_path.mpfa') + m.extract() + assert m.get_path() == '/tmp/mpfa' + assert m.is_extracted() + assert m.get_metadata() is not None + # extract twice and verify no issue + m.extract() + m.cleanup() + assert m.get_path() is None + assert not m.is_extracted() + assert m.get_metadata() is None + + def test_onie_updater_parse_onie_version(self): + o = ONIEUpdater() + onie_year, onie_month, onie_major, onie_minor, onie_release, onie_baudrate = \ + o.parse_onie_version('2022.08-5.3.0010-9600') + assert onie_year == '2022' + assert onie_month == '08' + assert onie_major == '5' + assert onie_minor == '3' + assert onie_release == '0010' + assert onie_baudrate == '9600' + with pytest.raises(RuntimeError): + o.parse_onie_version('invalid', is_base=True) + with pytest.raises(RuntimeError): + o.parse_onie_version('invalid', is_base=False) + onie_year, onie_month, onie_major, onie_minor, onie_release, onie_baudrate = \ + o.parse_onie_version('2022.08-5.3.0010-9600', is_base=True) + assert onie_year is None + assert onie_month is None + assert onie_major == '5' + assert onie_minor == '3' + assert onie_release == '0010' + assert onie_baudrate is None + + assert o.get_onie_required_version() == o.ONIE_VERSION_REQUIRED + + @mock.patch('sonic_platform.component.ONIEUpdater.get_onie_version') + @mock.patch('sonic_platform.component.device_info.get_platform') + def test_onie_updater_is_non_onie_firmware_update_supported(self, mock_platform, mock_version): + mock_platform.return_value = 'x86_64-nvidia_sn5600-r0' + o = ONIEUpdater() + mock_version.return_value = '2022.08-5.3.0010-9600' + assert o.is_non_onie_firmware_update_supported() + mock_version.return_value = '2022.08-5.1.0010-9600' + assert not o.is_non_onie_firmware_update_supported() + + mock_platform.return_value = 'x86_64-nvidia_sn2201-r0' + o = ONIEUpdater() + assert o.is_non_onie_firmware_update_supported() + + def test_onie_updater_get_onie_version(self): + o = ONIEUpdater() + o._ONIEUpdater__mount_onie_fs = mock.MagicMock() + o._ONIEUpdater__umount_onie_fs = mock.MagicMock() + mock_os_open = mock.mock_open(read_data='') + with mock.patch('sonic_platform.component.open', mock_os_open): + with pytest.raises(RuntimeError): + o.get_onie_version() + o._ONIEUpdater__umount_onie_fs.assert_called_once() + + mock_os_open = mock.mock_open(read_data='onie_version') + with mock.patch('sonic_platform.component.open', mock_os_open): + with pytest.raises(RuntimeError): + o.get_onie_version() + + mock_os_open = mock.mock_open(read_data='onie_version=2022.08-5.1.0010-9600') + with mock.patch('sonic_platform.component.open', mock_os_open): + assert o.get_onie_version() == '2022.08-5.1.0010-9600' + + @mock.patch('sonic_platform.component.subprocess.check_output') + def test_onie_updater_get_onie_firmware_info(self, mock_check_output): + o = ONIEUpdater() + o._ONIEUpdater__mount_onie_fs = mock.MagicMock() + o._ONIEUpdater__umount_onie_fs = mock.MagicMock() + mock_check_output.return_value = 'a' + with pytest.raises(RuntimeError): + o.get_onie_firmware_info('') + o._ONIEUpdater__umount_onie_fs.assert_called_once() + mock_check_output.return_value = 'a=b' + fi = o.get_onie_firmware_info('') + assert fi == {'a':'b'} + mock_check_output.side_effect = subprocess.CalledProcessError(1, None) + with pytest.raises(RuntimeError): + o.get_onie_firmware_info('') + + def test_onie_updater_update_firmware(self): + o = ONIEUpdater() + o._ONIEUpdater__stage_update = mock.MagicMock() + o._ONIEUpdater__trigger_update = mock.MagicMock() + o._ONIEUpdater__is_update_staged = mock.MagicMock() + o._ONIEUpdater__unstage_update = mock.MagicMock() + o.update_firmware('') + o._ONIEUpdater__stage_update.assert_called_once() + o._ONIEUpdater__trigger_update.assert_called_once() + o._ONIEUpdater__is_update_staged.assert_not_called() + o._ONIEUpdater__unstage_update.assert_not_called() + o._ONIEUpdater__is_update_staged.return_value = False + o._ONIEUpdater__stage_update.side_effect = RuntimeError('') + with pytest.raises(RuntimeError): + o.update_firmware('') + o._ONIEUpdater__unstage_update.assert_not_called() + o._ONIEUpdater__is_update_staged.return_value = True + with pytest.raises(RuntimeError): + o.update_firmware('') + o._ONIEUpdater__unstage_update.assert_called_once() + + @mock.patch('sonic_platform.component.os.path.lexists') + @mock.patch('sonic_platform.component.os.path.exists', mock.MagicMock(return_value=False)) + @mock.patch('sonic_platform.component.os.mkdir', mock.MagicMock()) + @mock.patch('sonic_platform.component.subprocess.check_call', mock.MagicMock()) + @mock.patch('sonic_platform.component.os.symlink', mock.MagicMock()) + @mock.patch('sonic_platform.component.check_output_pipe', mock.MagicMock()) + def test_onie_updater_mount_onie_fs(self, mock_lexists): + o = ONIEUpdater() + o._ONIEUpdater__umount_onie_fs = mock.MagicMock() + mock_lexists.return_value = False + mp = o._ONIEUpdater__mount_onie_fs() + assert mp == '/mnt/onie-fs' + o._ONIEUpdater__umount_onie_fs.assert_not_called() + mock_lexists.return_value = True + o._ONIEUpdater__mount_onie_fs() + o._ONIEUpdater__umount_onie_fs.assert_called_once() + + @mock.patch('sonic_platform.component.os.rmdir') + @mock.patch('sonic_platform.component.os.path.exists', mock.MagicMock(return_value=True)) + @mock.patch('sonic_platform.component.subprocess.check_call') + @mock.patch('sonic_platform.component.os.path.ismount', mock.MagicMock(return_value=True)) + @mock.patch('sonic_platform.component.os.unlink') + @mock.patch('sonic_platform.component.os.path.islink', mock.MagicMock(return_value=True)) + def test_onie_updater_umount_onie_fs(self, mock_unlink, mock_check_call, mock_rmdir): + o = ONIEUpdater() + o._ONIEUpdater__umount_onie_fs() + mock_unlink.assert_called_once() + mock_check_call.assert_called_once() + mock_rmdir.assert_called_once() + + @mock.patch('sonic_platform.component.subprocess.check_output') + @mock.patch('sonic_platform.component.subprocess.check_call') + @mock.patch('sonic_platform.component.copyfile', mock.MagicMock()) + def test_onie_updater_stage(self, mock_check_call, mock_check_output): + o = ONIEUpdater() + o._ONIEUpdater__stage_update('') + mock_check_call.assert_called_once() + + mock_check_call.reset_mock() + o._ONIEUpdater__unstage_update('a.rom') + mock_check_call.assert_called_once() + + mock_check_call.reset_mock() + o._ONIEUpdater__trigger_update(True) + mock_check_call.assert_called_with(o.ONIE_FW_UPDATE_CMD_UPDATE, universal_newlines=True) + mock_check_call.reset_mock() + o._ONIEUpdater__trigger_update(False) + mock_check_call.assert_called_with(o.ONIE_FW_UPDATE_CMD_INSTALL, universal_newlines=True) + + mock_check_output.return_value = 'invalid/' + assert not o._ONIEUpdater__is_update_staged('') + mock_check_output.return_value = '00-' + assert o._ONIEUpdater__is_update_staged('') + + mock_check_call.side_effect = subprocess.CalledProcessError(1, None) + with pytest.raises(RuntimeError): + o._ONIEUpdater__stage_update('') + with pytest.raises(RuntimeError): + o._ONIEUpdater__unstage_update('') + with pytest.raises(RuntimeError): + o._ONIEUpdater__trigger_update(True) + mock_check_output.side_effect = subprocess.CalledProcessError(1, None) + with pytest.raises(RuntimeError): + o._ONIEUpdater__is_update_staged('') + + def test_read_generic_file(self): + with pytest.raises(RuntimeError): + Component._read_generic_file('invalid', 1) + content = Component._read_generic_file(os.path.abspath(__file__), 1) + assert content == '#' + + def test_check_file_validity(self): + c = ComponentONIE() + assert not c._check_file_validity('invalid') + assert c._check_file_validity(os.path.abspath(__file__)) + c.image_ext_name = '.py' + assert c._check_file_validity(os.path.abspath(__file__)) + c.image_ext_name = '.txt' + assert not c._check_file_validity(os.path.abspath(__file__)) diff --git a/platform/mellanox/mlnx-platform-api/tests/test_device_data.py b/platform/mellanox/mlnx-platform-api/tests/test_device_data.py new file mode 100644 index 000000000000..d99591d513c8 --- /dev/null +++ b/platform/mellanox/mlnx-platform-api/tests/test_device_data.py @@ -0,0 +1,56 @@ +# +# Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. +# Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +import os +import pytest +import subprocess +import sys +if sys.version_info.major == 3: + from unittest import mock +else: + import mock + +test_path = os.path.dirname(os.path.abspath(__file__)) +modules_path = os.path.dirname(test_path) +sys.path.insert(0, modules_path) + +from sonic_platform.device_data import DeviceDataManager + + +class TestDeviceData: + @mock.patch('sonic_platform.device_data.utils.read_int_from_file', mock.MagicMock(return_value=1)) + def test_is_fan_hotswapable(self): + assert DeviceDataManager.is_fan_hotswapable() + + @mock.patch('sonic_platform.device_data.utils.read_int_from_file', mock.MagicMock(return_value=1)) + def test_get_linecard_sfp_count(self): + assert DeviceDataManager.get_linecard_sfp_count(1) == 1 + + @mock.patch('sonic_platform.device_data.utils.read_int_from_file', mock.MagicMock(return_value=1)) + def test_get_gearbox_count(self): + assert DeviceDataManager.get_gearbox_count('') == 1 + + @mock.patch('sonic_platform.device_data.DeviceDataManager.get_platform_name', mock.MagicMock(return_value='x86_64-mlnx_msn3420-r0')) + def test_get_linecard_max_port_count(self): + assert DeviceDataManager.get_linecard_max_port_count() == 0 + + @mock.patch('sonic_platform.device_data.DeviceDataManager.get_platform_name', mock.MagicMock(return_value='x86_64-nvidia_sn2201-r0')) + def test_get_bios_component(self): + assert DeviceDataManager.get_bios_component() is not None + + + diff --git a/platform/mellanox/mlnx-platform-api/tests/test_led.py b/platform/mellanox/mlnx-platform-api/tests/test_led.py index a46daec16879..3e60016a0703 100644 --- a/platform/mellanox/mlnx-platform-api/tests/test_led.py +++ b/platform/mellanox/mlnx-platform-api/tests/test_led.py @@ -1,5 +1,5 @@ # -# Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. +# Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. # Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -179,3 +179,40 @@ def test_fixed_psu_led(self): psu = FixedPsu(0) physical_led = psu.led self._verify_non_shared_led(physical_led, psu) + + def test_get_actual_color(self): + led = Led() + assert led._get_actual_color('red') is None + led.supported_colors.add('orange') + assert led._get_actual_color('red') is 'orange' + + @mock.patch('os.path.exists') + @mock.patch('time.sleep', mock.MagicMock()) + def test_wait_files_ready(self, mock_exists): + mock_exists.side_effect = [True, True] + led = Led() + assert led._wait_files_ready(['a', 'b']) + mock_exists.side_effect = [False, False, True, True] + assert led._wait_files_ready(['a', 'b']) + mock_exists.side_effect = None + mock_exists.return_value = False + assert not led._wait_files_ready(['a', 'b']) + + @mock.patch('sonic_platform.utils.write_file') + @mock.patch('sonic_platform.led.Led.get_led_path', mock.MagicMock()) + @mock.patch('sonic_platform.led.Led._stop_blink', mock.MagicMock()) + @mock.patch('sonic_platform.led.Led.get_capability', mock.MagicMock()) + @mock.patch('sonic_platform.device_data.DeviceDataManager.is_simx_platform', mock.MagicMock(return_value=False)) + def test_get_set_led_status(self, mock_write): + led = Led() + led._led_id = 'fan' + led.supported_colors.add('red') + led.supported_colors.add('green') + assert not led.set_status('black') + assert led.set_status(led.STATUS_LED_COLOR_OFF) + assert mock_write.call_count == 2 + mock_write.side_effect = ValueError('') + assert not led.set_status(led.STATUS_LED_COLOR_OFF) + + led.supported_colors.clear() + assert led.get_status() == led.STATUS_LED_COLOR_OFF diff --git a/platform/mellanox/mlnx-platform-api/tests/test_pcie.py b/platform/mellanox/mlnx-platform-api/tests/test_pcie.py new file mode 100644 index 000000000000..781fd74fe9f0 --- /dev/null +++ b/platform/mellanox/mlnx-platform-api/tests/test_pcie.py @@ -0,0 +1,67 @@ +# +# Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. +# Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +import os +import sys +if sys.version_info.major == 3: + from unittest import mock +else: + import mock + +test_path = os.path.dirname(os.path.abspath(__file__)) +modules_path = os.path.dirname(test_path) +sys.path.insert(0, modules_path) + +from sonic_platform.pcie import Pcie + + +class TestPcie: + @mock.patch('sonic_platform.pcie.Pcie._create_device_id_to_bus_map', mock.MagicMock()) + @mock.patch('sonic_platform.pcie.Pcie.load_config_file', mock.MagicMock()) + def test_get_pcie_check(self): + p = Pcie('') + p._device_id_to_bus_map = {} + p.confInfo = [ + { + 'id': '1f0b', + 'dev': '00', + 'fn': '00' + } + ] + info = p.get_pcie_check() + assert info[0]['result'] == 'Failed' + + p.check_pcie_sysfs = mock.MagicMock(return_value=False) + p._device_id_to_bus_map = {'1f0b': '00'} + info = p.get_pcie_check() + assert info[0]['result'] == 'Failed' + + p.check_pcie_sysfs = mock.MagicMock(return_value=True) + info = p.get_pcie_check() + assert info[0]['result'] == 'Passed' + + @mock.patch('sonic_platform.pcie.os.listdir') + @mock.patch('sonic_platform.pcie.Pcie.load_config_file', mock.MagicMock()) + def test_create_device_id_to_bus_map(self, mock_dir): + p = Pcie('') + assert not p._device_id_to_bus_map + mock_dir.return_value = ['0000:01:00.0'] + + mock_os_open = mock.mock_open(read_data='0x23') + with mock.patch('sonic_platform.pcie.open', mock_os_open): + p._create_device_id_to_bus_map() + assert p._device_id_to_bus_map == {'23':'01'} diff --git a/platform/mellanox/mlnx-platform-api/tests/test_psu.py b/platform/mellanox/mlnx-platform-api/tests/test_psu.py index 2882776b6252..2c67fa999993 100644 --- a/platform/mellanox/mlnx-platform-api/tests/test_psu.py +++ b/platform/mellanox/mlnx-platform-api/tests/test_psu.py @@ -37,8 +37,14 @@ def test_fixed_psu(self): assert psu.get_model() == 'N/A' assert psu.get_serial() == 'N/A' assert psu.get_revision() == 'N/A' + avail, msg = psu.get_power_available_status() + assert not avail + assert msg == 'absence of power' utils.read_int_from_file = mock.MagicMock(return_value=1) assert psu.get_powergood_status() + avail, msg = psu.get_power_available_status() + assert avail + assert msg == '' utils.read_int_from_file = mock.MagicMock(return_value=0) assert not psu.get_powergood_status() assert psu.get_presence() @@ -69,6 +75,7 @@ def test_psu(self): psu.psu_temp_threshold: 50678, psu.psu_voltage_in: 102345, psu.psu_current_in: 676, + psu.psu_power_max: 1234567 } def mock_read_int_from_file(file_path, **kwargs): @@ -77,8 +84,12 @@ def mock_read_int_from_file(file_path, **kwargs): utils.read_int_from_file = mock_read_int_from_file utils.read_str_from_file = mock.MagicMock(return_value='min max') assert psu.get_presence() is True + assert psu.get_maximum_supplied_power() == 1.234567 mock_sysfs_content[psu.psu_presence] = 0 assert psu.get_presence() is False + avail, msg = psu.get_power_available_status() + assert not avail + assert msg == 'absence of PSU' assert psu.get_powergood_status() is True mock_sysfs_content[psu.psu_oper_status] = 0 @@ -91,6 +102,7 @@ def mock_read_int_from_file(file_path, **kwargs): assert psu.get_temperature_high_threshold() is None assert psu.get_input_voltage() is None assert psu.get_input_current() is None + assert psu.get_maximum_supplied_power() is None mock_sysfs_content[psu.psu_oper_status] = 1 assert psu.get_voltage() == 10.234 diff --git a/platform/mellanox/mlnx-platform-api/tests/test_sfp.py b/platform/mellanox/mlnx-platform-api/tests/test_sfp.py index 6cba2bb28627..57c221340c13 100644 --- a/platform/mellanox/mlnx-platform-api/tests/test_sfp.py +++ b/platform/mellanox/mlnx-platform-api/tests/test_sfp.py @@ -1,5 +1,5 @@ # -# Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. +# Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. # Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -37,6 +37,7 @@ class TestSfp: @mock.patch('sonic_platform.device_data.DeviceDataManager.get_linecard_max_port_count') def test_sfp_index(self, mock_max_port): sfp = SFP(0) + assert sfp.is_replaceable() assert sfp.sdk_index == 0 assert sfp.index == 1 @@ -267,3 +268,25 @@ def test_set_lpmode(self, mock_read_int, mock_write): assert sfp.set_lpmode(True) mock_write.assert_called_with('/sys/module/sx_core/asic0/module0/power_mode_policy', '2') + + @mock.patch('sonic_platform.sfp.SFP.read_eeprom') + def test_get_xcvr_api(self, mock_read): + sfp = SFP(0) + api = sfp.get_xcvr_api() + assert api is None + mock_read.return_value = bytearray([0x18]) + api = sfp.get_xcvr_api() + assert api is not None + + def test_rj45_basic(self): + sfp = RJ45Port(0) + assert not sfp.get_lpmode() + assert not sfp.reset() + assert not sfp.set_lpmode(True) + assert not sfp.get_error_description() + assert not sfp.get_reset_status() + assert sfp.read_eeprom(0, 0) is None + assert sfp.get_transceiver_info() + assert sfp.get_transceiver_bulk_status() + assert sfp.get_transceiver_threshold_info() + sfp.reinit() diff --git a/platform/mellanox/mlnx-platform-api/tests/test_thermal.py b/platform/mellanox/mlnx-platform-api/tests/test_thermal.py index 5d96d4661b6f..d906fdf4e02f 100644 --- a/platform/mellanox/mlnx-platform-api/tests/test_thermal.py +++ b/platform/mellanox/mlnx-platform-api/tests/test_thermal.py @@ -1,5 +1,5 @@ # -# Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. +# Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. # Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -42,7 +42,6 @@ class TestThermal: @mock.patch('sonic_platform.device_data.DeviceDataManager.get_platform_name', mock.MagicMock(return_value='x86_64-mlnx_msn2700-r0')) def test_chassis_thermal(self): from sonic_platform.thermal import THERMAL_NAMING_RULE - os.path.exists = mock.MagicMock(return_value=True) chassis = Chassis() thermal_list = chassis.get_all_thermals() assert thermal_list @@ -123,9 +122,9 @@ def test_chassis_thermal_includes(self, mock_capability): thermal_name = rule['name'] assert thermal_name in thermal_dict + @mock.patch('os.path.exists', mock.MagicMock(return_value=True)) def test_psu_thermal(self): from sonic_platform.thermal import initialize_psu_thermal, THERMAL_NAMING_RULE - os.path.exists = mock.MagicMock(return_value=True) presence_cb = mock.MagicMock(return_value=(True, '')) thermal_list = initialize_psu_thermal(0, presence_cb) assert len(thermal_list) == 1 @@ -147,9 +146,9 @@ def test_psu_thermal(self): assert thermal.get_high_threshold() is None assert thermal.get_high_critical_threshold() is None + @mock.patch('os.path.exists', mock.MagicMock(return_value=True)) def test_sfp_thermal(self): from sonic_platform.thermal import initialize_sfp_thermal, THERMAL_NAMING_RULE - os.path.exists = mock.MagicMock(return_value=True) thermal_list = initialize_sfp_thermal(0) assert len(thermal_list) == 1 thermal = thermal_list[0] @@ -162,66 +161,65 @@ def test_sfp_thermal(self): assert thermal.get_position_in_parent() == 1 assert thermal.is_replaceable() == False - def test_get_temperature(self): + @mock.patch('sonic_platform.utils.read_float_from_file') + def test_get_temperature(self, mock_read): from sonic_platform.thermal import Thermal - from sonic_platform import utils thermal = Thermal('test', 'temp_file', None, None, 1) - utils.read_float_from_file = mock.MagicMock(return_value=35727) + mock_read.return_value = 35727 assert thermal.get_temperature() == 35.727 - utils.read_float_from_file = mock.MagicMock(return_value=0.0) + mock_read.return_value = 0.0 assert thermal.get_temperature() is None - utils.read_float_from_file = mock.MagicMock(return_value=None) + mock_read.return_value = None assert thermal.get_temperature() is None - def test_get_high_threshold(self): + @mock.patch('sonic_platform.utils.read_float_from_file') + def test_get_high_threshold(self, mock_read): from sonic_platform.thermal import Thermal - from sonic_platform import utils thermal = Thermal('test', None, None, None, 1) assert thermal.get_high_threshold() is None thermal.high_threshold = 'high_th_file' - utils.read_float_from_file = mock.MagicMock(return_value=25833) + mock_read.return_value = 25833 assert thermal.get_temperature() == 25.833 - utils.read_float_from_file = mock.MagicMock(return_value=0.0) + mock_read.return_value = 0.0 assert thermal.get_temperature() is None - utils.read_float_from_file = mock.MagicMock(return_value=None) + mock_read.return_value = None assert thermal.get_temperature() is None - def test_get_high_critical_threshold(self): + @mock.patch('sonic_platform.utils.read_float_from_file') + def test_get_high_critical_threshold(self, mock_read): from sonic_platform.thermal import Thermal - from sonic_platform import utils thermal = Thermal('test', None, None, None, 1) assert thermal.get_high_critical_threshold() is None thermal.high_critical_threshold = 'high_th_file' - utils.read_float_from_file = mock.MagicMock(return_value=120839) + mock_read.return_value = 120839 assert thermal.get_high_critical_threshold() == 120.839 - utils.read_float_from_file = mock.MagicMock(return_value=0.0) + mock_read.return_value = 0.0 assert thermal.get_high_critical_threshold() is None - utils.read_float_from_file = mock.MagicMock(return_value=None) + mock_read.return_value = None assert thermal.get_high_critical_threshold() is None - def test_set_thermal_algorithm_status(self): + @mock.patch('glob.iglob', mock.MagicMock(return_value=['thermal_zone1', 'thermal_zone2'])) + @mock.patch('sonic_platform.utils.write_file') + def test_set_thermal_algorithm_status(self, mock_write): from sonic_platform.thermal import Thermal, THERMAL_ZONE_FOLDER_WILDCARD, THERMAL_ZONE_POLICY_FILE, THERMAL_ZONE_MODE_FILE - from sonic_platform import utils - glob.iglob = mock.MagicMock(return_value=['thermal_zone1', 'thermal_zone2']) - utils.write_file = mock.MagicMock() assert Thermal.set_thermal_algorithm_status(True, False) for folder in glob.iglob(THERMAL_ZONE_FOLDER_WILDCARD): - utils.write_file.assert_any_call(os.path.join(folder, THERMAL_ZONE_POLICY_FILE), 'step_wise') - utils.write_file.assert_any_call(os.path.join(folder, THERMAL_ZONE_MODE_FILE), 'enabled') + mock_write.assert_any_call(os.path.join(folder, THERMAL_ZONE_POLICY_FILE), 'step_wise') + mock_write.assert_any_call(os.path.join(folder, THERMAL_ZONE_MODE_FILE), 'enabled') assert Thermal.set_thermal_algorithm_status(False, False) for folder in glob.iglob(THERMAL_ZONE_FOLDER_WILDCARD): - utils.write_file.assert_any_call(os.path.join(folder, THERMAL_ZONE_POLICY_FILE), 'user_space') - utils.write_file.assert_any_call(os.path.join(folder, THERMAL_ZONE_MODE_FILE), 'disabled') + mock_write.assert_any_call(os.path.join(folder, THERMAL_ZONE_POLICY_FILE), 'user_space') + mock_write.assert_any_call(os.path.join(folder, THERMAL_ZONE_MODE_FILE), 'disabled') assert not Thermal.set_thermal_algorithm_status(False, False) @@ -283,10 +281,10 @@ def mock_read_int_from_file(file_path, **kwargs): mock_file_content[os.path.join('thermal_zone2', THERMAL_ZONE_TEMP_FILE)] = 81000 assert Thermal.get_min_allowed_cooling_level_by_thermal_zone() is None + @mock.patch('glob.iglob', mock.MagicMock(return_value=['thermal_zone1', 'thermal_zone2'])) def test_check_module_temperature_trustable(self): from sonic_platform.thermal import Thermal from sonic_platform import utils - glob.iglob = mock.MagicMock(return_value=['thermal_zone1', 'thermal_zone2']) utils.read_int_from_file = mock.MagicMock(return_value=1) assert Thermal.check_module_temperature_trustable() == 'untrust' diff --git a/platform/mellanox/mlnx-platform-api/tests/test_utils.py b/platform/mellanox/mlnx-platform-api/tests/test_utils.py index 5e01fc70dc0e..ad474433bfe8 100644 --- a/platform/mellanox/mlnx-platform-api/tests/test_utils.py +++ b/platform/mellanox/mlnx-platform-api/tests/test_utils.py @@ -1,5 +1,5 @@ # -# Copyright (c) 2021 NVIDIA CORPORATION & AFFILIATES. +# Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. # Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -122,12 +122,45 @@ def func(): def test_run_command(self): output = utils.run_command(['ls']) assert output + assert utils.run_command(['not_a_command']) is None + def test_run_command_exception(self): + output = utils.run_command(['ls']) + assert output + + @mock.patch('sonic_platform.utils.load_json_file') + @mock.patch('os.path.exists') + @mock.patch('sonic_py_common.device_info.get_path_to_port_config_file', mock.MagicMock(return_value='')) @mock.patch('sonic_py_common.device_info.get_path_to_hwsku_dir', mock.MagicMock(return_value='/tmp')) - def test_extract_RJ45_ports_index(self): + def test_extract_RJ45_ports_index(self, mock_exists, mock_load_json): + mock_exists.return_value = False rj45_list = utils.extract_RJ45_ports_index() assert rj45_list is None + mock_exists.return_value = True + platform_json = { + 'interfaces': { + "Ethernet0": { + "index": "1", + "lanes": "0", + "breakout_modes": { + "1x1000[100,10]": ["etp1"] + } + } + } + } + hwsku_json = { + 'interfaces': { + "Ethernet0": { + "default_brkout_mode": "1x1000[100,10]", + "port_type": "RJ45" + } + } + } + + mock_load_json.side_effect = [platform_json, hwsku_json] + assert utils.extract_RJ45_ports_index() == [0] + def test_wait_until(self): values = [] assert utils.wait_until(lambda: len(values) == 0, timeout=1) @@ -141,3 +174,20 @@ def thread_func(items): t.start() assert utils.wait_until(lambda: len(values) > 0, timeout=5) t.join() + + def test_load_json_file(self): + assert utils.load_json_file('some_file') is None + + mock_os_open = mock.mock_open(read_data='') + with mock.patch('sonic_platform.utils.open', mock_os_open): + assert utils.load_json_file('some_file') is None + + mock_os_open = mock.mock_open(read_data='{"a": "b"}') + with mock.patch('sonic_platform.utils.open', mock_os_open): + data = utils.load_json_file('some_file') + assert data['a'] == 'b' + + def test_read_key_value_file(self): + mock_os_open = mock.mock_open(read_data='a:b') + with mock.patch('sonic_platform.utils.open', mock_os_open): + assert utils.read_key_value_file('some_file') == {'a':'b'} diff --git a/platform/mellanox/mlnx-platform-api/tests/test_watchdog.py b/platform/mellanox/mlnx-platform-api/tests/test_watchdog.py new file mode 100644 index 000000000000..d3dff9db8735 --- /dev/null +++ b/platform/mellanox/mlnx-platform-api/tests/test_watchdog.py @@ -0,0 +1,129 @@ +# +# Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. +# Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# + +import os +import pytest +import sys +if sys.version_info.major == 3: + from unittest import mock +else: + import mock + +test_path = os.path.dirname(os.path.abspath(__file__)) +modules_path = os.path.dirname(test_path) +sys.path.insert(0, modules_path) + +from sonic_platform.chassis import Chassis +from sonic_platform.watchdog import get_watchdog, \ + WatchdogType2, \ + WatchdogType1, \ + is_mlnx_wd_main, \ + is_wd_type2 + + +class TestWatchdog: + @mock.patch('sonic_platform.watchdog.is_mlnx_wd_main') + @mock.patch('sonic_platform.watchdog.os.listdir') + def test_get_watchdog_no_device(self, mock_listdir, mock_is_main): + mock_listdir.return_value = [] + assert get_watchdog() is None + + mock_listdir.return_value = ['invalid'] + mock_is_main.return_value = True + assert get_watchdog() is None + + mock_listdir.return_value = ['watchdog1'] + mock_is_main.return_value = False + assert get_watchdog() is None + + @mock.patch('sonic_platform.watchdog.is_mlnx_wd_main') + @mock.patch('sonic_platform.watchdog.is_wd_type2') + @mock.patch('sonic_platform.watchdog.os.listdir', mock.MagicMock(return_value=['watchdog1', 'watchdog2'])) + @mock.patch('sonic_platform.watchdog.WatchdogImplBase.open_handle', mock.MagicMock()) + @mock.patch('sonic_platform.watchdog.fcntl.ioctl', mock.MagicMock()) + @pytest.mark.parametrize('test_para', + [(True, WatchdogType2), (False, WatchdogType1)]) + def test_get_watchdog(self, mock_is_type2, mock_is_main, test_para): + mock_is_main.side_effect = lambda dev: dev == 'watchdog2' + mock_is_type2.return_value = test_para[0] + chassis = Chassis() + watchdog = chassis.get_watchdog() + assert isinstance(watchdog, test_para[1]) + assert watchdog.watchdog_path == '/dev/watchdog2' + + def test_is_mlnx_wd_main(self): + mock_os_open = mock.mock_open(read_data='mlx-wdt-main') + with mock.patch('sonic_platform.watchdog.open', mock_os_open): + assert is_mlnx_wd_main('') + + mock_os_open = mock.mock_open(read_data='invalid') + with mock.patch('sonic_platform.watchdog.open', mock_os_open): + assert not is_mlnx_wd_main('') + mock_os_open.side_effect = IOError + with mock.patch('sonic_platform.watchdog.open', mock_os_open): + assert not is_mlnx_wd_main('') + + @mock.patch('sonic_platform.watchdog.os.path.exists') + @pytest.mark.parametrize('test_para', + [True, False]) + def test_is_wd_type2(self, mock_exists, test_para): + mock_exists.return_value = test_para + assert is_wd_type2('') is test_para + + @mock.patch('sonic_platform.watchdog.WatchdogImplBase.open_handle', mock.MagicMock()) + @mock.patch('sonic_platform.watchdog.fcntl.ioctl', mock.MagicMock()) + def test_arm_disarm_watchdog2(self): + watchdog = WatchdogType2('watchdog2') + assert watchdog.arm(-1) == -1 + assert not watchdog.is_armed() + watchdog.arm(10) + assert watchdog.is_armed() + watchdog.arm(5) + assert watchdog.is_armed() + watchdog.disarm() + assert not watchdog.is_armed() + + @mock.patch('sonic_platform.watchdog.WatchdogImplBase.open_handle', mock.MagicMock()) + @mock.patch('sonic_platform.watchdog.fcntl.ioctl', mock.MagicMock()) + def test_arm_disarm_watchdog1(self): + watchdog = WatchdogType1('watchdog1') + assert watchdog.arm(-1) == -1 + assert not watchdog.is_armed() + watchdog.arm(10) + assert watchdog.is_armed() + watchdog.arm(5) + assert watchdog.is_armed() + watchdog.disarm() + assert not watchdog.is_armed() + + @mock.patch('sonic_platform.watchdog.WatchdogImplBase.open_handle', mock.MagicMock()) + @mock.patch('sonic_platform.watchdog.fcntl.ioctl', mock.MagicMock()) + @mock.patch('sonic_platform.watchdog.WatchdogImplBase._gettimeleft', mock.MagicMock(return_value=10)) + def test_get_remaining_time_watchdog2(self): + watchdog = WatchdogType2('watchdog2') + assert watchdog.get_remaining_time() == -1 + watchdog.arm(10) + assert watchdog.get_remaining_time() == 10 + + @mock.patch('sonic_platform.watchdog.WatchdogImplBase.open_handle', mock.MagicMock()) + @mock.patch('sonic_platform.watchdog.fcntl.ioctl', mock.MagicMock()) + @mock.patch('sonic_platform.watchdog.WatchdogImplBase._gettimeleft', mock.MagicMock(return_value=10)) + def test_get_remaining_time_watchdog1(self): + watchdog = WatchdogType1('watchdog2') + assert watchdog.get_remaining_time() == -1 + watchdog.arm(10) + assert watchdog.get_remaining_time() > 0 diff --git a/platform/mellanox/mlnx-sai.mk b/platform/mellanox/mlnx-sai.mk index 2714d473943b..39015f758f03 100644 --- a/platform/mellanox/mlnx-sai.mk +++ b/platform/mellanox/mlnx-sai.mk @@ -1,8 +1,21 @@ # Mellanox SAI -MLNX_SAI_VERSION = SAIBuild2305.24.0.1 +MLNX_SAI_VERSION = SAIBuild2305.25.0.3 +MLNX_SAI_ASSETS_GITHUB_URL = https://github.com/Mellanox/Spectrum-SDK-Drivers-SONiC-Bins +MLNX_SAI_ASSETS_RELEASE_TAG = sai-$(MLNX_SAI_VERSION)-$(BLDENV)-$(CONFIGURED_ARCH) +MLNX_SAI_ASSETS_URL = $(MLNX_ASSETS_GITHUB_URL)/releases/download/$(MLNX_SAI_ASSETS_RELEASE_TAG) +MLNX_SAI_DEB_VERSION = $(subst -,.,$(subst _,.,$(MLNX_SAI_VERSION))) -export MLNX_SAI_VERSION +# Place here URL where SAI sources exist +MLNX_SAI_SOURCE_BASE_URL = + +ifneq ($(MLNX_SAI_SOURCE_BASE_URL), ) +SAI_FROM_SRC = y +else +SAI_FROM_SRC = n +endif + +export MLNX_SAI_VERSION MLNX_SAI_SOURCE_BASE_URL MLNX_SAI = mlnx-sai_1.mlnx.$(MLNX_SAI_VERSION)_$(CONFIGURED_ARCH).deb $(MLNX_SAI)_SRC_PATH = $(PLATFORM_PATH)/mlnx-sai @@ -11,4 +24,16 @@ $(MLNX_SAI)_RDEPENDS += $(MLNX_SDK_RDEBS) $(MLNX_SDK_DEBS) $(eval $(call add_conflict_package,$(MLNX_SAI),$(LIBSAIVS_DEV))) MLNX_SAI_DBGSYM = mlnx-sai-dbgsym_1.mlnx.$(MLNX_SAI_VERSION)_$(CONFIGURED_ARCH).deb $(eval $(call add_derived_package,$(MLNX_SAI),$(MLNX_SAI_DBGSYM))) + +define make_url + $(1)_URL = $(MLNX_SAI_ASSETS_URL)/$(1) + +endef + +$(eval $(foreach deb,$(MLNX_SAI) $(MLNX_SAI_DBGSYM),$(call make_url,$(deb)))) + +ifeq ($(SAI_FROM_SRC), y) SONIC_MAKE_DEBS += $(MLNX_SAI) +else +SONIC_ONLINE_DEBS += $(MLNX_SAI) +endif diff --git a/platform/mellanox/mlnx-sai/.gitignore b/platform/mellanox/mlnx-sai/.gitignore new file mode 100644 index 000000000000..7e5cb7d266aa --- /dev/null +++ b/platform/mellanox/mlnx-sai/.gitignore @@ -0,0 +1,6 @@ +# Ignore everything in this directory +* +# Except this file +!.gitignore +!Makefile + diff --git a/platform/mellanox/mlnx-sai/Makefile b/platform/mellanox/mlnx-sai/Makefile index 55c453e77e6d..ecfba91fd752 100644 --- a/platform/mellanox/mlnx-sai/Makefile +++ b/platform/mellanox/mlnx-sai/Makefile @@ -6,12 +6,11 @@ MAIN_TARGET = mlnx-sai_1.mlnx.$(MLNX_SAI_VERSION)_$(CONFIGURED_ARCH).deb DERIVED_TARGETS = mlnx-sai-dbgsym_1.mlnx.$(MLNX_SAI_VERSION)_$(CONFIGURED_ARCH).deb $(addprefix $(DEST)/, $(MAIN_TARGET)): $(DEST)/% : - pushd SAI-Implementation + rm -rf mlnx_sai + wget -c $(MLNX_SAI_SOURCE_BASE_URL)/$(MLNX_SAI_VERSION).tar.gz -O - | tar -xz pushd mlnx_sai - chmod a+x autogen.sh debuild -e 'make_extra_flags="DEFS=-DACS_OS -DCONFIG_SYSLOG"' -us -uc -d -b popd mv $(DERIVED_TARGETS) $* $(DEST)/ - popd diff --git a/platform/mellanox/mlnx-sai/SAI-Implementation b/platform/mellanox/mlnx-sai/SAI-Implementation deleted file mode 160000 index ec7fa674f143..000000000000 --- a/platform/mellanox/mlnx-sai/SAI-Implementation +++ /dev/null @@ -1 +0,0 @@ -Subproject commit ec7fa674f143809e602a56b6ef5d279ade8b77d2 diff --git a/platform/mellanox/one-image.mk b/platform/mellanox/one-image.mk index ad912e260d1e..74365cfea430 100644 --- a/platform/mellanox/one-image.mk +++ b/platform/mellanox/one-image.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2017-2021 NVIDIA CORPORATION & AFFILIATES. +# Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. # Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -19,7 +19,7 @@ SONIC_ONE_IMAGE = sonic-mellanox.bin $(SONIC_ONE_IMAGE)_MACHINE = mellanox $(SONIC_ONE_IMAGE)_IMAGE_TYPE = onie -$(SONIC_ONE_IMAGE)_INSTALLS += $(SX_KERNEL) $(KERNEL_MFT) $(MFT_OEM) $(MFT) $(MLNX_HW_MANAGEMENT) +$(SONIC_ONE_IMAGE)_INSTALLS += $(SX_KERNEL) $(KERNEL_MFT) $(MFT_OEM) $(MFT) $(MFT_FWTRACE_CFG) $(MLNX_HW_MANAGEMENT) $(SONIC_ONE_IMAGE)_INSTALLS += $(SYSTEMD_SONIC_GENERATOR) ifeq ($(INSTALL_DEBUG_TOOLS),y) $(SONIC_ONE_IMAGE)_DOCKERS += $(SONIC_INSTALL_DOCKER_DBG_IMAGES) diff --git a/platform/mellanox/rules.mk b/platform/mellanox/rules.mk index a640fd093889..654c6b65ab4f 100644 --- a/platform/mellanox/rules.mk +++ b/platform/mellanox/rules.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. +# Copyright (c) 2016-2023 NVIDIA CORPORATION & AFFILIATES. # Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -17,6 +17,7 @@ include $(PLATFORM_PATH)/sdk.mk include $(PLATFORM_PATH)/fw.mk include $(PLATFORM_PATH)/mft.mk +include $(PLATFORM_PATH)/mft-fwtrace-cfg.mk include $(PLATFORM_PATH)/mlnx-sai.mk include $(PLATFORM_PATH)/hw-management.mk include $(PLATFORM_PATH)/mlnx-platform-api.mk diff --git a/platform/mellanox/sdk-src/sx-obj-desc-lib/Makefile b/platform/mellanox/sdk-src/sx-obj-desc-lib/Makefile new file mode 100644 index 000000000000..26d1f65ca720 --- /dev/null +++ b/platform/mellanox/sdk-src/sx-obj-desc-lib/Makefile @@ -0,0 +1,29 @@ +.ONESHELL: +SHELL = /bin/bash + +MAIN_TARGET = sx-obj-desc-lib_1.mlnx.$(MLNX_SDK_DEB_VERSION)_$(CONFIGURED_ARCH).deb +DERIVED_TARGETS = sx-obj-desc-lib-dev_1.mlnx.$(MLNX_SDK_DEB_VERSION)_$(CONFIGURED_ARCH).deb \ + sx-obj-desc-lib-dev-static_1.mlnx.$(MLNX_SDK_DEB_VERSION)_$(CONFIGURED_ARCH).deb \ + sx-obj-desc-lib-dbgsym_1.mlnx.$(MLNX_SDK_DEB_VERSION)_$(CONFIGURED_ARCH).deb +PACKAGE_NAME = sx_obj_desc_lib + +$(addprefix $(DEST)/, $(MAIN_TARGET)): $(DEST)/% : + # get sources + rm -rf $(PACKAGE_NAME)-$(MLNX_SDK_VERSION)-$(MLNX_SDK_ISSU_VERSION) + + wget -c $(MLNX_SDK_SOURCE_BASE_URL)/$(PACKAGE_NAME)-$(MLNX_SDK_VERSION)-$(MLNX_SDK_ISSU_VERSION).tar.gz -O - | tar -xz + + # build + pushd $(PACKAGE_NAME)-$(MLNX_SDK_VERSION)-$(MLNX_SDK_ISSU_VERSION) + + if [ -f autogen.sh ]; then + ./autogen.sh + fi + + debuild -b -us -uc -j$(SONIC_CONFIG_MAKE_JOBS) + + popd + + mv $(DERIVED_TARGETS) $* $(DEST)/ + +$(addprefix $(DEST)/, $(DERIVED_TARGETS)): $(DEST)/% : $(DEST)/$(MAIN_TARGET) diff --git a/platform/mellanox/sdk.dep b/platform/mellanox/sdk.dep index e5be175286c4..122548192c6c 100644 --- a/platform/mellanox/sdk.dep +++ b/platform/mellanox/sdk.dep @@ -94,27 +94,6 @@ $(SX_GEN_UTILS_DBGSYM)_DEP_FLAGS := $(MLNX_SDK_COMMON_FLAGS_LIST) $(SX_GEN_UTILS_DBGSYM)_DEP_FILES := $(DEP_FILES) endif -# SX_SCEW - -SPATH := $($(SX_SCEW)_SRC_PATH) -DEP_FILES := $(SONIC_COMMON_FILES_LIST) $(PLATFORM_PATH)/sdk.mk $(PLATFORM_PATH)/sdk.dep -DEP_FILES += $(SONIC_COMMON_BASE_FILES_LIST) -DEP_FILES += $(shell git ls-files -- $(SPATH)) - -$(SX_SCEW)_CACHE_MODE := GIT_CONTENT_SHA -$(SX_SCEW)_DEP_FLAGS := $(MLNX_SDK_COMMON_FLAGS_LIST) -$(SX_SCEW)_DEP_FILES := $(DEP_FILES) - -$(SX_SCEW_DEV)_CACHE_MODE := GIT_CONTENT_SHA -$(SX_SCEW_DEV)_DEP_FLAGS := $(MLNX_SDK_COMMON_FLAGS_LIST) -$(SX_SCEW_DEV)_DEP_FILES := $(DEP_FILES) - -ifeq ($(SDK_FROM_SRC),y) -$(SX_SCEW_DBGSYM)_CACHE_MODE := GIT_CONTENT_SHA -$(SX_SCEW_DBGSYM)_DEP_FLAGS := $(MLNX_SDK_COMMON_FLAGS_LIST) -$(SX_SCEW_DBGSYM)_DEP_FILES := $(DEP_FILES) -endif - # SXD_LIBS SPATH := $($(SXD_LIBS)_SRC_PATH) @@ -212,6 +191,23 @@ $(SX_HASH_CALC_DBGSYM)_DEP_FLAGS := $(MLNX_SDK_COMMON_FLAGS_LIST) $(SX_HASH_CALC_DBGSYM)_DEP_FILES := $(DEP_FILES) endif +# SX_OBJ_DESC_LIB + +SPATH := $($(SX_OBJ_DESC_LIB)_SRC_PATH) +DEP_FILES := $(SONIC_COMMON_FILES_LIST) $(PLATFORM_PATH)/sdk.mk $(PLATFORM_PATH)/sdk.dep +DEP_FILES += $(SONIC_COMMON_BASE_FILES_LIST) +DEP_FILES += $(shell git ls-files -- $(SPATH)) + +$(SX_OBJ_DESC_LIB)_CACHE_MODE := GIT_CONTENT_SHA +$(SX_OBJ_DESC_LIB)_DEP_FLAGS := $(MLNX_SDK_COMMON_FLAGS_LIST) +$(SX_OBJ_DESC_LIB)_DEP_FILES := $(DEP_FILES) + +ifeq ($(SDK_FROM_SRC),y) +$(SX_OBJ_DESC_LIB_DBGSYM)_CACHE_MODE := GIT_CONTENT_SHA +$(SX_OBJ_DESC_LIB_DBGSYM)_DEP_FLAGS := $(MLNX_SDK_COMMON_FLAGS_LIST) +$(SX_OBJ_DESC_LIB_DBGSYM)_DEP_FILES := $(DEP_FILES) +endif + # SX_KERNEL SPATH := $($(SX_KERNEL)_SRC_PATH) diff --git a/platform/mellanox/sdk.mk b/platform/mellanox/sdk.mk index 8a22444e4489..69a28c247778 100644 --- a/platform/mellanox/sdk.mk +++ b/platform/mellanox/sdk.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2016-2022 NVIDIA CORPORATION & AFFILIATES. +# Copyright (c) 2016-2023 NVIDIA CORPORATION & AFFILIATES. # Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -14,7 +14,7 @@ # See the License for the specific language governing permissions and # limitations under the License. # -MLNX_SDK_VERSION = 4.5.5142 +MLNX_SDK_VERSION = 4.6.1020 MLNX_SDK_ISSU_VERSION = 101 MLNX_SDK_DRIVERS_GITHUB_URL = https://github.com/Mellanox/Spectrum-SDK-Drivers @@ -35,18 +35,18 @@ endif export MLNX_SDK_SOURCE_BASE_URL MLNX_SDK_VERSION MLNX_SDK_ISSU_VERSION MLNX_SDK_DEB_VERSION MLNX_ASSETS_GITHUB_URL MLNX_SDK_DRIVERS_GITHUB_URL MLNX_SDK_RDEBS += $(APPLIBS) $(SX_COMPLIB) $(SX_EXAMPLES) \ - $(SX_GEN_UTILS) $(SX_SCEW) $(SXD_LIBS) $(WJH_LIBS) $(SX_ACL_HELPER) \ - $(SX_HASH_CALC) + $(SX_GEN_UTILS) $(SXD_LIBS) $(WJH_LIBS) $(SX_ACL_HELPER) \ + $(SX_HASH_CALC) $(SX_OBJ_DESC_LIB) MLNX_SDK_DEBS += $(APPLIBS_DEV) $(SX_COMPLIB_DEV) \ $(SX_COMPLIB_DEV_STATIC) $(SX_EXAMPLES_DEV) $(SX_GEN_UTILS_DEV) \ - $(SX_SCEW_DEV) $(SX_SCEW_DEV_STATIC) $(SXD_LIBS_DEV)\ - $(SXD_LIBS_DEV_STATIC) $(WJH_LIBS_DEV) $(SX_ACL_HELPER_DEV) $(SX_HASH_CALC) + $(SXD_LIBS_DEV) $(SXD_LIBS_DEV_STATIC) $(WJH_LIBS_DEV) $(SX_ACL_HELPER_DEV) \ + $(SX_HASH_CALC) $(SX_OBJ_DESC_LIB_DEV) MLNX_SDK_DBG_DEBS += $(APPLIBS_DBGSYM) $(SX_COMPLIB_DBGSYM) \ - $(SX_EXAMPLES_DBGSYM) $(SX_GEN_UTILS_DBGSYM) $(SX_SCEW_DBGSYM) \ + $(SX_EXAMPLES_DBGSYM) $(SX_GEN_UTILS_DBGSYM) \ $(SXD_LIBS_DBGSYM) $(WJH_LIBS_DBGSYM) $(SX_ACL_HELPER_DBGSYM) \ - $(SX_HASH_CALC_DBGSYM) + $(SX_HASH_CALC_DBGSYM) $(SX_OBJ_DESC_LIB_DBGSYM) APPLIBS = applibs_1.mlnx.$(MLNX_SDK_DEB_VERSION)_$(CONFIGURED_ARCH).deb $(APPLIBS)_SRC_PATH = $(PLATFORM_PATH)/sdk-src/applibs @@ -70,8 +70,8 @@ endif SX_EXAMPLES = sx-examples_1.mlnx.$(MLNX_SDK_DEB_VERSION)_$(CONFIGURED_ARCH).deb $(SX_EXAMPLES)_SRC_PATH = $(PLATFORM_PATH)/sdk-src/sx-examples -$(SX_EXAMPLES)_DEPENDS += $(APPLIBS_DEV) $(SX_SCEW_DEV) $(SXD_LIBS_DEV) -$(SX_EXAMPLES)_RDEPENDS += $(APPLIBS) $(SX_SCEW) $(SXD_LIBS) +$(SX_EXAMPLES)_DEPENDS += $(APPLIBS_DEV) $(SXD_LIBS_DEV) +$(SX_EXAMPLES)_RDEPENDS += $(APPLIBS) $(SXD_LIBS) SX_EXAMPLES_DEV = sx-examples-dev_1.mlnx.$(MLNX_SDK_DEB_VERSION)_$(CONFIGURED_ARCH).deb $(eval $(call add_derived_package,$(SX_EXAMPLES),$(SX_EXAMPLES_DEV))) SX_EXAMPLES_DBGSYM = sx-examples-dbgsym_1.mlnx.$(MLNX_SDK_DEB_VERSION)_$(CONFIGURED_ARCH).deb @@ -90,15 +90,6 @@ ifeq ($(SDK_FROM_SRC),y) $(eval $(call add_derived_package,$(SX_GEN_UTILS),$(SX_GEN_UTILS_DBGSYM))) endif -SX_SCEW = sx-scew_1.mlnx.$(MLNX_SDK_DEB_VERSION)_$(CONFIGURED_ARCH).deb -$(SX_SCEW)_SRC_PATH = $(PLATFORM_PATH)/sdk-src/sx-scew -SX_SCEW_DEV = sx-scew-dev_1.mlnx.$(MLNX_SDK_DEB_VERSION)_$(CONFIGURED_ARCH).deb -$(eval $(call add_derived_package,$(SX_SCEW),$(SX_SCEW_DEV))) -SX_SCEW_DBGSYM = sx-scew-dbgsym_1.mlnx.$(MLNX_SDK_DEB_VERSION)_$(CONFIGURED_ARCH).deb -ifeq ($(SDK_FROM_SRC),y) -$(eval $(call add_derived_package,$(SX_SCEW),$(SX_SCEW_DBGSYM))) -endif - SXD_LIBS = sxd-libs_1.mlnx.$(MLNX_SDK_DEB_VERSION)_$(CONFIGURED_ARCH).deb $(SXD_LIBS)_SRC_PATH = $(PLATFORM_PATH)/sdk-src/sxd-libs $(SXD_LIBS)_DEPENDS += $(SX_COMPLIB_DEV) $(SX_GEN_UTILS_DEV) @@ -130,9 +121,20 @@ ifeq ($(SDK_FROM_SRC),y) $(eval $(call add_derived_package,$(SX_ACL_HELPER),$(SX_ACL_HELPER_DBGSYM))) endif +SX_OBJ_DESC_LIB = sx-obj-desc-lib_1.mlnx.$(MLNX_SDK_DEB_VERSION)_$(CONFIGURED_ARCH).deb +$(SX_OBJ_DESC_LIB)_SRC_PATH = $(PLATFORM_PATH)/sdk-src/sx-obj-desc-lib +$(SX_OBJ_DESC_LIB)_DEPENDS += $(APPLIBS_DEV) $(SX_COMPLIB_DEV) $(SXD_LIBS_DEV) +$(SX_OBJ_DESC_LIB)_RDEPENDS += $(APPLIBS) $(SX_COMPLIB) $(PYTHON_SDK_API) +SX_OBJ_DESC_LIB_DEV = sx-obj-desc-lib-dev_1.mlnx.$(MLNX_SDK_DEB_VERSION)_$(CONFIGURED_ARCH).deb +$(eval $(call add_derived_package,$(SX_OBJ_DESC_LIB),$(SX_OBJ_DESC_LIB_DEV))) +SX_OBJ_DESC_LIB_DBGSYM = sx-obj-desc-lib-dbgsym_1.mlnx.$(MLNX_SDK_DEB_VERSION)_$(CONFIGURED_ARCH).deb +ifeq ($(SDK_FROM_SRC),y) +$(eval $(call add_derived_package,$(SX_OBJ_DESC_LIB),$(SX_OBJ_DESC_LIB_DBGSYM))) +endif + WJH_LIBS = wjh-libs_1.mlnx.$(MLNX_SDK_DEB_VERSION)_$(CONFIGURED_ARCH).deb $(WJH_LIBS)_SRC_PATH = $(PLATFORM_PATH)/sdk-src/wjh-libs -$(WJH_LIBS)_DEPENDS += $(SX_COMPLIB_DEV) $(SXD_LIBS_DEV) $(APPLIBS_DEV) $(SX_ACL_HELPER_DEV) $(SX_SCEW_DEV) +$(WJH_LIBS)_DEPENDS += $(SX_COMPLIB_DEV) $(SXD_LIBS_DEV) $(APPLIBS_DEV) $(SX_ACL_HELPER_DEV) $(WJH_LIBS)_RDEPENDS += $(SX_COMPLIB) $(PYTHON_SDK_API) $(SX_ACL_HELPER) WJH_LIBS_DEV = wjh-libs-dev_1.mlnx.$(MLNX_SDK_DEB_VERSION)_$(CONFIGURED_ARCH).deb $(eval $(call add_derived_package,$(WJH_LIBS),$(WJH_LIBS_DEV))) diff --git a/platform/pddf/i2c/modules/fan/driver/pddf_fan_api.c b/platform/pddf/i2c/modules/fan/driver/pddf_fan_api.c index 66bd2169c1ee..4b95060e3c80 100644 --- a/platform/pddf/i2c/modules/fan/driver/pddf_fan_api.c +++ b/platform/pddf/i2c/modules/fan/driver/pddf_fan_api.c @@ -106,6 +106,18 @@ void get_fan_extra_default_sysfs(int idx, char *str) break; case FAN12_PRESENT: strcpy(str, "fan12_status"); + break; + case FAN13_PRESENT: + strcpy(str, "fan13_status"); + break; + case FAN14_PRESENT: + strcpy(str, "fan14_status"); + break; + case FAN15_PRESENT: + strcpy(str, "fan15_status"); + break; + case FAN16_PRESENT: + strcpy(str, "fan16_status"); break; default: break; @@ -242,6 +254,10 @@ ssize_t fan_show_default(struct device *dev, struct device_attribute *da, char * case FAN10_PRESENT: case FAN11_PRESENT: case FAN12_PRESENT: + case FAN13_PRESENT: + case FAN14_PRESENT: + case FAN15_PRESENT: + case FAN16_PRESENT: case FAN1_DIRECTION: case FAN2_DIRECTION: case FAN3_DIRECTION: @@ -254,6 +270,10 @@ ssize_t fan_show_default(struct device *dev, struct device_attribute *da, char * case FAN10_DIRECTION: case FAN11_DIRECTION: case FAN12_DIRECTION: + case FAN13_DIRECTION: + case FAN14_DIRECTION: + case FAN15_DIRECTION: + case FAN16_DIRECTION: case FAN1_INPUT: case FAN2_INPUT: case FAN3_INPUT: @@ -266,6 +286,10 @@ ssize_t fan_show_default(struct device *dev, struct device_attribute *da, char * case FAN10_INPUT: case FAN11_INPUT: case FAN12_INPUT: + case FAN13_INPUT: + case FAN14_INPUT: + case FAN15_INPUT: + case FAN16_INPUT: case FAN1_PWM: case FAN2_PWM: case FAN3_PWM: @@ -278,6 +302,10 @@ ssize_t fan_show_default(struct device *dev, struct device_attribute *da, char * case FAN10_PWM: case FAN11_PWM: case FAN12_PWM: + case FAN13_PWM: + case FAN14_PWM: + case FAN15_PWM: + case FAN16_PWM: case FAN1_FAULT: case FAN2_FAULT: case FAN3_FAULT: @@ -290,6 +318,10 @@ ssize_t fan_show_default(struct device *dev, struct device_attribute *da, char * case FAN10_FAULT: case FAN11_FAULT: case FAN12_FAULT: + case FAN13_FAULT: + case FAN14_FAULT: + case FAN15_FAULT: + case FAN16_FAULT: case FAN_DUTY_CYCLE: status = attr_info->val.intval; break; @@ -359,6 +391,10 @@ ssize_t fan_store_default(struct device *dev, struct device_attribute *da, const case FAN10_PWM: case FAN11_PWM: case FAN12_PWM: + case FAN13_PWM: + case FAN14_PWM: + case FAN15_PWM: + case FAN16_PWM: ret = kstrtoint(buf, 10, &val); if (ret) { diff --git a/platform/pddf/i2c/modules/fan/driver/pddf_fan_driver.c b/platform/pddf/i2c/modules/fan/driver/pddf_fan_driver.c index 6c72b4adc4a3..cf83724d1f97 100644 --- a/platform/pddf/i2c/modules/fan/driver/pddf_fan_driver.c +++ b/platform/pddf/i2c/modules/fan/driver/pddf_fan_driver.c @@ -77,6 +77,14 @@ FAN_SYSFS_ATTR_DATA data_fan11_present = {FAN11_PRESENT, S_IRUGO, fan_show_defau EXPORT_SYMBOL(data_fan11_present); FAN_SYSFS_ATTR_DATA data_fan12_present = {FAN12_PRESENT, S_IRUGO, fan_show_default, NULL, sonic_i2c_get_fan_present_default, NULL, NULL, NULL, NULL, NULL, NULL}; EXPORT_SYMBOL(data_fan12_present); +FAN_SYSFS_ATTR_DATA data_fan13_present = {FAN13_PRESENT, S_IRUGO, fan_show_default, NULL, sonic_i2c_get_fan_present_default, NULL, NULL, NULL, NULL, NULL, NULL}; +EXPORT_SYMBOL(data_fan13_present); +FAN_SYSFS_ATTR_DATA data_fan14_present = {FAN14_PRESENT, S_IRUGO, fan_show_default, NULL, sonic_i2c_get_fan_present_default, NULL, NULL, NULL, NULL, NULL, NULL}; +EXPORT_SYMBOL(data_fan14_present); +FAN_SYSFS_ATTR_DATA data_fan15_present = {FAN15_PRESENT, S_IRUGO, fan_show_default, NULL, sonic_i2c_get_fan_present_default, NULL, NULL, NULL, NULL, NULL, NULL}; +EXPORT_SYMBOL(data_fan15_present); +FAN_SYSFS_ATTR_DATA data_fan16_present = {FAN16_PRESENT, S_IRUGO, fan_show_default, NULL, sonic_i2c_get_fan_present_default, NULL, NULL, NULL, NULL, NULL, NULL}; +EXPORT_SYMBOL(data_fan16_present); FAN_SYSFS_ATTR_DATA data_fan1_direction = {FAN1_DIRECTION, S_IRUGO, fan_show_default, NULL, sonic_i2c_get_fan_direction_default, NULL, NULL, NULL, NULL, NULL, NULL}; @@ -103,6 +111,14 @@ FAN_SYSFS_ATTR_DATA data_fan11_direction = {FAN11_DIRECTION, S_IRUGO, fan_show_d EXPORT_SYMBOL(data_fan11_direction); FAN_SYSFS_ATTR_DATA data_fan12_direction = {FAN12_DIRECTION, S_IRUGO, fan_show_default, NULL, sonic_i2c_get_fan_direction_default, NULL, NULL, NULL, NULL, NULL, NULL}; EXPORT_SYMBOL(data_fan12_direction); +FAN_SYSFS_ATTR_DATA data_fan13_direction = {FAN13_DIRECTION, S_IRUGO, fan_show_default, NULL, sonic_i2c_get_fan_direction_default, NULL, NULL, NULL, NULL, NULL, NULL}; +EXPORT_SYMBOL(data_fan13_direction); +FAN_SYSFS_ATTR_DATA data_fan14_direction = {FAN14_DIRECTION, S_IRUGO, fan_show_default, NULL, sonic_i2c_get_fan_direction_default, NULL, NULL, NULL, NULL, NULL, NULL}; +EXPORT_SYMBOL(data_fan14_direction); +FAN_SYSFS_ATTR_DATA data_fan15_direction = {FAN15_DIRECTION, S_IRUGO, fan_show_default, NULL, sonic_i2c_get_fan_direction_default, NULL, NULL, NULL, NULL, NULL, NULL}; +EXPORT_SYMBOL(data_fan15_direction); +FAN_SYSFS_ATTR_DATA data_fan16_direction = {FAN16_DIRECTION, S_IRUGO, fan_show_default, NULL, sonic_i2c_get_fan_direction_default, NULL, NULL, NULL, NULL, NULL, NULL}; +EXPORT_SYMBOL(data_fan16_direction); FAN_SYSFS_ATTR_DATA data_fan1_input = {FAN1_INPUT, S_IRUGO, fan_show_default, NULL, sonic_i2c_get_fan_rpm_default, NULL, NULL, NULL, NULL, NULL, NULL}; @@ -129,6 +145,14 @@ FAN_SYSFS_ATTR_DATA data_fan11_input = {FAN11_INPUT, S_IRUGO, fan_show_default, EXPORT_SYMBOL(data_fan11_input); FAN_SYSFS_ATTR_DATA data_fan12_input = {FAN12_INPUT, S_IRUGO, fan_show_default, NULL, sonic_i2c_get_fan_rpm_default, NULL, NULL, NULL, NULL, NULL, NULL}; EXPORT_SYMBOL(data_fan12_input); +FAN_SYSFS_ATTR_DATA data_fan13_input = {FAN13_INPUT, S_IRUGO, fan_show_default, NULL, sonic_i2c_get_fan_rpm_default, NULL, NULL, NULL, NULL, NULL, NULL}; +EXPORT_SYMBOL(data_fan13_input); +FAN_SYSFS_ATTR_DATA data_fan14_input = {FAN14_INPUT, S_IRUGO, fan_show_default, NULL, sonic_i2c_get_fan_rpm_default, NULL, NULL, NULL, NULL, NULL, NULL}; +EXPORT_SYMBOL(data_fan14_input); +FAN_SYSFS_ATTR_DATA data_fan15_input = {FAN15_INPUT, S_IRUGO, fan_show_default, NULL, sonic_i2c_get_fan_rpm_default, NULL, NULL, NULL, NULL, NULL, NULL}; +EXPORT_SYMBOL(data_fan15_input); +FAN_SYSFS_ATTR_DATA data_fan16_input = {FAN16_INPUT, S_IRUGO, fan_show_default, NULL, sonic_i2c_get_fan_rpm_default, NULL, NULL, NULL, NULL, NULL, NULL}; +EXPORT_SYMBOL(data_fan16_input); FAN_SYSFS_ATTR_DATA data_fan1_pwm = {FAN1_PWM, S_IRUGO | S_IWUSR, fan_show_default, NULL, sonic_i2c_get_fan_pwm_default, NULL, fan_store_default, NULL, sonic_i2c_set_fan_pwm_default, NULL, NULL}; @@ -155,6 +179,14 @@ FAN_SYSFS_ATTR_DATA data_fan11_pwm = {FAN11_PWM, S_IRUGO | S_IWUSR, fan_show_def EXPORT_SYMBOL(data_fan11_pwm); FAN_SYSFS_ATTR_DATA data_fan12_pwm = {FAN12_PWM, S_IRUGO | S_IWUSR, fan_show_default, NULL, sonic_i2c_get_fan_pwm_default, NULL, fan_store_default, NULL, sonic_i2c_set_fan_pwm_default, NULL, NULL}; EXPORT_SYMBOL(data_fan12_pwm); +FAN_SYSFS_ATTR_DATA data_fan13_pwm = {FAN13_PWM, S_IRUGO | S_IWUSR, fan_show_default, NULL, sonic_i2c_get_fan_pwm_default, NULL, fan_store_default, NULL, sonic_i2c_set_fan_pwm_default, NULL, NULL}; +EXPORT_SYMBOL(data_fan13_pwm); +FAN_SYSFS_ATTR_DATA data_fan14_pwm = {FAN14_PWM, S_IRUGO | S_IWUSR, fan_show_default, NULL, sonic_i2c_get_fan_pwm_default, NULL, fan_store_default, NULL, sonic_i2c_set_fan_pwm_default, NULL, NULL}; +EXPORT_SYMBOL(data_fan14_pwm); +FAN_SYSFS_ATTR_DATA data_fan15_pwm = {FAN15_PWM, S_IRUGO | S_IWUSR, fan_show_default, NULL, sonic_i2c_get_fan_pwm_default, NULL, fan_store_default, NULL, sonic_i2c_set_fan_pwm_default, NULL, NULL}; +EXPORT_SYMBOL(data_fan15_pwm); +FAN_SYSFS_ATTR_DATA data_fan16_pwm = {FAN16_PWM, S_IRUGO | S_IWUSR, fan_show_default, NULL, sonic_i2c_get_fan_pwm_default, NULL, fan_store_default, NULL, sonic_i2c_set_fan_pwm_default, NULL, NULL}; +EXPORT_SYMBOL(data_fan16_pwm); FAN_SYSFS_ATTR_DATA data_fan1_fault = {FAN1_FAULT, S_IRUGO, fan_show_default, NULL, sonic_i2c_get_fan_fault_default, NULL, NULL, NULL, NULL, NULL, NULL}; @@ -181,6 +213,14 @@ FAN_SYSFS_ATTR_DATA data_fan11_fault = {FAN11_FAULT, S_IRUGO, fan_show_default, EXPORT_SYMBOL(data_fan11_fault); FAN_SYSFS_ATTR_DATA data_fan12_fault = {FAN12_FAULT, S_IRUGO, fan_show_default, NULL, sonic_i2c_get_fan_fault_default, NULL, NULL, NULL, NULL, NULL, NULL}; EXPORT_SYMBOL(data_fan12_fault); +FAN_SYSFS_ATTR_DATA data_fan13_fault = {FAN13_FAULT, S_IRUGO, fan_show_default, NULL, sonic_i2c_get_fan_fault_default, NULL, NULL, NULL, NULL, NULL, NULL}; +EXPORT_SYMBOL(data_fan13_fault); +FAN_SYSFS_ATTR_DATA data_fan14_fault = {FAN14_FAULT, S_IRUGO, fan_show_default, NULL, sonic_i2c_get_fan_fault_default, NULL, NULL, NULL, NULL, NULL, NULL}; +EXPORT_SYMBOL(data_fan14_fault); +FAN_SYSFS_ATTR_DATA data_fan15_fault = {FAN15_FAULT, S_IRUGO, fan_show_default, NULL, sonic_i2c_get_fan_fault_default, NULL, NULL, NULL, NULL, NULL, NULL}; +EXPORT_SYMBOL(data_fan15_fault); +FAN_SYSFS_ATTR_DATA data_fan16_fault = {FAN16_FAULT, S_IRUGO, fan_show_default, NULL, sonic_i2c_get_fan_fault_default, NULL, NULL, NULL, NULL, NULL, NULL}; +EXPORT_SYMBOL(data_fan16_fault); /* Derived attributes like status (should be derived from 'presence' and 'speed'/'fault' attributes) etc */ FAN_SYSFS_ATTR_DATA data_fan1_status = {FAN1_STATUS, S_IRUGO, fan_show_status, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL}; @@ -207,6 +247,14 @@ FAN_SYSFS_ATTR_DATA data_fan11_status = {FAN11_STATUS, S_IRUGO, fan_show_status, EXPORT_SYMBOL(data_fan11_status); FAN_SYSFS_ATTR_DATA data_fan12_status = {FAN12_STATUS, S_IRUGO, fan_show_status, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL}; EXPORT_SYMBOL(data_fan12_status); +FAN_SYSFS_ATTR_DATA data_fan13_status = {FAN13_STATUS, S_IRUGO, fan_show_status, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL}; +EXPORT_SYMBOL(data_fan13_status); +FAN_SYSFS_ATTR_DATA data_fan14_status = {FAN14_STATUS, S_IRUGO, fan_show_status, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL}; +EXPORT_SYMBOL(data_fan14_status); +FAN_SYSFS_ATTR_DATA data_fan15_status = {FAN15_STATUS, S_IRUGO, fan_show_status, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL}; +EXPORT_SYMBOL(data_fan15_status); +FAN_SYSFS_ATTR_DATA data_fan16_status = {FAN16_STATUS, S_IRUGO, fan_show_status, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL}; +EXPORT_SYMBOL(data_fan16_status); /* Some generic fan attributes */ FAN_SYSFS_ATTR_DATA data_fan_duty_cycle = {FAN_DUTY_CYCLE, S_IRUGO | S_IWUSR, fan_show_default, NULL, sonic_i2c_get_fan_dc_default, NULL, fan_store_default, NULL, sonic_i2c_set_fan_dc_default, NULL, NULL}; @@ -238,6 +286,10 @@ FAN_SYSFS_ATTR_DATA_ENTRY fan_sysfs_attr_data_tbl[]= { "fan10_present", &data_fan10_present}, { "fan11_present", &data_fan11_present}, { "fan12_present", &data_fan12_present}, + { "fan13_present", &data_fan13_present}, + { "fan14_present", &data_fan14_present}, + { "fan15_present", &data_fan15_present}, + { "fan16_present", &data_fan16_present}, { "fan1_direction", &data_fan1_direction}, { "fan2_direction", &data_fan2_direction}, { "fan3_direction", &data_fan3_direction}, @@ -250,6 +302,10 @@ FAN_SYSFS_ATTR_DATA_ENTRY fan_sysfs_attr_data_tbl[]= { "fan10_direction", &data_fan10_direction}, { "fan11_direction", &data_fan11_direction}, { "fan12_direction", &data_fan12_direction}, + { "fan13_direction", &data_fan13_direction}, + { "fan14_direction", &data_fan14_direction}, + { "fan15_direction", &data_fan15_direction}, + { "fan16_direction", &data_fan16_direction}, { "fan1_input", &data_fan1_input}, { "fan2_input", &data_fan2_input}, { "fan3_input", &data_fan3_input}, @@ -262,6 +318,10 @@ FAN_SYSFS_ATTR_DATA_ENTRY fan_sysfs_attr_data_tbl[]= { "fan10_input", &data_fan10_input}, { "fan11_input", &data_fan11_input}, { "fan12_input", &data_fan12_input}, + { "fan13_input", &data_fan13_input}, + { "fan14_input", &data_fan14_input}, + { "fan15_input", &data_fan15_input}, + { "fan16_input", &data_fan16_input}, { "fan1_pwm", &data_fan1_pwm}, { "fan2_pwm", &data_fan2_pwm}, { "fan3_pwm", &data_fan3_pwm}, @@ -274,6 +334,10 @@ FAN_SYSFS_ATTR_DATA_ENTRY fan_sysfs_attr_data_tbl[]= { "fan10_pwm", &data_fan10_pwm}, { "fan11_pwm", &data_fan11_pwm}, { "fan12_pwm", &data_fan12_pwm}, + { "fan13_pwm", &data_fan13_pwm}, + { "fan14_pwm", &data_fan14_pwm}, + { "fan15_pwm", &data_fan15_pwm}, + { "fan16_pwm", &data_fan16_pwm}, { "fan1_fault", &data_fan1_fault}, { "fan2_fault", &data_fan2_fault}, { "fan3_fault", &data_fan3_fault}, @@ -286,6 +350,10 @@ FAN_SYSFS_ATTR_DATA_ENTRY fan_sysfs_attr_data_tbl[]= { "fan10_fault", &data_fan10_fault}, { "fan11_fault", &data_fan11_fault}, { "fan12_fault", &data_fan12_fault}, + { "fan13_fault", &data_fan13_fault}, + { "fan14_fault", &data_fan14_fault}, + { "fan15_fault", &data_fan15_fault}, + { "fan16_fault", &data_fan16_fault}, { "fan1_status", &data_fan1_status}, { "fan2_status", &data_fan2_status}, { "fan3_status", &data_fan3_status}, @@ -298,6 +366,10 @@ FAN_SYSFS_ATTR_DATA_ENTRY fan_sysfs_attr_data_tbl[]= { "fan10_status", &data_fan10_status}, { "fan11_status", &data_fan11_status}, { "fan12_status", &data_fan12_status}, + { "fan13_status", &data_fan13_status}, + { "fan14_status", &data_fan14_status}, + { "fan15_status", &data_fan15_status}, + { "fan16_status", &data_fan16_status}, { "fan_duty_cycle", &data_fan_duty_cycle}, { "fan_model_name", &data_fan_model_name}, { "fan_serial_num", &data_fan_serial_num}, diff --git a/platform/pddf/i2c/modules/gpio/pddf_gpio_module.c b/platform/pddf/i2c/modules/gpio/pddf_gpio_module.c index 30eec5f185f4..3921fcdfb86a 100644 --- a/platform/pddf/i2c/modules/gpio/pddf_gpio_module.c +++ b/platform/pddf/i2c/modules/gpio/pddf_gpio_module.c @@ -16,6 +16,7 @@ * PDDF generic kernle module to create the I2C client for pca955x type of GPIO module */ +#define __STDC_WANT_LIB_EXT1__ 1 #include #include #include @@ -67,13 +68,19 @@ struct i2c_board_info *i2c_get_gpio_board_info(GPIO_DATA* mdata, NEW_DEV_ATTR *d if (strncmp(device_data->dev_type, "pca9554", strlen("pca9554")) == 0 || strncmp(device_data->dev_type, "pca9534", strlen("pca9534")) == 0 || - strncmp(device_data->dev_type, "pca9538", strlen("pca9538")) == 0) + strncmp(device_data->dev_type, "pca9538", strlen("pca9538")) == 0 || + strncmp(device_data->dev_type, "tca6408", strlen("tca6408")) == 0 || + strncmp(device_data->dev_type, "tca9554", strlen("tca9554")) == 0) def_num_gpios = 0x8; else if (strncmp(device_data->dev_type, "pca9555", strlen("pca9555")) == 0 || strncmp(device_data->dev_type, "pca9535", strlen("pca9535")) == 0 || strncmp(device_data->dev_type, "pca9539", strlen("pca9539")) == 0 || - strncmp(device_data->dev_type, "pca9575", strlen("pca9575")) == 0) + strncmp(device_data->dev_type, "pca9575", strlen("pca9575")) == 0 || + strncmp(device_data->dev_type, "tca6416", strlen("tca6416")) == 0 || + strncmp(device_data->dev_type, "tca9539", strlen("tca9539")) == 0) def_num_gpios = 0x10; + else if (strncmp(device_data->dev_type, "tca6424", strlen("tca6424")) == 0) + def_num_gpios = 0x18; else if (strncmp(device_data->dev_type, "pca9698", strlen("pca9698")) == 0 || strncmp(device_data->dev_type, "pca9505", strlen("pca9505")) == 0) def_num_gpios = 0x28; @@ -82,7 +89,7 @@ struct i2c_board_info *i2c_get_gpio_board_info(GPIO_DATA* mdata, NEW_DEV_ATTR *d printk(KERN_ERR "%s: Unknown type of gpio device\n", __FUNCTION__); return NULL; } - + if(mdata->gpio_base == 0) { base = base_gpio_num; base_gpio_num += def_num_gpios; @@ -127,7 +134,7 @@ static ssize_t do_device_operation(struct device *dev, struct device_attribute * pddf_dbg(GPIO, KERN_ERR "Created %s client: 0x%p\n", device_ptr->i2c_name, (void *)client_ptr); add_device_table(device_ptr->i2c_name, (void*)client_ptr); } - else + else { kfree(board_info); goto free_data; @@ -158,9 +165,18 @@ static ssize_t do_device_operation(struct device *dev, struct device_attribute * } free_data: + +#ifdef __STDC_LIB_EXT1__ + memset_s(gpio_ptr, sizeof(GPIO_DATA), 0, sizeof(GPIO_DATA)); +#else memset(gpio_ptr, 0, sizeof(GPIO_DATA)); +#endif /*TODO: free the device_ptr->data is dynamically allocated*/ +#ifdef __STDC_LIB_EXT1__ + memset_s(device_ptr, sizeof(NEW_DEV_ATTR), 0 , sizeof(NEW_DEV_ATTR)); +#else memset(device_ptr, 0 , sizeof(NEW_DEV_ATTR)); +#endif return count; } @@ -177,14 +193,14 @@ int __init gpio_data_init(void) pddf_dbg(GPIO, "GPIO_DATA MODULE.. init\n"); device_kobj = get_device_i2c_kobj(); - if(!device_kobj) + if(!device_kobj) return -ENOMEM; gpio_kobj = kobject_create_and_add("gpio", device_kobj); - if(!gpio_kobj) + if(!gpio_kobj) return -ENOMEM; - - + + ret = sysfs_create_group(gpio_kobj, &pddf_clients_data_group); if (ret) { diff --git a/platform/pddf/i2c/modules/include/pddf_fan_driver.h b/platform/pddf/i2c/modules/include/pddf_fan_driver.h index ca5b73da276c..07e1339a8555 100644 --- a/platform/pddf/i2c/modules/include/pddf_fan_driver.h +++ b/platform/pddf/i2c/modules/include/pddf_fan_driver.h @@ -32,6 +32,10 @@ enum fan_sysfs_attributes { FAN10_PRESENT, FAN11_PRESENT, FAN12_PRESENT, + FAN13_PRESENT, + FAN14_PRESENT, + FAN15_PRESENT, + FAN16_PRESENT, FAN1_DIRECTION, FAN2_DIRECTION, FAN3_DIRECTION, @@ -44,6 +48,10 @@ enum fan_sysfs_attributes { FAN10_DIRECTION, FAN11_DIRECTION, FAN12_DIRECTION, + FAN13_DIRECTION, + FAN14_DIRECTION, + FAN15_DIRECTION, + FAN16_DIRECTION, FAN1_INPUT, FAN2_INPUT, FAN3_INPUT, @@ -56,6 +64,10 @@ enum fan_sysfs_attributes { FAN10_INPUT, FAN11_INPUT, FAN12_INPUT, + FAN13_INPUT, + FAN14_INPUT, + FAN15_INPUT, + FAN16_INPUT, FAN1_PWM, FAN2_PWM, FAN3_PWM, @@ -68,6 +80,10 @@ enum fan_sysfs_attributes { FAN10_PWM, FAN11_PWM, FAN12_PWM, + FAN13_PWM, + FAN14_PWM, + FAN15_PWM, + FAN16_PWM, FAN1_FAULT, FAN2_FAULT, FAN3_FAULT, @@ -80,6 +96,10 @@ enum fan_sysfs_attributes { FAN10_FAULT, FAN11_FAULT, FAN12_FAULT, + FAN13_FAULT, + FAN14_FAULT, + FAN15_FAULT, + FAN16_FAULT, FAN1_STATUS, FAN2_STATUS, FAN3_STATUS, @@ -92,6 +112,10 @@ enum fan_sysfs_attributes { FAN10_STATUS, FAN11_STATUS, FAN12_STATUS, + FAN13_STATUS, + FAN14_STATUS, + FAN15_STATUS, + FAN16_STATUS, FAN_DUTY_CYCLE, FAN_MODEL_NAME, FAN_SERIAL_NUM, diff --git a/platform/vs/syncd-vs.mk b/platform/vs/syncd-vs.mk index 22b34fbcaae3..6ff00a3508b9 100644 --- a/platform/vs/syncd-vs.mk +++ b/platform/vs/syncd-vs.mk @@ -1,10 +1,10 @@ -$(LIBSAIREDIS)_DPKG_TARGET = binary-syncd-vs +$(LIBSAIREDIS)_DEB_BUILD_PROFILES += syncd vs SYNCD_VS = syncd-vs_1.0.0_amd64.deb $(SYNCD_VS)_RDEPENDS += $(LIBSAIREDIS) $(LIBSAIMETADATA) $(LIBSAIVS) $(eval $(call add_derived_package,$(LIBSAIREDIS),$(SYNCD_VS))) -SYNCD_VS_DBG = syncd-vs-dbg_1.0.0_amd64.deb -$(SYNCD_VS_DBG)_DEPENDS += $(SYNCD_VS) -$(SYNCD_VS_DBG)_RDEPENDS += $(SYNCD_VS) -$(eval $(call add_derived_package,$(LIBSAIREDIS),$(SYNCD_VS_DBG))) +SYNCD_VS_DBGSYM = syncd-vs-dbgsym_1.0.0_amd64.deb +$(SYNCD_VS_DBGSYM)_DEPENDS += $(SYNCD_VS) +$(SYNCD_VS_DBGSYM)_RDEPENDS += $(SYNCD_VS) +$(eval $(call add_derived_package,$(LIBSAIREDIS),$(SYNCD_VS_DBGSYM))) diff --git a/rules/config b/rules/config index 6a3de7546c0e..7607e42e2401 100644 --- a/rules/config +++ b/rules/config @@ -202,12 +202,23 @@ INCLUDE_KUBERNETES_MASTER ?= n # MASTER_PAUSE_VERSION - version of pause container image # MASTER_COREDNS_VERSION - version of coredns container image # MASTER_ETCD_VERSION = version of etcd container image +# MASTER_CRI_DOCKERD = version of cri-dockerd container image +# MASTER_UI_METRIC_VERSION = version of k8s metrics server container image +# MASTER_UI_DASH_VERSION = version of k8s dashboard container image +# MASTER_MDM_VERSION = version of mdm container image +# MASTER_MDS_VERSION = version of mds container image +# MASTER_FLUENTD_VERSION = version of fluentd container image MASTER_KUBERNETES_VERSION = 1.22.2-00 MASTER_KUBERNETES_CONTAINER_IMAGE_VERSION = v1.22.2 MASTER_PAUSE_VERSION = 3.5 MASTER_COREDNS_VERSION = v1.8.4 MASTER_ETCD_VERSION = 3.5.0-0 -MASTER_CRI_DOCKERD = 0.2.5 +MASTER_CRI_DOCKERD = 0.3.1 +MASTER_UI_METRIC_VERSION = v1.0.8 +MASTER_UI_DASH_VERSION = v2.7.0 +MASTER_MDM_VERSION = 2.2023.505.1124-45da18-20230505t1700 +MASTER_MDS_VERSION = mariner_20230517.1 +MASTER_FLUENTD_VERSION = mariner_20230517.1 # SONIC_ENABLE_IMAGE_SIGNATURE - enable image signature # To not use the auto-generated self-signed certificate, the required files to sign the image as below: diff --git a/rules/docker-database.mk b/rules/docker-database.mk index a10609933c35..48f3b88a0294 100644 --- a/rules/docker-database.mk +++ b/rules/docker-database.mk @@ -25,7 +25,7 @@ SONIC_DOCKER_DBG_IMAGES += $(DOCKER_DATABASE_DBG) SONIC_INSTALL_DOCKER_DBG_IMAGES += $(DOCKER_DATABASE_DBG) $(DOCKER_DATABASE)_CONTAINER_NAME = database -$(DOCKER_DATABASE)_RUN_OPT += --privileged -t +$(DOCKER_DATABASE)_RUN_OPT += -t $(DOCKER_DATABASE)_RUN_OPT += -v /etc/sonic:/etc/sonic:ro $(DOCKER_DATABASE)_RUN_OPT += -v /etc/timezone:/etc/timezone:ro diff --git a/rules/docker-lldp.mk b/rules/docker-lldp.mk index 95172d6cf368..ddd079c4d3e2 100644 --- a/rules/docker-lldp.mk +++ b/rules/docker-lldp.mk @@ -28,7 +28,7 @@ SONIC_DOCKER_DBG_IMAGES += $(DOCKER_LLDP_DBG) SONIC_INSTALL_DOCKER_DBG_IMAGES += $(DOCKER_LLDP_DBG) $(DOCKER_LLDP)_CONTAINER_NAME = lldp -$(DOCKER_LLDP)_RUN_OPT += --privileged -t +$(DOCKER_LLDP)_RUN_OPT += -t --cap-add=NET_ADMIN $(DOCKER_LLDP)_RUN_OPT += -v /etc/sonic:/etc/sonic:ro $(DOCKER_LLDP)_RUN_OPT += -v /etc/timezone:/etc/timezone:ro diff --git a/rules/docker-snmp.mk b/rules/docker-snmp.mk index d350540dbe2f..00c20ab6cf72 100644 --- a/rules/docker-snmp.mk +++ b/rules/docker-snmp.mk @@ -28,7 +28,7 @@ SONIC_DOCKER_DBG_IMAGES += $(DOCKER_SNMP_DBG) SONIC_INSTALL_DOCKER_DBG_IMAGES += $(DOCKER_SNMP_DBG) $(DOCKER_SNMP)_CONTAINER_NAME = snmp -$(DOCKER_SNMP)_RUN_OPT += --privileged -t +$(DOCKER_SNMP)_RUN_OPT += -t $(DOCKER_SNMP)_RUN_OPT += -v /etc/sonic:/etc/sonic:ro $(DOCKER_SNMP)_RUN_OPT += -v /etc/timezone:/etc/timezone:ro $(DOCKER_SNMP)_FILES += $(SUPERVISOR_PROC_EXIT_LISTENER_SCRIPT) diff --git a/rules/docker-teamd.mk b/rules/docker-teamd.mk index ae5cc838450d..275fe1c06310 100644 --- a/rules/docker-teamd.mk +++ b/rules/docker-teamd.mk @@ -33,7 +33,7 @@ SONIC_INSTALL_DOCKER_DBG_IMAGES += $(DOCKER_TEAMD_DBG) endif $(DOCKER_TEAMD)_CONTAINER_NAME = teamd -$(DOCKER_TEAMD)_RUN_OPT += --privileged -t +$(DOCKER_TEAMD)_RUN_OPT += -t --cap-add=NET_ADMIN $(DOCKER_TEAMD)_RUN_OPT += -v /etc/sonic:/etc/sonic:ro $(DOCKER_TEAMD)_RUN_OPT += -v /etc/timezone:/etc/timezone:ro $(DOCKER_TEAMD)_RUN_OPT += -v /host/warmboot:/var/warmboot diff --git a/rules/frr.mk b/rules/frr.mk index 7bc5cc8024f0..b062016fbc09 100644 --- a/rules/frr.mk +++ b/rules/frr.mk @@ -1,9 +1,9 @@ # FRRouting (frr) package -FRR_VERSION = 8.2.2 +FRR_VERSION = 8.5.1 FRR_SUBVERSION = 0 -FRR_BRANCH = frr/8.2 -FRR_TAG = frr-8.2.2 +FRR_BRANCH = frr/8.5 +FRR_TAG = frr-8.5.1 export FRR_VERSION FRR_SUBVERSION FRR_BRANCH FRR_TAG diff --git a/rules/protobuf.mk b/rules/protobuf.mk index 8822d1357498..5e50eac86292 100644 --- a/rules/protobuf.mk +++ b/rules/protobuf.mk @@ -17,17 +17,13 @@ $(eval $(call add_derived_package,$(PROTOBUF),$(PROTOBUF_DEV))) PROTOBUF_LITE = libprotobuf-lite32_$(PROTOBUF_VERSION_FULL)_$(CONFIGURED_ARCH).deb $(eval $(call add_derived_package,$(PROTOBUF),$(PROTOBUF_LITE))) -PROTOC = libprotoc_$(PROTOBUF_VERSION_FULL)_$(CONFIGURED_ARCH).deb -$(PROTOC)_RDEPENDS = $(PROTOBUF) $(PROTOBUF_LITE) -$(eval $(call add_derived_package,$(PROTOBUF),$(PROTOC))) - PROTOC32 = libprotoc32_$(PROTOBUF_VERSION_FULL)_$(CONFIGURED_ARCH).deb $(PROTOC32)_RDEPENDS = $(PROTOBUF) $(PROTOBUF_LITE) $(eval $(call add_derived_package,$(PROTOBUF),$(PROTOC32))) PROTOBUF_COMPILER = protobuf-compiler_$(PROTOBUF_VERSION_FULL)_$(CONFIGURED_ARCH).deb $(PROTOBUF_COMPILER)_DEPENDS = $(PROTOC32) -$(PROTOBUF_COMPILER)_RDEPENDS = $(PROTOC) +$(PROTOBUF_COMPILER)_RDEPENDS = $(PROTOC32) $(eval $(call add_derived_package,$(PROTOBUF),$(PROTOBUF_COMPILER))) PYTHON3_PROTOBUF = python3-protobuf_$(PROTOBUF_VERSION_FULL)_$(CONFIGURED_ARCH).deb diff --git a/rules/sairedis.mk b/rules/sairedis.mk index baa32493b330..163e9b797645 100644 --- a/rules/sairedis.mk +++ b/rules/sairedis.mk @@ -4,7 +4,6 @@ LIBSAIREDIS_VERSION = 1.0.0 LIBSAIREDIS_NAME = libsairedis LIBSAIREDIS = $(LIBSAIREDIS_NAME)_$(LIBSAIREDIS_VERSION)_$(CONFIGURED_ARCH).deb -$(LIBSAIREDIS)_DPKG_TARGET = binary-sairedis $(LIBSAIREDIS)_SRC_PATH = $(SRC_PATH)/sonic-sairedis $(LIBSAIREDIS)_VERSION = $(LIBSAIREDIS_VERSION) $(LIBSAIREDIS)_NAME = $(LIBSAIREDIS_NAME) @@ -30,23 +29,23 @@ LIBSAIMETADATA_DEV = libsaimetadata-dev_$(LIBSAIREDIS_VERSION)_$(CONFIGURED_ARCH $(LIBSAIMETADATA_DEV)_DEPENDS += $(LIBSAIMETADATA) $(eval $(call add_derived_package,$(LIBSAIREDIS),$(LIBSAIMETADATA_DEV))) -LIBSAIREDIS_DBG = $(LIBSAIREDIS_NAME)-dbg_$(LIBSAIREDIS_VERSION)_$(CONFIGURED_ARCH).deb -$(LIBSAIREDIS_DBG)_DEPENDS += $(LIBSAIREDIS) -$(LIBSAIREDIS_DBG)_RDEPENDS += $(LIBSAIREDIS) -$(eval $(call add_derived_package,$(LIBSAIREDIS),$(LIBSAIREDIS_DBG))) +LIBSAIREDIS_DBGSYM = $(LIBSAIREDIS_NAME)-dbgsym_$(LIBSAIREDIS_VERSION)_$(CONFIGURED_ARCH).deb +$(LIBSAIREDIS_DBGSYM)_DEPENDS += $(LIBSAIREDIS) +$(LIBSAIREDIS_DBGSYM)_RDEPENDS += $(LIBSAIREDIS) +$(eval $(call add_derived_package,$(LIBSAIREDIS),$(LIBSAIREDIS_DBGSYM))) -LIBSAIVS_DBG = libsaivs-dbg_$(LIBSAIREDIS_VERSION)_$(CONFIGURED_ARCH).deb -$(LIBSAIVS_DBG)_DEPENDS += $(LIBSAIVS) -$(LIBSAIVS_DBG)_RDEPENDS += $(LIBSAIVS) -$(eval $(call add_derived_package,$(LIBSAIREDIS),$(LIBSAIVS_DBG))) +LIBSAIVS_DBGSYM = libsaivs-dbgsym_$(LIBSAIREDIS_VERSION)_$(CONFIGURED_ARCH).deb +$(LIBSAIVS_DBGSYM)_DEPENDS += $(LIBSAIVS) +$(LIBSAIVS_DBGSYM)_RDEPENDS += $(LIBSAIVS) +$(eval $(call add_derived_package,$(LIBSAIREDIS),$(LIBSAIVS_DBGSYM))) -LIBSAIMETADATA_DBG = libsaimetadata-dbg_$(LIBSAIREDIS_VERSION)_$(CONFIGURED_ARCH).deb -$(LIBSAIMETADATA_DBG)_DEPENDS += $(LIBSAIMETADATA) -$(LIBSAIMETADATA_DBG)_RDEPENDS += $(LIBSAIMETADATA) -$(eval $(call add_derived_package,$(LIBSAIREDIS),$(LIBSAIMETADATA_DBG))) +LIBSAIMETADATA_DBGSYM = libsaimetadata-dbgsym_$(LIBSAIREDIS_VERSION)_$(CONFIGURED_ARCH).deb +$(LIBSAIMETADATA_DBGSYM)_DEPENDS += $(LIBSAIMETADATA) +$(LIBSAIMETADATA_DBGSYM)_RDEPENDS += $(LIBSAIMETADATA) +$(eval $(call add_derived_package,$(LIBSAIREDIS),$(LIBSAIMETADATA_DBGSYM))) ifeq ($(ENABLE_PY2_MODULES), n) - $(LIBSAIREDIS)_BUILD_ENV += DEB_BUILD_PROFILES=nopython2 + $(LIBSAIREDIS)_DEB_BUILD_PROFILES += nopython2 endif # The .c, .cpp, .h & .hpp files under src/{$DBG_SRC_ARCHIVE list} diff --git a/rules/sonic-dash-api.dep b/rules/sonic-dash-api.dep index 6bf9209e499d..6d4ffcad847f 100644 --- a/rules/sonic-dash-api.dep +++ b/rules/sonic-dash-api.dep @@ -2,7 +2,8 @@ SPATH := $($(LIB_SONIC_DASH_API)_SRC_PATH) DEP_FILES := $(SONIC_COMMON_FILES_LIST) rules/sonic-dash-api.mk rules/sonic-dash-api.dep DEP_FILES += $(SONIC_COMMON_BASE_FILES_LIST) -SMDEP_FILES := $(addprefix $(SPATH)/,$(shell cd $(SPATH) && git ls-files)) +DEP_FILES += $(shell git ls-files $(SPATH) | grep -v sonic-dash-api) +SMDEP_FILES := $(addprefix $(SPATH)/sonic-dash-api/,$(shell cd $(SPATH)/sonic-dash-api && git ls-files)) $(LIB_SONIC_DASH_API)_CACHE_MODE := GIT_CONTENT_SHA $(LIB_SONIC_DASH_API)_DEP_FLAGS := $(SONIC_COMMON_FLAGS_LIST) diff --git a/rules/sonic-dash-api.mk b/rules/sonic-dash-api.mk index eeea7271d8cc..e6d9e34c0395 100644 --- a/rules/sonic-dash-api.mk +++ b/rules/sonic-dash-api.mk @@ -6,7 +6,7 @@ LIB_SONIC_DASH_API = libdashapi_$(LIB_SONIC_DASH_API_VERSION)_$(CONFIGURED_ARCH) $(LIB_SONIC_DASH_API)_SRC_PATH = $(SRC_PATH)/sonic-dash-api $(LIB_SONIC_DASH_API)_DEPENDS += $(PROTOBUF) $(PROTOBUF_LITE) $(PROTOBUF_DEV) $(PROTOBUF_COMPILER) -$(LIB_SONIC_DASH_API)_RDEPENDS += $(LIBSWSSCOMMON) $(LIBNL3) $(LIBNL_GENL3) $(LIBNL_ROUTE3) $(PROTOBUF) $(PROTOBUF_LITE) +$(LIB_SONIC_DASH_API)_RDEPENDS += $(PROTOBUF) $(PROTOBUF_LITE) $(PYTHON3_PROTOBUF) SONIC_DPKG_DEBS += $(LIB_SONIC_DASH_API) diff --git a/rules/sonic-host-services.mk b/rules/sonic-host-services.mk index eeb931ce5666..6d204fa41e0a 100644 --- a/rules/sonic-host-services.mk +++ b/rules/sonic-host-services.mk @@ -3,7 +3,8 @@ SONIC_HOST_SERVICES_PY3 = sonic_host_services-1.0-py3-none-any.whl $(SONIC_HOST_SERVICES_PY3)_SRC_PATH = $(SRC_PATH)/sonic-host-services $(SONIC_HOST_SERVICES_PY3)_PYTHON_VERSION = 3 -$(SONIC_HOST_SERVICES_PY3)_DEPENDS += $(SONIC_PY_COMMON_PY3) +$(SONIC_HOST_SERVICES_PY3)_DEPENDS += $(SONIC_PY_COMMON_PY3) \ + $(SONIC_UTILITIES_PY3) $(SONIC_HOST_SERVICES_PY3)_DEBS_DEPENDS = $(LIBSWSSCOMMON) \ $(PYTHON3_SWSSCOMMON) SONIC_PYTHON_WHEELS += $(SONIC_HOST_SERVICES_PY3) diff --git a/rules/sonic-mgmt-common.mk b/rules/sonic-mgmt-common.mk index cde659484df6..41441ab3ee94 100644 --- a/rules/sonic-mgmt-common.mk +++ b/rules/sonic-mgmt-common.mk @@ -5,6 +5,7 @@ SONIC_MGMT_COMMON = sonic-mgmt-common_$(MGMT_COMMON_VERSION)_$(CONFIGURED_ARCH). $(SONIC_MGMT_COMMON)_SRC_PATH = $(SRC_PATH)/sonic-mgmt-common $(SONIC_MGMT_COMMON)_DEPENDS = $(LIBYANG_DEV) $(LIBYANG) $(SONIC_MGMT_COMMON)_RDEPENDS = $(LIBYANG) +$(SONIC_MGMT_COMMON)_WHEEL_DEPENDS = $(SONIC_YANG_MODELS_PY3) SONIC_DPKG_DEBS += $(SONIC_MGMT_COMMON) SONIC_MGMT_COMMON_CODEGEN = sonic-mgmt-common-codegen_$(MGMT_COMMON_VERSION)_$(CONFIGURED_ARCH).deb diff --git a/rules/swss-common.mk b/rules/swss-common.mk index 462e0b3e96f3..838c9a6725da 100644 --- a/rules/swss-common.mk +++ b/rules/swss-common.mk @@ -21,7 +21,7 @@ ifeq ($(ENABLE_PY2_MODULES), y) PYTHON_SWSSCOMMON = python-swsscommon_$(LIBSWSSCOMMON_VERSION)_$(CONFIGURED_ARCH).deb $(eval $(call add_derived_package,$(LIBSWSSCOMMON),$(PYTHON_SWSSCOMMON))) else - $(LIBSWSSCOMMON)_BUILD_ENV += DEB_BUILD_PROFILES=nopython2 + $(LIBSWSSCOMMON)_DEB_BUILD_PROFILES += nopython2 endif PYTHON3_SWSSCOMMON = python3-swsscommon_$(LIBSWSSCOMMON_VERSION)_$(CONFIGURED_ARCH).deb diff --git a/rules/syncd.mk b/rules/syncd.mk index 225f7ec0574c..2f5cce6cebff 100644 --- a/rules/syncd.mk +++ b/rules/syncd.mk @@ -4,7 +4,7 @@ ifneq ($(CONFIGURED_PLATFORM),vs) SYNCD = syncd_1.0.0_$(CONFIGURED_ARCH).deb $(SYNCD)_RDEPENDS += $(LIBSAIREDIS) $(LIBSAIMETADATA) -$(SYNCD)_DPKG_TARGET = binary-syncd +$(SYNCD)_DEB_BUILD_PROFILES += syncd $(SYNCD)_SRC_PATH = $(SRC_PATH)/sonic-sairedis $(SYNCD)_DEPENDS += $(LIBSWSSCOMMON_DEV) $(LIBSAIREDIS) $(SYNCD)_RDEPENDS += $(LIBSWSSCOMMON) @@ -18,23 +18,23 @@ $(eval $(call add_derived_package,$(SYNCD),$(SYNCD_RPC))) # Inject libthrift build dependency for RPC build $(SYNCD)_DEPENDS += $(LIBSWSSCOMMON_DEV) $(LIBTHRIFT_DEV) -$(SYNCD)_DPKG_TARGET = binary-syncd-rpc +$(SYNCD)_DEB_BUILD_PROFILES += rpc endif -SYNCD_DBG = syncd-dbg_1.0.0_$(CONFIGURED_ARCH).deb -$(SYNCD_DBG)_DEPENDS += $(SYNCD) -$(SYNCD_DBG)_RDEPENDS += $(SYNCD) -$(eval $(call add_derived_package,$(SYNCD),$(SYNCD_DBG))) +SYNCD_DBGSYM = syncd-dbgsym_1.0.0_$(CONFIGURED_ARCH).deb +$(SYNCD_DBGSYM)_DEPENDS += $(SYNCD) +$(SYNCD_DBGSYM)_RDEPENDS += $(SYNCD) +$(eval $(call add_derived_package,$(SYNCD),$(SYNCD_DBGSYM))) ifeq ($(ENABLE_SYNCD_RPC),y) -SYNCD_RPC_DBG = syncd-rpc-dbg_1.0.0_$(CONFIGURED_ARCH).deb -$(SYNCD_RPC_DBG)_DEPENDS += $(SYNCD_RPC) -$(SYNCD_RPC_DBG)_RDEPENDS += $(SYNCD_RPC) -$(eval $(call add_derived_package,$(SYNCD),$(SYNCD_RPC_DBG))) +SYNCD_RPC_DBGSYM = syncd-rpc-dbgsym_1.0.0_$(CONFIGURED_ARCH).deb +$(SYNCD_RPC_DBGSYM)_DEPENDS += $(SYNCD_RPC) +$(SYNCD_RPC_DBGSYM)_RDEPENDS += $(SYNCD_RPC) +$(eval $(call add_derived_package,$(SYNCD),$(SYNCD_RPC_DBGSYM))) endif ifeq ($(ENABLE_PY2_MODULES), n) - $(SYNCD)_BUILD_ENV += DEB_BUILD_PROFILES=nopython2 + $(SYNCD)_DEB_BUILD_PROFILES += nopython2 endif endif diff --git a/rules/tacacs.dep b/rules/tacacs.dep index f7e807f9c47c..dedbd9e482b8 100644 --- a/rules/tacacs.dep +++ b/rules/tacacs.dep @@ -1,7 +1,7 @@ #DPKG FRK SPATH := $($(LIBTAC2)_SRC_PATH) -DEP_FILES := $(SONIC_COMMON_FILES_LIST) rules/tacacs.mk rules/tacacs.dep +DEP_FILES := $(SONIC_COMMON_FILES_LIST) rules/tacacs.mk rules/tacacs.dep DEP_FILES += $(SONIC_COMMON_BASE_FILES_LIST) DEP_FILES += $(shell git ls-files $(SPATH)) @@ -33,3 +33,15 @@ $(BASH_TACPLUS)_CACHE_MODE := GIT_CONTENT_SHA $(BASH_TACPLUS)_DEP_FLAGS := $(SONIC_COMMON_FLAGS_LIST) $(BASH_TACPLUS)_DEP_FILES := $(DEP_FILES) + + + +SPATH := $($(AUDISP_TACPLUS)_SRC_PATH) +DEP_FILES := $(SONIC_COMMON_FILES_LIST) rules/tacacs.mk rules/tacacs.dep +DEP_FILES += $(SONIC_COMMON_BASE_FILES_LIST) +DEP_FILES += $(shell git ls-files $(SPATH)) + +$(AUDISP_TACPLUS)_CACHE_MODE := GIT_CONTENT_SHA +$(AUDISP_TACPLUS)_DEP_FLAGS := $(SONIC_COMMON_FLAGS_LIST) +$(AUDISP_TACPLUS)_DEP_FILES := $(DEP_FILES) + diff --git a/slave.mk b/slave.mk index f2b39cc3e170..79ae6646c8a1 100644 --- a/slave.mk +++ b/slave.mk @@ -653,7 +653,7 @@ $(addprefix $(FILES_PATH)/, $(SONIC_MAKE_FILES)) : $(FILES_PATH)/% : .platform $ # Remove target to force rebuild rm -f $(addprefix $(FILES_PATH)/, $*) # Apply series of patches if exist - if [ -f $($*_SRC_PATH).patch/series ]; then pushd $($*_SRC_PATH) && quilt applied || QUILT_PATCHES=../$(notdir $($*_SRC_PATH)).patch quilt push -a; popd; fi $(LOG) + if [ -f $($*_SRC_PATH).patch/series ]; then pushd $($*_SRC_PATH) && ( quilt pop -a -f 1>/dev/null 2>&1 || true ) && QUILT_PATCHES=../$(notdir $($*_SRC_PATH)).patch quilt push -a; popd; fi $(LOG) # Build project and take package make DEST=$(shell pwd)/$(FILES_PATH) -C $($*_SRC_PATH) $(shell pwd)/$(FILES_PATH)/$* $(LOG) # Clean up @@ -684,6 +684,7 @@ SONIC_TARGET_LIST += $(addprefix $(FILES_PATH)/, $(SONIC_MAKE_FILES)) # $(SOME_NEW_DEB)_DEPENDS = $(SOME_OTHER_DEB1) $(SOME_OTHER_DEB2) ... # SONIC_MAKE_DEBS += $(SOME_NEW_DEB) $(addprefix $(DEBS_PATH)/, $(SONIC_MAKE_DEBS)) : $(DEBS_PATH)/% : .platform $$(addsuffix -install,$$(addprefix $(DEBS_PATH)/,$$($$*_DEPENDS))) \ + $$(addsuffix -install,$$(addprefix $(PYTHON_WHEELS_PATH)/,$$($$*_WHEEL_DEPENDS))) \ $$(addprefix $(DEBS_PATH)/,$$($$*_AFTER)) \ $(call dpkg_depend,$(DEBS_PATH)/%.dep) $(HEADER) @@ -697,7 +698,7 @@ $(addprefix $(DEBS_PATH)/, $(SONIC_MAKE_DEBS)) : $(DEBS_PATH)/% : .platform $$(a # Remove target to force rebuild rm -f $(addprefix $(DEBS_PATH)/, $* $($*_DERIVED_DEBS) $($*_EXTRA_DEBS)) # Apply series of patches if exist - if [ -f $($*_SRC_PATH).patch/series ]; then pushd $($*_SRC_PATH) && quilt applied || QUILT_PATCHES=../$(notdir $($*_SRC_PATH)).patch quilt push -a; popd; fi $(LOG) + if [ -f $($*_SRC_PATH).patch/series ]; then pushd $($*_SRC_PATH) && ( quilt pop -a -f 1>/dev/null 2>&1 || true ) && QUILT_PATCHES=../$(notdir $($*_SRC_PATH)).patch quilt push -a; popd; fi $(LOG) # Build project and take package $(SETUP_OVERLAYFS_FOR_DPKG_ADMINDIR) DEB_BUILD_OPTIONS="${DEB_BUILD_OPTIONS_GENERIC}" $(ANT_DEB_CONFIG) $(CROSS_COMPILE_FLAGS) make -j$(SONIC_CONFIG_MAKE_JOBS) DEST=$(shell pwd)/$(DEBS_PATH) -C $($*_SRC_PATH) $(shell pwd)/$(DEBS_PATH)/$* $(LOG) @@ -737,14 +738,14 @@ $(addprefix $(DEBS_PATH)/, $(SONIC_DPKG_DEBS)) : $(DEBS_PATH)/% : .platform $$(a # Remove old build logs if they exist rm -f $($*_SRC_PATH)/debian/*.debhelper.log # Apply series of patches if exist - if [ -f $($*_SRC_PATH).patch/series ]; then pushd $($*_SRC_PATH) && quilt applied || QUILT_PATCHES=../$(notdir $($*_SRC_PATH)).patch quilt push -a; popd; fi $(LOG) + if [ -f $($*_SRC_PATH).patch/series ]; then pushd $($*_SRC_PATH) && ( quilt pop -a -f 1>/dev/null 2>&1 || true ) && QUILT_PATCHES=../$(notdir $($*_SRC_PATH)).patch quilt push -a; popd; fi $(LOG) # Build project pushd $($*_SRC_PATH) $(LOG_SIMPLE) if [ -f ./autogen.sh ]; then ./autogen.sh $(LOG); fi $(SETUP_OVERLAYFS_FOR_DPKG_ADMINDIR) $(if $($*_DPKG_TARGET), - ${$*_BUILD_ENV} DEB_BUILD_OPTIONS="${DEB_BUILD_OPTIONS_GENERIC} ${$*_DEB_BUILD_OPTIONS}" $(ANT_DEB_CONFIG) $(CROSS_COMPILE_FLAGS) dpkg-buildpackage -rfakeroot -b $(ANT_DEB_CROSS_OPT) -us -uc -tc -j$(SONIC_CONFIG_MAKE_JOBS) --as-root -T$($*_DPKG_TARGET) --admindir $$mergedir $(LOG), - ${$*_BUILD_ENV} DEB_BUILD_OPTIONS="${DEB_BUILD_OPTIONS_GENERIC} ${$*_DEB_BUILD_OPTIONS}" $(ANT_DEB_CONFIG) $(CROSS_COMPILE_FLAGS) dpkg-buildpackage -rfakeroot -b $(ANT_DEB_CROSS_OPT) -us -uc -tc -j$(SONIC_CONFIG_MAKE_JOBS) --admindir $$mergedir $(LOG) + ${$*_BUILD_ENV} DEB_BUILD_OPTIONS="${DEB_BUILD_OPTIONS_GENERIC} ${$*_DEB_BUILD_OPTIONS}" DEB_BUILD_PROFILES="${$*_DEB_BUILD_PROFILES}" $(ANT_DEB_CONFIG) $(CROSS_COMPILE_FLAGS) dpkg-buildpackage -rfakeroot -b $(ANT_DEB_CROSS_OPT) -us -uc -tc -j$(SONIC_CONFIG_MAKE_JOBS) --as-root -T$($*_DPKG_TARGET) --admindir $$mergedir $(LOG), + ${$*_BUILD_ENV} DEB_BUILD_OPTIONS="${DEB_BUILD_OPTIONS_GENERIC} ${$*_DEB_BUILD_OPTIONS}" DEB_BUILD_PROFILES="${$*_DEB_BUILD_PROFILES}" $(ANT_DEB_CONFIG) $(CROSS_COMPILE_FLAGS) dpkg-buildpackage -rfakeroot -b $(ANT_DEB_CROSS_OPT) -us -uc -tc -j$(SONIC_CONFIG_MAKE_JOBS) --admindir $$mergedir $(LOG) ) popd $(LOG_SIMPLE) # Clean up @@ -851,7 +852,7 @@ $(addprefix $(PYTHON_DEBS_PATH)/, $(SONIC_PYTHON_STDEB_DEBS)) : $(PYTHON_DEBS_PA if [ -z '$($*_CACHE_LOADED)' ] ; then # Apply series of patches if exist - if [ -f $($*_SRC_PATH).patch/series ]; then pushd $($*_SRC_PATH) && quilt applied || QUILT_PATCHES=../$(notdir $($*_SRC_PATH)).patch quilt push -a; popd; fi $(LOG) + if [ -f $($*_SRC_PATH).patch/series ]; then pushd $($*_SRC_PATH) && ( quilt pop -a -f 1>/dev/null 2>&1 || true ) && QUILT_PATCHES=../$(notdir $($*_SRC_PATH)).patch quilt push -a; popd; fi $(LOG) # Build project pushd $($*_SRC_PATH) $(LOG_SIMPLE) rm -rf deb_dist/* $(LOG) @@ -891,7 +892,7 @@ $(addprefix $(PYTHON_WHEELS_PATH)/, $(SONIC_PYTHON_WHEELS)) : $(PYTHON_WHEELS_PA pushd $($*_SRC_PATH) $(LOG_SIMPLE) # apply series of patches if exist - if [ -f ../$(notdir $($*_SRC_PATH)).patch/series ]; then quilt applied || QUILT_PATCHES=../$(notdir $($*_SRC_PATH)).patch quilt push -a; fi $(LOG) + if [ -f ../$(notdir $($*_SRC_PATH)).patch/series ]; then ( quilt pop -a -f 1>/dev/null 2>&1 || true ) && QUILT_PATCHES=../$(notdir $($*_SRC_PATH)).patch quilt push -a; fi $(LOG) ifneq ($(CROSS_BUILD_ENVIRON),y) # Use pip instead of later setup.py to install dependencies into user home, but uninstall self pip$($*_PYTHON_VERSION) install . && pip$($*_PYTHON_VERSION) uninstall --yes `python$($*_PYTHON_VERSION) setup.py --name` @@ -957,7 +958,7 @@ docker-start : $(addprefix $(TARGET_PATH)/, $(SONIC_SIMPLE_DOCKER_IMAGES)) : $(TARGET_PATH)/%.gz : .platform docker-start $$(addsuffix -load,$$(addprefix $(TARGET_PATH)/,$$($$*.gz_LOAD_DOCKERS))) $(HEADER) # Apply series of patches if exist - if [ -f $($*.gz_PATH).patch/series ]; then pushd $($*.gz_PATH) && quilt applied || QUILT_PATCHES=../$(notdir $($*.gz_PATH)).patch quilt push -a; popd; fi $(LOG) + if [ -f $($*.gz_PATH).patch/series ]; then pushd $($*.gz_PATH) && ( quilt pop -a -f 1>/dev/null 2>&1 || true ) && QUILT_PATCHES=../$(notdir $($*.gz_PATH)).patch quilt push -a; popd; fi $(LOG) # Prepare docker build info SONIC_ENFORCE_VERSIONS=$(SONIC_ENFORCE_VERSIONS) \ TRUSTED_GPG_URLS=$(TRUSTED_GPG_URLS) \ @@ -1055,7 +1056,7 @@ $(addprefix $(TARGET_PATH)/, $(DOCKER_IMAGES)) : $(TARGET_PATH)/%.gz : .platform if [ -z '$($*.gz_CACHE_LOADED)' ] ; then # Apply series of patches if exist - if [ -f $($*.gz_PATH).patch/series ]; then pushd $($*.gz_PATH) && quilt applied || QUILT_PATCHES=../$(notdir $($*.gz_PATH)).patch quilt push -a; popd; fi $(LOG) + if [ -f $($*.gz_PATH).patch/series ]; then pushd $($*.gz_PATH) && ( quilt pop -a -f 1>/dev/null 2>&1 || true ) && QUILT_PATCHES=../$(notdir $($*.gz_PATH)).patch quilt push -a; popd; fi $(LOG) mkdir -p $($*.gz_PATH)/debs $(LOG) mkdir -p $($*.gz_PATH)/files $(LOG) mkdir -p $($*.gz_PATH)/python-debs $(LOG) @@ -1454,6 +1455,11 @@ $(addprefix $(TARGET_PATH)/, $(SONIC_INSTALLERS)) : $(TARGET_PATH)/% : \ MASTER_COREDNS_VERSION=$(MASTER_COREDNS_VERSION) \ MASTER_ETCD_VERSION=$(MASTER_ETCD_VERSION) \ MASTER_CRI_DOCKERD=$(MASTER_CRI_DOCKERD) \ + MASTER_UI_METRIC_VERSION=$(MASTER_UI_METRIC_VERSION) \ + MASTER_UI_DASH_VERSION=$(MASTER_UI_DASH_VERSION) \ + MASTER_MDM_VERSION=$(MASTER_MDM_VERSION) \ + MASTER_MDS_VERSION=$(MASTER_MDS_VERSION) \ + MASTER_FLUENTD_VERSION=$(MASTER_FLUENTD_VERSION) \ ./build_debian.sh $(LOG) USERNAME="$(USERNAME)" \ @@ -1519,7 +1525,7 @@ SONIC_CLEAN_TARGETS += $(addsuffix -clean,$(addprefix $(TARGET_PATH)/, \ $(SONIC_SIMPLE_DOCKER_IMAGES) \ $(SONIC_INSTALLERS))) $(SONIC_CLEAN_TARGETS) :: $(TARGET_PATH)/%-clean : .platform - $(Q)rm -f $(TARGET_PATH)/$* target/versions/dockers/$(subst .gz,,$*) + $(Q)rm -rf $(TARGET_PATH)/$* target/versions/dockers/$(subst .gz,,$*) SONIC_CLEAN_STDEB_DEBS = $(addsuffix -clean,$(addprefix $(PYTHON_DEBS_PATH)/, \ $(SONIC_PYTHON_STDEB_DEBS))) @@ -1566,4 +1572,4 @@ jessie : $$(addprefix $(TARGET_PATH)/,$$(JESSIE_DOCKER_IMAGES)) \ ## To build some commonly used libs. Some submodules depend on these libs. ## It is used in component pipelines. For example: swss needs libnl, libyang -lib-packages: $(addprefix $(DEBS_PATH)/,$(LIBNL3) $(LIBYANG)) +lib-packages: $(addprefix $(DEBS_PATH)/,$(LIBNL3) $(LIBYANG) $(PROTOBUF) $(LIB_SONIC_DASH_API)) diff --git a/sonic-slave-bullseye/Dockerfile.j2 b/sonic-slave-bullseye/Dockerfile.j2 index bc97ed56b1a9..7294bc2efbfa 100644 --- a/sonic-slave-bullseye/Dockerfile.j2 +++ b/sonic-slave-bullseye/Dockerfile.j2 @@ -536,7 +536,8 @@ RUN pip3 uninstall -y enum34 RUN pip3 install j2cli==0.3.10 # For sonic-mgmt-framework -RUN pip3 install "PyYAML==5.4.1" +# The option --no-build-isolation can be removed when upgrading PyYAML to 6.0.1 +RUN pip3 install "PyYAML==5.4.1" --no-build-isolation {%- if CROSS_BUILD_ENVIRON != "y" %} RUN pip3 install "lxml==4.9.1" {%- endif %} @@ -578,10 +579,6 @@ RUN cd /usr/src/gtest && cmake . && make -C /usr/src/gtest RUN mkdir /var/run/sshd EXPOSE 22 -# Install depot-tools (for git-retry) -RUN git clone https://chromium.googlesource.com/chromium/tools/depot_tools.git /usr/share/depot_tools -ENV PATH /usr/share/depot_tools:$PATH - # Install dependencies for dhcp relay test RUN pip3 install parameterized==0.8.1 RUN pip3 install pyfakefs diff --git a/sonic-slave-buster/Dockerfile.j2 b/sonic-slave-buster/Dockerfile.j2 index 7e0bf6d06bcf..637ac02f857e 100644 --- a/sonic-slave-buster/Dockerfile.j2 +++ b/sonic-slave-buster/Dockerfile.j2 @@ -541,8 +541,9 @@ RUN pip3 install MarkupSafe==2.0.1 RUN pip3 install Jinja2==3.0.3 # For sonic-mgmt-framework -RUN pip2 install "PyYAML==5.4.1" -RUN pip3 install "PyYAML==5.4.1" +# The option --no-build-isolation can be removed when upgrading PyYAML to 6.0.1 +RUN pip2 install "PyYAML==5.4.1" --no-build-isolation +RUN pip3 install "PyYAML==5.4.1" --no-build-isolation {%- if CROSS_BUILD_ENVIRON != "y" %} RUN pip2 install "lxml==4.9.1" diff --git a/src/dhcprelay b/src/dhcprelay index c36b8e3d2113..6a6ce245125d 160000 --- a/src/dhcprelay +++ b/src/dhcprelay @@ -1 +1 @@ -Subproject commit c36b8e3d2113976f319fb02db94971e9b27e6416 +Subproject commit 6a6ce245125d600ad07fc02638e96ba6c18d1b4b diff --git a/src/linkmgrd b/src/linkmgrd index 4bda49bd71ac..b0adf57655eb 160000 --- a/src/linkmgrd +++ b/src/linkmgrd @@ -1 +1 @@ -Subproject commit 4bda49bd71acccb644293da662a9ac937ddd6e7a +Subproject commit b0adf57655eb1e72316c6f90fe0a2d072322f473 diff --git a/src/radius/nss/libnss-radius/nss_radius_common.c b/src/radius/nss/libnss-radius/nss_radius_common.c index 652d04ae5c7b..bd828ffc8036 100644 --- a/src/radius/nss/libnss-radius/nss_radius_common.c +++ b/src/radius/nss/libnss-radius/nss_radius_common.c @@ -25,6 +25,7 @@ The term "Broadcom" refers to Broadcom Inc. and/or its subsidiaries. #include #include #include +#include #include "nss_radius_common.h" @@ -167,6 +168,124 @@ static void init_rnm(RADIUS_NSS_CONF_B * conf) { } +static int user_add(const char* name, char* gid, char* sec_grp, char* gecos, + char* home, char* shell, const char* unconfirmed_user, int many_to_one) { + pid_t pid, w; + int status = 0; + int wstatus; + char cmd[64]; + + snprintf(cmd, 63, "%s", USERADD); + + pid = fork(); + + if(pid > 0) { + do { + w = waitpid(pid, &wstatus, WUNTRACED | WCONTINUED); + if (w == -1) + return -1; + } while (!WIFEXITED(wstatus) && !WIFSIGNALED(wstatus)); + if WIFEXITED(wstatus) + return WEXITSTATUS(wstatus); + else + return -1; + + // Child + + } else if(pid == 0) { + + if (many_to_one) + execl(cmd, cmd, "-g", gid, "-G", sec_grp, "-c", gecos, "-m", "-s", shell, name, NULL); + else + execl(cmd, cmd, "-U", "-G", sec_grp, "-c", unconfirmed_user, "-d", home, "-m", "-s", shell, name, NULL); + syslog(LOG_ERR, "exec of %s failed with errno=%d", cmd, errno); + return -1; + + // Error + } else { + fprintf(stderr, "error forking the child\n"); + return -1; + } + + return status; +} + +static int user_del(const char* name) { + pid_t pid, w; + int status = 0; + int wstatus; + char cmd[64]; + + snprintf(cmd, 63, "%s", USERDEL); + + pid = fork(); + + if(pid > 0) { + do { + w = waitpid(pid, &wstatus, WUNTRACED | WCONTINUED); + if (w == -1) + return -1; + } while (!WIFEXITED(wstatus) && !WIFSIGNALED(wstatus)); + if WIFEXITED(wstatus) + return WEXITSTATUS(wstatus); + else + return -1; + + // Child + + } else if(pid == 0) { + + execl(cmd, cmd, "-r", name, NULL); + syslog(LOG_ERR, "exec of %s failed with errno=%d", cmd, errno); + return -1; + + // Error + } else { + fprintf(stderr, "error forking the child\n"); + return -1; + } + + return status; +} + +static int user_mod(const char* name, char* sec_grp) { + pid_t pid, w; + int status = 0; + int wstatus; + char cmd[64]; + + snprintf(cmd, 63, "%s", USERMOD); + + pid = fork(); + + if(pid > 0) { + do { + w = waitpid(pid, &wstatus, WUNTRACED | WCONTINUED); + if (w == -1) + return -1; + } while (!WIFEXITED(wstatus) && !WIFSIGNALED(wstatus)); + if WIFEXITED(wstatus) + return WEXITSTATUS(wstatus); + else + return -1; + + // Child + + } else if(pid == 0) { + + execl(cmd, cmd, "-G", sec_grp, "-c", name, name, NULL); + syslog(LOG_ERR, "exec of %s failed with errno=%d", cmd, errno); + return -1; + + // Error + } else { + fprintf(stderr, "error forking the child\n"); + return -1; + } + + return status; +} + int parse_nss_config(RADIUS_NSS_CONF_B * conf, char * prog, char * file_buf, int file_buf_sz, int * errnop, int * plockfd) { @@ -379,22 +498,6 @@ int unparse_nss_config(RADIUS_NSS_CONF_B * conf, int * errnop, int * plockfd) { return 0; } -static int invoke_popen(RADIUS_NSS_CONF_B * conf, char * cmd) { - FILE * fp; - int status = 0; - - if (conf->debug) - syslog(LOG_DEBUG, "%s:%s", conf->prog, cmd); - - if (((fp = popen(cmd, "r")) == NULL) || (pclose(fp) == -1)) { - syslog(LOG_ERR, "%s: %s: popen()/pclose() failed %p, errno=%d", - conf->prog, cmd, fp, errno); - status = errno; - } - - return status; -} - static int radius_getpwnam_r_cleanup(int status, FILE * fp) { if (fp) fclose(fp); @@ -434,10 +537,8 @@ static int radius_update_user_cleanup(int status) { int radius_update_user(RADIUS_NSS_CONF_B * conf, const char * user, int mpl) { char buf[BUFLEN]; - char usermod[4096]; struct passwd pw, *result = NULL; RADIUS_NSS_MPL * rnm = NULL; - int written = 0; int status; /* Verify uid is not in the reserved range (<=1000). @@ -466,82 +567,53 @@ int radius_update_user(RADIUS_NSS_CONF_B * conf, const char * user, int mpl) { if (conf->trace) dump_rnm(mpl, rnm, "update"); - written = snprintf(usermod, sizeof(usermod), - "%s -G %s -c \"%s\" \"%s\"", USERMOD, rnm->groups, user, user); - - if (written >= sizeof(usermod)) { - syslog(LOG_ERR, - "%s: truncated usermod cmd. Skipping:\"%s\"\n", conf->prog, usermod); - return radius_update_user_cleanup(STATUS_E2BIG); + if(0 != user_mod(user, rnm->groups)) { + syslog(LOG_ERR, "%s: %s %s failed", conf->prog, USERMOD, user); + return -1; } - - return radius_update_user_cleanup(invoke_popen(conf, usermod)); -} - -static int radius_create_user_cleanup(int status) { - return status; + return 0; } int radius_create_user(RADIUS_NSS_CONF_B * conf, const char * user, int mpl, int unconfirmed) { - char buf[BUFLEN]; - char useradd[4096]; + char buf[BUFLEN] = {0}; RADIUS_NSS_MPL * rnm = &((conf->rnm)[mpl-1]); - int written = 0; if (conf->trace) dump_rnm(mpl, rnm, "create"); + if(strlen(user) > 32) { + syslog(LOG_ERR, "%s: Username too long", conf->prog); + return -1; + } - if (conf->many_to_one) { + syslog(LOG_INFO, "%s: Creating user \"%s\"", conf->prog, user); - written = snprintf(useradd, sizeof(useradd), - "%s -g %d -G %s -c \"%s\" -m -s %s \"%s\"", - USERADD, rnm->gid, rnm->groups, rnm->gecos, rnm->shell, user); + char sgid[10] = {0}; + char home[64] = {0}; + snprintf(sgid, 10, "%d", rnm->gid); + snprintf(home, 63, "/home/%s", user); - } else { + snprintf(buf, sizeof(buf), "Unconfirmed-%ld", time(NULL)); - snprintf(buf, sizeof(buf), "Unconfirmed-%ld", time(NULL)); - written = snprintf(useradd, sizeof(useradd), - "%s -U -G %s -c \"%s\" -d \"/home/%s\" -m -s %s \"%s\"", - USERADD, rnm->groups, unconfirmed ? buf : user, user, - rnm->shell, user); - - } + if(0 != user_add(user, sgid, rnm->groups, rnm->gecos, home, rnm->shell, unconfirmed ? buf : user, conf->many_to_one)) { + syslog(LOG_ERR, "%s: %s %s failed", conf->prog, USERADD, user); - if (written >= sizeof(useradd)) { - syslog(LOG_ERR, - "%s: truncated useradd cmd. Skipping:\"%s\"\n", conf->prog, useradd); - return radius_create_user_cleanup(STATUS_E2BIG); + return -1; } - - syslog(LOG_INFO, "%s: Creating user \"%s\"", conf->prog, user); - - return radius_create_user_cleanup(invoke_popen(conf, useradd)); -} - -static int radius_delete_user_cleanup(int status) { - return status; + return 0; } int radius_delete_user(RADIUS_NSS_CONF_B * conf, const char * user) { - char buf[BUFLEN]; - char userdel[4096]; - int written = 0; - - written = snprintf(userdel, sizeof(userdel), "%s -r \"%s\"", USERDEL, user); - - if (written >= sizeof(userdel)) { - syslog(LOG_ERR, - "%s: truncated userdel cmd. Skipping:\"%s\"\n", conf->prog, userdel); - return radius_delete_user_cleanup(STATUS_E2BIG); - } - syslog(LOG_INFO, "%s: Deleting user \"%s\"", conf->prog, user); + if(0 != user_del(user)) { + syslog(LOG_ERR, "%s: %s %s failed", conf->prog, USERDEL, user); - return radius_delete_user_cleanup(invoke_popen(conf, userdel)); + return -1; + } + return 0; } int radius_clear_unconfirmed_users_cleanup(int status, FILE * fp) { diff --git a/src/sonic-bgpcfgd/bgpcfgd/main.py b/src/sonic-bgpcfgd/bgpcfgd/main.py index d6434a193106..624d311037ad 100644 --- a/src/sonic-bgpcfgd/bgpcfgd/main.py +++ b/src/sonic-bgpcfgd/bgpcfgd/main.py @@ -60,6 +60,7 @@ def do_work(): BGPPeerMgrBase(common_objs, "CONFIG_DB", "BGP_MONITORS", "monitors", False), BGPPeerMgrBase(common_objs, "CONFIG_DB", "BGP_PEER_RANGE", "dynamic", False), BGPPeerMgrBase(common_objs, "CONFIG_DB", "BGP_VOQ_CHASSIS_NEIGHBOR", "voq_chassis", False), + BGPPeerMgrBase(common_objs, "CONFIG_DB", "BGP_SENTINELS", "sentinels", False), # AllowList Managers BGPAllowListMgr(common_objs, "CONFIG_DB", "BGP_ALLOWED_PREFIXES"), # BBR Manager diff --git a/src/sonic-bgpcfgd/tests/data/sentinels/instance.conf/param_all_v4.json b/src/sonic-bgpcfgd/tests/data/sentinels/instance.conf/param_all_v4.json new file mode 100644 index 000000000000..13a73405c74c --- /dev/null +++ b/src/sonic-bgpcfgd/tests/data/sentinels/instance.conf/param_all_v4.json @@ -0,0 +1,8 @@ +{ + "bgp_asn": "555", + "bgp_session": { + "ip_range": "10.10.20.0/24,20.20.20.0/24", + "name": "BGPSentinel", + "src_address": "1.1.1.1" + } +} diff --git a/src/sonic-bgpcfgd/tests/data/sentinels/instance.conf/param_all_v6.json b/src/sonic-bgpcfgd/tests/data/sentinels/instance.conf/param_all_v6.json new file mode 100644 index 000000000000..05765bbd7409 --- /dev/null +++ b/src/sonic-bgpcfgd/tests/data/sentinels/instance.conf/param_all_v6.json @@ -0,0 +1,8 @@ +{ + "bgp_asn": "555", + "bgp_session": { + "ip_range": "2603:10a0:321:82f9::/64,2603:10a1:30a:8000::/59", + "name": "BGPSentinelV6", + "src_address": "fc00:1::32" + } +} diff --git a/src/sonic-bgpcfgd/tests/data/sentinels/instance.conf/result_all_v4.conf b/src/sonic-bgpcfgd/tests/data/sentinels/instance.conf/result_all_v4.conf new file mode 100644 index 000000000000..7a64e2cd4894 --- /dev/null +++ b/src/sonic-bgpcfgd/tests/data/sentinels/instance.conf/result_all_v4.conf @@ -0,0 +1,28 @@ +! +! template: bgpd/templates/sentinels/instance.conf.j2 +! + neighbor BGPSentinel peer-group + neighbor BGPSentinel remote-as 555 + neighbor BGPSentinel update-source 1.1.1.1 + bgp listen range 10.10.20.0/24 peer-group BGPSentinel + bgp listen range 20.20.20.0/24 peer-group BGPSentinel +! + address-family ipv4 + neighbor BGPSentinel activate + neighbor BGPSentinel addpath-tx-all-paths + neighbor BGPSentinel soft-reconfiguration inbound + neighbor BGPSentinel route-map FROM_BGP_SENTINEL in + neighbor BGPSentinel route-map TO_BGP_SENTINEL out + neighbor BGPSentinel maximum-prefix 200 + exit-address-family + address-family ipv6 + neighbor BGPSentinel activate + neighbor BGPSentinel addpath-tx-all-paths + neighbor BGPSentinel soft-reconfiguration inbound + neighbor BGPSentinel route-map FROM_BGP_SENTINEL in + neighbor BGPSentinel route-map TO_BGP_SENTINEL out + neighbor BGPSentinel maximum-prefix 200 + exit-address-family +! +! end of template: bgpd/templates/sentinels/instance.conf.j2 +! diff --git a/src/sonic-bgpcfgd/tests/data/sentinels/instance.conf/result_all_v6.conf b/src/sonic-bgpcfgd/tests/data/sentinels/instance.conf/result_all_v6.conf new file mode 100644 index 000000000000..8cb2836f7aac --- /dev/null +++ b/src/sonic-bgpcfgd/tests/data/sentinels/instance.conf/result_all_v6.conf @@ -0,0 +1,28 @@ +! +! template: bgpd/templates/sentinels/instance.conf.j2 +! + neighbor BGPSentinelV6 peer-group + neighbor BGPSentinelV6 remote-as 555 + neighbor BGPSentinelV6 update-source fc00:1::32 + bgp listen range 2603:10a0:321:82f9::/64 peer-group BGPSentinelV6 + bgp listen range 2603:10a1:30a:8000::/59 peer-group BGPSentinelV6 +! + address-family ipv4 + neighbor BGPSentinelV6 activate + neighbor BGPSentinelV6 addpath-tx-all-paths + neighbor BGPSentinelV6 soft-reconfiguration inbound + neighbor BGPSentinelV6 route-map FROM_BGP_SENTINEL in + neighbor BGPSentinelV6 route-map TO_BGP_SENTINEL out + neighbor BGPSentinelV6 maximum-prefix 200 + exit-address-family + address-family ipv6 + neighbor BGPSentinelV6 activate + neighbor BGPSentinelV6 addpath-tx-all-paths + neighbor BGPSentinelV6 soft-reconfiguration inbound + neighbor BGPSentinelV6 route-map FROM_BGP_SENTINEL in + neighbor BGPSentinelV6 route-map TO_BGP_SENTINEL out + neighbor BGPSentinelV6 maximum-prefix 200 + exit-address-family +! +! end of template: bgpd/templates/sentinels/instance.conf.j2 +! diff --git a/src/sonic-bgpcfgd/tests/data/sentinels/peer-group.conf/param_all.json b/src/sonic-bgpcfgd/tests/data/sentinels/peer-group.conf/param_all.json new file mode 100644 index 000000000000..0967ef424bce --- /dev/null +++ b/src/sonic-bgpcfgd/tests/data/sentinels/peer-group.conf/param_all.json @@ -0,0 +1 @@ +{} diff --git a/src/sonic-bgpcfgd/tests/data/sentinels/peer-group.conf/result_all.conf b/src/sonic-bgpcfgd/tests/data/sentinels/peer-group.conf/result_all.conf new file mode 100644 index 000000000000..86d5c0297227 --- /dev/null +++ b/src/sonic-bgpcfgd/tests/data/sentinels/peer-group.conf/result_all.conf @@ -0,0 +1,7 @@ +! +! template: bgpd/templates/BGP_SPEAKER/peer-group.conf.j2 +! +! nothing is here +! +! end of template: bgpd/templates/BGP_SPEAKER/peer-group.conf.j2 +! diff --git a/src/sonic-bgpcfgd/tests/data/sentinels/policies.conf/param_all.json b/src/sonic-bgpcfgd/tests/data/sentinels/policies.conf/param_all.json new file mode 100644 index 000000000000..4270a2ab6b59 --- /dev/null +++ b/src/sonic-bgpcfgd/tests/data/sentinels/policies.conf/param_all.json @@ -0,0 +1,7 @@ +{ + "constants": { + "bgp": { + "sentinel_community": "12345:12346" + } + } +} diff --git a/src/sonic-bgpcfgd/tests/data/sentinels/policies.conf/param_base.json b/src/sonic-bgpcfgd/tests/data/sentinels/policies.conf/param_base.json new file mode 100644 index 000000000000..d6eb89f96850 --- /dev/null +++ b/src/sonic-bgpcfgd/tests/data/sentinels/policies.conf/param_base.json @@ -0,0 +1,6 @@ +{ + "constants": { + "bgp": { + } + } +} diff --git a/src/sonic-bgpcfgd/tests/data/sentinels/policies.conf/result_all.conf b/src/sonic-bgpcfgd/tests/data/sentinels/policies.conf/result_all.conf new file mode 100644 index 000000000000..b64e3ceb0dcc --- /dev/null +++ b/src/sonic-bgpcfgd/tests/data/sentinels/policies.conf/result_all.conf @@ -0,0 +1,14 @@ +! +! template: bgpd/templates/sentinels/policies.conf.j2 +! +bgp community-list standard sentinel_community permit 12345:12346 +! +route-map FROM_BGP_SENTINEL permit 100 + match community sentinel_community +! +route-map FROM_BGP_SENTINEL deny 200 +! +route-map TO_BGP_SENTINEL permit 100 +! +! end of template: bgpd/templates/sentinels/policies.conf.j2 +! diff --git a/src/sonic-bgpcfgd/tests/data/sentinels/policies.conf/result_base.conf b/src/sonic-bgpcfgd/tests/data/sentinels/policies.conf/result_base.conf new file mode 100644 index 000000000000..2ca5f064d5d3 --- /dev/null +++ b/src/sonic-bgpcfgd/tests/data/sentinels/policies.conf/result_base.conf @@ -0,0 +1,10 @@ +! +! template: bgpd/templates/sentinels/policies.conf.j2 +! +! +route-map FROM_BGP_SENTINEL deny 200 +! +route-map TO_BGP_SENTINEL permit 100 +! +! end of template: bgpd/templates/sentinels/policies.conf.j2 +! diff --git a/src/sonic-bgpcfgd/tests/data/sonic-cfggen/bgpd.main.conf.j2/packet_chassis.conf b/src/sonic-bgpcfgd/tests/data/sonic-cfggen/bgpd.main.conf.j2/packet_chassis.conf index 0f7f227e0e2c..6b2e1f257948 100644 --- a/src/sonic-bgpcfgd/tests/data/sonic-cfggen/bgpd.main.conf.j2/packet_chassis.conf +++ b/src/sonic-bgpcfgd/tests/data/sonic-cfggen/bgpd.main.conf.j2/packet_chassis.conf @@ -47,6 +47,7 @@ router bgp 55555 ! address-family ipv6 network fc00::1/64 + network fc00::1/128 route-map HIDE_INTERNAL exit-address-family ! network 10.10.10.1/24 diff --git a/src/sonic-bgpcfgd/tests/data/sonic-cfggen/bgpd.main.conf.j2/voq_chassis.conf b/src/sonic-bgpcfgd/tests/data/sonic-cfggen/bgpd.main.conf.j2/voq_chassis.conf index ef28d67c1c9d..efd45eda1ea9 100644 --- a/src/sonic-bgpcfgd/tests/data/sonic-cfggen/bgpd.main.conf.j2/voq_chassis.conf +++ b/src/sonic-bgpcfgd/tests/data/sonic-cfggen/bgpd.main.conf.j2/voq_chassis.conf @@ -48,6 +48,7 @@ router bgp 55555 ! address-family ipv6 network fc00::1/64 + network fc00::1/128 route-map HIDE_INTERNAL exit-address-family address-family ipv6 network fc00::2/128 route-map HIDE_INTERNAL diff --git a/src/sonic-bgpcfgd/tests/test_templates.py b/src/sonic-bgpcfgd/tests/test_templates.py index 23ada1aaf3f6..79774e7e57dc 100644 --- a/src/sonic-bgpcfgd/tests/test_templates.py +++ b/src/sonic-bgpcfgd/tests/test_templates.py @@ -152,3 +152,15 @@ def test_voq_chassis_pg(): def test_voq_chassis_instance(): test_data = load_tests("voq_chassis", "instance.conf") run_tests("voq_chassis_instance", *test_data) + +def test_sentinel_policies(): + test_data = load_tests("sentinels", "policies.conf") + run_tests("sentinel_policies", *test_data) + +def test_sentinel_pg(): + test_data = load_tests("sentinels", "peer-group.conf") + run_tests("sentinel_pg", *test_data) + +def test_sentinel_instance(): + test_data = load_tests("sentinels", "instance.conf") + run_tests("sentinel_instance", *test_data) diff --git a/src/sonic-config-engine/minigraph.py b/src/sonic-config-engine/minigraph.py index e0a8b3bd79cb..276e9e2d177c 100644 --- a/src/sonic-config-engine/minigraph.py +++ b/src/sonic-config-engine/minigraph.py @@ -5,6 +5,7 @@ import os import sys import json +import jinja2 import subprocess from collections import defaultdict @@ -887,6 +888,7 @@ def parse_cpg(cpg, hname, local_devices=[]): bgp_voq_chassis_sessions = {} myasn = None bgp_peers_with_range = {} + bgp_sentinel_sessions = {} for child in cpg: tag = child.tag if tag == str(QName(ns, "PeeringSessions")): @@ -956,14 +958,22 @@ def parse_cpg(cpg, hname, local_devices=[]): name = bgpPeer.find(str(QName(ns1, "Name"))).text ip_range = bgpPeer.find(str(QName(ns1, "PeersRange"))).text ip_range_group = ip_range.split(';') if ip_range and ip_range != "" else [] - bgp_peers_with_range[name] = { - 'name': name, - 'ip_range': ip_range_group - } - if bgpPeer.find(str(QName(ns, "Address"))) is not None: - bgp_peers_with_range[name]['src_address'] = bgpPeer.find(str(QName(ns, "Address"))).text - if bgpPeer.find(str(QName(ns1, "PeerAsn"))) is not None: - bgp_peers_with_range[name]['peer_asn'] = bgpPeer.find(str(QName(ns1, "PeerAsn"))).text + if name == "BGPSentinel" or name == "BGPSentinelV6": + bgp_sentinel_sessions[name] = { + 'name': name, + 'ip_range': ip_range_group + } + if bgpPeer.find(str(QName(ns, "Address"))) is not None: + bgp_sentinel_sessions[name]['src_address'] = bgpPeer.find(str(QName(ns, "Address"))).text + else: + bgp_peers_with_range[name] = { + 'name': name, + 'ip_range': ip_range_group + } + if bgpPeer.find(str(QName(ns, "Address"))) is not None: + bgp_peers_with_range[name]['src_address'] = bgpPeer.find(str(QName(ns, "Address"))).text + if bgpPeer.find(str(QName(ns1, "PeerAsn"))) is not None: + bgp_peers_with_range[name]['peer_asn'] = bgpPeer.find(str(QName(ns1, "PeerAsn"))).text else: for peer in bgp_sessions: bgp_session = bgp_sessions[peer] @@ -985,7 +995,7 @@ def filter_bad_asn(table): bgp_internal_sessions = filter_bad_asn(bgp_internal_sessions) bgp_voq_chassis_sessions = filter_bad_asn(bgp_voq_chassis_sessions) - return bgp_sessions, bgp_internal_sessions, bgp_voq_chassis_sessions, myasn, bgp_peers_with_range, bgp_monitors + return bgp_sessions, bgp_internal_sessions, bgp_voq_chassis_sessions, myasn, bgp_peers_with_range, bgp_monitors, bgp_sentinel_sessions def parse_meta(meta, hname): @@ -1537,7 +1547,7 @@ def parse_xml(filename, platform=None, port_config_file=None, asic_name=None, hw if child.tag == str(QName(ns, "DpgDec")): (intfs, lo_intfs, mvrf, mgmt_intf, voq_inband_intfs, vlans, vlan_members, dhcp_relay_table, pcs, pc_members, acls, acl_table_types, vni, tunnel_intfs, dpg_ecmp_content, static_routes, tunnel_intfs_qos_remap_config) = parse_dpg(child, hostname) elif child.tag == str(QName(ns, "CpgDec")): - (bgp_sessions, bgp_internal_sessions, bgp_voq_chassis_sessions, bgp_asn, bgp_peers_with_range, bgp_monitors) = parse_cpg(child, hostname) + (bgp_sessions, bgp_internal_sessions, bgp_voq_chassis_sessions, bgp_asn, bgp_peers_with_range, bgp_monitors, bgp_sentinel_sessions) = parse_cpg(child, hostname) elif child.tag == str(QName(ns, "PngDec")): (neighbors, devices, console_dev, console_port, mgmt_dev, mgmt_port, port_speed_png, console_ports, mux_cable_ports, png_ecmp_content) = parse_png(child, hostname, dpg_ecmp_content) elif child.tag == str(QName(ns, "UngDec")): @@ -1553,7 +1563,7 @@ def parse_xml(filename, platform=None, port_config_file=None, asic_name=None, hw (intfs, lo_intfs, mvrf, mgmt_intf, voq_inband_intfs, vlans, vlan_members, dhcp_relay_table, pcs, pc_members, acls, acl_table_types, vni, tunnel_intfs, dpg_ecmp_content, static_routes, tunnel_intfs_qos_remap_config) = parse_dpg(child, asic_name) host_lo_intfs = parse_host_loopback(child, hostname) elif child.tag == str(QName(ns, "CpgDec")): - (bgp_sessions, bgp_internal_sessions, bgp_voq_chassis_sessions, bgp_asn, bgp_peers_with_range, bgp_monitors) = parse_cpg(child, asic_name, local_devices) + (bgp_sessions, bgp_internal_sessions, bgp_voq_chassis_sessions, bgp_asn, bgp_peers_with_range, bgp_monitors, bgp_sentinel_sessions) = parse_cpg(child, asic_name, local_devices) elif child.tag == str(QName(ns, "PngDec")): (neighbors, devices, port_speed_png) = parse_asic_png(child, asic_name, hostname) elif child.tag == str(QName(ns, "MetadataDeclaration")): @@ -1670,6 +1680,7 @@ def parse_xml(filename, platform=None, port_config_file=None, asic_name=None, hw results['BGP_PEER_RANGE'] = bgp_peers_with_range results['BGP_INTERNAL_NEIGHBOR'] = bgp_internal_sessions results['BGP_VOQ_CHASSIS_NEIGHBOR'] = bgp_voq_chassis_sessions + results['BGP_SENTINELS'] = bgp_sentinel_sessions if mgmt_routes: # TODO: differentiate v4 and v6 next(iter(mgmt_intf.values()))['forced_mgmt_routes'] = mgmt_routes @@ -1767,6 +1778,9 @@ def parse_xml(filename, platform=None, port_config_file=None, asic_name=None, hw port_default_speed = port_speeds_default.get(port_name, None) port_png_speed = port_speed_png[port_name] + # set Port Speed before lane update + ports.setdefault(port_name, {})['speed'] = port_png_speed + # when the port speed is changes from 400g to 100g/40g # update the port lanes, use the first 4 lanes of the 400G port to support 100G/40G port if port_default_speed == '400000' and (port_png_speed == '100000' or port_png_speed == '40000'): @@ -1777,7 +1791,6 @@ def parse_xml(filename, platform=None, port_config_file=None, asic_name=None, hw updated_lanes = ",".join(port_lanes[:4]) ports[port_name]['lanes'] = updated_lanes - ports.setdefault(port_name, {})['speed'] = port_speed_png[port_name] for port_name, port in list(ports.items()): # get port alias from port_config.ini @@ -1962,6 +1975,7 @@ def parse_xml(filename, platform=None, port_config_file=None, asic_name=None, hw if is_storage_device and 'BackEnd' in current_device['type']: results['BGP_MONITORS'] = {} results['BGP_PEER_RANGE'] = {} + results['BGP_SENTINELS'] = {} results['VLAN'] = vlans results['VLAN_MEMBER'] = vlan_members @@ -1999,6 +2013,27 @@ def parse_xml(filename, platform=None, port_config_file=None, asic_name=None, hw results['DHCP_SERVER'] = dict((item, {}) for item in dhcp_servers) results['DHCP_RELAY'] = dhcp_relay_table results['NTP_SERVER'] = dict((item, {}) for item in ntp_servers) + # Set default DNS nameserver from dns.j2 + results['DNS_NAMESERVER'] = {} + if os.environ.get("CFGGEN_UNIT_TESTING", "0") == "2": + dns_conf = os.path.join(os.path.dirname(__file__), "tests/", "dns.j2") + else: + dns_conf = "/usr/share/sonic/templates/dns.j2" + if os.path.isfile(dns_conf): + text = "" + with open(dns_conf) as template_file: + # Semgrep does not allow to use jinja2 directly, but we do need jinja2 for SONiC + environment = jinja2.Environment(trim_blocks=True) # nosemgrep + dns_template = environment.from_string(template_file.read()) + text = dns_template.render(results) + try: + dns_res = json.loads(text) + except ValueError as e: + sys.exit("Error: fail to load dns configuration, %s" % str(e)) + else: + dns_nameservers = dns_res.get('DNS_NAMESERVER', {}) + for k in dns_nameservers.keys(): + results['DNS_NAMESERVER'][str(k)] = {} results['TACPLUS_SERVER'] = dict((item, {'priority': '1', 'tcp_port': '49'}) for item in tacacs_servers) if len(acl_table_types) > 0: results['ACL_TABLE_TYPE'] = acl_table_types diff --git a/src/sonic-config-engine/tests/data/j2_template/config.bcm.j2 b/src/sonic-config-engine/tests/data/j2_template/config.bcm.j2 index 61aeb0eff901..8a10ddb91936 100644 --- a/src/sonic-config-engine/tests/data/j2_template/config.bcm.j2 +++ b/src/sonic-config-engine/tests/data/j2_template/config.bcm.j2 @@ -14,8 +14,7 @@ {%- set switch_subtype = DEVICE_METADATA['localhost']['subtype'] -%} {%- if 'dualtor' in switch_subtype.lower() %} {%- set IPinIP_sock = -'sai_tunnel_support=1 -sai_tunnel_underlay_route_mode=1 +'sai_tunnel_underlay_route_mode=1 host_as_route_disable=1 l3_ecmp_levels=2' -%} {%- set map_prio = 'sai_remap_prio_on_tnl_egress=1' -%} @@ -33,5 +32,6 @@ sai_pfc_dlr_init_capability=1' -%} l3_alpm_hit_skip=1 {{ map_prio }} {{ mmu_sock }} +sai_tunnel_support=1 {{ IPinIP_sock }} {{ pfcwd_sock }} diff --git a/src/sonic-config-engine/tests/dns.j2 b/src/sonic-config-engine/tests/dns.j2 new file mode 100644 index 000000000000..3ee2ab038af6 --- /dev/null +++ b/src/sonic-config-engine/tests/dns.j2 @@ -0,0 +1,9 @@ +{ + "DNS_NAMESERVER": { +{% if DEVICE_METADATA.localhost.cloudtype == "Public" %} + "6.6.6.6": {} +{% else %} + "8.8.8.8": {} +{% endif %} + } +} diff --git a/src/sonic-config-engine/tests/sample-cisco-8111-100-minigraph.xml b/src/sonic-config-engine/tests/sample-cisco-8111-100-minigraph.xml new file mode 100755 index 000000000000..bf51944cc6c6 --- /dev/null +++ b/src/sonic-config-engine/tests/sample-cisco-8111-100-minigraph.xml @@ -0,0 +1,2389 @@ + + + + + + false + Device-8111-01 + 10.0.0.32 + ARISTA01T0 + 10.0.0.33 + 1 + 10 + 3 + + + Device-8111-01 + FC00::41 + ARISTA01T0 + FC00::42 + 1 + 10 + 3 + + + false + Device-8111-01 + 10.0.0.0 + ARISTA01T2 + 10.0.0.1 + 1 + 10 + 3 + + + Device-8111-01 + FC00::1 + ARISTA01T2 + FC00::2 + 1 + 10 + 3 + + + false + Device-8111-01 + 10.0.0.34 + ARISTA02T0 + 10.0.0.35 + 1 + 10 + 3 + + + Device-8111-01 + FC00::45 + ARISTA02T0 + FC00::46 + 1 + 10 + 3 + + + false + Device-8111-01 + 10.0.0.36 + ARISTA03T0 + 10.0.0.37 + 1 + 10 + 3 + + + Device-8111-01 + FC00::49 + ARISTA03T0 + FC00::4A + 1 + 10 + 3 + + + false + Device-8111-01 + 10.0.0.4 + ARISTA03T2 + 10.0.0.5 + 1 + 10 + 3 + + + Device-8111-01 + FC00::5 + ARISTA03T2 + FC00::6 + 1 + 10 + 3 + + + false + Device-8111-01 + 10.0.0.38 + ARISTA04T0 + 10.0.0.39 + 1 + 10 + 3 + + + Device-8111-01 + FC00::4D + ARISTA04T0 + FC00::4E + 1 + 10 + 3 + + + false + Device-8111-01 + 10.0.0.40 + ARISTA05T0 + 10.0.0.41 + 1 + 10 + 3 + + + Device-8111-01 + FC00::51 + ARISTA05T0 + FC00::52 + 1 + 10 + 3 + + + false + Device-8111-01 + 10.0.0.8 + ARISTA05T2 + 10.0.0.9 + 1 + 10 + 3 + + + Device-8111-01 + FC00::9 + ARISTA05T2 + FC00::A + 1 + 10 + 3 + + + false + Device-8111-01 + 10.0.0.42 + ARISTA06T0 + 10.0.0.43 + 1 + 10 + 3 + + + Device-8111-01 + FC00::55 + ARISTA06T0 + FC00::56 + 1 + 10 + 3 + + + false + Device-8111-01 + 10.0.0.44 + ARISTA07T0 + 10.0.0.45 + 1 + 10 + 3 + + + Device-8111-01 + FC00::59 + ARISTA07T0 + FC00::5A + 1 + 10 + 3 + + + false + Device-8111-01 + 10.0.0.12 + ARISTA07T2 + 10.0.0.13 + 1 + 10 + 3 + + + Device-8111-01 + FC00::D + ARISTA07T2 + FC00::E + 1 + 10 + 3 + + + false + Device-8111-01 + 10.0.0.46 + ARISTA08T0 + 10.0.0.47 + 1 + 10 + 3 + + + Device-8111-01 + FC00::5D + ARISTA08T0 + FC00::5E + 1 + 10 + 3 + + + false + Device-8111-01 + 10.0.0.48 + ARISTA09T0 + 10.0.0.49 + 1 + 10 + 3 + + + Device-8111-01 + FC00::61 + ARISTA09T0 + FC00::62 + 1 + 10 + 3 + + + false + Device-8111-01 + 10.0.0.50 + ARISTA10T0 + 10.0.0.51 + 1 + 10 + 3 + + + Device-8111-01 + FC00::65 + ARISTA10T0 + FC00::66 + 1 + 10 + 3 + + + false + Device-8111-01 + 10.0.0.52 + ARISTA11T0 + 10.0.0.53 + 1 + 10 + 3 + + + Device-8111-01 + FC00::69 + ARISTA11T0 + FC00::6A + 1 + 10 + 3 + + + false + Device-8111-01 + 10.0.0.54 + ARISTA12T0 + 10.0.0.55 + 1 + 10 + 3 + + + Device-8111-01 + FC00::6D + ARISTA12T0 + FC00::6E + 1 + 10 + 3 + + + false + Device-8111-01 + 10.0.0.56 + ARISTA13T0 + 10.0.0.57 + 1 + 10 + 3 + + + Device-8111-01 + FC00::71 + ARISTA13T0 + FC00::72 + 1 + 10 + 3 + + + false + Device-8111-01 + 10.0.0.58 + ARISTA14T0 + 10.0.0.59 + 1 + 10 + 3 + + + Device-8111-01 + FC00::75 + ARISTA14T0 + FC00::76 + 1 + 10 + 3 + + + false + Device-8111-01 + 10.0.0.60 + ARISTA15T0 + 10.0.0.61 + 1 + 10 + 3 + + + Device-8111-01 + FC00::79 + ARISTA15T0 + FC00::7A + 1 + 10 + 3 + + + false + Device-8111-01 + 10.0.0.62 + ARISTA16T0 + 10.0.0.63 + 1 + 10 + 3 + + + Device-8111-01 + FC00::7D + ARISTA16T0 + FC00::7E + 1 + 10 + 3 + + + false + Device-8111-01 + 10.0.0.64 + ARISTA17T0 + 10.0.0.65 + 1 + 10 + 3 + + + Device-8111-01 + FC00::81 + ARISTA17T0 + FC00::82 + 1 + 10 + 3 + + + false + Device-8111-01 + 10.0.0.66 + ARISTA18T0 + 10.0.0.67 + 1 + 10 + 3 + + + Device-8111-01 + FC00::85 + ARISTA18T0 + FC00::86 + 1 + 10 + 3 + + + false + Device-8111-01 + 10.0.0.68 + ARISTA19T0 + 10.0.0.69 + 1 + 10 + 3 + + + Device-8111-01 + FC00::89 + ARISTA19T0 + FC00::8A + 1 + 10 + 3 + + + false + Device-8111-01 + 10.0.0.70 + ARISTA20T0 + 10.0.0.71 + 1 + 10 + 3 + + + Device-8111-01 + FC00::8D + ARISTA20T0 + FC00::8E + 1 + 10 + 3 + + + + + 65100 + Device-8111-01 + + +
10.0.0.33
+ + + + + +
10.0.0.1
+ + + + + +
10.0.0.35
+ + + + + +
10.0.0.37
+ + + + + +
10.0.0.5
+ + + + + +
10.0.0.39
+ + + + + +
10.0.0.41
+ + + + + +
10.0.0.9
+ + + + + +
10.0.0.43
+ + + + + +
10.0.0.45
+ + + + + +
10.0.0.13
+ + + + + +
10.0.0.47
+ + + + + +
10.0.0.49
+ + + + + +
10.0.0.51
+ + + + + +
10.0.0.53
+ + + + + +
10.0.0.55
+ + + + + +
10.0.0.57
+ + + + + +
10.0.0.59
+ + + + + +
10.0.0.61
+ + + + + +
10.0.0.63
+ + + + + +
10.0.0.65
+ + + + + +
10.0.0.67
+ + + + + +
10.0.0.69
+ + + + + +
10.0.0.71
+ + + + + + + + + 64001 + ARISTA01T0 + + + + 65200 + ARISTA01T2 + + + + 64002 + ARISTA02T0 + + + + 64003 + ARISTA03T0 + + + + 65200 + ARISTA03T2 + + + + 64004 + ARISTA04T0 + + + + 64005 + ARISTA05T0 + + + + 65200 + ARISTA05T2 + + + + 64006 + ARISTA06T0 + + + + 64007 + ARISTA07T0 + + + + 65200 + ARISTA07T2 + + + + 64008 + ARISTA08T0 + + + + 64009 + ARISTA09T0 + + + + 64010 + ARISTA10T0 + + + + 64011 + ARISTA11T0 + + + + 64012 + ARISTA12T0 + + + + 64013 + ARISTA13T0 + + + + 64014 + ARISTA14T0 + + + + 64015 + ARISTA15T0 + + + + 64016 + ARISTA16T0 + + + + 64017 + ARISTA17T0 + + + + 64018 + ARISTA18T0 + + + + 64019 + ARISTA19T0 + + + + 64020 + ARISTA20T0 + + + + + + + + + + HostIP + Loopback0 + + 10.1.0.32/32 + + 10.1.0.32/32 + + + HostIP1 + Loopback0 + + FC00:1::32/128 + + FC00:1::32/128 + + + + + HostIP + eth0 + + 1.1.1.1/23 + + 1.1.1.1/23 + + + V6HostIP + eth0 + + FC00:2::32/64 + + FC00:2::32/64 + + + + + + + Device-8111-01 + + + PortChannel101 + etp0a + + + + PortChannel102 + etp12;etp13 + + + + PortChannel103 + etp0b + + + + PortChannel104 + etp2a + + + + PortChannel105 + etp14;etp15 + + + + PortChannel106 + etp2b + + + + PortChannel107 + etp8a + + + + PortChannel108 + etp16;etp17 + + + + PortChannel109 + etp8b + + + + PortChannel1010 + etp10a + + + + PortChannel1011 + etp18;etp19 + + + + PortChannel1012 + etp10b + + + + PortChannel1013 + etp21a + + + + PortChannel1014 + etp22b + + + + PortChannel1015 + etp25a + + + + PortChannel1016 + etp25b + + + + PortChannel1017 + etp26b + + + + PortChannel1018 + etp27a + + + + PortChannel1019 + etp27b + + + + PortChannel1020 + etp29a + + + + PortChannel1021 + etp30a + + + + PortChannel1022 + etp30b + + + + PortChannel1023 + etp31a + + + + PortChannel1024 + etp31b + + + + + + + + + PortChannel101 + 10.0.0.32/31 + + + + PortChannel101 + FC00::41/126 + + + + PortChannel102 + 10.0.0.0/31 + + + + PortChannel102 + FC00::1/126 + + + + PortChannel103 + 10.0.0.34/31 + + + + PortChannel103 + FC00::45/126 + + + + PortChannel104 + 10.0.0.36/31 + + + + PortChannel104 + FC00::49/126 + + + + PortChannel105 + 10.0.0.4/31 + + + + PortChannel105 + FC00::5/126 + + + + PortChannel106 + 10.0.0.38/31 + + + + PortChannel106 + FC00::4D/126 + + + + PortChannel107 + 10.0.0.40/31 + + + + PortChannel107 + FC00::51/126 + + + + PortChannel108 + 10.0.0.8/31 + + + + PortChannel108 + FC00::9/126 + + + + PortChannel109 + 10.0.0.42/31 + + + + PortChannel109 + FC00::55/126 + + + + PortChannel1010 + 10.0.0.44/31 + + + + PortChannel1010 + FC00::59/126 + + + + PortChannel1011 + 10.0.0.12/31 + + + + PortChannel1011 + FC00::D/126 + + + + PortChannel1012 + 10.0.0.46/31 + + + + PortChannel1012 + FC00::5D/126 + + + + PortChannel1013 + 10.0.0.48/31 + + + + PortChannel1013 + FC00::61/126 + + + + PortChannel1014 + 10.0.0.50/31 + + + + PortChannel1014 + FC00::65/126 + + + + PortChannel1015 + 10.0.0.52/31 + + + + PortChannel1015 + FC00::69/126 + + + + PortChannel1016 + 10.0.0.54/31 + + + + PortChannel1016 + FC00::6D/126 + + + + PortChannel1017 + 10.0.0.56/31 + + + + PortChannel1017 + FC00::71/126 + + + + PortChannel1018 + 10.0.0.58/31 + + + + PortChannel1018 + FC00::75/126 + + + + PortChannel1019 + 10.0.0.60/31 + + + + PortChannel1019 + FC00::79/126 + + + + PortChannel1020 + 10.0.0.62/31 + + + + PortChannel1020 + FC00::7D/126 + + + + PortChannel1021 + 10.0.0.64/31 + + + + PortChannel1021 + FC00::81/126 + + + + PortChannel1022 + 10.0.0.66/31 + + + + PortChannel1022 + FC00::85/126 + + + + PortChannel1023 + 10.0.0.68/31 + + + + PortChannel1023 + FC00::89/126 + + + + PortChannel1024 + 10.0.0.70/31 + + + + PortChannel1024 + FC00::8D/126 + + + + + + NTP_ACL + NTP + NTP + + + SNMP_ACL + SNMP + SNMP + + + VTY_LINE + ssh-only + SSH + + + ERSPAN + Everflow + Everflow + + + ERSPANV6 + EverflowV6 + EverflowV6 + + + PortChannel101;PortChannel102;PortChannel103;PortChannel104;PortChannel105;PortChannel106;PortChannel107;PortChannel108;PortChannel109;PortChannel1010;PortChannel1011;PortChannel1012;PortChannel1013;PortChannel1014;PortChannel1015;PortChannel1016;PortChannel1017;PortChannel1018;PortChannel1019;PortChannel1020;PortChannel1021;PortChannel1022;PortChannel1023;PortChannel1024 + DataAcl + DataPlane + + + + + + + + + + DeviceInterfaceLink + ARISTA01T0 + Ethernet1 + Device-8111-01 + etp0a + 100000 + + + DeviceInterfaceLink + ARISTA01T2 + Ethernet1 + Device-8111-01 + etp12 + 100000 + + + DeviceInterfaceLink + ARISTA01T2 + Ethernet2 + Device-8111-01 + etp13 + 100000 + + + DeviceInterfaceLink + ARISTA02T0 + Ethernet1 + Device-8111-01 + etp0b + 100000 + + + DeviceInterfaceLink + ARISTA03T0 + Ethernet1 + Device-8111-01 + etp2a + 100000 + + + DeviceInterfaceLink + ARISTA03T2 + Ethernet1 + Device-8111-01 + etp14 + 100000 + + + DeviceInterfaceLink + ARISTA03T2 + Ethernet2 + Device-8111-01 + etp15 + 100000 + + + DeviceInterfaceLink + ARISTA04T0 + Ethernet1 + Device-8111-01 + etp2b + 100000 + + + DeviceInterfaceLink + ARISTA05T0 + Ethernet1 + Device-8111-01 + etp8a + 100000 + + + DeviceInterfaceLink + ARISTA05T2 + Ethernet1 + Device-8111-01 + etp16 + 100000 + + + DeviceInterfaceLink + ARISTA05T2 + Ethernet2 + Device-8111-01 + etp17 + 100000 + + + DeviceInterfaceLink + ARISTA06T0 + Ethernet1 + Device-8111-01 + etp8b + 100000 + + + DeviceInterfaceLink + ARISTA07T0 + Ethernet1 + Device-8111-01 + etp10a + 100000 + + + DeviceInterfaceLink + ARISTA07T2 + Ethernet1 + Device-8111-01 + etp18 + 100000 + + + DeviceInterfaceLink + ARISTA07T2 + Ethernet2 + Device-8111-01 + etp19 + 100000 + + + DeviceInterfaceLink + ARISTA08T0 + Ethernet1 + Device-8111-01 + etp10b + 100000 + + + DeviceInterfaceLink + ARISTA09T0 + Ethernet1 + Device-8111-01 + etp21a + 100000 + + + DeviceInterfaceLink + ARISTA10T0 + Ethernet1 + Device-8111-01 + etp22b + 100000 + + + DeviceInterfaceLink + ARISTA11T0 + Ethernet1 + Device-8111-01 + etp25a + 100000 + + + DeviceInterfaceLink + ARISTA12T0 + Ethernet1 + Device-8111-01 + etp25b + 100000 + + + DeviceInterfaceLink + ARISTA13T0 + Ethernet1 + Device-8111-01 + etp26b + 100000 + + + DeviceInterfaceLink + ARISTA14T0 + Ethernet1 + Device-8111-01 + etp27a + 100000 + + + DeviceInterfaceLink + ARISTA15T0 + Ethernet1 + Device-8111-01 + etp27b + 100000 + + + DeviceInterfaceLink + ARISTA16T0 + Ethernet1 + Device-8111-01 + etp29a + 100000 + + + DeviceInterfaceLink + ARISTA17T0 + Ethernet1 + Device-8111-01 + etp30a + 100000 + + + DeviceInterfaceLink + ARISTA18T0 + Ethernet1 + Device-8111-01 + etp30b + 100000 + + + DeviceInterfaceLink + ARISTA19T0 + Ethernet1 + Device-8111-01 + etp31a + 100000 + + + DeviceInterfaceLink + ARISTA20T0 + Ethernet1 + Device-8111-01 + etp31b + 100000 + + + + + Device-8111-01 + Cisco-8111-O64 + + 1.1.1.1 + + + + ARISTA16T0 + + 172.16.134.203 + + Arista-VM + + + ARISTA11T0 + + 172.16.134.198 + + Arista-VM + + + ARISTA10T0 + + 172.16.134.197 + + Arista-VM + + + ARISTA17T0 + + 172.16.134.204 + + Arista-VM + + + ARISTA09T0 + + 172.16.134.196 + + Arista-VM + + + ARISTA20T0 + + 172.16.134.207 + + Arista-VM + + + ARISTA08T0 + + 172.16.134.191 + + Arista-VM + + + ARISTA07T0 + + 172.16.134.190 + + Arista-VM + + + ARISTA07T2 + + 172.16.134.195 + + Arista-VM + + + ARISTA01T2 + + 172.16.134.192 + + Arista-VM + + + ARISTA01T0 + + 172.16.134.184 + + Arista-VM + + + ARISTA05T2 + + 172.16.134.194 + + Arista-VM + + + ARISTA05T0 + + 172.16.134.188 + + Arista-VM + + + ARISTA02T0 + + 172.16.134.185 + + Arista-VM + + + ARISTA03T0 + + 172.16.134.186 + + Arista-VM + + + ARISTA03T2 + + 172.16.134.193 + + Arista-VM + + + ARISTA04T0 + + 172.16.134.187 + + Arista-VM + + + ARISTA18T0 + + 172.16.134.205 + + Arista-VM + + + ARISTA15T0 + + 172.16.134.202 + + Arista-VM + + + ARISTA19T0 + + 172.16.134.206 + + Arista-VM + + + ARISTA14T0 + + 172.16.134.201 + + Arista-VM + + + ARISTA12T0 + + 172.16.134.199 + + Arista-VM + + + ARISTA13T0 + + 172.16.134.200 + + Arista-VM + + + ARISTA06T0 + + 172.16.134.189 + + Arista-VM + + + + + + true + + + DeviceInterface + + true + true + 1 + etp0a + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp0b + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp1a + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp1b + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp2a + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp2b + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp3a + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp3b + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp4a + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp4b + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp5a + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp5b + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp6a + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp6b + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp7a + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp7b + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp8a + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp8b + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp9a + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp9b + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp10a + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp10b + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp11a + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp11b + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp12 + + false + 0 + 0 + 400000 + + + DeviceInterface + + true + true + 1 + etp13 + + false + 0 + 0 + 400000 + + + DeviceInterface + + true + true + 1 + etp14 + + false + 0 + 0 + 400000 + + + DeviceInterface + + true + true + 1 + etp15 + + false + 0 + 0 + 400000 + + + DeviceInterface + + true + true + 1 + etp16 + + false + 0 + 0 + 400000 + + + DeviceInterface + + true + true + 1 + etp17 + + false + 0 + 0 + 400000 + + + DeviceInterface + + true + true + 1 + etp18 + + false + 0 + 0 + 400000 + + + DeviceInterface + + true + true + 1 + etp19 + + false + 0 + 0 + 400000 + + + DeviceInterface + + true + true + 1 + etp20a + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp20b + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp21a + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp21b + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp22a + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp22b + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp23a + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp23b + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp24a + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp24b + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp25a + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp25b + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp26a + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp26b + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp27a + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp27b + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp28a + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp28b + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp29a + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp29b + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp30a + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp30b + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp31a + + false + 0 + 0 + 100000 + + + DeviceInterface + + true + true + 1 + etp31b + + false + 0 + 0 + 100000 + + + true + 0 + Cisco-8111-O64 + + + + + + + Device-8111-01 + + + DeploymentId + + 1 + + + QosProfile + + Profile0 + + + DhcpResources + + 192.0.0.1;192.0.0.2;192.0.0.3;192.0.0.4;192.0.0.5;192.0.0.6;192.0.0.7;192.0.0.8;192.0.0.9;192.0.0.10;192.0.0.11;192.0.0.12;192.0.0.13;192.0.0.14;192.0.0.15;192.0.0.16;192.0.0.17;192.0.0.18;192.0.0.19;192.0.0.20;192.0.0.21;192.0.0.22;192.0.0.23;192.0.0.24;192.0.0.25;192.0.0.26;192.0.0.27;192.0.0.28;192.0.0.29;192.0.0.30;192.0.0.31;192.0.0.32;192.0.0.33;192.0.0.34;192.0.0.35;192.0.0.36;192.0.0.37;192.0.0.38;192.0.0.39;192.0.0.40;192.0.0.41;192.0.0.42;192.0.0.43;192.0.0.44;192.0.0.45;192.0.0.46;192.0.0.47;192.0.0.48 + + + NtpResources + + 10.20.8.129;10.20.8.130 + + + SnmpResources + + 10.3.145.98 + + + SyslogResources + + 10.64.246.95 + + + TacacsGroup + + Starlab + + + TacacsServer + + 10.3.145.14;10.3.145.15 + + + ForcedMgmtRoutes + + 10.3.145.98/31;10.3.145.8;100.127.20.16/28;10.3.149.170/31;40.122.216.24;13.91.48.226;10.64.246.0/23;10.3.146.0/23;10.64.5.5;10.201.148.32/28 + + + ErspanDestinationIpv4 + + 10.20.6.16 + + + + + + + Device-8111-01 + Cisco-8111-O64 + diff --git a/src/sonic-config-engine/tests/sample-cisco-8111-port-config.ini b/src/sonic-config-engine/tests/sample-cisco-8111-port-config.ini new file mode 100644 index 000000000000..02def0a7809c --- /dev/null +++ b/src/sonic-config-engine/tests/sample-cisco-8111-port-config.ini @@ -0,0 +1,57 @@ +# name lanes alias index speed +Ethernet0 2304,2305,2306,2307 etp0a 0 100000 +Ethernet4 2308,2309,2310,2311 etp0b 0 100000 +Ethernet8 2320,2321,2322,2323 etp1a 1 100000 +Ethernet12 2324,2325,2326,2327 etp1b 1 100000 +Ethernet16 2312,2313,2314,2315 etp2a 2 100000 +Ethernet20 2316,2317,2318,2319 etp2b 2 100000 +Ethernet24 2056,2057,2058,2059 etp3a 3 100000 +Ethernet28 2060,2061,2062,2063 etp3b 3 100000 +Ethernet32 1792,1793,1794,1795 etp4a 4 100000 +Ethernet36 1796,1797,1798,1799 etp4b 4 100000 +Ethernet40 2048,2049,2050,2051 etp5a 5 100000 +Ethernet44 2052,2053,2054,2055 etp5b 5 100000 +Ethernet48 2560,2561,2562,2563 etp6a 6 100000 +Ethernet52 2564,2565,2566,2567 etp6b 6 100000 +Ethernet56 2824,2825,2826,2827 etp7a 7 100000 +Ethernet60 2828,2829,2830,2831 etp7b 7 100000 +Ethernet64 2832,2833,2834,2835 etp8a 8 100000 +Ethernet68 2836,2837,2838,2839 etp8b 8 100000 +Ethernet72 2816,2817,2818,2819 etp9a 9 100000 +Ethernet76 2820,2821,2822,2823 etp9b 9 100000 +Ethernet80 2568,2569,2570,2571 etp10a 10 100000 +Ethernet84 2572,2573,2574,2575 etp10b 10 100000 +Ethernet88 2576,2577,2578,2579 etp11a 11 100000 +Ethernet92 2580,2581,2582,2583 etp11b 11 100000 +Ethernet96 1536,1537,1538,1539 etp12 12 400000 +Ethernet104 1800,1801,1802,1803 etp13 13 400000 +Ethernet112 1552,1553,1554,1555 etp14 14 400000 +Ethernet120 1544,1545,1546,1547 etp15 15 400000 +Ethernet128 1296,1297,1298,1299 etp16 16 400000 +Ethernet136 1288,1289,1290,1291 etp17 17 400000 +Ethernet144 1280,1281,1282,1283 etp18 18 400000 +Ethernet152 1032,1033,1034,1035 etp19 19 400000 +Ethernet160 264,265,266,267 etp20a 20 100000 +Ethernet164 268,269,270,271 etp20b 20 100000 +Ethernet168 272,273,274,275 etp21a 21 100000 +Ethernet172 276,277,278,279 etp21b 21 100000 +Ethernet176 16,17,18,19 etp22a 22 100000 +Ethernet180 20,21,22,23 etp22b 22 100000 +Ethernet184 0,1,2,3 etp23a 23 100000 +Ethernet188 4,5,6,7 etp23b 23 100000 +Ethernet192 256,257,258,259 etp24a 24 100000 +Ethernet196 260,261,262,263 etp24b 24 100000 +Ethernet200 8,9,10,11 etp25a 25 100000 +Ethernet204 12,13,14,15 etp25b 25 100000 +Ethernet208 1024,1025,1026,1027 etp26a 26 100000 +Ethernet212 1028,1029,1030,1031 etp26b 26 100000 +Ethernet216 768,769,770,771 etp27a 27 100000 +Ethernet220 772,773,774,775 etp27b 27 100000 +Ethernet224 524,525,526,527 etp28a 28 100000 +Ethernet228 520,521,522,523 etp28b 28 100000 +Ethernet232 776,777,778,779 etp29a 29 100000 +Ethernet236 780,781,782,783 etp29b 29 100000 +Ethernet240 516,517,518,519 etp30a 30 100000 +Ethernet244 512,513,514,515 etp30b 30 100000 +Ethernet248 528,529,530,531 etp31a 31 100000 +Ethernet252 532,533,534,535 etp31b 31 100000 diff --git a/src/sonic-config-engine/tests/sample_output/py2/qos-arista7800r3-48cq2-lc.json b/src/sonic-config-engine/tests/sample_output/py2/qos-arista7800r3-48cq2-lc.json index 7aecbdbd90e5..1296b4e2b8fc 100644 --- a/src/sonic-config-engine/tests/sample_output/py2/qos-arista7800r3-48cq2-lc.json +++ b/src/sonic-config-engine/tests/sample_output/py2/qos-arista7800r3-48cq2-lc.json @@ -496,1040 +496,3174 @@ } }, "QUEUE": { - "Ethernet0|3": { + "dut-lc5|Asic0|Ethernet52|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet4|3": { + "dut-lc5|Asic0|Ethernet56|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet8|3": { + "dut-lc3|Asic0|Ethernet72|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet12|3": { + "dut-lc3|Asic0|Ethernet76|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet16|3": { + "dut-lc4|Asic0|Ethernet84|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet20|3": { + "dut-lc4|Asic0|Ethernet80|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet24|3": { + "dut-lc4|Asic0|Ethernet88|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet28|3": { + "dut-lc3|Asic0|Ethernet4|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet32|3": { + "dut-lc4|Asic0|Ethernet56|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet36|3": { + "dut-lc3|Asic0|Ethernet0|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet40|3": { + "dut-lc3|Asic0|Ethernet8|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet44|3": { + "dut-lc3|Asic0|Ethernet112|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet48|3": { + "dut-lc4|Asic0|Ethernet52|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet52|3": { + "dut-lc4|Asic0|Ethernet152|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet56|3": { + "dut-lc5|Asic0|Ethernet44|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet60|3": { + "dut-lc4|Asic0|Ethernet12|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet64|3": { + "dut-lc3|Asic0|Ethernet68|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet68|3": { + "dut-lc4|Asic0|Ethernet16|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet72|3": { + "dut-lc3|Asic0|Ethernet64|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet76|3": { + "dut-lc3|Asic0|Ethernet124|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet80|3": { + "dut-lc3|Asic0|Ethernet60|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet84|3": { + "dut-lc3|Asic0|Ethernet116|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet88|3": { + "dut-lc3|Asic0|Ethernet120|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet92|3": { + "dut-lc4|Asic0|Ethernet104|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet96|3": { + "dut-lc5|Asic0|Ethernet152|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet100|3": { + "dut-lc4|Asic0|Ethernet188|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet104|3": { + "dut-lc5|Asic0|Ethernet156|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet108|3": { + "dut-lc4|Asic0|Ethernet148|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet112|3": { + "dut-lc4|Asic0|Ethernet140|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet116|3": { + "dut-lc4|Asic0|Ethernet64|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet120|3": { + "dut-lc3|Asic0|Ethernet92|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet124|3": { + "dut-lc4|Asic0|Ethernet60|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet128|3": { + "dut-lc3|Asic0|Ethernet96|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet132|3": { + "dut-lc3|Asic0|Ethernet144|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet136|3": { + "dut-lc4|Asic0|Ethernet68|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet140|3": { + "dut-lc4|Asic0|Ethernet40|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet144|3": { + "dut-lc4|Asic0|Ethernet72|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet148|3": { + "dut-lc5|Asic0|Ethernet128|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet152|3": { + "dut-lc5|Asic0|Ethernet124|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet156|3": { + "dut-lc4|Asic0|Ethernet92|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet164|3": { + "dut-lc5|Asic0|Ethernet120|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet176|3": { + "dut-lc4|Asic0|Ethernet96|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet180|3": { + "dut-lc4|Asic0|Ethernet172|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet184|3": { + "dut-lc5|Asic0|Ethernet32|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet188|3": { + "dut-lc4|Asic0|Ethernet176|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet0|4": { + "dut-lc5|Asic0|Ethernet36|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet4|4": { + "dut-lc4|Asic0|Ethernet32|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet8|4": { + "dut-lc3|Asic0|Ethernet12|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet12|4": { + "dut-lc3|Asic0|Ethernet16|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet16|4": { + "dut-lc4|Asic0|Ethernet76|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet20|4": { + "dut-lc3|Asic0|Ethernet80|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet24|4": { + "dut-lc3|Asic0|Ethernet140|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet28|4": { + "dut-lc3|Asic0|Ethernet84|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet32|4": { + "dut-lc3|Asic0|Ethernet88|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet36|4": { + "dut-lc3|Asic0|Ethernet148|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet40|4": { + "dut-lc4|Asic0|Ethernet100|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet44|4": { + "dut-lc4|Asic0|Ethernet36|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet48|4": { + "dut-lc4|Asic0|Ethernet112|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet52|4": { + "dut-lc5|Asic0|Ethernet180|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet56|4": { + "dut-lc4|Asic0|Ethernet144|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet60|4": { + "dut-lc5|Asic0|Ethernet184|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet64|4": { + "dut-lc5|Asic0|Ethernet136|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet68|4": { + "dut-lc5|Asic0|Ethernet104|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet72|4": { + "dut-lc5|Asic0|Ethernet132|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet76|4": { + "dut-lc4|Asic0|Ethernet164|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet80|4": { + "dut-lc5|Asic0|Ethernet188|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet84|4": { + "dut-lc4|Asic0|Ethernet160|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet88|4": { + "dut-lc5|Asic0|Ethernet24|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet92|4": { + "dut-lc5|Asic0|Ethernet28|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet96|4": { + "dut-lc4|Asic0|Ethernet168|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet100|4": { + "dut-lc3|Asic0|Ethernet156|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet104|4": { + "dut-lc3|Asic0|Ethernet152|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet108|4": { + "dut-lc3|Asic0|Ethernet132|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet112|4": { + "dut-lc4|Asic0|Ethernet48|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet116|4": { + "dut-lc4|Asic0|Ethernet180|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet120|4": { + "dut-lc4|Asic0|Ethernet44|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet124|4": { + "dut-lc5|Asic0|Ethernet100|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet128|4": { + "dut-lc3|Asic0|Ethernet136|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet132|4": { + "dut-lc4|Asic0|Ethernet116|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet136|4": { + "dut-lc5|Asic0|Ethernet96|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet140|4": { + "dut-lc5|Asic0|Ethernet108|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet144|4": { + "dut-lc5|Asic0|Ethernet92|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet148|4": { + "dut-lc5|Asic0|Ethernet16|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet152|4": { + "dut-lc5|Asic0|Ethernet12|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet156|4": { + "dut-lc3|Asic0|Ethernet36|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet164|4": { + "dut-lc3|Asic0|Ethernet32|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet176|4": { + "dut-lc5|Asic0|Ethernet48|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet180|4": { + "dut-lc5|Asic0|Ethernet160|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet184|4": { + "dut-lc3|Asic0|Ethernet168|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet188|4": { + "dut-lc5|Asic0|Ethernet164|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet0|0": { + "dut-lc5|Asic0|Ethernet168|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet160|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet164|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet80|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet116|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet156|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet84|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet112|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet88|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet108|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet20|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet24|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet28|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet28|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet20|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet76|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet24|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet72|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet172|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet184|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet8|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet4|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet176|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet0|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet172|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet40|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet136|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet132|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet128|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet56|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet20|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet52|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet108|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet68|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet100|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet176|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet64|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet104|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet60|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet180|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet144|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet184|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet140|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet188|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet148|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet128|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet4|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet44|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet0|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet40|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet120|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet124|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet8|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet48|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet52|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet56|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet72|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet76|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet84|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet80|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet88|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet4|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet56|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet0|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet8|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet112|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet52|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet152|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet44|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet12|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet68|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet16|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet64|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet124|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet60|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet116|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet120|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet104|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet152|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet188|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet156|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet148|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet140|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet64|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet92|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet60|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet96|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet144|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet68|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet40|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet72|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet128|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet124|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet92|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet120|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet96|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet172|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet32|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet176|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet36|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet32|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet12|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet16|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet76|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet80|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet140|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet84|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet88|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet148|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet100|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet36|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet112|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet180|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet144|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet184|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet136|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet104|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet132|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet164|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet188|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet160|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet24|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet28|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet168|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet156|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet152|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet132|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet48|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet180|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet44|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet100|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet136|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet116|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet96|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet108|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet92|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet16|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet12|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet36|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet32|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet48|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet160|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet168|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet164|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet168|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet160|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet164|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet80|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet116|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet156|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet84|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet112|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet88|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet108|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet20|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet24|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet28|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet28|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet20|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet76|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet24|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet72|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet172|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet184|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet8|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet4|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet176|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet0|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet172|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet40|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet136|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet132|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet128|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet56|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet20|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet52|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet108|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet68|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet100|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet176|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet64|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet104|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet60|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet180|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet144|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet184|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet140|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet188|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet148|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet128|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet4|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet44|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet0|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet40|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet120|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet124|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet8|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet48|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet52|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet56|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet72|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet76|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet84|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet80|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet88|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet4|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet56|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet0|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet8|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet112|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet52|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet152|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet44|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet12|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet68|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet16|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet64|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet124|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet60|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet116|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet120|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet104|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet152|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet188|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet156|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet148|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet140|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet64|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet92|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet60|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet96|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet144|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet68|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet40|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet72|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet128|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet124|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet92|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet120|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet96|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet172|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet32|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet176|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet36|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet32|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet12|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet16|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet76|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet80|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet140|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet84|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet88|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet148|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet100|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet36|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet112|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet180|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet144|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet184|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet136|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet104|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet132|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet164|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet188|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet160|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet24|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet28|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet168|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet156|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet152|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet132|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet48|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet180|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet44|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet100|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet136|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet116|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet96|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet108|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet92|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet16|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet12|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet36|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet32|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet48|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet160|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet168|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet164|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet168|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet160|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet164|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet80|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet116|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet156|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet84|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet112|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet88|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet108|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet20|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet24|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet28|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet28|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet20|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet76|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet24|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet72|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet172|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet184|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet8|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet4|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet176|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet0|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet172|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet40|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet136|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet132|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet128|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet56|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet20|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet52|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet108|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet68|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet100|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet176|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet64|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet104|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet60|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet180|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet144|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet184|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet140|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet188|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet148|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet128|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet4|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet44|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet0|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet40|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet120|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet124|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet8|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet48|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet52|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet56|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet72|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet76|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet84|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet80|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet88|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet4|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet56|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet0|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet8|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet112|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet52|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet152|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet44|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet12|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet68|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet16|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet64|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet124|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet60|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet116|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet120|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet104|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet152|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet188|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet156|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet148|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet140|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet64|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet92|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet60|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet96|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet144|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet68|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet40|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet72|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet128|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet124|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet92|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet120|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet96|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet172|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet32|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet176|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet36|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet32|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet12|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet16|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet76|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet80|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet140|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet84|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet88|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet148|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet100|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet36|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet112|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet180|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet144|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet184|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet136|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet104|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet132|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet164|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet188|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet160|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet24|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet28|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet168|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet156|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet152|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet132|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet48|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet180|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet44|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet100|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet136|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet116|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet96|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet108|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet92|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet16|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet12|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet36|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet32|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet48|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet160|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet168|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet164|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet168|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet160|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet164|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet80|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet116|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet156|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet84|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet112|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet88|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet108|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet20|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet24|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet28|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet28|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet20|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet76|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet24|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet72|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet172|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet184|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet8|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet4|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet176|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet0|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet172|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet40|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet136|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet132|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet128|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet56|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet20|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet52|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet108|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet68|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet100|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet176|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet64|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet104|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet60|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet180|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet144|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet184|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet140|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet188|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet148|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet128|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet4|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet44|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet0|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet40|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet120|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet124|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet8|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet48|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet52|2": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet56|2": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet72|2": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet76|2": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet84|2": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet80|2": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet88|2": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet4|2": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet56|2": { "scheduler": "scheduler.0" }, - "Ethernet4|0": { + "dut-lc3|Asic0|Ethernet0|2": { "scheduler": "scheduler.0" }, - "Ethernet8|0": { + "dut-lc3|Asic0|Ethernet8|2": { "scheduler": "scheduler.0" }, - "Ethernet12|0": { + "dut-lc3|Asic0|Ethernet112|2": { "scheduler": "scheduler.0" }, - "Ethernet16|0": { + "dut-lc4|Asic0|Ethernet52|2": { "scheduler": "scheduler.0" }, - "Ethernet20|0": { + "dut-lc4|Asic0|Ethernet152|2": { "scheduler": "scheduler.0" }, - "Ethernet24|0": { + "dut-lc5|Asic0|Ethernet44|2": { "scheduler": "scheduler.0" }, - "Ethernet28|0": { + "dut-lc4|Asic0|Ethernet12|2": { "scheduler": "scheduler.0" }, - "Ethernet32|0": { + "dut-lc3|Asic0|Ethernet68|2": { "scheduler": "scheduler.0" }, - "Ethernet36|0": { + "dut-lc4|Asic0|Ethernet16|2": { "scheduler": "scheduler.0" }, - "Ethernet40|0": { + "dut-lc3|Asic0|Ethernet64|2": { "scheduler": "scheduler.0" }, - "Ethernet44|0": { + "dut-lc3|Asic0|Ethernet124|2": { "scheduler": "scheduler.0" }, - "Ethernet48|0": { + "dut-lc3|Asic0|Ethernet60|2": { "scheduler": "scheduler.0" }, - "Ethernet52|0": { + "dut-lc3|Asic0|Ethernet116|2": { "scheduler": "scheduler.0" }, - "Ethernet56|0": { + "dut-lc3|Asic0|Ethernet120|2": { "scheduler": "scheduler.0" }, - "Ethernet60|0": { + "dut-lc4|Asic0|Ethernet104|2": { "scheduler": "scheduler.0" }, - "Ethernet64|0": { + "dut-lc5|Asic0|Ethernet152|2": { "scheduler": "scheduler.0" }, - "Ethernet68|0": { + "dut-lc4|Asic0|Ethernet188|2": { "scheduler": "scheduler.0" }, - "Ethernet72|0": { + "dut-lc5|Asic0|Ethernet156|2": { "scheduler": "scheduler.0" }, - "Ethernet76|0": { + "dut-lc4|Asic0|Ethernet148|2": { "scheduler": "scheduler.0" }, - "Ethernet80|0": { + "dut-lc4|Asic0|Ethernet140|2": { "scheduler": "scheduler.0" }, - "Ethernet84|0": { + "dut-lc4|Asic0|Ethernet64|2": { "scheduler": "scheduler.0" }, - "Ethernet88|0": { + "dut-lc3|Asic0|Ethernet92|2": { "scheduler": "scheduler.0" }, - "Ethernet92|0": { + "dut-lc4|Asic0|Ethernet60|2": { "scheduler": "scheduler.0" }, - "Ethernet96|0": { + "dut-lc3|Asic0|Ethernet96|2": { "scheduler": "scheduler.0" }, - "Ethernet100|0": { + "dut-lc3|Asic0|Ethernet144|2": { "scheduler": "scheduler.0" }, - "Ethernet104|0": { + "dut-lc4|Asic0|Ethernet68|2": { "scheduler": "scheduler.0" }, - "Ethernet108|0": { + "dut-lc4|Asic0|Ethernet40|2": { "scheduler": "scheduler.0" }, - "Ethernet112|0": { + "dut-lc4|Asic0|Ethernet72|2": { "scheduler": "scheduler.0" }, - "Ethernet116|0": { + "dut-lc5|Asic0|Ethernet128|2": { "scheduler": "scheduler.0" }, - "Ethernet120|0": { + "dut-lc5|Asic0|Ethernet124|2": { "scheduler": "scheduler.0" }, - "Ethernet124|0": { + "dut-lc4|Asic0|Ethernet92|2": { "scheduler": "scheduler.0" }, - "Ethernet128|0": { + "dut-lc5|Asic0|Ethernet120|2": { "scheduler": "scheduler.0" }, - "Ethernet132|0": { + "dut-lc4|Asic0|Ethernet96|2": { "scheduler": "scheduler.0" }, - "Ethernet136|0": { + "dut-lc4|Asic0|Ethernet172|2": { "scheduler": "scheduler.0" }, - "Ethernet140|0": { + "dut-lc5|Asic0|Ethernet32|2": { "scheduler": "scheduler.0" }, - "Ethernet144|0": { + "dut-lc4|Asic0|Ethernet176|2": { "scheduler": "scheduler.0" }, - "Ethernet148|0": { + "dut-lc5|Asic0|Ethernet36|2": { "scheduler": "scheduler.0" }, - "Ethernet152|0": { + "dut-lc4|Asic0|Ethernet32|2": { "scheduler": "scheduler.0" }, - "Ethernet156|0": { + "dut-lc3|Asic0|Ethernet12|2": { "scheduler": "scheduler.0" }, - "Ethernet164|0": { + "dut-lc3|Asic0|Ethernet16|2": { "scheduler": "scheduler.0" }, - "Ethernet176|0": { + "dut-lc4|Asic0|Ethernet76|2": { "scheduler": "scheduler.0" }, - "Ethernet180|0": { + "dut-lc3|Asic0|Ethernet80|2": { "scheduler": "scheduler.0" }, - "Ethernet184|0": { + "dut-lc3|Asic0|Ethernet140|2": { "scheduler": "scheduler.0" }, - "Ethernet188|0": { + "dut-lc3|Asic0|Ethernet84|2": { "scheduler": "scheduler.0" }, - "Ethernet0|1": { + "dut-lc3|Asic0|Ethernet88|2": { "scheduler": "scheduler.0" }, - "Ethernet4|1": { + "dut-lc3|Asic0|Ethernet148|2": { "scheduler": "scheduler.0" }, - "Ethernet8|1": { + "dut-lc4|Asic0|Ethernet100|2": { "scheduler": "scheduler.0" }, - "Ethernet12|1": { + "dut-lc4|Asic0|Ethernet36|2": { "scheduler": "scheduler.0" }, - "Ethernet16|1": { + "dut-lc4|Asic0|Ethernet112|2": { "scheduler": "scheduler.0" }, - "Ethernet20|1": { + "dut-lc5|Asic0|Ethernet180|2": { "scheduler": "scheduler.0" }, - "Ethernet24|1": { + "dut-lc4|Asic0|Ethernet144|2": { "scheduler": "scheduler.0" }, - "Ethernet28|1": { + "dut-lc5|Asic0|Ethernet184|2": { "scheduler": "scheduler.0" }, - "Ethernet32|1": { + "dut-lc5|Asic0|Ethernet136|2": { "scheduler": "scheduler.0" }, - "Ethernet36|1": { + "dut-lc5|Asic0|Ethernet104|2": { "scheduler": "scheduler.0" }, - "Ethernet40|1": { + "dut-lc5|Asic0|Ethernet132|2": { "scheduler": "scheduler.0" }, - "Ethernet44|1": { + "dut-lc4|Asic0|Ethernet164|2": { "scheduler": "scheduler.0" }, - "Ethernet48|1": { + "dut-lc5|Asic0|Ethernet188|2": { "scheduler": "scheduler.0" }, - "Ethernet52|1": { + "dut-lc4|Asic0|Ethernet160|2": { "scheduler": "scheduler.0" }, - "Ethernet56|1": { + "dut-lc5|Asic0|Ethernet24|2": { "scheduler": "scheduler.0" }, - "Ethernet60|1": { + "dut-lc5|Asic0|Ethernet28|2": { "scheduler": "scheduler.0" }, - "Ethernet64|1": { + "dut-lc4|Asic0|Ethernet168|2": { "scheduler": "scheduler.0" }, - "Ethernet68|1": { + "dut-lc3|Asic0|Ethernet156|2": { "scheduler": "scheduler.0" }, - "Ethernet72|1": { + "dut-lc3|Asic0|Ethernet152|2": { "scheduler": "scheduler.0" }, - "Ethernet76|1": { + "dut-lc3|Asic0|Ethernet132|2": { "scheduler": "scheduler.0" }, - "Ethernet80|1": { + "dut-lc4|Asic0|Ethernet48|2": { "scheduler": "scheduler.0" }, - "Ethernet84|1": { + "dut-lc4|Asic0|Ethernet180|2": { "scheduler": "scheduler.0" }, - "Ethernet88|1": { + "dut-lc4|Asic0|Ethernet44|2": { "scheduler": "scheduler.0" }, - "Ethernet92|1": { + "dut-lc5|Asic0|Ethernet100|2": { "scheduler": "scheduler.0" }, - "Ethernet96|1": { + "dut-lc3|Asic0|Ethernet136|2": { "scheduler": "scheduler.0" }, - "Ethernet100|1": { + "dut-lc4|Asic0|Ethernet116|2": { "scheduler": "scheduler.0" }, - "Ethernet104|1": { + "dut-lc5|Asic0|Ethernet96|2": { "scheduler": "scheduler.0" }, - "Ethernet108|1": { + "dut-lc5|Asic0|Ethernet108|2": { "scheduler": "scheduler.0" }, - "Ethernet112|1": { + "dut-lc5|Asic0|Ethernet92|2": { "scheduler": "scheduler.0" }, - "Ethernet116|1": { + "dut-lc5|Asic0|Ethernet16|2": { "scheduler": "scheduler.0" }, - "Ethernet120|1": { + "dut-lc5|Asic0|Ethernet12|2": { "scheduler": "scheduler.0" }, - "Ethernet124|1": { + "dut-lc3|Asic0|Ethernet36|2": { "scheduler": "scheduler.0" }, - "Ethernet128|1": { + "dut-lc3|Asic0|Ethernet32|2": { "scheduler": "scheduler.0" }, - "Ethernet132|1": { + "dut-lc5|Asic0|Ethernet48|2": { "scheduler": "scheduler.0" }, - "Ethernet136|1": { + "dut-lc5|Asic0|Ethernet160|2": { "scheduler": "scheduler.0" }, - "Ethernet140|1": { + "dut-lc3|Asic0|Ethernet168|2": { "scheduler": "scheduler.0" }, - "Ethernet144|1": { + "dut-lc5|Asic0|Ethernet164|2": { "scheduler": "scheduler.0" }, - "Ethernet148|1": { + "dut-lc5|Asic0|Ethernet168|2": { "scheduler": "scheduler.0" }, - "Ethernet152|1": { + "dut-lc3|Asic0|Ethernet160|2": { "scheduler": "scheduler.0" }, - "Ethernet156|1": { + "dut-lc3|Asic0|Ethernet164|2": { "scheduler": "scheduler.0" }, - "Ethernet164|1": { + "dut-lc5|Asic0|Ethernet80|2": { "scheduler": "scheduler.0" }, - "Ethernet176|1": { + "dut-lc5|Asic0|Ethernet116|2": { "scheduler": "scheduler.0" }, - "Ethernet180|1": { + "dut-lc4|Asic0|Ethernet156|2": { "scheduler": "scheduler.0" }, - "Ethernet184|1": { + "dut-lc5|Asic0|Ethernet84|2": { "scheduler": "scheduler.0" }, - "Ethernet188|1": { + "dut-lc5|Asic0|Ethernet112|2": { "scheduler": "scheduler.0" }, - "Ethernet0|2": { + "dut-lc5|Asic0|Ethernet88|2": { "scheduler": "scheduler.0" }, - "Ethernet4|2": { + "dut-lc4|Asic0|Ethernet108|2": { "scheduler": "scheduler.0" }, - "Ethernet8|2": { + "dut-lc3|Asic0|Ethernet20|2": { "scheduler": "scheduler.0" }, - "Ethernet12|2": { + "dut-lc3|Asic0|Ethernet24|2": { "scheduler": "scheduler.0" }, - "Ethernet16|2": { + "dut-lc3|Asic0|Ethernet28|2": { "scheduler": "scheduler.0" }, - "Ethernet20|2": { + "dut-lc4|Asic0|Ethernet28|2": { "scheduler": "scheduler.0" }, - "Ethernet24|2": { + "dut-lc4|Asic0|Ethernet20|2": { "scheduler": "scheduler.0" }, - "Ethernet28|2": { + "dut-lc5|Asic0|Ethernet76|2": { "scheduler": "scheduler.0" }, - "Ethernet32|2": { + "dut-lc4|Asic0|Ethernet24|2": { "scheduler": "scheduler.0" }, - "Ethernet36|2": { + "dut-lc5|Asic0|Ethernet72|2": { "scheduler": "scheduler.0" }, - "Ethernet40|2": { + "dut-lc5|Asic0|Ethernet172|2": { "scheduler": "scheduler.0" }, - "Ethernet44|2": { + "dut-lc4|Asic0|Ethernet184|2": { "scheduler": "scheduler.0" }, - "Ethernet48|2": { + "dut-lc5|Asic0|Ethernet8|2": { "scheduler": "scheduler.0" }, - "Ethernet52|2": { + "dut-lc5|Asic0|Ethernet4|2": { "scheduler": "scheduler.0" }, - "Ethernet56|2": { + "dut-lc3|Asic0|Ethernet176|2": { "scheduler": "scheduler.0" }, - "Ethernet60|2": { + "dut-lc5|Asic0|Ethernet0|2": { "scheduler": "scheduler.0" }, - "Ethernet64|2": { + "dut-lc3|Asic0|Ethernet172|2": { "scheduler": "scheduler.0" }, - "Ethernet68|2": { + "dut-lc5|Asic0|Ethernet40|2": { "scheduler": "scheduler.0" }, - "Ethernet72|2": { + "dut-lc4|Asic0|Ethernet136|2": { "scheduler": "scheduler.0" }, - "Ethernet76|2": { + "dut-lc4|Asic0|Ethernet132|2": { "scheduler": "scheduler.0" }, - "Ethernet80|2": { + "dut-lc3|Asic0|Ethernet128|2": { "scheduler": "scheduler.0" }, - "Ethernet84|2": { + "dut-lc3|Asic0|Ethernet56|2": { "scheduler": "scheduler.0" }, - "Ethernet88|2": { + "dut-lc5|Asic0|Ethernet20|2": { "scheduler": "scheduler.0" }, - "Ethernet92|2": { + "dut-lc3|Asic0|Ethernet52|2": { "scheduler": "scheduler.0" }, - "Ethernet96|2": { + "dut-lc3|Asic0|Ethernet108|2": { "scheduler": "scheduler.0" }, - "Ethernet100|2": { + "dut-lc5|Asic0|Ethernet68|2": { "scheduler": "scheduler.0" }, - "Ethernet104|2": { + "dut-lc3|Asic0|Ethernet100|2": { "scheduler": "scheduler.0" }, - "Ethernet108|2": { + "dut-lc5|Asic0|Ethernet176|2": { "scheduler": "scheduler.0" }, - "Ethernet112|2": { + "dut-lc5|Asic0|Ethernet64|2": { "scheduler": "scheduler.0" }, - "Ethernet116|2": { + "dut-lc3|Asic0|Ethernet104|2": { "scheduler": "scheduler.0" }, - "Ethernet120|2": { + "dut-lc5|Asic0|Ethernet60|2": { "scheduler": "scheduler.0" }, - "Ethernet124|2": { + "dut-lc3|Asic0|Ethernet180|2": { "scheduler": "scheduler.0" }, - "Ethernet128|2": { + "dut-lc5|Asic0|Ethernet144|2": { "scheduler": "scheduler.0" }, - "Ethernet132|2": { + "dut-lc3|Asic0|Ethernet184|2": { "scheduler": "scheduler.0" }, - "Ethernet136|2": { + "dut-lc5|Asic0|Ethernet140|2": { "scheduler": "scheduler.0" }, - "Ethernet140|2": { + "dut-lc3|Asic0|Ethernet188|2": { "scheduler": "scheduler.0" }, - "Ethernet144|2": { + "dut-lc5|Asic0|Ethernet148|2": { "scheduler": "scheduler.0" }, - "Ethernet148|2": { + "dut-lc4|Asic0|Ethernet128|2": { "scheduler": "scheduler.0" }, - "Ethernet152|2": { + "dut-lc4|Asic0|Ethernet4|2": { "scheduler": "scheduler.0" }, - "Ethernet156|2": { + "dut-lc3|Asic0|Ethernet44|2": { "scheduler": "scheduler.0" }, - "Ethernet164|2": { + "dut-lc4|Asic0|Ethernet0|2": { "scheduler": "scheduler.0" }, - "Ethernet176|2": { + "dut-lc3|Asic0|Ethernet40|2": { "scheduler": "scheduler.0" }, - "Ethernet180|2": { + "dut-lc4|Asic0|Ethernet120|2": { "scheduler": "scheduler.0" }, - "Ethernet184|2": { + "dut-lc4|Asic0|Ethernet124|2": { "scheduler": "scheduler.0" }, - "Ethernet188|2": { + "dut-lc4|Asic0|Ethernet8|2": { "scheduler": "scheduler.0" }, - "Ethernet0|5": { + "dut-lc3|Asic0|Ethernet48|2": { "scheduler": "scheduler.0" }, - "Ethernet4|5": { + "dut-lc5|Asic0|Ethernet52|5": { "scheduler": "scheduler.0" }, - "Ethernet8|5": { + "dut-lc5|Asic0|Ethernet56|5": { "scheduler": "scheduler.0" }, - "Ethernet12|5": { + "dut-lc3|Asic0|Ethernet72|5": { "scheduler": "scheduler.0" }, - "Ethernet16|5": { + "dut-lc3|Asic0|Ethernet76|5": { "scheduler": "scheduler.0" }, - "Ethernet20|5": { + "dut-lc4|Asic0|Ethernet84|5": { "scheduler": "scheduler.0" }, - "Ethernet24|5": { + "dut-lc4|Asic0|Ethernet80|5": { "scheduler": "scheduler.0" }, - "Ethernet28|5": { + "dut-lc4|Asic0|Ethernet88|5": { "scheduler": "scheduler.0" }, - "Ethernet32|5": { + "dut-lc3|Asic0|Ethernet4|5": { "scheduler": "scheduler.0" }, - "Ethernet36|5": { + "dut-lc4|Asic0|Ethernet56|5": { "scheduler": "scheduler.0" }, - "Ethernet40|5": { + "dut-lc3|Asic0|Ethernet0|5": { "scheduler": "scheduler.0" }, - "Ethernet44|5": { + "dut-lc3|Asic0|Ethernet8|5": { "scheduler": "scheduler.0" }, - "Ethernet48|5": { + "dut-lc3|Asic0|Ethernet112|5": { "scheduler": "scheduler.0" }, - "Ethernet52|5": { + "dut-lc4|Asic0|Ethernet52|5": { "scheduler": "scheduler.0" }, - "Ethernet56|5": { + "dut-lc4|Asic0|Ethernet152|5": { "scheduler": "scheduler.0" }, - "Ethernet60|5": { + "dut-lc5|Asic0|Ethernet44|5": { "scheduler": "scheduler.0" }, - "Ethernet64|5": { + "dut-lc4|Asic0|Ethernet12|5": { "scheduler": "scheduler.0" }, - "Ethernet68|5": { + "dut-lc3|Asic0|Ethernet68|5": { "scheduler": "scheduler.0" }, - "Ethernet72|5": { + "dut-lc4|Asic0|Ethernet16|5": { "scheduler": "scheduler.0" }, - "Ethernet76|5": { + "dut-lc3|Asic0|Ethernet64|5": { "scheduler": "scheduler.0" }, - "Ethernet80|5": { + "dut-lc3|Asic0|Ethernet124|5": { "scheduler": "scheduler.0" }, - "Ethernet84|5": { + "dut-lc3|Asic0|Ethernet60|5": { "scheduler": "scheduler.0" }, - "Ethernet88|5": { + "dut-lc3|Asic0|Ethernet116|5": { "scheduler": "scheduler.0" }, - "Ethernet92|5": { + "dut-lc3|Asic0|Ethernet120|5": { "scheduler": "scheduler.0" }, - "Ethernet96|5": { + "dut-lc4|Asic0|Ethernet104|5": { "scheduler": "scheduler.0" }, - "Ethernet100|5": { + "dut-lc5|Asic0|Ethernet152|5": { "scheduler": "scheduler.0" }, - "Ethernet104|5": { + "dut-lc4|Asic0|Ethernet188|5": { "scheduler": "scheduler.0" }, - "Ethernet108|5": { + "dut-lc5|Asic0|Ethernet156|5": { "scheduler": "scheduler.0" }, - "Ethernet112|5": { + "dut-lc4|Asic0|Ethernet148|5": { "scheduler": "scheduler.0" }, - "Ethernet116|5": { + "dut-lc4|Asic0|Ethernet140|5": { "scheduler": "scheduler.0" }, - "Ethernet120|5": { + "dut-lc4|Asic0|Ethernet64|5": { "scheduler": "scheduler.0" }, - "Ethernet124|5": { + "dut-lc3|Asic0|Ethernet92|5": { "scheduler": "scheduler.0" }, - "Ethernet128|5": { + "dut-lc4|Asic0|Ethernet60|5": { "scheduler": "scheduler.0" }, - "Ethernet132|5": { + "dut-lc3|Asic0|Ethernet96|5": { "scheduler": "scheduler.0" }, - "Ethernet136|5": { + "dut-lc3|Asic0|Ethernet144|5": { "scheduler": "scheduler.0" }, - "Ethernet140|5": { + "dut-lc4|Asic0|Ethernet68|5": { "scheduler": "scheduler.0" }, - "Ethernet144|5": { + "dut-lc4|Asic0|Ethernet40|5": { "scheduler": "scheduler.0" }, - "Ethernet148|5": { + "dut-lc4|Asic0|Ethernet72|5": { "scheduler": "scheduler.0" }, - "Ethernet152|5": { + "dut-lc5|Asic0|Ethernet128|5": { "scheduler": "scheduler.0" }, - "Ethernet156|5": { + "dut-lc5|Asic0|Ethernet124|5": { "scheduler": "scheduler.0" }, - "Ethernet164|5": { + "dut-lc4|Asic0|Ethernet92|5": { "scheduler": "scheduler.0" }, - "Ethernet176|5": { + "dut-lc5|Asic0|Ethernet120|5": { "scheduler": "scheduler.0" }, - "Ethernet180|5": { + "dut-lc4|Asic0|Ethernet96|5": { "scheduler": "scheduler.0" }, - "Ethernet184|5": { + "dut-lc4|Asic0|Ethernet172|5": { "scheduler": "scheduler.0" }, - "Ethernet188|5": { + "dut-lc5|Asic0|Ethernet32|5": { "scheduler": "scheduler.0" }, - "Ethernet0|6": { + "dut-lc4|Asic0|Ethernet176|5": { "scheduler": "scheduler.0" }, - "Ethernet4|6": { + "dut-lc5|Asic0|Ethernet36|5": { "scheduler": "scheduler.0" }, - "Ethernet8|6": { + "dut-lc4|Asic0|Ethernet32|5": { "scheduler": "scheduler.0" }, - "Ethernet12|6": { + "dut-lc3|Asic0|Ethernet12|5": { "scheduler": "scheduler.0" }, - "Ethernet16|6": { + "dut-lc3|Asic0|Ethernet16|5": { "scheduler": "scheduler.0" }, - "Ethernet20|6": { + "dut-lc4|Asic0|Ethernet76|5": { "scheduler": "scheduler.0" }, - "Ethernet24|6": { + "dut-lc3|Asic0|Ethernet80|5": { "scheduler": "scheduler.0" }, - "Ethernet28|6": { + "dut-lc3|Asic0|Ethernet140|5": { "scheduler": "scheduler.0" }, - "Ethernet32|6": { + "dut-lc3|Asic0|Ethernet84|5": { "scheduler": "scheduler.0" }, - "Ethernet36|6": { + "dut-lc3|Asic0|Ethernet88|5": { "scheduler": "scheduler.0" }, - "Ethernet40|6": { + "dut-lc3|Asic0|Ethernet148|5": { "scheduler": "scheduler.0" }, - "Ethernet44|6": { + "dut-lc4|Asic0|Ethernet100|5": { "scheduler": "scheduler.0" }, - "Ethernet48|6": { + "dut-lc4|Asic0|Ethernet36|5": { "scheduler": "scheduler.0" }, - "Ethernet52|6": { + "dut-lc4|Asic0|Ethernet112|5": { "scheduler": "scheduler.0" }, - "Ethernet56|6": { + "dut-lc5|Asic0|Ethernet180|5": { "scheduler": "scheduler.0" }, - "Ethernet60|6": { + "dut-lc4|Asic0|Ethernet144|5": { "scheduler": "scheduler.0" }, - "Ethernet64|6": { + "dut-lc5|Asic0|Ethernet184|5": { "scheduler": "scheduler.0" }, - "Ethernet68|6": { + "dut-lc5|Asic0|Ethernet136|5": { "scheduler": "scheduler.0" }, - "Ethernet72|6": { + "dut-lc5|Asic0|Ethernet104|5": { "scheduler": "scheduler.0" }, - "Ethernet76|6": { + "dut-lc5|Asic0|Ethernet132|5": { "scheduler": "scheduler.0" }, - "Ethernet80|6": { + "dut-lc4|Asic0|Ethernet164|5": { "scheduler": "scheduler.0" }, - "Ethernet84|6": { + "dut-lc5|Asic0|Ethernet188|5": { "scheduler": "scheduler.0" }, - "Ethernet88|6": { + "dut-lc4|Asic0|Ethernet160|5": { "scheduler": "scheduler.0" }, - "Ethernet92|6": { + "dut-lc5|Asic0|Ethernet24|5": { "scheduler": "scheduler.0" }, - "Ethernet96|6": { + "dut-lc5|Asic0|Ethernet28|5": { "scheduler": "scheduler.0" }, - "Ethernet100|6": { + "dut-lc4|Asic0|Ethernet168|5": { "scheduler": "scheduler.0" }, - "Ethernet104|6": { + "dut-lc3|Asic0|Ethernet156|5": { "scheduler": "scheduler.0" }, - "Ethernet108|6": { + "dut-lc3|Asic0|Ethernet152|5": { "scheduler": "scheduler.0" }, - "Ethernet112|6": { + "dut-lc3|Asic0|Ethernet132|5": { "scheduler": "scheduler.0" }, - "Ethernet116|6": { + "dut-lc4|Asic0|Ethernet48|5": { "scheduler": "scheduler.0" }, - "Ethernet120|6": { + "dut-lc4|Asic0|Ethernet180|5": { "scheduler": "scheduler.0" }, - "Ethernet124|6": { + "dut-lc4|Asic0|Ethernet44|5": { "scheduler": "scheduler.0" }, - "Ethernet128|6": { + "dut-lc5|Asic0|Ethernet100|5": { "scheduler": "scheduler.0" }, - "Ethernet132|6": { + "dut-lc3|Asic0|Ethernet136|5": { "scheduler": "scheduler.0" }, - "Ethernet136|6": { + "dut-lc4|Asic0|Ethernet116|5": { "scheduler": "scheduler.0" }, - "Ethernet140|6": { + "dut-lc5|Asic0|Ethernet96|5": { "scheduler": "scheduler.0" }, - "Ethernet144|6": { + "dut-lc5|Asic0|Ethernet108|5": { "scheduler": "scheduler.0" }, - "Ethernet148|6": { + "dut-lc5|Asic0|Ethernet92|5": { "scheduler": "scheduler.0" }, - "Ethernet152|6": { + "dut-lc5|Asic0|Ethernet16|5": { "scheduler": "scheduler.0" }, - "Ethernet156|6": { + "dut-lc5|Asic0|Ethernet12|5": { "scheduler": "scheduler.0" }, - "Ethernet164|6": { + "dut-lc3|Asic0|Ethernet36|5": { "scheduler": "scheduler.0" }, - "Ethernet176|6": { + "dut-lc3|Asic0|Ethernet32|5": { "scheduler": "scheduler.0" }, - "Ethernet180|6": { + "dut-lc5|Asic0|Ethernet48|5": { "scheduler": "scheduler.0" }, - "Ethernet184|6": { + "dut-lc5|Asic0|Ethernet160|5": { "scheduler": "scheduler.0" }, - "Ethernet188|6": { + "dut-lc3|Asic0|Ethernet168|5": { "scheduler": "scheduler.0" - } + }, + "dut-lc5|Asic0|Ethernet164|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet168|5": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet160|5": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet164|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet80|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet116|5": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet156|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet84|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet112|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet88|5": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet108|5": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet20|5": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet24|5": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet28|5": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet28|5": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet20|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet76|5": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet24|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet72|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet172|5": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet184|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet8|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet4|5": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet176|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet0|5": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet172|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet40|5": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet136|5": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet132|5": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet128|5": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet56|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet20|5": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet52|5": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet108|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet68|5": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet100|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet176|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet64|5": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet104|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet60|5": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet180|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet144|5": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet184|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet140|5": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet188|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet148|5": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet128|5": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet4|5": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet44|5": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet0|5": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet40|5": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet120|5": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet124|5": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet8|5": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet48|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet52|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet56|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet72|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet76|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet84|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet80|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet88|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet4|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet56|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet0|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet8|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet112|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet52|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet152|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet44|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet12|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet68|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet16|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet64|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet124|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet60|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet116|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet120|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet104|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet152|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet188|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet156|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet148|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet140|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet64|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet92|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet60|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet96|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet144|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet68|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet40|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet72|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet128|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet124|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet92|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet120|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet96|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet172|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet32|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet176|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet36|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet32|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet12|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet16|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet76|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet80|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet140|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet84|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet88|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet148|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet100|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet36|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet112|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet180|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet144|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet184|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet136|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet104|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet132|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet164|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet188|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet160|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet24|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet28|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet168|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet156|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet152|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet132|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet48|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet180|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet44|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet100|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet136|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet116|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet96|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet108|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet92|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet16|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet12|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet36|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet32|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet48|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet160|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet168|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet164|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet168|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet160|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet164|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet80|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet116|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet156|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet84|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet112|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet88|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet108|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet20|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet24|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet28|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet28|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet20|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet76|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet24|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet72|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet172|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet184|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet8|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet4|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet176|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet0|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet172|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet40|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet136|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet132|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet128|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet56|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet20|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet52|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet108|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet68|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet100|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet176|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet64|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet104|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet60|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet180|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet144|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet184|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet140|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet188|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet148|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet128|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet4|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet44|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet0|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet40|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet120|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet124|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet8|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet48|6": { + "scheduler": "scheduler.0" + } } } diff --git a/src/sonic-config-engine/tests/sample_output/py2/qos-arista7800r3-48cqm2-lc.json b/src/sonic-config-engine/tests/sample_output/py2/qos-arista7800r3-48cqm2-lc.json index 7aecbdbd90e5..1296b4e2b8fc 100644 --- a/src/sonic-config-engine/tests/sample_output/py2/qos-arista7800r3-48cqm2-lc.json +++ b/src/sonic-config-engine/tests/sample_output/py2/qos-arista7800r3-48cqm2-lc.json @@ -496,1040 +496,3174 @@ } }, "QUEUE": { - "Ethernet0|3": { + "dut-lc5|Asic0|Ethernet52|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet4|3": { + "dut-lc5|Asic0|Ethernet56|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet8|3": { + "dut-lc3|Asic0|Ethernet72|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet12|3": { + "dut-lc3|Asic0|Ethernet76|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet16|3": { + "dut-lc4|Asic0|Ethernet84|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet20|3": { + "dut-lc4|Asic0|Ethernet80|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet24|3": { + "dut-lc4|Asic0|Ethernet88|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet28|3": { + "dut-lc3|Asic0|Ethernet4|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet32|3": { + "dut-lc4|Asic0|Ethernet56|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet36|3": { + "dut-lc3|Asic0|Ethernet0|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet40|3": { + "dut-lc3|Asic0|Ethernet8|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet44|3": { + "dut-lc3|Asic0|Ethernet112|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet48|3": { + "dut-lc4|Asic0|Ethernet52|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet52|3": { + "dut-lc4|Asic0|Ethernet152|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet56|3": { + "dut-lc5|Asic0|Ethernet44|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet60|3": { + "dut-lc4|Asic0|Ethernet12|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet64|3": { + "dut-lc3|Asic0|Ethernet68|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet68|3": { + "dut-lc4|Asic0|Ethernet16|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet72|3": { + "dut-lc3|Asic0|Ethernet64|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet76|3": { + "dut-lc3|Asic0|Ethernet124|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet80|3": { + "dut-lc3|Asic0|Ethernet60|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet84|3": { + "dut-lc3|Asic0|Ethernet116|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet88|3": { + "dut-lc3|Asic0|Ethernet120|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet92|3": { + "dut-lc4|Asic0|Ethernet104|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet96|3": { + "dut-lc5|Asic0|Ethernet152|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet100|3": { + "dut-lc4|Asic0|Ethernet188|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet104|3": { + "dut-lc5|Asic0|Ethernet156|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet108|3": { + "dut-lc4|Asic0|Ethernet148|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet112|3": { + "dut-lc4|Asic0|Ethernet140|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet116|3": { + "dut-lc4|Asic0|Ethernet64|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet120|3": { + "dut-lc3|Asic0|Ethernet92|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet124|3": { + "dut-lc4|Asic0|Ethernet60|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet128|3": { + "dut-lc3|Asic0|Ethernet96|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet132|3": { + "dut-lc3|Asic0|Ethernet144|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet136|3": { + "dut-lc4|Asic0|Ethernet68|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet140|3": { + "dut-lc4|Asic0|Ethernet40|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet144|3": { + "dut-lc4|Asic0|Ethernet72|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet148|3": { + "dut-lc5|Asic0|Ethernet128|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet152|3": { + "dut-lc5|Asic0|Ethernet124|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet156|3": { + "dut-lc4|Asic0|Ethernet92|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet164|3": { + "dut-lc5|Asic0|Ethernet120|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet176|3": { + "dut-lc4|Asic0|Ethernet96|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet180|3": { + "dut-lc4|Asic0|Ethernet172|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet184|3": { + "dut-lc5|Asic0|Ethernet32|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet188|3": { + "dut-lc4|Asic0|Ethernet176|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet0|4": { + "dut-lc5|Asic0|Ethernet36|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet4|4": { + "dut-lc4|Asic0|Ethernet32|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet8|4": { + "dut-lc3|Asic0|Ethernet12|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet12|4": { + "dut-lc3|Asic0|Ethernet16|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet16|4": { + "dut-lc4|Asic0|Ethernet76|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet20|4": { + "dut-lc3|Asic0|Ethernet80|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet24|4": { + "dut-lc3|Asic0|Ethernet140|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet28|4": { + "dut-lc3|Asic0|Ethernet84|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet32|4": { + "dut-lc3|Asic0|Ethernet88|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet36|4": { + "dut-lc3|Asic0|Ethernet148|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet40|4": { + "dut-lc4|Asic0|Ethernet100|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet44|4": { + "dut-lc4|Asic0|Ethernet36|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet48|4": { + "dut-lc4|Asic0|Ethernet112|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet52|4": { + "dut-lc5|Asic0|Ethernet180|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet56|4": { + "dut-lc4|Asic0|Ethernet144|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet60|4": { + "dut-lc5|Asic0|Ethernet184|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet64|4": { + "dut-lc5|Asic0|Ethernet136|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet68|4": { + "dut-lc5|Asic0|Ethernet104|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet72|4": { + "dut-lc5|Asic0|Ethernet132|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet76|4": { + "dut-lc4|Asic0|Ethernet164|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet80|4": { + "dut-lc5|Asic0|Ethernet188|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet84|4": { + "dut-lc4|Asic0|Ethernet160|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet88|4": { + "dut-lc5|Asic0|Ethernet24|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet92|4": { + "dut-lc5|Asic0|Ethernet28|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet96|4": { + "dut-lc4|Asic0|Ethernet168|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet100|4": { + "dut-lc3|Asic0|Ethernet156|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet104|4": { + "dut-lc3|Asic0|Ethernet152|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet108|4": { + "dut-lc3|Asic0|Ethernet132|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet112|4": { + "dut-lc4|Asic0|Ethernet48|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet116|4": { + "dut-lc4|Asic0|Ethernet180|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet120|4": { + "dut-lc4|Asic0|Ethernet44|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet124|4": { + "dut-lc5|Asic0|Ethernet100|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet128|4": { + "dut-lc3|Asic0|Ethernet136|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet132|4": { + "dut-lc4|Asic0|Ethernet116|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet136|4": { + "dut-lc5|Asic0|Ethernet96|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet140|4": { + "dut-lc5|Asic0|Ethernet108|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet144|4": { + "dut-lc5|Asic0|Ethernet92|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet148|4": { + "dut-lc5|Asic0|Ethernet16|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet152|4": { + "dut-lc5|Asic0|Ethernet12|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet156|4": { + "dut-lc3|Asic0|Ethernet36|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet164|4": { + "dut-lc3|Asic0|Ethernet32|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet176|4": { + "dut-lc5|Asic0|Ethernet48|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet180|4": { + "dut-lc5|Asic0|Ethernet160|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet184|4": { + "dut-lc3|Asic0|Ethernet168|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet188|4": { + "dut-lc5|Asic0|Ethernet164|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet0|0": { + "dut-lc5|Asic0|Ethernet168|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet160|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet164|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet80|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet116|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet156|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet84|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet112|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet88|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet108|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet20|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet24|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet28|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet28|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet20|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet76|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet24|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet72|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet172|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet184|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet8|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet4|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet176|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet0|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet172|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet40|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet136|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet132|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet128|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet56|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet20|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet52|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet108|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet68|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet100|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet176|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet64|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet104|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet60|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet180|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet144|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet184|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet140|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet188|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet148|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet128|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet4|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet44|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet0|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet40|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet120|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet124|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet8|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet48|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet52|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet56|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet72|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet76|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet84|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet80|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet88|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet4|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet56|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet0|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet8|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet112|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet52|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet152|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet44|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet12|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet68|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet16|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet64|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet124|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet60|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet116|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet120|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet104|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet152|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet188|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet156|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet148|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet140|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet64|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet92|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet60|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet96|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet144|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet68|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet40|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet72|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet128|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet124|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet92|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet120|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet96|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet172|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet32|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet176|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet36|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet32|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet12|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet16|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet76|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet80|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet140|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet84|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet88|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet148|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet100|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet36|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet112|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet180|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet144|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet184|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet136|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet104|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet132|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet164|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet188|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet160|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet24|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet28|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet168|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet156|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet152|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet132|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet48|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet180|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet44|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet100|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet136|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet116|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet96|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet108|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet92|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet16|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet12|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet36|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet32|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet48|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet160|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet168|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet164|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet168|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet160|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet164|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet80|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet116|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet156|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet84|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet112|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet88|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet108|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet20|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet24|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet28|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet28|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet20|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet76|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet24|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet72|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet172|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet184|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet8|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet4|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet176|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet0|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet172|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet40|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet136|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet132|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet128|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet56|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet20|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet52|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet108|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet68|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet100|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet176|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet64|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet104|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet60|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet180|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet144|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet184|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet140|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet188|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet148|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet128|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet4|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet44|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet0|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet40|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet120|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet124|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet8|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet48|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet52|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet56|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet72|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet76|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet84|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet80|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet88|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet4|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet56|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet0|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet8|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet112|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet52|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet152|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet44|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet12|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet68|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet16|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet64|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet124|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet60|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet116|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet120|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet104|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet152|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet188|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet156|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet148|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet140|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet64|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet92|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet60|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet96|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet144|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet68|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet40|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet72|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet128|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet124|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet92|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet120|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet96|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet172|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet32|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet176|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet36|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet32|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet12|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet16|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet76|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet80|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet140|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet84|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet88|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet148|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet100|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet36|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet112|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet180|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet144|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet184|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet136|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet104|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet132|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet164|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet188|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet160|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet24|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet28|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet168|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet156|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet152|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet132|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet48|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet180|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet44|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet100|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet136|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet116|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet96|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet108|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet92|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet16|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet12|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet36|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet32|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet48|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet160|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet168|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet164|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet168|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet160|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet164|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet80|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet116|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet156|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet84|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet112|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet88|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet108|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet20|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet24|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet28|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet28|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet20|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet76|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet24|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet72|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet172|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet184|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet8|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet4|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet176|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet0|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet172|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet40|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet136|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet132|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet128|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet56|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet20|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet52|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet108|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet68|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet100|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet176|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet64|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet104|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet60|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet180|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet144|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet184|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet140|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet188|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet148|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet128|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet4|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet44|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet0|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet40|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet120|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet124|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet8|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet48|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet52|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet56|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet72|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet76|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet84|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet80|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet88|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet4|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet56|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet0|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet8|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet112|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet52|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet152|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet44|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet12|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet68|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet16|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet64|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet124|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet60|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet116|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet120|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet104|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet152|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet188|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet156|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet148|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet140|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet64|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet92|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet60|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet96|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet144|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet68|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet40|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet72|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet128|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet124|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet92|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet120|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet96|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet172|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet32|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet176|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet36|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet32|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet12|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet16|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet76|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet80|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet140|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet84|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet88|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet148|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet100|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet36|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet112|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet180|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet144|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet184|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet136|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet104|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet132|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet164|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet188|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet160|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet24|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet28|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet168|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet156|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet152|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet132|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet48|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet180|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet44|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet100|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet136|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet116|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet96|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet108|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet92|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet16|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet12|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet36|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet32|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet48|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet160|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet168|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet164|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet168|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet160|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet164|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet80|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet116|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet156|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet84|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet112|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet88|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet108|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet20|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet24|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet28|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet28|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet20|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet76|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet24|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet72|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet172|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet184|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet8|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet4|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet176|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet0|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet172|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet40|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet136|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet132|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet128|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet56|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet20|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet52|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet108|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet68|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet100|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet176|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet64|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet104|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet60|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet180|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet144|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet184|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet140|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet188|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet148|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet128|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet4|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet44|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet0|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet40|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet120|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet124|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet8|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet48|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet52|2": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet56|2": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet72|2": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet76|2": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet84|2": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet80|2": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet88|2": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet4|2": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet56|2": { "scheduler": "scheduler.0" }, - "Ethernet4|0": { + "dut-lc3|Asic0|Ethernet0|2": { "scheduler": "scheduler.0" }, - "Ethernet8|0": { + "dut-lc3|Asic0|Ethernet8|2": { "scheduler": "scheduler.0" }, - "Ethernet12|0": { + "dut-lc3|Asic0|Ethernet112|2": { "scheduler": "scheduler.0" }, - "Ethernet16|0": { + "dut-lc4|Asic0|Ethernet52|2": { "scheduler": "scheduler.0" }, - "Ethernet20|0": { + "dut-lc4|Asic0|Ethernet152|2": { "scheduler": "scheduler.0" }, - "Ethernet24|0": { + "dut-lc5|Asic0|Ethernet44|2": { "scheduler": "scheduler.0" }, - "Ethernet28|0": { + "dut-lc4|Asic0|Ethernet12|2": { "scheduler": "scheduler.0" }, - "Ethernet32|0": { + "dut-lc3|Asic0|Ethernet68|2": { "scheduler": "scheduler.0" }, - "Ethernet36|0": { + "dut-lc4|Asic0|Ethernet16|2": { "scheduler": "scheduler.0" }, - "Ethernet40|0": { + "dut-lc3|Asic0|Ethernet64|2": { "scheduler": "scheduler.0" }, - "Ethernet44|0": { + "dut-lc3|Asic0|Ethernet124|2": { "scheduler": "scheduler.0" }, - "Ethernet48|0": { + "dut-lc3|Asic0|Ethernet60|2": { "scheduler": "scheduler.0" }, - "Ethernet52|0": { + "dut-lc3|Asic0|Ethernet116|2": { "scheduler": "scheduler.0" }, - "Ethernet56|0": { + "dut-lc3|Asic0|Ethernet120|2": { "scheduler": "scheduler.0" }, - "Ethernet60|0": { + "dut-lc4|Asic0|Ethernet104|2": { "scheduler": "scheduler.0" }, - "Ethernet64|0": { + "dut-lc5|Asic0|Ethernet152|2": { "scheduler": "scheduler.0" }, - "Ethernet68|0": { + "dut-lc4|Asic0|Ethernet188|2": { "scheduler": "scheduler.0" }, - "Ethernet72|0": { + "dut-lc5|Asic0|Ethernet156|2": { "scheduler": "scheduler.0" }, - "Ethernet76|0": { + "dut-lc4|Asic0|Ethernet148|2": { "scheduler": "scheduler.0" }, - "Ethernet80|0": { + "dut-lc4|Asic0|Ethernet140|2": { "scheduler": "scheduler.0" }, - "Ethernet84|0": { + "dut-lc4|Asic0|Ethernet64|2": { "scheduler": "scheduler.0" }, - "Ethernet88|0": { + "dut-lc3|Asic0|Ethernet92|2": { "scheduler": "scheduler.0" }, - "Ethernet92|0": { + "dut-lc4|Asic0|Ethernet60|2": { "scheduler": "scheduler.0" }, - "Ethernet96|0": { + "dut-lc3|Asic0|Ethernet96|2": { "scheduler": "scheduler.0" }, - "Ethernet100|0": { + "dut-lc3|Asic0|Ethernet144|2": { "scheduler": "scheduler.0" }, - "Ethernet104|0": { + "dut-lc4|Asic0|Ethernet68|2": { "scheduler": "scheduler.0" }, - "Ethernet108|0": { + "dut-lc4|Asic0|Ethernet40|2": { "scheduler": "scheduler.0" }, - "Ethernet112|0": { + "dut-lc4|Asic0|Ethernet72|2": { "scheduler": "scheduler.0" }, - "Ethernet116|0": { + "dut-lc5|Asic0|Ethernet128|2": { "scheduler": "scheduler.0" }, - "Ethernet120|0": { + "dut-lc5|Asic0|Ethernet124|2": { "scheduler": "scheduler.0" }, - "Ethernet124|0": { + "dut-lc4|Asic0|Ethernet92|2": { "scheduler": "scheduler.0" }, - "Ethernet128|0": { + "dut-lc5|Asic0|Ethernet120|2": { "scheduler": "scheduler.0" }, - "Ethernet132|0": { + "dut-lc4|Asic0|Ethernet96|2": { "scheduler": "scheduler.0" }, - "Ethernet136|0": { + "dut-lc4|Asic0|Ethernet172|2": { "scheduler": "scheduler.0" }, - "Ethernet140|0": { + "dut-lc5|Asic0|Ethernet32|2": { "scheduler": "scheduler.0" }, - "Ethernet144|0": { + "dut-lc4|Asic0|Ethernet176|2": { "scheduler": "scheduler.0" }, - "Ethernet148|0": { + "dut-lc5|Asic0|Ethernet36|2": { "scheduler": "scheduler.0" }, - "Ethernet152|0": { + "dut-lc4|Asic0|Ethernet32|2": { "scheduler": "scheduler.0" }, - "Ethernet156|0": { + "dut-lc3|Asic0|Ethernet12|2": { "scheduler": "scheduler.0" }, - "Ethernet164|0": { + "dut-lc3|Asic0|Ethernet16|2": { "scheduler": "scheduler.0" }, - "Ethernet176|0": { + "dut-lc4|Asic0|Ethernet76|2": { "scheduler": "scheduler.0" }, - "Ethernet180|0": { + "dut-lc3|Asic0|Ethernet80|2": { "scheduler": "scheduler.0" }, - "Ethernet184|0": { + "dut-lc3|Asic0|Ethernet140|2": { "scheduler": "scheduler.0" }, - "Ethernet188|0": { + "dut-lc3|Asic0|Ethernet84|2": { "scheduler": "scheduler.0" }, - "Ethernet0|1": { + "dut-lc3|Asic0|Ethernet88|2": { "scheduler": "scheduler.0" }, - "Ethernet4|1": { + "dut-lc3|Asic0|Ethernet148|2": { "scheduler": "scheduler.0" }, - "Ethernet8|1": { + "dut-lc4|Asic0|Ethernet100|2": { "scheduler": "scheduler.0" }, - "Ethernet12|1": { + "dut-lc4|Asic0|Ethernet36|2": { "scheduler": "scheduler.0" }, - "Ethernet16|1": { + "dut-lc4|Asic0|Ethernet112|2": { "scheduler": "scheduler.0" }, - "Ethernet20|1": { + "dut-lc5|Asic0|Ethernet180|2": { "scheduler": "scheduler.0" }, - "Ethernet24|1": { + "dut-lc4|Asic0|Ethernet144|2": { "scheduler": "scheduler.0" }, - "Ethernet28|1": { + "dut-lc5|Asic0|Ethernet184|2": { "scheduler": "scheduler.0" }, - "Ethernet32|1": { + "dut-lc5|Asic0|Ethernet136|2": { "scheduler": "scheduler.0" }, - "Ethernet36|1": { + "dut-lc5|Asic0|Ethernet104|2": { "scheduler": "scheduler.0" }, - "Ethernet40|1": { + "dut-lc5|Asic0|Ethernet132|2": { "scheduler": "scheduler.0" }, - "Ethernet44|1": { + "dut-lc4|Asic0|Ethernet164|2": { "scheduler": "scheduler.0" }, - "Ethernet48|1": { + "dut-lc5|Asic0|Ethernet188|2": { "scheduler": "scheduler.0" }, - "Ethernet52|1": { + "dut-lc4|Asic0|Ethernet160|2": { "scheduler": "scheduler.0" }, - "Ethernet56|1": { + "dut-lc5|Asic0|Ethernet24|2": { "scheduler": "scheduler.0" }, - "Ethernet60|1": { + "dut-lc5|Asic0|Ethernet28|2": { "scheduler": "scheduler.0" }, - "Ethernet64|1": { + "dut-lc4|Asic0|Ethernet168|2": { "scheduler": "scheduler.0" }, - "Ethernet68|1": { + "dut-lc3|Asic0|Ethernet156|2": { "scheduler": "scheduler.0" }, - "Ethernet72|1": { + "dut-lc3|Asic0|Ethernet152|2": { "scheduler": "scheduler.0" }, - "Ethernet76|1": { + "dut-lc3|Asic0|Ethernet132|2": { "scheduler": "scheduler.0" }, - "Ethernet80|1": { + "dut-lc4|Asic0|Ethernet48|2": { "scheduler": "scheduler.0" }, - "Ethernet84|1": { + "dut-lc4|Asic0|Ethernet180|2": { "scheduler": "scheduler.0" }, - "Ethernet88|1": { + "dut-lc4|Asic0|Ethernet44|2": { "scheduler": "scheduler.0" }, - "Ethernet92|1": { + "dut-lc5|Asic0|Ethernet100|2": { "scheduler": "scheduler.0" }, - "Ethernet96|1": { + "dut-lc3|Asic0|Ethernet136|2": { "scheduler": "scheduler.0" }, - "Ethernet100|1": { + "dut-lc4|Asic0|Ethernet116|2": { "scheduler": "scheduler.0" }, - "Ethernet104|1": { + "dut-lc5|Asic0|Ethernet96|2": { "scheduler": "scheduler.0" }, - "Ethernet108|1": { + "dut-lc5|Asic0|Ethernet108|2": { "scheduler": "scheduler.0" }, - "Ethernet112|1": { + "dut-lc5|Asic0|Ethernet92|2": { "scheduler": "scheduler.0" }, - "Ethernet116|1": { + "dut-lc5|Asic0|Ethernet16|2": { "scheduler": "scheduler.0" }, - "Ethernet120|1": { + "dut-lc5|Asic0|Ethernet12|2": { "scheduler": "scheduler.0" }, - "Ethernet124|1": { + "dut-lc3|Asic0|Ethernet36|2": { "scheduler": "scheduler.0" }, - "Ethernet128|1": { + "dut-lc3|Asic0|Ethernet32|2": { "scheduler": "scheduler.0" }, - "Ethernet132|1": { + "dut-lc5|Asic0|Ethernet48|2": { "scheduler": "scheduler.0" }, - "Ethernet136|1": { + "dut-lc5|Asic0|Ethernet160|2": { "scheduler": "scheduler.0" }, - "Ethernet140|1": { + "dut-lc3|Asic0|Ethernet168|2": { "scheduler": "scheduler.0" }, - "Ethernet144|1": { + "dut-lc5|Asic0|Ethernet164|2": { "scheduler": "scheduler.0" }, - "Ethernet148|1": { + "dut-lc5|Asic0|Ethernet168|2": { "scheduler": "scheduler.0" }, - "Ethernet152|1": { + "dut-lc3|Asic0|Ethernet160|2": { "scheduler": "scheduler.0" }, - "Ethernet156|1": { + "dut-lc3|Asic0|Ethernet164|2": { "scheduler": "scheduler.0" }, - "Ethernet164|1": { + "dut-lc5|Asic0|Ethernet80|2": { "scheduler": "scheduler.0" }, - "Ethernet176|1": { + "dut-lc5|Asic0|Ethernet116|2": { "scheduler": "scheduler.0" }, - "Ethernet180|1": { + "dut-lc4|Asic0|Ethernet156|2": { "scheduler": "scheduler.0" }, - "Ethernet184|1": { + "dut-lc5|Asic0|Ethernet84|2": { "scheduler": "scheduler.0" }, - "Ethernet188|1": { + "dut-lc5|Asic0|Ethernet112|2": { "scheduler": "scheduler.0" }, - "Ethernet0|2": { + "dut-lc5|Asic0|Ethernet88|2": { "scheduler": "scheduler.0" }, - "Ethernet4|2": { + "dut-lc4|Asic0|Ethernet108|2": { "scheduler": "scheduler.0" }, - "Ethernet8|2": { + "dut-lc3|Asic0|Ethernet20|2": { "scheduler": "scheduler.0" }, - "Ethernet12|2": { + "dut-lc3|Asic0|Ethernet24|2": { "scheduler": "scheduler.0" }, - "Ethernet16|2": { + "dut-lc3|Asic0|Ethernet28|2": { "scheduler": "scheduler.0" }, - "Ethernet20|2": { + "dut-lc4|Asic0|Ethernet28|2": { "scheduler": "scheduler.0" }, - "Ethernet24|2": { + "dut-lc4|Asic0|Ethernet20|2": { "scheduler": "scheduler.0" }, - "Ethernet28|2": { + "dut-lc5|Asic0|Ethernet76|2": { "scheduler": "scheduler.0" }, - "Ethernet32|2": { + "dut-lc4|Asic0|Ethernet24|2": { "scheduler": "scheduler.0" }, - "Ethernet36|2": { + "dut-lc5|Asic0|Ethernet72|2": { "scheduler": "scheduler.0" }, - "Ethernet40|2": { + "dut-lc5|Asic0|Ethernet172|2": { "scheduler": "scheduler.0" }, - "Ethernet44|2": { + "dut-lc4|Asic0|Ethernet184|2": { "scheduler": "scheduler.0" }, - "Ethernet48|2": { + "dut-lc5|Asic0|Ethernet8|2": { "scheduler": "scheduler.0" }, - "Ethernet52|2": { + "dut-lc5|Asic0|Ethernet4|2": { "scheduler": "scheduler.0" }, - "Ethernet56|2": { + "dut-lc3|Asic0|Ethernet176|2": { "scheduler": "scheduler.0" }, - "Ethernet60|2": { + "dut-lc5|Asic0|Ethernet0|2": { "scheduler": "scheduler.0" }, - "Ethernet64|2": { + "dut-lc3|Asic0|Ethernet172|2": { "scheduler": "scheduler.0" }, - "Ethernet68|2": { + "dut-lc5|Asic0|Ethernet40|2": { "scheduler": "scheduler.0" }, - "Ethernet72|2": { + "dut-lc4|Asic0|Ethernet136|2": { "scheduler": "scheduler.0" }, - "Ethernet76|2": { + "dut-lc4|Asic0|Ethernet132|2": { "scheduler": "scheduler.0" }, - "Ethernet80|2": { + "dut-lc3|Asic0|Ethernet128|2": { "scheduler": "scheduler.0" }, - "Ethernet84|2": { + "dut-lc3|Asic0|Ethernet56|2": { "scheduler": "scheduler.0" }, - "Ethernet88|2": { + "dut-lc5|Asic0|Ethernet20|2": { "scheduler": "scheduler.0" }, - "Ethernet92|2": { + "dut-lc3|Asic0|Ethernet52|2": { "scheduler": "scheduler.0" }, - "Ethernet96|2": { + "dut-lc3|Asic0|Ethernet108|2": { "scheduler": "scheduler.0" }, - "Ethernet100|2": { + "dut-lc5|Asic0|Ethernet68|2": { "scheduler": "scheduler.0" }, - "Ethernet104|2": { + "dut-lc3|Asic0|Ethernet100|2": { "scheduler": "scheduler.0" }, - "Ethernet108|2": { + "dut-lc5|Asic0|Ethernet176|2": { "scheduler": "scheduler.0" }, - "Ethernet112|2": { + "dut-lc5|Asic0|Ethernet64|2": { "scheduler": "scheduler.0" }, - "Ethernet116|2": { + "dut-lc3|Asic0|Ethernet104|2": { "scheduler": "scheduler.0" }, - "Ethernet120|2": { + "dut-lc5|Asic0|Ethernet60|2": { "scheduler": "scheduler.0" }, - "Ethernet124|2": { + "dut-lc3|Asic0|Ethernet180|2": { "scheduler": "scheduler.0" }, - "Ethernet128|2": { + "dut-lc5|Asic0|Ethernet144|2": { "scheduler": "scheduler.0" }, - "Ethernet132|2": { + "dut-lc3|Asic0|Ethernet184|2": { "scheduler": "scheduler.0" }, - "Ethernet136|2": { + "dut-lc5|Asic0|Ethernet140|2": { "scheduler": "scheduler.0" }, - "Ethernet140|2": { + "dut-lc3|Asic0|Ethernet188|2": { "scheduler": "scheduler.0" }, - "Ethernet144|2": { + "dut-lc5|Asic0|Ethernet148|2": { "scheduler": "scheduler.0" }, - "Ethernet148|2": { + "dut-lc4|Asic0|Ethernet128|2": { "scheduler": "scheduler.0" }, - "Ethernet152|2": { + "dut-lc4|Asic0|Ethernet4|2": { "scheduler": "scheduler.0" }, - "Ethernet156|2": { + "dut-lc3|Asic0|Ethernet44|2": { "scheduler": "scheduler.0" }, - "Ethernet164|2": { + "dut-lc4|Asic0|Ethernet0|2": { "scheduler": "scheduler.0" }, - "Ethernet176|2": { + "dut-lc3|Asic0|Ethernet40|2": { "scheduler": "scheduler.0" }, - "Ethernet180|2": { + "dut-lc4|Asic0|Ethernet120|2": { "scheduler": "scheduler.0" }, - "Ethernet184|2": { + "dut-lc4|Asic0|Ethernet124|2": { "scheduler": "scheduler.0" }, - "Ethernet188|2": { + "dut-lc4|Asic0|Ethernet8|2": { "scheduler": "scheduler.0" }, - "Ethernet0|5": { + "dut-lc3|Asic0|Ethernet48|2": { "scheduler": "scheduler.0" }, - "Ethernet4|5": { + "dut-lc5|Asic0|Ethernet52|5": { "scheduler": "scheduler.0" }, - "Ethernet8|5": { + "dut-lc5|Asic0|Ethernet56|5": { "scheduler": "scheduler.0" }, - "Ethernet12|5": { + "dut-lc3|Asic0|Ethernet72|5": { "scheduler": "scheduler.0" }, - "Ethernet16|5": { + "dut-lc3|Asic0|Ethernet76|5": { "scheduler": "scheduler.0" }, - "Ethernet20|5": { + "dut-lc4|Asic0|Ethernet84|5": { "scheduler": "scheduler.0" }, - "Ethernet24|5": { + "dut-lc4|Asic0|Ethernet80|5": { "scheduler": "scheduler.0" }, - "Ethernet28|5": { + "dut-lc4|Asic0|Ethernet88|5": { "scheduler": "scheduler.0" }, - "Ethernet32|5": { + "dut-lc3|Asic0|Ethernet4|5": { "scheduler": "scheduler.0" }, - "Ethernet36|5": { + "dut-lc4|Asic0|Ethernet56|5": { "scheduler": "scheduler.0" }, - "Ethernet40|5": { + "dut-lc3|Asic0|Ethernet0|5": { "scheduler": "scheduler.0" }, - "Ethernet44|5": { + "dut-lc3|Asic0|Ethernet8|5": { "scheduler": "scheduler.0" }, - "Ethernet48|5": { + "dut-lc3|Asic0|Ethernet112|5": { "scheduler": "scheduler.0" }, - "Ethernet52|5": { + "dut-lc4|Asic0|Ethernet52|5": { "scheduler": "scheduler.0" }, - "Ethernet56|5": { + "dut-lc4|Asic0|Ethernet152|5": { "scheduler": "scheduler.0" }, - "Ethernet60|5": { + "dut-lc5|Asic0|Ethernet44|5": { "scheduler": "scheduler.0" }, - "Ethernet64|5": { + "dut-lc4|Asic0|Ethernet12|5": { "scheduler": "scheduler.0" }, - "Ethernet68|5": { + "dut-lc3|Asic0|Ethernet68|5": { "scheduler": "scheduler.0" }, - "Ethernet72|5": { + "dut-lc4|Asic0|Ethernet16|5": { "scheduler": "scheduler.0" }, - "Ethernet76|5": { + "dut-lc3|Asic0|Ethernet64|5": { "scheduler": "scheduler.0" }, - "Ethernet80|5": { + "dut-lc3|Asic0|Ethernet124|5": { "scheduler": "scheduler.0" }, - "Ethernet84|5": { + "dut-lc3|Asic0|Ethernet60|5": { "scheduler": "scheduler.0" }, - "Ethernet88|5": { + "dut-lc3|Asic0|Ethernet116|5": { "scheduler": "scheduler.0" }, - "Ethernet92|5": { + "dut-lc3|Asic0|Ethernet120|5": { "scheduler": "scheduler.0" }, - "Ethernet96|5": { + "dut-lc4|Asic0|Ethernet104|5": { "scheduler": "scheduler.0" }, - "Ethernet100|5": { + "dut-lc5|Asic0|Ethernet152|5": { "scheduler": "scheduler.0" }, - "Ethernet104|5": { + "dut-lc4|Asic0|Ethernet188|5": { "scheduler": "scheduler.0" }, - "Ethernet108|5": { + "dut-lc5|Asic0|Ethernet156|5": { "scheduler": "scheduler.0" }, - "Ethernet112|5": { + "dut-lc4|Asic0|Ethernet148|5": { "scheduler": "scheduler.0" }, - "Ethernet116|5": { + "dut-lc4|Asic0|Ethernet140|5": { "scheduler": "scheduler.0" }, - "Ethernet120|5": { + "dut-lc4|Asic0|Ethernet64|5": { "scheduler": "scheduler.0" }, - "Ethernet124|5": { + "dut-lc3|Asic0|Ethernet92|5": { "scheduler": "scheduler.0" }, - "Ethernet128|5": { + "dut-lc4|Asic0|Ethernet60|5": { "scheduler": "scheduler.0" }, - "Ethernet132|5": { + "dut-lc3|Asic0|Ethernet96|5": { "scheduler": "scheduler.0" }, - "Ethernet136|5": { + "dut-lc3|Asic0|Ethernet144|5": { "scheduler": "scheduler.0" }, - "Ethernet140|5": { + "dut-lc4|Asic0|Ethernet68|5": { "scheduler": "scheduler.0" }, - "Ethernet144|5": { + "dut-lc4|Asic0|Ethernet40|5": { "scheduler": "scheduler.0" }, - "Ethernet148|5": { + "dut-lc4|Asic0|Ethernet72|5": { "scheduler": "scheduler.0" }, - "Ethernet152|5": { + "dut-lc5|Asic0|Ethernet128|5": { "scheduler": "scheduler.0" }, - "Ethernet156|5": { + "dut-lc5|Asic0|Ethernet124|5": { "scheduler": "scheduler.0" }, - "Ethernet164|5": { + "dut-lc4|Asic0|Ethernet92|5": { "scheduler": "scheduler.0" }, - "Ethernet176|5": { + "dut-lc5|Asic0|Ethernet120|5": { "scheduler": "scheduler.0" }, - "Ethernet180|5": { + "dut-lc4|Asic0|Ethernet96|5": { "scheduler": "scheduler.0" }, - "Ethernet184|5": { + "dut-lc4|Asic0|Ethernet172|5": { "scheduler": "scheduler.0" }, - "Ethernet188|5": { + "dut-lc5|Asic0|Ethernet32|5": { "scheduler": "scheduler.0" }, - "Ethernet0|6": { + "dut-lc4|Asic0|Ethernet176|5": { "scheduler": "scheduler.0" }, - "Ethernet4|6": { + "dut-lc5|Asic0|Ethernet36|5": { "scheduler": "scheduler.0" }, - "Ethernet8|6": { + "dut-lc4|Asic0|Ethernet32|5": { "scheduler": "scheduler.0" }, - "Ethernet12|6": { + "dut-lc3|Asic0|Ethernet12|5": { "scheduler": "scheduler.0" }, - "Ethernet16|6": { + "dut-lc3|Asic0|Ethernet16|5": { "scheduler": "scheduler.0" }, - "Ethernet20|6": { + "dut-lc4|Asic0|Ethernet76|5": { "scheduler": "scheduler.0" }, - "Ethernet24|6": { + "dut-lc3|Asic0|Ethernet80|5": { "scheduler": "scheduler.0" }, - "Ethernet28|6": { + "dut-lc3|Asic0|Ethernet140|5": { "scheduler": "scheduler.0" }, - "Ethernet32|6": { + "dut-lc3|Asic0|Ethernet84|5": { "scheduler": "scheduler.0" }, - "Ethernet36|6": { + "dut-lc3|Asic0|Ethernet88|5": { "scheduler": "scheduler.0" }, - "Ethernet40|6": { + "dut-lc3|Asic0|Ethernet148|5": { "scheduler": "scheduler.0" }, - "Ethernet44|6": { + "dut-lc4|Asic0|Ethernet100|5": { "scheduler": "scheduler.0" }, - "Ethernet48|6": { + "dut-lc4|Asic0|Ethernet36|5": { "scheduler": "scheduler.0" }, - "Ethernet52|6": { + "dut-lc4|Asic0|Ethernet112|5": { "scheduler": "scheduler.0" }, - "Ethernet56|6": { + "dut-lc5|Asic0|Ethernet180|5": { "scheduler": "scheduler.0" }, - "Ethernet60|6": { + "dut-lc4|Asic0|Ethernet144|5": { "scheduler": "scheduler.0" }, - "Ethernet64|6": { + "dut-lc5|Asic0|Ethernet184|5": { "scheduler": "scheduler.0" }, - "Ethernet68|6": { + "dut-lc5|Asic0|Ethernet136|5": { "scheduler": "scheduler.0" }, - "Ethernet72|6": { + "dut-lc5|Asic0|Ethernet104|5": { "scheduler": "scheduler.0" }, - "Ethernet76|6": { + "dut-lc5|Asic0|Ethernet132|5": { "scheduler": "scheduler.0" }, - "Ethernet80|6": { + "dut-lc4|Asic0|Ethernet164|5": { "scheduler": "scheduler.0" }, - "Ethernet84|6": { + "dut-lc5|Asic0|Ethernet188|5": { "scheduler": "scheduler.0" }, - "Ethernet88|6": { + "dut-lc4|Asic0|Ethernet160|5": { "scheduler": "scheduler.0" }, - "Ethernet92|6": { + "dut-lc5|Asic0|Ethernet24|5": { "scheduler": "scheduler.0" }, - "Ethernet96|6": { + "dut-lc5|Asic0|Ethernet28|5": { "scheduler": "scheduler.0" }, - "Ethernet100|6": { + "dut-lc4|Asic0|Ethernet168|5": { "scheduler": "scheduler.0" }, - "Ethernet104|6": { + "dut-lc3|Asic0|Ethernet156|5": { "scheduler": "scheduler.0" }, - "Ethernet108|6": { + "dut-lc3|Asic0|Ethernet152|5": { "scheduler": "scheduler.0" }, - "Ethernet112|6": { + "dut-lc3|Asic0|Ethernet132|5": { "scheduler": "scheduler.0" }, - "Ethernet116|6": { + "dut-lc4|Asic0|Ethernet48|5": { "scheduler": "scheduler.0" }, - "Ethernet120|6": { + "dut-lc4|Asic0|Ethernet180|5": { "scheduler": "scheduler.0" }, - "Ethernet124|6": { + "dut-lc4|Asic0|Ethernet44|5": { "scheduler": "scheduler.0" }, - "Ethernet128|6": { + "dut-lc5|Asic0|Ethernet100|5": { "scheduler": "scheduler.0" }, - "Ethernet132|6": { + "dut-lc3|Asic0|Ethernet136|5": { "scheduler": "scheduler.0" }, - "Ethernet136|6": { + "dut-lc4|Asic0|Ethernet116|5": { "scheduler": "scheduler.0" }, - "Ethernet140|6": { + "dut-lc5|Asic0|Ethernet96|5": { "scheduler": "scheduler.0" }, - "Ethernet144|6": { + "dut-lc5|Asic0|Ethernet108|5": { "scheduler": "scheduler.0" }, - "Ethernet148|6": { + "dut-lc5|Asic0|Ethernet92|5": { "scheduler": "scheduler.0" }, - "Ethernet152|6": { + "dut-lc5|Asic0|Ethernet16|5": { "scheduler": "scheduler.0" }, - "Ethernet156|6": { + "dut-lc5|Asic0|Ethernet12|5": { "scheduler": "scheduler.0" }, - "Ethernet164|6": { + "dut-lc3|Asic0|Ethernet36|5": { "scheduler": "scheduler.0" }, - "Ethernet176|6": { + "dut-lc3|Asic0|Ethernet32|5": { "scheduler": "scheduler.0" }, - "Ethernet180|6": { + "dut-lc5|Asic0|Ethernet48|5": { "scheduler": "scheduler.0" }, - "Ethernet184|6": { + "dut-lc5|Asic0|Ethernet160|5": { "scheduler": "scheduler.0" }, - "Ethernet188|6": { + "dut-lc3|Asic0|Ethernet168|5": { "scheduler": "scheduler.0" - } + }, + "dut-lc5|Asic0|Ethernet164|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet168|5": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet160|5": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet164|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet80|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet116|5": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet156|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet84|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet112|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet88|5": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet108|5": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet20|5": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet24|5": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet28|5": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet28|5": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet20|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet76|5": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet24|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet72|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet172|5": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet184|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet8|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet4|5": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet176|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet0|5": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet172|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet40|5": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet136|5": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet132|5": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet128|5": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet56|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet20|5": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet52|5": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet108|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet68|5": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet100|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet176|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet64|5": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet104|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet60|5": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet180|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet144|5": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet184|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet140|5": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet188|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet148|5": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet128|5": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet4|5": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet44|5": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet0|5": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet40|5": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet120|5": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet124|5": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet8|5": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet48|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet52|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet56|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet72|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet76|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet84|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet80|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet88|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet4|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet56|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet0|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet8|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet112|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet52|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet152|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet44|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet12|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet68|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet16|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet64|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet124|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet60|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet116|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet120|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet104|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet152|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet188|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet156|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet148|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet140|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet64|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet92|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet60|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet96|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet144|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet68|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet40|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet72|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet128|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet124|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet92|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet120|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet96|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet172|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet32|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet176|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet36|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet32|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet12|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet16|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet76|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet80|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet140|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet84|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet88|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet148|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet100|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet36|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet112|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet180|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet144|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet184|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet136|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet104|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet132|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet164|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet188|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet160|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet24|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet28|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet168|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet156|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet152|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet132|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet48|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet180|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet44|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet100|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet136|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet116|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet96|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet108|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet92|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet16|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet12|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet36|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet32|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet48|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet160|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet168|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet164|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet168|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet160|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet164|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet80|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet116|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet156|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet84|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet112|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet88|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet108|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet20|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet24|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet28|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet28|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet20|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet76|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet24|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet72|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet172|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet184|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet8|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet4|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet176|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet0|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet172|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet40|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet136|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet132|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet128|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet56|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet20|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet52|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet108|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet68|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet100|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet176|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet64|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet104|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet60|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet180|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet144|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet184|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet140|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet188|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet148|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet128|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet4|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet44|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet0|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet40|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet120|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet124|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet8|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet48|6": { + "scheduler": "scheduler.0" + } } } diff --git a/src/sonic-config-engine/tests/sample_output/py2/qos-arista7800r3a-36dm2-c36-lc.json b/src/sonic-config-engine/tests/sample_output/py2/qos-arista7800r3a-36dm2-c36-lc.json index cf6fbf64f8db..1007b272c466 100644 --- a/src/sonic-config-engine/tests/sample_output/py2/qos-arista7800r3a-36dm2-c36-lc.json +++ b/src/sonic-config-engine/tests/sample_output/py2/qos-arista7800r3a-36dm2-c36-lc.json @@ -280,418 +280,3040 @@ } }, "QUEUE": { - "Ethernet0|3": { - "scheduler" : "scheduler.1", + "str2-7804-lc3-1|Asic0|Ethernet0|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet0|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet0|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet0|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet0|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet0|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet0|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet4|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet4|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet4|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet4|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet4|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet4|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet4|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet8|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet8|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet8|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet8|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet8|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet8|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet8|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet12|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet12|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet12|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet12|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet12|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet12|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet12|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet16|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet16|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet16|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet16|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet16|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet16|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet16|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet20|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet20|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet20|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet20|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet20|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet20|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet20|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet24|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet24|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet24|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet24|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet24|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet24|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet24|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet28|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet28|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet28|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet28|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet28|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet28|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet28|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet32|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet32|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet32|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet32|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet32|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet32|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet32|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet36|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet36|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet36|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet36|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet36|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet36|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet36|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet40|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet40|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet40|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet40|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet40|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet40|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet40|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet44|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet44|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet44|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet44|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet44|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet44|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet44|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet48|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet48|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet48|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet48|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet48|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet48|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet48|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet52|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet52|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet52|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet52|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet52|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet52|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet52|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet56|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet56|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet56|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet56|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet56|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet56|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet56|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet60|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet60|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet60|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet60|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet60|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet60|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet60|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet64|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet64|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet64|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet64|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet64|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet64|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet64|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet68|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet68|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet68|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet68|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet68|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet68|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet68|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet72|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet72|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet72|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet72|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet72|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet72|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet72|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet76|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet76|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet76|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet76|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet76|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet76|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet76|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet80|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet80|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet80|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet80|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet80|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet80|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet80|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet84|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet84|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet84|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet84|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet84|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet84|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet84|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet88|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet88|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet88|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet88|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet88|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet88|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet88|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet92|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet92|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet92|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet92|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet92|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet92|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet92|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet96|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet96|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet96|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet96|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet96|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet96|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet96|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet100|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet100|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet100|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet100|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet100|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet100|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet100|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet104|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet104|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet104|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet104|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet104|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet104|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet104|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet108|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet108|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet108|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet108|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet108|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet108|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet108|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet112|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet112|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet112|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet112|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet112|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet112|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet112|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet116|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet116|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet116|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet116|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet116|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet116|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet116|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet120|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet120|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet120|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet120|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet120|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet120|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet120|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet124|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet124|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet124|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet124|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet124|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet124|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet124|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet128|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet128|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet128|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet128|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet128|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet128|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet128|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet132|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet132|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet132|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet132|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet132|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet132|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet132|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet136|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet136|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet136|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet136|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet136|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet136|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet136|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet140|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet140|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet140|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet140|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet140|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet140|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet140|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet144|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet144|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet144|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet144|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet144|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet144|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet144|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet148|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet148|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet148|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet148|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet148|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet148|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet148|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet152|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet152|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet152|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet152|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet152|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet152|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet152|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet156|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet156|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet156|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet156|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet156|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet156|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet156|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet160|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet160|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet160|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet160|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet160|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet160|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet160|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet164|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet164|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet164|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet164|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet164|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet164|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet164|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet168|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet168|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet168|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet168|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet168|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet168|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet168|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet172|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet172|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet172|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet172|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet172|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet172|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet172|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet176|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet176|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet176|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet176|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet176|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet176|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet176|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet180|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet180|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet180|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet180|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet180|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet180|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet180|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet184|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet184|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet184|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet184|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet184|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet184|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet184|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet188|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet188|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet188|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet188|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet188|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet188|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet188|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet0|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet0|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet0|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet0|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet0|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet0|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet0|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet8|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet8|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet8|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet8|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet8|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet8|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet8|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet16|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet16|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet16|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet16|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet16|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet16|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet16|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet24|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet24|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet24|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet24|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet24|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet24|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet24|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet32|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet32|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet32|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet32|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet32|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet32|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet32|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet40|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet40|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet40|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet40|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet40|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet40|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet40|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet48|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet48|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet48|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet48|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet48|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet48|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet48|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet56|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet56|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet56|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet56|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet56|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet56|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet56|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet64|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet64|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet64|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet64|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet64|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet64|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet64|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet72|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet72|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet72|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet72|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet72|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet72|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet72|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet80|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet80|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet80|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet80|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet80|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet80|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet80|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet88|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet88|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet88|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet88|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet88|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet88|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet88|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet96|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet96|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet96|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet96|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet96|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet96|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet96|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet104|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet104|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet104|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet104|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet104|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet104|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet104|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet112|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet112|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet112|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet112|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet112|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet112|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet112|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet120|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet120|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet120|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet120|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet120|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet120|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet120|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet128|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet128|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet128|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet128|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet128|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet128|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet128|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet136|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet136|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet136|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet136|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet136|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet136|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet136|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet144|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet144|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet144|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet144|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet144|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet144|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet144|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet152|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet152|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet152|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet152|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet152|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet152|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet152|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet160|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet160|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet160|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet160|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet160|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet160|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet160|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet168|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet168|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet168|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet168|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet168|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet168|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet168|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet176|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet176|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet176|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet176|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet176|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet176|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet176|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet184|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet184|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet184|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet184|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet184|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet184|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet184|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet192|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet192|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet192|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet192|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet192|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet192|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet192|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet200|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet200|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet200|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet200|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet200|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet200|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet200|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet208|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet208|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet208|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet208|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet208|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet208|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet208|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet216|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet216|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet216|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet216|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet216|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet216|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet216|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet224|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet224|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet224|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet224|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet224|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet224|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet224|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet232|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet232|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet232|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet232|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet232|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet232|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet232|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet240|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet240|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet240|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet240|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet240|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet240|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet240|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet248|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet248|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet248|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet248|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet248|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet248|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet248|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet256|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet256|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet256|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet256|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet256|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet256|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet256|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet264|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet264|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet264|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet264|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet264|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet264|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet264|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet272|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet272|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet272|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet272|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet272|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet272|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet272|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet280|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet280|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet280|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet280|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet280|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet280|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet280|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet0|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet0|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet0|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet0|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet0|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet0|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet0|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet4|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet4|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet4|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet4|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet4|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet4|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet4|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet8|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet8|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet8|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet8|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet8|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet8|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet8|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet12|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet12|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet12|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet12|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet12|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet12|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet12|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet16|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet16|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet16|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet16|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet16|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet16|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet16|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet20|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet20|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet20|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet20|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet20|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet20|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet20|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet24|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet24|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet24|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet24|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet24|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet24|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet24|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet28|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet28|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet28|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet28|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet28|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet28|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet28|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet32|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet32|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet32|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet32|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet32|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet32|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet32|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet36|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet36|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet36|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet36|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet36|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet36|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet36|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet40|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet40|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet40|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet40|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet40|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet40|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet40|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet44|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet44|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet44|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet44|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet44|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet44|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet44|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet48|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet48|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet48|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet48|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet8|3": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet48|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet16|3": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet48|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet48|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet52|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet52|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet52|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet52|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet24|3": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet52|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet32|3": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet52|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet52|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet56|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet56|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet56|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet56|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet40|3": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet56|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet48|3": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet56|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet56|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet60|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet60|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet60|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet60|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet56|3": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet60|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet64|3": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet60|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet60|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet64|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet64|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet64|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet64|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet72|3": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet64|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet80|3": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet64|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet64|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet68|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet68|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet68|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet68|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet88|3": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet68|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet96|3": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet68|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet68|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet72|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet72|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet72|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet72|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet104|3": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet72|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet112|3": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet72|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet72|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet76|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet76|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet76|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet76|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet120|3": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet76|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet128|3": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet76|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet76|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet80|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet80|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet80|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet80|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet136|3": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet80|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet0|4": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet80|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet80|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet84|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet84|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet84|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet84|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet8|4": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet84|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet16|4": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet84|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet84|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet88|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet88|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet88|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet88|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet24|4": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet88|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet32|4": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet88|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet88|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet92|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet92|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet92|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet92|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet40|4": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet92|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet48|4": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet92|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet92|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet96|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet96|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet96|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet96|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet56|4": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet96|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet64|4": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet96|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet96|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet100|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet100|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet100|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet100|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet72|4": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet100|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet80|4": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet100|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet100|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet104|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet104|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet104|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet104|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet88|4": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet104|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet96|4": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet104|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet104|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet108|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet108|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet108|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet108|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet104|4": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet108|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet112|4": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet108|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet108|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet112|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet112|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet112|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet112|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet120|4": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet112|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet128|4": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet112|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet112|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet116|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet116|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet116|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet116|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet136|4": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet116|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet0|0": { + "str2-7804-lc7-1|Asic0|Ethernet116|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet116|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet120|0": { "scheduler": "scheduler.0" }, - "Ethernet8|0": { + "str2-7804-lc7-1|Asic0|Ethernet120|1": { "scheduler": "scheduler.0" }, - "Ethernet16|0": { + "str2-7804-lc7-1|Asic0|Ethernet120|2": { "scheduler": "scheduler.0" }, - "Ethernet24|0": { + "str2-7804-lc7-1|Asic0|Ethernet120|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet120|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet120|5": { "scheduler": "scheduler.0" }, - "Ethernet32|0": { + "str2-7804-lc7-1|Asic0|Ethernet120|6": { "scheduler": "scheduler.0" }, - "Ethernet40|0": { + "str2-7804-lc7-1|Asic0|Ethernet124|0": { "scheduler": "scheduler.0" }, - "Ethernet48|0": { + "str2-7804-lc7-1|Asic0|Ethernet124|1": { "scheduler": "scheduler.0" }, - "Ethernet56|0": { + "str2-7804-lc7-1|Asic0|Ethernet124|2": { "scheduler": "scheduler.0" }, - "Ethernet64|0": { + "str2-7804-lc7-1|Asic0|Ethernet124|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet124|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet124|5": { "scheduler": "scheduler.0" }, - "Ethernet72|0": { + "str2-7804-lc7-1|Asic0|Ethernet124|6": { "scheduler": "scheduler.0" }, - "Ethernet80|0": { + "str2-7804-lc7-1|Asic0|Ethernet128|0": { "scheduler": "scheduler.0" }, - "Ethernet88|0": { + "str2-7804-lc7-1|Asic0|Ethernet128|1": { "scheduler": "scheduler.0" }, - "Ethernet96|0": { + "str2-7804-lc7-1|Asic0|Ethernet128|2": { "scheduler": "scheduler.0" }, - "Ethernet104|0": { + "str2-7804-lc7-1|Asic0|Ethernet128|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet128|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet128|5": { "scheduler": "scheduler.0" }, - "Ethernet112|0": { + "str2-7804-lc7-1|Asic0|Ethernet128|6": { "scheduler": "scheduler.0" }, - "Ethernet120|0": { + "str2-7804-lc7-1|Asic0|Ethernet132|0": { "scheduler": "scheduler.0" }, - "Ethernet128|0": { + "str2-7804-lc7-1|Asic0|Ethernet132|1": { "scheduler": "scheduler.0" }, - "Ethernet136|0": { + "str2-7804-lc7-1|Asic0|Ethernet132|2": { "scheduler": "scheduler.0" }, - "Ethernet0|1": { + "str2-7804-lc7-1|Asic0|Ethernet132|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet132|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet132|5": { "scheduler": "scheduler.0" }, - "Ethernet8|1": { + "str2-7804-lc7-1|Asic0|Ethernet132|6": { "scheduler": "scheduler.0" }, - "Ethernet16|1": { + "str2-7804-lc7-1|Asic0|Ethernet136|0": { "scheduler": "scheduler.0" }, - "Ethernet24|1": { + "str2-7804-lc7-1|Asic0|Ethernet136|1": { "scheduler": "scheduler.0" }, - "Ethernet32|1": { + "str2-7804-lc7-1|Asic0|Ethernet136|2": { "scheduler": "scheduler.0" }, - "Ethernet40|1": { + "str2-7804-lc7-1|Asic0|Ethernet136|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet136|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet136|5": { "scheduler": "scheduler.0" }, - "Ethernet48|1": { + "str2-7804-lc7-1|Asic0|Ethernet136|6": { "scheduler": "scheduler.0" }, - "Ethernet56|1": { + "str2-7804-lc7-1|Asic0|Ethernet140|0": { "scheduler": "scheduler.0" }, - "Ethernet64|1": { + "str2-7804-lc7-1|Asic0|Ethernet140|1": { "scheduler": "scheduler.0" }, - "Ethernet72|1": { + "str2-7804-lc7-1|Asic0|Ethernet140|2": { "scheduler": "scheduler.0" }, - "Ethernet80|1": { + "str2-7804-lc7-1|Asic0|Ethernet140|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet140|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet140|5": { "scheduler": "scheduler.0" }, - "Ethernet88|1": { + "str2-7804-lc7-1|Asic0|Ethernet140|6": { "scheduler": "scheduler.0" }, - "Ethernet96|1": { + "str2-7804-lc7-1|Asic0|Ethernet144|0": { "scheduler": "scheduler.0" }, - "Ethernet104|1": { + "str2-7804-lc7-1|Asic0|Ethernet144|1": { "scheduler": "scheduler.0" }, - "Ethernet112|1": { + "str2-7804-lc7-1|Asic0|Ethernet144|2": { "scheduler": "scheduler.0" }, - "Ethernet120|1": { + "str2-7804-lc7-1|Asic0|Ethernet144|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet144|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet144|5": { "scheduler": "scheduler.0" }, - "Ethernet128|1": { + "str2-7804-lc7-1|Asic0|Ethernet144|6": { "scheduler": "scheduler.0" }, - "Ethernet136|1": { + "str2-7804-lc7-1|Asic0|Ethernet148|0": { "scheduler": "scheduler.0" }, - "Ethernet0|2": { + "str2-7804-lc7-1|Asic0|Ethernet148|1": { "scheduler": "scheduler.0" }, - "Ethernet8|2": { + "str2-7804-lc7-1|Asic0|Ethernet148|2": { "scheduler": "scheduler.0" }, - "Ethernet16|2": { + "str2-7804-lc7-1|Asic0|Ethernet148|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet148|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet148|5": { "scheduler": "scheduler.0" }, - "Ethernet24|2": { + "str2-7804-lc7-1|Asic0|Ethernet148|6": { "scheduler": "scheduler.0" }, - "Ethernet32|2": { + "str2-7804-lc7-1|Asic0|Ethernet152|0": { "scheduler": "scheduler.0" }, - "Ethernet40|2": { + "str2-7804-lc7-1|Asic0|Ethernet152|1": { "scheduler": "scheduler.0" }, - "Ethernet48|2": { + "str2-7804-lc7-1|Asic0|Ethernet152|2": { "scheduler": "scheduler.0" }, - "Ethernet56|2": { + "str2-7804-lc7-1|Asic0|Ethernet152|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet152|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet152|5": { "scheduler": "scheduler.0" }, - "Ethernet64|2": { + "str2-7804-lc7-1|Asic0|Ethernet152|6": { "scheduler": "scheduler.0" }, - "Ethernet72|2": { + "str2-7804-lc7-1|Asic0|Ethernet156|0": { "scheduler": "scheduler.0" }, - "Ethernet80|2": { + "str2-7804-lc7-1|Asic0|Ethernet156|1": { "scheduler": "scheduler.0" }, - "Ethernet88|2": { + "str2-7804-lc7-1|Asic0|Ethernet156|2": { "scheduler": "scheduler.0" }, - "Ethernet96|2": { + "str2-7804-lc7-1|Asic0|Ethernet156|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet156|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet156|5": { "scheduler": "scheduler.0" }, - "Ethernet104|2": { + "str2-7804-lc7-1|Asic0|Ethernet156|6": { "scheduler": "scheduler.0" }, - "Ethernet112|2": { + "str2-7804-lc7-1|Asic0|Ethernet160|0": { "scheduler": "scheduler.0" }, - "Ethernet120|2": { + "str2-7804-lc7-1|Asic0|Ethernet160|1": { "scheduler": "scheduler.0" }, - "Ethernet128|2": { + "str2-7804-lc7-1|Asic0|Ethernet160|2": { "scheduler": "scheduler.0" }, - "Ethernet136|2": { + "str2-7804-lc7-1|Asic0|Ethernet160|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet160|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet160|5": { "scheduler": "scheduler.0" }, - "Ethernet0|5": { + "str2-7804-lc7-1|Asic0|Ethernet160|6": { "scheduler": "scheduler.0" }, - "Ethernet8|5": { + "str2-7804-lc7-1|Asic0|Ethernet164|0": { "scheduler": "scheduler.0" }, - "Ethernet16|5": { + "str2-7804-lc7-1|Asic0|Ethernet164|1": { "scheduler": "scheduler.0" }, - "Ethernet24|5": { + "str2-7804-lc7-1|Asic0|Ethernet164|2": { "scheduler": "scheduler.0" }, - "Ethernet32|5": { + "str2-7804-lc7-1|Asic0|Ethernet164|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet164|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet164|5": { "scheduler": "scheduler.0" }, - "Ethernet40|5": { + "str2-7804-lc7-1|Asic0|Ethernet164|6": { "scheduler": "scheduler.0" }, - "Ethernet48|5": { + "str2-7804-lc7-1|Asic0|Ethernet168|0": { "scheduler": "scheduler.0" }, - "Ethernet56|5": { + "str2-7804-lc7-1|Asic0|Ethernet168|1": { "scheduler": "scheduler.0" }, - "Ethernet64|5": { + "str2-7804-lc7-1|Asic0|Ethernet168|2": { "scheduler": "scheduler.0" }, - "Ethernet72|5": { + "str2-7804-lc7-1|Asic0|Ethernet168|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet168|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet168|5": { "scheduler": "scheduler.0" }, - "Ethernet80|5": { + "str2-7804-lc7-1|Asic0|Ethernet168|6": { "scheduler": "scheduler.0" }, - "Ethernet88|5": { + "str2-7804-lc7-1|Asic0|Ethernet172|0": { "scheduler": "scheduler.0" }, - "Ethernet96|5": { + "str2-7804-lc7-1|Asic0|Ethernet172|1": { "scheduler": "scheduler.0" }, - "Ethernet104|5": { + "str2-7804-lc7-1|Asic0|Ethernet172|2": { "scheduler": "scheduler.0" }, - "Ethernet112|5": { + "str2-7804-lc7-1|Asic0|Ethernet172|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet172|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet172|5": { "scheduler": "scheduler.0" }, - "Ethernet120|5": { + "str2-7804-lc7-1|Asic0|Ethernet172|6": { "scheduler": "scheduler.0" }, - "Ethernet128|5": { + "str2-7804-lc7-1|Asic0|Ethernet176|0": { "scheduler": "scheduler.0" }, - "Ethernet136|5": { + "str2-7804-lc7-1|Asic0|Ethernet176|1": { "scheduler": "scheduler.0" }, - "Ethernet0|6": { + "str2-7804-lc7-1|Asic0|Ethernet176|2": { "scheduler": "scheduler.0" }, - "Ethernet8|6": { + "str2-7804-lc7-1|Asic0|Ethernet176|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet176|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet176|5": { "scheduler": "scheduler.0" }, - "Ethernet16|6": { + "str2-7804-lc7-1|Asic0|Ethernet176|6": { "scheduler": "scheduler.0" }, - "Ethernet24|6": { + "str2-7804-lc7-1|Asic0|Ethernet180|0": { "scheduler": "scheduler.0" }, - "Ethernet32|6": { + "str2-7804-lc7-1|Asic0|Ethernet180|1": { "scheduler": "scheduler.0" }, - "Ethernet40|6": { + "str2-7804-lc7-1|Asic0|Ethernet180|2": { "scheduler": "scheduler.0" }, - "Ethernet48|6": { + "str2-7804-lc7-1|Asic0|Ethernet180|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet180|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet180|5": { "scheduler": "scheduler.0" }, - "Ethernet56|6": { + "str2-7804-lc7-1|Asic0|Ethernet180|6": { "scheduler": "scheduler.0" }, - "Ethernet64|6": { + "str2-7804-lc7-1|Asic0|Ethernet184|0": { "scheduler": "scheduler.0" }, - "Ethernet72|6": { + "str2-7804-lc7-1|Asic0|Ethernet184|1": { "scheduler": "scheduler.0" }, - "Ethernet80|6": { + "str2-7804-lc7-1|Asic0|Ethernet184|2": { "scheduler": "scheduler.0" }, - "Ethernet88|6": { + "str2-7804-lc7-1|Asic0|Ethernet184|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet184|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet184|5": { "scheduler": "scheduler.0" }, - "Ethernet96|6": { + "str2-7804-lc7-1|Asic0|Ethernet184|6": { "scheduler": "scheduler.0" }, - "Ethernet104|6": { + "str2-7804-lc7-1|Asic0|Ethernet188|0": { "scheduler": "scheduler.0" }, - "Ethernet112|6": { + "str2-7804-lc7-1|Asic0|Ethernet188|1": { "scheduler": "scheduler.0" }, - "Ethernet120|6": { + "str2-7804-lc7-1|Asic0|Ethernet188|2": { "scheduler": "scheduler.0" }, - "Ethernet128|6": { + "str2-7804-lc7-1|Asic0|Ethernet188|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet188|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet188|5": { "scheduler": "scheduler.0" }, - "Ethernet136|6": { + "str2-7804-lc7-1|Asic0|Ethernet188|6": { "scheduler": "scheduler.0" } } diff --git a/src/sonic-config-engine/tests/sample_output/py2/qos-arista7800r3a-36dm2-d36-lc.json b/src/sonic-config-engine/tests/sample_output/py2/qos-arista7800r3a-36dm2-d36-lc.json index cf6fbf64f8db..d66ef4f84a37 100644 --- a/src/sonic-config-engine/tests/sample_output/py2/qos-arista7800r3a-36dm2-d36-lc.json +++ b/src/sonic-config-engine/tests/sample_output/py2/qos-arista7800r3a-36dm2-d36-lc.json @@ -280,419 +280,2910 @@ } }, "QUEUE": { - "Ethernet0|3": { + "str3-7800-lc1-1|Asic0|Ethernet104|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet8|3": { + "str3-7800-lc2-1|Asic0|Ethernet124|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet16|3": { + "str3-7800-lc1-1|Asic0|Ethernet100|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet24|3": { + "str3-7800-lc2-1|Asic0|Ethernet120|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet32|3": { + "str3-7800-lc1-1|Asic0|Ethernet72|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet40|3": { + "str3-7800-lc2-1|Asic0|Ethernet48|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet48|3": { + "str3-7800-lc1-1|Asic0|Ethernet76|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet56|3": { + "str3-7800-lc1-1|Asic0|Ethernet108|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet64|3": { + "str3-7800-lc2-1|Asic0|Ethernet128|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet72|3": { + "str3-7800-lc8-1|asic0|Ethernet32|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet80|3": { + "str3-7800-lc8-1|asic0|Ethernet8|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet88|3": { + "str3-7800-lc1-1|Asic0|Ethernet8|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet96|3": { + "str3-7800-lc2-1|Asic0|Ethernet56|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet104|3": { + "str3-7800-lc8-1|asic0|Ethernet0|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet112|3": { + "str3-7800-lc2-1|Asic0|Ethernet52|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet120|3": { + "str3-7800-lc8-1|asic1|Ethernet200|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet128|3": { + "str3-7800-lc8-1|asic1|Ethernet224|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet136|3": { + "str3-7800-lc8-1|asic1|Ethernet184|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet0|4": { + "str3-7800-lc1-1|Asic0|Ethernet48|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet8|4": { + "str3-7800-lc1-1|Asic0|Ethernet132|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet16|4": { + "str3-7800-lc1-1|Asic0|Ethernet44|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet24|4": { + "str3-7800-lc1-1|Asic0|Ethernet136|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet32|4": { + "str3-7800-lc1-1|Asic0|Ethernet40|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet40|4": { + "str3-7800-lc8-1|asic0|Ethernet24|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet48|4": { + "str3-7800-lc2-1|Asic0|Ethernet44|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet56|4": { + "str3-7800-lc2-1|Asic0|Ethernet40|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet64|4": { + "str3-7800-lc2-1|Asic0|Ethernet12|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet72|4": { + "str3-7800-lc8-1|asic1|Ethernet232|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet80|4": { + "str3-7800-lc2-1|Asic0|Ethernet72|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet88|4": { + "str3-7800-lc1-1|Asic0|Ethernet68|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet96|4": { + "str3-7800-lc1-1|Asic0|Ethernet128|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet104|4": { + "str3-7800-lc2-1|Asic0|Ethernet8|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet112|4": { + "str3-7800-lc2-1|Asic0|Ethernet64|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet120|4": { + "str3-7800-lc8-1|asic0|Ethernet96|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet128|4": { + "str3-7800-lc2-1|Asic0|Ethernet144|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet136|4": { + "str3-7800-lc1-1|Asic0|Ethernet120|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet0|0": { + "str3-7800-lc2-1|Asic0|Ethernet140|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet16|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet140|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet52|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet248|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet56|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet240|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet0|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet60|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet156|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet152|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet68|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet48|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet152|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet156|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet24|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet80|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet20|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet256|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet88|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet28|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet208|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet128|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet92|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet120|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet96|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet148|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet16|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet152|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet56|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet4|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet72|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet148|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet264|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet124|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet160|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet32|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet164|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet168|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet80|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet88|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet132|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet84|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet136|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet88|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet80|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet84|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet0|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet144|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet4|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet176|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet64|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet172|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet272|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet176|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet172|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet36|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet160|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet100|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet96|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet164|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet104|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet92|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet168|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet108|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet36|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet76|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet32|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet176|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet280|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet188|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet104|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet180|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet184|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet12|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet112|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet116|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet116|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet40|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet112|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet60|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet64|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet16|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet28|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet168|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet136|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet20|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet160|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet24|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet144|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet188|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet184|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet180|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet192|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet216|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet112|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet104|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet124|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet100|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet120|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet72|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet48|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet76|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet108|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet128|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet32|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet8|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet8|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet56|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet0|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet52|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet200|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet224|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet184|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet48|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet132|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet44|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet136|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet40|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet24|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet44|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet40|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet12|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet232|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet72|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet68|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet128|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet8|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet64|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet96|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet144|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet120|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet140|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet16|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet140|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet52|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet248|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet56|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet240|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet0|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet60|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet156|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet152|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet68|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet48|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet152|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet156|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet24|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet80|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet20|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet256|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet88|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet28|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet208|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet128|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet92|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet120|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet96|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet148|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet16|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet152|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet56|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet4|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet72|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet148|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet264|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet124|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet160|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet32|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet164|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet168|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet80|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet88|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet132|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet84|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet136|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet88|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet80|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet84|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet0|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet144|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet4|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet176|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet64|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet172|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet272|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet176|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet172|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet36|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet160|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet100|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet96|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet164|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet104|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet92|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet168|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet108|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet36|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet76|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet32|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet176|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet280|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet188|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet104|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet180|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet184|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet12|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet112|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet116|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet116|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet40|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet112|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet60|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet64|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet16|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet28|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet168|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet136|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet20|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet160|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet24|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet144|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet188|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet184|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet180|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet192|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet216|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet112|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet104|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet124|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet100|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet120|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet72|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet48|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet76|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet108|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet128|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet32|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet8|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet8|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet56|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet0|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet52|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet200|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet224|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet184|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet48|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet132|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet44|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet136|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet40|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet24|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet44|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet40|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet12|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet232|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet72|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet68|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet128|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet8|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet64|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet96|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet144|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet120|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet140|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet16|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet140|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet52|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet248|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet56|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet240|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet0|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet60|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet156|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet152|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet68|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet48|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet152|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet156|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet24|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet80|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet20|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet256|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet88|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet28|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet208|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet128|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet92|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet120|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet96|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet148|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet16|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet152|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet56|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet4|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet72|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet148|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet264|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet124|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet160|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet32|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet164|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet168|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet80|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet88|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet132|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet84|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet136|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet88|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet80|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet84|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet0|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet144|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet4|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet176|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet64|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet172|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet272|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet176|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet172|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet36|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet160|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet100|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet96|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet164|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet104|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet92|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet168|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet108|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet36|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet76|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet32|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet176|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet280|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet188|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet104|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet180|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet184|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet12|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet112|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet116|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet116|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet40|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet112|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet60|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet64|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet16|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet28|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet168|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet136|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet20|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet160|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet24|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet144|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet188|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet184|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet180|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet192|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet216|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet112|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet104|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet124|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet100|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet120|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet72|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet48|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet76|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet108|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet128|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet32|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet8|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet8|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet56|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet0|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet52|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet200|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet224|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet184|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet48|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet132|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet44|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet136|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet40|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet24|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet44|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet40|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet12|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet232|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet72|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet68|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet128|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet8|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet64|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet96|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet144|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet120|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet140|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet16|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet140|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet52|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet248|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet56|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet240|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet0|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet60|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet156|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet152|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet68|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet48|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet152|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet156|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet24|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet80|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet20|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet256|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet88|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet28|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet208|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet128|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet92|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet120|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet96|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet148|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet16|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet152|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet56|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet4|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet72|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet148|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet264|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet124|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet160|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet32|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet164|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet168|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet80|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet88|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet132|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet84|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet136|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet88|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet80|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet84|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet0|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet144|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet4|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet176|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet64|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet172|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet272|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet176|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet172|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet36|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet160|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet100|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet96|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet164|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet104|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet92|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet168|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet108|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet36|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet76|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet32|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet176|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet280|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet188|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet104|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet180|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet184|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet12|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet112|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet116|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet116|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet40|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet112|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet60|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet64|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet16|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet28|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet168|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet136|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet20|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet160|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet24|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet144|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet188|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet184|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet180|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet192|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet216|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet112|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet104|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet124|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet100|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet120|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet72|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet48|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet76|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet108|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet128|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet32|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet8|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet8|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet56|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet0|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet52|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet200|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet224|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet184|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet48|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet132|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet44|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet136|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet40|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet24|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet44|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet40|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet12|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet232|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet72|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet68|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet128|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet8|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet64|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet96|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet144|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet120|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet140|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet16|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet140|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet52|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet248|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet56|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet240|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet0|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet60|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet156|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet152|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet68|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet48|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet152|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet156|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet24|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet80|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet20|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet256|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet88|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet28|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet208|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet128|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet92|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet120|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet96|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet148|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet16|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet152|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet56|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet4|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet72|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet148|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet264|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet124|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet160|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet32|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet164|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet168|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet80|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet88|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet132|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet84|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet136|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet88|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet80|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet84|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet0|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet144|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet4|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet176|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet64|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet172|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet272|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet176|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet172|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet36|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet160|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet100|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet96|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet164|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet104|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet92|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet168|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet108|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet36|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet76|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet32|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet176|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet280|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet188|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet104|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet180|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet184|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet12|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet112|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet116|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet116|2": { "scheduler": "scheduler.0" }, - "Ethernet8|0": { + "str3-7800-lc8-1|asic0|Ethernet40|2": { "scheduler": "scheduler.0" }, - "Ethernet16|0": { + "str3-7800-lc1-1|Asic0|Ethernet112|2": { "scheduler": "scheduler.0" }, - "Ethernet24|0": { + "str3-7800-lc1-1|Asic0|Ethernet60|2": { "scheduler": "scheduler.0" }, - "Ethernet32|0": { + "str3-7800-lc1-1|Asic0|Ethernet64|2": { "scheduler": "scheduler.0" }, - "Ethernet40|0": { + "str3-7800-lc1-1|Asic0|Ethernet16|2": { "scheduler": "scheduler.0" }, - "Ethernet48|0": { + "str3-7800-lc2-1|Asic0|Ethernet28|2": { "scheduler": "scheduler.0" }, - "Ethernet56|0": { + "str3-7800-lc8-1|asic1|Ethernet168|2": { "scheduler": "scheduler.0" }, - "Ethernet64|0": { + "str3-7800-lc2-1|Asic0|Ethernet136|2": { "scheduler": "scheduler.0" }, - "Ethernet72|0": { + "str3-7800-lc2-1|Asic0|Ethernet20|2": { "scheduler": "scheduler.0" }, - "Ethernet80|0": { + "str3-7800-lc8-1|asic1|Ethernet160|2": { "scheduler": "scheduler.0" }, - "Ethernet88|0": { + "str3-7800-lc2-1|Asic0|Ethernet24|2": { "scheduler": "scheduler.0" }, - "Ethernet96|0": { + "str3-7800-lc1-1|Asic0|Ethernet144|2": { "scheduler": "scheduler.0" }, - "Ethernet104|0": { + "str3-7800-lc1-1|Asic0|Ethernet188|2": { "scheduler": "scheduler.0" }, - "Ethernet112|0": { + "str3-7800-lc1-1|Asic0|Ethernet184|2": { "scheduler": "scheduler.0" }, - "Ethernet120|0": { + "str3-7800-lc1-1|Asic0|Ethernet180|2": { "scheduler": "scheduler.0" }, - "Ethernet128|0": { + "str3-7800-lc8-1|asic1|Ethernet192|2": { "scheduler": "scheduler.0" }, - "Ethernet136|0": { + "str3-7800-lc8-1|asic1|Ethernet216|2": { "scheduler": "scheduler.0" }, - "Ethernet0|1": { + "str3-7800-lc8-1|asic0|Ethernet112|2": { "scheduler": "scheduler.0" }, - "Ethernet8|1": { + "str3-7800-lc1-1|Asic0|Ethernet104|5": { "scheduler": "scheduler.0" }, - "Ethernet16|1": { + "str3-7800-lc2-1|Asic0|Ethernet124|5": { "scheduler": "scheduler.0" }, - "Ethernet24|1": { + "str3-7800-lc1-1|Asic0|Ethernet100|5": { "scheduler": "scheduler.0" }, - "Ethernet32|1": { + "str3-7800-lc2-1|Asic0|Ethernet120|5": { "scheduler": "scheduler.0" }, - "Ethernet40|1": { + "str3-7800-lc1-1|Asic0|Ethernet72|5": { "scheduler": "scheduler.0" }, - "Ethernet48|1": { + "str3-7800-lc2-1|Asic0|Ethernet48|5": { "scheduler": "scheduler.0" }, - "Ethernet56|1": { + "str3-7800-lc1-1|Asic0|Ethernet76|5": { "scheduler": "scheduler.0" }, - "Ethernet64|1": { + "str3-7800-lc1-1|Asic0|Ethernet108|5": { "scheduler": "scheduler.0" }, - "Ethernet72|1": { + "str3-7800-lc2-1|Asic0|Ethernet128|5": { "scheduler": "scheduler.0" }, - "Ethernet80|1": { + "str3-7800-lc8-1|asic0|Ethernet32|5": { "scheduler": "scheduler.0" }, - "Ethernet88|1": { + "str3-7800-lc8-1|asic0|Ethernet8|5": { "scheduler": "scheduler.0" }, - "Ethernet96|1": { + "str3-7800-lc1-1|Asic0|Ethernet8|5": { "scheduler": "scheduler.0" }, - "Ethernet104|1": { + "str3-7800-lc2-1|Asic0|Ethernet56|5": { "scheduler": "scheduler.0" }, - "Ethernet112|1": { + "str3-7800-lc8-1|asic0|Ethernet0|5": { "scheduler": "scheduler.0" }, - "Ethernet120|1": { + "str3-7800-lc2-1|Asic0|Ethernet52|5": { "scheduler": "scheduler.0" }, - "Ethernet128|1": { + "str3-7800-lc8-1|asic1|Ethernet200|5": { "scheduler": "scheduler.0" }, - "Ethernet136|1": { + "str3-7800-lc8-1|asic1|Ethernet224|5": { "scheduler": "scheduler.0" }, - "Ethernet0|2": { + "str3-7800-lc8-1|asic1|Ethernet184|5": { "scheduler": "scheduler.0" }, - "Ethernet8|2": { + "str3-7800-lc1-1|Asic0|Ethernet48|5": { "scheduler": "scheduler.0" }, - "Ethernet16|2": { + "str3-7800-lc1-1|Asic0|Ethernet132|5": { "scheduler": "scheduler.0" }, - "Ethernet24|2": { + "str3-7800-lc1-1|Asic0|Ethernet44|5": { "scheduler": "scheduler.0" }, - "Ethernet32|2": { + "str3-7800-lc1-1|Asic0|Ethernet136|5": { "scheduler": "scheduler.0" }, - "Ethernet40|2": { + "str3-7800-lc1-1|Asic0|Ethernet40|5": { "scheduler": "scheduler.0" }, - "Ethernet48|2": { + "str3-7800-lc8-1|asic0|Ethernet24|5": { "scheduler": "scheduler.0" }, - "Ethernet56|2": { + "str3-7800-lc2-1|Asic0|Ethernet44|5": { "scheduler": "scheduler.0" }, - "Ethernet64|2": { + "str3-7800-lc2-1|Asic0|Ethernet40|5": { "scheduler": "scheduler.0" }, - "Ethernet72|2": { + "str3-7800-lc2-1|Asic0|Ethernet12|5": { "scheduler": "scheduler.0" }, - "Ethernet80|2": { + "str3-7800-lc8-1|asic1|Ethernet232|5": { "scheduler": "scheduler.0" }, - "Ethernet88|2": { + "str3-7800-lc2-1|Asic0|Ethernet72|5": { "scheduler": "scheduler.0" }, - "Ethernet96|2": { + "str3-7800-lc1-1|Asic0|Ethernet68|5": { "scheduler": "scheduler.0" }, - "Ethernet104|2": { + "str3-7800-lc1-1|Asic0|Ethernet128|5": { "scheduler": "scheduler.0" }, - "Ethernet112|2": { + "str3-7800-lc2-1|Asic0|Ethernet8|5": { "scheduler": "scheduler.0" }, - "Ethernet120|2": { + "str3-7800-lc2-1|Asic0|Ethernet64|5": { "scheduler": "scheduler.0" }, - "Ethernet128|2": { + "str3-7800-lc8-1|asic0|Ethernet96|5": { "scheduler": "scheduler.0" }, - "Ethernet136|2": { + "str3-7800-lc2-1|Asic0|Ethernet144|5": { "scheduler": "scheduler.0" }, - "Ethernet0|5": { + "str3-7800-lc1-1|Asic0|Ethernet120|5": { "scheduler": "scheduler.0" }, - "Ethernet8|5": { + "str3-7800-lc2-1|Asic0|Ethernet140|5": { "scheduler": "scheduler.0" }, - "Ethernet16|5": { + "str3-7800-lc8-1|asic0|Ethernet16|5": { "scheduler": "scheduler.0" }, - "Ethernet24|5": { + "str3-7800-lc1-1|Asic0|Ethernet140|5": { "scheduler": "scheduler.0" }, - "Ethernet32|5": { + "str3-7800-lc1-1|Asic0|Ethernet52|5": { "scheduler": "scheduler.0" }, - "Ethernet40|5": { + "str3-7800-lc8-1|asic1|Ethernet248|5": { "scheduler": "scheduler.0" }, - "Ethernet48|5": { + "str3-7800-lc1-1|Asic0|Ethernet56|5": { "scheduler": "scheduler.0" }, - "Ethernet56|5": { + "str3-7800-lc8-1|asic1|Ethernet240|5": { "scheduler": "scheduler.0" }, - "Ethernet64|5": { + "str3-7800-lc2-1|Asic0|Ethernet0|5": { "scheduler": "scheduler.0" }, - "Ethernet72|5": { + "str3-7800-lc2-1|Asic0|Ethernet60|5": { "scheduler": "scheduler.0" }, - "Ethernet80|5": { + "str3-7800-lc2-1|Asic0|Ethernet156|5": { "scheduler": "scheduler.0" }, - "Ethernet88|5": { + "str3-7800-lc2-1|Asic0|Ethernet152|5": { "scheduler": "scheduler.0" }, - "Ethernet96|5": { + "str3-7800-lc2-1|Asic0|Ethernet68|5": { "scheduler": "scheduler.0" }, - "Ethernet104|5": { + "str3-7800-lc8-1|asic0|Ethernet48|5": { "scheduler": "scheduler.0" }, - "Ethernet112|5": { + "str3-7800-lc1-1|Asic0|Ethernet152|5": { "scheduler": "scheduler.0" }, - "Ethernet120|5": { + "str3-7800-lc1-1|Asic0|Ethernet156|5": { "scheduler": "scheduler.0" }, - "Ethernet128|5": { + "str3-7800-lc1-1|Asic0|Ethernet24|5": { "scheduler": "scheduler.0" }, - "Ethernet136|5": { + "str3-7800-lc8-1|asic0|Ethernet80|5": { "scheduler": "scheduler.0" }, - "Ethernet0|6": { + "str3-7800-lc1-1|Asic0|Ethernet20|5": { "scheduler": "scheduler.0" }, - "Ethernet8|6": { + "str3-7800-lc8-1|asic1|Ethernet256|5": { "scheduler": "scheduler.0" }, - "Ethernet16|6": { + "str3-7800-lc8-1|asic0|Ethernet88|5": { "scheduler": "scheduler.0" }, - "Ethernet24|6": { + "str3-7800-lc1-1|Asic0|Ethernet28|5": { "scheduler": "scheduler.0" }, - "Ethernet32|6": { + "str3-7800-lc8-1|asic1|Ethernet208|5": { "scheduler": "scheduler.0" }, - "Ethernet40|6": { + "str3-7800-lc8-1|asic0|Ethernet128|5": { "scheduler": "scheduler.0" }, - "Ethernet48|6": { + "str3-7800-lc2-1|Asic0|Ethernet92|5": { "scheduler": "scheduler.0" }, - "Ethernet56|6": { + "str3-7800-lc8-1|asic0|Ethernet120|5": { "scheduler": "scheduler.0" }, - "Ethernet64|6": { + "str3-7800-lc2-1|Asic0|Ethernet96|5": { "scheduler": "scheduler.0" }, - "Ethernet72|6": { + "str3-7800-lc1-1|Asic0|Ethernet148|5": { "scheduler": "scheduler.0" }, - "Ethernet80|6": { + "str3-7800-lc2-1|Asic0|Ethernet16|5": { "scheduler": "scheduler.0" }, - "Ethernet88|6": { + "str3-7800-lc8-1|asic1|Ethernet152|5": { "scheduler": "scheduler.0" }, - "Ethernet96|6": { + "str3-7800-lc8-1|asic0|Ethernet56|5": { "scheduler": "scheduler.0" }, - "Ethernet104|6": { + "str3-7800-lc2-1|Asic0|Ethernet4|5": { "scheduler": "scheduler.0" }, - "Ethernet112|6": { + "str3-7800-lc8-1|asic0|Ethernet72|5": { "scheduler": "scheduler.0" }, - "Ethernet120|6": { + "str3-7800-lc2-1|Asic0|Ethernet148|5": { "scheduler": "scheduler.0" }, - "Ethernet128|6": { + "str3-7800-lc8-1|asic1|Ethernet264|5": { "scheduler": "scheduler.0" }, - "Ethernet136|6": { + "str3-7800-lc1-1|Asic0|Ethernet124|5": { "scheduler": "scheduler.0" - } + }, + "str3-7800-lc2-1|Asic0|Ethernet160|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet32|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet164|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet168|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet80|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet88|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet132|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet84|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet136|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet88|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet80|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet84|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet0|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet144|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet4|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet176|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet64|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet172|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet272|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet176|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet172|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet36|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet160|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet100|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet96|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet164|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet104|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet92|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet168|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet108|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet36|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet76|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet32|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet176|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet280|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet188|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet104|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet180|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet184|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet12|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet112|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet116|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet116|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet40|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet112|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet60|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet64|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet16|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet28|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet168|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet136|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet20|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet160|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet24|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet144|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet188|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet184|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet180|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet192|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet216|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet112|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet104|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet124|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet100|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet120|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet72|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet48|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet76|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet108|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet128|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic0|Ethernet32|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic0|Ethernet8|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet8|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet56|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic0|Ethernet0|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet52|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic1|Ethernet200|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic1|Ethernet224|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic1|Ethernet184|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet48|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet132|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet44|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet136|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet40|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic0|Ethernet24|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet44|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet40|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet12|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic1|Ethernet232|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet72|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet68|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet128|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet8|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet64|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic0|Ethernet96|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet144|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet120|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet140|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic0|Ethernet16|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet140|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet52|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic1|Ethernet248|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet56|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic1|Ethernet240|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet0|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet60|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet156|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet152|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet68|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic0|Ethernet48|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet152|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet156|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet24|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic0|Ethernet80|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet20|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic1|Ethernet256|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic0|Ethernet88|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet28|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic1|Ethernet208|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic0|Ethernet128|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet92|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic0|Ethernet120|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet96|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet148|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet16|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic1|Ethernet152|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic0|Ethernet56|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet4|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic0|Ethernet72|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet148|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic1|Ethernet264|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet124|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet160|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet32|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet164|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet168|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet80|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet88|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet132|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet84|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic0|Ethernet136|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet88|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet80|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet84|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet0|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic1|Ethernet144|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet4|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet176|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic0|Ethernet64|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet172|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic1|Ethernet272|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet176|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet172|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet36|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet160|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet100|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet96|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet164|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet104|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet92|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet168|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet108|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet36|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet76|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet32|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic1|Ethernet176|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic1|Ethernet280|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet188|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic0|Ethernet104|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet180|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet184|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet12|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet112|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet116|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet116|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic0|Ethernet40|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet112|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet60|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet64|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet16|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet28|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic1|Ethernet168|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet136|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet20|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic1|Ethernet160|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet24|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet144|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet188|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet184|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet180|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic1|Ethernet192|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic1|Ethernet216|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic0|Ethernet112|6": { + "scheduler": "scheduler.0" + } } } diff --git a/src/sonic-config-engine/tests/sample_output/py2/qos-nokia-ixr7250e-36x100g.json b/src/sonic-config-engine/tests/sample_output/py2/qos-nokia-ixr7250e-36x100g.json index cf6fbf64f8db..cff51028497c 100644 --- a/src/sonic-config-engine/tests/sample_output/py2/qos-nokia-ixr7250e-36x100g.json +++ b/src/sonic-config-engine/tests/sample_output/py2/qos-nokia-ixr7250e-36x100g.json @@ -280,419 +280,2382 @@ } }, "QUEUE": { - "Ethernet0|3": { + "svcstr-7250-lc2-1|asic1|Ethernet248|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet8|3": { + "svcstr-7250-lc3-1|asic1|Ethernet160|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet16|3": { + "svcstr-7250-lc2-1|asic1|Ethernet240|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet24|3": { + "svcstr-7250-lc1-1|asic1|Ethernet280|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet32|3": { + "svcstr-7250-lc3-1|asic0|Ethernet32|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet40|3": { + "svcstr-7250-lc2-1|asic0|Ethernet104|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet48|3": { + "svcstr-7250-lc3-1|asic0|Ethernet72|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet56|3": { + "svcstr-7250-lc1-1|asic0|Ethernet128|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet64|3": { + "svcstr-7250-lc2-1|asic1|Ethernet152|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet72|3": { + "svcstr-7250-lc1-1|asic0|Ethernet120|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet80|3": { + "svcstr-7250-lc2-1|asic0|Ethernet96|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet88|3": { + "svcstr-7250-lc1-1|asic0|Ethernet64|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet96|3": { + "svcstr-7250-lc1-1|asic1|Ethernet168|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet104|3": { + "svcstr-7250-lc3-1|asic1|Ethernet240|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet112|3": { + "svcstr-7250-lc3-1|asic0|Ethernet40|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet120|3": { + "svcstr-7250-lc3-1|asic1|Ethernet168|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet128|3": { + "svcstr-7250-lc1-1|asic1|Ethernet160|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet136|3": { + "svcstr-7250-lc2-1|asic0|Ethernet56|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet0|4": { + "svcstr-7250-lc3-1|asic1|Ethernet176|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet8|4": { + "svcstr-7250-lc2-1|asic1|Ethernet256|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet16|4": { + "svcstr-7250-lc3-1|asic0|Ethernet48|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet24|4": { + "svcstr-7250-lc2-1|asic0|Ethernet112|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet32|4": { + "svcstr-7250-lc1-1|asic1|Ethernet272|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet40|4": { + "svcstr-7250-lc2-1|asic1|Ethernet144|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet48|4": { + "svcstr-7250-lc2-1|asic0|Ethernet48|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet56|4": { + "svcstr-7250-lc1-1|asic0|Ethernet72|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet64|4": { + "svcstr-7250-lc2-1|asic0|Ethernet40|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet72|4": { + "svcstr-7250-lc3-1|asic1|Ethernet272|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet80|4": { + "svcstr-7250-lc1-1|asic1|Ethernet176|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet88|4": { + "svcstr-7250-lc2-1|asic0|Ethernet120|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet96|4": { + "svcstr-7250-lc2-1|asic0|Ethernet128|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet104|4": { + "svcstr-7250-lc3-1|asic1|Ethernet184|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet112|4": { + "svcstr-7250-lc2-1|asic0|Ethernet8|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet120|4": { + "svcstr-7250-lc3-1|asic0|Ethernet56|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet128|4": { + "svcstr-7250-lc2-1|asic0|Ethernet0|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet136|4": { + "svcstr-7250-lc2-1|asic1|Ethernet224|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet0|0": { + "svcstr-7250-lc1-1|asic1|Ethernet264|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet48|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet40|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet144|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet264|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet72|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet136|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet64|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet192|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet200|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet216|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet232|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet152|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet280|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet64|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet256|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet56|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet208|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet208|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet136|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet200|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet24|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet280|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet208|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet200|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet16|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet8|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet248|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet0|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet240|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet120|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet88|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet216|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet88|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet128|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet80|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet192|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet80|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet232|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet112|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet248|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet232|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet264|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet184|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet96|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet80|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet16|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet144|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet88|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet104|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet176|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet32|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet184|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet224|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet192|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet224|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet32|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet272|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet104|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet24|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet96|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet152|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet160|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet0|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet136|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet168|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet8|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet24|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet256|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet112|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet16|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet216|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet248|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet160|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet240|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet280|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet32|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet104|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet72|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet128|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet152|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet120|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet96|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet64|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet168|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet240|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet40|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet168|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet160|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet56|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet176|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet256|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet48|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet112|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet272|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet144|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet48|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet72|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet40|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet272|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet176|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet120|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet128|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet184|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet8|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet56|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet0|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet224|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet264|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet48|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet40|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet144|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet264|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet72|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet136|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet64|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet192|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet200|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet216|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet232|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet152|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet280|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet64|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet256|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet56|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet208|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet208|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet136|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet200|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet24|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet280|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet208|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet200|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet16|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet8|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet248|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet0|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet240|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet120|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet88|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet216|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet88|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet128|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet80|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet192|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet80|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet232|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet112|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet248|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet232|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet264|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet184|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet96|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet80|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet16|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet144|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet88|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet104|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet176|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet32|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet184|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet224|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet192|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet224|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet32|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet272|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet104|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet24|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet96|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet152|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet160|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet0|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet136|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet168|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet8|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet24|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet256|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet112|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet16|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet216|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet248|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet160|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet240|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet280|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet32|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet104|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet72|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet128|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet152|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet120|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet96|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet64|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet168|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet240|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet40|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet168|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet160|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet56|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet176|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet256|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet48|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet112|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet272|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet144|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet48|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet72|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet40|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet272|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet176|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet120|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet128|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet184|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet8|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet56|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet0|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet224|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet264|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet48|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet40|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet144|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet264|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet72|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet136|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet64|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet192|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet200|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet216|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet232|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet152|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet280|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet64|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet256|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet56|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet208|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet208|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet136|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet200|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet24|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet280|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet208|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet200|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet16|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet8|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet248|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet0|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet240|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet120|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet88|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet216|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet88|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet128|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet80|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet192|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet80|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet232|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet112|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet248|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet232|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet264|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet184|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet96|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet80|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet16|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet144|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet88|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet104|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet176|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet32|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet184|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet224|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet192|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet224|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet32|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet272|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet104|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet24|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet96|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet152|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet160|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet0|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet136|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet168|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet8|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet24|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet256|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet112|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet16|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet216|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet248|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet160|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet240|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet280|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet32|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet104|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet72|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet128|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet152|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet120|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet96|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet64|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet168|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet240|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet40|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet168|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet160|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet56|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet176|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet256|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet48|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet112|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet272|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet144|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet48|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet72|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet40|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet272|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet176|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet120|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet128|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet184|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet8|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet56|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet0|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet224|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet264|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet48|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet40|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet144|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet264|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet72|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet136|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet64|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet192|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet200|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet216|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet232|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet152|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet280|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet64|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet256|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet56|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet208|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet208|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet136|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet200|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet24|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet280|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet208|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet200|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet16|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet8|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet248|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet0|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet240|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet120|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet88|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet216|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet88|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet128|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet80|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet192|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet80|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet232|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet112|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet248|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet232|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet264|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet184|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet96|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet80|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet16|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet144|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet88|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet104|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet176|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet32|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet184|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet224|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet192|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet224|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet32|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet272|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet104|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet24|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet96|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet152|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet160|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet0|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet136|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet168|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet8|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet24|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet256|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet112|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet16|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet216|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet248|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet160|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet240|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet280|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet32|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet104|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet72|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet128|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet152|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet120|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet96|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet64|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet168|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet240|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet40|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet168|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet160|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet56|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet176|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet256|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet48|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet112|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet272|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet144|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet48|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet72|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet40|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet272|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet176|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet120|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet128|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet184|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet8|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet56|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet0|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet224|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet264|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet48|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet40|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet144|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet264|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet72|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet136|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet64|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet192|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet200|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet216|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet232|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet152|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet280|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet64|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet256|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet56|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet208|2": { "scheduler": "scheduler.0" }, - "Ethernet8|0": { + "svcstr-7250-lc3-1|asic1|Ethernet208|2": { "scheduler": "scheduler.0" }, - "Ethernet16|0": { + "svcstr-7250-lc3-1|asic0|Ethernet136|2": { "scheduler": "scheduler.0" }, - "Ethernet24|0": { + "svcstr-7250-lc3-1|asic1|Ethernet200|2": { "scheduler": "scheduler.0" }, - "Ethernet32|0": { + "svcstr-7250-lc1-1|asic0|Ethernet24|2": { "scheduler": "scheduler.0" }, - "Ethernet40|0": { + "svcstr-7250-lc3-1|asic1|Ethernet280|2": { "scheduler": "scheduler.0" }, - "Ethernet48|0": { + "svcstr-7250-lc2-1|asic1|Ethernet208|2": { "scheduler": "scheduler.0" }, - "Ethernet56|0": { + "svcstr-7250-lc2-1|asic1|Ethernet200|2": { "scheduler": "scheduler.0" }, - "Ethernet64|0": { + "svcstr-7250-lc2-1|asic0|Ethernet16|2": { "scheduler": "scheduler.0" }, - "Ethernet72|0": { + "svcstr-7250-lc1-1|asic0|Ethernet8|2": { "scheduler": "scheduler.0" }, - "Ethernet80|0": { + "svcstr-7250-lc1-1|asic1|Ethernet248|2": { "scheduler": "scheduler.0" }, - "Ethernet88|0": { + "svcstr-7250-lc1-1|asic0|Ethernet0|2": { "scheduler": "scheduler.0" }, - "Ethernet96|0": { + "svcstr-7250-lc1-1|asic1|Ethernet240|2": { "scheduler": "scheduler.0" }, - "Ethernet104|0": { + "svcstr-7250-lc3-1|asic0|Ethernet120|2": { "scheduler": "scheduler.0" }, - "Ethernet112|0": { + "svcstr-7250-lc3-1|asic0|Ethernet88|2": { "scheduler": "scheduler.0" }, - "Ethernet120|0": { + "svcstr-7250-lc2-1|asic1|Ethernet216|2": { "scheduler": "scheduler.0" }, - "Ethernet128|0": { + "svcstr-7250-lc2-1|asic0|Ethernet88|2": { "scheduler": "scheduler.0" }, - "Ethernet136|0": { + "svcstr-7250-lc3-1|asic0|Ethernet128|2": { "scheduler": "scheduler.0" }, - "Ethernet0|1": { + "svcstr-7250-lc3-1|asic0|Ethernet80|2": { "scheduler": "scheduler.0" }, - "Ethernet8|1": { + "svcstr-7250-lc2-1|asic1|Ethernet192|2": { "scheduler": "scheduler.0" }, - "Ethernet16|1": { + "svcstr-7250-lc2-1|asic0|Ethernet80|2": { "scheduler": "scheduler.0" }, - "Ethernet24|1": { + "svcstr-7250-lc3-1|asic1|Ethernet232|2": { "scheduler": "scheduler.0" }, - "Ethernet32|1": { + "svcstr-7250-lc1-1|asic0|Ethernet112|2": { "scheduler": "scheduler.0" }, - "Ethernet40|1": { + "svcstr-7250-lc3-1|asic1|Ethernet248|2": { "scheduler": "scheduler.0" }, - "Ethernet48|1": { + "svcstr-7250-lc1-1|asic1|Ethernet232|2": { "scheduler": "scheduler.0" }, - "Ethernet56|1": { + "svcstr-7250-lc2-1|asic1|Ethernet264|2": { "scheduler": "scheduler.0" }, - "Ethernet64|1": { + "svcstr-7250-lc2-1|asic1|Ethernet184|2": { "scheduler": "scheduler.0" }, - "Ethernet72|1": { + "svcstr-7250-lc3-1|asic0|Ethernet96|2": { "scheduler": "scheduler.0" }, - "Ethernet80|1": { + "svcstr-7250-lc1-1|asic0|Ethernet80|2": { "scheduler": "scheduler.0" }, - "Ethernet88|1": { + "svcstr-7250-lc3-1|asic0|Ethernet16|2": { "scheduler": "scheduler.0" }, - "Ethernet96|1": { + "svcstr-7250-lc3-1|asic1|Ethernet144|2": { "scheduler": "scheduler.0" }, - "Ethernet104|1": { + "svcstr-7250-lc1-1|asic0|Ethernet88|2": { "scheduler": "scheduler.0" }, - "Ethernet112|1": { + "svcstr-7250-lc1-1|asic0|Ethernet104|2": { "scheduler": "scheduler.0" }, - "Ethernet120|1": { + "svcstr-7250-lc2-1|asic1|Ethernet176|2": { "scheduler": "scheduler.0" }, - "Ethernet128|1": { + "svcstr-7250-lc2-1|asic0|Ethernet32|2": { "scheduler": "scheduler.0" }, - "Ethernet136|1": { + "svcstr-7250-lc1-1|asic1|Ethernet184|2": { "scheduler": "scheduler.0" }, - "Ethernet0|2": { + "svcstr-7250-lc3-1|asic1|Ethernet224|2": { "scheduler": "scheduler.0" }, - "Ethernet8|2": { + "svcstr-7250-lc1-1|asic1|Ethernet192|2": { "scheduler": "scheduler.0" }, - "Ethernet16|2": { + "svcstr-7250-lc1-1|asic1|Ethernet224|2": { "scheduler": "scheduler.0" }, - "Ethernet24|2": { + "svcstr-7250-lc1-1|asic0|Ethernet32|2": { "scheduler": "scheduler.0" }, - "Ethernet32|2": { + "svcstr-7250-lc2-1|asic1|Ethernet272|2": { "scheduler": "scheduler.0" }, - "Ethernet40|2": { + "svcstr-7250-lc3-1|asic0|Ethernet104|2": { "scheduler": "scheduler.0" }, - "Ethernet48|2": { + "svcstr-7250-lc3-1|asic0|Ethernet24|2": { "scheduler": "scheduler.0" }, - "Ethernet56|2": { + "svcstr-7250-lc1-1|asic0|Ethernet96|2": { "scheduler": "scheduler.0" }, - "Ethernet64|2": { + "svcstr-7250-lc3-1|asic1|Ethernet152|2": { "scheduler": "scheduler.0" }, - "Ethernet72|2": { + "svcstr-7250-lc2-1|asic1|Ethernet160|2": { "scheduler": "scheduler.0" }, - "Ethernet80|2": { + "svcstr-7250-lc3-1|asic0|Ethernet0|2": { "scheduler": "scheduler.0" }, - "Ethernet88|2": { + "svcstr-7250-lc1-1|asic0|Ethernet136|2": { "scheduler": "scheduler.0" }, - "Ethernet96|2": { + "svcstr-7250-lc2-1|asic1|Ethernet168|2": { "scheduler": "scheduler.0" }, - "Ethernet104|2": { + "svcstr-7250-lc3-1|asic0|Ethernet8|2": { "scheduler": "scheduler.0" }, - "Ethernet112|2": { + "svcstr-7250-lc2-1|asic0|Ethernet24|2": { "scheduler": "scheduler.0" }, - "Ethernet120|2": { + "svcstr-7250-lc3-1|asic1|Ethernet256|2": { "scheduler": "scheduler.0" }, - "Ethernet128|2": { + "svcstr-7250-lc3-1|asic0|Ethernet112|2": { "scheduler": "scheduler.0" }, - "Ethernet136|2": { + "svcstr-7250-lc1-1|asic0|Ethernet16|2": { "scheduler": "scheduler.0" }, - "Ethernet0|5": { + "svcstr-7250-lc1-1|asic1|Ethernet216|2": { "scheduler": "scheduler.0" }, - "Ethernet8|5": { + "svcstr-7250-lc2-1|asic1|Ethernet248|5": { "scheduler": "scheduler.0" }, - "Ethernet16|5": { + "svcstr-7250-lc3-1|asic1|Ethernet160|5": { "scheduler": "scheduler.0" }, - "Ethernet24|5": { + "svcstr-7250-lc2-1|asic1|Ethernet240|5": { "scheduler": "scheduler.0" }, - "Ethernet32|5": { + "svcstr-7250-lc1-1|asic1|Ethernet280|5": { "scheduler": "scheduler.0" }, - "Ethernet40|5": { + "svcstr-7250-lc3-1|asic0|Ethernet32|5": { "scheduler": "scheduler.0" }, - "Ethernet48|5": { + "svcstr-7250-lc2-1|asic0|Ethernet104|5": { "scheduler": "scheduler.0" }, - "Ethernet56|5": { + "svcstr-7250-lc3-1|asic0|Ethernet72|5": { "scheduler": "scheduler.0" }, - "Ethernet64|5": { + "svcstr-7250-lc1-1|asic0|Ethernet128|5": { "scheduler": "scheduler.0" }, - "Ethernet72|5": { + "svcstr-7250-lc2-1|asic1|Ethernet152|5": { "scheduler": "scheduler.0" }, - "Ethernet80|5": { + "svcstr-7250-lc1-1|asic0|Ethernet120|5": { "scheduler": "scheduler.0" }, - "Ethernet88|5": { + "svcstr-7250-lc2-1|asic0|Ethernet96|5": { "scheduler": "scheduler.0" }, - "Ethernet96|5": { + "svcstr-7250-lc1-1|asic0|Ethernet64|5": { "scheduler": "scheduler.0" }, - "Ethernet104|5": { + "svcstr-7250-lc1-1|asic1|Ethernet168|5": { "scheduler": "scheduler.0" }, - "Ethernet112|5": { + "svcstr-7250-lc3-1|asic1|Ethernet240|5": { "scheduler": "scheduler.0" }, - "Ethernet120|5": { + "svcstr-7250-lc3-1|asic0|Ethernet40|5": { "scheduler": "scheduler.0" }, - "Ethernet128|5": { + "svcstr-7250-lc3-1|asic1|Ethernet168|5": { "scheduler": "scheduler.0" }, - "Ethernet136|5": { + "svcstr-7250-lc1-1|asic1|Ethernet160|5": { "scheduler": "scheduler.0" }, - "Ethernet0|6": { + "svcstr-7250-lc2-1|asic0|Ethernet56|5": { "scheduler": "scheduler.0" }, - "Ethernet8|6": { + "svcstr-7250-lc3-1|asic1|Ethernet176|5": { "scheduler": "scheduler.0" }, - "Ethernet16|6": { + "svcstr-7250-lc2-1|asic1|Ethernet256|5": { "scheduler": "scheduler.0" }, - "Ethernet24|6": { + "svcstr-7250-lc3-1|asic0|Ethernet48|5": { "scheduler": "scheduler.0" }, - "Ethernet32|6": { + "svcstr-7250-lc2-1|asic0|Ethernet112|5": { "scheduler": "scheduler.0" }, - "Ethernet40|6": { + "svcstr-7250-lc1-1|asic1|Ethernet272|5": { "scheduler": "scheduler.0" }, - "Ethernet48|6": { + "svcstr-7250-lc2-1|asic1|Ethernet144|5": { "scheduler": "scheduler.0" }, - "Ethernet56|6": { + "svcstr-7250-lc2-1|asic0|Ethernet48|5": { "scheduler": "scheduler.0" }, - "Ethernet64|6": { + "svcstr-7250-lc1-1|asic0|Ethernet72|5": { "scheduler": "scheduler.0" }, - "Ethernet72|6": { + "svcstr-7250-lc2-1|asic0|Ethernet40|5": { "scheduler": "scheduler.0" }, - "Ethernet80|6": { + "svcstr-7250-lc3-1|asic1|Ethernet272|5": { "scheduler": "scheduler.0" }, - "Ethernet88|6": { + "svcstr-7250-lc1-1|asic1|Ethernet176|5": { "scheduler": "scheduler.0" }, - "Ethernet96|6": { + "svcstr-7250-lc2-1|asic0|Ethernet120|5": { "scheduler": "scheduler.0" }, - "Ethernet104|6": { + "svcstr-7250-lc2-1|asic0|Ethernet128|5": { "scheduler": "scheduler.0" }, - "Ethernet112|6": { + "svcstr-7250-lc3-1|asic1|Ethernet184|5": { "scheduler": "scheduler.0" }, - "Ethernet120|6": { + "svcstr-7250-lc2-1|asic0|Ethernet8|5": { "scheduler": "scheduler.0" }, - "Ethernet128|6": { + "svcstr-7250-lc3-1|asic0|Ethernet56|5": { "scheduler": "scheduler.0" }, - "Ethernet136|6": { + "svcstr-7250-lc2-1|asic0|Ethernet0|5": { "scheduler": "scheduler.0" - } + }, + "svcstr-7250-lc2-1|asic1|Ethernet224|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet264|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet48|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet40|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet144|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet264|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet72|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet136|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet64|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet192|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet200|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet216|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet232|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet152|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet280|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet64|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet256|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet56|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet208|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet208|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet136|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet200|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet24|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet280|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet208|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet200|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet16|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet8|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet248|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet0|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet240|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet120|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet88|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet216|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet88|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet128|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet80|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet192|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet80|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet232|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet112|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet248|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet232|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet264|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet184|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet96|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet80|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet16|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet144|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet88|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet104|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet176|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet32|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet184|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet224|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet192|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet224|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet32|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet272|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet104|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet24|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet96|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet152|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet160|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet0|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet136|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet168|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet8|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet24|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet256|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet112|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet16|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet216|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet248|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic1|Ethernet160|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic1|Ethernet240|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic1|Ethernet280|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic0|Ethernet32|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic0|Ethernet104|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic0|Ethernet72|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic0|Ethernet128|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic1|Ethernet152|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic0|Ethernet120|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic0|Ethernet96|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic0|Ethernet64|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic1|Ethernet168|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic1|Ethernet240|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic0|Ethernet40|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic1|Ethernet168|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic1|Ethernet160|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic0|Ethernet56|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic1|Ethernet176|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic1|Ethernet256|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic0|Ethernet48|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic0|Ethernet112|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic1|Ethernet272|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic1|Ethernet144|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic0|Ethernet48|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic0|Ethernet72|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic0|Ethernet40|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic1|Ethernet272|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic1|Ethernet176|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic0|Ethernet120|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic0|Ethernet128|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic1|Ethernet184|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic0|Ethernet8|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic0|Ethernet56|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic0|Ethernet0|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic1|Ethernet224|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic1|Ethernet264|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic0|Ethernet48|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic0|Ethernet40|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic1|Ethernet144|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic1|Ethernet264|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic0|Ethernet72|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic0|Ethernet136|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic0|Ethernet64|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic1|Ethernet192|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic1|Ethernet200|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic1|Ethernet216|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic1|Ethernet232|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic1|Ethernet152|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic1|Ethernet280|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic0|Ethernet64|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic1|Ethernet256|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic0|Ethernet56|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic1|Ethernet208|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic1|Ethernet208|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic0|Ethernet136|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic1|Ethernet200|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic0|Ethernet24|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic1|Ethernet280|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic1|Ethernet208|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic1|Ethernet200|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic0|Ethernet16|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic0|Ethernet8|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic1|Ethernet248|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic0|Ethernet0|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic1|Ethernet240|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic0|Ethernet120|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic0|Ethernet88|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic1|Ethernet216|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic0|Ethernet88|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic0|Ethernet128|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic0|Ethernet80|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic1|Ethernet192|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic0|Ethernet80|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic1|Ethernet232|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic0|Ethernet112|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic1|Ethernet248|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic1|Ethernet232|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic1|Ethernet264|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic1|Ethernet184|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic0|Ethernet96|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic0|Ethernet80|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic0|Ethernet16|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic1|Ethernet144|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic0|Ethernet88|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic0|Ethernet104|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic1|Ethernet176|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic0|Ethernet32|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic1|Ethernet184|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic1|Ethernet224|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic1|Ethernet192|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic1|Ethernet224|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic0|Ethernet32|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic1|Ethernet272|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic0|Ethernet104|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic0|Ethernet24|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic0|Ethernet96|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic1|Ethernet152|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic1|Ethernet160|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic0|Ethernet0|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic0|Ethernet136|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic1|Ethernet168|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic0|Ethernet8|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic0|Ethernet24|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic1|Ethernet256|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic0|Ethernet112|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic0|Ethernet16|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic1|Ethernet216|6": { + "scheduler": "scheduler.0" + } } } diff --git a/src/sonic-config-engine/tests/sample_output/py2/qos-nokia-ixr7250e-36x400g.json b/src/sonic-config-engine/tests/sample_output/py2/qos-nokia-ixr7250e-36x400g.json index cf6fbf64f8db..5a5badc9d369 100644 --- a/src/sonic-config-engine/tests/sample_output/py2/qos-nokia-ixr7250e-36x400g.json +++ b/src/sonic-config-engine/tests/sample_output/py2/qos-nokia-ixr7250e-36x400g.json @@ -280,418 +280,1660 @@ } }, "QUEUE": { - "Ethernet0|3": { - "scheduler" : "scheduler.1", + "str2-7250-lc1-1|asic0|Ethernet0|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet0|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet0|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet0|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet0|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet0|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet0|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet8|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet8|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet8|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet8|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet8|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet8|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet8|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet16|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet16|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet16|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet16|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet16|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet16|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet16|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet24|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet24|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet24|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet24|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet24|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet24|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet24|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet32|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet32|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet32|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet32|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet32|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet32|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet32|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet40|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet40|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet40|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet40|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet40|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet40|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet40|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet48|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet48|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet48|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet48|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet48|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet48|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet48|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet56|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet56|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet56|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet56|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet56|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet56|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet56|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet64|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet64|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet64|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet64|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet64|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet64|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet64|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet72|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet72|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet72|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet72|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet72|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet72|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet72|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet80|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet80|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet80|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet80|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet80|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet80|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet80|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet88|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet88|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet88|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet88|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet88|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet88|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet88|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet96|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet96|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet96|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet96|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet96|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet96|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet96|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet104|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet104|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet104|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet104|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet104|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet104|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet104|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet112|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet112|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet112|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet112|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet112|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet112|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet112|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet120|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet120|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet120|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet120|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet120|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet120|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet120|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet128|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet128|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet128|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet128|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet128|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet128|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet128|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet136|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet136|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet136|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet136|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet136|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet136|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet136|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet144|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet144|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet144|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet144|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet144|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet144|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet144|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet152|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet152|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet152|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet152|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet152|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet152|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet152|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet160|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet160|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet160|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet160|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet160|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet160|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet160|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet168|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet168|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet168|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet168|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet168|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet168|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet168|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet176|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet176|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet176|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet176|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet176|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet176|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet176|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet184|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet184|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet184|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet184|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet184|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet184|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet184|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet192|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet192|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet192|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet192|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet192|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet192|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet192|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet200|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet200|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet200|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet200|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet200|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet200|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet200|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet208|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet208|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet208|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet208|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet208|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet208|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet208|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet216|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet216|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet216|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet216|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet216|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet216|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet216|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet224|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet224|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet224|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet224|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet224|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet224|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet224|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet232|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet232|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet232|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet232|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet232|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet232|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet232|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet240|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet240|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet240|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet240|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet240|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet240|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet240|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet248|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet248|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet248|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet248|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet248|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet248|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet248|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet256|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet256|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet256|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet256|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet256|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet256|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet256|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet264|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet264|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet264|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet264|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet264|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet264|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet264|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet272|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet272|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet272|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet272|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet272|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet272|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet272|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet280|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet280|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet280|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet280|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet280|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet280|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet280|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet0|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet0|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet0|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet0|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet8|3": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet0|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet16|3": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet0|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet0|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet8|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet8|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet8|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet8|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet24|3": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet8|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet32|3": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet8|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet8|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet16|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet16|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet16|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet16|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet40|3": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet16|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet48|3": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet16|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet16|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet24|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet24|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet24|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet24|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet56|3": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet24|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet64|3": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet24|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet24|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet32|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet32|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet32|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet32|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet72|3": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet32|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet80|3": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet32|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet32|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet40|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet40|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet40|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet40|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet88|3": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet40|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet96|3": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet40|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet40|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet48|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet48|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet48|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet48|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet104|3": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet48|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet112|3": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet48|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet48|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet56|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet56|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet56|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet56|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet120|3": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet56|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet128|3": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet56|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet56|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet64|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet64|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet64|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet64|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet136|3": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet64|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet0|4": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet64|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet64|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet72|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet72|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet72|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet72|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet8|4": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet72|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet16|4": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet72|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet72|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet80|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet80|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet80|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet80|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet24|4": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet80|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet32|4": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet80|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet80|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet88|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet88|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet88|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet88|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet40|4": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet88|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet48|4": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet88|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet88|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet96|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet96|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet96|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet96|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet56|4": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet96|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet64|4": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet96|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet96|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet104|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet104|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet104|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet104|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet72|4": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet104|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet80|4": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet104|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet104|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet112|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet112|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet112|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet112|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet88|4": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet112|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet96|4": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet112|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet112|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet120|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet120|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet120|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet120|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet104|4": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet120|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet112|4": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet120|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet120|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet128|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet128|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet128|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet128|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet120|4": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet128|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet128|4": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet128|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet128|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet136|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet136|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet136|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet136|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet136|4": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet136|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet0|0": { + "str2-7250-lc2-1|asic0|Ethernet136|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet136|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic1|Ethernet144|0": { "scheduler": "scheduler.0" }, - "Ethernet8|0": { + "str2-7250-lc2-1|asic1|Ethernet144|1": { "scheduler": "scheduler.0" }, - "Ethernet16|0": { + "str2-7250-lc2-1|asic1|Ethernet144|2": { "scheduler": "scheduler.0" }, - "Ethernet24|0": { + "str2-7250-lc2-1|asic1|Ethernet144|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet144|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet144|5": { "scheduler": "scheduler.0" }, - "Ethernet32|0": { + "str2-7250-lc2-1|asic1|Ethernet144|6": { "scheduler": "scheduler.0" }, - "Ethernet40|0": { + "str2-7250-lc2-1|asic1|Ethernet152|0": { "scheduler": "scheduler.0" }, - "Ethernet48|0": { + "str2-7250-lc2-1|asic1|Ethernet152|1": { "scheduler": "scheduler.0" }, - "Ethernet56|0": { + "str2-7250-lc2-1|asic1|Ethernet152|2": { "scheduler": "scheduler.0" }, - "Ethernet64|0": { + "str2-7250-lc2-1|asic1|Ethernet152|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet152|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet152|5": { "scheduler": "scheduler.0" }, - "Ethernet72|0": { + "str2-7250-lc2-1|asic1|Ethernet152|6": { "scheduler": "scheduler.0" }, - "Ethernet80|0": { + "str2-7250-lc2-1|asic1|Ethernet160|0": { "scheduler": "scheduler.0" }, - "Ethernet88|0": { + "str2-7250-lc2-1|asic1|Ethernet160|1": { "scheduler": "scheduler.0" }, - "Ethernet96|0": { + "str2-7250-lc2-1|asic1|Ethernet160|2": { "scheduler": "scheduler.0" }, - "Ethernet104|0": { + "str2-7250-lc2-1|asic1|Ethernet160|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet160|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet160|5": { "scheduler": "scheduler.0" }, - "Ethernet112|0": { + "str2-7250-lc2-1|asic1|Ethernet160|6": { "scheduler": "scheduler.0" }, - "Ethernet120|0": { + "str2-7250-lc2-1|asic1|Ethernet168|0": { "scheduler": "scheduler.0" }, - "Ethernet128|0": { + "str2-7250-lc2-1|asic1|Ethernet168|1": { "scheduler": "scheduler.0" }, - "Ethernet136|0": { + "str2-7250-lc2-1|asic1|Ethernet168|2": { "scheduler": "scheduler.0" }, - "Ethernet0|1": { + "str2-7250-lc2-1|asic1|Ethernet168|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet168|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet168|5": { "scheduler": "scheduler.0" }, - "Ethernet8|1": { + "str2-7250-lc2-1|asic1|Ethernet168|6": { "scheduler": "scheduler.0" }, - "Ethernet16|1": { + "str2-7250-lc2-1|asic1|Ethernet176|0": { "scheduler": "scheduler.0" }, - "Ethernet24|1": { + "str2-7250-lc2-1|asic1|Ethernet176|1": { "scheduler": "scheduler.0" }, - "Ethernet32|1": { + "str2-7250-lc2-1|asic1|Ethernet176|2": { "scheduler": "scheduler.0" }, - "Ethernet40|1": { + "str2-7250-lc2-1|asic1|Ethernet176|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet176|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet176|5": { "scheduler": "scheduler.0" }, - "Ethernet48|1": { + "str2-7250-lc2-1|asic1|Ethernet176|6": { "scheduler": "scheduler.0" }, - "Ethernet56|1": { + "str2-7250-lc2-1|asic1|Ethernet184|0": { "scheduler": "scheduler.0" }, - "Ethernet64|1": { + "str2-7250-lc2-1|asic1|Ethernet184|1": { "scheduler": "scheduler.0" }, - "Ethernet72|1": { + "str2-7250-lc2-1|asic1|Ethernet184|2": { "scheduler": "scheduler.0" }, - "Ethernet80|1": { + "str2-7250-lc2-1|asic1|Ethernet184|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet184|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet184|5": { "scheduler": "scheduler.0" }, - "Ethernet88|1": { + "str2-7250-lc2-1|asic1|Ethernet184|6": { "scheduler": "scheduler.0" }, - "Ethernet96|1": { + "str2-7250-lc2-1|asic1|Ethernet192|0": { "scheduler": "scheduler.0" }, - "Ethernet104|1": { + "str2-7250-lc2-1|asic1|Ethernet192|1": { "scheduler": "scheduler.0" }, - "Ethernet112|1": { + "str2-7250-lc2-1|asic1|Ethernet192|2": { "scheduler": "scheduler.0" }, - "Ethernet120|1": { + "str2-7250-lc2-1|asic1|Ethernet192|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet192|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet192|5": { "scheduler": "scheduler.0" }, - "Ethernet128|1": { + "str2-7250-lc2-1|asic1|Ethernet192|6": { "scheduler": "scheduler.0" }, - "Ethernet136|1": { + "str2-7250-lc2-1|asic1|Ethernet200|0": { "scheduler": "scheduler.0" }, - "Ethernet0|2": { + "str2-7250-lc2-1|asic1|Ethernet200|1": { "scheduler": "scheduler.0" }, - "Ethernet8|2": { + "str2-7250-lc2-1|asic1|Ethernet200|2": { "scheduler": "scheduler.0" }, - "Ethernet16|2": { + "str2-7250-lc2-1|asic1|Ethernet200|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet200|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet200|5": { "scheduler": "scheduler.0" }, - "Ethernet24|2": { + "str2-7250-lc2-1|asic1|Ethernet200|6": { "scheduler": "scheduler.0" }, - "Ethernet32|2": { + "str2-7250-lc2-1|asic1|Ethernet208|0": { "scheduler": "scheduler.0" }, - "Ethernet40|2": { + "str2-7250-lc2-1|asic1|Ethernet208|1": { "scheduler": "scheduler.0" }, - "Ethernet48|2": { + "str2-7250-lc2-1|asic1|Ethernet208|2": { "scheduler": "scheduler.0" }, - "Ethernet56|2": { + "str2-7250-lc2-1|asic1|Ethernet208|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet208|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet208|5": { "scheduler": "scheduler.0" }, - "Ethernet64|2": { + "str2-7250-lc2-1|asic1|Ethernet208|6": { "scheduler": "scheduler.0" }, - "Ethernet72|2": { + "str2-7250-lc2-1|asic1|Ethernet216|0": { "scheduler": "scheduler.0" }, - "Ethernet80|2": { + "str2-7250-lc2-1|asic1|Ethernet216|1": { "scheduler": "scheduler.0" }, - "Ethernet88|2": { + "str2-7250-lc2-1|asic1|Ethernet216|2": { "scheduler": "scheduler.0" }, - "Ethernet96|2": { + "str2-7250-lc2-1|asic1|Ethernet216|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet216|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet216|5": { "scheduler": "scheduler.0" }, - "Ethernet104|2": { + "str2-7250-lc2-1|asic1|Ethernet216|6": { "scheduler": "scheduler.0" }, - "Ethernet112|2": { + "str2-7250-lc2-1|asic1|Ethernet224|0": { "scheduler": "scheduler.0" }, - "Ethernet120|2": { + "str2-7250-lc2-1|asic1|Ethernet224|1": { "scheduler": "scheduler.0" }, - "Ethernet128|2": { + "str2-7250-lc2-1|asic1|Ethernet224|2": { "scheduler": "scheduler.0" }, - "Ethernet136|2": { + "str2-7250-lc2-1|asic1|Ethernet224|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet224|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet224|5": { "scheduler": "scheduler.0" }, - "Ethernet0|5": { + "str2-7250-lc2-1|asic1|Ethernet224|6": { "scheduler": "scheduler.0" }, - "Ethernet8|5": { + "str2-7250-lc2-1|asic1|Ethernet232|0": { "scheduler": "scheduler.0" }, - "Ethernet16|5": { + "str2-7250-lc2-1|asic1|Ethernet232|1": { "scheduler": "scheduler.0" }, - "Ethernet24|5": { + "str2-7250-lc2-1|asic1|Ethernet232|2": { "scheduler": "scheduler.0" }, - "Ethernet32|5": { + "str2-7250-lc2-1|asic1|Ethernet232|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet232|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet232|5": { "scheduler": "scheduler.0" }, - "Ethernet40|5": { + "str2-7250-lc2-1|asic1|Ethernet232|6": { "scheduler": "scheduler.0" }, - "Ethernet48|5": { + "str2-7250-lc2-1|asic1|Ethernet240|0": { "scheduler": "scheduler.0" }, - "Ethernet56|5": { + "str2-7250-lc2-1|asic1|Ethernet240|1": { "scheduler": "scheduler.0" }, - "Ethernet64|5": { + "str2-7250-lc2-1|asic1|Ethernet240|2": { "scheduler": "scheduler.0" }, - "Ethernet72|5": { + "str2-7250-lc2-1|asic1|Ethernet240|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet240|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet240|5": { "scheduler": "scheduler.0" }, - "Ethernet80|5": { + "str2-7250-lc2-1|asic1|Ethernet240|6": { "scheduler": "scheduler.0" }, - "Ethernet88|5": { + "str2-7250-lc2-1|asic1|Ethernet248|0": { "scheduler": "scheduler.0" }, - "Ethernet96|5": { + "str2-7250-lc2-1|asic1|Ethernet248|1": { "scheduler": "scheduler.0" }, - "Ethernet104|5": { + "str2-7250-lc2-1|asic1|Ethernet248|2": { "scheduler": "scheduler.0" }, - "Ethernet112|5": { + "str2-7250-lc2-1|asic1|Ethernet248|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet248|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet248|5": { "scheduler": "scheduler.0" }, - "Ethernet120|5": { + "str2-7250-lc2-1|asic1|Ethernet248|6": { "scheduler": "scheduler.0" }, - "Ethernet128|5": { + "str2-7250-lc2-1|asic1|Ethernet256|0": { "scheduler": "scheduler.0" }, - "Ethernet136|5": { + "str2-7250-lc2-1|asic1|Ethernet256|1": { "scheduler": "scheduler.0" }, - "Ethernet0|6": { + "str2-7250-lc2-1|asic1|Ethernet256|2": { "scheduler": "scheduler.0" }, - "Ethernet8|6": { + "str2-7250-lc2-1|asic1|Ethernet256|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet256|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet256|5": { "scheduler": "scheduler.0" }, - "Ethernet16|6": { + "str2-7250-lc2-1|asic1|Ethernet256|6": { "scheduler": "scheduler.0" }, - "Ethernet24|6": { + "str2-7250-lc2-1|asic1|Ethernet264|0": { "scheduler": "scheduler.0" }, - "Ethernet32|6": { + "str2-7250-lc2-1|asic1|Ethernet264|1": { "scheduler": "scheduler.0" }, - "Ethernet40|6": { + "str2-7250-lc2-1|asic1|Ethernet264|2": { "scheduler": "scheduler.0" }, - "Ethernet48|6": { + "str2-7250-lc2-1|asic1|Ethernet264|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet264|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet264|5": { "scheduler": "scheduler.0" }, - "Ethernet56|6": { + "str2-7250-lc2-1|asic1|Ethernet264|6": { "scheduler": "scheduler.0" }, - "Ethernet64|6": { + "str2-7250-lc2-1|asic1|Ethernet272|0": { "scheduler": "scheduler.0" }, - "Ethernet72|6": { + "str2-7250-lc2-1|asic1|Ethernet272|1": { "scheduler": "scheduler.0" }, - "Ethernet80|6": { + "str2-7250-lc2-1|asic1|Ethernet272|2": { "scheduler": "scheduler.0" }, - "Ethernet88|6": { + "str2-7250-lc2-1|asic1|Ethernet272|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet272|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet272|5": { "scheduler": "scheduler.0" }, - "Ethernet96|6": { + "str2-7250-lc2-1|asic1|Ethernet272|6": { "scheduler": "scheduler.0" }, - "Ethernet104|6": { + "str2-7250-lc2-1|asic1|Ethernet280|0": { "scheduler": "scheduler.0" }, - "Ethernet112|6": { + "str2-7250-lc2-1|asic1|Ethernet280|1": { "scheduler": "scheduler.0" }, - "Ethernet120|6": { + "str2-7250-lc2-1|asic1|Ethernet280|2": { "scheduler": "scheduler.0" }, - "Ethernet128|6": { + "str2-7250-lc2-1|asic1|Ethernet280|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet280|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet280|5": { "scheduler": "scheduler.0" }, - "Ethernet136|6": { + "str2-7250-lc2-1|asic1|Ethernet280|6": { "scheduler": "scheduler.0" } } diff --git a/src/sonic-config-engine/tests/sample_output/py3/arista7260-t1.config.bcm b/src/sonic-config-engine/tests/sample_output/py3/arista7260-t1.config.bcm index a76c2173f436..c3323f545aa4 100644 --- a/src/sonic-config-engine/tests/sample_output/py3/arista7260-t1.config.bcm +++ b/src/sonic-config-engine/tests/sample_output/py3/arista7260-t1.config.bcm @@ -2,6 +2,7 @@ l3_alpm_hit_skip=1 mmu_init_config="MSFT-TH2-Tier1" +sai_tunnel_support=1 hybrid_pfc_deadlock_enable=1 pfc_deadlock_seq_control=1 diff --git a/src/sonic-config-engine/tests/sample_output/py3/qos-arista7800r3-48cq2-lc.json b/src/sonic-config-engine/tests/sample_output/py3/qos-arista7800r3-48cq2-lc.json index 7aecbdbd90e5..32d49aa9709c 100644 --- a/src/sonic-config-engine/tests/sample_output/py3/qos-arista7800r3-48cq2-lc.json +++ b/src/sonic-config-engine/tests/sample_output/py3/qos-arista7800r3-48cq2-lc.json @@ -496,1040 +496,3174 @@ } }, "QUEUE": { - "Ethernet0|3": { + "dut-lc3|Asic0|Ethernet0|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet4|3": { + "dut-lc3|Asic0|Ethernet4|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet8|3": { + "dut-lc3|Asic0|Ethernet8|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet12|3": { + "dut-lc3|Asic0|Ethernet12|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet16|3": { + "dut-lc3|Asic0|Ethernet16|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet20|3": { + "dut-lc3|Asic0|Ethernet20|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet24|3": { + "dut-lc3|Asic0|Ethernet24|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet28|3": { + "dut-lc3|Asic0|Ethernet28|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet32|3": { + "dut-lc3|Asic0|Ethernet32|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet36|3": { + "dut-lc3|Asic0|Ethernet36|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet40|3": { + "dut-lc3|Asic0|Ethernet40|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet44|3": { + "dut-lc3|Asic0|Ethernet44|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet48|3": { + "dut-lc3|Asic0|Ethernet48|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet52|3": { + "dut-lc3|Asic0|Ethernet52|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet56|3": { + "dut-lc3|Asic0|Ethernet56|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet60|3": { + "dut-lc3|Asic0|Ethernet60|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet64|3": { + "dut-lc3|Asic0|Ethernet64|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet68|3": { + "dut-lc3|Asic0|Ethernet68|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet72|3": { + "dut-lc3|Asic0|Ethernet72|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet76|3": { + "dut-lc3|Asic0|Ethernet76|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet80|3": { + "dut-lc3|Asic0|Ethernet80|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet84|3": { + "dut-lc3|Asic0|Ethernet84|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet88|3": { + "dut-lc3|Asic0|Ethernet88|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet92|3": { + "dut-lc3|Asic0|Ethernet92|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet96|3": { + "dut-lc3|Asic0|Ethernet96|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet100|3": { + "dut-lc3|Asic0|Ethernet100|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet104|3": { + "dut-lc3|Asic0|Ethernet104|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet108|3": { + "dut-lc3|Asic0|Ethernet108|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet112|3": { + "dut-lc3|Asic0|Ethernet112|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet116|3": { + "dut-lc3|Asic0|Ethernet116|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet120|3": { + "dut-lc3|Asic0|Ethernet120|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet124|3": { + "dut-lc3|Asic0|Ethernet124|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet128|3": { + "dut-lc3|Asic0|Ethernet128|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet132|3": { + "dut-lc3|Asic0|Ethernet132|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet136|3": { + "dut-lc3|Asic0|Ethernet136|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet140|3": { + "dut-lc3|Asic0|Ethernet140|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet144|3": { + "dut-lc3|Asic0|Ethernet144|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet148|3": { + "dut-lc3|Asic0|Ethernet148|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet152|3": { + "dut-lc3|Asic0|Ethernet152|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet156|3": { + "dut-lc3|Asic0|Ethernet156|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet164|3": { + "dut-lc3|Asic0|Ethernet160|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet176|3": { + "dut-lc3|Asic0|Ethernet164|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet180|3": { + "dut-lc3|Asic0|Ethernet168|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet184|3": { + "dut-lc3|Asic0|Ethernet172|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet188|3": { + "dut-lc3|Asic0|Ethernet176|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet0|4": { + "dut-lc3|Asic0|Ethernet180|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet4|4": { + "dut-lc3|Asic0|Ethernet184|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet8|4": { + "dut-lc3|Asic0|Ethernet188|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet12|4": { + "dut-lc4|Asic0|Ethernet0|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet16|4": { + "dut-lc4|Asic0|Ethernet4|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet20|4": { + "dut-lc4|Asic0|Ethernet8|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet24|4": { + "dut-lc4|Asic0|Ethernet12|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet28|4": { + "dut-lc4|Asic0|Ethernet16|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet32|4": { + "dut-lc4|Asic0|Ethernet20|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet36|4": { + "dut-lc4|Asic0|Ethernet24|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet40|4": { + "dut-lc4|Asic0|Ethernet28|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet44|4": { + "dut-lc4|Asic0|Ethernet32|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet48|4": { + "dut-lc4|Asic0|Ethernet36|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet52|4": { + "dut-lc4|Asic0|Ethernet40|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet56|4": { + "dut-lc4|Asic0|Ethernet44|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet60|4": { + "dut-lc4|Asic0|Ethernet48|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet64|4": { + "dut-lc4|Asic0|Ethernet52|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet68|4": { + "dut-lc4|Asic0|Ethernet56|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet72|4": { + "dut-lc4|Asic0|Ethernet60|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet76|4": { + "dut-lc4|Asic0|Ethernet64|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet80|4": { + "dut-lc4|Asic0|Ethernet68|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet84|4": { + "dut-lc4|Asic0|Ethernet72|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet88|4": { + "dut-lc4|Asic0|Ethernet76|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet92|4": { + "dut-lc4|Asic0|Ethernet80|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet96|4": { + "dut-lc4|Asic0|Ethernet84|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet100|4": { + "dut-lc4|Asic0|Ethernet88|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet104|4": { + "dut-lc4|Asic0|Ethernet92|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet108|4": { + "dut-lc4|Asic0|Ethernet96|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet112|4": { + "dut-lc4|Asic0|Ethernet100|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet116|4": { + "dut-lc4|Asic0|Ethernet104|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet120|4": { + "dut-lc4|Asic0|Ethernet108|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet124|4": { + "dut-lc4|Asic0|Ethernet112|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet128|4": { + "dut-lc4|Asic0|Ethernet116|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet132|4": { + "dut-lc4|Asic0|Ethernet120|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet136|4": { + "dut-lc4|Asic0|Ethernet124|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet140|4": { + "dut-lc4|Asic0|Ethernet128|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet144|4": { + "dut-lc4|Asic0|Ethernet132|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet148|4": { + "dut-lc4|Asic0|Ethernet136|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet152|4": { + "dut-lc4|Asic0|Ethernet140|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet156|4": { + "dut-lc4|Asic0|Ethernet144|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet164|4": { + "dut-lc4|Asic0|Ethernet148|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet176|4": { + "dut-lc4|Asic0|Ethernet152|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet180|4": { + "dut-lc4|Asic0|Ethernet156|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet184|4": { + "dut-lc4|Asic0|Ethernet160|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet188|4": { + "dut-lc4|Asic0|Ethernet164|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet0|0": { + "dut-lc4|Asic0|Ethernet168|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet172|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet176|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet180|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet184|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet188|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet0|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet4|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet8|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet12|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet16|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet20|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet24|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet28|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet32|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet36|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet40|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet44|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet48|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet52|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet56|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet60|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet64|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet68|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet72|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet76|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet80|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet84|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet88|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet92|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet96|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet100|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet104|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet108|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet112|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet116|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet120|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet124|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet128|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet132|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet136|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet140|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet144|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet148|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet152|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet156|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet160|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet164|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet168|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet172|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet176|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet180|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet184|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet188|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet0|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet4|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet8|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet12|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet16|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet20|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet24|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet28|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet32|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet36|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet40|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet44|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet48|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet52|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet56|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet60|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet64|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet68|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet72|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet76|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet80|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet84|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet88|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet92|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet96|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet100|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet104|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet108|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet112|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet116|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet120|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet124|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet128|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet132|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet136|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet140|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet144|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet148|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet152|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet156|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet160|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet164|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet168|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet172|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet176|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet180|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet184|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet188|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet0|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet4|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet8|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet12|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet16|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet20|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet24|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet28|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet32|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet36|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet40|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet44|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet48|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet52|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet56|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet60|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet64|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet68|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet72|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet76|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet80|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet84|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet88|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet92|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet96|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet100|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet104|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet108|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet112|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet116|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet120|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet124|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet128|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet132|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet136|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet140|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet144|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet148|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet152|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet156|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet160|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet164|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet168|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet172|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet176|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet180|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet184|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet188|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet0|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet4|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet8|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet12|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet16|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet20|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet24|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet28|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet32|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet36|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet40|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet44|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet48|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet52|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet56|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet60|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet64|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet68|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet72|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet76|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet80|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet84|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet88|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet92|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet96|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet100|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet104|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet108|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet112|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet116|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet120|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet124|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet128|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet132|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet136|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet140|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet144|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet148|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet152|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet156|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet160|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet164|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet168|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet172|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet176|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet180|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet184|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet188|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet0|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet4|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet8|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet12|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet16|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet20|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet24|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet28|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet32|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet36|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet40|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet44|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet48|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet52|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet56|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet60|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet64|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet68|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet72|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet76|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet80|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet84|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet88|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet92|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet96|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet100|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet104|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet108|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet112|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet116|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet120|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet124|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet128|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet132|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet136|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet140|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet144|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet148|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet152|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet156|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet160|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet164|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet168|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet172|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet176|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet180|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet184|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet188|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet0|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet4|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet8|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet12|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet16|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet20|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet24|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet28|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet32|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet36|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet40|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet44|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet48|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet52|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet56|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet60|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet64|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet68|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet72|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet76|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet80|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet84|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet88|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet92|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet96|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet100|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet104|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet108|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet112|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet116|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet120|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet124|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet128|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet132|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet136|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet140|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet144|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet148|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet152|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet156|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet160|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet164|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet168|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet172|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet176|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet180|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet184|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet188|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet0|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet4|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet8|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet12|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet16|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet20|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet24|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet28|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet32|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet36|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet40|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet44|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet48|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet52|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet56|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet60|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet64|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet68|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet72|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet76|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet80|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet84|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet88|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet92|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet96|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet100|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet104|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet108|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet112|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet116|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet120|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet124|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet128|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet132|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet136|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet140|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet144|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet148|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet152|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet156|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet160|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet164|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet168|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet172|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet176|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet180|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet184|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet188|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet0|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet4|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet8|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet12|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet16|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet20|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet24|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet28|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet32|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet36|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet40|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet44|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet48|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet52|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet56|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet60|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet64|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet68|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet72|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet76|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet80|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet84|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet88|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet92|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet96|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet100|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet104|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet108|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet112|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet116|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet120|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet124|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet128|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet132|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet136|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet140|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet144|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet148|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet152|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet156|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet160|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet164|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet168|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet172|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet176|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet180|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet184|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet188|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet0|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet4|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet8|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet12|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet16|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet20|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet24|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet28|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet32|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet36|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet40|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet44|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet48|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet52|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet56|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet60|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet64|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet68|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet72|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet76|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet80|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet84|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet88|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet92|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet96|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet100|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet104|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet108|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet112|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet116|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet120|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet124|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet128|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet132|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet136|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet140|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet144|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet148|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet152|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet156|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet160|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet164|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet168|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet172|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet176|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet180|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet184|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet188|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet0|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet4|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet8|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet12|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet16|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet20|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet24|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet28|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet32|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet36|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet40|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet44|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet48|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet52|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet56|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet60|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet64|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet68|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet72|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet76|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet80|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet84|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet88|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet92|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet96|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet100|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet104|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet108|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet112|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet116|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet120|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet124|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet128|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet132|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet136|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet140|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet144|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet148|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet152|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet156|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet160|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet164|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet168|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet172|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet176|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet180|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet184|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet188|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet0|2": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet4|2": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet8|2": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet12|2": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet16|2": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet20|2": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet24|2": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet28|2": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet32|2": { "scheduler": "scheduler.0" }, - "Ethernet4|0": { + "dut-lc3|Asic0|Ethernet36|2": { "scheduler": "scheduler.0" }, - "Ethernet8|0": { + "dut-lc3|Asic0|Ethernet40|2": { "scheduler": "scheduler.0" }, - "Ethernet12|0": { + "dut-lc3|Asic0|Ethernet44|2": { "scheduler": "scheduler.0" }, - "Ethernet16|0": { + "dut-lc3|Asic0|Ethernet48|2": { "scheduler": "scheduler.0" }, - "Ethernet20|0": { + "dut-lc3|Asic0|Ethernet52|2": { "scheduler": "scheduler.0" }, - "Ethernet24|0": { + "dut-lc3|Asic0|Ethernet56|2": { "scheduler": "scheduler.0" }, - "Ethernet28|0": { + "dut-lc3|Asic0|Ethernet60|2": { "scheduler": "scheduler.0" }, - "Ethernet32|0": { + "dut-lc3|Asic0|Ethernet64|2": { "scheduler": "scheduler.0" }, - "Ethernet36|0": { + "dut-lc3|Asic0|Ethernet68|2": { "scheduler": "scheduler.0" }, - "Ethernet40|0": { + "dut-lc3|Asic0|Ethernet72|2": { "scheduler": "scheduler.0" }, - "Ethernet44|0": { + "dut-lc3|Asic0|Ethernet76|2": { "scheduler": "scheduler.0" }, - "Ethernet48|0": { + "dut-lc3|Asic0|Ethernet80|2": { "scheduler": "scheduler.0" }, - "Ethernet52|0": { + "dut-lc3|Asic0|Ethernet84|2": { "scheduler": "scheduler.0" }, - "Ethernet56|0": { + "dut-lc3|Asic0|Ethernet88|2": { "scheduler": "scheduler.0" }, - "Ethernet60|0": { + "dut-lc3|Asic0|Ethernet92|2": { "scheduler": "scheduler.0" }, - "Ethernet64|0": { + "dut-lc3|Asic0|Ethernet96|2": { "scheduler": "scheduler.0" }, - "Ethernet68|0": { + "dut-lc3|Asic0|Ethernet100|2": { "scheduler": "scheduler.0" }, - "Ethernet72|0": { + "dut-lc3|Asic0|Ethernet104|2": { "scheduler": "scheduler.0" }, - "Ethernet76|0": { + "dut-lc3|Asic0|Ethernet108|2": { "scheduler": "scheduler.0" }, - "Ethernet80|0": { + "dut-lc3|Asic0|Ethernet112|2": { "scheduler": "scheduler.0" }, - "Ethernet84|0": { + "dut-lc3|Asic0|Ethernet116|2": { "scheduler": "scheduler.0" }, - "Ethernet88|0": { + "dut-lc3|Asic0|Ethernet120|2": { "scheduler": "scheduler.0" }, - "Ethernet92|0": { + "dut-lc3|Asic0|Ethernet124|2": { "scheduler": "scheduler.0" }, - "Ethernet96|0": { + "dut-lc3|Asic0|Ethernet128|2": { "scheduler": "scheduler.0" }, - "Ethernet100|0": { + "dut-lc3|Asic0|Ethernet132|2": { "scheduler": "scheduler.0" }, - "Ethernet104|0": { + "dut-lc3|Asic0|Ethernet136|2": { "scheduler": "scheduler.0" }, - "Ethernet108|0": { + "dut-lc3|Asic0|Ethernet140|2": { "scheduler": "scheduler.0" }, - "Ethernet112|0": { + "dut-lc3|Asic0|Ethernet144|2": { "scheduler": "scheduler.0" }, - "Ethernet116|0": { + "dut-lc3|Asic0|Ethernet148|2": { "scheduler": "scheduler.0" }, - "Ethernet120|0": { + "dut-lc3|Asic0|Ethernet152|2": { "scheduler": "scheduler.0" }, - "Ethernet124|0": { + "dut-lc3|Asic0|Ethernet156|2": { "scheduler": "scheduler.0" }, - "Ethernet128|0": { + "dut-lc3|Asic0|Ethernet160|2": { "scheduler": "scheduler.0" }, - "Ethernet132|0": { + "dut-lc3|Asic0|Ethernet164|2": { "scheduler": "scheduler.0" }, - "Ethernet136|0": { + "dut-lc3|Asic0|Ethernet168|2": { "scheduler": "scheduler.0" }, - "Ethernet140|0": { + "dut-lc3|Asic0|Ethernet172|2": { "scheduler": "scheduler.0" }, - "Ethernet144|0": { + "dut-lc3|Asic0|Ethernet176|2": { "scheduler": "scheduler.0" }, - "Ethernet148|0": { + "dut-lc3|Asic0|Ethernet180|2": { "scheduler": "scheduler.0" }, - "Ethernet152|0": { + "dut-lc3|Asic0|Ethernet184|2": { "scheduler": "scheduler.0" }, - "Ethernet156|0": { + "dut-lc3|Asic0|Ethernet188|2": { "scheduler": "scheduler.0" }, - "Ethernet164|0": { + "dut-lc4|Asic0|Ethernet0|2": { "scheduler": "scheduler.0" }, - "Ethernet176|0": { + "dut-lc4|Asic0|Ethernet4|2": { "scheduler": "scheduler.0" }, - "Ethernet180|0": { + "dut-lc4|Asic0|Ethernet8|2": { "scheduler": "scheduler.0" }, - "Ethernet184|0": { + "dut-lc4|Asic0|Ethernet12|2": { "scheduler": "scheduler.0" }, - "Ethernet188|0": { + "dut-lc4|Asic0|Ethernet16|2": { "scheduler": "scheduler.0" }, - "Ethernet0|1": { + "dut-lc4|Asic0|Ethernet20|2": { "scheduler": "scheduler.0" }, - "Ethernet4|1": { + "dut-lc4|Asic0|Ethernet24|2": { "scheduler": "scheduler.0" }, - "Ethernet8|1": { + "dut-lc4|Asic0|Ethernet28|2": { "scheduler": "scheduler.0" }, - "Ethernet12|1": { + "dut-lc4|Asic0|Ethernet32|2": { "scheduler": "scheduler.0" }, - "Ethernet16|1": { + "dut-lc4|Asic0|Ethernet36|2": { "scheduler": "scheduler.0" }, - "Ethernet20|1": { + "dut-lc4|Asic0|Ethernet40|2": { "scheduler": "scheduler.0" }, - "Ethernet24|1": { + "dut-lc4|Asic0|Ethernet44|2": { "scheduler": "scheduler.0" }, - "Ethernet28|1": { + "dut-lc4|Asic0|Ethernet48|2": { "scheduler": "scheduler.0" }, - "Ethernet32|1": { + "dut-lc4|Asic0|Ethernet52|2": { "scheduler": "scheduler.0" }, - "Ethernet36|1": { + "dut-lc4|Asic0|Ethernet56|2": { "scheduler": "scheduler.0" }, - "Ethernet40|1": { + "dut-lc4|Asic0|Ethernet60|2": { "scheduler": "scheduler.0" }, - "Ethernet44|1": { + "dut-lc4|Asic0|Ethernet64|2": { "scheduler": "scheduler.0" }, - "Ethernet48|1": { + "dut-lc4|Asic0|Ethernet68|2": { "scheduler": "scheduler.0" }, - "Ethernet52|1": { + "dut-lc4|Asic0|Ethernet72|2": { "scheduler": "scheduler.0" }, - "Ethernet56|1": { + "dut-lc4|Asic0|Ethernet76|2": { "scheduler": "scheduler.0" }, - "Ethernet60|1": { + "dut-lc4|Asic0|Ethernet80|2": { "scheduler": "scheduler.0" }, - "Ethernet64|1": { + "dut-lc4|Asic0|Ethernet84|2": { "scheduler": "scheduler.0" }, - "Ethernet68|1": { + "dut-lc4|Asic0|Ethernet88|2": { "scheduler": "scheduler.0" }, - "Ethernet72|1": { + "dut-lc4|Asic0|Ethernet92|2": { "scheduler": "scheduler.0" }, - "Ethernet76|1": { + "dut-lc4|Asic0|Ethernet96|2": { "scheduler": "scheduler.0" }, - "Ethernet80|1": { + "dut-lc4|Asic0|Ethernet100|2": { "scheduler": "scheduler.0" }, - "Ethernet84|1": { + "dut-lc4|Asic0|Ethernet104|2": { "scheduler": "scheduler.0" }, - "Ethernet88|1": { + "dut-lc4|Asic0|Ethernet108|2": { "scheduler": "scheduler.0" }, - "Ethernet92|1": { + "dut-lc4|Asic0|Ethernet112|2": { "scheduler": "scheduler.0" }, - "Ethernet96|1": { + "dut-lc4|Asic0|Ethernet116|2": { "scheduler": "scheduler.0" }, - "Ethernet100|1": { + "dut-lc4|Asic0|Ethernet120|2": { "scheduler": "scheduler.0" }, - "Ethernet104|1": { + "dut-lc4|Asic0|Ethernet124|2": { "scheduler": "scheduler.0" }, - "Ethernet108|1": { + "dut-lc4|Asic0|Ethernet128|2": { "scheduler": "scheduler.0" }, - "Ethernet112|1": { + "dut-lc4|Asic0|Ethernet132|2": { "scheduler": "scheduler.0" }, - "Ethernet116|1": { + "dut-lc4|Asic0|Ethernet136|2": { "scheduler": "scheduler.0" }, - "Ethernet120|1": { + "dut-lc4|Asic0|Ethernet140|2": { "scheduler": "scheduler.0" }, - "Ethernet124|1": { + "dut-lc4|Asic0|Ethernet144|2": { "scheduler": "scheduler.0" }, - "Ethernet128|1": { + "dut-lc4|Asic0|Ethernet148|2": { "scheduler": "scheduler.0" }, - "Ethernet132|1": { + "dut-lc4|Asic0|Ethernet152|2": { "scheduler": "scheduler.0" }, - "Ethernet136|1": { + "dut-lc4|Asic0|Ethernet156|2": { "scheduler": "scheduler.0" }, - "Ethernet140|1": { + "dut-lc4|Asic0|Ethernet160|2": { "scheduler": "scheduler.0" }, - "Ethernet144|1": { + "dut-lc4|Asic0|Ethernet164|2": { "scheduler": "scheduler.0" }, - "Ethernet148|1": { + "dut-lc4|Asic0|Ethernet168|2": { "scheduler": "scheduler.0" }, - "Ethernet152|1": { + "dut-lc4|Asic0|Ethernet172|2": { "scheduler": "scheduler.0" }, - "Ethernet156|1": { + "dut-lc4|Asic0|Ethernet176|2": { "scheduler": "scheduler.0" }, - "Ethernet164|1": { + "dut-lc4|Asic0|Ethernet180|2": { "scheduler": "scheduler.0" }, - "Ethernet176|1": { + "dut-lc4|Asic0|Ethernet184|2": { "scheduler": "scheduler.0" }, - "Ethernet180|1": { + "dut-lc4|Asic0|Ethernet188|2": { "scheduler": "scheduler.0" }, - "Ethernet184|1": { + "dut-lc5|Asic0|Ethernet0|2": { "scheduler": "scheduler.0" }, - "Ethernet188|1": { + "dut-lc5|Asic0|Ethernet4|2": { "scheduler": "scheduler.0" }, - "Ethernet0|2": { + "dut-lc5|Asic0|Ethernet8|2": { "scheduler": "scheduler.0" }, - "Ethernet4|2": { + "dut-lc5|Asic0|Ethernet12|2": { "scheduler": "scheduler.0" }, - "Ethernet8|2": { + "dut-lc5|Asic0|Ethernet16|2": { "scheduler": "scheduler.0" }, - "Ethernet12|2": { + "dut-lc5|Asic0|Ethernet20|2": { "scheduler": "scheduler.0" }, - "Ethernet16|2": { + "dut-lc5|Asic0|Ethernet24|2": { "scheduler": "scheduler.0" }, - "Ethernet20|2": { + "dut-lc5|Asic0|Ethernet28|2": { "scheduler": "scheduler.0" }, - "Ethernet24|2": { + "dut-lc5|Asic0|Ethernet32|2": { "scheduler": "scheduler.0" }, - "Ethernet28|2": { + "dut-lc5|Asic0|Ethernet36|2": { "scheduler": "scheduler.0" }, - "Ethernet32|2": { + "dut-lc5|Asic0|Ethernet40|2": { "scheduler": "scheduler.0" }, - "Ethernet36|2": { + "dut-lc5|Asic0|Ethernet44|2": { "scheduler": "scheduler.0" }, - "Ethernet40|2": { + "dut-lc5|Asic0|Ethernet48|2": { "scheduler": "scheduler.0" }, - "Ethernet44|2": { + "dut-lc5|Asic0|Ethernet52|2": { "scheduler": "scheduler.0" }, - "Ethernet48|2": { + "dut-lc5|Asic0|Ethernet56|2": { "scheduler": "scheduler.0" }, - "Ethernet52|2": { + "dut-lc5|Asic0|Ethernet60|2": { "scheduler": "scheduler.0" }, - "Ethernet56|2": { + "dut-lc5|Asic0|Ethernet64|2": { "scheduler": "scheduler.0" }, - "Ethernet60|2": { + "dut-lc5|Asic0|Ethernet68|2": { "scheduler": "scheduler.0" }, - "Ethernet64|2": { + "dut-lc5|Asic0|Ethernet72|2": { "scheduler": "scheduler.0" }, - "Ethernet68|2": { + "dut-lc5|Asic0|Ethernet76|2": { "scheduler": "scheduler.0" }, - "Ethernet72|2": { + "dut-lc5|Asic0|Ethernet80|2": { "scheduler": "scheduler.0" }, - "Ethernet76|2": { + "dut-lc5|Asic0|Ethernet84|2": { "scheduler": "scheduler.0" }, - "Ethernet80|2": { + "dut-lc5|Asic0|Ethernet88|2": { "scheduler": "scheduler.0" }, - "Ethernet84|2": { + "dut-lc5|Asic0|Ethernet92|2": { "scheduler": "scheduler.0" }, - "Ethernet88|2": { + "dut-lc5|Asic0|Ethernet96|2": { "scheduler": "scheduler.0" }, - "Ethernet92|2": { + "dut-lc5|Asic0|Ethernet100|2": { "scheduler": "scheduler.0" }, - "Ethernet96|2": { + "dut-lc5|Asic0|Ethernet104|2": { "scheduler": "scheduler.0" }, - "Ethernet100|2": { + "dut-lc5|Asic0|Ethernet108|2": { "scheduler": "scheduler.0" }, - "Ethernet104|2": { + "dut-lc5|Asic0|Ethernet112|2": { "scheduler": "scheduler.0" }, - "Ethernet108|2": { + "dut-lc5|Asic0|Ethernet116|2": { "scheduler": "scheduler.0" }, - "Ethernet112|2": { + "dut-lc5|Asic0|Ethernet120|2": { "scheduler": "scheduler.0" }, - "Ethernet116|2": { + "dut-lc5|Asic0|Ethernet124|2": { "scheduler": "scheduler.0" }, - "Ethernet120|2": { + "dut-lc5|Asic0|Ethernet128|2": { "scheduler": "scheduler.0" }, - "Ethernet124|2": { + "dut-lc5|Asic0|Ethernet132|2": { "scheduler": "scheduler.0" }, - "Ethernet128|2": { + "dut-lc5|Asic0|Ethernet136|2": { "scheduler": "scheduler.0" }, - "Ethernet132|2": { + "dut-lc5|Asic0|Ethernet140|2": { "scheduler": "scheduler.0" }, - "Ethernet136|2": { + "dut-lc5|Asic0|Ethernet144|2": { "scheduler": "scheduler.0" }, - "Ethernet140|2": { + "dut-lc5|Asic0|Ethernet148|2": { "scheduler": "scheduler.0" }, - "Ethernet144|2": { + "dut-lc5|Asic0|Ethernet152|2": { "scheduler": "scheduler.0" }, - "Ethernet148|2": { + "dut-lc5|Asic0|Ethernet156|2": { "scheduler": "scheduler.0" }, - "Ethernet152|2": { + "dut-lc5|Asic0|Ethernet160|2": { "scheduler": "scheduler.0" }, - "Ethernet156|2": { + "dut-lc5|Asic0|Ethernet164|2": { "scheduler": "scheduler.0" }, - "Ethernet164|2": { + "dut-lc5|Asic0|Ethernet168|2": { "scheduler": "scheduler.0" }, - "Ethernet176|2": { + "dut-lc5|Asic0|Ethernet172|2": { "scheduler": "scheduler.0" }, - "Ethernet180|2": { + "dut-lc5|Asic0|Ethernet176|2": { "scheduler": "scheduler.0" }, - "Ethernet184|2": { + "dut-lc5|Asic0|Ethernet180|2": { "scheduler": "scheduler.0" }, - "Ethernet188|2": { + "dut-lc5|Asic0|Ethernet184|2": { "scheduler": "scheduler.0" }, - "Ethernet0|5": { + "dut-lc5|Asic0|Ethernet188|2": { "scheduler": "scheduler.0" }, - "Ethernet4|5": { + "dut-lc3|Asic0|Ethernet0|5": { "scheduler": "scheduler.0" }, - "Ethernet8|5": { + "dut-lc3|Asic0|Ethernet4|5": { "scheduler": "scheduler.0" }, - "Ethernet12|5": { + "dut-lc3|Asic0|Ethernet8|5": { "scheduler": "scheduler.0" }, - "Ethernet16|5": { + "dut-lc3|Asic0|Ethernet12|5": { "scheduler": "scheduler.0" }, - "Ethernet20|5": { + "dut-lc3|Asic0|Ethernet16|5": { "scheduler": "scheduler.0" }, - "Ethernet24|5": { + "dut-lc3|Asic0|Ethernet20|5": { "scheduler": "scheduler.0" }, - "Ethernet28|5": { + "dut-lc3|Asic0|Ethernet24|5": { "scheduler": "scheduler.0" }, - "Ethernet32|5": { + "dut-lc3|Asic0|Ethernet28|5": { "scheduler": "scheduler.0" }, - "Ethernet36|5": { + "dut-lc3|Asic0|Ethernet32|5": { "scheduler": "scheduler.0" }, - "Ethernet40|5": { + "dut-lc3|Asic0|Ethernet36|5": { "scheduler": "scheduler.0" }, - "Ethernet44|5": { + "dut-lc3|Asic0|Ethernet40|5": { "scheduler": "scheduler.0" }, - "Ethernet48|5": { + "dut-lc3|Asic0|Ethernet44|5": { "scheduler": "scheduler.0" }, - "Ethernet52|5": { + "dut-lc3|Asic0|Ethernet48|5": { "scheduler": "scheduler.0" }, - "Ethernet56|5": { + "dut-lc3|Asic0|Ethernet52|5": { "scheduler": "scheduler.0" }, - "Ethernet60|5": { + "dut-lc3|Asic0|Ethernet56|5": { "scheduler": "scheduler.0" }, - "Ethernet64|5": { + "dut-lc3|Asic0|Ethernet60|5": { "scheduler": "scheduler.0" }, - "Ethernet68|5": { + "dut-lc3|Asic0|Ethernet64|5": { "scheduler": "scheduler.0" }, - "Ethernet72|5": { + "dut-lc3|Asic0|Ethernet68|5": { "scheduler": "scheduler.0" }, - "Ethernet76|5": { + "dut-lc3|Asic0|Ethernet72|5": { "scheduler": "scheduler.0" }, - "Ethernet80|5": { + "dut-lc3|Asic0|Ethernet76|5": { "scheduler": "scheduler.0" }, - "Ethernet84|5": { + "dut-lc3|Asic0|Ethernet80|5": { "scheduler": "scheduler.0" }, - "Ethernet88|5": { + "dut-lc3|Asic0|Ethernet84|5": { "scheduler": "scheduler.0" }, - "Ethernet92|5": { + "dut-lc3|Asic0|Ethernet88|5": { "scheduler": "scheduler.0" }, - "Ethernet96|5": { + "dut-lc3|Asic0|Ethernet92|5": { "scheduler": "scheduler.0" }, - "Ethernet100|5": { + "dut-lc3|Asic0|Ethernet96|5": { "scheduler": "scheduler.0" }, - "Ethernet104|5": { + "dut-lc3|Asic0|Ethernet100|5": { "scheduler": "scheduler.0" }, - "Ethernet108|5": { + "dut-lc3|Asic0|Ethernet104|5": { "scheduler": "scheduler.0" }, - "Ethernet112|5": { + "dut-lc3|Asic0|Ethernet108|5": { "scheduler": "scheduler.0" }, - "Ethernet116|5": { + "dut-lc3|Asic0|Ethernet112|5": { "scheduler": "scheduler.0" }, - "Ethernet120|5": { + "dut-lc3|Asic0|Ethernet116|5": { "scheduler": "scheduler.0" }, - "Ethernet124|5": { + "dut-lc3|Asic0|Ethernet120|5": { "scheduler": "scheduler.0" }, - "Ethernet128|5": { + "dut-lc3|Asic0|Ethernet124|5": { "scheduler": "scheduler.0" }, - "Ethernet132|5": { + "dut-lc3|Asic0|Ethernet128|5": { "scheduler": "scheduler.0" }, - "Ethernet136|5": { + "dut-lc3|Asic0|Ethernet132|5": { "scheduler": "scheduler.0" }, - "Ethernet140|5": { + "dut-lc3|Asic0|Ethernet136|5": { "scheduler": "scheduler.0" }, - "Ethernet144|5": { + "dut-lc3|Asic0|Ethernet140|5": { "scheduler": "scheduler.0" }, - "Ethernet148|5": { + "dut-lc3|Asic0|Ethernet144|5": { "scheduler": "scheduler.0" }, - "Ethernet152|5": { + "dut-lc3|Asic0|Ethernet148|5": { "scheduler": "scheduler.0" }, - "Ethernet156|5": { + "dut-lc3|Asic0|Ethernet152|5": { "scheduler": "scheduler.0" }, - "Ethernet164|5": { + "dut-lc3|Asic0|Ethernet156|5": { "scheduler": "scheduler.0" }, - "Ethernet176|5": { + "dut-lc3|Asic0|Ethernet160|5": { "scheduler": "scheduler.0" }, - "Ethernet180|5": { + "dut-lc3|Asic0|Ethernet164|5": { "scheduler": "scheduler.0" }, - "Ethernet184|5": { + "dut-lc3|Asic0|Ethernet168|5": { "scheduler": "scheduler.0" }, - "Ethernet188|5": { + "dut-lc3|Asic0|Ethernet172|5": { "scheduler": "scheduler.0" }, - "Ethernet0|6": { + "dut-lc3|Asic0|Ethernet176|5": { "scheduler": "scheduler.0" }, - "Ethernet4|6": { + "dut-lc3|Asic0|Ethernet180|5": { "scheduler": "scheduler.0" }, - "Ethernet8|6": { + "dut-lc3|Asic0|Ethernet184|5": { "scheduler": "scheduler.0" }, - "Ethernet12|6": { + "dut-lc3|Asic0|Ethernet188|5": { "scheduler": "scheduler.0" }, - "Ethernet16|6": { + "dut-lc4|Asic0|Ethernet0|5": { "scheduler": "scheduler.0" }, - "Ethernet20|6": { + "dut-lc4|Asic0|Ethernet4|5": { "scheduler": "scheduler.0" }, - "Ethernet24|6": { + "dut-lc4|Asic0|Ethernet8|5": { "scheduler": "scheduler.0" }, - "Ethernet28|6": { + "dut-lc4|Asic0|Ethernet12|5": { "scheduler": "scheduler.0" }, - "Ethernet32|6": { + "dut-lc4|Asic0|Ethernet16|5": { "scheduler": "scheduler.0" }, - "Ethernet36|6": { + "dut-lc4|Asic0|Ethernet20|5": { "scheduler": "scheduler.0" }, - "Ethernet40|6": { + "dut-lc4|Asic0|Ethernet24|5": { "scheduler": "scheduler.0" }, - "Ethernet44|6": { + "dut-lc4|Asic0|Ethernet28|5": { "scheduler": "scheduler.0" }, - "Ethernet48|6": { + "dut-lc4|Asic0|Ethernet32|5": { "scheduler": "scheduler.0" }, - "Ethernet52|6": { + "dut-lc4|Asic0|Ethernet36|5": { "scheduler": "scheduler.0" }, - "Ethernet56|6": { + "dut-lc4|Asic0|Ethernet40|5": { "scheduler": "scheduler.0" }, - "Ethernet60|6": { + "dut-lc4|Asic0|Ethernet44|5": { "scheduler": "scheduler.0" }, - "Ethernet64|6": { + "dut-lc4|Asic0|Ethernet48|5": { "scheduler": "scheduler.0" }, - "Ethernet68|6": { + "dut-lc4|Asic0|Ethernet52|5": { "scheduler": "scheduler.0" }, - "Ethernet72|6": { + "dut-lc4|Asic0|Ethernet56|5": { "scheduler": "scheduler.0" }, - "Ethernet76|6": { + "dut-lc4|Asic0|Ethernet60|5": { "scheduler": "scheduler.0" }, - "Ethernet80|6": { + "dut-lc4|Asic0|Ethernet64|5": { "scheduler": "scheduler.0" }, - "Ethernet84|6": { + "dut-lc4|Asic0|Ethernet68|5": { "scheduler": "scheduler.0" }, - "Ethernet88|6": { + "dut-lc4|Asic0|Ethernet72|5": { "scheduler": "scheduler.0" }, - "Ethernet92|6": { + "dut-lc4|Asic0|Ethernet76|5": { "scheduler": "scheduler.0" }, - "Ethernet96|6": { + "dut-lc4|Asic0|Ethernet80|5": { "scheduler": "scheduler.0" }, - "Ethernet100|6": { + "dut-lc4|Asic0|Ethernet84|5": { "scheduler": "scheduler.0" }, - "Ethernet104|6": { + "dut-lc4|Asic0|Ethernet88|5": { "scheduler": "scheduler.0" }, - "Ethernet108|6": { + "dut-lc4|Asic0|Ethernet92|5": { "scheduler": "scheduler.0" }, - "Ethernet112|6": { + "dut-lc4|Asic0|Ethernet96|5": { "scheduler": "scheduler.0" }, - "Ethernet116|6": { + "dut-lc4|Asic0|Ethernet100|5": { "scheduler": "scheduler.0" }, - "Ethernet120|6": { + "dut-lc4|Asic0|Ethernet104|5": { "scheduler": "scheduler.0" }, - "Ethernet124|6": { + "dut-lc4|Asic0|Ethernet108|5": { "scheduler": "scheduler.0" }, - "Ethernet128|6": { + "dut-lc4|Asic0|Ethernet112|5": { "scheduler": "scheduler.0" }, - "Ethernet132|6": { + "dut-lc4|Asic0|Ethernet116|5": { "scheduler": "scheduler.0" }, - "Ethernet136|6": { + "dut-lc4|Asic0|Ethernet120|5": { "scheduler": "scheduler.0" }, - "Ethernet140|6": { + "dut-lc4|Asic0|Ethernet124|5": { "scheduler": "scheduler.0" }, - "Ethernet144|6": { + "dut-lc4|Asic0|Ethernet128|5": { "scheduler": "scheduler.0" }, - "Ethernet148|6": { + "dut-lc4|Asic0|Ethernet132|5": { "scheduler": "scheduler.0" }, - "Ethernet152|6": { + "dut-lc4|Asic0|Ethernet136|5": { "scheduler": "scheduler.0" }, - "Ethernet156|6": { + "dut-lc4|Asic0|Ethernet140|5": { "scheduler": "scheduler.0" }, - "Ethernet164|6": { + "dut-lc4|Asic0|Ethernet144|5": { "scheduler": "scheduler.0" }, - "Ethernet176|6": { + "dut-lc4|Asic0|Ethernet148|5": { "scheduler": "scheduler.0" }, - "Ethernet180|6": { + "dut-lc4|Asic0|Ethernet152|5": { "scheduler": "scheduler.0" }, - "Ethernet184|6": { + "dut-lc4|Asic0|Ethernet156|5": { "scheduler": "scheduler.0" }, - "Ethernet188|6": { + "dut-lc4|Asic0|Ethernet160|5": { "scheduler": "scheduler.0" - } + }, + "dut-lc4|Asic0|Ethernet164|5": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet168|5": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet172|5": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet176|5": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet180|5": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet184|5": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet188|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet0|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet4|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet8|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet12|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet16|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet20|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet24|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet28|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet32|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet36|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet40|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet44|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet48|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet52|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet56|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet60|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet64|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet68|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet72|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet76|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet80|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet84|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet88|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet92|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet96|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet100|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet104|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet108|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet112|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet116|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet120|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet124|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet128|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet132|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet136|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet140|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet144|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet148|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet152|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet156|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet160|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet164|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet168|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet172|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet176|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet180|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet184|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet188|5": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet0|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet4|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet8|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet12|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet16|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet20|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet24|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet28|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet32|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet36|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet40|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet44|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet48|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet52|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet56|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet60|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet64|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet68|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet72|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet76|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet80|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet84|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet88|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet92|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet96|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet100|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet104|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet108|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet112|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet116|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet120|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet124|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet128|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet132|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet136|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet140|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet144|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet148|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet152|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet156|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet160|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet164|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet168|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet172|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet176|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet180|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet184|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet188|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet0|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet4|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet8|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet12|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet16|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet20|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet24|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet28|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet32|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet36|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet40|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet44|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet48|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet52|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet56|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet60|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet64|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet68|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet72|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet76|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet80|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet84|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet88|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet92|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet96|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet100|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet104|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet108|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet112|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet116|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet120|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet124|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet128|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet132|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet136|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet140|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet144|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet148|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet152|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet156|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet160|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet164|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet168|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet172|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet176|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet180|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet184|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet188|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet0|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet4|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet8|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet12|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet16|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet20|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet24|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet28|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet32|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet36|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet40|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet44|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet48|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet52|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet56|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet60|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet64|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet68|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet72|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet76|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet80|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet84|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet88|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet92|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet96|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet100|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet104|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet108|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet112|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet116|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet120|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet124|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet128|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet132|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet136|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet140|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet144|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet148|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet152|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet156|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet160|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet164|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet168|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet172|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet176|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet180|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet184|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet188|6": { + "scheduler": "scheduler.0" + } } } diff --git a/src/sonic-config-engine/tests/sample_output/py3/qos-arista7800r3-48cqm2-lc.json b/src/sonic-config-engine/tests/sample_output/py3/qos-arista7800r3-48cqm2-lc.json index 7aecbdbd90e5..32d49aa9709c 100644 --- a/src/sonic-config-engine/tests/sample_output/py3/qos-arista7800r3-48cqm2-lc.json +++ b/src/sonic-config-engine/tests/sample_output/py3/qos-arista7800r3-48cqm2-lc.json @@ -496,1040 +496,3174 @@ } }, "QUEUE": { - "Ethernet0|3": { + "dut-lc3|Asic0|Ethernet0|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet4|3": { + "dut-lc3|Asic0|Ethernet4|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet8|3": { + "dut-lc3|Asic0|Ethernet8|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet12|3": { + "dut-lc3|Asic0|Ethernet12|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet16|3": { + "dut-lc3|Asic0|Ethernet16|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet20|3": { + "dut-lc3|Asic0|Ethernet20|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet24|3": { + "dut-lc3|Asic0|Ethernet24|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet28|3": { + "dut-lc3|Asic0|Ethernet28|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet32|3": { + "dut-lc3|Asic0|Ethernet32|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet36|3": { + "dut-lc3|Asic0|Ethernet36|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet40|3": { + "dut-lc3|Asic0|Ethernet40|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet44|3": { + "dut-lc3|Asic0|Ethernet44|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet48|3": { + "dut-lc3|Asic0|Ethernet48|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet52|3": { + "dut-lc3|Asic0|Ethernet52|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet56|3": { + "dut-lc3|Asic0|Ethernet56|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet60|3": { + "dut-lc3|Asic0|Ethernet60|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet64|3": { + "dut-lc3|Asic0|Ethernet64|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet68|3": { + "dut-lc3|Asic0|Ethernet68|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet72|3": { + "dut-lc3|Asic0|Ethernet72|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet76|3": { + "dut-lc3|Asic0|Ethernet76|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet80|3": { + "dut-lc3|Asic0|Ethernet80|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet84|3": { + "dut-lc3|Asic0|Ethernet84|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet88|3": { + "dut-lc3|Asic0|Ethernet88|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet92|3": { + "dut-lc3|Asic0|Ethernet92|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet96|3": { + "dut-lc3|Asic0|Ethernet96|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet100|3": { + "dut-lc3|Asic0|Ethernet100|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet104|3": { + "dut-lc3|Asic0|Ethernet104|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet108|3": { + "dut-lc3|Asic0|Ethernet108|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet112|3": { + "dut-lc3|Asic0|Ethernet112|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet116|3": { + "dut-lc3|Asic0|Ethernet116|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet120|3": { + "dut-lc3|Asic0|Ethernet120|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet124|3": { + "dut-lc3|Asic0|Ethernet124|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet128|3": { + "dut-lc3|Asic0|Ethernet128|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet132|3": { + "dut-lc3|Asic0|Ethernet132|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet136|3": { + "dut-lc3|Asic0|Ethernet136|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet140|3": { + "dut-lc3|Asic0|Ethernet140|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet144|3": { + "dut-lc3|Asic0|Ethernet144|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet148|3": { + "dut-lc3|Asic0|Ethernet148|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet152|3": { + "dut-lc3|Asic0|Ethernet152|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet156|3": { + "dut-lc3|Asic0|Ethernet156|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet164|3": { + "dut-lc3|Asic0|Ethernet160|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet176|3": { + "dut-lc3|Asic0|Ethernet164|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet180|3": { + "dut-lc3|Asic0|Ethernet168|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet184|3": { + "dut-lc3|Asic0|Ethernet172|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet188|3": { + "dut-lc3|Asic0|Ethernet176|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet0|4": { + "dut-lc3|Asic0|Ethernet180|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet4|4": { + "dut-lc3|Asic0|Ethernet184|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet8|4": { + "dut-lc3|Asic0|Ethernet188|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet12|4": { + "dut-lc4|Asic0|Ethernet0|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet16|4": { + "dut-lc4|Asic0|Ethernet4|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet20|4": { + "dut-lc4|Asic0|Ethernet8|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet24|4": { + "dut-lc4|Asic0|Ethernet12|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet28|4": { + "dut-lc4|Asic0|Ethernet16|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet32|4": { + "dut-lc4|Asic0|Ethernet20|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet36|4": { + "dut-lc4|Asic0|Ethernet24|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet40|4": { + "dut-lc4|Asic0|Ethernet28|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet44|4": { + "dut-lc4|Asic0|Ethernet32|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet48|4": { + "dut-lc4|Asic0|Ethernet36|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet52|4": { + "dut-lc4|Asic0|Ethernet40|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet56|4": { + "dut-lc4|Asic0|Ethernet44|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet60|4": { + "dut-lc4|Asic0|Ethernet48|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet64|4": { + "dut-lc4|Asic0|Ethernet52|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet68|4": { + "dut-lc4|Asic0|Ethernet56|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet72|4": { + "dut-lc4|Asic0|Ethernet60|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet76|4": { + "dut-lc4|Asic0|Ethernet64|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet80|4": { + "dut-lc4|Asic0|Ethernet68|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet84|4": { + "dut-lc4|Asic0|Ethernet72|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet88|4": { + "dut-lc4|Asic0|Ethernet76|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet92|4": { + "dut-lc4|Asic0|Ethernet80|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet96|4": { + "dut-lc4|Asic0|Ethernet84|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet100|4": { + "dut-lc4|Asic0|Ethernet88|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet104|4": { + "dut-lc4|Asic0|Ethernet92|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet108|4": { + "dut-lc4|Asic0|Ethernet96|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet112|4": { + "dut-lc4|Asic0|Ethernet100|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet116|4": { + "dut-lc4|Asic0|Ethernet104|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet120|4": { + "dut-lc4|Asic0|Ethernet108|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet124|4": { + "dut-lc4|Asic0|Ethernet112|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet128|4": { + "dut-lc4|Asic0|Ethernet116|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet132|4": { + "dut-lc4|Asic0|Ethernet120|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet136|4": { + "dut-lc4|Asic0|Ethernet124|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet140|4": { + "dut-lc4|Asic0|Ethernet128|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet144|4": { + "dut-lc4|Asic0|Ethernet132|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet148|4": { + "dut-lc4|Asic0|Ethernet136|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet152|4": { + "dut-lc4|Asic0|Ethernet140|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet156|4": { + "dut-lc4|Asic0|Ethernet144|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet164|4": { + "dut-lc4|Asic0|Ethernet148|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet176|4": { + "dut-lc4|Asic0|Ethernet152|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet180|4": { + "dut-lc4|Asic0|Ethernet156|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet184|4": { + "dut-lc4|Asic0|Ethernet160|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet188|4": { + "dut-lc4|Asic0|Ethernet164|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet0|0": { + "dut-lc4|Asic0|Ethernet168|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet172|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet176|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet180|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet184|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet188|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet0|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet4|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet8|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet12|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet16|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet20|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet24|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet28|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet32|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet36|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet40|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet44|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet48|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet52|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet56|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet60|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet64|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet68|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet72|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet76|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet80|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet84|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet88|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet92|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet96|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet100|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet104|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet108|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet112|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet116|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet120|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet124|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet128|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet132|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet136|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet140|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet144|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet148|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet152|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet156|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet160|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet164|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet168|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet172|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet176|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet180|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet184|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet188|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet0|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet4|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet8|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet12|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet16|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet20|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet24|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet28|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet32|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet36|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet40|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet44|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet48|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet52|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet56|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet60|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet64|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet68|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet72|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet76|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet80|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet84|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet88|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet92|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet96|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet100|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet104|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet108|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet112|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet116|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet120|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet124|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet128|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet132|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet136|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet140|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet144|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet148|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet152|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet156|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet160|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet164|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet168|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet172|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet176|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet180|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet184|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet188|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet0|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet4|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet8|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet12|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet16|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet20|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet24|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet28|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet32|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet36|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet40|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet44|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet48|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet52|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet56|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet60|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet64|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet68|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet72|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet76|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet80|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet84|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet88|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet92|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet96|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet100|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet104|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet108|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet112|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet116|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet120|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet124|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet128|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet132|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet136|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet140|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet144|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet148|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet152|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet156|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet160|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet164|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet168|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet172|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet176|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet180|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet184|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc4|Asic0|Ethernet188|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet0|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet4|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet8|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet12|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet16|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet20|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet24|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet28|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet32|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet36|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet40|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet44|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet48|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet52|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet56|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet60|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet64|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet68|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet72|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet76|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet80|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet84|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet88|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet92|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet96|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet100|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet104|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet108|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet112|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet116|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet120|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet124|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet128|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet132|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet136|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet140|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet144|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet148|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet152|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet156|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet160|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet164|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet168|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet172|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet176|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet180|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet184|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc5|Asic0|Ethernet188|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "dut-lc3|Asic0|Ethernet0|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet4|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet8|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet12|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet16|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet20|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet24|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet28|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet32|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet36|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet40|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet44|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet48|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet52|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet56|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet60|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet64|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet68|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet72|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet76|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet80|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet84|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet88|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet92|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet96|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet100|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet104|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet108|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet112|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet116|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet120|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet124|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet128|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet132|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet136|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet140|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet144|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet148|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet152|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet156|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet160|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet164|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet168|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet172|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet176|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet180|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet184|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet188|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet0|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet4|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet8|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet12|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet16|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet20|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet24|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet28|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet32|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet36|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet40|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet44|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet48|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet52|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet56|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet60|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet64|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet68|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet72|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet76|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet80|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet84|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet88|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet92|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet96|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet100|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet104|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet108|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet112|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet116|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet120|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet124|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet128|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet132|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet136|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet140|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet144|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet148|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet152|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet156|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet160|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet164|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet168|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet172|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet176|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet180|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet184|0": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet188|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet0|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet4|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet8|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet12|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet16|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet20|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet24|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet28|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet32|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet36|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet40|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet44|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet48|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet52|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet56|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet60|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet64|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet68|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet72|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet76|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet80|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet84|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet88|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet92|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet96|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet100|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet104|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet108|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet112|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet116|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet120|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet124|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet128|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet132|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet136|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet140|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet144|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet148|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet152|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet156|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet160|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet164|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet168|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet172|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet176|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet180|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet184|0": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet188|0": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet0|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet4|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet8|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet12|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet16|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet20|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet24|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet28|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet32|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet36|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet40|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet44|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet48|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet52|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet56|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet60|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet64|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet68|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet72|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet76|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet80|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet84|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet88|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet92|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet96|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet100|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet104|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet108|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet112|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet116|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet120|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet124|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet128|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet132|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet136|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet140|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet144|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet148|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet152|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet156|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet160|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet164|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet168|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet172|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet176|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet180|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet184|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet188|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet0|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet4|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet8|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet12|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet16|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet20|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet24|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet28|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet32|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet36|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet40|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet44|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet48|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet52|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet56|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet60|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet64|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet68|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet72|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet76|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet80|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet84|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet88|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet92|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet96|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet100|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet104|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet108|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet112|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet116|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet120|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet124|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet128|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet132|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet136|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet140|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet144|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet148|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet152|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet156|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet160|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet164|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet168|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet172|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet176|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet180|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet184|1": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet188|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet0|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet4|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet8|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet12|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet16|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet20|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet24|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet28|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet32|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet36|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet40|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet44|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet48|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet52|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet56|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet60|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet64|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet68|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet72|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet76|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet80|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet84|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet88|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet92|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet96|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet100|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet104|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet108|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet112|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet116|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet120|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet124|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet128|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet132|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet136|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet140|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet144|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet148|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet152|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet156|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet160|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet164|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet168|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet172|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet176|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet180|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet184|1": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet188|1": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet0|2": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet4|2": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet8|2": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet12|2": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet16|2": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet20|2": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet24|2": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet28|2": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet32|2": { "scheduler": "scheduler.0" }, - "Ethernet4|0": { + "dut-lc3|Asic0|Ethernet36|2": { "scheduler": "scheduler.0" }, - "Ethernet8|0": { + "dut-lc3|Asic0|Ethernet40|2": { "scheduler": "scheduler.0" }, - "Ethernet12|0": { + "dut-lc3|Asic0|Ethernet44|2": { "scheduler": "scheduler.0" }, - "Ethernet16|0": { + "dut-lc3|Asic0|Ethernet48|2": { "scheduler": "scheduler.0" }, - "Ethernet20|0": { + "dut-lc3|Asic0|Ethernet52|2": { "scheduler": "scheduler.0" }, - "Ethernet24|0": { + "dut-lc3|Asic0|Ethernet56|2": { "scheduler": "scheduler.0" }, - "Ethernet28|0": { + "dut-lc3|Asic0|Ethernet60|2": { "scheduler": "scheduler.0" }, - "Ethernet32|0": { + "dut-lc3|Asic0|Ethernet64|2": { "scheduler": "scheduler.0" }, - "Ethernet36|0": { + "dut-lc3|Asic0|Ethernet68|2": { "scheduler": "scheduler.0" }, - "Ethernet40|0": { + "dut-lc3|Asic0|Ethernet72|2": { "scheduler": "scheduler.0" }, - "Ethernet44|0": { + "dut-lc3|Asic0|Ethernet76|2": { "scheduler": "scheduler.0" }, - "Ethernet48|0": { + "dut-lc3|Asic0|Ethernet80|2": { "scheduler": "scheduler.0" }, - "Ethernet52|0": { + "dut-lc3|Asic0|Ethernet84|2": { "scheduler": "scheduler.0" }, - "Ethernet56|0": { + "dut-lc3|Asic0|Ethernet88|2": { "scheduler": "scheduler.0" }, - "Ethernet60|0": { + "dut-lc3|Asic0|Ethernet92|2": { "scheduler": "scheduler.0" }, - "Ethernet64|0": { + "dut-lc3|Asic0|Ethernet96|2": { "scheduler": "scheduler.0" }, - "Ethernet68|0": { + "dut-lc3|Asic0|Ethernet100|2": { "scheduler": "scheduler.0" }, - "Ethernet72|0": { + "dut-lc3|Asic0|Ethernet104|2": { "scheduler": "scheduler.0" }, - "Ethernet76|0": { + "dut-lc3|Asic0|Ethernet108|2": { "scheduler": "scheduler.0" }, - "Ethernet80|0": { + "dut-lc3|Asic0|Ethernet112|2": { "scheduler": "scheduler.0" }, - "Ethernet84|0": { + "dut-lc3|Asic0|Ethernet116|2": { "scheduler": "scheduler.0" }, - "Ethernet88|0": { + "dut-lc3|Asic0|Ethernet120|2": { "scheduler": "scheduler.0" }, - "Ethernet92|0": { + "dut-lc3|Asic0|Ethernet124|2": { "scheduler": "scheduler.0" }, - "Ethernet96|0": { + "dut-lc3|Asic0|Ethernet128|2": { "scheduler": "scheduler.0" }, - "Ethernet100|0": { + "dut-lc3|Asic0|Ethernet132|2": { "scheduler": "scheduler.0" }, - "Ethernet104|0": { + "dut-lc3|Asic0|Ethernet136|2": { "scheduler": "scheduler.0" }, - "Ethernet108|0": { + "dut-lc3|Asic0|Ethernet140|2": { "scheduler": "scheduler.0" }, - "Ethernet112|0": { + "dut-lc3|Asic0|Ethernet144|2": { "scheduler": "scheduler.0" }, - "Ethernet116|0": { + "dut-lc3|Asic0|Ethernet148|2": { "scheduler": "scheduler.0" }, - "Ethernet120|0": { + "dut-lc3|Asic0|Ethernet152|2": { "scheduler": "scheduler.0" }, - "Ethernet124|0": { + "dut-lc3|Asic0|Ethernet156|2": { "scheduler": "scheduler.0" }, - "Ethernet128|0": { + "dut-lc3|Asic0|Ethernet160|2": { "scheduler": "scheduler.0" }, - "Ethernet132|0": { + "dut-lc3|Asic0|Ethernet164|2": { "scheduler": "scheduler.0" }, - "Ethernet136|0": { + "dut-lc3|Asic0|Ethernet168|2": { "scheduler": "scheduler.0" }, - "Ethernet140|0": { + "dut-lc3|Asic0|Ethernet172|2": { "scheduler": "scheduler.0" }, - "Ethernet144|0": { + "dut-lc3|Asic0|Ethernet176|2": { "scheduler": "scheduler.0" }, - "Ethernet148|0": { + "dut-lc3|Asic0|Ethernet180|2": { "scheduler": "scheduler.0" }, - "Ethernet152|0": { + "dut-lc3|Asic0|Ethernet184|2": { "scheduler": "scheduler.0" }, - "Ethernet156|0": { + "dut-lc3|Asic0|Ethernet188|2": { "scheduler": "scheduler.0" }, - "Ethernet164|0": { + "dut-lc4|Asic0|Ethernet0|2": { "scheduler": "scheduler.0" }, - "Ethernet176|0": { + "dut-lc4|Asic0|Ethernet4|2": { "scheduler": "scheduler.0" }, - "Ethernet180|0": { + "dut-lc4|Asic0|Ethernet8|2": { "scheduler": "scheduler.0" }, - "Ethernet184|0": { + "dut-lc4|Asic0|Ethernet12|2": { "scheduler": "scheduler.0" }, - "Ethernet188|0": { + "dut-lc4|Asic0|Ethernet16|2": { "scheduler": "scheduler.0" }, - "Ethernet0|1": { + "dut-lc4|Asic0|Ethernet20|2": { "scheduler": "scheduler.0" }, - "Ethernet4|1": { + "dut-lc4|Asic0|Ethernet24|2": { "scheduler": "scheduler.0" }, - "Ethernet8|1": { + "dut-lc4|Asic0|Ethernet28|2": { "scheduler": "scheduler.0" }, - "Ethernet12|1": { + "dut-lc4|Asic0|Ethernet32|2": { "scheduler": "scheduler.0" }, - "Ethernet16|1": { + "dut-lc4|Asic0|Ethernet36|2": { "scheduler": "scheduler.0" }, - "Ethernet20|1": { + "dut-lc4|Asic0|Ethernet40|2": { "scheduler": "scheduler.0" }, - "Ethernet24|1": { + "dut-lc4|Asic0|Ethernet44|2": { "scheduler": "scheduler.0" }, - "Ethernet28|1": { + "dut-lc4|Asic0|Ethernet48|2": { "scheduler": "scheduler.0" }, - "Ethernet32|1": { + "dut-lc4|Asic0|Ethernet52|2": { "scheduler": "scheduler.0" }, - "Ethernet36|1": { + "dut-lc4|Asic0|Ethernet56|2": { "scheduler": "scheduler.0" }, - "Ethernet40|1": { + "dut-lc4|Asic0|Ethernet60|2": { "scheduler": "scheduler.0" }, - "Ethernet44|1": { + "dut-lc4|Asic0|Ethernet64|2": { "scheduler": "scheduler.0" }, - "Ethernet48|1": { + "dut-lc4|Asic0|Ethernet68|2": { "scheduler": "scheduler.0" }, - "Ethernet52|1": { + "dut-lc4|Asic0|Ethernet72|2": { "scheduler": "scheduler.0" }, - "Ethernet56|1": { + "dut-lc4|Asic0|Ethernet76|2": { "scheduler": "scheduler.0" }, - "Ethernet60|1": { + "dut-lc4|Asic0|Ethernet80|2": { "scheduler": "scheduler.0" }, - "Ethernet64|1": { + "dut-lc4|Asic0|Ethernet84|2": { "scheduler": "scheduler.0" }, - "Ethernet68|1": { + "dut-lc4|Asic0|Ethernet88|2": { "scheduler": "scheduler.0" }, - "Ethernet72|1": { + "dut-lc4|Asic0|Ethernet92|2": { "scheduler": "scheduler.0" }, - "Ethernet76|1": { + "dut-lc4|Asic0|Ethernet96|2": { "scheduler": "scheduler.0" }, - "Ethernet80|1": { + "dut-lc4|Asic0|Ethernet100|2": { "scheduler": "scheduler.0" }, - "Ethernet84|1": { + "dut-lc4|Asic0|Ethernet104|2": { "scheduler": "scheduler.0" }, - "Ethernet88|1": { + "dut-lc4|Asic0|Ethernet108|2": { "scheduler": "scheduler.0" }, - "Ethernet92|1": { + "dut-lc4|Asic0|Ethernet112|2": { "scheduler": "scheduler.0" }, - "Ethernet96|1": { + "dut-lc4|Asic0|Ethernet116|2": { "scheduler": "scheduler.0" }, - "Ethernet100|1": { + "dut-lc4|Asic0|Ethernet120|2": { "scheduler": "scheduler.0" }, - "Ethernet104|1": { + "dut-lc4|Asic0|Ethernet124|2": { "scheduler": "scheduler.0" }, - "Ethernet108|1": { + "dut-lc4|Asic0|Ethernet128|2": { "scheduler": "scheduler.0" }, - "Ethernet112|1": { + "dut-lc4|Asic0|Ethernet132|2": { "scheduler": "scheduler.0" }, - "Ethernet116|1": { + "dut-lc4|Asic0|Ethernet136|2": { "scheduler": "scheduler.0" }, - "Ethernet120|1": { + "dut-lc4|Asic0|Ethernet140|2": { "scheduler": "scheduler.0" }, - "Ethernet124|1": { + "dut-lc4|Asic0|Ethernet144|2": { "scheduler": "scheduler.0" }, - "Ethernet128|1": { + "dut-lc4|Asic0|Ethernet148|2": { "scheduler": "scheduler.0" }, - "Ethernet132|1": { + "dut-lc4|Asic0|Ethernet152|2": { "scheduler": "scheduler.0" }, - "Ethernet136|1": { + "dut-lc4|Asic0|Ethernet156|2": { "scheduler": "scheduler.0" }, - "Ethernet140|1": { + "dut-lc4|Asic0|Ethernet160|2": { "scheduler": "scheduler.0" }, - "Ethernet144|1": { + "dut-lc4|Asic0|Ethernet164|2": { "scheduler": "scheduler.0" }, - "Ethernet148|1": { + "dut-lc4|Asic0|Ethernet168|2": { "scheduler": "scheduler.0" }, - "Ethernet152|1": { + "dut-lc4|Asic0|Ethernet172|2": { "scheduler": "scheduler.0" }, - "Ethernet156|1": { + "dut-lc4|Asic0|Ethernet176|2": { "scheduler": "scheduler.0" }, - "Ethernet164|1": { + "dut-lc4|Asic0|Ethernet180|2": { "scheduler": "scheduler.0" }, - "Ethernet176|1": { + "dut-lc4|Asic0|Ethernet184|2": { "scheduler": "scheduler.0" }, - "Ethernet180|1": { + "dut-lc4|Asic0|Ethernet188|2": { "scheduler": "scheduler.0" }, - "Ethernet184|1": { + "dut-lc5|Asic0|Ethernet0|2": { "scheduler": "scheduler.0" }, - "Ethernet188|1": { + "dut-lc5|Asic0|Ethernet4|2": { "scheduler": "scheduler.0" }, - "Ethernet0|2": { + "dut-lc5|Asic0|Ethernet8|2": { "scheduler": "scheduler.0" }, - "Ethernet4|2": { + "dut-lc5|Asic0|Ethernet12|2": { "scheduler": "scheduler.0" }, - "Ethernet8|2": { + "dut-lc5|Asic0|Ethernet16|2": { "scheduler": "scheduler.0" }, - "Ethernet12|2": { + "dut-lc5|Asic0|Ethernet20|2": { "scheduler": "scheduler.0" }, - "Ethernet16|2": { + "dut-lc5|Asic0|Ethernet24|2": { "scheduler": "scheduler.0" }, - "Ethernet20|2": { + "dut-lc5|Asic0|Ethernet28|2": { "scheduler": "scheduler.0" }, - "Ethernet24|2": { + "dut-lc5|Asic0|Ethernet32|2": { "scheduler": "scheduler.0" }, - "Ethernet28|2": { + "dut-lc5|Asic0|Ethernet36|2": { "scheduler": "scheduler.0" }, - "Ethernet32|2": { + "dut-lc5|Asic0|Ethernet40|2": { "scheduler": "scheduler.0" }, - "Ethernet36|2": { + "dut-lc5|Asic0|Ethernet44|2": { "scheduler": "scheduler.0" }, - "Ethernet40|2": { + "dut-lc5|Asic0|Ethernet48|2": { "scheduler": "scheduler.0" }, - "Ethernet44|2": { + "dut-lc5|Asic0|Ethernet52|2": { "scheduler": "scheduler.0" }, - "Ethernet48|2": { + "dut-lc5|Asic0|Ethernet56|2": { "scheduler": "scheduler.0" }, - "Ethernet52|2": { + "dut-lc5|Asic0|Ethernet60|2": { "scheduler": "scheduler.0" }, - "Ethernet56|2": { + "dut-lc5|Asic0|Ethernet64|2": { "scheduler": "scheduler.0" }, - "Ethernet60|2": { + "dut-lc5|Asic0|Ethernet68|2": { "scheduler": "scheduler.0" }, - "Ethernet64|2": { + "dut-lc5|Asic0|Ethernet72|2": { "scheduler": "scheduler.0" }, - "Ethernet68|2": { + "dut-lc5|Asic0|Ethernet76|2": { "scheduler": "scheduler.0" }, - "Ethernet72|2": { + "dut-lc5|Asic0|Ethernet80|2": { "scheduler": "scheduler.0" }, - "Ethernet76|2": { + "dut-lc5|Asic0|Ethernet84|2": { "scheduler": "scheduler.0" }, - "Ethernet80|2": { + "dut-lc5|Asic0|Ethernet88|2": { "scheduler": "scheduler.0" }, - "Ethernet84|2": { + "dut-lc5|Asic0|Ethernet92|2": { "scheduler": "scheduler.0" }, - "Ethernet88|2": { + "dut-lc5|Asic0|Ethernet96|2": { "scheduler": "scheduler.0" }, - "Ethernet92|2": { + "dut-lc5|Asic0|Ethernet100|2": { "scheduler": "scheduler.0" }, - "Ethernet96|2": { + "dut-lc5|Asic0|Ethernet104|2": { "scheduler": "scheduler.0" }, - "Ethernet100|2": { + "dut-lc5|Asic0|Ethernet108|2": { "scheduler": "scheduler.0" }, - "Ethernet104|2": { + "dut-lc5|Asic0|Ethernet112|2": { "scheduler": "scheduler.0" }, - "Ethernet108|2": { + "dut-lc5|Asic0|Ethernet116|2": { "scheduler": "scheduler.0" }, - "Ethernet112|2": { + "dut-lc5|Asic0|Ethernet120|2": { "scheduler": "scheduler.0" }, - "Ethernet116|2": { + "dut-lc5|Asic0|Ethernet124|2": { "scheduler": "scheduler.0" }, - "Ethernet120|2": { + "dut-lc5|Asic0|Ethernet128|2": { "scheduler": "scheduler.0" }, - "Ethernet124|2": { + "dut-lc5|Asic0|Ethernet132|2": { "scheduler": "scheduler.0" }, - "Ethernet128|2": { + "dut-lc5|Asic0|Ethernet136|2": { "scheduler": "scheduler.0" }, - "Ethernet132|2": { + "dut-lc5|Asic0|Ethernet140|2": { "scheduler": "scheduler.0" }, - "Ethernet136|2": { + "dut-lc5|Asic0|Ethernet144|2": { "scheduler": "scheduler.0" }, - "Ethernet140|2": { + "dut-lc5|Asic0|Ethernet148|2": { "scheduler": "scheduler.0" }, - "Ethernet144|2": { + "dut-lc5|Asic0|Ethernet152|2": { "scheduler": "scheduler.0" }, - "Ethernet148|2": { + "dut-lc5|Asic0|Ethernet156|2": { "scheduler": "scheduler.0" }, - "Ethernet152|2": { + "dut-lc5|Asic0|Ethernet160|2": { "scheduler": "scheduler.0" }, - "Ethernet156|2": { + "dut-lc5|Asic0|Ethernet164|2": { "scheduler": "scheduler.0" }, - "Ethernet164|2": { + "dut-lc5|Asic0|Ethernet168|2": { "scheduler": "scheduler.0" }, - "Ethernet176|2": { + "dut-lc5|Asic0|Ethernet172|2": { "scheduler": "scheduler.0" }, - "Ethernet180|2": { + "dut-lc5|Asic0|Ethernet176|2": { "scheduler": "scheduler.0" }, - "Ethernet184|2": { + "dut-lc5|Asic0|Ethernet180|2": { "scheduler": "scheduler.0" }, - "Ethernet188|2": { + "dut-lc5|Asic0|Ethernet184|2": { "scheduler": "scheduler.0" }, - "Ethernet0|5": { + "dut-lc5|Asic0|Ethernet188|2": { "scheduler": "scheduler.0" }, - "Ethernet4|5": { + "dut-lc3|Asic0|Ethernet0|5": { "scheduler": "scheduler.0" }, - "Ethernet8|5": { + "dut-lc3|Asic0|Ethernet4|5": { "scheduler": "scheduler.0" }, - "Ethernet12|5": { + "dut-lc3|Asic0|Ethernet8|5": { "scheduler": "scheduler.0" }, - "Ethernet16|5": { + "dut-lc3|Asic0|Ethernet12|5": { "scheduler": "scheduler.0" }, - "Ethernet20|5": { + "dut-lc3|Asic0|Ethernet16|5": { "scheduler": "scheduler.0" }, - "Ethernet24|5": { + "dut-lc3|Asic0|Ethernet20|5": { "scheduler": "scheduler.0" }, - "Ethernet28|5": { + "dut-lc3|Asic0|Ethernet24|5": { "scheduler": "scheduler.0" }, - "Ethernet32|5": { + "dut-lc3|Asic0|Ethernet28|5": { "scheduler": "scheduler.0" }, - "Ethernet36|5": { + "dut-lc3|Asic0|Ethernet32|5": { "scheduler": "scheduler.0" }, - "Ethernet40|5": { + "dut-lc3|Asic0|Ethernet36|5": { "scheduler": "scheduler.0" }, - "Ethernet44|5": { + "dut-lc3|Asic0|Ethernet40|5": { "scheduler": "scheduler.0" }, - "Ethernet48|5": { + "dut-lc3|Asic0|Ethernet44|5": { "scheduler": "scheduler.0" }, - "Ethernet52|5": { + "dut-lc3|Asic0|Ethernet48|5": { "scheduler": "scheduler.0" }, - "Ethernet56|5": { + "dut-lc3|Asic0|Ethernet52|5": { "scheduler": "scheduler.0" }, - "Ethernet60|5": { + "dut-lc3|Asic0|Ethernet56|5": { "scheduler": "scheduler.0" }, - "Ethernet64|5": { + "dut-lc3|Asic0|Ethernet60|5": { "scheduler": "scheduler.0" }, - "Ethernet68|5": { + "dut-lc3|Asic0|Ethernet64|5": { "scheduler": "scheduler.0" }, - "Ethernet72|5": { + "dut-lc3|Asic0|Ethernet68|5": { "scheduler": "scheduler.0" }, - "Ethernet76|5": { + "dut-lc3|Asic0|Ethernet72|5": { "scheduler": "scheduler.0" }, - "Ethernet80|5": { + "dut-lc3|Asic0|Ethernet76|5": { "scheduler": "scheduler.0" }, - "Ethernet84|5": { + "dut-lc3|Asic0|Ethernet80|5": { "scheduler": "scheduler.0" }, - "Ethernet88|5": { + "dut-lc3|Asic0|Ethernet84|5": { "scheduler": "scheduler.0" }, - "Ethernet92|5": { + "dut-lc3|Asic0|Ethernet88|5": { "scheduler": "scheduler.0" }, - "Ethernet96|5": { + "dut-lc3|Asic0|Ethernet92|5": { "scheduler": "scheduler.0" }, - "Ethernet100|5": { + "dut-lc3|Asic0|Ethernet96|5": { "scheduler": "scheduler.0" }, - "Ethernet104|5": { + "dut-lc3|Asic0|Ethernet100|5": { "scheduler": "scheduler.0" }, - "Ethernet108|5": { + "dut-lc3|Asic0|Ethernet104|5": { "scheduler": "scheduler.0" }, - "Ethernet112|5": { + "dut-lc3|Asic0|Ethernet108|5": { "scheduler": "scheduler.0" }, - "Ethernet116|5": { + "dut-lc3|Asic0|Ethernet112|5": { "scheduler": "scheduler.0" }, - "Ethernet120|5": { + "dut-lc3|Asic0|Ethernet116|5": { "scheduler": "scheduler.0" }, - "Ethernet124|5": { + "dut-lc3|Asic0|Ethernet120|5": { "scheduler": "scheduler.0" }, - "Ethernet128|5": { + "dut-lc3|Asic0|Ethernet124|5": { "scheduler": "scheduler.0" }, - "Ethernet132|5": { + "dut-lc3|Asic0|Ethernet128|5": { "scheduler": "scheduler.0" }, - "Ethernet136|5": { + "dut-lc3|Asic0|Ethernet132|5": { "scheduler": "scheduler.0" }, - "Ethernet140|5": { + "dut-lc3|Asic0|Ethernet136|5": { "scheduler": "scheduler.0" }, - "Ethernet144|5": { + "dut-lc3|Asic0|Ethernet140|5": { "scheduler": "scheduler.0" }, - "Ethernet148|5": { + "dut-lc3|Asic0|Ethernet144|5": { "scheduler": "scheduler.0" }, - "Ethernet152|5": { + "dut-lc3|Asic0|Ethernet148|5": { "scheduler": "scheduler.0" }, - "Ethernet156|5": { + "dut-lc3|Asic0|Ethernet152|5": { "scheduler": "scheduler.0" }, - "Ethernet164|5": { + "dut-lc3|Asic0|Ethernet156|5": { "scheduler": "scheduler.0" }, - "Ethernet176|5": { + "dut-lc3|Asic0|Ethernet160|5": { "scheduler": "scheduler.0" }, - "Ethernet180|5": { + "dut-lc3|Asic0|Ethernet164|5": { "scheduler": "scheduler.0" }, - "Ethernet184|5": { + "dut-lc3|Asic0|Ethernet168|5": { "scheduler": "scheduler.0" }, - "Ethernet188|5": { + "dut-lc3|Asic0|Ethernet172|5": { "scheduler": "scheduler.0" }, - "Ethernet0|6": { + "dut-lc3|Asic0|Ethernet176|5": { "scheduler": "scheduler.0" }, - "Ethernet4|6": { + "dut-lc3|Asic0|Ethernet180|5": { "scheduler": "scheduler.0" }, - "Ethernet8|6": { + "dut-lc3|Asic0|Ethernet184|5": { "scheduler": "scheduler.0" }, - "Ethernet12|6": { + "dut-lc3|Asic0|Ethernet188|5": { "scheduler": "scheduler.0" }, - "Ethernet16|6": { + "dut-lc4|Asic0|Ethernet0|5": { "scheduler": "scheduler.0" }, - "Ethernet20|6": { + "dut-lc4|Asic0|Ethernet4|5": { "scheduler": "scheduler.0" }, - "Ethernet24|6": { + "dut-lc4|Asic0|Ethernet8|5": { "scheduler": "scheduler.0" }, - "Ethernet28|6": { + "dut-lc4|Asic0|Ethernet12|5": { "scheduler": "scheduler.0" }, - "Ethernet32|6": { + "dut-lc4|Asic0|Ethernet16|5": { "scheduler": "scheduler.0" }, - "Ethernet36|6": { + "dut-lc4|Asic0|Ethernet20|5": { "scheduler": "scheduler.0" }, - "Ethernet40|6": { + "dut-lc4|Asic0|Ethernet24|5": { "scheduler": "scheduler.0" }, - "Ethernet44|6": { + "dut-lc4|Asic0|Ethernet28|5": { "scheduler": "scheduler.0" }, - "Ethernet48|6": { + "dut-lc4|Asic0|Ethernet32|5": { "scheduler": "scheduler.0" }, - "Ethernet52|6": { + "dut-lc4|Asic0|Ethernet36|5": { "scheduler": "scheduler.0" }, - "Ethernet56|6": { + "dut-lc4|Asic0|Ethernet40|5": { "scheduler": "scheduler.0" }, - "Ethernet60|6": { + "dut-lc4|Asic0|Ethernet44|5": { "scheduler": "scheduler.0" }, - "Ethernet64|6": { + "dut-lc4|Asic0|Ethernet48|5": { "scheduler": "scheduler.0" }, - "Ethernet68|6": { + "dut-lc4|Asic0|Ethernet52|5": { "scheduler": "scheduler.0" }, - "Ethernet72|6": { + "dut-lc4|Asic0|Ethernet56|5": { "scheduler": "scheduler.0" }, - "Ethernet76|6": { + "dut-lc4|Asic0|Ethernet60|5": { "scheduler": "scheduler.0" }, - "Ethernet80|6": { + "dut-lc4|Asic0|Ethernet64|5": { "scheduler": "scheduler.0" }, - "Ethernet84|6": { + "dut-lc4|Asic0|Ethernet68|5": { "scheduler": "scheduler.0" }, - "Ethernet88|6": { + "dut-lc4|Asic0|Ethernet72|5": { "scheduler": "scheduler.0" }, - "Ethernet92|6": { + "dut-lc4|Asic0|Ethernet76|5": { "scheduler": "scheduler.0" }, - "Ethernet96|6": { + "dut-lc4|Asic0|Ethernet80|5": { "scheduler": "scheduler.0" }, - "Ethernet100|6": { + "dut-lc4|Asic0|Ethernet84|5": { "scheduler": "scheduler.0" }, - "Ethernet104|6": { + "dut-lc4|Asic0|Ethernet88|5": { "scheduler": "scheduler.0" }, - "Ethernet108|6": { + "dut-lc4|Asic0|Ethernet92|5": { "scheduler": "scheduler.0" }, - "Ethernet112|6": { + "dut-lc4|Asic0|Ethernet96|5": { "scheduler": "scheduler.0" }, - "Ethernet116|6": { + "dut-lc4|Asic0|Ethernet100|5": { "scheduler": "scheduler.0" }, - "Ethernet120|6": { + "dut-lc4|Asic0|Ethernet104|5": { "scheduler": "scheduler.0" }, - "Ethernet124|6": { + "dut-lc4|Asic0|Ethernet108|5": { "scheduler": "scheduler.0" }, - "Ethernet128|6": { + "dut-lc4|Asic0|Ethernet112|5": { "scheduler": "scheduler.0" }, - "Ethernet132|6": { + "dut-lc4|Asic0|Ethernet116|5": { "scheduler": "scheduler.0" }, - "Ethernet136|6": { + "dut-lc4|Asic0|Ethernet120|5": { "scheduler": "scheduler.0" }, - "Ethernet140|6": { + "dut-lc4|Asic0|Ethernet124|5": { "scheduler": "scheduler.0" }, - "Ethernet144|6": { + "dut-lc4|Asic0|Ethernet128|5": { "scheduler": "scheduler.0" }, - "Ethernet148|6": { + "dut-lc4|Asic0|Ethernet132|5": { "scheduler": "scheduler.0" }, - "Ethernet152|6": { + "dut-lc4|Asic0|Ethernet136|5": { "scheduler": "scheduler.0" }, - "Ethernet156|6": { + "dut-lc4|Asic0|Ethernet140|5": { "scheduler": "scheduler.0" }, - "Ethernet164|6": { + "dut-lc4|Asic0|Ethernet144|5": { "scheduler": "scheduler.0" }, - "Ethernet176|6": { + "dut-lc4|Asic0|Ethernet148|5": { "scheduler": "scheduler.0" }, - "Ethernet180|6": { + "dut-lc4|Asic0|Ethernet152|5": { "scheduler": "scheduler.0" }, - "Ethernet184|6": { + "dut-lc4|Asic0|Ethernet156|5": { "scheduler": "scheduler.0" }, - "Ethernet188|6": { + "dut-lc4|Asic0|Ethernet160|5": { "scheduler": "scheduler.0" - } + }, + "dut-lc4|Asic0|Ethernet164|5": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet168|5": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet172|5": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet176|5": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet180|5": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet184|5": { + "scheduler": "scheduler.0" + }, + "dut-lc4|Asic0|Ethernet188|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet0|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet4|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet8|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet12|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet16|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet20|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet24|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet28|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet32|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet36|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet40|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet44|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet48|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet52|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet56|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet60|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet64|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet68|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet72|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet76|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet80|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet84|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet88|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet92|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet96|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet100|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet104|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet108|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet112|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet116|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet120|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet124|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet128|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet132|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet136|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet140|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet144|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet148|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet152|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet156|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet160|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet164|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet168|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet172|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet176|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet180|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet184|5": { + "scheduler": "scheduler.0" + }, + "dut-lc5|Asic0|Ethernet188|5": { + "scheduler": "scheduler.0" + }, + "dut-lc3|Asic0|Ethernet0|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet4|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet8|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet12|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet16|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet20|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet24|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet28|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet32|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet36|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet40|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet44|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet48|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet52|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet56|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet60|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet64|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet68|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet72|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet76|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet80|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet84|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet88|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet92|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet96|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet100|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet104|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet108|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet112|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet116|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet120|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet124|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet128|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet132|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet136|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet140|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet144|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet148|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet152|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet156|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet160|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet164|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet168|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet172|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet176|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet180|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet184|6": { + "scheduler": "scheduler.0" + }, "dut-lc3|Asic0|Ethernet188|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet0|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet4|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet8|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet12|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet16|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet20|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet24|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet28|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet32|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet36|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet40|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet44|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet48|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet52|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet56|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet60|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet64|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet68|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet72|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet76|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet80|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet84|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet88|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet92|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet96|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet100|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet104|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet108|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet112|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet116|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet120|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet124|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet128|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet132|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet136|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet140|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet144|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet148|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet152|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet156|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet160|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet164|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet168|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet172|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet176|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet180|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet184|6": { + "scheduler": "scheduler.0" + }, "dut-lc4|Asic0|Ethernet188|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet0|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet4|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet8|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet12|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet16|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet20|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet24|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet28|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet32|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet36|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet40|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet44|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet48|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet52|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet56|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet60|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet64|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet68|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet72|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet76|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet80|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet84|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet88|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet92|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet96|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet100|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet104|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet108|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet112|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet116|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet120|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet124|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet128|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet132|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet136|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet140|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet144|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet148|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet152|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet156|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet160|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet164|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet168|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet172|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet176|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet180|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet184|6": { + "scheduler": "scheduler.0" + }, "dut-lc5|Asic0|Ethernet188|6": { + "scheduler": "scheduler.0" + } } } diff --git a/src/sonic-config-engine/tests/sample_output/py3/qos-arista7800r3a-36dm2-c36-lc.json b/src/sonic-config-engine/tests/sample_output/py3/qos-arista7800r3a-36dm2-c36-lc.json index cf6fbf64f8db..1007b272c466 100644 --- a/src/sonic-config-engine/tests/sample_output/py3/qos-arista7800r3a-36dm2-c36-lc.json +++ b/src/sonic-config-engine/tests/sample_output/py3/qos-arista7800r3a-36dm2-c36-lc.json @@ -280,418 +280,3040 @@ } }, "QUEUE": { - "Ethernet0|3": { - "scheduler" : "scheduler.1", + "str2-7804-lc3-1|Asic0|Ethernet0|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet0|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet0|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet0|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet0|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet0|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet0|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet4|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet4|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet4|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet4|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet4|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet4|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet4|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet8|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet8|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet8|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet8|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet8|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet8|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet8|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet12|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet12|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet12|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet12|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet12|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet12|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet12|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet16|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet16|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet16|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet16|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet16|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet16|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet16|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet20|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet20|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet20|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet20|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet20|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet20|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet20|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet24|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet24|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet24|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet24|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet24|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet24|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet24|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet28|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet28|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet28|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet28|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet28|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet28|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet28|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet32|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet32|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet32|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet32|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet32|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet32|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet32|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet36|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet36|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet36|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet36|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet36|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet36|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet36|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet40|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet40|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet40|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet40|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet40|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet40|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet40|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet44|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet44|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet44|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet44|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet44|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet44|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet44|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet48|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet48|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet48|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet48|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet48|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet48|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet48|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet52|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet52|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet52|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet52|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet52|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet52|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet52|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet56|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet56|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet56|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet56|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet56|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet56|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet56|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet60|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet60|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet60|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet60|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet60|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet60|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet60|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet64|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet64|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet64|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet64|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet64|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet64|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet64|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet68|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet68|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet68|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet68|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet68|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet68|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet68|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet72|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet72|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet72|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet72|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet72|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet72|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet72|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet76|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet76|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet76|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet76|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet76|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet76|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet76|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet80|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet80|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet80|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet80|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet80|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet80|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet80|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet84|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet84|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet84|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet84|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet84|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet84|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet84|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet88|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet88|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet88|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet88|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet88|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet88|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet88|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet92|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet92|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet92|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet92|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet92|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet92|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet92|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet96|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet96|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet96|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet96|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet96|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet96|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet96|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet100|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet100|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet100|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet100|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet100|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet100|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet100|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet104|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet104|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet104|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet104|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet104|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet104|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet104|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet108|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet108|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet108|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet108|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet108|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet108|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet108|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet112|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet112|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet112|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet112|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet112|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet112|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet112|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet116|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet116|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet116|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet116|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet116|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet116|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet116|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet120|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet120|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet120|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet120|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet120|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet120|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet120|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet124|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet124|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet124|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet124|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet124|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet124|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet124|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet128|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet128|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet128|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet128|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet128|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet128|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet128|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet132|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet132|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet132|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet132|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet132|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet132|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet132|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet136|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet136|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet136|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet136|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet136|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet136|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet136|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet140|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet140|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet140|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet140|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet140|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet140|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet140|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet144|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet144|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet144|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet144|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet144|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet144|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet144|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet148|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet148|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet148|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet148|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet148|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet148|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet148|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet152|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet152|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet152|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet152|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet152|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet152|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet152|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet156|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet156|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet156|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet156|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet156|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet156|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet156|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet160|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet160|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet160|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet160|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet160|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet160|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet160|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet164|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet164|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet164|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet164|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet164|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet164|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet164|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet168|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet168|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet168|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet168|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet168|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet168|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet168|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet172|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet172|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet172|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet172|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet172|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet172|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet172|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet176|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet176|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet176|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet176|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet176|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet176|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet176|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet180|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet180|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet180|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet180|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet180|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet180|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet180|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet184|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet184|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet184|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet184|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet184|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet184|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet184|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet188|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet188|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet188|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet188|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet188|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc3-1|Asic0|Ethernet188|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc3-1|Asic0|Ethernet188|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet0|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet0|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet0|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet0|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet0|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet0|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet0|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet8|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet8|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet8|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet8|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet8|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet8|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet8|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet16|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet16|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet16|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet16|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet16|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet16|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet16|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet24|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet24|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet24|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet24|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet24|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet24|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet24|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet32|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet32|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet32|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet32|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet32|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet32|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet32|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet40|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet40|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet40|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet40|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet40|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet40|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet40|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet48|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet48|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet48|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet48|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet48|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet48|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet48|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet56|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet56|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet56|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet56|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet56|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet56|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet56|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet64|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet64|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet64|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet64|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet64|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet64|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet64|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet72|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet72|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet72|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet72|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet72|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet72|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet72|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet80|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet80|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet80|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet80|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet80|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet80|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet80|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet88|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet88|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet88|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet88|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet88|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet88|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet88|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet96|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet96|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet96|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet96|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet96|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet96|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet96|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet104|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet104|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet104|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet104|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet104|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet104|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet104|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet112|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet112|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet112|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet112|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet112|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet112|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet112|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet120|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet120|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet120|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet120|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet120|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet120|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet120|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet128|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet128|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet128|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet128|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet128|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet128|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet128|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet136|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet136|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet136|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet136|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet136|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic0|Ethernet136|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic0|Ethernet136|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet144|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet144|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet144|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet144|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet144|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet144|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet144|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet152|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet152|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet152|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet152|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet152|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet152|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet152|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet160|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet160|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet160|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet160|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet160|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet160|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet160|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet168|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet168|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet168|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet168|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet168|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet168|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet168|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet176|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet176|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet176|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet176|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet176|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet176|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet176|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet184|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet184|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet184|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet184|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet184|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet184|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet184|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet192|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet192|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet192|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet192|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet192|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet192|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet192|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet200|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet200|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet200|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet200|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet200|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet200|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet200|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet208|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet208|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet208|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet208|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet208|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet208|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet208|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet216|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet216|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet216|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet216|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet216|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet216|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet216|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet224|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet224|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet224|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet224|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet224|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet224|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet224|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet232|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet232|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet232|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet232|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet232|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet232|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet232|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet240|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet240|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet240|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet240|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet240|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet240|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet240|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet248|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet248|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet248|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet248|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet248|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet248|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet248|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet256|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet256|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet256|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet256|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet256|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet256|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet256|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet264|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet264|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet264|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet264|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet264|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet264|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet264|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet272|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet272|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet272|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet272|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet272|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet272|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet272|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet280|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet280|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet280|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet280|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet280|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc5-1|asic1|Ethernet280|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc5-1|asic1|Ethernet280|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet0|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet0|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet0|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet0|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet0|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet0|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet0|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet4|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet4|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet4|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet4|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet4|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet4|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet4|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet8|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet8|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet8|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet8|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet8|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet8|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet8|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet12|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet12|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet12|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet12|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet12|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet12|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet12|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet16|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet16|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet16|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet16|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet16|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet16|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet16|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet20|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet20|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet20|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet20|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet20|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet20|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet20|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet24|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet24|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet24|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet24|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet24|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet24|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet24|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet28|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet28|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet28|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet28|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet28|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet28|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet28|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet32|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet32|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet32|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet32|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet32|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet32|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet32|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet36|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet36|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet36|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet36|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet36|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet36|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet36|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet40|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet40|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet40|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet40|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet40|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet40|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet40|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet44|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet44|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet44|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet44|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet44|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet44|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet44|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet48|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet48|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet48|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet48|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet8|3": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet48|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet16|3": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet48|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet48|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet52|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet52|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet52|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet52|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet24|3": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet52|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet32|3": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet52|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet52|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet56|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet56|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet56|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet56|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet40|3": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet56|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet48|3": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet56|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet56|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet60|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet60|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet60|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet60|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet56|3": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet60|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet64|3": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet60|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet60|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet64|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet64|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet64|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet64|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet72|3": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet64|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet80|3": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet64|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet64|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet68|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet68|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet68|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet68|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet88|3": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet68|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet96|3": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet68|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet68|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet72|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet72|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet72|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet72|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet104|3": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet72|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet112|3": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet72|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet72|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet76|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet76|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet76|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet76|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet120|3": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet76|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet128|3": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet76|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet76|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet80|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet80|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet80|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet80|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet136|3": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet80|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet0|4": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet80|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet80|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet84|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet84|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet84|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet84|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet8|4": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet84|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet16|4": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet84|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet84|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet88|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet88|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet88|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet88|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet24|4": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet88|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet32|4": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet88|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet88|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet92|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet92|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet92|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet92|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet40|4": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet92|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet48|4": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet92|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet92|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet96|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet96|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet96|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet96|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet56|4": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet96|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet64|4": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet96|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet96|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet100|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet100|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet100|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet100|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet72|4": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet100|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet80|4": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet100|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet100|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet104|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet104|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet104|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet104|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet88|4": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet104|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet96|4": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet104|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet104|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet108|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet108|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet108|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet108|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet104|4": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet108|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet112|4": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet108|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet108|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet112|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet112|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet112|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet112|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet120|4": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet112|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet128|4": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet112|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet112|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet116|0": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet116|1": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet116|2": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet116|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet136|4": { - "scheduler" : "scheduler.1", + "str2-7804-lc7-1|Asic0|Ethernet116|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet0|0": { + "str2-7804-lc7-1|Asic0|Ethernet116|5": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet116|6": { + "scheduler": "scheduler.0" + }, + "str2-7804-lc7-1|Asic0|Ethernet120|0": { "scheduler": "scheduler.0" }, - "Ethernet8|0": { + "str2-7804-lc7-1|Asic0|Ethernet120|1": { "scheduler": "scheduler.0" }, - "Ethernet16|0": { + "str2-7804-lc7-1|Asic0|Ethernet120|2": { "scheduler": "scheduler.0" }, - "Ethernet24|0": { + "str2-7804-lc7-1|Asic0|Ethernet120|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet120|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet120|5": { "scheduler": "scheduler.0" }, - "Ethernet32|0": { + "str2-7804-lc7-1|Asic0|Ethernet120|6": { "scheduler": "scheduler.0" }, - "Ethernet40|0": { + "str2-7804-lc7-1|Asic0|Ethernet124|0": { "scheduler": "scheduler.0" }, - "Ethernet48|0": { + "str2-7804-lc7-1|Asic0|Ethernet124|1": { "scheduler": "scheduler.0" }, - "Ethernet56|0": { + "str2-7804-lc7-1|Asic0|Ethernet124|2": { "scheduler": "scheduler.0" }, - "Ethernet64|0": { + "str2-7804-lc7-1|Asic0|Ethernet124|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet124|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet124|5": { "scheduler": "scheduler.0" }, - "Ethernet72|0": { + "str2-7804-lc7-1|Asic0|Ethernet124|6": { "scheduler": "scheduler.0" }, - "Ethernet80|0": { + "str2-7804-lc7-1|Asic0|Ethernet128|0": { "scheduler": "scheduler.0" }, - "Ethernet88|0": { + "str2-7804-lc7-1|Asic0|Ethernet128|1": { "scheduler": "scheduler.0" }, - "Ethernet96|0": { + "str2-7804-lc7-1|Asic0|Ethernet128|2": { "scheduler": "scheduler.0" }, - "Ethernet104|0": { + "str2-7804-lc7-1|Asic0|Ethernet128|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet128|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet128|5": { "scheduler": "scheduler.0" }, - "Ethernet112|0": { + "str2-7804-lc7-1|Asic0|Ethernet128|6": { "scheduler": "scheduler.0" }, - "Ethernet120|0": { + "str2-7804-lc7-1|Asic0|Ethernet132|0": { "scheduler": "scheduler.0" }, - "Ethernet128|0": { + "str2-7804-lc7-1|Asic0|Ethernet132|1": { "scheduler": "scheduler.0" }, - "Ethernet136|0": { + "str2-7804-lc7-1|Asic0|Ethernet132|2": { "scheduler": "scheduler.0" }, - "Ethernet0|1": { + "str2-7804-lc7-1|Asic0|Ethernet132|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet132|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet132|5": { "scheduler": "scheduler.0" }, - "Ethernet8|1": { + "str2-7804-lc7-1|Asic0|Ethernet132|6": { "scheduler": "scheduler.0" }, - "Ethernet16|1": { + "str2-7804-lc7-1|Asic0|Ethernet136|0": { "scheduler": "scheduler.0" }, - "Ethernet24|1": { + "str2-7804-lc7-1|Asic0|Ethernet136|1": { "scheduler": "scheduler.0" }, - "Ethernet32|1": { + "str2-7804-lc7-1|Asic0|Ethernet136|2": { "scheduler": "scheduler.0" }, - "Ethernet40|1": { + "str2-7804-lc7-1|Asic0|Ethernet136|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet136|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet136|5": { "scheduler": "scheduler.0" }, - "Ethernet48|1": { + "str2-7804-lc7-1|Asic0|Ethernet136|6": { "scheduler": "scheduler.0" }, - "Ethernet56|1": { + "str2-7804-lc7-1|Asic0|Ethernet140|0": { "scheduler": "scheduler.0" }, - "Ethernet64|1": { + "str2-7804-lc7-1|Asic0|Ethernet140|1": { "scheduler": "scheduler.0" }, - "Ethernet72|1": { + "str2-7804-lc7-1|Asic0|Ethernet140|2": { "scheduler": "scheduler.0" }, - "Ethernet80|1": { + "str2-7804-lc7-1|Asic0|Ethernet140|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet140|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet140|5": { "scheduler": "scheduler.0" }, - "Ethernet88|1": { + "str2-7804-lc7-1|Asic0|Ethernet140|6": { "scheduler": "scheduler.0" }, - "Ethernet96|1": { + "str2-7804-lc7-1|Asic0|Ethernet144|0": { "scheduler": "scheduler.0" }, - "Ethernet104|1": { + "str2-7804-lc7-1|Asic0|Ethernet144|1": { "scheduler": "scheduler.0" }, - "Ethernet112|1": { + "str2-7804-lc7-1|Asic0|Ethernet144|2": { "scheduler": "scheduler.0" }, - "Ethernet120|1": { + "str2-7804-lc7-1|Asic0|Ethernet144|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet144|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet144|5": { "scheduler": "scheduler.0" }, - "Ethernet128|1": { + "str2-7804-lc7-1|Asic0|Ethernet144|6": { "scheduler": "scheduler.0" }, - "Ethernet136|1": { + "str2-7804-lc7-1|Asic0|Ethernet148|0": { "scheduler": "scheduler.0" }, - "Ethernet0|2": { + "str2-7804-lc7-1|Asic0|Ethernet148|1": { "scheduler": "scheduler.0" }, - "Ethernet8|2": { + "str2-7804-lc7-1|Asic0|Ethernet148|2": { "scheduler": "scheduler.0" }, - "Ethernet16|2": { + "str2-7804-lc7-1|Asic0|Ethernet148|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet148|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet148|5": { "scheduler": "scheduler.0" }, - "Ethernet24|2": { + "str2-7804-lc7-1|Asic0|Ethernet148|6": { "scheduler": "scheduler.0" }, - "Ethernet32|2": { + "str2-7804-lc7-1|Asic0|Ethernet152|0": { "scheduler": "scheduler.0" }, - "Ethernet40|2": { + "str2-7804-lc7-1|Asic0|Ethernet152|1": { "scheduler": "scheduler.0" }, - "Ethernet48|2": { + "str2-7804-lc7-1|Asic0|Ethernet152|2": { "scheduler": "scheduler.0" }, - "Ethernet56|2": { + "str2-7804-lc7-1|Asic0|Ethernet152|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet152|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet152|5": { "scheduler": "scheduler.0" }, - "Ethernet64|2": { + "str2-7804-lc7-1|Asic0|Ethernet152|6": { "scheduler": "scheduler.0" }, - "Ethernet72|2": { + "str2-7804-lc7-1|Asic0|Ethernet156|0": { "scheduler": "scheduler.0" }, - "Ethernet80|2": { + "str2-7804-lc7-1|Asic0|Ethernet156|1": { "scheduler": "scheduler.0" }, - "Ethernet88|2": { + "str2-7804-lc7-1|Asic0|Ethernet156|2": { "scheduler": "scheduler.0" }, - "Ethernet96|2": { + "str2-7804-lc7-1|Asic0|Ethernet156|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet156|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet156|5": { "scheduler": "scheduler.0" }, - "Ethernet104|2": { + "str2-7804-lc7-1|Asic0|Ethernet156|6": { "scheduler": "scheduler.0" }, - "Ethernet112|2": { + "str2-7804-lc7-1|Asic0|Ethernet160|0": { "scheduler": "scheduler.0" }, - "Ethernet120|2": { + "str2-7804-lc7-1|Asic0|Ethernet160|1": { "scheduler": "scheduler.0" }, - "Ethernet128|2": { + "str2-7804-lc7-1|Asic0|Ethernet160|2": { "scheduler": "scheduler.0" }, - "Ethernet136|2": { + "str2-7804-lc7-1|Asic0|Ethernet160|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet160|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet160|5": { "scheduler": "scheduler.0" }, - "Ethernet0|5": { + "str2-7804-lc7-1|Asic0|Ethernet160|6": { "scheduler": "scheduler.0" }, - "Ethernet8|5": { + "str2-7804-lc7-1|Asic0|Ethernet164|0": { "scheduler": "scheduler.0" }, - "Ethernet16|5": { + "str2-7804-lc7-1|Asic0|Ethernet164|1": { "scheduler": "scheduler.0" }, - "Ethernet24|5": { + "str2-7804-lc7-1|Asic0|Ethernet164|2": { "scheduler": "scheduler.0" }, - "Ethernet32|5": { + "str2-7804-lc7-1|Asic0|Ethernet164|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet164|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet164|5": { "scheduler": "scheduler.0" }, - "Ethernet40|5": { + "str2-7804-lc7-1|Asic0|Ethernet164|6": { "scheduler": "scheduler.0" }, - "Ethernet48|5": { + "str2-7804-lc7-1|Asic0|Ethernet168|0": { "scheduler": "scheduler.0" }, - "Ethernet56|5": { + "str2-7804-lc7-1|Asic0|Ethernet168|1": { "scheduler": "scheduler.0" }, - "Ethernet64|5": { + "str2-7804-lc7-1|Asic0|Ethernet168|2": { "scheduler": "scheduler.0" }, - "Ethernet72|5": { + "str2-7804-lc7-1|Asic0|Ethernet168|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet168|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet168|5": { "scheduler": "scheduler.0" }, - "Ethernet80|5": { + "str2-7804-lc7-1|Asic0|Ethernet168|6": { "scheduler": "scheduler.0" }, - "Ethernet88|5": { + "str2-7804-lc7-1|Asic0|Ethernet172|0": { "scheduler": "scheduler.0" }, - "Ethernet96|5": { + "str2-7804-lc7-1|Asic0|Ethernet172|1": { "scheduler": "scheduler.0" }, - "Ethernet104|5": { + "str2-7804-lc7-1|Asic0|Ethernet172|2": { "scheduler": "scheduler.0" }, - "Ethernet112|5": { + "str2-7804-lc7-1|Asic0|Ethernet172|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet172|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet172|5": { "scheduler": "scheduler.0" }, - "Ethernet120|5": { + "str2-7804-lc7-1|Asic0|Ethernet172|6": { "scheduler": "scheduler.0" }, - "Ethernet128|5": { + "str2-7804-lc7-1|Asic0|Ethernet176|0": { "scheduler": "scheduler.0" }, - "Ethernet136|5": { + "str2-7804-lc7-1|Asic0|Ethernet176|1": { "scheduler": "scheduler.0" }, - "Ethernet0|6": { + "str2-7804-lc7-1|Asic0|Ethernet176|2": { "scheduler": "scheduler.0" }, - "Ethernet8|6": { + "str2-7804-lc7-1|Asic0|Ethernet176|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet176|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet176|5": { "scheduler": "scheduler.0" }, - "Ethernet16|6": { + "str2-7804-lc7-1|Asic0|Ethernet176|6": { "scheduler": "scheduler.0" }, - "Ethernet24|6": { + "str2-7804-lc7-1|Asic0|Ethernet180|0": { "scheduler": "scheduler.0" }, - "Ethernet32|6": { + "str2-7804-lc7-1|Asic0|Ethernet180|1": { "scheduler": "scheduler.0" }, - "Ethernet40|6": { + "str2-7804-lc7-1|Asic0|Ethernet180|2": { "scheduler": "scheduler.0" }, - "Ethernet48|6": { + "str2-7804-lc7-1|Asic0|Ethernet180|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet180|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet180|5": { "scheduler": "scheduler.0" }, - "Ethernet56|6": { + "str2-7804-lc7-1|Asic0|Ethernet180|6": { "scheduler": "scheduler.0" }, - "Ethernet64|6": { + "str2-7804-lc7-1|Asic0|Ethernet184|0": { "scheduler": "scheduler.0" }, - "Ethernet72|6": { + "str2-7804-lc7-1|Asic0|Ethernet184|1": { "scheduler": "scheduler.0" }, - "Ethernet80|6": { + "str2-7804-lc7-1|Asic0|Ethernet184|2": { "scheduler": "scheduler.0" }, - "Ethernet88|6": { + "str2-7804-lc7-1|Asic0|Ethernet184|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet184|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet184|5": { "scheduler": "scheduler.0" }, - "Ethernet96|6": { + "str2-7804-lc7-1|Asic0|Ethernet184|6": { "scheduler": "scheduler.0" }, - "Ethernet104|6": { + "str2-7804-lc7-1|Asic0|Ethernet188|0": { "scheduler": "scheduler.0" }, - "Ethernet112|6": { + "str2-7804-lc7-1|Asic0|Ethernet188|1": { "scheduler": "scheduler.0" }, - "Ethernet120|6": { + "str2-7804-lc7-1|Asic0|Ethernet188|2": { "scheduler": "scheduler.0" }, - "Ethernet128|6": { + "str2-7804-lc7-1|Asic0|Ethernet188|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet188|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7804-lc7-1|Asic0|Ethernet188|5": { "scheduler": "scheduler.0" }, - "Ethernet136|6": { + "str2-7804-lc7-1|Asic0|Ethernet188|6": { "scheduler": "scheduler.0" } } diff --git a/src/sonic-config-engine/tests/sample_output/py3/qos-arista7800r3a-36dm2-d36-lc.json b/src/sonic-config-engine/tests/sample_output/py3/qos-arista7800r3a-36dm2-d36-lc.json index cf6fbf64f8db..027753a09f2f 100644 --- a/src/sonic-config-engine/tests/sample_output/py3/qos-arista7800r3a-36dm2-d36-lc.json +++ b/src/sonic-config-engine/tests/sample_output/py3/qos-arista7800r3a-36dm2-d36-lc.json @@ -280,419 +280,2910 @@ } }, "QUEUE": { - "Ethernet0|3": { + "str3-7800-lc8-1|asic0|Ethernet0|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet8|3": { + "str3-7800-lc8-1|asic0|Ethernet8|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet16|3": { + "str3-7800-lc8-1|asic0|Ethernet16|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet24|3": { + "str3-7800-lc8-1|asic0|Ethernet24|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet32|3": { + "str3-7800-lc8-1|asic0|Ethernet32|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet40|3": { + "str3-7800-lc8-1|asic0|Ethernet40|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet48|3": { + "str3-7800-lc8-1|asic0|Ethernet48|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet56|3": { + "str3-7800-lc8-1|asic0|Ethernet56|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet64|3": { + "str3-7800-lc8-1|asic0|Ethernet64|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet72|3": { + "str3-7800-lc8-1|asic0|Ethernet72|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet80|3": { + "str3-7800-lc8-1|asic0|Ethernet80|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet88|3": { + "str3-7800-lc8-1|asic0|Ethernet88|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet96|3": { + "str3-7800-lc8-1|asic0|Ethernet96|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet104|3": { + "str3-7800-lc8-1|asic0|Ethernet104|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet112|3": { + "str3-7800-lc8-1|asic0|Ethernet112|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet120|3": { + "str3-7800-lc8-1|asic0|Ethernet120|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet128|3": { + "str3-7800-lc8-1|asic0|Ethernet128|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet136|3": { + "str3-7800-lc8-1|asic0|Ethernet136|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet0|4": { + "str3-7800-lc8-1|asic1|Ethernet144|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet8|4": { + "str3-7800-lc8-1|asic1|Ethernet152|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet16|4": { + "str3-7800-lc8-1|asic1|Ethernet160|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet24|4": { + "str3-7800-lc8-1|asic1|Ethernet168|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet32|4": { + "str3-7800-lc8-1|asic1|Ethernet176|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet40|4": { + "str3-7800-lc8-1|asic1|Ethernet184|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet48|4": { + "str3-7800-lc8-1|asic1|Ethernet192|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet56|4": { + "str3-7800-lc8-1|asic1|Ethernet200|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet64|4": { + "str3-7800-lc8-1|asic1|Ethernet208|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet72|4": { + "str3-7800-lc8-1|asic1|Ethernet216|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet80|4": { + "str3-7800-lc8-1|asic1|Ethernet224|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet88|4": { + "str3-7800-lc8-1|asic1|Ethernet232|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet96|4": { + "str3-7800-lc8-1|asic1|Ethernet240|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet104|4": { + "str3-7800-lc8-1|asic1|Ethernet248|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet112|4": { + "str3-7800-lc8-1|asic1|Ethernet256|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet120|4": { + "str3-7800-lc8-1|asic1|Ethernet264|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet128|4": { + "str3-7800-lc8-1|asic1|Ethernet272|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet136|4": { + "str3-7800-lc8-1|asic1|Ethernet280|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet0|0": { + "str3-7800-lc1-1|Asic0|Ethernet0|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet4|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet8|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet12|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet16|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet20|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet24|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet28|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet32|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet36|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet40|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet44|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet48|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet52|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet56|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet60|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet64|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet68|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet72|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet76|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet80|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet84|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet88|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet92|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet96|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet100|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet104|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet108|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet112|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet116|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet120|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet124|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet128|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet132|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet136|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet140|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet144|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet148|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet152|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet156|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet160|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet164|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet168|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet172|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet176|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet180|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet184|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet188|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet0|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet4|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet8|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet12|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet16|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet20|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet24|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet28|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet32|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet36|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet40|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet44|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet48|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet52|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet56|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet60|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet64|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet68|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet72|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet76|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet80|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet84|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet88|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet92|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet96|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet100|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet104|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet108|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet112|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet116|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet120|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet124|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet128|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet132|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet136|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet140|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet144|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet148|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet152|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet156|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet160|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet164|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet168|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet172|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet176|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet180|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet184|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet188|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet0|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet8|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet16|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet24|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet32|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet40|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet48|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet56|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet64|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet72|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet80|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet88|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet96|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet104|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet112|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet120|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet128|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet136|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet144|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet152|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet160|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet168|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet176|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet184|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet192|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet200|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet208|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet216|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet224|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet232|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet240|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet248|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet256|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet264|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet272|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic1|Ethernet280|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet0|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet4|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet8|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet12|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet16|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet20|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet24|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet28|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet32|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet36|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet40|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet44|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet48|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet52|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet56|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet60|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet64|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet68|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet72|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet76|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet80|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet84|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet88|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet92|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet96|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet100|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet104|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet108|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet112|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet116|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet120|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet124|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet128|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet132|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet136|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet140|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet144|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet148|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet152|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet156|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet160|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet164|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet168|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet172|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet176|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet180|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet184|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc1-1|Asic0|Ethernet188|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet0|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet4|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet8|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet12|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet16|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet20|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet24|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet28|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet32|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet36|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet40|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet44|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet48|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet52|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet56|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet60|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet64|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet68|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet72|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet76|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet80|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet84|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet88|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet92|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet96|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet100|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet104|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet108|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet112|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet116|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet120|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet124|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet128|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet132|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet136|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet140|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet144|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet148|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet152|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet156|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet160|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet164|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet168|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet172|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet176|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet180|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet184|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc2-1|Asic0|Ethernet188|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str3-7800-lc8-1|asic0|Ethernet0|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet8|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet16|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet24|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet32|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet40|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet48|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet56|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet64|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet72|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet80|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet88|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet96|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet104|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet112|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet120|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet128|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet136|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet144|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet152|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet160|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet168|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet176|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet184|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet192|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet200|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet208|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet216|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet224|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet232|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet240|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet248|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet256|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet264|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet272|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet280|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet0|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet4|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet8|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet12|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet16|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet20|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet24|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet28|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet32|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet36|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet40|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet44|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet48|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet52|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet56|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet60|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet64|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet68|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet72|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet76|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet80|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet84|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet88|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet92|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet96|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet100|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet104|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet108|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet112|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet116|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet120|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet124|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet128|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet132|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet136|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet140|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet144|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet148|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet152|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet156|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet160|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet164|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet168|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet172|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet176|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet180|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet184|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet188|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet0|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet4|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet8|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet12|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet16|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet20|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet24|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet28|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet32|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet36|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet40|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet44|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet48|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet52|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet56|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet60|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet64|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet68|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet72|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet76|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet80|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet84|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet88|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet92|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet96|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet100|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet104|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet108|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet112|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet116|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet120|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet124|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet128|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet132|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet136|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet140|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet144|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet148|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet152|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet156|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet160|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet164|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet168|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet172|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet176|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet180|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet184|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet188|0": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet0|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet8|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet16|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet24|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet32|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet40|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet48|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet56|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet64|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet72|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet80|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet88|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet96|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet104|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet112|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet120|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet128|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet136|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet144|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet152|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet160|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet168|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet176|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet184|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet192|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet200|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet208|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet216|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet224|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet232|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet240|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet248|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet256|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet264|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet272|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet280|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet0|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet4|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet8|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet12|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet16|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet20|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet24|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet28|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet32|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet36|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet40|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet44|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet48|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet52|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet56|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet60|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet64|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet68|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet72|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet76|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet80|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet84|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet88|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet92|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet96|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet100|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet104|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet108|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet112|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet116|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet120|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet124|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet128|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet132|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet136|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet140|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet144|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet148|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet152|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet156|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet160|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet164|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet168|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet172|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet176|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet180|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet184|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet188|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet0|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet4|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet8|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet12|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet16|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet20|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet24|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet28|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet32|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet36|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet40|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet44|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet48|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet52|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet56|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet60|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet64|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet68|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet72|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet76|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet80|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet84|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet88|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet92|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet96|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet100|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet104|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet108|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet112|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet116|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet120|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet124|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet128|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet132|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet136|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet140|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet144|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet148|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet152|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet156|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet160|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet164|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet168|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet172|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet176|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet180|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet184|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet188|1": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet0|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet8|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet16|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet24|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet32|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet40|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet48|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet56|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet64|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet72|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet80|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet88|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet96|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet104|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet112|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet120|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet128|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet136|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet144|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet152|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet160|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet168|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet176|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet184|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet192|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet200|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet208|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet216|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet224|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet232|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet240|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet248|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet256|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet264|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet272|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic1|Ethernet280|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet0|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet4|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet8|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet12|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet16|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet20|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet24|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet28|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet32|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet36|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet40|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet44|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet48|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet52|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet56|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet60|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet64|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet68|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet72|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet76|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet80|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet84|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet88|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet92|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet96|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet100|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet104|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet108|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet112|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet116|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet120|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet124|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet128|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet132|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet136|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet140|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet144|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet148|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet152|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet156|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet160|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet164|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet168|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet172|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet176|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet180|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet184|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet188|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet0|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet4|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet8|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet12|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet16|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet20|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet24|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet28|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet32|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet36|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet40|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet44|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet48|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet52|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet56|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet60|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet64|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet68|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet72|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet76|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet80|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet84|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet88|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet92|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet96|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet100|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet104|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet108|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet112|2": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet116|2": { "scheduler": "scheduler.0" }, - "Ethernet8|0": { + "str3-7800-lc2-1|Asic0|Ethernet120|2": { "scheduler": "scheduler.0" }, - "Ethernet16|0": { + "str3-7800-lc2-1|Asic0|Ethernet124|2": { "scheduler": "scheduler.0" }, - "Ethernet24|0": { + "str3-7800-lc2-1|Asic0|Ethernet128|2": { "scheduler": "scheduler.0" }, - "Ethernet32|0": { + "str3-7800-lc2-1|Asic0|Ethernet132|2": { "scheduler": "scheduler.0" }, - "Ethernet40|0": { + "str3-7800-lc2-1|Asic0|Ethernet136|2": { "scheduler": "scheduler.0" }, - "Ethernet48|0": { + "str3-7800-lc2-1|Asic0|Ethernet140|2": { "scheduler": "scheduler.0" }, - "Ethernet56|0": { + "str3-7800-lc2-1|Asic0|Ethernet144|2": { "scheduler": "scheduler.0" }, - "Ethernet64|0": { + "str3-7800-lc2-1|Asic0|Ethernet148|2": { "scheduler": "scheduler.0" }, - "Ethernet72|0": { + "str3-7800-lc2-1|Asic0|Ethernet152|2": { "scheduler": "scheduler.0" }, - "Ethernet80|0": { + "str3-7800-lc2-1|Asic0|Ethernet156|2": { "scheduler": "scheduler.0" }, - "Ethernet88|0": { + "str3-7800-lc2-1|Asic0|Ethernet160|2": { "scheduler": "scheduler.0" }, - "Ethernet96|0": { + "str3-7800-lc2-1|Asic0|Ethernet164|2": { "scheduler": "scheduler.0" }, - "Ethernet104|0": { + "str3-7800-lc2-1|Asic0|Ethernet168|2": { "scheduler": "scheduler.0" }, - "Ethernet112|0": { + "str3-7800-lc2-1|Asic0|Ethernet172|2": { "scheduler": "scheduler.0" }, - "Ethernet120|0": { + "str3-7800-lc2-1|Asic0|Ethernet176|2": { "scheduler": "scheduler.0" }, - "Ethernet128|0": { + "str3-7800-lc2-1|Asic0|Ethernet180|2": { "scheduler": "scheduler.0" }, - "Ethernet136|0": { + "str3-7800-lc2-1|Asic0|Ethernet184|2": { "scheduler": "scheduler.0" }, - "Ethernet0|1": { + "str3-7800-lc2-1|Asic0|Ethernet188|2": { "scheduler": "scheduler.0" }, - "Ethernet8|1": { + "str3-7800-lc8-1|asic0|Ethernet0|5": { "scheduler": "scheduler.0" }, - "Ethernet16|1": { + "str3-7800-lc8-1|asic0|Ethernet8|5": { "scheduler": "scheduler.0" }, - "Ethernet24|1": { + "str3-7800-lc8-1|asic0|Ethernet16|5": { "scheduler": "scheduler.0" }, - "Ethernet32|1": { + "str3-7800-lc8-1|asic0|Ethernet24|5": { "scheduler": "scheduler.0" }, - "Ethernet40|1": { + "str3-7800-lc8-1|asic0|Ethernet32|5": { "scheduler": "scheduler.0" }, - "Ethernet48|1": { + "str3-7800-lc8-1|asic0|Ethernet40|5": { "scheduler": "scheduler.0" }, - "Ethernet56|1": { + "str3-7800-lc8-1|asic0|Ethernet48|5": { "scheduler": "scheduler.0" }, - "Ethernet64|1": { + "str3-7800-lc8-1|asic0|Ethernet56|5": { "scheduler": "scheduler.0" }, - "Ethernet72|1": { + "str3-7800-lc8-1|asic0|Ethernet64|5": { "scheduler": "scheduler.0" }, - "Ethernet80|1": { + "str3-7800-lc8-1|asic0|Ethernet72|5": { "scheduler": "scheduler.0" }, - "Ethernet88|1": { + "str3-7800-lc8-1|asic0|Ethernet80|5": { "scheduler": "scheduler.0" }, - "Ethernet96|1": { + "str3-7800-lc8-1|asic0|Ethernet88|5": { "scheduler": "scheduler.0" }, - "Ethernet104|1": { + "str3-7800-lc8-1|asic0|Ethernet96|5": { "scheduler": "scheduler.0" }, - "Ethernet112|1": { + "str3-7800-lc8-1|asic0|Ethernet104|5": { "scheduler": "scheduler.0" }, - "Ethernet120|1": { + "str3-7800-lc8-1|asic0|Ethernet112|5": { "scheduler": "scheduler.0" }, - "Ethernet128|1": { + "str3-7800-lc8-1|asic0|Ethernet120|5": { "scheduler": "scheduler.0" }, - "Ethernet136|1": { + "str3-7800-lc8-1|asic0|Ethernet128|5": { "scheduler": "scheduler.0" }, - "Ethernet0|2": { + "str3-7800-lc8-1|asic0|Ethernet136|5": { "scheduler": "scheduler.0" }, - "Ethernet8|2": { + "str3-7800-lc8-1|asic1|Ethernet144|5": { "scheduler": "scheduler.0" }, - "Ethernet16|2": { + "str3-7800-lc8-1|asic1|Ethernet152|5": { "scheduler": "scheduler.0" }, - "Ethernet24|2": { + "str3-7800-lc8-1|asic1|Ethernet160|5": { "scheduler": "scheduler.0" }, - "Ethernet32|2": { + "str3-7800-lc8-1|asic1|Ethernet168|5": { "scheduler": "scheduler.0" }, - "Ethernet40|2": { + "str3-7800-lc8-1|asic1|Ethernet176|5": { "scheduler": "scheduler.0" }, - "Ethernet48|2": { + "str3-7800-lc8-1|asic1|Ethernet184|5": { "scheduler": "scheduler.0" }, - "Ethernet56|2": { + "str3-7800-lc8-1|asic1|Ethernet192|5": { "scheduler": "scheduler.0" }, - "Ethernet64|2": { + "str3-7800-lc8-1|asic1|Ethernet200|5": { "scheduler": "scheduler.0" }, - "Ethernet72|2": { + "str3-7800-lc8-1|asic1|Ethernet208|5": { "scheduler": "scheduler.0" }, - "Ethernet80|2": { + "str3-7800-lc8-1|asic1|Ethernet216|5": { "scheduler": "scheduler.0" }, - "Ethernet88|2": { + "str3-7800-lc8-1|asic1|Ethernet224|5": { "scheduler": "scheduler.0" }, - "Ethernet96|2": { + "str3-7800-lc8-1|asic1|Ethernet232|5": { "scheduler": "scheduler.0" }, - "Ethernet104|2": { + "str3-7800-lc8-1|asic1|Ethernet240|5": { "scheduler": "scheduler.0" }, - "Ethernet112|2": { + "str3-7800-lc8-1|asic1|Ethernet248|5": { "scheduler": "scheduler.0" }, - "Ethernet120|2": { + "str3-7800-lc8-1|asic1|Ethernet256|5": { "scheduler": "scheduler.0" }, - "Ethernet128|2": { + "str3-7800-lc8-1|asic1|Ethernet264|5": { "scheduler": "scheduler.0" }, - "Ethernet136|2": { + "str3-7800-lc8-1|asic1|Ethernet272|5": { "scheduler": "scheduler.0" }, - "Ethernet0|5": { + "str3-7800-lc8-1|asic1|Ethernet280|5": { "scheduler": "scheduler.0" }, - "Ethernet8|5": { + "str3-7800-lc1-1|Asic0|Ethernet0|5": { "scheduler": "scheduler.0" }, - "Ethernet16|5": { + "str3-7800-lc1-1|Asic0|Ethernet4|5": { "scheduler": "scheduler.0" }, - "Ethernet24|5": { + "str3-7800-lc1-1|Asic0|Ethernet8|5": { "scheduler": "scheduler.0" }, - "Ethernet32|5": { + "str3-7800-lc1-1|Asic0|Ethernet12|5": { "scheduler": "scheduler.0" }, - "Ethernet40|5": { + "str3-7800-lc1-1|Asic0|Ethernet16|5": { "scheduler": "scheduler.0" }, - "Ethernet48|5": { + "str3-7800-lc1-1|Asic0|Ethernet20|5": { "scheduler": "scheduler.0" }, - "Ethernet56|5": { + "str3-7800-lc1-1|Asic0|Ethernet24|5": { "scheduler": "scheduler.0" }, - "Ethernet64|5": { + "str3-7800-lc1-1|Asic0|Ethernet28|5": { "scheduler": "scheduler.0" }, - "Ethernet72|5": { + "str3-7800-lc1-1|Asic0|Ethernet32|5": { "scheduler": "scheduler.0" }, - "Ethernet80|5": { + "str3-7800-lc1-1|Asic0|Ethernet36|5": { "scheduler": "scheduler.0" }, - "Ethernet88|5": { + "str3-7800-lc1-1|Asic0|Ethernet40|5": { "scheduler": "scheduler.0" }, - "Ethernet96|5": { + "str3-7800-lc1-1|Asic0|Ethernet44|5": { "scheduler": "scheduler.0" }, - "Ethernet104|5": { + "str3-7800-lc1-1|Asic0|Ethernet48|5": { "scheduler": "scheduler.0" }, - "Ethernet112|5": { + "str3-7800-lc1-1|Asic0|Ethernet52|5": { "scheduler": "scheduler.0" }, - "Ethernet120|5": { + "str3-7800-lc1-1|Asic0|Ethernet56|5": { "scheduler": "scheduler.0" }, - "Ethernet128|5": { + "str3-7800-lc1-1|Asic0|Ethernet60|5": { "scheduler": "scheduler.0" }, - "Ethernet136|5": { + "str3-7800-lc1-1|Asic0|Ethernet64|5": { "scheduler": "scheduler.0" }, - "Ethernet0|6": { + "str3-7800-lc1-1|Asic0|Ethernet68|5": { "scheduler": "scheduler.0" }, - "Ethernet8|6": { + "str3-7800-lc1-1|Asic0|Ethernet72|5": { "scheduler": "scheduler.0" }, - "Ethernet16|6": { + "str3-7800-lc1-1|Asic0|Ethernet76|5": { "scheduler": "scheduler.0" }, - "Ethernet24|6": { + "str3-7800-lc1-1|Asic0|Ethernet80|5": { "scheduler": "scheduler.0" }, - "Ethernet32|6": { + "str3-7800-lc1-1|Asic0|Ethernet84|5": { "scheduler": "scheduler.0" }, - "Ethernet40|6": { + "str3-7800-lc1-1|Asic0|Ethernet88|5": { "scheduler": "scheduler.0" }, - "Ethernet48|6": { + "str3-7800-lc1-1|Asic0|Ethernet92|5": { "scheduler": "scheduler.0" }, - "Ethernet56|6": { + "str3-7800-lc1-1|Asic0|Ethernet96|5": { "scheduler": "scheduler.0" }, - "Ethernet64|6": { + "str3-7800-lc1-1|Asic0|Ethernet100|5": { "scheduler": "scheduler.0" }, - "Ethernet72|6": { + "str3-7800-lc1-1|Asic0|Ethernet104|5": { "scheduler": "scheduler.0" }, - "Ethernet80|6": { + "str3-7800-lc1-1|Asic0|Ethernet108|5": { "scheduler": "scheduler.0" }, - "Ethernet88|6": { + "str3-7800-lc1-1|Asic0|Ethernet112|5": { "scheduler": "scheduler.0" }, - "Ethernet96|6": { + "str3-7800-lc1-1|Asic0|Ethernet116|5": { "scheduler": "scheduler.0" }, - "Ethernet104|6": { + "str3-7800-lc1-1|Asic0|Ethernet120|5": { "scheduler": "scheduler.0" }, - "Ethernet112|6": { + "str3-7800-lc1-1|Asic0|Ethernet124|5": { "scheduler": "scheduler.0" }, - "Ethernet120|6": { + "str3-7800-lc1-1|Asic0|Ethernet128|5": { "scheduler": "scheduler.0" }, - "Ethernet128|6": { + "str3-7800-lc1-1|Asic0|Ethernet132|5": { "scheduler": "scheduler.0" }, - "Ethernet136|6": { + "str3-7800-lc1-1|Asic0|Ethernet136|5": { "scheduler": "scheduler.0" - } + }, + "str3-7800-lc1-1|Asic0|Ethernet140|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet144|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet148|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet152|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet156|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet160|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet164|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet168|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet172|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet176|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet180|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet184|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc1-1|Asic0|Ethernet188|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet0|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet4|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet8|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet12|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet16|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet20|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet24|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet28|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet32|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet36|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet40|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet44|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet48|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet52|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet56|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet60|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet64|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet68|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet72|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet76|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet80|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet84|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet88|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet92|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet96|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet100|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet104|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet108|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet112|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet116|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet120|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet124|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet128|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet132|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet136|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet140|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet144|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet148|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet152|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet156|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet160|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet164|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet168|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet172|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet176|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet180|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet184|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc2-1|Asic0|Ethernet188|5": { + "scheduler": "scheduler.0" + }, + "str3-7800-lc8-1|asic0|Ethernet0|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic0|Ethernet8|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic0|Ethernet16|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic0|Ethernet24|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic0|Ethernet32|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic0|Ethernet40|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic0|Ethernet48|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic0|Ethernet56|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic0|Ethernet64|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic0|Ethernet72|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic0|Ethernet80|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic0|Ethernet88|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic0|Ethernet96|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic0|Ethernet104|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic0|Ethernet112|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic0|Ethernet120|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic0|Ethernet128|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic0|Ethernet136|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic1|Ethernet144|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic1|Ethernet152|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic1|Ethernet160|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic1|Ethernet168|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic1|Ethernet176|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic1|Ethernet184|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic1|Ethernet192|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic1|Ethernet200|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic1|Ethernet208|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic1|Ethernet216|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic1|Ethernet224|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic1|Ethernet232|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic1|Ethernet240|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic1|Ethernet248|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic1|Ethernet256|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic1|Ethernet264|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic1|Ethernet272|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc8-1|asic1|Ethernet280|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet0|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet4|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet8|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet12|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet16|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet20|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet24|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet28|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet32|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet36|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet40|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet44|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet48|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet52|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet56|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet60|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet64|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet68|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet72|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet76|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet80|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet84|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet88|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet92|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet96|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet100|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet104|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet108|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet112|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet116|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet120|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet124|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet128|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet132|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet136|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet140|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet144|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet148|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet152|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet156|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet160|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet164|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet168|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet172|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet176|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet180|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet184|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc1-1|Asic0|Ethernet188|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet0|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet4|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet8|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet12|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet16|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet20|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet24|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet28|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet32|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet36|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet40|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet44|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet48|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet52|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet56|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet60|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet64|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet68|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet72|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet76|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet80|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet84|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet88|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet92|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet96|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet100|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet104|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet108|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet112|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet116|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet120|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet124|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet128|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet132|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet136|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet140|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet144|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet148|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet152|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet156|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet160|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet164|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet168|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet172|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet176|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet180|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet184|6": { + "scheduler": "scheduler.0" + }, "str3-7800-lc2-1|Asic0|Ethernet188|6": { + "scheduler": "scheduler.0" + } } } diff --git a/src/sonic-config-engine/tests/sample_output/py3/qos-nokia-ixr7250e-36x100g.json b/src/sonic-config-engine/tests/sample_output/py3/qos-nokia-ixr7250e-36x100g.json index cf6fbf64f8db..351c9cd8a509 100644 --- a/src/sonic-config-engine/tests/sample_output/py3/qos-nokia-ixr7250e-36x100g.json +++ b/src/sonic-config-engine/tests/sample_output/py3/qos-nokia-ixr7250e-36x100g.json @@ -280,419 +280,2382 @@ } }, "QUEUE": { - "Ethernet0|3": { + "svcstr-7250-lc1-1|asic0|Ethernet0|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet8|3": { + "svcstr-7250-lc1-1|asic0|Ethernet8|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet16|3": { + "svcstr-7250-lc1-1|asic0|Ethernet16|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet24|3": { + "svcstr-7250-lc1-1|asic0|Ethernet24|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet32|3": { + "svcstr-7250-lc1-1|asic0|Ethernet32|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet40|3": { + "svcstr-7250-lc1-1|asic0|Ethernet40|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet48|3": { + "svcstr-7250-lc1-1|asic0|Ethernet48|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet56|3": { + "svcstr-7250-lc1-1|asic0|Ethernet56|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet64|3": { + "svcstr-7250-lc1-1|asic0|Ethernet64|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet72|3": { + "svcstr-7250-lc1-1|asic0|Ethernet72|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet80|3": { + "svcstr-7250-lc1-1|asic0|Ethernet80|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet88|3": { + "svcstr-7250-lc1-1|asic0|Ethernet88|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet96|3": { + "svcstr-7250-lc1-1|asic0|Ethernet96|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet104|3": { + "svcstr-7250-lc1-1|asic0|Ethernet104|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet112|3": { + "svcstr-7250-lc1-1|asic0|Ethernet112|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet120|3": { + "svcstr-7250-lc1-1|asic0|Ethernet120|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet128|3": { + "svcstr-7250-lc1-1|asic0|Ethernet128|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet136|3": { + "svcstr-7250-lc1-1|asic0|Ethernet136|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet0|4": { + "svcstr-7250-lc1-1|asic1|Ethernet144|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet8|4": { + "svcstr-7250-lc1-1|asic1|Ethernet152|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet16|4": { + "svcstr-7250-lc1-1|asic1|Ethernet160|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet24|4": { + "svcstr-7250-lc1-1|asic1|Ethernet168|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet32|4": { + "svcstr-7250-lc1-1|asic1|Ethernet176|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet40|4": { + "svcstr-7250-lc1-1|asic1|Ethernet184|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet48|4": { + "svcstr-7250-lc1-1|asic1|Ethernet192|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet56|4": { + "svcstr-7250-lc1-1|asic1|Ethernet200|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet64|4": { + "svcstr-7250-lc1-1|asic1|Ethernet208|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet72|4": { + "svcstr-7250-lc1-1|asic1|Ethernet216|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet80|4": { + "svcstr-7250-lc1-1|asic1|Ethernet224|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet88|4": { + "svcstr-7250-lc1-1|asic1|Ethernet232|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet96|4": { + "svcstr-7250-lc1-1|asic1|Ethernet240|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet104|4": { + "svcstr-7250-lc1-1|asic1|Ethernet248|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet112|4": { + "svcstr-7250-lc1-1|asic1|Ethernet256|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet120|4": { + "svcstr-7250-lc1-1|asic1|Ethernet264|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet128|4": { + "svcstr-7250-lc1-1|asic1|Ethernet272|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet136|4": { + "svcstr-7250-lc1-1|asic1|Ethernet280|3": { "scheduler" : "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet0|0": { + "svcstr-7250-lc2-1|asic0|Ethernet0|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet8|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet16|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet24|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet32|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet40|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet48|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet56|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet64|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet72|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet80|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet88|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet96|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet104|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet112|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet120|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet128|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet136|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet144|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet152|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet160|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet168|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet176|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet184|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet192|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet200|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet208|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet216|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet224|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet232|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet240|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet248|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet256|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet264|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet272|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet280|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet0|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet8|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet16|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet24|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet32|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet40|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet48|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet56|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet64|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet72|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet80|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet88|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet96|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet104|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet112|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet120|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet128|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet136|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet144|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet152|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet160|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet168|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet176|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet184|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet192|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet200|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet208|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet216|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet224|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet232|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet240|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet248|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet256|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet264|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet272|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet280|3": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet0|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet8|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet16|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet24|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet32|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet40|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet48|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet56|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet64|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet72|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet80|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet88|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet96|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet104|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet112|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet120|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet128|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet136|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet144|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet152|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet160|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet168|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet176|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet184|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet192|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet200|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet208|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet216|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet224|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet232|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet240|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet248|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet256|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet264|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet272|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic1|Ethernet280|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet0|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet8|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet16|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet24|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet32|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet40|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet48|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet56|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet64|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet72|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet80|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet88|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet96|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet104|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet112|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet120|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet128|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic0|Ethernet136|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet144|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet152|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet160|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet168|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet176|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet184|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet192|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet200|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet208|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet216|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet224|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet232|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet240|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet248|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet256|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet264|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet272|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc2-1|asic1|Ethernet280|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet0|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet8|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet16|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet24|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet32|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet40|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet48|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet56|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet64|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet72|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet80|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet88|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet96|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet104|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet112|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet120|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet128|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic0|Ethernet136|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet144|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet152|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet160|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet168|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet176|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet184|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet192|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet200|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet208|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet216|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet224|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet232|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet240|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet248|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet256|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet264|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet272|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc3-1|asic1|Ethernet280|4": { + "scheduler" : "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "svcstr-7250-lc1-1|asic0|Ethernet0|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet8|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet16|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet24|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet32|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet40|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet48|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet56|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet64|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet72|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet80|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet88|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet96|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet104|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet112|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet120|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet128|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet136|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet144|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet152|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet160|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet168|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet176|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet184|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet192|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet200|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet208|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet216|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet224|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet232|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet240|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet248|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet256|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet264|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet272|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet280|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet0|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet8|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet16|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet24|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet32|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet40|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet48|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet56|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet64|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet72|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet80|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet88|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet96|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet104|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet112|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet120|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet128|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet136|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet144|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet152|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet160|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet168|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet176|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet184|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet192|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet200|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet208|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet216|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet224|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet232|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet240|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet248|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet256|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet264|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet272|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet280|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet0|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet8|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet16|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet24|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet32|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet40|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet48|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet56|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet64|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet72|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet80|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet88|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet96|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet104|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet112|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet120|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet128|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet136|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet144|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet152|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet160|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet168|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet176|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet184|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet192|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet200|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet208|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet216|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet224|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet232|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet240|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet248|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet256|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet264|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet272|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet280|0": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet0|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet8|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet16|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet24|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet32|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet40|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet48|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet56|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet64|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet72|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet80|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet88|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet96|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet104|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet112|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet120|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet128|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet136|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet144|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet152|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet160|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet168|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet176|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet184|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet192|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet200|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet208|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet216|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet224|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet232|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet240|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet248|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet256|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet264|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet272|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet280|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet0|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet8|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet16|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet24|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet32|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet40|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet48|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet56|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet64|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet72|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet80|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet88|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet96|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet104|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet112|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet120|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet128|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet136|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet144|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet152|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet160|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet168|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet176|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet184|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet192|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet200|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet208|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet216|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet224|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet232|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet240|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet248|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet256|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet264|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet272|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet280|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet0|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet8|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet16|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet24|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet32|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet40|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet48|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet56|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet64|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet72|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet80|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet88|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet96|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet104|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet112|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet120|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet128|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet136|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet144|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet152|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet160|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet168|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet176|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet184|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet192|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet200|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet208|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet216|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet224|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet232|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet240|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet248|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet256|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet264|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet272|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet280|1": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet0|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet8|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet16|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet24|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet32|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet40|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet48|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet56|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet64|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet72|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet80|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet88|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet96|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet104|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet112|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet120|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet128|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet136|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet144|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet152|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet160|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet168|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet176|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet184|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet192|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet200|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet208|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet216|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet224|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet232|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet240|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet248|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet256|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet264|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet272|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic1|Ethernet280|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet0|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet8|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet16|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet24|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet32|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet40|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet48|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet56|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet64|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet72|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet80|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet88|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet96|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet104|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet112|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet120|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet128|2": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet136|2": { "scheduler": "scheduler.0" }, - "Ethernet8|0": { + "svcstr-7250-lc2-1|asic1|Ethernet144|2": { "scheduler": "scheduler.0" }, - "Ethernet16|0": { + "svcstr-7250-lc2-1|asic1|Ethernet152|2": { "scheduler": "scheduler.0" }, - "Ethernet24|0": { + "svcstr-7250-lc2-1|asic1|Ethernet160|2": { "scheduler": "scheduler.0" }, - "Ethernet32|0": { + "svcstr-7250-lc2-1|asic1|Ethernet168|2": { "scheduler": "scheduler.0" }, - "Ethernet40|0": { + "svcstr-7250-lc2-1|asic1|Ethernet176|2": { "scheduler": "scheduler.0" }, - "Ethernet48|0": { + "svcstr-7250-lc2-1|asic1|Ethernet184|2": { "scheduler": "scheduler.0" }, - "Ethernet56|0": { + "svcstr-7250-lc2-1|asic1|Ethernet192|2": { "scheduler": "scheduler.0" }, - "Ethernet64|0": { + "svcstr-7250-lc2-1|asic1|Ethernet200|2": { "scheduler": "scheduler.0" }, - "Ethernet72|0": { + "svcstr-7250-lc2-1|asic1|Ethernet208|2": { "scheduler": "scheduler.0" }, - "Ethernet80|0": { + "svcstr-7250-lc2-1|asic1|Ethernet216|2": { "scheduler": "scheduler.0" }, - "Ethernet88|0": { + "svcstr-7250-lc2-1|asic1|Ethernet224|2": { "scheduler": "scheduler.0" }, - "Ethernet96|0": { + "svcstr-7250-lc2-1|asic1|Ethernet232|2": { "scheduler": "scheduler.0" }, - "Ethernet104|0": { + "svcstr-7250-lc2-1|asic1|Ethernet240|2": { "scheduler": "scheduler.0" }, - "Ethernet112|0": { + "svcstr-7250-lc2-1|asic1|Ethernet248|2": { "scheduler": "scheduler.0" }, - "Ethernet120|0": { + "svcstr-7250-lc2-1|asic1|Ethernet256|2": { "scheduler": "scheduler.0" }, - "Ethernet128|0": { + "svcstr-7250-lc2-1|asic1|Ethernet264|2": { "scheduler": "scheduler.0" }, - "Ethernet136|0": { + "svcstr-7250-lc2-1|asic1|Ethernet272|2": { "scheduler": "scheduler.0" }, - "Ethernet0|1": { + "svcstr-7250-lc2-1|asic1|Ethernet280|2": { "scheduler": "scheduler.0" }, - "Ethernet8|1": { + "svcstr-7250-lc3-1|asic0|Ethernet0|2": { "scheduler": "scheduler.0" }, - "Ethernet16|1": { + "svcstr-7250-lc3-1|asic0|Ethernet8|2": { "scheduler": "scheduler.0" }, - "Ethernet24|1": { + "svcstr-7250-lc3-1|asic0|Ethernet16|2": { "scheduler": "scheduler.0" }, - "Ethernet32|1": { + "svcstr-7250-lc3-1|asic0|Ethernet24|2": { "scheduler": "scheduler.0" }, - "Ethernet40|1": { + "svcstr-7250-lc3-1|asic0|Ethernet32|2": { "scheduler": "scheduler.0" }, - "Ethernet48|1": { + "svcstr-7250-lc3-1|asic0|Ethernet40|2": { "scheduler": "scheduler.0" }, - "Ethernet56|1": { + "svcstr-7250-lc3-1|asic0|Ethernet48|2": { "scheduler": "scheduler.0" }, - "Ethernet64|1": { + "svcstr-7250-lc3-1|asic0|Ethernet56|2": { "scheduler": "scheduler.0" }, - "Ethernet72|1": { + "svcstr-7250-lc3-1|asic0|Ethernet64|2": { "scheduler": "scheduler.0" }, - "Ethernet80|1": { + "svcstr-7250-lc3-1|asic0|Ethernet72|2": { "scheduler": "scheduler.0" }, - "Ethernet88|1": { + "svcstr-7250-lc3-1|asic0|Ethernet80|2": { "scheduler": "scheduler.0" }, - "Ethernet96|1": { + "svcstr-7250-lc3-1|asic0|Ethernet88|2": { "scheduler": "scheduler.0" }, - "Ethernet104|1": { + "svcstr-7250-lc3-1|asic0|Ethernet96|2": { "scheduler": "scheduler.0" }, - "Ethernet112|1": { + "svcstr-7250-lc3-1|asic0|Ethernet104|2": { "scheduler": "scheduler.0" }, - "Ethernet120|1": { + "svcstr-7250-lc3-1|asic0|Ethernet112|2": { "scheduler": "scheduler.0" }, - "Ethernet128|1": { + "svcstr-7250-lc3-1|asic0|Ethernet120|2": { "scheduler": "scheduler.0" }, - "Ethernet136|1": { + "svcstr-7250-lc3-1|asic0|Ethernet128|2": { "scheduler": "scheduler.0" }, - "Ethernet0|2": { + "svcstr-7250-lc3-1|asic0|Ethernet136|2": { "scheduler": "scheduler.0" }, - "Ethernet8|2": { + "svcstr-7250-lc3-1|asic1|Ethernet144|2": { "scheduler": "scheduler.0" }, - "Ethernet16|2": { + "svcstr-7250-lc3-1|asic1|Ethernet152|2": { "scheduler": "scheduler.0" }, - "Ethernet24|2": { + "svcstr-7250-lc3-1|asic1|Ethernet160|2": { "scheduler": "scheduler.0" }, - "Ethernet32|2": { + "svcstr-7250-lc3-1|asic1|Ethernet168|2": { "scheduler": "scheduler.0" }, - "Ethernet40|2": { + "svcstr-7250-lc3-1|asic1|Ethernet176|2": { "scheduler": "scheduler.0" }, - "Ethernet48|2": { + "svcstr-7250-lc3-1|asic1|Ethernet184|2": { "scheduler": "scheduler.0" }, - "Ethernet56|2": { + "svcstr-7250-lc3-1|asic1|Ethernet192|2": { "scheduler": "scheduler.0" }, - "Ethernet64|2": { + "svcstr-7250-lc3-1|asic1|Ethernet200|2": { "scheduler": "scheduler.0" }, - "Ethernet72|2": { + "svcstr-7250-lc3-1|asic1|Ethernet208|2": { "scheduler": "scheduler.0" }, - "Ethernet80|2": { + "svcstr-7250-lc3-1|asic1|Ethernet216|2": { "scheduler": "scheduler.0" }, - "Ethernet88|2": { + "svcstr-7250-lc3-1|asic1|Ethernet224|2": { "scheduler": "scheduler.0" }, - "Ethernet96|2": { + "svcstr-7250-lc3-1|asic1|Ethernet232|2": { "scheduler": "scheduler.0" }, - "Ethernet104|2": { + "svcstr-7250-lc3-1|asic1|Ethernet240|2": { "scheduler": "scheduler.0" }, - "Ethernet112|2": { + "svcstr-7250-lc3-1|asic1|Ethernet248|2": { "scheduler": "scheduler.0" }, - "Ethernet120|2": { + "svcstr-7250-lc3-1|asic1|Ethernet256|2": { "scheduler": "scheduler.0" }, - "Ethernet128|2": { + "svcstr-7250-lc3-1|asic1|Ethernet264|2": { "scheduler": "scheduler.0" }, - "Ethernet136|2": { + "svcstr-7250-lc3-1|asic1|Ethernet272|2": { "scheduler": "scheduler.0" }, - "Ethernet0|5": { + "svcstr-7250-lc3-1|asic1|Ethernet280|2": { "scheduler": "scheduler.0" }, - "Ethernet8|5": { + "svcstr-7250-lc1-1|asic0|Ethernet0|5": { "scheduler": "scheduler.0" }, - "Ethernet16|5": { + "svcstr-7250-lc1-1|asic0|Ethernet8|5": { "scheduler": "scheduler.0" }, - "Ethernet24|5": { + "svcstr-7250-lc1-1|asic0|Ethernet16|5": { "scheduler": "scheduler.0" }, - "Ethernet32|5": { + "svcstr-7250-lc1-1|asic0|Ethernet24|5": { "scheduler": "scheduler.0" }, - "Ethernet40|5": { + "svcstr-7250-lc1-1|asic0|Ethernet32|5": { "scheduler": "scheduler.0" }, - "Ethernet48|5": { + "svcstr-7250-lc1-1|asic0|Ethernet40|5": { "scheduler": "scheduler.0" }, - "Ethernet56|5": { + "svcstr-7250-lc1-1|asic0|Ethernet48|5": { "scheduler": "scheduler.0" }, - "Ethernet64|5": { + "svcstr-7250-lc1-1|asic0|Ethernet56|5": { "scheduler": "scheduler.0" }, - "Ethernet72|5": { + "svcstr-7250-lc1-1|asic0|Ethernet64|5": { "scheduler": "scheduler.0" }, - "Ethernet80|5": { + "svcstr-7250-lc1-1|asic0|Ethernet72|5": { "scheduler": "scheduler.0" }, - "Ethernet88|5": { + "svcstr-7250-lc1-1|asic0|Ethernet80|5": { "scheduler": "scheduler.0" }, - "Ethernet96|5": { + "svcstr-7250-lc1-1|asic0|Ethernet88|5": { "scheduler": "scheduler.0" }, - "Ethernet104|5": { + "svcstr-7250-lc1-1|asic0|Ethernet96|5": { "scheduler": "scheduler.0" }, - "Ethernet112|5": { + "svcstr-7250-lc1-1|asic0|Ethernet104|5": { "scheduler": "scheduler.0" }, - "Ethernet120|5": { + "svcstr-7250-lc1-1|asic0|Ethernet112|5": { "scheduler": "scheduler.0" }, - "Ethernet128|5": { + "svcstr-7250-lc1-1|asic0|Ethernet120|5": { "scheduler": "scheduler.0" }, - "Ethernet136|5": { + "svcstr-7250-lc1-1|asic0|Ethernet128|5": { "scheduler": "scheduler.0" }, - "Ethernet0|6": { + "svcstr-7250-lc1-1|asic0|Ethernet136|5": { "scheduler": "scheduler.0" }, - "Ethernet8|6": { + "svcstr-7250-lc1-1|asic1|Ethernet144|5": { "scheduler": "scheduler.0" }, - "Ethernet16|6": { + "svcstr-7250-lc1-1|asic1|Ethernet152|5": { "scheduler": "scheduler.0" }, - "Ethernet24|6": { + "svcstr-7250-lc1-1|asic1|Ethernet160|5": { "scheduler": "scheduler.0" }, - "Ethernet32|6": { + "svcstr-7250-lc1-1|asic1|Ethernet168|5": { "scheduler": "scheduler.0" }, - "Ethernet40|6": { + "svcstr-7250-lc1-1|asic1|Ethernet176|5": { "scheduler": "scheduler.0" }, - "Ethernet48|6": { + "svcstr-7250-lc1-1|asic1|Ethernet184|5": { "scheduler": "scheduler.0" }, - "Ethernet56|6": { + "svcstr-7250-lc1-1|asic1|Ethernet192|5": { "scheduler": "scheduler.0" }, - "Ethernet64|6": { + "svcstr-7250-lc1-1|asic1|Ethernet200|5": { "scheduler": "scheduler.0" }, - "Ethernet72|6": { + "svcstr-7250-lc1-1|asic1|Ethernet208|5": { "scheduler": "scheduler.0" }, - "Ethernet80|6": { + "svcstr-7250-lc1-1|asic1|Ethernet216|5": { "scheduler": "scheduler.0" }, - "Ethernet88|6": { + "svcstr-7250-lc1-1|asic1|Ethernet224|5": { "scheduler": "scheduler.0" }, - "Ethernet96|6": { + "svcstr-7250-lc1-1|asic1|Ethernet232|5": { "scheduler": "scheduler.0" }, - "Ethernet104|6": { + "svcstr-7250-lc1-1|asic1|Ethernet240|5": { "scheduler": "scheduler.0" }, - "Ethernet112|6": { + "svcstr-7250-lc1-1|asic1|Ethernet248|5": { "scheduler": "scheduler.0" }, - "Ethernet120|6": { + "svcstr-7250-lc1-1|asic1|Ethernet256|5": { "scheduler": "scheduler.0" }, - "Ethernet128|6": { + "svcstr-7250-lc1-1|asic1|Ethernet264|5": { "scheduler": "scheduler.0" }, - "Ethernet136|6": { + "svcstr-7250-lc1-1|asic1|Ethernet272|5": { "scheduler": "scheduler.0" - } + }, + "svcstr-7250-lc1-1|asic1|Ethernet280|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet0|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet8|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet16|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet24|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet32|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet40|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet48|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet56|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet64|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet72|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet80|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet88|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet96|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet104|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet112|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet120|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet128|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic0|Ethernet136|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet144|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet152|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet160|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet168|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet176|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet184|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet192|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet200|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet208|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet216|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet224|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet232|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet240|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet248|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet256|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet264|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet272|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc2-1|asic1|Ethernet280|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet0|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet8|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet16|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet24|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet32|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet40|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet48|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet56|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet64|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet72|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet80|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet88|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet96|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet104|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet112|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet120|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet128|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic0|Ethernet136|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet144|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet152|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet160|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet168|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet176|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet184|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet192|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet200|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet208|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet216|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet224|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet232|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet240|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet248|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet256|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet264|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet272|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc3-1|asic1|Ethernet280|5": { + "scheduler": "scheduler.0" + }, + "svcstr-7250-lc1-1|asic0|Ethernet0|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic0|Ethernet8|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic0|Ethernet16|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic0|Ethernet24|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic0|Ethernet32|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic0|Ethernet40|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic0|Ethernet48|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic0|Ethernet56|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic0|Ethernet64|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic0|Ethernet72|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic0|Ethernet80|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic0|Ethernet88|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic0|Ethernet96|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic0|Ethernet104|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic0|Ethernet112|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic0|Ethernet120|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic0|Ethernet128|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic0|Ethernet136|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic1|Ethernet144|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic1|Ethernet152|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic1|Ethernet160|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic1|Ethernet168|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic1|Ethernet176|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic1|Ethernet184|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic1|Ethernet192|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic1|Ethernet200|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic1|Ethernet208|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic1|Ethernet216|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic1|Ethernet224|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic1|Ethernet232|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic1|Ethernet240|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic1|Ethernet248|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic1|Ethernet256|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic1|Ethernet264|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic1|Ethernet272|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc1-1|asic1|Ethernet280|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic0|Ethernet0|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic0|Ethernet8|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic0|Ethernet16|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic0|Ethernet24|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic0|Ethernet32|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic0|Ethernet40|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic0|Ethernet48|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic0|Ethernet56|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic0|Ethernet64|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic0|Ethernet72|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic0|Ethernet80|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic0|Ethernet88|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic0|Ethernet96|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic0|Ethernet104|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic0|Ethernet112|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic0|Ethernet120|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic0|Ethernet128|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic0|Ethernet136|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic1|Ethernet144|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic1|Ethernet152|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic1|Ethernet160|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic1|Ethernet168|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic1|Ethernet176|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic1|Ethernet184|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic1|Ethernet192|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic1|Ethernet200|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic1|Ethernet208|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic1|Ethernet216|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic1|Ethernet224|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic1|Ethernet232|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic1|Ethernet240|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic1|Ethernet248|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic1|Ethernet256|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic1|Ethernet264|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic1|Ethernet272|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc2-1|asic1|Ethernet280|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic0|Ethernet0|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic0|Ethernet8|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic0|Ethernet16|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic0|Ethernet24|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic0|Ethernet32|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic0|Ethernet40|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic0|Ethernet48|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic0|Ethernet56|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic0|Ethernet64|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic0|Ethernet72|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic0|Ethernet80|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic0|Ethernet88|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic0|Ethernet96|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic0|Ethernet104|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic0|Ethernet112|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic0|Ethernet120|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic0|Ethernet128|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic0|Ethernet136|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic1|Ethernet144|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic1|Ethernet152|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic1|Ethernet160|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic1|Ethernet168|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic1|Ethernet176|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic1|Ethernet184|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic1|Ethernet192|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic1|Ethernet200|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic1|Ethernet208|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic1|Ethernet216|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic1|Ethernet224|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic1|Ethernet232|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic1|Ethernet240|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic1|Ethernet248|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic1|Ethernet256|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic1|Ethernet264|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic1|Ethernet272|6": { + "scheduler": "scheduler.0" + }, "svcstr-7250-lc3-1|asic1|Ethernet280|6": { + "scheduler": "scheduler.0" + } } } diff --git a/src/sonic-config-engine/tests/sample_output/py3/qos-nokia-ixr7250e-36x400g.json b/src/sonic-config-engine/tests/sample_output/py3/qos-nokia-ixr7250e-36x400g.json index cf6fbf64f8db..5a5badc9d369 100644 --- a/src/sonic-config-engine/tests/sample_output/py3/qos-nokia-ixr7250e-36x400g.json +++ b/src/sonic-config-engine/tests/sample_output/py3/qos-nokia-ixr7250e-36x400g.json @@ -280,418 +280,1660 @@ } }, "QUEUE": { - "Ethernet0|3": { - "scheduler" : "scheduler.1", + "str2-7250-lc1-1|asic0|Ethernet0|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet0|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet0|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet0|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet0|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet0|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet0|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet8|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet8|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet8|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet8|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet8|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet8|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet8|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet16|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet16|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet16|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet16|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet16|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet16|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet16|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet24|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet24|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet24|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet24|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet24|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet24|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet24|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet32|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet32|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet32|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet32|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet32|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet32|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet32|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet40|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet40|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet40|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet40|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet40|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet40|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet40|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet48|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet48|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet48|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet48|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet48|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet48|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet48|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet56|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet56|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet56|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet56|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet56|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet56|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet56|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet64|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet64|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet64|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet64|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet64|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet64|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet64|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet72|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet72|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet72|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet72|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet72|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet72|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet72|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet80|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet80|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet80|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet80|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet80|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet80|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet80|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet88|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet88|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet88|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet88|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet88|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet88|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet88|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet96|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet96|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet96|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet96|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet96|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet96|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet96|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet104|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet104|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet104|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet104|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet104|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet104|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet104|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet112|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet112|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet112|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet112|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet112|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet112|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet112|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet120|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet120|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet120|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet120|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet120|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet120|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet120|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet128|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet128|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet128|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet128|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet128|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet128|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet128|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet136|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet136|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet136|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet136|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet136|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic0|Ethernet136|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic0|Ethernet136|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet144|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet144|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet144|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet144|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet144|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet144|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet144|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet152|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet152|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet152|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet152|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet152|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet152|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet152|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet160|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet160|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet160|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet160|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet160|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet160|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet160|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet168|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet168|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet168|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet168|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet168|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet168|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet168|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet176|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet176|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet176|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet176|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet176|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet176|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet176|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet184|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet184|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet184|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet184|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet184|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet184|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet184|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet192|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet192|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet192|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet192|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet192|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet192|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet192|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet200|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet200|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet200|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet200|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet200|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet200|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet200|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet208|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet208|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet208|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet208|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet208|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet208|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet208|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet216|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet216|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet216|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet216|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet216|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet216|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet216|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet224|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet224|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet224|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet224|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet224|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet224|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet224|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet232|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet232|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet232|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet232|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet232|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet232|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet232|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet240|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet240|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet240|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet240|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet240|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet240|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet240|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet248|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet248|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet248|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet248|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet248|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet248|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet248|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet256|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet256|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet256|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet256|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet256|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet256|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet256|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet264|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet264|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet264|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet264|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet264|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet264|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet264|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet272|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet272|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet272|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet272|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet272|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet272|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet272|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet280|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet280|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet280|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet280|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet280|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc1-1|asic1|Ethernet280|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc1-1|asic1|Ethernet280|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet0|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet0|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet0|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet0|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet8|3": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet0|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet16|3": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet0|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet0|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet8|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet8|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet8|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet8|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet24|3": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet8|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet32|3": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet8|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet8|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet16|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet16|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet16|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet16|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet40|3": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet16|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet48|3": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet16|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet16|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet24|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet24|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet24|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet24|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet56|3": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet24|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet64|3": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet24|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet24|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet32|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet32|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet32|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet32|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet72|3": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet32|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet80|3": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet32|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet32|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet40|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet40|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet40|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet40|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet88|3": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet40|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet96|3": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet40|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet40|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet48|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet48|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet48|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet48|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet104|3": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet48|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet112|3": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet48|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet48|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet56|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet56|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet56|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet56|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet120|3": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet56|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet128|3": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet56|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet56|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet64|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet64|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet64|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet64|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet136|3": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet64|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet0|4": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet64|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet64|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet72|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet72|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet72|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet72|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet8|4": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet72|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet16|4": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet72|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet72|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet80|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet80|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet80|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet80|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet24|4": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet80|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet32|4": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet80|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet80|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet88|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet88|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet88|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet88|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet40|4": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet88|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet48|4": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet88|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet88|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet96|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet96|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet96|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet96|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet56|4": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet96|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet64|4": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet96|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet96|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet104|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet104|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet104|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet104|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet72|4": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet104|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet80|4": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet104|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet104|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet112|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet112|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet112|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet112|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet88|4": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet112|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet96|4": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet112|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet112|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet120|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet120|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet120|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet120|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet104|4": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet120|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet112|4": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet120|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet120|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet128|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet128|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet128|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet128|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet120|4": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet128|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet128|4": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet128|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet128|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet136|0": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet136|1": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet136|2": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet136|3": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet136|4": { - "scheduler" : "scheduler.1", + "str2-7250-lc2-1|asic0|Ethernet136|4": { + "scheduler": "scheduler.1", "wred_profile": "AZURE_LOSSLESS" }, - "Ethernet0|0": { + "str2-7250-lc2-1|asic0|Ethernet136|5": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic0|Ethernet136|6": { + "scheduler": "scheduler.0" + }, + "str2-7250-lc2-1|asic1|Ethernet144|0": { "scheduler": "scheduler.0" }, - "Ethernet8|0": { + "str2-7250-lc2-1|asic1|Ethernet144|1": { "scheduler": "scheduler.0" }, - "Ethernet16|0": { + "str2-7250-lc2-1|asic1|Ethernet144|2": { "scheduler": "scheduler.0" }, - "Ethernet24|0": { + "str2-7250-lc2-1|asic1|Ethernet144|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet144|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet144|5": { "scheduler": "scheduler.0" }, - "Ethernet32|0": { + "str2-7250-lc2-1|asic1|Ethernet144|6": { "scheduler": "scheduler.0" }, - "Ethernet40|0": { + "str2-7250-lc2-1|asic1|Ethernet152|0": { "scheduler": "scheduler.0" }, - "Ethernet48|0": { + "str2-7250-lc2-1|asic1|Ethernet152|1": { "scheduler": "scheduler.0" }, - "Ethernet56|0": { + "str2-7250-lc2-1|asic1|Ethernet152|2": { "scheduler": "scheduler.0" }, - "Ethernet64|0": { + "str2-7250-lc2-1|asic1|Ethernet152|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet152|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet152|5": { "scheduler": "scheduler.0" }, - "Ethernet72|0": { + "str2-7250-lc2-1|asic1|Ethernet152|6": { "scheduler": "scheduler.0" }, - "Ethernet80|0": { + "str2-7250-lc2-1|asic1|Ethernet160|0": { "scheduler": "scheduler.0" }, - "Ethernet88|0": { + "str2-7250-lc2-1|asic1|Ethernet160|1": { "scheduler": "scheduler.0" }, - "Ethernet96|0": { + "str2-7250-lc2-1|asic1|Ethernet160|2": { "scheduler": "scheduler.0" }, - "Ethernet104|0": { + "str2-7250-lc2-1|asic1|Ethernet160|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet160|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet160|5": { "scheduler": "scheduler.0" }, - "Ethernet112|0": { + "str2-7250-lc2-1|asic1|Ethernet160|6": { "scheduler": "scheduler.0" }, - "Ethernet120|0": { + "str2-7250-lc2-1|asic1|Ethernet168|0": { "scheduler": "scheduler.0" }, - "Ethernet128|0": { + "str2-7250-lc2-1|asic1|Ethernet168|1": { "scheduler": "scheduler.0" }, - "Ethernet136|0": { + "str2-7250-lc2-1|asic1|Ethernet168|2": { "scheduler": "scheduler.0" }, - "Ethernet0|1": { + "str2-7250-lc2-1|asic1|Ethernet168|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet168|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet168|5": { "scheduler": "scheduler.0" }, - "Ethernet8|1": { + "str2-7250-lc2-1|asic1|Ethernet168|6": { "scheduler": "scheduler.0" }, - "Ethernet16|1": { + "str2-7250-lc2-1|asic1|Ethernet176|0": { "scheduler": "scheduler.0" }, - "Ethernet24|1": { + "str2-7250-lc2-1|asic1|Ethernet176|1": { "scheduler": "scheduler.0" }, - "Ethernet32|1": { + "str2-7250-lc2-1|asic1|Ethernet176|2": { "scheduler": "scheduler.0" }, - "Ethernet40|1": { + "str2-7250-lc2-1|asic1|Ethernet176|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet176|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet176|5": { "scheduler": "scheduler.0" }, - "Ethernet48|1": { + "str2-7250-lc2-1|asic1|Ethernet176|6": { "scheduler": "scheduler.0" }, - "Ethernet56|1": { + "str2-7250-lc2-1|asic1|Ethernet184|0": { "scheduler": "scheduler.0" }, - "Ethernet64|1": { + "str2-7250-lc2-1|asic1|Ethernet184|1": { "scheduler": "scheduler.0" }, - "Ethernet72|1": { + "str2-7250-lc2-1|asic1|Ethernet184|2": { "scheduler": "scheduler.0" }, - "Ethernet80|1": { + "str2-7250-lc2-1|asic1|Ethernet184|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet184|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet184|5": { "scheduler": "scheduler.0" }, - "Ethernet88|1": { + "str2-7250-lc2-1|asic1|Ethernet184|6": { "scheduler": "scheduler.0" }, - "Ethernet96|1": { + "str2-7250-lc2-1|asic1|Ethernet192|0": { "scheduler": "scheduler.0" }, - "Ethernet104|1": { + "str2-7250-lc2-1|asic1|Ethernet192|1": { "scheduler": "scheduler.0" }, - "Ethernet112|1": { + "str2-7250-lc2-1|asic1|Ethernet192|2": { "scheduler": "scheduler.0" }, - "Ethernet120|1": { + "str2-7250-lc2-1|asic1|Ethernet192|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet192|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet192|5": { "scheduler": "scheduler.0" }, - "Ethernet128|1": { + "str2-7250-lc2-1|asic1|Ethernet192|6": { "scheduler": "scheduler.0" }, - "Ethernet136|1": { + "str2-7250-lc2-1|asic1|Ethernet200|0": { "scheduler": "scheduler.0" }, - "Ethernet0|2": { + "str2-7250-lc2-1|asic1|Ethernet200|1": { "scheduler": "scheduler.0" }, - "Ethernet8|2": { + "str2-7250-lc2-1|asic1|Ethernet200|2": { "scheduler": "scheduler.0" }, - "Ethernet16|2": { + "str2-7250-lc2-1|asic1|Ethernet200|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet200|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet200|5": { "scheduler": "scheduler.0" }, - "Ethernet24|2": { + "str2-7250-lc2-1|asic1|Ethernet200|6": { "scheduler": "scheduler.0" }, - "Ethernet32|2": { + "str2-7250-lc2-1|asic1|Ethernet208|0": { "scheduler": "scheduler.0" }, - "Ethernet40|2": { + "str2-7250-lc2-1|asic1|Ethernet208|1": { "scheduler": "scheduler.0" }, - "Ethernet48|2": { + "str2-7250-lc2-1|asic1|Ethernet208|2": { "scheduler": "scheduler.0" }, - "Ethernet56|2": { + "str2-7250-lc2-1|asic1|Ethernet208|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet208|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet208|5": { "scheduler": "scheduler.0" }, - "Ethernet64|2": { + "str2-7250-lc2-1|asic1|Ethernet208|6": { "scheduler": "scheduler.0" }, - "Ethernet72|2": { + "str2-7250-lc2-1|asic1|Ethernet216|0": { "scheduler": "scheduler.0" }, - "Ethernet80|2": { + "str2-7250-lc2-1|asic1|Ethernet216|1": { "scheduler": "scheduler.0" }, - "Ethernet88|2": { + "str2-7250-lc2-1|asic1|Ethernet216|2": { "scheduler": "scheduler.0" }, - "Ethernet96|2": { + "str2-7250-lc2-1|asic1|Ethernet216|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet216|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet216|5": { "scheduler": "scheduler.0" }, - "Ethernet104|2": { + "str2-7250-lc2-1|asic1|Ethernet216|6": { "scheduler": "scheduler.0" }, - "Ethernet112|2": { + "str2-7250-lc2-1|asic1|Ethernet224|0": { "scheduler": "scheduler.0" }, - "Ethernet120|2": { + "str2-7250-lc2-1|asic1|Ethernet224|1": { "scheduler": "scheduler.0" }, - "Ethernet128|2": { + "str2-7250-lc2-1|asic1|Ethernet224|2": { "scheduler": "scheduler.0" }, - "Ethernet136|2": { + "str2-7250-lc2-1|asic1|Ethernet224|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet224|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet224|5": { "scheduler": "scheduler.0" }, - "Ethernet0|5": { + "str2-7250-lc2-1|asic1|Ethernet224|6": { "scheduler": "scheduler.0" }, - "Ethernet8|5": { + "str2-7250-lc2-1|asic1|Ethernet232|0": { "scheduler": "scheduler.0" }, - "Ethernet16|5": { + "str2-7250-lc2-1|asic1|Ethernet232|1": { "scheduler": "scheduler.0" }, - "Ethernet24|5": { + "str2-7250-lc2-1|asic1|Ethernet232|2": { "scheduler": "scheduler.0" }, - "Ethernet32|5": { + "str2-7250-lc2-1|asic1|Ethernet232|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet232|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet232|5": { "scheduler": "scheduler.0" }, - "Ethernet40|5": { + "str2-7250-lc2-1|asic1|Ethernet232|6": { "scheduler": "scheduler.0" }, - "Ethernet48|5": { + "str2-7250-lc2-1|asic1|Ethernet240|0": { "scheduler": "scheduler.0" }, - "Ethernet56|5": { + "str2-7250-lc2-1|asic1|Ethernet240|1": { "scheduler": "scheduler.0" }, - "Ethernet64|5": { + "str2-7250-lc2-1|asic1|Ethernet240|2": { "scheduler": "scheduler.0" }, - "Ethernet72|5": { + "str2-7250-lc2-1|asic1|Ethernet240|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet240|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet240|5": { "scheduler": "scheduler.0" }, - "Ethernet80|5": { + "str2-7250-lc2-1|asic1|Ethernet240|6": { "scheduler": "scheduler.0" }, - "Ethernet88|5": { + "str2-7250-lc2-1|asic1|Ethernet248|0": { "scheduler": "scheduler.0" }, - "Ethernet96|5": { + "str2-7250-lc2-1|asic1|Ethernet248|1": { "scheduler": "scheduler.0" }, - "Ethernet104|5": { + "str2-7250-lc2-1|asic1|Ethernet248|2": { "scheduler": "scheduler.0" }, - "Ethernet112|5": { + "str2-7250-lc2-1|asic1|Ethernet248|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet248|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet248|5": { "scheduler": "scheduler.0" }, - "Ethernet120|5": { + "str2-7250-lc2-1|asic1|Ethernet248|6": { "scheduler": "scheduler.0" }, - "Ethernet128|5": { + "str2-7250-lc2-1|asic1|Ethernet256|0": { "scheduler": "scheduler.0" }, - "Ethernet136|5": { + "str2-7250-lc2-1|asic1|Ethernet256|1": { "scheduler": "scheduler.0" }, - "Ethernet0|6": { + "str2-7250-lc2-1|asic1|Ethernet256|2": { "scheduler": "scheduler.0" }, - "Ethernet8|6": { + "str2-7250-lc2-1|asic1|Ethernet256|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet256|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet256|5": { "scheduler": "scheduler.0" }, - "Ethernet16|6": { + "str2-7250-lc2-1|asic1|Ethernet256|6": { "scheduler": "scheduler.0" }, - "Ethernet24|6": { + "str2-7250-lc2-1|asic1|Ethernet264|0": { "scheduler": "scheduler.0" }, - "Ethernet32|6": { + "str2-7250-lc2-1|asic1|Ethernet264|1": { "scheduler": "scheduler.0" }, - "Ethernet40|6": { + "str2-7250-lc2-1|asic1|Ethernet264|2": { "scheduler": "scheduler.0" }, - "Ethernet48|6": { + "str2-7250-lc2-1|asic1|Ethernet264|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet264|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet264|5": { "scheduler": "scheduler.0" }, - "Ethernet56|6": { + "str2-7250-lc2-1|asic1|Ethernet264|6": { "scheduler": "scheduler.0" }, - "Ethernet64|6": { + "str2-7250-lc2-1|asic1|Ethernet272|0": { "scheduler": "scheduler.0" }, - "Ethernet72|6": { + "str2-7250-lc2-1|asic1|Ethernet272|1": { "scheduler": "scheduler.0" }, - "Ethernet80|6": { + "str2-7250-lc2-1|asic1|Ethernet272|2": { "scheduler": "scheduler.0" }, - "Ethernet88|6": { + "str2-7250-lc2-1|asic1|Ethernet272|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet272|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet272|5": { "scheduler": "scheduler.0" }, - "Ethernet96|6": { + "str2-7250-lc2-1|asic1|Ethernet272|6": { "scheduler": "scheduler.0" }, - "Ethernet104|6": { + "str2-7250-lc2-1|asic1|Ethernet280|0": { "scheduler": "scheduler.0" }, - "Ethernet112|6": { + "str2-7250-lc2-1|asic1|Ethernet280|1": { "scheduler": "scheduler.0" }, - "Ethernet120|6": { + "str2-7250-lc2-1|asic1|Ethernet280|2": { "scheduler": "scheduler.0" }, - "Ethernet128|6": { + "str2-7250-lc2-1|asic1|Ethernet280|3": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet280|4": { + "scheduler": "scheduler.1", + "wred_profile": "AZURE_LOSSLESS" + }, + "str2-7250-lc2-1|asic1|Ethernet280|5": { "scheduler": "scheduler.0" }, - "Ethernet136|6": { + "str2-7250-lc2-1|asic1|Ethernet280|6": { "scheduler": "scheduler.0" } } diff --git a/src/sonic-config-engine/tests/simple-sample-graph.xml b/src/sonic-config-engine/tests/simple-sample-graph.xml index c8cd3eacdc31..7da7cb58d4ad 100644 --- a/src/sonic-config-engine/tests/simple-sample-graph.xml +++ b/src/sonic-config-engine/tests/simple-sample-graph.xml @@ -108,6 +108,24 @@ + + BGPPeer +
10.2.0.20
+ + + + BGPSentinel + 10.154.232.0/21;10.42.168.0/21 + + + BGPPeer +
fc00:1::32
+ + + + BGPSentinelV6 + 2603:10a0:321:82f9::/64;2603:10a1:30a:8000::/59 + diff --git a/src/sonic-config-engine/tests/test_cfggen.py b/src/sonic-config-engine/tests/test_cfggen.py index b84d5acdc5e2..77c95c496795 100644 --- a/src/sonic-config-engine/tests/test_cfggen.py +++ b/src/sonic-config-engine/tests/test_cfggen.py @@ -44,6 +44,8 @@ def setUp(self): self.sample_cisco_port_config_400g = os.path.join(self.test_dir, 'sample-cisco-8101-t1-port-config.ini') self.sample_cisco_100_graph = os.path.join(self.test_dir, 'sample-cisco-8101-t1-100-minigraph.xml') self.sample_cisco_400_graph = os.path.join(self.test_dir, 'sample-cisco-8101-t1-400-minigraph.xml') + self.sample_cisco_8111_port_config = os.path.join(self.test_dir, 'sample-cisco-8111-port-config.ini') + self.sample_cisco_8111_graph = os.path.join(self.test_dir, 'sample-cisco-8111-100-minigraph.xml') # To ensure that mock config_db data is used for unit-test cases os.environ["CFGGEN_UNIT_TESTING"] = "2" @@ -696,6 +698,11 @@ def test_metadata_ntp(self): output = self.run_script(argument) self.assertEqual(utils.to_dict(output.strip()), utils.to_dict("{'10.0.10.1': {}, '10.0.10.2': {}}")) + def test_dns_nameserver(self): + argument = ['-m', self.sample_graph_metadata, '-p', self.port_config, '-v', "DNS_NAMESERVER"] + output = self.run_script(argument) + self.assertEqual(utils.to_dict(output.strip()), utils.to_dict("{'6.6.6.6': {}}")) + def test_minigraph_vnet(self, **kwargs): graph_file = kwargs.get('graph_file', self.sample_graph_simple) argument = ['-m', graph_file, '-p', self.port_config, '-v', "VNET"] @@ -729,6 +736,21 @@ def test_minigraph_bgp_voq_chassis_peer(self): output = self.run_script(argument) self.assertEqual(output.strip(), "") + def test_minigraph_bgp_sentinel(self): + argument = ['-m', self.sample_graph_simple, '-p', self.port_config, '-v', "BGP_SENTINELS[\'BGPSentinel\']"] + output = self.run_script(argument) + self.assertEqual( + utils.to_dict(output.strip()), + utils.to_dict("{'name': 'BGPSentinel', 'ip_range': ['10.154.232.0/21','10.42.168.0/21'], 'src_address': '10.2.0.20'}") + ) + + argument = ['-m', self.sample_graph_simple, '-p', self.port_config, '-v', "BGP_SENTINELS[\'BGPSentinelV6\']"] + output = self.run_script(argument) + self.assertEqual( + utils.to_dict(output.strip()), + utils.to_dict("{'name': 'BGPSentinelV6', 'ip_range': ['2603:10a0:321:82f9::/64','2603:10a1:30a:8000::/59'], 'src_address': 'fc00:1::32'}") + ) + def test_minigraph_sub_port_intf_resource_type_non_backend_tor(self, check_stderr=True): self.verify_sub_intf_non_backend_tor(graph_file=self.sample_resource_graph, check_stderr=check_stderr) @@ -1110,3 +1132,17 @@ def test_minigraph_cisco_400G_to_400G_speed(self): "{'Ethernet0': {'lanes': '2304,2305,2306,2307', 'alias': 'etp0a', 'index': '0', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA01T0:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet4': {'lanes': '2308,2309,2310,2311', 'alias': 'etp0b', 'index': '0', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA02T0:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet8': {'lanes': '2320,2321,2322,2323', 'alias': 'etp1a', 'index': '1', 'speed': '100000', 'fec': 'rs', 'description': 'etp1a', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet12': {'lanes': '2324,2325,2326,2327', 'alias': 'etp1b', 'index': '1', 'speed': '100000', 'fec': 'rs', 'description': 'etp1b', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet16': {'lanes': '2312,2313,2314,2315', 'alias': 'etp2a', 'index': '2', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA03T0:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet20': {'lanes': '2316,2317,2318,2319', 'alias': 'etp2b', 'index': '2', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA04T0:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet24': {'lanes': '2056,2057,2058,2059', 'alias': 'etp3a', 'index': '3', 'speed': '100000', 'fec': 'rs', 'description': 'etp3a', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet28': {'lanes': '2060,2061,2062,2063', 'alias': 'etp3b', 'index': '3', 'speed': '100000', 'fec': 'rs', 'description': 'etp3b', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet32': {'lanes': '1792,1793,1794,1795', 'alias': 'etp4a', 'index': '4', 'speed': '100000', 'fec': 'rs', 'description': 'etp4a', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet36': {'lanes': '1796,1797,1798,1799', 'alias': 'etp4b', 'index': '4', 'speed': '100000', 'fec': 'rs', 'description': 'etp4b', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet40': {'lanes': '2048,2049,2050,2051', 'alias': 'etp5a', 'index': '5', 'speed': '100000', 'fec': 'rs', 'description': 'etp5a', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet44': {'lanes': '2052,2053,2054,2055', 'alias': 'etp5b', 'index': '5', 'speed': '100000', 'fec': 'rs', 'description': 'etp5b', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet48': {'lanes': '2560,2561,2562,2563', 'alias': 'etp6a', 'index': '6', 'speed': '100000', 'fec': 'rs', 'description': 'etp6a', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet52': {'lanes': '2564,2565,2566,2567', 'alias': 'etp6b', 'index': '6', 'speed': '100000', 'fec': 'rs', 'description': 'etp6b', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet56': {'lanes': '2824,2825,2826,2827', 'alias': 'etp7a', 'index': '7', 'speed': '100000', 'fec': 'rs', 'description': 'etp7a', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet60': {'lanes': '2828,2829,2830,2831', 'alias': 'etp7b', 'index': '7', 'speed': '100000', 'fec': 'rs', 'description': 'etp7b', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet64': {'lanes': '2832,2833,2834,2835', 'alias': 'etp8a', 'index': '8', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA05T0:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet68': {'lanes': '2836,2837,2838,2839', 'alias': 'etp8b', 'index': '8', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA06T0:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet72': {'lanes': '2816,2817,2818,2819', 'alias': 'etp9a', 'index': '9', 'speed': '100000', 'fec': 'rs', 'description': 'etp9a', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet76': {'lanes': '2820,2821,2822,2823', 'alias': 'etp9b', 'index': '9', 'speed': '100000', 'fec': 'rs', 'description': 'etp9b', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet80': {'lanes': '2568,2569,2570,2571', 'alias': 'etp10a', 'index': '10', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA07T0:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet84': {'lanes': '2572,2573,2574,2575', 'alias': 'etp10b', 'index': '10', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA08T0:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet88': {'lanes': '2576,2577,2578,2579', 'alias': 'etp11a', 'index': '11', 'speed': '100000', 'fec': 'rs', 'description': 'etp11a', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet92': {'lanes': '2580,2581,2582,2583', 'alias': 'etp11b', 'index': '11', 'speed': '100000', 'fec': 'rs', 'description': 'etp11b', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet96': {'lanes': '1536,1537,1538,1539,1540,1541,1542,1543', 'alias': 'etp12', 'index': '12', 'speed': '400000', 'description': 'ARISTA01T2:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet104': {'lanes': '1800,1801,1802,1803,1804,1805,1806,1807', 'alias': 'etp13', 'index': '13', 'speed': '400000', 'description': 'ARISTA01T2:Ethernet2', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet112': {'lanes': '1552,1553,1554,1555,1556,1557,1558,1559', 'alias': 'etp14', 'index': '14', 'speed': '400000', 'description': 'ARISTA03T2:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet120': {'lanes': '1544,1545,1546,1547,1548,1549,1550,1551', 'alias': 'etp15', 'index': '15', 'speed': '400000', 'description': 'ARISTA03T2:Ethernet2', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet128': {'lanes': '1296,1297,1298,1299,1300,1301,1302,1303', 'alias': 'etp16', 'index': '16', 'speed': '400000', 'description': 'ARISTA05T2:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet136': {'lanes': '1288,1289,1290,1291,1292,1293,1294,1295', 'alias': 'etp17', 'index': '17', 'speed': '400000', 'description': 'ARISTA05T2:Ethernet2', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet144': {'lanes': '1280,1281,1282,1283,1284,1285,1286,1287', 'alias': 'etp18', 'index': '18', 'speed': '400000', 'description': 'ARISTA07T2:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet152': {'lanes': '1032,1033,1034,1035,1036,1037,1038,1039', 'alias': 'etp19', 'index': '19', 'speed': '400000', 'description': 'ARISTA07T2:Ethernet2', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet160': {'lanes': '264,265,266,267', 'alias': 'etp20a', 'index': '20', 'speed': '100000', 'fec': 'rs', 'description': 'etp20a', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet164': {'lanes': '268,269,270,271', 'alias': 'etp20b', 'index': '20', 'speed': '100000', 'fec': 'rs', 'description': 'etp20b', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet168': {'lanes': '272,273,274,275', 'alias': 'etp21a', 'index': '21', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA09T0:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet172': {'lanes': '276,277,278,279', 'alias': 'etp21b', 'index': '21', 'speed': '100000', 'fec': 'rs', 'description': 'etp21b', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet176': {'lanes': '16,17,18,19', 'alias': 'etp22a', 'index': '22', 'speed': '100000', 'fec': 'rs', 'description': 'etp22a', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet180': {'lanes': '20,21,22,23', 'alias': 'etp22b', 'index': '22', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA10T0:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet184': {'lanes': '0,1,2,3', 'alias': 'etp23a', 'index': '23', 'speed': '100000', 'fec': 'rs', 'description': 'etp23a', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet188': {'lanes': '4,5,6,7', 'alias': 'etp23b', 'index': '23', 'speed': '100000', 'fec': 'rs', 'description': 'etp23b', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet192': {'lanes': '256,257,258,259', 'alias': 'etp24a', 'index': '24', 'speed': '100000', 'fec': 'rs', 'description': 'etp24a', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet196': {'lanes': '260,261,262,263', 'alias': 'etp24b', 'index': '24', 'speed': '100000', 'fec': 'rs', 'description': 'etp24b', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet200': {'lanes': '8,9,10,11', 'alias': 'etp25a', 'index': '25', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA11T0:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet204': {'lanes': '12,13,14,15', 'alias': 'etp25b', 'index': '25', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA12T0:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet208': {'lanes': '1024,1025,1026,1027', 'alias': 'etp26a', 'index': '26', 'speed': '100000', 'fec': 'rs', 'description': 'etp26a', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet212': {'lanes': '1028,1029,1030,1031', 'alias': 'etp26b', 'index': '26', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA13T0:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet216': {'lanes': '768,769,770,771', 'alias': 'etp27a', 'index': '27', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA14T0:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet220': {'lanes': '772,773,774,775', 'alias': 'etp27b', 'index': '27', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA15T0:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet224': {'lanes': '524,525,526,527', 'alias': 'etp28a', 'index': '28', 'speed': '100000', 'fec': 'rs', 'description': 'etp28a', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet228': {'lanes': '520,521,522,523', 'alias': 'etp28b', 'index': '28', 'speed': '100000', 'fec': 'rs', 'description': 'etp28b', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet232': {'lanes': '776,777,778,779', 'alias': 'etp29a', 'index': '29', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA16T0:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet236': {'lanes': '780,781,782,783', 'alias': 'etp29b', 'index': '29', 'speed': '100000', 'fec': 'rs', 'description': 'etp29b', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet240': {'lanes': '516,517,518,519', 'alias': 'etp30a', 'index': '30', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA17T0:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet244': {'lanes': '512,513,514,515', 'alias': 'etp30b', 'index': '30', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA18T0:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet248': {'lanes': '528,529,530,531', 'alias': 'etp31a', 'index': '31', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA19T0:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet252': {'lanes': '532,533,534,535', 'alias': 'etp31b', 'index': '31', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA20T0:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}}" ) ) + + + def test_minigraph_cisco_400g_to_100G_speed_no_lane_change(self): + argument = ["-m", self.sample_cisco_8111_graph, "-p", self.sample_cisco_8111_port_config, "-v", "PORT"] + self.assertTrue(self.yang.validate(argument)) + output = self.run_script(argument) + self.assertEqual( + utils.to_dict(output.strip()), + utils.to_dict( + "{'Ethernet0': {'lanes': '2304,2305,2306,2307', 'alias': 'etp0a', 'index': '0', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA01T0:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet4': {'lanes': '2308,2309,2310,2311', 'alias': 'etp0b', 'index': '0', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA02T0:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet8': {'lanes': '2320,2321,2322,2323', 'alias': 'etp1a', 'index': '1', 'speed': '100000', 'fec': 'rs', 'description': 'etp1a', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet12': {'lanes': '2324,2325,2326,2327', 'alias': 'etp1b', 'index': '1', 'speed': '100000', 'fec': 'rs', 'description': 'etp1b', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet16': {'lanes': '2312,2313,2314,2315', 'alias': 'etp2a', 'index': '2', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA03T0:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet20': {'lanes': '2316,2317,2318,2319', 'alias': 'etp2b', 'index': '2', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA04T0:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet24': {'lanes': '2056,2057,2058,2059', 'alias': 'etp3a', 'index': '3', 'speed': '100000', 'fec': 'rs', 'description': 'etp3a', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet28': {'lanes': '2060,2061,2062,2063', 'alias': 'etp3b', 'index': '3', 'speed': '100000', 'fec': 'rs', 'description': 'etp3b', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet32': {'lanes': '1792,1793,1794,1795', 'alias': 'etp4a', 'index': '4', 'speed': '100000', 'fec': 'rs', 'description': 'etp4a', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet36': {'lanes': '1796,1797,1798,1799', 'alias': 'etp4b', 'index': '4', 'speed': '100000', 'fec': 'rs', 'description': 'etp4b', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet40': {'lanes': '2048,2049,2050,2051', 'alias': 'etp5a', 'index': '5', 'speed': '100000', 'fec': 'rs', 'description': 'etp5a', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet44': {'lanes': '2052,2053,2054,2055', 'alias': 'etp5b', 'index': '5', 'speed': '100000', 'fec': 'rs', 'description': 'etp5b', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet48': {'lanes': '2560,2561,2562,2563', 'alias': 'etp6a', 'index': '6', 'speed': '100000', 'fec': 'rs', 'description': 'etp6a', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet52': {'lanes': '2564,2565,2566,2567', 'alias': 'etp6b', 'index': '6', 'speed': '100000', 'fec': 'rs', 'description': 'etp6b', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet56': {'lanes': '2824,2825,2826,2827', 'alias': 'etp7a', 'index': '7', 'speed': '100000', 'fec': 'rs', 'description': 'etp7a', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet60': {'lanes': '2828,2829,2830,2831', 'alias': 'etp7b', 'index': '7', 'speed': '100000', 'fec': 'rs', 'description': 'etp7b', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet64': {'lanes': '2832,2833,2834,2835', 'alias': 'etp8a', 'index': '8', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA05T0:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet68': {'lanes': '2836,2837,2838,2839', 'alias': 'etp8b', 'index': '8', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA06T0:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet72': {'lanes': '2816,2817,2818,2819', 'alias': 'etp9a', 'index': '9', 'speed': '100000', 'fec': 'rs', 'description': 'etp9a', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet76': {'lanes': '2820,2821,2822,2823', 'alias': 'etp9b', 'index': '9', 'speed': '100000', 'fec': 'rs', 'description': 'etp9b', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet80': {'lanes': '2568,2569,2570,2571', 'alias': 'etp10a', 'index': '10', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA07T0:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet84': {'lanes': '2572,2573,2574,2575', 'alias': 'etp10b', 'index': '10', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA08T0:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet88': {'lanes': '2576,2577,2578,2579', 'alias': 'etp11a', 'index': '11', 'speed': '100000', 'fec': 'rs', 'description': 'etp11a', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet92': {'lanes': '2580,2581,2582,2583', 'alias': 'etp11b', 'index': '11', 'speed': '100000', 'fec': 'rs', 'description': 'etp11b', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet96': {'lanes': '1536,1537,1538,1539', 'alias': 'etp12', 'index': '12', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA01T2:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet104': {'lanes': '1800,1801,1802,1803', 'alias': 'etp13', 'index': '13', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA01T2:Ethernet2', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet112': {'lanes': '1552,1553,1554,1555', 'alias': 'etp14', 'index': '14', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA03T2:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet120': {'lanes': '1544,1545,1546,1547', 'alias': 'etp15', 'index': '15', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA03T2:Ethernet2', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet128': {'lanes': '1296,1297,1298,1299', 'alias': 'etp16', 'index': '16', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA05T2:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet136': {'lanes': '1288,1289,1290,1291', 'alias': 'etp17', 'index': '17', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA05T2:Ethernet2', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet144': {'lanes': '1280,1281,1282,1283', 'alias': 'etp18', 'index': '18', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA07T2:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet152': {'lanes': '1032,1033,1034,1035', 'alias': 'etp19', 'index': '19', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA07T2:Ethernet2', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet160': {'lanes': '264,265,266,267', 'alias': 'etp20a', 'index': '20', 'speed': '100000', 'fec': 'rs', 'description': 'etp20a', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet164': {'lanes': '268,269,270,271', 'alias': 'etp20b', 'index': '20', 'speed': '100000', 'fec': 'rs', 'description': 'etp20b', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet168': {'lanes': '272,273,274,275', 'alias': 'etp21a', 'index': '21', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA09T0:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet172': {'lanes': '276,277,278,279', 'alias': 'etp21b', 'index': '21', 'speed': '100000', 'fec': 'rs', 'description': 'etp21b', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet176': {'lanes': '16,17,18,19', 'alias': 'etp22a', 'index': '22', 'speed': '100000', 'fec': 'rs', 'description': 'etp22a', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet180': {'lanes': '20,21,22,23', 'alias': 'etp22b', 'index': '22', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA10T0:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet184': {'lanes': '0,1,2,3', 'alias': 'etp23a', 'index': '23', 'speed': '100000', 'fec': 'rs', 'description': 'etp23a', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet188': {'lanes': '4,5,6,7', 'alias': 'etp23b', 'index': '23', 'speed': '100000', 'fec': 'rs', 'description': 'etp23b', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet192': {'lanes': '256,257,258,259', 'alias': 'etp24a', 'index': '24', 'speed': '100000', 'fec': 'rs', 'description': 'etp24a', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet196': {'lanes': '260,261,262,263', 'alias': 'etp24b', 'index': '24', 'speed': '100000', 'fec': 'rs', 'description': 'etp24b', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet200': {'lanes': '8,9,10,11', 'alias': 'etp25a', 'index': '25', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA11T0:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet204': {'lanes': '12,13,14,15', 'alias': 'etp25b', 'index': '25', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA12T0:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet208': {'lanes': '1024,1025,1026,1027', 'alias': 'etp26a', 'index': '26', 'speed': '100000', 'fec': 'rs', 'description': 'etp26a', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet212': {'lanes': '1028,1029,1030,1031', 'alias': 'etp26b', 'index': '26', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA13T0:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet216': {'lanes': '768,769,770,771', 'alias': 'etp27a', 'index': '27', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA14T0:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet220': {'lanes': '772,773,774,775', 'alias': 'etp27b', 'index': '27', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA15T0:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet224': {'lanes': '524,525,526,527', 'alias': 'etp28a', 'index': '28', 'speed': '100000', 'fec': 'rs', 'description': 'etp28a', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet228': {'lanes': '520,521,522,523', 'alias': 'etp28b', 'index': '28', 'speed': '100000', 'fec': 'rs', 'description': 'etp28b', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet232': {'lanes': '776,777,778,779', 'alias': 'etp29a', 'index': '29', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA16T0:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet236': {'lanes': '780,781,782,783', 'alias': 'etp29b', 'index': '29', 'speed': '100000', 'fec': 'rs', 'description': 'etp29b', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off'}, 'Ethernet240': {'lanes': '516,517,518,519', 'alias': 'etp30a', 'index': '30', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA17T0:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet244': {'lanes': '512,513,514,515', 'alias': 'etp30b', 'index': '30', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA18T0:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet248': {'lanes': '528,529,530,531', 'alias': 'etp31a', 'index': '31', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA19T0:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}, 'Ethernet252': {'lanes': '532,533,534,535', 'alias': 'etp31b', 'index': '31', 'speed': '100000', 'fec': 'rs', 'description': 'ARISTA20T0:Ethernet1', 'mtu': '9100', 'tpid': '0x8100', 'pfc_asym': 'off', 'admin_status': 'up'}}" + ) + ) + + diff --git a/src/sonic-device-data/LICENSE b/src/sonic-device-data/LICENSE deleted file mode 100644 index 2ff086dedcdd..000000000000 --- a/src/sonic-device-data/LICENSE +++ /dev/null @@ -1,15 +0,0 @@ -Copyright (C) 2017 Microsoft - -This program is free software; you can redistribute it and/or -modify it under the terms of the GNU General Public License -as published by the Free Software Foundation; either version 2 -of the License, or (at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. diff --git a/src/sonic-device-data/tests/permitted_list b/src/sonic-device-data/tests/permitted_list index 82c92126e6bc..cb99b99fd3d9 100644 --- a/src/sonic-device-data/tests/permitted_list +++ b/src/sonic-device-data/tests/permitted_list @@ -168,6 +168,7 @@ ifp_inports_support_enable port_flex_enable pdma_descriptor_prefetch_enable pktdma_poll_mode_channel_bitmap +warmboot_knet_shutdown_mode num_queues_pci num_queues_uc0 num_queues_uc1 @@ -333,3 +334,8 @@ cmic_dma_abort_in_cold_boot hybrid_pfc_deadlock_enable sai_pfc_dlr_init_capability appl_param_nof_ports_per_modid +sai_fdb_entry_l2_discard_src_enable +svi_my_station_optimization +sai_nbr_bcast_ifp_optimized +sai_pfc_defaults_disable +sai_optimized_mmu diff --git a/src/sonic-device-health b/src/sonic-device-health index 222fd8ebd670..cf9423251b96 160000 --- a/src/sonic-device-health +++ b/src/sonic-device-health @@ -1 +1 @@ -Subproject commit 222fd8ebd6707e8cf0d9296fbcbc43590c8f0176 +Subproject commit cf9423251b96520494ae21e6935909af166ca856 diff --git a/src/sonic-frr/frr b/src/sonic-frr/frr index 79188bf710e9..7a2b85ae52b3 160000 --- a/src/sonic-frr/frr +++ b/src/sonic-frr/frr @@ -1 +1 @@ -Subproject commit 79188bf710e92acf42fb5b9b0a2e9593a5ee9b05 +Subproject commit 7a2b85ae52b354248fa9da04100efba0ec6c70c9 diff --git a/src/sonic-frr/patch/0001-Add-support-of-bgp-tcp-DSCP-value.patch b/src/sonic-frr/patch/0001-Add-support-of-bgp-tcp-DSCP-value.patch deleted file mode 100644 index ba5668394385..000000000000 --- a/src/sonic-frr/patch/0001-Add-support-of-bgp-tcp-DSCP-value.patch +++ /dev/null @@ -1,141 +0,0 @@ -From 4ab192df23362e64d1a11441fae82329388f103e Mon Sep 17 00:00:00 2001 -From: Pavel Shirshov -Date: Mon, 16 Nov 2020 18:00:12 -0800 -Subject: [PATCH 1/8] Add support of bgp tcp DSCP value - ---- - bgpd/bgp_network.c | 11 ++++------- - bgpd/bgp_vty.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ - bgpd/bgpd.c | 1 + - bgpd/bgpd.h | 3 +++ - 4 files changed, 52 insertions(+), 7 deletions(-) - -diff --git a/bgpd/bgp_network.c b/bgpd/bgp_network.c -index 3fb7619ed..70c771683 100644 ---- a/bgpd/bgp_network.c -+++ b/bgpd/bgp_network.c -@@ -743,11 +743,9 @@ int bgp_connect(struct peer *peer) - #ifdef IPTOS_PREC_INTERNETCONTROL - frr_with_privs(&bgpd_privs) { - if (sockunion_family(&peer->su) == AF_INET) -- setsockopt_ipv4_tos(peer->fd, -- IPTOS_PREC_INTERNETCONTROL); -+ setsockopt_ipv4_tos(peer->fd, peer->bgp->tcp_dscp); - else if (sockunion_family(&peer->su) == AF_INET6) -- setsockopt_ipv6_tclass(peer->fd, -- IPTOS_PREC_INTERNETCONTROL); -+ setsockopt_ipv6_tclass(peer->fd, peer->bgp->tcp_dscp); - } - #endif - -@@ -824,10 +822,9 @@ static int bgp_listener(int sock, struct sockaddr *sa, socklen_t salen, - - #ifdef IPTOS_PREC_INTERNETCONTROL - if (sa->sa_family == AF_INET) -- setsockopt_ipv4_tos(sock, IPTOS_PREC_INTERNETCONTROL); -+ setsockopt_ipv4_tos(sock, bgp->tcp_dscp); - else if (sa->sa_family == AF_INET6) -- setsockopt_ipv6_tclass(sock, -- IPTOS_PREC_INTERNETCONTROL); -+ setsockopt_ipv6_tclass(sock, bgp->tcp_dscp); - #endif - - sockopt_v6only(sa->sa_family, sock); -diff --git a/bgpd/bgp_vty.c b/bgpd/bgp_vty.c -index 4df2abef8..950d1d25c 100644 ---- a/bgpd/bgp_vty.c -+++ b/bgpd/bgp_vty.c -@@ -1558,6 +1558,42 @@ DEFUN (no_router_bgp, - return CMD_SUCCESS; - } - -+/* bgp session-dscp */ -+ -+DEFUN (bgp_session_dscp, -+ bgp_session_dscp_cmd, -+ "bgp session-dscp DSCP", -+ BGP_STR -+ "Override default (C0) bgp TCP session DSCP value\n" -+ "Manually configured dscp parameter\n") -+{ -+ struct bgp *bgp = VTY_GET_CONTEXT(bgp); -+ -+ uint8_t value = (uint8_t)strtol(argv[2]->arg, NULL, 16); -+ if ((value == 0 && errno == EINVAL) || (value > 0x3f)) -+ { -+ vty_out (vty, "%% Malformed bgp session-dscp parameter\n"); -+ return CMD_WARNING_CONFIG_FAILED; -+ } -+ -+ bgp->tcp_dscp = value << 2; -+ -+ return CMD_SUCCESS; -+} -+ -+DEFUN (no_bgp_session_dscp, -+ no_bgp_session_dscp_cmd, -+ "no bgp session-dscp", -+ NO_STR -+ BGP_STR -+ "Override default (C0) bgp tcp session ip dscp value\n") -+{ -+ struct bgp *bgp = VTY_GET_CONTEXT(bgp); -+ -+ bgp->tcp_dscp = IPTOS_PREC_INTERNETCONTROL; -+ -+ return CMD_SUCCESS; -+} - - /* BGP router-id. */ - -@@ -17053,6 +17089,10 @@ int bgp_config_write(struct vty *vty) - if (CHECK_FLAG(bgp->flags, BGP_FLAG_NO_FAST_EXT_FAILOVER)) - vty_out(vty, " no bgp fast-external-failover\n"); - -+ /* BGP session DSCP value */ -+ if (bgp->tcp_dscp != IPTOS_PREC_INTERNETCONTROL) -+ vty_out(vty, " bgp session-dscp %02X\n", bgp->tcp_dscp >> 2); -+ - /* BGP router ID. */ - if (bgp->router_id_static.s_addr != INADDR_ANY) - vty_out(vty, " bgp router-id %pI4\n", -@@ -17662,6 +17702,10 @@ void bgp_vty_init(void) - /* "no router bgp" commands. */ - install_element(CONFIG_NODE, &no_router_bgp_cmd); - -+ /* "bgp session-dscp command */ -+ install_element (BGP_NODE, &bgp_session_dscp_cmd); -+ install_element (BGP_NODE, &no_bgp_session_dscp_cmd); -+ - /* "bgp router-id" commands. */ - install_element(BGP_NODE, &bgp_router_id_cmd); - install_element(BGP_NODE, &no_bgp_router_id_cmd); -diff --git a/bgpd/bgpd.c b/bgpd/bgpd.c -index 7e528b219..005523544 100644 ---- a/bgpd/bgpd.c -+++ b/bgpd/bgpd.c -@@ -3229,6 +3229,7 @@ static struct bgp *bgp_create(as_t *as, const char *name, - bgp->evpn_info = XCALLOC(MTYPE_BGP_EVPN_INFO, - sizeof(struct bgp_evpn_info)); - -+ bgp->tcp_dscp = IPTOS_PREC_INTERNETCONTROL; - bgp_evpn_init(bgp); - bgp_evpn_vrf_es_init(bgp); - bgp_pbr_init(bgp); -diff --git a/bgpd/bgpd.h b/bgpd/bgpd.h -index 8b93c450e..e780d8a03 100644 ---- a/bgpd/bgpd.h -+++ b/bgpd/bgpd.h -@@ -743,6 +743,9 @@ struct bgp { - /* Weighted ECMP related config. */ - enum bgp_link_bw_handling lb_handling; - -+ /* dscp value for tcp sessions */ -+ uint8_t tcp_dscp; -+ - /* Process Queue for handling routes */ - struct work_queue *process_queue; - --- -2.12.2 - diff --git a/src/sonic-frr/patch/0002-Reduce-severity-of-Vty-connected-from-message.patch b/src/sonic-frr/patch/0001-Reduce-severity-of-Vty-connected-from-message.patch similarity index 52% rename from src/sonic-frr/patch/0002-Reduce-severity-of-Vty-connected-from-message.patch rename to src/sonic-frr/patch/0001-Reduce-severity-of-Vty-connected-from-message.patch index 764d38463289..3aafe4c93d03 100644 --- a/src/sonic-frr/patch/0002-Reduce-severity-of-Vty-connected-from-message.patch +++ b/src/sonic-frr/patch/0001-Reduce-severity-of-Vty-connected-from-message.patch @@ -1,17 +1,16 @@ -From 15274a197e4d3b7ac0f11ca63a5274f1168739f5 Mon Sep 17 00:00:00 2001 +From 69370e52e94c66e06052a7859dd059dfa34fd61e Mon Sep 17 00:00:00 2001 From: Pavel Shirshov Date: Mon, 16 Nov 2020 18:11:47 -0800 -Subject: [PATCH 2/8] Reduce severity of 'Vty connected from' message +Subject: [PATCH] From 15274a197e4d3b7ac0f11ca63a5274f1168739f5 Mon Sep 17 + 00:00:00 2001 Subject: [PATCH 2/8] Reduce severity of 'Vty connected from' + message ---- - lib/vty.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/vty.c b/lib/vty.c -index 8eaf13619..7edeb5538 100644 +index ab98ac14e..c32fc13ba 100644 --- a/lib/vty.c +++ b/lib/vty.c -@@ -1814,7 +1814,7 @@ static int vty_accept(struct thread *thread) +@@ -1843,7 +1843,7 @@ static void vty_accept(struct thread *thread) zlog_info("can't set sockopt to vty_sock : %s", safe_strerror(errno)); @@ -19,7 +18,7 @@ index 8eaf13619..7edeb5538 100644 + zlog_debug("Vty connection from %pSU", &su); vty_create(vty_sock, &su); - + } -- -2.12.2 +2.17.1 diff --git a/src/sonic-frr/patch/0002-Allow-BGP-attr-NEXT_HOP-to-be-0.0.0.0-due-to-allevia.patch b/src/sonic-frr/patch/0002-Allow-BGP-attr-NEXT_HOP-to-be-0.0.0.0-due-to-allevia.patch new file mode 100644 index 000000000000..f80a3d5d5e4e --- /dev/null +++ b/src/sonic-frr/patch/0002-Allow-BGP-attr-NEXT_HOP-to-be-0.0.0.0-due-to-allevia.patch @@ -0,0 +1,25 @@ +From 44ed2b0d2a2ca6029238118603264e02e2e965f4 Mon Sep 17 00:00:00 2001 +From: Pavel Shirshov +Date: Mon, 16 Nov 2020 18:33:46 -0800 +Subject: [PATCH] From afff474c79e0c177e090d1b45d68c9f816a52e3e Mon Sep 17 + 00:00:00 2001 Subject: [PATCH 4/8] Allow BGP attr NEXT_HOP to be 0.0.0.0 due + to alleviate + + +diff --git a/bgpd/bgp_route.c b/bgpd/bgp_route.c +index f4dff0d80..f00c54c40 100644 +--- a/bgpd/bgp_route.c ++++ b/bgpd/bgp_route.c +@@ -3835,8 +3835,7 @@ bool bgp_update_martian_nexthop(struct bgp *bgp, afi_t afi, safi_t safi, + + /* If NEXT_HOP is present, validate it. */ + if (attr->flag & ATTR_FLAG_BIT(BGP_ATTR_NEXT_HOP)) { +- if (attr->nexthop.s_addr == INADDR_ANY || +- !ipv4_unicast_valid(&attr->nexthop) || ++ if (!ipv4_unicast_valid(&attr->nexthop) || + bgp_nexthop_self(bgp, afi, type, stype, attr, dest)) + return true; + } +-- +2.17.1 + diff --git a/src/sonic-frr/patch/0005-nexthops-compare-vrf-only-if-ip-type.patch b/src/sonic-frr/patch/0003-nexthops-compare-vrf-only-if-ip-type.patch similarity index 75% rename from src/sonic-frr/patch/0005-nexthops-compare-vrf-only-if-ip-type.patch rename to src/sonic-frr/patch/0003-nexthops-compare-vrf-only-if-ip-type.patch index 2db1105622eb..1d5b89a30f72 100644 --- a/src/sonic-frr/patch/0005-nexthops-compare-vrf-only-if-ip-type.patch +++ b/src/sonic-frr/patch/0003-nexthops-compare-vrf-only-if-ip-type.patch @@ -1,15 +1,12 @@ -From 786087468520db44c55e3566f77438b41f52763f Mon Sep 17 00:00:00 2001 +From 2b778b1984c5f88500625a0e96a5ba1d1fe0316c Mon Sep 17 00:00:00 2001 From: Pavel Shirshov Date: Mon, 16 Nov 2020 18:35:01 -0800 -Subject: [PATCH 5/8] nexthops compare vrf only if ip type +Subject: [PATCH] From 786087468520db44c55e3566f77438b41f52763f Mon Sep 17 + 00:00:00 2001 Subject: [PATCH 5/8] nexthops compare vrf only if ip type ---- - lib/nexthop.c | 12 ++++++------ - lib/zclient.c | 12 ++++++------ - 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/lib/nexthop.c b/lib/nexthop.c -index e17eeb830..a1ce22e3b 100644 +index 248acd270..7ebc4fefb 100644 --- a/lib/nexthop.c +++ b/lib/nexthop.c @@ -140,12 +140,6 @@ static int _nexthop_cmp_no_labels(const struct nexthop *next1, @@ -39,10 +36,10 @@ index e17eeb830..a1ce22e3b 100644 if (ret != 0) return ret; diff --git a/lib/zclient.c b/lib/zclient.c -index 445837017..c104623b7 100644 +index 07c7e5aea..0082b2148 100644 --- a/lib/zclient.c +++ b/lib/zclient.c -@@ -864,12 +864,6 @@ static int zapi_nexthop_cmp_no_labels(const struct zapi_nexthop *next1, +@@ -869,12 +869,6 @@ static int zapi_nexthop_cmp_no_labels(const struct zapi_nexthop *next1, { int ret = 0; @@ -55,7 +52,7 @@ index 445837017..c104623b7 100644 if (next1->type < next2->type) return -1; -@@ -885,6 +879,12 @@ static int zapi_nexthop_cmp_no_labels(const struct zapi_nexthop *next1, +@@ -890,6 +884,12 @@ static int zapi_nexthop_cmp_no_labels(const struct zapi_nexthop *next1, switch (next1->type) { case NEXTHOP_TYPE_IPV4: case NEXTHOP_TYPE_IPV6: @@ -69,5 +66,5 @@ index 445837017..c104623b7 100644 &next2->gate); if (ret != 0) -- -2.12.2 +2.17.1 diff --git a/src/sonic-frr/patch/0004-Allow-BGP-attr-NEXT_HOP-to-be-0.0.0.0-due-to-allevia.patch b/src/sonic-frr/patch/0004-Allow-BGP-attr-NEXT_HOP-to-be-0.0.0.0-due-to-allevia.patch deleted file mode 100644 index 9d2f08efb191..000000000000 --- a/src/sonic-frr/patch/0004-Allow-BGP-attr-NEXT_HOP-to-be-0.0.0.0-due-to-allevia.patch +++ /dev/null @@ -1,27 +0,0 @@ -From afff474c79e0c177e090d1b45d68c9f816a52e3e Mon Sep 17 00:00:00 2001 -From: Pavel Shirshov -Date: Mon, 16 Nov 2020 18:33:46 -0800 -Subject: [PATCH 4/8] Allow BGP attr NEXT_HOP to be 0.0.0.0 due to - alleviate - ---- - bgpd/bgp_route.c | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - -diff --git a/bgpd/bgp_route.c b/bgpd/bgp_route.c -index b297ca006..d4b5066c6 100644 ---- a/bgpd/bgp_route.c -+++ b/bgpd/bgp_route.c -@@ -3625,8 +3625,7 @@ bool bgp_update_martian_nexthop(struct bgp *bgp, afi_t afi, safi_t safi, - - /* If NEXT_HOP is present, validate it. */ - if (attr->flag & ATTR_FLAG_BIT(BGP_ATTR_NEXT_HOP)) { -- if (attr->nexthop.s_addr == INADDR_ANY -- || IPV4_CLASS_DE(ntohl(attr->nexthop.s_addr)) -+ if (IPV4_CLASS_DE(ntohl(attr->nexthop.s_addr)) - || bgp_nexthop_self(bgp, afi, type, stype, attr, dest)) - return true; - } --- -2.12.2 - diff --git a/src/sonic-frr/patch/0006-frr-remove-frr-log-outchannel-to-var-log-frr.log.patch b/src/sonic-frr/patch/0004-frr-remove-frr-log-outchannel-to-var-log-frr.log.patch similarity index 60% rename from src/sonic-frr/patch/0006-frr-remove-frr-log-outchannel-to-var-log-frr.log.patch rename to src/sonic-frr/patch/0004-frr-remove-frr-log-outchannel-to-var-log-frr.log.patch index 6d3db6d518e9..6936e36100a0 100644 --- a/src/sonic-frr/patch/0006-frr-remove-frr-log-outchannel-to-var-log-frr.log.patch +++ b/src/sonic-frr/patch/0004-frr-remove-frr-log-outchannel-to-var-log-frr.log.patch @@ -1,27 +1,25 @@ -From 0417036a3aece862c95111d4646ca7508a028165 Mon Sep 17 00:00:00 2001 +From ece5d83bebfe2345edf8e18f5af713bd99cc3739 Mon Sep 17 00:00:00 2001 From: Ying Xie Date: Wed, 25 Nov 2020 22:28:43 +0000 -Subject: [PATCH] [PATCH 6/8] [frr] remove frr log outchannel to /var/log/frr.log -SONiC runs frr inside a docker and the logs are sent to base image -via rsyslog and recorded already. There is no need to keep the -frr.log inside the docker. It will grow and take all harddrive -space eventually. +Subject: [PATCH] From 0417036a3aece862c95111d4646ca7508a028165 Mon Sep 17 + 00:00:00 2001 Subject: [PATCH] [PATCH 6/8] [frr] remove frr log outchannel to + /var/log/frr.log SONiC runs frr inside a docker and the logs are sent to base + image via rsyslog and recorded already. There is no need to keep the frr.log + inside the docker. It will grow and take all harddrive space eventually. ---- - tools/etc/rsyslog.d/45-frr.conf | 19 ------------------- - 1 file changed, 19 deletions(-) diff --git a/tools/etc/rsyslog.d/45-frr.conf b/tools/etc/rsyslog.d/45-frr.conf -index feeeb13f1..fcd23d23a 100644 +index 75b20d76b..9cdd55762 100644 --- a/tools/etc/rsyslog.d/45-frr.conf +++ b/tools/etc/rsyslog.d/45-frr.conf -@@ -2,25 +2,6 @@ +@@ -2,29 +2,6 @@ # to /var/log/frr/frr.log, then drops the message so it does # not also go to /var/log/syslog, so the messages are not duplicated -$outchannel frr_log,/var/log/frr/frr.log -if $programname == 'babeld' or - $programname == 'bgpd' or +- $programname == 'bfdd' or - $programname == 'eigrpd' or - $programname == 'frr' or - $programname == 'isisd' or @@ -31,6 +29,9 @@ index feeeb13f1..fcd23d23a 100644 - $programname == 'ospf6d' or - $programname == 'ospfd' or - $programname == 'pimd' or +- $programname == 'pim6d' or +- $programname == 'pathd' or +- $programname == 'pbrd' or - $programname == 'ripd' or - $programname == 'ripngd' or - $programname == 'vrrpd' or @@ -40,7 +41,7 @@ index feeeb13f1..fcd23d23a 100644 - if $programname == 'babeld' or $programname == 'bgpd' or - $programname == 'eigrpd' or + $programname == 'bfdd' or -- -2.12.2 +2.17.1 diff --git a/src/sonic-frr/patch/0007-Add-support-of-bgp-l3vni-evpn.patch b/src/sonic-frr/patch/0005-Add-support-of-bgp-l3vni-evpn.patch similarity index 78% rename from src/sonic-frr/patch/0007-Add-support-of-bgp-l3vni-evpn.patch rename to src/sonic-frr/patch/0005-Add-support-of-bgp-l3vni-evpn.patch index 5efd29fdcf09..fe2636c2e289 100644 --- a/src/sonic-frr/patch/0007-Add-support-of-bgp-l3vni-evpn.patch +++ b/src/sonic-frr/patch/0005-Add-support-of-bgp-l3vni-evpn.patch @@ -1,22 +1,16 @@ -From 369bbb4d62aa47d5a6d5157ca6ea819c4cb80f15 Mon Sep 17 00:00:00 2001 +From f5f0018266c98ad96cdbe69ae60d501de21e5600 Mon Sep 17 00:00:00 2001 From: Stepan Blyschak Date: Thu, 20 Oct 2022 13:19:31 +0000 -Subject: [PATCH 07/13] Added support of L3VNI EVPN +Subject: [PATCH] From 369bbb4d62aa47d5a6d5157ca6ea819c4cb80f15 Mon Sep 17 + 00:00:00 2001 Subject: [PATCH 07/13] Added support of L3VNI EVPN This is temp patch till Prefix to ARP indirection is add in neighorch Signed-off-by: Kishore Kunal Signed-off-by: Stepan Blyschak ---- - lib/nexthop.c | 1 + - lib/nexthop.h | 7 ++++++- - zebra/rt_netlink.c | 15 ++++++++++++++- - zebra/zapi_msg.c | 4 ++++ - zebra/zebra_dplane.c | 2 +- - 5 files changed, 26 insertions(+), 3 deletions(-) diff --git a/lib/nexthop.c b/lib/nexthop.c -index a1ce22e3b..10a87f072 100644 +index 7ebc4fefb..2f7bb0e7b 100644 --- a/lib/nexthop.c +++ b/lib/nexthop.c @@ -813,6 +813,7 @@ void nexthop_copy_no_recurse(struct nexthop *copy, @@ -28,13 +22,13 @@ index a1ce22e3b..10a87f072 100644 nexthop_add_labels(copy, nexthop->nh_label_type, nexthop->nh_label->num_labels, diff --git a/lib/nexthop.h b/lib/nexthop.h -index 320b46315..77eea3674 100644 +index f1309aa52..7b4bbbafd 100644 --- a/lib/nexthop.h +++ b/lib/nexthop.h @@ -66,6 +66,11 @@ enum nh_encap_type { /* Backup index value is limited */ #define NEXTHOP_BACKUP_IDX_MAX 255 - + +struct vxlan_nh_encap { + vni_t vni; + struct ethaddr rmac; @@ -43,31 +37,31 @@ index 320b46315..77eea3674 100644 /* Nexthop structure. */ struct nexthop { struct nexthop *next; -@@ -135,7 +140,7 @@ struct nexthop { +@@ -137,7 +142,7 @@ struct nexthop { /* Encapsulation information. */ enum nh_encap_type nh_encap_type; union { - vni_t vni; + struct vxlan_nh_encap encap_data; } nh_encap; - + /* SR-TE color used for matching SR-TE policies */ diff --git a/zebra/rt_netlink.c b/zebra/rt_netlink.c -index 03c84d6dc..a56a95276 100644 +index 79d79d74b..325199eff 100644 --- a/zebra/rt_netlink.c +++ b/zebra/rt_netlink.c -@@ -1869,6 +1869,7 @@ static int netlink_route_nexthop_encap(struct nlmsghdr *n, size_t nlen, +@@ -1969,6 +1969,7 @@ static int netlink_route_nexthop_encap(struct nlmsghdr *n, size_t nlen, struct nexthop *nh) { struct rtattr *nest; + struct vxlan_nh_encap* encap_data; - + switch (nh->nh_encap_type) { case NET_VXLAN: -@@ -1879,9 +1880,21 @@ static int netlink_route_nexthop_encap(struct nlmsghdr *n, size_t nlen, +@@ -1979,9 +1980,21 @@ static int netlink_route_nexthop_encap(struct nlmsghdr *n, size_t nlen, if (!nest) return false; - + + encap_data = &nh->nh_encap.encap_data; + if (!nl_attr_put32(n, nlen, 0 /* VXLAN_VNI */, @@ -88,10 +82,10 @@ index 03c84d6dc..a56a95276 100644 break; } diff --git a/zebra/zapi_msg.c b/zebra/zapi_msg.c -index 5cf7d815d..529cbb44b 100644 +index c0945eae2..157c33ced 100644 --- a/zebra/zapi_msg.c +++ b/zebra/zapi_msg.c -@@ -1577,6 +1577,8 @@ static struct nexthop *nexthop_from_zapi(const struct zapi_nexthop *api_nh, +@@ -1605,6 +1605,8 @@ static struct nexthop *nexthop_from_zapi(const struct zapi_nexthop *api_nh, vtep_ip.ipa_type = IPADDR_V4; memcpy(&(vtep_ip.ipaddr_v4), &(api_nh->gate.ipv4), sizeof(struct in_addr)); @@ -99,8 +93,8 @@ index 5cf7d815d..529cbb44b 100644 + &api_nh->rmac, ETH_ALEN); zebra_rib_queue_evpn_route_add( api_nh->vrf_id, &api_nh->rmac, &vtep_ip, p); - } -@@ -1610,6 +1612,8 @@ static struct nexthop *nexthop_from_zapi(const struct zapi_nexthop *api_nh, + SET_FLAG(nexthop->flags, NEXTHOP_FLAG_EVPN); +@@ -1639,6 +1641,8 @@ static struct nexthop *nexthop_from_zapi(const struct zapi_nexthop *api_nh, vtep_ip.ipa_type = IPADDR_V6; memcpy(&vtep_ip.ipaddr_v6, &(api_nh->gate.ipv6), sizeof(struct in6_addr)); @@ -108,12 +102,12 @@ index 5cf7d815d..529cbb44b 100644 + &api_nh->rmac, ETH_ALEN); zebra_rib_queue_evpn_route_add( api_nh->vrf_id, &api_nh->rmac, &vtep_ip, p); - } + SET_FLAG(nexthop->flags, NEXTHOP_FLAG_EVPN); diff --git a/zebra/zebra_dplane.c b/zebra/zebra_dplane.c -index 656ebcf3b..bd59df189 100644 +index f6f436f39..c8511bd28 100644 --- a/zebra/zebra_dplane.c +++ b/zebra/zebra_dplane.c -@@ -2420,7 +2420,7 @@ int dplane_ctx_route_init(struct zebra_dplane_ctx *ctx, enum dplane_op_e op, +@@ -2917,7 +2917,7 @@ int dplane_ctx_route_init(struct zebra_dplane_ctx *ctx, enum dplane_op_e op, zl3vni = zl3vni_from_vrf(nexthop->vrf_id); if (zl3vni && is_l3vni_oper_up(zl3vni)) { nexthop->nh_encap_type = NET_VXLAN; @@ -121,7 +115,7 @@ index 656ebcf3b..bd59df189 100644 + nexthop->nh_encap.encap_data.vni = zl3vni->vni; } } - --- -2.30.2 + +-- +2.17.1 diff --git a/src/sonic-frr/patch/0006-Link-local-scope-was-not-set-while-binding-socket-for-bgp-ipv6-link-local-neighbors.patch b/src/sonic-frr/patch/0006-Link-local-scope-was-not-set-while-binding-socket-for-bgp-ipv6-link-local-neighbors.patch new file mode 100644 index 000000000000..575e636593bb --- /dev/null +++ b/src/sonic-frr/patch/0006-Link-local-scope-was-not-set-while-binding-socket-for-bgp-ipv6-link-local-neighbors.patch @@ -0,0 +1,28 @@ +From 4fdb386b2b41278ca10431fe2b386853985aff0f Mon Sep 17 00:00:00 2001 +From: Akhilesh Samineni +Date: Mon, 5 Apr 2021 13:21:40 -0700 +Subject: [PATCH] From 92ab2d74fca06f86c00d886ac249f7f2d89e93fe Mon Sep 17 + 00:00:00 2001 Subject: [PATCH 8/8] Link local scope was not set while binding + socket with local address causing socket errors for bgp ipv6 link local + neighbors. + + +diff --git a/bgpd/bgp_network.c b/bgpd/bgp_network.c +index 76bb9949d..5acdde08d 100644 +--- a/bgpd/bgp_network.c ++++ b/bgpd/bgp_network.c +@@ -678,6 +678,11 @@ int bgp_update_address(struct interface *ifp, const union sockunion *dst, + return 1; + + prefix2sockunion(sel, addr); ++ ++ if (IN6_IS_ADDR_LINKLOCAL(&addr->sin6.sin6_addr)) { ++ addr->sin6.sin6_scope_id = ifp->ifindex; ++ } ++ + return 0; + } + +-- +2.17.1 + diff --git a/src/sonic-frr/patch/0009-ignore-route-from-default-table.patch b/src/sonic-frr/patch/0007-ignore-route-from-default-table.patch similarity index 68% rename from src/sonic-frr/patch/0009-ignore-route-from-default-table.patch rename to src/sonic-frr/patch/0007-ignore-route-from-default-table.patch index 6af5bfc45783..52167d765287 100644 --- a/src/sonic-frr/patch/0009-ignore-route-from-default-table.patch +++ b/src/sonic-frr/patch/0007-ignore-route-from-default-table.patch @@ -1,21 +1,19 @@ -From ca66350aecf7db3354019480d11754fabae3a97c Mon Sep 17 00:00:00 2001 +From 1a639f2dcd400997345dab424a2adbc091752661 Mon Sep 17 00:00:00 2001 From: Stepan Blyschak Date: Thu, 20 Oct 2022 13:07:18 +0000 -Subject: [PATCH 09/13] ignore route from default table +Subject: [PATCH] From ca66350aecf7db3354019480d11754fabae3a97c Mon Sep 17 + 00:00:00 2001 Subject: [PATCH 09/13] ignore route from default table Signed-off-by: Stepan Blyschak ---- - zebra/dplane_fpm_nl.c | 9 +++++++++ - 1 file changed, 9 insertions(+) diff --git a/zebra/dplane_fpm_nl.c b/zebra/dplane_fpm_nl.c -index 3b02128c9..da8504adf 100644 +index 0a9fecc9d..b18a96353 100644 --- a/zebra/dplane_fpm_nl.c +++ b/zebra/dplane_fpm_nl.c -@@ -699,6 +699,15 @@ static int fpm_nl_enqueue(struct fpm_nl_ctx *fnc, struct zebra_dplane_ctx *ctx) +@@ -814,6 +814,15 @@ static int fpm_nl_enqueue(struct fpm_nl_ctx *fnc, struct zebra_dplane_ctx *ctx) || op == DPLANE_OP_NH_UPDATE)) return 0; - + + /* + * Ignore route from default table, because when mgmt port goes down, + * zebra will remove the default route and causing ASIC to blackhole IO. @@ -26,7 +24,8 @@ index 3b02128c9..da8504adf 100644 + } + nl_buf_len = 0; - + frr_mutex_lock_autounlock(&fnc->obuf_mutex); --- -2.30.2 +-- +2.17.1 + diff --git a/src/sonic-frr/patch/0008-Link-local-scope-was-not-set-while-binding-socket-for-bgp-ipv6-link-local-neighbors.patch b/src/sonic-frr/patch/0008-Link-local-scope-was-not-set-while-binding-socket-for-bgp-ipv6-link-local-neighbors.patch deleted file mode 100644 index c2ff17dab88c..000000000000 --- a/src/sonic-frr/patch/0008-Link-local-scope-was-not-set-while-binding-socket-for-bgp-ipv6-link-local-neighbors.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 92ab2d74fca06f86c00d886ac249f7f2d89e93fe Mon Sep 17 00:00:00 2001 -From: Akhilesh Samineni -Date: Mon, 5 Apr 2021 13:21:40 -0700 -Subject: [PATCH 8/8] Link local scope was not set while binding socket - with local address causing socket errors for bgp ipv6 link local neighbors. - ---- - bgpd/bgp_network.c | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/bgpd/bgp_network.c b/bgpd/bgp_network.c -index 70c771683..dbc9870a5 100644 ---- a/bgpd/bgp_network.c -+++ b/bgpd/bgp_network.c -@@ -662,6 +662,11 @@ static int bgp_update_address(struct interface *ifp, const union sockunion *dst, - return 1; - - prefix2sockunion(sel, addr); -+ -+ if (IN6_IS_ADDR_LINKLOCAL(&addr->sin6.sin6_addr)) { -+ addr->sin6.sin6_scope_id = ifp->ifindex; -+ } -+ - return 0; - } - --- -2.12.2 - diff --git a/src/sonic-frr/patch/0023-Use-vrf_id-for-vrf-not-tabled_id.patch b/src/sonic-frr/patch/0008-Use-vrf_id-for-vrf-not-tabled_id.patch similarity index 84% rename from src/sonic-frr/patch/0023-Use-vrf_id-for-vrf-not-tabled_id.patch rename to src/sonic-frr/patch/0008-Use-vrf_id-for-vrf-not-tabled_id.patch index b69ce1fbb811..ae8b05f06bd0 100644 --- a/src/sonic-frr/patch/0023-Use-vrf_id-for-vrf-not-tabled_id.patch +++ b/src/sonic-frr/patch/0008-Use-vrf_id-for-vrf-not-tabled_id.patch @@ -1,18 +1,16 @@ -From 349e3f758860be0077b69919c39764d3486ec44a Mon Sep 17 00:00:00 2001 +From 44f3736ee601e06e43e978fa075402c3da4823bd Mon Sep 17 00:00:00 2001 From: Stepan Blyschak Date: Mon, 16 Jan 2023 11:45:19 +0000 -Subject: [PATCH] use vrf id instead of table id +Subject: [PATCH] From 349e3f758860be0077b69919c39764d3486ec44a Mon Sep 17 + 00:00:00 2001 Subject: [PATCH] use vrf id instead of table id Signed-off-by: Stepan Blyschak ---- - zebra/rt_netlink.c | 74 ++++++++++++++++++++++++++++++++++++++-------- - 1 file changed, 61 insertions(+), 13 deletions(-) diff --git a/zebra/rt_netlink.c b/zebra/rt_netlink.c -index 29137a09f..e7b808754 100644 +index 325199eff..587045eac 100644 --- a/zebra/rt_netlink.c +++ b/zebra/rt_netlink.c -@@ -388,6 +388,30 @@ vrf_id_t vrf_lookup_by_table(uint32_t table_id, ns_id_t ns_id) +@@ -406,6 +406,30 @@ vrf_id_t vrf_lookup_by_table(uint32_t table_id, ns_id_t ns_id) return VRF_DEFAULT; } @@ -43,7 +41,7 @@ index 29137a09f..e7b808754 100644 /** * @parse_encap_mpls() - Parses encapsulated mpls attributes * @tb: Pointer to rtattr to look for nested items in. -@@ -754,14 +778,26 @@ int netlink_route_change_read_unicast_internal(struct nlmsghdr *h, +@@ -782,14 +806,26 @@ int netlink_route_change_read_unicast_internal(struct nlmsghdr *h, if (rtm->rtm_family == AF_MPLS) return 0; @@ -77,8 +75,8 @@ index 29137a09f..e7b808754 100644 if (vrf_id == VRF_DEFAULT) { if (!is_zebra_valid_kernel_table(table) && !is_zebra_main_routing_table(table)) -@@ -2004,12 +2040,24 @@ ssize_t netlink_route_multipath_msg_encode(int cmd, - #endif +@@ -2102,12 +2138,24 @@ ssize_t netlink_route_multipath_msg_encode(int cmd, + /* Table corresponding to this route. */ table_id = dplane_ctx_get_table(ctx); - if (table_id < 256) @@ -109,5 +107,5 @@ index 29137a09f..e7b808754 100644 if (IS_ZEBRA_DEBUG_KERNEL) -- -2.30.2 +2.17.1 diff --git a/src/sonic-frr/patch/0026-bgpd-Ensure-suppress-fib-pending-works-with-network-.patch b/src/sonic-frr/patch/0009-bgpd-Ensure-suppress-fib-pending-works-with-network-.patch similarity index 80% rename from src/sonic-frr/patch/0026-bgpd-Ensure-suppress-fib-pending-works-with-network-.patch rename to src/sonic-frr/patch/0009-bgpd-Ensure-suppress-fib-pending-works-with-network-.patch index 4805315cee1d..a276f9ba5b49 100644 --- a/src/sonic-frr/patch/0026-bgpd-Ensure-suppress-fib-pending-works-with-network-.patch +++ b/src/sonic-frr/patch/0009-bgpd-Ensure-suppress-fib-pending-works-with-network-.patch @@ -1,8 +1,9 @@ -From 5a1d3c9e24791ebdb7e375a02afe9c5f6146c488 Mon Sep 17 00:00:00 2001 +From c4a198c977168a6bd420197d19c8a4c0f4eacc8a Mon Sep 17 00:00:00 2001 From: Donald Sharp Date: Wed, 22 Mar 2023 11:35:28 -0400 -Subject: [PATCH] bgpd: Ensure suppress-fib-pending works with network - statements +Subject: [PATCH] From 5a1d3c9e24791ebdb7e375a02afe9c5f6146c488 Mon Sep 17 + 00:00:00 2001 Subject: [PATCH] bgpd: Ensure suppress-fib-pending works with + network statements The flag for telling BGP that a route is expected to be installed first before notifying a peer was always being set upon receipt @@ -22,17 +23,12 @@ cover the case when a network statement is added after the route has been learned from a peer. Signed-off-by: Donald Sharp ---- - bgpd/bgp_route.c | 22 ------------------- - bgpd/bgp_zebra.c | 14 ++++++++++++ - .../bgp_suppress_fib/test_bgp_suppress_fib.py | 14 ++++++++++++ - 3 files changed, 28 insertions(+), 22 deletions(-) diff --git a/bgpd/bgp_route.c b/bgpd/bgp_route.c -index d4b5066c6..c01e2fd2c 100644 +index f00c54c40..a7a5c9849 100644 --- a/bgpd/bgp_route.c +++ b/bgpd/bgp_route.c -@@ -2994,11 +2994,6 @@ static void bgp_process_main_one(struct bgp *bgp, struct bgp_dest *dest, +@@ -3203,11 +3203,6 @@ static void bgp_process_main_one(struct bgp *bgp, struct bgp_dest *dest, if (bgp_fibupd_safi(safi) && !bgp_option_check(BGP_OPT_NO_FIB)) { @@ -44,7 +40,7 @@ index d4b5066c6..c01e2fd2c 100644 if (new_select->type == ZEBRA_ROUTE_BGP && (new_select->sub_type == BGP_ROUTE_NORMAL || new_select->sub_type -@@ -3104,10 +3099,6 @@ static void bgp_process_main_one(struct bgp *bgp, struct bgp_dest *dest, +@@ -3313,10 +3308,6 @@ static void bgp_process_main_one(struct bgp *bgp, struct bgp_dest *dest, || new_select->sub_type == BGP_ROUTE_AGGREGATE || new_select->sub_type == BGP_ROUTE_IMPORTED)) { @@ -55,10 +51,10 @@ index d4b5066c6..c01e2fd2c 100644 /* if this is an evpn imported type-5 prefix, * we need to withdraw the route first to clear * the nh neigh and the RMAC entry. -@@ -3953,19 +3944,6 @@ int bgp_update(struct peer *peer, const struct prefix *p, uint32_t addpath_id, +@@ -4261,18 +4252,6 @@ void bgp_update(struct peer *peer, const struct prefix *p, uint32_t addpath_id, + bgp_attr_flush(&new_attr); goto filtered; } - - /* The flag BGP_NODE_FIB_INSTALL_PENDING is for the following - * condition : - * Suppress fib is enabled @@ -71,17 +67,16 @@ index d4b5066c6..c01e2fd2c 100644 - && (!bgp_option_check(BGP_OPT_NO_FIB)) - && (!CHECK_FLAG(dest->flags, BGP_NODE_FIB_INSTALLED))) - SET_FLAG(dest->flags, BGP_NODE_FIB_INSTALL_PENDING); -- - /* If maximum prefix count is configured and current prefix - * count exeed it. - */ + + /* If neighbor soo is configured, tag all incoming routes with + * this SoO tag and then filter out advertisements in diff --git a/bgpd/bgp_zebra.c b/bgpd/bgp_zebra.c -index 21912d143..71816813a 100644 +index 95e80ba1b..efcf49785 100644 --- a/bgpd/bgp_zebra.c +++ b/bgpd/bgp_zebra.c -@@ -1269,6 +1269,14 @@ void bgp_zebra_announce(struct bgp_dest *dest, const struct prefix *p, - uint32_t nhg_id = 0; - bool is_add; +@@ -1322,6 +1322,14 @@ void bgp_zebra_announce(struct bgp_dest *dest, const struct prefix *p, + uint32_t bos = 0; + uint32_t exp = 0; + /* + * BGP is installing this route and bgp has been configured @@ -94,7 +89,7 @@ index 21912d143..71816813a 100644 /* Don't try to install if we're not connected to Zebra or Zebra doesn't * know of this instance. */ -@@ -1681,6 +1689,12 @@ void bgp_zebra_withdraw(const struct prefix *p, struct bgp_path_info *info, +@@ -1758,6 +1766,12 @@ void bgp_zebra_withdraw(const struct prefix *p, struct bgp_path_info *info, struct zapi_route api; struct peer *peer; @@ -108,10 +103,10 @@ index 21912d143..71816813a 100644 * know of this instance. */ diff --git a/tests/topotests/bgp_suppress_fib/test_bgp_suppress_fib.py b/tests/topotests/bgp_suppress_fib/test_bgp_suppress_fib.py -index 96a294cae..f812079c7 100644 +index 6d2b65a61..7bcb28166 100644 --- a/tests/topotests/bgp_suppress_fib/test_bgp_suppress_fib.py +++ b/tests/topotests/bgp_suppress_fib/test_bgp_suppress_fib.py -@@ -229,6 +229,20 @@ def test_bgp_allow_as_in(): +@@ -230,6 +230,20 @@ def test_bgp_allow_as_in(): assertmsg = '"r2" 192.168.1.1/32 route should be gone' assert result is None, assertmsg @@ -133,5 +128,5 @@ index 96a294cae..f812079c7 100644 if __name__ == "__main__": args = ["-s"] + sys.argv[1:] -- -2.20.1 +2.17.1 diff --git a/src/sonic-frr/patch/0010-bgpd-Change-log-level-for-graceful-restart-events.patch b/src/sonic-frr/patch/0010-bgpd-Change-log-level-for-graceful-restart-events.patch new file mode 100644 index 000000000000..54fcc1575a75 --- /dev/null +++ b/src/sonic-frr/patch/0010-bgpd-Change-log-level-for-graceful-restart-events.patch @@ -0,0 +1,116 @@ +From a05f213343ee7ee5dbfcfd1984c40db5c262db3c Mon Sep 17 00:00:00 2001 +From: stormliang +Date: Mon, 19 Jun 2023 13:57:01 +0000 +Subject: [PATCH] From c423bce4db804c1d07d65ce3d06a9e62c4eceb2b Mon Sep 17 + 00:00:00 2001 Subject: [PATCH] change log level for graceful restart events + + +diff --git a/bgpd/bgp_fsm.c b/bgpd/bgp_fsm.c +index 9624adfbe..74b4dfc4a 100644 +--- a/bgpd/bgp_fsm.c ++++ b/bgpd/bgp_fsm.c +@@ -778,10 +778,10 @@ static void bgp_graceful_restart_timer_expire(struct thread *thread) + + peer = THREAD_ARG(thread); + +- if (bgp_debug_neighbor_events(peer)) { +- zlog_debug("%pBP graceful restart timer expired", peer); +- zlog_debug("%pBP graceful restart stalepath timer stopped", +- peer); ++ if (peer) { ++ zlog_info("%pBP graceful restart timer expired", peer); ++ zlog_info("%pBP graceful restart stalepath timer stopped", ++ peer); + } + + FOREACH_AFI_SAFI (afi, safi) { +@@ -842,8 +842,8 @@ static void bgp_graceful_stale_timer_expire(struct thread *thread) + + peer = THREAD_ARG(thread); + +- if (bgp_debug_neighbor_events(peer)) +- zlog_debug("%pBP graceful restart stalepath timer expired", ++ if (peer) ++ zlog_info("%pBP graceful restart stalepath timer expired", + peer); + + /* NSF delete stale route */ +@@ -1412,20 +1412,17 @@ enum bgp_fsm_state_progress bgp_stop(struct peer *peer) + /* graceful restart */ + if (peer->t_gr_stale) { + THREAD_OFF(peer->t_gr_stale); +- if (bgp_debug_neighbor_events(peer)) +- zlog_debug( +- "%pBP graceful restart stalepath timer stopped", +- peer); ++ zlog_info( ++ "%pBP graceful restart stalepath timer stopped", ++ peer); + } + if (CHECK_FLAG(peer->sflags, PEER_STATUS_NSF_WAIT)) { +- if (bgp_debug_neighbor_events(peer)) { +- zlog_debug( +- "%pBP graceful restart timer started for %d sec", +- peer, peer->v_gr_restart); +- zlog_debug( +- "%pBP graceful restart stalepath timer started for %d sec", +- peer, peer->bgp->stalepath_time); +- } ++ zlog_info( ++ "%pBP graceful restart timer started for %d sec", ++ peer, peer->v_gr_restart); ++ zlog_info( ++ "%pBP graceful restart stalepath timer started for %d sec", ++ peer, peer->bgp->stalepath_time); + BGP_TIMER_ON(peer->t_gr_restart, + bgp_graceful_restart_timer_expire, + peer->v_gr_restart); +@@ -2225,17 +2222,15 @@ static enum bgp_fsm_state_progress bgp_establish(struct peer *peer) + UNSET_FLAG(peer->sflags, PEER_STATUS_NSF_MODE); + if (peer->t_gr_stale) { + THREAD_OFF(peer->t_gr_stale); +- if (bgp_debug_neighbor_events(peer)) +- zlog_debug( +- "%pBP graceful restart stalepath timer stopped", +- peer); ++ zlog_info( ++ "%pBP graceful restart stalepath timer stopped", ++ peer); + } + } + + if (peer->t_gr_restart) { + THREAD_OFF(peer->t_gr_restart); +- if (bgp_debug_neighbor_events(peer)) +- zlog_debug("%pBP graceful restart timer stopped", peer); ++ zlog_info("%pBP graceful restart timer stopped", peer); + } + + /* Reset uptime, turn on keepalives, send current table. */ +diff --git a/bgpd/bgpd.c b/bgpd/bgpd.c +index 8b3a1e3dd..2f3b837a5 100644 +--- a/bgpd/bgpd.c ++++ b/bgpd/bgpd.c +@@ -2453,15 +2453,13 @@ void peer_nsf_stop(struct peer *peer) + + if (peer->t_gr_restart) { + THREAD_OFF(peer->t_gr_restart); +- if (bgp_debug_neighbor_events(peer)) +- zlog_debug("%pBP graceful restart timer stopped", peer); ++ zlog_info("%pBP graceful restart timer stopped", peer); + } + if (peer->t_gr_stale) { + THREAD_OFF(peer->t_gr_stale); +- if (bgp_debug_neighbor_events(peer)) +- zlog_debug( +- "%pBP graceful restart stalepath timer stopped", +- peer); ++ zlog_info( ++ "%pBP graceful restart stalepath timer stopped", ++ peer); + } + bgp_clear_route_all(peer); + } +-- +2.17.1 + diff --git a/src/sonic-frr/patch/0010-zebra-Note-when-the-netlink-DUMP-command-is-interrup.patch b/src/sonic-frr/patch/0010-zebra-Note-when-the-netlink-DUMP-command-is-interrup.patch deleted file mode 100644 index 3da1ab318d1c..000000000000 --- a/src/sonic-frr/patch/0010-zebra-Note-when-the-netlink-DUMP-command-is-interrup.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 8f10590a85669f300d2706d5ef1e560cdbaaf0f8 Mon Sep 17 00:00:00 2001 -From: Donald Sharp -Date: Fri, 25 Mar 2022 19:08:14 -0400 -Subject: [PATCH 10/10] zebra: Note when the netlink DUMP command is - interrupted - -There exists code paths in the linux kernel where a dump command -will be interrupted( I am not sure I understand what this really -means ) and the data sent back from the kernel is wrong or incomplete. - -At this point in time I am not 100% certain what should be done, but -let's start noticing that this has happened so we can formulate a plan -or allow the end operator to know bad stuff is a foot at the circle K. - -Signed-off-by: Donald Sharp ---- - zebra/kernel_netlink.c | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - -diff --git a/zebra/kernel_netlink.c b/zebra/kernel_netlink.c -index ccafc8f0c..9dc597fad 100644 ---- a/zebra/kernel_netlink.c -+++ b/zebra/kernel_netlink.c -@@ -972,6 +972,18 @@ int netlink_parse_info(int (*filter)(struct nlmsghdr *, ns_id_t, int), - return err; - } - -+ /* -+ * What is the right thing to do? The kernel -+ * is telling us that the dump request was interrupted -+ * and we more than likely are out of luck and have -+ * missed data from the kernel. At this point in time -+ * lets just note that this is happening. -+ */ -+ if (h->nlmsg_flags & NLM_F_DUMP_INTR) -+ flog_err( -+ EC_ZEBRA_NETLINK_BAD_SEQUENCE, -+ "netlink recvmsg: The Dump request was interrupted"); -+ - /* OK we got netlink message. */ - if (IS_ZEBRA_DEBUG_KERNEL) - zlog_debug( --- -2.17.1 - diff --git a/src/sonic-frr/patch/0011-bgpd-enhanced-capability-is-always-turned-on-for-int.patch b/src/sonic-frr/patch/0011-bgpd-enhanced-capability-is-always-turned-on-for-int.patch deleted file mode 100644 index cefa7c31449f..000000000000 --- a/src/sonic-frr/patch/0011-bgpd-enhanced-capability-is-always-turned-on-for-int.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 4db4fc1bf0599f79067bfd62aa435be8e161d81e Mon Sep 17 00:00:00 2001 -From: Donald Sharp -Date: Tue, 3 May 2022 12:51:21 -0400 -Subject: [PATCH] bgpd: enhanced capability is always turned on for interface - based peers - -FRR is displaying that the peer enhanced capability command is not -turned on when the interface is part of a peer group. Saving the -config and then reloading actually turns it off. - -Fix the code so that FRR does not display the enhanced capability -for interface based peers. - -Fixes: #11108 -Signed-off-by: Donald Sharp ---- - bgpd/bgp_vty.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/bgpd/bgp_vty.c b/bgpd/bgp_vty.c -index 4df2abef8..6fcce239b 100644 ---- a/bgpd/bgp_vty.c -+++ b/bgpd/bgp_vty.c -@@ -16586,7 +16586,8 @@ static void bgp_config_write_peer_global(struct vty *vty, struct bgp *bgp, - - /* capability extended-nexthop */ - if (peergroup_flag_check(peer, PEER_FLAG_CAPABILITY_ENHE)) { -- if (CHECK_FLAG(peer->flags_invert, PEER_FLAG_CAPABILITY_ENHE)) -+ if (CHECK_FLAG(peer->flags_invert, PEER_FLAG_CAPABILITY_ENHE) && -+ !peer->conf_if) - vty_out(vty, - " no neighbor %s capability extended-nexthop\n", - addr); --- -2.17.1 - diff --git a/src/sonic-frr/patch/0011-zebra-Static-routes-async-notification-do-not-need-t.patch b/src/sonic-frr/patch/0011-zebra-Static-routes-async-notification-do-not-need-t.patch new file mode 100644 index 000000000000..6b633badf97b --- /dev/null +++ b/src/sonic-frr/patch/0011-zebra-Static-routes-async-notification-do-not-need-t.patch @@ -0,0 +1,99 @@ +From 56d349ef47ba24bcf838488b1e40474755655259 Mon Sep 17 00:00:00 2001 +From: Donald Sharp +Date: Thu, 29 Jun 2023 09:35:00 -0400 +Subject: [PATCH] zebra: Static routes async notification do not need this test + +When using asic_offload with an asynchronous notification the +rib_route_match_ctx function is testing for distance and tag +being correct against the re. + +Normal route notification for static routes is this(well really all routes): +a) zebra dplane generates a ctx to send to the dplane for route install +b) dplane installs it in the kernel +c) if the dplane_fpm_nl.c module is being used it installs it. +d) The context's success code is set to it worked and passes the context +back up to zebra for processing. +e) Zebra master receives this and checks the distance and tag are correct +for static routes and accepts the route and marks it installed. + +If the operator is using a wait for install mechansim where the dplane +is asynchronously sending the result back up at a future time *and* +it is using the dplane_fpm_nl.c code where it uses the rt_netlink.c +route parsing code, then there is no way to set distance as that we +do not pass distance to the kernel. + +As such static routes were never being properly handled since the re and +context would not match and the route would still be marked as queued. + +Modify the code such that the asynchronous path notification for static +routes ignores the distance and tag's as that there is no way to test +for this data from that path at this point in time. + +Signed-off-by: Donald Sharp + +diff --git a/zebra/zebra_rib.c b/zebra/zebra_rib.c +index fd6df441c6..039c44cc09 100644 +--- a/zebra/zebra_rib.c ++++ b/zebra/zebra_rib.c +@@ -1465,7 +1465,7 @@ static void zebra_rib_evaluate_mpls(struct route_node *rn) + */ + static bool rib_route_match_ctx(const struct route_entry *re, + const struct zebra_dplane_ctx *ctx, +- bool is_update) ++ bool is_update, bool async) + { + bool result = false; + +@@ -1481,13 +1481,12 @@ static bool rib_route_match_ctx(const struct route_entry *re, + /* We use an extra test for statics, and another for + * kernel routes. + */ +- if (re->type == ZEBRA_ROUTE_STATIC && ++ if (re->type == ZEBRA_ROUTE_STATIC && !async && + (re->distance != dplane_ctx_get_old_distance(ctx) || + re->tag != dplane_ctx_get_old_tag(ctx))) { + result = false; + } else if (re->type == ZEBRA_ROUTE_KERNEL && +- re->metric != +- dplane_ctx_get_old_metric(ctx)) { ++ re->metric != dplane_ctx_get_old_metric(ctx)) { + result = false; + } + } +@@ -1509,7 +1508,7 @@ static bool rib_route_match_ctx(const struct route_entry *re, + /* We use an extra test for statics, and another for + * kernel routes. + */ +- if (re->type == ZEBRA_ROUTE_STATIC && ++ if (re->type == ZEBRA_ROUTE_STATIC && !async && + (re->distance != dplane_ctx_get_distance(ctx) || + re->tag != dplane_ctx_get_tag(ctx))) { + result = false; +@@ -1973,13 +1972,13 @@ static void rib_process_result(struct zebra_dplane_ctx *ctx) + RNODE_FOREACH_RE(rn, rib) { + + if (re == NULL) { +- if (rib_route_match_ctx(rib, ctx, false)) ++ if (rib_route_match_ctx(rib, ctx, false, false)) + re = rib; + } + + /* Check for old route match */ + if (is_update && (old_re == NULL)) { +- if (rib_route_match_ctx(rib, ctx, true /*is_update*/)) ++ if (rib_route_match_ctx(rib, ctx, true, false)) + old_re = rib; + } + +@@ -2247,7 +2246,7 @@ static void rib_process_dplane_notify(struct zebra_dplane_ctx *ctx) + * info. + */ + RNODE_FOREACH_RE(rn, re) { +- if (rib_route_match_ctx(re, ctx, false /*!update*/)) ++ if (rib_route_match_ctx(re, ctx, false, true)) + break; + } + +-- +2.17.1 + diff --git a/src/sonic-frr/patch/0012-Ensure-ospf_apiclient_lsa_originate-cannot-accidently-write-into-stack.patch b/src/sonic-frr/patch/0012-Ensure-ospf_apiclient_lsa_originate-cannot-accidently-write-into-stack.patch deleted file mode 100644 index d46f13a3caf1..000000000000 --- a/src/sonic-frr/patch/0012-Ensure-ospf_apiclient_lsa_originate-cannot-accidently-write-into-stack.patch +++ /dev/null @@ -1,108 +0,0 @@ -From d8d77d3733bc299ed5dd7b44c4d464ba2bfed288 Mon Sep 17 00:00:00 2001 -From: Donald Sharp -Date: Wed, 20 Jul 2022 16:43:17 -0400 -Subject: [PATCH 1/3] ospfclient: Ensure ospf_apiclient_lsa_originate cannot - accidently write into stack - -Even though OSPF_MAX_LSA_SIZE is quite large and holds the upper bound -on what can be written into a lsa, let's add a small check to ensure -it is not possible to do a bad thing. - -This wins one of the long standing bug awards. 2003! - -Fixes: #11602 -Signed-off-by: Donald Sharp ---- - ospfclient/ospf_apiclient.c | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/ospfclient/ospf_apiclient.c b/ospfclient/ospf_apiclient.c -index 29f1c0807db..51c8a5b8c06 100644 ---- a/ospfclient/ospf_apiclient.c -+++ b/ospfclient/ospf_apiclient.c -@@ -447,6 +447,12 @@ int ospf_apiclient_lsa_originate(struct ospf_apiclient *oclient, - return OSPF_API_ILLEGALLSATYPE; - } - -+ if ((size_t)opaquelen > sizeof(buf) - sizeof(struct lsa_header)) { -+ fprintf(stderr, "opaquelen(%d) is larger than buf size %zu\n", -+ opaquelen, sizeof(buf)); -+ return OSPF_API_NOMEMORY; -+ } -+ - /* Make a new LSA from parameters */ - lsah = (struct lsa_header *)buf; - lsah->ls_age = 0; - -From 519929cdd47ac4d9f7f33e13922e1a063f69bb24 Mon Sep 17 00:00:00 2001 -From: Donald Sharp -Date: Wed, 20 Jul 2022 16:49:09 -0400 -Subject: [PATCH 2/3] isisd: Ensure rcap is freed in error case - -unpack_tlv_router_cap allocates memory that in the error -case is not being freed. - -Signed-off-by: Donald Sharp ---- - isisd/isis_tlvs.c | 8 ++++---- - 1 file changed, 4 insertions(+), 4 deletions(-) - -diff --git a/isisd/isis_tlvs.c b/isisd/isis_tlvs.c -index f1aae7caf10..dad271225b3 100644 ---- a/isisd/isis_tlvs.c -+++ b/isisd/isis_tlvs.c -@@ -2966,9 +2966,9 @@ static int pack_tlv_router_cap(const struct isis_router_cap *router_cap, - } - - static int unpack_tlv_router_cap(enum isis_tlv_context context, -- uint8_t tlv_type, uint8_t tlv_len, -- struct stream *s, struct sbuf *log, -- void *dest, int indent) -+ uint8_t tlv_type, uint8_t tlv_len, -+ struct stream *s, struct sbuf *log, void *dest, -+ int indent) - { - struct isis_tlvs *tlvs = dest; - struct isis_router_cap *rcap; -@@ -3013,7 +3013,7 @@ static int unpack_tlv_router_cap(enum isis_tlv_context context, - log, indent, - "WARNING: Router Capability subTLV length too large compared to expected size\n"); - stream_forward_getp(s, STREAM_READABLE(s)); -- -+ XFREE(MTYPE_ISIS_TLV, rcap); - return 0; - } - - -From 3c4821679f2362bcd38fcc7803f28a5210441ddb Mon Sep 17 00:00:00 2001 -From: Donald Sharp -Date: Thu, 21 Jul 2022 08:11:58 -0400 -Subject: [PATCH 3/3] bgpd: Make sure hdr length is at a minimum of what is - expected - -Ensure that if the capability length specified is enough data. - -Signed-off-by: Donald Sharp ---- - bgpd/bgp_packet.c | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/bgpd/bgp_packet.c b/bgpd/bgp_packet.c -index 7c92a8d9e83..bcd47e32d45 100644 ---- a/bgpd/bgp_packet.c -+++ b/bgpd/bgp_packet.c -@@ -2440,6 +2440,14 @@ static int bgp_capability_msg_parse(struct peer *peer, uint8_t *pnt, - "%s CAPABILITY has action: %d, code: %u, length %u", - peer->host, action, hdr->code, hdr->length); - -+ if (hdr->length < sizeof(struct capability_mp_data)) { -+ zlog_info( -+ "%s Capability structure is not properly filled out, expected at least %zu bytes but header length specified is %d", -+ peer->host, sizeof(struct capability_mp_data), -+ hdr->length); -+ return BGP_Stop; -+ } -+ - /* Capability length check. */ - if ((pnt + hdr->length + 3) > end) { - zlog_info("%s Capability length error", peer->host); diff --git a/src/sonic-frr/patch/0012-zebra-Rename-vrf_lookup_by_tableid-to-zebra_vrf_look.patch b/src/sonic-frr/patch/0012-zebra-Rename-vrf_lookup_by_tableid-to-zebra_vrf_look.patch new file mode 100644 index 000000000000..ca6517fbf655 --- /dev/null +++ b/src/sonic-frr/patch/0012-zebra-Rename-vrf_lookup_by_tableid-to-zebra_vrf_look.patch @@ -0,0 +1,147 @@ +From 2b9c7592a9857ddccc77b9d3f178e0c5bd5f19ed Mon Sep 17 00:00:00 2001 +From: Donald Sharp +Date: Wed, 26 Apr 2023 23:25:27 -0400 +Subject: [PATCH] zebra: Rename vrf_lookup_by_tableid to zebra_vrf_lookup.. + +Rename the vrf_lookup_by_id function to zebra_vrf_lookup_by_id +and move to zebra_vrf.c where it nominally belongs, as that +we need zebra specific data to find this vrf_id and as such +it does not belong in vrf.c + +Signed-off-by: Donald Sharp + +diff --git a/zebra/if_netlink.c b/zebra/if_netlink.c +index 81347b550a..4599121261 100644 +--- a/zebra/if_netlink.c ++++ b/zebra/if_netlink.c +@@ -342,7 +342,8 @@ static void netlink_vrf_change(struct nlmsghdr *h, struct rtattr *tb, + if (!vrf_lookup_by_id((vrf_id_t)ifi->ifi_index)) { + vrf_id_t exist_id; + +- exist_id = vrf_lookup_by_table(nl_table_id, ns_id); ++ exist_id = ++ zebra_vrf_lookup_by_table(nl_table_id, ns_id); + if (exist_id != VRF_DEFAULT) { + vrf = vrf_lookup_by_id(exist_id); + +diff --git a/zebra/rt_netlink.c b/zebra/rt_netlink.c +index 587045eac2..6b9b047858 100644 +--- a/zebra/rt_netlink.c ++++ b/zebra/rt_netlink.c +@@ -379,33 +379,6 @@ static inline int proto2zebra(int proto, int family, bool is_nexthop) + return proto; + } + +-/* +-Pending: create an efficient table_id (in a tree/hash) based lookup) +- */ +-vrf_id_t vrf_lookup_by_table(uint32_t table_id, ns_id_t ns_id) +-{ +- struct vrf *vrf; +- struct zebra_vrf *zvrf; +- +- RB_FOREACH (vrf, vrf_id_head, &vrfs_by_id) { +- zvrf = vrf->info; +- if (zvrf == NULL) +- continue; +- /* case vrf with netns : match the netnsid */ +- if (vrf_is_backend_netns()) { +- if (ns_id == zvrf_id(zvrf)) +- return zvrf_id(zvrf); +- } else { +- /* VRF is VRF_BACKEND_VRF_LITE */ +- if (zvrf->table_id != table_id) +- continue; +- return zvrf_id(zvrf); +- } +- } +- +- return VRF_DEFAULT; +-} +- + static uint32_t table_lookup_by_vrf(vrf_id_t vrf_id, ns_id_t ns_id) + { + struct vrf *vrf; +@@ -814,7 +787,7 @@ int netlink_route_change_read_unicast_internal(struct nlmsghdr *h, + table = rtm->rtm_table; + + /* Map to VRF */ +- vrf_id = vrf_lookup_by_table(table, ns_id); ++ vrf_id = zebra_vrf_lookup_by_table(table, ns_id); + } else { + /* With FPM, rtm_table contains vrf id, see netlink_route_multipath_msg_encode */ + if (tb[RTA_TABLE]) +@@ -1114,7 +1087,7 @@ static int netlink_route_change_read_multicast(struct nlmsghdr *h, + else + table = rtm->rtm_table; + +- vrf = vrf_lookup_by_table(table, ns_id); ++ vrf = zebra_vrf_lookup_by_table(table, ns_id); + + if (tb[RTA_IIF]) + iif = *(int *)RTA_DATA(tb[RTA_IIF]); +diff --git a/zebra/rt_netlink.h b/zebra/rt_netlink.h +index 8506367ae4..364aac0f6b 100644 +--- a/zebra/rt_netlink.h ++++ b/zebra/rt_netlink.h +@@ -102,7 +102,6 @@ extern int netlink_macfdb_read_specific_mac(struct zebra_ns *zns, + uint16_t vid); + extern int netlink_neigh_read_specific_ip(const struct ipaddr *ip, + struct interface *vlan_if); +-extern vrf_id_t vrf_lookup_by_table(uint32_t table_id, ns_id_t ns_id); + + struct nl_batch; + extern enum netlink_msg_status +diff --git a/zebra/zebra_vrf.c b/zebra/zebra_vrf.c +index be5e91495f..c59cb7c0a7 100644 +--- a/zebra/zebra_vrf.c ++++ b/zebra/zebra_vrf.c +@@ -389,6 +389,33 @@ struct zebra_vrf *zebra_vrf_alloc(struct vrf *vrf) + return zvrf; + } + ++/* ++Pending: create an efficient table_id (in a tree/hash) based lookup) ++ */ ++vrf_id_t zebra_vrf_lookup_by_table(uint32_t table_id, ns_id_t ns_id) ++{ ++ struct vrf *vrf; ++ struct zebra_vrf *zvrf; ++ ++ RB_FOREACH (vrf, vrf_id_head, &vrfs_by_id) { ++ zvrf = vrf->info; ++ if (zvrf == NULL) ++ continue; ++ /* case vrf with netns : match the netnsid */ ++ if (vrf_is_backend_netns()) { ++ if (ns_id == zvrf_id(zvrf)) ++ return zvrf_id(zvrf); ++ } else { ++ /* VRF is VRF_BACKEND_VRF_LITE */ ++ if (zvrf->table_id != table_id) ++ continue; ++ return zvrf_id(zvrf); ++ } ++ } ++ ++ return VRF_DEFAULT; ++} ++ + /* Lookup VRF by identifier. */ + struct zebra_vrf *zebra_vrf_lookup_by_id(vrf_id_t vrf_id) + { +diff --git a/zebra/zebra_vrf.h b/zebra/zebra_vrf.h +index 02e3c197c9..937e7fb144 100644 +--- a/zebra/zebra_vrf.h ++++ b/zebra/zebra_vrf.h +@@ -252,6 +252,7 @@ extern struct route_table *zebra_vrf_get_table_with_table_id(afi_t afi, + extern void zebra_vrf_update_all(struct zserv *client); + extern struct zebra_vrf *zebra_vrf_lookup_by_id(vrf_id_t vrf_id); + extern struct zebra_vrf *zebra_vrf_lookup_by_name(const char *); ++extern vrf_id_t zebra_vrf_lookup_by_table(uint32_t table_id, ns_id_t ns_id); + extern struct zebra_vrf *zebra_vrf_alloc(struct vrf *vrf); + extern struct route_table *zebra_vrf_table(afi_t, safi_t, vrf_id_t); + +-- +2.17.1 + diff --git a/src/sonic-frr/patch/0013-zebra-Move-protodown_r_bit-to-a-better-spot.patch b/src/sonic-frr/patch/0013-zebra-Move-protodown_r_bit-to-a-better-spot.patch new file mode 100644 index 000000000000..cd88419fcbd6 --- /dev/null +++ b/src/sonic-frr/patch/0013-zebra-Move-protodown_r_bit-to-a-better-spot.patch @@ -0,0 +1,181 @@ +From c43808ca6daa59d533e14790ffc7f2e11b508924 Mon Sep 17 00:00:00 2001 +From: Donald Sharp +Date: Thu, 27 Apr 2023 07:37:58 -0400 +Subject: [PATCH] zebra: Move protodown_r_bit to a better spot + +Since we are moving some code handling out of the dataplane +and into zebra proper, lets move the protodown r bit as well. + +Signed-off-by: Donald Sharp + +diff --git a/zebra/if_netlink.c b/zebra/if_netlink.c +index 4599121261..95889e22fd 100644 +--- a/zebra/if_netlink.c ++++ b/zebra/if_netlink.c +@@ -78,7 +78,6 @@ + #include "zebra/zebra_trace.h" + + extern struct zebra_privs_t zserv_privs; +-uint8_t frr_protodown_r_bit = FRR_PROTODOWN_REASON_DEFAULT_BIT; + + /* Note: on netlink systems, there should be a 1-to-1 mapping between interface + names and ifindex values. */ +@@ -819,9 +818,7 @@ static int netlink_bridge_interface(struct nlmsghdr *h, int len, ns_id_t ns_id, + + static bool is_if_protodown_reason_only_frr(uint32_t rc_bitfield) + { +- /* This shouldn't be possible */ +- assert(frr_protodown_r_bit < 32); +- return (rc_bitfield == (((uint32_t)1) << frr_protodown_r_bit)); ++ return (rc_bitfield == (((uint32_t)1) << if_netlink_get_frr_protodown_r_bit())); + } + + /* +@@ -2247,9 +2244,10 @@ ssize_t netlink_intf_msg_encode(uint16_t cmd, + return -1; + + nl_attr_put32(&req->n, buflen, IFLA_PROTO_DOWN_REASON_MASK, +- (1 << frr_protodown_r_bit)); ++ (1 << if_netlink_get_frr_protodown_r_bit())); + nl_attr_put32(&req->n, buflen, IFLA_PROTO_DOWN_REASON_VALUE, +- ((int)pd_reason_val) << frr_protodown_r_bit); ++ ((int)pd_reason_val) ++ << if_netlink_get_frr_protodown_r_bit()); + + nl_attr_nest_end(&req->n, nest_protodown_reason); + +@@ -2274,37 +2272,6 @@ void interface_list(struct zebra_ns *zns) + interface_addr_lookup_netlink(zns); + } + +-void if_netlink_set_frr_protodown_r_bit(uint8_t bit) +-{ +- if (IS_ZEBRA_DEBUG_KERNEL) +- zlog_debug( +- "Protodown reason bit index changed: bit-index %u -> bit-index %u", +- frr_protodown_r_bit, bit); +- +- frr_protodown_r_bit = bit; +-} +- +-void if_netlink_unset_frr_protodown_r_bit(void) +-{ +- if (IS_ZEBRA_DEBUG_KERNEL) +- zlog_debug( +- "Protodown reason bit index changed: bit-index %u -> bit-index %u", +- frr_protodown_r_bit, FRR_PROTODOWN_REASON_DEFAULT_BIT); +- +- frr_protodown_r_bit = FRR_PROTODOWN_REASON_DEFAULT_BIT; +-} +- +- +-bool if_netlink_frr_protodown_r_bit_is_set(void) +-{ +- return (frr_protodown_r_bit != FRR_PROTODOWN_REASON_DEFAULT_BIT); +-} +- +-uint8_t if_netlink_get_frr_protodown_r_bit(void) +-{ +- return frr_protodown_r_bit; +-} +- + /** + * netlink_request_tunneldump() - Request all tunnels from the linux kernel + * +diff --git a/zebra/if_netlink.h b/zebra/if_netlink.h +index 21ae1713be..f5a170a609 100644 +--- a/zebra/if_netlink.h ++++ b/zebra/if_netlink.h +@@ -54,17 +54,6 @@ extern int netlink_tunneldump_read(struct zebra_ns *zns); + extern enum netlink_msg_status + netlink_put_intf_update_msg(struct nl_batch *bth, struct zebra_dplane_ctx *ctx); + +-#define FRR_PROTODOWN_REASON_DEFAULT_BIT 7 +-/* Protodown bit setter/getter +- * +- * Allow users to change the bit if it conflicts with another +- * on their system. +- */ +-extern void if_netlink_set_frr_protodown_r_bit(uint8_t bit); +-extern void if_netlink_unset_frr_protodown_r_bit(void); +-extern bool if_netlink_frr_protodown_r_bit_is_set(void); +-extern uint8_t if_netlink_get_frr_protodown_r_bit(void); +- + #ifdef __cplusplus + } + #endif +diff --git a/zebra/zebra_router.c b/zebra/zebra_router.c +index a9a7b66ce7..12689804ea 100644 +--- a/zebra/zebra_router.c ++++ b/zebra/zebra_router.c +@@ -280,6 +280,8 @@ void zebra_router_init(bool asic_offload, bool notify_on_ack) + { + zrouter.sequence_num = 0; + ++ zrouter.protodown_r_bit = FRR_PROTODOWN_REASON_DEFAULT_BIT; ++ + zrouter.allow_delete = false; + + zrouter.packets_to_process = ZEBRA_ZAPI_PACKETS_TO_PROCESS; +diff --git a/zebra/zebra_router.h b/zebra/zebra_router.h +index e0ef86f082..61bde4ac2a 100644 +--- a/zebra/zebra_router.h ++++ b/zebra/zebra_router.h +@@ -244,6 +244,8 @@ struct zebra_router { + + /* Should we allow non FRR processes to delete our routes */ + bool allow_delete; ++ ++ uint8_t protodown_r_bit; + }; + + #define GRACEFUL_RESTART_TIME 60 +@@ -302,6 +304,32 @@ static inline bool zebra_router_in_shutdown(void) + return atomic_load_explicit(&zrouter.in_shutdown, memory_order_relaxed); + } + ++#define FRR_PROTODOWN_REASON_DEFAULT_BIT 7 ++/* Protodown bit setter/getter ++ * ++ * Allow users to change the bit if it conflicts with another ++ * on their system. ++ */ ++static inline void if_netlink_set_frr_protodown_r_bit(uint8_t bit) ++{ ++ zrouter.protodown_r_bit = bit; ++} ++ ++static inline void if_netlink_unset_frr_protodown_r_bit(void) ++{ ++ zrouter.protodown_r_bit = FRR_PROTODOWN_REASON_DEFAULT_BIT; ++} ++ ++static inline bool if_netlink_frr_protodown_r_bit_is_set(void) ++{ ++ return (zrouter.protodown_r_bit != FRR_PROTODOWN_REASON_DEFAULT_BIT); ++} ++ ++static inline uint8_t if_netlink_get_frr_protodown_r_bit(void) ++{ ++ return zrouter.protodown_r_bit; ++} ++ + /* zebra_northbound.c */ + extern const struct frr_yang_module_info frr_zebra_info; + +diff --git a/zebra/zebra_vrf.c b/zebra/zebra_vrf.c +index c59cb7c0a7..9c5b38b96b 100644 +--- a/zebra/zebra_vrf.c ++++ b/zebra/zebra_vrf.c +@@ -390,7 +390,7 @@ struct zebra_vrf *zebra_vrf_alloc(struct vrf *vrf) + } + + /* +-Pending: create an efficient table_id (in a tree/hash) based lookup) ++ * Pending: create an efficient table_id (in a tree/hash) based lookup) + */ + vrf_id_t zebra_vrf_lookup_by_table(uint32_t table_id, ns_id_t ns_id) + { +-- +2.17.1 + diff --git a/src/sonic-frr/patch/0013-zebra-fix-dplane-fpm-nl-to-allow-for-fast-configuration.patch b/src/sonic-frr/patch/0013-zebra-fix-dplane-fpm-nl-to-allow-for-fast-configuration.patch deleted file mode 100644 index 9a412d24ee86..000000000000 --- a/src/sonic-frr/patch/0013-zebra-fix-dplane-fpm-nl-to-allow-for-fast-configuration.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 551fa8c3549e24020dfce33d06ade4a14f72abfe Mon Sep 17 00:00:00 2001 -From: Donald Sharp -Date: Mon, 14 Nov 2022 08:28:45 -0500 -Subject: [PATCH] zebra: Fix dplane_fpm_nl to allow for fast configuration - -If you have this order in your configuration file: - -no fpm use-next-hop-groups -fpm address 127.0.0.1 - -the dplane code was using the same event thread t_event and the second -add event in the code was going, you already have an event scheduled -and as such the second event does not overwrite it. Leaving -no code to actually start the whole processing. There are probably -other cli iterations that will cause this fun as well, but I'm -not going to spend the time sussing them out at the moment. - -Fixes: #12314 -Signed-off-by: Donald Sharp ---- - zebra/dplane_fpm_nl.c | 7 +++++-- - 1 file changed, 5 insertions(+), 2 deletions(-) - -diff --git a/zebra/dplane_fpm_nl.c b/zebra/dplane_fpm_nl.c -index 7383c982baa..c5e1c113cb0 100644 ---- a/zebra/dplane_fpm_nl.c -+++ b/zebra/dplane_fpm_nl.c -@@ -98,6 +98,7 @@ struct fpm_nl_ctx { - struct thread *t_read; - struct thread *t_write; - struct thread *t_event; -+ struct thread *t_nhg; - struct thread *t_dequeue; - - /* zebra events. */ -@@ -271,7 +272,7 @@ DEFUN(fpm_use_nhg, fpm_use_nhg_cmd, - return CMD_SUCCESS; - - thread_add_event(gfnc->fthread->master, fpm_process_event, gfnc, -- FNE_TOGGLE_NHG, &gfnc->t_event); -+ FNE_TOGGLE_NHG, &gfnc->t_nhg); - - return CMD_SUCCESS; - } -@@ -287,7 +288,7 @@ DEFUN(no_fpm_use_nhg, no_fpm_use_nhg_cmd, - return CMD_SUCCESS; - - thread_add_event(gfnc->fthread->master, fpm_process_event, gfnc, -- FNE_TOGGLE_NHG, &gfnc->t_event); -+ FNE_TOGGLE_NHG, &gfnc->t_nhg); - - return CMD_SUCCESS; - } -@@ -1367,6 +1368,8 @@ static int fpm_nl_finish_early(struct fpm_nl_ctx *fnc) - THREAD_OFF(fnc->t_ribwalk); - THREAD_OFF(fnc->t_rmacreset); - THREAD_OFF(fnc->t_rmacwalk); -+ THREAD_OFF(fnc->t_event); -+ THREAD_OFF(fnc->t_nhg); - thread_cancel_async(fnc->fthread->master, &fnc->t_read, NULL); - thread_cancel_async(fnc->fthread->master, &fnc->t_write, NULL); - thread_cancel_async(fnc->fthread->master, &fnc->t_connect, NULL); diff --git a/src/sonic-frr/patch/0014-bgpd-Allow-network-XXX-to-work-with-bgp-suppress-fib.patch b/src/sonic-frr/patch/0014-bgpd-Allow-network-XXX-to-work-with-bgp-suppress-fib.patch deleted file mode 100644 index 60f1aa4cd357..000000000000 --- a/src/sonic-frr/patch/0014-bgpd-Allow-network-XXX-to-work-with-bgp-suppress-fib.patch +++ /dev/null @@ -1,190 +0,0 @@ -From 2ce65073a1c2c1a225488287eb886a76149db0a4 Mon Sep 17 00:00:00 2001 -From: Donald Sharp -Date: Wed, 12 Oct 2022 14:53:21 -0400 -Subject: [PATCH 04/11] bgpd: Allow `network XXX` to work with bgp - suppress-fib-pending - -When bgp is using `bgp suppress-fib-pending` and the end -operator is using network statements, bgp was not sending -the network'ed prefix'es to it's peers. Fix this. - -Also update the test cases for bgp_suppress_fib to test -this new corner case( I am sure that there are going to -be others that will need to be added ). - -Fixes: #12112 -Signed-off-by: Donald Sharp -(cherry picked from commit 4801fc4670020406fc609dedabc7482d88e3b656) ---- - bgpd/bgp_route.h | 20 ++++++++++++++-- - .../bgp_suppress_fib/r1/bgp_ipv4_allowas.json | 2 +- - .../bgp_suppress_fib/r2/bgp_ipv4_allowas.json | 2 +- - tests/topotests/bgp_suppress_fib/r2/bgpd.conf | 2 ++ - .../topotests/bgp_suppress_fib/r2/zebra.conf | 3 +++ - .../bgp_suppress_fib/r3/v4_route3.json | 23 +++++++++++++++++++ - .../bgp_suppress_fib/test_bgp_suppress_fib.py | 14 ++++++++--- - 7 files changed, 59 insertions(+), 7 deletions(-) - create mode 100644 tests/topotests/bgp_suppress_fib/r3/v4_route3.json - -diff --git a/bgpd/bgp_route.h b/bgpd/bgp_route.h -index a8ec2dc90..003a6cb79 100644 ---- a/bgpd/bgp_route.h -+++ b/bgpd/bgp_route.h -@@ -595,19 +595,35 @@ static inline bool bgp_check_advertise(struct bgp *bgp, struct bgp_dest *dest) - */ - static inline bool bgp_check_withdrawal(struct bgp *bgp, struct bgp_dest *dest) - { -- struct bgp_path_info *pi; -+ struct bgp_path_info *pi, *selected = NULL; - - if (!BGP_SUPPRESS_FIB_ENABLED(bgp)) - return false; - - for (pi = bgp_dest_get_bgp_path_info(dest); pi; pi = pi->next) { -- if (CHECK_FLAG(pi->flags, BGP_PATH_SELECTED)) -+ if (CHECK_FLAG(pi->flags, BGP_PATH_SELECTED)) { -+ selected = pi; - continue; -+ } - - if (pi->sub_type != BGP_ROUTE_NORMAL) - return true; - } - -+ /* -+ * pi is selected and bgp is dealing with a static route -+ * ( ie a network statement of some sort ). FIB installed -+ * is irrelevant -+ * -+ * I am not sure what the above for loop is wanted in this -+ * manner at this point. But I do know that if I have -+ * a static route that is selected and it's the one -+ * being checked for should I withdrawal we do not -+ * want to withdraw the route on installation :) -+ */ -+ if (selected && selected->sub_type == BGP_ROUTE_STATIC) -+ return false; -+ - if (CHECK_FLAG(dest->flags, BGP_NODE_FIB_INSTALLED)) - return false; - -diff --git a/tests/topotests/bgp_suppress_fib/r1/bgp_ipv4_allowas.json b/tests/topotests/bgp_suppress_fib/r1/bgp_ipv4_allowas.json -index bc4d0f479..1a5ede276 100644 ---- a/tests/topotests/bgp_suppress_fib/r1/bgp_ipv4_allowas.json -+++ b/tests/topotests/bgp_suppress_fib/r1/bgp_ipv4_allowas.json -@@ -32,7 +32,7 @@ - ], - "peer":{ - "peerId":"10.0.0.2", -- "routerId":"10.0.0.9", -+ "routerId":"60.0.0.1", - "type":"external" - } - } -diff --git a/tests/topotests/bgp_suppress_fib/r2/bgp_ipv4_allowas.json b/tests/topotests/bgp_suppress_fib/r2/bgp_ipv4_allowas.json -index 16561ce83..4a35abfd6 100644 ---- a/tests/topotests/bgp_suppress_fib/r2/bgp_ipv4_allowas.json -+++ b/tests/topotests/bgp_suppress_fib/r2/bgp_ipv4_allowas.json -@@ -61,7 +61,7 @@ - ], - "peer":{ - "peerId":"0.0.0.0", -- "routerId":"10.0.0.9" -+ "routerId":"60.0.0.1" - } - } - ] -diff --git a/tests/topotests/bgp_suppress_fib/r2/bgpd.conf b/tests/topotests/bgp_suppress_fib/r2/bgpd.conf -index ebef2012a..010e86aad 100644 ---- a/tests/topotests/bgp_suppress_fib/r2/bgpd.conf -+++ b/tests/topotests/bgp_suppress_fib/r2/bgpd.conf -@@ -7,3 +7,5 @@ router bgp 2 - bgp suppress-fib-pending - neighbor 10.0.0.1 remote-as 1 - neighbor 10.0.0.10 remote-as 3 -+ address-family ipv4 uni -+ network 60.0.0.0/24 -\ No newline at end of file -diff --git a/tests/topotests/bgp_suppress_fib/r2/zebra.conf b/tests/topotests/bgp_suppress_fib/r2/zebra.conf -index 443fffc70..6e8bce045 100644 ---- a/tests/topotests/bgp_suppress_fib/r2/zebra.conf -+++ b/tests/topotests/bgp_suppress_fib/r2/zebra.conf -@@ -1,4 +1,7 @@ - ! -+interface lo -+ ip address 60.0.0.1/24 -+! - interface r2-eth0 - ip address 10.0.0.2/30 - ! -diff --git a/tests/topotests/bgp_suppress_fib/r3/v4_route3.json b/tests/topotests/bgp_suppress_fib/r3/v4_route3.json -new file mode 100644 -index 000000000..ab8c3aa5e ---- /dev/null -+++ b/tests/topotests/bgp_suppress_fib/r3/v4_route3.json -@@ -0,0 +1,23 @@ -+{ -+ "60.0.0.0/24":[ -+ { -+ "prefix":"60.0.0.0/24", -+ "protocol":"bgp", -+ "selected":true, -+ "destSelected":true, -+ "distance":20, -+ "metric":0, -+ "installed":true, -+ "table":254, -+ "nexthops":[ -+ { -+ "fib":true, -+ "ip":"10.0.0.9", -+ "afi":"ipv4", -+ "interfaceName":"r3-eth0", -+ "active":true -+ } -+ ] -+ } -+ ] -+} -diff --git a/tests/topotests/bgp_suppress_fib/test_bgp_suppress_fib.py b/tests/topotests/bgp_suppress_fib/test_bgp_suppress_fib.py -index 2c87d9d7b..96a294cae 100644 ---- a/tests/topotests/bgp_suppress_fib/test_bgp_suppress_fib.py -+++ b/tests/topotests/bgp_suppress_fib/test_bgp_suppress_fib.py -@@ -84,8 +84,6 @@ def test_bgp_route(): - - r3 = tgen.gears["r3"] - -- sleep(5) -- - json_file = "{}/r3/v4_route.json".format(CWD) - expected = json.loads(open(json_file).read()) - -@@ -95,7 +93,7 @@ def test_bgp_route(): - "show ip route 40.0.0.0 json", - expected, - ) -- _, result = topotest.run_and_expect(test_func, None, count=2, wait=0.5) -+ _, result = topotest.run_and_expect(test_func, None, count=20, wait=0.5) - assertmsg = '"r3" JSON output mismatches' - assert result is None, assertmsg - -@@ -112,6 +110,16 @@ def test_bgp_route(): - assertmsg = '"r3" JSON output mismatches' - assert result is None, assertmsg - -+ json_file = "{}/r3/v4_route3.json".format(CWD) -+ expected = json.loads(open(json_file).read()) -+ -+ test_func = partial( -+ topotest.router_json_cmp, -+ r3, -+ "show ip route 10.0.0.3 json", -+ expected, -+ ) -+ _, result = topotest.run_and_expect(test_func, None, count=3, wait=0.5) - - def test_bgp_better_admin_won(): - "A better Admin distance protocol may come along and knock us out" --- -2.30.2 - diff --git a/src/sonic-frr/patch/0014-zebra-Remove-unused-dplane_intf_delete.patch b/src/sonic-frr/patch/0014-zebra-Remove-unused-dplane_intf_delete.patch new file mode 100644 index 000000000000..756e0cf97419 --- /dev/null +++ b/src/sonic-frr/patch/0014-zebra-Remove-unused-dplane_intf_delete.patch @@ -0,0 +1,48 @@ +From 88f7441f56bf61008a52adda97525ffb20f9543d Mon Sep 17 00:00:00 2001 +From: Donald Sharp +Date: Fri, 14 Apr 2023 07:43:19 -0400 +Subject: [PATCH] zebra: Remove unused dplane_intf_delete + +There is no need for this functionality and it is +not used. + +Signed-off-by: Donald Sharp + +diff --git a/zebra/zebra_dplane.c b/zebra/zebra_dplane.c +index 4927af5625..a6c08f7371 100644 +--- a/zebra/zebra_dplane.c ++++ b/zebra/zebra_dplane.c +@@ -4648,18 +4648,6 @@ enum zebra_dplane_result dplane_intf_update(const struct interface *ifp) + return ret; + } + +-/* +- * Enqueue a interface delete for the dataplane. +- */ +-enum zebra_dplane_result dplane_intf_delete(const struct interface *ifp) +-{ +- enum zebra_dplane_result ret = ZEBRA_DPLANE_REQUEST_FAILURE; +- +- if (ifp) +- ret = dplane_intf_update_internal(ifp, DPLANE_OP_INTF_DELETE); +- return ret; +-} +- + /* + * Enqueue vxlan/evpn mac add (or update). + */ +diff --git a/zebra/zebra_dplane.h b/zebra/zebra_dplane.h +index ae13243a16..9ef0afd3a8 100644 +--- a/zebra/zebra_dplane.h ++++ b/zebra/zebra_dplane.h +@@ -758,7 +758,6 @@ enum zebra_dplane_result dplane_intf_addr_unset(const struct interface *ifp, + */ + enum zebra_dplane_result dplane_intf_add(const struct interface *ifp); + enum zebra_dplane_result dplane_intf_update(const struct interface *ifp); +-enum zebra_dplane_result dplane_intf_delete(const struct interface *ifp); + + /* + * Enqueue tc link changes for the dataplane. +-- +2.17.1 + diff --git a/src/sonic-frr/patch/0015-zebra-Remove-unused-add-variable.patch b/src/sonic-frr/patch/0015-zebra-Remove-unused-add-variable.patch new file mode 100644 index 000000000000..dc263d3d94c0 --- /dev/null +++ b/src/sonic-frr/patch/0015-zebra-Remove-unused-add-variable.patch @@ -0,0 +1,53 @@ +From 4cc6c7af6f7c72ddf18ab562f4e2c2b25e32f1b5 Mon Sep 17 00:00:00 2001 +From: Donald Sharp +Date: Sat, 15 Apr 2023 08:04:51 -0400 +Subject: [PATCH] zebra: Remove unused add variable + +Function was not using the add variable. Remove it. + +Signed-off-by: Donald Sharp + +diff --git a/zebra/if_netlink.c b/zebra/if_netlink.c +index 95889e22fd..e54fb09022 100644 +--- a/zebra/if_netlink.c ++++ b/zebra/if_netlink.c +@@ -670,7 +670,7 @@ static void netlink_interface_update_l2info(struct interface *ifp, + struct zebra_l2info_bridge bridge_info; + + netlink_extract_bridge_info(link_data, &bridge_info); +- zebra_l2_bridge_add_update(ifp, &bridge_info, add); ++ zebra_l2_bridge_add_update(ifp, &bridge_info); + } else if (IS_ZEBRA_IF_VLAN(ifp)) { + struct zebra_l2info_vlan vlan_info; + +diff --git a/zebra/zebra_l2.c b/zebra/zebra_l2.c +index 8a9f3dffe3..07bbc6e3bc 100644 +--- a/zebra/zebra_l2.c ++++ b/zebra/zebra_l2.c +@@ -258,8 +258,7 @@ void zebra_l2if_update_bond(struct interface *ifp, bool add) + * map slaves (if any) to the bridge. + */ + void zebra_l2_bridge_add_update(struct interface *ifp, +- struct zebra_l2info_bridge *bridge_info, +- int add) ++ struct zebra_l2info_bridge *bridge_info) + { + struct zebra_if *zif; + +diff --git a/zebra/zebra_l2.h b/zebra/zebra_l2.h +index 1c3e98158d..8fef008f52 100644 +--- a/zebra/zebra_l2.h ++++ b/zebra/zebra_l2.h +@@ -109,8 +109,7 @@ extern void zebra_l2_map_slave_to_bridge(struct zebra_l2info_brslave *br_slave, + extern void + zebra_l2_unmap_slave_from_bridge(struct zebra_l2info_brslave *br_slave); + extern void zebra_l2_bridge_add_update(struct interface *ifp, +- struct zebra_l2info_bridge *bridge_info, +- int add); ++ struct zebra_l2info_bridge *bridge_info); + extern void zebra_l2_bridge_del(struct interface *ifp); + extern void zebra_l2_vlanif_update(struct interface *ifp, + struct zebra_l2info_vlan *vlan_info); +-- +2.17.1 + diff --git a/src/sonic-frr/patch/0015-zebra-Return-statements-do-not-use-paranthesis.patch b/src/sonic-frr/patch/0015-zebra-Return-statements-do-not-use-paranthesis.patch deleted file mode 100755 index 592af9308c07..000000000000 --- a/src/sonic-frr/patch/0015-zebra-Return-statements-do-not-use-paranthesis.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 07a41dcd82ff41b406d0011554d70ce79da68df5 Mon Sep 17 00:00:00 2001 -From: Donald Sharp -Date: Wed, 5 Oct 2022 10:26:07 -0400 -Subject: [PATCH 1/8] zebra: Return statements do not use paranthesis - -Signed-off-by: Donald Sharp ---- - zebra/zebra_rib.c | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - -diff --git a/zebra/zebra_rib.c b/zebra/zebra_rib.c -index cf1baf077..472e48925 100644 ---- a/zebra/zebra_rib.c -+++ b/zebra/zebra_rib.c -@@ -1403,8 +1403,7 @@ static bool rib_route_match_ctx(const struct route_entry *re, - } - - done: -- -- return (result); -+ return result; - } - - static void zebra_rib_fixup_system(struct route_node *rn) --- -2.30.2 - diff --git a/src/sonic-frr/patch/0016-zebra-Add-zrouter.asic_notification_nexthop_control.patch b/src/sonic-frr/patch/0016-zebra-Add-zrouter.asic_notification_nexthop_control.patch deleted file mode 100755 index 78e17849cad0..000000000000 --- a/src/sonic-frr/patch/0016-zebra-Add-zrouter.asic_notification_nexthop_control.patch +++ /dev/null @@ -1,205 +0,0 @@ -From 01e267d98c63ee4464f96fead11dda9ee0ad911b Mon Sep 17 00:00:00 2001 -From: Donald Sharp -Date: Wed, 5 Oct 2022 10:04:11 -0400 -Subject: [PATCH 2/8] zebra: Add `zrouter.asic_notification_nexthop_control` - -Volta submitted notification changes for the dplane that had a -special use case for their system. Volta is no more, the code -is not being actively developed and from talking with ex-Volta -employees there is no current plans to even maintain this code. -Wrap the special handling of nexthops that their asic-dataplane -did in a bit of code to isolate it and allow for future removal, -as that I do not actually believe anyone else is using this code. -Add a CPP_NOTICE several years into the future that will tell us -to remove the code. If someone starts using it then they will -have to notice this variable to set it and hopefully they will -see my CPP_NOTICE to come talk to us. If this is being used then -we can just remove this wrapper. - -Signed-off-by: Donald Sharp ---- - zebra/zebra_rib.c | 95 +++++++++++++++++++++++++------------------- - zebra/zebra_router.c | 11 +++++ - zebra/zebra_router.h | 8 ++++ - zebra/zebra_vty.c | 9 +++++ - 4 files changed, 83 insertions(+), 40 deletions(-) - -diff --git a/zebra/zebra_rib.c b/zebra/zebra_rib.c -index 472e48925..abd6e07f9 100644 ---- a/zebra/zebra_rib.c -+++ b/zebra/zebra_rib.c -@@ -2215,55 +2215,70 @@ static void rib_process_dplane_notify(struct zebra_dplane_ctx *ctx) - /* Various fib transitions: changed nexthops; from installed to - * not-installed; or not-installed to installed. - */ -- if (start_count > 0 && end_count > 0) { -- if (debug_p) -- zlog_debug( -- "%s(%u:%u):%pRN applied nexthop changes from dplane notification", -- VRF_LOGNAME(vrf), dplane_ctx_get_vrf(ctx), -- dplane_ctx_get_table(ctx), rn); -+ if (zrouter.asic_notification_nexthop_control) { -+ if (start_count > 0 && end_count > 0) { -+ if (debug_p) -+ zlog_debug( -+ "%s(%u:%u):%pRN applied nexthop changes from dplane notification", -+ VRF_LOGNAME(vrf), -+ dplane_ctx_get_vrf(ctx), -+ dplane_ctx_get_table(ctx), rn); - -- /* Changed nexthops - update kernel/others */ -- dplane_route_notif_update(rn, re, -- DPLANE_OP_ROUTE_UPDATE, ctx); -+ /* Changed nexthops - update kernel/others */ -+ dplane_route_notif_update(rn, re, -+ DPLANE_OP_ROUTE_UPDATE, ctx); - -- } else if (start_count == 0 && end_count > 0) { -- if (debug_p) -- zlog_debug( -- "%s(%u:%u):%pRN installed transition from dplane notification", -- VRF_LOGNAME(vrf), dplane_ctx_get_vrf(ctx), -- dplane_ctx_get_table(ctx), rn); -+ } else if (start_count == 0 && end_count > 0) { -+ if (debug_p) -+ zlog_debug( -+ "%s(%u:%u):%pRN installed transition from dplane notification", -+ VRF_LOGNAME(vrf), -+ dplane_ctx_get_vrf(ctx), -+ dplane_ctx_get_table(ctx), rn); - -- /* We expect this to be the selected route, so we want -- * to tell others about this transition. -- */ -- SET_FLAG(re->status, ROUTE_ENTRY_INSTALLED); -+ /* We expect this to be the selected route, so we want -+ * to tell others about this transition. -+ */ -+ SET_FLAG(re->status, ROUTE_ENTRY_INSTALLED); - -- /* Changed nexthops - update kernel/others */ -- dplane_route_notif_update(rn, re, DPLANE_OP_ROUTE_UPDATE, ctx); -+ /* Changed nexthops - update kernel/others */ -+ dplane_route_notif_update(rn, re, -+ DPLANE_OP_ROUTE_UPDATE, ctx); - -- /* Redistribute, lsp, and nht update */ -- redistribute_update(rn, re, NULL); -+ /* Redistribute, lsp, and nht update */ -+ redistribute_update(rn, re, NULL); - -- } else if (start_count > 0 && end_count == 0) { -- if (debug_p) -- zlog_debug( -- "%s(%u:%u):%pRN un-installed transition from dplane notification", -- VRF_LOGNAME(vrf), dplane_ctx_get_vrf(ctx), -- dplane_ctx_get_table(ctx), rn); -+ } else if (start_count > 0 && end_count == 0) { -+ if (debug_p) -+ zlog_debug( -+ "%s(%u:%u):%pRN un-installed transition from dplane notification", -+ VRF_LOGNAME(vrf), -+ dplane_ctx_get_vrf(ctx), -+ dplane_ctx_get_table(ctx), rn); - -- /* Transition from _something_ installed to _nothing_ -- * installed. -- */ -- /* We expect this to be the selected route, so we want -- * to tell others about this transistion. -- */ -- UNSET_FLAG(re->status, ROUTE_ENTRY_INSTALLED); -+ /* Transition from _something_ installed to _nothing_ -+ * installed. -+ */ -+ /* We expect this to be the selected route, so we want -+ * to tell others about this transistion. -+ */ -+ UNSET_FLAG(re->status, ROUTE_ENTRY_INSTALLED); - -- /* Changed nexthops - update kernel/others */ -- dplane_route_notif_update(rn, re, DPLANE_OP_ROUTE_DELETE, ctx); -+ /* Changed nexthops - update kernel/others */ -+ dplane_route_notif_update(rn, re, -+ DPLANE_OP_ROUTE_DELETE, ctx); - -- /* Redistribute, lsp, and nht update */ -- redistribute_delete(rn, re, NULL); -+ /* Redistribute, lsp, and nht update */ -+ redistribute_delete(rn, re, NULL); -+ } -+ } -+ -+ if (!zebra_router_notify_on_ack()) { -+ if (CHECK_FLAG(re->flags, ZEBRA_FLAG_OFFLOADED)) -+ zsend_route_notify_owner_ctx(ctx, ZAPI_ROUTE_INSTALLED); -+ if (CHECK_FLAG(re->flags, ZEBRA_FLAG_OFFLOAD_FAILED)) -+ zsend_route_notify_owner_ctx(ctx, -+ ZAPI_ROUTE_FAIL_INSTALL); - } - - /* Make any changes visible for lsp and nexthop-tracking processing */ -diff --git a/zebra/zebra_router.c b/zebra/zebra_router.c -index 92a3b9424..d47517bbb 100644 ---- a/zebra/zebra_router.c -+++ b/zebra/zebra_router.c -@@ -304,6 +304,17 @@ void zebra_router_init(bool asic_offload, bool notify_on_ack) - zrouter.asic_offloaded = asic_offload; - zrouter.notify_on_ack = notify_on_ack; - -+ /* -+ * If you start using asic_notification_nexthop_control -+ * come talk to the FRR community about what you are doing -+ * We would like to know. -+ */ -+#if CONFDATE > 20251231 -+ CPP_NOTICE( -+ "Remove zrouter.asic_notification_nexthop_control as that it's not being maintained or used"); -+#endif -+ zrouter.asic_notification_nexthop_control = false; -+ - #ifdef HAVE_SCRIPTING - zebra_script_init(); - #endif -diff --git a/zebra/zebra_router.h b/zebra/zebra_router.h -index c0eab9cd6..583bd0038 100644 ---- a/zebra/zebra_router.h -+++ b/zebra/zebra_router.h -@@ -209,6 +209,14 @@ struct zebra_router { - */ - bool asic_offloaded; - bool notify_on_ack; -+ -+ /* -+ * If the asic is notifying us about successful nexthop -+ * allocation/control. Some developers have made their -+ * asic take control of how many nexthops/ecmp they can -+ * have and will report what is successfull or not -+ */ -+ bool asic_notification_nexthop_control; - }; - - #define GRACEFUL_RESTART_TIME 60 -diff --git a/zebra/zebra_vty.c b/zebra/zebra_vty.c -index 0a3d676a9..a7eb09df0 100644 ---- a/zebra/zebra_vty.c -+++ b/zebra/zebra_vty.c -@@ -3972,6 +3972,15 @@ DEFUN (show_zebra, - if (zrouter.asic_offloaded) - vty_out(vty, "Asic Offload is being used\n"); - -+ /* -+ * Do not display this unless someone is actually using it -+ * -+ * Why this distinction? I think this is effectively dead code -+ * and should not be exposed. Maybe someone proves me wrong. -+ */ -+ if (zrouter.asic_notification_nexthop_control) -+ vty_out(vty, "ASIC offload and nexthop control is being used"); -+ - vty_out(vty, - " Route Route Neighbor LSP LSP\n"); - vty_out(vty, --- -2.30.2 - diff --git a/src/sonic-frr/patch/0016-zebra-Remove-duplicate-function-for-netlink-interfac.patch b/src/sonic-frr/patch/0016-zebra-Remove-duplicate-function-for-netlink-interfac.patch new file mode 100644 index 000000000000..8f13d20f0052 --- /dev/null +++ b/src/sonic-frr/patch/0016-zebra-Remove-duplicate-function-for-netlink-interfac.patch @@ -0,0 +1,301 @@ +From e12ffa6871d33712b03fc2ca28de278913e95bce Mon Sep 17 00:00:00 2001 +From: Donald Sharp +Date: Thu, 13 Apr 2023 16:43:27 -0400 +Subject: [PATCH] zebra: Remove duplicate function for netlink interface + changes + +Turns out FRR has 2 functions one specifically for startup +and one for normal day to day operations. There were only +a couple of minor differences from what I could tell, and +where they were different the after startup functionality should +have been updated too. I cannot figure out why we have 2. + +Non-startup handling of bonds appears to be incorrect +so let's fix that. Additionally the speed was not +properly being set in non-startup situations. + +Signed-off-by: Donald Sharp + +diff --git a/zebra/if_netlink.c b/zebra/if_netlink.c +index e54fb09022..ed5b3c4a66 100644 +--- a/zebra/if_netlink.c ++++ b/zebra/if_netlink.c +@@ -938,178 +938,6 @@ static void if_sweep_protodown(struct zebra_if *zif) + dplane_intf_update(zif->ifp); + } + +-/* +- * Called from interface_lookup_netlink(). This function is only used +- * during bootstrap. +- */ +-static int netlink_interface(struct nlmsghdr *h, ns_id_t ns_id, int startup) +-{ +- int len; +- struct ifinfomsg *ifi; +- struct rtattr *tb[IFLA_MAX + 1]; +- struct rtattr *linkinfo[IFLA_MAX + 1]; +- struct interface *ifp; +- char *name = NULL; +- char *kind = NULL; +- char *desc = NULL; +- char *slave_kind = NULL; +- struct zebra_ns *zns = NULL; +- vrf_id_t vrf_id = VRF_DEFAULT; +- enum zebra_iftype zif_type = ZEBRA_IF_OTHER; +- enum zebra_slave_iftype zif_slave_type = ZEBRA_IF_SLAVE_NONE; +- ifindex_t bridge_ifindex = IFINDEX_INTERNAL; +- ifindex_t link_ifindex = IFINDEX_INTERNAL; +- ifindex_t bond_ifindex = IFINDEX_INTERNAL; +- struct zebra_if *zif; +- ns_id_t link_nsid = ns_id; +- uint8_t bypass = 0; +- +- frrtrace(3, frr_zebra, netlink_interface, h, ns_id, startup); +- +- zns = zebra_ns_lookup(ns_id); +- ifi = NLMSG_DATA(h); +- +- if (h->nlmsg_type != RTM_NEWLINK) +- return 0; +- +- len = h->nlmsg_len - NLMSG_LENGTH(sizeof(struct ifinfomsg)); +- if (len < 0) { +- zlog_err( +- "%s: Message received from netlink is of a broken size: %d %zu", +- __func__, h->nlmsg_len, +- (size_t)NLMSG_LENGTH(sizeof(struct ifinfomsg))); +- return -1; +- } +- +- /* We are interested in some AF_BRIDGE notifications. */ +- if (ifi->ifi_family == AF_BRIDGE) +- return netlink_bridge_interface(h, len, ns_id, startup); +- +- /* Looking up interface name. */ +- memset(linkinfo, 0, sizeof(linkinfo)); +- netlink_parse_rtattr_flags(tb, IFLA_MAX, IFLA_RTA(ifi), len, +- NLA_F_NESTED); +- +- /* check for wireless messages to ignore */ +- if ((tb[IFLA_WIRELESS] != NULL) && (ifi->ifi_change == 0)) { +- if (IS_ZEBRA_DEBUG_KERNEL) +- zlog_debug("%s: ignoring IFLA_WIRELESS message", +- __func__); +- return 0; +- } +- +- if (tb[IFLA_IFNAME] == NULL) +- return -1; +- name = (char *)RTA_DATA(tb[IFLA_IFNAME]); +- +- if (tb[IFLA_IFALIAS]) +- desc = (char *)RTA_DATA(tb[IFLA_IFALIAS]); +- +- if (tb[IFLA_LINKINFO]) { +- netlink_parse_rtattr_nested(linkinfo, IFLA_INFO_MAX, +- tb[IFLA_LINKINFO]); +- +- if (linkinfo[IFLA_INFO_KIND]) +- kind = RTA_DATA(linkinfo[IFLA_INFO_KIND]); +- +- if (linkinfo[IFLA_INFO_SLAVE_KIND]) +- slave_kind = RTA_DATA(linkinfo[IFLA_INFO_SLAVE_KIND]); +- +- if ((slave_kind != NULL) && strcmp(slave_kind, "bond") == 0) +- netlink_determine_zebra_iftype("bond_slave", &zif_type); +- else +- netlink_determine_zebra_iftype(kind, &zif_type); +- } +- +- /* If VRF, create the VRF structure itself. */ +- if (zif_type == ZEBRA_IF_VRF && !vrf_is_backend_netns()) { +- netlink_vrf_change(h, tb[IFLA_LINKINFO], ns_id, name); +- vrf_id = (vrf_id_t)ifi->ifi_index; +- } +- +- if (tb[IFLA_MASTER]) { +- if (slave_kind && (strcmp(slave_kind, "vrf") == 0) +- && !vrf_is_backend_netns()) { +- zif_slave_type = ZEBRA_IF_SLAVE_VRF; +- vrf_id = *(uint32_t *)RTA_DATA(tb[IFLA_MASTER]); +- } else if (slave_kind && (strcmp(slave_kind, "bridge") == 0)) { +- zif_slave_type = ZEBRA_IF_SLAVE_BRIDGE; +- bridge_ifindex = +- *(ifindex_t *)RTA_DATA(tb[IFLA_MASTER]); +- } else if (slave_kind && (strcmp(slave_kind, "bond") == 0)) { +- zif_slave_type = ZEBRA_IF_SLAVE_BOND; +- bond_ifindex = *(ifindex_t *)RTA_DATA(tb[IFLA_MASTER]); +- bypass = netlink_parse_lacp_bypass(linkinfo); +- } else +- zif_slave_type = ZEBRA_IF_SLAVE_OTHER; +- } +- if (vrf_is_backend_netns()) +- vrf_id = (vrf_id_t)ns_id; +- +- /* If linking to another interface, note it. */ +- if (tb[IFLA_LINK]) +- link_ifindex = *(ifindex_t *)RTA_DATA(tb[IFLA_LINK]); +- +- if (tb[IFLA_LINK_NETNSID]) { +- link_nsid = *(ns_id_t *)RTA_DATA(tb[IFLA_LINK_NETNSID]); +- link_nsid = ns_id_get_absolute(ns_id, link_nsid); +- } +- +- ifp = if_get_by_name(name, vrf_id, NULL); +- set_ifindex(ifp, ifi->ifi_index, zns); /* add it to ns struct */ +- +- ifp->flags = ifi->ifi_flags & 0x0000fffff; +- ifp->mtu6 = ifp->mtu = *(uint32_t *)RTA_DATA(tb[IFLA_MTU]); +- ifp->metric = 0; +- ifp->speed = get_iflink_speed(ifp, NULL); +- ifp->ptm_status = ZEBRA_PTM_STATUS_UNKNOWN; +- +- /* Set zebra interface type */ +- zebra_if_set_ziftype(ifp, zif_type, zif_slave_type); +- if (IS_ZEBRA_IF_VRF(ifp)) +- SET_FLAG(ifp->status, ZEBRA_INTERFACE_VRF_LOOPBACK); +- +- /* +- * Just set the @link/lower-device ifindex. During nldump interfaces are +- * not ordered in any fashion so we may end up getting upper devices +- * before lower devices. We will setup the real linkage once the dump +- * is complete. +- */ +- zif = (struct zebra_if *)ifp->info; +- zif->link_ifindex = link_ifindex; +- +- if (desc) { +- XFREE(MTYPE_ZIF_DESC, zif->desc); +- zif->desc = XSTRDUP(MTYPE_ZIF_DESC, desc); +- } +- +- /* Hardware type and address. */ +- ifp->ll_type = netlink_to_zebra_link_type(ifi->ifi_type); +- +- netlink_interface_update_hw_addr(tb, ifp); +- +- if_add_update(ifp); +- +- /* Extract and save L2 interface information, take additional actions. +- */ +- netlink_interface_update_l2info(ifp, linkinfo[IFLA_INFO_DATA], +- 1, link_nsid); +- if (IS_ZEBRA_IF_BOND(ifp)) +- zebra_l2if_update_bond(ifp, true); +- if (IS_ZEBRA_IF_BRIDGE_SLAVE(ifp)) +- zebra_l2if_update_bridge_slave(ifp, bridge_ifindex, ns_id, +- ZEBRA_BRIDGE_NO_ACTION); +- else if (IS_ZEBRA_IF_BOND_SLAVE(ifp)) +- zebra_l2if_update_bond_slave(ifp, bond_ifindex, !!bypass); +- +- if (tb[IFLA_PROTO_DOWN]) { +- netlink_proc_dplane_if_protodown(zif, tb); +- if_sweep_protodown(zif); +- } +- +- return 0; +-} +- + /* Request for specific interface or address information from the kernel */ + static int netlink_request_intf_addr(struct nlsock *netlink_cmd, int family, + int type, uint32_t filter_mask) +@@ -1165,7 +993,7 @@ int interface_lookup_netlink(struct zebra_ns *zns) + ret = netlink_request_intf_addr(netlink_cmd, AF_PACKET, RTM_GETLINK, 0); + if (ret < 0) + return ret; +- ret = netlink_parse_info(netlink_interface, netlink_cmd, &dp_info, 0, ++ ret = netlink_parse_info(netlink_link_change, netlink_cmd, &dp_info, 0, + true); + if (ret < 0) + return ret; +@@ -1175,7 +1003,7 @@ int interface_lookup_netlink(struct zebra_ns *zns) + RTEXT_FILTER_BRVLAN); + if (ret < 0) + return ret; +- ret = netlink_parse_info(netlink_interface, netlink_cmd, &dp_info, 0, ++ ret = netlink_parse_info(netlink_link_change, netlink_cmd, &dp_info, 0, + true); + if (ret < 0) + return ret; +@@ -1816,6 +1644,8 @@ int netlink_link_change(struct nlmsghdr *h, ns_id_t ns_id, int startup) + ifindex_t master_infindex = IFINDEX_INTERNAL; + uint8_t bypass = 0; + ++ frrtrace(3, frr_zebra, netlink_interface, h, ns_id, startup); ++ + zns = zebra_ns_lookup(ns_id); + ifi = NLMSG_DATA(h); + +@@ -1884,7 +1714,10 @@ int netlink_link_change(struct nlmsghdr *h, ns_id_t ns_id, int startup) + if (linkinfo[IFLA_INFO_SLAVE_KIND]) + slave_kind = RTA_DATA(linkinfo[IFLA_INFO_SLAVE_KIND]); + +- netlink_determine_zebra_iftype(kind, &zif_type); ++ if ((slave_kind != NULL) && strcmp(slave_kind, "bond") == 0) ++ netlink_determine_zebra_iftype("bond_slave", &zif_type); ++ else ++ netlink_determine_zebra_iftype(kind, &zif_type); + } + + /* If linking to another interface, note it. */ +@@ -1961,6 +1794,7 @@ int netlink_link_change(struct nlmsghdr *h, ns_id_t ns_id, int startup) + } + ifp->mtu6 = ifp->mtu = *(int *)RTA_DATA(tb[IFLA_MTU]); + ifp->metric = 0; ++ ifp->speed = get_iflink_speed(ifp, NULL); + ifp->ptm_status = ZEBRA_PTM_STATUS_UNKNOWN; + + /* Set interface type */ +@@ -1972,6 +1806,16 @@ int netlink_link_change(struct nlmsghdr *h, ns_id_t ns_id, int startup) + /* Update link. */ + zebra_if_update_link(ifp, link_ifindex, link_nsid); + ++ /* ++ * Just set the @link/lower-device ifindex. During ++ * nldump interfaces are not ordered in any fashion so ++ * we may end up getting upper devices before lower ++ * devices. We will setup the real linkage once the dump ++ * is complete. ++ */ ++ zif = (struct zebra_if *)ifp->info; ++ zif->link_ifindex = link_ifindex; ++ + ifp->ll_type = + netlink_to_zebra_link_type(ifi->ifi_type); + netlink_interface_update_hw_addr(tb, ifp); +@@ -1984,6 +1828,8 @@ int netlink_link_change(struct nlmsghdr *h, ns_id_t ns_id, int startup) + netlink_interface_update_l2info( + ifp, linkinfo[IFLA_INFO_DATA], + 1, link_nsid); ++ if (IS_ZEBRA_IF_BOND(ifp)) ++ zebra_l2if_update_bond(ifp, true); + if (IS_ZEBRA_IF_BRIDGE_SLAVE(ifp)) + zebra_l2if_update_bridge_slave( + ifp, bridge_ifindex, ns_id, +@@ -1992,10 +1838,12 @@ int netlink_link_change(struct nlmsghdr *h, ns_id_t ns_id, int startup) + zebra_l2if_update_bond_slave(ifp, bond_ifindex, + !!bypass); + +- if (tb[IFLA_PROTO_DOWN]) ++ if (tb[IFLA_PROTO_DOWN]) { + netlink_proc_dplane_if_protodown(ifp->info, tb); ++ if (startup) ++ if_sweep_protodown(zif); ++ } + if (IS_ZEBRA_IF_BRIDGE(ifp)) { +- zif = ifp->info; + if (IS_ZEBRA_DEBUG_KERNEL) + zlog_debug( + "RTM_NEWLINK ADD for %s(%u), vlan-aware %d", +@@ -2329,7 +2177,7 @@ int netlink_tunneldump_read(struct zebra_ns *zns) + if (ret < 0) + return ret; + +- ret = netlink_parse_info(netlink_interface, netlink_cmd, ++ ret = netlink_parse_info(netlink_link_change, netlink_cmd, + &dp_info, 0, true); + + if (ret < 0) +-- +2.17.1 + diff --git a/src/sonic-frr/patch/0017-zebra-Add-code-to-get-set-interface-to-pass-up-from-.patch b/src/sonic-frr/patch/0017-zebra-Add-code-to-get-set-interface-to-pass-up-from-.patch new file mode 100644 index 000000000000..c46c29737a0e --- /dev/null +++ b/src/sonic-frr/patch/0017-zebra-Add-code-to-get-set-interface-to-pass-up-from-.patch @@ -0,0 +1,809 @@ +From 1b576b080613cd545ecd742b6a16146ab781695f Mon Sep 17 00:00:00 2001 +From: Donald Sharp +Date: Thu, 20 Apr 2023 08:51:42 -0400 +Subject: [PATCH] zebra: Add code to get/set interface to pass up from dplane + +1) Add a bunch of get/set functions and associated data +structure in zebra_dplane to allow the setting and retrieval +of interface netlink data up into the master pthread. + +2) Add a bit of code to breakup startup into stages. This is +because FRR currently has a mix of dplane and non dplane interactions +and the code needs to be paused before continuing on. + +Signed-off-by: Donald Sharp + +diff --git a/zebra/dplane_fpm_nl.c b/zebra/dplane_fpm_nl.c +index 804eb43a44..0d629fe0b9 100644 +--- a/zebra/dplane_fpm_nl.c ++++ b/zebra/dplane_fpm_nl.c +@@ -955,6 +955,7 @@ static int fpm_nl_enqueue(struct fpm_nl_ctx *fnc, struct zebra_dplane_ctx *ctx) + case DPLANE_OP_TC_FILTER_DELETE: + case DPLANE_OP_TC_FILTER_UPDATE: + case DPLANE_OP_NONE: ++ case DPLANE_OP_STARTUP_STAGE: + break; + + } +diff --git a/zebra/interface.c b/zebra/interface.c +index 84e52d4b43..a05b9690ef 100644 +--- a/zebra/interface.c ++++ b/zebra/interface.c +@@ -1590,6 +1590,7 @@ void zebra_if_dplane_result(struct zebra_dplane_ctx *ctx) + case DPLANE_OP_TC_FILTER_ADD: + case DPLANE_OP_TC_FILTER_DELETE: + case DPLANE_OP_TC_FILTER_UPDATE: ++ case DPLANE_OP_STARTUP_STAGE: + break; /* should never hit here */ + } + } +diff --git a/zebra/kernel_netlink.c b/zebra/kernel_netlink.c +index 42afe61469..4cd84cada2 100644 +--- a/zebra/kernel_netlink.c ++++ b/zebra/kernel_netlink.c +@@ -1632,6 +1632,7 @@ static enum netlink_msg_status nl_put_msg(struct nl_batch *bth, + case DPLANE_OP_IPSET_DELETE: + case DPLANE_OP_IPSET_ENTRY_ADD: + case DPLANE_OP_IPSET_ENTRY_DELETE: ++ case DPLANE_OP_STARTUP_STAGE: + return FRR_NETLINK_ERROR; + + case DPLANE_OP_GRE_SET: +diff --git a/zebra/kernel_socket.c b/zebra/kernel_socket.c +index 684ccc3ed5..f3462b9f22 100644 +--- a/zebra/kernel_socket.c ++++ b/zebra/kernel_socket.c +@@ -1631,6 +1631,7 @@ void kernel_update_multi(struct dplane_ctx_list_head *ctx_list) + case DPLANE_OP_GRE_SET: + case DPLANE_OP_INTF_ADDR_ADD: + case DPLANE_OP_INTF_ADDR_DEL: ++ case DPLANE_OP_STARTUP_STAGE: + zlog_err("Unhandled dplane data for %s", + dplane_op2str(dplane_ctx_get_op(ctx))); + res = ZEBRA_DPLANE_REQUEST_FAILURE; +diff --git a/zebra/zebra_dplane.c b/zebra/zebra_dplane.c +index a6c08f7371..0b33a5189c 100644 +--- a/zebra/zebra_dplane.c ++++ b/zebra/zebra_dplane.c +@@ -193,10 +193,43 @@ struct dplane_br_port_info { + */ + struct dplane_intf_info { + ++ enum zebra_iftype zif_type; ++ ifindex_t bond_ifindex; ++ ifindex_t link_ifindex; ++ int32_t mtu; ++ vrf_id_t vrf_id; ++ enum zebra_slave_iftype zif_slave_type; ++ ifindex_t master_ifindex; ++ ifindex_t bridge_ifindex; ++ ns_id_t link_nsid; ++ enum zebra_slave_iftype zslave_type; ++ uint8_t bypass; ++ enum zebra_link_type zltype; ++ bool startup; ++ uint8_t family; ++ struct zebra_vxlan_vni_array *vniarray; ++ struct zebra_dplane_bridge_vlan_info bvinfo; ++ struct zebra_dplane_bridge_vlan_info_array *bvarray; ++ ++ char desc[128]; ++ ++ int32_t hw_addr_len; ++ uint8_t hw_addr[INTERFACE_HWADDR_MAX]; ++ ++ uint32_t table_id; ++ ++ struct zebra_l2info_bridge binfo; ++ struct zebra_l2info_vlan vinfo; ++ struct zebra_l2info_vxlan vxinfo; ++ struct zebra_l2info_gre grinfo; ++ ++ uint32_t rc_bitfield; ++ + uint32_t metric; + uint32_t flags; + + bool protodown; ++ bool protodown_set; + bool pd_reason_val; + + #define DPLANE_INTF_CONNECTED (1 << 0) /* Connected peer, p2p */ +@@ -408,6 +441,7 @@ struct zebra_dplane_ctx { + struct dplane_neigh_table neightable; + struct dplane_gre_ctx gre; + struct dplane_netconf_info netconf; ++ enum zebra_dplane_startup_notifications spot; + } u; + + /* Namespace info, used especially for netlink kernel communication */ +@@ -820,8 +854,14 @@ static void dplane_ctx_free_internal(struct zebra_dplane_ctx *ctx) + case DPLANE_OP_NONE: + case DPLANE_OP_IPSET_ADD: + case DPLANE_OP_IPSET_DELETE: ++ break; + case DPLANE_OP_INTF_INSTALL: + case DPLANE_OP_INTF_UPDATE: ++ if (ctx->u.intf.vniarray) ++ XFREE(MTYPE_TMP, ctx->u.intf.vniarray); ++ if (ctx->u.intf.bvarray) ++ XFREE(MTYPE_TMP, ctx->u.intf.bvarray); ++ break; + case DPLANE_OP_INTF_DELETE: + case DPLANE_OP_TC_QDISC_INSTALL: + case DPLANE_OP_TC_QDISC_UNINSTALL: +@@ -845,6 +885,7 @@ static void dplane_ctx_free_internal(struct zebra_dplane_ctx *ctx) + break; + case DPLANE_OP_GRE_SET: + case DPLANE_OP_INTF_NETCONFIG: ++ case DPLANE_OP_STARTUP_STAGE: + break; + } + } +@@ -1168,6 +1209,8 @@ const char *dplane_op2str(enum dplane_op_e op) + case DPLANE_OP_TC_FILTER_UPDATE: + ret = "TC__FILTER_UPDATE"; + break; ++ case DPLANE_OP_STARTUP_STAGE: ++ ret = "STARTUP_STAGE"; + } + + return ret; +@@ -1309,6 +1352,422 @@ const char *dplane_ctx_get_ifname(const struct zebra_dplane_ctx *ctx) + return ctx->zd_ifname; + } + ++void dplane_ctx_set_ifp_bridge_vlan_info_array( ++ struct zebra_dplane_ctx *ctx, ++ struct zebra_dplane_bridge_vlan_info_array *bvarray) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ ctx->u.intf.bvarray = bvarray; ++} ++ ++const struct zebra_dplane_bridge_vlan_info_array * ++dplane_ctx_get_ifp_bridge_vlan_info_array(const struct zebra_dplane_ctx *ctx) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ return ctx->u.intf.bvarray; ++} ++ ++void dplane_ctx_set_ifp_vxlan_vni_array(struct zebra_dplane_ctx *ctx, ++ struct zebra_vxlan_vni_array *vniarray) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ ctx->u.intf.vniarray = vniarray; ++} ++ ++const struct zebra_vxlan_vni_array * ++dplane_ctx_get_ifp_vxlan_vni_array(const struct zebra_dplane_ctx *ctx) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ return ctx->u.intf.vniarray; ++} ++ ++void dplane_ctx_set_ifp_bridge_vlan_info( ++ struct zebra_dplane_ctx *ctx, ++ struct zebra_dplane_bridge_vlan_info *bvinfo) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ ctx->u.intf.bvinfo = *bvinfo; ++} ++ ++const struct zebra_dplane_bridge_vlan_info * ++dplane_ctx_get_ifp_bridge_vlan_info(const struct zebra_dplane_ctx *ctx) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ return &ctx->u.intf.bvinfo; ++} ++ ++void dplane_ctx_set_ifp_family(struct zebra_dplane_ctx *ctx, uint8_t family) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ ctx->u.intf.family = family; ++} ++ ++uint8_t dplane_ctx_get_ifp_family(const struct zebra_dplane_ctx *ctx) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ return ctx->u.intf.family; ++} ++ ++void dplane_ctx_set_ifp_zltype(struct zebra_dplane_ctx *ctx, ++ enum zebra_link_type zltype) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ ctx->u.intf.zltype = zltype; ++} ++ ++enum zebra_link_type ++dplane_ctx_get_ifp_zltype(const struct zebra_dplane_ctx *ctx) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ return ctx->u.intf.zltype; ++} ++ ++void dplane_ctx_set_ifp_link_ifindex(struct zebra_dplane_ctx *ctx, ++ ifindex_t link_ifindex) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ ctx->u.intf.link_ifindex = link_ifindex; ++} ++ ++ifindex_t dplane_ctx_get_ifp_link_ifindex(const struct zebra_dplane_ctx *ctx) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ return ctx->u.intf.link_ifindex; ++} ++ ++void dplane_ctx_set_ifp_desc(struct zebra_dplane_ctx *ctx, const char *desc) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ strlcpy(ctx->u.intf.desc, desc, sizeof(ctx->u.intf.desc)); ++} ++ ++char *dplane_ctx_get_ifp_desc(struct zebra_dplane_ctx *ctx) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ return ctx->u.intf.desc; ++} ++ ++void dplane_ctx_set_ifp_flags(struct zebra_dplane_ctx *ctx, uint64_t flags) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ ctx->u.intf.flags = flags; ++} ++ ++uint64_t dplane_ctx_get_ifp_flags(const struct zebra_dplane_ctx *ctx) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ return ctx->u.intf.flags; ++} ++ ++void dplane_ctx_set_ifp_bypass(struct zebra_dplane_ctx *ctx, uint8_t bypass) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ ctx->u.intf.bypass = bypass; ++} ++ ++uint8_t dplane_ctx_get_ifp_bypass(const struct zebra_dplane_ctx *ctx) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ return ctx->u.intf.bypass; ++} ++ ++void dplane_ctx_set_ifp_bridge_ifindex(struct zebra_dplane_ctx *ctx, ++ ifindex_t bridge_ifindex) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ ctx->u.intf.bridge_ifindex = bridge_ifindex; ++} ++ ++ifindex_t dplane_ctx_get_ifp_bridge_ifindex(const struct zebra_dplane_ctx *ctx) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ return ctx->u.intf.bridge_ifindex; ++} ++ ++void dplane_ctx_set_ifp_zif_slave_type(struct zebra_dplane_ctx *ctx, ++ enum zebra_slave_iftype zslave_type) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ ctx->u.intf.zslave_type = zslave_type; ++} ++ ++enum zebra_slave_iftype ++dplane_ctx_get_ifp_zif_slave_type(const struct zebra_dplane_ctx *ctx) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ return ctx->u.intf.zslave_type; ++} ++ ++void dplane_ctx_set_ifp_master_ifindex(struct zebra_dplane_ctx *ctx, ++ ifindex_t master_ifindex) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ ctx->u.intf.master_ifindex = master_ifindex; ++} ++ ++ifindex_t dplane_ctx_get_ifp_master_ifindex(const struct zebra_dplane_ctx *ctx) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ return ctx->u.intf.master_ifindex; ++} ++ ++void dplane_ctx_set_ifp_mtu(struct zebra_dplane_ctx *ctx, uint32_t mtu) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ ctx->u.intf.mtu = mtu; ++} ++ ++uint32_t dplane_ctx_get_ifp_mtu(const struct zebra_dplane_ctx *ctx) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ return ctx->u.intf.mtu; ++} ++ ++void dplane_ctx_set_ifp_vrf_id(struct zebra_dplane_ctx *ctx, vrf_id_t vrf_id) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ ctx->u.intf.vrf_id = vrf_id; ++} ++ ++vrf_id_t dplane_ctx_get_ifp_vrf_id(const struct zebra_dplane_ctx *ctx) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ return ctx->u.intf.vrf_id; ++} ++ ++void dplane_ctx_set_ifp_link_nsid(struct zebra_dplane_ctx *ctx, ++ ns_id_t link_nsid) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ ctx->u.intf.link_nsid = link_nsid; ++} ++ ++ns_id_t dplane_ctx_get_ifp_link_nsid(const struct zebra_dplane_ctx *ctx) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ return ctx->u.intf.link_nsid; ++} ++ ++void dplane_ctx_set_ifp_startup(struct zebra_dplane_ctx *ctx, bool startup) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ ctx->u.intf.startup = startup; ++} ++ ++bool dplane_ctx_get_ifp_startup(const struct zebra_dplane_ctx *ctx) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ return ctx->u.intf.startup; ++} ++ ++void dplane_ctx_set_ifp_protodown_set(struct zebra_dplane_ctx *ctx, bool set) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ ctx->u.intf.protodown_set = set; ++} ++ ++bool dplane_ctx_get_ifp_protodown_set(const struct zebra_dplane_ctx *ctx) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ return ctx->u.intf.protodown_set; ++} ++ ++void dplane_ctx_set_ifp_protodown(struct zebra_dplane_ctx *ctx, bool protodown) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ ctx->u.intf.protodown = protodown; ++} ++ ++bool dplane_ctx_get_ifp_protodown(const struct zebra_dplane_ctx *ctx) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ return ctx->u.intf.protodown; ++} ++ ++ifindex_t dplane_ctx_get_ifp_bond_ifindex(const struct zebra_dplane_ctx *ctx) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ return ctx->u.intf.bond_ifindex; ++} ++ ++void dplane_ctx_set_ifp_rc_bitfield(struct zebra_dplane_ctx *ctx, ++ uint32_t rc_bitfield) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ ctx->u.intf.rc_bitfield = rc_bitfield; ++} ++ ++uint32_t dplane_ctx_get_ifp_rc_bitfield(const struct zebra_dplane_ctx *ctx) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ return ctx->u.intf.rc_bitfield; ++} ++ ++void dplane_ctx_set_ifp_gre_info(struct zebra_dplane_ctx *ctx, ++ struct zebra_l2info_gre *grinfo) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ ctx->u.intf.grinfo = *grinfo; ++} ++ ++const struct zebra_l2info_gre * ++dplane_ctx_get_ifp_gre_info(const struct zebra_dplane_ctx *ctx) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ return &ctx->u.intf.grinfo; ++} ++ ++void dplane_ctx_set_ifp_vxlan_info(struct zebra_dplane_ctx *ctx, ++ struct zebra_l2info_vxlan *vxinfo) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ ctx->u.intf.vxinfo = *vxinfo; ++} ++ ++const struct zebra_l2info_vxlan * ++dplane_ctx_get_ifp_vxlan_info(const struct zebra_dplane_ctx *ctx) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ return &ctx->u.intf.vxinfo; ++} ++ ++void dplane_ctx_set_ifp_vlan_info(struct zebra_dplane_ctx *ctx, ++ struct zebra_l2info_vlan *vinfo) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ ctx->u.intf.vinfo = *vinfo; ++} ++ ++const struct zebra_l2info_vlan * ++dplane_ctx_get_ifp_vlan_info(const struct zebra_dplane_ctx *ctx) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ return &ctx->u.intf.vinfo; ++} ++ ++void dplane_ctx_set_ifp_bridge_info(struct zebra_dplane_ctx *ctx, ++ struct zebra_l2info_bridge *binfo) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ ctx->u.intf.binfo = *binfo; ++} ++ ++const struct zebra_l2info_bridge * ++dplane_ctx_get_ifp_bridge_info(const struct zebra_dplane_ctx *ctx) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ return &ctx->u.intf.binfo; ++} ++ ++void dplane_ctx_set_ifp_table_id(struct zebra_dplane_ctx *ctx, ++ uint32_t table_id) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ ctx->u.intf.table_id = table_id; ++} ++ ++uint32_t dplane_ctx_get_ifp_table_id(const struct zebra_dplane_ctx *ctx) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ return ctx->u.intf.table_id; ++} ++ ++void dplane_ctx_set_ifp_hw_addr(struct zebra_dplane_ctx *ctx, ++ int32_t hw_addr_len, uint8_t *hw_addr) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ ctx->u.intf.hw_addr_len = hw_addr_len; ++ memcpy(ctx->u.intf.hw_addr, hw_addr, hw_addr_len); ++} ++ ++int32_t dplane_ctx_get_ifp_hw_addr_len(const struct zebra_dplane_ctx *ctx) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ return ctx->u.intf.hw_addr_len; ++} ++ ++const uint8_t *dplane_ctx_get_ifp_hw_addr(const struct zebra_dplane_ctx *ctx) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ return ctx->u.intf.hw_addr; ++} ++ ++void dplane_ctx_set_ifp_bond_ifindex(struct zebra_dplane_ctx *ctx, ++ ifindex_t bond_ifindex) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ ctx->u.intf.bond_ifindex = bond_ifindex; ++} ++ ++enum zebra_iftype ++dplane_ctx_get_ifp_zif_type(const struct zebra_dplane_ctx *ctx) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ return ctx->u.intf.zif_type; ++} ++ ++void dplane_ctx_set_ifp_zif_type(struct zebra_dplane_ctx *ctx, ++ enum zebra_iftype zif_type) ++{ ++ DPLANE_CTX_VALID(ctx); ++ ++ ctx->u.intf.zif_type = zif_type; ++} ++ + void dplane_ctx_set_ifname(struct zebra_dplane_ctx *ctx, const char *ifname) + { + DPLANE_CTX_VALID(ctx); +@@ -6102,6 +6561,7 @@ static void kernel_dplane_log_detail(struct zebra_dplane_ctx *ctx) + case DPLANE_OP_TC_FILTER_ADD: + case DPLANE_OP_TC_FILTER_DELETE: + case DPLANE_OP_TC_FILTER_UPDATE: ++ case DPLANE_OP_STARTUP_STAGE: + break; + } + } +@@ -6274,6 +6734,7 @@ static void kernel_dplane_handle_result(struct zebra_dplane_ctx *ctx) + break; + + case DPLANE_OP_NONE: ++ case DPLANE_OP_STARTUP_STAGE: + if (res != ZEBRA_DPLANE_REQUEST_SUCCESS) + atomic_fetch_add_explicit(&zdplane_info.dg_other_errors, + 1, memory_order_relaxed); +@@ -6966,6 +7427,25 @@ void zebra_dplane_start(void) + frr_pthread_run(zdplane_info.dg_pthread, NULL); + } + ++enum zebra_dplane_startup_notifications ++dplane_ctx_get_startup_spot(struct zebra_dplane_ctx *ctx) ++{ ++ return ctx->u.spot; ++} ++ ++void zebra_dplane_startup_stage(struct zebra_ns *zns, ++ enum zebra_dplane_startup_notifications spot) ++{ ++ struct zebra_dplane_ctx *ctx = dplane_ctx_alloc(); ++ ++ ctx->zd_op = DPLANE_OP_STARTUP_STAGE; ++ ctx->zd_status = ZEBRA_DPLANE_REQUEST_QUEUED; ++ ++ ctx->u.spot = spot; ++ dplane_ctx_set_ns_id(ctx, zns->ns_id); ++ ++ dplane_provider_enqueue_to_zebra(ctx); ++} + /* + * Initialize the dataplane module at startup; called by zebra rib_init() + */ +diff --git a/zebra/zebra_dplane.h b/zebra/zebra_dplane.h +index 9ef0afd3a8..c10482ed96 100644 +--- a/zebra/zebra_dplane.h ++++ b/zebra/zebra_dplane.h +@@ -100,6 +100,11 @@ enum zebra_dplane_result { + ZEBRA_DPLANE_REQUEST_FAILURE, + }; + ++enum zebra_dplane_startup_notifications { ++ ZEBRA_DPLANE_INTERFACES_READ, ++ ZEBRA_DPLANE_TUNNELS_READ, ++ ZEBRA_DPLANE_ADDRESSES_READ, ++}; + /* + * API between the zebra dataplane system and the main zebra processing + * context. +@@ -201,7 +206,10 @@ enum dplane_op_e { + DPLANE_OP_TC_CLASS_UPDATE, + DPLANE_OP_TC_FILTER_ADD, + DPLANE_OP_TC_FILTER_DELETE, +- DPLANE_OP_TC_FILTER_UPDATE ++ DPLANE_OP_TC_FILTER_UPDATE, ++ ++ /* Startup Control */ ++ DPLANE_OP_STARTUP_STAGE, + }; + + /* +@@ -336,6 +344,105 @@ const char *dplane_ctx_get_ifname(const struct zebra_dplane_ctx *ctx); + void dplane_ctx_set_ifname(struct zebra_dplane_ctx *ctx, const char *ifname); + ifindex_t dplane_ctx_get_ifindex(const struct zebra_dplane_ctx *ctx); + void dplane_ctx_set_ifindex(struct zebra_dplane_ctx *ctx, ifindex_t ifindex); ++void dplane_ctx_set_ifp_bond_ifindex(struct zebra_dplane_ctx *ctx, ++ ifindex_t ifindex); ++ifindex_t dplane_ctx_get_ifp_bond_ifindex(const struct zebra_dplane_ctx *ctx); ++enum zebra_iftype ++dplane_ctx_get_ifp_zif_type(const struct zebra_dplane_ctx *ctx); ++void dplane_ctx_set_ifp_zif_type(struct zebra_dplane_ctx *ctx, ++ enum zebra_iftype zif_type); ++void dplane_ctx_set_ifp_table_id(struct zebra_dplane_ctx *ctx, ++ uint32_t table_id); ++uint32_t dplane_ctx_get_ifp_table_id(const struct zebra_dplane_ctx *ctx); ++void dplane_ctx_set_ifp_hw_addr(struct zebra_dplane_ctx *ctx, ++ int32_t hw_addr_len, uint8_t *hw_addr); ++int32_t dplane_ctx_get_ifp_hw_addr_len(const struct zebra_dplane_ctx *ctx); ++const uint8_t *dplane_ctx_get_ifp_hw_addr(const struct zebra_dplane_ctx *ctx); ++struct zebra_l2info_bridge; ++void dplane_ctx_set_ifp_bridge_info(struct zebra_dplane_ctx *ctx, ++ struct zebra_l2info_bridge *binfo); ++const struct zebra_l2info_bridge * ++dplane_ctx_get_ifp_bridge_info(const struct zebra_dplane_ctx *ctx); ++struct zebra_l2info_vlan; ++void dplane_ctx_set_ifp_vlan_info(struct zebra_dplane_ctx *ctx, ++ struct zebra_l2info_vlan *vinfo); ++const struct zebra_l2info_vlan * ++dplane_ctx_get_ifp_vlan_info(const struct zebra_dplane_ctx *ctx); ++struct zebra_l2info_vxlan; ++void dplane_ctx_set_ifp_vxlan_info(struct zebra_dplane_ctx *ctx, ++ struct zebra_l2info_vxlan *vxinfo); ++const struct zebra_l2info_vxlan * ++dplane_ctx_get_ifp_vxlan_info(const struct zebra_dplane_ctx *ctx); ++struct zebra_l2info_gre; ++void dplane_ctx_set_ifp_gre_info(struct zebra_dplane_ctx *ctx, ++ struct zebra_l2info_gre *greinfo); ++const struct zebra_l2info_gre * ++dplane_ctx_get_ifp_gre_info(const struct zebra_dplane_ctx *ctx); ++void dplane_ctx_set_ifp_zltype(struct zebra_dplane_ctx *ctx, ++ enum zebra_link_type zlt); ++enum zebra_link_type ++dplane_ctx_get_ifp_zltype(const struct zebra_dplane_ctx *ctx); ++void dplane_ctx_set_ifp_link_nsid(struct zebra_dplane_ctx *ctx, ns_id_t ns_id); ++ns_id_t dplane_ctx_get_ifp_link_nsid(const struct zebra_dplane_ctx *ctx); ++void dplane_ctx_set_ifp_desc(struct zebra_dplane_ctx *ctx, const char *desc); ++char *dplane_ctx_get_ifp_desc(struct zebra_dplane_ctx *ctx); ++void dplane_ctx_set_ifp_mtu(struct zebra_dplane_ctx *ctx, uint32_t mtu); ++uint32_t dplane_ctx_get_ifp_mtu(const struct zebra_dplane_ctx *ctx); ++void dplane_ctx_set_ifp_vrf_id(struct zebra_dplane_ctx *ctx, vrf_id_t vrf_id); ++vrf_id_t dplane_ctx_get_ifp_vrf_id(const struct zebra_dplane_ctx *ctx); ++enum zebra_slave_iftype; ++void dplane_ctx_set_ifp_zif_slave_type(struct zebra_dplane_ctx *ctx, ++ enum zebra_slave_iftype zslave_type); ++enum zebra_slave_iftype ++dplane_ctx_get_ifp_zif_slave_type(const struct zebra_dplane_ctx *ctx); ++void dplane_ctx_set_ifp_master_ifindex(struct zebra_dplane_ctx *ctx, ++ ifindex_t master_ifindex); ++ifindex_t dplane_ctx_get_ifp_master_ifindex(const struct zebra_dplane_ctx *ctx); ++void dplane_ctx_set_ifp_bridge_ifindex(struct zebra_dplane_ctx *ctx, ++ ifindex_t bridge_ifindex); ++ifindex_t dplane_ctx_get_ifp_bridge_ifindex(const struct zebra_dplane_ctx *ctx); ++void dplane_ctx_set_ifp_bypass(struct zebra_dplane_ctx *ctx, uint8_t bypass); ++uint8_t dplane_ctx_get_ifp_bypass(const struct zebra_dplane_ctx *ctx); ++void dplane_ctx_set_ifp_flags(struct zebra_dplane_ctx *ctx, uint64_t flags); ++uint64_t dplane_ctx_get_ifp_flags(const struct zebra_dplane_ctx *ctx); ++void dplane_ctx_set_ifp_protodown(struct zebra_dplane_ctx *ctx, bool protodown); ++bool dplane_ctx_get_ifp_protodown(const struct zebra_dplane_ctx *ctx); ++void dplane_ctx_set_ifp_startup(struct zebra_dplane_ctx *ctx, bool startup); ++bool dplane_ctx_get_ifp_startup(const struct zebra_dplane_ctx *ctx); ++void dplane_ctx_set_ifp_protodown_set(struct zebra_dplane_ctx *ctx, bool set); ++bool dplane_ctx_get_ifp_protodown_set(const struct zebra_dplane_ctx *ctx); ++void dplane_ctx_set_ifp_rc_bitfield(struct zebra_dplane_ctx *ctx, ++ uint32_t rc_bitfield); ++uint32_t dplane_ctx_get_ifp_rc_bitfield(const struct zebra_dplane_ctx *ctx); ++void dplane_ctx_set_ifp_link_ifindex(struct zebra_dplane_ctx *ctx, ++ ifindex_t link_ifindex); ++ifindex_t dplane_ctx_get_ifp_link_ifindex(const struct zebra_dplane_ctx *ctx); ++void dplane_ctx_set_ifp_family(struct zebra_dplane_ctx *ctx, uint8_t family); ++uint8_t dplane_ctx_get_ifp_family(const struct zebra_dplane_ctx *ctx); ++struct zebra_vxlan_vni_array; ++void dplane_ctx_set_ifp_vxlan_vni_array(struct zebra_dplane_ctx *ctx, ++ struct zebra_vxlan_vni_array *vniarray); ++const struct zebra_vxlan_vni_array * ++dplane_ctx_get_ifp_vxlan_vni_array(const struct zebra_dplane_ctx *ctx); ++struct zebra_dplane_bridge_vlan_info { ++ uint16_t flags; ++ uint16_t vid; ++}; ++void dplane_ctx_set_ifp_bridge_vlan_info( ++ struct zebra_dplane_ctx *ctx, ++ struct zebra_dplane_bridge_vlan_info *bvinfo); ++const struct zebra_dplane_bridge_vlan_info * ++dplane_ctx_get_ifp_bridge_vlan_info(const struct zebra_dplane_ctx *ctx); ++ ++struct zebra_dplane_bridge_vlan_info_array { ++ int count; ++ struct zebra_dplane_bridge_vlan_info array[0]; ++}; ++void dplane_ctx_set_ifp_bridge_vlan_info_array( ++ struct zebra_dplane_ctx *ctx, ++ struct zebra_dplane_bridge_vlan_info_array *bvarray); ++const struct zebra_dplane_bridge_vlan_info_array * ++dplane_ctx_get_ifp_bridge_vlan_info_array(const struct zebra_dplane_ctx *ctx); + + /* Retrieve last/current provider id */ + uint32_t dplane_ctx_get_provider(const struct zebra_dplane_ctx *ctx); +@@ -1083,6 +1190,9 @@ void zebra_dplane_pre_finish(void); + void zebra_dplane_finish(void); + void zebra_dplane_shutdown(void); + ++void zebra_dplane_startup_stage(struct zebra_ns *zns, ++ enum zebra_dplane_startup_notifications spot); ++ + /* + * decision point for sending a routing update through the old + * straight to zebra master pthread or through the dplane to +@@ -1093,6 +1203,9 @@ void dplane_rib_add_multipath(afi_t afi, safi_t safi, struct prefix *p, + struct nexthop_group *ng, int startup, + struct zebra_dplane_ctx *ctx); + ++enum zebra_dplane_startup_notifications ++dplane_ctx_get_startup_spot(struct zebra_dplane_ctx *ctx); ++ + #ifdef __cplusplus + } + #endif +diff --git a/zebra/zebra_nhg.c b/zebra/zebra_nhg.c +index 758fed7280..8f686eb5f8 100644 +--- a/zebra/zebra_nhg.c ++++ b/zebra/zebra_nhg.c +@@ -3177,6 +3177,7 @@ void zebra_nhg_dplane_result(struct zebra_dplane_ctx *ctx) + case DPLANE_OP_TC_FILTER_ADD: + case DPLANE_OP_TC_FILTER_DELETE: + case DPLANE_OP_TC_FILTER_UPDATE: ++ case DPLANE_OP_STARTUP_STAGE: + break; + } + } +diff --git a/zebra/zebra_rib.c b/zebra/zebra_rib.c +index 5e50d720a6..201fc761ae 100644 +--- a/zebra/zebra_rib.c ++++ b/zebra/zebra_rib.c +@@ -4770,6 +4770,7 @@ static void rib_process_dplane_results(struct thread *thread) + case DPLANE_OP_NEIGH_TABLE_UPDATE: + case DPLANE_OP_GRE_SET: + case DPLANE_OP_NONE: ++ case DPLANE_OP_STARTUP_STAGE: + break; + + } /* Dispatch by op code */ +diff --git a/zebra/zebra_script.c b/zebra/zebra_script.c +index 5c67ad4f16..22c1824b5a 100644 +--- a/zebra/zebra_script.c ++++ b/zebra/zebra_script.c +@@ -428,6 +428,7 @@ void lua_pushzebra_dplane_ctx(lua_State *L, const struct zebra_dplane_ctx *ctx) + /* Not currently handled */ + case DPLANE_OP_INTF_NETCONFIG: /*NYI*/ + case DPLANE_OP_NONE: ++ case DPLANE_OP_STARTUP_STAGE: + break; + } /* Dispatch by op code */ + } +-- +2.17.1 + diff --git a/src/sonic-frr/patch/0017-zebra-Re-arrange-fpm_read-to-reduce-code-duplication.patch b/src/sonic-frr/patch/0017-zebra-Re-arrange-fpm_read-to-reduce-code-duplication.patch deleted file mode 100755 index 4c392f511118..000000000000 --- a/src/sonic-frr/patch/0017-zebra-Re-arrange-fpm_read-to-reduce-code-duplication.patch +++ /dev/null @@ -1,56 +0,0 @@ -From 88ba9ad950d461847a159b0f4899375ecd23d4b9 Mon Sep 17 00:00:00 2001 -From: Donald Sharp -Date: Wed, 5 Oct 2022 11:28:43 -0400 -Subject: [PATCH 3/8] zebra: Re-arrange fpm_read to reduce code duplication - -Signed-off-by: Donald Sharp ---- - zebra/dplane_fpm_nl.c | 19 +++++++++---------- - 1 file changed, 9 insertions(+), 10 deletions(-) - -diff --git a/zebra/dplane_fpm_nl.c b/zebra/dplane_fpm_nl.c -index 3b02128c9..8d41f3b07 100644 ---- a/zebra/dplane_fpm_nl.c -+++ b/zebra/dplane_fpm_nl.c -@@ -466,13 +466,6 @@ static int fpm_read(struct thread *t) - /* Let's ignore the input at the moment. */ - rv = stream_read_try(fnc->ibuf, fnc->socket, - STREAM_WRITEABLE(fnc->ibuf)); -- /* We've got an interruption. */ -- if (rv == -2) { -- /* Schedule next read. */ -- thread_add_read(fnc->fthread->master, fpm_read, fnc, -- fnc->socket, &fnc->t_read); -- return 0; -- } - if (rv == 0) { - atomic_fetch_add_explicit(&fnc->counters.connection_closes, 1, - memory_order_relaxed); -@@ -491,15 +484,21 @@ static int fpm_read(struct thread *t) - FPM_RECONNECT(fnc); - return 0; - } -+ -+ /* Schedule the next read */ -+ thread_add_read(fnc->fthread->master, fpm_read, fnc, fnc->socket, -+ &fnc->t_read); -+ -+ /* We've got an interruption. */ -+ if (rv == -2) -+ return 0; -+ - stream_reset(fnc->ibuf); - - /* Account all bytes read. */ - atomic_fetch_add_explicit(&fnc->counters.bytes_read, rv, - memory_order_relaxed); - -- thread_add_read(fnc->fthread->master, fpm_read, fnc, fnc->socket, -- &fnc->t_read); -- - return 0; - } - --- -2.30.2 - diff --git a/src/sonic-frr/patch/0018-zebra-Add-dplane_ctx_get-set_flags.patch b/src/sonic-frr/patch/0018-zebra-Add-dplane_ctx_get-set_flags.patch deleted file mode 100755 index a75623cc5b8c..000000000000 --- a/src/sonic-frr/patch/0018-zebra-Add-dplane_ctx_get-set_flags.patch +++ /dev/null @@ -1,78 +0,0 @@ -From 77d430e04359417d6fca8226e256ee2845fbbc58 Mon Sep 17 00:00:00 2001 -From: Donald Sharp -Date: Mon, 3 Oct 2022 15:28:48 -0400 -Subject: [PATCH 4/8] zebra: Add dplane_ctx_get|set_flags - -Zebra needs the ability to pass this data around. -Add it to the dplanes ability to pass. - -Signed-off-by: Donald Sharp - -zebra: Add a dplane_ctx_set_flags - -The dplane_ctx_set_flags call is missing, we will need it. Add it. - -Signed-off-by: Donald Sharp ---- - zebra/zebra_dplane.c | 17 +++++++++++++++++ - zebra/zebra_dplane.h | 2 ++ - 2 files changed, 19 insertions(+) - -diff --git a/zebra/zebra_dplane.c b/zebra/zebra_dplane.c -index 656ebcf3b..5d94e1a0b 100644 ---- a/zebra/zebra_dplane.c -+++ b/zebra/zebra_dplane.c -@@ -132,6 +132,8 @@ struct dplane_route_info { - uint32_t zd_mtu; - uint32_t zd_nexthop_mtu; - -+ uint32_t zd_flags; -+ - /* Nexthop hash entry info */ - struct dplane_nexthop_info nhe; - -@@ -1323,6 +1325,20 @@ uint16_t dplane_ctx_get_old_instance(const struct zebra_dplane_ctx *ctx) - return ctx->u.rinfo.zd_old_instance; - } - -+uint32_t dplane_ctx_get_flags(const struct zebra_dplane_ctx *ctx) -+{ -+ DPLANE_CTX_VALID(ctx); -+ -+ return ctx->u.rinfo.zd_flags; -+} -+ -+void dplane_ctx_set_flags(struct zebra_dplane_ctx *ctx, uint32_t flags) -+{ -+ DPLANE_CTX_VALID(ctx); -+ -+ ctx->u.rinfo.zd_flags = flags; -+} -+ - uint32_t dplane_ctx_get_metric(const struct zebra_dplane_ctx *ctx) - { - DPLANE_CTX_VALID(ctx); -@@ -2358,6 +2374,7 @@ int dplane_ctx_route_init(struct zebra_dplane_ctx *ctx, enum dplane_op_e op, - - ctx->zd_table_id = re->table; - -+ ctx->u.rinfo.zd_flags = re->flags; - ctx->u.rinfo.zd_metric = re->metric; - ctx->u.rinfo.zd_old_metric = re->metric; - ctx->zd_vrf_id = re->vrf_id; -diff --git a/zebra/zebra_dplane.h b/zebra/zebra_dplane.h -index 1d5518138..3210137c0 100644 ---- a/zebra/zebra_dplane.h -+++ b/zebra/zebra_dplane.h -@@ -343,6 +343,8 @@ route_tag_t dplane_ctx_get_old_tag(const struct zebra_dplane_ctx *ctx); - uint16_t dplane_ctx_get_instance(const struct zebra_dplane_ctx *ctx); - void dplane_ctx_set_instance(struct zebra_dplane_ctx *ctx, uint16_t instance); - uint16_t dplane_ctx_get_old_instance(const struct zebra_dplane_ctx *ctx); -+uint32_t dplane_ctx_get_flags(const struct zebra_dplane_ctx *ctx); -+void dplane_ctx_set_flags(struct zebra_dplane_ctx *ctx, uint32_t flags); - uint32_t dplane_ctx_get_metric(const struct zebra_dplane_ctx *ctx); - uint32_t dplane_ctx_get_old_metric(const struct zebra_dplane_ctx *ctx); - uint32_t dplane_ctx_get_mtu(const struct zebra_dplane_ctx *ctx); --- -2.30.2 - diff --git a/src/sonic-frr/patch/0018-zebra-Use-zebra-dplane-for-RTM-link-and-addr.patch b/src/sonic-frr/patch/0018-zebra-Use-zebra-dplane-for-RTM-link-and-addr.patch new file mode 100644 index 000000000000..98f3b224a75e --- /dev/null +++ b/src/sonic-frr/patch/0018-zebra-Use-zebra-dplane-for-RTM-link-and-addr.patch @@ -0,0 +1,2154 @@ +From 2c33b9ab847a53d8006687e89c0cbd589fe7071f Mon Sep 17 00:00:00 2001 +From: Donald Sharp +Date: Wed, 26 Apr 2023 23:02:09 -0400 +Subject: [PATCH] zebra: Use zebra dplane for RTM link and addr + +a) Move the reads of link and address information +into the dplane +b) Move the startup read of data into the dplane +as well. +c) Break up startup reading of the linux kernel data +into multiple phases. As that we have implied ordering +of data that must be read first and if the dplane has +taken over some data reading then we must delay initial +read-in of other data. + +Fixes: #13288 +Signed-off-by: Donald Sharp + +diff --git a/zebra/if_netlink.c b/zebra/if_netlink.c +index ed5b3c4a66..7613f5fcc4 100644 +--- a/zebra/if_netlink.c ++++ b/zebra/if_netlink.c +@@ -79,64 +79,21 @@ + + extern struct zebra_privs_t zserv_privs; + +-/* Note: on netlink systems, there should be a 1-to-1 mapping between interface +- names and ifindex values. */ +-static void set_ifindex(struct interface *ifp, ifindex_t ifi_index, +- struct zebra_ns *zns) +-{ +- struct interface *oifp; +- +- if (((oifp = if_lookup_by_index_per_ns(zns, ifi_index)) != NULL) +- && (oifp != ifp)) { +- if (ifi_index == IFINDEX_INTERNAL) +- flog_err( +- EC_LIB_INTERFACE, +- "Netlink is setting interface %s ifindex to reserved internal value %u", +- ifp->name, ifi_index); +- else { +- if (IS_ZEBRA_DEBUG_KERNEL) +- zlog_debug( +- "interface index %d was renamed from %s to %s", +- ifi_index, oifp->name, ifp->name); +- if (if_is_up(oifp)) +- flog_err( +- EC_LIB_INTERFACE, +- "interface rename detected on up interface: index %d was renamed from %s to %s, results are uncertain!", +- ifi_index, oifp->name, ifp->name); +- if_delete_update(&oifp); +- } +- } +- if_set_index(ifp, ifi_index); +-} +- + /* Utility function to parse hardware link-layer address and update ifp */ + static void netlink_interface_update_hw_addr(struct rtattr **tb, +- struct interface *ifp) ++ struct zebra_dplane_ctx *ctx) + { +- int i; +- + if (tb[IFLA_ADDRESS]) { + int hw_addr_len; + + hw_addr_len = RTA_PAYLOAD(tb[IFLA_ADDRESS]); + + if (hw_addr_len > INTERFACE_HWADDR_MAX) +- zlog_debug("Hardware address is too large: %d", +- hw_addr_len); +- else { +- ifp->hw_addr_len = hw_addr_len; +- memcpy(ifp->hw_addr, RTA_DATA(tb[IFLA_ADDRESS]), +- hw_addr_len); +- +- for (i = 0; i < hw_addr_len; i++) +- if (ifp->hw_addr[i] != 0) +- break; +- +- if (i == hw_addr_len) +- ifp->hw_addr_len = 0; +- else +- ifp->hw_addr_len = hw_addr_len; +- } ++ zlog_warn("Hardware address is too large: %d", ++ hw_addr_len); ++ else ++ dplane_ctx_set_ifp_hw_addr(ctx, hw_addr_len, ++ RTA_DATA(tb[IFLA_ADDRESS])); + } + } + +@@ -251,26 +208,6 @@ static enum zebra_link_type netlink_to_zebra_link_type(unsigned int hwt) + } + } + +-static inline void zebra_if_set_ziftype(struct interface *ifp, +- enum zebra_iftype zif_type, +- enum zebra_slave_iftype zif_slave_type) +-{ +- struct zebra_if *zif; +- +- zif = (struct zebra_if *)ifp->info; +- zif->zif_slave_type = zif_slave_type; +- +- if (zif->zif_type != zif_type) { +- zif->zif_type = zif_type; +- /* If the if_type has been set to bond initialize ES info +- * against it. XXX - note that we don't handle the case where +- * a zif changes from bond to non-bond; it is really +- * an unexpected/error condition. +- */ +- zebra_evpn_if_init(zif); +- } +-} +- + static void netlink_determine_zebra_iftype(const char *kind, + enum zebra_iftype *zif_type) + { +@@ -300,16 +237,11 @@ static void netlink_determine_zebra_iftype(const char *kind, + } + + static void netlink_vrf_change(struct nlmsghdr *h, struct rtattr *tb, +- uint32_t ns_id, const char *name) ++ uint32_t ns_id, const char *name, ++ struct zebra_dplane_ctx *ctx) + { +- struct ifinfomsg *ifi; + struct rtattr *linkinfo[IFLA_INFO_MAX + 1]; + struct rtattr *attr[IFLA_VRF_MAX + 1]; +- struct vrf *vrf = NULL; +- struct zebra_vrf *zvrf; +- uint32_t nl_table_id; +- +- ifi = NLMSG_DATA(h); + + netlink_parse_rtattr_nested(linkinfo, IFLA_INFO_MAX, tb); + +@@ -331,75 +263,8 @@ static void netlink_vrf_change(struct nlmsghdr *h, struct rtattr *tb, + return; + } + +- nl_table_id = *(uint32_t *)RTA_DATA(attr[IFLA_VRF_TABLE]); +- +- if (h->nlmsg_type == RTM_NEWLINK) { +- if (IS_ZEBRA_DEBUG_KERNEL) +- zlog_debug("RTM_NEWLINK for VRF %s(%u) table %u", name, +- ifi->ifi_index, nl_table_id); +- +- if (!vrf_lookup_by_id((vrf_id_t)ifi->ifi_index)) { +- vrf_id_t exist_id; +- +- exist_id = +- zebra_vrf_lookup_by_table(nl_table_id, ns_id); +- if (exist_id != VRF_DEFAULT) { +- vrf = vrf_lookup_by_id(exist_id); +- +- flog_err( +- EC_ZEBRA_VRF_MISCONFIGURED, +- "VRF %s id %u table id overlaps existing vrf %s, misconfiguration exiting", +- name, ifi->ifi_index, vrf->name); +- exit(-1); +- } +- } +- +- vrf = vrf_update((vrf_id_t)ifi->ifi_index, name); +- if (!vrf) { +- flog_err(EC_LIB_INTERFACE, "VRF %s id %u not created", +- name, ifi->ifi_index); +- return; +- } +- +- /* +- * This is the only place that we get the actual kernel table_id +- * being used. We need it to set the table_id of the routes +- * we are passing to the kernel.... And to throw some totally +- * awesome parties. that too. +- * +- * At this point we *must* have a zvrf because the vrf_create +- * callback creates one. We *must* set the table id +- * before the vrf_enable because of( at the very least ) +- * static routes being delayed for installation until +- * during the vrf_enable callbacks. +- */ +- zvrf = (struct zebra_vrf *)vrf->info; +- zvrf->table_id = nl_table_id; +- +- /* Enable the created VRF. */ +- if (!vrf_enable(vrf)) { +- flog_err(EC_LIB_INTERFACE, +- "Failed to enable VRF %s id %u", name, +- ifi->ifi_index); +- return; +- } +- +- } else // h->nlmsg_type == RTM_DELLINK +- { +- if (IS_ZEBRA_DEBUG_KERNEL) +- zlog_debug("RTM_DELLINK for VRF %s(%u)", name, +- ifi->ifi_index); +- +- vrf = vrf_lookup_by_id((vrf_id_t)ifi->ifi_index); +- +- if (!vrf) { +- flog_warn(EC_ZEBRA_VRF_NOT_FOUND, "%s: vrf not found", +- __func__); +- return; +- } +- +- vrf_delete(vrf); +- } ++ dplane_ctx_set_ifp_table_id( ++ ctx, *(uint32_t *)RTA_DATA(attr[IFLA_VRF_TABLE])); + } + + static uint32_t get_iflink_speed(struct interface *interface, int *error) +@@ -659,58 +524,120 @@ static int netlink_extract_vxlan_info(struct rtattr *link_data, + * bridge interface is added or updated, take further actions to map + * its members. Likewise, for VxLAN interface. + */ +-static void netlink_interface_update_l2info(struct interface *ifp, ++static void netlink_interface_update_l2info(struct zebra_dplane_ctx *ctx, ++ enum zebra_iftype zif_type, + struct rtattr *link_data, int add, + ns_id_t link_nsid) + { ++ struct zebra_l2info_bridge bridge_info; ++ struct zebra_l2info_vlan vlan_info; ++ struct zebra_l2info_vxlan vxlan_info; ++ struct zebra_l2info_gre gre_info; ++ + if (!link_data) + return; + +- if (IS_ZEBRA_IF_BRIDGE(ifp)) { +- struct zebra_l2info_bridge bridge_info; +- ++ switch (zif_type) { ++ case ZEBRA_IF_BRIDGE: + netlink_extract_bridge_info(link_data, &bridge_info); +- zebra_l2_bridge_add_update(ifp, &bridge_info); +- } else if (IS_ZEBRA_IF_VLAN(ifp)) { +- struct zebra_l2info_vlan vlan_info; +- ++ dplane_ctx_set_ifp_bridge_info(ctx, &bridge_info); ++ break; ++ case ZEBRA_IF_VLAN: + netlink_extract_vlan_info(link_data, &vlan_info); +- zebra_l2_vlanif_update(ifp, &vlan_info); +- zebra_evpn_acc_bd_svi_set(ifp->info, NULL, +- !!if_is_operative(ifp)); +- } else if (IS_ZEBRA_IF_VXLAN(ifp)) { +- struct zebra_l2info_vxlan vxlan_info; +- ++ dplane_ctx_set_ifp_vlan_info(ctx, &vlan_info); ++ break; ++ case ZEBRA_IF_VXLAN: + netlink_extract_vxlan_info(link_data, &vxlan_info); + vxlan_info.link_nsid = link_nsid; +- zebra_l2_vxlanif_add_update(ifp, &vxlan_info, add); +- if (link_nsid != NS_UNKNOWN && +- vxlan_info.ifindex_link) +- zebra_if_update_link(ifp, vxlan_info.ifindex_link, +- link_nsid); +- } else if (IS_ZEBRA_IF_GRE(ifp)) { +- struct zebra_l2info_gre gre_info; +- ++ dplane_ctx_set_ifp_vxlan_info(ctx, &vxlan_info); ++ break; ++ case ZEBRA_IF_GRE: + netlink_extract_gre_info(link_data, &gre_info); + gre_info.link_nsid = link_nsid; +- zebra_l2_greif_add_update(ifp, &gre_info, add); +- if (link_nsid != NS_UNKNOWN && +- gre_info.ifindex_link) +- zebra_if_update_link(ifp, gre_info.ifindex_link, +- link_nsid); ++ dplane_ctx_set_ifp_gre_info(ctx, &gre_info); ++ break; ++ case ZEBRA_IF_OTHER: ++ case ZEBRA_IF_VRF: ++ case ZEBRA_IF_MACVLAN: ++ case ZEBRA_IF_VETH: ++ case ZEBRA_IF_BOND: ++ case ZEBRA_IF_BOND_SLAVE: ++ break; + } + } + +-static int netlink_bridge_vxlan_update(struct interface *ifp, +- struct rtattr *af_spec) ++#if 0 ++static int ++netlink_bridge_vxlan_vlan_vni_map_update(struct zebra_dplane_ctx *ctx, ++ struct rtattr *af_spec) ++{ ++ int rem; ++ uint16_t flags; ++ struct rtattr *i; ++ struct zebra_vxlan_vni_array *vniarray = NULL; ++ struct zebra_vxlan_vni vni_end; ++ struct zebra_vxlan_vni vni_start; ++ struct rtattr *aftb[IFLA_BRIDGE_VLAN_TUNNEL_MAX + 1]; ++ int32_t count = 0; ++ ++ memset(&vni_start, 0, sizeof(vni_start)); ++ memset(&vni_end, 0, sizeof(vni_end)); ++ ++ for (i = RTA_DATA(af_spec), rem = RTA_PAYLOAD(af_spec); RTA_OK(i, rem); ++ i = RTA_NEXT(i, rem)) { ++ ++ if (i->rta_type != IFLA_BRIDGE_VLAN_TUNNEL_INFO) ++ continue; ++ ++ memset(aftb, 0, sizeof(aftb)); ++ netlink_parse_rtattr_nested(aftb, IFLA_BRIDGE_VLAN_TUNNEL_MAX, ++ i); ++ if (!aftb[IFLA_BRIDGE_VLAN_TUNNEL_ID] || ++ !aftb[IFLA_BRIDGE_VLAN_TUNNEL_VID]) ++ /* vlan-vni info missing */ ++ return 0; ++ ++ count++; ++ flags = 0; ++ vniarray = XREALLOC( ++ MTYPE_TMP, vniarray, ++ sizeof(struct zebra_vxlan_vni_array) + ++ count * sizeof(struct zebra_vxlan_vni)); ++ ++ memset(&vniarray->vnis[count - 1], 0, ++ sizeof(struct zebra_vxlan_vni)); ++ ++ vniarray->vnis[count - 1].vni = ++ *(vni_t *)RTA_DATA(aftb[IFLA_BRIDGE_VLAN_TUNNEL_ID]); ++ vniarray->vnis[count - 1].access_vlan = *(vlanid_t *)RTA_DATA( ++ aftb[IFLA_BRIDGE_VLAN_TUNNEL_VID]); ++ ++ if (aftb[IFLA_BRIDGE_VLAN_TUNNEL_FLAGS]) ++ flags = *(uint16_t *)RTA_DATA( ++ aftb[IFLA_BRIDGE_VLAN_TUNNEL_FLAGS]); ++ ++ vniarray->vnis[count - 1].flags = flags; ++ } ++ ++ if (count) { ++ vniarray->count = count; ++ dplane_ctx_set_ifp_vxlan_vni_array(ctx, vniarray); ++ } ++ return 0; ++} ++#endif ++static int netlink_bridge_vxlan_update(struct zebra_dplane_ctx *ctx, ++ struct rtattr *af_spec) + { + struct rtattr *aftb[IFLA_BRIDGE_MAX + 1]; + struct bridge_vlan_info *vinfo; +- vlanid_t access_vlan; ++ struct zebra_dplane_bridge_vlan_info bvinfo; + + if (!af_spec) + return 0; + ++ //netlink_bridge_vxlan_vlan_vni_map_update(ctx, af_spec); ++ + /* There is a 1-to-1 mapping of VLAN to VxLAN - hence + * only 1 access VLAN is accepted. + */ +@@ -719,119 +646,73 @@ static int netlink_bridge_vxlan_update(struct interface *ifp, + return 0; + + vinfo = RTA_DATA(aftb[IFLA_BRIDGE_VLAN_INFO]); +- if (!(vinfo->flags & BRIDGE_VLAN_INFO_PVID)) +- return 0; ++ bvinfo.flags = vinfo->flags; ++ bvinfo.vid = vinfo->vid; + +- access_vlan = (vlanid_t)vinfo->vid; +- if (IS_ZEBRA_DEBUG_KERNEL) +- zlog_debug("Access VLAN %u for VxLAN IF %s(%u)", access_vlan, +- ifp->name, ifp->ifindex); +- zebra_l2_vxlanif_update_access_vlan(ifp, access_vlan); ++ dplane_ctx_set_ifp_bridge_vlan_info(ctx, &bvinfo); + return 0; + } + +-static void netlink_bridge_vlan_update(struct interface *ifp, +- struct rtattr *af_spec) ++static void netlink_bridge_vlan_update(struct zebra_dplane_ctx *ctx, ++ struct rtattr *af_spec) + { + struct rtattr *i; + int rem; +- uint16_t vid_range_start = 0; +- struct zebra_if *zif; +- bitfield_t old_vlan_bitmap; + struct bridge_vlan_info *vinfo; +- +- zif = (struct zebra_if *)ifp->info; +- +- /* cache the old bitmap addrs */ +- old_vlan_bitmap = zif->vlan_bitmap; +- /* create a new bitmap space for re-eval */ +- bf_init(zif->vlan_bitmap, IF_VLAN_BITMAP_MAX); ++ struct zebra_dplane_bridge_vlan_info_array *bvarray = NULL; ++ int32_t count = 0; + + if (af_spec) { + for (i = RTA_DATA(af_spec), rem = RTA_PAYLOAD(af_spec); + RTA_OK(i, rem); i = RTA_NEXT(i, rem)) { +- + if (i->rta_type != IFLA_BRIDGE_VLAN_INFO) + continue; + +- vinfo = RTA_DATA(i); +- +- if (vinfo->flags & BRIDGE_VLAN_INFO_RANGE_BEGIN) { +- vid_range_start = vinfo->vid; +- continue; +- } ++ count++; ++ bvarray = XREALLOC( ++ MTYPE_TMP, bvarray, ++ sizeof(struct ++ zebra_dplane_bridge_vlan_info_array) + ++ count * sizeof(struct ++ zebra_dplane_bridge_vlan_info)); + +- if (!(vinfo->flags & BRIDGE_VLAN_INFO_RANGE_END)) +- vid_range_start = vinfo->vid; +- +- zebra_vlan_bitmap_compute(ifp, vid_range_start, +- vinfo->vid); ++ vinfo = RTA_DATA(i); ++ bvarray->array[count - 1].flags = vinfo->flags; ++ bvarray->array[count - 1].vid = vinfo->vid; + } + } + +- zebra_vlan_mbr_re_eval(ifp, old_vlan_bitmap); +- +- bf_free(old_vlan_bitmap); ++ if (count) { ++ bvarray->count = count; ++ dplane_ctx_set_ifp_bridge_vlan_info_array(ctx, bvarray); ++ } + } + +-static int netlink_bridge_interface(struct nlmsghdr *h, int len, ns_id_t ns_id, +- int startup) ++static int netlink_bridge_interface(struct zebra_dplane_ctx *ctx, ++ struct rtattr *af_spec, int startup) + { +- char *name = NULL; +- struct ifinfomsg *ifi; +- struct rtattr *tb[IFLA_MAX + 1]; +- struct interface *ifp; +- struct zebra_if *zif; +- struct rtattr *af_spec; + +- /* Fetch name and ifindex */ +- ifi = NLMSG_DATA(h); +- netlink_parse_rtattr(tb, IFLA_MAX, IFLA_RTA(ifi), len); +- +- if (tb[IFLA_IFNAME] == NULL) +- return -1; +- name = (char *)RTA_DATA(tb[IFLA_IFNAME]); +- +- /* The interface should already be known, if not discard. */ +- ifp = if_lookup_by_index_per_ns(zebra_ns_lookup(ns_id), ifi->ifi_index); +- if (!ifp) { +- zlog_debug("Cannot find bridge IF %s(%u)", name, +- ifi->ifi_index); +- return 0; +- } +- +- /* We are only interested in the access VLAN i.e., AF_SPEC */ +- af_spec = tb[IFLA_AF_SPEC]; +- +- if (IS_ZEBRA_IF_VXLAN(ifp)) +- return netlink_bridge_vxlan_update(ifp, af_spec); ++ netlink_bridge_vxlan_update(ctx, af_spec); + + /* build vlan bitmap associated with this interface if that + * device type is interested in the vlans + */ +- zif = (struct zebra_if *)ifp->info; +- if (bf_is_inited(zif->vlan_bitmap)) +- netlink_bridge_vlan_update(ifp, af_spec); ++ netlink_bridge_vlan_update(ctx, af_spec); + ++ dplane_provider_enqueue_to_zebra(ctx); + return 0; + } + +-static bool is_if_protodown_reason_only_frr(uint32_t rc_bitfield) +-{ +- return (rc_bitfield == (((uint32_t)1) << if_netlink_get_frr_protodown_r_bit())); +-} +- + /* + * Process interface protodown dplane update. + * + * If the interface is an es bond member then it must follow EVPN's + * protodown setting. + */ +-static void netlink_proc_dplane_if_protodown(struct zebra_if *zif, ++static void netlink_proc_dplane_if_protodown(struct zebra_dplane_ctx *ctx, + struct rtattr **tb) + { + bool protodown; +- bool old_protodown; + uint32_t rc_bitfield = 0; + struct rtattr *pd_reason_info[IFLA_MAX + 1]; + +@@ -846,59 +727,9 @@ static void netlink_proc_dplane_if_protodown(struct zebra_if *zif, + pd_reason_info[IFLA_PROTO_DOWN_REASON_VALUE]); + } + +- /* +- * Set our reason code to note it wasn't us. +- * If the reason we got from the kernel is ONLY frr though, don't +- * set it. +- */ +- COND_FLAG(zif->protodown_rc, ZEBRA_PROTODOWN_EXTERNAL, +- protodown && rc_bitfield && +- !is_if_protodown_reason_only_frr(rc_bitfield)); +- +- +- old_protodown = !!ZEBRA_IF_IS_PROTODOWN(zif); +- if (protodown == old_protodown) +- return; +- +- if (IS_ZEBRA_DEBUG_EVPN_MH_ES || IS_ZEBRA_DEBUG_KERNEL) +- zlog_debug("interface %s dplane change, protdown %s", +- zif->ifp->name, protodown ? "on" : "off"); +- +- /* Set protodown, respectively */ +- COND_FLAG(zif->flags, ZIF_FLAG_PROTODOWN, protodown); +- +- if (zebra_evpn_is_es_bond_member(zif->ifp)) { +- /* Check it's not already being sent to the dplane first */ +- if (protodown && +- CHECK_FLAG(zif->flags, ZIF_FLAG_SET_PROTODOWN)) { +- if (IS_ZEBRA_DEBUG_EVPN_MH_ES || IS_ZEBRA_DEBUG_KERNEL) +- zlog_debug( +- "bond mbr %s protodown on recv'd but already sent protodown on to the dplane", +- zif->ifp->name); +- return; +- } +- +- if (!protodown && +- CHECK_FLAG(zif->flags, ZIF_FLAG_UNSET_PROTODOWN)) { +- if (IS_ZEBRA_DEBUG_EVPN_MH_ES || IS_ZEBRA_DEBUG_KERNEL) +- zlog_debug( +- "bond mbr %s protodown off recv'd but already sent protodown off to the dplane", +- zif->ifp->name); +- return; +- } +- +- if (IS_ZEBRA_DEBUG_EVPN_MH_ES || IS_ZEBRA_DEBUG_KERNEL) +- zlog_debug( +- "bond mbr %s reinstate protodown %s in the dplane", +- zif->ifp->name, old_protodown ? "on" : "off"); +- +- if (old_protodown) +- SET_FLAG(zif->flags, ZIF_FLAG_SET_PROTODOWN); +- else +- SET_FLAG(zif->flags, ZIF_FLAG_UNSET_PROTODOWN); +- +- dplane_intf_update(zif->ifp); +- } ++ dplane_ctx_set_ifp_rc_bitfield(ctx, rc_bitfield); ++ dplane_ctx_set_ifp_protodown(ctx, protodown); ++ dplane_ctx_set_ifp_protodown_set(ctx, true); + } + + static uint8_t netlink_parse_lacp_bypass(struct rtattr **linkinfo) +@@ -915,29 +746,6 @@ static uint8_t netlink_parse_lacp_bypass(struct rtattr **linkinfo) + return bypass; + } + +-/* +- * Only called at startup to cleanup leftover protodown reasons we may +- * have not cleaned up. We leave protodown set though. +- */ +-static void if_sweep_protodown(struct zebra_if *zif) +-{ +- bool protodown; +- +- protodown = !!ZEBRA_IF_IS_PROTODOWN(zif); +- +- if (!protodown) +- return; +- +- if (IS_ZEBRA_DEBUG_KERNEL) +- zlog_debug("interface %s sweeping protodown %s reason 0x%x", +- zif->ifp->name, protodown ? "on" : "off", +- zif->protodown_rc); +- +- /* Only clear our reason codes, leave external if it was set */ +- UNSET_FLAG(zif->protodown_rc, ZEBRA_PROTODOWN_ALL); +- dplane_intf_update(zif->ifp); +-} +- + /* Request for specific interface or address information from the kernel */ + static int netlink_request_intf_addr(struct nlsock *netlink_cmd, int family, + int type, uint32_t filter_mask) +@@ -984,7 +792,7 @@ int interface_lookup_netlink(struct zebra_ns *zns) + { + int ret; + struct zebra_dplane_info dp_info; +- struct nlsock *netlink_cmd = &zns->netlink_cmd; ++ struct nlsock *netlink_cmd = &zns->netlink_dplane_out; + + /* Capture key info from ns struct */ + zebra_dplane_info_from_zns(&dp_info, zns, true /*is_cmd*/); +@@ -1008,6 +816,13 @@ int interface_lookup_netlink(struct zebra_ns *zns) + if (ret < 0) + return ret; + ++ return ret; ++} ++ ++void interface_list_tunneldump(struct zebra_ns *zns) ++{ ++ int ret; ++ + /* + * So netlink_tunneldump_read will initiate a request + * per tunnel to get data. If we are on a kernel that +@@ -1020,13 +835,12 @@ int interface_lookup_netlink(struct zebra_ns *zns) + */ + ret = netlink_tunneldump_read(zns); + if (ret < 0) +- return ret; ++ return; + +- /* fixup linkages */ +- zebra_if_update_all_links(zns); +- return 0; ++ zebra_dplane_startup_stage(zns, ZEBRA_DPLANE_TUNNELS_READ); + } + ++ + /** + * interface_addr_lookup_netlink() - Look up interface addresses + * +@@ -1046,8 +860,8 @@ static int interface_addr_lookup_netlink(struct zebra_ns *zns) + ret = netlink_request_intf_addr(netlink_cmd, AF_INET, RTM_GETADDR, 0); + if (ret < 0) + return ret; +- ret = netlink_parse_info(netlink_interface_addr, netlink_cmd, &dp_info, +- 0, true); ++ ret = netlink_parse_info(netlink_interface_addr_dplane, netlink_cmd, ++ &dp_info, 0, true); + if (ret < 0) + return ret; + +@@ -1055,8 +869,8 @@ static int interface_addr_lookup_netlink(struct zebra_ns *zns) + ret = netlink_request_intf_addr(netlink_cmd, AF_INET6, RTM_GETADDR, 0); + if (ret < 0) + return ret; +- ret = netlink_parse_info(netlink_interface_addr, netlink_cmd, &dp_info, +- 0, true); ++ ret = netlink_parse_info(netlink_interface_addr_dplane, netlink_cmd, ++ &dp_info, 0, true); + if (ret < 0) + return ret; + +@@ -1616,7 +1430,6 @@ int netlink_interface_addr_dplane(struct nlmsghdr *h, ns_id_t ns_id, + + /* Enqueue ctx for main pthread to process */ + dplane_provider_enqueue_to_zebra(ctx); +- + return 0; + } + +@@ -1626,27 +1439,21 @@ int netlink_link_change(struct nlmsghdr *h, ns_id_t ns_id, int startup) + struct ifinfomsg *ifi; + struct rtattr *tb[IFLA_MAX + 1]; + struct rtattr *linkinfo[IFLA_MAX + 1]; +- struct interface *ifp; + char *name = NULL; + char *kind = NULL; +- char *desc = NULL; + char *slave_kind = NULL; +- struct zebra_ns *zns; + vrf_id_t vrf_id = VRF_DEFAULT; + enum zebra_iftype zif_type = ZEBRA_IF_OTHER; + enum zebra_slave_iftype zif_slave_type = ZEBRA_IF_SLAVE_NONE; + ifindex_t bridge_ifindex = IFINDEX_INTERNAL; + ifindex_t bond_ifindex = IFINDEX_INTERNAL; + ifindex_t link_ifindex = IFINDEX_INTERNAL; +- uint8_t old_hw_addr[INTERFACE_HWADDR_MAX]; +- struct zebra_if *zif; + ns_id_t link_nsid = ns_id; + ifindex_t master_infindex = IFINDEX_INTERNAL; + uint8_t bypass = 0; + + frrtrace(3, frr_zebra, netlink_interface, h, ns_id, startup); + +- zns = zebra_ns_lookup(ns_id); + ifi = NLMSG_DATA(h); + + /* assume if not default zns, then new VRF */ +@@ -1675,10 +1482,6 @@ int netlink_link_change(struct nlmsghdr *h, ns_id_t ns_id, int startup) + return -1; + } + +- /* We are interested in some AF_BRIDGE notifications. */ +- if (ifi->ifi_family == AF_BRIDGE) +- return netlink_bridge_interface(h, len, ns_id, startup); +- + /* Looking up interface name. */ + memset(linkinfo, 0, sizeof(linkinfo)); + netlink_parse_rtattr_flags(tb, IFLA_MAX, IFLA_RTA(ifi), len, +@@ -1728,18 +1531,47 @@ int netlink_link_change(struct nlmsghdr *h, ns_id_t ns_id, int startup) + link_nsid = *(ns_id_t *)RTA_DATA(tb[IFLA_LINK_NETNSID]); + link_nsid = ns_id_get_absolute(ns_id, link_nsid); + } +- if (tb[IFLA_IFALIAS]) { +- desc = (char *)RTA_DATA(tb[IFLA_IFALIAS]); +- } + +- /* See if interface is present. */ +- ifp = if_lookup_by_name_per_ns(zns, name); ++ struct zebra_dplane_ctx *ctx = dplane_ctx_alloc(); ++ dplane_ctx_set_ns_id(ctx, ns_id); ++ dplane_ctx_set_ifp_link_nsid(ctx, link_nsid); ++ dplane_ctx_set_ifp_zif_type(ctx, zif_type); ++ dplane_ctx_set_ifindex(ctx, ifi->ifi_index); ++ dplane_ctx_set_ifname(ctx, name); ++ dplane_ctx_set_ifp_startup(ctx, startup); ++ dplane_ctx_set_ifp_family(ctx, ifi->ifi_family); ++ ++ /* We are interested in some AF_BRIDGE notifications. */ ++#ifndef AF_BRIDGE ++#define AF_BRIDGE 7 ++#endif ++ if (ifi->ifi_family == AF_BRIDGE) { ++ dplane_ctx_set_op(ctx, DPLANE_OP_INTF_INSTALL); ++ return netlink_bridge_interface(ctx, tb[IFLA_AF_SPEC], startup); ++ } + + if (h->nlmsg_type == RTM_NEWLINK) { ++ dplane_ctx_set_ifp_link_ifindex(ctx, link_ifindex); ++ dplane_ctx_set_op(ctx, DPLANE_OP_INTF_INSTALL); ++ dplane_ctx_set_status(ctx, ZEBRA_DPLANE_REQUEST_QUEUED); ++ if (tb[IFLA_IFALIAS]) { ++ dplane_ctx_set_ifp_desc(ctx, ++ RTA_DATA(tb[IFLA_IFALIAS])); ++ } ++ if (!tb[IFLA_MTU]) { ++ if (IS_ZEBRA_DEBUG_KERNEL) ++ zlog_debug( ++ "RTM_NEWLINK for interface %s(%u) without MTU set", ++ name, ifi->ifi_index); ++ return 0; ++ } ++ dplane_ctx_set_ifp_mtu(ctx, *(int *)RTA_DATA(tb[IFLA_MTU])); ++ + /* If VRF, create or update the VRF structure itself. */ + if (zif_type == ZEBRA_IF_VRF && !vrf_is_backend_netns()) { +- netlink_vrf_change(h, tb[IFLA_LINKINFO], ns_id, name); +- vrf_id = (vrf_id_t)ifi->ifi_index; ++ netlink_vrf_change(h, tb[IFLA_LINKINFO], ns_id, name, ++ ctx); ++ vrf_id = ifi->ifi_index; + } + + if (tb[IFLA_MASTER]) { +@@ -1762,279 +1594,45 @@ int netlink_link_change(struct nlmsghdr *h, ns_id_t ns_id, int startup) + } else + zif_slave_type = ZEBRA_IF_SLAVE_OTHER; + } ++ dplane_ctx_set_ifp_zif_slave_type(ctx, zif_slave_type); ++ dplane_ctx_set_ifp_vrf_id(ctx, vrf_id); ++ dplane_ctx_set_ifp_master_ifindex(ctx, master_infindex); ++ dplane_ctx_set_ifp_bridge_ifindex(ctx, bridge_ifindex); ++ dplane_ctx_set_ifp_bond_ifindex(ctx, bond_ifindex); ++ dplane_ctx_set_ifp_bypass(ctx, bypass); ++ dplane_ctx_set_ifp_zltype( ++ ctx, netlink_to_zebra_link_type(ifi->ifi_type)); ++ + if (vrf_is_backend_netns()) +- vrf_id = (vrf_id_t)ns_id; +- if (ifp == NULL +- || !CHECK_FLAG(ifp->status, ZEBRA_INTERFACE_ACTIVE)) { +- /* Add interface notification from kernel */ +- if (IS_ZEBRA_DEBUG_KERNEL) +- zlog_debug( +- "RTM_NEWLINK ADD for %s(%u) vrf_id %u type %d sl_type %d master %u flags 0x%x", +- name, ifi->ifi_index, vrf_id, zif_type, +- zif_slave_type, master_infindex, +- ifi->ifi_flags); +- +- if (ifp == NULL) { +- /* unknown interface */ +- ifp = if_get_by_name(name, vrf_id, NULL); +- } else { +- /* pre-configured interface, learnt now */ +- if (ifp->vrf->vrf_id != vrf_id) +- if_update_to_new_vrf(ifp, vrf_id); +- } +- +- /* Update interface information. */ +- set_ifindex(ifp, ifi->ifi_index, zns); +- ifp->flags = ifi->ifi_flags & 0x0000fffff; +- if (!tb[IFLA_MTU]) { +- zlog_debug( +- "RTM_NEWLINK for interface %s(%u) without MTU set", +- name, ifi->ifi_index); +- return 0; +- } +- ifp->mtu6 = ifp->mtu = *(int *)RTA_DATA(tb[IFLA_MTU]); +- ifp->metric = 0; +- ifp->speed = get_iflink_speed(ifp, NULL); +- ifp->ptm_status = ZEBRA_PTM_STATUS_UNKNOWN; +- +- /* Set interface type */ +- zebra_if_set_ziftype(ifp, zif_type, zif_slave_type); +- if (IS_ZEBRA_IF_VRF(ifp)) +- SET_FLAG(ifp->status, +- ZEBRA_INTERFACE_VRF_LOOPBACK); +- +- /* Update link. */ +- zebra_if_update_link(ifp, link_ifindex, link_nsid); +- +- /* +- * Just set the @link/lower-device ifindex. During +- * nldump interfaces are not ordered in any fashion so +- * we may end up getting upper devices before lower +- * devices. We will setup the real linkage once the dump +- * is complete. +- */ +- zif = (struct zebra_if *)ifp->info; +- zif->link_ifindex = link_ifindex; +- +- ifp->ll_type = +- netlink_to_zebra_link_type(ifi->ifi_type); +- netlink_interface_update_hw_addr(tb, ifp); +- +- /* Inform clients, install any configured addresses. */ +- if_add_update(ifp); +- +- /* Extract and save L2 interface information, take +- * additional actions. */ +- netlink_interface_update_l2info( +- ifp, linkinfo[IFLA_INFO_DATA], +- 1, link_nsid); +- if (IS_ZEBRA_IF_BOND(ifp)) +- zebra_l2if_update_bond(ifp, true); +- if (IS_ZEBRA_IF_BRIDGE_SLAVE(ifp)) +- zebra_l2if_update_bridge_slave( +- ifp, bridge_ifindex, ns_id, +- ZEBRA_BRIDGE_NO_ACTION); +- else if (IS_ZEBRA_IF_BOND_SLAVE(ifp)) +- zebra_l2if_update_bond_slave(ifp, bond_ifindex, +- !!bypass); +- +- if (tb[IFLA_PROTO_DOWN]) { +- netlink_proc_dplane_if_protodown(ifp->info, tb); +- if (startup) +- if_sweep_protodown(zif); +- } +- if (IS_ZEBRA_IF_BRIDGE(ifp)) { +- if (IS_ZEBRA_DEBUG_KERNEL) +- zlog_debug( +- "RTM_NEWLINK ADD for %s(%u), vlan-aware %d", +- name, ifp->ifindex, +- IS_ZEBRA_IF_BRIDGE_VLAN_AWARE( +- zif)); +- } +- } else if (ifp->vrf->vrf_id != vrf_id) { +- /* VRF change for an interface. */ +- if (IS_ZEBRA_DEBUG_KERNEL) +- zlog_debug( +- "RTM_NEWLINK vrf-change for %s(%u) vrf_id %u -> %u flags 0x%x", +- name, ifp->ifindex, ifp->vrf->vrf_id, +- vrf_id, ifi->ifi_flags); ++ dplane_ctx_set_ifp_vrf_id(ctx, ns_id); + +- if_handle_vrf_change(ifp, vrf_id); +- } else { +- bool was_bridge_slave, was_bond_slave; +- uint8_t chgflags = ZEBRA_BRIDGE_NO_ACTION; +- zif = ifp->info; ++ dplane_ctx_set_ifp_flags(ctx, ifi->ifi_flags & 0x0000fffff); + +- /* Interface update. */ +- if (IS_ZEBRA_DEBUG_KERNEL) +- zlog_debug( +- "RTM_NEWLINK update for %s(%u) sl_type %d master %u flags 0x%x", +- name, ifp->ifindex, zif_slave_type, +- master_infindex, ifi->ifi_flags); ++ if (tb[IFLA_PROTO_DOWN]) { ++ dplane_ctx_set_ifp_protodown_set(ctx, true); ++ netlink_proc_dplane_if_protodown(ctx, tb); ++ } else ++ dplane_ctx_set_ifp_protodown_set(ctx, false); + +- set_ifindex(ifp, ifi->ifi_index, zns); +- if (!tb[IFLA_MTU]) { +- zlog_debug( +- "RTM_NEWLINK for interface %s(%u) without MTU set", +- name, ifi->ifi_index); +- return 0; +- } +- ifp->mtu6 = ifp->mtu = *(int *)RTA_DATA(tb[IFLA_MTU]); +- ifp->metric = 0; +- +- /* Update interface type - NOTE: Only slave_type can +- * change. */ +- was_bridge_slave = IS_ZEBRA_IF_BRIDGE_SLAVE(ifp); +- was_bond_slave = IS_ZEBRA_IF_BOND_SLAVE(ifp); +- zebra_if_set_ziftype(ifp, zif_type, zif_slave_type); +- +- memcpy(old_hw_addr, ifp->hw_addr, INTERFACE_HWADDR_MAX); +- +- /* Update link. */ +- zebra_if_update_link(ifp, link_ifindex, link_nsid); +- +- ifp->ll_type = +- netlink_to_zebra_link_type(ifi->ifi_type); +- netlink_interface_update_hw_addr(tb, ifp); +- +- if (tb[IFLA_PROTO_DOWN]) +- netlink_proc_dplane_if_protodown(ifp->info, tb); +- +- if (if_is_no_ptm_operative(ifp)) { +- bool is_up = if_is_operative(ifp); +- ifp->flags = ifi->ifi_flags & 0x0000fffff; +- if (!if_is_no_ptm_operative(ifp) || +- CHECK_FLAG(zif->flags, +- ZIF_FLAG_PROTODOWN)) { +- if (IS_ZEBRA_DEBUG_KERNEL) +- zlog_debug( +- "Intf %s(%u) has gone DOWN", +- name, ifp->ifindex); +- if_down(ifp); +- rib_update(RIB_UPDATE_KERNEL); +- } else if (if_is_operative(ifp)) { +- bool mac_updated = false; +- +- /* Must notify client daemons of new +- * interface status. */ +- if (IS_ZEBRA_DEBUG_KERNEL) +- zlog_debug( +- "Intf %s(%u) PTM up, notifying clients", +- name, ifp->ifindex); +- if_up(ifp, !is_up); +- +- /* Update EVPN VNI when SVI MAC change +- */ +- if (memcmp(old_hw_addr, ifp->hw_addr, +- INTERFACE_HWADDR_MAX)) +- mac_updated = true; +- if (IS_ZEBRA_IF_VLAN(ifp) +- && mac_updated) { +- struct interface *link_if; +- +- link_if = +- if_lookup_by_index_per_ns( +- zebra_ns_lookup(NS_DEFAULT), +- link_ifindex); +- if (link_if) +- zebra_vxlan_svi_up(ifp, +- link_if); +- } else if (mac_updated +- && IS_ZEBRA_IF_BRIDGE(ifp)) { +- zlog_debug( +- "Intf %s(%u) bridge changed MAC address", +- name, ifp->ifindex); +- chgflags = +- ZEBRA_BRIDGE_MASTER_MAC_CHANGE; +- } +- } +- } else { +- ifp->flags = ifi->ifi_flags & 0x0000fffff; +- if (if_is_operative(ifp) && +- !CHECK_FLAG(zif->flags, +- ZIF_FLAG_PROTODOWN)) { +- if (IS_ZEBRA_DEBUG_KERNEL) +- zlog_debug( +- "Intf %s(%u) has come UP", +- name, ifp->ifindex); +- if_up(ifp, true); +- if (IS_ZEBRA_IF_BRIDGE(ifp)) +- chgflags = +- ZEBRA_BRIDGE_MASTER_UP; +- } else { +- if (IS_ZEBRA_DEBUG_KERNEL) +- zlog_debug( +- "Intf %s(%u) has gone DOWN", +- name, ifp->ifindex); +- if_down(ifp); +- rib_update(RIB_UPDATE_KERNEL); +- } +- } +- +- /* Extract and save L2 interface information, take +- * additional actions. */ +- netlink_interface_update_l2info( +- ifp, linkinfo[IFLA_INFO_DATA], +- 0, link_nsid); +- if (IS_ZEBRA_IF_BRIDGE(ifp)) +- zebra_l2if_update_bridge(ifp, chgflags); +- if (IS_ZEBRA_IF_BOND(ifp)) +- zebra_l2if_update_bond(ifp, true); +- if (IS_ZEBRA_IF_BRIDGE_SLAVE(ifp) || was_bridge_slave) +- zebra_l2if_update_bridge_slave( +- ifp, bridge_ifindex, ns_id, chgflags); +- else if (IS_ZEBRA_IF_BOND_SLAVE(ifp) || was_bond_slave) +- zebra_l2if_update_bond_slave(ifp, bond_ifindex, +- !!bypass); +- if (IS_ZEBRA_IF_BRIDGE(ifp)) { +- if (IS_ZEBRA_DEBUG_KERNEL) +- zlog_debug( +- "RTM_NEWLINK update for %s(%u), vlan-aware %d", +- name, ifp->ifindex, +- IS_ZEBRA_IF_BRIDGE_VLAN_AWARE( +- zif)); +- } +- } ++ netlink_interface_update_hw_addr(tb, ctx); + +- zif = ifp->info; +- if (zif) { +- XFREE(MTYPE_ZIF_DESC, zif->desc); +- if (desc) +- zif->desc = XSTRDUP(MTYPE_ZIF_DESC, desc); +- } ++ /* Extract and save L2 interface information, take ++ * additional actions. */ ++ netlink_interface_update_l2info( ++ ctx, zif_type, linkinfo[IFLA_INFO_DATA], 1, link_nsid); + } else { +- /* Delete interface notification from kernel */ +- if (ifp == NULL) { +- if (IS_ZEBRA_DEBUG_KERNEL) +- zlog_debug( +- "RTM_DELLINK for unknown interface %s(%u)", +- name, ifi->ifi_index); +- return 0; +- } +- + if (IS_ZEBRA_DEBUG_KERNEL) +- zlog_debug("RTM_DELLINK for %s(%u)", name, +- ifp->ifindex); +- +- UNSET_FLAG(ifp->status, ZEBRA_INTERFACE_VRF_LOOPBACK); +- +- if (IS_ZEBRA_IF_BOND(ifp)) +- zebra_l2if_update_bond(ifp, false); +- if (IS_ZEBRA_IF_BOND_SLAVE(ifp)) +- zebra_l2if_update_bond_slave(ifp, bond_ifindex, false); +- /* Special handling for bridge or VxLAN interfaces. */ +- if (IS_ZEBRA_IF_BRIDGE(ifp)) +- zebra_l2_bridge_del(ifp); +- else if (IS_ZEBRA_IF_VXLAN(ifp)) +- zebra_l2_vxlanif_del(ifp); +- +- if_delete_update(&ifp); +- +- /* If VRF, delete the VRF structure itself. */ +- if (zif_type == ZEBRA_IF_VRF && !vrf_is_backend_netns()) +- netlink_vrf_change(h, tb[IFLA_LINKINFO], ns_id, name); ++ zlog_debug("RTM_DELLINK for %s(%u), enqueuing to zebra", ++ name, ifi->ifi_index); ++ ++ dplane_ctx_set_op(ctx, DPLANE_OP_INTF_DELETE); ++ dplane_ctx_set_status(ctx, ZEBRA_DPLANE_REQUEST_QUEUED); ++ ++ dplane_ctx_set_ifp_bond_ifindex(ctx, bond_ifindex); + } + ++ dplane_provider_enqueue_to_zebra(ctx); ++ + return 0; + } + +@@ -2111,6 +1709,13 @@ ssize_t netlink_intf_msg_encode(uint16_t cmd, + void interface_list(struct zebra_ns *zns) + { + interface_lookup_netlink(zns); ++ ++ zebra_dplane_startup_stage(zns, ZEBRA_DPLANE_INTERFACES_READ); ++} ++ ++void interface_list_second(struct zebra_ns *zns) ++{ ++ zebra_if_update_all_links(zns); + /* We add routes for interface address, + * so we need to get the nexthop info + * from the kernel before we can do that +@@ -2118,6 +1723,8 @@ void interface_list(struct zebra_ns *zns) + netlink_nexthop_read(zns); + + interface_addr_lookup_netlink(zns); ++ ++ zebra_dplane_startup_stage(zns, ZEBRA_DPLANE_ADDRESSES_READ); + } + + /** +diff --git a/zebra/interface.c b/zebra/interface.c +index a05b9690ef..bfe7a06896 100644 +--- a/zebra/interface.c ++++ b/zebra/interface.c +@@ -1298,6 +1298,9 @@ static void zebra_if_addr_update_ctx(struct zebra_dplane_ctx *ctx, + const struct prefix *addr, *dest = NULL; + enum dplane_op_e op; + ++ if (!ifp) ++ return; ++ + op = dplane_ctx_get_op(ctx); + addr = dplane_ctx_get_intf_addr(ctx); + +@@ -1416,6 +1419,13 @@ static void zebra_if_netconf_update_ctx(struct zebra_dplane_ctx *ctx, + enum dplane_netconf_status_e mpls, mcast_on, linkdown; + bool *mcast_set, *linkdown_set; + ++ if (!ifp && ifindex != -1 && ifindex != -2) { ++ if (IS_ZEBRA_DEBUG_KERNEL) ++ zlog_debug("%s: Can't find ifp(%u)", __func__, ifindex); ++ ++ return; ++ } ++ + afi = dplane_ctx_get_afi(ctx); + mpls = dplane_ctx_get_netconf_mpls(ctx); + linkdown = dplane_ctx_get_netconf_linkdown(ctx); +@@ -1485,6 +1495,686 @@ static void zebra_if_netconf_update_ctx(struct zebra_dplane_ctx *ctx, + (*linkdown_set ? "ON" : "OFF")); + } + ++static void interface_vrf_change(enum dplane_op_e op, ifindex_t ifindex, ++ const char *name, uint32_t tableid, ++ ns_id_t ns_id) ++{ ++ struct vrf *vrf; ++ struct zebra_vrf *zvrf = NULL; ++ ++ if (op == DPLANE_OP_INTF_DELETE) { ++ if (IS_ZEBRA_DEBUG_DPLANE) ++ zlog_debug("DPLANE_OP_INTF_DELETE for VRF %s(%u)", name, ++ ifindex); ++ ++ vrf = vrf_lookup_by_id((vrf_id_t)ifindex); ++ if (!vrf) { ++ flog_warn(EC_ZEBRA_VRF_NOT_FOUND, ++ "%s(%u): vrf not found", name, ifindex); ++ return; ++ } ++ ++ vrf_delete(vrf); ++ } else { ++ if (IS_ZEBRA_DEBUG_DPLANE) ++ zlog_debug( ++ "DPLANE_OP_INTF_UPDATE for VRF %s(%u) table %u", ++ name, ifindex, tableid); ++ ++ if (!vrf_lookup_by_id((vrf_id_t)ifindex)) { ++ vrf_id_t exist_id; ++ ++ exist_id = zebra_vrf_lookup_by_table(tableid, ns_id); ++ if (exist_id != VRF_DEFAULT) { ++ vrf = vrf_lookup_by_id(exist_id); ++ ++ flog_err( ++ EC_ZEBRA_VRF_MISCONFIGURED, ++ "VRF %s id %u table id overlaps existing vrf %s(%d), misconfiguration exiting", ++ name, ifindex, vrf->name, vrf->vrf_id); ++ exit(-1); ++ } ++ } ++ ++ vrf = vrf_update((vrf_id_t)ifindex, name); ++ if (!vrf) { ++ flog_err(EC_LIB_INTERFACE, "VRF %s id %u not created", ++ name, ifindex); ++ return; ++ } ++ ++ /* ++ * This is the only place that we get the actual kernel table_id ++ * being used. We need it to set the table_id of the routes ++ * we are passing to the kernel.... And to throw some totally ++ * awesome parties. that too. ++ * ++ * At this point we *must* have a zvrf because the vrf_create ++ * callback creates one. We *must* set the table id ++ * before the vrf_enable because of( at the very least ) ++ * static routes being delayed for installation until ++ * during the vrf_enable callbacks. ++ */ ++ zvrf = (struct zebra_vrf *)vrf->info; ++ zvrf->table_id = tableid; ++ ++ /* Enable the created VRF. */ ++ if (!vrf_enable(vrf)) { ++ flog_err(EC_LIB_INTERFACE, ++ "Failed to enable VRF %s id %u", name, ++ ifindex); ++ return; ++ } ++ } ++} ++ ++/* ++ * Note: on netlink systems, there should be a 1-to-1 mapping ++ * between interface names and ifindex values. ++ */ ++static void set_ifindex(struct interface *ifp, ifindex_t ifi_index, ++ struct zebra_ns *zns) ++{ ++ struct interface *oifp; ++ ++ oifp = if_lookup_by_index_per_ns(zns, ifi_index); ++ if ((oifp != NULL) && (oifp != ifp)) { ++ if (ifi_index == IFINDEX_INTERNAL) ++ flog_err( ++ EC_LIB_INTERFACE, ++ "Netlink is setting interface %s ifindex to reserved internal value %u", ++ ifp->name, ifi_index); ++ else { ++ if (IS_ZEBRA_DEBUG_KERNEL) ++ zlog_debug( ++ "interface index %d was renamed from %s to %s", ++ ifi_index, oifp->name, ifp->name); ++ if (if_is_up(oifp)) ++ flog_err( ++ EC_LIB_INTERFACE, ++ "interface rename detected on up interface: index %d was renamed from %s to %s, results are uncertain!", ++ ifi_index, oifp->name, ifp->name); ++ if_delete_update(&oifp); ++ } ++ } ++ if_set_index(ifp, ifi_index); ++} ++ ++static inline void zebra_if_set_ziftype(struct interface *ifp, ++ enum zebra_iftype zif_type, ++ enum zebra_slave_iftype zif_slave_type) ++{ ++ struct zebra_if *zif; ++ ++ zif = (struct zebra_if *)ifp->info; ++ zif->zif_slave_type = zif_slave_type; ++ ++ if (zif->zif_type != zif_type) { ++ zif->zif_type = zif_type; ++ /* If the if_type has been set to bond initialize ES info ++ * against it. XXX - note that we don't handle the case where ++ * a zif changes from bond to non-bond; it is really ++ * an unexpected/error condition. ++ */ ++ zebra_evpn_if_init(zif); ++ } ++} ++ ++static void interface_update_hw_addr(struct zebra_dplane_ctx *ctx, ++ struct interface *ifp) ++{ ++ int i; ++ ++ ifp->hw_addr_len = dplane_ctx_get_ifp_hw_addr_len(ctx); ++ memcpy(ifp->hw_addr, dplane_ctx_get_ifp_hw_addr(ctx), ifp->hw_addr_len); ++ ++ for (i = 0; i < ifp->hw_addr_len; i++) ++ if (ifp->hw_addr[i] != 0) ++ break; ++ ++ if (i == ifp->hw_addr_len) ++ ifp->hw_addr_len = 0; ++} ++ ++static void interface_update_l2info(struct zebra_dplane_ctx *ctx, ++ struct interface *ifp, ++ enum zebra_iftype zif_type, int add, ++ ns_id_t link_nsid) ++{ ++ const struct zebra_l2info_vxlan *vxlan_info; ++ const struct zebra_l2info_gre *gre_info; ++ ++ switch (zif_type) { ++ case ZEBRA_IF_BRIDGE: ++ zebra_l2_bridge_add_update(ifp, ++ dplane_ctx_get_ifp_bridge_info(ctx)); ++ break; ++ case ZEBRA_IF_VLAN: ++ zebra_l2_vlanif_update(ifp, dplane_ctx_get_ifp_vlan_info(ctx)); ++ zebra_evpn_acc_bd_svi_set(ifp->info, NULL, ++ !!if_is_operative(ifp)); ++ break; ++ case ZEBRA_IF_VXLAN: ++ vxlan_info = dplane_ctx_get_ifp_vxlan_info(ctx); ++ zebra_l2_vxlanif_add_update(ifp, vxlan_info, add); ++ if (link_nsid != NS_UNKNOWN && vxlan_info->ifindex_link) ++ zebra_if_update_link(ifp, vxlan_info->ifindex_link, ++ link_nsid); ++ break; ++ case ZEBRA_IF_GRE: ++ gre_info = dplane_ctx_get_ifp_gre_info(ctx); ++ zebra_l2_greif_add_update(ifp, gre_info, add); ++ if (link_nsid != NS_UNKNOWN && gre_info->ifindex_link) ++ zebra_if_update_link(ifp, gre_info->ifindex_link, ++ link_nsid); ++ break; ++ case ZEBRA_IF_OTHER: ++ case ZEBRA_IF_VRF: ++ case ZEBRA_IF_MACVLAN: ++ case ZEBRA_IF_VETH: ++ case ZEBRA_IF_BOND: ++ case ZEBRA_IF_BOND_SLAVE: ++ break; ++ } ++} ++ ++static bool is_if_protodown_reason_only_frr(uint32_t rc_bitfield) ++{ ++ uint8_t frr_protodown_r_bit = if_netlink_get_frr_protodown_r_bit(); ++ ++ return (rc_bitfield == (((uint32_t)1) << frr_protodown_r_bit)); ++} ++ ++static void interface_if_protodown(struct interface *ifp, bool protodown, ++ uint32_t rc_bitfield) ++{ ++ struct zebra_if *zif = ifp->info; ++ bool old_protodown; ++ ++ /* ++ * Set our reason code to note it wasn't us. ++ * If the reason we got from the kernel is ONLY frr though, don't ++ * set it. ++ */ ++ COND_FLAG(zif->protodown_rc, ZEBRA_PROTODOWN_EXTERNAL, ++ protodown && rc_bitfield && ++ !is_if_protodown_reason_only_frr(rc_bitfield)); ++ ++ ++ old_protodown = !!ZEBRA_IF_IS_PROTODOWN(zif); ++ if (protodown == old_protodown) ++ return; ++ ++ if (IS_ZEBRA_DEBUG_EVPN_MH_ES || IS_ZEBRA_DEBUG_DPLANE) ++ zlog_debug("interface %s dplane change, protodown %s", ++ ifp->name, protodown ? "on" : "off"); ++ ++ /* Set protodown, respectively */ ++ COND_FLAG(zif->flags, ZIF_FLAG_PROTODOWN, protodown); ++ ++ if (zebra_evpn_is_es_bond_member(ifp)) { ++ /* Check it's not already being sent to the dplane first */ ++ if (protodown && ++ CHECK_FLAG(zif->flags, ZIF_FLAG_SET_PROTODOWN)) { ++ if (IS_ZEBRA_DEBUG_EVPN_MH_ES || IS_ZEBRA_DEBUG_KERNEL) ++ zlog_debug( ++ "bond mbr %s protodown on recv'd but already sent protodown on to the dplane", ++ ifp->name); ++ return; ++ } ++ ++ if (!protodown && ++ CHECK_FLAG(zif->flags, ZIF_FLAG_UNSET_PROTODOWN)) { ++ if (IS_ZEBRA_DEBUG_EVPN_MH_ES || IS_ZEBRA_DEBUG_KERNEL) ++ zlog_debug( ++ "bond mbr %s protodown off recv'd but already sent protodown off to the dplane", ++ ifp->name); ++ return; ++ } ++ ++ if (IS_ZEBRA_DEBUG_EVPN_MH_ES || IS_ZEBRA_DEBUG_KERNEL) ++ zlog_debug( ++ "bond mbr %s reinstate protodown %s in the dplane", ++ ifp->name, old_protodown ? "on" : "off"); ++ ++ if (old_protodown) ++ SET_FLAG(zif->flags, ZIF_FLAG_SET_PROTODOWN); ++ else ++ SET_FLAG(zif->flags, ZIF_FLAG_UNSET_PROTODOWN); ++ ++ dplane_intf_update(zif->ifp); ++ } ++} ++ ++static void if_sweep_protodown(struct zebra_if *zif) ++{ ++ bool protodown; ++ ++ protodown = !!ZEBRA_IF_IS_PROTODOWN(zif); ++ ++ if (!protodown) ++ return; ++ ++ if (IS_ZEBRA_DEBUG_KERNEL) ++ zlog_debug("interface %s sweeping protodown %s reason 0x%x", ++ zif->ifp->name, protodown ? "on" : "off", ++ zif->protodown_rc); ++ ++ /* Only clear our reason codes, leave external if it was set */ ++ UNSET_FLAG(zif->protodown_rc, ZEBRA_PROTODOWN_ALL); ++ dplane_intf_update(zif->ifp); ++} ++ ++static void interface_bridge_vxlan_update(struct zebra_dplane_ctx *ctx, ++ struct interface *ifp) ++{ ++ const struct zebra_dplane_bridge_vlan_info *bvinfo; ++ ++ bvinfo = dplane_ctx_get_ifp_bridge_vlan_info(ctx); ++ ++ if (!(bvinfo->flags & DPLANE_BRIDGE_VLAN_INFO_PVID)) ++ return; ++ ++ if (IS_ZEBRA_DEBUG_DPLANE) ++ zlog_debug("Access VLAN %u for VxLAN IF %s(%u)", bvinfo->vid, ++ ifp->name, ifp->ifindex); ++ ++ zebra_l2_vxlanif_update_access_vlan(ifp, bvinfo->vid); ++} ++ ++static void interface_bridge_vlan_update(struct zebra_dplane_ctx *ctx, ++ struct interface *ifp) ++{ ++ struct zebra_if *zif = ifp->info; ++ const struct zebra_dplane_bridge_vlan_info_array *bvarray; ++ struct zebra_dplane_bridge_vlan_info bvinfo; ++ bitfield_t old_vlan_bitmap; ++ uint16_t vid_range_start = 0; ++ int32_t i; ++ ++ /* cache the old bitmap addrs */ ++ old_vlan_bitmap = zif->vlan_bitmap; ++ /* create a new bitmap space for re-eval */ ++ bf_init(zif->vlan_bitmap, IF_VLAN_BITMAP_MAX); ++ ++ /* Could we have multiple bridge vlan infos? */ ++ bvarray = dplane_ctx_get_ifp_bridge_vlan_info_array(ctx); ++ if (!bvarray) ++ return; ++ ++ for (i = 0; i < bvarray->count; i++) { ++ bvinfo = bvarray->array[i]; ++ ++ if (bvinfo.flags & DPLANE_BRIDGE_VLAN_INFO_RANGE_BEGIN) { ++ vid_range_start = bvinfo.vid; ++ continue; ++ } ++ ++ if (!(bvinfo.flags & DPLANE_BRIDGE_VLAN_INFO_RANGE_END)) ++ vid_range_start = bvinfo.vid; ++ ++ zebra_vlan_bitmap_compute(ifp, vid_range_start, bvinfo.vid); ++ } ++ ++ zebra_vlan_mbr_re_eval(ifp, old_vlan_bitmap); ++ bf_free(old_vlan_bitmap); ++} ++ ++static void interface_bridge_handling(struct zebra_dplane_ctx *ctx, ++ struct interface *ifp, ++ enum zebra_iftype zif_type) ++{ ++ struct zebra_if *zif; ++ ++ if (!ifp) { ++ zlog_warn("Cannot find bridge if %s(%u)", ++ dplane_ctx_get_ifname(ctx), ++ dplane_ctx_get_ifindex(ctx)); ++ return; ++ } ++ ++ if (IS_ZEBRA_IF_VXLAN(ifp)) ++ return interface_bridge_vxlan_update(ctx, ifp); ++ ++ /* ++ * build vlan bitmap associated with this interface if that ++ * device type is interested in the vlans ++ */ ++ zif = ifp->info; ++ if (bf_is_inited(zif->vlan_bitmap)) ++ interface_bridge_vlan_update(ctx, ifp); ++} ++ ++static void zebra_if_dplane_ifp_handling(struct zebra_dplane_ctx *ctx) ++{ ++ enum dplane_op_e op = dplane_ctx_get_op(ctx); ++ const char *name = dplane_ctx_get_ifname(ctx); ++ ns_id_t ns_id = dplane_ctx_get_ns_id(ctx); ++ ifindex_t ifindex = dplane_ctx_get_ifindex(ctx); ++ ifindex_t bond_ifindex = dplane_ctx_get_ifp_bond_ifindex(ctx); ++ uint32_t tableid = dplane_ctx_get_ifp_table_id(ctx); ++ enum zebra_iftype zif_type = dplane_ctx_get_ifp_zif_type(ctx); ++ struct interface *ifp; ++ struct zebra_ns *zns; ++ ++ zns = zebra_ns_lookup(ns_id); ++ if (!zns) { ++ zlog_err("Where is our namespace?"); ++ return; ++ } ++ ++ if (IS_ZEBRA_DEBUG_DPLANE) ++ zlog_debug("%s for %s(%u)", dplane_op2str(op), name, ifindex); ++ ++ ifp = if_lookup_by_name_per_ns(zns, name); ++ if (op == DPLANE_OP_INTF_DELETE) { ++ /* Delete interface notification from kernel */ ++ if (ifp == NULL) { ++ if (IS_ZEBRA_DEBUG_EVENT) ++ zlog_debug( ++ "Delete LINK received for unknown interface %s(%u)", ++ name, ifindex); ++ return; ++ } ++ ++ if (IS_ZEBRA_IF_BOND(ifp)) ++ zebra_l2if_update_bond(ifp, false); ++ if (IS_ZEBRA_IF_BOND_SLAVE(ifp)) ++ zebra_l2if_update_bond_slave(ifp, bond_ifindex, false); ++ /* Special handling for bridge or VxLAN interfaces. */ ++ if (IS_ZEBRA_IF_BRIDGE(ifp)) ++ zebra_l2_bridge_del(ifp); ++ else if (IS_ZEBRA_IF_VXLAN(ifp)) ++ zebra_l2_vxlanif_del(ifp); ++ ++ if_delete_update(&ifp); ++ ++ if (zif_type == ZEBRA_IF_VRF && !vrf_is_backend_netns()) ++ interface_vrf_change(op, ifindex, name, tableid, ns_id); ++ } else { ++ ifindex_t master_ifindex, bridge_ifindex, bond_ifindex, ++ link_ifindex; ++ enum zebra_slave_iftype zif_slave_type; ++ uint8_t bypass; ++ uint64_t flags; ++ vrf_id_t vrf_id; ++ uint32_t mtu; ++ ns_id_t link_nsid; ++ struct zebra_if *zif; ++ bool protodown, protodown_set, startup; ++ uint32_t rc_bitfield; ++ uint8_t old_hw_addr[INTERFACE_HWADDR_MAX]; ++ char *desc; ++ uint8_t family; ++ ++ /* If VRF, create or update the VRF structure itself. */ ++ if (zif_type == ZEBRA_IF_VRF && !vrf_is_backend_netns()) ++ interface_vrf_change(op, ifindex, name, tableid, ns_id); ++ ++ master_ifindex = dplane_ctx_get_ifp_master_ifindex(ctx); ++ zif_slave_type = dplane_ctx_get_ifp_zif_slave_type(ctx); ++ bridge_ifindex = dplane_ctx_get_ifp_bridge_ifindex(ctx); ++ bond_ifindex = dplane_ctx_get_ifp_bond_ifindex(ctx); ++ bypass = dplane_ctx_get_ifp_bypass(ctx); ++ flags = dplane_ctx_get_ifp_flags(ctx); ++ vrf_id = dplane_ctx_get_ifp_vrf_id(ctx); ++ mtu = dplane_ctx_get_ifp_mtu(ctx); ++ link_ifindex = dplane_ctx_get_ifp_link_ifindex(ctx); ++ link_nsid = dplane_ctx_get_ifp_link_nsid(ctx); ++ protodown_set = dplane_ctx_get_ifp_protodown_set(ctx); ++ protodown = dplane_ctx_get_ifp_protodown(ctx); ++ rc_bitfield = dplane_ctx_get_ifp_rc_bitfield(ctx); ++ startup = dplane_ctx_get_ifp_startup(ctx); ++ desc = dplane_ctx_get_ifp_desc(ctx); ++ family = dplane_ctx_get_ifp_family(ctx); ++ ++#ifndef AF_BRIDGE ++ /* ++ * Work around to make free bsd happy at the moment ++ */ ++#define AF_BRIDGE 7 ++#endif ++ if (family == AF_BRIDGE) ++ return interface_bridge_handling(ctx, ifp, zif_type); ++ ++ if (ifp == NULL || ++ !CHECK_FLAG(ifp->status, ZEBRA_INTERFACE_ACTIVE)) { ++ /* Add interface notification from kernel */ ++ if (IS_ZEBRA_DEBUG_KERNEL) ++ zlog_debug( ++ "RTM_NEWLINK ADD for %s(%u) vrf_id %u type %d sl_type %d master %u", ++ name, ifindex, vrf_id, zif_type, ++ zif_slave_type, master_ifindex); ++ ++ if (ifp == NULL) { ++ /* unknown interface */ ++ ifp = if_get_by_name(name, vrf_id, NULL); ++ } else { ++ /* pre-configured interface, learnt now */ ++ if (ifp->vrf->vrf_id != vrf_id) ++ if_update_to_new_vrf(ifp, vrf_id); ++ } ++ ++ /* Update interface information. */ ++ set_ifindex(ifp, ifindex, zns); ++ ifp->flags = flags; ++ ifp->mtu6 = ifp->mtu = mtu; ++ ifp->metric = 0; ++ ifp->speed = kernel_get_speed(ifp, NULL); ++ ifp->ptm_status = ZEBRA_PTM_STATUS_UNKNOWN; ++ ++ /* Set interface type */ ++ zebra_if_set_ziftype(ifp, zif_type, zif_slave_type); ++ if (IS_ZEBRA_IF_VRF(ifp)) ++ SET_FLAG(ifp->status, ++ ZEBRA_INTERFACE_VRF_LOOPBACK); ++ ++ /* Update link. */ ++ zebra_if_update_link(ifp, link_ifindex, link_nsid); ++ ++ /* ++ * Just set the @link/lower-device ifindex. During ++ * nldump interfaces are not ordered in any fashion so ++ * we may end up getting upper devices before lower ++ * devices. We will setup the real linkage once the dump ++ * is complete. ++ */ ++ zif = (struct zebra_if *)ifp->info; ++ zif->link_ifindex = link_ifindex; ++ ++ ifp->ll_type = dplane_ctx_get_ifp_zltype(ctx); ++ interface_update_hw_addr(ctx, ifp); ++ ++ /* Inform clients, install any configured addresses. */ ++ if_add_update(ifp); ++ ++ /* ++ * Extract and save L2 interface information, take ++ * additional actions. ++ */ ++ interface_update_l2info(ctx, ifp, zif_type, 1, ++ link_nsid); ++ if (IS_ZEBRA_IF_BOND(ifp)) ++ zebra_l2if_update_bond(ifp, true); ++ if (IS_ZEBRA_IF_BRIDGE_SLAVE(ifp)) ++ zebra_l2if_update_bridge_slave( ++ ifp, bridge_ifindex, ns_id, ++ ZEBRA_BRIDGE_NO_ACTION); ++ else if (IS_ZEBRA_IF_BOND_SLAVE(ifp)) ++ zebra_l2if_update_bond_slave(ifp, bond_ifindex, ++ !!bypass); ++ ++ if (protodown_set) { ++ interface_if_protodown(ifp, protodown, ++ rc_bitfield); ++ if (startup) ++ if_sweep_protodown(zif); ++ } ++ ++ if (IS_ZEBRA_IF_BRIDGE(ifp)) { ++ if (IS_ZEBRA_DEBUG_KERNEL) ++ zlog_debug( ++ "RTM_NEWLINK ADD for %s(%u), vlan-aware %d", ++ name, ifp->ifindex, ++ IS_ZEBRA_IF_BRIDGE_VLAN_AWARE( ++ zif)); ++ } ++ } else if (ifp->vrf->vrf_id != vrf_id) { ++ /* VRF change for an interface. */ ++ if (IS_ZEBRA_DEBUG_KERNEL) ++ zlog_debug( ++ "RTM_NEWLINK vrf-change for %s(%u) vrf_id %u -> %u", ++ name, ifp->ifindex, ifp->vrf->vrf_id, ++ vrf_id); ++ ++ if_handle_vrf_change(ifp, vrf_id); ++ } else { ++ bool was_bridge_slave, was_bond_slave; ++ uint8_t chgflags = ZEBRA_BRIDGE_NO_ACTION; ++ ++ zif = ifp->info; ++ ++ /* Interface update. */ ++ if (IS_ZEBRA_DEBUG_KERNEL) ++ zlog_debug( ++ "RTM_NEWLINK update for %s(%u) sl_type %d master %u", ++ name, ifp->ifindex, zif_slave_type, ++ master_ifindex); ++ ++ set_ifindex(ifp, ifindex, zns); ++ ifp->mtu6 = ifp->mtu = mtu; ++ ifp->metric = 0; ++ ++ /* ++ * Update interface type - NOTE: Only slave_type can ++ * change. ++ */ ++ was_bridge_slave = IS_ZEBRA_IF_BRIDGE_SLAVE(ifp); ++ was_bond_slave = IS_ZEBRA_IF_BOND_SLAVE(ifp); ++ zebra_if_set_ziftype(ifp, zif_type, zif_slave_type); ++ ++ memcpy(old_hw_addr, ifp->hw_addr, INTERFACE_HWADDR_MAX); ++ ++ /* Update link. */ ++ zebra_if_update_link(ifp, link_ifindex, link_nsid); ++ ++ ifp->ll_type = dplane_ctx_get_ifp_zltype(ctx); ++ interface_update_hw_addr(ctx, ifp); ++ ++ if (protodown_set) ++ interface_if_protodown(ifp, protodown, ++ rc_bitfield); ++ ++ if (if_is_no_ptm_operative(ifp)) { ++ bool is_up = if_is_operative(ifp); ++ ++ ifp->flags = flags; ++ if (!if_is_no_ptm_operative(ifp) || ++ CHECK_FLAG(zif->flags, ++ ZIF_FLAG_PROTODOWN)) { ++ if (IS_ZEBRA_DEBUG_KERNEL) ++ zlog_debug( ++ "Intf %s(%u) has gone DOWN", ++ name, ifp->ifindex); ++ if_down(ifp); ++ rib_update(RIB_UPDATE_KERNEL); ++ } else if (if_is_operative(ifp)) { ++ bool mac_updated = false; ++ ++ /* ++ * Must notify client daemons of new ++ * interface status. ++ */ ++ if (IS_ZEBRA_DEBUG_KERNEL) ++ zlog_debug( ++ "Intf %s(%u) PTM up, notifying clients", ++ name, ifp->ifindex); ++ if_up(ifp, !is_up); ++ ++ /* ++ * Update EVPN VNI when SVI MAC change ++ */ ++ if (memcmp(old_hw_addr, ifp->hw_addr, ++ INTERFACE_HWADDR_MAX)) ++ mac_updated = true; ++ if (IS_ZEBRA_IF_VLAN(ifp) && ++ mac_updated) { ++ struct interface *link_if; ++ ++ link_if = if_lookup_by_index_per_ns( ++ zebra_ns_lookup( ++ NS_DEFAULT), ++ link_ifindex); ++ if (link_if) ++ zebra_vxlan_svi_up( ++ ifp, link_if); ++ } else if (mac_updated && ++ IS_ZEBRA_IF_BRIDGE(ifp)) { ++ zlog_debug( ++ "Intf %s(%u) bridge changed MAC address", ++ name, ifp->ifindex); ++ chgflags = ++ ZEBRA_BRIDGE_MASTER_MAC_CHANGE; ++ } ++ } ++ } else { ++ ifp->flags = flags; ++ if (if_is_operative(ifp) && ++ !CHECK_FLAG(zif->flags, ++ ZIF_FLAG_PROTODOWN)) { ++ if (IS_ZEBRA_DEBUG_KERNEL) ++ zlog_debug( ++ "Intf %s(%u) has come UP", ++ name, ifp->ifindex); ++ if_up(ifp, true); ++ if (IS_ZEBRA_IF_BRIDGE(ifp)) ++ chgflags = ++ ZEBRA_BRIDGE_MASTER_UP; ++ } else { ++ if (IS_ZEBRA_DEBUG_KERNEL) ++ zlog_debug( ++ "Intf %s(%u) has gone DOWN", ++ name, ifp->ifindex); ++ if_down(ifp); ++ rib_update(RIB_UPDATE_KERNEL); ++ } ++ } ++ ++ /* ++ * Extract and save L2 interface information, take ++ * additional actions. ++ */ ++ interface_update_l2info(ctx, ifp, zif_type, 0, ++ link_nsid); ++ if (IS_ZEBRA_IF_BRIDGE(ifp)) ++ zebra_l2if_update_bridge(ifp, chgflags); ++ if (IS_ZEBRA_IF_BOND(ifp)) ++ zebra_l2if_update_bond(ifp, true); ++ if (IS_ZEBRA_IF_BRIDGE_SLAVE(ifp) || was_bridge_slave) ++ zebra_l2if_update_bridge_slave( ++ ifp, bridge_ifindex, ns_id, chgflags); ++ else if (IS_ZEBRA_IF_BOND_SLAVE(ifp) || was_bond_slave) ++ zebra_l2if_update_bond_slave(ifp, bond_ifindex, ++ !!bypass); ++ if (IS_ZEBRA_IF_BRIDGE(ifp)) { ++ if (IS_ZEBRA_DEBUG_KERNEL) ++ zlog_debug( ++ "RTM_NEWLINK update for %s(%u), vlan-aware %d", ++ name, ifp->ifindex, ++ IS_ZEBRA_IF_BRIDGE_VLAN_AWARE( ++ zif)); ++ } ++ } ++ ++ zif = ifp->info; ++ if (zif) { ++ XFREE(MTYPE_ZIF_DESC, zif->desc); ++ if (desc[0]) ++ zif->desc = XSTRDUP(MTYPE_ZIF_DESC, desc); ++ } ++ } ++} ++ + void zebra_if_dplane_result(struct zebra_dplane_ctx *ctx) + { + struct zebra_ns *zns; +@@ -1514,17 +2204,6 @@ void zebra_if_dplane_result(struct zebra_dplane_ctx *ctx) + } + + ifp = if_lookup_by_index_per_ns(zns, ifindex); +- if (ifp == NULL) { +- if (op != DPLANE_OP_INTF_NETCONFIG || +- (ifindex != -1 && ifindex != -2)) { +- if (IS_ZEBRA_DEBUG_KERNEL) +- zlog_debug( +- "%s: can't find ifp at nsid %u index %d", +- __func__, ns_id, ifindex); +- +- return; +- } +- } + + switch (op) { + case DPLANE_OP_INTF_ADDR_ADD: +@@ -1535,7 +2214,15 @@ void zebra_if_dplane_result(struct zebra_dplane_ctx *ctx) + case DPLANE_OP_INTF_INSTALL: + case DPLANE_OP_INTF_UPDATE: + case DPLANE_OP_INTF_DELETE: +- zebra_if_update_ctx(ctx, ifp); ++ /* ++ * Queued from the dplane means it is something ++ * that we need to handle( create/delete the ++ * interface as needed ) ++ */ ++ if (dp_res == ZEBRA_DPLANE_REQUEST_QUEUED) ++ zebra_if_dplane_ifp_handling(ctx); ++ else ++ zebra_if_update_ctx(ctx, ifp); + break; + + case DPLANE_OP_INTF_NETCONFIG: +diff --git a/zebra/kernel_netlink.c b/zebra/kernel_netlink.c +index 4cd84cada2..3756a4ab0c 100644 +--- a/zebra/kernel_netlink.c ++++ b/zebra/kernel_netlink.c +@@ -410,7 +410,7 @@ static int netlink_information_fetch(struct nlmsghdr *h, ns_id_t ns_id, + case RTM_NEWLINK: + return netlink_link_change(h, ns_id, startup); + case RTM_DELLINK: +- return netlink_link_change(h, ns_id, startup); ++ return 0; + case RTM_NEWNEIGH: + case RTM_DELNEIGH: + case RTM_GETNEIGH: +@@ -482,6 +482,7 @@ static int dplane_netlink_information_fetch(struct nlmsghdr *h, ns_id_t ns_id, + + case RTM_NEWLINK: + case RTM_DELLINK: ++ return netlink_link_change(h, ns_id, startup); + + default: + break; +@@ -1170,7 +1171,6 @@ int netlink_parse_info(int (*filter)(struct nlmsghdr *, ns_id_t, int), + h->nlmsg_type, h->nlmsg_len, + h->nlmsg_seq, h->nlmsg_pid); + +- + /* + * Ignore messages that maybe sent from + * other actors besides the kernel +@@ -1774,17 +1774,11 @@ void kernel_init(struct zebra_ns *zns) + * lead to confusion, so we need to convert the + * RTNLGRP_XXX to a bit position for ourself + */ +- groups = RTMGRP_LINK | +- RTMGRP_IPV4_ROUTE | +- RTMGRP_IPV4_IFADDR | +- RTMGRP_IPV6_ROUTE | +- RTMGRP_IPV6_IFADDR | +- RTMGRP_IPV4_MROUTE | +- RTMGRP_NEIGH | +- ((uint32_t) 1 << (RTNLGRP_IPV4_RULE - 1)) | +- ((uint32_t) 1 << (RTNLGRP_IPV6_RULE - 1)) | +- ((uint32_t) 1 << (RTNLGRP_NEXTHOP - 1)) | +- ((uint32_t) 1 << (RTNLGRP_TC - 1)); ++ groups = RTMGRP_IPV4_ROUTE | RTMGRP_IPV6_ROUTE | RTMGRP_IPV4_MROUTE | ++ RTMGRP_NEIGH | ((uint32_t)1 << (RTNLGRP_IPV4_RULE - 1)) | ++ ((uint32_t)1 << (RTNLGRP_IPV6_RULE - 1)) | ++ ((uint32_t)1 << (RTNLGRP_NEXTHOP - 1)) | ++ ((uint32_t)1 << (RTNLGRP_TC - 1)); + + dplane_groups = (RTMGRP_LINK | + RTMGRP_IPV4_IFADDR | +diff --git a/zebra/kernel_socket.c b/zebra/kernel_socket.c +index f3462b9f22..98553edae6 100644 +--- a/zebra/kernel_socket.c ++++ b/zebra/kernel_socket.c +@@ -1482,6 +1482,14 @@ static void routing_socket(struct zebra_ns *zns) + thread_add_read(zrouter.master, kernel_read, NULL, routing_sock, NULL); + } + ++void interface_list_second(struct zebra_ns *zns) ++{ ++} ++ ++void interface_list_tunneldump(struct zebra_ns *zns) ++{ ++} ++ + /* Exported interface function. This function simply calls + routing_socket (). */ + void kernel_init(struct zebra_ns *zns) +diff --git a/zebra/rt.h b/zebra/rt.h +index 6f4dd48a54..3e91cdfffa 100644 +--- a/zebra/rt.h ++++ b/zebra/rt.h +@@ -99,6 +99,8 @@ extern int kernel_get_ipmr_sg_stats(struct zebra_vrf *zvrf, void *mroute); + * state. + */ + extern void interface_list(struct zebra_ns *zns); ++extern void interface_list_tunneldump(struct zebra_ns *zns); ++extern void interface_list_second(struct zebra_ns *zns); + extern void kernel_init(struct zebra_ns *zns); + extern void kernel_terminate(struct zebra_ns *zns, bool complete); + extern void macfdb_read(struct zebra_ns *zns); +diff --git a/zebra/rule_netlink.c b/zebra/rule_netlink.c +index 135f065428..4cc4281c1e 100644 +--- a/zebra/rule_netlink.c ++++ b/zebra/rule_netlink.c +@@ -416,6 +416,7 @@ int netlink_rules_read(struct zebra_ns *zns) + + ret = netlink_parse_info(netlink_rule_change, &zns->netlink_cmd, + &dp_info, 0, true); ++ + return ret; + } + +diff --git a/zebra/zebra_dplane.h b/zebra/zebra_dplane.h +index c10482ed96..9f9496c8f4 100644 +--- a/zebra/zebra_dplane.h ++++ b/zebra/zebra_dplane.h +@@ -422,6 +422,19 @@ uint8_t dplane_ctx_get_ifp_family(const struct zebra_dplane_ctx *ctx); + struct zebra_vxlan_vni_array; + void dplane_ctx_set_ifp_vxlan_vni_array(struct zebra_dplane_ctx *ctx, + struct zebra_vxlan_vni_array *vniarray); ++ ++/* ++ * These defines mirror the values for bridge values in linux ++ * at this point since we only have a linux implementation ++ * we don't need to do any type of translation. Let's just ++ * pass these through and use them ++ */ ++#define DPLANE_BRIDGE_VLAN_INFO_PVID \ ++ (1 << 1) /* VLAN is PVID, ingress untagged */ ++#define DPLANE_BRIDGE_VLAN_INFO_RANGE_BEGIN \ ++ (1 << 3) /* VLAN is start of vlan range */ ++#define DPLANE_BRIDGE_VLAN_INFO_RANGE_END \ ++ (1 << 4) /* VLAN is end of vlan range */ + const struct zebra_vxlan_vni_array * + dplane_ctx_get_ifp_vxlan_vni_array(const struct zebra_dplane_ctx *ctx); + struct zebra_dplane_bridge_vlan_info { +diff --git a/zebra/zebra_l2.c b/zebra/zebra_l2.c +index 07bbc6e3bc..4ad262a21d 100644 +--- a/zebra/zebra_l2.c ++++ b/zebra/zebra_l2.c +@@ -258,7 +258,7 @@ void zebra_l2if_update_bond(struct interface *ifp, bool add) + * map slaves (if any) to the bridge. + */ + void zebra_l2_bridge_add_update(struct interface *ifp, +- struct zebra_l2info_bridge *bridge_info) ++ const struct zebra_l2info_bridge *bridge_info) + { + struct zebra_if *zif; + +@@ -293,7 +293,7 @@ void zebra_l2if_update_bridge(struct interface *ifp, uint8_t chgflags) + * VLAN Id and this cannot change. + */ + void zebra_l2_vlanif_update(struct interface *ifp, +- struct zebra_l2info_vlan *vlan_info) ++ const struct zebra_l2info_vlan *vlan_info) + { + struct zebra_if *zif; + +@@ -310,7 +310,7 @@ void zebra_l2_vlanif_update(struct interface *ifp, + * clients about GRE information. + */ + void zebra_l2_greif_add_update(struct interface *ifp, +- struct zebra_l2info_gre *gre_info, int add) ++ const struct zebra_l2info_gre *gre_info, int add) + { + struct zebra_if *zif; + struct in_addr old_vtep_ip; +@@ -337,7 +337,8 @@ void zebra_l2_greif_add_update(struct interface *ifp, + * IP and VLAN mapping, but the latter is handled separately. + */ + void zebra_l2_vxlanif_add_update(struct interface *ifp, +- struct zebra_l2info_vxlan *vxlan_info, int add) ++ const struct zebra_l2info_vxlan *vxlan_info, ++ int add) + { + struct zebra_if *zif; + struct in_addr old_vtep_ip; +diff --git a/zebra/zebra_l2.h b/zebra/zebra_l2.h +index 8fef008f52..e3c5544f8f 100644 +--- a/zebra/zebra_l2.h ++++ b/zebra/zebra_l2.h +@@ -71,6 +71,18 @@ struct zebra_l2info_gre { + ns_id_t link_nsid; + }; + ++struct zebra_vxlan_vni { ++ vni_t vni; /* VNI */ ++ vlanid_t access_vlan; /* Access VLAN - for VLAN-aware bridge. */ ++ struct in_addr mcast_grp; ++ uint16_t flags; ++}; ++ ++struct zebra_vxlan_vni_array { ++ uint16_t count; ++ struct zebra_vxlan_vni vnis[0]; ++}; ++ + /* zebra L2 interface information - VXLAN interface */ + struct zebra_l2info_vxlan { + vni_t vni; /* VNI */ +@@ -108,17 +120,19 @@ extern void zebra_l2_map_slave_to_bridge(struct zebra_l2info_brslave *br_slave, + struct zebra_ns *zns); + extern void + zebra_l2_unmap_slave_from_bridge(struct zebra_l2info_brslave *br_slave); +-extern void zebra_l2_bridge_add_update(struct interface *ifp, +- struct zebra_l2info_bridge *bridge_info); ++extern void ++zebra_l2_bridge_add_update(struct interface *ifp, ++ const struct zebra_l2info_bridge *bridge_info); + extern void zebra_l2_bridge_del(struct interface *ifp); + extern void zebra_l2_vlanif_update(struct interface *ifp, +- struct zebra_l2info_vlan *vlan_info); ++ const struct zebra_l2info_vlan *vlan_info); + extern void zebra_l2_greif_add_update(struct interface *ifp, +- struct zebra_l2info_gre *vxlan_info, ++ const struct zebra_l2info_gre *vxlan_info, + int add); +-extern void zebra_l2_vxlanif_add_update(struct interface *ifp, +- struct zebra_l2info_vxlan *vxlan_info, +- int add); ++extern void ++zebra_l2_vxlanif_add_update(struct interface *ifp, ++ const struct zebra_l2info_vxlan *vxlan_info, ++ int add); + extern void zebra_l2_vxlanif_update_access_vlan(struct interface *ifp, + vlanid_t access_vlan); + extern void zebra_l2_greif_del(struct interface *ifp); +diff --git a/zebra/zebra_ns.c b/zebra/zebra_ns.c +index 7b076b8a4a..4714cdbff8 100644 +--- a/zebra/zebra_ns.c ++++ b/zebra/zebra_ns.c +@@ -38,6 +38,7 @@ + #include "rib.h" + #include "table_manager.h" + #include "zebra_errors.h" ++#include "zebra_dplane.h" + + extern struct zebra_privs_t zserv_privs; + +@@ -116,6 +117,35 @@ int zebra_ns_disabled(struct ns *ns) + return zebra_ns_disable_internal(zns, true); + } + ++void zebra_ns_startup_continue(struct zebra_dplane_ctx *ctx) ++{ ++ struct zebra_ns *zns = zebra_ns_lookup(dplane_ctx_get_ns_id(ctx)); ++ enum zebra_dplane_startup_notifications spot; ++ ++ if (!zns) { ++ zlog_err("%s: No Namespace associated with %u", __func__, ++ dplane_ctx_get_ns_id(ctx)); ++ return; ++ } ++ ++ spot = dplane_ctx_get_startup_spot(ctx); ++ ++ switch (spot) { ++ case ZEBRA_DPLANE_INTERFACES_READ: ++ interface_list_tunneldump(zns); ++ break; ++ case ZEBRA_DPLANE_TUNNELS_READ: ++ interface_list_second(zns); ++ break; ++ case ZEBRA_DPLANE_ADDRESSES_READ: ++ route_read(zns); ++ ++ kernel_read_pbr_rules(zns); ++ kernel_read_tc_qdisc(zns); ++ break; ++ } ++} ++ + /* Do global enable actions - open sockets, read kernel config etc. */ + int zebra_ns_enable(ns_id_t ns_id, void **info) + { +@@ -126,9 +156,6 @@ int zebra_ns_enable(ns_id_t ns_id, void **info) + kernel_init(zns); + zebra_dplane_ns_enable(zns, true); + interface_list(zns); +- route_read(zns); +- kernel_read_pbr_rules(zns); +- kernel_read_tc_qdisc(zns); + + return 0; + } +diff --git a/zebra/zebra_ns.h b/zebra/zebra_ns.h +index 7a0ffbc1ee..3d7d96c83f 100644 +--- a/zebra/zebra_ns.h ++++ b/zebra/zebra_ns.h +@@ -83,6 +83,8 @@ int zebra_ns_final_shutdown(struct ns *ns, + void **param_out __attribute__((unused))); + int zebra_ns_config_write(struct vty *vty, struct ns *ns); + ++void zebra_ns_startup_continue(struct zebra_dplane_ctx *ctx); ++ + #ifdef __cplusplus + } + #endif +diff --git a/zebra/zebra_rib.c b/zebra/zebra_rib.c +index 201fc761ae..fd6df441c6 100644 +--- a/zebra/zebra_rib.c ++++ b/zebra/zebra_rib.c +@@ -4770,7 +4770,9 @@ static void rib_process_dplane_results(struct thread *thread) + case DPLANE_OP_NEIGH_TABLE_UPDATE: + case DPLANE_OP_GRE_SET: + case DPLANE_OP_NONE: ++ break; + case DPLANE_OP_STARTUP_STAGE: ++ zebra_ns_startup_continue(ctx); + break; + + } /* Dispatch by op code */ +-- +2.17.1 + diff --git a/src/sonic-frr/patch/0019-zebra-Abstract-dplane_ctx_route_init-to-init-route-w.patch b/src/sonic-frr/patch/0019-zebra-Abstract-dplane_ctx_route_init-to-init-route-w.patch new file mode 100644 index 000000000000..583609209e71 --- /dev/null +++ b/src/sonic-frr/patch/0019-zebra-Abstract-dplane_ctx_route_init-to-init-route-w.patch @@ -0,0 +1,74 @@ +From 6fe32f784f57b4f10b96c9cdb938bf5ebf097fa2 Mon Sep 17 00:00:00 2001 +From: Carmine Scarpitta +Date: Fri, 7 Jul 2023 02:55:18 +0200 +Subject: [PATCH 1/2] zebra: Abstract `dplane_ctx_route_init` to init route + without copying + +The function `dplane_ctx_route_init` initializes a dplane route context +from the route object passed as an argument. Let's abstract this +function to allow initializing the dplane route context without actually +copying a route object. + +This allows us to use this function for initializing a dplane route +context when we don't have any route to copy in it. + +Signed-off-by: Carmine Scarpitta + +diff --git a/zebra/zebra_dplane.c b/zebra/zebra_dplane.c +index 83a38c2199..ae87e4f8b6 100644 +--- a/zebra/zebra_dplane.c ++++ b/zebra/zebra_dplane.c +@@ -3257,7 +3257,7 @@ int dplane_ctx_route_init_basic(struct zebra_dplane_ctx *ctx, + { + int ret = EINVAL; + +- if (!ctx || !re) ++ if (!ctx) + return ret; + + dplane_intf_extra_list_init(&ctx->u.rinfo.intf_extra_list); +@@ -3265,6 +3265,13 @@ int dplane_ctx_route_init_basic(struct zebra_dplane_ctx *ctx, + ctx->zd_op = op; + ctx->zd_status = ZEBRA_DPLANE_REQUEST_SUCCESS; + ++ /* This function may be called to create/init a dplane context, not ++ * necessarily to copy a route object. Let's return if there is no route ++ * object to copy. ++ */ ++ if (!re) ++ return AOK; ++ + ctx->u.rinfo.zd_type = re->type; + ctx->u.rinfo.zd_old_type = re->type; + +@@ -3296,6 +3303,8 @@ int dplane_ctx_route_init_basic(struct zebra_dplane_ctx *ctx, + + /* + * Initialize a context block for a route update from zebra data structs. ++ * If the `rn` or `re` parameters are NULL, this function only initializes the ++ * dplane context without copying a route object into it. + */ + int dplane_ctx_route_init(struct zebra_dplane_ctx *ctx, enum dplane_op_e op, + struct route_node *rn, struct route_entry *re) +@@ -3312,9 +3321,17 @@ int dplane_ctx_route_init(struct zebra_dplane_ctx *ctx, enum dplane_op_e op, + const struct interface *ifp; + struct dplane_intf_extra *if_extra; + +- if (!ctx || !rn || !re) ++ if (!ctx) + return ret; + ++ /* ++ * Initialize the dplane context and return, if there is no route ++ * object to copy ++ */ ++ if (!re || !rn) ++ return dplane_ctx_route_init_basic(ctx, op, NULL, NULL, NULL, ++ AFI_UNSPEC, SAFI_UNSPEC); ++ + /* + * Let's grab the data from the route_node + * so that we can call a helper function +-- +2.17.1 + diff --git a/src/sonic-frr/patch/0019-zebra-Rearrange-dplane_ctx_route_init.patch b/src/sonic-frr/patch/0019-zebra-Rearrange-dplane_ctx_route_init.patch deleted file mode 100755 index 5e76f7abdb68..000000000000 --- a/src/sonic-frr/patch/0019-zebra-Rearrange-dplane_ctx_route_init.patch +++ /dev/null @@ -1,135 +0,0 @@ -From 1ecc146b19ea78a34fc5cba08d55aca72527d7c3 Mon Sep 17 00:00:00 2001 -From: Donald Sharp -Date: Mon, 3 Oct 2022 13:22:22 -0400 -Subject: [PATCH 5/8] zebra: Rearrange dplane_ctx_route_init - -In order for a future commit to abstract the dplane_ctx_route_init -so that the kernel can use it, let's move some stuff around -and add a dplane_ctx_route_init_basic that can be used by multiple -different paths - -Signed-off-by: Donald Sharp - -create a dplane_ctx_route_init_basic so it can be used - -Signed-off-by: Donald Sharp ---- - zebra/zebra_dplane.c | 64 +++++++++++++++++++++++++++++--------------- - zebra/zebra_dplane.h | 6 +++++ - 2 files changed, 49 insertions(+), 21 deletions(-) - -diff --git a/zebra/zebra_dplane.c b/zebra/zebra_dplane.c -index 5d94e1a0b..05f9c2e08 100644 ---- a/zebra/zebra_dplane.c -+++ b/zebra/zebra_dplane.c -@@ -2334,25 +2334,16 @@ static int dplane_ctx_ns_init(struct zebra_dplane_ctx *ctx, - return AOK; - } - --/* -- * Initialize a context block for a route update from zebra data structs. -- */ --int dplane_ctx_route_init(struct zebra_dplane_ctx *ctx, enum dplane_op_e op, -- struct route_node *rn, struct route_entry *re) -+int dplane_ctx_route_init_basic(struct zebra_dplane_ctx *ctx, -+ enum dplane_op_e op, struct route_entry *re, -+ const struct prefix *p, -+ const struct prefix *src_p, afi_t afi, -+ safi_t safi) - { - int ret = EINVAL; -- const struct route_table *table = NULL; -- const struct rib_table_info *info; -- const struct prefix *p, *src_p; -- struct zebra_ns *zns; -- struct zebra_vrf *zvrf; -- struct nexthop *nexthop; -- struct zebra_l3vni *zl3vni; -- const struct interface *ifp; -- struct dplane_intf_extra *if_extra; - -- if (!ctx || !rn || !re) -- goto done; -+ if (!ctx || !re) -+ return ret; - - TAILQ_INIT(&ctx->u.rinfo.intf_extra_q); - -@@ -2362,9 +2353,6 @@ int dplane_ctx_route_init(struct zebra_dplane_ctx *ctx, enum dplane_op_e op, - ctx->u.rinfo.zd_type = re->type; - ctx->u.rinfo.zd_old_type = re->type; - -- /* Prefixes: dest, and optional source */ -- srcdest_rnode_prefixes(rn, &p, &src_p); -- - prefix_copy(&(ctx->u.rinfo.zd_dest), p); - - if (src_p) -@@ -2385,11 +2373,45 @@ int dplane_ctx_route_init(struct zebra_dplane_ctx *ctx, enum dplane_op_e op, - ctx->u.rinfo.zd_old_tag = re->tag; - ctx->u.rinfo.zd_distance = re->distance; - -+ ctx->u.rinfo.zd_afi = afi; -+ ctx->u.rinfo.zd_safi = safi; -+ -+ return AOK; -+} -+ -+/* -+ * Initialize a context block for a route update from zebra data structs. -+ */ -+int dplane_ctx_route_init(struct zebra_dplane_ctx *ctx, enum dplane_op_e op, -+ struct route_node *rn, struct route_entry *re) -+{ -+ int ret = EINVAL; -+ const struct route_table *table = NULL; -+ const struct rib_table_info *info; -+ const struct prefix *p, *src_p; -+ struct zebra_ns *zns; -+ struct zebra_vrf *zvrf; -+ struct nexthop *nexthop; -+ struct zebra_l3vni *zl3vni; -+ const struct interface *ifp; -+ struct dplane_intf_extra *if_extra; -+ -+ if (!ctx || !rn || !re) -+ return ret; -+ -+ /* -+ * Let's grab the data from the route_node -+ * so that we can call a helper function -+ */ -+ -+ /* Prefixes: dest, and optional source */ -+ srcdest_rnode_prefixes(rn, &p, &src_p); - table = srcdest_rnode_table(rn); - info = table->info; - -- ctx->u.rinfo.zd_afi = info->afi; -- ctx->u.rinfo.zd_safi = info->safi; -+ if (dplane_ctx_route_init_basic(ctx, op, re, p, src_p, info->afi, -+ info->safi) != AOK) -+ return ret; - - /* Copy nexthops; recursive info is included too */ - copy_nexthops(&(ctx->u.rinfo.zd_ng.nexthop), -diff --git a/zebra/zebra_dplane.h b/zebra/zebra_dplane.h -index 3210137c0..9d7502828 100644 ---- a/zebra/zebra_dplane.h -+++ b/zebra/zebra_dplane.h -@@ -774,6 +774,12 @@ dplane_pbr_ipset_entry_delete(struct zebra_pbr_ipset_entry *ipset); - int dplane_ctx_route_init(struct zebra_dplane_ctx *ctx, enum dplane_op_e op, - struct route_node *rn, struct route_entry *re); - -+int dplane_ctx_route_init_basic(struct zebra_dplane_ctx *ctx, -+ enum dplane_op_e op, struct route_entry *re, -+ const struct prefix *p, -+ const struct prefix *src_p, afi_t afi, -+ safi_t safi); -+ - /* Encode next hop information into data plane context. */ - int dplane_ctx_nexthop_init(struct zebra_dplane_ctx *ctx, enum dplane_op_e op, - struct nhg_hash_entry *nhe); --- -2.30.2 - diff --git a/src/sonic-frr/patch/0020-zebra-Add-ctx-to-netlink-message-parsing.patch b/src/sonic-frr/patch/0020-zebra-Add-ctx-to-netlink-message-parsing.patch deleted file mode 100755 index 9c1dd6ac5f76..000000000000 --- a/src/sonic-frr/patch/0020-zebra-Add-ctx-to-netlink-message-parsing.patch +++ /dev/null @@ -1,155 +0,0 @@ -From aebf87ce244c5189cec686ddf1278ae343807a53 Mon Sep 17 00:00:00 2001 -From: Donald Sharp -Date: Tue, 4 Oct 2022 15:41:36 -0400 -Subject: [PATCH 6/8] zebra: Add ctx to netlink message parsing - -Add the initial step of passing in a dplane context -to reading route netlink messages. This code -will be run in two contexts: - -a) The normal pthread for reading netlink messages from -the kernel -b) The dplane_fpm_nl pthread. - -The goal of this commit is too just allow a) to work -b) will be filled in in the future. Effectively -everything should still be working as it should -pre this change. We will just possibly allow -the passing of the context around( but not used ) - -Signed-off-by: Donald Sharp ---- - zebra/rt_netlink.c | 31 +++++++++++++++++++++++-------- - zebra/rt_netlink.h | 4 ++++ - zebra/zebra_dplane.c | 11 +++++++++++ - zebra/zebra_dplane.h | 10 ++++++++++ - 4 files changed, 48 insertions(+), 8 deletions(-) - -diff --git a/zebra/rt_netlink.c b/zebra/rt_netlink.c -index 24c01b7f5..b2df2cd8a 100644 ---- a/zebra/rt_netlink.c -+++ b/zebra/rt_netlink.c -@@ -667,8 +667,9 @@ static uint8_t parse_multipath_nexthops_unicast(ns_id_t ns_id, - } - - /* Looking up routing table by netlink interface. */ --static int netlink_route_change_read_unicast(struct nlmsghdr *h, ns_id_t ns_id, -- int startup) -+int netlink_route_change_read_unicast_internal(struct nlmsghdr *h, -+ ns_id_t ns_id, int startup, -+ struct zebra_dplane_ctx *ctx) - { - int len; - struct rtmsg *rtm; -@@ -740,9 +741,8 @@ static int netlink_route_change_read_unicast(struct nlmsghdr *h, ns_id_t ns_id, - - selfroute = is_selfroute(rtm->rtm_protocol); - -- if (!startup && selfroute -- && h->nlmsg_type == RTM_NEWROUTE -- && !zrouter.asic_offloaded) { -+ if (!startup && selfroute && h->nlmsg_type == RTM_NEWROUTE && -+ !zrouter.asic_offloaded && !ctx) { - if (IS_ZEBRA_DEBUG_KERNEL) - zlog_debug("Route type: %d Received that we think we have originated, ignoring", - rtm->rtm_protocol); -@@ -963,12 +963,20 @@ static int netlink_route_change_read_unicast(struct nlmsghdr *h, ns_id_t ns_id, - } - - if (nhe_id || ng) -- rib_add_multipath(afi, SAFI_UNICAST, &p, -- &src_p, re, ng); -+ dplane_rib_add_multipath(afi, SAFI_UNICAST, &p, -+ &src_p, re, ng, -+ startup, ctx); - else - XFREE(MTYPE_RE, re); - } - } else { -+ if (ctx) { -+ zlog_err( -+ "%s: %pFX RTM_DELROUTE received but received a context as well", -+ __func__, &p); -+ return 0; -+ } -+ - if (nhe_id) { - rib_delete(afi, SAFI_UNICAST, vrf_id, proto, 0, flags, - &p, &src_p, NULL, nhe_id, table, metric, -@@ -993,7 +1001,14 @@ static int netlink_route_change_read_unicast(struct nlmsghdr *h, ns_id_t ns_id, - } - } - -- return 0; -+ return 1; -+} -+ -+static int netlink_route_change_read_unicast(struct nlmsghdr *h, ns_id_t ns_id, -+ int startup) -+{ -+ return netlink_route_change_read_unicast_internal(h, ns_id, startup, -+ NULL); - } - - static struct mcast_route_data *mroute = NULL; -diff --git a/zebra/rt_netlink.h b/zebra/rt_netlink.h -index 93c06e555..da044c2c4 100644 ---- a/zebra/rt_netlink.h -+++ b/zebra/rt_netlink.h -@@ -122,6 +122,10 @@ netlink_put_lsp_update_msg(struct nl_batch *bth, struct zebra_dplane_ctx *ctx); - extern enum netlink_msg_status - netlink_put_pw_update_msg(struct nl_batch *bth, struct zebra_dplane_ctx *ctx); - -+int netlink_route_change_read_unicast_internal(struct nlmsghdr *h, -+ ns_id_t ns_id, int startup, -+ struct zebra_dplane_ctx *ctx); -+ - #ifdef NETLINK_DEBUG - const char *nlmsg_type2str(uint16_t type); - const char *af_type2str(int type); -diff --git a/zebra/zebra_dplane.c b/zebra/zebra_dplane.c -index 05f9c2e08..5048bf7dc 100644 ---- a/zebra/zebra_dplane.c -+++ b/zebra/zebra_dplane.c -@@ -5320,6 +5320,17 @@ kernel_dplane_process_ipset_entry(struct zebra_dplane_provider *prov, - dplane_provider_enqueue_out_ctx(prov, ctx); - } - -+void dplane_rib_add_multipath(afi_t afi, safi_t safi, struct prefix *p, -+ struct prefix_ipv6 *src_p, struct route_entry *re, -+ struct nexthop_group *ng, int startup, -+ struct zebra_dplane_ctx *ctx) -+{ -+ if (!ctx) -+ rib_add_multipath(afi, safi, p, src_p, re, ng); -+ else { -+ } -+} -+ - /* - * Kernel provider callback - */ -diff --git a/zebra/zebra_dplane.h b/zebra/zebra_dplane.h -index 9d7502828..4732a1628 100644 ---- a/zebra/zebra_dplane.h -+++ b/zebra/zebra_dplane.h -@@ -938,6 +938,16 @@ void zebra_dplane_pre_finish(void); - void zebra_dplane_finish(void); - void zebra_dplane_shutdown(void); - -+/* -+ * decision point for sending a routing update through the old -+ * straight to zebra master pthread or through the dplane to -+ * the master pthread for handling -+ */ -+void dplane_rib_add_multipath(afi_t afi, safi_t safi, struct prefix *p, -+ struct prefix_ipv6 *src_p, struct route_entry *re, -+ struct nexthop_group *ng, int startup, -+ struct zebra_dplane_ctx *ctx); -+ - #ifdef __cplusplus - } - #endif --- -2.30.2 - diff --git a/src/sonic-frr/patch/0020-zebra-Fix-crash-when-dplane_fpm_nl-fails-to-process-.patch b/src/sonic-frr/patch/0020-zebra-Fix-crash-when-dplane_fpm_nl-fails-to-process-.patch new file mode 100644 index 000000000000..f1bbf13061f2 --- /dev/null +++ b/src/sonic-frr/patch/0020-zebra-Fix-crash-when-dplane_fpm_nl-fails-to-process-.patch @@ -0,0 +1,50 @@ +From 6d7a251e5075a6fbced11e43fcdaa9e324c3871f Mon Sep 17 00:00:00 2001 +From: Carmine Scarpitta +Date: Fri, 7 Jul 2023 02:57:07 +0200 +Subject: [PATCH 2/2] zebra: Fix crash when `dplane_fpm_nl` fails to process + received routes + +When `dplane_fpm_nl` receives a route, it allocates memory for a dplane +context and calls `netlink_route_change_read_unicast_internal` without +initializing the `intf_extra_list` contained in the dplane context. If +`netlink_route_change_read_unicast_internal` is not able to process the +route, we call `dplane_ctx_fini` to free the dplane context. This causes +a crash because `dplane_ctx_fini` attempts to access the intf_extra_list +which is not initialized. + +To solve this issue, we can call `dplane_ctx_route_init`to initialize +the dplane route context properly, just after the dplane context +allocation. + +(gdb) bt +#0 0x0000555dd5ceae80 in dplane_intf_extra_list_pop (h=0x7fae1c007e68) at ../zebra/zebra_dplane.c:427 +#1 dplane_ctx_free_internal (ctx=0x7fae1c0074b0) at ../zebra/zebra_dplane.c:724 +#2 0x0000555dd5cebc99 in dplane_ctx_free (pctx=0x7fae2aa88c98) at ../zebra/zebra_dplane.c:869 +#3 dplane_ctx_free (pctx=0x7fae2aa88c98, pctx@entry=0x7fae2aa78c28) at ../zebra/zebra_dplane.c:855 +#4 dplane_ctx_fini (pctx=pctx@entry=0x7fae2aa88c98) at ../zebra/zebra_dplane.c:890 +#5 0x00007fae31e93f29 in fpm_read (t=) at ../zebra/dplane_fpm_nl.c:605 +#6 0x00007fae325191dd in thread_call (thread=thread@entry=0x7fae2aa98da0) at ../lib/thread.c:2006 +#7 0x00007fae324c42b8 in fpt_run (arg=0x555dd74777c0) at ../lib/frr_pthread.c:309 +#8 0x00007fae32405ea7 in start_thread () from /lib/x86_64-linux-gnu/libpthread.so.0 +#9 0x00007fae32325a2f in clone () from /lib/x86_64-linux-gnu/libc.so.6 + +Fixes: #13754 +Signed-off-by: Carmine Scarpitta + +diff --git a/zebra/dplane_fpm_nl.c b/zebra/dplane_fpm_nl.c +index 9f38401618..caa2f988e2 100644 +--- a/zebra/dplane_fpm_nl.c ++++ b/zebra/dplane_fpm_nl.c +@@ -599,7 +599,8 @@ static void fpm_read(struct thread *t) + switch (hdr->nlmsg_type) { + case RTM_NEWROUTE: + ctx = dplane_ctx_alloc(); +- dplane_ctx_set_op(ctx, DPLANE_OP_ROUTE_NOTIFY); ++ dplane_ctx_route_init(ctx, DPLANE_OP_ROUTE_NOTIFY, NULL, ++ NULL); + if (netlink_route_change_read_unicast_internal( + hdr, 0, false, ctx) != 1) { + dplane_ctx_fini(&ctx); +-- +2.17.1 + diff --git a/src/sonic-frr/patch/0021-zebra-Read-from-the-dplane_fpm_nl-a-route-update.patch b/src/sonic-frr/patch/0021-zebra-Read-from-the-dplane_fpm_nl-a-route-update.patch deleted file mode 100755 index 0af36d76172a..000000000000 --- a/src/sonic-frr/patch/0021-zebra-Read-from-the-dplane_fpm_nl-a-route-update.patch +++ /dev/null @@ -1,289 +0,0 @@ -From 95fac14ae8076ef4f5749aa3b761a7603b8c05cc Mon Sep 17 00:00:00 2001 -From: Donald Sharp -Date: Fri, 7 Oct 2022 08:02:44 -0400 -Subject: [PATCH 7/8] zebra: Read from the dplane_fpm_nl a route update - -Read from the fpm dplane a route update that will -include status about whether or not the asic was -successfull in offloading the route. - -Have this data passed up to zebra for processing and disseminate -this data as appropriate. - -Signed-off-by: Donald Sharp ---- - doc/developer/fpm.rst | 16 ++++++ - zebra/dplane_fpm_nl.c | 122 +++++++++++++++++++++++++++++++++++++++++- - zebra/zebra_dplane.c | 10 ++-- - zebra/zebra_dplane.h | 2 +- - zebra/zebra_rib.c | 16 +++++- - 5 files changed, 158 insertions(+), 8 deletions(-) - -diff --git a/doc/developer/fpm.rst b/doc/developer/fpm.rst -index 984986913..56d33671d 100644 ---- a/doc/developer/fpm.rst -+++ b/doc/developer/fpm.rst -@@ -101,3 +101,19 @@ Data - ^^^^ - - The netlink or protobuf message payload. -+ -+ -+Route Status Notification from ASIC -+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -+ -+The dplane_fpm_nl has the ability to read route netlink messages -+from the underlying fpm implementation that can tell zebra -+whether or not the route has been Offloaded/Failed or Trapped. -+The end developer must send the data up the same socket that has -+been created to listen for FPM messages from Zebra. The data sent -+must have a Frame Header with Version set to 1, Message Type set to 1 -+and an appropriate message Length. The message data must contain -+a RTM_NEWROUTE netlink message that sends the prefix and nexthops -+associated with the route. Finally rtm_flags must contain -+RTM_F_OFFLOAD, RTM_F_TRAP and or RTM_F_OFFLOAD_FAILED to signify -+what has happened to the route in the ASIC. -diff --git a/zebra/dplane_fpm_nl.c b/zebra/dplane_fpm_nl.c -index 8d41f3b07..893ee5845 100644 ---- a/zebra/dplane_fpm_nl.c -+++ b/zebra/dplane_fpm_nl.c -@@ -51,6 +51,7 @@ - #include "zebra/kernel_netlink.h" - #include "zebra/rt_netlink.h" - #include "zebra/debug.h" -+#include "fpm/fpm.h" - - #define SOUTHBOUND_DEFAULT_ADDR INADDR_LOOPBACK - #define SOUTHBOUND_DEFAULT_PORT 2620 -@@ -461,7 +462,13 @@ static void fpm_reconnect(struct fpm_nl_ctx *fnc) - static int fpm_read(struct thread *t) - { - struct fpm_nl_ctx *fnc = THREAD_ARG(t); -+ fpm_msg_hdr_t fpm; - ssize_t rv; -+ char buf[65535]; -+ struct nlmsghdr *hdr; -+ struct zebra_dplane_ctx *ctx; -+ size_t available_bytes; -+ size_t hdr_available_bytes; - - /* Let's ignore the input at the moment. */ - rv = stream_read_try(fnc->ibuf, fnc->socket, -@@ -493,12 +500,123 @@ static int fpm_read(struct thread *t) - if (rv == -2) - return 0; - -- stream_reset(fnc->ibuf); -- - /* Account all bytes read. */ - atomic_fetch_add_explicit(&fnc->counters.bytes_read, rv, - memory_order_relaxed); - -+ available_bytes = STREAM_READABLE(fnc->ibuf); -+ while (available_bytes) { -+ if (available_bytes < (ssize_t)FPM_MSG_HDR_LEN) { -+ stream_pulldown(fnc->ibuf); -+ return 0; -+ } -+ -+ fpm.version = stream_getc(fnc->ibuf); -+ fpm.msg_type = stream_getc(fnc->ibuf); -+ fpm.msg_len = stream_getw(fnc->ibuf); -+ -+ if (fpm.version != FPM_PROTO_VERSION && -+ fpm.msg_type != FPM_MSG_TYPE_NETLINK) { -+ stream_reset(fnc->ibuf); -+ zlog_warn( -+ "%s: Received version/msg_type %u/%u, expected 1/1", -+ __func__, fpm.version, fpm.msg_type); -+ -+ FPM_RECONNECT(fnc); -+ return 0; -+ } -+ -+ /* -+ * If the passed in length doesn't even fill in the header -+ * something is wrong and reset. -+ */ -+ if (fpm.msg_len < FPM_MSG_HDR_LEN) { -+ zlog_warn( -+ "%s: Received message length: %u that does not even fill the FPM header", -+ __func__, fpm.msg_len); -+ FPM_RECONNECT(fnc); -+ return 0; -+ } -+ -+ /* -+ * If we have not received the whole payload, reset the stream -+ * back to the beginning of the header and move it to the -+ * top. -+ */ -+ if (fpm.msg_len > available_bytes) { -+ stream_rewind_getp(fnc->ibuf, FPM_MSG_HDR_LEN); -+ stream_pulldown(fnc->ibuf); -+ return 0; -+ } -+ -+ available_bytes -= FPM_MSG_HDR_LEN; -+ -+ /* -+ * Place the data from the stream into a buffer -+ */ -+ hdr = (struct nlmsghdr *)buf; -+ stream_get(buf, fnc->ibuf, fpm.msg_len - FPM_MSG_HDR_LEN); -+ hdr_available_bytes = fpm.msg_len - FPM_MSG_HDR_LEN; -+ available_bytes -= hdr_available_bytes; -+ -+ /* Sanity check: must be at least header size. */ -+ if (hdr->nlmsg_len < sizeof(*hdr)) { -+ zlog_warn( -+ "%s: [seq=%u] invalid message length %u (< %zu)", -+ __func__, hdr->nlmsg_seq, hdr->nlmsg_len, -+ sizeof(*hdr)); -+ continue; -+ } -+ -+ if (hdr->nlmsg_len > fpm.msg_len) { -+ zlog_warn( -+ "%s: Received a inner header length of %u that is greater than the fpm total length of %u", -+ __func__, hdr->nlmsg_len, fpm.msg_len); -+ FPM_RECONNECT(fnc); -+ } -+ -+ /* Not enough bytes available. */ -+ if (hdr->nlmsg_len > hdr_available_bytes) { -+ zlog_warn( -+ "%s: [seq=%u] invalid message length %u (> %zu)", -+ __func__, hdr->nlmsg_seq, hdr->nlmsg_len, -+ available_bytes); -+ continue; -+ } -+ -+ if (!(hdr->nlmsg_flags & NLM_F_REQUEST)) { -+ if (IS_ZEBRA_DEBUG_FPM) -+ zlog_debug( -+ "%s: [seq=%u] not a request, skipping", -+ __func__, hdr->nlmsg_seq); -+ -+ /* -+ * This request is a bust, go to the next one -+ */ -+ continue; -+ } -+ -+ switch (hdr->nlmsg_type) { -+ case RTM_NEWROUTE: -+ ctx = dplane_ctx_alloc(); -+ dplane_ctx_set_op(ctx, DPLANE_OP_ROUTE_NOTIFY); -+ if (netlink_route_change_read_unicast_internal( -+ hdr, 0, false, ctx) != 1) { -+ dplane_ctx_fini(&ctx); -+ stream_pulldown(fnc->ibuf); -+ return 0; -+ } -+ break; -+ default: -+ if (IS_ZEBRA_DEBUG_FPM) -+ zlog_debug( -+ "%s: Received message type %u which is not currently handled", -+ __func__, hdr->nlmsg_type); -+ break; -+ } -+ } -+ -+ stream_reset(fnc->ibuf); - return 0; - } - -diff --git a/zebra/zebra_dplane.c b/zebra/zebra_dplane.c -index 5048bf7dc..336056abb 100644 ---- a/zebra/zebra_dplane.c -+++ b/zebra/zebra_dplane.c -@@ -2337,7 +2337,7 @@ static int dplane_ctx_ns_init(struct zebra_dplane_ctx *ctx, - int dplane_ctx_route_init_basic(struct zebra_dplane_ctx *ctx, - enum dplane_op_e op, struct route_entry *re, - const struct prefix *p, -- const struct prefix *src_p, afi_t afi, -+ const struct prefix_ipv6 *src_p, afi_t afi, - safi_t safi) - { - int ret = EINVAL; -@@ -2388,7 +2388,8 @@ int dplane_ctx_route_init(struct zebra_dplane_ctx *ctx, enum dplane_op_e op, - int ret = EINVAL; - const struct route_table *table = NULL; - const struct rib_table_info *info; -- const struct prefix *p, *src_p; -+ const struct prefix *p; -+ const struct prefix_ipv6 *src_p; - struct zebra_ns *zns; - struct zebra_vrf *zvrf; - struct nexthop *nexthop; -@@ -2405,7 +2406,7 @@ int dplane_ctx_route_init(struct zebra_dplane_ctx *ctx, enum dplane_op_e op, - */ - - /* Prefixes: dest, and optional source */ -- srcdest_rnode_prefixes(rn, &p, &src_p); -+ srcdest_rnode_prefixes(rn, &p, (const struct prefix **)&src_p); - table = srcdest_rnode_table(rn); - info = table->info; - -@@ -5328,6 +5329,9 @@ void dplane_rib_add_multipath(afi_t afi, safi_t safi, struct prefix *p, - if (!ctx) - rib_add_multipath(afi, safi, p, src_p, re, ng); - else { -+ dplane_ctx_route_init_basic(ctx, dplane_ctx_get_op(ctx), re, p, -+ src_p, afi, safi); -+ dplane_provider_enqueue_to_zebra(ctx); - } - } - -diff --git a/zebra/zebra_dplane.h b/zebra/zebra_dplane.h -index 4732a1628..c3fe3ba40 100644 ---- a/zebra/zebra_dplane.h -+++ b/zebra/zebra_dplane.h -@@ -777,7 +777,7 @@ int dplane_ctx_route_init(struct zebra_dplane_ctx *ctx, enum dplane_op_e op, - int dplane_ctx_route_init_basic(struct zebra_dplane_ctx *ctx, - enum dplane_op_e op, struct route_entry *re, - const struct prefix *p, -- const struct prefix *src_p, afi_t afi, -+ const struct prefix_ipv6 *src_p, afi_t afi, - safi_t safi); - - /* Encode next hop information into data plane context. */ -diff --git a/zebra/zebra_rib.c b/zebra/zebra_rib.c -index abd6e07f9..50f19adcc 100644 ---- a/zebra/zebra_rib.c -+++ b/zebra/zebra_rib.c -@@ -2138,8 +2138,7 @@ static void rib_process_dplane_notify(struct zebra_dplane_ctx *ctx) - } - - /* Ensure we clear the QUEUED flag */ -- if (!zrouter.asic_offloaded) -- UNSET_FLAG(re->status, ROUTE_ENTRY_QUEUED); -+ UNSET_FLAG(re->status, ROUTE_ENTRY_QUEUED); - - /* Is this a notification that ... matters? We mostly care about - * the route that is currently selected for installation; we may also -@@ -2182,6 +2181,19 @@ static void rib_process_dplane_notify(struct zebra_dplane_ctx *ctx) - dplane_ctx_get_type(ctx))); - } - goto done; -+ } else { -+ uint32_t flags = dplane_ctx_get_flags(ctx); -+ -+ if (CHECK_FLAG(flags, ZEBRA_FLAG_OFFLOADED)) { -+ UNSET_FLAG(re->flags, ZEBRA_FLAG_OFFLOAD_FAILED); -+ SET_FLAG(re->flags, ZEBRA_FLAG_OFFLOADED); -+ } -+ if (CHECK_FLAG(flags, ZEBRA_FLAG_OFFLOAD_FAILED)) { -+ UNSET_FLAG(re->flags, ZEBRA_FLAG_OFFLOADED); -+ SET_FLAG(re->flags, ZEBRA_FLAG_OFFLOAD_FAILED); -+ } -+ if (CHECK_FLAG(flags, ZEBRA_FLAG_TRAPPED)) -+ SET_FLAG(re->flags, ZEBRA_FLAG_TRAPPED); - } - - /* We'll want to determine whether the installation status of the --- -2.30.2 - diff --git a/src/sonic-frr/patch/0022-zebra-Fix-code-because-missing-backport.patch b/src/sonic-frr/patch/0022-zebra-Fix-code-because-missing-backport.patch deleted file mode 100755 index 4fa3a490ffac..000000000000 --- a/src/sonic-frr/patch/0022-zebra-Fix-code-because-missing-backport.patch +++ /dev/null @@ -1,100 +0,0 @@ -From 0104413e893f3e2d41da101b6788aea240e5a21a Mon Sep 17 00:00:00 2001 -From: Donald Sharp -Date: Thu, 15 Dec 2022 10:52:38 -0500 -Subject: [PATCH 8/8] zebra: Fix code because missing backport - -The commit: -commit 07fd1f7e9420efd480e85a9ab72b88fff274f791 -Author: Donald Sharp -Date: Tue Aug 9 20:07:09 2022 -0400 - - zebra: use rib_add_multipath in rt_netlink.c - - The new route code path was using a combination of - both rib_add() and rib_add_multipath() let's clean - it up some to use rib_add_multipath() - - Signed-off-by: Donald Sharp - -Abstracted the calling of rib_add and rib_add_multipath in -netlink_route_change_read_unicast to just calling rib_add_multipath -one time. Since this commit was not backported the netlink_route_change_read_unicast -function had an additional rib_add that is not going through the new dplane -code to make a decision point about how to send up the message. - -Make it so the non multipath case uses the new decision point. - -Signed-off-by: Donald Sharp ---- - zebra/rt_netlink.c | 41 ++++++++++++++++++++++++----------------- - 1 file changed, 24 insertions(+), 17 deletions(-) - -diff --git a/zebra/rt_netlink.c b/zebra/rt_netlink.c -index b2df2cd8a..76402561e 100644 ---- a/zebra/rt_netlink.c -+++ b/zebra/rt_netlink.c -@@ -909,37 +909,44 @@ int netlink_route_change_read_unicast_internal(struct nlmsghdr *h, - afi = AFI_IP6; - - if (h->nlmsg_type == RTM_NEWROUTE) { -+ struct route_entry *re; -+ struct nexthop_group *ng = NULL; -+ -+ re = XCALLOC(MTYPE_RE, sizeof(struct route_entry)); -+ re->type = proto; -+ re->distance = distance; -+ re->flags = flags; -+ re->metric = metric; -+ re->mtu = mtu; -+ re->vrf_id = vrf_id; -+ re->table = table; -+ re->uptime = monotime(NULL); -+ re->tag = tag; -+ re->nhe_id = nhe_id; -+ -+ if (!nhe_id) -+ ng = nexthop_group_new(); - - if (!tb[RTA_MULTIPATH]) { -- struct nexthop nh = {0}; -+ struct nexthop *nexthop, nh = {0}; - - if (!nhe_id) { - nh = parse_nexthop_unicast( - ns_id, rtm, tb, bh_type, index, prefsrc, - gate, afi, vrf_id); -+ -+ nexthop = nexthop_new(); -+ *nexthop = nh; -+ nexthop_group_add_sorted(ng, nexthop); - } -- rib_add(afi, SAFI_UNICAST, vrf_id, proto, 0, flags, &p, -- &src_p, &nh, nhe_id, table, metric, mtu, -- distance, tag); -+ dplane_rib_add_multipath(afi, SAFI_UNICAST, &p, &src_p, -+ re, ng, startup, ctx); - } else { - /* This is a multipath route */ -- struct route_entry *re; - struct nexthop_group *ng = NULL; - struct rtnexthop *rtnh = - (struct rtnexthop *)RTA_DATA(tb[RTA_MULTIPATH]); - -- re = XCALLOC(MTYPE_RE, sizeof(struct route_entry)); -- re->type = proto; -- re->distance = distance; -- re->flags = flags; -- re->metric = metric; -- re->mtu = mtu; -- re->vrf_id = vrf_id; -- re->table = table; -- re->uptime = monotime(NULL); -- re->tag = tag; -- re->nhe_id = nhe_id; -- - if (!nhe_id) { - uint8_t nhop_num; - --- -2.30.2 - diff --git a/src/sonic-frr/patch/0024-zebra-continue-fpm-read-when-we-decide-a-netlink-message-is-not-needed.patch b/src/sonic-frr/patch/0024-zebra-continue-fpm-read-when-we-decide-a-netlink-message-is-not-needed.patch deleted file mode 100644 index 6014fa3ea400..000000000000 --- a/src/sonic-frr/patch/0024-zebra-continue-fpm-read-when-we-decide-a-netlink-message-is-not-needed.patch +++ /dev/null @@ -1,31 +0,0 @@ -From c0275ab189d619c2f688a383e5e83183f02eaf6f Mon Sep 17 00:00:00 2001 -From: Donald Sharp -Date: Tue, 10 Jan 2023 08:36:50 -0500 -Subject: [PATCH] zebra: Continue fpm_read when we decide a netlink message is - not needed - -When FRR receives a netlink message that it decides to stop parsing -it returns a 0 ( instead of a -1 ). Just make the dplane continue -reading other data instead of aborting the read. - -Signed-off-by: Donald Sharp ---- - zebra/dplane_fpm_nl.c | 5 ++++- - 1 file changed, 4 insertions(+), 1 deletion(-) - -diff --git a/zebra/dplane_fpm_nl.c b/zebra/dplane_fpm_nl.c -index a31e79212..9d9ea7283 100644 ---- a/zebra/dplane_fpm_nl.c -+++ b/zebra/dplane_fpm_nl.c -@@ -605,7 +610,10 @@ static void fpm_read(struct thread *t) - hdr, 0, false, ctx) != 1) { - dplane_ctx_fini(&ctx); - stream_pulldown(fnc->ibuf); -- return 0; -+ /* -+ * Let's continue to read other messages -+ * Even if we ignore this one. -+ */ - } - break; - default: diff --git a/src/sonic-frr/patch/0025-zebra-Send-nht-resolved-entry-up-to-concerned-protoc.patch b/src/sonic-frr/patch/0025-zebra-Send-nht-resolved-entry-up-to-concerned-protoc.patch deleted file mode 100644 index 402515c3c8d4..000000000000 --- a/src/sonic-frr/patch/0025-zebra-Send-nht-resolved-entry-up-to-concerned-protoc.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 49c14222cb0d3cb60b32340976b4e42e5644a563 Mon Sep 17 00:00:00 2001 -From: Stepan Blyschak -Date: Tue, 31 Jan 2023 10:24:30 +0000 -Subject: [PATCH] zebra: Send nht resolved entry up to concerned protocols in - all cases - -There existed the idea, from Volta, that a nexthop group would not have -the same nexthops installed -vs- what FRR actually sent down. The -dplane would notify you. - -With the addition of 06525c4 -the code was put behind a bit of a wall controlled the usage -of it. - -The flag ROUTE_ENTRY_USE_FIB_NHG flag was being used -to control which set was being sent up to concerned parties -in nexthop tracking. Put this flag behind the wall and -do not necessarily set it when we receive a data plane -notification about a route being installed or not. - -Fixes: #12706 -Signed-off-by: Donald Sharp ---- - zebra/zebra_rib.c | 9 ++++++--- - 1 file changed, 6 insertions(+), 3 deletions(-) - -diff --git a/zebra/zebra_rib.c b/zebra/zebra_rib.c -index 50f19adcc..a8dbe4470 100644 ---- a/zebra/zebra_rib.c -+++ b/zebra/zebra_rib.c -@@ -1666,9 +1666,12 @@ no_nexthops: - ctxnhg->nexthop != NULL ? "" : " (empty)"); - - /* Set the flag about the dedicated fib list */ -- SET_FLAG(re->status, ROUTE_ENTRY_USE_FIB_NHG); -- if (ctxnhg->nexthop) -- copy_nexthops(&(re->fib_ng.nexthop), ctxnhg->nexthop, NULL); -+ if (zrouter.asic_notification_nexthop_control) { -+ SET_FLAG(re->status, ROUTE_ENTRY_USE_FIB_NHG); -+ if (ctxnhg->nexthop) -+ copy_nexthops(&(re->fib_ng.nexthop), ctxnhg->nexthop, -+ NULL); -+ } - - check_backups: - --- -2.30.2 - diff --git a/src/sonic-frr/patch/0027-bgpd-Ensure-FRR-has-enough-data-to-read-in-peek_for_as4_capability-and-bgp_open_option_parse.patch b/src/sonic-frr/patch/0027-bgpd-Ensure-FRR-has-enough-data-to-read-in-peek_for_as4_capability-and-bgp_open_option_parse.patch deleted file mode 100644 index fb6352b3fc9d..000000000000 --- a/src/sonic-frr/patch/0027-bgpd-Ensure-FRR-has-enough-data-to-read-in-peek_for_as4_capability-and-bgp_open_option_parse.patch +++ /dev/null @@ -1,130 +0,0 @@ -From 3e46b43e3788f0f87bae56a86b54d412b4710286 Mon Sep 17 00:00:00 2001 -From: Donald Sharp -Date: Fri, 30 Sep 2022 08:51:45 -0400 -Subject: [PATCH 1/2] bgpd: Ensure FRR has enough data to read 2 bytes in - peek_for_as4_capability - -In peek_for_as4_capability the code is checking that the -stream has at least 2 bytes to read ( the opt_type and the -opt_length ). However if BGP_OPEN_EXT_OPT_PARAMS_CAPABLE(peer) -is configured then FRR is reading 3 bytes. Which is not good -since the packet could be badly formated. Ensure that -FRR has the appropriate data length to read the data. - -Signed-off-by: Donald Sharp ---- - bgpd/bgp_open.c | 27 +++++++++++++++++++++------ - 1 file changed, 21 insertions(+), 6 deletions(-) - -diff --git a/bgpd/bgp_open.c b/bgpd/bgp_open.c -index 7248f034a5a..a760a7ca013 100644 ---- a/bgpd/bgp_open.c -+++ b/bgpd/bgp_open.c -@@ -1185,15 +1185,30 @@ as_t peek_for_as4_capability(struct peer *peer, uint16_t length) - uint8_t opt_type; - uint16_t opt_length; - -- /* Check the length. */ -- if (stream_get_getp(s) + 2 > end) -+ /* Ensure we can read the option type */ -+ if (stream_get_getp(s) + 1 > end) - goto end; - -- /* Fetch option type and length. */ -+ /* Fetch the option type */ - opt_type = stream_getc(s); -- opt_length = BGP_OPEN_EXT_OPT_PARAMS_CAPABLE(peer) -- ? stream_getw(s) -- : stream_getc(s); -+ -+ /* -+ * Check the length and fetch the opt_length -+ * If the peer is BGP_OPEN_EXT_OPT_PARAMS_CAPABLE(peer) -+ * then we do a getw which is 2 bytes. So we need to -+ * ensure that we can read that as well -+ */ -+ if (BGP_OPEN_EXT_OPT_PARAMS_CAPABLE(peer)) { -+ if (stream_get_getp(s) + 2 > end) -+ goto end; -+ -+ opt_length = stream_getw(s); -+ } else { -+ if (stream_get_getp(s) + 1 > end) -+ goto end; -+ -+ opt_length = stream_getc(s); -+ } - - /* Option length check. */ - if (stream_get_getp(s) + opt_length > end) - -From 1117baca3c592877a4d8a13ed6a1d9bd83977487 Mon Sep 17 00:00:00 2001 -From: Donald Sharp -Date: Fri, 30 Sep 2022 08:57:43 -0400 -Subject: [PATCH 2/2] bgpd: Ensure FRR has enough data to read 2 bytes in - bgp_open_option_parse - -In bgp_open_option_parse the code is checking that the -stream has at least 2 bytes to read ( the opt_type and -the opt_length). However if BGP_OPEN_EXT_OPT_PARAMS_CAPABLE(peer) -is configured then FRR is reading 3 bytes. Which is not good -since the packet could be badly formateed. Ensure that -FRR has the appropriate data length to read the data. - -Signed-off-by: Donald Sharp ---- - bgpd/bgp_open.c | 35 ++++++++++++++++++++++++++++------- - 1 file changed, 28 insertions(+), 7 deletions(-) - -diff --git a/bgpd/bgp_open.c b/bgpd/bgp_open.c -index a760a7ca013..d1667fac261 100644 ---- a/bgpd/bgp_open.c -+++ b/bgpd/bgp_open.c -@@ -1278,19 +1278,40 @@ int bgp_open_option_parse(struct peer *peer, uint16_t length, - uint8_t opt_type; - uint16_t opt_length; - -- /* Must have at least an OPEN option header */ -- if (STREAM_READABLE(s) < 2) { -+ /* -+ * Check that we can read the opt_type and fetch it -+ */ -+ if (STREAM_READABLE(s) < 1) { - zlog_info("%s Option length error", peer->host); - bgp_notify_send(peer, BGP_NOTIFY_OPEN_ERR, - BGP_NOTIFY_OPEN_MALFORMED_ATTR); - return -1; - } -- -- /* Fetch option type and length. */ - opt_type = stream_getc(s); -- opt_length = BGP_OPEN_EXT_OPT_PARAMS_CAPABLE(peer) -- ? stream_getw(s) -- : stream_getc(s); -+ -+ /* -+ * Check the length of the stream to ensure that -+ * FRR can properly read the opt_length. Then read it -+ */ -+ if (BGP_OPEN_EXT_OPT_PARAMS_CAPABLE(peer)) { -+ if (STREAM_READABLE(s) < 2) { -+ zlog_info("%s Option length error", peer->host); -+ bgp_notify_send(peer, BGP_NOTIFY_OPEN_ERR, -+ BGP_NOTIFY_OPEN_MALFORMED_ATTR); -+ return -1; -+ } -+ -+ opt_length = stream_getw(s); -+ } else { -+ if (STREAM_READABLE(s) < 1) { -+ zlog_info("%s Option length error", peer->host); -+ bgp_notify_send(peer, BGP_NOTIFY_OPEN_ERR, -+ BGP_NOTIFY_OPEN_MALFORMED_ATTR); -+ return -1; -+ } -+ -+ opt_length = stream_getc(s); -+ } - - /* Option length check. */ - if (STREAM_READABLE(s) < opt_length) { diff --git a/src/sonic-frr/patch/0028-bgpd-Ensure-that-bgp-open-message-stream-has-enough-data-to-read.patch b/src/sonic-frr/patch/0028-bgpd-Ensure-that-bgp-open-message-stream-has-enough-data-to-read.patch deleted file mode 100644 index 73fcfc30266b..000000000000 --- a/src/sonic-frr/patch/0028-bgpd-Ensure-that-bgp-open-message-stream-has-enough-data-to-read.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 766eec1b7accffe2c04a5c9ebb14e9f487bb9f78 Mon Sep 17 00:00:00 2001 -From: Donald Sharp -Date: Wed, 2 Nov 2022 13:24:48 -0400 -Subject: [PATCH] bgpd: Ensure that bgp open message stream has enough data to - read - -If a operator receives an invalid packet that is of insufficient size -then it is possible for BGP to assert during reading of the packet -instead of gracefully resetting the connection with the peer. - -Signed-off-by: Donald Sharp ---- - bgpd/bgp_packet.c | 19 +++++++++++++++++++ - 1 file changed, 19 insertions(+) - -diff --git a/bgpd/bgp_packet.c b/bgpd/bgp_packet.c -index 769f9613da8..72d6a923175 100644 ---- a/bgpd/bgp_packet.c -+++ b/bgpd/bgp_packet.c -@@ -1386,8 +1386,27 @@ static int bgp_open_receive(struct peer *peer, bgp_size_t size) - || CHECK_FLAG(peer->flags, PEER_FLAG_EXTENDED_OPT_PARAMS)) { - uint8_t opttype; - -+ if (STREAM_READABLE(peer->curr) < 1) { -+ flog_err( -+ EC_BGP_PKT_OPEN, -+ "%s: stream does not have enough bytes for extended optional parameters", -+ peer->host); -+ bgp_notify_send(peer, BGP_NOTIFY_OPEN_ERR, -+ BGP_NOTIFY_OPEN_MALFORMED_ATTR); -+ return BGP_Stop; -+ } -+ - opttype = stream_getc(peer->curr); - if (opttype == BGP_OPEN_NON_EXT_OPT_TYPE_EXTENDED_LENGTH) { -+ if (STREAM_READABLE(peer->curr) < 2) { -+ flog_err( -+ EC_BGP_PKT_OPEN, -+ "%s: stream does not have enough bytes to read the extended optional parameters optlen", -+ peer->host); -+ bgp_notify_send(peer, BGP_NOTIFY_OPEN_ERR, -+ BGP_NOTIFY_OPEN_MALFORMED_ATTR); -+ return BGP_Stop; -+ } - optlen = stream_getw(peer->curr); - SET_FLAG(peer->sflags, - PEER_STATUS_EXT_OPT_PARAMS_LENGTH); diff --git a/src/sonic-frr/patch/0029-bgpd-Change-log-level-for-graceful-restart-events.patch b/src/sonic-frr/patch/0029-bgpd-Change-log-level-for-graceful-restart-events.patch deleted file mode 100644 index a3474ae64f71..000000000000 --- a/src/sonic-frr/patch/0029-bgpd-Change-log-level-for-graceful-restart-events.patch +++ /dev/null @@ -1,122 +0,0 @@ -From c423bce4db804c1d07d65ce3d06a9e62c4eceb2b Mon Sep 17 00:00:00 2001 -From: stormliang -Date: Mon, 19 Jun 2023 13:57:01 +0000 -Subject: [PATCH] change log level for graceful restart events - ---- - bgpd/bgp_fsm.c | 44 ++++++++++++++++++++------------------------ - bgpd/bgpd.c | 12 +++++------- - 2 files changed, 25 insertions(+), 31 deletions(-) - -diff --git a/bgpd/bgp_fsm.c b/bgpd/bgp_fsm.c -index 672fa4512..e392cd6e1 100644 ---- a/bgpd/bgp_fsm.c -+++ b/bgpd/bgp_fsm.c -@@ -786,9 +786,9 @@ static int bgp_graceful_restart_timer_expire(struct thread *thread) - - peer = THREAD_ARG(thread); - -- if (bgp_debug_neighbor_events(peer)) { -- zlog_debug("%s graceful restart timer expired", peer->host); -- zlog_debug("%s graceful restart stalepath timer stopped", -+ if (peer) { -+ zlog_info("%s graceful restart timer expired", peer->host); -+ zlog_info("%s graceful restart stalepath timer stopped", - peer->host); - } - -@@ -852,8 +852,8 @@ static int bgp_graceful_stale_timer_expire(struct thread *thread) - - peer = THREAD_ARG(thread); - -- if (bgp_debug_neighbor_events(peer)) -- zlog_debug("%s graceful restart stalepath timer expired", -+ if (peer) -+ zlog_info("%s graceful restart stalepath timer expired", - peer->host); - - /* NSF delete stale route */ -@@ -1427,20 +1427,18 @@ int bgp_stop(struct peer *peer) - /* graceful restart */ - if (peer->t_gr_stale) { - BGP_TIMER_OFF(peer->t_gr_stale); -- if (bgp_debug_neighbor_events(peer)) -- zlog_debug( -- "%s graceful restart stalepath timer stopped", -- peer->host); -+ zlog_info( -+ "%s graceful restart stalepath timer stopped", -+ peer->host); - } - if (CHECK_FLAG(peer->sflags, PEER_STATUS_NSF_WAIT)) { -- if (bgp_debug_neighbor_events(peer)) { -- zlog_debug( -- "%s graceful restart timer started for %d sec", -- peer->host, peer->v_gr_restart); -- zlog_debug( -- "%s graceful restart stalepath timer started for %d sec", -- peer->host, peer->bgp->stalepath_time); -- } -+ zlog_info( -+ "%s graceful restart timer started for %d sec", -+ peer->host, peer->v_gr_restart); -+ zlog_info( -+ "%s graceful restart stalepath timer started for %d sec", -+ peer->host, peer->bgp->stalepath_time); -+ - BGP_TIMER_ON(peer->t_gr_restart, - bgp_graceful_restart_timer_expire, - peer->v_gr_restart); -@@ -2205,18 +2203,16 @@ static int bgp_establish(struct peer *peer) - UNSET_FLAG(peer->sflags, PEER_STATUS_NSF_MODE); - if (peer->t_gr_stale) { - BGP_TIMER_OFF(peer->t_gr_stale); -- if (bgp_debug_neighbor_events(peer)) -- zlog_debug( -- "%s graceful restart stalepath timer stopped", -- peer->host); -+ zlog_info( -+ "%s graceful restart stalepath timer stopped", -+ peer->host); - } - } - - if (peer->t_gr_restart) { - BGP_TIMER_OFF(peer->t_gr_restart); -- if (bgp_debug_neighbor_events(peer)) -- zlog_debug("%s graceful restart timer stopped", -- peer->host); -+ zlog_info("%s graceful restart timer stopped", -+ peer->host); - } - - /* Reset uptime, turn on keepalives, send current table. */ -diff --git a/bgpd/bgpd.c b/bgpd/bgpd.c -index 7e528b219..2fc471555 100644 ---- a/bgpd/bgpd.c -+++ b/bgpd/bgpd.c -@@ -2346,16 +2346,14 @@ void peer_nsf_stop(struct peer *peer) - - if (peer->t_gr_restart) { - BGP_TIMER_OFF(peer->t_gr_restart); -- if (bgp_debug_neighbor_events(peer)) -- zlog_debug("%s graceful restart timer stopped", -- peer->host); -+ zlog_info("%s graceful restart timer stopped", -+ peer->host); - } - if (peer->t_gr_stale) { - BGP_TIMER_OFF(peer->t_gr_stale); -- if (bgp_debug_neighbor_events(peer)) -- zlog_debug( -- "%s graceful restart stalepath timer stopped", -- peer->host); -+ zlog_info( -+ "%s graceful restart stalepath timer stopped", -+ peer->host); - } - bgp_clear_route_all(peer); - } --- -2.25.1 - diff --git a/src/sonic-frr/patch/0030-zebra-Static-routes-async-notification-do-not-need-t.patch b/src/sonic-frr/patch/0030-zebra-Static-routes-async-notification-do-not-need-t.patch deleted file mode 100644 index aab240f018ab..000000000000 --- a/src/sonic-frr/patch/0030-zebra-Static-routes-async-notification-do-not-need-t.patch +++ /dev/null @@ -1,46 +0,0 @@ -From cb89515f7751c23368bc8dcaf0bcf768a42a0c11 Mon Sep 17 00:00:00 2001 -From: dgsudharsan -Date: Wed, 28 Jun 2023 19:42:16 +0000 -Subject: [PATCH] zebra: Static routes async notification do not need this test - When using asic_offload with an asynchronous notification the - rib_route_match_ctx function is testing for distance and tag being correct - against the re. This is no longer necessary. - -Normal route notification for static routes is this(well really all routes): a) zebra dplane generates a ctx to send to the dplane for route install b) dplane installs it in the kernel -c) if the dplane_fpm_nl.c module is being used it installs it. d) The context's success code is set to it worked and passes the context back up to zebra for processing. -e) Zebra master receives this and checks the distance and tag are correct for static routes and accepts the route and marks it installed. - -If the operator is using a wait for install mechansim where the dplane is asynchronously sending the result back up at a future time and it is using the dplane_fpm_nl.c code where it uses the rt_netlink.c route parsing code, then there is no way to set distance as that we do not pass distance to the kernel. - -As such static routes were never being properly handled since the re and context would not match and the route would still be marked as queued. - -This code is historical in nature and is no longer necessary. rib_route_match_ctx is only ever used with dplane notifications. Additionally static routes are now handled more intelligently from staticd and the distance changes are held in staticd not zebra, thus it can be removed. - -diff --git a/zebra/zebra_rib.c b/zebra/zebra_rib.c -index a8dbe4470..e021ed142 100644 ---- a/zebra/zebra_rib.c -+++ b/zebra/zebra_rib.c -@@ -1385,15 +1385,12 @@ static bool rib_route_match_ctx(const struct route_entry *re, - (re->instance == dplane_ctx_get_instance(ctx))) { - result = true; - -- /* We use an extra test for statics, and another for -- * kernel routes. -+ /* -+ * We use different tests for kernel and for -+ * connected routes. - */ -- if (re->type == ZEBRA_ROUTE_STATIC && -- (re->distance != dplane_ctx_get_distance(ctx) || -- re->tag != dplane_ctx_get_tag(ctx))) { -- result = false; -- } else if (re->type == ZEBRA_ROUTE_KERNEL && -- re->metric != dplane_ctx_get_metric(ctx)) { -+ if (re->type == ZEBRA_ROUTE_KERNEL && -+ re->metric != dplane_ctx_get_metric(ctx)) { - result = false; - } else if (re->type == ZEBRA_ROUTE_CONNECT) { - result = nexthop_group_equal_no_recurse( --- -2.17.1 - diff --git a/src/sonic-frr/patch/Disable-ipv6-src-address-test-in-pceplib.patch b/src/sonic-frr/patch/Disable-ipv6-src-address-test-in-pceplib.patch index b924b9a66fc4..3bf2fa42eae7 100644 --- a/src/sonic-frr/patch/Disable-ipv6-src-address-test-in-pceplib.patch +++ b/src/sonic-frr/patch/Disable-ipv6-src-address-test-in-pceplib.patch @@ -1,13 +1,11 @@ -From dfe0158344ea581370dd2dba8e4db189cf369147 Mon Sep 17 00:00:00 2001 +From 54ac159d360a8fc9e8fcb19d984e8230e16f6fc0 Mon Sep 17 00:00:00 2001 From: Syed Hasan Raza Naqvi Date: Wed, 4 May 2022 05:11:01 +0000 -Subject: [PATCH] Disable ipv6 src address test in pcep. Docker lo interface - doesn't have ipv6 enabled. Socket bind returns cannot assign requested - address. +Subject: [PATCH] From dfe0158344ea581370dd2dba8e4db189cf369147 Mon Sep 17 + 00:00:00 2001 Subject: [PATCH] Disable ipv6 src address test in pcep. Docker + lo interface doesn't have ipv6 enabled. Socket bind returns cannot assign + requested address. ---- - pceplib/test/pcep_socket_comm_test.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pceplib/test/pcep_socket_comm_test.c b/pceplib/test/pcep_socket_comm_test.c index 116531f12..8b71a5090 100644 @@ -23,5 +21,5 @@ index 116531f12..8b71a5090 100644 void pcep_socket_comm_test_teardown() -- -2.20.1 +2.17.1 diff --git a/src/sonic-frr/patch/cross-compile-changes.patch b/src/sonic-frr/patch/cross-compile-changes.patch index 621a8a66985d..2e618f059fc6 100644 --- a/src/sonic-frr/patch/cross-compile-changes.patch +++ b/src/sonic-frr/patch/cross-compile-changes.patch @@ -1,52 +1,47 @@ -From ece218405fe4c086017f2a4f2b2b4c86b9790db0 Mon Sep 17 00:00:00 2001 +From 611505531a96375000184fdf191d91bd021bd35f Mon Sep 17 00:00:00 2001 From: Saikrishna Arcot Date: Wed, 6 Jul 2022 11:28:16 -0700 -Subject: [PATCH] Make changes to support crosscompilation in SONiC +Subject: [PATCH] From ece218405fe4c086017f2a4f2b2b4c86b9790db0 Mon Sep 17 + 00:00:00 2001 Subject: [PATCH] Make changes to support crosscompilation in + SONiC Signed-off-by: Saikrishna Arcot ---- - debian/frr-doc.info | 1 - - debian/frr.manpages | 16 ---------------- - debian/rules | 17 ++++++++++++----- - 3 files changed, 12 insertions(+), 22 deletions(-) - delete mode 100644 debian/frr-doc.info - delete mode 100644 debian/frr.manpages diff --git a/debian/frr-doc.info b/debian/frr-doc.info deleted file mode 100644 -index a83255a24..000000000 +index 1976365e3..000000000 --- a/debian/frr-doc.info +++ /dev/null @@ -1 +0,0 @@ --doc/user/_build/texinfo/frr.info +-build/doc/user/_build/texinfo/frr.info diff --git a/debian/frr.manpages b/debian/frr.manpages deleted file mode 100644 -index 5075fd763..000000000 +index 5a1b74cfc..000000000 --- a/debian/frr.manpages +++ /dev/null @@ -1,16 +0,0 @@ --doc/manpages/_build/man/frr-bgpd.8 --doc/manpages/_build/man/frr-eigrpd.8 --doc/manpages/_build/man/frr-fabricd.8 --doc/manpages/_build/man/frr-isisd.8 --doc/manpages/_build/man/frr-ldpd.8 --doc/manpages/_build/man/frr-nhrpd.8 --doc/manpages/_build/man/frr-ospf6d.8 --doc/manpages/_build/man/frr-ospfd.8 --doc/manpages/_build/man/frr-pimd.8 --doc/manpages/_build/man/frr-ripd.8 --doc/manpages/_build/man/frr-ripngd.8 --doc/manpages/_build/man/frr-watchfrr.8 --doc/manpages/_build/man/frr-zebra.8 --doc/manpages/_build/man/frr.1 --doc/manpages/_build/man/mtracebis.8 --doc/manpages/_build/man/vtysh.1 +-build/doc/manpages/_build/man/frr-bgpd.8 +-build/doc/manpages/_build/man/frr-eigrpd.8 +-build/doc/manpages/_build/man/frr-fabricd.8 +-build/doc/manpages/_build/man/frr-isisd.8 +-build/doc/manpages/_build/man/frr-ldpd.8 +-build/doc/manpages/_build/man/frr-nhrpd.8 +-build/doc/manpages/_build/man/frr-ospf6d.8 +-build/doc/manpages/_build/man/frr-ospfd.8 +-build/doc/manpages/_build/man/frr-pimd.8 +-build/doc/manpages/_build/man/frr-ripd.8 +-build/doc/manpages/_build/man/frr-ripngd.8 +-build/doc/manpages/_build/man/frr-watchfrr.8 +-build/doc/manpages/_build/man/frr-zebra.8 +-build/doc/manpages/_build/man/frr.1 +-build/doc/manpages/_build/man/mtracebis.8 +-build/doc/manpages/_build/man/vtysh.1 diff --git a/debian/rules b/debian/rules -index 0fa9c3a3b..6b005ea5f 100755 +index 43e5d7e61..aa13106fe 100755 --- a/debian/rules +++ b/debian/rules -@@ -27,10 +27,17 @@ else - CONF_LUA=--enable-scripting +@@ -33,10 +33,17 @@ else + CONF_PIM6=--disable-pim6d endif +DEB_BUILD_ARCH ?= $(shell dpkg-architecture -qDEB_BUILD_ARCH) @@ -59,28 +54,26 @@ index 0fa9c3a3b..6b005ea5f 100755 +endif %: -- dh $@ -+ dh $@ --builddirectory=build +- dh $@ -Bbuild --with=sphinxdoc ++ dh $@ -Bbuild --with=sphinxdoc --builddirectory=build override_dh_auto_configure: $(shell dpkg-buildflags --export=sh); \ -@@ -67,12 +74,12 @@ override_dh_auto_configure: +@@ -74,10 +81,10 @@ override_dh_auto_configure: override_dh_auto_install: dh_auto_install - sed -e '1c #!/usr/bin/python3' -i debian/tmp/usr/lib/frr/frr-reload.py - sed -e '1c #!/usr/bin/python3' -i debian/tmp/usr/lib/frr/generate_support_bundle.py +- sed -e '1c #!/usr/bin/python3' -i debian/tmp/usr/lib/frr/frr_babeltrace.py +- sed -e '1c #!/usr/bin/python3' -i debian/tmp/usr/lib/frr/ospfclient.py + sed -e '1c #!$(shell which $PYTHON)' -i debian/tmp/usr/lib/frr/frr-reload.py + sed -e '1c #!$(shell which $PYTHON)' -i debian/tmp/usr/lib/frr/generate_support_bundle.py ++ sed -e '1c #!$(shell which $PYTHON)' -i debian/tmp/usr/lib/frr/frr_babeltrace.py ++ sed -e '1c #!$(shell which $PYTHON)' -i debian/tmp/usr/lib/frr/ospfclient.py # let dh_systemd_* and dh_installinit do their thing automatically -- cp tools/frr.service debian/frr.service -- cp tools/frrinit.sh debian/frr.init -+ cp build/tools/frr.service debian/frr.service -+ cp build/tools/frrinit.sh debian/frr.init - -rm -f debian/tmp/usr/lib/frr/frr - - # install config files + cp build/tools/frr.service debian/frr.service -- -2.25.1 +2.17.1 diff --git a/src/sonic-frr/patch/series b/src/sonic-frr/patch/series index 0de573f3a596..a0cdde792fac 100644 --- a/src/sonic-frr/patch/series +++ b/src/sonic-frr/patch/series @@ -1,31 +1,22 @@ -0001-Add-support-of-bgp-tcp-DSCP-value.patch -0002-Reduce-severity-of-Vty-connected-from-message.patch -0004-Allow-BGP-attr-NEXT_HOP-to-be-0.0.0.0-due-to-allevia.patch -0005-nexthops-compare-vrf-only-if-ip-type.patch -0006-frr-remove-frr-log-outchannel-to-var-log-frr.log.patch -0007-Add-support-of-bgp-l3vni-evpn.patch -0008-Link-local-scope-was-not-set-while-binding-socket-for-bgp-ipv6-link-local-neighbors.patch +0001-Reduce-severity-of-Vty-connected-from-message.patch +0002-Allow-BGP-attr-NEXT_HOP-to-be-0.0.0.0-due-to-allevia.patch +0003-nexthops-compare-vrf-only-if-ip-type.patch +0004-frr-remove-frr-log-outchannel-to-var-log-frr.log.patch +0005-Add-support-of-bgp-l3vni-evpn.patch +0006-Link-local-scope-was-not-set-while-binding-socket-for-bgp-ipv6-link-local-neighbors.patch Disable-ipv6-src-address-test-in-pceplib.patch cross-compile-changes.patch -0009-ignore-route-from-default-table.patch -0010-zebra-Note-when-the-netlink-DUMP-command-is-interrup.patch -0011-bgpd-enhanced-capability-is-always-turned-on-for-int.patch -0012-Ensure-ospf_apiclient_lsa_originate-cannot-accidently-write-into-stack.patch -0013-zebra-fix-dplane-fpm-nl-to-allow-for-fast-configuration.patch -0014-bgpd-Allow-network-XXX-to-work-with-bgp-suppress-fib.patch -0015-zebra-Return-statements-do-not-use-paranthesis.patch -0016-zebra-Add-zrouter.asic_notification_nexthop_control.patch -0017-zebra-Re-arrange-fpm_read-to-reduce-code-duplication.patch -0018-zebra-Add-dplane_ctx_get-set_flags.patch -0019-zebra-Rearrange-dplane_ctx_route_init.patch -0020-zebra-Add-ctx-to-netlink-message-parsing.patch -0021-zebra-Read-from-the-dplane_fpm_nl-a-route-update.patch -0022-zebra-Fix-code-because-missing-backport.patch -0023-Use-vrf_id-for-vrf-not-tabled_id.patch -0024-zebra-continue-fpm-read-when-we-decide-a-netlink-message-is-not-needed.patch -0025-zebra-Send-nht-resolved-entry-up-to-concerned-protoc.patch -0026-bgpd-Ensure-suppress-fib-pending-works-with-network-.patch -0027-bgpd-Ensure-FRR-has-enough-data-to-read-in-peek_for_as4_capability-and-bgp_open_option_parse.patch -0028-bgpd-Ensure-that-bgp-open-message-stream-has-enough-data-to-read.patch -0029-bgpd-Change-log-level-for-graceful-restart-events.patch -0030-zebra-Static-routes-async-notification-do-not-need-t.patch +0007-ignore-route-from-default-table.patch +0008-Use-vrf_id-for-vrf-not-tabled_id.patch +0009-bgpd-Ensure-suppress-fib-pending-works-with-network-.patch +0010-bgpd-Change-log-level-for-graceful-restart-events.patch +0011-zebra-Static-routes-async-notification-do-not-need-t.patch +0012-zebra-Rename-vrf_lookup_by_tableid-to-zebra_vrf_look.patch +0013-zebra-Move-protodown_r_bit-to-a-better-spot.patch +0014-zebra-Remove-unused-dplane_intf_delete.patch +0015-zebra-Remove-unused-add-variable.patch +0016-zebra-Remove-duplicate-function-for-netlink-interfac.patch +0017-zebra-Add-code-to-get-set-interface-to-pass-up-from-.patch +0018-zebra-Use-zebra-dplane-for-RTM-link-and-addr.patch +0019-zebra-Abstract-dplane_ctx_route_init-to-init-route-w.patch +0020-zebra-Fix-crash-when-dplane_fpm_nl-fails-to-process-.patch diff --git a/src/sonic-gnmi b/src/sonic-gnmi index 01fe667e7d44..c548cc208862 160000 --- a/src/sonic-gnmi +++ b/src/sonic-gnmi @@ -1 +1 @@ -Subproject commit 01fe667e7d44cdfb2d046064c18e4d14ac6c0b4d +Subproject commit c548cc2088625c6a2ec3d4bea7f41a080f25cb0e diff --git a/src/sonic-host-services b/src/sonic-host-services index bc08806b6400..6767bc7b6d45 160000 --- a/src/sonic-host-services +++ b/src/sonic-host-services @@ -1 +1 @@ -Subproject commit bc08806b64002c506b8401eae5d9e1c760651e49 +Subproject commit 6767bc7b6d45979660a653e7b837501e00d05cde diff --git a/src/sonic-host-services-data/LICENSE b/src/sonic-host-services-data/LICENSE deleted file mode 100644 index 6e2e81a75fda..000000000000 --- a/src/sonic-host-services-data/LICENSE +++ /dev/null @@ -1,15 +0,0 @@ -Copyright (C) 2020 Microsoft - -This program is free software; you can redistribute it and/or -modify it under the terms of the GNU General Public License -as published by the Free Software Foundation; either version 2 -of the License, or (at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. diff --git a/src/sonic-host-services-data/debian/rules b/src/sonic-host-services-data/debian/rules index 22c7450193e8..47d26ccbc12f 100755 --- a/src/sonic-host-services-data/debian/rules +++ b/src/sonic-host-services-data/debian/rules @@ -15,6 +15,7 @@ build: override_dh_installsystemd: dh_installsystemd --no-start --name=caclmgrd dh_installsystemd --no-start --name=hostcfgd + dh_installsystemd --no-start --name=featured dh_installsystemd --no-start --name=aaastatsd dh_installsystemd --no-start --name=procdockerstatsd dh_installsystemd --no-start --name=determine-reboot-cause diff --git a/src/sonic-host-services-data/debian/sonic-host-services-data.featured.service b/src/sonic-host-services-data/debian/sonic-host-services-data.featured.service new file mode 100644 index 000000000000..0913e9458cc2 --- /dev/null +++ b/src/sonic-host-services-data/debian/sonic-host-services-data.featured.service @@ -0,0 +1,10 @@ +[Unit] +Description=Feature configuration daemon +Requires=updategraph.service +After=updategraph.service +BindsTo=sonic.target +After=sonic.target + +[Service] +Type=simple +ExecStart=/usr/local/bin/featured diff --git a/src/sonic-host-services-data/debian/sonic-host-services-data.featured.timer b/src/sonic-host-services-data/debian/sonic-host-services-data.featured.timer new file mode 100644 index 000000000000..12fbbe10f257 --- /dev/null +++ b/src/sonic-host-services-data/debian/sonic-host-services-data.featured.timer @@ -0,0 +1,12 @@ +[Unit] +Description=Delays feature daemon until SONiC has started +PartOf=featured.service + +[Timer] +OnUnitActiveSec=0 sec +OnBootSec=1min 30 sec +Unit=featured.service + +[Install] +WantedBy=timers.target sonic.target + diff --git a/src/sonic-linux-kernel b/src/sonic-linux-kernel index d070cae8e92a..e72818fcb6c2 160000 --- a/src/sonic-linux-kernel +++ b/src/sonic-linux-kernel @@ -1 +1 @@ -Subproject commit d070cae8e92ae3cd9798546e27d796a71fd7e914 +Subproject commit e72818fcb6c2b02864e66d842d67e13d8b67df4a diff --git a/src/sonic-platform-common b/src/sonic-platform-common index 465f95eed18c..ae7049cd0ac9 160000 --- a/src/sonic-platform-common +++ b/src/sonic-platform-common @@ -1 +1 @@ -Subproject commit 465f95eed18cd9a9a598beabb8c02cb5387e199a +Subproject commit ae7049cd0ac917c7f19f82fa3a5fb1fc231eefbb diff --git a/src/sonic-platform-daemons b/src/sonic-platform-daemons index d73808cead2a..f3c26319c423 160000 --- a/src/sonic-platform-daemons +++ b/src/sonic-platform-daemons @@ -1 +1 @@ -Subproject commit d73808cead2aaf386ae033d9d571882c92f0377c +Subproject commit f3c26319c423c38c8f8aa16e112c1ea768ea4497 diff --git a/src/sonic-py-common/sonic_py_common/device_info.py b/src/sonic-py-common/sonic_py_common/device_info.py index 2a7713433148..7a4cec81605d 100644 --- a/src/sonic-py-common/sonic_py_common/device_info.py +++ b/src/sonic-py-common/sonic_py_common/device_info.py @@ -713,19 +713,21 @@ def get_system_mac(namespace=None): machine_vars = get_machine_info() (mac, err) = run_command(syseeprom_cmd) hw_mac_entry_outputs.append((mac, err)) - if not mac: - if machine_vars is not None and machine_key in machine_vars: - hwsku = machine_vars[machine_key] - profile_cmd0 = ['cat', HOST_DEVICE_PATH + '/' + platform + '/' + hwsku + '/profile.ini'] + if machine_vars is not None and machine_key in machine_vars: + hwsku = machine_vars[machine_key] + profile_file = HOST_DEVICE_PATH + '/' + platform + '/' + hwsku + '/profile.ini' + if os.path.exists(profile_file): + profile_cmd0 = ['cat', profile_file] profile_cmd1 = ['grep', 'switchMacAddress'] profile_cmd2 = ['cut', '-f2', '-d', '='] (mac, err) = run_command_pipe(profile_cmd0, profile_cmd1, profile_cmd2) - else: - profile_cmd = ["false"] - (mac, err) = run_command(profile_cmd) - hw_mac_entry_outputs.append((mac, err)) - (mac, err) = run_command_pipe(iplink_cmd0, iplink_cmd1, iplink_cmd2) + hw_mac_entry_outputs.append((mac, err)) + else: + profile_cmd = ["false"] + (mac, err) = run_command(profile_cmd) hw_mac_entry_outputs.append((mac, err)) + (mac, err) = run_command_pipe(iplink_cmd0, iplink_cmd1, iplink_cmd2) + hw_mac_entry_outputs.append((mac, err)) elif (version_info['asic_type'] == 'cisco-8000'): # Try to get valid MAC from profile.ini first, else fetch it from syseeprom or eth0 platform = get_platform() diff --git a/src/sonic-py-common/sonic_py_common/multi_asic.py b/src/sonic-py-common/sonic_py_common/multi_asic.py index 792f1557ce86..ead29ef9b91d 100644 --- a/src/sonic-py-common/sonic_py_common/multi_asic.py +++ b/src/sonic-py-common/sonic_py_common/multi_asic.py @@ -157,7 +157,7 @@ def get_current_namespace(pid=None): """ net_namespace = None - command = ["sudo", '/bin/ip', 'netns', 'identify', "{}".format(os.getpid() if not pid else pid)] + command = ['/bin/ip', 'netns', 'identify', "{}".format(os.getpid() if not pid else pid)] proc = subprocess.Popen(command, stdout=subprocess.PIPE, universal_newlines=True, diff --git a/src/sonic-sairedis b/src/sonic-sairedis index 14a863a6d8f2..eb24302b877a 160000 --- a/src/sonic-sairedis +++ b/src/sonic-sairedis @@ -1 +1 @@ -Subproject commit 14a863a6d8f2855a7cebf1b7e62bc46dbed76ff6 +Subproject commit eb24302b877a09a6b255bc76dae6e93c85e13acb diff --git a/src/sonic-snmpagent b/src/sonic-snmpagent index 4948ea34b0f7..005bbc9dcca7 160000 --- a/src/sonic-snmpagent +++ b/src/sonic-snmpagent @@ -1 +1 @@ -Subproject commit 4948ea34b0f7e9ac82b2ef308d3e6253b22107f9 +Subproject commit 005bbc9dcca7705287d29e3df9156fa864dc8f86 diff --git a/src/sonic-swss b/src/sonic-swss index c7e1308ec6e0..aabe7411c113 160000 --- a/src/sonic-swss +++ b/src/sonic-swss @@ -1 +1 @@ -Subproject commit c7e1308ec6e00035136da09f6cb0f43bf5f82b46 +Subproject commit aabe7411c1132fe7559536da3d3cc3ea11798586 diff --git a/src/sonic-swss-common b/src/sonic-swss-common index 00db81f68b55..be425ede57b4 160000 --- a/src/sonic-swss-common +++ b/src/sonic-swss-common @@ -1 +1 @@ -Subproject commit 00db81f68b5520df6b32acab9d5834b0320eae3a +Subproject commit be425ede57b4412c51b240f285d80a10c40fa077 diff --git a/src/sonic-utilities b/src/sonic-utilities index 51c7a43cc04b..5b492d546ef8 160000 --- a/src/sonic-utilities +++ b/src/sonic-utilities @@ -1 +1 @@ -Subproject commit 51c7a43cc04bfd4feef354689f47e12ee9c404c1 +Subproject commit 5b492d546ef8a76cd90c4d15f645df1c730184ae diff --git a/src/sonic-yang-models/doc/Configuration.md b/src/sonic-yang-models/doc/Configuration.md index 44b9f5aa9425..9e1f709300dd 100644 --- a/src/sonic-yang-models/doc/Configuration.md +++ b/src/sonic-yang-models/doc/Configuration.md @@ -424,7 +424,14 @@ group name and IP ranges in **BGP_PEER_RANGE** table. "ip_range": [ "10.2.0.0/16" ] - } + }, + "BGPSentinel": { + "name": "BGPSentinel", + "ip_range": [ + "10.1.0.0/24" + ], + "src_address": "10.1.0.32" + } } } ``` @@ -1439,6 +1446,12 @@ The **MUX_LINKMGR** table is used for dualtor device configuration. "use_well_known_mac": "enabled", "src_mac": "ToRMac", "interval_pck_loss_count_update": "3" + }, + "MUXLOGGER": { + "log_verbosity": "debug" + }, + "SERVICE_MGMT": { + "kill_radv": "True" } } } @@ -2498,6 +2511,21 @@ The DNS_NAMESERVER table introduces static DNS nameservers configuration. } ``` +### FIPS + +The FIPS table introduces FIPS configuration. + +```json +{ + "FIPS": { + "global" : { + "enable": "true", + "enforce": "false" + } + } +} +``` + #### 5.2.3 Update value directly in db memory For Developers diff --git a/src/sonic-yang-models/setup.py b/src/sonic-yang-models/setup.py index f3de50de857a..e20c10da05db 100644 --- a/src/sonic-yang-models/setup.py +++ b/src/sonic-yang-models/setup.py @@ -121,6 +121,7 @@ def run(self): './yang-models/sonic-flex_counter.yang', './yang-models/sonic-fine-grained-ecmp.yang', './yang-models/sonic-feature.yang', + './yang-models/sonic-fips.yang', './yang-models/sonic-hash.yang', './yang-models/sonic-system-defaults.yang', './yang-models/sonic-interface.yang', @@ -188,7 +189,8 @@ def run(self): './yang-models/sonic-port-qos-map.yang', './yang-models/sonic-static-route.yang', './yang-models/sonic-system-port.yang', - './yang-models/sonic-macsec.yang']), + './yang-models/sonic-macsec.yang', + './yang-models/sonic-bgp-sentinel.yang']), ('cvlyang-models', ['./cvlyang-models/sonic-acl.yang', './cvlyang-models/sonic-bgp-common.yang', './cvlyang-models/sonic-bgp-global.yang', @@ -215,6 +217,7 @@ def run(self): './cvlyang-models/sonic-flex_counter.yang', './cvlyang-models/sonic-feature.yang', './cvlyang-models/sonic-fine-grained-ecmp.yang', + './cvlyang-models/sonic-fips.yang', './cvlyang-models/sonic-hash.yang', './cvlyang-models/sonic-system-defaults.yang', './cvlyang-models/sonic-interface.yang', @@ -261,7 +264,8 @@ def run(self): './cvlyang-models/sonic-port-qos-map.yang', './cvlyang-models/sonic-static-route.yang', './cvlyang-models/sonic-system-port.yang', - './cvlyang-models/sonic-macsec.yang']), + './cvlyang-models/sonic-macsec.yang', + './cvlyang-models/sonic-bgp-sentinel.yang']), ], zip_safe=False, ) diff --git a/src/sonic-yang-models/tests/files/sample_config_db.json b/src/sonic-yang-models/tests/files/sample_config_db.json index 742c68848f42..1e01dcbdba66 100644 --- a/src/sonic-yang-models/tests/files/sample_config_db.json +++ b/src/sonic-yang-models/tests/files/sample_config_db.json @@ -1098,12 +1098,14 @@ "Ethernet12.10|10.0.1.56/31": {}, "Ethernet12.10|fc00::1:71/126": {}, "Po0003.10": { - "admin_status": "up" + "admin_status": "up", + "vlan": "10" }, "Po0003.10|10.0.1.58/31": {}, "Po0003.10|fc00::1:75/126": {}, "Eth120.10": { - "admin_status": "up" + "admin_status": "up", + "vlan": "10" }, "Eth120.10|10.0.1.60/31": {}, "Eth120.10|fc00::1:79/126": {} @@ -1618,6 +1620,23 @@ "src_address": "10.1.0.32" } }, + "BGP_SENTINELS": { + "BGPSentinel": { + "ip_range": [ + "10.1.0.0/24" + ], + "name": "BGPSentinel", + "src_address": "10.1.0.32" + }, + "BGPSentinelV6": { + "ip_range": [ + "2603:10a0:321:82f9::/64", + "2603:10a1:30a:8000::/59" + ], + "name": "BGPSentinelV6", + "src_address": "fc00:1::32" + } + }, "BGP_MONITORS": { "5.6.7.8": { "admin_status": "up", @@ -2153,6 +2172,12 @@ "use_well_known_mac": "enabled", "src_mac": "ToRMac", "interval_pck_loss_count_update": "3" + }, + "MUXLOGGER": { + "log_verbosity": "debug" + }, + "SERVICE_MGMT": { + "kill_radv": "False" } }, @@ -2433,6 +2458,12 @@ "FG_NHG": "nhg2" } }, + "FIPS":{ + "global": { + "enable": "true", + "enforce": "true" + } + }, "FG_NHG_MEMBER": { "192.168.1.1": { "FG_NHG": "nhg1", diff --git a/src/sonic-yang-models/tests/yang_model_tests/tests/bgp.json b/src/sonic-yang-models/tests/yang_model_tests/tests/bgp.json index 966171888b37..543a985670f3 100644 --- a/src/sonic-yang-models/tests/yang_model_tests/tests/bgp.json +++ b/src/sonic-yang-models/tests/yang_model_tests/tests/bgp.json @@ -197,6 +197,20 @@ "BGP_ALLOWED_PREFIXES_LIST_INVALID_PREFIXES_IPV6": { "desc": "Invalid IPv6 prefix.", "eStrKey" : "Pattern" + }, + "BGP_SENTINEL_ALL_VALID_V4": { + "desc": "Configure BGP Sentinel table." + }, + "BGP_SENTINEL_ALL_VALID_V6": { + "desc": "Configure BGP SentinelV6 table." + }, + "BGP_SENTINEL_INVALID_RANGE_IPV4": { + "desc": "does not satisfy.", + "eStr": "Invalid value \"10.0.0.0/48\" in \"ip_range\" element." + }, + "BGP_SENTINEL_INVALID_RANGE_IPV6": { + "desc": "does not satisfy.", + "eStr": "Invalid value \"fc00:f0::/129\" in \"ip_range\" element." } } diff --git a/src/sonic-yang-models/tests/yang_model_tests/tests/fips.json b/src/sonic-yang-models/tests/yang_model_tests/tests/fips.json new file mode 100644 index 000000000000..74b1d386de12 --- /dev/null +++ b/src/sonic-yang-models/tests/yang_model_tests/tests/fips.json @@ -0,0 +1,10 @@ +{ + "FIPS_WITH_CORRECT_VALUES_ENABLE": { + "desc": "CONFIG FIPS TABLE WITH ALL THE CORRECT VALUES" + }, + "FIPS_WITH_INVALID_VALUES_ENABLE" : { + "desc": "Configure invalid mode in fips.", + "eStrKey": "Pattern", + "eStr": ["false|true|False|True"] + } +} diff --git a/src/sonic-yang-models/tests/yang_model_tests/tests/mux-linkmgr.json b/src/sonic-yang-models/tests/yang_model_tests/tests/mux-linkmgr.json index 3f399eec76cc..7c4aeadffddc 100644 --- a/src/sonic-yang-models/tests/yang_model_tests/tests/mux-linkmgr.json +++ b/src/sonic-yang-models/tests/yang_model_tests/tests/mux-linkmgr.json @@ -4,5 +4,11 @@ }, "MUX_LINKMGR_LINK_PROBER_CHANGE_MAC_ADDR": { "desc": "Use well-known mac and vlan mac as dst/src in linkmgrd link prober. " + }, + "MUX_LINKMGR_MUXLOGGER_CHANGE_VERBOSITY_LEVEL": { + "desc": "Consume verbosity level config changes. " + }, + "MUX_LINKMGR_SERVICE_MGMT_KILL_RADV_DISABLED": { + "desc": "Disable feature to kill radv." } } \ No newline at end of file diff --git a/src/sonic-yang-models/tests/yang_model_tests/tests/snmp.json b/src/sonic-yang-models/tests/yang_model_tests/tests/snmp.json index 14c387d5effa..95e9b7ba9f80 100644 --- a/src/sonic-yang-models/tests/yang_model_tests/tests/snmp.json +++ b/src/sonic-yang-models/tests/yang_model_tests/tests/snmp.json @@ -113,5 +113,40 @@ "SNMP_USER_PRIV_LONG_ENCRYPT_PASS_NEG_TEST": { "desc": "Load SNMP user with user type Priv with long encryption password", "eStrKey": "Range" + }, + "SNMP_AGENT_ADDRESS_CONFIG": { + "desc": "Load SNMP agent address config" + }, + "SNMP_AGENT_ADDRESS_CONFIG_IPV6": { + "desc": "Load SNMP agent address config" + }, + "SNMP_AGENT_ADDRESS_CONFIG_EMPTY_PORT_NUMBER": { + "desc": "Load SNMP agent address config with empty port number" + }, + "SNMP_AGENT_ADDRESS_CONFIG_MGMT_VRF": { + "desc": "Load SNMP agent address config with mgmt vrf" + }, + "SNMP_AGENT_ADDRESS_CONFIG_NO_VRF": { + "desc": "Load SNMP agent address config with no vrf", + "eStr": ["Missing required element"] + }, + "SNMP_AGENT_ADDRESS_CONFIG_INVALID_PORT": { + "desc": "Load SNMP agent address config with invalid port", + "eStrKey": "InvalidValue" + }, + "SNMP_AGENT_ADDRESS_CONFIG_DUPLICATE_IP_PORT": { + "desc": "Load two SNMP agent address config same ip and port", + "eStr": ["Unique data leaf(s)"] + }, + "SNMP_AGENT_ADDRESS_CONFIG_INVALID_IPV4_ADDRESS": { + "desc": "Load SNMP agent address config with invalid IPv4 address", + "eStrKey": "InvalidValue", + "eStr": ["ip"] + }, + "SNMP_AGENT_ADDRESS_CONFIG_INVALID_IPV6_ADDRESS": { + "desc": "Load SNMP agent address config with invalid IPV6 address", + "eStrKey": "InvalidValue", + "eStr": ["ip"] } } + diff --git a/src/sonic-yang-models/tests/yang_model_tests/tests/vlan_sub_interface.json b/src/sonic-yang-models/tests/yang_model_tests/tests/vlan_sub_interface.json index b91c8a94f386..52b3968d5d9f 100644 --- a/src/sonic-yang-models/tests/yang_model_tests/tests/vlan_sub_interface.json +++ b/src/sonic-yang-models/tests/yang_model_tests/tests/vlan_sub_interface.json @@ -55,5 +55,9 @@ "desc": "INCORRECT LOOPBACK ACTION IN VLAN_SUB_INTERFACE TABLE.", "eStrKey" : "Pattern", "eStr": ["drop|forward"] + }, + "VLAN_SUB_INTERFACE_SHORT_NAME_FORMAT_VLAN_CHECK_MUST_CONDITION_FALSE_TEST": { + "desc": "Configure valid short name format vlan sub interface vlan must check condition false.", + "eStrKey": "Must" } } diff --git a/src/sonic-yang-models/tests/yang_model_tests/tests_config/bgp.json b/src/sonic-yang-models/tests/yang_model_tests/tests_config/bgp.json index e18e0bea8f40..6ecc90c38699 100644 --- a/src/sonic-yang-models/tests/yang_model_tests/tests_config/bgp.json +++ b/src/sonic-yang-models/tests/yang_model_tests/tests_config/bgp.json @@ -1591,6 +1591,62 @@ ] } } + }, + "BGP_SENTINEL_ALL_VALID_V4": { + "sonic-bgp-sentinel:sonic-bgp-sentinel": { + "sonic-bgp-sentinel:BGP_SENTINELS": { + "BGP_SENTINELS_LIST": [ + { + "sentinel_name": "BGPSentinel", + "name": "BGPSentinel", + "src_address": "10.1.0.32", + "ip_range": ["10.1.0.0/24"] + } + ] + } + } + }, + "BGP_SENTINEL_ALL_VALID_V6": { + "sonic-bgp-sentinel:sonic-bgp-sentinel": { + "sonic-bgp-sentinel:BGP_SENTINELS": { + "BGP_SENTINELS_LIST": [ + { + "sentinel_name": "BGPSentinelV6", + "name": "BGPSentinelV6", + "src_address": "fc00:1::32", + "ip_range": ["2603:10a0:321:82f9::/64", "2603:10a1:30a:8000::/59"] + } + ] + } + } + }, + "BGP_SENTINEL_INVALID_RANGE_IPV4": { + "sonic-bgp-sentinel:sonic-bgp-sentinel": { + "sonic-bgp-sentinel:BGP_SENTINELS": { + "BGP_SENTINELS_LIST": [ + { + "sentinel_name": "BGPSentinel", + "name": "BGPSentinel", + "src_address": "10.1.0.32", + "ip_range": ["10.0.0.0/48", "10.1.0.0/24"] + } + ] + } + } + }, + "BGP_SENTINEL_INVALID_RANGE_IPV6": { + "sonic-bgp-sentinel:sonic-bgp-sentinel": { + "sonic-bgp-sentinel:BGP_SENTINELS": { + "BGP_SENTINELS_LIST": [ + { + "sentinel_name": "BGPSentinelV6", + "name": "BGPSentinelV6", + "src_address": "fc00:1::32", + "ip_range": ["fc00:f0::/129", "fc00:a0::/64"] + } + ] + } + } } } diff --git a/src/sonic-yang-models/tests/yang_model_tests/tests_config/fips.json b/src/sonic-yang-models/tests/yang_model_tests/tests_config/fips.json new file mode 100644 index 000000000000..8c7b989aee2c --- /dev/null +++ b/src/sonic-yang-models/tests/yang_model_tests/tests_config/fips.json @@ -0,0 +1,21 @@ +{ + "FIPS_WITH_CORRECT_VALUES_ENABLE": { + "sonic-fips:sonic-fips": { + "sonic-fips:FIPS": { + "sonic-fips:global": { + "enable": "true", + "enforce": "false" + } + } + } + }, + "FIPS_WITH_INVALID_VALUES_ENABLE": { + "sonic-fips:sonic-fips": { + "sonic-fips:FIPS": { + "sonic-fips:global": { + "enable": "Invalid" + } + } + } + } +} diff --git a/src/sonic-yang-models/tests/yang_model_tests/tests_config/mux-linkmgr.json b/src/sonic-yang-models/tests/yang_model_tests/tests_config/mux-linkmgr.json index 2210c169365c..1feff4f44038 100644 --- a/src/sonic-yang-models/tests/yang_model_tests/tests_config/mux-linkmgr.json +++ b/src/sonic-yang-models/tests/yang_model_tests/tests_config/mux-linkmgr.json @@ -22,5 +22,25 @@ } } } + }, + "MUX_LINKMGR_MUXLOGGER_CHANGE_VERBOSITY_LEVEL": { + "sonic-mux-linkmgr:sonic-mux-linkmgr": { + "sonic-mux-linkmgr:MUX_LINKMGR": { + "sonic-mux-linkmgr:MUXLOGGER": + { + "log_verbosity": "debug" + } + } + } + }, + "MUX_LINKMGR_SERVICE_MGMT_KILL_RADV_DISABLED": { + "sonic-mux-linkmgr:sonic-mux-linkmgr": { + "sonic-mux-linkmgr:MUX_LINKMGR": { + "sonic-mux-linkmgr:SERVICE_MGMT": + { + "kill_radv": "False" + } + } + } } } \ No newline at end of file diff --git a/src/sonic-yang-models/tests/yang_model_tests/tests_config/snmp.json b/src/sonic-yang-models/tests/yang_model_tests/tests_config/snmp.json index 3f6d5e6c16c4..d1e82873bdda 100644 --- a/src/sonic-yang-models/tests/yang_model_tests/tests_config/snmp.json +++ b/src/sonic-yang-models/tests/yang_model_tests/tests_config/snmp.json @@ -502,5 +502,126 @@ ] } } + }, + "SNMP_AGENT_ADDRESS_CONFIG": { + "sonic-snmp:sonic-snmp": { + "sonic-snmp:SNMP_AGENT_ADDRESS_CONFIG": { + "SNMP_AGENT_ADDRESS_LIST": [ + { + "agent_ip": "10.0.0.1", + "port": "161", + "vrf_name": "" + } + ] + } + } + }, + "SNMP_AGENT_ADDRESS_CONFIG_IPV6": { + "sonic-snmp:sonic-snmp": { + "sonic-snmp:SNMP_AGENT_ADDRESS_CONFIG": { + "SNMP_AGENT_ADDRESS_LIST": [ + { + "agent_ip": "fd00::1", + "port": "161", + "vrf_name": "" + } + ] + } + } + }, + "SNMP_AGENT_ADDRESS_CONFIG_EMPTY_PORT_NUMBER": { + "sonic-snmp:sonic-snmp": { + "sonic-snmp:SNMP_AGENT_ADDRESS_CONFIG": { + "SNMP_AGENT_ADDRESS_LIST": [ + { + "agent_ip": "10.0.0.1", + "port": "", + "vrf_name": "mgmt" + } + ] + } + } + }, + "SNMP_AGENT_ADDRESS_CONFIG_MGMT_VRF": { + "sonic-snmp:sonic-snmp": { + "sonic-snmp:SNMP_AGENT_ADDRESS_CONFIG": { + "SNMP_AGENT_ADDRESS_LIST": [ + { + "agent_ip": "10.0.0.1", + "port": "161", + "vrf_name": "mgmt" + } + ] + } + } + }, + "SNMP_AGENT_ADDRESS_CONFIG_NO_VRF": { + "sonic-snmp:sonic-snmp": { + "sonic-snmp:SNMP_AGENT_ADDRESS_CONFIG": { + "SNMP_AGENT_ADDRESS_LIST": [ + { + "agent_ip": "10.0.0.1", + "port": "161" + } + ] + } + } + }, + "SNMP_AGENT_ADDRESS_CONFIG_INVALID_PORT": { + "sonic-snmp:sonic-snmp": { + "sonic-snmp:SNMP_AGENT_ADDRESS_CONFIG": { + "SNMP_AGENT_ADDRESS_LIST": [ + { + "agent_ip": "10.0.0.1", + "port": "65536", + "vrf_name": "mgmt" + } + ] + } + } + }, + "SNMP_AGENT_ADDRESS_CONFIG_DUPLICATE_IP_PORT": { + "sonic-snmp:sonic-snmp": { + "sonic-snmp:SNMP_AGENT_ADDRESS_CONFIG": { + "SNMP_AGENT_ADDRESS_LIST": [ + { + "agent_ip": "10.0.0.1", + "port": "161", + "vrf_name": "mgmt" + }, + { + "agent_ip": "10.0.0.1", + "port": "161", + "vrf_name": "" + } + ] + } + } + }, + "SNMP_AGENT_ADDRESS_CONFIG_INVALID_IPV4_ADDRESS": { + "sonic-snmp:sonic-snmp": { + "sonic-snmp:SNMP_AGENT_ADDRESS_CONFIG": { + "SNMP_AGENT_ADDRESS_LIST": [ + { + "agent_ip": "340.1.1.10", + "port": "161", + "vrf_name": "" + } + ] + } + } + }, + "SNMP_AGENT_ADDRESS_CONFIG_INVALID_IPV6_ADDRESS": { + "sonic-snmp:sonic-snmp": { + "sonic-snmp:SNMP_AGENT_ADDRESS_CONFIG": { + "SNMP_AGENT_ADDRESS_LIST": [ + { + "agent_ip": "2001:aa:aa:aa", + "port": "161", + "vrf_name": "" + } + ] + } + } } } diff --git a/src/sonic-yang-models/tests/yang_model_tests/tests_config/sonic-events-host.json b/src/sonic-yang-models/tests/yang_model_tests/tests_config/sonic-events-host.json index 98ee755b510a..886863698392 100644 --- a/src/sonic-yang-models/tests/yang_model_tests/tests_config/sonic-events-host.json +++ b/src/sonic-yang-models/tests/yang_model_tests/tests_config/sonic-events-host.json @@ -3,8 +3,8 @@ "sonic-events-host:sonic-events-host": { "sonic-events-host:disk-usage": { "fs": "FILESYSTEM", - "usage": -30, - "limit": 99, + "usage": "INCORRECT_USAGE", + "limit": "2.0", "timestamp": "1985-04-12T23:20:50.52Z" } } @@ -13,7 +13,7 @@ "sonic-events-host:sonic-events-host": { "sonic-events-host:disk-usage": { "fs": "FILESYSTEM", - "usage": 32, + "usage": "2.0", "limit": "INCORRECT_LIMIT", "timestamp": "1985-04-12T23:20:50.52Z" } @@ -23,8 +23,8 @@ "sonic-events-host:sonic-events-host": { "sonic-events-host:disk-usage": { "fs": "FILESYSTEM", - "usage": 32, - "limit": 99, + "usage": "2.0", + "limit": "2.0", "timestamp": "INCORRECT_TIMESTAMP" } } @@ -33,8 +33,8 @@ "sonic-events-host:sonic-events-host": { "sonic-events-host:disk-usage": { "fs": "FILESYSTEM", - "usage": 32, - "limit": 99, + "usage": "2.0", + "limit": "2.0", "timestamp": "1985-04-12T23:20:50.52Z" } } @@ -42,8 +42,8 @@ "SONIC_EVENTS_HOST_MEMORY_USAGE_INCORRECT_USAGE": { "sonic-events-host:sonic-events-host": { "sonic-events-host:memory-usage": { - "usage": -30, - "limit": 99, + "usage": "INCORRECT_USAGE", + "limit": "2.0", "timestamp": "1985-04-12T23:20:50.52Z" } } @@ -51,7 +51,7 @@ "SONIC_EVENTS_HOST_MEMORY_USAGE_INCORRECT_LIMIT": { "sonic-events-host:sonic-events-host": { "sonic-events-host:memory-usage": { - "usage": 32, + "usage": "2.0", "limit": "INCORRECT_LIMIT", "timestamp": "1985-04-12T23:20:50.52Z" } @@ -60,8 +60,8 @@ "SONIC_EVENTS_HOST_MEMORY_USAGE_INCORRECT_TIMESTAMP": { "sonic-events-host:sonic-events-host": { "sonic-events-host:memory-usage": { - "usage": 32, - "limit": 99, + "usage": "2.0", + "limit": "2.0", "timestamp": "INCORRECT_TIMESTAMP" } } @@ -69,8 +69,8 @@ "SONIC_EVENTS_HOST_MEMORY_USAGE_VALID": { "sonic-events-host:sonic-events-host": { "sonic-events-host:memory-usage": { - "usage": 32, - "limit": 99, + "usage": "2.0", + "limit": "2.0", "timestamp": "1985-04-12T23:20:50.52Z" } } @@ -78,8 +78,8 @@ "SONIC_EVENTS_HOST_CPU_USAGE_INCORRECT_USAGE": { "sonic-events-host:sonic-events-host": { "sonic-events-host:cpu-usage": { - "usage": -30, - "limit": 99, + "usage": "INCORRECT_USAGE", + "limit": "2.0", "timestamp": "1985-04-12T23:20:50.52Z" } } @@ -87,7 +87,7 @@ "SONIC_EVENTS_HOST_CPU_USAGE_INCORRECT_LIMIT": { "sonic-events-host:sonic-events-host": { "sonic-events-host:cpu-usage": { - "usage": 32, + "usage": "2.0", "limit": "INCORRECT_LIMIT", "timestamp": "1985-04-12T23:20:50.52Z" } @@ -96,8 +96,8 @@ "SONIC_EVENTS_HOST_CPU_USAGE_INCORRECT_TIMESTAMP": { "sonic-events-host:sonic-events-host": { "sonic-events-host:cpu-usage": { - "usage": 32, - "limit": 99, + "usage": "2.0", + "limit": "2.0", "timestamp": "INCORRECT_TIMESTAMP" } } @@ -105,8 +105,8 @@ "SONIC_EVENTS_HOST_CPU_USAGE_VALID": { "sonic-events-host:sonic-events-host": { "sonic-events-host:cpu-usage": { - "usage": 32, - "limit": 99, + "usage": "2.0", + "limit": "2.0", "timestamp": "1985-04-12T23:20:50.52Z" } } diff --git a/src/sonic-yang-models/tests/yang_model_tests/tests_config/vlan_sub_interface.json b/src/sonic-yang-models/tests/yang_model_tests/tests_config/vlan_sub_interface.json index 6f200ef4b7ea..bb3ba554e4eb 100644 --- a/src/sonic-yang-models/tests/yang_model_tests/tests_config/vlan_sub_interface.json +++ b/src/sonic-yang-models/tests/yang_model_tests/tests_config/vlan_sub_interface.json @@ -36,7 +36,8 @@ "sonic-vlan-sub-interface:VLAN_SUB_INTERFACE": { "VLAN_SUB_INTERFACE_LIST": [ { - "name": "Eth8.10" + "name": "Eth8.10", + "vlan": 10 } ], "VLAN_SUB_INTERFACE_IPPREFIX_LIST": [ @@ -132,7 +133,8 @@ "sonic-vlan-sub-interface:VLAN_SUB_INTERFACE": { "VLAN_SUB_INTERFACE_LIST": [ { - "name": "Eth8.10" + "name": "Eth8.10", + "vlan": 10 } ], "VLAN_SUB_INTERFACE_IPPREFIX_LIST": [ @@ -164,7 +166,8 @@ "sonic-vlan-sub-interface:VLAN_SUB_INTERFACE": { "VLAN_SUB_INTERFACE_LIST": [ { - "name": "Po0001.10" + "name": "Po0001.10", + "vlan": 10 } ], "VLAN_SUB_INTERFACE_IPPREFIX_LIST": [ @@ -305,7 +308,8 @@ "sonic-vlan-sub-interface:VLAN_SUB_INTERFACE": { "VLAN_SUB_INTERFACE_LIST": [ { - "name": "Po0002.10" + "name": "Po0002.10", + "vlan": 10 } ], "VLAN_SUB_INTERFACE_IPPREFIX_LIST": [ @@ -533,5 +537,37 @@ ] } } + }, + "VLAN_SUB_INTERFACE_SHORT_NAME_FORMAT_VLAN_CHECK_MUST_CONDITION_FALSE_TEST": { + "sonic-vlan-sub-interface:sonic-vlan-sub-interface": { + "sonic-vlan-sub-interface:VLAN_SUB_INTERFACE": { + "VLAN_SUB_INTERFACE_LIST": [ + { + "name": "Eth8.10" + } + ], + "VLAN_SUB_INTERFACE_IPPREFIX_LIST": [ + { + "name": "Eth8.10", + "ip-prefix": "10.0.0.1/30" + } + ] + } + }, + "sonic-port:sonic-port": { + "sonic-port:PORT": { + "PORT_LIST": [ + { + "name": "Ethernet8", + "admin_status": "up", + "alias": "Ethernet8/1", + "description": "Ethernet8", + "lanes": "45,46,47,48", + "mtu": 9000, + "speed": 100000 + } + ] + } + } } } diff --git a/src/sonic-yang-models/yang-models/sonic-bgp-sentinel.yang b/src/sonic-yang-models/yang-models/sonic-bgp-sentinel.yang new file mode 100644 index 000000000000..747aadd2f89e --- /dev/null +++ b/src/sonic-yang-models/yang-models/sonic-bgp-sentinel.yang @@ -0,0 +1,58 @@ +module sonic-bgp-sentinel { + namespace "http://github.com/Azure/sonic-bgp-sentinel"; + prefix pr; + yang-version 1.1; + + import ietf-inet-types { + prefix inet; + } + + import sonic-types { + prefix stypes; + } + + organization + "SONiC"; + + contact + "SONiC"; + + description + "SONIC BGP Sentinel YANG"; + + revision 2023-06-06 { + description + "Initial revision."; + } + + container sonic-bgp-sentinel { + container BGP_SENTINELS { + list BGP_SENTINELS_LIST { + key "sentinel_name"; + + leaf sentinel_name { + type string; + description "BGP Sentinel name"; + } + + leaf name { + type string; + must "(current() = current()/../sentinel_name)" { + error-message "Invalid BGP Sentinel name"; + } + description "BGP Sentinel name"; + } + + leaf src_address { + type inet:ip-address; + description "Source address to use for connection"; + } + + leaf-list ip_range { + type stypes:sonic-ip-prefix; + description "A range of addresses"; + } + } + } + } +} diff --git a/src/sonic-yang-models/yang-models/sonic-events-common.yang b/src/sonic-yang-models/yang-models/sonic-events-common.yang index 778f2ecbda95..ed6c81a7b908 100644 --- a/src/sonic-yang-models/yang-models/sonic-events-common.yang +++ b/src/sonic-yang-models/yang-models/sonic-events-common.yang @@ -30,19 +30,15 @@ module sonic-events-common { grouping sonic-events-usage { leaf usage { - type uint8 { - range "0..100" { - error-message "Incorrect val for %"; - } + type decimal64 { + fraction-digits 1; } description "Percentage in use"; } leaf limit { - type uint8 { - range "0..100" { - error-message "Incorrect val for %"; - } + type decimal64 { + fraction-digits 1; } description "Percentage limit set"; } diff --git a/src/sonic-yang-models/yang-models/sonic-fips.yang b/src/sonic-yang-models/yang-models/sonic-fips.yang new file mode 100644 index 000000000000..0bf96f7b0f13 --- /dev/null +++ b/src/sonic-yang-models/yang-models/sonic-fips.yang @@ -0,0 +1,45 @@ +module sonic-fips { + + yang-version 1.1; + + namespace "http://github.com/sonic-net/sonic-fips"; + + prefix sonic-fips; + + import sonic-types { + prefix stypes; + } + + description "FIPS YANG Module for SONiC OS"; + + revision 2023-06-20 { + description "First Revision"; + } + + container sonic-fips { + + container FIPS { + + description "FIPS part of config_db.json"; + + container global { + + leaf enable { + description "This configuration identicates whether enable fips"; + type stypes:boolean_type; + default "false"; + } + + leaf enforce { + description "This configuration identicates whether enforce fips"; + type stypes:boolean_type; + default "false"; + } + } + /* end of container global */ + } + /* end of container FIPS */ + } + /* end of top level container */ +} +/* end of module sonic-fips */ diff --git a/src/sonic-yang-models/yang-models/sonic-mux-linkmgr.yang b/src/sonic-yang-models/yang-models/sonic-mux-linkmgr.yang index 93e605ea8e51..d7b07ed7335b 100644 --- a/src/sonic-yang-models/yang-models/sonic-mux-linkmgr.yang +++ b/src/sonic-yang-models/yang-models/sonic-mux-linkmgr.yang @@ -83,6 +83,35 @@ module sonic-mux-linkmgr { description "The frequency of streaming ICMP heartbeat loss data to telemetry. "; } } + + container MUXLOGGER { + + leaf log_verbosity { + type enumeration { + enum trace; + enum debug; + enum info; + enum error; + enum fatal; + } + + description "Linkmgrd log verbosity level. "; + } + } + + container SERVICE_MGMT { + + leaf kill_radv { + type enumeration { + enum True; + enum False; + } + + default True; + + description "Kill radv service instead of gracefully stopping it. "; + } + } } } } \ No newline at end of file diff --git a/src/sonic-yang-models/yang-models/sonic-snmp.yang b/src/sonic-yang-models/yang-models/sonic-snmp.yang index f49c28f98050..1579dc1f04d8 100644 --- a/src/sonic-yang-models/yang-models/sonic-snmp.yang +++ b/src/sonic-yang-models/yang-models/sonic-snmp.yang @@ -3,6 +3,12 @@ module sonic-snmp { prefix ssnmp; yang-version 1.1; + import ietf-inet-types { + prefix inet; + } + import sonic-vrf { + prefix vrf; + } organization "SONiC"; @@ -156,5 +162,42 @@ module sonic-snmp { } } } + container SNMP_AGENT_ADDRESS_CONFIG { + list SNMP_AGENT_ADDRESS_LIST { + key "agent_ip port vrf_name"; + unique "agent_ip port"; + description "List of SNMP agent listening IP Addresses and ports."; + + leaf agent_ip { + type inet:ip-address; + description "SNMP agent listening IP"; + } + leaf port { + type union { + type string { + pattern ''; + } + type inet:port-number; + } + default ""; + description "SNMP agent listening port number"; + } + leaf vrf_name { + type union { + type string { + pattern ''; + } + type string { + pattern 'mgmt'; + } + type string { + pattern "Vrf[a-zA-Z0-9_-]+"; + } + } + default ""; + description "VRF name"; + } + } + } } } diff --git a/src/sonic-yang-models/yang-models/sonic-vlan-sub-interface.yang b/src/sonic-yang-models/yang-models/sonic-vlan-sub-interface.yang index 5a7f02c75143..37e5f47a104c 100644 --- a/src/sonic-yang-models/yang-models/sonic-vlan-sub-interface.yang +++ b/src/sonic-yang-models/yang-models/sonic-vlan-sub-interface.yang @@ -37,6 +37,14 @@ module sonic-vlan-sub-interface { description "VLAN_SUB_INTERFACE part of config_db.json with vrf"; + // encap vlan is mandatory for short name subinterfaces + must "(substring-before(name, '.') = /port:sonic-port/port:PORT/port:PORT_LIST/port:name) or " + + "(substring-before(name, '.') = /lag:sonic-portchannel/lag:PORTCHANNEL/lag:PORTCHANNEL_LIST/lag:name) or " + + "vlan" + { + error-message "Must condition not satisfied, no encap vlan provided for short-name format vlan sub interface"; + } + key "name"; leaf name { @@ -70,6 +78,12 @@ module sonic-vlan-sub-interface { description "Packet action when a packet ingress and gets routed on the same IP interface"; type stypes:loopback_action; } + + leaf vlan { + type uint16 { + range 1..4094; + } + } } list VLAN_SUB_INTERFACE_IPPREFIX_LIST { diff --git a/src/system-health/health_checker/hardware_checker.py b/src/system-health/health_checker/hardware_checker.py index 992bdbab545c..8f7a11f55c2e 100644 --- a/src/system-health/health_checker/hardware_checker.py +++ b/src/system-health/health_checker/hardware_checker.py @@ -257,12 +257,13 @@ def _check_psu_status(self, config): if not self._ignore_check(config.ignore_devices, 'psu', name, 'power_threshold'): power_overload = data_dict.get('power_overload', None) if power_overload == 'True': + try: power = data_dict['power'] power_critical_threshold = data_dict['power_critical_threshold'] - self.set_object_not_ok('PSU', name, 'power of {} ({}w) exceeds threshold ({}w)'.format(name, power, power_critical_threshold)) + self.set_object_not_ok('PSU', name, 'System power exceeds threshold ({}w)'.format(power_critical_threshold)) except KeyError: - self.set_object_not_ok('PSU', name, 'power of {} exceeds threshold but power or power_critical_threshold is invalid'.format(name)) + self.set_object_not_ok('PSU', name, 'System power exceeds threshold but power_critical_threshold is invalid') continue self.set_object_ok('PSU', name) diff --git a/src/system-health/tests/test_system_health.py b/src/system-health/tests/test_system_health.py index 10bdf3d7d9f8..2d46140e2ff6 100644 --- a/src/system-health/tests/test_system_health.py +++ b/src/system-health/tests/test_system_health.py @@ -444,12 +444,12 @@ def test_hardware_checker(): assert checker._info['PSU 5'][HealthChecker.INFO_FIELD_OBJECT_STATUS] == HealthChecker.STATUS_NOT_OK assert 'PSU 6' in checker._info - assert checker._info['PSU 6'][HealthChecker.INFO_FIELD_OBJECT_MSG] == 'power of PSU 6 (101.0w) exceeds threshold (100.0w)' + assert checker._info['PSU 6'][HealthChecker.INFO_FIELD_OBJECT_MSG] == 'System power exceeds threshold (100.0w)' assert checker._info['PSU 6'][HealthChecker.INFO_FIELD_OBJECT_STATUS] == HealthChecker.STATUS_NOT_OK assert 'PSU 7' in checker._info assert checker._info['PSU 7'][HealthChecker.INFO_FIELD_OBJECT_STATUS] == HealthChecker.STATUS_NOT_OK - assert checker._info['PSU 7'][HealthChecker.INFO_FIELD_OBJECT_MSG] == 'power of PSU 7 exceeds threshold but power or power_critical_threshold is invalid' + assert checker._info['PSU 7'][HealthChecker.INFO_FIELD_OBJECT_MSG] == 'System power exceeds threshold but power_critical_threshold is invalid' def test_config():