In systems built with an Incoming Message-Signaled Interrupt Controller (IMSIC), the IOPMP can trigger message-signaled interrupts (MSI) by writing a word of data to a specific physical address. The address is MSI address and is specified by ERR_MSIADDR and ERR_MSIADDRH (implemented only when HWCFG0.addrh_en = 1), while the content to write is stored in the field msidata in the register ERR_CFG. The ERR_MSIADDR, ERR_MSIADDRH, and ERR_CFG are locked by the ERR_CFG.l.
ERR_MSIADDRH is available if the target address of IMSIC uses over 34 bits (greater than 0x2_0000_0000). ERR_MSIADDR encodes bit 31 to bit 0 of the address, while ERR_MSIADDRH encodes bit 63 to bit 32. When the target address of IMSIC uses less than or equal to 34 bits, ERR_MSIADDR encodes bit 33 to bit 2. ERR_MSIADDRH is available only when HWCFG0.addrh_en = 1 and ERR_CFG.msi_en = 1.
The bit ERR_CFG.msi_en indicates whether the IOPMP triggers interrupt by MSI or wired interrupt. IOPMP triggers MSI when ERR_CFG.msi_en = 1 and triggers wired interrupt when ERR_CFG.msi_en = 0. ERR_MSIADDR, ERR_MSIADDRH, and ERR_CFG.msidata are not necessary available when ERR_CFG.msi_en = 0. ERR_CFG.msi_en can be programmable or hardwired.
ERR_INFO.msi_werr indicates whether a write access to trigger an IOPMP-originated MSI has failed. It is asserted when the write access to trigger an IOPMP-originated MSI has failed. When it’s not available, it should be zero. Writing 1 to ERR_INFO.msi_werr clears the bit.