From a4cda877efdc5f2d19ad05252b16c57a76aea782 Mon Sep 17 00:00:00 2001
From: Rose Thompson <rose@rosethompson.net>
Date: Mon, 21 Oct 2024 14:52:40 -0500
Subject: [PATCH] Fixed bit position of SPI fifo receive and transmit flags.

---
 src/uncore/spi_apb.sv | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/uncore/spi_apb.sv b/src/uncore/spi_apb.sv
index 91021e2b6d..57260e769f 100644
--- a/src/uncore/spi_apb.sv
+++ b/src/uncore/spi_apb.sv
@@ -221,8 +221,8 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
                 SPI_DELAY0:  Dout <= {8'b0, Delay0[15:8], 8'b0, Delay0[7:0]};
                 SPI_DELAY1:  Dout <= {8'b0, Delay1[15:8], 8'b0, Delay1[7:0]};
                 SPI_FMT:     Dout <= {12'b0, Format[4:1], 13'b0, Format[0], 2'b0};
-                SPI_TXDATA:  Dout <= {23'b0, TransmitFIFOWriteFull, 8'b0};
-                SPI_RXDATA:  Dout <= {23'b0, ReceiveFIFOReadEmpty, ReceiveData[7:0]};
+                SPI_TXDATA:  Dout <= {TransmitFIFOWriteFull, 23'b0, 8'b0};
+                SPI_RXDATA:  Dout <= {ReceiveFIFOReadEmpty, 23'b0, ReceiveData[7:0]};
                 SPI_TXMARK:  Dout <= {29'b0, TransmitWatermark};
                 SPI_RXMARK:  Dout <= {29'b0, ReceiveWatermark};
                 SPI_IE:      Dout <= {30'b0, InterruptEnable};