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There is currently no support for SPI operations (in a transaction slice) to mutably share data.
Use case: SPI devices often implement the following behavior (happy to provide numerous examples if this is in doubt) to implement an atomic update of several bits.
Load "active" bits into the SPI shift register (that sits between SDI and SDO) on CS assertion.
Load new bits from shift register into "active" register on CS deassertion.
The intention is to implement a read of the active bits without altering them (not even a transient alteration).
The approach would be to keep CS asserted accross a transaction of reading and writing the same values again.
There is currently no support for SPI operations (in a transaction slice) to mutably share data.
Use case: SPI devices often implement the following behavior (happy to provide numerous examples if this is in doubt) to implement an atomic update of several bits.
The intention is to implement a read of the active bits without altering them (not even a transient alteration).
The approach would be to keep CS asserted accross a transaction of reading and writing the same values again.
This is currently not possible with the
Operation
enum.The text was updated successfully, but these errors were encountered: