diff --git a/svd-encoder/CHANGELOG.md b/svd-encoder/CHANGELOG.md
index 2ce2f947..cdf42a8b 100644
--- a/svd-encoder/CHANGELOG.md
+++ b/svd-encoder/CHANGELOG.md
@@ -7,6 +7,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## Unreleased
 
+## [v0.13.0] - 2022-01-02
+
+- Bump `svd-rs`
+
 ## [v0.12.0] - 2021-11-11
 
 - Bump `svd-rs`
diff --git a/svd-encoder/Cargo.toml b/svd-encoder/Cargo.toml
index 84f587f3..2fe7703a 100644
--- a/svd-encoder/Cargo.toml
+++ b/svd-encoder/Cargo.toml
@@ -9,11 +9,11 @@ license = "MIT OR Apache-2.0"
 name = "svd-encoder"
 repository = "https://github.com/rust-embedded/svd"
 edition = "2018"
-version = "0.12.0"
+version = "0.13.0"
 readme = "README.md"
 
 [dependencies]
-svd-rs = { version = "0.12.0", path = "../svd-rs"}
+svd-rs = { version = "0.13.0", path = "../svd-rs"}
 thiserror = "1.0.30"
 
 [dependencies.xmltree]
diff --git a/svd-parser/CHANGELOG.md b/svd-parser/CHANGELOG.md
index 819bf4a8..c9616f2a 100644
--- a/svd-parser/CHANGELOG.md
+++ b/svd-parser/CHANGELOG.md
@@ -7,6 +7,11 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## Unreleased
 
+## [v0.13.0] - 2022-01-02
+
+- Add `svd2yaml` example
+- Bump `svd-rs`
+
 ## [v0.12.0] - 2021-11-11
 
 - Bump `svd-rs`
diff --git a/svd-parser/Cargo.toml b/svd-parser/Cargo.toml
index b4e85cf4..2194d23d 100644
--- a/svd-parser/Cargo.toml
+++ b/svd-parser/Cargo.toml
@@ -10,14 +10,14 @@ license = "MIT OR Apache-2.0"
 name = "svd-parser"
 repository = "https://github.com/rust-embedded/svd"
 edition = "2018"
-version = "0.12.0"
+version = "0.13.0"
 readme = "README.md"
 
 [features]
 derive-from = ["svd-rs/derive-from"]
 
 [dependencies]
-svd-rs = { version = "0.12.0", path = "../svd-rs"}
+svd-rs = { version = "0.13.0", path = "../svd-rs"}
 roxmltree = "0.14.1"
 anyhow = "1.0.45"
 thiserror = "1.0.30"
@@ -25,7 +25,7 @@ thiserror = "1.0.30"
 [dev-dependencies]
 serde_json = { version = "1.0", features = ["preserve_order"] }
 serde_yaml = "0.8.23"
-svd-rs = { version = "0.12.0", path = "../svd-rs", features = ["serde"] }
+svd-rs = { version = "0.13.0", path = "../svd-rs", features = ["serde"] }
 
 [[example]]
 name = "svd2json"
diff --git a/svd-rs/CHANGELOG.md b/svd-rs/CHANGELOG.md
index 18a39b5e..975ff86b 100644
--- a/svd-rs/CHANGELOG.md
+++ b/svd-rs/CHANGELOG.md
@@ -7,6 +7,9 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## Unreleased
 
+## [v0.13.0] - 2022-01-02
+
+- skip serializing optional fields in `Cpu` if empty
 - skip serializing `values` in `EnumeratedValues` if empty
 - add missing fields in `Device`, require `version`, `description`, `address_unit_bits` and `width`,
   also `schema_version` is required, but skipped during (de)serialization
diff --git a/svd-rs/Cargo.toml b/svd-rs/Cargo.toml
index 7fc1e24b..5592db99 100644
--- a/svd-rs/Cargo.toml
+++ b/svd-rs/Cargo.toml
@@ -9,7 +9,7 @@ license = "MIT OR Apache-2.0"
 name = "svd-rs"
 repository = "https://github.com/rust-embedded/svd"
 edition = "2018"
-version = "0.12.1"
+version = "0.13.0"
 readme = "README.md"
 
 [features]
diff --git a/svd-rs/src/cpu.rs b/svd-rs/src/cpu.rs
index c2c7f318..8d11f044 100644
--- a/svd-rs/src/cpu.rs
+++ b/svd-rs/src/cpu.rs
@@ -25,26 +25,53 @@ pub struct Cpu {
 
     /// Indicate whether the processor is equipped with a double precision floating point unit.
     /// This element is valid only when `fpu_present` is set to `true`
-    #[cfg_attr(feature = "serde", serde(rename = "fpuDP"))]
+    #[cfg_attr(
+        feature = "serde",
+        serde(default, skip_serializing_if = "Option::is_none", rename = "fpuDP")
+    )]
     pub fpu_double_precision: Option<bool>,
 
     /// Indicates whether the processor implements the optional SIMD DSP extensions (DSP)
+    #[cfg_attr(
+        feature = "serde",
+        serde(default, skip_serializing_if = "Option::is_none")
+    )]
     pub dsp_present: Option<bool>,
 
     /// Indicate whether the processor has an instruction cache
+    #[cfg_attr(
+        feature = "serde",
+        serde(default, skip_serializing_if = "Option::is_none")
+    )]
     pub icache_present: Option<bool>,
 
     /// Indicate whether the processor has a data cache
+    #[cfg_attr(
+        feature = "serde",
+        serde(default, skip_serializing_if = "Option::is_none")
+    )]
     pub dcache_present: Option<bool>,
 
     /// Indicate whether the processor has an instruction tightly coupled memory
+    #[cfg_attr(
+        feature = "serde",
+        serde(default, skip_serializing_if = "Option::is_none")
+    )]
     pub itcm_present: Option<bool>,
 
     /// Indicate whether the processor has a data tightly coupled memory
+    #[cfg_attr(
+        feature = "serde",
+        serde(default, skip_serializing_if = "Option::is_none")
+    )]
     pub dtcm_present: Option<bool>,
 
     /// Indicate whether the Vector Table Offset Register (VTOR) is implemented.
     /// If not specified, then VTOR is assumed to be present
+    #[cfg_attr(
+        feature = "serde",
+        serde(default, skip_serializing_if = "Option::is_none")
+    )]
     pub vtor_present: Option<bool>,
 
     /// Define the number of bits available in the Nested Vectored Interrupt Controller (NVIC) for configuring priority
@@ -56,9 +83,17 @@ pub struct Cpu {
     pub has_vendor_systick: bool,
 
     /// Add 1 to the highest interrupt number and specify this number in here
+    #[cfg_attr(
+        feature = "serde",
+        serde(default, skip_serializing_if = "Option::is_none")
+    )]
     pub device_num_interrupts: Option<u32>,
 
     /// Indicate the amount of regions in the Security Attribution Unit (SAU)
+    #[cfg_attr(
+        feature = "serde",
+        serde(default, skip_serializing_if = "Option::is_none")
+    )]
     pub sau_num_regions: Option<u32>,
     // sauRegionsConfig
 }