From bec3a545a55590dd8029bad61d5ea18416c4caf8 Mon Sep 17 00:00:00 2001 From: jam1garner Date: Mon, 18 Jul 2022 20:40:41 -0400 Subject: [PATCH] Add support for MIPS VZ ISA extension --- compiler/rustc_codegen_llvm/src/llvm_util.rs | 4 ++++ compiler/rustc_codegen_ssa/src/target_features.rs | 7 +++++-- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/compiler/rustc_codegen_llvm/src/llvm_util.rs b/compiler/rustc_codegen_llvm/src/llvm_util.rs index a0a640473eb51..47590c8578c56 100644 --- a/compiler/rustc_codegen_llvm/src/llvm_util.rs +++ b/compiler/rustc_codegen_llvm/src/llvm_util.rs @@ -165,6 +165,10 @@ pub fn time_trace_profiler_finish(file_name: &Path) { // // To find a list of LLVM's names, check llvm-project/llvm/include/llvm/Support/*TargetParser.def // where the * matches the architecture's name +// +// For targets not present in the above location, see llvm-project/llvm/lib/Target/{ARCH}/*.td +// where `{ARCH}` is the architecture name. Look for instances of `SubtargetFeature`. +// // Beware to not use the llvm github project for this, but check the git submodule // found in src/llvm-project // Though note that Rust can also be build with an external precompiled version of LLVM diff --git a/compiler/rustc_codegen_ssa/src/target_features.rs b/compiler/rustc_codegen_ssa/src/target_features.rs index bfdef2dc0e80c..a3ad6a3fcbd40 100644 --- a/compiler/rustc_codegen_ssa/src/target_features.rs +++ b/compiler/rustc_codegen_ssa/src/target_features.rs @@ -210,8 +210,11 @@ const POWERPC_ALLOWED_FEATURES: &[(&str, Option)] = &[ ("vsx", Some(sym::powerpc_target_feature)), ]; -const MIPS_ALLOWED_FEATURES: &[(&str, Option)] = - &[("fp64", Some(sym::mips_target_feature)), ("msa", Some(sym::mips_target_feature))]; +const MIPS_ALLOWED_FEATURES: &[(&str, Option)] = &[ + ("fp64", Some(sym::mips_target_feature)), + ("msa", Some(sym::mips_target_feature)), + ("virt", Some(sym::mips_target_feature)), +]; const RISCV_ALLOWED_FEATURES: &[(&str, Option)] = &[ ("m", Some(sym::riscv_target_feature)),