diff --git a/compiler/rustc_codegen_llvm/src/intrinsic.rs b/compiler/rustc_codegen_llvm/src/intrinsic.rs index 9705dd506b97b..15c519dfcb4a3 100644 --- a/compiler/rustc_codegen_llvm/src/intrinsic.rs +++ b/compiler/rustc_codegen_llvm/src/intrinsic.rs @@ -2066,14 +2066,14 @@ fn generic_simd_intrinsic<'ll, 'tcx>( }; } - arith_red!(simd_reduce_add_ordered: vector_reduce_add, vector_reduce_fadd, true, add, 0.0); + arith_red!(simd_reduce_add_ordered: vector_reduce_add, vector_reduce_fadd, true, add, -0.0); arith_red!(simd_reduce_mul_ordered: vector_reduce_mul, vector_reduce_fmul, true, mul, 1.0); arith_red!( simd_reduce_add_unordered: vector_reduce_add, vector_reduce_fadd_reassoc, false, add, - 0.0 + -0.0 ); arith_red!( simd_reduce_mul_unordered: vector_reduce_mul, diff --git a/compiler/rustc_target/src/spec/targets/armv8r_none_eabihf.rs b/compiler/rustc_target/src/spec/targets/armv8r_none_eabihf.rs index 042a9a140710c..762084291a696 100644 --- a/compiler/rustc_target/src/spec/targets/armv8r_none_eabihf.rs +++ b/compiler/rustc_target/src/spec/targets/armv8r_none_eabihf.rs @@ -21,16 +21,16 @@ pub(crate) fn target() -> Target { linker: Some("rust-lld".into()), relocation_model: RelocModel::Static, panic_strategy: PanicStrategy::Abort, - // The Cortex-R52 has two variants with respect to floating-point support: - // 1. fp-armv8, SP-only, with 16 DP (32 SP) registers - // 2. neon-fp-armv8, SP+DP, with 32 DP registers - // Use the lesser of these two options as the default, as it will produce code - // compatible with either variant. + // Armv8-R requires a minimum set of floating-point features equivalent to: + // fp-armv8, SP-only, with 16 DP (32 SP) registers + // LLVM defines Armv8-R to include these features automatically. + // + // The Cortex-R52 supports these default features and optionally includes: + // neon-fp-armv8, SP+DP, with 32 DP registers // // Reference: // Arm Cortex-R52 Processor Technical Reference Manual // - Chapter 15 Advanced SIMD and floating-point support - features: "+fp-armv8,-fp64,-d32".into(), max_atomic_width: Some(64), emit_debug_gdb_scripts: false, // GCC defaults to 8 for arm-none here. diff --git a/compiler/rustc_transmute/src/layout/tree.rs b/compiler/rustc_transmute/src/layout/tree.rs index c3fd771b79734..b5ce465a1739f 100644 --- a/compiler/rustc_transmute/src/layout/tree.rs +++ b/compiler/rustc_transmute/src/layout/tree.rs @@ -175,7 +175,7 @@ pub(crate) mod rustc { use rustc_middle::ty::{self, AdtDef, AdtKind, List, ScalarInt, Ty, TyCtxt, TypeVisitableExt}; use rustc_span::ErrorGuaranteed; use rustc_target::abi::{ - FieldIdx, FieldsShape, Layout, Size, TyAndLayout, VariantIdx, Variants, + FieldIdx, FieldsShape, Layout, Size, TagEncoding, TyAndLayout, VariantIdx, Variants, }; use super::Tree; @@ -319,11 +319,17 @@ pub(crate) mod rustc { assert!(def.is_enum()); // Computes the variant of a given index. - let layout_of_variant = |index| { + let layout_of_variant = |index, encoding: Option>| { let tag = cx.tcx.tag_for_variant((cx.tcx.erase_regions(ty), index)); let variant_def = Def::Variant(def.variant(index)); let variant_layout = ty_variant(cx, (ty, layout), index); - Self::from_variant(variant_def, tag, (ty, variant_layout), layout.size, cx) + Self::from_variant( + variant_def, + tag.map(|tag| (tag, index, encoding.unwrap())), + (ty, variant_layout), + layout.size, + cx, + ) }; // We consider three kinds of enums, each demanding a different @@ -345,9 +351,9 @@ pub(crate) mod rustc { Variants::Single { index } => { // `Variants::Single` on enums with variants denotes that // the enum delegates its layout to the variant at `index`. - layout_of_variant(*index) + layout_of_variant(*index, None) } - Variants::Multiple { tag_field, .. } => { + Variants::Multiple { tag, tag_encoding, tag_field, .. } => { // `Variants::Multiple` denotes an enum with multiple // variants. The layout of such an enum is the disjunction // of the layouts of its tagged variants. @@ -359,7 +365,7 @@ pub(crate) mod rustc { let variants = def.discriminants(cx.tcx()).try_fold( Self::uninhabited(), |variants, (idx, ref discriminant)| { - let variant = layout_of_variant(idx)?; + let variant = layout_of_variant(idx, Some(tag_encoding.clone()))?; Result::::Ok(variants.or(variant)) }, )?; @@ -380,7 +386,7 @@ pub(crate) mod rustc { /// `0`. fn from_variant( def: Def<'tcx>, - tag: Option, + tag: Option<(ScalarInt, VariantIdx, TagEncoding)>, (ty, layout): (Ty<'tcx>, Layout<'tcx>), total_size: Size, cx: LayoutCx<'tcx, TyCtxt<'tcx>>, @@ -400,9 +406,18 @@ pub(crate) mod rustc { let mut struct_tree = Self::def(def); // If a `tag` is provided, place it at the start of the layout. - if let Some(tag) = tag { - size += tag.size(); - struct_tree = struct_tree.then(Self::from_tag(tag, cx.tcx)); + if let Some((tag, index, encoding)) = &tag { + match encoding { + TagEncoding::Direct => { + size += tag.size(); + } + TagEncoding::Niche { niche_variants, .. } => { + if !niche_variants.contains(index) { + size += tag.size(); + } + } + } + struct_tree = struct_tree.then(Self::from_tag(*tag, cx.tcx)); } // Append the fields, in memory order, to the layout. diff --git a/tests/assembly/simd/reduce-fadd-unordered.rs b/tests/assembly/simd/reduce-fadd-unordered.rs new file mode 100644 index 0000000000000..25e9ad7dc57c4 --- /dev/null +++ b/tests/assembly/simd/reduce-fadd-unordered.rs @@ -0,0 +1,36 @@ +//@ revisions: x86_64 x86_64-avx2 aarch64 +//@ assembly-output: emit-asm +//@ compile-flags: --crate-type=lib -O +//@[aarch64] only-aarch64 +//@[x86_64] only-x86_64 +//@[x86_64-avx2] only-x86_64 +//@[x86_64-avx2] compile-flags: -Ctarget-cpu=x86-64-v3 +#![feature(portable_simd)] +#![feature(core_intrinsics)] +use std::intrinsics::simd as intrinsics; +use std::simd::*; +// Regression test for https://github.com/rust-lang/rust/issues/130028 +// This intrinsic produces much worse code if you use +0.0 instead of -0.0 because +// +0.0 isn't as easy to algebraically reassociate, even using LLVM's reassoc attribute! +// It would emit about an extra fadd, depending on the architecture. + +// CHECK-LABEL: reduce_fadd_negative_zero +pub unsafe fn reduce_fadd_negative_zero(v: f32x4) -> f32 { + // x86_64: addps + // x86_64-NEXT: movaps + // x86_64-NEXT: shufps + // x86_64-NEXT: addss + // x86_64-NOT: xorps + + // x86_64-avx2: vaddps + // x86_64-avx2-NEXT: vmovshdup + // x86_64-avx2-NEXT: vaddss + // x86_64-avx2-NOT: vxorps + + // aarch64: faddp + // aarch64-NEXT: faddp + + // CHECK-NOT: {{f?}}add{{p?s*}} + // CHECK: ret + intrinsics::simd_reduce_add_unordered(v) +} diff --git a/tests/crashes/123693.rs b/tests/crashes/123693.rs deleted file mode 100644 index c3236322c6e2a..0000000000000 --- a/tests/crashes/123693.rs +++ /dev/null @@ -1,22 +0,0 @@ -//@ known-bug: #123693 - -#![feature(transmutability)] - -mod assert { - use std::mem::{Assume, TransmuteFrom}; - - pub fn is_transmutable() - where - Dst: TransmuteFrom, - { - } -} - -enum Lopsided { - Smol(()), - Lorg(bool), -} - -fn should_pad_variants() { - assert::is_transmutable::(); -} diff --git a/tests/ui/transmutability/enums/niche_optimization.rs b/tests/ui/transmutability/enums/niche_optimization.rs index 802d174756868..2436be500279f 100644 --- a/tests/ui/transmutability/enums/niche_optimization.rs +++ b/tests/ui/transmutability/enums/niche_optimization.rs @@ -154,3 +154,12 @@ fn no_niche() { assert::is_transmutable::>, OptionLike>(); assert::is_transmutable::>, OptionLike>(); } + +fn niche_fields() { + enum Kind { + A(bool, bool), + B(bool), + } + + assert::is_maybe_transmutable::(); +}