README.md

LiteX Ethernet

Basic vexriscv/picorv32 SoC with Ethernet connectivity generated by LiteX.

UART is 8N1 115200 baud with TX on J19 DATA_LED- and RX on J19 KEY+. Default Ethernet IP is 192.168.1.20 which is configurable through the Makefile.

Resources

• trabucayre/litexOnColorlightLab004
• Running RISC-V core on small FPGA board
• GuzTech/colorlight_5a_75b.py
• enjoy-digital/colorlite