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OpenPhySyn

OpenPhySyn is a physical synthesis optimization kit developed at Brown University SCALE lab as part of the OpenROAD flow.

Reference

If you use OpenPhySyn in your research or exeperimental evaluation, please cite OpenPhySyn's paper as:

@inproceedings{agiza2020openphysyn,
  title={Openphysyn: An open-source physical synthesis optimization toolkit},
  author={Agiza, Ahmed and Reda, Sherief},
  booktitle={2020 Workshop on Open-Source EDA Technology (WOSET)},
  year={2020}
}

Building

Clone and build OpenPhySyn using the following commands:

git clone --recursive https://github.com/scale-lab/OpenPhySyn.git
cd OpenPhySyn
mkdir build && cd build
cmake ..
make
make install # Or sudo make install
Psn
make test # Runs the unit tests

Dependencies

OpenPhySyn depends on the following libraries:

Docker Instructions

You can run OpenPhySyn inside Docker using the provided Dockerfile

docker build -t scale/openphysyn .
docker run --rm -itu $(id -u ${USER}):$(id -g ${USER}) -v $(pwd):/OpenPhySyn scale/openphysyn bash
Psn ./tests/tcl/getting_started.tcl

Getting Started

Read design and run a transform:

Psn
import_lef <lef file>
import_def <def file>
transform <transform name> <arguments...>
export_def <def file>

Example: Repair design timing violations

Psn ; # or ./build/Psn if not installed in the global path

import_lib ./tests/data/libraries/Nangate45/NangateOpenCellLibrary_typical.lib
import_lef ./tests/data/libraries/Nangate45/NangateOpenCellLibrary.mod.lef
import_def ./tests/data/designs/timing_buffer/ibex_gp.def
read_sdc ./tests/data/designs/timing_buffer/ibex_tight_clk.sdc

set_wire_rc 1.0e-03 1.0e-03 ; # or set_wire_rc <metal layer>

puts "=============== Initial Reports ============="
report_checks
report_check_types -max_slew -max_capacitance -violators
puts "Capacitance violations: [llength [capacitance_violations]]"
puts "Transition violations: [llength [transition_violations]]"
report_wns
report_tns

puts "Initial area: [expr round([design_area] * 10E12) ] um2"

puts "OpenPhySyn timing repair:"
repair_timing

puts "=============== Final Reports ============="
report_checks
report_check_types -max_slew -max_capacitance -violators
puts "Capacitance violations: [llength [capacitance_violations]]"
puts "Transition violations: [llength [transition_violations]]"
report_wns
report_tns

puts "Final area: [expr round([design_area] * 10E12) ] um2"

puts "Export optimized design"
export_def optimized.def

exit 0

You can also run the previous example from a Tcl script: ./build/Psn ./tests/tcl/getting_started.tcl

List available commands:

> Psn
> help
design_area			Report design total cell area
export_db			Export OpenDB database file
export_def			Export design DEF file
gate_clone			Perform load-driven gate cloning
get_database			Return OpenDB database object
get_database_handler		Return OpenPhySyn database handler
get_handler			Alias for get_database_handler
get_liberty			Return first loaded liberty file
has_transform			Check if the specified transform is loaded
help				Print this help
import_db			Import OpenDB database file
import_def			Import design DEF file
import_lef			Import technology LEF file
import_lib			Alias for import_liberty
import_liberty			Import liberty file
link				Alias for link_design
link_design			Link design top module
make_steiner_tree		Create steiner tree around net
optimize_design			Perform timing optimization
optimize_fanout			Perform maximum-fanout based buffering
optimize_logic			Perform logic optimization
optimize_power			Perform power optimization
pin_swap			Perform timing optimization by commutative pin swapping
print_liberty_cells		Print liberty cells available in the  loaded library
print_license			Print license information
print_transforms		Print loaded transforms
print_usage			Print usage instructions
print_version			Print tool version
propagate_constants		Perform logic optimization by constant propgation
timing_buffer			Repair violations through buffer tree insertion
repair_timing			Repair design timing and electrical violations through resizing, buffer insertion, and pin-swapping
capacitance_violations		Print pins with capacitance limit violation
transition_violations		Print pins with transition limit violation
set_log				Alias for set_log_level
set_log_level			Set log level [trace, debug, info, warn, error, critical, off]
set_log_pattern			Set log printing pattern, refer to spdlog logger for pattern formats
set_max_area			Set maximum design area
set_wire_rc			Set wire resistance/capacitance per micron, you can also specify technology layer
transform			Run loaded transform
version				Alias for print_version

List loaded transforms:

Psn
print_transforms

Print usage information for a transform:

Psn
transform <transform name> help

Running OpenSTA commands:

Psn
import_lef <lef file>
import_def <def file>
create_clock [get_ports clk] -name core_clock -period 10
report_checks

Default Transforms

By default, the following transforms are built with OpenPhySyn:

  • buffer_fanout: adds buffers to high fan-out nets.
  • gate_clone: performs load driven gate cloning.
  • pin_swap: performs timing-driven/power-driven commutative pin-swapping optimization.
  • constant_propagation: perform constant propagation optimization across the design hierarchy.
  • timing_buffer: perform van Ginneken based buffer tree insertion to fix capacitance and transition violations.
  • repair_timing: repair design timing and electrical violations through resizing, buffer insertion, and pin-swapping.

Fixing Timing Violations

The repair_timing command repairs negative slack, maximum capacitance and transition violations by buffer tree insertion, gate sizing, and pin-swapping.

repair_timing options:

  • [-capacitance_violations]: Repair capacitance violations.
  • [-transition_violations]: Repair transition violations.
  • [-fanout_violations]: Repair fanout violations.
  • [-negative_slack_violations]: Repair paths with negative slacks.
  • [-iterations iterations]: Maximum number of iterations.
  • [-buffers buffer_cells]: Manually specify buffer cells to use.
  • [-inverters inverter cells]: Manually specify inverter cells to use.
  • [-auto_buffer_library <single|small|medium|large|all>]: Auto-select buffer library.
  • [-no_minimize_buffer_library]: Do not run initial pruning phase for buffer selection.
  • [-auto_buffer_library_inverters_enabled]: Include inverters in the selected buffer library.
  • [-buffer_disabled]: Disable all buffering.
  • [-resize_disabled]: Disable driver sizing.
  • [-pin_swap_disabled]: Disable pin-swapping.
  • [-transition_pessimism_factor factor] Scaling factor for transition violation limits, default is 1.0, should be non-negative, < 1.0 is pessimistic, 1.0 is ideal, > 1.0 is optimistic (default is 1.0).
  • [-capacitance_pessimism_factor factor] Scaling factor for capacitance violation limits, default is 1.0, should be non-negative, < 1.0 is pessimistic, 1.0 is ideal, > 1.0 is optimistic (default is 1.0).
  • [-minimum_cost_buffer_enabled]: Enable minimum cost buffering.
  • [-legalization_frequency <num_edits>]: Legalize after how many edits (has no effect without plugging a legalizer).
  • [-legalize_eventually]: Legalize at the end of the optimization (has no effect without plugging a legalizer).
  • [-legalize_each_iteration]: Legalize after each iteration (has no effect without plugging a legalizer).
  • [-post_place|-post_route]: Post-placement phase mode or post-routing phase mode (post-routing is not currently supported).
  • [-minimum_gain <unit_time>]: Minimum slack gain to accept an optimization.
  • [-high_effort]: Trade-off runtime versus optimization quality by weaker pruning.
  • [-no_resize_for_negative_slack]: Disable resizing when solving negative slack violations (enhances runtime).
  • [-maximum_negative_slack_paths count]: Maximum number of negative slack paths to try to optimize.
  • [-maximum_negative_slack_path_depth count]: Maximum depth per negative slack path to try to optimize.
  • [-pins pin_names]: Manually select the pins to optimize.

Note: you should run the design through an external legalization pass after the optimization when running without plugging a legalizer or using legalization flags.

Example Code

Refer to the provided tests directory for C++ example code.

You can also refer to the tcl tests directory for examples for using the Tcl API.

Building Custom Transforms

For examples to add new transforms, check the standard transforms directory and the corresponding project configuration.

Issues

Please open a GitHub issue if you find any bugs.