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verilog.tmLanguage.json
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verilog.tmLanguage.json
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{
"scopeName": "source.verilog",
"fileTypes": ["v", "vh", "sv", "svh", "svi", "vlib", "vp", "svp"],
"patterns": [
{
"name": "keyword.control.verilog",
"match": "\\b(accept_on|alias|always|always_comb|always_ff|always_latch|and|assert|assign|assume|automatic|before|begin|bind|bins|binsof|bit|break|buf|bufif0|bufif1|byte|case|casex|casez|cell|chandle|checker|class|clocking|cmos|config|const|constraint|context|continue|cover|covergroup|coverpoint|cross|deassign|default|defparam|design|disable|dist|do|edge|else|end|endcase|endchecker|endclass|endclocking|endconfig|endfunction|endgenerate|endgroup|endinterface|endmodule|endpackage|endprimitive|endprogram|endproperty|endsequence|endspecify|endtable|endtask|enum|event|eventually|expect|export|extends|extern|final|first_match|for|force|foreach|forever|fork|forkjoin|function|generate|genvar|global|highz0|highz1|if|iff|ifnone|ignore_bins|illegal_bins|implements|implies|import|initial|inout|input|inside|instance|int|integer|interconnect|interface|intersect|join|join_any|join_none|large|let|liblist|local|localparam|logic|longint|macromodule|matches|medium|modport|module|nand|negedge|nettype|new|nexttime|nmos|nor|noshowcancelled|not|notif0|notif1|null|or|output|package|packed|parameter|pmos|posedge|primitive|priority|program|property|protected|pull0|pull1|pulldown|pullup|pulsestyle_ondetect|pulsestyle_onevent|pure|rand|randc|randcase|randsequence|rcmos|real|realtime|ref|reg|reject_on|release|repeat|restrict|return|rnmos|rpmos|rtran|rtranif0|rtranif1|s_always|s_eventually|s_nexttime|s_until|s_until_with|scalared|sequence|shortint|shortreal|showcancelled|signed|small|soft|solve|specify|specparam|static|string|strong|strong0|strong1|struct|super|supply0|supply1|sync_accept_on|sync_reject_on|table|tagged|task|this|throughout|time|timeprecision|timeunit|tran|tranif0|tranif1|tri|tri0|tri1|triand|trior|trireg|type|typedef|union|unique|unique0|unsigned|until|until_with|untyped|use|uwire|var|vectored|virtual|void|wait|wait_order|wand|weak|weak0|weak1|while|wildcard|wire|with|within|wor|xnor|xor)\\b"
},
{
"name": "support.function.path_pulse.verilog",
"match": "PATHPULSE\\$([a-z]|[A-Z]|_)([a-z]|[A-Z]|_|[0-9]|\\$)*"
},
{
"name": "variable.other.constant.macro.verilog",
"match": "`(([a-z]|[A-Z]|_)([a-z]|[A-Z]|_|[0-9]|\\$)*|\\\\(`[^\\\"\\s \\\t\\\r\\\n]|[^`\\s \\\t\\\r\\\n])[^\\s \\\t\\\r\\\n]+)"
},
{
"name": "variable.other.constant.incomplete_macro.verilog",
"match": "`"
},
{
"name": "support.function.system_id.verilog",
"match": "\\$([a-z]|[A-Z]|_|[0-9]|\\$)+"
},
{
"name": "identifier.valid.verilog",
"match": "(([a-z]|[A-Z]|_)([a-z]|[A-Z]|_|[0-9]|\\$)*|\\\\[^\\s \\\t\\\r\\\n]+)"
},
{
"name": "constant.numeric.time_literal.verilog",
"match": "[0-9]([0-9]|_)*(\\.[0-9]([0-9]|_)*)?(s|ms|us|ns|ps|fs)"
},
{
"name": "constant.numeric.real.verilog",
"match": "[0-9]([0-9]|_)*(\\.[0-9]([0-9]|_)*((e|E)(-|\\+)?[0-9]([0-9]|_)*)?|(e|E)(-|\\+)?[0-9]([0-9]|_)*)"
},
{
"name": "constant.numeric.decimal_number.verilog",
"match": "[0-9]([0-9]|_)*"
},
{
"name": "constant.numeric.based_number.verilog",
"match": "\u0027(s|S)?((d|D)(((\\s| ||\\\t|\\\r)|\\\n))*(([0-9]|_)*|(x|X)_*|(z|Z|\\?)_*)|(h|H)(((\\s| ||\\\t|\\\r)|\\\n))*((x|X)|(z|Z|\\?)|[0-9]|[a-f]|[A-F]|_)*|(o|O)(((\\s| ||\\\t|\\\r)|\\\n))*((x|X)|(z|Z|\\?)|[0-7]|_)*|(b|B)(((\\s| ||\\\t|\\\r)|\\\n))*((x|X)|(z|Z|\\?)|[0-1]|_)*)"
},
{
"name": "string.quoted.double.verilog",
"match": "\\\"(\\\\.|\\\\\\\r\\\n|[^\\\\\\\n\\\r\\\"])*\\\""
},
{
"name": "string.quoted.double.verilog",
"match": "\\\"(\\\\.|\\\\\\\r\\\n|[^\\\\\\\n\\\r\\\"])*(\\\r\\\n|\\\r|\\\n|)"
},
{
"name": "comment.block.verilog",
"begin": "/\\*",
"end": "\\*/",
"patterns": []
},
{
"name": "comment.line.verilog",
"match": "//[^\\\n]*\\\n?"
}
]
}