spacecubics · sasataku · Aug 16, 2024 · Aug 16, 2024 · Aug 16, 2024 · Aug 16, 2024
@@ -5,9 +5,6 @@
 
 if BOARD_SCSAT1_ADCS
 
-config BOARD
-	default "scsat1_adcs"
-
 config CPU_CORTEX_M_HAS_SYSTICK
 	default y
 

@@ -1,8 +1,5 @@
-# SC-Sat1 ADCS Board configuration
-
 # Copyright (c) 2023 Space Cubics, LLC.
 # SPDX-License-Identifier: Apache-2.0
 
 config BOARD_SCSAT1_ADCS
-	bool "SC-Sat1 ADCS Board"
-	depends on SOC_SERIES_ARM_DESIGNSTART
+	select SOC_DESIGNSTART_FPGA_CORTEX_M3
@@ -0,0 +1,5 @@
+board:
+  name: scsat1_adcs
+  vendor: sc
+  socs:
+    - name: designstart_fpga_cortex_m3
@@ -1,8 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_SOC_SERIES_ARM_DESIGNSTART=y
-CONFIG_SOC_ARM_DESIGNSTART_FPGA_CORTEX_M3=y
-CONFIG_BOARD_SCSAT1_ADCS=y
 CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000
 CONFIG_ARM_MPU=n
 

@@ -5,9 +5,6 @@
 
 if BOARD_SCSAT1_MAIN
 
-config BOARD
-	default "scsat1_main"
-
 config CPU_CORTEX_M_HAS_SYSTICK
 	default y
 

@@ -1,8 +1,5 @@
-# SC-Sat1 MAIN Board configuration
-
 # Copyright (c) 2023 Space Cubics, LLC.
 # SPDX-License-Identifier: Apache-2.0
 
 config BOARD_SCSAT1_MAIN
-	bool "SC-Sat1 MAIN Board"
-	depends on SOC_SERIES_ARM_DESIGNSTART
+	select SOC_DESIGNSTART_FPGA_CORTEX_M3
@@ -0,0 +1,5 @@
+board:
+  name: scsat1_main
+  vendor: sc
+  socs:
+    - name: designstart_fpga_cortex_m3
@@ -1,8 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_SOC_SERIES_ARM_DESIGNSTART=y
-CONFIG_SOC_ARM_DESIGNSTART_FPGA_CORTEX_M3=y
-CONFIG_BOARD_SCSAT1_MAIN=y
 CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000
 CONFIG_ARM_MPU=n
 

@@ -3,7 +3,7 @@ manifest:
   projects:
     - name: zephyr
       url: https://github.com/zephyrproject-rtos/zephyr
-      revision: v3.6.0
+      revision: v3.7-branch
       path: zephyr
       west-commands: scripts/west-commands.yml
       import:

@@ -883,7 +883,7 @@ static void sc_can_set_state_change_callback(const struct device *dev,
 	data->common.state_change_cb_user_data = user_data;
 }
 
-#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY
+#ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE
 static int sc_can_recover(const struct device *dev, k_timeout_t timeout)
 {
 	const struct sc_can_cfg *config = dev->config;
@@ -1050,7 +1050,7 @@ static int sc_can_init(const struct device *dev)
 	uint32_t v;
 
 	/* Set timing according to dts default setting */
-	ret = can_calc_timing(dev, &timing, config->common.bus_speed, config->common.sample_point);
+	ret = can_calc_timing(dev, &timing, config->common.bitrate, config->common.sample_point);
 	if (ret == -EINVAL) {
 		LOG_ERR("Can't find timing for given param");
 		return -EIO;
@@ -1102,7 +1102,7 @@ static const struct can_driver_api sc_can_driver_api = {
 	.add_rx_filter = sc_can_add_rx_filter,
 	.remove_rx_filter = sc_can_remove_rx_filter,
 	.get_state = sc_can_get_state,
-#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY
+#ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE
 	.recover = sc_can_recover,
 #endif
 	.set_state_change_callback = sc_can_set_state_change_callback,
@@ -1153,7 +1153,7 @@ static const struct can_driver_api sc_can_driver_api = {
 	static struct sc_can_tx_cb_data tx_cb_data_list_##n[DT_INST_PROP(n, tx_fifo_depth)];       \
 	static struct sc_can_rx_filters rx_filters_##n[DT_INST_PROP(n, max_filter)];          \
 	static const struct sc_can_cfg sc_can_cfg_##n = {                                          \
-		.common = CAN_DT_DRIVER_CONFIG_INST_GET(n, 1000000),       \
+		.common = CAN_DT_DRIVER_CONFIG_INST_GET(n, 0, 1000000),                            \
 		.reg_addr = DT_INST_REG_ADDR(n),                                                   \
 		.irq_init = sc_can_##n##_irq_init,                                                 \
 		.clock_frequency = DT_INST_PROP(n, clock_frequency),                               \