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JSInth.qsf
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JSInth.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, the Altera Quartus II License Agreement,
# the Altera MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Altera and sold by Altera or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 14.1.0 Build 186 12/03/2014 SJ Web Edition
# Date created = 12:19:58 April 19, 2015
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# JSInth_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE115F29C7
set_global_assignment -name TOP_LEVEL_ENTITY JSInth
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 14.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:19:58 APRIL 19, 2015"
set_global_assignment -name LAST_QUARTUS_VERSION 14.1.0
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_location_assignment PIN_Y2 -to clk
set_location_assignment PIN_G13 -to horiz_sync
set_location_assignment PIN_F11 -to vga_blank
set_location_assignment PIN_C13 -to vert_sync
set_location_assignment PIN_D12 -to vga_blue[7]
set_location_assignment PIN_D11 -to vga_blue[6]
set_location_assignment PIN_C12 -to vga_blue[5]
set_location_assignment PIN_A11 -to vga_blue[4]
set_location_assignment PIN_B11 -to vga_blue[3]
set_location_assignment PIN_C11 -to vga_blue[2]
set_location_assignment PIN_A10 -to vga_blue[1]
set_location_assignment PIN_B10 -to vga_blue[0]
set_location_assignment PIN_A12 -to vga_clk
set_location_assignment PIN_C9 -to vga_green[7]
set_location_assignment PIN_F10 -to vga_green[6]
set_location_assignment PIN_B8 -to vga_green[5]
set_location_assignment PIN_C8 -to vga_green[4]
set_location_assignment PIN_H12 -to vga_green[3]
set_location_assignment PIN_F8 -to vga_green[2]
set_location_assignment PIN_G11 -to vga_green[1]
set_location_assignment PIN_G8 -to vga_green[0]
set_location_assignment PIN_H10 -to vga_red[7]
set_location_assignment PIN_H8 -to vga_red[6]
set_location_assignment PIN_J12 -to vga_red[5]
set_location_assignment PIN_G10 -to vga_red[4]
set_location_assignment PIN_F12 -to vga_red[3]
set_location_assignment PIN_D10 -to vga_red[2]
set_location_assignment PIN_E11 -to vga_red[1]
set_location_assignment PIN_E10 -to vga_red[0]
set_location_assignment PIN_Y24 -to keys[15]
set_location_assignment PIN_AA22 -to keys[14]
set_location_assignment PIN_AA23 -to keys[13]
set_location_assignment PIN_AA24 -to keys[12]
set_location_assignment PIN_AB23 -to keys[11]
set_location_assignment PIN_AB24 -to keys[10]
set_location_assignment PIN_AC24 -to keys[9]
set_location_assignment PIN_AB25 -to keys[8]
set_location_assignment PIN_AC25 -to keys[7]
set_location_assignment PIN_AB26 -to keys[6]
set_location_assignment PIN_AD26 -to keys[5]
set_location_assignment PIN_AC26 -to keys[4]
set_location_assignment PIN_AB27 -to keys[3]
set_location_assignment PIN_AD27 -to keys[2]
set_location_assignment PIN_AC27 -to keys[1]
set_location_assignment PIN_AC28 -to keys[0]
set_location_assignment PIN_AB28 -to mute_sel
set_location_assignment PIN_N21 -to vol_up
set_location_assignment PIN_R24 -to vol_down
set_location_assignment PIN_D2 -to AUD_ADCDAT
set_location_assignment PIN_C2 -to AUD_ADCLRCK
set_location_assignment PIN_F2 -to AUD_BCLK
set_location_assignment PIN_D1 -to AUD_DACDAT
set_location_assignment PIN_E3 -to AUD_DACLRCK
set_location_assignment PIN_E1 -to AUD_XCK
set_location_assignment PIN_B7 -to I2C_SCLK
set_location_assignment PIN_A8 -to I2C_SDAT
set_location_assignment PIN_M21 -to oct_sel
set_location_assignment PIN_M23 -to synth_sel
set_global_assignment -name VHDL_FILE typeDeclarations.vhd
set_global_assignment -name VHDL_FILE FIFO.vhd
set_global_assignment -name VHDL_FILE FSM_synth.vhd
set_global_assignment -name VHDL_FILE reverb_FIFO.vhd
set_global_assignment -name VHDL_FILE reverb_adder.vhd
set_global_assignment -name VHDL_FILE reverb.vhd
set_global_assignment -name VHDL_FILE constants.vhd
set_global_assignment -name VHDL_FILE AND16.vhd
set_global_assignment -name VHDL_FILE audioROM.vhd
set_global_assignment -name VHDL_FILE SampleAdder16.vhd
set_global_assignment -name VHDL_FILE WM8731_Controller.vhd
set_global_assignment -name VERILOG_FILE de2_i2c_controller.v
set_global_assignment -name VERILOG_FILE de2_i2c_av_config.v
set_global_assignment -name VHDL_FILE VGA_top_level.vhd
set_global_assignment -name VHDL_FILE vga_sync.vhd
set_global_assignment -name VHDL_FILE pixelGenerator.vhd
set_global_assignment -name VHDL_FILE colorROM.vhd
set_global_assignment -name VHDL_FILE JSInth.vhd
set_global_assignment -name VHDL_FILE FSM_volume.vhd
set_global_assignment -name VHDL_FILE FSM_octave.vhd
set_global_assignment -name VHDL_FILE SampleContainer.vhd
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top